From kgene.kim at samsung.com  Thu Mar  1 00:12:56 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 01 Mar 2012 14:12:56 +0900
Subject: [GIT PULL] merge PL330 DMAC driver
Message-ID: <077301ccf769$f6ac3750$e404a5f0$%kim@samsung.com>

Hi Russell and Vinod,

Please pull merging dma pl330 driver into drivers/dma/.
It's time to send this to you, and I think that should be sent to upstream
via rmk and dma tree together.

If any problems, please kindly let me know.

As a note, since there is no regarding samsung stuff here, I don't merge
this into samsung tree.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:

  Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)

are available in the git repository at:
  git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
v3.4-for-vkoul-v3

Boojin Kim (3):
      DMA: PL330: Merge PL330 driver into drivers/dma/
      DMA: PL330: Removes useless function
      DMA: PL330: Support MEMTOMEM transmit w/o RMB, WMB

 arch/arm/common/Kconfig               |    3 -
 arch/arm/common/Makefile              |    1 -
 arch/arm/common/pl330.c               | 1959
-------------------------------
 arch/arm/include/asm/hardware/pl330.h |  217 ----
 drivers/dma/Kconfig                   |    1 -
 drivers/dma/pl330.c                   | 2089
++++++++++++++++++++++++++++++++-
 include/linux/amba/pl330.h            |    1 -
 7 files changed, 2088 insertions(+), 2183 deletions(-)
 delete mode 100644 arch/arm/common/pl330.c
 delete mode 100644 arch/arm/include/asm/hardware/pl330.h



From jg1.han at samsung.com  Thu Mar  1 00:15:04 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Thu, 01 Mar 2012 14:15:04 +0900
Subject: [PATCH 1/2] ARM: EXYNOS: Add USB HOST register definitions
In-Reply-To: <4F4EED42.2010700@linaro.org>
References: <000101ccf6ef$f4efbab0$decf3010$%han@samsung.com>
 <4F4EED42.2010700@linaro.org>
Message-ID: <000601ccf76a$479d58b0$d6d80a10$%han@samsung.com>



> -----Original Message-----
> From: Tushar Behera [mailto:tushar.behera at linaro.org]
> Sent: Thursday, March 01, 2012 12:30 PM
> To: Jingoo Han
> Cc: linux-usb at vger.kernel.org; 'Greg Kroah-Hartman'; linux-samsung-soc at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; 'Sangwook Lee'; 'Alan Stern'; 'Joonyoung Shim'; 'Kukjin Kim';
> patches at linaro.org; linaro-dev at lists.linaro.org; 'Thomas Abraham'
> Subject: Re: [PATCH 1/2] ARM: EXYNOS: Add USB HOST register definitions
> 
> On 02/29/2012 08:09 PM, Jingoo Han wrote:
> > This patch adds USB HOST register definitions. The definition for
> > EHCI INSNREG00 regiser and corresponding bit field definitions are
> > added.
> >
> > Signed-off-by: Jingoo Han <jg1.han at samsung.com>
> > ---
> >  arch/arm/mach-exynos/include/mach/regs-usb-host.h |   23 +++++++++++++++++++++
> >  1 files changed, 23 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/mach-exynos/include/mach/regs-usb-host.h
> >
> > diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-host.h b/arch/arm/mach-
> exynos/include/mach/regs-usb-host.h
> > new file mode 100644
> > index 0000000..1a60f27
> > --- /dev/null
> > +++ b/arch/arm/mach-exynos/include/mach/regs-usb-host.h
> > @@ -0,0 +1,23 @@
> > +/*
> > + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> > + *		http://www.samsung.com
> > + *
> > + * EXYNOS - USB HOST register definitions
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#ifndef __REGS_USB_HOST_H
> > +#define __REGS_USB_HOST_H __FILE__
> > +
> > +#define EHCI_INSNREG00(base)		(base + 0x90)
> > +#define EHCI_ENA_INCR16			(0x1 << 25)
> > +#define EHCI_ENA_INCR8			(0x1 << 24)
> > +#define EHCI_ENA_INCR4			(0x1 << 23)
> > +#define EHCI_ENA_INCRX_ALIGN		(0x1 << 22)
> > +#define EHCI_ENABLE_DMA_INCR		(EHCI_ENA_INCR16 | EHCI_ENA_INCR8| \
> > +					 EHCI_ENA_INCR4 | EHCI_ENA_INCRX_ALIGN)
> > +
> As per the definition of bit-fields in other registers, it would be good
> to prepend the complete register name before the bit-field defines.
> 
> EHCI_INSNREG00_ENA_INCR16 ...
OK, I will change the definitions from EHCI_ENA_xxx to EHCI_INSNREG00_ENA_xxx.

> 
> Considering the similarity of this patchset with the earlier patchset
> from Sangwook, IMO, it would be appropriate to give him due credit in
> both these patches.
OK, I will give Sangwook Signed-off.

> > > +#endif /* __REGS_USB_HOST_H */
> 
> 
> --
> Tushar Behera



From rnayak at ti.com  Thu Mar  1 00:36:40 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 01 Mar 2012 11:06:40 +0530
Subject: [PATCH] ARM: OMAP2+: powerdomain: unwrap and simplify logging
 strings
In-Reply-To: <alpine.DEB.2.00.1202292122560.12752@utopia.booyaka.com>
References: <alpine.DEB.2.00.1202292122560.12752@utopia.booyaka.com>
Message-ID: <4F4F0AE8.40903@ti.com>

Hi Paul,

On Thursday 01 March 2012 09:53 AM, Paul Walmsley wrote:
>
> The current kernel doctrine is to not break printk() strings that
> cross the 80-column boundary into multiple strings.  This is intended
> to ease grepping.  This patch unwraps and simplifies many strings in
> the OMAP powerdomain implementation code, standardizing the format as
> it does so.

looks good to me. Thanks,
Acked-by: Rajendra Nayak <rnayak at ti.com>

>
> Signed-off-by: Paul Walmsley<paul at pwsan.com>
> Cc: Rajendra Nayak<rnayak at ti.com>
> ---
>   arch/arm/mach-omap2/powerdomain.c          |   30 ++++++++++++++--------------
>   arch/arm/mach-omap2/powerdomain2xxx_3xxx.c |    7 +++--
>   arch/arm/mach-omap2/powerdomain44xx.c      |    7 +++--
>   3 files changed, 23 insertions(+), 21 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
> index 8a18d1b..89000d3 100644
> --- a/arch/arm/mach-omap2/powerdomain.c
> +++ b/arch/arm/mach-omap2/powerdomain.c
> @@ -339,8 +339,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
>   	if (!pwrdm || !clkdm)
>   		return -EINVAL;
>
> -	pr_debug("powerdomain: associating clockdomain %s with powerdomain "
> -		 "%s\n", clkdm->name, pwrdm->name);
> +	pr_debug("powerdomain: %s: associating clockdomain %s\n",
> +		 clkdm->name, pwrdm->name);
>
>   	for (i = 0; i<  PWRDM_MAX_CLKDMS; i++) {
>   		if (!pwrdm->pwrdm_clkdms[i])
> @@ -354,8 +354,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
>   	}
>
>   	if (i == PWRDM_MAX_CLKDMS) {
> -		pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
> -			 "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
> +		pr_debug("powerdomain: %s: increase PWRDM_MAX_CLKDMS (%s)\n",
> +			 pwrdm->name, clkdm->name);
>   		WARN_ON(1);
>   		ret = -ENOMEM;
>   		goto pac_exit;
> @@ -387,16 +387,16 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
>   	if (!pwrdm || !clkdm)
>   		return -EINVAL;
>
> -	pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
> -		 "%s\n", clkdm->name, pwrdm->name);
> +	pr_debug("powerdomain: %s: dissociating clockdomain %s\n",
> +		 clkdm->name, pwrdm->name);
>
>   	for (i = 0; i<  PWRDM_MAX_CLKDMS; i++)
>   		if (pwrdm->pwrdm_clkdms[i] == clkdm)
>   			break;
>
>   	if (i == PWRDM_MAX_CLKDMS) {
> -		pr_debug("powerdomain: clkdm %s not associated with pwrdm "
> -			 "%s ?!\n", clkdm->name, pwrdm->name);
> +		pr_debug("powerdomain: %s: clkdm %s not associated ?!\n",
> +			 clkdm->name, pwrdm->name);
>   		ret = -ENOENT;
>   		goto pdc_exit;
>   	}
> @@ -485,7 +485,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
>   	if (!(pwrdm->pwrsts&  (1<<  pwrst)))
>   		return -EINVAL;
>
> -	pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
> +	pr_debug("powerdomain: %s: setting next powerstate to %0x\n",
>   		 pwrdm->name, pwrst);
>
>   	if (arch_pwrdm&&  arch_pwrdm->pwrdm_set_next_pwrst) {
> @@ -583,7 +583,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
>   	if (!(pwrdm->pwrsts_logic_ret&  (1<<  pwrst)))
>   		return -EINVAL;
>
> -	pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
> +	pr_debug("powerdomain: %s: setting next logic powerstate to %0x\n",
>   		 pwrdm->name, pwrst);
>
>   	if (arch_pwrdm&&  arch_pwrdm->pwrdm_set_logic_retst)
> @@ -620,8 +620,8 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
>   	if (!(pwrdm->pwrsts_mem_on[bank]&  (1<<  pwrst)))
>   		return -EINVAL;
>
> -	pr_debug("powerdomain: setting next memory powerstate for domain %s "
> -		 "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
> +	pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-%s to %0x\n",
> +		 pwrdm->name, bank, "ON", pwrst);
>
>   	if (arch_pwrdm&&  arch_pwrdm->pwrdm_set_mem_onst)
>   		ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
> @@ -658,8 +658,8 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
>   	if (!(pwrdm->pwrsts_mem_ret[bank]&  (1<<  pwrst)))
>   		return -EINVAL;
>
> -	pr_debug("powerdomain: setting next memory powerstate for domain %s "
> -		 "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
> +	pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-%s to %0x\n",
> +		 pwrdm->name, bank, "RET", pwrst);
>
>   	if (arch_pwrdm&&  arch_pwrdm->pwrdm_set_mem_retst)
>   		ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
> @@ -837,7 +837,7 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
>   	 * warn&  fail if it is not ON.
>   	 */
>
> -	pr_debug("powerdomain: clearing previous power state reg for %s\n",
> +	pr_debug("powerdomain: %s: clearing previous power state reg\n",
>   		 pwrdm->name);
>
>   	if (arch_pwrdm&&  arch_pwrdm->pwrdm_clear_all_prev_pwrst)
> diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
> index 6a17e4c..c2cb416 100644
> --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
> +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
> @@ -121,12 +121,13 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
>   			udelay(1);
>
>   	if (c>  PWRDM_TRANSITION_BAILOUT) {
> -		printk(KERN_ERR "powerdomain: waited too long for "
> -			"powerdomain %s to complete transition\n", pwrdm->name);
> +		pr_err("powerdomain: %s: waited too long to complete transition\n",
> +		       pwrdm->name);
>   		return -EAGAIN;
>   	}
>
> -	pr_debug("powerdomain: completed transition in %d loops\n", c);
> +	pr_debug("powerdomain: %s: completed transition in %d loops\n",
> +		 pwrdm->name, c);
>
>   	return 0;
>   }
> diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
> index a7880af..2db97a9 100644
> --- a/arch/arm/mach-omap2/powerdomain44xx.c
> +++ b/arch/arm/mach-omap2/powerdomain44xx.c
> @@ -197,12 +197,13 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
>   		udelay(1);
>
>   	if (c>  PWRDM_TRANSITION_BAILOUT) {
> -		printk(KERN_ERR "powerdomain: waited too long for "
> -		       "powerdomain %s to complete transition\n", pwrdm->name);
> +		pr_err("powerdomain: %s: waited too long to complete transition\n",
> +		       pwrdm->name);
>   		return -EAGAIN;
>   	}
>
> -	pr_debug("powerdomain: completed transition in %d loops\n", c);
> +	pr_debug("powerdomain: %s: completed transition in %d loops\n",
> +		 pwrdm->name, c);
>
>   	return 0;
>   }



From jassisinghbrar at gmail.com  Thu Mar  1 00:37:05 2012
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Thu, 1 Mar 2012 11:07:05 +0530
Subject: [GIT PULL] merge PL330 DMAC driver
In-Reply-To: <077301ccf769$f6ac3750$e404a5f0$%kim@samsung.com>
References: <077301ccf769$f6ac3750$e404a5f0$%kim@samsung.com>
Message-ID: <CABb+yY2hxuxMKsN0gHKwwoVtnHJ+z-gANtsMXA+tKsmk+MRzew@mail.gmail.com>

On Thu, Mar 1, 2012 at 10:42 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>
> Boojin Kim (3):
> ? ? ?DMA: PL330: Merge PL330 driver into drivers/dma/
>
You didn't check if upstream has moved since you first prepared your
patchset.
This patch doesn't account for
    ARM: 7326/2: PL330: fix null pointer dereference in pl330_chan_ctrl()
    ARM: 7164/3: PL330: Fix the size of the dst_cache_ctrl field

Btw, adding new copyright notice every year, rather than updating the existing
one isn't very cool. Other than that it looks ok finally.


> ? ? ?DMA: PL330: Removes useless function
> ? ? ?DMA: PL330: Support MEMTOMEM transmit w/o RMB, WMB
Look OK.
      Acked-by: Jassi Brar <jassisinghbrar at gmail.com>


From jg1.han at samsung.com  Thu Mar  1 00:38:20 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Thu, 01 Mar 2012 14:38:20 +0900
Subject: [PATCH v2 1/2] ARM: EXYNOS: Add USB HOST register definitions
Message-ID: <000701ccf76d$8316b0a0$894411e0$%han@samsung.com>

This patch adds USB HOST register definitions. The definition for
EHCI INSNREG00 regiser and corresponding bit field definitions are
added.

Signed-off-by: Sangwook Lee <sangwook.lee at linaro.org>
Signed-off-by: Jingoo Han <jg1.han at samsung.com>
---
v2: change the definition name from EHCI_ENA_xxx to EHCI_INSNREG00_ENA_xxx.

arch/arm/mach-exynos/include/mach/regs-usb-host.h |   24 +++++++++++++++++++++
 1 files changed, 24 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/include/mach/regs-usb-host.h

diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-host.h b/arch/arm/mach-exynos/include/mach/regs-usb-host.h
new file mode 100644
index 0000000..572b7d4
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-host.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *		http://www.samsung.com
+ *
+ * EXYNOS - USB HOST register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __REGS_USB_HOST_H
+#define __REGS_USB_HOST_H __FILE__
+
+#define EHCI_INSNREG00(base)			(base + 0x90)
+#define EHCI_INSNREG00_ENA_INCR16		(0x1 << 25)
+#define EHCI_INSNREG00_ENA_INCR8		(0x1 << 24)
+#define EHCI_INSNREG00_ENA_INCR4		(0x1 << 23)
+#define EHCI_INSNREG00_ENA_INCRX_ALIGN		(0x1 << 22)
+#define EHCI_INSNREG00_ENABLE_DMA_BURST	\
+	(EHCI_INSNREG00_ENA_INCR16 | EHCI_INSNREG00_ENA_INCR8 |	\
+	 EHCI_INSNREG00_ENA_INCR4 | EHCI_INSNREG00_ENA_INCRX_ALIGN)
+
+#endif /* __REGS_USB_HOST_H */
-- 
1.7.1




From jg1.han at samsung.com  Thu Mar  1 00:40:03 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Thu, 01 Mar 2012 14:40:03 +0900
Subject: [PATCH v2 2/2] USB: ehci-s5p: add DMA burst support
Message-ID: <000801ccf76d$c01e2a00$405a7e00$%han@samsung.com>

DMA burst support is added to improve performance in EHCI data
transfer. The USB EHCI controller on Exynos SoCs can use INCR16,
INCR8, and INCR4 mode. These modes of INSNREG00 register should
be set in order to enable DMA burst transfer. This feature is
also related to AHB spec.

Signed-off-by: Jingoo Han <jg1.han at samsung.com>
Cc: Sangwook Lee <sangwook.lee at linaro.org>
---
v2: change the definition name from EHCI_ENA_xxx to EHCI_INSNREG00_ENA_xxx.

drivers/usb/host/ehci-s5p.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 293f741..b337f72 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <plat/ehci.h>
 #include <plat/usb-phy.h>
+#include <mach/regs-usb-host.h>
 
 struct s5p_ehci_hcd {
 	struct device *dev;
@@ -128,6 +129,9 @@ static int __devinit s5p_ehci_probe(struct platform_device *pdev)
 	ehci->regs = hcd->regs +
 		HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
 
+	/* DMA burst Enable */
+	writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
+
 	dbg_hcs_params(ehci, "reset");
 	dbg_hcc_params(ehci, "reset");
 
@@ -234,6 +238,9 @@ static int s5p_ehci_resume(struct device *dev)
 	if (pdata && pdata->phy_init)
 		pdata->phy_init(pdev, S5P_USB_PHY_HOST);
 
+	/* DMA burst Enable */
+	writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
+
 	if (time_before(jiffies, ehci->next_statechange))
 		msleep(100);
 
-- 
1.7.1




From sfr at canb.auug.org.au  Thu Mar  1 00:40:01 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 1 Mar 2012 16:40:01 +1100
Subject: linux-next: manual merge of the arm-soc tree with the gpio tree
Message-ID: <20120301164001.77a063ceed2deaf37cf68e3c@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got conflicts in
arch/arm/mach-omap1/gpio16xx.c between commit ab985f0f7c2c ("gpio/omap:
cleanup omap_gpio_mod_init function") from the gpio tree and commit
63325ff235de ("ARM: OMAP1: Move 16xx GPIO system clock to platform init
code") from the arm-soc tree.

OK, I can't decide which is correct here - the former adds this code
inside the loop (even though it seems to not depend on anything in the
loop) and the latter adds it before.  I have used the former (but am
happy to be corrected).  And both commits remove the code in
drivers/gpio/gpio-omap.c.

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From rnayak at ti.com  Thu Mar  1 00:40:40 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 01 Mar 2012 11:10:40 +0530
Subject: [PATCH 0/4] twl-regulator DT adaptation and updates to add new
 regulators
In-Reply-To: <20120229231818.GA8295@opensource.wolfsonmicro.com>
References: <1330421953-29517-1-git-send-email-rnayak@ti.com>
 <20120229231818.GA8295@opensource.wolfsonmicro.com>
Message-ID: <4F4F0BD8.7090506@ti.com>

On Thursday 01 March 2012 04:48 AM, Mark Brown wrote:
> On Tue, Feb 28, 2012 at 03:09:09PM +0530, Rajendra Nayak wrote:
>> Hi Mark,
>>
>> Here is a consolidated series which adds DT support for twl regulator
>> driver and adds support for VDD1/2/3 regulator and support for
>> fixed LDO V1V8 and V2V1. The patches are based on -next and tested
>> on omap3 beagle and omap4 panda boards.
>
> Applied all, thanks.  Please do try to use subject lines consistent with
> the subsystem.

Thanks Mark, will remember to keep the subject lines consistent
hence forth.


From haojian.zhuang at marvell.com  Thu Mar  1 01:10:21 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Thu,  1 Mar 2012 14:10:21 +0800
Subject: [PATCH 1/8] gpio: pxa: add OF support
In-Reply-To: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330582228-12424-2-git-send-email-haojian.zhuang@marvell.com>

gpio-pxa drivers needs to parse two properties: mrvl,gpio-irq0 and
mrvl,gpio-irq1.

There may be 3 irqs in gpio devices in arch-pxa. The first one may
be only for gpio0, the second on may be only for gpio1, and the last
one may be the irq mux for other gpios. In arch-mmp, there's only
one irq mux for all gpios.

Since irq mux is common, we only specify it in interrupts propery.
And we creates two properties mrvl,gpio-irq0 and mrvl,gpio-irq1 for
arch-pxa.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/gpio/gpio-pxa.c |   40 +++++++++++++++++++++++++++++++++++++---
 1 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index b2d3ee1..7d8e1d0 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
@@ -464,6 +465,39 @@ static int pxa_gpio_nums(void)
 	return count;
 }
 
+#ifdef CONFIG_OF
+static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev,
+				       int *irq0, int *irq1, int *irq_mux)
+{
+	struct device_node *np = pdev->dev.of_node;
+	const __be32 *irq;
+
+	irq = of_get_property(np, "mrvl,gpio-irq0", NULL);
+	if (irq)
+		*irq0 = be32_to_cpup(irq);
+	irq = of_get_property(np, "mrvl,gpio-irq1", NULL);
+	if (irq)
+		*irq1 = be32_to_cpup(irq);
+	*irq_mux = platform_get_irq(pdev, 0);
+	return 0;
+}
+#else
+static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev,
+				       int *irq0, int *irq1, int *irq_mux)
+{
+	return 1;
+}
+#endif
+
+static int __devinit pxa_gpio_probe_irq(struct platform_device *pdev,
+					int *irq0, int *irq1, int *irq_mux)
+{
+	*irq0 = platform_get_irq_byname(pdev, "gpio0");
+	*irq1 = platform_get_irq_byname(pdev, "gpio1");
+	*irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
+	return 0;
+}
+
 static int __devinit pxa_gpio_probe(struct platform_device *pdev)
 {
 	struct pxa_gpio_chip *c;
@@ -476,9 +510,9 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
 	if (!pxa_last_gpio)
 		return -EINVAL;
 
-	irq0 = platform_get_irq_byname(pdev, "gpio0");
-	irq1 = platform_get_irq_byname(pdev, "gpio1");
-	irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
+	ret = pxa_gpio_probe_dt(pdev, &irq0, &irq1, &irq_mux);
+	if (ret > 0)
+		ret = pxa_gpio_probe_irq(pdev, &irq0, &irq1, &irq_mux);
 	if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
 		|| (irq_mux <= 0))
 		return -EINVAL;
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Thu Mar  1 01:10:22 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Thu,  1 Mar 2012 14:10:22 +0800
Subject: [PATCH 2/8] serial: pxa: add OF support
In-Reply-To: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330582228-12424-3-git-send-email-haojian.zhuang@marvell.com>

Parse uart device id from alias in DTS file.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/tty/serial/pxa.c |   57 ++++++++++++++++++++++++++++++++++++---------
 1 files changed, 45 insertions(+), 12 deletions(-)

diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
index 5c8e3bb..380f15f 100644
--- a/drivers/tty/serial/pxa.c
+++ b/drivers/tty/serial/pxa.c
@@ -36,6 +36,7 @@
 #include <linux/circ_buf.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
@@ -781,6 +782,39 @@ static const struct dev_pm_ops serial_pxa_pm_ops = {
 };
 #endif
 
+static struct of_device_id serial_pxa_dt_ids[] = {
+	{ .compatible = "mrvl,pxa-uart", },
+	{ .compatible = "mrvl,mmp-uart", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids);
+
+#ifdef CONFIG_OF
+static int serial_pxa_probe_dt(struct platform_device *pdev,
+			       struct uart_pxa_port *sport)
+{
+	struct device_node *np = pdev->dev.of_node;
+	int ret;
+
+	if (!np)
+		return 1;
+
+	ret = of_alias_get_id(np, "serial");
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+		return ret;
+	}
+	sport->port.line = ret;
+	return 0;
+}
+#else
+static int serial_pxa_probe_dt(struct platform_device *pdev,
+			       struct uart_pxa_port *sport)
+{
+	return 1;
+}
+#endif
+
 static int serial_pxa_probe(struct platform_device *dev)
 {
 	struct uart_pxa_port *sport;
@@ -792,7 +826,7 @@ static int serial_pxa_probe(struct platform_device *dev)
 	if (!mmres || !irqres)
 		return -ENODEV;
 
-	sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
+	sport = kzalloc(sizeof(struct uart_pxa_port) + 8, GFP_KERNEL);
 	if (!sport)
 		return -ENOMEM;
 
@@ -808,20 +842,18 @@ static int serial_pxa_probe(struct platform_device *dev)
 	sport->port.irq = irqres->start;
 	sport->port.fifosize = 64;
 	sport->port.ops = &serial_pxa_pops;
-	sport->port.line = dev->id;
 	sport->port.dev = &dev->dev;
 	sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
 	sport->port.uartclk = clk_get_rate(sport->clk);
 
-	switch (dev->id) {
-	case 0: sport->name = "FFUART"; break;
-	case 1: sport->name = "BTUART"; break;
-	case 2: sport->name = "STUART"; break;
-	case 3: sport->name = "HWUART"; break;
-	default:
-		sport->name = "???";
-		break;
-	}
+	ret = serial_pxa_probe_dt(dev, sport);
+	if (ret > 0)
+		sport->port.line = dev->id;
+	else if (ret < 0)
+		goto err_clk;
+	sport->name = (char *)((unsigned int)sport + 8);
+	/* name can't exceed 8 bytes */
+	sprintf(sport->name, "UART%d", sport->port.line + 1);
 
 	sport->port.membase = ioremap(mmres->start, resource_size(mmres));
 	if (!sport->port.membase) {
@@ -829,7 +861,7 @@ static int serial_pxa_probe(struct platform_device *dev)
 		goto err_clk;
 	}
 
-	serial_pxa_ports[dev->id] = sport;
+	serial_pxa_ports[sport->port.line] = sport;
 
 	uart_add_one_port(&serial_pxa_reg, &sport->port);
 	platform_set_drvdata(dev, sport);
@@ -866,6 +898,7 @@ static struct platform_driver serial_pxa_driver = {
 #ifdef CONFIG_PM
 		.pm	= &serial_pxa_pm_ops,
 #endif
+		.of_match_table = serial_pxa_dt_ids,
 	},
 };
 
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Thu Mar  1 01:10:20 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Thu,  1 Mar 2012 14:10:20 +0800
Subject: [PATCH 0/8] ARM: mmp: support OF on pxa168
Message-ID: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>

Add OF support on gpio/serial/rtc/i2c components in pxa168 aspenite.



From haojian.zhuang at marvell.com  Thu Mar  1 01:10:23 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Thu,  1 Mar 2012 14:10:23 +0800
Subject: [PATCH 3/8] rtc: sa1100: add OF support
In-Reply-To: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330582228-12424-4-git-send-email-haojian.zhuang@marvell.com>

There're two interrupts are used in rtc-sa1100 devices. The RTC-alarm
interrupt is specified as default interrupt. The RTC-1Hz interrupt is
specified as "mrvl,rtc-irqhz" property in DTS file.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/rtc/rtc-sa1100.c |   54 +++++++++++++++++++++++++++++++++++++++------
 1 files changed, 46 insertions(+), 8 deletions(-)

diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index 962510c..09f05d5 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -30,6 +30,7 @@
 #include <linux/interrupt.h>
 #include <linux/slab.h>
 #include <linux/string.h>
+#include <linux/of.h>
 #include <linux/pm.h>
 #include <linux/bitops.h>
 
@@ -228,28 +229,64 @@ static const struct rtc_class_ops sa1100_rtc_ops = {
 	.alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
 };
 
+static struct of_device_id sa1100_rtc_dt_ids[] = {
+	{ .compatible = "mrvl,sa1100-rtc", },
+	{ .compatible = "mrvl,mmp-rtc", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids);
+
+#ifdef CONFIG_OF
+static int sa1100_rtc_probe_dt(struct platform_device *pdev,
+			       struct sa1100_rtc *info)
+{
+	info->irq_alarm = platform_get_irq(pdev, 0);
+	info->irq_1hz = platform_get_irq(pdev, 1);
+	if (info->irq_1hz < 0 || info->irq_alarm < 0)
+		return -ENODEV;
+	return 0;
+}
+#else
+static int sa1100_rtc_probe_dt(struct platform_device *pdev,
+			       struct sa1100_rtc *info)
+{
+	return 1;
+}
+#endif
+
+static int sa1100_rtc_probe_irq(struct platform_device *pdev,
+				struct sa1100_rtc *info)
+{
+	info->irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz");
+	info->irq_alarm = platform_get_irq_byname(pdev, "rtc alarm");
+	if (info->irq_1hz < 0 || info->irq_alarm < 0)
+		return -ENODEV;
+	return 0;
+}
+
 static int sa1100_rtc_probe(struct platform_device *pdev)
 {
 	struct rtc_device *rtc;
 	struct sa1100_rtc *info;
-	int irq_1hz, irq_alarm, ret = 0;
-
-	irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz");
-	irq_alarm = platform_get_irq_byname(pdev, "rtc alarm");
-	if (irq_1hz < 0 || irq_alarm < 0)
-		return -ENODEV;
+	int ret = 0;
 
 	info = kzalloc(sizeof(struct sa1100_rtc), GFP_KERNEL);
 	if (!info)
 		return -ENOMEM;
+	ret = sa1100_rtc_probe_dt(pdev, info);
+	if (ret > 0)
+		ret = sa1100_rtc_probe_irq(pdev, info);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get rtc irq\n");
+		goto err_clk;
+	}
+
 	info->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(info->clk)) {
 		dev_err(&pdev->dev, "failed to find rtc clock source\n");
 		ret = PTR_ERR(info->clk);
 		goto err_clk;
 	}
-	info->irq_1hz = irq_1hz;
-	info->irq_alarm = irq_alarm;
 	spin_lock_init(&info->lock);
 	platform_set_drvdata(pdev, info);
 
@@ -357,6 +394,7 @@ static struct platform_driver sa1100_rtc_driver = {
 #ifdef CONFIG_PM
 		.pm	= &sa1100_rtc_pm_ops,
 #endif
+		.of_match_table = sa1100_rtc_dt_ids,
 	},
 };
 
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Thu Mar  1 01:10:26 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Thu,  1 Mar 2012 14:10:26 +0800
Subject: [PATCH 6/8] ARM: mmp: append OF support on pxa168
In-Reply-To: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330582228-12424-7-git-send-email-haojian.zhuang@marvell.com>

Enable PXA168 and aspenite support.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/mach-mmp/Kconfig  |   10 ++++++
 arch/arm/mach-mmp/Makefile |    1 +
 arch/arm/mach-mmp/mmp-dt.c |   75 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 86 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-mmp/mmp-dt.c

diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 323d4c9..5a90b9a 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -2,6 +2,16 @@ if ARCH_MMP
 
 menu "Marvell PXA168/910/MMP2 Implmentations"
 
+config MACH_MMP_DT
+	bool "Support MMP2 platforms from device tree"
+	select CPU_PXA168
+	select CPU_PXA910
+	select USE_OF
+	help
+	  Include support for Marvell MMP2 based platforms using
+	  the device tree. Needn't select any other machine while
+	  MACH_MMP_DT is enabled.
+
 config MACH_ASPENITE
 	bool "Marvell's PXA168 Aspenite Development Board"
 	select CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index ba254a7..4fc0ff5 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_MACH_TTC_DKB)	+= ttc_dkb.o
 obj-$(CONFIG_MACH_BROWNSTONE)	+= brownstone.o
 obj-$(CONFIG_MACH_FLINT)	+= flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
+obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o
 obj-$(CONFIG_MACH_TETON_BGA)	+= teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)	+= gplugd.o
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
new file mode 100644
index 0000000..6707539
--- /dev/null
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -0,0 +1,75 @@
+/*
+ *  linux/arch/arm/mach-mmp/mmp-dt.c
+ *
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+extern struct sys_timer pxa168_timer;
+extern void __init icu_init_irq(void);
+
+static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+	{}
+};
+
+static int __init mmp_intc_add_irq_domain(struct device_node *np,
+					   struct device_node *parent)
+{
+	irq_domain_add_simple(np, 0);
+	return 0;
+}
+
+static int __init mmp_gpio_add_irq_domain(struct device_node *np,
+					   struct device_node *parent)
+{
+	irq_domain_add_simple(np, IRQ_GPIO_START);
+	return 0;
+}
+
+static const struct of_device_id mmp_irq_match[] __initconst = {
+	{ .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
+	{ .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
+	{}
+};
+
+static void __init mmp_dt_init(void)
+{
+
+	of_irq_init(mmp_irq_match);
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     mmp_auxdata_lookup, NULL);
+}
+
+static const char *pxa168_dt_board_compat[] __initdata = {
+	"mrvl,pxa168-aspenite",
+	NULL,
+};
+
+DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
+	.map_io		= mmp_map_io,
+	.init_irq	= icu_init_irq,
+	.timer		= &pxa168_timer,
+	.init_machine	= mmp_dt_init,
+	.dt_compat	= pxa168_dt_board_compat,
+MACHINE_END
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Thu Mar  1 01:10:24 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Thu,  1 Mar 2012 14:10:24 +0800
Subject: [PATCH 4/8] i2c: pxa: add OF support
In-Reply-To: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330582228-12424-5-git-send-email-haojian.zhuang@marvell.com>

Append these properties in below.
mrvl,i2c-polling
mrvl,i2c-mode

Still keep slave, slave_addr and class in platform data.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/i2c/busses/i2c-pxa.c |  101 ++++++++++++++++++++++++++++++++---------
 1 files changed, 79 insertions(+), 22 deletions(-)

diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index d603646..883d14f 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -29,6 +29,8 @@
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/i2c-pxa.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/of_i2c.h>
 #include <linux/platform_device.h>
 #include <linux/err.h>
@@ -1044,23 +1046,64 @@ static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
 	.functionality	= i2c_pxa_functionality,
 };
 
-static int i2c_pxa_probe(struct platform_device *dev)
+static struct of_device_id i2c_pxa_dt_ids[] = {
+	{ .compatible = "mrvl,pxa-i2c", .data = &pxa_reg_layout[REGS_PXA2XX] },
+	{ .compatible = "mrvl,pwri2c", .data = &pxa_reg_layout[REGS_PXA3XX] },
+	{ .compatible = "mrvl,mmp-twsi", .data = &pxa_reg_layout[REGS_PXA2XX] },
+	{}
+};
+MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
+
+#ifdef CONFIG_OF
+static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
+			    enum pxa_i2c_types *i2c_types)
 {
-	struct pxa_i2c *i2c;
-	struct resource *res;
-	struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
-	const struct platform_device_id *id = platform_get_device_id(dev);
-	enum pxa_i2c_types i2c_type = id->driver_data;
-	int ret;
-	int irq;
+	struct device_node *np = pdev->dev.of_node;
+	const struct of_device_id *of_id =
+			of_match_device(i2c_pxa_dt_ids, &pdev->dev);
+	const char *status;
+	int len;
+
+	if (of_get_property(np, "mrvl,i2c-polling", NULL))
+		i2c->use_pio = 1;
+	status = of_get_property(np, "mrvl,i2c-mode", &len);
+	if (status && len > 0)
+		if (!strcmp(status, "fast"))
+			i2c->fast_mode = 1;
+	*i2c_types = ((u32)(of_id->data) - (u32)&pxa_reg_layout[0])
+			/ sizeof(struct pxa_reg_layout);
+	return 0;
+}
+#else
+static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
+			    enum pxa_i2c_types *i2c_types)
+{
+	return 1;
+}
+#endif
 
-	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-	irq = platform_get_irq(dev, 0);
-	if (res == NULL || irq < 0)
-		return -ENODEV;
+static int i2c_pxa_probe_pdata(struct platform_device *pdev,
+			       struct pxa_i2c *i2c,
+			       enum pxa_i2c_types *i2c_types)
+{
+	struct i2c_pxa_platform_data *plat = pdev->dev.platform_data;
+	const struct platform_device_id *id = platform_get_device_id(pdev);
 
-	if (!request_mem_region(res->start, resource_size(res), res->name))
-		return -ENOMEM;
+	*i2c_types = id->driver_data;
+	if (plat) {
+		i2c->use_pio = plat->use_pio;
+		i2c->fast_mode = plat->fast_mode;
+	}
+	return 0;
+}
+
+static int i2c_pxa_probe(struct platform_device *dev)
+{
+	struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
+	enum pxa_i2c_types i2c_type;
+	struct pxa_i2c *i2c;
+	struct resource *res = NULL;
+	int ret, irq;
 
 	i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
 	if (!i2c) {
@@ -1068,6 +1111,24 @@ static int i2c_pxa_probe(struct platform_device *dev)
 		goto emalloc;
 	}
 
+	ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
+	if (ret > 0)
+		ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
+	if (ret < 0)
+		goto eclk;
+
+	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(dev, 0);
+	if (res == NULL || irq < 0) {
+		ret = -ENODEV;
+		goto eclk;
+	}
+
+	if (!request_mem_region(res->start, resource_size(res), res->name)) {
+		ret = -ENOMEM;
+		goto eclk;
+	}
+
 	i2c->adap.owner   = THIS_MODULE;
 	i2c->adap.retries = 5;
 
@@ -1109,21 +1170,16 @@ static int i2c_pxa_probe(struct platform_device *dev)
 
 	i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
 
-#ifdef CONFIG_I2C_PXA_SLAVE
 	if (plat) {
+#ifdef CONFIG_I2C_PXA_SLAVE
 		i2c->slave_addr = plat->slave_addr;
 		i2c->slave = plat->slave;
-	}
 #endif
-
-	clk_enable(i2c->clk);
-
-	if (plat) {
 		i2c->adap.class = plat->class;
-		i2c->use_pio = plat->use_pio;
-		i2c->fast_mode = plat->fast_mode;
 	}
 
+	clk_enable(i2c->clk);
+
 	if (i2c->use_pio) {
 		i2c->adap.algo = &i2c_pxa_pio_algorithm;
 	} else {
@@ -1234,6 +1290,7 @@ static struct platform_driver i2c_pxa_driver = {
 		.name	= "pxa2xx-i2c",
 		.owner	= THIS_MODULE,
 		.pm	= I2C_PXA_DEV_PM_OPS,
+		.of_match_table = i2c_pxa_dt_ids,
 	},
 	.id_table	= i2c_pxa_id_table,
 };
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Thu Mar  1 01:10:25 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Thu,  1 Mar 2012 14:10:25 +0800
Subject: [PATCH 5/8] ARM: mmp: enable rtc clk in pxa168
In-Reply-To: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330582228-12424-6-git-send-email-haojian.zhuang@marvell.com>

Enable clk of rtc-sa1100 device in pxa168.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/mach-mmp/pxa168.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 9f61256..aa62d0c 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -65,6 +65,7 @@ static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
 static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
 static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
+static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
 
 static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(lcd, LCD, 0x7f, 312000000);
@@ -93,6 +94,7 @@ static struct clk_lookup pxa168_clkregs[] = {
 	INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
 	INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
 	INIT_CLKREG(&clk_usb, "pxa168-ehci", "PXA168-USBCLK"),
+	INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
 };
 
 static int __init pxa168_init(void)
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Thu Mar  1 01:10:27 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Thu,  1 Mar 2012 14:10:27 +0800
Subject: [PATCH 7/8] ARM: dts: append DTS file of pxa168
In-Reply-To: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330582228-12424-8-git-send-email-haojian.zhuang@marvell.com>

DTS files of both PXA168 and aspenite are appended.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/boot/dts/pxa168-aspenite.dts |   38 +++++++++++++
 arch/arm/boot/dts/pxa168.dtsi         |   96 +++++++++++++++++++++++++++++++++
 2 files changed, 134 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/pxa168-aspenite.dts
 create mode 100644 arch/arm/boot/dts/pxa168.dtsi

diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
new file mode 100644
index 0000000..e762fac
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168-aspenite.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "pxa168.dtsi"
+
+/ {
+	model = "Marvell PXA168 Aspenite Development Board";
+	compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+	};
+
+	memory {
+		reg = <0x00000000 0x04000000>;
+	};
+
+	soc {
+		apb at d4000000 {
+			uart1: uart at d4017000 {
+				status = "okay";
+			};
+			twsi1: i2c at d4011000 {
+				status = "okay";
+			};
+			rtc: rtc at d4010000 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
new file mode 100644
index 0000000..e624c10
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -0,0 +1,96 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+	};
+
+	intc: intc-interrupt-controller at d4282000 {
+		compatible = "mrvl,mmp-intc", "mrvl,intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0xd4282000 0x1000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		apb at d4000000 {	/* APB */
+			compatible = "mrvl,apb-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4000000 0x00200000>;
+			ranges;
+
+			uart1: uart at d4017000 {
+				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				reg = <0xd4017000 0x1000>;
+				interrupts = <27>;
+				status = "disabled";
+			};
+
+			uart2: uart at d4018000 {
+				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				reg = <0xd4018000 0x1000>;
+				interrupts = <28>;
+				status = "disabled";
+			};
+
+			uart3: uart at d4026000 {
+				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				reg = <0xd4026000 0x1000>;
+				interrupts = <29>;
+				status = "disabled";
+			};
+
+			gpio: gpio at d4019000 {
+				compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+				reg = <0xd4019000 0x1000>;
+				interrupts = <49>;
+				gpio-controller;
+				#gpio-cells = <1>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				mrvl,gpio-irq0 = <17>;
+				mrvl,gpio-irq1 = <18>;
+			};
+
+			twsi1: i2c at d4011000 {
+				compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+				reg = <0xd4011000 0x1000>;
+				interrupts = <7>;
+				mrvl,i2c-mode = "fast";
+				status = "disabled";
+			};
+
+			twsi2: i2c at d4025000 {
+				compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+				reg = <0xd4025000 0x1000>;
+				interrupts = <58>;
+				status = "disabled";
+			};
+
+			rtc: rtc at d4010000 {
+				compatible = "mrvl,mmp-rtc";
+				reg = <0xd4010000 0x1000>;
+				interrupts = <6 5>;
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Thu Mar  1 01:10:28 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Thu,  1 Mar 2012 14:10:28 +0800
Subject: [PATCH 8/8] Document: devicetree: add OF documents for arch-mmp
In-Reply-To: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330582228-12424-9-git-send-email-haojian.zhuang@marvell.com>

Add OF support in Document/devicetree directory.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 Documentation/devicetree/bindings/arm/mrvl.txt     |    6 +++
 .../devicetree/bindings/gpio/mrvl-gpio.txt         |   27 ++++++++++++++
 Documentation/devicetree/bindings/i2c/mrvl-i2c.txt |   37 ++++++++++++++++++++
 .../devicetree/bindings/rtc/sa1100-rtc.txt         |   15 ++++++++
 4 files changed, 85 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
 create mode 100644 Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/sa1100-rtc.txt

diff --git a/Documentation/devicetree/bindings/arm/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl.txt
new file mode 100644
index 0000000..d8de933
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl.txt
@@ -0,0 +1,6 @@
+Marvell Platforms Device Tree Bindings
+----------------------------------------------------
+
+PXA168 Aspenite Board
+Required root node properties:
+	- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
new file mode 100644
index 0000000..c2c7995
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
@@ -0,0 +1,27 @@
+* Marvell PXA GPIO controller
+
+Required properties:
+- compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
+- reg : Address and length of the register set for the device
+- interrupts : Should be the port interrupt shared by all gpio pins, if
+  one number.
+- gpio-controller : Marks the device node as a gpio controller.
+- #gpio-cells : Should be one.  It is the pin number.
+
+Recommended properties:
+- mrvl,gpio-irq0: Should be interrupt number of gpio0 in pxa2xx/pxa3xx/pxa95x.
+- mrvl,gpio-irq1: should be interrupt number of gpio1 in pxa2xx/pxa3xx/pxa95x.
+
+Example:
+
+	gpio: gpio at d4019000 {
+		compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+		reg = <0xd4019000 0x1000>;
+		interrupts = <49>;
+		gpio-controller;
+		#gpio-cells = <1>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		mrvl,gpio-irq0 = <17>;
+		mrvl,gpio-irq1 = <18>;
+	};
diff --git a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
new file mode 100644
index 0000000..699c7ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
@@ -0,0 +1,37 @@
+* I2C
+
+Required properties :
+
+ - reg : Offset and length of the register set for the device
+ - compatible : should be "mrvl,mmp-twsi" where CHIP is the name of a
+   compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
+   For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
+   as shown in the example below.
+
+Recommended properties :
+
+ - interrupts : <a b> where a is the interrupt number and b is a
+   field that represents an encoding of the sense and level
+   information for the interrupt.  This should be encoded based on
+   the information in section 2) depending on the type of interrupt
+   controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+   services interrupts for this device.
+ - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
+   status register of i2c controller instead.
+ - mrvl,i2c-mode : "fast" means fast mode of i2c controller.
+
+Examples:
+	twsi1: i2c at d4011000 {
+		compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+		reg = <0xd4011000 0x1000>;
+		interrupts = <7>;
+		mrvl,i2c-mode = "fast";
+	};
+	
+	twsi2: i2c at d4025000 {
+		compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+		reg = <0xd4025000 0x1000>;
+		interrupts = <58>;
+	};
+
diff --git a/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt b/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
new file mode 100644
index 0000000..f3a0118
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
@@ -0,0 +1,15 @@
+* Marvell Real Time Clock controller
+
+Required properties:
+- compatible: should be "mrvl,sa1100-rtc"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: Should be two. The first interrupt number is the rtc alarm
+  interrupt and the second interrupt number is the rtc hz interrupt.
+
+Example:
+	rtc: rtc at d4010000 {
+		compatible = "mrvl,mmp-rtc";
+		reg = <0xd4010000 0x1000>;
+		interrupts = <6 5>;
+	};
-- 
1.7.0.4



From hvaibhav at ti.com  Thu Mar  1 01:19:41 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Thu, 1 Mar 2012 06:19:41 +0000
Subject: [PATCH-V1] arm/dts: Add support for TI OMAP3 EVM board
In-Reply-To: <4F4EA91F.1030305@ti.com>
References: <1324019153-13316-1-git-send-email-hvaibhav@ti.com>
 <79CD15C6BA57404B839C016229A409A80719AC@DBDE01.ent.ti.com>
 <20120229223114.GS18901@atomide.com> <4F4EA91F.1030305@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A8317E4B6B@DBDE01.ent.ti.com>

On Thu, Mar 01, 2012 at 04:09:27, Cousson, Benoit wrote:
> On 2/29/2012 11:31 PM, Tony Lindgren wrote:
> > * Hiremath, Vaibhav<hvaibhav at ti.com>  [120105 02:46]:
> ...
> >> Can this merged? OR anybody has any comments here?
> >
> > For reference, looks like this one is queued up as
> > commit f0e15e2b0c6b3e89daade25a1e9a2d80136c14c3.
> 
> Yes, it is, I included it in my DTS pull-request because it was the only 
> one with Grant's ack.
> 
> I have the whole series ready to be pulled but was waiting for DT 
> maintainers acked-by.
> 
> I still have these four ones in my branch.
> 
> d5c9442 arm/dts: Add support for TI AM3517/05 EVM board
> 3b5fa9a arm/dts: omap3-evm: Add i2c and twl4030 support
> 7f4ca5f arm/dts: Add support for TI AM335x EVM board
> d0c3aca ARM: OMAP2+: board-generic: Add DT support for AM33xx devices
> 
> In fact the board one already has the proper ack, only the DTS are 
> missing it.
> 

Ping to Grant !!!

Thanks,
Vaibhav


> Regards,
> Benoit
> 



From shawn.guo at linaro.org  Thu Mar  1 02:00:36 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 1 Mar 2012 15:00:36 +0800
Subject: [PATCH] Add devicetree support for i.MX27 SoCs
In-Reply-To: <1330503654-2197-1-git-send-email-s.hauer@pengutronix.de>
References: <1330503654-2197-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120301070034.GA2268@S2101-09.ap.freescale.net>

On Wed, Feb 29, 2012 at 09:20:51AM +0100, Sascha Hauer wrote:
> Hi all,
> 
> I created the following mainly out of curiosity to find out what's
> missing to support a new i.MX SoC in the devicetree. It turned out
> it's not much thanks to the driver bindings which already exist for
> the bigger i.MXes. So here it is.
> 
> Sascha
> 
> Sascha Hauer (3):
>       ARM i.MX27: Add devicetree support
>       ARM i.MX: Add phytec phycore-i.MX27 (aka pcm038) devicetree support
>       devicetree-bindings: Add documentation for i.MX generic boards

For the series,

Acked-by: Shawn Guo <shawn.guo at linaro.org>

Regards,
Shawn

> 
>  Documentation/devicetree/bindings/arm/fsl.txt |   22 +++
>  arch/arm/boot/dts/imx27-phytec-phycore.dts    |   76 +++++++++
>  arch/arm/boot/dts/imx27.dtsi                  |  217 +++++++++++++++++++++++++
>  arch/arm/mach-imx/Kconfig                     |    8 +
>  arch/arm/mach-imx/Makefile                    |    1 +
>  arch/arm/mach-imx/clock-imx27.c               |   18 ++
>  arch/arm/mach-imx/imx27-dt.c                  |   89 ++++++++++
>  arch/arm/plat-mxc/include/mach/common.h       |    1 +
>  8 files changed, 432 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/imx27-phytec-phycore.dts
>  create mode 100644 arch/arm/boot/dts/imx27.dtsi
>  create mode 100644 arch/arm/mach-imx/imx27-dt.c


From rnayak at ti.com  Thu Mar  1 01:49:33 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 01 Mar 2012 12:19:33 +0530
Subject: [PATCHv3 2/6] ARM: OMAP3 PM: Move IO Daisychain function to omap3
 prm file
In-Reply-To: <1330525621-29836-3-git-send-email-t-kristo@ti.com>
References: <1330525621-29836-1-git-send-email-t-kristo@ti.com>
 <1330525621-29836-3-git-send-email-t-kristo@ti.com>
Message-ID: <4F4F1BFD.4020903@ti.com>

On Wednesday 29 February 2012 07:56 PM, Tero Kristo wrote:
> From: Vishwanath BS<vishwanath.bs at ti.com>
>
> Since IO Daisychain modifies only PRM registers, it makes sense to move
> it to PRM File.
>
> Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com>
> Tested-by: Govindraj.R<govindraj.raja at ti.com>
> Signed-off-by: Tero Kristo<t-kristo at ti.com>
> ---
>   arch/arm/mach-omap2/pm34xx.c       |   30 +-----------------------------
>   arch/arm/mach-omap2/prm2xxx_3xxx.c |   32 ++++++++++++++++++++++++++++++++
>   arch/arm/mach-omap2/prm2xxx_3xxx.h |   14 ++++++++++++++
>   3 files changed, 47 insertions(+), 29 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index b0821a8..e97ec3f 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -85,34 +85,6 @@ static inline void omap3_per_restore_context(void)
>   	omap_gpio_restore_context();
>   }
>
> -static void omap3_enable_io_chain(void)
> -{
> -	int timeout = 0;
> -
> -	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> -				   PM_WKEN);
> -	/* Do a readback to assure write has been done */
> -	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
> -
> -	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST)&
> -		 OMAP3430_ST_IO_CHAIN_MASK)) {
> -		timeout++;
> -		if (timeout>  1000) {
> -			pr_err("Wake up daisy chain activation failed.\n");
> -			return;
> -		}
> -	}
> -	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> -			PM_WKEN);
> -
> -}
> -
> -static void omap3_disable_io_chain(void)
> -{
> -	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> -				     PM_WKEN);
> -}
> -
>   static void omap3_core_save_context(void)
>   {
>   	omap3_ctrl_save_padconf();
> @@ -324,7 +296,7 @@ void omap_sram_idle(void)
>   	     core_next_state<  PWRDM_POWER_ON)) {
>   		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
>   		if (omap3_has_io_chain_ctrl())
> -			omap3_enable_io_chain();
> +			omap3_trigger_io_chain();
>   	}
>
>   	pwrdm_pre_transition();
> diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> index 9ce7654..fc98781 100644
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> @@ -301,6 +301,38 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
>   				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
>   }
>
> +/**
> + * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
> + * the I/O ring after asserting WUCLKIN high
> + */
> +#define MAX_IOPAD_LATCH_TIME 1000

Since we are changing the implementation to use omap_test_timeout()
in this patch, it makes sense to make this 100 so we have a max 100us
delay, similar to what we did on OMAP4.

> +
> +/* OMAP3 Daisychain enable sequence */
> +void omap3_trigger_io_chain(void)
> +{
> +	int i = 0;
> +
> +	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> +				   PM_WKEN);
> +	/* Do a readback to assure write has been done */
> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
> +
> +	omap_test_timeout(((omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST)&
> +			    OMAP3430_ST_IO_CHAIN_MASK) == 1),
> +			  MAX_IOPAD_LATCH_TIME, i);
> +
> +	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> +				     PM_WKEN);

The comment from Djamil should hold good here too. We should wait for
IO chain status to show 0 here.

> +}
> +

regards,
Rajendra


From rnayak at ti.com  Thu Mar  1 01:52:42 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 01 Mar 2012 12:22:42 +0530
Subject: [PATCHv3 4/6] ARM: OMAP3 PM: Enable IO Wake up
In-Reply-To: <1330525621-29836-5-git-send-email-t-kristo@ti.com>
References: <1330525621-29836-1-git-send-email-t-kristo@ti.com>
 <1330525621-29836-5-git-send-email-t-kristo@ti.com>
Message-ID: <4F4F1CBA.7040502@ti.com>

On Wednesday 29 February 2012 07:56 PM, Tero Kristo wrote:
> From: Vishwanath BS<vishwanath.bs at ti.com>
>
> Enable IO Wake up for OMAP3 as part of PM Init. Currently this has been
> managed in cpuidle path which is not the right place. Subsequent patch
> will remove IO Daisy chain handling in cpuidle path once daisy chain is
> handled as part of hwmod mux.
>
> Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com>
> Tested-by: Govindraj.R<govindraj.raja at ti.com>
> Signed-off-by: Tero Kristo<t-kristo at ti.com>
> ---
>   arch/arm/mach-omap2/pm34xx.c |    4 ++++
>   1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index e97ec3f..e6c2d39 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -793,6 +793,10 @@ static int __init omap3_pm_init(void)
>   		goto err1;
>   	}
>
> +	if (omap3_has_io_wakeup())
> +		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
> +					   PM_WKEN);

On OMAP4 this GLOBAL IO chain enable happens as part of the trigger
function itself, it might make sense to do that for OMAP3 too to avoid
similar issues as seen on OMAP4 when the GLOBAL switch is enabled too
late in boot. The best however would be to get rid of it in the trigger
function and enable this early during PM init, but I am not sure whats
a good place to do this 'early' enough.

regards,
Rajendra

> +
>   	ret = pwrdm_for_each(pwrdms_setup, NULL);
>   	if (ret) {
>   		printk(KERN_ERR "Failed to setup powerdomains\n");



From rnayak at ti.com  Thu Mar  1 02:01:07 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 01 Mar 2012 12:31:07 +0530
Subject: [PATCHv3 4/4] ARM: OMAP3+: add prcm chain interrupts to the
 interrupt list
In-Reply-To: <1330529106-10423-5-git-send-email-t-kristo@ti.com>
References: <1330529106-10423-1-git-send-email-t-kristo@ti.com>
 <1330529106-10423-5-git-send-email-t-kristo@ti.com>
Message-ID: <4F4F1EB3.6020707@ti.com>

On Wednesday 29 February 2012 08:55 PM, Tero Kristo wrote:
> Currently PRCM chain handler for OMAP4 requires SPARSE_IRQ to be enabled
> from kernel config, however enabling this option breaks the OMAP kernel
> completely and it can't be used. Thus, OMAP_PRCM_IRQ_BASE was added
> to the end of the irq list, and the prm_common code was changed to use
> this instead of irq_desc allocation scheme.
>
> Once SPARSE_IRQ is enabled for OMAP kernel, this patch can be reverted.

Do you still need this, despite this fix from Benoit?
http://marc.info/?l=linux-arm-kernel&m=133043468329275&w=2

>
> Signed-off-by: Tero Kristo<t-kristo at ti.com>
> Cc: Paul Walmsley<paul at pwsan.com>
> ---
>   arch/arm/mach-omap2/prm_common.c       |   14 +-------------
>   arch/arm/plat-omap/include/plat/irqs.h |    6 +++++-
>   2 files changed, 6 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
> index 860118a..9ca829f 100644
> --- a/arch/arm/mach-omap2/prm_common.c
> +++ b/arch/arm/mach-omap2/prm_common.c
> @@ -196,11 +196,6 @@ void omap_prcm_irq_cleanup(void)
>   	prcm_irq_setup->priority_mask = NULL;
>
>   	irq_set_chained_handler(prcm_irq_setup->irq, NULL);
> -
> -	if (prcm_irq_setup->base_irq>  0)
> -		irq_free_descs(prcm_irq_setup->base_irq,
> -			prcm_irq_setup->nr_regs * 32);
> -	prcm_irq_setup->base_irq = 0;
>   }
>
>   void omap_prcm_irq_prepare(void)
> @@ -282,14 +277,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
>
>   	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
>
> -	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
> -		0);
> -
> -	if (irq_setup->base_irq<  0) {
> -		pr_err("PRCM: failed to allocate irq descs: %d\n",
> -			irq_setup->base_irq);
> -		goto err;
> -	}
> +	irq_setup->base_irq = OMAP_PRCM_IRQ_BASE;
>
>   	for (i = 0; i<= irq_setup->nr_regs; i++) {
>   		gc = irq_alloc_generic_chip("PRCM", 1,
> diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
> index 2efd645..fe1be1d 100644
> --- a/arch/arm/plat-omap/include/plat/irqs.h
> +++ b/arch/arm/plat-omap/include/plat/irqs.h
> @@ -428,8 +428,12 @@
>   #define OMAP_GPMC_NR_IRQS	8
>   #define OMAP_GPMC_IRQ_END	(OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
>
> +/* PRCM chain handler */
> +#define OMAP_PRCM_IRQ_BASE	(OMAP_GPMC_IRQ_END)
> +#define OMAP_PRCM_NR_IRQS	64
> +#define OMAP_PRCM_IRQ_END	(OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
>
> -#define NR_IRQS			OMAP_GPMC_IRQ_END
> +#define NR_IRQS			OMAP_PRCM_IRQ_END
>
>   #define OMAP_IRQ_BIT(irq)	(1<<  ((irq) % 32))
>



From subhashj at codeaurora.org  Thu Mar  1 03:08:51 2012
From: subhashj at codeaurora.org (Subhash Jadavani)
Date: Thu, 01 Mar 2012 13:38:51 +0530
Subject: [PATCH V2 1/1] mmc: start removing enable / disable API
In-Reply-To: <1330499841-6879-2-git-send-email-adrian.hunter@intel.com>
References: <1330499841-6879-1-git-send-email-adrian.hunter@intel.com>
 <1330499841-6879-2-git-send-email-adrian.hunter@intel.com>
Message-ID: <4F4F2E93.1090109@codeaurora.org>

On 2/29/2012 12:47 PM, Adrian Hunter wrote:
> Most parts of the enable / disable API are no longer used and
> can be removed.
>
> Cc: Rajendra Nayak<rnayak at ti.com>
> Cc: Venkatraman S<svenkatr at ti.com>
> Cc: Kukjin Kim<kgene.kim at samsung.com>
> Cc: Thomas Abraham<thomas.abraham at linaro.org>
> Cc: Kyungmin Park<kyungmin.park at samsung.com>
> Cc: Sekhar Nori<nsekhar at ti.com>
> Cc: Kevin Hilman<khilman at ti.com>
> Signed-off-by: Adrian Hunter<adrian.hunter at intel.com>
> ---
>   arch/arm/mach-exynos/mach-nuri.c           |    5 +-
>   arch/arm/mach-exynos/mach-universal_c210.c |    9 +-
>   drivers/mmc/core/core.c                    |  187 +++-------------------------
>   drivers/mmc/core/host.c                    |    1 -
>   drivers/mmc/core/host.h                    |    1 -
>   drivers/mmc/host/davinci_mmc.c             |    4 -
>   drivers/mmc/host/omap_hsmmc.c              |   15 +--
>   include/linux/mmc/core.h                   |    1 -
>   include/linux/mmc/host.h                   |   46 +------
>   9 files changed, 27 insertions(+), 242 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
> index 644af11..de68248 100644
> --- a/arch/arm/mach-exynos/mach-nuri.c
> +++ b/arch/arm/mach-exynos/mach-nuri.c
> @@ -109,7 +109,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
>   	.max_width		= 8,
>   	.host_caps		= (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
>   				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> -				MMC_CAP_DISABLE | MMC_CAP_ERASE),
> +				MMC_CAP_ERASE),
>   	.cd_type		= S3C_SDHCI_CD_PERMANENT,
>   };
>
> @@ -147,8 +147,7 @@ static struct platform_device emmc_fixed_voltage = {
>   static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
>   	.max_width		= 4,
>   	.host_caps		= MMC_CAP_4_BIT_DATA |
> -				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> -				MMC_CAP_DISABLE,
> +				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>   	.ext_cd_gpio		= EXYNOS4_GPX3(3),	/* XEINT_27 */
>   	.ext_cd_gpio_invert	= 1,
>   	.cd_type		= S3C_SDHCI_CD_GPIO,
> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
> index 9b3fbae..57cfe61 100644
> --- a/arch/arm/mach-exynos/mach-universal_c210.c
> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
> @@ -734,8 +734,7 @@ static struct platform_device universal_gpio_keys = {
>   static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
>   	.max_width		= 8,
>   	.host_caps		= (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
> -				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> -				MMC_CAP_DISABLE),
> +				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
>   	.cd_type		= S3C_SDHCI_CD_PERMANENT,
>   };
>
> @@ -772,8 +771,7 @@ static struct platform_device mmc0_fixed_voltage = {
>   static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
>   	.max_width		= 4,
>   	.host_caps		= MMC_CAP_4_BIT_DATA |
> -				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> -				MMC_CAP_DISABLE,
> +				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>   	.ext_cd_gpio		= EXYNOS4_GPX3(4),      /* XEINT_28 */
>   	.ext_cd_gpio_invert	= 1,
>   	.cd_type		= S3C_SDHCI_CD_GPIO,
> @@ -783,8 +781,7 @@ static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
>   static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
>   	.max_width		= 4,
>   	.host_caps		= MMC_CAP_4_BIT_DATA |
> -				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> -				MMC_CAP_DISABLE,
> +				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>   	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
>   };
>
> diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
> index 0b317f0..44dd013 100644
> --- a/drivers/mmc/core/core.c
> +++ b/drivers/mmc/core/core.c
> @@ -605,105 +605,6 @@ unsigned int mmc_align_data_size(struct mmc_card *card, unsigned int sz)
>   EXPORT_SYMBOL(mmc_align_data_size);
>
>   /**
> - *	mmc_host_enable - enable a host.
> - *	@host: mmc host to enable
> - *
> - *	Hosts that support power saving can use the 'enable' and 'disable'
> - *	methods to exit and enter power saving states. For more information
> - *	see comments for struct mmc_host_ops.
> - */
> -int mmc_host_enable(struct mmc_host *host)
> -{
> -	if (!(host->caps&  MMC_CAP_DISABLE))
> -		return 0;
> -
> -	if (host->en_dis_recurs)
> -		return 0;
> -
> -	if (host->nesting_cnt++)
> -		return 0;
> -
> -	cancel_delayed_work_sync(&host->disable);
> -
> -	if (host->enabled)
> -		return 0;
> -
> -	if (host->ops->enable) {
> -		int err;
> -
> -		host->en_dis_recurs = 1;
> -		mmc_host_clk_hold(host);
> -		err = host->ops->enable(host);
> -		mmc_host_clk_release(host);
> -		host->en_dis_recurs = 0;
> -
> -		if (err) {
> -			pr_debug("%s: enable error %d\n",
> -				 mmc_hostname(host), err);
> -			return err;
> -		}
> -	}
> -	host->enabled = 1;
> -	return 0;
> -}
> -EXPORT_SYMBOL(mmc_host_enable);
> -
> -static int mmc_host_do_disable(struct mmc_host *host, int lazy)
> -{
> -	if (host->ops->disable) {
> -		int err;
> -
> -		host->en_dis_recurs = 1;
> -		mmc_host_clk_hold(host);
> -		err = host->ops->disable(host, lazy);
> -		mmc_host_clk_release(host);
> -		host->en_dis_recurs = 0;
> -
> -		if (err<  0) {
> -			pr_debug("%s: disable error %d\n",
> -				 mmc_hostname(host), err);
> -			return err;
> -		}
> -		if (err>  0) {
> -			unsigned long delay = msecs_to_jiffies(err);
> -
> -			mmc_schedule_delayed_work(&host->disable, delay);
> -		}
> -	}
> -	host->enabled = 0;
> -	return 0;
> -}
> -
> -/**
> - *	mmc_host_disable - disable a host.
> - *	@host: mmc host to disable
> - *
> - *	Hosts that support power saving can use the 'enable' and 'disable'
> - *	methods to exit and enter power saving states. For more information
> - *	see comments for struct mmc_host_ops.
> - */
> -int mmc_host_disable(struct mmc_host *host)
> -{
> -	int err;
> -
> -	if (!(host->caps&  MMC_CAP_DISABLE))
> -		return 0;
> -
> -	if (host->en_dis_recurs)
> -		return 0;
> -
> -	if (--host->nesting_cnt)
> -		return 0;
> -
> -	if (!host->enabled)
> -		return 0;
> -
> -	err = mmc_host_do_disable(host, 0);
> -	return err;
> -}
> -EXPORT_SYMBOL(mmc_host_disable);
> -
> -/**
>    *	__mmc_claim_host - exclusively claim a host
>    *	@host: mmc host to claim
>    *	@abort: whether or not the operation should be aborted
> @@ -741,8 +642,8 @@ int __mmc_claim_host(struct mmc_host *host, atomic_t *abort)
>   		wake_up(&host->wq);
>   	spin_unlock_irqrestore(&host->lock, flags);
>   	remove_wait_queue(&host->wq,&wait);
> -	if (!stop)
> -		mmc_host_enable(host);
> +	if (host->ops->enable&&  !stop&&  host->claim_cnt == 1)
Shouldn't we still make sure that clocks are hold (by calling 
mmc_host_clk_hold() ) before calling enable?
> +		host->ops->enable(host);
>   	return stop;
>   }
>
> @@ -767,21 +668,28 @@ int mmc_try_claim_host(struct mmc_host *host)
>   		claimed_host = 1;
>   	}
>   	spin_unlock_irqrestore(&host->lock, flags);
> +	if (host->ops->enable&&  claimed_host&&  host->claim_cnt == 1)
mmc_host_clk_hold() ?
> +		host->ops->enable(host);
>   	return claimed_host;
>   }
>   EXPORT_SYMBOL(mmc_try_claim_host);
>
>   /**
> - *	mmc_do_release_host - release a claimed host
> + *	mmc_release_host - release a host
>    *	@host: mmc host to release
>    *
> - *	If you successfully claimed a host, this function will
> - *	release it again.
> + *	Release a MMC host, allowing others to claim the host
> + *	for their operations.
>    */
> -void mmc_do_release_host(struct mmc_host *host)
> +void mmc_release_host(struct mmc_host *host)
>   {
>   	unsigned long flags;
>
> +	WARN_ON(!host->claimed);
> +
> +	if (host->ops->disable&&  host->claim_cnt == 1)
mmc_host_clk_hold ??
> +		host->ops->disable(host);
> +
>   	spin_lock_irqsave(&host->lock, flags);
>   	if (--host->claim_cnt) {
>   		/* Release for nested claim */
> @@ -793,67 +701,6 @@ void mmc_do_release_host(struct mmc_host *host)
>   		wake_up(&host->wq);
>   	}
>   }
> -EXPORT_SYMBOL(mmc_do_release_host);
> -
> -void mmc_host_deeper_disable(struct work_struct *work)
> -{
> -	struct mmc_host *host =
> -		container_of(work, struct mmc_host, disable.work);
> -
> -	/* If the host is claimed then we do not want to disable it anymore */
> -	if (!mmc_try_claim_host(host))
> -		return;
> -	mmc_host_do_disable(host, 1);
> -	mmc_do_release_host(host);
> -}
> -
> -/**
> - *	mmc_host_lazy_disable - lazily disable a host.
> - *	@host: mmc host to disable
> - *
> - *	Hosts that support power saving can use the 'enable' and 'disable'
> - *	methods to exit and enter power saving states. For more information
> - *	see comments for struct mmc_host_ops.
> - */
> -int mmc_host_lazy_disable(struct mmc_host *host)
> -{
> -	if (!(host->caps&  MMC_CAP_DISABLE))
> -		return 0;
> -
> -	if (host->en_dis_recurs)
> -		return 0;
> -
> -	if (--host->nesting_cnt)
> -		return 0;
> -
> -	if (!host->enabled)
> -		return 0;
> -
> -	if (host->disable_delay) {
> -		mmc_schedule_delayed_work(&host->disable,
> -				msecs_to_jiffies(host->disable_delay));
> -		return 0;
> -	} else
> -		return mmc_host_do_disable(host, 1);
> -}
> -EXPORT_SYMBOL(mmc_host_lazy_disable);
> -
> -/**
> - *	mmc_release_host - release a host
> - *	@host: mmc host to release
> - *
> - *	Release a MMC host, allowing others to claim the host
> - *	for their operations.
> - */
> -void mmc_release_host(struct mmc_host *host)
> -{
> -	WARN_ON(!host->claimed);
> -
> -	mmc_host_lazy_disable(host);
> -
> -	mmc_do_release_host(host);
> -}
> -
>   EXPORT_SYMBOL(mmc_release_host);
>
>   /*
> @@ -2206,8 +2053,6 @@ void mmc_stop_host(struct mmc_host *host)
>   	spin_unlock_irqrestore(&host->lock, flags);
>   #endif
>
> -	if (host->caps&  MMC_CAP_DISABLE)
> -		cancel_delayed_work(&host->disable);
>   	cancel_delayed_work_sync(&host->detect);
>   	mmc_flush_scheduled_work();
>
> @@ -2402,13 +2247,11 @@ int mmc_suspend_host(struct mmc_host *host)
>   {
>   	int err = 0;
>
> -	if (host->caps&  MMC_CAP_DISABLE)
> -		cancel_delayed_work(&host->disable);
>   	cancel_delayed_work(&host->detect);
>   	mmc_flush_scheduled_work();
>   	if (mmc_try_claim_host(host)) {
>   		err = mmc_cache_ctrl(host, 0);
> -		mmc_do_release_host(host);
> +		mmc_release_host(host);
>   	} else {
>   		err = -EBUSY;
>   	}
> @@ -2429,7 +2272,7 @@ int mmc_suspend_host(struct mmc_host *host)
>   			if (host->bus_ops->suspend) {
>   				err = host->bus_ops->suspend(host);
>   			}
> -			mmc_do_release_host(host);
> +			mmc_release_host(host);
>
>   			if (err == -ENOSYS || !host->bus_ops->resume) {
>   				/*
> diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
> index c3704e2..91c84c7 100644
> --- a/drivers/mmc/core/host.c
> +++ b/drivers/mmc/core/host.c
> @@ -330,7 +330,6 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
>   	spin_lock_init(&host->lock);
>   	init_waitqueue_head(&host->wq);
>   	INIT_DELAYED_WORK(&host->detect, mmc_rescan);
> -	INIT_DELAYED_WORK_DEFERRABLE(&host->disable, mmc_host_deeper_disable);
>   #ifdef CONFIG_PM
>   	host->pm_notify.notifier_call = mmc_pm_notify;
>   #endif
> diff --git a/drivers/mmc/core/host.h b/drivers/mmc/core/host.h
> index 08a7852..f2ab9e5 100644
> --- a/drivers/mmc/core/host.h
> +++ b/drivers/mmc/core/host.h
> @@ -14,7 +14,6 @@
>
>   int mmc_register_host_class(void);
>   void mmc_unregister_host_class(void);
> -void mmc_host_deeper_disable(struct work_struct *work);
>
>   #endif
>
> diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
> index 64a8325..8de9c9b 100644
> --- a/drivers/mmc/host/davinci_mmc.c
> +++ b/drivers/mmc/host/davinci_mmc.c
> @@ -1418,17 +1418,14 @@ static int davinci_mmcsd_suspend(struct device *dev)
>   	struct mmc_davinci_host *host = platform_get_drvdata(pdev);
>   	int ret;
>
> -	mmc_host_enable(host->mmc);
>   	ret = mmc_suspend_host(host->mmc);
>   	if (!ret) {
>   		writel(0, host->base + DAVINCI_MMCIM);
>   		mmc_davinci_reset_ctrl(host, 1);
> -		mmc_host_disable(host->mmc);
>   		clk_disable(host->clk);
>   		host->suspended = 1;
>   	} else {
>   		host->suspended = 0;
> -		mmc_host_disable(host->mmc);
>   	}
>
>   	return ret;
> @@ -1444,7 +1441,6 @@ static int davinci_mmcsd_resume(struct device *dev)
>   		return 0;
>
>   	clk_enable(host->clk);
> -	mmc_host_enable(host->mmc);
>
>   	mmc_davinci_reset_ctrl(host, 0);
>   	ret = mmc_resume_host(host->mmc);
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index 36e7f5b..fdb24cf 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -179,7 +179,6 @@ struct omap_hsmmc_host {
>   	int			got_dbclk;
>   	int			response_busy;
>   	int			context_loss;
> -	int			dpm_state;
>   	int			vdd;
>   	int			protect_card;
>   	int			reqs_blocked;
> @@ -1748,7 +1747,7 @@ static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
>   	return 0;
>   }
>
> -static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
> +static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
>   {
>   	struct omap_hsmmc_host *host = mmc_priv(mmc);
>
> @@ -1782,15 +1781,8 @@ static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
>   	if (host->pdata->get_context_loss_count)
>   		context_loss = host->pdata->get_context_loss_count(host->dev);
>
> -	seq_printf(s, "mmc%d:\n"
> -			" enabled:\t%d\n"
> -			" dpm_state:\t%d\n"
> -			" nesting_cnt:\t%d\n"
> -			" ctx_loss:\t%d:%d\n"
> -			"\nregs:\n",
> -			mmc->index, mmc->enabled ? 1 : 0,
> -			host->dpm_state, mmc->nesting_cnt,
> -			host->context_loss, context_loss);
> +	seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
> +			mmc->index, host->context_loss, context_loss);
>
>   	if (host->suspended) {
>   		seq_printf(s, "host suspended, can't read registers\n");
> @@ -1930,7 +1922,6 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>
>   	omap_hsmmc_context_save(host);
>
> -	mmc->caps |= MMC_CAP_DISABLE;
>   	if (host->pdata->controller_flags&  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
>   		dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
>   		mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
> diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
> index 87a976c..2bfa589 100644
> --- a/include/linux/mmc/core.h
> +++ b/include/linux/mmc/core.h
> @@ -175,7 +175,6 @@ extern unsigned int mmc_align_data_size(struct mmc_card *, unsigned int);
>
>   extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort);
>   extern void mmc_release_host(struct mmc_host *host);
> -extern void mmc_do_release_host(struct mmc_host *host);
>   extern int mmc_try_claim_host(struct mmc_host *host);
>
>   extern int mmc_flush_cache(struct mmc_card *);
> diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
> index 37147a4..4da98f7 100644
> --- a/include/linux/mmc/host.h
> +++ b/include/linux/mmc/host.h
> @@ -80,34 +80,11 @@ struct mmc_ios {
>
>   struct mmc_host_ops {
>   	/*
> -	 * Hosts that support power saving can use the 'enable' and 'disable'
> -	 * methods to exit and enter power saving states. 'enable' is called
> -	 * when the host is claimed and 'disable' is called (or scheduled with
> -	 * a delay) when the host is released. The 'disable' is scheduled if
> -	 * the disable delay set by 'mmc_set_disable_delay()' is non-zero,
> -	 * otherwise 'disable' is called immediately. 'disable' may be
> -	 * scheduled repeatedly, to permit ever greater power saving at the
> -	 * expense of ever greater latency to re-enable. Rescheduling is
> -	 * determined by the return value of the 'disable' method. A positive
> -	 * value gives the delay in milliseconds.
> -	 *
> -	 * In the case where a host function (like set_ios) may be called
> -	 * with or without the host claimed, enabling and disabling can be
> -	 * done directly and will nest correctly. Call 'mmc_host_enable()' and
> -	 * 'mmc_host_lazy_disable()' for this purpose, but note that these
> -	 * functions must be paired.
> -	 *
> -	 * Alternatively, 'mmc_host_enable()' may be paired with
> -	 * 'mmc_host_disable()' which calls 'disable' immediately.  In this
> -	 * case the 'disable' method will be called with 'lazy' set to 0.
> -	 * This is mainly useful for error paths.
> -	 *
> -	 * Because lazy disable may be called from a work queue, the 'disable'
> -	 * method must claim the host when 'lazy' != 0, which will work
> -	 * correctly because recursion is detected and handled.
> +	 * 'enable' is called when the host is claimed and 'disable' is called
> +	 * when the host is released. 'enable' and 'disable' are deprecated.
>   	 */
>   	int (*enable)(struct mmc_host *host);
> -	int (*disable)(struct mmc_host *host, int lazy);
> +	int (*disable)(struct mmc_host *host);
>   	/*
>   	 * It is optional for the host to implement pre_req and post_req in
>   	 * order to support double buffering of requests (prepare one
> @@ -218,7 +195,7 @@ struct mmc_host {
>   #define MMC_CAP_SPI		(1<<  4)	/* Talks only SPI protocols */
>   #define MMC_CAP_NEEDS_POLL	(1<<  5)	/* Needs polling for card-detection */
>   #define MMC_CAP_8_BIT_DATA	(1<<  6)	/* Can the host do 8 bit transfers */
> -#define MMC_CAP_DISABLE		(1<<  7)	/* Can the host be disabled */
> +
>   #define MMC_CAP_NONREMOVABLE	(1<<  8)	/* Nonremovable e.g. eMMC */
>   #define MMC_CAP_WAIT_WHILE_BUSY	(1<<  9)	/* Waits while card is busy */
>   #define MMC_CAP_ERASE		(1<<  10)	/* Allow erase/trim commands */
> @@ -301,13 +278,7 @@ struct mmc_host {
>   	unsigned int		removed:1;	/* host is being removed */
>   #endif
>
> -	/* Only used with MMC_CAP_DISABLE */
> -	int			enabled;	/* host is enabled */
>   	int			rescan_disable;	/* disable card detection */
> -	int			nesting_cnt;	/* "enable" nesting count */
> -	int			en_dis_recurs;	/* detect recursion */
> -	unsigned int		disable_delay;	/* disable delay in msecs */
> -	struct delayed_work	disable;	/* disabling work */
>
>   	struct mmc_card		*card;		/* device attached to this host */
>
> @@ -407,17 +378,8 @@ int mmc_card_awake(struct mmc_host *host);
>   int mmc_card_sleep(struct mmc_host *host);
>   int mmc_card_can_sleep(struct mmc_host *host);
>
> -int mmc_host_enable(struct mmc_host *host);
> -int mmc_host_disable(struct mmc_host *host);
> -int mmc_host_lazy_disable(struct mmc_host *host);
>   int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *);
>
> -static inline void mmc_set_disable_delay(struct mmc_host *host,
> -					 unsigned int disable_delay)
> -{
> -	host->disable_delay = disable_delay;
> -}
> -
>   /* Module parameter */
>   extern bool mmc_assume_removable;
>



From ohad at wizery.com  Thu Mar  1 03:11:30 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Thu,  1 Mar 2012 10:11:30 +0200
Subject: [PATCH 0/7] remoteproc: additional virtio support
Message-ID: <1330589497-4139-1-git-send-email-ohad@wizery.com>

The patch set focuses on extending remoteproc's virtio support: we're
putting behind the single rpmsg virtio device limitation, and allowing
firmwares to publish any number of virtio devices and of any type.

This allows us to reuse the existing virtio drivers with remote processor
backends.

For example, by publishing a virtio console device and hooking it up to the
logging mechanism of OMAP's SYS/BIOS (the RTOS which runs on the M3
subsystem), we get a fancy console with log messages coming from the M3
without writing any additional driver:

root at omap4430-panda:~# modprobe virtio_console
root at omap4430-panda:~# cat /dev/hvc0 
M3 Core0 init...
Hello from SYS/BIOS
copyTask 50: Entered...:
registering rpmsg-client-sample service on 50 with HOST
copyTask 51: Entered...:
registering rpmsg-proto service on 51 with HOST
registering rpmsg-omx service on 60 with HOST
copyTask 1: Received data: hello world!, len:12
copyTask 2: Received data: hello world!, len:12
copyTask 3: Received data: hello world!, len:12
...

Note: at this point, whether you can start using vanilla virtio drivers
with your remote processor strongly depends on your platform. E.g., there
are additional changes required for this to work on OMAP4 (mainly to
satisfy the M3's iommu requirements), and that's not upstream yet.
Other non-iommu remote processors might be able to use vanilla virtio
drivers though (probably DaVinci, for example, but this wasn't tested yet).

Cc: Brian Swetland <swetland at google.com>
Cc: Iliyan Malchev <malchev at google.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rusty Russell <rusty at rustcorp.com.au>
Cc: Mark Grosen <mgrosen at ti.com>
Cc: John Williams <john.williams at petalogix.com>
Cc: Michal Simek <monstr at monstr.eu>
Cc: Loic PALLARDY <loic.pallardy at stericsson.com>
Cc: Ludovic BARRE <ludovic.barre at stericsson.com>
Cc: Omar Ramirez Luna <omar.luna at linaro.org>
Cc: Guzman Lugo Fernando <fernando.lugo at ti.com>
Cc: Anna Suman <s-anna at ti.com>
Cc: Clark Rob <rob at ti.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: David Brown <davidb at codeaurora.org>
Cc: Kieran Bingham <kieranbingham at gmail.com>
Cc: Tony Lindgren <tony at atomide.com>

Ohad Ben-Cohen (7):
  remoteproc: resource table overhaul
  remoteproc: remoteproc_rpmsg -> remoteproc_virtio
  remoteproc: safer boot/shutdown order
  remoteproc: remove the single rpmsg vdev limitation
  remoteproc/omap: remove the mbox_callback limitation
  remoteproc: remove the hardcoded vring alignment
  remoteproc: cleanup resource table parsing paths

 Documentation/remoteproc.txt                       |  136 +++---
 drivers/remoteproc/Makefile                        |    2 +-
 drivers/remoteproc/omap_remoteproc.c               |   11 +-
 drivers/remoteproc/remoteproc_core.c               |  524 ++++++++++++--------
 drivers/remoteproc/remoteproc_internal.h           |    6 +-
 .../{remoteproc_rpmsg.c => remoteproc_virtio.c}    |  162 +++----
 include/linux/remoteproc.h                         |  339 ++++++++++---
 7 files changed, 747 insertions(+), 433 deletions(-)
 rename drivers/remoteproc/{remoteproc_rpmsg.c => remoteproc_virtio.c} (65%)

-- 
1.7.5.4



From ohad at wizery.com  Thu Mar  1 03:11:31 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Thu,  1 Mar 2012 10:11:31 +0200
Subject: [PATCH 1/7] remoteproc: resource table overhaul
In-Reply-To: <1330589497-4139-1-git-send-email-ohad@wizery.com>
References: <1330589497-4139-1-git-send-email-ohad@wizery.com>
Message-ID: <1330589497-4139-2-git-send-email-ohad@wizery.com>

The resource table is an array of 'struct fw_resource' members, where
each resource entry is expressed as a single member of that array.

This approach got us this far, but it has a few drawbacks:

1. Different resource entries end up overloading the same members of 'struct
   fw_resource' with different meanings. The resulting code is error prone
   and hard to read and maintain.

2. It's impossible to extend 'struct fw_resource' without breaking the
   existing firmware images (and we already want to: we can't introduce the
   new virito device resource entry with the current scheme).

3. It doesn't scale: 'struct fw_resource' must be as big as the largest
   resource entry type. As a result, smaller resource entries end up
   utilizing only small part of it.

This is fixed by defining a dedicated structure for every resource type,
and then converting the resource table to a list of type-value members.
Instead of a rigid array of homogeneous structs, the resource table
is turned into a collection of heterogeneous structures.

This way:
1. Resource entries consume exactly the amount of bytes they need.
2. It's easy to extend: just create a new resource entry structure, and assign
   it a new type.
3. The code is easier to read and maintain: the structures' members names are
   meaningful.

While we're at it, this patch has several other resource table changes:
1. The resource table gains a simple header which contains the
   number of entries in the table and their offsets within the table. This
   makes the parsing code simpler and easier to read.
2. A version member is added to the resource table. Should we change the
   format again, we'll bump up this version to prevent breakage with
   existing firmware images.
3. The VRING and VIRTIO_DEV resource entries are combined to a single
   VDEV entry. This paves the way to supporting multiple VDEV entries.
4. Since we don't really support 64-bit rprocs yet, convert two stray u64
   members to u32.

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Cc: Brian Swetland <swetland at google.com>
Cc: Iliyan Malchev <malchev at google.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rusty Russell <rusty at rustcorp.com.au>
Cc: Mark Grosen <mgrosen at ti.com>
Cc: John Williams <john.williams at petalogix.com>
Cc: Michal Simek <monstr at monstr.eu>
Cc: Loic PALLARDY <loic.pallardy at stericsson.com>
Cc: Ludovic BARRE <ludovic.barre at stericsson.com>
Cc: Omar Ramirez Luna <omar.luna at linaro.org>
Cc: Guzman Lugo Fernando <fernando.lugo at ti.com>
Cc: Anna Suman <s-anna at ti.com>
Cc: Clark Rob <rob at ti.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: David Brown <davidb at codeaurora.org>
Cc: Kieran Bingham <kieranbingham at gmail.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 Documentation/remoteproc.txt         |  127 +++++++--------
 drivers/remoteproc/remoteproc_core.c |  306 +++++++++++++++++++++++-----------
 include/linux/remoteproc.h           |  289 ++++++++++++++++++++++++++------
 3 files changed, 505 insertions(+), 217 deletions(-)

diff --git a/Documentation/remoteproc.txt b/Documentation/remoteproc.txt
index 23ff734..07057ca 100644
--- a/Documentation/remoteproc.txt
+++ b/Documentation/remoteproc.txt
@@ -221,43 +221,52 @@ resource entries that publish the existence of supported features
 or configurations by the remote processor, such as trace buffers and
 supported virtio devices (and their configurations).
 
-Currently the resource table is just an array of:
+The resource table begins with this header:
 
 /**
- * struct fw_resource - describes an entry from the resource section
+ * struct resource_table - firmware resource table header
+ * @ver: version number
+ * @num: number of resource entries
+ * @reserved: reserved (must be zero)
+ * @offset: array of offsets pointing at the various resource entries
+ *
+ * The header of the resource table, as expressed by this structure,
+ * contains a version number (should we need to change this format in the
+ * future), the number of available resource entries, and their offsets
+ * in the table.
+ */
+struct resource_table {
+	u32 ver;
+	u32 num;
+	u32 reserved[2];
+	u32 offset[0];
+} __packed;
+
+Immediately following this header are the resource entries themselves,
+each of which begins with the following resource entry header:
+
+/**
+ * struct fw_rsc_hdr - firmware resource entry header
  * @type: resource type
- * @id: index number of the resource
- * @da: device address of the resource
- * @pa: physical address of the resource
- * @len: size, in bytes, of the resource
- * @flags: properties of the resource, e.g. iommu protection required
- * @reserved: must be 0 atm
- * @name: name of resource
+ * @data: resource data
+ *
+ * Every resource entry begins with a 'struct fw_rsc_hdr' header providing
+ * its @type. The content of the entry itself will immediately follow
+ * this header, and it should be parsed according to the resource type.
  */
-struct fw_resource {
+struct fw_rsc_hdr {
 	u32 type;
-	u32 id;
-	u64 da;
-	u64 pa;
-	u32 len;
-	u32 flags;
-	u8 reserved[16];
-	u8 name[48];
+	u8 data[0];
 } __packed;
 
 Some resources entries are mere announcements, where the host is informed
 of specific remoteproc configuration. Other entries require the host to
-do something (e.g. reserve a requested resource) and possibly also reply
-by overwriting a member inside 'struct fw_resource' with info about the
-allocated resource.
-
-Different resource entries use different members of this struct,
-with different meanings. This is pretty limiting and error-prone,
-so the plan is to move to variable-length TLV-based resource entries,
-where each resource will begin with a type and length fields, followed by
-its own specific structure.
+do something (e.g. allocate a system resource). Sometimes a negotiation
+is expected, where the firmware requests a resource, and once allocated,
+the host should provide back its details (e.g. address of an allocated
+memory region).
 
-Here are the resource types that are currently being used:
+Here are the various resource types that are currently supported:
 
 /**
  * enum fw_resource_type - types of resource entries
@@ -266,59 +275,45 @@ Here are the resource types that are currently being used:
  *		    memory region.
  * @RSC_DEVMEM:     request to iommu_map a memory-based peripheral.
  * @RSC_TRACE:	    announces the availability of a trace buffer into which
- *		    the remote processor will be writing logs. In this case,
- *		    'da' indicates the device address where logs are written to,
- *		    and 'len' is the size of the trace buffer.
- * @RSC_VRING:	    request for allocation of a virtio vring (address should
- *		    be indicated in 'da', and 'len' should contain the number
- *		    of buffers supported by the vring).
- * @RSC_VIRTIO_DEV: announces support for a virtio device, and serves as
- *		    the virtio header. 'da' contains the virtio device
- *		    features, 'pa' holds the virtio guest features (host
- *		    will write them here after they're negotiated), 'len'
- *		    holds the virtio status, and 'flags' holds the virtio
- *		    device id (currently only VIRTIO_ID_RPMSG is supported).
+ *		    the remote processor will be writing logs.
+ * @RSC_VDEV:       declare support for a virtio device, and serve as its
+ *		    virtio header.
+ * @RSC_LAST:       just keep this one at the end
+ *
+ * Please note that these values are used as indices to the rproc_handle_rsc
+ * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to
+ * check the validity of an index before the lookup table is accessed, so
+ * please update it as needed.
  */
 enum fw_resource_type {
 	RSC_CARVEOUT	= 0,
 	RSC_DEVMEM	= 1,
 	RSC_TRACE	= 2,
-	RSC_VRING	= 3,
-	RSC_VIRTIO_DEV	= 4,
-	RSC_VIRTIO_CFG	= 5,
+	RSC_VDEV	= 3,
+	RSC_LAST	= 4,
 };
 
-Most of the resource entries share the basic idea of address/length
-negotiation with the host: the firmware usually asks for memory
-of size 'len' bytes, and the host needs to allocate it and provide
-the device/physical address (when relevant) in 'da'/'pa' respectively.
-
-If the firmware is compiled with hard coded device addresses, and
-can't handle dynamically allocated 'da' values, then the 'da' field
-will contain the expected device addresses (today we actually only support
-this scheme, as there aren't yet any use cases for dynamically allocated
-device addresses).
+For more details regarding a specific resource type, please see its
+dedicated structure in include/linux/remoteproc.h.
 
 We also expect that platform-specific resource entries will show up
-at some point. When that happens, we could easily add a new RSC_PLAFORM
+at some point. When that happens, we could easily add a new RSC_PLATFORM
 type, and hand those resources to the platform-specific rproc driver to handle.
 
 7. Virtio and remoteproc
 
 The firmware should provide remoteproc information about virtio devices
-that it supports, and their configurations: a RSC_VIRTIO_DEV resource entry
-should specify the virtio device id, and subsequent RSC_VRING resource entries
-should indicate the vring size (i.e. how many buffers do they support) and
-where should they be mapped (i.e. which device address). Note: the alignment
-between the consumer and producer parts of the vring is assumed to be 4096.
-
-At this point we only support a single virtio rpmsg device per remote
-processor, but the plan is to remove this limitation. In addition, once we
-move to TLV-based resource table, the plan is to have a single RSC_VIRTIO
-entry per supported virtio device, which will include the virtio header,
-the vrings information and the virtio config space.
-
-Of course, RSC_VIRTIO resource entries are only good enough for static
+that it supports, and their configurations: a RSC_VDEV resource entry
+should specify the virtio device id (as in virtio_ids.h), virtio features,
+virtio config space, vrings information, etc.
+
+When a new remote processor is registered, the remoteproc framework
+will look for its resource table and will register the virtio devices
+it supports. A firmware may support any number of virtio devices, and
+of any type (a single remote processor can also easily support several
+rpmsg virtio devices this way, if desired).
+
+Of course, RSC_VDEV resource entries are only good enough for static
 allocation of virtio devices. Dynamic allocations will also be made possible
 using the rpmsg bus (similar to how we already do dynamic allocations of
 rpmsg channels; read more about it in rpmsg.txt).
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index 8990c51..1034845 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -63,9 +63,8 @@ static void klist_rproc_put(struct klist_node *n);
 static DEFINE_KLIST(rprocs, klist_rproc_get, klist_rproc_put);
 
 typedef int (*rproc_handle_resources_t)(struct rproc *rproc,
-				struct fw_resource *rsc, int len);
-typedef int (*rproc_handle_resource_t)(struct rproc *rproc,
-				struct fw_resource *rsc);
+				struct resource_table *table, int len);
+typedef int (*rproc_handle_resource_t)(struct rproc *rproc, void *, int avail);
 
 /*
  * This is the IOMMU fault handler we register with the IOMMU API
@@ -281,9 +280,10 @@ rproc_load_segments(struct rproc *rproc, const u8 *elf_data, size_t len)
 }
 
 /**
- * rproc_handle_virtio_hdr() - handle a virtio header resource
+ * rproc_handle_early_vdev() - early handle a virtio header resource
  * @rproc: the remote processor
  * @rsc: the resource descriptor
+ * @avail: size of available data (for sanity checking the image)
  *
  * The existence of this virtio hdr resource entry means that the firmware
  * of this @rproc supports this virtio device.
@@ -291,37 +291,32 @@ rproc_load_segments(struct rproc *rproc, const u8 *elf_data, size_t len)
  * Currently we support only a single virtio device of type VIRTIO_ID_RPMSG,
  * but the plan is to remove this limitation and support any number
  * of virtio devices (and of any type). We'll also add support for dynamically
- * adding (and removing) virtio devices over the rpmsg bus, but small
+ * adding (and removing) virtio devices over the rpmsg bus, but simple
  * firmwares that doesn't want to get involved with rpmsg will be able
- * to simple use the resource table for this.
- *
- * At this point this virtio header entry is rather simple: it just
- * announces the virtio device id and the supported virtio device features.
- * The plan though is to extend this to include the vring information and
- * the virtio config space, too (but first, some resource table overhaul
- * is needed: move from fixed-sized to variable-length TLV entries).
- *
- * For now, the 'flags' member of the resource entry contains the virtio
- * device id, the 'da' member contains the device features, and 'pa' is
- * where we need to store the guest features once negotiation completes.
- * As usual, the 'id' member of this resource contains the index of this
- * resource type (i.e. is this the first virtio hdr entry, the 2nd, ...).
+ * to simply use the resource table for this.
  *
  * Returns 0 on success, or an appropriate error code otherwise
  */
-static int rproc_handle_virtio_hdr(struct rproc *rproc, struct fw_resource *rsc)
+static int rproc_handle_early_vdev(struct rproc *rproc, struct fw_rsc_vdev *rsc,
+								int avail)
 {
 	struct rproc_vdev *rvdev;
 
+	/* make sure resource isn't truncated */
+	if (sizeof(*rsc) > avail) {
+		dev_err(rproc->dev, "vdev rsc is truncated\n");
+		return -EINVAL;
+	}
+
 	/* we only support VIRTIO_ID_RPMSG devices for now */
-	if (rsc->flags != VIRTIO_ID_RPMSG) {
-		dev_warn(rproc->dev, "unsupported vdev: %d\n", rsc->flags);
+	if (rsc->id != VIRTIO_ID_RPMSG) {
+		dev_warn(rproc->dev, "unsupported vdev: %d\n", rsc->id);
 		return -EINVAL;
 	}
 
 	/* we only support a single vdev per rproc for now */
-	if (rsc->id || rproc->rvdev) {
-		dev_warn(rproc->dev, "redundant vdev entry: %s\n", rsc->name);
+	if (rproc->rvdev) {
+		dev_warn(rproc->dev, "redundant vdev entry\n");
 		return -EINVAL;
 	}
 
@@ -330,7 +325,7 @@ static int rproc_handle_virtio_hdr(struct rproc *rproc, struct fw_resource *rsc)
 		return -ENOMEM;
 
 	/* remember the device features */
-	rvdev->dfeatures = rsc->da;
+	rvdev->dfeatures = rsc->dfeatures;
 
 	rproc->rvdev = rvdev;
 	rvdev->rproc = rproc;
@@ -339,9 +334,10 @@ static int rproc_handle_virtio_hdr(struct rproc *rproc, struct fw_resource *rsc)
 }
 
 /**
- * rproc_handle_vring() - handle a vring fw resource
+ * rproc_handle_vdev() - handle a vdev fw resource
  * @rproc: the remote processor
  * @rsc: the vring resource descriptor
+ * @avail: size of available data (for sanity checking the image)
  *
  * This resource entry requires allocation of non-cacheable memory
  * for a virtio vring. Currently we only support two vrings per remote
@@ -360,57 +356,82 @@ static int rproc_handle_virtio_hdr(struct rproc *rproc, struct fw_resource *rsc)
  *
  * Returns 0 on success, or an appropriate error code otherwise
  */
-static int rproc_handle_vring(struct rproc *rproc, struct fw_resource *rsc)
+static int rproc_handle_vdev(struct rproc *rproc, struct fw_rsc_vdev *rsc,
+								int avail)
 {
 	struct device *dev = rproc->dev;
 	struct rproc_vdev *rvdev = rproc->rvdev;
-	dma_addr_t dma;
-	int size, id = rsc->id;
-	void *va;
+	int i;
 
-	/* no vdev is in place ? */
-	if (!rvdev) {
-		dev_err(dev, "vring requested without a virtio dev entry\n");
+	/* make sure resource isn't truncated */
+	if (sizeof(*rsc) + rsc->num_of_vrings * sizeof(struct fw_rsc_vdev_vring)
+			+ rsc->config_len > avail) {
+		dev_err(rproc->dev, "vdev rsc is truncated\n");
 		return -EINVAL;
 	}
 
-	/* the firmware must provide the expected queue size */
-	if (!rsc->len) {
-		dev_err(dev, "missing expected queue size\n");
+	/* make sure reserved bytes are zeroes */
+	if (rsc->reserved[0] || rsc->reserved[1]) {
+		dev_err(dev, "vdev rsc has non zero reserved bytes\n");
 		return -EINVAL;
 	}
 
-	/* we currently support two vrings per rproc (for rx and tx) */
-	if (id >= ARRAY_SIZE(rvdev->vring)) {
-		dev_err(dev, "%s: invalid vring id %d\n", rsc->name, id);
+	dev_dbg(dev, "vdev rsc: id %d, dfeatures %x, cfg len %d, %d vrings\n",
+		rsc->id, rsc->dfeatures, rsc->config_len, rsc->num_of_vrings);
+
+	/* no vdev is in place ? */
+	if (!rvdev) {
+		dev_err(dev, "vring requested without a virtio dev entry\n");
 		return -EINVAL;
 	}
 
-	/* have we already allocated this vring id ? */
-	if (rvdev->vring[id].len) {
-		dev_err(dev, "%s: duplicated id %d\n", rsc->name, id);
+	/* we currently support two vrings per rproc (for rx and tx) */
+	if (rsc->num_of_vrings != ARRAY_SIZE(rvdev->vring)) {
+		dev_err(dev, "too many vrings: %d\n", rsc->num_of_vrings);
 		return -EINVAL;
 	}
 
-	/* actual size of vring (in bytes) */
-	size = PAGE_ALIGN(vring_size(rsc->len, AMP_VRING_ALIGN));
+	/* initialize the vrings */
+	for (i = 0; i < rsc->num_of_vrings; i++) {
+		struct fw_rsc_vdev_vring *vring = &rsc->vring[i];
+		dma_addr_t dma;
+		int size;
+		void *va;
+
+		/* make sure reserved bytes are zeroes */
+		if (vring->reserved) {
+			dev_err(dev, "vring rsc has non zero reserved bytes\n");
+			return -EINVAL;
+		}
 
-	/*
-	 * Allocate non-cacheable memory for the vring. In the future
-	 * this call will also configure the IOMMU for us
-	 */
-	va = dma_alloc_coherent(dev, size, &dma, GFP_KERNEL);
-	if (!va) {
-		dev_err(dev, "dma_alloc_coherent failed\n");
-		return -ENOMEM;
-	}
+		/* the firmware must provide the expected queue size */
+		if (!vring->num) {
+			dev_err(dev, "missing expected queue size\n");
+			/* potential cleanups are taken care of later on */
+			return -EINVAL;
+		}
 
-	dev_dbg(dev, "vring%d: va %p dma %x qsz %d ring size %x\n", id, va,
-					dma, rsc->len, size);
+		/* actual size of vring (in bytes) */
+		size = PAGE_ALIGN(vring_size(vring->num, AMP_VRING_ALIGN));
 
-	rvdev->vring[id].len = rsc->len;
-	rvdev->vring[id].va = va;
-	rvdev->vring[id].dma = dma;
+		/*
+		 * Allocate non-cacheable memory for the vring. In the future
+		 * this call will also configure the IOMMU for us
+		 */
+		va = dma_alloc_coherent(dev, size, &dma, GFP_KERNEL);
+		if (!va) {
+			dev_err(dev, "dma_alloc_coherent failed\n");
+			/* potential cleanups are taken care of later on */
+			return -EINVAL;
+		}
+
+		dev_dbg(dev, "vring%d: va %p dma %x qsz %d ring size %x\n", i,
+						va, dma, vring->num, size);
+
+		rvdev->vring[i].len = vring->num;
+		rvdev->vring[i].va = va;
+		rvdev->vring[i].dma = dma;
+	}
 
 	return 0;
 }
@@ -419,6 +440,7 @@ static int rproc_handle_vring(struct rproc *rproc, struct fw_resource *rsc)
  * rproc_handle_trace() - handle a shared trace buffer resource
  * @rproc: the remote processor
  * @rsc: the trace resource descriptor
+ * @avail: size of available data (for sanity checking the image)
  *
  * In case the remote processor dumps trace logs into memory,
  * export it via debugfs.
@@ -430,13 +452,25 @@ static int rproc_handle_vring(struct rproc *rproc, struct fw_resource *rsc)
  *
  * Returns 0 on success, or an appropriate error code otherwise
  */
-static int rproc_handle_trace(struct rproc *rproc, struct fw_resource *rsc)
+static int rproc_handle_trace(struct rproc *rproc, struct fw_rsc_trace *rsc,
+								int avail)
 {
 	struct rproc_mem_entry *trace;
 	struct device *dev = rproc->dev;
 	void *ptr;
 	char name[15];
 
+	if (sizeof(*rsc) > avail) {
+		dev_err(rproc->dev, "trace rsc is truncated\n");
+		return -EINVAL;
+	}
+
+	/* make sure reserved bytes are zeroes */
+	if (rsc->reserved) {
+		dev_err(dev, "trace rsc has non zero reserved bytes\n");
+		return -EINVAL;
+	}
+
 	/* what's the kernel address of this resource ? */
 	ptr = rproc_da_to_va(rproc, rsc->da, rsc->len);
 	if (!ptr) {
@@ -469,7 +503,7 @@ static int rproc_handle_trace(struct rproc *rproc, struct fw_resource *rsc)
 
 	rproc->num_traces++;
 
-	dev_dbg(dev, "%s added: va %p, da 0x%llx, len 0x%x\n", name, ptr,
+	dev_dbg(dev, "%s added: va %p, da 0x%x, len 0x%x\n", name, ptr,
 						rsc->da, rsc->len);
 
 	return 0;
@@ -479,6 +513,7 @@ static int rproc_handle_trace(struct rproc *rproc, struct fw_resource *rsc)
  * rproc_handle_devmem() - handle devmem resource entry
  * @rproc: remote processor handle
  * @rsc: the devmem resource entry
+ * @avail: size of available data (for sanity checking the image)
  *
  * Remote processors commonly need to access certain on-chip peripherals.
  *
@@ -499,7 +534,8 @@ static int rproc_handle_trace(struct rproc *rproc, struct fw_resource *rsc)
  * and not allow firmwares to request access to physical addresses that
  * are outside those ranges.
  */
-static int rproc_handle_devmem(struct rproc *rproc, struct fw_resource *rsc)
+static int rproc_handle_devmem(struct rproc *rproc, struct fw_rsc_devmem *rsc,
+								int avail)
 {
 	struct rproc_mem_entry *mapping;
 	int ret;
@@ -508,6 +544,17 @@ static int rproc_handle_devmem(struct rproc *rproc, struct fw_resource *rsc)
 	if (!rproc->domain)
 		return -EINVAL;
 
+	if (sizeof(*rsc) > avail) {
+		dev_err(rproc->dev, "devmem rsc is truncated\n");
+		return -EINVAL;
+	}
+
+	/* make sure reserved bytes are zeroes */
+	if (rsc->reserved) {
+		dev_err(rproc->dev, "devmem rsc has non zero reserved bytes\n");
+		return -EINVAL;
+	}
+
 	mapping = kzalloc(sizeof(*mapping), GFP_KERNEL);
 	if (!mapping) {
 		dev_err(rproc->dev, "kzalloc mapping failed\n");
@@ -531,7 +578,7 @@ static int rproc_handle_devmem(struct rproc *rproc, struct fw_resource *rsc)
 	mapping->len = rsc->len;
 	list_add_tail(&mapping->node, &rproc->mappings);
 
-	dev_dbg(rproc->dev, "mapped devmem pa 0x%llx, da 0x%llx, len 0x%x\n",
+	dev_dbg(rproc->dev, "mapped devmem pa 0x%x, da 0x%x, len 0x%x\n",
 					rsc->pa, rsc->da, rsc->len);
 
 	return 0;
@@ -545,6 +592,7 @@ out:
  * rproc_handle_carveout() - handle phys contig memory allocation requests
  * @rproc: rproc handle
  * @rsc: the resource entry
+ * @avail: size of available data (for image validation)
  *
  * This function will handle firmware requests for allocation of physically
  * contiguous memory regions.
@@ -558,7 +606,8 @@ out:
  * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB
  * pressure is important; it may have a substantial impact on performance.
  */
-static int rproc_handle_carveout(struct rproc *rproc, struct fw_resource *rsc)
+static int rproc_handle_carveout(struct rproc *rproc,
+				struct fw_rsc_carveout *rsc, int avail)
 {
 	struct rproc_mem_entry *carveout, *mapping;
 	struct device *dev = rproc->dev;
@@ -566,6 +615,20 @@ static int rproc_handle_carveout(struct rproc *rproc, struct fw_resource *rsc)
 	void *va;
 	int ret;
 
+	if (sizeof(*rsc) > avail) {
+		dev_err(rproc->dev, "carveout rsc is truncated\n");
+		return -EINVAL;
+	}
+
+	/* make sure reserved bytes are zeroes */
+	if (rsc->reserved) {
+		dev_err(dev, "carveout rsc has non zero reserved bytes\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dev, "carveout rsc: da %x, pa %x, len %x, flags %x\n",
+			rsc->da, rsc->pa, rsc->len, rsc->flags);
+
 	mapping = kzalloc(sizeof(*mapping), GFP_KERNEL);
 	if (!mapping) {
 		dev_err(dev, "kzalloc mapping failed\n");
@@ -624,7 +687,7 @@ static int rproc_handle_carveout(struct rproc *rproc, struct fw_resource *rsc)
 		mapping->len = rsc->len;
 		list_add_tail(&mapping->node, &rproc->mappings);
 
-		dev_dbg(dev, "carveout mapped 0x%llx to 0x%x\n", rsc->da, dma);
+		dev_dbg(dev, "carveout mapped 0x%x to 0x%x\n", rsc->da, dma);
 
 		/*
 		 * Some remote processors might need to know the pa
@@ -665,36 +728,44 @@ free_mapping:
  * enum fw_resource_type.
  */
 static rproc_handle_resource_t rproc_handle_rsc[] = {
-	[RSC_CARVEOUT] = rproc_handle_carveout,
-	[RSC_DEVMEM] = rproc_handle_devmem,
-	[RSC_TRACE] = rproc_handle_trace,
-	[RSC_VRING] = rproc_handle_vring,
-	[RSC_VIRTIO_DEV] = NULL, /* handled early upon registration */
+	[RSC_CARVEOUT] = (rproc_handle_resource_t)rproc_handle_carveout,
+	[RSC_DEVMEM] = (rproc_handle_resource_t)rproc_handle_devmem,
+	[RSC_TRACE] = (rproc_handle_resource_t)rproc_handle_trace,
+	[RSC_VDEV] = (rproc_handle_resource_t)rproc_handle_vdev,
 };
 
 /* handle firmware resource entries before booting the remote processor */
 static int
-rproc_handle_boot_rsc(struct rproc *rproc, struct fw_resource *rsc, int len)
+rproc_handle_boot_rsc(struct rproc *rproc, struct resource_table *table, int len)
 {
 	struct device *dev = rproc->dev;
 	rproc_handle_resource_t handler;
-	int ret = 0;
+	int ret = 0, i;
+
+	for (i = 0; i < table->num; i++) {
+		int offset = table->offset[i];
+		struct fw_rsc_hdr *hdr = (void *)table + offset;
+		int avail = len - offset - sizeof(*hdr);
+		void *rsc = (void *)hdr + sizeof(*hdr);
+
+		/* make sure table isn't truncated */
+		if (avail < 0) {
+			dev_err(dev, "rsc table is truncated\n");
+			return -EINVAL;
+		}
 
-	for (; len >= sizeof(*rsc); rsc++, len -= sizeof(*rsc)) {
-		dev_dbg(dev, "rsc: type %d, da 0x%llx, pa 0x%llx, len 0x%x, "
-			"id %d, name %s, flags %x\n", rsc->type, rsc->da,
-			rsc->pa, rsc->len, rsc->id, rsc->name, rsc->flags);
+		dev_dbg(dev, "rsc: type %d\n", hdr->type);
 
-		if (rsc->type >= RSC_LAST) {
-			dev_warn(dev, "unsupported resource %d\n", rsc->type);
+		if (hdr->type >= RSC_LAST) {
+			dev_warn(dev, "unsupported resource %d\n", hdr->type);
 			continue;
 		}
 
-		handler = rproc_handle_rsc[rsc->type];
+		handler = rproc_handle_rsc[hdr->type];
 		if (!handler)
 			continue;
 
-		ret = handler(rproc, rsc);
+		ret = handler(rproc, rsc, avail);
 		if (ret)
 			break;
 	}
@@ -704,18 +775,31 @@ rproc_handle_boot_rsc(struct rproc *rproc, struct fw_resource *rsc, int len)
 
 /* handle firmware resource entries while registering the remote processor */
 static int
-rproc_handle_virtio_rsc(struct rproc *rproc, struct fw_resource *rsc, int len)
+rproc_handle_virtio_rsc(struct rproc *rproc, struct resource_table *table, int len)
 {
 	struct device *dev = rproc->dev;
-	int ret = -ENODEV;
+	int ret = 0, i;
+
+	for (i = 0; i < table->num; i++) {
+		int offset = table->offset[i];
+		struct fw_rsc_hdr *hdr = (void *)table + offset;
+		int avail = len - offset - sizeof(*hdr);
 
-	for (; len >= sizeof(*rsc); rsc++, len -= sizeof(*rsc))
-		if (rsc->type == RSC_VIRTIO_DEV) {
-			dev_dbg(dev, "found vdev %d/%s features %llx\n",
-					rsc->flags, rsc->name, rsc->da);
-			ret = rproc_handle_virtio_hdr(rproc, rsc);
+		/* make sure table isn't truncated */
+		if (avail < 0) {
+			dev_err(dev, "rsc table is truncated\n");
+			return -EINVAL;
+		}
+
+		dev_dbg(dev, "%s: rsc type %d\n", __func__, hdr->type);
+
+		if (hdr->type == RSC_VDEV) {
+			struct fw_rsc_vdev *vrsc =
+					(struct fw_rsc_vdev *)hdr->data;
+			ret = rproc_handle_early_vdev(rproc, vrsc, avail);
 			break;
 		}
+	}
 
 	return ret;
 }
@@ -744,7 +828,9 @@ static int rproc_handle_resources(struct rproc *rproc, const u8 *elf_data,
 	struct elf32_hdr *ehdr;
 	struct elf32_shdr *shdr;
 	const char *name_table;
+	struct device *dev = rproc->dev;
 	int i, ret = -EINVAL;
+	struct resource_table *table;
 
 	ehdr = (struct elf32_hdr *)elf_data;
 	shdr = (struct elf32_shdr *)(elf_data + ehdr->e_shoff);
@@ -752,21 +838,47 @@ static int rproc_handle_resources(struct rproc *rproc, const u8 *elf_data,
 
 	/* look for the resource table and handle it */
 	for (i = 0; i < ehdr->e_shnum; i++, shdr++) {
-		if (!strcmp(name_table + shdr->sh_name, ".resource_table")) {
-			struct fw_resource *table = (struct fw_resource *)
-						(elf_data + shdr->sh_offset);
+		int size = shdr->sh_size;
+		int offset = shdr->sh_offset;
 
-			if (shdr->sh_offset + shdr->sh_size > len) {
-				dev_err(rproc->dev,
-					"truncated fw: need 0x%x avail 0x%x\n",
-					shdr->sh_offset + shdr->sh_size, len);
-				ret = -EINVAL;
-			}
+		if (strcmp(name_table + shdr->sh_name, ".resource_table"))
+			continue;
 
-			ret = handler(rproc, table, shdr->sh_size);
+		table = (struct resource_table *)(elf_data + offset);
 
-			break;
+		/* make sure we have the entire table */
+		if (offset + size > len) {
+			dev_err(dev, "resource table truncated\n");
+			return -EINVAL;
+		}
+
+		/* make sure table has at least the header */
+		if (sizeof(struct resource_table) > size) {
+			dev_err(dev, "header-less resource table\n");
+			return -EINVAL;
 		}
+
+		/* we don't support any version beyond the first */
+		if (table->ver != 1) {
+			dev_err(dev, "unsupported fw ver: %d\n", table->ver);
+			return -EINVAL;
+		}
+
+		/* make sure reserved bytes are zeroes */
+		if (table->reserved[0] || table->reserved[1]) {
+			dev_err(dev, "non zero reserved bytes\n");
+			return -EINVAL;
+		}
+
+		/* make sure the offsets array isn't truncated */
+		if (table->num * sizeof(table->offset[0]) +
+				sizeof(struct resource_table) > size) {
+			dev_err(dev, "resource table incomplete\n");
+			return -EINVAL;
+		}
+
+		ret = handler(rproc, table, shdr->sh_size);
+		break;
 	}
 
 	return ret;
@@ -980,7 +1092,7 @@ static void rproc_fw_config_virtio(const struct firmware *fw, void *context)
 	if (rproc_fw_sanity_check(rproc, fw) < 0)
 		goto out;
 
-	/* does the fw supports any virtio devices ? */
+	/* does the fw support any virtio devices ? */
 	ret = rproc_handle_resources(rproc, fw->data, fw->size,
 						rproc_handle_virtio_rsc);
 	if (ret) {
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index ada4cb0..6040f83 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -50,39 +50,51 @@
 #define AMP_VRING_ALIGN	(4096)
 
 /**
- * struct fw_resource - describes an entry from the resource section
- * @type: resource type
- * @id: index number of the resource
- * @da: device address of the resource
- * @pa: physical address of the resource
- * @len: size, in bytes, of the resource
- * @flags: properties of the resource, e.g. iommu protection required
- * @reserved: must be 0 atm
- * @name: name of resource
+ * struct resource_table - firmware resource table header
+ * @ver: version number
+ * @num: number of resource entries
+ * @reserved: reserved (must be zero)
+ * @offset: array of offsets pointing at the various resource entries
  *
- * The remote processor firmware should contain a "resource table":
- * array of 'struct fw_resource' entries.
+ * A resource table is essentially a list of system resources required
+ * by the remote processor. It may also include configuration entries.
+ * If needed, the remote processor firmware should contain this table
+ * as a dedicated ".resource_table" ELF section.
  *
  * Some resources entries are mere announcements, where the host is informed
  * of specific remoteproc configuration. Other entries require the host to
- * do something (e.g. reserve a requested resource) and possibly also reply
- * by overwriting a member inside 'struct fw_resource' with info about the
- * allocated resource.
- *
- * Different resource entries use different members of this struct,
- * with different meanings. This is pretty limiting and error-prone,
- * so the plan is to move to variable-length TLV-based resource entries,
- * where each resource type will have its own structure.
+ * do something (e.g. allocate a system resource). Sometimes a negotiation
+ * is expected, where the firmware requests a resource, and once allocated,
+ * the host should provide back its details (e.g. address of an allocated
+ * memory region).
+ *
+ * The header of the resource table, as expressed by this structure,
+ * contains a version number (should we need to change this format in the
+ * future), the number of available resource entries, and their offsets
+ * in the table.
+ *
+ * Immediately following this header are the resource entries themselves,
+ * each of which begins with a resource entry header (as described below).
+ */
+struct resource_table {
+	u32 ver;
+	u32 num;
+	u32 reserved[2];
+	u32 offset[0];
+} __packed;
+
+/**
+ * struct fw_rsc_hdr - firmware resource entry header
+ * @type: resource type
+ * @data: resource data
+ *
+ * Every resource entry begins with a 'struct fw_rsc_hdr' header providing
+ * its @type. The content of the entry itself will immediately follow
+ * this header, and it should be parsed according to the resource type.
  */
-struct fw_resource {
+struct fw_rsc_hdr {
 	u32 type;
-	u32 id;
-	u64 da;
-	u64 pa;
-	u32 len;
-	u32 flags;
-	u8 reserved[16];
-	u8 name[48];
+	u8 data[0];
 } __packed;
 
 /**
@@ -92,30 +104,13 @@ struct fw_resource {
  *		    memory region.
  * @RSC_DEVMEM:     request to iommu_map a memory-based peripheral.
  * @RSC_TRACE:	    announces the availability of a trace buffer into which
- *		    the remote processor will be writing logs. In this case,
- *		    'da' indicates the device address where logs are written to,
- *		    and 'len' is the size of the trace buffer.
- * @RSC_VRING:	    request for allocation of a virtio vring (address should
- *		    be indicated in 'da', and 'len' should contain the number
- *		    of buffers supported by the vring).
- * @RSC_VIRTIO_DEV: this entry declares about support for a virtio device,
- *		    and serves as the virtio header. 'da' holds the
- *		    the virtio device features, 'pa' holds the virtio guest
- *		    features, 'len' holds the virtio status, and 'flags' holds
- *		    the virtio id (currently only VIRTIO_ID_RPMSG is supported).
+ *		    the remote processor will be writing logs.
+ * @RSC_VDEV:       declare support for a virtio device, and serve as its
+ *		    virtio header.
  * @RSC_LAST:       just keep this one at the end
  *
- * Most of the resource entries share the basic idea of address/length
- * negotiation with the host: the firmware usually asks (on behalf of the
- * remote processor that will soon be booted with it) for memory
- * of size 'len' bytes, and the host needs to allocate it and provide
- * the device/physical address (when relevant) in 'da'/'pa' respectively.
- *
- * If the firmware is compiled with hard coded device addresses, and
- * can't handle dynamically allocated 'da' values, then the 'da' field
- * will contain the expected device addresses (today we actually only support
- * this scheme, as there aren't yet any use cases for dynamically allocated
- * device addresses).
+ * For more details regarding a specific resource type, please see its
+ * dedicated structure below.
  *
  * Please note that these values are used as indices to the rproc_handle_rsc
  * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to
@@ -126,11 +121,197 @@ enum fw_resource_type {
 	RSC_CARVEOUT	= 0,
 	RSC_DEVMEM	= 1,
 	RSC_TRACE	= 2,
-	RSC_VRING	= 3,
-	RSC_VIRTIO_DEV	= 4,
-	RSC_LAST	= 5,
+	RSC_VDEV	= 3,
+	RSC_LAST	= 4,
 };
 
+#define FW_RSC_ADDR_ANY (0xFFFFFFFFFFFFFFFF)
+
+/**
+ * struct fw_rsc_carveout - physically contiguous memory request
+ * @da: device address
+ * @pa: physical address
+ * @len: length (in bytes)
+ * @flags: iommu protection flags
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the requested memory region
+ *
+ * This resource entry requests the host to allocate a physically contiguous
+ * memory region.
+ *
+ * These request entries should precede other firmware resource entries,
+ * as other entries might request placing other data objects inside
+ * these memory regions (e.g. data/code segments, trace resource entries, ...).
+ *
+ * Allocating memory this way helps utilizing the reserved physical memory
+ * (e.g. CMA) more efficiently, and also minimizes the number of TLB entries
+ * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB
+ * pressure is important; it may have a substantial impact on performance.
+ *
+ * If the firmware is compiled with static addresses, then @da should specify
+ * the expected device address of this memory region. If @da is set to
+ * FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then
+ * overwrite @da with the dynamically allocated address.
+ *
+ * We will always use @da to negotiate the device addresses, even if it
+ * isn't using an iommu. In that case, though, it will obviously contain
+ * physical addresses.
+ *
+ * Some remote processors needs to know the allocated physical address
+ * even if they do use an iommu. This is needed, e.g., if they control
+ * hardware accelerators which access the physical memory directly (this
+ * is the case with OMAP4 for instance). In that case, the host will
+ * overwrite @pa with the dynamically allocated physical address.
+ * Generally we don't want to expose physical addresses if we don't have to
+ * (remote processors are generally _not_ trusted), so we might want to
+ * change this to happen _only_ when explicitly required by the hardware.
+ *
+ * @flags is used to provide IOMMU protection flags, and @name should
+ * (optionally) contain a human readable name of this carveout region
+ * (mainly for debugging purposes).
+ */
+struct fw_rsc_carveout {
+	u32 da;
+	u32 pa;
+	u32 len;
+	u32 flags;
+	u32 reserved;
+	u8 name[32];
+} __packed;
+
+/**
+ * struct fw_rsc_devmem - iommu mapping request
+ * @da: device address
+ * @pa: physical address
+ * @len: length (in bytes)
+ * @flags: iommu protection flags
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the requested region to be mapped
+ *
+ * This resource entry requests the host to iommu map a physically contiguous
+ * memory region. This is needed in case the remote processor requires
+ * access to certain memory-based peripherals; _never_ use it to access
+ * regular memory.
+ *
+ * This is obviously only needed if the remote processor is accessing memory
+ * via an iommu.
+ *
+ * @da should specify the required device address, @pa should specify
+ * the physical address we want to map, @len should specify the size of
+ * the mapping and @flags is the IOMMU protection flags. As always, @name may
+ * (optionally) contain a human readable name of this mapping (mainly for
+ * debugging purposes).
+ *
+ * Note: at this point we just "trust" those devmem entries to contain valid
+ * physical addresses, but this isn't safe and will be changed: eventually we
+ * want remoteproc implementations to provide us ranges of physical addresses
+ * the firmware is allowed to request, and not allow firmwares to request
+ * access to physical addresses that are outside those ranges.
+ */
+struct fw_rsc_devmem {
+	u32 da;
+	u32 pa;
+	u32 len;
+	u32 flags;
+	u32 reserved;
+	u8 name[32];
+} __packed;
+
+/**
+ * struct fw_rsc_trace - trace buffer declaration
+ * @da: device address
+ * @len: length (in bytes)
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the trace buffer
+ *
+ * This resource entry provides the host information about a trace buffer
+ * into which the remote processor will write log messages.
+ *
+ * @da specifies the device address of the buffer, @len specifies
+ * its size, and @name may contain a human readable name of the trace buffer.
+ *
+ * After booting the remote processor, the trace buffers are exposed to the
+ * user via debugfs entries (called trace0, trace1, etc..).
+ */
+struct fw_rsc_trace {
+	u32 da;
+	u32 len;
+	u32 reserved;
+	u8 name[32];
+} __packed;
+
+/**
+ * struct fw_rsc_vdev_vring - vring descriptor entry
+ * @da: device address
+ * @align: the alignment between the consumer and producer parts of the vring
+ * @num: num of buffers supported by this vring (must be power of two)
+ * @notifyid is a unique rproc-wide notify index for this vring. This notify
+ * index is used when kicking a remote processor, to let it know that this
+ * vring is triggered.
+ * @reserved: reserved (must be zero)
+ *
+ * This descriptor is not a resource entry by itself; it is part of the
+ * vdev resource type (see below).
+ *
+ * Note that @da should either contain the device address where
+ * the remote processor is expecting the vring, or indicate that
+ * dynamically allocation of the vring's device address is supported.
+ */
+struct fw_rsc_vdev_vring {
+	u32 da;
+	u32 align;
+	u32 num;
+	u32 notifyid;
+	u32 reserved;
+} __packed;
+
+/**
+ * struct fw_rsc_vdev - virtio device header
+ * @id: virtio device id (as in virtio_ids.h)
+ * @notifyid is a unique rproc-wide notify index for this vdev. This notify
+ * index is used when kicking a remote processor, to let it know that the
+ * status/features of this vdev have changes.
+ * @dfeatures specifies the virtio device features supported by the firmware
+ * @gfeatures is a place holder used by the host to write back the
+ * negotiated features that are supported by both sides.
+ * @config_len is the size of the virtio config space of this vdev. The config
+ * space lies in the resource table immediate after this vdev header.
+ * @status is a place holder where the host will indicate its virtio progress.
+ * @num_of_vrings indicates how many vrings are described in this vdev header
+ * @reserved: reserved (must be zero)
+ * @vring is an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring'.
+ *
+ * This resource is a virtio device header: it provides information about
+ * the vdev, and is then used by the host and its peer remote processors
+ * to negotiate and share certain virtio properties.
+ *
+ * By providing this resource entry, the firmware essentially asks remoteproc
+ * to statically allocate a vdev upon registration of the rproc (dynamic vdev
+ * allocation is not yet supported).
+ *
+ * Note: unlike virtualization systems, the term 'host' here means
+ * the Linux side which is running remoteproc to control the remote
+ * processors. We use the name 'gfeatures' to comply with virtio's terms,
+ * though there isn't really any virtualized guest OS here: it's the host
+ * which is responsible for negotiating the final features.
+ * Yeah, it's a bit confusing.
+ *
+ * Note: immediately following this structure is the virtio config space for
+ * this vdev (which is specific to the vdev; for more info, read the virtio
+ * spec). the size of the config space is specified by @config_len.
+ */
+struct fw_rsc_vdev {
+	u32 id;
+	u32 notifyid;
+	u32 dfeatures;
+	u32 gfeatures;
+	u32 config_len;
+	u8 status;
+	u8 num_of_vrings;
+	u8 reserved[2];
+	struct fw_rsc_vdev_vring vring[0];
+} __packed;
+
 /**
  * struct rproc_mem_entry - memory entry descriptor
  * @va:	virtual address
@@ -144,7 +325,7 @@ struct rproc_mem_entry {
 	void *va;
 	dma_addr_t dma;
 	int len;
-	u64 da;
+	u32 da;
 	void *priv;
 	struct list_head node;
 };
@@ -226,7 +407,7 @@ struct rproc {
 	struct list_head carveouts;
 	struct list_head mappings;
 	struct completion firmware_loading_complete;
-	u64 bootaddr;
+	u32 bootaddr;
 	struct rproc_vdev *rvdev;
 };
 
-- 
1.7.5.4



From ohad at wizery.com  Thu Mar  1 03:11:32 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Thu,  1 Mar 2012 10:11:32 +0200
Subject: [PATCH 2/7] remoteproc: remoteproc_rpmsg -> remoteproc_virtio
In-Reply-To: <1330589497-4139-1-git-send-email-ohad@wizery.com>
References: <1330589497-4139-1-git-send-email-ohad@wizery.com>
Message-ID: <1330589497-4139-3-git-send-email-ohad@wizery.com>

At this point remoteproc can only register a single VIRTIO_ID_RPMSG virtio
device.

This limitation is going away soon: remoteproc is getting support for
registering any number of virtio devices and of any type (as
published by the firmware of the remote processor).

Rename remoteproc_rpmsg.c to remoteproc_virtio.c in preparation of
this generalization work.

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Cc: Brian Swetland <swetland at google.com>
Cc: Iliyan Malchev <malchev at google.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rusty Russell <rusty at rustcorp.com.au>
Cc: Mark Grosen <mgrosen at ti.com>
Cc: John Williams <john.williams at petalogix.com>
Cc: Michal Simek <monstr at monstr.eu>
Cc: Loic PALLARDY <loic.pallardy at stericsson.com>
Cc: Ludovic BARRE <ludovic.barre at stericsson.com>
Cc: Omar Ramirez Luna <omar.luna at linaro.org>
Cc: Guzman Lugo Fernando <fernando.lugo at ti.com>
Cc: Anna Suman <s-anna at ti.com>
Cc: Clark Rob <rob at ti.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: David Brown <davidb at codeaurora.org>
Cc: Kieran Bingham <kieranbingham at gmail.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 drivers/remoteproc/Makefile                        |    2 +-
 .../{remoteproc_rpmsg.c => remoteproc_virtio.c}    |    0
 2 files changed, 1 insertions(+), 1 deletions(-)
 rename drivers/remoteproc/{remoteproc_rpmsg.c => remoteproc_virtio.c} (100%)

diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index df0897f..5445d9b 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -5,5 +5,5 @@
 obj-$(CONFIG_REMOTEPROC)		+= remoteproc.o
 remoteproc-y				:= remoteproc_core.o
 remoteproc-y				+= remoteproc_debugfs.o
-remoteproc-y				+= remoteproc_rpmsg.o
+remoteproc-y				+= remoteproc_virtio.o
 obj-$(CONFIG_OMAP_REMOTEPROC)		+= omap_remoteproc.o
diff --git a/drivers/remoteproc/remoteproc_rpmsg.c b/drivers/remoteproc/remoteproc_virtio.c
similarity index 100%
rename from drivers/remoteproc/remoteproc_rpmsg.c
rename to drivers/remoteproc/remoteproc_virtio.c
-- 
1.7.5.4



From ohad at wizery.com  Thu Mar  1 03:11:33 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Thu,  1 Mar 2012 10:11:33 +0200
Subject: [PATCH 3/7] remoteproc: safer boot/shutdown order
In-Reply-To: <1330589497-4139-1-git-send-email-ohad@wizery.com>
References: <1330589497-4139-1-git-send-email-ohad@wizery.com>
Message-ID: <1330589497-4139-4-git-send-email-ohad@wizery.com>

Boot the remote processor only after setting up the virtqueues,
and shut it down before deleting them.

Remote processors should obey virtio status changes, and
therefore not manipulate/trigger the virtqueues while the virtio
driver isn't ready, but it's just safer not to rely on that
(plus a vq access might already be inflight while a vdev
status is changed).

We also don't have yet status change notifications, but that's
a temporary limitation.

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Cc: Brian Swetland <swetland at google.com>
Cc: Iliyan Malchev <malchev at google.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rusty Russell <rusty at rustcorp.com.au>
Cc: Mark Grosen <mgrosen at ti.com>
Cc: John Williams <john.williams at petalogix.com>
Cc: Michal Simek <monstr at monstr.eu>
Cc: Loic PALLARDY <loic.pallardy at stericsson.com>
Cc: Ludovic BARRE <ludovic.barre at stericsson.com>
Cc: Omar Ramirez Luna <omar.luna at linaro.org>
Cc: Guzman Lugo Fernando <fernando.lugo at ti.com>
Cc: Anna Suman <s-anna at ti.com>
Cc: Clark Rob <rob at ti.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: David Brown <davidb at codeaurora.org>
Cc: Kieran Bingham <kieranbingham at gmail.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 drivers/remoteproc/remoteproc_virtio.c |   20 ++++++++++----------
 1 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/remoteproc/remoteproc_virtio.c b/drivers/remoteproc/remoteproc_virtio.c
index 4f73e81..78d8527 100644
--- a/drivers/remoteproc/remoteproc_virtio.c
+++ b/drivers/remoteproc/remoteproc_virtio.c
@@ -123,14 +123,14 @@ static void rproc_virtio_del_vqs(struct virtio_device *vdev)
 	struct virtqueue *vq, *n;
 	struct rproc *rproc = vdev_to_rproc(vdev);
 
+	/* power down the remote processor before deleting vqs */
+	rproc_shutdown(rproc);
+
 	list_for_each_entry_safe(vq, n, &vdev->vqs, list) {
 		struct rproc_virtio_vq_info *rpvq = vq->priv;
 		vring_del_virtqueue(vq);
 		kfree(rpvq);
 	}
-
-	/* power down the remote processor */
-	rproc_shutdown(rproc);
 }
 
 static int rproc_virtio_find_vqs(struct virtio_device *vdev, unsigned nvqs,
@@ -145,13 +145,6 @@ static int rproc_virtio_find_vqs(struct virtio_device *vdev, unsigned nvqs,
 	if (nvqs != 2)
 		return -EINVAL;
 
-	/* boot the remote processor */
-	ret = rproc_boot(rproc);
-	if (ret) {
-		dev_err(rproc->dev, "rproc_boot() failed %d\n", ret);
-		goto error;
-	}
-
 	for (i = 0; i < nvqs; ++i) {
 		vqs[i] = rp_find_vq(vdev, i, callbacks[i], names[i]);
 		if (IS_ERR(vqs[i])) {
@@ -160,6 +153,13 @@ static int rproc_virtio_find_vqs(struct virtio_device *vdev, unsigned nvqs,
 		}
 	}
 
+	/* now that the vqs are all set, boot the remote processor */
+	ret = rproc_boot(rproc);
+	if (ret) {
+		dev_err(rproc->dev, "rproc_boot() failed %d\n", ret);
+		goto error;
+	}
+
 	return 0;
 
 error:
-- 
1.7.5.4



From ohad at wizery.com  Thu Mar  1 03:11:34 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Thu,  1 Mar 2012 10:11:34 +0200
Subject: [PATCH 4/7] remoteproc: remove the single rpmsg vdev limitation
In-Reply-To: <1330589497-4139-1-git-send-email-ohad@wizery.com>
References: <1330589497-4139-1-git-send-email-ohad@wizery.com>
Message-ID: <1330589497-4139-5-git-send-email-ohad@wizery.com>

Now that the resource table supports publishing a virtio device
in a single resource entry, firmware images can start supporting
more than a single vdev.

This patch removes the single vdev limitation of the remoteproc
framework so multi-vdev firmwares can be leveraged: VDEV resource
entries are parsed when the rproc is registered, and as a result
their vrings are set up and the virtio devices are registered
(and they go away when the rproc goes away).

Moreover, we no longer only support VIRTIO_ID_RPMSG vdevs; any
virtio device type goes now. As a result, there's no more any
rpmsg-specific APIs or code in remoteproc: it all becomes generic
virtio handling.

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Cc: Brian Swetland <swetland at google.com>
Cc: Iliyan Malchev <malchev at google.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rusty Russell <rusty at rustcorp.com.au>
Cc: Mark Grosen <mgrosen at ti.com>
Cc: John Williams <john.williams at petalogix.com>
Cc: Michal Simek <monstr at monstr.eu>
Cc: Loic PALLARDY <loic.pallardy at stericsson.com>
Cc: Ludovic BARRE <ludovic.barre at stericsson.com>
Cc: Omar Ramirez Luna <omar.luna at linaro.org>
Cc: Guzman Lugo Fernando <fernando.lugo at ti.com>
Cc: Anna Suman <s-anna at ti.com>
Cc: Clark Rob <rob at ti.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: David Brown <davidb at codeaurora.org>
Cc: Kieran Bingham <kieranbingham at gmail.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 Documentation/remoteproc.txt             |    9 +-
 drivers/remoteproc/remoteproc_core.c     |  292 +++++++++++++++---------------
 drivers/remoteproc/remoteproc_internal.h |    6 +-
 drivers/remoteproc/remoteproc_virtio.c   |  140 +++++++--------
 include/linux/remoteproc.h               |   41 ++++-
 5 files changed, 260 insertions(+), 228 deletions(-)

diff --git a/Documentation/remoteproc.txt b/Documentation/remoteproc.txt
index 07057ca..70a048c 100644
--- a/Documentation/remoteproc.txt
+++ b/Documentation/remoteproc.txt
@@ -20,6 +20,11 @@ platform-specific remoteproc drivers only need to provide a few low-level
 handlers, and then all rpmsg drivers will then just work
 (for more information about the virtio-based rpmsg bus and its drivers,
 please read Documentation/rpmsg.txt).
+Registration of other types of virtio devices is now also possible. Firmwares
+just need to publish what kind of virtio devices do they support, and then
+remoteproc will add those devices. This makes it possible to reuse the
+existing virtio drivers with remote processor backends at a minimal development
+cost.
 
 2. User API
 
@@ -136,8 +141,6 @@ int dummy_rproc_example(struct rproc *my_rproc)
       If found, those virtio devices will be created and added, so as a result
       of registering this remote processor, additional virtio drivers might get
       probed.
-      Currently, though, we only support a single RPMSG virtio vdev per remote
-      processor.
 
   int rproc_unregister(struct rproc *rproc)
     - Unregister a remote processor, and decrement its refcount.
@@ -174,7 +177,7 @@ struct rproc_ops {
 };
 
 Every remoteproc implementation should at least provide the ->start and ->stop
-handlers. If rpmsg functionality is also desired, then the ->kick handler
+handlers. If rpmsg/virtio functionality is also desired, then the ->kick handler
 should be provided as well.
 
 The ->start() handler takes an rproc handle and should then power on the
diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index 1034845..ca02f12 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -52,8 +52,8 @@ static void klist_rproc_put(struct klist_node *n);
  * We need this in order to support name-based lookups (needed by the
  * rproc_get_by_name()).
  *
- * That said, we don't use rproc_get_by_name() anymore within the rpmsg
- * framework. The use cases that do require its existence should be
+ * That said, we don't use rproc_get_by_name() at this point.
+ * The use cases that do require its existence should be
  * scrutinized, and hopefully migrated to rproc_boot() using device-based
  * binding.
  *
@@ -279,80 +279,112 @@ rproc_load_segments(struct rproc *rproc, const u8 *elf_data, size_t len)
 	return ret;
 }
 
-/**
- * rproc_handle_early_vdev() - early handle a virtio header resource
- * @rproc: the remote processor
- * @rsc: the resource descriptor
- * @avail: size of available data (for sanity checking the image)
- *
- * The existence of this virtio hdr resource entry means that the firmware
- * of this @rproc supports this virtio device.
- *
- * Currently we support only a single virtio device of type VIRTIO_ID_RPMSG,
- * but the plan is to remove this limitation and support any number
- * of virtio devices (and of any type). We'll also add support for dynamically
- * adding (and removing) virtio devices over the rpmsg bus, but simple
- * firmwares that doesn't want to get involved with rpmsg will be able
- * to simply use the resource table for this.
- *
- * Returns 0 on success, or an appropriate error code otherwise
- */
-static int rproc_handle_early_vdev(struct rproc *rproc, struct fw_rsc_vdev *rsc,
-								int avail)
+static int
+__rproc_handle_vring(struct rproc_vdev *rvdev, struct fw_rsc_vdev *rsc, int i)
 {
-	struct rproc_vdev *rvdev;
+	struct rproc *rproc = rvdev->rproc;
+	struct device *dev = rproc->dev;
+	struct fw_rsc_vdev_vring *vring = &rsc->vring[i];
+	dma_addr_t dma;
+	void *va;
+	int ret, size, notifyid;
 
-	/* make sure resource isn't truncated */
-	if (sizeof(*rsc) > avail) {
-		dev_err(rproc->dev, "vdev rsc is truncated\n");
+	dev_dbg(dev, "vdev rsc: vring%d: da %x, qsz %d, align %d\n",
+				i, vring->da, vring->num, vring->align);
+
+	/* make sure reserved bytes are zeroes */
+	if (vring->reserved) {
+		dev_err(dev, "vring rsc has non zero reserved bytes\n");
 		return -EINVAL;
 	}
 
-	/* we only support VIRTIO_ID_RPMSG devices for now */
-	if (rsc->id != VIRTIO_ID_RPMSG) {
-		dev_warn(rproc->dev, "unsupported vdev: %d\n", rsc->id);
+	/* the firmware must provide the expected queue size */
+	if (!vring->num) {
+		dev_err(dev, "invalid qsz (%d)\n", vring->num);
 		return -EINVAL;
 	}
 
-	/* we only support a single vdev per rproc for now */
-	if (rproc->rvdev) {
-		dev_warn(rproc->dev, "redundant vdev entry\n");
+	/* actual size of vring (in bytes) */
+	size = PAGE_ALIGN(vring_size(vring->num, AMP_VRING_ALIGN));
+
+	if (!idr_pre_get(&rproc->notifyids, GFP_KERNEL)) {
+		dev_err(dev, "idr_pre_get failed\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * Allocate non-cacheable memory for the vring. In the future
+	 * this call will also configure the IOMMU for us
+	 */
+	va = dma_alloc_coherent(dev, size, &dma, GFP_KERNEL);
+	if (!va) {
+		dev_err(dev, "dma_alloc_coherent failed\n");
 		return -EINVAL;
 	}
 
-	rvdev = kzalloc(sizeof(struct rproc_vdev), GFP_KERNEL);
-	if (!rvdev)
-		return -ENOMEM;
+	/* assign an rproc-wide unique index for this vring */
+	/* TODO: assign a notifyid for rvdev updates as well */
+	ret = idr_get_new(&rproc->notifyids, &rvdev->vring[i], &notifyid);
+	if (ret) {
+		dev_err(dev, "idr_get_new failed: %d\n", ret);
+		dma_free_coherent(dev, size, va, dma);
+		return ret;
+	}
 
-	/* remember the device features */
-	rvdev->dfeatures = rsc->dfeatures;
+	/* let the rproc know the da and notifyid of this vring */
+	/* TODO: expose this to remote processor */
+	vring->da = dma;
+	vring->notifyid = notifyid;
 
-	rproc->rvdev = rvdev;
-	rvdev->rproc = rproc;
+	dev_dbg(dev, "vring%d: va %p dma %x size %x idr %d\n", i, va,
+					dma, size, notifyid);
+
+	rvdev->vring[i].len = vring->num;
+	rvdev->vring[i].va = va;
+	rvdev->vring[i].dma = dma;
+	rvdev->vring[i].notifyid = notifyid;
+	rvdev->vring[i].rvdev = rvdev;
 
 	return 0;
 }
 
+static void __rproc_free_vrings(struct rproc_vdev *rvdev, int i)
+{
+	struct rproc *rproc = rvdev->rproc;
+
+	for (i--; i > 0; i--) {
+		struct rproc_vring *rvring = &rvdev->vring[i];
+		int size = PAGE_ALIGN(vring_size(rvring->len, AMP_VRING_ALIGN));
+
+		dma_free_coherent(rproc->dev, size, rvring->va, rvring->dma);
+		idr_remove(&rproc->notifyids, rvring->notifyid);
+	}
+}
+
 /**
  * rproc_handle_vdev() - handle a vdev fw resource
  * @rproc: the remote processor
  * @rsc: the vring resource descriptor
  * @avail: size of available data (for sanity checking the image)
  *
- * This resource entry requires allocation of non-cacheable memory
- * for a virtio vring. Currently we only support two vrings per remote
- * processor, required for the virtio rpmsg device.
- *
- * The 'len' member of @rsc should contain the number of buffers this vring
- * support and 'da' should either contain the device address where
- * the remote processor is expecting the vring, or indicate that
- * dynamically allocation of the vring's device address is supported.
- *
- * Note: 'da' is currently not handled. This will be revised when the generic
- * iommu-based DMA API will arrive, or a dynanic & non-iommu use case show
- * up. Meanwhile, statically-addressed iommu-based images should use
- * RSC_DEVMEM resource entries to map their require 'da' to the physical
- * address of their base CMA region.
+ * This resource entry requests the host to statically register a virtio
+ * device (vdev), and setup everything needed to support it. It contains
+ * everything needed to make it possible: the virtio device id, virtio
+ * device features, vrings information, virtio config space, etc...
+ *
+ * Before registering the vdev, the vrings are allocated from non-cacheable
+ * physically contiguous memory. Currently we only support two vrings per
+ * remote processor (temporary limitation). We might also want to consider
+ * doing the vring allocation only later when ->find_vqs() is invoked, and
+ * then release them upon ->del_vqs().
+ *
+ * Note: @da is currently not really handled correctly: we dynamically
+ * allocate it using the DMA API, ignoring requested hard coded addresses,
+ * and we don't take care of any required IOMMU programming. This is all
+ * going to be taken care of when the generic iommu-based DMA API will be
+ * merged. Meanwhile, statically-addressed iommu-based firmware images should
+ * use RSC_DEVMEM resource entries to map their required @da to the physical
+ * address of their base CMA region (ouch, hacky!).
  *
  * Returns 0 on success, or an appropriate error code otherwise
  */
@@ -360,8 +392,8 @@ static int rproc_handle_vdev(struct rproc *rproc, struct fw_rsc_vdev *rsc,
 								int avail)
 {
 	struct device *dev = rproc->dev;
-	struct rproc_vdev *rvdev = rproc->rvdev;
-	int i;
+	struct rproc_vdev *rvdev;
+	int i, ret;
 
 	/* make sure resource isn't truncated */
 	if (sizeof(*rsc) + rsc->num_of_vrings * sizeof(struct fw_rsc_vdev_vring)
@@ -379,61 +411,41 @@ static int rproc_handle_vdev(struct rproc *rproc, struct fw_rsc_vdev *rsc,
 	dev_dbg(dev, "vdev rsc: id %d, dfeatures %x, cfg len %d, %d vrings\n",
 		rsc->id, rsc->dfeatures, rsc->config_len, rsc->num_of_vrings);
 
-	/* no vdev is in place ? */
-	if (!rvdev) {
-		dev_err(dev, "vring requested without a virtio dev entry\n");
-		return -EINVAL;
-	}
-
-	/* we currently support two vrings per rproc (for rx and tx) */
-	if (rsc->num_of_vrings != ARRAY_SIZE(rvdev->vring)) {
+	/* we currently support only two vrings per rvdev */
+	if (rsc->num_of_vrings > ARRAY_SIZE(rvdev->vring)) {
 		dev_err(dev, "too many vrings: %d\n", rsc->num_of_vrings);
 		return -EINVAL;
 	}
 
-	/* initialize the vrings */
-	for (i = 0; i < rsc->num_of_vrings; i++) {
-		struct fw_rsc_vdev_vring *vring = &rsc->vring[i];
-		dma_addr_t dma;
-		int size;
-		void *va;
-
-		/* make sure reserved bytes are zeroes */
-		if (vring->reserved) {
-			dev_err(dev, "vring rsc has non zero reserved bytes\n");
-			return -EINVAL;
-		}
+	rvdev = kzalloc(sizeof(struct rproc_vdev), GFP_KERNEL);
+	if (!rvdev)
+		return -ENOMEM;
 
-		/* the firmware must provide the expected queue size */
-		if (!vring->num) {
-			dev_err(dev, "missing expected queue size\n");
-			/* potential cleanups are taken care of later on */
-			return -EINVAL;
-		}
+	rvdev->rproc = rproc;
 
-		/* actual size of vring (in bytes) */
-		size = PAGE_ALIGN(vring_size(vring->num, AMP_VRING_ALIGN));
+	/* allocate the vrings */
+	for (i = 0; i < rsc->num_of_vrings; i++) {
+		ret = __rproc_handle_vring(rvdev, rsc, i);
+		if (ret)
+			goto free_vrings;
+	}
 
-		/*
-		 * Allocate non-cacheable memory for the vring. In the future
-		 * this call will also configure the IOMMU for us
-		 */
-		va = dma_alloc_coherent(dev, size, &dma, GFP_KERNEL);
-		if (!va) {
-			dev_err(dev, "dma_alloc_coherent failed\n");
-			/* potential cleanups are taken care of later on */
-			return -EINVAL;
-		}
+	/* remember the device features */
+	rvdev->dfeatures = rsc->dfeatures;
 
-		dev_dbg(dev, "vring%d: va %p dma %x qsz %d ring size %x\n", i,
-						va, dma, vring->num, size);
+	list_add_tail(&rvdev->node, &rproc->rvdevs);
 
-		rvdev->vring[i].len = vring->num;
-		rvdev->vring[i].va = va;
-		rvdev->vring[i].dma = dma;
-	}
+	/* it is now safe to add the virtio device */
+	ret = rproc_add_virtio_dev(rvdev, rsc->id);
+	if (ret)
+		goto free_vrings;
 
 	return 0;
+
+free_vrings:
+	__rproc_free_vrings(rvdev, i);
+	kfree(rvdev);
+	return ret;
 }
 
 /**
@@ -731,7 +743,7 @@ static rproc_handle_resource_t rproc_handle_rsc[] = {
 	[RSC_CARVEOUT] = (rproc_handle_resource_t)rproc_handle_carveout,
 	[RSC_DEVMEM] = (rproc_handle_resource_t)rproc_handle_devmem,
 	[RSC_TRACE] = (rproc_handle_resource_t)rproc_handle_trace,
-	[RSC_VDEV] = (rproc_handle_resource_t)rproc_handle_vdev,
+	[RSC_VDEV] = NULL, /* VDEVs were handled upon registrarion */
 };
 
 /* handle firmware resource entries before booting the remote processor */
@@ -784,6 +796,7 @@ rproc_handle_virtio_rsc(struct rproc *rproc, struct resource_table *table, int l
 		int offset = table->offset[i];
 		struct fw_rsc_hdr *hdr = (void *)table + offset;
 		int avail = len - offset - sizeof(*hdr);
+		struct fw_rsc_vdev *vrsc;
 
 		/* make sure table isn't truncated */
 		if (avail < 0) {
@@ -793,12 +806,14 @@ rproc_handle_virtio_rsc(struct rproc *rproc, struct resource_table *table, int l
 
 		dev_dbg(dev, "%s: rsc type %d\n", __func__, hdr->type);
 
-		if (hdr->type == RSC_VDEV) {
-			struct fw_rsc_vdev *vrsc =
-					(struct fw_rsc_vdev *)hdr->data;
-			ret = rproc_handle_early_vdev(rproc, vrsc, avail);
+		if (hdr->type != RSC_VDEV)
+			continue;
+
+		vrsc = (struct fw_rsc_vdev *)hdr->data;
+
+		ret = rproc_handle_vdev(rproc, vrsc, avail);
+		if (ret)
 			break;
-		}
 	}
 
 	return ret;
@@ -889,14 +904,12 @@ static int rproc_handle_resources(struct rproc *rproc, const u8 *elf_data,
  * @rproc: rproc handle
  *
  * This function will free all resources acquired for @rproc, and it
- * is called when @rproc shuts down, or just failed booting.
+ * is called whenever @rproc either shuts down or fails to boot.
  */
 static void rproc_resource_cleanup(struct rproc *rproc)
 {
 	struct rproc_mem_entry *entry, *tmp;
 	struct device *dev = rproc->dev;
-	struct rproc_vdev *rvdev = rproc->rvdev;
-	int i;
 
 	/* clean up debugfs trace entries */
 	list_for_each_entry_safe(entry, tmp, &rproc->traces, node) {
@@ -906,23 +919,6 @@ static void rproc_resource_cleanup(struct rproc *rproc)
 		kfree(entry);
 	}
 
-	/* free the coherent memory allocated for the vrings */
-	for (i = 0; rvdev && i < ARRAY_SIZE(rvdev->vring); i++) {
-		int qsz = rvdev->vring[i].len;
-		void *va = rvdev->vring[i].va;
-		int dma = rvdev->vring[i].dma;
-
-		/* virtqueue size is expressed in number of buffers supported */
-		if (qsz) {
-			/* how many bytes does this vring really occupy ? */
-			int size = PAGE_ALIGN(vring_size(qsz, AMP_VRING_ALIGN));
-
-			dma_free_coherent(rproc->dev, size, va, dma);
-
-			rvdev->vring[i].len = 0;
-		}
-	}
-
 	/* clean up carveout allocations */
 	list_for_each_entry_safe(entry, tmp, &rproc->carveouts, node) {
 		dma_free_coherent(dev, entry->len, entry->va, entry->dma);
@@ -1100,11 +1096,6 @@ static void rproc_fw_config_virtio(const struct firmware *fw, void *context)
 		goto out;
 	}
 
-	/* add the virtio device (currently only rpmsg vdevs are supported) */
-	ret = rproc_add_rpmsg_vdev(rproc);
-	if (ret)
-		goto out;
-
 out:
 	if (fw)
 		release_firmware(fw);
@@ -1266,13 +1257,23 @@ EXPORT_SYMBOL(rproc_shutdown);
 void rproc_release(struct kref *kref)
 {
 	struct rproc *rproc = container_of(kref, struct rproc, refcount);
+	struct rproc_vdev *rvdev, *rvtmp;
 
 	dev_info(rproc->dev, "removing %s\n", rproc->name);
 
 	rproc_delete_debug_dir(rproc);
 
-	/* at this point no one holds a reference to rproc anymore */
-	kfree(rproc);
+	/* clean up remote vdev entries */
+	list_for_each_entry_safe(rvdev, rvtmp, &rproc->rvdevs, node) {
+		__rproc_free_vrings(rvdev, RVDEV_NUM_VRINGS);
+		list_del(&rvdev->node);
+	}
+
+	/*
+	 * At this point no one holds a reference to rproc anymore,
+	 * so we can directly unroll rproc_alloc()
+	 */
+	rproc_free(rproc);
 }
 
 /* will be called when an rproc is added to the rprocs klist */
@@ -1316,7 +1317,7 @@ static struct rproc *next_rproc(struct klist_iter *i)
  * use rproc_put() to decrement it back once rproc isn't needed anymore.
  *
  * Note: currently this function (and its counterpart rproc_put()) are not
- * used anymore by the rpmsg subsystem. We need to scrutinize the use cases
+ * being used. We need to scrutinize the use cases
  * that still need them, and see if we can migrate them to use the non
  * name-based boot/shutdown interface.
  */
@@ -1391,11 +1392,8 @@ EXPORT_SYMBOL(rproc_put);
  * firmware.
  *
  * If found, those virtio devices will be created and added, so as a result
- * of registering this remote processor, additional virtio drivers will be
+ * of registering this remote processor, additional virtio drivers might be
  * probed.
- *
- * Currently, though, we only support a single RPMSG virtio vdev per remote
- * processor.
  */
 int rproc_register(struct rproc *rproc)
 {
@@ -1418,7 +1416,7 @@ int rproc_register(struct rproc *rproc)
 
 	/*
 	 * We must retrieve early virtio configuration info from
-	 * the firmware (e.g. whether to register a virtio rpmsg device,
+	 * the firmware (e.g. whether to register a virtio device,
 	 * what virtio features does it support, ...).
 	 *
 	 * We're initiating an asynchronous firmware loading, so we can
@@ -1487,9 +1485,12 @@ struct rproc *rproc_alloc(struct device *dev, const char *name,
 
 	mutex_init(&rproc->lock);
 
+	idr_init(&rproc->notifyids);
+
 	INIT_LIST_HEAD(&rproc->carveouts);
 	INIT_LIST_HEAD(&rproc->mappings);
 	INIT_LIST_HEAD(&rproc->traces);
+	INIT_LIST_HEAD(&rproc->rvdevs);
 
 	rproc->state = RPROC_OFFLINE;
 
@@ -1509,6 +1510,9 @@ EXPORT_SYMBOL(rproc_alloc);
  */
 void rproc_free(struct rproc *rproc)
 {
+	idr_remove_all(&rproc->notifyids);
+	idr_destroy(&rproc->notifyids);
+
 	kfree(rproc);
 }
 EXPORT_SYMBOL(rproc_free);
@@ -1535,18 +1539,22 @@ EXPORT_SYMBOL(rproc_free);
  */
 int rproc_unregister(struct rproc *rproc)
 {
+	struct rproc_vdev *rvdev;
+
 	if (!rproc)
 		return -EINVAL;
 
 	/* if rproc is just being registered, wait */
 	wait_for_completion(&rproc->firmware_loading_complete);
 
-	/* was an rpmsg vdev created ? */
-	if (rproc->rvdev)
-		rproc_remove_rpmsg_vdev(rproc);
+	/* clean up remote vdev entries */
+	list_for_each_entry(rvdev, &rproc->rvdevs, node)
+		rproc_remove_virtio_dev(rvdev);
 
-	klist_remove(&rproc->node);
+	/* the rproc is downref'ed as soon as it's removed from the klist */
+	klist_del(&rproc->node);
 
+	/* the rproc will only be released after its refcount drops to zero */
 	kref_put(&rproc->refcount, rproc_release);
 
 	return 0;
diff --git a/drivers/remoteproc/remoteproc_internal.h b/drivers/remoteproc/remoteproc_internal.h
index 8b2fc40..9f336d6 100644
--- a/drivers/remoteproc/remoteproc_internal.h
+++ b/drivers/remoteproc/remoteproc_internal.h
@@ -28,9 +28,9 @@ struct rproc;
 void rproc_release(struct kref *kref);
 irqreturn_t rproc_vq_interrupt(struct rproc *rproc, int vq_id);
 
-/* from remoteproc_rpmsg.c */
-int rproc_add_rpmsg_vdev(struct rproc *);
-void rproc_remove_rpmsg_vdev(struct rproc *rproc);
+/* from remoteproc_virtio.c */
+int rproc_add_virtio_dev(struct rproc_vdev *rvdev, int id);
+void rproc_remove_virtio_dev(struct rproc_vdev *rvdev);
 
 /* from remoteproc_debugfs.c */
 void rproc_remove_trace_file(struct dentry *tfile);
diff --git a/drivers/remoteproc/remoteproc_virtio.c b/drivers/remoteproc/remoteproc_virtio.c
index 78d8527..0700410 100644
--- a/drivers/remoteproc/remoteproc_virtio.c
+++ b/drivers/remoteproc/remoteproc_virtio.c
@@ -19,7 +19,6 @@
 
 #include <linux/export.h>
 #include <linux/remoteproc.h>
-#include <linux/rpmsg.h>
 #include <linux/virtio.h>
 #include <linux/virtio_config.h>
 #include <linux/virtio_ids.h>
@@ -30,45 +29,41 @@
 
 #include "remoteproc_internal.h"
 
-/**
- * struct rproc_virtio_vq_info - virtqueue state
- * @vq_id: a unique index of this virtqueue (unique for this @rproc)
- * @rproc: handle to the remote processor
- *
- * Such a struct will be maintained for every virtqueue we're
- * using to communicate with the remote processor
- */
-struct rproc_virtio_vq_info {
-	__u16 vq_id;
-	struct rproc *rproc;
-};
-
 /* kick the remote processor, and let it know which virtqueue to poke at */
 static void rproc_virtio_notify(struct virtqueue *vq)
 {
-	struct rproc_virtio_vq_info *rpvq = vq->priv;
-	struct rproc *rproc = rpvq->rproc;
+	struct rproc_vring *rvring = vq->priv;
+	struct rproc *rproc = rvring->rvdev->rproc;
+	int notifyid = rvring->notifyid;
 
-	dev_dbg(rproc->dev, "kicking vq id: %d\n", rpvq->vq_id);
+	dev_dbg(rproc->dev, "kicking vq index: %d\n", notifyid);
 
-	rproc->ops->kick(rproc, rpvq->vq_id);
+	rproc->ops->kick(rproc, notifyid);
 }
 
 /**
  * rproc_vq_interrupt() - tell remoteproc that a virtqueue is interrupted
  * @rproc: handle to the remote processor
- * @vq_id: index of the signalled virtqueue
+ * @notifyid: index of the signalled virtqueue (unique per this @rproc)
  *
  * This function should be called by the platform-specific rproc driver,
  * when the remote processor signals that a specific virtqueue has pending
  * messages available.
  *
- * Returns IRQ_NONE if no message was found in the @vq_id virtqueue,
+ * Returns IRQ_NONE if no message was found in the @notifyid virtqueue,
  * and otherwise returns IRQ_HANDLED.
  */
-irqreturn_t rproc_vq_interrupt(struct rproc *rproc, int vq_id)
+irqreturn_t rproc_vq_interrupt(struct rproc *rproc, int notifyid)
 {
-	return vring_interrupt(0, rproc->rvdev->vq[vq_id]);
+	struct rproc_vring *rvring;
+
+	dev_dbg(rproc->dev, "vq index %d is interrupted\n", notifyid);
+
+	rvring = idr_find(&rproc->notifyids, notifyid);
+	if (!rvring || !rvring->vq)
+		return IRQ_NONE;
+
+	return vring_interrupt(0, rvring->vq);
 }
 EXPORT_SYMBOL(rproc_vq_interrupt);
 
@@ -77,24 +72,28 @@ static struct virtqueue *rp_find_vq(struct virtio_device *vdev,
 				    void (*callback)(struct virtqueue *vq),
 				    const char *name)
 {
+	struct rproc_vdev *rvdev = vdev_to_rvdev(vdev);
 	struct rproc *rproc = vdev_to_rproc(vdev);
-	struct rproc_vdev *rvdev = rproc->rvdev;
-	struct rproc_virtio_vq_info *rpvq;
+	struct rproc_vring *rvring;
 	struct virtqueue *vq;
 	void *addr;
-	int ret, len;
+	int len, size;
 
-	rpvq = kmalloc(sizeof(*rpvq), GFP_KERNEL);
-	if (!rpvq)
-		return ERR_PTR(-ENOMEM);
+	/* we're temporarily limited to two virtqueues per rvdev */
+	if (id >= ARRAY_SIZE(rvdev->vring))
+		return ERR_PTR(-EINVAL);
+
+	rvring = &rvdev->vring[id];
 
-	rpvq->rproc = rproc;
-	rpvq->vq_id = id;
+	addr = rvring->va;
+	len = rvring->len;
 
-	addr = rvdev->vring[id].va;
-	len = rvdev->vring[id].len;
+	/* zero vring */
+	size = vring_size(len, rvring->align);
+	memset(addr, 0, size);
 
-	dev_dbg(rproc->dev, "vring%d: va %p qsz %d\n", id, addr, len);
+	dev_dbg(rproc->dev, "vring%d: va %p qsz %d notifyid %d\n",
+					id, addr, len, rvring->notifyid);
 
 	/*
 	 * Create the new vq, and tell virtio we're not interested in
@@ -104,32 +103,28 @@ static struct virtqueue *rp_find_vq(struct virtio_device *vdev,
 					rproc_virtio_notify, callback, name);
 	if (!vq) {
 		dev_err(rproc->dev, "vring_new_virtqueue %s failed\n", name);
-		ret = -ENOMEM;
-		goto free_rpvq;
+		return ERR_PTR(-ENOMEM);
 	}
 
-	rvdev->vq[id] = vq;
-	vq->priv = rpvq;
+	rvring->vq = vq;
+	vq->priv = rvring;
 
 	return vq;
-
-free_rpvq:
-	kfree(rpvq);
-	return ERR_PTR(ret);
 }
 
 static void rproc_virtio_del_vqs(struct virtio_device *vdev)
 {
 	struct virtqueue *vq, *n;
 	struct rproc *rproc = vdev_to_rproc(vdev);
+	struct rproc_vring *rvring;
 
 	/* power down the remote processor before deleting vqs */
 	rproc_shutdown(rproc);
 
 	list_for_each_entry_safe(vq, n, &vdev->vqs, list) {
-		struct rproc_virtio_vq_info *rpvq = vq->priv;
+		rvring = vq->priv;
+		rvring->vq = NULL;
 		vring_del_virtqueue(vq);
-		kfree(rpvq);
 	}
 }
 
@@ -141,10 +136,6 @@ static int rproc_virtio_find_vqs(struct virtio_device *vdev, unsigned nvqs,
 	struct rproc *rproc = vdev_to_rproc(vdev);
 	int i, ret;
 
-	/* we maintain two virtqueues per remote processor (for RX and TX) */
-	if (nvqs != 2)
-		return -EINVAL;
-
 	for (i = 0; i < nvqs; ++i) {
 		vqs[i] = rp_find_vq(vdev, i, callbacks[i], names[i]);
 		if (IS_ERR(vqs[i])) {
@@ -170,7 +161,7 @@ error:
 /*
  * We don't support yet real virtio status semantics.
  *
- * The plan is to provide this via the VIRTIO HDR resource entry
+ * The plan is to provide this via the VDEV resource entry
  * which is part of the firmware: this way the remote processor
  * will be able to access the status values as set by us.
  */
@@ -181,7 +172,7 @@ static u8 rproc_virtio_get_status(struct virtio_device *vdev)
 
 static void rproc_virtio_set_status(struct virtio_device *vdev, u8 status)
 {
-	dev_dbg(&vdev->dev, "new status: %d\n", status);
+	dev_dbg(&vdev->dev, "status: %d\n", status);
 }
 
 static void rproc_virtio_reset(struct virtio_device *vdev)
@@ -192,15 +183,14 @@ static void rproc_virtio_reset(struct virtio_device *vdev)
 /* provide the vdev features as retrieved from the firmware */
 static u32 rproc_virtio_get_features(struct virtio_device *vdev)
 {
-	struct rproc *rproc = vdev_to_rproc(vdev);
+	struct rproc_vdev *rvdev = vdev_to_rvdev(vdev);
 
-	/* we only support a single vdev device for now */
-	return rproc->rvdev->dfeatures;
+	return rvdev->dfeatures;
 }
 
 static void rproc_virtio_finalize_features(struct virtio_device *vdev)
 {
-	struct rproc *rproc = vdev_to_rproc(vdev);
+	struct rproc_vdev *rvdev = vdev_to_rvdev(vdev);
 
 	/* Give virtio_ring a chance to accept features */
 	vring_transport_features(vdev);
@@ -214,7 +204,7 @@ static void rproc_virtio_finalize_features(struct virtio_device *vdev)
 	 * fixed as part of a small resource table overhaul and then an
 	 * extension of the virtio resource entries.
 	 */
-	rproc->rvdev->gfeatures = vdev->features[0];
+	rvdev->gfeatures = vdev->features[0];
 }
 
 static struct virtio_config_ops rproc_virtio_config_ops = {
@@ -244,26 +234,25 @@ static void rproc_vdev_release(struct device *dev)
 }
 
 /**
- * rproc_add_rpmsg_vdev() - create an rpmsg virtio device
- * @rproc: the rproc handle
+ * rproc_add_virtio_dev() - register an rproc-induced virtio device
+ * @rvdev: the remote vdev
  *
- * This function is called if virtio rpmsg support was found in the
- * firmware of the remote processor.
+ * This function registers a virtio device. This vdev's partent is
+ * the rproc device.
  *
- * Today we only support creating a single rpmsg vdev (virtio device),
- * but the plan is to remove this limitation. At that point this interface
- * will be revised/extended.
+ * Returns 0 on success or an appropriate error value otherwise.
  */
-int rproc_add_rpmsg_vdev(struct rproc *rproc)
+int rproc_add_virtio_dev(struct rproc_vdev *rvdev, int id)
 {
+	struct rproc *rproc = rvdev->rproc;
 	struct device *dev = rproc->dev;
-	struct rproc_vdev *rvdev = rproc->rvdev;
+	struct virtio_device *vdev = &rvdev->vdev;
 	int ret;
 
-	rvdev->vdev.id.device	= VIRTIO_ID_RPMSG,
-	rvdev->vdev.config	= &rproc_virtio_config_ops,
-	rvdev->vdev.dev.parent	= dev;
-	rvdev->vdev.dev.release	= rproc_vdev_release;
+	vdev->id.device	= id,
+	vdev->config = &rproc_virtio_config_ops,
+	vdev->dev.parent = dev;
+	vdev->dev.release = rproc_vdev_release;
 
 	/*
 	 * We're indirectly making a non-temporary copy of the rproc pointer
@@ -275,25 +264,26 @@ int rproc_add_rpmsg_vdev(struct rproc *rproc)
 	 */
 	kref_get(&rproc->refcount);
 
-	ret = register_virtio_device(&rvdev->vdev);
+	ret = register_virtio_device(vdev);
 	if (ret) {
 		kref_put(&rproc->refcount, rproc_release);
 		dev_err(dev, "failed to register vdev: %d\n", ret);
+		goto out;
 	}
 
+	dev_info(dev, "registered %s (type %d)\n", dev_name(&vdev->dev), id);
+
+out:
 	return ret;
 }
 
 /**
- * rproc_remove_rpmsg_vdev() - remove an rpmsg vdev device
- * @rproc: the rproc handle
+ * rproc_remove_virtio_dev() - remove an rproc-induced virtio device
+ * @rvdev: the remote vdev
  *
- * This function is called whenever @rproc is removed _iff_ an rpmsg
- * vdev was created beforehand.
+ * This function unregisters an existing virtio device.
  */
-void rproc_remove_rpmsg_vdev(struct rproc *rproc)
+void rproc_remove_virtio_dev(struct rproc_vdev *rvdev)
 {
-	struct rproc_vdev *rvdev = rproc->rvdev;
-
 	unregister_virtio_device(&rvdev->vdev);
 }
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index 6040f83..7750d8a 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -41,6 +41,7 @@
 #include <linux/mutex.h>
 #include <linux/virtio.h>
 #include <linux/completion.h>
+#include <linux/idr.h>
 
 /*
  * The alignment between the consumer and producer parts of the vring.
@@ -387,7 +388,8 @@ enum rproc_state {
  * @mappings: list of iommu mappings we initiated, needed on shutdown
  * @firmware_loading_complete: marks e/o asynchronous firmware loading
  * @bootaddr: address of first instruction to boot rproc with (optional)
- * @rvdev: virtio device (we only support a single rpmsg virtio device for now)
+ * @rvdevs: list of remote virtio devices
+ * @notifyids: idr for dynamically assigning rproc-wide unique notify ids
  */
 struct rproc {
 	struct klist_node node;
@@ -408,23 +410,47 @@ struct rproc {
 	struct list_head mappings;
 	struct completion firmware_loading_complete;
 	u32 bootaddr;
+	struct list_head rvdevs;
+	struct idr notifyids;
+};
+
+/* we currently support only two vrings per rvdev */
+#define RVDEV_NUM_VRINGS 2
+
+/**
+ * struct rproc_vring - remoteproc vring state
+ * @va:	virtual address
+ * @dma: dma address
+ * @len: length, in bytes
+ * @da: device address
+ * @notifyid: rproc-specific unique vring index
+ * @rvdev: remote vdev
+ * @vq: the virtqueue of this vring
+ */
+struct rproc_vring {
+	void *va;
+	dma_addr_t dma;
+	int len;
+	u32 da;
+	int notifyid;
 	struct rproc_vdev *rvdev;
+	struct virtqueue *vq;
 };
 
 /**
  * struct rproc_vdev - remoteproc state for a supported virtio device
+ * @node: list node
  * @rproc: the rproc handle
  * @vdev: the virio device
- * @vq: the virtqueues for this vdev
  * @vring: the vrings for this vdev
  * @dfeatures: virtio device features
  * @gfeatures: virtio guest features
  */
 struct rproc_vdev {
+	struct list_head node;
 	struct rproc *rproc;
 	struct virtio_device vdev;
-	struct virtqueue *vq[2];
-	struct rproc_mem_entry vring[2];
+	struct rproc_vring vring[RVDEV_NUM_VRINGS];
 	unsigned long dfeatures;
 	unsigned long gfeatures;
 };
@@ -442,9 +468,14 @@ int rproc_unregister(struct rproc *rproc);
 int rproc_boot(struct rproc *rproc);
 void rproc_shutdown(struct rproc *rproc);
 
+static inline struct rproc_vdev *vdev_to_rvdev(struct virtio_device *vdev)
+{
+	return container_of(vdev, struct rproc_vdev, vdev);
+}
+
 static inline struct rproc *vdev_to_rproc(struct virtio_device *vdev)
 {
-	struct rproc_vdev *rvdev = container_of(vdev, struct rproc_vdev, vdev);
+	struct rproc_vdev *rvdev = vdev_to_rvdev(vdev);
 
 	return rvdev->rproc;
 }
-- 
1.7.5.4



From ohad at wizery.com  Thu Mar  1 03:11:35 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Thu,  1 Mar 2012 10:11:35 +0200
Subject: [PATCH 5/7] remoteproc/omap: remove the mbox_callback limitation
In-Reply-To: <1330589497-4139-1-git-send-email-ohad@wizery.com>
References: <1330589497-4139-1-git-send-email-ohad@wizery.com>
Message-ID: <1330589497-4139-6-git-send-email-ohad@wizery.com>

Now that remoteproc supports any number of virtio devices,
the previous sanity check in omap_rproc_mbox_callback
doesn't make sense anymore.

Remove that so we can start supporting multiple vdevs.

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Cc: Brian Swetland <swetland at google.com>
Cc: Iliyan Malchev <malchev at google.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rusty Russell <rusty at rustcorp.com.au>
Cc: Mark Grosen <mgrosen at ti.com>
Cc: John Williams <john.williams at petalogix.com>
Cc: Michal Simek <monstr at monstr.eu>
Cc: Loic PALLARDY <loic.pallardy at stericsson.com>
Cc: Ludovic BARRE <ludovic.barre at stericsson.com>
Cc: Omar Ramirez Luna <omar.luna at linaro.org>
Cc: Guzman Lugo Fernando <fernando.lugo at ti.com>
Cc: Anna Suman <s-anna at ti.com>
Cc: Clark Rob <rob at ti.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: David Brown <davidb at codeaurora.org>
Cc: Kieran Bingham <kieranbingham at gmail.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 drivers/remoteproc/omap_remoteproc.c |   11 +----------
 1 files changed, 1 insertions(+), 10 deletions(-)

diff --git a/drivers/remoteproc/omap_remoteproc.c b/drivers/remoteproc/omap_remoteproc.c
index aa3ce52..69425c4 100644
--- a/drivers/remoteproc/omap_remoteproc.c
+++ b/drivers/remoteproc/omap_remoteproc.c
@@ -80,16 +80,7 @@ static int omap_rproc_mbox_callback(struct notifier_block *this,
 		dev_info(dev, "received echo reply from %s\n", name);
 		break;
 	default:
-		/* ignore vq indices which are too large to be valid */
-		if (msg >= 2) {
-			dev_warn(dev, "invalid mbox msg: 0x%x\n", msg);
-			break;
-		}
-
-		/*
-		 * At this point, 'msg' contains the index of the vring
-		 * which was just triggered.
-		 */
+		/* msg contains the index of the triggered vring */
 		if (rproc_vq_interrupt(oproc->rproc, msg) == IRQ_NONE)
 			dev_dbg(dev, "no message was found in vqid %d\n", msg);
 	}
-- 
1.7.5.4



From ohad at wizery.com  Thu Mar  1 03:11:36 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Thu,  1 Mar 2012 10:11:36 +0200
Subject: [PATCH 6/7] remoteproc: remove the hardcoded vring alignment
In-Reply-To: <1330589497-4139-1-git-send-email-ohad@wizery.com>
References: <1330589497-4139-1-git-send-email-ohad@wizery.com>
Message-ID: <1330589497-4139-7-git-send-email-ohad@wizery.com>

Remove the hardcoded vring alignment of 4096 bytes,
and instead utilize tha vring alignment as specified in
the resource table.

This is needed for remote processors that have rigid
memory requirement, and which have found the alignment of
4096 bytes to be excessively big.

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Cc: Brian Swetland <swetland at google.com>
Cc: Iliyan Malchev <malchev at google.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rusty Russell <rusty at rustcorp.com.au>
Cc: Mark Grosen <mgrosen at ti.com>
Cc: John Williams <john.williams at petalogix.com>
Cc: Michal Simek <monstr at monstr.eu>
Cc: Loic PALLARDY <loic.pallardy at stericsson.com>
Cc: Ludovic BARRE <ludovic.barre at stericsson.com>
Cc: Omar Ramirez Luna <omar.luna at linaro.org>
Cc: Guzman Lugo Fernando <fernando.lugo at ti.com>
Cc: Anna Suman <s-anna at ti.com>
Cc: Clark Rob <rob at ti.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: David Brown <davidb at codeaurora.org>
Cc: Kieran Bingham <kieranbingham at gmail.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 drivers/remoteproc/remoteproc_core.c   |   12 +++++++-----
 drivers/remoteproc/remoteproc_virtio.c |    2 +-
 include/linux/remoteproc.h             |    9 ++-------
 3 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index ca02f12..9be5dad 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -298,14 +298,15 @@ __rproc_handle_vring(struct rproc_vdev *rvdev, struct fw_rsc_vdev *rsc, int i)
 		return -EINVAL;
 	}
 
-	/* the firmware must provide the expected queue size */
-	if (!vring->num) {
-		dev_err(dev, "invalid qsz (%d)\n", vring->num);
+	/* verify queue size and vring alignment are sane */
+	if (!vring->num || !vring->align) {
+		dev_err(dev, "invalid qsz (%d) or alignment (%d)\n",
+						vring->num, vring->align);
 		return -EINVAL;
 	}
 
 	/* actual size of vring (in bytes) */
-	size = PAGE_ALIGN(vring_size(vring->num, AMP_VRING_ALIGN));
+	size = PAGE_ALIGN(vring_size(vring->num, vring->align));
 
 	if (!idr_pre_get(&rproc->notifyids, GFP_KERNEL)) {
 		dev_err(dev, "idr_pre_get failed\n");
@@ -340,6 +341,7 @@ __rproc_handle_vring(struct rproc_vdev *rvdev, struct fw_rsc_vdev *rsc, int i)
 					dma, size, notifyid);
 
 	rvdev->vring[i].len = vring->num;
+	rvdev->vring[i].align = vring->align;
 	rvdev->vring[i].va = va;
 	rvdev->vring[i].dma = dma;
 	rvdev->vring[i].notifyid = notifyid;
@@ -354,7 +356,7 @@ static void __rproc_free_vrings(struct rproc_vdev *rvdev, int i)
 
 	for (i--; i > 0; i--) {
 		struct rproc_vring *rvring = &rvdev->vring[i];
-		int size = PAGE_ALIGN(vring_size(rvring->len, AMP_VRING_ALIGN));
+		int size = PAGE_ALIGN(vring_size(rvring->len, rvring->align));
 
 		dma_free_coherent(rproc->dev, size, rvring->va, rvring->dma);
 		idr_remove(&rproc->notifyids, rvring->notifyid);
diff --git a/drivers/remoteproc/remoteproc_virtio.c b/drivers/remoteproc/remoteproc_virtio.c
index 0700410..ecf6121 100644
--- a/drivers/remoteproc/remoteproc_virtio.c
+++ b/drivers/remoteproc/remoteproc_virtio.c
@@ -99,7 +99,7 @@ static struct virtqueue *rp_find_vq(struct virtio_device *vdev,
 	 * Create the new vq, and tell virtio we're not interested in
 	 * the 'weak' smp barriers, since we're talking with a real device.
 	 */
-	vq = vring_new_virtqueue(len, AMP_VRING_ALIGN, vdev, false, addr,
+	vq = vring_new_virtqueue(len, rvring->align, vdev, false, addr,
 					rproc_virtio_notify, callback, name);
 	if (!vq) {
 		dev_err(rproc->dev, "vring_new_virtqueue %s failed\n", name);
diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
index 7750d8a..f1ffabb 100644
--- a/include/linux/remoteproc.h
+++ b/include/linux/remoteproc.h
@@ -43,13 +43,6 @@
 #include <linux/completion.h>
 #include <linux/idr.h>
 
-/*
- * The alignment between the consumer and producer parts of the vring.
- * Note: this is part of the "wire" protocol. If you change this, you need
- * to update your peers too.
- */
-#define AMP_VRING_ALIGN	(4096)
-
 /**
  * struct resource_table - firmware resource table header
  * @ver: version number
@@ -423,6 +416,7 @@ struct rproc {
  * @dma: dma address
  * @len: length, in bytes
  * @da: device address
+ * @align: vring alignment
  * @notifyid: rproc-specific unique vring index
  * @rvdev: remote vdev
  * @vq: the virtqueue of this vring
@@ -432,6 +426,7 @@ struct rproc_vring {
 	dma_addr_t dma;
 	int len;
 	u32 da;
+	u32 align;
 	int notifyid;
 	struct rproc_vdev *rvdev;
 	struct virtqueue *vq;
-- 
1.7.5.4



From ohad at wizery.com  Thu Mar  1 03:11:37 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Thu,  1 Mar 2012 10:11:37 +0200
Subject: [PATCH 7/7] remoteproc: cleanup resource table parsing paths
In-Reply-To: <1330589497-4139-1-git-send-email-ohad@wizery.com>
References: <1330589497-4139-1-git-send-email-ohad@wizery.com>
Message-ID: <1330589497-4139-8-git-send-email-ohad@wizery.com>

rproc_handle_resources() looks for the resource table and then
invokes a resource handler function which it took as a parameter.

This works, but it's a bit unintuitive to follow.

Instead of passing around function pointers, this patch changes
rproc_handle_resource() to just find and return the resource table,
and then the calling sites of rproc_handle_resource() invoke their
resource handlers directly.

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Cc: Brian Swetland <swetland at google.com>
Cc: Iliyan Malchev <malchev at google.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rusty Russell <rusty at rustcorp.com.au>
Cc: Mark Grosen <mgrosen at ti.com>
Cc: John Williams <john.williams at petalogix.com>
Cc: Michal Simek <monstr at monstr.eu>
Cc: Loic PALLARDY <loic.pallardy at stericsson.com>
Cc: Ludovic BARRE <ludovic.barre at stericsson.com>
Cc: Omar Ramirez Luna <omar.luna at linaro.org>
Cc: Guzman Lugo Fernando <fernando.lugo at ti.com>
Cc: Anna Suman <s-anna at ti.com>
Cc: Clark Rob <rob at ti.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: David Brown <davidb at codeaurora.org>
Cc: Kieran Bingham <kieranbingham at gmail.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 drivers/remoteproc/remoteproc_core.c |   70 ++++++++++++++++++---------------
 1 files changed, 38 insertions(+), 32 deletions(-)

diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
index 9be5dad..ee15c68 100644
--- a/drivers/remoteproc/remoteproc_core.c
+++ b/drivers/remoteproc/remoteproc_core.c
@@ -822,32 +822,31 @@ rproc_handle_virtio_rsc(struct rproc *rproc, struct resource_table *table, int l
 }
 
 /**
- * rproc_handle_resources() - find and handle the resource table
+ * rproc_find_rsc_table() - find the resource table
  * @rproc: the rproc handle
  * @elf_data: the content of the ELF firmware image
  * @len: firmware size (in bytes)
- * @handler: function that should be used to handle the resource table
+ * @tablesz: place holder for providing back the table size
  *
  * This function finds the resource table inside the remote processor's
- * firmware, and invoke a user-supplied handler with it (we have two
- * possible handlers: one is invoked upon registration of @rproc,
- * in order to register the supported virito devices, and the other is
- * invoked when @rproc is actually booted).
- *
- * Currently this function fails if a resource table doesn't exist.
- * This restriction will be removed when we'll start supporting remote
- * processors that don't need a resource table.
+ * firmware. It is used both upon the registration of @rproc (in order
+ * to look for and register the supported virito devices), and when the
+ * @rproc is booted.
+ *
+ * Returns the pointer to the resource table if it is found, and write its
+ * size into @tablesz. If a valid table isn't found, NULL is returned
+ * (and @tablesz isn't set).
  */
-static int rproc_handle_resources(struct rproc *rproc, const u8 *elf_data,
-				size_t len, rproc_handle_resources_t handler)
-
+static struct resource_table *
+rproc_find_rsc_table(struct rproc *rproc, const u8 *elf_data, size_t len,
+							int *tablesz)
 {
 	struct elf32_hdr *ehdr;
 	struct elf32_shdr *shdr;
 	const char *name_table;
 	struct device *dev = rproc->dev;
-	int i, ret = -EINVAL;
-	struct resource_table *table;
+	struct resource_table *table = NULL;
+	int i;
 
 	ehdr = (struct elf32_hdr *)elf_data;
 	shdr = (struct elf32_shdr *)(elf_data + ehdr->e_shoff);
@@ -866,39 +865,39 @@ static int rproc_handle_resources(struct rproc *rproc, const u8 *elf_data,
 		/* make sure we have the entire table */
 		if (offset + size > len) {
 			dev_err(dev, "resource table truncated\n");
-			return -EINVAL;
+			return NULL;
 		}
 
 		/* make sure table has at least the header */
 		if (sizeof(struct resource_table) > size) {
 			dev_err(dev, "header-less resource table\n");
-			return -EINVAL;
+			return NULL;
 		}
 
 		/* we don't support any version beyond the first */
 		if (table->ver != 1) {
 			dev_err(dev, "unsupported fw ver: %d\n", table->ver);
-			return -EINVAL;
+			return NULL;
 		}
 
 		/* make sure reserved bytes are zeroes */
 		if (table->reserved[0] || table->reserved[1]) {
 			dev_err(dev, "non zero reserved bytes\n");
-			return -EINVAL;
+			return NULL;
 		}
 
 		/* make sure the offsets array isn't truncated */
 		if (table->num * sizeof(table->offset[0]) +
 				sizeof(struct resource_table) > size) {
 			dev_err(dev, "resource table incomplete\n");
-			return -EINVAL;
+			return NULL;
 		}
 
-		ret = handler(rproc, table, shdr->sh_size);
+		*tablesz = shdr->sh_size;
 		break;
 	}
 
-	return ret;
+	return table;
 }
 
 /**
@@ -1012,7 +1011,8 @@ static int rproc_fw_boot(struct rproc *rproc, const struct firmware *fw)
 	struct device *dev = rproc->dev;
 	const char *name = rproc->firmware;
 	struct elf32_hdr *ehdr;
-	int ret;
+	struct resource_table *table;
+	int ret, tablesz;
 
 	ret = rproc_fw_sanity_check(rproc, fw);
 	if (ret)
@@ -1039,9 +1039,13 @@ static int rproc_fw_boot(struct rproc *rproc, const struct firmware *fw)
 	 */
 	rproc->bootaddr = ehdr->e_entry;
 
+	/* look for the resource table */
+	table = rproc_find_rsc_table(rproc, fw->data, fw->size, &tablesz);
+	if (!table)
+		goto clean_up;
+
 	/* handle fw resources which are required to boot rproc */
-	ret = rproc_handle_resources(rproc, fw->data, fw->size,
-						rproc_handle_boot_rsc);
+	ret = rproc_handle_boot_rsc(rproc, table, tablesz);
 	if (ret) {
 		dev_err(dev, "Failed to process resources: %d\n", ret);
 		goto clean_up;
@@ -1084,19 +1088,21 @@ clean_up:
 static void rproc_fw_config_virtio(const struct firmware *fw, void *context)
 {
 	struct rproc *rproc = context;
-	struct device *dev = rproc->dev;
-	int ret;
+	struct resource_table *table;
+	int ret, tablesz;
 
 	if (rproc_fw_sanity_check(rproc, fw) < 0)
 		goto out;
 
-	/* does the fw support any virtio devices ? */
-	ret = rproc_handle_resources(rproc, fw->data, fw->size,
-						rproc_handle_virtio_rsc);
-	if (ret) {
-		dev_info(dev, "No fw virtio device was found\n");
+	/* look for the resource table */
+	table = rproc_find_rsc_table(rproc, fw->data, fw->size, &tablesz);
+	if (!table)
+		goto out;
+
+	/* look for virtio devices and register them */
+	ret = rproc_handle_virtio_rsc(rproc, table, tablesz);
+	if (ret)
 		goto out;
-	}
 
 out:
 	if (fw)
-- 
1.7.5.4



From adrian.hunter at intel.com  Thu Mar  1 03:21:59 2012
From: adrian.hunter at intel.com (Adrian Hunter)
Date: Thu, 01 Mar 2012 10:21:59 +0200
Subject: [PATCH V2 1/1] mmc: start removing enable / disable API
In-Reply-To: <4F4F2E93.1090109@codeaurora.org>
References: <1330499841-6879-1-git-send-email-adrian.hunter@intel.com>
 <1330499841-6879-2-git-send-email-adrian.hunter@intel.com>
 <4F4F2E93.1090109@codeaurora.org>
Message-ID: <4F4F31A7.3060307@intel.com>

On 01/03/12 10:08, Subhash Jadavani wrote:
> On 2/29/2012 12:47 PM, Adrian Hunter wrote:
>> Most parts of the enable / disable API are no longer used and
>> can be removed.
>>
>> Cc: Rajendra Nayak<rnayak at ti.com>
>> Cc: Venkatraman S<svenkatr at ti.com>
>> Cc: Kukjin Kim<kgene.kim at samsung.com>
>> Cc: Thomas Abraham<thomas.abraham at linaro.org>
>> Cc: Kyungmin Park<kyungmin.park at samsung.com>
>> Cc: Sekhar Nori<nsekhar at ti.com>
>> Cc: Kevin Hilman<khilman at ti.com>
>> Signed-off-by: Adrian Hunter<adrian.hunter at intel.com>
>> ---
>>   arch/arm/mach-exynos/mach-nuri.c           |    5 +-
>>   arch/arm/mach-exynos/mach-universal_c210.c |    9 +-
>>   drivers/mmc/core/core.c                    |  187
>> +++-------------------------
>>   drivers/mmc/core/host.c                    |    1 -
>>   drivers/mmc/core/host.h                    |    1 -
>>   drivers/mmc/host/davinci_mmc.c             |    4 -
>>   drivers/mmc/host/omap_hsmmc.c              |   15 +--
>>   include/linux/mmc/core.h                   |    1 -
>>   include/linux/mmc/host.h                   |   46 +------
>>   9 files changed, 27 insertions(+), 242 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/mach-nuri.c
>> b/arch/arm/mach-exynos/mach-nuri.c
>> index 644af11..de68248 100644
>> --- a/arch/arm/mach-exynos/mach-nuri.c
>> +++ b/arch/arm/mach-exynos/mach-nuri.c
>> @@ -109,7 +109,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data
>> __initdata = {
>>       .max_width        = 8,
>>       .host_caps        = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
>>                   MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
>> -                MMC_CAP_DISABLE | MMC_CAP_ERASE),
>> +                MMC_CAP_ERASE),
>>       .cd_type        = S3C_SDHCI_CD_PERMANENT,
>>   };
>>
>> @@ -147,8 +147,7 @@ static struct platform_device emmc_fixed_voltage = {
>>   static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
>>       .max_width        = 4,
>>       .host_caps        = MMC_CAP_4_BIT_DATA |
>> -                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
>> -                MMC_CAP_DISABLE,
>> +                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>>       .ext_cd_gpio        = EXYNOS4_GPX3(3),    /* XEINT_27 */
>>       .ext_cd_gpio_invert    = 1,
>>       .cd_type        = S3C_SDHCI_CD_GPIO,
>> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c
>> b/arch/arm/mach-exynos/mach-universal_c210.c
>> index 9b3fbae..57cfe61 100644
>> --- a/arch/arm/mach-exynos/mach-universal_c210.c
>> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
>> @@ -734,8 +734,7 @@ static struct platform_device universal_gpio_keys = {
>>   static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
>>       .max_width        = 8,
>>       .host_caps        = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
>> -                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
>> -                MMC_CAP_DISABLE),
>> +                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
>>       .cd_type        = S3C_SDHCI_CD_PERMANENT,
>>   };
>>
>> @@ -772,8 +771,7 @@ static struct platform_device mmc0_fixed_voltage = {
>>   static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
>>       .max_width        = 4,
>>       .host_caps        = MMC_CAP_4_BIT_DATA |
>> -                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
>> -                MMC_CAP_DISABLE,
>> +                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>>       .ext_cd_gpio        = EXYNOS4_GPX3(4),      /* XEINT_28 */
>>       .ext_cd_gpio_invert    = 1,
>>       .cd_type        = S3C_SDHCI_CD_GPIO,
>> @@ -783,8 +781,7 @@ static struct s3c_sdhci_platdata universal_hsmmc2_data
>> __initdata = {
>>   static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
>>       .max_width        = 4,
>>       .host_caps        = MMC_CAP_4_BIT_DATA |
>> -                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
>> -                MMC_CAP_DISABLE,
>> +                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>>       .cd_type        = S3C_SDHCI_CD_EXTERNAL,
>>   };
>>
>> diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
>> index 0b317f0..44dd013 100644
>> --- a/drivers/mmc/core/core.c
>> +++ b/drivers/mmc/core/core.c
>> @@ -605,105 +605,6 @@ unsigned int mmc_align_data_size(struct mmc_card
>> *card, unsigned int sz)
>>   EXPORT_SYMBOL(mmc_align_data_size);
>>
>>   /**
>> - *    mmc_host_enable - enable a host.
>> - *    @host: mmc host to enable
>> - *
>> - *    Hosts that support power saving can use the 'enable' and 'disable'
>> - *    methods to exit and enter power saving states. For more information
>> - *    see comments for struct mmc_host_ops.
>> - */
>> -int mmc_host_enable(struct mmc_host *host)
>> -{
>> -    if (!(host->caps&  MMC_CAP_DISABLE))
>> -        return 0;
>> -
>> -    if (host->en_dis_recurs)
>> -        return 0;
>> -
>> -    if (host->nesting_cnt++)
>> -        return 0;
>> -
>> -    cancel_delayed_work_sync(&host->disable);
>> -
>> -    if (host->enabled)
>> -        return 0;
>> -
>> -    if (host->ops->enable) {
>> -        int err;
>> -
>> -        host->en_dis_recurs = 1;
>> -        mmc_host_clk_hold(host);
>> -        err = host->ops->enable(host);
>> -        mmc_host_clk_release(host);
>> -        host->en_dis_recurs = 0;
>> -
>> -        if (err) {
>> -            pr_debug("%s: enable error %d\n",
>> -                 mmc_hostname(host), err);
>> -            return err;
>> -        }
>> -    }
>> -    host->enabled = 1;
>> -    return 0;
>> -}
>> -EXPORT_SYMBOL(mmc_host_enable);
>> -
>> -static int mmc_host_do_disable(struct mmc_host *host, int lazy)
>> -{
>> -    if (host->ops->disable) {
>> -        int err;
>> -
>> -        host->en_dis_recurs = 1;
>> -        mmc_host_clk_hold(host);
>> -        err = host->ops->disable(host, lazy);
>> -        mmc_host_clk_release(host);
>> -        host->en_dis_recurs = 0;
>> -
>> -        if (err<  0) {
>> -            pr_debug("%s: disable error %d\n",
>> -                 mmc_hostname(host), err);
>> -            return err;
>> -        }
>> -        if (err>  0) {
>> -            unsigned long delay = msecs_to_jiffies(err);
>> -
>> -            mmc_schedule_delayed_work(&host->disable, delay);
>> -        }
>> -    }
>> -    host->enabled = 0;
>> -    return 0;
>> -}
>> -
>> -/**
>> - *    mmc_host_disable - disable a host.
>> - *    @host: mmc host to disable
>> - *
>> - *    Hosts that support power saving can use the 'enable' and 'disable'
>> - *    methods to exit and enter power saving states. For more information
>> - *    see comments for struct mmc_host_ops.
>> - */
>> -int mmc_host_disable(struct mmc_host *host)
>> -{
>> -    int err;
>> -
>> -    if (!(host->caps&  MMC_CAP_DISABLE))
>> -        return 0;
>> -
>> -    if (host->en_dis_recurs)
>> -        return 0;
>> -
>> -    if (--host->nesting_cnt)
>> -        return 0;
>> -
>> -    if (!host->enabled)
>> -        return 0;
>> -
>> -    err = mmc_host_do_disable(host, 0);
>> -    return err;
>> -}
>> -EXPORT_SYMBOL(mmc_host_disable);
>> -
>> -/**
>>    *    __mmc_claim_host - exclusively claim a host
>>    *    @host: mmc host to claim
>>    *    @abort: whether or not the operation should be aborted
>> @@ -741,8 +642,8 @@ int __mmc_claim_host(struct mmc_host *host, atomic_t
>> *abort)
>>           wake_up(&host->wq);
>>       spin_unlock_irqrestore(&host->lock, flags);
>>       remove_wait_queue(&host->wq,&wait);
>> -    if (!stop)
>> -        mmc_host_enable(host);
>> +    if (host->ops->enable&&  !stop&&  host->claim_cnt == 1)
> Shouldn't we still make sure that clocks are hold (by calling
> mmc_host_clk_hold() ) before calling enable?

The only enable / disable user is omap_hsmmc which uses it to get
and put runtime pm, so there is no reason to hold / release clock
gating - since that path will also get / put runtime pm which is synchronized.


From t-kristo at ti.com  Thu Mar  1 03:23:49 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Thu, 1 Mar 2012 10:23:49 +0200
Subject: [PATCHv3 4/4] ARM: OMAP3+: add prcm chain interrupts to the
 interrupt list
In-Reply-To: <4F4F1EB3.6020707@ti.com>
References: <1330529106-10423-1-git-send-email-t-kristo@ti.com>
 <1330529106-10423-5-git-send-email-t-kristo@ti.com>
 <4F4F1EB3.6020707@ti.com>
Message-ID: <1330590229.2116.72.camel@sokoban>

On Thu, 2012-03-01 at 12:31 +0530, Rajendra Nayak wrote:
> On Wednesday 29 February 2012 08:55 PM, Tero Kristo wrote:
> > Currently PRCM chain handler for OMAP4 requires SPARSE_IRQ to be enabled
> > from kernel config, however enabling this option breaks the OMAP kernel
> > completely and it can't be used. Thus, OMAP_PRCM_IRQ_BASE was added
> > to the end of the irq list, and the prm_common code was changed to use
> > this instead of irq_desc allocation scheme.
> >
> > Once SPARSE_IRQ is enabled for OMAP kernel, this patch can be reverted.
> 
> Do you still need this, despite this fix from Benoit?
> http://marc.info/?l=linux-arm-kernel&m=133043468329275&w=2

Not sure, I haven't tested that yet.

-Tero

> 
> >
> > Signed-off-by: Tero Kristo<t-kristo at ti.com>
> > Cc: Paul Walmsley<paul at pwsan.com>
> > ---
> >   arch/arm/mach-omap2/prm_common.c       |   14 +-------------
> >   arch/arm/plat-omap/include/plat/irqs.h |    6 +++++-
> >   2 files changed, 6 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
> > index 860118a..9ca829f 100644
> > --- a/arch/arm/mach-omap2/prm_common.c
> > +++ b/arch/arm/mach-omap2/prm_common.c
> > @@ -196,11 +196,6 @@ void omap_prcm_irq_cleanup(void)
> >   	prcm_irq_setup->priority_mask = NULL;
> >
> >   	irq_set_chained_handler(prcm_irq_setup->irq, NULL);
> > -
> > -	if (prcm_irq_setup->base_irq>  0)
> > -		irq_free_descs(prcm_irq_setup->base_irq,
> > -			prcm_irq_setup->nr_regs * 32);
> > -	prcm_irq_setup->base_irq = 0;
> >   }
> >
> >   void omap_prcm_irq_prepare(void)
> > @@ -282,14 +277,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
> >
> >   	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
> >
> > -	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
> > -		0);
> > -
> > -	if (irq_setup->base_irq<  0) {
> > -		pr_err("PRCM: failed to allocate irq descs: %d\n",
> > -			irq_setup->base_irq);
> > -		goto err;
> > -	}
> > +	irq_setup->base_irq = OMAP_PRCM_IRQ_BASE;
> >
> >   	for (i = 0; i<= irq_setup->nr_regs; i++) {
> >   		gc = irq_alloc_generic_chip("PRCM", 1,
> > diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
> > index 2efd645..fe1be1d 100644
> > --- a/arch/arm/plat-omap/include/plat/irqs.h
> > +++ b/arch/arm/plat-omap/include/plat/irqs.h
> > @@ -428,8 +428,12 @@
> >   #define OMAP_GPMC_NR_IRQS	8
> >   #define OMAP_GPMC_IRQ_END	(OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
> >
> > +/* PRCM chain handler */
> > +#define OMAP_PRCM_IRQ_BASE	(OMAP_GPMC_IRQ_END)
> > +#define OMAP_PRCM_NR_IRQS	64
> > +#define OMAP_PRCM_IRQ_END	(OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
> >
> > -#define NR_IRQS			OMAP_GPMC_IRQ_END
> > +#define NR_IRQS			OMAP_PRCM_IRQ_END
> >
> >   #define OMAP_IRQ_BIT(irq)	(1<<  ((irq) % 32))
> >
> 




From t-kristo at ti.com  Thu Mar  1 03:25:55 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Thu, 1 Mar 2012 10:25:55 +0200
Subject: [PATCHv3 4/6] ARM: OMAP3 PM: Enable IO Wake up
In-Reply-To: <4F4F1CBA.7040502@ti.com>
References: <1330525621-29836-1-git-send-email-t-kristo@ti.com>
 <1330525621-29836-5-git-send-email-t-kristo@ti.com>
 <4F4F1CBA.7040502@ti.com>
Message-ID: <1330590355.2116.74.camel@sokoban>

On Thu, 2012-03-01 at 12:22 +0530, Rajendra Nayak wrote:
> On Wednesday 29 February 2012 07:56 PM, Tero Kristo wrote:
> > From: Vishwanath BS<vishwanath.bs at ti.com>
> >
> > Enable IO Wake up for OMAP3 as part of PM Init. Currently this has been
> > managed in cpuidle path which is not the right place. Subsequent patch
> > will remove IO Daisy chain handling in cpuidle path once daisy chain is
> > handled as part of hwmod mux.
> >
> > Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com>
> > Tested-by: Govindraj.R<govindraj.raja at ti.com>
> > Signed-off-by: Tero Kristo<t-kristo at ti.com>
> > ---
> >   arch/arm/mach-omap2/pm34xx.c |    4 ++++
> >   1 files changed, 4 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> > index e97ec3f..e6c2d39 100644
> > --- a/arch/arm/mach-omap2/pm34xx.c
> > +++ b/arch/arm/mach-omap2/pm34xx.c
> > @@ -793,6 +793,10 @@ static int __init omap3_pm_init(void)
> >   		goto err1;
> >   	}
> >
> > +	if (omap3_has_io_wakeup())
> > +		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
> > +					   PM_WKEN);
> 
> On OMAP4 this GLOBAL IO chain enable happens as part of the trigger
> function itself, it might make sense to do that for OMAP3 too to avoid
> similar issues as seen on OMAP4 when the GLOBAL switch is enabled too
> late in boot. The best however would be to get rid of it in the trigger
> function and enable this early during PM init, but I am not sure whats
> a good place to do this 'early' enough.

Sounds good. This will take care of the comment from Paul also.

-Tero

> 
> regards,
> Rajendra
> 
> > +
> >   	ret = pwrdm_for_each(pwrdms_setup, NULL);
> >   	if (ret) {
> >   		printk(KERN_ERR "Failed to setup powerdomains\n");
> 




From t-kristo at ti.com  Thu Mar  1 03:28:04 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Thu, 1 Mar 2012 10:28:04 +0200
Subject: [PATCHv3 2/6] ARM: OMAP3 PM: Move IO Daisychain function to
 omap3 prm file
In-Reply-To: <4F4F1BFD.4020903@ti.com>
References: <1330525621-29836-1-git-send-email-t-kristo@ti.com>
 <1330525621-29836-3-git-send-email-t-kristo@ti.com>
 <4F4F1BFD.4020903@ti.com>
Message-ID: <1330590484.2116.76.camel@sokoban>

On Thu, 2012-03-01 at 12:19 +0530, Rajendra Nayak wrote:
> On Wednesday 29 February 2012 07:56 PM, Tero Kristo wrote:
> > From: Vishwanath BS<vishwanath.bs at ti.com>
> >
> > Since IO Daisychain modifies only PRM registers, it makes sense to move
> > it to PRM File.
> >
> > Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com>
> > Tested-by: Govindraj.R<govindraj.raja at ti.com>
> > Signed-off-by: Tero Kristo<t-kristo at ti.com>
> > ---
> >   arch/arm/mach-omap2/pm34xx.c       |   30 +-----------------------------
> >   arch/arm/mach-omap2/prm2xxx_3xxx.c |   32 ++++++++++++++++++++++++++++++++
> >   arch/arm/mach-omap2/prm2xxx_3xxx.h |   14 ++++++++++++++
> >   3 files changed, 47 insertions(+), 29 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> > index b0821a8..e97ec3f 100644
> > --- a/arch/arm/mach-omap2/pm34xx.c
> > +++ b/arch/arm/mach-omap2/pm34xx.c
> > @@ -85,34 +85,6 @@ static inline void omap3_per_restore_context(void)
> >   	omap_gpio_restore_context();
> >   }
> >
> > -static void omap3_enable_io_chain(void)
> > -{
> > -	int timeout = 0;
> > -
> > -	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> > -				   PM_WKEN);
> > -	/* Do a readback to assure write has been done */
> > -	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
> > -
> > -	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST)&
> > -		 OMAP3430_ST_IO_CHAIN_MASK)) {
> > -		timeout++;
> > -		if (timeout>  1000) {
> > -			pr_err("Wake up daisy chain activation failed.\n");
> > -			return;
> > -		}
> > -	}
> > -	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> > -			PM_WKEN);
> > -
> > -}
> > -
> > -static void omap3_disable_io_chain(void)
> > -{
> > -	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> > -				     PM_WKEN);
> > -}
> > -
> >   static void omap3_core_save_context(void)
> >   {
> >   	omap3_ctrl_save_padconf();
> > @@ -324,7 +296,7 @@ void omap_sram_idle(void)
> >   	     core_next_state<  PWRDM_POWER_ON)) {
> >   		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
> >   		if (omap3_has_io_chain_ctrl())
> > -			omap3_enable_io_chain();
> > +			omap3_trigger_io_chain();
> >   	}
> >
> >   	pwrdm_pre_transition();
> > diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> > index 9ce7654..fc98781 100644
> > --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
> > +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> > @@ -301,6 +301,38 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
> >   				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
> >   }
> >
> > +/**
> > + * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
> > + * the I/O ring after asserting WUCLKIN high
> > + */
> > +#define MAX_IOPAD_LATCH_TIME 1000
> 
> Since we are changing the implementation to use omap_test_timeout()
> in this patch, it makes sense to make this 100 so we have a max 100us
> delay, similar to what we did on OMAP4.

I didn't change this timeout as I wasn't quite sure what is a safe value
for it. Do you know if 100us is safe for omap3 also in all possible
scenarios?

> 
> > +
> > +/* OMAP3 Daisychain enable sequence */
> > +void omap3_trigger_io_chain(void)
> > +{
> > +	int i = 0;
> > +
> > +	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> > +				   PM_WKEN);
> > +	/* Do a readback to assure write has been done */
> > +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
> > +
> > +	omap_test_timeout(((omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST)&
> > +			    OMAP3430_ST_IO_CHAIN_MASK) == 1),
> > +			  MAX_IOPAD_LATCH_TIME, i);
> > +
> > +	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> > +				     PM_WKEN);
> 
> The comment from Djamil should hold good here too. We should wait for
> IO chain status to show 0 here.

Hmm okay, I'll address this also for next version.

-Tero


> 
> > +}
> > +
> 
> regards,
> Rajendra




From javier.martin at vista-silicon.com  Thu Mar  1 03:37:54 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Thu, 1 Mar 2012 09:37:54 +0100
Subject: [RFC] Merge 'arch/arm/mach-imx/dma-v1.c' into 'drivers/dma/imx-dma.c'
Message-ID: <CACKLOr0gR12p0i7nVeyLiMn3Bay01tj+5QTqV2QAcYeX+fxu=Q@mail.gmail.com>

Hi,
as you know my goal is implementing dma interleave support to imx-dma.
I tried this (among other things) with the following series:
[PATCH 0/4] dmaengine: i.MX DMA series.

However, patches 2 an 3 of the series modified 'drivers/dma/imx-dma.c'
file. So, Sascha and Vinod were quite reluctant to merge the series
just for that reason arguing that this file was meant to be removed.

Then I sent a v2 version of my series dropping the problematic patches:
[PATCH v2 0/2] dmaengine: i.MX DMA series.

I'm still encouraged to achieve my original goal of adding interleave
support but I don't want my work to be blocked again. For this purpose
I want to inform you previously that I will prepare another series
with the following patches:

1. Merge 'arch/arm/mach-imx/dma-v1.c' into 'drivers/dma/imx-dma.c'
2. Provide support for dma interleaved.

I will develop this on top of my previous series, so it would be great
if you could merge it as soon as possible in order to have a decent
base to work on.

Regards.
-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From bill4carson at gmail.com  Thu Mar  1 03:44:13 2012
From: bill4carson at gmail.com (bill4carson)
Date: Thu, 01 Mar 2012 16:44:13 +0800
Subject: [PATCH 7/7] Minor compiling fix
In-Reply-To: <201202291235.04113.arnd@arndb.de>
References: <1329126268-11032-1-git-send-email-bill4carson@gmail.com>
 <1329126268-11032-8-git-send-email-bill4carson@gmail.com>
 <201202291235.04113.arnd@arndb.de>
Message-ID: <4F4F36DD.3020005@gmail.com>



On 2012?02?29? 20:35, Arnd Bergmann wrote:
> On Monday 13 February 2012, Bill Carson wrote:
>> --- a/arch/arm/mm/dma-mapping.c
>> +++ b/arch/arm/mm/dma-mapping.c
>> @@ -152,9 +152,6 @@ static struct arm_vmregion_head consistent_head = {
>>          .vm_end         = CONSISTENT_END,
>>   };
>>
>> -#ifdef CONFIG_HUGETLB_PAGE
>> -#error ARM Coherent DMA allocator does not (yet) support huge TLB
>> -#endif
>
> This one needs an explanation, too. What has changed that now allows
> dma_alloc_coherent to work with CONFIG_HUGETLB_PAGE set that did not
> work before?
>

AFAIK, __dma_alloc has the finest granularity at 4k page size even when
user requests 1M bytes memory.

but current hugetlb low level set_hugepte_at *ONLY*/*MUST* support 2M 
page mapping, so it can't be used to create huge dma mapping in a more
general way.

comments this error out doesn't mean that it could support huge page dma
mapping now with this patch, just shut up gcc when compiling.

Adding a single low level hook to create 1M page mapping can satisfy
the needs, but apparently that's out of hugetlb scope.
And it's on my TODO list :)



> In general, please add a description with each patch you send, following
> the instructions in Documentation/SubmittingPatches.
>

Thanks, I will follow the rules.

> 	Arnd
>

-- 
I am a slow learner
but I will keep trying to fight for my dreams!

--bill


From rnayak at ti.com  Thu Mar  1 03:43:27 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 01 Mar 2012 14:13:27 +0530
Subject: [PATCHv3 2/6] ARM: OMAP3 PM: Move IO Daisychain function to omap3
 prm file
In-Reply-To: <1330590484.2116.76.camel@sokoban>
References: <1330525621-29836-1-git-send-email-t-kristo@ti.com>	
 <1330525621-29836-3-git-send-email-t-kristo@ti.com>	
 <4F4F1BFD.4020903@ti.com> <1330590484.2116.76.camel@sokoban>
Message-ID: <4F4F36AF.5010000@ti.com>

On Thursday 01 March 2012 01:58 PM, Tero Kristo wrote:
> On Thu, 2012-03-01 at 12:19 +0530, Rajendra Nayak wrote:
>> On Wednesday 29 February 2012 07:56 PM, Tero Kristo wrote:
>>> From: Vishwanath BS<vishwanath.bs at ti.com>
>>>
>>> Since IO Daisychain modifies only PRM registers, it makes sense to move
>>> it to PRM File.
>>>
>>> Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com>
>>> Tested-by: Govindraj.R<govindraj.raja at ti.com>
>>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
>>> ---
>>>    arch/arm/mach-omap2/pm34xx.c       |   30 +-----------------------------
>>>    arch/arm/mach-omap2/prm2xxx_3xxx.c |   32 ++++++++++++++++++++++++++++++++
>>>    arch/arm/mach-omap2/prm2xxx_3xxx.h |   14 ++++++++++++++
>>>    3 files changed, 47 insertions(+), 29 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>>> index b0821a8..e97ec3f 100644
>>> --- a/arch/arm/mach-omap2/pm34xx.c
>>> +++ b/arch/arm/mach-omap2/pm34xx.c
>>> @@ -85,34 +85,6 @@ static inline void omap3_per_restore_context(void)
>>>    	omap_gpio_restore_context();
>>>    }
>>>
>>> -static void omap3_enable_io_chain(void)
>>> -{
>>> -	int timeout = 0;
>>> -
>>> -	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
>>> -				   PM_WKEN);
>>> -	/* Do a readback to assure write has been done */
>>> -	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
>>> -
>>> -	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST)&
>>> -		 OMAP3430_ST_IO_CHAIN_MASK)) {
>>> -		timeout++;
>>> -		if (timeout>   1000) {
>>> -			pr_err("Wake up daisy chain activation failed.\n");
>>> -			return;
>>> -		}
>>> -	}
>>> -	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
>>> -			PM_WKEN);
>>> -
>>> -}
>>> -
>>> -static void omap3_disable_io_chain(void)
>>> -{
>>> -	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
>>> -				     PM_WKEN);
>>> -}
>>> -
>>>    static void omap3_core_save_context(void)
>>>    {
>>>    	omap3_ctrl_save_padconf();
>>> @@ -324,7 +296,7 @@ void omap_sram_idle(void)
>>>    	     core_next_state<   PWRDM_POWER_ON)) {
>>>    		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
>>>    		if (omap3_has_io_chain_ctrl())
>>> -			omap3_enable_io_chain();
>>> +			omap3_trigger_io_chain();
>>>    	}
>>>
>>>    	pwrdm_pre_transition();
>>> diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
>>> index 9ce7654..fc98781 100644
>>> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
>>> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
>>> @@ -301,6 +301,38 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
>>>    				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
>>>    }
>>>
>>> +/**
>>> + * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
>>> + * the I/O ring after asserting WUCLKIN high
>>> + */
>>> +#define MAX_IOPAD_LATCH_TIME 1000
>>
>> Since we are changing the implementation to use omap_test_timeout()
>> in this patch, it makes sense to make this 100 so we have a max 100us
>> delay, similar to what we did on OMAP4.
>
> I didn't change this timeout as I wasn't quite sure what is a safe value
> for it. Do you know if 100us is safe for omap3 also in all possible
> scenarios?

The IO daisy implementation is essentially the same on OMAP3 and OMAP4.
I looped in Nilesh again who can shout if it isn't.

Besides the previous implementation was just a loop of 1000  (not using
omap_test_timeout() which internally does udelay(1)) and that should be
always less than 100us even with MPU at the lowest OPP on OMAP3.

>
>>
>>> +
>>> +/* OMAP3 Daisychain enable sequence */
>>> +void omap3_trigger_io_chain(void)
>>> +{
>>> +	int i = 0;
>>> +
>>> +	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
>>> +				   PM_WKEN);
>>> +	/* Do a readback to assure write has been done */
>>> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
>>> +
>>> +	omap_test_timeout(((omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST)&
>>> +			    OMAP3430_ST_IO_CHAIN_MASK) == 1),
>>> +			  MAX_IOPAD_LATCH_TIME, i);
>>> +
>>> +	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
>>> +				     PM_WKEN);
>>
>> The comment from Djamil should hold good here too. We should wait for
>> IO chain status to show 0 here.
>
> Hmm okay, I'll address this also for next version.
>
> -Tero
>
>
>>
>>> +}
>>> +
>>
>> regards,
>> Rajendra
>
>



From santosh.shilimkar at ti.com  Thu Mar  1 04:09:36 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Thu, 1 Mar 2012 14:39:36 +0530
Subject: Randconfig module build error with OMAP4_ERRATA_I688
In-Reply-To: <20120229173719.GN18901@atomide.com>
References: <20120229173719.GN18901@atomide.com>
Message-ID: <CAMQu2gxg_57AVW+MT_Sgi+gr2OUge-YPdSUxoG+z-zQth=4-UA@mail.gmail.com>

On Wed, Feb 29, 2012 at 11:07 PM, Tony Lindgren <tony at atomide.com> wrote:
> Hi Santosh,
>
> Looks like OMAP4_ERRATA_I688 still has one more issue:
> Modules won't build at least with the attached randconfig
> generated file.
>
> Can you please take a look at how to deal with it?
>
> Maybe omap_bus_sync should be an inline function with some
> wrapper for the sleep44xx.S to call?
>
> I already posted a fix for the GPMC related error with the
> same .config file.
>
This one builds for me against 'Linux 3.3-rc5,
Ofocurse I got below error with the attached .config which
I bypassed to see the Errata build failure.

arch/arm/mach-omap2/built-in.o: In function `n8x0_mmc_callback':
linux-2.6/arch/arm/mach-omap2/board-n8x0.c:374: undefined reference to
`omap_mmc_notify_cover_event'
make: *** [.tmp_vmlinux1] Error 1

I build this with below toolchain...
$arm-none-linux-gnueabi-gcc --version
arm-none-linux-gnueabi-gcc (Sourcery G++ Lite 2011.03-41) 4.5.2
Copyright (C) 2010 Free Software Foundation, Inc.

Am I missing anything ?

Regards
Santosh


From paul.liu at linaro.org  Thu Mar  1 04:10:51 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Thu,  1 Mar 2012 17:10:51 +0800
Subject: [PATCH v5 1/2] mfd: Add anatop mfd driver
In-Reply-To: <1328734286-30091-1-git-send-email-paul.liu@linaro.org>
References: <1328734286-30091-1-git-send-email-paul.liu@linaro.org>
Message-ID: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
Anatop provides regulators and thermal.
This driver handles the address space and the operation of the mfd device.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/mfd/Kconfig        |    6 ++
 drivers/mfd/Makefile       |    1 +
 drivers/mfd/anatop-mfd.c   |  144 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/anatop.h |   40 ++++++++++++
 4 files changed, 191 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mfd/anatop-mfd.c
 create mode 100644 include/linux/mfd/anatop.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index f147395..f787d17 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -830,6 +830,12 @@ config MFD_INTEL_MSIC
 	  Passage) chip. This chip embeds audio, battery, GPIO, etc.
 	  devices used in Intel Medfield platforms.
 
+config MFD_ANATOP
+        bool "Support for Anatop"
+	depends on SOC_IMX6Q
+	help
+	  Select this option to enable Anatop MFD driver.
+
 endmenu
 endif
 
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b953bab..8e11060 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -112,3 +112,4 @@ obj-$(CONFIG_TPS65911_COMPARATOR)	+= tps65911-comparator.o
 obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
 obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
 obj-$(CONFIG_MFD_S5M_CORE)	+= s5m-core.o s5m-irq.o
+obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
new file mode 100644
index 0000000..86e2b8e
--- /dev/null
+++ b/drivers/mfd/anatop-mfd.c
@@ -0,0 +1,144 @@
+/*
+ * Anatop MFD driver
+ *
+ * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ * Copyright (C) 2012 Linaro
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+
+u32 anatop_get_bits(struct anatop *adata, u32 addr, int bit_shift, int bits)
+{
+	u32 val;
+	int mask;
+
+	if (bits == 32)
+		mask = ~0;
+	else
+		mask = (1 << bits) - 1;
+
+	spin_lock(&adata->reglock);
+	val = readl(adata->ioreg + addr);
+	spin_unlock(&adata->reglock);
+	val = (val >> bit_shift) & mask;
+
+	return val;
+}
+EXPORT_SYMBOL(anatop_get_bits);
+
+void anatop_set_bits(struct anatop *adata, u32 addr, int bit_shift,
+		     int bits, u32 data)
+{
+	u32 val;
+	int mask;
+	if (bits == 32)
+		mask = ~0;
+	else
+		mask = (1 << bits) - 1;
+
+	spin_lock(&adata->reglock);
+	val = readl(adata->ioreg + addr) & ~(mask << bit_shift);
+	writel((data << bit_shift) | val, adata->ioreg);
+	spin_unlock(&adata->reglock);
+}
+EXPORT_SYMBOL(anatop_set_bits);
+
+static const struct of_device_id of_anatop_subdevice_match[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ .compatible = "fsl,anatop-thermal", },
+	{ },
+};
+
+static int of_anatop_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	void *ioreg;
+	struct anatop *drvdata;
+
+	ioreg = of_iomap(np, 0);
+	if (!ioreg)
+		return -EINVAL;
+	drvdata = devm_kzalloc(dev, sizeof(struct anatop), GFP_KERNEL);
+	if (!drvdata)
+		return -EINVAL;
+	drvdata->ioreg = ioreg;
+	spin_lock_init(&drvdata->reglock);
+	platform_set_drvdata(pdev, drvdata);
+	of_platform_bus_probe(np, of_anatop_subdevice_match, dev);
+
+	return 0;
+}
+
+static int of_anatop_remove(struct platform_device *pdev)
+{
+	struct anatop *drvdata;
+	drvdata = platform_get_drvdata(pdev);
+	iounmap(drvdata->ioreg);
+	return 0;
+}
+
+static const struct of_device_id of_anatop_match[] = {
+	{ .compatible = "fsl,imx6q-anatop", },
+	{ },
+};
+
+static struct platform_driver anatop_of_driver = {
+	.driver = {
+		.name = "anatop-mfd",
+		.owner = THIS_MODULE,
+		.of_match_table = of_anatop_match,
+	},
+	.probe		= of_anatop_probe,
+	.remove		= of_anatop_remove,
+};
+
+static int __init anatop_init(void)
+{
+	return platform_driver_register(&anatop_of_driver);
+}
+postcore_initcall(anatop_init);
+
+static void __exit anatop_exit(void)
+{
+	platform_driver_unregister(&anatop_of_driver);
+}
+module_exit(anatop_exit);
+
+MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP MFD driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
new file mode 100644
index 0000000..22c1007
--- /dev/null
+++ b/include/linux/mfd/anatop.h
@@ -0,0 +1,40 @@
+/*
+ * anatop.h - Anatop MFD driver
+ *
+ *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ *  Copyright (C) 2012 Linaro
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_MFD_ANATOP_H
+#define __LINUX_MFD_ANATOP_H
+
+#include <linux/spinlock.h>
+
+/**
+ * anatop - MFD data
+ * @ioreg: ioremap register
+ * @reglock: spinlock for register read/write
+ */
+struct anatop {
+	void *ioreg;
+	spinlock_t reglock;
+};
+
+extern u32 anatop_get_bits(struct anatop *, u32, int, int);
+extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
+
+#endif /*  __LINUX_MFD_ANATOP_H */
-- 
1.7.9



From paul.liu at linaro.org  Thu Mar  1 04:10:52 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Thu,  1 Mar 2012 17:10:52 +0800
Subject: [PATCH v5 2/2] Regulator: Add Anatop regulator driver
In-Reply-To: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
References: <1328734286-30091-1-git-send-email-paul.liu@linaro.org>
 <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
Message-ID: <1330593052-15184-2-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.

Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Liam Girdwood <lrg at ti.com>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 .../bindings/regulator/anatop-regulator.txt        |   28 +++
 drivers/regulator/Kconfig                          |    6 +
 drivers/regulator/Makefile                         |    1 +
 drivers/regulator/anatop-regulator.c               |  203 ++++++++++++++++++++
 include/linux/regulator/anatop-regulator.h         |   40 ++++
 5 files changed, 278 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.txt
 create mode 100644 drivers/regulator/anatop-regulator.c
 create mode 100644 include/linux/regulator/anatop-regulator.h

diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
new file mode 100644
index 0000000..9ed7326
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -0,0 +1,28 @@
+Anatop Voltage regulators
+
+Required properties:
+- compatible: Must be "fsl,anatop-regulator"
+- vol-bit-shift: Bit shift for the register
+- vol-bit-size: Number of bits used in the register
+- min-bit-val: Minimum value of this register
+- min-voltage: Minimum voltage of this regulator
+- max-voltage: Maximum voltage of this regulator
+
+Any property defined as part of the core regulator
+binding, defined in regulator.txt, can also be used.
+
+Example:
+
+	reg_vddpu: regulator-vddpu at 140 {
+		compatible = "fsl,anatop-regulator";
+		regulator-name = "vddpu";
+		regulator-min-microvolt = <725000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-always-on;
+		reg = <0x140>;
+		vol-bit-shift = <9>;
+		vol-bit-size = <5>;
+		min-bit-val = <1>;
+		min-voltage = <725000>;
+		max-voltage = <1300000>;
+	};
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 7a61b17..5fbcda2 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -335,5 +335,11 @@ config REGULATOR_AAT2870
 	  If you have a AnalogicTech AAT2870 say Y to enable the
 	  regulator driver.
 
+config REGULATOR_ANATOP
+	tristate "ANATOP LDO regulators"
+	depends on MFD_ANATOP
+	help
+	  Say y here to support ANATOP LDOs regulators.
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 503bac8..8440871 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -48,5 +48,6 @@ obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
 obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
 obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
 obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
+obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
new file mode 100644
index 0000000..1f3a878
--- /dev/null
+++ b/drivers/regulator/anatop-regulator.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/anatop-regulator.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regulator/of_regulator.h>
+
+static int anatop_set_voltage(struct regulator_dev *reg, int min_uV,
+				  int max_uV, unsigned *selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	u32 val, sel;
+	int uv;
+
+	uv = min_uV;
+	dev_dbg(&reg->dev, "%s: uv %d, min %d, max %d\n", __func__,
+		uv, anatop_reg->min_voltage,
+		anatop_reg->max_voltage);
+
+	if (uv < anatop_reg->min_voltage) {
+		if (max_uV > anatop_reg->min_voltage)
+			uv = anatop_reg->min_voltage;
+		else
+			return -EINVAL;
+	}
+
+	if (anatop_reg->control_reg) {
+		sel = (uv - anatop_reg->min_voltage) / 25000;
+		if (sel * 25000 + anatop_reg->min_voltage
+		    > anatop_reg->max_voltage)
+			return -EINVAL;
+		val = anatop_reg->min_bit_val + sel;
+		*selector = sel;
+		dev_dbg(&reg->dev, "%s: calculated val %d\n", __func__, val);
+		anatop_set_bits(anatop_reg->mfd,
+				anatop_reg->control_reg,
+				anatop_reg->vol_bit_shift,
+				anatop_reg->vol_bit_size,
+				val);
+		return 0;
+	} else {
+		return -ENOTSUPP;
+	}
+}
+
+static int anatop_get_voltage_sel(struct regulator_dev *reg)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int selector;
+
+	if (anatop_reg->control_reg) {
+		u32 val = anatop_get_bits(anatop_reg->mfd,
+					  anatop_reg->control_reg,
+					  anatop_reg->vol_bit_shift,
+					  anatop_reg->vol_bit_size);
+		selector = val - anatop_reg->min_bit_val;
+		return selector;
+	} else {
+		return -ENOTSUPP;
+	}
+}
+
+static int anatop_list_voltage(struct regulator_dev *reg, unsigned selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int uv;
+
+	uv = anatop_reg->min_voltage + selector * 25000;
+	dev_dbg(&reg->dev, "vddio = %d, selector = %u\n", uv, selector);
+
+	return uv;
+}
+
+static struct regulator_ops anatop_rops = {
+	.set_voltage     = anatop_set_voltage,
+	.get_voltage_sel = anatop_get_voltage_sel,
+	.list_voltage    = anatop_list_voltage,
+};
+
+int anatop_regulator_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct regulator_desc *rdesc;
+	struct regulator_dev *rdev;
+	struct anatop_regulator *sreg;
+	struct regulator_init_data *initdata;
+	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
+	const __be32 *rval;
+	u64 ofsize;
+
+	initdata = of_get_regulator_init_data(dev, dev->of_node);
+	sreg = devm_kzalloc(dev, sizeof(struct anatop_regulator), GFP_KERNEL);
+	if (!sreg)
+		return -EINVAL;
+	rdesc = devm_kzalloc(dev, sizeof(struct regulator_desc), GFP_KERNEL);
+	if (!rdesc)
+		return -EINVAL;
+	sreg->initdata = initdata;
+	sreg->regulator = rdesc;
+	memset(rdesc, 0, sizeof(struct regulator_desc));
+	rdesc->name = kstrdup(of_get_property(np, "regulator-name", NULL),
+			      GFP_KERNEL);
+	rdesc->ops = &anatop_rops;
+	rdesc->type = REGULATOR_VOLTAGE;
+	rdesc->owner = THIS_MODULE;
+	sreg->name = rdesc->name;
+	sreg->mfd = anatopmfd;
+	rval = of_get_address(np, 0, &ofsize, NULL);
+	if (rval)
+		sreg->control_reg = be32_to_cpu(*rval);
+	rval = of_get_property(np, "vol-bit-size", NULL);
+	if (rval)
+		sreg->vol_bit_size = be32_to_cpu(*rval);
+	rval = of_get_property(np, "vol-bit-shift", NULL);
+	if (rval)
+		sreg->vol_bit_shift = be32_to_cpu(*rval);
+	rval = of_get_property(np, "min-bit-val", NULL);
+	if (rval)
+		sreg->min_bit_val = be32_to_cpu(*rval);
+	rval = of_get_property(np, "min-voltage", NULL);
+	if (rval)
+		sreg->min_voltage = be32_to_cpu(*rval);
+	rval = of_get_property(np, "max-voltage", NULL);
+	if (rval)
+		sreg->max_voltage = be32_to_cpu(*rval);
+
+	/* register regulator */
+	rdev = regulator_register(rdesc, &pdev->dev,
+				  initdata, sreg, pdev->dev.of_node);
+	platform_set_drvdata(pdev, rdev);
+
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			rdesc->name);
+		kfree(rdesc->name);
+		return PTR_ERR(rdev);
+	}
+
+	return 0;
+}
+
+int anatop_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+	regulator_unregister(rdev);
+	return 0;
+}
+
+struct of_device_id __devinitdata of_anatop_regulator_match_tbl[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ /* end */ }
+};
+
+struct platform_driver anatop_regulator = {
+	.driver = {
+		.name	= "anatop_regulator",
+		.owner  = THIS_MODULE,
+		.of_match_table = of_anatop_regulator_match_tbl,
+	},
+	.probe	= anatop_regulator_probe,
+	.remove	= anatop_regulator_remove,
+};
+
+int anatop_regulator_init(void)
+{
+	return platform_driver_register(&anatop_regulator);
+}
+postcore_initcall(anatop_regulator_init);
+
+void anatop_regulator_exit(void)
+{
+	platform_driver_unregister(&anatop_regulator);
+}
+module_exit(anatop_regulator_exit);
+
+MODULE_DESCRIPTION("ANATOP Regulator driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/regulator/anatop-regulator.h b/include/linux/regulator/anatop-regulator.h
new file mode 100644
index 0000000..7a9a05b
--- /dev/null
+++ b/include/linux/regulator/anatop-regulator.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ANATOP_REGULATOR_H
+#define __ANATOP_REGULATOR_H
+
+#include <linux/regulator/driver.h>
+#include <linux/mfd/anatop.h>
+
+struct anatop_regulator {
+	struct regulator_desc *regulator;
+	struct regulator_init_data *initdata;
+	const char *name;
+	u32 control_reg;
+	struct anatop *mfd;
+	int vol_bit_shift;
+	int vol_bit_size;
+	int min_bit_val;
+	int min_voltage;
+	int max_voltage;
+};
+
+#endif /* __ANATOP_REGULATOR_H */
-- 
1.7.9



From grinberg at compulab.co.il  Thu Mar  1 04:19:04 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Thu,  1 Mar 2012 11:19:04 +0200
Subject: [PATCH 2/2] ARM: OMAP3: cm-t3517: add EMAC support
In-Reply-To: <1324423590-32489-1-git-send-email-yanok@emcraft.com>
References: <1324423590-32489-1-git-send-email-yanok@emcraft.com>
Message-ID: <1330593544-25411-2-git-send-email-grinberg@compulab.co.il>

Add support for the EMAC Ethernet controller in the AM35xx SoC.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/mach-omap2/board-cm-t3517.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index f36d694..9e66e16 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -49,6 +49,7 @@
 #include "mux.h"
 #include "control.h"
 #include "common-board-devices.h"
+#include "am35xx-emac.h"
 
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
 static struct gpio_led cm_t3517_leds[] = {
@@ -291,6 +292,7 @@ static void __init cm_t3517_init(void)
 	cm_t3517_init_rtc();
 	cm_t3517_init_usbh();
 	cm_t3517_init_hecc();
+	am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 }
 
 MACHINE_START(CM_T3517, "Compulab CM-T3517")
-- 
1.7.3.4



From grinberg at compulab.co.il  Thu Mar  1 04:19:03 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Thu,  1 Mar 2012 11:19:03 +0200
Subject: [PATCH v3 1/2] ARM: OMAP: move generic EMAC init to separate file
In-Reply-To: <1324423590-32489-1-git-send-email-yanok@emcraft.com>
References: <1324423590-32489-1-git-send-email-yanok@emcraft.com>
Message-ID: <1330593544-25411-1-git-send-email-grinberg@compulab.co.il>

From: Ilya Yanok <yanok at emcraft.com>

AM35xx SoCs include DaVinci EMAC IP. Initialization code in
board-am3517evm.c is pretty board independent and will work for any
AM35xx based board so move this code to it's own file to be reused by
other boards.

Signed-off-by: Ilya Yanok <yanok at emcraft.com>
Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
v3:	- use DEFINE_RES_* macros
	- check error of platform_device_register()
	- introduce a default MDIO bus frequency define

Tony, this patch has been floating for about two months:
http://www.spinics.net/lists/linux-omap/msg62160.html
can it be applied for 3.4?

Thanks

 arch/arm/mach-omap2/Makefile          |    3 +
 arch/arm/mach-omap2/am35xx-emac.c     |  117 +++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/am35xx-emac.h     |   15 ++++
 arch/arm/mach-omap2/board-am3517evm.c |  117 +--------------------------------
 4 files changed, 137 insertions(+), 115 deletions(-)
 create mode 100644 arch/arm/mach-omap2/am35xx-emac.c
 create mode 100644 arch/arm/mach-omap2/am35xx-emac.h

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 56a6e98..64f79da 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -267,4 +267,7 @@ smsc911x-$(CONFIG_SMSC911X)		:= gpmc-smsc911x.o
 obj-y					+= $(smsc911x-m) $(smsc911x-y)
 obj-$(CONFIG_ARCH_OMAP4)		+= hwspinlock.o
 
+emac-$(CONFIG_TI_DAVINCI_EMAC)		:= am35xx-emac.o
+obj-y					+= $(emac-m) $(emac-y)
+
 obj-y					+= common-board-devices.o twl-common.o
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
new file mode 100644
index 0000000..1f97e74
--- /dev/null
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * Based on mach-omap2/board-am3517evm.c
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ * Author: Ranjith Lohithakshan <ranjithl at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/davinci_emac.h>
+#include <linux/platform_device.h>
+#include <plat/irqs.h>
+#include <mach/am35xx.h>
+
+#include "control.h"
+
+static struct mdio_platform_data am35xx_emac_mdio_pdata;
+
+static struct resource am35xx_emac_mdio_resources[] = {
+	DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K),
+};
+
+static struct platform_device am35xx_emac_mdio_device = {
+	.name		= "davinci_mdio",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(am35xx_emac_mdio_resources),
+	.resource	= am35xx_emac_mdio_resources,
+	.dev.platform_data = &am35xx_emac_mdio_pdata,
+};
+
+static void am35xx_enable_emac_int(void)
+{
+	u32 regval;
+
+	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+	regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
+		  AM35XX_CPGMAC_C0_TX_PULSE_CLR |
+		  AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
+		  AM35XX_CPGMAC_C0_RX_THRESH_CLR);
+	omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
+	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+}
+
+static void am35xx_disable_emac_int(void)
+{
+	u32 regval;
+
+	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+	regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
+		  AM35XX_CPGMAC_C0_TX_PULSE_CLR);
+	omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
+	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+}
+
+static struct emac_platform_data am35xx_emac_pdata = {
+	.ctrl_reg_offset	= AM35XX_EMAC_CNTRL_OFFSET,
+	.ctrl_mod_reg_offset	= AM35XX_EMAC_CNTRL_MOD_OFFSET,
+	.ctrl_ram_offset	= AM35XX_EMAC_CNTRL_RAM_OFFSET,
+	.ctrl_ram_size		= AM35XX_EMAC_CNTRL_RAM_SIZE,
+	.hw_ram_addr		= AM35XX_EMAC_HW_RAM_ADDR,
+	.version		= EMAC_VERSION_2,
+	.interrupt_enable	= am35xx_enable_emac_int,
+	.interrupt_disable	= am35xx_disable_emac_int,
+};
+
+static struct resource am35xx_emac_resources[] = {
+	DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000),
+	DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ),
+	DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ),
+	DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ),
+	DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ),
+};
+
+static struct platform_device am35xx_emac_device = {
+	.name		= "davinci_emac",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(am35xx_emac_resources),
+	.resource	= am35xx_emac_resources,
+	.dev		= {
+		.platform_data	= &am35xx_emac_pdata,
+	},
+};
+
+void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
+{
+	unsigned int regval;
+	int err;
+
+	am35xx_emac_pdata.rmii_en = rmii_en;
+	am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq;
+	err = platform_device_register(&am35xx_emac_device);
+	if (err) {
+		pr_err("AM35x: failed registering EMAC device: %d\n", err);
+		return;
+	}
+
+	err = platform_device_register(&am35xx_emac_mdio_device);
+	if (err) {
+		pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err);
+		platform_device_unregister(&am35xx_emac_device);
+		return;
+	}
+
+	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+	regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
+	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+}
diff --git a/arch/arm/mach-omap2/am35xx-emac.h b/arch/arm/mach-omap2/am35xx-emac.h
new file mode 100644
index 0000000..15c6f9c
--- /dev/null
+++ b/arch/arm/mach-omap2/am35xx-emac.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define AM35XX_DEFAULT_MDIO_FREQUENCY	1000000
+
+#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
+void am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en);
+#else
+static inline void am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) {}
+#endif
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 71138a1..3645285 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -39,124 +39,11 @@
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-dvi.h>
 
+#include "am35xx-emac.h"
 #include "mux.h"
 #include "control.h"
 #include "hsmmc.h"
 
-#define AM35XX_EVM_MDIO_FREQUENCY	(1000000)
-
-static struct mdio_platform_data am3517_evm_mdio_pdata = {
-	.bus_freq	= AM35XX_EVM_MDIO_FREQUENCY,
-};
-
-static struct resource am3517_mdio_resources[] = {
-	{
-		.start  = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET,
-		.end    = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET +
-			  SZ_4K - 1,
-		.flags  = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device am3517_mdio_device = {
-	.name		= "davinci_mdio",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(am3517_mdio_resources),
-	.resource	= am3517_mdio_resources,
-	.dev.platform_data = &am3517_evm_mdio_pdata,
-};
-
-static struct emac_platform_data am3517_evm_emac_pdata = {
-	.rmii_en	= 1,
-};
-
-static struct resource am3517_emac_resources[] = {
-	{
-		.start  = AM35XX_IPSS_EMAC_BASE,
-		.end    = AM35XX_IPSS_EMAC_BASE + 0x2FFFF,
-		.flags  = IORESOURCE_MEM,
-	},
-	{
-		.start  = INT_35XX_EMAC_C0_RXTHRESH_IRQ,
-		.end    = INT_35XX_EMAC_C0_RXTHRESH_IRQ,
-		.flags  = IORESOURCE_IRQ,
-	},
-	{
-		.start  = INT_35XX_EMAC_C0_RX_PULSE_IRQ,
-		.end    = INT_35XX_EMAC_C0_RX_PULSE_IRQ,
-		.flags  = IORESOURCE_IRQ,
-	},
-	{
-		.start  = INT_35XX_EMAC_C0_TX_PULSE_IRQ,
-		.end    = INT_35XX_EMAC_C0_TX_PULSE_IRQ,
-		.flags  = IORESOURCE_IRQ,
-	},
-	{
-		.start  = INT_35XX_EMAC_C0_MISC_PULSE_IRQ,
-		.end    = INT_35XX_EMAC_C0_MISC_PULSE_IRQ,
-		.flags  = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device am3517_emac_device = {
-	.name		= "davinci_emac",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(am3517_emac_resources),
-	.resource	= am3517_emac_resources,
-};
-
-static void am3517_enable_ethernet_int(void)
-{
-	u32 regval;
-
-	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-	regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
-		AM35XX_CPGMAC_C0_TX_PULSE_CLR |
-		AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
-		AM35XX_CPGMAC_C0_RX_THRESH_CLR);
-	omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
-	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-}
-
-static void am3517_disable_ethernet_int(void)
-{
-	u32 regval;
-
-	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-	regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
-		AM35XX_CPGMAC_C0_TX_PULSE_CLR);
-	omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
-	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-}
-
-static void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
-{
-	unsigned int regval;
-
-	pdata->ctrl_reg_offset		= AM35XX_EMAC_CNTRL_OFFSET;
-	pdata->ctrl_mod_reg_offset	= AM35XX_EMAC_CNTRL_MOD_OFFSET;
-	pdata->ctrl_ram_offset		= AM35XX_EMAC_CNTRL_RAM_OFFSET;
-	pdata->ctrl_ram_size		= AM35XX_EMAC_CNTRL_RAM_SIZE;
-	pdata->version			= EMAC_VERSION_2;
-	pdata->hw_ram_addr		= AM35XX_EMAC_HW_RAM_ADDR;
-	pdata->interrupt_enable		= am3517_enable_ethernet_int;
-	pdata->interrupt_disable	= am3517_disable_ethernet_int;
-	am3517_emac_device.dev.platform_data	= pdata;
-	platform_device_register(&am3517_emac_device);
-	platform_device_register(&am3517_mdio_device);
-	clk_add_alias(NULL, dev_name(&am3517_mdio_device.dev),
-		      NULL, &am3517_emac_device.dev);
-
-	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-	regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
-	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
-	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-
-	return ;
-}
-
-
-
 #define LCD_PANEL_PWR		176
 #define LCD_PANEL_BKLIGHT_PWR	182
 #define LCD_PANEL_PWM		181
@@ -498,7 +385,7 @@ static void __init am3517_evm_init(void)
 	i2c_register_board_info(1, am3517evm_i2c1_boardinfo,
 				ARRAY_SIZE(am3517evm_i2c1_boardinfo));
 	/*Ethernet*/
-	am3517_evm_ethernet_init(&am3517_evm_emac_pdata);
+	am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 
 	/* MUSB */
 	am3517_evm_musb_init();
-- 
1.7.3.4



From paul.liu at linaro.org  Thu Mar  1 04:19:47 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Thu, 01 Mar 2012 17:19:47 +0800
Subject: [PATCH v4 1/2] mfd: Add anatop mfd driver
In-Reply-To: <20120221111705.GV5387@sortiz-mobl>
References: <1324980994-18462-1-git-send-email-paul.liu@linaro.org>
 <1328734286-30091-1-git-send-email-paul.liu@linaro.org>
 <20120221111705.GV5387@sortiz-mobl>
Message-ID: <4F4F3F33.4000608@linaro.org>

(2012?02?21? 19:17), Samuel Ortiz wrote:
> Hi Paul,
> 
> I didn't get patch #2, so I don't get to see how the read/write functions ar
> eused for example.
> 

Hi Samuel,

Sorry for late reply.
I've sent out v5 today.

>> +	ioreg = ioremap(ofaddr, ofsize);
>> +	if (!ioreg)
>> +		return -EINVAL;
>> +	drvdata = devm_kzalloc(dev, sizeof(struct anatop), GFP_KERNEL);
>> +	if (!drvdata)
>> +		return -EINVAL;
>> +	drvdata->ioreg = ioreg;
>> +	drvdata->read = anatop_read;
>> +	drvdata->write = anatop_write;
>> +	platform_set_drvdata(pdev, drvdata);
>> +	of_platform_bus_probe(np, of_anatop_regulator_match, dev);
>> +	return ret;
>> +}
> So it seems that your driver here does nothing but extending your device tree
> definition. Correct me if I'm wrong, aren't you trying to fix a broken device
> tree definition here ?
> 

The driver here ioremap the addresses for anatop chip in i.MX6Q SoC. The
addresses are shared by several regulators. Also thermal drivers are
also in the same range.

Here are examples of the anatop description in dts file

   anatop at 020c8000 {
           compatible = "fsl,imx6q-anatop";
           reg = <0x020c8000 0x1000>;
           interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
           #address-cells = <1>;
           #size-cells = <1>;
           reg_vddpu: regulator-vddpu at 140 {
                   compatible = "fsl,anatop-regulator";
                   regulator-name = "vddpu";
                   regulator-min-microvolt = <725000>;
                   regulator-max-microvolt = <1300000>;
                   regulator-always-on;
                   reg = <0x140 1>;
                   vol-bit-shift = <9>;
                   vol-bit-size = <5>;
                   min-bit-val = <1>;
                   min-voltage = <725000>;
                   max-voltage = <1300000>;
           };
           reg_vddcore: regulator-vddcore at 140 {
                   compatible = "fsl,anatop-regulator";
                   regulator-name = "vddcore";
                   regulator-min-microvolt = <725000>;
                   regulator-max-microvolt = <1300000>;
                   regulator-always-on;
                   reg = <0x140 1>;
                   vol-bit-shift = <0>;
                   vol-bit-size = <5>;
                   min-bit-val = <1>;
                   min-voltage = <725000>;
                   max-voltage = <1300000>;
           };
           ...

So both reg_vddpu and reg_vddcore are using the same address.

Yours Sincerely,
Paul


From tushar.behera at linaro.org  Thu Mar  1 04:17:22 2012
From: tushar.behera at linaro.org (Tushar Behera)
Date: Thu,  1 Mar 2012 14:47:22 +0530
Subject: [PATCH 0/4] ARM: SAMSUNG: Add __init attribute to functions calling
 s3c_set_platdata
Message-ID: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>

The function s3c_set_platdata is defined with __init attribute, hence the
functions calling s3c_set_platdata should also be defined with __init
attribute.

Even though all the modified functions are called from xxx_machine_init()
functions, it is still better to define each of them with __init attribute.

Tushar Behera (4):
  ARM: EXYNOS: Add __init attribute to nuri_camera_init()
  ARM: EXYNOS: Add __init attribute to universal_camera_init()
  ARM: SAMSUNG: Add __init attribute to samsung_bl_set()
  ARM: SAMSUNG: Add __init attribute to xxx_set_platdata() wrappers

 arch/arm/mach-exynos/mach-nuri.c           |    2 +-
 arch/arm/mach-exynos/mach-universal_c210.c |    2 +-
 arch/arm/plat-samsung/dev-backlight.c      |    2 +-
 arch/arm/plat-samsung/devs.c               |    4 ++--
 4 files changed, 5 insertions(+), 5 deletions(-)

-- 
1.7.4.1



From tushar.behera at linaro.org  Thu Mar  1 04:17:23 2012
From: tushar.behera at linaro.org (Tushar Behera)
Date: Thu,  1 Mar 2012 14:47:23 +0530
Subject: [PATCH 1/4] ARM: EXYNOS: Add __init attribute to nuri_camera_init()
In-Reply-To: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
References: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <1330593446-663-2-git-send-email-tushar.behera@linaro.org>

s3c_set_platdata() is defined with __init attribute, hence all functions
referencing this function should also be defined with __init attribute.

nuri_camera_init() is referenced only in '__init nuri_machine_init()', thus
this change won't put any additional constraint on the usage of
nuri_camera_init().

Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---
 arch/arm/mach-exynos/mach-nuri.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index a6b9162..7dc5c99 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1255,7 +1255,7 @@ static struct gpio nuri_camera_gpios[] = {
 	{ GPIO_CAM_MEGA_RST,	GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
 };
 
-static void nuri_camera_init(void)
+static void __init nuri_camera_init(void)
 {
 	s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
 			 &s5p_device_mipi_csis0);
-- 
1.7.4.1



From tushar.behera at linaro.org  Thu Mar  1 04:17:24 2012
From: tushar.behera at linaro.org (Tushar Behera)
Date: Thu,  1 Mar 2012 14:47:24 +0530
Subject: [PATCH 2/4] ARM: EXYNOS: Add __init attribute to
 universal_camera_init()
In-Reply-To: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
References: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <1330593446-663-3-git-send-email-tushar.behera@linaro.org>

s3c_set_platdata() is defined with __init attribute, hence all functions
referencing this function should also be defined with __init attribute.

universal_camera_init() is referenced only in '__init universal_machine_init()',
thus this change won't put any additional constraint on the usage of
universal_camera_init().

Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---
 arch/arm/mach-exynos/mach-universal_c210.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 6017a21..be50e5e 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -990,7 +990,7 @@ static struct gpio universal_camera_gpios[] = {
 	{ GPIO_CAM_VGA_NSTBY,	GPIOF_OUT_INIT_LOW,  "CAM_VGA_NSTBY" },
 };
 
-static void universal_camera_init(void)
+static void __init universal_camera_init(void)
 {
 	s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
 			 &s5p_device_mipi_csis0);
-- 
1.7.4.1



From tushar.behera at linaro.org  Thu Mar  1 04:17:25 2012
From: tushar.behera at linaro.org (Tushar Behera)
Date: Thu,  1 Mar 2012 14:47:25 +0530
Subject: [PATCH 3/4] ARM: SAMSUNG: Add __init attribute to samsung_bl_set()
In-Reply-To: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
References: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <1330593446-663-4-git-send-email-tushar.behera@linaro.org>

s3c_set_platdata() is defined with __init attribute, hence all functions
referencing this function should also be defined with __init attribute.

samsung_bl_set() is referenced only in '__init xxx_machine_init()' functions,
thus this change won't put any additional constraint on the usage of
samsung_bl_set().

Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---
 arch/arm/plat-samsung/dev-backlight.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/plat-samsung/dev-backlight.c
index 2254920..5f197dc 100644
--- a/arch/arm/plat-samsung/dev-backlight.c
+++ b/arch/arm/plat-samsung/dev-backlight.c
@@ -77,7 +77,7 @@ static struct platform_device samsung_dfl_bl_device __initdata = {
  * @gpio_info:	structure containing GPIO info for PWM timer
  * @bl_data:	structure containing Backlight control data
  */
-void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
+void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
 	struct platform_pwm_backlight_data *bl_data)
 {
 	int ret = 0;
-- 
1.7.4.1



From tushar.behera at linaro.org  Thu Mar  1 04:17:26 2012
From: tushar.behera at linaro.org (Tushar Behera)
Date: Thu,  1 Mar 2012 14:47:26 +0530
Subject: [PATCH 4/4] ARM: SAMSUNG: Add __init attribute to xxx_set_platdata()
 wrappers
In-Reply-To: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
References: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <1330593446-663-5-git-send-email-tushar.behera@linaro.org>

s3c_set_platdata() is defined with __init attribute, hence all functions
referencing this function should also be defined with __init attribute.

Signed-off-by: Tushar Behera <tushar.behera at linaro.org>
---
 arch/arm/plat-samsung/devs.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 75ff3b0..b7d4cdc 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -782,7 +782,7 @@ struct platform_device s3c_device_cfcon = {
 	.resource	= s3c_cfcon_resource,
 };
 
-void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
+void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
 {
 	s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
 			 &s3c_device_cfcon);
@@ -1062,7 +1062,7 @@ struct platform_device s3c64xx_device_onenand1 = {
 	.resource	= s3c64xx_onenand1_resources,
 };
 
-void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
+void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
 {
 	s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
 			 &s3c64xx_device_onenand1);
-- 
1.7.4.1



From s.nawrocki at samsung.com  Thu Mar  1 04:33:14 2012
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Thu, 01 Mar 2012 10:33:14 +0100
Subject: [PATCH 1/4] ARM: EXYNOS: Add __init attribute to
 nuri_camera_init()
In-Reply-To: <1330593446-663-2-git-send-email-tushar.behera@linaro.org>
References: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
 <1330593446-663-2-git-send-email-tushar.behera@linaro.org>
Message-ID: <4F4F425A.7090302@samsung.com>

On 03/01/2012 10:17 AM, Tushar Behera wrote:
> s3c_set_platdata() is defined with __init attribute, hence all functions
> referencing this function should also be defined with __init attribute.
> 
> nuri_camera_init() is referenced only in '__init nuri_machine_init()', thus
> this change won't put any additional constraint on the usage of
> nuri_camera_init().
> 
> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>

Thanks.

Acked-by: Sylwester Nawrocki <s.nawrocki at samsung.com>






From s.nawrocki at samsung.com  Thu Mar  1 04:33:47 2012
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Thu, 01 Mar 2012 10:33:47 +0100
Subject: [PATCH 2/4] ARM: EXYNOS: Add __init attribute to
 universal_camera_init()
In-Reply-To: <1330593446-663-3-git-send-email-tushar.behera@linaro.org>
References: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
 <1330593446-663-3-git-send-email-tushar.behera@linaro.org>
Message-ID: <4F4F427B.3030502@samsung.com>

On 03/01/2012 10:17 AM, Tushar Behera wrote:
> s3c_set_platdata() is defined with __init attribute, hence all functions
> referencing this function should also be defined with __init attribute.
> 
> universal_camera_init() is referenced only in '__init universal_machine_init()',
> thus this change won't put any additional constraint on the usage of
> universal_camera_init().
> 
> Signed-off-by: Tushar Behera <tushar.behera at linaro.org>

Thanks.

Acked-by: Sylwester Nawrocki <s.nawrocki at samsung.com>


From dave.martin at linaro.org  Thu Mar  1 04:35:33 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 1 Mar 2012 09:35:33 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <1330526664.4270.128.camel@zakaz.uk.xensource.com>
References: <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <1330526664.4270.128.camel@zakaz.uk.xensource.com>
Message-ID: <20120301093533.GB2034@linaro.org>

On Wed, Feb 29, 2012 at 02:44:24PM +0000, Ian Campbell wrote:
> On Wed, 2012-02-29 at 12:58 +0000, Dave Martin wrote:
> > On Wed, Feb 29, 2012 at 09:56:02AM +0000, Ian Campbell wrote:
> > > On Wed, 2012-02-29 at 09:34 +0000, Dave Martin wrote:
> > > > On Tue, Feb 28, 2012 at 12:28:29PM +0000, Stefano Stabellini wrote:
> > > 
> > > > > I don't have a very strong opinion on which register we should use, but
> > > > > I would like to avoid r7 if it is already actively used by gcc.
> > > > 
> > > > But there is no framepointer for Thumb-2 code (?)
> > > 
> > > Peter Maydell suggested there was:
> > > > r7 is (used by gcc as) the Thumb frame pointer; I don't know if this
> > > > makes it worth avoiding in this context.
> > > 
> > > Sounds like it might be a gcc-ism, possibly a non-default option?
> > > 
> > > Anyway, I think r12 will be fine for our purposes so the point is rather
> > > moot.
> > 
> > Just had a chat with some tools guys -- apparently, when passing register
> > arguments to gcc inline asms there really isn't a guarantee that those
> > variables will be in the expected registers on entry to the inline asm.
> > 
> > If gcc reorders other function calls or other code around the inline asm
> > (which it can do, except under certain controlled situations), then
> > intervening code can clobber any registers in general.
> > 
> > Or, to summarise another way, there is no way to control which register
> > is used to pass something to an inline asm in general (often we get away
> > with this, and there are a lot of inline asms in the kernel that assume
> > it works, but the more you inline the more likely you are to get nasty
> > surprises).  There is no workaroud, except on some architectures where
> > special asm constraints allow specific individual registers to be
> > specified for operands (i386 for example).
> 
> I had assumed I just couldn't find the right syntax. Useful to know that
> I couldn't find it because it doesn't exist!
> 
> > If you need a specific register, this means that you must set up that
> > register explicitly inside the asm if you want a guarantee that the
> > code will work:
> > 
> > 	asm volatile (
> > 		"movw	r12, %[hvc_num]\n\t"
> 
> Is gcc (or gas?) smart enough to optimise this away if it turns out that
> %[hvc_num] == r12?

No, unfortunately.  Except for the information defined by the constraints,
the inline asm block is completely opaque to the compiler (except for
pasting in operands -- which is a string operation done with no knowledge
of what the text means for the assembler).

> 
> > 		...
> > 		"hvc	#0"
> > 		:: [hvc_num] "i" (NUMBER) : "r12"
> > 	);
> > 
> > Of course, if you need to set up more than about 5 or 6 registers in
> > this way, the doubled register footprint means that the compiler will
> > have to start spilling stuff to the stack.
> > 
> > 
> > This is the kind of problem which goes away when out-of-lining the
> > hvc wrapper behind a C function interface, since the ABI then provides
> > guarantees about how values are mershaled into and out of that code.
> 
> I don't think anything would stop gcc from clobbering an argument
> register right on function entry (e..g it might move r0 to r8 and
> clobber r0, for whatever reason), so that they are no longer where you
> expect them to be when you hit the asm. Unlikely perhaps but no more so
> than the other issues you've raised?
> 	
> Or did you mean out-of-line as in "written in a .S file" as well as out
> of line?

Yes.  Some toolchains have a concept of out-of-line assembler functions
in a .c file, but gcc doesn't -- the asm is always inline in its
immediate context, even if the containing function won't be inlined.

However, the compiler would have to be applying pretty creative
optimizations to break cases cases where an inlinable function contains,
say, nothing except for declarations, the asm() and a return statement.

I feel that the kernel implicitly relies on such things working in too
many places for breakage of that assumption to go unnoticed.

> 
> > Notwithstanding the above, even if we do make theoretically unsound
> > (but often true) assumptions about inline asms, ARM will be no worse
> > than other arches in this respect.
> 
> This is true.
> 
> > Other than serving as a reminder that inline asm is a deep can of
> > worms, this doesn't really give us a neat solution...
> 
> How are system calls implemented on the userspace side? I confess I
> don't know what the ARM syscall ABI looks like -- is it all registers or
> is some of it on the stack? It sounds like the solution ought to be
> pretty similar though.

I _believe_ it's now out of line in most cases.

I'm not sure I totally understand it all, though:

http://www.eglibc.org/cgi-bin/viewvc.cgi/trunk/ports/sysdeps/unix/sysv/linux/arm/eabi/

There is an internal inline syscall wrapper INTERNAL_SYSCALL_RAW(), but
I can't see where it is used.  For Thumb code it actually just munges
registers around and calls an out-of-line function.

If I grep the disassembly of a recent EABI libc, there appear to be only
207 svc call sites, and most of them look like they are out-of-linux
wrappers, generated from the DO_CALL macro in
ports/sysdeps/unix/sysv/linux/arm/eabi/sysdep.h

That's based on a hasty reading of the code though... I'm not very
familiar with the way libc works.  (Disassembling stripped arm binaries
can also be a bit unrelieable.)

It's also worth nothing that the inline asm sycall macros which used
to exist in userspace <asm/unistd.h> are gone (at least for EABI).

Cheers
---Dave


From arnd at arndb.de  Thu Mar  1 04:40:36 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 09:40:36 +0000
Subject: [PATCH 1/8] gpio: pxa: add OF support
In-Reply-To: <1330582228-12424-2-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
 <1330582228-12424-2-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203010940.37123.arnd@arndb.de>

On Thursday 01 March 2012, Haojian Zhuang wrote:
> +#ifdef CONFIG_OF
> +static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev,
> +                                      int *irq0, int *irq1, int *irq_mux)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       const __be32 *irq;
> +
> +       irq = of_get_property(np, "mrvl,gpio-irq0", NULL);
> +       if (irq)
> +               *irq0 = be32_to_cpup(irq);
> +       irq = of_get_property(np, "mrvl,gpio-irq1", NULL);
> +       if (irq)
> +               *irq1 = be32_to_cpup(irq);
> +       *irq_mux = platform_get_irq(pdev, 0);
> +       return 0;
> +}
> +#else
> +static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev,
> +                                      int *irq0, int *irq1, int *irq_mux)
> +{
> +       return 1;
> +}
> +#endif
> +

It seems that you are not following the regular IRQ binding. This should
probably use irq_of_parse_and_map().

For other code like the one above, I suggest you use
of_property_read_u32_array(), which will already compile to nothing
if CONFIG_OF is not set, so you don't have to provide two versions of
the fucntion.

	Arnd


From linux at arm.linux.org.uk  Thu Mar  1 04:46:53 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 09:46:53 +0000
Subject: [PATCHv3 4/4] ARM: OMAP3+: add prcm chain interrupts to the
 interrupt list
In-Reply-To: <1330529106-10423-5-git-send-email-t-kristo@ti.com>
References: <1330529106-10423-1-git-send-email-t-kristo@ti.com>
 <1330529106-10423-5-git-send-email-t-kristo@ti.com>
Message-ID: <20120301094653.GA7413@n2100.arm.linux.org.uk>

On Wed, Feb 29, 2012 at 05:25:06PM +0200, Tero Kristo wrote:
> Currently PRCM chain handler for OMAP4 requires SPARSE_IRQ to be enabled
> from kernel config, however enabling this option breaks the OMAP kernel
> completely and it can't be used.

No it does not.  Look:

	irq_alloc_descs(start, from, num, -1)

will allocate num interrupt descriptors from within from..NR_IRQS if
sparse IRQ is disabled.  So, provided there is sufficient space within
the available NR_IRQS, irq_alloc_descs() works for non-sparse IRQ.
There is no need to get rid of it at all.

If start is -1, then it will allocate from where-ever it can in the
range from..NR_IRQS.  Otherwise, it will fail if it can't get an
allocation starting at 'start'.

If sparse IRQ is enabled, then it will start allocating from whatever
the last figure output from the:

	NR_IRQS:%d nr_irqs:%d %d

line.


From arnd at arndb.de  Thu Mar  1 04:47:39 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 09:47:39 +0000
Subject: [PATCH 2/8] serial: pxa: add OF support
In-Reply-To: <1330582228-12424-3-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
 <1330582228-12424-3-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203010947.39601.arnd@arndb.de>

On Thursday 01 March 2012, Haojian Zhuang wrote:
> @@ -792,7 +826,7 @@ static int serial_pxa_probe(struct platform_device *dev)
>         if (!mmres || !irqres)
>                 return -ENODEV;
>  
> -       sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
> +       sport = kzalloc(sizeof(struct uart_pxa_port) + 8, GFP_KERNEL);
>         if (!sport)
>                 return -ENOMEM;
>  
> @@ -808,20 +842,18 @@ static int serial_pxa_probe(struct platform_device *dev)
> +       ret = serial_pxa_probe_dt(dev, sport);
> +       if (ret > 0)
> +               sport->port.line = dev->id;
> +       else if (ret < 0)
> +               goto err_clk;
> +       sport->name = (char *)((unsigned int)sport + 8);
> +       /* name can't exceed 8 bytes */
> +       sprintf(sport->name, "UART%d", sport->port.line + 1);

The pointer arithmetic looks wrong to me, both technically and morally ;-)

Since struct uart_pxa_port is a local data structure, why don't you just
turn the name field into a fixed-length array?

	Arnd


From linux at arm.linux.org.uk  Thu Mar  1 04:48:53 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 09:48:53 +0000
Subject: [PATCH 2/8] serial: pxa: add OF support
In-Reply-To: <201203010947.39601.arnd@arndb.de>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
 <1330582228-12424-3-git-send-email-haojian.zhuang@marvell.com>
 <201203010947.39601.arnd@arndb.de>
Message-ID: <20120301094853.GA7363@n2100.arm.linux.org.uk>

On Thu, Mar 01, 2012 at 09:47:39AM +0000, Arnd Bergmann wrote:
> On Thursday 01 March 2012, Haojian Zhuang wrote:
> > @@ -792,7 +826,7 @@ static int serial_pxa_probe(struct platform_device *dev)
> >         if (!mmres || !irqres)
> >                 return -ENODEV;
> >  
> > -       sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
> > +       sport = kzalloc(sizeof(struct uart_pxa_port) + 8, GFP_KERNEL);
> >         if (!sport)
> >                 return -ENOMEM;
> >  
> > @@ -808,20 +842,18 @@ static int serial_pxa_probe(struct platform_device *dev)
> > +       ret = serial_pxa_probe_dt(dev, sport);
> > +       if (ret > 0)
> > +               sport->port.line = dev->id;
> > +       else if (ret < 0)
> > +               goto err_clk;
> > +       sport->name = (char *)((unsigned int)sport + 8);
> > +       /* name can't exceed 8 bytes */
> > +       sprintf(sport->name, "UART%d", sport->port.line + 1);
> 
> The pointer arithmetic looks wrong to me, both technically and morally ;-)
> 
> Since struct uart_pxa_port is a local data structure, why don't you just
> turn the name field into a fixed-length array?

and then use snprintf() to ensure that it doesn't overflow.


From arnd at arndb.de  Thu Mar  1 04:51:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 09:51:12 +0000
Subject: [PATCH 3/8] rtc: sa1100: add OF support
In-Reply-To: <1330582228-12424-4-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
 <1330582228-12424-4-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203010951.12405.arnd@arndb.de>

On Thursday 01 March 2012, Haojian Zhuang wrote:
> +#ifdef CONFIG_OF
> +static int sa1100_rtc_probe_dt(struct platform_device *pdev,
> +                              struct sa1100_rtc *info)
> +{
> +       info->irq_alarm = platform_get_irq(pdev, 0);
> +       info->irq_1hz = platform_get_irq(pdev, 1);
> +       if (info->irq_1hz < 0 || info->irq_alarm < 0)
> +               return -ENODEV;
> +       return 0;
> +}
> +#else
> +static int sa1100_rtc_probe_dt(struct platform_device *pdev,
> +                              struct sa1100_rtc *info)
> +{
> +       return 1;
> +}
> +#endif
> +
> +static int sa1100_rtc_probe_irq(struct platform_device *pdev,
> +                               struct sa1100_rtc *info)
> +{
> +       info->irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz");
> +       info->irq_alarm = platform_get_irq_byname(pdev, "rtc alarm");
> +       if (info->irq_1hz < 0 || info->irq_alarm < 0)
> +               return -ENODEV;
> +       return 0;
> +}

This should not be necessary. I thought we had already added support
for named irq resources coming from the device tree. If not, why not
just make the other ones anonymous as well and just use platform_get_irq()?

	Arnd


From dave.martin at linaro.org  Thu Mar  1 04:51:39 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 1 Mar 2012 09:51:39 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <alpine.DEB.2.00.1202291435400.23091@kaball-desktop>
References: <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <alpine.DEB.2.00.1202291435400.23091@kaball-desktop>
Message-ID: <20120301095139.GC2034@linaro.org>

On Wed, Feb 29, 2012 at 02:52:38PM +0000, Stefano Stabellini wrote:
> On Wed, 29 Feb 2012, Dave Martin wrote:
> > On Wed, Feb 29, 2012 at 09:56:02AM +0000, Ian Campbell wrote:
> > > On Wed, 2012-02-29 at 09:34 +0000, Dave Martin wrote:
> > > > On Tue, Feb 28, 2012 at 12:28:29PM +0000, Stefano Stabellini wrote:
> > > 
> > > > > I don't have a very strong opinion on which register we should use, but
> > > > > I would like to avoid r7 if it is already actively used by gcc.
> > > > 
> > > > But there is no framepointer for Thumb-2 code (?)
> > > 
> > > Peter Maydell suggested there was:
> > > > r7 is (used by gcc as) the Thumb frame pointer; I don't know if this
> > > > makes it worth avoiding in this context.
> > > 
> > > Sounds like it might be a gcc-ism, possibly a non-default option?
> > > 
> > > Anyway, I think r12 will be fine for our purposes so the point is rather
> > > moot.
> > 
> > Just had a chat with some tools guys -- apparently, when passing register
> > arguments to gcc inline asms there really isn't a guarantee that those
> > variables will be in the expected registers on entry to the inline asm.
> > 
> > If gcc reorders other function calls or other code around the inline asm
> > (which it can do, except under certain controlled situations), then
> > intervening code can clobber any registers in general.
> > 
> > Or, to summarise another way, there is no way to control which register
> > is used to pass something to an inline asm in general (often we get away
> > with this, and there are a lot of inline asms in the kernel that assume
> > it works, but the more you inline the more likely you are to get nasty
> > surprises).  There is no workaroud, except on some architectures where
> > special asm constraints allow specific individual registers to be
> > specified for operands (i386 for example).
> > 
> > If you need a specific register, this means that you must set up that
> > register explicitly inside the asm if you want a guarantee that the
> > code will work:
> > 
> > 	asm volatile (
> > 		"movw	r12, %[hvc_num]\n\t"
> > 		...
> > 		"hvc	#0"
> > 		:: [hvc_num] "i" (NUMBER) : "r12"
> > 	);
> > 
> 
> OK, we can arrange the hypercall code to be like that.
> Also with your patch series it would be "_hvc" because of the .macro,
> right?

Yes, but I would avoid making too many assumptions about the final form
of that patch -- it looks like there's significant work to do there,
since I made some unsafe assumptions about how the tools work...

We might end up with a magic #define after all.

> > This is the kind of problem which goes away when out-of-lining the
> > hvc wrapper behind a C function interface, since the ABI then provides
> > guarantees about how values are mershaled into and out of that code.
> 
> Do you mean implementing the entire HYPERVISOR_example_op in assembly
> and calling it from C?
> Because I guess that gcc would still be free to mess with the registers
> between the C function entry point and any inline assembly code.

gcc can arrange for the relevant things to be already in r0-r3 and the
relevant stack slots before branching to a function just as for inline
asm.  The only differences are that the compiler cannot choose which
registers to use, and the branch cannot be optimised away by the compiler
(the CPU may be able to optimise the branch away at runtime of course,
but that's another story...)

What libc appears to do is wrap each syscall in a separate function.
This means that it's not necessary to shuffle all the arguments by
one position when invoking the actual syscall.  (The generic "syscall"
function does of course need to shuffle the arguments so as to
displace the syscall number from the first argument to r7 --
but that's hard to avoid without inlining.)

For example:

00090b50 <shmdt>:
   90b50:       e52d7004        push    {r7}            ; (str r7, [sp, #-4]!)
   90b54:       e59f7010        ldr     r7, [pc, #16]   ; 90b6c <shmdt+0x1c>
   90b58:       ef000000        svc     0x00000000
   90b5c:       e49d7004        pop     {r7}            ; (ldr r7, [sp], #4)
   90b60:       e3700a01        cmn     r0, #4096       ; 0x1000
...

Syscalls with more than 4 args still need to load the extra ones
from the stack, of course:

00090090 <getsockopt>:
   90090:       e92d0090        push    {r4, r7}
   90094:       e59d4008        ldr     r4, [sp, #8]
   90098:       e59f7010        ldr     r7, [pc, #16]   ; 900b0 <getsockopt+0x20>
   9009c:       ef000000        svc     0x00000000
...


I don't know whether that makes sense for a hypervisor... it partly
depends on how many different hypercalls there are.

By all means implement it both ways and measure the performance
difference, if possible.

Cheers
---Dave


From arnd at arndb.de  Thu Mar  1 04:51:46 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 09:51:46 +0000
Subject: [PATCH 1/8] gpio: pxa: add OF support
In-Reply-To: <201203010940.37123.arnd@arndb.de>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
 <1330582228-12424-2-git-send-email-haojian.zhuang@marvell.com>
 <201203010940.37123.arnd@arndb.de>
Message-ID: <201203010951.46871.arnd@arndb.de>

On Thursday 01 March 2012, Arnd Bergmann wrote:
> It seems that you are not following the regular IRQ binding. This should
> probably use irq_of_parse_and_map().

Or better platform_get_irq, see comment on rtc driver.

	Arnd


From jamie at jamieiles.com  Thu Mar  1 04:53:09 2012
From: jamie at jamieiles.com (Jamie Iles)
Date: Thu, 1 Mar 2012 09:53:09 +0000
Subject: ARM: ep93xx: convert vision_ep9307 to MULTI_IRQ_HANDLER
In-Reply-To: <201202291312.21318.hartleys@visionengravers.com>
References: <201202291312.21318.hartleys@visionengravers.com>
Message-ID: <CACb=_tQP8ex7haOAuhMXFghDgscN6QU7YT5+m5fXbdtOas66RA@mail.gmail.com>

On 29 February 2012 20:12, H Hartley Sweeten
<hartleys at visionengravers.com> wrote:
> As done for the other ep93xx machines in:
>
> commit 9a6879bd902e2ec605fff4d9fb3247b440a1f66a
> ARM: ep93xx: convert to MULTI_IRQ_HANDLER
>
> Now that there is a generic IRQ handler for multiple VIC devices use it
> for vision_ep9307 to help building multi platform kernels.
>
> Signed-off-by: Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <rmallon at gmail.com>
> Cc: Jamie Iles <jamie at jamieiles.com>

Reviewed-by: Jamie Iles <jamie at jamieiles.com>


From s.hauer at pengutronix.de  Thu Mar  1 04:58:48 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2012 10:58:48 +0100
Subject: [PATCH] regulator mc13783: bail out without platform data
In-Reply-To: <20120229231951.GB8295@opensource.wolfsonmicro.com>
References: <1330502500-30567-1-git-send-email-s.hauer@pengutronix.de>
 <20120229231951.GB8295@opensource.wolfsonmicro.com>
Message-ID: <20120301095848.GZ3852@pengutronix.de>

On Wed, Feb 29, 2012 at 11:19:51PM +0000, Mark Brown wrote:
> On Wed, Feb 29, 2012 at 09:01:40AM +0100, Sascha Hauer wrote:
> > the platform data pointer is used without checking it. Bail out
> > in the driver instead of crashing the kernel.
> 
> Applied, thanks.  Ideally the platform data would just specify the
> constraints and the driver would still be able to register the
> regulators even without constriants being provided to allow diagnostics.

Indeed. I can follow up on this when I find the time. For now I'm happy
with the kernel not crashing.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Thu Mar  1 05:01:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 10:01:00 +0000
Subject: [PATCH 4/8] i2c: pxa: add OF support
In-Reply-To: <1330582228-12424-5-git-send-email-haojian.zhuang@marvell.com>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
 <1330582228-12424-5-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203011001.00289.arnd@arndb.de>

On Thursday 01 March 2012, Haojian Zhuang wrote:
> +#ifdef CONFIG_OF
> +static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
> +                           enum pxa_i2c_types *i2c_types)
>  {
> +       struct device_node *np = pdev->dev.of_node;
> +       const struct of_device_id *of_id =
> +                       of_match_device(i2c_pxa_dt_ids, &pdev->dev);
> +       const char *status;
> +       int len;
> +
> +       if (of_get_property(np, "mrvl,i2c-polling", NULL))
> +               i2c->use_pio = 1;
> +       status = of_get_property(np, "mrvl,i2c-mode", &len);
> +       if (status && len > 0)
> +               if (!strcmp(status, "fast"))
> +                       i2c->fast_mode = 1;

This would be easier if you made it an empty "mrvl,i2c-fast-mode"
property to get rid of the strcmp.

> +       *i2c_types = ((u32)(of_id->data) - (u32)&pxa_reg_layout[0])
> +                       / sizeof(struct pxa_reg_layout);

This looks unnecessarily complicated. Just put the enum into of_id->data
instead of the pointer, with a cast to unsigned long.

> +       return 0;
> +}
> +#else
> +static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
> +                           enum pxa_i2c_types *i2c_types)
> +{
> +       return 1;
> +}
> +#endif

Again, no need for the #ifdef. Just add in the beginning

	if (!of_id)
		return 1;

And the rest will be optimized out without CONFIG_OF.

	Arnd


From t-kristo at ti.com  Thu Mar  1 05:03:55 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Thu, 1 Mar 2012 12:03:55 +0200
Subject: [PATCHv3 4/4] ARM: OMAP3+: add prcm chain interrupts to the
 interrupt list
In-Reply-To: <20120301094653.GA7413@n2100.arm.linux.org.uk>
References: <1330529106-10423-1-git-send-email-t-kristo@ti.com>
 <1330529106-10423-5-git-send-email-t-kristo@ti.com>
 <20120301094653.GA7413@n2100.arm.linux.org.uk>
Message-ID: <1330596235.2116.81.camel@sokoban>

On Thu, 2012-03-01 at 09:46 +0000, Russell King - ARM Linux wrote:
> On Wed, Feb 29, 2012 at 05:25:06PM +0200, Tero Kristo wrote:
> > Currently PRCM chain handler for OMAP4 requires SPARSE_IRQ to be enabled
> > from kernel config, however enabling this option breaks the OMAP kernel
> > completely and it can't be used.
> 
> No it does not.  Look:
> 
> 	irq_alloc_descs(start, from, num, -1)
> 
> will allocate num interrupt descriptors from within from..NR_IRQS if
> sparse IRQ is disabled.  So, provided there is sufficient space within
> the available NR_IRQS, irq_alloc_descs() works for non-sparse IRQ.
> There is no need to get rid of it at all.
> 
> If start is -1, then it will allocate from where-ever it can in the
> range from..NR_IRQS.  Otherwise, it will fail if it can't get an
> allocation starting at 'start'.
> 
> If sparse IRQ is enabled, then it will start allocating from whatever
> the last figure output from the:
> 
> 	NR_IRQS:%d nr_irqs:%d %d
> 
> line.

With the patch from Benoit
(http://marc.info/?l=linux-arm-kernel&m=133043468329275&w=2) this patch
is no longer needed. Previously the NR_IRQS definition was too small for
omap4 and the alloc_descs was failing because of that. It seems I
overshoot with this patch of mine and dropped also the irq_alloc_desc
implementation while fixing the problem.

-Tero




From nicolas.ferre at atmel.com  Thu Mar  1 05:05:21 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 01 Mar 2012 11:05:21 +0100
Subject: at91: Error while registering DMA controller in 3.3-rc
Message-ID: <4F4F49E1.4020902@atmel.com>

Arnd, Olof,

We currently have a regression on 3.3-rc kernels about the DMA
controller registration.

http://article.gmane.org/gmane.linux.kernel.mmc/13014

This is due to the DMA driver having seen an update during the 3.3 merge
window  but the AT91 device files not having the corresponding
modifications.

Maybe you remember, those modifications where part of the famous AT91
board/device series that was postponed to 3.4 due to a flood of issues...

So now, I would like to know if it is possible to resolve this problem
by queuing the DMA related patches that we have already in
at91/device-board branch to mainline before 3.3-final?

The patches that I am talking about are:

bdad0b9 ARM: at91/dma: remove platform data from DMA controller
and
2756bf5 ARM: at91/dma: DMA controller registering with DT support

I do think it is pretty silly to try to resolve this issue by not taking
those two little patches and modifying source code to workaround this
issue. If we do this, we will get conflicts and need to rework the
already queued 3.4 material.

Do you want me to prepare a new at91-fixes branch with those two patches
or you can take them yourself?

Thanks for your help, best regards,
-- 
Nicolas Ferre


From s.hauer at pengutronix.de  Thu Mar  1 05:08:47 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2012 11:08:47 +0100
Subject: [PATCH] ARM: 3ds_debugboard: Let ethernet be functional again
In-Reply-To: <20120216075825.GA11631@opensource.wolfsonmicro.com>
References: <1328646473-11828-1-git-send-email-festevam@gmail.com>
 <20120213082741.GN3852@pengutronix.de>
 <20120213144820.GA3494@opensource.wolfsonmicro.com>
 <20120214105823.GS3852@pengutronix.de>
 <20120214172902.GB3916@opensource.wolfsonmicro.com>
 <20120216073236.GE3852@pengutronix.de>
 <20120216075825.GA11631@opensource.wolfsonmicro.com>
Message-ID: <20120301100847.GF26642@pengutronix.de>

On Wed, Feb 15, 2012 at 11:58:26PM -0800, Mark Brown wrote:
> On Thu, Feb 16, 2012 at 08:32:36AM +0100, Sascha Hauer wrote:
> > On Tue, Feb 14, 2012 at 09:29:04AM -0800, Mark Brown wrote:
> 
> > > The main thing here is to avoid these driver specific bodges that people
> > > keep churning out again and again, it's quite depressing really.
> 
> > I think this churning will continue until we either make the dummy
> > regulator non optional and drop this warning that gets printed each
> > time it is used, or we at least provide a way to easily add a fixed
> 
> That's obviously not a good idea, if we do that we may as well just drop
> all error checking from the API.
> 
> > dummy regulator without adding >20 lines of code to each board just
> > for saying that we don't have a regulator for this particular device.
> 
> It's not per device, of course - there's an overhead from putting a
> fixed regulator in but then per supply it's just a line.
> 
> > +#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
> > +struct platform_device *regulator_register_fixed(const char *name, int id,
> > +		int microvolts, struct regulator_consumer_supply *supplies,
> > +		int num_supplies);
> > +#else
> > +static struct platform_device *regulator_register_fixed(const char *name, int id,
> > +		int microvolts, struct regulator_consumer_supply *supplies,
> > +		int num_supplies)
> > +{
> > +	return NULL;
> > +}
> > +#endif
> 
> This is obviously not good for users, they'd still have to do error
> checking to determine if the device was created or not and then manually
> register the device with the driver core and ideally also care if that
> worked or not.  I'm not sure something like this will really save enough
> unless the device actually gets registered by the function, otherwise
> it's going to be converting data to code.
> 
> I'd also drop the microvolts and name parameters,

Ok, I tried to do this. I Changed the function to:

static struct platform_device *regulator_register_fixed(int id,
		struct regulator_consumer_supply *supplies, int num_supplies)

Now I have to register a fixed regulator with some invented value
for microvolts. What value should I choose? I tried 0 but the core
won't accept this as explained earlier, in short regulator_register()
returns with an error.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linux at arm.linux.org.uk  Thu Mar  1 05:10:29 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 10:10:29 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall
 number to the hypervisor
In-Reply-To: <20120229125826.GC2077@linaro.org>
References: <1330019314-20865-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
Message-ID: <20120301101029.GB7363@n2100.arm.linux.org.uk>

On Wed, Feb 29, 2012 at 12:58:26PM +0000, Dave Martin wrote:
> On Wed, Feb 29, 2012 at 09:56:02AM +0000, Ian Campbell wrote:
> > On Wed, 2012-02-29 at 09:34 +0000, Dave Martin wrote:
> > > On Tue, Feb 28, 2012 at 12:28:29PM +0000, Stefano Stabellini wrote:
> > 
> > > > I don't have a very strong opinion on which register we should use, but
> > > > I would like to avoid r7 if it is already actively used by gcc.
> > > 
> > > But there is no framepointer for Thumb-2 code (?)
> > 
> > Peter Maydell suggested there was:
> > > r7 is (used by gcc as) the Thumb frame pointer; I don't know if this
> > > makes it worth avoiding in this context.
> > 
> > Sounds like it might be a gcc-ism, possibly a non-default option?
> > 
> > Anyway, I think r12 will be fine for our purposes so the point is rather
> > moot.
> 
> Just had a chat with some tools guys -- apparently, when passing register
> arguments to gcc inline asms there really isn't a guarantee that those
> variables will be in the expected registers on entry to the inline asm.

The best you can do is:

	register unsigned int foo asm("r7") = value;

	asm("blah %0" : : "r" (foo));

and ensure that your assembly checks that %0 _is_ r7 and produces a build
error if not.  See the __asmeq() macro in asm/system.h to find out how to
do that.

This feature has been missing from ARM GCC for quite a long time - it's
used extensively on x86 GCC, where they have one register class per
register, so they can do stuff like:

	asm("blah %0" : : "a" (value));

and be guaranteed that %0 will be eax.

> If you need a specific register, this means that you must set up that
> register explicitly inside the asm if you want a guarantee that the
> code will work:
> 
> 	asm volatile (
> 		"movw	r12, %[hvc_num]\n\t"
> 		...
> 		"hvc	#0"
> 		:: [hvc_num] "i" (NUMBER) : "r12"
> 	);
> 
> Of course, if you need to set up more than about 5 or 6 registers in
> this way, the doubled register footprint means that the compiler will
> have to start spilling stuff to the stack.

No it won't - it will barf instead - think about it.  If you're clobbering
r0 - r5, but need to pass in six values in registers, gcc can't use r0-r5
for that, so it must use the remaining registers.  It gets rather unhappy
with that, and starts erroring out (iirc 'too many reloads' or some similar
error.)  I've been there.

If you want to do it that way, your only option is to store them to memory
and pass the address of the block into the assembly, and reload them there.
Which is extremely sucky and inefficient.

Practically, the register variable plus asm() does seem to work, and seems
to work for virtually all gcc versions out there (there have been the odd
buggy version, but those bugs appear to get fixed.)



From catalin.marinas at arm.com  Thu Mar  1 05:13:22 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 1 Mar 2012 10:13:22 +0000
Subject: [PATCH 2/7] Add various hugetlb page table fix
In-Reply-To: <1329126268-11032-3-git-send-email-bill4carson@gmail.com>
References: <1329126268-11032-1-git-send-email-bill4carson@gmail.com>
 <1329126268-11032-3-git-send-email-bill4carson@gmail.com>
Message-ID: <20120301101321.GC21445@arm.com>

On Mon, Feb 13, 2012 at 09:44:23AM +0000, Bill Carson wrote:
> --- a/arch/arm/include/asm/pgtable.h
> +++ b/arch/arm/include/asm/pgtable.h
> @@ -236,6 +244,7 @@ PTE_BIT_FUNC(mkdirty,   |= L_PTE_DIRTY);
>  PTE_BIT_FUNC(mkold,     &= ~L_PTE_YOUNG);
>  PTE_BIT_FUNC(mkyoung,   |= L_PTE_YOUNG);
>  
> +static inline pte_t pte_mkhuge(pte_t pte) { return pte; }

Do we need to set the PMD_TYPE_SECT here or you just do it via
set_huge_pte()?

-- 
Catalin


From linux at arm.linux.org.uk  Thu Mar  1 05:12:58 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 10:12:58 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall
 number to the hypervisor
In-Reply-To: <1330526664.4270.128.camel@zakaz.uk.xensource.com>
References: <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <1330526664.4270.128.camel@zakaz.uk.xensource.com>
Message-ID: <20120301101258.GC7363@n2100.arm.linux.org.uk>

On Wed, Feb 29, 2012 at 02:44:24PM +0000, Ian Campbell wrote:
> > If you need a specific register, this means that you must set up that
> > register explicitly inside the asm if you want a guarantee that the
> > code will work:
> > 
> > 	asm volatile (
> > 		"movw	r12, %[hvc_num]\n\t"
> 
> Is gcc (or gas?) smart enough to optimise this away if it turns out that
> %[hvc_num] == r12?

No, and it won't do, because %[hvc_num] is specified in these operands:

> > 		...
> > 		"hvc	#0"
> > 		:: [hvc_num] "i" (NUMBER) : "r12"

to be an integer, not a register.

> How are system calls implemented on the userspace side? I confess I
> don't know what the ARM syscall ABI looks like -- is it all registers or
> is some of it on the stack? It sounds like the solution ought to be
> pretty similar though.

All registers.  We have a few which take a pointer to an in memory array,
but those are for some old multiplexed syscalls.


From s.hauer at pengutronix.de  Thu Mar  1 05:19:05 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2012 11:19:05 +0100
Subject: [PATCH v2 2/2] dmaengine: Add support for multiple descriptors
 for imx-dma.
In-Reply-To: <1330445298-3522-3-git-send-email-javier.martin@vista-silicon.com>
References: <1330445298-3522-1-git-send-email-javier.martin@vista-silicon.com>
 <1330445298-3522-3-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120301101904.GA3852@pengutronix.de>

On Tue, Feb 28, 2012 at 05:08:18PM +0100, Javier Martin wrote:
> dmaengine specifies the possibility that several descriptors
> can be queued for transfer. It also indicates that tasklets
> must be used for DMA callbacks.
> 
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>

Have you tested this patch with audio?


> +static int imxdma_xfer_desc(struct imxdma_desc *d)
> +{
> +	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
> +	int ret;
> +
> +	/* Configure and enable */
> +	switch (d->type) {
> +	case IMXDMA_DESC_MEMCPY:
> +		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
> +					  d->config_port, d->config_mem, 0, 0);
> +		if (ret < 0)
> +			return ret;
> +		ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
> +					   d->len, d->dest, d->dmamode);
> +		if (ret < 0)
> +			return ret;
> +		break;
> +	case IMXDMA_DESC_CYCLIC:
> +		ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
> +							imxdma_progression);
> +		if (ret < 0)
> +			return ret;

You fall through here. Is this intended? If yes, a comment would be good
here.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From subhashj at codeaurora.org  Thu Mar  1 05:21:02 2012
From: subhashj at codeaurora.org (Subhash Jadavani)
Date: Thu, 01 Mar 2012 15:51:02 +0530
Subject: [PATCH V2 1/1] mmc: start removing enable / disable API
In-Reply-To: <4F4F31A7.3060307@intel.com>
References: <1330499841-6879-1-git-send-email-adrian.hunter@intel.com>
 <1330499841-6879-2-git-send-email-adrian.hunter@intel.com>
 <4F4F2E93.1090109@codeaurora.org> <4F4F31A7.3060307@intel.com>
Message-ID: <4F4F4D8E.5030305@codeaurora.org>

On 3/1/2012 1:51 PM, Adrian Hunter wrote:
> On 01/03/12 10:08, Subhash Jadavani wrote:
>> On 2/29/2012 12:47 PM, Adrian Hunter wrote:
>>> Most parts of the enable / disable API are no longer used and
>>> can be removed.
>>>
>>> Cc: Rajendra Nayak<rnayak at ti.com>
>>> Cc: Venkatraman S<svenkatr at ti.com>
>>> Cc: Kukjin Kim<kgene.kim at samsung.com>
>>> Cc: Thomas Abraham<thomas.abraham at linaro.org>
>>> Cc: Kyungmin Park<kyungmin.park at samsung.com>
>>> Cc: Sekhar Nori<nsekhar at ti.com>
>>> Cc: Kevin Hilman<khilman at ti.com>
>>> Signed-off-by: Adrian Hunter<adrian.hunter at intel.com>
>>> ---
>>>    arch/arm/mach-exynos/mach-nuri.c           |    5 +-
>>>    arch/arm/mach-exynos/mach-universal_c210.c |    9 +-
>>>    drivers/mmc/core/core.c                    |  187
>>> +++-------------------------
>>>    drivers/mmc/core/host.c                    |    1 -
>>>    drivers/mmc/core/host.h                    |    1 -
>>>    drivers/mmc/host/davinci_mmc.c             |    4 -
>>>    drivers/mmc/host/omap_hsmmc.c              |   15 +--
>>>    include/linux/mmc/core.h                   |    1 -
>>>    include/linux/mmc/host.h                   |   46 +------
>>>    9 files changed, 27 insertions(+), 242 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/mach-nuri.c
>>> b/arch/arm/mach-exynos/mach-nuri.c
>>> index 644af11..de68248 100644
>>> --- a/arch/arm/mach-exynos/mach-nuri.c
>>> +++ b/arch/arm/mach-exynos/mach-nuri.c
>>> @@ -109,7 +109,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data
>>> __initdata = {
>>>        .max_width        = 8,
>>>        .host_caps        = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
>>>                    MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
>>> -                MMC_CAP_DISABLE | MMC_CAP_ERASE),
>>> +                MMC_CAP_ERASE),
>>>        .cd_type        = S3C_SDHCI_CD_PERMANENT,
>>>    };
>>>
>>> @@ -147,8 +147,7 @@ static struct platform_device emmc_fixed_voltage = {
>>>    static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
>>>        .max_width        = 4,
>>>        .host_caps        = MMC_CAP_4_BIT_DATA |
>>> -                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
>>> -                MMC_CAP_DISABLE,
>>> +                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>>>        .ext_cd_gpio        = EXYNOS4_GPX3(3),    /* XEINT_27 */
>>>        .ext_cd_gpio_invert    = 1,
>>>        .cd_type        = S3C_SDHCI_CD_GPIO,
>>> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c
>>> b/arch/arm/mach-exynos/mach-universal_c210.c
>>> index 9b3fbae..57cfe61 100644
>>> --- a/arch/arm/mach-exynos/mach-universal_c210.c
>>> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
>>> @@ -734,8 +734,7 @@ static struct platform_device universal_gpio_keys = {
>>>    static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
>>>        .max_width        = 8,
>>>        .host_caps        = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
>>> -                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
>>> -                MMC_CAP_DISABLE),
>>> +                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
>>>        .cd_type        = S3C_SDHCI_CD_PERMANENT,
>>>    };
>>>
>>> @@ -772,8 +771,7 @@ static struct platform_device mmc0_fixed_voltage = {
>>>    static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
>>>        .max_width        = 4,
>>>        .host_caps        = MMC_CAP_4_BIT_DATA |
>>> -                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
>>> -                MMC_CAP_DISABLE,
>>> +                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>>>        .ext_cd_gpio        = EXYNOS4_GPX3(4),      /* XEINT_28 */
>>>        .ext_cd_gpio_invert    = 1,
>>>        .cd_type        = S3C_SDHCI_CD_GPIO,
>>> @@ -783,8 +781,7 @@ static struct s3c_sdhci_platdata universal_hsmmc2_data
>>> __initdata = {
>>>    static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
>>>        .max_width        = 4,
>>>        .host_caps        = MMC_CAP_4_BIT_DATA |
>>> -                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
>>> -                MMC_CAP_DISABLE,
>>> +                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>>>        .cd_type        = S3C_SDHCI_CD_EXTERNAL,
>>>    };
>>>
>>> diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
>>> index 0b317f0..44dd013 100644
>>> --- a/drivers/mmc/core/core.c
>>> +++ b/drivers/mmc/core/core.c
>>> @@ -605,105 +605,6 @@ unsigned int mmc_align_data_size(struct mmc_card
>>> *card, unsigned int sz)
>>>    EXPORT_SYMBOL(mmc_align_data_size);
>>>
>>>    /**
>>> - *    mmc_host_enable - enable a host.
>>> - *    @host: mmc host to enable
>>> - *
>>> - *    Hosts that support power saving can use the 'enable' and 'disable'
>>> - *    methods to exit and enter power saving states. For more information
>>> - *    see comments for struct mmc_host_ops.
>>> - */
>>> -int mmc_host_enable(struct mmc_host *host)
>>> -{
>>> -    if (!(host->caps&   MMC_CAP_DISABLE))
>>> -        return 0;
>>> -
>>> -    if (host->en_dis_recurs)
>>> -        return 0;
>>> -
>>> -    if (host->nesting_cnt++)
>>> -        return 0;
>>> -
>>> -    cancel_delayed_work_sync(&host->disable);
>>> -
>>> -    if (host->enabled)
>>> -        return 0;
>>> -
>>> -    if (host->ops->enable) {
>>> -        int err;
>>> -
>>> -        host->en_dis_recurs = 1;
>>> -        mmc_host_clk_hold(host);
>>> -        err = host->ops->enable(host);
>>> -        mmc_host_clk_release(host);
>>> -        host->en_dis_recurs = 0;
>>> -
>>> -        if (err) {
>>> -            pr_debug("%s: enable error %d\n",
>>> -                 mmc_hostname(host), err);
>>> -            return err;
>>> -        }
>>> -    }
>>> -    host->enabled = 1;
>>> -    return 0;
>>> -}
>>> -EXPORT_SYMBOL(mmc_host_enable);
>>> -
>>> -static int mmc_host_do_disable(struct mmc_host *host, int lazy)
>>> -{
>>> -    if (host->ops->disable) {
>>> -        int err;
>>> -
>>> -        host->en_dis_recurs = 1;
>>> -        mmc_host_clk_hold(host);
>>> -        err = host->ops->disable(host, lazy);
>>> -        mmc_host_clk_release(host);
>>> -        host->en_dis_recurs = 0;
>>> -
>>> -        if (err<   0) {
>>> -            pr_debug("%s: disable error %d\n",
>>> -                 mmc_hostname(host), err);
>>> -            return err;
>>> -        }
>>> -        if (err>   0) {
>>> -            unsigned long delay = msecs_to_jiffies(err);
>>> -
>>> -            mmc_schedule_delayed_work(&host->disable, delay);
>>> -        }
>>> -    }
>>> -    host->enabled = 0;
>>> -    return 0;
>>> -}
>>> -
>>> -/**
>>> - *    mmc_host_disable - disable a host.
>>> - *    @host: mmc host to disable
>>> - *
>>> - *    Hosts that support power saving can use the 'enable' and 'disable'
>>> - *    methods to exit and enter power saving states. For more information
>>> - *    see comments for struct mmc_host_ops.
>>> - */
>>> -int mmc_host_disable(struct mmc_host *host)
>>> -{
>>> -    int err;
>>> -
>>> -    if (!(host->caps&   MMC_CAP_DISABLE))
>>> -        return 0;
>>> -
>>> -    if (host->en_dis_recurs)
>>> -        return 0;
>>> -
>>> -    if (--host->nesting_cnt)
>>> -        return 0;
>>> -
>>> -    if (!host->enabled)
>>> -        return 0;
>>> -
>>> -    err = mmc_host_do_disable(host, 0);
>>> -    return err;
>>> -}
>>> -EXPORT_SYMBOL(mmc_host_disable);
>>> -
>>> -/**
>>>     *    __mmc_claim_host - exclusively claim a host
>>>     *    @host: mmc host to claim
>>>     *    @abort: whether or not the operation should be aborted
>>> @@ -741,8 +642,8 @@ int __mmc_claim_host(struct mmc_host *host, atomic_t
>>> *abort)
>>>            wake_up(&host->wq);
>>>        spin_unlock_irqrestore(&host->lock, flags);
>>>        remove_wait_queue(&host->wq,&wait);
>>> -    if (!stop)
>>> -        mmc_host_enable(host);
>>> +    if (host->ops->enable&&   !stop&&   host->claim_cnt == 1)
>> Shouldn't we still make sure that clocks are hold (by calling
>> mmc_host_clk_hold() ) before calling enable?
> The only enable / disable user is omap_hsmmc which uses it to get
> and put runtime pm, so there is no reason to hold / release clock
> gating - since that path will also get / put runtime pm which is synchronized.
Ok.

> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From dave.martin at linaro.org  Thu Mar  1 05:27:02 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 1 Mar 2012 10:27:02 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <20120301101029.GB7363@n2100.arm.linux.org.uk>
References: <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <20120301101029.GB7363@n2100.arm.linux.org.uk>
Message-ID: <20120301102702.GD2034@linaro.org>

On Thu, Mar 01, 2012 at 10:10:29AM +0000, Russell King - ARM Linux wrote:
> On Wed, Feb 29, 2012 at 12:58:26PM +0000, Dave Martin wrote:
> > On Wed, Feb 29, 2012 at 09:56:02AM +0000, Ian Campbell wrote:
> > > On Wed, 2012-02-29 at 09:34 +0000, Dave Martin wrote:
> > > > On Tue, Feb 28, 2012 at 12:28:29PM +0000, Stefano Stabellini wrote:
> > > 
> > > > > I don't have a very strong opinion on which register we should use, but
> > > > > I would like to avoid r7 if it is already actively used by gcc.
> > > > 
> > > > But there is no framepointer for Thumb-2 code (?)
> > > 
> > > Peter Maydell suggested there was:
> > > > r7 is (used by gcc as) the Thumb frame pointer; I don't know if this
> > > > makes it worth avoiding in this context.
> > > 
> > > Sounds like it might be a gcc-ism, possibly a non-default option?
> > > 
> > > Anyway, I think r12 will be fine for our purposes so the point is rather
> > > moot.
> > 
> > Just had a chat with some tools guys -- apparently, when passing register
> > arguments to gcc inline asms there really isn't a guarantee that those
> > variables will be in the expected registers on entry to the inline asm.
> 
> The best you can do is:
> 
> 	register unsigned int foo asm("r7") = value;
> 
> 	asm("blah %0" : : "r" (foo));
> 
> and ensure that your assembly checks that %0 _is_ r7 and produces a build
> error if not.  See the __asmeq() macro in asm/system.h to find out how to
> do that.
> 
> This feature has been missing from ARM GCC for quite a long time - it's
> used extensively on x86 GCC, where they have one register class per
> register, so they can do stuff like:
> 
> 	asm("blah %0" : : "a" (value));
> 
> and be guaranteed that %0 will be eax.
> 
> > If you need a specific register, this means that you must set up that
> > register explicitly inside the asm if you want a guarantee that the
> > code will work:
> > 
> > 	asm volatile (
> > 		"movw	r12, %[hvc_num]\n\t"
> > 		...
> > 		"hvc	#0"
> > 		:: [hvc_num] "i" (NUMBER) : "r12"
> > 	);
> > 
> > Of course, if you need to set up more than about 5 or 6 registers in
> > this way, the doubled register footprint means that the compiler will
> > have to start spilling stuff to the stack.
> 
> No it won't - it will barf instead - think about it.  If you're clobbering
> r0 - r5, but need to pass in six values in registers, gcc can't use r0-r5
> for that, so it must use the remaining registers.  It gets rather unhappy
> with that, and starts erroring out (iirc 'too many reloads' or some similar
> error.)  I've been there.

You're right about that -- I didn't pursue my line of thought to the end,
there.  I have see the behaviour you describe.

> If you want to do it that way, your only option is to store them to memory
> and pass the address of the block into the assembly, and reload them there.
> Which is extremely sucky and inefficient.
> 
> Practically, the register variable plus asm() does seem to work, and seems
> to work for virtually all gcc versions out there (there have been the odd
> buggy version, but those bugs appear to get fixed.)

That is inconvenient for us, but it's a not a bug.  The ability for asm
contraints to be able to gcc to put things in specific registers (as with
the gcc "abcd" constraints for i386) would be nice, but as you point out,
this capability is simply not supported by gcc right now for ARM -- the
compiler guys seem to be pretty opposed to it, so I can't say I anticiapte
this being supported in the near future.

So, where there's a compelling reason to inline these things, we can use
the existing techniques if we're alert to the risks.  But in cases where
there isn't a compelling reason, aren't we just inviting fragility
unnecessarily?

Cheers
---Dave


From javier.martin at vista-silicon.com  Thu Mar  1 05:28:18 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Thu, 1 Mar 2012 11:28:18 +0100
Subject: [PATCH v2 2/2] dmaengine: Add support for multiple descriptors
 for imx-dma.
In-Reply-To: <20120301101904.GA3852@pengutronix.de>
References: <1330445298-3522-1-git-send-email-javier.martin@vista-silicon.com>
 <1330445298-3522-3-git-send-email-javier.martin@vista-silicon.com>
 <20120301101904.GA3852@pengutronix.de>
Message-ID: <CACKLOr2bFgSUW+oXgFReHt6ZS+t7atMJ6nzDgF4-e9cRyOYX4w@mail.gmail.com>

Hi Sascha,

On 1 March 2012 11:19, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Tue, Feb 28, 2012 at 05:08:18PM +0100, Javier Martin wrote:
>> dmaengine specifies the possibility that several descriptors
>> can be queued for transfer. It also indicates that tasklets
>> must be used for DMA callbacks.
>>
>> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
>
> Have you tested this patch with audio?

Yes,
I have a test battery which tests audio, mmc, runs dmatest module and
a custom mem2mem video device I'm developing.

>
>> +static int imxdma_xfer_desc(struct imxdma_desc *d)
>> +{
>> + ? ? struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
>> + ? ? int ret;
>> +
>> + ? ? /* Configure and enable */
>> + ? ? switch (d->type) {
>> + ? ? case IMXDMA_DESC_MEMCPY:
>> + ? ? ? ? ? ? ret = imx_dma_config_channel(imxdmac->imxdma_channel,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d->config_port, d->config_mem, 0, 0);
>> + ? ? ? ? ? ? if (ret < 0)
>> + ? ? ? ? ? ? ? ? ? ? return ret;
>> + ? ? ? ? ? ? ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?d->len, d->dest, d->dmamode);
>> + ? ? ? ? ? ? if (ret < 0)
>> + ? ? ? ? ? ? ? ? ? ? return ret;
>> + ? ? ? ? ? ? break;
>> + ? ? case IMXDMA_DESC_CYCLIC:
>> + ? ? ? ? ? ? ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? imxdma_progression);
>> + ? ? ? ? ? ? if (ret < 0)
>> + ? ? ? ? ? ? ? ? ? ? return ret;
>
> You fall through here. Is this intended? If yes, a comment would be good
> here.

Yes it is. cyclic is the same as slave_sg with the add-on of the
progression handler and a specific configuration of the sglist which
is done in 'imxdma_prep_dma_cyclic'.
Do you want me to send a new version with a comment on the matter?

-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From linux at arm.linux.org.uk  Thu Mar  1 05:35:20 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 10:35:20 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall
 number to the hypervisor
In-Reply-To: <20120301102702.GD2034@linaro.org>
References: <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <20120301101029.GB7363@n2100.arm.linux.org.uk>
 <20120301102702.GD2034@linaro.org>
Message-ID: <20120301103520.GD7363@n2100.arm.linux.org.uk>

On Thu, Mar 01, 2012 at 10:27:02AM +0000, Dave Martin wrote:
> So, where there's a compelling reason to inline these things, we can use
> the existing techniques if we're alert to the risks.  But in cases where
> there isn't a compelling reason, aren't we just inviting fragility
> unnecessarily?

The practical experience from the kernel suggests that there isn't a
problem - that's not to say that future versions of gcc won't become
a problem, and that the compiler guys may refuse to fix it.

I think it's a feature that we should be pressing gcc guys for - it's
fairly fundamental to any programming which requires interfaces that
require certain args in certain registers, or receive results in
certain registers.

The options over this are basically:
1. refusing to upgrade to any version of gcc which does not allow
   registers-in-asm
2. doing the store-to-memory reload-in-asm thing
3. hand-coding veneers for every call to marshall the registers

Each of those has its down sides, but I suspect with (1), it may be
possible to have enough people applying pressure to the compiler guys
that they finally see sense on this matter.


From m.szyprowski at samsung.com  Thu Mar  1 05:40:27 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Thu, 01 Mar 2012 11:40:27 +0100
Subject: [PATCH v9 0/2] iommu/exynos: Add IOMMU/System MMU driver for
 Samsung Exynos
In-Reply-To: <001801ccf5e3$69d79860$3d86c920$%cho@samsung.com>
References: <001801ccf5e3$69d79860$3d86c920$%cho@samsung.com>
Message-ID: <00fe01ccf797$b7ced690$276c83b0$%szyprowski@samsung.com>

Hi,

On Tuesday, February 28, 2012 7:37 AM KyongHo Cho wrote:

> Changes since v8:
> - exynos_iommu_map/unmap() just works for the page sizes
>    that System MMU supports. (Joerg's comment)
> - 1 platform device for 1 H/W though a multimedia accelerator
>    with several System MMUs attached.
>    This make controlling System MMU simpler.
> - Information between System MMU and the accelerators:
>    Shifted to accelerator's device structure from System MMU's

Could you tell which kernel tree did you use as a base for this patch? 

It doesn't apply onto any of the known kernel trees (I've tried v3.2, v3.3-rc5 and
kgene/for-next). It looks that you have used some internal tree because cannot 
find arch/arm/mach-exynos/clock-exynos5.c or arch/arm/mach-exynos/clock-exynos4212.c
files in any of the public git repositories. 

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From hvaibhav at ti.com  Thu Mar  1 05:42:04 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Thu, 1 Mar 2012 10:42:04 +0000
Subject: [PATCH-V2 2/2] arm:omap:am33xx: Add power domain data
In-Reply-To: <alpine.DEB.2.00.1202291810230.12752@utopia.booyaka.com>
References: <1324803628-16790-1-git-send-email-hvaibhav@ti.com>
 <1324803628-16790-3-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1202291810230.12752@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A8317E5134@DBDE01.ent.ti.com>

On Thu, Mar 01, 2012 at 07:07:01, Paul Walmsley wrote:
> Hi
> 
> a question -
> 
> On Sun, 25 Dec 2011, Vaibhav Hiremath wrote:
> 
> > +static struct powerdomain mpu_33xx_pwrdm = {
> > +	.name			= "mpu_pwrdm",
> > +	.voltdm			= { .name = "mpu" },
> > +	.prcm_partition		= AM33XX_PRM_PARTITION,
> > +	.prcm_offs		= AM33XX_PRM_MPU_MOD,
> > +	.pwrsts			= PWRSTS_OFF_RET_ON,
> > +	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
> > +	.pwrstctrl_offs		= AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
> > +	.pwrstst_offs		= AM33XX_PM_MPU_PWRSTST_OFFSET,
> > +	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
> > +	.banks			= 3,
> > +	.pwrsts_mem_ret		= {
> > +		[0]	= PWRSTS_OFF_RET,	/* mpu_l1 */
> > +		[1]	= PWRSTS_OFF_RET,	/* mpu_l2 */
> > +		[2]	= PWRSTS_OFF_RET,	/* mpu_ram */
> > +	},
> > +	.pwrsts_mem_on		= {
> > +		[0]	= PWRSTS_ON,		/* mpu_l1 */
> > +		[1]	= PWRSTS_ON,		/* mpu_l2 */
> > +		[2]	= PWRSTS_ON,		/* mpu_ram */
> > +	},
> > +};
> 
> Comparing this with Table 8-191 "PM_MPU_PWRSTCTRL Register Field 
> Descriptions" of the AM335x TRM Rev C [SPRUH73C], it seems that something 
> is really wrong here.
> 
> On the OMAP4430's *_PWRSTCTRL registers,
> 
> - the memory bank RETSTATE fields always start at bit 8;
> 
> - the RETSTATE fields are contiguous;
> 
> - the bank ONSTATE fields always start at bit 16; and 
> 
> - the ONSTATE fields are contiguous;
> 
> - the order of the RETSTATE and ONSTATE fields always matches.
> 
> The OMAP4430 TRM Rev O [SWPU231O] Table 3-449 "PM_CORE_PWRSTCTRL" table 
> is a good illustration of this.
> 
> But, looking at SPRUH73C, none of these criteria seem to apply 
> consistently on AM335x :-(
> 
> Table 8-191 "PM_MPU_PWRSTCTRL Register Field Descriptions" starts its 
> RETSTATE bitfields at bit 22, not bit 8.  The ONSTATE bitfields are at bit 
> 16 (at least this part is normal).  And both sets of bitfields are 
> internally contiguous.  But then the order of the bitfields does not match 
> between the RETSTATE bitfields and ONSTATE bitfields - the RETSTATE order 
> is (L1, L2, RAM), but the ONSTATE order is (RAM, L1, L2)!
> 
> Then looking at Table 8-184 "PM_PER_PWRSTCTRL Register Field Descriptions" 
> for the same chip, the layout is completely different.  The PRUSS memory 
> ONSTATE starts at bit 5, and its RETSTATE field is at bit 7.  But then 
> PER_MEM's ONSTATE field starts at bit 25, and is followed immediately by 
> *RAM*_MEM's RETSTATE field at bit 27!  And then PER_MEM's RETSTATE field 
> shows up at bit 29, followed by RAM_MEM's ONSTATE field at bit 30.
> 
> Is the TRM accurate in these examples?  Or is this a documentation bug?
> 

Unfortunately, the spec is correct in this context.

> Anyway, if this is really accurate, this per-powerdomain bitfield 
> reordering is definitely not expected by the existing powerdomain code.  
> Looks to me that someone will have to add bitshift fields into the struct 
> powerdomain for every single bank RETSTATE and ONSTATE field.
> 

That would be me... :)
I have started looking at it and will soon submit the patches for this.

Side note,

I am not sure whether we access these bits explicitly. If I understand correctly, API's which access these bits are not being called from anywhere, 
For example,

	omap4_pwrdm_read_mem_retst
	omap4_pwrdm_set_mem_retst
	omap4_pwrdm_set_mem_onst

Currently the major issue would be, for PM_PER_PWRSTCTRL, where 
LogicRETState bit has been moved to offset 3. This is being used in 
omap4_pwrdm_set_logic_retst() api.

And in order to support weird/non-standard bit-offsets, we have to clean omap2_pwrdm_get_mem_bank_onstate/retst/_mask() api and have bitshift field in struct powerdomain, as you have rightly pointed out.

Is my all understanding correct?

If yes, do you think this patch should get blocked for above cleanup? I feel
Cleanup can still follow, since this won't impact the AM33xx boot.

What's your opinion on this??

> Does this match your understanding?
> 

Yes, certainly.


Thanks,
Vaibhav

> 
> - Paul
> 



From sshtylyov at mvista.com  Thu Mar  1 05:48:05 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Thu, 01 Mar 2012 14:48:05 +0400
Subject: [PATCH] iop-adma: Corrected array overflow in RAID6 Xscale(R)
 test.
In-Reply-To: <1330547295-25615-1-git-send-email-don.morris@hp.com>
References: <1330547295-25615-1-git-send-email-don.morris@hp.com>
Message-ID: <4F4F53E5.8020404@ru.mvista.com>

Hello.

On 01-03-2012 0:28, Don Morris wrote:

> Reported as: https://bugzilla.kernel.org/show_bug.cgi?id=42677

> Test code pq_src array was grown by two elements to correspond with actual
> usage (IOP_ADMA_NUM_SRC_TEST+2), stack consumption was kept constant by
> modifying the pq_dest two element array which is only used when pq_src
> is referenced up to IOP_ADMA_NUM_SRC_TEST elements into the address
> of the new last two elements of the pq_src array. This is presumed to
> be the original intent but would be reliant on compilers always having
> pq_dest contiguous with the final element of pq_src.

    Signoff is missing -- the patch can't be applied without it.

> ---
>   drivers/dma/iop-adma.c |    4 ++--
>   1 files changed, 2 insertions(+), 2 deletions(-)

> diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
> index 04be90b..58173ee 100644
> --- a/drivers/dma/iop-adma.c
> +++ b/drivers/dma/iop-adma.c
> @@ -1271,8 +1271,8 @@ iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device)
>   	struct page **pq_hw =&pq[IOP_ADMA_NUM_SRC_TEST+2];
>   	/* address conversion buffers (dma_map / page_address) */
>   	void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2];
> -	dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST];
> -	dma_addr_t pq_dest[2];
> +	dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST+2];
> +	dma_addr_t *pq_dest =&(pq_src[IOP_ADMA_NUM_SRC_TEST]);

    () not necessary.

WBR, Sergei


From broonie at opensource.wolfsonmicro.com  Thu Mar  1 05:52:40 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 1 Mar 2012 10:52:40 +0000
Subject: [PATCH] ARM: 3ds_debugboard: Let ethernet be functional again
In-Reply-To: <20120301100847.GF26642@pengutronix.de>
References: <1328646473-11828-1-git-send-email-festevam@gmail.com>
 <20120213082741.GN3852@pengutronix.de>
 <20120213144820.GA3494@opensource.wolfsonmicro.com>
 <20120214105823.GS3852@pengutronix.de>
 <20120214172902.GB3916@opensource.wolfsonmicro.com>
 <20120216073236.GE3852@pengutronix.de>
 <20120216075825.GA11631@opensource.wolfsonmicro.com>
 <20120301100847.GF26642@pengutronix.de>
Message-ID: <20120301105239.GA3124@opensource.wolfsonmicro.com>

On Thu, Mar 01, 2012 at 11:08:47AM +0100, Sascha Hauer wrote:

> Ok, I tried to do this. I Changed the function to:

> static struct platform_device *regulator_register_fixed(int id,
> 		struct regulator_consumer_supply *supplies, int num_supplies)

> Now I have to register a fixed regulator with some invented value
> for microvolts. What value should I choose? I tried 0 but the core
> won't accept this as explained earlier, in short regulator_register()
> returns with an error.

I've already suggested just fixing the fixed voltage regulator to be
more sensible when it doesn't have a voltage but you say that won't work
without explaining why you think that is the case and are still ignoring
my repeated queries about that.
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From hvaibhav at ti.com  Thu Mar  1 05:54:41 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Thu, 1 Mar 2012 10:54:41 +0000
Subject: [PATCH-V2 2/2] arm:omap:am33xx: Add power domain data
In-Reply-To: <alpine.DEB.2.00.1202291839130.12752@utopia.booyaka.com>
References: <1324803628-16790-1-git-send-email-hvaibhav@ti.com>
 <1324803628-16790-3-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1202291839130.12752@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A8317E515D@DBDE01.ent.ti.com>

On Thu, Mar 01, 2012 at 07:14:24, Paul Walmsley wrote:
> Hi
> 
> some other observations:
> 
> On Sun, 25 Dec 2011, Vaibhav Hiremath wrote:
> 
> > +static struct powerdomain per_33xx_pwrdm = {
> > +	.name			= "per_pwrdm",
> > +	.voltdm			= { .name = "core" },
> > +	.prcm_partition		= AM33XX_PRM_PARTITION,
> > +	.prcm_offs		= AM33XX_PRM_PER_MOD,
> > +	.pwrsts			= PWRSTS_OFF_RET_ON,
> > +	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
> > +	.pwrstctrl_offs		= AM33XX_PM_PER_PWRSTCTRL_OFFSET,
> > +	.pwrstst_offs		= AM33XX_PM_PER_PWRSTST_OFFSET,
> > +	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
> > +	.banks			= 3,
> > +	.pwrsts_mem_ret		= {
> > +		[0]	= PWRSTS_OFF_RET,	/* icss_mem */
> > +		[1]	= PWRSTS_OFF_RET,	/* per_mem */
> > +		[2]	= PWRSTS_OFF_RET,	/* ram_mem */
> > +	},
> > +	.pwrsts_mem_on		= {
> > +		[0]	= PWRSTS_ON,		/* icss_mem */
> > +		[1]	= PWRSTS_ON,		/* per_mem */
> > +		[2]	= PWRSTS_ON,		/* ram_mem */
> > +	},
> > +};
> 
> According to SPRUH73C Table 8-184 "PM_PER_PWRSTCTRL Register Field 
> Descriptions" the pwrsts_mem_on field for RAM_MEM should be 
> PWRSTS_OFF_RET_ON.
> 
> > +static struct powerdomain mpu_33xx_pwrdm = {
> > +     .name                   = "mpu_pwrdm",
> > +     .voltdm                 = { .name = "mpu" },
> > +     .prcm_partition         = AM33XX_PRM_PARTITION,
> > +     .prcm_offs              = AM33XX_PRM_MPU_MOD,
> > +     .pwrsts                 = PWRSTS_OFF_RET_ON,
> > +     .pwrsts_logic_ret       = PWRSTS_OFF_RET,
> > +     .pwrstctrl_offs         = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
> > +     .pwrstst_offs           = AM33XX_PM_MPU_PWRSTST_OFFSET,
> > +     .flags                  = PWRDM_HAS_LOWPOWERSTATECHANGE,
> > +     .banks                  = 3,
> > +     .pwrsts_mem_ret         = {
> > +             [0]     = PWRSTS_OFF_RET,       /* mpu_l1 */
> > +             [1]     = PWRSTS_OFF_RET,       /* mpu_l2 */
> > +             [2]     = PWRSTS_OFF_RET,       /* mpu_ram */
> > +     },
> 
> Again SPRUH73C Table 8-191 "PM_MPU_PWRSTCTRL Register Field Descriptions" 
> claims these should simply by PWRSTS_RET.
> 
> > +     .pwrsts_mem_on          = {
> > +             [0]     = PWRSTS_ON,            /* mpu_l1 */
> > +             [1]     = PWRSTS_ON,            /* mpu_l2 */
> > +             [2]     = PWRSTS_ON,            /* mpu_ram */
> > +     },
> > +};
> 
> And the same table claims the MPU_RAM pwrsts_mem_on field should be 
> PWRSTS_OFF_ON.
> 
> Can you please reconcile these differences and let us know which values 
> should be correct?
> 

Paul,

The initialization used in the patch is correct. Unfortunately, the TRM is 
incorrect here. I have already raised this issue with respective folks and soon it will get corrected.

Thanks,
Vaibhav

> thanks
> 
> 
> - Paul
> 



From sameo at linux.intel.com  Thu Mar  1 06:01:46 2012
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Thu, 1 Mar 2012 12:01:46 +0100
Subject: [V4 0/4] patches for power control on pm8606 oscillator
In-Reply-To: <1330397869-31644-1-git-send-email-jtzhou@marvell.com>
References: <1330397869-31644-1-git-send-email-jtzhou@marvell.com>
Message-ID: <20120301110146.GG9008@sortiz-mobl>

Hi Jett,

On Tue, Feb 28, 2012 at 10:57:49AM +0800, Jett.Zhou wrote:
> change log:
> V4:
> 1 seperated the mfd power control osc patch for more clear.

All 4 patches applied now, thanks.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From sameo at linux.intel.com  Thu Mar  1 06:23:29 2012
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Thu, 1 Mar 2012 12:23:29 +0100
Subject: [PATCH v5 2/3] arm:davinci: move emif driver to mfd framework
In-Reply-To: <A73F36158E33644199EB82C5EC81C7BC3176D103@DBDE01.ent.ti.com>
References: <y> <1330005504-25321-3-git-send-email-prakash.pm@ti.com>
 <20120227142638.GN27687@sortiz-mobl>
 <A73F36158E33644199EB82C5EC81C7BC3176D103@DBDE01.ent.ti.com>
Message-ID: <20120301112329.GI9008@sortiz-mobl>

Hi Prakash,

On Tue, Feb 28, 2012 at 05:44:39AM +0000, Manjunathappa, Prakash wrote:
> Hi Samuel,
> 
> On Mon, Feb 27, 2012 at 19:56:38, Samuel Ortiz wrote:
> [snip]
> > So it seems you're passing a platform devices array through your mfd aemif
> > platform data pointer. And from what I can see, it's mostly a 1 entry array
> > (for the NAND case) or a 2 entries array (for the NAND and NOR case).
> > In that case, adding an MFD driver in the middle brings basically nothing but
> > confusion and overhead (and 200+ lines of code).
> > So unless someone explains to me how this is doing any good to the kernel in
> > general, I'm not going to take this patchset.
> > 
> > Cheers,
> > Samuel.
> >
> 
> In this way we trying to isolate future modification of aemif driver not to depict
> as platform code change, the need for this is based on discussion in below thread
> http://davinci-linux-open-source.1494791.n2.nabble.com/PATCH-arm-davinci-configure-davinci-aemif-chipselects-through-OF-tt7059739.html#none
> 
I fail to see how you're going to achieve that with adding an MFD platform
device registration in the middle.


> Earlier also concern was expressed to move aemif driver out of arch/arm to drivers folder.
> Here is the link for the same: http://lists.infradead.org/pipermail/linux-mtd/2011-August/037308.html
> Since aemif driver supports NAND/NOR devices, we feel MFD is the place holder.
I would disagree with that. And it certainly makes sense to move many drivers
out of arch/arm into a more appropriate place but I'd like to keep mfd as
something else than yet another misc.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From broonie at opensource.wolfsonmicro.com  Thu Mar  1 06:17:45 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 1 Mar 2012 11:17:45 +0000
Subject: [PATCH v5 2/2] Regulator: Add Anatop regulator driver
In-Reply-To: <1330593052-15184-2-git-send-email-paul.liu@linaro.org>
References: <1328734286-30091-1-git-send-email-paul.liu@linaro.org>
 <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
 <1330593052-15184-2-git-send-email-paul.liu@linaro.org>
Message-ID: <20120301111744.GC3124@opensource.wolfsonmicro.com>

On Thu, Mar 01, 2012 at 05:10:52PM +0800, Ying-Chun Liu (PaulLiu) wrote:

> +	if (IS_ERR(rdev)) {
> +		dev_err(&pdev->dev, "failed to register %s\n",
> +			rdesc->name);
> +		kfree(rdesc->name);
> +		return PTR_ERR(rdev);
> +	}
> +
> +	return 0;
> +}
> +
> +int anatop_regulator_remove(struct platform_device *pdev)
> +{
> +	struct regulator_dev *rdev = platform_get_drvdata(pdev);
> +	regulator_unregister(rdev);
> +	return 0;

Looks mostly good but this leaks rdesc->name which was allocated with
kstrdup() in the probe() function.
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From sameo at linux.intel.com  Thu Mar  1 06:39:44 2012
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Thu, 1 Mar 2012 12:39:44 +0100
Subject: [PATCH 1/5] mfd : ux500 - Cleanup duplicate definitions
In-Reply-To: <1330465569-567-1-git-send-email-daniel.lezcano@linaro.org>
References: <1330465569-567-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <20120301113944.GJ9008@sortiz-mobl>

Hi Daniel,

On Tue, Feb 28, 2012 at 10:46:05PM +0100, daniel.lezcano at linaro.org wrote:
> From: Daniel Lezcano <daniel.lezcano at linaro.org>
> 
> I missed in my previous patch the A9_MASK_REQ[_MASK] were
> already defined. Let's remove the duplicate definitions.
> 
> The PRCMU_GIC_DELAY macro could be removed as it is not
> really useful here.
This one and the 4 other patches applied. Thanks.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From daniel.lezcano at linaro.org  Thu Mar  1 06:34:44 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Thu, 01 Mar 2012 12:34:44 +0100
Subject: [PATCH 1/5] mfd : ux500 - Cleanup duplicate definitions
In-Reply-To: <20120301113944.GJ9008@sortiz-mobl>
References: <1330465569-567-1-git-send-email-daniel.lezcano@linaro.org>
 <20120301113944.GJ9008@sortiz-mobl>
Message-ID: <4F4F5ED4.2070508@linaro.org>

On 03/01/2012 12:39 PM, Samuel Ortiz wrote:
> Hi Daniel,
>
> On Tue, Feb 28, 2012 at 10:46:05PM +0100, daniel.lezcano at linaro.org wrote:
>> From: Daniel Lezcano<daniel.lezcano at linaro.org>
>>
>> I missed in my previous patch the A9_MASK_REQ[_MASK] were
>> already defined. Let's remove the duplicate definitions.
>>
>> The PRCMU_GIC_DELAY macro could be removed as it is not
>> really useful here.
> This one and the 4 other patches applied. Thanks.

Thanks Samuel.

   -- Daniel

-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From broonie at opensource.wolfsonmicro.com  Thu Mar  1 06:30:32 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 1 Mar 2012 11:30:32 +0000
Subject: [PATCH v5 1/2] mfd: Add anatop mfd driver
In-Reply-To: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
References: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120301113031.GD3124@opensource.wolfsonmicro.com>

On Thu, Mar 01, 2012 at 05:10:51PM +0800, Ying-Chun Liu (PaulLiu) wrote:

> +	spin_lock(&adata->reglock);
> +	val = readl(adata->ioreg + addr);
> +	spin_unlock(&adata->reglock);

Do you really need to take a lock for a single read operation from a
memory mapped register?  I'd expect this to be atomic in itself.  You
need to lock on read/modify/write cycles to make sure that you don't get
a read/read/modify/modify/write/write and misplace one of the modifies
but that's not an issue for an isolated read.
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From arnd at arndb.de  Thu Mar  1 06:40:43 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 11:40:43 +0000
Subject: [PATCH 7/7] Minor compiling fix
In-Reply-To: <4F4F36DD.3020005@gmail.com>
References: <1329126268-11032-1-git-send-email-bill4carson@gmail.com>
 <201202291235.04113.arnd@arndb.de> <4F4F36DD.3020005@gmail.com>
Message-ID: <201203011140.44364.arnd@arndb.de>

On Thursday 01 March 2012, bill4carson wrote:
> On 2012?02?29? 20:35, Arnd Bergmann wrote:
> > On Monday 13 February 2012, Bill Carson wrote:
> >> --- a/arch/arm/mm/dma-mapping.c
> >> +++ b/arch/arm/mm/dma-mapping.c
> >> @@ -152,9 +152,6 @@ static struct arm_vmregion_head consistent_head = {
> >>          .vm_end         = CONSISTENT_END,
> >>   };
> >>
> >> -#ifdef CONFIG_HUGETLB_PAGE
> >> -#error ARM Coherent DMA allocator does not (yet) support huge TLB
> >> -#endif
> >
> > This one needs an explanation, too. What has changed that now allows
> > dma_alloc_coherent to work with CONFIG_HUGETLB_PAGE set that did not
> > work before?
> >
> 
> AFAIK, __dma_alloc has the finest granularity at 4k page size even when
> user requests 1M bytes memory.
> 
> but current hugetlb low level set_hugepte_at *ONLY*/*MUST* support 2M 
> page mapping, so it can't be used to create huge dma mapping in a more
> general way.
> 
> comments this error out doesn't mean that it could support huge page dma
> mapping now with this patch, just shut up gcc when compiling.
> 
> Adding a single low level hook to create 1M page mapping can satisfy
> the needs, but apparently that's out of hugetlb scope.
> And it's on my TODO list :)

Hmm, I'm still not sure I'm following. The coherent DMA area is currently
limited to 2MB or a small multiple of that, so you would not be able
to allocate coherent hugepages anyway.

Further, I don't think there are any device drivers that call
dma_alloc_coherent and expect to map the resulting page into
user space, or that we even have an interface for that.

This entire chunk of code is also getting changed with the addition of CMA.

	Arnd


From pdeschrijver at nvidia.com  Thu Mar  1 06:42:11 2012
From: pdeschrijver at nvidia.com (Peter De Schrijver)
Date: Thu, 1 Mar 2012 13:42:11 +0200
Subject: [PATCH v3 00/10] Add tegra30 support for secondary cores
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BDDF21F3@HQMAIL01.nvidia.com>
References: <1328831277-21002-1-git-send-email-pdeschrijver@nvidia.com>
 <74CDBE0F657A3D45AFBB94109FB122FF178FACB954@HQMAIL01.nvidia.com>
 <20120229154229.GL12917@tbergstrom-lnx.Nvidia.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF21F3@HQMAIL01.nvidia.com>
Message-ID: <20120301114211.GP12917@tbergstrom-lnx.Nvidia.com>

On Wed, Feb 29, 2012 at 11:38:16PM +0100, Stephen Warren wrote:
> Peter De Schrijver wrote at Wednesday, February 29, 2012 8:42 AM:
> > On Wed, Feb 15, 2012 at 10:27:43PM +0100, Stephen Warren wrote:
> > > Peter De Schrijver wrote at Thursday, February 09, 2012 4:48 PM:
> > > > This patchset introduces support for secondary cores on tegra30. It also
> > > > introduces some functions for the flowcontroller and adds basic support for
> > > > tegra30 powerdomains.
> > >
> > > The code looks fine to me. I do notice the following when running
> > > "shutdown -h now":
> > >
> > > [   27.762124] SMP: failed to stop secondary CPUs
> 
> I can't seem to reproduce this at all on next-20120229 anymore. What
> kind of repro frequency are you seeing, and does it get fixed if you
> update to that baseline?
> 

I see it abount once every 3 reboots. I have a an expect script which
automates the test. I haven't tried with next-20120229 yet.

> (I tried 20 times with shutdown, and 15 of them I reverted all the CPU
> and cache errata in case they affected the issue at all)

Cheers,

Peter.


From arnd at arndb.de  Thu Mar  1 06:49:42 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 11:49:42 +0000
Subject: at91: Error while registering DMA controller in 3.3-rc
In-Reply-To: <4F4F49E1.4020902@atmel.com>
References: <4F4F49E1.4020902@atmel.com>
Message-ID: <201203011149.42948.arnd@arndb.de>

On Thursday 01 March 2012, Nicolas Ferre wrote:
> We currently have a regression on 3.3-rc kernels about the DMA
> controller registration.
> 
> http://article.gmane.org/gmane.linux.kernel.mmc/13014
> 
> This is due to the DMA driver having seen an update during the 3.3 merge
> window  but the AT91 device files not having the corresponding
> modifications.
> 
> Maybe you remember, those modifications where part of the famous AT91
> board/device series that was postponed to 3.4 due to a flood of issues...
> 
> So now, I would like to know if it is possible to resolve this problem
> by queuing the DMA related patches that we have already in
> at91/device-board branch to mainline before 3.3-final?

Yes, that should be possible. We try not have the same patches in multiple
branches, but since this is a regression, I think we should do it anyway.

> The patches that I am talking about are:
> 
> bdad0b9 ARM: at91/dma: remove platform data from DMA controller
> and
> 2756bf5 ARM: at91/dma: DMA controller registering with DT support
> 
> I do think it is pretty silly to try to resolve this issue by not taking
> those two little patches and modifying source code to workaround this
> issue. If we do this, we will get conflicts and need to rework the
> already queued 3.4 material.
> 
> Do you want me to prepare a new at91-fixes branch with those two patches
> or you can take them yourself?

Better send me a pull request so that you can do some testing on the
exact branch that you send me. I would probably end up with the
same tree and I'm not worried about doing it, but we should make sure
that it actually works.

	Arnd


From dave.martin at linaro.org  Thu Mar  1 06:49:42 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 1 Mar 2012 11:49:42 +0000
Subject: [RFC PATCH 0/2] ARM: assembler: Add uniform assembler framework
In-Reply-To: <20120228192458.GC3617@n2100.arm.linux.org.uk>
References: <1330455586-10353-1-git-send-email-dave.martin@linaro.org>
 <20120228192458.GC3617@n2100.arm.linux.org.uk>
Message-ID: <20120301114942.GA2040@linaro.org>

On Tue, Feb 28, 2012 at 07:24:59PM +0000, Russell King - ARM Linux wrote:
> On Tue, Feb 28, 2012 at 06:59:44PM +0000, Dave Martin wrote:
> > #ifdef __ASSEMBLY__
> > stuff
> > for
> > the
> > assembler
> > #else
> > asm("stuff");
> > asm("for");
> > asm("the");
> > asm("assembler");
> 
> That's invalid - nothing guarantees that the compiler won't place
> anything in between these asm statements in the output assembly
> file.

Are you still interested in this series?

I have a workaround for the above now, but it's not pretty -- I seem to
have opened a can of worms here.


We would need something like

#define EXTENDED_ASM(stuff) asm ( ".include \"macros.inc\"\n\t" stuff )
#define EXTENDED_VASM(stuff) asm volatile ( ".include \"macros.inc\"\n\t" stuff )

...where macros.inc includes some logic to protect against multiple
inclusion.

This would avoid problems caused by reordering done by the compiler.

I think this can work, but it may be a step too far...


The above could help fix the incorrect way that asm/unified.h defines
the it* macros (though admittedly that does not seem to have caused
problems for anyone so far...)

Cheers
---Dave


From stefano.stabellini at eu.citrix.com  Thu Mar  1 07:12:25 2012
From: stefano.stabellini at eu.citrix.com (Stefano Stabellini)
Date: Thu, 1 Mar 2012 12:12:25 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <20120301103520.GD7363@n2100.arm.linux.org.uk>
References: <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <20120301101029.GB7363@n2100.arm.linux.org.uk>
 <20120301102702.GD2034@linaro.org>
 <20120301103520.GD7363@n2100.arm.linux.org.uk>
Message-ID: <alpine.DEB.2.00.1203011209580.923@kaball-desktop>

On Thu, 1 Mar 2012, Russell King - ARM Linux wrote:
> On Thu, Mar 01, 2012 at 10:27:02AM +0000, Dave Martin wrote:
> > So, where there's a compelling reason to inline these things, we can use
> > the existing techniques if we're alert to the risks.  But in cases where
> > there isn't a compelling reason, aren't we just inviting fragility
> > unnecessarily?
> 
> The practical experience from the kernel suggests that there isn't a
> problem - that's not to say that future versions of gcc won't become
> a problem, and that the compiler guys may refuse to fix it.
> 
> I think it's a feature that we should be pressing gcc guys for - it's
> fairly fundamental to any programming which requires interfaces that
> require certain args in certain registers, or receive results in
> certain registers.
> 
> The options over this are basically:
> 1. refusing to upgrade to any version of gcc which does not allow
>    registers-in-asm
> 2. doing the store-to-memory reload-in-asm thing
> 3. hand-coding veneers for every call to marshall the registers
> 
> Each of those has its down sides, but I suspect with (1), it may be
> possible to have enough people applying pressure to the compiler guys
> that they finally see sense on this matter.

I tend to have a very practical approach about this sort of issues, so I
am tempted to go with 1) if you agree.


From arnd at arndb.de  Thu Mar  1 07:28:33 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 12:28:33 +0000
Subject: linux-next: manual merge of the arm-soc tree with the gpio tree
In-Reply-To: <20120301164001.77a063ceed2deaf37cf68e3c@canb.auug.org.au>
References: <20120301164001.77a063ceed2deaf37cf68e3c@canb.auug.org.au>
Message-ID: <201203011228.33983.arnd@arndb.de>

On Thursday 01 March 2012, Stephen Rothwell wrote:
> Today's linux-next merge of the arm-soc tree got conflicts in
> arch/arm/mach-omap1/gpio16xx.c between commit ab985f0f7c2c ("gpio/omap:
> cleanup omap_gpio_mod_init function") from the gpio tree and commit
> 63325ff235de ("ARM: OMAP1: Move 16xx GPIO system clock to platform init
> code") from the arm-soc tree.
> 
> OK, I can't decide which is correct here - the former adds this code
> inside the loop (even though it seems to not depend on anything in the
> loop) and the latter adds it before.  I have used the former (but am
> happy to be corrected).  And both commits remove the code in
> drivers/gpio/gpio-omap.c.

Right, having the code outside of the loop seems correct to me, too.

Grant, I would suggest that I resolve this by merging the the
omap/gpio/runtime-pm-cleanup branch (f86bcc3) that is in your
tree into the arm-soc tree as a dependency for the omap1 stuff,
with the resolution below.

	Arnd

--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@@ -218,17 -225,34 +225,34 @@@ static int __init omap16xx_gpio_init(vo
  	if (!cpu_is_omap16xx())
  		return -EINVAL;
  
 +	/*
 +	 * Enable system clock for GPIO module.
 +	 * The CAM_CLK_CTRL *is* really the right place.
 +	 */
 +	omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
 +					ULPD_CAM_CLK_CTRL);
 +
- 	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
- 		platform_device_register(omap16xx_gpio_dev[i]);
+ 	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
+ 		pdev = omap16xx_gpio_dev[i];
+ 		pdata = pdev->dev.platform_data;
+ 
+ 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 		if (unlikely(!res)) {
+ 			dev_err(&pdev->dev, "Invalid mem resource.\n");
+ 			return -ENODEV;
+ 		}
  
- 	gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
+ 		base = ioremap(res->start, resource_size(res));
+ 		if (unlikely(!base)) {
+ 			dev_err(&pdev->dev, "ioremap failed.\n");
+ 			return -ENOMEM;
+ 		}
+ 
+ 		__raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG);
+ 		iounmap(base);
+ 
 -		/*
 -		 * Enable system clock for GPIO module.
 -		 * The CAM_CLK_CTRL *is* really the right place.
 -		 */
 -		omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
 -					ULPD_CAM_CLK_CTRL);
 -
+ 		platform_device_register(omap16xx_gpio_dev[i]);
+ 	}
  
  	return 0;
  }


From svenkatr at ti.com  Thu Mar  1 07:40:40 2012
From: svenkatr at ti.com (S, Venkatraman)
Date: Thu, 1 Mar 2012 18:10:40 +0530
Subject: [PATCH V2 1/1] mmc: start removing enable / disable API
In-Reply-To: <1330499841-6879-2-git-send-email-adrian.hunter@intel.com>
References: <1330499841-6879-1-git-send-email-adrian.hunter@intel.com>
 <1330499841-6879-2-git-send-email-adrian.hunter@intel.com>
Message-ID: <CANfBPZ-JLoMqq0ZfpbFTHDprkAPdqorTRyuyAJ=oLCbSwWhRjg@mail.gmail.com>

On Wed, Feb 29, 2012 at 12:47 PM, Adrian Hunter <adrian.hunter at intel.com> wrote:
> Most parts of the enable / disable API are no longer used and
> can be removed.
>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Cc: Venkatraman S <svenkatr at ti.com>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Cc: Thomas Abraham <thomas.abraham at linaro.org>
> Cc: Kyungmin Park <kyungmin.park at samsung.com>
> Cc: Sekhar Nori <nsekhar at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Signed-off-by: Adrian Hunter <adrian.hunter at intel.com>

Tested on OMAP4 SDP Platform
Tested-by: Venkatraman S <svenkatr at ti.com>
> ---
> ?arch/arm/mach-exynos/mach-nuri.c ? ? ? ? ? | ? ?5 +-
> ?arch/arm/mach-exynos/mach-universal_c210.c | ? ?9 +-
> ?drivers/mmc/core/core.c ? ? ? ? ? ? ? ? ? ?| ?187 +++-------------------------
> ?drivers/mmc/core/host.c ? ? ? ? ? ? ? ? ? ?| ? ?1 -
> ?drivers/mmc/core/host.h ? ? ? ? ? ? ? ? ? ?| ? ?1 -
> ?drivers/mmc/host/davinci_mmc.c ? ? ? ? ? ? | ? ?4 -
> ?drivers/mmc/host/omap_hsmmc.c ? ? ? ? ? ? ?| ? 15 +--
> ?include/linux/mmc/core.h ? ? ? ? ? ? ? ? ? | ? ?1 -
> ?include/linux/mmc/host.h ? ? ? ? ? ? ? ? ? | ? 46 +------
> ?9 files changed, 27 insertions(+), 242 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
> index 644af11..de68248 100644
> --- a/arch/arm/mach-exynos/mach-nuri.c
> +++ b/arch/arm/mach-exynos/mach-nuri.c
> @@ -109,7 +109,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
> ? ? ? ?.max_width ? ? ? ? ? ? ?= 8,
> ? ? ? ?.host_caps ? ? ? ? ? ? ?= (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_DISABLE | MMC_CAP_ERASE),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_ERASE),
> ? ? ? ?.cd_type ? ? ? ? ? ? ? ?= S3C_SDHCI_CD_PERMANENT,
> ?};
>
> @@ -147,8 +147,7 @@ static struct platform_device emmc_fixed_voltage = {
> ?static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
> ? ? ? ?.max_width ? ? ? ? ? ? ?= 4,
> ? ? ? ?.host_caps ? ? ? ? ? ? ?= MMC_CAP_4_BIT_DATA |
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_DISABLE,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
> ? ? ? ?.ext_cd_gpio ? ? ? ? ? ?= EXYNOS4_GPX3(3), ? ? ?/* XEINT_27 */
> ? ? ? ?.ext_cd_gpio_invert ? ? = 1,
> ? ? ? ?.cd_type ? ? ? ? ? ? ? ?= S3C_SDHCI_CD_GPIO,
> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
> index 9b3fbae..57cfe61 100644
> --- a/arch/arm/mach-exynos/mach-universal_c210.c
> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
> @@ -734,8 +734,7 @@ static struct platform_device universal_gpio_keys = {
> ?static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
> ? ? ? ?.max_width ? ? ? ? ? ? ?= 8,
> ? ? ? ?.host_caps ? ? ? ? ? ? ?= (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_DISABLE),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
> ? ? ? ?.cd_type ? ? ? ? ? ? ? ?= S3C_SDHCI_CD_PERMANENT,
> ?};
>
> @@ -772,8 +771,7 @@ static struct platform_device mmc0_fixed_voltage = {
> ?static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
> ? ? ? ?.max_width ? ? ? ? ? ? ?= 4,
> ? ? ? ?.host_caps ? ? ? ? ? ? ?= MMC_CAP_4_BIT_DATA |
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_DISABLE,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
> ? ? ? ?.ext_cd_gpio ? ? ? ? ? ?= EXYNOS4_GPX3(4), ? ? ?/* XEINT_28 */
> ? ? ? ?.ext_cd_gpio_invert ? ? = 1,
> ? ? ? ?.cd_type ? ? ? ? ? ? ? ?= S3C_SDHCI_CD_GPIO,
> @@ -783,8 +781,7 @@ static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
> ?static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
> ? ? ? ?.max_width ? ? ? ? ? ? ?= 4,
> ? ? ? ?.host_caps ? ? ? ? ? ? ?= MMC_CAP_4_BIT_DATA |
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_DISABLE,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
> ? ? ? ?.cd_type ? ? ? ? ? ? ? ?= S3C_SDHCI_CD_EXTERNAL,
> ?};
>
> diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
> index 0b317f0..44dd013 100644
> --- a/drivers/mmc/core/core.c
> +++ b/drivers/mmc/core/core.c
> @@ -605,105 +605,6 @@ unsigned int mmc_align_data_size(struct mmc_card *card, unsigned int sz)
> ?EXPORT_SYMBOL(mmc_align_data_size);
>
> ?/**
> - * ? ? mmc_host_enable - enable a host.
> - * ? ? @host: mmc host to enable
> - *
> - * ? ? Hosts that support power saving can use the 'enable' and 'disable'
> - * ? ? methods to exit and enter power saving states. For more information
> - * ? ? see comments for struct mmc_host_ops.
> - */
> -int mmc_host_enable(struct mmc_host *host)
> -{
> - ? ? ? if (!(host->caps & MMC_CAP_DISABLE))
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? if (host->en_dis_recurs)
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? if (host->nesting_cnt++)
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? cancel_delayed_work_sync(&host->disable);
> -
> - ? ? ? if (host->enabled)
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? if (host->ops->enable) {
> - ? ? ? ? ? ? ? int err;
> -
> - ? ? ? ? ? ? ? host->en_dis_recurs = 1;
> - ? ? ? ? ? ? ? mmc_host_clk_hold(host);
> - ? ? ? ? ? ? ? err = host->ops->enable(host);
> - ? ? ? ? ? ? ? mmc_host_clk_release(host);
> - ? ? ? ? ? ? ? host->en_dis_recurs = 0;
> -
> - ? ? ? ? ? ? ? if (err) {
> - ? ? ? ? ? ? ? ? ? ? ? pr_debug("%s: enable error %d\n",
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?mmc_hostname(host), err);
> - ? ? ? ? ? ? ? ? ? ? ? return err;
> - ? ? ? ? ? ? ? }
> - ? ? ? }
> - ? ? ? host->enabled = 1;
> - ? ? ? return 0;
> -}
> -EXPORT_SYMBOL(mmc_host_enable);
> -
> -static int mmc_host_do_disable(struct mmc_host *host, int lazy)
> -{
> - ? ? ? if (host->ops->disable) {
> - ? ? ? ? ? ? ? int err;
> -
> - ? ? ? ? ? ? ? host->en_dis_recurs = 1;
> - ? ? ? ? ? ? ? mmc_host_clk_hold(host);
> - ? ? ? ? ? ? ? err = host->ops->disable(host, lazy);
> - ? ? ? ? ? ? ? mmc_host_clk_release(host);
> - ? ? ? ? ? ? ? host->en_dis_recurs = 0;
> -
> - ? ? ? ? ? ? ? if (err < 0) {
> - ? ? ? ? ? ? ? ? ? ? ? pr_debug("%s: disable error %d\n",
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?mmc_hostname(host), err);
> - ? ? ? ? ? ? ? ? ? ? ? return err;
> - ? ? ? ? ? ? ? }
> - ? ? ? ? ? ? ? if (err > 0) {
> - ? ? ? ? ? ? ? ? ? ? ? unsigned long delay = msecs_to_jiffies(err);
> -
> - ? ? ? ? ? ? ? ? ? ? ? mmc_schedule_delayed_work(&host->disable, delay);
> - ? ? ? ? ? ? ? }
> - ? ? ? }
> - ? ? ? host->enabled = 0;
> - ? ? ? return 0;
> -}
> -
> -/**
> - * ? ? mmc_host_disable - disable a host.
> - * ? ? @host: mmc host to disable
> - *
> - * ? ? Hosts that support power saving can use the 'enable' and 'disable'
> - * ? ? methods to exit and enter power saving states. For more information
> - * ? ? see comments for struct mmc_host_ops.
> - */
> -int mmc_host_disable(struct mmc_host *host)
> -{
> - ? ? ? int err;
> -
> - ? ? ? if (!(host->caps & MMC_CAP_DISABLE))
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? if (host->en_dis_recurs)
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? if (--host->nesting_cnt)
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? if (!host->enabled)
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? err = mmc_host_do_disable(host, 0);
> - ? ? ? return err;
> -}
> -EXPORT_SYMBOL(mmc_host_disable);
> -
> -/**
> ?* ? ? __mmc_claim_host - exclusively claim a host
> ?* ? ? @host: mmc host to claim
> ?* ? ? @abort: whether or not the operation should be aborted
> @@ -741,8 +642,8 @@ int __mmc_claim_host(struct mmc_host *host, atomic_t *abort)
> ? ? ? ? ? ? ? ?wake_up(&host->wq);
> ? ? ? ?spin_unlock_irqrestore(&host->lock, flags);
> ? ? ? ?remove_wait_queue(&host->wq, &wait);
> - ? ? ? if (!stop)
> - ? ? ? ? ? ? ? mmc_host_enable(host);
> + ? ? ? if (host->ops->enable && !stop && host->claim_cnt == 1)
> + ? ? ? ? ? ? ? host->ops->enable(host);
> ? ? ? ?return stop;
> ?}
>
> @@ -767,21 +668,28 @@ int mmc_try_claim_host(struct mmc_host *host)
> ? ? ? ? ? ? ? ?claimed_host = 1;
> ? ? ? ?}
> ? ? ? ?spin_unlock_irqrestore(&host->lock, flags);
> + ? ? ? if (host->ops->enable && claimed_host && host->claim_cnt == 1)
> + ? ? ? ? ? ? ? host->ops->enable(host);
> ? ? ? ?return claimed_host;
> ?}
> ?EXPORT_SYMBOL(mmc_try_claim_host);
>
> ?/**
> - * ? ? mmc_do_release_host - release a claimed host
> + * ? ? mmc_release_host - release a host
> ?* ? ? @host: mmc host to release
> ?*
> - * ? ? If you successfully claimed a host, this function will
> - * ? ? release it again.
> + * ? ? Release a MMC host, allowing others to claim the host
> + * ? ? for their operations.
> ?*/
> -void mmc_do_release_host(struct mmc_host *host)
> +void mmc_release_host(struct mmc_host *host)
> ?{
> ? ? ? ?unsigned long flags;
>
> + ? ? ? WARN_ON(!host->claimed);
> +
> + ? ? ? if (host->ops->disable && host->claim_cnt == 1)
> + ? ? ? ? ? ? ? host->ops->disable(host);
> +
> ? ? ? ?spin_lock_irqsave(&host->lock, flags);
> ? ? ? ?if (--host->claim_cnt) {
> ? ? ? ? ? ? ? ?/* Release for nested claim */
> @@ -793,67 +701,6 @@ void mmc_do_release_host(struct mmc_host *host)
> ? ? ? ? ? ? ? ?wake_up(&host->wq);
> ? ? ? ?}
> ?}
> -EXPORT_SYMBOL(mmc_do_release_host);
> -
> -void mmc_host_deeper_disable(struct work_struct *work)
> -{
> - ? ? ? struct mmc_host *host =
> - ? ? ? ? ? ? ? container_of(work, struct mmc_host, disable.work);
> -
> - ? ? ? /* If the host is claimed then we do not want to disable it anymore */
> - ? ? ? if (!mmc_try_claim_host(host))
> - ? ? ? ? ? ? ? return;
> - ? ? ? mmc_host_do_disable(host, 1);
> - ? ? ? mmc_do_release_host(host);
> -}
> -
> -/**
> - * ? ? mmc_host_lazy_disable - lazily disable a host.
> - * ? ? @host: mmc host to disable
> - *
> - * ? ? Hosts that support power saving can use the 'enable' and 'disable'
> - * ? ? methods to exit and enter power saving states. For more information
> - * ? ? see comments for struct mmc_host_ops.
> - */
> -int mmc_host_lazy_disable(struct mmc_host *host)
> -{
> - ? ? ? if (!(host->caps & MMC_CAP_DISABLE))
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? if (host->en_dis_recurs)
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? if (--host->nesting_cnt)
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? if (!host->enabled)
> - ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? if (host->disable_delay) {
> - ? ? ? ? ? ? ? mmc_schedule_delayed_work(&host->disable,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? msecs_to_jiffies(host->disable_delay));
> - ? ? ? ? ? ? ? return 0;
> - ? ? ? } else
> - ? ? ? ? ? ? ? return mmc_host_do_disable(host, 1);
> -}
> -EXPORT_SYMBOL(mmc_host_lazy_disable);
> -
> -/**
> - * ? ? mmc_release_host - release a host
> - * ? ? @host: mmc host to release
> - *
> - * ? ? Release a MMC host, allowing others to claim the host
> - * ? ? for their operations.
> - */
> -void mmc_release_host(struct mmc_host *host)
> -{
> - ? ? ? WARN_ON(!host->claimed);
> -
> - ? ? ? mmc_host_lazy_disable(host);
> -
> - ? ? ? mmc_do_release_host(host);
> -}
> -
> ?EXPORT_SYMBOL(mmc_release_host);
>
> ?/*
> @@ -2206,8 +2053,6 @@ void mmc_stop_host(struct mmc_host *host)
> ? ? ? ?spin_unlock_irqrestore(&host->lock, flags);
> ?#endif
>
> - ? ? ? if (host->caps & MMC_CAP_DISABLE)
> - ? ? ? ? ? ? ? cancel_delayed_work(&host->disable);
> ? ? ? ?cancel_delayed_work_sync(&host->detect);
> ? ? ? ?mmc_flush_scheduled_work();
>
> @@ -2402,13 +2247,11 @@ int mmc_suspend_host(struct mmc_host *host)
> ?{
> ? ? ? ?int err = 0;
>
> - ? ? ? if (host->caps & MMC_CAP_DISABLE)
> - ? ? ? ? ? ? ? cancel_delayed_work(&host->disable);
> ? ? ? ?cancel_delayed_work(&host->detect);
> ? ? ? ?mmc_flush_scheduled_work();
> ? ? ? ?if (mmc_try_claim_host(host)) {
> ? ? ? ? ? ? ? ?err = mmc_cache_ctrl(host, 0);
> - ? ? ? ? ? ? ? mmc_do_release_host(host);
> + ? ? ? ? ? ? ? mmc_release_host(host);
> ? ? ? ?} else {
> ? ? ? ? ? ? ? ?err = -EBUSY;
> ? ? ? ?}
> @@ -2429,7 +2272,7 @@ int mmc_suspend_host(struct mmc_host *host)
> ? ? ? ? ? ? ? ? ? ? ? ?if (host->bus_ops->suspend) {
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?err = host->bus_ops->suspend(host);
> ? ? ? ? ? ? ? ? ? ? ? ?}
> - ? ? ? ? ? ? ? ? ? ? ? mmc_do_release_host(host);
> + ? ? ? ? ? ? ? ? ? ? ? mmc_release_host(host);
>
> ? ? ? ? ? ? ? ? ? ? ? ?if (err == -ENOSYS || !host->bus_ops->resume) {
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?/*
> diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
> index c3704e2..91c84c7 100644
> --- a/drivers/mmc/core/host.c
> +++ b/drivers/mmc/core/host.c
> @@ -330,7 +330,6 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
> ? ? ? ?spin_lock_init(&host->lock);
> ? ? ? ?init_waitqueue_head(&host->wq);
> ? ? ? ?INIT_DELAYED_WORK(&host->detect, mmc_rescan);
> - ? ? ? INIT_DELAYED_WORK_DEFERRABLE(&host->disable, mmc_host_deeper_disable);
> ?#ifdef CONFIG_PM
> ? ? ? ?host->pm_notify.notifier_call = mmc_pm_notify;
> ?#endif
> diff --git a/drivers/mmc/core/host.h b/drivers/mmc/core/host.h
> index 08a7852..f2ab9e5 100644
> --- a/drivers/mmc/core/host.h
> +++ b/drivers/mmc/core/host.h
> @@ -14,7 +14,6 @@
>
> ?int mmc_register_host_class(void);
> ?void mmc_unregister_host_class(void);
> -void mmc_host_deeper_disable(struct work_struct *work);
>
> ?#endif
>
> diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
> index 64a8325..8de9c9b 100644
> --- a/drivers/mmc/host/davinci_mmc.c
> +++ b/drivers/mmc/host/davinci_mmc.c
> @@ -1418,17 +1418,14 @@ static int davinci_mmcsd_suspend(struct device *dev)
> ? ? ? ?struct mmc_davinci_host *host = platform_get_drvdata(pdev);
> ? ? ? ?int ret;
>
> - ? ? ? mmc_host_enable(host->mmc);
> ? ? ? ?ret = mmc_suspend_host(host->mmc);
> ? ? ? ?if (!ret) {
> ? ? ? ? ? ? ? ?writel(0, host->base + DAVINCI_MMCIM);
> ? ? ? ? ? ? ? ?mmc_davinci_reset_ctrl(host, 1);
> - ? ? ? ? ? ? ? mmc_host_disable(host->mmc);
> ? ? ? ? ? ? ? ?clk_disable(host->clk);
> ? ? ? ? ? ? ? ?host->suspended = 1;
> ? ? ? ?} else {
> ? ? ? ? ? ? ? ?host->suspended = 0;
> - ? ? ? ? ? ? ? mmc_host_disable(host->mmc);
> ? ? ? ?}
>
> ? ? ? ?return ret;
> @@ -1444,7 +1441,6 @@ static int davinci_mmcsd_resume(struct device *dev)
> ? ? ? ? ? ? ? ?return 0;
>
> ? ? ? ?clk_enable(host->clk);
> - ? ? ? mmc_host_enable(host->mmc);
>
> ? ? ? ?mmc_davinci_reset_ctrl(host, 0);
> ? ? ? ?ret = mmc_resume_host(host->mmc);
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index 36e7f5b..fdb24cf 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -179,7 +179,6 @@ struct omap_hsmmc_host {
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? got_dbclk;
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? response_busy;
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? context_loss;
> - ? ? ? int ? ? ? ? ? ? ? ? ? ? dpm_state;
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? vdd;
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? protect_card;
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? reqs_blocked;
> @@ -1748,7 +1747,7 @@ static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
> ? ? ? ?return 0;
> ?}
>
> -static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
> +static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
> ?{
> ? ? ? ?struct omap_hsmmc_host *host = mmc_priv(mmc);
>
> @@ -1782,15 +1781,8 @@ static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
> ? ? ? ?if (host->pdata->get_context_loss_count)
> ? ? ? ? ? ? ? ?context_loss = host->pdata->get_context_loss_count(host->dev);
>
> - ? ? ? seq_printf(s, "mmc%d:\n"
> - ? ? ? ? ? ? ? ? ? ? ? " enabled:\t%d\n"
> - ? ? ? ? ? ? ? ? ? ? ? " dpm_state:\t%d\n"
> - ? ? ? ? ? ? ? ? ? ? ? " nesting_cnt:\t%d\n"
> - ? ? ? ? ? ? ? ? ? ? ? " ctx_loss:\t%d:%d\n"
> - ? ? ? ? ? ? ? ? ? ? ? "\nregs:\n",
> - ? ? ? ? ? ? ? ? ? ? ? mmc->index, mmc->enabled ? 1 : 0,
> - ? ? ? ? ? ? ? ? ? ? ? host->dpm_state, mmc->nesting_cnt,
> - ? ? ? ? ? ? ? ? ? ? ? host->context_loss, context_loss);
> + ? ? ? seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
> + ? ? ? ? ? ? ? ? ? ? ? mmc->index, host->context_loss, context_loss);
>
> ? ? ? ?if (host->suspended) {
> ? ? ? ? ? ? ? ?seq_printf(s, "host suspended, can't read registers\n");
> @@ -1930,7 +1922,6 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>
> ? ? ? ?omap_hsmmc_context_save(host);
>
> - ? ? ? mmc->caps |= MMC_CAP_DISABLE;
> ? ? ? ?if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
> ? ? ? ? ? ? ? ?dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
> ? ? ? ? ? ? ? ?mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
> diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
> index 87a976c..2bfa589 100644
> --- a/include/linux/mmc/core.h
> +++ b/include/linux/mmc/core.h
> @@ -175,7 +175,6 @@ extern unsigned int mmc_align_data_size(struct mmc_card *, unsigned int);
>
> ?extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort);
> ?extern void mmc_release_host(struct mmc_host *host);
> -extern void mmc_do_release_host(struct mmc_host *host);
> ?extern int mmc_try_claim_host(struct mmc_host *host);
>
> ?extern int mmc_flush_cache(struct mmc_card *);
> diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
> index 37147a4..4da98f7 100644
> --- a/include/linux/mmc/host.h
> +++ b/include/linux/mmc/host.h
> @@ -80,34 +80,11 @@ struct mmc_ios {
>
> ?struct mmc_host_ops {
> ? ? ? ?/*
> - ? ? ? ?* Hosts that support power saving can use the 'enable' and 'disable'
> - ? ? ? ?* methods to exit and enter power saving states. 'enable' is called
> - ? ? ? ?* when the host is claimed and 'disable' is called (or scheduled with
> - ? ? ? ?* a delay) when the host is released. The 'disable' is scheduled if
> - ? ? ? ?* the disable delay set by 'mmc_set_disable_delay()' is non-zero,
> - ? ? ? ?* otherwise 'disable' is called immediately. 'disable' may be
> - ? ? ? ?* scheduled repeatedly, to permit ever greater power saving at the
> - ? ? ? ?* expense of ever greater latency to re-enable. Rescheduling is
> - ? ? ? ?* determined by the return value of the 'disable' method. A positive
> - ? ? ? ?* value gives the delay in milliseconds.
> - ? ? ? ?*
> - ? ? ? ?* In the case where a host function (like set_ios) may be called
> - ? ? ? ?* with or without the host claimed, enabling and disabling can be
> - ? ? ? ?* done directly and will nest correctly. Call 'mmc_host_enable()' and
> - ? ? ? ?* 'mmc_host_lazy_disable()' for this purpose, but note that these
> - ? ? ? ?* functions must be paired.
> - ? ? ? ?*
> - ? ? ? ?* Alternatively, 'mmc_host_enable()' may be paired with
> - ? ? ? ?* 'mmc_host_disable()' which calls 'disable' immediately. ?In this
> - ? ? ? ?* case the 'disable' method will be called with 'lazy' set to 0.
> - ? ? ? ?* This is mainly useful for error paths.
> - ? ? ? ?*
> - ? ? ? ?* Because lazy disable may be called from a work queue, the 'disable'
> - ? ? ? ?* method must claim the host when 'lazy' != 0, which will work
> - ? ? ? ?* correctly because recursion is detected and handled.
> + ? ? ? ?* 'enable' is called when the host is claimed and 'disable' is called
> + ? ? ? ?* when the host is released. 'enable' and 'disable' are deprecated.
> ? ? ? ? */
> ? ? ? ?int (*enable)(struct mmc_host *host);
> - ? ? ? int (*disable)(struct mmc_host *host, int lazy);
> + ? ? ? int (*disable)(struct mmc_host *host);
> ? ? ? ?/*
> ? ? ? ? * It is optional for the host to implement pre_req and post_req in
> ? ? ? ? * order to support double buffering of requests (prepare one
> @@ -218,7 +195,7 @@ struct mmc_host {
> ?#define MMC_CAP_SPI ? ? ? ? ? ?(1 << 4) ? ? ? ?/* Talks only SPI protocols */
> ?#define MMC_CAP_NEEDS_POLL ? ? (1 << 5) ? ? ? ?/* Needs polling for card-detection */
> ?#define MMC_CAP_8_BIT_DATA ? ? (1 << 6) ? ? ? ?/* Can the host do 8 bit transfers */
> -#define MMC_CAP_DISABLE ? ? ? ? ? ? ? ?(1 << 7) ? ? ? ?/* Can the host be disabled */
> +
> ?#define MMC_CAP_NONREMOVABLE ? (1 << 8) ? ? ? ?/* Nonremovable e.g. eMMC */
> ?#define MMC_CAP_WAIT_WHILE_BUSY ? ? ? ?(1 << 9) ? ? ? ?/* Waits while card is busy */
> ?#define MMC_CAP_ERASE ? ? ? ? ?(1 << 10) ? ? ? /* Allow erase/trim commands */
> @@ -301,13 +278,7 @@ struct mmc_host {
> ? ? ? ?unsigned int ? ? ? ? ? ?removed:1; ? ? ?/* host is being removed */
> ?#endif
>
> - ? ? ? /* Only used with MMC_CAP_DISABLE */
> - ? ? ? int ? ? ? ? ? ? ? ? ? ? enabled; ? ? ? ?/* host is enabled */
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? rescan_disable; /* disable card detection */
> - ? ? ? int ? ? ? ? ? ? ? ? ? ? nesting_cnt; ? ?/* "enable" nesting count */
> - ? ? ? int ? ? ? ? ? ? ? ? ? ? en_dis_recurs; ?/* detect recursion */
> - ? ? ? unsigned int ? ? ? ? ? ?disable_delay; ?/* disable delay in msecs */
> - ? ? ? struct delayed_work ? ? disable; ? ? ? ?/* disabling work */
>
> ? ? ? ?struct mmc_card ? ? ? ? *card; ? ? ? ? ?/* device attached to this host */
>
> @@ -407,17 +378,8 @@ int mmc_card_awake(struct mmc_host *host);
> ?int mmc_card_sleep(struct mmc_host *host);
> ?int mmc_card_can_sleep(struct mmc_host *host);
>
> -int mmc_host_enable(struct mmc_host *host);
> -int mmc_host_disable(struct mmc_host *host);
> -int mmc_host_lazy_disable(struct mmc_host *host);
> ?int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *);
>
> -static inline void mmc_set_disable_delay(struct mmc_host *host,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned int disable_delay)
> -{
> - ? ? ? host->disable_delay = disable_delay;
> -}
> -
> ?/* Module parameter */
> ?extern bool mmc_assume_removable;
>
> --
> 1.7.6.4
>


From bill4carson at gmail.com  Thu Mar  1 07:42:37 2012
From: bill4carson at gmail.com (carson bill)
Date: Thu, 1 Mar 2012 20:42:37 +0800
Subject: [PATCH 7/7] Minor compiling fix
In-Reply-To: <201203011140.44364.arnd@arndb.de>
References: <1329126268-11032-1-git-send-email-bill4carson@gmail.com>
 <201202291235.04113.arnd@arndb.de> <4F4F36DD.3020005@gmail.com>
 <201203011140.44364.arnd@arndb.de>
Message-ID: <CAOMgcGK4h1CtyF=F5_u17NmF54Rvvj31P-=LXhpKeM4JqmuC1A@mail.gmail.com>

2012/3/1 Arnd Bergmann <arnd at arndb.de>
>
> On Thursday 01 March 2012, bill4carson wrote:
> > On 2012?02?29? 20:35, Arnd Bergmann wrote:
> > > On Monday 13 February 2012, Bill Carson wrote:
> > >> --- a/arch/arm/mm/dma-mapping.c
> > >> +++ b/arch/arm/mm/dma-mapping.c
> > >> @@ -152,9 +152,6 @@ static struct arm_vmregion_head consistent_head = {
> > >>          .vm_end         = CONSISTENT_END,
> > >>   };
> > >>
> > >> -#ifdef CONFIG_HUGETLB_PAGE
> > >> -#error ARM Coherent DMA allocator does not (yet) support huge TLB
> > >> -#endif
> > >
> > > This one needs an explanation, too. What has changed that now allows
> > > dma_alloc_coherent to work with CONFIG_HUGETLB_PAGE set that did not
> > > work before?
> > >
> >
> > AFAIK, __dma_alloc has the finest granularity at 4k page size even when
> > user requests 1M bytes memory.
> >
> > but current hugetlb low level set_hugepte_at *ONLY*/*MUST* support 2M
> > page mapping, so it can't be used to create huge dma mapping in a more
> > general way.
> >
> > comments this error out doesn't mean that it could support huge page dma
> > mapping now with this patch, just shut up gcc when compiling.
> >
> > Adding a single low level hook to create 1M page mapping can satisfy
> > the needs, but apparently that's out of hugetlb scope.
> > And it's on my TODO list :)
>
> Hmm, I'm still not sure I'm following. The coherent DMA area is currently
> limited to 2MB or a small multiple of that, so you would not be able
> to allocate coherent hugepages anyway.
>
>
> Further, I don't think there are any device drivers that call
> dma_alloc_coherent and expect to map the resulting page into
> user space, or that we even have an interface for that.
>

This "ifdef" is used to remind dma implementation should use hugetlb low
API to set up huge page mappings one day hugetlb is supported, just it!

For now, I don't see any direct relationship dma alloc has to do with hugetlb
in a more general way other than both could share low level page table
management.


> This entire chunk of code is also getting changed with the addition of CMA.
>
>        Arnd


From haojian.zhuang at gmail.com  Thu Mar  1 07:52:56 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Thu, 1 Mar 2012 20:52:56 +0800
Subject: [PATCH 3/8] rtc: sa1100: add OF support
In-Reply-To: <201203010951.12405.arnd@arndb.de>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
 <1330582228-12424-4-git-send-email-haojian.zhuang@marvell.com>
 <201203010951.12405.arnd@arndb.de>
Message-ID: <CAN1soZwe+NRaf--SKupqtTnJ=YExT9LYBx+R9jUV3aA0ecbkbg@mail.gmail.com>

On Thu, Mar 1, 2012 at 5:51 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Thursday 01 March 2012, Haojian Zhuang wrote:
>> +#ifdef CONFIG_OF
>> +static int sa1100_rtc_probe_dt(struct platform_device *pdev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct sa1100_rtc *info)
>> +{
>> + ? ? ? info->irq_alarm = platform_get_irq(pdev, 0);
>> + ? ? ? info->irq_1hz = platform_get_irq(pdev, 1);
>> + ? ? ? if (info->irq_1hz < 0 || info->irq_alarm < 0)
>> + ? ? ? ? ? ? ? return -ENODEV;
>> + ? ? ? return 0;
>> +}
>> +#else
>> +static int sa1100_rtc_probe_dt(struct platform_device *pdev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct sa1100_rtc *info)
>> +{
>> + ? ? ? return 1;
>> +}
>> +#endif
>> +
>> +static int sa1100_rtc_probe_irq(struct platform_device *pdev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct sa1100_rtc *info)
>> +{
>> + ? ? ? info->irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz");
>> + ? ? ? info->irq_alarm = platform_get_irq_byname(pdev, "rtc alarm");
>> + ? ? ? if (info->irq_1hz < 0 || info->irq_alarm < 0)
>> + ? ? ? ? ? ? ? return -ENODEV;
>> + ? ? ? return 0;
>> +}
>
> This should not be necessary. I thought we had already added support
> for named irq resources coming from the device tree. If not, why not
> just make the other ones anonymous as well and just use platform_get_irq()?
>

Yes, platform_get_irq() is better. I'll append the two irqs into
interrupts property.


From haojian.zhuang at gmail.com  Thu Mar  1 07:55:13 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Thu, 1 Mar 2012 20:55:13 +0800
Subject: [PATCH 2/8] serial: pxa: add OF support
In-Reply-To: <20120301094853.GA7363@n2100.arm.linux.org.uk>
References: <1330582228-12424-1-git-send-email-haojian.zhuang@marvell.com>
 <1330582228-12424-3-git-send-email-haojian.zhuang@marvell.com>
 <201203010947.39601.arnd@arndb.de>
 <20120301094853.GA7363@n2100.arm.linux.org.uk>
Message-ID: <CAN1soZyDaKV62dweNdtSiyFNnUOh0u5_LZL8UxBMOdz6SxRryA@mail.gmail.com>

On Thu, Mar 1, 2012 at 5:48 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Thu, Mar 01, 2012 at 09:47:39AM +0000, Arnd Bergmann wrote:
>> On Thursday 01 March 2012, Haojian Zhuang wrote:
>> > @@ -792,7 +826,7 @@ static int serial_pxa_probe(struct platform_device *dev)
>> > ? ? ? ? if (!mmres || !irqres)
>> > ? ? ? ? ? ? ? ? return -ENODEV;
>> >
>> > - ? ? ? sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
>> > + ? ? ? sport = kzalloc(sizeof(struct uart_pxa_port) + 8, GFP_KERNEL);
>> > ? ? ? ? if (!sport)
>> > ? ? ? ? ? ? ? ? return -ENOMEM;
>> >
>> > @@ -808,20 +842,18 @@ static int serial_pxa_probe(struct platform_device *dev)
>> > + ? ? ? ret = serial_pxa_probe_dt(dev, sport);
>> > + ? ? ? if (ret > 0)
>> > + ? ? ? ? ? ? ? sport->port.line = dev->id;
>> > + ? ? ? else if (ret < 0)
>> > + ? ? ? ? ? ? ? goto err_clk;
>> > + ? ? ? sport->name = (char *)((unsigned int)sport + 8);
>> > + ? ? ? /* name can't exceed 8 bytes */
>> > + ? ? ? sprintf(sport->name, "UART%d", sport->port.line + 1);
>>
>> The pointer arithmetic looks wrong to me, both technically and morally ;-)
>>
>> Since struct uart_pxa_port is a local data structure, why don't you just
>> turn the name field into a fixed-length array?
>
> and then use snprintf() to ensure that it doesn't overflow.

OK. I'll use local data structure and snprintf() instead.


From linux at arm.linux.org.uk  Thu Mar  1 08:00:51 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 13:00:51 +0000
Subject: [RFC PATCH 0/2] ARM: assembler: Add uniform assembler framework
In-Reply-To: <20120301114942.GA2040@linaro.org>
References: <1330455586-10353-1-git-send-email-dave.martin@linaro.org>
 <20120228192458.GC3617@n2100.arm.linux.org.uk>
 <20120301114942.GA2040@linaro.org>
Message-ID: <20120301130051.GE7363@n2100.arm.linux.org.uk>

On Thu, Mar 01, 2012 at 11:49:42AM +0000, Dave Martin wrote:
> Are you still interested in this series?
> 
> I have a workaround for the above now, but it's not pretty -- I seem to
> have opened a can of worms here.
> 
> 
> We would need something like
> 
> #define EXTENDED_ASM(stuff) asm ( ".include \"macros.inc\"\n\t" stuff )
> #define EXTENDED_VASM(stuff) asm volatile ( ".include \"macros.inc\"\n\t" stuff )
> 
> ...where macros.inc includes some logic to protect against multiple
> inclusion.
> 
> This would avoid problems caused by reordering done by the compiler.
> 
> I think this can work, but it may be a step too far...

I'm fairly tempted to say: "if it ain't broke, don't fix".  AFAIK no one
has reported problems here, so lets not hastily try to fix something that
will error out if it does go wrong.


From jason at lakedaemon.net  Thu Mar  1 07:20:00 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 1 Mar 2012 07:20:00 -0500
Subject: [PATCH 2/3 v4] arm: kirkwood: add dreamplug (fdt) support.
In-Reply-To: <20120229235326.GA3207@lunn.ch>
References: <20120224075753.GA24858@lunn.ch>
 <20120229144450.GB23524@titan.lakedaemon.net>
 <20120229235326.GA3207@lunn.ch>
Message-ID: <20120301122000.GA6276@titan.lakedaemon.net>

On Thu, Mar 01, 2012 at 12:53:26AM +0100, Andrew Lunn wrote:
> On Wed, Feb 29, 2012 at 09:44:50AM -0500, Jason wrote:
> > On Fri, Feb 24, 2012 at 08:57:53AM +0100, Andrew Lunn wrote:
> > > I have some patches under development which will help.
> > 
> > Any chance you could shoot those to me?  (on-list preferable)  I'm
> > thinking we could convert it to an interim solution eg
> > kirkwood_{get,put}_clock() that would be easy to migrate to generic
> > CLK/clkdev once it lands.
> 
> It is not that easy. It is not kirkwood, but all platform orion, so
> includes dove, orion5x, mv78xx0 and kirkwood. All these share the same
> device drivers, since they all share the same SoC peripheral
> cores. However, only kirkwood has per peripheral gated clocks and all
> the others share tclk.
> 
> I've also broke orion5x twice so far with my patches, since i don't
> have any hardware with that SoC. So this time i was hoping to ask for
> testing on orion5x before submitting to mainline.
> 
> Mike did say he hoped the generic clk would be ready last week. Maybe
> we should ping him and ask for a new ETA?

Nah, it'll be ready when it's ready.  I'll keep things the way they are
and gut through the conversion once his stuff is in mainline.

thx,

Jason.


From nicolas.ferre at atmel.com  Thu Mar  1 08:19:29 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 01 Mar 2012 14:19:29 +0100
Subject: [GIT PULL] at91: irqdomain and device tree for AIC and GPIO
In-Reply-To: <4F4B8FCF.2050702@atmel.com>
References: <4F4B8FCF.2050702@atmel.com>
Message-ID: <4F4F7761.2040607@atmel.com>

On 02/27/2012 03:14 PM, Nicolas Ferre :
> Hi,

Hi,

Hold on with this pull request:
- I can now base the similar one on top of the "cleanup2" branch
- the irqdomain/next is now considered stable so I can
  merge it beforehand
- I can add some more material to it (still related to 
  AT91 the Device Tree conversion)

Thanks, best regards,

> This series adds irqdomain and device tree support for both the
> interrupt and GPIO controllers of AT91 SoC. It has been discussed a lot
> and I think that I have addressed all comments and advices.
> 
> This irqdomain work takes advantage of Grant's patch series that is present
> in:
> git://git.secretlab.ca/git/linux-2.6 irqdomain/next
> And it will not compile without it. So, the inclusion of such work is needed
> before we can apply this series on mainline.
> 
> On the other hand, I have not included Grant's branch in mine on purpose: All
> this simply goes on top of current AT91 material that is already in arm-soc
> (merge of all at91/* branches). You can find it in the AT91 git tree with
> at91-3.4-base2 branch name). I have made merge tests and all seems to integrate
> without conflicts.
> 
> 
> The following changes since commit 11a25ea7e4f870a37093258f577e11cec703e37e:
> 
>   Merge remote-tracking branch 'armsoc/at91/9x5' into at91-3.4-base2 (2012-02-11 14:33:03 +0100)
> 
> are available in the git repository at:
> 
> 
>   git://github.com/at91linux/linux-at91.git at91-3.4-base2+aic_gpio
> 
> for you to fetch changes up to 29751864cc12425fe2b3a75658baea9ebe54609e:
> 
>   ARM: at91: AIC and GPIO IRQ device tree initialization (2012-02-27 14:38:08 +0100)
> 
> ----------------------------------------------------------------
> Nicolas Ferre (10):
>       ARM: at91/aic: add irq domain and device tree support
>       ARM: at91/snapper9260: move gpio_to_irq out of structure initialization
>       ARM/USB: at91/ohci-at91: remove the use of irq_to_gpio
>       ARM: at91/gpio: change comments and one variable name
>       ARM: at91/gpio: add irqdomain and DT support
>       ARM: at91/gpio: non-DT builds do not have gpio_chip.of_node field
>       ARM: at91/gpio: add .to_irq gpio_chip handler
>       ARM: at91/gpio: remove the static specification of gpio_chip.base
>       ARM: at91/board-dt: remove AIC irq domain from board file
>       ARM: at91: AIC and GPIO IRQ device tree initialization
> 
>  .../devicetree/bindings/arm/atmel-aic.txt          |   38 ++
>  .../devicetree/bindings/gpio/gpio_atmel.txt        |   20 +
>  arch/arm/Kconfig                                   |    1 +
>  arch/arm/boot/dts/at91sam9g20.dtsi                 |   48 ++-
>  arch/arm/boot/dts/at91sam9g45.dtsi                 |   66 +++-
>  arch/arm/boot/dts/at91sam9x5.dtsi                  |    4 +
>  arch/arm/mach-at91/board-dt.c                      |   13 +-
>  arch/arm/mach-at91/board-snapper9260.c             |   10 +-
>  arch/arm/mach-at91/generic.h                       |    6 +
>  arch/arm/mach-at91/gpio.c                          |  363 ++++++++++++++++----
>  arch/arm/mach-at91/include/mach/gpio.h             |   12 -
>  arch/arm/mach-at91/irq.c                           |  132 ++++++--
>  drivers/usb/host/ohci-at91.c                       |    5 +-
>  13 files changed, 581 insertions(+), 137 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/atmel-aic.txt
>  create mode 100644 Documentation/devicetree/bindings/gpio/gpio_atmel.txt
> 
> Thanks a lot, best regards,


-- 
Nicolas Ferre


From dave.martin at linaro.org  Thu Mar  1 08:20:41 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 1 Mar 2012 13:20:41 +0000
Subject: [RFC PATCH 0/2] ARM: assembler: Add uniform assembler framework
In-Reply-To: <20120301130051.GE7363@n2100.arm.linux.org.uk>
References: <1330455586-10353-1-git-send-email-dave.martin@linaro.org>
 <20120228192458.GC3617@n2100.arm.linux.org.uk>
 <20120301114942.GA2040@linaro.org>
 <20120301130051.GE7363@n2100.arm.linux.org.uk>
Message-ID: <20120301132041.GB2040@linaro.org>

On Thu, Mar 01, 2012 at 01:00:51PM +0000, Russell King - ARM Linux wrote:
> On Thu, Mar 01, 2012 at 11:49:42AM +0000, Dave Martin wrote:
> > Are you still interested in this series?
> > 
> > I have a workaround for the above now, but it's not pretty -- I seem to
> > have opened a can of worms here.
> > 
> > 
> > We would need something like
> > 
> > #define EXTENDED_ASM(stuff) asm ( ".include \"macros.inc\"\n\t" stuff )
> > #define EXTENDED_VASM(stuff) asm volatile ( ".include \"macros.inc\"\n\t" stuff )
> > 
> > ...where macros.inc includes some logic to protect against multiple
> > inclusion.
> > 
> > This would avoid problems caused by reordering done by the compiler.
> > 
> > I think this can work, but it may be a step too far...
> 
> I'm fairly tempted to say: "if it ain't broke, don't fix".  AFAIK no one
> has reported problems here, so lets not hastily try to fix something that
> will error out if it does go wrong.

OK -- I'll shelve this series for now and we'll see if we can come up
with something more localised for the kvm/Xen case.

unified.h may work for now, but I don't want to add anything more along
those lines for unless it's definitely correct to do so...

Cheers
---Dave


From rubini at gnudd.com  Thu Mar  1 08:28:57 2012
From: rubini at gnudd.com (Alessandro Rubini)
Date: Thu, 1 Mar 2012 14:28:57 +0100
Subject: [PATCH 3/4] amba: use the new linux/sizes.h
In-Reply-To: <cover.1330607068.git.rubini@gnudd.com>
References: <cover.1330607068.git.rubini@gnudd.com>
Message-ID: <77a3185dda7be993be3538c9e5cc59e6d95f14aa.1330607068.git.rubini@gnudd.com>

Signed-off-by: Alessandro Rubini <rubini at gnudd.com>
Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi at st.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Alan Cox <alan at linux.intel.com>
---
 drivers/amba/bus.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 01c2cf4..d7fe84a 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -18,7 +18,7 @@
 #include <linux/amba/bus.h>
 
 #include <asm/irq.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #define to_amba_driver(d)	container_of(d, struct amba_driver, drv)
 
-- 
1.7.7.2


From rubini at gnudd.com  Thu Mar  1 08:28:46 2012
From: rubini at gnudd.com (Alessandro Rubini)
Date: Thu, 1 Mar 2012 14:28:46 +0100
Subject: [PATCH 2/4] sizes.h: move from asm-generic to <linux/sizes.h>
In-Reply-To: <cover.1330607068.git.rubini@gnudd.com>
References: <cover.1330607068.git.rubini@gnudd.com>
Message-ID: <7bbc4b3dc5a9fadfe7d8ce3f9846b03ada68424e.1330607068.git.rubini@gnudd.com>

sizes.h is used throughout the AMBA code and drivers, so the header
should be available to everyone in order to driver AMBA/PrimeCell
peripherals behind a PCI bridge where the host can be any platform
(I'm doing it under x86).

At this step <asm-generic/sizes.h> includes <linux/sizes.h>,
to allow a grace period for both in-tree and out-of-tree drivers.

Signed-off-by: Alessandro Rubini <rubini at gnudd.com>
Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi at st.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Alan Cox <alan at linux.intel.com>
---
 include/asm-generic/sizes.h |   49 +-----------------------------------------
 include/linux/sizes.h       |   47 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+), 47 deletions(-)
 create mode 100644 include/linux/sizes.h

diff --git a/include/asm-generic/sizes.h b/include/asm-generic/sizes.h
index ea5d4ef..1dcfad9 100644
--- a/include/asm-generic/sizes.h
+++ b/include/asm-generic/sizes.h
@@ -1,47 +1,2 @@
-/*
- * linux/include/asm-generic/sizes.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_GENERIC_SIZES_H__
-#define __ASM_GENERIC_SIZES_H__
-
-#define SZ_1				0x00000001
-#define SZ_2				0x00000002
-#define SZ_4				0x00000004
-#define SZ_8				0x00000008
-#define SZ_16				0x00000010
-#define SZ_32				0x00000020
-#define SZ_64				0x00000040
-#define SZ_128				0x00000080
-#define SZ_256				0x00000100
-#define SZ_512				0x00000200
-
-#define SZ_1K				0x00000400
-#define SZ_2K				0x00000800
-#define SZ_4K				0x00001000
-#define SZ_8K				0x00002000
-#define SZ_16K				0x00004000
-#define SZ_32K				0x00008000
-#define SZ_64K				0x00010000
-#define SZ_128K				0x00020000
-#define SZ_256K				0x00040000
-#define SZ_512K				0x00080000
-
-#define SZ_1M				0x00100000
-#define SZ_2M				0x00200000
-#define SZ_4M				0x00400000
-#define SZ_8M				0x00800000
-#define SZ_16M				0x01000000
-#define SZ_32M				0x02000000
-#define SZ_64M				0x04000000
-#define SZ_128M				0x08000000
-#define SZ_256M				0x10000000
-#define SZ_512M				0x20000000
-
-#define SZ_1G				0x40000000
-#define SZ_2G				0x80000000
-
-#endif /* __ASM_GENERIC_SIZES_H__ */
+/* This is a placeholder, to be removed over time */
+#include <linux/sizes.h>
diff --git a/include/linux/sizes.h b/include/linux/sizes.h
new file mode 100644
index 0000000..ce3e815
--- /dev/null
+++ b/include/linux/sizes.h
@@ -0,0 +1,47 @@
+/*
+ * include/linux/sizes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_SIZES_H__
+#define __LINUX_SIZES_H__
+
+#define SZ_1				0x00000001
+#define SZ_2				0x00000002
+#define SZ_4				0x00000004
+#define SZ_8				0x00000008
+#define SZ_16				0x00000010
+#define SZ_32				0x00000020
+#define SZ_64				0x00000040
+#define SZ_128				0x00000080
+#define SZ_256				0x00000100
+#define SZ_512				0x00000200
+
+#define SZ_1K				0x00000400
+#define SZ_2K				0x00000800
+#define SZ_4K				0x00001000
+#define SZ_8K				0x00002000
+#define SZ_16K				0x00004000
+#define SZ_32K				0x00008000
+#define SZ_64K				0x00010000
+#define SZ_128K				0x00020000
+#define SZ_256K				0x00040000
+#define SZ_512K				0x00080000
+
+#define SZ_1M				0x00100000
+#define SZ_2M				0x00200000
+#define SZ_4M				0x00400000
+#define SZ_8M				0x00800000
+#define SZ_16M				0x01000000
+#define SZ_32M				0x02000000
+#define SZ_64M				0x04000000
+#define SZ_128M				0x08000000
+#define SZ_256M				0x10000000
+#define SZ_512M				0x20000000
+
+#define SZ_1G				0x40000000
+#define SZ_2G				0x80000000
+
+#endif /* __LINUX_SIZES_H__ */
-- 
1.7.7.2


From linux at arm.linux.org.uk  Thu Mar  1 08:30:12 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 13:30:12 +0000
Subject: [PATCH 1/4] x86: add NO_IRQ macro
In-Reply-To: <6bda7538144dce0bf5780df3d0601147dae753b5.1330607068.git.rubini@gnudd.com>
References: <cover.1330607068.git.rubini@gnudd.com>
 <6bda7538144dce0bf5780df3d0601147dae753b5.1330607068.git.rubini@gnudd.com>
Message-ID: <20120301133012.GF7363@n2100.arm.linux.org.uk>

On Thu, Mar 01, 2012 at 02:28:36PM +0100, Alessandro Rubini wrote:
> This is needed to compile AMBA drivers. Most architectures define
> NO_IRQ as -1, and this does the same for the PC.

No.  We're getting rid of NO_IRQ, and it will be gone from AMBA stuff
probably for 3.5.


From rubini at gnudd.com  Thu Mar  1 08:28:24 2012
From: rubini at gnudd.com (Alessandro Rubini)
Date: Thu, 1 Mar 2012 14:28:24 +0100
Subject: [PATCH 0/4] Initial steps to compile AMBA for x86
Message-ID: <cover.1330607068.git.rubini@gnudd.com>

I'm working on the sta2x11 I/O Hub, which is basically a bridge from
PCIe to AMBA.  While current code uses PCI drivers for all the
PrimeCell devices (with a lot of code duplication), I think we should
be able to compile native amba drivers. The chip has uart, spi, mmc, i2c
and dma cells, for which an AMBA driver is already in the kernel.

This patch-set is the first steps needed to build amba drivers for
x86.  I'm currently using the pl011 UART as a testbed, and it's up on
my system (with other not-ready-to-be-published patches).

As for sizes, there are a number of users of <asm/sizes.h>. If these
initial patches are accepted, I'll take care to convert other stuff,
add a #warning to asm/sizes.h and remove it after a pair of releases.

The patches have been build-tested under ARM with versatile_defconfig,
at91sam9263_defconfig, vexpress_defconfig and realview-smp_defconfig
-- as well as sta2x11 on x86.

Alessandro Rubini (4):
  x86: add NO_IRQ macro
  sizes.h: move from asm-generic to <linux/sizes.h>
  amba: use the new linux/sizes.h
  ARM: use the new linux/sizes.h

 arch/arm/include/asm/memory.h |    2 +-
 arch/arm/mm/dma-mapping.c     |    2 +-
 arch/arm/mm/init.c            |    2 +-
 arch/arm/mm/ioremap.c         |    2 +-
 arch/arm/mm/mmu.c             |    2 +-
 arch/x86/include/asm/irq.h    |    2 +
 drivers/amba/bus.c            |    2 +-
 include/asm-generic/sizes.h   |   49 +---------------------------------------
 include/linux/sizes.h         |   47 +++++++++++++++++++++++++++++++++++++++
 9 files changed, 57 insertions(+), 53 deletions(-)
 create mode 100644 include/linux/sizes.h

-- 
1.7.7.2


From rubini at gnudd.com  Thu Mar  1 08:28:36 2012
From: rubini at gnudd.com (Alessandro Rubini)
Date: Thu, 1 Mar 2012 14:28:36 +0100
Subject: [PATCH 1/4] x86: add NO_IRQ macro
In-Reply-To: <cover.1330607068.git.rubini@gnudd.com>
References: <cover.1330607068.git.rubini@gnudd.com>
Message-ID: <6bda7538144dce0bf5780df3d0601147dae753b5.1330607068.git.rubini@gnudd.com>

This is needed to compile AMBA drivers. Most architectures define
NO_IRQ as -1, and this does the same for the PC.

Signed-off-by: Alessandro Rubini <rubini at gnudd.com>
Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi at st.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Alan Cox <alan at linux.intel.com>
---
 arch/x86/include/asm/irq.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index ba870bb..c9072f5 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -10,6 +10,8 @@
 #include <asm/apicdef.h>
 #include <asm/irq_vectors.h>
 
+#define NO_IRQ	(-1)
+
 static inline int irq_canonicalize(int irq)
 {
 	return ((irq == 2) ? 9 : irq);
-- 
1.7.7.2


From rubini at gnudd.com  Thu Mar  1 08:29:08 2012
From: rubini at gnudd.com (Alessandro Rubini)
Date: Thu, 1 Mar 2012 14:29:08 +0100
Subject: [PATCH 4/4] ARM: use the new linux/sizes.h
In-Reply-To: <cover.1330607068.git.rubini@gnudd.com>
References: <cover.1330607068.git.rubini@gnudd.com>
Message-ID: <2ec6cf32ff4e5dbdf7fa6ad58bac5dc959d0c875.1330607068.git.rubini@gnudd.com>

Signed-off-by: Alessandro Rubini <rubini at gnudd.com>
Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi at st.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Alan Cox <alan at linux.intel.com>
---
 arch/arm/include/asm/memory.h |    2 +-
 arch/arm/mm/dma-mapping.c     |    2 +-
 arch/arm/mm/init.c            |    2 +-
 arch/arm/mm/ioremap.c         |    2 +-
 arch/arm/mm/mmu.c             |    2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index a8997d7..5848eba 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -16,7 +16,7 @@
 #include <linux/compiler.h>
 #include <linux/const.h>
 #include <linux/types.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #ifdef CONFIG_NEED_MACH_MEMORY_H
 #include <mach/memory.h>
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index db23ae4..364defd 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -19,12 +19,12 @@
 #include <linux/dma-mapping.h>
 #include <linux/highmem.h>
 #include <linux/slab.h>
+#include <linux/sizes.h>
 
 #include <asm/memory.h>
 #include <asm/highmem.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
-#include <asm/sizes.h>
 #include <asm/mach/arch.h>
 
 #include "mm.h"
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 595079f..288b77d 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -20,13 +20,13 @@
 #include <linux/highmem.h>
 #include <linux/gfp.h>
 #include <linux/memblock.h>
+#include <linux/sizes.h>
 
 #include <asm/mach-types.h>
 #include <asm/memblock.h>
 #include <asm/prom.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
-#include <asm/sizes.h>
 #include <asm/tlb.h>
 #include <asm/fixmap.h>
 
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 66daf17..1d24bef 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -25,6 +25,7 @@
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
 #include <linux/io.h>
+#include <linux/sizes.h>
 
 #include <asm/cp15.h>
 #include <asm/cputype.h>
@@ -32,7 +33,6 @@
 #include <asm/mmu_context.h>
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
-#include <asm/sizes.h>
 
 #include <asm/mach/map.h>
 #include "mm.h"
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index f77f1db..f3ee2b8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -16,13 +16,13 @@
 #include <linux/memblock.h>
 #include <linux/fs.h>
 #include <linux/vmalloc.h>
+#include <linux/sizes.h>
 
 #include <asm/cp15.h>
 #include <asm/cputype.h>
 #include <asm/sections.h>
 #include <asm/cachetype.h>
 #include <asm/setup.h>
-#include <asm/sizes.h>
 #include <asm/smp_plat.h>
 #include <asm/tlb.h>
 #include <asm/highmem.h>
-- 
1.7.7.2


From rnayak at ti.com  Thu Mar  1 08:47:54 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 1 Mar 2012 19:17:54 +0530
Subject: [PATCH] ARM: OMAP: hwmod: Use sysc_fields->srst_shift and get rid of
 hardcoded SYSC_TYPE2_SOFTRESET_MASK
Message-ID: <1330609674-20826-1-git-send-email-rnayak@ti.com>

This is useful when we have broken type2 compliant IPs' where
the softreset shift is not the same as SYSC_TYPE2_SOFTRESET_SHIFT
and hence is overridden using sysc_fields->srst_shift.

We have atleast one such instance now with onchip keypad on OMAP5
which has a different softreset shift as compared to other type2
IPs'.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Balaji TK  <balajitk at ti.com>
Tested-by: Sourav Poddar <sourav.poddar at ti.com>
---
Paul,

I based the patch on top of your reset/data cleanup series
for hwmod. So its based on 'hwmod_data_cleanup_3.4' branch.

regards,
Rajendra

 arch/arm/mach-omap2/omap_hwmod.c |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 3462dc5..6aadba2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1524,7 +1524,7 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
  */
 static int _ocp_softreset(struct omap_hwmod *oh)
 {
-	u32 v;
+	u32 v, softrst_mask;
 	int c = 0;
 	int ret = 0;
 
@@ -1559,11 +1559,13 @@ static int _ocp_softreset(struct omap_hwmod *oh)
 						    oh->class->sysc->syss_offs)
 				   & SYSS_RESETDONE_MASK),
 				  MAX_MODULE_SOFTRESET_WAIT, c);
-	else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS)
+	else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) {
+		softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
 		omap_test_timeout(!(omap_hwmod_read(oh,
 						     oh->class->sysc->sysc_offs)
-				   & SYSC_TYPE2_SOFTRESET_MASK),
+				   & softrst_mask),
 				  MAX_MODULE_SOFTRESET_WAIT, c);
+	}
 
 	if (c == MAX_MODULE_SOFTRESET_WAIT)
 		pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
-- 
1.7.1



From dron0gus at gmail.com  Thu Mar  1 08:53:51 2012
From: dron0gus at gmail.com (Gusakov Andrey)
Date: Thu,  1 Mar 2012 17:53:51 +0400
Subject: [PATCH v3] ARM: S3C24XX DMA resume regression fix
In-Reply-To: <077201ccf767c6d1ec05475c40$%kim@samsung.com>
References: <077201ccf767c6d1ec05475c40$%kim@samsung.com>
Message-ID: <1330610031-2237-1-git-send-email-dron0gus@gmail.com>

s3c2410_dma_suspend suspends channels from 0 to dma_channels.
s3c2410_dma_resume resumes channels in reverse order. So
pointer should be decremented instead of being incremented.

Signed-off-by: Gusakov Andrey <dron0gus at gmail.com>
Reviewed-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/plat-s3c24xx/dma.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 57abec9..16510d5 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1249,7 +1249,7 @@ static void s3c2410_dma_resume(void)
 	struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1;
 	int channel;
 
-	for (channel = dma_channels - 1; channel >= 0; cp++, channel--)
+	for (channel = dma_channels - 1; channel >= 0; cp--, channel--)
 		s3c2410_dma_resume_chan(cp);
 }
 
-- 
1.7.0.4



From arnd at arndb.de  Thu Mar  1 08:55:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 13:55:56 +0000
Subject: [PATCH 2/4] sizes.h: move from asm-generic to <linux/sizes.h>
In-Reply-To: <7bbc4b3dc5a9fadfe7d8ce3f9846b03ada68424e.1330607068.git.rubini@gnudd.com>
References: <cover.1330607068.git.rubini@gnudd.com>
 <7bbc4b3dc5a9fadfe7d8ce3f9846b03ada68424e.1330607068.git.rubini@gnudd.com>
Message-ID: <201203011355.57356.arnd@arndb.de>

On Thursday 01 March 2012, Alessandro Rubini wrote:
> sizes.h is used throughout the AMBA code and drivers, so the header
> should be available to everyone in order to driver AMBA/PrimeCell
> peripherals behind a PCI bridge where the host can be any platform
> (I'm doing it under x86).
> 
> At this step <asm-generic/sizes.h> includes <linux/sizes.h>,
> to allow a grace period for both in-tree and out-of-tree drivers.
> 
> Signed-off-by: Alessandro Rubini <rubini at gnudd.com>
> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi at st.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Alan Cox <alan at linux.intel.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>

For the asm-generic part of this.


From arnd at arndb.de  Thu Mar  1 08:52:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 13:52:35 +0000
Subject: [PATCH v2 19/28] ARM: Add fixed PCI i/o mapping
In-Reply-To: <20120229232154.GG16999@n2100.arm.linux.org.uk>
References: <1330547147-22867-1-git-send-email-robherring2@gmail.com>
 <201202292243.13923.arnd@arndb.de>
 <20120229232154.GG16999@n2100.arm.linux.org.uk>
Message-ID: <201203011352.36067.arnd@arndb.de>

On Wednesday 29 February 2012, Russell King - ARM Linux wrote:
> On Wed, Feb 29, 2012 at 10:43:13PM +0000, Arnd Bergmann wrote:
> > On Wednesday 29 February 2012, Rob Herring wrote:
> > > No, then the mapping will fail. I do need to double check all the
> > > mappings and make sure there is no overlap but we only care on the PCI
> > > platforms I converted.
> > > 
> > > Also, it should be noted this shrinks the i/o space on some platforms.
> > > dove and kirkwood had 1MB x 2 buses and now have 64KB per bus. ixp2000 I
> > > think has 32MB with a note saying they need "a lot". Is there really a
> > > use for lots of i/o space?
> > 
> > Given that each PCI bus only wires up the lower 64k, I'd say no ;-)
> 
> That's incorrect.  There's no "wires up" option there.  Addresses and
> data are transferred over a common set of 32 wires on 32-bit PCI, and
> the bus has separate 'address' and 'data' phases.  If you only wire up
> 16 of those lines, then things aren't going to work (because you won't
> be able to access bytes 2,3 of each word.)
> 
> However, there's a separate issue here:
> (1) do peripherals decode the upper 16 bits programmed into their IO BARs?
>     Some do.
> (2) are host PCI controllers capable of generating IO accesses in the
>     lower 64k bus address region?

Very interesting, I had no idea and when I looked up the PCI spec, I
found this PCI-3.0, section 6.2.5.1:

"The upper 16 bits of the I/O Base Address register may be hardwired to
 zero for devices intended for 16-bit I/O systems, such as PC compatibles.
 However, a full 32-bit decode of I/O addresses must still be done."

So it is indeed valid to have a larger I/O space, although in practice
I would expect this not to get used because in an x86 PC it is impossible
to issue an instruction that accesses an I/O port beyond 0xffff.

> I think while I was fiddling with an IOP platform years ago that it did
> not work with PCI setup to only use the lower 64k bus address region
> for IO accesses.  So I'd suggest a certain amount of care is required
> here.

Ok. I've looked up the manual for IOP134x and it's very clear there that
it has only two 64k I/O windows but no more (developer manual, sections
2.2.2.1 and 3.3.2.1). Limiting the virtual space to 64k would result in
seeing only one of the buses, but 1 MB is enough if we map both buses
in there.

Similarly, the IOP333 defines one outbound I/O space window of a fixed
length of 64kb (processor developer's manual section 3.10.33) and won't
need more than that.

Any idea which IOP you might have seen this on?

> > My guess is that they used 1MB ranges in order to benefit from section
> > mapping. In case of ixp2000, I only see 64k in the resource:
> > 
> > static struct resource ixp2000_pci_io_space = {
> >         .start  = 0x00010000,
> >         .end    = 0x0001ffff,
> >         .flags  = IORESOURCE_IO,
> >         .name   = "PCI I/O Space"
> > };
> > 
> > The part that I don't understand here is why the resource starts at
> > 64k and is another 64k in size. I think we need to double-check this
> > in order to be sure whether we have to put the pci io space into the
> > first or the second 64k chunk of the new mapping area.
> > 
> > Hmm, I guess you meant ixp23xx, not ixp2000, which indeed has
> > 
> > static struct resource ixp23xx_pci_io_space = {
> >         .start  = 0x00000100,
> >         .end    = 0x01ffffff,
> >         .flags  = IORESOURCE_IO,
> >         .name   = "PCI I/O Space"
> > };
> > 
> > This seems to be done just for simplicity in the implementation,
> > to keep all parts of the PCI controller 32MB aligned, I can't
> > see any real technical reason why it would be useful othewise.
> 
> It's certainly a weird way to avoid ISA addresses.  Note that these
> will control the set of bus addresses which get assigned within PCI.

Are you referring to ipx2000 or the ixp23xx here?

	Arnd


From arnd at arndb.de  Thu Mar  1 09:03:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 14:03:11 +0000
Subject: [GIT PULL] at91: fixes for DMA registration (3.3-rc)
In-Reply-To: <4F4F7254.9060306@atmel.com>
References: <4F4F49E1.4020902@atmel.com> <201203011149.42948.arnd@arndb.de>
 <4F4F7254.9060306@atmel.com>
Message-ID: <201203011403.11369.arnd@arndb.de>

On Thursday 01 March 2012, Nicolas Ferre wrote:
> As discussed on the mailing-list, we experience an out-of-sync situation
> between the DMA controller driver and the related code in AT91 devices files.
> 
> Those two patches already queued for 3.4 are correcting the problem that we found on
> the current 3.3-rc kernels. I have tested that the DMA driver is registering well
> with those fixes applied.
> 
> Can you please pull them in a "fixes" branch and send them to Linus before 3.3-final?

Hi Nicolas,

I've just sent a pull request for bug fixes yesterday, so I'll wait
until Linus has pulled that one and probably a few days before I
send another one.

I have applied it to the fixes branch now but not updated the
tag that I sent him.

	Arnd


From alan at lxorguk.ukuu.org.uk  Thu Mar  1 09:07:53 2012
From: alan at lxorguk.ukuu.org.uk (Alan Cox)
Date: Thu, 1 Mar 2012 14:07:53 +0000
Subject: [PATCH 1/4] x86: add NO_IRQ macro
In-Reply-To: <6bda7538144dce0bf5780df3d0601147dae753b5.1330607068.git.rubini@gnudd.com>
References: <cover.1330607068.git.rubini@gnudd.com>
 <6bda7538144dce0bf5780df3d0601147dae753b5.1330607068.git.rubini@gnudd.com>
Message-ID: <20120301140753.5c44e27e@pyramind.ukuu.org.uk>

On Thu, 1 Mar 2012 14:28:36 +0100
Alessandro Rubini <rubini at gnudd.com> wrote:

> This is needed to compile AMBA drivers. Most architectures define
> NO_IRQ as -1, and this does the same for the PC.

NAK

"No IRQ" is 0. There are a few platforms which incorrectly still define it
as -1 but they are broken and in fact many drivers won't work with
platforms that still incorrectly use -1. Nothing should be using a
NO_IRQ define.

Fix the users.


Alan


From nicolas.ferre at atmel.com  Thu Mar  1 09:06:31 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 01 Mar 2012 15:06:31 +0100
Subject: [GIT PULL] at91: fixes for DMA registration (3.3-rc)
In-Reply-To: <201203011403.11369.arnd@arndb.de>
References: <4F4F49E1.4020902@atmel.com> <201203011149.42948.arnd@arndb.de>
 <4F4F7254.9060306@atmel.com> <201203011403.11369.arnd@arndb.de>
Message-ID: <4F4F8267.5030408@atmel.com>

On 03/01/2012 03:03 PM, Arnd Bergmann :
> On Thursday 01 March 2012, Nicolas Ferre wrote:
>> As discussed on the mailing-list, we experience an out-of-sync situation
>> between the DMA controller driver and the related code in AT91 devices files.
>>
>> Those two patches already queued for 3.4 are correcting the problem that we found on
>> the current 3.3-rc kernels. I have tested that the DMA driver is registering well
>> with those fixes applied.
>>
>> Can you please pull them in a "fixes" branch and send them to Linus before 3.3-final?
> 
> Hi Nicolas,
> 
> I've just sent a pull request for bug fixes yesterday, so I'll wait
> until Linus has pulled that one and probably a few days before I
> send another one.

Sure.

> I have applied it to the fixes branch now but not updated the
> tag that I sent him.

Ok, thanks a lot for your quick help.

Best regards,
-- 
Nicolas Ferre


From b-cousson at ti.com  Thu Mar  1 09:08:10 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Thu, 1 Mar 2012 15:08:10 +0100
Subject: [PATCH] ARM: OMAP: hwmod: Use sysc_fields->srst_shift and get
 rid of hardcoded SYSC_TYPE2_SOFTRESET_MASK
In-Reply-To: <1330609674-20826-1-git-send-email-rnayak@ti.com>
References: <1330609674-20826-1-git-send-email-rnayak@ti.com>
Message-ID: <4F4F82CA.7040607@ti.com>

On 3/1/2012 2:47 PM, Rajendra Nayak wrote:
> This is useful when we have broken type2 compliant IPs' where
> the softreset shift is not the same as SYSC_TYPE2_SOFTRESET_SHIFT
> and hence is overridden using sysc_fields->srst_shift.
>
> We have atleast one such instance now with onchip keypad on OMAP5

Nit: space is missing.

> which has a different softreset shift as compared to other type2
> IPs'.

A broken IP again :-)

That's anyway a good fix since the srst_shift was already configurable, 
so having a hard-coded mask was wrong or at least error prone for non 
standard IP.

> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
> Cc: Paul Walmsley<paul at pwsan.com>
> Cc: Benoit Cousson<b-cousson at ti.com>
> Cc: Balaji TK<balajitk at ti.com>
> Tested-by: Sourav Poddar<sourav.poddar at ti.com>
> ---
> Paul,
>
> I based the patch on top of your reset/data cleanup series
> for hwmod. So its based on 'hwmod_data_cleanup_3.4' branch.
>
> regards,
> Rajendra
>
>   arch/arm/mach-omap2/omap_hwmod.c |    8 +++++---
>   1 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 3462dc5..6aadba2 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -1524,7 +1524,7 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
>    */
>   static int _ocp_softreset(struct omap_hwmod *oh)
>   {
> -	u32 v;
> +	u32 v, softrst_mask;
>   	int c = 0;
>   	int ret = 0;
>
> @@ -1559,11 +1559,13 @@ static int _ocp_softreset(struct omap_hwmod *oh)
>   						    oh->class->sysc->syss_offs)
>   				&  SYSS_RESETDONE_MASK),
>   				  MAX_MODULE_SOFTRESET_WAIT, c);
> -	else if (oh->class->sysc->sysc_flags&  SYSC_HAS_RESET_STATUS)
> +	else if (oh->class->sysc->sysc_flags&  SYSC_HAS_RESET_STATUS) {
> +		softrst_mask = (0x1<<  oh->class->sysc->sysc_fields->srst_shift);
>   		omap_test_timeout(!(omap_hwmod_read(oh,
>   						     oh->class->sysc->sysc_offs)
> -				&  SYSC_TYPE2_SOFTRESET_MASK),
> +				&  softrst_mask),
>   				  MAX_MODULE_SOFTRESET_WAIT, c);
> +	}
>
>   	if (c == MAX_MODULE_SOFTRESET_WAIT)
>   		pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",

Acked-by: Benoit Cousson<b-cousson at ti.com>

Thanks,
Benoit



From linux at arm.linux.org.uk  Thu Mar  1 09:08:17 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 14:08:17 +0000
Subject: [PATCH v2 19/28] ARM: Add fixed PCI i/o mapping
In-Reply-To: <201203011352.36067.arnd@arndb.de>
References: <1330547147-22867-1-git-send-email-robherring2@gmail.com>
 <201202292243.13923.arnd@arndb.de>
 <20120229232154.GG16999@n2100.arm.linux.org.uk>
 <201203011352.36067.arnd@arndb.de>
Message-ID: <20120301140817.GG7363@n2100.arm.linux.org.uk>

On Thu, Mar 01, 2012 at 01:52:35PM +0000, Arnd Bergmann wrote:
> Ok. I've looked up the manual for IOP134x and it's very clear there that
> it has only two 64k I/O windows but no more (developer manual, sections
> 2.2.2.1 and 3.3.2.1). Limiting the virtual space to 64k would result in
> seeing only one of the buses, but 1 MB is enough if we map both buses
> in there.

I think it was the 80312, and the manual does limit the window to 64k.

I did try shifting the PCI bus IO base for outbound transactions to
zero, and although the PCI BAR setup and bridge setup was correct, the
peripherals would not respond.  (That's because I've always hated the
way these buses are setup, mapping their PCI spaces at the physical
address location.)

I came to the conclusion that there was an undocumented problem which
meant that it doesn't work.


From linux at arm.linux.org.uk  Thu Mar  1 09:11:53 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 14:11:53 +0000
Subject: [PATCH 1/4] x86: add NO_IRQ macro
In-Reply-To: <20120301140753.5c44e27e@pyramind.ukuu.org.uk>
References: <cover.1330607068.git.rubini@gnudd.com>
 <6bda7538144dce0bf5780df3d0601147dae753b5.1330607068.git.rubini@gnudd.com>
 <20120301140753.5c44e27e@pyramind.ukuu.org.uk>
Message-ID: <20120301141153.GH7363@n2100.arm.linux.org.uk>

On Thu, Mar 01, 2012 at 02:07:53PM +0000, Alan Cox wrote:
> On Thu, 1 Mar 2012 14:28:36 +0100
> Alessandro Rubini <rubini at gnudd.com> wrote:
> 
> > This is needed to compile AMBA drivers. Most architectures define
> > NO_IRQ as -1, and this does the same for the PC.
> 
> NAK
> 
> "No IRQ" is 0. There are a few platforms which incorrectly still define it
> as -1 but they are broken and in fact many drivers won't work with
> platforms that still incorrectly use -1. Nothing should be using a
> NO_IRQ define.
> 
> Fix the users.

The users in this area are fixed and have been 'fixed' since December, it's
just going to take a couple of kernel cycles to get rid of it in a sane way
without causing breakage.  And yes, this has fallen squarely on my shoulders
to 'fix' because no one else is the least bit interested in the problem.

So, as I'm about the only one who has done any work towards this, you can
expect NO_IRQ to take a long time to finally go away.


From pdeschrijver at nvidia.com  Thu Mar  1 09:35:13 2012
From: pdeschrijver at nvidia.com (Peter De Schrijver)
Date: Thu, 1 Mar 2012 16:35:13 +0200
Subject: [PATCH v3 00/10] Add tegra30 support for secondary cores
In-Reply-To: <20120301114211.GP12917@tbergstrom-lnx.Nvidia.com>
References: <1328831277-21002-1-git-send-email-pdeschrijver@nvidia.com>
 <74CDBE0F657A3D45AFBB94109FB122FF178FACB954@HQMAIL01.nvidia.com>
 <20120229154229.GL12917@tbergstrom-lnx.Nvidia.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF21F3@HQMAIL01.nvidia.com>
 <20120301114211.GP12917@tbergstrom-lnx.Nvidia.com>
Message-ID: <20120301143513.GR12917@tbergstrom-lnx.Nvidia.com>

On Thu, Mar 01, 2012 at 12:42:11PM +0100, Peter De Schrijver wrote:
> On Wed, Feb 29, 2012 at 11:38:16PM +0100, Stephen Warren wrote:
> > Peter De Schrijver wrote at Wednesday, February 29, 2012 8:42 AM:
> > > On Wed, Feb 15, 2012 at 10:27:43PM +0100, Stephen Warren wrote:
> > > > Peter De Schrijver wrote at Thursday, February 09, 2012 4:48 PM:
> > > > > This patchset introduces support for secondary cores on tegra30. It also
> > > > > introduces some functions for the flowcontroller and adds basic support for
> > > > > tegra30 powerdomains.
> > > >
> > > > The code looks fine to me. I do notice the following when running
> > > > "shutdown -h now":
> > > >
> > > > [   27.762124] SMP: failed to stop secondary CPUs
> > 
> > I can't seem to reproduce this at all on next-20120229 anymore. What
> > kind of repro frequency are you seeing, and does it get fixed if you
> > update to that baseline?
> > 
> 
> I see it abount once every 3 reboots. I have a an expect script which
> automates the test. I haven't tried with next-20120229 yet.
> 
> > (I tried 20 times with shutdown, and 15 of them I reverted all the CPU
> > and cache errata in case they affected the issue at all)

Tried it with next-20120229 and it works fine here. I also noticed
next-20120229 does not have https://lkml.org/lkml/2012/1/31/444
which was part of the earlier tree I used for testing. So num_online_cpus()
recalculates the number of online CPUs everytime instead of trying to only
recalculate it when there is a change.

Cheers,

Peter.


From nicolas.ferre at atmel.com  Thu Mar  1 09:53:26 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 01 Mar 2012 15:53:26 +0100
Subject: [GIT PULL v2] at91: irqdomain and device tree for 3.4
Message-ID: <4F4F8D66.7040205@atmel.com>

Hi Arnd and Olof,

This pull request supersedes the previous:
"[GIT PULL] at91: irqdomain and device tree for AIC and GPIO"

This series adds irqdomain and device tree support for both the
interrupt and GPIO controllers of AT91 SoC. It has been discussed a lot
and I think that I have addressed all comments and advices.

To the AIC, GPIO device tree work, it also adds the the conversion of the 
PIT and TC timers, the PIO3 support and some basic LED and gpio-keys entries.

The irqdomain work takes advantage of Grant's patch series that is present
in:
git://git.secretlab.ca/git/linux-2.6 irqdomain/next
This branch is merged into this tree, on top of at91/base2+cleanup (aka cleanup2)
and before the application of new AT91 material.


The following changes since commit 89d4a1753b6632327f18d6c8e0842b366b736621:

  Merge branch 'irqdomain/next' of git://git.secretlab.ca/git/linux-2.6 (2012-03-01 13:26:51 +0100)

are available in the git repository at:


  git://github.com/at91linux/linux-at91.git at91-3.4-cleanup2+DT


for you to fetch changes up to f75622f4679479d352d2fa83e0d84c6c13cfcb5f:

  ARM: at91: at91sam9x5cm/dt: add leds support (2012-03-01 22:34:22 +0800)

----------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD (6):
      ARM: at91: pit add DT support
      ARM: at91: usb_a9g20/dt: add leds support
      ARM: at91: at91sam9m10g45ek/dt: add gpio-keys support
      ARM: at91: usb_a9g20/dt: add gpio-keys support
      ARM: at91: at91sam9x5cm/dt: add leds support

Nicolas Ferre (16):
      ARM: at91/aic: add irq domain and device tree support
      ARM: at91/snapper9260: move gpio_to_irq out of structure initialization
      ARM/USB: at91/ohci-at91: remove the use of irq_to_gpio
      ARM: at91/gpio: change comments and one variable name
      ARM: at91/gpio: add irqdomain and DT support
      ARM: at91/gpio: non-DT builds do not have gpio_chip.of_node field
      ARM: at91/gpio: add .to_irq gpio_chip handler
      ARM: at91/gpio: remove the static specification of gpio_chip.base
      ARM: at91/board-dt: remove AIC irq domain from board file
      ARM: at91: AIC and GPIO IRQ device tree initialization
      ARM: at91/pit: add traces in case of error  
      ARM: at91/tclib: take iomem size from resource
      ARM: at91/tc: add device tree support to atmel_tclib
      ARM: at91/tc/clocksource: Add 32 bit variant to Timer Counter
      ARM: at91: add sam9_smc.o to at91sam9x5 build
      ARM: at91/pio: add new PIO3 features

 .../devicetree/bindings/arm/atmel-aic.txt          |   38 ++
 .../devicetree/bindings/arm/atmel-at91.txt         |   32 +
 .../devicetree/bindings/gpio/gpio_atmel.txt        |   20 +
 arch/arm/Kconfig                                   |    1 +
 arch/arm/boot/dts/at91sam9g20.dtsi                 |   68 ++-
 arch/arm/boot/dts/at91sam9g45.dtsi                 |   87 +++-
 arch/arm/boot/dts/at91sam9m10g45ek.dts             |   72 +++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |   12 +-
 arch/arm/boot/dts/at91sam9x5cm.dtsi                |   15 +
 arch/arm/boot/dts/usb_a9g20.dts                    |   23 +
 arch/arm/mach-at91/Makefile                        |    2 +-
 arch/arm/mach-at91/at91sam9260.c                   |    7 +
 arch/arm/mach-at91/at91sam9260_devices.c           |   21 +-
 arch/arm/mach-at91/at91sam926x_time.c              |   68 ++-
 arch/arm/mach-at91/at91sam9g45.c                   |    3 +
 arch/arm/mach-at91/at91sam9g45_devices.c           |   21 +-
 arch/arm/mach-at91/at91sam9x5.c                    |    2 -
 arch/arm/mach-at91/board-dt.c                      |   14 +-
 arch/arm/mach-at91/board-snapper9260.c             |   10 +-
 arch/arm/mach-at91/generic.h                       |    6 +
 arch/arm/mach-at91/gpio.c                          |  625 +++++++++++++++++---
 arch/arm/mach-at91/include/mach/at91_pio.h         |   25 +
 arch/arm/mach-at91/include/mach/gpio.h             |   17 +-
 arch/arm/mach-at91/irq.c                           |  132 ++++-
 drivers/clocksource/tcb_clksrc.c                   |   90 ++-
 drivers/misc/atmel_tclib.c                         |   64 ++-
 drivers/usb/host/ohci-at91.c                       |    5 +-
 include/linux/atmel_tc.h                           |   10 +
 28 files changed, 1286 insertions(+), 204 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-aic.txt
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_atmel.txt

Thanks, best regards,
-- 
Nicolas Ferre


From m.szyprowski at samsung.com  Thu Mar  1 09:57:18 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Thu, 01 Mar 2012 15:57:18 +0100
Subject: [PATCH v9 1/2] ARM: EXYNOS: Change System MMU platform device
 definitions
In-Reply-To: <CAHQjnOO1aADVQWxNt-J3nb0bgJvc2dfk+6qTWKWx7w+-LUVSmw@mail.gmail.com>
References: <001901ccf5e3$6a363320$3ea29960$%cho@samsung.com>
 <CAH9JG2Uvh=_GWFWyBrE-hfGTvrwvs6n37bmKaHbCovJ++EeJ7g@mail.gmail.com>
 <CAHQjnOO1aADVQWxNt-J3nb0bgJvc2dfk+6qTWKWx7w+-LUVSmw@mail.gmail.com>
Message-ID: <011401ccf7bb$98d51c30$ca7f5490$%szyprowski@samsung.com>

Hello,

On Wednesday, February 29, 2012 1:26 AM KyongHo Cho wrote:

 
> On Tue, Feb 28, 2012 at 4:20 PM, Kyungmin Park
> <kyungmin.park at samsung.com> wrote:
> > Hi,
> >
> > On 2/28/12, KyongHo Cho <pullip.cho at samsung.com> wrote:
> >> Handling System MMUs with an identifier is not flexible to manage
> >> System MMU platform devices because of the following reasons:
> >> 1. A device driver which needs to handle System MMU must know the ID.
> >> 2. A System MMU may not present in some implementations of Exynos family.
> >> 3. Handling System MMU with IOMMU API does not require an ID.
> >>
> >> This patch is the result of removing ID of System MMUs.
> >> Instead, a device driver that needs to handle its System MMU must
> >> use IOMMU API while its descriptor of platform device is given.
> >>
> >> This patch also includes the following enhancements:
> >> - A System MMU device becomes a child if its power domain device.
> >> - clkdev
> >>
> >> Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
> >> ---
> >> ?arch/arm/mach-exynos/Kconfig ? ? ? ? ? ? ? ? ? ?| ? 11 +-
> >> ?arch/arm/mach-exynos/Makefile ? ? ? ? ? ? ? ? ? | ? ?2 +-
> >> ?arch/arm/mach-exynos/clock-exynos4.c ? ? ? ? ? ?| ? 79 ++--
> >> ?arch/arm/mach-exynos/clock-exynos4.h ? ? ? ? ? ?| ? ?2 +
> >> ?arch/arm/mach-exynos/clock-exynos4210.c ? ? ? ? | ? 11 +
> >> ?arch/arm/mach-exynos/clock-exynos4212.c ? ? ? ? | ? 28 ++-
> >> ?arch/arm/mach-exynos/clock-exynos5.c ? ? ? ? ? ?| ? 90 +++++
> >> ?arch/arm/mach-exynos/dev-sysmmu.c ? ? ? ? ? ? ? | ?451
> >> ++++++++++++-----------
> >> ?arch/arm/mach-exynos/include/mach/irqs.h ? ? ? ?| ?179 +++++-----
> >> ?arch/arm/mach-exynos/include/mach/map.h ? ? ? ? | ? 38 ++
> >> ?arch/arm/mach-exynos/include/mach/regs-clock.h ?| ? ?5 +
> >> ?arch/arm/mach-exynos/include/mach/regs-sysmmu.h | ? 28 --
> >> ?arch/arm/mach-exynos/include/mach/sysmmu.h ? ? ?| ? 84 +++--
> >> ?arch/arm/mach-exynos/mach-armlex4210.c ? ? ? ? ?| ? ?1 -
> >> ?arch/arm/mach-exynos/mach-smdkv310.c ? ? ? ? ? ?| ? ?1 -
> >> ?arch/arm/plat-s5p/sysmmu.c ? ? ? ? ? ? ? ? ? ? ?| ? 13 +-
> >> ?arch/arm/plat-samsung/include/plat/devs.h ? ? ? | ? ?1 -
> >> ?17 files changed, 618 insertions(+), 406 deletions(-)
> > It's too big to cover these changes. Can you make it more small changes.
> > 1. Remove existing ones since no user at this time.
> > 2. Add new define and data structures.
> > 3. Support new system mmu features based on generic iommu.
> >
> 
> Your suggestion sounds good. Thank you.
> 
> >> ?static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
> >> ?{
> >> ? ? ? return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
> >> @@ -679,61 +684,55 @@ static struct clk exynos4_init_clocks_off[] = {
> >> ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clk_ip_peril_ctrl,
> >> ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 14),
> >> ? ? ? }, {
> >> - ? ? ? ? ? ? .name ? ? ? ? ? = "SYSMMU_MDMA",
> >> + ? ? ? ? ? ? .name ? ? ? ? ? = SYSMMU_CLOCK_NAME,
> >> + ? ? ? ? ? ? .devname ? ? ? ?= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
> >> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clk_ip_mfc_ctrl,
> >> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 1),
> >> + ? ? }, {
> >> + ? ? ? ? ? ? .name ? ? ? ? ? = SYSMMU_CLOCK_NAME,
> >> + ? ? ? ? ? ? .devname ? ? ? ?= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
> >> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clk_ip_mfc_ctrl,
> >> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 2),
> >> + ? ? }, {
> >> + ? ? ? ? ? ? .name ? ? ? ? ? = SYSMMU_CLOCK_NAME,
> >> + ? ? ? ? ? ? .devname ? ? ? ?= SYSMMU_CLOCK_DEVNAME(tv, 2),
> >> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clk_ip_tv_ctrl,
> >> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 4),
> >> + ? ? }, {
> >> + ? ? ? ? ? ? .name ? ? ? ? ? = SYSMMU_CLOCK_NAME,
> >> + ? ? ? ? ? ? .devname ? ? ? ?= SYSMMU_CLOCK_DEVNAME(jpeg, 3),
> >> + ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clk_ip_cam_ctrl,
> >> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 11),
> >> + ? ? }, {
> >> + ? ? ? ? ? ? .name ? ? ? ? ? = SYSMMU_CLOCK_NAME,
> >> + ? ? ? ? ? ? .devname ? ? ? ?= SYSMMU_CLOCK_DEVNAME(rot, 4),
> >> ? ? ? ? ? ? ? .enable ? ? ? ? = exynos4_clk_ip_image_ctrl,
> >> - ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 5),
> >> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 4),
> >> ? ? ? }, {
> >> - ? ? ? ? ? ? .name ? ? ? ? ? = "SYSMMU_FIMC0",
> >> + ? ? ? ? ? ? .name ? ? ? ? ? = SYSMMU_CLOCK_NAME,
> >> + ? ? ? ? ? ? .devname ? ? ? ?= SYSMMU_CLOCK_DEVNAME(gsc0, 5),
> > It's exynos4 series clock and don't have gsc name. I don't know LSI
> > decides to use gsc instead of fimc for both exynos4 and exynos5. but
> > there's no name gsc at Spec..
> 
> gsc0 is just a name of the platform device of FIMC0 in Exynos4.
> It is also used for GSclaler0 in Exynos5.
> I wanted to reduce waste of platform device definitions that do not exist
> in an application processor.
> 
> If it looks confused, I will find another way.
> >> +#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
> >> +
> >> +#define SYSMMU_RESOURCE(core, ipname) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> >> + ? ? static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
> >> +
> >> +#define DEFINE_SYSMMU_RESOURCE(core, mem, irq) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> >> + ? ? DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem), ? ? ?\
> >> + ? ? DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
> >> +
> >> +#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq) ? ? ? ? ? ? ? ? ? ? ? \
> >> + ? ? SYSMMU_RESOURCE(core, ipname) { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> >> + ? ? ? ? ? ? DEFINE_SYSMMU_RESOURCE(core, mem, irq) ? ? ? ? ? ? ? ? ?\
> >> + ? ? }
> >>
> >> -struct platform_device exynos4_device_sysmmu = {
> >> - ? ? .name ? ? ? ? ? = "s5p-sysmmu",
> >> - ? ? .id ? ? ? ? ? ? = 32,
> >> - ? ? .num_resources ?= ARRAY_SIZE(exynos4_sysmmu_resource),
> >> - ? ? .resource ? ? ? = exynos4_sysmmu_resource,
> >> +struct sysmmu_resource_map {
> >> + ? ? struct platform_device *pdev;
> >> + ? ? struct resource *res;
> >> + ? ? u32 rnum;
> >> + ? ? struct device *pdd;
> >> + ? ? char *clocknames;
> >> ?};
> >> -EXPORT_SYMBOL(exynos4_device_sysmmu);
> >>
> >> -static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
> >> -void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
> >> -{
> >> - ? ? sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
> >> - ? ? if (IS_ERR(sysmmu_clk[ips]))
> >> - ? ? ? ? ? ? sysmmu_clk[ips] = NULL;
> >> - ? ? else
> >> - ? ? ? ? ? ? clk_put(sysmmu_clk[ips]);
> >> +#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) { ? ? ? ? ? ? \
> >> + ? ? .pdev = &SYSMMU_PLATDEV(ipname), ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> >> + ? ? .res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), ? ? ? ? ? ? \
> >> + ? ? .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
> >> + ? ? .clocknames = SYSMMU_CLOCK_NAME, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> >> ?}
> >>
> >> -void sysmmu_clk_enable(sysmmu_ips ips)
> >> -{
> >> - ? ? if (sysmmu_clk[ips])
> >> - ? ? ? ? ? ? clk_enable(sysmmu_clk[ips]);
> >> +#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) { ? \
> >> + ? ? .pdev = &SYSMMU_PLATDEV(ipname), ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> >> + ? ? .res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), ? ? ? ? ? ? \
> >> + ? ? .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
> >> + ? ? .clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, ? ? ? ? \
> >> +}
> >> +
> >> +#ifdef CONFIG_EXYNOS_DEV_PD
> >> +#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) { ? ? ? ? ? ? ?\
> >> + ? ? .pdev = &SYSMMU_PLATDEV(ipname), ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> >> + ? ? .res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), ? ? ? ? ? ?\
> >> + ? ? .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
> >> + ? ? .clocknames = SYSMMU_CLOCK_NAME, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> >> + ? ? .pdd = &exynos##core##_device_pd[pd].dev, ? ? ? ? ? ? ? ? ? ? ? \
> >> +}
> >> +
> >> +#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
> >> + ? ? .pdev = &SYSMMU_PLATDEV(ipname), ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> >> + ? ? .res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), ? ? ? ? ? ?\
> >> + ? ? .rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
> >> + ? ? .clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, ? ? ? ? \
> >> + ? ? .pdd = &exynos##core##_device_pd[pd].dev, ? ? ? ? ? ? ? ? ? ? ? \
> >> ?}
> >> +#else
> >> +#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) ? ? ? ? ? ? ? ?\
> >> + ? ? ? ? ? ? SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
> >> +#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) ? ? ? \
> >> + ? ? ? ? ? ? SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
> >> +
> >> +#endif /* CONFIG_EXYNOS_DEV_PD */
> >> +
> >> +#ifdef CONFIG_ARCH_EXYNOS4
> > Below definitions are almost __initdata. So don't need to use ARCH_EXYNOS4.
> > and another reason is that it can detect the duplicated entry if it's
> > used both exynos4 and exynos5.

FIMC devices use s5p-fimc name in the mainline kernel. The driver is already there so
there, so please don't change it. 4 more lines with proper 'fimc' name will not cause
any problems.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From zonque at gmail.com  Thu Mar  1 10:10:50 2012
From: zonque at gmail.com (Daniel Mack)
Date: Thu, 01 Mar 2012 16:10:50 +0100
Subject: [PATCH 0/2] mxc_ehci: expand usb_hwinit options from boardfile
In-Reply-To: <3F263ABB4EDE344D974E1983B56807739E4BC6AC@EX-DAG02.eckelmann.group>
References: <3F263ABB4EDE344D974E1983B56807739E4BC6AC@EX-DAG02.eckelmann.group>
Message-ID: <4F4F917A.3040106@gmail.com>

On 28.02.2012 18:48, Mehnert, Torsten wrote:
> This patch series is about to expand the possibilities to configure mxc USB hardware initialization from boardfile.
> The expansions, defined in mxc_ehci.h, are implemented for the mx25.

FWIW, they both seem reasonable to me. I didn't check the datasheet
though, nor can I test these changes.


Daniel


From linux-arm at overkiz.com  Thu Mar  1 10:14:39 2012
From: linux-arm at overkiz.com (Boris BREZILLON)
Date: Thu, 01 Mar 2012 16:14:39 +0100
Subject: [PATCH] ARM: at91: Add support for configurable main clock frequency.
Message-ID: <4F4F925F.2020405@overkiz.com>

This patch provides main clock frequency configuration from device tree
definition.

If the "main-clock" attribute of pmc node is not specified it takes
12MHz as default value.

With this patch we can add board support using a different main clock
frequency (our custom board is using a 18,432MHz main clock).

---
 arch/arm/boot/dts/at91sam9g20.dtsi |    5 +++++
 arch/arm/mach-at91/board-dt.c      |   21 ++++++++++++++++++++-
 2 files changed, 25 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi
b/arch/arm/boot/dts/at91sam9g20.dtsi
index 07603b8..da253b2 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -46,6 +46,11 @@
 			#size-cells = <1>;
 			ranges;

+			pmc {
+				compatible = "atmel,at91-pmc";
+				reg = <0xfffffc00 0x100>;
+			};
+
 			aic: interrupt-controller at fffff000 {
 				#interrupt-cells = <1>;
 				compatible = "atmel,at91rm9200-aic";
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index bb6b434..c64a3b0 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -33,11 +33,30 @@
 #include "sam9_smc.h"
 #include "generic.h"

+static const struct of_device_id pmc_of_match[] __initconst = {
+	{ .compatible = "atmel,at91-pmc" },
+	{},
+};

 static void __init ek_init_early(void)
 {
+	struct device_node *node;
+	unsigned long main_clock = 12000000;
+
+	node = of_find_matching_node(NULL, pmc_of_match);
+
+	if (node) {
+		const __be32 *ip;
+		ip = of_get_property(node, "main-clock", NULL);
+		if (ip) {
+			main_clock = be32_to_cpup(ip);
+		}
+		of_node_put(node);
+	}
+
+
 	/* Initialize processor: 12.000 MHz crystal */
-	at91_initialize(12000000);
+	at91_initialize(main_clock);

 	/* DGBU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
-- 
1.7.0.4




From heiko at sntech.de  Thu Mar  1 10:24:03 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Thu, 1 Mar 2012 16:24:03 +0100
Subject: [PATCH v2 1/2] ARM: EXYNOS: Add USB HOST register definitions
In-Reply-To: <000701ccf76d$8316b0a0$894411e0$%han@samsung.com>
References: <000701ccf76d$8316b0a0$894411e0$%han@samsung.com>
Message-ID: <201203011624.04551.heiko@sntech.de>

Am Donnerstag, 1. M?rz 2012, 06:38:20 schrieb Jingoo Han:
> This patch adds USB HOST register definitions. The definition for
> EHCI INSNREG00 regiser and corresponding bit field definitions are
> added.
> 
> Signed-off-by: Sangwook Lee <sangwook.lee at linaro.org>
> Signed-off-by: Jingoo Han <jg1.han at samsung.com>
> ---
> v2: change the definition name from EHCI_ENA_xxx to EHCI_INSNREG00_ENA_xxx.
> 
> arch/arm/mach-exynos/include/mach/regs-usb-host.h |   24
> +++++++++++++++++++++ 1 files changed, 24 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-exynos/include/mach/regs-usb-host.h
Isn't the general idea to depopulate the mach directories and make drivers 
buildable across architectures?

The definitions are only used in drivers/usb/host/ehci-s5p.c [in the second 
patch], so there should be no need to add another arch-header and they could 
simply be included in the driver itself or if necessary a 
drivers/usb/host/ehci-s5p.h .


Heiko

> diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-host.h
> b/arch/arm/mach-exynos/include/mach/regs-usb-host.h new file mode 100644
> index 0000000..572b7d4
> --- /dev/null
> +++ b/arch/arm/mach-exynos/include/mach/regs-usb-host.h
> @@ -0,0 +1,24 @@
> +/*
> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> + *		http://www.samsung.com
> + *
> + * EXYNOS - USB HOST register definitions
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __REGS_USB_HOST_H
> +#define __REGS_USB_HOST_H __FILE__
> +
> +#define EHCI_INSNREG00(base)			(base + 0x90)
> +#define EHCI_INSNREG00_ENA_INCR16		(0x1 << 25)
> +#define EHCI_INSNREG00_ENA_INCR8		(0x1 << 24)
> +#define EHCI_INSNREG00_ENA_INCR4		(0x1 << 23)
> +#define EHCI_INSNREG00_ENA_INCRX_ALIGN		(0x1 << 22)
> +#define EHCI_INSNREG00_ENABLE_DMA_BURST	\
> +	(EHCI_INSNREG00_ENA_INCR16 | EHCI_INSNREG00_ENA_INCR8 |	\
> +	 EHCI_INSNREG00_ENA_INCR4 | EHCI_INSNREG00_ENA_INCRX_ALIGN)
> +
> +#endif /* __REGS_USB_HOST_H */



From broonie at opensource.wolfsonmicro.com  Thu Mar  1 10:34:38 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 1 Mar 2012 15:34:38 +0000
Subject: [PATCH 1/2] ARM: Add Kconfig option to use mkimage -T
 kernel_noload
In-Reply-To: <20120229194409.GO14173@pengutronix.de>
References: <1330473804-23348-1-git-send-email-swarren@nvidia.com>
 <20120229122942.GF3318@game.jcrosoft.org>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF206A@HQMAIL01.nvidia.com>
 <20120229181430.GI3318@game.jcrosoft.org>
 <4F4E6F96.8080907@am.sony.com>
 <20120229191209.GN14173@pengutronix.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF2122@HQMAIL01.nvidia.com>
 <20120229194409.GO14173@pengutronix.de>
Message-ID: <20120301153438.GA16916@sirena.org.uk>

On Wed, Feb 29, 2012 at 08:44:09PM +0100, Uwe Kleine-K?nig wrote:

> If you want to give incentive for U-Boot to improve, drop the target
> today. And note that at least people caring about boot time must not use
> the kernel's uImage target anyhow.

It's not just u-boot, at least Qi also uses uImage (I'm stuck with it on
one platform and don't currently have the time/enthusiasm to fix either
the bootloader selection or the zImage support).


From don.morris at hp.com  Thu Mar  1 10:48:37 2012
From: don.morris at hp.com (Don Morris)
Date: Thu,  1 Mar 2012 07:48:37 -0800
Subject: [PATCH V2] iop-adma: Corrected array overflow in RAID6 Xscale(R) test.
Message-ID: <1330616917-5198-1-git-send-email-don.morris@hp.com>

Bug: cppcheck reported overflow in array assignment (for loop walks
0 to IOP_ADMA_NUM_SRC_TEST+2, array size is IOP_ADMA_NUM_SRC_TEST).

Reported as: https://bugzilla.kernel.org/show_bug.cgi?id=42677

Test code pq_src array was grown by two elements to correspond with actual
usage (IOP_ADMA_NUM_SRC_TEST+2), stack consumption was kept constant by
modifying the pq_dest two element array which is only used when pq_src
is referenced up to IOP_ADMA_NUM_SRC_TEST elements into the address
of the new last two elements of the pq_src array. This is presumed to
be the original intent but would be reliant on compilers always having
pq_dest contiguous with the final element of pq_src.

Updated per review comments of Sergei Shtylyov <sshtylyov at mvista.com>

Signed-off-by: Don Morris <don.morris at hp.com>
---
 drivers/dma/iop-adma.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index 04be90b..9b1951d 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -1271,8 +1271,8 @@ iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device)
 	struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2];
 	/* address conversion buffers (dma_map / page_address) */
 	void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2];
-	dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST];
-	dma_addr_t pq_dest[2];
+	dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST+2];
+	dma_addr_t *pq_dest = &pq_src[IOP_ADMA_NUM_SRC_TEST];
 
 	int i;
 	struct dma_async_tx_descriptor *tx;
-- 
1.7.9.111.gf3fb0



From plagnioj at jcrosoft.com  Thu Mar  1 11:02:27 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 1 Mar 2012 17:02:27 +0100
Subject: [PATCH] ARM: at91: Add support for configurable main clock
 frequency.
In-Reply-To: <4F4F925F.2020405@overkiz.com>
References: <4F4F925F.2020405@overkiz.com>
Message-ID: <20120301160227.GB31766@game.jcrosoft.org>

On 16:14 Thu 01 Mar     , Boris BREZILLON wrote:
> This patch provides main clock frequency configuration from device tree
> definition.
> 
> If the "main-clock" attribute of pmc node is not specified it takes
> 12MHz as default value.
> 
> With this patch we can add board support using a different main clock
> frequency (our custom board is using a 18,432MHz main clock).
> 
This is not the right way you need to define a fixed clock

and the pmc is at91rm9200 compatible

You did do the Documentation either

wait a few I'll send it's support

Best Regards,
J.


From tony at atomide.com  Thu Mar  1 11:25:56 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 1 Mar 2012 08:25:56 -0800
Subject: Randconfig module build error with OMAP4_ERRATA_I688
In-Reply-To: <CAMQu2gxg_57AVW+MT_Sgi+gr2OUge-YPdSUxoG+z-zQth=4-UA@mail.gmail.com>
References: <20120229173719.GN18901@atomide.com>
 <CAMQu2gxg_57AVW+MT_Sgi+gr2OUge-YPdSUxoG+z-zQth=4-UA@mail.gmail.com>
Message-ID: <20120301162556.GY18901@atomide.com>

* Shilimkar, Santosh <santosh.shilimkar at ti.com> [120301 00:38]:
> On Wed, Feb 29, 2012 at 11:07 PM, Tony Lindgren <tony at atomide.com> wrote:
> > Hi Santosh,
> >
> > Looks like OMAP4_ERRATA_I688 still has one more issue:
> > Modules won't build at least with the attached randconfig
> > generated file.
> >
> > Can you please take a look at how to deal with it?
> >
> > Maybe omap_bus_sync should be an inline function with some
> > wrapper for the sleep44xx.S to call?
> >
> > I already posted a fix for the GPMC related error with the
> > same .config file.
> >
> This one builds for me against 'Linux 3.3-rc5,
> Ofocurse I got below error with the attached .config which
> I bypassed to see the Errata build failure.
> 
> arch/arm/mach-omap2/built-in.o: In function `n8x0_mmc_callback':
> linux-2.6/arch/arm/mach-omap2/board-n8x0.c:374: undefined reference to
> `omap_mmc_notify_cover_event'
> make: *** [.tmp_vmlinux1] Error 1

Yes a fix for that has been queued already.
 
> I build this with below toolchain...
> $arm-none-linux-gnueabi-gcc --version
> arm-none-linux-gnueabi-gcc (Sourcery G++ Lite 2011.03-41) 4.5.2
> Copyright (C) 2010 Free Software Foundation, Inc.
> 
> Am I missing anything ?

I think you're missing your commit 2ec1fc4e169acc0b8d6733ff028fd52e766773d9
(ARM: OMAP4: Move the barrier memboclk_steal() as part of reserve callback)
thats' queued up in fixes, and CONFIG_OMAP4_ERRATA_I688=y.

Then with -rc5 + 2ec1fc4e when you build modules you'll get this:

ERROR: "omap_bus_sync" [drivers/watchdog/sp805_wdt.ko] undefined!
ERROR: "omap_bus_sync" [drivers/watchdog/dw_wdt.ko] undefined!
ERROR: "omap_bus_sync" [drivers/virtio/virtio_ring.ko] undefined!
ERROR: "omap_bus_sync" [drivers/video/sm501fb.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/mon/usbmon.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/sl811-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/ohci-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/isp1760.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/isp1362-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/isp116x-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/core/usbcore.ko] undefined!
ERROR: "omap_bus_sync" [drivers/tty/serial/altera_uart.ko] undefined!
ERROR: "omap_bus_sync" [drivers/tty/serial/altera_jtaguart.ko] undefined!
ERROR: "omap_bus_sync" [drivers/tty/serial/8250/8250_dw.ko] undefined!
ERROR: "omap_bus_sync" [drivers/ssb/ssb.ko] undefined!
ERROR: "omap_bus_sync" [drivers/rtc/rtc-cmos.ko] undefined!
ERROR: "omap_bus_sync" [drivers/rtc/rtc-bq4802.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mtd/nand/tmio_nand.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mtd/nand/omap2.ko] undefined!

ERROR: "gpmc_calculate_ecc" [drivers/mtd/nand/omap2.ko] undefined!
ERROR: "gpmc_enable_hwecc" [drivers/mtd/nand/omap2.ko] undefined!

For the two above I already posted a fix for.

ERROR: "omap_bus_sync" [drivers/mtd/nand/nand.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mtd/nand/diskonchip.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mtd/maps/map_funcs.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mtd/devices/docprobe.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mtd/devices/doc2001.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mtd/devices/doc2000.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mmc/host/sdhci.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mmc/host/sdhci-pxav3.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mmc/host/sdhci-pxav2.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mmc/host/dw_mmc.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mfd/sm501.ko] undefined!
ERROR: "omap_bus_sync" [drivers/leds/leds-ot200.ko] undefined!
ERROR: "omap_bus_sync" [drivers/input/touchscreen/w90p910_ts.ko] undefined!
ERROR: "omap_bus_sync" [drivers/input/touchscreen/tsc2007.ko] undefined!
ERROR: "omap_bus_sync" [drivers/input/touchscreen/pixcir_i2c_ts.ko] undefined!
ERROR: "omap_bus_sync" [drivers/input/touchscreen/mk712.ko] undefined!
ERROR: "omap_bus_sync" [drivers/input/touchscreen/auo-pixcir-ts.ko] undefined!
ERROR: "omap_bus_sync" [drivers/input/serio/ambakmi.ko] undefined!
ERROR: "omap_bus_sync" [drivers/input/keyboard/matrix_keypad.ko] undefined!
ERROR: "omap_bus_sync" [drivers/input/keyboard/atkbd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/i2c/busses/i2c-simtec.ko] undefined!
ERROR: "omap_bus_sync" [drivers/i2c/busses/i2c-pca-platform.ko] undefined!
ERROR: "omap_bus_sync" [drivers/i2c/busses/i2c-ocores.ko] undefined!
ERROR: "omap_bus_sync" [drivers/gpu/drm/drm.ko] undefined!
ERROR: "omap_bus_sync" [drivers/dma/dw_dmac.ko] undefined!
ERROR: "omap_bus_sync" [drivers/char/nvram.ko] undefined!
ERROR: "omap_bus_sync" [drivers/block/mg_disk.ko] undefined!
ERROR: "omap_bus_sync" [drivers/base/firmware_class.ko] undefined!

Regards,

Tony


From laurent.pinchart at ideasonboard.com  Thu Mar  1 11:37:40 2012
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Thu, 01 Mar 2012 17:37:40 +0100
Subject: [PATCH] ARM: OMAP: make iommu subsys_initcall to fix builtin
 omap3isp
In-Reply-To: <CAK=WgbZRjGEyx0mKmgoWYiOnuvUAka0kTzpLAYbra94Mfpp6qg@mail.gmail.com>
References: <1330251254-14693-1-git-send-email-ohad@wizery.com>
 <35010303.ArkW8BdIu6@avalon>
 <CAK=WgbZRjGEyx0mKmgoWYiOnuvUAka0kTzpLAYbra94Mfpp6qg@mail.gmail.com>
Message-ID: <6354375.6C9sXAHKbF@avalon>

Hi Ohad,

On Monday 27 February 2012 09:00:51 Ohad Ben-Cohen wrote:
> On Mon, Feb 27, 2012 at 12:47 AM, Laurent Pinchart wrote:
> > I'm asking about the probe deferral mechanism. The omap3-isp driver will
> > still call iommu_attach_device() in its probe function. What will happen
> > then ? Will it return an error ? On what basis will it do so ?
> 
> Yes, iommu_attach_device() will fail, and omap3isp's probe function will
> then need to return -EAGAIN to request that its probe function will be
> invoked again later on.
> 
> > That's what the comment in the Makefile is for ;-) I don't think it's a
> > perfect solution either, but it avoids playing with the various initcalls.
> > The OMAP3 IOMMU isn't a subsystem, subsys_initcall() looks a bit like an
> > API abuse to me.
> 
> Yes, it's dirty.
> 
> But it's explicit and consistent across build system changes (without
> imposing anything on the build system). We do it all the time with other
> subsystems. We don't like it, but luckily Grant came up with the deferred
> probing mechanism, which will fix this all very nicely.
> 
> > Are drivers supposed to call iommu_attach_device() in their probe()
> > function or later on ?
> 
> If you can defer attaching to a later point, most commonly to a point
> where the device is opened by the user, it's better - less power will
> be consumed.

I'll try that then. How expensive is the iommu_attach_device() (and detach) 
operation in terms of CPU time ?

-- 
Regards,

Laurent Pinchart



From matt at genesi-usa.com  Thu Mar  1 11:41:43 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Thu, 1 Mar 2012 10:41:43 -0600
Subject: [PATCH] efikamx: match machine descriptions with legacy
In-Reply-To: <CAODfWeG4OpH1VkWOuHntUCygC8YVMfgTK=1onDweAZ8WYW6w+Q@mail.gmail.com>
References: <1329779368-27878-1-git-send-email-hector.oron@gmail.com>
 <CAHLCerPwJpM7x6WJ=1FUwJ96X-rgfLUEN840eoJ3SQsHg5gBDA@mail.gmail.com>
 <CAODfWeG4OpH1VkWOuHntUCygC8YVMfgTK=1onDweAZ8WYW6w+Q@mail.gmail.com>
Message-ID: <CAKGA1bnrQd9FpgfZpYu=_BiWNd5A+SP7GNfU9qsEJ3TFw4d-vw@mail.gmail.com>

On Thu, Feb 23, 2012 at 10:49 AM, Hector Oron <hector.oron at gmail.com> wrote:
> Hello,
>
> 2012/2/23 Amit Kucheria <amit.kucheria at linaro.org>:
>> On Tue, Feb 21, 2012 at 1:09 AM, Hector Oron <hector.oron at gmail.com> wrote:
>
>>> ?Rename machine descriptions to match legacy descriptions distributed by
>>> ?manufacturer BSP. This way distributions can do clean upgrades from
>>> ?userspace scripts which check for these values to differentiate platforms
>>> ?with single kernel binaries.
>>>
>>> Signed-off-by: Hector Oron <hector.oron at gmail.com>
>>> Acked-by: Matt Sealey <matt at genesi-usa.com>
>
>> This is likely to break flash-kernel used in debian/ubuntu/linaro I
>> suspect. Can you fix that too?
>
> Surely, I can and I will do.
>
>> Otherwise,
>> Acked-by: Amit Kucheria <amit.kucheria at linaro.org>

Thanks, Amit.

The patch is predicated on two things. Firstly that it unifies
behavior and the board identification across both BSP kernels and
mainline kernels, which is not up for argument on which is more
"correct" (vendor defines this, it is not a random freeform string of
the pusher's choosing, more importantly it is something at least 2
userspace tools use as input to seek board type and therefore is under
some restriction to change).

Secondly, upstream flash-kernel never worked on Debian or Ubuntu
anyway (patches sent upstream were needlessly rewritten to the point
that they actually simply did not work to produce a bootable kernel
image set, and pushed to Debian therefore breaking any chance of
Debian or Ubuntu supporting the board) and Linaro don't support the
EfikaMX with their MX5 kernels.

So this breaks nobody currently, but we actually want to get this
stuff done right upstream.

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.


From swarren at nvidia.com  Thu Mar  1 12:01:04 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Thu, 1 Mar 2012 09:01:04 -0800
Subject: [PATCH 1/2] ARM: Add Kconfig option to use mkimage -T
 kernel_noload
In-Reply-To: <1330473804-23348-1-git-send-email-swarren@nvidia.com>
References: <1330473804-23348-1-git-send-email-swarren@nvidia.com>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861683@HQMAIL01.nvidia.com>

Stephen Warren wrote at Tuesday, February 28, 2012 5:03 PM:
> uImage files typically encode a single absolute load and entry address.
> This is inconvenient when attempting to share that uImage across multiple
> SoCs with different physical RAM addresses. Recent versions of mkimage
> implement a "kernel_noload" image type which encodes no absolute load
> address, and a relative entry address. This works well for uImage-wrapped
> ARM zImages, since they are relocatable.
> 
> This is enabled by commit b9b50e89d317c58becd0e2d7fac2e21e3a81dd0a
> "image: Implement IH_TYPE_KERNEL_NOLOAD" in U-Boot.

So Russell, are you NAKing this patch then?

If so, I guess I'll just go and add more cruft to my copy-a-kernel-to-
an-sd-card script. Which is a pity since every other person will have
to do the same, but oh well.

-- 
nvpublic



From ohad at wizery.com  Thu Mar  1 12:12:40 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Thu, 1 Mar 2012 19:12:40 +0200
Subject: [PATCH] ARM: OMAP: make iommu subsys_initcall to fix builtin
 omap3isp
In-Reply-To: <6354375.6C9sXAHKbF@avalon>
References: <1330251254-14693-1-git-send-email-ohad@wizery.com>
 <35010303.ArkW8BdIu6@avalon>
 <CAK=WgbZRjGEyx0mKmgoWYiOnuvUAka0kTzpLAYbra94Mfpp6qg@mail.gmail.com>
 <6354375.6C9sXAHKbF@avalon>
Message-ID: <CAK=WgbariR4w_w3tzZtWdoMfxtzvNEJpcdh2VMFUWDUnfCqirA@mail.gmail.com>

Hi Laurent,

On Thu, Mar 1, 2012 at 6:37 PM, Laurent Pinchart
<laurent.pinchart at ideasonboard.com> wrote:
> I'll try that then. How expensive is the iommu_attach_device() (and detach)
> operation in terms of CPU time ?

omap_iommu_attach() basically enables the iommu clock and configures
that IP block.

I suspect it's negligible but I didn't really measure it...

Thanks,
Ohad.


From tony at atomide.com  Thu Mar  1 12:42:12 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 01 Mar 2012 09:42:12 -0800
Subject: [PATCH 0/2] Few more omap DT patches for next merge window
Message-ID: <20120301174037.12471.72457.stgit@kaulin.local>

Hi all,

Looks like we need one fix to what's currently queued up in
dt-part2 branch for omaps. And we can make board-generic more
readable by cutting down the ifdefs.

Regards,

Tony

---

Tony Lindgren (2):
      ARM: OMAP2+: Fix build error when only ARCH_OMAP2/3 or 4 is selected
      ARM: OMAP2+: Remove extra ifdefs for board-generic


 arch/arm/mach-omap2/board-generic.c |   83 ++++++++++++++++-------------------
 1 files changed, 39 insertions(+), 44 deletions(-)

-- 
Signature


From tony at atomide.com  Thu Mar  1 12:42:16 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 01 Mar 2012 09:42:16 -0800
Subject: [PATCH 1/2] ARM: OMAP2+: Fix build error when only ARCH_OMAP2/3 or
 4 is selected
In-Reply-To: <20120301174037.12471.72457.stgit@kaulin.local>
References: <20120301174037.12471.72457.stgit@kaulin.local>
Message-ID: <20120301174216.12471.75885.stgit@kaulin.local>

Otherwise we'll get undefined reference to `gic_of_init' or
undefined reference to `omap_intc_of_init'.

This was caused by commit fbf75da733e82bb17a01e1b907b0e40d9c028823
(ARM: OMAP2+: board-generic: Use of_irq_init API).

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-generic.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 12f4c5f..25d195f 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -25,6 +25,13 @@
 #include "common.h"
 #include "common-board-devices.h"
 
+#if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
+#define omap_intc_of_init	NULL
+#endif
+#ifndef CONFIG_ARCH_OMAP4
+#define gic_of_init		NULL
+#endif
+
 static struct of_device_id irq_match[] __initdata = {
 	{ .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },



From tony at atomide.com  Thu Mar  1 12:42:19 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 01 Mar 2012 09:42:19 -0800
Subject: [PATCH 2/2] ARM: OMAP2+: Remove extra ifdefs for board-generic
In-Reply-To: <20120301174037.12471.72457.stgit@kaulin.local>
References: <20120301174037.12471.72457.stgit@kaulin.local>
Message-ID: <20120301174219.12471.29458.stgit@kaulin.local>

We need just one ifdef for each ARCH_OMAP2/3/4.

Also remove the comment about i2c & twl driver as it's
pretty obvious that we still need some platform data
until drivers are converted to device tree.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-generic.c |   76 +++++++++++++++--------------------
 1 files changed, 32 insertions(+), 44 deletions(-)

diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 25d195f..74e1687 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -43,34 +43,6 @@ static void __init omap_init_irq(void)
 	of_irq_init(irq_match);
 }
 
-/*
- * XXX: Still needed to boot until the i2c & twl driver is adapted to
- * device-tree
- */
-#ifdef CONFIG_ARCH_OMAP4
-static struct twl4030_platform_data sdp4430_twldata = {
-	.irq_base	= TWL6030_IRQ_BASE,
-	.irq_end	= TWL6030_IRQ_END,
-};
-
-static void __init omap4_i2c_init(void)
-{
-	omap4_pmic_init("twl6030", &sdp4430_twldata);
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct twl4030_platform_data beagle_twldata = {
-	.irq_base	= TWL4030_IRQ_BASE,
-	.irq_end	= TWL4030_IRQ_END,
-};
-
-static void __init omap3_i2c_init(void)
-{
-	omap3_pmic_init("twl4030", &beagle_twldata);
-}
-#endif
-
 static struct of_device_id omap_dt_match_table[] __initdata = {
 	{ .compatible = "simple-bus", },
 	{ .compatible = "ti,omap-infra", },
@@ -84,22 +56,6 @@ static void __init omap_generic_init(void)
 	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
 }
 
-#ifdef CONFIG_ARCH_OMAP4
-static void __init omap4_init(void)
-{
-	omap4_i2c_init();
-	omap_generic_init();
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static void __init omap3_init(void)
-{
-	omap3_i2c_init();
-	omap_generic_init();
-}
-#endif
-
 #ifdef CONFIG_SOC_OMAP2420
 static const char *omap242x_boards_compat[] __initdata = {
 	"ti,omap2420",
@@ -139,6 +95,22 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
+static struct twl4030_platform_data beagle_twldata = {
+	.irq_base	= TWL4030_IRQ_BASE,
+	.irq_end	= TWL4030_IRQ_END,
+};
+
+static void __init omap3_i2c_init(void)
+{
+	omap3_pmic_init("twl4030", &beagle_twldata);
+}
+
+static void __init omap3_init(void)
+{
+	omap3_i2c_init();
+	omap_generic_init();
+}
+
 static const char *omap3_boards_compat[] __initdata = {
 	"ti,omap3",
 	NULL,
@@ -158,6 +130,22 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
+static struct twl4030_platform_data sdp4430_twldata = {
+	.irq_base	= TWL6030_IRQ_BASE,
+	.irq_end	= TWL6030_IRQ_END,
+};
+
+static void __init omap4_i2c_init(void)
+{
+	omap4_pmic_init("twl6030", &sdp4430_twldata);
+}
+
+static void __init omap4_init(void)
+{
+	omap4_i2c_init();
+	omap_generic_init();
+}
+
 static const char *omap4_boards_compat[] __initdata = {
 	"ti,omap4",
 	NULL,



From s.hauer at pengutronix.de  Thu Mar  1 13:18:46 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2012 19:18:46 +0100
Subject: [PATCH v2 2/2] dmaengine: Add support for multiple descriptors
 for imx-dma.
In-Reply-To: <CACKLOr2bFgSUW+oXgFReHt6ZS+t7atMJ6nzDgF4-e9cRyOYX4w@mail.gmail.com>
References: <1330445298-3522-1-git-send-email-javier.martin@vista-silicon.com>
 <1330445298-3522-3-git-send-email-javier.martin@vista-silicon.com>
 <20120301101904.GA3852@pengutronix.de>
 <CACKLOr2bFgSUW+oXgFReHt6ZS+t7atMJ6nzDgF4-e9cRyOYX4w@mail.gmail.com>
Message-ID: <20120301181846.GB3852@pengutronix.de>

On Thu, Mar 01, 2012 at 11:28:18AM +0100, javier Martin wrote:
> Hi Sascha,
> 
> On 1 March 2012 11:19, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > On Tue, Feb 28, 2012 at 05:08:18PM +0100, Javier Martin wrote:
> >> dmaengine specifies the possibility that several descriptors
> >> can be queued for transfer. It also indicates that tasklets
> >> must be used for DMA callbacks.
> >>
> >> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> >
> > Have you tested this patch with audio?
> 
> Yes,
> I have a test battery which tests audio, mmc, runs dmatest module and
> a custom mem2mem video device I'm developing.

Cool.

> 
> >
> >> +static int imxdma_xfer_desc(struct imxdma_desc *d)
> >> +{
> >> + ? ? struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
> >> + ? ? int ret;
> >> +
> >> + ? ? /* Configure and enable */
> >> + ? ? switch (d->type) {
> >> + ? ? case IMXDMA_DESC_MEMCPY:
> >> + ? ? ? ? ? ? ret = imx_dma_config_channel(imxdmac->imxdma_channel,
> >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d->config_port, d->config_mem, 0, 0);
> >> + ? ? ? ? ? ? if (ret < 0)
> >> + ? ? ? ? ? ? ? ? ? ? return ret;
> >> + ? ? ? ? ? ? ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
> >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?d->len, d->dest, d->dmamode);
> >> + ? ? ? ? ? ? if (ret < 0)
> >> + ? ? ? ? ? ? ? ? ? ? return ret;
> >> + ? ? ? ? ? ? break;
> >> + ? ? case IMXDMA_DESC_CYCLIC:
> >> + ? ? ? ? ? ? ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
> >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? imxdma_progression);
> >> + ? ? ? ? ? ? if (ret < 0)
> >> + ? ? ? ? ? ? ? ? ? ? return ret;
> >
> > You fall through here. Is this intended? If yes, a comment would be good
> > here.
> 
> Yes it is. cyclic is the same as slave_sg with the add-on of the
> progression handler and a specific configuration of the sglist which
> is done in 'imxdma_prep_dma_cyclic'.
> Do you want me to send a new version with a comment on the matter?

Yes, it's better to have a comment there. People looking at this code
will ask themselves the same question otherwise.

With this you can add my:

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Mar  1 13:20:25 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2012 19:20:25 +0100
Subject: [PATCH] ARM: 3ds_debugboard: Let ethernet be functional again
In-Reply-To: <20120301105239.GA3124@opensource.wolfsonmicro.com>
References: <1328646473-11828-1-git-send-email-festevam@gmail.com>
 <20120213082741.GN3852@pengutronix.de>
 <20120213144820.GA3494@opensource.wolfsonmicro.com>
 <20120214105823.GS3852@pengutronix.de>
 <20120214172902.GB3916@opensource.wolfsonmicro.com>
 <20120216073236.GE3852@pengutronix.de>
 <20120216075825.GA11631@opensource.wolfsonmicro.com>
 <20120301100847.GF26642@pengutronix.de>
 <20120301105239.GA3124@opensource.wolfsonmicro.com>
Message-ID: <20120301182025.GC3852@pengutronix.de>

On Thu, Mar 01, 2012 at 10:52:40AM +0000, Mark Brown wrote:
> On Thu, Mar 01, 2012 at 11:08:47AM +0100, Sascha Hauer wrote:
> 
> > Ok, I tried to do this. I Changed the function to:
> 
> > static struct platform_device *regulator_register_fixed(int id,
> > 		struct regulator_consumer_supply *supplies, int num_supplies)
> 
> > Now I have to register a fixed regulator with some invented value
> > for microvolts. What value should I choose? I tried 0 but the core
> > won't accept this as explained earlier, in short regulator_register()
> > returns with an error.
> 
> I've already suggested just fixing the fixed voltage regulator to be
> more sensible when it doesn't have a voltage but you say that won't work
> without explaining why you think that is the case and are still ignoring
> my repeated queries about that.

Maybe because I don't understand what you mean. What should the fixed
regulator do when voltage == 0?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From jason at lakedaemon.net  Thu Mar  1 13:20:51 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu,  1 Mar 2012 18:20:51 +0000
Subject: [PATCH 0/4] ARM: kirkwood: fdt: convert kirkwood init funcs to fdt
Message-ID: <cover.1330625877.git.jason@lakedaemon.net>

This series begins the process of converting all of the drivers initialized
from kirkwood_init() to devicetree.

The first patch cleans up kirkwood_init() by moving a flag setting to it's
appropriate location.  This will help later when converting the audio driver.

Next, I pull the functionality of kirkwood_init() into kirkwood_dt_init() in
board-dt.c  This way, as drivers are converted, their init calls can be removed
from kirkwood_dt_init() and non-fdt users won't be affected (they call
kirkwood_init()).

Last, I converted the two easiest drivers, rtc and wdt.  The xor and crypto
drivers remain for a later patch series.

Jason Cooper (4):
  ARM: kirkwood: move var setting to correct location.
  ARM: kirkwood: fdt: absorb kirkwood_init()
  ARM: kirkwood: convert rtc-mv to fdt.
  ARM: kirkwood: convert orion-wdt to fdt.

 arch/arm/boot/dts/kirkwood.dtsi   |   12 ++++++++++
 arch/arm/mach-kirkwood/board-dt.c |   28 ++++++++++++++++++++++-
 arch/arm/mach-kirkwood/common.c   |   10 ++++----
 arch/arm/mach-kirkwood/common.h   |    6 +++++
 drivers/rtc/rtc-mv.c              |   19 ++++++++++++++++
 drivers/watchdog/orion_wdt.c      |   44 ++++++++++++++++++++++++++----------
 6 files changed, 101 insertions(+), 18 deletions(-)

-- 
1.7.3.4



From jason at lakedaemon.net  Thu Mar  1 13:20:53 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu,  1 Mar 2012 18:20:53 +0000
Subject: [PATCH 2/4] ARM: kirkwood: fdt: absorb kirkwood_init()
In-Reply-To: <cover.1330625877.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
Message-ID: <9d9a87361c05b8b85e1ee2cdabb46a365c7abca8.1330625877.git.jason@lakedaemon.net>

We need to absorb kirkwood_init() into kirkwood_dt_init() so that as we
convert drivers, we can remove the platform call, eg
kirkwood_rtc_init().  This maintains compatibility with non-fdt
configurations because they still call kirkwood_init() in common.c.

As drivers are converted, we will reinstate the 'static' qualifier in
common.c.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/mach-kirkwood/board-dt.c |   30 +++++++++++++++++++++++++++++-
 arch/arm/mach-kirkwood/common.c   |   12 ++++++------
 arch/arm/mach-kirkwood/common.h   |    8 ++++++++
 3 files changed, 43 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 4960e63..a0cc28b 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -29,7 +29,9 @@
 #include <linux/spi/orion_spi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 #include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
 #include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
@@ -115,7 +117,33 @@ static void __init dreamplug_init(void)
 
 static void __init kirkwood_dt_init(void)
 {
-	kirkwood_init();
+	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
+		kirkwood_id(), kirkwood_tclk);
+
+	/*
+	 * Disable propagation of mbus errors to the CPU local bus,
+	 * as this causes mbus errors (which can occur for example
+	 * for PCI aborts) to throw CPU aborts, which we're not set
+	 * up to deal with.
+	 */
+	writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
+
+	kirkwood_setup_cpu_mbus();
+
+#ifdef CONFIG_CACHE_FEROCEON_L2
+	kirkwood_l2_init();
+#endif
+
+	/* internal devices that every board has */
+	kirkwood_rtc_init();
+	kirkwood_wdt_init();
+	kirkwood_xor0_init();
+	kirkwood_xor1_init();
+	kirkwood_crypto_init();
+
+#ifdef CONFIG_KEXEC
+	kexec_reinit = kirkwood_enable_pcie;
+#endif
 
 	if (of_machine_is_compatible("globalscale,dreamplug"))
 		dreamplug_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index d9e4d99..167b6c8 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -163,7 +163,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-static void __init kirkwood_rtc_init(void)
+void __init kirkwood_rtc_init(void)
 {
 	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
@@ -279,7 +279,7 @@ void __init kirkwood_crypto_init(void)
 /*****************************************************************************
  * XOR0
  ****************************************************************************/
-static void __init kirkwood_xor0_init(void)
+void __init kirkwood_xor0_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_XOR0;
 
@@ -291,7 +291,7 @@ static void __init kirkwood_xor0_init(void)
 /*****************************************************************************
  * XOR1
  ****************************************************************************/
-static void __init kirkwood_xor1_init(void)
+void __init kirkwood_xor1_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_XOR1;
 
@@ -303,7 +303,7 @@ static void __init kirkwood_xor1_init(void)
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-static void __init kirkwood_wdt_init(void)
+void __init kirkwood_wdt_init(void)
 {
 	orion_wdt_init(kirkwood_tclk);
 }
@@ -393,7 +393,7 @@ void __init kirkwood_audio_init(void)
 /*
  * Identify device ID and revision.
  */
-static char * __init kirkwood_id(void)
+char * __init kirkwood_id(void)
 {
 	u32 dev, rev;
 
@@ -436,7 +436,7 @@ static char * __init kirkwood_id(void)
 	}
 }
 
-static void __init kirkwood_l2_init(void)
+void __init kirkwood_l2_init(void)
 {
 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
 	writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 9071a39..c382447 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -51,6 +51,14 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev
 void kirkwood_audio_init(void);
 void kirkwood_restart(char, const char *);
 
+char *kirkwood_id(void);
+void kirkwood_l2_init(void);
+void kirkwood_rtc_init(void);
+void kirkwood_wdt_init(void);
+void kirkwood_xor0_init(void);
+void kirkwood_xor1_init(void);
+void kirkwood_crypto_init(void);
+
 extern int kirkwood_tclk;
 extern struct sys_timer kirkwood_timer;
 
-- 
1.7.3.4



From jason at lakedaemon.net  Thu Mar  1 13:20:54 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu,  1 Mar 2012 18:20:54 +0000
Subject: [PATCH 3/4] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <cover.1330625877.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
Message-ID: <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>

The comment at mach-kirkwood/common.c:469, says this device is in every
kirkwood board.  So, it is placed in kirkwood.dtsi.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
 arch/arm/mach-kirkwood/board-dt.c |    1 -
 arch/arm/mach-kirkwood/common.c   |    2 +-
 arch/arm/mach-kirkwood/common.h   |    1 -
 drivers/rtc/rtc-mv.c              |   19 +++++++++++++++++++
 5 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 771c6bb..5fb185c 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -2,5 +2,11 @@
 
 / {
 	compatible = "marvell,kirkwood";
+
+	rtc at f1010300 {
+		compatible = "marvell,rtc";
+		reg = <0xf1010300 0x1f>;
+		interrupts = <53>;
+	};
 };
 
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index a0cc28b..6fc41ae 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -135,7 +135,6 @@ static void __init kirkwood_dt_init(void)
 #endif
 
 	/* internal devices that every board has */
-	kirkwood_rtc_init();
 	kirkwood_wdt_init();
 	kirkwood_xor0_init();
 	kirkwood_xor1_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 167b6c8..0c0375f 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -163,7 +163,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-void __init kirkwood_rtc_init(void)
+static void __init kirkwood_rtc_init(void)
 {
 	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index c382447..ca08826 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -53,7 +53,6 @@ void kirkwood_restart(char, const char *);
 
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-void kirkwood_rtc_init(void);
 void kirkwood_wdt_init(void);
 void kirkwood_xor0_init(void);
 void kirkwood_xor1_init(void);
diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c
index 768e2ed..38abbf7 100644
--- a/drivers/rtc/rtc-mv.c
+++ b/drivers/rtc/rtc-mv.c
@@ -12,6 +12,8 @@
 #include <linux/bcd.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 #include <linux/delay.h>
 #include <linux/gfp.h>
 #include <linux/module.h>
@@ -218,10 +220,15 @@ static int __devinit mv_rtc_probe(struct platform_device *pdev)
 {
 	struct resource *res;
 	struct rtc_plat_data *pdata;
+	struct device_node *np = pdev->dev.of_node;
 	resource_size_t size;
 	u32 rtc_time;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	if (np)
+		of_address_to_resource(np, 0, res);
+
 	if (!res)
 		return -ENODEV;
 
@@ -257,6 +264,8 @@ static int __devinit mv_rtc_probe(struct platform_device *pdev)
 
 	pdata->irq = platform_get_irq(pdev, 0);
 
+	of_property_read_u32(np, "interrupts", &pdata->irq);
+
 	platform_set_drvdata(pdev, pdata);
 
 	if (pdata->irq >= 0) {
@@ -294,11 +303,21 @@ static int __exit mv_rtc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id rtc_mv_of_match_table[] = {
+	{ .compatible = "marvell,rtc", },
+	{}
+};
+#else
+#define rtc_mv_of_match_table NULL
+#endif
+
 static struct platform_driver mv_rtc_driver = {
 	.remove		= __exit_p(mv_rtc_remove),
 	.driver		= {
 		.name	= "rtc-mv",
 		.owner	= THIS_MODULE,
+		.of_match_table = rtc_mv_of_match_table,
 	},
 };
 
-- 
1.7.3.4



From jason at lakedaemon.net  Thu Mar  1 13:20:52 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu,  1 Mar 2012 18:20:52 +0000
Subject: [PATCH 1/4] ARM: kirkwood: move var setting to correct location.
In-Reply-To: <cover.1330625877.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
Message-ID: <dd039cd4cb126bd4c64903f6208500ae93d674b1.1330625877.git.jason@lakedaemon.net>

This variable should be set within the driver init function that uses
it's struct, not in the generic init function.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/mach-kirkwood/common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 357fcde..d9e4d99 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -382,6 +382,7 @@ static struct platform_device kirkwood_pcm_device = {
 void __init kirkwood_audio_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_AUDIO;
+	kirkwood_i2s_data.tclk = kirkwood_tclk;
 	platform_device_register(&kirkwood_i2s_device);
 	platform_device_register(&kirkwood_pcm_device);
 }
@@ -450,7 +451,6 @@ void __init kirkwood_init(void)
 {
 	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
 		kirkwood_id(), kirkwood_tclk);
-	kirkwood_i2s_data.tclk = kirkwood_tclk;
 
 	/*
 	 * Disable propagation of mbus errors to the CPU local bus,
-- 
1.7.3.4



From jason at lakedaemon.net  Thu Mar  1 13:20:55 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu,  1 Mar 2012 18:20:55 +0000
Subject: [PATCH 4/4] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <cover.1330625877.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
Message-ID: <2f29e88b98b2bcff0c241996e6d7216a60995d2d.1330625878.git.jason@lakedaemon.net>

Converted register address to a variable so that it could be set from
fdt.  Also, pull clock frequency from fdt and clean up failure logic a
bit.

Same as rtc-mv, this device is used in all kirkwood boards.  So, it is
placed in kirkwood.dtsi.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/boot/dts/kirkwood.dtsi   |    6 +++++
 arch/arm/mach-kirkwood/board-dt.c |    1 -
 arch/arm/mach-kirkwood/common.c   |    2 +-
 arch/arm/mach-kirkwood/common.h   |    1 -
 drivers/watchdog/orion_wdt.c      |   44 ++++++++++++++++++++++++++----------
 5 files changed, 39 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 5fb185c..bf28424 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -8,5 +8,11 @@
 		reg = <0xf1010300 0x1f>;
 		interrupts = <53>;
 	};
+
+	wdt at fed20300 {
+		compatible = "marvell,orion-wdt";
+		reg = <0xfed20300 0x28>;
+		clock-frequency = <200000000>;
+	};
 };
 
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 6fc41ae..7ef5fb7 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -135,7 +135,6 @@ static void __init kirkwood_dt_init(void)
 #endif
 
 	/* internal devices that every board has */
-	kirkwood_wdt_init();
 	kirkwood_xor0_init();
 	kirkwood_xor1_init();
 	kirkwood_crypto_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 0c0375f..35dc40b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -303,7 +303,7 @@ void __init kirkwood_xor1_init(void)
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-void __init kirkwood_wdt_init(void)
+static void __init kirkwood_wdt_init(void)
 {
 	orion_wdt_init(kirkwood_tclk);
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index ca08826..ac4b2fb 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -53,7 +53,6 @@ void kirkwood_restart(char, const char *);
 
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-void kirkwood_wdt_init(void);
 void kirkwood_xor0_init(void);
 void kirkwood_xor1_init(void);
 void kirkwood_crypto_init(void);
diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
index 4ad78f8..4be76ca 100644
--- a/drivers/watchdog/orion_wdt.c
+++ b/drivers/watchdog/orion_wdt.c
@@ -17,6 +17,7 @@
 #include <linux/fs.h>
 #include <linux/miscdevice.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/watchdog.h>
 #include <linux/init.h>
 #include <linux/uaccess.h>
@@ -28,9 +29,9 @@
 /*
  * Watchdog timer block registers.
  */
-#define TIMER_CTRL		(TIMER_VIRT_BASE + 0x0000)
+#define TIMER_CTRL		0x0000
 #define  WDT_EN			0x0010
-#define WDT_VAL			(TIMER_VIRT_BASE + 0x0024)
+#define WDT_VAL			0x0024
 
 #define WDT_MAX_CYCLE_COUNT	0xffffffff
 #define WDT_IN_USE		0
@@ -40,6 +41,7 @@ static int nowayout = WATCHDOG_NOWAYOUT;
 static int heartbeat = -1;		/* module parameter (seconds) */
 static unsigned int wdt_max_duration;	/* (seconds) */
 static unsigned int wdt_tclk;
+static unsigned int wdt_reg;
 static unsigned long wdt_status;
 static DEFINE_SPINLOCK(wdt_lock);
 
@@ -48,7 +50,7 @@ static void orion_wdt_ping(void)
 	spin_lock(&wdt_lock);
 
 	/* Reload watchdog duration */
-	writel(wdt_tclk * heartbeat, WDT_VAL);
+	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
 
 	spin_unlock(&wdt_lock);
 }
@@ -60,7 +62,7 @@ static void orion_wdt_enable(void)
 	spin_lock(&wdt_lock);
 
 	/* Set watchdog duration */
-	writel(wdt_tclk * heartbeat, WDT_VAL);
+	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
 
 	/* Clear watchdog timer interrupt */
 	reg = readl(BRIDGE_CAUSE);
@@ -68,9 +70,9 @@ static void orion_wdt_enable(void)
 	writel(reg, BRIDGE_CAUSE);
 
 	/* Enable watchdog timer */
-	reg = readl(TIMER_CTRL);
+	reg = readl(wdt_reg + TIMER_CTRL);
 	reg |= WDT_EN;
-	writel(reg, TIMER_CTRL);
+	writel(reg, wdt_reg + TIMER_CTRL);
 
 	/* Enable reset on watchdog */
 	reg = readl(RSTOUTn_MASK);
@@ -92,9 +94,9 @@ static void orion_wdt_disable(void)
 	writel(reg, RSTOUTn_MASK);
 
 	/* Disable watchdog timer */
-	reg = readl(TIMER_CTRL);
+	reg = readl(wdt_reg + TIMER_CTRL);
 	reg &= ~WDT_EN;
-	writel(reg, TIMER_CTRL);
+	writel(reg, wdt_reg + TIMER_CTRL);
 
 	spin_unlock(&wdt_lock);
 }
@@ -102,7 +104,7 @@ static void orion_wdt_disable(void)
 static int orion_wdt_get_timeleft(int *time_left)
 {
 	spin_lock(&wdt_lock);
-	*time_left = readl(WDT_VAL) / wdt_tclk;
+	*time_left = readl(wdt_reg + WDT_VAL) / wdt_tclk;
 	spin_unlock(&wdt_lock);
 	return 0;
 }
@@ -236,15 +238,23 @@ static struct miscdevice orion_wdt_miscdev = {
 static int __devinit orion_wdt_probe(struct platform_device *pdev)
 {
 	struct orion_wdt_platform_data *pdata = pdev->dev.platform_data;
+	struct device_node *np = pdev->dev.of_node;
 	int ret;
 
-	if (pdata) {
+	if (pdata)
 		wdt_tclk = pdata->tclk;
-	} else {
-		printk(KERN_ERR "Orion Watchdog misses platform data\n");
+
+	of_property_read_u32(np, "clock-frequency", &wdt_tclk);
+
+	if (!wdt_tclk) {
+		printk(KERN_ERR "Orion Watchdog can't get clock freq\n");
 		return -ENODEV;
 	}
 
+	wdt_reg = TIMER_VIRT_BASE;
+
+	of_property_read_u32(np, "reg", &wdt_reg);
+
 	if (orion_wdt_miscdev.parent)
 		return -EBUSY;
 	orion_wdt_miscdev.parent = &pdev->dev;
@@ -284,6 +294,15 @@ static void orion_wdt_shutdown(struct platform_device *pdev)
 		orion_wdt_disable();
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id orion_wdt_of_match_table[] = {
+	{ .compatible = "marvell,orion-wdt", },
+	{},
+};
+#else
+#define orion_wdt_of_match_table NULL
+#endif
+
 static struct platform_driver orion_wdt_driver = {
 	.probe		= orion_wdt_probe,
 	.remove		= __devexit_p(orion_wdt_remove),
@@ -291,6 +310,7 @@ static struct platform_driver orion_wdt_driver = {
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "orion_wdt",
+		.of_match_table = orion_wdt_of_match_table,
 	},
 };
 
-- 
1.7.3.4



From broonie at opensource.wolfsonmicro.com  Thu Mar  1 13:21:39 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 1 Mar 2012 18:21:39 +0000
Subject: [PATCH] ARM: 3ds_debugboard: Let ethernet be functional again
In-Reply-To: <20120301182025.GC3852@pengutronix.de>
References: <1328646473-11828-1-git-send-email-festevam@gmail.com>
 <20120213082741.GN3852@pengutronix.de>
 <20120213144820.GA3494@opensource.wolfsonmicro.com>
 <20120214105823.GS3852@pengutronix.de>
 <20120214172902.GB3916@opensource.wolfsonmicro.com>
 <20120216073236.GE3852@pengutronix.de>
 <20120216075825.GA11631@opensource.wolfsonmicro.com>
 <20120301100847.GF26642@pengutronix.de>
 <20120301105239.GA3124@opensource.wolfsonmicro.com>
 <20120301182025.GC3852@pengutronix.de>
Message-ID: <20120301182139.GE10915@opensource.wolfsonmicro.com>

On Thu, Mar 01, 2012 at 07:20:25PM +0100, Sascha Hauer wrote:
> On Thu, Mar 01, 2012 at 10:52:40AM +0000, Mark Brown wrote:

> > I've already suggested just fixing the fixed voltage regulator to be
> > more sensible when it doesn't have a voltage but you say that won't work
> > without explaining why you think that is the case and are still ignoring
> > my repeated queries about that.

> Maybe because I don't understand what you mean. What should the fixed
> regulator do when voltage == 0?

Not report that it has a voltage so report an error when asked and not
claim you can enumerate them.
-------------- next part --------------
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From s.hauer at pengutronix.de  Thu Mar  1 13:30:23 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 1 Mar 2012 19:30:23 +0100
Subject: [PATCH] ARM: 3ds_debugboard: Let ethernet be functional again
In-Reply-To: <20120301182139.GE10915@opensource.wolfsonmicro.com>
References: <20120213082741.GN3852@pengutronix.de>
 <20120213144820.GA3494@opensource.wolfsonmicro.com>
 <20120214105823.GS3852@pengutronix.de>
 <20120214172902.GB3916@opensource.wolfsonmicro.com>
 <20120216073236.GE3852@pengutronix.de>
 <20120216075825.GA11631@opensource.wolfsonmicro.com>
 <20120301100847.GF26642@pengutronix.de>
 <20120301105239.GA3124@opensource.wolfsonmicro.com>
 <20120301182025.GC3852@pengutronix.de>
 <20120301182139.GE10915@opensource.wolfsonmicro.com>
Message-ID: <20120301183023.GD3852@pengutronix.de>

On Thu, Mar 01, 2012 at 06:21:39PM +0000, Mark Brown wrote:
> On Thu, Mar 01, 2012 at 07:20:25PM +0100, Sascha Hauer wrote:
> > On Thu, Mar 01, 2012 at 10:52:40AM +0000, Mark Brown wrote:
> 
> > > I've already suggested just fixing the fixed voltage regulator to be
> > > more sensible when it doesn't have a voltage but you say that won't work
> > > without explaining why you think that is the case and are still ignoring
> > > my repeated queries about that.
> 
> > Maybe because I don't understand what you mean. What should the fixed
> > regulator do when voltage == 0?
> 
> Not report that it has a voltage so report an error when asked and not
> claim you can enumerate them.

Now I got it. That was a loooong way ;)

Thanks
 Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linus.walleij at linaro.org  Thu Mar  1 13:34:07 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu,  1 Mar 2012 19:34:07 +0100
Subject: [GIT PULL] ux500 fixes for v3.4, take 3
Message-ID: <1330626847-3266-1-git-send-email-linus.walleij@linaro.org>


-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Hi ARM-SoC maintainers,

here is an updated pull request for the 3.4 merge window, and I
still expect it to be pretty orthogonal to most other stuff going on
except for maybe Lee Jones' SoC bus patches.

I've left the two U9540 patches off this pull request, I may
present these separately if I get to test the fix suggested
by Arnd, in the meantime this is up for grabs.

The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:

  Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)

are available in the git repository at:
  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git/ ux500-fixes-20120301

Arnd Bergmann (4):
      ARM: ux500: U8500 depends on MMU
      ARM: ux500: add board autoselection
      ARM: ux500: select L2X0 cache on ux500
      ARM: ux500: select CPU_FREQ_TABLE where needed

Danny Kukawka (1):
      ARM: ux500: included linux/gpio.h twice

Linus Walleij (2):
      ARM: ux500: delete TPS6105X selection
      ARM: ux500: solve some Kconfig mess

Ola Lilja (3):
      ARM: ux500: Add placeholder for clk_set_parent
      ARM: ux500: Add DMA-channels for MSP
      ARM: ux500: Add audio-regulators

Philippe Langlais (2):
      ARM: ux500: set ARCH_NR_GPIO to 355 on U8500 platforms
      ARM: ux500: fix around AB8500 GPIO macro name

 arch/arm/Kconfig                              |    3 +-
 arch/arm/mach-ux500/Kconfig                   |   44 ++++++++++++++----------
 arch/arm/mach-ux500/Makefile                  |    2 +-
 arch/arm/mach-ux500/board-mop500-regulators.c |   28 ++++++++++++++++
 arch/arm/mach-ux500/board-mop500-u8500uib.c   |    1 -
 arch/arm/mach-ux500/board-mop500.c            |    2 +-
 arch/arm/mach-ux500/board-mop500.h            |    2 +-
 arch/arm/mach-ux500/clock.c                   |    7 ++++
 arch/arm/mach-ux500/clock.h                   |    1 +
 arch/arm/mach-ux500/devices-db8500.c          |    6 +++
 arch/arm/mach-ux500/include/mach/hardware.h   |    2 +
 arch/arm/mach-ux500/include/mach/irqs.h       |    2 +-
 12 files changed, 76 insertions(+), 24 deletions(-)
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qGa8Gc8xgoQjez+SUOfj
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From robert.jarzmik at free.fr  Thu Mar  1 13:50:50 2012
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Thu, 01 Mar 2012 19:50:50 +0100
Subject: Linux 3.3-rc5 and pxa-gpio possible regression
In-Reply-To: <1330565036.86950.YahooMailClassic@web29009.mail.ird.yahoo.com>
 (Paul Parsons's message of "Thu, 1 Mar 2012 01:23:56 +0000 (GMT)")
References: <1330565036.86950.YahooMailClassic@web29009.mail.ird.yahoo.com>
Message-ID: <87sjhstat1.fsf@free.fr>

Paul Parsons <lost.distance at yahoo.com> writes:

>> I've tried the 3.3-rc5 kernel and my boot hangs (PXA270
>> platform).
>
> Same here. Your problem may be the same as this:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/084307.html
>
> Does the patch below fix your problem?
Yes, absolutely, it fixes it.

Thanks for the info.

Cheers.

--
Robert


From tony at atomide.com  Thu Mar  1 13:55:21 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 01 Mar 2012 10:55:21 -0800
Subject: [PATCH 0/4] Start getting rid of pdata callbacks with
 gpio_find_by_chip_name()
Message-ID: <20120301185044.29210.44521.stgit@kaulin.local>

Hi all,

This series adds gpio_find_by_name() that allows finding
GPIOs on specific gpio_chips. As the GPIO numbers can be
dynamic, it's hard to find the GPIO numbers from drivers
using them directly.

So far we've dealt with this using platform specific callbacks,
but that is messy. This series removes the needs for these
callbacks for omap hsmmc driver. Further callbacks can be
removed people are OK with adding gpio_find_by_name().

This series is based on the omap fixes-non-critical that's
needed for the arch/arm/mach-omap2 parts of this series.

Regards,

Tony

---

Tony Lindgren (4):
      gpiolib: Add gpiochip_find_by_name() and gpio_find_by_chip_name()
      mmc: omap_hsmmc: Use gpio_find_by_chip_name() for omap_hsmmc_gpio_init()
      mmc: omap_hsmmc: Use GPIO offset for external GPIO chips
      mmc: omap_hsmmc: Simplify init for twl6030 MMC card detect


 arch/arm/mach-omap2/board-3430sdp.c          |   13 +-
 arch/arm/mach-omap2/board-4430sdp.c          |   45 --------
 arch/arm/mach-omap2/board-cm-t35.c           |    8 -
 arch/arm/mach-omap2/board-devkit8000.c       |    7 -
 arch/arm/mach-omap2/board-igep0020.c         |    8 -
 arch/arm/mach-omap2/board-omap3beagle.c      |    9 +-
 arch/arm/mach-omap2/board-omap3evm.c         |    8 -
 arch/arm/mach-omap2/board-omap3pandora.c     |   13 +-
 arch/arm/mach-omap2/board-omap3stalker.c     |    8 -
 arch/arm/mach-omap2/board-omap3touchbook.c   |    7 -
 arch/arm/mach-omap2/board-omap4panda.c       |   52 ----------
 arch/arm/mach-omap2/board-zoom-peripherals.c |    7 -
 arch/arm/mach-omap2/hsmmc.c                  |    3 +
 arch/arm/mach-omap2/hsmmc.h                  |    5 +
 arch/arm/plat-omap/include/plat/mmc.h        |    3 +
 drivers/gpio/gpio-twl4030.c                  |    2 
 drivers/gpio/gpiolib.c                       |   47 +++++++++
 drivers/mfd/twl6030-irq.c                    |   33 +++---
 drivers/mmc/host/omap_hsmmc.c                |  140 +++++++++++++++++++-------
 include/asm-generic/gpio.h                   |    3 -
 20 files changed, 204 insertions(+), 217 deletions(-)

-- 
Signature


From tony at atomide.com  Thu Mar  1 13:55:24 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 01 Mar 2012 10:55:24 -0800
Subject: [PATCH 1/4] gpiolib: Add gpiochip_find_by_name() and
 gpio_find_by_chip_name()
In-Reply-To: <20120301185044.29210.44521.stgit@kaulin.local>
References: <20120301185044.29210.44521.stgit@kaulin.local>
Message-ID: <20120301185524.29210.60381.stgit@kaulin.local>

Currently there is no way for drivers to request a GPIO on a particular
gpio chip. This makes it hard to support multiple GPIO controllers
with dynamic GPIO and interrupt numbering, such as with CONFIG_SPARSE_IRQ.

Make it easier for device drivers to find GPIOs on a specific gpio_chip
by adding two functions: gpiochip_find_by_name() and gpio_find_by_chip_name().

Note that as gpiochip_find() is already exported, we may as well
export gpiochip_find_by_name() too.

Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 drivers/gpio/gpiolib.c     |   47 ++++++++++++++++++++++++++++++++++++++++++++
 include/asm-generic/gpio.h |    3 ++-
 2 files changed, 49 insertions(+), 1 deletions(-)

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 17fdf4b..0e5bf55 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1173,6 +1173,53 @@ struct gpio_chip *gpiochip_find(void *data,
 }
 EXPORT_SYMBOL_GPL(gpiochip_find);
 
+static int match_name(struct gpio_chip *chip, void *data)
+{
+	const char *name = data;
+
+	return sysfs_streq(name, chip->label);
+}
+
+/**
+ * gpiochip_find_by_name() - iterator for locating a gpio_chip by name
+ * @name: name of the gpio_chip
+ *
+ * Similar to bus_find_device_by_name. It returns a reference to the
+ * first gpio_chip with matching name. It ignores NULL and empty names.
+ * If you need to do something more complex, then use gpiochip_find.
+ */
+struct gpio_chip *gpiochip_find_by_name(const char *name)
+{
+	if (!name || !strcmp(name, ""))
+		return NULL;
+
+	return gpiochip_find((void *)name, match_name);
+}
+EXPORT_SYMBOL_GPL(gpiochip_find_by_name);
+
+/**
+ * gpio_find_by_chip_name() - find a gpio on a specific gpio_chip
+ * @chip_name: name of the gpio_chip
+ * @gpio_offset: offset of the gpio on the gpio_chip
+ *
+ * Note that gpiochip_find_by_name returns the first matching
+ * gpio_chip name. For more complex matching, see gpio_find.
+ */
+int gpio_find_by_chip_name(const char *chip_name, unsigned gpio_offset)
+{
+	struct gpio_chip *chip;
+	int gpio, res;
+
+	chip = gpiochip_find_by_name(chip_name);
+	if (!chip)
+		return -ENODEV;
+
+	gpio = chip->base + gpio_offset;
+
+	return gpio;
+}
+EXPORT_SYMBOL_GPL(gpio_find_by_chip_name);
+
 /* These "optional" allocation calls help prevent drivers from stomping
  * on each other, and help provide better diagnostics in debugfs.
  * They're called even less than the "set direction" calls.
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 1ff4e22..d7a2100 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -145,7 +145,8 @@ extern int __must_check gpiochip_remove(struct gpio_chip *chip);
 extern struct gpio_chip *gpiochip_find(void *data,
 					int (*match)(struct gpio_chip *chip,
 						     void *data));
-
+extern struct gpio_chip *gpiochip_find_by_name(const char *name);
+extern int gpio_find_by_chip_name(const char *chip_name, unsigned gpio_offset);
 
 /* Always use the library code for GPIO management calls,
  * or when sleeping may be involved.



From tony at atomide.com  Thu Mar  1 13:55:32 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 01 Mar 2012 10:55:32 -0800
Subject: [PATCH 3/4] mmc: omap_hsmmc: Use GPIO offset for external GPIO chips
In-Reply-To: <20120301185044.29210.44521.stgit@kaulin.local>
References: <20120301185044.29210.44521.stgit@kaulin.local>
Message-ID: <20120301185532.29210.32421.stgit@kaulin.local>

We can now remove the setting of GPIO pins with callbacks
as the drivers can access a GPIO offset on a named gpio_chip
directly with gpio_find_by_chip_name().

Cc: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-3430sdp.c          |   13 ++++---------
 arch/arm/mach-omap2/board-cm-t35.c           |    8 ++------
 arch/arm/mach-omap2/board-devkit8000.c       |    7 ++-----
 arch/arm/mach-omap2/board-igep0020.c         |    8 ++------
 arch/arm/mach-omap2/board-omap3beagle.c      |    9 +++------
 arch/arm/mach-omap2/board-omap3evm.c         |    8 ++------
 arch/arm/mach-omap2/board-omap3pandora.c     |   13 ++++---------
 arch/arm/mach-omap2/board-omap3stalker.c     |    8 ++------
 arch/arm/mach-omap2/board-omap3touchbook.c   |    7 ++-----
 arch/arm/mach-omap2/board-zoom-peripherals.c |    7 ++-----
 10 files changed, 25 insertions(+), 63 deletions(-)

diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index da75f23..238b95a 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -231,14 +231,16 @@ static struct omap2_hsmmc_info mmc[] = {
 		 * so the SIM card isn't used; else 4 bits.
 		 */
 		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
 		.gpio_wp	= 4,
-		.deferred	= true,
 	},
 	{
 		.mmc		= 2,
 		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 1,	/* mmc1_cd offset in twl4030 */
 		.gpio_wp	= 7,
-		.deferred	= true,
 	},
 	{}	/* Terminator */
 };
@@ -246,13 +248,6 @@ static struct omap2_hsmmc_info mmc[] = {
 static int sdp3430_twl_gpio_setup(struct device *dev,
 		unsigned gpio, unsigned ngpio)
 {
-	/* gpio + 0 is "mmc0_cd" (input/IRQ),
-	 * gpio + 1 is "mmc1_cd" (input/IRQ)
-	 */
-	mmc[0].gpio_cd = gpio + 0;
-	mmc[1].gpio_cd = gpio + 1;
-	omap_hsmmc_late_init(mmc);
-
 	/* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
 	gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
 
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 49e6405..26466f3 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -411,9 +411,9 @@ static struct omap2_hsmmc_info mmc[] = {
 	{
 		.mmc		= 1,
 		.caps		= MMC_CAP_4_BIT_DATA,
-		.gpio_cd	= -EINVAL,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
 		.gpio_wp	= -EINVAL,
-		.deferred	= true,
 	},
 	{
 		.mmc		= 2,
@@ -469,10 +469,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
 		pr_err("CM-T35: could not obtain gpio for WiFi reset\n");
 	}
 
-	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
-	mmc[0].gpio_cd = gpio + 0;
-	omap_hsmmc_late_init(mmc);
-
 	return 0;
 }
 
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 11cd2a8..b250999 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -99,8 +99,9 @@ static struct omap2_hsmmc_info mmc[] = {
 	{
 		.mmc		= 1,
 		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
 		.gpio_wp	= 29,
-		.deferred	= true,
 	},
 	{}	/* Terminator */
 };
@@ -227,10 +228,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
 {
 	int ret;
 
-	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
-	mmc[0].gpio_cd = gpio + 0;
-	omap_hsmmc_late_init(mmc);
-
 	/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
 	gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
 
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index e558800..d39f016 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -293,9 +293,9 @@ static struct omap2_hsmmc_info mmc[] = {
 	{
 		.mmc		= 1,
 		.caps		= MMC_CAP_4_BIT_DATA,
-		.gpio_cd	= -EINVAL,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
 		.gpio_wp	= -EINVAL,
-		.deferred	= true,
 	},
 #if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
 	{
@@ -401,10 +401,6 @@ static int igep_twl_gpio_setup(struct device *dev,
 {
 	int ret;
 
-	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
-	mmc[0].gpio_cd = gpio + 0;
-	omap_hsmmc_late_init(mmc);
-
 	/* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
 #if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
 	ret = gpio_request_one(gpio + TWL4030_GPIO_MAX + 1, GPIOF_OUT_INIT_HIGH,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7be8d65..bbb3234 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -252,8 +252,9 @@ static struct omap2_hsmmc_info mmc[] = {
 	{
 		.mmc		= 1,
 		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
 		.gpio_wp	= -EINVAL,
-		.deferred	= true,
 	},
 	{}	/* Terminator */
 };
@@ -273,11 +274,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
 {
 	int r;
 
-	mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
-	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
-	mmc[0].gpio_cd = gpio + 0;
-	omap_hsmmc_late_init(mmc);
-
 	/*
 	 * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
 	 * high / others active low)
@@ -523,6 +519,7 @@ static void __init omap3_beagle_init(void)
 
 	if (beagle_config.mmc1_gpio_wp != -EINVAL)
 		omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
+	mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
 	omap_hsmmc_init(mmc);
 
 	omap3_beagle_i2c_init();
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 6b77ad9..4bc86d9 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -315,9 +315,9 @@ static struct omap2_hsmmc_info mmc[] = {
 	{
 		.mmc		= 1,
 		.caps		= MMC_CAP_4_BIT_DATA,
-		.gpio_cd	= -EINVAL,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
 		.gpio_wp	= 63,
-		.deferred	= true,
 	},
 #ifdef CONFIG_WL12XX_PLATFORM_DATA
 	{
@@ -361,10 +361,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
 {
 	int r, lcd_bl_en;
 
-	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
-	mmc[0].gpio_cd = gpio + 0;
-	omap_hsmmc_late_init(mmc);
-
 	/*
 	 * Most GPIOs are for USB OTG.  Some are mostly sent to
 	 * the P2 connector; notably LEDA for the LCD backlight.
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index ace466b..b387264 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -270,19 +270,19 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
 	{
 		.mmc		= 1,
 		.caps		= MMC_CAP_4_BIT_DATA,
-		.gpio_cd	= -EINVAL,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
 		.gpio_wp	= 126,
 		.ext_clock	= 0,
-		.deferred	= true,
 	},
 	{
 		.mmc		= 2,
 		.caps		= MMC_CAP_4_BIT_DATA,
-		.gpio_cd	= -EINVAL,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
 		.gpio_wp	= 127,
 		.ext_clock	= 1,
 		.transceiver	= true,
-		.deferred	= true,
 	},
 	{
 		.mmc		= 3,
@@ -299,11 +299,6 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
 {
 	int ret, gpio_32khz;
 
-	/* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */
-	omap3pandora_mmc[0].gpio_cd = gpio + 0;
-	omap3pandora_mmc[1].gpio_cd = gpio + 1;
-	omap_hsmmc_late_init(omap3pandora_mmc);
-
 	/* gpio + 13 drives 32kHz buffer for wifi module */
 	gpio_32khz = gpio + 13;
 	ret = gpio_request_one(gpio_32khz, GPIOF_OUT_INIT_HIGH, "wifi 32kHz");
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 6410043..6d0deb9 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -211,9 +211,9 @@ static struct omap2_hsmmc_info mmc[] = {
 	{
 		.mmc		= 1,
 		.caps		= MMC_CAP_4_BIT_DATA,
-		.gpio_cd	= -EINVAL,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
 		.gpio_wp	= 23,
-		.deferred	= true,
 	 },
 	{}			/* Terminator */
 };
@@ -282,10 +282,6 @@ static int
 omap3stalker_twl_gpio_setup(struct device *dev,
 			    unsigned gpio, unsigned ngpio)
 {
-	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
-	mmc[0].gpio_cd = gpio + 0;
-	omap_hsmmc_late_init(mmc);
-
 	/*
 	 * Most GPIOs are for USB OTG.  Some are mostly sent to
 	 * the P2 connector; notably LEDA for the LCD backlight.
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 8842e04..cf270b8 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -99,8 +99,9 @@ static struct omap2_hsmmc_info mmc[] = {
 	{
 		.mmc		= 1,
 		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
 		.gpio_wp	= 29,
-		.deferred	= true,
 	},
 	{}	/* Terminator */
 };
@@ -118,10 +119,6 @@ static struct gpio_led gpio_leds[];
 static int touchbook_twl_gpio_setup(struct device *dev,
 		unsigned gpio, unsigned ngpio)
 {
-	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
-	mmc[0].gpio_cd = gpio + 0;
-	omap_hsmmc_late_init(mmc);
-
 	/* REVISIT: need ehci-omap hooks for external VBUS
 	 * power switch and overcurrent detect
 	 */
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 3d39cdb..604df86 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -203,9 +203,10 @@ static struct omap2_hsmmc_info mmc[] = {
 		.name		= "external",
 		.mmc		= 1,
 		.caps		= MMC_CAP_4_BIT_DATA,
+		.gpiochip_cd	= "twl4030_gpio",
+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
 		.gpio_wp	= -EINVAL,
 		.power_saving	= true,
-		.deferred	= true,
 	},
 	{
 		.name		= "internal",
@@ -232,10 +233,6 @@ static int zoom_twl_gpio_setup(struct device *dev,
 {
 	int ret;
 
-	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
-	mmc[0].gpio_cd = gpio + 0;
-	omap_hsmmc_late_init(mmc);
-
 	ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
 			       "lcd enable");
 	if (ret)



From tony at atomide.com  Thu Mar  1 13:55:28 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 01 Mar 2012 10:55:28 -0800
Subject: [PATCH 2/4] mmc: omap_hsmmc: Use gpio_find_by_chip_name() for
 omap_hsmmc_gpio_init()
In-Reply-To: <20120301185044.29210.44521.stgit@kaulin.local>
References: <20120301185044.29210.44521.stgit@kaulin.local>
Message-ID: <20120301185528.29210.85854.stgit@kaulin.local>

Use gpio_find_by_chip_name() to find the GPIO pins as they can
be dynamically allocated on various gpio_chips.

Note that we don't want to touch the platform data as it can
now specify the GPIO offset on a named gpio_chip.

This removes the need to use callbacks to set the GPIO pins
in platform data.

Cc: Chris Ball <cjb at laptop.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/hsmmc.c           |    3 +
 arch/arm/mach-omap2/hsmmc.h           |    5 ++
 arch/arm/plat-omap/include/plat/mmc.h |    3 +
 drivers/gpio/gpio-twl4030.c           |    2 +
 drivers/mmc/host/omap_hsmmc.c         |  109 +++++++++++++++++++++------------
 5 files changed, 82 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index a97876d..dda88f7 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -323,7 +323,10 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 
 	mmc->get_context_loss_count = hsmmc_get_context_loss;
 
+	mmc->slots[0].gpiochip_cd = c->gpiochip_cd;
 	mmc->slots[0].switch_pin = c->gpio_cd;
+
+	mmc->slots[0].gpiochip_wp = c->gpiochip_wp;
 	mmc->slots[0].gpio_wp = c->gpio_wp;
 
 	mmc->slots[0].remux = c->remux;
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index 07831cc..ffbb78d 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -22,8 +22,13 @@ struct omap2_hsmmc_info {
 	bool	no_off_init;	/* no power off when not in MMC sleep state */
 	bool	vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */
 	bool	deferred;	/* mmc needs a deferred probe */
+
+	char	*gpiochip_cd;	/* Optional gpiochip for gpio_cd */
 	int	gpio_cd;	/* or -EINVAL */
+
+	char	*gpiochip_wp;	/* Optional gpiochip for gpio_wp */
 	int	gpio_wp;	/* or -EINVAL */
+
 	char	*name;		/* or NULL for default */
 	struct platform_device *pdev;	/* mmc controller instance */
 	int	ocr_mask;	/* temporary HACK */
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index f75946c..cbfbdc3 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -130,7 +130,10 @@ struct omap_mmc_platform_data {
 #define HSMMC_HAS_UPDATED_RESET	(1 << 1)
 		unsigned features;
 
+		char *gpiochip_cd;		/* optional gpiochip for card detect */
 		int switch_pin;			/* gpio (card detect) */
+
+		char *gpiochip_wp;		/* optional gpiochip for write protect */
 		int gpio_wp;			/* gpio (write protect) */
 
 		int (*set_bus_mode)(struct device *dev, int slot, int bus_mode);
diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index b8b4f22..d0f266c 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -391,6 +391,7 @@ static int __devinit gpio_twl4030_debounce(u32 debounce, u8 mmc_cd)
 }
 
 static int gpio_twl4030_remove(struct platform_device *pdev);
+static struct platform_driver gpio_twl4030_driver;
 
 static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
 {
@@ -430,6 +431,7 @@ no_irqs:
 				pdata->debounce, pdata->mmc_cd,
 				ret);
 
+	twl_gpiochip.label = gpio_twl4030_driver.driver.name;
 	twl_gpiochip.base = pdata->gpio_base;
 	twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
 	twl_gpiochip.dev = &pdev->dev;
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index fd0c661..1aa2420 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -176,6 +176,8 @@ struct omap_hsmmc_host {
 	int			use_dma, dma_ch;
 	int			dma_line_tx, dma_line_rx;
 	int			slot_id;
+	int			gpio_cd;
+	int			gpio_wp;
 	int			got_dbclk;
 	int			response_busy;
 	int			context_loss;
@@ -192,26 +194,29 @@ struct omap_hsmmc_host {
 
 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 {
-	struct omap_mmc_platform_data *mmc = dev->platform_data;
+	struct omap_hsmmc_host *host =
+		platform_get_drvdata(to_platform_device(dev));
 
 	/* NOTE: assumes card detect signal is active-low */
-	return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
+	return !gpio_get_value_cansleep(host->gpio_cd);
 }
 
 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 {
-	struct omap_mmc_platform_data *mmc = dev->platform_data;
+	struct omap_hsmmc_host *host =
+		platform_get_drvdata(to_platform_device(dev));
 
 	/* NOTE: assumes write protect signal is active-high */
-	return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
+	return gpio_get_value_cansleep(host->gpio_wp);
 }
 
 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 {
-	struct omap_mmc_platform_data *mmc = dev->platform_data;
+	struct omap_hsmmc_host *host =
+		platform_get_drvdata(to_platform_device(dev));
 
 	/* NOTE: assumes card detect signal is active-low */
-	return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
+	return !gpio_get_value_cansleep(host->gpio_cd);
 }
 
 #ifdef CONFIG_PM
@@ -497,55 +502,80 @@ static inline int omap_hsmmc_have_reg(void)
 
 #endif
 
-static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
+static int omap_hsmmc_gpio_init(struct omap_hsmmc_host *host)
 {
-	int ret;
-
-	if (gpio_is_valid(pdata->slots[0].switch_pin)) {
-		if (pdata->slots[0].cover)
-			pdata->slots[0].get_cover_state =
+	struct omap_mmc_platform_data *pdata = host->pdata;
+	struct omap_mmc_slot_data *slot = &pdata->slots[0];
+	int gpio, ret;
+
+	gpio = slot->switch_pin;
+	if (slot->gpiochip_cd)
+		gpio = gpio_find_by_chip_name(slot->gpiochip_cd, gpio);
+	if (gpio_is_valid(gpio)) {
+		if (slot->cover)
+			slot->get_cover_state =
 					omap_hsmmc_get_cover_state;
 		else
-			pdata->slots[0].card_detect = omap_hsmmc_card_detect;
-		pdata->slots[0].card_detect_irq =
-				gpio_to_irq(pdata->slots[0].switch_pin);
-		ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
+			slot->card_detect = omap_hsmmc_card_detect;
+		slot->card_detect_irq =
+				gpio_to_irq(gpio);
+		ret = gpio_request(gpio, "mmc_cd");
 		if (ret)
 			return ret;
-		ret = gpio_direction_input(pdata->slots[0].switch_pin);
+		ret = gpio_direction_input(gpio);
 		if (ret)
 			goto err_free_sp;
-	} else
-		pdata->slots[0].switch_pin = -EINVAL;
+		host->gpio_cd = gpio;
+	} else {
+		if (slot->gpiochip_cd) {
+			pr_warning("MMC %s card detect GPIO chip %s unavailable\n",
+				slot->name, slot->gpiochip_cd);
+			ret = -ENODEV;
+			goto err_free_sp;
+		}
+		host->gpio_cd = -EINVAL;
+	}
 
-	if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
-		pdata->slots[0].get_ro = omap_hsmmc_get_wp;
-		ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
+	gpio = slot->gpio_wp;
+	if (slot->gpiochip_wp)
+		gpio = gpio_find_by_chip_name(slot->gpiochip_wp, gpio);
+	if (gpio_is_valid(gpio)) {
+		slot->get_ro = omap_hsmmc_get_wp;
+		ret = gpio_request(gpio, "mmc_wp");
 		if (ret)
 			goto err_free_cd;
-		ret = gpio_direction_input(pdata->slots[0].gpio_wp);
+		ret = gpio_direction_input(gpio);
 		if (ret)
 			goto err_free_wp;
-	} else
-		pdata->slots[0].gpio_wp = -EINVAL;
+		host->gpio_wp = gpio;
+	} else {
+		if (slot->gpiochip_wp) {
+			pr_warning("MMC %s write protect GPIO chip %s unavailable\n",
+				slot->name, slot->gpiochip_wp);
+			ret = -ENODEV;
+			goto err_free_wp;
+		}
+		host->gpio_wp = -EINVAL;
+	}
 
 	return 0;
 
 err_free_wp:
-	gpio_free(pdata->slots[0].gpio_wp);
+	if (gpio_is_valid(host->gpio_wp))
+		gpio_free(host->gpio_wp);
 err_free_cd:
-	if (gpio_is_valid(pdata->slots[0].switch_pin))
+	if (gpio_is_valid(host->gpio_cd))
 err_free_sp:
-		gpio_free(pdata->slots[0].switch_pin);
+		gpio_free(host->gpio_cd);
 	return ret;
 }
 
-static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
+static void omap_hsmmc_gpio_free(struct omap_hsmmc_host *host)
 {
-	if (gpio_is_valid(pdata->slots[0].gpio_wp))
-		gpio_free(pdata->slots[0].gpio_wp);
-	if (gpio_is_valid(pdata->slots[0].switch_pin))
-		gpio_free(pdata->slots[0].switch_pin);
+	if (gpio_is_valid(host->gpio_wp))
+		gpio_free(host->gpio_wp);
+	if (gpio_is_valid(host->gpio_cd))
+		gpio_free(host->gpio_cd);
 }
 
 /*
@@ -1876,10 +1906,6 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
 	if (res == NULL)
 		return -EBUSY;
 
-	ret = omap_hsmmc_gpio_init(pdata);
-	if (ret)
-		goto err;
-
 	mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
 	if (!mmc) {
 		ret = -ENOMEM;
@@ -1903,6 +1929,10 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, host);
 
+	ret = omap_hsmmc_gpio_init(host);
+	if (ret)
+		goto err1;
+
 	mmc->ops	= &omap_hsmmc_ops;
 
 	/*
@@ -2093,8 +2123,7 @@ err1:
 	platform_set_drvdata(pdev, NULL);
 	mmc_free_host(mmc);
 err_alloc:
-	omap_hsmmc_gpio_free(pdata);
-err:
+	omap_hsmmc_gpio_free(host);
 	release_mem_region(res->start, resource_size(res));
 	return ret;
 }
@@ -2125,7 +2154,7 @@ static int omap_hsmmc_remove(struct platform_device *pdev)
 
 		mmc_free_host(host->mmc);
 		iounmap(host->base);
-		omap_hsmmc_gpio_free(pdev->dev.platform_data);
+		omap_hsmmc_gpio_free(host);
 	}
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);



From tony at atomide.com  Thu Mar  1 13:55:35 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 01 Mar 2012 10:55:35 -0800
Subject: [PATCH 4/4] mmc: omap_hsmmc: Simplify init for twl6030 MMC card detect
In-Reply-To: <20120301185044.29210.44521.stgit@kaulin.local>
References: <20120301185044.29210.44521.stgit@kaulin.local>
Message-ID: <20120301185535.29210.71546.stgit@kaulin.local>

There's no need to use callbacks for this, we can
do it directly between MMC driver and twl6030.

Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Chris Ball <cjb at laptop.org>
Cc: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-4430sdp.c    |   45 +---------------------------
 arch/arm/mach-omap2/board-omap4panda.c |   52 +-------------------------------
 drivers/mfd/twl6030-irq.c              |   33 +++++++++-----------
 drivers/mmc/host/omap_hsmmc.c          |   31 +++++++++++++++++++
 4 files changed, 48 insertions(+), 113 deletions(-)

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 09ae257..c31efa4 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -455,49 +455,6 @@ static struct platform_device omap_vwlan_device = {
 	},
 };
 
-static int omap4_twl6030_hsmmc_late_init(struct device *dev)
-{
-	int ret = 0;
-	struct platform_device *pdev = container_of(dev,
-				struct platform_device, dev);
-	struct omap_mmc_platform_data *pdata = dev->platform_data;
-
-	/* Setting MMC1 Card detect Irq */
-	if (pdev->id == 0) {
-		ret = twl6030_mmc_card_detect_config();
-		if (ret)
-			pr_err("Failed configuring MMC1 card detect\n");
-		pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE +
-						MMCDETECT_INTR_OFFSET;
-		pdata->slots[0].card_detect = twl6030_mmc_card_detect;
-	}
-	return ret;
-}
-
-static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
-{
-	struct omap_mmc_platform_data *pdata;
-
-	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
-	if (!dev) {
-		pr_err("Failed %s\n", __func__);
-		return;
-	}
-	pdata = dev->platform_data;
-	pdata->init =	omap4_twl6030_hsmmc_late_init;
-}
-
-static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
-{
-	struct omap2_hsmmc_info *c;
-
-	omap_hsmmc_init(controllers);
-	for (c = controllers; c->mmc; c++)
-		omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
-
-	return 0;
-}
-
 static struct regulator_init_data sdp4430_vaux1 = {
 	.constraints = {
 		.min_uV			= 1000000,
@@ -906,7 +863,7 @@ static void __init omap_4430sdp_init(void)
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
 	omap4_sdp4430_wifi_init();
-	omap4_twl6030_hsmmc_init(mmc);
+	omap_hsmmc_init(mmc);
 
 	usb_musb_init(&musb_board_data);
 
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 7ca7a5c..8cf4e54 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -153,8 +153,8 @@ static struct omap2_hsmmc_info mmc[] = {
 	{
 		.mmc		= 1,
 		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-		.gpio_wp	= -EINVAL,
 		.gpio_cd	= -EINVAL,
+		.gpio_wp	= -EINVAL,
 	},
 	{
 		.name		= "wl1271",
@@ -204,54 +204,6 @@ struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
 	.board_ref_clock = 2,
 };
 
-static int omap4_twl6030_hsmmc_late_init(struct device *dev)
-{
-	int ret = 0;
-	struct platform_device *pdev = container_of(dev,
-				struct platform_device, dev);
-	struct omap_mmc_platform_data *pdata = dev->platform_data;
-
-	if (!pdata) {
-		dev_err(dev, "%s: NULL platform data\n", __func__);
-		return -EINVAL;
-	}
-	/* Setting MMC1 Card detect Irq */
-	if (pdev->id == 0) {
-		ret = twl6030_mmc_card_detect_config();
-		 if (ret)
-			dev_err(dev, "%s: Error card detect config(%d)\n",
-				__func__, ret);
-		 else
-			pdata->slots[0].card_detect = twl6030_mmc_card_detect;
-	}
-	return ret;
-}
-
-static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
-{
-	struct omap_mmc_platform_data *pdata;
-
-	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
-	if (!dev) {
-		pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n");
-		return;
-	}
-	pdata = dev->platform_data;
-
-	pdata->init =	omap4_twl6030_hsmmc_late_init;
-}
-
-static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
-{
-	struct omap2_hsmmc_info *c;
-
-	omap_hsmmc_init(controllers);
-	for (c = controllers; c->mmc; c++)
-		omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
-
-	return 0;
-}
-
 /* Panda board uses the common PMIC configuration */
 static struct twl4030_platform_data omap4_panda_twldata;
 
@@ -503,7 +455,7 @@ static void __init omap4_panda_init(void)
 	platform_device_register(&omap_vwlan_device);
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
-	omap4_twl6030_hsmmc_init(mmc);
+	omap_hsmmc_init(mmc);
 	omap4_ehci_init();
 	usb_musb_init(&musb_board_data);
 	omap4_panda_display_init();
diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
index c6b456a..ce0002b 100644
--- a/drivers/mfd/twl6030-irq.c
+++ b/drivers/mfd/twl6030-irq.c
@@ -283,35 +283,30 @@ int twl6030_mmc_card_detect_config(void)
 	 * Card status on TWL6030 for MMC1
 	 */
 	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
-	if (ret < 0) {
-		pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
-		return ret;
-	}
+	if (ret < 0)
+		goto err;
 	reg_val &= ~VMMC_AUTO_OFF;
 	reg_val |= SW_FC;
 	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
-	if (ret < 0) {
-		pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
-		return ret;
-	}
+	if (ret < 0)
+		goto err;
 
 	/* Configuring PullUp-PullDown register */
 	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
 						TWL6030_CFG_INPUT_PUPD3);
-	if (ret < 0) {
-		pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
-									ret);
-		return ret;
-	}
+	if (ret < 0)
+		goto err;
 	reg_val &= ~(MMC_PU | MMC_PD);
 	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
 						TWL6030_CFG_INPUT_PUPD3);
-	if (ret < 0) {
-		pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
-									ret);
-		return ret;
-	}
-	return 0;
+	if (ret < 0)
+		goto err;
+
+	return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
+
+err:
+	pr_err("twl6030: Failed to initialize MMC card detect: %d\n", ret);
+	return -ENODEV;
 }
 EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
 
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 1aa2420..7f483b7 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -34,6 +34,7 @@
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
 #include <linux/pm_runtime.h>
+#include <linux/i2c/twl.h>
 #include <plat/dma.h>
 #include <mach/hardware.h>
 #include <plat/board.h>
@@ -578,6 +579,32 @@ static void omap_hsmmc_gpio_free(struct omap_hsmmc_host *host)
 		gpio_free(host->gpio_cd);
 }
 
+#ifdef CONFIG_TWL4030_CORE
+static int omap_hsmmc_init_twl6030(struct omap_hsmmc_host *host)
+{
+	struct omap_mmc_platform_data *pdata = host->pdata;
+	struct omap_mmc_slot_data *slot = &pdata->slots[0];
+	int irq;
+
+	if (gpio_is_valid(host->gpio_cd) || host->id)
+		return 0;
+
+	irq = twl6030_mmc_card_detect_config();
+	if (irq <= 0)
+		return irq;
+
+	slot->card_detect_irq = irq;
+	slot->card_detect = twl6030_mmc_card_detect;
+
+	return 0;
+}
+#else
+static inline int omap_hsmmc_init_twl6030(struct omap_hsmmc_host *host)
+{
+	return -ENODEV;
+}
+#endif
+
 /*
  * Start clock to the card
  */
@@ -1933,6 +1960,10 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
 	if (ret)
 		goto err1;
 
+	ret = omap_hsmmc_init_twl6030(host);
+	if (ret)
+		goto err1;
+
 	mmc->ops	= &omap_hsmmc_ops;
 
 	/*



From tony at atomide.com  Thu Mar  1 13:58:54 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 1 Mar 2012 10:58:54 -0800
Subject: [PATCH 5/6] ARM: OMAP3: Modify omap_hsmmc_late_init to handle
 deleting mmc devices
In-Reply-To: <4F48677E.30803@ti.com>
References: <1330077537-19618-1-git-send-email-rnayak@ti.com>
 <1330077537-19618-6-git-send-email-rnayak@ti.com>
 <20120225003352.GC18901@atomide.com> <4F48677E.30803@ti.com>
Message-ID: <20120301185854.GA18901@atomide.com>

* Rajendra Nayak <rnayak at ti.com> [120224 20:14]:
> On Saturday 25 February 2012 06:03 AM, Tony Lindgren wrote:
> >Hi,
> >
> >* Rajendra Nayak<rnayak at ti.com>  [120224 01:27]:
> >>omap_hsmmc_late_init() adds deferred (if any) mmc devices which are
> >>dependent on twl4030-gpio device to be available.
> >>If twl4030-gpio is built as a module and inserted and deleted multiple
> >>times, the mmc devices also should be added and deleted accordingly.
> >>Split omap_hsmmc_late_init() into omap_hsmmc_deferred_add() and
> >>omap_hsmmc_deferred_del() to handle this.
> >>The .setup board hook for twl4030-gpio handles the runtime adding
> >>on deferred mmc devices. Similarly a .teardown board hook for twl4030-gpio
> >>should handle the runtime deletion by calling omap_hsmmc_deferred_del().
> >>This is done for all existing omap3 boards in subsequent patches.
> >
> >This gets complex.. But I think I've found a simpler way where we
> >can use the twl gpio offsets and let the drivers take care of the rest.
> >I'll post some patches hopefully on Monday.
> 
> I agree it gets complex. If you have a simpler way to handle this, that
> would be great.

Posted now, sorry it too a bit longer, I got distracted with other
stuff. The thread is "[PATCH 0/4] Start getting rid of pdata callbacks
with gpio_find_by_chip_name()". Some further testing would be
appreciated.

Regards,

Tony


From arnd at arndb.de  Thu Mar  1 13:25:43 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 18:25:43 +0000
Subject: [PATCH v2 19/28] ARM: Add fixed PCI i/o mapping
In-Reply-To: <20120301140817.GG7363@n2100.arm.linux.org.uk>
References: <1330547147-22867-1-git-send-email-robherring2@gmail.com>
 <201203011352.36067.arnd@arndb.de>
 <20120301140817.GG7363@n2100.arm.linux.org.uk>
Message-ID: <201203011825.44049.arnd@arndb.de>

On Thursday 01 March 2012, Russell King - ARM Linux wrote:
> On Thu, Mar 01, 2012 at 01:52:35PM +0000, Arnd Bergmann wrote:
> > Ok. I've looked up the manual for IOP134x and it's very clear there that
> > it has only two 64k I/O windows but no more (developer manual, sections
> > 2.2.2.1 and 3.3.2.1). Limiting the virtual space to 64k would result in
> > seeing only one of the buses, but 1 MB is enough if we map both buses
> > in there.
> 
> I think it was the 80312, and the manual does limit the window to 64k.

I can't see where we suport that one in Linux, was it removed at some
point? I also can't find any documentation for it on the web.

This makes it hard to figure out now what exactly the problem was,
but at least we don't have to worry about breaking that machine now.

The iop variants in the kernel today only map 64kb of I/O window
today, so I can't see how we would regress.
That leaves us still with Kirkwood/Dove and ixp2000 to figure out.

I can imagine that ixp2000 has a similar problem to the one you describe
because of the way it uses the second 64kb in the resource instead of
the first 64kb. I would suggest that for ixp2000 we just make the first
1MB of of the 32MB window, which covers the 64kb resource and more.
I've checked that none of the ixp2000 specific drivers use PC-style
I/O anywhere outside of PCI and that the only IO resource that is
registered is the one for the PCI bus, so I'm rather optimistic about this
one.

For Kirkwood and Dove, an easy way out would be to extend the I/O
space window to 2MB right away and just map both as before, but we
can also try just using the two lower 64k windows in each and see what
breaks, as those seem to be widely available for testing still.

	Arnd


From alan at signal11.us  Thu Mar  1 14:26:42 2012
From: alan at signal11.us (Alan Ott)
Date: Thu,  1 Mar 2012 14:26:42 -0500
Subject: [PATCH 0/8] ARM: Tegra: cleanup patches from Arnd Bergmann
Message-ID: <1330630010-11241-1-git-send-email-alan@signal11.us>

Hello,

I'm helping Arnd Bergmann get some of his cleanup patches upstream. This
set covers the Tegra.

Thanks,

Alan.

Arnd Bergmann (8):
  ARM: tegra: export tegra_gpio_{en,dis}able
  ARM: tegra: do not hide dma declarations
  ARM: tegra: select CPU_FREQ_TABLE
  ARM: tegra: build localtimer support only when needed
  ARM: tegra: work around tegra THUMB2_KERNEL bug
  ARM: tegra: USB_ULPI needs USB
  ARM: tegra: export usb phy symbols
  ARM: tegra: HACK: remove set_irq_flags() from driver

 arch/arm/Kconfig                       |    1 +
 arch/arm/mach-tegra/Kconfig            |    2 ++
 arch/arm/mach-tegra/Makefile           |    3 ++-
 arch/arm/mach-tegra/include/mach/dma.h |    4 ----
 arch/arm/mach-tegra/usb_phy.c          |   10 ++++++++++
 drivers/gpio/gpio-tegra.c              |    2 ++
 drivers/usb/host/ehci-tegra.c          |    1 -
 7 files changed, 17 insertions(+), 6 deletions(-)



From alan at signal11.us  Thu Mar  1 14:26:43 2012
From: alan at signal11.us (Alan Ott)
Date: Thu,  1 Mar 2012 14:26:43 -0500
Subject: [PATCH 1/8] ARM: tegra: export tegra_gpio_{en,dis}able
In-Reply-To: <1330630010-11241-1-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
Message-ID: <1330630010-11241-2-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

These two functions are used in drivers that can be
modules, so they need to be exported.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/gpio/gpio-tegra.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index bdc2937..96662cc 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -107,11 +107,13 @@ void tegra_gpio_enable(int gpio)
 {
 	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 }
+EXPORT_SYMBOL_GPL(tegra_gpio_enable);
 
 void tegra_gpio_disable(int gpio)
 {
 	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 }
+EXPORT_SYMBOL_GPL(tegra_gpio_disable);
 
 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-- 
1.7.0.4



From alan at signal11.us  Thu Mar  1 14:26:44 2012
From: alan at signal11.us (Alan Ott)
Date: Thu,  1 Mar 2012 14:26:44 -0500
Subject: [PATCH 2/8] ARM: tegra: do not hide dma declarations
In-Reply-To: <1330630010-11241-1-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
Message-ID: <1330630010-11241-3-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The declarations are actually required for the device
definitions, and are still valid even if the dma controller
is disabled:

arch/arm/mach-tegra/devices.c:559:12: error: 'TEGRA_DMA_REQ_SEL_I2S_1' undeclared here (not in a function)
arch/arm/mach-tegra/devices.c:577:12: error: 'TEGRA_DMA_REQ_SEL_I2S2_1' undeclared here (not in a function)

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-tegra/include/mach/dma.h |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 3c93390..9077092 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -51,8 +51,6 @@
 #define TEGRA_DMA_REQ_SEL_OWR			25
 #define TEGRA_DMA_REQ_SEL_INVALID		31
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-
 struct tegra_dma_req;
 struct tegra_dma_channel;
 
@@ -151,5 +149,3 @@ void tegra_dma_free_channel(struct tegra_dma_channel *ch);
 int __init tegra_dma_init(void);
 
 #endif
-
-#endif
-- 
1.7.0.4



From alan at signal11.us  Thu Mar  1 14:26:45 2012
From: alan at signal11.us (Alan Ott)
Date: Thu,  1 Mar 2012 14:26:45 -0500
Subject: [PATCH 3/8] ARM: tegra: select CPU_FREQ_TABLE
In-Reply-To: <1330630010-11241-1-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
Message-ID: <1330630010-11241-4-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The tegra cpufreq implementation relies on the cpu_freq_table
code, so make sure that this is always there when needed.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-tegra/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 373652d..b2a038e 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -10,6 +10,7 @@ config ARCH_TEGRA_2x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
+	select CPU_FREQ_TABLE if CPU_FREQ
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
-- 
1.7.0.4



From alan at signal11.us  Thu Mar  1 14:26:46 2012
From: alan at signal11.us (Alan Ott)
Date: Thu,  1 Mar 2012 14:26:46 -0500
Subject: [PATCH 4/8] ARM: tegra: build localtimer support only when needed
In-Reply-To: <1330630010-11241-1-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
Message-ID: <1330630010-11241-5-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

It is possible to build a tegra kernel without localtimer
support, so the tegra specific parts should only be built
when that is indeed enabled.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-tegra/Makefile |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e120ff5..a956df8 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -13,7 +13,8 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-tegra20-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= pinmux-tegra30-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
-obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
+obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
+obj-$(CONFIG_LOCAL_TIMERS)		+= localtimer.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_SYSTEM_DMA)		+= dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
-- 
1.7.0.4



From alan at signal11.us  Thu Mar  1 14:26:47 2012
From: alan at signal11.us (Alan Ott)
Date: Thu,  1 Mar 2012 14:26:47 -0500
Subject: [PATCH 5/8] ARM: tegra: work around tegra THUMB2_KERNEL bug
In-Reply-To: <1330630010-11241-1-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
Message-ID: <1330630010-11241-6-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The tegra smp code cannot currently be built for t2, so
disable that combination for now, as a workaround.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a48aecc..ea1d59b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1598,6 +1598,7 @@ config HZ
 config THUMB2_KERNEL
 	bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
 	depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
+	depends on !SMP || !ARCH_TEGRA
 	select AEABI
 	select ARM_ASM_UNIFIED
 	select ARM_UNWIND
-- 
1.7.0.4



From alan at signal11.us  Thu Mar  1 14:26:48 2012
From: alan at signal11.us (Alan Ott)
Date: Thu,  1 Mar 2012 14:26:48 -0500
Subject: [PATCH 6/8] ARM: tegra: USB_ULPI needs USB
In-Reply-To: <1330630010-11241-1-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
Message-ID: <1330630010-11241-7-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The USB_ULPI driver is selected by tegra, but can only be
built if at least one of USB or USB_GADGET is enabled.
The kernel fails to link if both are off.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-tegra/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index b2a038e..7ac3011 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -10,6 +10,7 @@ config ARCH_TEGRA_2x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
+	select USB_GADGET if USB_SUPPORT && !USB
 	select CPU_FREQ_TABLE if CPU_FREQ
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
-- 
1.7.0.4



From alan at signal11.us  Thu Mar  1 14:26:49 2012
From: alan at signal11.us (Alan Ott)
Date: Thu,  1 Mar 2012 14:26:49 -0500
Subject: [PATCH 7/8] ARM: tegra: export usb phy symbols
In-Reply-To: <1330630010-11241-1-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
Message-ID: <1330630010-11241-8-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The ehci driver can be a module, so the functions provided
by the tegra platform code used by ehci-tegra need to
be exported.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-tegra/usb_phy.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index 37576a7..3c45264 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -730,6 +730,7 @@ err0:
 	kfree(phy);
 	return ERR_PTR(err);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
 
 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 {
@@ -738,6 +739,7 @@ int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 	else
 		return utmi_phy_power_on(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on);
 
 void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 {
@@ -746,18 +748,21 @@ void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 	else
 		utmi_phy_power_off(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off);
 
 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_preresume(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 
 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_postresume(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 
 void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
 				 enum tegra_usb_phy_port_speed port_speed)
@@ -765,24 +770,28 @@ void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
 	if (!phy_is_ulpi(phy))
 		utmi_phy_restore_start(phy, port_speed);
 }
+EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 
 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_restore_end(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 
 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_clk_disable(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
 
 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_clk_enable(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
 
 void tegra_usb_phy_close(struct tegra_usb_phy *phy)
 {
@@ -794,3 +803,4 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
 	clk_put(phy->pll_u);
 	kfree(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_close);
-- 
1.7.0.4



From alan at signal11.us  Thu Mar  1 14:26:50 2012
From: alan at signal11.us (Alan Ott)
Date: Thu,  1 Mar 2012 14:26:50 -0500
Subject: [PATCH 8/8] ARM: tegra: HACK: remove set_irq_flags() from driver
In-Reply-To: <1330630010-11241-1-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
Message-ID: <1330630010-11241-9-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The driver should not call set_irq_flags itself, and
cannot do this from a loadable module.

Remove the call for now, which might break the driver
but at least lets the kernel link again.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 drivers/usb/host/ehci-tegra.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index dbc7fe8..ab91f26 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -729,7 +729,6 @@ static int tegra_ehci_probe(struct platform_device *pdev)
 		err = -ENODEV;
 		goto fail;
 	}
-	set_irq_flags(irq, IRQF_VALID);
 
 #ifdef CONFIG_USB_OTG_UTILS
 	if (pdata->operating_mode == TEGRA_USB_OTG) {
-- 
1.7.0.4



From arnd at arndb.de  Thu Mar  1 14:35:58 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 19:35:58 +0000
Subject: [PATCH 3/4] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>
Message-ID: <201203011935.58503.arnd@arndb.de>

On Thursday 01 March 2012, Jason Cooper wrote:
> The comment at mach-kirkwood/common.c:469, says this device is in every
> kirkwood board.  So, it is placed in kirkwood.dtsi.
>
> @@ -218,10 +220,15 @@ static int __devinit mv_rtc_probe(struct platform_device *pdev)
>  {
>  	struct resource *res;
>  	struct rtc_plat_data *pdata;
> +	struct device_node *np = pdev->dev.of_node;
>  	resource_size_t size;
>  	u32 rtc_time;
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> +	if (np)
> +		of_address_to_resource(np, 0, res);
> +
>  	if (!res)
>  		return -ENODEV;
>  
> @@ -257,6 +264,8 @@ static int __devinit mv_rtc_probe(struct platform_device *pdev)
>  
>  	pdata->irq = platform_get_irq(pdev, 0);
>  
> +	of_property_read_u32(np, "interrupts", &pdata->irq);
> +
>  	platform_set_drvdata(pdev, pdata);
>  
>  	if (pdata->irq >= 0) {

The two additions here don't seem necessary, the second one not even
correct: Any interrupts and register properties automatically get
turned into platform resources when the device is instatiated.

The interrupt number should not be taken verbatim from the device tree
because it is always local to the "interrupt-parent" node, so you would
have to use irq_of_parse_and map rather than reading the property
directly, but as I said you don't even need to do that for platform
devices.

	Arnd


From gregkh at linuxfoundation.org  Thu Mar  1 14:36:43 2012
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Thu, 1 Mar 2012 11:36:43 -0800
Subject: [PATCH 8/8] ARM: tegra: HACK: remove set_irq_flags() from driver
In-Reply-To: <1330630010-11241-9-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-9-git-send-email-alan@signal11.us>
Message-ID: <20120301193643.GA607@kroah.com>

On Thu, Mar 01, 2012 at 02:26:50PM -0500, Alan Ott wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The driver should not call set_irq_flags itself, and
> cannot do this from a loadable module.
> 
> Remove the call for now, which might break the driver
> but at least lets the kernel link again.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Um, I think you should test this out before submitting it anywhere :)

As it is, I can't accept it.

greg k-h


From veli-pekka.peltola at bluegiga.com  Thu Mar  1 14:45:19 2012
From: veli-pekka.peltola at bluegiga.com (Veli-Pekka Peltola)
Date: Thu,  1 Mar 2012 21:45:19 +0200
Subject: [PATCH] mm: module_alloc: check if size is 0
Message-ID: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com>

After commit de7d2b567d040e3b67fe7121945982f14343213d (mm/vmalloc.c: report
more vmalloc failures) users will get a warning if vmalloc_node_range() is
called with size 0. This happens if module's init size equals to 0. This
patch changes ARM, MIPS and x86 module_alloc() to return NULL before calling
vmalloc_node_range() that would also return NULL and print a warning.

Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola at bluegiga.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Ingo Molnar <mingo at redhat.com>
Cc: "H. Peter Anvin" <hpa at zytor.com>
Cc: x86 at kernel.org
---
I found this with ARM but after checking out various implementations of
module_alloc() I thought it would be better to fix all at once.

One way to replicate the warning:
compile kernel with CONFIG_KALLSYMS=n
insmod module without init, I used usb-common.ko

 arch/arm/kernel/module.c  |    4 ++--
 arch/mips/kernel/module.c |    4 ++--
 arch/x86/kernel/module.c  |    2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 1e9be5d..d44d212 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -39,8 +39,8 @@
 #ifdef CONFIG_MMU
 void *module_alloc(unsigned long size)
 {
-	return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
-				GFP_KERNEL, PAGE_KERNEL_EXEC, -1,
+	return size == 0 ? NULL : __vmalloc_node_range(size, 1, MODULES_VADDR,
+				MODULES_END, GFP_KERNEL, PAGE_KERNEL_EXEC, -1,
 				__builtin_return_address(0));
 }
 #endif
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index a5066b1..cd768e9 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -47,8 +47,8 @@ static DEFINE_SPINLOCK(dbe_lock);
 #ifdef MODULE_START
 void *module_alloc(unsigned long size)
 {
-	return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END,
-				GFP_KERNEL, PAGE_KERNEL, -1,
+	return size == 0 ? NULL : __vmalloc_node_range(size, 1, MODULE_START,
+				MODULE_END, GFP_KERNEL, PAGE_KERNEL, -1,
 				__builtin_return_address(0));
 }
 #endif
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index 925179f..bff6118 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -38,7 +38,7 @@
 
 void *module_alloc(unsigned long size)
 {
-	if (PAGE_ALIGN(size) > MODULES_LEN)
+	if (size == 0 || PAGE_ALIGN(size) > MODULES_LEN)
 		return NULL;
 	return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
 				GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL_EXEC,
-- 
1.7.5.4



From arnd at arndb.de  Thu Mar  1 14:48:51 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 19:48:51 +0000
Subject: [PATCH 4/4] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <2f29e88b98b2bcff0c241996e6d7216a60995d2d.1330625878.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2f29e88b98b2bcff0c241996e6d7216a60995d2d.1330625878.git.jason@lakedaemon.net>
Message-ID: <201203011948.51642.arnd@arndb.de>

On Thursday 01 March 2012, Jason Cooper wrote:
>  static int heartbeat = -1;             /* module parameter (seconds) */
>  static unsigned int wdt_max_duration;  /* (seconds) */
>  static unsigned int wdt_tclk;
> +static unsigned int wdt_reg;
>  static unsigned long wdt_status;
> static DEFINE_SPINLOCK(wdt_lock);

This variable needs to be a 'void __iomem *', not an int.

> +       wdt_reg = TIMER_VIRT_BASE;
> +
> +       of_property_read_u32(np, "reg", &wdt_reg);
> +
>         if (orion_wdt_miscdev.parent)
>                 return -EBUSY;
>         orion_wdt_miscdev.parent = &pdev->dev;

Don't just read a reg property, but use the resource instead and ioremap it.

This driver still uses hardcoded virtual addresses for its registers, which
we're trying to get rid of. The best solution would be to always put the
register address into the platform device resources, either hardcoded for
classic boards or automatic through the device tree.

A reg property is special in that it's not just a number but is relative
to the "ranges" property of the parent device and can be multiple 32 bit
values for the address, which get turned into a CPU physical address using
of_translate_address().

	Arnd


From arnd at arndb.de  Thu Mar  1 14:50:51 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 19:50:51 +0000
Subject: [PATCH 0/4] ARM: kirkwood: fdt: convert kirkwood init funcs to fdt
In-Reply-To: <cover.1330625877.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
Message-ID: <201203011950.51210.arnd@arndb.de>

On Thursday 01 March 2012, Jason Cooper wrote:
> This series begins the process of converting all of the drivers initialized
> from kirkwood_init() to devicetree.
> 
> The first patch cleans up kirkwood_init() by moving a flag setting to it's
> appropriate location.  This will help later when converting the audio driver.
> 
> Next, I pull the functionality of kirkwood_init() into kirkwood_dt_init() in
> board-dt.c  This way, as drivers are converted, their init calls can be removed
> from kirkwood_dt_init() and non-fdt users won't be affected (they call
> kirkwood_init()).
> 
> Last, I converted the two easiest drivers, rtc and wdt.  The xor and crypto
> drivers remain for a later patch series.

Hi Jason,

Nice patch series! I've commented on a few details that need improving, but
it seems you're making good progress overall. Note that in other platforms,
we typically focus on converting all the devices outside of the soc first,
because that lets us get away from board files faster, but there is nothing
wrong in principle in converting the devices on the soc as well.

	Arnd


From olof at lixom.net  Thu Mar  1 14:59:21 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 1 Mar 2012 11:59:21 -0800
Subject: [PATCH 1/8] ARM: tegra: export tegra_gpio_{en,dis}able
In-Reply-To: <1330630010-11241-2-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-2-git-send-email-alan@signal11.us>
Message-ID: <CAOesGMhom2ybsKKgezPKkrhH9NniZu+FMprQhibHwEX92MNtEQ@mail.gmail.com>

Hi,

On Thu, Mar 1, 2012 at 11:26 AM, Alan Ott <alan at signal11.us> wrote:
> From: Arnd Bergmann <arnd at arndb.de>
>
> These two functions are used in drivers that can be
> modules, so they need to be exported.
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

With some of the pinmux changes going in this will no longer be
needed, but it is for now so:

Acked-by: Olof Johansson <olof at lixom.net>


From jason at lakedaemon.net  Thu Mar  1 15:01:36 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 1 Mar 2012 15:01:36 -0500
Subject: [PATCH 0/4] ARM: kirkwood: fdt: convert kirkwood init funcs to fdt
In-Reply-To: <201203011950.51210.arnd@arndb.de>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203011950.51210.arnd@arndb.de>
Message-ID: <20120301200136.GA11986@titan.lakedaemon.net>

On Thu, Mar 01, 2012 at 07:50:51PM +0000, Arnd Bergmann wrote:
> On Thursday 01 March 2012, Jason Cooper wrote:
> > This series begins the process of converting all of the drivers initialized
> > from kirkwood_init() to devicetree.
> > 
> > The first patch cleans up kirkwood_init() by moving a flag setting to it's
> > appropriate location.  This will help later when converting the audio driver.
> > 
> > Next, I pull the functionality of kirkwood_init() into kirkwood_dt_init() in
> > board-dt.c  This way, as drivers are converted, their init calls can be removed
> > from kirkwood_dt_init() and non-fdt users won't be affected (they call
> > kirkwood_init()).
> > 
> > Last, I converted the two easiest drivers, rtc and wdt.  The xor and crypto
> > drivers remain for a later patch series.
> 
> Hi Jason,
> 
> Nice patch series! I've commented on a few details that need improving, but
> it seems you're making good progress overall. Note that in other platforms,
> we typically focus on converting all the devices outside of the soc first,
> because that lets us get away from board files faster, but there is nothing
> wrong in principle in converting the devices on the soc as well.

Thanks for the feedback.  I'll redo this series and resubmit.  Did you
catch my patch from yesterday?

[PATCH v3] ARM: kirkwood: covert orion-spi to fdt. [1]

thx,

Jason.

[1] http://www.spinics.net/lists/arm-kernel/msg161975.html
> 
> 	Arnd
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From swarren at nvidia.com  Thu Mar  1 15:02:42 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Thu, 1 Mar 2012 12:02:42 -0800
Subject: [PATCH 5/8] ARM: tegra: work around tegra THUMB2_KERNEL bug
In-Reply-To: <1330630010-11241-6-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-6-git-send-email-alan@signal11.us>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861726@HQMAIL01.nvidia.com>

Alan Ott wrote at Thursday, March 01, 2012 12:27 PM:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The tegra smp code cannot currently be built for t2, so
> disable that combination for now, as a workaround.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

At least in next-20120229 with the .config I'm using, everything appears
to compile fine. The link step does fail, but the error messages I get
don't appear to be Tegra specific:

xxx/kernel/sched/clock.c:334: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `sched_clock' defined in .text section in arch/arm/kernel/built-in.o
kernel/built-in.o: In function `post_relocation':
xxx/kernel/module.c:2860: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `module_finalize' defined in .text section in arch/arm/kernel/built-in.o
kernel/built-in.o: In function `show_interrupts':
xxx/kernel/irq/proc.c:431: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `arch_show_interrupts' defined in .text section in arch/arm/kernel/built-in.o
drivers/built-in.o: In function `pci_set_master':
xxx/drivers/pci/pci.c:2674: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `pcibios_set_master' defined in .text section in arch/arm/kernel/built-in.o

What failure does this solve, and how do I trigger it?

-- 
nvpublic



From olof at lixom.net  Thu Mar  1 15:05:37 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 1 Mar 2012 12:05:37 -0800
Subject: [PATCH 3/8] ARM: tegra: select CPU_FREQ_TABLE
In-Reply-To: <1330630010-11241-4-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-4-git-send-email-alan@signal11.us>
Message-ID: <CAOesGMiFbggUz6_GH-5htzFJuaXzeYhXpTfHafy-LSPAEmkQnw@mail.gmail.com>

Hi,

On Thu, Mar 1, 2012 at 11:26 AM, Alan Ott <alan at signal11.us> wrote:
> From: Arnd Bergmann <arnd at arndb.de>
>
> The tegra cpufreq implementation relies on the cpu_freq_table
> code, so make sure that this is always there when needed.
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
> ?arch/arm/mach-tegra/Kconfig | ? ?1 +
> ?1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> index 373652d..b2a038e 100644
> --- a/arch/arm/mach-tegra/Kconfig
> +++ b/arch/arm/mach-tegra/Kconfig
> @@ -10,6 +10,7 @@ config ARCH_TEGRA_2x_SOC
> ? ? ? ?select USB_ARCH_HAS_EHCI if USB_SUPPORT
> ? ? ? ?select USB_ULPI if USB_SUPPORT
> ? ? ? ?select USB_ULPI_VIEWPORT if USB_SUPPORT
> + ? ? ? select CPU_FREQ_TABLE if CPU_FREQ

The corresponding chance is needed for T30 as well.

(the cpufreq driver should probably be moved out to drivers/cpufreq
and given its own but that's a separate issue)


-Olof


From swarren at nvidia.com  Thu Mar  1 15:05:34 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Thu, 1 Mar 2012 12:05:34 -0800
Subject: [PATCH 6/8] ARM: tegra: USB_ULPI needs USB
In-Reply-To: <1330630010-11241-7-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-7-git-send-email-alan@signal11.us>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE86172C@HQMAIL01.nvidia.com>

Alan Ott wrote at Thursday, March 01, 2012 12:27 PM:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The USB_ULPI driver is selected by tegra, but can only be
> built if at least one of USB or USB_GADGET is enabled.
> The kernel fails to link if both are off.

> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
...
> @@ -10,6 +10,7 @@ config ARCH_TEGRA_2x_SOC
...
> +	select USB_GADGET if USB_SUPPORT && !USB

I don't believe the Tegra USB driver supports gadget mode at present.
Would the above be better written as:

    select USB if USB_SUPPORT

And I wonder if the Tegra EHCI driver shouldn't be doing some of these
selects, not the ARCH_TEGRA_* option.

And this is probably required for Tegra30 too not just Tegra20.

-- 
nvpublic



From arnd at arndb.de  Thu Mar  1 15:12:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 20:12:00 +0000
Subject: [PATCH 8/8] ARM: tegra: HACK: remove set_irq_flags() from driver
In-Reply-To: <20120301193643.GA607@kroah.com>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-9-git-send-email-alan@signal11.us>
 <20120301193643.GA607@kroah.com>
Message-ID: <201203012012.01266.arnd@arndb.de>

On Thursday 01 March 2012, Greg Kroah-Hartman wrote:
> On Thu, Mar 01, 2012 at 02:26:50PM -0500, Alan Ott wrote:
> > From: Arnd Bergmann <arnd at arndb.de>
> > 
> > The driver should not call set_irq_flags itself, and
> > cannot do this from a loadable module.
> > 
> > Remove the call for now, which might break the driver
> > but at least lets the kernel link again.
> > 
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> 
> Um, I think you should test this out before submitting it anywhere :)
> 
> As it is, I can't accept it.

Right, this one was not meant for inclusion, similar to patch 5 in this
series.

Alan:
Part of the reason I asked for help getting the patches out is that
they need a lot of auditing, both for whether they still apply to
current kernels and for whether they are a good solution to the problem
at hand. When in doubt, it's probably better to leave out any patch
that looks like it might not be ready for inclusion, or that might
make thinks uglier in some way.

	Arnd


From swarren at nvidia.com  Thu Mar  1 15:14:37 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Thu, 1 Mar 2012 12:14:37 -0800
Subject: [PATCH 7/8] ARM: tegra: export usb phy symbols
In-Reply-To: <1330630010-11241-8-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-8-git-send-email-alan@signal11.us>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861731@HQMAIL01.nvidia.com>

Alan Ott wrote at Thursday, March 01, 2012 12:27 PM:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The ehci driver can be a module, so the functions provided
> by the tegra platform code used by ehci-tegra need to
> be exported.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

I think this one need to add:

#include <linux/export.h>

In the relevant place.

-- 
nvpublic



From tony at atomide.com  Thu Mar  1 15:15:18 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 1 Mar 2012 12:15:18 -0800
Subject: linux-next: manual merge of the arm-soc tree with the gpio tree
In-Reply-To: <201203011228.33983.arnd@arndb.de>
References: <20120301164001.77a063ceed2deaf37cf68e3c@canb.auug.org.au>
 <201203011228.33983.arnd@arndb.de>
Message-ID: <20120301201518.GB18901@atomide.com>

* Arnd Bergmann <arnd at arndb.de> [120301 03:57]:
> On Thursday 01 March 2012, Stephen Rothwell wrote:
> > Today's linux-next merge of the arm-soc tree got conflicts in
> > arch/arm/mach-omap1/gpio16xx.c between commit ab985f0f7c2c ("gpio/omap:
> > cleanup omap_gpio_mod_init function") from the gpio tree and commit
> > 63325ff235de ("ARM: OMAP1: Move 16xx GPIO system clock to platform init
> > code") from the arm-soc tree.
> > 
> > OK, I can't decide which is correct here - the former adds this code
> > inside the loop (even though it seems to not depend on anything in the
> > loop) and the latter adds it before.  I have used the former (but am
> > happy to be corrected).  And both commits remove the code in
> > drivers/gpio/gpio-omap.c.
> 
> Right, having the code outside of the loop seems correct to me, too.
> 
> Grant, I would suggest that I resolve this by merging the the
> omap/gpio/runtime-pm-cleanup branch (f86bcc3) that is in your
> tree into the arm-soc tree as a dependency for the omap1 stuff,
> with the resolution below.

For gpio16xx.c the resolution is to use the version from ab985f0f7c2c,
so below looks good to me.

Regards,

Tony


> --- a/arch/arm/mach-omap1/gpio16xx.c
> +++ b/arch/arm/mach-omap1/gpio16xx.c
> @@@ -218,17 -225,34 +225,34 @@@ static int __init omap16xx_gpio_init(vo
>   	if (!cpu_is_omap16xx())
>   		return -EINVAL;
>   
>  +	/*
>  +	 * Enable system clock for GPIO module.
>  +	 * The CAM_CLK_CTRL *is* really the right place.
>  +	 */
>  +	omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
>  +					ULPD_CAM_CLK_CTRL);
>  +
> - 	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
> - 		platform_device_register(omap16xx_gpio_dev[i]);
> + 	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
> + 		pdev = omap16xx_gpio_dev[i];
> + 		pdata = pdev->dev.platform_data;
> + 
> + 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + 		if (unlikely(!res)) {
> + 			dev_err(&pdev->dev, "Invalid mem resource.\n");
> + 			return -ENODEV;
> + 		}
>   
> - 	gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
> + 		base = ioremap(res->start, resource_size(res));
> + 		if (unlikely(!base)) {
> + 			dev_err(&pdev->dev, "ioremap failed.\n");
> + 			return -ENOMEM;
> + 		}
> + 
> + 		__raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG);
> + 		iounmap(base);
> + 
>  -		/*
>  -		 * Enable system clock for GPIO module.
>  -		 * The CAM_CLK_CTRL *is* really the right place.
>  -		 */
>  -		omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
>  -					ULPD_CAM_CLK_CTRL);
>  -
> + 		platform_device_register(omap16xx_gpio_dev[i]);
> + 	}
>   
>   	return 0;
>   }


From heiko at sntech.de  Thu Mar  1 15:15:41 2012
From: heiko at sntech.de (Heiko =?iso-8859-15?q?St=FCbner?=)
Date: Thu, 1 Mar 2012 21:15:41 +0100
Subject: [PATCH v2 1/2] ARM: EXYNOS: Add USB HOST register definitions
In-Reply-To: <CADPsn1ZfXqmOVtw5OdfbXv=xZ3EREbPqCRnpnsYHbhkvx=nb5Q@mail.gmail.com>
References: <000701ccf76d$8316b0a0$894411e0$%han@samsung.com>
 <201203011624.04551.heiko@sntech.de>
 <CADPsn1ZfXqmOVtw5OdfbXv=xZ3EREbPqCRnpnsYHbhkvx=nb5Q@mail.gmail.com>
Message-ID: <201203012115.42915.heiko@sntech.de>

Am Donnerstag 01 M?rz 2012, 17:10:52 schrieb Sangwook Lee:
> On 1 March 2012 15:24, Heiko St?bner <heiko at sntech.de> wrote:
> > Am Donnerstag, 1. M?rz 2012, 06:38:20 schrieb Jingoo Han:
> > > This patch adds USB HOST register definitions. The definition for
> > > EHCI INSNREG00 regiser and corresponding bit field definitions are
> > > added.
> > > 
> > > Signed-off-by: Sangwook Lee <sangwook.lee at linaro.org>
> > > Signed-off-by: Jingoo Han <jg1.han at samsung.com>
> > > ---
> > > v2: change the definition name from EHCI_ENA_xxx to
> > 
> > EHCI_INSNREG00_ENA_xxx.
> > 
> > > arch/arm/mach-exynos/include/mach/regs-usb-host.h |   24
> > > +++++++++++++++++++++ 1 files changed, 24 insertions(+), 0 deletions(-)
> > > 
> > >  create mode 100644 arch/arm/mach-exynos/include/mach/regs-usb-host.h
> > 
> > Isn't the general idea to depopulate the mach directories and make
> > drivers buildable across architectures?
> > 
> > The definitions are only used in drivers/usb/host/ehci-s5p.c [in the
> > second patch], so there should be no need to add another arch-header and
> > they could
> > simply be included in the driver itself or if necessary a
> > drivers/usb/host/ehci-s5p.h .
> 
>  I found out some code related to this burst function.
> 
>  the snip from ehci-s5pv210.c, 2.6.35 kernel
> 
>         /* Mark hardware accessible again as we are out of D3 state by now
> */
>         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
> #if defined(CONFIG_ARCH_S5PV210) || defined(CONFIG_ARCH_S5P6450)
>         ehci_writel(ehci, 0x000F0000, (void __iomem *)ehci->caps + 0x90);
> #endif
> 
> #if defined(CONFIG_ARCH_S5PV310)
>         ehci_writel(ehci, 0x03C00000, (void __iomem *)ehci->caps + 0x90);
> #endif
>         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
> 
> From this code, this burst function seems to be depending on CPUs,
> The driver by itself is not good idea because echi-s5p.c will have defined.

The current driver in mainline does not contain these ifdefs and this also 
should not change. What would happen in the code above if ARCH_S5PV210 and 
ARCH_S5PV310 are selected?

As providing support for more than one SoC in a kernel image is one of the 
current targets, architecture dependant stuff like the code above should 
probably be detected at runtime and definitly not compile-time.

> Which is the better place to pus this CPU specific definition either
> drivers/usb/host/ehci-s5p.h is
> or mach/xx.h or  include/linux/usb/xxx.h ?  I am not clear about this.

As I understand it, drivers should be compileable even if the underlying 
architecture is not selected and hence mustn't depend on architecure code.

Use-cases are for example compile-testing all usb-host drivers at once during 
some sort of rework, or the multi-arch kernel mentioned above.

But I really do not see why these defines you're adding cannot simply live 
inside the ehci-s5p.c . For example take a look at 
drivers/usb/gadget/s3c-hsudc.c . This driver also contains its private defines 
without the need for another header.


> > > diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-host.h
> > > b/arch/arm/mach-exynos/include/mach/regs-usb-host.h new file mode
> > > 100644 index 0000000..572b7d4
> > > --- /dev/null
> > > +++ b/arch/arm/mach-exynos/include/mach/regs-usb-host.h
> > > @@ -0,0 +1,24 @@
> > > +/*
> > > + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> > > + *           http://www.samsung.com
> > > + *
> > > + * EXYNOS - USB HOST register definitions
> > > + *
> > > + * This program is free software; you can redistribute it and/or
> > > modify + * it under the terms of the GNU General Public License
> > > version 2 as + * published by the Free Software Foundation.
> > > + */
> > > +
> > > +#ifndef __REGS_USB_HOST_H
> > > +#define __REGS_USB_HOST_H __FILE__
> > > +
> > > +#define EHCI_INSNREG00(base)                 (base + 0x90)
> > > +#define EHCI_INSNREG00_ENA_INCR16            (0x1 << 25)
> > > +#define EHCI_INSNREG00_ENA_INCR8             (0x1 << 24)
> > > +#define EHCI_INSNREG00_ENA_INCR4             (0x1 << 23)
> > > +#define EHCI_INSNREG00_ENA_INCRX_ALIGN               (0x1 << 22)
> > > +#define EHCI_INSNREG00_ENABLE_DMA_BURST      \
> > > +     (EHCI_INSNREG00_ENA_INCR16 | EHCI_INSNREG00_ENA_INCR8 | \
> > > +      EHCI_INSNREG00_ENA_INCR4 | EHCI_INSNREG00_ENA_INCRX_ALIGN)
> > > +
> > > +#endif /* __REGS_USB_HOST_H */
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe
> > linux-samsung-soc" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html



From arnd at arndb.de  Thu Mar  1 15:19:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 20:19:04 +0000
Subject: [PATCH 0/8] ARM: Tegra: cleanup patches from Arnd Bergmann
In-Reply-To: <1330630010-11241-1-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
Message-ID: <201203012019.04316.arnd@arndb.de>

On Thursday 01 March 2012, Alan Ott wrote:
> I'm helping Arnd Bergmann get some of his cleanup patches upstream. This
> set covers the Tegra.
> 
> Thanks,
> 
> Alan.
> 
> Arnd Bergmann (8):
>   ARM: tegra: export tegra_gpio_{en,dis}able
>   ARM: tegra: do not hide dma declarations
>   ARM: tegra: select CPU_FREQ_TABLE
>   ARM: tegra: build localtimer support only when needed
>   ARM: tegra: work around tegra THUMB2_KERNEL bug
>   ARM: tegra: USB_ULPI needs USB
>   ARM: tegra: export usb phy symbols
>   ARM: tegra: HACK: remove set_irq_flags() from driver
> 

Hi Alan,

Thanks for getting this started!

As Greg already commented, there are some patches that you
should probably drop. When you send out a series with the
name of a subarchitecture, it's best to leave out the patches
that only address device drivers. I had initially sorted these
into the subarch series instead of the drivers series but that
turned out to be a bad idea. Sorry I didn't remember about this
detail when we first discussed the way forward on my patches.

Also, it's better if you have a slightly shorter Cc list and
for each patch take only the people on Cc that are actually
interested, rather than send the whole series to everyone
that get_maintainer.pl lists for one of the patches. If the
Cc list gets too long, that often means that the mails get
dropped from the mailing lists, and people might ignore them
when they don't understand why they were on Cc to start with.
It does help to have everyone on Cc for the initial mail though.

You can add 'Cc:' tags in the individual patches to help you
with that. This is another thing I never got around to for
the patches I did not send out.

Finally, when sending patches from someone else, you have
to add your own Signed-off-by: line below the others (i.e. mine).
Everyone who is handling the patch by sending it to someone
else should have a Signed-off-by in the email until the
point when it gets applied to a git tree that is pulled into
the Linus' tree.

	Arnd


From arnd at arndb.de  Thu Mar  1 15:25:53 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 20:25:53 +0000
Subject: [PATCH 6/8] ARM: tegra: USB_ULPI needs USB
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE86172C@HQMAIL01.nvidia.com>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-7-git-send-email-alan@signal11.us>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE86172C@HQMAIL01.nvidia.com>
Message-ID: <201203012025.53560.arnd@arndb.de>

On Thursday 01 March 2012, Stephen Warren wrote:
> Alan Ott wrote at Thursday, March 01, 2012 12:27 PM:
> > From: Arnd Bergmann <arnd at arndb.de>
> > 
> > The USB_ULPI driver is selected by tegra, but can only be
> > built if at least one of USB or USB_GADGET is enabled.
> > The kernel fails to link if both are off.
> 
> > diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> ...
> > @@ -10,6 +10,7 @@ config ARCH_TEGRA_2x_SOC
> ...
> > +	select USB_GADGET if USB_SUPPORT && !USB
> 
> I don't believe the Tegra USB driver supports gadget mode at present.

ok.

> Would the above be better written as:
> 
>     select USB if USB_SUPPORT

That does not look correct either. There is no reason why USB
can't be disabled with USB_SUPPORT enabled on other platforms.

Maybe it's better to change the 'select USB_ULPI if USB_SUPPORT'
into 'select USB_ULPI if USB' instead? Or maybe just don't select
USB_ULPI to start with and put it into the defconfig instead.

> And this is probably required for Tegra30 too not just Tegra20.

Right. Tegra30 was not there when I did these patches, so it's
probably missing in other places, too.

	Arnd


From swarren at nvidia.com  Thu Mar  1 15:29:43 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Thu, 1 Mar 2012 12:29:43 -0800
Subject: [PATCH 8/8] ARM: tegra: HACK: remove set_irq_flags() from driver
In-Reply-To: <1330630010-11241-9-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-9-git-send-email-alan@signal11.us>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE86173C@HQMAIL01.nvidia.com>

Alan Ott wrote at Thursday, March 01, 2012 12:27 PM:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The driver should not call set_irq_flags itself, and

Probably true in this case.

> cannot do this from a loadable module.

I hope that's not true; grep'ing the entire of drivers/ shows a bunch
of drivers calling this function, and many look like they'd be reasonable
as module.

>From what little I understand of this, any irq_chip is going to call
that function after setting up any child/cascaded IRQs, and I assume
that irq_chips can be in modules.

> Remove the call for now, which might break the driver
> but at least lets the kernel link again.

The driver appears to work fine with this removed. At least, on Tegra20
Harmony, I was able to modprobe ehci-hcd and then use the USB Ethernet
controller for DHCP and SSH.

So,

Tested-by: Stephen Warren <swarren at nvidia.com>

-- 
nvpublic



From arnd at arndb.de  Thu Mar  1 15:28:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 20:28:04 +0000
Subject: [PATCH 0/4] ARM: kirkwood: fdt: convert kirkwood init funcs to fdt
In-Reply-To: <20120301200136.GA11986@titan.lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203011950.51210.arnd@arndb.de>
 <20120301200136.GA11986@titan.lakedaemon.net>
Message-ID: <201203012028.04773.arnd@arndb.de>

On Thursday 01 March 2012, Jason wrote:
> Thanks for the feedback.  I'll redo this series and resubmit.  Did you
> catch my patch from yesterday?
> 
> [PATCH v3] ARM: kirkwood: covert orion-spi to fdt. [1]

Yes, I saw that. It looks good and I was just waiting if other people
have comments on it. Maybe you can put it into the same git tree as
these ones when they are ready and you send a pull request.

	Arnd


From linus.walleij at linaro.org  Thu Mar  1 15:33:03 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 1 Mar 2012 21:33:03 +0100
Subject: [PATCH 8/8] ARM: tegra: HACK: remove set_irq_flags() from driver
In-Reply-To: <1330630010-11241-9-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-9-git-send-email-alan@signal11.us>
Message-ID: <CACRpkdZK+9gF7N2akyWw=tvcBS2X2FmSd2-SiNKiuRgUCYXx7w@mail.gmail.com>

On Thu, Mar 1, 2012 at 8:26 PM, Alan Ott <alan at signal11.us> wrote:

> From: Arnd Bergmann <arnd at arndb.de>
>
> The driver should not call set_irq_flags itself, and
> cannot do this from a loadable module.
>
> Remove the call for now, which might break the driver
> but at least lets the kernel link again.
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> ---
> ?drivers/usb/host/ehci-tegra.c | ? ?1 -
> ?1 files changed, 0 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
> index dbc7fe8..ab91f26 100644
> --- a/drivers/usb/host/ehci-tegra.c
> +++ b/drivers/usb/host/ehci-tegra.c
> @@ -729,7 +729,6 @@ static int tegra_ehci_probe(struct platform_device *pdev)
> ? ? ? ? ? ? ? ?err = -ENODEV;
> ? ? ? ? ? ? ? ?goto fail;
> ? ? ? ?}
> - ? ? ? set_irq_flags(irq, IRQF_VALID);

The kernel is full of this kind of stuff (drivers/mfd/twl4030-irq.c):

#ifdef CONFIG_ARM
        /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
         * sets on behalf of every irq_chip.  Also sets IRQ_NOPROBE.
         */
        set_irq_flags(irq, IRQF_VALID);
#else
        /* same effect on other architectures */
        irq_set_noprobe(irq);
#endif

Can't we try to fix this for real instead of breaking the universe,
hehe :-)

Yours,
Linus Walleij


From andrew at lunn.ch  Thu Mar  1 15:32:39 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Thu, 1 Mar 2012 21:32:39 +0100
Subject: [PATCH v2 19/28] ARM: Add fixed PCI i/o mapping
In-Reply-To: <201203011825.44049.arnd@arndb.de>
References: <1330547147-22867-1-git-send-email-robherring2@gmail.com>
 <201203011352.36067.arnd@arndb.de>
 <20120301140817.GG7363@n2100.arm.linux.org.uk>
 <201203011825.44049.arnd@arndb.de>
Message-ID: <20120301203239.GA10854@lunn.ch>

> That leaves us still with Kirkwood/Dove and ixp2000 to figure out.
> 
...
> 
> For Kirkwood and Dove, an easy way out would be to extend the I/O
> space window to 2MB right away and just map both as before, but we
> can also try just using the two lower 64k windows in each and see what
> breaks, as those seem to be widely available for testing still.

I have two different kirkwood devices i can test with. Unfortunately,
only one has a pcie devices, an Atheros wireless card. I might be able
to test the machine without any pcie devices tomorrow, but the
interesting device will have to wait until next week.

	    Andrew


From khilman at ti.com  Thu Mar  1 15:36:57 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 01 Mar 2012 12:36:57 -0800
Subject: [PATCH v3] ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
 regulators
In-Reply-To: <1330006564-13290-1-git-send-email-mporter@ti.com> (Matt Porter's
 message of "Thu, 23 Feb 2012 09:16:04 -0500")
References: <1330006564-13290-1-git-send-email-mporter@ti.com>
Message-ID: <87wr74gis6.fsf@ti.com>

Matt Porter <mporter at ti.com> writes:

> This fixes smsc911x support on platforms using gpmc_smsc911x_init().
>
> Commit c7e963f6888816 (net/smsc911x: Add regulator support) added
> the requirement that platforms provide vdd33a and vddvario supplies.
>
> Signed-off-by: Matt Porter <mporter at ti.com>

[...]

>  /*
>   * Initialize smsc911x device connected to the GPMC. Note that we
>   * assume that pin multiplexing is done in the board-*.c file,
> @@ -55,6 +101,12 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
>  
>  	gpmc_cfg = board_data;
>  
> +	ret = platform_device_register(&gpmc_smsc911x_regulator);
> +	if (ret < 0) {
> +		pr_err("Unable to register smsc911x regulators: %d\n", ret);
> +		return;
> +	}
> +

Boards that have more than one instance of the smsc911x (OMAP3/Overo)
barf here because of trying to register the same device twice.

We need something like the patch below to make Overo boot again.

Kevin



>From 4114dea2fb897ab75d05eaa943d29454034fc025 Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman at ti.com>
Date: Thu, 1 Mar 2012 12:30:42 -0800
Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulators once

commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
regulators) added regulators which are registered during
gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
than one instance of the SMSC911x and result in attempting to register
the same regulator more than once which causes a panic().  Fix this by
tracking the regulator registration ensuring only a single device is
registered.

Cc: Matt Porter <mporter at ti.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/gpmc-smsc911x.c |   14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index bbb870c..95e6c7d 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -88,6 +88,8 @@ static struct platform_device gpmc_smsc911x_regulator = {
 	},
 };
 
+static bool regulator_registered;
+
 /*
  * Initialize smsc911x device connected to the GPMC. Note that we
  * assume that pin multiplexing is done in the board-*.c file,
@@ -101,10 +103,14 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
 
 	gpmc_cfg = board_data;
 
-	ret = platform_device_register(&gpmc_smsc911x_regulator);
-	if (ret < 0) {
-		pr_err("Unable to register smsc911x regulators: %d\n", ret);
-		return;
+	if (!regulator_registered) {
+		ret = platform_device_register(&gpmc_smsc911x_regulator);
+		if (ret < 0) {
+			pr_err("Unable to register smsc911x regulators: %d\n",
+			       ret);
+			return;
+		}
+		regulator_registered = true;
 	}
 
 	if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
-- 
1.7.9.2



From swarren at nvidia.com  Thu Mar  1 15:36:58 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Thu, 1 Mar 2012 12:36:58 -0800
Subject: [PATCH 6/8] ARM: tegra: USB_ULPI needs USB
In-Reply-To: <201203012025.53560.arnd@arndb.de>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-7-git-send-email-alan@signal11.us>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE86172C@HQMAIL01.nvidia.com>
 <201203012025.53560.arnd@arndb.de>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861741@HQMAIL01.nvidia.com>

Arnd Bergmann wrote at Thursday, March 01, 2012 1:26 PM:
> On Thursday 01 March 2012, Stephen Warren wrote:
> > Alan Ott wrote at Thursday, March 01, 2012 12:27 PM:
> > > From: Arnd Bergmann <arnd at arndb.de>
> > >
> > > The USB_ULPI driver is selected by tegra, but can only be
> > > built if at least one of USB or USB_GADGET is enabled.
> > > The kernel fails to link if both are off.
> >
> > > diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> > ...
> > > @@ -10,6 +10,7 @@ config ARCH_TEGRA_2x_SOC
> > ...
> > > +	select USB_GADGET if USB_SUPPORT && !USB
> >
> > I don't believe the Tegra USB driver supports gadget mode at present.
> 
> ok.
> 
> > Would the above be better written as:
> >
> >     select USB if USB_SUPPORT
> 
> That does not look correct either. There is no reason why USB
> can't be disabled with USB_SUPPORT enabled on other platforms.
> 
> Maybe it's better to change the 'select USB_ULPI if USB_SUPPORT'
> into 'select USB_ULPI if USB' instead?

That sounds reasonable.

> Or maybe just don't select
> USB_ULPI to start with and put it into the defconfig instead.

Perhaps USB_EHCI_TEGRA should depend on USB, and select USB_EHCI?

-- 
nvpublic



From arnd at arndb.de  Thu Mar  1 15:38:27 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 20:38:27 +0000
Subject: [PATCH 8/8] ARM: tegra: HACK: remove set_irq_flags() from driver
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE86173C@HQMAIL01.nvidia.com>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-9-git-send-email-alan@signal11.us>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE86173C@HQMAIL01.nvidia.com>
Message-ID: <201203012038.28062.arnd@arndb.de>

On Thursday 01 March 2012, Stephen Warren wrote:
> 
> Alan Ott wrote at Thursday, March 01, 2012 12:27 PM:
> > From: Arnd Bergmann <arnd at arndb.de>
> > 
> > The driver should not call set_irq_flags itself, and
> 
> Probably true in this case.
> 
> > cannot do this from a loadable module.
> 
> I hope that's not true; grep'ing the entire of drivers/ shows a bunch
> of drivers calling this function, and many look like they'd be reasonable
> as module.

The drivers that I can see using it are for the most part implementing
irq controllers by themselves, which is different from merely using an
interrupt.

There are three exceptions today:

arnd at klappe2:~/linux-arm$ git grep -l set_irq_flags  drivers/ | xargs grep -L irq_chip
drivers/tty/serial/serial_ks8695.c
drivers/tty/serial/sirfsoc_uart.c
drivers/usb/host/ehci-tegra.c

> From what little I understand of this, any irq_chip is going to call
> that function after setting up any child/cascaded IRQs, and I assume
> that irq_chips can be in modules.

But the function is not exported. I guess if we want to allow
irq_chips in loadable modules, we could export it, but I don't see
how it could ever have worked so far.
 
> > Remove the call for now, which might break the driver
> > but at least lets the kernel link again.
> 
> The driver appears to work fine with this removed. At least, on Tegra20
> Harmony, I was able to modprobe ehci-hcd and then use the USB Ethernet
> controller for DHCP and SSH.

Ok, maybe it was the right fix after all then and it just needs a proper
change description ;-)

	Arnd


From jason at lakedaemon.net  Thu Mar  1 15:39:17 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 1 Mar 2012 15:39:17 -0500
Subject: [PATCH] mach-kirkwood: Support for DLink DNS-320 & DNS-325 NAS
In-Reply-To: <201202291440.10418.arnd@arndb.de>
References: <alpine.DEB.2.02.1202121424080.16803@bunsen.wrottesley.wormnet.eu>
 <201202291440.10418.arnd@arndb.de>
Message-ID: <20120301203917.GB11986@titan.lakedaemon.net>

On Wed, Feb 29, 2012 at 02:40:10PM +0000, Arnd Bergmann wrote:
> On Sunday 12 February 2012, Jamie Lentin wrote:
> > This patch adds support for the D-Link DNS-320 & DNS-325 NAS. Kirkwood-based
> > successors to the DNS-323.
> > 
> > Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> > ---
> > My previous patch supported just the DNS-325, the DNS-320 is a very similar
> > device and so I've combined the support for both devices into one board support
> > file. The main difference with the DNS-320 is that the temperature sensor
> > is accessed via ttyS1 instead of I2C (I have a userland script to do this).
> > 
> > I appreciate board support files like this are old hat and should be using
> > device tree instead. If I should be focusing on that instead of getting this
> > merged, some pointers would be very useful.
> 
> Hi Jamie,
> 
> I just saw this patch going through the mailing list and noticed that you
> had sent it out another time before without getting any reply. 
> 
> I'm sorry that you did not get any feedback on this. Jason Cooper had a
> similar patch and he ended up a bit more fortunate than you, since he
> got support for the kirkwood based "dreamplug" into the arm-soc tree
> and is working on converting that to device tree now.
> 
> I would suggest that you two team up and put DNS-32x support into the new
> common board-dt.c file as well.

Jamie,

Take a look at the dreamplug initial support patch series, latest here
[1].  Make a kirkwood-dns-320.dts and a kirkwood-dns-325.dts file
mimicing kirkwood-dreamplug.dts.  All you should need to start out is
the compatible property and memory.

[1] http://www.spinics.net/lists/arm-kernel/msg161696.html

> Some more comments:
> 
> > diff --git a/arch/arm/mach-kirkwood/dnskw-setup.c b/arch/arm/mach-kirkwood/dnskw-setup.c
> > new file mode 100644
> > index 0000000..25ea0fa
> > --- /dev/null
> > +++ b/arch/arm/mach-kirkwood/dnskw-setup.c
> > @@ -0,0 +1,431 @@
> > +/*
> > + * arch/arm/mach-kirkwood/dnskw-setup.c
> 
> All future boards should ideally go through a single board file, and the plan
> is to work on minimizing the non-generic contents of that over time.
> Right now, it only contains support for the dreamplug, but there is no
> reason why this one couldn't get merged into it as well.
> 
> > +static struct mtd_partition dnskw_nand_parts[] = {
> > +	{
> > +		.name		= "u-boot",
> > +		.offset		= 0,
> > +		.size		= SZ_1M,
> > +		.mask_flags	= MTD_WRITEABLE
> > +	}, {
> > +		.name		= "uImage",
> > +		.offset		= MTDPART_OFS_NXTBLK,
> > +		.size		= 5 * SZ_1M
> > +	}, {
> > +		.name		= "ramdisk",
> > +		.offset		= MTDPART_OFS_NXTBLK,
> > +		.size		= 5 * SZ_1M
> > +	}, {
> > +		.name		= "image",
> > +		.offset		= MTDPART_OFS_NXTBLK,
> > +		.size		= 102 * SZ_1M
> > +	}, {
> > +		.name		= "mini firmware",
> > +		.offset		= MTDPART_OFS_NXTBLK,
> > +		.size		= 10 * SZ_1M
> > +	}, {
> > +		.name		= "config",
> > +		.offset		= MTDPART_OFS_NXTBLK,
> > +		.size		= 5 * SZ_1M
> > +	},
> > +};
> 
> Jason already has a patch for NAND partitions through the SPI attachment,
> I would suggest that you do the same for the nand controller, the patch
> should be fairly similar.
> 
> > +static struct mv643xx_eth_platform_data dnskw_ge00_data = {
> > +	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
> > +};
> > +
> > +static struct mv_sata_platform_data dnskw_sata_data = {
> > +	.n_ports	= 2,
> > +};
> > +
> > +/*****************************************************************************
> > + *  I2C-based devices
> > + *
> > + *  i2c addr | chip        | description
> > + *  0x48     | GMT G751-2f | LM75-compatible temp. sensor (DNS-325 only)
> > + *  0x0c     | ?           | (DNS-325 only)
> > + *  0x64     | ?           |
> > + ****************************************************************************/
> > +
> > +#ifdef CONFIG_MACH_DNS325
> > +static struct i2c_board_info dns325_i2c_board_info[] __initdata = {
> > +	{
> > +		I2C_BOARD_INFO("lm75", 0x48),
> > +	},
> > +};
> > +#endif
> 
> These three things will require simple device tree bindings, but I think you
> can leave them present in the first version and then submit follow-on patches
> for them, moving all the data into the device tree.
> 
> > +/*****************************************************************************
> > + * MPP / GPIO setup
> > + ****************************************************************************/
> > +
> > +static unsigned int dnskw_mpp_config[] __initdata = {
> > +	MPP13_UART1_TXD,	/* Custom ... */
> > +	MPP14_UART1_RXD,	/* ... Controller (DNS-320 only) */
> > +	MPP20_SATA1_ACTn,	/* LED: White Right HDD */
> > +	MPP21_SATA0_ACTn,	/* LED: White Left HDD */
> > +	MPP24_GPIO,
> > +	MPP25_GPIO,
> > +	MPP26_GPIO,	/* LED: Power */
> > +	MPP27_GPIO,	/* LED: Red Right HDD */
> > +	MPP28_GPIO,	/* LED: Red Left HDD */
> > +	MPP29_GPIO,	/* LED: Red USB (DNS-325 only) */
> > +	MPP30_GPIO,
> > +	MPP31_GPIO,
> > +	MPP32_GPIO,
> > +	MPP33_GPO,
> > +	MPP34_GPIO,	/* Button: Front power */
> > +	MPP35_GPIO,	/* LED: Red USB (DNS-320 only) */
> > +	MPP36_GPIO,	/* Power: MV88F6281_DEV_ID Board */
> > +	MPP37_GPIO,	/* Power: Boot when power applied */
> > +	MPP38_GPIO,
> > +	MPP39_GPIO,	/* Power: SATA0 */
> > +	MPP40_GPIO,	/* Power: SATA1 */
> > +	MPP41_GPIO,
> > +	MPP42_GPIO,
> > +	MPP43_GPIO,	/* LED: White USB */
> > +	MPP44_GPIO,	/* Fan: Tachometer Pin */
> > +	MPP45_GPIO,	/* Fan: high speed */
> > +	MPP46_GPIO,	/* Fan: low speed */
> > +	MPP47_GPIO,	/* Button: Back unmount */
> > +	MPP48_GPIO,	/* Button: Back reset */
> > +	MPP49_GPIO,	/* Pin of unused U5 (DNS-320 only) */
> > +	0
> > +};
> 
> mpp config is a bit tricky, this will likely stay like this for the
> next time.
> 
> > +/*****************************************************************************
> > + * Power controls
> > + ****************************************************************************/
> > +
> > +static void dnskw_power_off(void)
> > +{
> > +	gpio_set_value(DNSKW_GPIO_POWER, 1);
> > +}
> > ... <snip -- lots of gpio stuff>
> 
> The entire gpio setup is rather complex, and I don't know how much of it
> can be handled with the existing gpio device tree bindings. I hope someone
> else can comment here.
> 
> > +/*****************************************************************************
> > + * Main init
> > + ****************************************************************************/
> > +
> > +static void __init dnskw_init(void)
> > +{
> > +	u32 dev, rev;
> > +
> > +	/*
> > +	 * Basic setup. Needs to be called early.
> > +	 */
> > +	kirkwood_init();
> > +	kirkwood_mpp_conf(dnskw_mpp_config);
> 
> There is now a kirkwood_dt_init function that calls the board specific
> functions based on an of_machine_is_compatible() check. Best add anything
> from this function in there that cannot be handled using device tree
> probing yet.
> 
> > +	kirkwood_uart0_init();
> > +	kirkwood_uart1_init();
> 
> These can be done from the device tree already.
> 
> > +	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
> 
> This is the one I mentioned above that I think you should try to convert.
> 
> > +	kirkwood_ehci_init();
> > +	kirkwood_i2c_init();
> > +	kirkwood_ge00_init(&dnskw_ge00_data);
> > +	kirkwood_sata_init(&dnskw_sata_data);
> 
> These should be handled next, but not necessarily before this board
> supports makes it into the upstream kernel. Adding the bindings for
> these should be fairly straightforward, and it will get easier
> if kirkwood is first converted to use the generic clock framework.

I've got a handle on these after I do xor and crypto.  If you get to it
before I do, hit sata and ge00/01.  I'll start with ehci and i2c.


> > +#ifdef CONFIG_MACH_DNS320
> > +	if (machine_is_dns320())
> > +		platform_device_register(&dns320_led_device);
> > +#endif
> > +#ifdef CONFIG_MACH_DNS325
> > +	if (machine_is_dns325()) {
> > +		platform_device_register(&dns325_led_device);
> > +
> > +		i2c_register_board_info(0, dns325_i2c_board_info,
> > +					ARRAY_SIZE(dns325_i2c_board_info));
> > +	}
> > +#endif
> > +
> > +	/*
> > +	 * Turn on power to harddrives, then enable SATA.
> > +	 * NB: Bootloader should have turned sata0 on already, kernel needs
> > +	 * to turn on sata1. The idea is to stagger spin-up of HDDs.
> > +	 */
> > +	dnskw_gpio_register(DNSKW_GPIO_POWER_SATA0, "dnskw:power:sata0", 1);
> > +	dnskw_gpio_register(DNSKW_GPIO_POWER_SATA1, "dnskw:power:sata1", 1);
> > +
> > +	platform_device_register(&dnskw_button_device);
> > +	platform_device_register(&dnskw_fan_device);
> 
> It should be possible to handle all this by putting the right devices
> into the device tree, but I don't know how to do that.
> 
> > +	/* Register power off routine */
> > +	kirkwood_pcie_id(&dev, &rev);
> > +	if (dev == MV88F6281_DEV_ID) {
> > +		pr_info("PCI-E Device ID: MV88F6281, configuring power-off");
> > +		if (gpio_request(DNSKW_GPIO_POWER, "dnskw:power:off") == 0 &&
> > +		    gpio_direction_output(DNSKW_GPIO_POWER, 0) == 0)
> > +			pm_power_off = dnskw_power_off;
> > +		else
> > +			pr_err("dnskw: failed to configure power-off GPIO\n");
> > +	} else {
> > +		/*
> > +		 * Dlink code also defines 0x6192, and sets LOW_BASE +
> > +		 * 0x01000000 high. Either cargo-culted code or another model.
> > +		 */
> > +		pr_err("Unknown PCI-E Device ID %x, no power-off", dev);
> > +	}
> > +
> > +	/* Set state of power_recover pin */
> > +	if (gpio_request(DNSKW_GPIO_POWER_RECOVER, "dnskw:power:recover") == 0
> > +	 && gpio_direction_output(DNSKW_GPIO_POWER_RECOVER, 0) == 0) {
> > +		pr_info("dnskw: Setting power-recover %s\n",
> > +			power_recover_value ? "on" : "off");
> > +		gpio_set_value(DNSKW_GPIO_POWER_RECOVER, power_recover_value);
> > +	} else
> > +		pr_err("dnskw: Failed to register power-recover GPIO\n");
> > +}
> 
> This might have to stay board specific.
> 
> > +#ifdef CONFIG_MACH_DNS320
> > +MACHINE_START(DNS320, "D-Link DNS-320")
> > +	/* Maintainer: Jamie Lentin <jm at lentin.co.uk> */
> > +	.atag_offset	= 0x100,
> > +	.init_machine	= dnskw_init,
> > +	.map_io		= kirkwood_map_io,
> > +	.init_early	= kirkwood_init_early,
> > +	.init_irq	= kirkwood_init_irq,
> > +	.timer		= &kirkwood_timer,
> > +	.restart	= kirkwood_restart,
> > +MACHINE_END
> > +#endif
> > +
> > +#ifdef CONFIG_MACH_DNS325
> > +MACHINE_START(DNS325, "D-Link DNS-325")
> > +	/* Maintainer: Jamie Lentin <jm at lentin.co.uk> */
> > +	.atag_offset	= 0x100,
> > +	.init_machine	= dnskw_init,
> > +	.map_io		= kirkwood_map_io,
> > +	.init_early	= kirkwood_init_early,
> > +	.init_irq	= kirkwood_init_irq,
> > +	.timer		= &kirkwood_timer,
> > +	.restart	= kirkwood_restart,
> > +MACHINE_END
> > +#endif
> 
> Just use DT_MACHINE_START here and remove the machine ID and atag_offset. See
> the board-dt.c file.

See the link [1], above.

thx,

Jason.


From arnd at arndb.de  Thu Mar  1 15:40:17 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 20:40:17 +0000
Subject: [PATCH 8/8] ARM: tegra: HACK: remove set_irq_flags() from driver
In-Reply-To: <CACRpkdZK+9gF7N2akyWw=tvcBS2X2FmSd2-SiNKiuRgUCYXx7w@mail.gmail.com>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-9-git-send-email-alan@signal11.us>
 <CACRpkdZK+9gF7N2akyWw=tvcBS2X2FmSd2-SiNKiuRgUCYXx7w@mail.gmail.com>
Message-ID: <201203012040.18158.arnd@arndb.de>

On Thursday 01 March 2012, Linus Walleij wrote:
> The kernel is full of this kind of stuff (drivers/mfd/twl4030-irq.c):
> 
> #ifdef CONFIG_ARM
>         /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
>          * sets on behalf of every irq_chip.  Also sets IRQ_NOPROBE.
>          */
>         set_irq_flags(irq, IRQF_VALID);
> #else
>         /* same effect on other architectures */
>         irq_set_noprobe(irq);
> #endif

That is the implementation of an irq_chip, not a random device driver.

	Arnd


From rob.lee at linaro.org  Thu Mar  1 15:42:32 2012
From: rob.lee at linaro.org (Rob Lee)
Date: Thu, 1 Mar 2012 14:42:32 -0600
Subject: [PATCH v7 1/9] cpuidle: Add common time keeping and irq enabling
In-Reply-To: <4F4EF7FC.9040403@linux.vnet.ibm.com>
References: <1330562578-3410-1-git-send-email-rob.lee@linaro.org>
 <1330562578-3410-2-git-send-email-rob.lee@linaro.org>
 <4F4EF7FC.9040403@linux.vnet.ibm.com>
Message-ID: <CAMXH7KHn-bLckyXKv3mWM6GY8DQ7yJY9kLteM-xRCFWFTH1Gew@mail.gmail.com>

Hello Deepthi,

On Wed, Feb 29, 2012 at 10:15 PM, Deepthi Dharwar
<deepthi at linux.vnet.ibm.com> wrote:
> Hi Rob,
>
> On 03/01/2012 06:12 AM, Robert Lee wrote:
>
>> Make necessary changes to implement time keeping and irq enabling
>> in the core cpuidle code. ?This will allow the removal of these
>> functionalities from various platform cpuidle implementations whose
>> timekeeping and irq enabling follows the form in this common code.
>
>
> The generic cpuidle changes look good, but is there a reason as
> to why these changes are enabled only for ARM and not other
> archs ?
>

Besides ARM, this patchset also enables some of this new consolidation
functionality on arch/SH and for archs that use the
CONFIG_ARCH_HAS_CPU_RELAX (maybe x86 uses this?).

For the powerpc P-series, it could probably could be modified to use
the consolidated timekeeping but I didn't feel comfortable making that
change myself for a couple of reasons.  First, the common wrapper also
includes the local_irq_enable() call, but the p-series cpuidle code
doesn't include this call, as instead, it relies on the
local_irq_enable() call in the cpu_idle() function in
arch/powerpc/kernel/idle.c.  Is it OK to remove this
local_irq_enable() once the wrapper is used?  Second, is there any
special coordination needed with the timekeeping functions and the
mfspr() calls?

Looking at the intel and acpi cpuidle implementations, their current
organization does seem to be able to use the common time keeping / irq
enabling wrapper.  Upon first glance, it appears that there are
special timer/timekeeping requirements for x86 that aren't required by
other platforms.  But that may not be correct.

If you look back at v4 of this patch series, you'll see an attempt at
a common timekeeping that could be used by x86 and acpi , but it
causes other compromises that to me aren't worth the extra gain from a
100% common timekeeping / irq enable solution.  I requested
feedback/opinions on this issue after v4 but didn't hear anything
about changes made to the intel or acpi implementations.  So I
continued on with the common wrapper direction from v3 when making v5.

Ultimately, even if the consolidated code only can be used by most and
not all arch or platform cpuidle implementations, it still reduces
some platform cpuidle fragmentation and duplicated code and hopefully
improves the maintainability of the core cpuidle.


From linux at arm.linux.org.uk  Thu Mar  1 15:42:04 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 20:42:04 +0000
Subject: [PATCH 5/8] ARM: tegra: work around tegra THUMB2_KERNEL bug
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE861726@HQMAIL01.nvidia.com>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-6-git-send-email-alan@signal11.us>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861726@HQMAIL01.nvidia.com>
Message-ID: <20120301204203.GA19274@n2100.arm.linux.org.uk>

On Thu, Mar 01, 2012 at 12:02:42PM -0800, Stephen Warren wrote:
> Alan Ott wrote at Thursday, March 01, 2012 12:27 PM:
> > From: Arnd Bergmann <arnd at arndb.de>
> > 
> > The tegra smp code cannot currently be built for t2, so
> > disable that combination for now, as a workaround.
> > 
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> 
> At least in next-20120229 with the .config I'm using, everything appears
> to compile fine. The link step does fail, but the error messages I get
> don't appear to be Tegra specific:
> 
> xxx/kernel/sched/clock.c:334: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `sched_clock' defined in .text section in arch/arm/kernel/built-in.o
> kernel/built-in.o: In function `post_relocation':
> xxx/kernel/module.c:2860: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `module_finalize' defined in .text section in arch/arm/kernel/built-in.o
> kernel/built-in.o: In function `show_interrupts':
> xxx/kernel/irq/proc.c:431: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `arch_show_interrupts' defined in .text section in arch/arm/kernel/built-in.o
> drivers/built-in.o: In function `pci_set_master':
> xxx/drivers/pci/pci.c:2674: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `pcibios_set_master' defined in .text section in arch/arm/kernel/built-in.o

At a guess, it suggests your kernel image is too big for the relocations
contained within the code.  That's something for Thumb people to look
into and solve.


From arnd at arndb.de  Thu Mar  1 15:42:51 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 20:42:51 +0000
Subject: [PATCH 6/8] ARM: tegra: USB_ULPI needs USB
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE861741@HQMAIL01.nvidia.com>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <201203012025.53560.arnd@arndb.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861741@HQMAIL01.nvidia.com>
Message-ID: <201203012042.51936.arnd@arndb.de>

On Thursday 01 March 2012, Stephen Warren wrote:
> > Or maybe just don't select
> > USB_ULPI to start with and put it into the defconfig instead.
> 
> Perhaps USB_EHCI_TEGRA should depend on USB, and select USB_EHCI?

I think it should, but that is a different issue. All EHCI bus
glues currently depend on USB_EHCI_HCD instead of selecting it.

Changing that would likely break a number of other things that
have come to depend on the current behavior.

	Arnd


From balbi at ti.com  Thu Mar  1 15:45:54 2012
From: balbi at ti.com (Felipe Balbi)
Date: Thu, 1 Mar 2012 22:45:54 +0200
Subject: [PATCH v3] ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
 regulators
In-Reply-To: <87wr74gis6.fsf@ti.com>
References: <1330006564-13290-1-git-send-email-mporter@ti.com>
 <87wr74gis6.fsf@ti.com>
Message-ID: <20120301204553.GA21841@legolas.emea.dhcp.ti.com>

Hi,

On Thu, Mar 01, 2012 at 12:36:57PM -0800, Kevin Hilman wrote:
> Matt Porter <mporter at ti.com> writes:
> 
> > This fixes smsc911x support on platforms using gpmc_smsc911x_init().
> >
> > Commit c7e963f6888816 (net/smsc911x: Add regulator support) added
> > the requirement that platforms provide vdd33a and vddvario supplies.
> >
> > Signed-off-by: Matt Porter <mporter at ti.com>
> 
> [...]
> 
> >  /*
> >   * Initialize smsc911x device connected to the GPMC. Note that we
> >   * assume that pin multiplexing is done in the board-*.c file,
> > @@ -55,6 +101,12 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
> >  
> >  	gpmc_cfg = board_data;
> >  
> > +	ret = platform_device_register(&gpmc_smsc911x_regulator);
> > +	if (ret < 0) {
> > +		pr_err("Unable to register smsc911x regulators: %d\n", ret);
> > +		return;
> > +	}
> > +
> 
> Boards that have more than one instance of the smsc911x (OMAP3/Overo)
> barf here because of trying to register the same device twice.
> 
> We need something like the patch below to make Overo boot again.
> 
> Kevin
> 
> 
> 
> From 4114dea2fb897ab75d05eaa943d29454034fc025 Mon Sep 17 00:00:00 2001
> From: Kevin Hilman <khilman at ti.com>
> Date: Thu, 1 Mar 2012 12:30:42 -0800
> Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulators once
> 
> commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
> regulators) added regulators which are registered during
> gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
> than one instance of the SMSC911x and result in attempting to register
> the same regulator more than once which causes a panic().  Fix this by
> tracking the regulator registration ensuring only a single device is
> registered.
> 
> Cc: Matt Porter <mporter at ti.com>
> Signed-off-by: Kevin Hilman <khilman at ti.com>
> ---
>  arch/arm/mach-omap2/gpmc-smsc911x.c |   14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
> index bbb870c..95e6c7d 100644
> --- a/arch/arm/mach-omap2/gpmc-smsc911x.c
> +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
> @@ -88,6 +88,8 @@ static struct platform_device gpmc_smsc911x_regulator = {
>  	},
>  };
>  
> +static bool regulator_registered;
> +
>  /*
>   * Initialize smsc911x device connected to the GPMC. Note that we
>   * assume that pin multiplexing is done in the board-*.c file,
> @@ -101,10 +103,14 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
>  
>  	gpmc_cfg = board_data;
>  
> -	ret = platform_device_register(&gpmc_smsc911x_regulator);
> -	if (ret < 0) {
> -		pr_err("Unable to register smsc911x regulators: %d\n", ret);
> -		return;
> +	if (!regulator_registered) {
> +		ret = platform_device_register(&gpmc_smsc911x_regulator);
> +		if (ret < 0) {
> +			pr_err("Unable to register smsc911x regulators: %d\n",
> +			       ret);
> +			return;
> +		}
> +		regulator_registered = true;

Wow, this is quite a hack. Is the regulator part of the SMSC911x device
or is it outside ? If it's outside the SMSC91xx (which I believe it is)
there should be a regulator driver instead of this hack. For boards
which don't provide such a regulator (and tie the supply pin to some
constant voltage source) there should be a constant regulator supplying
the pin. But this patch is quite hacky.

-- 
balbi
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From arnd at arndb.de  Thu Mar  1 15:46:17 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 20:46:17 +0000
Subject: [PATCH 5/8] ARM: tegra: work around tegra THUMB2_KERNEL bug
In-Reply-To: <20120301204203.GA19274@n2100.arm.linux.org.uk>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861726@HQMAIL01.nvidia.com>
 <20120301204203.GA19274@n2100.arm.linux.org.uk>
Message-ID: <201203012046.17768.arnd@arndb.de>

On Thursday 01 March 2012, Russell King - ARM Linux wrote:
> On Thu, Mar 01, 2012 at 12:02:42PM -0800, Stephen Warren wrote:
> > Alan Ott wrote at Thursday, March 01, 2012 12:27 PM:
> > > From: Arnd Bergmann <arnd at arndb.de>
> > > 
> > > The tegra smp code cannot currently be built for t2, so
> > > disable that combination for now, as a workaround.
> > > 
> > > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > 
> > At least in next-20120229 with the .config I'm using, everything appears
> > to compile fine. The link step does fail, but the error messages I get
> > don't appear to be Tegra specific:
> > 
> > xxx/kernel/sched/clock.c:334: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `sched_clock' defined in .text section in arch/arm/kernel/built-in.o
> > kernel/built-in.o: In function `post_relocation':
> > xxx/kernel/module.c:2860: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `module_finalize' defined in .text section in arch/arm/kernel/built-in.o
> > kernel/built-in.o: In function `show_interrupts':
> > xxx/kernel/irq/proc.c:431: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `arch_show_interrupts' defined in .text section in arch/arm/kernel/built-in.o
> > drivers/built-in.o: In function `pci_set_master':
> > xxx/drivers/pci/pci.c:2674: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `pcibios_set_master' defined in .text section in arch/arm/kernel/built-in.o
> 
> At a guess, it suggests your kernel image is too big for the relocations
> contained within the code.  That's something for Thumb people to look
> into and solve.

IIRC, that was not the issue I was trying to fix when I originally made the
patch. It's quite likely that the original bug was fixed already, so I'd suggest
we drop the patch for now and see if the problem comes back when all other
randconfig problems have been resolved on Tegra.

	Arnd


From hpa at zytor.com  Thu Mar  1 15:46:57 2012
From: hpa at zytor.com (H. Peter Anvin)
Date: Thu, 01 Mar 2012 12:46:57 -0800
Subject: [PATCH] mm: module_alloc: check if size is 0
In-Reply-To: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com>
References: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com>
Message-ID: <4F4FE041.1000507@zytor.com>

On 03/01/2012 11:45 AM, Veli-Pekka Peltola wrote:
> diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
> index 1e9be5d..d44d212 100644
> --- a/arch/arm/kernel/module.c
> +++ b/arch/arm/kernel/module.c
> @@ -39,8 +39,8 @@
>  #ifdef CONFIG_MMU
>  void *module_alloc(unsigned long size)
>  {
> -	return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
> -				GFP_KERNEL, PAGE_KERNEL_EXEC, -1,
> +	return size == 0 ? NULL : __vmalloc_node_range(size, 1, MODULES_VADDR,
> +				MODULES_END, GFP_KERNEL, PAGE_KERNEL_EXEC, -1,
>  				__builtin_return_address(0));
>  }
>  #endif
> diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
> index a5066b1..cd768e9 100644
> --- a/arch/mips/kernel/module.c
> +++ b/arch/mips/kernel/module.c
> @@ -47,8 +47,8 @@ static DEFINE_SPINLOCK(dbe_lock);
>  #ifdef MODULE_START
>  void *module_alloc(unsigned long size)
>  {
> -	return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END,
> -				GFP_KERNEL, PAGE_KERNEL, -1,
> +	return size == 0 ? NULL : __vmalloc_node_range(size, 1, MODULE_START,
> +				MODULE_END, GFP_KERNEL, PAGE_KERNEL, -1,
>  				__builtin_return_address(0));
>  }
>  #endif
> diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
> index 925179f..bff6118 100644
> --- a/arch/x86/kernel/module.c
> +++ b/arch/x86/kernel/module.c
> @@ -38,7 +38,7 @@
>  
>  void *module_alloc(unsigned long size)
>  {
> -	if (PAGE_ALIGN(size) > MODULES_LEN)
> +	if (size == 0 || PAGE_ALIGN(size) > MODULES_LEN)
>  		return NULL;
>  	return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
>  				GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL_EXEC,

Looks good stylistically but really awkward technically.

I would like to suggest using the idiom:

	if (!size)
		return NULL;

... consistently; combined with the PAGE_ALIGN() clause for x86 is fine too.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.



From linux at arm.linux.org.uk  Thu Mar  1 15:54:08 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 20:54:08 +0000
Subject: [PATCH 8/8] ARM: tegra: HACK: remove set_irq_flags() from driver
In-Reply-To: <CACRpkdZK+9gF7N2akyWw=tvcBS2X2FmSd2-SiNKiuRgUCYXx7w@mail.gmail.com>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-9-git-send-email-alan@signal11.us>
 <CACRpkdZK+9gF7N2akyWw=tvcBS2X2FmSd2-SiNKiuRgUCYXx7w@mail.gmail.com>
Message-ID: <20120301205408.GB19274@n2100.arm.linux.org.uk>

On Thu, Mar 01, 2012 at 09:33:03PM +0100, Linus Walleij wrote:
> On Thu, Mar 1, 2012 at 8:26 PM, Alan Ott <alan at signal11.us> wrote:
> 
> > From: Arnd Bergmann <arnd at arndb.de>
> >
> > The driver should not call set_irq_flags itself, and
> > cannot do this from a loadable module.
> >
> > Remove the call for now, which might break the driver
> > but at least lets the kernel link again.
> >
> > Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> > ---
> > ?drivers/usb/host/ehci-tegra.c | ? ?1 -
> > ?1 files changed, 0 insertions(+), 1 deletions(-)
> >
> > diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
> > index dbc7fe8..ab91f26 100644
> > --- a/drivers/usb/host/ehci-tegra.c
> > +++ b/drivers/usb/host/ehci-tegra.c
> > @@ -729,7 +729,6 @@ static int tegra_ehci_probe(struct platform_device *pdev)
> > ? ? ? ? ? ? ? ?err = -ENODEV;
> > ? ? ? ? ? ? ? ?goto fail;
> > ? ? ? ?}
> > - ? ? ? set_irq_flags(irq, IRQF_VALID);
> 
> The kernel is full of this kind of stuff (drivers/mfd/twl4030-irq.c):
> 
> #ifdef CONFIG_ARM
>         /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
>          * sets on behalf of every irq_chip.  Also sets IRQ_NOPROBE.
>          */
>         set_irq_flags(irq, IRQF_VALID);
> #else
>         /* same effect on other architectures */
>         irq_set_noprobe(irq);
> #endif
> 
> Can't we try to fix this for real instead of breaking the universe,
> hehe :-)

That depends whether you want 0..NR_IRQS to all be request-able before
they've been setup with their irq chips and handlers etc.

Unfortunately, genirq doesn't provide a standard helper to clear
IRQ_NOREQUEST, and that's why this pain persists.


From stigge at antcom.de  Thu Mar  1 15:42:21 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 01 Mar 2012 21:42:21 +0100
Subject: [PATCH v3] lpc32xx: Added ethernet driver
In-Reply-To: <201202271949.03144.arnd@arndb.de>
References: <1330364539-23152-1-git-send-email-stigge@antcom.de>
 <201202271949.03144.arnd@arndb.de>
Message-ID: <4F4FDF2D.5040508@antcom.de>

On 27/02/12 20:49, Arnd Bergmann wrote:
> Are you sure that npx is actually the origin of this controller?
> If they only licensed the IP themselves, it would be better to list
> it under the name of the actual creator so that the next person
> who has the same core can find it.

I have no hint for another origin of this core (see manual). However, as
soon as we get new info on this, we can move the driver easily.

Thanks to all of you for your suggestions, I will include all the
suggested changes an repost an updated driver.

Roland


From rob.lee at linaro.org  Thu Mar  1 15:57:54 2012
From: rob.lee at linaro.org (Rob Lee)
Date: Thu, 1 Mar 2012 14:57:54 -0600
Subject: [PATCH v7 0/9] Consolidate cpuidle functionality
In-Reply-To: <1330562578-3410-1-git-send-email-rob.lee@linaro.org>
References: <1330562578-3410-1-git-send-email-rob.lee@linaro.org>
Message-ID: <CAMXH7KGJtSyeGwEN4jz9TRPxHUjtreMHRG-4WDChB0BC88P=OA@mail.gmail.com>

On Wed, Feb 29, 2012 at 6:42 PM, Robert Lee <rob.lee at linaro.org> wrote:
> This patch series moves various functionality duplicated in platform
> cpuidle drivers to the core cpuidle driver. Also, the platform irq
> disabling was removed as it appears that all calls into
> cpuidle_call_idle will have already called local_irq_disable().
>

I'm told that I forgot to add the Acks from the previous v6 to this version:

Acked-by: Jean Pihet <j-pihet at ti.com> (v6)
Tested-by: Jean Pihet <j-pihet at ti.com> (v6, omap3)
Tested-by: Amit Daniel <amit.kachhap at linaro.org> (v6, Exynos4)
For the generic cpuidle changes:
Reviewed-by: Deepthi Dharwar <deepthi at linux.vnet.ibm.com>

If anyone sees other omissions or has any suggested changes or
improvements in my patch submissions semantics, please let me know.

Thanks,
Rob

> Rafael,
>
> Could you review this patchset and merge patch 1/9 once its ready? ?It
> seems pretty close to being acceptable. ?The get_maintainer script shows
> Len Brown as the cpuidle maintainer but I've been unable to get a response
> from him so far. ?If you are not the right person, could you suggest
> who I can make this request to? ?Thanks.
>
> Note to platform maintainers:
>
> Platform patches (2/9 to 9/9) in this patchset are not required to work
> with patch 1/9 but please review and push these platform changes as possible
> to allow this consolidation to occur.
>
> Based on 3.3-rc5 plus recent exynos cpuidle patch (affects exynos cpuidle only):
> http://www.spinics.net/lists/linux-samsung-soc/msg09467.html
>
> v6 submission tested successfully on Exynos (thanks Amit Kacchap) and OMAP3
> (thanks Jean Pihet) platforms.
>
> v6 submission can be found here:
> http://www.spinics.net/lists/arm-kernel/msg162018.html
> Changes since v6:
> * Made some ?struct whitespace alignment changes.
> * Fixed a coding style violation (thanks Jean Pihet)
> * Fixed a bug in davinci cpuidle (thanks Jean Pihet)
> * Corrected the common ARM cpuidle WFI state description to be ARM platform
> ?agnostic (thanks Kevin Hilman)
> * Fixed the problem causing x86 and PPC builds to fail (thanks Deepthi)
> * Re-added a line of code that was mistakenly removed (thanks Deepthi)
>
> Robert Lee (9):
> ?cpuidle: Add common time keeping and irq enabling
> ?ARM: at91: Consolidate time keeping and irq enable
> ?ARM: exynos: Consolidate time keeping and irq enable
> ?ARM: kirkwood: Consolidate time keeping and irq enable
> ?ARM: davinci: Consolidate time keeping and irq enable
> ?ARM: omap: Consolidate OMAP3 time keeping and irq enable
> ?ARM: omap: Consolidate OMAP4 time keeping and irq enable
> ?ARM: shmobile: Consolidate time keeping and irq enable
> ?SH: shmobile: Consolidate time keeping and irq enable
>
> ?arch/arm/include/asm/cpuidle.h ? ? ? ?| ? 22 +++++++++
> ?arch/arm/kernel/Makefile ? ? ? ? ? ? ?| ? ?2 +-
> ?arch/arm/kernel/cpuidle.c ? ? ? ? ? ? | ? 21 ++++++++
> ?arch/arm/mach-at91/cpuidle.c ? ? ? ? ?| ? 67 ++++++++++-----------------
> ?arch/arm/mach-davinci/cpuidle.c ? ? ? | ? 82 +++++++++++++-------------------
> ?arch/arm/mach-exynos/cpuidle.c ? ? ? ?| ? 53 ++-------------------
> ?arch/arm/mach-kirkwood/cpuidle.c ? ? ?| ? 72 ++++++++--------------------
> ?arch/arm/mach-omap2/cpuidle34xx.c ? ? | ? 42 +++++++----------
> ?arch/arm/mach-omap2/cpuidle44xx.c ? ? | ? 21 +-------
> ?arch/arm/mach-shmobile/cpuidle.c ? ? ?| ? 31 +++----------
> ?arch/sh/kernel/cpu/shmobile/cpuidle.c | ? 10 +---
> ?drivers/cpuidle/cpuidle.c ? ? ? ? ? ? | ? 79 +++++++++++++++++++++++++------
> ?include/linux/cpuidle.h ? ? ? ? ? ? ? | ? 13 +++++-
> ?13 files changed, 233 insertions(+), 282 deletions(-)
> ?create mode 100644 arch/arm/include/asm/cpuidle.h
> ?create mode 100644 arch/arm/kernel/cpuidle.c
>


From linux at arm.linux.org.uk  Thu Mar  1 16:00:20 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 1 Mar 2012 21:00:20 +0000
Subject: [PATCH 8/8] ARM: tegra: HACK: remove set_irq_flags() from driver
In-Reply-To: <201203012038.28062.arnd@arndb.de>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-9-git-send-email-alan@signal11.us>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE86173C@HQMAIL01.nvidia.com>
 <201203012038.28062.arnd@arndb.de>
Message-ID: <20120301210020.GC19274@n2100.arm.linux.org.uk>

On Thu, Mar 01, 2012 at 08:38:27PM +0000, Arnd Bergmann wrote:
> On Thursday 01 March 2012, Stephen Warren wrote:
> > 
> > Alan Ott wrote at Thursday, March 01, 2012 12:27 PM:
> > > From: Arnd Bergmann <arnd at arndb.de>
> > > 
> > > The driver should not call set_irq_flags itself, and
> > 
> > Probably true in this case.
> > 
> > > cannot do this from a loadable module.
> > 
> > I hope that's not true; grep'ing the entire of drivers/ shows a bunch
> > of drivers calling this function, and many look like they'd be reasonable
> > as module.
> 
> The drivers that I can see using it are for the most part implementing
> irq controllers by themselves, which is different from merely using an
> interrupt.
> 
> There are three exceptions today:
> 
> arnd at klappe2:~/linux-arm$ git grep -l set_irq_flags  drivers/ | xargs grep -L irq_chip
> drivers/tty/serial/serial_ks8695.c

Setting NOAUTOEN should be done elsewhere (in platform code.)  Better
still, fixing genirq to allow request_irq() to permit the interrupt
to be requested *without enabling it* would be a step forwards.  I
thought my original ARM IRQ code did that.

> drivers/tty/serial/sirfsoc_uart.c

Same issue, so same comments.

> drivers/usb/host/ehci-tegra.c

This one should not be there.  Having drivers mark IRQs as being
requestable when the whole point of the flag is to stop request_irq()
being used on non-initialized interrupts is just plain stupid.

> > From what little I understand of this, any irq_chip is going to call
> > that function after setting up any child/cascaded IRQs, and I assume
> > that irq_chips can be in modules.
> 
> But the function is not exported. I guess if we want to allow
> irq_chips in loadable modules, we could export it, but I don't see
> how it could ever have worked so far.

genirq does not permit flow handlers in modules - I suspect that's
because it's pretty hard to remove them safely from the system without
a lot of effort.  Certainly, a whole bunch of genirq functions which
are required to implement external flow handlers etc aren't exported.


From jason at lakedaemon.net  Thu Mar  1 16:23:53 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 1 Mar 2012 16:23:53 -0500
Subject: [PATCH 0/4] ARM: kirkwood: fdt: convert kirkwood init funcs to fdt
In-Reply-To: <201203012028.04773.arnd@arndb.de>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203011950.51210.arnd@arndb.de>
 <20120301200136.GA11986@titan.lakedaemon.net>
 <201203012028.04773.arnd@arndb.de>
Message-ID: <20120301212353.GC11986@titan.lakedaemon.net>

On Thu, Mar 01, 2012 at 08:28:04PM +0000, Arnd Bergmann wrote:
> On Thursday 01 March 2012, Jason wrote:
> > Thanks for the feedback.  I'll redo this series and resubmit.  Did you
> > catch my patch from yesterday?
> > 
> > [PATCH v3] ARM: kirkwood: covert orion-spi to fdt. [1]
> 
> Yes, I saw that. It looks good and I was just waiting if other people
> have comments on it. Maybe you can put it into the same git tree as
> these ones when they are ready and you send a pull request.

Okay, I have a local branch, 'dreamplug_dt' based at v3.3-rc3.  It
includes the two patches you've already merged into your tree:

c9780e7 ARM: kirkwood: add dreamplug (fdt) support.
dbc3c26 ARM: kirkwood: convert uart0 to devicetree.

Plus the spi/flash/partitions, and the most recent series.

Can I just do:

git push linux-kirkwood dreamplug_dt:kirkwood_dt

Then, issue a pull request for

git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt

and reference the first uncommitted patch?

Most of the googlings for 'pull request' yield github's "click the
button", yuck.

Also, is there an equivalent to 'git format-patch/send-email' for pull
requests?  The pull requests I've looked at seem awfully consistent in
formatting.

thx,

Jason.


From jason at lakedaemon.net  Thu Mar  1 16:26:20 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 1 Mar 2012 16:26:20 -0500
Subject: [PATCH 3/4] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <201203011935.58503.arnd@arndb.de>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>
 <201203011935.58503.arnd@arndb.de>
Message-ID: <20120301212620.GD11986@titan.lakedaemon.net>

On Thu, Mar 01, 2012 at 07:35:58PM +0000, Arnd Bergmann wrote:
> On Thursday 01 March 2012, Jason Cooper wrote:
> > The comment at mach-kirkwood/common.c:469, says this device is in every
> > kirkwood board.  So, it is placed in kirkwood.dtsi.
> >
> > @@ -218,10 +220,15 @@ static int __devinit mv_rtc_probe(struct platform_device *pdev)
> >  {
> >  	struct resource *res;
> >  	struct rtc_plat_data *pdata;
> > +	struct device_node *np = pdev->dev.of_node;
> >  	resource_size_t size;
> >  	u32 rtc_time;
> >  
> >  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +
> > +	if (np)
> > +		of_address_to_resource(np, 0, res);
> > +
> >  	if (!res)
> >  		return -ENODEV;
> >  
> > @@ -257,6 +264,8 @@ static int __devinit mv_rtc_probe(struct platform_device *pdev)
> >  
> >  	pdata->irq = platform_get_irq(pdev, 0);
> >  
> > +	of_property_read_u32(np, "interrupts", &pdata->irq);
> > +
> >  	platform_set_drvdata(pdev, pdata);
> >  
> >  	if (pdata->irq >= 0) {
> 
> The two additions here don't seem necessary, the second one not even
> correct: Any interrupts and register properties automatically get
> turned into platform resources when the device is instatiated.
> 
> The interrupt number should not be taken verbatim from the device tree
> because it is always local to the "interrupt-parent" node, so you would
> have to use irq_of_parse_and map rather than reading the property
> directly, but as I said you don't even need to do that for platform
> devices.

Learning everyday... :-)

thx,

Jason.


From arnd at arndb.de  Thu Mar  1 17:14:06 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 1 Mar 2012 22:14:06 +0000
Subject: [PATCH 0/4] ARM: kirkwood: fdt: convert kirkwood init funcs to fdt
In-Reply-To: <20120301212353.GC11986@titan.lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203012028.04773.arnd@arndb.de>
 <20120301212353.GC11986@titan.lakedaemon.net>
Message-ID: <201203012214.07019.arnd@arndb.de>

On Thursday 01 March 2012, Jason wrote:
> On Thu, Mar 01, 2012 at 08:28:04PM +0000, Arnd Bergmann wrote:
> > On Thursday 01 March 2012, Jason wrote:
> > > Thanks for the feedback.  I'll redo this series and resubmit.  Did you
> > > catch my patch from yesterday?
> > > 
> > > [PATCH v3] ARM: kirkwood: covert orion-spi to fdt. [1]
> > 
> > Yes, I saw that. It looks good and I was just waiting if other people
> > have comments on it. Maybe you can put it into the same git tree as
> > these ones when they are ready and you send a pull request.
> 
> Okay, I have a local branch, 'dreamplug_dt' based at v3.3-rc3.  It
> includes the two patches you've already merged into your tree:
> 
> c9780e7 ARM: kirkwood: add dreamplug (fdt) support.
> dbc3c26 ARM: kirkwood: convert uart0 to devicetree.
> 
> Plus the spi/flash/partitions, and the most recent series.
> 
> Can I just do:
> 
> git push linux-kirkwood dreamplug_dt:kirkwood_dt
> 
> Then, issue a pull request for
> 
> git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt
> 
> and reference the first uncommitted patch?

I have other commit IDs for the two patches that I took from your
emails, so you should rebase the other patches on top of the
version that I have in the arm-soc/kirkwood/board branch, otherwise
we end up with duplicate commits my tree when I pull them again.

> Most of the googlings for 'pull request' yield github's "click the
> button", yuck.
> 
> Also, is there an equivalent to 'git format-patch/send-email' for pull
> requests?  The pull requests I've looked at seem awfully consistent in
> formatting.

It's "git request-pull".

	Arnd


From jkrzyszt at tis.icnet.pl  Thu Mar  1 17:26:21 2012
From: jkrzyszt at tis.icnet.pl (Janusz Krzysztofik)
Date: Thu, 01 Mar 2012 23:26:21 +0100
Subject: [GIT PULL 3/5] First set of omap1 related changes
In-Reply-To: <20120229211331.GP18901@atomide.com>
References: <0Mfo5g-1RocQt3wlY-00NttP@mx.kundenserver.de>
 <201202292106.40731.arnd@arndb.de> <20120229211331.GP18901@atomide.com>
Message-ID: <3378572.m1z82NvySs@acer>

On Wed, 29 Feb 2012 13:13:31 Tony Lindgren wrote:
> * Arnd Bergmann <arnd at arndb.de> [120229 12:35]:
> > On Wednesday 29 February 2012, Tony Lindgren wrote:
> > >   git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap 
omap1
> > > 
> > > Janusz Krzysztofik (7):
> > >       ARM: OMAP1: ams-delta: register latch dependent devices 
later
> > >       ARM: OMAP1: ams-delta: convert latches to basic_mmio_gpio
> > >       ARM: OMAP1: ams-delta: supersede custom led device by leds-
gpio
> > >       LED: drop leds-ams-delta driver
> > >       MTD: NAND: ams-delta: use GPIO instead of custom I/O
> > >       omapfb: lcd_ams_delta: drive control lines over GPIO
> > >       input: serio: ams-delta: toggle keyboard power over GPIO
> > > 
> > 
> > Since these are all for ams-delta, I pulled them into next/boards 
together
> > with other board specific updates.
> 
> OK makes sense.

Any chance for the continuation series [1] as well as two section 
mismatch related fixes [2] [3] getting your attention? NB, that 
continuation series needs another section mismatch fix, which I was 
planing to submit once there was a stable base for it.

Thanks,
Janusz

[1] http://www.spinics.net/lists/linux-omap/msg64146.html
[2] http://www.spinics.net/lists/linux-omap/msg64441.html
[3] http://www.spinics.net/lists/linux-omap/msg64442.html


From khilman at ti.com  Thu Mar  1 17:37:09 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 01 Mar 2012 14:37:09 -0800
Subject: [PATCHv3 4/6] ARM: OMAP3 PM: Enable IO Wake up
In-Reply-To: <4F4F1CBA.7040502@ti.com> (Rajendra Nayak's message of "Thu, 01
 Mar 2012 12:22:42 +0530")
References: <1330525621-29836-1-git-send-email-t-kristo@ti.com>
 <1330525621-29836-5-git-send-email-t-kristo@ti.com>
 <4F4F1CBA.7040502@ti.com>
Message-ID: <87sjhsdk2y.fsf@ti.com>

Rajendra Nayak <rnayak at ti.com> writes:

> On Wednesday 29 February 2012 07:56 PM, Tero Kristo wrote:
>> From: Vishwanath BS<vishwanath.bs at ti.com>
>>
>> Enable IO Wake up for OMAP3 as part of PM Init. Currently this has been
>> managed in cpuidle path which is not the right place. Subsequent patch
>> will remove IO Daisy chain handling in cpuidle path once daisy chain is
>> handled as part of hwmod mux.
>>
>> Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com>
>> Tested-by: Govindraj.R<govindraj.raja at ti.com>
>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
>> ---
>>   arch/arm/mach-omap2/pm34xx.c |    4 ++++
>>   1 files changed, 4 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index e97ec3f..e6c2d39 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -793,6 +793,10 @@ static int __init omap3_pm_init(void)
>>   		goto err1;
>>   	}
>>
>> +	if (omap3_has_io_wakeup())
>> +		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
>> +					   PM_WKEN);
>
> On OMAP4 this GLOBAL IO chain enable happens as part of the trigger
> function itself, it might make sense to do that for OMAP3 too to avoid
> similar issues as seen on OMAP4 when the GLOBAL switch is enabled too
> late in boot. The best however would be to get rid of it in the trigger
> function and enable this early during PM init, but I am not sure whats
> a good place to do this 'early' enough.

What about the subsys_initcall() that's already in the prm*.c files?

IMO, the global one-time init doesn't belong in the trigger function
because there's no need to do the extra PRM read/write when it should be
a one-shot init.

Kevin




From tony at atomide.com  Thu Mar  1 18:31:01 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 1 Mar 2012 15:31:01 -0800
Subject: [GIT PULL 3/5] First set of omap1 related changes
In-Reply-To: <3378572.m1z82NvySs@acer>
References: <0Mfo5g-1RocQt3wlY-00NttP@mx.kundenserver.de>
 <201202292106.40731.arnd@arndb.de>
 <20120229211331.GP18901@atomide.com> <3378572.m1z82NvySs@acer>
Message-ID: <20120301233101.GC18901@atomide.com>

* Janusz Krzysztofik <jkrzyszt at tis.icnet.pl> [120301 13:56]:
> 
> Any chance for the continuation series [1] as well as two section 
> mismatch related fixes [2] [3] getting your attention? NB, that 
> continuation series needs another section mismatch fix, which I was 
> planing to submit once there was a stable base for it.
> 
> [1] http://www.spinics.net/lists/linux-omap/msg64146.html
> [2] http://www.spinics.net/lists/linux-omap/msg64441.html
> [3] http://www.spinics.net/lists/linux-omap/msg64442.html

Hmm sorry I guess I was waiting for the missing section
mismatch patch.

I've pushed ams-delta branch that's based on -rc5 merged
with what Arnd pulled yesterday as -rc1 has i2c-omap.c
a compile bug for omap1. I've applied these two patches
there as the second one depends on what got pulled:

ARM: OMAP1: ams-delta: clean up init data section assignments
ARM: OMAP1: ams-delta: fix incorrect section tags

Looks like your patch "ARM: OMAP1: ams-delta: set up regulator
over modem reset GPIO pin" causes the following error with
CONFIG_DEBUG_SECTION_MISMATCH=y:

arch/arm/mach-omap1/board-ams-delta.c:273:36: error:
modem_nreset_config causes a section type conflict

So care to update and repost that (and possibly the following
two patches) with your missing fixes?

Regards,

Tony


From tony at atomide.com  Thu Mar  1 19:11:21 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 1 Mar 2012 16:11:21 -0800
Subject: [PATCH] ARM: OMAP: hsmmc: add max_freq field
In-Reply-To: <CACTFLAMCoKfQbTe2RLTvi1_CH0nKzAOthAwrifNe2+F2sf3uPA@mail.gmail.com>
References: <1323868927-3738-1-git-send-email-zonque@gmail.com>
 <CANrkHUY3Zf4a2K5769Z=7Wng339zB6+z_Tgd4mOPChZ1RvZ=Kw@mail.gmail.com>
 <4EFC6992.4020501@gmail.com>
 <CACTFLAMCoKfQbTe2RLTvi1_CH0nKzAOthAwrifNe2+F2sf3uPA@mail.gmail.com>
Message-ID: <20120302001121.GE18901@atomide.com>

Hi,

* Daniel Mack <zonque at gmail.com> [120217 05:13]:
> ping? Could anyone care for queueing this please?
 
I suggest Rajendra queue up omap_hsmmc.c patches as he's already
patching it.

Regards,

Tony

 
> On Thu, Dec 29, 2011 at 2:22 PM, Daniel Mack <zonque at gmail.com> wrote:
> > On 12/23/2011 04:40 PM, T Krishnamoorthy, Balaji wrote:
> >> On Wed, Dec 14, 2011 at 6:52 PM, Daniel Mack <zonque at gmail.com> wrote:
> >>> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> >>> index 101cd31..8215ef9 100644
> >>> --- a/drivers/mmc/host/omap_hsmmc.c
> >>> +++ b/drivers/mmc/host/omap_hsmmc.c
> >>> @@ -1927,8 +1927,12 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
> >>> ? ? ? ?if (mmc_slot(host).vcc_aux_disable_is_sleep)
> >>> ? ? ? ? ? ? ? ?mmc_slot(host).no_off = 1;
> >>>
> >>> - ? ? ? mmc->f_min ? ? ?= OMAP_MMC_MIN_CLOCK;
> >>> - ? ? ? mmc->f_max ? ? ?= OMAP_MMC_MAX_CLOCK;
> >>> + ? ? ? mmc->f_min = OMAP_MMC_MIN_CLOCK;
> >>
> >> Stray change for f_min ?
> >
> > No, this was intended. The indentation doesn't make sense anymore when
> > not grouped with the f_max assignment.
> >
> > Other than that, what is necessary to get this picked? Tony? :)
> >
> >
> > Thanks,
> > Daniel


From hartleys at visionengravers.com  Thu Mar  1 19:13:59 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Thu, 1 Mar 2012 17:13:59 -0700
Subject: ARM: ep93xx: convert vision_ep9307 to MULTI_IRQ_HANDLER
Message-ID: <201203011713.59663.hartleys@visionengravers.com>

As done for the other ep93xx machines in:

commit 9a6879bd902e2ec605fff4d9fb3247b440a1f66a
ARM: ep93xx: convert to MULTI_IRQ_HANDLER

Now that there is a generic IRQ handler for multiple VIC devices use it
for vision_ep9307 to help building multi platform kernels.

Signed-off-by: Hartley Sweeten <hsweeten at visionengravers.com>
Acked-by: Ryan Mallon <rmallon at gmail.com>
Reviewed-by: Jamie Iles <jamie at jamieiles.com>

---

diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index d5fb44f..d67d0b4 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -34,6 +34,7 @@
 #include <mach/ep93xx_spi.h>
 #include <mach/gpio-ep93xx.h>
 
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
@@ -361,6 +362,7 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
 	.atag_offset	= 0x100,
 	.map_io		= vision_map_io,
 	.init_irq	= ep93xx_init_irq,
+	.handle_irq	= vic_handle_irq,
 	.timer		= &ep93xx_timer,
 	.init_machine	= vision_init_machine,
 	.restart	= ep93xx_restart,


From nm at ti.com  Thu Mar  1 19:36:01 2012
From: nm at ti.com (Menon, Nishanth)
Date: Thu, 1 Mar 2012 18:36:01 -0600
Subject: [PATCH] ARM: OMAP2+: powerdomain: unwrap and simplify logging
 strings
In-Reply-To: <alpine.DEB.2.00.1202292122560.12752@utopia.booyaka.com>
References: <alpine.DEB.2.00.1202292122560.12752@utopia.booyaka.com>
Message-ID: <CAOMWX4cAABO8jUCi8g_vbv6SnU3vPcqOULV6ui2jV7E2Nt8g0Q@mail.gmail.com>

On Wed, Feb 29, 2012 at 22:23, Paul Walmsley <paul at pwsan.com> wrote:
> b/arch/arm/mach-omap2/powerdomain.c
> index 8a18d1b..89000d3 100644
> --- a/arch/arm/mach-omap2/powerdomain.c
> +++ b/arch/arm/mach-omap2/powerdomain.c
> @@ -339,8 +339,8 @@ int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct
> clockdomain *clkdm)
> ? ? ? ?if (!pwrdm || !clkdm)
> ? ? ? ? ? ? ? ?return -EINVAL;
>
> - ? ? ? pr_debug("powerdomain: associating clockdomain %s with powerdomain
> "
> - ? ? ? ? ? ? ? ?"%s\n", clkdm->name, pwrdm->name);
> + ? ? ? pr_debug("powerdomain: %s: associating clockdomain %s\n",
> + ? ? ? ? ? ? ? ?clkdm->name, pwrdm->name);

while at this, could i suggest having instead:
pr_debug("%s: %s: associating clockdomain %s\n", __func__,
                clkdm->name, pwrdm->name);
since the function name helps associate the message back in, wont it
be a bit of a dual edged information as well?

or even simplify it further with

#define pr_fmt(fmt)  "%s:%s: " fmt, "powerdomain", __func__
?
Regards,
Nishanth Menon


From paul at pwsan.com  Thu Mar  1 20:08:37 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 1 Mar 2012 18:08:37 -0700 (MST)
Subject: [PATCH] ARM: OMAP: hwmod: Use sysc_fields->srst_shift and get
 rid of hardcoded SYSC_TYPE2_SOFTRESET_MASK
In-Reply-To: <1330609674-20826-1-git-send-email-rnayak@ti.com>
References: <1330609674-20826-1-git-send-email-rnayak@ti.com>
Message-ID: <alpine.DEB.2.00.1203011808070.22980@utopia.booyaka.com>

On Thu, 1 Mar 2012, Rajendra Nayak wrote:

> This is useful when we have broken type2 compliant IPs' where
> the softreset shift is not the same as SYSC_TYPE2_SOFTRESET_SHIFT
> and hence is overridden using sysc_fields->srst_shift.
> 
> We have atleast one such instance now with onchip keypad on OMAP5
> which has a different softreset shift as compared to other type2
> IPs'.
> 
> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Balaji TK  <balajitk at ti.com>
> Tested-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
> Paul,
> 
> I based the patch on top of your reset/data cleanup series
> for hwmod. So its based on 'hwmod_data_cleanup_3.4' branch.

Thanks, Beno?t's ack added and queued.


- Paul

From thomas.abraham at linaro.org  Thu Mar  1 21:01:16 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 2 Mar 2012 07:31:16 +0530
Subject: [PATCH v2 1/2] ARM: EXYNOS: Add USB HOST register definitions
In-Reply-To: <CADPsn1ZfXqmOVtw5OdfbXv=xZ3EREbPqCRnpnsYHbhkvx=nb5Q@mail.gmail.com>
References: <000701ccf76d$8316b0a0$894411e0$%han@samsung.com>
 <201203011624.04551.heiko@sntech.de>
 <CADPsn1ZfXqmOVtw5OdfbXv=xZ3EREbPqCRnpnsYHbhkvx=nb5Q@mail.gmail.com>
Message-ID: <CAJuYYwSiKAbMz68GQWCnD9po-cf6=xpWj-wQRcvj4kwneG0sMg@mail.gmail.com>

On 1 March 2012 21:40, Sangwook Lee <sangwook.lee at linaro.org> wrote:
[...]

> ?I found out some code related to this burst function.
>
> ?the snip from ehci-s5pv210.c, 2.6.35 kernel
>
> ??????? /* Mark hardware accessible again as we are out of D3 state by now
> */
> ??????? set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
> #if defined(CONFIG_ARCH_S5PV210) || defined(CONFIG_ARCH_S5P6450)
> ??????? ehci_writel(ehci, 0x000F0000, (void __iomem *)ehci->caps + 0x90);
> #endif
>
> #if defined(CONFIG_ARCH_S5PV310)
> ??????? ehci_writel(ehci, 0x03C00000, (void __iomem *)ehci->caps + 0x90);
> #endif
> ??????? if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
>
> From this code, this burst function seems to be depending on CPUs,
> The driver by itself is not good idea because echi-s5p.c will have defined.
>
> Which is the better place to pus this CPU specific definition either
> drivers/usb/host/ehci-s5p.h is
> or mach/xx.h or? include/linux/usb/xxx.h ?? I am not clear about this.

Any configuration that is controller specific should be in the driver.
If that configuration has a SoC specific behavior, a id_table can be
provided to the platform_driver which can provide any SoC specific
information. The samsung keypad driver is an example of how this can
be handled (drivers/input/keyboard/samsung.c).

Thanks,
Thomas.


From Barry.Song at csr.com  Thu Mar  1 21:52:22 2012
From: Barry.Song at csr.com (Barry Song)
Date: Fri, 2 Mar 2012 10:52:22 +0800
Subject: [PATCH] MM: CMA: add a simple kernel module as the helper to test CMA
Message-ID: <1330656742-5233-1-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

Any write request to /dev/cma_test will let the module to allocate memory from
CMA, for example:

1st time
$ echo 0 > /dev/cma_test
will require cma_test to request 1MB
2nd time
$ echo 0 > /dev/cma_test
will require cma_test to request 2MB

Any read request to /dev/cma_test will let the module to free memory from CMA,
for example:

1st time
$ cat /dev/cma_test
will require cma_test to free the 1MB allocated in the first write request
2nd time
$ echo 0 > /dev/cma_test
will require cma_test to free the 2MB allocated in the second write request

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 tools/cma/Makefile   |   13 ++++++
 tools/cma/cma_test.c |  108 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 121 insertions(+), 0 deletions(-)
 create mode 100644 tools/cma/Makefile
 create mode 100644 tools/cma/cma_test.c

diff --git a/tools/cma/Makefile b/tools/cma/Makefile
new file mode 100644
index 0000000..d15c2c0
--- /dev/null
+++ b/tools/cma/Makefile
@@ -0,0 +1,13 @@
+# Kernel modules
+#
+# To compile for ARM:
+# make ARCH=arm CC=arm-none-linux-gnueabi-gcc
+#
+obj-m	+= cma_test.o
+
+build: kernel_modules
+
+kernel_modules:
+	${MAKE} -C $(CURDIR)/../.. M=$(CURDIR)
+clean:
+	${MAKE} -C $(CURDIR)/../.. M=$(CURDIR) clean
diff --git a/tools/cma/cma_test.c b/tools/cma/cma_test.c
new file mode 100644
index 0000000..3ee89f3
--- /dev/null
+++ b/tools/cma/cma_test.c
@@ -0,0 +1,108 @@
+/*
+ * kernel module helper for testing CMA
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/dma-mapping.h>
+
+#define CMA_NUM  10
+static struct device *cma_dev;
+static dma_addr_t dma_phys[CMA_NUM];
+static void *dma_virt[CMA_NUM];
+
+/* any read request will free coherent memory, eg.
+ * cat /dev/cma_test
+ */
+static ssize_t
+cma_test_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
+{
+	int i;
+
+	for (i = 0; i < CMA_NUM; i++) {
+		if (dma_virt[i]) {
+			dma_free_coherent(cma_dev, (i + 1) * SZ_1M, dma_virt[i], dma_phys[i]);
+			_dev_info(cma_dev, "free virt: %p phys: %p\n", dma_virt[i], (void *)dma_phys[i]);
+			dma_virt[i] = NULL;
+			break;
+		}
+	}
+	return 0;
+}
+
+/*
+ * any write request will alloc coherent memory, eg.
+ * echo 0 > /dev/cma_test
+ */
+static ssize_t
+cma_test_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
+{
+	int i;
+	int ret;
+
+	for (i = 0; i < CMA_NUM; i++) {
+		if (!dma_virt[i]) {
+			dma_virt[i] = dma_alloc_coherent(cma_dev, (i + 1) * SZ_1M, &dma_phys[i], GFP_KERNEL);
+
+			if (dma_virt[i]) {
+				void *p;
+				/* touch every page in the allocated memory */
+				for (p = dma_virt[i]; p <  dma_virt[i] + (i + 1) * SZ_1M; p += PAGE_SIZE)
+					*(u32 *)p = 0;
+
+				_dev_info(cma_dev, "alloc virt: %p phys: %p\n", dma_virt[i], (void *)dma_phys[i]);
+			} else {
+				dev_err(cma_dev, "no mem in CMA area\n");
+				ret = -ENOMEM;
+			}
+			break;
+		}
+	}
+
+	return count;
+}
+
+static const struct file_operations cma_test_fops = {
+	.owner =    THIS_MODULE,
+	.read  =    cma_test_read,
+	.write =    cma_test_write,
+};
+
+static struct miscdevice cma_test_misc = {
+	.name = "cma_test",
+	.fops = &cma_test_fops,
+};
+
+static int __init cma_test_init(void)
+{
+	int ret = 0;
+
+	ret = misc_register(&cma_test_misc);
+	if (unlikely(ret)) {
+		pr_err("failed to register cma test misc device!\n");
+		return ret;
+	}
+	cma_dev = cma_test_misc.this_device;
+	cma_dev->coherent_dma_mask = ~0;
+	_dev_info(cma_dev, "registered.\n");
+
+	return ret;
+}
+module_init(cma_test_init);
+
+static void __exit cma_test_exit(void)
+{
+	misc_deregister(&cma_test_misc);
+}
+module_exit(cma_test_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Barry Song <Baohua.Song at csr.com>");
+MODULE_DESCRIPTION("kernel module to help the test of CMA");
+MODULE_ALIAS("CMA test");
-- 
1.7.1



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From robherring2 at gmail.com  Thu Mar  1 22:13:12 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:12 -0600
Subject: [PATCH v3 00/30] mach/io.h cleanup and removal
Message-ID: <1330658022-14559-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

The last version got bounced from lists with too many CC's, so I've cut
back the CC lists.

This series removes mach/io.h from all but a few platforms. The major change
from the last version is the addition of fixed PCI I/O mapping and coverting
most PCI platforms over. I don't have any platforms with PCI to test on, so
I need people to test. Dove and Kirkwood with 2 buses in particular need
testing.

Changes from last version:
- use pfn rather than phys addr as some platforms have >32-bit addresses
- move pci_map_io (now pci_map_io_pfn) into bios32.c
- omap and davinci mach/io.h fixes
- remove Tegra MMIO_BASE define
- move ep93xx IO_MEM define
- fix some compile breaks

I'd like to merge the first 19 patches for 3.4. The PCI changes need time
to review and test, so they I don't think they will get sorted out in time.

These are the remaining io.h headers and reasons they are still needed:

Non-standard io accessors or mapping:
arch/arm/mach-ebsa110/include/mach/io.h
arch/arm/mach-rpc/include/mach/io.h
arch/arm/mach-s3c2410/include/mach/io.h
arch/arm/mach-ixp4xx/include/mach/io.h

Probably can be fixed, but needs more work on PCI mapping and resources:
arch/arm/mach-mv78xx0/include/mach/io.h
arch/arm/mach-iop32x/include/mach/io.h
arch/arm/mach-iop33x/include/mach/io.h

Propose removing the platform altogether:
arch/arm/mach-ixp2000/include/mach/io.h

See http://www.spinics.net/lists/arm-kernel/msg161977.html

Only needed for !CONFIG_MMU:
arch/arm/mach-footbridge/include/mach/io.h


This is based on at91 and omap io.h clean-up from these 2 trees queued for
3.4:
git://github.com/at91linux/linux-at91 at91-3.4-for_cleanup2
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap iomap

This series is available here:
git://sources.calxeda.com/kernel/linux.git io-cleanup

Rob

Arnd Bergmann (1):
  iop13xx: use more regular PCI I/O space handling

Rob Herring (28):
  usb: ohci-pxa27x: add explicit include of hardware.h
  ARM: provide runtime hook for ioremap/iounmap
  ARM: imx: convert to common runtime ioremap hook
  ARM: msm: use runtime ioremap hook
  ARM: msm: clean-up mach/io.h
  ARM: iop13xx: use runtime ioremap hook
  ARM: iop13xx: move io.h externs to pci.h
  [media] davinci: remove includes of mach/io.h
  ARM: davinci: remove unneeded mach/io.h include
  ARM: orion5x: clean-up mach/io.h
  ARM: tegra: clean-up mach/io.h
  ARM: ep93xx: clean-up mach/io.h
  ARM: at91: add explicit include of hardware.h to uncompressor
  ARM: dove: add explicit include of dove.h to addr-map.c
  ARM: clps711x: remove unneeded include of mach/io.h
  ARM: make mach/io.h include optional
  ARM: remove bunch of now unused mach/io.h files
  ARM: kill off __mem_pci
  ARM: Add fixed PCI i/o mapping
  ARM: tegra: use fixed PCI i/o mapping
  ARM: integrator: use fixed PCI i/o mapping
  ARM: shark: use fixed PCI i/o mapping
  ARM: footbridge: use fixed PCI i/o mapping
  ARM: dove: use fixed PCI i/o mapping
  ARM: kirkwood: use fixed PCI i/o mapping
  ARM: ixp23xx: use fixed PCI i/o mapping
  ARM: iop13xx: use fixed PCI i/o mapping
  ARM: orion5x: use fixed PCI i/o mapping

Tony Lindgren (1):
  ARM: OMAP: Remove remaining includes for mach/io.h

 arch/arm/Kconfig                                   |   12 +++
 arch/arm/include/asm/io.h                          |   62 +++++++------
 arch/arm/include/asm/mach/pci.h                    |   18 ++++
 arch/arm/kernel/bios32.c                           |   23 +++++
 arch/arm/mach-at91/include/mach/io.h               |   31 -------
 arch/arm/mach-at91/include/mach/uncompress.h       |    1 +
 arch/arm/mach-bcmring/include/mach/io.h            |   33 -------
 arch/arm/mach-clps711x/include/mach/io.h           |   36 --------
 arch/arm/mach-clps711x/include/mach/uncompress.h   |    1 -
 arch/arm/mach-cns3xxx/include/mach/io.h            |   17 ----
 arch/arm/mach-davinci/include/mach/entry-macro.S   |    1 -
 arch/arm/mach-davinci/include/mach/io.h            |   24 -----
 arch/arm/mach-dove/addr-map.c                      |    1 +
 arch/arm/mach-dove/common.c                        |   15 +--
 arch/arm/mach-dove/include/mach/dove.h             |    8 +-
 arch/arm/mach-dove/include/mach/io.h               |   20 ----
 arch/arm/mach-dove/pcie.c                          |    9 +--
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h    |    9 ++
 arch/arm/mach-ep93xx/include/mach/io.h             |   22 -----
 arch/arm/mach-exynos/include/mach/io.h             |   26 ------
 arch/arm/mach-footbridge/common.c                  |   12 +--
 .../arm/mach-footbridge/include/mach/debug-macro.S |    3 +-
 arch/arm/mach-footbridge/include/mach/io.h         |   25 +-----
 arch/arm/mach-gemini/include/mach/io.h             |   18 ----
 arch/arm/mach-h720x/include/mach/io.h              |   22 -----
 arch/arm/mach-highbank/include/mach/io.h           |    7 --
 arch/arm/mach-imx/mm-imx3.c                        |    4 +-
 arch/arm/mach-integrator/include/mach/io.h         |   34 -------
 arch/arm/mach-integrator/include/mach/platform.h   |    4 +
 arch/arm/mach-integrator/integrator_ap.c           |   11 +--
 arch/arm/mach-iop13xx/include/mach/io.h            |   41 ---------
 arch/arm/mach-iop13xx/include/mach/iop13xx.h       |   15 +---
 arch/arm/mach-iop13xx/io.c                         |   37 ++------
 arch/arm/mach-iop13xx/iq81340mc.c                  |    1 +
 arch/arm/mach-iop13xx/iq81340sc.c                  |    1 +
 arch/arm/mach-iop13xx/pci.c                        |   12 ++--
 arch/arm/mach-iop13xx/pci.h                        |    6 ++
 arch/arm/mach-iop13xx/setup.c                      |   17 ++--
 arch/arm/mach-iop32x/include/mach/io.h             |    1 -
 arch/arm/mach-iop33x/include/mach/io.h             |    1 -
 arch/arm/mach-ixp2000/include/mach/io.h            |    1 -
 arch/arm/mach-ixp23xx/core.c                       |    7 +-
 arch/arm/mach-ixp23xx/include/mach/io.h            |   23 -----
 arch/arm/mach-ixp23xx/include/mach/ixp23xx.h       |   20 ++---
 arch/arm/mach-ixp23xx/pci.c                        |    2 +-
 arch/arm/mach-ixp4xx/include/mach/io.h             |    6 +-
 arch/arm/mach-kirkwood/common.c                    |   21 ++---
 arch/arm/mach-kirkwood/include/mach/io.h           |   26 ------
 arch/arm/mach-kirkwood/include/mach/kirkwood.h     |    8 +-
 arch/arm/mach-kirkwood/pcie.c                      |    8 +-
 arch/arm/mach-ks8695/include/mach/io.h             |   19 ----
 arch/arm/mach-lpc32xx/include/mach/io.h            |   27 ------
 arch/arm/mach-mmp/include/mach/io.h                |   21 -----
 arch/arm/mach-msm/board-halibut.c                  |    6 ++
 arch/arm/mach-msm/board-trout.c                    |    6 ++
 arch/arm/mach-msm/include/mach/io.h                |   36 --------
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h    |    6 ++
 arch/arm/mach-msm/include/mach/msm_iomap-7x30.h    |    4 +
 arch/arm/mach-msm/include/mach/msm_iomap-8960.h    |    4 +
 arch/arm/mach-msm/include/mach/msm_iomap-8x50.h    |    4 +
 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h    |    4 +
 arch/arm/mach-msm/io.c                             |    1 -
 arch/arm/mach-mv78xx0/include/mach/io.h            |    2 -
 arch/arm/mach-mxs/include/mach/io.h                |   22 -----
 arch/arm/mach-netx/include/mach/io.h               |   28 ------
 arch/arm/mach-nomadik/include/mach/io.h            |   22 -----
 arch/arm/mach-omap1/include/mach/entry-macro.S     |    1 -
 arch/arm/mach-omap1/include/mach/io.h              |   46 ----------
 arch/arm/mach-omap1/sram.S                         |    1 -
 arch/arm/mach-omap2/include/mach/io.h              |   49 ----------
 arch/arm/mach-orion5x/common.c                     |   16 ++--
 arch/arm/mach-orion5x/common.h                     |    9 ++
 arch/arm/mach-orion5x/include/mach/io.h            |   33 -------
 arch/arm/mach-orion5x/pci.c                        |    1 +
 arch/arm/mach-orion5x/tsx09-common.c               |    1 +
 arch/arm/mach-picoxcell/include/mach/io.h          |   22 -----
 arch/arm/mach-pnx4008/include/mach/io.h            |   21 -----
 arch/arm/mach-prima2/include/mach/io.h             |   16 ----
 arch/arm/mach-pxa/include/mach/io.h                |   20 ----
 arch/arm/mach-realview/include/mach/io.h           |   28 ------
 arch/arm/mach-rpc/include/mach/io.h                |    5 -
 arch/arm/mach-s3c2410/include/mach/io.h            |    5 -
 arch/arm/mach-s3c64xx/include/mach/io.h            |   18 ----
 arch/arm/mach-s5p64x0/include/mach/io.h            |   25 -----
 arch/arm/mach-s5pc100/include/mach/io.h            |   18 ----
 arch/arm/mach-s5pv210/include/mach/io.h            |   26 ------
 arch/arm/mach-sa1100/include/mach/io.h             |   20 ----
 arch/arm/mach-shark/core.c                         |   14 +---
 arch/arm/mach-shark/include/mach/debug-macro.S     |    7 +-
 arch/arm/mach-shark/include/mach/entry-macro.S     |    3 +-
 arch/arm/mach-shark/include/mach/io.h              |   20 ----
 arch/arm/mach-shmobile/include/mach/io.h           |    9 --
 arch/arm/mach-spear3xx/include/mach/io.h           |   19 ----
 arch/arm/mach-spear6xx/include/mach/io.h           |   20 ----
 arch/arm/mach-tegra/include/mach/debug-macro.S     |    1 -
 arch/arm/mach-tegra/include/mach/io.h              |   95 --------------------
 arch/arm/mach-tegra/include/mach/iomap.h           |   51 +++++++++++
 arch/arm/mach-tegra/io.c                           |    3 +
 arch/arm/mach-tegra/pcie.c                         |   41 +--------
 arch/arm/mach-u300/include/mach/io.h               |   20 ----
 arch/arm/mach-ux500/include/mach/io.h              |   22 -----
 arch/arm/mach-versatile/include/mach/io.h          |   28 ------
 arch/arm/mach-vexpress/include/mach/io.h           |   26 ------
 arch/arm/mach-vt8500/include/mach/io.h             |   26 ------
 arch/arm/mach-w90x900/include/mach/io.h            |   30 ------
 arch/arm/mach-zynq/include/mach/io.h               |   33 -------
 arch/arm/mm/ioremap.c                              |    6 ++
 arch/arm/plat-mxc/include/mach/hardware.h          |    3 +
 arch/arm/plat-mxc/include/mach/io.h                |   39 --------
 arch/arm/plat-omap/include/plat/sdrc.h             |    1 -
 arch/arm/plat-spear/include/plat/io.h              |   22 -----
 drivers/media/video/davinci/vpbe_osd.c             |    1 -
 drivers/media/video/davinci/vpbe_venc.c            |    1 -
 drivers/usb/host/ohci-pxa27x.c                     |    1 +
 drivers/video/omap2/vrfb.c                         |    1 -
 115 files changed, 315 insertions(+), 1584 deletions(-)
 delete mode 100644 arch/arm/mach-at91/include/mach/io.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/io.h
 delete mode 100644 arch/arm/mach-clps711x/include/mach/io.h
 delete mode 100644 arch/arm/mach-cns3xxx/include/mach/io.h
 delete mode 100644 arch/arm/mach-davinci/include/mach/io.h
 delete mode 100644 arch/arm/mach-dove/include/mach/io.h
 delete mode 100644 arch/arm/mach-ep93xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/io.h
 delete mode 100644 arch/arm/mach-gemini/include/mach/io.h
 delete mode 100644 arch/arm/mach-h720x/include/mach/io.h
 delete mode 100644 arch/arm/mach-highbank/include/mach/io.h
 delete mode 100644 arch/arm/mach-integrator/include/mach/io.h
 delete mode 100644 arch/arm/mach-iop13xx/include/mach/io.h
 create mode 100644 arch/arm/mach-iop13xx/pci.h
 delete mode 100644 arch/arm/mach-ixp23xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-kirkwood/include/mach/io.h
 delete mode 100644 arch/arm/mach-ks8695/include/mach/io.h
 delete mode 100644 arch/arm/mach-lpc32xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/io.h
 delete mode 100644 arch/arm/mach-msm/include/mach/io.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/io.h
 delete mode 100644 arch/arm/mach-netx/include/mach/io.h
 delete mode 100644 arch/arm/mach-nomadik/include/mach/io.h
 delete mode 100644 arch/arm/mach-omap1/include/mach/io.h
 delete mode 100644 arch/arm/mach-omap2/include/mach/io.h
 delete mode 100644 arch/arm/mach-orion5x/include/mach/io.h
 delete mode 100644 arch/arm/mach-picoxcell/include/mach/io.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/io.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/io.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/io.h
 delete mode 100644 arch/arm/mach-realview/include/mach/io.h
 delete mode 100644 arch/arm/mach-s3c64xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/io.h
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/io.h
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/io.h
 delete mode 100644 arch/arm/mach-sa1100/include/mach/io.h
 delete mode 100644 arch/arm/mach-shark/include/mach/io.h
 delete mode 100644 arch/arm/mach-shmobile/include/mach/io.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-tegra/include/mach/io.h
 delete mode 100644 arch/arm/mach-u300/include/mach/io.h
 delete mode 100644 arch/arm/mach-ux500/include/mach/io.h
 delete mode 100644 arch/arm/mach-versatile/include/mach/io.h
 delete mode 100644 arch/arm/mach-vexpress/include/mach/io.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/io.h
 delete mode 100644 arch/arm/mach-w90x900/include/mach/io.h
 delete mode 100644 arch/arm/mach-zynq/include/mach/io.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/io.h
 delete mode 100644 arch/arm/plat-spear/include/plat/io.h

-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:13 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:13 -0600
Subject: [PATCH v3 01/30] usb: ohci-pxa27x: add explicit include of hardware.h
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-2-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

ohci-pxa27x needs cpu_is_pxa3xx macro.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: linux-usb at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
---
 drivers/usb/host/ohci-pxa27x.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index 6313e44..4db399c 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -23,6 +23,7 @@
 #include <linux/signal.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <mach/hardware.h>
 #include <mach/ohci.h>
 #include <mach/pxa3xx-u2d.h>
 
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:14 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:14 -0600
Subject: [PATCH v3 02/30] ARM: provide runtime hook for ioremap/iounmap
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-3-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

We have compile time over-ride of ioremap and iounmap, but an run-time
override is needed for multi-platform builds.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/include/asm/io.h |    8 ++++++--
 arch/arm/mm/ioremap.c     |    6 ++++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 9275828..9bf9d00 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -264,9 +264,13 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
  * Documentation/io-mapping.txt.
  *
  */
+
+extern void __iomem * (*arch_ioremap)(unsigned long, size_t, unsigned int);
+extern void (*arch_iounmap)(volatile void __iomem *);
+
 #ifndef __arch_ioremap
-#define __arch_ioremap			__arm_ioremap
-#define __arch_iounmap			__iounmap
+#define __arch_ioremap			arch_ioremap
+#define __arch_iounmap			arch_iounmap
 #endif
 
 #define ioremap(cookie,size)		__arch_ioremap((cookie), (size), MT_DEVICE)
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 80632e8..d164dea 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -314,6 +314,9 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
+void __iomem * (*arch_ioremap)(unsigned long , size_t , unsigned int ) = __arm_ioremap;
+EXPORT_SYMBOL(arch_ioremap);
+
 /*
  * Remap an arbitrary physical address space into the kernel virtual
  * address space as memory. Needed when the kernel wants to execute
@@ -370,3 +373,6 @@ void __iounmap(volatile void __iomem *io_addr)
 	vunmap(addr);
 }
 EXPORT_SYMBOL(__iounmap);
+
+void (*arch_iounmap)(volatile void __iomem *) = __iounmap;
+EXPORT_SYMBOL(arch_iounmap);
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:15 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:15 -0600
Subject: [PATCH v3 03/30] ARM: imx: convert to common runtime ioremap hook
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-4-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert i.MX platforms to use the common run-time ioremap hook instead of
the imx specific hook.

Also, move addr_in_module out of io.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Sascha Hauer <kernel at pengutronix.de>
---
 arch/arm/mach-imx/mm-imx3.c               |    4 ++--
 arch/arm/plat-mxc/include/mach/hardware.h |    3 +++
 arch/arm/plat-mxc/include/mach/io.h       |   17 -----------------
 3 files changed, 5 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 8404ee7..9db7c8d 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -132,7 +132,7 @@ void __init imx31_init_early(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX31);
 	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-	imx_ioremap = imx3_ioremap;
+	arch_ioremap = imx3_ioremap;
 	arm_pm_idle = imx3_idle;
 }
 
@@ -196,7 +196,7 @@ void __init imx35_init_early(void)
 	mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
 	mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
 	arm_pm_idle = imx3_idle;
-	imx_ioremap = imx3_ioremap;
+	arch_ioremap = imx3_ioremap;
 }
 
 void __init mx35_init_irq(void)
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index a599f01..ca06a68 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -28,6 +28,9 @@
 #define IOMEM(addr)	((void __force __iomem *)(addr))
 #endif
 
+#define addr_in_module(addr, mod) \
+	((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
+
 #define IMX_IO_P2V_MODULE(addr, module)					\
 	(((addr) - module ## _BASE_ADDR) < module ## _SIZE ?		\
 	 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index 338300b..ea9d95e 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -14,23 +14,6 @@
 /* Allow IO space to be anywhere in the memory */
 #define IO_SPACE_LIMIT 0xffffffff
 
-#define __arch_ioremap __imx_ioremap
-#define __arch_iounmap __iounmap
-
-#define addr_in_module(addr, mod) \
-	((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
-
-extern void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int);
-
-static inline void __iomem *
-__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
-{
-	if (imx_ioremap != NULL)
-		return imx_ioremap(phys_addr, size, mtype);
-	else
-		return __arm_ioremap(phys_addr, size, mtype);
-}
-
 /* io address mapping macro */
 #define __io(a)		__typesafe_io(a)
 
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:16 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:16 -0600
Subject: [PATCH v3 04/30] ARM: msm: use runtime ioremap hook
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-5-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert msm platforms to use run-time ioremap hook instead of the compile
time hook.

According to David Brown, only the msm7201 needed the ioremap hook.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Tested-by: David Brown <davidb at codeaurora.org>
Acked-by: David Brown <davidb at codeaurora.org>
Cc: Daniel Walker <dwalker at fifo99.com>
Cc: Bryan Huntsman <bryanh at codeaurora.org>
---
 arch/arm/mach-msm/board-halibut.c               |    6 ++++++
 arch/arm/mach-msm/board-trout.c                 |    6 ++++++
 arch/arm/mach-msm/include/mach/io.h             |    5 -----
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |    6 ++++++
 arch/arm/mach-msm/io.c                          |    1 -
 5 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index a60ab6d..b6cff3a 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -68,6 +68,11 @@ static struct platform_device *devices[] __initdata = {
 
 extern struct sys_timer msm_timer;
 
+static void __init halibut_init_early(void)
+{
+	arch_ioremap = __msm_ioremap;
+}
+
 static void __init halibut_init_irq(void)
 {
 	msm_init_irq();
@@ -96,6 +101,7 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
 	.atag_offset	= 0x100,
 	.fixup		= halibut_fixup,
 	.map_io		= halibut_map_io,
+	.init_early	= halibut_init_early,
 	.init_irq	= halibut_init_irq,
 	.init_machine	= halibut_init,
 	.timer		= &msm_timer,
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 6b9b227..509d94c 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -43,6 +43,11 @@ static struct platform_device *devices[] __initdata = {
 
 extern struct sys_timer msm_timer;
 
+static void __init trout_init_early(void)
+{
+	arch_ioremap = __msm_ioremap;
+}
+
 static void __init trout_init_irq(void)
 {
 	msm_init_irq();
@@ -96,6 +101,7 @@ MACHINE_START(TROUT, "HTC Dream")
 	.atag_offset	= 0x100,
 	.fixup		= trout_fixup,
 	.map_io		= trout_map_io,
+	.init_early	= trout_init_early,
 	.init_irq	= trout_init_irq,
 	.init_machine	= trout_init,
 	.timer		= &msm_timer,
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index dc1b928..c6ff9bb 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -18,11 +18,6 @@
 
 #define IO_SPACE_LIMIT 0xffffffff
 
-#define __arch_ioremap __msm_ioremap
-#define __arch_iounmap __iounmap
-
-void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)    (a)
 
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 8af4612..c355886 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -111,5 +111,11 @@
 #define MSM_AD5_PHYS          0xAC000000
 #define MSM_AD5_SIZE          (SZ_1M*13)
 
+#ifndef __ASSEMBLY__
+
+extern void __iomem *
+__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
+
+#endif
 
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 578b04e..283cdff 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -187,4 +187,3 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 	return __arm_ioremap_caller(phys_addr, size, mtype,
 		__builtin_return_address(0));
 }
-EXPORT_SYMBOL(__msm_ioremap);
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:17 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:17 -0600
Subject: [PATCH v3 05/30] ARM: msm: clean-up mach/io.h
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-6-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Move msm specifics in mach/io.h to respective msm_iomap-*.h headers.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: David Brown <davidb at codeaurora.org>
Cc: Daniel Walker <dwalker at fifo99.com>
Cc: Bryan Huntsman <bryanh at codeaurora.org>
---
 arch/arm/mach-msm/include/mach/io.h             |    7 -------
 arch/arm/mach-msm/include/mach/msm_iomap-7x30.h |    4 ++++
 arch/arm/mach-msm/include/mach/msm_iomap-8960.h |    4 ++++
 arch/arm/mach-msm/include/mach/msm_iomap-8x50.h |    4 ++++
 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h |    4 ++++
 5 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index c6ff9bb..1071f98 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -21,11 +21,4 @@
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)    (a)
 
-void msm_map_qsd8x50_io(void);
-void msm_map_msm7x30_io(void);
-void msm_map_msm8x60_io(void);
-void msm_map_msm8960_io(void);
-
-extern unsigned int msm_shared_ram_phys;
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 198202c..f944fe6 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -100,4 +100,8 @@
 #define MSM_HSUSB_PHYS        0xA3600000
 #define MSM_HSUSB_SIZE        SZ_1K
 
+#ifndef __ASSEMBLY__
+extern void msm_map_msm7x30_io(void);
+#endif
+
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index 800b557..a1752c0 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -50,4 +50,8 @@
 #define MSM_DEBUG_UART_PHYS	0x16440000
 #endif
 
+#ifndef __ASSEMBLY__
+extern void msm_map_msm8960_io(void);
+#endif
+
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index 0faa894..da77cc1 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -122,4 +122,8 @@
 #define MSM_SDC4_PHYS          0xA0600000
 #define MSM_SDC4_SIZE          SZ_4K
 
+#ifndef __ASSEMBLY__
+extern void msm_map_qsd8x50_io(void);
+#endif
+
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 54e12ca..5aed57d 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -67,4 +67,8 @@
 #define MSM_DEBUG_UART_PHYS	0x19C40000
 #endif
 
+#ifndef __ASSEMBLY__
+extern void msm_map_msm8x60_io(void);
+#endif
+
 #endif
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:18 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:18 -0600
Subject: [PATCH v3 06/30] ARM: iop13xx: use runtime ioremap hook
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-7-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert iop13xx platforms to use run-time ioremap hook instead of the
compile time hook. The custom ioremap is still needed for 64-bit address
handling.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/mach-iop13xx/include/mach/io.h |    7 -------
 arch/arm/mach-iop13xx/io.c              |   10 ++++++++--
 arch/arm/mach-iop13xx/iq81340mc.c       |    1 +
 arch/arm/mach-iop13xx/iq81340sc.c       |    1 +
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index dffb234..2a69fc0 100644
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -26,16 +26,9 @@
 #define __mem_isa(a) (a)
 
 extern void __iomem * __iop13xx_io(unsigned long io_addr);
-extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
-	unsigned int mtype);
-extern void __iop13xx_iounmap(void __iomem *addr);
-
 extern u32 iop13xx_atue_mem_base;
 extern u32 iop13xx_atux_mem_base;
 extern size_t iop13xx_atue_mem_size;
 extern size_t iop13xx_atux_mem_size;
 
-#define __arch_ioremap	__iop13xx_ioremap
-#define __arch_iounmap	__iop13xx_iounmap
-
 #endif
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 48642e6..d63585e 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -40,7 +40,7 @@ void * __iomem __iop13xx_io(unsigned long io_addr)
 }
 EXPORT_SYMBOL(__iop13xx_io);
 
-void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
+void __iomem * __iop13xx_ioremap(unsigned long cookie, size_t size,
 	unsigned int mtype)
 {
 	void __iomem * retval;
@@ -83,7 +83,7 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
 }
 EXPORT_SYMBOL(__iop13xx_ioremap);
 
-void __iop13xx_iounmap(void __iomem *addr)
+void __iop13xx_iounmap(volatile void __iomem *addr)
 {
 	extern void __iounmap(volatile void __iomem *addr);
 
@@ -111,3 +111,9 @@ skip:
 	return;
 }
 EXPORT_SYMBOL(__iop13xx_iounmap);
+
+void __init iop13xx_init_early(void)
+{
+	arch_ioremap = __iop13xx_ioremap;
+	arch_iounmap = __iop13xx_iounmap;
+}
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index abaee88..5c96b73 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -92,6 +92,7 @@ static struct sys_timer iq81340mc_timer = {
 MACHINE_START(IQ81340MC, "Intel IQ81340MC")
 	/* Maintainer: Dan Williams <dan.j.williams at intel.com> */
 	.atag_offset    = 0x100,
+	.init_early     = iop13xx_init_early,
 	.map_io         = iop13xx_map_io,
 	.init_irq       = iop13xx_init_irq,
 	.timer          = &iq81340mc_timer,
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index 690916a..aa4dd75 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -94,6 +94,7 @@ static struct sys_timer iq81340sc_timer = {
 MACHINE_START(IQ81340SC, "Intel IQ81340SC")
 	/* Maintainer: Dan Williams <dan.j.williams at intel.com> */
 	.atag_offset    = 0x100,
+	.init_early     = iop13xx_init_early,
 	.map_io         = iop13xx_map_io,
 	.init_irq       = iop13xx_init_irq,
 	.timer          = &iq81340sc_timer,
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:19 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:19 -0600
Subject: [PATCH v3 07/30] ARM: iop13xx: move io.h externs to pci.h
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-8-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

These variables are just needed in pci.c and io.c, so move them out of
io.h in preparation to remove io.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/mach-iop13xx/include/mach/io.h |    4 ----
 arch/arm/mach-iop13xx/io.c              |    2 ++
 arch/arm/mach-iop13xx/pci.h             |    6 ++++++
 3 files changed, 8 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-iop13xx/pci.h

diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index 2a69fc0..058dbfd 100644
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -26,9 +26,5 @@
 #define __mem_isa(a) (a)
 
 extern void __iomem * __iop13xx_io(unsigned long io_addr);
-extern u32 iop13xx_atue_mem_base;
-extern u32 iop13xx_atux_mem_base;
-extern size_t iop13xx_atue_mem_size;
-extern size_t iop13xx_atux_mem_size;
 
 #endif
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index d63585e..70f716f 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -21,6 +21,8 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
 
+#include "pci.h"
+
 void * __iomem __iop13xx_io(unsigned long io_addr)
 {
 	void __iomem * io_virt;
diff --git a/arch/arm/mach-iop13xx/pci.h b/arch/arm/mach-iop13xx/pci.h
new file mode 100644
index 0000000..c70cf5b
--- /dev/null
+++ b/arch/arm/mach-iop13xx/pci.h
@@ -0,0 +1,6 @@
+#include <linux/types.h>
+
+extern u32 iop13xx_atue_mem_base;
+extern u32 iop13xx_atux_mem_base;
+extern size_t iop13xx_atue_mem_size;
+extern size_t iop13xx_atux_mem_size;
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:20 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:20 -0600
Subject: [PATCH v3 08/30] ARM: OMAP: Remove remaining includes for mach/io.h
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-9-git-send-email-robherring2@gmail.com>

From: Tony Lindgren <tony at atomide.com>

These are no longer needed with the recent iomap.h
changes.

Reported-by: Rob Herring <robherring2 at gmail.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Tomi Valkeinen <tomi.valkeinen at ti.com>
Cc: Florian Tobias Schandinat <FlorianSchandinat at gmx.de>
---
 arch/arm/mach-omap1/include/mach/entry-macro.S |    1 -
 arch/arm/mach-omap1/sram.S                     |    1 -
 arch/arm/plat-omap/include/plat/sdrc.h         |    1 -
 drivers/video/omap2/vrfb.c                     |    1 -
 4 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S
index 68d2679..d0b18b5 100644
--- a/arch/arm/mach-omap1/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
@@ -11,7 +11,6 @@
  */
 
 #include <mach/hardware.h>
-#include <mach/io.h>
 #include <mach/irqs.h>
 
 #include "../../iomap.h"
diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S
index 2ce0b9a..00e9d9e 100644
--- a/arch/arm/mach-omap1/sram.S
+++ b/arch/arm/mach-omap1/sram.S
@@ -12,7 +12,6 @@
 
 #include <asm/assembler.h>
 
-#include <mach/io.h>
 #include <mach/hardware.h>
 
 #include "iomap.h"
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 925b12b..9bb978e 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -16,7 +16,6 @@
  * published by the Free Software Foundation.
  */
 
-#include <mach/io.h>
 
 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
 
diff --git a/drivers/video/omap2/vrfb.c b/drivers/video/omap2/vrfb.c
index fd22716..4e5b960 100644
--- a/drivers/video/omap2/vrfb.c
+++ b/drivers/video/omap2/vrfb.c
@@ -27,7 +27,6 @@
 #include <linux/bitops.h>
 #include <linux/mutex.h>
 
-#include <mach/io.h>
 #include <plat/vrfb.h>
 #include <plat/sdrc.h>
 
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:21 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:21 -0600
Subject: [PATCH v3 09/30] [media] davinci: remove includes of mach/io.h
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-10-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Remove a few remaining includes of mach/io.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Mauro Carvalho Chehab <mchehab at infradead.org>
---
 drivers/media/video/davinci/vpbe_osd.c  |    1 -
 drivers/media/video/davinci/vpbe_venc.c |    1 -
 2 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/drivers/media/video/davinci/vpbe_osd.c b/drivers/media/video/davinci/vpbe_osd.c
index d6488b7..bba299d 100644
--- a/drivers/media/video/davinci/vpbe_osd.c
+++ b/drivers/media/video/davinci/vpbe_osd.c
@@ -28,7 +28,6 @@
 #include <linux/clk.h>
 #include <linux/slab.h>
 
-#include <mach/io.h>
 #include <mach/cputype.h>
 #include <mach/hardware.h>
 
diff --git a/drivers/media/video/davinci/vpbe_venc.c b/drivers/media/video/davinci/vpbe_venc.c
index 00e80f5..b21ecc8 100644
--- a/drivers/media/video/davinci/vpbe_venc.c
+++ b/drivers/media/video/davinci/vpbe_venc.c
@@ -27,7 +27,6 @@
 
 #include <mach/hardware.h>
 #include <mach/mux.h>
-#include <mach/io.h>
 #include <mach/i2c.h>
 
 #include <linux/io.h>
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:22 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:22 -0600
Subject: [PATCH v3 10/30] ARM: davinci: remove unneeded mach/io.h include
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-11-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

entry-macro.S doesn't actually need mach/io.h, so remove it.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-davinci/include/mach/entry-macro.S |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index e14c0dc..f6e1d33 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -8,7 +8,6 @@
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
-#include <mach/io.h>
 #include <mach/irqs.h>
 
 		.macro	disable_fiq
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:23 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:23 -0600
Subject: [PATCH v3 11/30] ARM: orion5x: clean-up mach/io.h
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-12-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Move orion5x specific mach/io.h parts into common.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Lennert Buytenhek <kernel at wantstofly.org>
Cc: Nicolas Pitre <nico at fluxnic.net>
---
 arch/arm/mach-orion5x/common.h          |    9 +++++++++
 arch/arm/mach-orion5x/include/mach/io.h |   12 ------------
 arch/arm/mach-orion5x/pci.c             |    1 +
 arch/arm/mach-orion5x/tsx09-common.c    |    1 +
 4 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index d2513ac..2e6454c 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -57,5 +57,14 @@ struct meminfo;
 struct tag;
 extern void __init tag_fixup_mem32(struct tag *, char **, struct meminfo *);
 
+/*****************************************************************************
+ * Helpers to access Orion registers
+ ****************************************************************************/
+/*
+ * These are not preempt-safe.  Locks, if needed, must be taken
+ * care of by the caller.
+ */
+#define orion5x_setbits(r, mask)	writel(readl(r) | (mask), (r))
+#define orion5x_clrbits(r, mask)	writel(readl(r) & ~(mask), (r))
 
 #endif
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
index e9d9afd..444136d 100644
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ b/arch/arm/mach-orion5x/include/mach/io.h
@@ -18,16 +18,4 @@
 #define __io(a)			__typesafe_io(a)
 #define __mem_pci(a)		(a)
 
-
-/*****************************************************************************
- * Helpers to access Orion registers
- ****************************************************************************/
-/*
- * These are not preempt-safe.  Locks, if needed, must be taken
- * care of by the caller.
- */
-#define orion5x_setbits(r, mask)	writel(readl(r) | (mask), (r))
-#define orion5x_clrbits(r, mask)	writel(readl(r) & ~(mask), (r))
-
-
 #endif
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 09a045f..a9d2151 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -19,6 +19,7 @@
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
 #include <plat/addr-map.h>
+#include <mach/orion5x.h>
 #include "common.h"
 
 /*****************************************************************************
diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c
index c9abb8f..7189827 100644
--- a/arch/arm/mach-orion5x/tsx09-common.c
+++ b/arch/arm/mach-orion5x/tsx09-common.c
@@ -15,6 +15,7 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/timex.h>
 #include <linux/serial_reg.h>
+#include <mach/orion5x.h>
 #include "tsx09-common.h"
 #include "common.h"
 
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:24 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:24 -0600
Subject: [PATCH v3 12/30] ARM: tegra: clean-up mach/io.h
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-13-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Move tegra specific mach/io.h parts into iomap.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Tested-by: Stephen Warren <swarren at nvidia.com>
Acked-by: Stephen Warren <swarren at nvidia.com>
Cc: Colin Cross <ccross at android.com>
Cc: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-tegra/include/mach/debug-macro.S |    1 -
 arch/arm/mach-tegra/include/mach/io.h          |   48 ------------------------
 arch/arm/mach-tegra/include/mach/iomap.h       |   48 ++++++++++++++++++++++++
 arch/arm/mach-tegra/io.c                       |    1 +
 4 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index 619abc6..e28ce16 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -18,7 +18,6 @@
  *
  */
 
-#include <mach/io.h>
 #include <mach/iomap.h>
 
 	.macro  addruart, rp, rv, tmp
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
index f15deff..47b4b61 100644
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -23,56 +23,8 @@
 
 #define IO_SPACE_LIMIT 0xffff
 
-/* On TEGRA, many peripherals are very closely packed in
- * two 256MB io windows (that actually only use about 64KB
- * at the start of each).
- *
- * We will just map the first 1MB of each window (to minimize
- * pt entries needed) and provide a macro to transform physical
- * io addresses to an appropriate void __iomem *.
- *
- */
-
-#ifdef __ASSEMBLY__
-#define IOMEM(x)	(x)
-#else
-#define IOMEM(x)	((void __force __iomem *)(x))
-#endif
-
-#define IO_IRAM_PHYS	0x40000000
-#define IO_IRAM_VIRT	IOMEM(0xFE400000)
-#define IO_IRAM_SIZE	SZ_256K
-
-#define IO_CPU_PHYS     0x50040000
-#define IO_CPU_VIRT     IOMEM(0xFE000000)
-#define IO_CPU_SIZE	SZ_16K
-
-#define IO_PPSB_PHYS	0x60000000
-#define IO_PPSB_VIRT	IOMEM(0xFE200000)
-#define IO_PPSB_SIZE	SZ_1M
-
-#define IO_APB_PHYS	0x70000000
-#define IO_APB_VIRT	IOMEM(0xFE300000)
-#define IO_APB_SIZE	SZ_1M
-
-#define IO_TO_VIRT_BETWEEN(p, st, sz)	((p) >= (st) && (p) < ((st) + (sz)))
-#define IO_TO_VIRT_XLATE(p, pst, vst)	(((p) - (pst) + (vst)))
-
-#define IO_TO_VIRT(n) ( \
-	IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ?		\
-		IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) :	\
-	IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ?		\
-		IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :	\
-	IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?		\
-		IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :	\
-	IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ?		\
-		IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) :	\
-	NULL)
-
 #ifndef __ASSEMBLER__
 
-#define IO_ADDRESS(n) (IO_TO_VIRT(n))
-
 #ifdef CONFIG_TEGRA_PCI
 extern void __iomem *tegra_pcie_io_base;
 
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 19dec3a..082b4d1 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -271,4 +271,52 @@
 # define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
 #endif
 
+/* On TEGRA, many peripherals are very closely packed in
+ * two 256MB io windows (that actually only use about 64KB
+ * at the start of each).
+ *
+ * We will just map the first 1MB of each window (to minimize
+ * pt entries needed) and provide a macro to transform physical
+ * io addresses to an appropriate void __iomem *.
+ *
+ */
+
+#ifdef __ASSEMBLY__
+#define IOMEM(x)	(x)
+#else
+#define IOMEM(x)	((void __force __iomem *)(x))
+#endif
+
+#define IO_IRAM_PHYS	0x40000000
+#define IO_IRAM_VIRT	IOMEM(0xFE400000)
+#define IO_IRAM_SIZE	SZ_256K
+
+#define IO_CPU_PHYS     0x50040000
+#define IO_CPU_VIRT     IOMEM(0xFE000000)
+#define IO_CPU_SIZE	SZ_16K
+
+#define IO_PPSB_PHYS	0x60000000
+#define IO_PPSB_VIRT	IOMEM(0xFE200000)
+#define IO_PPSB_SIZE	SZ_1M
+
+#define IO_APB_PHYS	0x70000000
+#define IO_APB_VIRT	IOMEM(0xFE300000)
+#define IO_APB_SIZE	SZ_1M
+
+#define IO_TO_VIRT_BETWEEN(p, st, sz)	((p) >= (st) && (p) < ((st) + (sz)))
+#define IO_TO_VIRT_XLATE(p, pst, vst)	(((p) - (pst) + (vst)))
+
+#define IO_TO_VIRT(n) ( \
+	IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ?		\
+		IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) :	\
+	IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ?		\
+		IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :	\
+	IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?		\
+		IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :	\
+	IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ?		\
+		IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) :	\
+	NULL)
+
+#define IO_ADDRESS(n) (IO_TO_VIRT(n))
+
 #endif
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index d23ee2d..58b4baf 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -26,6 +26,7 @@
 
 #include <asm/page.h>
 #include <asm/mach/map.h>
+#include <mach/iomap.h>
 
 #include "board.h"
 
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:25 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:25 -0600
Subject: [PATCH v3 13/30] ARM: ep93xx: clean-up mach/io.h
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-14-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Move ep93xx specifics in mach/io.h to ep93xx-regs.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>
Cc: Ryan Mallon <rmallon at gmail.com>
---
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |    9 +++++++++
 arch/arm/mach-ep93xx/include/mach/io.h          |    9 ---------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index c4a7b84..e711d0e 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -6,6 +6,15 @@
 #define __ASM_ARCH_EP93XX_REGS_H
 
 /*
+ * A typesafe __io() variation for variable initialisers
+ */
+#ifdef __ASSEMBLER__
+#define IOMEM(p)                p
+#else
+#define IOMEM(p)                ((void __iomem __force *)(p))
+#endif
+
+/*
  * EP93xx Physical Memory Map:
  *
  * The ASDO pin is sampled at system reset to select a synchronous or
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
index 594b77f..17e76ef 100644
--- a/arch/arm/mach-ep93xx/include/mach/io.h
+++ b/arch/arm/mach-ep93xx/include/mach/io.h
@@ -10,13 +10,4 @@
 #define __io(p)			__typesafe_io(p)
 #define __mem_pci(p)		(p)
 
-/*
- * A typesafe __io() variation for variable initialisers
- */
-#ifdef __ASSEMBLER__
-#define IOMEM(p)		p
-#else
-#define IOMEM(p)		((void __iomem __force *)(p))
-#endif
-
 #endif /* __ASM_MACH_IO_H */
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:26 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:26 -0600
Subject: [PATCH v3 14/30] ARM: at91: add explicit include of hardware.h to
 uncompressor
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-15-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation to remove mach/io.h, add explicit include of hardware.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Andrew Victor <linux at maxim.org.za>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/mach-at91/include/mach/uncompress.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 0234fd9..4218647 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -23,6 +23,7 @@
 
 #include <linux/io.h>
 #include <linux/atmel_serial.h>
+#include <mach/hardware.h>
 
 #if defined(CONFIG_AT91_EARLY_DBGU0)
 #define UART_OFFSET AT91_BASE_DBGU0
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:27 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:27 -0600
Subject: [PATCH v3 15/30] ARM: dove: add explicit include of dove.h to
 addr-map.c
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-16-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation to remove mach/io.h, add explicit include of mach/dove.h

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/mach-dove/addr-map.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
index 98b8c83..2a06c01 100644
--- a/arch/arm/mach-dove/addr-map.c
+++ b/arch/arm/mach-dove/addr-map.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <asm/mach/arch.h>
 #include <asm/setup.h>
+#include <mach/dove.h>
 #include <plat/addr-map.h>
 #include "common.h"
 
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:28 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:28 -0600
Subject: [PATCH v3 16/30] ARM: clps711x: remove unneeded include of mach/io.h
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-17-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

In preparation to remove mach/io.h, remove an unneeded include of it.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/mach-clps711x/include/mach/uncompress.h |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h
index 7164310..35ed731 100644
--- a/arch/arm/mach-clps711x/include/mach/uncompress.h
+++ b/arch/arm/mach-clps711x/include/mach/uncompress.h
@@ -17,7 +17,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#include <mach/io.h>
 #include <mach/hardware.h>
 #include <asm/hardware/clps7111.h>
 
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:29 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:29 -0600
Subject: [PATCH v3 17/30] ARM: make mach/io.h include optional
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-18-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Add a kconfig option NEED_MACH_IO_H to conditionally include mach/io.h.

Basing this on CONFIG_PCI and CONFIG_ISA doesn't quite work. Most ISA
platforms don't need mach/io.h, but ebsa110 does. Most PCI platforms need
mach/io.h for now, but ks8695 doesn't which means it's broken? omap has a
lot of other stuff in its io.h, so it also needs io.h until it is cleaned
up.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>
---
 arch/arm/Kconfig          |   19 +++++++++++++++++++
 arch/arm/include/asm/io.h |    5 +++++
 2 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 92c9c79..ae016cd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -186,6 +186,9 @@ config GENERIC_ISA_DMA
 config FIQ
 	bool
 
+config NEED_MACH_IO_H
+	bool
+
 config ARCH_MTD_XIP
 	bool
 
@@ -265,6 +268,7 @@ config ARCH_INTEGRATOR
 	select GENERIC_CLOCKEVENTS
 	select PLAT_VERSATILE
 	select PLAT_VERSATILE_FPGA_IRQ
+	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for ARM's Integrator platform.
@@ -400,6 +404,7 @@ config ARCH_EBSA110
 	select ISA
 	select NO_IOPORT
 	select ARCH_USES_GETTIMEOFFSET
+	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  This is an evaluation board for the StrongARM processor available
@@ -426,6 +431,7 @@ config ARCH_FOOTBRIDGE
 	select FOOTBRIDGE
 	select GENERIC_CLOCKEVENTS
 	select HAVE_IDE
+	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for systems based on the DC21285 companion chip
@@ -478,6 +484,7 @@ config ARCH_IOP13XX
 	select PCI
 	select ARCH_SUPPORTS_MSI
 	select VMSPLIT_1G
+	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for Intel's IOP13XX (XScale) family of processors.
@@ -486,6 +493,7 @@ config ARCH_IOP32X
 	bool "IOP32x-based"
 	depends on MMU
 	select CPU_XSCALE
+	select NEED_MACH_IO_H
 	select PLAT_IOP
 	select PCI
 	select ARCH_REQUIRE_GPIOLIB
@@ -497,6 +505,7 @@ config ARCH_IOP33X
 	bool "IOP33x-based"
 	depends on MMU
 	select CPU_XSCALE
+	select NEED_MACH_IO_H
 	select PLAT_IOP
 	select PCI
 	select ARCH_REQUIRE_GPIOLIB
@@ -509,6 +518,7 @@ config ARCH_IXP23XX
 	select CPU_XSC3
  	select PCI
 	select ARCH_USES_GETTIMEOFFSET
+	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for Intel's IXP23xx (XScale) family of processors.
@@ -519,6 +529,7 @@ config ARCH_IXP2000
 	select CPU_XSCALE
 	select PCI
 	select ARCH_USES_GETTIMEOFFSET
+	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for Intel's IXP2400/2800 (XScale) family of processors.
@@ -532,6 +543,7 @@ config ARCH_IXP4XX
 	select GENERIC_CLOCKEVENTS
 	select HAVE_SCHED_CLOCK
 	select MIGHT_HAVE_PCI
+	select NEED_MACH_IO_H
 	select DMABOUNCE if PCI
 	help
 	  Support for Intel's IXP4XX (XScale) family of processors.
@@ -542,6 +554,7 @@ config ARCH_DOVE
 	select PCI
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
+	select NEED_MACH_IO_H
 	select PLAT_ORION
 	help
 	  Support for the Marvell Dove SoC 88AP510
@@ -552,6 +565,7 @@ config ARCH_KIRKWOOD
 	select PCI
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
+	select NEED_MACH_IO_H
 	select PLAT_ORION
 	help
 	  Support for the following Marvell Kirkwood series SoCs:
@@ -576,6 +590,7 @@ config ARCH_MV78XX0
 	select PCI
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
+	select NEED_MACH_IO_H
 	select PLAT_ORION
 	help
 	  Support for the following Marvell MV78xx0 series SoCs:
@@ -645,6 +660,7 @@ config ARCH_TEGRA
 	select HAVE_SCHED_CLOCK
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
+	select NEED_MACH_IO_H if PCI
 	select ARCH_HAS_CPUFREQ
 	help
 	  This enables support for NVIDIA Tegra based systems (Tegra APX,
@@ -739,6 +755,7 @@ config ARCH_RPC
 	select ARCH_SPARSEMEM_ENABLE
 	select ARCH_USES_GETTIMEOFFSET
 	select HAVE_IDE
+	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
@@ -771,6 +788,7 @@ config ARCH_S3C2410
 	select CLKDEV_LOOKUP
 	select ARCH_USES_GETTIMEOFFSET
 	select HAVE_S3C2410_I2C if I2C
+	select NEED_MACH_IO_H
 	help
 	  Samsung S3C2410X CPU based systems, such as the Simtec Electronics
 	  BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
@@ -877,6 +895,7 @@ config ARCH_SHARK
 	select PCI
 	select ARCH_USES_GETTIMEOFFSET
 	select NEED_MACH_MEMORY_H
+	select NEED_MACH_IO_H
 	help
 	  Support for the StrongARM based Digital DNARD machine, also known
 	  as "Shark" (<http://www.shark-linux.de/shark.html>).
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 9bf9d00..cd8c125 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -109,7 +109,12 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 /*
  * Now, pick up the machine-defined IO definitions
  */
+#ifdef CONFIG_NEED_MACH_IO_H
 #include <mach/io.h>
+#else
+#define __io(a)		({ (void)(a); __typesafe_io(0); })
+#define __mem_pci(a)	(a)
+#endif
 
 /*
  * This is the limit of PC card/PCI/ISA IO space, which is by default
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:30 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:30 -0600
Subject: [PATCH v3 18/30] ARM: remove bunch of now unused mach/io.h files
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-19-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Now that many platforms don't need mach/io.h, remove the usused ones.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Jamie Iles <jamie at jamieiles.com>
Acked-by: Pawel Moll <pawel.moll at arm.com>
---
 arch/arm/mach-at91/include/mach/io.h      |   31 ------------------
 arch/arm/mach-bcmring/include/mach/io.h   |   33 -------------------
 arch/arm/mach-clps711x/include/mach/io.h  |   36 ---------------------
 arch/arm/mach-cns3xxx/include/mach/io.h   |   17 ----------
 arch/arm/mach-davinci/include/mach/io.h   |   24 --------------
 arch/arm/mach-ep93xx/include/mach/io.h    |   13 --------
 arch/arm/mach-exynos/include/mach/io.h    |   26 ---------------
 arch/arm/mach-gemini/include/mach/io.h    |   18 ----------
 arch/arm/mach-h720x/include/mach/io.h     |   22 -------------
 arch/arm/mach-highbank/include/mach/io.h  |    7 ----
 arch/arm/mach-ks8695/include/mach/io.h    |   19 -----------
 arch/arm/mach-lpc32xx/include/mach/io.h   |   27 ----------------
 arch/arm/mach-mmp/include/mach/io.h       |   21 ------------
 arch/arm/mach-msm/include/mach/io.h       |   24 --------------
 arch/arm/mach-mxs/include/mach/io.h       |   22 -------------
 arch/arm/mach-netx/include/mach/io.h      |   28 ----------------
 arch/arm/mach-nomadik/include/mach/io.h   |   22 -------------
 arch/arm/mach-omap1/include/mach/io.h     |   46 ---------------------------
 arch/arm/mach-omap2/include/mach/io.h     |   49 -----------------------------
 arch/arm/mach-orion5x/include/mach/io.h   |   21 ------------
 arch/arm/mach-picoxcell/include/mach/io.h |   22 -------------
 arch/arm/mach-pnx4008/include/mach/io.h   |   21 ------------
 arch/arm/mach-prima2/include/mach/io.h    |   16 ---------
 arch/arm/mach-pxa/include/mach/io.h       |   20 ------------
 arch/arm/mach-realview/include/mach/io.h  |   28 ----------------
 arch/arm/mach-s3c64xx/include/mach/io.h   |   18 ----------
 arch/arm/mach-s5p64x0/include/mach/io.h   |   25 ---------------
 arch/arm/mach-s5pc100/include/mach/io.h   |   18 ----------
 arch/arm/mach-s5pv210/include/mach/io.h   |   26 ---------------
 arch/arm/mach-sa1100/include/mach/io.h    |   20 ------------
 arch/arm/mach-shmobile/include/mach/io.h  |    9 -----
 arch/arm/mach-spear3xx/include/mach/io.h  |   19 -----------
 arch/arm/mach-spear6xx/include/mach/io.h  |   20 ------------
 arch/arm/mach-u300/include/mach/io.h      |   20 ------------
 arch/arm/mach-ux500/include/mach/io.h     |   22 -------------
 arch/arm/mach-versatile/include/mach/io.h |   28 ----------------
 arch/arm/mach-vexpress/include/mach/io.h  |   26 ---------------
 arch/arm/mach-vt8500/include/mach/io.h    |   26 ---------------
 arch/arm/mach-w90x900/include/mach/io.h   |   30 -----------------
 arch/arm/mach-zynq/include/mach/io.h      |   33 -------------------
 arch/arm/plat-mxc/include/mach/io.h       |   22 -------------
 arch/arm/plat-spear/include/plat/io.h     |   22 -------------
 42 files changed, 0 insertions(+), 997 deletions(-)
 delete mode 100644 arch/arm/mach-at91/include/mach/io.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/io.h
 delete mode 100644 arch/arm/mach-clps711x/include/mach/io.h
 delete mode 100644 arch/arm/mach-cns3xxx/include/mach/io.h
 delete mode 100644 arch/arm/mach-davinci/include/mach/io.h
 delete mode 100644 arch/arm/mach-ep93xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/io.h
 delete mode 100644 arch/arm/mach-gemini/include/mach/io.h
 delete mode 100644 arch/arm/mach-h720x/include/mach/io.h
 delete mode 100644 arch/arm/mach-highbank/include/mach/io.h
 delete mode 100644 arch/arm/mach-ks8695/include/mach/io.h
 delete mode 100644 arch/arm/mach-lpc32xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/io.h
 delete mode 100644 arch/arm/mach-msm/include/mach/io.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/io.h
 delete mode 100644 arch/arm/mach-netx/include/mach/io.h
 delete mode 100644 arch/arm/mach-nomadik/include/mach/io.h
 delete mode 100644 arch/arm/mach-omap1/include/mach/io.h
 delete mode 100644 arch/arm/mach-omap2/include/mach/io.h
 delete mode 100644 arch/arm/mach-orion5x/include/mach/io.h
 delete mode 100644 arch/arm/mach-picoxcell/include/mach/io.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/io.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/io.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/io.h
 delete mode 100644 arch/arm/mach-realview/include/mach/io.h
 delete mode 100644 arch/arm/mach-s3c64xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/io.h
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/io.h
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/io.h
 delete mode 100644 arch/arm/mach-sa1100/include/mach/io.h
 delete mode 100644 arch/arm/mach-shmobile/include/mach/io.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-u300/include/mach/io.h
 delete mode 100644 arch/arm/mach-ux500/include/mach/io.h
 delete mode 100644 arch/arm/mach-versatile/include/mach/io.h
 delete mode 100644 arch/arm/mach-vexpress/include/mach/io.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/io.h
 delete mode 100644 arch/arm/mach-w90x900/include/mach/io.h
 delete mode 100644 arch/arm/mach-zynq/include/mach/io.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/io.h
 delete mode 100644 arch/arm/plat-spear/include/plat/io.h

diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
deleted file mode 100644
index 4003001..0000000
--- a/arch/arm/mach-at91/include/mach/io.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/io.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include <mach/hardware.h>
-
-#define IO_SPACE_LIMIT		0xFFFFFFFF
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/io.h b/arch/arm/mach-bcmring/include/mach/io.h
deleted file mode 100644
index dae5e9b..0000000
--- a/arch/arm/mach-bcmring/include/mach/io.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <mach/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-clps711x/include/mach/io.h b/arch/arm/mach-clps711x/include/mach/io.h
deleted file mode 100644
index 2e0b3ce..0000000
--- a/arch/arm/mach-clps711x/include/mach/io.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/io.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-/*
- * We don't support ins[lb]/outs[lb].  Make them fault.
- */
-#define __raw_readsb(p,d,l)	do { *(int *)0 = 0; } while (0)
-#define __raw_readsl(p,d,l)	do { *(int *)0 = 0; } while (0)
-#define __raw_writesb(p,d,l)	do { *(int *)0 = 0; } while (0)
-#define __raw_writesl(p,d,l)	do { *(int *)0 = 0; } while (0)
-
-#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/io.h b/arch/arm/mach-cns3xxx/include/mach/io.h
deleted file mode 100644
index 33b6fc1..0000000
--- a/arch/arm/mach-cns3xxx/include/mach/io.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2008 Cavium Networks
- * Copyright 2003 ARM Limited
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-#ifndef __MACH_IO_H
-#define __MACH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)			__typesafe_io(a)
-#define __mem_pci(a)		(a)
-
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
deleted file mode 100644
index b2267d1..0000000
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * DaVinci IO address definitions
- *
- * Copied from include/asm/arm/arch-omap/io.h
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)			__typesafe_io(a)
-#define __mem_pci(a)		(a)
-#define __mem_isa(a)		(a)
-
-#endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
deleted file mode 100644
index 17e76ef..0000000
--- a/arch/arm/mach-ep93xx/include/mach/io.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/io.h
- */
-
-#ifndef __ASM_MACH_IO_H
-#define __ASM_MACH_IO_H
-
-#define IO_SPACE_LIMIT		0xffffffff
-
-#define __io(p)			__typesafe_io(p)
-#define __mem_pci(p)		(p)
-
-#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-exynos/include/mach/io.h b/arch/arm/mach-exynos/include/mach/io.h
deleted file mode 100644
index d5478d2..0000000
--- a/arch/arm/mach-exynos/include/mach/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/io.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * Copyright 2008-2010 Ben Dooks <ben-linux at fluff.org>
- *
- * Based on arch/arm/mach-s5p6442/include/mach/io.h
- *
- * Default IO routines for EXYNOS4
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H __FILE__
-
-/* No current ISA/PCI bus support. */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
-#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-gemini/include/mach/io.h b/arch/arm/mach-gemini/include/mach/io.h
deleted file mode 100644
index c548056..0000000
--- a/arch/arm/mach-gemini/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  Copyright (C) 2001-2006 Storlink, Corp.
- *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas at teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef __MACH_IO_H
-#define __MACH_IO_H
-
-#define IO_SPACE_LIMIT	0xffffffff
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-h720x/include/mach/io.h b/arch/arm/mach-h720x/include/mach/io.h
deleted file mode 100644
index 2c8659c..0000000
--- a/arch/arm/mach-h720x/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/io.h
- *
- * Copyright (C) 2000 Steve Hill (sjhill at cotw.com)
- *
- * Changelog:
- *
- *  09-19-2001	JJKIM
- *  		Created from arch/arm/mach-l7200/include/mach/io.h
- *
- *  03-27-2003  Robert Schwebel <r.schwebel at pengutronix.de>:
- *  		re-unified header files for h720x
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-highbank/include/mach/io.h b/arch/arm/mach-highbank/include/mach/io.h
deleted file mode 100644
index 70cfa3b..0000000
--- a/arch/arm/mach-highbank/include/mach/io.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_IO_H
-#define __MACH_IO_H
-
-#define __io(a)		({ (void)(a); __typesafe_io(0); })
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-ks8695/include/mach/io.h b/arch/arm/mach-ks8695/include/mach/io.h
deleted file mode 100644
index a7a63ac..0000000
--- a/arch/arm/mach-ks8695/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/io.h
- *
- * Copyright (C) 2006 Andrew Victor
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT		0xffffffff
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/io.h b/arch/arm/mach-lpc32xx/include/mach/io.h
deleted file mode 100644
index 9b59ab5..0000000
--- a/arch/arm/mach-lpc32xx/include/mach/io.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-lpc32xx/include/mach/io.h
- *
- * Author: Kevin Wells <kevin.wells at nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT	0xffffffff
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h
deleted file mode 100644
index e7adf3d..0000000
--- a/arch/arm/mach-mmp/include/mach/io.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * linux/arch/arm/mach-mmp/include/mach/io.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_IO_H
-#define __ASM_MACH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
deleted file mode 100644
index 1071f98..0000000
--- a/arch/arm/mach-msm/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-msm/include/mach/io.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)    (a)
-
-#endif
diff --git a/arch/arm/mach-mxs/include/mach/io.h b/arch/arm/mach-mxs/include/mach/io.h
deleted file mode 100644
index 289b722..0000000
--- a/arch/arm/mach-mxs/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MXS_IO_H__
-#define __MACH_MXS_IO_H__
-
-/* Allow IO space to be anywhere in the memory */
-#define IO_SPACE_LIMIT 0xffffffff
-
-/* io address mapping macro */
-#define __io(a)		__typesafe_io(a)
-
-#define __mem_pci(a)	(a)
-
-#endif /* __MACH_MXS_IO_H__ */
diff --git a/arch/arm/mach-netx/include/mach/io.h b/arch/arm/mach-netx/include/mach/io.h
deleted file mode 100644
index c3921cb..0000000
--- a/arch/arm/mach-netx/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- *  arch/arm/mach-netx/include/mach/io.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/arch/arm/mach-nomadik/include/mach/io.h b/arch/arm/mach-nomadik/include/mach/io.h
deleted file mode 100644
index 2e1eca1..0000000
--- a/arch/arm/mach-nomadik/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-nomadik/include/mach/io.h   (copied from mach-sa1100)
- *
- * Copyright (C) 1997-1999 Russell King
- *
- * Modifications:
- *  06-12-1997  RMK     Created.
- *  07-04-1999  RMK     Major cleanup
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)         __typesafe_io(a)
-#define __mem_pci(a)    (a)
-
-#endif
diff --git a/arch/arm/mach-omap1/include/mach/io.h b/arch/arm/mach-omap1/include/mach/io.h
deleted file mode 100644
index 37b12e1..0000000
--- a/arch/arm/mach-omap1/include/mach/io.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/io.h
- *
- * IO definitions for TI OMAP processors and boards
- *
- * Copied from arch/arm/mach-sa1100/include/mach/io.h
- * Copyright (C) 1997-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Modifications:
- *  06-12-1997	RMK	Created.
- *  07-04-1999	RMK	Major cleanup
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-omap2/include/mach/io.h b/arch/arm/mach-omap2/include/mach/io.h
deleted file mode 100644
index b8758c8..0000000
--- a/arch/arm/mach-omap2/include/mach/io.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/io.h
- *
- * IO definitions for TI OMAP processors and boards
- *
- * Copied from arch/arm/mach-sa1100/include/mach/io.h
- * Copyright (C) 1997-1999 Russell King
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar at ti.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Modifications:
- *  06-12-1997	RMK	Created.
- *  07-04-1999	RMK	Major cleanup
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
deleted file mode 100644
index 444136d..0000000
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/io.h
- *
- * Tzachi Perelstein <tzachi at marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "orion5x.h"
-
-#define IO_SPACE_LIMIT		0xffffffff
-
-#define __io(a)			__typesafe_io(a)
-#define __mem_pci(a)		(a)
-
-#endif
diff --git a/arch/arm/mach-picoxcell/include/mach/io.h b/arch/arm/mach-picoxcell/include/mach/io.h
deleted file mode 100644
index 7573ec7..0000000
--- a/arch/arm/mach-picoxcell/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/* No ioports, but needed for driver compatibility. */
-#define __io(a)			__typesafe_io(a)
-/* No PCI possible on picoxcell. */
-#define __mem_pci(a)		(a)
-
-#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/io.h b/arch/arm/mach-pnx4008/include/mach/io.h
deleted file mode 100644
index cbf0904..0000000
--- a/arch/arm/mach-pnx4008/include/mach/io.h
+++ /dev/null
@@ -1,21 +0,0 @@
-
-/*
- *  arch/arm/mach-pnx4008/include/mach/io.h
- *
- * Author: Dmitry Chigirev <chigirev at ru.mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/io.h b/arch/arm/mach-prima2/include/mach/io.h
deleted file mode 100644
index 6c31e9e..0000000
--- a/arch/arm/mach-prima2/include/mach/io.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/io.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_PRIMA2_IO_H
-#define __MACH_PRIMA2_IO_H
-
-#define IO_SPACE_LIMIT ((resource_size_t)0)
-
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
deleted file mode 100644
index fdca3be..0000000
--- a/arch/arm/mach-pxa/include/mach/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/io.h
- *
- * Copied from asm/arch/sa1100/io.h
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <mach/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-realview/include/mach/io.h b/arch/arm/mach-realview/include/mach/io.h
deleted file mode 100644
index f05bcdf..0000000
--- a/arch/arm/mach-realview/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- *  arch/arm/mach-realview/include/mach/io.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/io.h b/arch/arm/mach-s3c64xx/include/mach/io.h
deleted file mode 100644
index de5716d..0000000
--- a/arch/arm/mach-s3c64xx/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-s3c64xxinclude/mach/io.h
- *
- * Copyright 2008 Simtec Electronics
- *	Ben Dooks <ben-linux at fluff.org>
- *
- * Default IO routines for S3C64XX based
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/* No current ISA/PCI bus support. */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
-#endif
diff --git a/arch/arm/mach-s5p64x0/include/mach/io.h b/arch/arm/mach-s5p64x0/include/mach/io.h
deleted file mode 100644
index a3e095c..0000000
--- a/arch/arm/mach-s5p64x0/include/mach/io.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/io.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * Copyright 2008 Simtec Electronics
- *	Ben Dooks <ben-linux at fluff.org>
- *
- * Default IO routines for S5P64X0 based
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/* No current ISA/PCI bus support. */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
-#endif
diff --git a/arch/arm/mach-s5pc100/include/mach/io.h b/arch/arm/mach-s5pc100/include/mach/io.h
deleted file mode 100644
index 819acf5..0000000
--- a/arch/arm/mach-s5pc100/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-s5pc100/include/mach/io.h
- *
- * Copyright 2008 Simtec Electronics
- *	Ben Dooks <ben-linux at fluff.org>
- *
- * Default IO routines for S5PC100 systems
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/* No current ISA/PCI bus support. */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
-#endif
diff --git a/arch/arm/mach-s5pv210/include/mach/io.h b/arch/arm/mach-s5pv210/include/mach/io.h
deleted file mode 100644
index 5ab9d56..0000000
--- a/arch/arm/mach-s5pv210/include/mach/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/io.h
- *
- * Copyright 2008-2010 Ben Dooks <ben-linux at fluff.org>
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com/
- *
- * Based on arch/arm/mach-s5p6442/include/mach/io.h
- *
- * Default IO routines for S5PV210
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H __FILE__
-
-/* No current ISA/PCI bus support. */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
-#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h
deleted file mode 100644
index dfc27ff..0000000
--- a/arch/arm/mach-sa1100/include/mach/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/io.h
- *
- * Copyright (C) 1997-1999 Russell King
- *
- * Modifications:
- *  06-12-1997	RMK	Created.
- *  07-04-1999	RMK	Major cleanup
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/*
- * __io() is required to be an equivalent mapping to __mem_pci() for
- * SOC_COMMON to work.
- */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-shmobile/include/mach/io.h b/arch/arm/mach-shmobile/include/mach/io.h
deleted file mode 100644
index 7339fe4..0000000
--- a/arch/arm/mach-shmobile/include/mach/io.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __ASM_MACH_IO_H
-#define __ASM_MACH_IO_H
-
-#define IO_SPACE_LIMIT		0xffffffff
-
-#define __io(a)			((void __iomem *)(a))
-#define __mem_pci(a)		(a)
-
-#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/io.h b/arch/arm/mach-spear3xx/include/mach/io.h
deleted file mode 100644
index 30cff8a..0000000
--- a/arch/arm/mach-spear3xx/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/io.h
- *
- * IO definitions for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_IO_H
-#define __MACH_IO_H
-
-#include <plat/io.h>
-
-#endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/io.h b/arch/arm/mach-spear6xx/include/mach/io.h
deleted file mode 100644
index fb7c106..0000000
--- a/arch/arm/mach-spear6xx/include/mach/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/io.h
- *
- * IO definitions for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar Kumar<rajeev-dlh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_IO_H
-#define __MACH_IO_H
-
-#include <plat/io.h>
-
-#endif	/* __MACH_IO_H */
-
diff --git a/arch/arm/mach-u300/include/mach/io.h b/arch/arm/mach-u300/include/mach/io.h
deleted file mode 100644
index 5d6b4c1..0000000
--- a/arch/arm/mach-u300/include/mach/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/io.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Dummy IO map for being able to use writew()/readw(),
- * writel()/readw() and similar accessor functions.
- * Author: Linus Walleij <linus.walleij at stericsson.com>
- */
-#ifndef __MACH_IO_H
-#define __MACH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
deleted file mode 100644
index 1cf3f44..0000000
--- a/arch/arm/mach-ux500/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-u8500/include/mach/io.h
- *
- * Copyright (C) 1997-1999 Russell King
- *
- * Modifications:
- *  06-12-1997	RMK	Created.
- *  07-04-1999	RMK	Major cleanup
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
deleted file mode 100644
index f067c14..0000000
--- a/arch/arm/mach-versatile/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- *  arch/arm/mach-versatile/include/mach/io.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-vexpress/include/mach/io.h b/arch/arm/mach-vexpress/include/mach/io.h
deleted file mode 100644
index 13522d8..0000000
--- a/arch/arm/mach-vexpress/include/mach/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  arch/arm/mach-vexpress/include/mach/io.h
- *
- *  Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-vt8500/include/mach/io.h b/arch/arm/mach-vt8500/include/mach/io.h
deleted file mode 100644
index 46181ee..0000000
--- a/arch/arm/mach-vt8500/include/mach/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/io.h
- *
- *  Copyright (C) 2010 Alexey Charkov
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define __io(a)		__typesafe_io((a) + 0xf0000000)
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/mach-w90x900/include/mach/io.h b/arch/arm/mach-w90x900/include/mach/io.h
deleted file mode 100644
index d96ab99..0000000
--- a/arch/arm/mach-w90x900/include/mach/io.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * arch/arm/mach-w90x900/include/mach/io.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com at gmail.com>
- *
- * Based on arch/arm/mach-s3c2410/include/mach/io.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT	0xffffffff
-
-/*
- * 1:1 mapping for ioremapped regions.
- */
-
-#define __mem_pci(a)	(a)
-#define __io(a)		__typesafe_io(a)
-
-#endif
diff --git a/arch/arm/mach-zynq/include/mach/io.h b/arch/arm/mach-zynq/include/mach/io.h
deleted file mode 100644
index 39d9885..0000000
--- a/arch/arm/mach-zynq/include/mach/io.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* arch/arm/mach-zynq/include/mach/io.h
- *
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_IO_H__
-#define __MACH_IO_H__
-
-/* Allow IO space to be anywhere in the memory */
-
-#define IO_SPACE_LIMIT 0xffff
-
-/* IO address mapping macros, nothing special at this time but required */
-
-#ifdef __ASSEMBLER__
-#define IOMEM(x)		(x)
-#else
-#define IOMEM(x)		((void __force __iomem *)(x))
-#endif
-
-#define __io(a)			__typesafe_io(a)
-#define __mem_pci(a)		(a)
-
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
deleted file mode 100644
index ea9d95e..0000000
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_IO_H__
-#define __ASM_ARCH_MXC_IO_H__
-
-/* Allow IO space to be anywhere in the memory */
-#define IO_SPACE_LIMIT 0xffffffff
-
-/* io address mapping macro */
-#define __io(a)		__typesafe_io(a)
-
-#define __mem_pci(a)	(a)
-
-#endif
diff --git a/arch/arm/plat-spear/include/plat/io.h b/arch/arm/plat-spear/include/plat/io.h
deleted file mode 100644
index 4d4ba82..0000000
--- a/arch/arm/plat-spear/include/plat/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/io.h
- *
- * IO definitions for SPEAr platform
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_IO_H
-#define __PLAT_IO_H
-
-#define IO_SPACE_LIMIT		0xFFFFFFFF
-
-#define __io(a)			__typesafe_io(a)
-#define __mem_pci(a)		(a)
-
-#endif /* __PLAT_IO_H */
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:31 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:31 -0600
Subject: [PATCH v3 19/30] ARM: kill off __mem_pci
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-20-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

__mem_pci is only used to enable readl/writel and friends. Just condition
this on readl being defined and remove all the __mem_pci defines.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Lennert Buytenhek <kernel at wantstofly.org>
Cc: Imre Kaloz <kaloz at openwrt.org>
Cc: Krzysztof Halasa <khc at pm.waw.pl>
Cc: Nicolas Pitre <nico at fluxnic.net>
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Colin Cross <ccross at android.com>
Cc: Olof Johansson <olof at lixom.net>
Cc: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/include/asm/io.h                  |   46 ++++++++++-----------------
 arch/arm/mach-dove/include/mach/io.h       |    1 -
 arch/arm/mach-footbridge/include/mach/io.h |   13 --------
 arch/arm/mach-integrator/include/mach/io.h |    1 -
 arch/arm/mach-iop13xx/include/mach/io.h    |    2 -
 arch/arm/mach-iop32x/include/mach/io.h     |    1 -
 arch/arm/mach-iop33x/include/mach/io.h     |    1 -
 arch/arm/mach-ixp2000/include/mach/io.h    |    1 -
 arch/arm/mach-ixp23xx/include/mach/io.h    |    1 -
 arch/arm/mach-ixp4xx/include/mach/io.h     |    6 +---
 arch/arm/mach-kirkwood/include/mach/io.h   |    2 -
 arch/arm/mach-mv78xx0/include/mach/io.h    |    2 -
 arch/arm/mach-rpc/include/mach/io.h        |    5 ---
 arch/arm/mach-s3c2410/include/mach/io.h    |    5 ---
 arch/arm/mach-shark/include/mach/io.h      |    2 -
 arch/arm/mach-tegra/include/mach/io.h      |    1 -
 16 files changed, 18 insertions(+), 72 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index cd8c125..d7861b9 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -113,7 +113,6 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 #include <mach/io.h>
 #else
 #define __io(a)		({ (void)(a); __typesafe_io(0); })
-#define __mem_pci(a)	(a)
 #endif
 
 /*
@@ -216,18 +215,18 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
  * Again, this are defined to perform little endian accesses.  See the
  * IO port primitives for more information.
  */
-#ifdef __mem_pci
-#define readb_relaxed(c) ({ u8  __r = __raw_readb(__mem_pci(c)); __r; })
+#ifndef readl
+#define readb_relaxed(c) ({ u8  __r = __raw_readb(c); __r; })
 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
-					__raw_readw(__mem_pci(c))); __r; })
+					__raw_readw(c)); __r; })
 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
-					__raw_readl(__mem_pci(c))); __r; })
+					__raw_readl(c)); __r; })
 
-#define writeb_relaxed(v,c)	((void)__raw_writeb(v,__mem_pci(c)))
+#define writeb_relaxed(v,c)	((void)__raw_writeb(v,c))
 #define writew_relaxed(v,c)	((void)__raw_writew((__force u16) \
-					cpu_to_le16(v),__mem_pci(c)))
+					cpu_to_le16(v),c))
 #define writel_relaxed(v,c)	((void)__raw_writel((__force u32) \
-					cpu_to_le32(v),__mem_pci(c)))
+					cpu_to_le32(v),c))
 
 #define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 #define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })
@@ -237,30 +236,19 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
 #define writew(v,c)		({ __iowmb(); writew_relaxed(v,c); })
 #define writel(v,c)		({ __iowmb(); writel_relaxed(v,c); })
 
-#define readsb(p,d,l)		__raw_readsb(__mem_pci(p),d,l)
-#define readsw(p,d,l)		__raw_readsw(__mem_pci(p),d,l)
-#define readsl(p,d,l)		__raw_readsl(__mem_pci(p),d,l)
+#define readsb(p,d,l)		__raw_readsb(p,d,l)
+#define readsw(p,d,l)		__raw_readsw(p,d,l)
+#define readsl(p,d,l)		__raw_readsl(p,d,l)
 
-#define writesb(p,d,l)		__raw_writesb(__mem_pci(p),d,l)
-#define writesw(p,d,l)		__raw_writesw(__mem_pci(p),d,l)
-#define writesl(p,d,l)		__raw_writesl(__mem_pci(p),d,l)
+#define writesb(p,d,l)		__raw_writesb(p,d,l)
+#define writesw(p,d,l)		__raw_writesw(p,d,l)
+#define writesl(p,d,l)		__raw_writesl(p,d,l)
 
-#define memset_io(c,v,l)	_memset_io(__mem_pci(c),(v),(l))
-#define memcpy_fromio(a,c,l)	_memcpy_fromio((a),__mem_pci(c),(l))
-#define memcpy_toio(c,a,l)	_memcpy_toio(__mem_pci(c),(a),(l))
+#define memset_io(c,v,l)	_memset_io(c,(v),(l))
+#define memcpy_fromio(a,c,l)	_memcpy_fromio((a),c,(l))
+#define memcpy_toio(c,a,l)	_memcpy_toio(c,(a),(l))
 
-#elif !defined(readb)
-
-#define readb(c)			(__readwrite_bug("readb"),0)
-#define readw(c)			(__readwrite_bug("readw"),0)
-#define readl(c)			(__readwrite_bug("readl"),0)
-#define writeb(v,c)			__readwrite_bug("writeb")
-#define writew(v,c)			__readwrite_bug("writew")
-#define writel(v,c)			__readwrite_bug("writel")
-
-#define check_signature(io,sig,len)	(0)
-
-#endif	/* __mem_pci */
+#endif	/* readl */
 
 /*
  * ioremap and friends.
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
index eb4936f..29c8b85 100644
--- a/arch/arm/mach-dove/include/mach/io.h
+++ b/arch/arm/mach-dove/include/mach/io.h
@@ -15,6 +15,5 @@
 
 #define __io(a)  	((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
 						 DOVE_PCIE0_IO_VIRT_BASE))
-#define __mem_pci(a)	(a)
 
 #endif
diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
index 15a7039..aba531ee 100644
--- a/arch/arm/mach-footbridge/include/mach/io.h
+++ b/arch/arm/mach-footbridge/include/mach/io.h
@@ -27,18 +27,5 @@
  * Translation of various region addresses to virtual addresses
  */
 #define __io(a)			((void __iomem *)(PCIO_BASE + (a)))
-#if 1
-#define __mem_pci(a)		(a)
-#else
-
-static inline void __iomem *___mem_pci(void __iomem *p)
-{
-	unsigned long a = (unsigned long)p;
-	BUG_ON(a <= 0xc0000000 || a >= 0xe0000000);
-	return p;
-}
-
-#define __mem_pci(a)		___mem_pci(a)
-#endif
 
 #endif
diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h
index 37beed3..8de70de 100644
--- a/arch/arm/mach-integrator/include/mach/io.h
+++ b/arch/arm/mach-integrator/include/mach/io.h
@@ -29,6 +29,5 @@
 #define PCI_IO_VADDR            0xee000000
 
 #define __io(a)			((void __iomem *)(PCI_IO_VADDR + (a)))
-#define __mem_pci(a)		(a)
 
 #endif
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index 058dbfd..f131885 100644
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -22,8 +22,6 @@
 #define IO_SPACE_LIMIT 0xffffffff
 
 #define __io(a) __iop13xx_io(a)
-#define __mem_pci(a) (a)
-#define __mem_isa(a) (a)
 
 extern void __iomem * __iop13xx_io(unsigned long io_addr);
 
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
index 2d88264..e2ada26 100644
--- a/arch/arm/mach-iop32x/include/mach/io.h
+++ b/arch/arm/mach-iop32x/include/mach/io.h
@@ -15,6 +15,5 @@
 
 #define IO_SPACE_LIMIT		0xffffffff
 #define __io(p)		((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-#define __mem_pci(a)		(a)
 
 #endif
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
index a8a66fc..f7c1b65 100644
--- a/arch/arm/mach-iop33x/include/mach/io.h
+++ b/arch/arm/mach-iop33x/include/mach/io.h
@@ -15,6 +15,5 @@
 
 #define IO_SPACE_LIMIT		0xffffffff
 #define __io(p)		((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-#define __mem_pci(a)		(a)
 
 #endif
diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h
index 859e584..f6552d6 100644
--- a/arch/arm/mach-ixp2000/include/mach/io.h
+++ b/arch/arm/mach-ixp2000/include/mach/io.h
@@ -18,7 +18,6 @@
 #include <mach/hardware.h>
 
 #define IO_SPACE_LIMIT		0xffffffff
-#define __mem_pci(a)		(a)
 
 /*
  * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
index 4ce4353..a7aceb5 100644
--- a/arch/arm/mach-ixp23xx/include/mach/io.h
+++ b/arch/arm/mach-ixp23xx/include/mach/io.h
@@ -18,6 +18,5 @@
 #define IO_SPACE_LIMIT 0xffffffff
 
 #define __io(p)		((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
-#define __mem_pci(a)	(a)
 
 #endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index ffb9d6a..d76a9bb 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -39,11 +39,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  *    but in some cases the performance hit is acceptable. In addition, you
  *    cannot mmap() PCI devices in this case.
  */
-#ifndef	CONFIG_IXP4XX_INDIRECT_PCI
-
-#define __mem_pci(a)		(a)
-
-#else
+#ifdef	CONFIG_IXP4XX_INDIRECT_PCI
 
 /*
  * In the case of using indirect PCI, we simply return the actual PCI
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
index 49dd0cb..5d0ab61 100644
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ b/arch/arm/mach-kirkwood/include/mach/io.h
@@ -20,7 +20,5 @@ static inline void __iomem *__io(unsigned long addr)
 }
 
 #define __io(a)			__io(a)
-#define __mem_pci(a)		(a)
-
 
 #endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h
index 450e0e1..c7d9d00 100644
--- a/arch/arm/mach-mv78xx0/include/mach/io.h
+++ b/arch/arm/mach-mv78xx0/include/mach/io.h
@@ -20,7 +20,5 @@ static inline void __iomem *__io(unsigned long addr)
 }
 
 #define __io(a)			__io(a)
-#define __mem_pci(a)		(a)
-
 
 #endif
diff --git a/arch/arm/mach-rpc/include/mach/io.h b/arch/arm/mach-rpc/include/mach/io.h
index 695f4ed..707071a 100644
--- a/arch/arm/mach-rpc/include/mach/io.h
+++ b/arch/arm/mach-rpc/include/mach/io.h
@@ -28,9 +28,4 @@
  */
 #define __io(a)		(PCIO_BASE + ((a) << 2))
 
-/*
- * 1:1 mapping for ioremapped regions.
- */
-#define __mem_pci(x)	(x)
-
 #endif
diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c2410/include/mach/io.h
index 118749f..5dd1db4 100644
--- a/arch/arm/mach-s3c2410/include/mach/io.h
+++ b/arch/arm/mach-s3c2410/include/mach/io.h
@@ -208,9 +208,4 @@ DECLARE_IO(int,l,"")
 #define outsw(p,d,l)	__raw_writesw(__ioaddr(p),d,l)
 #define outsl(p,d,l)	__raw_writesl(__ioaddr(p),d,l)
 
-/*
- * 1:1 mapping for ioremapped regions.
- */
-#define __mem_pci(x)	(x)
-
 #endif
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
index 9ccbcec..1a45fc0 100644
--- a/arch/arm/mach-shark/include/mach/io.h
+++ b/arch/arm/mach-shark/include/mach/io.h
@@ -15,6 +15,4 @@
 
 #define __io(a)                 ((void __iomem *)(0xe0000000 + (a)))
 
-#define __mem_pci(addr) (addr)
-
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
index 47b4b61..fe700f9 100644
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -40,7 +40,6 @@ static inline void __iomem *__io(unsigned long addr)
 #endif
 
 #define __io(a)         __io(a)
-#define __mem_pci(a)    (a)
 
 #endif
 
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:33 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:33 -0600
Subject: [PATCH v3 21/30] ARM: Add fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-22-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

This adds a fixed virtual mapping for PCI i/o addresses. The mapping is
located at the last 1MB of vmalloc region (0xfef00000).

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/include/asm/io.h       |    5 +++++
 arch/arm/include/asm/mach/pci.h |   18 ++++++++++++++++++
 arch/arm/kernel/bios32.c        |   23 +++++++++++++++++++++++
 3 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index d7861b9..5a01930 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -106,11 +106,16 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 #define __iowmb()		do { } while (0)
 #endif
 
+#define PCI_IO_VIRT_BASE	0xfef00000
+
 /*
  * Now, pick up the machine-defined IO definitions
  */
 #ifdef CONFIG_NEED_MACH_IO_H
 #include <mach/io.h>
+#elif defined(CONFIG_PCI)
+#define IO_SPACE_LIMIT	((resource_size_t)0xfffff)
+#define __io(a)		__typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
 #else
 #define __io(a)		({ (void)(a); __typesafe_io(0); })
 #endif
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index d943b7d..6d326d7 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -60,6 +60,24 @@ struct pci_sys_data {
 void pci_common_init(struct hw_pci *);
 
 /*
+ * Setup fixed I/O mapping. Must be called from .map_io function.
+ */
+#ifdef CONFIG_PCI
+extern void pci_map_io_pfn(unsigned long pfn[], int nr);
+#else
+static inline void pci_map_io_pfn(unsigned long pfn[], int nr) {}
+#endif
+static inline void __init pci_map_io_single_pfn(unsigned long pfn)
+{
+	pci_map_io_pfn(&pfn, 1);
+}
+
+static inline void __init pci_map_io_single(unsigned long paddr)
+{
+	pci_map_io_single_pfn(__phys_to_pfn(paddr));
+}
+
+/*
  * PCI controllers
  */
 extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index f58ba35..199f383 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 
 #include <asm/mach-types.h>
+#include <asm/mach/map.h>
 #include <asm/mach/pci.h>
 
 static int debug_pci;
@@ -674,3 +675,25 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 
 	return 0;
 }
+
+static struct map_desc pci_io_desc __initdata = {
+	.virtual	= PCI_IO_VIRT_BASE,
+	.length		= SZ_1M,
+	.type		= MT_DEVICE,
+};
+
+void __init pci_map_io_pfn(unsigned long pfn[], int nr)
+{
+	int i;
+
+	if (nr > 1)
+		pci_io_desc.length = SZ_64K;
+
+	for (i = 0; i < nr; i++) {
+		pci_io_desc.pfn = pfn[i];
+		iotable_init(&pci_io_desc, 1);
+
+		pci_io_desc.virtual += SZ_64K;
+	}
+}
+
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:32 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:32 -0600
Subject: [PATCH v3 20/30] iop13xx: use more regular PCI I/O space handling
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-21-git-send-email-robherring2@gmail.com>

From: Arnd Bergmann <arnd at arndb.de>

iop13xx confuses I/O port numbers with physical addresses, which breaks
legacy ISA I/O access behind PCI bridges and makes it unnecessarily hard
to unify the inb/outb accessors with other platforms. This removes the
special-casing and just puts all I/O ports into a single 128KB virtually
mapped I/O port range starting at port zero.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/mach-iop13xx/include/mach/io.h      |    6 ++--
 arch/arm/mach-iop13xx/include/mach/iop13xx.h |   12 ++--------
 arch/arm/mach-iop13xx/io.c                   |   27 --------------------------
 arch/arm/mach-iop13xx/pci.c                  |   12 +++++-----
 4 files changed, 12 insertions(+), 45 deletions(-)

diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index f131885..e197cb8 100644
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -19,10 +19,10 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
+#include <mach/iop13xx.h>
 
-#define __io(a) __iop13xx_io(a)
+#define IO_SPACE_LIMIT (IOP13XX_PCIE_IO_WINDOW_SIZE + IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
 
-extern void __iomem * __iop13xx_io(unsigned long io_addr);
+#define __io(a) (IOP13XX_PCIX_LOWER_IO_VA + ((a) & IO_SPACE_LIMIT))
 
 #endif
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index 07e9ff7..ee1dfd2 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -68,17 +68,15 @@ extern unsigned long get_iop_tick_rate(void);
  * 0x8000.0000 + 928M	0x2.8000.0000   (ioremap)	PCIE outbound memory window
  *
  * IO MAP
- * 0x1000 + 64K	0x0.fffb.1000	0xfec6.1000	PCIX outbound i/o window
+ * 0x1000 + 64K	0x0.fffb.1000	0xfed6.1000	PCIX outbound i/o window
  * 0x1000 + 64K	0x0.fffd.1000	0xfed7.1000	PCIE outbound i/o window
  */
 #define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
 #define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
-#define IOP13XX_PCIX_LOWER_IO_VA      0xfec60000UL
+#define IOP13XX_PCIX_LOWER_IO_VA      0xfed60000UL
 #define IOP13XX_PCIX_LOWER_IO_BA      0x0UL /* OIOTVR */
 #define IOP13XX_PCIX_IO_BUS_OFFSET    0x1000UL
-#define IOP13XX_PCIX_UPPER_IO_PA      (IOP13XX_PCIX_LOWER_IO_PA +\
-				       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIX_UPPER_IO_VA      (IOP13XX_PCIX_LOWER_IO_VA +\
+#define IOP13XX_PCIX_UPPER_IO_BA      (IOP13XX_PCIX_LOWER_IO_BA +\
 				       IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
 #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
 					   (IOP13XX_PCIX_LOWER_IO_PA\
@@ -107,10 +105,6 @@ extern unsigned long get_iop_tick_rate(void);
 #define IOP13XX_PCIE_LOWER_IO_VA      	 0xfed70000UL
 #define IOP13XX_PCIE_LOWER_IO_BA      	 0x0UL  /* OIOTVR */
 #define IOP13XX_PCIE_IO_BUS_OFFSET	 0x1000UL
-#define IOP13XX_PCIE_UPPER_IO_PA      	 (IOP13XX_PCIE_LOWER_IO_PA +\
-					 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_UPPER_IO_VA      	 (IOP13XX_PCIE_LOWER_IO_VA +\
-					 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
 #define IOP13XX_PCIE_UPPER_IO_BA      	 (IOP13XX_PCIE_LOWER_IO_BA +\
 					 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
 #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 70f716f..e0ecb38 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,25 +23,6 @@
 
 #include "pci.h"
 
-void * __iomem __iop13xx_io(unsigned long io_addr)
-{
-	void __iomem * io_virt;
-
-	switch (io_addr) {
-	case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
-		io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr);
-		break;
-	case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
-		io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr);
-		break;
-	default:
-		BUG();
-	}
-
-	return io_virt;
-}
-EXPORT_SYMBOL(__iop13xx_io);
-
 void __iomem * __iop13xx_ioremap(unsigned long cookie, size_t size,
 	unsigned int mtype)
 {
@@ -67,12 +48,6 @@ void __iomem * __iop13xx_ioremap(unsigned long cookie, size_t size,
 				       (cookie - IOP13XX_PBI_LOWER_MEM_RA),
 				       size, mtype, __builtin_return_address(0));
 		break;
-	case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
-		retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
-		break;
-	case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
-		retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
-		break;
 	case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
 		retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
 		break;
@@ -102,8 +77,6 @@ void __iop13xx_iounmap(volatile void __iomem *addr)
 		    goto skip;
 
 	switch ((u32) addr) {
-	case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
-	case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
 	case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
 		goto skip;
 	}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index b8f5a87..d72eddf 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -1042,8 +1042,8 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
 				  << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
 		__raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
 
-		res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
-		res[0].end   = IOP13XX_PCIX_UPPER_IO_PA;
+		res[0].start = IOP13XX_PCIX_LOWER_IO_BA + IOP13XX_PCIX_IO_BUS_OFFSET;
+		res[0].end   = IOP13XX_PCIX_UPPER_IO_BA;
 		res[0].name  = "IQ81340 ATUX PCI I/O Space";
 		res[0].flags = IORESOURCE_IO;
 
@@ -1052,7 +1052,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
 		res[1].name  = "IQ81340 ATUX PCI Memory Space";
 		res[1].flags = IORESOURCE_MEM;
 		sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
-		sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
+		sys->io_offset = IOP13XX_PCIX_LOWER_IO_BA;
 		break;
 	case IOP13XX_INIT_ATU_ATUE:
 		/* Note: the function number field in the PCSR is ro */
@@ -1063,8 +1063,8 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
 
 		__raw_writel(pcsr, IOP13XX_ATUE_PCSR);
 
-		res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
-		res[0].end   = IOP13XX_PCIE_UPPER_IO_PA;
+		res[0].start = IOP13XX_PCIE_LOWER_IO_BA + IOP13XX_PCIE_IO_BUS_OFFSET;
+		res[0].end   = IOP13XX_PCIE_UPPER_IO_BA;
 		res[0].name  = "IQ81340 ATUE PCI I/O Space";
 		res[0].flags = IORESOURCE_IO;
 
@@ -1073,7 +1073,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
 		res[1].name  = "IQ81340 ATUE PCI Memory Space";
 		res[1].flags = IORESOURCE_MEM;
 		sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
-		sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
+		sys->io_offset = IOP13XX_PCIE_LOWER_IO_BA;
 		sys->map_irq = iop13xx_pcie_map_irq;
 		break;
 	default:
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:34 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:34 -0600
Subject: [PATCH v3 22/30] ARM: tegra: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-23-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Colin Cross <ccross at android.com>
Cc: Olof Johansson <olof at lixom.net>
Acked-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/Kconfig                         |    1 -
 arch/arm/mach-tegra/include/mach/io.h    |   46 ------------------------------
 arch/arm/mach-tegra/include/mach/iomap.h |    3 ++
 arch/arm/mach-tegra/io.c                 |    2 +
 arch/arm/mach-tegra/pcie.c               |   41 ++------------------------
 5 files changed, 9 insertions(+), 84 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/include/mach/io.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ae016cd..c98861f2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -660,7 +660,6 @@ config ARCH_TEGRA
 	select HAVE_SCHED_CLOCK
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
-	select NEED_MACH_IO_H if PCI
 	select ARCH_HAS_CPUFREQ
 	help
 	  This enables support for NVIDIA Tegra based systems (Tegra APX,
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
deleted file mode 100644
index fe700f9..0000000
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/io.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *	Colin Cross <ccross at google.com>
- *	Erik Gilling <konkers at google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_IO_H
-#define __MACH_TEGRA_IO_H
-
-#define IO_SPACE_LIMIT 0xffff
-
-#ifndef __ASSEMBLER__
-
-#ifdef CONFIG_TEGRA_PCI
-extern void __iomem *tegra_pcie_io_base;
-
-static inline void __iomem *__io(unsigned long addr)
-{
-	return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
-}
-#else
-static inline void __iomem *__io(unsigned long addr)
-{
-	return (void __iomem *)addr;
-}
-#endif
-
-#define __io(a)         __io(a)
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 082b4d1..e2b700a 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -303,6 +303,9 @@
 #define IO_APB_VIRT	IOMEM(0xFE300000)
 #define IO_APB_SIZE	SZ_1M
 
+#define TEGRA_PCIE_BASE		0x80000000
+#define TEGRA_PCIE_IO_BASE	(TEGRA_PCIE_BASE + SZ_4M)
+
 #define IO_TO_VIRT_BETWEEN(p, st, sz)	((p) >= (st) && (p) < ((st) + (sz)))
 #define IO_TO_VIRT_XLATE(p, pst, vst)	(((p) - (pst) + (vst)))
 
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index 58b4baf..7a29e10 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -26,6 +26,7 @@
 
 #include <asm/page.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include <mach/iomap.h>
 
 #include "board.h"
@@ -59,5 +60,6 @@ static struct map_desc tegra_io_desc[] __initdata = {
 
 void __init tegra_map_common_io(void)
 {
+	pci_map_io_single(TEGRA_PCIE_IO_BASE);
 	iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
 }
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index af8b634..442af44 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -171,8 +171,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
  * 0x90000000 - 0x9fffffff - non-prefetchable memory
  * 0xa0000000 - 0xbfffffff - prefetchable memory
  */
-#define TEGRA_PCIE_BASE		0x80000000
-
 #define PCIE_REGS_SZ		SZ_16K
 #define PCIE_CFG_OFF		PCIE_REGS_SZ
 #define PCIE_CFG_SZ		SZ_1M
@@ -180,8 +178,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
 #define PCIE_EXT_CFG_SZ		SZ_1M
 #define PCIE_IOMAP_SZ		(PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
 
-#define MMIO_BASE		(TEGRA_PCIE_BASE + SZ_4M)
-#define MMIO_SIZE		SZ_64K
 #define MEM_BASE_0		(TEGRA_PCIE_BASE + SZ_256M)
 #define MEM_SIZE_0		SZ_128M
 #define MEM_BASE_1		(MEM_BASE_0 + MEM_SIZE_0)
@@ -223,17 +219,7 @@ struct tegra_pcie_info {
 	struct clk		*pll_e;
 };
 
-static struct tegra_pcie_info tegra_pcie = {
-	.res_mmio = {
-		.name = "PCI IO",
-		.start = MMIO_BASE,
-		.end = MMIO_BASE + MMIO_SIZE - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-void __iomem *tegra_pcie_io_base;
-EXPORT_SYMBOL(tegra_pcie_io_base);
+static struct tegra_pcie_info tegra_pcie;
 
 static inline void afi_writel(u32 value, unsigned long offset)
 {
@@ -542,8 +528,8 @@ static void tegra_pcie_setup_translations(void)
 
 	/* Bar 2: downstream IO bar */
 	fpci_bar = ((__u32)0xfdfc << 16);
-	size = MMIO_SIZE;
-	axi_address = MMIO_BASE;
+	size = SZ_64K;
+	axi_address = TEGRA_PCIE_IO_BASE;
 	afi_writel(axi_address, AFI_AXI_BAR2_START);
 	afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
 	afi_writel(fpci_bar, AFI_FPCI_BAR2);
@@ -771,7 +757,6 @@ static void tegra_pcie_clocks_put(void)
 
 static int __init tegra_pcie_get_resources(void)
 {
-	struct resource *res_mmio = &tegra_pcie.res_mmio;
 	int err;
 
 	err = tegra_pcie_clocks_get();
@@ -793,34 +778,16 @@ static int __init tegra_pcie_get_resources(void)
 		goto err_map_reg;
 	}
 
-	err = request_resource(&iomem_resource, res_mmio);
-	if (err) {
-		pr_err("PCIE: Failed to request resources: %d\n", err);
-		goto err_req_io;
-	}
-
-	tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
-					     resource_size(res_mmio));
-	if (tegra_pcie_io_base == NULL) {
-		pr_err("PCIE: Failed to map IO\n");
-		err = -ENOMEM;
-		goto err_map_io;
-	}
-
 	err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
 			  IRQF_SHARED, "PCIE", &tegra_pcie);
 	if (err) {
 		pr_err("PCIE: Failed to register IRQ: %d\n", err);
-		goto err_irq;
+		goto err_req_io;
 	}
 	set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
 
 	return 0;
 
-err_irq:
-	iounmap(tegra_pcie_io_base);
-err_map_io:
-	release_resource(&tegra_pcie.res_mmio);
 err_req_io:
 	iounmap(tegra_pcie.regs);
 err_map_reg:
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:35 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:35 -0600
Subject: [PATCH v3 23/30] ARM: integrator: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-24-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/Kconfig                                 |    1 -
 arch/arm/mach-integrator/include/mach/io.h       |   33 ----------------------
 arch/arm/mach-integrator/include/mach/platform.h |    4 ++
 arch/arm/mach-integrator/integrator_ap.c         |   11 ++----
 4 files changed, 8 insertions(+), 41 deletions(-)
 delete mode 100644 arch/arm/mach-integrator/include/mach/io.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c98861f2..682c5d8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -268,7 +268,6 @@ config ARCH_INTEGRATOR
 	select GENERIC_CLOCKEVENTS
 	select PLAT_VERSATILE
 	select PLAT_VERSATILE_FPGA_IRQ
-	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for ARM's Integrator platform.
diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h
deleted file mode 100644
index 8de70de..0000000
--- a/arch/arm/mach-integrator/include/mach/io.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/io.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/*
- * WARNING: this has to mirror definitions in platform.h
- */
-#define PCI_MEMORY_VADDR        0xe8000000
-#define PCI_CONFIG_VADDR        0xec000000
-#define PCI_V3_VADDR            0xed000000
-#define PCI_IO_VADDR            0xee000000
-
-#define __io(a)			((void __iomem *)(PCI_IO_VADDR + (a)))
-
-#endif
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index ec467ba..4c03475 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -324,6 +324,10 @@
  */
 #define PHYS_PCI_V3_BASE                0x62000000
 
+#define PCI_MEMORY_VADDR		0xe8000000
+#define PCI_CONFIG_VADDR		0xec000000
+#define PCI_V3_VADDR			0xed000000
+
 /* ------------------------------------------------------------------------
  *  Integrator Interrupt Controllers
  * ------------------------------------------------------------------------
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 21a1d6c..410e6b1 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -48,13 +48,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 
 #include <plat/fpga-irq.h>
 
 #include "common.h"
 
-/* 
+/*
  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  * is the (PA >> 12).
  *
@@ -71,7 +72,7 @@
  * e8000000	40000000	PCI memory		PHYS_PCI_MEM_BASE	(max 512M)
  * ec000000	61000000	PCI config space	PHYS_PCI_CONFIG_BASE	(max 16M)
  * ed000000	62000000	PCI V3 regs		PHYS_PCI_V3_BASE	(max 64k)
- * ee000000	60000000	PCI IO			PHYS_PCI_IO_BASE	(max 16M)
+ * fef00000	60000000	PCI IO			PHYS_PCI_IO_BASE	(max 16M)
  * ef000000			Cache flush
  * f1000000	10000000	Core module registers
  * f1100000	11000000	System controller registers
@@ -145,16 +146,12 @@ static struct map_desc ap_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(PHYS_PCI_V3_BASE),
 		.length		= SZ_64K,
 		.type		= MT_DEVICE
-	}, {
-		.virtual	= PCI_IO_VADDR,
-		.pfn		= __phys_to_pfn(PHYS_PCI_IO_BASE),
-		.length		= SZ_64K,
-		.type		= MT_DEVICE
 	}
 };
 
 static void __init ap_map_io(void)
 {
+	pci_map_io_single(PHYS_PCI_IO_BASE);
 	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 	vga_base = PCI_MEMORY_VADDR;
 }
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:36 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:36 -0600
Subject: [PATCH v3 24/30] ARM: shark: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-25-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/Kconfig                               |    1 -
 arch/arm/mach-shark/core.c                     |   14 ++------------
 arch/arm/mach-shark/include/mach/debug-macro.S |    7 ++++---
 arch/arm/mach-shark/include/mach/entry-macro.S |    3 ++-
 arch/arm/mach-shark/include/mach/io.h          |   18 ------------------
 5 files changed, 8 insertions(+), 35 deletions(-)
 delete mode 100644 arch/arm/mach-shark/include/mach/io.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 682c5d8..b14bf3c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -893,7 +893,6 @@ config ARCH_SHARK
 	select PCI
 	select ARCH_USES_GETTIMEOFFSET
 	select NEED_MACH_MEMORY_H
-	select NEED_MACH_IO_H
 	help
 	  Support for the StrongARM based Digital DNARD machine, also known
 	  as "Shark" (<http://www.shark-linux.de/shark.html>).
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 6a2a7f2..da12ad0 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -17,11 +17,10 @@
 #include <asm/param.h>
 
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
-#define IO_BASE                 0xe0000000
-#define IO_SIZE                 0x08000000
 #define IO_START                0x40000000
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
@@ -103,18 +102,9 @@ arch_initcall(shark_init);
 
 extern void shark_init_irq(void);
 
-static struct map_desc shark_io_desc[] __initdata = {
-	{
-		.virtual	= IO_BASE,
-		.pfn		= __phys_to_pfn(IO_START),
-		.length		= IO_SIZE,
-		.type		= MT_DEVICE
-	}
-};
-
 static void __init shark_map_io(void)
 {
-	iotable_init(shark_io_desc, ARRAY_SIZE(shark_io_desc));
+	pci_map_io_single(IO_START);
 }
 
 #define IRQ_TIMER 0
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index 20eb2bf..b08ef9d 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -12,9 +12,10 @@
 */
 
 		.macro	addruart, rp, rv, tmp
-		mov	\rp, #0xe0000000
-		orr	\rp, \rp, #0x000003f8
-		mov	\rv, \rp
+		mov	\rp, #0x3f8
+		orr	\rv, \rp, #0xfe000000
+		orr	\rv, \rv, #0x00f00000
+		orr	\rp, \rp, #0x40000000
 		.endm
 
 		.macro	senduart,rd,rx
diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S
index 0bb6cc6..3ff46fc 100644
--- a/arch/arm/mach-shark/include/mach/entry-macro.S
+++ b/arch/arm/mach-shark/include/mach/entry-macro.S
@@ -11,7 +11,8 @@
 		.endm
 
 		.macro  get_irqnr_preamble, base, tmp
-		mov	\base, #0xe0000000
+		mov	\base, #0xfe000000
+		orr	\base, \base, #0x00f00000
 		.endm
 
 		.macro  arch_ret_to_user, tmp1, tmp2
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
deleted file mode 100644
index 1a45fc0..0000000
--- a/arch/arm/mach-shark/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/mach-shark/include/mach/io.h
- *
- * by Alexander Schulz
- *
- * derived from:
- * arch/arm/mach-ebsa110/include/mach/io.h
- * Copyright (C) 1997,1998 Russell King
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a)                 ((void __iomem *)(0xe0000000 + (a)))
-
-#endif
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:37 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:37 -0600
Subject: [PATCH v3 25/30] ARM: footbridge: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-26-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/Kconfig                                   |    2 +-
 arch/arm/mach-footbridge/common.c                  |   12 +++++-------
 .../arm/mach-footbridge/include/mach/debug-macro.S |    3 ++-
 arch/arm/mach-footbridge/include/mach/io.h         |   12 ++----------
 4 files changed, 10 insertions(+), 19 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b14bf3c..f2c6727 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -430,7 +430,7 @@ config ARCH_FOOTBRIDGE
 	select FOOTBRIDGE
 	select GENERIC_CLOCKEVENTS
 	select HAVE_IDE
-	select NEED_MACH_IO_H
+	select NEED_MACH_IO_H if !MMU
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for systems based on the DC21285 companion chip
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 41978ee..5c3c7a7 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
- 
+
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/irq.h>
@@ -25,6 +25,7 @@
 
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 
 #include "common.h"
 
@@ -174,11 +175,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(DC21285_PCI_IACK),
 		.length		= PCIIACK_SIZE,
 		.type		= MT_DEVICE,
-	}, {
-		.virtual	= PCIO_BASE,
-		.pfn		= __phys_to_pfn(DC21285_PCI_IO),
-		.length		= PCIO_SIZE,
-		.type		= MT_DEVICE,
 	},
 #endif
 };
@@ -195,8 +191,10 @@ void __init footbridge_map_io(void)
 	 * Now, work out what we've got to map in addition on this
 	 * platform.
 	 */
-	if (footbridge_cfn_mode())
+	if (footbridge_cfn_mode()) {
+		pci_map_io_single(DC21285_PCI_IO);
 		iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
+	}
 }
 
 void footbridge_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S
index e5acde2..87c75c8 100644
--- a/arch/arm/mach-footbridge/include/mach/debug-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S
@@ -17,7 +17,8 @@
 	/* For NetWinder debugging */
 		.macro	addruart, rp, rv, tmp
 		mov	\rp, #0x000003f8
-		orr	\rv, \rp, #0xff000000	@ virtual
+		orr	\rv, \rp, #0xfe000000	@ virtual
+		orr	\rv, \rv, #0x00f00000	@ virtual
 		orr	\rp, \rp, #0x7c000000	@ physical
 		.endm
 
diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
index aba531ee..aba4638 100644
--- a/arch/arm/mach-footbridge/include/mach/io.h
+++ b/arch/arm/mach-footbridge/include/mach/io.h
@@ -14,18 +14,10 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#ifdef CONFIG_MMU
-#define MMU_IO(a, b)	(a)
-#else
-#define MMU_IO(a, b)	(b)
-#endif
-
-#define PCIO_SIZE       0x00100000
-#define PCIO_BASE       MMU_IO(0xff000000, 0x7c000000)
-
 /*
- * Translation of various region addresses to virtual addresses
+ * Translation of various i/o addresses to host addresses for !CONFIG_MMU
  */
+#define PCIO_BASE       0x7c000000
 #define __io(a)			((void __iomem *)(PCIO_BASE + (a)))
 
 #endif
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:38 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:38 -0600
Subject: [PATCH v3 26/30] ARM: dove: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-27-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

The i/o regions are changed from 1MB to 64KB. It's likely that the 2nd
bus is not setup correctly.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig                       |    1 -
 arch/arm/mach-dove/common.c            |   15 +++++----------
 arch/arm/mach-dove/include/mach/dove.h |    8 +++-----
 arch/arm/mach-dove/include/mach/io.h   |   19 -------------------
 arch/arm/mach-dove/pcie.c              |    9 ++-------
 5 files changed, 10 insertions(+), 42 deletions(-)
 delete mode 100644 arch/arm/mach-dove/include/mach/io.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f2c6727..24fe29e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -553,7 +553,6 @@ config ARCH_DOVE
 	select PCI
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
-	select NEED_MACH_IO_H
 	select PLAT_ORION
 	help
 	  Support for the Marvell Dove SoC 88AP510
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index dd1429a..a062ba6 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -48,21 +48,16 @@ static struct map_desc dove_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
 		.length		= DOVE_NB_REGS_SIZE,
 		.type		= MT_DEVICE,
-	}, {
-		.virtual	= DOVE_PCIE0_IO_VIRT_BASE,
-		.pfn		= __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
-		.length		= DOVE_PCIE0_IO_SIZE,
-		.type		= MT_DEVICE,
-	}, {
-		.virtual	= DOVE_PCIE1_IO_VIRT_BASE,
-		.pfn		= __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
-		.length		= DOVE_PCIE1_IO_SIZE,
-		.type		= MT_DEVICE,
 	},
 };
 
 void __init dove_map_io(void)
 {
+	unsigned long pci_io_pfn[] = {
+		__phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
+		__phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
+	};
+	pci_map_io_pfn(pci_io_pfn, ARRAY_SIZE(pci_io_pfn));
 	iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
 }
 
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index ad1165d..50b9046 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -50,14 +50,12 @@
 #define DOVE_NB_REGS_SIZE		SZ_8M
 
 #define DOVE_PCIE0_IO_PHYS_BASE		0xf2000000
-#define DOVE_PCIE0_IO_VIRT_BASE		0xfee00000
 #define DOVE_PCIE0_IO_BUS_BASE		0x00000000
-#define DOVE_PCIE0_IO_SIZE		SZ_1M
+#define DOVE_PCIE0_IO_SIZE		SZ_64K
 
 #define DOVE_PCIE1_IO_PHYS_BASE		0xf2100000
-#define DOVE_PCIE1_IO_VIRT_BASE		0xfef00000
-#define DOVE_PCIE1_IO_BUS_BASE		0x00100000
-#define DOVE_PCIE1_IO_SIZE		SZ_1M
+#define DOVE_PCIE1_IO_BUS_BASE		0x00010000
+#define DOVE_PCIE1_IO_SIZE		SZ_64K
 
 /*
  * Dove Core Registers Map
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
deleted file mode 100644
index 29c8b85..0000000
--- a/arch/arm/mach-dove/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "dove.h"
-
-#define IO_SPACE_LIMIT		0xffffffff
-
-#define __io(a)  	((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
-						 DOVE_PCIE0_IO_VIRT_BASE))
-
-#endif
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 52e96d3..0a741bd 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -59,13 +59,8 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
 		 "PCIe %d I/O", pp->index);
 	pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
 	pp->res[0].name = pp->io_space_name;
-	if (pp->index == 0) {
-		pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
-		pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
-	} else {
-		pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
-		pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
-	}
+	pp->res[0].start = nr * SZ_64K;
+	pp->res[0].end = pp->res[0].start + SZ_64K;
 	pp->res[0].flags = IORESOURCE_IO;
 	if (request_resource(&ioport_resource, &pp->res[0]))
 		panic("Request PCIe IO resource failed\n");
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:39 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:39 -0600
Subject: [PATCH v3 27/30] ARM: kirkwood: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-28-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Lennert Buytenhek <kernel at wantstofly.org>
Cc: Nicolas Pitre <nico at fluxnic.net>
---
 arch/arm/Kconfig                               |    1 -
 arch/arm/mach-kirkwood/common.c                |   21 +++++++++------------
 arch/arm/mach-kirkwood/include/mach/io.h       |   24 ------------------------
 arch/arm/mach-kirkwood/include/mach/kirkwood.h |    8 +++-----
 arch/arm/mach-kirkwood/pcie.c                  |    8 ++++----
 5 files changed, 16 insertions(+), 46 deletions(-)
 delete mode 100644 arch/arm/mach-kirkwood/include/mach/io.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 24fe29e..50e68b6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -563,7 +563,6 @@ config ARCH_KIRKWOOD
 	select PCI
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
-	select NEED_MACH_IO_H
 	select PLAT_ORION
 	help
 	  Support for the following Marvell Kirkwood series SoCs:
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index cc15426..db4caa3 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -20,6 +20,7 @@
 #include <asm/timex.h>
 #include <asm/kexec.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
@@ -37,16 +38,6 @@
  ****************************************************************************/
 static struct map_desc kirkwood_io_desc[] __initdata = {
 	{
-		.virtual	= KIRKWOOD_PCIE_IO_VIRT_BASE,
-		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
-		.length		= KIRKWOOD_PCIE_IO_SIZE,
-		.type		= MT_DEVICE,
-	}, {
-		.virtual	= KIRKWOOD_PCIE1_IO_VIRT_BASE,
-		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
-		.length		= KIRKWOOD_PCIE1_IO_SIZE,
-		.type		= MT_DEVICE,
-	}, {
 		.virtual	= KIRKWOOD_REGS_VIRT_BASE,
 		.pfn		= __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
 		.length		= KIRKWOOD_REGS_SIZE,
@@ -56,6 +47,12 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
 
 void __init kirkwood_map_io(void)
 {
+	unsigned long pci_io_pfn[] = {
+		__phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
+		__phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
+	};
+	pci_map_io_pfn(pci_io_pfn, ARRAY_SIZE(pci_io_pfn));
+
 	iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
 }
 
@@ -472,7 +469,7 @@ void __init kirkwood_init(void)
 	kirkwood_xor1_init();
 	kirkwood_crypto_init();
 
-#ifdef CONFIG_KEXEC 
+#ifdef CONFIG_KEXEC
 	kexec_reinit = kirkwood_enable_pcie;
 #endif
 }
@@ -502,7 +499,7 @@ static int __init kirkwood_clock_gate(void)
 		/* Disable PHY */
 		writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
 	}
-	
+
 	/* For PCIe: first shutdown the phy */
 	if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
 		writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
deleted file mode 100644
index 5d0ab61..0000000
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "kirkwood.h"
-
-#define IO_SPACE_LIMIT		0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
-	return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE)
-					+ KIRKWOOD_PCIE_IO_VIRT_BASE);
-}
-
-#define __io(a)			__io(a)
-
-#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index fede3d5..63565fb 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -37,14 +37,12 @@
 #define KIRKWOOD_NAND_MEM_SIZE		SZ_1K
 
 #define KIRKWOOD_PCIE1_IO_PHYS_BASE	0xf3000000
-#define KIRKWOOD_PCIE1_IO_VIRT_BASE	0xfef00000
-#define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00100000
-#define KIRKWOOD_PCIE1_IO_SIZE		SZ_1M
+#define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00010000
+#define KIRKWOOD_PCIE1_IO_SIZE		SZ_64K
 
 #define KIRKWOOD_PCIE_IO_PHYS_BASE	0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE	0xfee00000
 #define KIRKWOOD_PCIE_IO_BUS_BASE	0x00000000
-#define KIRKWOOD_PCIE_IO_SIZE		SZ_1M
+#define KIRKWOOD_PCIE_IO_SIZE		SZ_64K
 
 #define KIRKWOOD_REGS_PHYS_BASE		0xf1000000
 #define KIRKWOOD_REGS_VIRT_BASE		0xfed00000
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index a066a6d..11f557e 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -126,8 +126,8 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
 	 * IORESOURCE_IO
 	 */
 	pp->res[0].name = "PCIe 0 I/O Space";
-	pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+	pp->res[0].start = 0;
+	pp->res[0].end = pp->res[0].start + SZ_64K - 1;
 	pp->res[0].flags = IORESOURCE_IO;
 
 	/*
@@ -148,8 +148,8 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
 	 * IORESOURCE_IO
 	 */
 	pp->res[0].name = "PCIe 1 I/O Space";
-	pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
-	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
+	pp->res[0].start = SZ_64K;
+	pp->res[0].end = pp->res[0].start + SZ_64K - 1;
 	pp->res[0].flags = IORESOURCE_IO;
 
 	/*
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:40 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:40 -0600
Subject: [PATCH v3 28/30] ARM: ixp23xx: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-29-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Lennert Buytenhek <kernel at wantstofly.org>
---
 arch/arm/Kconfig                             |    1 -
 arch/arm/mach-ixp23xx/core.c                 |    7 ++-----
 arch/arm/mach-ixp23xx/include/mach/io.h      |   22 ----------------------
 arch/arm/mach-ixp23xx/include/mach/ixp23xx.h |   20 +++++++++-----------
 arch/arm/mach-ixp23xx/pci.c                  |    2 +-
 5 files changed, 12 insertions(+), 40 deletions(-)
 delete mode 100644 arch/arm/mach-ixp23xx/include/mach/io.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 50e68b6..73a86c7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -517,7 +517,6 @@ config ARCH_IXP23XX
 	select CPU_XSC3
  	select PCI
 	select ARCH_USES_GETTIMEOFFSET
-	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for Intel's IXP23xx (XScale) family of processors.
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index 7c1495e..38cbb99 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -39,6 +39,7 @@
 #include <asm/pgtable.h>
 
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/arch.h>
@@ -73,11 +74,6 @@ static struct map_desc ixp23xx_io_desc[] __initdata = {
 	 	.pfn		= __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
 	 	.length		= IXP23XX_MSF_CSR_SIZE,
 		.type		= MT_DEVICE,
-	}, { /* PCI I/O Space */
-	 	.virtual	= IXP23XX_PCI_IO_VIRT,
-	 	.pfn		= __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
-	 	.length		= IXP23XX_PCI_IO_SIZE,
-		.type		= MT_DEVICE,
 	}, { /* PCI Config Space */
 	 	.virtual	= IXP23XX_PCI_CFG_VIRT,
 	 	.pfn		= __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
@@ -98,6 +94,7 @@ static struct map_desc ixp23xx_io_desc[] __initdata = {
 
 void __init ixp23xx_map_io(void)
 {
+	pci_map_io_single(__phys_to_pfn(IXP23XX_PCI_IO_PHYS));
 	iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
 }
 
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
deleted file mode 100644
index a7aceb5..0000000
--- a/arch/arm/mach-ixp23xx/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/io.h
- *
- * Original Author: Naeem M Afzal <naeem.m.afzal at intel.com>
- * Maintainer: Deepak Saxena <dsaxena at plexity.net>
- *
- * Copyright (C) 2003-2005 Intel Corp.
- * Copyright (C) 2005 MontaVista Software, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(p)		((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
-
-#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h b/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
index 6d02481..93309d7 100644
--- a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
+++ b/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
@@ -20,13 +20,12 @@
  * IXP2300 linux memory map:
  *
  * virt		phys		size
- * fffd0000	a0000000	64K		XSI2CPP_CSR
- * fffc0000	c4000000	4K		EXP_CFG
- * fff00000	c8000000	64K		PERIPHERAL
- * fe000000	1c0000000	16M		CAP_CSR
+ * fef00000	1d8000000	1M		PCI_IO
  * fd000000	1c8000000	16M		MSF_CSR
- * fb000000			16M		---
- * fa000000	1d8000000	32M		PCI_IO
+ * fbfd0000	a0000000	64K		XSI2CPP_CSR
+ * fbfc0000	c4000000	4K		EXP_CFG
+ * fbf00000	c8000000	64K		PERIPHERAL
+ * fa000000	1c0000000	16M		CAP_CSR
  * f8000000	1da000000	32M		PCI_CFG
  * f6000000	1de000000	32M		PCI_CREG
  * f4000000			32M		---
@@ -39,19 +38,19 @@
  * Static mappings.
  ****************************************************************************/
 #define IXP23XX_XSI2CPP_CSR_PHYS	0xa0000000
-#define IXP23XX_XSI2CPP_CSR_VIRT	0xfffd0000
+#define IXP23XX_XSI2CPP_CSR_VIRT	0xfbfd0000
 #define IXP23XX_XSI2CPP_CSR_SIZE	0x00010000
 
 #define IXP23XX_EXP_CFG_PHYS		0xc4000000
-#define IXP23XX_EXP_CFG_VIRT		0xfffc0000
+#define IXP23XX_EXP_CFG_VIRT		0xfbfc0000
 #define IXP23XX_EXP_CFG_SIZE		0x00001000
 
 #define IXP23XX_PERIPHERAL_PHYS		0xc8000000
-#define IXP23XX_PERIPHERAL_VIRT		0xfff00000
+#define IXP23XX_PERIPHERAL_VIRT		0xfbf00000
 #define IXP23XX_PERIPHERAL_SIZE		0x00010000
 
 #define IXP23XX_CAP_CSR_PHYS		0x1c0000000ULL
-#define IXP23XX_CAP_CSR_VIRT		0xfe000000
+#define IXP23XX_CAP_CSR_VIRT		0xfa000000
 #define IXP23XX_CAP_CSR_SIZE		0x01000000
 
 #define IXP23XX_MSF_CSR_PHYS		0x1c8000000ULL
@@ -59,7 +58,6 @@
 #define IXP23XX_MSF_CSR_SIZE		0x01000000
 
 #define IXP23XX_PCI_IO_PHYS		0x1d8000000ULL
-#define IXP23XX_PCI_IO_VIRT		0xfa000000
 #define IXP23XX_PCI_IO_SIZE		0x02000000
 
 #define IXP23XX_PCI_CFG_PHYS		0x1da000000ULL
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 25b5c46..f6f9b89 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -271,7 +271,7 @@ static struct resource ixp23xx_pci_mem_space = {
 
 static struct resource ixp23xx_pci_io_space = {
 	.start	= 0x00000100,
-	.end	= 0x01ffffff,
+	.end	= SZ_1M - 1,
 	.flags	= IORESOURCE_IO,
 	.name	= "PCI I/O Space"
 };
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:41 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:41 -0600
Subject: [PATCH v3 29/30] ARM: iop13xx: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-30-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig                             |    1 -
 arch/arm/mach-iop13xx/include/mach/io.h      |   28 --------------------------
 arch/arm/mach-iop13xx/include/mach/iop13xx.h |    7 ++---
 arch/arm/mach-iop13xx/setup.c                |   17 ++++++---------
 4 files changed, 10 insertions(+), 43 deletions(-)
 delete mode 100644 arch/arm/mach-iop13xx/include/mach/io.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 73a86c7..10c99f9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -483,7 +483,6 @@ config ARCH_IOP13XX
 	select PCI
 	select ARCH_SUPPORTS_MSI
 	select VMSPLIT_1G
-	select NEED_MACH_IO_H
 	select NEED_MACH_MEMORY_H
 	help
 	  Support for Intel's IOP13XX (XScale) family of processors.
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
deleted file mode 100644
index e197cb8..0000000
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * iop13xx custom ioremap implementation
- * Copyright (c) 2005-2006, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <mach/iop13xx.h>
-
-#define IO_SPACE_LIMIT (IOP13XX_PCIE_IO_WINDOW_SIZE + IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
-
-#define __io(a) (IOP13XX_PCIX_LOWER_IO_VA + ((a) & IO_SPACE_LIMIT))
-
-#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index ee1dfd2..8153ed2 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -5,6 +5,7 @@
 /* The ATU offsets can change based on the strapping */
 extern u32 iop13xx_atux_pmmr_offset;
 extern u32 iop13xx_atue_pmmr_offset;
+void iop13xx_init_early(void);
 void iop13xx_init_irq(void);
 void iop13xx_map_io(void);
 void iop13xx_platform_init(void);
@@ -68,12 +69,11 @@ extern unsigned long get_iop_tick_rate(void);
  * 0x8000.0000 + 928M	0x2.8000.0000   (ioremap)	PCIE outbound memory window
  *
  * IO MAP
- * 0x1000 + 64K	0x0.fffb.1000	0xfed6.1000	PCIX outbound i/o window
- * 0x1000 + 64K	0x0.fffd.1000	0xfed7.1000	PCIE outbound i/o window
+ * 0x1000 + 64K	0x0.fffb.1000	0xfef0.1000	PCIX outbound i/o window
+ * 0x1000 + 64K	0x0.fffd.1000	0xfef1.1000	PCIE outbound i/o window
  */
 #define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
 #define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
-#define IOP13XX_PCIX_LOWER_IO_VA      0xfed60000UL
 #define IOP13XX_PCIX_LOWER_IO_BA      0x0UL /* OIOTVR */
 #define IOP13XX_PCIX_IO_BUS_OFFSET    0x1000UL
 #define IOP13XX_PCIX_UPPER_IO_BA      (IOP13XX_PCIX_LOWER_IO_BA +\
@@ -102,7 +102,6 @@ extern unsigned long get_iop_tick_rate(void);
 /* PCI-E ranges */
 #define IOP13XX_PCIE_IO_WINDOW_SIZE   	 0x10000UL
 #define IOP13XX_PCIE_LOWER_IO_PA      	 0xfffd0000UL
-#define IOP13XX_PCIE_LOWER_IO_VA      	 0xfed70000UL
 #define IOP13XX_PCIE_LOWER_IO_BA      	 0x0UL  /* OIOTVR */
 #define IOP13XX_PCIE_IO_BUS_OFFSET	 0x1000UL
 #define IOP13XX_PCIE_UPPER_IO_BA      	 (IOP13XX_PCIE_LOWER_IO_BA +\
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index daabb1f..9038626 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -24,6 +24,7 @@
 #include <linux/mtd/physmap.h>
 #endif
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/hardware/iop_adma.h>
@@ -40,16 +41,6 @@ static struct map_desc iop13xx_std_desc[] __initdata = {
 		.pfn 	 = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
 		.length  = IOP13XX_PMMR_SIZE,
 		.type	 = MT_DEVICE,
-	}, { /* PCIE IO space */
-		.virtual = IOP13XX_PCIE_LOWER_IO_VA,
-		.pfn 	 = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
-		.length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
-		.type	 = MT_DEVICE,
-	}, { /* PCIX IO space */
-		.virtual = IOP13XX_PCIX_LOWER_IO_VA,
-		.pfn 	 = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
-		.length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
-		.type	 = MT_DEVICE,
 	},
 };
 
@@ -363,6 +354,12 @@ static struct platform_device iop13xx_adma_2_channel = {
 
 void __init iop13xx_map_io(void)
 {
+	unsigned long pfn[] = {
+		__phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
+		__phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
+	};
+	pci_map_io_pfn(pfn, ARRAY_SIZE(pfn));
+
 	/* Initialize the Static Page Table maps */
 	iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
 }
-- 
1.7.5.4



From robherring2 at gmail.com  Thu Mar  1 22:13:42 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu,  1 Mar 2012 21:13:42 -0600
Subject: [PATCH v3 30/30] ARM: orion5x: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
Message-ID: <1330658022-14559-31-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

orion5x i/o handling must have been broken as it had no __io()
translation. It may actually work now.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Lennert Buytenhek <kernel at wantstofly.org>
Cc: Nicolas Pitre <nico at fluxnic.net>
---
 arch/arm/mach-orion5x/common.c |   16 ++++++----------
 1 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 0e28bae..9bab4cb 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -24,6 +24,7 @@
 #include <asm/timex.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 #include <mach/bridge-regs.h>
 #include <mach/hardware.h>
@@ -44,16 +45,6 @@ static struct map_desc orion5x_io_desc[] __initdata = {
 		.length		= ORION5X_REGS_SIZE,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= ORION5X_PCIE_IO_VIRT_BASE,
-		.pfn		= __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
-		.length		= ORION5X_PCIE_IO_SIZE,
-		.type		= MT_DEVICE,
-	}, {
-		.virtual	= ORION5X_PCI_IO_VIRT_BASE,
-		.pfn		= __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
-		.length		= ORION5X_PCI_IO_SIZE,
-		.type		= MT_DEVICE,
-	}, {
 		.virtual	= ORION5X_PCIE_WA_VIRT_BASE,
 		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
 		.length		= ORION5X_PCIE_WA_SIZE,
@@ -63,6 +54,11 @@ static struct map_desc orion5x_io_desc[] __initdata = {
 
 void __init orion5x_map_io(void)
 {
+	unsigned long pci_io_pfn[] = {
+		__phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
+		__phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
+	};
+	pci_map_io_pfn(pci_io_pfn, ARRAY_SIZE(pci_io_pfn));
 	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
 }
 
-- 
1.7.5.4



From pullip.cho at samsung.com  Fri Mar  2 00:45:43 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Fri, 2 Mar 2012 14:45:43 +0900
Subject: [PATCH v9 0/2] iommu/exynos: Add IOMMU/System MMU driver for
 Samsung Exynos
In-Reply-To: <CAH9JG2Vg8o_mm0gM042T0-kjMUoAdLzF+DeGErD7R86H0xqXZQ@mail.gmail.com>
References: <001801ccf5e3$69d79860$3d86c920$%cho@samsung.com>
 <CAH9JG2Vg8o_mm0gM042T0-kjMUoAdLzF+DeGErD7R86H0xqXZQ@mail.gmail.com>
Message-ID: <CAHQjnONxO32WP40sJz80=rjv3kqxmx55MUvjvhhO_mo3DNH8-A@mail.gmail.com>

On Tue, Feb 28, 2012 at 4:01 PM, Kyungmin Park
<kyungmin.park at samsung.com> wrote:
> Hi,
>
> Some comments.
> 1. It's not same patch series. since it has additional feature,
> exynos5 series support which don't covered at previous time.
> 2. It assumes that name conversion is based on exynos5 as default. now
> you use gsc at exynos4 even though there's no gsc block. It should be
> fimc.

Thanks. I agree about the second and applied it in the next patchset.

>
> So I suggest to send exynos4 series patch as before and send
> additional exynos5 patch series next.
>

I will just extract a new patch that removes existing system MMU driver from
the previous 2 patches and the patchset will consist of 3 patches.


From paul at pwsan.com  Fri Mar  2 00:49:40 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 1 Mar 2012 22:49:40 -0700 (MST)
Subject: [PATCH-V2 2/2] arm:omap:am33xx: Add power domain data
In-Reply-To: <79CD15C6BA57404B839C016229A409A8317E5134@DBDE01.ent.ti.com>
References: <1324803628-16790-1-git-send-email-hvaibhav@ti.com>
 <1324803628-16790-3-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1202291810230.12752@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A8317E5134@DBDE01.ent.ti.com>
Message-ID: <alpine.DEB.2.00.1203011847480.22980@utopia.booyaka.com>

Hi

On Thu, 1 Mar 2012, Hiremath, Vaibhav wrote:

> I am not sure whether we access these bits explicitly. If I understand 
> correctly, API's which access these bits are not being called from 
> anywhere, For example,
> 
> 	omap4_pwrdm_read_mem_retst
> 	omap4_pwrdm_set_mem_retst
> 	omap4_pwrdm_set_mem_onst

They'll be needed for the functional powerstate code, device PM QoS, and 
OSWR.

> Currently the major issue would be, for PM_PER_PWRSTCTRL, where 
> LogicRETState bit has been moved to offset 3. This is being used in 
> omap4_pwrdm_set_logic_retst() api.
> 
> And in order to support weird/non-standard bit-offsets, we have to clean 
> omap2_pwrdm_get_mem_bank_onstate/retst/_mask() api and have bitshift 
> field in struct powerdomain, as you have rightly pointed out.

As you work on this, I have a request.  Please place the AM33xx 
powerdomain implementation functions into a separate file, 
powerdomain33xx.c perhaps, rather than trying to merge them with the OMAP4 
powerdomain implementation functions.

Some functions can be shared -- maybe place those into a separate file, 
powerdomain33xx_44xx.c perhaps?

> Is my all understanding correct?
> 
> If yes, do you think this patch should get blocked for above cleanup? I feel
> Cleanup can still follow, since this won't impact the AM33xx boot.
> 
> What's your opinion on this??

We can't merge patches which are known to be broken.  That's a rule from 
Linus (and a good one).  Better to try to get it right the first time it 
hits mainline.


- Paul


From rnayak at ti.com  Fri Mar  2 00:54:56 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 02 Mar 2012 11:24:56 +0530
Subject: [PATCH 2/4] mmc: omap_hsmmc: Use gpio_find_by_chip_name() for
 omap_hsmmc_gpio_init()
In-Reply-To: <20120301185528.29210.85854.stgit@kaulin.local>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185528.29210.85854.stgit@kaulin.local>
Message-ID: <4F5060B0.7010703@ti.com>

On Friday 02 March 2012 12:25 AM, Tony Lindgren wrote:
> Use gpio_find_by_chip_name() to find the GPIO pins as they can
> be dynamically allocated on various gpio_chips.
>
> Note that we don't want to touch the platform data as it can
> now specify the GPIO offset on a named gpio_chip.
>
> This removes the need to use callbacks to set the GPIO pins
> in platform data.

While one of the reasons for those callbacks was to set the GPIO
pins in platform data, I guess the other and more important one
was to make sure the init sequencing between twl4030-gpio and the
mmc device depending on it was done rightly. Doesn't this patch now
leave the sequencing to work by luck (in the absence of something
like deferred probe being in place) like is the case of twl6030 and
mmc init sequence on OMAP4 already?

regards,
Rajendra

>
> Cc: Chris Ball<cjb at laptop.org>
> Cc: Grant Likely<grant.likely at secretlab.ca>
> Cc: Rajendra Nayak<rnayak at ti.com>
> Signed-off-by: Tony Lindgren<tony at atomide.com>
> ---
>   arch/arm/mach-omap2/hsmmc.c           |    3 +
>   arch/arm/mach-omap2/hsmmc.h           |    5 ++
>   arch/arm/plat-omap/include/plat/mmc.h |    3 +
>   drivers/gpio/gpio-twl4030.c           |    2 +
>   drivers/mmc/host/omap_hsmmc.c         |  109 +++++++++++++++++++++------------
>   5 files changed, 82 insertions(+), 40 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
> index a97876d..dda88f7 100644
> --- a/arch/arm/mach-omap2/hsmmc.c
> +++ b/arch/arm/mach-omap2/hsmmc.c
> @@ -323,7 +323,10 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
>
>   	mmc->get_context_loss_count = hsmmc_get_context_loss;
>
> +	mmc->slots[0].gpiochip_cd = c->gpiochip_cd;
>   	mmc->slots[0].switch_pin = c->gpio_cd;
> +
> +	mmc->slots[0].gpiochip_wp = c->gpiochip_wp;
>   	mmc->slots[0].gpio_wp = c->gpio_wp;
>
>   	mmc->slots[0].remux = c->remux;
> diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
> index 07831cc..ffbb78d 100644
> --- a/arch/arm/mach-omap2/hsmmc.h
> +++ b/arch/arm/mach-omap2/hsmmc.h
> @@ -22,8 +22,13 @@ struct omap2_hsmmc_info {
>   	bool	no_off_init;	/* no power off when not in MMC sleep state */
>   	bool	vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */
>   	bool	deferred;	/* mmc needs a deferred probe */
> +
> +	char	*gpiochip_cd;	/* Optional gpiochip for gpio_cd */
>   	int	gpio_cd;	/* or -EINVAL */
> +
> +	char	*gpiochip_wp;	/* Optional gpiochip for gpio_wp */
>   	int	gpio_wp;	/* or -EINVAL */
> +
>   	char	*name;		/* or NULL for default */
>   	struct platform_device *pdev;	/* mmc controller instance */
>   	int	ocr_mask;	/* temporary HACK */
> diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
> index f75946c..cbfbdc3 100644
> --- a/arch/arm/plat-omap/include/plat/mmc.h
> +++ b/arch/arm/plat-omap/include/plat/mmc.h
> @@ -130,7 +130,10 @@ struct omap_mmc_platform_data {
>   #define HSMMC_HAS_UPDATED_RESET	(1<<  1)
>   		unsigned features;
>
> +		char *gpiochip_cd;		/* optional gpiochip for card detect */
>   		int switch_pin;			/* gpio (card detect) */
> +
> +		char *gpiochip_wp;		/* optional gpiochip for write protect */
>   		int gpio_wp;			/* gpio (write protect) */
>
>   		int (*set_bus_mode)(struct device *dev, int slot, int bus_mode);
> diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
> index b8b4f22..d0f266c 100644
> --- a/drivers/gpio/gpio-twl4030.c
> +++ b/drivers/gpio/gpio-twl4030.c
> @@ -391,6 +391,7 @@ static int __devinit gpio_twl4030_debounce(u32 debounce, u8 mmc_cd)
>   }
>
>   static int gpio_twl4030_remove(struct platform_device *pdev);
> +static struct platform_driver gpio_twl4030_driver;
>
>   static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
>   {
> @@ -430,6 +431,7 @@ no_irqs:
>   				pdata->debounce, pdata->mmc_cd,
>   				ret);
>
> +	twl_gpiochip.label = gpio_twl4030_driver.driver.name;
>   	twl_gpiochip.base = pdata->gpio_base;
>   	twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
>   	twl_gpiochip.dev =&pdev->dev;
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index fd0c661..1aa2420 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -176,6 +176,8 @@ struct omap_hsmmc_host {
>   	int			use_dma, dma_ch;
>   	int			dma_line_tx, dma_line_rx;
>   	int			slot_id;
> +	int			gpio_cd;
> +	int			gpio_wp;
>   	int			got_dbclk;
>   	int			response_busy;
>   	int			context_loss;
> @@ -192,26 +194,29 @@ struct omap_hsmmc_host {
>
>   static int omap_hsmmc_card_detect(struct device *dev, int slot)
>   {
> -	struct omap_mmc_platform_data *mmc = dev->platform_data;
> +	struct omap_hsmmc_host *host =
> +		platform_get_drvdata(to_platform_device(dev));
>
>   	/* NOTE: assumes card detect signal is active-low */
> -	return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
> +	return !gpio_get_value_cansleep(host->gpio_cd);
>   }
>
>   static int omap_hsmmc_get_wp(struct device *dev, int slot)
>   {
> -	struct omap_mmc_platform_data *mmc = dev->platform_data;
> +	struct omap_hsmmc_host *host =
> +		platform_get_drvdata(to_platform_device(dev));
>
>   	/* NOTE: assumes write protect signal is active-high */
> -	return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
> +	return gpio_get_value_cansleep(host->gpio_wp);
>   }
>
>   static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
>   {
> -	struct omap_mmc_platform_data *mmc = dev->platform_data;
> +	struct omap_hsmmc_host *host =
> +		platform_get_drvdata(to_platform_device(dev));
>
>   	/* NOTE: assumes card detect signal is active-low */
> -	return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
> +	return !gpio_get_value_cansleep(host->gpio_cd);
>   }
>
>   #ifdef CONFIG_PM
> @@ -497,55 +502,80 @@ static inline int omap_hsmmc_have_reg(void)
>
>   #endif
>
> -static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
> +static int omap_hsmmc_gpio_init(struct omap_hsmmc_host *host)
>   {
> -	int ret;
> -
> -	if (gpio_is_valid(pdata->slots[0].switch_pin)) {
> -		if (pdata->slots[0].cover)
> -			pdata->slots[0].get_cover_state =
> +	struct omap_mmc_platform_data *pdata = host->pdata;
> +	struct omap_mmc_slot_data *slot =&pdata->slots[0];
> +	int gpio, ret;
> +
> +	gpio = slot->switch_pin;
> +	if (slot->gpiochip_cd)
> +		gpio = gpio_find_by_chip_name(slot->gpiochip_cd, gpio);
> +	if (gpio_is_valid(gpio)) {
> +		if (slot->cover)
> +			slot->get_cover_state =
>   					omap_hsmmc_get_cover_state;
>   		else
> -			pdata->slots[0].card_detect = omap_hsmmc_card_detect;
> -		pdata->slots[0].card_detect_irq =
> -				gpio_to_irq(pdata->slots[0].switch_pin);
> -		ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
> +			slot->card_detect = omap_hsmmc_card_detect;
> +		slot->card_detect_irq =
> +				gpio_to_irq(gpio);
> +		ret = gpio_request(gpio, "mmc_cd");
>   		if (ret)
>   			return ret;
> -		ret = gpio_direction_input(pdata->slots[0].switch_pin);
> +		ret = gpio_direction_input(gpio);
>   		if (ret)
>   			goto err_free_sp;
> -	} else
> -		pdata->slots[0].switch_pin = -EINVAL;
> +		host->gpio_cd = gpio;
> +	} else {
> +		if (slot->gpiochip_cd) {
> +			pr_warning("MMC %s card detect GPIO chip %s unavailable\n",
> +				slot->name, slot->gpiochip_cd);
> +			ret = -ENODEV;
> +			goto err_free_sp;
> +		}
> +		host->gpio_cd = -EINVAL;
> +	}
>
> -	if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
> -		pdata->slots[0].get_ro = omap_hsmmc_get_wp;
> -		ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
> +	gpio = slot->gpio_wp;
> +	if (slot->gpiochip_wp)
> +		gpio = gpio_find_by_chip_name(slot->gpiochip_wp, gpio);
> +	if (gpio_is_valid(gpio)) {
> +		slot->get_ro = omap_hsmmc_get_wp;
> +		ret = gpio_request(gpio, "mmc_wp");
>   		if (ret)
>   			goto err_free_cd;
> -		ret = gpio_direction_input(pdata->slots[0].gpio_wp);
> +		ret = gpio_direction_input(gpio);
>   		if (ret)
>   			goto err_free_wp;
> -	} else
> -		pdata->slots[0].gpio_wp = -EINVAL;
> +		host->gpio_wp = gpio;
> +	} else {
> +		if (slot->gpiochip_wp) {
> +			pr_warning("MMC %s write protect GPIO chip %s unavailable\n",
> +				slot->name, slot->gpiochip_wp);
> +			ret = -ENODEV;
> +			goto err_free_wp;
> +		}
> +		host->gpio_wp = -EINVAL;
> +	}
>
>   	return 0;
>
>   err_free_wp:
> -	gpio_free(pdata->slots[0].gpio_wp);
> +	if (gpio_is_valid(host->gpio_wp))
> +		gpio_free(host->gpio_wp);
>   err_free_cd:
> -	if (gpio_is_valid(pdata->slots[0].switch_pin))
> +	if (gpio_is_valid(host->gpio_cd))
>   err_free_sp:
> -		gpio_free(pdata->slots[0].switch_pin);
> +		gpio_free(host->gpio_cd);
>   	return ret;
>   }
>
> -static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
> +static void omap_hsmmc_gpio_free(struct omap_hsmmc_host *host)
>   {
> -	if (gpio_is_valid(pdata->slots[0].gpio_wp))
> -		gpio_free(pdata->slots[0].gpio_wp);
> -	if (gpio_is_valid(pdata->slots[0].switch_pin))
> -		gpio_free(pdata->slots[0].switch_pin);
> +	if (gpio_is_valid(host->gpio_wp))
> +		gpio_free(host->gpio_wp);
> +	if (gpio_is_valid(host->gpio_cd))
> +		gpio_free(host->gpio_cd);
>   }
>
>   /*
> @@ -1876,10 +1906,6 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>   	if (res == NULL)
>   		return -EBUSY;
>
> -	ret = omap_hsmmc_gpio_init(pdata);
> -	if (ret)
> -		goto err;
> -
>   	mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host),&pdev->dev);
>   	if (!mmc) {
>   		ret = -ENOMEM;
> @@ -1903,6 +1929,10 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>
>   	platform_set_drvdata(pdev, host);
>
> +	ret = omap_hsmmc_gpio_init(host);
> +	if (ret)
> +		goto err1;
> +
>   	mmc->ops	=&omap_hsmmc_ops;
>
>   	/*
> @@ -2093,8 +2123,7 @@ err1:
>   	platform_set_drvdata(pdev, NULL);
>   	mmc_free_host(mmc);
>   err_alloc:
> -	omap_hsmmc_gpio_free(pdata);
> -err:
> +	omap_hsmmc_gpio_free(host);
>   	release_mem_region(res->start, resource_size(res));
>   	return ret;
>   }
> @@ -2125,7 +2154,7 @@ static int omap_hsmmc_remove(struct platform_device *pdev)
>
>   		mmc_free_host(host->mmc);
>   		iounmap(host->base);
> -		omap_hsmmc_gpio_free(pdev->dev.platform_data);
> +		omap_hsmmc_gpio_free(host);
>   	}
>
>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>



From jh80.chung at samsung.com  Fri Mar  2 00:58:24 2012
From: jh80.chung at samsung.com (Jaehoon Chung)
Date: Fri, 02 Mar 2012 14:58:24 +0900
Subject: [PATCH V2 1/1] mmc: start removing enable / disable API
In-Reply-To: <1330499841-6879-2-git-send-email-adrian.hunter@intel.com>
References: <1330499841-6879-1-git-send-email-adrian.hunter@intel.com>
 <1330499841-6879-2-git-send-email-adrian.hunter@intel.com>
Message-ID: <4F506180.1030203@samsung.com>

Tested on Samsung-SoC
Tested-by: Jaehoon Chung <jh80.chung at samsung.com>
On 02/29/2012 04:17 PM, Adrian Hunter wrote:

> Most parts of the enable / disable API are no longer used and
> can be removed.
> 
> Cc: Rajendra Nayak <rnayak at ti.com>
> Cc: Venkatraman S <svenkatr at ti.com>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Cc: Thomas Abraham <thomas.abraham at linaro.org>
> Cc: Kyungmin Park <kyungmin.park at samsung.com>
> Cc: Sekhar Nori <nsekhar at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Signed-off-by: Adrian Hunter <adrian.hunter at intel.com>
> ---
>  arch/arm/mach-exynos/mach-nuri.c           |    5 +-
>  arch/arm/mach-exynos/mach-universal_c210.c |    9 +-
>  drivers/mmc/core/core.c                    |  187 +++-------------------------
>  drivers/mmc/core/host.c                    |    1 -
>  drivers/mmc/core/host.h                    |    1 -
>  drivers/mmc/host/davinci_mmc.c             |    4 -
>  drivers/mmc/host/omap_hsmmc.c              |   15 +--
>  include/linux/mmc/core.h                   |    1 -
>  include/linux/mmc/host.h                   |   46 +------
>  9 files changed, 27 insertions(+), 242 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
> index 644af11..de68248 100644
> --- a/arch/arm/mach-exynos/mach-nuri.c
> +++ b/arch/arm/mach-exynos/mach-nuri.c
> @@ -109,7 +109,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
>  	.max_width		= 8,
>  	.host_caps		= (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
>  				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> -				MMC_CAP_DISABLE | MMC_CAP_ERASE),
> +				MMC_CAP_ERASE),
>  	.cd_type		= S3C_SDHCI_CD_PERMANENT,
>  };
>  
> @@ -147,8 +147,7 @@ static struct platform_device emmc_fixed_voltage = {
>  static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
>  	.max_width		= 4,
>  	.host_caps		= MMC_CAP_4_BIT_DATA |
> -				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> -				MMC_CAP_DISABLE,
> +				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>  	.ext_cd_gpio		= EXYNOS4_GPX3(3),	/* XEINT_27 */
>  	.ext_cd_gpio_invert	= 1,
>  	.cd_type		= S3C_SDHCI_CD_GPIO,
> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
> index 9b3fbae..57cfe61 100644
> --- a/arch/arm/mach-exynos/mach-universal_c210.c
> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
> @@ -734,8 +734,7 @@ static struct platform_device universal_gpio_keys = {
>  static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
>  	.max_width		= 8,
>  	.host_caps		= (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
> -				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> -				MMC_CAP_DISABLE),
> +				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
>  	.cd_type		= S3C_SDHCI_CD_PERMANENT,
>  };
>  
> @@ -772,8 +771,7 @@ static struct platform_device mmc0_fixed_voltage = {
>  static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
>  	.max_width		= 4,
>  	.host_caps		= MMC_CAP_4_BIT_DATA |
> -				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> -				MMC_CAP_DISABLE,
> +				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>  	.ext_cd_gpio		= EXYNOS4_GPX3(4),      /* XEINT_28 */
>  	.ext_cd_gpio_invert	= 1,
>  	.cd_type		= S3C_SDHCI_CD_GPIO,
> @@ -783,8 +781,7 @@ static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
>  static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
>  	.max_width		= 4,
>  	.host_caps		= MMC_CAP_4_BIT_DATA |
> -				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> -				MMC_CAP_DISABLE,
> +				MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
>  	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
>  };
>  
> diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
> index 0b317f0..44dd013 100644
> --- a/drivers/mmc/core/core.c
> +++ b/drivers/mmc/core/core.c
> @@ -605,105 +605,6 @@ unsigned int mmc_align_data_size(struct mmc_card *card, unsigned int sz)
>  EXPORT_SYMBOL(mmc_align_data_size);
>  
>  /**
> - *	mmc_host_enable - enable a host.
> - *	@host: mmc host to enable
> - *
> - *	Hosts that support power saving can use the 'enable' and 'disable'
> - *	methods to exit and enter power saving states. For more information
> - *	see comments for struct mmc_host_ops.
> - */
> -int mmc_host_enable(struct mmc_host *host)
> -{
> -	if (!(host->caps & MMC_CAP_DISABLE))
> -		return 0;
> -
> -	if (host->en_dis_recurs)
> -		return 0;
> -
> -	if (host->nesting_cnt++)
> -		return 0;
> -
> -	cancel_delayed_work_sync(&host->disable);
> -
> -	if (host->enabled)
> -		return 0;
> -
> -	if (host->ops->enable) {
> -		int err;
> -
> -		host->en_dis_recurs = 1;
> -		mmc_host_clk_hold(host);
> -		err = host->ops->enable(host);
> -		mmc_host_clk_release(host);
> -		host->en_dis_recurs = 0;
> -
> -		if (err) {
> -			pr_debug("%s: enable error %d\n",
> -				 mmc_hostname(host), err);
> -			return err;
> -		}
> -	}
> -	host->enabled = 1;
> -	return 0;
> -}
> -EXPORT_SYMBOL(mmc_host_enable);
> -
> -static int mmc_host_do_disable(struct mmc_host *host, int lazy)
> -{
> -	if (host->ops->disable) {
> -		int err;
> -
> -		host->en_dis_recurs = 1;
> -		mmc_host_clk_hold(host);
> -		err = host->ops->disable(host, lazy);
> -		mmc_host_clk_release(host);
> -		host->en_dis_recurs = 0;
> -
> -		if (err < 0) {
> -			pr_debug("%s: disable error %d\n",
> -				 mmc_hostname(host), err);
> -			return err;
> -		}
> -		if (err > 0) {
> -			unsigned long delay = msecs_to_jiffies(err);
> -
> -			mmc_schedule_delayed_work(&host->disable, delay);
> -		}
> -	}
> -	host->enabled = 0;
> -	return 0;
> -}
> -
> -/**
> - *	mmc_host_disable - disable a host.
> - *	@host: mmc host to disable
> - *
> - *	Hosts that support power saving can use the 'enable' and 'disable'
> - *	methods to exit and enter power saving states. For more information
> - *	see comments for struct mmc_host_ops.
> - */
> -int mmc_host_disable(struct mmc_host *host)
> -{
> -	int err;
> -
> -	if (!(host->caps & MMC_CAP_DISABLE))
> -		return 0;
> -
> -	if (host->en_dis_recurs)
> -		return 0;
> -
> -	if (--host->nesting_cnt)
> -		return 0;
> -
> -	if (!host->enabled)
> -		return 0;
> -
> -	err = mmc_host_do_disable(host, 0);
> -	return err;
> -}
> -EXPORT_SYMBOL(mmc_host_disable);
> -
> -/**
>   *	__mmc_claim_host - exclusively claim a host
>   *	@host: mmc host to claim
>   *	@abort: whether or not the operation should be aborted
> @@ -741,8 +642,8 @@ int __mmc_claim_host(struct mmc_host *host, atomic_t *abort)
>  		wake_up(&host->wq);
>  	spin_unlock_irqrestore(&host->lock, flags);
>  	remove_wait_queue(&host->wq, &wait);
> -	if (!stop)
> -		mmc_host_enable(host);
> +	if (host->ops->enable && !stop && host->claim_cnt == 1)
> +		host->ops->enable(host);
>  	return stop;
>  }
>  
> @@ -767,21 +668,28 @@ int mmc_try_claim_host(struct mmc_host *host)
>  		claimed_host = 1;
>  	}
>  	spin_unlock_irqrestore(&host->lock, flags);
> +	if (host->ops->enable && claimed_host && host->claim_cnt == 1)
> +		host->ops->enable(host);
>  	return claimed_host;
>  }
>  EXPORT_SYMBOL(mmc_try_claim_host);
>  
>  /**
> - *	mmc_do_release_host - release a claimed host
> + *	mmc_release_host - release a host
>   *	@host: mmc host to release
>   *
> - *	If you successfully claimed a host, this function will
> - *	release it again.
> + *	Release a MMC host, allowing others to claim the host
> + *	for their operations.
>   */
> -void mmc_do_release_host(struct mmc_host *host)
> +void mmc_release_host(struct mmc_host *host)
>  {
>  	unsigned long flags;
>  
> +	WARN_ON(!host->claimed);
> +
> +	if (host->ops->disable && host->claim_cnt == 1)
> +		host->ops->disable(host);
> +
>  	spin_lock_irqsave(&host->lock, flags);
>  	if (--host->claim_cnt) {
>  		/* Release for nested claim */
> @@ -793,67 +701,6 @@ void mmc_do_release_host(struct mmc_host *host)
>  		wake_up(&host->wq);
>  	}
>  }
> -EXPORT_SYMBOL(mmc_do_release_host);
> -
> -void mmc_host_deeper_disable(struct work_struct *work)
> -{
> -	struct mmc_host *host =
> -		container_of(work, struct mmc_host, disable.work);
> -
> -	/* If the host is claimed then we do not want to disable it anymore */
> -	if (!mmc_try_claim_host(host))
> -		return;
> -	mmc_host_do_disable(host, 1);
> -	mmc_do_release_host(host);
> -}
> -
> -/**
> - *	mmc_host_lazy_disable - lazily disable a host.
> - *	@host: mmc host to disable
> - *
> - *	Hosts that support power saving can use the 'enable' and 'disable'
> - *	methods to exit and enter power saving states. For more information
> - *	see comments for struct mmc_host_ops.
> - */
> -int mmc_host_lazy_disable(struct mmc_host *host)
> -{
> -	if (!(host->caps & MMC_CAP_DISABLE))
> -		return 0;
> -
> -	if (host->en_dis_recurs)
> -		return 0;
> -
> -	if (--host->nesting_cnt)
> -		return 0;
> -
> -	if (!host->enabled)
> -		return 0;
> -
> -	if (host->disable_delay) {
> -		mmc_schedule_delayed_work(&host->disable,
> -				msecs_to_jiffies(host->disable_delay));
> -		return 0;
> -	} else
> -		return mmc_host_do_disable(host, 1);
> -}
> -EXPORT_SYMBOL(mmc_host_lazy_disable);
> -
> -/**
> - *	mmc_release_host - release a host
> - *	@host: mmc host to release
> - *
> - *	Release a MMC host, allowing others to claim the host
> - *	for their operations.
> - */
> -void mmc_release_host(struct mmc_host *host)
> -{
> -	WARN_ON(!host->claimed);
> -
> -	mmc_host_lazy_disable(host);
> -
> -	mmc_do_release_host(host);
> -}
> -
>  EXPORT_SYMBOL(mmc_release_host);
>  
>  /*
> @@ -2206,8 +2053,6 @@ void mmc_stop_host(struct mmc_host *host)
>  	spin_unlock_irqrestore(&host->lock, flags);
>  #endif
>  
> -	if (host->caps & MMC_CAP_DISABLE)
> -		cancel_delayed_work(&host->disable);
>  	cancel_delayed_work_sync(&host->detect);
>  	mmc_flush_scheduled_work();
>  
> @@ -2402,13 +2247,11 @@ int mmc_suspend_host(struct mmc_host *host)
>  {
>  	int err = 0;
>  
> -	if (host->caps & MMC_CAP_DISABLE)
> -		cancel_delayed_work(&host->disable);
>  	cancel_delayed_work(&host->detect);
>  	mmc_flush_scheduled_work();
>  	if (mmc_try_claim_host(host)) {
>  		err = mmc_cache_ctrl(host, 0);
> -		mmc_do_release_host(host);
> +		mmc_release_host(host);
>  	} else {
>  		err = -EBUSY;
>  	}
> @@ -2429,7 +2272,7 @@ int mmc_suspend_host(struct mmc_host *host)
>  			if (host->bus_ops->suspend) {
>  				err = host->bus_ops->suspend(host);
>  			}
> -			mmc_do_release_host(host);
> +			mmc_release_host(host);
>  
>  			if (err == -ENOSYS || !host->bus_ops->resume) {
>  				/*
> diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
> index c3704e2..91c84c7 100644
> --- a/drivers/mmc/core/host.c
> +++ b/drivers/mmc/core/host.c
> @@ -330,7 +330,6 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
>  	spin_lock_init(&host->lock);
>  	init_waitqueue_head(&host->wq);
>  	INIT_DELAYED_WORK(&host->detect, mmc_rescan);
> -	INIT_DELAYED_WORK_DEFERRABLE(&host->disable, mmc_host_deeper_disable);
>  #ifdef CONFIG_PM
>  	host->pm_notify.notifier_call = mmc_pm_notify;
>  #endif
> diff --git a/drivers/mmc/core/host.h b/drivers/mmc/core/host.h
> index 08a7852..f2ab9e5 100644
> --- a/drivers/mmc/core/host.h
> +++ b/drivers/mmc/core/host.h
> @@ -14,7 +14,6 @@
>  
>  int mmc_register_host_class(void);
>  void mmc_unregister_host_class(void);
> -void mmc_host_deeper_disable(struct work_struct *work);
>  
>  #endif
>  
> diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
> index 64a8325..8de9c9b 100644
> --- a/drivers/mmc/host/davinci_mmc.c
> +++ b/drivers/mmc/host/davinci_mmc.c
> @@ -1418,17 +1418,14 @@ static int davinci_mmcsd_suspend(struct device *dev)
>  	struct mmc_davinci_host *host = platform_get_drvdata(pdev);
>  	int ret;
>  
> -	mmc_host_enable(host->mmc);
>  	ret = mmc_suspend_host(host->mmc);
>  	if (!ret) {
>  		writel(0, host->base + DAVINCI_MMCIM);
>  		mmc_davinci_reset_ctrl(host, 1);
> -		mmc_host_disable(host->mmc);
>  		clk_disable(host->clk);
>  		host->suspended = 1;
>  	} else {
>  		host->suspended = 0;
> -		mmc_host_disable(host->mmc);
>  	}
>  
>  	return ret;
> @@ -1444,7 +1441,6 @@ static int davinci_mmcsd_resume(struct device *dev)
>  		return 0;
>  
>  	clk_enable(host->clk);
> -	mmc_host_enable(host->mmc);
>  
>  	mmc_davinci_reset_ctrl(host, 0);
>  	ret = mmc_resume_host(host->mmc);
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index 36e7f5b..fdb24cf 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -179,7 +179,6 @@ struct omap_hsmmc_host {
>  	int			got_dbclk;
>  	int			response_busy;
>  	int			context_loss;
> -	int			dpm_state;
>  	int			vdd;
>  	int			protect_card;
>  	int			reqs_blocked;
> @@ -1748,7 +1747,7 @@ static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
>  	return 0;
>  }
>  
> -static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
> +static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
>  {
>  	struct omap_hsmmc_host *host = mmc_priv(mmc);
>  
> @@ -1782,15 +1781,8 @@ static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
>  	if (host->pdata->get_context_loss_count)
>  		context_loss = host->pdata->get_context_loss_count(host->dev);
>  
> -	seq_printf(s, "mmc%d:\n"
> -			" enabled:\t%d\n"
> -			" dpm_state:\t%d\n"
> -			" nesting_cnt:\t%d\n"
> -			" ctx_loss:\t%d:%d\n"
> -			"\nregs:\n",
> -			mmc->index, mmc->enabled ? 1 : 0,
> -			host->dpm_state, mmc->nesting_cnt,
> -			host->context_loss, context_loss);
> +	seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
> +			mmc->index, host->context_loss, context_loss);
>  
>  	if (host->suspended) {
>  		seq_printf(s, "host suspended, can't read registers\n");
> @@ -1930,7 +1922,6 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>  
>  	omap_hsmmc_context_save(host);
>  
> -	mmc->caps |= MMC_CAP_DISABLE;
>  	if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
>  		dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
>  		mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
> diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
> index 87a976c..2bfa589 100644
> --- a/include/linux/mmc/core.h
> +++ b/include/linux/mmc/core.h
> @@ -175,7 +175,6 @@ extern unsigned int mmc_align_data_size(struct mmc_card *, unsigned int);
>  
>  extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort);
>  extern void mmc_release_host(struct mmc_host *host);
> -extern void mmc_do_release_host(struct mmc_host *host);
>  extern int mmc_try_claim_host(struct mmc_host *host);
>  
>  extern int mmc_flush_cache(struct mmc_card *);
> diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
> index 37147a4..4da98f7 100644
> --- a/include/linux/mmc/host.h
> +++ b/include/linux/mmc/host.h
> @@ -80,34 +80,11 @@ struct mmc_ios {
>  
>  struct mmc_host_ops {
>  	/*
> -	 * Hosts that support power saving can use the 'enable' and 'disable'
> -	 * methods to exit and enter power saving states. 'enable' is called
> -	 * when the host is claimed and 'disable' is called (or scheduled with
> -	 * a delay) when the host is released. The 'disable' is scheduled if
> -	 * the disable delay set by 'mmc_set_disable_delay()' is non-zero,
> -	 * otherwise 'disable' is called immediately. 'disable' may be
> -	 * scheduled repeatedly, to permit ever greater power saving at the
> -	 * expense of ever greater latency to re-enable. Rescheduling is
> -	 * determined by the return value of the 'disable' method. A positive
> -	 * value gives the delay in milliseconds.
> -	 *
> -	 * In the case where a host function (like set_ios) may be called
> -	 * with or without the host claimed, enabling and disabling can be
> -	 * done directly and will nest correctly. Call 'mmc_host_enable()' and
> -	 * 'mmc_host_lazy_disable()' for this purpose, but note that these
> -	 * functions must be paired.
> -	 *
> -	 * Alternatively, 'mmc_host_enable()' may be paired with
> -	 * 'mmc_host_disable()' which calls 'disable' immediately.  In this
> -	 * case the 'disable' method will be called with 'lazy' set to 0.
> -	 * This is mainly useful for error paths.
> -	 *
> -	 * Because lazy disable may be called from a work queue, the 'disable'
> -	 * method must claim the host when 'lazy' != 0, which will work
> -	 * correctly because recursion is detected and handled.
> +	 * 'enable' is called when the host is claimed and 'disable' is called
> +	 * when the host is released. 'enable' and 'disable' are deprecated.
>  	 */
>  	int (*enable)(struct mmc_host *host);
> -	int (*disable)(struct mmc_host *host, int lazy);
> +	int (*disable)(struct mmc_host *host);
>  	/*
>  	 * It is optional for the host to implement pre_req and post_req in
>  	 * order to support double buffering of requests (prepare one
> @@ -218,7 +195,7 @@ struct mmc_host {
>  #define MMC_CAP_SPI		(1 << 4)	/* Talks only SPI protocols */
>  #define MMC_CAP_NEEDS_POLL	(1 << 5)	/* Needs polling for card-detection */
>  #define MMC_CAP_8_BIT_DATA	(1 << 6)	/* Can the host do 8 bit transfers */
> -#define MMC_CAP_DISABLE		(1 << 7)	/* Can the host be disabled */
> +
>  #define MMC_CAP_NONREMOVABLE	(1 << 8)	/* Nonremovable e.g. eMMC */
>  #define MMC_CAP_WAIT_WHILE_BUSY	(1 << 9)	/* Waits while card is busy */
>  #define MMC_CAP_ERASE		(1 << 10)	/* Allow erase/trim commands */
> @@ -301,13 +278,7 @@ struct mmc_host {
>  	unsigned int		removed:1;	/* host is being removed */
>  #endif
>  
> -	/* Only used with MMC_CAP_DISABLE */
> -	int			enabled;	/* host is enabled */
>  	int			rescan_disable;	/* disable card detection */
> -	int			nesting_cnt;	/* "enable" nesting count */
> -	int			en_dis_recurs;	/* detect recursion */
> -	unsigned int		disable_delay;	/* disable delay in msecs */
> -	struct delayed_work	disable;	/* disabling work */
>  
>  	struct mmc_card		*card;		/* device attached to this host */
>  
> @@ -407,17 +378,8 @@ int mmc_card_awake(struct mmc_host *host);
>  int mmc_card_sleep(struct mmc_host *host);
>  int mmc_card_can_sleep(struct mmc_host *host);
>  
> -int mmc_host_enable(struct mmc_host *host);
> -int mmc_host_disable(struct mmc_host *host);
> -int mmc_host_lazy_disable(struct mmc_host *host);
>  int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *);
>  
> -static inline void mmc_set_disable_delay(struct mmc_host *host,
> -					 unsigned int disable_delay)
> -{
> -	host->disable_delay = disable_delay;
> -}
> -
>  /* Module parameter */
>  extern bool mmc_assume_removable;
>  




From hvaibhav at ti.com  Fri Mar  2 00:58:47 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 2 Mar 2012 05:58:47 +0000
Subject: [PATCH-V2 2/2] arm:omap:am33xx: Add power domain data
In-Reply-To: <alpine.DEB.2.00.1203011847480.22980@utopia.booyaka.com>
References: <1324803628-16790-1-git-send-email-hvaibhav@ti.com>
 <1324803628-16790-3-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1202291810230.12752@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A8317E5134@DBDE01.ent.ti.com>
 <alpine.DEB.2.00.1203011847480.22980@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A8317E66C1@DBDE01.ent.ti.com>

On Fri, Mar 02, 2012 at 11:19:40, Paul Walmsley wrote:
> Hi
> 
> On Thu, 1 Mar 2012, Hiremath, Vaibhav wrote:
> 
> > I am not sure whether we access these bits explicitly. If I understand 
> > correctly, API's which access these bits are not being called from 
> > anywhere, For example,
> > 
> > 	omap4_pwrdm_read_mem_retst
> > 	omap4_pwrdm_set_mem_retst
> > 	omap4_pwrdm_set_mem_onst
> 
> They'll be needed for the functional powerstate code, device PM QoS, and 
> OSWR.
> 
> > Currently the major issue would be, for PM_PER_PWRSTCTRL, where 
> > LogicRETState bit has been moved to offset 3. This is being used in 
> > omap4_pwrdm_set_logic_retst() api.
> > 
> > And in order to support weird/non-standard bit-offsets, we have to clean 
> > omap2_pwrdm_get_mem_bank_onstate/retst/_mask() api and have bitshift 
> > field in struct powerdomain, as you have rightly pointed out.
> 
> As you work on this, I have a request.  Please place the AM33xx 
> powerdomain implementation functions into a separate file, 
> powerdomain33xx.c perhaps, rather than trying to merge them with the OMAP4 
> powerdomain implementation functions.
> 

That was my initial code and I had submitted same to the list as an RFC, 
Request you to refer to the link - 
http://www.mail-archive.com/linux-omap at vger.kernel.org/msg58746.html


And the reason behind merging am33xx with omap4 thing was triggered
from the discussion on the above patch (between me, KevinH and RajendraNaik), 
and we all believed that, with some cleanup in OMAP4 code we can reuse it 
for am33xx.

Thanks,
Vaibhav

> Some functions can be shared -- maybe place those into a separate file, 
> powerdomain33xx_44xx.c perhaps?
> 
> > Is my all understanding correct?
> > 
> > If yes, do you think this patch should get blocked for above cleanup? I feel
> > Cleanup can still follow, since this won't impact the AM33xx boot.
> > 
> > What's your opinion on this??
> 
> We can't merge patches which are known to be broken.  That's a rule from 
> Linus (and a good one).  Better to try to get it right the first time it 
> hits mainline.
> 
> 
> - Paul
> 



From rnayak at ti.com  Fri Mar  2 01:02:52 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 02 Mar 2012 11:32:52 +0530
Subject: [PATCH 3/4] mmc: omap_hsmmc: Use GPIO offset for external GPIO
 chips
In-Reply-To: <20120301185532.29210.32421.stgit@kaulin.local>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185532.29210.32421.stgit@kaulin.local>
Message-ID: <4F50628C.9080706@ti.com>

On Friday 02 March 2012 12:25 AM, Tony Lindgren wrote:
> We can now remove the setting of GPIO pins with callbacks
> as the drivers can access a GPIO offset on a named gpio_chip
> directly with gpio_find_by_chip_name().
>
> Cc: Rajendra Nayak<rnayak at ti.com>
> Signed-off-by: Tony Lindgren<tony at atomide.com>
> ---
>   arch/arm/mach-omap2/board-3430sdp.c          |   13 ++++---------
>   arch/arm/mach-omap2/board-cm-t35.c           |    8 ++------
>   arch/arm/mach-omap2/board-devkit8000.c       |    7 ++-----
>   arch/arm/mach-omap2/board-igep0020.c         |    8 ++------
>   arch/arm/mach-omap2/board-omap3beagle.c      |    9 +++------
>   arch/arm/mach-omap2/board-omap3evm.c         |    8 ++------
>   arch/arm/mach-omap2/board-omap3pandora.c     |   13 ++++---------
>   arch/arm/mach-omap2/board-omap3stalker.c     |    8 ++------
>   arch/arm/mach-omap2/board-omap3touchbook.c   |    7 ++-----
>   arch/arm/mach-omap2/board-zoom-peripherals.c |    7 ++-----
>   10 files changed, 25 insertions(+), 63 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
> index da75f23..238b95a 100644
> --- a/arch/arm/mach-omap2/board-3430sdp.c
> +++ b/arch/arm/mach-omap2/board-3430sdp.c
> @@ -231,14 +231,16 @@ static struct omap2_hsmmc_info mmc[] = {
>   		 * so the SIM card isn't used; else 4 bits.
>   		 */
>   		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
> +		.gpiochip_cd	= "twl4030_gpio",
> +		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
>   		.gpio_wp	= 4,
> -		.deferred	= true,

Shouldn't this patch completely get rid of all the 'deferred'
infrastructure that was put in place, including the 
omap_hsmmc_late_init() function, since there is no need for it
anymore?

>   	},
[..]

>   	/*
>   	 * Most GPIOs are for USB OTG.  Some are mostly sent to
>   	 * the P2 connector; notably LEDA for the LCD backlight.
> diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
> index ace466b..b387264 100644
> --- a/arch/arm/mach-omap2/board-omap3pandora.c
> +++ b/arch/arm/mach-omap2/board-omap3pandora.c
> @@ -270,19 +270,19 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
>   	{
>   		.mmc		= 1,
>   		.caps		= MMC_CAP_4_BIT_DATA,
> -		.gpio_cd	= -EINVAL,
> +		.gpiochip_cd	= "twl4030_gpio",
> +		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
>   		.gpio_wp	= 126,
>   		.ext_clock	= 0,
> -		.deferred	= true,
>   	},
>   	{
>   		.mmc		= 2,
>   		.caps		= MMC_CAP_4_BIT_DATA,
> -		.gpio_cd	= -EINVAL,
> +		.gpiochip_cd	= "twl4030_gpio",
> +		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */

This one should be gpio_cd = 1,

regards,
Rajendra

>   		.gpio_wp	= 127,
>   		.ext_clock	= 1,
>   		.transceiver	= true,
> -		.deferred	= true,
>   	},
>   	{
>   		.mmc		= 3,
> @@ -299,11 +299,6 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
>   {
>   	int ret, gpio_32khz;
>
> -	/* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */
> -	omap3pandora_mmc[0].gpio_cd = gpio + 0;
> -	omap3pandora_mmc[1].gpio_cd = gpio + 1;
> -	omap_hsmmc_late_init(omap3pandora_mmc);
> -
>   	/* gpio + 13 drives 32kHz buffer for wifi module */
>   	gpio_32khz = gpio + 13;
>   	ret = gpio_request_one(gpio_32khz, GPIOF_OUT_INIT_HIGH, "wifi 32kHz");
> diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
> index 6410043..6d0deb9 100644
> --- a/arch/arm/mach-omap2/board-omap3stalker.c
> +++ b/arch/arm/mach-omap2/board-omap3stalker.c
> @@ -211,9 +211,9 @@ static struct omap2_hsmmc_info mmc[] = {
>   	{
>   		.mmc		= 1,
>   		.caps		= MMC_CAP_4_BIT_DATA,
> -		.gpio_cd	= -EINVAL,
> +		.gpiochip_cd	= "twl4030_gpio",
> +		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
>   		.gpio_wp	= 23,
> -		.deferred	= true,
>   	 },
>   	{}			/* Terminator */
>   };
> @@ -282,10 +282,6 @@ static int
>   omap3stalker_twl_gpio_setup(struct device *dev,
>   			    unsigned gpio, unsigned ngpio)
>   {
> -	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
> -	mmc[0].gpio_cd = gpio + 0;
> -	omap_hsmmc_late_init(mmc);
> -
>   	/*
>   	 * Most GPIOs are for USB OTG.  Some are mostly sent to
>   	 * the P2 connector; notably LEDA for the LCD backlight.
> diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
> index 8842e04..cf270b8 100644
> --- a/arch/arm/mach-omap2/board-omap3touchbook.c
> +++ b/arch/arm/mach-omap2/board-omap3touchbook.c
> @@ -99,8 +99,9 @@ static struct omap2_hsmmc_info mmc[] = {
>   	{
>   		.mmc		= 1,
>   		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
> +		.gpiochip_cd	= "twl4030_gpio",
> +		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
>   		.gpio_wp	= 29,
> -		.deferred	= true,
>   	},
>   	{}	/* Terminator */
>   };
> @@ -118,10 +119,6 @@ static struct gpio_led gpio_leds[];
>   static int touchbook_twl_gpio_setup(struct device *dev,
>   		unsigned gpio, unsigned ngpio)
>   {
> -	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
> -	mmc[0].gpio_cd = gpio + 0;
> -	omap_hsmmc_late_init(mmc);
> -
>   	/* REVISIT: need ehci-omap hooks for external VBUS
>   	 * power switch and overcurrent detect
>   	 */
> diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
> index 3d39cdb..604df86 100644
> --- a/arch/arm/mach-omap2/board-zoom-peripherals.c
> +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
> @@ -203,9 +203,10 @@ static struct omap2_hsmmc_info mmc[] = {
>   		.name		= "external",
>   		.mmc		= 1,
>   		.caps		= MMC_CAP_4_BIT_DATA,
> +		.gpiochip_cd	= "twl4030_gpio",
> +		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
>   		.gpio_wp	= -EINVAL,
>   		.power_saving	= true,
> -		.deferred	= true,
>   	},
>   	{
>   		.name		= "internal",
> @@ -232,10 +233,6 @@ static int zoom_twl_gpio_setup(struct device *dev,
>   {
>   	int ret;
>
> -	/* gpio + 0 is "mmc0_cd" (input/IRQ) */
> -	mmc[0].gpio_cd = gpio + 0;
> -	omap_hsmmc_late_init(mmc);
> -
>   	ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
>   			       "lcd enable");
>   	if (ret)
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From rnayak at ti.com  Fri Mar  2 01:10:03 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 02 Mar 2012 11:40:03 +0530
Subject: [PATCH 4/4] mmc: omap_hsmmc: Simplify init for twl6030 MMC card
 detect
In-Reply-To: <20120301185535.29210.71546.stgit@kaulin.local>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185535.29210.71546.stgit@kaulin.local>
Message-ID: <4F50643B.9050500@ti.com>

On Friday 02 March 2012 12:25 AM, Tony Lindgren wrote:
> There's no need to use callbacks for this, we can
> do it directly between MMC driver and twl6030.
>
> Cc: Samuel Ortiz<sameo at linux.intel.com>
> Cc: Chris Ball<cjb at laptop.org>
> Cc: Rajendra Nayak<rnayak at ti.com>
> Signed-off-by: Tony Lindgren<tony at atomide.com>
> ---
[..]
> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
> index 7ca7a5c..8cf4e54 100644
> --- a/arch/arm/mach-omap2/board-omap4panda.c
> +++ b/arch/arm/mach-omap2/board-omap4panda.c
> @@ -153,8 +153,8 @@ static struct omap2_hsmmc_info mmc[] = {
>   	{
>   		.mmc		= 1,
>   		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
> -		.gpio_wp	= -EINVAL,
>   		.gpio_cd	= -EINVAL,
> +		.gpio_wp	= -EINVAL,

stray change.

>   	},
[..]
> diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
> index c6b456a..ce0002b 100644
> --- a/drivers/mfd/twl6030-irq.c
> +++ b/drivers/mfd/twl6030-irq.c
> @@ -283,35 +283,30 @@ int twl6030_mmc_card_detect_config(void)
>   	 * Card status on TWL6030 for MMC1
>   	 */
>   	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0,&reg_val, TWL6030_MMCCTRL);
> -	if (ret<  0) {
> -		pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
> -		return ret;
> -	}
> +	if (ret<  0)
> +		goto err;
>   	reg_val&= ~VMMC_AUTO_OFF;
>   	reg_val |= SW_FC;
>   	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
> -	if (ret<  0) {
> -		pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
> -		return ret;
> -	}
> +	if (ret<  0)
> +		goto err;
>
>   	/* Configuring PullUp-PullDown register */
>   	ret = twl_i2c_read_u8(TWL6030_MODULE_ID0,&reg_val,
>   						TWL6030_CFG_INPUT_PUPD3);
> -	if (ret<  0) {
> -		pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
> -									ret);
> -		return ret;
> -	}
> +	if (ret<  0)
> +		goto err;
>   	reg_val&= ~(MMC_PU | MMC_PD);
>   	ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
>   						TWL6030_CFG_INPUT_PUPD3);
> -	if (ret<  0) {
> -		pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
> -									ret);
> -		return ret;
> -	}
> -	return 0;
> +	if (ret<  0)
> +		goto err;
> +
> +	return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
> +
> +err:
> +	pr_err("twl6030: Failed to initialize MMC card detect: %d\n", ret);
> +	return -ENODEV;
>   }
>   EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
>
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index 1aa2420..7f483b7 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -34,6 +34,7 @@
>   #include<linux/gpio.h>
>   #include<linux/regulator/consumer.h>
>   #include<linux/pm_runtime.h>
> +#include<linux/i2c/twl.h>
>   #include<plat/dma.h>
>   #include<mach/hardware.h>
>   #include<plat/board.h>
> @@ -578,6 +579,32 @@ static void omap_hsmmc_gpio_free(struct omap_hsmmc_host *host)
>   		gpio_free(host->gpio_cd);
>   }
>
> +#ifdef CONFIG_TWL4030_CORE
> +static int omap_hsmmc_init_twl6030(struct omap_hsmmc_host *host)
> +{
> +	struct omap_mmc_platform_data *pdata = host->pdata;
> +	struct omap_mmc_slot_data *slot =&pdata->slots[0];
> +	int irq;
> +
> +	if (gpio_is_valid(host->gpio_cd) || host->id)

I have a series, which I am asking Chris to pull, which completely
gets rid of all host->id based hard-codings' in the driver.
Isn't there a better way to do this than rely on the device instance?

regards,
Rajendra

> +		return 0;
> +
> +	irq = twl6030_mmc_card_detect_config();
> +	if (irq<= 0)
> +		return irq;
> +
> +	slot->card_detect_irq = irq;
> +	slot->card_detect = twl6030_mmc_card_detect;
> +
> +	return 0;
> +}
> +#else
> +static inline int omap_hsmmc_init_twl6030(struct omap_hsmmc_host *host)
> +{
> +	return -ENODEV;
> +}
> +#endif
> +
>   /*
>    * Start clock to the card
>    */
> @@ -1933,6 +1960,10 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>   	if (ret)
>   		goto err1;
>
> +	ret = omap_hsmmc_init_twl6030(host);
> +	if (ret)
> +		goto err1;
> +
>   	mmc->ops	=&omap_hsmmc_ops;
>
>   	/*
>



From paul at pwsan.com  Fri Mar  2 01:32:31 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 1 Mar 2012 23:32:31 -0700 (MST)
Subject: [PATCH-V2 2/2] arm:omap:am33xx: Add power domain data
In-Reply-To: <79CD15C6BA57404B839C016229A409A8317E515D@DBDE01.ent.ti.com>
References: <1324803628-16790-1-git-send-email-hvaibhav@ti.com>
 <1324803628-16790-3-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1202291839130.12752@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A8317E515D@DBDE01.ent.ti.com>
Message-ID: <alpine.DEB.2.00.1203012330490.22980@utopia.booyaka.com>

Hi,

On Thu, 1 Mar 2012, Hiremath, Vaibhav wrote:

> The initialization used in the patch is correct. Unfortunately, the TRM 
> is incorrect here. I have already raised this issue with respective 
> folks and soon it will get corrected.

thanks for looking into this.  Could you add a brief comment or comments 
in this file to indicate that the TRM Rev C is incorrect about those?  
That will help others who may be reviewing this code as they track down 
bugs.


thanks


- Paul


From hvaibhav at ti.com  Fri Mar  2 01:37:58 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 2 Mar 2012 06:37:58 +0000
Subject: [PATCH-V2 2/2] arm:omap:am33xx: Add power domain data
In-Reply-To: <alpine.DEB.2.00.1203012330490.22980@utopia.booyaka.com>
References: <1324803628-16790-1-git-send-email-hvaibhav@ti.com>
 <1324803628-16790-3-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1202291839130.12752@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A8317E515D@DBDE01.ent.ti.com>
 <alpine.DEB.2.00.1203012330490.22980@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A8317E6763@DBDE01.ent.ti.com>

On Fri, Mar 02, 2012 at 12:02:31, Paul Walmsley wrote:
> Hi,
> 
> On Thu, 1 Mar 2012, Hiremath, Vaibhav wrote:
> 
> > The initialization used in the patch is correct. Unfortunately, the TRM 
> > is incorrect here. I have already raised this issue with respective 
> > folks and soon it will get corrected.
> 
> thanks for looking into this.  Could you add a brief comment or comments 
> in this file to indicate that the TRM Rev C is incorrect about those?  
> That will help others who may be reviewing this code as they track down 
> bugs.
> 

Good point. I will certainly add it in the next version of patch-sets.

Paul,
Thanks for your review comments, can we also align on the approach, 
Whether to merge am33xx powerdomain with omap4 (same direction we are now)
OR
Have separate implementation (my original approach).


Thanks,
Vaibhav
> 
> thanks
> 
> 
> - Paul
> 



From thierry.reding at avionic-design.de  Fri Mar  2 01:59:20 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 2 Mar 2012 07:59:20 +0100
Subject: [PATCH v3 22/30] ARM: tegra: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-23-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-23-git-send-email-robherring2@gmail.com>
Message-ID: <20120302065920.GA441@avionic-0098.mockup.avionic-design.de>

* Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Colin Cross <ccross at android.com>
> Cc: Olof Johansson <olof at lixom.net>
> Acked-by: Stephen Warren <swarren at nvidia.com>
> ---
>  arch/arm/Kconfig                         |    1 -
>  arch/arm/mach-tegra/include/mach/io.h    |   46 ------------------------------
>  arch/arm/mach-tegra/include/mach/iomap.h |    3 ++
>  arch/arm/mach-tegra/io.c                 |    2 +
>  arch/arm/mach-tegra/pcie.c               |   41 ++------------------------
>  5 files changed, 9 insertions(+), 84 deletions(-)
>  delete mode 100644 arch/arm/mach-tegra/include/mach/io.h
[...]

This looks good to me. Moreover this gets rid of some of the ugly globals
initialized by the PCI support and should fit in nicely with the work I'm
doing to rewrite it as a driver and add device tree support.

Unfortunately I'm unable to test actual accesses because none of the PCI
devices that I use have I/O regions.

Thierry
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From paul.liu at linaro.org  Fri Mar  2 02:00:40 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Fri,  2 Mar 2012 15:00:40 +0800
Subject: [PATCH v6 1/2] mfd: Add anatop mfd driver
In-Reply-To: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
References: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
Message-ID: <1330671641-6439-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
Anatop provides regulators and thermal.
This driver handles the address space and the operation of the mfd device.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/mfd/Kconfig        |    6 ++
 drivers/mfd/Makefile       |    1 +
 drivers/mfd/anatop-mfd.c   |  142 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/anatop.h |   40 ++++++++++++
 4 files changed, 189 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mfd/anatop-mfd.c
 create mode 100644 include/linux/mfd/anatop.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index f147395..f787d17 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -830,6 +830,12 @@ config MFD_INTEL_MSIC
 	  Passage) chip. This chip embeds audio, battery, GPIO, etc.
 	  devices used in Intel Medfield platforms.
 
+config MFD_ANATOP
+        bool "Support for Anatop"
+	depends on SOC_IMX6Q
+	help
+	  Select this option to enable Anatop MFD driver.
+
 endmenu
 endif
 
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b953bab..8e11060 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -112,3 +112,4 @@ obj-$(CONFIG_TPS65911_COMPARATOR)	+= tps65911-comparator.o
 obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
 obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
 obj-$(CONFIG_MFD_S5M_CORE)	+= s5m-core.o s5m-irq.o
+obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
new file mode 100644
index 0000000..0307051
--- /dev/null
+++ b/drivers/mfd/anatop-mfd.c
@@ -0,0 +1,142 @@
+/*
+ * Anatop MFD driver
+ *
+ * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ * Copyright (C) 2012 Linaro
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+
+u32 anatop_get_bits(struct anatop *adata, u32 addr, int bit_shift, int bits)
+{
+	u32 val;
+	int mask;
+
+	if (bits == 32)
+		mask = ~0;
+	else
+		mask = (1 << bits) - 1;
+
+	val = readl(adata->ioreg + addr);
+	val = (val >> bit_shift) & mask;
+
+	return val;
+}
+EXPORT_SYMBOL(anatop_get_bits);
+
+void anatop_set_bits(struct anatop *adata, u32 addr, int bit_shift,
+		     int bits, u32 data)
+{
+	u32 val;
+	int mask;
+	if (bits == 32)
+		mask = ~0;
+	else
+		mask = (1 << bits) - 1;
+
+	spin_lock(&adata->reglock);
+	val = readl(adata->ioreg + addr) & ~(mask << bit_shift);
+	writel((data << bit_shift) | val, adata->ioreg);
+	spin_unlock(&adata->reglock);
+}
+EXPORT_SYMBOL(anatop_set_bits);
+
+static const struct of_device_id of_anatop_subdevice_match[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ .compatible = "fsl,anatop-thermal", },
+	{ },
+};
+
+static int of_anatop_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	void *ioreg;
+	struct anatop *drvdata;
+
+	ioreg = of_iomap(np, 0);
+	if (!ioreg)
+		return -EINVAL;
+	drvdata = devm_kzalloc(dev, sizeof(struct anatop), GFP_KERNEL);
+	if (!drvdata)
+		return -EINVAL;
+	drvdata->ioreg = ioreg;
+	spin_lock_init(&drvdata->reglock);
+	platform_set_drvdata(pdev, drvdata);
+	of_platform_bus_probe(np, of_anatop_subdevice_match, dev);
+
+	return 0;
+}
+
+static int of_anatop_remove(struct platform_device *pdev)
+{
+	struct anatop *drvdata;
+	drvdata = platform_get_drvdata(pdev);
+	iounmap(drvdata->ioreg);
+	return 0;
+}
+
+static const struct of_device_id of_anatop_match[] = {
+	{ .compatible = "fsl,imx6q-anatop", },
+	{ },
+};
+
+static struct platform_driver anatop_of_driver = {
+	.driver = {
+		.name = "anatop-mfd",
+		.owner = THIS_MODULE,
+		.of_match_table = of_anatop_match,
+	},
+	.probe		= of_anatop_probe,
+	.remove		= of_anatop_remove,
+};
+
+static int __init anatop_init(void)
+{
+	return platform_driver_register(&anatop_of_driver);
+}
+postcore_initcall(anatop_init);
+
+static void __exit anatop_exit(void)
+{
+	platform_driver_unregister(&anatop_of_driver);
+}
+module_exit(anatop_exit);
+
+MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP MFD driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
new file mode 100644
index 0000000..22c1007
--- /dev/null
+++ b/include/linux/mfd/anatop.h
@@ -0,0 +1,40 @@
+/*
+ * anatop.h - Anatop MFD driver
+ *
+ *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ *  Copyright (C) 2012 Linaro
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_MFD_ANATOP_H
+#define __LINUX_MFD_ANATOP_H
+
+#include <linux/spinlock.h>
+
+/**
+ * anatop - MFD data
+ * @ioreg: ioremap register
+ * @reglock: spinlock for register read/write
+ */
+struct anatop {
+	void *ioreg;
+	spinlock_t reglock;
+};
+
+extern u32 anatop_get_bits(struct anatop *, u32, int, int);
+extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
+
+#endif /*  __LINUX_MFD_ANATOP_H */
-- 
1.7.9.1



From paul.liu at linaro.org  Fri Mar  2 02:00:41 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Fri,  2 Mar 2012 15:00:41 +0800
Subject: [PATCH v6 2/2] Regulator: Add Anatop regulator driver
In-Reply-To: <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
References: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
 <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
Message-ID: <1330671641-6439-2-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.

Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Liam Girdwood <lrg at ti.com>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 .../bindings/regulator/anatop-regulator.txt        |   28 +++
 drivers/regulator/Kconfig                          |    6 +
 drivers/regulator/Makefile                         |    1 +
 drivers/regulator/anatop-regulator.c               |  205 ++++++++++++++++++++
 include/linux/regulator/anatop-regulator.h         |   40 ++++
 5 files changed, 280 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.txt
 create mode 100644 drivers/regulator/anatop-regulator.c
 create mode 100644 include/linux/regulator/anatop-regulator.h

diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
new file mode 100644
index 0000000..f19cfea
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -0,0 +1,28 @@
+Anatop Voltage regulators
+
+Required properties:
+- compatible: Must be "fsl,anatop-regulator"
+- vol-bit-shift: Bit shift for the register
+- vol-bit-size: Number of bits used in the register
+- min-bit-val: Minimum value of this register
+- min-voltage: Minimum voltage of this regulator
+- max-voltage: Maximum voltage of this regulator
+
+Any property defined as part of the core regulator
+binding, defined in regulator.txt, can also be used.
+
+Example:
+
+	reg_vddpu: regulator-vddpu at 140 {
+		compatible = "fsl,anatop-regulator";
+		regulator-name = "vddpu";
+		regulator-min-microvolt = <725000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-always-on;
+		reg = <0x140 1>;
+		vol-bit-shift = <9>;
+		vol-bit-size = <5>;
+		min-bit-val = <1>;
+		min-voltage = <725000>;
+		max-voltage = <1300000>;
+	};
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 7a61b17..5fbcda2 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -335,5 +335,11 @@ config REGULATOR_AAT2870
 	  If you have a AnalogicTech AAT2870 say Y to enable the
 	  regulator driver.
 
+config REGULATOR_ANATOP
+	tristate "ANATOP LDO regulators"
+	depends on MFD_ANATOP
+	help
+	  Say y here to support ANATOP LDOs regulators.
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 503bac8..8440871 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -48,5 +48,6 @@ obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
 obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
 obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
 obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
+obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
new file mode 100644
index 0000000..84d8f50
--- /dev/null
+++ b/drivers/regulator/anatop-regulator.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/anatop-regulator.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regulator/of_regulator.h>
+
+static int anatop_set_voltage(struct regulator_dev *reg, int min_uV,
+				  int max_uV, unsigned *selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	u32 val, sel;
+	int uv;
+
+	uv = min_uV;
+	dev_dbg(&reg->dev, "%s: uv %d, min %d, max %d\n", __func__,
+		uv, anatop_reg->min_voltage,
+		anatop_reg->max_voltage);
+
+	if (uv < anatop_reg->min_voltage) {
+		if (max_uV > anatop_reg->min_voltage)
+			uv = anatop_reg->min_voltage;
+		else
+			return -EINVAL;
+	}
+
+	if (anatop_reg->control_reg) {
+		sel = (uv - anatop_reg->min_voltage) / 25000;
+		if (sel * 25000 + anatop_reg->min_voltage
+		    > anatop_reg->max_voltage)
+			return -EINVAL;
+		val = anatop_reg->min_bit_val + sel;
+		*selector = sel;
+		dev_dbg(&reg->dev, "%s: calculated val %d\n", __func__, val);
+		anatop_set_bits(anatop_reg->mfd,
+				anatop_reg->control_reg,
+				anatop_reg->vol_bit_shift,
+				anatop_reg->vol_bit_size,
+				val);
+		return 0;
+	} else {
+		return -ENOTSUPP;
+	}
+}
+
+static int anatop_get_voltage_sel(struct regulator_dev *reg)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int selector;
+
+	if (anatop_reg->control_reg) {
+		u32 val = anatop_get_bits(anatop_reg->mfd,
+					  anatop_reg->control_reg,
+					  anatop_reg->vol_bit_shift,
+					  anatop_reg->vol_bit_size);
+		selector = val - anatop_reg->min_bit_val;
+		return selector;
+	} else {
+		return -ENOTSUPP;
+	}
+}
+
+static int anatop_list_voltage(struct regulator_dev *reg, unsigned selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int uv;
+
+	uv = anatop_reg->min_voltage + selector * 25000;
+	dev_dbg(&reg->dev, "vddio = %d, selector = %u\n", uv, selector);
+
+	return uv;
+}
+
+static struct regulator_ops anatop_rops = {
+	.set_voltage     = anatop_set_voltage,
+	.get_voltage_sel = anatop_get_voltage_sel,
+	.list_voltage    = anatop_list_voltage,
+};
+
+int anatop_regulator_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct regulator_desc *rdesc;
+	struct regulator_dev *rdev;
+	struct anatop_regulator *sreg;
+	struct regulator_init_data *initdata;
+	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
+	const __be32 *rval;
+	u64 ofsize;
+
+	initdata = of_get_regulator_init_data(dev, dev->of_node);
+	sreg = devm_kzalloc(dev, sizeof(struct anatop_regulator), GFP_KERNEL);
+	if (!sreg)
+		return -EINVAL;
+	rdesc = devm_kzalloc(dev, sizeof(struct regulator_desc), GFP_KERNEL);
+	if (!rdesc)
+		return -EINVAL;
+	sreg->initdata = initdata;
+	sreg->name = kstrdup(of_get_property(np, "regulator-name", NULL),
+			     GFP_KERNEL);
+	sreg->regulator = rdesc;
+	memset(rdesc, 0, sizeof(struct regulator_desc));
+	rdesc->name = sreg->name;
+	rdesc->ops = &anatop_rops;
+	rdesc->type = REGULATOR_VOLTAGE;
+	rdesc->owner = THIS_MODULE;
+	sreg->mfd = anatopmfd;
+	rval = of_get_address(np, 0, &ofsize, NULL);
+	if (rval)
+		sreg->control_reg = be32_to_cpu(*rval);
+	rval = of_get_property(np, "vol-bit-size", NULL);
+	if (rval)
+		sreg->vol_bit_size = be32_to_cpu(*rval);
+	rval = of_get_property(np, "vol-bit-shift", NULL);
+	if (rval)
+		sreg->vol_bit_shift = be32_to_cpu(*rval);
+	rval = of_get_property(np, "min-bit-val", NULL);
+	if (rval)
+		sreg->min_bit_val = be32_to_cpu(*rval);
+	rval = of_get_property(np, "min-voltage", NULL);
+	if (rval)
+		sreg->min_voltage = be32_to_cpu(*rval);
+	rval = of_get_property(np, "max-voltage", NULL);
+	if (rval)
+		sreg->max_voltage = be32_to_cpu(*rval);
+
+	/* register regulator */
+	rdev = regulator_register(rdesc, &pdev->dev,
+				  initdata, sreg, pdev->dev.of_node);
+	platform_set_drvdata(pdev, rdev);
+
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			rdesc->name);
+		kfree(sreg->name);
+		return PTR_ERR(rdev);
+	}
+
+	return 0;
+}
+
+int anatop_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
+	kfree(sreg->name);
+	regulator_unregister(rdev);
+	return 0;
+}
+
+struct of_device_id __devinitdata of_anatop_regulator_match_tbl[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ /* end */ }
+};
+
+struct platform_driver anatop_regulator = {
+	.driver = {
+		.name	= "anatop_regulator",
+		.owner  = THIS_MODULE,
+		.of_match_table = of_anatop_regulator_match_tbl,
+	},
+	.probe	= anatop_regulator_probe,
+	.remove	= anatop_regulator_remove,
+};
+
+int anatop_regulator_init(void)
+{
+	return platform_driver_register(&anatop_regulator);
+}
+postcore_initcall(anatop_regulator_init);
+
+void anatop_regulator_exit(void)
+{
+	platform_driver_unregister(&anatop_regulator);
+}
+module_exit(anatop_regulator_exit);
+
+MODULE_DESCRIPTION("ANATOP Regulator driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/regulator/anatop-regulator.h b/include/linux/regulator/anatop-regulator.h
new file mode 100644
index 0000000..7a9a05b
--- /dev/null
+++ b/include/linux/regulator/anatop-regulator.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ANATOP_REGULATOR_H
+#define __ANATOP_REGULATOR_H
+
+#include <linux/regulator/driver.h>
+#include <linux/mfd/anatop.h>
+
+struct anatop_regulator {
+	struct regulator_desc *regulator;
+	struct regulator_init_data *initdata;
+	const char *name;
+	u32 control_reg;
+	struct anatop *mfd;
+	int vol_bit_shift;
+	int vol_bit_size;
+	int min_bit_val;
+	int min_voltage;
+	int max_voltage;
+};
+
+#endif /* __ANATOP_REGULATOR_H */
-- 
1.7.9.1



From tsoni at codeaurora.org  Fri Mar  2 02:02:56 2012
From: tsoni at codeaurora.org (Trilok Soni)
Date: Fri, 02 Mar 2012 12:32:56 +0530
Subject: [PATCH v3 1/1] rc: Add support for GPIO based IR Receiver driver.
In-Reply-To: <4F4E1911.5050208@codeaurora.org>
References: <1330408300-21939-1-git-send-email-kumarrav@codeaurora.org>
 <20120228202944.GA9373@balrog> <4F4E1911.5050208@codeaurora.org>
Message-ID: <4F5070A0.9070609@codeaurora.org>

Hi Mauro/Wilson,

On 2/29/2012 5:54 PM, Trilok Soni wrote:
> Hi Mauro/Wilson,
>
> On 2/29/2012 1:59 AM, James Hogan wrote:
>> On Tue, Feb 28, 2012 at 11:21:40AM +0530, Ravi Kumar V wrote:
>>> Adds GPIO based IR Receiver driver. It decodes signals using decoders
>>> available in rc framework.
>>>
>>> Signed-off-by: Ravi Kumar V<kumarrav at codeaurora.org>
>>
>> Looks good to me (but I'm no expert).
>>
>
> Please review this patch.
>
> Thank you James for the review comments.

Please review and check if this patch can be merged in your tree.

---Trilok Soni

--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From vbyravarasu at nvidia.com  Fri Mar  2 02:07:48 2012
From: vbyravarasu at nvidia.com (Venu Byravarasu)
Date: Fri, 2 Mar 2012 12:37:48 +0530
Subject: [PATCH v6 1/2] mfd: Add anatop mfd driver
In-Reply-To: <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
References: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
 <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
Message-ID: <D958900912E20642BCBC71664EFECE3E6DD2912252@BGMAIL02.nvidia.com>

Why you did not made use of regmap?

> -----Original Message-----
> From: linux-kernel-owner at vger.kernel.org [mailto:linux-kernel-
> owner at vger.kernel.org] On Behalf Of Ying-Chun Liu (PaulLiu)
> Sent: Friday, March 02, 2012 12:31 PM
> To: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org; linaro-dev at lists.linaro.org;
> patches at linaro.org; Ying-Chun Liu (PaulLiu); Samuel Ortiz; Mark Brown; Shawn
> Guo
> Subject: [PATCH v6 1/2] mfd: Add anatop mfd driver
> 
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
> Anatop provides regulators and thermal.
> This driver handles the address space and the operation of the mfd device.
> 
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> ---
>  drivers/mfd/Kconfig        |    6 ++
>  drivers/mfd/Makefile       |    1 +
>  drivers/mfd/anatop-mfd.c   |  142
> ++++++++++++++++++++++++++++++++++++++++++++
>  include/linux/mfd/anatop.h |   40 ++++++++++++
>  4 files changed, 189 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/mfd/anatop-mfd.c
>  create mode 100644 include/linux/mfd/anatop.h
> 
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index f147395..f787d17 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -830,6 +830,12 @@ config MFD_INTEL_MSIC
>  	  Passage) chip. This chip embeds audio, battery, GPIO, etc.
>  	  devices used in Intel Medfield platforms.
> 
> +config MFD_ANATOP
> +        bool "Support for Anatop"
> +	depends on SOC_IMX6Q
> +	help
> +	  Select this option to enable Anatop MFD driver.
> +
>  endmenu
>  endif
> 
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index b953bab..8e11060 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -112,3 +112,4 @@ obj-$(CONFIG_TPS65911_COMPARATOR)	+=
> tps65911-comparator.o
>  obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
>  obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
>  obj-$(CONFIG_MFD_S5M_CORE)	+= s5m-core.o s5m-irq.o
> +obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
> diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
> new file mode 100644
> index 0000000..0307051
> --- /dev/null
> +++ b/drivers/mfd/anatop-mfd.c
> @@ -0,0 +1,142 @@
> +/*
> + * Anatop MFD driver
> + *
> + * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> + * Copyright (C) 2012 Linaro
> + *
> + *  This program is free software; you can redistribute it and/or modify
> + *  it under the terms of the GNU General Public License as published by
> + *  the Free Software Foundation; either version 2 of the License, or
> + *   (at your option) any later version.
> + *
> + *  This program is distributed in the hope that it will be useful,
> + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *  GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License along
> + *  with this program; if not, write to the Free Software Foundation, Inc.,
> + *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + *  This program is free software; you can redistribute it and/or modify
> + *  it under the terms of the GNU General Public License as published by
> + *  the Free Software Foundation; either version 2 of the License, or
> + *  (at your option) any later version.
> + *
> + *  This program is distributed in the hope that it will be useful,
> + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *  GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License along
> + *  with this program; if not, write to the Free Software Foundation, Inc.,
> + *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + *
> + */
> +
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/mfd/anatop.h>
> +
> +u32 anatop_get_bits(struct anatop *adata, u32 addr, int bit_shift, int bits)
> +{
> +	u32 val;
> +	int mask;
> +
> +	if (bits == 32)
> +		mask = ~0;
> +	else
> +		mask = (1 << bits) - 1;
> +
> +	val = readl(adata->ioreg + addr);
> +	val = (val >> bit_shift) & mask;
> +
> +	return val;
> +}
> +EXPORT_SYMBOL(anatop_get_bits);
> +
> +void anatop_set_bits(struct anatop *adata, u32 addr, int bit_shift,
> +		     int bits, u32 data)
> +{
> +	u32 val;
> +	int mask;
> +	if (bits == 32)
> +		mask = ~0;
> +	else
> +		mask = (1 << bits) - 1;
> +
> +	spin_lock(&adata->reglock);
> +	val = readl(adata->ioreg + addr) & ~(mask << bit_shift);
> +	writel((data << bit_shift) | val, adata->ioreg);
> +	spin_unlock(&adata->reglock);
> +}
> +EXPORT_SYMBOL(anatop_set_bits);
> +
> +static const struct of_device_id of_anatop_subdevice_match[] = {
> +	{ .compatible = "fsl,anatop-regulator", },
> +	{ .compatible = "fsl,anatop-thermal", },
> +	{ },
> +};
> +
> +static int of_anatop_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	void *ioreg;
> +	struct anatop *drvdata;
> +
> +	ioreg = of_iomap(np, 0);
> +	if (!ioreg)
> +		return -EINVAL;
> +	drvdata = devm_kzalloc(dev, sizeof(struct anatop), GFP_KERNEL);
> +	if (!drvdata)
> +		return -EINVAL;
> +	drvdata->ioreg = ioreg;
> +	spin_lock_init(&drvdata->reglock);
> +	platform_set_drvdata(pdev, drvdata);
> +	of_platform_bus_probe(np, of_anatop_subdevice_match, dev);
> +
> +	return 0;
> +}
> +
> +static int of_anatop_remove(struct platform_device *pdev)
> +{
> +	struct anatop *drvdata;
> +	drvdata = platform_get_drvdata(pdev);
> +	iounmap(drvdata->ioreg);
> +	return 0;
> +}
> +
> +static const struct of_device_id of_anatop_match[] = {
> +	{ .compatible = "fsl,imx6q-anatop", },
> +	{ },
> +};
> +
> +static struct platform_driver anatop_of_driver = {
> +	.driver = {
> +		.name = "anatop-mfd",
> +		.owner = THIS_MODULE,
> +		.of_match_table = of_anatop_match,
> +	},
> +	.probe		= of_anatop_probe,
> +	.remove		= of_anatop_remove,
> +};
> +
> +static int __init anatop_init(void)
> +{
> +	return platform_driver_register(&anatop_of_driver);
> +}
> +postcore_initcall(anatop_init);
> +
> +static void __exit anatop_exit(void)
> +{
> +	platform_driver_unregister(&anatop_of_driver);
> +}
> +module_exit(anatop_exit);
> +
> +MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
> +MODULE_DESCRIPTION("ANATOP MFD driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
> new file mode 100644
> index 0000000..22c1007
> --- /dev/null
> +++ b/include/linux/mfd/anatop.h
> @@ -0,0 +1,40 @@
> +/*
> + * anatop.h - Anatop MFD driver
> + *
> + *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> + *  Copyright (C) 2012 Linaro
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +
> +#ifndef __LINUX_MFD_ANATOP_H
> +#define __LINUX_MFD_ANATOP_H
> +
> +#include <linux/spinlock.h>
> +
> +/**
> + * anatop - MFD data
> + * @ioreg: ioremap register
> + * @reglock: spinlock for register read/write
> + */
> +struct anatop {
> +	void *ioreg;
> +	spinlock_t reglock;
> +};
> +
> +extern u32 anatop_get_bits(struct anatop *, u32, int, int);
> +extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
> +
> +#endif /*  __LINUX_MFD_ANATOP_H */
> --
> 1.7.9.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/


From svenkatr at ti.com  Fri Mar  2 02:11:45 2012
From: svenkatr at ti.com (S, Venkatraman)
Date: Fri, 2 Mar 2012 12:41:45 +0530
Subject: [PATCH] ARM: OMAP: hsmmc: add max_freq field
In-Reply-To: <20120302001121.GE18901@atomide.com>
References: <1323868927-3738-1-git-send-email-zonque@gmail.com>
 <CANrkHUY3Zf4a2K5769Z=7Wng339zB6+z_Tgd4mOPChZ1RvZ=Kw@mail.gmail.com>
 <4EFC6992.4020501@gmail.com>
 <CACTFLAMCoKfQbTe2RLTvi1_CH0nKzAOthAwrifNe2+F2sf3uPA@mail.gmail.com>
 <20120302001121.GE18901@atomide.com>
Message-ID: <CANfBPZ8Oypwqq2p3rcNpp5M8+XPHDmUxMRw2J5Jw5DdAKQj8cw@mail.gmail.com>

+Chris queues all MMC patches including omap_hsmmc.
Ping ?


On Fri, Mar 2, 2012 at 5:41 AM, Tony Lindgren <tony at atomide.com> wrote:
> Hi,
>
> * Daniel Mack <zonque at gmail.com> [120217 05:13]:
>> ping? Could anyone care for queueing this please?
>
> I suggest Rajendra queue up omap_hsmmc.c patches as he's already
> patching it.
>
> Regards,
>
> Tony
>
>
>> On Thu, Dec 29, 2011 at 2:22 PM, Daniel Mack <zonque at gmail.com> wrote:
>> > On 12/23/2011 04:40 PM, T Krishnamoorthy, Balaji wrote:
>> >> On Wed, Dec 14, 2011 at 6:52 PM, Daniel Mack <zonque at gmail.com> wrote:
>> >>> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
>> >>> index 101cd31..8215ef9 100644
>> >>> --- a/drivers/mmc/host/omap_hsmmc.c
>> >>> +++ b/drivers/mmc/host/omap_hsmmc.c
>> >>> @@ -1927,8 +1927,12 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>> >>> ? ? ? ?if (mmc_slot(host).vcc_aux_disable_is_sleep)
>> >>> ? ? ? ? ? ? ? ?mmc_slot(host).no_off = 1;
>> >>>
>> >>> - ? ? ? mmc->f_min ? ? ?= OMAP_MMC_MIN_CLOCK;
>> >>> - ? ? ? mmc->f_max ? ? ?= OMAP_MMC_MAX_CLOCK;
>> >>> + ? ? ? mmc->f_min = OMAP_MMC_MIN_CLOCK;
>> >>
>> >> Stray change for f_min ?
>> >
>> > No, this was intended. The indentation doesn't make sense anymore when
>> > not grouped with the f_max assignment.
>> >
>> > Other than that, what is necessary to get this picked? Tony? :)
>> >
>> >
>> > Thanks,
>> > Daniel
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html


From rnayak at ti.com  Fri Mar  2 02:25:34 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 02 Mar 2012 12:55:34 +0530
Subject: [PATCH 2/4] mmc: omap_hsmmc: Use gpio_find_by_chip_name() for
 omap_hsmmc_gpio_init()
In-Reply-To: <20120301185528.29210.85854.stgit@kaulin.local>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185528.29210.85854.stgit@kaulin.local>
Message-ID: <4F5075EE.1050902@ti.com>

On Friday 02 March 2012 12:25 AM, Tony Lindgren wrote:
> Use gpio_find_by_chip_name() to find the GPIO pins as they can
> be dynamically allocated on various gpio_chips.
>
> Note that we don't want to touch the platform data as it can
> now specify the GPIO offset on a named gpio_chip.
>
> This removes the need to use callbacks to set the GPIO pins
> in platform data.
>
> Cc: Chris Ball<cjb at laptop.org>
> Cc: Grant Likely<grant.likely at secretlab.ca>
> Cc: Rajendra Nayak<rnayak at ti.com>
> Signed-off-by: Tony Lindgren<tony at atomide.com>
> ---

some more comments based on my testing with twl4030-gpio
built as a module..

>   arch/arm/mach-omap2/hsmmc.c           |    3 +
>   arch/arm/mach-omap2/hsmmc.h           |    5 ++
>   arch/arm/plat-omap/include/plat/mmc.h |    3 +
>   drivers/gpio/gpio-twl4030.c           |    2 +
>   drivers/mmc/host/omap_hsmmc.c         |  109 +++++++++++++++++++++------------
>   5 files changed, 82 insertions(+), 40 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
> index a97876d..dda88f7 100644
> --- a/arch/arm/mach-omap2/hsmmc.c
> +++ b/arch/arm/mach-omap2/hsmmc.c
> @@ -323,7 +323,10 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,

> @@ -497,55 +502,80 @@ static inline int omap_hsmmc_have_reg(void)
>
>   #endif
>
> -static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
> +static int omap_hsmmc_gpio_init(struct omap_hsmmc_host *host)
>   {
> -	int ret;
> -
> -	if (gpio_is_valid(pdata->slots[0].switch_pin)) {
> -		if (pdata->slots[0].cover)
> -			pdata->slots[0].get_cover_state =
> +	struct omap_mmc_platform_data *pdata = host->pdata;
> +	struct omap_mmc_slot_data *slot =&pdata->slots[0];
> +	int gpio, ret;
> +
> +	gpio = slot->switch_pin;
> +	if (slot->gpiochip_cd)
> +		gpio = gpio_find_by_chip_name(slot->gpiochip_cd, gpio);
> +	if (gpio_is_valid(gpio)) {
> +		if (slot->cover)
> +			slot->get_cover_state =
>   					omap_hsmmc_get_cover_state;
>   		else
> -			pdata->slots[0].card_detect = omap_hsmmc_card_detect;
> -		pdata->slots[0].card_detect_irq =
> -				gpio_to_irq(pdata->slots[0].switch_pin);
> -		ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
> +			slot->card_detect = omap_hsmmc_card_detect;
> +		slot->card_detect_irq =
> +				gpio_to_irq(gpio);
> +		ret = gpio_request(gpio, "mmc_cd");
>   		if (ret)
>   			return ret;
> -		ret = gpio_direction_input(pdata->slots[0].switch_pin);
> +		ret = gpio_direction_input(gpio);
>   		if (ret)
>   			goto err_free_sp;
> -	} else
> -		pdata->slots[0].switch_pin = -EINVAL;
> +		host->gpio_cd = gpio;
> +	} else {
> +		if (slot->gpiochip_cd) {
> +			pr_warning("MMC %s card detect GPIO chip %s unavailable\n",
> +				slot->name, slot->gpiochip_cd);
> +			ret = -ENODEV;
> +			goto err_free_sp;

This should just return -ENODEV, nothing really to free here.

> +		}
> +		host->gpio_cd = -EINVAL;
> +	}
>
> -	if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
> -		pdata->slots[0].get_ro = omap_hsmmc_get_wp;
> -		ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
> +	gpio = slot->gpio_wp;
> +	if (slot->gpiochip_wp)
> +		gpio = gpio_find_by_chip_name(slot->gpiochip_wp, gpio);
> +	if (gpio_is_valid(gpio)) {
> +		slot->get_ro = omap_hsmmc_get_wp;
> +		ret = gpio_request(gpio, "mmc_wp");
>   		if (ret)
>   			goto err_free_cd;
> -		ret = gpio_direction_input(pdata->slots[0].gpio_wp);
> +		ret = gpio_direction_input(gpio);
>   		if (ret)
>   			goto err_free_wp;
> -	} else
> -		pdata->slots[0].gpio_wp = -EINVAL;
> +		host->gpio_wp = gpio;
> +	} else {
> +		if (slot->gpiochip_wp) {
> +			pr_warning("MMC %s write protect GPIO chip %s unavailable\n",
> +				slot->name, slot->gpiochip_wp);
> +			ret = -ENODEV;
> +			goto err_free_wp;
> +		}
> +		host->gpio_wp = -EINVAL;
> +	}
>
>   	return 0;
>
>   err_free_wp:
> -	gpio_free(pdata->slots[0].gpio_wp);
> +	if (gpio_is_valid(host->gpio_wp))
> +		gpio_free(host->gpio_wp);
>   err_free_cd:
> -	if (gpio_is_valid(pdata->slots[0].switch_pin))
> +	if (gpio_is_valid(host->gpio_cd))
>   err_free_sp:
> -		gpio_free(pdata->slots[0].switch_pin);
> +		gpio_free(host->gpio_cd);
>   	return ret;
>   }
>
> -static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
> +static void omap_hsmmc_gpio_free(struct omap_hsmmc_host *host)
>   {
> -	if (gpio_is_valid(pdata->slots[0].gpio_wp))
> -		gpio_free(pdata->slots[0].gpio_wp);
> -	if (gpio_is_valid(pdata->slots[0].switch_pin))
> -		gpio_free(pdata->slots[0].switch_pin);
> +	if (gpio_is_valid(host->gpio_wp))
> +		gpio_free(host->gpio_wp);
> +	if (gpio_is_valid(host->gpio_cd))
> +		gpio_free(host->gpio_cd);
>   }
>
>   /*
> @@ -1876,10 +1906,6 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>   	if (res == NULL)
>   		return -EBUSY;
>
> -	ret = omap_hsmmc_gpio_init(pdata);
> -	if (ret)
> -		goto err;
> -
>   	mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host),&pdev->dev);
>   	if (!mmc) {
>   		ret = -ENOMEM;
> @@ -1903,6 +1929,10 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>
>   	platform_set_drvdata(pdev, host);
>
> +	ret = omap_hsmmc_gpio_init(host);
> +	if (ret)
> +		goto err1;
> +
>   	mmc->ops	=&omap_hsmmc_ops;
>
>   	/*
> @@ -2093,8 +2123,7 @@ err1:
>   	platform_set_drvdata(pdev, NULL);
>   	mmc_free_host(mmc);
>   err_alloc:
> -	omap_hsmmc_gpio_free(pdata);
> -err:
> +	omap_hsmmc_gpio_free(host);

This error handling needs to be fixed up. In case
omap_hsmmc_gpio_init() fails, which already frees up
any requested gpios, omap_hsmmc_gpio_free() again tries
freeing gpios.

regards,
Rajendra

>   	release_mem_region(res->start, resource_size(res));
>   	return ret;
>   }
> @@ -2125,7 +2154,7 @@ static int omap_hsmmc_remove(struct platform_device *pdev)
>
>   		mmc_free_host(host->mmc);
>   		iounmap(host->base);
> -		omap_hsmmc_gpio_free(pdev->dev.platform_data);
> +		omap_hsmmc_gpio_free(host);
>   	}
>
>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>



From s.hauer at pengutronix.de  Fri Mar  2 02:26:17 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2012 08:26:17 +0100
Subject: [PATCH 0/4] i.MX27: visstrim_m10: Add several peripherals.
In-Reply-To: <1330446711-6970-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330446711-6970-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120302072617.GA19905@pengutronix.de>

On Tue, Feb 28, 2012 at 05:31:47PM +0100, Javier Martin wrote:
> I've splitted video related patch into three to attend Uwe's requirements
> and have added RTC support too.
> 
> [PATCH v2 1/4] i.MX27: visstrim_m10: Sort IMX_HAVE_PLATFORM_MXC_MMC properly.
> [PATCH v2 2/4] i.MX27: visstrim_m10: Register I2C devices after I2C busses have been added.
> [PATCH v2 3/4] i.MX27: visstrim_m10: Add m41t00 RTC support.
> [PATCH v2 4/4] i.MX27: visstrim_m10: Add video support.

Applied, thanks.

Sascha

> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar  2 02:26:40 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2012 08:26:40 +0100
Subject: [PATCH] i.MX27: visstrim_m10: Add led support.
In-Reply-To: <1330517853-30870-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330517853-30870-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120302072640.GB19905@pengutronix.de>

On Wed, Feb 29, 2012 at 01:17:33PM +0100, Javier Martin wrote:
> Vista Silicon Visstrim_m10 board has 4
> leds to signal several working conditions.
> 
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>

Applied, thanks

Sascha

> ---
>  This patch has to be applied on top of the following series:
>    [PATCH 0/4] i.MX27: visstrim_m10: Add several peripherals.
> 
> ---
>  arch/arm/mach-imx/Kconfig                   |    1 +
>  arch/arm/mach-imx/mach-imx27_visstrim_m10.c |   31 +++++++++++++++++++++++++++
>  2 files changed, 32 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 8102e7f..a3125ac 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -323,6 +323,7 @@ config MACH_IMX27_VISSTRIM_M10
>  	select IMX_HAVE_PLATFORM_MX2_CAMERA
>  	select IMX_HAVE_PLATFORM_MXC_EHCI
>  	select IMX_HAVE_PLATFORM_MXC_MMC
> +	select LEDS_GPIO_REGISTER
>  	help
>  	  Include support for Visstrim_m10 platform and its different variants.
>  	  This includes specific configurations for the board and its
> diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> index 7208a9e..0a1643c 100644
> --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> @@ -31,6 +31,7 @@
>  #include <linux/gpio.h>
>  #include <linux/delay.h>
>  #include <linux/dma-mapping.h>
> +#include <linux/leds.h>
>  #include <linux/memblock.h>
>  #include <media/soc_camera.h>
>  #include <sound/tlv320aic32x4.h>
> @@ -232,6 +233,35 @@ static const struct gpio_keys_platform_data
>  	.nbuttons	= ARRAY_SIZE(visstrim_gpio_keys),
>  };
>  
> +/* led */
> +static const struct gpio_led visstrim_m10_leds[] __initconst = {
> +	{
> +		.name = "visstrim:ld0",
> +		.default_trigger = "nand-disk",
> +		.gpio = (GPIO_PORTC + 29),
> +	},
> +	{
> +		.name = "visstrim:ld1",
> +		.default_trigger = "nand-disk",
> +		.gpio = (GPIO_PORTC + 24),
> +	},
> +	{
> +		.name = "visstrim:ld2",
> +		.default_trigger = "nand-disk",
> +		.gpio = (GPIO_PORTC + 28),
> +	},
> +	{
> +		.name = "visstrim:ld3",
> +		.default_trigger = "nand-disk",
> +		.gpio = (GPIO_PORTC + 25),
> +	},
> +};
> +
> +static const struct gpio_led_platform_data visstrim_m10_led_data __initconst = {
> +	.leds = visstrim_m10_leds,
> +	.num_leds = ARRAY_SIZE(visstrim_m10_leds),
> +};
> +
>  /* Visstrim_SM10 has a microSD slot connected to sdhc1 */
>  static int visstrim_m10_sdhc1_init(struct device *dev,
>  		irq_handler_t detect_irq, void *data)
> @@ -365,6 +395,7 @@ static void __init visstrim_m10_board_init(void)
>  	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
>  	platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
>  				      &iclink_tvp5150, sizeof(iclink_tvp5150));
> +	gpio_led_register_device(0, &visstrim_m10_led_data);
>  	visstrim_camera_init();
>  }
>  
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar  2 02:30:20 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2012 08:30:20 +0100
Subject: [GIT PULL] i.MX visstrim patches
Message-ID: <20120302073020.GH26642@pengutronix.de>

Hi Arnd,

Please pull the following i.MX27 visstrim driver updates for
-next.

Sascha


The following changes since commit 6b21d18ed50c7d145220b0724ea7f2613abf0f95:

  Linux 3.3-rc5 (2012-02-25 12:18:16 -0800)

are available in the git repository at:

  git://git.pengutronix.de/git/imx/linux-2.6.git features/imx27-visstrim

for you to fetch changes up to acb6464c7bcbfe23a9979f1eeed5acd9aff49774:

  i.MX27: visstrim_m10: Add led support. (2012-03-02 08:25:54 +0100)

----------------------------------------------------------------
Javier Martin (5):
      i.MX27: visstrim_m10: Add m41t00 RTC support.
      i.MX27: visstrim_m10: Sort IMX_HAVE_PLATFORM_MXC_MMC properly.
      i.MX27: visstrim_m10: Register I2C devices after I2C busses have been added.
      i.MX27: visstrim_m10: Add video support.
      i.MX27: visstrim_m10: Add led support.

 arch/arm/mach-imx/Kconfig                   |    4 +-
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c |  139 ++++++++++++++++++++++++++-
 2 files changed, 140 insertions(+), 3 deletions(-)
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar  2 02:32:24 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2012 08:32:24 +0100
Subject: [GIT PULL] i.MX27 devicetree support
Message-ID: <20120302073224.GI26642@pengutronix.de>

Hi Arnd,

Please pull the following series adding devicetree support for i.MX27
for -next

Sascha


The following changes since commit 6b21d18ed50c7d145220b0724ea7f2613abf0f95:

  Linux 3.3-rc5 (2012-02-25 12:18:16 -0800)

are available in the git repository at:

  git://git.pengutronix.de/git/imx/linux-2.6.git features/imx27-dt

for you to fetch changes up to 6ad109fa3f46713a5cd28f41d872c9a4fc2bcedc:

  devicetree-bindings: Add documentation for i.MX generic boards (2012-02-29 09:16:50 +0100)

----------------------------------------------------------------
Sascha Hauer (3):
      ARM i.MX27: Add devicetree support
      ARM i.MX: Add phytec phycore-i.MX27 (aka pcm038) devicetree support
      devicetree-bindings: Add documentation for i.MX generic boards

 Documentation/devicetree/bindings/arm/fsl.txt |   22 +++
 arch/arm/boot/dts/imx27-phytec-phycore.dts    |   76 +++++++++
 arch/arm/boot/dts/imx27.dtsi                  |  217 +++++++++++++++++++++++++
 arch/arm/mach-imx/Kconfig                     |    8 +
 arch/arm/mach-imx/Makefile                    |    1 +
 arch/arm/mach-imx/clock-imx27.c               |   18 ++
 arch/arm/mach-imx/imx27-dt.c                  |   89 ++++++++++
 arch/arm/plat-mxc/include/mach/common.h       |    1 +
 8 files changed, 432 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx27-phytec-phycore.dts
 create mode 100644 arch/arm/boot/dts/imx27.dtsi
 create mode 100644 arch/arm/mach-imx/imx27-dt.c
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar  2 02:42:58 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2012 08:42:58 +0100
Subject: [GIT PULL] i.MX31 Moboard updates
Message-ID: <20120302074258.GG3852@pengutronix.de>

Hi Arnd,

Please pull the following i.MX31 Moboard specific updates for -next

Sascha


The following changes since commit 6b21d18ed50c7d145220b0724ea7f2613abf0f95:

  Linux 3.3-rc5 (2012-02-25 12:18:16 -0800)

are available in the git repository at:

  git://git.pengutronix.de/git/imx/linux-2.6.git features/imx31-moboard

for you to fetch changes up to 31776fbc66fef50cad30dc65404145d254646172:

  mx31moboard: Add watchdog support (2012-03-02 08:38:44 +0100)

----------------------------------------------------------------
Philippe R?tornaz (2):
      mx31moboard: update maintainer
      mx31moboard: Add watchdog support

 arch/arm/mach-imx/Kconfig            |    1 +
 arch/arm/mach-imx/mach-mx31moboard.c |    4 +++-
 2 files changed, 4 insertions(+), 1 deletions(-)
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar  2 02:50:04 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2012 08:50:04 +0100
Subject: [PATCH v3] ARM: mx3: Setup AIPS registers
In-Reply-To: <1330522088-20357-1-git-send-email-festevam@gmail.com>
References: <1330522088-20357-1-git-send-email-festevam@gmail.com>
Message-ID: <20120302075004.GH3852@pengutronix.de>

On Wed, Feb 29, 2012 at 10:28:08AM -0300, Fabio Estevam wrote:
> It was observed on a mx31pdk board that audio playback only worked when the bootloader was Redboot, and 
> did not work when U-boot was used. 
> 
> Comparing the sources of these bootloaders showed that the AIPS registers were not setup in U-boot.
> 
> Instead of relying on the bootloader to setup the AIPS registers, do it in the kernel so that audio
> playback can work independantly of the bootloader being used.
> 
> Copied the AIPS settings from Redboot to the kernel.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Applied, thanks.

Sascha

> ---
> Changes since v2:
> - Place mx_set_aips inside imx31_soc_init
> Changes since v1:
> - Make sure post_cpu_init() only runs on mx31
> - Place imx_set_aips() in a common location so that other SoCs can use it.
> - Improve comments about OPACRx
>  arch/arm/mach-imx/mm-imx3.c             |    3 +++
>  arch/arm/plat-mxc/cpu.c                 |   24 ++++++++++++++++++++++++
>  arch/arm/plat-mxc/include/mach/common.h |    1 +
>  3 files changed, 28 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
> index 6222151..77cf553 100644
> --- a/arch/arm/mach-imx/mm-imx3.c
> +++ b/arch/arm/mach-imx/mm-imx3.c
> @@ -173,6 +173,9 @@ void __init imx31_soc_init(void)
>  	}
>  
>  	imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
> +
> +	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
> +	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
>  }
>  #endif /* ifdef CONFIG_SOC_IMX31 */
>  
> diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
> index f5b7e0f..220dd6f 100644
> --- a/arch/arm/plat-mxc/cpu.c
> +++ b/arch/arm/plat-mxc/cpu.c
> @@ -1,5 +1,6 @@
>  
>  #include <linux/module.h>
> +#include <linux/io.h>
>  #include <mach/hardware.h>
>  
>  unsigned int __mxc_cpu_type;
> @@ -18,3 +19,26 @@ void imx_print_silicon_rev(const char *cpu, int srev)
>  		pr_info("CPU identified as %s, silicon rev %d.%d\n",
>  				cpu, (srev >> 4) & 0xf, srev & 0xf);
>  }
> +
> +void __init imx_set_aips(void __iomem *base)
> +{
> +	unsigned int reg;
> +/*
> + * Set all MPROTx to be non-bufferable, trusted for R/W,
> + * not forced to user-mode.
> + */
> +	__raw_writel(0x77777777, base + 0x0);
> +	__raw_writel(0x77777777, base + 0x4);
> +
> +/*
> + * Set all OPACRx to be non-bufferable, to not require
> + * supervisor privilege level for access, allow for
> + * write access and untrusted master access.
> + */
> +	__raw_writel(0x0, base + 0x40);
> +	__raw_writel(0x0, base + 0x44);
> +	__raw_writel(0x0, base + 0x48);
> +	__raw_writel(0x0, base + 0x4C);
> +	reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
> +	__raw_writel(reg, base + 0x50);
> +}
> diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
> index 1bf0df8..16c3864 100644
> --- a/arch/arm/plat-mxc/include/mach/common.h
> +++ b/arch/arm/plat-mxc/include/mach/common.h
> @@ -75,6 +75,7 @@ extern void mxc_restart(char, const char *);
>  extern void mxc_arch_reset_init(void __iomem *);
>  extern int mx53_revision(void);
>  extern int mx53_display_revision(void);
> +extern void imx_set_aips(void __iomem *);
>  
>  enum mxc_cpu_pwr_mode {
>  	WAIT_CLOCKED,		/* wfi only */
> -- 
> 1.7.1
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From paul.liu at linaro.org  Fri Mar  2 02:51:55 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Fri, 02 Mar 2012 15:51:55 +0800
Subject: [PATCH v6 1/2] mfd: Add anatop mfd driver
In-Reply-To: <D958900912E20642BCBC71664EFECE3E6DD2912252@BGMAIL02.nvidia.com>
References: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
 <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
 <D958900912E20642BCBC71664EFECE3E6DD2912252@BGMAIL02.nvidia.com>
Message-ID: <4F507C1B.1050909@linaro.org>

(2012?03?02? 15:07), Venu Byravarasu wrote:
> Why you did not made use of regmap?
> 

Hi Venu,

I cannot fully understand. Anatop is not SPI or I2C device. It is
internally embedded into the SoC. It is directly accessed by memory I/O.

Do you mean I should implement a regmap_bus which uses memory I/O and
then use regmap?

Regards,
Paul

>> -----Original Message-----
>> From: linux-kernel-owner at vger.kernel.org [mailto:linux-kernel-
>> owner at vger.kernel.org] On Behalf Of Ying-Chun Liu (PaulLiu)
>> Sent: Friday, March 02, 2012 12:31 PM
>> To: linux-arm-kernel at lists.infradead.org
>> Cc: linux-kernel at vger.kernel.org; linaro-dev at lists.linaro.org;
>> patches at linaro.org; Ying-Chun Liu (PaulLiu); Samuel Ortiz; Mark Brown; Shawn
>> Guo
>> Subject: [PATCH v6 1/2] mfd: Add anatop mfd driver
>>
>> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
>>
>> Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
>> Anatop provides regulators and thermal.
>> This driver handles the address space and the operation of the mfd device.
>>
>> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
>> Cc: Samuel Ortiz <sameo at linux.intel.com>
>> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
>> Cc: Shawn Guo <shawn.guo at linaro.org>
>> ---
>>  drivers/mfd/Kconfig        |    6 ++



From s.hauer at pengutronix.de  Fri Mar  2 03:01:05 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2012 09:01:05 +0100
Subject: [GIT PULL] i.MX3 patches
Message-ID: <20120302080105.GJ3852@pengutronix.de>

Hi Arnd,

Please pull the following i.MX3 specific patches for -next. Note
that 1/2 depends on your imx/cleanup branch since it includes
crmregs-imx3.h which is created in this branch.

Sascha

The following changes since commit d65b4e98d7ea3038b767b70fe8be959b2913f16d:

  Linux 3.3-rc3 (2012-02-08 19:21:53 -0800)

are available in the git repository at:

  git://git.pengutronix.de/git/imx/linux-2.6.git features/imx3

for you to fetch changes up to bb07d7511e0884f913a0610d5f9a2f8a27914042:

  ARM: mx3: Setup AIPS registers (2012-03-02 08:49:37 +0100)

----------------------------------------------------------------
Fabio Estevam (2):
      ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI
      ARM: mx3: Setup AIPS registers

 arch/arm/mach-imx/Makefile              |    4 +-
 arch/arm/mach-imx/crmregs-imx31.h       |    1 +
 arch/arm/mach-imx/mm-imx3.c             |    5 ++++
 arch/arm/mach-imx/pm-imx3.c             |   37 +++++++++++++++++++++++++++++++
 arch/arm/plat-mxc/cpu.c                 |   24 ++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/common.h |    9 +++++++
 6 files changed, 78 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-imx/pm-imx3.c
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From vbyravarasu at nvidia.com  Fri Mar  2 03:02:34 2012
From: vbyravarasu at nvidia.com (Venu Byravarasu)
Date: Fri, 2 Mar 2012 13:32:34 +0530
Subject: [PATCH v6 1/2] mfd: Add anatop mfd driver
In-Reply-To: <4F507C1B.1050909@linaro.org>
References: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
 <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
 <D958900912E20642BCBC71664EFECE3E6DD2912252@BGMAIL02.nvidia.com>
 <4F507C1B.1050909@linaro.org>
Message-ID: <D958900912E20642BCBC71664EFECE3E6DD2912265@BGMAIL02.nvidia.com>

> I cannot fully understand. Anatop is not SPI or I2C device. It is
> internally embedded into the SoC. It is directly accessed by memory I/O.

Sorry, I missed this.

> Do you mean I should implement a regmap_bus which uses memory I/O and
> then use regmap?
> 
> Regards,
> Paul

From pullip.cho at samsung.com  Fri Mar  2 03:05:30 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Fri, 2 Mar 2012 17:05:30 +0900
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
Message-ID: <CAHQjnOO5DLOj8Fw=ZriSnXg8W3k7y8Dnu--Peqe6JJX0xGMhoQ@mail.gmail.com>

On Thu, Mar 1, 2012 at 12:04 AM, Marek Szyprowski
<m.szyprowski at samsung.com> wrote:
> +/**
> + * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
> + * @dev: valid struct device pointer
> + * @sg: list of buffers
> + * @nents: number of buffers to map
> + * @dir: DMA transfer direction
> + *
> + * Map a set of buffers described by scatterlist in streaming mode for DMA.
> + * The scatter gather list elements are merged together (if possible) and
> + * tagged with the appropriate dma address and length. They are obtained via
> + * sg_dma_{address,length}.
> + */
> +int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
> + ? ? ? ? ? ? ? ? ? ?enum dma_data_direction dir, struct dma_attrs *attrs)
> +{
> + ? ? ? struct scatterlist *s = sg, *dma = sg, *start = sg;
> + ? ? ? int i, count = 0;
> + ? ? ? unsigned int offset = s->offset;
> + ? ? ? unsigned int size = s->offset + s->length;
> + ? ? ? unsigned int max = dma_get_max_seg_size(dev);
> +
> + ? ? ? for (i = 1; i < nents; i++) {
> + ? ? ? ? ? ? ? s->dma_address = ARM_DMA_ERROR;
> + ? ? ? ? ? ? ? s->dma_length = 0;
> +
> + ? ? ? ? ? ? ? s = sg_next(s);
> +
> + ? ? ? ? ? ? ? if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
> + ? ? ? ? ? ? ? ? ? ? ? if (__map_sg_chunk(dev, start, size, &dma->dma_address,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? dir) < 0)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? goto bad_mapping;
> +
> + ? ? ? ? ? ? ? ? ? ? ? dma->dma_address += offset;
> + ? ? ? ? ? ? ? ? ? ? ? dma->dma_length = size - offset;
> +
> + ? ? ? ? ? ? ? ? ? ? ? size = offset = s->offset;
> + ? ? ? ? ? ? ? ? ? ? ? start = s;
> + ? ? ? ? ? ? ? ? ? ? ? dma = sg_next(dma);
> + ? ? ? ? ? ? ? ? ? ? ? count += 1;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? size += s->length;
> + ? ? ? }
> + ? ? ? if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir) < 0)
> + ? ? ? ? ? ? ? goto bad_mapping;
> +
> + ? ? ? dma->dma_address += offset;
> + ? ? ? dma->dma_length = size - offset;
> +
> + ? ? ? return count+1;
> +
> +bad_mapping:
> + ? ? ? for_each_sg(sg, s, count, i)
> + ? ? ? ? ? ? ? __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
> + ? ? ? return 0;
> +}
> +
This looks that the given sg list specifies the list of physical
memory chunks and
the list of IO virtual memory chunks at the same time after calling
arm_dma_map_sg().
It can happen that dma_address and dma_length of a sg entry does not
correspond to
physical memory information of the sg entry.

I think it is beneficial for handling IO virtual memory.

However, I worry about any other problems caused by a single sg entry contains
information from 2 different context.

Regards,

Cho KyongHo.


From javier.martin at vista-silicon.com  Fri Mar  2 03:28:47 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  2 Mar 2012 09:28:47 +0100
Subject: [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for
 imx-dma.
Message-ID: <1330676927-7330-1-git-send-email-javier.martin@vista-silicon.com>

dmaengine specifies the possibility that several descriptors
can be queued for transfer. It also indicates that tasklets
must be used for DMA callbacks.

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 Added comment explaining fall through in 'imxdma_xfer_desc'.

---
 drivers/dma/imx-dma.c |  332 ++++++++++++++++++++++++++++++++++++++-----------
 1 files changed, 258 insertions(+), 74 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 9aa6e85..c32103f 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -5,6 +5,7 @@
  * found on i.MX1/21/27
  *
  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
+ * Copyright 2012 Javier Martin, Vista Silicon <javier.martin at vista-silicon.com>
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -13,6 +14,7 @@
  * http://www.opensource.org/licenses/gpl-license.html
  * http://www.gnu.org/copyleft/gpl.html
  */
+
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/types.h>
@@ -30,19 +32,52 @@
 #include <mach/dma-v1.h>
 #include <mach/hardware.h>
 
+#define IMXDMA_MAX_CHAN_DESCRIPTORS	16
+
+enum  imxdma_prep_type {
+	IMXDMA_DESC_MEMCPY,
+	IMXDMA_DESC_INTERLEAVED,
+	IMXDMA_DESC_SLAVE_SG,
+	IMXDMA_DESC_CYCLIC,
+};
+
+struct imxdma_desc {
+	struct list_head		node;
+	struct dma_async_tx_descriptor	desc;
+	enum dma_status			status;
+	dma_addr_t			src;
+	dma_addr_t			dest;
+	size_t				len;
+	unsigned int			dmamode;
+	enum imxdma_prep_type		type;
+	/* For memcpy and interleaved */
+	unsigned int			config_port;
+	unsigned int			config_mem;
+	/* For interleaved transfers */
+	unsigned int			x;
+	unsigned int			y;
+	unsigned int			w;
+	/* For slave sg and cyclic */
+	struct scatterlist		*sg;
+	unsigned int			sgcount;
+};
+
 struct imxdma_channel {
 	struct imxdma_engine		*imxdma;
 	unsigned int			channel;
 	unsigned int			imxdma_channel;
 
+	struct tasklet_struct		dma_tasklet;
+	struct list_head		ld_free;
+	struct list_head		ld_queue;
+	struct list_head		ld_active;
+	int				descs_allocated;
 	enum dma_slave_buswidth		word_size;
 	dma_addr_t			per_address;
 	u32				watermark_level;
 	struct dma_chan			chan;
 	spinlock_t			lock;
-	struct dma_async_tx_descriptor	desc;
 	dma_cookie_t			last_completed;
-	enum dma_status			status;
 	int				dma_request;
 	struct scatterlist		*sg_list;
 };
@@ -61,27 +96,31 @@ static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
 	return container_of(chan, struct imxdma_channel, chan);
 }
 
-static void imxdma_handle(struct imxdma_channel *imxdmac)
+static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 {
-	if (imxdmac->desc.callback)
-		imxdmac->desc.callback(imxdmac->desc.callback_param);
-	imxdmac->last_completed = imxdmac->desc.cookie;
+	struct imxdma_desc *desc;
+
+	if (!list_empty(&imxdmac->ld_active)) {
+		desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
+					node);
+		if (desc->type == IMXDMA_DESC_CYCLIC)
+			return true;
+	}
+	return false;
 }
 
 static void imxdma_irq_handler(int channel, void *data)
 {
 	struct imxdma_channel *imxdmac = data;
 
-	imxdmac->status = DMA_SUCCESS;
-	imxdma_handle(imxdmac);
+	tasklet_schedule(&imxdmac->dma_tasklet);
 }
 
 static void imxdma_err_handler(int channel, void *data, int error)
 {
 	struct imxdma_channel *imxdmac = data;
 
-	imxdmac->status = DMA_ERROR;
-	imxdma_handle(imxdmac);
+	tasklet_schedule(&imxdmac->dma_tasklet);
 }
 
 static void imxdma_progression(int channel, void *data,
@@ -89,8 +128,88 @@ static void imxdma_progression(int channel, void *data,
 {
 	struct imxdma_channel *imxdmac = data;
 
-	imxdmac->status = DMA_SUCCESS;
-	imxdma_handle(imxdmac);
+	tasklet_schedule(&imxdmac->dma_tasklet);
+}
+
+static int imxdma_xfer_desc(struct imxdma_desc *d)
+{
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	int ret;
+
+	/* Configure and enable */
+	switch (d->type) {
+	case IMXDMA_DESC_MEMCPY:
+		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+					  d->config_port, d->config_mem, 0, 0);
+		if (ret < 0)
+			return ret;
+		ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
+					   d->len, d->dest, d->dmamode);
+		if (ret < 0)
+			return ret;
+		break;
+	case IMXDMA_DESC_CYCLIC:
+		ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
+							imxdma_progression);
+		if (ret < 0)
+			return ret;
+		/*
+		 * We fall through here since cyclic transfer is the same as
+		 * slave_sg adding a progression handler and a specific sg
+		 * configuration which is done in 'imxdma_prep_dma_cyclic'.
+		 */
+	case IMXDMA_DESC_SLAVE_SG:
+		if (d->dmamode == DMA_MODE_READ)
+			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+				       d->sgcount, d->len, d->src, d->dmamode);
+		else
+			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+				      d->sgcount, d->len, d->dest, d->dmamode);
+		if (ret < 0)
+			return ret;
+		break;
+	default:
+		return -EINVAL;
+	}
+	imx_dma_enable(imxdmac->imxdma_channel);
+	return 0;
+}
+
+static void imxdma_tasklet(unsigned long data)
+{
+	struct imxdma_channel *imxdmac = (void *)data;
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
+	struct imxdma_desc *desc;
+
+	spin_lock(&imxdmac->lock);
+
+	if (list_empty(&imxdmac->ld_active)) {
+		/* Someone might have called terminate all */
+		goto out;
+	}
+	desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
+
+	if (desc->desc.callback)
+		desc->desc.callback(desc->desc.callback_param);
+
+	imxdmac->last_completed = desc->desc.cookie;
+
+	/* If we are dealing with a cyclic descriptor keep it on ld_active */
+	if (imxdma_chan_is_doing_cyclic(imxdmac))
+		goto out;
+
+	list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
+
+	if (!list_empty(&imxdmac->ld_queue)) {
+		desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
+					node);
+		list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
+		if (imxdma_xfer_desc(desc) < 0)
+			dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
+				 __func__, imxdmac->channel);
+	}
+out:
+	spin_unlock(&imxdmac->lock);
 }
 
 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
@@ -99,12 +218,17 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct dma_slave_config *dmaengine_cfg = (void *)arg;
 	int ret;
+	unsigned long flags;
 	unsigned int mode = 0;
 
 	switch (cmd) {
 	case DMA_TERMINATE_ALL:
-		imxdmac->status = DMA_ERROR;
 		imx_dma_disable(imxdmac->imxdma_channel);
+
+		spin_lock_irqsave(&imxdmac->lock, flags);
+		list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
+		list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
+		spin_unlock_irqrestore(&imxdmac->lock, flags);
 		return 0;
 	case DMA_SLAVE_CONFIG:
 		if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
@@ -155,11 +279,14 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	dma_cookie_t last_used;
 	enum dma_status ret;
+	unsigned long flags;
 
+	spin_lock_irqsave(&imxdmac->lock, flags);
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, imxdmac->last_completed, last_used);
 	dma_set_tx_state(txstate, imxdmac->last_completed, last_used, 0);
+	spin_unlock_irqrestore(&imxdmac->lock, flags);
 
 	return ret;
 }
@@ -172,7 +299,6 @@ static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma)
 		cookie = 1;
 
 	imxdma->chan.cookie = cookie;
-	imxdma->desc.cookie = cookie;
 
 	return cookie;
 }
@@ -181,12 +307,15 @@ static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
 	dma_cookie_t cookie;
+	unsigned long flags;
 
-	spin_lock_irq(&imxdmac->lock);
+	spin_lock_irqsave(&imxdmac->lock, flags);
 
+	list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
 	cookie = imxdma_assign_cookie(imxdmac);
+	tx->cookie = cookie;
 
-	spin_unlock_irq(&imxdmac->lock);
+	spin_unlock_irqrestore(&imxdmac->lock, flags);
 
 	return cookie;
 }
@@ -199,21 +328,48 @@ static int imxdma_alloc_chan_resources(struct dma_chan *chan)
 	if (data != NULL)
 		imxdmac->dma_request = data->dma_request;
 
-	dma_async_tx_descriptor_init(&imxdmac->desc, chan);
-	imxdmac->desc.tx_submit = imxdma_tx_submit;
-	/* txd.flags will be overwritten in prep funcs */
-	imxdmac->desc.flags = DMA_CTRL_ACK;
+	while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
+		struct imxdma_desc *desc;
 
-	imxdmac->status = DMA_SUCCESS;
+		desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+		if (!desc)
+			break;
+		__memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
+		dma_async_tx_descriptor_init(&desc->desc, chan);
+		desc->desc.tx_submit = imxdma_tx_submit;
+		/* txd.flags will be overwritten in prep funcs */
+		desc->desc.flags = DMA_CTRL_ACK;
+		desc->status = DMA_SUCCESS;
+
+		list_add_tail(&desc->node, &imxdmac->ld_free);
+		imxdmac->descs_allocated++;
+	}
 
-	return 0;
+	if (!imxdmac->descs_allocated)
+		return -ENOMEM;
+
+	return imxdmac->descs_allocated;
 }
 
 static void imxdma_free_chan_resources(struct dma_chan *chan)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
+	struct imxdma_desc *desc, *_desc;
+	unsigned long flags;
+
+	spin_lock_irqsave(&imxdmac->lock, flags);
 
 	imx_dma_disable(imxdmac->imxdma_channel);
+	list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
+	list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
+
+	spin_unlock_irqrestore(&imxdmac->lock, flags);
+
+	list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
+		kfree(desc);
+		imxdmac->descs_allocated--;
+	}
+	INIT_LIST_HEAD(&imxdmac->ld_free);
 
 	if (imxdmac->sg_list) {
 		kfree(imxdmac->sg_list);
@@ -228,23 +384,19 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct scatterlist *sg;
-	int i, ret, dma_length = 0;
-	unsigned int dmamode;
+	int i, dma_length = 0;
+	struct imxdma_desc *desc;
 
-	if (imxdmac->status == DMA_IN_PROGRESS)
+	if (list_empty(&imxdmac->ld_free) ||
+	    imxdma_chan_is_doing_cyclic(imxdmac))
 		return NULL;
 
-	imxdmac->status = DMA_IN_PROGRESS;
+	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 
 	for_each_sg(sgl, sg, sg_len, i) {
 		dma_length += sg->length;
 	}
 
-	if (direction == DMA_DEV_TO_MEM)
-		dmamode = DMA_MODE_READ;
-	else
-		dmamode = DMA_MODE_WRITE;
-
 	switch (imxdmac->word_size) {
 	case DMA_SLAVE_BUSWIDTH_4_BYTES:
 		if (sgl->length & 3 || sgl->dma_address & 3)
@@ -260,12 +412,21 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
 		return NULL;
 	}
 
-	ret = imx_dma_setup_sg(imxdmac->imxdma_channel, sgl, sg_len,
-		 dma_length, imxdmac->per_address, dmamode);
-	if (ret)
-		return NULL;
+	desc->type = IMXDMA_DESC_SLAVE_SG;
+	desc->sg = sgl;
+	desc->sgcount = sg_len;
+	desc->len = dma_length;
+	if (direction == DMA_DEV_TO_MEM) {
+		desc->dmamode = DMA_MODE_READ;
+		desc->src = imxdmac->per_address;
+	} else {
+		desc->dmamode = DMA_MODE_WRITE;
+		desc->dest = imxdmac->per_address;
+	}
+	desc->desc.callback = NULL;
+	desc->desc.callback_param = NULL;
 
-	return &imxdmac->desc;
+	return &desc->desc;
 }
 
 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
@@ -274,23 +435,18 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
-	int i, ret;
+	struct imxdma_desc *desc;
+	int i;
 	unsigned int periods = buf_len / period_len;
-	unsigned int dmamode;
 
 	dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
 			__func__, imxdmac->channel, buf_len, period_len);
 
-	if (imxdmac->status == DMA_IN_PROGRESS)
+	if (list_empty(&imxdmac->ld_free) ||
+	    imxdma_chan_is_doing_cyclic(imxdmac))
 		return NULL;
-	imxdmac->status = DMA_IN_PROGRESS;
 
-	ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
-			imxdma_progression);
-	if (ret) {
-		dev_err(imxdma->dev, "Failed to setup the DMA handler\n");
-		return NULL;
-	}
+	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 
 	if (imxdmac->sg_list)
 		kfree(imxdmac->sg_list);
@@ -316,17 +472,21 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
 	imxdmac->sg_list[periods].page_link =
 		((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
 
-	if (direction == DMA_DEV_TO_MEM)
-		dmamode = DMA_MODE_READ;
-	else
-		dmamode = DMA_MODE_WRITE;
-
-	ret = imx_dma_setup_sg(imxdmac->imxdma_channel, imxdmac->sg_list, periods,
-		 IMX_DMA_LENGTH_LOOP, imxdmac->per_address, dmamode);
-	if (ret)
-		return NULL;
+	desc->type = IMXDMA_DESC_CYCLIC;
+	desc->sg = imxdmac->sg_list;
+	desc->sgcount = periods;
+	desc->len = IMX_DMA_LENGTH_LOOP;
+	if (direction == DMA_DEV_TO_MEM) {
+		desc->dmamode = DMA_MODE_READ;
+		desc->src = imxdmac->per_address;
+	} else {
+		desc->dmamode = DMA_MODE_WRITE;
+		desc->dest = imxdmac->per_address;
+	}
+	desc->desc.callback = NULL;
+	desc->desc.callback_param = NULL;
 
-	return &imxdmac->desc;
+	return &desc->desc;
 }
 
 static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
@@ -335,36 +495,53 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
-	int ret;
+	struct imxdma_desc *desc;
 
 	dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
 			__func__, imxdmac->channel, src, dest, len);
 
-	if (imxdmac->status == DMA_IN_PROGRESS)
+	if (list_empty(&imxdmac->ld_free) ||
+	    imxdma_chan_is_doing_cyclic(imxdmac))
 		return NULL;
-	imxdmac->status = DMA_IN_PROGRESS;
 
-	ret = imx_dma_config_channel(imxdmac->imxdma_channel,
-			       IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
-			       IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
-			       0, 0);
-	if (ret)
-		return NULL;
+	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 
-	ret = imx_dma_setup_single(imxdmac->imxdma_channel, src, len,
-				   dest, DMA_MODE_WRITE);
-	if (ret)
-		return NULL;
+	desc->type = IMXDMA_DESC_MEMCPY;
+	desc->src = src;
+	desc->dest = dest;
+	desc->len = len;
+	desc->dmamode = DMA_MODE_WRITE;
+	desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
+	desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
+	desc->desc.callback = NULL;
+	desc->desc.callback_param = NULL;
 
-	return &imxdmac->desc;
+	return &desc->desc;
 }
 
 static void imxdma_issue_pending(struct dma_chan *chan)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
-
-	if (imxdmac->status == DMA_IN_PROGRESS)
-		imx_dma_enable(imxdmac->imxdma_channel);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
+	struct imxdma_desc *desc;
+	unsigned long flags;
+
+	spin_lock_irqsave(&imxdmac->lock, flags);
+	if (list_empty(&imxdmac->ld_active) &&
+	    !list_empty(&imxdmac->ld_queue)) {
+		desc = list_first_entry(&imxdmac->ld_queue,
+					struct imxdma_desc, node);
+
+		if (imxdma_xfer_desc(desc) < 0) {
+			dev_warn(imxdma->dev,
+				 "%s: channel: %d couldn't issue DMA xfer\n",
+				 __func__, imxdmac->channel);
+		} else {
+			list_move_tail(imxdmac->ld_queue.next,
+				       &imxdmac->ld_active);
+		}
+	}
+	spin_unlock_irqrestore(&imxdmac->lock, flags);
 }
 
 static int __init imxdma_probe(struct platform_device *pdev)
@@ -399,11 +576,18 @@ static int __init imxdma_probe(struct platform_device *pdev)
 		imxdmac->imxdma = imxdma;
 		spin_lock_init(&imxdmac->lock);
 
+		INIT_LIST_HEAD(&imxdmac->ld_queue);
+		INIT_LIST_HEAD(&imxdmac->ld_free);
+		INIT_LIST_HEAD(&imxdmac->ld_active);
+
+		tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
+			     (unsigned long)imxdmac);
 		imxdmac->chan.device = &imxdma->dma_device;
 		imxdmac->channel = i;
 
 		/* Add the channel to the DMAC list */
-		list_add_tail(&imxdmac->chan.device_node, &imxdma->dma_device.channels);
+		list_add_tail(&imxdmac->chan.device_node,
+			      &imxdma->dma_device.channels);
 	}
 
 	imxdma->dev = &pdev->dev;
-- 
1.7.0.4



From simon at sequanux.org  Fri Mar  2 04:15:11 2012
From: simon at sequanux.org (Simon Guinot)
Date: Fri, 2 Mar 2012 10:15:11 +0100
Subject: [PATCH 4/4] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <2f29e88b98b2bcff0c241996e6d7216a60995d2d.1330625878.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2f29e88b98b2bcff0c241996e6d7216a60995d2d.1330625878.git.jason@lakedaemon.net>
Message-ID: <20120302091510.GC29461@kw.sim.vm.gnt>

Hi Jason,

On Thu, Mar 01, 2012 at 06:20:55PM +0000, Jason Cooper wrote:
> Converted register address to a variable so that it could be set from
> fdt.  Also, pull clock frequency from fdt and clean up failure logic a
> bit.
> 
> Same as rtc-mv, this device is used in all kirkwood boards.  So, it is
> placed in kirkwood.dtsi.
> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  arch/arm/boot/dts/kirkwood.dtsi   |    6 +++++
>  arch/arm/mach-kirkwood/board-dt.c |    1 -
>  arch/arm/mach-kirkwood/common.c   |    2 +-
>  arch/arm/mach-kirkwood/common.h   |    1 -
>  drivers/watchdog/orion_wdt.c      |   44 ++++++++++++++++++++++++++----------
>  5 files changed, 39 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
> index 5fb185c..bf28424 100644
> --- a/arch/arm/boot/dts/kirkwood.dtsi
> +++ b/arch/arm/boot/dts/kirkwood.dtsi
> @@ -8,5 +8,11 @@
>  		reg = <0xf1010300 0x1f>;
>  		interrupts = <53>;
>  	};
> +
> +	wdt at fed20300 {
> +		compatible = "marvell,orion-wdt";
> +		reg = <0xfed20300 0x28>;
> +		clock-frequency = <200000000>;
> +	};

How this will work for boards using a different clock frequency (TCLK) ?
Here, we could have 166MHz for example.

Can this node be updated during the board initialization with a detected
TCLK value ?

Or maybe this clock-frequency can reference a TCLK frequency defined in
a board specific dts (I don't know if the DT format allow such things) ?

Regards,

Simon

>  };
>  
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index 6fc41ae..7ef5fb7 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -135,7 +135,6 @@ static void __init kirkwood_dt_init(void)
>  #endif
>  
>  	/* internal devices that every board has */
> -	kirkwood_wdt_init();
>  	kirkwood_xor0_init();
>  	kirkwood_xor1_init();
>  	kirkwood_crypto_init();
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index 0c0375f..35dc40b 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -303,7 +303,7 @@ void __init kirkwood_xor1_init(void)
>  /*****************************************************************************
>   * Watchdog
>   ****************************************************************************/
> -void __init kirkwood_wdt_init(void)
> +static void __init kirkwood_wdt_init(void)
>  {
>  	orion_wdt_init(kirkwood_tclk);
>  }
> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
> index ca08826..ac4b2fb 100644
> --- a/arch/arm/mach-kirkwood/common.h
> +++ b/arch/arm/mach-kirkwood/common.h
> @@ -53,7 +53,6 @@ void kirkwood_restart(char, const char *);
>  
>  char *kirkwood_id(void);
>  void kirkwood_l2_init(void);
> -void kirkwood_wdt_init(void);
>  void kirkwood_xor0_init(void);
>  void kirkwood_xor1_init(void);
>  void kirkwood_crypto_init(void);
> diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
> index 4ad78f8..4be76ca 100644
> --- a/drivers/watchdog/orion_wdt.c
> +++ b/drivers/watchdog/orion_wdt.c
> @@ -17,6 +17,7 @@
>  #include <linux/fs.h>
>  #include <linux/miscdevice.h>
>  #include <linux/platform_device.h>
> +#include <linux/of.h>
>  #include <linux/watchdog.h>
>  #include <linux/init.h>
>  #include <linux/uaccess.h>
> @@ -28,9 +29,9 @@
>  /*
>   * Watchdog timer block registers.
>   */
> -#define TIMER_CTRL		(TIMER_VIRT_BASE + 0x0000)
> +#define TIMER_CTRL		0x0000
>  #define  WDT_EN			0x0010
> -#define WDT_VAL			(TIMER_VIRT_BASE + 0x0024)
> +#define WDT_VAL			0x0024
>  
>  #define WDT_MAX_CYCLE_COUNT	0xffffffff
>  #define WDT_IN_USE		0
> @@ -40,6 +41,7 @@ static int nowayout = WATCHDOG_NOWAYOUT;
>  static int heartbeat = -1;		/* module parameter (seconds) */
>  static unsigned int wdt_max_duration;	/* (seconds) */
>  static unsigned int wdt_tclk;
> +static unsigned int wdt_reg;
>  static unsigned long wdt_status;
>  static DEFINE_SPINLOCK(wdt_lock);
>  
> @@ -48,7 +50,7 @@ static void orion_wdt_ping(void)
>  	spin_lock(&wdt_lock);
>  
>  	/* Reload watchdog duration */
> -	writel(wdt_tclk * heartbeat, WDT_VAL);
> +	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
>  
>  	spin_unlock(&wdt_lock);
>  }
> @@ -60,7 +62,7 @@ static void orion_wdt_enable(void)
>  	spin_lock(&wdt_lock);
>  
>  	/* Set watchdog duration */
> -	writel(wdt_tclk * heartbeat, WDT_VAL);
> +	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
>  
>  	/* Clear watchdog timer interrupt */
>  	reg = readl(BRIDGE_CAUSE);
> @@ -68,9 +70,9 @@ static void orion_wdt_enable(void)
>  	writel(reg, BRIDGE_CAUSE);
>  
>  	/* Enable watchdog timer */
> -	reg = readl(TIMER_CTRL);
> +	reg = readl(wdt_reg + TIMER_CTRL);
>  	reg |= WDT_EN;
> -	writel(reg, TIMER_CTRL);
> +	writel(reg, wdt_reg + TIMER_CTRL);
>  
>  	/* Enable reset on watchdog */
>  	reg = readl(RSTOUTn_MASK);
> @@ -92,9 +94,9 @@ static void orion_wdt_disable(void)
>  	writel(reg, RSTOUTn_MASK);
>  
>  	/* Disable watchdog timer */
> -	reg = readl(TIMER_CTRL);
> +	reg = readl(wdt_reg + TIMER_CTRL);
>  	reg &= ~WDT_EN;
> -	writel(reg, TIMER_CTRL);
> +	writel(reg, wdt_reg + TIMER_CTRL);
>  
>  	spin_unlock(&wdt_lock);
>  }
> @@ -102,7 +104,7 @@ static void orion_wdt_disable(void)
>  static int orion_wdt_get_timeleft(int *time_left)
>  {
>  	spin_lock(&wdt_lock);
> -	*time_left = readl(WDT_VAL) / wdt_tclk;
> +	*time_left = readl(wdt_reg + WDT_VAL) / wdt_tclk;
>  	spin_unlock(&wdt_lock);
>  	return 0;
>  }
> @@ -236,15 +238,23 @@ static struct miscdevice orion_wdt_miscdev = {
>  static int __devinit orion_wdt_probe(struct platform_device *pdev)
>  {
>  	struct orion_wdt_platform_data *pdata = pdev->dev.platform_data;
> +	struct device_node *np = pdev->dev.of_node;
>  	int ret;
>  
> -	if (pdata) {
> +	if (pdata)
>  		wdt_tclk = pdata->tclk;
> -	} else {
> -		printk(KERN_ERR "Orion Watchdog misses platform data\n");
> +
> +	of_property_read_u32(np, "clock-frequency", &wdt_tclk);
> +
> +	if (!wdt_tclk) {
> +		printk(KERN_ERR "Orion Watchdog can't get clock freq\n");
>  		return -ENODEV;
>  	}
>  
> +	wdt_reg = TIMER_VIRT_BASE;
> +
> +	of_property_read_u32(np, "reg", &wdt_reg);
> +
>  	if (orion_wdt_miscdev.parent)
>  		return -EBUSY;
>  	orion_wdt_miscdev.parent = &pdev->dev;
> @@ -284,6 +294,15 @@ static void orion_wdt_shutdown(struct platform_device *pdev)
>  		orion_wdt_disable();
>  }
>  
> +#ifdef CONFIG_OF
> +static struct of_device_id orion_wdt_of_match_table[] = {
> +	{ .compatible = "marvell,orion-wdt", },
> +	{},
> +};
> +#else
> +#define orion_wdt_of_match_table NULL
> +#endif
> +
>  static struct platform_driver orion_wdt_driver = {
>  	.probe		= orion_wdt_probe,
>  	.remove		= __devexit_p(orion_wdt_remove),
> @@ -291,6 +310,7 @@ static struct platform_driver orion_wdt_driver = {
>  	.driver		= {
>  		.owner	= THIS_MODULE,
>  		.name	= "orion_wdt",
> +		.of_match_table = orion_wdt_of_match_table,
>  	},
>  };
>  
> -- 
> 1.7.3.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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From maxime.ripard at free-electrons.com  Fri Mar  2 04:03:12 2012
From: maxime.ripard at free-electrons.com (Maxime Ripard)
Date: Fri, 02 Mar 2012 10:03:12 +0100
Subject: IIO irq allocation fails on AT91SAM9G45
In-Reply-To: <20120229204853.GE16999@n2100.arm.linux.org.uk>
References: <4F4E36E6.1010704@free-electrons.com>
 <4F4E8C0F.5090104@kernel.org> <20120229204853.GE16999@n2100.arm.linux.org.uk>
Message-ID: <4F508CD0.20906@free-electrons.com>

Le 29/02/2012 21:48, Russell King - ARM Linux a ?crit :
> On Wed, Feb 29, 2012 at 08:35:27PM +0000, Jonathan Cameron wrote:
>> On 02/29/2012 02:32 PM, Maxime Ripard wrote:
>>> Hi everyone,
>>>
>>> I'm working on adding the support for the AT91SAM9M10G45-EK board from
>>> Atmel for the at91_adc driver I previously posted, and I encounter some
>>> weird issue here.
>>>
>>> When calling the iio_allocate_trigger
>>> (http://lxr.free-electrons.com/source/drivers/staging/iio/industrialio-trigger.c?a=arm#L421)
>>> from my driver on the G45, it returns ENOMEM, while on the
>>> AT91SAM9G20-EK board, it works perfectly.
>>>
>>> Digging a bit into it, it seems that the call to irq_alloc_descs is
>>> returning the error (the value of CONFIG_IIO_CONSUMERS_PER_TRIGGER is 2
>>> in my configuration, which seems pretty reasonable and is the default
>>> value anyway), which is itself getting that return value from
>>> irq_expand_nr_irqs.
>>>
>>> Here, I'm left confused, I don't know this part of the kernel anymore,
>>> and most importantly, it seems to be pretty-much arch-independant, while
>>> the nature of my issue seems really platform-dependant.
>>>
>>> Do you have any clue of what's going on here ?
>> We ran into this originally on the pxa as well.   My guess is that
>> nr_irqs is not set high enough for that particular board.
>>
>> Looking back I can find some mention of a nasty bit of code that
>> just adds a bit of padding but I can't find it now.
>>
>> Anyhow, you probably have a line somewhere in the kernel log
>> saying something like:
>>
>> [    0.000000] NR_IRQS:288 nr_irqs:296 296
>>
>> NR_IRQS is typically the number of the SoC
>> nr_irqs should be large enough to accomodate those provided by
>> other peripherals.
>>
>> I also have a vague recollection that the problem goes away entirely
>> with sparse irqs?
> 
> Yes, because IRQs will be allocated above the last figure on that
> line, up to IRQ_BITMAP_BITS which happens to be 8192 above NR_IRQS.
> 
> There's an issue though: if your on-SoC IRQ controller is already
> using irq_alloc_descs(), it will fail if you want it to grab IRQs
> below the last figure on that line, because those will have already
> been allocated for you.

Ok, so using either the sparse irqs or changing the definition of
NR_IRQS from 192 to 224 makes the problem go away.

I guess the reason because I was not seeing this issue with the G20 is
because it has less interrupt sources.

Anyway, I'm not sure about the augmenting the NR_IRQS fix. It seems to
work pretty well, but might it have some weird side-effects ?

Should I send a patch for it, or should I find another way to fix this ?

-- 
Maxime Ripard, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From rnayak at ti.com  Fri Mar  2 04:06:54 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 02 Mar 2012 14:36:54 +0530
Subject: [PATCH 0/4] Start getting rid of pdata callbacks with
 gpio_find_by_chip_name()
In-Reply-To: <20120301185044.29210.44521.stgit@kaulin.local>
References: <20120301185044.29210.44521.stgit@kaulin.local>
Message-ID: <4F508DAE.9000005@ti.com>

Hi Tony,

On Friday 02 March 2012 12:25 AM, Tony Lindgren wrote:
> Hi all,
>
> This series adds gpio_find_by_name() that allows finding
> GPIOs on specific gpio_chips. As the GPIO numbers can be
> dynamic, it's hard to find the GPIO numbers from drivers
> using them directly.
>
> So far we've dealt with this using platform specific callbacks,
> but that is messy. This series removes the needs for these
> callbacks for omap hsmmc driver. Further callbacks can be
> removed people are OK with adding gpio_find_by_name().
>
> This series is based on the omap fixes-non-critical that's
> needed for the arch/arm/mach-omap2 parts of this series.

I tested these on my beagle/panda/omap4sdp and they seem to
work fine, also fixing the broken panda card detect (due to
missing card_detect_irq in the board file). There are still
issues however when I build twl4030-gpio as a module, which I
already commented on, and the fact that the init sequence now
works by luck :)
The other issue also is that the multiple insmod/rmmod test
suggested by Russell still fails, since the second time around
the gpio_requests in the board callback fail because they are
not freed when you do a module unload/unbind.
That would need this patch from me to add the .teardown
hooks
http://marc.info/?l=linux-omap&m=133007767831297&w=2

regards,
Rajendra

>
> Regards,
>
> Tony
>
> ---
>
> Tony Lindgren (4):
>        gpiolib: Add gpiochip_find_by_name() and gpio_find_by_chip_name()
>        mmc: omap_hsmmc: Use gpio_find_by_chip_name() for omap_hsmmc_gpio_init()
>        mmc: omap_hsmmc: Use GPIO offset for external GPIO chips
>        mmc: omap_hsmmc: Simplify init for twl6030 MMC card detect
>
>
>   arch/arm/mach-omap2/board-3430sdp.c          |   13 +-
>   arch/arm/mach-omap2/board-4430sdp.c          |   45 --------
>   arch/arm/mach-omap2/board-cm-t35.c           |    8 -
>   arch/arm/mach-omap2/board-devkit8000.c       |    7 -
>   arch/arm/mach-omap2/board-igep0020.c         |    8 -
>   arch/arm/mach-omap2/board-omap3beagle.c      |    9 +-
>   arch/arm/mach-omap2/board-omap3evm.c         |    8 -
>   arch/arm/mach-omap2/board-omap3pandora.c     |   13 +-
>   arch/arm/mach-omap2/board-omap3stalker.c     |    8 -
>   arch/arm/mach-omap2/board-omap3touchbook.c   |    7 -
>   arch/arm/mach-omap2/board-omap4panda.c       |   52 ----------
>   arch/arm/mach-omap2/board-zoom-peripherals.c |    7 -
>   arch/arm/mach-omap2/hsmmc.c                  |    3 +
>   arch/arm/mach-omap2/hsmmc.h                  |    5 +
>   arch/arm/plat-omap/include/plat/mmc.h        |    3 +
>   drivers/gpio/gpio-twl4030.c                  |    2
>   drivers/gpio/gpiolib.c                       |   47 +++++++++
>   drivers/mfd/twl6030-irq.c                    |   33 +++---
>   drivers/mmc/host/omap_hsmmc.c                |  140 +++++++++++++++++++-------
>   include/asm-generic/gpio.h                   |    3 -
>   20 files changed, 204 insertions(+), 217 deletions(-)
>



From svenkatr at ti.com  Fri Mar  2 04:14:00 2012
From: svenkatr at ti.com (S, Venkatraman)
Date: Fri, 2 Mar 2012 14:44:00 +0530
Subject: [PATCH] ARM: OMAP: hsmmc: add max_freq field
In-Reply-To: <CANfBPZ8Oypwqq2p3rcNpp5M8+XPHDmUxMRw2J5Jw5DdAKQj8cw@mail.gmail.com>
References: <1323868927-3738-1-git-send-email-zonque@gmail.com>
 <CANrkHUY3Zf4a2K5769Z=7Wng339zB6+z_Tgd4mOPChZ1RvZ=Kw@mail.gmail.com>
 <4EFC6992.4020501@gmail.com>
 <CACTFLAMCoKfQbTe2RLTvi1_CH0nKzAOthAwrifNe2+F2sf3uPA@mail.gmail.com>
 <20120302001121.GE18901@atomide.com>
 <CANfBPZ8Oypwqq2p3rcNpp5M8+XPHDmUxMRw2J5Jw5DdAKQj8cw@mail.gmail.com>
Message-ID: <CANfBPZ-aezGCxSc5rUdU8fHxhPMQ5qx1D6zAtmwGyoBDz3YKtA@mail.gmail.com>

On Fri, Mar 2, 2012 at 12:41 PM, S, Venkatraman <svenkatr at ti.com> wrote:
> +Chris queues all MMC patches including omap_hsmmc.
> Ping ?
>
Just realized that it's already queued in mmc-next
http://git.kernel.org/?p=linux/kernel/git/cjb/mmc.git;a=commitdiff;h=25d6ba8171995230b3757c78c7470fa76a931b98


>
> On Fri, Mar 2, 2012 at 5:41 AM, Tony Lindgren <tony at atomide.com> wrote:
>> Hi,
>>
>> * Daniel Mack <zonque at gmail.com> [120217 05:13]:
>>> ping? Could anyone care for queueing this please?
>>
>> I suggest Rajendra queue up omap_hsmmc.c patches as he's already
>> patching it.
>>
>> Regards,
>>
>> Tony
>>
>>
>>> On Thu, Dec 29, 2011 at 2:22 PM, Daniel Mack <zonque at gmail.com> wrote:
>>> > On 12/23/2011 04:40 PM, T Krishnamoorthy, Balaji wrote:
>>> >> On Wed, Dec 14, 2011 at 6:52 PM, Daniel Mack <zonque at gmail.com> wrote:
>>> >>> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
>>> >>> index 101cd31..8215ef9 100644
>>> >>> --- a/drivers/mmc/host/omap_hsmmc.c
>>> >>> +++ b/drivers/mmc/host/omap_hsmmc.c
>>> >>> @@ -1927,8 +1927,12 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>>> >>> ? ? ? ?if (mmc_slot(host).vcc_aux_disable_is_sleep)
>>> >>> ? ? ? ? ? ? ? ?mmc_slot(host).no_off = 1;
>>> >>>
>>> >>> - ? ? ? mmc->f_min ? ? ?= OMAP_MMC_MIN_CLOCK;
>>> >>> - ? ? ? mmc->f_max ? ? ?= OMAP_MMC_MAX_CLOCK;
>>> >>> + ? ? ? mmc->f_min = OMAP_MMC_MIN_CLOCK;
>>> >>
>>> >> Stray change for f_min ?
>>> >
>>> > No, this was intended. The indentation doesn't make sense anymore when
>>> > not grouped with the f_max assignment.
>>> >
>>> > Other than that, what is necessary to get this picked? Tony? :)
>>> >
>>> >
>>> > Thanks,
>>> > Daniel
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at ?http://vger.kernel.org/majordomo-info.html


From t-kristo at ti.com  Fri Mar  2 04:19:00 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Fri, 2 Mar 2012 11:19:00 +0200
Subject: [PATCHv3 4/6] ARM: OMAP3 PM: Enable IO Wake up
In-Reply-To: <87sjhsdk2y.fsf@ti.com>
References: <1330525621-29836-1-git-send-email-t-kristo@ti.com>
 <1330525621-29836-5-git-send-email-t-kristo@ti.com>
 <4F4F1CBA.7040502@ti.com>  <87sjhsdk2y.fsf@ti.com>
Message-ID: <1330679940.2116.95.camel@sokoban>

On Thu, 2012-03-01 at 14:37 -0800, Kevin Hilman wrote:
> Rajendra Nayak <rnayak at ti.com> writes:
> 
> > On Wednesday 29 February 2012 07:56 PM, Tero Kristo wrote:
> >> From: Vishwanath BS<vishwanath.bs at ti.com>
> >>
> >> Enable IO Wake up for OMAP3 as part of PM Init. Currently this has been
> >> managed in cpuidle path which is not the right place. Subsequent patch
> >> will remove IO Daisy chain handling in cpuidle path once daisy chain is
> >> handled as part of hwmod mux.
> >>
> >> Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com>
> >> Tested-by: Govindraj.R<govindraj.raja at ti.com>
> >> Signed-off-by: Tero Kristo<t-kristo at ti.com>
> >> ---
> >>   arch/arm/mach-omap2/pm34xx.c |    4 ++++
> >>   1 files changed, 4 insertions(+), 0 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> >> index e97ec3f..e6c2d39 100644
> >> --- a/arch/arm/mach-omap2/pm34xx.c
> >> +++ b/arch/arm/mach-omap2/pm34xx.c
> >> @@ -793,6 +793,10 @@ static int __init omap3_pm_init(void)
> >>   		goto err1;
> >>   	}
> >>
> >> +	if (omap3_has_io_wakeup())
> >> +		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
> >> +					   PM_WKEN);
> >
> > On OMAP4 this GLOBAL IO chain enable happens as part of the trigger
> > function itself, it might make sense to do that for OMAP3 too to avoid
> > similar issues as seen on OMAP4 when the GLOBAL switch is enabled too
> > late in boot. The best however would be to get rid of it in the trigger
> > function and enable this early during PM init, but I am not sure whats
> > a good place to do this 'early' enough.
> 
> What about the subsys_initcall() that's already in the prm*.c files?
> 
> IMO, the global one-time init doesn't belong in the trigger function
> because there's no need to do the extra PRM read/write when it should be
> a one-shot init.

This sounds good to me at least, I can change the patches to work like
this, Rajendra?

-Tero



From rnayak at ti.com  Fri Mar  2 04:23:45 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 02 Mar 2012 14:53:45 +0530
Subject: [PATCHv3 4/6] ARM: OMAP3 PM: Enable IO Wake up
In-Reply-To: <1330679940.2116.95.camel@sokoban>
References: <1330525621-29836-1-git-send-email-t-kristo@ti.com>	
 <1330525621-29836-5-git-send-email-t-kristo@ti.com>	
 <4F4F1CBA.7040502@ti.com> <87sjhsdk2y.fsf@ti.com>
 <1330679940.2116.95.camel@sokoban>
Message-ID: <4F5091A1.3030802@ti.com>

On Friday 02 March 2012 02:49 PM, Tero Kristo wrote:
> On Thu, 2012-03-01 at 14:37 -0800, Kevin Hilman wrote:
>> Rajendra Nayak<rnayak at ti.com>  writes:
>>
>>> On Wednesday 29 February 2012 07:56 PM, Tero Kristo wrote:
>>>> From: Vishwanath BS<vishwanath.bs at ti.com>
>>>>
>>>> Enable IO Wake up for OMAP3 as part of PM Init. Currently this has been
>>>> managed in cpuidle path which is not the right place. Subsequent patch
>>>> will remove IO Daisy chain handling in cpuidle path once daisy chain is
>>>> handled as part of hwmod mux.
>>>>
>>>> Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com>
>>>> Tested-by: Govindraj.R<govindraj.raja at ti.com>
>>>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
>>>> ---
>>>>    arch/arm/mach-omap2/pm34xx.c |    4 ++++
>>>>    1 files changed, 4 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>>>> index e97ec3f..e6c2d39 100644
>>>> --- a/arch/arm/mach-omap2/pm34xx.c
>>>> +++ b/arch/arm/mach-omap2/pm34xx.c
>>>> @@ -793,6 +793,10 @@ static int __init omap3_pm_init(void)
>>>>    		goto err1;
>>>>    	}
>>>>
>>>> +	if (omap3_has_io_wakeup())
>>>> +		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
>>>> +					   PM_WKEN);
>>>
>>> On OMAP4 this GLOBAL IO chain enable happens as part of the trigger
>>> function itself, it might make sense to do that for OMAP3 too to avoid
>>> similar issues as seen on OMAP4 when the GLOBAL switch is enabled too
>>> late in boot. The best however would be to get rid of it in the trigger
>>> function and enable this early during PM init, but I am not sure whats
>>> a good place to do this 'early' enough.
>>
>> What about the subsys_initcall() that's already in the prm*.c files?
>>
>> IMO, the global one-time init doesn't belong in the trigger function
>> because there's no need to do the extra PRM read/write when it should be
>> a one-shot init.
>
> This sounds good to me at least, I can change the patches to work like
> this, Rajendra?

Yup, sounds good to me too. The extra PRM read/write is really an
overhead when done for every trigger. Thanks Kevin.

>
> -Tero
>



From grant.likely at secretlab.ca  Fri Mar  2 02:24:05 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 02 Mar 2012 01:24:05 -0600
Subject: [PATCH 1/8] ARM: tegra: export tegra_gpio_{en,dis}able
In-Reply-To: <1330630010-11241-2-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-2-git-send-email-alan@signal11.us>
Message-ID: <20120302072405.C11743E2D96@localhost>

On Thu,  1 Mar 2012 14:26:43 -0500, Alan Ott <alan at signal11.us> wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> These two functions are used in drivers that can be
> modules, so they need to be exported.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Grant Likely <grant.likely at secretlab.ca>

> ---
>  drivers/gpio/gpio-tegra.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
> index bdc2937..96662cc 100644
> --- a/drivers/gpio/gpio-tegra.c
> +++ b/drivers/gpio/gpio-tegra.c
> @@ -107,11 +107,13 @@ void tegra_gpio_enable(int gpio)
>  {
>  	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
>  }
> +EXPORT_SYMBOL_GPL(tegra_gpio_enable);
>  
>  void tegra_gpio_disable(int gpio)
>  {
>  	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
>  }
> +EXPORT_SYMBOL_GPL(tegra_gpio_disable);
>  
>  static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
>  {
> -- 
> 1.7.0.4
> 

-- 
email sent from notmuch.vim plugin


From grant.likely at secretlab.ca  Fri Mar  2 02:22:40 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 02 Mar 2012 01:22:40 -0600
Subject: [PATCH 4/4] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <2f29e88b98b2bcff0c241996e6d7216a60995d2d.1330625878.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2f29e88b98b2bcff0c241996e6d7216a60995d2d.1330625878.git.jason@lakedaemon.net>
Message-ID: <20120302072240.C16033E2D8D@localhost>

On Thu,  1 Mar 2012 18:20:55 +0000, Jason Cooper <jason at lakedaemon.net> wrote:
> Converted register address to a variable so that it could be set from
> fdt.  Also, pull clock frequency from fdt and clean up failure logic a
> bit.
> 
> Same as rtc-mv, this device is used in all kirkwood boards.  So, it is
> placed in kirkwood.dtsi.
> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  arch/arm/boot/dts/kirkwood.dtsi   |    6 +++++
>  arch/arm/mach-kirkwood/board-dt.c |    1 -
>  arch/arm/mach-kirkwood/common.c   |    2 +-
>  arch/arm/mach-kirkwood/common.h   |    1 -
>  drivers/watchdog/orion_wdt.c      |   44 ++++++++++++++++++++++++++----------
>  5 files changed, 39 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
> index 5fb185c..bf28424 100644
> --- a/arch/arm/boot/dts/kirkwood.dtsi
> +++ b/arch/arm/boot/dts/kirkwood.dtsi
> @@ -8,5 +8,11 @@
>  		reg = <0xf1010300 0x1f>;
>  		interrupts = <53>;
>  	};
> +
> +	wdt at fed20300 {
> +		compatible = "marvell,orion-wdt";
> +		reg = <0xfed20300 0x28>;
> +		clock-frequency = <200000000>;
> +	};
>  };
>  
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index 6fc41ae..7ef5fb7 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -135,7 +135,6 @@ static void __init kirkwood_dt_init(void)
>  #endif
>  
>  	/* internal devices that every board has */
> -	kirkwood_wdt_init();
>  	kirkwood_xor0_init();
>  	kirkwood_xor1_init();
>  	kirkwood_crypto_init();
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index 0c0375f..35dc40b 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -303,7 +303,7 @@ void __init kirkwood_xor1_init(void)
>  /*****************************************************************************
>   * Watchdog
>   ****************************************************************************/
> -void __init kirkwood_wdt_init(void)
> +static void __init kirkwood_wdt_init(void)
>  {
>  	orion_wdt_init(kirkwood_tclk);
>  }
> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
> index ca08826..ac4b2fb 100644
> --- a/arch/arm/mach-kirkwood/common.h
> +++ b/arch/arm/mach-kirkwood/common.h
> @@ -53,7 +53,6 @@ void kirkwood_restart(char, const char *);
>  
>  char *kirkwood_id(void);
>  void kirkwood_l2_init(void);
> -void kirkwood_wdt_init(void);

Similar comment here; patch undoes changes made in patch 2.

>  void kirkwood_xor0_init(void);
>  void kirkwood_xor1_init(void);
>  void kirkwood_crypto_init(void);
> diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
> index 4ad78f8..4be76ca 100644
> --- a/drivers/watchdog/orion_wdt.c
> +++ b/drivers/watchdog/orion_wdt.c
> @@ -17,6 +17,7 @@
>  #include <linux/fs.h>
>  #include <linux/miscdevice.h>
>  #include <linux/platform_device.h>
> +#include <linux/of.h>
>  #include <linux/watchdog.h>
>  #include <linux/init.h>
>  #include <linux/uaccess.h>
> @@ -28,9 +29,9 @@
>  /*
>   * Watchdog timer block registers.
>   */
> -#define TIMER_CTRL		(TIMER_VIRT_BASE + 0x0000)
> +#define TIMER_CTRL		0x0000
>  #define  WDT_EN			0x0010
> -#define WDT_VAL			(TIMER_VIRT_BASE + 0x0024)
> +#define WDT_VAL			0x0024
>  
>  #define WDT_MAX_CYCLE_COUNT	0xffffffff
>  #define WDT_IN_USE		0
> @@ -40,6 +41,7 @@ static int nowayout = WATCHDOG_NOWAYOUT;
>  static int heartbeat = -1;		/* module parameter (seconds) */
>  static unsigned int wdt_max_duration;	/* (seconds) */
>  static unsigned int wdt_tclk;
> +static unsigned int wdt_reg;
>  static unsigned long wdt_status;
>  static DEFINE_SPINLOCK(wdt_lock);
>  
> @@ -48,7 +50,7 @@ static void orion_wdt_ping(void)
>  	spin_lock(&wdt_lock);
>  
>  	/* Reload watchdog duration */
> -	writel(wdt_tclk * heartbeat, WDT_VAL);
> +	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
>  
>  	spin_unlock(&wdt_lock);
>  }
> @@ -60,7 +62,7 @@ static void orion_wdt_enable(void)
>  	spin_lock(&wdt_lock);
>  
>  	/* Set watchdog duration */
> -	writel(wdt_tclk * heartbeat, WDT_VAL);
> +	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
>  
>  	/* Clear watchdog timer interrupt */
>  	reg = readl(BRIDGE_CAUSE);
> @@ -68,9 +70,9 @@ static void orion_wdt_enable(void)
>  	writel(reg, BRIDGE_CAUSE);
>  
>  	/* Enable watchdog timer */
> -	reg = readl(TIMER_CTRL);
> +	reg = readl(wdt_reg + TIMER_CTRL);
>  	reg |= WDT_EN;
> -	writel(reg, TIMER_CTRL);
> +	writel(reg, wdt_reg + TIMER_CTRL);
>  
>  	/* Enable reset on watchdog */
>  	reg = readl(RSTOUTn_MASK);
> @@ -92,9 +94,9 @@ static void orion_wdt_disable(void)
>  	writel(reg, RSTOUTn_MASK);
>  
>  	/* Disable watchdog timer */
> -	reg = readl(TIMER_CTRL);
> +	reg = readl(wdt_reg + TIMER_CTRL);
>  	reg &= ~WDT_EN;
> -	writel(reg, TIMER_CTRL);
> +	writel(reg, wdt_reg + TIMER_CTRL);
>  
>  	spin_unlock(&wdt_lock);
>  }
> @@ -102,7 +104,7 @@ static void orion_wdt_disable(void)
>  static int orion_wdt_get_timeleft(int *time_left)
>  {
>  	spin_lock(&wdt_lock);
> -	*time_left = readl(WDT_VAL) / wdt_tclk;
> +	*time_left = readl(wdt_reg + WDT_VAL) / wdt_tclk;
>  	spin_unlock(&wdt_lock);
>  	return 0;
>  }
> @@ -236,15 +238,23 @@ static struct miscdevice orion_wdt_miscdev = {
>  static int __devinit orion_wdt_probe(struct platform_device *pdev)
>  {
>  	struct orion_wdt_platform_data *pdata = pdev->dev.platform_data;
> +	struct device_node *np = pdev->dev.of_node;
>  	int ret;
>  
> -	if (pdata) {
> +	if (pdata)
>  		wdt_tclk = pdata->tclk;
> -	} else {
> -		printk(KERN_ERR "Orion Watchdog misses platform data\n");
> +
> +	of_property_read_u32(np, "clock-frequency", &wdt_tclk);
> +
> +	if (!wdt_tclk) {
> +		printk(KERN_ERR "Orion Watchdog can't get clock freq\n");
>  		return -ENODEV;
>  	}
>  
> +	wdt_reg = TIMER_VIRT_BASE;
> +
> +	of_property_read_u32(np, "reg", &wdt_reg);
> +

Never decode 'reg' directly.  Always use platform_get_resource() for
platform devices.  That works for DT and non-DT users.

>  	if (orion_wdt_miscdev.parent)
>  		return -EBUSY;
>  	orion_wdt_miscdev.parent = &pdev->dev;
> @@ -284,6 +294,15 @@ static void orion_wdt_shutdown(struct platform_device *pdev)
>  		orion_wdt_disable();
>  }
>  
> +#ifdef CONFIG_OF
> +static struct of_device_id orion_wdt_of_match_table[] = {
> +	{ .compatible = "marvell,orion-wdt", },
> +	{},
> +};
> +#else
> +#define orion_wdt_of_match_table NULL
> +#endif
> +
>  static struct platform_driver orion_wdt_driver = {
>  	.probe		= orion_wdt_probe,
>  	.remove		= __devexit_p(orion_wdt_remove),
> @@ -291,6 +310,7 @@ static struct platform_driver orion_wdt_driver = {
>  	.driver		= {
>  		.owner	= THIS_MODULE,
>  		.name	= "orion_wdt",
> +		.of_match_table = orion_wdt_of_match_table,

of_match_ptr()

>  	},
>  };
>  
> -- 
> 1.7.3.4
> 

-- 
email sent from notmuch.vim plugin


From grant.likely at secretlab.ca  Fri Mar  2 02:09:41 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 02 Mar 2012 01:09:41 -0600
Subject: [PATCH 2/4] ARM: kirkwood: fdt: absorb kirkwood_init()
In-Reply-To: <9d9a87361c05b8b85e1ee2cdabb46a365c7abca8.1330625877.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <9d9a87361c05b8b85e1ee2cdabb46a365c7abca8.1330625877.git.jason@lakedaemon.net>
Message-ID: <20120302070941.851923E2D7B@localhost>

On Thu,  1 Mar 2012 18:20:53 +0000, Jason Cooper <jason at lakedaemon.net> wrote:
> We need to absorb kirkwood_init() into kirkwood_dt_init() so that as we
> convert drivers, we can remove the platform call, eg
> kirkwood_rtc_init().  This maintains compatibility with non-fdt
> configurations because they still call kirkwood_init() in common.c.
> 
> As drivers are converted, we will reinstate the 'static' qualifier in
> common.c.
> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  arch/arm/mach-kirkwood/board-dt.c |   30 +++++++++++++++++++++++++++++-
>  arch/arm/mach-kirkwood/common.c   |   12 ++++++------
>  arch/arm/mach-kirkwood/common.h   |    8 ++++++++
>  3 files changed, 43 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index 4960e63..a0cc28b 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -29,7 +29,9 @@
>  #include <linux/spi/orion_spi.h>
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
>  #include <mach/kirkwood.h>
> +#include <mach/bridge-regs.h>
>  #include <plat/mvsdio.h>
>  #include "common.h"
>  #include "mpp.h"
> @@ -115,7 +117,33 @@ static void __init dreamplug_init(void)
>  
>  static void __init kirkwood_dt_init(void)
>  {
> -	kirkwood_init();
> +	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
> +		kirkwood_id(), kirkwood_tclk);

Nit: pr_info()

g.


From grant.likely at secretlab.ca  Fri Mar  2 02:48:43 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 02 Mar 2012 00:48:43 -0700
Subject: linux-next: manual merge of the arm-soc tree with the gpio tree
In-Reply-To: <201203011228.33983.arnd@arndb.de>
References: <20120301164001.77a063ceed2deaf37cf68e3c@canb.auug.org.au>
 <201203011228.33983.arnd@arndb.de>
Message-ID: <20120302074843.2E45A3E2DAC@localhost>

On Thu, 1 Mar 2012 12:28:33 +0000, Arnd Bergmann <arnd at arndb.de> wrote:
> On Thursday 01 March 2012, Stephen Rothwell wrote:
> > Today's linux-next merge of the arm-soc tree got conflicts in
> > arch/arm/mach-omap1/gpio16xx.c between commit ab985f0f7c2c ("gpio/omap:
> > cleanup omap_gpio_mod_init function") from the gpio tree and commit
> > 63325ff235de ("ARM: OMAP1: Move 16xx GPIO system clock to platform init
> > code") from the arm-soc tree.
> > 
> > OK, I can't decide which is correct here - the former adds this code
> > inside the loop (even though it seems to not depend on anything in the
> > loop) and the latter adds it before.  I have used the former (but am
> > happy to be corrected).  And both commits remove the code in
> > drivers/gpio/gpio-omap.c.
> 
> Right, having the code outside of the loop seems correct to me, too.
> 
> Grant, I would suggest that I resolve this by merging the the
> omap/gpio/runtime-pm-cleanup branch (f86bcc3) that is in your
> tree into the arm-soc tree as a dependency for the omap1 stuff,
> with the resolution below.

Okay by me.

g.

> 
> 	Arnd
> 
> --- a/arch/arm/mach-omap1/gpio16xx.c
> +++ b/arch/arm/mach-omap1/gpio16xx.c
> @@@ -218,17 -225,34 +225,34 @@@ static int __init omap16xx_gpio_init(vo
>   	if (!cpu_is_omap16xx())
>   		return -EINVAL;
>   
>  +	/*
>  +	 * Enable system clock for GPIO module.
>  +	 * The CAM_CLK_CTRL *is* really the right place.
>  +	 */
>  +	omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
>  +					ULPD_CAM_CLK_CTRL);
>  +
> - 	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
> - 		platform_device_register(omap16xx_gpio_dev[i]);
> + 	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
> + 		pdev = omap16xx_gpio_dev[i];
> + 		pdata = pdev->dev.platform_data;
> + 
> + 		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + 		if (unlikely(!res)) {
> + 			dev_err(&pdev->dev, "Invalid mem resource.\n");
> + 			return -ENODEV;
> + 		}
>   
> - 	gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
> + 		base = ioremap(res->start, resource_size(res));
> + 		if (unlikely(!base)) {
> + 			dev_err(&pdev->dev, "ioremap failed.\n");
> + 			return -ENOMEM;
> + 		}
> + 
> + 		__raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG);
> + 		iounmap(base);
> + 
>  -		/*
>  -		 * Enable system clock for GPIO module.
>  -		 * The CAM_CLK_CTRL *is* really the right place.
>  -		 */
>  -		omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
>  -					ULPD_CAM_CLK_CTRL);
>  -
> + 		platform_device_register(omap16xx_gpio_dev[i]);
> + 	}
>   
>   	return 0;
>   }

-- 
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From grant.likely at secretlab.ca  Fri Mar  2 02:19:39 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 02 Mar 2012 01:19:39 -0600
Subject: [PATCH 3/4] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>
Message-ID: <20120302071939.A1BE83E2D8A@localhost>

On Thu,  1 Mar 2012 18:20:54 +0000, Jason Cooper <jason at lakedaemon.net> wrote:
> The comment at mach-kirkwood/common.c:469, says this device is in every
> kirkwood board.  So, it is placed in kirkwood.dtsi.
> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
>  arch/arm/mach-kirkwood/board-dt.c |    1 -
>  arch/arm/mach-kirkwood/common.c   |    2 +-
>  arch/arm/mach-kirkwood/common.h   |    1 -
>  drivers/rtc/rtc-mv.c              |   19 +++++++++++++++++++
>  5 files changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
> index 771c6bb..5fb185c 100644
> --- a/arch/arm/boot/dts/kirkwood.dtsi
> +++ b/arch/arm/boot/dts/kirkwood.dtsi
> @@ -2,5 +2,11 @@
>  
>  / {
>  	compatible = "marvell,kirkwood";
> +
> +	rtc at f1010300 {
> +		compatible = "marvell,rtc";
> +		reg = <0xf1010300 0x1f>;
> +		interrupts = <53>;
> +	};
>  };
>  
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index a0cc28b..6fc41ae 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -135,7 +135,6 @@ static void __init kirkwood_dt_init(void)
>  #endif
>  
>  	/* internal devices that every board has */
> -	kirkwood_rtc_init();
>  	kirkwood_wdt_init();
>  	kirkwood_xor0_init();
>  	kirkwood_xor1_init();
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index 167b6c8..0c0375f 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -163,7 +163,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
>  /*****************************************************************************
>   * SoC RTC
>   ****************************************************************************/
> -void __init kirkwood_rtc_init(void)
> +static void __init kirkwood_rtc_init(void)

This undoes the code changed in the previous patch.  If you reorder the patches then
this change goes away in both.

>  {
>  	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
>  }
> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
> index c382447..ca08826 100644
> --- a/arch/arm/mach-kirkwood/common.h
> +++ b/arch/arm/mach-kirkwood/common.h
> @@ -53,7 +53,6 @@ void kirkwood_restart(char, const char *);
>  
>  char *kirkwood_id(void);
>  void kirkwood_l2_init(void);
> -void kirkwood_rtc_init(void);
>  void kirkwood_wdt_init(void);
>  void kirkwood_xor0_init(void);
>  void kirkwood_xor1_init(void);
> diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c
> index 768e2ed..38abbf7 100644
> --- a/drivers/rtc/rtc-mv.c
> +++ b/drivers/rtc/rtc-mv.c
> @@ -12,6 +12,8 @@
>  #include <linux/bcd.h>
>  #include <linux/io.h>
>  #include <linux/platform_device.h>
> +#include <linux/of_address.h>
> +#include <linux/of.h>
>  #include <linux/delay.h>
>  #include <linux/gfp.h>
>  #include <linux/module.h>
> @@ -218,10 +220,15 @@ static int __devinit mv_rtc_probe(struct platform_device *pdev)
>  {
>  	struct resource *res;
>  	struct rtc_plat_data *pdata;
> +	struct device_node *np = pdev->dev.of_node;
>  	resource_size_t size;
>  	u32 rtc_time;
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> +	if (np)
> +		of_address_to_resource(np, 0, res);
> +

This should not be needed.  The of_platform_populate() code should have
filled the platform_device with mem resources.

>  	if (!res)
>  		return -ENODEV;
>  
> @@ -257,6 +264,8 @@ static int __devinit mv_rtc_probe(struct platform_device *pdev)
>  
>  	pdata->irq = platform_get_irq(pdev, 0);
>  
> +	of_property_read_u32(np, "interrupts", &pdata->irq);
> +

Definitely don't do this.  Same as with memory regions, the irq will be
pre-populated in the platform device resource table.  platform_get_irq()
should already work.

>  	platform_set_drvdata(pdev, pdata);
>  
>  	if (pdata->irq >= 0) {
> @@ -294,11 +303,21 @@ static int __exit mv_rtc_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +#ifdef CONFIG_OF
> +static struct of_device_id rtc_mv_of_match_table[] = {
> +	{ .compatible = "marvell,rtc", },
> +	{}
> +};
> +#else
> +#define rtc_mv_of_match_table NULL
> +#endif
> +
>  static struct platform_driver mv_rtc_driver = {
>  	.remove		= __exit_p(mv_rtc_remove),
>  	.driver		= {
>  		.name	= "rtc-mv",
>  		.owner	= THIS_MODULE,
> +		.of_match_table = rtc_mv_of_match_table,

should be:
		.of_match_table = of_match_ptr(rtc_mv_of_match_table),

that would get rid of the #else clause above.

>  	},
>  };
>  
> -- 
> 1.7.3.4
> 

-- 
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From grant.likely at secretlab.ca  Fri Mar  2 02:58:04 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 02 Mar 2012 00:58:04 -0700
Subject: [PATCH 1/4] gpiolib: Add gpiochip_find_by_name() and
 gpio_find_by_chip_name()
In-Reply-To: <20120301185524.29210.60381.stgit@kaulin.local>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185524.29210.60381.stgit@kaulin.local>
Message-ID: <20120302075804.F28DB3E2DB4@localhost>

On Thu, 01 Mar 2012 10:55:24 -0800, Tony Lindgren <tony at atomide.com> wrote:
> Currently there is no way for drivers to request a GPIO on a particular
> gpio chip. This makes it hard to support multiple GPIO controllers
> with dynamic GPIO and interrupt numbering, such as with CONFIG_SPARSE_IRQ.
> 
> Make it easier for device drivers to find GPIOs on a specific gpio_chip
> by adding two functions: gpiochip_find_by_name() and gpio_find_by_chip_name().
> 
> Note that as gpiochip_find() is already exported, we may as well
> export gpiochip_find_by_name() too.

How is the device going to know the name of the gpio controller?  I
don't particularly like interfaces that find devices by-names since
I don't think device names can be relied to be stable when devices
are instantiated from device tree data.

> 
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Signed-off-by: Tony Lindgren <tony at atomide.com>
> ---
>  drivers/gpio/gpiolib.c     |   47 ++++++++++++++++++++++++++++++++++++++++++++
>  include/asm-generic/gpio.h |    3 ++-
>  2 files changed, 49 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
> index 17fdf4b..0e5bf55 100644
> --- a/drivers/gpio/gpiolib.c
> +++ b/drivers/gpio/gpiolib.c
> @@ -1173,6 +1173,53 @@ struct gpio_chip *gpiochip_find(void *data,
>  }
>  EXPORT_SYMBOL_GPL(gpiochip_find);
>  
> +static int match_name(struct gpio_chip *chip, void *data)

Even though this is a static, please keep the prefix to avoid
namespace conflicts.  gpiochip_match_name()

> +{
> +	const char *name = data;

This is unnecessary; the void* can be passed directly to sysfs_streq...
but why is sysfs_streq being used here instead of strcmp?  This is 
not sysfs related code.

> +
> +	return sysfs_streq(name, chip->label);
> +}
> +
> +/**
> + * gpiochip_find_by_name() - iterator for locating a gpio_chip by name
> + * @name: name of the gpio_chip
> + *
> + * Similar to bus_find_device_by_name. It returns a reference to the
> + * first gpio_chip with matching name. It ignores NULL and empty names.
> + * If you need to do something more complex, then use gpiochip_find.
> + */
> +struct gpio_chip *gpiochip_find_by_name(const char *name)
> +{
> +	if (!name || !strcmp(name, ""))
> +		return NULL;
> +
> +	return gpiochip_find((void *)name, match_name);

Nasty cast.  Can the signature for gpiochip_find be changed to accept
a (const void *)?

> +}
> +EXPORT_SYMBOL_GPL(gpiochip_find_by_name);
> +
> +/**
> + * gpio_find_by_chip_name() - find a gpio on a specific gpio_chip
> + * @chip_name: name of the gpio_chip
> + * @gpio_offset: offset of the gpio on the gpio_chip
> + *
> + * Note that gpiochip_find_by_name returns the first matching
> + * gpio_chip name. For more complex matching, see gpio_find.
> + */
> +int gpio_find_by_chip_name(const char *chip_name, unsigned gpio_offset)
> +{
> +	struct gpio_chip *chip;
> +	int gpio, res;
> +
> +	chip = gpiochip_find_by_name(chip_name);
> +	if (!chip)
> +		return -ENODEV;
> +
> +	gpio = chip->base + gpio_offset;
> +
> +	return gpio;
> +}
> +EXPORT_SYMBOL_GPL(gpio_find_by_chip_name);
> +
>  /* These "optional" allocation calls help prevent drivers from stomping
>   * on each other, and help provide better diagnostics in debugfs.
>   * They're called even less than the "set direction" calls.
> diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
> index 1ff4e22..d7a2100 100644
> --- a/include/asm-generic/gpio.h
> +++ b/include/asm-generic/gpio.h
> @@ -145,7 +145,8 @@ extern int __must_check gpiochip_remove(struct gpio_chip *chip);
>  extern struct gpio_chip *gpiochip_find(void *data,
>  					int (*match)(struct gpio_chip *chip,
>  						     void *data));
> -
> +extern struct gpio_chip *gpiochip_find_by_name(const char *name);
> +extern int gpio_find_by_chip_name(const char *chip_name, unsigned gpio_offset);
>  
>  /* Always use the library code for GPIO management calls,
>   * or when sleeping may be involved.
> 

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From arnd at arndb.de  Fri Mar  2 04:48:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 09:48:11 +0000
Subject: [PATCH 3/4] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <20120302071939.A1BE83E2D8A@localhost>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>
 <20120302071939.A1BE83E2D8A@localhost>
Message-ID: <201203020948.12235.arnd@arndb.de>

On Friday 02 March 2012, Grant Likely wrote:
> > --- a/arch/arm/mach-kirkwood/common.c
> > +++ b/arch/arm/mach-kirkwood/common.c
> > @@ -163,7 +163,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
> >  /*****************************************************************************
> >   * SoC RTC
> >   ****************************************************************************/
> > -void __init kirkwood_rtc_init(void)
> > +static void __init kirkwood_rtc_init(void)
> 
> This undoes the code changed in the previous patch.  If you reorder the patches then
> this change goes away in both.
> 

That would break bisection because you end up with two rtc devices after this
patch without first moving out the kirkwood_rtc_init into board-dt.c

	Arnd


From linus.walleij at linaro.org  Fri Mar  2 05:07:23 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri,  2 Mar 2012 11:07:23 +0100
Subject: [PATCH 1/2] ARM: dts: versatile-pb/ab fix MMC IRQs
Message-ID: <1330682843-21163-1-git-send-email-linus.walleij@linaro.org>

The MMCI driver will not work without two IRQs since this is not
flagged as a single-irq variant. Looking through the complex IRQ
definition for the MMCI on the versatile (including an #if 1
statement forcing MMCI IRQ0 to the VIC) this appears to the the
correct IRQ number for both models.

Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Niklas Hernaeus <niklas.hernaeus at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/boot/dts/versatile-ab.dts |    2 +-
 arch/arm/boot/dts/versatile-pb.dts |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 0b32925..e2fe319 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -173,7 +173,7 @@
 			mmc at 5000 {
 				compatible = "arm,primecell";
 				reg = < 0x5000 0x1000>;
-				interrupts = <22>;
+				interrupts = <22 34>;
 			};
 			kmi at 6000 {
 				compatible = "arm,pl050", "arm,primecell";
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index 1664610..7e81752 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -41,7 +41,7 @@
 			mmc at b000 {
 				compatible = "arm,primecell";
 				reg = <0xb000 0x1000>;
-				interrupts = <23>;
+				interrupts = <23 34>;
 			};
 		};
 	};
-- 
1.7.7.6



From linus.walleij at linaro.org  Fri Mar  2 05:07:35 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri,  2 Mar 2012 11:07:35 +0100
Subject: [PATCH 2/2] ARM: versatile: add some auxdata for device trees
Message-ID: <1330682855-21199-1-git-send-email-linus.walleij@linaro.org>

The MMCI and PL022 SPI drivers sure need their platform data to
work on the Versatile as well. (This does not fix the auxdata for
MMCI instance mmc1 on the Versatile PB though.)

Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Niklas Hernaeus <niklas.hernaeus at linaro.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-versatile/core.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 02b7b93..d72c8ad 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -664,17 +664,18 @@ static struct amba_device *amba_devs[] __initdata = {
  * having a specific name.
  */
 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
-	OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL),
+	OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
 	OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
 	OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
 	OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
+	/* FIXME: this is buggy, the platform data is needed for this MMC instance too */
 	OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
 
 	OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
 	OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
 	OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
 	OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
-	OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL),
+	OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
 
 #if 0
 	/*
-- 
1.7.7.6



From plagnioj at jcrosoft.com  Fri Mar  2 05:03:07 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri,  2 Mar 2012 11:03:07 +0100
Subject: [PATCH 3/3 v3] spi/atmel: add DT support
In-Reply-To: <1330682587-20636-1-git-send-email-plagnioj@jcrosoft.com>
References: <1330682587-20636-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1330682587-20636-3-git-send-email-plagnioj@jcrosoft.com>

The atmel_spi use only gpio for chip select.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: spi-devel-general at lists.sourceforge.net
---
 .../devicetree/bindings/spi/spi_atmel.txt          |    6 ++++++
 drivers/spi/spi-atmel.c                            |   12 +++++++++++-
 2 files changed, 17 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
new file mode 100644
index 0000000..7ec3d8d
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -0,0 +1,6 @@
+Atmel SPI device
+
+Required properties:
+- compatible : should be "atmel,at91rm9200-spi".
+- reg: Address and length of the register set for the device
+- interrupts: Should contain macb interrupt
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 16d6a83..7bcd11f 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -19,6 +19,7 @@
 #include <linux/interrupt.h>
 #include <linux/spi/spi.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 #include <asm/io.h>
 #include <mach/board.h>
@@ -938,7 +939,7 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 
 	master->bus_num = pdev->id;
-	master->num_chipselect = 4;
+	master->num_chipselect = master->dev.of_node ? 0 : 4;
 	master->setup = atmel_spi_setup;
 	master->transfer = atmel_spi_transfer;
 	master->cleanup = atmel_spi_cleanup;
@@ -1064,11 +1065,20 @@ static int atmel_spi_resume(struct platform_device *pdev)
 #define	atmel_spi_resume	NULL
 #endif
 
+#if defined(CONFIG_OF)
+static const struct of_device_id atmel_spi_dt_ids[] = {
+	{ .compatible = "atmel,at91rm9200-spi" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
+#endif
 
 static struct platform_driver atmel_spi_driver = {
 	.driver		= {
 		.name	= "atmel_spi",
 		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(atmel_spi_dt_ids),
 	},
 	.suspend	= atmel_spi_suspend,
 	.resume		= atmel_spi_resume,
-- 
1.7.7



From plagnioj at jcrosoft.com  Fri Mar  2 05:03:06 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri,  2 Mar 2012 11:03:06 +0100
Subject: [PATCH 2/3 v3] of_spi: add generic binding support to specify ncs gpio
In-Reply-To: <1330682587-20636-1-git-send-email-plagnioj@jcrosoft.com>
References: <1330682587-20636-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1330682587-20636-2-git-send-email-plagnioj@jcrosoft.com>

This will allow to use gpio for chip select with no modification in the
driver binding

When use the ncs-gpios, the gpio number will be passed via the controller_data
and the number of chip select will automatically increased.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: spi-devel-general at lists.sourceforge.net
Cc: Grant Likely <grant.likely at secretlab.ca>
---
v3:
	use devm_kzalloc

v2:
	specify the gpio array at controller level

Best Regards,
J.
 Documentation/devicetree/bindings/spi/spi-bus.txt |    6 +++
 drivers/spi/spi.c                                 |   49 +++++++++++++++++++-
 include/linux/spi/spi.h                           |    5 ++
 3 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
index e782add..5a24729 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -12,6 +12,7 @@ The SPI master node requires the following properties:
 - #size-cells     - should be zero.
 - compatible      - name of SPI bus controller following generic names
     		recommended practice.
+- ncs-gpios       - (optional) gpios chip select.
 No other properties are required in the SPI bus node.  It is assumed
 that a driver for an SPI bus device will understand that it is an SPI bus.
 However, the binding does not attempt to define the specific method for
@@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
 chip selects.  Individual drivers can define additional properties to
 support describing the chip select layout.
 
+If ncs-gpios is used the number of chip select will automatically increased.
+
 SPI slave nodes must be children of the SPI master node and can
 contain the following properties.
 - reg             - (required) chip select address of device.
@@ -34,6 +37,9 @@ contain the following properties.
 - spi-cs-high     - (optional) Empty property indicating device requires
     		chip select active high
 
+If a gpio chipselect is used for the SPI slave the gpio number will be passed
+via the controller_data
+
 SPI example for an MPC5200 SPI bus:
 	spi at f00 {
 		#address-cells = <1>;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index e2f4ca0..f3df51f 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -28,6 +28,7 @@
 #include <linux/mod_devicetable.h>
 #include <linux/spi/spi.h>
 #include <linux/of_spi.h>
+#include <linux/of_gpio.h>
 #include <linux/pm_runtime.h>
 #include <linux/export.h>
 
@@ -339,15 +340,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
 int spi_add_device(struct spi_device *spi)
 {
 	static DEFINE_MUTEX(spi_add_lock);
-	struct device *dev = spi->master->dev.parent;
+	struct spi_master *master = spi->master;
+	struct device *dev = master->dev.parent;
 	struct device *d;
 	int status;
 
 	/* Chipselects are numbered 0..max; validate. */
-	if (spi->chip_select >= spi->master->num_chipselect) {
+	if (spi->chip_select >= master->num_chipselect) {
 		dev_err(dev, "cs%d >= max %d\n",
 			spi->chip_select,
-			spi->master->num_chipselect);
+			master->num_chipselect);
 		return -EINVAL;
 	}
 
@@ -371,6 +373,13 @@ int spi_add_device(struct spi_device *spi)
 		goto done;
 	}
 
+	if (master->num_gpio_chipselect &&
+	    spi->chip_select >= master->first_gpio_chipselect) {
+		int num = spi->chip_select - master->first_gpio_chipselect;
+
+		spi->controller_data = (void*)master->chipselect_gpios[num];
+	}
+
 	/* Drivers may modify this initial i/o setup, but will
 	 * normally rely on the device being setup.  Devices
 	 * using SPI_CS_HIGH can't coexist well otherwise...
@@ -562,6 +571,36 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
 }
 EXPORT_SYMBOL_GPL(spi_alloc_master);
 
+static int of_spi_register_master(struct spi_master *master)
+{
+	int nb, i;
+	int *cs;
+	struct device_node *np = master->dev.of_node;
+
+	if (!np)
+		return 0;
+
+	nb = of_gpio_named_count(np, "ncs-gpios");
+
+	if (nb < 1)
+		return 0;
+
+	cs = devm_kzalloc(&master->dev, sizeof(int) * nb, GFP_KERNEL);
+	master->chipselect_gpios = cs;
+
+	if (!master->chipselect_gpios)
+		return -ENOMEM;
+
+	master->first_gpio_chipselect = master->num_chipselect;
+	master->num_chipselect += nb;
+	master->num_gpio_chipselect = nb;
+
+	for (i = 0; i < nb; i++)
+		cs[i] = of_get_named_gpio(np, "ncs-gpios", i);
+
+	return 0;
+}
+
 /**
  * spi_register_master - register SPI master controller
  * @master: initialized master, originally from spi_alloc_master()
@@ -593,6 +632,10 @@ int spi_register_master(struct spi_master *master)
 	if (!dev)
 		return -ENODEV;
 
+	status = of_spi_register_master(master);
+	if (status)
+		return status;
+
 	/* even if it's just one always-selected device, there must
 	 * be at least one chipselect
 	 */
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 176fce9..d21c267 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -318,6 +318,11 @@ struct spi_master {
 
 	/* called on release() to free memory provided by spi_master */
 	void			(*cleanup)(struct spi_device *spi);
+
+	/* gpio chip select */
+	int			*chipselect_gpios;
+	int			first_gpio_chipselect;
+	int			num_gpio_chipselect;
 };
 
 static inline void *spi_master_get_devdata(struct spi_master *master)
-- 
1.7.7



From plagnioj at jcrosoft.com  Fri Mar  2 05:03:05 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri,  2 Mar 2012 11:03:05 +0100
Subject: [PATCH 1/3 v3] spi: move master of_node init to spi_alloc_master
Message-ID: <1330682587-20636-1-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: spi-devel-general at lists.sourceforge.net
Cc: Grant Likely <grant.likely at secretlab.ca>
---
 drivers/spi/spi-altera.c      |    3 ---
 drivers/spi/spi-fsl-lib.c     |    1 -
 drivers/spi/spi-imx.c         |    1 -
 drivers/spi/spi-mpc512x-psc.c |    1 -
 drivers/spi/spi-mpc52xx-psc.c |    1 -
 drivers/spi/spi-mpc52xx.c     |    1 -
 drivers/spi/spi-oc-tiny.c     |    1 -
 drivers/spi/spi-ppc4xx.c      |    1 -
 drivers/spi/spi-pxa2xx-pci.c  |    1 -
 drivers/spi/spi-pxa2xx.c      |    1 -
 drivers/spi/spi-tegra.c       |    1 -
 drivers/spi/spi-xilinx.c      |    1 -
 drivers/spi/spi.c             |    1 +
 13 files changed, 1 insertions(+), 14 deletions(-)

diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c
index c00d00e..ac6badc 100644
--- a/drivers/spi/spi-altera.c
+++ b/drivers/spi/spi-altera.c
@@ -270,9 +270,6 @@ static int __devinit altera_spi_probe(struct platform_device *pdev)
 		if (err)
 			goto exit;
 	}
-	/* find platform data */
-	if (!platp)
-		hw->bitbang.master->dev.of_node = pdev->dev.of_node;
 
 	/* register our spi controller */
 	err = spi_bitbang_start(&hw->bitbang);
diff --git a/drivers/spi/spi-fsl-lib.c b/drivers/spi/spi-fsl-lib.c
index 2674fad..810aa01 100644
--- a/drivers/spi/spi-fsl-lib.c
+++ b/drivers/spi/spi-fsl-lib.c
@@ -133,7 +133,6 @@ int mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
 
 	master->transfer = mpc8xxx_spi_transfer;
 	master->cleanup = mpc8xxx_spi_cleanup;
-	master->dev.of_node = dev->of_node;
 
 	mpc8xxx_spi = spi_master_get_devdata(master);
 	mpc8xxx_spi->dev = dev;
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index c6e697f..bebcd01 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -860,7 +860,6 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 
 	spi_imx->devtype_data->intctrl(spi_imx, 0);
 
-	master->dev.of_node = pdev->dev.of_node;
 	ret = spi_bitbang_start(&spi_imx->bitbang);
 	if (ret) {
 		dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 4c63f77..583d0c5 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -441,7 +441,6 @@ static int __devinit mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
 	master->setup = mpc512x_psc_spi_setup;
 	master->transfer = mpc512x_psc_spi_transfer;
 	master->cleanup = mpc512x_psc_spi_cleanup;
-	master->dev.of_node = dev->of_node;
 
 	tempp = ioremap(regaddr, size);
 	if (!tempp) {
diff --git a/drivers/spi/spi-mpc52xx-psc.c b/drivers/spi/spi-mpc52xx-psc.c
index 6604715..502c953 100644
--- a/drivers/spi/spi-mpc52xx-psc.c
+++ b/drivers/spi/spi-mpc52xx-psc.c
@@ -398,7 +398,6 @@ static int __devinit mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
 	master->setup = mpc52xx_psc_spi_setup;
 	master->transfer = mpc52xx_psc_spi_transfer;
 	master->cleanup = mpc52xx_psc_spi_cleanup;
-	master->dev.of_node = dev->of_node;
 
 	mps->psc = ioremap(regaddr, size);
 	if (!mps->psc) {
diff --git a/drivers/spi/spi-mpc52xx.c b/drivers/spi/spi-mpc52xx.c
index 57633d9..1a099f8 100644
--- a/drivers/spi/spi-mpc52xx.c
+++ b/drivers/spi/spi-mpc52xx.c
@@ -437,7 +437,6 @@ static int __devinit mpc52xx_spi_probe(struct platform_device *op)
 	master->setup = mpc52xx_spi_setup;
 	master->transfer = mpc52xx_spi_transfer;
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
-	master->dev.of_node = op->dev.of_node;
 
 	dev_set_drvdata(&op->dev, master);
 
diff --git a/drivers/spi/spi-oc-tiny.c b/drivers/spi/spi-oc-tiny.c
index 698018f..d030857 100644
--- a/drivers/spi/spi-oc-tiny.c
+++ b/drivers/spi/spi-oc-tiny.c
@@ -266,7 +266,6 @@ static int __devinit tiny_spi_of_probe(struct platform_device *pdev)
 		if (hw->gpio_cs[i] < 0)
 			return -ENODEV;
 	}
-	hw->bitbang.master->dev.of_node = pdev->dev.of_node;
 	val = of_get_property(pdev->dev.of_node,
 			      "clock-frequency", &len);
 	if (val && len >= sizeof(__be32))
diff --git a/drivers/spi/spi-ppc4xx.c b/drivers/spi/spi-ppc4xx.c
index 98ec532..1aa8b33 100644
--- a/drivers/spi/spi-ppc4xx.c
+++ b/drivers/spi/spi-ppc4xx.c
@@ -406,7 +406,6 @@ static int __init spi_ppc4xx_of_probe(struct platform_device *op)
 	master = spi_alloc_master(dev, sizeof *hw);
 	if (master == NULL)
 		return -ENOMEM;
-	master->dev.of_node = np;
 	dev_set_drvdata(dev, master);
 	hw = spi_master_get_devdata(master);
 	hw->master = spi_master_get(master);
diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c
index 8caa07d..5012979 100644
--- a/drivers/spi/spi-pxa2xx-pci.c
+++ b/drivers/spi/spi-pxa2xx-pci.c
@@ -90,7 +90,6 @@ static int __devinit ce4100_spi_probe(struct pci_dev *dev,
 		goto err_nomem;
 
 	pdev->dev.parent = &dev->dev;
-	pdev->dev.of_node = dev->dev.of_node;
 	ssp = &spi_info->ssp;
 	ssp->phys_base = pci_resource_start(dev, 0);
 	ssp->mmio_base = ioremap(phys_beg, phys_len);
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index dc25bee..7546f49 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1557,7 +1557,6 @@ static int __devinit pxa2xx_spi_probe(struct platform_device *pdev)
 	drv_data->ssp = ssp;
 
 	master->dev.parent = &pdev->dev;
-	master->dev.of_node = pdev->dev.of_node;
 	/* the spi->mode bits understood by this driver: */
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c
index ae6d78a..65561be 100644
--- a/drivers/spi/spi-tegra.c
+++ b/drivers/spi/spi-tegra.c
@@ -547,7 +547,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
 	tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
 	tspi->rx_dma_req.dev = tspi;
 
-	master->dev.of_node = pdev->dev.of_node;
 	ret = spi_register_master(master);
 
 	if (ret < 0)
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index 4c5a663..a7ce78f 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -392,7 +392,6 @@ struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
 
 	master->bus_num = bus_num;
 	master->num_chipselect = num_cs;
-	master->dev.of_node = dev->of_node;
 
 	xspi->mem = *mem;
 	xspi->irq = irq;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index b2ccdea..e2f4ca0 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -556,6 +556,7 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
 	master->dev.class = &spi_master_class;
 	master->dev.parent = get_device(dev);
 	spi_master_set_devdata(master, &master[1]);
+	master->dev.of_node = dev->of_node;
 
 	return master;
 }
-- 
1.7.7



From sameo at linux.intel.com  Fri Mar  2 05:25:20 2012
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Fri, 2 Mar 2012 11:25:20 +0100
Subject: [PATCH 4/4] mmc: omap_hsmmc: Simplify init for twl6030 MMC card
 detect
In-Reply-To: <20120301185535.29210.71546.stgit@kaulin.local>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185535.29210.71546.stgit@kaulin.local>
Message-ID: <20120302102520.GQ9008@sortiz-mobl>

Hi Tony,

On Thu, Mar 01, 2012 at 10:55:35AM -0800, Tony Lindgren wrote:
> There's no need to use callbacks for this, we can
> do it directly between MMC driver and twl6030.
> 
> Cc: Samuel Ortiz <sameo at linux.intel.com>
Acked-by: Samuel Ortiz <sameo at linux.intel.com>

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From festevam at gmail.com  Fri Mar  2 05:45:58 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri,  2 Mar 2012 07:45:58 -0300
Subject: [PATCH 1/2] ARM: mx5: Use common function for configuring AIPS
Message-ID: <1330685159-4137-1-git-send-email-festevam@gmail.com>

Now that a common imx_set_aips() function is available, use it on mx51 and mx53.

This lets the code smaller and cleaner.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-imx/cpu-imx5.c |   36 ------------------------------------
 arch/arm/mach-imx/mm-imx5.c  |    8 ++++++++
 2 files changed, 8 insertions(+), 36 deletions(-)

diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index 5e2e7a8..aa15c51 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -149,39 +149,3 @@ int mx50_revision(void)
 	return mx5_cpu_rev;
 }
 EXPORT_SYMBOL(mx50_revision);
-
-static int __init post_cpu_init(void)
-{
-	unsigned int reg;
-	void __iomem *base;
-
-	if (cpu_is_mx51() || cpu_is_mx53()) {
-		if (cpu_is_mx51())
-			base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
-		else
-			base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
-
-		__raw_writel(0x0, base + 0x40);
-		__raw_writel(0x0, base + 0x44);
-		__raw_writel(0x0, base + 0x48);
-		__raw_writel(0x0, base + 0x4C);
-		reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-		__raw_writel(reg, base + 0x50);
-
-		if (cpu_is_mx51())
-			base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
-		else
-			base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
-
-		__raw_writel(0x0, base + 0x40);
-		__raw_writel(0x0, base + 0x44);
-		__raw_writel(0x0, base + 0x48);
-		__raw_writel(0x0, base + 0x4C);
-		reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-		__raw_writel(reg, base + 0x50);
-	}
-
-	return 0;
-}
-
-postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 49549a7..8543ffb 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -185,6 +185,10 @@ void __init imx51_soc_init(void)
 
 	/* i.mx51 has the i.mx35 type sdma */
 	imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
+
+	/* Setup AIPS registers */
+	imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
+	imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
 }
 
 void __init imx53_soc_init(void)
@@ -200,4 +204,8 @@ void __init imx53_soc_init(void)
 
 	/* i.mx53 has the i.mx35 type sdma */
 	imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
+
+	/* Setup AIPS registers */
+	imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
+	imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
 }
-- 
1.7.1



From festevam at gmail.com  Fri Mar  2 05:45:59 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri,  2 Mar 2012 07:45:59 -0300
Subject: [PATCH 2/2] ARM: mx35: Setup the AIPS registers
In-Reply-To: <1330685159-4137-1-git-send-email-festevam@gmail.com>
References: <1330685159-4137-1-git-send-email-festevam@gmail.com>
Message-ID: <1330685159-4137-2-git-send-email-festevam@gmail.com>

Setup the AIPS registers on mx35.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-imx/mm-imx3.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 77cf553..cc8a707 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -260,5 +260,9 @@ void __init imx35_soc_init(void)
 	}
 
 	imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
+
+	/* Setup AIPS registers */
+	imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
+	imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
 }
 #endif /* ifdef CONFIG_SOC_IMX35 */
-- 
1.7.1



From paul at pwsan.com  Fri Mar  2 05:46:47 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 2 Mar 2012 03:46:47 -0700 (MST)
Subject: [PATCH-V2 2/2] arm:omap:am33xx: Add power domain data
In-Reply-To: <79CD15C6BA57404B839C016229A409A8317E6763@DBDE01.ent.ti.com>
References: <1324803628-16790-1-git-send-email-hvaibhav@ti.com>
 <1324803628-16790-3-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1202291839130.12752@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A8317E515D@DBDE01.ent.ti.com>
 <alpine.DEB.2.00.1203012330490.22980@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A8317E6763@DBDE01.ent.ti.com>
Message-ID: <alpine.DEB.2.00.1203020337330.15424@utopia.booyaka.com>

Hi

On Fri, 2 Mar 2012, Hiremath, Vaibhav wrote:

> Paul,
> Thanks for your review comments, can we also align on the approach, 
> Whether to merge am33xx powerdomain with omap4 (same direction we are now)
> OR
> Have separate implementation (my original approach).

Could you please take a look at the "am335x_prcm_devel_3.4" branch on 
git://git.pwsan.com/linux-2.6 and let me know what you think?

It is still rough, incomplete, and compile-tested only; and the patch 
commit messages have to be updated and revised; but I think it is a 
slightly better approach.

A significant change is that the prminst code changes have been removed.  
That is only needed when PRM registers are spread across multiple PRCM IP 
blocks.  This does not appear to be the case with AM33xx?  So the 
implementation has been modified to create a prm33xx.c file instead.  
This avoids an extra, unnecessary layer of indirection for PRM accesses.

This, along with the other differences between OMAP4 and this chip, means 
that a separate powerdomain33xx.c file had to be created.

The powerdomains33xx_data.c file is still missing the bitmask position 
data, but the structure members are there.

Feel free to combine, rework, or merge this series with what you are 
working on if you feel that it is a good approach.  Otherwise, let's 
discuss.


- Paul


From paul at pwsan.com  Fri Mar  2 05:52:17 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 2 Mar 2012 03:52:17 -0700 (MST)
Subject: [PATCH-V3 2/3] ARM: OMAP4: prminst: Add boot time __init function
 for prminst
In-Reply-To: <1328269436-18668-3-git-send-email-hvaibhav@ti.com>
References: <1328269436-18668-1-git-send-email-hvaibhav@ti.com>
 <1328269436-18668-3-git-send-email-hvaibhav@ti.com>
Message-ID: <alpine.DEB.2.00.1203020348460.15424@utopia.booyaka.com>

Hi

On Fri, 3 Feb 2012, Vaibhav Hiremath wrote:

> AM33xx PRM module is closer to OMAP4 PRM module, and
> in order to reuse prminst api's we have to address
> some of the differences like, base addresses and partitions.
> Unlike OMAP4 PRM, AM33xx doesn't have any partitions and
> maintains single partition.
> 
> So, in order to reuse the existing OMAP4 prminst code
> for AM33xx this patch adds,
> 
>   - Boot time __init function, to initialize _prm_bases
>     based on cpu_is_xxx
>   - Instead of maintaining phy addr for PRM partition
>     in _prm_bases[] table and then changing it to virt addr,
>     directly maintain respective virt addr.

So as was mentioned in another thread, the prminst code is really for 
cases where there are PRM registers split across multiple IP blocks.  So 
far this doesn't appear to the case with AM33xx.  A better approach is 
probably to create a prm33xx.c, as was done in the branch that was 
mentioned in my last message.

Another problem with this patch is that it causes a large number of 
warnings from sparse -- the type casts aren't right or are missing. Please 
make sure that your patches don't add any sparse warnings before posting.  
You can do this with 'make C=2' assuming that you have sparse installed.


- Paul


From r.sricharan at ti.com  Fri Mar  2 06:01:18 2012
From: r.sricharan at ti.com (R Sricharan)
Date: Fri, 2 Mar 2012 16:31:18 +0530
Subject: [PATCH] ARM: OMAP2+: Fix module build errors with
 CONFIG_OMAP4_ERRATA_I688
Message-ID: <1330686078-9478-1-git-send-email-r.sricharan@ti.com>

While building modules with randconfig the below errors are observed.

ERROR: "omap_bus_sync" [drivers/watchdog/sp805_wdt.ko] undefined!
ERROR: "omap_bus_sync" [drivers/watchdog/dw_wdt.ko] undefined!
ERROR: "omap_bus_sync" [drivers/virtio/virtio_ring.ko] undefined!
ERROR: "omap_bus_sync" [drivers/video/sm501fb.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/mon/usbmon.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/sl811-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/ohci-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/isp1760.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/isp1362-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/host/isp116x-hcd.ko] undefined!
ERROR: "omap_bus_sync" [drivers/usb/core/usbcore.ko] undefined!
ERROR: "omap_bus_sync" [drivers/tty/serial/altera_uart.ko] undefined!
ERROR: "omap_bus_sync" [drivers/tty/serial/altera_jtaguart.ko] undefined!
ERROR: "omap_bus_sync" [drivers/tty/serial/8250/8250_dw.ko] undefined!
ERROR: "omap_bus_sync" [drivers/ssb/ssb.ko] undefined!
ERROR: "omap_bus_sync" [drivers/rtc/rtc-cmos.ko] undefined!
ERROR: "omap_bus_sync" [drivers/rtc/rtc-bq4802.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mtd/nand/tmio_nand.ko] undefined!
ERROR: "omap_bus_sync" [drivers/mtd/nand/omap2.ko] undefined!

Signed-off-by: R Sricharan <r.sricharan at ti.com>
---
 arch/arm/mach-omap2/omap4-common.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index ebc5950..70de277 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -31,6 +31,7 @@
 
 #include "common.h"
 #include "omap4-sar-layout.h"
+#include <linux/export.h>
 
 #ifdef CONFIG_CACHE_L2X0
 static void __iomem *l2cache_base;
@@ -55,6 +56,7 @@ void omap_bus_sync(void)
 		isb();
 	}
 }
+EXPORT_SYMBOL(omap_bus_sync);
 
 /* Steal one page physical memory for barrier implementation */
 int __init omap_barrier_reserve_memblock(void)
-- 
1.7.1



From m.szyprowski at samsung.com  Fri Mar  2 06:07:59 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 02 Mar 2012 12:07:59 +0100
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <CAHQjnOO5DLOj8Fw=ZriSnXg8W3k7y8Dnu--Peqe6JJX0xGMhoQ@mail.gmail.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <CAHQjnOO5DLOj8Fw=ZriSnXg8W3k7y8Dnu--Peqe6JJX0xGMhoQ@mail.gmail.com>
Message-ID: <015101ccf864$bacb1070$30613150$%szyprowski@samsung.com>

Hello,

On Friday, March 02, 2012 9:06 AM KyongHo Cho wrote:

> On Thu, Mar 1, 2012 at 12:04 AM, Marek Szyprowski
> <m.szyprowski at samsung.com> wrote:
> > +/**
> > + * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
> > + * @dev: valid struct device pointer
> > + * @sg: list of buffers
> > + * @nents: number of buffers to map
> > + * @dir: DMA transfer direction
> > + *
> > + * Map a set of buffers described by scatterlist in streaming mode for DMA.
> > + * The scatter gather list elements are merged together (if possible) and
> > + * tagged with the appropriate dma address and length. They are obtained via
> > + * sg_dma_{address,length}.
> > + */
> > +int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
> > + ? ? ? ? ? ? ? ? ? ?enum dma_data_direction dir, struct dma_attrs *attrs)
> > +{
> > + ? ? ? struct scatterlist *s = sg, *dma = sg, *start = sg;
> > + ? ? ? int i, count = 0;
> > + ? ? ? unsigned int offset = s->offset;
> > + ? ? ? unsigned int size = s->offset + s->length;
> > + ? ? ? unsigned int max = dma_get_max_seg_size(dev);
> > +
> > + ? ? ? for (i = 1; i < nents; i++) {
> > + ? ? ? ? ? ? ? s->dma_address = ARM_DMA_ERROR;
> > + ? ? ? ? ? ? ? s->dma_length = 0;
> > +
> > + ? ? ? ? ? ? ? s = sg_next(s);
> > +
> > + ? ? ? ? ? ? ? if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
> > + ? ? ? ? ? ? ? ? ? ? ? if (__map_sg_chunk(dev, start, size, &dma->dma_address,
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? dir) < 0)
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? goto bad_mapping;
> > +
> > + ? ? ? ? ? ? ? ? ? ? ? dma->dma_address += offset;
> > + ? ? ? ? ? ? ? ? ? ? ? dma->dma_length = size - offset;
> > +
> > + ? ? ? ? ? ? ? ? ? ? ? size = offset = s->offset;
> > + ? ? ? ? ? ? ? ? ? ? ? start = s;
> > + ? ? ? ? ? ? ? ? ? ? ? dma = sg_next(dma);
> > + ? ? ? ? ? ? ? ? ? ? ? count += 1;
> > + ? ? ? ? ? ? ? }
> > + ? ? ? ? ? ? ? size += s->length;
> > + ? ? ? }
> > + ? ? ? if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir) < 0)
> > + ? ? ? ? ? ? ? goto bad_mapping;
> > +
> > + ? ? ? dma->dma_address += offset;
> > + ? ? ? dma->dma_length = size - offset;
> > +
> > + ? ? ? return count+1;
> > +
> > +bad_mapping:
> > + ? ? ? for_each_sg(sg, s, count, i)
> > + ? ? ? ? ? ? ? __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
> > + ? ? ? return 0;
> > +}
> > +
> This looks that the given sg list specifies the list of physical
> memory chunks and
> the list of IO virtual memory chunks at the same time after calling
> arm_dma_map_sg().
> It can happen that dma_address and dma_length of a sg entry does not
> correspond to
> physical memory information of the sg entry.

Right, that's how it is designed. If fact sg entries describes 2 independent 
lists - one for physical memory chunks and one for virtual memory chunks. 
It might happen that the whole scattered physical memory can be mapped into
contiguous virtual memory chunk, what result in only one element describing
the io dma addresses. Here is the respective paragraph from 
Documentation/DMA-API-HOWTO.txt (lines 511-517):

'The implementation is free to merge several consecutive sglist entries
into one (e.g. if DMA mapping is done with PAGE_SIZE granularity, any
consecutive sglist entries can be merged into one provided the first one
ends and the second one starts on a page boundary - in fact this is a huge
advantage for cards which either cannot do scatter-gather or have very
limited number of scatter-gather entries) and returns the actual number
of sg entries it mapped them to. On failure 0 is returned.'

> I think it is beneficial for handling IO virtual memory.
> 
> However, I worry about any other problems caused by a single sg entry contains
> information from 2 different context.

What do you mean by the 'context'. DMA mapping assumes that a single call to 
dma_map_sg maps a single memory buffer.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From sshtylyov at mvista.com  Fri Mar  2 06:40:23 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 02 Mar 2012 15:40:23 +0400
Subject: [PATCH 4/8] ARM: tegra: build localtimer support only when needed
In-Reply-To: <1330630010-11241-5-git-send-email-alan@signal11.us>
References: <1330630010-11241-1-git-send-email-alan@signal11.us>
 <1330630010-11241-5-git-send-email-alan@signal11.us>
Message-ID: <4F50B1A7.60207@ru.mvista.com>

Hello.

On 01-03-2012 23:26, Alan Ott wrote:

> From: Arnd Bergmann<arnd at arndb.de>

> It is possible to build a tegra kernel without localtimer
> support, so the tegra specific parts should only be built
> when that is indeed enabled.

> Signed-off-by: Arnd Bergmann<arnd at arndb.de>
> ---
>   arch/arm/mach-tegra/Makefile |    3 ++-
>   1 files changed, 2 insertions(+), 1 deletions(-)

> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> index e120ff5..a956df8 100644
> --- a/arch/arm/mach-tegra/Makefile
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -13,7 +13,8 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
>   obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-tegra20-tables.o
>   obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= pinmux-tegra30-tables.o
>   obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
> -obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
> +obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o

   Could use the chance to indent here with tabs instead of spaces, like below.

> +obj-$(CONFIG_LOCAL_TIMERS)		+= localtimer.o

WBR, Sergei


From santosh.shilimkar at ti.com  Fri Mar  2 06:46:29 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 2 Mar 2012 17:16:29 +0530
Subject: Randconfig module build error with OMAP4_ERRATA_I688
In-Reply-To: <20120301162556.GY18901@atomide.com>
References: <20120229173719.GN18901@atomide.com>
 <CAMQu2gxg_57AVW+MT_Sgi+gr2OUge-YPdSUxoG+z-zQth=4-UA@mail.gmail.com>
 <20120301162556.GY18901@atomide.com>
Message-ID: <CAMQu2gy9XksJ+8Q_Ygwtx7n2tVfd2KCu0o54SisuV8_QUX_rUQ@mail.gmail.com>

On Thu, Mar 1, 2012 at 9:55 PM, Tony Lindgren <tony at atomide.com> wrote:
> * Shilimkar, Santosh <santosh.shilimkar at ti.com> [120301 00:38]:
>> On Wed, Feb 29, 2012 at 11:07 PM, Tony Lindgren <tony at atomide.com> wrote:
>> > Hi Santosh,
>> >
>> > Looks like OMAP4_ERRATA_I688 still has one more issue:
>> > Modules won't build at least with the attached randconfig
>> > generated file.
>> >
>> > Can you please take a look at how to deal with it?
>> >
>> > Maybe omap_bus_sync should be an inline function with some
>> > wrapper for the sleep44xx.S to call?
>> >
>> > I already posted a fix for the GPMC related error with the
>> > same .config file.
>> >
>> This one builds for me against 'Linux 3.3-rc5,
>> Ofocurse I got below error with the attached .config which
>> I bypassed to see the Errata build failure.
>>
>> arch/arm/mach-omap2/built-in.o: In function `n8x0_mmc_callback':
>> linux-2.6/arch/arm/mach-omap2/board-n8x0.c:374: undefined reference to
>> `omap_mmc_notify_cover_event'
>> make: *** [.tmp_vmlinux1] Error 1
>
> Yes a fix for that has been queued already.
>
>> I build this with below toolchain...
>> $arm-none-linux-gnueabi-gcc --version
>> arm-none-linux-gnueabi-gcc (Sourcery G++ Lite 2011.03-41) 4.5.2
>> Copyright (C) 2010 Free Software Foundation, Inc.
>>
>> Am I missing anything ?
>
> I think you're missing your commit 2ec1fc4e169acc0b8d6733ff028fd52e766773d9
> (ARM: OMAP4: Move the barrier memboclk_steal() as part of reserve callback)
> thats' queued up in fixes, and CONFIG_OMAP4_ERRATA_I688=y.
>
> Then with -rc5 + 2ec1fc4e when you build modules you'll get this:
>
> ERROR: "omap_bus_sync" [drivers/watchdog/sp805_wdt.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/watchdog/dw_wdt.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/virtio/virtio_ring.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/video/sm501fb.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/mon/usbmon.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/host/sl811-hcd.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/host/ohci-hcd.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/host/isp1760.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/host/isp1362-hcd.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/host/isp116x-hcd.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/core/usbcore.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/tty/serial/altera_uart.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/tty/serial/altera_jtaguart.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/tty/serial/8250/8250_dw.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/ssb/ssb.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/rtc/rtc-cmos.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/rtc/rtc-bq4802.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/mtd/nand/tmio_nand.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/mtd/nand/omap2.ko] undefined!
>
Sricharan has posted a fix for it. [1]
The sleep code stuff is just dummy function for the cases when the errata
is not defined. When Errata is defined the generic barriers too get impacted
and hence the function needs to be exported.

Regards
Santosh
[1] http://www.spinics.net/lists/arm-kernel/msg162608.html


From heiko at sntech.de  Fri Mar  2 07:55:21 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Fri, 2 Mar 2012 13:55:21 +0100
Subject: [PATCH 0/2] Remove bq24022 driver superseeded by gpio-regulator
Message-ID: <201203021355.21669.heiko@sntech.de>

The bq24022 regulator is simply a more specialised variant of the now
present gpio-regulator. Therefore it probably shouldn't stay around.

This series converts the two users of bq24022 pxa/hx4700 and
pxa/magician to use the gpio-regulator instead, and after this removes
the then unused bq24022 driver.

The series was compile-tested only, but the gpio-regulator itself is
sucessfully used on my platform for the dcdc3 of a tps650240 (voltage
regulator with one gpio) and for a bq24075 (current regulator with two
gpios). So I'm quite sure it should work correctly but would welcome
testers :-) .

Heiko Stuebner (2):
  pxa: magician/hx4700: Convert to gpio-regulator from bq24022
  regulator: Remove bq24022 regulator driver

 arch/arm/configs/magician_defconfig |    2 +-
 arch/arm/mach-pxa/hx4700.c          |   33 ++++++--
 arch/arm/mach-pxa/magician.c        |   33 ++++++--
 drivers/regulator/Kconfig           |    8 --
 drivers/regulator/Makefile          |    1 -
 drivers/regulator/bq24022.c         |  162 -----------------------------------
 include/linux/regulator/bq24022.h   |   24 -----
 7 files changed, 55 insertions(+), 208 deletions(-)
 delete mode 100644 drivers/regulator/bq24022.c
 delete mode 100644 include/linux/regulator/bq24022.h

-- 
1.7.5.4



From heiko at sntech.de  Fri Mar  2 07:56:38 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Fri, 2 Mar 2012 13:56:38 +0100
Subject: [PATCH 1/2] pxa: magician/hx4700: Convert to gpio-regulator from
 bq24022
In-Reply-To: <201203021355.21669.heiko@sntech.de>
References: <201203021355.21669.heiko@sntech.de>
Message-ID: <201203021356.38857.heiko@sntech.de>

The bq24022 on these machines is a very simple regulator using gpios.
One provides the on/off functionality and a second one is used to
change the current between 100 and 500 mA.

This functionality can also be provided by the more generic gpio-regulator.

Therefore convert both machines which makes it possible to remove the
bq24022 driver later on.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/configs/magician_defconfig |    2 +-
 arch/arm/mach-pxa/hx4700.c          |   33 +++++++++++++++++++++++++++------
 arch/arm/mach-pxa/magician.c        |   33 +++++++++++++++++++++++++++------
 3 files changed, 55 insertions(+), 13 deletions(-)

diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
index 443675d..a691ef4 100644
--- a/arch/arm/configs/magician_defconfig
+++ b/arch/arm/configs/magician_defconfig
@@ -101,7 +101,7 @@ CONFIG_MFD_ASIC3=y
 CONFIG_HTC_EGPIO=y
 CONFIG_HTC_PASIC3=y
 CONFIG_REGULATOR=y
-CONFIG_REGULATOR_BQ24022=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_FB=y
 CONFIG_FB_PXA=y
 CONFIG_FB_PXA_OVERLAY=y
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index f2c23ea..7571f0d 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -28,7 +28,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
-#include <linux/regulator/bq24022.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/max1586.h>
 #include <linux/spi/ads7846.h>
@@ -698,14 +699,34 @@ static struct regulator_init_data bq24022_init_data = {
 	.consumer_supplies      = bq24022_consumers,
 };
 
-static struct bq24022_mach_info bq24022_info = {
-	.gpio_nce   = GPIO72_HX4700_BQ24022_nCHARGE_EN,
-	.gpio_iset2 = GPIO96_HX4700_BQ24022_ISET2,
-	.init_data  = &bq24022_init_data,
+static struct gpio bq24022_gpios[] = {
+	{ GPIO96_HX4700_BQ24022_ISET2, GPIOF_OUT_INIT_LOW, "bq24022_iset2" },
+};
+
+static struct gpio_regulator_state bq24022_states[] = {
+	{ .value = 100000, .gpios = (0 << 0) },
+	{ .value = 500000, .gpios = (1 << 0) },
+};
+
+static struct gpio_regulator_config bq24022_info = {
+	.supply_name = "bq24022",
+
+	.enable_gpio = GPIO72_HX4700_BQ24022_nCHARGE_EN,
+	.enable_high = 0,
+	.enabled_at_boot = 0,
+
+	.gpios = bq24022_gpios,
+	.nr_gpios = ARRAY_SIZE(bq24022_gpios),
+
+	.states = bq24022_states,
+	.nr_states = ARRAY_SIZE(bq24022_states),
+
+	.type = REGULATOR_CURRENT,
+	.init_data = &bq24022_init_data,
 };
 
 static struct platform_device bq24022 = {
-	.name = "bq24022",
+	.name = "gpio-regulator",
 	.id   = -1,
 	.dev  = {
 		.platform_data = &bq24022_info,
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 3d6baf9..5e26f3e 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -25,7 +25,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
-#include <linux/regulator/bq24022.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/usb/gpio_vbus.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -596,14 +597,34 @@ static struct regulator_init_data bq24022_init_data = {
 	.consumer_supplies      = bq24022_consumers,
 };
 
-static struct bq24022_mach_info bq24022_info = {
-	.gpio_nce   = GPIO30_MAGICIAN_BQ24022_nCHARGE_EN,
-	.gpio_iset2 = EGPIO_MAGICIAN_BQ24022_ISET2,
-	.init_data  = &bq24022_init_data,
+static struct gpio bq24022_gpios[] = {
+	{ EGPIO_MAGICIAN_BQ24022_ISET2, GPIOF_OUT_INIT_LOW, "bq24022_iset2" },
+};
+
+static struct gpio_regulator_state bq24022_states[] = {
+	{ .value = 100000, .gpios = (0 << 0) },
+	{ .value = 500000, .gpios = (1 << 0) },
+};
+
+static struct gpio_regulator_config bq24022_info = {
+	.supply_name = "bq24022",
+
+	.enable_gpio = GPIO30_MAGICIAN_BQ24022_nCHARGE_EN,
+	.enable_high = 0,
+	.enabled_at_boot = 0,
+
+	.gpios = bq24022_gpios,
+	.nr_gpios = ARRAY_SIZE(bq24022_gpios),
+
+	.states = bq24022_states,
+	.nr_states = ARRAY_SIZE(bq24022_states),
+
+	.type = REGULATOR_CURRENT,
+	.init_data = &bq24022_init_data,
 };
 
 static struct platform_device bq24022 = {
-	.name = "bq24022",
+	.name = "gpio-regulator",
 	.id   = -1,
 	.dev  = {
 		.platform_data = &bq24022_info,
-- 
1.7.5.4



From heiko at sntech.de  Fri Mar  2 07:57:44 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Fri, 2 Mar 2012 13:57:44 +0100
Subject: [PATCH 2/2] regulator: Remove bq24022 regulator driver
In-Reply-To: <201203021355.21669.heiko@sntech.de>
References: <201203021355.21669.heiko@sntech.de>
Message-ID: <201203021357.44770.heiko@sntech.de>

The bq24022 driver is just a specialised form of a gpio-regulator.

As all former users of it now use the gpio-regulator directly, there
is no need to keep it around.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 drivers/regulator/Kconfig         |    8 --
 drivers/regulator/Makefile        |    1 -
 drivers/regulator/bq24022.c       |  162 -------------------------------------
 include/linux/regulator/bq24022.h |   24 ------
 4 files changed, 0 insertions(+), 195 deletions(-)
 delete mode 100644 drivers/regulator/bq24022.c
 delete mode 100644 include/linux/regulator/bq24022.h

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index c733df5..25cfe1c 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -250,14 +250,6 @@ config REGULATOR_DB8500_PRCMU
 	  This driver supports the voltage domain regulators controlled by the
 	  DB8500 PRCMU
 
-config REGULATOR_BQ24022
-	tristate "TI bq24022 Dual Input 1-Cell Li-Ion Charger IC"
-	help
-	  This driver controls a TI bq24022 Charger attached via
-	  GPIOs. The provided current regulator can enable/disable
-	  charging select between 100 mA and 500 mA charging current
-	  limit.
-
 config REGULATOR_TPS6105X
 	tristate "TI TPS6105X Power regulators"
 	depends on TPS6105X
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index cf0934b..1339198 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
 obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
 obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
 obj-$(CONFIG_REGULATOR_AD5398) += ad5398.o
-obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o
 obj-$(CONFIG_REGULATOR_DA903X)	+= da903x.o
 obj-$(CONFIG_REGULATOR_DA9052)	+= da9052-regulator.o
 obj-$(CONFIG_REGULATOR_DBX500_PRCMU) += dbx500-prcmu.o
diff --git a/drivers/regulator/bq24022.c b/drivers/regulator/bq24022.c
deleted file mode 100644
index 9fab6d1..0000000
--- a/drivers/regulator/bq24022.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Support for TI bq24022 (bqTINY-II) Dual Input (USB/AC Adpater)
- * 1-Cell Li-Ion Charger connected via GPIOs.
- *
- * Copyright (c) 2008 Philipp Zabel
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <linux/module.h>
-#include <linux/gpio.h>
-#include <linux/regulator/bq24022.h>
-#include <linux/regulator/driver.h>
-
-
-static int bq24022_set_current_limit(struct regulator_dev *rdev,
-					int min_uA, int max_uA)
-{
-	struct bq24022_mach_info *pdata = rdev_get_drvdata(rdev);
-
-	dev_dbg(rdev_get_dev(rdev), "setting current limit to %s mA\n",
-		max_uA >= 500000 ? "500" : "100");
-
-	/* REVISIT: maybe return error if min_uA != 0 ? */
-	gpio_set_value(pdata->gpio_iset2, max_uA >= 500000);
-	return 0;
-}
-
-static int bq24022_get_current_limit(struct regulator_dev *rdev)
-{
-	struct bq24022_mach_info *pdata = rdev_get_drvdata(rdev);
-
-	return gpio_get_value(pdata->gpio_iset2) ? 500000 : 100000;
-}
-
-static int bq24022_enable(struct regulator_dev *rdev)
-{
-	struct bq24022_mach_info *pdata = rdev_get_drvdata(rdev);
-
-	dev_dbg(rdev_get_dev(rdev), "enabling charger\n");
-
-	gpio_set_value(pdata->gpio_nce, 0);
-	return 0;
-}
-
-static int bq24022_disable(struct regulator_dev *rdev)
-{
-	struct bq24022_mach_info *pdata = rdev_get_drvdata(rdev);
-
-	dev_dbg(rdev_get_dev(rdev), "disabling charger\n");
-
-	gpio_set_value(pdata->gpio_nce, 1);
-	return 0;
-}
-
-static int bq24022_is_enabled(struct regulator_dev *rdev)
-{
-	struct bq24022_mach_info *pdata = rdev_get_drvdata(rdev);
-
-	return !gpio_get_value(pdata->gpio_nce);
-}
-
-static struct regulator_ops bq24022_ops = {
-	.set_current_limit = bq24022_set_current_limit,
-	.get_current_limit = bq24022_get_current_limit,
-	.enable            = bq24022_enable,
-	.disable           = bq24022_disable,
-	.is_enabled        = bq24022_is_enabled,
-};
-
-static struct regulator_desc bq24022_desc = {
-	.name  = "bq24022",
-	.ops   = &bq24022_ops,
-	.type  = REGULATOR_CURRENT,
-	.owner = THIS_MODULE,
-};
-
-static int __init bq24022_probe(struct platform_device *pdev)
-{
-	struct bq24022_mach_info *pdata = pdev->dev.platform_data;
-	struct regulator_dev *bq24022;
-	int ret;
-
-	if (!pdata || !pdata->gpio_nce || !pdata->gpio_iset2)
-		return -EINVAL;
-
-	ret = gpio_request(pdata->gpio_nce, "ncharge_en");
-	if (ret) {
-		dev_dbg(&pdev->dev, "couldn't request nCE GPIO: %d\n",
-			pdata->gpio_nce);
-		goto err_ce;
-	}
-	ret = gpio_request(pdata->gpio_iset2, "charge_mode");
-	if (ret) {
-		dev_dbg(&pdev->dev, "couldn't request ISET2 GPIO: %d\n",
-			pdata->gpio_iset2);
-		goto err_iset2;
-	}
-	ret = gpio_direction_output(pdata->gpio_iset2, 0);
-	ret = gpio_direction_output(pdata->gpio_nce, 1);
-
-	bq24022 = regulator_register(&bq24022_desc, &pdev->dev,
-				     pdata->init_data, pdata, NULL);
-	if (IS_ERR(bq24022)) {
-		dev_dbg(&pdev->dev, "couldn't register regulator\n");
-		ret = PTR_ERR(bq24022);
-		goto err_reg;
-	}
-	platform_set_drvdata(pdev, bq24022);
-	dev_dbg(&pdev->dev, "registered regulator\n");
-
-	return 0;
-err_reg:
-	gpio_free(pdata->gpio_iset2);
-err_iset2:
-	gpio_free(pdata->gpio_nce);
-err_ce:
-	return ret;
-}
-
-static int __devexit bq24022_remove(struct platform_device *pdev)
-{
-	struct bq24022_mach_info *pdata = pdev->dev.platform_data;
-	struct regulator_dev *bq24022 = platform_get_drvdata(pdev);
-
-	regulator_unregister(bq24022);
-	gpio_free(pdata->gpio_iset2);
-	gpio_free(pdata->gpio_nce);
-
-	return 0;
-}
-
-static struct platform_driver bq24022_driver = {
-	.driver = {
-		.name = "bq24022",
-	},
-	.remove = __devexit_p(bq24022_remove),
-};
-
-static int __init bq24022_init(void)
-{
-	return platform_driver_probe(&bq24022_driver, bq24022_probe);
-}
-
-static void __exit bq24022_exit(void)
-{
-	platform_driver_unregister(&bq24022_driver);
-}
-
-module_init(bq24022_init);
-module_exit(bq24022_exit);
-
-MODULE_AUTHOR("Philipp Zabel");
-MODULE_DESCRIPTION("TI bq24022 Li-Ion Charger driver");
-MODULE_LICENSE("GPL");
diff --git a/include/linux/regulator/bq24022.h b/include/linux/regulator/bq24022.h
deleted file mode 100644
index a6d0140..0000000
--- a/include/linux/regulator/bq24022.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Support for TI bq24022 (bqTINY-II) Dual Input (USB/AC Adpater)
- * 1-Cell Li-Ion Charger connected via GPIOs.
- *
- * Copyright (c) 2008 Philipp Zabel
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-struct regulator_init_data;
-
-/**
- * bq24022_mach_info - platform data for bq24022
- * @gpio_nce: GPIO line connected to the nCE pin, used to enable / disable charging
- * @gpio_iset2: GPIO line connected to the ISET2 pin, used to limit charging current to 100 mA / 500 mA
- */
-struct bq24022_mach_info {
-	int gpio_nce;
-	int gpio_iset2;
-	struct regulator_init_data *init_data;
-};
-- 
1.7.5.4



From hunold at linuxtv.org  Fri Mar  2 08:12:20 2012
From: hunold at linuxtv.org (Michael Hunold)
Date: Fri, 02 Mar 2012 14:12:20 +0100
Subject: iMX53 quick start board and SATA
Message-ID: <4F50C734.90302@linuxtv.org>

Hello all,

I am trying to setup a iMX53 quick start board. This is my first
encounter with Freescale, so please bear with me.

I used the Code Sourcery arm-2011.03 toolchain and a stock Linux 3.2.8
kernel. I used "mx5_defconfig" and selected support for the "LOCO"
board, nothing more.

I have used other kernels as well, for example linux-linaro-3.1
(http://git.linaro.org/gitweb?p=kernel/linux-linaro-3.1.git;a=summary)
but with the same results.

>From the U-Boot bootloader I can access the SATA controller just fine.

But from the Linux side, there is zero evidence that the SATA controller
is recognised.

I have searched back and forth through the Linux kernel config, various
(Git) kernel trees around, Google, whatever. I have not found a
definitive answer about SATA support unfortunately.

I must be missing something fairly obvious.

Can somebody please confirm that SATA is supported on the iMX53 quick
start board using some kind of recent kernel?

If so, can you please point my to a tree that has this working?

If it should be working with the trees I have used, does anybody know
which config option I have missed?

Thanks and best regards
Michael.



From arnd at arndb.de  Fri Mar  2 08:27:23 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 13:27:23 +0000
Subject: [GIT PULL v2] at91: irqdomain and device tree for 3.4
In-Reply-To: <4F4F8D66.7040205@atmel.com>
References: <4F4F8D66.7040205@atmel.com>
Message-ID: <201203021327.24417.arnd@arndb.de>

On Thursday 01 March 2012, Nicolas Ferre wrote:
> This pull request supersedes the previous:
> "[GIT PULL] at91: irqdomain and device tree for AIC and GPIO"
> 
> This series adds irqdomain and device tree support for both the
> interrupt and GPIO controllers of AT91 SoC. It has been discussed a lot
> and I think that I have addressed all comments and advices.
> 
> To the AIC, GPIO device tree work, it also adds the the conversion of the 
> PIT and TC timers, the PIO3 support and some basic LED and gpio-keys entries.
> 
> The irqdomain work takes advantage of Grant's patch series that is present
> in:
> git://git.secretlab.ca/git/linux-2.6 irqdomain/next
> This branch is merged into this tree, on top of at91/base2+cleanup (aka cleanup2)
> and before the application of new AT91 material.
> 
> 
> The following changes since commit 89d4a1753b6632327f18d6c8e0842b366b736621:
> 
>   Merge branch 'irqdomain/next' of git://git.secretlab.ca/git/linux-2.6 (2012-03-01 13:26:51 +0100)
 
Pulled into next/dt, looks good!

Thanks,

	Arnd


From sameo at linux.intel.com  Fri Mar  2 08:53:35 2012
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Fri, 2 Mar 2012 14:53:35 +0100
Subject: [PATCH 1/4] regulator: twl6030: add support for vdd1, vdd2 and
 vdd3 regulators
In-Reply-To: <1330421953-29517-2-git-send-email-rnayak@ti.com>
References: <1330421953-29517-1-git-send-email-rnayak@ti.com>
 <1330421953-29517-2-git-send-email-rnayak@ti.com>
Message-ID: <20120302135335.GS9008@sortiz-mobl>

Hi,

On Tue, Feb 28, 2012 at 03:09:10PM +0530, Rajendra Nayak wrote:
> From: Tero Kristo <t-kristo at ti.com>
> 
> vdd1 and vdd2 are now common regulators for twl4030 and twl6030. Also
> added vdd3 as a new regulator for twl6030. twl6030 vdd1...vdd3 smps
> regulator voltages can only be controlled through the smartreflex
> voltage channel, thus the support for the voltage_get and set is
> minimal and requires external controller.
> 
> Signed-off-by: Tero Kristo <t-kristo at ti.com>
> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Liam Girdwood <lrg at ti.com>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
Acked-by: Samuel Ortiz <sameo at linux.intel.com>

Mark, Liam, are you guys taking this one ?

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From jacmet at sunsite.dk  Fri Mar  2 09:00:04 2012
From: jacmet at sunsite.dk (Peter Korsgaard)
Date: Fri, 02 Mar 2012 15:00:04 +0100
Subject: [PATCH v6 1/2] mfd: Add anatop mfd driver
In-Reply-To: <1330671641-6439-1-git-send-email-paul.liu@linaro.org> (Ying-Chun
 Liu's message of "Fri, 2 Mar 2012 15:00:40 +0800")
References: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
 <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
Message-ID: <87fwdrhzmj.fsf@macbook.be.48ers.dk>

>>>>> "Y" == Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org> writes:

Hi,

 Y> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
 Y> Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
 Y> Anatop provides regulators and thermal.
 Y> This driver handles the address space and the operation of the mfd device.

 Y> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
 Y> Cc: Samuel Ortiz <sameo at linux.intel.com>
 Y> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
 Y> Cc: Shawn Guo <shawn.guo at linaro.org>
 Y> ---
 Y>  drivers/mfd/Kconfig        |    6 ++
 Y>  drivers/mfd/Makefile       |    1 +
 Y>  drivers/mfd/anatop-mfd.c   |  142 ++++++++++++++++++++++++++++++++++++++++++++
 Y>  include/linux/mfd/anatop.h |   40 ++++++++++++
 Y>  4 files changed, 189 insertions(+), 0 deletions(-)
 Y>  create mode 100644 drivers/mfd/anatop-mfd.c
 Y>  create mode 100644 include/linux/mfd/anatop.h

 Y> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
 Y> index f147395..f787d17 100644
 Y> --- a/drivers/mfd/Kconfig
 Y> +++ b/drivers/mfd/Kconfig
 Y> @@ -830,6 +830,12 @@ config MFD_INTEL_MSIC
 Y>  	  Passage) chip. This chip embeds audio, battery, GPIO, etc.
 Y>  	  devices used in Intel Medfield platforms.
 
 Y> +config MFD_ANATOP
 Y> +        bool "Support for Anatop"
 Y> +	depends on SOC_IMX6Q

The bool line should be indented with a <tab>, not spaces.

-- 
Bye, Peter Korsgaard


From jason at lakedaemon.net  Fri Mar  2 09:15:41 2012
From: jason at lakedaemon.net (Jason)
Date: Fri, 2 Mar 2012 09:15:41 -0500
Subject: [PATCH 4/4] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <20120302091510.GC29461@kw.sim.vm.gnt>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2f29e88b98b2bcff0c241996e6d7216a60995d2d.1330625878.git.jason@lakedaemon.net>
 <20120302091510.GC29461@kw.sim.vm.gnt>
Message-ID: <20120302141541.GE11986@titan.lakedaemon.net>

On Fri, Mar 02, 2012 at 10:15:11AM +0100, Simon Guinot wrote:
> Hi Jason,
> 
> On Thu, Mar 01, 2012 at 06:20:55PM +0000, Jason Cooper wrote:
> > Converted register address to a variable so that it could be set from
> > fdt.  Also, pull clock frequency from fdt and clean up failure logic a
> > bit.
> > 
> > Same as rtc-mv, this device is used in all kirkwood boards.  So, it is
> > placed in kirkwood.dtsi.
> > 
> > Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> > ---
> >  arch/arm/boot/dts/kirkwood.dtsi   |    6 +++++
> >  arch/arm/mach-kirkwood/board-dt.c |    1 -
> >  arch/arm/mach-kirkwood/common.c   |    2 +-
> >  arch/arm/mach-kirkwood/common.h   |    1 -
> >  drivers/watchdog/orion_wdt.c      |   44 ++++++++++++++++++++++++++----------
> >  5 files changed, 39 insertions(+), 15 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
> > index 5fb185c..bf28424 100644
> > --- a/arch/arm/boot/dts/kirkwood.dtsi
> > +++ b/arch/arm/boot/dts/kirkwood.dtsi
> > @@ -8,5 +8,11 @@
> >  		reg = <0xf1010300 0x1f>;
> >  		interrupts = <53>;
> >  	};
> > +
> > +	wdt at fed20300 {
> > +		compatible = "marvell,orion-wdt";
> > +		reg = <0xfed20300 0x28>;
> > +		clock-frequency = <200000000>;
> > +	};
> 
> How this will work for boards using a different clock frequency (TCLK) ?
> Here, we could have 166MHz for example.
> 
> Can this node be updated during the board initialization with a detected
> TCLK value ?
> 
> Or maybe this clock-frequency can reference a TCLK frequency defined in
> a board specific dts (I don't know if the DT format allow such things) ?

Grr... good catch.  I originally had this in kirkwood-dreamplug.dts,
which is always 200000000.  That's not the case in kirkwood.dtsi.  What
I would like to do, and I haven't had time to look into it (I thought I
would tackle it later as a refinement :-( ), is a reference of some
sort, eg:

in kirkwood.dtsi:

/ {
	compatible = "marvell,kirkwood";
	tclk:clock-frequency = <200000000>;

	wdt at fed20300 {
		compatible = "marvell,orion-wdt";
		reg = <0xfed20300 0x28>;
		clock-frequency = &tclk;
	};
};

then, in kirkwood-foobar.dts

/include/ "kirkwood.dtsi"

/ {
	model = "foobar";
	compatible = "...";
	tclk:clock-frequency = <166000000>;
};

but I'm not sure if that would work.

In any case, the simplest answer is to set clock-frequency in
kirkwood-dreamplug.dts as a root node property, and then each driver
that needs tclk, requests the clock-frequency from the root node.
Hopefully, Grant can chime in on this one.

Thanks for the review,

Jason.


From arnd at arndb.de  Fri Mar  2 09:45:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 14:45:56 +0000
Subject: [GIT PULL] i.MX visstrim patches
In-Reply-To: <20120302073020.GH26642@pengutronix.de>
References: <20120302073020.GH26642@pengutronix.de>
Message-ID: <201203021445.56653.arnd@arndb.de>

On Friday 02 March 2012, Sascha Hauer wrote:
> Please pull the following i.MX27 visstrim driver updates for
> -next.
> 
> Sascha
> 
> 
> The following changes since commit 6b21d18ed50c7d145220b0724ea7f2613abf0f95:
> 
>   Linux 3.3-rc5 (2012-02-25 12:18:16 -0800)
> 
> are available in the git repository at:
> 
>   git://git.pengutronix.de/git/imx/linux-2.6.git features/imx27-visstrim
> 

Pulled into next/boards branch.

Thanks,

	Arnd


From arnd at arndb.de  Fri Mar  2 09:47:54 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 14:47:54 +0000
Subject: [GIT PULL] i.MX27 devicetree support
In-Reply-To: <20120302073224.GI26642@pengutronix.de>
References: <20120302073224.GI26642@pengutronix.de>
Message-ID: <201203021447.55128.arnd@arndb.de>

On Friday 02 March 2012, Sascha Hauer wrote:
> The following changes since commit 6b21d18ed50c7d145220b0724ea7f2613abf0f95:
> 
>   Linux 3.3-rc5 (2012-02-25 12:18:16 -0800)
> 
> are available in the git repository at:
> 
>   git://git.pengutronix.de/git/imx/linux-2.6.git features/imx27-dt
> 

Pulled into next/dt branch.

Thanks,

	Arnd


From arnd at arndb.de  Fri Mar  2 09:56:47 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 14:56:47 +0000
Subject: [PATCH 4/4] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <20120302141541.GE11986@titan.lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <20120302091510.GC29461@kw.sim.vm.gnt>
 <20120302141541.GE11986@titan.lakedaemon.net>
Message-ID: <201203021456.47896.arnd@arndb.de>

On Friday 02 March 2012, Jason wrote:
> Grr... good catch.  I originally had this in kirkwood-dreamplug.dts,
> which is always 200000000.  That's not the case in kirkwood.dtsi.  What
> I would like to do, and I haven't had time to look into it (I thought I
> would tackle it later as a refinement :-( ), is a reference of some
> sort, eg:
> 
> in kirkwood.dtsi:
> 
> / {
>         compatible = "marvell,kirkwood";
>         tclk:clock-frequency = <200000000>;
> 
>         wdt at fed20300 {
>                 compatible = "marvell,orion-wdt";
>                 reg = <0xfed20300 0x28>;
>                 clock-frequency = &tclk;
>         };
> };
> 
> then, in kirkwood-foobar.dts
> 
> include "kirkwood.dtsi"
> 
> / {
>         model = "foobar";
>         compatible = "...";
>         tclk:clock-frequency = <166000000>;
> };
> 
> but I'm not sure if that would work.

That would make wdt at fed20300/clock-frequency a phandle pointing to the
root property, which is not what we want here.

> In any case, the simplest answer is to set clock-frequency in
> kirkwood-dreamplug.dts as a root node property, and then each driver
> that needs tclk, requests the clock-frequency from the root node.
> Hopefully, Grant can chime in on this one.

I think you can just pick a reasonable default value for
wdt at fed20300/clock-frequency, and let the board override that
by setting it to something else if necessary. I suppose this
will also change a bit when kirkwood gets moved over to generic
clk support in the future and starts using the clk binding instead
of what you do now.

	Arnd


From arnd at arndb.de  Fri Mar  2 10:07:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 15:07:56 +0000
Subject: [GIT PULL] i.MX3 patches
In-Reply-To: <20120302080105.GJ3852@pengutronix.de>
References: <20120302080105.GJ3852@pengutronix.de>
Message-ID: <201203021507.57409.arnd@arndb.de>

On Friday 02 March 2012, Sascha Hauer wrote:
> Hi Arnd,
> 
> Please pull the following i.MX3 specific patches for -next. Note
> that 1/2 depends on your imx/cleanup branch since it includes
> crmregs-imx3.h which is created in this branch.
> 
> The following changes since commit d65b4e98d7ea3038b767b70fe8be959b2913f16d:
> 
>   Linux 3.3-rc3 (2012-02-08 19:21:53 -0800)
> 
> are available in the git repository at:
> 
>   git://git.pengutronix.de/git/imx/linux-2.6.git features/imx3

Pulled into next/soc. 

I got a merge conflict against Nico's 4a3ea244 "ARM: plat-mxc: hook special idle
handlers to arm_pm_idle" and did the obvious merge below. Please complain
if this needs some other resolution.

Thanks,

	Arnd

diff --cc arch/arm/mach-imx/mm-imx3.c
index 8404ee7,35ce8b5..b23bd3f
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@@ -34,29 -34,33 +34,31 @@@ static void imx3_idle(void
  {
  	unsigned long reg = 0;
  
+ 	mx3_cpu_lp_set(MX3_WAIT);
+ 
 -	if (!need_resched())
 -		__asm__ __volatile__(
 -			/* disable I and D cache */
 -			"mrc p15, 0, %0, c1, c0, 0\n"
 -			"bic %0, %0, #0x00001000\n"
 -			"bic %0, %0, #0x00000004\n"
 -			"mcr p15, 0, %0, c1, c0, 0\n"
 -			/* invalidate I cache */
 -			"mov %0, #0\n"
 -			"mcr p15, 0, %0, c7, c5, 0\n"
 -			/* clear and invalidate D cache */
 -			"mov %0, #0\n"
 -			"mcr p15, 0, %0, c7, c14, 0\n"
 -			/* WFI */
 -			"mov %0, #0\n"
 -			"mcr p15, 0, %0, c7, c0, 4\n"
 -			"nop\n" "nop\n" "nop\n" "nop\n"
 -			"nop\n" "nop\n" "nop\n"
 -			/* enable I and D cache */
 -			"mrc p15, 0, %0, c1, c0, 0\n"
 -			"orr %0, %0, #0x00001000\n"
 -			"orr %0, %0, #0x00000004\n"
 -			"mcr p15, 0, %0, c1, c0, 0\n"
 -			: "=r" (reg));
 -	local_irq_enable();
 +	__asm__ __volatile__(
 +		/* disable I and D cache */
 +		"mrc p15, 0, %0, c1, c0, 0\n"
 +		"bic %0, %0, #0x00001000\n"
 +		"bic %0, %0, #0x00000004\n"
 +		"mcr p15, 0, %0, c1, c0, 0\n"
 +		/* invalidate I cache */
 +		"mov %0, #0\n"
 +		"mcr p15, 0, %0, c7, c5, 0\n"
 +		/* clear and invalidate D cache */
 +		"mov %0, #0\n"
 +		"mcr p15, 0, %0, c7, c14, 0\n"
 +		/* WFI */
 +		"mov %0, #0\n"
 +		"mcr p15, 0, %0, c7, c0, 4\n"
 +		"nop\n" "nop\n" "nop\n" "nop\n"
 +		"nop\n" "nop\n" "nop\n"
 +		/* enable I and D cache */
 +		"mrc p15, 0, %0, c1, c0, 0\n"
 +		"orr %0, %0, #0x00001000\n"
 +		"orr %0, %0, #0x00000004\n"
 +		"mcr p15, 0, %0, c1, c0, 0\n"
 +		: "=r" (reg));
  }
  
  static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,


From s.hauer at pengutronix.de  Fri Mar  2 10:11:52 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 2 Mar 2012 16:11:52 +0100
Subject: [GIT PULL] i.MX3 patches
In-Reply-To: <201203021507.57409.arnd@arndb.de>
References: <20120302080105.GJ3852@pengutronix.de>
 <201203021507.57409.arnd@arndb.de>
Message-ID: <20120302151152.GO3852@pengutronix.de>

On Fri, Mar 02, 2012 at 03:07:56PM +0000, Arnd Bergmann wrote:
> On Friday 02 March 2012, Sascha Hauer wrote:
> > Hi Arnd,
> > 
> > Please pull the following i.MX3 specific patches for -next. Note
> > that 1/2 depends on your imx/cleanup branch since it includes
> > crmregs-imx3.h which is created in this branch.
> > 
> > The following changes since commit d65b4e98d7ea3038b767b70fe8be959b2913f16d:
> > 
> >   Linux 3.3-rc3 (2012-02-08 19:21:53 -0800)
> > 
> > are available in the git repository at:
> > 
> >   git://git.pengutronix.de/git/imx/linux-2.6.git features/imx3
> 
> Pulled into next/soc. 
> 
> I got a merge conflict against Nico's 4a3ea244 "ARM: plat-mxc: hook special idle
> handlers to arm_pm_idle" and did the obvious merge below. Please complain
> if this needs some other resolution.

Looks good.

Thanks
 Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From broonie at opensource.wolfsonmicro.com  Fri Mar  2 10:15:58 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 2 Mar 2012 15:15:58 +0000
Subject: [PATCH 1/4] regulator: twl6030: add support for vdd1, vdd2 and
 vdd3 regulators
In-Reply-To: <20120302135335.GS9008@sortiz-mobl>
References: <1330421953-29517-1-git-send-email-rnayak@ti.com>
 <1330421953-29517-2-git-send-email-rnayak@ti.com>
 <20120302135335.GS9008@sortiz-mobl>
Message-ID: <20120302151558.GH3230@opensource.wolfsonmicro.com>

On Fri, Mar 02, 2012 at 02:53:35PM +0100, Samuel Ortiz wrote:

> Mark, Liam, are you guys taking this one ?

Yes.
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From t-kristo at ti.com  Fri Mar  2 10:17:49 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Fri, 2 Mar 2012 17:17:49 +0200
Subject: [PATCHv4 0/6] ARM: OMAP3+: IO daisychain support fixes
Message-ID: <1330701475-22576-1-git-send-email-t-kristo@ti.com>

Hi,

Changes compared to previous version:

- patch2:
 * changed timeout value to 100us (from 1000)
 * added poll for the IO status == 0 at the end of trigger sequence
- patch4:
 * omap3: global wakeup done in PRM init instead of OMAP3 PM init
 * omap4: moved global wakeup enable from trigger func to PRM init

Tested on omap3beagle / omap4blaze, suspend / resume works with io chain.

-Tero



From t-kristo at ti.com  Fri Mar  2 10:17:50 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Fri, 2 Mar 2012 17:17:50 +0200
Subject: [PATCHv4 1/6] ARM: OMAP3 PM: correct enable/disable of daisy io chain
In-Reply-To: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
Message-ID: <1330701475-22576-2-git-send-email-t-kristo@ti.com>

From: Mohan V <mohanv at ti.com>

Currently the enabling and disabling of IO Daisy chain is not
according to the TRM. The below steps are followed to enable/
disable the IO chain according to the "Sec 3.5.7.2.2
I/O Wake-Up Mechanism" in OMAP3630 Public TRM[1].

Steps to enable IO chain:
[a] Set PM_WKEN_WKUP.EN_IO bit
[b] Set the PM_WKEN_WKUP.EN_IO_CHAIN bit
[c] Poll for PM_WKST_WKUP.ST_IO_CHAIN.
[d] When ST_IO_CHAIN bit set to 1, clear PM_WKEN_WKUP.EN_IO_CHAIN
[e] Clear ST_IO_CHAIN bit.

Steps to disable IO chain:
[a] Clear PM_WKEN_WKUP.EN_IO_CHAIN bit
[b] Clear PM_WKEN_WKUP.EN_IO bit
[c] Clear PM_WKST_WKUP.ST_IO bit by writing 1 to it.

Step [e] & [c] in each case can be skipped, as these are handled
by the PRCM interrupt handler later.

[1] http://focus.ti.com/pdfs/wtbu/OMAP36xx_ES1.x_PUBLIC_TRM_vV.zip

Signed-off-by: Mohan V <mohanv at ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc69875..b0821a8 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -94,16 +94,17 @@ static void omap3_enable_io_chain(void)
 	/* Do a readback to assure write has been done */
 	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 
-	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
+	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
 		 OMAP3430_ST_IO_CHAIN_MASK)) {
 		timeout++;
 		if (timeout > 1000) {
 			pr_err("Wake up daisy chain activation failed.\n");
 			return;
 		}
-		omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
-					   WKUP_MOD, PM_WKEN);
 	}
+	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+			PM_WKEN);
+
 }
 
 static void omap3_disable_io_chain(void)
-- 
1.7.4.1



From t-kristo at ti.com  Fri Mar  2 10:17:51 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Fri, 2 Mar 2012 17:17:51 +0200
Subject: [PATCHv4 2/6] ARM: OMAP3 PM: Move IO Daisychain function to omap3 prm
 file
In-Reply-To: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
Message-ID: <1330701475-22576-3-git-send-email-t-kristo@ti.com>

From: Vishwanath BS <vishwanath.bs at ti.com>

Since IO Daisychain modifies only PRM registers, it makes sense to move
it to PRM File. Also changed the timeout value for IO chain enable to
100us and added a wait for status disable at the end.

Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
---
 arch/arm/mach-omap2/pm34xx.c       |   30 +-----------------------------
 arch/arm/mach-omap2/prm2xxx_3xxx.c |   36 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm2xxx_3xxx.h |   14 ++++++++++++++
 3 files changed, 51 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b0821a8..e97ec3f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -85,34 +85,6 @@ static inline void omap3_per_restore_context(void)
 	omap_gpio_restore_context();
 }
 
-static void omap3_enable_io_chain(void)
-{
-	int timeout = 0;
-
-	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-				   PM_WKEN);
-	/* Do a readback to assure write has been done */
-	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
-
-	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
-		 OMAP3430_ST_IO_CHAIN_MASK)) {
-		timeout++;
-		if (timeout > 1000) {
-			pr_err("Wake up daisy chain activation failed.\n");
-			return;
-		}
-	}
-	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-			PM_WKEN);
-
-}
-
-static void omap3_disable_io_chain(void)
-{
-	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-				     PM_WKEN);
-}
-
 static void omap3_core_save_context(void)
 {
 	omap3_ctrl_save_padconf();
@@ -324,7 +296,7 @@ void omap_sram_idle(void)
 	     core_next_state < PWRDM_POWER_ON)) {
 		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 		if (omap3_has_io_chain_ctrl())
-			omap3_enable_io_chain();
+			omap3_trigger_io_chain();
 	}
 
 	pwrdm_pre_transition();
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 9ce7654..4f4f08a 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -301,6 +301,42 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 }
 
+/*
+ * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
+ * the I/O ring after asserting WUCLKIN high
+ */
+#define MAX_IOPAD_LATCH_TIME 100
+
+/* OMAP3 Daisychain enable sequence */
+void omap3_trigger_io_chain(void)
+{
+	int i = 0;
+
+	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+				   PM_WKEN);
+	/* Do a readback to assure write has been done */
+	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+
+	omap_test_timeout(((omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
+			    OMAP3430_ST_IO_CHAIN_MASK) == 1),
+			  MAX_IOPAD_LATCH_TIME, i);
+
+	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+				     PM_WKEN);
+
+	omap_test_timeout(((omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
+			    OMAP3430_ST_IO_CHAIN_MASK) == 0),
+			  MAX_IOPAD_LATCH_TIME, i);
+}
+
+/* OMAP3 Daisychain disable sequence */
+void omap3_disable_io_chain(void)
+{
+	if (omap_rev() >= OMAP3430_REV_ES3_1)
+		omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK,
+					     WKUP_MOD, PM_WKEN);
+}
+
 static int __init omap3xxx_prcm_init(void)
 {
 	if (cpu_is_omap34xx())
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 70ac2a1..15973aa 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -289,6 +289,18 @@ static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
 		"not suppose to be used on omap4\n");
 	return 0;
 }
+static inline void omap3_trigger_io_chain(void)
+{
+	WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+		"not suppose to be used on omap4\n");
+	return 0;
+}
+static inline void omap3_disable_io_chain(void)
+{
+	WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+		"not suppose to be used on omap4\n");
+	return 0;
+}
 #else
 /* Power/reset management domain register get/set */
 extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
@@ -302,6 +314,8 @@ extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
 extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
 extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
 extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
+extern void omap3_trigger_io_chain(void);
+extern void omap3_disable_io_chain(void);
 
 /* OMAP3-specific VP functions */
 u32 omap3_prm_vp_check_txdone(u8 vp_id);
-- 
1.7.4.1



From t-kristo at ti.com  Fri Mar  2 10:17:52 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Fri, 2 Mar 2012 17:17:52 +0200
Subject: [PATCHv4 3/6] ARM: OMAP4 PM: Add IO Daisychain support
In-Reply-To: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
Message-ID: <1330701475-22576-4-git-send-email-t-kristo@ti.com>

From: Rajendra Nayak <rnayak at ti.com>

IO daisychain is a mechanism that allows individual IO pads to generate
wakeup events on their own based on a switch of an input signal level.
This allows the hardware module behind the pad to be powered down, but
still have device level capability to detect IO events, and once this
happens the module can be powered back up to resume IO. See section
3.9.4 in OMAP4430 Public TRM for details.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
---
 arch/arm/mach-omap2/prm44xx.c |   41 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm44xx.h |    1 +
 2 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a37bfd4..caa5e0f 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -231,6 +231,47 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
 				 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
 }
 
+/*
+ * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
+ * the I/O ring after asserting WUCLKIN high
+ */
+#define MAX_IOPAD_LATCH_TIME 100
+
+/* OMAP4 IO Daisychain trigger sequence */
+void omap4_trigger_io_chain(void)
+{
+	int i = 0;
+
+	/* Enable GLOBAL_WUEN */
+	if (!(omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+		OMAP4_PRM_IO_PMCTRL_OFFSET) & OMAP4430_GLOBAL_WUEN_MASK))
+		omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
+			OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET);
+
+	/* Trigger WUCLKIN enable */
+	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
+			OMAP4430_WUCLK_CTRL_MASK, OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET);
+	omap_test_timeout(
+		(((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET) &
+			OMAP4430_WUCLK_STATUS_MASK) >>
+			OMAP4430_WUCLK_STATUS_SHIFT) == 1),
+		MAX_IOPAD_LATCH_TIME, i);
+
+	/* Trigger WUCLKIN disable */
+	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
+			OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_IO_PMCTRL_OFFSET);
+	omap_test_timeout(
+		(((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET) &
+			OMAP4430_WUCLK_STATUS_MASK) >>
+			OMAP4430_WUCLK_STATUS_SHIFT) == 0),
+		MAX_IOPAD_LATCH_TIME, i);
+	return;
+}
+
 static int __init omap4xxx_prcm_init(void)
 {
 	if (cpu_is_omap44xx())
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7978092..54a057e 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -762,6 +762,7 @@ void omap4_prm_vp_clear_txdone(u8 vp_id);
 extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+extern void omap4_trigger_io_chain(void);
 
 /* PRM interrupt-related functions */
 extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
-- 
1.7.4.1



From t-kristo at ti.com  Fri Mar  2 10:17:53 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Fri, 2 Mar 2012 17:17:53 +0200
Subject: [PATCHv4 4/6] ARM: OMAP3+: PRM: Enable IO wake up
In-Reply-To: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
Message-ID: <1330701475-22576-5-git-send-email-t-kristo@ti.com>

Enable IO Wake up for OMAP3/4 as part of PRM Init. Currently this has been
managed in cpuidle path which is not the right place. Subsequent patch
will remove IO Daisy chain handling in cpuidle path once daisy chain is
handled as part of hwmod mux. This patch also moves the OMAP4 IO wakeup
enable code from the trigger function to init time setup.

Signed-off-by: Tero Kristo <t-kristo at ti.com>
---
 arch/arm/mach-omap2/prm2xxx_3xxx.c |   11 ++++++++++-
 arch/arm/mach-omap2/prm44xx.c      |   18 ++++++++++--------
 2 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 4f4f08a..f681628 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -337,10 +337,19 @@ void omap3_disable_io_chain(void)
 					     WKUP_MOD, PM_WKEN);
 }
 
+static void __init omap3_enable_io_wakeup(void)
+{
+	if (omap3_has_io_wakeup())
+		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+					   PM_WKEN);
+}
+
 static int __init omap3xxx_prcm_init(void)
 {
-	if (cpu_is_omap34xx())
+	if (cpu_is_omap34xx()) {
+		omap3_enable_io_wakeup();
 		return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
+	}
 	return 0;
 }
 subsys_initcall(omap3xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index caa5e0f..4ce6f08 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -242,13 +242,6 @@ void omap4_trigger_io_chain(void)
 {
 	int i = 0;
 
-	/* Enable GLOBAL_WUEN */
-	if (!(omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
-		OMAP4_PRM_IO_PMCTRL_OFFSET) & OMAP4430_GLOBAL_WUEN_MASK))
-		omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
-			OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_PRM_DEVICE_INST,
-			OMAP4_PRM_IO_PMCTRL_OFFSET);
-
 	/* Trigger WUCLKIN enable */
 	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
 			OMAP4430_WUCLK_CTRL_MASK, OMAP4430_PRM_DEVICE_INST,
@@ -272,10 +265,19 @@ void omap4_trigger_io_chain(void)
 	return;
 }
 
+static void __init omap4_enable_io_wakeup(void)
+{
+	omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
+			OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET);
+}
+
 static int __init omap4xxx_prcm_init(void)
 {
-	if (cpu_is_omap44xx())
+	if (cpu_is_omap44xx()) {
+		omap4_enable_io_wakeup();
 		return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+	}
 	return 0;
 }
 subsys_initcall(omap4xxx_prcm_init);
-- 
1.7.4.1



From t-kristo at ti.com  Fri Mar  2 10:17:54 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Fri, 2 Mar 2012 17:17:54 +0200
Subject: [PATCHv4 5/6] ARM: OMAP3PLUS PM: Add IO Daisychain support via hwmod
 mux
In-Reply-To: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
Message-ID: <1330701475-22576-6-git-send-email-t-kristo@ti.com>

From: Vishwanath BS <vishwanath.bs at ti.com>

IO Daisychain feature has to be triggered whenever there is a change in
device's mux configuration (See section 3.9.4 in OMAP4 Public TRM vP).

Now devices can idle independent of the powerdomain, there can be a
window where device is idled and corresponding powerdomain can be
ON/INACTIVE state. In such situations, since both module wake up is
enabled at padlevel as well as io daisychain sequence is triggered,
there will be 2 PRCM interrupts (Module async wake up via swakeup and
IO Pad interrupt). But as PRCM Interrupt handler clears the Module
Padlevel WKST bit in the first interrupt, module specific interrupt
handler will not triggered for the second time

Also look at detailed explanation given by Rajendra at
http://www.spinics.net/lists/linux-serial/msg04480.html

Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    9 +++++++--
 arch/arm/mach-omap2/pm.c         |   15 +++++++++++++++
 arch/arm/mach-omap2/pm.h         |    1 +
 3 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5192cab..56adbfb 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -152,6 +152,7 @@
 #include "prm44xx.h"
 #include "prminst44xx.h"
 #include "mux.h"
+#include "pm.h"
 
 /* Maximum microseconds to wait for OMAP module to softreset */
 #define MAX_MODULE_SOFTRESET_WAIT	10000
@@ -1535,8 +1536,10 @@ static int _enable(struct omap_hwmod *oh)
 	/* Mux pins for device runtime if populated */
 	if (oh->mux && (!oh->mux->enabled ||
 			((oh->_state == _HWMOD_STATE_IDLE) &&
-			 oh->mux->pads_dynamic)))
+			 oh->mux->pads_dynamic))) {
 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+		omap_trigger_io_chain();
+	}
 
 	_add_initiator_dep(oh, mpu_oh);
 
@@ -1622,8 +1625,10 @@ static int _idle(struct omap_hwmod *oh)
 		clkdm_hwmod_disable(oh->clkdm, oh);
 
 	/* Mux pins for device idle if populated */
-	if (oh->mux && oh->mux->pads_dynamic)
+	if (oh->mux && oh->mux->pads_dynamic) {
 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+		omap_trigger_io_chain();
+	}
 
 	oh->_state = _HWMOD_STATE_IDLE;
 
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 1881fe9..4f1dcb5 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -25,8 +25,11 @@
 #include "clockdomain.h"
 #include "pm.h"
 #include "twl-common.h"
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
 
 static struct omap_device_pm_latency *pm_lats;
+static void (*io_chain_trigger_func) (void);
 
 static int _init_omap_device(char *name)
 {
@@ -64,6 +67,12 @@ static void omap2_init_processor_devices(void)
 	}
 }
 
+void omap_trigger_io_chain(void)
+{
+	if (io_chain_trigger_func)
+		io_chain_trigger_func();
+}
+
 /* Types of sleep_switch used in omap_set_pwrdm_state */
 #define FORCEWAKEUP_SWITCH	0
 #define LOWPOWERSTATE_SWITCH	1
@@ -221,6 +230,12 @@ static int __init omap2_common_pm_init(void)
 		omap2_init_processor_devices();
 	omap_pm_if_init();
 
+	if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl())
+		io_chain_trigger_func = omap3_trigger_io_chain;
+
+	if (cpu_is_omap44xx())
+		io_chain_trigger_func = omap4_trigger_io_chain;
+
 	return 0;
 }
 postcore_initcall(omap2_common_pm_init);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index b737b11..f9dac40 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -22,6 +22,7 @@ extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
 extern int omap4_idle_init(void);
+extern void omap_trigger_io_chain(void);
 
 #if defined(CONFIG_PM_OPP)
 extern int omap3_opp_init(void);
-- 
1.7.4.1



From t-kristo at ti.com  Fri Mar  2 10:17:55 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Fri, 2 Mar 2012 17:17:55 +0200
Subject: [PATCHv4 6/6] ARM: OMAP3 PM: Remove IO Daisychain control from cpuidle
In-Reply-To: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
Message-ID: <1330701475-22576-7-git-send-email-t-kristo@ti.com>

From: Vishwanath BS <vishwanath.bs at ti.com>

As IO Daisy chain sequence is triggered via hwmod mux, there is no need to
control it from cpuidle path for OMAP3.

Also as omap3_disable_io_chain is no longer being used, just remove the
function.

Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
---
 arch/arm/mach-omap2/pm34xx.c       |   17 -----------------
 arch/arm/mach-omap2/prm2xxx_3xxx.c |    8 --------
 arch/arm/mach-omap2/prm2xxx_3xxx.h |    7 -------
 3 files changed, 0 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e97ec3f..ed12bb4 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -291,13 +291,6 @@ void omap_sram_idle(void)
 	/* Enable IO-PAD and IO-CHAIN wakeups */
 	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
-	if (omap3_has_io_wakeup() &&
-	    (per_next_state < PWRDM_POWER_ON ||
-	     core_next_state < PWRDM_POWER_ON)) {
-		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
-		if (omap3_has_io_chain_ctrl())
-			omap3_trigger_io_chain();
-	}
 
 	pwrdm_pre_transition();
 
@@ -376,16 +369,6 @@ void omap_sram_idle(void)
 			omap3_per_restore_context();
 	}
 
-	/* Disable IO-PAD and IO-CHAIN wakeup */
-	if (omap3_has_io_wakeup() &&
-	    (per_next_state < PWRDM_POWER_ON ||
-	     core_next_state < PWRDM_POWER_ON)) {
-		omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
-					     PM_WKEN);
-		if (omap3_has_io_chain_ctrl())
-			omap3_disable_io_chain();
-	}
-
 	clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 }
 
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index f681628..31a7c27 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -329,14 +329,6 @@ void omap3_trigger_io_chain(void)
 			  MAX_IOPAD_LATCH_TIME, i);
 }
 
-/* OMAP3 Daisychain disable sequence */
-void omap3_disable_io_chain(void)
-{
-	if (omap_rev() >= OMAP3430_REV_ES3_1)
-		omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK,
-					     WKUP_MOD, PM_WKEN);
-}
-
 static void __init omap3_enable_io_wakeup(void)
 {
 	if (omap3_has_io_wakeup())
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 15973aa..391b844 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -295,12 +295,6 @@ static inline void omap3_trigger_io_chain(void)
 		"not suppose to be used on omap4\n");
 	return 0;
 }
-static inline void omap3_disable_io_chain(void)
-{
-	WARN(1, "prm: omap2xxx/omap3xxx specific function and "
-		"not suppose to be used on omap4\n");
-	return 0;
-}
 #else
 /* Power/reset management domain register get/set */
 extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
@@ -315,7 +309,6 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
 extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
 extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
 extern void omap3_trigger_io_chain(void);
-extern void omap3_disable_io_chain(void);
 
 /* OMAP3-specific VP functions */
 u32 omap3_prm_vp_check_txdone(u8 vp_id);
-- 
1.7.4.1



From mina86 at mina86.com  Fri Mar  2 10:26:39 2012
From: mina86 at mina86.com (Michal Nazarewicz)
Date: Fri, 02 Mar 2012 16:26:39 +0100
Subject: [PATCH] MM: CMA: add a simple kernel module as the helper to test
 CMA
In-Reply-To: <1330656742-5233-1-git-send-email-Barry.Song@csr.com>
References: <1330656742-5233-1-git-send-email-Barry.Song@csr.com>
Message-ID: <op.wajuip2a3l0zgt@mpn-glaptop>

On Fri, 02 Mar 2012 03:52:22 +0100, Barry Song <Barry.Song at csr.com> wrote:

> From: Barry Song <Baohua.Song at csr.com>
>
> Any write request to /dev/cma_test will let the module to allocate memory from
> CMA, for example:
>
> 1st time
> $ echo 0 > /dev/cma_test
> will require cma_test to request 1MB
> 2nd time
> $ echo 0 > /dev/cma_test
> will require cma_test to request 2MB
>
> Any read request to /dev/cma_test will let the module to free memory from CMA,
> for example:
>
> 1st time
> $ cat /dev/cma_test
> will require cma_test to free the 1MB allocated in the first write request
> 2nd time
> $ echo 0 > /dev/cma_test
> will require cma_test to free the 2MB allocated in the second write request

Looks quite all right.  It has a race condition but I guess for a test device it's
not that big of a deal (I think the race cannot cause panic).  Either way, would be
nice if one could specify how much memory device should allocate.  How about those
changes:

diff --git a/tools/cma/cma_test.c b/tools/cma/cma_test.c
index 3ee89f3..3d3b074 100644
--- a/tools/cma/cma_test.c
+++ b/tools/cma/cma_test.c
@@ -6,66 +6,96 @@
   * Licensed under GPLv2 or later.
   */

-#include <linux/module.h>
  #include <linux/device.h>
+#include <linux/dma-mapping.h>
  #include <linux/fs.h>
+#include <linux/list.h>
  #include <linux/miscdevice.h>
-#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+struct cma_allocation {
+	struct list_head list;
+	unsigned long size;
+	dma_addr_t dma;
+	void *virt;
+};

-#define CMA_NUM  10
  static struct device *cma_dev;
-static dma_addr_t dma_phys[CMA_NUM];
-static void *dma_virt[CMA_NUM];
+static LIST_HEAD(cma_allocations);
+static DEFINE_SPINLOCK(cma_lock);

-/* any read request will free coherent memory, eg.
+/*
+ * Any read request will free a single coherent memory, eg.
   * cat /dev/cma_test
   */
  static ssize_t
  cma_test_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
  {
-	int i;
-
-	for (i = 0; i < CMA_NUM; i++) {
-		if (dma_virt[i]) {
-			dma_free_coherent(cma_dev, (i + 1) * SZ_1M, dma_virt[i], dma_phys[i]);
-			_dev_info(cma_dev, "free virt: %p phys: %p\n", dma_virt[i], (void *)dma_phys[i]);
-			dma_virt[i] = NULL;
-			break;
-		}
+	struct cma_allocation *alloc = NULL;
+
+	spin_lock(&cma_lock);
+	if (!list_empty(&cma_allocations)) {
+		alloc = list_first_entry(&cma_allocations,
+					 struct cma_allocation, list);
+		list_del(&alloc->list);
  	}
+	spin_unlock(&cma_lock);
+
+	if (alloc) {
+		dma_free_coherent(cma_dev, alloc->size, alloc->virt,
+				  alloc->dma);
+		_dev_info(cma_dev, "free virt: %p phys: %p\n",
+			  alloc->phys, (void *)alloc->dma);
+		kfree(alloc);
+	}
+
  	return 0;
  }

  /*
- * any write request will alloc coherent memory, eg.
- * echo 0 > /dev/cma_test
+ * Writes request specified number of pages, eg.
+ * echo 1024 > /dev/cma_test
   */
  static ssize_t
-cma_test_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
+cma_test_write(struct file *file, const char __user *buf, size_t count,
+	       loff_t *ppos)
  {
-	int i;
+	struct cma_allocation *alloc;
  	int ret;

-	for (i = 0; i < CMA_NUM; i++) {
-		if (!dma_virt[i]) {
-			dma_virt[i] = dma_alloc_coherent(cma_dev, (i + 1) * SZ_1M, &dma_phys[i], GFP_KERNEL);
-
-			if (dma_virt[i]) {
-				void *p;
-				/* touch every page in the allocated memory */
-				for (p = dma_virt[i]; p <  dma_virt[i] + (i + 1) * SZ_1M; p += PAGE_SIZE)
-					*(u32 *)p = 0;
-
-				_dev_info(cma_dev, "alloc virt: %p phys: %p\n", dma_virt[i], (void *)dma_phys[i]);
-			} else {
-				dev_err(cma_dev, "no mem in CMA area\n");
-				ret = -ENOMEM;
-			}
-			break;
-		}
-	}
+	alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
+	if (!alloc)
+		return -ENOMEM;
+
+	ret = kstrtouint_from_user(buf, count, 0, &alloc->size);
+	if (ret)
+		return ret;
+
+	if (!alloc->size)
+		return -EINVAL;
+
+	if (alloc->size > (ULONG_MAX << PAGE_SHIFT))
+		return -EOVERFLOW;

-	return count;
+	alloc->size >>= PAGE_SHIFT;
+	alloc->virt = dma_alloc_coherent(cma_dev, alloc->size,
+					 &alloc->dma, GFP_KERNEL);
+
+	if (alloc->virt) {
+		_dev_info(cma_dev, "alloc virt: %p phys: %p\n", alloc->virt,
+			  (void *)alloc->dma);
+
+		spin_lock(&cma_lock);
+		list_add_tail(&alloc->list, &cma_allocations);
+		spin_unlock(&cma_lock);
+
+		return count;
+	} else {
+		dev_err(cma_dev, "no mem in CMA area\n");
+		kfree(alloc);
+		return -ENOSPC;
+	}
  }

  static const struct file_operations cma_test_fops = {

> Signed-off-by: Barry Song <Baohua.Song at csr.com>
> ---
>  tools/cma/Makefile   |   13 ++++++
>  tools/cma/cma_test.c |  108 ++++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 121 insertions(+), 0 deletions(-)
>  create mode 100644 tools/cma/Makefile
>  create mode 100644 tools/cma/cma_test.c
>
> diff --git a/tools/cma/Makefile b/tools/cma/Makefile
> new file mode 100644
> index 0000000..d15c2c0
> --- /dev/null
> +++ b/tools/cma/Makefile
> @@ -0,0 +1,13 @@
> +# Kernel modules
> +#
> +# To compile for ARM:
> +# make ARCH=arm CC=arm-none-linux-gnueabi-gcc
> +#
> +obj-m	+= cma_test.o
> +
> +build: kernel_modules
> +
> +kernel_modules:
> +	${MAKE} -C $(CURDIR)/../.. M=$(CURDIR)
> +clean:
> +	${MAKE} -C $(CURDIR)/../.. M=$(CURDIR) clean
> diff --git a/tools/cma/cma_test.c b/tools/cma/cma_test.c
> new file mode 100644
> index 0000000..3ee89f3
> --- /dev/null
> +++ b/tools/cma/cma_test.c
> @@ -0,0 +1,108 @@
> +/*
> + * kernel module helper for testing CMA
> + *
> + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/device.h>
> +#include <linux/fs.h>
> +#include <linux/miscdevice.h>
> +#include <linux/dma-mapping.h>
> +
> +#define CMA_NUM  10
> +static struct device *cma_dev;
> +static dma_addr_t dma_phys[CMA_NUM];
> +static void *dma_virt[CMA_NUM];
> +
> +/* any read request will free coherent memory, eg.
> + * cat /dev/cma_test
> + */
> +static ssize_t
> +cma_test_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
> +{
> +	int i;
> +
> +	for (i = 0; i < CMA_NUM; i++) {
> +		if (dma_virt[i]) {
> +			dma_free_coherent(cma_dev, (i + 1) * SZ_1M, dma_virt[i], dma_phys[i]);
> +			_dev_info(cma_dev, "free virt: %p phys: %p\n", dma_virt[i], (void *)dma_phys[i]);
> +			dma_virt[i] = NULL;
> +			break;
> +		}
> +	}
> +	return 0;
> +}
> +
> +/*
> + * any write request will alloc coherent memory, eg.
> + * echo 0 > /dev/cma_test
> + */
> +static ssize_t
> +cma_test_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
> +{
> +	int i;
> +	int ret;
> +
> +	for (i = 0; i < CMA_NUM; i++) {
> +		if (!dma_virt[i]) {
> +			dma_virt[i] = dma_alloc_coherent(cma_dev, (i + 1) * SZ_1M, &dma_phys[i], GFP_KERNEL);
> +
> +			if (dma_virt[i]) {
> +				void *p;
> +				/* touch every page in the allocated memory */
> +				for (p = dma_virt[i]; p <  dma_virt[i] + (i + 1) * SZ_1M; p += PAGE_SIZE)
> +					*(u32 *)p = 0;
> +
> +				_dev_info(cma_dev, "alloc virt: %p phys: %p\n", dma_virt[i], (void *)dma_phys[i]);
> +			} else {
> +				dev_err(cma_dev, "no mem in CMA area\n");
> +				ret = -ENOMEM;
> +			}
> +			break;
> +		}
> +	}
> +
> +	return count;
> +}
> +
> +static const struct file_operations cma_test_fops = {
> +	.owner =    THIS_MODULE,
> +	.read  =    cma_test_read,
> +	.write =    cma_test_write,
> +};
> +
> +static struct miscdevice cma_test_misc = {
> +	.name = "cma_test",
> +	.fops = &cma_test_fops,
> +};
> +
> +static int __init cma_test_init(void)
> +{
> +	int ret = 0;
> +
> +	ret = misc_register(&cma_test_misc);
> +	if (unlikely(ret)) {
> +		pr_err("failed to register cma test misc device!\n");
> +		return ret;
> +	}
> +	cma_dev = cma_test_misc.this_device;
> +	cma_dev->coherent_dma_mask = ~0;
> +	_dev_info(cma_dev, "registered.\n");
> +
> +	return ret;
> +}
> +module_init(cma_test_init);
> +
> +static void __exit cma_test_exit(void)
> +{
> +	misc_deregister(&cma_test_misc);
> +}
> +module_exit(cma_test_exit);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Barry Song <Baohua.Song at csr.com>");
> +MODULE_DESCRIPTION("kernel module to help the test of CMA");
> +MODULE_ALIAS("CMA test");


-- 
Best regards,                                         _     _
.o. | Liege of Serenely Enlightened Majesty of      o' \,=./ `o
..o | Computer Science,  Micha? ?mina86? Nazarewicz    (o o)
ooo +----<email/xmpp: mpn at google.com>--------------ooO--(_)--Ooo--


From jason at lakedaemon.net  Fri Mar  2 10:36:14 2012
From: jason at lakedaemon.net (Jason)
Date: Fri, 2 Mar 2012 10:36:14 -0500
Subject: [PATCH 4/4] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <201203021456.47896.arnd@arndb.de>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <20120302091510.GC29461@kw.sim.vm.gnt>
 <20120302141541.GE11986@titan.lakedaemon.net>
 <201203021456.47896.arnd@arndb.de>
Message-ID: <20120302153614.GG11986@titan.lakedaemon.net>

On Fri, Mar 02, 2012 at 02:56:47PM +0000, Arnd Bergmann wrote:
> On Friday 02 March 2012, Jason wrote:
> > Grr... good catch.  I originally had this in kirkwood-dreamplug.dts,
> > which is always 200000000.  That's not the case in kirkwood.dtsi.  What
> > I would like to do, and I haven't had time to look into it (I thought I
> > would tackle it later as a refinement :-( ), is a reference of some
> > sort, eg:
> > 
> > in kirkwood.dtsi:
> > 
> > / {
> >         compatible = "marvell,kirkwood";
> >         tclk:clock-frequency = <200000000>;
> > 
> >         wdt at fed20300 {
> >                 compatible = "marvell,orion-wdt";
> >                 reg = <0xfed20300 0x28>;
> >                 clock-frequency = &tclk;
> >         };
> > };
> > 
> > then, in kirkwood-foobar.dts
> > 
> > include "kirkwood.dtsi"
> > 
> > / {
> >         model = "foobar";
> >         compatible = "...";
> >         tclk:clock-frequency = <166000000>;
> > };
> > 
> > but I'm not sure if that would work.
> 
> That would make wdt at fed20300/clock-frequency a phandle pointing to the
> root property, which is not what we want here.

The 200000000 value is not the actual value used in most drivers [1],
but rather the speed of the system clock [2] (hence, my inclination to
make it a root property), the drivers have been pulling this number from
a global variable [3] and dividing/rounding it as needed for their own needs
[1].

Since it's derived from the SoC core [2], it would seem to make sense to
have a root "clock-frequency" in the board dts.  Am I missing something?
Is there a better way to do this?

> > In any case, the simplest answer is to set clock-frequency in
> > kirkwood-dreamplug.dts as a root node property, and then each driver
> > that needs tclk, requests the clock-frequency from the root node.
> > Hopefully, Grant can chime in on this one.
> 
> I think you can just pick a reasonable default value for
> wdt at fed20300/clock-frequency, and let the board override that
> by setting it to something else if necessary.

True, for now, I can just set clock-frequency for each device to the
exact same value and we'll polish later once we have a better idea of
the pattern it's following.

> I suppose this will also change a bit when kirkwood gets moved over to
> generic clk support in the future and starts using the clk binding
> instead of what you do now.

Yes, I don't want to over-think it, but I would like to make sure it's
in the correct place, since it is a global property of the board.

thanks for the review,

Jason.

[1] drivers/spi/spi-orion.c:110-117,500,501

# 110-117 ### orion_spi_baudrate_set()
        tclk_hz = orion_spi->tclk;

        /*
         * the supported rates are: 4,6,8...30
         * round up as we look for equal or less speed
         */
        rate = DIV_ROUND_UP(tclk_hz, speed);
        rate = roundup(rate, 2);
# 500-501 ### orion_spi_probe()
        spi->max_speed = DIV_ROUND_UP(spi->tclk, 4);
        spi->min_speed = DIV_ROUND_UP(spi->tclk, 30);
#############

[2] arch/arm/mach-kirkwood/common.c:320-332

# 320-332 ###
int kirkwood_tclk;

static int __init kirkwood_find_tclk(void)
{
        u32 dev, rev;

        kirkwood_pcie_id(&dev, &rev);

        if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
                if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
                        return 200000000;

        return 166666667;
}
#############

[3] arch/arm/mach-kirkwood/common.c:235

# 235 ####### kirkwood_spi_init()
        orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk);
#############



From 21cnbao at gmail.com  Fri Mar  2 10:37:46 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Fri, 2 Mar 2012 23:37:46 +0800
Subject: [PATCH] MM: CMA: add a simple kernel module as the helper to test
 CMA
In-Reply-To: <op.wajuip2a3l0zgt@mpn-glaptop>
References: <1330656742-5233-1-git-send-email-Barry.Song@csr.com>
 <op.wajuip2a3l0zgt@mpn-glaptop>
Message-ID: <CAGsJ_4zz=C2k3pvc=1_=iviSUkz78QCF+yumEEMaknysLHFxag@mail.gmail.com>

2012/3/2 Michal Nazarewicz <mina86 at mina86.com>:
> On Fri, 02 Mar 2012 03:52:22 +0100, Barry Song <Barry.Song at csr.com> wrote:
>
>> From: Barry Song <Baohua.Song at csr.com>
>>
>> Any write request to /dev/cma_test will let the module to allocate memory
>> from
>> CMA, for example:
>>
>> 1st time
>> $ echo 0 > /dev/cma_test
>> will require cma_test to request 1MB
>> 2nd time
>> $ echo 0 > /dev/cma_test
>> will require cma_test to request 2MB
>>
>> Any read request to /dev/cma_test will let the module to free memory from
>> CMA,
>> for example:
>>
>> 1st time
>> $ cat /dev/cma_test
>> will require cma_test to free the 1MB allocated in the first write request
>> 2nd time
>> $ echo 0 > /dev/cma_test
>> will require cma_test to free the 2MB allocated in the second write
>> request
>
>
> Looks quite all right. ?It has a race condition but I guess for a test
> device it's
> not that big of a deal (I think the race cannot cause panic). ?Either way,
> would be
> nice if one could specify how much memory device should allocate. ?How about
> those
> changes:

Michal, i think these improvements have maken the cma_test much more
useful and flexible.

>
> diff --git a/tools/cma/cma_test.c b/tools/cma/cma_test.c
> index 3ee89f3..3d3b074 100644
> --- a/tools/cma/cma_test.c
> +++ b/tools/cma/cma_test.c
> @@ -6,66 +6,96 @@
>
> ?* Licensed under GPLv2 or later.
> ?*/
>
> -#include <linux/module.h>
> ?#include <linux/device.h>
> +#include <linux/dma-mapping.h>
> ?#include <linux/fs.h>
> +#include <linux/list.h>
> ?#include <linux/miscdevice.h>
> -#include <linux/dma-mapping.h>
> +#include <linux/module.h>
> +#include <linux/spinlock.h>
> +
> +struct cma_allocation {
> + ? ? ? struct list_head list;
> + ? ? ? unsigned long size;
> + ? ? ? dma_addr_t dma;
> + ? ? ? void *virt;
> +};
>
> -#define CMA_NUM ?10
> ?static struct device *cma_dev;
> -static dma_addr_t dma_phys[CMA_NUM];
> -static void *dma_virt[CMA_NUM];
> +static LIST_HEAD(cma_allocations);
> +static DEFINE_SPINLOCK(cma_lock);
>
>
> -/* any read request will free coherent memory, eg.
> +/*
> + * Any read request will free a single coherent memory, eg.
> ?* cat /dev/cma_test
> ?*/
> ?static ssize_t
>
> ?cma_test_read(struct file *file, char __user *buf, size_t count, loff_t
> *ppos)
> ?{
> - ? ? ? int i;
> -
> - ? ? ? for (i = 0; i < CMA_NUM; i++) {
> - ? ? ? ? ? ? ? if (dma_virt[i]) {
> - ? ? ? ? ? ? ? ? ? ? ? dma_free_coherent(cma_dev, (i + 1) * SZ_1M,
> dma_virt[i], dma_phys[i]);
> - ? ? ? ? ? ? ? ? ? ? ? _dev_info(cma_dev, "free virt: %p phys: %p\n",
> dma_virt[i], (void *)dma_phys[i]);
> - ? ? ? ? ? ? ? ? ? ? ? dma_virt[i] = NULL;
> - ? ? ? ? ? ? ? ? ? ? ? break;
> - ? ? ? ? ? ? ? }
> + ? ? ? struct cma_allocation *alloc = NULL;
> +
> + ? ? ? spin_lock(&cma_lock);
> + ? ? ? if (!list_empty(&cma_allocations)) {
> + ? ? ? ? ? ? ? alloc = list_first_entry(&cma_allocations,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct cma_allocation, list);
> + ? ? ? ? ? ? ? list_del(&alloc->list);
> ? ? ? ?}
> + ? ? ? spin_unlock(&cma_lock);
> +
> + ? ? ? if (alloc) {
> + ? ? ? ? ? ? ? dma_free_coherent(cma_dev, alloc->size, alloc->virt,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? alloc->dma);
>
> + ? ? ? ? ? ? ? _dev_info(cma_dev, "free virt: %p phys: %p\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? alloc->phys, (void *)alloc->dma);
> + ? ? ? ? ? ? ? kfree(alloc);
> + ? ? ? }
> +
> ? ? ? ?return 0;
>
> ?}
>
> ?/*
> - * any write request will alloc coherent memory, eg.
> - * echo 0 > /dev/cma_test
> + * Writes request specified number of pages, eg.
> + * echo 1024 > /dev/cma_test
> ?*/
>
> ?static ssize_t
> -cma_test_write(struct file *file, const char __user *buf, size_t count,
> loff_t *ppos)
> +cma_test_write(struct file *file, const char __user *buf, size_t count,
> + ? ? ? ? ? ? ?loff_t *ppos)
> ?{
> - ? ? ? int i;
> + ? ? ? struct cma_allocation *alloc;
> ? ? ? ?int ret;
>
> - ? ? ? for (i = 0; i < CMA_NUM; i++) {
> - ? ? ? ? ? ? ? if (!dma_virt[i]) {
> - ? ? ? ? ? ? ? ? ? ? ? dma_virt[i] = dma_alloc_coherent(cma_dev, (i + 1) *
> SZ_1M, &dma_phys[i], GFP_KERNEL);
> -
> - ? ? ? ? ? ? ? ? ? ? ? if (dma_virt[i]) {
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? void *p;
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* touch every page in the allocated memory
> */
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? for (p = dma_virt[i]; p < ?dma_virt[i] + (i
> + 1) * SZ_1M; p += PAGE_SIZE)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? *(u32 *)p = 0;
> -
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _dev_info(cma_dev, "alloc virt: %p phys:
> %p\n", dma_virt[i], (void *)dma_phys[i]);
> - ? ? ? ? ? ? ? ? ? ? ? } else {
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dev_err(cma_dev, "no mem in CMA area\n");
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ret = -ENOMEM;
> - ? ? ? ? ? ? ? ? ? ? ? }
> - ? ? ? ? ? ? ? ? ? ? ? break;
> - ? ? ? ? ? ? ? }
> - ? ? ? }
> + ? ? ? alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
> + ? ? ? if (!alloc)
> + ? ? ? ? ? ? ? return -ENOMEM;
> +
> + ? ? ? ret = kstrtouint_from_user(buf, count, 0, &alloc->size);
> + ? ? ? if (ret)
> + ? ? ? ? ? ? ? return ret;
> +
> + ? ? ? if (!alloc->size)
> + ? ? ? ? ? ? ? return -EINVAL;
> +
> + ? ? ? if (alloc->size > (ULONG_MAX << PAGE_SHIFT))
> + ? ? ? ? ? ? ? return -EOVERFLOW;
>
> - ? ? ? return count;
> + ? ? ? alloc->size >>= PAGE_SHIFT;
> + ? ? ? alloc->virt = dma_alloc_coherent(cma_dev, alloc->size,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?&alloc->dma, GFP_KERNEL);
> +
> + ? ? ? if (alloc->virt) {
> + ? ? ? ? ? ? ? _dev_info(cma_dev, "alloc virt: %p phys: %p\n", alloc->virt,
> + ? ? ? ? ? ? ? ? ? ? ? ? (void *)alloc->dma);
> +
> + ? ? ? ? ? ? ? spin_lock(&cma_lock);
> + ? ? ? ? ? ? ? list_add_tail(&alloc->list, &cma_allocations);
> + ? ? ? ? ? ? ? spin_unlock(&cma_lock);
> +
> + ? ? ? ? ? ? ? return count;
> + ? ? ? } else {
>
> + ? ? ? ? ? ? ? dev_err(cma_dev, "no mem in CMA area\n");
> + ? ? ? ? ? ? ? kfree(alloc);
> + ? ? ? ? ? ? ? return -ENOSPC;
> + ? ? ? }
>
> ?}
>
> ?static const struct file_operations cma_test_fops = {
>
>> Signed-off-by: Barry Song <Baohua.Song at csr.com>
>> ---
>> ?tools/cma/Makefile ? | ? 13 ++++++
>> ?tools/cma/cma_test.c | ?108
>> ++++++++++++++++++++++++++++++++++++++++++++++++++
>> ?2 files changed, 121 insertions(+), 0 deletions(-)
>> ?create mode 100644 tools/cma/Makefile
>> ?create mode 100644 tools/cma/cma_test.c
>>
>> diff --git a/tools/cma/Makefile b/tools/cma/Makefile
>> new file mode 100644
>> index 0000000..d15c2c0
>> --- /dev/null
>> +++ b/tools/cma/Makefile
>> @@ -0,0 +1,13 @@
>> +# Kernel modules
>> +#
>> +# To compile for ARM:
>> +# make ARCH=arm CC=arm-none-linux-gnueabi-gcc
>> +#
>> +obj-m ?+= cma_test.o
>> +
>> +build: kernel_modules
>> +
>> +kernel_modules:
>> + ? ? ? ${MAKE} -C $(CURDIR)/../.. M=$(CURDIR)
>> +clean:
>> + ? ? ? ${MAKE} -C $(CURDIR)/../.. M=$(CURDIR) clean
>> diff --git a/tools/cma/cma_test.c b/tools/cma/cma_test.c
>> new file mode 100644
>> index 0000000..3ee89f3
>> --- /dev/null
>> +++ b/tools/cma/cma_test.c
>> @@ -0,0 +1,108 @@
>> +/*
>> + * kernel module helper for testing CMA
>> + *
>> + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group
>> company.
>> + *
>> + * Licensed under GPLv2 or later.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/device.h>
>> +#include <linux/fs.h>
>> +#include <linux/miscdevice.h>
>> +#include <linux/dma-mapping.h>
>> +
>> +#define CMA_NUM ?10
>> +static struct device *cma_dev;
>> +static dma_addr_t dma_phys[CMA_NUM];
>> +static void *dma_virt[CMA_NUM];
>> +
>> +/* any read request will free coherent memory, eg.
>> + * cat /dev/cma_test
>> + */
>> +static ssize_t
>> +cma_test_read(struct file *file, char __user *buf, size_t count, loff_t
>> *ppos)
>> +{
>> + ? ? ? int i;
>> +
>> + ? ? ? for (i = 0; i < CMA_NUM; i++) {
>> + ? ? ? ? ? ? ? if (dma_virt[i]) {
>> + ? ? ? ? ? ? ? ? ? ? ? dma_free_coherent(cma_dev, (i + 1) * SZ_1M,
>> dma_virt[i], dma_phys[i]);
>> + ? ? ? ? ? ? ? ? ? ? ? _dev_info(cma_dev, "free virt: %p phys: %p\n",
>> dma_virt[i], (void *)dma_phys[i]);
>> + ? ? ? ? ? ? ? ? ? ? ? dma_virt[i] = NULL;
>> + ? ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? ? ? ? ? ? }
>> + ? ? ? }
>> + ? ? ? return 0;
>> +}
>> +
>> +/*
>> + * any write request will alloc coherent memory, eg.
>> + * echo 0 > /dev/cma_test
>> + */
>> +static ssize_t
>> +cma_test_write(struct file *file, const char __user *buf, size_t count,
>> loff_t *ppos)
>> +{
>> + ? ? ? int i;
>> + ? ? ? int ret;
>> +
>> + ? ? ? for (i = 0; i < CMA_NUM; i++) {
>> + ? ? ? ? ? ? ? if (!dma_virt[i]) {
>> + ? ? ? ? ? ? ? ? ? ? ? dma_virt[i] = dma_alloc_coherent(cma_dev, (i + 1)
>> * SZ_1M, &dma_phys[i], GFP_KERNEL);
>> +
>> + ? ? ? ? ? ? ? ? ? ? ? if (dma_virt[i]) {
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? void *p;
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* touch every page in the allocated
>> memory */
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? for (p = dma_virt[i]; p < ?dma_virt[i] +
>> (i + 1) * SZ_1M; p += PAGE_SIZE)
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? *(u32 *)p = 0;
>> +
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _dev_info(cma_dev, "alloc virt: %p phys:
>> %p\n", dma_virt[i], (void *)dma_phys[i]);
>> + ? ? ? ? ? ? ? ? ? ? ? } else {
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dev_err(cma_dev, "no mem in CMA area\n");
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ret = -ENOMEM;
>> + ? ? ? ? ? ? ? ? ? ? ? }
>> + ? ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? ? ? ? ? ? }
>> + ? ? ? }
>> +
>> + ? ? ? return count;
>> +}
>> +
>> +static const struct file_operations cma_test_fops = {
>> + ? ? ? .owner = ? ?THIS_MODULE,
>> + ? ? ? .read ?= ? ?cma_test_read,
>> + ? ? ? .write = ? ?cma_test_write,
>> +};
>> +
>> +static struct miscdevice cma_test_misc = {
>> + ? ? ? .name = "cma_test",
>> + ? ? ? .fops = &cma_test_fops,
>> +};
>> +
>> +static int __init cma_test_init(void)
>> +{
>> + ? ? ? int ret = 0;
>> +
>> + ? ? ? ret = misc_register(&cma_test_misc);
>> + ? ? ? if (unlikely(ret)) {
>> + ? ? ? ? ? ? ? pr_err("failed to register cma test misc device!\n");
>> + ? ? ? ? ? ? ? return ret;
>> + ? ? ? }
>> + ? ? ? cma_dev = cma_test_misc.this_device;
>> + ? ? ? cma_dev->coherent_dma_mask = ~0;
>> + ? ? ? _dev_info(cma_dev, "registered.\n");
>> +
>> + ? ? ? return ret;
>> +}
>> +module_init(cma_test_init);
>> +
>> +static void __exit cma_test_exit(void)
>> +{
>> + ? ? ? misc_deregister(&cma_test_misc);
>> +}
>> +module_exit(cma_test_exit);
>> +
>> +MODULE_LICENSE("GPL");
>> +MODULE_AUTHOR("Barry Song <Baohua.Song at csr.com>");
>> +MODULE_DESCRIPTION("kernel module to help the test of CMA");
>> +MODULE_ALIAS("CMA test");
>
>
>
> --
> Best regards, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _ ? ? _
> .o. | Liege of Serenely Enlightened Majesty of ? ? ?o' \,=./ `o
> ..o | Computer Science, ?Micha? ?mina86? Nazarewicz ? ?(o o)
> ooo +----<email/xmpp: mpn at google.com>--------------ooO--(_)--Ooo--
>
>

-barry


From mina86 at mina86.com  Fri Mar  2 10:44:48 2012
From: mina86 at mina86.com (Michal Nazarewicz)
Date: Fri, 02 Mar 2012 16:44:48 +0100
Subject: [PATCH] MM: CMA: add a simple kernel module as the helper to test
 CMA
In-Reply-To: <CAGsJ_4zz=C2k3pvc=1_=iviSUkz78QCF+yumEEMaknysLHFxag@mail.gmail.com>
References: <1330656742-5233-1-git-send-email-Barry.Song@csr.com>
 <op.wajuip2a3l0zgt@mpn-glaptop>
 <CAGsJ_4zz=C2k3pvc=1_=iviSUkz78QCF+yumEEMaknysLHFxag@mail.gmail.com>
Message-ID: <op.wajvcyle3l0zgt@mpn-glaptop>

> 2012/3/2 Michal Nazarewicz <mina86 at mina86.com>:
>> Looks quite all right.  It has a race condition but I guess for a test
>> device it's not that big of a deal (I think the race cannot cause
>> panic).  Either way, would be nice if one could specify how much memory
>> device should allocate.  How about those changes: [...]

On Fri, 02 Mar 2012 16:37:46 +0100, Barry Song <21cnbao at gmail.com> wrote:
> Michal, I think these improvements have maken the cma_test much more
> useful and flexible.

Sure, no problem, just squash it and resend the patch and I'll take one more
look at the result. :)

-- 
Best regards,                                         _     _
.o. | Liege of Serenely Enlightened Majesty of      o' \,=./ `o
..o | Computer Science,  Micha? ?mina86? Nazarewicz    (o o)
ooo +----<email/xmpp: mpn at google.com>--------------ooO--(_)--Ooo--


From linus.walleij at stericsson.com  Fri Mar  2 10:53:41 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 2 Mar 2012 16:53:41 +0100
Subject: [PATCH] pinctrl: fix the pin descriptor kerneldoc
Message-ID: <1330703621-4044-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

The introduction of the owner field on the pin descriptor was not
properly documented so fix this up.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/core.h |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 97f8124..e1dfdb3 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -76,9 +76,7 @@ struct pinctrl {
  *	datasheet or such
  * @dynamic_name: if the name of this pin was dynamically allocated
  * @lock: a lock to protect the descriptor structure
- * @mux_requested: whether the pin is already requested by pinmux or not
- * @mux_function: a named muxing function for the pin that will be passed to
- *	subdrivers and shown in debugfs etc
+ * @owner: the device holding this pin or NULL of no device has claimed it
  */
 struct pin_desc {
 	struct pinctrl_dev *pctldev;
-- 
1.7.8



From niklas.hernaeus at stericsson.com  Fri Mar  2 10:52:47 2012
From: niklas.hernaeus at stericsson.com (Niklas Hernaeus)
Date: Fri, 2 Mar 2012 16:52:47 +0100
Subject: [PATCH] Initial Device Tree system for Snowball
Message-ID: <1330703567-17925-1-git-send-email-niklas.hernaeus@stericsson.com>

From: Niklas Hernaeus <niklas.hernaeus at linaro.org>

This is the base system for using Device Tree for Snowball.
The new boardfile is a slightly modified copy of the original board file,
so new Device Tree stuff can simply be added and code removed, while
functionality stays the same.

Signed-off-by: Niklas Hernaeus <niklas.hernaeus at linaro.org>
---
 arch/arm/boot/dts/snowball.dts          |   32 ++
 arch/arm/mach-ux500/Kconfig             |   17 +-
 arch/arm/mach-ux500/Makefile            |    5 +-
 arch/arm/mach-ux500/board-mop500-dt.c   |  729 +++++++++++++++++++++++++++++++
 arch/arm/mach-ux500/include/mach/irqs.h |    2 +-
 5 files changed, 779 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/boot/dts/snowball.dts
 create mode 100644 arch/arm/mach-ux500/board-mop500-dt.c

diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
new file mode 100644
index 0000000..02305fb
--- /dev/null
+++ b/arch/arm/boot/dts/snowball.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2011 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+/ {
+	model = "Calao Systems Snowball platform with device tree";
+	compatible = "calaosystems,snowball-a9500";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;
+	};
+
+	soc-u9500 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+	};
+};
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 52af004..be7e4fe 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -27,19 +27,22 @@ menu "Ux500 target platform (boards)"
 config MACH_U8500
 	bool "U8500 Development platform"
 	depends on UX500_SOC_DB8500
+	depends on !USE_OF
 	select TPS6105X
 	help
 	  Include support for the mop500 development platform.
 
 config MACH_HREFV60
-       bool "U85000 Development platform, HREFv60 version"
-       depends on UX500_SOC_DB8500
-       help
-         Include support for the HREFv60 new development platform.
+	bool "U85000 Development platform, HREFv60 version"
+	depends on UX500_SOC_DB8500
+	depends on !USE_OF
+	help
+	  Include support for the HREFv60 new development platform.
 
 config MACH_SNOWBALL
 	bool "U8500 Snowball platform"
 	depends on UX500_SOC_DB8500
+	depends on !USE_OF
 	select MACH_U8500
 	help
 	  Include support for the snowball development platform.
@@ -49,6 +52,12 @@ config MACH_U5500
 	depends on UX500_SOC_DB5500
 	help
 	  Include support for the U5500 development platform.
+config MACH_UX500_DT
+	def_bool y if USE_OF
+	depends on UX500_SOC_DB8500 || UX500_SOC_DB5500
+
+config MACH_MOP500
+	def_bool y if MACH_U8500 || MACH_UX500_DT
 endmenu
 
 config UX500_DEBUG_UART
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 6bd2f45..05bee25 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -7,7 +7,10 @@ obj-y				:= clock.o cpu.o devices.o devices-common.o \
 obj-$(CONFIG_CACHE_L2X0)	+= cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB5500)	+= cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)	+= cpu-db8500.o devices-db8500.o
-obj-$(CONFIG_MACH_U8500)	+= board-mop500.o board-mop500-sdi.o \
+
+obj-$(CONFIG_MACH_UX500_DT)    += board-mop500-dt.o
+obj-$(CONFIG_MACH_U8500)       += board-mop500.o
+obj-$(CONFIG_MACH_MOP500)      += board-mop500-sdi.o \
 				board-mop500-regulators.o \
 				board-mop500-uib.o board-mop500-stuib.o \
 				board-mop500-u8500uib.o \
diff --git a/arch/arm/mach-ux500/board-mop500-dt.c b/arch/arm/mach-ux500/board-mop500-dt.c
new file mode 100644
index 0000000..33f4a83
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-dt.c
@@ -0,0 +1,729 @@
+/*
+ * Copyright (C) 2008-2009 ST-Ericsson
+ *
+ * Author: Srinidhi KASAGAR <srinidhi.kasagar at stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl022.h>
+#include <linux/amba/serial.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/abx500/ab8500.h>
+#include <linux/regulator/ab8500.h>
+#include <linux/mfd/tc3589x.h>
+#include <linux/mfd/tps6105x.h>
+#include <linux/mfd/abx500/ab8500-gpio.h>
+#include <linux/leds-lp5521.h>
+#include <linux/input.h>
+#include <linux/smsc911x.h>
+#include <linux/gpio_keys.h>
+#include <linux/delay.h>
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <plat/i2c.h>
+#include <plat/ste_dma40.h>
+#include <plat/pincfg.h>
+#include <plat/gpio-nomadik.h>
+
+#include <mach/hardware.h>
+#include <mach/setup.h>
+#include <mach/devices.h>
+#include <mach/irqs.h>
+
+#include "pins-db8500.h"
+#include "ste-dma40-db8500.h"
+#include "devices-db8500.h"
+#include "board-mop500.h"
+#include "board-mop500-regulators.h"
+
+static struct gpio_led snowball_led_array[] = {
+	{
+		.name = "user_led",
+		.default_trigger = "none",
+		.gpio = 142,
+	},
+};
+
+static struct gpio_led_platform_data snowball_led_data = {
+	.leds = snowball_led_array,
+	.num_leds = ARRAY_SIZE(snowball_led_array),
+};
+
+static struct platform_device snowball_led_dev = {
+	.name = "leds-gpio",
+	.dev = {
+		.platform_data = &snowball_led_data,
+	},
+};
+
+static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
+	.gpio_base		= MOP500_AB8500_GPIO(0),
+	.irq_base		= MOP500_AB8500_VIR_GPIO_IRQ_BASE,
+	/* config_reg is the initial configuration of ab8500 pins.
+	 * The pins can be configured as GPIO or alt functions based
+	 * on value present in GpioSel1 to GpioSel6 and AlternatFunction
+	 * register. This is the array of 7 configuration settings.
+	 * One has to compile time decide these settings. Below is the
+	 * explanation of these setting
+	 * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
+	 * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
+	 * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
+	 * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO
+	 * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO
+	 * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO
+	 * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured
+	 * as GPIO then this register selectes the alternate fucntions
+	 */
+	.config_reg		= {0x00, 0x1E, 0x80, 0x01,
+					0x7A, 0x00, 0x00},
+};
+
+static struct gpio_keys_button snowball_key_array[] = {
+	{
+		.gpio           = 32,
+		.type           = EV_KEY,
+		.code           = KEY_1,
+		.desc           = "userpb",
+		.active_low     = 1,
+		.debounce_interval = 50,
+		.wakeup         = 1,
+	},
+	{
+		.gpio           = 151,
+		.type           = EV_KEY,
+		.code           = KEY_2,
+		.desc           = "extkb1",
+		.active_low     = 1,
+		.debounce_interval = 50,
+		.wakeup         = 1,
+	},
+	{
+		.gpio           = 152,
+		.type           = EV_KEY,
+		.code           = KEY_3,
+		.desc           = "extkb2",
+		.active_low     = 1,
+		.debounce_interval = 50,
+		.wakeup         = 1,
+	},
+	{
+		.gpio           = 161,
+		.type           = EV_KEY,
+		.code           = KEY_4,
+		.desc           = "extkb3",
+		.active_low     = 1,
+		.debounce_interval = 50,
+		.wakeup         = 1,
+	},
+	{
+		.gpio           = 162,
+		.type           = EV_KEY,
+		.code           = KEY_5,
+		.desc           = "extkb4",
+		.active_low     = 1,
+		.debounce_interval = 50,
+		.wakeup         = 1,
+	},
+};
+
+static struct gpio_keys_platform_data snowball_key_data = {
+	.buttons        = snowball_key_array,
+	.nbuttons       = ARRAY_SIZE(snowball_key_array),
+};
+
+static struct platform_device snowball_key_dev = {
+	.name           = "gpio-keys",
+	.id             = -1,
+	.dev            = {
+		.platform_data  = &snowball_key_data,
+	}
+};
+
+static struct smsc911x_platform_config snowball_sbnet_cfg = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+	.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+	.shift = 1,
+};
+
+static struct resource sbnet_res[] = {
+	{
+		.name = "smsc911x-memory",
+		.start = (0x5000 << 16),
+		.end  =  (0x5000 << 16) + 0xffff,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = NOMADIK_GPIO_TO_IRQ(140),
+		.end = NOMADIK_GPIO_TO_IRQ(140),
+		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+	},
+};
+
+static struct platform_device snowball_sbnet_dev = {
+	.name           = "smsc911x",
+	.num_resources  = ARRAY_SIZE(sbnet_res),
+	.resource       = sbnet_res,
+	.dev            = {
+		.platform_data = &snowball_sbnet_cfg,
+	},
+};
+
+static struct ab8500_platform_data ab8500_platdata = {
+	.irq_base	= MOP500_AB8500_IRQ_BASE,
+	.regulator_reg_init = ab8500_regulator_reg_init,
+	.num_regulator_reg_init	= ARRAY_SIZE(ab8500_regulator_reg_init),
+	.regulator	= ab8500_regulators,
+	.num_regulator	= ARRAY_SIZE(ab8500_regulators),
+	.gpio		= &ab8500_gpio_pdata,
+};
+
+static struct resource ab8500_resources[] = {
+	[0] = {
+		.start	= IRQ_DB8500_AB8500,
+		.end	= IRQ_DB8500_AB8500,
+		.flags	= IORESOURCE_IRQ
+	}
+};
+
+struct platform_device ab8500_device = {
+	.name = "ab8500-i2c",
+	.id = 0,
+	.dev = {
+		.platform_data = &ab8500_platdata,
+	},
+	.num_resources = 1,
+	.resource = ab8500_resources,
+};
+
+/*
+ * TPS61052
+ */
+
+static struct tps6105x_platform_data mop500_tps61052_data = {
+	.mode = TPS6105X_MODE_VOLTAGE,
+	.regulator_data = &tps61052_regulator,
+};
+
+/*
+ * TC35892
+ */
+
+static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base)
+{
+	mop500_sdi_tc35892_init();
+}
+
+static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = {
+	.gpio_base	= MOP500_EGPIO(0),
+	.setup		= mop500_tc35892_init,
+};
+
+static struct tc3589x_platform_data mop500_tc35892_data = {
+	.block		= TC3589x_BLOCK_GPIO,
+	.gpio		= &mop500_tc35892_gpio_data,
+	.irq_base	= MOP500_EGPIO_IRQ_BASE,
+};
+
+static struct lp5521_led_config lp5521_pri_led[] = {
+       [0] = {
+	       .chan_nr = 0,
+	       .led_current = 0x2f,
+	       .max_current = 0x5f,
+       },
+       [1] = {
+	       .chan_nr = 1,
+	       .led_current = 0x2f,
+	       .max_current = 0x5f,
+       },
+       [2] = {
+	       .chan_nr = 2,
+	       .led_current = 0x2f,
+	       .max_current = 0x5f,
+       },
+};
+
+static struct lp5521_platform_data __initdata lp5521_pri_data = {
+       .label = "lp5521_pri",
+       .led_config     = &lp5521_pri_led[0],
+       .num_channels   = 3,
+       .clock_mode     = LP5521_CLOCK_EXT,
+};
+
+static struct lp5521_led_config lp5521_sec_led[] = {
+       [0] = {
+	       .chan_nr = 0,
+	       .led_current = 0x2f,
+	       .max_current = 0x5f,
+       },
+       [1] = {
+	       .chan_nr = 1,
+	       .led_current = 0x2f,
+	       .max_current = 0x5f,
+       },
+       [2] = {
+	       .chan_nr = 2,
+	       .led_current = 0x2f,
+	       .max_current = 0x5f,
+       },
+};
+
+static struct lp5521_platform_data __initdata lp5521_sec_data = {
+       .label = "lp5521_sec",
+       .led_config     = &lp5521_sec_led[0],
+       .num_channels   = 3,
+       .clock_mode     = LP5521_CLOCK_EXT,
+};
+
+static struct i2c_board_info __initdata mop500_i2c0_devices[] = {
+	{
+		I2C_BOARD_INFO("tc3589x", 0x42),
+		.irq		= NOMADIK_GPIO_TO_IRQ(217),
+		.platform_data  = &mop500_tc35892_data,
+	},
+	/* I2C0 devices only available prior to HREFv60 */
+	{
+		I2C_BOARD_INFO("tps61052", 0x33),
+		.platform_data  = &mop500_tps61052_data,
+	},
+};
+
+#define NUM_PRE_V60_I2C0_DEVICES 1
+
+static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
+	{
+		/* lp5521 LED driver, 1st device */
+		I2C_BOARD_INFO("lp5521", 0x33),
+		.platform_data = &lp5521_pri_data,
+	},
+	{
+		/* lp5521 LED driver, 2st device */
+		I2C_BOARD_INFO("lp5521", 0x34),
+		.platform_data = &lp5521_sec_data,
+	},
+	{
+		/* Light sensor Rohm BH1780GLI */
+		I2C_BOARD_INFO("bh1780", 0x29),
+	},
+};
+
+#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, t_out, _sm)	\
+static struct nmk_i2c_controller u8500_i2c##id##_data = { \
+	/*				\
+	 * slave data setup time, which is	\
+	 * 250 ns,100ns,10ns which is 14,6,2	\
+	 * respectively for a 48 Mhz	\
+	 * i2c clock			\
+	 */				\
+	.slsu		= _slsu,	\
+	/* Tx FIFO threshold */		\
+	.tft		= _tft,		\
+	/* Rx FIFO threshold */		\
+	.rft		= _rft,		\
+	/* std. mode operation */	\
+	.clk_freq	= clk,		\
+	/* Slave response timeout(ms) */\
+	.timeout	= t_out,	\
+	.sm		= _sm,		\
+}
+
+/*
+ * The board uses 4 i2c controllers, initialize all of
+ * them with slave data setup time of 250 ns,
+ * Tx & Rx FIFO threshold values as 8 and standard
+ * mode of operation
+ */
+U8500_I2C_CONTROLLER(0, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(2,	0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(3,	0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
+
+static void __init mop500_i2c_init(void)
+{
+	db8500_add_i2c0(&u8500_i2c0_data);
+	db8500_add_i2c1(&u8500_i2c1_data);
+	db8500_add_i2c2(&u8500_i2c2_data);
+	db8500_add_i2c3(&u8500_i2c3_data);
+}
+
+static struct gpio_keys_button mop500_gpio_keys[] = {
+	{
+		.desc			= "SFH7741 Proximity Sensor",
+		.type			= EV_SW,
+		.code			= SW_FRONT_PROXIMITY,
+		.active_low		= 0,
+		.can_disable		= 1,
+	}
+};
+
+static struct regulator *prox_regulator;
+static int mop500_prox_activate(struct device *dev);
+static void mop500_prox_deactivate(struct device *dev);
+
+static struct gpio_keys_platform_data mop500_gpio_keys_data = {
+	.buttons	= mop500_gpio_keys,
+	.nbuttons	= ARRAY_SIZE(mop500_gpio_keys),
+	.enable		= mop500_prox_activate,
+	.disable	= mop500_prox_deactivate,
+};
+
+static struct platform_device mop500_gpio_keys_device = {
+	.name	= "gpio-keys",
+	.id	= 0,
+	.dev	= {
+		.platform_data	= &mop500_gpio_keys_data,
+	},
+};
+
+static int mop500_prox_activate(struct device *dev)
+{
+	prox_regulator = regulator_get(&mop500_gpio_keys_device.dev,
+						"vcc");
+	if (IS_ERR(prox_regulator)) {
+		dev_err(&mop500_gpio_keys_device.dev,
+			"no regulator\n");
+		return PTR_ERR(prox_regulator);
+	}
+	regulator_enable(prox_regulator);
+	return 0;
+}
+
+static void mop500_prox_deactivate(struct device *dev)
+{
+	regulator_disable(prox_regulator);
+	regulator_put(prox_regulator);
+}
+
+/* add any platform devices here - TODO */
+static struct platform_device *mop500_platform_devs[] __initdata = {
+	&mop500_gpio_keys_device,
+	&ab8500_device,
+};
+
+#ifdef CONFIG_STE_DMA40
+static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
+	.mode = STEDMA40_MODE_LOGICAL,
+	.dir = STEDMA40_PERIPH_TO_MEM,
+	.src_dev_type =  DB8500_DMA_DEV8_SSP0_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
+	.mode = STEDMA40_MODE_LOGICAL,
+	.dir = STEDMA40_MEM_TO_PERIPH,
+	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+	.dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+#endif
+
+static struct pl022_ssp_controller ssp0_platform_data = {
+	.bus_id = 0,
+#ifdef CONFIG_STE_DMA40
+	.enable_dma = 1,
+	.dma_filter = stedma40_filter,
+	.dma_rx_param = &ssp0_dma_cfg_rx,
+	.dma_tx_param = &ssp0_dma_cfg_tx,
+#else
+	.enable_dma = 0,
+#endif
+	/* on this platform, gpio 31,142,144,214 &
+	 * 224 are connected as chip selects
+	 */
+	.num_chipselect = 5,
+};
+
+static void __init mop500_spi_init(void)
+{
+	db8500_add_ssp0(&ssp0_platform_data);
+}
+
+#ifdef CONFIG_STE_DMA40
+static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
+	.mode = STEDMA40_MODE_LOGICAL,
+	.dir = STEDMA40_PERIPH_TO_MEM,
+	.src_dev_type =  DB8500_DMA_DEV13_UART0_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
+	.mode = STEDMA40_MODE_LOGICAL,
+	.dir = STEDMA40_MEM_TO_PERIPH,
+	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+	.dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
+	.mode = STEDMA40_MODE_LOGICAL,
+	.dir = STEDMA40_PERIPH_TO_MEM,
+	.src_dev_type =  DB8500_DMA_DEV12_UART1_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
+	.mode = STEDMA40_MODE_LOGICAL,
+	.dir = STEDMA40_MEM_TO_PERIPH,
+	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+	.dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
+	.mode = STEDMA40_MODE_LOGICAL,
+	.dir = STEDMA40_PERIPH_TO_MEM,
+	.src_dev_type =  DB8500_DMA_DEV11_UART2_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
+	.mode = STEDMA40_MODE_LOGICAL,
+	.dir = STEDMA40_MEM_TO_PERIPH,
+	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+	.dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+#endif
+
+
+static pin_cfg_t mop500_pins_uart0[] = {
+	GPIO0_U0_CTSn   | PIN_INPUT_PULLUP,
+	GPIO1_U0_RTSn   | PIN_OUTPUT_HIGH,
+	GPIO2_U0_RXD    | PIN_INPUT_PULLUP,
+	GPIO3_U0_TXD    | PIN_OUTPUT_HIGH,
+};
+
+#define PRCC_K_SOFTRST_SET      0x18
+#define PRCC_K_SOFTRST_CLEAR    0x1C
+static void ux500_uart0_reset(void)
+{
+	void __iomem *prcc_rst_set, *prcc_rst_clr;
+
+	prcc_rst_set = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE +
+			PRCC_K_SOFTRST_SET);
+	prcc_rst_clr = (void __iomem *)IO_ADDRESS(U8500_CLKRST1_BASE +
+			PRCC_K_SOFTRST_CLEAR);
+
+	/* Activate soft reset PRCC_K_SOFTRST_CLEAR */
+	writel((readl(prcc_rst_clr) | 0x1), prcc_rst_clr);
+	udelay(1);
+
+	/* Release soft reset PRCC_K_SOFTRST_SET */
+	writel((readl(prcc_rst_set) | 0x1), prcc_rst_set);
+	udelay(1);
+}
+
+static void ux500_uart0_init(void)
+{
+	int ret;
+
+	ret = nmk_config_pins(mop500_pins_uart0,
+			ARRAY_SIZE(mop500_pins_uart0));
+	if (ret < 0)
+		pr_err("pl011: uart pins_enable failed\n");
+}
+
+static void ux500_uart0_exit(void)
+{
+	int ret;
+
+	ret = nmk_config_pins_sleep(mop500_pins_uart0,
+			ARRAY_SIZE(mop500_pins_uart0));
+	if (ret < 0)
+		pr_err("pl011: uart pins_disable failed\n");
+}
+
+static struct amba_pl011_data uart0_plat = {
+#ifdef CONFIG_STE_DMA40
+	.dma_filter = stedma40_filter,
+	.dma_rx_param = &uart0_dma_cfg_rx,
+	.dma_tx_param = &uart0_dma_cfg_tx,
+#endif
+	.init = ux500_uart0_init,
+	.exit = ux500_uart0_exit,
+	.reset = ux500_uart0_reset,
+};
+
+static struct amba_pl011_data uart1_plat = {
+#ifdef CONFIG_STE_DMA40
+	.dma_filter = stedma40_filter,
+	.dma_rx_param = &uart1_dma_cfg_rx,
+	.dma_tx_param = &uart1_dma_cfg_tx,
+#endif
+};
+
+static struct amba_pl011_data uart2_plat = {
+#ifdef CONFIG_STE_DMA40
+	.dma_filter = stedma40_filter,
+	.dma_rx_param = &uart2_dma_cfg_rx,
+	.dma_tx_param = &uart2_dma_cfg_tx,
+#endif
+};
+
+static void __init mop500_uart_init(void)
+{
+	db8500_add_uart0(&uart0_plat);
+	db8500_add_uart1(&uart1_plat);
+	db8500_add_uart2(&uart2_plat);
+}
+
+static struct platform_device *snowball_platform_devs[] __initdata = {
+	&snowball_led_dev,
+	&snowball_key_dev,
+	&snowball_sbnet_dev,
+	&ab8500_device,
+};
+
+static void __init mop500_init_machine(void)
+{
+	int i2c0_devs;
+
+	mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+
+	u8500_init_devices();
+
+	mop500_pins_init();
+
+	platform_add_devices(mop500_platform_devs,
+			ARRAY_SIZE(mop500_platform_devs));
+
+	mop500_i2c_init();
+	mop500_sdi_init();
+	mop500_spi_init();
+	mop500_uart_init();
+
+	i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+
+	i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+	i2c_register_board_info(2, mop500_i2c2_devices,
+				ARRAY_SIZE(mop500_i2c2_devices));
+
+	/* This board has full regulator constraints */
+	regulator_has_full_constraints();
+}
+
+static void __init snowball_init_machine(void)
+{
+	int i2c0_devs;
+
+	u8500_init_devices();
+
+	snowball_pins_init();
+
+	platform_add_devices(snowball_platform_devs,
+			ARRAY_SIZE(snowball_platform_devs));
+
+	mop500_i2c_init();
+	snowball_sdi_init();
+	mop500_spi_init();
+	mop500_uart_init();
+
+	i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+	i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+	i2c_register_board_info(2, mop500_i2c2_devices,
+				ARRAY_SIZE(mop500_i2c2_devices));
+
+	/* This board has full regulator constraints */
+	regulator_has_full_constraints();
+}
+
+static void __init hrefv60_init_machine(void)
+{
+	int i2c0_devs;
+
+	/*
+	 * The HREFv60 board removed a GPIO expander and routed
+	 * all these GPIO pins to the internal GPIO controller
+	 * instead.
+	 */
+	mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
+
+	u8500_init_devices();
+
+	hrefv60_pins_init();
+
+	platform_add_devices(mop500_platform_devs,
+			ARRAY_SIZE(mop500_platform_devs));
+
+	mop500_i2c_init();
+	hrefv60_sdi_init();
+	mop500_spi_init();
+	mop500_uart_init();
+
+	i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+
+	i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
+
+	i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+	i2c_register_board_info(2, mop500_i2c2_devices,
+				ARRAY_SIZE(mop500_i2c2_devices));
+
+	/* This board has full regulator constraints */
+	regulator_has_full_constraints();
+}
+
+static const char * snowball_dt_board_compat[] = {
+	"calaosystems,snowball-a9500",
+	NULL
+};
+
+MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
+	/* Maintainer: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com> */
+	.atag_offset	= 0x100,
+	.map_io		= u8500_map_io,
+	.init_irq	= ux500_init_irq,
+	/* we re-use nomadik timer here */
+	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= mop500_init_machine,
+MACHINE_END
+
+MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
+	.atag_offset	= 0x100,
+	.map_io		= u8500_map_io,
+	.init_irq	= ux500_init_irq,
+	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= hrefv60_init_machine,
+MACHINE_END
+
+DT_MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
+	.atag_offset	= 0x100,
+	.map_io		= u8500_map_io,
+	.init_irq	= ux500_init_irq,
+	/* we re-use nomadik timer here */
+	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= snowball_init_machine,
+	.dt_compat      = snowball_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 9db68d2..11e15d4 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -43,7 +43,7 @@
 /* This will be overridden by board-specific irq headers */
 #define IRQ_BOARD_END		IRQ_BOARD_START
 
-#ifdef CONFIG_MACH_U8500
+#if defined(CONFIG_MACH_U8500) || defined(CONFIG_MACH_MOP500)
 #include <mach/irqs-board-mop500.h>
 #endif
 
-- 
1.7.5.4



From jason at lakedaemon.net  Fri Mar  2 11:27:38 2012
From: jason at lakedaemon.net (Jason)
Date: Fri, 2 Mar 2012 11:27:38 -0500
Subject: [PATCH 3/4] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <20120302071939.A1BE83E2D8A@localhost>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>
 <20120302071939.A1BE83E2D8A@localhost>
Message-ID: <20120302162738.GH11986@titan.lakedaemon.net>

On Fri, Mar 02, 2012 at 01:19:39AM -0600, Grant Likely wrote:
> On Thu,  1 Mar 2012 18:20:54 +0000, Jason Cooper <jason at lakedaemon.net> wrote:
> > The comment at mach-kirkwood/common.c:469, says this device is in every
> > kirkwood board.  So, it is placed in kirkwood.dtsi.
> > 
> > Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> > ---
> >  arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
> >  arch/arm/mach-kirkwood/board-dt.c |    1 -
> >  arch/arm/mach-kirkwood/common.c   |    2 +-
> >  arch/arm/mach-kirkwood/common.h   |    1 -
> >  drivers/rtc/rtc-mv.c              |   19 +++++++++++++++++++
> >  5 files changed, 26 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
> > index 771c6bb..5fb185c 100644
> > --- a/arch/arm/boot/dts/kirkwood.dtsi
> > +++ b/arch/arm/boot/dts/kirkwood.dtsi
> > @@ -2,5 +2,11 @@
> >  
> >  / {
> >  	compatible = "marvell,kirkwood";
> > +
> > +	rtc at f1010300 {
> > +		compatible = "marvell,rtc";
> > +		reg = <0xf1010300 0x1f>;
> > +		interrupts = <53>;
> > +	};
> >  };
> >  
> > diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> > index a0cc28b..6fc41ae 100644
> > --- a/arch/arm/mach-kirkwood/board-dt.c
> > +++ b/arch/arm/mach-kirkwood/board-dt.c
> > @@ -135,7 +135,6 @@ static void __init kirkwood_dt_init(void)
> >  #endif
> >  
> >  	/* internal devices that every board has */
> > -	kirkwood_rtc_init();
> >  	kirkwood_wdt_init();
> >  	kirkwood_xor0_init();
> >  	kirkwood_xor1_init();
> > diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> > index 167b6c8..0c0375f 100644
> > --- a/arch/arm/mach-kirkwood/common.c
> > +++ b/arch/arm/mach-kirkwood/common.c
> > @@ -163,7 +163,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
> >  /*****************************************************************************
> >   * SoC RTC
> >   ****************************************************************************/
> > -void __init kirkwood_rtc_init(void)
> > +static void __init kirkwood_rtc_init(void)
> 
> This undoes the code changed in the previous patch.  If you reorder the patches then
> this change goes away in both.

My goal was to make sure the series could compile with and without fdt
no matter where a bisect might land in the series.  What would cause a
reorder?

> >  {
> >  	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
> >  }
> > diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
> > index c382447..ca08826 100644
> > --- a/arch/arm/mach-kirkwood/common.h
> > +++ b/arch/arm/mach-kirkwood/common.h
> > @@ -53,7 +53,6 @@ void kirkwood_restart(char, const char *);
> >  
> >  char *kirkwood_id(void);
> >  void kirkwood_l2_init(void);
> > -void kirkwood_rtc_init(void);
> >  void kirkwood_wdt_init(void);
> >  void kirkwood_xor0_init(void);
> >  void kirkwood_xor1_init(void);
> > diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c
> > index 768e2ed..38abbf7 100644
> > --- a/drivers/rtc/rtc-mv.c
> > +++ b/drivers/rtc/rtc-mv.c
> > @@ -12,6 +12,8 @@
> >  #include <linux/bcd.h>
> >  #include <linux/io.h>
> >  #include <linux/platform_device.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of.h>
> >  #include <linux/delay.h>
> >  #include <linux/gfp.h>
> >  #include <linux/module.h>
> > @@ -218,10 +220,15 @@ static int __devinit mv_rtc_probe(struct platform_device *pdev)
> >  {
> >  	struct resource *res;
> >  	struct rtc_plat_data *pdata;
> > +	struct device_node *np = pdev->dev.of_node;
> >  	resource_size_t size;
> >  	u32 rtc_time;
> >  
> >  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +
> > +	if (np)
> > +		of_address_to_resource(np, 0, res);
> > +
> 
> This should not be needed.  The of_platform_populate() code should have
> filled the platform_device with mem resources.

fixed in next version.

> >  	if (!res)
> >  		return -ENODEV;
> >  
> > @@ -257,6 +264,8 @@ static int __devinit mv_rtc_probe(struct platform_device *pdev)
> >  
> >  	pdata->irq = platform_get_irq(pdev, 0);
> >  
> > +	of_property_read_u32(np, "interrupts", &pdata->irq);
> > +
> 
> Definitely don't do this.  Same as with memory regions, the irq will be
> pre-populated in the platform device resource table.  platform_get_irq()
> should already work.

Same.

> >  	platform_set_drvdata(pdev, pdata);
> >  
> >  	if (pdata->irq >= 0) {
> > @@ -294,11 +303,21 @@ static int __exit mv_rtc_remove(struct platform_device *pdev)
> >  	return 0;
> >  }
> >  
> > +#ifdef CONFIG_OF
> > +static struct of_device_id rtc_mv_of_match_table[] = {
> > +	{ .compatible = "marvell,rtc", },
> > +	{}
> > +};
> > +#else
> > +#define rtc_mv_of_match_table NULL
> > +#endif
> > +
> >  static struct platform_driver mv_rtc_driver = {
> >  	.remove		= __exit_p(mv_rtc_remove),
> >  	.driver		= {
> >  		.name	= "rtc-mv",
> >  		.owner	= THIS_MODULE,
> > +		.of_match_table = rtc_mv_of_match_table,
> 
> should be:
> 		.of_match_table = of_match_ptr(rtc_mv_of_match_table),
> 
> that would get rid of the #else clause above.

fixed across kirkwood patches so far.

Thanks for the review.

Jason.


From jason at lakedaemon.net  Fri Mar  2 11:31:21 2012
From: jason at lakedaemon.net (Jason)
Date: Fri, 2 Mar 2012 11:31:21 -0500
Subject: [PATCH 0/4] ARM: kirkwood: fdt: convert kirkwood init funcs to fdt
In-Reply-To: <201203012214.07019.arnd@arndb.de>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203012028.04773.arnd@arndb.de>
 <20120301212353.GC11986@titan.lakedaemon.net>
 <201203012214.07019.arnd@arndb.de>
Message-ID: <20120302163121.GI11986@titan.lakedaemon.net>

On Thu, Mar 01, 2012 at 10:14:06PM +0000, Arnd Bergmann wrote:
> On Thursday 01 March 2012, Jason wrote:
> > On Thu, Mar 01, 2012 at 08:28:04PM +0000, Arnd Bergmann wrote:
> > > On Thursday 01 March 2012, Jason wrote:
> > > > Thanks for the feedback.  I'll redo this series and resubmit.  Did you
> > > > catch my patch from yesterday?
> > > > 
> > > > [PATCH v3] ARM: kirkwood: covert orion-spi to fdt. [1]
> > > 
> > > Yes, I saw that. It looks good and I was just waiting if other people
> > > have comments on it. Maybe you can put it into the same git tree as
> > > these ones when they are ready and you send a pull request.
> > 
> > Okay, I have a local branch, 'dreamplug_dt' based at v3.3-rc3.  It
> > includes the two patches you've already merged into your tree:
> > 
> > c9780e7 ARM: kirkwood: add dreamplug (fdt) support.
> > dbc3c26 ARM: kirkwood: convert uart0 to devicetree.
> > 
> > Plus the spi/flash/partitions, and the most recent series.
> > 
> > Can I just do:
> > 
> > git push linux-kirkwood dreamplug_dt:kirkwood_dt
> > 
> > Then, issue a pull request for
> > 
> > git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt
> > 
> > and reference the first uncommitted patch?
> 
> I have other commit IDs for the two patches that I took from your
> emails, so you should rebase the other patches on top of the
> version that I have in the arm-soc/kirkwood/board branch, otherwise
> we end up with duplicate commits my tree when I pull them again.

Got it, I cherry-picked the series over and incorporated Grant's
suggestions.

> > Most of the googlings for 'pull request' yield github's "click the
> > button", yuck.
> > 
> > Also, is there an equivalent to 'git format-patch/send-email' for pull
> > requests?  The pull requests I've looked at seem awfully consistent in
> > formatting.
> 
> It's "git request-pull".

Of course it is.  :-)  duh.  Thanks.  I'm pushing to my tree now.  I'll
probably submit the series attached to the pull request just so it's
easy to review and easy to pull (hopefully).

Thanks for all the help.

Jason.


From arnd at arndb.de  Fri Mar  2 11:48:51 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 16:48:51 +0000
Subject: [PATCH 4/4] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <20120302153614.GG11986@titan.lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203021456.47896.arnd@arndb.de>
 <20120302153614.GG11986@titan.lakedaemon.net>
Message-ID: <201203021648.52523.arnd@arndb.de>

On Friday 02 March 2012, Jason wrote:
> > 
> > That would make wdt at fed20300/clock-frequency a phandle pointing to the
> > root property, which is not what we want here.
> 
> The 200000000 value is not the actual value used in most drivers [1],
> but rather the speed of the system clock [2] (hence, my inclination to
> make it a root property), the drivers have been pulling this number from
> a global variable [3] and dividing/rounding it as needed for their own needs
> [1].

Ah, I see. If you put a "clock-frequency" property into a device node,
it should definitely be the frequency used by that device, not the system
clock that it is derived from.

> Since it's derived from the SoC core [2], it would seem to make sense to
> have a root "clock-frequency" in the board dts.  Am I missing something?
> Is there a better way to do this?

The correct solution would be to use the clock binding, but I'm not sure
how far we are in making that final or usable.

> > > In any case, the simplest answer is to set clock-frequency in
> > > kirkwood-dreamplug.dts as a root node property, and then each driver
> > > that needs tclk, requests the clock-frequency from the root node.
> > > Hopefully, Grant can chime in on this one.
> > 
> > I think you can just pick a reasonable default value for
> > wdt at fed20300/clock-frequency, and let the board override that
> > by setting it to something else if necessary.
> 
> True, for now, I can just set clock-frequency for each device to the
> exact same value and we'll polish later once we have a better idea of
> the pattern it's following.
> 
> > I suppose this will also change a bit when kirkwood gets moved over to
> > generic clk support in the future and starts using the clk binding
> > instead of what you do now.
> 
> Yes, I don't want to over-think it, but I would like to make sure it's
> in the correct place, since it is a global property of the board.

Andrew Lunn said that he has a patch for plat-orion to use the generic
clock framework. I think we should look at that before introducing
a hack that will have to be removed again very soon.

Kirkwood/orion is probably not a bad platform to add to the initial
set of platforms for which we use the common clk infrastructure,
so maybe the best way forward for you is to take Andrews patches
and build on top of that. It might mean that your follow-on patches
get delayed until v3.5 instead of going into v3.4, but the initial
code you have in arm-soc is working already and you can work on
getting it the clock code right in the initial code.

	Arnd


From b-cousson at ti.com  Fri Mar  2 11:50:12 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:12 +0100
Subject: [PATCH 00/12] mfd: twl: Fix for irqdomain/next + SPARSE_IRQ + MMC
 card detect
Message-ID: <1330707024-23730-1-git-send-email-b-cousson@ti.com>

Hi Samuel and Tony,

Here is a fix + cleanup + SPARSE_IRQ series for TWL4030 and TWL6030.

The first goal was to fix the current regression due to irqdomain
support inside twl-core for OMAP3 + twl4030.

The issue is that there is no quick and dirty fix for that, hence this
exhaustive series started by Felipe to add SPARSE_IRQ support for TWL
modules.

On top of that a bunch of code cleanup are done, and in order to make
the MMC card detect still operational, some fixes are needed in the
board file too.

Due to the modification in the SIH setup API, the twl4030-gpio driver
has to be updated as well.

It was then trivial to add some basic device tree support for the
twl4030-gpio driver.

Please note that this series does depend on the irqdomain/next series
from Grant.

These patches will be probably sent in separate pull request. The only
strong dependency is with the irqdomain series.

This series is available here for reference:
  git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/twl_irq_gpio_cleanup

This is not for pull-request, becasue it is based on irqdomain + OMAP
IRQ DT series + OMAP twl DT series yet to be pushed.

Regards,
Benoit


Benoit Cousson (9):
  mfd: twl-core: Remove references already defined in header file
  mfd: twl-core: Move IRQ allocation into twl[4030|6030]-irq files
  mfd: twl4030-irq: Make SIH SPARSE_IRQ capable
  mfd: twl-*: Change from pr_XXX to dev_XXX macros and various cleanups
  gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ support
  gpio/twl: Add DT support to gpio-twl4030 driver
  arm/dts: twl4030: Add twl4030-gpio node
  mfd: twl4030-irq: Return twl6030_mmc_card_detect IRQ for board setup
  ARM: OMAP2+: board-omap4-*: Do not use anymore TWL6030_IRQ_BASE in board files

Felipe Balbi (3):
  mfd: twl-core: don't depend on pdata->irq_base/end
  mfd: twl-core: remove unneeded header
  mfd: twl4030-irq: micro-optimization on IRQ handler

 .../devicetree/bindings/gpio/gpio-twl4030.txt      |   23 ++++
 arch/arm/boot/dts/twl4030.dtsi                     |    8 ++
 arch/arm/mach-omap2/board-4430sdp.c                |   13 ++-
 arch/arm/mach-omap2/board-omap4panda.c             |   15 ++--
 drivers/gpio/gpio-twl4030.c                        |  111 ++++++++++++--------
 drivers/mfd/twl-core.c                             |   99 +++++++-----------
 drivers/mfd/twl-core.h                             |    4 +-
 drivers/mfd/twl4030-irq.c                          |   87 +++++++++-------
 drivers/mfd/twl6030-irq.c                          |   71 ++++++++-----
 include/linux/i2c/twl.h                            |    2 +-
 10 files changed, 247 insertions(+), 186 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-twl4030.txt



From b-cousson at ti.com  Fri Mar  2 11:50:13 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:13 +0100
Subject: [PATCH 01/12] mfd: twl-core: don't depend on pdata->irq_base/end
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-2-git-send-email-b-cousson@ti.com>

From: Felipe Balbi <balbi at ti.com>

With sparse IRQs the driver shouldn't depend at all on
any IRQ values coming from board-file.

Remove every occurences of pdata->irq_base/end.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Benoit Cousson <b-cousson at ti.com>
---
 drivers/mfd/twl-core.c |   49 ++++++++++++++++++++++++-----------------------
 1 files changed, 25 insertions(+), 24 deletions(-)

diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 4970d43..f28a1dc 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -648,7 +648,8 @@ add_regulator(int num, struct regulator_init_data *pdata,
  */
 
 static int
-add_children(struct twl4030_platform_data *pdata, unsigned long features)
+add_children(struct twl4030_platform_data *pdata, unsigned irq_base,
+		unsigned long features)
 {
 	struct device	*child;
 	unsigned sub_chip_id;
@@ -656,7 +657,7 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
 	if (twl_has_gpio() && pdata->gpio) {
 		child = add_child(SUB_CHIP_ID1, "twl4030_gpio",
 				pdata->gpio, sizeof(*pdata->gpio),
-				false, pdata->irq_base + GPIO_INTR_OFFSET, 0);
+				false, irq_base + GPIO_INTR_OFFSET, 0);
 		if (IS_ERR(child))
 			return PTR_ERR(child);
 	}
@@ -664,7 +665,7 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
 	if (twl_has_keypad() && pdata->keypad) {
 		child = add_child(SUB_CHIP_ID2, "twl4030_keypad",
 				pdata->keypad, sizeof(*pdata->keypad),
-				true, pdata->irq_base + KEYPAD_INTR_OFFSET, 0);
+				true, irq_base + KEYPAD_INTR_OFFSET, 0);
 		if (IS_ERR(child))
 			return PTR_ERR(child);
 	}
@@ -672,7 +673,7 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
 	if (twl_has_madc() && pdata->madc) {
 		child = add_child(2, "twl4030_madc",
 				pdata->madc, sizeof(*pdata->madc),
-				true, pdata->irq_base + MADC_INTR_OFFSET, 0);
+				true, irq_base + MADC_INTR_OFFSET, 0);
 		if (IS_ERR(child))
 			return PTR_ERR(child);
 	}
@@ -688,7 +689,7 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
 		sub_chip_id = twl_map[TWL_MODULE_RTC].sid;
 		child = add_child(sub_chip_id, "twl_rtc",
 				NULL, 0,
-				true, pdata->irq_base + RTC_INTR_OFFSET, 0);
+				true, irq_base + RTC_INTR_OFFSET, 0);
 		if (IS_ERR(child))
 			return PTR_ERR(child);
 	}
@@ -741,8 +742,8 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
 				pdata->usb, sizeof(*pdata->usb),
 				true,
 				/* irq0 = USB_PRES, irq1 = USB */
-				pdata->irq_base + USB_PRES_INTR_OFFSET,
-				pdata->irq_base + USB_INTR_OFFSET);
+				irq_base + USB_PRES_INTR_OFFSET,
+				irq_base + USB_INTR_OFFSET);
 
 		if (IS_ERR(child))
 			return PTR_ERR(child);
@@ -790,8 +791,8 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
 			pdata->usb, sizeof(*pdata->usb),
 			true,
 			/* irq1 = VBUS_PRES, irq0 = USB ID */
-			pdata->irq_base + USBOTG_INTR_OFFSET,
-			pdata->irq_base + USB_PRES_INTR_OFFSET);
+			irq_base + USBOTG_INTR_OFFSET,
+			irq_base + USB_PRES_INTR_OFFSET);
 
 		if (IS_ERR(child))
 			return PTR_ERR(child);
@@ -818,7 +819,7 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
 
 	if (twl_has_pwrbutton() && twl_class_is_4030()) {
 		child = add_child(1, "twl4030_pwrbutton",
-				NULL, 0, true, pdata->irq_base + 8 + 0, 0);
+				NULL, 0, true, irq_base + 8 + 0, 0);
 		if (IS_ERR(child))
 			return PTR_ERR(child);
 	}
@@ -1052,8 +1053,8 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
 		child = add_child(3, "twl4030_bci",
 				pdata->bci, sizeof(*pdata->bci), false,
 				/* irq0 = CHG_PRES, irq1 = BCI */
-				pdata->irq_base + BCI_PRES_INTR_OFFSET,
-				pdata->irq_base + BCI_INTR_OFFSET);
+				irq_base + BCI_PRES_INTR_OFFSET,
+				irq_base + BCI_INTR_OFFSET);
 		if (IS_ERR(child))
 			return PTR_ERR(child);
 	}
@@ -1187,6 +1188,8 @@ static int twl_remove(struct i2c_client *client)
 static int __devinit
 twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 {
+	int				irq_base;
+	int				irq_end;
 	int				status;
 	unsigned			i;
 	struct twl4030_platform_data	*pdata = client->dev.platform_data;
@@ -1215,15 +1218,15 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		return -EINVAL;
 	}
 
-	status = irq_alloc_descs(-1, pdata->irq_base, nr_irqs, 0);
+	status = irq_alloc_descs(-1, 0, nr_irqs, 0);
 	if (IS_ERR_VALUE(status)) {
 		dev_err(&client->dev, "Fail to allocate IRQ descs\n");
 		return status;
 	}
 
-	pdata->irq_base = status;
-	pdata->irq_end = pdata->irq_base + nr_irqs;
-	irq_domain_add_legacy(node, nr_irqs, pdata->irq_base, 0,
+	irq_base = status;
+	irq_end = irq_base + nr_irqs;
+	irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
 			      &irq_domain_simple_ops, NULL);
 
 	if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) {
@@ -1277,16 +1280,14 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		twl4030_power_init(pdata->power);
 
 	/* Maybe init the T2 Interrupt subsystem */
-	if (client->irq
-			&& pdata->irq_base
-			&& pdata->irq_end > pdata->irq_base) {
+	if (client->irq) {
 		if (twl_class_is_4030()) {
 			twl4030_init_chip_irq(id->name);
-			status = twl4030_init_irq(client->irq, pdata->irq_base,
-			pdata->irq_end);
+			status = twl4030_init_irq(client->irq, irq_base,
+			irq_end);
 		} else {
-			status = twl6030_init_irq(client->irq, pdata->irq_base,
-			pdata->irq_end);
+			status = twl6030_init_irq(client->irq, irq_base,
+			irq_end);
 		}
 
 		if (status < 0)
@@ -1309,7 +1310,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 	if (node)
 		status = of_platform_populate(node, NULL, NULL, &client->dev);
 	if (status)
-		status = add_children(pdata, id->driver_data);
+		status = add_children(pdata, irq_base, id->driver_data);
 
 fail:
 	if (status < 0)
-- 
1.7.0.4



From b-cousson at ti.com  Fri Mar  2 11:50:15 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:15 +0100
Subject: [PATCH 03/12] mfd: twl-core: Remove references already defined in
 header file
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-4-git-send-email-b-cousson@ti.com>

The twl-core exported functions are already declared in twl-core.h

Include the header file instead or re-declaring the functions.

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/mfd/twl-core.c |    7 ++-----
 1 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index e612678..d0f08b0 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -45,6 +45,8 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 
+#include "twl-core.h"
+
 /*
  * The TWL4030 "Triton 2" is one of a family of a multi-function "Power
  * Management and System Companion Device" chips originally designed for
@@ -1150,11 +1152,6 @@ static void clocks_init(struct device *dev,
 
 /*----------------------------------------------------------------------*/
 
-int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end);
-int twl4030_exit_irq(void);
-int twl4030_init_chip_irq(const char *chip);
-int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end);
-int twl6030_exit_irq(void);
 
 static int twl_remove(struct i2c_client *client)
 {
-- 
1.7.0.4



From b-cousson at ti.com  Fri Mar  2 11:50:14 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:14 +0100
Subject: [PATCH 02/12] mfd: twl-core: remove unneeded header
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-3-git-send-email-b-cousson@ti.com>

From: Felipe Balbi <balbi at ti.com>

This driver doesn't really need <plat/cpu.h>, so remove it.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/mfd/twl-core.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index f28a1dc..e612678 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -45,10 +45,6 @@
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-#include <plat/cpu.h>
-#endif
-
 /*
  * The TWL4030 "Triton 2" is one of a family of a multi-function "Power
  * Management and System Companion Device" chips originally designed for
-- 
1.7.0.4



From b-cousson at ti.com  Fri Mar  2 11:50:17 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:17 +0100
Subject: [PATCH 05/12] mfd: twl4030-irq: Make SIH SPARSE_IRQ capable
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-6-git-send-email-b-cousson@ti.com>

twl4030 is using a two level irq controllers infrastruture.
So far, only the first level was using dynamic irq_desc allocation
to be able to have irq_domain support for device tree.
There is a need to allocate separate irq_descs for the SIH too to
avoid hacking the first level with interrupts from the second level.

Add an irq_base parameter to allow the caller to provide the base from
pdata or from dynamic allocation.

Affect TWL4030_NR_IRQS to the twl-core IRQs only.

Moreover that will allow the extraction of the of_node pointer for further
Device Tree conversion.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Benoit Cousson <b-cousson at ti.com>
---
 drivers/gpio/gpio-twl4030.c |    3 ++-
 drivers/mfd/twl4030-irq.c   |   23 ++++++-----------------
 include/linux/i2c/twl.h     |    2 +-
 3 files changed, 9 insertions(+), 19 deletions(-)

diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index b8b4f22..697396c 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -404,7 +404,8 @@ static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
 				"can't dispatch IRQs from modules\n");
 			goto no_irqs;
 		}
-		ret = twl4030_sih_setup(TWL4030_MODULE_GPIO);
+		ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO,
+					pdata->irq_base);
 		if (ret < 0)
 			return ret;
 		WARN_ON(ret != pdata->irq_base);
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index 3b34531..faf3318 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -625,30 +625,23 @@ static irqreturn_t handle_twl4030_sih(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
-static unsigned twl4030_irq_next;
-
 /* returns the first IRQ used by this SIH bank,
  * or negative errno
  */
-int twl4030_sih_setup(int module)
+int twl4030_sih_setup(struct device *dev, int module, int irq_base)
 {
 	int			sih_mod;
 	const struct sih	*sih = NULL;
 	struct sih_agent	*agent;
 	int			i, irq;
 	int			status = -EINVAL;
-	unsigned		irq_base = twl4030_irq_next;
 
 	/* only support modules with standard clear-on-read for now */
 	for (sih_mod = 0, sih = sih_modules;
 			sih_mod < nr_sih_modules;
 			sih_mod++, sih++) {
 		if (sih->module == module && sih->set_cor) {
-			if (!WARN((irq_base + sih->bits) > NR_IRQS,
-					"irq %d for %s too big\n",
-					irq_base + sih->bits,
-					sih->name))
-				status = 0;
+			status = 0;
 			break;
 		}
 	}
@@ -659,8 +652,6 @@ int twl4030_sih_setup(int module)
 	if (!agent)
 		return -ENOMEM;
 
-	status = 0;
-
 	agent->irq_base = irq_base;
 	agent->sih = sih;
 	agent->imr = ~0;
@@ -676,8 +667,6 @@ int twl4030_sih_setup(int module)
 		activate_irq(irq);
 	}
 
-	twl4030_irq_next += i;
-
 	/* replace generic PIH handler (handle_simple_irq) */
 	irq = sih_mod + twl4030_irq_base;
 	irq_set_handler_data(irq, agent);
@@ -686,7 +675,7 @@ int twl4030_sih_setup(int module)
 				      agent->irq_name ?: sih->name, NULL);
 
 	pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
-			irq, irq_base, twl4030_irq_next - 1);
+			irq, irq_base, irq_base + i - 1);
 
 	return status < 0 ? status : irq_base;
 }
@@ -750,12 +739,12 @@ int twl4030_init_irq(struct device *dev, int irq_num)
 		irq_set_nested_thread(i, 1);
 		activate_irq(i);
 	}
-	twl4030_irq_next = i;
+
 	pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
-			irq_num, irq_base, twl4030_irq_next - 1);
+			irq_num, irq_base, irq_end);
 
 	/* ... and the PWR_INT module ... */
-	status = twl4030_sih_setup(TWL4030_MODULE_INT);
+	status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
 	if (status < 0) {
 		pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
 		goto fail;
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 78d3465..8b9904a 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -751,7 +751,7 @@ struct twl4030_platform_data {
 
 /*----------------------------------------------------------------------*/
 
-int twl4030_sih_setup(int module);
+int twl4030_sih_setup(struct device *dev, int module, int irq_base);
 
 /* Offsets to Power Registers */
 #define TWL4030_VDAC_DEV_GRP		0x3B
-- 
1.7.0.4



From b-cousson at ti.com  Fri Mar  2 11:50:16 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:16 +0100
Subject: [PATCH 04/12] mfd: twl-core: Move IRQ allocation into
 twl[4030|6030]-irq files
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-5-git-send-email-b-cousson@ti.com>

During DT adaptation, the irq_alloc_desc was added into twl-core, but
due to the rather different and weird IRQ management required by the twl4030,
it is much better to have a different approach for it.
The issue is that twl4030 uses a two level IRQ mechanism but handles all the
PWR interrupts as part of the twl-core interrupt range. It ends up with a
range of 16 interrupts total for CORE and PWR.

The other twl4030 functionalities already have a dedicated driver and thus
their IRQs and irqdomain can and should be defined localy.

twl6030 is using a single level IRQ controller and thus does not require any
trick.

Move the irq_alloc_desc and irq_domain_add_legacy in twl4030-irq and
twl6030-irq.

Allocate together CORE and PWR IRQs for twl4030-irq.

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/mfd/twl-core.c    |   29 +++++------------------------
 drivers/mfd/twl-core.h    |    4 ++--
 drivers/mfd/twl4030-irq.c |   29 +++++++++++++++++++++++++++--
 drivers/mfd/twl6030-irq.c |   31 ++++++++++++++++++++++---------
 4 files changed, 56 insertions(+), 37 deletions(-)

diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index d0f08b0..1c1b7d1 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -147,9 +147,6 @@
 
 #define TWL_MODULE_LAST TWL4030_MODULE_LAST
 
-#define TWL4030_NR_IRQS    34 /* core:8, power:8, gpio: 18 */
-#define TWL6030_NR_IRQS    20
-
 /* Base Address defns for twl4030_map[] */
 
 /* subchip/slave 0 - USB ID */
@@ -1182,17 +1179,12 @@ static int __devinit
 twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 {
 	int				irq_base;
-	int				irq_end;
 	int				status;
 	unsigned			i;
 	struct twl4030_platform_data	*pdata = client->dev.platform_data;
 	struct device_node		*node = client->dev.of_node;
 	u8 temp;
 	int ret = 0;
-	int nr_irqs = TWL4030_NR_IRQS;
-
-	if ((id->driver_data) & TWL6030_CLASS)
-		nr_irqs = TWL6030_NR_IRQS;
 
 	if (node && !pdata) {
 		/*
@@ -1211,17 +1203,6 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		return -EINVAL;
 	}
 
-	status = irq_alloc_descs(-1, 0, nr_irqs, 0);
-	if (IS_ERR_VALUE(status)) {
-		dev_err(&client->dev, "Fail to allocate IRQ descs\n");
-		return status;
-	}
-
-	irq_base = status;
-	irq_end = irq_base + nr_irqs;
-	irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
-			      &irq_domain_simple_ops, NULL);
-
 	if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) {
 		dev_dbg(&client->dev, "can't talk I2C?\n");
 		return -EIO;
@@ -1276,15 +1257,15 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 	if (client->irq) {
 		if (twl_class_is_4030()) {
 			twl4030_init_chip_irq(id->name);
-			status = twl4030_init_irq(client->irq, irq_base,
-			irq_end);
+			irq_base = twl4030_init_irq(&client->dev, client->irq);
 		} else {
-			status = twl6030_init_irq(client->irq, irq_base,
-			irq_end);
+			irq_base = twl6030_init_irq(&client->dev, client->irq);
 		}
 
-		if (status < 0)
+		if (irq_base < 0) {
+			status = irq_base;
 			goto fail;
+		}
 	}
 
 	/* Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
diff --git a/drivers/mfd/twl-core.h b/drivers/mfd/twl-core.h
index 8c50a55..6ff99dc 100644
--- a/drivers/mfd/twl-core.h
+++ b/drivers/mfd/twl-core.h
@@ -1,9 +1,9 @@
 #ifndef __TWL_CORE_H__
 #define __TWL_CORE_H__
 
-extern int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end);
+extern int twl6030_init_irq(struct device *dev, int irq_num);
 extern int twl6030_exit_irq(void);
-extern int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end);
+extern int twl4030_init_irq(struct device *dev, int irq_num);
 extern int twl4030_exit_irq(void);
 extern int twl4030_init_chip_irq(const char *chip);
 
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index b69bb51..3b34531 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -28,10 +28,13 @@
  */
 
 #include <linux/init.h>
+#include <linux/export.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/slab.h>
 
+#include <linux/of.h>
+#include <linux/irqdomain.h>
 #include <linux/i2c/twl.h>
 
 #include "twl-core.h"
@@ -53,6 +56,8 @@
  *	base + 8  .. base + 15	SIH for PWR_INT
  *	base + 16 .. base + 33	SIH for GPIO
  */
+#define TWL4030_CORE_NR_IRQS	8
+#define TWL4030_PWR_NR_IRQS	8
 
 /* PIH register offsets */
 #define REG_PIH_ISR_P1			0x01
@@ -694,14 +699,34 @@ int twl4030_sih_setup(int module)
 /* FIXME pass in which interrupt line we'll use ... */
 #define twl_irq_line	0
 
-int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
+int twl4030_init_irq(struct device *dev, int irq_num)
 {
 	static struct irq_chip	twl4030_irq_chip;
+	int			irq_base, irq_end, nr_irqs;
+	struct			device_node *node = dev->of_node;
 
 	int			status;
 	int			i;
 
 	/*
+	 * TWL core and pwr interrupts must be contiguous because
+	 * the hwirqs numbers are defined contiguously from 1 to 15.
+	 * Create only one domain for both.
+	 */
+	nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS;
+
+	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+	if (IS_ERR_VALUE(irq_base)) {
+		dev_err(dev, "Fail to allocate IRQ descs\n");
+		return irq_base;
+	}
+
+	irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
+			      &irq_domain_simple_ops, NULL);
+
+	irq_end = irq_base + TWL4030_CORE_NR_IRQS;
+
+	/*
 	 * Mask and clear all TWL4030 interrupts since initially we do
 	 * not have any TWL4030 module interrupt handlers present
 	 */
@@ -745,7 +770,7 @@ int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
 		goto fail_rqirq;
 	}
 
-	return status;
+	return irq_base;
 fail_rqirq:
 	/* clean up twl4030_sih_setup */
 fail:
diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
index c6b456a..b4d5e0e 100644
--- a/drivers/mfd/twl6030-irq.c
+++ b/drivers/mfd/twl6030-irq.c
@@ -39,6 +39,8 @@
 #include <linux/i2c/twl.h>
 #include <linux/platform_device.h>
 #include <linux/suspend.h>
+#include <linux/of.h>
+#include <linux/irqdomain.h>
 
 #include "twl-core.h"
 
@@ -53,6 +55,7 @@
  * specifies mapping between interrupt number and the associated module.
  *
  */
+#define TWL6030_NR_IRQS    20
 
 static int twl6030_interrupt_mapping[24] = {
 	PWR_INTR_OFFSET,	/* Bit 0	PWRON			*/
@@ -237,11 +240,6 @@ int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
 	return 0;
 }
 
-/*----------------------------------------------------------------------*/
-
-static unsigned twl6030_irq_next;
-
-/*----------------------------------------------------------------------*/
 int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
 {
 	int ret;
@@ -340,8 +338,10 @@ int twl6030_mmc_card_detect(struct device *dev, int slot)
 }
 EXPORT_SYMBOL(twl6030_mmc_card_detect);
 
-int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
+int twl6030_init_irq(struct device *dev, int irq_num)
 {
+	struct			device_node *node = dev->of_node;
+	int			nr_irqs, irq_base, irq_end;
 
 	int	status = 0;
 	int	i;
@@ -350,6 +350,20 @@ int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
 	u8 mask[4];
 
 	static struct irq_chip	twl6030_irq_chip;
+
+	nr_irqs = TWL6030_NR_IRQS;
+
+	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+	if (IS_ERR_VALUE(irq_base)) {
+		dev_err(dev, "Fail to allocate IRQ descs\n");
+		return irq_base;
+	}
+
+	irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
+			      &irq_domain_simple_ops, NULL);
+
+	irq_end = irq_base + nr_irqs;
+
 	mask[1] = 0xFF;
 	mask[2] = 0xFF;
 	mask[3] = 0xFF;
@@ -377,9 +391,8 @@ int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
 		activate_irq(i);
 	}
 
-	twl6030_irq_next = i;
 	pr_info("twl6030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
-			irq_num, irq_base, twl6030_irq_next - 1);
+			irq_num, irq_base, irq_end);
 
 	/* install an irq handler to demultiplex the TWL6030 interrupt */
 	init_completion(&irq_event);
@@ -400,7 +413,7 @@ int twl6030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
 
 	twl_irq = irq_num;
 	register_pm_notifier(&twl6030_irq_pm_notifier_block);
-	return status;
+	return irq_base;
 
 fail_kthread:
 	free_irq(irq_num, &irq_event);
-- 
1.7.0.4



From b-cousson at ti.com  Fri Mar  2 11:50:21 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:21 +0100
Subject: [PATCH 09/12] gpio/twl: Add DT support to gpio-twl4030 driver
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-10-git-send-email-b-cousson@ti.com>

Add the DT support for the I2C GPIO expander inside the twl4030.

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 .../devicetree/bindings/gpio/gpio-twl4030.txt      |   23 ++++++
 drivers/gpio/gpio-twl4030.c                        |   79 ++++++++++++-------
 2 files changed, 73 insertions(+), 29 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-twl4030.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
new file mode 100644
index 0000000..16695d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
@@ -0,0 +1,23 @@
+twl4030 GPIO controller bindings
+
+Required properties:
+- compatible:
+  - "ti,twl4030-gpio" for twl4030 GPIO controller
+- #gpio-cells : Should be two.
+  - first cell is the pin number
+  - second cell is used to specify optional parameters (unused)
+- gpio-controller : Marks the device node as a GPIO controller.
+- #interrupt-cells : Should be 2.
+- interrupt-controller: Mark the device node as an interrupt controller
+  The first cell is the GPIO number.
+  The second cell is not used.
+
+Example:
+
+twl_gpio: gpio {
+    compatible = "ti,twl4030-gpio";
+    #gpio-cells = <2>;
+    gpio-controller;
+    #interrupt-cells = <2>;
+    interrupt-controller;
+};
diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index 49e5c6e..94256fe 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -32,6 +32,8 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/irqdomain.h>
 
 #include <linux/i2c/twl.h>
 
@@ -256,7 +258,8 @@ static int twl_request(struct gpio_chip *chip, unsigned offset)
 		 * and vMMC2 power supplies based on card presence.
 		 */
 		pdata = chip->dev->platform_data;
-		value |= pdata->mmc_cd & 0x03;
+		if (pdata)
+			value |= pdata->mmc_cd & 0x03;
 
 		status = gpio_twl4030_write(REG_GPIO_CTRL, value);
 	}
@@ -395,6 +398,7 @@ static int gpio_twl4030_remove(struct platform_device *pdev);
 static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
 {
 	struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
+	struct device_node *node = pdev->dev.of_node;
 	int ret, irq_base;
 
 	/* maybe setup IRQs */
@@ -409,6 +413,9 @@ static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
 		return irq_base;
 	}
 
+	irq_domain_add_legacy(node, TWL4030_GPIO_MAX, irq_base, 0,
+			      &irq_domain_simple_ops, NULL);
+
 	ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO, irq_base);
 	if (ret < 0)
 		return ret;
@@ -416,40 +423,45 @@ static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
 	twl4030_gpio_irq_base = irq_base;
 
 no_irqs:
-	/*
-	 * NOTE:  boards may waste power if they don't set pullups
-	 * and pulldowns correctly ... default for non-ULPI pins is
-	 * pulldown, and some other pins may have external pullups
-	 * or pulldowns.  Careful!
-	 */
-	ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
-	if (ret)
-		dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
-				pdata->pullups, pdata->pulldowns,
-				ret);
-
-	ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
-	if (ret)
-		dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
-				pdata->debounce, pdata->mmc_cd,
-				ret);
-
-	twl_gpiochip.base = pdata->gpio_base;
+	twl_gpiochip.base = -1;
 	twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
 	twl_gpiochip.dev = &pdev->dev;
 
-	/* NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
-	 * is (still) clear if use_leds is set.
-	 */
-	if (pdata->use_leds)
-		twl_gpiochip.ngpio += 2;
+	if (pdata) {
+		twl_gpiochip.base = pdata->gpio_base;
+
+		/*
+		 * NOTE:  boards may waste power if they don't set pullups
+		 * and pulldowns correctly ... default for non-ULPI pins is
+		 * pulldown, and some other pins may have external pullups
+		 * or pulldowns.  Careful!
+		 */
+		ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
+		if (ret)
+			dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
+					pdata->pullups, pdata->pulldowns,
+					ret);
+
+		ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
+		if (ret)
+			dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
+					pdata->debounce, pdata->mmc_cd,
+					ret);
+
+		/*
+		 * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
+		 * is (still) clear if use_leds is set.
+		 */
+		if (pdata->use_leds)
+			twl_gpiochip.ngpio += 2;
+	}
 
 	ret = gpiochip_add(&twl_gpiochip);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
 		twl_gpiochip.ngpio = 0;
 		gpio_twl4030_remove(pdev);
-	} else if (pdata->setup) {
+	} else if (pdata && pdata->setup) {
 		int status;
 
 		status = pdata->setup(&pdev->dev,
@@ -467,7 +479,7 @@ static int gpio_twl4030_remove(struct platform_device *pdev)
 	struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
 	int status;
 
-	if (pdata->teardown) {
+	if (pdata && pdata->teardown) {
 		status = pdata->teardown(&pdev->dev,
 				pdata->gpio_base, TWL4030_GPIO_MAX);
 		if (status) {
@@ -488,12 +500,21 @@ static int gpio_twl4030_remove(struct platform_device *pdev)
 	return -EIO;
 }
 
+static const struct of_device_id twl_gpio_match[] = {
+	{ .compatible = "ti,twl4030-gpio", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, twl_gpio_match);
+
 /* Note:  this hardware lives inside an I2C-based multi-function device. */
 MODULE_ALIAS("platform:twl4030_gpio");
 
 static struct platform_driver gpio_twl4030_driver = {
-	.driver.name	= "twl4030_gpio",
-	.driver.owner	= THIS_MODULE,
+	.driver = {
+		.name	= "twl4030_gpio",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(twl_gpio_match),
+	},
 	.probe		= gpio_twl4030_probe,
 	.remove		= gpio_twl4030_remove,
 };
-- 
1.7.0.4



From b-cousson at ti.com  Fri Mar  2 11:50:22 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:22 +0100
Subject: [PATCH 10/12] arm/dts: twl4030: Add twl4030-gpio node
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-11-git-send-email-b-cousson@ti.com>

Add the twl-gpio node inside twl4030 definition.

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
---
 arch/arm/boot/dts/twl4030.dtsi |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 8be5223..82a27f4 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -18,4 +18,12 @@
 		compatible = "ti,twl4030-rtc";
 		interrupts = <11>;
 	};
+
+	twl_gpio: gpio {
+		compatible = "ti,twl4030-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
 };
-- 
1.7.0.4



From b-cousson at ti.com  Fri Mar  2 11:50:23 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:23 +0100
Subject: [PATCH 11/12] mfd: twl4030-irq: Return twl6030_mmc_card_detect IRQ
 for board setup
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-12-git-send-email-b-cousson@ti.com>

Card detect IRQ from the TWL6030 used to be provided to the MMC
controller code using a statically allocated IRQ scheme:

  card_detect_irq = TWL6030_IRQ_BASE + MMCDETECT_INTR_OFFSET;

This is no longer valid in a SPARSE_IRQ context since there is no more
pre-defined TWL6030_IRQ_BASE.

Return the proper card detect IRQ value in the twl6030_mmc_card_detect_config
that will be called from the MMC controller.

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Rajendra Nayak <rnayak at ti.com>
---
 drivers/mfd/twl6030-irq.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
index a1c7183..4a63de2 100644
--- a/drivers/mfd/twl6030-irq.c
+++ b/drivers/mfd/twl6030-irq.c
@@ -308,7 +308,8 @@ int twl6030_mmc_card_detect_config(void)
 									ret);
 		return ret;
 	}
-	return 0;
+
+	return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
 }
 EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
 
-- 
1.7.0.4



From b-cousson at ti.com  Fri Mar  2 11:50:24 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:24 +0100
Subject: [PATCH 12/12] ARM: OMAP2+: board-omap4-*: Do not use anymore
 TWL6030_IRQ_BASE in board files
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-13-git-send-email-b-cousson@ti.com>

With the introduction of dynamically allocated IRQ in the twl6030 driver,
the board files can no longer rely of static IRQ defines like before.

Retrieve the value dynamically allocated from the mmc -> twl6030 init
callback.

Note: The Panda board does not seems to use the card detect IRQ.

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-4430sdp.c    |   13 +++++++------
 arch/arm/mach-omap2/board-omap4panda.c |   15 ++++++++-------
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 4e90715..79c4eba 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -457,21 +457,22 @@ static struct platform_device omap_vwlan_device = {
 
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 {
-	int ret = 0;
+	int irq = 0;
 	struct platform_device *pdev = container_of(dev,
 				struct platform_device, dev);
 	struct omap_mmc_platform_data *pdata = dev->platform_data;
 
 	/* Setting MMC1 Card detect Irq */
 	if (pdev->id == 0) {
-		ret = twl6030_mmc_card_detect_config();
-		if (ret)
+		irq = twl6030_mmc_card_detect_config();
+		if (irq < 0) {
 			pr_err("Failed configuring MMC1 card detect\n");
-		pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE +
-						MMCDETECT_INTR_OFFSET;
+			return irq;
+		}
+		pdata->slots[0].card_detect_irq = irq;
 		pdata->slots[0].card_detect = twl6030_mmc_card_detect;
 	}
-	return ret;
+	return 0;
 }
 
 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 28fc271..297f30b 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -206,7 +206,7 @@ struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
 
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 {
-	int ret = 0;
+	int irq = 0;
 	struct platform_device *pdev = container_of(dev,
 				struct platform_device, dev);
 	struct omap_mmc_platform_data *pdata = dev->platform_data;
@@ -217,14 +217,15 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 	}
 	/* Setting MMC1 Card detect Irq */
 	if (pdev->id == 0) {
-		ret = twl6030_mmc_card_detect_config();
-		 if (ret)
+		irq = twl6030_mmc_card_detect_config();
+		if (irq < 0) {
 			dev_err(dev, "%s: Error card detect config(%d)\n",
-				__func__, ret);
-		 else
-			pdata->slots[0].card_detect = twl6030_mmc_card_detect;
+				__func__, irq);
+			return irq;
+		}
+		pdata->slots[0].card_detect = twl6030_mmc_card_detect;
 	}
-	return ret;
+	return 0;
 }
 
 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
-- 
1.7.0.4



From b-cousson at ti.com  Fri Mar  2 11:50:20 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:20 +0100
Subject: [PATCH 08/12] gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ
 support
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-9-git-send-email-b-cousson@ti.com>

Do not use the board pdata for irq_base, but allocate them dynamically
to allow a proper support of SPARSE_IRQ.

Fix an unneeded line wrap.

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-twl4030.c |   33 +++++++++++++++++----------------
 1 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index 697396c..49e5c6e 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -395,23 +395,26 @@ static int gpio_twl4030_remove(struct platform_device *pdev);
 static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
 {
 	struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
-	int ret;
+	int ret, irq_base;
 
 	/* maybe setup IRQs */
-	if (pdata->irq_base) {
-		if (is_module()) {
-			dev_err(&pdev->dev,
-				"can't dispatch IRQs from modules\n");
-			goto no_irqs;
-		}
-		ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO,
-					pdata->irq_base);
-		if (ret < 0)
-			return ret;
-		WARN_ON(ret != pdata->irq_base);
-		twl4030_gpio_irq_base = ret;
+	if (is_module()) {
+		dev_err(&pdev->dev, "can't dispatch IRQs from modules\n");
+		goto no_irqs;
+	}
+
+	irq_base = irq_alloc_descs(-1, 0, TWL4030_GPIO_MAX, 0);
+	if (irq_base < 0) {
+		dev_err(&pdev->dev, "Failed to alloc irq_descs\n");
+		return irq_base;
 	}
 
+	ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO, irq_base);
+	if (ret < 0)
+		return ret;
+
+	twl4030_gpio_irq_base = irq_base;
+
 no_irqs:
 	/*
 	 * NOTE:  boards may waste power if they don't set pullups
@@ -443,9 +446,7 @@ no_irqs:
 
 	ret = gpiochip_add(&twl_gpiochip);
 	if (ret < 0) {
-		dev_err(&pdev->dev,
-				"could not register gpiochip, %d\n",
-				ret);
+		dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
 		twl_gpiochip.ngpio = 0;
 		gpio_twl4030_remove(pdev);
 	} else if (pdata->setup) {
-- 
1.7.0.4



From b-cousson at ti.com  Fri Mar  2 11:50:18 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:18 +0100
Subject: [PATCH 06/12] mfd: twl4030-irq: micro-optimization on IRQ handler
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-7-git-send-email-b-cousson@ti.com>

From: Felipe Balbi <balbi at ti.com>

__ffs() will be far faster than the for loop used.

Signed-off-by: Felipe Balbi <balbi at ti.com>
---
 drivers/mfd/twl4030-irq.c |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index faf3318..e6dc8f9 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -293,7 +293,6 @@ static unsigned twl4030_irq_base;
  */
 static irqreturn_t handle_twl4030_pih(int irq, void *devid)
 {
-	int		module_irq;
 	irqreturn_t	ret;
 	u8		pih_isr;
 
@@ -304,12 +303,13 @@ static irqreturn_t handle_twl4030_pih(int irq, void *devid)
 		return IRQ_NONE;
 	}
 
-	/* these handlers deal with the relevant SIH irq status */
-	for (module_irq = twl4030_irq_base;
-			pih_isr;
-			pih_isr >>= 1, module_irq++) {
-		if (pih_isr & 0x1)
-			handle_nested_irq(module_irq);
+	while (pih_isr) {
+		unsigned long	pending = __ffs(pih_isr);
+		unsigned int	irq;
+
+		pih_isr &= ~BIT(pending);
+		irq = pending + twl4030_irq_base;
+		handle_nested_irq(irq);
 	}
 
 	return IRQ_HANDLED;
-- 
1.7.0.4



From b-cousson at ti.com  Fri Mar  2 11:50:19 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 17:50:19 +0100
Subject: [PATCH 07/12] mfd: twl-*: Change from pr_XXX to dev_XXX macros and
 various cleanups
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330707024-23730-8-git-send-email-b-cousson@ti.com>

Since a structure device is available now, use the dev_ macros instead
of the pr_ ones.

Clean some badly formatted comments.
Remove some unused variables.
Move some variable to the place they belong.
Clean some badly wrapped lines.
Align variable definition
Add missing braces in if-then-else block.
Add blank line for better readability.
Move stuff here and there...

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
---
 drivers/mfd/twl-core.c    |   32 ++++++++++++++++++--------------
 drivers/mfd/twl4030-irq.c |   23 +++++++++++------------
 drivers/mfd/twl6030-irq.c |   39 +++++++++++++++++++--------------------
 3 files changed, 48 insertions(+), 46 deletions(-)

diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 1c1b7d1..9bf14ef 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -1174,17 +1174,15 @@ static int twl_remove(struct i2c_client *client)
 	return 0;
 }
 
-/* NOTE:  this driver only handles a single twl4030/tps659x0 chip */
+/* NOTE: This driver only handles a single twl4030/tps659x0 chip */
 static int __devinit
 twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 {
-	int				irq_base;
-	int				status;
-	unsigned			i;
 	struct twl4030_platform_data	*pdata = client->dev.platform_data;
 	struct device_node		*node = client->dev.of_node;
-	u8 temp;
-	int ret = 0;
+	int				irq_base = 0;
+	int				status;
+	unsigned			i;
 
 	if (node && !pdata) {
 		/*
@@ -1214,12 +1212,12 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 	}
 
 	for (i = 0; i < TWL_NUM_SLAVES; i++) {
-		struct twl_client	*twl = &twl_modules[i];
+		struct twl_client *twl = &twl_modules[i];
 
 		twl->address = client->addr + i;
-		if (i == 0)
+		if (i == 0) {
 			twl->client = client;
-		else {
+		} else {
 			twl->client = i2c_new_dummy(client->adapter,
 					twl->address);
 			if (!twl->client) {
@@ -1231,7 +1229,9 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		}
 		mutex_init(&twl->xfer_lock);
 	}
+
 	inuse = true;
+
 	if ((id->driver_data) & TWL6030_CLASS) {
 		twl_id = TWL6030_CLASS_ID;
 		twl_map = &twl6030_map[0];
@@ -1245,8 +1245,8 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 
 	/* read TWL IDCODE Register */
 	if (twl_id == TWL4030_CLASS_ID) {
-		ret = twl_read_idcode_register();
-		WARN(ret < 0, "Error: reading twl_idcode register value\n");
+		status = twl_read_idcode_register();
+		WARN(status < 0, "Error: reading twl_idcode register value\n");
 	}
 
 	/* load power event scripts */
@@ -1268,19 +1268,22 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		}
 	}
 
-	/* Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
+	/*
+	 * Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
 	 * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
 	 * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
 	 */
-
 	if (twl_class_is_4030()) {
+		u8 temp;
+
 		twl_i2c_read_u8(TWL4030_MODULE_INTBR, &temp, REG_GPPUPDCTR1);
 		temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
-		I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
+			I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
 		twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
 	}
 
 	status = -ENODEV;
+
 	if (node)
 		status = of_platform_populate(node, NULL, NULL, &client->dev);
 	if (status)
@@ -1289,6 +1292,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 fail:
 	if (status < 0)
 		twl_remove(client);
+
 	return status;
 }
 
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index e6dc8f9..e523499 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -32,7 +32,6 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/slab.h>
-
 #include <linux/of.h>
 #include <linux/irqdomain.h>
 #include <linux/i2c/twl.h>
@@ -625,7 +624,8 @@ static irqreturn_t handle_twl4030_sih(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
-/* returns the first IRQ used by this SIH bank,
+/*
+ * returns the first IRQ used by this SIH bank,
  * or negative errno
  */
 int twl4030_sih_setup(struct device *dev, int module, int irq_base)
@@ -637,14 +637,14 @@ int twl4030_sih_setup(struct device *dev, int module, int irq_base)
 	int			status = -EINVAL;
 
 	/* only support modules with standard clear-on-read for now */
-	for (sih_mod = 0, sih = sih_modules;
-			sih_mod < nr_sih_modules;
+	for (sih_mod = 0, sih = sih_modules; sih_mod < nr_sih_modules;
 			sih_mod++, sih++) {
 		if (sih->module == module && sih->set_cor) {
 			status = 0;
 			break;
 		}
 	}
+
 	if (status < 0)
 		return status;
 
@@ -674,7 +674,7 @@ int twl4030_sih_setup(struct device *dev, int module, int irq_base)
 	status = request_threaded_irq(irq, NULL, handle_twl4030_sih, 0,
 				      agent->irq_name ?: sih->name, NULL);
 
-	pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
+	dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name,
 			irq, irq_base, irq_base + i - 1);
 
 	return status < 0 ? status : irq_base;
@@ -691,12 +691,10 @@ int twl4030_sih_setup(struct device *dev, int module, int irq_base)
 int twl4030_init_irq(struct device *dev, int irq_num)
 {
 	static struct irq_chip	twl4030_irq_chip;
+	int			status, i;
 	int			irq_base, irq_end, nr_irqs;
 	struct			device_node *node = dev->of_node;
 
-	int			status;
-	int			i;
-
 	/*
 	 * TWL core and pwr interrupts must be contiguous because
 	 * the hwirqs numbers are defined contiguously from 1 to 15.
@@ -725,7 +723,8 @@ int twl4030_init_irq(struct device *dev, int irq_num)
 
 	twl4030_irq_base = irq_base;
 
-	/* install an irq handler for each of the SIH modules;
+	/*
+	 * Install an irq handler for each of the SIH modules;
 	 * clone dummy irq_chip since PIH can't *do* anything
 	 */
 	twl4030_irq_chip = dummy_irq_chip;
@@ -740,13 +739,13 @@ int twl4030_init_irq(struct device *dev, int irq_num)
 		activate_irq(i);
 	}
 
-	pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
+	dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH",
 			irq_num, irq_base, irq_end);
 
 	/* ... and the PWR_INT module ... */
 	status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
 	if (status < 0) {
-		pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
+		dev_err(dev, "sih_setup PWR INT --> %d\n", status);
 		goto fail;
 	}
 
@@ -755,7 +754,7 @@ int twl4030_init_irq(struct device *dev, int irq_num)
 				      IRQF_ONESHOT,
 				      "TWL4030-PIH", NULL);
 	if (status < 0) {
-		pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status);
+		dev_err(dev, "could not claim irq%d: %d\n", irq_num, status);
 		goto fail_rqirq;
 	}
 
diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
index b4d5e0e..a1c7183 100644
--- a/drivers/mfd/twl6030-irq.c
+++ b/drivers/mfd/twl6030-irq.c
@@ -53,7 +53,6 @@
  *
  * We set up IRQs starting at a platform-specified base. An interrupt map table,
  * specifies mapping between interrupt number and the associated module.
- *
  */
 #define TWL6030_NR_IRQS    20
 
@@ -342,14 +341,11 @@ int twl6030_init_irq(struct device *dev, int irq_num)
 {
 	struct			device_node *node = dev->of_node;
 	int			nr_irqs, irq_base, irq_end;
-
-	int	status = 0;
-	int	i;
 	struct task_struct	*task;
-	int ret;
-	u8 mask[4];
-
-	static struct irq_chip	twl6030_irq_chip;
+	static struct irq_chip  twl6030_irq_chip;
+	int			status = 0;
+	int			i;
+	u8			mask[4];
 
 	nr_irqs = TWL6030_NR_IRQS;
 
@@ -367,16 +363,18 @@ int twl6030_init_irq(struct device *dev, int irq_num)
 	mask[1] = 0xFF;
 	mask[2] = 0xFF;
 	mask[3] = 0xFF;
-	ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
-			REG_INT_MSK_LINE_A, 3); /* MASK ALL INT LINES */
-	ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
-			REG_INT_MSK_STS_A, 3); /* MASK ALL INT STS */
-	ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
-			REG_INT_STS_A, 3); /* clear INT_STS_A,B,C */
+
+	/* mask all int lines */
+	twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
+	/* mask all int sts */
+	twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
+	/* clear INT_STS_A,B,C */
+	twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
 
 	twl6030_irq_base = irq_base;
 
-	/* install an irq handler for each of the modules;
+	/*
+	 * install an irq handler for each of the modules;
 	 * clone dummy irq_chip since PIH can't *do* anything
 	 */
 	twl6030_irq_chip = dummy_irq_chip;
@@ -391,22 +389,22 @@ int twl6030_init_irq(struct device *dev, int irq_num)
 		activate_irq(i);
 	}
 
-	pr_info("twl6030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
+	dev_info(dev, "PIH (irq %d) chaining IRQs %d..%d\n",
 			irq_num, irq_base, irq_end);
 
 	/* install an irq handler to demultiplex the TWL6030 interrupt */
 	init_completion(&irq_event);
 
-	status = request_irq(irq_num, handle_twl6030_pih, 0,
-				"TWL6030-PIH", &irq_event);
+	status = request_irq(irq_num, handle_twl6030_pih, 0, "TWL6030-PIH",
+			     &irq_event);
 	if (status < 0) {
-		pr_err("twl6030: could not claim irq%d: %d\n", irq_num, status);
+		dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
 		goto fail_irq;
 	}
 
 	task = kthread_run(twl6030_irq_thread, (void *)irq_num, "twl6030-irq");
 	if (IS_ERR(task)) {
-		pr_err("twl6030: could not create irq %d thread!\n", irq_num);
+		dev_err(dev, "could not create irq %d thread!\n", irq_num);
 		status = PTR_ERR(task);
 		goto fail_kthread;
 	}
@@ -421,6 +419,7 @@ fail_kthread:
 fail_irq:
 	for (i = irq_base; i < irq_end; i++)
 		irq_set_chip_and_handler(i, NULL, NULL);
+
 	return status;
 }
 
-- 
1.7.0.4



From arnd at arndb.de  Fri Mar  2 11:58:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 16:58:11 +0000
Subject: [PATCH 0/4] ARM: kirkwood: fdt: convert kirkwood init funcs to fdt
In-Reply-To: <20120302163121.GI11986@titan.lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203012214.07019.arnd@arndb.de>
 <20120302163121.GI11986@titan.lakedaemon.net>
Message-ID: <201203021658.12047.arnd@arndb.de>

On Friday 02 March 2012, Jason wrote:
> > 
> > I have other commit IDs for the two patches that I took from your
> > emails, so you should rebase the other patches on top of the
> > version that I have in the arm-soc/kirkwood/board branch, otherwise
> > we end up with duplicate commits my tree when I pull them again.
> 
> Got it, I cherry-picked the series over and incorporated Grant's
> suggestions.
> 

Just making sure you know about this one:

git rebase -i --onto arm-soc/kirkwood/board torvalds/master

The '-i' lets you pick which ones you want to move over, then it
applies all patches from the current branch that are not on
torvalds/master on top of the last commit from arm-soc/kirkwood/board.

If you don't know it yet, I suggest you play with this for an hour
or so that will be very well invested time. If you knew this, then nevermind.

	Arnd


From linus.walleij at stericsson.com  Fri Mar  2 11:31:13 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 2 Mar 2012 17:31:13 +0100
Subject: [PATCH] pinctrl: resurrect verbose pinmux-pins
Message-ID: <1330705873-10798-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This reintroduces the verbosity in the pinmux-pins file, now this
file will list all pins, their names, owning device (and if it's
a hog) and also in applicable cases the function and group making
use of that pin right now.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/core.h   |    4 ++++
 drivers/pinctrl/pinmux.c |   34 +++++++++++++++++++++++++++++-----
 2 files changed, 33 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index e1dfdb3..0a52e39 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -12,6 +12,7 @@
 #include <linux/pinctrl/pinconf.h>
 
 struct pinctrl_gpio_range;
+struct pinmux_group;
 
 /**
  * struct pinctrl_dev - pin control class device
@@ -77,6 +78,8 @@ struct pinctrl {
  * @dynamic_name: if the name of this pin was dynamically allocated
  * @lock: a lock to protect the descriptor structure
  * @owner: the device holding this pin or NULL of no device has claimed it
+ * @grp: the pinmux group used for this pin if it is used by a pin group
+ *	or NULL
  */
 struct pin_desc {
 	struct pinctrl_dev *pctldev;
@@ -86,6 +89,7 @@ struct pin_desc {
 	/* These fields only added when supporting pinmux drivers */
 #ifdef CONFIG_PINMUX
 	const char *owner;
+	struct pinmux_group *grp;
 #endif
 };
 
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index f409f16..5785b09 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -76,11 +76,14 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev)
  * @pin: the pin number in the global pin space
  * @owner: a representation of the owner of this pin; typically the device
  *	name that controls its mux function, or the requested GPIO name
+ * @grp: the pinmux group used for this pin or NULL of it is requested as
+ *	a GPIO pin
  * @gpio_range: the range matching the GPIO pin if this is a request for a
  *	single GPIO pin
  */
 static int pin_request(struct pinctrl_dev *pctldev,
 		       int pin, const char *owner,
+		       struct pinmux_group *grp,
 		       struct pinctrl_gpio_range *gpio_range)
 {
 	struct pin_desc *desc;
@@ -104,6 +107,7 @@ static int pin_request(struct pinctrl_dev *pctldev,
 		goto out;
 	}
 	desc->owner = owner;
+	desc->grp = grp;
 	spin_unlock(&desc->lock);
 
 	/* Let each pin increase references to this module */
@@ -181,6 +185,7 @@ static const char *pin_free(struct pinctrl_dev *pctldev, int pin,
 	spin_lock(&desc->lock);
 	owner = desc->owner;
 	desc->owner = NULL;
+	desc->grp = NULL;
 	spin_unlock(&desc->lock);
 	module_put(pctldev->owner);
 
@@ -208,7 +213,7 @@ int pinmux_request_gpio(struct pinctrl_dev *pctldev,
 	if (!owner)
 		return -EINVAL;
 
-	ret = pin_request(pctldev, pin, owner, range);
+	ret = pin_request(pctldev, pin, owner, NULL, range);
 	if (ret < 0)
 		kfree(owner);
 
@@ -259,10 +264,12 @@ int pinmux_gpio_direction(struct pinctrl_dev *pctldev,
  * @pctldev: the device to take the pins on
  * @owner: a representation of the owner of this pin; typically the device
  *	name that controls its mux function
+ * @grp: the pinmux group that will use the pins
  * @group_selector: the group selector containing the pins to acquire
  */
 static int acquire_pins(struct pinctrl_dev *pctldev,
 			const char *owner,
+			struct pinmux_group *grp,
 			unsigned group_selector)
 {
 	const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
@@ -281,7 +288,7 @@ static int acquire_pins(struct pinctrl_dev *pctldev,
 
 	/* Try to allocate all pins in this group, one by one */
 	for (i = 0; i < num_pins; i++) {
-		ret = pin_request(pctldev, pins[i], owner, NULL);
+		ret = pin_request(pctldev, pins[i], owner, grp, NULL);
 		if (ret) {
 			dev_err(pctldev->dev,
 				"could not get request pin %d on device %s - conflicting mux mappings?\n",
@@ -485,7 +492,7 @@ static int pinmux_enable_muxmap(struct pinctrl_dev *pctldev,
 		return -ENOMEM;
 	grp->func_selector = func_selector;
 	grp->group_selector = group_selector;
-	ret = acquire_pins(pctldev, devname, group_selector);
+	ret = acquire_pins(pctldev, devname, grp, group_selector);
 	if (ret) {
 		kfree(grp);
 		return ret;
@@ -606,13 +613,25 @@ static int pinmux_functions_show(struct seq_file *s, void *what)
 	return 0;
 }
 
+static void pinmux_pins_show_groupinfo(struct seq_file *s,
+				       struct pinctrl_dev *pctldev,
+				       struct pinmux_group *grp)
+{
+	const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
+	const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
+
+	seq_printf(s, " function: \"%s\" group: \"%s\"\n",
+		   pmxops->get_function_name(pctldev, grp->func_selector),
+		   pctlops->get_group_name(pctldev, grp->group_selector));
+}
+
 static int pinmux_pins_show(struct seq_file *s, void *what)
 {
 	struct pinctrl_dev *pctldev = s->private;
 	unsigned i, pin;
 
 	seq_puts(s, "Pinmux settings per pin\n");
-	seq_puts(s, "Format: pin (name): owner\n");
+	seq_puts(s, "Format: pin (name): owner [function]\n");
 
 	/* The pin number can be retrived from the pin controller descriptor */
 	for (i = 0; i < pctldev->desc->npins; i++) {
@@ -629,10 +648,15 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
 		    !strcmp(desc->owner, pinctrl_dev_get_name(pctldev)))
 			is_hog = true;
 
-		seq_printf(s, "pin %d (%s): %s%s\n", pin,
+		seq_printf(s, "pin %d (%s): %s%s", pin,
 			   desc->name ? desc->name : "unnamed",
 			   desc->owner ? desc->owner : "UNCLAIMED",
 			   is_hog ? " (HOG)" : "");
+
+		if (desc->grp)
+			pinmux_pins_show_groupinfo(s, pctldev, desc->grp);
+		else
+			seq_printf(s, "\n");
 	}
 
 	return 0;
-- 
1.7.8



From jason at lakedaemon.net  Fri Mar  2 12:02:52 2012
From: jason at lakedaemon.net (Jason)
Date: Fri, 2 Mar 2012 12:02:52 -0500
Subject: [PATCH 4/4] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <201203021648.52523.arnd@arndb.de>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203021456.47896.arnd@arndb.de>
 <20120302153614.GG11986@titan.lakedaemon.net>
 <201203021648.52523.arnd@arndb.de>
Message-ID: <20120302170252.GJ11986@titan.lakedaemon.net>

On Fri, Mar 02, 2012 at 04:48:51PM +0000, Arnd Bergmann wrote:
> On Friday 02 March 2012, Jason wrote:
> > > 
> > > That would make wdt at fed20300/clock-frequency a phandle pointing to the
> > > root property, which is not what we want here.
> > 
> > The 200000000 value is not the actual value used in most drivers [1],
> > but rather the speed of the system clock [2] (hence, my inclination to
> > make it a root property), the drivers have been pulling this number from
> > a global variable [3] and dividing/rounding it as needed for their own needs
> > [1].
> 
> Ah, I see. If you put a "clock-frequency" property into a device node,
> it should definitely be the frequency used by that device, not the system
> clock that it is derived from.

Whew, glad to know I'm not crazy.

> > Since it's derived from the SoC core [2], it would seem to make sense to
> > have a root "clock-frequency" in the board dts.  Am I missing something?
> > Is there a better way to do this?
> 
> The correct solution would be to use the clock binding, but I'm not sure
> how far we are in making that final or usable.
> 
> > > > In any case, the simplest answer is to set clock-frequency in
> > > > kirkwood-dreamplug.dts as a root node property, and then each driver
> > > > that needs tclk, requests the clock-frequency from the root node.
> > > > Hopefully, Grant can chime in on this one.
> > > 
> > > I think you can just pick a reasonable default value for
> > > wdt at fed20300/clock-frequency, and let the board override that
> > > by setting it to something else if necessary.
> > 
> > True, for now, I can just set clock-frequency for each device to the
> > exact same value and we'll polish later once we have a better idea of
> > the pattern it's following.
> > 
> > > I suppose this will also change a bit when kirkwood gets moved over to
> > > generic clk support in the future and starts using the clk binding
> > > instead of what you do now.
> > 
> > Yes, I don't want to over-think it, but I would like to make sure it's
> > in the correct place, since it is a global property of the board.
> 
> Andrew Lunn said that he has a patch for plat-orion to use the generic
> clock framework. I think we should look at that before introducing
> a hack that will have to be removed again very soon.

I asked him for it earlier [1], apparently it's a very invasive patch
series which breaks things.  I would like to look at it as a reference,
even if applying it isn't a good idea.

How about it, Andrew?

> Kirkwood/orion is probably not a bad platform to add to the initial
> set of platforms for which we use the common clk infrastructure,
> so maybe the best way forward for you is to take Andrews patches
> and build on top of that.

Agreed.

> It might mean that your follow-on patches get delayed until v3.5
> instead of going into v3.4, but the initial code you have in arm-soc
> is working already and you can work on getting it the clock code right
> in the initial code.

In [1] I was trying to setup a stand-in, eg kirkwood_get_clock() and
kirkwood_put_clock() that could be replaced once the clock code lands.
That way, we're on the right path, but not blocked waiting for the clock
code.

thx,

Jason.

[1] http://www.spinics.net/lists/arm-kernel/msg162284.html


From tony at atomide.com  Fri Mar  2 12:03:27 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 09:03:27 -0800
Subject: [PATCH 1/4] gpiolib: Add gpiochip_find_by_name() and
 gpio_find_by_chip_name()
In-Reply-To: <20120302075804.F28DB3E2DB4@localhost>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185524.29210.60381.stgit@kaulin.local>
 <20120302075804.F28DB3E2DB4@localhost>
Message-ID: <20120302170327.GF18901@atomide.com>

Hi,

Correcting a typo in the LKML address..

* Grant Likely <grant.likely at secretlab.ca> [120302 01:00]:
> On Thu, 01 Mar 2012 10:55:24 -0800, Tony Lindgren <tony at atomide.com> wrote:
> > Currently there is no way for drivers to request a GPIO on a particular
> > gpio chip. This makes it hard to support multiple GPIO controllers
> > with dynamic GPIO and interrupt numbering, such as with CONFIG_SPARSE_IRQ.
> > 
> > Make it easier for device drivers to find GPIOs on a specific gpio_chip
> > by adding two functions: gpiochip_find_by_name() and gpio_find_by_chip_name().
> > 
> > Note that as gpiochip_find() is already exported, we may as well
> > export gpiochip_find_by_name() too.
> 
> How is the device going to know the name of the gpio controller?  I
> don't particularly like interfaces that find devices by-names since
> I don't think device names can be relied to be stable when devices
> are instantiated from device tree data.

The gpio_chip name + gpio offset is coming from pdata until things
are converted over to use DT.

For DT, this should not be needed, this is needed for removing callbacks
in pdata so we can clean up some drivers and keep them working with
both pdata and DT until things are converted over to DT.

> > +static int match_name(struct gpio_chip *chip, void *data)
> 
> Even though this is a static, please keep the prefix to avoid
> namespace conflicts.  gpiochip_match_name()
> 
> > +{
> > +	const char *name = data;
> 
> This is unnecessary; the void* can be passed directly to sysfs_streq...
> but why is sysfs_streq being used here instead of strcmp?  This is 
> not sysfs related code.

That comes from the bus code, will take a look.
 
> > +
> > +	return sysfs_streq(name, chip->label);
> > +}
> > +
> > +/**
> > + * gpiochip_find_by_name() - iterator for locating a gpio_chip by name
> > + * @name: name of the gpio_chip
> > + *
> > + * Similar to bus_find_device_by_name. It returns a reference to the
> > + * first gpio_chip with matching name. It ignores NULL and empty names.
> > + * If you need to do something more complex, then use gpiochip_find.
> > + */
> > +struct gpio_chip *gpiochip_find_by_name(const char *name)
> > +{
> > +	if (!name || !strcmp(name, ""))
> > +		return NULL;
> > +
> > +	return gpiochip_find((void *)name, match_name);
> 
> Nasty cast.  Can the signature for gpiochip_find be changed to accept
> a (const void *)?

I think so, this too comes from the bus code.

Regards,

Tony 


From jason at lakedaemon.net  Fri Mar  2 12:04:41 2012
From: jason at lakedaemon.net (Jason)
Date: Fri, 2 Mar 2012 12:04:41 -0500
Subject: [PATCH 0/4] ARM: kirkwood: fdt: convert kirkwood init funcs to fdt
In-Reply-To: <201203021658.12047.arnd@arndb.de>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203012214.07019.arnd@arndb.de>
 <20120302163121.GI11986@titan.lakedaemon.net>
 <201203021658.12047.arnd@arndb.de>
Message-ID: <20120302170441.GK11986@titan.lakedaemon.net>

On Fri, Mar 02, 2012 at 04:58:11PM +0000, Arnd Bergmann wrote:
> On Friday 02 March 2012, Jason wrote:
> > > 
> > > I have other commit IDs for the two patches that I took from your
> > > emails, so you should rebase the other patches on top of the
> > > version that I have in the arm-soc/kirkwood/board branch, otherwise
> > > we end up with duplicate commits my tree when I pull them again.
> > 
> > Got it, I cherry-picked the series over and incorporated Grant's
> > suggestions.
> > 
> 
> Just making sure you know about this one:
> 
> git rebase -i --onto arm-soc/kirkwood/board torvalds/master
> 
> The '-i' lets you pick which ones you want to move over, then it
> applies all patches from the current branch that are not on
> torvalds/master on top of the last commit from arm-soc/kirkwood/board.
> 
> If you don't know it yet, I suggest you play with this for an hour
> or so that will be very well invested time. If you knew this, then nevermind.

I use the daylights out of git rebase -i, but hadn't made use of --onto
yet.  Thanks for the tip.

thx,

Jason.


From tony at atomide.com  Fri Mar  2 12:06:01 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 09:06:01 -0800
Subject: [PATCH 2/4] mmc: omap_hsmmc: Use gpio_find_by_chip_name() for
 omap_hsmmc_gpio_init()
In-Reply-To: <4F5060B0.7010703@ti.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185528.29210.85854.stgit@kaulin.local>
 <4F5060B0.7010703@ti.com>
Message-ID: <20120302170600.GG18901@atomide.com>

* Rajendra Nayak <rnayak at ti.com> [120301 21:23]:
> On Friday 02 March 2012 12:25 AM, Tony Lindgren wrote:
> >Use gpio_find_by_chip_name() to find the GPIO pins as they can
> >be dynamically allocated on various gpio_chips.
> >
> >Note that we don't want to touch the platform data as it can
> >now specify the GPIO offset on a named gpio_chip.
> >
> >This removes the need to use callbacks to set the GPIO pins
> >in platform data.
> 
> While one of the reasons for those callbacks was to set the GPIO
> pins in platform data, I guess the other and more important one
> was to make sure the init sequencing between twl4030-gpio and the
> mmc device depending on it was done rightly. Doesn't this patch now
> leave the sequencing to work by luck (in the absence of something
> like deferred probe being in place) like is the case of twl6030 and
> mmc init sequence on OMAP4 already?

Nope :) The difference is that  we can exit and produce a sensible
error to the user about the particular gpio_chip not being available.

Regards,

Tony


From tony at atomide.com  Fri Mar  2 12:08:30 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 09:08:30 -0800
Subject: [PATCH 2/4] mmc: omap_hsmmc: Use gpio_find_by_chip_name() for
 omap_hsmmc_gpio_init()
In-Reply-To: <4F5075EE.1050902@ti.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185528.29210.85854.stgit@kaulin.local>
 <4F5075EE.1050902@ti.com>
Message-ID: <20120302170830.GH18901@atomide.com>

* Rajendra Nayak <rnayak at ti.com> [120301 22:54]:
> On Friday 02 March 2012 12:25 AM, Tony Lindgren wrote:
> >+		if (slot->gpiochip_cd) {
> >+			pr_warning("MMC %s card detect GPIO chip %s unavailable\n",
> >+				slot->name, slot->gpiochip_cd);
> >+			ret = -ENODEV;
> >+			goto err_free_sp;
> 
> This should just return -ENODEV, nothing really to free here.

Thanks, will correct.
 
> >@@ -2093,8 +2123,7 @@ err1:
> >  	platform_set_drvdata(pdev, NULL);
> >  	mmc_free_host(mmc);
> >  err_alloc:
> >-	omap_hsmmc_gpio_free(pdata);
> >-err:
> >+	omap_hsmmc_gpio_free(host);
> 
> This error handling needs to be fixed up. In case
> omap_hsmmc_gpio_init() fails, which already frees up
> any requested gpios, omap_hsmmc_gpio_free() again tries
> freeing gpios.

Hmm that sounds like a separate patch that should be a fixed
before this series?

Regards,

Tony


From plagnioj at jcrosoft.com  Fri Mar  2 12:05:54 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 2 Mar 2012 18:05:54 +0100
Subject: [PATCH] Initial Device Tree system for Snowball
In-Reply-To: <1330703567-17925-1-git-send-email-niklas.hernaeus@stericsson.com>
References: <1330703567-17925-1-git-send-email-niklas.hernaeus@stericsson.com>
Message-ID: <20120302170554.GA21255@game.jcrosoft.org>

On 16:52 Fri 02 Mar     , Niklas Hernaeus wrote:
> From: Niklas Hernaeus <niklas.hernaeus at linaro.org>
> 
> This is the base system for using Device Tree for Snowball.
> The new boardfile is a slightly modified copy of the original board file,
> so new Device Tree stuff can simply be added and code removed, while
> functionality stays the same.
duplicating the code is not a good idea

do the invert put the minimum in c and then add the rest slowly via DT

Best Regards,
J.


From tony at atomide.com  Fri Mar  2 12:16:46 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 09:16:46 -0800
Subject: [PATCH 3/4] mmc: omap_hsmmc: Use GPIO offset for external GPIO
 chips
In-Reply-To: <4F50628C.9080706@ti.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185532.29210.32421.stgit@kaulin.local>
 <4F50628C.9080706@ti.com>
Message-ID: <20120302171646.GI18901@atomide.com>

* Rajendra Nayak <rnayak at ti.com> [120301 21:31]:
> On Friday 02 March 2012 12:25 AM, Tony Lindgren wrote:
> >--- a/arch/arm/mach-omap2/board-3430sdp.c
> >+++ b/arch/arm/mach-omap2/board-3430sdp.c
> >@@ -231,14 +231,16 @@ static struct omap2_hsmmc_info mmc[] = {
> >  		 * so the SIM card isn't used; else 4 bits.
> >  		 */
> >  		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
> >+		.gpiochip_cd	= "twl4030_gpio",
> >+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
> >  		.gpio_wp	= 4,
> >-		.deferred	= true,
> 
> Shouldn't this patch completely get rid of all the 'deferred'
> infrastructure that was put in place, including the
> omap_hsmmc_late_init() function, since there is no need for it
> anymore?

Yes, that was needed as a fix so unfortunately there's a little
bit going back and forth. But now we can get rid of other stuff
too in addition to deferred omap_hsmmc_late_init(), we can remove
init and cleanup callbacks for hsmmc. I'll do another patch for
that.

> >--- a/arch/arm/mach-omap2/board-omap3pandora.c
> >+++ b/arch/arm/mach-omap2/board-omap3pandora.c
> >@@ -270,19 +270,19 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
> >  	{
> >  		.mmc		= 1,
> >  		.caps		= MMC_CAP_4_BIT_DATA,
> >-		.gpio_cd	= -EINVAL,
> >+		.gpiochip_cd	= "twl4030_gpio",
> >+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
> >  		.gpio_wp	= 126,
> >  		.ext_clock	= 0,
> >-		.deferred	= true,
> >  	},
> >  	{
> >  		.mmc		= 2,
> >  		.caps		= MMC_CAP_4_BIT_DATA,
> >-		.gpio_cd	= -EINVAL,
> >+		.gpiochip_cd	= "twl4030_gpio",
> >+		.gpio_cd	= 0,	/* mmc0_cd offset in twl4030 */
> 
> This one should be gpio_cd = 1,

Thanks, will correct.

Regards,

Tony 


From swarren at nvidia.com  Fri Mar  2 12:17:17 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Fri, 2 Mar 2012 09:17:17 -0800
Subject: [PATCH] pinctrl: fix the pin descriptor kerneldoc
In-Reply-To: <1330703621-4044-1-git-send-email-linus.walleij@stericsson.com>
References: <1330703621-4044-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861969@HQMAIL01.nvidia.com>

Linus Walleij wrote at Friday, March 02, 2012 8:54 AM:
> The introduction of the owner field on the pin descriptor was not
> properly documented so fix this up.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

I did have this fix buried later in my patch series, but it's probably a
good idea to patch it separately before then.

Acked-by: Stephen Warren <swarren at nvidia.com>

-- 
nvpublic



From swarren at nvidia.com  Fri Mar  2 12:22:14 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Fri, 2 Mar 2012 09:22:14 -0800
Subject: [PATCH] pinctrl: resurrect verbose pinmux-pins
In-Reply-To: <1330705873-10798-1-git-send-email-linus.walleij@stericsson.com>
References: <1330705873-10798-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861978@HQMAIL01.nvidia.com>

Linus Walleij wrote at riday, March 02, 2012 9:31 AM:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This reintroduces the verbosity in the pinmux-pins file, now this
> file will list all pins, their names, owning device (and if it's
> a hog) and also in applicable cases the function and group making
> use of that pin right now.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

It'd be nice if we could defer this fix until after all the API rework,
because it'll cause all kinds of conflicts otherwise.

The type "struct pinmux_group" you added to struct pin_desc is removed by
patches in my series. If this patch goes in before my series, it'd be best
if it just stored the char* for the function instead of that type, so the
rework by my patche series will be smaller.

I don't think it make sense to store a "group" as owning a pin; each pin
should be part of one muxing group as defined by the hardware so there isn't
a concept of "which group acquired the pin", just "which function is
programmed on the pin". Even if multiple "virtual groups" contain a pin
(which I think would be a bad idea) then the important information from a
HW perspective is the function and not the arbitrary group name.

-- 
nvpublic



From tony at atomide.com  Fri Mar  2 12:22:51 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 09:22:51 -0800
Subject: [PATCH 4/4] mmc: omap_hsmmc: Simplify init for twl6030 MMC
 card detect
In-Reply-To: <4F50643B.9050500@ti.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185535.29210.71546.stgit@kaulin.local>
 <4F50643B.9050500@ti.com>
Message-ID: <20120302172251.GJ18901@atomide.com>

* Rajendra Nayak <rnayak at ti.com> [120301 21:38]:
> On Friday 02 March 2012 12:25 AM, Tony Lindgren wrote:
> >--- a/arch/arm/mach-omap2/board-omap4panda.c
> >+++ b/arch/arm/mach-omap2/board-omap4panda.c
> >@@ -153,8 +153,8 @@ static struct omap2_hsmmc_info mmc[] = {
> >  	{
> >  		.mmc		= 1,
> >  		.caps		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
> >-		.gpio_wp	= -EINVAL,
> >  		.gpio_cd	= -EINVAL,
> >+		.gpio_wp	= -EINVAL,
> 
> stray change.

Hmm I'd like to keep this change before this ordering gets copied
to ten other board files that we may have in testing-board for a while..
I'll add a comment to the patch description about that.

> >--- a/drivers/mmc/host/omap_hsmmc.c
> >+++ b/drivers/mmc/host/omap_hsmmc.c
> >@@ -34,6 +34,7 @@
> >  #include<linux/gpio.h>
> >  #include<linux/regulator/consumer.h>
> >  #include<linux/pm_runtime.h>
> >+#include<linux/i2c/twl.h>
> >  #include<plat/dma.h>
> >  #include<mach/hardware.h>
> >  #include<plat/board.h>
> >@@ -578,6 +579,32 @@ static void omap_hsmmc_gpio_free(struct omap_hsmmc_host *host)
> >  		gpio_free(host->gpio_cd);
> >  }
> >
> >+#ifdef CONFIG_TWL4030_CORE
> >+static int omap_hsmmc_init_twl6030(struct omap_hsmmc_host *host)
> >+{
> >+	struct omap_mmc_platform_data *pdata = host->pdata;
> >+	struct omap_mmc_slot_data *slot =&pdata->slots[0];
> >+	int irq;
> >+
> >+	if (gpio_is_valid(host->gpio_cd) || host->id)
> 
> I have a series, which I am asking Chris to pull, which completely
> gets rid of all host->id based hard-codings' in the driver.
> Isn't there a better way to do this than rely on the device instance?

Yes I was thinking about that too. I guess we need to pass some
flag in pdata for twl6030 card detect. I was thinking about using
the gpiochip_cd, but twl6030 is not gpio based card detect, so
a separate flag is better.

BTW, with -rc5, looks like re-inserting omap_hsmmc on omap4 fails
to detect any cards, and then fails to unload. This works on omap3
just fine. Any ideas why that would be?

Regards,

Tony


From jkrzyszt at tis.icnet.pl  Fri Mar  2 12:20:38 2012
From: jkrzyszt at tis.icnet.pl (Janusz Krzysztofik)
Date: Fri, 02 Mar 2012 18:20:38 +0100
Subject: [GIT PULL 3/5] First set of omap1 related changes
In-Reply-To: <20120301233101.GC18901@atomide.com>
References: <0Mfo5g-1RocQt3wlY-00NttP@mx.kundenserver.de>
 <3378572.m1z82NvySs@acer> <20120301233101.GC18901@atomide.com>
Message-ID: <35028515.2H84FQMe6Y@acer>

On Thu, 1 Mar 2012 15:31:01 Tony Lindgren wrote:
> 
> I've pushed ams-delta branch that's based on -rc5 merged
> with what Arnd pulled yesterday as -rc1 has i2c-omap.c
> a compile bug for omap1. I've applied these two patches
> there as the second one depends on what got pulled:
> 
> ARM: OMAP1: ams-delta: clean up init data section assignments
> ARM: OMAP1: ams-delta: fix incorrect section tags

Thanks!

> Looks like your patch "ARM: OMAP1: ams-delta: set up regulator
> over modem reset GPIO pin" causes the following error with
> CONFIG_DEBUG_SECTION_MISMATCH=y:
> 
> arch/arm/mach-omap1/board-ams-delta.c:273:36: error:
> modem_nreset_config causes a section type conflict
> 
> So care to update and repost that (and possibly the following
> two patches) with your missing fixes?

OK, I will, in a couple of days.

Thanks,
Janusz


From tony at atomide.com  Fri Mar  2 12:30:18 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 09:30:18 -0800
Subject: [PATCH 0/4] Start getting rid of pdata callbacks with
 gpio_find_by_chip_name()
In-Reply-To: <4F508DAE.9000005@ti.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <4F508DAE.9000005@ti.com>
Message-ID: <20120302173017.GK18901@atomide.com>

* Rajendra Nayak <rnayak at ti.com> [120302 00:35]:
> Hi Tony,
> 
> On Friday 02 March 2012 12:25 AM, Tony Lindgren wrote:
> >Hi all,
> >
> >This series adds gpio_find_by_name() that allows finding
> >GPIOs on specific gpio_chips. As the GPIO numbers can be
> >dynamic, it's hard to find the GPIO numbers from drivers
> >using them directly.
> >
> >So far we've dealt with this using platform specific callbacks,
> >but that is messy. This series removes the needs for these
> >callbacks for omap hsmmc driver. Further callbacks can be
> >removed people are OK with adding gpio_find_by_name().
> >
> >This series is based on the omap fixes-non-critical that's
> >needed for the arch/arm/mach-omap2 parts of this series.
> 
> I tested these on my beagle/panda/omap4sdp and they seem to
> work fine, also fixing the broken panda card detect (due to
> missing card_detect_irq in the board file). There are still
> issues however when I build twl4030-gpio as a module, which I
> already commented on, and the fact that the init sequence now
> works by luck :)

Hmm it should not be luck based, loading omap_hsmmc module
should fail with a sensible error if the configured card detect
or write protect is not available.

I guess this is with twl6030 non-gpio based card detect?

If so, I'll add something to pass the twl6030 card detect from
pdata so we can fail with a sensible error in that case too.

Also, sounds like twl as module and mmc built in case won't
work without deferred probe. But at least there is a sensible
error for that. And maybe we can prevent that in Kconfig.

> The other issue also is that the multiple insmod/rmmod test
> suggested by Russell still fails, since the second time around
> the gpio_requests in the board callback fail because they are
> not freed when you do a module unload/unbind.
> That would need this patch from me to add the .teardown
> hooks
> http://marc.info/?l=linux-omap&m=133007767831297&w=2

Yes let's add the teardown patch as a fix for now, but let's
plan on getting rid of the twl_setup callback function
completely.

With these patches LCD and WLAN too can request the twl gpios
directly from the driver based on gpio_chip + gpio offset.

Regards,

Tony


From tony at atomide.com  Fri Mar  2 12:38:12 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 09:38:12 -0800
Subject: Randconfig module build error with OMAP4_ERRATA_I688
In-Reply-To: <CAMQu2gy9XksJ+8Q_Ygwtx7n2tVfd2KCu0o54SisuV8_QUX_rUQ@mail.gmail.com>
References: <20120229173719.GN18901@atomide.com>
 <CAMQu2gxg_57AVW+MT_Sgi+gr2OUge-YPdSUxoG+z-zQth=4-UA@mail.gmail.com>
 <20120301162556.GY18901@atomide.com>
 <CAMQu2gy9XksJ+8Q_Ygwtx7n2tVfd2KCu0o54SisuV8_QUX_rUQ@mail.gmail.com>
Message-ID: <20120302173811.GL18901@atomide.com>

* Shilimkar, Santosh <santosh.shilimkar at ti.com> [120302 03:15]:
> On Thu, Mar 1, 2012 at 9:55 PM, Tony Lindgren <tony at atomide.com> wrote:
> > * Shilimkar, Santosh <santosh.shilimkar at ti.com> [120301 00:38]:
> >> On Wed, Feb 29, 2012 at 11:07 PM, Tony Lindgren <tony at atomide.com> wrote:
> >> > Hi Santosh,
> >> >
> >> > Looks like OMAP4_ERRATA_I688 still has one more issue:
> >> > Modules won't build at least with the attached randconfig
> >> > generated file.
> >> >
> >> > Can you please take a look at how to deal with it?
> >> >
> >> > Maybe omap_bus_sync should be an inline function with some
> >> > wrapper for the sleep44xx.S to call?
> >> >
> >> > I already posted a fix for the GPMC related error with the
> >> > same .config file.
> >> >
> >> This one builds for me against 'Linux 3.3-rc5,
> >> Ofocurse I got below error with the attached .config which
> >> I bypassed to see the Errata build failure.
> >>
> >> arch/arm/mach-omap2/built-in.o: In function `n8x0_mmc_callback':
> >> linux-2.6/arch/arm/mach-omap2/board-n8x0.c:374: undefined reference to
> >> `omap_mmc_notify_cover_event'
> >> make: *** [.tmp_vmlinux1] Error 1
> >
> > Yes a fix for that has been queued already.
> >
> >> I build this with below toolchain...
> >> $arm-none-linux-gnueabi-gcc --version
> >> arm-none-linux-gnueabi-gcc (Sourcery G++ Lite 2011.03-41) 4.5.2
> >> Copyright (C) 2010 Free Software Foundation, Inc.
> >>
> >> Am I missing anything ?
> >
> > I think you're missing your commit 2ec1fc4e169acc0b8d6733ff028fd52e766773d9
> > (ARM: OMAP4: Move the barrier memboclk_steal() as part of reserve callback)
> > thats' queued up in fixes, and CONFIG_OMAP4_ERRATA_I688=y.
> >
> > Then with -rc5 + 2ec1fc4e when you build modules you'll get this:
> >
> > ERROR: "omap_bus_sync" [drivers/watchdog/sp805_wdt.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/watchdog/dw_wdt.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/virtio/virtio_ring.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/video/sm501fb.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/usb/mon/usbmon.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/usb/host/sl811-hcd.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/usb/host/ohci-hcd.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/usb/host/isp1760.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/usb/host/isp1362-hcd.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/usb/host/isp116x-hcd.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/usb/core/usbcore.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/tty/serial/altera_uart.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/tty/serial/altera_jtaguart.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/tty/serial/8250/8250_dw.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/ssb/ssb.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/rtc/rtc-cmos.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/rtc/rtc-bq4802.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/mtd/nand/tmio_nand.ko] undefined!
> > ERROR: "omap_bus_sync" [drivers/mtd/nand/omap2.ko] undefined!
> >
> Sricharan has posted a fix for it. [1]
> The sleep code stuff is just dummy function for the cases when the errata
> is not defined. When Errata is defined the generic barriers too get impacted
> and hence the function needs to be exported.

OK thanks,

Tony

 
> [1] http://www.spinics.net/lists/arm-kernel/msg162608.html


From jonathan.austin at arm.com  Fri Mar  2 12:37:34 2012
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Fri,  2 Mar 2012 17:37:34 +0000
Subject: [PATCH 1/2] ARM: ThumbEE: Disable userspace TEEHBR access for
 !CONFIG_ARM_THUMBEE
Message-ID: <1330709855-4793-1-git-send-email-jonathan.austin@arm.com>

Currently when ThumbEE is not enabled (!CONFIG_ARM_THUMBEE) the ThumbEE
register states are not saved/restored at context switch. The default state
of the ThumbEE Ctrl register (TEECR) allows userspace accesses to the
ThumbEE Base Handler register (TEEHBR). This can cause unexpected behaviour
when people use ThumbEE on !CONFIG_ARM_THUMBEE kernels, as well as allowing
covert communication - eg between userspace tasks running inside chroot
jails.

This patch sets up TEECR in order to prevent user-space access to TEEHBR
when !CONFIG_ARM_THUMBEE. In this case, tasks are sent SIGILL if they try to
access TEEHBR.

Reviewed-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
---
 arch/arm/mm/proc-v7.S |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 0404ccb..9a05e7f 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -257,6 +257,18 @@ __v7_setup:
 	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
 	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
 #endif
+#ifndef CONFIG_ARM_THUMBEE
+	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
+	and	r0, r0, #(0xf << 12)		@ ThumbEE enabled field
+	teq	r0, #(1 << 12)			@ check if ThumbEE is present
+	bne	1f
+	mov	r5, #0
+	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0
+	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR
+	orr	r0, r0, #1			@ set the 1st bit in order to
+	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access
+1:
+#endif
 	adr	r5, v7_crval
 	ldmia	r5, {r5, r6}
 #ifdef CONFIG_CPU_ENDIAN_BE8
-- 
1.7.1




From jonathan.austin at arm.com  Fri Mar  2 12:37:35 2012
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Fri,  2 Mar 2012 17:37:35 +0000
Subject: [PATCH 2/2] ARM: ThumbEE: Use cpuid macros to read ID_PFR0 for ThumbEE
In-Reply-To: <1330709855-4793-1-git-send-email-jonathan.austin@arm.com>
References: <1330709855-4793-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1330709855-4793-2-git-send-email-jonathan.austin@arm.com>

The ThumbEE probe code uses inline assembly to read ID_PFR0 in order to
detect whether ThumbEE is implemented by the processor.

This patch replaces the inline asm with the read_cpuid_ext macro.

Reviewed-by: Will Deacon <will.deacon at arm.com>
Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
---
 arch/arm/kernel/thumbee.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c
index 9cb7aac..3471f63 100644
--- a/arch/arm/kernel/thumbee.c
+++ b/arch/arm/kernel/thumbee.c
@@ -20,6 +20,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
+#include <asm/cputype.h>
 #include <asm/thread_notify.h>
 
 /*
@@ -66,8 +67,7 @@ static int __init thumbee_init(void)
 	if (cpu_arch < CPU_ARCH_ARMv7)
 		return 0;
 
-	/* processor feature register 0 */
-	asm("mrc	p15, 0, %0, c0, c1, 0\n" : "=r" (pfr0));
+	pfr0 = read_cpuid_ext(CPUID_EXT_PFR0);
 	if ((pfr0 & 0x0000f000) != 0x00001000)
 		return 0;
 
-- 
1.7.1




From swarren at nvidia.com  Fri Mar  2 12:41:04 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Fri, 2 Mar 2012 09:41:04 -0800
Subject: [PATCH] pinctrl: resurrect verbose pinmux-pins
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE861978@HQMAIL01.nvidia.com>
References: <1330705873-10798-1-git-send-email-linus.walleij@stericsson.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861978@HQMAIL01.nvidia.com>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861991@HQMAIL01.nvidia.com>

Stephen Warren wrote at Friday, March 02, 2012 10:22 AM:
> Linus Walleij wrote at riday, March 02, 2012 9:31 AM:
> > From: Linus Walleij <linus.walleij at linaro.org>
> >
> > This reintroduces the verbosity in the pinmux-pins file, now this
> > file will list all pins, their names, owning device (and if it's
> > a hog) and also in applicable cases the function and group making
> > use of that pin right now.
> >
> > Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> 
> It'd be nice if we could defer this fix until after all the API rework,
> because it'll cause all kinds of conflicts otherwise.

Oh, I see this patch is in your for-next branch already before I had a chance
to comment on it. I guess I'll have write a patch to convert the removed struct
type to char*s and rebase on top of it:-(

--
nvpublic



From arnd.bergmann at linaro.org  Fri Mar  2 12:44:11 2012
From: arnd.bergmann at linaro.org (Arnd Bergmann)
Date: Fri, 2 Mar 2012 17:44:11 +0000
Subject: [PATCH] Initial Device Tree system for Snowball
In-Reply-To: <1330703567-17925-1-git-send-email-niklas.hernaeus@stericsson.com>
References: <1330703567-17925-1-git-send-email-niklas.hernaeus@stericsson.com>
Message-ID: <201203021744.12088.arnd.bergmann@linaro.org>

On Friday 02 March 2012, Niklas Hernaeus wrote:
> From: Niklas Hernaeus <niklas.hernaeus at linaro.org>
> 
> This is the base system for using Device Tree for Snowball.
> The new boardfile is a slightly modified copy of the original board file,
> so new Device Tree stuff can simply be added and code removed, while
> functionality stays the same.
> 
> Signed-off-by: Niklas Hernaeus <niklas.hernaeus at linaro.org>

Hi Niklas,

Great to see this has finally worked.

As Jean-Christophe already commented, we should drastically limit
the amount of code duplication between this platform and the one
that is already there. I can see two ways out of here:

a) Make sure that all hardware that was working with the
existing code still works with this one, and just replace it
(or patch it to look like what you have), mandating the use
of device tree blobs on u8500 right away. We should get there
anyway over time, so we could just as well do it now.

b) keep using your patch as a work-in-progress copy of the
existing code, but when we get to merge it into upstream make sure
that any part of it that is just duplicated either gets replaced
with a device node and associated properties, or calls the respective
function from a common location.

In any case, I would suggest you remove the platform_device definitions
for all devices and just leave the platform_data that you can pass
using the auxdata mechanism.

> diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
> index 52af004..be7e4fe 100644
> --- a/arch/arm/mach-ux500/Kconfig
> +++ b/arch/arm/mach-ux500/Kconfig
> @@ -27,19 +27,22 @@ menu "Ux500 target platform (boards)"
>  config MACH_U8500
>  	bool "U8500 Development platform"
>  	depends on UX500_SOC_DB8500
> +	depends on !USE_OF
>  	select TPS6105X
>  	help
>  	  Include support for the mop500 development platform.
>  
>  config MACH_HREFV60
> -       bool "U85000 Development platform, HREFv60 version"
> -       depends on UX500_SOC_DB8500
> -       help
> -         Include support for the HREFv60 new development platform.
> +	bool "U85000 Development platform, HREFv60 version"
> +	depends on UX500_SOC_DB8500
> +	depends on !USE_OF
> +	help
> +	  Include support for the HREFv60 new development platform.
>  
>  config MACH_SNOWBALL
>  	bool "U8500 Snowball platform"
>  	depends on UX500_SOC_DB8500
> +	depends on !USE_OF
>  	select MACH_U8500
>  	help
>  	  Include support for the snowball development platform.
> @@ -49,6 +52,12 @@ config MACH_U5500
>  	depends on UX500_SOC_DB5500
>  	help
>  	  Include support for the U5500 development platform.
> +config MACH_UX500_DT
> +	def_bool y if USE_OF
> +	depends on UX500_SOC_DB8500 || UX500_SOC_DB5500
> +
> +config MACH_MOP500
> +	def_bool y if MACH_U8500 || MACH_UX500_DT
>  endmenu
>  

This change conflicts with some other patches that we have been discussing
recently. I'd suggest rebasing your change on top of the others as soon
as they are merged into arm-soc/next/fixes-non-critical.

> +
> +static struct gpio_led snowball_led_array[] = {
> +	{
> +		.name = "user_led",
> +		.default_trigger = "none",
> +		.gpio = 142,
> +	},
> +};
> +
> +static struct gpio_led_platform_data snowball_led_data = {
> +	.leds = snowball_led_array,
> +	.num_leds = ARRAY_SIZE(snowball_led_array),
> +};
> +
> +static struct platform_device snowball_led_dev = {
> +	.name = "leds-gpio",
> +	.dev = {
> +		.platform_data = &snowball_led_data,
> +	},
> +};

I would prefer if we could move those devices that have binding already
into the device tree right away and leave only the ones that are missing
in the initial merge of this.

gpio-leds has bindings according to
Documentation/devicetree/bindings/gpio/led.txt

Converting those should be straightforward as soon as the gpio node
is converted. The same is true for gpio-keys.

> +static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
> +	.gpio_base		= MOP500_AB8500_GPIO(0),
> +	.irq_base		= MOP500_AB8500_VIR_GPIO_IRQ_BASE,
> +	/* config_reg is the initial configuration of ab8500 pins.
> +	 * The pins can be configured as GPIO or alt functions based
> +	 * on value present in GpioSel1 to GpioSel6 and AlternatFunction
> +	 * register. This is the array of 7 configuration settings.
> +	 * One has to compile time decide these settings. Below is the
> +	 * explanation of these setting
> +	 * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
> +	 * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
> +	 * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
> +	 * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO
> +	 * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO
> +	 * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO
> +	 * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured
> +	 * as GPIO then this register selectes the alternate fucntions
> +	 */
> +	.config_reg		= {0x00, 0x1E, 0x80, 0x01,
> +					0x7A, 0x00, 0x00},
> +};
> +
> +static struct smsc911x_platform_config snowball_sbnet_cfg = {
> +	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
> +	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
> +	.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
> +	.shift = 1,
> +};
> +
> +static struct resource sbnet_res[] = {
> +	{
> +		.name = "smsc911x-memory",
> +		.start = (0x5000 << 16),
> +		.end  =  (0x5000 << 16) + 0xffff,
> +		.flags = IORESOURCE_MEM,
> +	},
> +	{
> +		.start = NOMADIK_GPIO_TO_IRQ(140),
> +		.end = NOMADIK_GPIO_TO_IRQ(140),
> +		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
> +	},
> +};
> +
> +static struct platform_device snowball_sbnet_dev = {
> +	.name           = "smsc911x",
> +	.num_resources  = ARRAY_SIZE(sbnet_res),
> +	.resource       = sbnet_res,
> +	.dev            = {
> +		.platform_data = &snowball_sbnet_cfg,
> +	},
> +};

This one does not have bindings yet, so let's leave it for now.

> +static struct ab8500_platform_data ab8500_platdata = {
> +	.irq_base	= MOP500_AB8500_IRQ_BASE,
> +	.regulator_reg_init = ab8500_regulator_reg_init,
> +	.num_regulator_reg_init	= ARRAY_SIZE(ab8500_regulator_reg_init),
> +	.regulator	= ab8500_regulators,
> +	.num_regulator	= ARRAY_SIZE(ab8500_regulators),
> +	.gpio		= &ab8500_gpio_pdata,
> +};
> +
> +static struct resource ab8500_resources[] = {
> +	[0] = {
> +		.start	= IRQ_DB8500_AB8500,
> +		.end	= IRQ_DB8500_AB8500,
> +		.flags	= IORESOURCE_IRQ
> +	}
> +};
> +
> +struct platform_device ab8500_device = {
> +	.name = "ab8500-i2c",
> +	.id = 0,
> +	.dev = {
> +		.platform_data = &ab8500_platdata,
> +	},
> +	.num_resources = 1,
> +	.resource = ab8500_resources,
> +};

Converting ab8500 to device tree is key here, because almost everything
else is located below it. I'd suggest you use auxdata to replace the
get the platform_data in unmodified as a start and then change the
ab8500 mfd driver to scan its child buses.


> +#ifdef CONFIG_STE_DMA40
> +static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
> +	.mode = STEDMA40_MODE_LOGICAL,
> +	.dir = STEDMA40_PERIPH_TO_MEM,
> +	.src_dev_type =  DB8500_DMA_DEV13_UART0_RX,
> +	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
> +	.src_info.data_width = STEDMA40_BYTE_WIDTH,
> +	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
> +};

It looks like the uart device could just as well work without DMA support,
right? How about leaving the dma out for now, until we have bindings for
it? That will also remove the need for platform_data in most of the uart
devices.

> +static const char * snowball_dt_board_compat[] = {
> +	"calaosystems,snowball-a9500",
> +	NULL
> +};
>
> +MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
> +	/* Maintainer: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com> */
> +	.atag_offset	= 0x100,
> +	.map_io		= u8500_map_io,
> +	.init_irq	= ux500_init_irq,
> +	/* we re-use nomadik timer here */
> +	.timer		= &ux500_timer,
> +	.handle_irq	= gic_handle_irq,
> +	.init_machine	= mop500_init_machine,
> +MACHINE_END
> +
> +MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
> +	.atag_offset	= 0x100,
> +	.map_io		= u8500_map_io,
> +	.init_irq	= ux500_init_irq,
> +	.timer		= &ux500_timer,
> +	.handle_irq	= gic_handle_irq,
> +	.init_machine	= hrefv60_init_machine,
> +MACHINE_END
> +
> +DT_MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
> +	.atag_offset	= 0x100,
> +	.map_io		= u8500_map_io,
> +	.init_irq	= ux500_init_irq,
> +	/* we re-use nomadik timer here */
> +	.timer		= &ux500_timer,
> +	.handle_irq	= gic_handle_irq,
> +	.init_machine	= snowball_init_machine,
> +	.dt_compat      = snowball_dt_board_compat,
> +MACHINE_END

Here, you should really have only one DT_MACHINE_START for all three, and
use a common init_machine function but a dt_compat list for all three.

Inside of the init_machine function, you can use of_machine_is_compatible()
to find out which one you are on, and call the machine specific functions.

	Arnd


From jason at lakedaemon.net  Fri Mar  2 12:50:19 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri,  2 Mar 2012 17:50:19 +0000
Subject: [PATCH 2/5] ARM: kirkwood: move var setting to correct location.
In-Reply-To: <cover.1330709314.git.jason@lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
Message-ID: <f32cdce5ddde93ed6705b505262494efe92db4c7.1330709314.git.jason@lakedaemon.net>

This variable should be set within the driver init function that uses
it's struct, not in the generic init function.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/mach-kirkwood/common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 357fcde..d9e4d99 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -382,6 +382,7 @@ static struct platform_device kirkwood_pcm_device = {
 void __init kirkwood_audio_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_AUDIO;
+	kirkwood_i2s_data.tclk = kirkwood_tclk;
 	platform_device_register(&kirkwood_i2s_device);
 	platform_device_register(&kirkwood_pcm_device);
 }
@@ -450,7 +451,6 @@ void __init kirkwood_init(void)
 {
 	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
 		kirkwood_id(), kirkwood_tclk);
-	kirkwood_i2s_data.tclk = kirkwood_tclk;
 
 	/*
 	 * Disable propagation of mbus errors to the CPU local bus,
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar  2 12:50:17 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri,  2 Mar 2012 17:50:17 +0000
Subject: [PATCH 0/5 v2] ARM: kirkwood: fdt: convert kirkwood init funcs to fdt
In-Reply-To: <cover.1330625877.git.jason@lakedaemon.net>
Message-ID: <cover.1330709314.git.jason@lakedaemon.net>

This series begins the process of converting all of the drivers initialized
from kirkwood_init() to devicetree.

The first patch converts an off-SoC driver (spi) to device tree and moves flash
partition definitions to the device tree.  This was previously it's own
submission, but I've included it here since I want this series to match the
subsequent pull request against arm-soc/kirkwood/board.

The second patch cleans up kirkwood_init() by moving a flag setting to it's
appropriate location.  This will help later when converting the audio driver.

Next, I pull the functionality of kirkwood_init() into kirkwood_dt_init() in
board-dt.c  This way, as drivers are converted, their init calls can be removed
from kirkwood_dt_init() and non-fdt users won't be affected (they call
kirkwood_init()).

Last, I converted the two easiest drivers, rtc and wdt.  The xor and crypto
drivers remain for a later patch series.

Jason Cooper (5):
  ARM: kirkwood: covert orion-spi to fdt.
  ARM: kirkwood: move var setting to correct location.
  ARM: kirkwood: fdt: absorb kirkwood_init()
  ARM: kirkwood: convert rtc-mv to fdt.
  ARM: kirkwood: convert orion-wdt to fdt.

 arch/arm/boot/dts/kirkwood-dreamplug.dts |   34 +++++++++++++++
 arch/arm/boot/dts/kirkwood.dtsi          |   12 +++++
 arch/arm/mach-kirkwood/board-dt.c        |   67 +++++++++++------------------
 arch/arm/mach-kirkwood/common.c          |   21 +++++++--
 arch/arm/mach-kirkwood/common.h          |    6 +++
 drivers/rtc/rtc-mv.c                     |    7 +++
 drivers/spi/spi-orion.c                  |   37 +++++++++++++++--
 drivers/watchdog/orion_wdt.c             |   48 ++++++++++++++++-----
 8 files changed, 170 insertions(+), 62 deletions(-)

-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar  2 12:50:21 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri,  2 Mar 2012 17:50:21 +0000
Subject: [PATCH 4/5 v2] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <cover.1330709314.git.jason@lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
Message-ID: <4de611961e8210a0a2c3b56fe72b40dba638752a.1330709314.git.jason@lakedaemon.net>

The comment at mach-kirkwood/common.c:469, says this device is in every
kirkwood board.  So, it is placed in kirkwood.dtsi.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes since v1:

    - removed unnecessary of_*() code from _probe()
    - use of_match_ptr()

 arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
 arch/arm/mach-kirkwood/board-dt.c |    1 -
 arch/arm/mach-kirkwood/common.c   |    2 +-
 arch/arm/mach-kirkwood/common.h   |    1 -
 drivers/rtc/rtc-mv.c              |    7 +++++++
 5 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 771c6bb..5fb185c 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -2,5 +2,11 @@
 
 / {
 	compatible = "marvell,kirkwood";
+
+	rtc at f1010300 {
+		compatible = "marvell,rtc";
+		reg = <0xf1010300 0x1f>;
+		interrupts = <53>;
+	};
 };
 
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 2a45656..6e18338 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -134,7 +134,6 @@ static void __init kirkwood_dt_init(void)
 #endif
 
 	/* internal devices that every board has */
-	kirkwood_rtc_init();
 	kirkwood_wdt_init();
 	kirkwood_xor0_init();
 	kirkwood_xor1_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 167b6c8..0c0375f 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -163,7 +163,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-void __init kirkwood_rtc_init(void)
+static void __init kirkwood_rtc_init(void)
 {
 	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index c382447..ca08826 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -53,7 +53,6 @@ void kirkwood_restart(char, const char *);
 
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-void kirkwood_rtc_init(void);
 void kirkwood_wdt_init(void);
 void kirkwood_xor0_init(void);
 void kirkwood_xor1_init(void);
diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c
index 768e2ed..3108b18 100644
--- a/drivers/rtc/rtc-mv.c
+++ b/drivers/rtc/rtc-mv.c
@@ -12,6 +12,7 @@
 #include <linux/bcd.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/delay.h>
 #include <linux/gfp.h>
 #include <linux/module.h>
@@ -294,11 +295,17 @@ static int __exit mv_rtc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static struct of_device_id rtc_mv_of_match_table[] = {
+	{ .compatible = "marvell,rtc", },
+	{}
+};
+
 static struct platform_driver mv_rtc_driver = {
 	.remove		= __exit_p(mv_rtc_remove),
 	.driver		= {
 		.name	= "rtc-mv",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(rtc_mv_of_match_table),
 	},
 };
 
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar  2 12:50:22 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri,  2 Mar 2012 17:50:22 +0000
Subject: [PATCH 5/5 v2] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <cover.1330709314.git.jason@lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
Message-ID: <e2fe5e97a83fc753559bbb18d5d111ed01b89034.1330709314.git.jason@lakedaemon.net>

Converted register address to a variable so that it could be set from
fdt.  Also, pull clock frequency from fdt and clean up failure logic a
bit.

Same as rtc-mv, this device is used in all kirkwood boards.  So, it is
placed in kirkwood.dtsi.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes since v1:

    - use of_match_ptr()

 arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++
 arch/arm/mach-kirkwood/board-dt.c |    1 -
 arch/arm/mach-kirkwood/common.c   |    2 +-
 arch/arm/mach-kirkwood/common.h   |    1 -
 drivers/watchdog/orion_wdt.c      |   48 +++++++++++++++++++++++++++---------
 5 files changed, 43 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 5fb185c..bf28424 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -8,5 +8,11 @@
 		reg = <0xf1010300 0x1f>;
 		interrupts = <53>;
 	};
+
+	wdt at fed20300 {
+		compatible = "marvell,orion-wdt";
+		reg = <0xfed20300 0x28>;
+		clock-frequency = <200000000>;
+	};
 };
 
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 6e18338..fb03318 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -134,7 +134,6 @@ static void __init kirkwood_dt_init(void)
 #endif
 
 	/* internal devices that every board has */
-	kirkwood_wdt_init();
 	kirkwood_xor0_init();
 	kirkwood_xor1_init();
 	kirkwood_crypto_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 0c0375f..35dc40b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -303,7 +303,7 @@ void __init kirkwood_xor1_init(void)
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-void __init kirkwood_wdt_init(void)
+static void __init kirkwood_wdt_init(void)
 {
 	orion_wdt_init(kirkwood_tclk);
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index ca08826..ac4b2fb 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -53,7 +53,6 @@ void kirkwood_restart(char, const char *);
 
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-void kirkwood_wdt_init(void);
 void kirkwood_xor0_init(void);
 void kirkwood_xor1_init(void);
 void kirkwood_crypto_init(void);
diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
index 4ad78f8..8704b98 100644
--- a/drivers/watchdog/orion_wdt.c
+++ b/drivers/watchdog/orion_wdt.c
@@ -17,6 +17,8 @@
 #include <linux/fs.h>
 #include <linux/miscdevice.h>
 #include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
 #include <linux/watchdog.h>
 #include <linux/init.h>
 #include <linux/uaccess.h>
@@ -28,9 +30,9 @@
 /*
  * Watchdog timer block registers.
  */
-#define TIMER_CTRL		(TIMER_VIRT_BASE + 0x0000)
+#define TIMER_CTRL		0x0000
 #define  WDT_EN			0x0010
-#define WDT_VAL			(TIMER_VIRT_BASE + 0x0024)
+#define WDT_VAL			0x0024
 
 #define WDT_MAX_CYCLE_COUNT	0xffffffff
 #define WDT_IN_USE		0
@@ -40,6 +42,7 @@ static int nowayout = WATCHDOG_NOWAYOUT;
 static int heartbeat = -1;		/* module parameter (seconds) */
 static unsigned int wdt_max_duration;	/* (seconds) */
 static unsigned int wdt_tclk;
+static void __iomem *wdt_reg;
 static unsigned long wdt_status;
 static DEFINE_SPINLOCK(wdt_lock);
 
@@ -48,7 +51,7 @@ static void orion_wdt_ping(void)
 	spin_lock(&wdt_lock);
 
 	/* Reload watchdog duration */
-	writel(wdt_tclk * heartbeat, WDT_VAL);
+	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
 
 	spin_unlock(&wdt_lock);
 }
@@ -60,7 +63,7 @@ static void orion_wdt_enable(void)
 	spin_lock(&wdt_lock);
 
 	/* Set watchdog duration */
-	writel(wdt_tclk * heartbeat, WDT_VAL);
+	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
 
 	/* Clear watchdog timer interrupt */
 	reg = readl(BRIDGE_CAUSE);
@@ -68,9 +71,9 @@ static void orion_wdt_enable(void)
 	writel(reg, BRIDGE_CAUSE);
 
 	/* Enable watchdog timer */
-	reg = readl(TIMER_CTRL);
+	reg = readl(wdt_reg + TIMER_CTRL);
 	reg |= WDT_EN;
-	writel(reg, TIMER_CTRL);
+	writel(reg, wdt_reg + TIMER_CTRL);
 
 	/* Enable reset on watchdog */
 	reg = readl(RSTOUTn_MASK);
@@ -92,9 +95,9 @@ static void orion_wdt_disable(void)
 	writel(reg, RSTOUTn_MASK);
 
 	/* Disable watchdog timer */
-	reg = readl(TIMER_CTRL);
+	reg = readl(wdt_reg + TIMER_CTRL);
 	reg &= ~WDT_EN;
-	writel(reg, TIMER_CTRL);
+	writel(reg, wdt_reg + TIMER_CTRL);
 
 	spin_unlock(&wdt_lock);
 }
@@ -102,7 +105,7 @@ static void orion_wdt_disable(void)
 static int orion_wdt_get_timeleft(int *time_left)
 {
 	spin_lock(&wdt_lock);
-	*time_left = readl(WDT_VAL) / wdt_tclk;
+	*time_left = readl(wdt_reg + WDT_VAL) / wdt_tclk;
 	spin_unlock(&wdt_lock);
 	return 0;
 }
@@ -236,15 +239,30 @@ static struct miscdevice orion_wdt_miscdev = {
 static int __devinit orion_wdt_probe(struct platform_device *pdev)
 {
 	struct orion_wdt_platform_data *pdata = pdev->dev.platform_data;
+	struct device_node *np = pdev->dev.of_node;
+	struct resource res;
 	int ret;
 
-	if (pdata) {
+	if (pdata)
 		wdt_tclk = pdata->tclk;
-	} else {
-		printk(KERN_ERR "Orion Watchdog misses platform data\n");
+
+	of_property_read_u32(np, "clock-frequency", &wdt_tclk);
+
+	if (!wdt_tclk) {
+		printk(KERN_ERR "Orion Watchdog can't get clock freq\n");
 		return -ENODEV;
 	}
 
+	wdt_reg = (void __iomem *)TIMER_VIRT_BASE;
+
+	ret = of_address_to_resource(np, 0, &res);
+	if (ret) {
+		printk(KERN_ERR "invalid address\n");
+		return ret;
+	}
+
+	wdt_reg = ioremap(res.start, res.end - res.start);
+
 	if (orion_wdt_miscdev.parent)
 		return -EBUSY;
 	orion_wdt_miscdev.parent = &pdev->dev;
@@ -284,6 +302,11 @@ static void orion_wdt_shutdown(struct platform_device *pdev)
 		orion_wdt_disable();
 }
 
+static struct of_device_id orion_wdt_of_match_table[] = {
+	{ .compatible = "marvell,orion-wdt", },
+	{},
+};
+
 static struct platform_driver orion_wdt_driver = {
 	.probe		= orion_wdt_probe,
 	.remove		= __devexit_p(orion_wdt_remove),
@@ -291,6 +314,7 @@ static struct platform_driver orion_wdt_driver = {
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "orion_wdt",
+		.of_match_table = of_match_ptr(orion_wdt_of_match_table),
 	},
 };
 
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar  2 12:50:20 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri,  2 Mar 2012 17:50:20 +0000
Subject: [PATCH 3/5 v2] ARM: kirkwood: fdt: absorb kirkwood_init()
In-Reply-To: <cover.1330709314.git.jason@lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
Message-ID: <ebd67d97d13fed0608bcf482e739479693c465b5.1330709314.git.jason@lakedaemon.net>

We need to absorb kirkwood_init() into kirkwood_dt_init() so that as we
convert drivers, we can remove the platform call, eg
kirkwood_rtc_init().  This maintains compatibility with non-fdt
configurations because they still call kirkwood_init() in common.c.

As drivers are converted, we will reinstate the 'static' qualifier in
common.c.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes since v1:

    - changed printk() to pr_info() as suggested by Grant Likely.

 arch/arm/mach-kirkwood/board-dt.c |   29 ++++++++++++++++++++++++++++-
 arch/arm/mach-kirkwood/common.c   |   12 ++++++------
 arch/arm/mach-kirkwood/common.h   |    8 ++++++++
 3 files changed, 42 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 4960e63..2a45656 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -29,7 +29,9 @@
 #include <linux/spi/orion_spi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 #include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
 #include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
@@ -115,7 +117,32 @@ static void __init dreamplug_init(void)
 
 static void __init kirkwood_dt_init(void)
 {
-	kirkwood_init();
+	pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
+
+	/*
+	 * Disable propagation of mbus errors to the CPU local bus,
+	 * as this causes mbus errors (which can occur for example
+	 * for PCI aborts) to throw CPU aborts, which we're not set
+	 * up to deal with.
+	 */
+	writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
+
+	kirkwood_setup_cpu_mbus();
+
+#ifdef CONFIG_CACHE_FEROCEON_L2
+	kirkwood_l2_init();
+#endif
+
+	/* internal devices that every board has */
+	kirkwood_rtc_init();
+	kirkwood_wdt_init();
+	kirkwood_xor0_init();
+	kirkwood_xor1_init();
+	kirkwood_crypto_init();
+
+#ifdef CONFIG_KEXEC
+	kexec_reinit = kirkwood_enable_pcie;
+#endif
 
 	if (of_machine_is_compatible("globalscale,dreamplug"))
 		dreamplug_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index d9e4d99..167b6c8 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -163,7 +163,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-static void __init kirkwood_rtc_init(void)
+void __init kirkwood_rtc_init(void)
 {
 	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
@@ -279,7 +279,7 @@ void __init kirkwood_crypto_init(void)
 /*****************************************************************************
  * XOR0
  ****************************************************************************/
-static void __init kirkwood_xor0_init(void)
+void __init kirkwood_xor0_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_XOR0;
 
@@ -291,7 +291,7 @@ static void __init kirkwood_xor0_init(void)
 /*****************************************************************************
  * XOR1
  ****************************************************************************/
-static void __init kirkwood_xor1_init(void)
+void __init kirkwood_xor1_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_XOR1;
 
@@ -303,7 +303,7 @@ static void __init kirkwood_xor1_init(void)
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-static void __init kirkwood_wdt_init(void)
+void __init kirkwood_wdt_init(void)
 {
 	orion_wdt_init(kirkwood_tclk);
 }
@@ -393,7 +393,7 @@ void __init kirkwood_audio_init(void)
 /*
  * Identify device ID and revision.
  */
-static char * __init kirkwood_id(void)
+char * __init kirkwood_id(void)
 {
 	u32 dev, rev;
 
@@ -436,7 +436,7 @@ static char * __init kirkwood_id(void)
 	}
 }
 
-static void __init kirkwood_l2_init(void)
+void __init kirkwood_l2_init(void)
 {
 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
 	writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 9071a39..c382447 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -51,6 +51,14 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev
 void kirkwood_audio_init(void);
 void kirkwood_restart(char, const char *);
 
+char *kirkwood_id(void);
+void kirkwood_l2_init(void);
+void kirkwood_rtc_init(void);
+void kirkwood_wdt_init(void);
+void kirkwood_xor0_init(void);
+void kirkwood_xor1_init(void);
+void kirkwood_crypto_init(void);
+
 extern int kirkwood_tclk;
 extern struct sys_timer kirkwood_timer;
 
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar  2 12:50:18 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri,  2 Mar 2012 17:50:18 +0000
Subject: [PATCH 1/5 v2] ARM: kirkwood: covert orion-spi to fdt.
In-Reply-To: <cover.1330709314.git.jason@lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
Message-ID: <a3c65ac8146eab1796dec771c1ddfe403d1471a9.1330709314.git.jason@lakedaemon.net>

On the Globalscale Dreamplug (Marvell Kirkwood Development Platform),
2MB of NOR flash are used to hold the bootloader, bootloader
environment, and devicetree blob.  It is connected via spi.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes from v1:

    - used of_match_ptr() as suggested by Grant Likely

 arch/arm/boot/dts/kirkwood-dreamplug.dts |   34 +++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c        |   40 ------------------------------
 arch/arm/mach-kirkwood/common.c          |   11 ++++++++
 drivers/spi/spi-orion.c                  |   37 ++++++++++++++++++++++++---
 4 files changed, 78 insertions(+), 44 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 8a5dff8..bdf2ddc 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -22,4 +22,38 @@
 		interrupts = <33>;
 		clock-frequency = <200000000>;
 	};
+
+	spi at f1010600 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		compatible = "marvell,orion-spi";
+		reg = <0xf1010600 0x1ff>;
+		clock-frequency = <200000000>;
+
+		flash at 0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			compatible = "macronix,mx25l1606e", "jedec-flash";
+
+			spi-max-frequency = <50000000>;
+			reg = <0>;
+
+			partition at 0 {
+				label = "U-Boot";
+				reg = <0x0 0x100000>;
+			};
+
+			partition at 100000 {
+				label = "U-Boot Environment";
+				reg = <0x100000 0x080000>;
+			};
+
+			partition at 180000 {
+				label = "Flattened Device Tree";
+				reg = <0x180000 0x080000>;
+			};
+		};
+	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index fbe6405..4960e63 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -39,42 +39,6 @@ static struct of_device_id kirkwood_dt_match_table[] __initdata = {
 	{ }
 };
 
-struct mtd_partition dreamplug_partitions[] = {
-	{
-		.name	= "u-boot",
-		.size	= SZ_512K,
-		.offset = 0,
-	},
-	{
-		.name	= "u-boot env",
-		.size	= SZ_64K,
-		.offset = SZ_512K + SZ_512K,
-	},
-	{
-		.name	= "dtb",
-		.size	= SZ_64K,
-		.offset = SZ_512K + SZ_512K + SZ_512K,
-	},
-};
-
-static const struct flash_platform_data dreamplug_spi_slave_data = {
-	.type		= "mx25l1606e",
-	.name		= "spi_flash",
-	.parts		= dreamplug_partitions,
-	.nr_parts	= ARRAY_SIZE(dreamplug_partitions),
-};
-
-static struct spi_board_info __initdata dreamplug_spi_slave_info[] = {
-	{
-		.modalias	= "m25p80",
-		.platform_data	= &dreamplug_spi_slave_data,
-		.irq		= -1,
-		.max_speed_hz	= 50000000,
-		.bus_num	= 0,
-		.chip_select	= 0,
-	},
-};
-
 static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
 	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
 };
@@ -140,10 +104,6 @@ static void __init dreamplug_init(void)
 	 */
 	kirkwood_mpp_conf(dreamplug_mpp_config);
 
-	spi_register_board_info(dreamplug_spi_slave_info,
-				ARRAY_SIZE(dreamplug_spi_slave_info));
-	kirkwood_spi_init();
-
 	kirkwood_ehci_init();
 	kirkwood_ge00_init(&dreamplug_ge00_data);
 	kirkwood_ge01_init(&dreamplug_ge01_data);
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index cc15426..357fcde 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -15,6 +15,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mtd/nand.h>
 #include <linux/dma-mapping.h>
+#include <linux/of.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -481,6 +482,9 @@ static int __init kirkwood_clock_gate(void)
 {
 	unsigned int curr = readl(CLOCK_GATING_CTRL);
 	u32 dev, rev;
+#ifdef CONFIG_OF
+	struct device_node *dp;
+#endif
 
 	kirkwood_pcie_id(&dev, &rev);
 	printk(KERN_DEBUG "Gating clock of unused units\n");
@@ -524,6 +528,13 @@ static int __init kirkwood_clock_gate(void)
 	} else  /* keep this bit set for devices that don't have PCIe1 */
 		kirkwood_clk_ctrl |= CGC_PEX1;
 
+#ifdef CONFIG_OF
+	dp = of_find_node_by_path("/");
+	if (dp && of_device_is_available(of_find_compatible_node(dp, NULL,
+							  "marvell,orion-spi")))
+		kirkwood_clk_ctrl |= CGC_RUNIT;
+#endif
+
 	/* Now gate clock the required units */
 	writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
 	printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index 13448c8..acfb240 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -18,6 +18,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/orion_spi.h>
 #include <linux/module.h>
+#include <linux/of_device.h>
 #include <asm/unaligned.h>
 
 #define DRIVER_NAME			"orion_spi"
@@ -45,6 +46,8 @@ struct orion_spi {
 	void __iomem		*base;
 	unsigned int		max_speed;
 	unsigned int		min_speed;
+	unsigned int		tclk;
+	unsigned int		clock_fix;
 	struct orion_spi_info	*spi_info;
 };
 
@@ -104,7 +107,7 @@ static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
 
 	orion_spi = spi_master_get_devdata(spi->master);
 
-	tclk_hz = orion_spi->spi_info->tclk;
+	tclk_hz = orion_spi->tclk;
 
 	/*
 	 * the supported rates are: 4,6,8...30
@@ -360,7 +363,7 @@ static int orion_spi_setup(struct spi_device *spi)
 	orion_spi = spi_master_get_devdata(spi->master);
 
 	/* Fix ac timing if required.   */
-	if (orion_spi->spi_info->enable_clock_fix)
+	if (orion_spi->clock_fix)
 		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
 				  (1 << 14));
 
@@ -474,6 +477,7 @@ static int __init orion_spi_probe(struct platform_device *pdev)
 	master->setup = orion_spi_setup;
 	master->transfer = orion_spi_transfer;
 	master->num_chipselect = ORION_NUM_CHIPSELECTS;
+	master->dev.of_node = pdev->dev.of_node;
 
 	dev_set_drvdata(&pdev->dev, master);
 
@@ -481,8 +485,26 @@ static int __init orion_spi_probe(struct platform_device *pdev)
 	spi->master = master;
 	spi->spi_info = spi_info;
 
-	spi->max_speed = DIV_ROUND_UP(spi_info->tclk, 4);
-	spi->min_speed = DIV_ROUND_UP(spi_info->tclk, 30);
+	if (spi_info)
+		spi->tclk = spi_info->tclk;
+
+	of_property_read_u32(master->dev.of_node,
+				"clock-frequency", &spi->tclk);
+
+	if (!spi->tclk) {
+		dev_err(&pdev->dev, "cannot set clock rate\n");
+		status = -EINVAL;
+		goto out;
+	}
+
+	spi->max_speed = DIV_ROUND_UP(spi->tclk, 4);
+	spi->min_speed = DIV_ROUND_UP(spi->tclk, 30);
+
+	if (spi_info)
+		spi->clock_fix = spi_info->enable_clock_fix;
+
+	if (of_find_property(master->dev.of_node, "spi-clock-fix", NULL))
+		spi->clock_fix = 1;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
@@ -541,10 +563,17 @@ static int __exit orion_spi_remove(struct platform_device *pdev)
 
 MODULE_ALIAS("platform:" DRIVER_NAME);
 
+static struct of_device_id spi_orion_of_match_table[] __devinitdata = {
+	{ .compatible = "marvell,orion-spi", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, spi_orion_of_match_table);
+
 static struct platform_driver orion_spi_driver = {
 	.driver = {
 		.name	= DRIVER_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(spi_orion_of_match_table),
 	},
 	.remove		= __exit_p(orion_spi_remove),
 };
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar  2 12:52:33 2012
From: jason at lakedaemon.net (Jason)
Date: Fri, 2 Mar 2012 12:52:33 -0500
Subject: [PULL REQUEST] ARM: kirkwood: fdt: convert kirkwood init funcs
 to fdt
In-Reply-To: <cover.1330709314.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <cover.1330709314.git.jason@lakedaemon.net>
Message-ID: <20120302175233.GM11986@titan.lakedaemon.net>

The following changes since commit 759a45185ac0e4dfaf8bbfcb390ec73aca4b7a34:

  ARM: kirkwood: convert uart0 to devicetree. (2012-02-27 16:21:44 +0000)

are available in the git repository at:
  git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_test

Jason Cooper (5):
      ARM: kirkwood: covert orion-spi to fdt.
      ARM: kirkwood: move var setting to correct location.
      ARM: kirkwood: fdt: absorb kirkwood_init()
      ARM: kirkwood: convert rtc-mv to fdt.
      ARM: kirkwood: convert orion-wdt to fdt.

 arch/arm/boot/dts/kirkwood-dreamplug.dts |   34 +++++++++++++++
 arch/arm/boot/dts/kirkwood.dtsi          |   12 +++++
 arch/arm/mach-kirkwood/board-dt.c        |   67 +++++++++++------------------
 arch/arm/mach-kirkwood/common.c          |   21 +++++++--
 arch/arm/mach-kirkwood/common.h          |    6 +++
 drivers/rtc/rtc-mv.c                     |    7 +++
 drivers/spi/spi-orion.c                  |   37 +++++++++++++++--
 drivers/watchdog/orion_wdt.c             |   48 ++++++++++++++++-----
 8 files changed, 170 insertions(+), 62 deletions(-)


From jason at lakedaemon.net  Fri Mar  2 12:56:18 2012
From: jason at lakedaemon.net (Jason)
Date: Fri, 2 Mar 2012 12:56:18 -0500
Subject: [PULL REQUEST] ARM: kirkwood: fdt: convert kirkwood init funcs
 to fdt
In-Reply-To: <20120302175233.GM11986@titan.lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <cover.1330709314.git.jason@lakedaemon.net>
 <20120302175233.GM11986@titan.lakedaemon.net>
Message-ID: <20120302175618.GN11986@titan.lakedaemon.net>

Oops, forgot to remove the Re:...

On Fri, Mar 02, 2012 at 12:52:33PM -0500, Jason wrote:
> The following changes since commit 759a45185ac0e4dfaf8bbfcb390ec73aca4b7a34:
> 
>   ARM: kirkwood: convert uart0 to devicetree. (2012-02-27 16:21:44 +0000)
> 
> are available in the git repository at:
>   git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_test
> 
> Jason Cooper (5):
>       ARM: kirkwood: covert orion-spi to fdt.
>       ARM: kirkwood: move var setting to correct location.
>       ARM: kirkwood: fdt: absorb kirkwood_init()
>       ARM: kirkwood: convert rtc-mv to fdt.
>       ARM: kirkwood: convert orion-wdt to fdt.
> 
>  arch/arm/boot/dts/kirkwood-dreamplug.dts |   34 +++++++++++++++
>  arch/arm/boot/dts/kirkwood.dtsi          |   12 +++++
>  arch/arm/mach-kirkwood/board-dt.c        |   67 +++++++++++------------------
>  arch/arm/mach-kirkwood/common.c          |   21 +++++++--
>  arch/arm/mach-kirkwood/common.h          |    6 +++
>  drivers/rtc/rtc-mv.c                     |    7 +++
>  drivers/spi/spi-orion.c                  |   37 +++++++++++++++--
>  drivers/watchdog/orion_wdt.c             |   48 ++++++++++++++++-----
>  8 files changed, 170 insertions(+), 62 deletions(-)
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From tony at atomide.com  Fri Mar  2 13:08:48 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 10:08:48 -0800
Subject: [PATCH 1/4] gpiolib: Add gpiochip_find_by_name() and
 gpio_find_by_chip_name()
In-Reply-To: <20120302170327.GF18901@atomide.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185524.29210.60381.stgit@kaulin.local>
 <20120302075804.F28DB3E2DB4@localhost>
 <20120302170327.GF18901@atomide.com>
Message-ID: <20120302180848.GM18901@atomide.com>

* Tony Lindgren <tony at atomide.com> [120302 08:31]:
> * Grant Likely <grant.likely at secretlab.ca> [120302 01:00]:
> > On Thu, 01 Mar 2012 10:55:24 -0800, Tony Lindgren <tony at atomide.com> wrote:
> > > +
> > > +/**
> > > + * gpiochip_find_by_name() - iterator for locating a gpio_chip by name
> > > + * @name: name of the gpio_chip
> > > + *
> > > + * Similar to bus_find_device_by_name. It returns a reference to the
> > > + * first gpio_chip with matching name. It ignores NULL and empty names.
> > > + * If you need to do something more complex, then use gpiochip_find.
> > > + */
> > > +struct gpio_chip *gpiochip_find_by_name(const char *name)
> > > +{
> > > +	if (!name || !strcmp(name, ""))
> > > +		return NULL;
> > > +
> > > +	return gpiochip_find((void *)name, match_name);
> > 
> > Nasty cast.  Can the signature for gpiochip_find be changed to accept
> > a (const void *)?
> 
> I think so, this too comes from the bus code.

Looks like it can't be const as of_node_to_gpiochip uses it with
a struct device_node * that for of_get_named_gpio_flags comes from
of_parse_phandle_with_args.

Regards,

Tony


From balbi at ti.com  Fri Mar  2 13:15:23 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 2 Mar 2012 20:15:23 +0200
Subject: [PATCH 11/12] mfd: twl4030-irq: Return twl6030_mmc_card_detect
 IRQ for board setup
In-Reply-To: <1330707024-23730-12-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-12-git-send-email-b-cousson@ti.com>
Message-ID: <20120302181522.GC13967@legolas.emea.dhcp.ti.com>

Hi,

On Fri, Mar 02, 2012 at 05:50:23PM +0100, Benoit Cousson wrote:
> Card detect IRQ from the TWL6030 used to be provided to the MMC
> controller code using a statically allocated IRQ scheme:
> 
>   card_detect_irq = TWL6030_IRQ_BASE + MMCDETECT_INTR_OFFSET;
> 
> This is no longer valid in a SPARSE_IRQ context since there is no more
> pre-defined TWL6030_IRQ_BASE.
> 
> Return the proper card detect IRQ value in the twl6030_mmc_card_detect_config
> that will be called from the MMC controller.
> 
> Signed-off-by: Benoit Cousson <b-cousson at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Rajendra Nayak <rnayak at ti.com>

Reviewed-by: Felipe Balbi <balbi at ti.com>

> ---
>  drivers/mfd/twl6030-irq.c |    3 ++-
>  1 files changed, 2 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
> index a1c7183..4a63de2 100644
> --- a/drivers/mfd/twl6030-irq.c
> +++ b/drivers/mfd/twl6030-irq.c
> @@ -308,7 +308,8 @@ int twl6030_mmc_card_detect_config(void)
>  									ret);
>  		return ret;
>  	}
> -	return 0;
> +
> +	return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
>  }
>  EXPORT_SYMBOL(twl6030_mmc_card_detect_config);

At some point this twl6030_mmc_card_detect_config() needs to vanish in
favor of a better mechanism. Maybe passing the GPIO number an requiring
the driver to request the GPIO, set its direction and use it as IRQ
line.

the only problem would arise if we end up hooking the Card Detect pin to
a real IRQ line, but then we can use a flag to differentiate.

-- 
balbi
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From swarren at nvidia.com  Fri Mar  2 13:24:34 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Fri, 2 Mar 2012 10:24:34 -0800
Subject: [PATCH] pinctrl: resurrect verbose pinmux-pins
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE861991@HQMAIL01.nvidia.com>
References: <1330705873-10798-1-git-send-email-linus.walleij@stericsson.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861978@HQMAIL01.nvidia.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861991@HQMAIL01.nvidia.com>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE8619C2@HQMAIL01.nvidia.com>

Stephen Warren wrote at Friday, March 02, 2012 10:41 AM:
> Stephen Warren wrote at Friday, March 02, 2012 10:22 AM:
> > Linus Walleij wrote at riday, March 02, 2012 9:31 AM:
> > > From: Linus Walleij <linus.walleij at linaro.org>
> > >
> > > This reintroduces the verbosity in the pinmux-pins file, now this
> > > file will list all pins, their names, owning device (and if it's
> > > a hog) and also in applicable cases the function and group making
> > > use of that pin right now.
> > >
> > > Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> >
> > It'd be nice if we could defer this fix until after all the API rework,
> > because it'll cause all kinds of conflicts otherwise.
> 
> Oh, I see this patch is in your for-next branch already before I had a chance
> to comment on it. I guess I'll have write a patch to convert the removed struct
> type to char*s and rebase on top of it:-(

I take that back. Can we please drop this patch and I'll provide an
equivalent in my API rework series?

The main reason is that before the API rework (i.e. what's currently in
pinctrl's for-next branch where the patch was written), the function/group
are set during pinctrl_get(state), whereas after the API rework they aren't
known or set until pinctrl_select_state(state). This is exactly why I
removed the code that saved the function value in the per-pin data-structure
from pinctrl_get() in the first place.

If we don't drop the patch, once of my patches is going to have to
basically include a revert of it, and then a reimplementation of this
patch in the correct place anyway, so we may as well just not apply it
in the first place.

Thanks.

-- 
nvpublic



From arnd at arndb.de  Fri Mar  2 13:32:33 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 18:32:33 +0000
Subject: [PATCH 5/5 v2] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <e2fe5e97a83fc753559bbb18d5d111ed01b89034.1330709314.git.jason@lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <e2fe5e97a83fc753559bbb18d5d111ed01b89034.1330709314.git.jason@lakedaemon.net>
Message-ID: <201203021832.34901.arnd@arndb.de>

On Friday 02 March 2012, Jason Cooper wrote:
> +       wdt_reg = (void __iomem *)TIMER_VIRT_BASE;
> +
> +       ret = of_address_to_resource(np, 0, &res);
> +       if (ret) {
> +               printk(KERN_ERR "invalid address\n");
> +               return ret;
> +       }
> +
> +       wdt_reg = ioremap(res.start, res.end - res.start);
> +

This will break non-dt uses because you overwrite the wdt_reg value.

As I commented before, I think the best approach would be to
provide a hardcoded resource for the device in the legacy case
and just use platform_get_resource() to get the resource
and ioremap it in either case.

of_address_to_resource() works only for the DT case, while
platform_get_resource() works in either case.

You need to add something like

8<---
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 089899a..d16f43f 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -568,13 +568,17 @@ void __init orion_spi_1_init(unsigned long mapbase,
  ****************************************************************************/
 static struct orion_wdt_platform_data orion_wdt_data;
 
+static struct resource orion_wdt_resource =
+               DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x28);
+
 static struct platform_device orion_wdt_device = {
        .name           = "orion_wdt",
        .id             = -1,
        .dev            = {
                .platform_data  = &orion_wdt_data,
        },
-       .num_resources  = 0,
+       .resources      = &orion_wdt_resource,
+       .num_resources  = 1,
 };
 
 void __init orion_wdt_init(unsigned long tclk)
---->8

and an appropriate definition for TIMER_PHYS_BASE.


	Arnd


From grant.likely at secretlab.ca  Fri Mar  2 13:48:33 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 02 Mar 2012 11:48:33 -0700
Subject: [PATCH 1/4] gpiolib: Add gpiochip_find_by_name() and
 gpio_find_by_chip_name()
In-Reply-To: <20120302180848.GM18901@atomide.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185524.29210.60381.stgit@kaulin.local>
 <20120302075804.F28DB3E2DB4@localhost> <20120302170327.GF18901@atomide.com>
 <20120302180848.GM18901@atomide.com>
Message-ID: <20120302184833.C296A3E1C63@localhost>

On Fri, 2 Mar 2012 10:08:48 -0800, Tony Lindgren <tony at atomide.com> wrote:
> * Tony Lindgren <tony at atomide.com> [120302 08:31]:
> > * Grant Likely <grant.likely at secretlab.ca> [120302 01:00]:
> > > On Thu, 01 Mar 2012 10:55:24 -0800, Tony Lindgren <tony at atomide.com> wrote:
> > > > +
> > > > +/**
> > > > + * gpiochip_find_by_name() - iterator for locating a gpio_chip by name
> > > > + * @name: name of the gpio_chip
> > > > + *
> > > > + * Similar to bus_find_device_by_name. It returns a reference to the
> > > > + * first gpio_chip with matching name. It ignores NULL and empty names.
> > > > + * If you need to do something more complex, then use gpiochip_find.
> > > > + */
> > > > +struct gpio_chip *gpiochip_find_by_name(const char *name)
> > > > +{
> > > > +	if (!name || !strcmp(name, ""))
> > > > +		return NULL;
> > > > +
> > > > +	return gpiochip_find((void *)name, match_name);
> > > 
> > > Nasty cast.  Can the signature for gpiochip_find be changed to accept
> > > a (const void *)?
> > 
> > I think so, this too comes from the bus code.
> 
> Looks like it can't be const as of_node_to_gpiochip uses it with
> a struct device_node * that for of_get_named_gpio_flags comes from
> of_parse_phandle_with_args.

Really? It sees to work fine here:

---

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index d773540..e633a2a 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1152,8 +1152,9 @@ EXPORT_SYMBOL_GPL(gpiochip_remove);
  * non-zero, this function will return to the caller and not iterate over any
  * more gpio_chips.
  */
-struct gpio_chip *gpiochip_find(void *data,
-				int (*match)(struct gpio_chip *chip, void *data))
+struct gpio_chip *gpiochip_find(const void *data,
+				int (*match)(struct gpio_chip *chip,
+					     const void *data))
 {
 	struct gpio_chip *chip = NULL;
 	unsigned long flags;
diff --git a/drivers/of/gpio.c b/drivers/of/gpio.c
index e034b38..bba8121 100644
--- a/drivers/of/gpio.c
+++ b/drivers/of/gpio.c
@@ -229,7 +229,7 @@ void of_gpiochip_remove(struct gpio_chip *chip)
 }
 
 /* Private function for resolving node pointer to gpio_chip */
-static int of_gpiochip_is_match(struct gpio_chip *chip, void *data)
+static int of_gpiochip_is_match(struct gpio_chip *chip, const void *data)
 {
 	return chip->of_node == data;
 }
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 1ff4e22..5f52690 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -142,9 +142,9 @@ extern int __must_check gpiochip_reserve(int start, int ngpio);
 /* add/remove chips */
 extern int gpiochip_add(struct gpio_chip *chip);
 extern int __must_check gpiochip_remove(struct gpio_chip *chip);
-extern struct gpio_chip *gpiochip_find(void *data,
+extern struct gpio_chip *gpiochip_find(const void *data,
 					int (*match)(struct gpio_chip *chip,
-						     void *data));
+						     const void *data));
 
 
 /* Always use the library code for GPIO management calls,



From tony at atomide.com  Fri Mar  2 13:35:05 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 10:35:05 -0800
Subject: [PATCH 2/4] mmc: omap_hsmmc: Use gpio_find_by_chip_name() for
 omap_hsmmc_gpio_init()
In-Reply-To: <20120302170830.GH18901@atomide.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185528.29210.85854.stgit@kaulin.local>
 <4F5075EE.1050902@ti.com> <20120302170830.GH18901@atomide.com>
Message-ID: <20120302183505.GN18901@atomide.com>

* Tony Lindgren <tony at atomide.com> [120302 08:38]:
> * Rajendra Nayak <rnayak at ti.com> [120301 22:54]:
>
> > >@@ -2093,8 +2123,7 @@ err1:
> > >  	platform_set_drvdata(pdev, NULL);
> > >  	mmc_free_host(mmc);
> > >  err_alloc:
> > >-	omap_hsmmc_gpio_free(pdata);
> > >-err:
> > >+	omap_hsmmc_gpio_free(host);
> > 
> > This error handling needs to be fixed up. In case
> > omap_hsmmc_gpio_init() fails, which already frees up
> > any requested gpios, omap_hsmmc_gpio_free() again tries
> > freeing gpios.
> 
> Hmm that sounds like a separate patch that should be a fixed
> before this series?

Nope, I was confused. The error handling needs to change
as the omap_hsmmc_gpio_init() got moved later so host is
initialized. Will fix.

Regards,

Tony


From tony at atomide.com  Fri Mar  2 14:06:15 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 11:06:15 -0800
Subject: [PATCH 1/4] gpiolib: Add gpiochip_find_by_name() and
 gpio_find_by_chip_name()
In-Reply-To: <20120302184833.C296A3E1C63@localhost>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185524.29210.60381.stgit@kaulin.local>
 <20120302075804.F28DB3E2DB4@localhost>
 <20120302170327.GF18901@atomide.com>
 <20120302180848.GM18901@atomide.com>
 <20120302184833.C296A3E1C63@localhost>
Message-ID: <20120302190614.GO18901@atomide.com>

* Grant Likely <grant.likely at secretlab.ca> [120302 10:16]:
> On Fri, 2 Mar 2012 10:08:48 -0800, Tony Lindgren <tony at atomide.com> wrote:
> > * Tony Lindgren <tony at atomide.com> [120302 08:31]:
> > > * Grant Likely <grant.likely at secretlab.ca> [120302 01:00]:
> > > > On Thu, 01 Mar 2012 10:55:24 -0800, Tony Lindgren <tony at atomide.com> wrote:
> > > > > +
> > > > > +/**
> > > > > + * gpiochip_find_by_name() - iterator for locating a gpio_chip by name
> > > > > + * @name: name of the gpio_chip
> > > > > + *
> > > > > + * Similar to bus_find_device_by_name. It returns a reference to the
> > > > > + * first gpio_chip with matching name. It ignores NULL and empty names.
> > > > > + * If you need to do something more complex, then use gpiochip_find.
> > > > > + */
> > > > > +struct gpio_chip *gpiochip_find_by_name(const char *name)
> > > > > +{
> > > > > +	if (!name || !strcmp(name, ""))
> > > > > +		return NULL;
> > > > > +
> > > > > +	return gpiochip_find((void *)name, match_name);
> > > > 
> > > > Nasty cast.  Can the signature for gpiochip_find be changed to accept
> > > > a (const void *)?
> > > 
> > > I think so, this too comes from the bus code.
> > 
> > Looks like it can't be const as of_node_to_gpiochip uses it with
> > a struct device_node * that for of_get_named_gpio_flags comes from
> > of_parse_phandle_with_args.
> 
> Really? It sees to work fine here:

Hmm right you are. I must have missed adding the const to
of_gpiochip_is_match, that's good news :)

Want to do that as a separate patch or want me to fold it in?

Tony
 
> ---
> 
> diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
> index d773540..e633a2a 100644
> --- a/drivers/gpio/gpiolib.c
> +++ b/drivers/gpio/gpiolib.c
> @@ -1152,8 +1152,9 @@ EXPORT_SYMBOL_GPL(gpiochip_remove);
>   * non-zero, this function will return to the caller and not iterate over any
>   * more gpio_chips.
>   */
> -struct gpio_chip *gpiochip_find(void *data,
> -				int (*match)(struct gpio_chip *chip, void *data))
> +struct gpio_chip *gpiochip_find(const void *data,
> +				int (*match)(struct gpio_chip *chip,
> +					     const void *data))
>  {
>  	struct gpio_chip *chip = NULL;
>  	unsigned long flags;
> diff --git a/drivers/of/gpio.c b/drivers/of/gpio.c
> index e034b38..bba8121 100644
> --- a/drivers/of/gpio.c
> +++ b/drivers/of/gpio.c
> @@ -229,7 +229,7 @@ void of_gpiochip_remove(struct gpio_chip *chip)
>  }
>  
>  /* Private function for resolving node pointer to gpio_chip */
> -static int of_gpiochip_is_match(struct gpio_chip *chip, void *data)
> +static int of_gpiochip_is_match(struct gpio_chip *chip, const void *data)
>  {
>  	return chip->of_node == data;
>  }
> diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
> index 1ff4e22..5f52690 100644
> --- a/include/asm-generic/gpio.h
> +++ b/include/asm-generic/gpio.h
> @@ -142,9 +142,9 @@ extern int __must_check gpiochip_reserve(int start, int ngpio);
>  /* add/remove chips */
>  extern int gpiochip_add(struct gpio_chip *chip);
>  extern int __must_check gpiochip_remove(struct gpio_chip *chip);
> -extern struct gpio_chip *gpiochip_find(void *data,
> +extern struct gpio_chip *gpiochip_find(const void *data,
>  					int (*match)(struct gpio_chip *chip,
> -						     void *data));
> +						     const void *data));
>  
>  
>  /* Always use the library code for GPIO management calls,
> 


From grant.likely at secretlab.ca  Fri Mar  2 14:14:53 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 02 Mar 2012 12:14:53 -0700
Subject: [PATCH] Initial Device Tree system for Snowball
In-Reply-To: <1330703567-17925-1-git-send-email-niklas.hernaeus@stericsson.com>
References: <1330703567-17925-1-git-send-email-niklas.hernaeus@stericsson.com>
Message-ID: <20120302191453.C972F3E1C63@localhost>

On Fri, 2 Mar 2012 16:52:47 +0100, Niklas Hernaeus <niklas.hernaeus at stericsson.com> wrote:
> From: Niklas Hernaeus <niklas.hernaeus at linaro.org>
> 
> This is the base system for using Device Tree for Snowball.
> The new boardfile is a slightly modified copy of the original board file,
> so new Device Tree stuff can simply be added and code removed, while
> functionality stays the same.
> 
> Signed-off-by: Niklas Hernaeus <niklas.hernaeus at linaro.org>
> ---
>  arch/arm/boot/dts/snowball.dts          |   32 ++
>  arch/arm/mach-ux500/Kconfig             |   17 +-
>  arch/arm/mach-ux500/Makefile            |    5 +-
>  arch/arm/mach-ux500/board-mop500-dt.c   |  729 +++++++++++++++++++++++++++++++
>  arch/arm/mach-ux500/include/mach/irqs.h |    2 +-
>  5 files changed, 779 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm/boot/dts/snowball.dts
>  create mode 100644 arch/arm/mach-ux500/board-mop500-dt.c
> 
> diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
> new file mode 100644
> index 0000000..02305fb
> --- /dev/null
> +++ b/arch/arm/boot/dts/snowball.dts
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright 2011 ST-Ericsson AB
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +
> +/ {
> +	model = "Calao Systems Snowball platform with device tree";
> +	compatible = "calaosystems,snowball-a9500";
> +
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x20000000>;
> +	};
> +
> +	soc-u9500 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		ranges;
> +	};
> +};
> diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
> index 52af004..be7e4fe 100644
> --- a/arch/arm/mach-ux500/Kconfig
> +++ b/arch/arm/mach-ux500/Kconfig
> @@ -27,19 +27,22 @@ menu "Ux500 target platform (boards)"
>  config MACH_U8500
>  	bool "U8500 Development platform"
>  	depends on UX500_SOC_DB8500
> +	depends on !USE_OF

Hi Niklas,

Don't make any configurations depend on !USE_OF.  Turning on device
tree support must not disable non-DT booting.  This is a policy
decision made a while ago.  You'll need to ensure the code is
structured so that the DT and non-DT code paths can co-exist.

>  	select TPS6105X
>  	help
>  	  Include support for the mop500 development platform.
>  
>  config MACH_HREFV60
> -       bool "U85000 Development platform, HREFv60 version"
> -       depends on UX500_SOC_DB8500
> -       help
> -         Include support for the HREFv60 new development platform.
> +	bool "U85000 Development platform, HREFv60 version"
> +	depends on UX500_SOC_DB8500
> +	depends on !USE_OF

Ditto here.

> +	help
> +	  Include support for the HREFv60 new development platform.
>  
>  config MACH_SNOWBALL
>  	bool "U8500 Snowball platform"
>  	depends on UX500_SOC_DB8500
> +	depends on !USE_OF
>  	select MACH_U8500
>  	help
>  	  Include support for the snowball development platform.
> @@ -49,6 +52,12 @@ config MACH_U5500
>  	depends on UX500_SOC_DB5500
>  	help
>  	  Include support for the U5500 development platform.
> +config MACH_UX500_DT
> +	def_bool y if USE_OF
> +	depends on UX500_SOC_DB8500 || UX500_SOC_DB5500
> +
> +config MACH_MOP500
> +	def_bool y if MACH_U8500 || MACH_UX500_DT
>  endmenu


From grant.likely at secretlab.ca  Fri Mar  2 14:20:32 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 02 Mar 2012 12:20:32 -0700
Subject: [PATCH 1/3 v3] spi: move master of_node init to spi_alloc_master
In-Reply-To: <1330682587-20636-1-git-send-email-plagnioj@jcrosoft.com>
References: <1330682587-20636-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120302192032.3ACF33E1C63@localhost>

On Fri,  2 Mar 2012 11:03:05 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: spi-devel-general at lists.sourceforge.net
> Cc: Grant Likely <grant.likely at secretlab.ca>

Actually, the of_node pointer setting was purposefully left out
of spi_alloc_master() because it is not necesarily true that the
dt node associated with the struct device will be the node where
all the spi children are parented.  I want to leave this
initialization in the drivers.

g.



From tony at atomide.com  Fri Mar  2 14:20:58 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 11:20:58 -0800
Subject: [PATCH 11/12] mfd: twl4030-irq: Return twl6030_mmc_card_detect
 IRQ for board setup
In-Reply-To: <20120302181522.GC13967@legolas.emea.dhcp.ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-12-git-send-email-b-cousson@ti.com>
 <20120302181522.GC13967@legolas.emea.dhcp.ti.com>
Message-ID: <20120302192058.GP18901@atomide.com>

* Felipe Balbi <balbi at ti.com> [120302 09:43]:
> Hi,
> 
> On Fri, Mar 02, 2012 at 05:50:23PM +0100, Benoit Cousson wrote:
> > Card detect IRQ from the TWL6030 used to be provided to the MMC
> > controller code using a statically allocated IRQ scheme:
> > 
> >   card_detect_irq = TWL6030_IRQ_BASE + MMCDETECT_INTR_OFFSET;
> > 
> > This is no longer valid in a SPARSE_IRQ context since there is no more
> > pre-defined TWL6030_IRQ_BASE.
> > 
> > Return the proper card detect IRQ value in the twl6030_mmc_card_detect_config
> > that will be called from the MMC controller.
> > 
> > Signed-off-by: Benoit Cousson <b-cousson at ti.com>
> > Cc: Felipe Balbi <balbi at ti.com>
> > Cc: Tony Lindgren <tony at atomide.com>
> > Cc: Rajendra Nayak <rnayak at ti.com>
> 
> Reviewed-by: Felipe Balbi <balbi at ti.com>
> 
> > ---
> >  drivers/mfd/twl6030-irq.c |    3 ++-
> >  1 files changed, 2 insertions(+), 1 deletions(-)
> > 
> > diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
> > index a1c7183..4a63de2 100644
> > --- a/drivers/mfd/twl6030-irq.c
> > +++ b/drivers/mfd/twl6030-irq.c
> > @@ -308,7 +308,8 @@ int twl6030_mmc_card_detect_config(void)
> >  									ret);
> >  		return ret;
> >  	}
> > -	return 0;
> > +
> > +	return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
> >  }
> >  EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
> 
> At some point this twl6030_mmc_card_detect_config() needs to vanish in
> favor of a better mechanism. Maybe passing the GPIO number an requiring
> the driver to request the GPIO, set its direction and use it as IRQ
> line.
> 
> the only problem would arise if we end up hooking the Card Detect pin to
> a real IRQ line, but then we can use a flag to differentiate.

I'm trying to leave out the need for this callback to pdata..
See mmc: omap_hsmmc: Simplify init for twl6030 MMC card detect
that does pretty much the same as Benoit's patch plus removes
the need for the callback.

Tony


From plagnioj at jcrosoft.com  Fri Mar  2 14:28:44 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 2 Mar 2012 20:28:44 +0100
Subject: [PATCH 0/6] AT91 more DT bindings
Message-ID: <20120302192844.GB21255@game.jcrosoft.org>

HI,

	The following patch series add the bindings for:
	 - PMC
	 - SDRAM/DDR Controller
	 - Reset Controller
	 - Shutdown Controller

The following changes since commit c5ec01650adb1976f928177cd7e71afcb82026c5:

  ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5 (2012-03-02 00:46:37 +0800)

are available in the git repository at:
  git://github.com/at91linux/linux-at91.git ..BRANCH.NOT.VERIFIED..

Jean-Christophe PLAGNIOL-VILLARD (6):
      ARM: at91/dt: add specific DT soc init
      ARM: at91: add pmc DT support
      ARM: at91: always enable sam9 restart
      ARM: at91: add RSTC (Reset Controller) dt support
      ARM: at91: add ram controller DT support
      ARM: at91: add Shutdown Controller (SHDWC) DT support

 .../devicetree/bindings/arm/atmel-at91.txt         |   60 ++++++++
 .../devicetree/bindings/arm/atmel-pmc.txt          |   11 ++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |   20 +++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |   21 +++
 arch/arm/boot/dts/at91sam9m10g45ek.dts             |   11 ++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |   20 +++
 arch/arm/boot/dts/at91sam9x5cm.dtsi                |   11 ++
 arch/arm/boot/dts/usb_a9g20.dts                    |   11 ++
 arch/arm/mach-at91/Kconfig                         |   10 +-
 arch/arm/mach-at91/at91sam9x5.c                    |    7 -
 arch/arm/mach-at91/board-dt.c                      |    8 +-
 arch/arm/mach-at91/clock.c                         |   54 ++++++-
 arch/arm/mach-at91/generic.h                       |    2 +
 arch/arm/mach-at91/include/mach/at91_shdwc.h       |    4 +-
 arch/arm/mach-at91/include/mach/at91sam9x5.h       |    5 -
 arch/arm/mach-at91/setup.c                         |  158 ++++++++++++++++++++
 16 files changed, 380 insertions(+), 33 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-pmc.txt

Best Regards,
J.


From jason at lakedaemon.net  Fri Mar  2 14:57:10 2012
From: jason at lakedaemon.net (Jason)
Date: Fri, 2 Mar 2012 14:57:10 -0500
Subject: [PATCH 5/5 v2] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <201203021832.34901.arnd@arndb.de>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <e2fe5e97a83fc753559bbb18d5d111ed01b89034.1330709314.git.jason@lakedaemon.net>
 <201203021832.34901.arnd@arndb.de>
Message-ID: <20120302195710.GP11986@titan.lakedaemon.net>

On Fri, Mar 02, 2012 at 06:32:33PM +0000, Arnd Bergmann wrote:
> On Friday 02 March 2012, Jason Cooper wrote:
> > +       wdt_reg = (void __iomem *)TIMER_VIRT_BASE;
> > +
> > +       ret = of_address_to_resource(np, 0, &res);
> > +       if (ret) {
> > +               printk(KERN_ERR "invalid address\n");
> > +               return ret;
> > +       }
> > +
> > +       wdt_reg = ioremap(res.start, res.end - res.start);
> > +
> 
> This will break non-dt uses because you overwrite the wdt_reg value.

I thought for non-dt configurations of_.*() zeroed out.  No problem, I
must've misunderstood something from earlier.

> As I commented before, I think the best approach would be to
> provide a hardcoded resource for the device in the legacy case
> and just use platform_get_resource() to get the resource
> and ioremap it in either case.

Sorry, my denseness got in the way.  When you said hardcoded, I thought
you meant #define TIMER_VIRT_BASE .

> of_address_to_resource() works only for the DT case, while
> platform_get_resource() works in either case.
> 
> You need to add something like

Ahh... now *that* makes sense.

> 8<---
> diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
> index 089899a..d16f43f 100644
> --- a/arch/arm/plat-orion/common.c
> +++ b/arch/arm/plat-orion/common.c
> @@ -568,13 +568,17 @@ void __init orion_spi_1_init(unsigned long mapbase,
>   ****************************************************************************/
>  static struct orion_wdt_platform_data orion_wdt_data;
>  
> +static struct resource orion_wdt_resource =
> +               DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x28);
> +
>  static struct platform_device orion_wdt_device = {
>         .name           = "orion_wdt",
>         .id             = -1,
>         .dev            = {
>                 .platform_data  = &orion_wdt_data,
>         },
> -       .num_resources  = 0,
> +       .resources      = &orion_wdt_resource,
> +       .num_resources  = 1,
>  };
>  
>  void __init orion_wdt_init(unsigned long tclk)
> ---->8
> 
> and an appropriate definition for TIMER_PHYS_BASE.

thx,

Jason.


From arnd at arndb.de  Fri Mar  2 15:02:59 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 20:02:59 +0000
Subject: [PATCH 5/5 v2] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <20120302195710.GP11986@titan.lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <201203021832.34901.arnd@arndb.de>
 <20120302195710.GP11986@titan.lakedaemon.net>
Message-ID: <201203022003.08756.arnd@arndb.de>

On Friday 02 March 2012, Jason wrote:
> On Fri, Mar 02, 2012 at 06:32:33PM +0000, Arnd Bergmann wrote:
>
> > As I commented before, I think the best approach would be to
> > provide a hardcoded resource for the device in the legacy case
> > and just use platform_get_resource() to get the resource
> > and ioremap it in either case.
> 
> Sorry, my denseness got in the way.  When you said hardcoded, I thought
> you meant #define TIMER_VIRT_BASE .

Using TIMER_VIRT_BASE wouldn't be all that wrong either, but I think it's
better to use the same code path in both ways. Using a resource also has
the nice side-effect of allowing us to build a multiplatform kernel for
anything that uses orion-wdt but has different constants for TIMER_VIRT_BASE.

	Arnd


From plagnioj at jcrosoft.com  Fri Mar  2 14:54:05 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri,  2 Mar 2012 20:54:05 +0100
Subject: [PATCH 3/6] ARM: at91: always enable sam9 restart
In-Reply-To: <20120302192844.GB21255@game.jcrosoft.org>
References: <20120302192844.GB21255@game.jcrosoft.org>
Message-ID: <1330718048-9314-3-git-send-email-plagnioj@jcrosoft.com>

This is need for multiple SoC in the same kernel image and DT.
As we will chose the restart function via binding.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/Kconfig |   10 ++--------
 1 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index e55cdcb..45db05d 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -20,9 +20,11 @@ config HAVE_AT91_USART5
 
 config AT91_SAM9_ALT_RESET
 	bool
+	default !ARCH_AT91X40
 
 config AT91_SAM9G45_RESET
 	bool
+	default !ARCH_AT91X40
 
 menu "Atmel AT91 System-on-Chip"
 
@@ -45,7 +47,6 @@ config ARCH_AT91SAM9260
 	select HAVE_AT91_USART4
 	select HAVE_AT91_USART5
 	select HAVE_NET_MACB
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9261
 	bool "AT91SAM9261"
@@ -53,7 +54,6 @@ config ARCH_AT91SAM9261
 	select GENERIC_CLOCKEVENTS
 	select HAVE_FB_ATMEL
 	select HAVE_AT91_DBGU0
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G10
 	bool "AT91SAM9G10"
@@ -61,7 +61,6 @@ config ARCH_AT91SAM9G10
 	select GENERIC_CLOCKEVENTS
 	select HAVE_AT91_DBGU0
 	select HAVE_FB_ATMEL
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9263
 	bool "AT91SAM9263"
@@ -70,7 +69,6 @@ config ARCH_AT91SAM9263
 	select HAVE_FB_ATMEL
 	select HAVE_NET_MACB
 	select HAVE_AT91_DBGU1
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9RL
 	bool "AT91SAM9RL"
@@ -79,7 +77,6 @@ config ARCH_AT91SAM9RL
 	select HAVE_AT91_USART3
 	select HAVE_FB_ATMEL
 	select HAVE_AT91_DBGU0
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G20
 	bool "AT91SAM9G20"
@@ -90,7 +87,6 @@ config ARCH_AT91SAM9G20
 	select HAVE_AT91_USART4
 	select HAVE_AT91_USART5
 	select HAVE_NET_MACB
-	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G45
 	bool "AT91SAM9G45"
@@ -100,7 +96,6 @@ config ARCH_AT91SAM9G45
 	select HAVE_FB_ATMEL
 	select HAVE_NET_MACB
 	select HAVE_AT91_DBGU1
-	select AT91_SAM9G45_RESET
 
 config ARCH_AT91SAM9X5
 	bool "AT91SAM9x5 family"
@@ -109,7 +104,6 @@ config ARCH_AT91SAM9X5
 	select HAVE_FB_ATMEL
 	select HAVE_NET_MACB
 	select HAVE_AT91_DBGU0
-	select AT91_SAM9G45_RESET
 
 config ARCH_AT91X40
 	bool "AT91x40"
-- 
1.7.7



From plagnioj at jcrosoft.com  Fri Mar  2 14:54:03 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri,  2 Mar 2012 20:54:03 +0100
Subject: [PATCH 1/6] ARM: at91/dt: add specific DT soc init
In-Reply-To: <20120302192844.GB21255@game.jcrosoft.org>
References: <20120302192844.GB21255@game.jcrosoft.org>
Message-ID: <1330718048-9314-1-git-send-email-plagnioj@jcrosoft.com>

This will allow to have static Device mapping and DT probe mapping for the
System Controller.

Temporary keep the call to ioremap_registers() until we have the binding
for the SDRAM/DDR Controller.

Temporary keep the main clock hardcoded to 12MHz until we have the binding
for the PMC.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/board-dt.c |    8 +-------
 arch/arm/mach-at91/generic.h  |    1 +
 arch/arm/mach-at91/setup.c    |   18 ++++++++++++++++++
 3 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index 9f729d6..c18d4d3 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -30,12 +30,6 @@
 #include "generic.h"
 
 
-static void __init ek_init_early(void)
-{
-	/* Initialize processor: 12.000 MHz crystal */
-	at91_initialize(12000000);
-}
-
 static const struct of_device_id irq_of_match[] __initconst = {
 
 	{ .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
@@ -65,7 +59,7 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
 	/* Maintainer: Atmel */
 	.timer		= &at91sam926x_timer,
 	.map_io		= at91_map_io,
-	.init_early	= ek_init_early,
+	.init_early	= at91_dt_initialize,
 	.init_irq	= at91_dt_init_irq,
 	.init_machine	= at91_dt_device_init,
 	.dt_compat	= at91_dt_board_compat,
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 459f01a..d5f5083 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -20,6 +20,7 @@ extern void __init at91_init_sram(int bank, unsigned long base,
 extern void __init at91rm9200_set_type(int type);
 extern void __init at91_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
+extern void __init at91_dt_initialize(void);
 
  /* Interrupts */
 extern void __init at91_init_irq_default(void);
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 372396c..c0bd5a6 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -9,6 +9,7 @@
 #include <linux/io.h>
 #include <linux/mm.h>
 #include <linux/pm.h>
+#include <linux/of_address.h>
 
 #include <asm/mach/map.h>
 
@@ -285,6 +286,23 @@ void __init at91_ioremap_matrix(u32 base_addr)
 		panic("Impossible to ioremap at91_matrix_base\n");
 }
 
+#if defined(CONFIG_OF)
+void __init at91_dt_initialize(void)
+{
+	/* temporary until have the ramc binding*/
+	at91_boot_soc.ioremap_registers();
+
+	/* temporary until have the pmc binding */
+	/* Init clock subsystem */
+	at91_clock_init(12000000);
+
+	/* Register the processor-specific clocks */
+	at91_boot_soc.register_clocks();
+
+	at91_boot_soc.init();
+}
+#endif
+
 void __init at91_initialize(unsigned long main_clock)
 {
 	at91_boot_soc.ioremap_registers();
-- 
1.7.7



From plagnioj at jcrosoft.com  Fri Mar  2 14:54:06 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri,  2 Mar 2012 20:54:06 +0100
Subject: [PATCH 4/6] ARM: at91: add RSTC (Reset Controller) dt support
In-Reply-To: <20120302192844.GB21255@game.jcrosoft.org>
References: <20120302192844.GB21255@game.jcrosoft.org>
Message-ID: <1330718048-9314-4-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 .../devicetree/bindings/arm/atmel-at91.txt         |   12 ++++++++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 +++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    5 +++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |    5 +++
 arch/arm/mach-at91/at91sam9x5.c                    |    1 -
 arch/arm/mach-at91/setup.c                         |   30 ++++++++++++++++++++
 6 files changed, 57 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 1aeaf6f..a64f867 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -30,3 +30,15 @@ One interrupt per TC channel in a TC block:
 		reg = <0xfffdc000 0x100>;
 		interrupts = <26 4 27 4 28 4>;
 	};
+
+RSTC Reset Controller required properties:
+- compatible: Should be "atmel,<chip>-rstc".
+  <chip> can be "at91sam9260" or "at91sam9g45"
+- reg: Should contain registers location and length
+
+Example:
+
+	rstc at fffffd00 {
+		compatible = "atmel,at91sam9260-rstc";
+		reg = <0xfffffd00 0x10>;
+	};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index ee94828..5414347 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -64,6 +64,11 @@
 				reg = <0xfffffc00 0x100>;
 			};
 
+			rstc at fffffd00 {
+				compatible = "atmel,at91sam9260-rstc";
+				reg = <0xfffffd00 0x10>;
+			};
+
 			pit: timer at fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index dfb71d5..e2ccba5 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -65,6 +65,11 @@
 				reg = <0xfffffc00 0x100>;
 			};
 
+			rstc at fffffd00 {
+				compatible = "atmel,at91sam9g45-rstc";
+				reg = <0xfffffd00 0x10>;
+			};
+
 			pit: timer at fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index a7d7107..54e3030 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -63,6 +63,11 @@
 				reg = <0xfffffc00 0x100>;
 			};
 
+			rstc at fffffe00 {
+				compatible = "atmel,at91sam9g45-rstc";
+				reg = <0xfffffe00 0x10>;
+			};
+
 			pit: timer at fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 7333276..0b82c34 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -309,7 +309,6 @@ static void __init at91sam9x5_ioremap_registers(void)
 
 void __init at91sam9x5_initialize(void)
 {
-	arm_pm_restart = at91sam9g45_restart;
 	at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
 
 	/* Register GPIO subsystem (using DT) */
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index d7abc25..3e48b59 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -287,8 +287,38 @@ void __init at91_ioremap_matrix(u32 base_addr)
 }
 
 #if defined(CONFIG_OF)
+static struct of_device_id rstc_ids[] = {
+	{ .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
+	{ .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
+	{ /*sentinel*/ }
+};
+
+static void at91_dt_rstc(void)
+{
+	struct device_node *np;
+	const struct of_device_id *of_id;
+
+	np = of_find_matching_node(NULL, rstc_ids);
+	if (!np)
+		panic("unable to find compatible rstc node in dtb\n");
+
+	at91_rstc_base = of_iomap(np, 0);
+	if (!at91_rstc_base)
+		panic("unable to map rstc cpu registers\n");
+
+	of_id = of_match_node(rstc_ids, np);
+	if (!of_id)
+		panic("AT91: rtsc no restart function availlable\n");
+
+	arm_pm_restart = of_id->data;
+
+	of_node_put(np);
+}
+
 void __init at91_dt_initialize(void)
 {
+	at91_dt_rstc();
+
 	/* temporary until have the ramc binding*/
 	at91_boot_soc.ioremap_registers();
 
-- 
1.7.7



From plagnioj at jcrosoft.com  Fri Mar  2 14:54:04 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri,  2 Mar 2012 20:54:04 +0100
Subject: [PATCH 2/6] ARM: at91: add pmc DT support
In-Reply-To: <20120302192844.GB21255@game.jcrosoft.org>
References: <20120302192844.GB21255@game.jcrosoft.org>
Message-ID: <1330718048-9314-2-git-send-email-plagnioj@jcrosoft.com>

Specified the main Oscillator via clock binding.
This will allow to do not hardcode it anymore in the DT board at 12MHz.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 .../devicetree/bindings/arm/atmel-pmc.txt          |   11 ++++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 ++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    5 ++
 arch/arm/boot/dts/at91sam9m10g45ek.dts             |   11 ++++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |    5 ++
 arch/arm/boot/dts/at91sam9x5cm.dtsi                |   11 ++++
 arch/arm/boot/dts/usb_a9g20.dts                    |   11 ++++
 arch/arm/mach-at91/clock.c                         |   56 ++++++++++++++++++--
 arch/arm/mach-at91/generic.h                       |    1 +
 arch/arm/mach-at91/setup.c                         |    3 +-
 10 files changed, 112 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-pmc.txt

diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
new file mode 100644
index 0000000..389bed5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
@@ -0,0 +1,11 @@
+* Power Management Controller (PMC)
+
+Required properties:
+- compatible: Should be "atmel,at91rm9200-pmc"
+- reg: Should contain PMC registers location and length
+
+Examples:
+	pmc: pmc at fffffc00 {
+		compatible = "atmel,at91rm9200-pmc";
+		reg = <0xfffffc00 0x100>;
+	};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index c030703..ee94828 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -59,6 +59,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pmc: pmc at fffffc00 {
+				compatible = "atmel,at91rm9200-pmc";
+				reg = <0xfffffc00 0x100>;
+			};
+
 			pit: timer at fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 4b54424..dfb71d5 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -60,6 +60,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pmc: pmc at fffffc00 {
+				compatible = "atmel,at91rm9200-pmc";
+				reg = <0xfffffc00 0x100>;
+			};
+
 			pit: timer at fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 4b1eb36..7147588 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -21,6 +21,17 @@
 		reg = <0x70000000 0x4000000>;
 	};
 
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		main_clock: clock at 0 {
+			compatible = "atmel,osc", "fixed-clock";
+			clock-frequency = <12000000>;
+		};
+	};
+
 	ahb {
 		apb {
 			dbgu: serial at ffffee00 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index ac3c96c..a7d7107 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -58,6 +58,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			pmc: pmc at fffffc00 {
+				compatible = "atmel,at91rm9200-pmc";
+				reg = <0xfffffc00 0x100>;
+			};
+
 			pit: timer at fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 3f84585..03116b2 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -12,6 +12,17 @@
 		reg = <0x20000000 0x8000000>;
 	};
 
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		main_clock: clock at 0 {
+			compatible = "atmel,osc", "fixed-clock";
+			clock-frequency = <12000000>;
+		};
+	};
+
 	ahb {
 		nand0: nand at 40000000 {
 			nand-bus-width = <8>;
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index e4a732f..390c481 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -20,6 +20,17 @@
 		reg = <0x20000000 0x4000000>;
 	};
 
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		main_clock: clock at 0 {
+			compatible = "atmel,osc", "fixed-clock";
+			clock-frequency = <12000000>;
+		};
+	};
+
 	ahb {
 		apb {
 			dbgu: serial at fffff200 {
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index be51ca7..a0f4d74 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -23,6 +23,7 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
 
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
@@ -671,16 +672,12 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
 	uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
 
-int __init at91_clock_init(unsigned long main_clock)
+static int __init at91_pmc_init(unsigned long main_clock)
 {
 	unsigned tmp, freq, mckr;
 	int i;
 	int pll_overclock = false;
 
-	at91_pmc_base = ioremap(AT91_PMC, 256);
-	if (!at91_pmc_base)
-		panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
-
 	/*
 	 * When the bootloader initialized the main oscillator correctly,
 	 * there's no problem using the cycle counter.  But if it didn't,
@@ -802,6 +799,55 @@ int __init at91_clock_init(unsigned long main_clock)
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static struct of_device_id pmc_ids[] = {
+	{ .compatible = "atmel,at91rm9200-pmc" },
+	{ /*sentinel*/ }
+};
+
+static struct of_device_id osc_ids[] = {
+	{ .compatible = "atmel,osc" },
+	{ /*sentinel*/ }
+};
+
+int __init at91_dt_clock_init(void)
+{
+	struct device_node *np;
+	u32 main_clock = 0;
+
+	np = of_find_matching_node(NULL, pmc_ids);
+	if (!np)
+		panic("unable to find compatible pmc node in dtb\n");
+
+	at91_pmc_base = of_iomap(np, 0);
+	if (!at91_pmc_base)
+		panic("unable to map pmc cpu registers\n");
+
+	of_node_put(np);
+
+	/* retrieve the freqency of fixed clocks from device tree */
+	np = of_find_matching_node(NULL, osc_ids);
+	if (np) {
+		u32 rate;
+		if (!of_property_read_u32(np, "clock-frequency", &rate))
+			main_clock = rate;
+	}
+
+	of_node_put(np);
+
+	return at91_pmc_init(main_clock);
+}
+#endif
+
+int __init at91_clock_init(unsigned long main_clock)
+{
+	at91_pmc_base = ioremap(AT91_PMC, 256);
+	if (!at91_pmc_base)
+		panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
+
+	return at91_pmc_init(main_clock);
+}
+
 /*
  * Several unused clocks may be active.  Turn them off.
  */
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index d5f5083..dd9b346 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -53,6 +53,7 @@ extern void __init at91sam9rl_set_console_clock(int id);
 extern void __init at91sam9g45_set_console_clock(int id);
 #ifdef CONFIG_AT91_PMC_UNIT
 extern int __init at91_clock_init(unsigned long main_clock);
+extern int __init at91_dt_clock_init(void);
 #else
 static int inline at91_clock_init(unsigned long main_clock) { return 0; }
 #endif
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index c0bd5a6..d7abc25 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -292,9 +292,8 @@ void __init at91_dt_initialize(void)
 	/* temporary until have the ramc binding*/
 	at91_boot_soc.ioremap_registers();
 
-	/* temporary until have the pmc binding */
 	/* Init clock subsystem */
-	at91_clock_init(12000000);
+	at91_dt_clock_init();
 
 	/* Register the processor-specific clocks */
 	at91_boot_soc.register_clocks();
-- 
1.7.7



From plagnioj at jcrosoft.com  Fri Mar  2 14:54:07 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri,  2 Mar 2012 20:54:07 +0100
Subject: [PATCH 5/6] ARM: at91: add ram controller DT support
In-Reply-To: <20120302192844.GB21255@game.jcrosoft.org>
References: <20120302192844.GB21255@game.jcrosoft.org>
Message-ID: <1330718048-9314-5-git-send-email-plagnioj@jcrosoft.com>

We can now drop the call to ioremap_registers() as we have the binding for the
SDRAM/DDR Controller.

Drop ioremap_registers() for sam9x5 too.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 .../devicetree/bindings/arm/atmel-at91.txt         |   19 ++++++++++++++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 +++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |    5 +++
 arch/arm/mach-at91/at91sam9x5.c                    |    6 ----
 arch/arm/mach-at91/include/mach/at91sam9x5.h       |    5 ---
 arch/arm/mach-at91/setup.c                         |   27 +++++++++++++++++--
 7 files changed, 59 insertions(+), 14 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index a64f867..1f87820 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -42,3 +42,22 @@ Example:
 		compatible = "atmel,at91sam9260-rstc";
 		reg = <0xfffffd00 0x10>;
 	};
+
+RAMC SDRAM/DDR Controller required properties:
+- compatible: Should be "atmel,at91sam9260-sdramc",
+			"atmel,at91sam9g45-ddramc",
+- reg: Should contain registers location and length
+  For at91sam9263 and at91sam9g45 you must specify 2 entries.
+
+Examples:
+
+	ramc0: ramc at ffffe800 {
+		compatible = "atmel,at91sam9g45-ddramc";
+		reg = <0xffffe800 0x200>;
+	};
+
+	ramc0: ramc at ffffe400 {
+		compatible = "atmel,at91sam9g45-ddramc";
+		reg = <0xffffe400 0x200
+		       0xffffe600 0x200>;
+	};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 5414347..573ac5a 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -59,6 +59,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			ramc0: ramc at ffffea00 {
+				compatible = "atmel,at91sam9260-sdramc";
+				reg = <0xffffea00 0x200>;
+			};
+
 			pmc: pmc at fffffc00 {
 				compatible = "atmel,at91rm9200-pmc";
 				reg = <0xfffffc00 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index e2ccba5..6da07a9 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -60,6 +60,12 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			ramc0: ramc at ffffe400 {
+				compatible = "atmel,at91sam9g45-ddramc";
+				reg = <0xffffe400 0x200
+				       0xffffe600 0x200>;
+			};
+
 			pmc: pmc at fffffc00 {
 				compatible = "atmel,at91rm9200-pmc";
 				reg = <0xfffffc00 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 54e3030..09bc806 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -58,6 +58,11 @@
 				reg = <0xfffff000 0x200>;
 			};
 
+			ramc0: ramc at ffffe800 {
+				compatible = "atmel,at91sam9g45-ddramc";
+				reg = <0xffffe800 0x200>;
+			};
+
 			pmc: pmc at fffffc00 {
 				compatible = "atmel,at91rm9200-pmc";
 				reg = <0xfffffc00 0x100>;
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 0b82c34..b6831ee 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -302,11 +302,6 @@ static void __init at91sam9x5_map_io(void)
 	at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
 }
 
-static void __init at91sam9x5_ioremap_registers(void)
-{
-	at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
-}
-
 void __init at91sam9x5_initialize(void)
 {
 	at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
@@ -359,7 +354,6 @@ static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9x5_soc = {
 	.map_io = at91sam9x5_map_io,
 	.default_irq_priority = at91sam9x5_default_irq_priority,
-	.ioremap_registers = at91sam9x5_ioremap_registers,
 	.register_clocks = at91sam9x5_register_clocks,
 	.init = at91sam9x5_initialize,
 };
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index a297a77..88e43d5 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -55,11 +55,6 @@
 #define AT91SAM9X5_BASE_USART2	0xf8024000
 
 /*
- * System Peripherals
- */
-#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
-
-/*
  * Base addresses for early serial code (uncompress.h)
  */
 #define AT91_DBGU	AT91_BASE_DBGU0
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 3e48b59..f86450d 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
 	of_node_put(np);
 }
 
+static struct of_device_id ramc_ids[] = {
+	{ .compatible = "atmel,at91sam9260-sdramc" },
+	{ .compatible = "atmel,at91sam9g45-ddramc" },
+	{ /*sentinel*/ }
+};
+
+static void at91_dt_ramc(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, ramc_ids);
+	if (!np)
+		panic("unable to find compatible ram conroller node in dtb\n");
+
+	at91_ramc_base[0] = of_iomap(np, 0);
+	if (!at91_ramc_base[0])
+		panic("unable to map ramc[0] cpu registers\n");
+	/* the controller may have 2 banks */
+	at91_ramc_base[1] = of_iomap(np, 1);
+
+	of_node_put(np);
+}
+
 void __init at91_dt_initialize(void)
 {
 	at91_dt_rstc();
-
-	/* temporary until have the ramc binding*/
-	at91_boot_soc.ioremap_registers();
+	at91_dt_ramc();
 
 	/* Init clock subsystem */
 	at91_dt_clock_init();
-- 
1.7.7



From plagnioj at jcrosoft.com  Fri Mar  2 14:54:08 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri,  2 Mar 2012 20:54:08 +0100
Subject: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support
In-Reply-To: <20120302192844.GB21255@game.jcrosoft.org>
References: <20120302192844.GB21255@game.jcrosoft.org>
Message-ID: <1330718048-9314-6-git-send-email-plagnioj@jcrosoft.com>

Use a string to specific the wakeup mode to make it more readable.

Add the Real-time Clock Wake-up support too for sam9g45 and sam9x5.
Add AT91_SHDW_CPTWK0_MAX to specific the Max of the Wakeup Counter.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 .../devicetree/bindings/arm/atmel-at91.txt         |   29 +++++++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 +
 arch/arm/boot/dts/at91sam9g45.dtsi                 |    5 +
 arch/arm/boot/dts/at91sam9x5.dtsi                  |    5 +
 arch/arm/mach-at91/include/mach/at91_shdwc.h       |    4 +-
 arch/arm/mach-at91/setup.c                         |   89 ++++++++++++++++++++
 6 files changed, 136 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 1f87820..ecc81e3 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -61,3 +61,32 @@ Examples:
 		reg = <0xffffe400 0x200
 		       0xffffe600 0x200>;
 	};
+
+SHDWC Shutdown Controller
+
+required properties:
+- compatible: Should be "atmel,<chip>-shdwc".
+  <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
+- reg: Should contain registers location and length
+
+optional properties:
+- atmel,wakeup-mode: String, operation mode of the wakeup mode.
+  Supported values are: "none", "high", "low", "any".
+- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
+
+optional at91sam9260 properties:
+- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
+
+optional at91sam9rl properties:
+- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
+- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
+
+optional at91sam9x5 properties:
+- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
+
+Example:
+
+	rstc at fffffd00 {
+		compatible = "atmel,at91sam9260-rstc";
+		reg = <0xfffffd00 0x10>;
+	};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 573ac5a..62c85ac 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -74,6 +74,11 @@
 				reg = <0xfffffd00 0x10>;
 			};
 
+			shdwc at fffffd10 {
+				compatible = "atmel,at91sam9260-shdwc";
+				reg = <0xfffffd10 0x10>;
+			};
+
 			pit: timer at fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 6da07a9..e655d01 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -83,6 +83,11 @@
 			};
 
 
+			shdwc at fffffd10 {
+				compatible = "atmel,at91sam9rl-shdwc";
+				reg = <0xfffffd10 0x10>;
+			};
+
 			tcb0: timer at fff7c000 {
 				compatible = "atmel,at91rm9200-tcb";
 				reg = <0xfff7c000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 09bc806..8a68f33 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -73,6 +73,11 @@
 				reg = <0xfffffe00 0x10>;
 			};
 
+			shdwc at fffffe10 {
+				compatible = "atmel,at91sam9x5-shdwc";
+				reg = <0xfffffe10 0x10>;
+			};
+
 			pit: timer at fffffe30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffe30 0xf>;
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h
index 1d4fe82..60478ea 100644
--- a/arch/arm/mach-at91/include/mach/at91_shdwc.h
+++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h
@@ -36,9 +36,11 @@ extern void __iomem *at91_shdwc_base;
 #define			AT91_SHDW_WKMODE0_HIGH		1
 #define			AT91_SHDW_WKMODE0_LOW		2
 #define			AT91_SHDW_WKMODE0_ANYLEVEL	3
-#define		AT91_SHDW_CPTWK0	(0xf << 4)		/* Counter On Wake Up 0 */
+#define		AT91_SHDW_CPTWK0_MAX	0xf			/* Maximum Counter On Wake Up 0 */
+#define		AT91_SHDW_CPTWK0	(AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
 #define			AT91_SHDW_CPTWK0_(x)	((x) << 4)
 #define		AT91_SHDW_RTTWKEN	(1   << 16)		/* Real Time Timer Wake-up Enable */
+#define		AT91_SHDW_RTCWKEN	(1   << 17)		/* Real Time Clock Wake-up Enable */
 
 #define AT91_SHDW_SR		0x08			/* Shut Down Status Register */
 #define		AT91_SHDW_WAKEUP0	(1 <<  0)		/* Wake-up 0 Status */
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index f86450d..9206a67 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -338,10 +338,99 @@ static void at91_dt_ramc(void)
 	of_node_put(np);
 }
 
+static struct of_device_id shdwc_ids[] = {
+	{ .compatible = "atmel,at91sam9260-shdwc", },
+	{ .compatible = "atmel,at91sam9rl-shdwc", },
+	{ .compatible = "atmel,at91sam9x5-shdwc", },
+	{ /*sentinel*/ }
+};
+
+static const char *shdwc_wakeup_modes[] = {
+	[AT91_SHDW_WKMODE0_NONE]	= "none",
+	[AT91_SHDW_WKMODE0_HIGH]	= "high",
+	[AT91_SHDW_WKMODE0_LOW]		= "low",
+	[AT91_SHDW_WKMODE0_ANYLEVEL]	= "any",
+};
+
+const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
+{
+	const char *pm;
+	int err, i;
+
+	err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
+	if (err < 0)
+		return AT91_SHDW_WKMODE0_ANYLEVEL;
+
+	for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
+		if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
+			return i;
+
+	return -ENODEV;
+}
+
+static void at91_dt_shdwc(void)
+{
+	struct device_node *np;
+	int wakeup_mode;
+	bool have_rtt, have_rtc;
+	u32 reg;
+	u32 mode = 0;
+
+	np = of_find_matching_node(NULL, shdwc_ids);
+	if (!np) {
+		pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
+		return;
+	}
+
+	at91_shdwc_base = of_iomap(np, 0);
+	if (!at91_shdwc_base)
+		panic("AT91: unable to map shdwc cpu registers\n");
+
+	wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
+	if (wakeup_mode < 0) {
+		pr_warn("AT91: shdwc unknown wakeup mode\n");
+		goto end;
+	}
+
+	if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
+		if (reg > AT91_SHDW_CPTWK0_MAX) {
+			pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
+				reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
+			reg = AT91_SHDW_CPTWK0_MAX;
+		}
+		mode |= AT91_SHDW_CPTWK0_(reg);
+	}
+
+	if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
+		have_rtt = false;
+		have_rtc = true;
+	} else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
+		have_rtt = true;
+		have_rtc = true;
+	} else {
+		have_rtt = true;
+		have_rtc = false;
+	}
+
+	if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
+			mode |= AT91_SHDW_RTCWKEN;
+
+	if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
+			mode |= AT91_SHDW_RTTWKEN;
+
+	at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
+
+end:
+	pm_power_off = at91sam9_poweroff;
+
+	of_node_put(np);
+}
+
 void __init at91_dt_initialize(void)
 {
 	at91_dt_rstc();
 	at91_dt_ramc();
+	at91_dt_shdwc();
 
 	/* Init clock subsystem */
 	at91_dt_clock_init();
-- 
1.7.7



From arnd at arndb.de  Fri Mar  2 15:24:19 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 20:24:19 +0000
Subject: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support
In-Reply-To: <1330718048-9314-6-git-send-email-plagnioj@jcrosoft.com>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <1330718048-9314-6-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <201203022024.19488.arnd@arndb.de>

On Friday 02 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> +       }
> +
> +       if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
> +               have_rtt = false;
> +               have_rtc = true;
> +       } else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
> +               have_rtt = true;
> +               have_rtc = true;
> +       } else {
> +               have_rtt = true;
> +               have_rtc = false;
> +       }
> +
> +       if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
> +                       mode |= AT91_SHDW_RTCWKEN;
> +
> +       if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
> +                       mode |= AT91_SHDW_RTTWKEN;
> +
> +       at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
> +

Hi Jean-Christophe,

I don't understand why you check the specific part here. Isn't it enough to
check the property when you already mandate that they can only be present
on devices that support the specific wakeup?

If there is a good explanation for that, maybe add a code comment why it's
required.

	Arnd


From b-cousson at ti.com  Fri Mar  2 15:28:34 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Fri, 2 Mar 2012 21:28:34 +0100
Subject: [PATCH 11/12] mfd: twl4030-irq: Return twl6030_mmc_card_detect
 IRQ for board setup
In-Reply-To: <20120302192058.GP18901@atomide.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-12-git-send-email-b-cousson@ti.com>
 <20120302181522.GC13967@legolas.emea.dhcp.ti.com>
 <20120302192058.GP18901@atomide.com>
Message-ID: <4F512D72.1090002@ti.com>

Hi Tony,

On 3/2/2012 8:20 PM, Tony Lindgren wrote:
> * Felipe Balbi<balbi at ti.com>  [120302 09:43]:
>> Hi,
>>
>> On Fri, Mar 02, 2012 at 05:50:23PM +0100, Benoit Cousson wrote:
>>> Card detect IRQ from the TWL6030 used to be provided to the MMC
>>> controller code using a statically allocated IRQ scheme:
>>>
>>>    card_detect_irq = TWL6030_IRQ_BASE + MMCDETECT_INTR_OFFSET;
>>>
>>> This is no longer valid in a SPARSE_IRQ context since there is no more
>>> pre-defined TWL6030_IRQ_BASE.
>>>
>>> Return the proper card detect IRQ value in the twl6030_mmc_card_detect_config
>>> that will be called from the MMC controller.
>>>
>>> Signed-off-by: Benoit Cousson<b-cousson at ti.com>
>>> Cc: Felipe Balbi<balbi at ti.com>
>>> Cc: Tony Lindgren<tony at atomide.com>
>>> Cc: Rajendra Nayak<rnayak at ti.com>
>>
>> Reviewed-by: Felipe Balbi<balbi at ti.com>
>>
>>> ---
>>>   drivers/mfd/twl6030-irq.c |    3 ++-
>>>   1 files changed, 2 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
>>> index a1c7183..4a63de2 100644
>>> --- a/drivers/mfd/twl6030-irq.c
>>> +++ b/drivers/mfd/twl6030-irq.c
>>> @@ -308,7 +308,8 @@ int twl6030_mmc_card_detect_config(void)
>>>   									ret);
>>>   		return ret;
>>>   	}
>>> -	return 0;
>>> +
>>> +	return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
>>>   }
>>>   EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
>>
>> At some point this twl6030_mmc_card_detect_config() needs to vanish in
>> favor of a better mechanism. Maybe passing the GPIO number an requiring
>> the driver to request the GPIO, set its direction and use it as IRQ
>> line.
>>
>> the only problem would arise if we end up hooking the Card Detect pin to
>> a real IRQ line, but then we can use a flag to differentiate.
>
> I'm trying to leave out the need for this callback to pdata..
> See mmc: omap_hsmmc: Simplify init for twl6030 MMC card detect
> that does pretty much the same as Benoit's patch plus removes
> the need for the callback.

That's cool. I did that patch to still have a working MMC after my TWL 
series, and I missed your MMC series.

The patch #4 "mmc: omap_hsmmc: Simplify init for twl6030 MMC card 
detect" is indeed simplifying a lot that IRQ mess.

I will check with that TWL series, but since you are already using the 
twl6030_irq_base it should work without any trouble.

Thanks,
Benoit


From b-cousson at ti.com  Fri Mar  2 15:33:44 2012
From: b-cousson at ti.com (Benoit Cousson)
Date: Fri, 2 Mar 2012 21:33:44 +0100
Subject: [PATCH 07/12] mfd: twl-*: Replace pr_ macros by the dev_ equivalent
 and do various cleanups
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <1330720424-30225-1-git-send-email-b-cousson@ti.com>

Since a structure device is available now, use the dev_ macros instead
of the pr_ ones.

Clean some badly formatted comments.
Remove some unused variables.
Move some variable to the place they belong.
Clean some badly wrapped lines.
Align variable definition
Add missing braces in if-then-else block.
Add blank line for better readability.
Move stuff here and there...

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
---
 drivers/mfd/twl-core.c    |   32 ++++++++++++++++++--------------
 drivers/mfd/twl4030-irq.c |   23 +++++++++++------------
 drivers/mfd/twl6030-irq.c |   39 +++++++++++++++++++--------------------
 3 files changed, 48 insertions(+), 46 deletions(-)

diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 1c1b7d1..9bf14ef 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -1174,17 +1174,15 @@ static int twl_remove(struct i2c_client *client)
 	return 0;
 }
 
-/* NOTE:  this driver only handles a single twl4030/tps659x0 chip */
+/* NOTE: This driver only handles a single twl4030/tps659x0 chip */
 static int __devinit
 twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 {
-	int				irq_base;
-	int				status;
-	unsigned			i;
 	struct twl4030_platform_data	*pdata = client->dev.platform_data;
 	struct device_node		*node = client->dev.of_node;
-	u8 temp;
-	int ret = 0;
+	int				irq_base = 0;
+	int				status;
+	unsigned			i;
 
 	if (node && !pdata) {
 		/*
@@ -1214,12 +1212,12 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 	}
 
 	for (i = 0; i < TWL_NUM_SLAVES; i++) {
-		struct twl_client	*twl = &twl_modules[i];
+		struct twl_client *twl = &twl_modules[i];
 
 		twl->address = client->addr + i;
-		if (i == 0)
+		if (i == 0) {
 			twl->client = client;
-		else {
+		} else {
 			twl->client = i2c_new_dummy(client->adapter,
 					twl->address);
 			if (!twl->client) {
@@ -1231,7 +1229,9 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		}
 		mutex_init(&twl->xfer_lock);
 	}
+
 	inuse = true;
+
 	if ((id->driver_data) & TWL6030_CLASS) {
 		twl_id = TWL6030_CLASS_ID;
 		twl_map = &twl6030_map[0];
@@ -1245,8 +1245,8 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 
 	/* read TWL IDCODE Register */
 	if (twl_id == TWL4030_CLASS_ID) {
-		ret = twl_read_idcode_register();
-		WARN(ret < 0, "Error: reading twl_idcode register value\n");
+		status = twl_read_idcode_register();
+		WARN(status < 0, "Error: reading twl_idcode register value\n");
 	}
 
 	/* load power event scripts */
@@ -1268,19 +1268,22 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		}
 	}
 
-	/* Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
+	/*
+	 * Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
 	 * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
 	 * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
 	 */
-
 	if (twl_class_is_4030()) {
+		u8 temp;
+
 		twl_i2c_read_u8(TWL4030_MODULE_INTBR, &temp, REG_GPPUPDCTR1);
 		temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
-		I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
+			I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
 		twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
 	}
 
 	status = -ENODEV;
+
 	if (node)
 		status = of_platform_populate(node, NULL, NULL, &client->dev);
 	if (status)
@@ -1289,6 +1292,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 fail:
 	if (status < 0)
 		twl_remove(client);
+
 	return status;
 }
 
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index e6dc8f9..e523499 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -32,7 +32,6 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/slab.h>
-
 #include <linux/of.h>
 #include <linux/irqdomain.h>
 #include <linux/i2c/twl.h>
@@ -625,7 +624,8 @@ static irqreturn_t handle_twl4030_sih(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
-/* returns the first IRQ used by this SIH bank,
+/*
+ * returns the first IRQ used by this SIH bank,
  * or negative errno
  */
 int twl4030_sih_setup(struct device *dev, int module, int irq_base)
@@ -637,14 +637,14 @@ int twl4030_sih_setup(struct device *dev, int module, int irq_base)
 	int			status = -EINVAL;
 
 	/* only support modules with standard clear-on-read for now */
-	for (sih_mod = 0, sih = sih_modules;
-			sih_mod < nr_sih_modules;
+	for (sih_mod = 0, sih = sih_modules; sih_mod < nr_sih_modules;
 			sih_mod++, sih++) {
 		if (sih->module == module && sih->set_cor) {
 			status = 0;
 			break;
 		}
 	}
+
 	if (status < 0)
 		return status;
 
@@ -674,7 +674,7 @@ int twl4030_sih_setup(struct device *dev, int module, int irq_base)
 	status = request_threaded_irq(irq, NULL, handle_twl4030_sih, 0,
 				      agent->irq_name ?: sih->name, NULL);
 
-	pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
+	dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name,
 			irq, irq_base, irq_base + i - 1);
 
 	return status < 0 ? status : irq_base;
@@ -691,12 +691,10 @@ int twl4030_sih_setup(struct device *dev, int module, int irq_base)
 int twl4030_init_irq(struct device *dev, int irq_num)
 {
 	static struct irq_chip	twl4030_irq_chip;
+	int			status, i;
 	int			irq_base, irq_end, nr_irqs;
 	struct			device_node *node = dev->of_node;
 
-	int			status;
-	int			i;
-
 	/*
 	 * TWL core and pwr interrupts must be contiguous because
 	 * the hwirqs numbers are defined contiguously from 1 to 15.
@@ -725,7 +723,8 @@ int twl4030_init_irq(struct device *dev, int irq_num)
 
 	twl4030_irq_base = irq_base;
 
-	/* install an irq handler for each of the SIH modules;
+	/*
+	 * Install an irq handler for each of the SIH modules;
 	 * clone dummy irq_chip since PIH can't *do* anything
 	 */
 	twl4030_irq_chip = dummy_irq_chip;
@@ -740,13 +739,13 @@ int twl4030_init_irq(struct device *dev, int irq_num)
 		activate_irq(i);
 	}
 
-	pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
+	dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH",
 			irq_num, irq_base, irq_end);
 
 	/* ... and the PWR_INT module ... */
 	status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
 	if (status < 0) {
-		pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
+		dev_err(dev, "sih_setup PWR INT --> %d\n", status);
 		goto fail;
 	}
 
@@ -755,7 +754,7 @@ int twl4030_init_irq(struct device *dev, int irq_num)
 				      IRQF_ONESHOT,
 				      "TWL4030-PIH", NULL);
 	if (status < 0) {
-		pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status);
+		dev_err(dev, "could not claim irq%d: %d\n", irq_num, status);
 		goto fail_rqirq;
 	}
 
diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
index b4d5e0e..a1c7183 100644
--- a/drivers/mfd/twl6030-irq.c
+++ b/drivers/mfd/twl6030-irq.c
@@ -53,7 +53,6 @@
  *
  * We set up IRQs starting at a platform-specified base. An interrupt map table,
  * specifies mapping between interrupt number and the associated module.
- *
  */
 #define TWL6030_NR_IRQS    20
 
@@ -342,14 +341,11 @@ int twl6030_init_irq(struct device *dev, int irq_num)
 {
 	struct			device_node *node = dev->of_node;
 	int			nr_irqs, irq_base, irq_end;
-
-	int	status = 0;
-	int	i;
 	struct task_struct	*task;
-	int ret;
-	u8 mask[4];
-
-	static struct irq_chip	twl6030_irq_chip;
+	static struct irq_chip  twl6030_irq_chip;
+	int			status = 0;
+	int			i;
+	u8			mask[4];
 
 	nr_irqs = TWL6030_NR_IRQS;
 
@@ -367,16 +363,18 @@ int twl6030_init_irq(struct device *dev, int irq_num)
 	mask[1] = 0xFF;
 	mask[2] = 0xFF;
 	mask[3] = 0xFF;
-	ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
-			REG_INT_MSK_LINE_A, 3); /* MASK ALL INT LINES */
-	ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
-			REG_INT_MSK_STS_A, 3); /* MASK ALL INT STS */
-	ret = twl_i2c_write(TWL_MODULE_PIH, &mask[0],
-			REG_INT_STS_A, 3); /* clear INT_STS_A,B,C */
+
+	/* mask all int lines */
+	twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
+	/* mask all int sts */
+	twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
+	/* clear INT_STS_A,B,C */
+	twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
 
 	twl6030_irq_base = irq_base;
 
-	/* install an irq handler for each of the modules;
+	/*
+	 * install an irq handler for each of the modules;
 	 * clone dummy irq_chip since PIH can't *do* anything
 	 */
 	twl6030_irq_chip = dummy_irq_chip;
@@ -391,22 +389,22 @@ int twl6030_init_irq(struct device *dev, int irq_num)
 		activate_irq(i);
 	}
 
-	pr_info("twl6030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
+	dev_info(dev, "PIH (irq %d) chaining IRQs %d..%d\n",
 			irq_num, irq_base, irq_end);
 
 	/* install an irq handler to demultiplex the TWL6030 interrupt */
 	init_completion(&irq_event);
 
-	status = request_irq(irq_num, handle_twl6030_pih, 0,
-				"TWL6030-PIH", &irq_event);
+	status = request_irq(irq_num, handle_twl6030_pih, 0, "TWL6030-PIH",
+			     &irq_event);
 	if (status < 0) {
-		pr_err("twl6030: could not claim irq%d: %d\n", irq_num, status);
+		dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
 		goto fail_irq;
 	}
 
 	task = kthread_run(twl6030_irq_thread, (void *)irq_num, "twl6030-irq");
 	if (IS_ERR(task)) {
-		pr_err("twl6030: could not create irq %d thread!\n", irq_num);
+		dev_err(dev, "could not create irq %d thread!\n", irq_num);
 		status = PTR_ERR(task);
 		goto fail_kthread;
 	}
@@ -421,6 +419,7 @@ fail_kthread:
 fail_irq:
 	for (i = irq_base; i < irq_end; i++)
 		irq_set_chip_and_handler(i, NULL, NULL);
+
 	return status;
 }
 
-- 
1.7.0.4



From arnd at arndb.de  Fri Mar  2 15:35:44 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 20:35:44 +0000
Subject: [PULL REQUEST v2] ARM: kirkwood: fdt: convert kirkwood init funcs
 to fdt
In-Reply-To: <20120302200034.GQ11986@titan.lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <201203021832.34901.arnd@arndb.de>
 <20120302200034.GQ11986@titan.lakedaemon.net>
Message-ID: <201203022035.44672.arnd@arndb.de>

On Friday 02 March 2012, Jason wrote:
> The following changes since commit 759a45185ac0e4dfaf8bbfcb390ec73aca4b7a34:
> 
>   ARM: kirkwood: convert uart0 to devicetree. (2012-02-27 16:21:44 +0000)
> 
> are available in the git repository at:
>   git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_test
> 

Applied to next/dt branch.

Thanks,

	Arnd


From cjb at laptop.org  Fri Mar  2 15:40:05 2012
From: cjb at laptop.org (Chris Ball)
Date: Fri, 02 Mar 2012 15:40:05 -0500
Subject: [PATCH v3 0/6] mmc: sdhci-s3c: Rework platform data and add
 device tree support
In-Reply-To: <20120222125823.GA14463@sirena.org.uk> (Mark Brown's message of
 "Wed, 22 Feb 2012 12:58:23 +0000")
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>
 <003401cce730$baf979a0$30ec6ce0$%kim@samsung.com>
 <m2aa4pkq5g.fsf@bob.laptop.org> <4F3CFEED.6060206@samsung.com>
 <m239abgc32.fsf@bob.laptop.org>
 <00b901ccf08d$2fc18b50$8f44a1f0$%kim@samsung.com>
 <m2vcn0496y.fsf@bob.laptop.org> <20120222125823.GA14463@sirena.org.uk>
Message-ID: <m2ty26n3dm.fsf@bob.laptop.org>

Hi,

On Wed, Feb 22 2012, Mark Brown wrote:
> On Tue, Feb 21, 2012 at 08:17:41AM -0500, Chris Ball wrote:
>
>> Pushed to mmc-next, thanks.  (I'm expecting that you'll do the merge
>> to Linus.)
>
> I've been sending patches adding runtime PM support to this driver for a
> while with no response - are there any issues with those?

I don't have s3c hardware, so I've been waiting for a Tested-by or ACK
from someone who does -- Kukjin, any objection if I take this into
mmc-next with a plan to merge it, to provoke some testing?  Is it
possible for you to test/review the patch?

Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From b-cousson at ti.com  Fri Mar  2 15:49:25 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Fri, 2 Mar 2012 21:49:25 +0100
Subject: [PATCH 07/12] mfd: twl-*: Replace pr_ macros by the dev_
 equivalent and do various cleanups
In-Reply-To: <1330720424-30225-1-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330720424-30225-1-git-send-email-b-cousson@ti.com>
Message-ID: <4F513255.7090900@ti.com>

For people who were really impatient to get that patch #7, here is the 
reason it was rejected...

vger.kernel.org #<vger.kernel.org #5.7.1 SMTP; 550 5.7.1 Content-Policy 
reject msg: The capital Triple-X in subject is way too often associated 
with junk email, please rephrase. BF:<H 0>; S1758911Ab2CBQvf> #SMTP#

The original subject was indeed using a *double* Triple-X...
   mfd: twl-*: Change from pr_XXX to dev_XXX macros and various cleanups

Definitively too nasty for linux-omap mailing list...

I'm really glad vger.kernel.org is taking care of the ethics of the 
patches :-)

Regards,
Benoit


On 3/2/2012 9:33 PM, Benoit Cousson wrote:
> Since a structure device is available now, use the dev_ macros instead
> of the pr_ ones.
>
> Clean some badly formatted comments.
> Remove some unused variables.
> Move some variable to the place they belong.
> Clean some badly wrapped lines.
> Align variable definition
> Add missing braces in if-then-else block.
> Add blank line for better readability.
> Move stuff here and there...
>
> Signed-off-by: Benoit Cousson<b-cousson at ti.com>
> Cc: Felipe Balbi<balbi at ti.com>
> ---
>   drivers/mfd/twl-core.c    |   32 ++++++++++++++++++--------------
>   drivers/mfd/twl4030-irq.c |   23 +++++++++++------------
>   drivers/mfd/twl6030-irq.c |   39 +++++++++++++++++++--------------------
>   3 files changed, 48 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
> index 1c1b7d1..9bf14ef 100644
> --- a/drivers/mfd/twl-core.c
> +++ b/drivers/mfd/twl-core.c
> @@ -1174,17 +1174,15 @@ static int twl_remove(struct i2c_client *client)
>   	return 0;
>   }
>
> -/* NOTE:  this driver only handles a single twl4030/tps659x0 chip */
> +/* NOTE: This driver only handles a single twl4030/tps659x0 chip */
>   static int __devinit
>   twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
>   {
> -	int				irq_base;
> -	int				status;
> -	unsigned			i;
>   	struct twl4030_platform_data	*pdata = client->dev.platform_data;
>   	struct device_node		*node = client->dev.of_node;
> -	u8 temp;
> -	int ret = 0;
> +	int				irq_base = 0;
> +	int				status;
> +	unsigned			i;
>
>   	if (node&&  !pdata) {
>   		/*
> @@ -1214,12 +1212,12 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
>   	}
>
>   	for (i = 0; i<  TWL_NUM_SLAVES; i++) {
> -		struct twl_client	*twl =&twl_modules[i];
> +		struct twl_client *twl =&twl_modules[i];
>
>   		twl->address = client->addr + i;
> -		if (i == 0)
> +		if (i == 0) {
>   			twl->client = client;
> -		else {
> +		} else {
>   			twl->client = i2c_new_dummy(client->adapter,
>   					twl->address);
>   			if (!twl->client) {
> @@ -1231,7 +1229,9 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
>   		}
>   		mutex_init(&twl->xfer_lock);
>   	}
> +
>   	inuse = true;
> +
>   	if ((id->driver_data)&  TWL6030_CLASS) {
>   		twl_id = TWL6030_CLASS_ID;
>   		twl_map =&twl6030_map[0];
> @@ -1245,8 +1245,8 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
>
>   	/* read TWL IDCODE Register */
>   	if (twl_id == TWL4030_CLASS_ID) {
> -		ret = twl_read_idcode_register();
> -		WARN(ret<  0, "Error: reading twl_idcode register value\n");
> +		status = twl_read_idcode_register();
> +		WARN(status<  0, "Error: reading twl_idcode register value\n");
>   	}
>
>   	/* load power event scripts */
> @@ -1268,19 +1268,22 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
>   		}
>   	}
>
> -	/* Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
> +	/*
> +	 * Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface.
>   	 * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0,
>   	 * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0.
>   	 */
> -
>   	if (twl_class_is_4030()) {
> +		u8 temp;
> +
>   		twl_i2c_read_u8(TWL4030_MODULE_INTBR,&temp, REG_GPPUPDCTR1);
>   		temp&= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \
> -		I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
> +			I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU);
>   		twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1);
>   	}
>
>   	status = -ENODEV;
> +
>   	if (node)
>   		status = of_platform_populate(node, NULL, NULL,&client->dev);
>   	if (status)
> @@ -1289,6 +1292,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
>   fail:
>   	if (status<  0)
>   		twl_remove(client);
> +
>   	return status;
>   }
>
> diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
> index e6dc8f9..e523499 100644
> --- a/drivers/mfd/twl4030-irq.c
> +++ b/drivers/mfd/twl4030-irq.c
> @@ -32,7 +32,6 @@
>   #include<linux/interrupt.h>
>   #include<linux/irq.h>
>   #include<linux/slab.h>
> -
>   #include<linux/of.h>
>   #include<linux/irqdomain.h>
>   #include<linux/i2c/twl.h>
> @@ -625,7 +624,8 @@ static irqreturn_t handle_twl4030_sih(int irq, void *data)
>   	return IRQ_HANDLED;
>   }
>
> -/* returns the first IRQ used by this SIH bank,
> +/*
> + * returns the first IRQ used by this SIH bank,
>    * or negative errno
>    */
>   int twl4030_sih_setup(struct device *dev, int module, int irq_base)
> @@ -637,14 +637,14 @@ int twl4030_sih_setup(struct device *dev, int module, int irq_base)
>   	int			status = -EINVAL;
>
>   	/* only support modules with standard clear-on-read for now */
> -	for (sih_mod = 0, sih = sih_modules;
> -			sih_mod<  nr_sih_modules;
> +	for (sih_mod = 0, sih = sih_modules; sih_mod<  nr_sih_modules;
>   			sih_mod++, sih++) {
>   		if (sih->module == module&&  sih->set_cor) {
>   			status = 0;
>   			break;
>   		}
>   	}
> +
>   	if (status<  0)
>   		return status;
>
> @@ -674,7 +674,7 @@ int twl4030_sih_setup(struct device *dev, int module, int irq_base)
>   	status = request_threaded_irq(irq, NULL, handle_twl4030_sih, 0,
>   				      agent->irq_name ?: sih->name, NULL);
>
> -	pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
> +	dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name,
>   			irq, irq_base, irq_base + i - 1);
>
>   	return status<  0 ? status : irq_base;
> @@ -691,12 +691,10 @@ int twl4030_sih_setup(struct device *dev, int module, int irq_base)
>   int twl4030_init_irq(struct device *dev, int irq_num)
>   {
>   	static struct irq_chip	twl4030_irq_chip;
> +	int			status, i;
>   	int			irq_base, irq_end, nr_irqs;
>   	struct			device_node *node = dev->of_node;
>
> -	int			status;
> -	int			i;
> -
>   	/*
>   	 * TWL core and pwr interrupts must be contiguous because
>   	 * the hwirqs numbers are defined contiguously from 1 to 15.
> @@ -725,7 +723,8 @@ int twl4030_init_irq(struct device *dev, int irq_num)
>
>   	twl4030_irq_base = irq_base;
>
> -	/* install an irq handler for each of the SIH modules;
> +	/*
> +	 * Install an irq handler for each of the SIH modules;
>   	 * clone dummy irq_chip since PIH can't *do* anything
>   	 */
>   	twl4030_irq_chip = dummy_irq_chip;
> @@ -740,13 +739,13 @@ int twl4030_init_irq(struct device *dev, int irq_num)
>   		activate_irq(i);
>   	}
>
> -	pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
> +	dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH",
>   			irq_num, irq_base, irq_end);
>
>   	/* ... and the PWR_INT module ... */
>   	status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
>   	if (status<  0) {
> -		pr_err("twl4030: sih_setup PWR INT -->  %d\n", status);
> +		dev_err(dev, "sih_setup PWR INT -->  %d\n", status);
>   		goto fail;
>   	}
>
> @@ -755,7 +754,7 @@ int twl4030_init_irq(struct device *dev, int irq_num)
>   				      IRQF_ONESHOT,
>   				      "TWL4030-PIH", NULL);
>   	if (status<  0) {
> -		pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status);
> +		dev_err(dev, "could not claim irq%d: %d\n", irq_num, status);
>   		goto fail_rqirq;
>   	}
>
> diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
> index b4d5e0e..a1c7183 100644
> --- a/drivers/mfd/twl6030-irq.c
> +++ b/drivers/mfd/twl6030-irq.c
> @@ -53,7 +53,6 @@
>    *
>    * We set up IRQs starting at a platform-specified base. An interrupt map table,
>    * specifies mapping between interrupt number and the associated module.
> - *
>    */
>   #define TWL6030_NR_IRQS    20
>
> @@ -342,14 +341,11 @@ int twl6030_init_irq(struct device *dev, int irq_num)
>   {
>   	struct			device_node *node = dev->of_node;
>   	int			nr_irqs, irq_base, irq_end;
> -
> -	int	status = 0;
> -	int	i;
>   	struct task_struct	*task;
> -	int ret;
> -	u8 mask[4];
> -
> -	static struct irq_chip	twl6030_irq_chip;
> +	static struct irq_chip  twl6030_irq_chip;
> +	int			status = 0;
> +	int			i;
> +	u8			mask[4];
>
>   	nr_irqs = TWL6030_NR_IRQS;
>
> @@ -367,16 +363,18 @@ int twl6030_init_irq(struct device *dev, int irq_num)
>   	mask[1] = 0xFF;
>   	mask[2] = 0xFF;
>   	mask[3] = 0xFF;
> -	ret = twl_i2c_write(TWL_MODULE_PIH,&mask[0],
> -			REG_INT_MSK_LINE_A, 3); /* MASK ALL INT LINES */
> -	ret = twl_i2c_write(TWL_MODULE_PIH,&mask[0],
> -			REG_INT_MSK_STS_A, 3); /* MASK ALL INT STS */
> -	ret = twl_i2c_write(TWL_MODULE_PIH,&mask[0],
> -			REG_INT_STS_A, 3); /* clear INT_STS_A,B,C */
> +
> +	/* mask all int lines */
> +	twl_i2c_write(TWL_MODULE_PIH,&mask[0], REG_INT_MSK_LINE_A, 3);
> +	/* mask all int sts */
> +	twl_i2c_write(TWL_MODULE_PIH,&mask[0], REG_INT_MSK_STS_A, 3);
> +	/* clear INT_STS_A,B,C */
> +	twl_i2c_write(TWL_MODULE_PIH,&mask[0], REG_INT_STS_A, 3);
>
>   	twl6030_irq_base = irq_base;
>
> -	/* install an irq handler for each of the modules;
> +	/*
> +	 * install an irq handler for each of the modules;
>   	 * clone dummy irq_chip since PIH can't *do* anything
>   	 */
>   	twl6030_irq_chip = dummy_irq_chip;
> @@ -391,22 +389,22 @@ int twl6030_init_irq(struct device *dev, int irq_num)
>   		activate_irq(i);
>   	}
>
> -	pr_info("twl6030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
> +	dev_info(dev, "PIH (irq %d) chaining IRQs %d..%d\n",
>   			irq_num, irq_base, irq_end);
>
>   	/* install an irq handler to demultiplex the TWL6030 interrupt */
>   	init_completion(&irq_event);
>
> -	status = request_irq(irq_num, handle_twl6030_pih, 0,
> -				"TWL6030-PIH",&irq_event);
> +	status = request_irq(irq_num, handle_twl6030_pih, 0, "TWL6030-PIH",
> +			&irq_event);
>   	if (status<  0) {
> -		pr_err("twl6030: could not claim irq%d: %d\n", irq_num, status);
> +		dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
>   		goto fail_irq;
>   	}
>
>   	task = kthread_run(twl6030_irq_thread, (void *)irq_num, "twl6030-irq");
>   	if (IS_ERR(task)) {
> -		pr_err("twl6030: could not create irq %d thread!\n", irq_num);
> +		dev_err(dev, "could not create irq %d thread!\n", irq_num);
>   		status = PTR_ERR(task);
>   		goto fail_kthread;
>   	}
> @@ -421,6 +419,7 @@ fail_kthread:
>   fail_irq:
>   	for (i = irq_base; i<  irq_end; i++)
>   		irq_set_chip_and_handler(i, NULL, NULL);
> +
>   	return status;
>   }
>



From cjb at laptop.org  Fri Mar  2 15:50:25 2012
From: cjb at laptop.org (Chris Ball)
Date: Fri, 02 Mar 2012 15:50:25 -0500
Subject: [PATCH v6 0/2] patch set about the MXS-DMA
In-Reply-To: <CAMiH66HmV+58w36DGCt+e=ihTrYUwXf1Cur+678YX2GKcB1-jA@mail.gmail.com>
 (Huang Shijie's message of "Wed, 29 Feb 2012 08:13:15 -0500")
References: <1329373053-19494-1-git-send-email-b32955@freescale.com>
 <4F4D9725.3090100@freescale.com>
 <1330502098.3545.78.camel@sauron.fi.intel.com>
 <4F4DE0E5.8070808@freescale.com>
 <1330516974.3545.104.camel@sauron.fi.intel.com>
 <CAMiH66HmV+58w36DGCt+e=ihTrYUwXf1Cur+678YX2GKcB1-jA@mail.gmail.com>
Message-ID: <m2mx7yn2we.fsf@bob.laptop.org>

Hi,

On Wed, Feb 29 2012, Huang Shijie wrote:
>> Pushed both to l2-mtd.git tree, thanks. I am worried that it touches
>> other subsystems like dma, sound, and mmc and there are no acks for
>> those. Would be nice to get them somehow.
>
> I ever thought Vinod could accept this patch set.
>
> To Vinod & Chris:
>       Could you give the ack to the first patch?

Yes -- for the first patch:

Acked-by: Chris Ball <cjb at laptop.org>

(I think Shawn's ACK is sufficient for the second patch.)

Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From alan at signal11.us  Fri Mar  2 15:58:04 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 15:58:04 -0500
Subject: [PATCH v2 0/6] ARM: Tegra: cleanup patches from Arnd Bergmann
Message-ID: <1330721884-8495-1-git-send-email-alan@signal11.us>

Sorry for the mess yesterday....
This is V2 of Arnd's Patch series from yesterday. Hopefully this one will be
smoother.

Changes:
	* set_irq_flags() removal patch is out
	* driver-only patch has been moved to another set
	* Distribution list should be cleaner
	* Added proper sign-off
	* Select CPU_FREQ_TABLE for ARCH_TEGRA_3x_SOC as well
	* Fixed spacing on the localtimer patch
	* added linux/export.h to the export usb phy symbols patch

Arnd Bergmann (6):
  ARM: tegra: do not hide dma declarations
  ARM: tegra: select CPU_FREQ_TABLE
  ARM: tegra: build localtimer support only when needed
  ARM: tegra: work around tegra THUMB2_KERNEL bug
  ARM: tegra: USB_ULPI needs USB
  ARM: tegra: export usb phy symbols

 arch/arm/Kconfig                       |    1 +
 arch/arm/mach-tegra/Kconfig            |    3 +++
 arch/arm/mach-tegra/Makefile           |    3 ++-
 arch/arm/mach-tegra/include/mach/dma.h |    4 ----
 arch/arm/mach-tegra/usb_phy.c          |   11 +++++++++++
 5 files changed, 17 insertions(+), 5 deletions(-)



From alan at signal11.us  Fri Mar  2 15:58:23 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 15:58:23 -0500
Subject: [PATCH v2 1/6] ARM: tegra: do not hide dma declarations
Message-ID: <1330721903-8571-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The declarations are actually required for the device
definitions, and are still valid even if the dma controller
is disabled:

arch/arm/mach-tegra/devices.c:559:12: error: 'TEGRA_DMA_REQ_SEL_I2S_1' undeclared here (not in a function)
arch/arm/mach-tegra/devices.c:577:12: error: 'TEGRA_DMA_REQ_SEL_I2S2_1' undeclared here (not in a function)

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-tegra/include/mach/dma.h |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 3c93390..9077092 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -51,8 +51,6 @@
 #define TEGRA_DMA_REQ_SEL_OWR			25
 #define TEGRA_DMA_REQ_SEL_INVALID		31
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-
 struct tegra_dma_req;
 struct tegra_dma_channel;
 
@@ -151,5 +149,3 @@ void tegra_dma_free_channel(struct tegra_dma_channel *ch);
 int __init tegra_dma_init(void);
 
 #endif
-
-#endif
-- 
1.7.0.4



From alan at signal11.us  Fri Mar  2 15:58:28 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 15:58:28 -0500
Subject: [PATCH v2 2/6] ARM: tegra: select CPU_FREQ_TABLE
Message-ID: <1330721908-8633-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The tegra cpufreq implementation relies on the cpu_freq_table
code, so make sure that this is always there when needed.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-tegra/Kconfig |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 373652d..60f3e4b 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -10,6 +10,7 @@ config ARCH_TEGRA_2x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
+	select CPU_FREQ_TABLE if CPU_FREQ
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -23,6 +24,7 @@ config ARCH_TEGRA_3x_SOC
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
 	select USE_OF
+	select CPU_FREQ_TABLE if CPU_FREQ
 	help
 	  Support for NVIDIA Tegra T30 processor family, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
-- 
1.7.0.4



From alan at signal11.us  Fri Mar  2 15:58:32 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 15:58:32 -0500
Subject: [PATCH v2 3/6] ARM: tegra: build localtimer support only when needed
Message-ID: <1330721912-8694-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

It is possible to build a tegra kernel without localtimer
support, so the tegra specific parts should only be built
when that is indeed enabled.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-tegra/Makefile |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e120ff5..829066f 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -13,7 +13,8 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-tegra20-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= pinmux-tegra30-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
-obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
+obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
+obj-$(CONFIG_LOCAL_TIMERS)		+= localtimer.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_SYSTEM_DMA)		+= dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
-- 
1.7.0.4



From alan at signal11.us  Fri Mar  2 15:58:35 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 15:58:35 -0500
Subject: [PATCH v2 4/6] ARM: tegra: work around tegra THUMB2_KERNEL bug
Message-ID: <1330721915-8739-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The tegra smp code cannot currently be built for t2, so
disable that combination for now, as a workaround.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a48aecc..ea1d59b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1598,6 +1598,7 @@ config HZ
 config THUMB2_KERNEL
 	bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
 	depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
+	depends on !SMP || !ARCH_TEGRA
 	select AEABI
 	select ARM_ASM_UNIFIED
 	select ARM_UNWIND
-- 
1.7.0.4



From alan at signal11.us  Fri Mar  2 15:58:39 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 15:58:39 -0500
Subject: [PATCH v2 5/6] ARM: tegra: USB_ULPI needs USB
Message-ID: <1330721919-8800-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The USB_ULPI driver is selected by tegra, but can only be
built if at least one of USB or USB_GADGET is enabled.
The kernel fails to link if both are off.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-tegra/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 60f3e4b..9bb8a37 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -10,6 +10,7 @@ config ARCH_TEGRA_2x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
+	select USB_GADGET if USB_SUPPORT && !USB
 	select CPU_FREQ_TABLE if CPU_FREQ
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
-- 
1.7.0.4



From alan at signal11.us  Fri Mar  2 15:58:42 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 15:58:42 -0500
Subject: [PATCH v2 6/6] ARM: tegra: export usb phy symbols
Message-ID: <1330721922-8861-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The ehci driver can be a module, so the functions provided
by the tegra platform code used by ehci-tegra need to
be exported.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-tegra/usb_phy.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index 37576a7..6091cf3 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -22,6 +22,7 @@
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/err.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
@@ -730,6 +731,7 @@ err0:
 	kfree(phy);
 	return ERR_PTR(err);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
 
 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 {
@@ -738,6 +740,7 @@ int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 	else
 		return utmi_phy_power_on(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on);
 
 void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 {
@@ -746,18 +749,21 @@ void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 	else
 		utmi_phy_power_off(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off);
 
 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_preresume(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 
 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_postresume(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 
 void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
 				 enum tegra_usb_phy_port_speed port_speed)
@@ -765,24 +771,28 @@ void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
 	if (!phy_is_ulpi(phy))
 		utmi_phy_restore_start(phy, port_speed);
 }
+EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 
 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_restore_end(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 
 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_clk_disable(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
 
 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_clk_enable(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
 
 void tegra_usb_phy_close(struct tegra_usb_phy *phy)
 {
@@ -794,3 +804,4 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
 	clk_put(phy->pll_u);
 	kfree(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_close);
-- 
1.7.0.4



From swarren at nvidia.com  Fri Mar  2 16:04:25 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Fri, 2 Mar 2012 13:04:25 -0800
Subject: [PATCH v2 0/6] ARM: Tegra: cleanup patches from Arnd Bergmann
In-Reply-To: <1330721884-8495-1-git-send-email-alan@signal11.us>
References: <1330721884-8495-1-git-send-email-alan@signal11.us>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861A54@HQMAIL01.nvidia.com>

Alan Ott wrote at Friday, March 02, 2012 1:58 PM:
> Sorry for the mess yesterday....
> This is V2 of Arnd's Patch series from yesterday. Hopefully this one will be
> smoother.

There was feedback on at least patches 4 and 5 that doesn't appear to
have been incorporated into this updated version.

-- 
nvpublic



From zsadecki at itwatchdogs.com  Fri Mar  2 16:04:42 2012
From: zsadecki at itwatchdogs.com (Zach Sadecki)
Date: Fri, 2 Mar 2012 15:04:42 -0600
Subject: mxs auart driver problems
Message-ID: <4F5135EA.4080501@itwatchdogs.com>

I am having some problems with the mxs-auart driver in the mainline 
kernel.  If I use minicom to access the port (/dev/ttyAPP1) it seems to 
behave.  If I just send it some characters using 'echo -n " " > 
/dev/ttyAPP1'  it appears to work the first time, then if I repeat the 
same command it hangs until I kill it with ^C.

After some experimentation it seems that it only works if I'm actively 
reading characters out of it 'cat /dev/ttyAPP1' (in background or a 2nd 
terminal) and if I have turned off 'echo' using 'stty -F /dev/ttyAPP1 
-echo'.

Also, when it's in the hanging state, other ttys don't behave either 
(the AMBA serial console can't respawn the login process and I can't ssh 
into the system either).  Once I ^C the hanging 'echo' command 
immediately the console login respawns and ssh login works again.

Anybody else have this problem?  The Freescale kernel (driver with DMA) 
doesn't seem to have this issue.  Any ideas on what may be going on here?

Thanks,
   Zach


From nicolas.pitre at linaro.org  Fri Mar  2 16:15:12 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 2 Mar 2012 16:15:12 -0500 (EST)
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <20120229125826.GC2077@linaro.org>
References: <alpine.DEB.2.00.1202231714590.23091@kaball-desktop>
 <1330019314-20865-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
Message-ID: <alpine.LFD.2.02.1203021528150.31242@xanadu.home>

[ coming back from vacation and trying to catch up ]

On Wed, 29 Feb 2012, Dave Martin wrote:

> Just had a chat with some tools guys -- apparently, when passing register
> arguments to gcc inline asms there really isn't a guarantee that those
> variables will be in the expected registers on entry to the inline asm.
> 
> If gcc reorders other function calls or other code around the inline asm
> (which it can do, except under certain controlled situations), then
> intervening code can clobber any registers in general.

I'm hearing this argument about once every year or so for the last 8 
years.  I think that the tools people are getting confused between 
themselves as you may get a different interpretation of what gcc should 
do depending to whom you happen to talk to.

I did submit a bug to gcc in 2004 about this:

	http://gcc.gnu.org/bugzilla/show_bug.cgi?id=15089

You can see the confusion among gcc developers lurking there.

So let's quote the relevant gcc documentation:

-> * C Extensions::    GNU extensions to the C language family.
   -> * Explicit Reg Vars::   Defining variables residing in specified registers.

|GNU C allows you to put a few global variables into specified hardware 
|registers.  You can also specify the register in which an ordinary 
|register variable should be allocated.
|
|   * Global register variables reserve registers throughout the program.
|     This may be useful in programs such as programming language
|     interpreters which have a couple of global variables that are
|     accessed very often.
|
|   * Local register variables in specific registers do not reserve the
|     registers, except at the point where they are used as input or
|     output operands in an `asm' statement and the `asm' statement
|     itself is not deleted.  The compiler's data flow analysis is
|     capable of determining where the specified registers contain live
|     values, and where they are available for other uses.  Stores into
|     local register variables may be deleted when they appear to be
|     dead according to dataflow analysis.  References to local register
|     variables may be deleted or moved or simplified.
|
|     These local variables are sometimes convenient for use with the
|     extended `asm' feature (*note Extended Asm::), if you want to
|     write one output of the assembler instruction directly into a
|     particular register.  (This will work provided the register you
|     specify fits the constraints specified for that operand in the
|     `asm'.)

      -> * Local Reg Vars::

[...]

| Defining such a register variable does not reserve the register; it 
|remains available for other uses in places where flow control 
|determines the variable's value is not live.
|
| This option does not guarantee that GCC will generate code that has
|this variable in the register you specify at all times.  You may not
|code an explicit reference to this register in the _assembler
|instruction template_ part of an `asm' statement and assume it will
|always refer to this variable.  However, using the variable as an `asm'
|_operand_ guarantees that the specified register is used for the
|operand.

So, to me, the gcc documentation is perfectly clear on this topic.  
there really _is_ a guarantee that those asm marked variables will be in 
the expected registers on entry to the inline asm, given that the 
variable is _also_ listed as an operand to the asm statement.  But only 
in that case.

It is true that gcc may reorder other function calls or other code 
around the inline asm and then intervening code can clobber any 
registers.  Then it is up to gcc to preserve the variable's content 
elsewhere when its register is used for other purposes, and restore it 
when some inline asm statement is referring to it.

And if gcc does not do this then it is buggy.  Version 3.4.0 of gcc was 
buggy.  No other gcc versions in the last 7 years had such a problem or 
the __asmeq macro in the kernel would have told us.

> Or, to summarise another way, there is no way to control which register
> is used to pass something to an inline asm in general (often we get away
> with this, and there are a lot of inline asms in the kernel that assume
> it works, but the more you inline the more likely you are to get nasty
> surprises). 

This statement is therefore unfounded and wrong.  Please direct the 
tools guy who mislead you to the above gcc documentation.


Nicolas


From arnd at arndb.de  Fri Mar  2 16:18:05 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 21:18:05 +0000
Subject: [PULL REQUEST v2] ARM: kirkwood: fdt: convert kirkwood init funcs
 to fdt
In-Reply-To: <201203022035.44672.arnd@arndb.de>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <20120302200034.GQ11986@titan.lakedaemon.net>
 <201203022035.44672.arnd@arndb.de>
Message-ID: <201203022118.05796.arnd@arndb.de>

On Friday 02 March 2012, Arnd Bergmann wrote:
> On Friday 02 March 2012, Jason wrote:
> > The following changes since commit 759a45185ac0e4dfaf8bbfcb390ec73aca4b7a34:
> > 
> >   ARM: kirkwood: convert uart0 to devicetree. (2012-02-27 16:21:44 +0000)
> > 
> > are available in the git repository at:
> >   git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_test
> > 
> 
> Applied to next/dt branch.

On second thought, I should probably wait for the maintainer to comment
as well ;-)

Nico, does this look ok to you?

	Arnd


From nicolas.pitre at linaro.org  Fri Mar  2 16:19:35 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 2 Mar 2012 16:19:35 -0500 (EST)
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <1330526664.4270.128.camel@zakaz.uk.xensource.com>
References: <alpine.DEB.2.00.1202231714590.23091@kaball-desktop>
 <1330019314-20865-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <1330526664.4270.128.camel@zakaz.uk.xensource.com>
Message-ID: <alpine.LFD.2.02.1203021615350.31242@xanadu.home>

On Wed, 29 Feb 2012, Ian Campbell wrote:

> On Wed, 2012-02-29 at 12:58 +0000, Dave Martin wrote:
> > On Wed, Feb 29, 2012 at 09:56:02AM +0000, Ian Campbell wrote:
> > > On Wed, 2012-02-29 at 09:34 +0000, Dave Martin wrote:
> > > > On Tue, Feb 28, 2012 at 12:28:29PM +0000, Stefano Stabellini wrote:
> > > 
> > > > > I don't have a very strong opinion on which register we should use, but
> > > > > I would like to avoid r7 if it is already actively used by gcc.
> > > > 
> > > > But there is no framepointer for Thumb-2 code (?)
> > > 
> > > Peter Maydell suggested there was:
> > > > r7 is (used by gcc as) the Thumb frame pointer; I don't know if this
> > > > makes it worth avoiding in this context.
> > > 
> > > Sounds like it might be a gcc-ism, possibly a non-default option?
> > > 
> > > Anyway, I think r12 will be fine for our purposes so the point is rather
> > > moot.
> > 
> > Just had a chat with some tools guys -- apparently, when passing register
> > arguments to gcc inline asms there really isn't a guarantee that those
> > variables will be in the expected registers on entry to the inline asm.
> > 
> > If gcc reorders other function calls or other code around the inline asm
> > (which it can do, except under certain controlled situations), then
> > intervening code can clobber any registers in general.
> > 
> > Or, to summarise another way, there is no way to control which register
> > is used to pass something to an inline asm in general (often we get away
> > with this, and there are a lot of inline asms in the kernel that assume
> > it works, but the more you inline the more likely you are to get nasty
> > surprises).  There is no workaroud, except on some architectures where
> > special asm constraints allow specific individual registers to be
> > specified for operands (i386 for example).
> 
> I had assumed I just couldn't find the right syntax. Useful to know that
> I couldn't find it because it doesn't exist!

It does exist.  See my previous reply to this thread.

You can find this syntax described in section 6.44.2 "Specifying 
Registers for Local Variables" in gcc v4.6.1 (possibly another section 
number in the documentation for a different gcc version).


Nicolas


From b-cousson at ti.com  Fri Mar  2 16:38:18 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Fri, 2 Mar 2012 22:38:18 +0100
Subject: [PATCH 11/12] mfd: twl4030-irq: Return twl6030_mmc_card_detect
 IRQ for board setup
In-Reply-To: <4F512D72.1090002@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-12-git-send-email-b-cousson@ti.com>
 <20120302181522.GC13967@legolas.emea.dhcp.ti.com>
 <20120302192058.GP18901@atomide.com> <4F512D72.1090002@ti.com>
Message-ID: <4F513DCA.1070301@ti.com>

On 3/2/2012 9:28 PM, Cousson, Benoit wrote:
> Hi Tony,
>
> On 3/2/2012 8:20 PM, Tony Lindgren wrote:
>> * Felipe Balbi<balbi at ti.com> [120302 09:43]:
>>> Hi,
>>>
>>> On Fri, Mar 02, 2012 at 05:50:23PM +0100, Benoit Cousson wrote:
>>>> Card detect IRQ from the TWL6030 used to be provided to the MMC
>>>> controller code using a statically allocated IRQ scheme:
>>>>
>>>> card_detect_irq = TWL6030_IRQ_BASE + MMCDETECT_INTR_OFFSET;
>>>>
>>>> This is no longer valid in a SPARSE_IRQ context since there is no more
>>>> pre-defined TWL6030_IRQ_BASE.
>>>>
>>>> Return the proper card detect IRQ value in the
>>>> twl6030_mmc_card_detect_config
>>>> that will be called from the MMC controller.
>>>>
>>>> Signed-off-by: Benoit Cousson<b-cousson at ti.com>
>>>> Cc: Felipe Balbi<balbi at ti.com>
>>>> Cc: Tony Lindgren<tony at atomide.com>
>>>> Cc: Rajendra Nayak<rnayak at ti.com>
>>>
>>> Reviewed-by: Felipe Balbi<balbi at ti.com>
>>>
>>>> ---
>>>> drivers/mfd/twl6030-irq.c | 3 ++-
>>>> 1 files changed, 2 insertions(+), 1 deletions(-)
>>>>
>>>> diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
>>>> index a1c7183..4a63de2 100644
>>>> --- a/drivers/mfd/twl6030-irq.c
>>>> +++ b/drivers/mfd/twl6030-irq.c
>>>> @@ -308,7 +308,8 @@ int twl6030_mmc_card_detect_config(void)
>>>> ret);
>>>> return ret;
>>>> }
>>>> - return 0;
>>>> +
>>>> + return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
>>>> }
>>>> EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
>>>
>>> At some point this twl6030_mmc_card_detect_config() needs to vanish in
>>> favor of a better mechanism. Maybe passing the GPIO number an requiring
>>> the driver to request the GPIO, set its direction and use it as IRQ
>>> line.
>>>
>>> the only problem would arise if we end up hooking the Card Detect pin to
>>> a real IRQ line, but then we can use a flag to differentiate.
>>
>> I'm trying to leave out the need for this callback to pdata..
>> See mmc: omap_hsmmc: Simplify init for twl6030 MMC card detect
>> that does pretty much the same as Benoit's patch plus removes
>> the need for the callback.
>
> That's cool. I did that patch to still have a working MMC after my TWL
> series because I missed your MMC series :-(.
>
> The patch #4 "mmc: omap_hsmmc: Simplify init for twl6030 MMC card
> detect" is indeed simplifying a lot that IRQ mess.
>
> I will check with that TWL series, but since you are already using the
> twl6030_irq_base it should work without any trouble.

I created a for_3.4/twl_irq_gpio_fix branch based on irqdomain/next with 
all the TWL + GPIO patches except the DTS and without the MMC hacks.

And I merged it into your hsmmc-gpio branch. There is a small conflict 
in gpio-twl4030 but otherwise it works on the SDP4430.

I cannot test remotely with Panda or Beagle, the animals are already 
sleeping.

The branch is there if you want to check for OMAP3 as well.
git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git 
for_3.4/twl_irq_gpio_fix

Regards,
Benoit


From alan at signal11.us  Fri Mar  2 16:38:43 2012
From: alan at signal11.us (Alan Ott)
Date: Fri, 02 Mar 2012 16:38:43 -0500
Subject: [PATCH v2 0/6] ARM: Tegra: cleanup patches from Arnd Bergmann
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE861A54@HQMAIL01.nvidia.com>
References: <1330721884-8495-1-git-send-email-alan@signal11.us>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861A54@HQMAIL01.nvidia.com>
Message-ID: <4F513DE3.9020707@signal11.us>

On 03/02/2012 04:04 PM, Stephen Warren wrote:
> Alan Ott wrote at Friday, March 02, 2012 1:58 PM:
>> Sorry for the mess yesterday....
>> This is V2 of Arnd's Patch series from yesterday. Hopefully this one will be
>> smoother.
> There was feedback on at least patches 4 and 5 that doesn't appear to
> have been incorporated into this updated version.

Hi Stephen,

For patch #4 (ARM: tegra: work around tegra THUMB2_KERNEL bug) I missed
the last email in that series. I'm sorry, I'll drop this patch from v3.

For patch #5 (ARM: tegra: USB_ULPI needs USB), it didn't look to me like
there was a resolution on that thread yesterday. On reading it again, if
we change
    select USB_ULPI if USB_SUPPORT
to:
    select USB_ULPI if USB
for both Tegra 2 and 3, does that satisfy you and Arnd?

Thanks for catching these Stephen.

Alan.





From nicolas.pitre at linaro.org  Fri Mar  2 16:40:55 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 2 Mar 2012 16:40:55 -0500 (EST)
Subject: [RFC PATCH 0/2] ARM: assembler: Add uniform assembler
 framework
In-Reply-To: <20120301114942.GA2040@linaro.org>
References: <1330455586-10353-1-git-send-email-dave.martin@linaro.org>
 <20120228192458.GC3617@n2100.arm.linux.org.uk>
 <20120301114942.GA2040@linaro.org>
Message-ID: <alpine.LFD.2.02.1203021633530.31242@xanadu.home>

On Thu, 1 Mar 2012, Dave Martin wrote:

> I have a workaround for the above now, but it's not pretty -- I seem to
> have opened a can of worms here.
> 
> 
> We would need something like
> 
> #define EXTENDED_ASM(stuff) asm ( ".include \"macros.inc\"\n\t" stuff )
> #define EXTENDED_VASM(stuff) asm volatile ( ".include \"macros.inc\"\n\t" stuff )
> 
> ...where macros.inc includes some logic to protect against multiple
> inclusion.
> 
> This would avoid problems caused by reordering done by the compiler.
> 
> I think this can work, but it may be a step too far...
> 
> 
> The above could help fix the incorrect way that asm/unified.h defines
> the it* macros (though admittedly that does not seem to have caused
> problems for anyone so far...)

"If it aint broken dont fix it."

Yes, we might be making assumptions that are not guaranteed by the tools 
here, but as long as you make sure that some assumption going wrong 
won't go unnoticed and produce a broken binary then it is probably fine.

I did like your initial approach better, even if there is a risk that 
future tools might break it.  At least there was very little chances for 
the build to succeed if the global asm macros are not defined early 
enough.


Nicolas


From nicolas.pitre at linaro.org  Fri Mar  2 16:42:36 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 2 Mar 2012 16:42:36 -0500 (EST)
Subject: [RFC PATCH 0/2] ARM: assembler: Add uniform assembler
 framework
In-Reply-To: <20120301130051.GE7363@n2100.arm.linux.org.uk>
References: <1330455586-10353-1-git-send-email-dave.martin@linaro.org>
 <20120228192458.GC3617@n2100.arm.linux.org.uk>
 <20120301114942.GA2040@linaro.org>
 <20120301130051.GE7363@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.02.1203021641340.31242@xanadu.home>

On Thu, 1 Mar 2012, Russell King - ARM Linux wrote:

> On Thu, Mar 01, 2012 at 11:49:42AM +0000, Dave Martin wrote:
> > Are you still interested in this series?
> > 
> > I have a workaround for the above now, but it's not pretty -- I seem to
> > have opened a can of worms here.
> > 
> > 
> > We would need something like
> > 
> > #define EXTENDED_ASM(stuff) asm ( ".include \"macros.inc\"\n\t" stuff )
> > #define EXTENDED_VASM(stuff) asm volatile ( ".include \"macros.inc\"\n\t" stuff )
> > 
> > ...where macros.inc includes some logic to protect against multiple
> > inclusion.
> > 
> > This would avoid problems caused by reordering done by the compiler.
> > 
> > I think this can work, but it may be a step too far...
> 
> I'm fairly tempted to say: "if it ain't broke, don't fix".  AFAIK no one
> has reported problems here, so lets not hastily try to fix something that
> will error out if it does go wrong.

OK, exactly what I said.

(I should have read further down the thread before replying)


Nicolas


From swarren at nvidia.com  Fri Mar  2 16:43:23 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Fri, 2 Mar 2012 13:43:23 -0800
Subject: [PATCH v2 0/6] ARM: Tegra: cleanup patches from Arnd Bergmann
In-Reply-To: <4F513DE3.9020707@signal11.us>
References: <1330721884-8495-1-git-send-email-alan@signal11.us>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861A54@HQMAIL01.nvidia.com>
 <4F513DE3.9020707@signal11.us>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861A73@HQMAIL01.nvidia.com>

Alan Ott wrote at Friday, March 02, 2012 2:39 PM:
> On 03/02/2012 04:04 PM, Stephen Warren wrote:
> > Alan Ott wrote at Friday, March 02, 2012 1:58 PM:
> >> Sorry for the mess yesterday....
> >> This is V2 of Arnd's Patch series from yesterday. Hopefully this one will be
> >> smoother.
> > There was feedback on at least patches 4 and 5 that doesn't appear to
> > have been incorporated into this updated version.
...
> For patch #5 (ARM: tegra: USB_ULPI needs USB), it didn't look to me like
> there was a resolution on that thread yesterday. On reading it again, if
> we change
>     select USB_ULPI if USB_SUPPORT
> to:
>     select USB_ULPI if USB
> for both Tegra 2 and 3, does that satisfy you and Arnd?

I believe so yes. Thanks.

-- 
nvpublic



From tony at atomide.com  Fri Mar  2 16:44:17 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 2 Mar 2012 13:44:17 -0800
Subject: [PATCH 11/12] mfd: twl4030-irq: Return twl6030_mmc_card_detect
 IRQ for board setup
In-Reply-To: <4F513DCA.1070301@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-12-git-send-email-b-cousson@ti.com>
 <20120302181522.GC13967@legolas.emea.dhcp.ti.com>
 <20120302192058.GP18901@atomide.com> <4F512D72.1090002@ti.com>
 <4F513DCA.1070301@ti.com>
Message-ID: <20120302214416.GQ18901@atomide.com>

* Cousson, Benoit <b-cousson at ti.com> [120302 13:06]:
> 
> I created a for_3.4/twl_irq_gpio_fix branch based on irqdomain/next
> with all the TWL + GPIO patches except the DTS and without the MMC
> hacks.
> 
> And I merged it into your hsmmc-gpio branch. There is a small
> conflict in gpio-twl4030 but otherwise it works on the SDP4430.

OK cool.
 
> I cannot test remotely with Panda or Beagle, the animals are already
> sleeping.
> 
> The branch is there if you want to check for OMAP3 as well.
> git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git
> for_3.4/twl_irq_gpio_fix

I'll give it a try at some point, looks like there's few more
hsmmc fixes needed first..

Tony


From arnd at arndb.de  Fri Mar  2 17:09:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 2 Mar 2012 22:09:04 +0000
Subject: [PATCH v2 0/6] ARM: Tegra: cleanup patches from Arnd Bergmann
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE861A73@HQMAIL01.nvidia.com>
References: <1330721884-8495-1-git-send-email-alan@signal11.us>
 <4F513DE3.9020707@signal11.us>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861A73@HQMAIL01.nvidia.com>
Message-ID: <201203022209.04419.arnd@arndb.de>

On Friday 02 March 2012, Stephen Warren wrote:
> > For patch #5 (ARM: tegra: USB_ULPI needs USB), it didn't look to me like
> > there was a resolution on that thread yesterday. On reading it again, if
> > we change
> >     select USB_ULPI if USB_SUPPORT
> > to:
> >     select USB_ULPI if USB
> > for both Tegra 2 and 3, does that satisfy you and Arnd?
> 
> I believe so yes. Thanks.

Agreed.

	Arnd


From alan at signal11.us  Fri Mar  2 17:24:35 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 17:24:35 -0500
Subject: [PATCH v3 0/5] ARM: Tegra: cleanup patches from Arnd Bergmann
In-Reply-To: <1330721884-8495-1-git-send-email-alan@signal11.us>
References: <1330721884-8495-1-git-send-email-alan@signal11.us>
Message-ID: <1330727075-10974-1-git-send-email-alan@signal11.us>

Version 3 of the patch set.

Changes:
	* change of logic (and commit message change) for
	  "select USB_ULPI if USB is selected"
	* dropped THUMB2 patch

Arnd Bergmann (5):
  ARM: tegra: do not hide dma declarations
  ARM: tegra: select CPU_FREQ_TABLE
  ARM: tegra: build localtimer support only when needed
  ARM: tegra: select USB_ULPI if USB is selected
  ARM: tegra: export usb phy symbols

 arch/arm/mach-tegra/Kconfig            |    6 ++++--
 arch/arm/mach-tegra/Makefile           |    3 ++-
 arch/arm/mach-tegra/include/mach/dma.h |    4 ----
 arch/arm/mach-tegra/usb_phy.c          |   11 +++++++++++
 4 files changed, 17 insertions(+), 7 deletions(-)



From alan at signal11.us  Fri Mar  2 17:25:37 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 17:25:37 -0500
Subject: [PATCH v3 1/5] ARM: tegra: do not hide dma declarations
In-Reply-To: <1330727075-10974-1-git-send-email-alan@signal11.us>
References: <1330727075-10974-1-git-send-email-alan@signal11.us>
Message-ID: <1330727137-11052-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The declarations are actually required for the device
definitions, and are still valid even if the dma controller
is disabled:

arch/arm/mach-tegra/devices.c:559:12: error: 'TEGRA_DMA_REQ_SEL_I2S_1' undeclared here (not in a function)
arch/arm/mach-tegra/devices.c:577:12: error: 'TEGRA_DMA_REQ_SEL_I2S2_1' undeclared here (not in a function)

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-tegra/include/mach/dma.h |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 3c93390..9077092 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -51,8 +51,6 @@
 #define TEGRA_DMA_REQ_SEL_OWR			25
 #define TEGRA_DMA_REQ_SEL_INVALID		31
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-
 struct tegra_dma_req;
 struct tegra_dma_channel;
 
@@ -151,5 +149,3 @@ void tegra_dma_free_channel(struct tegra_dma_channel *ch);
 int __init tegra_dma_init(void);
 
 #endif
-
-#endif
-- 
1.7.0.4



From alan at signal11.us  Fri Mar  2 17:25:44 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 17:25:44 -0500
Subject: [PATCH v3 2/5] ARM: tegra: select CPU_FREQ_TABLE
In-Reply-To: <1330727075-10974-1-git-send-email-alan@signal11.us>
References: <1330727075-10974-1-git-send-email-alan@signal11.us>
Message-ID: <1330727144-11120-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The tegra cpufreq implementation relies on the cpu_freq_table
code, so make sure that this is always there when needed.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-tegra/Kconfig |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 373652d..60f3e4b 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -10,6 +10,7 @@ config ARCH_TEGRA_2x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
+	select CPU_FREQ_TABLE if CPU_FREQ
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -23,6 +24,7 @@ config ARCH_TEGRA_3x_SOC
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
 	select USE_OF
+	select CPU_FREQ_TABLE if CPU_FREQ
 	help
 	  Support for NVIDIA Tegra T30 processor family, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
-- 
1.7.0.4



From alan at signal11.us  Fri Mar  2 17:25:52 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 17:25:52 -0500
Subject: [PATCH v3 3/5] ARM: tegra: build localtimer support only when needed
In-Reply-To: <1330727075-10974-1-git-send-email-alan@signal11.us>
References: <1330727075-10974-1-git-send-email-alan@signal11.us>
Message-ID: <1330727152-11181-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

It is possible to build a tegra kernel without localtimer
support, so the tegra specific parts should only be built
when that is indeed enabled.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-tegra/Makefile |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e120ff5..829066f 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -13,7 +13,8 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-tegra20-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= pinmux-tegra30-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
-obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
+obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
+obj-$(CONFIG_LOCAL_TIMERS)		+= localtimer.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_SYSTEM_DMA)		+= dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
-- 
1.7.0.4



From alan at signal11.us  Fri Mar  2 17:26:00 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 17:26:00 -0500
Subject: [PATCH v3 4/5] ARM: tegra: select USB_ULPI if USB is selected
In-Reply-To: <1330727075-10974-1-git-send-email-alan@signal11.us>
References: <1330727075-10974-1-git-send-email-alan@signal11.us>
Message-ID: <1330727160-11242-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

Automatically select USB_ULPI if USB is enabled on Tegra.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-tegra/Kconfig |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 60f3e4b..fdef6b2 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -8,7 +8,7 @@ config ARCH_TEGRA_2x_SOC
 	select ARM_GIC
 	select ARCH_REQUIRE_GPIOLIB
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
-	select USB_ULPI if USB_SUPPORT
+	select USB_ULPI if USB
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
 	select CPU_FREQ_TABLE if CPU_FREQ
 	help
@@ -21,7 +21,7 @@ config ARCH_TEGRA_3x_SOC
 	select ARM_GIC
 	select ARCH_REQUIRE_GPIOLIB
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
-	select USB_ULPI if USB_SUPPORT
+	select USB_ULPI if USB
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
 	select USE_OF
 	select CPU_FREQ_TABLE if CPU_FREQ
-- 
1.7.0.4



From alan at signal11.us  Fri Mar  2 17:26:08 2012
From: alan at signal11.us (Alan Ott)
Date: Fri,  2 Mar 2012 17:26:08 -0500
Subject: [PATCH v3 5/5] ARM: tegra: export usb phy symbols
In-Reply-To: <1330727075-10974-1-git-send-email-alan@signal11.us>
References: <1330727075-10974-1-git-send-email-alan@signal11.us>
Message-ID: <1330727168-11304-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

The ehci driver can be a module, so the functions provided
by the tegra platform code used by ehci-tegra need to
be exported.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-tegra/usb_phy.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index 37576a7..6091cf3 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -22,6 +22,7 @@
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/err.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
@@ -730,6 +731,7 @@ err0:
 	kfree(phy);
 	return ERR_PTR(err);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
 
 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 {
@@ -738,6 +740,7 @@ int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 	else
 		return utmi_phy_power_on(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on);
 
 void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 {
@@ -746,18 +749,21 @@ void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 	else
 		utmi_phy_power_off(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off);
 
 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_preresume(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 
 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_postresume(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 
 void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
 				 enum tegra_usb_phy_port_speed port_speed)
@@ -765,24 +771,28 @@ void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
 	if (!phy_is_ulpi(phy))
 		utmi_phy_restore_start(phy, port_speed);
 }
+EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 
 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_restore_end(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 
 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_clk_disable(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
 
 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
 {
 	if (!phy_is_ulpi(phy))
 		utmi_phy_clk_enable(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
 
 void tegra_usb_phy_close(struct tegra_usb_phy *phy)
 {
@@ -794,3 +804,4 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
 	clk_put(phy->pll_u);
 	kfree(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_close);
-- 
1.7.0.4



From swarren at nvidia.com  Fri Mar  2 17:30:14 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Fri, 2 Mar 2012 14:30:14 -0800
Subject: [PATCH v3 0/5] ARM: Tegra: cleanup patches from Arnd Bergmann
In-Reply-To: <1330727075-10974-1-git-send-email-alan@signal11.us>
References: <1330721884-8495-1-git-send-email-alan@signal11.us>
 <1330727075-10974-1-git-send-email-alan@signal11.us>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861AAB@HQMAIL01.nvidia.com>

Alan Ott wrote at Friday, March 02, 2012 3:25 PM:
> Version 3 of the patch set.
> 
> Changes:
> 	* change of logic (and commit message change) for
> 	  "select USB_ULPI if USB is selected"
> 	* dropped THUMB2 patch
> 
> Arnd Bergmann (5):
>   ARM: tegra: do not hide dma declarations
>   ARM: tegra: select CPU_FREQ_TABLE
>   ARM: tegra: build localtimer support only when needed
>   ARM: tegra: select USB_ULPI if USB is selected
>   ARM: tegra: export usb phy symbols

The series,

Acked-by: Stephen Warren <swarren at nvidia.com>

Thanks Arnd and Alan for cleaning Tegra up!

-- 
nvpublic



From andrew at lunn.ch  Fri Mar  2 17:36:29 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Fri, 2 Mar 2012 23:36:29 +0100
Subject: [PATCH 4/4] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <20120302170252.GJ11986@titan.lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203021456.47896.arnd@arndb.de>
 <20120302153614.GG11986@titan.lakedaemon.net>
 <201203021648.52523.arnd@arndb.de>
 <20120302170252.GJ11986@titan.lakedaemon.net>
Message-ID: <20120302223629.GA21080@lunn.ch>

> > Andrew Lunn said that he has a patch for plat-orion to use the generic
> > clock framework. I think we should look at that before introducing
> > a hack that will have to be removed again very soon.
> 
> I asked him for it earlier [1], apparently it's a very invasive patch
> series which breaks things.  I would like to look at it as a reference,
> even if applying it isn't a good idea.

I did not say it breaks things. I said i have a habit of breaking
orion5x, because i cannot test it.

I will send the patches as RFC on Sunday. I'm traveling at the moment.

  Andrew


From khilman at ti.com  Fri Mar  2 17:42:01 2012
From: khilman at ti.com (Kevin Hilman)
Date: Fri,  2 Mar 2012 14:42:01 -0800
Subject: [PATCH] ARM: OMAP2+: voltage: ensure voltage used is exact voltage
 from OPP table
Message-ID: <1330728121-26664-1-git-send-email-khilman@ti.com>

When using the SMPS regulators to scale voltages, the regulator
framework may pass a minimum voltage that is not an exact OPP voltage.
For the VC/VP controlled voltage domains, we must ensure that the
voltage requested is the exact voltage from the OPP table.  This is
especially critical when using SR.

To fix, voltdm_scale() uses the target voltage passed to walk through
the OPP voltages until it finds a voltage that is >= one of the OPP
voltages.

Cc: Tero Kristo <t-kristo at ti.com>
Cc: Nishanth Menon <nm at ti.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
Unless there are any objections, this will be queued along with the
rest of the SMPS regulator series from Tero.  Currently availble in
my for_3.4/pm/smps-regulator branch at
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git

 arch/arm/mach-omap2/voltage.c |   21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 8a36342..4dc60e8 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -73,7 +73,8 @@ unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
 int voltdm_scale(struct voltagedomain *voltdm,
 		 unsigned long target_volt)
 {
-	int ret;
+	int ret, i;
+	unsigned long volt = 0;
 
 	if (!voltdm || IS_ERR(voltdm)) {
 		pr_warning("%s: VDD specified does not exist!\n", __func__);
@@ -86,9 +87,23 @@ int voltdm_scale(struct voltagedomain *voltdm,
 		return -ENODATA;
 	}
 
-	ret = voltdm->scale(voltdm, target_volt);
+	/* Adjust voltage to the exact voltage from the OPP table */
+	for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) {
+		if (voltdm->volt_data[i].volt_nominal >= target_volt) {
+			volt = voltdm->volt_data[i].volt_nominal;
+			break;
+		}
+	}
+
+	if (!volt) {
+		pr_warning("%s: not scaling. OPP voltage for %lu, not found.\n",
+			   __func__, target_volt);
+		return -EINVAL;
+	}
+
+	ret = voltdm->scale(voltdm, volt);
 	if (!ret)
-		voltdm->nominal_volt = target_volt;
+		voltdm->nominal_volt = volt;
 
 	return ret;
 }
-- 
1.7.9.2



From kgene.kim at samsung.com  Fri Mar  2 18:57:27 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 03 Mar 2012 08:57:27 +0900
Subject: [PATCH v3] ARM: S3C24XX DMA resume regression fix
In-Reply-To: <1330610031-2237-1-git-send-email-dron0gus@gmail.com>
References: <077201ccf767c6d1ec05475c40$%kim@samsung.com>
 <1330610031-2237-1-git-send-email-dron0gus@gmail.com>
Message-ID: <4F515E67.20500@samsung.com>

On 03/01/12 22:53, Gusakov Andrey wrote:
> s3c2410_dma_suspend suspends channels from 0 to dma_channels.
> s3c2410_dma_resume resumes channels in reverse order. So
> pointer should be decremented instead of being incremented.
>
> Signed-off-by: Gusakov Andrey<dron0gus at gmail.com>
> Reviewed-by: Heiko Stuebner<heiko at sntech.de>
> ---
>   arch/arm/plat-s3c24xx/dma.c |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
> index 57abec9..16510d5 100644
> --- a/arch/arm/plat-s3c24xx/dma.c
> +++ b/arch/arm/plat-s3c24xx/dma.c
> @@ -1249,7 +1249,7 @@ static void s3c2410_dma_resume(void)
>   	struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1;
>   	int channel;
>
> -	for (channel = dma_channels - 1; channel>= 0; cp++, channel--)
> +	for (channel = dma_channels - 1; channel>= 0; cp--, channel--)
>   		s3c2410_dma_resume_chan(cp);
>   }
>

Applied, thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From hartleys at visionengravers.com  Fri Mar  2 19:08:23 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Fri, 2 Mar 2012 18:08:23 -0600
Subject: ep93xx: convert vision_ep9307 to MULTI_IRQ_HANDLER
In-Reply-To: <201203011713.59663.hartleys@visionengravers.com>
References: <201203011713.59663.hartleys@visionengravers.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F001F41FF55112@AUSP01VMBX24.collaborationhost.net>

On Thursday, March 01, 2012 5:14 PM, H Hartley Sweeten wrote:
> As done for the other ep93xx machines in:
>
> commit 9a6879bd902e2ec605fff4d9fb3247b440a1f66a
> ARM: ep93xx: convert to MULTI_IRQ_HANDLER
>
> Now that there is a generic IRQ handler for multiple VIC devices use it
> for vision_ep9307 to help building multi platform kernels.
>
> Signed-off-by: Hartley Sweeten <hsweeten at visionengravers.com>
> Acked-by: Ryan Mallon <rmallon at gmail.com>
> Reviewed-by: Jamie Iles <jamie at jamieiles.com>

Arnd,

Could you merge this into linux-next?

It needs to go in when commit 9a6879bd902e2ec605fff4d9fb3247b440a1f66a
is merged into mainline. Otherwise the vision_ep9307 machine will not work.

Thanks,
Hartley

> ---
>
> diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
> index d5fb44f..d67d0b4 100644
> --- a/arch/arm/mach-ep93xx/vision_ep9307.c
> +++ b/arch/arm/mach-ep93xx/vision_ep9307.c
> @@ -34,6 +34,7 @@
>  #include <mach/ep93xx_spi.h>
>  #include <mach/gpio-ep93xx.h>
>  
> +#include <asm/hardware/vic.h>
>  #include <asm/mach-types.h>
>  #include <asm/mach/map.h>
>  #include <asm/mach/arch.h>
> @@ -361,6 +362,7 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
>  	.atag_offset	= 0x100,
>  	.map_io		= vision_map_io,
>  	.init_irq	= ep93xx_init_irq,
> +	.handle_irq	= vic_handle_irq,
>  	.timer		= &ep93xx_timer,
>  	.init_machine	= vision_init_machine,
>  	.restart	= ep93xx_restart,



From kgene.kim at samsung.com  Fri Mar  2 19:44:44 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 03 Mar 2012 09:44:44 +0900
Subject: [PATCH v3 0/6] mmc: sdhci-s3c: Rework platform data and add device
 tree support
In-Reply-To: <m2ty26n3dm.fsf@bob.laptop.org>
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>	<003401cce730$baf979a0$30ec6ce0$%kim@samsung.com>	<m2aa4pkq5g.fsf@bob.laptop.org>
 <4F3CFEED.6060206@samsung.com>	<m239abgc32.fsf@bob.laptop.org>	<00b901ccf08d$2fc18b50$8f44a1f0$%kim@samsung.com>	<m2vcn0496y.fsf@bob.laptop.org>
 <20120222125823.GA14463@sirena.org.uk> <m2ty26n3dm.fsf@bob.laptop.org>
Message-ID: <4F51697C.40408@samsung.com>

On 03/03/12 05:40, Chris Ball wrote:
> Hi,
>
> On Wed, Feb 22 2012, Mark Brown wrote:
>> On Tue, Feb 21, 2012 at 08:17:41AM -0500, Chris Ball wrote:
>>
>>> Pushed to mmc-next, thanks.  (I'm expecting that you'll do the merge
>>> to Linus.)
>>
>> I've been sending patches adding runtime PM support to this driver for a
>> while with no response - are there any issues with those?
>
> I don't have s3c hardware, so I've been waiting for a Tested-by or ACK
> from someone who does -- Kukjin, any objection if I take this into
> mmc-next with a plan to merge it, to provoke some testing?  Is it
> possible for you to test/review the patch?
>
Hi Chris,

Maybe I lost Mark's runtime PM supporting patches. I couldn't find it in 
my mail box. Sorry for that :(

Mark, could you please send it to me again?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From broonie at opensource.wolfsonmicro.com  Fri Mar  2 19:46:41 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat,  3 Mar 2012 00:46:41 +0000
Subject: [PATCH 1/2] mmc: sdhci-s3c: Use CONFIG_PM_SLEEP to ifdef system
 suspend
In-Reply-To: <4F51697C.40408@samsung.com>
References: <4F51697C.40408@samsung.com>
Message-ID: <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>

This matches current best practice as one can have runtime PM enabled
without system sleep and CONFIG_PM is defined for both.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 drivers/mmc/host/sdhci-s3c.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index ea0767e..46152d6 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -22,6 +22,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
+#include <linux/pm.h>
 
 #include <linux/mmc/host.h>
 
@@ -807,8 +808,7 @@ static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
 	return 0;
 }
 
-#ifdef CONFIG_PM
-
+#ifdef CONFIG_PM_SLEEP
 static int sdhci_s3c_suspend(struct device *dev)
 {
 	struct sdhci_host *host = dev_get_drvdata(dev);
@@ -822,10 +822,11 @@ static int sdhci_s3c_resume(struct device *dev)
 
 	return sdhci_resume_host(host);
 }
+#endif
 
+#ifdef CONFIG_PM
 static const struct dev_pm_ops sdhci_s3c_pmops = {
-	.suspend	= sdhci_s3c_suspend,
-	.resume		= sdhci_s3c_resume,
+	SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
 };
 
 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
-- 
1.7.9.1



From broonie at opensource.wolfsonmicro.com  Fri Mar  2 19:46:42 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat,  3 Mar 2012 00:46:42 +0000
Subject: [PATCH 2/2] mmc: sdhci-s3c: Enable runtime power management
In-Reply-To: <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <4F51697C.40408@samsung.com>
 <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <1330735602-22409-2-git-send-email-broonie@opensource.wolfsonmicro.com>

Since most of the work is already done by the core we just need to add
runtime suspend methods and tell the PM core that runtime PM is enabled
for this device.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 drivers/mmc/host/sdhci-s3c.c |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 46152d6..6926ac9 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -23,6 +23,7 @@
 #include <linux/of.h>
 #include <linux/of_gpio.h>
 #include <linux/pm.h>
+#include <linux/pm_runtime.h>
 
 #include <linux/mmc/host.h>
 
@@ -721,6 +722,11 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	if (pdata->host_caps2)
 		host->mmc->caps2 |= pdata->host_caps2;
 
+	pm_runtime_enable(&pdev->dev);
+	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
+	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_suspend_ignore_children(&pdev->dev, 1);
+
 	ret = sdhci_add_host(host);
 	if (ret) {
 		dev_err(dev, "sdhci_add_host() failed\n");
@@ -740,6 +746,8 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 
  err_add_host:
 	release_resource(sc->ioarea);
+	pm_runtime_forbid(&pdev->dev);
+	pm_runtime_get_noresume(&pdev->dev);
 	kfree(sc->ioarea);
 
  err_req_regs:
@@ -784,6 +792,8 @@ static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
 
 	sdhci_remove_host(host, 1);
 
+	pm_runtime_disable(&pdev->dev);
+
 	for (ptr = 0; ptr < 3; ptr++) {
 		if (sc->clk_bus[ptr]) {
 			clk_disable(sc->clk_bus[ptr]);
@@ -824,9 +834,27 @@ static int sdhci_s3c_resume(struct device *dev)
 }
 #endif
 
+#ifdef CONFIG_PM_RUNTIME
+static int sdhci_s3c_runtime_suspend(struct device *dev)
+{
+	struct sdhci_host *host = dev_get_drvdata(dev);
+
+	return sdhci_runtime_suspend_host(host);
+}
+
+static int sdhci_s3c_runtime_resume(struct device *dev)
+{
+	struct sdhci_host *host = dev_get_drvdata(dev);
+
+	return sdhci_runtime_resume_host(host);
+}
+#endif
+
 #ifdef CONFIG_PM
 static const struct dev_pm_ops sdhci_s3c_pmops = {
 	SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
+	SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
+			   NULL)
 };
 
 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
-- 
1.7.9.1



From lost.distance at yahoo.com  Fri Mar  2 20:46:43 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Sat, 3 Mar 2012 01:46:43 +0000 (GMT)
Subject: [PATCH 1/2] pxa: magician/hx4700: Convert to gpio-regulator from
 bq24022
In-Reply-To: <201203021356.38857.heiko@sntech.de>
Message-ID: <1330739203.95123.YahooMailClassic@web29010.mail.ird.yahoo.com>

Thanks Heiko.

The hx4700 patch works for me on linux-3.3-rc5.
I'm not able to test the magician patch.

Tested-by: Paul Parsons <lost.distance at yahoo.com>

--- On Fri, 2/3/12, Heiko St?bner <heiko at sntech.de> wrote:

> From: Heiko St?bner <heiko at sntech.de>
> Subject: [PATCH 1/2] pxa: magician/hx4700: Convert to gpio-regulator from bq24022
> To: "Mark Brown" <broonie at opensource.wolfsonmicro.com>, "Liam Girdwood" <lrg at ti.com>, "Philipp Zabel" <philipp.zabel at gmail.com>, "Eric Miao" <eric.y.miao at gmail.com>, "Haojian Zhuang" <haojian.zhuang at marvell.com>, "Russell King - ARM Linux" <linux at arm.linux.org.uk>
> Cc: linux-arm-kernel at lists.infradead.org, "LKML" <linux-kernel at vger.kernel.org>
> Date: Friday, 2 March, 2012, 12:56
> The bq24022 on these machines is a
> very simple regulator using gpios.
> One provides the on/off functionality and a second one is
> used to
> change the current between 100 and 500 mA.
> 
> This functionality can also be provided by the more generic
> gpio-regulator.
> 
> Therefore convert both machines which makes it possible to
> remove the
> bq24022 driver later on.
> 
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> ---
>  arch/arm/configs/magician_defconfig |? ? 2 +-
>  arch/arm/mach-pxa/hx4700.c? ? ? ?
> ? |???33
> +++++++++++++++++++++++++++------
>  arch/arm/mach-pxa/magician.c? ? ? ?
> |???33 +++++++++++++++++++++++++++------
>  3 files changed, 55 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/configs/magician_defconfig
> b/arch/arm/configs/magician_defconfig
> index 443675d..a691ef4 100644
> --- a/arch/arm/configs/magician_defconfig
> +++ b/arch/arm/configs/magician_defconfig
> @@ -101,7 +101,7 @@ CONFIG_MFD_ASIC3=y
>  CONFIG_HTC_EGPIO=y
>  CONFIG_HTC_PASIC3=y
>  CONFIG_REGULATOR=y
> -CONFIG_REGULATOR_BQ24022=y
> +CONFIG_REGULATOR_GPIO=y
>  CONFIG_FB=y
>  CONFIG_FB_PXA=y
>  CONFIG_FB_PXA_OVERLAY=y
> diff --git a/arch/arm/mach-pxa/hx4700.c
> b/arch/arm/mach-pxa/hx4700.c
> index f2c23ea..7571f0d 100644
> --- a/arch/arm/mach-pxa/hx4700.c
> +++ b/arch/arm/mach-pxa/hx4700.c
> @@ -28,7 +28,8 @@
>  #include <linux/mtd/physmap.h>
>  #include <linux/pda_power.h>
>  #include <linux/pwm_backlight.h>
> -#include <linux/regulator/bq24022.h>
> +#include <linux/regulator/driver.h>
> +#include <linux/regulator/gpio-regulator.h>
>  #include <linux/regulator/machine.h>
>  #include <linux/regulator/max1586.h>
>  #include <linux/spi/ads7846.h>
> @@ -698,14 +699,34 @@ static struct regulator_init_data
> bq24022_init_data = {
>  ??? .consumer_supplies? ? ? =
> bq24022_consumers,
>  };
>  
> -static struct bq24022_mach_info bq24022_info = {
> -??? .gpio_nce???=
> GPIO72_HX4700_BQ24022_nCHARGE_EN,
> -??? .gpio_iset2 =
> GPIO96_HX4700_BQ24022_ISET2,
> -??? .init_data? =
> &bq24022_init_data,
> +static struct gpio bq24022_gpios[] = {
> +??? { GPIO96_HX4700_BQ24022_ISET2,
> GPIOF_OUT_INIT_LOW, "bq24022_iset2" },
> +};
> +
> +static struct gpio_regulator_state bq24022_states[] = {
> +??? { .value = 100000, .gpios = (0 <<
> 0) },
> +??? { .value = 500000, .gpios = (1 <<
> 0) },
> +};
> +
> +static struct gpio_regulator_config bq24022_info = {
> +??? .supply_name = "bq24022",
> +
> +??? .enable_gpio =
> GPIO72_HX4700_BQ24022_nCHARGE_EN,
> +??? .enable_high = 0,
> +??? .enabled_at_boot = 0,
> +
> +??? .gpios = bq24022_gpios,
> +??? .nr_gpios = ARRAY_SIZE(bq24022_gpios),
> +
> +??? .states = bq24022_states,
> +??? .nr_states =
> ARRAY_SIZE(bq24022_states),
> +
> +??? .type = REGULATOR_CURRENT,
> +??? .init_data = &bq24022_init_data,
>  };
>  
>  static struct platform_device bq24022 = {
> -??? .name = "bq24022",
> +??? .name = "gpio-regulator",
>  ??? .id???= -1,
>  ??? .dev? = {
>  ??? ??? .platform_data =
> &bq24022_info,
> diff --git a/arch/arm/mach-pxa/magician.c
> b/arch/arm/mach-pxa/magician.c
> index 3d6baf9..5e26f3e 100644
> --- a/arch/arm/mach-pxa/magician.c
> +++ b/arch/arm/mach-pxa/magician.c
> @@ -25,7 +25,8 @@
>  #include <linux/mtd/physmap.h>
>  #include <linux/pda_power.h>
>  #include <linux/pwm_backlight.h>
> -#include <linux/regulator/bq24022.h>
> +#include <linux/regulator/driver.h>
> +#include <linux/regulator/gpio-regulator.h>
>  #include <linux/regulator/machine.h>
>  #include <linux/usb/gpio_vbus.h>
>  #include <linux/i2c/pxa-i2c.h>
> @@ -596,14 +597,34 @@ static struct regulator_init_data
> bq24022_init_data = {
>  ??? .consumer_supplies? ? ? =
> bq24022_consumers,
>  };
>  
> -static struct bq24022_mach_info bq24022_info = {
> -??? .gpio_nce???=
> GPIO30_MAGICIAN_BQ24022_nCHARGE_EN,
> -??? .gpio_iset2 =
> EGPIO_MAGICIAN_BQ24022_ISET2,
> -??? .init_data? =
> &bq24022_init_data,
> +static struct gpio bq24022_gpios[] = {
> +??? { EGPIO_MAGICIAN_BQ24022_ISET2,
> GPIOF_OUT_INIT_LOW, "bq24022_iset2" },
> +};
> +
> +static struct gpio_regulator_state bq24022_states[] = {
> +??? { .value = 100000, .gpios = (0 <<
> 0) },
> +??? { .value = 500000, .gpios = (1 <<
> 0) },
> +};
> +
> +static struct gpio_regulator_config bq24022_info = {
> +??? .supply_name = "bq24022",
> +
> +??? .enable_gpio =
> GPIO30_MAGICIAN_BQ24022_nCHARGE_EN,
> +??? .enable_high = 0,
> +??? .enabled_at_boot = 0,
> +
> +??? .gpios = bq24022_gpios,
> +??? .nr_gpios = ARRAY_SIZE(bq24022_gpios),
> +
> +??? .states = bq24022_states,
> +??? .nr_states =
> ARRAY_SIZE(bq24022_states),
> +
> +??? .type = REGULATOR_CURRENT,
> +??? .init_data = &bq24022_init_data,
>  };
>  
>  static struct platform_device bq24022 = {
> -??? .name = "bq24022",
> +??? .name = "gpio-regulator",
>  ??? .id???= -1,
>  ??? .dev? = {
>  ??? ??? .platform_data =
> &bq24022_info,
> -- 
> 1.7.5.4



From shijie8 at gmail.com  Fri Mar  2 20:54:05 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Sat, 3 Mar 2012 09:54:05 +0800
Subject: [PATCH v6 0/2] patch set about the MXS-DMA
In-Reply-To: <m2mx7yn2we.fsf@bob.laptop.org>
References: <1329373053-19494-1-git-send-email-b32955@freescale.com>
 <4F4D9725.3090100@freescale.com>
 <1330502098.3545.78.camel@sauron.fi.intel.com>
 <4F4DE0E5.8070808@freescale.com>
 <1330516974.3545.104.camel@sauron.fi.intel.com>
 <CAMiH66HmV+58w36DGCt+e=ihTrYUwXf1Cur+678YX2GKcB1-jA@mail.gmail.com>
 <m2mx7yn2we.fsf@bob.laptop.org>
Message-ID: <CAMiH66G54BCoMrSTqnXyJy=C8w4RqVkv_qvQosUHWj4qd+Xh=Q@mail.gmail.com>

hi,

On Sat, Mar 3, 2012 at 4:50 AM, Chris Ball <cjb at laptop.org> wrote:
> Hi,
>
> On Wed, Feb 29 2012, Huang Shijie wrote:
>>> Pushed both to l2-mtd.git tree, thanks. I am worried that it touches
>>> other subsystems like dma, sound, and mmc and there are no acks for
>>> those. Would be nice to get them somehow.
>>
>> I ever thought Vinod could accept this patch set.
>>
>> To Vinod & Chris:
>> ? ? ? Could you give the ack to the first patch?
>
> Yes -- for the first patch:
>
> Acked-by: Chris Ball <cjb at laptop.org>
>

thanks a lot.

Huang Shijie


> (I think Shawn's ACK is sufficient for the second patch.)
>
> Thanks,
>
> - Chris.
> --
> Chris Ball ? <cjb at laptop.org> ? <http://printf.net/>
> One Laptop Per Child


From arnd.bergmann at linaro.org  Fri Mar  2 21:09:51 2012
From: arnd.bergmann at linaro.org (Arnd Bergmann)
Date: Sat, 3 Mar 2012 02:09:51 +0000
Subject: [PATCH] Initial Device Tree system for Snowball
In-Reply-To: <1330703567-17925-1-git-send-email-niklas.hernaeus@stericsson.com>
References: <1330703567-17925-1-git-send-email-niklas.hernaeus@stericsson.com>
Message-ID: <201203030209.51767.arnd.bergmann@linaro.org>

On Friday 02 March 2012, Niklas Hernaeus wrote:
> 
> From: Niklas Hernaeus <niklas.hernaeus at linaro.org>
> 
> This is the base system for using Device Tree for Snowball.
> The new boardfile is a slightly modified copy of the original board file,
> so new Device Tree stuff can simply be added and code removed, while
> functionality stays the same.

I realized that this series is based on a version before Lee's patches
to add the soc information, and things have changed quite a bit with that.

I've played a bit more with this and tried to merge the two, the result
is a series in the testing/ux500/dt branch of arm-soc.git. I'm sure it's not
actually all correct, but I've tried my best there and also added quite
a bit of device tree source for illustration. Maybe the two of you can
have a look there and see what you can make of it.

	Arnd


From grant.likely at secretlab.ca  Fri Mar  2 21:39:29 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 02 Mar 2012 19:39:29 -0700
Subject: [PATCH 3/3] spi/atmel: add DT support
In-Reply-To: <1328804077-6121-3-git-send-email-plagnioj@jcrosoft.com>
References: <1328804077-6121-1-git-send-email-plagnioj@jcrosoft.com>
 <1328804077-6121-3-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120303023929.BE8F93E2D8D@localhost>

On Thu,  9 Feb 2012 17:14:37 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> the atmel_spi use only gpio for chip select
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: spi-devel-general at lists.sourceforge.net

Looks good to me; applied.

g.

> ---
>  .../devicetree/bindings/spi/spi_atmel.txt          |    6 ++++++
>  drivers/spi/spi-atmel.c                            |   12 +++++++++++-
>  2 files changed, 17 insertions(+), 1 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
> new file mode 100644
> index 0000000..7ec3d8d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
> @@ -0,0 +1,6 @@
> +Atmel SPI device
> +
> +Required properties:
> +- compatible : should be "atmel,at91rm9200-spi".
> +- reg: Address and length of the register set for the device
> +- interrupts: Should contain macb interrupt
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 16d6a83..7bcd11f 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -19,6 +19,7 @@
>  #include <linux/interrupt.h>
>  #include <linux/spi/spi.h>
>  #include <linux/slab.h>
> +#include <linux/of.h>
>  
>  #include <asm/io.h>
>  #include <mach/board.h>
> @@ -938,7 +939,7 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
>  	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
>  
>  	master->bus_num = pdev->id;
> -	master->num_chipselect = 4;
> +	master->num_chipselect = master->dev.of_node ? 0 : 4;
>  	master->setup = atmel_spi_setup;
>  	master->transfer = atmel_spi_transfer;
>  	master->cleanup = atmel_spi_cleanup;
> @@ -1064,11 +1065,20 @@ static int atmel_spi_resume(struct platform_device *pdev)
>  #define	atmel_spi_resume	NULL
>  #endif
>  
> +#if defined(CONFIG_OF)
> +static const struct of_device_id atmel_spi_dt_ids[] = {
> +	{ .compatible = "atmel,at91rm9200-spi" },
> +	{ /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
> +#endif
>  
>  static struct platform_driver atmel_spi_driver = {
>  	.driver		= {
>  		.name	= "atmel_spi",
>  		.owner	= THIS_MODULE,
> +		.of_match_table	= of_match_ptr(atmel_spi_dt_ids),
>  	},
>  	.suspend	= atmel_spi_suspend,
>  	.resume		= atmel_spi_resume,
> -- 
> 1.7.7
> 
> 
> ------------------------------------------------------------------------------
> Virtualization & Cloud Management Using Capacity Planning
> Cloud computing makes use of virtualization - but cloud computing 
> also focuses on allowing computing to be delivered as a service.
> http://www.accelacomm.com/jaw/sfnl/114/51521223/
> _______________________________________________
> spi-devel-general mailing list
> spi-devel-general at lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/spi-devel-general

-- 
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From grant.likely at secretlab.ca  Fri Mar  2 21:32:07 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 02 Mar 2012 19:32:07 -0700
Subject: [PATCH 2/3 v3] of_spi: add generic binding support to specify ncs
 gpio
In-Reply-To: <1330682587-20636-2-git-send-email-plagnioj@jcrosoft.com>
References: <1330682587-20636-1-git-send-email-plagnioj@jcrosoft.com>
 <1330682587-20636-2-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120303023207.7241E3E2D8A@localhost>

On Fri,  2 Mar 2012 11:03:06 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> This will allow to use gpio for chip select with no modification in the
> driver binding
> 
> When use the ncs-gpios, the gpio number will be passed via the controller_data
> and the number of chip select will automatically increased.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: spi-devel-general at lists.sourceforge.net
> Cc: Grant Likely <grant.likely at secretlab.ca>
> ---
> v3:
> 	use devm_kzalloc
> 
> v2:
> 	specify the gpio array at controller level
> 
> Best Regards,
> J.
>  Documentation/devicetree/bindings/spi/spi-bus.txt |    6 +++
>  drivers/spi/spi.c                                 |   49 +++++++++++++++++++-
>  include/linux/spi/spi.h                           |    5 ++
>  3 files changed, 57 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
> index e782add..5a24729 100644
> --- a/Documentation/devicetree/bindings/spi/spi-bus.txt
> +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
> @@ -12,6 +12,7 @@ The SPI master node requires the following properties:
>  - #size-cells     - should be zero.
>  - compatible      - name of SPI bus controller following generic names
>      		recommended practice.
> +- ncs-gpios       - (optional) gpios chip select.

ncs?  What does the 'n' stand for?

>  No other properties are required in the SPI bus node.  It is assumed
>  that a driver for an SPI bus device will understand that it is an SPI bus.
>  However, the binding does not attempt to define the specific method for
> @@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
>  chip selects.  Individual drivers can define additional properties to
>  support describing the chip select layout.
>  
> +If ncs-gpios is used the number of chip select will automatically increased.
> +
>  SPI slave nodes must be children of the SPI master node and can
>  contain the following properties.
>  - reg             - (required) chip select address of device.
> @@ -34,6 +37,9 @@ contain the following properties.
>  - spi-cs-high     - (optional) Empty property indicating device requires
>      		chip select active high
>  
> +If a gpio chipselect is used for the SPI slave the gpio number will be passed
> +via the controller_data
> +
>  SPI example for an MPC5200 SPI bus:
>  	spi at f00 {
>  		#address-cells = <1>;
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index e2f4ca0..f3df51f 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -28,6 +28,7 @@
>  #include <linux/mod_devicetable.h>
>  #include <linux/spi/spi.h>
>  #include <linux/of_spi.h>
> +#include <linux/of_gpio.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/export.h>
>  
> @@ -339,15 +340,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
>  int spi_add_device(struct spi_device *spi)
>  {
>  	static DEFINE_MUTEX(spi_add_lock);
> -	struct device *dev = spi->master->dev.parent;
> +	struct spi_master *master = spi->master;
> +	struct device *dev = master->dev.parent;
>  	struct device *d;
>  	int status;
>  
>  	/* Chipselects are numbered 0..max; validate. */
> -	if (spi->chip_select >= spi->master->num_chipselect) {
> +	if (spi->chip_select >= master->num_chipselect) {
>  		dev_err(dev, "cs%d >= max %d\n",
>  			spi->chip_select,
> -			spi->master->num_chipselect);
> +			master->num_chipselect);
>  		return -EINVAL;
>  	}
>  
> @@ -371,6 +373,13 @@ int spi_add_device(struct spi_device *spi)
>  		goto done;
>  	}
>  
> +	if (master->num_gpio_chipselect &&
> +	    spi->chip_select >= master->first_gpio_chipselect) {
> +		int num = spi->chip_select - master->first_gpio_chipselect;

I'd rather see an unconditional array of gpios; which only get used if a
valid gpio number is assigned.

> +
> +		spi->controller_data = (void*)master->chipselect_gpios[num];

Controller_data cannot be used here since it is provided for use
by the controller driver.

> +	}
> +
>  	/* Drivers may modify this initial i/o setup, but will
>  	 * normally rely on the device being setup.  Devices
>  	 * using SPI_CS_HIGH can't coexist well otherwise...
> @@ -562,6 +571,36 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
>  }
>  EXPORT_SYMBOL_GPL(spi_alloc_master);
>  
> +static int of_spi_register_master(struct spi_master *master)
> +{
> +	int nb, i;
> +	int *cs;
> +	struct device_node *np = master->dev.of_node;
> +
> +	if (!np)
> +		return 0;
> +
> +	nb = of_gpio_named_count(np, "ncs-gpios");
> +
> +	if (nb < 1)
> +		return 0;
> +
> +	cs = devm_kzalloc(&master->dev, sizeof(int) * nb, GFP_KERNEL);
> +	master->chipselect_gpios = cs;

the chipselect gpios functionality should be available regardless
of whether or not DT is used.  This should be moved out of the of-specific
register function.

> +
> +	if (!master->chipselect_gpios)
> +		return -ENOMEM;
> +
> +	master->first_gpio_chipselect = master->num_chipselect;
> +	master->num_chipselect += nb;
> +	master->num_gpio_chipselect = nb;
> +
> +	for (i = 0; i < nb; i++)
> +		cs[i] = of_get_named_gpio(np, "ncs-gpios", i);
> +
> +	return 0;
> +}

This function should be #ifdefed out when !OF

> +
>  /**
>   * spi_register_master - register SPI master controller
>   * @master: initialized master, originally from spi_alloc_master()
> @@ -593,6 +632,10 @@ int spi_register_master(struct spi_master *master)
>  	if (!dev)
>  		return -ENODEV;
>  
> +	status = of_spi_register_master(master);
> +	if (status)
> +		return status;
> +
>  	/* even if it's just one always-selected device, there must
>  	 * be at least one chipselect
>  	 */
> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> index 176fce9..d21c267 100644
> --- a/include/linux/spi/spi.h
> +++ b/include/linux/spi/spi.h
> @@ -318,6 +318,11 @@ struct spi_master {
>  
>  	/* called on release() to free memory provided by spi_master */
>  	void			(*cleanup)(struct spi_device *spi);
> +
> +	/* gpio chip select */
> +	int			*chipselect_gpios;
> +	int			first_gpio_chipselect;
> +	int			num_gpio_chipselect;

s/chipselect/cs/ would be quite a bit less verbose

>  };
>  
>  static inline void *spi_master_get_devdata(struct spi_master *master)
> -- 
> 1.7.7
> 

-- 
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From plagnioj at jcrosoft.com  Fri Mar  2 22:45:26 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sat, 3 Mar 2012 04:45:26 +0100
Subject: [PATCH 2/3 v3] of_spi: add generic binding support to specify
 ncs gpio
In-Reply-To: <20120303023207.7241E3E2D8A@localhost>
References: <1330682587-20636-1-git-send-email-plagnioj@jcrosoft.com>
 <1330682587-20636-2-git-send-email-plagnioj@jcrosoft.com>
 <20120303023207.7241E3E2D8A@localhost>
Message-ID: <20120303034526.GC21255@game.jcrosoft.org>

On 19:32 Fri 02 Mar     , Grant Likely wrote:
> On Fri,  2 Mar 2012 11:03:06 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > This will allow to use gpio for chip select with no modification in the
> > driver binding
> > 
> > When use the ncs-gpios, the gpio number will be passed via the controller_data
> > and the number of chip select will automatically increased.
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Cc: devicetree-discuss at lists.ozlabs.org
> > Cc: spi-devel-general at lists.sourceforge.net
> > Cc: Grant Likely <grant.likely at secretlab.ca>
> > ---
> > v3:
> > 	use devm_kzalloc
> > 
> > v2:
> > 	specify the gpio array at controller level
> > 
> > Best Regards,
> > J.
> >  Documentation/devicetree/bindings/spi/spi-bus.txt |    6 +++
> >  drivers/spi/spi.c                                 |   49 +++++++++++++++++++-
> >  include/linux/spi/spi.h                           |    5 ++
> >  3 files changed, 57 insertions(+), 3 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
> > index e782add..5a24729 100644
> > --- a/Documentation/devicetree/bindings/spi/spi-bus.txt
> > +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
> > @@ -12,6 +12,7 @@ The SPI master node requires the following properties:
> >  - #size-cells     - should be zero.
> >  - compatible      - name of SPI bus controller following generic names
> >      		recommended practice.
> > +- ncs-gpios       - (optional) gpios chip select.
> 
> ncs?  What does the 'n' stand for?
for not chipslelect will remove
> 
> >  No other properties are required in the SPI bus node.  It is assumed
> >  that a driver for an SPI bus device will understand that it is an SPI bus.
> >  However, the binding does not attempt to define the specific method for
> > @@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
> >  chip selects.  Individual drivers can define additional properties to
> >  support describing the chip select layout.
> >  
> > +If ncs-gpios is used the number of chip select will automatically increased.
> > +
> >  SPI slave nodes must be children of the SPI master node and can
> >  contain the following properties.
> >  - reg             - (required) chip select address of device.
> > @@ -34,6 +37,9 @@ contain the following properties.
> >  - spi-cs-high     - (optional) Empty property indicating device requires
> >      		chip select active high
> >  
> > +If a gpio chipselect is used for the SPI slave the gpio number will be passed
> > +via the controller_data
> > +
> >  SPI example for an MPC5200 SPI bus:
> >  	spi at f00 {
> >  		#address-cells = <1>;
> > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> > index e2f4ca0..f3df51f 100644
> > --- a/drivers/spi/spi.c
> > +++ b/drivers/spi/spi.c
> > @@ -28,6 +28,7 @@
> >  #include <linux/mod_devicetable.h>
> >  #include <linux/spi/spi.h>
> >  #include <linux/of_spi.h>
> > +#include <linux/of_gpio.h>
> >  #include <linux/pm_runtime.h>
> >  #include <linux/export.h>
> >  
> > @@ -339,15 +340,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
> >  int spi_add_device(struct spi_device *spi)
> >  {
> >  	static DEFINE_MUTEX(spi_add_lock);
> > -	struct device *dev = spi->master->dev.parent;
> > +	struct spi_master *master = spi->master;
> > +	struct device *dev = master->dev.parent;
> >  	struct device *d;
> >  	int status;
> >  
> >  	/* Chipselects are numbered 0..max; validate. */
> > -	if (spi->chip_select >= spi->master->num_chipselect) {
> > +	if (spi->chip_select >= master->num_chipselect) {
> >  		dev_err(dev, "cs%d >= max %d\n",
> >  			spi->chip_select,
> > -			spi->master->num_chipselect);
> > +			master->num_chipselect);
> >  		return -EINVAL;
> >  	}
> >  
> > @@ -371,6 +373,13 @@ int spi_add_device(struct spi_device *spi)
> >  		goto done;
> >  	}
> >  
> > +	if (master->num_gpio_chipselect &&
> > +	    spi->chip_select >= master->first_gpio_chipselect) {
> > +		int num = spi->chip_select - master->first_gpio_chipselect;
> 
> I'd rather see an unconditional array of gpios; which only get used if a
> valid gpio number is assigned.

I want to have this transparent for the driver

I don't want it to manage this. The driver just need to known it's cs-gpio
and wich one
> 
> > +
> > +		spi->controller_data = (void*)master->chipselect_gpios[num];
> 
> Controller_data cannot be used here since it is provided for use
> by the controller driver.
a new entry cs_gpio in the spi_device

> 
> > +	}
> > +
> >  	/* Drivers may modify this initial i/o setup, but will
> >  	 * normally rely on the device being setup.  Devices
> >  	 * using SPI_CS_HIGH can't coexist well otherwise...
> > @@ -562,6 +571,36 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
> >  }
> >  EXPORT_SYMBOL_GPL(spi_alloc_master);
> >  
> > +static int of_spi_register_master(struct spi_master *master)
> > +{
> > +	int nb, i;
> > +	int *cs;
> > +	struct device_node *np = master->dev.of_node;
> > +
> > +	if (!np)
> > +		return 0;
> > +
> > +	nb = of_gpio_named_count(np, "ncs-gpios");
> > +
> > +	if (nb < 1)
> > +		return 0;
> > +
> > +	cs = devm_kzalloc(&master->dev, sizeof(int) * nb, GFP_KERNEL);
> > +	master->chipselect_gpios = cs;
> 
> the chipselect gpios functionality should be available regardless
> of whether or not DT is used.  This should be moved out of the of-specific
> register function.
it's the case here it's just the management on the binding
> 
> > +
> > +	if (!master->chipselect_gpios)
> > +		return -ENOMEM;
> > +
> > +	master->first_gpio_chipselect = master->num_chipselect;
> > +	master->num_chipselect += nb;
> > +	master->num_gpio_chipselect = nb;
> > +
> > +	for (i = 0; i < nb; i++)
> > +		cs[i] = of_get_named_gpio(np, "ncs-gpios", i);
> > +
> > +	return 0;
> > +}
> 
> This function should be #ifdefed out when !OF
> 
> > +
> >  /**
> >   * spi_register_master - register SPI master controller
> >   * @master: initialized master, originally from spi_alloc_master()
> > @@ -593,6 +632,10 @@ int spi_register_master(struct spi_master *master)
> >  	if (!dev)
> >  		return -ENODEV;
> >  
> > +	status = of_spi_register_master(master);
> > +	if (status)
> > +		return status;
> > +
> >  	/* even if it's just one always-selected device, there must
> >  	 * be at least one chipselect
> >  	 */
> > diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> > index 176fce9..d21c267 100644
> > --- a/include/linux/spi/spi.h
> > +++ b/include/linux/spi/spi.h
> > @@ -318,6 +318,11 @@ struct spi_master {
> >  
> >  	/* called on release() to free memory provided by spi_master */
> >  	void			(*cleanup)(struct spi_device *spi);
> > +
> > +	/* gpio chip select */
> > +	int			*chipselect_gpios;
> > +	int			first_gpio_chipselect;
> > +	int			num_gpio_chipselect;
> 
> s/chipselect/cs/ would be quite a bit less verbose
ok
> 
> >  };
Best Regards,
J.
> >  
> >  static inline void *spi_master_get_devdata(struct spi_master *master)
> > -- 
> > 1.7.7
> > 
> 
> -- 
> email sent from notmuch.vim plugin


From plagnioj at jcrosoft.com  Fri Mar  2 22:46:34 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sat, 3 Mar 2012 04:46:34 +0100
Subject: [PATCH 3/3] spi/atmel: add DT support
In-Reply-To: <20120303023929.BE8F93E2D8D@localhost>
References: <1328804077-6121-1-git-send-email-plagnioj@jcrosoft.com>
 <1328804077-6121-3-git-send-email-plagnioj@jcrosoft.com>
 <20120303023929.BE8F93E2D8D@localhost>
Message-ID: <20120303034634.GD21255@game.jcrosoft.org>

On 19:39 Fri 02 Mar     , Grant Likely wrote:
> On Thu,  9 Feb 2012 17:14:37 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > the atmel_spi use only gpio for chip select
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Cc: devicetree-discuss at lists.ozlabs.org
> > Cc: spi-devel-general at lists.sourceforge.net
> 
> Looks good to me; applied.
please wait it's need to patch that manage the cs-gpio

will resend a new version soon

Best Regards,
J.


From plagnioj at jcrosoft.com  Sat Mar  3 01:47:25 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sat,  3 Mar 2012 07:47:25 +0100
Subject: [PATCH 1/1] mtd: ofpart Kconfig fix typo
Message-ID: <1330757245-8691-1-git-send-email-plagnioj@jcrosoft.com>

it's "default y" not "default Y"

The typo was introduced in 3.1 by
Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
since commit
d6137badeff1ef64b4e0092ec249ebdeaeb3ff37

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
Cc: stable at vger.kernel.org
---
 drivers/mtd/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 1be6218..5e78236 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -128,7 +128,7 @@ config MTD_AFS_PARTS
 
 config MTD_OF_PARTS
 	tristate "OpenFirmware partitioning information support"
-	default Y
+	default y
 	depends on OF
 	help
 	  This provides a partition parsing function which derives
-- 
1.7.7



From shijie8 at gmail.com  Sat Mar  3 15:40:32 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Sat,  3 Mar 2012 15:40:32 -0500
Subject: [PATCH] mtd/gpmi : move the __mxs_setl()/__mxs_clrl() to gpmi-lib.c
Message-ID: <1330807232-5616-1-git-send-email-shijie8@gmail.com>

We will meet the compiler error in mx6q, since there is no mxs.h header anymore.
So move these two helper functions to gpmi-lib.c.

Signed-off-by: Huang Shijie <shijie8 at gmail.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 5e3c505..9a208cb 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -21,7 +21,6 @@
 #include <linux/mtd/gpmi-nand.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
-#include <mach/mxs.h>
 
 #include "gpmi-nand.h"
 #include "gpmi-regs.h"
@@ -37,6 +36,19 @@ struct timing_threshod timing_default_threshold = {
 	.max_dll_delay_in_ns         = 16,
 };
 
+#define MXS_SET_ADDR		0x4
+#define MXS_CLR_ADDR		0x8
+
+static inline void __mxs_setl(u32 mask, void __iomem *reg)
+{
+	writel(mask, reg + MXS_SET_ADDR);
+}
+
+static inline void __mxs_clrl(u32 mask, void __iomem *reg)
+{
+	writel(mask, reg + MXS_CLR_ADDR);
+}
+
 /*
  * Clear the bit and poll it cleared.  This is usually called with
  * a reset address and mask being either SFTRST(bit 31) or CLKGATE
-- 
1.7.4



From mturquette at linaro.org  Sat Mar  3 03:28:57 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Sat,  3 Mar 2012 00:28:57 -0800
Subject: [PATCH v5 0/4] common clk framework
Message-ID: <1330763341-3437-1-git-send-email-mturquette@linaro.org>

From: Mike Turquette <mturquette at ti.com>

The common clock framework defines a common struct clk as well as an
implementation of the clk api that unifies clock operations on various
platforms and devices.

The net result is consolidation of many different struct clk definitions
and platform-specific clock framework implementations.

I consider this version merge-worthy pending ACKs from the relevant
maintainers; namely Russell, Thomas and the platform folks interested in
porting to this framework.

I would like to thank everyone who participated in the common clk
sessions at Linaro Connect and ELC; the feedback was invaluable.

Also I would like to thank Shawn Guo, Richard Zhao, Saravana Kannan and
Magnus Damm for tirelessly updating their platforms for the last few
revisions of this patch series and providng excellent feedback each
time.

Major changes since v4:
 * rolled in TGLX's comments on overall design.  We now have,
   * proper handling of root clocks and orphan clocks
   * multi-parent clocks are handled in the core
   * struct clk is shielded from struct clk_foo and vice versa
     * this is a return to the previous struct clk_hw design
 * split basic clock types out into separate files
 * split headers up by purpose
   * clk.h remains the driver-level interface
     * declarations for rate change notifiers are the only additions
   * clk-provider.h is primary header for implementing clock operations
   * clk-private.h allows for static initialization of clock data
 * validation and bug fixes
 * rebased onto Linus' v3.3-rc5 tag

Patches can be pulled from:
git://git.linaro.org/people/mturquette/linux.git v3.3-rc5-clkv5

v4 can be found at,
http://article.gmane.org/gmane.linux.linaro.devel/8896/

v3 can be found at,
http://article.gmane.org/gmane.linux.kernel/1218622

Mike Turquette (4):
  Documentation: common clk API
  clk: Kconfig: add entry for HAVE_CLK_PREPARE
  clk: introduce the common clock framework
  clk: basic clock hardware types

 Documentation/clk.txt        |  201 +++++++
 drivers/clk/Kconfig          |   31 +
 drivers/clk/Makefile         |    2 +
 drivers/clk/clk-divider.c    |  199 +++++++
 drivers/clk/clk-fixed-rate.c |   81 +++
 drivers/clk/clk-gate.c       |  121 ++++
 drivers/clk/clk-mux.c        |  114 ++++
 drivers/clk/clk.c            | 1323 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-private.h  |  192 ++++++
 include/linux/clk-provider.h |  294 ++++++++++
 include/linux/clk.h          |   68 ++-
 11 files changed, 2621 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/clk.txt
 create mode 100644 drivers/clk/clk-divider.c
 create mode 100644 drivers/clk/clk-fixed-rate.c
 create mode 100644 drivers/clk/clk-gate.c
 create mode 100644 drivers/clk/clk-mux.c
 create mode 100644 drivers/clk/clk.c
 create mode 100644 include/linux/clk-private.h
 create mode 100644 include/linux/clk-provider.h

Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Andrew Lunn <andrew at lunn.ch>

-- 
1.7.5.4



From mturquette at linaro.org  Sat Mar  3 03:28:58 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Sat,  3 Mar 2012 00:28:58 -0800
Subject: [PATCH v5 1/4] Documentation: common clk API
In-Reply-To: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
Message-ID: <1330763341-3437-2-git-send-email-mturquette@linaro.org>

Provide documentation for the common clk structures and APIs.  This code
can be found in drivers/clk/ and include/linux/clk*.h.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Mike Turquette <mturquette at ti.com>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Andrew Lunn <andrew at lunn.ch>
---
 Documentation/clk.txt |  201 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 201 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/clk.txt

diff --git a/Documentation/clk.txt b/Documentation/clk.txt
new file mode 100644
index 0000000..d4db278
--- /dev/null
+++ b/Documentation/clk.txt
@@ -0,0 +1,201 @@
+		The Common Clk Framework
+		Mike Turquette <mturquette at ti.com>
+
+This document endeavours to explain the common clk framework details,
+and how to port a platform over to this framework.  It is not yet a
+detailed explanation of the clock api in include/linux/clk.h, but
+perhaps someday it will include that information.
+
+	Part 1 - introduction and interface split
+
+The common clk framework is an interface to control the clock nodes
+available on various devices today.  This may come in the form of clock
+gating, rate adjustment, muxing or other operations.  This framework is
+enabled with the CONFIG_COMMON_CLK option.
+
+The interface itself is divided into two halves, each shielded from the
+details of its counterpart.  First is the common definition of struct
+clk which attempts to unify the framework-level accounting and
+infrastructure that has traditionally been replicated across a variety of
+platforms.  This includes a top-level implementation of the clk.h api,
+defined in drivers/clk/clk.c.  The definition of struct clk_ops, whose
+operations are invoked by the clk api implementation, rounds out the
+first half the interface.
+
+The second half of the interface is comprised of the hardware-specific callbacks
+registered with struct clk_ops and the corresponding hardware-specific
+structures needed to model a particular clock.  For the remainder of this
+document any reference to a callback in struct clk_ops, such as .enable
+or .set_rate, implies the hardware-specific implementation of that code.
+Likewise references to struct clk_foo are a convenient shorthand for the
+hypothetical implementation of the clocks in the wildly popular "foo"
+hardware.
+
+Tying the two halves of this interface together is struct clk_hw, which is
+defined in struct clk_foo and pointed to within struct clk.  This allows easy
+navigaton between the two.
+
+	Part 2 - common data structures and api
+
+Below is the common struct clk definition from include/linux/clk.h, modified for brevity:
+
+	struct clk {
+		const char		*name;
+		const struct clk_ops	*ops;
+		struct clk_hw		*hw;
+		char			**parent_names;
+		struct clk		**parents;
+		struct clk		*parent;
+		struct hlist_head	children;
+		struct hlist_node	child_node;
+		...
+	};
+
+The members above make up the core of the clk tree topology.  The clk
+api itself defines several driver-facing functions which operate on
+struct clk.  That api is documented in include/linux/clk.h.
+
+Platforms and devices utilizing the common struct clk use the struct
+clk_ops pointer in struct clk to perform the hardware-specific parts of
+the operations defined in clk.h:
+
+	struct clk_ops {
+		int		(*prepare)(struct clk_hw *hw);
+		void		(*unprepare)(struct clk_hw *hw);
+		int		(*enable)(struct clk_hw *hw);
+		void		(*disable)(struct clk_hw *hw);
+		unsigned long	(*recalc_rate)(struct clk_hw *hw,
+						unsigned long parent_rate);
+		long		(*round_rate)(struct clk_hw *hw, unsigned long,
+						unsigned long *);
+		int		(*set_parent)(struct clk_hw *hw, u8 index);
+		u8		(*get_parent)(struct clk_hw *hw);
+		int		(*set_rate)(struct clk_hw *hw, unsigned long);
+		void		(*init)(struct clk_hw *hw);
+	};
+
+	Part 3 - hardware clk implementations
+
+The strength of the common struct clk comes from its .ops and .hw pointers
+which abstract the details of struct clk from the hardware-specific bits, and
+vice versa.  To illustrate consider the simple gateable clk implementation in
+drivers/clk/clk-basic.c:
+
+struct clk_gate {
+	struct clk_hw	hw;
+	void __iomem    *reg;
+	u8              bit_idx;
+	...
+};
+
+struct clk_gate contains clk_hw as well as hardware-specific knowledge about
+which register and bit controls this clk's gating.  Nothing about clock
+topology or accounting, such as enable_count or notifier_count, is needed here.
+That is all handled by the common framework code and struct clk.
+
+Let's walk through enabling this clk from driver code:
+
+	struct clk *clk;
+	clk = clk_get(NULL, "my_gateable_clk");
+
+	clk_prepare(clk);
+	clk_enable(clk);
+
+The call graph for clk_enable is very simple:
+
+clk_enable(clk);
+	clk->ops->enable(clk->hw);
+	[which resolves to...]
+		clk_gate_enable(hw);
+		[which resolves struct clk gate with to_clk_gate(hw)]
+			clk_gate_set_bit(gate);
+
+And the definition of clk_gate_set_bit:
+
+static void clk_gate_set_bit(struct clk_gate *gate)
+{
+	u32 reg;
+
+	reg = __raw_readl(gate->reg);
+	reg |= BIT(gate->bit_idx);
+	writel(reg, gate->reg);
+}
+
+Note to_clk_gate is defined as:
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, clk)
+
+This pattern of abstraction is used for every clock hardware
+representation.
+
+	Part 4 - supporting your own clk hardware
+
+When implementing support for a new type of clock it only necessary to
+include the following header:
+
+#include <linux/clk-provider.h>
+
+include/linux/clk.h is included within that header and clk-private.h
+must never be included from the code which implements the operations for
+a clock.  More on that below in Part 5.
+
+To construct a clk hardware structure for your platform you must define
+the following:
+
+struct clk_foo {
+	struct clk_hw hw;
+	... hardware specific data goes here ...
+};
+
+To take advantage of your data you'll need to support valid operations
+for your clk:
+
+struct clk_ops clk_foo_ops {
+	.enable		= &clk_foo_enable;
+	.disable	= &clk_foo_disable;
+};
+
+Implement the above functions using container_of:
+
+#define to_clk_foo(_hw) container_of(_hw, struct clk_foo, hw)
+
+int clk_foo_enable(struct clk_hw *hw)
+{
+	struct clk_foo *foo;
+
+	foo = to_clk_foo(hw);
+
+	... perform magic on foo ...
+
+	return 0;
+};
+
+Finally, register your clock at run-time with a hardware-specific
+registration function.  This function simply populates struct clk_foo's
+data and then calls:
+
+clk_register(...)
+
+With the appropriate parameters.  See the basic clock types in
+drivers/clk/clk-*.c for examples.
+
+	Part 5 - static initialization of clock data
+
+For platforms with many clocks (often numbering into the hundreds) it
+may be desirable to statically initialize some clock data.  This
+presents a problem since the definition of struct clk should be hidden
+from everyone except for the clock core in drivers/clk/clk.c.
+
+To get around this problem struct clk's definition is exposed in
+include/linux/clk-private.h along with some macros for more easily
+initializing instances of the basic clock types.
+
+clk-private.h must NEVER be included by code which implements struct
+clk_ops callbacks, nor must it be included by any logic which pokes
+around inside of struct clk at run-time.  To do so is a layering
+violation.
+
+To better enforce this policy, always follow this simple rule: any
+statically initialized clock data MUST be defined in a separate file
+from the logic that implements its ops.  Basically separate the logic
+from the data and all is well.
-- 
1.7.5.4



From mturquette at linaro.org  Sat Mar  3 03:28:59 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Sat,  3 Mar 2012 00:28:59 -0800
Subject: [PATCH v5 2/4] clk: Kconfig: add entry for HAVE_CLK_PREPARE
In-Reply-To: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
Message-ID: <1330763341-3437-3-git-send-email-mturquette@linaro.org>

The common clk framework provides clk_prepare and clk_unprepare
implementations.  Create an entry for HAVE_CLK_PREPARE so that
COMMON_CLK can select it.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Mike Turquette <mturquette at ti.com>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Andrew Lunn <andrew at lunn.ch>
---
 drivers/clk/Kconfig |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9b3cd08..3912576 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -8,3 +8,6 @@ config HAVE_CLK_PREPARE
 
 config HAVE_MACH_CLKDEV
 	bool
+
+config HAVE_CLK_PREPARE
+	bool
-- 
1.7.5.4



From mturquette at linaro.org  Sat Mar  3 03:29:00 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Sat,  3 Mar 2012 00:29:00 -0800
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
Message-ID: <1330763341-3437-4-git-send-email-mturquette@linaro.org>

The common clock framework defines a common struct clk useful across
most platforms as well as an implementation of the clk api that drivers
can use safely for managing clocks.

The net result is consolidation of many different struct clk definitions
and platform-specific clock framework implementations.

This patch introduces the common struct clk, struct clk_ops and an
implementation of the well-known clock api in include/clk/clk.h.
Platforms may define their own hardware-specific clock structure and
their own clock operation callbacks, so long as it wraps an instance of
struct clk_hw.

See Documentation/clk.txt for more details.

This patch is based on the work of Jeremy Kerr, which in turn was based
on the work of Ben Herrenschmidt.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Mike Turquette <mturquette at ti.com>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Andrew Lunn <andrew at lunn.ch>
---
 drivers/clk/Kconfig          |   28 +
 drivers/clk/Makefile         |    1 +
 drivers/clk/clk.c            | 1323 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-private.h  |   68 +++
 include/linux/clk-provider.h |  169 ++++++
 include/linux/clk.h          |   68 ++-
 6 files changed, 1652 insertions(+), 5 deletions(-)
 create mode 100644 drivers/clk/clk.c
 create mode 100644 include/linux/clk-private.h
 create mode 100644 include/linux/clk-provider.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 3912576..18eb8c2 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -11,3 +11,31 @@ config HAVE_MACH_CLKDEV
 
 config HAVE_CLK_PREPARE
 	bool
+
+menuconfig COMMON_CLK
+	bool "Common Clock Framework"
+	select HAVE_CLK_PREPARE
+	---help---
+	  The common clock framework is a single definition of struct
+	  clk, useful across many platforms, as well as an
+	  implementation of the clock API in include/linux/clk.h.
+	  Architectures utilizing the common struct clk should select
+	  this automatically, but it may be necessary to manually select
+	  this option for loadable modules requiring the common clock
+	  framework.
+
+	  If in doubt, say "N".
+
+if COMMON_CLK
+
+config COMMON_CLK_DEBUG
+	bool "DebugFS representation of clock tree"
+	depends on COMMON_CLK
+	---help---
+	  Creates a directory hierchy in debugfs for visualizing the clk
+	  tree structure.  Each directory contains read-only members
+	  that export information specific to that clk node: clk_rate,
+	  clk_flags, clk_prepare_count, clk_enable_count &
+	  clk_notifier_count.
+
+endif
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 07613fa..ff362c4 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,2 +1,3 @@
 
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
+obj-$(CONFIG_COMMON_CLK)	+= clk.o
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
new file mode 100644
index 0000000..b979d74
--- /dev/null
+++ b/drivers/clk/clk.c
@@ -0,0 +1,1323 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
+ * Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Standard functionality for the common clock API.  See Documentation/clk.txt
+ */
+
+#include <linux/clk-private.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/slab.h>
+
+static DEFINE_SPINLOCK(enable_lock);
+static DEFINE_MUTEX(prepare_lock);
+
+static HLIST_HEAD(clk_root_list);
+static HLIST_HEAD(clk_orphan_list);
+static LIST_HEAD(clk_notifier_list);
+
+/***        debugfs support        ***/
+
+#ifdef CONFIG_COMMON_CLK_DEBUG
+#include <linux/debugfs.h>
+
+static struct dentry *rootdir;
+static struct dentry *orphandir;
+static int inited = 0;
+
+/* caller must hold prepare_lock */
+static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
+{
+	struct dentry *d;
+	int ret = -ENOMEM;
+
+	if (!clk || !pdentry) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	d = debugfs_create_dir(clk->name, pdentry);
+	if (!d)
+		goto out;
+
+	clk->dentry = d;
+
+	d = debugfs_create_u32("clk_rate", S_IRUGO, clk->dentry,
+			(u32 *)&clk->rate);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
+			(u32 *)&clk->flags);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_u32("clk_prepare_count", S_IRUGO, clk->dentry,
+			(u32 *)&clk->prepare_count);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_u32("clk_enable_count", S_IRUGO, clk->dentry,
+			(u32 *)&clk->enable_count);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_u32("clk_notifier_count", S_IRUGO, clk->dentry,
+			(u32 *)&clk->notifier_count);
+	if (!d)
+		goto err_out;
+
+	ret = 0;
+	goto out;
+
+err_out:
+	debugfs_remove(clk->dentry);
+out:
+	return ret;
+}
+
+/* caller must hold prepare_lock */
+static int clk_debug_create_subtree(struct clk *clk, struct dentry *pdentry)
+{
+	struct clk *child;
+	struct hlist_node *tmp;
+	int ret = -EINVAL;;
+
+	if (!clk || !pdentry)
+		goto out;
+
+	ret = clk_debug_create_one(clk, pdentry);
+
+	if (ret)
+		goto out;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node)
+		clk_debug_create_subtree(child, clk->dentry);
+
+	ret = 0;
+out:
+	return ret;
+}
+
+/**
+ * clk_debug_register - add a clk node to the debugfs clk tree
+ * @clk: the clk being added to the debugfs clk tree
+ *
+ * Dynamically adds a clk to the debugfs clk tree if debugfs has been
+ * initialized.  Otherwise it bails out early since the debugfs clk tree
+ * will be created lazily by clk_debug_init as part of a late_initcall.
+ *
+ * Caller must hold prepare_lock.  Only clk_init calls this function (so
+ * far) so this is taken care.
+ */
+static int clk_debug_register(struct clk *clk)
+{
+	struct clk *parent;
+	struct dentry *pdentry;
+	int ret = 0;
+
+	if (!inited)
+		goto out;
+
+	parent = clk->parent;
+
+	/*
+	 * Check to see if a clk is a root clk.  Also check that it is
+	 * safe to add this clk to debugfs
+	 */
+	if (!parent)
+		if (clk->flags & CLK_IS_ROOT)
+			pdentry = rootdir;
+		else
+			pdentry = orphandir;
+	else
+		if (parent->dentry)
+			pdentry = parent->dentry;
+		else
+			goto out;
+
+	ret = clk_debug_create_subtree(clk, pdentry);
+
+out:
+	return ret;
+}
+
+/**
+ * clk_debug_init - lazily create the debugfs clk tree visualization
+ *
+ * clks are often initialized very early during boot before memory can
+ * be dynamically allocated and well before debugfs is setup.
+ * clk_debug_init walks the clk tree hierarchy while holding
+ * prepare_lock and creates the topology as part of a late_initcall,
+ * thus insuring that clks initialized very early will still be
+ * represented in the debugfs clk tree.  This function should only be
+ * called once at boot-time, and all other clks added dynamically will
+ * be done so with clk_debug_register.
+ */
+static int __init clk_debug_init(void)
+{
+	struct clk *clk;
+	struct hlist_node *tmp;
+
+	rootdir = debugfs_create_dir("clk", NULL);
+
+	if (!rootdir)
+		return -ENOMEM;
+
+	orphandir = debugfs_create_dir("orphans", rootdir);
+
+	if (!orphandir)
+		return -ENOMEM;
+
+	mutex_lock(&prepare_lock);
+
+	hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
+		clk_debug_create_subtree(clk, rootdir);
+
+	hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
+		clk_debug_create_subtree(clk, orphandir);
+
+	inited = 1;
+
+	mutex_unlock(&prepare_lock);
+
+	return 0;
+}
+late_initcall(clk_debug_init);
+#else
+static inline int clk_debug_register(struct clk *clk) { return 0; }
+#endif /* CONFIG_COMMON_CLK_DEBUG */
+
+/***    helper functions   ***/
+
+inline const char *__clk_get_name(struct clk *clk)
+{
+	return !clk ? NULL : clk->name;
+}
+
+inline struct clk_hw *__clk_get_hw(struct clk *clk)
+{
+	return !clk ? NULL : clk->hw;
+}
+
+inline u8 __clk_get_num_parents(struct clk *clk)
+{
+	return !clk ? -EINVAL : clk->num_parents;
+}
+
+inline struct clk *__clk_get_parent(struct clk *clk)
+{
+	return !clk ? NULL : clk->parent;
+}
+
+inline unsigned long __clk_get_rate(struct clk *clk)
+{
+	return !clk ? -EINVAL : clk->rate;
+}
+
+inline unsigned long __clk_get_flags(struct clk *clk)
+{
+	return !clk ? -EINVAL : clk->flags;
+}
+
+static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
+{
+	struct clk *child;
+	struct clk *ret;
+	struct hlist_node *tmp;
+
+	if (!strcmp(clk->name, name))
+		return clk;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		ret = __clk_lookup_subtree(name, child);
+		if (ret)
+			return ret;
+	}
+
+	return NULL;
+}
+
+struct clk *__clk_lookup(const char *name)
+{
+	struct clk *root_clk;
+	struct clk *ret;
+	struct hlist_node *tmp;
+
+	/* search the 'proper' clk tree first */
+	hlist_for_each_entry(root_clk, tmp, &clk_root_list, child_node) {
+		ret = __clk_lookup_subtree(name, root_clk);
+		if (ret)
+			return ret;
+	}
+
+	/* if not found, then search the orphan tree */
+	hlist_for_each_entry(root_clk, tmp, &clk_orphan_list, child_node) {
+		ret = __clk_lookup_subtree(name, root_clk);
+		if (ret)
+			return ret;
+	}
+
+	return NULL;
+}
+
+/***        clk api        ***/
+
+void __clk_unprepare(struct clk *clk)
+{
+	if (!clk)
+		return;
+
+	if (WARN_ON(clk->prepare_count == 0))
+		return;
+
+	if (--clk->prepare_count > 0)
+		return;
+
+	WARN_ON(clk->enable_count > 0);
+
+	if (clk->ops->unprepare)
+		clk->ops->unprepare(clk->hw);
+
+	__clk_unprepare(clk->parent);
+}
+
+/**
+ * clk_unprepare - undo preparation of a clock source
+ * @clk: the clk being unprepare
+ *
+ * clk_unprepare may sleep, which differentiates it from clk_disable.  In a
+ * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
+ * if the operation may sleep.  One example is a clk which is accessed over
+ * I2c.  In the complex case a clk gate operation may require a fast and a slow
+ * part.  It is this reason that clk_unprepare and clk_disable are not mutually
+ * exclusive.  In fact clk_disable must be called before clk_unprepare.
+ */
+void clk_unprepare(struct clk *clk)
+{
+	mutex_lock(&prepare_lock);
+	__clk_unprepare(clk);
+	mutex_unlock(&prepare_lock);
+}
+EXPORT_SYMBOL_GPL(clk_unprepare);
+
+int __clk_prepare(struct clk *clk)
+{
+	int ret = 0;
+
+	if (!clk)
+		return 0;
+
+	if (clk->prepare_count == 0) {
+		ret = __clk_prepare(clk->parent);
+		if (ret)
+			return ret;
+
+		if (clk->ops->prepare) {
+			ret = clk->ops->prepare(clk->hw);
+			if (ret) {
+				__clk_unprepare(clk->parent);
+				return ret;
+			}
+		}
+	}
+
+	clk->prepare_count++;
+
+	return 0;
+}
+
+/**
+ * clk_prepare - prepare a clock source
+ * @clk: the clk being prepared
+ *
+ * clk_prepare may sleep, which differentiates it from clk_enable.  In a simple
+ * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
+ * operation may sleep.  One example is a clk which is accessed over I2c.  In
+ * the complex case a clk ungate operation may require a fast and a slow part.
+ * It is this reason that clk_prepare and clk_enable are not mutually
+ * exclusive.  In fact clk_prepare must be called before clk_enable.
+ * Returns 0 on success, -EERROR otherwise.
+ */
+int clk_prepare(struct clk *clk)
+{
+	int ret;
+
+	mutex_lock(&prepare_lock);
+	ret = __clk_prepare(clk);
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_prepare);
+
+static void __clk_disable(struct clk *clk)
+{
+	if (!clk)
+		return;
+
+	if (WARN_ON(clk->enable_count == 0))
+		return;
+
+	if (--clk->enable_count > 0)
+		return;
+
+	if (clk->ops->disable)
+		clk->ops->disable(clk->hw);
+
+	if (clk->parent)
+		__clk_disable(clk->parent);
+}
+
+/**
+ * clk_disable - gate a clock
+ * @clk: the clk being gated
+ *
+ * clk_disable must not sleep, which differentiates it from clk_unprepare.  In
+ * a simple case, clk_disable can be used instead of clk_unprepare to gate a
+ * clk if the operation is fast and will never sleep.  One example is a
+ * SoC-internal clk which is controlled via simple register writes.  In the
+ * complex case a clk gate operation may require a fast and a slow part.  It is
+ * this reason that clk_unprepare and clk_disable are not mutually exclusive.
+ * In fact clk_disable must be called before clk_unprepare.
+ */
+void clk_disable(struct clk *clk)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&enable_lock, flags);
+	__clk_disable(clk);
+	spin_unlock_irqrestore(&enable_lock, flags);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+static int __clk_enable(struct clk *clk)
+{
+	int ret = 0;
+
+	if (!clk)
+		return 0;
+
+	if (WARN_ON(clk->prepare_count == 0))
+		return -ESHUTDOWN;
+
+	if (clk->enable_count == 0) {
+		if (clk->parent)
+			ret = __clk_enable(clk->parent);
+
+		if (ret)
+			return ret;
+
+		if (clk->ops->enable) {
+			ret = clk->ops->enable(clk->hw);
+			if (ret) {
+				__clk_disable(clk->parent);
+				return ret;
+			}
+		}
+	}
+
+	clk->enable_count++;
+	return 0;
+}
+
+/**
+ * clk_enable - ungate a clock
+ * @clk: the clk being ungated
+ *
+ * clk_enable must not sleep, which differentiates it from clk_prepare.  In a
+ * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
+ * if the operation will never sleep.  One example is a SoC-internal clk which
+ * is controlled via simple register writes.  In the complex case a clk ungate
+ * operation may require a fast and a slow part.  It is this reason that
+ * clk_enable and clk_prepare are not mutually exclusive.  In fact clk_prepare
+ * must be called before clk_enable.  Returns 0 on success, -EERROR
+ * otherwise.
+ */
+int clk_enable(struct clk *clk)
+{
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&enable_lock, flags);
+	ret = __clk_enable(clk);
+	spin_unlock_irqrestore(&enable_lock, flags);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+/**
+ * clk_get_rate - return the rate of clk
+ * @clk: the clk whose rate is being returned
+ *
+ * Simply returns the cached rate of the clk.  Does not query the hardware.  If
+ * clk is NULL then returns -EINVAL.
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+	unsigned long rate;
+
+	mutex_lock(&prepare_lock);
+	rate = __clk_get_rate(clk);
+	mutex_unlock(&prepare_lock);
+
+	return rate;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+/**
+ * __clk_round_rate - round the given rate for a clk
+ * @clk: round the rate of this clock
+ *
+ * Caller must hold prepare_lock.  Useful for clk_ops such as .set_rate
+ */
+unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (!clk && !clk->ops->round_rate)
+		return -EINVAL;
+
+	return clk->ops->round_rate(clk->hw, rate, NULL);
+}
+
+/**
+ * clk_round_rate - round the given rate for a clk
+ * @clk: the clk for which we are rounding a rate
+ * @rate: the rate which is to be rounded
+ *
+ * Takes in a rate as input and rounds it to a rate that the clk can actually
+ * use which is then returned.  If clk doesn't support round_rate operation
+ * then the rate passed in is returned.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long ret = rate;
+
+	mutex_lock(&prepare_lock);
+	if (clk && clk->ops->round_rate)
+		ret = __clk_round_rate(clk, rate);
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+/**
+ * __clk_notify - call clk notifier chain
+ * @clk: struct clk * that is changing rate
+ * @msg: clk notifier type (see include/linux/clk.h)
+ * @old_rate: old clk rate
+ * @new_rate: new clk rate
+ *
+ * Triggers a notifier call chain on the clk rate-change notification
+ * for 'clk'.  Passes a pointer to the struct clk and the previous
+ * and current rates to the notifier callback.  Intended to be called by
+ * internal clock code only.  Returns NOTIFY_DONE from the last driver
+ * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
+ * a driver returns that.
+ */
+static int __clk_notify(struct clk *clk, unsigned long msg,
+		unsigned long old_rate, unsigned long new_rate)
+{
+	struct clk_notifier *cn;
+	struct clk_notifier_data cnd;
+	int ret = NOTIFY_DONE;
+
+	cnd.clk = clk;
+	cnd.old_rate = old_rate;
+	cnd.new_rate = new_rate;
+
+	list_for_each_entry(cn, &clk_notifier_list, node) {
+		if (cn->clk == clk) {
+			ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
+					&cnd);
+			break;
+		}
+	}
+
+	return ret;
+}
+
+/**
+ * __clk_recalc_rates
+ * @clk: first clk in the subtree
+ * @msg: notification type (see include/linux/clk.h)
+ *
+ * Walks the subtree of clks starting with clk and recalculates rates as it
+ * goes.  Note that if a clk does not implement the recalc_rate operation then
+ * propagation of that subtree stops and all of that clks children will not
+ * have their rates updated.
+ *
+ * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
+ * if necessary.
+ *
+ * Caller must hold prepare_lock.
+ */
+static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
+{
+	unsigned long old_rate;
+	unsigned long parent_rate = 0;
+	struct hlist_node *tmp;
+	struct clk *child;
+
+	old_rate = clk->rate;
+
+	if (clk->parent)
+		parent_rate = clk->parent->rate;
+
+	if (clk->ops->recalc_rate)
+		clk->rate = clk->ops->recalc_rate(clk->hw, parent_rate);
+	else
+		clk->rate = parent_rate;
+
+	/*
+	 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
+	 * & ABORT_RATE_CHANGE notifiers
+	 */
+	if (clk->notifier_count && msg)
+		__clk_notify(clk, msg, old_rate, clk->rate);
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node)
+		__clk_recalc_rates(child, msg);
+}
+
+/**
+ * __clk_speculate_rates
+ * @clk: first clk in the subtree
+ * @parent_rate: the "future" rate of clk's parent
+ *
+ * Walks the subtree of clks starting with clk, speculating rates as it
+ * goes and firing off PRE_RATE_CHANGE notifications as necessary.
+ *
+ * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
+ * pre-rate change notifications and returns early if no clks in the
+ * subtree have subscribed to the notifications.
+ *
+ * Caller must hold prepare_lock.
+ */
+static int __clk_speculate_rates(struct clk *clk, unsigned long parent_rate)
+{
+	struct hlist_node *tmp;
+	struct clk *child;
+	unsigned long new_rate;
+	int ret = NOTIFY_DONE;
+
+	if (!clk->ops->recalc_rate)
+		goto out;
+
+	new_rate = clk->ops->recalc_rate(clk->hw, parent_rate);
+
+	/* abort the rate change if a driver returns NOTIFY_BAD */
+	if (clk->notifier_count)
+		ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
+
+	if (ret == NOTIFY_BAD)
+		goto out;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		ret = __clk_speculate_rates(child, new_rate);
+		if (ret == NOTIFY_BAD)
+			break;
+	}
+
+out:
+	return ret;
+}
+
+/**
+ * DOC: Using the CLK_SET_RATE_PARENT flag
+ *
+ * __clk_set_rate changes the child's rate before the parent's to more
+ * easily handle failure conditions.
+ *
+ * This means clk might run out of spec for a short time if its rate is
+ * increased before the parent's rate is updated.
+ *
+ * To prevent this consider setting the CLK_SET_RATE_GATE flag on any
+ * clk where you also set the CLK_SET_RATE_PARENT flag
+ *
+ * PRE_RATE_CHANGE notifications are supposed to stack as a rate change
+ * request propagates up the clk tree.  This reflects the different
+ * rates that a downstream clk might experience if left enabled while
+ * upstream parents change their rates.
+ */
+static struct clk *__clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk *fail_clk = NULL;
+	int ret = NOTIFY_DONE;
+	unsigned long old_rate = clk->rate;
+	unsigned long new_rate;
+	unsigned long parent_old_rate;
+	unsigned long parent_new_rate = 0;
+	struct clk *child;
+	struct hlist_node *tmp;
+
+	/* bail early if we can't change rate while clk is enabled */
+	if ((clk->flags & CLK_SET_RATE_GATE) && clk->enable_count)
+		return clk;
+
+	/* find the new rate and see if parent rate should change too */
+	WARN_ON(!clk->ops->round_rate);
+
+	new_rate = clk->ops->round_rate(clk->hw, rate, &parent_new_rate);
+
+	/* NOTE: pre-rate change notifications will stack */
+	if (clk->notifier_count)
+		ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
+
+	if (ret == NOTIFY_BAD)
+		return clk;
+
+	/* speculate rate changes down the tree */
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		ret = __clk_speculate_rates(child, new_rate);
+		if (ret == NOTIFY_BAD)
+			return clk;
+	}
+
+	/* change the rate of this clk */
+	if (clk->ops->set_rate)
+		ret = clk->ops->set_rate(clk->hw, new_rate);
+
+	if (ret == NOTIFY_BAD)
+		return clk;
+
+	/*
+	 * change the rate of the parent clk if necessary
+	 *
+	 * hitting the nested 'if' path implies we have hit a .set_rate
+	 * failure somewhere upstream while propagating __clk_set_rate
+	 * up the clk tree.  roll back the clk rates one by one and
+	 * return the pointer to the clk that failed.  clk_set_rate will
+	 * use the pointer to propagate a rate-change abort notifier
+	 * from the "highest" point.
+	 */
+	if ((clk->flags & CLK_SET_RATE_PARENT) && parent_new_rate) {
+		parent_old_rate = clk->parent->rate;
+		fail_clk = __clk_set_rate(clk->parent, parent_new_rate);
+
+		/* roll back changes if parent rate change failed */
+		if (fail_clk) {
+			pr_warn("%s: failed to set parent %s rate to %lu\n",
+					__func__, fail_clk->name,
+					parent_new_rate);
+
+			/*
+			 * Send PRE_RATE_CHANGE notifiers down the tree
+			 * again, since we're rolling back the rate
+			 * changes due to the abort.
+			 *
+			 * Ignore any NOTIFY_BAD's since this *is* the
+			 * exception handler.
+			 *
+			 * NOTE: pre-rate change notifications will stack
+			 */
+			__clk_speculate_rates(clk, clk->parent->rate);
+
+			clk->ops->set_rate(clk->hw, old_rate);
+		}
+		return fail_clk;
+	}
+
+	/*
+	 * set clk's rate & recalculate the rates of clk's children
+	 *
+	 * hitting this path implies we have successfully finished
+	 * propagating recursive calls to __clk_set_rate up the clk tree
+	 * (if necessary) and it is safe to propagate __clk_recalc_rates
+	 * and post-rate change notifiers down the clk tree from this
+	 * point.
+	 */
+	__clk_recalc_rates(clk, POST_RATE_CHANGE);
+
+	return NULL;
+}
+
+/**
+ * clk_set_rate - specify a new rate for clk
+ * @clk: the clk whose rate is being changed
+ * @rate: the new rate for clk
+ *
+ * In the simplest case clk_set_rate will only change the rate of clk.
+ *
+ * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call
+ * will fail; only when the clk is disabled will it be able to change
+ * its rate.
+ *
+ * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to
+ * recursively propagate up to clk's parent; whether or not this happens
+ * depends on the outcome of clk's .round_rate implementation.  If
+ * *parent_rate is 0 after calling .round_rate then upstream parent
+ * propagation is ignored.  If *parent_rate comes back with a new rate
+ * for clk's parent then we propagate up to clk's parent and set it's
+ * rate.  Upward propagation will continue until either a clk does not
+ * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting
+ * changes to clk's parent_rate.  If there is a failure during upstream
+ * propagation then clk_set_rate will unwind and restore each clk's rate
+ * that had been successfully changed.  Afterwards a rate change abort
+ * notification will be propagated downstream, starting from the clk
+ * that failed.
+ *
+ * At the end of all of the rate setting, clk_set_rate internally calls
+ * __clk_recalc_rates and propagates the rate changes downstream,
+ * starting from the highest clk whose rate was changed.  This has the
+ * added benefit of propagating post-rate change notifiers.
+ *
+ * Note that while post-rate change and rate change abort notifications
+ * are guaranteed to be sent to a clk only once per call to
+ * clk_set_rate, pre-change notifications will be sent for every clk
+ * whose rate is changed.  Stacking pre-change notifications is noisy
+ * for the drivers subscribed to them, but this allows drivers to react
+ * to intermediate clk rate changes up until the point where the final
+ * rate is achieved at the end of upstream propagation.
+ *
+ * Returns 0 on success, -EERROR otherwise.
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk *fail_clk;
+	int ret = 0;
+
+	/* prevent racing with updates to the clock topology */
+	mutex_lock(&prepare_lock);
+
+	/* bail early if nothing to do */
+	if (rate == clk->rate)
+		goto out;
+
+	fail_clk = __clk_set_rate(clk, rate);
+	if (fail_clk) {
+		pr_warn("%s: failed to set %s rate\n", __func__,
+				fail_clk->name);
+		__clk_recalc_rates(clk, ABORT_RATE_CHANGE);
+		ret = -EIO;
+	}
+
+out:
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+/**
+ * clk_get_parent - return the parent of a clk
+ * @clk: the clk whose parent gets returned
+ *
+ * Simply returns clk->parent.  Returns NULL if clk is NULL.
+ */
+struct clk *clk_get_parent(struct clk *clk)
+{
+	struct clk *parent;
+
+	mutex_lock(&prepare_lock);
+	parent = __clk_get_parent(clk);
+	mutex_unlock(&prepare_lock);
+
+	return parent;
+}
+EXPORT_SYMBOL_GPL(clk_get_parent);
+
+/*
+ * .get_parent is mandatory for clocks with multiple possible parents.  It is
+ * optional for single-parent clocks.  Always call .get_parent if it is
+ * available and WARN if it is missing for multi-parent clocks.
+ *
+ * For single-parent clocks without .get_parent, first check to see if the
+ * .parents array exists, and if so use it to avoid an expensive tree
+ * traversal.  If .parents does not exist then walk the tree with __clk_lookup.
+ */
+static struct clk *__clk_init_parent(struct clk *clk)
+{
+	struct clk *ret = NULL;
+	u8 index;
+
+	/* handle the trivial cases */
+
+	if (!clk->num_parents)
+		goto out;
+
+	if (clk->num_parents == 1) {
+		if (IS_ERR_OR_NULL(clk->parent))
+			ret = clk->parent = __clk_lookup(clk->parent_names[0]);
+		ret = clk->parent;
+		goto out;
+	}
+
+	if (!clk->ops->get_parent) {
+		WARN(!clk->ops->get_parent,
+			"%s: multi-parent clocks must implement .get_parent\n",
+			__func__);
+		goto out;
+	};
+
+	/*
+	 * Do our best to cache parent clocks in clk->parents.  This prevents
+	 * unnecessary and expensive calls to __clk_lookup.  We don't set
+	 * clk->parent here; that is done by the calling function
+	 */
+
+	index = clk->ops->get_parent(clk->hw);
+
+	if (!clk->parents)
+		clk->parents =
+			kmalloc((sizeof(struct clk*) * clk->num_parents),
+					GFP_KERNEL);
+
+	if (!clk->parents)
+		ret = __clk_lookup(clk->parent_names[index]);
+	else if (!clk->parents[index])
+		ret = clk->parents[index] =
+			__clk_lookup(clk->parent_names[index]);
+	else
+		ret = clk->parents[index];
+
+out:
+	return ret;
+}
+
+void __clk_reparent(struct clk *clk, struct clk *new_parent)
+{
+#ifdef CONFIG_COMMON_CLK_DEBUG
+	struct dentry *d;
+	struct dentry *new_parent_d;
+#endif
+
+	if (!clk || !new_parent)
+		return;
+
+	hlist_del(&clk->child_node);
+
+	if (new_parent)
+		hlist_add_head(&clk->child_node, &new_parent->children);
+	else
+		hlist_add_head(&clk->child_node, &clk_orphan_list);
+
+#ifdef CONFIG_COMMON_CLK_DEBUG
+	if (!inited)
+		goto out;
+
+	if (new_parent)
+		new_parent_d = new_parent->dentry;
+	else
+		new_parent_d = orphandir;
+
+	d = debugfs_rename(clk->dentry->d_parent, clk->dentry,
+			new_parent_d, clk->name);
+	if (d)
+		clk->dentry = d;
+	else
+		pr_debug("%s: failed to rename debugfs entry for %s\n",
+				__func__, clk->name);
+out:
+#endif
+
+	clk->parent = new_parent;
+
+	__clk_recalc_rates(clk, POST_RATE_CHANGE);
+}
+
+static int __clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct clk *old_parent;
+	unsigned long flags;
+	int ret = -EINVAL;
+	u8 i;
+
+	old_parent = clk->parent;
+
+	/* find index of new parent clock using cached parent ptrs */
+	for (i = 0; i < clk->num_parents; i++)
+		if (clk->parents[i] == parent)
+			break;
+
+	/*
+	 * find index of new parent clock using string name comparison
+	 * also try to cache the parent to avoid future calls to __clk_lookup
+	 */
+	if (i == clk->num_parents)
+		for (i = 0; i < clk->num_parents; i++)
+			if (!strcmp(clk->parent_names[i], parent->name)) {
+				clk->parents[i] = __clk_lookup(parent->name);
+				break;
+			}
+
+	if (i == clk->num_parents) {
+		pr_debug("%s: clock %s is not a possible parent of clock %s\n",
+				__func__, parent->name, clk->name);
+		goto out;
+	}
+
+	/* migrate prepare and enable */
+	if (clk->prepare_count)
+		__clk_prepare(parent);
+
+	/* FIXME replace with clk_is_enabled(clk) someday */
+	spin_lock_irqsave(&enable_lock, flags);
+	if (clk->enable_count)
+		__clk_enable(parent);
+	spin_unlock_irqrestore(&enable_lock, flags);
+
+	/* change clock input source */
+	ret = clk->ops->set_parent(clk->hw, i);
+
+	/* clean up old prepare and enable */
+	spin_lock_irqsave(&enable_lock, flags);
+	if (clk->enable_count)
+		__clk_disable(old_parent);
+	spin_unlock_irqrestore(&enable_lock, flags);
+
+	if (clk->prepare_count)
+		__clk_unprepare(old_parent);
+
+out:
+	return ret;
+}
+
+/**
+ * clk_set_parent - switch the parent of a mux clk
+ * @clk: the mux clk whose input we are switching
+ * @parent: the new input to clk
+ *
+ * Re-parent clk to use parent as it's new input source.  If clk has the
+ * CLK_SET_PARENT_GATE flag set then clk must be gated for this
+ * operation to succeed.  After successfully changing clk's parent
+ * clk_set_parent will update the clk topology, sysfs topology and
+ * propagate rate recalculation via __clk_recalc_rates.  Returns 0 on
+ * success, -EERROR otherwise.
+ */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	int ret = 0;
+
+	if (!clk || !clk->ops)
+		return -EINVAL;
+
+	if (!clk->ops->set_parent)
+		return -ENOSYS;
+
+	/* prevent racing with updates to the clock topology */
+	mutex_lock(&prepare_lock);
+
+	if (clk->parent == parent)
+		goto out;
+
+	/* propagate PRE_RATE_CHANGE notifications */
+	if (clk->notifier_count)
+		ret = __clk_speculate_rates(clk, parent->rate);
+
+	/* abort if a driver objects */
+	if (ret == NOTIFY_STOP)
+		goto out;
+
+	/* only re-parent if the clock is not in use */
+	if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count)
+		ret = -EBUSY;
+	else
+		ret = __clk_set_parent(clk, parent);
+
+	/* propagate ABORT_RATE_CHANGE if .set_parent failed */
+	if (ret) {
+		__clk_recalc_rates(clk, ABORT_RATE_CHANGE);
+		goto out;
+	}
+
+	/* propagate rate recalculation downstream */
+	__clk_reparent(clk, parent);
+
+out:
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+/**
+ * __clk_init - initialize the data structures in a struct clk
+ * @dev:	device initializing this clk, placeholder for now
+ * @clk:	clk being initialized
+ *
+ * Initializes the lists in struct clk, queries the hardware for the
+ * parent and rate and sets them both.
+ *
+ * Any struct clk passed into __clk_init must have the following members
+ * populated:
+ * 	.name
+ * 	.ops
+ * 	.hw
+ * 	.parent_names
+ * 	.num_parents
+ * 	.flags
+ *
+ * Essentially, everything that would normally be passed into clk_register is
+ * assumed to be initialized already in __clk_init.  The other members may be
+ * populated, but are optional.
+ *
+ * __clk_init is only exposed via clk-private.h and is intended for use with
+ * very large numbers of clocks that need to be statically initialized.  It is
+ * a layering violation to include clk-private.h from any code which implements
+ * a clock's .ops; as such any statically initialized clock data MUST be in a
+ * separate C file from the logic that implements it's operations.
+ */
+void __clk_init(struct device *dev, struct clk *clk)
+{
+	int i;
+	struct clk *orphan;
+	struct hlist_node *tmp;
+
+	if (!clk)
+		return;
+
+	mutex_lock(&prepare_lock);
+
+	/* check to see if a clock with this name is already registered */
+	if (__clk_lookup(clk->name))
+		goto out;
+
+	/*
+	 * Allocate an array of struct clk *'s to avoid unnecessary string
+	 * look-ups of clk's possible parents.  This can fail for clocks passed
+	 * in to clk_init during early boot; thus any access to clk->parents[]
+	 * must always check for a NULL pointer and try to populate it if
+	 * necessary.
+	 *
+	 * If clk->parents is not NULL we skip this entire block.  This allows
+	 * for clock drivers to statically initialize clk->parents.
+	 */
+	if (clk->num_parents && !clk->parents) {
+		clk->parents = kmalloc((sizeof(struct clk*) * clk->num_parents),
+				GFP_KERNEL);
+		/*
+		 * __clk_lookup returns NULL for parents that have not been
+		 * clk_init'd; thus any access to clk->parents[] must check
+		 * for a NULL pointer.  We can always perform lazy lookups for
+		 * missing parents later on.
+		 */
+		if (clk->parents)
+			for (i = 0; i < clk->num_parents; i++)
+				clk->parents[i] =
+					__clk_lookup(clk->parent_names[i]);
+	}
+
+	clk->parent = __clk_init_parent(clk);
+
+	/*
+	 * Populate clk->parent if parent has already been __clk_init'd.  If
+	 * parent has not yet been __clk_init'd then place clk in the orphan
+	 * list.  If clk has set the CLK_IS_ROOT flag then place it in the root
+	 * clk list.
+	 *
+	 * Every time a new clk is clk_init'd then we walk the list of orphan
+	 * clocks and re-parent any that are children of the clock currently
+	 * being clk_init'd.
+	 */
+	if (clk->parent)
+		hlist_add_head(&clk->child_node,
+				&clk->parent->children);
+	else if (clk->flags & CLK_IS_ROOT)
+		hlist_add_head(&clk->child_node, &clk_root_list);
+	else
+		hlist_add_head(&clk->child_node, &clk_orphan_list);
+
+	/*
+	 * Set clk's rate.  The preferred method is to use .recalc_rate.  For
+	 * simple clocks and lazy developers the default fallback is to use the
+	 * parent's rate.  If a clock doesn't have a parent (or is orphaned)
+	 * then rate is set to zero.
+	 */
+	if (clk->ops->recalc_rate)
+		clk->rate = clk->ops->recalc_rate(clk->hw,
+				__clk_get_rate(clk->parent));
+	else if (clk->parent)
+		clk->rate = clk->parent->rate;
+	else
+		clk->rate = 0;
+
+	/*
+	 * walk the list of orphan clocks and reparent any that are children of
+	 * this clock
+	 */
+	hlist_for_each_entry(orphan, tmp, &clk_orphan_list, child_node)
+		__clk_reparent(orphan, __clk_init_parent(orphan));
+
+	/*
+	 * optional platform-specific magic
+	 *
+	 * The .init callback is not used by any of the basic clock types, but
+	 * exists for weird hardware that must perform initialization magic.
+	 * Please consider other ways of solving initialization problems before
+	 * using this callback, as it's use is discouraged.
+	 */
+	if (clk->ops->init)
+		clk->ops->init(clk->hw);
+
+	clk_debug_register(clk);
+
+out:
+	mutex_unlock(&prepare_lock);
+
+	return;
+}
+
+/**
+ * clk_register - allocate a new clock, register it and return an opaque cookie
+ * @dev: device that is registering this clock
+ * @name: clock name
+ * @ops: operations this clock supports
+ * @hw: link to hardware-specific clock data
+ * @parent_names: array of string names for all possible parents
+ * @num_parents: number of possible parents
+ * @flags: framework-level hints and quirks
+ *
+ * clk_register is the primary interface for populating the clock tree with new
+ * clock nodes.  It returns a pointer to the newly allocated struct clk which
+ * cannot be dereferenced by driver code but may be used in conjuction with the
+ * rest of the clock API.
+ */
+struct clk *clk_register(struct device *dev, const char *name,
+		const struct clk_ops *ops, struct clk_hw *hw,
+		char **parent_names, u8 num_parents, unsigned long flags)
+{
+	struct clk *clk;
+
+	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+	if (!clk)
+		return NULL;
+
+	clk->name = name;
+	clk->ops = ops;
+	clk->hw = hw;
+	clk->flags = flags;
+	clk->parent_names = parent_names;
+	clk->num_parents = num_parents;
+	hw->clk = clk;
+
+	__clk_init(dev, clk);
+
+	return clk;
+}
+EXPORT_SYMBOL_GPL(clk_register);
+
+/***        clk rate change notifiers        ***/
+
+/**
+ * clk_notifier_register - add a clk rate change notifier
+ * @clk: struct clk * to watch
+ * @nb: struct notifier_block * with callback info
+ *
+ * Request notification when clk's rate changes.  This uses an SRCU
+ * notifier because we want it to block and notifier unregistrations are
+ * uncommon.  The callbacks associated with the notifier must not
+ * re-enter into the clk framework by calling any top-level clk APIs;
+ * this will cause a nested prepare_lock mutex.
+ *
+ * Pre-change notifier callbacks will be passed the current, pre-change
+ * rate of the clk via struct clk_notifier_data.old_rate.  The new,
+ * post-change rate of the clk is passed via struct
+ * clk_notifier.new_rate.
+ *
+ * Post-change notifiers will pass the now-current, post-change rate of
+ * the clk in both struct clk_notifier_data.old_rate and struct
+ * clk_notifier_data.new_rate.
+ *
+ * Abort-change notifiers are effectively the opposite of pre-change
+ * notifiers: the original pre-change clk rate is passed in via struct
+ * clk_notifier_data.new_rate and the failed post-change rate is passed
+ * in via struct clk_notifier_data.old_rate.
+ *
+ * clk_notifier_register() must be called from non-atomic context.
+ * Returns -EINVAL if called with null arguments, -ENOMEM upon
+ * allocation failure; otherwise, passes along the return value of
+ * srcu_notifier_chain_register().
+ */
+int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
+{
+	struct clk_notifier *cn;
+	int ret = -ENOMEM;
+
+	if (!clk || !nb)
+		return -EINVAL;
+
+	mutex_lock(&prepare_lock);
+
+	/* search the list of notifiers for this clk */
+	list_for_each_entry(cn, &clk_notifier_list, node)
+		if (cn->clk == clk)
+			break;
+
+	/* if clk wasn't in the notifier list, allocate new clk_notifier */
+	if (cn->clk != clk) {
+		cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
+		if (!cn)
+			goto out;
+
+		cn->clk = clk;
+		srcu_init_notifier_head(&cn->notifier_head);
+
+		list_add(&cn->node, &clk_notifier_list);
+	}
+
+	ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
+
+	clk->notifier_count++;
+
+out:
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_notifier_register);
+
+/**
+ * clk_notifier_unregister - remove a clk rate change notifier
+ * @clk: struct clk *
+ * @nb: struct notifier_block * with callback info
+ *
+ * Request no further notification for changes to 'clk' and frees memory
+ * allocated in clk_notifier_register.
+ *
+ * Returns -EINVAL if called with null arguments; otherwise, passes
+ * along the return value of srcu_notifier_chain_unregister().
+ */
+int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
+{
+	struct clk_notifier *cn = NULL;
+	int ret = -EINVAL;
+
+	if (!clk || !nb)
+		return -EINVAL;
+
+	mutex_lock(&prepare_lock);
+
+	list_for_each_entry(cn, &clk_notifier_list, node)
+		if (cn->clk == clk)
+			break;
+
+	if (cn->clk == clk) {
+		ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
+
+		clk->notifier_count--;
+
+		/* XXX the notifier code should handle this better */
+		if (!cn->notifier_head.head) {
+			srcu_cleanup_notifier_head(&cn->notifier_head);
+			kfree(cn);
+		}
+
+	} else {
+		ret = -ENOENT;
+	}
+
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_notifier_unregister);
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
new file mode 100644
index 0000000..33bf6a7
--- /dev/null
+++ b/include/linux/clk-private.h
@@ -0,0 +1,68 @@
+/*
+ *  linux/include/linux/clk-private.h
+ *
+ *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr at canonical.com>
+ *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_CLK_PRIVATE_H
+#define __LINUX_CLK_PRIVATE_H
+
+#include <linux/clk-provider.h>
+#include <linux/list.h>
+
+/*
+ * WARNING: Do not include clk-private.h from any file that implements struct
+ * clk_ops.  Doing so is a layering violation!
+ *
+ * This header exists only to allow for statically initialized clock data.  Any
+ * static clock data must be defined in a separate file from the logic that
+ * implements the clock operations for that same data.
+ */
+
+#ifdef CONFIG_COMMON_CLK
+
+struct clk {
+	const char		*name;
+	const struct clk_ops	*ops;
+	struct clk_hw		*hw;
+	struct clk		*parent;
+	char			**parent_names;
+	struct clk		**parents;
+	u8			num_parents;
+	unsigned long		rate;
+	unsigned long		flags;
+	unsigned int		enable_count;
+	unsigned int		prepare_count;
+	struct hlist_head	children;
+	struct hlist_node	child_node;
+	unsigned int		notifier_count;
+#ifdef CONFIG_COMMON_CLK_DEBUG
+	struct dentry		*dentry;
+#endif
+};
+
+/**
+ * __clk_init - initialize the data structures in a struct clk
+ * @dev:	device initializing this clk, placeholder for now
+ * @clk:	clk being initialized
+ *
+ * Initializes the lists in struct clk, queries the hardware for the
+ * parent and rate and sets them both.
+ *
+ * Any struct clk passed into __clk_init must have the following members
+ * populated:
+ * 	.name
+ * 	.ops
+ * 	.hw
+ * 	.parent_names
+ * 	.num_parents
+ * 	.flags
+ */
+void __clk_init(struct device *dev, struct clk *clk);
+
+#endif /* CONFIG_COMMON_CLK */
+#endif /* CLK_PRIVATE_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
new file mode 100644
index 0000000..c9ed582
--- /dev/null
+++ b/include/linux/clk-provider.h
@@ -0,0 +1,169 @@
+/*
+ *  linux/include/linux/clk-provider.h
+ *
+ *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr at canonical.com>
+ *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_CLK_PROVIDER_H
+#define __LINUX_CLK_PROVIDER_H
+
+#include <linux/clk.h>
+
+#ifdef CONFIG_COMMON_CLK
+
+/**
+ * struct clk_hw - handle for traversing from a struct clk to its corresponding
+ * hardware-specific structure.  struct clk_hw should be declared within struct
+ * clk_foo and then referenced by the struct clk instance that uses struct
+ * clk_foo's clk_ops
+ *
+ * clk: pointer to the struct clk instance that points back to this struct
+ * clk_hw instance
+ */
+struct clk_hw {
+	struct clk *clk;
+};
+
+/*
+ * flags used across common struct clk.  these flags should only affect the
+ * top-level framework.  custom flags for dealing with hardware specifics
+ * belong in struct clk_foo
+ */
+#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
+#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
+#define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
+#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
+#define CLK_IS_ROOT		BIT(4) /* root clk, has no parent */
+
+/**
+ * struct clk_ops -  Callback operations for hardware clocks; these are to
+ * be provided by the clock implementation, and will be called by drivers
+ * through the clk_* api.
+ *
+ * @prepare:	Prepare the clock for enabling. This must not return until
+ * 		the clock is fully prepared, and it's safe to call clk_enable.
+ * 		This callback is intended to allow clock implementations to
+ * 		do any initialisation that may sleep. Called with
+ * 		prepare_lock held.
+ *
+ * @unprepare:	Release the clock from its prepared state. This will typically
+ * 		undo any work done in the @prepare callback. Called with
+ * 		prepare_lock held.
+ *
+ * @enable:	Enable the clock atomically. This must not return until the
+ * 		clock is generating a valid clock signal, usable by consumer
+ * 		devices. Called with enable_lock held. This function must not
+ * 		sleep.
+ *
+ * @disable:	Disable the clock atomically. Called with enable_lock held.
+ * 		This function must not sleep.
+ *
+ * @recalc_rate	Recalculate the rate of this clock, by quering hardware.  The
+ * 		parent rate is an input parameter.  It is up to the caller to
+ * 		insure that the prepare_mutex is held across this call.
+ * 		Returns the calculated rate.  Optional, but recommended - if
+ * 		this op is not set then clock rate will be initialized to 0.
+ *
+ * @round_rate:	Given a target rate as input, returns the closest rate actually
+ * 		supported by the clock.
+ *
+ * @get_parent:	Queries the hardware to determine the parent of a clock.  The
+ * 		return value is a u8 which specifies the index corresponding to
+ * 		the parent clock.  This index can be applied to either the
+ * 		.parent_names or .parents arrays.  In short, this function
+ * 		translates the parent value read from hardware into an array
+ * 		index.  Currently only called when the clock is initialized by
+ * 		__clk_init.  This callback is mandatory for clocks with
+ * 		multiple parents.  It is optional (and unnecessary) for clocks
+ * 		with 0 or 1 parents.
+ *
+ * @set_parent:	Change the input source of this clock; for clocks with multiple
+ * 		possible parents specify a new parent by passing in the index
+ * 		as a u8 corresponding to the parent in either the .parent_names
+ * 		or .parents arrays.  This function in affect translates an
+ * 		array index into the value programmed into the hardware.
+ * 		Returns 0 on success, -EERROR otherwise.
+ *
+ * @set_rate:	Change the rate of this clock. If this callback returns
+ * 		CLK_SET_RATE_PARENT, the rate change will be propagated to the
+ * 		parent clock (which may propagate again if the parent clock
+ * 		also sets this flag). The requested rate of the parent is
+ * 		passed back from the callback in the second 'unsigned long *'
+ * 		argument.  Note that it is up to the hardware clock's set_rate
+ * 		implementation to insure that clocks do not run out of spec
+ * 		when propgating the call to set_rate up to the parent.  One way
+ * 		to do this is to gate the clock (via clk_disable and/or
+ * 		clk_unprepare) before calling clk_set_rate, then ungating it
+ * 		afterward.  If your clock also has the CLK_GATE_SET_RATE flag
+ * 		set then this will insure safety.  Returns 0 on success,
+ * 		-EERROR otherwise.
+ *
+ * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
+ * implementations to split any work between atomic (enable) and sleepable
+ * (prepare) contexts.  If enabling a clock requires code that might sleep,
+ * this must be done in clk_prepare.  Clock enable code that will never be
+ * called in a sleepable context may be implement in clk_enable.
+ *
+ * Typically, drivers will call clk_prepare when a clock may be needed later
+ * (eg. when a device is opened), and clk_enable when the clock is actually
+ * required (eg. from an interrupt). Note that clk_prepare MUST have been
+ * called before clk_enable.
+ */
+struct clk_ops {
+	int		(*prepare)(struct clk_hw *hw);
+	void		(*unprepare)(struct clk_hw *hw);
+	int		(*enable)(struct clk_hw *hw);
+	void		(*disable)(struct clk_hw *hw);
+	unsigned long	(*recalc_rate)(struct clk_hw *hw,
+					unsigned long parent_rate);
+	long		(*round_rate)(struct clk_hw *hw, unsigned long,
+					unsigned long *);
+	int		(*set_parent)(struct clk_hw *hw, u8 index);
+	u8		(*get_parent)(struct clk_hw *hw);
+	int		(*set_rate)(struct clk_hw *hw, unsigned long);
+	void		(*init)(struct clk_hw *hw);
+};
+
+
+/**
+ * clk_register - allocate a new clock, register it and return an opaque cookie
+ * @dev: device that is registering this clock
+ * @name: clock name
+ * @ops: operations this clock supports
+ * @hw: link to hardware-specific clock data
+ * @parent_names: array of string names for all possible parents
+ * @num_parents: number of possible parents
+ * @flags: framework-level hints and quirks
+ *
+ * clk_register is the primary interface for populating the clock tree with new
+ * clock nodes.  It returns a pointer to the newly allocated struct clk which
+ * cannot be dereferenced by driver code but may be used in conjuction with the
+ * rest of the clock API.
+ */
+struct clk *clk_register(struct device *dev, const char *name,
+		const struct clk_ops *ops, struct clk_hw *hw,
+		char **parent_names, u8 num_parents, unsigned long flags);
+
+/* helper functions */
+const char *__clk_get_name(struct clk *clk);
+struct clk_hw *__clk_get_hw(struct clk *clk);
+u8 __clk_get_num_parents(struct clk *clk);
+struct clk *__clk_get_parent(struct clk *clk);
+unsigned long __clk_get_rate(struct clk *clk);
+unsigned long __clk_get_flags(struct clk *clk);
+struct clk *__clk_lookup(const char *name);
+
+/*
+ * FIXME clock api without lock protection
+ */
+int __clk_prepare(struct clk *clk);
+void __clk_unprepare(struct clk *clk);
+void __clk_reparent(struct clk *clk, struct clk *new_parent);
+unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
+
+#endif /* CONFIG_COMMON_CLK */
+#endif /* CLK_PROVIDER_H */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index b9d46fa..b025272 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -3,6 +3,7 @@
  *
  *  Copyright (C) 2004 ARM Limited.
  *  Written by Deep Blue Solutions Limited.
+ *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,18 +13,75 @@
 #define __LINUX_CLK_H
 
 #include <linux/kernel.h>
+#include <linux/notifier.h>
 
 struct device;
 
-/*
- * The base API.
+struct clk;
+
+#ifdef CONFIG_COMMON_CLK
+
+/**
+ * DOC: clk notifier callback types
+ *
+ * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
+ *     to indicate that the rate change will proceed.  Drivers must
+ *     immediately terminate any operations that will be affected by the
+ *     rate change.  Callbacks may either return NOTIFY_DONE or
+ *     NOTIFY_STOP.
+ *
+ * ABORT_RATE_CHANGE: called if the rate change failed for some reason
+ *     after PRE_RATE_CHANGE.  In this case, all registered notifiers on
+ *     the clk will be called with ABORT_RATE_CHANGE. Callbacks must
+ *     always return NOTIFY_DONE.
+ *
+ * POST_RATE_CHANGE - called after the clk rate change has successfully
+ *     completed.  Callbacks must always return NOTIFY_DONE.
+ *
  */
+#define PRE_RATE_CHANGE			BIT(0)
+#define POST_RATE_CHANGE		BIT(1)
+#define ABORT_RATE_CHANGE		BIT(2)
 
+/**
+ * struct clk_notifier - associate a clk with a notifier
+ * @clk: struct clk * to associate the notifier with
+ * @notifier_head: a blocking_notifier_head for this clk
+ * @node: linked list pointers
+ *
+ * A list of struct clk_notifier is maintained by the notifier code.
+ * An entry is created whenever code registers the first notifier on a
+ * particular @clk.  Future notifiers on that @clk are added to the
+ * @notifier_head.
+ */
+struct clk_notifier {
+	struct clk			*clk;
+	struct srcu_notifier_head	notifier_head;
+	struct list_head		node;
+};
 
-/*
- * struct clk - an machine class defined object / cookie.
+/**
+ * struct clk_notifier_data - rate data to pass to the notifier callback
+ * @clk: struct clk * being changed
+ * @old_rate: previous rate of this clk
+ * @new_rate: new rate of this clk
+ *
+ * For a pre-notifier, old_rate is the clk's rate before this rate
+ * change, and new_rate is what the rate will be in the future.  For a
+ * post-notifier, old_rate and new_rate are both set to the clk's
+ * current rate (this was done to optimize the implementation).
  */
-struct clk;
+struct clk_notifier_data {
+	struct clk		*clk;
+	unsigned long		old_rate;
+	unsigned long		new_rate;
+};
+
+int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
+
+int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
+
+#endif /* !CONFIG_COMMON_CLK */
 
 /**
  * clk_get - lookup and obtain a reference to a clock producer.
-- 
1.7.5.4



From mturquette at linaro.org  Sat Mar  3 03:29:01 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Sat,  3 Mar 2012 00:29:01 -0800
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
Message-ID: <1330763341-3437-5-git-send-email-mturquette@linaro.org>

Many platforms support simple gateable clocks, fixed-rate clocks,
adjustable divider clocks and multi-parent multiplexer clocks.

This patch introduces basic clock types for the above-mentioned hardware
which share some common characteristics.

Based on original work by Jeremy Kerr and contribution by Jamie Iles.
Dividers and multiplexor clocks originally contributed by Richard Zhao &
Sascha Hauer.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Mike Turquette <mturquette at ti.com>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Jamie Iles <jamie at jamieiles.com>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Andrew Lunn <andrew at lunn.ch>
---
 drivers/clk/Makefile         |    3 +-
 drivers/clk/clk-divider.c    |  198 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/clk-fixed-rate.c |   81 +++++++++++++++++
 drivers/clk/clk-gate.c       |  121 +++++++++++++++++++++++++
 drivers/clk/clk-mux.c        |  114 ++++++++++++++++++++++++
 include/linux/clk-private.h  |  124 ++++++++++++++++++++++++++
 include/linux/clk-provider.h |  125 ++++++++++++++++++++++++++
 7 files changed, 765 insertions(+), 1 deletions(-)
 create mode 100644 drivers/clk/clk-divider.c
 create mode 100644 drivers/clk/clk-fixed-rate.c
 create mode 100644 drivers/clk/clk-gate.c
 create mode 100644 drivers/clk/clk-mux.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ff362c4..1f736bc 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,3 +1,4 @@
 
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
-obj-$(CONFIG_COMMON_CLK)	+= clk.o
+obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
+				   clk-mux.o clk-divider.o
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
new file mode 100644
index 0000000..8f02930
--- /dev/null
+++ b/drivers/clk/clk-divider.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Adjustable divider clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+/*
+ * DOC: basic adjustable divider clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is adjustable.  clk->rate = parent->rate / divisor
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	unsigned int div;
+
+	div = readl(divider->reg) >> divider->shift;
+	div &= (1 << divider->width) - 1;
+
+	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
+		div++;
+
+	return parent_rate / div;
+}
+
+static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+		unsigned long *best_parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	int i, bestdiv = 0;
+	unsigned long parent_rate, best = 0, now, maxdiv;
+
+	maxdiv = (1 << divider->width);
+
+	if (divider->flags & CLK_DIVIDER_ONE_BASED)
+		maxdiv--;
+
+	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
+		parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
+		bestdiv = parent_rate / rate;
+		bestdiv = bestdiv == 0 ? 1 : bestdiv;
+		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+		goto out;
+	}
+
+	/*
+	 * The maximum divider we can use without overflowing
+	 * unsigned long in rate * i below
+	 */
+	maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+	for (i = 1; i <= maxdiv; i++) {
+		int div;
+		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
+				rate * i);
+		div = parent_rate / rate;
+		div = div > maxdiv ? maxdiv : div;
+		div = div < 1 ? 1 : div;
+		now = parent_rate / div;
+
+		if (now <= rate && now >= best) {
+			bestdiv = div;
+			best = now;
+			*best_parent_rate = parent_rate;
+		}
+	}
+
+	if (!bestdiv) {
+		bestdiv = (1 << divider->width);
+		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
+	} else {
+		parent_rate = best * bestdiv;
+	}
+
+out:
+	if (best_parent_rate)
+		*best_parent_rate = parent_rate;
+
+	return bestdiv;
+}
+
+static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	unsigned long best_parent_rate;
+	int div = clk_divider_bestdiv(hw, rate, &best_parent_rate);
+	if (prate) {
+		if (best_parent_rate == __clk_get_rate(
+					__clk_get_parent(hw->clk)))
+			*prate = 0;
+		else
+			*prate = best_parent_rate;
+	}
+
+	return best_parent_rate / div;
+}
+
+static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
+{
+	unsigned long best_parent_rate;
+	struct clk_divider *divider = to_clk_divider(hw);
+	unsigned int div;
+	unsigned long flags = 0;
+	u32 val;
+
+	div = clk_divider_bestdiv(hw, rate, &best_parent_rate);
+
+	if (divider->lock)
+		spin_lock_irqsave(divider->lock, flags);
+
+	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
+		div--;
+
+	val = readl(divider->reg);
+	val &= ~(((1 << divider->width) - 1) << divider->shift);
+	val |= div << divider->shift;
+	writel(val, divider->reg);
+
+	if (divider->lock)
+		spin_unlock_irqrestore(divider->lock, flags);
+
+	return 0;
+}
+
+struct clk_ops clk_divider_ops = {
+	.recalc_rate = clk_divider_recalc_rate,
+	.round_rate = clk_divider_round_rate,
+	.set_rate = clk_divider_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_divider_ops);
+
+struct clk *clk_register_divider(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_divider_flags, spinlock_t *lock)
+{
+	struct clk_divider *div;
+	char **parent_names = NULL;
+	u8 len;
+
+	div = kmalloc(sizeof(struct clk_divider), GFP_KERNEL);
+
+	if (!div) {
+		pr_err("%s: could not allocate divider clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_divider assignments */
+	div->reg = reg;
+	div->shift = shift;
+	div->width = width;
+	div->flags = clk_divider_flags;
+	div->lock = lock;
+
+	if (parent_name) {
+		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
+
+		if (! parent_names)
+			goto out;
+
+		len = sizeof(char) * strlen(parent_name);
+
+		parent_names[0] = kmalloc(len, GFP_KERNEL);
+
+		if (!parent_names[0])
+			goto out;
+
+		strncpy(parent_names[0], parent_name, len);
+	}
+
+out:
+	return clk_register(dev, name,
+			&clk_divider_ops, &div->hw,
+			parent_names,
+			(parent_name ? 1 : 0),
+			flags);
+}
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
new file mode 100644
index 0000000..651b06f
--- /dev/null
+++ b/drivers/clk/clk-fixed-rate.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Fixed rate clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+/*
+ * DOC: basic fixed-rate clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parents are prepared
+ * enable - clk_enable only ensures parents are enabled
+ * rate - rate is always a fixed value.  No clk_set_rate support
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
+
+static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	return to_clk_fixed_rate(hw)->fixed_rate;
+}
+
+struct clk_ops clk_fixed_rate_ops = {
+	.recalc_rate = clk_fixed_rate_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
+
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		unsigned long fixed_rate)
+{
+	struct clk_fixed_rate *fixed;
+	char **parent_names = NULL;
+	u8 len;
+
+	fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
+
+	if (!fixed) {
+		pr_err("%s: could not allocate fixed clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_fixed_rate assignments */
+	fixed->fixed_rate = fixed_rate;
+
+	if (parent_name) {
+		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
+
+		if (! parent_names)
+			goto out;
+
+		len = sizeof(char) * strlen(parent_name);
+
+		parent_names[0] = kmalloc(len, GFP_KERNEL);
+
+		if (!parent_names[0])
+			goto out;
+
+		strncpy(parent_names[0], parent_name, len);
+	}
+
+out:
+	return clk_register(dev, name,
+			&clk_fixed_rate_ops, &fixed->hw,
+			parent_names,
+			(parent_name ? 1 : 0),
+			flags);
+}
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
new file mode 100644
index 0000000..e831f7b
--- /dev/null
+++ b/drivers/clk/clk-gate.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Gated clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+/**
+ * DOC: basic gatable clock which can gate and ungate it's ouput
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent are prepared
+ * enable - clk_enable and clk_disable are functional & control gating
+ * rate - inherits rate from parent.  No clk_set_rate support
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+
+static void clk_gate_set_bit(struct clk_gate *gate)
+{
+	u32 reg;
+
+	reg = readl(gate->reg);
+	reg |= BIT(gate->bit_idx);
+	writel(reg, gate->reg);
+}
+
+static void clk_gate_clear_bit(struct clk_gate *gate)
+{
+	u32 reg;
+
+	reg = readl(gate->reg);
+	reg &= ~BIT(gate->bit_idx);
+	writel(reg, gate->reg);
+}
+
+static int clk_gate_enable(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+
+	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+		clk_gate_clear_bit(gate);
+	else
+		clk_gate_set_bit(gate);
+
+	return 0;
+}
+
+static void clk_gate_disable(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+
+	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+		clk_gate_set_bit(gate);
+	else
+		clk_gate_clear_bit(gate);
+}
+
+struct clk_ops clk_gate_ops = {
+	.enable = clk_gate_enable,
+	.disable = clk_gate_disable,
+};
+EXPORT_SYMBOL_GPL(clk_gate_ops);
+
+struct clk *clk_register_gate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 bit_idx,
+		u8 clk_gate_flags, spinlock_t *lock)
+{
+	struct clk_gate *gate;
+	char **parent_names = NULL;
+	u8 len;
+
+	gate = kmalloc(sizeof(struct clk_gate), GFP_KERNEL);
+
+	if (!gate) {
+		pr_err("%s: could not allocate gated clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_gate assignments */
+	gate->reg = reg;
+	gate->bit_idx = bit_idx;
+	gate->flags = clk_gate_flags;
+	gate->lock = lock;
+
+	if (parent_name) {
+		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
+
+		if (! parent_names)
+			goto out;
+
+		len = sizeof(char) * strlen(parent_name);
+
+		parent_names[0] = kmalloc(len, GFP_KERNEL);
+
+		if (!parent_names[0])
+			goto out;
+
+		strncpy(parent_names[0], parent_name, len);
+	}
+
+out:
+	return clk_register(dev, name,
+			&clk_gate_ops, &gate->hw,
+			parent_names,
+			(parent_name ? 1 : 0),
+			flags);
+}
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
new file mode 100644
index 0000000..bb66f26
--- /dev/null
+++ b/drivers/clk/clk-mux.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Simple multiplexer clock implementation
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+/*
+ * DOC: basic adjustable multiplexer clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is only affected by parent switching.  No clk_set_rate support
+ * parent - parent is adjustable through clk_set_parent
+ */
+
+#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
+
+static u8 clk_mux_get_parent(struct clk_hw *hw)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	u32 val;
+
+	/*
+	 * FIXME need a mux-specific flag to determine if val is bitwise or numeric
+	 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
+	 * to 0x7 (index starts at one)
+	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
+	 * val = 0x4 really means "bit 2, index starts at bit 0"
+	 */
+	val = readl(mux->reg) >> mux->shift;
+	val &= (1 << mux->width) - 1;
+
+	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
+		val = ffs(val) - 1;
+
+	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
+		val--;
+
+	if (val >= __clk_get_num_parents(hw->clk))
+		return -EINVAL;
+
+	return val;
+}
+
+static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	u32 val;
+	unsigned long flags = 0;
+
+	if (mux->flags & CLK_MUX_INDEX_BIT)
+		index = (1 << ffs(index));
+
+	if (mux->flags & CLK_MUX_INDEX_ONE)
+		index++;
+
+	if (mux->lock)
+		spin_lock_irqsave(mux->lock, flags);
+
+	val = readl(mux->reg);
+	val &= ~(((1 << mux->width) - 1) << mux->shift);
+	val |= index << mux->shift;
+	writel(val, mux->reg);
+
+	if (mux->lock)
+		spin_unlock_irqrestore(mux->lock, flags);
+
+	return 0;
+}
+
+struct clk_ops clk_mux_ops = {
+	.get_parent = clk_mux_get_parent,
+	.set_parent = clk_mux_set_parent,
+};
+EXPORT_SYMBOL_GPL(clk_mux_ops);
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+		char **parent_names, u8 num_parents, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_mux_flags, spinlock_t *lock)
+{
+	struct clk_mux *mux;
+
+	mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL);
+
+	if (!mux) {
+		pr_err("%s: could not allocate mux clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_mux assignments */
+	mux->reg = reg;
+	mux->shift = shift;
+	mux->width = width;
+	mux->flags = clk_mux_flags;
+	mux->lock = lock;
+
+	return clk_register(dev, name, &clk_mux_ops, &mux->hw,
+			parent_names, num_parents, flags);
+}
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 33bf6a7..d06e6fb 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -45,6 +45,130 @@ struct clk {
 #endif
 };
 
+/*
+ * DOC: Basic clock implementations common to many platforms
+ *
+ * Each basic clock hardware type is comprised of a structure describing the
+ * clock hardware, implementations of the relevant callbacks in struct clk_ops,
+ * unique flags for that hardware type, a registration function and an
+ * alternative macro for static initialization
+ */
+
+extern struct clk_ops clk_fixed_rate_ops;
+
+#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate,		\
+				_fixed_rate_flags)		\
+	static struct clk _name;				\
+	static char *_name##_parent_names[] = {};		\
+	static struct clk_fixed_rate _name##_hw = {		\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.fixed_rate = _rate,				\
+		.flags = _fixed_rate_flags,			\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_fixed_rate_ops,			\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _name##_parent_names,		\
+		.num_parents =					\
+			ARRAY_SIZE(_name##_parent_names),	\
+		.flags = _flags,				\
+	};
+
+extern struct clk_ops clk_gate_ops;
+
+#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,	\
+				_flags, _reg, _bit_idx,		\
+				_gate_flags, _lock)		\
+	static struct clk _name;				\
+	static char *_name##_parent_names[] = {			\
+		_parent_name,					\
+	};							\
+	static struct clk *_name##_parents[] = {		\
+		_parent_ptr,					\
+	};							\
+	static struct clk_gate _name##_hw = {			\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.reg = _reg,					\
+		.bit_idx = _bit_idx,				\
+		.flags = _gate_flags				\
+		.lock = _lock,					\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_gate_ops,				\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _name##_parent_names,		\
+		.num_parents =					\
+			ARRAY_SIZE(_name##parent_names),	\
+		.parents = _name##_parents,			\
+		.flags = _flags,				\
+	};
+
+extern struct clk_ops clk_divider_ops;
+
+#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
+				_flags, _reg, _shift, _width,	\
+				_divider_flags, _lock)		\
+	static struct clk _name;				\
+	static char *_name##_parent_names[] = {			\
+		_parent_name,					\
+	};							\
+	static struct clk *_name##_parents[] = {		\
+		_parent_ptr,					\
+	};							\
+	static struct clk_divider _name##_hw = {		\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.reg = _reg,					\
+		.shift = _shift,				\
+		.width = _width,				\
+		.flags = _divider_flags,			\
+		.lock = _lock,					\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_divider_ops,			\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _name##_parent_names,		\
+		.num_parents =					\
+			ARRAY_SIZE(_name##_parent_names),	\
+		.parents = _name##_parents,			\
+		.flags = _flags,				\
+	};
+
+extern struct clk_ops clk_mux_ops;
+
+#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags,	\
+				_reg, _shift, _width,		\
+				_mux_flags, _lock)		\
+	static struct clk _name;				\
+	static struct clk_mux _name##_hw = {			\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.reg = _reg,					\
+		.shift = _shift,				\
+		.width = _width,				\
+		.flags = _mux_flags,				\
+		.lock = _lock,					\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_mux_ops,				\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _parent_names,			\
+		.num_parents =					\
+			ARRAY_SIZE(_parent_names),		\
+		.parents = _parents,				\
+		.flags = _flags,				\
+	};
+
 /**
  * __clk_init - initialize the data structures in a struct clk
  * @dev:	device initializing this clk, placeholder for now
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c9ed582..9b7dd5e 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -128,6 +128,131 @@ struct clk_ops {
 	void		(*init)(struct clk_hw *hw);
 };
 
+/*
+ * DOC: Basic clock implementations common to many platforms
+ *
+ * Each basic clock hardware type is comprised of a structure describing the
+ * clock hardware, implementations of the relevant callbacks in struct clk_ops,
+ * unique flags for that hardware type, a registration function and an
+ * alternative macro for static initialization
+ */
+
+/**
+ * struct clk_fixed_rate - fixed-rate clock
+ * @hw:		handle between common and hardware-specific interfaces
+ * @fixed_rate:	constant frequency of clock
+ */
+struct clk_fixed_rate {
+	struct		clk_hw hw;
+	unsigned long	fixed_rate;
+	u8		flags;
+};
+
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		unsigned long fixed_rate);
+
+/**
+ * struct clk_gate - gating clock
+ *
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register controlling gate
+ * @bit_idx:	single bit controlling gate
+ * @flags:	hardware-specific flags
+ * @lock:	register lock
+ *
+ * Clock which can gate its output.  Implements .enable & .disable
+ *
+ * Flags:
+ * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
+ * 	enable the clock.  Setting this flag does the opposite: setting the bit
+ * 	disable the clock and clearing it enables the clock
+ */
+struct clk_gate {
+	struct clk_hw hw;
+	void __iomem	*reg;
+	u8		bit_idx;
+	u8		flags;
+	spinlock_t	*lock;
+};
+
+#define CLK_GATE_SET_TO_DISABLE		BIT(0)
+
+struct clk *clk_register_gate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 bit_idx,
+		u8 clk_gate_flags, spinlock_t *lock);
+
+/**
+ * struct clk_divider - adjustable divider clock
+ *
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register containing the divider
+ * @shift:	shift to the divider bit field
+ * @width:	width of the divider bit field
+ * @lock:	register lock
+ *
+ * Clock with an adjustable divider affecting its output frequency.  Implements
+ * .recalc_rate, .set_rate and .round_rate
+ *
+ * Flags:
+ * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
+ * 	register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
+ * 	the raw value read from the register, with the value of zero considered
+ * 	invalid
+ * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
+ * 	the hardware register
+ */
+struct clk_divider {
+	struct clk_hw	hw;
+	void __iomem	*reg;
+	u8		shift;
+	u8		width;
+	u8		flags;
+	spinlock_t	*lock;
+};
+
+#define CLK_DIVIDER_ONE_BASED		BIT(0)
+#define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
+
+struct clk *clk_register_divider(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_divider_flags, spinlock_t *lock);
+
+/**
+ * struct clk_mux - multiplexer clock
+ *
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register controlling multiplexer
+ * @shift:	shift to multiplexer bit field
+ * @width:	width of mutliplexer bit field
+ * @num_clks:	number of parent clocks
+ * @lock:	register lock
+ *
+ * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
+ * and .recalc_rate
+ *
+ * Flags:
+ * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
+ * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two)
+ */
+struct clk_mux {
+	struct clk_hw	hw;
+	void __iomem	*reg;
+	u8		shift;
+	u8		width;
+	u8		flags;
+	spinlock_t	*lock;
+};
+
+#define CLK_MUX_INDEX_ONE		BIT(0)
+#define CLK_MUX_INDEX_BIT		BIT(1)
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+		char **parent_names, u8 num_parents, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_mux_flags, spinlock_t *lock);
 
 /**
  * clk_register - allocate a new clock, register it and return an opaque cookie
-- 
1.7.5.4



From linux at arm.linux.org.uk  Sat Mar  3 05:08:53 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 3 Mar 2012 10:08:53 +0000
Subject: [PATCH 5/5 v2] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <201203021832.34901.arnd@arndb.de>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <e2fe5e97a83fc753559bbb18d5d111ed01b89034.1330709314.git.jason@lakedaemon.net>
 <201203021832.34901.arnd@arndb.de>
Message-ID: <20120303100853.GK7363@n2100.arm.linux.org.uk>

On Fri, Mar 02, 2012 at 06:32:33PM +0000, Arnd Bergmann wrote:
> On Friday 02 March 2012, Jason Cooper wrote:
> > +       wdt_reg = (void __iomem *)TIMER_VIRT_BASE;
> > +
> > +       ret = of_address_to_resource(np, 0, &res);
> > +       if (ret) {
> > +               printk(KERN_ERR "invalid address\n");
> > +               return ret;
> > +       }
> > +
> > +       wdt_reg = ioremap(res.start, res.end - res.start);
> > +
> 
> This will break non-dt uses because you overwrite the wdt_reg value.

Don't also forget that "res.end - res.start" is also not correct, and
resource_size() should be used to prevent that kind of error.


From s.hauer at pengutronix.de  Sat Mar  3 06:40:03 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat,  3 Mar 2012 12:40:03 +0100
Subject: [PATCH 3/4] ARM i.MX pcm037: register a dummy regulator for the
 smsc911x device
In-Reply-To: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1330774804-7310-4-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/mach-pcm037.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index e48854b..5fddf94 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -32,6 +32,8 @@
 #include <linux/usb/ulpi.h>
 #include <linux/gfp.h>
 #include <linux/memblock.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
 
 #include <media/soc_camera.h>
 
@@ -570,6 +572,11 @@ static int __init pcm037_otg_mode(char *options)
 }
 __setup("otg_mode=", pcm037_otg_mode);
 
+static struct regulator_consumer_supply dummy_supplies[] = {
+	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+	REGULATOR_SUPPLY("vddvario", "smsc911x"),
+};
+
 /*
  * Board specific initialization.
  */
@@ -579,6 +586,8 @@ static void __init pcm037_init(void)
 
 	imx31_soc_init();
 
+	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
 	mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
 
 	mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
-- 
1.7.9.1



From s.hauer at pengutronix.de  Sat Mar  3 06:40:02 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat,  3 Mar 2012 12:40:02 +0100
Subject: [PATCH 2/4] regulator: provide a helper for registering a fixed
 regulator
In-Reply-To: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1330774804-7310-3-git-send-email-s.hauer@pengutronix.de>

Some devices require a regulator to work, but boards may not have
a software controllable regulator for this device. Provide a helper
function to make it simpler for these boards to register a fixed
regulator as a dummy regulator.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/regulator/Makefile       |    2 +-
 drivers/regulator/fixed-helper.c |   53 ++++++++++++++++++++++++++++++++++++++
 include/linux/regulator/fixed.h  |   13 +++++++++
 3 files changed, 67 insertions(+), 1 deletions(-)
 create mode 100644 drivers/regulator/fixed-helper.c

diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 503bac8..f76deb9 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -3,7 +3,7 @@
 #
 
 
-obj-$(CONFIG_REGULATOR) += core.o dummy.o
+obj-$(CONFIG_REGULATOR) += core.o dummy.o fixed-helper.o
 obj-$(CONFIG_OF) += of_regulator.o
 obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o
 obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o
diff --git a/drivers/regulator/fixed-helper.c b/drivers/regulator/fixed-helper.c
new file mode 100644
index 0000000..30d0a15
--- /dev/null
+++ b/drivers/regulator/fixed-helper.c
@@ -0,0 +1,53 @@
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+
+struct fixed_regulator_data {
+	struct fixed_voltage_config cfg;
+	struct regulator_init_data init_data;
+	struct platform_device pdev;
+};
+
+static void regulator_fixed_release(struct device *dev)
+{
+	struct fixed_regulator_data *data = container_of(dev,
+			struct fixed_regulator_data, pdev.dev);
+	kfree(data);
+}
+
+/**
+ * regulator_register_fixed - register a no-op fixed regulator
+ * @name: supply name
+ * @id: platform device id
+ * @supplies: consumers for this regulator
+ * @num_supplies: number of consumers
+ */
+struct platform_device *regulator_register_fixed(int id,
+		struct regulator_consumer_supply *supplies, int num_supplies)
+{
+	struct fixed_regulator_data *data;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return NULL;
+
+	data->cfg.supply_name = "dummy";
+	data->cfg.microvolts = 0;
+	data->cfg.gpio = -EINVAL;
+	data->cfg.enabled_at_boot = 1;
+	data->cfg.init_data = &data->init_data;
+
+	data->init_data.constraints.always_on = 1;
+	data->init_data.consumer_supplies = supplies;
+	data->init_data.num_consumer_supplies = num_supplies;
+
+	data->pdev.name = "reg-fixed-voltage";
+	data->pdev.id = id;
+	data->pdev.dev.platform_data = &data->cfg;
+	data->pdev.dev.release = regulator_fixed_release;
+
+	platform_device_register(&data->pdev);
+
+	return &data->pdev;
+}
diff --git a/include/linux/regulator/fixed.h b/include/linux/regulator/fixed.h
index ffd7d50..936a7d8 100644
--- a/include/linux/regulator/fixed.h
+++ b/include/linux/regulator/fixed.h
@@ -48,4 +48,17 @@ struct fixed_voltage_config {
 	struct regulator_init_data *init_data;
 };
 
+struct regulator_consumer_supply;
+
+#if IS_ENABLED(CONFIG_REGULATOR)
+struct platform_device *regulator_register_fixed(int id,
+		struct regulator_consumer_supply *supplies, int num_supplies);
+#else
+static inline struct platform_device *regulator_register_fixed(int id,
+		struct regulator_consumer_supply *supplies, int num_supplies)
+{
+	return NULL;
+}
+#endif
+
 #endif
-- 
1.7.9.1



From s.hauer at pengutronix.de  Sat Mar  3 06:40:00 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat,  3 Mar 2012 12:40:00 +0100
Subject: [PATCH] Add helper for registering a fixed regulator
Message-ID: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>


Hi,

The following adds a helper for registering a fixed dummy regulator
making it simple for boards which have no software controllable regulator
for certain devices to register a fixed regulator as a dummy.

The last two patches make smsc911x ethernet functional again which
broke when the smsc911x driver gained regulator support.

Sascha

----------------------------------------------------------------
Sascha Hauer (4):
      regulator fixed: Do not report enumaratable voltages if there are none
      regulator: provide a helper for registering a fixed regulator
      ARM i.MX pcm037: register a dummy regulator for the smsc911x device
      ARM i.MX 3ds debugboard: register a dummy regulator for the smsc911x device

 arch/arm/mach-imx/mach-pcm037.c    |    9 ++++++
 arch/arm/plat-mxc/3ds_debugboard.c |    9 ++++++
 drivers/regulator/Makefile         |    2 +-
 drivers/regulator/fixed-helper.c   |   53 ++++++++++++++++++++++++++++++++++++
 drivers/regulator/fixed.c          |    4 ++-
 include/linux/regulator/fixed.h    |   13 +++++++++
 6 files changed, 88 insertions(+), 2 deletions(-)
 create mode 100644 drivers/regulator/fixed-helper.c


From s.hauer at pengutronix.de  Sat Mar  3 06:40:01 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat,  3 Mar 2012 12:40:01 +0100
Subject: [PATCH 1/4] regulator fixed: Do not report enumaratable voltages if
 there are none
In-Reply-To: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1330774804-7310-2-git-send-email-s.hauer@pengutronix.de>

If used as a dummy voltage provider the fixed regulator should
not set n_voltages to make the core accept the device.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/regulator/fixed.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c
index e24e3a1..40f3803 100644
--- a/drivers/regulator/fixed.c
+++ b/drivers/regulator/fixed.c
@@ -192,7 +192,9 @@ static int __devinit reg_fixed_voltage_probe(struct platform_device *pdev)
 	drvdata->desc.type = REGULATOR_VOLTAGE;
 	drvdata->desc.owner = THIS_MODULE;
 	drvdata->desc.ops = &fixed_voltage_ops;
-	drvdata->desc.n_voltages = 1;
+
+	if (config->microvolts)
+		drvdata->desc.n_voltages = 1;
 
 	drvdata->microvolts = config->microvolts;
 	drvdata->gpio = config->gpio;
-- 
1.7.9.1



From s.hauer at pengutronix.de  Sat Mar  3 06:40:04 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat,  3 Mar 2012 12:40:04 +0100
Subject: [PATCH 4/4] ARM i.MX 3ds debugboard: register a dummy regulator for
 the smsc911x device
In-Reply-To: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1330774804-7310-5-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/plat-mxc/3ds_debugboard.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index f0ba072..d1e31fa 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -16,6 +16,8 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/smsc911x.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
 
 #include <mach/hardware.h>
 
@@ -148,6 +150,11 @@ static struct irq_chip expio_irq_chip = {
 	.irq_unmask = expio_unmask_irq,
 };
 
+static struct regulator_consumer_supply dummy_supplies[] = {
+	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+	REGULATOR_SUPPLY("vddvario", "smsc911x"),
+};
+
 int __init mxc_expio_init(u32 base, u32 p_irq)
 {
 	int i;
@@ -188,6 +195,8 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
 	irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
 
 	/* Register Lan device on the debugboard */
+	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
 	smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
 	smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
 	platform_device_register(&smsc_lan9217_device);
-- 
1.7.9.1



From broonie at opensource.wolfsonmicro.com  Sat Mar  3 07:56:53 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 3 Mar 2012 12:56:53 +0000
Subject: [PATCH 1/4] regulator fixed: Do not report enumaratable voltages
 if there are none
In-Reply-To: <1330774804-7310-2-git-send-email-s.hauer@pengutronix.de>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
 <1330774804-7310-2-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120303125652.GA16289@opensource.wolfsonmicro.com>

On Sat, Mar 03, 2012 at 12:40:01PM +0100, Sascha Hauer wrote:
> If used as a dummy voltage provider the fixed regulator should
> not set n_voltages to make the core accept the device.

Applied, thanks.
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From s.hauer at pengutronix.de  Sat Mar  3 08:31:58 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat, 3 Mar 2012 14:31:58 +0100
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <1330763341-3437-4-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
Message-ID: <20120303133158.GA26882@pengutronix.de>

On Sat, Mar 03, 2012 at 12:29:00AM -0800, Mike Turquette wrote:
> The common clock framework defines a common struct clk useful across
> most platforms as well as an implementation of the clk api that drivers
> can use safely for managing clocks.
> 
> The net result is consolidation of many different struct clk definitions
> and platform-specific clock framework implementations.
> 
> This patch introduces the common struct clk, struct clk_ops and an
> implementation of the well-known clock api in include/clk/clk.h.
> Platforms may define their own hardware-specific clock structure and
> their own clock operation callbacks, so long as it wraps an instance of
> struct clk_hw.
> 
> See Documentation/clk.txt for more details.
> 
> This patch is based on the work of Jeremy Kerr, which in turn was based
> on the work of Ben Herrenschmidt.
> 
> +
> +/**
> + * struct clk_hw - handle for traversing from a struct clk to its corresponding
> + * hardware-specific structure.  struct clk_hw should be declared within struct
> + * clk_foo and then referenced by the struct clk instance that uses struct
> + * clk_foo's clk_ops
> + *
> + * clk: pointer to the struct clk instance that points back to this struct
> + * clk_hw instance
> + */
> +struct clk_hw {
> +	struct clk *clk;
> +};

The reason for doing this is that struct clk should be an opaque cookie
for both drivers and implementers of clocks. I recently had the idea whether
the roles of these two structs could be swapped. So instead of the above we
could do:

struct clk {
	struct clk_hw *hw;
}

The effect would be the same, but this version would make the struct clk
pointer known at compile time thus making it possible for static
initializers to specify their parent clock.

I just saw that clk_register now takes a parent name array, that may
make this change unnecessary anyway.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From shawn.guo at linaro.org  Sat Mar  3 10:19:41 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:41 +0800
Subject: [PATCH 00/20] ASoC: add imx-sgtl5000 machine driver working with
 fsl_ssi
Message-ID: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>

It's the full series adding imx-sgtl5000 machine driver which works
with fsl_ssi driver on DT based imx platforms.
 - Patches 1 ~ 5: Convert audmux driver to a platform driver and move
   it into ASoC folder.
 - Patches 6 ~ 12: Merge ASoC imx and fsl folders.
 - Patches 13 ~17: Make fsl_ssi work for imx.
 - Patches 18 ~ 20: Add imx-sgtl5000 machine driver which supports
   DT only.

It's based on sound/for-next and tested on imx51-babbage board with
necessary platform/dts changes, which will be posted separately after
the ASoC changes get merged.

Regards,
Shawn

Richard Zhao (2):
      ARM: imx: convert audmux to a platform driver
      ASoC: fsl: add dt support for imx-audmux

Shawn Guo (18):
      ASoC: imx: move eukrea audmux call into ASoC machine driver
      ASoC: imx: move phycore audmux call into ASoC machine driver
      ARM: imx: merge audmux-v1 and audmux-v2
      ASoC: imx: move audmux driver into sound/soc/imx
      ASoC: imx: rename audmux prefix mxc to imx
      ASoC: imx: move SND_SOC_AC97_BUS selection down to machine driver
      ASoC: imx: initialize dma_params burstsize just in imx-ssi
      ASoC: imx: separate imx-pcm bits from imx-ssi driver
      ASoC: imx: add an explicit Kconfig option for imx-ssi driver
      ASoC: fsl: separate SSI and DMA Kconfig options
      ASoC: imx: merge sound/soc/imx into sound/soc/fsl
      ASoC: fsl: create fsl_utils to accommodate the common functions
      ASoC: fsl: check property 'compatible' for the machine name
      ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
      ASoC: fsl: remove the fatal error checking on codec-handle
      ASoC: fsl: let fsl_ssi work with imx pcm and machine drivers
      ASoC: rename sgtl5000 device tree binding document
      ASoC: fsl: add imx-sgtl5000 machine driver

 .../bindings/sound/imx-audio-sgtl5000.txt          |   24 +++
 .../devicetree/bindings/sound/imx-audmux.txt       |   13 ++
 .../{soc/codecs/fsl-sgtl5000.txt => sgtl5000.txt}  |    0
 arch/arm/mach-imx/Kconfig                          |    6 -
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c       |   27 +--
 arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c       |    1 -
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c     |   24 +--
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c     |   24 +--
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c        |    7 +
 arch/arm/mach-imx/mach-mx31ads.c                   |    6 +
 arch/arm/mach-imx/mach-pca100.c                    |   20 +--
 arch/arm/mach-imx/mach-pcm043.c                    |   20 +--
 arch/arm/plat-mxc/Kconfig                          |    6 -
 arch/arm/plat-mxc/Makefile                         |    2 -
 arch/arm/plat-mxc/audmux-v1.c                      |   64 ------
 arch/arm/plat-mxc/include/mach/audmux.h            |   60 ------
 sound/soc/Kconfig                                  |    1 -
 sound/soc/Makefile                                 |    1 -
 sound/soc/fsl/Kconfig                              |  124 +++++++++++-
 sound/soc/fsl/Makefile                             |   29 +++-
 sound/soc/{imx => fsl}/eukrea-tlv320.c             |   42 ++++-
 sound/soc/fsl/fsl_ssi.c                            |  146 ++++++++++----
 sound/soc/fsl/fsl_utils.c                          |  135 +++++++++++++
 sound/soc/fsl/fsl_utils.h                          |   27 +++
 .../audmux-v2.c => sound/soc/fsl/imx-audmux.c      |  185 +++++++++++++-----
 sound/soc/fsl/imx-audmux.h                         |   60 ++++++
 sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c           |    7 +-
 sound/soc/{imx => fsl}/imx-pcm-fiq.c               |    0
 sound/soc/fsl/imx-pcm.c                            |  105 ++++++++++
 sound/soc/fsl/imx-pcm.h                            |   32 +++
 sound/soc/fsl/imx-sgtl5000.c                       |  210 ++++++++++++++++++++
 sound/soc/{imx => fsl}/imx-ssi.c                   |   92 +---------
 sound/soc/{imx => fsl}/imx-ssi.h                   |   16 +--
 sound/soc/fsl/mpc8610_hpcd.c                       |  159 ++--------------
 sound/soc/{imx => fsl}/mx27vis-aic32x4.c           |   20 +-
 sound/soc/fsl/p1022_ds.c                           |  181 ++----------------
 sound/soc/{imx => fsl}/phycore-ac97.c              |   27 +++-
 sound/soc/{imx => fsl}/wm1133-ev1.c                |   25 ++--
 sound/soc/imx/Kconfig                              |   60 ------
 sound/soc/imx/Makefile                             |   19 --
 40 files changed, 1163 insertions(+), 844 deletions(-)


From shawn.guo at linaro.org  Sat Mar  3 10:19:42 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:42 +0800
Subject: [PATCH 01/20] ASoC: imx: move eukrea audmux call into ASoC machine
 driver
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-2-git-send-email-shawn.guo@linaro.org>

It moves eukrea audmux configuration call from board file into ASoC
machine driver eukrea-tlv320, so that it gets aligned wm1133-ev1 and
mx27vis-aic32x4, and more importantly it will ease the moving of audmux
into sound/soc/imx as a platform driver later.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c   |   20 ------------
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c |   17 ----------
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c |   17 ----------
 sound/soc/imx/eukrea-tlv320.c                  |   40 +++++++++++++++++++++--
 4 files changed, 36 insertions(+), 58 deletions(-)

diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 5db3e14..5f2f91d 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -32,7 +32,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx27.h>
 #include <mach/hardware.h>
-#include <mach/audmux.h>
 
 #include "devices-imx27.h"
 
@@ -306,25 +305,6 @@ void __init eukrea_mbimx27_baseboard_init(void)
 	mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
 		ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
 
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
-	|| defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
-	/* SSI unit master I2S codec connected to SSI_PINS_4*/
-	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_TFSDIR |
-			MXC_AUDMUX_V1_PCR_TCLKDIR |
-			MXC_AUDMUX_V1_PCR_RFSDIR |
-			MXC_AUDMUX_V1_PCR_RCLKDIR |
-			MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
-			MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
-	);
-	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
-	);
-#endif
-
 	imx27_add_imx_uart1(&uart_pdata);
 	imx27_add_imx_uart2(&uart_pdata);
 #if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 66e8726..2cf603e 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -31,7 +31,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/mx25.h>
-#include <mach/audmux.h>
 
 #include "devices-imx25.h"
 
@@ -241,22 +240,6 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
 			ARRAY_SIZE(eukrea_mbimxsd_pads)))
 		printk(KERN_ERR "error setting mbimxsd pads !\n");
 
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
-	/* SSI unit master I2S codec connected to SSI_AUD5*/
-	mxc_audmux_v2_configure_port(0,
-			MXC_AUDMUX_V2_PTCR_SYN |
-			MXC_AUDMUX_V2_PTCR_TFSDIR |
-			MXC_AUDMUX_V2_PTCR_TFSEL(4) |
-			MXC_AUDMUX_V2_PTCR_TCLKDIR |
-			MXC_AUDMUX_V2_PTCR_TCSEL(4),
-			MXC_AUDMUX_V2_PDCR_RXDSEL(4)
-	);
-	mxc_audmux_v2_configure_port(4,
-			MXC_AUDMUX_V2_PTCR_SYN,
-			MXC_AUDMUX_V2_PDCR_RXDSEL(0)
-	);
-#endif
-
 	imx25_add_imx_uart1(&uart_pdata);
 	imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
 	imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 0f0af02..fd8bf8a 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -38,7 +38,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
-#include <mach/audmux.h>
 
 #include "devices-imx35.h"
 
@@ -252,22 +251,6 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
 			ARRAY_SIZE(eukrea_mbimxsd_pads)))
 		printk(KERN_ERR "error setting mbimxsd pads !\n");
 
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
-	/* SSI unit master I2S codec connected to SSI_AUD4 */
-	mxc_audmux_v2_configure_port(0,
-			MXC_AUDMUX_V2_PTCR_SYN |
-			MXC_AUDMUX_V2_PTCR_TFSDIR |
-			MXC_AUDMUX_V2_PTCR_TFSEL(3) |
-			MXC_AUDMUX_V2_PTCR_TCLKDIR |
-			MXC_AUDMUX_V2_PTCR_TCSEL(3),
-			MXC_AUDMUX_V2_PDCR_RXDSEL(3)
-	);
-	mxc_audmux_v2_configure_port(3,
-			MXC_AUDMUX_V2_PTCR_SYN,
-			MXC_AUDMUX_V2_PDCR_RXDSEL(0)
-	);
-#endif
-
 	imx35_add_imx_uart1(&uart_pdata);
 	imx35_add_ipu_core(&mx3_ipu_data);
 	imx35_add_mx3_sdc_fb(&mx3fb_pdata);
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/imx/eukrea-tlv320.c
index 1c1fdd1..bfcb6d9 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/imx/eukrea-tlv320.c
@@ -23,6 +23,7 @@
 #include <sound/pcm.h>
 #include <sound/soc.h>
 #include <asm/mach-types.h>
+#include <mach/audmux.h>
 
 #include "../codecs/tlv320aic23.h"
 #include "imx-ssi.h"
@@ -97,12 +98,43 @@ static struct platform_device *eukrea_tlv320_snd_device;
 static int __init eukrea_tlv320_init(void)
 {
 	int ret;
-
-	if (!machine_is_eukrea_cpuimx27() && !machine_is_eukrea_cpuimx25sd()
-		&& !machine_is_eukrea_cpuimx35sd()
-		&& !machine_is_eukrea_cpuimx51sd())
+	int int_port = 0, ext_port;
+
+	if (machine_is_eukrea_cpuimx27()) {
+		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+			MXC_AUDMUX_V1_PCR_SYN |
+			MXC_AUDMUX_V1_PCR_TFSDIR |
+			MXC_AUDMUX_V1_PCR_TCLKDIR |
+			MXC_AUDMUX_V1_PCR_RFSDIR |
+			MXC_AUDMUX_V1_PCR_RCLKDIR |
+			MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+			MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
+		);
+		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
+			MXC_AUDMUX_V1_PCR_SYN |
+			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+		);
+	} else if (machine_is_eukrea_cpuimx25sd() ||
+		   machine_is_eukrea_cpuimx35sd() ||
+		   machine_is_eukrea_cpuimx51sd()) {
+		ext_port = machine_is_eukrea_cpuimx25sd() ? 4 : 3;
+		mxc_audmux_v2_configure_port(int_port,
+			MXC_AUDMUX_V2_PTCR_SYN |
+			MXC_AUDMUX_V2_PTCR_TFSDIR |
+			MXC_AUDMUX_V2_PTCR_TFSEL(ext_port) |
+			MXC_AUDMUX_V2_PTCR_TCLKDIR |
+			MXC_AUDMUX_V2_PTCR_TCSEL(ext_port),
+			MXC_AUDMUX_V2_PDCR_RXDSEL(ext_port)
+		);
+		mxc_audmux_v2_configure_port(ext_port,
+			MXC_AUDMUX_V2_PTCR_SYN,
+			MXC_AUDMUX_V2_PDCR_RXDSEL(int_port)
+		);
+	} else {
 		/* return happy. We might run on a totally different machine */
 		return 0;
+	}
 
 	eukrea_tlv320_snd_device = platform_device_alloc("soc-audio", -1);
 	if (!eukrea_tlv320_snd_device)
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:43 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:43 +0800
Subject: [PATCH 02/20] ASoC: imx: move phycore audmux call into ASoC machine
 driver
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-3-git-send-email-shawn.guo@linaro.org>

It moves phycore audmux configuration call from board file into ASoC
machine driver phycore-ac97 to ease converting audmux into a platform
driver later.
It moves phycore audmux configuration call from board file into ASoC
machine driver phycore-ac97, so that it gets aligned with wm1133-ev1
and mx27vis-aic32x4, and more importantly it will ease the moving of
audmux into sound/soc/imx as a platform driver later.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/mach-pca100.c |   13 -------------
 arch/arm/mach-imx/mach-pcm043.c |   13 -------------
 sound/soc/imx/phycore-ac97.c    |   26 +++++++++++++++++++++++++-
 3 files changed, 25 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index d3b9c6b..541152e 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,7 +36,6 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
 #include <asm/mach/time.h>
-#include <mach/audmux.h>
 #include <mach/irqs.h>
 #include <mach/ulpi.h>
 
@@ -359,18 +358,6 @@ static void __init pca100_init(void)
 
 	imx27_soc_init();
 
-	/* SSI unit */
-	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-				  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-				  MXC_AUDMUX_V1_PCR_TFCSEL(3) |
-				  MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
-				  MXC_AUDMUX_V1_PCR_RXDSEL(3));
-	mxc_audmux_v1_configure_port(3,
-				  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-				  MXC_AUDMUX_V1_PCR_TFCSEL(0) |
-				  MXC_AUDMUX_V1_PCR_TFSDIR |
-				  MXC_AUDMUX_V1_PCR_RXDSEL(0));
-
 	ret = mxc_gpio_setup_multiple_pins(pca100_pins,
 			ARRAY_SIZE(pca100_pins), "PCA100");
 	if (ret)
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 06dc106..237474f 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -37,7 +37,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
 #include <mach/ulpi.h>
-#include <mach/audmux.h>
 
 #include "devices-imx35.h"
 
@@ -362,18 +361,6 @@ static void __init pcm043_init(void)
 
 	mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
 
-	mxc_audmux_v2_configure_port(3,
-			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V2_PTCR_TFSEL(0) |
-			MXC_AUDMUX_V2_PTCR_TFSDIR,
-			MXC_AUDMUX_V2_PDCR_RXDSEL(0));
-
-	mxc_audmux_v2_configure_port(0,
-			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V2_PTCR_TCSEL(3) |
-			MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
-			MXC_AUDMUX_V2_PDCR_RXDSEL(3));
-
 	imx35_add_fec(NULL);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 	imx35_add_imx2_wdt(NULL);
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/imx/phycore-ac97.c
index 6ac1211..a59692e 100644
--- a/sound/soc/imx/phycore-ac97.c
+++ b/sound/soc/imx/phycore-ac97.c
@@ -18,6 +18,7 @@
 #include <sound/pcm.h>
 #include <sound/soc.h>
 #include <asm/mach-types.h>
+#include <mach/audmux.h>
 
 static struct snd_soc_card imx_phycore;
 
@@ -50,9 +51,32 @@ static int __init imx_phycore_init(void)
 {
 	int ret;
 
-	if (!machine_is_pcm043() && !machine_is_pca100())
+	if (machine_is_pca100()) {
+		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+			MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+			MXC_AUDMUX_V1_PCR_TFCSEL(3) |
+			MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
+			MXC_AUDMUX_V1_PCR_RXDSEL(3));
+		mxc_audmux_v1_configure_port(3,
+			MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+			MXC_AUDMUX_V1_PCR_TFCSEL(0) |
+			MXC_AUDMUX_V1_PCR_TFSDIR |
+			MXC_AUDMUX_V1_PCR_RXDSEL(0));
+	} else if (machine_is_pcm043()) {
+		mxc_audmux_v2_configure_port(3,
+			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+			MXC_AUDMUX_V2_PTCR_TFSEL(0) |
+			MXC_AUDMUX_V2_PTCR_TFSDIR,
+			MXC_AUDMUX_V2_PDCR_RXDSEL(0));
+		mxc_audmux_v2_configure_port(0,
+			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+			MXC_AUDMUX_V2_PTCR_TCSEL(3) |
+			MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
+			MXC_AUDMUX_V2_PDCR_RXDSEL(3));
+	} else {
 		/* return happy. We might run on a totally different machine */
 		return 0;
+	}
 
 	imx_phycore_snd_ac97_device = platform_device_alloc("soc-audio", -1);
 	if (!imx_phycore_snd_ac97_device)
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:44 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:44 +0800
Subject: [PATCH 03/20] ARM: imx: merge audmux-v1 and audmux-v2
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-4-git-send-email-shawn.guo@linaro.org>

It merges audmux-v1 and audmux-v2 under arch/arm/plat-mxc into one.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/Kconfig                   |   12 +++---
 arch/arm/plat-mxc/Kconfig                   |    5 +--
 arch/arm/plat-mxc/Makefile                  |    3 +-
 arch/arm/plat-mxc/audmux-v1.c               |   64 ---------------------------
 arch/arm/plat-mxc/{audmux-v2.c => audmux.c} |   29 +++++++++++-
 5 files changed, 34 insertions(+), 79 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/audmux-v1.c
 rename arch/arm/plat-mxc/{audmux-v2.c => audmux.c} (89%)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4defb97..495a854 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -46,7 +46,7 @@ config SOC_IMX21
 	bool
 	select MACH_MX21
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX_V1
+	select ARCH_MXC_AUDMUX
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
@@ -55,7 +55,7 @@ config SOC_IMX25
 	bool
 	select ARCH_MX25
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX_V2
+	select ARCH_MXC_AUDMUX
 	select ARCH_MXC_IOMUX_V3
 	select MXC_AVIC
 
@@ -63,7 +63,7 @@ config SOC_IMX27
 	bool
 	select MACH_MX27
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX_V1
+	select ARCH_MXC_AUDMUX
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
@@ -72,7 +72,7 @@ config SOC_IMX31
 	bool
 	select CPU_V6
 	select IMX_HAVE_PLATFORM_MXC_RNGA
-	select ARCH_MXC_AUDMUX_V2
+	select ARCH_MXC_AUDMUX
 	select MXC_AVIC
 	select SMP_ON_UP if SMP
 
@@ -80,7 +80,7 @@ config SOC_IMX35
 	bool
 	select CPU_V6
 	select ARCH_MXC_IOMUX_V3
-	select ARCH_MXC_AUDMUX_V2
+	select ARCH_MXC_AUDMUX
 	select HAVE_EPIT
 	select MXC_AVIC
 	select SMP_ON_UP if SMP
@@ -89,7 +89,7 @@ config SOC_IMX5
 	select CPU_V7
 	select MXC_TZIC
 	select ARCH_MXC_IOMUX_V3
-	select ARCH_MXC_AUDMUX_V2
+	select ARCH_MXC_AUDMUX
 	select ARCH_HAS_CPUFREQ
 	select ARCH_MX5
 	bool
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index dcebb12..0461d16 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -88,10 +88,7 @@ config IMX_HAVE_IOMUX_V1
 config ARCH_MXC_IOMUX_V3
 	bool
 
-config ARCH_MXC_AUDMUX_V1
-	bool
-
-config ARCH_MXC_AUDMUX_V2
+config ARCH_MXC_AUDMUX
 	bool
 
 config IRAM_ALLOC
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 076db84f..530c81d 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -14,8 +14,7 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
-obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
-obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+obj-$(CONFIG_ARCH_MXC_AUDMUX) += audmux.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
 ifdef CONFIG_SND_IMX_SOC
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
deleted file mode 100644
index 1180bef..0000000
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer at pengutronix.de>
- *
- * Initial development of this code was funded by
- * Phytec Messtechnik GmbH, http://www.phytec.de
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <mach/audmux.h>
-#include <mach/hardware.h>
-
-static void __iomem *audmux_base;
-
-static unsigned char port_mapping[] = {
-	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
-};
-
-int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
-{
-	if (!audmux_base) {
-		printk("%s: not configured\n", __func__);
-		return -ENOSYS;
-	}
-
-	if (port >= ARRAY_SIZE(port_mapping))
-		return -EINVAL;
-
-	writel(pcr, audmux_base + port_mapping[port]);
-
-	return 0;
-}
-EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
-
-static int mxc_audmux_v1_init(void)
-{
-#ifdef CONFIG_MACH_MX21
-	if (cpu_is_mx21())
-		audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR);
-	else
-#endif
-#ifdef CONFIG_MACH_MX27
-	if (cpu_is_mx27())
-		audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR);
-	else
-#endif
-		(void)0;
-	
-	return 0;
-}
-
-postcore_initcall(mxc_audmux_v1_init);
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux.c
similarity index 89%
rename from arch/arm/plat-mxc/audmux-v2.c
rename to arch/arm/plat-mxc/audmux.c
index 8cced35..f6dc536 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux.c
@@ -165,6 +165,24 @@ static inline void audmux_debugfs_init(void)
 }
 #endif
 
+static unsigned char port_mapping[] = {
+	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
+};
+
+int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
+{
+	if (!audmux_base)
+		return -ENOSYS;
+
+	if (port >= ARRAY_SIZE(port_mapping))
+		return -EINVAL;
+
+	writel(pcr, audmux_base + port_mapping[port]);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
+
 int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 		unsigned int pdcr)
 {
@@ -184,7 +202,7 @@ int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 }
 EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
 
-static int mxc_audmux_v2_init(void)
+static int mxc_audmux_init(void)
 {
 	int ret;
 	if (cpu_is_mx51()) {
@@ -209,11 +227,16 @@ static int mxc_audmux_v2_init(void)
 			return ret;
 		}
 		audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
+	} else if (cpu_is_mx27()) {
+		audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR);
+	} else if (cpu_is_mx21()) {
+		audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR);
 	}
 
-	audmux_debugfs_init();
+	if (!cpu_is_mx2())
+		audmux_debugfs_init();
 
 	return 0;
 }
 
-postcore_initcall(mxc_audmux_v2_init);
+postcore_initcall(mxc_audmux_init);
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:45 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:45 +0800
Subject: [PATCH 04/20] ARM: imx: convert audmux to a platform driver
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-5-git-send-email-shawn.guo@linaro.org>

From: Richard Zhao <richard.zhao at linaro.org>

It coverts audmux to a platform driver, so that it can be moved into
sound/soc/imx and adopt device tree support later.

Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c   |    7 ++
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c |    7 ++
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c |    7 ++
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c    |    7 ++
 arch/arm/mach-imx/mach-mx31ads.c               |    6 +
 arch/arm/mach-imx/mach-pca100.c                |    7 ++
 arch/arm/mach-imx/mach-pcm043.c                |    7 ++
 arch/arm/plat-mxc/audmux.c                     |  127 +++++++++++++++++-------
 8 files changed, 140 insertions(+), 35 deletions(-)

diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 5f2f91d..11cd0a0 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -294,6 +294,10 @@ struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = {
 	.flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
 };
 
+static const struct resource audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K),
+};
+
 /*
  * system init for baseboard usage. Will be called by cpuimx27 init.
  *
@@ -317,6 +321,9 @@ void __init eukrea_mbimx27_baseboard_init(void)
 	i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
 				ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
 
+	/* imx27 has the imx21 version audmux */
+	imx_add_platform_device("imx21-audmux", 0, audmux_res,
+				ARRAY_SIZE(audmux_res), NULL, 0);
 	imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata);
 
 #if defined(CONFIG_TOUCHSCREEN_ADS7846) \
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 2cf603e..2797da8 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -222,6 +222,10 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
 	.flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
 };
 
+static const struct resource audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 static struct esdhc_platform_data sd1_pdata = {
 	.cd_gpio = GPIO_SD1CD,
 	.cd_type = ESDHC_CD_GPIO,
@@ -242,6 +246,9 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
 
 	imx25_add_imx_uart1(&uart_pdata);
 	imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
+	/* imx25 has the imx31 version audmux */
+	imx_add_platform_device("imx31-audmux", 0, audmux_res,
+				ARRAY_SIZE(audmux_res), NULL, 0);
 	imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
 
 	imx25_add_flexcan1(NULL);
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index fd8bf8a..1878114 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -233,6 +233,10 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
 	.flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
 };
 
+static const struct resource audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 static struct esdhc_platform_data sd1_pdata = {
 	.cd_gpio = GPIO_SD1CD,
 	.cd_type = ESDHC_CD_GPIO,
@@ -255,6 +259,9 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
 	imx35_add_ipu_core(&mx3_ipu_data);
 	imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 
+	/* imx35 has the imx31 version audmux */
+	imx_add_platform_device("imx31-audmux", 0, audmux_res,
+				ARRAY_SIZE(audmux_res), NULL, 0);
 	imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
 
 	imx35_add_flexcan1(NULL);
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index c2766ae..8f03235 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -240,6 +240,10 @@ static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
 	.flags			= IMX_SSI_DMA | IMX_SSI_SYN,
 };
 
+static const struct resource audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K),
+};
+
 static void __init visstrim_m10_board_init(void)
 {
 	int ret;
@@ -251,6 +255,9 @@ static void __init visstrim_m10_board_init(void)
 	if (ret)
 		pr_err("Failed to setup pins (%d)\n", ret);
 
+	/* imx27 has the imx21 version audmux */
+	imx_add_platform_device("imx21-audmux", 0, audmux_res,
+				ARRAY_SIZE(audmux_res), NULL, 0);
 	imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
 	imx27_add_imx_uart0(&uart_pdata);
 
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 4917aab..f84bd46 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -486,8 +486,14 @@ static unsigned int ssi_pins[] = {
 	MX31_PIN_STXD5__STXD5,
 };
 
+static const struct resource audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 static void __init mxc_init_audio(void)
 {
+	imx_add_platform_device("imx31-audmux", 0, audmux_res,
+				ARRAY_SIZE(audmux_res), NULL, 0);
 	imx31_add_imx_ssi(0, NULL);
 	mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 }
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 541152e..8a491b3 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -240,6 +240,10 @@ static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = {
 	.flags			= IMX_SSI_USE_AC97,
 };
 
+static const struct resource audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K),
+};
+
 static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 		void *data)
 {
@@ -363,6 +367,9 @@ static void __init pca100_init(void)
 	if (ret)
 		printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
 
+	/* imx27 has the imx21 version audmux */
+	imx_add_platform_device("imx21-audmux", 0, audmux_res,
+				ARRAY_SIZE(audmux_res), NULL, 0);
 	imx27_add_imx_ssi(0, &pca100_ssi_pdata);
 
 	imx27_add_imx_uart0(&uart_pdata);
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 237474f..7d6a1e0 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -298,6 +298,10 @@ static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
 	.flags = IMX_SSI_USE_AC97,
 };
 
+static const struct resource audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 static const struct mxc_nand_platform_data
 pcm037_nand_board_info __initconst = {
 	.width = 1,
@@ -367,6 +371,9 @@ static void __init pcm043_init(void)
 
 	imx35_add_imx_uart0(&uart_pdata);
 	imx35_add_mxc_nand(&pcm037_nand_board_info);
+	/* imx35 has the imx31 version audmux */
+	imx_add_platform_device("imx31-audmux", 0, audmux_res,
+				ARRAY_SIZE(audmux_res), NULL, 0);
 	imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
 
 	imx35_add_imx_uart1(&uart_pdata);
diff --git a/arch/arm/plat-mxc/audmux.c b/arch/arm/plat-mxc/audmux.c
index f6dc536..98f5656 100644
--- a/arch/arm/plat-mxc/audmux.c
+++ b/arch/arm/plat-mxc/audmux.c
@@ -1,4 +1,6 @@
 /*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
  * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer at pengutronix.de>
  *
  * Initial development of this code was funded by
@@ -15,14 +17,16 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/debugfs.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <mach/audmux.h>
-#include <mach/hardware.h>
+
+#define DRIVER_NAME "imx-audmux"
 
 static struct clk *audmux_clk;
 static void __iomem *audmux_base;
@@ -140,7 +144,7 @@ static const struct file_operations audmux_debugfs_fops = {
 	.llseek = default_llseek,
 };
 
-static void audmux_debugfs_init(void)
+static void __init audmux_debugfs_init(void)
 {
 	int i;
 	char buf[20];
@@ -159,18 +163,48 @@ static void audmux_debugfs_init(void)
 				   i);
 	}
 }
+
+static void __exit audmux_debugfs_remove(void)
+{
+	debugfs_remove_recursive(audmux_debugfs_root);
+}
 #else
 static inline void audmux_debugfs_init(void)
 {
 }
+
+static inline void audmux_debugfs_remove(void)
+{
+}
 #endif
 
+enum imx_audmux_type {
+	IMX21_AUDMUX,
+	IMX31_AUDMUX,
+} audmux_type;
+
+static struct platform_device_id imx_audmux_ids[] = {
+	{
+		.name = "imx21-audmux",
+		.driver_data = IMX21_AUDMUX,
+	}, {
+		.name = "imx31-audmux",
+		.driver_data = IMX31_AUDMUX,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(platform, imx_audmux_ids);
+
 static unsigned char port_mapping[] = {
 	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
 };
 
 int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
 {
+	if (audmux_type != IMX21_AUDMUX)
+		return -EINVAL;
+
 	if (!audmux_base)
 		return -ENOSYS;
 
@@ -186,6 +220,9 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
 int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 		unsigned int pdcr)
 {
+	if (audmux_type != IMX31_AUDMUX)
+		return -EINVAL;
+
 	if (!audmux_base)
 		return -ENOSYS;
 
@@ -202,41 +239,61 @@ int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 }
 EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
 
-static int mxc_audmux_init(void)
+static int __init imx_audmux_probe(struct platform_device *pdev)
 {
-	int ret;
-	if (cpu_is_mx51()) {
-		audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR);
-	} else if (cpu_is_mx31()) {
-		audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
-	} else if (cpu_is_mx35()) {
-		audmux_clk = clk_get(NULL, "audmux");
-		if (IS_ERR(audmux_clk)) {
-			ret = PTR_ERR(audmux_clk);
-			printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
-					ret);
-			return ret;
-		}
-		audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
-	} else if (cpu_is_mx25()) {
-		audmux_clk = clk_get(NULL, "audmux");
-		if (IS_ERR(audmux_clk)) {
-			ret = PTR_ERR(audmux_clk);
-			printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
-					ret);
-			return ret;
-		}
-		audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
-	} else if (cpu_is_mx27()) {
-		audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR);
-	} else if (cpu_is_mx21()) {
-		audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR);
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	audmux_base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!audmux_base)
+		return -EADDRNOTAVAIL;
+
+	audmux_clk = clk_get(&pdev->dev, "audmux");
+	if (IS_ERR(audmux_clk)) {
+		dev_dbg(&pdev->dev, "cannot get clock: %ld\n",
+				PTR_ERR(audmux_clk));
+		audmux_clk = NULL;
 	}
 
-	if (!cpu_is_mx2())
+	audmux_type = pdev->id_entry->driver_data;
+	if (audmux_type == IMX31_AUDMUX)
 		audmux_debugfs_init();
 
 	return 0;
 }
 
-postcore_initcall(mxc_audmux_init);
+static int __exit imx_audmux_remove(struct platform_device *pdev)
+{
+	if (audmux_type == IMX31_AUDMUX)
+		audmux_debugfs_remove();
+	clk_put(audmux_clk);
+
+	return 0;
+}
+
+static struct platform_driver imx_audmux_driver = {
+	.probe		= imx_audmux_probe,
+	.remove		= __exit_p(imx_audmux_remove),
+	.id_table	= imx_audmux_ids,
+	.driver	= {
+		.name	= DRIVER_NAME,
+		.owner	= THIS_MODULE,
+	}
+};
+
+static int __init imx_audmux_init(void)
+{
+	return platform_driver_register(&imx_audmux_driver);
+}
+subsys_initcall(imx_audmux_init);
+
+static void __exit imx_audmux_exit(void)
+{
+	platform_driver_unregister(&imx_audmux_driver);
+}
+module_exit(imx_audmux_exit);
+
+MODULE_DESCRIPTION("Freescale i.MX AUDMUX driver");
+MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:46 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:46 +0800
Subject: [PATCH 05/20] ASoC: imx: move audmux driver into sound/soc/imx
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-6-git-send-email-shawn.guo@linaro.org>

As audmux becomes a platform driver and its callers are all ASoC
machine drivers, there is no reason to keep it in arch folder, so
move it to sound/soc/imx.

One bonus point would be those ASoC machine drivers stop including
mach/audmux.h, since it's been moved to sound/soc/imx/imx-audmux.h.
This should be a move to the right direction in terms of single kernel
image goal.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/Kconfig                          |    6 ------
 arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c       |    1 -
 arch/arm/plat-mxc/Kconfig                          |    3 ---
 arch/arm/plat-mxc/Makefile                         |    1 -
 sound/soc/imx/Kconfig                              |    7 +++++++
 sound/soc/imx/Makefile                             |    2 ++
 sound/soc/imx/eukrea-tlv320.c                      |    2 +-
 .../audmux.c => sound/soc/imx/imx-audmux.c         |    3 ++-
 .../mach/audmux.h => sound/soc/imx/imx-audmux.h    |    6 +++---
 sound/soc/imx/mx27vis-aic32x4.c                    |    2 +-
 sound/soc/imx/phycore-ac97.c                       |    3 ++-
 sound/soc/imx/wm1133-ev1.c                         |    3 +--
 12 files changed, 19 insertions(+), 20 deletions(-)
 rename arch/arm/plat-mxc/audmux.c => sound/soc/imx/imx-audmux.c (99%)
 rename arch/arm/plat-mxc/include/mach/audmux.h => sound/soc/imx/imx-audmux.h (96%)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 495a854..3919fba 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -46,7 +46,6 @@ config SOC_IMX21
 	bool
 	select MACH_MX21
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
@@ -55,7 +54,6 @@ config SOC_IMX25
 	bool
 	select ARCH_MX25
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX
 	select ARCH_MXC_IOMUX_V3
 	select MXC_AVIC
 
@@ -63,7 +61,6 @@ config SOC_IMX27
 	bool
 	select MACH_MX27
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
@@ -72,7 +69,6 @@ config SOC_IMX31
 	bool
 	select CPU_V6
 	select IMX_HAVE_PLATFORM_MXC_RNGA
-	select ARCH_MXC_AUDMUX
 	select MXC_AVIC
 	select SMP_ON_UP if SMP
 
@@ -80,7 +76,6 @@ config SOC_IMX35
 	bool
 	select CPU_V6
 	select ARCH_MXC_IOMUX_V3
-	select ARCH_MXC_AUDMUX
 	select HAVE_EPIT
 	select MXC_AVIC
 	select SMP_ON_UP if SMP
@@ -89,7 +84,6 @@ config SOC_IMX5
 	select CPU_V7
 	select MXC_TZIC
 	select ARCH_MXC_IOMUX_V3
-	select ARCH_MXC_AUDMUX
 	select ARCH_HAS_CPUFREQ
 	select ARCH_MX5
 	bool
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
index d817fc8..aaa592f 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
@@ -37,7 +37,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx51.h>
-#include <mach/audmux.h>
 
 #include "devices-imx51.h"
 
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 0461d16..c722f9c 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -88,9 +88,6 @@ config IMX_HAVE_IOMUX_V1
 config ARCH_MXC_IOMUX_V3
 	bool
 
-config ARCH_MXC_AUDMUX
-	bool
-
 config IRAM_ALLOC
 	bool
 	select GENERIC_ALLOCATOR
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 530c81d..e81290c 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
-obj-$(CONFIG_ARCH_MXC_AUDMUX) += audmux.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
 ifdef CONFIG_SND_IMX_SOC
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index 192861c..4025eee 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -17,11 +17,15 @@ config SND_MXC_SOC_MX2
 	select SND_SOC_DMAENGINE_PCM
 	tristate
 
+config SND_SOC_IMX_AUDMUX
+	tristate
+
 config SND_MXC_SOC_WM1133_EV1
 	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
 	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
 	select SND_SOC_WM8350
 	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
 	help
 	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
 	  PMIC board with WM8835x fitted.
@@ -31,6 +35,7 @@ config SND_SOC_MX27VIS_AIC32X4
 	depends on MACH_IMX27_VISSTRIM_M10 && I2C
 	select SND_SOC_TLV320AIC32X4
 	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_AUDMUX
 	help
 	  Say Y if you want to add support for SoC audio on Visstrim SM10
 	  board with TLV320AIC32X4 codec.
@@ -40,6 +45,7 @@ config SND_SOC_PHYCORE_AC97
 	depends on MACH_PCM043 || MACH_PCA100
 	select SND_SOC_WM9712
 	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
 	help
 	  Say Y if you want to add support for SoC audio on Phytec phyCORE
 	  and phyCARD boards in AC97 mode
@@ -53,6 +59,7 @@ config SND_SOC_EUKREA_TLV320
 	depends on I2C
 	select SND_SOC_TLV320AIC23
 	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
 	help
 	  Enable I2S based access to the TLV320AIC23B codec attached
 	  to the SSI interface
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
index d6d609b..5c40541 100644
--- a/sound/soc/imx/Makefile
+++ b/sound/soc/imx/Makefile
@@ -2,10 +2,12 @@
 snd-soc-imx-objs := imx-ssi.o
 snd-soc-imx-fiq-objs := imx-pcm-fiq.o
 snd-soc-imx-mx2-objs := imx-pcm-dma-mx2.o
+snd-soc-imx-audmux-objs := imx-audmux.o
 
 obj-$(CONFIG_SND_IMX_SOC) += snd-soc-imx.o
 obj-$(CONFIG_SND_MXC_SOC_FIQ) += snd-soc-imx-fiq.o
 obj-$(CONFIG_SND_MXC_SOC_MX2) += snd-soc-imx-mx2.o
+obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
 
 # i.MX Machine Support
 snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/imx/eukrea-tlv320.c
index bfcb6d9..b375ed4 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/imx/eukrea-tlv320.c
@@ -23,10 +23,10 @@
 #include <sound/pcm.h>
 #include <sound/soc.h>
 #include <asm/mach-types.h>
-#include <mach/audmux.h>
 
 #include "../codecs/tlv320aic23.h"
 #include "imx-ssi.h"
+#include "imx-audmux.h"
 
 #define CODEC_CLOCK 12000000
 
diff --git a/arch/arm/plat-mxc/audmux.c b/sound/soc/imx/imx-audmux.c
similarity index 99%
rename from arch/arm/plat-mxc/audmux.c
rename to sound/soc/imx/imx-audmux.c
index 98f5656..e0d8c4b 100644
--- a/arch/arm/plat-mxc/audmux.c
+++ b/sound/soc/imx/imx-audmux.c
@@ -24,7 +24,8 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
-#include <mach/audmux.h>
+
+#include "imx-audmux.h"
 
 #define DRIVER_NAME "imx-audmux"
 
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/sound/soc/imx/imx-audmux.h
similarity index 96%
rename from arch/arm/plat-mxc/include/mach/audmux.h
rename to sound/soc/imx/imx-audmux.h
index 6fda788..5136d948 100644
--- a/arch/arm/plat-mxc/include/mach/audmux.h
+++ b/sound/soc/imx/imx-audmux.h
@@ -1,5 +1,5 @@
-#ifndef __MACH_AUDMUX_H
-#define __MACH_AUDMUX_H
+#ifndef __IMX_AUDMUX_H
+#define __IMX_AUDMUX_H
 
 #define MX27_AUDMUX_HPCR1_SSI0		0
 #define MX27_AUDMUX_HPCR2_SSI1		1
@@ -57,4 +57,4 @@ int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
 int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 		unsigned int pdcr);
 
-#endif /* __MACH_AUDMUX_H */
+#endif /* __IMX_AUDMUX_H */
diff --git a/sound/soc/imx/mx27vis-aic32x4.c b/sound/soc/imx/mx27vis-aic32x4.c
index 155899c..dbfad0f 100644
--- a/sound/soc/imx/mx27vis-aic32x4.c
+++ b/sound/soc/imx/mx27vis-aic32x4.c
@@ -32,11 +32,11 @@
 #include <sound/soc-dapm.h>
 #include <sound/tlv.h>
 #include <asm/mach-types.h>
-#include <mach/audmux.h>
 #include <mach/iomux-mx27.h>
 
 #include "../codecs/tlv320aic32x4.h"
 #include "imx-ssi.h"
+#include "imx-audmux.h"
 
 #define MX27VIS_AMP_GAIN	0
 #define MX27VIS_AMP_MUTE	1
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/imx/phycore-ac97.c
index a59692e..7dab077 100644
--- a/sound/soc/imx/phycore-ac97.c
+++ b/sound/soc/imx/phycore-ac97.c
@@ -18,7 +18,8 @@
 #include <sound/pcm.h>
 #include <sound/soc.h>
 #include <asm/mach-types.h>
-#include <mach/audmux.h>
+
+#include "imx-audmux.h"
 
 static struct snd_soc_card imx_phycore;
 
diff --git a/sound/soc/imx/wm1133-ev1.c b/sound/soc/imx/wm1133-ev1.c
index 37480c9..15056d6 100644
--- a/sound/soc/imx/wm1133-ev1.c
+++ b/sound/soc/imx/wm1133-ev1.c
@@ -21,10 +21,9 @@
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 
-#include <mach/audmux.h>
-
 #include "imx-ssi.h"
 #include "../codecs/wm8350.h"
+#include "imx-audmux.h"
 
 /* There is a silicon mic on the board optionally connected via a solder pad
  * SP1.  Define this to enable it.
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:47 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:47 +0800
Subject: [PATCH 06/20] ASoC: imx: rename audmux prefix mxc to imx
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-7-git-send-email-shawn.guo@linaro.org>

It renames the legacy name mxc used in audmux function and macro
to imx.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/imx/eukrea-tlv320.c   |   44 +++++++++++++++---------------
 sound/soc/imx/imx-audmux.c      |   30 ++++++++++----------
 sound/soc/imx/imx-audmux.h      |   58 +++++++++++++++++++-------------------
 sound/soc/imx/mx27vis-aic32x4.c |   18 ++++++------
 sound/soc/imx/phycore-ac97.c    |   40 +++++++++++++-------------
 sound/soc/imx/wm1133-ev1.c      |   22 +++++++-------
 6 files changed, 106 insertions(+), 106 deletions(-)

diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/imx/eukrea-tlv320.c
index b375ed4..7d4475c 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/imx/eukrea-tlv320.c
@@ -101,35 +101,35 @@ static int __init eukrea_tlv320_init(void)
 	int int_port = 0, ext_port;
 
 	if (machine_is_eukrea_cpuimx27()) {
-		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_TFSDIR |
-			MXC_AUDMUX_V1_PCR_TCLKDIR |
-			MXC_AUDMUX_V1_PCR_RFSDIR |
-			MXC_AUDMUX_V1_PCR_RCLKDIR |
-			MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
-			MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
+		imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+			IMX_AUDMUX_V1_PCR_SYN |
+			IMX_AUDMUX_V1_PCR_TFSDIR |
+			IMX_AUDMUX_V1_PCR_TCLKDIR |
+			IMX_AUDMUX_V1_PCR_RFSDIR |
+			IMX_AUDMUX_V1_PCR_RCLKDIR |
+			IMX_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+			IMX_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+			IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
 		);
-		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+		imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
+			IMX_AUDMUX_V1_PCR_SYN |
+			IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
 		);
 	} else if (machine_is_eukrea_cpuimx25sd() ||
 		   machine_is_eukrea_cpuimx35sd() ||
 		   machine_is_eukrea_cpuimx51sd()) {
 		ext_port = machine_is_eukrea_cpuimx25sd() ? 4 : 3;
-		mxc_audmux_v2_configure_port(int_port,
-			MXC_AUDMUX_V2_PTCR_SYN |
-			MXC_AUDMUX_V2_PTCR_TFSDIR |
-			MXC_AUDMUX_V2_PTCR_TFSEL(ext_port) |
-			MXC_AUDMUX_V2_PTCR_TCLKDIR |
-			MXC_AUDMUX_V2_PTCR_TCSEL(ext_port),
-			MXC_AUDMUX_V2_PDCR_RXDSEL(ext_port)
+		imx_audmux_v2_configure_port(int_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TFSDIR |
+			IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TCLKDIR |
+			IMX_AUDMUX_V2_PTCR_TCSEL(ext_port),
+			IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port)
 		);
-		mxc_audmux_v2_configure_port(ext_port,
-			MXC_AUDMUX_V2_PTCR_SYN,
-			MXC_AUDMUX_V2_PDCR_RXDSEL(int_port)
+		imx_audmux_v2_configure_port(ext_port,
+			IMX_AUDMUX_V2_PTCR_SYN,
+			IMX_AUDMUX_V2_PDCR_RXDSEL(int_port)
 		);
 	} else {
 		/* return happy. We might run on a totally different machine */
diff --git a/sound/soc/imx/imx-audmux.c b/sound/soc/imx/imx-audmux.c
index e0d8c4b..d7bf154 100644
--- a/sound/soc/imx/imx-audmux.c
+++ b/sound/soc/imx/imx-audmux.c
@@ -32,8 +32,8 @@
 static struct clk *audmux_clk;
 static void __iomem *audmux_base;
 
-#define MXC_AUDMUX_V2_PTCR(x)		((x) * 8)
-#define MXC_AUDMUX_V2_PDCR(x)		((x) * 8 + 4)
+#define IMX_AUDMUX_V2_PTCR(x)		((x) * 8)
+#define IMX_AUDMUX_V2_PDCR(x)		((x) * 8 + 4)
 
 #ifdef CONFIG_DEBUG_FS
 static struct dentry *audmux_debugfs_root;
@@ -80,8 +80,8 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 	if (audmux_clk)
 		clk_enable(audmux_clk);
 
-	ptcr = readl(audmux_base + MXC_AUDMUX_V2_PTCR(port));
-	pdcr = readl(audmux_base + MXC_AUDMUX_V2_PDCR(port));
+	ptcr = readl(audmux_base + IMX_AUDMUX_V2_PTCR(port));
+	pdcr = readl(audmux_base + IMX_AUDMUX_V2_PDCR(port));
 
 	if (audmux_clk)
 		clk_disable(audmux_clk);
@@ -89,7 +89,7 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 	ret = snprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n",
 		       pdcr, ptcr);
 
-	if (ptcr & MXC_AUDMUX_V2_PTCR_TFSDIR)
+	if (ptcr & IMX_AUDMUX_V2_PTCR_TFSDIR)
 		ret += snprintf(buf + ret, PAGE_SIZE - ret,
 				"TxFS output from %s, ",
 				audmux_port_string((ptcr >> 27) & 0x7));
@@ -97,7 +97,7 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 		ret += snprintf(buf + ret, PAGE_SIZE - ret,
 				"TxFS input, ");
 
-	if (ptcr & MXC_AUDMUX_V2_PTCR_TCLKDIR)
+	if (ptcr & IMX_AUDMUX_V2_PTCR_TCLKDIR)
 		ret += snprintf(buf + ret, PAGE_SIZE - ret,
 				"TxClk output from %s",
 				audmux_port_string((ptcr >> 22) & 0x7));
@@ -107,11 +107,11 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 
 	ret += snprintf(buf + ret, PAGE_SIZE - ret, "\n");
 
-	if (ptcr & MXC_AUDMUX_V2_PTCR_SYN) {
+	if (ptcr & IMX_AUDMUX_V2_PTCR_SYN) {
 		ret += snprintf(buf + ret, PAGE_SIZE - ret,
 				"Port is symmetric");
 	} else {
-		if (ptcr & MXC_AUDMUX_V2_PTCR_RFSDIR)
+		if (ptcr & IMX_AUDMUX_V2_PTCR_RFSDIR)
 			ret += snprintf(buf + ret, PAGE_SIZE - ret,
 					"RxFS output from %s, ",
 					audmux_port_string((ptcr >> 17) & 0x7));
@@ -119,7 +119,7 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 			ret += snprintf(buf + ret, PAGE_SIZE - ret,
 					"RxFS input, ");
 
-		if (ptcr & MXC_AUDMUX_V2_PTCR_RCLKDIR)
+		if (ptcr & IMX_AUDMUX_V2_PTCR_RCLKDIR)
 			ret += snprintf(buf + ret, PAGE_SIZE - ret,
 					"RxClk output from %s",
 					audmux_port_string((ptcr >> 12) & 0x7));
@@ -201,7 +201,7 @@ static unsigned char port_mapping[] = {
 	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
 };
 
-int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
+int imx_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
 {
 	if (audmux_type != IMX21_AUDMUX)
 		return -EINVAL;
@@ -216,9 +216,9 @@ int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
+EXPORT_SYMBOL_GPL(imx_audmux_v1_configure_port);
 
-int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
+int imx_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 		unsigned int pdcr)
 {
 	if (audmux_type != IMX31_AUDMUX)
@@ -230,15 +230,15 @@ int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 	if (audmux_clk)
 		clk_enable(audmux_clk);
 
-	writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port));
-	writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port));
+	writel(ptcr, audmux_base + IMX_AUDMUX_V2_PTCR(port));
+	writel(pdcr, audmux_base + IMX_AUDMUX_V2_PDCR(port));
 
 	if (audmux_clk)
 		clk_disable(audmux_clk);
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
+EXPORT_SYMBOL_GPL(imx_audmux_v2_configure_port);
 
 static int __init imx_audmux_probe(struct platform_device *pdev)
 {
diff --git a/sound/soc/imx/imx-audmux.h b/sound/soc/imx/imx-audmux.h
index 5136d948..04ebbab 100644
--- a/sound/soc/imx/imx-audmux.h
+++ b/sound/soc/imx/imx-audmux.h
@@ -24,37 +24,37 @@
 #define MX51_AUDMUX_PORT7		6
 
 /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
-#define MXC_AUDMUX_V1_PCR_INMMASK(x)	((x) & 0xff)
-#define MXC_AUDMUX_V1_PCR_INMEN		(1 << 8)
-#define MXC_AUDMUX_V1_PCR_TXRXEN	(1 << 10)
-#define MXC_AUDMUX_V1_PCR_SYN		(1 << 12)
-#define MXC_AUDMUX_V1_PCR_RXDSEL(x)	(((x) & 0x7) << 13)
-#define MXC_AUDMUX_V1_PCR_RFCSEL(x)	(((x) & 0xf) << 20)
-#define MXC_AUDMUX_V1_PCR_RCLKDIR	(1 << 24)
-#define MXC_AUDMUX_V1_PCR_RFSDIR	(1 << 25)
-#define MXC_AUDMUX_V1_PCR_TFCSEL(x)	(((x) & 0xf) << 26)
-#define MXC_AUDMUX_V1_PCR_TCLKDIR	(1 << 30)
-#define MXC_AUDMUX_V1_PCR_TFSDIR	(1 << 31)
+#define IMX_AUDMUX_V1_PCR_INMMASK(x)	((x) & 0xff)
+#define IMX_AUDMUX_V1_PCR_INMEN		(1 << 8)
+#define IMX_AUDMUX_V1_PCR_TXRXEN	(1 << 10)
+#define IMX_AUDMUX_V1_PCR_SYN		(1 << 12)
+#define IMX_AUDMUX_V1_PCR_RXDSEL(x)	(((x) & 0x7) << 13)
+#define IMX_AUDMUX_V1_PCR_RFCSEL(x)	(((x) & 0xf) << 20)
+#define IMX_AUDMUX_V1_PCR_RCLKDIR	(1 << 24)
+#define IMX_AUDMUX_V1_PCR_RFSDIR	(1 << 25)
+#define IMX_AUDMUX_V1_PCR_TFCSEL(x)	(((x) & 0xf) << 26)
+#define IMX_AUDMUX_V1_PCR_TCLKDIR	(1 << 30)
+#define IMX_AUDMUX_V1_PCR_TFSDIR	(1 << 31)
 
 /* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */
-#define MXC_AUDMUX_V2_PTCR_TFSDIR	(1 << 31)
-#define MXC_AUDMUX_V2_PTCR_TFSEL(x)	(((x) & 0xf) << 27)
-#define MXC_AUDMUX_V2_PTCR_TCLKDIR	(1 << 26)
-#define MXC_AUDMUX_V2_PTCR_TCSEL(x)	(((x) & 0xf) << 22)
-#define MXC_AUDMUX_V2_PTCR_RFSDIR	(1 << 21)
-#define MXC_AUDMUX_V2_PTCR_RFSEL(x)	(((x) & 0xf) << 17)
-#define MXC_AUDMUX_V2_PTCR_RCLKDIR	(1 << 16)
-#define MXC_AUDMUX_V2_PTCR_RCSEL(x)	(((x) & 0xf) << 12)
-#define MXC_AUDMUX_V2_PTCR_SYN		(1 << 11)
-
-#define MXC_AUDMUX_V2_PDCR_RXDSEL(x)	(((x) & 0x7) << 13)
-#define MXC_AUDMUX_V2_PDCR_TXRXEN	(1 << 12)
-#define MXC_AUDMUX_V2_PDCR_MODE(x)	(((x) & 0x3) << 8)
-#define MXC_AUDMUX_V2_PDCR_INMMASK(x)	((x) & 0xff)
-
-int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
-
-int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
+#define IMX_AUDMUX_V2_PTCR_TFSDIR	(1 << 31)
+#define IMX_AUDMUX_V2_PTCR_TFSEL(x)	(((x) & 0xf) << 27)
+#define IMX_AUDMUX_V2_PTCR_TCLKDIR	(1 << 26)
+#define IMX_AUDMUX_V2_PTCR_TCSEL(x)	(((x) & 0xf) << 22)
+#define IMX_AUDMUX_V2_PTCR_RFSDIR	(1 << 21)
+#define IMX_AUDMUX_V2_PTCR_RFSEL(x)	(((x) & 0xf) << 17)
+#define IMX_AUDMUX_V2_PTCR_RCLKDIR	(1 << 16)
+#define IMX_AUDMUX_V2_PTCR_RCSEL(x)	(((x) & 0xf) << 12)
+#define IMX_AUDMUX_V2_PTCR_SYN		(1 << 11)
+
+#define IMX_AUDMUX_V2_PDCR_RXDSEL(x)	(((x) & 0x7) << 13)
+#define IMX_AUDMUX_V2_PDCR_TXRXEN	(1 << 12)
+#define IMX_AUDMUX_V2_PDCR_MODE(x)	(((x) & 0x3) << 8)
+#define IMX_AUDMUX_V2_PDCR_INMMASK(x)	((x) & 0xff)
+
+int imx_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
+
+int imx_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 		unsigned int pdcr);
 
 #endif /* __IMX_AUDMUX_H */
diff --git a/sound/soc/imx/mx27vis-aic32x4.c b/sound/soc/imx/mx27vis-aic32x4.c
index dbfad0f..976f857 100644
--- a/sound/soc/imx/mx27vis-aic32x4.c
+++ b/sound/soc/imx/mx27vis-aic32x4.c
@@ -207,16 +207,16 @@ static int __init mx27vis_aic32x4_init(void)
 	}
 
 	/* Connect SSI0 as clock slave to SSI1 external pins */
-	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_TFSDIR |
-			MXC_AUDMUX_V1_PCR_TCLKDIR |
-			MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1) |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1)
+	imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+			IMX_AUDMUX_V1_PCR_SYN |
+			IMX_AUDMUX_V1_PCR_TFSDIR |
+			IMX_AUDMUX_V1_PCR_TCLKDIR |
+			IMX_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1) |
+			IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1)
 	);
-	mxc_audmux_v1_configure_port(MX27_AUDMUX_PPCR1_SSI_PINS_1,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+	imx_audmux_v1_configure_port(MX27_AUDMUX_PPCR1_SSI_PINS_1,
+			IMX_AUDMUX_V1_PCR_SYN |
+			IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
 	);
 
 	ret = mxc_gpio_setup_multiple_pins(mx27vis_amp_pins,
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/imx/phycore-ac97.c
index 7dab077..f8da6dd 100644
--- a/sound/soc/imx/phycore-ac97.c
+++ b/sound/soc/imx/phycore-ac97.c
@@ -53,27 +53,27 @@ static int __init imx_phycore_init(void)
 	int ret;
 
 	if (machine_is_pca100()) {
-		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-			MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V1_PCR_TFCSEL(3) |
-			MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
-			MXC_AUDMUX_V1_PCR_RXDSEL(3));
-		mxc_audmux_v1_configure_port(3,
-			MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V1_PCR_TFCSEL(0) |
-			MXC_AUDMUX_V1_PCR_TFSDIR |
-			MXC_AUDMUX_V1_PCR_RXDSEL(0));
+		imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+			IMX_AUDMUX_V1_PCR_TFCSEL(3) |
+			IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
+			IMX_AUDMUX_V1_PCR_RXDSEL(3));
+		imx_audmux_v1_configure_port(3,
+			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+			IMX_AUDMUX_V1_PCR_TFCSEL(0) |
+			IMX_AUDMUX_V1_PCR_TFSDIR |
+			IMX_AUDMUX_V1_PCR_RXDSEL(0));
 	} else if (machine_is_pcm043()) {
-		mxc_audmux_v2_configure_port(3,
-			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V2_PTCR_TFSEL(0) |
-			MXC_AUDMUX_V2_PTCR_TFSDIR,
-			MXC_AUDMUX_V2_PDCR_RXDSEL(0));
-		mxc_audmux_v2_configure_port(0,
-			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V2_PTCR_TCSEL(3) |
-			MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
-			MXC_AUDMUX_V2_PDCR_RXDSEL(3));
+		imx_audmux_v2_configure_port(3,
+			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+			IMX_AUDMUX_V2_PTCR_TFSEL(0) |
+			IMX_AUDMUX_V2_PTCR_TFSDIR,
+			IMX_AUDMUX_V2_PDCR_RXDSEL(0));
+		imx_audmux_v2_configure_port(0,
+			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+			IMX_AUDMUX_V2_PTCR_TCSEL(3) |
+			IMX_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
+			IMX_AUDMUX_V2_PDCR_RXDSEL(3));
 	} else {
 		/* return happy. We might run on a totally different machine */
 		return 0;
diff --git a/sound/soc/imx/wm1133-ev1.c b/sound/soc/imx/wm1133-ev1.c
index 15056d6..fe54a69 100644
--- a/sound/soc/imx/wm1133-ev1.c
+++ b/sound/soc/imx/wm1133-ev1.c
@@ -267,17 +267,17 @@ static int __init wm1133_ev1_audio_init(void)
 	unsigned int ptcr, pdcr;
 
 	/* SSI0 mastered by port 5 */
-	ptcr = MXC_AUDMUX_V2_PTCR_SYN |
-		MXC_AUDMUX_V2_PTCR_TFSDIR |
-		MXC_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT5_SSI_PINS_5) |
-		MXC_AUDMUX_V2_PTCR_TCLKDIR |
-		MXC_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT5_SSI_PINS_5);
-	pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT5_SSI_PINS_5);
-	mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT1_SSI0, ptcr, pdcr);
-
-	ptcr = MXC_AUDMUX_V2_PTCR_SYN;
-	pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0);
-	mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT5_SSI_PINS_5, ptcr, pdcr);
+	ptcr = IMX_AUDMUX_V2_PTCR_SYN |
+		IMX_AUDMUX_V2_PTCR_TFSDIR |
+		IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT5_SSI_PINS_5) |
+		IMX_AUDMUX_V2_PTCR_TCLKDIR |
+		IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT5_SSI_PINS_5);
+	pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT5_SSI_PINS_5);
+	imx_audmux_v2_configure_port(MX31_AUDMUX_PORT1_SSI0, ptcr, pdcr);
+
+	ptcr = IMX_AUDMUX_V2_PTCR_SYN;
+	pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0);
+	imx_audmux_v2_configure_port(MX31_AUDMUX_PORT5_SSI_PINS_5, ptcr, pdcr);
 
 	wm1133_ev1_snd_device = platform_device_alloc("soc-audio", -1);
 	if (!wm1133_ev1_snd_device)
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:48 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:48 +0800
Subject: [PATCH 07/20] ASoC: imx: move SND_SOC_AC97_BUS selection down to
 machine driver
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-8-git-send-email-shawn.guo@linaro.org>

SND_SOC_AC97_BUS is selected to enable the AC97 support in soc-core.
Rather than selecting the option under SND_IMX_SOC, it's better to
leave the selection to individual machine driver which knows if AC97
support is needed or not.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/imx/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index 4025eee..d3b7166 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -1,7 +1,6 @@
 menuconfig SND_IMX_SOC
 	tristate "SoC Audio for Freescale i.MX CPUs"
 	depends on ARCH_MXC
-	select SND_SOC_AC97_BUS
 	help
 	  Say Y or M if you want to add support for codecs attached to
 	  the i.MX SSI interface.
@@ -43,6 +42,7 @@ config SND_SOC_MX27VIS_AIC32X4
 config SND_SOC_PHYCORE_AC97
 	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
 	depends on MACH_PCM043 || MACH_PCA100
+	select SND_SOC_AC97_BUS
 	select SND_SOC_WM9712
 	select SND_MXC_SOC_FIQ
 	select SND_SOC_IMX_AUDMUX
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:49 +0800
Subject: [PATCH 08/20] ASoC: imx: initialize dma_params burstsize just in
 imx-ssi
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-9-git-send-email-shawn.guo@linaro.org>

It's not necessary for imx-pcm-dma-mx2 to access imx_ssi.dma_params
for burstsize initialization.  Instead, it can just be done in imx-ssi
probe function once.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/imx/imx-pcm-dma-mx2.c |    5 -----
 sound/soc/imx/imx-ssi.c         |    2 +-
 2 files changed, 1 insertions(+), 6 deletions(-)

diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/imx/imx-pcm-dma-mx2.c
index 4cd5462..471e221 100644
--- a/sound/soc/imx/imx-pcm-dma-mx2.c
+++ b/sound/soc/imx/imx-pcm-dma-mx2.c
@@ -149,11 +149,6 @@ static struct snd_soc_platform_driver imx_soc_platform_mx2 = {
 
 static int __devinit imx_soc_platform_probe(struct platform_device *pdev)
 {
-	struct imx_ssi *ssi = platform_get_drvdata(pdev);
-
-	ssi->dma_params_tx.burstsize = 6;
-	ssi->dma_params_rx.burstsize = 4;
-
 	return snd_soc_register_platform(&pdev->dev, &imx_soc_platform_mx2);
 }
 
diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/imx/imx-ssi.c
index dac62b0..9af3a5b 100644
--- a/sound/soc/imx/imx-ssi.c
+++ b/sound/soc/imx/imx-ssi.c
@@ -668,7 +668,7 @@ static int imx_ssi_probe(struct platform_device *pdev)
 	ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
 	ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;
 
-	ssi->dma_params_tx.burstsize = 4;
+	ssi->dma_params_tx.burstsize = 6;
 	ssi->dma_params_rx.burstsize = 4;
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:50 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:50 +0800
Subject: [PATCH 09/20] ASoC: imx: separate imx-pcm bits from imx-ssi driver
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-10-git-send-email-shawn.guo@linaro.org>

Currently the imx-ssi.c[h] accommodates the imx-pcm common bits which
are shared between imx-pcm-dma-mx2 and imx-pcm-fiq drivers.  It assumes
that imx-pcm-dma-mx2 and imx-pcm-fiq will always be used together with
imx-ssi driver.  However this becomes untrue when we see that driver
sound/soc/fsl/fsl_ssi could possibly work with imx-pcm-dma-mx2 too.

The patch moves the imx-pcm common bits from imx-ssi.c[h] into new
files imx-pcm.c[h], and let imx-pcm-dma-mx2 and imx-pcm-fiq drivers
build it in, so that imx-pcm-dma-mx2 can work with no dependency on
imx-ssi driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/imx/Kconfig           |    7 ++-
 sound/soc/imx/Makefile          |    9 ++--
 sound/soc/imx/imx-pcm-dma-mx2.c |    2 +-
 sound/soc/imx/imx-pcm.c         |  105 +++++++++++++++++++++++++++++++++++++++
 sound/soc/imx/imx-pcm.h         |   32 ++++++++++++
 sound/soc/imx/imx-ssi.c         |   88 --------------------------------
 sound/soc/imx/imx-ssi.h         |   16 +------
 7 files changed, 150 insertions(+), 109 deletions(-)
 create mode 100644 sound/soc/imx/imx-pcm.c
 create mode 100644 sound/soc/imx/imx-pcm.h

diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index d3b7166..2566032 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -8,13 +8,18 @@ menuconfig SND_IMX_SOC
 
 if SND_IMX_SOC
 
+config SND_SOC_IMX_PCM
+	tristate
+
 config SND_MXC_SOC_FIQ
-	select FIQ
 	tristate
+	select FIQ
+	select SND_SOC_IMX_PCM
 
 config SND_MXC_SOC_MX2
 	select SND_SOC_DMAENGINE_PCM
 	tristate
+	select SND_SOC_IMX_PCM
 
 config SND_SOC_IMX_AUDMUX
 	tristate
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
index 5c40541..e9ed362 100644
--- a/sound/soc/imx/Makefile
+++ b/sound/soc/imx/Makefile
@@ -1,14 +1,15 @@
 # i.MX Platform Support
 snd-soc-imx-objs := imx-ssi.o
-snd-soc-imx-fiq-objs := imx-pcm-fiq.o
-snd-soc-imx-mx2-objs := imx-pcm-dma-mx2.o
 snd-soc-imx-audmux-objs := imx-audmux.o
 
 obj-$(CONFIG_SND_IMX_SOC) += snd-soc-imx.o
-obj-$(CONFIG_SND_MXC_SOC_FIQ) += snd-soc-imx-fiq.o
-obj-$(CONFIG_SND_MXC_SOC_MX2) += snd-soc-imx-mx2.o
 obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
 
+obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
+snd-soc-imx-pcm-y := imx-pcm.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
+
 # i.MX Machine Support
 snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
 snd-soc-phycore-ac97-objs := phycore-ac97.o
diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/imx/imx-pcm-dma-mx2.c
index 471e221..e43c8fa 100644
--- a/sound/soc/imx/imx-pcm-dma-mx2.c
+++ b/sound/soc/imx/imx-pcm-dma-mx2.c
@@ -31,7 +31,7 @@
 
 #include <mach/dma.h>
 
-#include "imx-ssi.h"
+#include "imx-pcm.h"
 
 static bool filter(struct dma_chan *chan, void *param)
 {
diff --git a/sound/soc/imx/imx-pcm.c b/sound/soc/imx/imx-pcm.c
new file mode 100644
index 0000000..93dc360
--- /dev/null
+++ b/sound/soc/imx/imx-pcm.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2009 Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This code is based on code copyrighted by Freescale,
+ * Liam Girdwood, Javier Martin and probably others.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include "imx-pcm.h"
+
+int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
+		struct vm_area_struct *vma)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	int ret;
+
+	ret = dma_mmap_writecombine(substream->pcm->card->dev, vma,
+		runtime->dma_area, runtime->dma_addr, runtime->dma_bytes);
+
+	pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
+			runtime->dma_area,
+			runtime->dma_addr,
+			runtime->dma_bytes);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(snd_imx_pcm_mmap);
+
+static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
+{
+	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+	struct snd_dma_buffer *buf = &substream->dma_buffer;
+	size_t size = IMX_SSI_DMABUF_SIZE;
+
+	buf->dev.type = SNDRV_DMA_TYPE_DEV;
+	buf->dev.dev = pcm->card->dev;
+	buf->private_data = NULL;
+	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
+					   &buf->addr, GFP_KERNEL);
+	if (!buf->area)
+		return -ENOMEM;
+	buf->bytes = size;
+
+	return 0;
+}
+
+static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
+
+int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
+{
+	struct snd_card *card = rtd->card->snd_card;
+	struct snd_pcm *pcm = rtd->pcm;
+	int ret = 0;
+
+	if (!card->dev->dma_mask)
+		card->dev->dma_mask = &imx_pcm_dmamask;
+	if (!card->dev->coherent_dma_mask)
+		card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
+	if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
+		ret = imx_pcm_preallocate_dma_buffer(pcm,
+			SNDRV_PCM_STREAM_PLAYBACK);
+		if (ret)
+			goto out;
+	}
+
+	if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
+		ret = imx_pcm_preallocate_dma_buffer(pcm,
+			SNDRV_PCM_STREAM_CAPTURE);
+		if (ret)
+			goto out;
+	}
+
+out:
+	return ret;
+}
+EXPORT_SYMBOL_GPL(imx_pcm_new);
+
+void imx_pcm_free(struct snd_pcm *pcm)
+{
+	struct snd_pcm_substream *substream;
+	struct snd_dma_buffer *buf;
+	int stream;
+
+	for (stream = 0; stream < 2; stream++) {
+		substream = pcm->streams[stream].substream;
+		if (!substream)
+			continue;
+
+		buf = &substream->dma_buffer;
+		if (!buf->area)
+			continue;
+
+		dma_free_writecombine(pcm->card->dev, buf->bytes,
+				      buf->area, buf->addr);
+		buf->area = NULL;
+	}
+}
+EXPORT_SYMBOL_GPL(imx_pcm_free);
diff --git a/sound/soc/imx/imx-pcm.h b/sound/soc/imx/imx-pcm.h
new file mode 100644
index 0000000..b5f5c3a
--- /dev/null
+++ b/sound/soc/imx/imx-pcm.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2009 Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This code is based on code copyrighted by Freescale,
+ * Liam Girdwood, Javier Martin and probably others.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _IMX_PCM_H
+#define _IMX_PCM_H
+
+/*
+ * Do not change this as the FIQ handler depends on this size
+ */
+#define IMX_SSI_DMABUF_SIZE	(64 * 1024)
+
+struct imx_pcm_dma_params {
+	int dma;
+	unsigned long dma_addr;
+	int burstsize;
+};
+
+int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
+		     struct vm_area_struct *vma);
+int imx_pcm_new(struct snd_soc_pcm_runtime *rtd);
+void imx_pcm_free(struct snd_pcm *pcm);
+
+#endif /* _IMX_PCM_H */
diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/imx/imx-ssi.c
index 9af3a5b..4f81ed4 100644
--- a/sound/soc/imx/imx-ssi.c
+++ b/sound/soc/imx/imx-ssi.c
@@ -363,94 +363,6 @@ static const struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
 	.trigger	= imx_ssi_trigger,
 };
 
-int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
-		struct vm_area_struct *vma)
-{
-	struct snd_pcm_runtime *runtime = substream->runtime;
-	int ret;
-
-	ret = dma_mmap_writecombine(substream->pcm->card->dev, vma,
-		runtime->dma_area, runtime->dma_addr, runtime->dma_bytes);
-
-	pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
-			runtime->dma_area,
-			runtime->dma_addr,
-			runtime->dma_bytes);
-	return ret;
-}
-EXPORT_SYMBOL_GPL(snd_imx_pcm_mmap);
-
-static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
-{
-	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
-	struct snd_dma_buffer *buf = &substream->dma_buffer;
-	size_t size = IMX_SSI_DMABUF_SIZE;
-
-	buf->dev.type = SNDRV_DMA_TYPE_DEV;
-	buf->dev.dev = pcm->card->dev;
-	buf->private_data = NULL;
-	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
-					   &buf->addr, GFP_KERNEL);
-	if (!buf->area)
-		return -ENOMEM;
-	buf->bytes = size;
-
-	return 0;
-}
-
-static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
-
-int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
-{
-	struct snd_card *card = rtd->card->snd_card;
-	struct snd_pcm *pcm = rtd->pcm;
-	int ret = 0;
-
-	if (!card->dev->dma_mask)
-		card->dev->dma_mask = &imx_pcm_dmamask;
-	if (!card->dev->coherent_dma_mask)
-		card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
-	if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
-		ret = imx_pcm_preallocate_dma_buffer(pcm,
-			SNDRV_PCM_STREAM_PLAYBACK);
-		if (ret)
-			goto out;
-	}
-
-	if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
-		ret = imx_pcm_preallocate_dma_buffer(pcm,
-			SNDRV_PCM_STREAM_CAPTURE);
-		if (ret)
-			goto out;
-	}
-
-out:
-	return ret;
-}
-EXPORT_SYMBOL_GPL(imx_pcm_new);
-
-void imx_pcm_free(struct snd_pcm *pcm)
-{
-	struct snd_pcm_substream *substream;
-	struct snd_dma_buffer *buf;
-	int stream;
-
-	for (stream = 0; stream < 2; stream++) {
-		substream = pcm->streams[stream].substream;
-		if (!substream)
-			continue;
-
-		buf = &substream->dma_buffer;
-		if (!buf->area)
-			continue;
-
-		dma_free_writecombine(pcm->card->dev, buf->bytes,
-				      buf->area, buf->addr);
-		buf->area = NULL;
-	}
-}
-EXPORT_SYMBOL_GPL(imx_pcm_free);
-
 static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
 {
 	struct imx_ssi *ssi = dev_get_drvdata(dai->dev);
diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/imx/imx-ssi.h
index 1072dfb..5744e86 100644
--- a/sound/soc/imx/imx-ssi.h
+++ b/sound/soc/imx/imx-ssi.h
@@ -187,12 +187,7 @@
 
 #include <linux/dmaengine.h>
 #include <mach/dma.h>
-
-struct imx_pcm_dma_params {
-	int dma;
-	unsigned long dma_addr;
-	int burstsize;
-};
+#include "imx-pcm.h"
 
 struct imx_ssi {
 	struct platform_device *ac97_dev;
@@ -218,13 +213,4 @@ struct imx_ssi {
 	struct platform_device *soc_platform_pdev_fiq;
 };
 
-int snd_imx_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma);
-int imx_pcm_new(struct snd_soc_pcm_runtime *rtd);
-void imx_pcm_free(struct snd_pcm *pcm);
-
-/*
- * Do not change this as the FIQ handler depends on this size
- */
-#define IMX_SSI_DMABUF_SIZE	(64 * 1024)
-
 #endif /* _IMX_SSI_H */
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:51 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:51 +0800
Subject: [PATCH 10/20] ASoC: imx: add an explicit Kconfig option for imx-ssi
 driver
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-11-git-send-email-shawn.guo@linaro.org>

Currently ASoC:imx uses menuconfig option SND_IMX_SOC selects imx-ssi
driver, and it works because all the machine driver covered by the
menuconfig need to build imx-ssi driver in.  However, it will not work
any more if we have a imx based machine driver going into the menuconfig
while working with fsl_ssi driver (sound/soc/fsl/fsl_ssi.c) rather than
imx-ssi one.

The patch adds an explicit Kconfig option SND_SOC_IMX_SSI for imx-ssi
driver, so that it can be selected independently from the menuconfig
option SND_IMX_SOC.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/imx/Kconfig  |    7 +++++++
 sound/soc/imx/Makefile |    4 ++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index 2566032..810acaa 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -8,6 +8,9 @@ menuconfig SND_IMX_SOC
 
 if SND_IMX_SOC
 
+config SND_SOC_IMX_SSI
+	tristate
+
 config SND_SOC_IMX_PCM
 	tristate
 
@@ -30,6 +33,7 @@ config SND_MXC_SOC_WM1133_EV1
 	select SND_SOC_WM8350
 	select SND_MXC_SOC_FIQ
 	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
 	help
 	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
 	  PMIC board with WM8835x fitted.
@@ -40,6 +44,7 @@ config SND_SOC_MX27VIS_AIC32X4
 	select SND_SOC_TLV320AIC32X4
 	select SND_MXC_SOC_MX2
 	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
 	help
 	  Say Y if you want to add support for SoC audio on Visstrim SM10
 	  board with TLV320AIC32X4 codec.
@@ -51,6 +56,7 @@ config SND_SOC_PHYCORE_AC97
 	select SND_SOC_WM9712
 	select SND_MXC_SOC_FIQ
 	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
 	help
 	  Say Y if you want to add support for SoC audio on Phytec phyCORE
 	  and phyCARD boards in AC97 mode
@@ -65,6 +71,7 @@ config SND_SOC_EUKREA_TLV320
 	select SND_SOC_TLV320AIC23
 	select SND_MXC_SOC_FIQ
 	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
 	help
 	  Enable I2S based access to the TLV320AIC23B codec attached
 	  to the SSI interface
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
index e9ed362..f5db3e9 100644
--- a/sound/soc/imx/Makefile
+++ b/sound/soc/imx/Makefile
@@ -1,8 +1,8 @@
 # i.MX Platform Support
-snd-soc-imx-objs := imx-ssi.o
+snd-soc-imx-ssi-objs := imx-ssi.o
 snd-soc-imx-audmux-objs := imx-audmux.o
 
-obj-$(CONFIG_SND_IMX_SOC) += snd-soc-imx.o
+obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
 obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
 
 obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:52 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:52 +0800
Subject: [PATCH 11/20] ASoC: fsl: separate SSI and DMA Kconfig options
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-12-git-send-email-shawn.guo@linaro.org>

The fsl_ssi driver will possibly be shared between Freescale PowerPC
and ARM/IMX families, so give it a separate Kconfig option.  Then
fsl_ssi driver can possibly be selected independently from selecting
PowerPC DMA based PCM driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/Kconfig  |   15 +++++++++------
 sound/soc/fsl/Makefile |    3 ++-
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index d754d34..ca693b2 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,10 +1,11 @@
 config SND_MPC52xx_DMA
 	tristate
 
-# ASoC platform support for the Freescale PowerPC SOCs that have an SSI and
-# an Elo DMA controller, such as the MPC8610 and P1022.  You will still need to
-# select a platform driver and a codec driver.
-config SND_SOC_POWERPC_SSI
+config SND_SOC_FSL_SSI
+	tristate
+	depends on FSL_SOC
+
+config SND_SOC_POWERPC_DMA
 	tristate
 	depends on FSL_SOC
 
@@ -12,7 +13,8 @@ config SND_SOC_MPC8610_HPCD
 	tristate "ALSA SoC support for the Freescale MPC8610 HPCD board"
 	# I2C is necessary for the CS4270 driver
 	depends on MPC8610_HPCD && I2C
-	select SND_SOC_POWERPC_SSI
+	select SND_SOC_FSL_SSI
+	select SND_SOC_POWERPC_DMA
 	select SND_SOC_CS4270
 	select SND_SOC_CS4270_VD33_ERRATA
 	default y if MPC8610_HPCD
@@ -23,7 +25,8 @@ config SND_SOC_P1022_DS
 	tristate "ALSA SoC support for the Freescale P1022 DS board"
 	# I2C is necessary for the WM8776 driver
 	depends on P1022_DS && I2C
-	select SND_SOC_POWERPC_SSI
+	select SND_SOC_FSL_SSI
+	select SND_SOC_POWERPC_DMA
 	select SND_SOC_WM8776
 	default y if P1022_DS
 	help
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index b4a38c0..95d483f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -9,7 +9,8 @@ obj-$(CONFIG_SND_SOC_P1022_DS) += snd-soc-p1022-ds.o
 # Freescale PowerPC SSI/DMA Platform Support
 snd-soc-fsl-ssi-objs := fsl_ssi.o
 snd-soc-fsl-dma-objs := fsl_dma.o
-obj-$(CONFIG_SND_SOC_POWERPC_SSI) += snd-soc-fsl-ssi.o snd-soc-fsl-dma.o
+obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 
 # MPC5200 Platform Support
 obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:53 +0800
Subject: [PATCH 12/20] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-13-git-send-email-shawn.guo@linaro.org>

Freescale PowerPC and ARM/IMX families share the same SSI IP block.
The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
code sharing and consolidation can happen.

This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
IMX platform.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/Kconfig                        |    1 -
 sound/soc/Makefile                       |    1 -
 sound/soc/fsl/Kconfig                    |   92 ++++++++++++++++++++++++++++++
 sound/soc/fsl/Makefile                   |   22 +++++++
 sound/soc/{imx => fsl}/eukrea-tlv320.c   |    2 +-
 sound/soc/{imx => fsl}/imx-audmux.c      |    0
 sound/soc/{imx => fsl}/imx-audmux.h      |    0
 sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c |    0
 sound/soc/{imx => fsl}/imx-pcm-fiq.c     |    0
 sound/soc/{imx => fsl}/imx-pcm.c         |    0
 sound/soc/{imx => fsl}/imx-pcm.h         |    0
 sound/soc/{imx => fsl}/imx-ssi.c         |    2 +-
 sound/soc/{imx => fsl}/imx-ssi.h         |    0
 sound/soc/{imx => fsl}/mx27vis-aic32x4.c |    0
 sound/soc/{imx => fsl}/phycore-ac97.c    |    0
 sound/soc/{imx => fsl}/wm1133-ev1.c      |    0
 sound/soc/imx/Kconfig                    |   79 -------------------------
 sound/soc/imx/Makefile                   |   22 -------
 18 files changed, 116 insertions(+), 105 deletions(-)
 rename sound/soc/{imx => fsl}/eukrea-tlv320.c (99%)
 rename sound/soc/{imx => fsl}/imx-audmux.c (100%)
 rename sound/soc/{imx => fsl}/imx-audmux.h (100%)
 rename sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm-fiq.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm.h (100%)
 rename sound/soc/{imx => fsl}/imx-ssi.c (99%)
 rename sound/soc/{imx => fsl}/imx-ssi.h (100%)
 rename sound/soc/{imx => fsl}/mx27vis-aic32x4.c (100%)
 rename sound/soc/{imx => fsl}/phycore-ac97.c (100%)
 rename sound/soc/{imx => fsl}/wm1133-ev1.c (100%)
 delete mode 100644 sound/soc/imx/Kconfig
 delete mode 100644 sound/soc/imx/Makefile

diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 91c9855..0f85f6d 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -35,7 +35,6 @@ source "sound/soc/blackfin/Kconfig"
 source "sound/soc/davinci/Kconfig"
 source "sound/soc/ep93xx/Kconfig"
 source "sound/soc/fsl/Kconfig"
-source "sound/soc/imx/Kconfig"
 source "sound/soc/jz4740/Kconfig"
 source "sound/soc/nuc900/Kconfig"
 source "sound/soc/omap/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 2feaf37..363dfd6 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_SND_SOC)	+= blackfin/
 obj-$(CONFIG_SND_SOC)	+= davinci/
 obj-$(CONFIG_SND_SOC)	+= ep93xx/
 obj-$(CONFIG_SND_SOC)	+= fsl/
-obj-$(CONFIG_SND_SOC)   += imx/
 obj-$(CONFIG_SND_SOC)	+= jz4740/
 obj-$(CONFIG_SND_SOC)	+= mid-x86/
 obj-$(CONFIG_SND_SOC)	+= mxs/
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index ca693b2..19856a0 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,3 +1,15 @@
+config SND_SOC_FSL_SSI
+	tristate
+
+menuconfig SND_POWERPC_SOC
+	tristate "SoC Audio for Freescale PowerPC CPUs"
+	depends on FSL_SOC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the PowerPC CPUs.
+
+if SND_POWERPC_SOC
+
 config SND_MPC52xx_DMA
 	tristate
 
@@ -68,3 +80,83 @@ config SND_MPC52xx_SOC_EFIKA
 	help
 	  Say Y if you want to add support for sound on the Efika.
 
+endif # SND_POWERPC_SOC
+
+menuconfig SND_IMX_SOC
+	tristate "SoC Audio for Freescale i.MX CPUs"
+	depends on ARCH_MXC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the i.MX CPUs.
+
+if SND_IMX_SOC
+
+config SND_SOC_IMX_SSI
+	tristate
+
+config SND_SOC_IMX_PCM
+	tristate
+
+config SND_MXC_SOC_FIQ
+	tristate
+	select FIQ
+	select SND_SOC_IMX_PCM
+
+config SND_MXC_SOC_MX2
+	tristate
+	select SND_SOC_DMAENGINE_PCM
+	select SND_SOC_IMX_PCM
+
+config SND_SOC_IMX_AUDMUX
+	tristate
+
+config SND_MXC_SOC_WM1133_EV1
+	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
+	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
+	select SND_SOC_WM8350
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
+	  PMIC board with WM8835x fitted.
+
+config SND_SOC_MX27VIS_AIC32X4
+	tristate "SoC audio support for Visstrim M10 boards"
+	depends on MACH_IMX27_VISSTRIM_M10 && I2C
+	select SND_SOC_TLV320AIC32X4
+	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Say Y if you want to add support for SoC audio on Visstrim SM10
+	  board with TLV320AIC32X4 codec.
+
+config SND_SOC_PHYCORE_AC97
+	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
+	depends on MACH_PCM043 || MACH_PCA100
+	select SND_SOC_AC97_BUS
+	select SND_SOC_WM9712
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Say Y if you want to add support for SoC audio on Phytec phyCORE
+	  and phyCARD boards in AC97 mode
+
+config SND_SOC_EUKREA_TLV320
+	tristate "Eukrea TLV320"
+	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
+	depends on I2C
+	select SND_SOC_TLV320AIC23
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Enable I2S based access to the TLV320AIC23B codec attached
+	  to the SSI interface
+
+endif # SND_IMX_SOC
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 95d483f..36c257f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -21,3 +21,25 @@ obj-$(CONFIG_SND_SOC_MPC5200_AC97) += mpc5200_psc_ac97.o
 obj-$(CONFIG_SND_MPC52xx_SOC_PCM030) += pcm030-audio-fabric.o
 obj-$(CONFIG_SND_MPC52xx_SOC_EFIKA) += efika-audio-fabric.o
 
+# i.MX Platform Support
+snd-soc-imx-ssi-objs := imx-ssi.o
+snd-soc-imx-audmux-objs := imx-audmux.o
+
+obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
+obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
+
+obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
+snd-soc-imx-pcm-y := imx-pcm.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
+
+# i.MX Machine Support
+snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
+snd-soc-phycore-ac97-objs := phycore-ac97.o
+snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
+snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+
+obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
+obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
+obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
+obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/fsl/eukrea-tlv320.c
similarity index 99%
rename from sound/soc/imx/eukrea-tlv320.c
rename to sound/soc/fsl/eukrea-tlv320.c
index 7d4475c..efb9ede 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/fsl/eukrea-tlv320.c
@@ -7,7 +7,7 @@
  * which is Copyright 2009 Simtec Electronics
  * and on sound/soc/imx/phycore-ac97.c which is
  * Copyright 2009 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
- * 
+ *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
  *  Free Software Foundation;  either version 2 of the  License, or (at your
diff --git a/sound/soc/imx/imx-audmux.c b/sound/soc/fsl/imx-audmux.c
similarity index 100%
rename from sound/soc/imx/imx-audmux.c
rename to sound/soc/fsl/imx-audmux.c
diff --git a/sound/soc/imx/imx-audmux.h b/sound/soc/fsl/imx-audmux.h
similarity index 100%
rename from sound/soc/imx/imx-audmux.h
rename to sound/soc/fsl/imx-audmux.h
diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/fsl/imx-pcm-dma-mx2.c
similarity index 100%
rename from sound/soc/imx/imx-pcm-dma-mx2.c
rename to sound/soc/fsl/imx-pcm-dma-mx2.c
diff --git a/sound/soc/imx/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
similarity index 100%
rename from sound/soc/imx/imx-pcm-fiq.c
rename to sound/soc/fsl/imx-pcm-fiq.c
diff --git a/sound/soc/imx/imx-pcm.c b/sound/soc/fsl/imx-pcm.c
similarity index 100%
rename from sound/soc/imx/imx-pcm.c
rename to sound/soc/fsl/imx-pcm.c
diff --git a/sound/soc/imx/imx-pcm.h b/sound/soc/fsl/imx-pcm.h
similarity index 100%
rename from sound/soc/imx/imx-pcm.h
rename to sound/soc/fsl/imx-pcm.h
diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
similarity index 99%
rename from sound/soc/imx/imx-ssi.c
rename to sound/soc/fsl/imx-ssi.c
index 4f81ed4..cf3ed03 100644
--- a/sound/soc/imx/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -28,7 +28,7 @@
  * value. When we read the same register two times (and the register still
  * contains the same value) these status bits are not set. We work
  * around this by not polling these bits but only wait a fixed delay.
- * 
+ *
  */
 
 #include <linux/clk.h>
diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/fsl/imx-ssi.h
similarity index 100%
rename from sound/soc/imx/imx-ssi.h
rename to sound/soc/fsl/imx-ssi.h
diff --git a/sound/soc/imx/mx27vis-aic32x4.c b/sound/soc/fsl/mx27vis-aic32x4.c
similarity index 100%
rename from sound/soc/imx/mx27vis-aic32x4.c
rename to sound/soc/fsl/mx27vis-aic32x4.c
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/fsl/phycore-ac97.c
similarity index 100%
rename from sound/soc/imx/phycore-ac97.c
rename to sound/soc/fsl/phycore-ac97.c
diff --git a/sound/soc/imx/wm1133-ev1.c b/sound/soc/fsl/wm1133-ev1.c
similarity index 100%
rename from sound/soc/imx/wm1133-ev1.c
rename to sound/soc/fsl/wm1133-ev1.c
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
deleted file mode 100644
index 810acaa..0000000
--- a/sound/soc/imx/Kconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-menuconfig SND_IMX_SOC
-	tristate "SoC Audio for Freescale i.MX CPUs"
-	depends on ARCH_MXC
-	help
-	  Say Y or M if you want to add support for codecs attached to
-	  the i.MX SSI interface.
-
-
-if SND_IMX_SOC
-
-config SND_SOC_IMX_SSI
-	tristate
-
-config SND_SOC_IMX_PCM
-	tristate
-
-config SND_MXC_SOC_FIQ
-	tristate
-	select FIQ
-	select SND_SOC_IMX_PCM
-
-config SND_MXC_SOC_MX2
-	select SND_SOC_DMAENGINE_PCM
-	tristate
-	select SND_SOC_IMX_PCM
-
-config SND_SOC_IMX_AUDMUX
-	tristate
-
-config SND_MXC_SOC_WM1133_EV1
-	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
-	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
-	select SND_SOC_WM8350
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
-	  PMIC board with WM8835x fitted.
-
-config SND_SOC_MX27VIS_AIC32X4
-	tristate "SoC audio support for Visstrim M10 boards"
-	depends on MACH_IMX27_VISSTRIM_M10 && I2C
-	select SND_SOC_TLV320AIC32X4
-	select SND_MXC_SOC_MX2
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Say Y if you want to add support for SoC audio on Visstrim SM10
-	  board with TLV320AIC32X4 codec.
-
-config SND_SOC_PHYCORE_AC97
-	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
-	depends on MACH_PCM043 || MACH_PCA100
-	select SND_SOC_AC97_BUS
-	select SND_SOC_WM9712
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Say Y if you want to add support for SoC audio on Phytec phyCORE
-	  and phyCARD boards in AC97 mode
-
-config SND_SOC_EUKREA_TLV320
-	tristate "Eukrea TLV320"
-	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
-	depends on I2C
-	select SND_SOC_TLV320AIC23
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Enable I2S based access to the TLV320AIC23B codec attached
-	  to the SSI interface
-
-endif	# SND_IMX_SOC
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
deleted file mode 100644
index f5db3e9..0000000
--- a/sound/soc/imx/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-# i.MX Platform Support
-snd-soc-imx-ssi-objs := imx-ssi.o
-snd-soc-imx-audmux-objs := imx-audmux.o
-
-obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
-obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
-
-obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
-snd-soc-imx-pcm-y := imx-pcm.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
-
-# i.MX Machine Support
-snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
-snd-soc-phycore-ac97-objs := phycore-ac97.o
-snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
-snd-soc-wm1133-ev1-objs := wm1133-ev1.o
-
-obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
-obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
-obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
-obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:54 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:54 +0800
Subject: [PATCH 13/20] ASoC: fsl: create fsl_utils to accommodate the common
 functions
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-14-git-send-email-shawn.guo@linaro.org>

There is some amount of code duplication between mpc8610_hpcd and
p1022_ds machine drivers, and the same code will be duplicated again
when another new machine driver is added.  The patch creates fsl_utils
to accommodate the common functions to stop the code duplication.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/Kconfig        |    5 ++
 sound/soc/fsl/Makefile       |    2 +
 sound/soc/fsl/fsl_utils.c    |  135 ++++++++++++++++++++++++++++++++++++
 sound/soc/fsl/fsl_utils.h    |   27 +++++++
 sound/soc/fsl/mpc8610_hpcd.c |  157 +++---------------------------------------
 sound/soc/fsl/p1022_ds.c     |  149 +++-------------------------------------
 6 files changed, 189 insertions(+), 286 deletions(-)
 create mode 100644 sound/soc/fsl/fsl_utils.c
 create mode 100644 sound/soc/fsl/fsl_utils.h

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 19856a0..e579671 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,6 +1,9 @@
 config SND_SOC_FSL_SSI
 	tristate
 
+config SND_SOC_FSL_UTILS
+	tristate
+
 menuconfig SND_POWERPC_SOC
 	tristate "SoC Audio for Freescale PowerPC CPUs"
 	depends on FSL_SOC
@@ -26,6 +29,7 @@ config SND_SOC_MPC8610_HPCD
 	# I2C is necessary for the CS4270 driver
 	depends on MPC8610_HPCD && I2C
 	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
 	select SND_SOC_POWERPC_DMA
 	select SND_SOC_CS4270
 	select SND_SOC_CS4270_VD33_ERRATA
@@ -38,6 +42,7 @@ config SND_SOC_P1022_DS
 	# I2C is necessary for the WM8776 driver
 	depends on P1022_DS && I2C
 	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
 	select SND_SOC_POWERPC_DMA
 	select SND_SOC_WM8776
 	default y if P1022_DS
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 36c257f..02b3e53 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -8,8 +8,10 @@ obj-$(CONFIG_SND_SOC_P1022_DS) += snd-soc-p1022-ds.o
 
 # Freescale PowerPC SSI/DMA Platform Support
 snd-soc-fsl-ssi-objs := fsl_ssi.o
+snd-soc-fsl-utils-objs := fsl_utils.o
 snd-soc-fsl-dma-objs := fsl_dma.o
 obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
 obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 
 # MPC5200 Platform Support
diff --git a/sound/soc/fsl/fsl_utils.c b/sound/soc/fsl/fsl_utils.c
new file mode 100644
index 0000000..4370c28
--- /dev/null
+++ b/sound/soc/fsl/fsl_utils.c
@@ -0,0 +1,135 @@
+/**
+ * Freescale ALSA SoC Machine driver utility
+ *
+ * Author: Timur Tabi <timur at freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_i2c.h>
+#include <sound/soc.h>
+
+#include "fsl_utils.h"
+
+/**
+ * fsl_asoc_get_codec_dev_name - determine the dev_name for a codec node
+ *
+ * @np: pointer to the I2C device tree node
+ * @buf: buffer to be filled with the dev_name of the I2C device
+ * @len: the length of the buffer
+ *
+ * This function determines the dev_name for an I2C node.  This is the name
+ * that would be returned by dev_name() if this device_node were part of a
+ * 'struct device'  It's ugly and hackish, but it works.
+ *
+ * The dev_name for such devices include the bus number and I2C address. For
+ * example, "cs4270.0-004f".
+ */
+int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len)
+{
+	const u32 *iprop;
+	u32 addr;
+	char temp[DAI_NAME_SIZE];
+	struct i2c_client *i2c;
+
+	of_modalias_node(np, temp, DAI_NAME_SIZE);
+
+	iprop = of_get_property(np, "reg", NULL);
+	if (!iprop)
+		return -EINVAL;
+
+	addr = be32_to_cpup(iprop);
+
+	/* We need the adapter number */
+	i2c = of_find_i2c_device_by_node(np);
+	if (!i2c) {
+		put_device(&i2c->dev);
+		return -ENODEV;
+	}
+
+	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
+	put_device(&i2c->dev);
+
+	return 0;
+}
+EXPORT_SYMBOL(fsl_asoc_get_codec_dev_name);
+
+/**
+ * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
+ *
+ * @ssi_np: pointer to the SSI device tree node
+ * @name: name of the phandle pointing to the dma channel
+ * @dai: ASoC DAI link pointer to be filled with platform_name
+ * @dma_channel_id: dma channel id to be returned
+ * @dma_id: dma id to be returned
+ *
+ * This function determines the dma and channel id for given SSI node.  It
+ * also discovers the platform_name for the ASoC DAI link.
+ */
+int fsl_asoc_get_dma_channel(struct device_node *ssi_np,
+			     const char *name,
+			     struct snd_soc_dai_link *dai,
+			     unsigned int *dma_channel_id,
+			     unsigned int *dma_id)
+{
+	struct resource res;
+	struct device_node *dma_channel_np, *dma_np;
+	const u32 *iprop;
+	int ret;
+
+	dma_channel_np = of_parse_phandle(ssi_np, name, 0);
+	if (!dma_channel_np)
+		return -EINVAL;
+
+	if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) {
+		of_node_put(dma_channel_np);
+		return -EINVAL;
+	}
+
+	/* Determine the dev_name for the device_node.  This code mimics the
+	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
+	 * the dev_name() of the device to match the platform (DMA) device with
+	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
+	 * now).
+	 *
+	 * dai->platform name should already point to an allocated buffer.
+	 */
+	ret = of_address_to_resource(dma_channel_np, 0, &res);
+	if (ret) {
+		of_node_put(dma_channel_np);
+		return ret;
+	}
+	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
+		 (unsigned long long) res.start, dma_channel_np->name);
+
+	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
+	if (!iprop) {
+		of_node_put(dma_channel_np);
+		return -EINVAL;
+	}
+	*dma_channel_id = be32_to_cpup(iprop);
+
+	dma_np = of_get_parent(dma_channel_np);
+	iprop = of_get_property(dma_np, "cell-index", NULL);
+	if (!iprop) {
+		of_node_put(dma_np);
+		return -EINVAL;
+	}
+	*dma_id = be32_to_cpup(iprop);
+
+	of_node_put(dma_np);
+	of_node_put(dma_channel_np);
+
+	return 0;
+}
+EXPORT_SYMBOL(fsl_asoc_get_dma_channel);
+
+MODULE_AUTHOR("Timur Tabi <timur at freescale.com>");
+MODULE_DESCRIPTION("Freescale ASoC utility code");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/fsl/fsl_utils.h b/sound/soc/fsl/fsl_utils.h
new file mode 100644
index 0000000..44d1436
--- /dev/null
+++ b/sound/soc/fsl/fsl_utils.h
@@ -0,0 +1,27 @@
+/**
+ * Freescale ALSA SoC Machine driver utility
+ *
+ * Author: Timur Tabi <timur at freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef _FSL_UTILS_H
+#define _FSL_UTILS_H
+
+#define DAI_NAME_SIZE	32
+
+struct snd_soc_dai_link;
+struct device_node;
+
+int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len);
+int fsl_asoc_get_dma_channel(struct device_node *ssi_np, const char *name,
+			     struct snd_soc_dai_link *dai,
+			     unsigned int *dma_channel_id,
+			     unsigned int *dma_id);
+
+#endif /* _FSL_UTILS_H */
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index fcf9302..7ead1e5 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -14,18 +14,16 @@
 #include <linux/interrupt.h>
 #include <linux/of_device.h>
 #include <linux/slab.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 #include <asm/fsl_guts.h>
 
 #include "fsl_dma.h"
 #include "fsl_ssi.h"
+#include "fsl_utils.h"
 
 /* There's only one global utilities register */
 static phys_addr_t guts_phys;
 
-#define DAI_NAME_SIZE	32
-
 /**
  * mpc8610_hpcd_data: machine-specific ASoC device data
  *
@@ -181,141 +179,6 @@ static struct snd_soc_ops mpc8610_hpcd_ops = {
 };
 
 /**
- * get_node_by_phandle_name - get a node by its phandle name
- *
- * This function takes a node, the name of a property in that node, and a
- * compatible string.  Assuming the property is a phandle to another node,
- * it returns that node, (optionally) if that node is compatible.
- *
- * If the property is not a phandle, or the node it points to is not compatible
- * with the specific string, then NULL is returned.
- */
-static struct device_node *get_node_by_phandle_name(struct device_node *np,
-					       const char *name,
-					       const char *compatible)
-{
-	const phandle *ph;
-	int len;
-
-	ph = of_get_property(np, name, &len);
-	if (!ph || (len != sizeof(phandle)))
-		return NULL;
-
-	np = of_find_node_by_phandle(*ph);
-	if (!np)
-		return NULL;
-
-	if (compatible && !of_device_is_compatible(np, compatible)) {
-		of_node_put(np);
-		return NULL;
-	}
-
-	return np;
-}
-
-/**
- * get_parent_cell_index -- return the cell-index of the parent of a node
- *
- * Return the value of the cell-index property of the parent of the given
- * node.  This is used for DMA channel nodes that need to know the DMA ID
- * of the controller they are on.
- */
-static int get_parent_cell_index(struct device_node *np)
-{
-	struct device_node *parent = of_get_parent(np);
-	const u32 *iprop;
-
-	if (!parent)
-		return -1;
-
-	iprop = of_get_property(parent, "cell-index", NULL);
-	of_node_put(parent);
-
-	if (!iprop)
-		return -1;
-
-	return be32_to_cpup(iprop);
-}
-
-/**
- * codec_node_dev_name - determine the dev_name for a codec node
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270.0-004f".
- */
-static int codec_node_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	int addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c)
-		return -ENODEV;
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-
-	return 0;
-}
-
-static int get_dma_channel(struct device_node *ssi_np,
-			   const char *name,
-			   struct snd_soc_dai_link *dai,
-			   unsigned int *dma_channel_id,
-			   unsigned int *dma_id)
-{
-	struct resource res;
-	struct device_node *dma_channel_np;
-	const u32 *iprop;
-	int ret;
-
-	dma_channel_np = get_node_by_phandle_name(ssi_np, name,
-						  "fsl,ssi-dma-channel");
-	if (!dma_channel_np)
-		return -EINVAL;
-
-	/* Determine the dev_name for the device_node.  This code mimics the
-	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
-	 * the dev_name() of the device to match the platform (DMA) device with
-	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
-	 * now).
-	 *
-	 * dai->platform name should already point to an allocated buffer.
-	 */
-	ret = of_address_to_resource(dma_channel_np, 0, &res);
-	if (ret)
-		return ret;
-	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
-		 (unsigned long long) res.start, dma_channel_np->name);
-
-	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
-	if (!iprop) {
-		of_node_put(dma_channel_np);
-		return -EINVAL;
-	}
-
-	*dma_channel_id = be32_to_cpup(iprop);
-	*dma_id = get_parent_cell_index(dma_channel_np);
-	of_node_put(dma_channel_np);
-
-	return 0;
-}
-
-/**
  * mpc8610_hpcd_probe: platform probe function for the machine driver
  *
  * Although this is a machine driver, the SSI node is the "master" node with
@@ -353,8 +216,8 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 	machine_data->dai[0].ops = &mpc8610_hpcd_ops;
 
 	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = codec_node_dev_name(codec_np, machine_data->codec_name,
-				  DAI_NAME_SIZE);
+	ret = fsl_asoc_get_codec_dev_name(codec_np, machine_data->codec_name,
+					  DAI_NAME_SIZE);
 	if (ret) {
 		dev_err(&pdev->dev, "invalid codec node %s\n",
 			codec_np->full_name);
@@ -458,9 +321,10 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 
 	/* Find the playback DMA channel to use. */
 	machine_data->dai[0].platform_name = machine_data->platform_name[0];
-	ret = get_dma_channel(np, "fsl,playback-dma", &machine_data->dai[0],
-			      &machine_data->dma_channel_id[0],
-			      &machine_data->dma_id[0]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma",
+				       &machine_data->dai[0],
+				       &machine_data->dma_channel_id[0],
+				       &machine_data->dma_id[0]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
 		goto error;
@@ -468,9 +332,10 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 
 	/* Find the capture DMA channel to use. */
 	machine_data->dai[1].platform_name = machine_data->platform_name[1];
-	ret = get_dma_channel(np, "fsl,capture-dma", &machine_data->dai[1],
-			      &machine_data->dma_channel_id[1],
-			      &machine_data->dma_id[1]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma",
+				       &machine_data->dai[1],
+				       &machine_data->dma_channel_id[1],
+				       &machine_data->dma_id[1]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
 		goto error;
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index d32ec46..60f7bb8 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -14,12 +14,12 @@
 #include <linux/interrupt.h>
 #include <linux/of_device.h>
 #include <linux/slab.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 #include <asm/fsl_guts.h>
 
 #include "fsl_dma.h"
 #include "fsl_ssi.h"
+#include "fsl_utils.h"
 
 /* P1022-specific PMUXCR and DMUXCR bit definitions */
 
@@ -57,8 +57,6 @@ static inline void guts_set_dmuxcr(struct ccsr_guts_85xx __iomem *guts,
 /* There's only one global utilities register */
 static phys_addr_t guts_phys;
 
-#define DAI_NAME_SIZE	32
-
 /**
  * machine_data: machine-specific ASoC device data
  *
@@ -191,136 +189,6 @@ static struct snd_soc_ops p1022_ds_ops = {
 };
 
 /**
- * get_node_by_phandle_name - get a node by its phandle name
- *
- * This function takes a node, the name of a property in that node, and a
- * compatible string.  Assuming the property is a phandle to another node,
- * it returns that node, (optionally) if that node is compatible.
- *
- * If the property is not a phandle, or the node it points to is not compatible
- * with the specific string, then NULL is returned.
- */
-static struct device_node *get_node_by_phandle_name(struct device_node *np,
-	const char *name, const char *compatible)
-{
-	np = of_parse_phandle(np, name, 0);
-	if (!np)
-		return NULL;
-
-	if (!of_device_is_compatible(np, compatible)) {
-		of_node_put(np);
-		return NULL;
-	}
-
-	return np;
-}
-
-/**
- * get_parent_cell_index -- return the cell-index of the parent of a node
- *
- * Return the value of the cell-index property of the parent of the given
- * node.  This is used for DMA channel nodes that need to know the DMA ID
- * of the controller they are on.
- */
-static int get_parent_cell_index(struct device_node *np)
-{
-	struct device_node *parent = of_get_parent(np);
-	const u32 *iprop;
-	int ret = -1;
-
-	if (!parent)
-		return -1;
-
-	iprop = of_get_property(parent, "cell-index", NULL);
-	if (iprop)
-		ret = be32_to_cpup(iprop);
-
-	of_node_put(parent);
-
-	return ret;
-}
-
-/**
- * codec_node_dev_name - determine the dev_name for a codec node
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270-codec.0-004f".
- */
-static int codec_node_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	int addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c)
-		return -ENODEV;
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-
-	return 0;
-}
-
-static int get_dma_channel(struct device_node *ssi_np,
-			   const char *name,
-			   struct snd_soc_dai_link *dai,
-			   unsigned int *dma_channel_id,
-			   unsigned int *dma_id)
-{
-	struct resource res;
-	struct device_node *dma_channel_np;
-	const u32 *iprop;
-	int ret;
-
-	dma_channel_np = get_node_by_phandle_name(ssi_np, name,
-						  "fsl,ssi-dma-channel");
-	if (!dma_channel_np)
-		return -EINVAL;
-
-	/* Determine the dev_name for the device_node.  This code mimics the
-	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
-	 * the dev_name() of the device to match the platform (DMA) device with
-	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
-	 * now).
-	 *
-	 * dai->platform name should already point to an allocated buffer.
-	 */
-	ret = of_address_to_resource(dma_channel_np, 0, &res);
-	if (ret) {
-		of_node_put(dma_channel_np);
-		return ret;
-	}
-	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
-		 (unsigned long long) res.start, dma_channel_np->name);
-
-	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
-	if (!iprop) {
-		of_node_put(dma_channel_np);
-		return -EINVAL;
-	}
-
-	*dma_channel_id = be32_to_cpup(iprop);
-	*dma_id = get_parent_cell_index(dma_channel_np);
-	of_node_put(dma_channel_np);
-
-	return 0;
-}
-
-/**
  * p1022_ds_probe: platform probe function for the machine driver
  *
  * Although this is a machine driver, the SSI node is the "master" node with
@@ -358,7 +226,8 @@ static int p1022_ds_probe(struct platform_device *pdev)
 	mdata->dai[0].ops = &p1022_ds_ops;
 
 	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = codec_node_dev_name(codec_np, mdata->codec_name, DAI_NAME_SIZE);
+	ret = fsl_asoc_get_codec_dev_name(codec_np, mdata->codec_name,
+					  DAI_NAME_SIZE);
 	if (ret) {
 		dev_err(&pdev->dev, "invalid codec node %s\n",
 			codec_np->full_name);
@@ -454,9 +323,9 @@ static int p1022_ds_probe(struct platform_device *pdev)
 
 	/* Find the playback DMA channel to use. */
 	mdata->dai[0].platform_name = mdata->platform_name[0];
-	ret = get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
-			      &mdata->dma_channel_id[0],
-			      &mdata->dma_id[0]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
+				       &mdata->dma_channel_id[0],
+				       &mdata->dma_id[0]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
 		goto error;
@@ -464,9 +333,9 @@ static int p1022_ds_probe(struct platform_device *pdev)
 
 	/* Find the capture DMA channel to use. */
 	mdata->dai[1].platform_name = mdata->platform_name[1];
-	ret = get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
-			      &mdata->dma_channel_id[1],
-			      &mdata->dma_id[1]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
+				       &mdata->dma_channel_id[1],
+				       &mdata->dma_id[1]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
 		goto error;
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:55 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:55 +0800
Subject: [PATCH 14/20] ASoC: fsl: check property 'compatible' for the machine
 name
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-15-git-send-email-shawn.guo@linaro.org>

Check /compatible rather than /model to determine the machine name.
The p1022ds older device trees get a different /model from the new
ones, while /compatible is consistent there, so checking /compatible
will save the bother of detecting older p1022ds device trees.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c      |    6 +++---
 sound/soc/fsl/mpc8610_hpcd.c |    2 +-
 sound/soc/fsl/p1022_ds.c     |   32 +++++---------------------------
 3 files changed, 9 insertions(+), 31 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 3e06696..2eb407f 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -716,12 +716,12 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 	}
 
 	/* Trigger the machine driver's probe function.  The platform driver
-	 * name of the machine driver is taken from the /model property of the
+	 * name of the machine driver is taken from /compatible property of the
 	 * device tree.  We also pass the address of the CPU DAI driver
 	 * structure.
 	 */
-	sprop = of_get_property(of_find_node_by_path("/"), "model", NULL);
-	/* Sometimes the model name has a "fsl," prefix, so we strip that. */
+	sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
+	/* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
 	p = strrchr(sprop, ',');
 	if (p)
 		sprop = p + 1;
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index 7ead1e5..4195182 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -411,7 +411,7 @@ static struct platform_driver mpc8610_hpcd_driver = {
 	.probe = mpc8610_hpcd_probe,
 	.remove = __devexit_p(mpc8610_hpcd_remove),
 	.driver = {
-		/* The name must match the 'model' property in the device tree,
+		/* The name must match 'compatible' property in the device tree,
 		 * in lowercase letters.
 		 */
 		.name = "snd-soc-mpc8610hpcd",
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index 60f7bb8..e3680ce 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -412,6 +412,11 @@ static struct platform_driver p1022_ds_driver = {
 	.probe = p1022_ds_probe,
 	.remove = __devexit_p(p1022_ds_remove),
 	.driver = {
+		/*
+		 * The name must match 'compatible' property in the device tree,
+		 * in lowercase letters.
+		 */
+		.name = "snd-soc-p1022ds",
 		.owner = THIS_MODULE,
 	},
 };
@@ -425,33 +430,6 @@ static int __init p1022_ds_init(void)
 {
 	struct device_node *guts_np;
 	struct resource res;
-	const char *sprop;
-
-	/*
-	 * Check if we're actually running on a P1022DS.  Older device trees
-	 * have a model of "fsl,P1022" and newer ones use "fsl,P1022DS", so we
-	 * need to support both.  The SSI driver uses that property to link to
-	 * the machine driver, so have to match it.
-	 */
-	sprop = of_get_property(of_find_node_by_path("/"), "model", NULL);
-	if (!sprop) {
-		pr_err("snd-soc-p1022ds: missing /model node");
-		return -ENODEV;
-	}
-
-	pr_debug("snd-soc-p1022ds: board model name is %s\n", sprop);
-
-	/*
-	 * The name of this board, taken from the device tree.  Normally, this is a*
-	 * fixed string, but some P1022DS device trees have a /model property of
-	 * "fsl,P1022", and others have "fsl,P1022DS".
-	 */
-	if (strcasecmp(sprop, "fsl,p1022ds") == 0)
-		p1022_ds_driver.driver.name = "snd-soc-p1022ds";
-	else if (strcasecmp(sprop, "fsl,p1022") == 0)
-		p1022_ds_driver.driver.name = "snd-soc-p1022";
-	else
-		return -ENODEV;
 
 	/* Get the physical address of the global utilities registers */
 	guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:56 +0800
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>

Provide different pair of accessors for accessing SSI registers on
PowerPC and ARM/IMX, so that fsl_ssi driver can be built on both
architectures.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |   83 ++++++++++++++++++++++++++++++----------------
 1 files changed, 54 insertions(+), 29 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 2eb407f..0b53682 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -11,11 +11,14 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 
 #include <sound/core.h>
@@ -26,6 +29,14 @@
 
 #include "fsl_ssi.h"
 
+#ifdef PPC
+#define read_ssi(addr)		in_be32(addr)
+#define write_ssi(val, addr)	out_be32(addr, val)
+#elif defined ARM
+#define read_ssi(addr)		readl(addr)
+#define write_ssi(val, addr)	writel(val, addr)
+#endif
+
 /**
  * FSLSSI_I2S_RATES: sample rates supported by the I2S
  *
@@ -145,7 +156,7 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 	   were interrupted for.  We mask it with the Interrupt Enable register
 	   so that we only check for events that we're interested in.
 	 */
-	sisr = in_be32(&ssi->sisr) & SIER_FLAGS;
+	sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
 
 	if (sisr & CCSR_SSI_SISR_RFRC) {
 		ssi_private->stats.rfrc++;
@@ -260,7 +271,7 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 
 	/* Clear the bits that we set */
 	if (sisr2)
-		out_be32(&ssi->sisr, sisr2);
+		write_ssi(sisr2, &ssi->sisr);
 
 	return ret;
 }
@@ -280,6 +291,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 	struct fsl_ssi_private *ssi_private =
 		snd_soc_dai_get_drvdata(rtd->cpu_dai);
 	int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
+	u32 val;
 
 	/*
 	 * If this is the first stream opened, then request the IRQ
@@ -295,7 +307,9 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 * SSI needs to be disabled before updating the registers we set
 		 * here.
 		 */
-		clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
+		val = read_ssi(&ssi->scr);
+		val &= ~CCSR_SSI_SCR_SSIEN;
+		write_ssi(val, &ssi->scr);
 
 		/*
 		 * Program the SSI into I2S Slave Non-Network Synchronous mode.
@@ -303,20 +317,19 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 *
 		 * FIXME: Little-endian samples require a different shift dir
 		 */
-		clrsetbits_be32(&ssi->scr,
-			CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
-			CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE
-			| (synchronous ? CCSR_SSI_SCR_SYN : 0));
+		val = read_ssi(&ssi->scr);
+		val &= ~(CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN);
+		val |= CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE |
+		       (synchronous ? CCSR_SSI_SCR_SYN : 0);
+		write_ssi(val, &ssi->scr);
 
-		out_be32(&ssi->stcr,
-			 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
+		write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
 			 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
-			 CCSR_SSI_STCR_TSCKP);
+			 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
 
-		out_be32(&ssi->srcr,
-			 CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
+		write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
 			 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
-			 CCSR_SSI_SRCR_RSCKP);
+			 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
 
 		/*
 		 * The DC and PM bits are only used if the SSI is the clock
@@ -324,7 +337,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 */
 
 		/* Enable the interrupts and DMA requests */
-		out_be32(&ssi->sier, SIER_FLAGS);
+		write_ssi(SIER_FLAGS, &ssi->sier);
 
 		/*
 		 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
@@ -339,9 +352,9 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 * make this value larger (and maybe we should), but this way
 		 * data will be written to memory as soon as it's available.
 		 */
-		out_be32(&ssi->sfcsr,
-			CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
-			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2));
+		write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
+			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2),
+			&ssi->sfcsr);
 
 		/*
 		 * We keep the SSI disabled because if we enable it, then the
@@ -417,7 +430,8 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 	unsigned int sample_size =
 		snd_pcm_format_width(params_format(hw_params));
 	u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
-	int enabled = in_be32(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
+	int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
+	u32 val;
 
 	/*
 	 * If we're in synchronous mode, and the SSI is already enabled,
@@ -438,10 +452,17 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 
 	/* In synchronous mode, the SSI uses STCCR for capture */
 	if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
-	    ssi_private->cpu_dai_drv.symmetric_rates)
-		clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
-	else
-		clrsetbits_be32(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+	    ssi_private->cpu_dai_drv.symmetric_rates) {
+		val = read_ssi(&ssi->stccr);
+		val &= CCSR_SSI_SxCCR_WL_MASK;
+		val |= wl;
+		write_ssi(val, &ssi->stccr);
+	} else {
+		val = read_ssi(&ssi->srccr);
+		val &= CCSR_SSI_SxCCR_WL_MASK;
+		val |= wl;
+		write_ssi(val, &ssi->srccr);
+	}
 
 	return 0;
 }
@@ -461,29 +482,30 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
 	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
 	struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+	u32 val;
 
+	val = read_ssi(&ssi->scr);
 	switch (cmd) {
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-			setbits32(&ssi->scr,
-				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
+			val |= CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
 		else
-			setbits32(&ssi->scr,
-				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
+			val |= CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
 		break;
 
 	case SNDRV_PCM_TRIGGER_STOP:
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-			clrbits32(&ssi->scr, CCSR_SSI_SCR_TE);
+			val &= ~CCSR_SSI_SCR_TE;
 		else
-			clrbits32(&ssi->scr, CCSR_SSI_SCR_RE);
+			val &= ~CCSR_SSI_SCR_RE;
 		break;
 
 	default:
 		return -EINVAL;
 	}
+	write_ssi(val, &ssi->scr);
 
 	return 0;
 }
@@ -498,6 +520,7 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
 {
 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
 	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+	u32 val;
 
 	if (ssi_private->first_stream == substream)
 		ssi_private->first_stream = ssi_private->second_stream;
@@ -510,7 +533,9 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
 	if (!ssi_private->first_stream) {
 		struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 
-		clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
+		val = read_ssi(&ssi->scr);
+		val &= ~CCSR_SSI_SCR_SSIEN;
+		write_ssi(val, &ssi->scr);
 	}
 }
 
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:57 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:57 +0800
Subject: [PATCH 16/20] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-17-git-send-email-shawn.guo@linaro.org>

As Documentation/devicetree/bindings/powerpc/fsl/ssi.txt documented,
codec-handle is an optional property, so missing it should not be a
fatal error.

More importantly, the imx machine drivers to be added working with
fsl_ssi will not have this property, as they use new ASoC machine
driver binding mechanism.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 0b53682..9846091 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -647,12 +647,6 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 	if (!of_device_is_available(np))
 		return -ENODEV;
 
-	/* Check for a codec-handle property. */
-	if (!of_get_property(np, "codec-handle", NULL)) {
-		dev_err(&pdev->dev, "missing codec-handle property\n");
-		return -ENODEV;
-	}
-
 	/* We only support the SSI in "I2S Slave" mode */
 	sprop = of_get_property(np, "fsl,mode", NULL);
 	if (!sprop || strcmp(sprop, "i2s-slave")) {
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:58 +0800
Subject: [PATCH 17/20] ASoC: fsl: let fsl_ssi work with imx pcm and machine
 drivers
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-18-git-send-email-shawn.guo@linaro.org>

Makes necessary changes on fsl_ssi to let it work with imx pcm and
machine drivers.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |   51 +++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 9846091..270fc81 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -28,6 +28,7 @@
 #include <sound/soc.h>
 
 #include "fsl_ssi.h"
+#include "imx-pcm.h"
 
 #ifdef PPC
 #define read_ssi(addr)		in_be32(addr)
@@ -105,6 +106,10 @@ struct fsl_ssi_private {
 	struct device_attribute dev_attr;
 	struct platform_device *pdev;
 
+	int ssi_on_imx;
+	struct imx_pcm_dma_params dma_params_tx;
+	struct imx_pcm_dma_params dma_params_rx;
+
 	struct {
 		unsigned int rfrc;
 		unsigned int tfrc;
@@ -406,6 +411,12 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		ssi_private->second_stream = substream;
 	}
 
+	if (ssi_private->ssi_on_imx)
+		snd_soc_dai_set_dma_data(dai, substream,
+			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+				&ssi_private->dma_params_tx :
+				&ssi_private->dma_params_rx);
+
 	return 0;
 }
 
@@ -711,6 +722,38 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
                 /* Older 8610 DTs didn't have the fifo-depth property */
 		ssi_private->fifo_depth = 8;
 
+	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx1-ssi")) {
+		u32 dma_events[2];
+		ssi_private->ssi_on_imx = 1;
+		/*
+		 * FIXME: The dma burst size must equal to ssi watermark
+		 * setting on imx.  We have burstsize be "fifo_depth - 2"
+		 * here because "fifo_depth - 2" rather than fifo_depth is
+		 * being written into watermark register in fsl_ssi_startup().
+		 * Is this something needs to be fixed for PowerPC?
+		 */
+		ssi_private->dma_params_tx.burstsize =
+			ssi_private->fifo_depth - 2;
+		ssi_private->dma_params_rx.burstsize =
+			ssi_private->fifo_depth - 2;
+		ssi_private->dma_params_tx.dma_addr =
+			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
+		ssi_private->dma_params_rx.dma_addr =
+			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
+		/*
+		 * TODO: This is a temporary solution and should be changed
+		 * to use generic DMA binding later when the helplers get in.
+		 */
+		ret = of_property_read_u32_array(pdev->dev.of_node,
+					"fsl,ssi-dma-events", dma_events, 2);
+		if (ret) {
+			dev_err(&pdev->dev, "could not get dma events\n");
+			goto error_irq;
+		}
+		ssi_private->dma_params_tx.dma = dma_events[0];
+		ssi_private->dma_params_rx.dma = dma_events[1];
+	}
+
 	/* Initialize the the device_attribute structure */
 	dev_attr = &ssi_private->dev_attr;
 	sysfs_attr_init(&dev_attr->attr);
@@ -734,6 +777,13 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 		goto error_dev;
 	}
 
+	/*
+	 * All imx machine drivers use new binding which does not require
+	 * SSI driver to trigger machine driver's probe.
+	 */
+	if (ssi_private->ssi_on_imx)
+		return 0;
+
 	/* Trigger the machine driver's probe function.  The platform driver
 	 * name of the machine driver is taken from /compatible property of the
 	 * device tree.  We also pass the address of the CPU DAI driver
@@ -798,6 +848,7 @@ static int fsl_ssi_remove(struct platform_device *pdev)
 
 static const struct of_device_id fsl_ssi_ids[] = {
 	{ .compatible = "fsl,mpc8610-ssi", },
+	{ .compatible = "fsl,imx1-ssi", },
 	{}
 };
 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:19:59 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:19:59 +0800
Subject: [PATCH 18/20] ASoC: fsl: add dt support for imx-audmux
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-19-git-send-email-shawn.guo@linaro.org>

From: Richard Zhao <richard.zhao at linaro.org>

It adds device tree probe support for imx-audmux driver.

Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../devicetree/bindings/sound/imx-audmux.txt       |   13 +++++++++++++
 sound/soc/fsl/imx-audmux.c                         |   14 ++++++++++++++
 2 files changed, 27 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/imx-audmux.txt

diff --git a/Documentation/devicetree/bindings/sound/imx-audmux.txt b/Documentation/devicetree/bindings/sound/imx-audmux.txt
new file mode 100644
index 0000000..215aa98
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audmux.txt
@@ -0,0 +1,13 @@
+Freescale Digital Audio Mux (AUDMUX) device
+
+Required properties:
+- compatible : "fsl,imx21-audmux" for AUDMUX version firstly used on i.MX21,
+  or "fsl,imx31-audmux" for the version firstly used on i.MX31.
+- reg : Should contain AUDMUX registers location and length
+
+Example:
+
+audmux at 021d8000 {
+	compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
+	reg = <0x021d8000 0x4000>;
+};
diff --git a/sound/soc/fsl/imx-audmux.c b/sound/soc/fsl/imx-audmux.c
index d7bf154..bcaa7ee 100644
--- a/sound/soc/fsl/imx-audmux.c
+++ b/sound/soc/fsl/imx-audmux.c
@@ -22,6 +22,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
@@ -197,6 +199,13 @@ static struct platform_device_id imx_audmux_ids[] = {
 };
 MODULE_DEVICE_TABLE(platform, imx_audmux_ids);
 
+static const struct of_device_id imx_audmux_dt_ids[] = {
+	{ .compatible = "fsl,imx21-audmux", .data = &imx_audmux_ids[0], },
+	{ .compatible = "fsl,imx31-audmux", .data = &imx_audmux_ids[1], },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_audmux_dt_ids);
+
 static unsigned char port_mapping[] = {
 	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
 };
@@ -243,6 +252,8 @@ EXPORT_SYMBOL_GPL(imx_audmux_v2_configure_port);
 static int __init imx_audmux_probe(struct platform_device *pdev)
 {
 	struct resource *res;
+	const struct of_device_id *of_id =
+			of_match_device(imx_audmux_dt_ids, &pdev->dev);
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	audmux_base = devm_request_and_ioremap(&pdev->dev, res);
@@ -256,6 +267,8 @@ static int __init imx_audmux_probe(struct platform_device *pdev)
 		audmux_clk = NULL;
 	}
 
+	if (of_id)
+		pdev->id_entry = of_id->data;
 	audmux_type = pdev->id_entry->driver_data;
 	if (audmux_type == IMX31_AUDMUX)
 		audmux_debugfs_init();
@@ -279,6 +292,7 @@ static struct platform_driver imx_audmux_driver = {
 	.driver	= {
 		.name	= DRIVER_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = imx_audmux_dt_ids,
 	}
 };
 
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:20:00 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:20:00 +0800
Subject: [PATCH 19/20] ASoC: rename sgtl5000 device tree binding document
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-20-git-send-email-shawn.guo@linaro.org>

It moves and renames sgtl5000 device tree binding document to make
it aligned with other codecs.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../{soc/codecs/fsl-sgtl5000.txt => sgtl5000.txt}  |    0
 1 files changed, 0 insertions(+), 0 deletions(-)
 rename Documentation/devicetree/bindings/sound/{soc/codecs/fsl-sgtl5000.txt => sgtl5000.txt} (100%)

diff --git a/Documentation/devicetree/bindings/sound/soc/codecs/fsl-sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt
similarity index 100%
rename from Documentation/devicetree/bindings/sound/soc/codecs/fsl-sgtl5000.txt
rename to Documentation/devicetree/bindings/sound/sgtl5000.txt
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar  3 10:20:01 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat,  3 Mar 2012 23:20:01 +0800
Subject: [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>

This is the initial imx-sgtl5000 machine driver support with only
playback dai link implemented.  More features can be added on top
of it later.

It's a device tree only machine driver working with fsl_ssi driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../bindings/sound/imx-audio-sgtl5000.txt          |   24 +++
 sound/soc/fsl/Kconfig                              |   12 ++
 sound/soc/fsl/Makefile                             |    2 +
 sound/soc/fsl/imx-sgtl5000.c                       |  210 ++++++++++++++++++++
 4 files changed, 248 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
 create mode 100644 sound/soc/fsl/imx-sgtl5000.c

diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
new file mode 100644
index 0000000..22b3f03
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
@@ -0,0 +1,24 @@
+Freescale i.MX audio complex with SGTL5000 codec
+
+Required properties:
+- compatible : "fsl,imx-audio-sgtl5000"
+- fsl,model : The user-visible name of this sound complex
+- fsl,ssi-controller : The phandle of the i.MX SSI controller
+- fsl,audio-codec : The phandle of the SGTL5000 audio codec
+- fsl,mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
+- fsl,mux-ext-port : The external port of the i.MX audio muxer
+
+Note: The AUDMUX port numbering should start at 1, which is consistent with
+hardware manual.
+
+Example:
+
+sound {
+	compatible = "fsl,imx51-babbage-sgtl5000",
+		     "fsl,imx-audio-sgtl5000";
+	fsl,model = "imx51-babbage-sgtl5000";
+	fsl,ssi-controller = <&ssi1>;
+	fsl,audio-codec = <&sgtl5000>;
+	fsl,mux-int-port = <1>;
+	fsl,mux-ext-port = <3>;
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index e579671..42a3842 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -164,4 +164,16 @@ config SND_SOC_EUKREA_TLV320
 	  Enable I2S based access to the TLV320AIC23B codec attached
 	  to the SSI interface
 
+config SND_SOC_IMX_SGTL5000
+	tristate "SoC Audio support for i.MX boards with sgtl5000"
+	depends on OF && I2C
+	select SND_SOC_SGTL5000
+	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
+	help
+	  Say Y if you want to add support for SoC audio on an i.MX board with
+	  a sgtl5000 codec.
+
 endif # SND_IMX_SOC
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 02b3e53..5ae854b 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -40,8 +40,10 @@ snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
 snd-soc-phycore-ac97-objs := phycore-ac97.o
 snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
 snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
 
 obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
 obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
 obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
 obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
+obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
diff --git a/sound/soc/fsl/imx-sgtl5000.c b/sound/soc/fsl/imx-sgtl5000.c
new file mode 100644
index 0000000..483733f
--- /dev/null
+++ b/sound/soc/fsl/imx-sgtl5000.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <sound/soc.h>
+
+#include "../codecs/sgtl5000.h"
+#include "fsl_utils.h"
+#include "imx-audmux.h"
+
+struct imx_sgtl5000_data {
+	struct snd_soc_dai_link dai[2];
+	struct snd_soc_card card;
+	struct platform_device *pcm_audio_pdev;
+	struct platform_device *soc_audio_pdev;
+	char codec_name[DAI_NAME_SIZE];
+	char codec_dai_name[DAI_NAME_SIZE];
+	char platform_name[DAI_NAME_SIZE];
+	unsigned int clk_frequency;
+};
+
+static int imx_sgtl5000_startup(struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct imx_sgtl5000_data *data = container_of(rtd->card,
+					struct imx_sgtl5000_data, card);
+	struct device *dev = rtd->card->dev;
+	int ret;
+
+	ret = snd_soc_dai_set_fmt(rtd->codec_dai, SND_SOC_DAIFMT_I2S |
+						  SND_SOC_DAIFMT_NB_NF |
+						  SND_SOC_DAIFMT_CBM_CFM);
+	if (ret) {
+		dev_err(dev, "could not set codec driver audio format\n");
+		return ret;
+	}
+
+	ret = snd_soc_dai_set_sysclk(rtd->codec_dai, SGTL5000_SYSCLK,
+				     data->clk_frequency, SND_SOC_CLOCK_IN);
+	if (ret) {
+		dev_err(dev, "could not set codec driver clock params\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static struct snd_soc_ops imx_sgtl5000_ops = {
+	.startup = imx_sgtl5000_startup,
+};
+
+static int __devinit imx_sgtl5000_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *ssi_np, *codec_np;
+	struct platform_device *ssi_pdev;
+	struct imx_sgtl5000_data *data;
+	int int_port, ext_port;
+	int ret;
+
+	ret = of_property_read_u32(np, "fsl,mux-int-port", &int_port);
+	if (ret) {
+		dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
+		return -EINVAL;
+	}
+	ret = of_property_read_u32(np, "fsl,mux-ext-port", &ext_port);
+	if (ret) {
+		dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * The port numbering in the hardware manual starts at 1, while
+	 * the audmux API expects it starts at 0.
+	 */
+	int_port--;
+	ext_port--;
+	imx_audmux_v2_configure_port(int_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TFSDIR |
+			IMX_AUDMUX_V2_PTCR_TCLKDIR,
+			IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
+	imx_audmux_v2_configure_port(ext_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TCSEL(int_port),
+			IMX_AUDMUX_V2_PDCR_RXDSEL(int_port));
+
+	ssi_np = of_parse_phandle(pdev->dev.of_node, "fsl,ssi-controller", 0);
+	codec_np = of_parse_phandle(pdev->dev.of_node, "fsl,audio-codec", 0);
+	if (!ssi_np || !codec_np) {
+		dev_err(&pdev->dev, "phandle missing or invalid\n");
+		return -EINVAL;
+	}
+
+	ssi_pdev = of_find_device_by_node(ssi_np);
+	if (!ssi_pdev) {
+		dev_err(&pdev->dev, "failed to find SSI platform device\n");
+		return -EINVAL;
+	}
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	ret = of_property_read_u32(codec_np, "clock-frequency",
+				   &data->clk_frequency);
+	if (ret) {
+		dev_err(&pdev->dev, "clock-frequency missing or invalid\n");
+		return -EINVAL;
+	}
+
+	ret = fsl_asoc_get_codec_dev_name(codec_np, data->codec_name,
+					  DAI_NAME_SIZE);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to get codec name\n");
+		return -EINVAL;
+	}
+
+	data->dai[0].name = "HiFi Tx";
+	data->dai[0].stream_name = "HiFi Playback";
+	data->dai[0].codec_dai_name = "sgtl5000";
+	data->dai[0].codec_name = data->codec_name;
+	data->dai[0].cpu_dai_name = dev_name(&ssi_pdev->dev);
+	data->dai[0].platform_name = "imx-pcm-audio";
+	data->dai[0].ops = &imx_sgtl5000_ops;
+
+	ret = of_property_read_string(np, "fsl,model", &data->card.name);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to get audio card name\n");
+		return -EINVAL;
+	}
+	data->card.num_links = 1;
+	data->card.dai_link = data->dai;
+
+	/* Add imx-pcm-audio device */
+	data->pcm_audio_pdev = platform_device_alloc("imx-pcm-audio", -1);
+	if (!data->pcm_audio_pdev)
+		return -ENOMEM;
+	ret = platform_device_add(data->pcm_audio_pdev);
+	if (ret) {
+		platform_device_put(data->pcm_audio_pdev);
+		return ret;
+	}
+
+	/* Add soc-audio device */
+	data->soc_audio_pdev = platform_device_alloc("soc-audio", -1);
+	if (!data->soc_audio_pdev) {
+		ret = -ENOMEM;
+		goto err;
+	}
+	platform_set_drvdata(data->soc_audio_pdev, &data->card);
+	ret = platform_device_add(data->soc_audio_pdev);
+	if (ret) {
+		platform_device_put(data->soc_audio_pdev);
+		goto err;
+	}
+
+	dev_set_drvdata(&pdev->dev, data);
+	of_node_put(codec_np);
+
+	return 0;
+err:
+	platform_device_unregister(data->pcm_audio_pdev);
+	return ret;
+}
+
+static int __devexit imx_sgtl5000_remove(struct platform_device *pdev)
+{
+	struct imx_sgtl5000_data *data = dev_get_drvdata(&pdev->dev);
+
+	platform_device_unregister(data->pcm_audio_pdev);
+	platform_device_unregister(data->soc_audio_pdev);
+
+	return 0;
+}
+
+static const struct of_device_id imx_sgtl5000_dt_ids[] = {
+	{ .compatible = "fsl,imx-audio-sgtl5000", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_sgtl5000_dt_ids);
+
+static struct platform_driver imx_sgtl5000_driver = {
+	.driver = {
+		.name = "imx-sgtl5000",
+		.owner = THIS_MODULE,
+		.of_match_table = imx_sgtl5000_dt_ids,
+	},
+	.probe = imx_sgtl5000_probe,
+	.remove = __devexit_p(imx_sgtl5000_remove),
+};
+module_platform_driver(imx_sgtl5000_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Freescale i.MX SGTL5000 ASoC machine driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx-sgtl5000");
-- 
1.7.5.4



From sshtylyov at ru.mvista.com  Sat Mar  3 10:09:13 2012
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Sat, 03 Mar 2012 19:09:13 +0400
Subject: [PATCH 11/12] mfd: twl4030-irq: Return twl6030_mmc_card_detect
 IRQ for board setup
In-Reply-To: <1330707024-23730-12-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-12-git-send-email-b-cousson@ti.com>
Message-ID: <4F523419.3080100@ru.mvista.com>

Hello.

On 02-03-2012 20:50, Benoit Cousson wrote:

> Card detect IRQ from the TWL6030 used to be provided to the MMC

> controller code using a statically allocated IRQ scheme:
>
>    card_detect_irq = TWL6030_IRQ_BASE + MMCDETECT_INTR_OFFSET;
>
> This is no longer valid in a SPARSE_IRQ context since there is no more
> pre-defined TWL6030_IRQ_BASE.
>
> Return the proper card detect IRQ value in the twl6030_mmc_card_detect_config
> that will be called from the MMC controller.
>
> Signed-off-by: Benoit Cousson<b-cousson at ti.com>
> Cc: Felipe Balbi<balbi at ti.com>
> Cc: Tony Lindgren<tony at atomide.com>
> Cc: Rajendra Nayak<rnayak at ti.com>
> ---
>   drivers/mfd/twl6030-irq.c |    3 ++-

     Subject talks about twl4030-irq.

WBR, Sergei


From zsadecki at itwatchdogs.com  Sat Mar  3 11:00:25 2012
From: zsadecki at itwatchdogs.com (Zach Sadecki)
Date: Sat, 3 Mar 2012 10:00:25 -0600
Subject: mxs auart driver problems
Message-ID: <4F524019.5070306@itwatchdogs.com>

I am having some problems with the mxs-auart driver in the mainline 
kernel on my mx28 board.  If I use minicom to access the port 
(/dev/ttyAPP1) it seems to behave.  If I just send it some characters 
using 'echo -n " " > /dev/ttyAPP1'  it appears to work the first time, 
then if I repeat the same command it hangs until I kill it with ^C.

After some experimentation it seems that it only works if I'm actively 
reading characters out of it 'cat /dev/ttyAPP1' (in background or a 2nd 
terminal) and if I have turned off 'echo' using 'stty -F /dev/ttyAPP1 
-echo'.  Without the '-echo' option the serial port spews random 
characters after sending it something.

Also, when it's in the hanging state, other ttys don't behave either 
(the AMBA serial console can't respawn the login process and I can't ssh 
into the system either).  Once I ^C the hanging 'echo' command 
immediately the console login respawns and ssh login works again.

Anybody else have this problem?  The Freescale kernel (driver with DMA) 
doesn't seem to have this issue (but it still suffers from the '-echo' 
problem described above).  Any ideas on what may be going on here?

Thanks,
   Zach



From broonie at opensource.wolfsonmicro.com  Sat Mar  3 11:33:54 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 3 Mar 2012 16:33:54 +0000
Subject: [PATCH 2/4] regulator: provide a helper for registering a fixed
 regulator
In-Reply-To: <1330774804-7310-3-git-send-email-s.hauer@pengutronix.de>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
 <1330774804-7310-3-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120303163354.GA3071@opensource.wolfsonmicro.com>

On Sat, Mar 03, 2012 at 12:40:02PM +0100, Sascha Hauer wrote:
> Some devices require a regulator to work, but boards may not have
> a software controllable regulator for this device. Provide a helper
> function to make it simpler for these boards to register a fixed
> regulator as a dummy regulator.

Applied, thanks.
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From broonie at opensource.wolfsonmicro.com  Sat Mar  3 11:34:08 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 3 Mar 2012 16:34:08 +0000
Subject: [PATCH 3/4] ARM i.MX pcm037: register a dummy regulator for the
 smsc911x device
In-Reply-To: <1330774804-7310-4-git-send-email-s.hauer@pengutronix.de>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
 <1330774804-7310-4-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120303163408.GB3071@opensource.wolfsonmicro.com>

On Sat, Mar 03, 2012 at 12:40:03PM +0100, Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>

Applied, thanks.
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From broonie at opensource.wolfsonmicro.com  Sat Mar  3 11:37:34 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 3 Mar 2012 16:37:34 +0000
Subject: [PATCH 4/4] ARM i.MX 3ds debugboard: register a dummy regulator
 for the smsc911x device
In-Reply-To: <1330774804-7310-5-git-send-email-s.hauer@pengutronix.de>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
 <1330774804-7310-5-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120303163733.GC3071@opensource.wolfsonmicro.com>

On Sat, Mar 03, 2012 at 12:40:04PM +0100, Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  arch/arm/plat-mxc/3ds_debugboard.c |    9 +++++++++
>  1 files changed, 9 insertions(+), 0 deletions(-)

applied, though with at least this board you clearly do have a sensible
regulator setup already and are just adding in a few extra regulators to
fill out things which for some reason aren't supplied by the PMIC.  It's
quite surprising that things like what look like the I/O reference
voltage are supplied elsewhere.
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From mturquette at ti.com  Sat Mar  3 12:14:43 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Sat, 3 Mar 2012 09:14:43 -0800
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120303133158.GA26882@pengutronix.de>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
Message-ID: <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>

On Sat, Mar 3, 2012 at 5:31 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Sat, Mar 03, 2012 at 12:29:00AM -0800, Mike Turquette wrote:
>> The common clock framework defines a common struct clk useful across
>> most platforms as well as an implementation of the clk api that drivers
>> can use safely for managing clocks.
>>
>> The net result is consolidation of many different struct clk definitions
>> and platform-specific clock framework implementations.
>>
>> This patch introduces the common struct clk, struct clk_ops and an
>> implementation of the well-known clock api in include/clk/clk.h.
>> Platforms may define their own hardware-specific clock structure and
>> their own clock operation callbacks, so long as it wraps an instance of
>> struct clk_hw.
>>
>> See Documentation/clk.txt for more details.
>>
>> This patch is based on the work of Jeremy Kerr, which in turn was based
>> on the work of Ben Herrenschmidt.
>>
>> +
>> +/**
>> + * struct clk_hw - handle for traversing from a struct clk to its corresponding
>> + * hardware-specific structure. ?struct clk_hw should be declared within struct
>> + * clk_foo and then referenced by the struct clk instance that uses struct
>> + * clk_foo's clk_ops
>> + *
>> + * clk: pointer to the struct clk instance that points back to this struct
>> + * clk_hw instance
>> + */
>> +struct clk_hw {
>> + ? ? struct clk *clk;
>> +};
>
> The reason for doing this is that struct clk should be an opaque cookie
> for both drivers and implementers of clocks. I recently had the idea whether
> the roles of these two structs could be swapped. So instead of the above we
> could do:
>
> struct clk {
> ? ? ? ?struct clk_hw *hw;
> }

Firstly, struct clk is an opaque cookie for both drivers and
implementers of clocks with this patchset.

Secondly, struct clk does indeed have a pointer to struct clk_hw.
Refer to include/linux/clk-private.h in this patch.

The reference is cyclical.  A reference to struct clk can navigate to
struct clk_foo via container_of (usually something like "#define
to_clk_foo(_hw) container_of(_hw, struct clk_foo, hw)" where struct
clk's pointer to it's .hw member is passed into one of the struct
clk_ops callbacks.

Likewise if struct clk_foo needs the struct clk ptr for any reason
then it can get it from foo->hw->clk.

I believe this patch already does what you suggest, but I might be
missing your point.

>
> The effect would be the same, but this version would make the struct clk
> pointer known at compile time thus making it possible for static
> initializers to specify their parent clock.

This series achieves this goal also.  include/linux/clk-private.h
defines struct clk as well as macros for statically initializing the
basic clock types.  Pointers to the struct clk of a parent clock can
and are pre-populated in these macros, along with the mandatory array
of parent string names.  (note that parent pointer initialization is
optional and you can always pass in NULL into that specific field of
the macro)

>
> I just saw that clk_register now takes a parent name array, that may
> make this change unnecessary anyway.

clk_register exists for dynamic allocation and solves a different
problem from what you describe above.  For statically initialized
clocks the following is sufficient:

#include <linux/clk-private.h>

static char *abe_dpll_refclk_mux_ck_parent_names[] = {
        "sys_clkin_ck",
        "sys_32k_ck",
};

static struct clk *abe_dpll_refclk_mux_ck_parents[] = {
        &sys_clkin_ck,
        &sys_32k_ck,
};

DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck,
        abe_dpll_refclk_mux_ck_parent_names,
        abe_dpll_refclk_mux_ck_parents,
        0x0,
        OMAP4430_CM_ABE_PLL_REF_CLKSEL,
        OMAP4430_CLKSEL_0_0_SHIFT,
        OMAP4430_CLKSEL_0_0_WIDTH,
        0x0,
        NULL);

__clk_init(NULL, &abe_dpll_refclk_mux_ck);

You might find it helpful to see how I've handled statically
initialized clocks for OMAP4.  These patches are a work in progress
but I'll send an RFC to the list very soon since others might find it
useful.  For now the above example can be seen in more detail at:
http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=arch/arm/mach-omap2/clock44xx_data.c;h=7f833a7b2dca84a52c2bd1e7c8d9cfe560771258;hb=v3.3-rc5-clkv5-omap#l205

Let me know if I've missed your point somehow.

Thanks for the review,
Mike

>
> Sascha
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |


From paul.liu at linaro.org  Sat Mar  3 12:39:12 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Sun,  4 Mar 2012 01:39:12 +0800
Subject: [PATCH v7 1/2] mfd: Add anatop mfd driver
In-Reply-To: <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
References: <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
Message-ID: <1330796352-6884-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
Anatop provides regulators and thermal.
This driver handles the address space and the operation of the mfd device.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Venu Byravarasu <vbyravarasu at nvidia.com>
Cc: Peter Korsgaard <jacmet at sunsite.dk>
---
 drivers/mfd/Kconfig        |    6 ++
 drivers/mfd/Makefile       |    1 +
 drivers/mfd/anatop-mfd.c   |  142 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/anatop.h |   40 ++++++++++++
 4 files changed, 189 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mfd/anatop-mfd.c
 create mode 100644 include/linux/mfd/anatop.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index f147395..78593e8 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -830,6 +830,12 @@ config MFD_INTEL_MSIC
 	  Passage) chip. This chip embeds audio, battery, GPIO, etc.
 	  devices used in Intel Medfield platforms.
 
+config MFD_ANATOP
+	bool "Support for Anatop"
+	depends on SOC_IMX6Q
+	help
+	  Select this option to enable Anatop MFD driver.
+
 endmenu
 endif
 
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b953bab..8e11060 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -112,3 +112,4 @@ obj-$(CONFIG_TPS65911_COMPARATOR)	+= tps65911-comparator.o
 obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
 obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
 obj-$(CONFIG_MFD_S5M_CORE)	+= s5m-core.o s5m-irq.o
+obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
new file mode 100644
index 0000000..0307051
--- /dev/null
+++ b/drivers/mfd/anatop-mfd.c
@@ -0,0 +1,142 @@
+/*
+ * Anatop MFD driver
+ *
+ * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ * Copyright (C) 2012 Linaro
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+
+u32 anatop_get_bits(struct anatop *adata, u32 addr, int bit_shift, int bits)
+{
+	u32 val;
+	int mask;
+
+	if (bits == 32)
+		mask = ~0;
+	else
+		mask = (1 << bits) - 1;
+
+	val = readl(adata->ioreg + addr);
+	val = (val >> bit_shift) & mask;
+
+	return val;
+}
+EXPORT_SYMBOL(anatop_get_bits);
+
+void anatop_set_bits(struct anatop *adata, u32 addr, int bit_shift,
+		     int bits, u32 data)
+{
+	u32 val;
+	int mask;
+	if (bits == 32)
+		mask = ~0;
+	else
+		mask = (1 << bits) - 1;
+
+	spin_lock(&adata->reglock);
+	val = readl(adata->ioreg + addr) & ~(mask << bit_shift);
+	writel((data << bit_shift) | val, adata->ioreg);
+	spin_unlock(&adata->reglock);
+}
+EXPORT_SYMBOL(anatop_set_bits);
+
+static const struct of_device_id of_anatop_subdevice_match[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ .compatible = "fsl,anatop-thermal", },
+	{ },
+};
+
+static int of_anatop_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	void *ioreg;
+	struct anatop *drvdata;
+
+	ioreg = of_iomap(np, 0);
+	if (!ioreg)
+		return -EINVAL;
+	drvdata = devm_kzalloc(dev, sizeof(struct anatop), GFP_KERNEL);
+	if (!drvdata)
+		return -EINVAL;
+	drvdata->ioreg = ioreg;
+	spin_lock_init(&drvdata->reglock);
+	platform_set_drvdata(pdev, drvdata);
+	of_platform_bus_probe(np, of_anatop_subdevice_match, dev);
+
+	return 0;
+}
+
+static int of_anatop_remove(struct platform_device *pdev)
+{
+	struct anatop *drvdata;
+	drvdata = platform_get_drvdata(pdev);
+	iounmap(drvdata->ioreg);
+	return 0;
+}
+
+static const struct of_device_id of_anatop_match[] = {
+	{ .compatible = "fsl,imx6q-anatop", },
+	{ },
+};
+
+static struct platform_driver anatop_of_driver = {
+	.driver = {
+		.name = "anatop-mfd",
+		.owner = THIS_MODULE,
+		.of_match_table = of_anatop_match,
+	},
+	.probe		= of_anatop_probe,
+	.remove		= of_anatop_remove,
+};
+
+static int __init anatop_init(void)
+{
+	return platform_driver_register(&anatop_of_driver);
+}
+postcore_initcall(anatop_init);
+
+static void __exit anatop_exit(void)
+{
+	platform_driver_unregister(&anatop_of_driver);
+}
+module_exit(anatop_exit);
+
+MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP MFD driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
new file mode 100644
index 0000000..22c1007
--- /dev/null
+++ b/include/linux/mfd/anatop.h
@@ -0,0 +1,40 @@
+/*
+ * anatop.h - Anatop MFD driver
+ *
+ *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ *  Copyright (C) 2012 Linaro
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_MFD_ANATOP_H
+#define __LINUX_MFD_ANATOP_H
+
+#include <linux/spinlock.h>
+
+/**
+ * anatop - MFD data
+ * @ioreg: ioremap register
+ * @reglock: spinlock for register read/write
+ */
+struct anatop {
+	void *ioreg;
+	spinlock_t reglock;
+};
+
+extern u32 anatop_get_bits(struct anatop *, u32, int, int);
+extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
+
+#endif /*  __LINUX_MFD_ANATOP_H */
-- 
1.7.9.1



From broonie at opensource.wolfsonmicro.com  Sat Mar  3 12:58:38 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 3 Mar 2012 17:58:38 +0000
Subject: [PATCH v7 1/2] mfd: Add anatop mfd driver
In-Reply-To: <1330796352-6884-1-git-send-email-paul.liu@linaro.org>
References: <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
 <1330796352-6884-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120303175838.GA14833@opensource.wolfsonmicro.com>

On Sun, Mar 04, 2012 at 01:39:12AM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
> Anatop provides regulators and thermal.
> This driver handles the address space and the operation of the mfd device.

Please stop sending new patches as followups to old versions, it tends
not to do the right thing in mail software.
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From s.hauer at pengutronix.de  Sat Mar  3 13:14:37 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat, 3 Mar 2012 19:14:37 +0100
Subject: [PATCH 4/4] ARM i.MX 3ds debugboard: register a dummy regulator
 for the smsc911x device
In-Reply-To: <20120303163733.GC3071@opensource.wolfsonmicro.com>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
 <1330774804-7310-5-git-send-email-s.hauer@pengutronix.de>
 <20120303163733.GC3071@opensource.wolfsonmicro.com>
Message-ID: <20120303181437.GJ26642@pengutronix.de>

On Sat, Mar 03, 2012 at 04:37:34PM +0000, Mark Brown wrote:
> On Sat, Mar 03, 2012 at 12:40:04PM +0100, Sascha Hauer wrote:
> > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> > ---
> >  arch/arm/plat-mxc/3ds_debugboard.c |    9 +++++++++
> >  1 files changed, 9 insertions(+), 0 deletions(-)
> 
> applied, though with at least this board you clearly do have a sensible
> regulator setup already and are just adding in a few extra regulators to
> fill out things which for some reason aren't supplied by the PMIC.  It's
> quite surprising that things like what look like the I/O reference
> voltage are supplied elsewhere.

This debug board is used with four different baseboards and one of them
indeed has regulator support in mainline. The regulator for the smsc911x
though is not software controllable on any of these boards. In the end
it's a debug board, energy efficiency might not be really important in
such a case.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From thierry.reding at avionic-design.de  Sat Mar  3 14:32:49 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Sat, 3 Mar 2012 20:32:49 +0100
Subject: [PATCH v3 02/10] pwm: Allow chips to support multiple PWMs.
In-Reply-To: <20120223160420.GA9899@avionic-0098.mockup.avionic-design.de>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <201202221634.45159.arnd@arndb.de>
 <20120223081235.GC8621@avionic-0098.mockup.avionic-design.de>
 <201202231407.12981.arnd@arndb.de>
 <20120223160420.GA9899@avionic-0098.mockup.avionic-design.de>
Message-ID: <20120303193249.GA22021@avionic-0098.mockup.avionic-design.de>

* Thierry Reding wrote:
> * Arnd Bergmann wrote:
> > On Thursday 23 February 2012, Thierry Reding wrote:
> > > > Is this only used for the device tree functions? If so, I would recommend
> > > > making it less generic and always search for a device node.
> > > 
> > > It is currently only used to look up a struct pwm_chip for a given struct
> > > device_node, yes. But I can see other uses for this. For instance this could
> > > be useful if we ever want to provide an alternative way of requesting a PWM
> > > on a per-chip basis.
> > 
> > Nah, just keep it simple for now. If we need it later, we can still
> > add something like this back, but for now it's just a source of
> > confusion and possible bugs.
> 
> Will do.

I turns out that this is not as easy to do as I thought. The problem is that
if I remove the pwmchip_find() from the core and move the lookup
functionality into the OF support code I no longer have access to the list of
PWM chips. So I guess it will have to stay in to keep things encapsulated
properly.

Thierry
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From paul at pwsan.com  Sat Mar  3 15:15:33 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Sat, 3 Mar 2012 13:15:33 -0700 (MST)
Subject: [PATCH] ARM: OMAP2+: omap_device: call all suspend, resume callbacks
 when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set
Message-ID: <alpine.DEB.2.00.1203031314050.10611@utopia.booyaka.com>


During system suspend, when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set on
an omap_device, call the corresponding driver's ->suspend() and
->suspend_noirq() callbacks (if present).  Similarly, during resume,
the driver's ->resume() and ->resume_noirq() callbacks must both be
called, if present.  (The previous code only called ->suspend_noirq()
and ->resume_noirq().)

If all of these callbacks aren't called, some important driver
suspend/resume code may not get executed.

In current mainline, the bug fixed by this patch is only a problem
under the following conditions:

- the kernel is running on an OMAP4

- an OMAP UART is used as a console

- the kernel command line parameter 'no_console_suspend' is specified

- and the system enters suspend ("echo mem > /sys/power/state").

Under this combined circumstance, the system cannot be awakened via
the serial port after commit be4b0281956c5cae4f63f31f11d07625a6988766c
("tty: serial: OMAP: block idle while the UART is transferring data in
PIO mode").  This is because the OMAP UART driver's ->suspend()
callback is never called.  The ->suspend() callback would have called
uart_suspend_port() which in turn would call enable_irq_wake().  Since
enable_irq_wake() isn't called for the UART's IRQ, check_wakeup_irqs()
would mask off the UART IRQ in the GIC.

On v3.3 kernels prior to the above commit, serial resume from suspend
presumably occurred via the PRCM interrupt.  The UART was in
smart-idle mode, so it was able to send a PRCM wakeup which in turn
would be converted into a PRCM interrupt to the GIC, waking up the
kernel.  But after the above commit, when the system is suspended in
the middle of a UART transmit, the UART IP block would be in no-idle
mode.  In no-idle mode, the UART won't generate wakeups to the PRCM
when incoming characters are received; only GIC interrupts.  But since
the UART driver's ->suspend() callback is never called,
uart_suspend_port() and enable_irq_wake() is never called; so the UART
interrupt is masked by check_wakeup_irqs() and the UART can't wake up
the MPU.

The remaining mechanism that could have awakened the system would have
been I/O chain wakeups.  These wouldn't be active because the console
UART's clocks are never disabled when no_console_suspend is used,
preventing the full chip from idling.  Also, current mainline doesn't
yet support full chip idle states for OMAP4, so I/O chain wakeups are
not enabled.

This patch is the result of a collaboration.  John Stultz
<johnstul at us.ibm.com> and Andy Green <andy.green at linaro.org> reported
the serial wakeup problem that led to the discovery of this problem.
Kevin Hilman <khilman at ti.com> narrowed the problem down to the use of
no_console_suspend.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: John Stultz <johnstul at us.ibm.com>
Cc: Andy Green <andy.green at linaro.org>
Cc: Kevin Hilman <khilman at ti.com>
---
Targeted for 3.4.

 arch/arm/plat-omap/omap_device.c |   12 ++++--------
 1 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index e8d9869..4988a78 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -762,14 +762,12 @@ static int _od_suspend_noirq(struct device *dev)
 	struct omap_device *od = to_omap_device(pdev);
 	int ret;
 
-	if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
-		return pm_generic_suspend_noirq(dev);
-
 	ret = pm_generic_suspend_noirq(dev);
 
 	if (!ret && !pm_runtime_status_suspended(dev)) {
 		if (pm_generic_runtime_suspend(dev) == 0) {
-			omap_device_idle(pdev);
+			if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
+				omap_device_idle(pdev);
 			od->flags |= OMAP_DEVICE_SUSPENDED;
 		}
 	}
@@ -782,13 +780,11 @@ static int _od_resume_noirq(struct device *dev)
 	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_device *od = to_omap_device(pdev);
 
-	if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
-		return pm_generic_resume_noirq(dev);
-
 	if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
 	    !pm_runtime_status_suspended(dev)) {
 		od->flags &= ~OMAP_DEVICE_SUSPENDED;
-		omap_device_enable(pdev);
+		if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
+			omap_device_enable(pdev);
 		pm_generic_runtime_resume(dev);
 	}
 
-- 
1.7.9.1



From heiko at sntech.de  Sat Mar  3 16:14:36 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sat, 3 Mar 2012 22:14:36 +0100
Subject: [PATCH 0/4] Use clock functions also for clk_h and clk_p on
 S3C2443/2416
Message-ID: <201203032214.36820.heiko@sntech.de>

This series modifies the clock init in common-s3c2443 to use the
struct clk operations also for clk_p and clk_h whose values were until
now set statically in s3c24xx_setup_clocks - a function more suited to
the earlier S3C-SoCs.

In the end it makes the code (hopefully) easier to read, as strange
divisions through register values get replaced by simply clk_get_rate
calls.

To apply on top of the current s3c24xx consolidation.

Heiko Stuebner (4):
  ARM: S3C24XX: remove XXX_setup_clocks method from S3C2443
  ARM: S3C24XX: add get_rate for clk_h on S3C2416/2443
  ARM: S3C24XX: add get_rate for clk_p on S3C2416/2443
  ARM: S3C24XX: remove call to s3c24xx_setup_clocks

 arch/arm/mach-s3c24xx/clock-s3c2443.c      |    7 ---
 arch/arm/mach-s3c24xx/common-s3c2443.c     |   70 +++++++++++++++++++---------
 arch/arm/plat-samsung/include/plat/clock.h |    1 -
 3 files changed, 48 insertions(+), 30 deletions(-)

-- 
1.7.2.3



From heiko at sntech.de  Sat Mar  3 16:15:27 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sat, 3 Mar 2012 22:15:27 +0100
Subject: [PATCH 1/4] ARM: S3C24XX: remove XXX_setup_clocks method from S3C2443
In-Reply-To: <201203032214.36820.heiko@sntech.de>
References: <201203032214.36820.heiko@sntech.de>
Message-ID: <201203032215.27901.heiko@sntech.de>

s3c2443_common_setup_clocks is always called through
s3c2443_common_init_clocks, so there is no need to call it separately.
It was also called twice through this separate call.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/clock-s3c2443.c      |    7 -------
 arch/arm/plat-samsung/include/plat/clock.h |    1 -
 2 files changed, 0 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index 6dde269..efb3ac3 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -179,11 +179,6 @@ static struct clk *clks[] __initdata = {
 	&clk_hsmmc,
 };
 
-void __init_or_cpufreq s3c2443_setup_clocks(void)
-{
-	s3c2443_common_setup_clocks(s3c2443_get_mpll);
-}
-
 void __init s3c2443_init_clocks(int xtal)
 {
 	unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
@@ -196,8 +191,6 @@ void __init s3c2443_init_clocks(int xtal)
 				   armdiv, ARRAY_SIZE(armdiv),
 				   S3C2443_CLKDIV0_ARMDIV_MASK);
 
-	s3c2443_setup_clocks();
-
 	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 
 	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 3b5a9dc..a62753d 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -118,7 +118,6 @@ extern void s3c24xx_setup_clocks(unsigned long fclk,
 extern void s3c2410_setup_clocks(void);
 extern void s3c2412_setup_clocks(void);
 extern void s3c244x_setup_clocks(void);
-extern void s3c2443_setup_clocks(void);
 
 /* S3C2410 specific clock functions */
 
-- 
1.7.2.3



From heiko at sntech.de  Sat Mar  3 16:16:05 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sat, 3 Mar 2012 22:16:05 +0100
Subject: [PATCH 2/4] ARM: S3C24XX: add get_rate for clk_h on S3C2416/2443
In-Reply-To: <201203032214.36820.heiko@sntech.de>
References: <201203032214.36820.heiko@sntech.de>
Message-ID: <201203032216.06249.heiko@sntech.de>

Currently the rate of clk_h is calculated once and set through the
s3c24xx_setup_clocks call. As the clk_h is a child of the prediv
we can evaluate its divider and calculate the rate in get_rate.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/common-s3c2443.c |   31 ++++++++++++++++++++++---------
 1 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index 30a3019..39f9613 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -168,6 +168,25 @@ static struct clk clk_prediv = {
 	},
 };
 
+/* hclk divider
+ *
+ * divides the prediv and provides the hclk.
+ */
+
+static unsigned long s3c2443_hclkdiv_getrate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+	clkdiv0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
+
+	return rate / (clkdiv0 + 1);
+}
+
+static struct clk_ops clk_h_ops = {
+	.get_rate	= s3c2443_hclkdiv_getrate,
+};
+
 /* armdiv
  *
  * this clock is sourced from msysclk and can have a number of
@@ -524,13 +543,6 @@ static struct clk hsmmc1_clk = {
 	.ctrlbit	= S3C2443_HCLKCON_HSMMC,
 };
 
-static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
-{
-	clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
-
-	return clkcon0 + 1;
-}
-
 /* EPLLCON compatible enough to get on/off information */
 
 void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
@@ -554,8 +566,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
 	clk_msysclk.clk.rate = pll;
 
 	fclk = clk_get_rate(&clk_armdiv);
-	hclk = s3c2443_prediv_getrate(&clk_prediv);
-	hclk /= s3c2443_get_hdiv(clkdiv0);
+	hclk = clk_get_rate(&clk_h);
 	pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
 
 	s3c24xx_setup_clocks(fclk, hclk, pclk);
@@ -621,6 +632,8 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
 
 	/* s3c2443 parents h and p clocks from prediv */
 	clk_h.parent = &clk_prediv;
+	clk_h.ops = &clk_h_ops;
+
 	clk_p.parent = &clk_prediv;
 
 	clk_usb_bus.parent = &clk_usb_bus_host.clk;
-- 
1.7.2.3



From heiko at sntech.de  Sat Mar  3 16:16:47 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sat, 3 Mar 2012 22:16:47 +0100
Subject: [PATCH 3/4] ARM: S3C24XX: add get_rate for clk_p on S3C2416/2443
In-Reply-To: <201203032214.36820.heiko@sntech.de>
References: <201203032214.36820.heiko@sntech.de>
Message-ID: <201203032216.48126.heiko@sntech.de>

Currently the rate of clk_p is calculated once and set through the
s3c24xx_setup_clocks call. As the clk_p is a child of clk_h we can
evaluate its divider and calculate the rate in get_rate.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/common-s3c2443.c |   28 ++++++++++++++++++++++++----
 1 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index 39f9613..6f3bcad 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -187,6 +187,25 @@ static struct clk_ops clk_h_ops = {
 	.get_rate	= s3c2443_hclkdiv_getrate,
 };
 
+/* pclk divider
+ *
+ * divides the hclk and provides the pclk.
+ */
+
+static unsigned long s3c2443_pclkdiv_getrate(struct clk *clk)
+{
+	unsigned long rate = clk_get_rate(clk->parent);
+	unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+	clkdiv0 = ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 1 : 0);
+
+	return rate / (clkdiv0 + 1);
+}
+
+static struct clk_ops clk_p_ops = {
+	.get_rate	= s3c2443_pclkdiv_getrate,
+};
+
 /* armdiv
  *
  * this clock is sourced from msysclk and can have a number of
@@ -549,7 +568,6 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
 {
 	unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
 	unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
-	unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
 	struct clk *xtal_clk;
 	unsigned long xtal;
 	unsigned long pll;
@@ -567,7 +585,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
 
 	fclk = clk_get_rate(&clk_armdiv);
 	hclk = clk_get_rate(&clk_h);
-	pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
+	pclk = clk_get_rate(&clk_p);
 
 	s3c24xx_setup_clocks(fclk, hclk, pclk);
 
@@ -630,11 +648,13 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
 	nr_armdiv = nr_divs;
 	armdivmask = divmask;
 
-	/* s3c2443 parents h and p clocks from prediv */
+	/* s3c2443 parents h clock from prediv */
 	clk_h.parent = &clk_prediv;
 	clk_h.ops = &clk_h_ops;
 
-	clk_p.parent = &clk_prediv;
+	/* and p clock from h clock */
+	clk_p.parent = &clk_h;
+	clk_p.ops = &clk_p_ops;
 
 	clk_usb_bus.parent = &clk_usb_bus_host.clk;
 	clk_epll.parent = &clk_epllref.clk;
-- 
1.7.2.3



From heiko at sntech.de  Sat Mar  3 16:18:24 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sat, 3 Mar 2012 22:18:24 +0100
Subject: [PATCH 4/4] ARM: S3C24XX: remove call to s3c24xx_setup_clocks
In-Reply-To: <201203032214.36820.heiko@sntech.de>
References: <201203032214.36820.heiko@sntech.de>
Message-ID: <201203032218.24421.heiko@sntech.de>

As the clocks can calculate their rate themself now, there is no
need to set it statically.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/common-s3c2443.c |   15 ++++-----------
 1 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index 6f3bcad..4604315 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -571,9 +571,6 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
 	struct clk *xtal_clk;
 	unsigned long xtal;
 	unsigned long pll;
-	unsigned long fclk;
-	unsigned long hclk;
-	unsigned long pclk;
 	int ptr;
 
 	xtal_clk = clk_get(NULL, "xtal");
@@ -582,17 +579,13 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
 
 	pll = get_mpll(mpllcon, xtal);
 	clk_msysclk.clk.rate = pll;
-
-	fclk = clk_get_rate(&clk_armdiv);
-	hclk = clk_get_rate(&clk_h);
-	pclk = clk_get_rate(&clk_p);
-
-	s3c24xx_setup_clocks(fclk, hclk, pclk);
+	clk_mpll.rate = pll;
 
 	printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
 	       (mpllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
-	       print_mhz(pll), print_mhz(fclk),
-	       print_mhz(hclk), print_mhz(pclk));
+	       print_mhz(pll), print_mhz(clk_get_rate(&clk_armdiv)),
+	       print_mhz(clk_get_rate(&clk_h)),
+	       print_mhz(clk_get_rate(&clk_p)));
 
 	for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
 		s3c_set_clksrc(&clksrc_clks[ptr], true);
-- 
1.7.2.3



From heiko at sntech.de  Sat Mar  3 16:19:45 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sat, 3 Mar 2012 22:19:45 +0100
Subject: [PATCH] ARM: S3C24XX: add support for second irq set of S3C2416
Message-ID: <201203032219.45813.heiko@sntech.de>

The S3C2416 has a separate second interrupt register-set to support
additional irqs. This patch adds the necessary constants and registers
the irq handlers for it.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
Patch should go on top of the current s3c24xx consolidation

 arch/arm/mach-s3c24xx/include/mach/irqs.h    |   15 ++++-
 arch/arm/mach-s3c24xx/irq-s3c2416.c          |   98 ++++++++++++++++++++++++++
 arch/arm/mach-s3c24xx/s3c2416.c              |    1 +
 arch/arm/plat-samsung/include/plat/s3c2416.h |    3 +
 4 files changed, 116 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index e53b217..e120576 100644
--- a/arch/arm/mach-s3c24xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -134,6 +134,17 @@
 #define IRQ_S32416_WDT		S3C2410_IRQSUB(27)
 #define IRQ_S32416_AC97		S3C2410_IRQSUB(28)
 
+/* second interrupt-register of s3c2416/s3c2450 */
+
+#define S3C2416_IRQ(x)		S3C2410_IRQ((x)+54+29)
+#define IRQ_S3C2416_2D		S3C2416_IRQ(0)
+#define IRQ_S3C2416_IIC1	S3C2416_IRQ(1)
+#define IRQ_S3C2416_RESERVED2	S3C2416_IRQ(2)
+#define IRQ_S3C2416_RESERVED3	S3C2416_IRQ(3)
+#define IRQ_S3C2416_PCM0	S3C2416_IRQ(4)
+#define IRQ_S3C2416_PCM1	S3C2416_IRQ(5)
+#define IRQ_S3C2416_I2S0	S3C2416_IRQ(6)
+#define IRQ_S3C2416_I2S1	S3C2416_IRQ(7)
 
 /* extra irqs for s3c2440 */
 
@@ -175,7 +186,9 @@
 #define IRQ_S3C2443_WDT		S3C2410_IRQSUB(27)
 #define IRQ_S3C2443_AC97	S3C2410_IRQSUB(28)
 
-#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
+#if defined(CONFIG_CPU_S3C2416)
+#define NR_IRQS (IRQ_S3C2416_I2S1+1)
+#elif defined(CONFIG_CPU_S3C2443)
 #define NR_IRQS (IRQ_S3C2443_AC97+1)
 #else
 #define NR_IRQS (IRQ_S3C2440_AC97+1)
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
index fd49f35..d92f879 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2416.c
@@ -27,6 +27,7 @@
 #include <linux/ioport.h>
 #include <linux/device.h>
 #include <linux/io.h>
+#include <linux/syscore_ops.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -192,6 +193,43 @@ static struct irq_chip s3c2416_irq_uart3 = {
 	.irq_ack	= s3c2416_irq_uart3_ack,
 };
 
+/* second interrupt register */
+
+static inline void s3c2416_irq_ack_second(struct irq_data *data)
+{
+	unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
+
+	__raw_writel(bitval, S3C2416_SRCPND2);
+	__raw_writel(bitval, S3C2416_INTPND2);
+}
+
+static void s3c2416_irq_mask_second(struct irq_data *data)
+{
+	unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
+	unsigned long mask;
+
+	mask = __raw_readl(S3C2416_INTMSK2);
+	mask |= bitval;
+	__raw_writel(mask, S3C2416_INTMSK2);
+}
+
+static void s3c2416_irq_unmask_second(struct irq_data *data)
+{
+	unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
+	unsigned long mask;
+
+	mask = __raw_readl(S3C2416_INTMSK2);
+	mask &= ~bitval;
+	__raw_writel(mask, S3C2416_INTMSK2);
+}
+
+struct irq_chip s3c2416_irq_second = {
+	.irq_ack	= s3c2416_irq_ack_second,
+	.irq_mask	= s3c2416_irq_mask_second,
+	.irq_unmask	= s3c2416_irq_unmask_second,
+};
+
+
 /* IRQ initialisation code */
 
 static int __init s3c2416_add_sub(unsigned int base,
@@ -213,6 +251,42 @@ static int __init s3c2416_add_sub(unsigned int base,
 	return 0;
 }
 
+static void __init s3c2416_add_second(void)
+{
+	unsigned long pend;
+	unsigned long last;
+	int irqno;
+	int i;
+
+	/* first, clear all interrupts pending... */
+	last = 0;
+	for (i = 0; i < 4; i++) {
+		pend = __raw_readl(S3C2416_INTPND2);
+
+		if (pend == 0 || pend == last)
+			break;
+
+		__raw_writel(pend, S3C2416_SRCPND2);
+		__raw_writel(pend, S3C2416_INTPND2);
+		printk(KERN_INFO "irq: clearing pending status %08x\n",
+		       (int)pend);
+		last = pend;
+	}
+
+	for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) {
+		switch (irqno) {
+		case IRQ_S3C2416_RESERVED2:
+		case IRQ_S3C2416_RESERVED3:
+			/* no IRQ here */
+			break;
+		default:
+			irq_set_chip_and_handler(irqno, &s3c2416_irq_second,
+						 handle_edge_irq);
+			set_irq_flags(irqno, IRQF_VALID);
+		}
+	}
+}
+
 static int __init s3c2416_irq_add(struct device *dev,
 				  struct subsys_interface *sif)
 {
@@ -232,6 +306,8 @@ static int __init s3c2416_irq_add(struct device *dev,
 			&s3c2416_irq_wdtac97,
 			IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
 
+	s3c2416_add_second();
+
 	return 0;
 }
 
@@ -248,3 +324,25 @@ static int __init s3c2416_irq_init(void)
 
 arch_initcall(s3c2416_irq_init);
 
+#ifdef CONFIG_PM
+static struct sleep_save irq_save[] = {
+	SAVE_ITEM(S3C2416_INTMSK2),
+};
+
+int s3c2416_irq_suspend(void)
+{
+	s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+
+	return 0;
+}
+
+void s3c2416_irq_resume(void)
+{
+	s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+}
+
+struct syscore_ops s3c2416_irq_syscore_ops = {
+	.suspend	= s3c2416_irq_suspend,
+	.resume		= s3c2416_irq_resume,
+};
+#endif
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 0e9a71c..694977e 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -105,6 +105,7 @@ int __init s3c2416_init(void)
 	register_syscore_ops(&s3c2416_pm_syscore_ops);
 #endif
 	register_syscore_ops(&s3c24xx_irq_syscore_ops);
+	register_syscore_ops(&s3c2416_irq_syscore_ops);
 
 	return device_register(&s3c2416_dev);
 }
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
index de2b5bd..7178e33 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2416.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2416.h
@@ -24,6 +24,9 @@ extern void s3c2416_init_clocks(int xtal);
 extern  int s3c2416_baseclk_add(void);
 
 extern void s3c2416_restart(char mode, const char *cmd);
+
+extern struct syscore_ops s3c2416_irq_syscore_ops;
+
 #else
 #define s3c2416_init_clocks NULL
 #define s3c2416_init_uarts NULL
-- 
1.7.2.3



From robert.jarzmik at free.fr  Sat Mar  3 16:34:26 2012
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Sat, 03 Mar 2012 22:34:26 +0100
Subject: Status of gpio-pxa driver and dummy clock
Message-ID: <87eht9tllp.fsf@free.fr>

Hi Haojian,

As you certainly know, Russell reverted the patch "ARM: pxa: add dummy clock for
sa1100-rtc", id a55b5adaf403c4d032e0871ad4ee3367782f4db6. As a consequence, the
dummy clock for gpio-pxa was removed, causing breakage of gpio-pxa driver.

I wonder if you (or somebody through you) sent an update to fix the gpio-pxa by
either fixing gpio-pxa or adding back "pxa-gpio" clock. As of today, I see no
fix in 3.3-rc free (Linus tree).

Cheers.

-- 
Robert


From thierry.reding at avionic-design.de  Sat Mar  3 17:42:12 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Sat, 3 Mar 2012 23:42:12 +0100
Subject: [PATCH v3 06/10] pwm: Add NVIDIA Tegra SoC support
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E63@HQMAIL01.nvidia.com>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <1329923841-32017-7-git-send-email-thierry.reding@avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E63@HQMAIL01.nvidia.com>
Message-ID: <20120303224212.GA6661@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> Thierry Reding wrote at Wednesday, February 22, 2012 8:17 AM:
> > This commit adds a generic PWM framework driver for the PWFM controller
> > found on NVIDIA Tegra SoCs. The driver is based on code from the
> > Chromium kernel tree and was originally written by Gary King (NVIDIA)
> > and later modified by Simon Que (Chromium).
> 
> > diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> 
> > +static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> 
> > +	/*
> > +	 * Convert from duty_ns / period_ns to a fixed number of duty
> > +	 * ticks per (1 << PWM_DUTY_WIDTH) cycles.
> > +	 */
> > +	c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1);
> 
> The driver in ChromeOS has the following extra line here:
> 
>     c += (period_ns / 2);
> 
> and the following extra line in the comment above:
> 
>     Also, make sure to round to the nearest integer during division.
> 
> I don't know the HW well enough to know if that line should be present?
> 
> Otherwise, this looks similar enough to the ChromeOS driver, so:
> 
> Acked-by: Stephen Warren <swarren at nvidia.com>

Those probably weren't there yet when I prepared the first series. I'll have
another look will sync up with it after testing that it still works.

Thierry
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From thierry.reding at avionic-design.de  Sat Mar  3 17:47:51 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Sat, 3 Mar 2012 23:47:51 +0100
Subject: [PATCH v3 04/10] arm/tegra: Fix PWM clock programming
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E52@HQMAIL01.nvidia.com>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <1329923841-32017-5-git-send-email-thierry.reding@avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E52@HQMAIL01.nvidia.com>
Message-ID: <20120303224751.GB6661@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> Thierry Reding wrote at Wednesday, February 22, 2012 8:17 AM:
> > PWM clock source registers in Tegra 2 have different clock source selection bit
> > fields than other registers.  PWM clock source bits in CLK_SOURCE_PWM_0 register
> > are located at bit field bit[30:28] while others are at bit field bit[31:30] in
> > their respective clock source register.
> > 
> > This patch updates the clock programming to correctly reflect that, by adding a
> > flag to indicate the alternate bit field format and checking for it when
> > selecting a clock source (parent clock).
> 
> tegra30_clocks.c needs this change too, although on Tegra30, it's bits
> 29:28 for the PWM, and bits 31:30 for non-PWM.

Okay, I'll add code for Tegra30 in the next version. I won't be able to test
that at all because I don't have any Tegra30 hardware.

> > diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
> 
> +#define PERIPH_CLK_SOURCE_4BIT_MASK	(7<<28)
> +#define PERIPH_CLK_SOURCE_4BIT_SHIFT	28
> 
> Why is this (and the flag that enables it) called "4 bit"; the existing
> code supports a 2-bit mux field (4-values), whereas this new code supports
> a 3-bit field (potentially 8 values, but only 5 actually assigned).
> Can this be renamed something more accurate, especially since on Tegra30
> the difference is only the bit position of the field, not the number of
> bits in the field.

This is taken directly from the Chromium tree, so I don't really know why
that name was chosen. But since the PWM clock source register seems to be the
only exception, how about calling the flag PWM_CLK and prefix the shift and
mask with PWM_CLK_SOURCE_ instead?

> > @@ -908,9 +910,16 @@ static void tegra2_periph_clk_init(struct clk *c)
> >  	u32 val = clk_readl(c->reg);
> >  	const struct clk_mux_sel *mux = NULL;
> >  	const struct clk_mux_sel *sel;
> > +	u32 shift;
> > +
> > +	if (c->flags & PERIPH_SOURCE_CLK_4BIT)
> > +		shift = PERIPH_CLK_SOURCE_4BIT_SHIFT;
> > +	else
> > +		shift = PERIPH_CLK_SOURCE_SHIFT;
> 
> I think you should assign a "mask" variable here too...
> 
> > +
> >  	if (c->flags & MUX) {
> >  		for (sel = c->inputs; sel->input != NULL; sel++) {
> > -			if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
> > +			if (val >> shift == sel->value)
> >  				mux = sel;
> 
> Because in the new case, bit 31 isn't part of the field, so just
> shifting doesn't isolate the mux field. In practice, this probably isn't
> an issue since bit 31 is undefined, but better to be safe than sorry...

Okay, I'll fix that as well.

Thierry
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From thierry.reding at avionic-design.de  Sat Mar  3 17:54:05 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Sat, 3 Mar 2012 23:54:05 +0100
Subject: [PATCH v3 07/10] arm/tegra: Add PWFM controller device tree
 probing
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E67@HQMAIL01.nvidia.com>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <1329923841-32017-8-git-send-email-thierry.reding@avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E67@HQMAIL01.nvidia.com>
Message-ID: <20120303225404.GC6661@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> Thierry Reding wrote at Wednesday, February 22, 2012 8:17 AM:
> > Add auxdata to instantiate a device tree for the PWFM controller and
> > include a corresponding node in the device tree.
> 
> > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> 
> > +	pwm: pwm at 7000a000 {
> > +		compatible = "nvidia,tegra20-pwm";
> > +		reg = <0x7000a000 0x100>;
> > +		#pwm-cells = <2>;
> > +	};
> 
> The compatible value probably should list both Tegra30 and Tegra20, so
> we can know exactly which HW is present, just in case we need to turn
> on some bug-fix only for one of the variants:
> 
>     compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";

I'm confused. If I know exactly that the hardware is Tegra30 (which it
definitely should be if I include tegra30.dtsi), then why list "tegra20-pwm"
as compatible?

Or did you mean to list tegra30-pwm as compatible value in the PWM driver?

> Could you also write binding documentation, in particular explaining
> what the two pwm-cells are specifically for Tegra:
> 
> Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> 
> (although perhaps that'd be part of the previous patch which implements
> the driver)

Actually for Tegra the values would be those documented in the generic
binding because Tegra uses of_pwm_simple_xlate(). Does it still make sense to
add a Tegra-specific binding?

Thierry
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From jason at lakedaemon.net  Sat Mar  3 17:54:40 2012
From: jason at lakedaemon.net (Jason)
Date: Sat, 3 Mar 2012 17:54:40 -0500
Subject: [PATCH 4/4] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <20120302223629.GA21080@lunn.ch>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203021456.47896.arnd@arndb.de>
 <20120302153614.GG11986@titan.lakedaemon.net>
 <201203021648.52523.arnd@arndb.de>
 <20120302170252.GJ11986@titan.lakedaemon.net>
 <20120302223629.GA21080@lunn.ch>
Message-ID: <20120303225440.GR11986@titan.lakedaemon.net>

On Fri, Mar 02, 2012 at 11:36:29PM +0100, Andrew Lunn wrote:
> > > Andrew Lunn said that he has a patch for plat-orion to use the generic
> > > clock framework. I think we should look at that before introducing
> > > a hack that will have to be removed again very soon.
> > 
> > I asked him for it earlier [1], apparently it's a very invasive patch
> > series which breaks things.  I would like to look at it as a reference,
> > even if applying it isn't a good idea.
> 
> I did not say it breaks things. I said i have a habit of breaking
> orion5x, because i cannot test it.

Wow, you're right, I was way off.  I must not have read that over before
sending.  My mistake.

> I will send the patches as RFC on Sunday. I'm traveling at the moment.

Awesome, thanks.

Jason.


From jason at lakedaemon.net  Sat Mar  3 18:05:11 2012
From: jason at lakedaemon.net (Jason)
Date: Sat, 3 Mar 2012 18:05:11 -0500
Subject: [PATCH 5/5 v2] ARM: kirkwood: convert orion-wdt to fdt.
In-Reply-To: <20120303100853.GK7363@n2100.arm.linux.org.uk>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <e2fe5e97a83fc753559bbb18d5d111ed01b89034.1330709314.git.jason@lakedaemon.net>
 <201203021832.34901.arnd@arndb.de>
 <20120303100853.GK7363@n2100.arm.linux.org.uk>
Message-ID: <20120303230511.GS11986@titan.lakedaemon.net>

On Sat, Mar 03, 2012 at 10:08:53AM +0000, Russell King - ARM Linux wrote:
> On Fri, Mar 02, 2012 at 06:32:33PM +0000, Arnd Bergmann wrote:
> > On Friday 02 March 2012, Jason Cooper wrote:
> > > +       wdt_reg = (void __iomem *)TIMER_VIRT_BASE;
> > > +
> > > +       ret = of_address_to_resource(np, 0, &res);
> > > +       if (ret) {
> > > +               printk(KERN_ERR "invalid address\n");
> > > +               return ret;
> > > +       }
> > > +
> > > +       wdt_reg = ioremap(res.start, res.end - res.start);
> > > +
> > 
> > This will break non-dt uses because you overwrite the wdt_reg value.
> 
> Don't also forget that "res.end - res.start" is also not correct, and
> resource_size() should be used to prevent that kind of error.

Russell, thanks for the review.  I'll redo this one and resubmit my
pull-request to Arnd.  I assume that we don't won't this to be a
separate patch as a future bisect could land inbetween this patch and
the fix.

Sorry for the extra work Arnd.

thx,

Jason.


From haojian.zhuang at gmail.com  Sat Mar  3 20:05:47 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Sun, 4 Mar 2012 09:05:47 +0800
Subject: Status of gpio-pxa driver and dummy clock
In-Reply-To: <87eht9tllp.fsf@free.fr>
References: <87eht9tllp.fsf@free.fr>
Message-ID: <CAN1soZwtVm=qBw97AeeysfTXhCQg7XonKkHAE_dn6EYbLHnKBw@mail.gmail.com>

On Sun, Mar 4, 2012 at 5:34 AM, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
> Hi Haojian,
>
> As you certainly know, Russell reverted the patch "ARM: pxa: add dummy clock for
> sa1100-rtc", id a55b5adaf403c4d032e0871ad4ee3367782f4db6. As a consequence, the
> dummy clock for gpio-pxa was removed, causing breakage of gpio-pxa driver.
>
> I wonder if you (or somebody through you) sent an update to fix the gpio-pxa by
> either fixing gpio-pxa or adding back "pxa-gpio" clock. As of today, I see no
> fix in 3.3-rc free (Linus tree).
>

This patch is already merged into arm-soc tree for v3.4. I don't have
a plan to push it into
v3.3.

Thanks
Haojian


From shijie8 at gmail.com  Sat Mar  3 20:11:18 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Sat, 3 Mar 2012 20:11:18 -0500
Subject: [PATCH] mtd/gpmi : move the __mxs_setl()/__mxs_clrl() to
 gpmi-lib.c
In-Reply-To: <1330807232-5616-1-git-send-email-shijie8@gmail.com>
References: <1330807232-5616-1-git-send-email-shijie8@gmail.com>
Message-ID: <CAMiH66E9Hr5oeNCk1cAQJKO-qtc8a=mHxNgDGgGwXC95XWhGMQ@mail.gmail.com>

please ignore this patch.

mxs-dma and some other module also have the same problem.
A more powerful patch is needed.

BR
Huang Shijie


On Sat, Mar 3, 2012 at 3:40 PM, Huang Shijie <shijie8 at gmail.com> wrote:
> We will meet the compiler error in mx6q, since there is no mxs.h header anymore.
> So move these two helper functions to gpmi-lib.c.
>
> Signed-off-by: Huang Shijie <shijie8 at gmail.com>
> ---
> ?drivers/mtd/nand/gpmi-nand/gpmi-lib.c | ? 14 +++++++++++++-
> ?1 files changed, 13 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> index 5e3c505..9a208cb 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> @@ -21,7 +21,6 @@
> ?#include <linux/mtd/gpmi-nand.h>
> ?#include <linux/delay.h>
> ?#include <linux/clk.h>
> -#include <mach/mxs.h>
>
> ?#include "gpmi-nand.h"
> ?#include "gpmi-regs.h"
> @@ -37,6 +36,19 @@ struct timing_threshod timing_default_threshold = {
> ? ? ? ?.max_dll_delay_in_ns ? ? ? ? = 16,
> ?};
>
> +#define MXS_SET_ADDR ? ? ? ? ? 0x4
> +#define MXS_CLR_ADDR ? ? ? ? ? 0x8
> +
> +static inline void __mxs_setl(u32 mask, void __iomem *reg)
> +{
> + ? ? ? writel(mask, reg + MXS_SET_ADDR);
> +}
> +
> +static inline void __mxs_clrl(u32 mask, void __iomem *reg)
> +{
> + ? ? ? writel(mask, reg + MXS_CLR_ADDR);
> +}
> +
> ?/*
> ?* Clear the bit and poll it cleared. ?This is usually called with
> ?* a reset address and mask being either SFTRST(bit 31) or CLKGATE
> --
> 1.7.4
>


From shawn.guo at linaro.org  Sun Mar  4 00:25:21 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 4 Mar 2012 13:25:21 +0800
Subject: [PATCH v7 1/2] mfd: Add anatop mfd driver
In-Reply-To: <1330796352-6884-1-git-send-email-paul.liu@linaro.org>
References: <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
 <1330796352-6884-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120304052517.GA10743@S2101-09.ap.freescale.net>

On Sun, Mar 04, 2012 at 01:39:12AM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
> Anatop provides regulators and thermal.
> This driver handles the address space and the operation of the mfd device.
> 
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>

A few trivial comments below, otherwise

Acked-by: Shawn Guo <shawn.guo at linaro.org>

> Cc: Venu Byravarasu <vbyravarasu at nvidia.com>
> Cc: Peter Korsgaard <jacmet at sunsite.dk>
> ---
>  drivers/mfd/Kconfig        |    6 ++
>  drivers/mfd/Makefile       |    1 +
>  drivers/mfd/anatop-mfd.c   |  142 ++++++++++++++++++++++++++++++++++++++++++++
>  include/linux/mfd/anatop.h |   40 ++++++++++++
>  4 files changed, 189 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/mfd/anatop-mfd.c
>  create mode 100644 include/linux/mfd/anatop.h
> 
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index f147395..78593e8 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -830,6 +830,12 @@ config MFD_INTEL_MSIC
>  	  Passage) chip. This chip embeds audio, battery, GPIO, etc.
>  	  devices used in Intel Medfield platforms.
>  
> +config MFD_ANATOP
> +	bool "Support for Anatop"

It might worth a more descriptive prompt, something like
"Support Freescale i.MX on-chip ANATOP controller"?

> +	depends on SOC_IMX6Q
> +	help
> +	  Select this option to enable Anatop MFD driver.

Ditto, a more descriptive help?

> +
>  endmenu
>  endif
>  
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index b953bab..8e11060 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -112,3 +112,4 @@ obj-$(CONFIG_TPS65911_COMPARATOR)	+= tps65911-comparator.o
>  obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
>  obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
>  obj-$(CONFIG_MFD_S5M_CORE)	+= s5m-core.o s5m-irq.o
> +obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
> diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
> new file mode 100644
> index 0000000..0307051
> --- /dev/null
> +++ b/drivers/mfd/anatop-mfd.c
> @@ -0,0 +1,142 @@
> +/*
> + * Anatop MFD driver
> + *
> + * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> + * Copyright (C) 2012 Linaro
> + *
> + *  This program is free software; you can redistribute it and/or modify
> + *  it under the terms of the GNU General Public License as published by
> + *  the Free Software Foundation; either version 2 of the License, or
> + *   (at your option) any later version.
> + *
> + *  This program is distributed in the hope that it will be useful,
> + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *  GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License along
> + *  with this program; if not, write to the Free Software Foundation, Inc.,
> + *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + *  This program is free software; you can redistribute it and/or modify
> + *  it under the terms of the GNU General Public License as published by
> + *  the Free Software Foundation; either version 2 of the License, or
> + *  (at your option) any later version.
> + *
> + *  This program is distributed in the hope that it will be useful,
> + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *  GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License along
> + *  with this program; if not, write to the Free Software Foundation, Inc.,
> + *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + *
> + */
> +
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/mfd/anatop.h>
> +
> +u32 anatop_get_bits(struct anatop *adata, u32 addr, int bit_shift, int bits)
> +{
> +	u32 val;
> +	int mask;

Shouldn't mask be also u32?  Then "u32 val, mask;"?
> +
> +	if (bits == 32)
> +		mask = ~0;
> +	else
> +		mask = (1 << bits) - 1;
> +
> +	val = readl(adata->ioreg + addr);
> +	val = (val >> bit_shift) & mask;
> +
> +	return val;
> +}
> +EXPORT_SYMBOL(anatop_get_bits);
> +
> +void anatop_set_bits(struct anatop *adata, u32 addr, int bit_shift,
> +		     int bits, u32 data)
> +{
> +	u32 val;
> +	int mask;

Ditto, with a blank line to be consistent with above function.

> +	if (bits == 32)
> +		mask = ~0;
> +	else
> +		mask = (1 << bits) - 1;
> +
> +	spin_lock(&adata->reglock);
> +	val = readl(adata->ioreg + addr) & ~(mask << bit_shift);
> +	writel((data << bit_shift) | val, adata->ioreg);
> +	spin_unlock(&adata->reglock);
> +}
> +EXPORT_SYMBOL(anatop_set_bits);
> +
> +static const struct of_device_id of_anatop_subdevice_match[] = {
> +	{ .compatible = "fsl,anatop-regulator", },
> +	{ .compatible = "fsl,anatop-thermal", },
> +	{ },
> +};
> +
> +static int of_anatop_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	void *ioreg;
> +	struct anatop *drvdata;
> +
> +	ioreg = of_iomap(np, 0);
> +	if (!ioreg)
> +		return -EINVAL;

return -EADDRNOTAVAIL;

> +	drvdata = devm_kzalloc(dev, sizeof(struct anatop), GFP_KERNEL);
> +	if (!drvdata)
> +		return -EINVAL;

return -ENOMEM;

The bonus point is we can know the failure cause from error number,
with no need of error message.

Regards,
Shawn

> +	drvdata->ioreg = ioreg;
> +	spin_lock_init(&drvdata->reglock);
> +	platform_set_drvdata(pdev, drvdata);
> +	of_platform_bus_probe(np, of_anatop_subdevice_match, dev);
> +
> +	return 0;
> +}
> +
> +static int of_anatop_remove(struct platform_device *pdev)
> +{
> +	struct anatop *drvdata;
> +	drvdata = platform_get_drvdata(pdev);
> +	iounmap(drvdata->ioreg);
> +	return 0;
> +}
> +
> +static const struct of_device_id of_anatop_match[] = {
> +	{ .compatible = "fsl,imx6q-anatop", },
> +	{ },
> +};
> +
> +static struct platform_driver anatop_of_driver = {
> +	.driver = {
> +		.name = "anatop-mfd",
> +		.owner = THIS_MODULE,
> +		.of_match_table = of_anatop_match,
> +	},
> +	.probe		= of_anatop_probe,
> +	.remove		= of_anatop_remove,
> +};
> +
> +static int __init anatop_init(void)
> +{
> +	return platform_driver_register(&anatop_of_driver);
> +}
> +postcore_initcall(anatop_init);
> +
> +static void __exit anatop_exit(void)
> +{
> +	platform_driver_unregister(&anatop_of_driver);
> +}
> +module_exit(anatop_exit);
> +
> +MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
> +MODULE_DESCRIPTION("ANATOP MFD driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
> new file mode 100644
> index 0000000..22c1007
> --- /dev/null
> +++ b/include/linux/mfd/anatop.h
> @@ -0,0 +1,40 @@
> +/*
> + * anatop.h - Anatop MFD driver
> + *
> + *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> + *  Copyright (C) 2012 Linaro
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +
> +#ifndef __LINUX_MFD_ANATOP_H
> +#define __LINUX_MFD_ANATOP_H
> +
> +#include <linux/spinlock.h>
> +
> +/**
> + * anatop - MFD data
> + * @ioreg: ioremap register
> + * @reglock: spinlock for register read/write
> + */
> +struct anatop {
> +	void *ioreg;
> +	spinlock_t reglock;
> +};
> +
> +extern u32 anatop_get_bits(struct anatop *, u32, int, int);
> +extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
> +
> +#endif /*  __LINUX_MFD_ANATOP_H */
> -- 
> 1.7.9.1
> 


From shawn.guo at linaro.org  Sun Mar  4 00:42:39 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 4 Mar 2012 13:42:39 +0800
Subject: [PATCH v7 1/2] mfd: Add anatop mfd driver
In-Reply-To: <1330796352-6884-1-git-send-email-paul.liu@linaro.org>
References: <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
 <1330796352-6884-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120304054237.GB10743@S2101-09.ap.freescale.net>

On Sun, Mar 04, 2012 at 01:39:12AM +0800, Ying-Chun Liu (PaulLiu) wrote:
...
> +static int of_anatop_probe(struct platform_device *pdev)

__devinit

> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	void *ioreg;
> +	struct anatop *drvdata;
> +
> +	ioreg = of_iomap(np, 0);
> +	if (!ioreg)
> +		return -EINVAL;
> +	drvdata = devm_kzalloc(dev, sizeof(struct anatop), GFP_KERNEL);
> +	if (!drvdata)
> +		return -EINVAL;
> +	drvdata->ioreg = ioreg;
> +	spin_lock_init(&drvdata->reglock);
> +	platform_set_drvdata(pdev, drvdata);
> +	of_platform_bus_probe(np, of_anatop_subdevice_match, dev);
> +
> +	return 0;
> +}
> +
> +static int of_anatop_remove(struct platform_device *pdev)

__devexit

> +{
> +	struct anatop *drvdata;
> +	drvdata = platform_get_drvdata(pdev);
> +	iounmap(drvdata->ioreg);
> +	return 0;
> +}
> +

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Sun Mar  4 00:55:04 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 4 Mar 2012 13:55:04 +0800
Subject: [PATCH v7 1/2] mfd: Add anatop mfd driver
In-Reply-To: <1330796352-6884-1-git-send-email-paul.liu@linaro.org>
References: <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
 <1330796352-6884-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120304055500.GC10743@S2101-09.ap.freescale.net>

Sorry, one more missing ...

On Sun, Mar 04, 2012 at 01:39:12AM +0800, Ying-Chun Liu (PaulLiu) wrote:
...
> +static int of_anatop_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	void *ioreg;
> +	struct anatop *drvdata;
> +
> +	ioreg = of_iomap(np, 0);
> +	if (!ioreg)
> +		return -EINVAL;
> +	drvdata = devm_kzalloc(dev, sizeof(struct anatop), GFP_KERNEL);

sizeof(*drvdata) please.

Documentation/CodingStyle, Chapter 14:

The preferred form for passing a size of a struct is the following:

        p = kmalloc(sizeof(*p), ...);

The alternative form where struct name is spelled out hurts readability and
introduces an opportunity for a bug when the pointer variable type is changed
but the corresponding sizeof that is passed to a memory allocator is not.

> +	if (!drvdata)
> +		return -EINVAL;
> +	drvdata->ioreg = ioreg;
> +	spin_lock_init(&drvdata->reglock);
> +	platform_set_drvdata(pdev, drvdata);
> +	of_platform_bus_probe(np, of_anatop_subdevice_match, dev);
> +
> +	return 0;
> +}

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Sun Mar  4 01:51:48 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 4 Mar 2012 14:51:48 +0800
Subject: [PATCH v6 2/2] Regulator: Add Anatop regulator driver
In-Reply-To: <1330671641-6439-2-git-send-email-paul.liu@linaro.org>
References: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
 <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
 <1330671641-6439-2-git-send-email-paul.liu@linaro.org>
Message-ID: <20120304065145.GD10743@S2101-09.ap.freescale.net>

On Fri, Mar 02, 2012 at 03:00:41PM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is an integrated regulator inside i.MX6 SoC.
> There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
> And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
> This patch adds the Anatop regulator driver.
> 
> Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Liam Girdwood <lrg at ti.com>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> ---
>  .../bindings/regulator/anatop-regulator.txt        |   28 +++
>  drivers/regulator/Kconfig                          |    6 +
>  drivers/regulator/Makefile                         |    1 +
>  drivers/regulator/anatop-regulator.c               |  205 ++++++++++++++++++++
>  include/linux/regulator/anatop-regulator.h         |   40 ++++
>  5 files changed, 280 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.txt
>  create mode 100644 drivers/regulator/anatop-regulator.c
>  create mode 100644 include/linux/regulator/anatop-regulator.h
> 
> diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
> new file mode 100644
> index 0000000..f19cfea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
> @@ -0,0 +1,28 @@
> +Anatop Voltage regulators
> +
> +Required properties:
> +- compatible: Must be "fsl,anatop-regulator"
> +- vol-bit-shift: Bit shift for the register
> +- vol-bit-size: Number of bits used in the register

A better name might be vol-bit-width, considering shift and width
are generally a couple.

> +- min-bit-val: Minimum value of this register
> +- min-voltage: Minimum voltage of this regulator
> +- max-voltage: Maximum voltage of this regulator
> +
> +Any property defined as part of the core regulator
> +binding, defined in regulator.txt, can also be used.
> +
> +Example:
> +
> +	reg_vddpu: regulator-vddpu at 140 {
> +		compatible = "fsl,anatop-regulator";
> +		regulator-name = "vddpu";
> +		regulator-min-microvolt = <725000>;
> +		regulator-max-microvolt = <1300000>;
> +		regulator-always-on;
> +		reg = <0x140 1>;

The size cell is useless and confusing here.  I think we can just have
it like "reg = <0x140>;".

> +		vol-bit-shift = <9>;
> +		vol-bit-size = <5>;
> +		min-bit-val = <1>;
> +		min-voltage = <725000>;
> +		max-voltage = <1300000>;
> +	};
> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> index 7a61b17..5fbcda2 100644
> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -335,5 +335,11 @@ config REGULATOR_AAT2870
>  	  If you have a AnalogicTech AAT2870 say Y to enable the
>  	  regulator driver.
>  
> +config REGULATOR_ANATOP
> +	tristate "ANATOP LDO regulators"

A more descriptive prompt?

> +	depends on MFD_ANATOP
> +	help
> +	  Say y here to support ANATOP LDOs regulators.

Ditto.

> +
>  endif
>  
> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
> index 503bac8..8440871 100644
> --- a/drivers/regulator/Makefile
> +++ b/drivers/regulator/Makefile
> @@ -48,5 +48,6 @@ obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
>  obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
>  obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
>  obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
> +obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
>  
>  ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
> diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
> new file mode 100644
> index 0000000..84d8f50
> --- /dev/null
> +++ b/drivers/regulator/anatop-regulator.c
> @@ -0,0 +1,205 @@
> +/*
> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> +
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> +
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + */
> +
> +#include <linux/slab.h>
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/driver.h>
> +#include <linux/regulator/anatop-regulator.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/regulator/of_regulator.h>

It may be good to have <linux/regulator/*> headers grouped/sorted
together, something like:

#include <linux/regulator/anatop-regulator.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/of_regulator.h>

> +
> +static int anatop_set_voltage(struct regulator_dev *reg, int min_uV,
> +				  int max_uV, unsigned *selector)
> +{
> +	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
> +	u32 val, sel;
> +	int uv;
> +
> +	uv = min_uV;
> +	dev_dbg(&reg->dev, "%s: uv %d, min %d, max %d\n", __func__,
> +		uv, anatop_reg->min_voltage,
> +		anatop_reg->max_voltage);
> +
> +	if (uv < anatop_reg->min_voltage) {
> +		if (max_uV > anatop_reg->min_voltage)
> +			uv = anatop_reg->min_voltage;
> +		else
> +			return -EINVAL;
> +	}
> +
> +	if (anatop_reg->control_reg) {
> +		sel = (uv - anatop_reg->min_voltage) / 25000;
> +		if (sel * 25000 + anatop_reg->min_voltage
> +		    > anatop_reg->max_voltage)
> +			return -EINVAL;
> +		val = anatop_reg->min_bit_val + sel;
> +		*selector = sel;
> +		dev_dbg(&reg->dev, "%s: calculated val %d\n", __func__, val);
> +		anatop_set_bits(anatop_reg->mfd,
> +				anatop_reg->control_reg,
> +				anatop_reg->vol_bit_shift,
> +				anatop_reg->vol_bit_size,
> +				val);
> +		return 0;
> +	} else {
> +		return -ENOTSUPP;
> +	}
> +}
> +
> +static int anatop_get_voltage_sel(struct regulator_dev *reg)
> +{
> +	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
> +	int selector;
> +
> +	if (anatop_reg->control_reg) {
> +		u32 val = anatop_get_bits(anatop_reg->mfd,
> +					  anatop_reg->control_reg,
> +					  anatop_reg->vol_bit_shift,
> +					  anatop_reg->vol_bit_size);
> +		selector = val - anatop_reg->min_bit_val;
> +		return selector;
> +	} else {
> +		return -ENOTSUPP;
> +	}
> +}
> +
> +static int anatop_list_voltage(struct regulator_dev *reg, unsigned selector)
> +{
> +	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
> +	int uv;
> +
> +	uv = anatop_reg->min_voltage + selector * 25000;
> +	dev_dbg(&reg->dev, "vddio = %d, selector = %u\n", uv, selector);
> +
> +	return uv;
> +}
> +
> +static struct regulator_ops anatop_rops = {
> +	.set_voltage     = anatop_set_voltage,
> +	.get_voltage_sel = anatop_get_voltage_sel,
> +	.list_voltage    = anatop_list_voltage,
> +};
> +
> +int anatop_regulator_probe(struct platform_device *pdev)

static int __devinit

> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	struct regulator_desc *rdesc;
> +	struct regulator_dev *rdev;
> +	struct anatop_regulator *sreg;
> +	struct regulator_init_data *initdata;
> +	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
> +	const __be32 *rval;
> +	u64 ofsize;
> +
> +	initdata = of_get_regulator_init_data(dev, dev->of_node);

You already have a variable np being dev->of_node.

> +	sreg = devm_kzalloc(dev, sizeof(struct anatop_regulator), GFP_KERNEL);
> +	if (!sreg)
> +		return -EINVAL;
> +	rdesc = devm_kzalloc(dev, sizeof(struct regulator_desc), GFP_KERNEL);
> +	if (!rdesc)
> +		return -EINVAL;

Would something like the following be better?

	sreg = devm_kzalloc(dev, sizeof(*sreg) + sizeof(*rdesc), GFP_KERNEL);
	if (!sreg)
		return -ENOMEM;
	rdesc = (struct regulator_desc *)(sreg + 1);

> +	sreg->initdata = initdata;
> +	sreg->name = kstrdup(of_get_property(np, "regulator-name", NULL),
> +			     GFP_KERNEL);
> +	sreg->regulator = rdesc;
> +	memset(rdesc, 0, sizeof(struct regulator_desc));

sizeof(*rdesc)

> +	rdesc->name = sreg->name;
> +	rdesc->ops = &anatop_rops;
> +	rdesc->type = REGULATOR_VOLTAGE;
> +	rdesc->owner = THIS_MODULE;
> +	sreg->mfd = anatopmfd;
> +	rval = of_get_address(np, 0, &ofsize, NULL);
> +	if (rval)
> +		sreg->control_reg = be32_to_cpu(*rval);

With size cell removed, we can just read the "reg" property as an u32
with helper function of_property_read_u32().

> +	rval = of_get_property(np, "vol-bit-size", NULL);
> +	if (rval)
> +		sreg->vol_bit_size = be32_to_cpu(*rval);
> +	rval = of_get_property(np, "vol-bit-shift", NULL);
> +	if (rval)
> +		sreg->vol_bit_shift = be32_to_cpu(*rval);
> +	rval = of_get_property(np, "min-bit-val", NULL);
> +	if (rval)
> +		sreg->min_bit_val = be32_to_cpu(*rval);
> +	rval = of_get_property(np, "min-voltage", NULL);
> +	if (rval)
> +		sreg->min_voltage = be32_to_cpu(*rval);
> +	rval = of_get_property(np, "max-voltage", NULL);
> +	if (rval)
> +		sreg->max_voltage = be32_to_cpu(*rval);

All above can just use of_property_read_u32().

> +
> +	/* register regulator */
> +	rdev = regulator_register(rdesc, &pdev->dev,
> +				  initdata, sreg, pdev->dev.of_node);
> +	platform_set_drvdata(pdev, rdev);
> +
> +	if (IS_ERR(rdev)) {
> +		dev_err(&pdev->dev, "failed to register %s\n",
> +			rdesc->name);
> +		kfree(sreg->name);
> +		return PTR_ERR(rdev);
> +	}

Shouldn't the error checking go right after regulator_register() call?

> +
> +	return 0;
> +}
> +
> +int anatop_regulator_remove(struct platform_device *pdev)

static int __devexit

> +{
> +	struct regulator_dev *rdev = platform_get_drvdata(pdev);
> +	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
> +	kfree(sreg->name);
> +	regulator_unregister(rdev);
> +	return 0;
> +}
> +
> +struct of_device_id __devinitdata of_anatop_regulator_match_tbl[] = {

static

> +	{ .compatible = "fsl,anatop-regulator", },
> +	{ /* end */ }
> +};
> +
> +struct platform_driver anatop_regulator = {

static

> +	.driver = {
> +		.name	= "anatop_regulator",
> +		.owner  = THIS_MODULE,
> +		.of_match_table = of_anatop_regulator_match_tbl,
> +	},
> +	.probe	= anatop_regulator_probe,
> +	.remove	= anatop_regulator_remove,
> +};
> +
> +int anatop_regulator_init(void)

static int __init

> +{
> +	return platform_driver_register(&anatop_regulator);
> +}
> +postcore_initcall(anatop_regulator_init);
> +
> +void anatop_regulator_exit(void)

static void __exit

> +{
> +	platform_driver_unregister(&anatop_regulator);
> +}
> +module_exit(anatop_regulator_exit);
> +
> +MODULE_DESCRIPTION("ANATOP Regulator driver");
> +MODULE_LICENSE("GPL v2");

MODULE_AUTHOR?  Multiple people can be listed there.

> diff --git a/include/linux/regulator/anatop-regulator.h b/include/linux/regulator/anatop-regulator.h
> new file mode 100644
> index 0000000..7a9a05b
> --- /dev/null
> +++ b/include/linux/regulator/anatop-regulator.h
> @@ -0,0 +1,40 @@
> +/*
> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> +
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> +
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + */
> +
> +#ifndef __ANATOP_REGULATOR_H
> +#define __ANATOP_REGULATOR_H
> +
> +#include <linux/regulator/driver.h>
> +#include <linux/mfd/anatop.h>
> +
> +struct anatop_regulator {
> +	struct regulator_desc *regulator;
> +	struct regulator_init_data *initdata;
> +	const char *name;
> +	u32 control_reg;
> +	struct anatop *mfd;
> +	int vol_bit_shift;
> +	int vol_bit_size;
> +	int min_bit_val;
> +	int min_voltage;
> +	int max_voltage;
> +};

Does this structure really need to be public?

> +
> +#endif /* __ANATOP_REGULATOR_H */
> -- 
> 1.7.9.1
> 

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Sun Mar  4 03:33:00 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 4 Mar 2012 16:33:00 +0800
Subject: iMX53 quick start board and SATA
In-Reply-To: <4F50C734.90302@linuxtv.org>
References: <4F50C734.90302@linuxtv.org>
Message-ID: <20120304083258.GE10743@S2101-09.ap.freescale.net>

On Fri, Mar 02, 2012 at 02:12:20PM +0100, Michael Hunold wrote:
> Hello all,
> 
> I am trying to setup a iMX53 quick start board. This is my first
> encounter with Freescale, so please bear with me.
> 
> I used the Code Sourcery arm-2011.03 toolchain and a stock Linux 3.2.8
> kernel. I used "mx5_defconfig" and selected support for the "LOCO"
> board, nothing more.
> 
I think with the following patches in Linux 3.2, the i.MX53 SATA
support should be there, though I never played with it.

904c04f [libata] ahci_platform: Add the board_ids and pi refer to different features
d870ea1 MX53 Enable the AHCI SATA on MX53 SMD board
0661b82 MX53 Enable the AHCI SATA on MX53 LOCO board
e97e303 MX53 Enable the AHCI SATA on MX53 ARD board
97915bd AHCI Add the AHCI SATA feature on the MX53 platforms

-- 
Regards,
Shawn


From ohad at wizery.com  Sun Mar  4 05:01:11 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Sun,  4 Mar 2012 12:01:11 +0200
Subject: [PATCH] ARM: OMAP: fix iommu, not mailbox
Message-ID: <1330855271-28820-1-git-send-email-ohad@wizery.com>

For some weird (freudian?) reason, commit 435792d "ARM: OMAP: make
iommu subsys_initcall to fix builtin omap3isp" unintentionally changed
the mailbox's initcall instead of the iommu's.

Fix that.

Reported-by: Fernando Guzman Lugo <fernando.lugo at ti.com>
Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Cc: Joerg Roedel <Joerg.Roedel at amd.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/mailbox.c    |    3 +--
 arch/arm/mach-omap2/omap-iommu.c |    3 ++-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index a6db1e4..609ea2d 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -412,8 +412,7 @@ static void __exit omap2_mbox_exit(void)
 	platform_driver_unregister(&omap2_mbox_driver);
 }
 
-/* must be ready before omap3isp is probed */
-subsys_initcall(omap2_mbox_init);
+module_init(omap2_mbox_init);
 module_exit(omap2_mbox_exit);
 
 MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index b882204..ac49384 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -150,7 +150,8 @@ err_out:
 		platform_device_put(omap_iommu_pdev[i]);
 	return err;
 }
-module_init(omap_iommu_init);
+/* must be ready before omap3isp is probed */
+subsys_initcall(omap_iommu_init);
 
 static void __exit omap_iommu_exit(void)
 {
-- 
1.7.5.4



From robert.jarzmik at free.fr  Sun Mar  4 05:25:06 2012
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Sun, 04 Mar 2012 11:25:06 +0100
Subject: Status of gpio-pxa driver and dummy clock
In-Reply-To: <CAN1soZwtVm=qBw97AeeysfTXhCQg7XonKkHAE_dn6EYbLHnKBw@mail.gmail.com>
 (Haojian Zhuang's message of "Sun, 4 Mar 2012 09:05:47 +0800")
References: <87eht9tllp.fsf@free.fr>
 <CAN1soZwtVm=qBw97AeeysfTXhCQg7XonKkHAE_dn6EYbLHnKBw@mail.gmail.com>
Message-ID: <87aa3wu0hp.fsf@free.fr>

Haojian Zhuang <haojian.zhuang at gmail.com> writes:

> On Sun, Mar 4, 2012 at 5:34 AM, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
>> Hi Haojian,
>>
>> As you certainly know, Russell reverted the patch "ARM: pxa: add dummy clock for
>> sa1100-rtc", id a55b5adaf403c4d032e0871ad4ee3367782f4db6. As a consequence, the
>> dummy clock for gpio-pxa was removed, causing breakage of gpio-pxa driver.
>>
>> I wonder if you (or somebody through you) sent an update to fix the gpio-pxa by
>> either fixing gpio-pxa or adding back "pxa-gpio" clock. As of today, I see no
>> fix in 3.3-rc free (Linus tree).
>>
>
> This patch is already merged into arm-soc tree for v3.4. I don't have
> a plan to push it into
> v3.3.

Oh, you should push it to 3.3. It's a fix, and the mioa701 board is broken (and
probably many others PXA based boards too) because no GPIO is available (as
probe function of pxa-gpio always fail on clk_get()).

If you don't want to push it to 3.3, I'll have to send a fix to Arnd to fix the
breakage.

Without it, a PXA based kernel (pxa2xx) will hang in its boot phase, on the
first gpio_get_* or gpio_set_*, which is called by many drivers.

Cheers.

-- 
Robert


From ohad at wizery.com  Sun Mar  4 06:05:29 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Sun,  4 Mar 2012 13:05:29 +0200
Subject: [PATCH] ARM: OMAP: don't build hwspinlock in vain
Message-ID: <1330859129-354-1-git-send-email-ohad@wizery.com>

Cleanup: don't build mach-omap2/hwspinlock.c if the OMAP hwspinlock
driver isn't configured.

This will both shorten build time and avoid registering a device
which isn't needed.

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
---
Tony, it's probably better if you take it, to minimize omap merge conflicts.
Thanks!

 arch/arm/mach-omap2/Makefile |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 00d7025..5bce3bd 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -268,7 +268,9 @@ obj-y					+= $(smc91x-m) $(smc91x-y)
 
 smsc911x-$(CONFIG_SMSC911X)		:= gpmc-smsc911x.o
 obj-y					+= $(smsc911x-m) $(smsc911x-y)
-obj-$(CONFIG_ARCH_OMAP4)		+= hwspinlock.o
+ifneq ($(CONFIG_HWSPINLOCK_OMAP),)
+obj-y					+= hwspinlock.o
+endif
 
 obj-y					+= common-board-devices.o twl-common.o
 
-- 
1.7.5.4



From ohad at wizery.com  Sun Mar  4 06:47:16 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Sun, 4 Mar 2012 13:47:16 +0200
Subject: [PATCH V2] rpmsg: fix build warning when dma_addr_t is 64-bit
In-Reply-To: <1330530066-17461-1-git-send-email-mark.asselstine@windriver.com>
References: <201202291455.20688.arnd@arndb.de>
 <1330530066-17461-1-git-send-email-mark.asselstine@windriver.com>
Message-ID: <CAK=WgbbjaQm6R3FL-dzpyZtu17Xq28_L6xvOu_tm5PEzm3ESqg@mail.gmail.com>

On Wed, Feb 29, 2012 at 5:41 PM, Mark Asselstine
<mark.asselstine at windriver.com> wrote:
> dev_dbg() in rpmsg_probe() made use of the %x formatting that
> expects an 'unsigned int' which dma_addr_t is not in cases where
> dma_addr_t is 64-bit (CONFIG_ARCH_DMA_ADDR_T_64BIT). Casting to
> a 'unsigned long long' and using %llx will avoid this.
>
> Signed-off-by: Mark Asselstine <mark.asselstine at windriver.com>
> CC: Ohad Ben-Cohen <ohad at wizery.com>
> CC: Arnd Bergmann <arnd at arndb.de>

Thanks, Mark !

I'll send this to Arnd later this week together with the other
remoteproc/rpmsg patches.

Ohad.


From s.hauer at pengutronix.de  Sun Mar  4 06:52:01 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sun, 4 Mar 2012 12:52:01 +0100
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
Message-ID: <20120304115201.GB26882@pengutronix.de>

On Sat, Mar 03, 2012 at 09:14:43AM -0800, Turquette, Mike wrote:
> On Sat, Mar 3, 2012 at 5:31 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > On Sat, Mar 03, 2012 at 12:29:00AM -0800, Mike Turquette wrote:
> >> The common clock framework defines a common struct clk useful across
> >> most platforms as well as an implementation of the clk api that drivers
> >> can use safely for managing clocks.
> >>
> >> The net result is consolidation of many different struct clk definitions
> >> and platform-specific clock framework implementations.
> >>
> >> This patch introduces the common struct clk, struct clk_ops and an
> >> implementation of the well-known clock api in include/clk/clk.h.
> >> Platforms may define their own hardware-specific clock structure and
> >> their own clock operation callbacks, so long as it wraps an instance of
> >> struct clk_hw.
> >>
> >> See Documentation/clk.txt for more details.
> >>
> >> This patch is based on the work of Jeremy Kerr, which in turn was based
> >> on the work of Ben Herrenschmidt.
> >>
> >> +
> >> +/**
> >> + * struct clk_hw - handle for traversing from a struct clk to its corresponding
> >> + * hardware-specific structure. ?struct clk_hw should be declared within struct
> >> + * clk_foo and then referenced by the struct clk instance that uses struct
> >> + * clk_foo's clk_ops
> >> + *
> >> + * clk: pointer to the struct clk instance that points back to this struct
> >> + * clk_hw instance
> >> + */
> >> +struct clk_hw {
> >> + ? ? struct clk *clk;
> >> +};
> >
> > The reason for doing this is that struct clk should be an opaque cookie
> > for both drivers and implementers of clocks. I recently had the idea whether
> > the roles of these two structs could be swapped. So instead of the above we
> > could do:
> >
> > struct clk {
> > ? ? ? ?struct clk_hw *hw;
> > }
> 
> Firstly, struct clk is an opaque cookie for both drivers and
> implementers of clocks with this patchset.
> 
> Secondly, struct clk does indeed have a pointer to struct clk_hw.
> Refer to include/linux/clk-private.h in this patch.
> 
> The reference is cyclical.  A reference to struct clk can navigate to
> struct clk_foo via container_of (usually something like "#define
> to_clk_foo(_hw) container_of(_hw, struct clk_foo, hw)" where struct
> clk's pointer to it's .hw member is passed into one of the struct
> clk_ops callbacks.
> 
> Likewise if struct clk_foo needs the struct clk ptr for any reason
> then it can get it from foo->hw->clk.
> 
> I believe this patch already does what you suggest, but I might be
> missing your point.

In include/linux/clk-private.h you expose struct clk outside the core.
This has to be done to make static initializers possible. There is a big
warning in this file that it must not be included from files implementing
struct clk_ops. You can simply avoid this warning by declaring struct clk
with only a single member:

include/linux/clk.h:

struct clk {
	struct clk_internal *internal;
};

This way everybody knows struct clk (thus can embed it in their static
initializers), but doesn't know anything about the internal members. Now
in drivers/clk/clk.c you declare struct clk_internal exactly like struct
clk was declared before:

struct clk_internal {
	const char		*name;
	const struct clk_ops	*ops;
	struct clk_hw		*hw;
	struct clk		*parent;
	char			**parent_names;
	struct clk		**parents;
	u8			num_parents;
	unsigned long		rate;
	unsigned long		flags;
	unsigned int		enable_count;
	unsigned int		prepare_count;
	struct hlist_head	children;
	struct hlist_node	child_node;
	unsigned int		notifier_count;
#ifdef CONFIG_COMMON_CLK_DEBUG
	struct dentry		*dentry;
#endif
};

An instance of struct clk_internal will be allocated in
__clk_init/clk_register. Now the private data stays completely inside
the core and noone can abuse it.

With this __clk_init could be something like:

struct clk_initializer {
	const char		*name;
	const struct clk_ops	*ops;
	char			**parent_names;
	u8			num_parents;
	unsigned long		flags;
	struct clk		*clk;
};

void __clk_init(struct device *dev, struct clk_initializer *init);

I hope I made my intention a bit clearer.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From broonie at opensource.wolfsonmicro.com  Sun Mar  4 08:26:27 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 4 Mar 2012 13:26:27 +0000
Subject: [PATCH 08/20] ASoC: imx: initialize dma_params burstsize just in
 imx-ssi
In-Reply-To: <1330788001-10158-9-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-9-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120304132627.GA3083@opensource.wolfsonmicro.com>

On Sat, Mar 03, 2012 at 11:19:49PM +0800, Shawn Guo wrote:
> It's not necessary for imx-pcm-dma-mx2 to access imx_ssi.dma_params
> for burstsize initialization.  Instead, it can just be done in imx-ssi
> probe function once.

Applied, thanks.
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From broonie at opensource.wolfsonmicro.com  Sun Mar  4 08:29:53 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 4 Mar 2012 13:29:53 +0000
Subject: [PATCH v6 2/2] Regulator: Add Anatop regulator driver
In-Reply-To: <20120304065145.GD10743@S2101-09.ap.freescale.net>
References: <1330593052-15184-1-git-send-email-paul.liu@linaro.org>
 <1330671641-6439-1-git-send-email-paul.liu@linaro.org>
 <1330671641-6439-2-git-send-email-paul.liu@linaro.org>
 <20120304065145.GD10743@S2101-09.ap.freescale.net>
Message-ID: <20120304132953.GB3083@opensource.wolfsonmicro.com>

On Sun, Mar 04, 2012 at 02:51:48PM +0800, Shawn Guo wrote:

> > +	sreg = devm_kzalloc(dev, sizeof(struct anatop_regulator), GFP_KERNEL);
> > +	if (!sreg)
> > +		return -EINVAL;
> > +	rdesc = devm_kzalloc(dev, sizeof(struct regulator_desc), GFP_KERNEL);
> > +	if (!rdesc)
> > +		return -EINVAL;

> Would something like the following be better?

> 	sreg = devm_kzalloc(dev, sizeof(*sreg) + sizeof(*rdesc), GFP_KERNEL);
> 	if (!sreg)
> 		return -ENOMEM;
> 	rdesc = (struct regulator_desc *)(sreg + 1);

No, that sort of pointer arithmetic would be much worse - it's harder to
read and more likely to break.  However, embedding the regulator_desc in
sreg would achieve the same result without the legibility issues.
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From broonie at opensource.wolfsonmicro.com  Sun Mar  4 08:32:42 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 4 Mar 2012 13:32:42 +0000
Subject: [PATCH 00/20] ASoC: add imx-sgtl5000 machine driver working with
 fsl_ssi
In-Reply-To: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120304133242.GC3083@opensource.wolfsonmicro.com>

On Sat, Mar 03, 2012 at 11:19:41PM +0800, Shawn Guo wrote:
> It's the full series adding imx-sgtl5000 machine driver which works
> with fsl_ssi driver on DT based imx platforms.
>  - Patches 1 ~ 5: Convert audmux driver to a platform driver and move
>    it into ASoC folder.
>  - Patches 6 ~ 12: Merge ASoC imx and fsl folders.

This also contains a bunch of random cleanups and refactorings which
*really* should have been at the start of the series so they could be
applied without dependencies on the other stuff...
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From broonie at opensource.wolfsonmicro.com  Sun Mar  4 08:34:43 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 4 Mar 2012 13:34:43 +0000
Subject: [PATCH 07/20] ASoC: imx: move SND_SOC_AC97_BUS selection down to
 machine driver
In-Reply-To: <1330788001-10158-8-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-8-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120304133442.GD3083@opensource.wolfsonmicro.com>

On Sat, Mar 03, 2012 at 11:19:48PM +0800, Shawn Guo wrote:
> SND_SOC_AC97_BUS is selected to enable the AC97 support in soc-core.
> Rather than selecting the option under SND_IMX_SOC, it's better to
> leave the selection to individual machine driver which knows if AC97
> support is needed or not.

Applied.
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From broonie at opensource.wolfsonmicro.com  Sun Mar  4 08:38:18 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 4 Mar 2012 13:38:18 +0000
Subject: [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120304133818.GE3083@opensource.wolfsonmicro.com>

On Sat, Mar 03, 2012 at 11:20:01PM +0800, Shawn Guo wrote:

> +	ret = snd_soc_dai_set_fmt(rtd->codec_dai, SND_SOC_DAIFMT_I2S |
> +						  SND_SOC_DAIFMT_NB_NF |
> +						  SND_SOC_DAIFMT_CBM_CFM);

Initialise this from the card.  

Since none of the startup is dynamic it should all be done on DAI init
rather than rerun each time audio is started.

> +	/* Add soc-audio device */
> +	data->soc_audio_pdev = platform_device_alloc("soc-audio", -1);
> +	if (!data->soc_audio_pdev) {
> +		ret = -ENOMEM;
> +		goto err;
> +	}

No, use snd_soc_register_card().  soc-audio has been deprecated since
2.6.38.

> +static int __devexit imx_sgtl5000_remove(struct platform_device *pdev)
> +{
> +	struct imx_sgtl5000_data *data = dev_get_drvdata(&pdev->dev);
> +
> +	platform_device_unregister(data->pcm_audio_pdev);

This looks like there's a problem with the bindings, why are you
registering the DMA device from the card?
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From broonie at opensource.wolfsonmicro.com  Sun Mar  4 08:39:08 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 4 Mar 2012 13:39:08 +0000
Subject: [PATCH 19/20] ASoC: rename sgtl5000 device tree binding document
In-Reply-To: <1330788001-10158-20-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-20-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120304133907.GF3083@opensource.wolfsonmicro.com>

On Sat, Mar 03, 2012 at 11:20:00PM +0800, Shawn Guo wrote:
> It moves and renames sgtl5000 device tree binding document to make
> it aligned with other codecs.

Applied, thanks.
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From broonie at opensource.wolfsonmicro.com  Sun Mar  4 08:41:35 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 4 Mar 2012 13:41:35 +0000
Subject: [PATCH 09/20] ASoC: imx: separate imx-pcm bits from imx-ssi driver
In-Reply-To: <1330788001-10158-10-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-10-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120304134135.GG3083@opensource.wolfsonmicro.com>

On Sat, Mar 03, 2012 at 11:19:50PM +0800, Shawn Guo wrote:
> Currently the imx-ssi.c[h] accommodates the imx-pcm common bits which
> are shared between imx-pcm-dma-mx2 and imx-pcm-fiq drivers.  It assumes
> that imx-pcm-dma-mx2 and imx-pcm-fiq will always be used together with
> imx-ssi driver.  However this becomes untrue when we see that driver
> sound/soc/fsl/fsl_ssi could possibly work with imx-pcm-dma-mx2 too.

I was going to apply this and the next patch but they depend on the
audmux stuff so they'll at least have to wait until that gets applied.
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From andrew at lunn.ch  Sun Mar  4 09:26:48 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 4 Mar 2012 15:26:48 +0100
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <1330763341-3437-5-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
Message-ID: <20120304142648.GB11546@lunn.ch>

> +#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,	\
> +				_flags, _reg, _bit_idx,		\
> +				_gate_flags, _lock)		\
> +	static struct clk _name;				\
> +	static char *_name##_parent_names[] = {			\
> +		_parent_name,					\
> +	};							\
> +	static struct clk *_name##_parents[] = {		\
> +		_parent_ptr,					\
> +	};							\
> +	static struct clk_gate _name##_hw = {			\
> +		.hw = {						\
> +			.clk = &_name,				\
> +		},						\
> +		.reg = _reg,					\
> +		.bit_idx = _bit_idx,				\
> +		.flags = _gate_flags				\

Hi Mike

Looks like a , is missing here after _gate_flags.

      Andrew


From andrew at lunn.ch  Sun Mar  4 09:35:02 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 4 Mar 2012 15:35:02 +0100
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <1330763341-3437-5-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
Message-ID: <20120304143502.GC11546@lunn.ch>

> +#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,	\
> +				_flags, _reg, _bit_idx,		\
> +				_gate_flags, _lock)		\
> +	static struct clk _name;				\
> +	static char *_name##_parent_names[] = {			\
> +		_parent_name,					\
> +	};							\
> +	static struct clk *_name##_parents[] = {		\
> +		_parent_ptr,					\
> +	};							\
> +	static struct clk_gate _name##_hw = {			\
> +		.hw = {						\
> +			.clk = &_name,				\
> +		},						\
> +		.reg = _reg,					\
> +		.bit_idx = _bit_idx,				\
> +		.flags = _gate_flags				\
> +		.lock = _lock,					\
> +	};							\
> +	static struct clk _name = {				\
> +		.name = #_name,					\
> +		.ops = &clk_gate_ops,				\
> +		.hw = &_name##_hw.hw,				\
> +		.parent_names = _name##_parent_names,		\
> +		.num_parents =					\
> +			ARRAY_SIZE(_name##parent_names),	\

Hi Mike

This should be _name##_parent_names, i.e. you are missing a _.

With this and the previous change, i get something which at least
compiles...

	Andrew


From michael at walle.cc  Sun Mar  4 09:59:23 2012
From: michael at walle.cc (Michael Walle)
Date: Sun, 4 Mar 2012 15:59:23 +0100
Subject: [PATCH 3/4] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>
Message-ID: <201203041559.23810.michael@walle.cc>

Am Donnerstag 01 M?rz 2012, 19:20:54 schrieb Jason Cooper:
> The comment at mach-kirkwood/common.c:469, says this device is in every
> kirkwood board.  So, it is placed in kirkwood.dtsi.
> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
>  arch/arm/mach-kirkwood/board-dt.c |    1 -
>  arch/arm/mach-kirkwood/common.c   |    2 +-
>  arch/arm/mach-kirkwood/common.h   |    1 -
>  drivers/rtc/rtc-mv.c              |   19 +++++++++++++++++++
>  5 files changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/kirkwood.dtsi
> b/arch/arm/boot/dts/kirkwood.dtsi index 771c6bb..5fb185c 100644
> --- a/arch/arm/boot/dts/kirkwood.dtsi
> +++ b/arch/arm/boot/dts/kirkwood.dtsi
> @@ -2,5 +2,11 @@
> 
>  / {
>  	compatible = "marvell,kirkwood";
> +
> +	rtc at f1010300 {
> +		compatible = "marvell,rtc";
what about the names used here?

in my older patch series i flagged all converted devices with two 
compatibility names. Eg:

       { .compatible = "marvell,orion5x-rtc", },
       { .compatible = "marvell,kirkwood-rtc", },

IMHO marvell,rtc is i little too general, i guess marvell won't have only one 
rtc ;)

Other opinions?

-- 
Michael


From michael at walle.cc  Sun Mar  4 10:12:44 2012
From: michael at walle.cc (Michael Walle)
Date: Sun, 4 Mar 2012 16:12:44 +0100
Subject: [PATCH 4/5 v2] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <4de611961e8210a0a2c3b56fe72b40dba638752a.1330709314.git.jason@lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <4de611961e8210a0a2c3b56fe72b40dba638752a.1330709314.git.jason@lakedaemon.net>
Message-ID: <201203041612.44966.michael@walle.cc>

Am Freitag 02 M?rz 2012, 18:50:21 schrieb Jason Cooper:
> The comment at mach-kirkwood/common.c:469, says this device is in every
> kirkwood board.  So, it is placed in kirkwood.dtsi.
> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
> 
> Changes since v1:
> 
>     - removed unnecessary of_*() code from _probe()
>     - use of_match_ptr()
> 
>  arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
>  arch/arm/mach-kirkwood/board-dt.c |    1 -
>  arch/arm/mach-kirkwood/common.c   |    2 +-
>  arch/arm/mach-kirkwood/common.h   |    1 -
>  drivers/rtc/rtc-mv.c              |    7 +++++++
>  5 files changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/kirkwood.dtsi
> b/arch/arm/boot/dts/kirkwood.dtsi index 771c6bb..5fb185c 100644
> --- a/arch/arm/boot/dts/kirkwood.dtsi
> +++ b/arch/arm/boot/dts/kirkwood.dtsi
> @@ -2,5 +2,11 @@
> 
>  / {
>  	compatible = "marvell,kirkwood";
> +
> +	rtc at f1010300 {
> +		compatible = "marvell,rtc";
> +		reg = <0xf1010300 0x1f>;
> +		interrupts = <53>;
> +	};
>  };
> 
> diff --git a/arch/arm/mach-kirkwood/board-dt.c
> b/arch/arm/mach-kirkwood/board-dt.c index 2a45656..6e18338 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -134,7 +134,6 @@ static void __init kirkwood_dt_init(void)
>  #endif
> 
>  	/* internal devices that every board has */
> -	kirkwood_rtc_init();
>  	kirkwood_wdt_init();
>  	kirkwood_xor0_init();
>  	kirkwood_xor1_init();
> diff --git a/arch/arm/mach-kirkwood/common.c
> b/arch/arm/mach-kirkwood/common.c index 167b6c8..0c0375f 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -163,7 +163,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition
> *parts, int nr_parts,
> /*************************************************************************
> **** * SoC RTC
>  
> **************************************************************************
> **/ -void __init kirkwood_rtc_init(void)
> +static void __init kirkwood_rtc_init(void)
>  {
>  	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
>  }
> diff --git a/arch/arm/mach-kirkwood/common.h
> b/arch/arm/mach-kirkwood/common.h index c382447..ca08826 100644
> --- a/arch/arm/mach-kirkwood/common.h
> +++ b/arch/arm/mach-kirkwood/common.h
> @@ -53,7 +53,6 @@ void kirkwood_restart(char, const char *);
> 
>  char *kirkwood_id(void);
>  void kirkwood_l2_init(void);
> -void kirkwood_rtc_init(void);
>  void kirkwood_wdt_init(void);
>  void kirkwood_xor0_init(void);
>  void kirkwood_xor1_init(void);
> diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c
> index 768e2ed..3108b18 100644
> --- a/drivers/rtc/rtc-mv.c
> +++ b/drivers/rtc/rtc-mv.c
> @@ -12,6 +12,7 @@
>  #include <linux/bcd.h>
>  #include <linux/io.h>
>  #include <linux/platform_device.h>
> +#include <linux/of.h>
>  #include <linux/delay.h>
>  #include <linux/gfp.h>
>  #include <linux/module.h>
> @@ -294,11 +295,17 @@ static int __exit mv_rtc_remove(struct
> platform_device *pdev) return 0;
>  }
> 
> +static struct of_device_id rtc_mv_of_match_table[] = {
> +	{ .compatible = "marvell,rtc", },
> +	{}
> +};
> +
Isn't here an ifdef CONFIG_OF missing to prevent compiler warnings?

>  static struct platform_driver mv_rtc_driver = {
>  	.remove		= __exit_p(mv_rtc_remove),
>  	.driver		= {
>  		.name	= "rtc-mv",
>  		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(rtc_mv_of_match_table),
>  	},
>  };


-- 
Michael



From arnd at arndb.de  Sun Mar  4 11:48:17 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 4 Mar 2012 16:48:17 +0000
Subject: [PATCH 3/4] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <201203041559.23810.michael@walle.cc>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>
 <201203041559.23810.michael@walle.cc>
Message-ID: <201203041648.17428.arnd@arndb.de>

On Sunday 04 March 2012, Michael Walle wrote:
> in my older patch series i flagged all converted devices with two 
> compatibility names. Eg:
> 
>        { .compatible = "marvell,orion5x-rtc", },
>        { .compatible = "marvell,kirkwood-rtc", },
> 
> IMHO marvell,rtc is i little too general, i guess marvell won't have only one 
> rtc ;)
> 
> Other opinions?

Being specific is certainly good, and it may also be a good idea to
list the first one it's compatible with in the device tree source.

So the device tree for a 88F6281 soc could list

	compatible = "marvell,88f6281-rtc", "marvell,kirkwood-rtc", "marvell,orion-rtc";

This would give the device driver the option which one to bind to. Anything that
has an rtc compatible with the one in orion should list that one, so that the driver
only has to list that one if they are truely identical, but if the driver has to
get modified later to know the difference between orion and kirkwood rtcs, it can
check the more specific value.

	Arnd


From arnd at arndb.de  Sun Mar  4 11:50:52 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 4 Mar 2012 16:50:52 +0000
Subject: [PATCH 4/5 v2] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <201203041612.44966.michael@walle.cc>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <4de611961e8210a0a2c3b56fe72b40dba638752a.1330709314.git.jason@lakedaemon.net>
 <201203041612.44966.michael@walle.cc>
Message-ID: <201203041650.52217.arnd@arndb.de>

On Sunday 04 March 2012, Michael Walle wrote:
> > @@ -294,11 +295,17 @@ static int __exit mv_rtc_remove(struct
> > platform_device *pdev) return 0;
> >  }
> > 
> > +static struct of_device_id rtc_mv_of_match_table[] = {
> > +     { .compatible = "marvell,rtc", },
> > +     {}
> > +};
> > +
> Isn't here an ifdef CONFIG_OF missing to prevent compiler warnings?
> 

Yes, I guess so. I keep thinking that an __unused attribute would
actually be more helpful here because it lets the compiler automatically
discard the symbol when it's not used, but we still get potential
compiler errors and warnings if something inside of the unused data
is broken.

	Arnd


From heiko at sntech.de  Sun Mar  4 12:42:35 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sun, 4 Mar 2012 18:42:35 +0100
Subject: [PATCH 0/3] S3C24XX: Enable DMA on S3C2416 by sharing S3C2443-DMA
Message-ID: <201203041842.35420.heiko@sntech.de>

The S3C2416/2450 contains the same DMA register layout as the S3C2443.
Therefore it can simply share this dma selection definition.

As we use the S3C2443_DMA the S3C2416_DMA is no longer necessary. The
third patch removes this remnant of the S3C24XX merge.

The whole series was made on top of the recent S3C24XX merge.

Heiko Stuebner (3):
  ARM: S3C24XX: Fix indentation of dma-s3c2443
  ARM: S3C24XX: Reuse S3C2443 dma for S3C2416
  ARM: S3C24XX: remove obsolete S3C2416_DMA option

 arch/arm/Kconfig                              |    1 -
 arch/arm/mach-s3c2416/Kconfig                 |   14 -----------
 arch/arm/mach-s3c2416/Makefile                |   12 ----------
 arch/arm/mach-s3c24xx/Kconfig                 |   10 ++++----
 arch/arm/mach-s3c24xx/Makefile                |    2 +-
 arch/arm/mach-s3c24xx/dma-s3c2443.c           |   30 ++++++++++++++++++++-----
 arch/arm/plat-samsung/include/plat/regs-dma.h |    2 +-
 7 files changed, 31 insertions(+), 40 deletions(-)
 delete mode 100644 arch/arm/mach-s3c2416/Kconfig
 delete mode 100644 arch/arm/mach-s3c2416/Makefile

-- 
1.7.2.3



From andrew at lunn.ch  Sun Mar  4 12:42:29 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 4 Mar 2012 18:42:29 +0100
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <1330763341-3437-5-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
Message-ID: <20120304174229.GD11546@lunn.ch>

On Sat, Mar 03, 2012 at 12:29:01AM -0800, Mike Turquette wrote:
> Many platforms support simple gateable clocks, fixed-rate clocks,
> adjustable divider clocks and multi-parent multiplexer clocks.
> 
> This patch introduces basic clock types for the above-mentioned hardware
> which share some common characteristics.

Hi Mike

These basic clocks don't allow the use of prepare/unprepare, from the
side of the clock provider. I think i need this.

The Orion Kirkwood SoC has clock gating for most of its on chip
peripherals, which the other older Orion devices don't have. The SATA
and PCIe also allows the PHY to be shut down, again which older Orion
devices don't have. The current code links the clock and the PHY
together, shutting both down are the same time. So i would like to
perform the PHY shutdown in the unprepare() function of the clk
driver.

Is allowing to pass prepare/unprepare functions to basic clocks
something you want to support? If i prepare a patch would you consider
it?

	Thanks
		Andrew


From heiko at sntech.de  Sun Mar  4 12:43:24 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sun, 4 Mar 2012 18:43:24 +0100
Subject: [PATCH 1/3] ARM: S3C24XX: Fix indentation of dma-s3c2443
In-Reply-To: <201203041842.35420.heiko@sntech.de>
References: <201203041842.35420.heiko@sntech.de>
Message-ID: <201203041843.24907.heiko@sntech.de>

Spaces seem to have slipped in at some point in the past.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/dma-s3c2443.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 1422451..d9e1b3b 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -71,11 +71,11 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
 		.name		= "uart1",
 		.channels	= MAP(S3C2443_DMAREQSEL_UART1_0),
 	},
-      	[DMACH_UART2] = {
+	[DMACH_UART2] = {
 		.name		= "uart2",
 		.channels	= MAP(S3C2443_DMAREQSEL_UART2_0),
 	},
-      	[DMACH_UART3] = {
+	[DMACH_UART3] = {
 		.name		= "uart3",
 		.channels	= MAP(S3C2443_DMAREQSEL_UART3_0),
 	},
@@ -87,11 +87,11 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
 		.name		= "uart1",
 		.channels	= MAP(S3C2443_DMAREQSEL_UART1_1),
 	},
-      	[DMACH_UART2_SRC2] = {
+	[DMACH_UART2_SRC2] = {
 		.name		= "uart2",
 		.channels	= MAP(S3C2443_DMAREQSEL_UART2_1),
 	},
-      	[DMACH_UART3_SRC2] = {
+	[DMACH_UART3_SRC2] = {
 		.name		= "uart3",
 		.channels	= MAP(S3C2443_DMAREQSEL_UART3_1),
 	},
-- 
1.7.2.3



From heiko at sntech.de  Sun Mar  4 12:44:29 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sun, 4 Mar 2012 18:44:29 +0100
Subject: [PATCH 2/3] ARM: S3C24XX: Reuse S3C2443 dma for S3C2416
In-Reply-To: <201203041842.35420.heiko@sntech.de>
References: <201203041842.35420.heiko@sntech.de>
Message-ID: <201203041844.30047.heiko@sntech.de>

The dma controller is similar in S3C2443 and S3C2416 and has also
the same register layout with the same REQSEL-bits in the source
select.

The only small difference is the SIO channel of the S3C2443 for the
non-hsmmc controller which is not present on S3C2416/2450 and
second spi channel which is not present on the S3C2416.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/Kconfig                 |   10 +++++-----
 arch/arm/mach-s3c24xx/Makefile                |    2 +-
 arch/arm/mach-s3c24xx/dma-s3c2443.c           |   22 ++++++++++++++++++++--
 arch/arm/plat-samsung/include/plat/regs-dma.h |    2 +-
 4 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 48af6fc..5ebd150 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -42,7 +42,7 @@ config CPU_S3C2416
 	select CPU_LLSERIAL_S3C2440
 	select SAMSUNG_CLKSRC
 	select S3C2443_COMMON
-	select S3C2416_DMA if S3C24XX_DMA
+	select S3C2443_DMA if S3C24XX_DMA
 	select S3C2416_PM if PM
 	help
 	  Support for the S3C2416 SoC from the S3C24XX line
@@ -479,15 +479,15 @@ config S3C2443_COMMON
 	  Common code for the S3C2443 and similar processors, which includes
 	  the S3C2416 and S3C2450.
 
-endif	# CPU_S3C2443 || CPU_S3C2416
-
-if CPU_S3C2443
-
 config S3C2443_DMA
 	bool
 	help
 	  Internal config node for S3C2443 DMA support
 
+endif	# CPU_S3C2443 || CPU_S3C2416
+
+if CPU_S3C2443
+
 comment "S3C2443 Boards"
 
 config MACH_SMDK2443
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 876e5e5..1909d66 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -32,11 +32,11 @@ obj-$(CONFIG_CPU_S3C244X)	+= s3c244x.o irq-s3c244x.o clock-s3c244x.o
 obj-$(CONFIG_S3C2440_DMA)	+= dma-s3c2440.o
 
 obj-$(CONFIG_CPU_S3C2443)	+= s3c2443.o irq-s3c2443.o clock-s3c2443.o
-obj-$(CONFIG_S3C2443_DMA)	+= dma-s3c2443.o
 
 # common code
 
 obj-$(CONFIG_S3C2443_COMMON)	+= common-s3c2443.o
+obj-$(CONFIG_S3C2443_DMA)	+= dma-s3c2443.o
 
 #
 # machine support
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index d9e1b3b..e227c47 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -51,7 +51,7 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
 		.name		= "xdreq1",
 		.channels	= MAP(S3C2443_DMAREQSEL_XDREQ1),
 	},
-	[DMACH_SDI] = {
+	[DMACH_SDI] = { /* only on S3C2443 */
 		.name		= "sdi",
 		.channels	= MAP(S3C2443_DMAREQSEL_SDI),
 	},
@@ -59,7 +59,7 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
 		.name		= "spi0",
 		.channels	= MAP(S3C2443_DMAREQSEL_SPI0TX),
 	},
-	[DMACH_SPI1] = {
+	[DMACH_SPI1] = { /* only on S3C2443/S3C2450 */
 		.name		= "spi1",
 		.channels	= MAP(S3C2443_DMAREQSEL_SPI1TX),
 	},
@@ -142,6 +142,23 @@ static int __init s3c2443_dma_add(struct device *dev,
 	return s3c24xx_dma_init_map(&s3c2443_dma_sel);
 }
 
+#ifdef CONFIG_CPU_S3C2416
+/* S3C2416 DMA contains the same selection table as the S3C2443 */
+static struct subsys_interface s3c2416_dma_interface = {
+	.name		= "s3c2416_dma",
+	.subsys		= &s3c2416_subsys,
+	.add_dev	= s3c2443_dma_add,
+};
+
+static int __init s3c2416_dma_init(void)
+{
+	return subsys_interface_register(&s3c2416_dma_interface);
+}
+
+arch_initcall(s3c2416_dma_init);
+#endif
+
+#ifdef CONFIG_CPU_S3C2443
 static struct subsys_interface s3c2443_dma_interface = {
 	.name		= "s3c2443_dma",
 	.subsys		= &s3c2443_subsys,
@@ -154,3 +171,4 @@ static int __init s3c2443_dma_init(void)
 }
 
 arch_initcall(s3c2443_dma_init);
+#endif
diff --git a/arch/arm/plat-samsung/include/plat/regs-dma.h b/arch/arm/plat-samsung/include/plat/regs-dma.h
index 178bccb..a7d622e 100644
--- a/arch/arm/plat-samsung/include/plat/regs-dma.h
+++ b/arch/arm/plat-samsung/include/plat/regs-dma.h
@@ -119,7 +119,7 @@
 #define S3C2412_DMAREQSEL_UART2_1	S3C2412_DMAREQSEL_SRC(24)
 #endif /* CONFIG_CPU_S3C2412 */
 
-#ifdef CONFIG_CPU_S3C2443
+#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
 
 #define S3C2443_DMAREQSEL_SRC(x)	((x) << 1)
 
-- 
1.7.2.3



From heiko at sntech.de  Sun Mar  4 12:45:18 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sun, 4 Mar 2012 18:45:18 +0100
Subject: [PATCH 3/3] ARM: S3C24XX: remove obsolete S3C2416_DMA option
In-Reply-To: <201203041842.35420.heiko@sntech.de>
References: <201203041842.35420.heiko@sntech.de>
Message-ID: <201203041845.18405.heiko@sntech.de>

The S3C2416 now reuses the dma selection of the S3C2443.
Therefore it is not necessary to keep the S3C2416_DMA option around.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/Kconfig               |    1 -
 arch/arm/mach-s3c2416/Kconfig  |   14 --------------
 arch/arm/mach-s3c2416/Makefile |   12 ------------
 3 files changed, 0 insertions(+), 27 deletions(-)
 delete mode 100644 arch/arm/mach-s3c2416/Kconfig
 delete mode 100644 arch/arm/mach-s3c2416/Makefile

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c0a87d0..86d0acf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1068,7 +1068,6 @@ source "arch/arm/plat-spear/Kconfig"
 source "arch/arm/mach-s3c24xx/Kconfig"
 if ARCH_S3C24XX
 source "arch/arm/mach-s3c2412/Kconfig"
-source "arch/arm/mach-s3c2416/Kconfig"
 source "arch/arm/mach-s3c2440/Kconfig"
 endif
 
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
deleted file mode 100644
index faaa289..0000000
--- a/arch/arm/mach-s3c2416/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-# arch/arm/mach-s3c2416/Kconfig
-#
-# Copyright 2009 Yauhen Kharuzhy <jekhor at gmail.com>
-#
-# Licensed under GPLv2
-
-# note, this also supports the S3C2450 which is so similar it has the same
-# ID code as the S3C2416.
-
-config S3C2416_DMA
-	bool
-	depends on CPU_S3C2416
-	help
-	  Internal config node for S3C2416 DMA support
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
deleted file mode 100644
index 3299f19..0000000
--- a/arch/arm/mach-s3c2416/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# arch/arm/mach-s3c2416/Makefile
-#
-# Copyright 2009 Yauhen Kharuzhy <jekhor at gmail.com>
-#
-# Licensed under GPLv2
-
-obj-y				:=
-obj-m				:=
-obj-n				:=
-obj-				:=
-
-#obj-$(CONFIG_S3C2416_DMA)	+= dma.o
-- 
1.7.2.3



From heiko at sntech.de  Sun Mar  4 13:02:38 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sun, 4 Mar 2012 19:02:38 +0100
Subject: [PATCH 0/6] S3C24XX: Add support for HSSPI on S3C2416/S3C2443
Message-ID: <201203041902.38318.heiko@sntech.de>

The S3C2416/S3C2443/S3C2450 SoCs contain HSSPI controllers compatible
with the ones in the S3C64xx and later.

The second patch modifying the dma selection depends on the series
enabling the dma support on the S3C2416, but as the whole s3c64xx-spi
driver needs dma support this should be ok.

Tested on an Asus DR-900 ebook reader with a Marvell MR8686 using the
libertas driver.

Heiko Stuebner (6):
  ARM: S3C24XX: Add forgotten clock lookup table to S3C2443
  ARM: S3C24XX: claim spi channels for hsspi in dma-s3c2443
  ARM: S3C24XX: Add map entries needed by the s3c64xx-spi devices
  ARM: S3C24XX: Add clock-lookup entries required by s3c64xx-spi
  ARM: S3C24XX: Add HSSPI setup callback for s3c64xx-spi driver
  spi/s3c64xx: Allow usage for ARCH_S3C24XX

 arch/arm/mach-s3c24xx/Kconfig            |    5 ++++
 arch/arm/mach-s3c24xx/Makefile           |    1 +
 arch/arm/mach-s3c24xx/clock-s3c2416.c    |    1 +
 arch/arm/mach-s3c24xx/clock-s3c2443.c    |    6 ++++
 arch/arm/mach-s3c24xx/common-s3c2443.c   |   15 +++++++----
 arch/arm/mach-s3c24xx/dma-s3c2443.c      |   16 +++++++++---
 arch/arm/mach-s3c24xx/include/mach/dma.h |    4 +++
 arch/arm/mach-s3c24xx/include/mach/map.h |    5 ++++
 arch/arm/mach-s3c24xx/setup-spi.c        |   39 ++++++++++++++++++++++++++++++
 drivers/spi/Kconfig                      |    2 +-
 10 files changed, 84 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/mach-s3c24xx/setup-spi.c

-- 
1.7.2.3



From heiko at sntech.de  Sun Mar  4 13:03:22 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sun, 4 Mar 2012 19:03:22 +0100
Subject: [PATCH 1/6] ARM: S3C24XX: Add forgotten clock lookup table to S3C2443
In-Reply-To: <201203041902.38318.heiko@sntech.de>
References: <201203041902.38318.heiko@sntech.de>
Message-ID: <201203041903.22607.heiko@sntech.de>

When the hsmmc clock lookup was changed to be lookup tables based,
it seems the S3C2443 was forgotten.

As subsequent patches will want to add more lookups to it, this
patch adds the base table with missing hsmmc lookup.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/clock-s3c2443.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index efb3ac3..bce1cd3 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -179,6 +179,10 @@ static struct clk *clks[] __initdata = {
 	&clk_hsmmc,
 };
 
+static struct clk_lookup s3c2443_clk_lookup[] = {
+	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
+};
+
 void __init s3c2443_init_clocks(int xtal)
 {
 	unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
@@ -210,6 +214,7 @@ void __init s3c2443_init_clocks(int xtal)
 
 	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+	clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
 
 	s3c_pwmclk_init();
 }
-- 
1.7.2.3



From heiko at sntech.de  Sun Mar  4 13:03:59 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sun, 4 Mar 2012 19:03:59 +0100
Subject: [PATCH 2/6] ARM: S3C24XX: claim spi channels for hsspi in dma-s3c2443
In-Reply-To: <201203041902.38318.heiko@sntech.de>
References: <201203041902.38318.heiko@sntech.de>
Message-ID: <201203041903.59525.heiko@sntech.de>

SoCs starting with the S3C2443 contain SPI controllers compatible with the
spi-s3c64xx driver and therefore need separate dma channels for rx and tx.

This patch introduces dma channel declarations for these and changes the
dma-s3c2443.c accordingly.

None of the older SoCs use the spi-dma at all. Most boards bitbang their
spi use and the spi-s3c24xx driver also does not use the dma system.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/dma-s3c2443.c      |   16 ++++++++++++----
 arch/arm/mach-s3c24xx/include/mach/dma.h |    4 ++++
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index e227c47..2d94228 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -55,12 +55,20 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
 		.name		= "sdi",
 		.channels	= MAP(S3C2443_DMAREQSEL_SDI),
 	},
-	[DMACH_SPI0] = {
-		.name		= "spi0",
+	[DMACH_SPI0_RX] = {
+		.name		= "spi0-rx",
+		.channels	= MAP(S3C2443_DMAREQSEL_SPI0RX),
+	},
+	[DMACH_SPI0_TX] = {
+		.name		= "spi0-tx",
 		.channels	= MAP(S3C2443_DMAREQSEL_SPI0TX),
 	},
-	[DMACH_SPI1] = { /* only on S3C2443/S3C2450 */
-		.name		= "spi1",
+	[DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
+		.name		= "spi1-rx",
+		.channels	= MAP(S3C2443_DMAREQSEL_SPI1RX),
+	},
+	[DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
+		.name		= "spi1-tx",
 		.channels	= MAP(S3C2443_DMAREQSEL_SPI1TX),
 	},
 	[DMACH_UART0] = {
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index acbdfec..454831b 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -47,6 +47,10 @@ enum dma_ch {
 	DMACH_UART2_SRC2,
 	DMACH_UART3,		/* s3c2443 has extra uart */
 	DMACH_UART3_SRC2,
+	DMACH_SPI0_TX,		/* s3c2443/2416/2450 hsspi0 */
+	DMACH_SPI0_RX,		/* s3c2443/2416/2450 hsspi0 */
+	DMACH_SPI1_TX,		/* s3c2443/2450 hsspi1 */
+	DMACH_SPI1_RX,		/* s3c2443/2450 hsspi1 */
 	DMACH_MAX,		/* the end entry */
 };
 
-- 
1.7.2.3



From heiko at sntech.de  Sun Mar  4 13:04:38 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sun, 4 Mar 2012 19:04:38 +0100
Subject: [PATCH 3/6] ARM: S3C24XX: Add map entries needed by the s3c64xx-spi
 devices
In-Reply-To: <201203041902.38318.heiko@sntech.de>
References: <201203041902.38318.heiko@sntech.de>
Message-ID: <201203041904.38865.heiko@sntech.de>

The S3C_PA_SPIx constants are only used by the s3c64xx-spi driver
and don't conflict with the older SoCs as they don't support hsspi.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/include/mach/map.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h
index 78ae807..8ba381f 100644
--- a/arch/arm/mach-s3c24xx/include/mach/map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/map.h
@@ -98,6 +98,8 @@
 
 /* SPI */
 #define S3C2410_PA_SPI	   (0x59000000)
+#define S3C2443_PA_SPI0		(0x52000000)
+#define S3C2443_PA_SPI1		S3C2410_PA_SPI
 
 /* SDI */
 #define S3C2410_PA_SDI	   (0x5A000000)
@@ -162,4 +164,7 @@
 #define S3C_PA_WDT	    S3C2410_PA_WATCHDOG
 #define S3C_PA_NAND	    S3C24XX_PA_NAND
 
+#define S3C_PA_SPI0		S3C2443_PA_SPI0
+#define S3C_PA_SPI1		S3C2443_PA_SPI1
+
 #endif /* __ASM_ARCH_MAP_H */
-- 
1.7.2.3



From heiko at sntech.de  Sun Mar  4 13:05:40 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sun, 4 Mar 2012 19:05:40 +0100
Subject: [PATCH 4/6] ARM: S3C24XX: Add clock-lookup entries required by
 s3c64xx-spi
In-Reply-To: <201203041902.38318.heiko@sntech.de>
References: <201203041902.38318.heiko@sntech.de>
Message-ID: <201203041905.41146.heiko@sntech.de>

Currently usable are busclk0 and busclk2.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/clock-s3c2416.c  |    1 +
 arch/arm/mach-s3c24xx/clock-s3c2443.c  |    1 +
 arch/arm/mach-s3c24xx/common-s3c2443.c |   15 ++++++++++-----
 3 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index dbc9ab4..8702ecf 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -144,6 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
+	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
 };
 
 void __init s3c2416_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index bce1cd3..bb3231d 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -181,6 +181,7 @@ static struct clk *clks[] __initdata = {
 
 static struct clk_lookup s3c2443_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
+	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi),
 };
 
 void __init s3c2443_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index 4604315..aeeb2be 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -424,11 +424,6 @@ static struct clk init_clocks_off[] = {
 		.enable		= s3c2443_clkcon_enable_p,
 		.ctrlbit	= S3C2443_PCLKCON_IIS,
 	}, {
-		.name		= "hsspi",
-		.parent		= &clk_p,
-		.enable		= s3c2443_clkcon_enable_p,
-		.ctrlbit	= S3C2443_PCLKCON_HSSPI,
-	}, {
 		.name		= "adc",
 		.parent		= &clk_p,
 		.enable		= s3c2443_clkcon_enable_p,
@@ -562,6 +557,14 @@ static struct clk hsmmc1_clk = {
 	.ctrlbit	= S3C2443_HCLKCON_HSMMC,
 };
 
+static struct clk hsspi_clk = {
+	.name		= "spi",
+	.devname	= "s3c64xx-spi.0",
+	.parent		= &clk_p,
+	.enable		= s3c2443_clkcon_enable_p,
+	.ctrlbit	= S3C2443_PCLKCON_HSSPI,
+};
+
 /* EPLLCON compatible enough to get on/off information */
 
 void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
@@ -612,6 +615,7 @@ static struct clk *clks[] __initdata = {
 	&clk_usb_bus,
 	&clk_armdiv,
 	&hsmmc1_clk,
+	&hsspi_clk,
 };
 
 static struct clksrc_clk *clksrcs[] __initdata = {
@@ -629,6 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
 	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
 	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
+	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
 };
 
 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
-- 
1.7.2.3



From heiko at sntech.de  Sun Mar  4 13:06:19 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sun, 4 Mar 2012 19:06:19 +0100
Subject: [PATCH 5/6] ARM: S3C24XX: Add HSSPI setup callback for s3c64xx-spi
 driver
In-Reply-To: <201203041902.38318.heiko@sntech.de>
References: <201203041902.38318.heiko@sntech.de>
Message-ID: <201203041906.20249.heiko@sntech.de>

This lets the s3c64xx-spi driver know the specifics of the controller-
variant and also setups the gpios and the misccr bit.

This setup is valid for all S3C24XX SoCs containing a HSSPI controller
(i.e. S3C2416/2450 and S3C2443)

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/Kconfig     |    5 ++++
 arch/arm/mach-s3c24xx/Makefile    |    1 +
 arch/arm/mach-s3c24xx/setup-spi.c |   39 +++++++++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s3c24xx/setup-spi.c

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 5ebd150..bc6758a 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -484,6 +484,11 @@ config S3C2443_DMA
 	help
 	  Internal config node for S3C2443 DMA support
 
+config S3C2443_SETUP_SPI
+	bool
+	help
+	  Common setup code for SPI GPIO configurations
+
 endif	# CPU_S3C2443 || CPU_S3C2416
 
 if CPU_S3C2443
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 1909d66..0f5d2dd 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -87,3 +87,4 @@ obj-$(CONFIG_MACH_OSIRIS_DVS)		+= mach-osiris-dvs.o
 # device setup
 
 obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
+obj-$(CONFIG_S3C2443_SETUP_SPI)		+= setup-spi.o
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
new file mode 100644
index 0000000..5712c85
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -0,0 +1,39 @@
+/*
+ * HS-SPI device setup for S3C2443/S3C2416
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+	.fifo_lvl_mask	= 0x7f,
+	.rx_lvl_offset	= 13,
+	.tx_st_done	= 21,
+	.high_speed	= 1,
+};
+
+int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
+{
+	/* enable hsspi bit in misccr */
+	s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
+
+	s3c_gpio_cfgall_range(S3C2410_GPE(11), 3,
+			      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+
+	return 0;
+}
+#endif
-- 
1.7.2.3



From heiko at sntech.de  Sun Mar  4 13:09:10 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Sun, 4 Mar 2012 19:09:10 +0100
Subject: [PATCH 6/6] spi/s3c64xx: Allow usage for ARCH_S3C24XX
In-Reply-To: <201203041902.38318.heiko@sntech.de>
References: <201203041902.38318.heiko@sntech.de>
Message-ID: <201203041909.10400.heiko@sntech.de>

Newer SoCs from the S3C24XX line, namely S3C2416/2443/2450 contain
hsspi-controllers compatible with the s3c64xx type.

The previous patches enabled platform support for it, so make the
driver also usable for the S3C24xx architecture.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
As it is part of a series this probably needs an ack from Grant Likely
and should be merged via the samsung tree.

 drivers/spi/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index ac92194..e411364 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -299,7 +299,7 @@ config SPI_S3C24XX_FIQ
 
 config SPI_S3C64XX
 	tristate "Samsung S3C64XX series type SPI"
-	depends on (ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
+	depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
 	select S3C64XX_DMA if ARCH_S3C64XX
 	help
 	  SPI driver for Samsung S3C64XX and newer SoCs.
-- 
1.7.2.3



From michael at walle.cc  Sun Mar  4 13:12:20 2012
From: michael at walle.cc (Michael Walle)
Date: Sun, 4 Mar 2012 19:12:20 +0100
Subject: [PATCH 1/5 v2] ARM: kirkwood: covert orion-spi to fdt.
In-Reply-To: <a3c65ac8146eab1796dec771c1ddfe403d1471a9.1330709314.git.jason@lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <a3c65ac8146eab1796dec771c1ddfe403d1471a9.1330709314.git.jason@lakedaemon.net>
Message-ID: <201203041912.21137.michael@walle.cc>

Am Freitag 02 M?rz 2012, 18:50:18 schrieb Jason Cooper:
> On the Globalscale Dreamplug (Marvell Kirkwood Development Platform),
> 2MB of NOR flash are used to hold the bootloader, bootloader
> environment, and devicetree blob.  It is connected via spi.
> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
> 
> Changes from v1:
> 
>     - used of_match_ptr() as suggested by Grant Likely
> 
>  arch/arm/boot/dts/kirkwood-dreamplug.dts |   34 +++++++++++++++++++++++++
>  arch/arm/mach-kirkwood/board-dt.c        |   40
> ------------------------------ arch/arm/mach-kirkwood/common.c          | 
>  11 ++++++++
>  drivers/spi/spi-orion.c                  |   37
> ++++++++++++++++++++++++--- 4 files changed, 78 insertions(+), 44
> deletions(-)
> 
> diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts
> b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 8a5dff8..bdf2ddc 100644
> --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
> +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
> @@ -22,4 +22,38 @@
>  		interrupts = <33>;
>  		clock-frequency = <200000000>;
>  	};
> +
> +	spi at f1010600 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		compatible = "marvell,orion-spi";
> +		reg = <0xf1010600 0x1ff>;
> +		clock-frequency = <200000000>;
> +
> +		flash at 0 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			compatible = "macronix,mx25l1606e", "jedec-flash";
> +
> +			spi-max-frequency = <50000000>;
> +			reg = <0>;
> +
> +			partition at 0 {
> +				label = "U-Boot";
> +				reg = <0x0 0x100000>;
> +			};
> +
> +			partition at 100000 {
> +				label = "U-Boot Environment";
> +				reg = <0x100000 0x080000>;
> +			};
> +
> +			partition at 180000 {
> +				label = "Flattened Device Tree";
> +				reg = <0x180000 0x080000>;
> +			};
> +		};
> +	};
>  };
> diff --git a/arch/arm/mach-kirkwood/board-dt.c
> b/arch/arm/mach-kirkwood/board-dt.c index fbe6405..4960e63 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -39,42 +39,6 @@ static struct of_device_id kirkwood_dt_match_table[]
> __initdata = { { }
>  };
> 
> -struct mtd_partition dreamplug_partitions[] = {
> -	{
> -		.name	= "u-boot",
> -		.size	= SZ_512K,
> -		.offset = 0,
> -	},
> -	{
> -		.name	= "u-boot env",
> -		.size	= SZ_64K,
> -		.offset = SZ_512K + SZ_512K,
> -	},
> -	{
> -		.name	= "dtb",
> -		.size	= SZ_64K,
> -		.offset = SZ_512K + SZ_512K + SZ_512K,
> -	},
> -};
> -
> -static const struct flash_platform_data dreamplug_spi_slave_data = {
> -	.type		= "mx25l1606e",
> -	.name		= "spi_flash",
> -	.parts		= dreamplug_partitions,
> -	.nr_parts	= ARRAY_SIZE(dreamplug_partitions),
> -};
> -
> -static struct spi_board_info __initdata dreamplug_spi_slave_info[] = {
> -	{
> -		.modalias	= "m25p80",
> -		.platform_data	= &dreamplug_spi_slave_data,
> -		.irq		= -1,
> -		.max_speed_hz	= 50000000,
> -		.bus_num	= 0,
> -		.chip_select	= 0,
> -	},
> -};
> -
>  static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
>  	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
>  };
> @@ -140,10 +104,6 @@ static void __init dreamplug_init(void)
>  	 */
>  	kirkwood_mpp_conf(dreamplug_mpp_config);
> 
> -	spi_register_board_info(dreamplug_spi_slave_info,
> -				ARRAY_SIZE(dreamplug_spi_slave_info));
> -	kirkwood_spi_init();
> -
>  	kirkwood_ehci_init();
>  	kirkwood_ge00_init(&dreamplug_ge00_data);
>  	kirkwood_ge01_init(&dreamplug_ge01_data);
> diff --git a/arch/arm/mach-kirkwood/common.c
> b/arch/arm/mach-kirkwood/common.c index cc15426..357fcde 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -15,6 +15,7 @@
>  #include <linux/ata_platform.h>
>  #include <linux/mtd/nand.h>
>  #include <linux/dma-mapping.h>
> +#include <linux/of.h>
>  #include <net/dsa.h>
>  #include <asm/page.h>
>  #include <asm/timex.h>
> @@ -481,6 +482,9 @@ static int __init kirkwood_clock_gate(void)
>  {
>  	unsigned int curr = readl(CLOCK_GATING_CTRL);
>  	u32 dev, rev;
> +#ifdef CONFIG_OF
> +	struct device_node *dp;
> +#endif
> 
>  	kirkwood_pcie_id(&dev, &rev);
>  	printk(KERN_DEBUG "Gating clock of unused units\n");
> @@ -524,6 +528,13 @@ static int __init kirkwood_clock_gate(void)
>  	} else  /* keep this bit set for devices that don't have PCIe1 */
>  		kirkwood_clk_ctrl |= CGC_PEX1;
> 
> +#ifdef CONFIG_OF
> +	dp = of_find_node_by_path("/");
> +	if (dp && of_device_is_available(of_find_compatible_node(dp, NULL,
> +							  "marvell,orion-
spi")))
> +		kirkwood_clk_ctrl |= CGC_RUNIT;
> +#endif
> +
>  	/* Now gate clock the required units */
>  	writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
>  	printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
> diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
> index 13448c8..acfb240 100644
> --- a/drivers/spi/spi-orion.c
> +++ b/drivers/spi/spi-orion.c
> @@ -18,6 +18,7 @@
>  #include <linux/spi/spi.h>
>  #include <linux/spi/orion_spi.h>
>  #include <linux/module.h>
> +#include <linux/of_device.h>
>  #include <asm/unaligned.h>
> 
>  #define DRIVER_NAME			"orion_spi"
> @@ -45,6 +46,8 @@ struct orion_spi {
>  	void __iomem		*base;
>  	unsigned int		max_speed;
>  	unsigned int		min_speed;
> +	unsigned int		tclk;
> +	unsigned int		clock_fix;
>  	struct orion_spi_info	*spi_info;
>  };
> 
> @@ -104,7 +107,7 @@ static int orion_spi_baudrate_set(struct spi_device
> *spi, unsigned int speed)
> 
>  	orion_spi = spi_master_get_devdata(spi->master);
> 
> -	tclk_hz = orion_spi->spi_info->tclk;
> +	tclk_hz = orion_spi->tclk;
> 
>  	/*
>  	 * the supported rates are: 4,6,8...30
> @@ -360,7 +363,7 @@ static int orion_spi_setup(struct spi_device *spi)
>  	orion_spi = spi_master_get_devdata(spi->master);
> 
>  	/* Fix ac timing if required.   */
> -	if (orion_spi->spi_info->enable_clock_fix)
> +	if (orion_spi->clock_fix)
>  		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
>  				  (1 << 14));
> 
> @@ -474,6 +477,7 @@ static int __init orion_spi_probe(struct
> platform_device *pdev) master->setup = orion_spi_setup;
>  	master->transfer = orion_spi_transfer;
>  	master->num_chipselect = ORION_NUM_CHIPSELECTS;
> +	master->dev.of_node = pdev->dev.of_node;
> 
>  	dev_set_drvdata(&pdev->dev, master);
> 
> @@ -481,8 +485,26 @@ static int __init orion_spi_probe(struct
> platform_device *pdev) spi->master = master;
>  	spi->spi_info = spi_info;
> 
> -	spi->max_speed = DIV_ROUND_UP(spi_info->tclk, 4);
> -	spi->min_speed = DIV_ROUND_UP(spi_info->tclk, 30);
> +	if (spi_info)
> +		spi->tclk = spi_info->tclk;
> +
> +	of_property_read_u32(master->dev.of_node,
> +				"clock-frequency", &spi->tclk);
> +
> +	if (!spi->tclk) {
> +		dev_err(&pdev->dev, "cannot set clock rate\n");
shouldn't you check the return value of of_property_read_u32 instead? and 
report a more meaningful error message, eg no valid clock-frequency property 
in the OF case?

> +		status = -EINVAL;
> +		goto out;
> +	}
> +
> +	spi->max_speed = DIV_ROUND_UP(spi->tclk, 4);
> +	spi->min_speed = DIV_ROUND_UP(spi->tclk, 30);
> +
> +	if (spi_info)
> +		spi->clock_fix = spi_info->enable_clock_fix;
> +
> +	if (of_find_property(master->dev.of_node, "spi-clock-fix", NULL))
> +		spi->clock_fix = 1;
> 
>  	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	if (r == NULL) {
> @@ -541,10 +563,17 @@ static int __exit orion_spi_remove(struct
> platform_device *pdev)
> 
>  MODULE_ALIAS("platform:" DRIVER_NAME);
> 

#ifdef CONFIG_OF
> +static struct of_device_id spi_orion_of_match_table[] __devinitdata = {
> +	{ .compatible = "marvell,orion-spi", },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, spi_orion_of_match_table);
#endif

>  static struct platform_driver orion_spi_driver = {
>  	.driver = {
>  		.name	= DRIVER_NAME,
>  		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(spi_orion_of_match_table),
>  	},
>  	.remove		= __exit_p(orion_spi_remove),
>  };


-- 
Michael


From lost.distance at yahoo.com  Sun Mar  4 13:26:11 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Sun, 4 Mar 2012 18:26:11 +0000 (GMT)
Subject: Status of gpio-pxa driver and dummy clock
In-Reply-To: <87aa3wu0hp.fsf@free.fr>
Message-ID: <1330885571.28077.YahooMailClassic@web29015.mail.ird.yahoo.com>

--- On Sun, 4/3/12, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
> From: Robert Jarzmik <robert.jarzmik at free.fr>
> Subject: Re: Status of gpio-pxa driver and dummy clock
> To: "Haojian Zhuang" <haojian.zhuang at gmail.com>
> Cc: "Arnd Bergmann" <arnd at arndb.de>, linux-arm-kernel at lists.infradead.org
> Date: Sunday, 4 March, 2012, 10:25
> Haojian Zhuang <haojian.zhuang at gmail.com>
> writes:
> 
> > On Sun, Mar 4, 2012 at 5:34 AM, Robert Jarzmik <robert.jarzmik at free.fr>
> wrote:
> >> Hi Haojian,
> >>
> >> As you certainly know, Russell reverted the patch
> "ARM: pxa: add dummy clock for
> >> sa1100-rtc", id
> a55b5adaf403c4d032e0871ad4ee3367782f4db6. As a consequence,
> the
> >> dummy clock for gpio-pxa was removed, causing
> breakage of gpio-pxa driver.
> >>
> >> I wonder if you (or somebody through you) sent an
> update to fix the gpio-pxa by
> >> either fixing gpio-pxa or adding back "pxa-gpio"
> clock. As of today, I see no
> >> fix in 3.3-rc free (Linus tree).
> >>
> >
> > This patch is already merged into arm-soc tree for
> v3.4. I don't have
> > a plan to push it into
> > v3.3.
> 
> Oh, you should push it to 3.3. It's a fix, and the mioa701
> board is broken (and
> probably many others PXA based boards too) because no GPIO
> is available (as
> probe function of pxa-gpio always fail on clk_get()).
> 
> If you don't want to push it to 3.3, I'll have to send a fix
> to Arnd to fix the
> breakage.
> 
> Without it, a PXA based kernel (pxa2xx) will hang in its
> boot phase, on the
> first gpio_get_* or gpio_set_*, which is called by many
> drivers.

There are two further pxa gpio regressions still present in
linux-3.3-rc5:

mfp/gpio regression: pxa_last_gpio used before initialized
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/082624.html

reboot/suspend regression: hx4700 freezes under linux-3.3-rc1
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/082873.html
(2 regressions are reported here; the reboot regression is still present in
linux-3.3-rc5 while the suspend regression has now been fixed).


From olof at lixom.net  Sun Mar  4 13:35:13 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 10:35:13 -0800
Subject: [PATCH v2 1/6] ARM: tegra: do not hide dma declarations
In-Reply-To: <1330721903-8571-1-git-send-email-alan@signal11.us>
References: <1330721903-8571-1-git-send-email-alan@signal11.us>
Message-ID: <20120304183513.GA31064@quad.lixom.net>

On Fri, Mar 02, 2012 at 03:58:23PM -0500, Alan Ott wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The declarations are actually required for the device
> definitions, and are still valid even if the dma controller
> is disabled:
> 
> arch/arm/mach-tegra/devices.c:559:12: error: 'TEGRA_DMA_REQ_SEL_I2S_1' undeclared here (not in a function)
> arch/arm/mach-tegra/devices.c:577:12: error: 'TEGRA_DMA_REQ_SEL_I2S2_1' undeclared here (not in a function)
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Alan Ott <alan at signal11.us>

Thanks, applied to cleanups-and-fixes for 3.4.


-Olof


From olof at lixom.net  Sun Mar  4 13:37:10 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 10:37:10 -0800
Subject: [PATCH v2 2/6] ARM: tegra: select CPU_FREQ_TABLE
In-Reply-To: <1330721908-8633-1-git-send-email-alan@signal11.us>
References: <1330721908-8633-1-git-send-email-alan@signal11.us>
Message-ID: <20120304183710.GB31064@quad.lixom.net>

On Fri, Mar 02, 2012 at 03:58:28PM -0500, Alan Ott wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The tegra cpufreq implementation relies on the cpu_freq_table
> code, so make sure that this is always there when needed.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Alan Ott <alan at signal11.us>

This didn't apply cleanly to the tegra tree (what was it based on?), but
I fixed it up manually and applied to for-3.4/cleanups-and-fixes.


Thanks,

-Olof


From olof at lixom.net  Sun Mar  4 13:37:32 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 10:37:32 -0800
Subject: [PATCH v2 3/6] ARM: tegra: build localtimer support only when
 needed
In-Reply-To: <1330721912-8694-1-git-send-email-alan@signal11.us>
References: <1330721912-8694-1-git-send-email-alan@signal11.us>
Message-ID: <20120304183732.GC31064@quad.lixom.net>

On Fri, Mar 02, 2012 at 03:58:32PM -0500, Alan Ott wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> It is possible to build a tegra kernel without localtimer
> support, so the tegra specific parts should only be built
> when that is indeed enabled.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Alan Ott <alan at signal11.us>

Thanks, applied.

-Olof


From olof at lixom.net  Sun Mar  4 13:38:23 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 10:38:23 -0800
Subject: [PATCH v2 6/6] ARM: tegra: export usb phy symbols
In-Reply-To: <1330721922-8861-1-git-send-email-alan@signal11.us>
References: <1330721922-8861-1-git-send-email-alan@signal11.us>
Message-ID: <20120304183823.GD31064@quad.lixom.net>

On Fri, Mar 02, 2012 at 03:58:42PM -0500, Alan Ott wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The ehci driver can be a module, so the functions provided
> by the tegra platform code used by ehci-tegra need to
> be exported.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Alan Ott <alan at signal11.us>

Thanks, applied.


-Olof


From olof at lixom.net  Sun Mar  4 13:40:15 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 10:40:15 -0800
Subject: [PATCH v2 5/6] ARM: tegra: USB_ULPI needs USB
In-Reply-To: <1330721919-8800-1-git-send-email-alan@signal11.us>
References: <1330721919-8800-1-git-send-email-alan@signal11.us>
Message-ID: <20120304184015.GE31064@quad.lixom.net>

On Fri, Mar 02, 2012 at 03:58:39PM -0500, Alan Ott wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The USB_ULPI driver is selected by tegra, but can only be
> built if at least one of USB or USB_GADGET is enabled.
> The kernel fails to link if both are off.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Alan Ott <alan at signal11.us>
> ---
>  arch/arm/mach-tegra/Kconfig |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> index 60f3e4b..9bb8a37 100644
> --- a/arch/arm/mach-tegra/Kconfig
> +++ b/arch/arm/mach-tegra/Kconfig
> @@ -10,6 +10,7 @@ config ARCH_TEGRA_2x_SOC
>  	select USB_ARCH_HAS_EHCI if USB_SUPPORT
>  	select USB_ULPI if USB_SUPPORT
>  	select USB_ULPI_VIEWPORT if USB_SUPPORT
> +	select USB_GADGET if USB_SUPPORT && !USB
>  	select CPU_FREQ_TABLE if CPU_FREQ
>  	help
>  	  Support for NVIDIA Tegra AP20 and T20 processors, based on the

This is another patch that needs the same change for T30.


-Olof


From olof at lixom.net  Sun Mar  4 13:41:34 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 10:41:34 -0800
Subject: [PATCH] ARM: tegra: match SoC name not board name in DT board
 files
In-Reply-To: <1330392376-7884-1-git-send-email-swarren@nvidia.com>
References: <1330392376-7884-1-git-send-email-swarren@nvidia.com>
Message-ID: <20120304184134.GF31064@quad.lixom.net>

On Mon, Feb 27, 2012 at 06:26:16PM -0700, Stephen Warren wrote:
> board-dt-tegra*.c should support any board using Tegra when booted using
> device tree. Instead of explicitly listing all the supported boards,
> which requires a kernel change for each new board, list the supported SoC
> model instead.
> 
> Note that the board files do currently have explicit support for setting
> up each board's pinmux. However, it's fairly likely that at least the
> basic devices on any new board will work just fine as set up by the boot-
> loader, and the pinmux data should be moving into device tree soon anyway.
> 
> Signed-off-by: Stephen Warren <swarren at nvidia.com>

Thanks, applied.


-Olof


From olof at lixom.net  Sun Mar  4 13:42:04 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 10:42:04 -0800
Subject: [PATCH] ARM: dt: Add ARM PMU to tegra*.dtsi
In-Reply-To: <1330392396-7919-1-git-send-email-swarren@nvidia.com>
References: <1330392396-7919-1-git-send-email-swarren@nvidia.com>
Message-ID: <20120304184204.GG31064@quad.lixom.net>

On Mon, Feb 27, 2012 at 06:26:36PM -0700, Stephen Warren wrote:
> This enables HW performance measurements, and usage of the "perf" tool.
> 
> Signed-off-by: Stephen Warren <swarren at nvidia.com>

Thanks, applied.


-Olof


From olof at lixom.net  Sun Mar  4 13:47:53 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 10:47:53 -0800
Subject: [PATCH] ARM: dt: Explicitly configure all serial ports on Tegra
 Cardhu
In-Reply-To: <1328210659-16869-1-git-send-email-swarren@nvidia.com>
References: <1328210659-16869-1-git-send-email-swarren@nvidia.com>
Message-ID: <20120304184753.GA32119@quad.lixom.net>

On Thu, Feb 02, 2012 at 12:24:19PM -0700, Stephen Warren wrote:
> The ports are used as follows:
> UART1/A: Routed to debug dongle
> UART2/B: GPS
> UART3/C: Bluetooth
> UART4/D: Routed to debug dongle
> UART5/E: Not connected
> 
> The debug dongle has jumpers to connect either UART1/A or UART4/D to
> the DB-9 connector. UART1/A is typically used on Cardhu, and is the option
> we assume here.
> 
> For now, only enable UART1/A, and explicitly disable all other ports.
> 
> The explicit disable prevents the message "of_serial 70006040.serial:
> no clock-frequency property set" being printed during boot.
> 
> Enabling the other ports requires their clocks to be enabled, or accesses
> to the registers will hang. At present, this requires adding entries into
> board-dt-tegra30.c's tegra_dt_clk_init_table[]. Lets punt on that and wait
> for the common clock bindings to set this all up, although that will also
> requiring adding clock support to 8250.c.
> 
> While we're at it, fix board-dt-tegra30.c to enable the correct clock for
> the debug UART. We got away with this before, because the bootloader already
> enabled it.
> 
> Signed-off-by: Stephen Warren <swarren at nvidia.com>

Thanks, applied to for-3.4/t30-smp (since it depends on other changes there).


-Olof


From olof at lixom.net  Sun Mar  4 13:51:55 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 10:51:55 -0800
Subject: [PATCH] ARM: tegra: Enable CPUIdle on Tegra20
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BD8BC9AB@HQMAIL01.nvidia.com>
References: <1330014056-26125-1-git-send-email-pdeschrijver@nvidia.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BD8BC9AB@HQMAIL01.nvidia.com>
Message-ID: <20120304185155.GA363@quad.lixom.net>

On Thu, Feb 23, 2012 at 09:25:34AM -0800, Stephen Warren wrote:
> Peter De Schrijver wrote at Thursday, February 23, 2012 9:21 AM:
> > As the LP3 code also works for Tegra20, we can enable cpuidle for Tegra20.
> > 
> > Signed-off-by: Peter De Schrijver <pdeschrijver at nvidia.com>
> 
> Acked-by: Stephen Warren <swarren at nvidia.com>
> Tested-by: Stephen Warren <swarren at nvidia.com>
> 
> Note that the commit which added this line appears to have been made in
> Nicolas's idle branch, which was merged into Russell's for-armsoc branch.
> This presumably impacts the path through which this fix should get merged.
> 
> (hence leaving the patch below for Nicolas/Russell to see)

Thanks, applied.


-Olof


From olof at lixom.net  Sun Mar  4 13:59:01 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 10:59:01 -0800
Subject: What's in tegra.git for 3.4
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BD8BCF6A@HQMAIL01.nvidia.com>
References: <CAOesGMjnWPgSa44hgRu+d0jrQLm9KuOcuufg9V8fYZ8TytsbPw@mail.gmail.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BD8BCF6A@HQMAIL01.nvidia.com>
Message-ID: <20120304185901.GI31064@quad.lixom.net>

On Mon, Feb 27, 2012 at 09:41:56AM -0800, Stephen Warren wrote:
> Olof Johansson wrote at Sunday, February 26, 2012 3:51 PM:
> > We're closing in on when things need to be in the sub-arch trees in
> > time to get merged for the next merge window. The shortlog below is
> > what i have queued up today.
> 
> The following are in patchwork and should probably be picked up:

Btw, patchwork is down, so I had to guess which patches were being referred to.
While it's convenient to have the links, also having the patch subject would be
good. :-)


> http://patchwork.ozlabs.org/patch/139197/
> http://patchwork.ozlabs.org/patch/142663/ (should be merged elsewhere?)

Applied x2.

> 
> Are these still relevant?
> http://patchwork.ozlabs.org/patch/132936/

I'll revisit this one later -- one of the drivers is buggy and causes problems
on boot.

> http://patchwork.ozlabs.org/patch/132919/

This is already in mainline

> Should you ping Dmitry on?
> http://patchwork.ozlabs.org/patch/134093/

Pinged repeatedly, no answers.

> I need to ping Ben on:
> http://patchwork.ozlabs.org/patch/139494/

Yeah, we can take it through tegra if needed, we've done it in the past.


-Olof


From olof at lixom.net  Sun Mar  4 14:00:26 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 11:00:26 -0800
Subject: [PATCH v2 1/6] ARM: tegra: do not hide dma declarations
In-Reply-To: <20120304183513.GA31064@quad.lixom.net>
References: <1330721903-8571-1-git-send-email-alan@signal11.us>
 <20120304183513.GA31064@quad.lixom.net>
Message-ID: <CAOesGMg4nBjUGb_KzZk1_d2FvCmbW2kwFqh9q_9S8TQqgYO8hw@mail.gmail.com>

On Sun, Mar 4, 2012 at 10:35 AM, Olof Johansson <olof at lixom.net> wrote:
> On Fri, Mar 02, 2012 at 03:58:23PM -0500, Alan Ott wrote:
>> From: Arnd Bergmann <arnd at arndb.de>
>>
>> The declarations are actually required for the device
>> definitions, and are still valid even if the dma controller
>> is disabled:
>>
>> arch/arm/mach-tegra/devices.c:559:12: error: 'TEGRA_DMA_REQ_SEL_I2S_1' undeclared here (not in a function)
>> arch/arm/mach-tegra/devices.c:577:12: error: 'TEGRA_DMA_REQ_SEL_I2S2_1' undeclared here (not in a function)
>>
>> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
>> Signed-off-by: Alan Ott <alan at signal11.us>
>
> Thanks, applied to cleanups-and-fixes for 3.4.

Oh, a corresponding fix for this is already in mainline, so I dropped
it again (noticed due to conflicts).


-Olof


From s.hauer at pengutronix.de  Sun Mar  4 14:00:31 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sun, 4 Mar 2012 20:00:31 +0100
Subject: [PATCH 04/20] ARM: imx: convert audmux to a platform driver
In-Reply-To: <1330788001-10158-5-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-5-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120304190031.GT3852@pengutronix.de>

On Sat, Mar 03, 2012 at 11:19:45PM +0800, Shawn Guo wrote:
> From: Richard Zhao <richard.zhao at linaro.org>
> 
> It coverts audmux to a platform driver, so that it can be moved into
> sound/soc/imx and adopt device tree support later.
> 
> Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  arch/arm/mach-imx/eukrea_mbimx27-baseboard.c   |    7 ++
>  arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c |    7 ++
>  arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c |    7 ++
>  arch/arm/mach-imx/mach-imx27_visstrim_m10.c    |    7 ++
>  arch/arm/mach-imx/mach-mx31ads.c               |    6 +
>  arch/arm/mach-imx/mach-pca100.c                |    7 ++
>  arch/arm/mach-imx/mach-pcm043.c                |    7 ++
>  arch/arm/plat-mxc/audmux.c                     |  127 +++++++++++++++++-------
>  8 files changed, 140 insertions(+), 35 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
> index 5f2f91d..11cd0a0 100644
> --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
> +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
> @@ -294,6 +294,10 @@ struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = {
>  	.flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
>  };
>  
> +static const struct resource audmux_res[] __initconst = {
> +	DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K),
> +};
> +
>  /*
>   * system init for baseboard usage. Will be called by cpuimx27 init.
>   *
> @@ -317,6 +321,9 @@ void __init eukrea_mbimx27_baseboard_init(void)
>  	i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
>  				ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
>  
> +	/* imx27 has the imx21 version audmux */
> +	imx_add_platform_device("imx21-audmux", 0, audmux_res,
> +				ARRAY_SIZE(audmux_res), NULL, 0);

The audmux is a device completely internal to the i.MX and is registered
without platform_data. I think we should do the device registration
somewhere in the SoC specific code and not do it in each board.
Also we now have platform_device_register_simple, we shouldn't use the
imx_ variant in new code.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From alan at signal11.us  Sun Mar  4 14:46:28 2012
From: alan at signal11.us (Alan Ott)
Date: Sun, 04 Mar 2012 14:46:28 -0500
Subject: [PATCH v2 5/6] ARM: tegra: USB_ULPI needs USB
In-Reply-To: <20120304184015.GE31064@quad.lixom.net>
References: <1330721919-8800-1-git-send-email-alan@signal11.us>
 <20120304184015.GE31064@quad.lixom.net>
Message-ID: <4F53C694.5060308@signal11.us>

On 3/4/12 1:40 PM, Olof Johansson wrote:
> On Fri, Mar 02, 2012 at 03:58:39PM -0500, Alan Ott wrote:
>> From: Arnd Bergmann<arnd at arndb.de>
>>
>> The USB_ULPI driver is selected by tegra, but can only be
>> built if at least one of USB or USB_GADGET is enabled.
>> The kernel fails to link if both are off.
>>
>> Signed-off-by: Arnd Bergmann<arnd at arndb.de>
>> Signed-off-by: Alan Ott<alan at signal11.us>
>> ---
> This is another patch that needs the same change for T30.
>
>
> -Olof

It is in v3. It looks like you took (or at least replied to) v2 for all 
these.

Alan.


From alan at signal11.us  Sun Mar  4 14:47:31 2012
From: alan at signal11.us (Alan Ott)
Date: Sun, 04 Mar 2012 14:47:31 -0500
Subject: [PATCH v2 2/6] ARM: tegra: select CPU_FREQ_TABLE
In-Reply-To: <20120304183710.GB31064@quad.lixom.net>
References: <1330721908-8633-1-git-send-email-alan@signal11.us>
 <20120304183710.GB31064@quad.lixom.net>
Message-ID: <4F53C6D3.2060404@signal11.us>

On 3/4/12 1:37 PM, Olof Johansson wrote:
> On Fri, Mar 02, 2012 at 03:58:28PM -0500, Alan Ott wrote:
>> From: Arnd Bergmann<arnd at arndb.de>
>>
>> The tegra cpufreq implementation relies on the cpu_freq_table
>> code, so make sure that this is always there when needed.
>>
>> Signed-off-by: Arnd Bergmann<arnd at arndb.de>
>> Signed-off-by: Alan Ott<alan at signal11.us>
>
> This didn't apply cleanly to the tegra tree (what was it based on?), but
> I fixed it up manually and applied to for-3.4/cleanups-and-fixes.
>

These were based on mainline.

Alan.


From olof at lixom.net  Sun Mar  4 15:13:56 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun,  4 Mar 2012 12:13:56 -0800
Subject: [GIT PULL 0/6] Tegra branches for 3.4
Message-ID: <1330892042-32065-1-git-send-email-olof@lixom.net>

Hi Arnd,

Below are the 6 pull requests for Tegra platforms for 3.4. This is also
likely my last merge request for tegra material (besides possibly some
stray patches between now and the merge window), since I am handing off
main maintainership to Stephen Warren for the next merge window.

Each branch is documented in the tag (they are all tag pull requests), as
well as in the emails below. Nothing too controversial.

There are a handful of trivial merge conflicts between the branches,
mostly to the Makefile due to context chances. I also had a local
issue where git auto-resolved the merge of the T30 SMP branch into
my for-next branch, and did NOT remove the mach/system.h include at
arch/arm/mach-tegra/common.c. This results in a build break since it
has been removed in rmk/for-armsoc. So just a heads up in case you see
the same thing.


-Olof




From arnd at arndb.de  Sun Mar  4 15:29:59 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 4 Mar 2012 20:29:59 +0000
Subject: [PATCH 1/5 v2] ARM: kirkwood: covert orion-spi to fdt.
In-Reply-To: <201203041912.21137.michael@walle.cc>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <a3c65ac8146eab1796dec771c1ddfe403d1471a9.1330709314.git.jason@lakedaemon.net>
 <201203041912.21137.michael@walle.cc>
Message-ID: <201203042030.00064.arnd@arndb.de>

On Sunday 04 March 2012, Michael Walle wrote:
> > @@ -481,8 +485,26 @@ static int __init orion_spi_probe(struct
> > platform_device *pdev) spi->master = master;
> >       spi->spi_info = spi_info;
> > 
> > -     spi->max_speed = DIV_ROUND_UP(spi_info->tclk, 4);
> > -     spi->min_speed = DIV_ROUND_UP(spi_info->tclk, 30);
> > +     if (spi_info)
> > +             spi->tclk = spi_info->tclk;
> > +
> > +     of_property_read_u32(master->dev.of_node,
> > +                             "clock-frequency", &spi->tclk);
> > +
> > +     if (!spi->tclk) {
> > +             dev_err(&pdev->dev, "cannot set clock rate\n");
> shouldn't you check the return value of of_property_read_u32 instead? and 
> report a more meaningful error message, eg no valid clock-frequency property 
> in the OF case?

I suggested this version, because it keeps the code very simple. Checking
the return value would of course be correct, but I don't think we
need any extra information here: there are only a few ways how this can
go wrong and it will be pretty obvious from the device tree when you
see the message.

	Arnd


From andrew at lunn.ch  Sun Mar  4 15:33:59 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sun, 4 Mar 2012 21:33:59 +0100
Subject: [PATCH] clk: Fix compile errors in DEFINE_CLK_GATE
In-Reply-To: <1330763341-3437-5-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
Message-ID: <20120304203359.GE11546@lunn.ch>

>From 71e9a676b2b2f0dc2bb0cc395e8325cf38f4808b Mon Sep 17 00:00:00 2001
From: Andrew Lunn <andrew at lunn.ch>
Date: Sun, 4 Mar 2012 16:31:14 +0100
Subject: [PATCH] [clk] Fix compile errors in DEFINE_CLK_GATE()

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
---
 include/linux/clk-private.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index d06e6fb..9d5c4b1 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -95,7 +95,7 @@ extern struct clk_ops clk_gate_ops;
 		},						\
 		.reg = _reg,					\
 		.bit_idx = _bit_idx,				\
-		.flags = _gate_flags				\
+		.flags = _gate_flags,				\
 		.lock = _lock,					\
 	};							\
 	static struct clk _name = {				\
@@ -104,7 +104,7 @@ extern struct clk_ops clk_gate_ops;
 		.hw = &_name##_hw.hw,				\
 		.parent_names = _name##_parent_names,		\
 		.num_parents =					\
-			ARRAY_SIZE(_name##parent_names),	\
+			ARRAY_SIZE(_name##_parent_names),	\
 		.parents = _name##_parents,			\
 		.flags = _flags,				\
 	};
-- 
1.7.2.5



From arnd at arndb.de  Sun Mar  4 15:39:14 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 4 Mar 2012 20:39:14 +0000
Subject: [PATCH v3 07/10] arm/tegra: Add PWFM controller device tree
 probing
In-Reply-To: <20120303225404.GC6661@avionic-0098.mockup.avionic-design.de>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E67@HQMAIL01.nvidia.com>
 <20120303225404.GC6661@avionic-0098.mockup.avionic-design.de>
Message-ID: <201203042039.14848.arnd@arndb.de>

On Saturday 03 March 2012, Thierry Reding wrote:
> Not enough information to check signature validity.  Show Details
>   * Stephen Warren wrote:
> > Thierry Reding wrote at Wednesday, February 22, 2012 8:17 AM:
> > > Add auxdata to instantiate a device tree for the PWFM controller and
> > > include a corresponding node in the device tree.
> > 
> > > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> > 
> > > +   pwm: pwm at 7000a000 {
> > > +           compatible = "nvidia,tegra20-pwm";
> > > +           reg = <0x7000a000 0x100>;
> > > +           #pwm-cells = <2>;
> > > +   };
> > 
> > The compatible value probably should list both Tegra30 and Tegra20, so
> > we can know exactly which HW is present, just in case we need to turn
> > on some bug-fix only for one of the variants:
> > 
> >     compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
> 
> I'm confused. If I know exactly that the hardware is Tegra30 (which it
> definitely should be if I include tegra30.dtsi), then why list "tegra20-pwm"
> as compatible?
> 
> Or did you mean to list tegra30-pwm as compatible value in the PWM driver?

We generally list the oldest version of the device that a specific version
is compatible to, in order to use the same driver unmodified.

E.g. an ns16550a serial port would list both ns16550a and i8250 in its
compatible fields so it works with operating systems that only know about
i8250.

It's not actually all that useful when you add device tree support for
two versions of the same device at the same time, but I think that
it's good style anyway, in particular when you consider other users of
the device tree data besides the Linux kernel.

	Arnd


From olof at lixom.net  Sun Mar  4 15:41:51 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 12:41:51 -0800
Subject: [GIT PULL 0/6] Tegra branches for 3.4
In-Reply-To: <1330892042-32065-1-git-send-email-olof@lixom.net>
References: <1330892042-32065-1-git-send-email-olof@lixom.net>
Message-ID: <CAOesGMgahK_wkM1PGb55D1gEzbYfJVQKO_XSqMPbw5wTP09Fag@mail.gmail.com>

On Sun, Mar 4, 2012 at 12:13 PM, Olof Johansson <olof at lixom.net> wrote:
> Hi Arnd,
>
> Below are the 6 pull requests for Tegra platforms for 3.4. This is also
> likely my last merge request for tegra material (besides possibly some
> stray patches between now and the merge window), since I am handing off
> main maintainership to Stephen Warren for the next merge window.
>
> Each branch is documented in the tag (they are all tag pull requests), as
> well as in the emails below. Nothing too controversial.

Oh, I did forget to mention one added dependency: The soc-drivers
branch has a dependency on Grant's irq_domain branch -- not for
merging but for building.


-Olof


From arnd at arndb.de  Sun Mar  4 16:27:52 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 4 Mar 2012 21:27:52 +0000
Subject: [GIT PULL 0/6] Tegra branches for 3.4
In-Reply-To: <1330892042-32065-1-git-send-email-olof@lixom.net>
References: <1330892042-32065-1-git-send-email-olof@lixom.net>
Message-ID: <201203042127.53017.arnd@arndb.de>

On Sunday 04 March 2012, Olof Johansson wrote:
> Hi Arnd,
> 
> Below are the 6 pull requests for Tegra platforms for 3.4. This is also
> likely my last merge request for tegra material (besides possibly some
> stray patches between now and the merge window), since I am handing off
> main maintainership to Stephen Warren for the next merge window.
> 
> Each branch is documented in the tag (they are all tag pull requests), as
> well as in the emails below. Nothing too controversial.
> 
> There are a handful of trivial merge conflicts between the branches,
> mostly to the Makefile due to context chances. I also had a local
> issue where git auto-resolved the merge of the T30 SMP branch into
> my for-next branch, and did NOT remove the mach/system.h include at
> arch/arm/mach-tegra/common.c. This results in a build break since it
> has been removed in rmk/for-armsoc. So just a heads up in case you see
> the same thing.

Hi Olof,

I've pulled them all into the respective branches. I'll send out a
status of all the stuff (and missing stuff) in arm-soc.git tomorrow
and then hand back over to you for a while until you need to shift
your own focus again.

	Arnd


From jason at lakedaemon.net  Sun Mar  4 17:27:10 2012
From: jason at lakedaemon.net (Jason)
Date: Sun, 4 Mar 2012 17:27:10 -0500
Subject: [PATCH 3/4] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <201203041648.17428.arnd@arndb.de>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <2c985a303f3b9b0cfcead25634b7e1db68d34ee3.1330625878.git.jason@lakedaemon.net>
 <201203041559.23810.michael@walle.cc>
 <201203041648.17428.arnd@arndb.de>
Message-ID: <20120304222710.GT11986@titan.lakedaemon.net>

On Sun, Mar 04, 2012 at 04:48:17PM +0000, Arnd Bergmann wrote:
> On Sunday 04 March 2012, Michael Walle wrote:
> > in my older patch series i flagged all converted devices with two 
> > compatibility names. Eg:
> > 
> >        { .compatible = "marvell,orion5x-rtc", },
> >        { .compatible = "marvell,kirkwood-rtc", },
> > 
> > IMHO marvell,rtc is i little too general, i guess marvell won't have only one 
> > rtc ;)
> > 
> > Other opinions?
> 
> Being specific is certainly good, and it may also be a good idea to
> list the first one it's compatible with in the device tree source.
> 
> So the device tree for a 88F6281 soc could list
> 
> 	compatible = "marvell,88f6281-rtc", "marvell,kirkwood-rtc", "marvell,orion-rtc";

I'll go ahead and make this style of change throughout.  I assume
"marvell,88f6281-rtc" would only be for SoC internal devices?  eg, the spi
driver wouldn't follow that convention.  I'll see if I can dig up a part
number on it.

> This would give the device driver the option which one to bind to. Anything that
> has an rtc compatible with the one in orion should list that one, so that the driver
> only has to list that one if they are truely identical, but if the driver has to
> get modified later to know the difference between orion and kirkwood rtcs, it can
> check the more specific value.
> 
> 	Arnd

thx,

Jason.


From B04825 at freescale.com  Sun Mar  4 18:13:09 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Sun, 4 Mar 2012 23:13:09 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F53F704.8080703@freescale.com>

Shawn Guo wrote:
> +#ifdef PPC
> +#define read_ssi(addr)		in_be32(addr)
> +#define write_ssi(val, addr)	out_be32(addr, val)
> +#elif defined ARM
> +#define read_ssi(addr)		readl(addr)
> +#define write_ssi(val, addr)	writel(val, addr)
> +#endif

Can you also add an ARM version of clrsetbits_be32()?  Something like this:

#ifdef PPC
#define read_ssi(addr)		in_be32(addr)
#define write_ssi(val, addr)	out_be32(addr, val)
#define write_ssi_mask(addr, clear, set)	clrsetbits_be32(addr, clear, set)
#elif defined ARM
#define read_ssi(addr)		readl(addr)
#define write_ssi(val, addr)	writel(val, addr)
#define write_ssi_mask(addr, clear, set) \
	{ u32 __val; \
	val = readl(&ssi->scr); \
	val = (val & ~(clear) | (set); \
	writel(val, addr)
#endif

-- 
Timur Tabi
Linux kernel developer at Freescale


From michael at walle.cc  Sun Mar  4 18:22:11 2012
From: michael at walle.cc (Michael Walle)
Date: Mon, 5 Mar 2012 00:22:11 +0100
Subject: [PATCH 3/4] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <20120304222710.GT11986@titan.lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203041648.17428.arnd@arndb.de>
 <20120304222710.GT11986@titan.lakedaemon.net>
Message-ID: <201203050022.12085.michael@walle.cc>

Am Sonntag 04 M?rz 2012, 23:27:10 schrieb Jason:
> On Sun, Mar 04, 2012 at 04:48:17PM +0000, Arnd Bergmann wrote:
> > On Sunday 04 March 2012, Michael Walle wrote:
> > > in my older patch series i flagged all converted devices with two
> > > 
> > > compatibility names. Eg:
> > >        { .compatible = "marvell,orion5x-rtc", },
> > >        { .compatible = "marvell,kirkwood-rtc", },
> > > 
> > > IMHO marvell,rtc is i little too general, i guess marvell won't have
> > > only one rtc ;)
> > > 
> > > Other opinions?
> > 
> > Being specific is certainly good, and it may also be a good idea to
> > list the first one it's compatible with in the device tree source.
> > 
> > So the device tree for a 88F6281 soc could list
> > 
> > 	compatible = "marvell,88f6281-rtc", "marvell,kirkwood-rtc",
> > 	"marvell,orion-rtc";
> 
> I'll go ahead and make this style of change throughout.  I assume
> "marvell,88f6281-rtc" would only be for SoC internal devices?  eg, the spi
> driver wouldn't follow that convention.  I'll see if I can dig up a part
> number on it.

following the filename spi-orion.c i guess it should use 'marvell,orion-spi'.

-- 
Michael


From linux at arm.linux.org.uk  Sun Mar  4 18:28:17 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 4 Mar 2012 23:28:17 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <4F53F704.8080703@freescale.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
Message-ID: <20120304232817.GA13516@n2100.arm.linux.org.uk>

On Sun, Mar 04, 2012 at 11:13:09PM +0000, Tabi Timur-B04825 wrote:
> Shawn Guo wrote:
> > +#ifdef PPC
> > +#define read_ssi(addr)		in_be32(addr)
> > +#define write_ssi(val, addr)	out_be32(addr, val)
> > +#elif defined ARM
> > +#define read_ssi(addr)		readl(addr)
> > +#define write_ssi(val, addr)	writel(val, addr)
> > +#endif
> 
> Can you also add an ARM version of clrsetbits_be32()?  Something like this:
> 
> #ifdef PPC
> #define read_ssi(addr)		in_be32(addr)
> #define write_ssi(val, addr)	out_be32(addr, val)
> #define write_ssi_mask(addr, clear, set)	clrsetbits_be32(addr, clear, set)
> #elif defined ARM
> #define read_ssi(addr)		readl(addr)
> #define write_ssi(val, addr)	writel(val, addr)
> #define write_ssi_mask(addr, clear, set) \
> 	{ u32 __val; \
> 	val = readl(&ssi->scr); \
> 	val = (val & ~(clear) | (set); \
> 	writel(val, addr)
> #endif

Is the SCR shared between capture and playback?  In that case, what
makes this read-modify-write thread safe?


From B04825 at freescale.com  Sun Mar  4 18:32:50 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Sun, 4 Mar 2012 23:32:50 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <20120304232817.GA13516@n2100.arm.linux.org.uk>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
Message-ID: <4F53FBA1.8090200@freescale.com>

Russell King - ARM Linux wrote:
> Is the SCR shared between capture and playback?  In that case, what
> makes this read-modify-write thread safe?

What's "SCR"?

It's not thread-safe on PPC, but then neither is the entire function.  You 
can't have two threads attempt to initialize the hardware at the same 
time.  The macro does not attempt to be atomic, just convenient.

-- 
Timur Tabi
Linux kernel developer at Freescale


From B04825 at freescale.com  Sun Mar  4 18:34:31 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Sun, 4 Mar 2012 23:34:31 +0000
Subject: [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F53FC06.1020805@freescale.com>

Shawn Guo wrote:
> +MODULE_AUTHOR("Freescale Semiconductor, Inc.");

I encourage developers to put their own name in the MODULE_AUTHOR macro.

-- 
Timur Tabi
Linux kernel developer at Freescale


From linux at arm.linux.org.uk  Sun Mar  4 19:04:11 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 5 Mar 2012 00:04:11 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <4F53FBA1.8090200@freescale.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
Message-ID: <20120305000411.GL7363@n2100.arm.linux.org.uk>

On Sun, Mar 04, 2012 at 11:32:50PM +0000, Tabi Timur-B04825 wrote:
> Russell King - ARM Linux wrote:
> > Is the SCR shared between capture and playback?  In that case, what
> > makes this read-modify-write thread safe?
> 
> What's "SCR"?

I assumed you knew the code you were commenting on.

                clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);

The register these functions seem to be used on appears to be called
'SCR'.

> It's not thread-safe on PPC, but then neither is the entire function.  You 
> can't have two threads attempt to initialize the hardware at the same 
> time.

Why do you say "can't" - what prevents it?  If nothing, then this stuff
is buggy when preempt is enabled, or you're running on SMP.


From mturquette at ti.com  Sun Mar  4 19:12:21 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Sun, 4 Mar 2012 16:12:21 -0800
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120304115201.GB26882@pengutronix.de>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
Message-ID: <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>

On Sun, Mar 4, 2012 at 3:52 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Sat, Mar 03, 2012 at 09:14:43AM -0800, Turquette, Mike wrote:
>> On Sat, Mar 3, 2012 at 5:31 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>> > On Sat, Mar 03, 2012 at 12:29:00AM -0800, Mike Turquette wrote:
>> >> The common clock framework defines a common struct clk useful across
>> >> most platforms as well as an implementation of the clk api that drivers
>> >> can use safely for managing clocks.
>> >>
>> >> The net result is consolidation of many different struct clk definitions
>> >> and platform-specific clock framework implementations.
>> >>
>> >> This patch introduces the common struct clk, struct clk_ops and an
>> >> implementation of the well-known clock api in include/clk/clk.h.
>> >> Platforms may define their own hardware-specific clock structure and
>> >> their own clock operation callbacks, so long as it wraps an instance of
>> >> struct clk_hw.
>> >>
>> >> See Documentation/clk.txt for more details.
>> >>
>> >> This patch is based on the work of Jeremy Kerr, which in turn was based
>> >> on the work of Ben Herrenschmidt.
>> >>
>> >> +
>> >> +/**
>> >> + * struct clk_hw - handle for traversing from a struct clk to its corresponding
>> >> + * hardware-specific structure. ?struct clk_hw should be declared within struct
>> >> + * clk_foo and then referenced by the struct clk instance that uses struct
>> >> + * clk_foo's clk_ops
>> >> + *
>> >> + * clk: pointer to the struct clk instance that points back to this struct
>> >> + * clk_hw instance
>> >> + */
>> >> +struct clk_hw {
>> >> + ? ? struct clk *clk;
>> >> +};
>> >
>> > The reason for doing this is that struct clk should be an opaque cookie
>> > for both drivers and implementers of clocks. I recently had the idea whether
>> > the roles of these two structs could be swapped. So instead of the above we
>> > could do:
>> >
>> > struct clk {
>> > ? ? ? ?struct clk_hw *hw;
>> > }
>>
>> Firstly, struct clk is an opaque cookie for both drivers and
>> implementers of clocks with this patchset.
>>
>> Secondly, struct clk does indeed have a pointer to struct clk_hw.
>> Refer to include/linux/clk-private.h in this patch.
>>
>> The reference is cyclical. ?A reference to struct clk can navigate to
>> struct clk_foo via container_of (usually something like "#define
>> to_clk_foo(_hw) container_of(_hw, struct clk_foo, hw)" where struct
>> clk's pointer to it's .hw member is passed into one of the struct
>> clk_ops callbacks.
>>
>> Likewise if struct clk_foo needs the struct clk ptr for any reason
>> then it can get it from foo->hw->clk.
>>
>> I believe this patch already does what you suggest, but I might be
>> missing your point.
>
> In include/linux/clk-private.h you expose struct clk outside the core.
> This has to be done to make static initializers possible. There is a big
> warning in this file that it must not be included from files implementing
> struct clk_ops. You can simply avoid this warning by declaring struct clk
> with only a single member:
>
> include/linux/clk.h:
>
> struct clk {
> ? ? ? ?struct clk_internal *internal;
> };
>
> This way everybody knows struct clk (thus can embed it in their static
> initializers), but doesn't know anything about the internal members. Now
> in drivers/clk/clk.c you declare struct clk_internal exactly like struct
> clk was declared before:
>
> struct clk_internal {
> ? ? ? ?const char ? ? ? ? ? ? ?*name;
> ? ? ? ?const struct clk_ops ? ?*ops;
> ? ? ? ?struct clk_hw ? ? ? ? ? *hw;
> ? ? ? ?struct clk ? ? ? ? ? ? ?*parent;
> ? ? ? ?char ? ? ? ? ? ? ? ? ? ?**parent_names;
> ? ? ? ?struct clk ? ? ? ? ? ? ?**parents;
> ? ? ? ?u8 ? ? ? ? ? ? ? ? ? ? ?num_parents;
> ? ? ? ?unsigned long ? ? ? ? ? rate;
> ? ? ? ?unsigned long ? ? ? ? ? flags;
> ? ? ? ?unsigned int ? ? ? ? ? ?enable_count;
> ? ? ? ?unsigned int ? ? ? ? ? ?prepare_count;
> ? ? ? ?struct hlist_head ? ? ? children;
> ? ? ? ?struct hlist_node ? ? ? child_node;
> ? ? ? ?unsigned int ? ? ? ? ? ?notifier_count;
> #ifdef CONFIG_COMMON_CLK_DEBUG
> ? ? ? ?struct dentry ? ? ? ? ? *dentry;
> #endif
> };
>
> An instance of struct clk_internal will be allocated in
> __clk_init/clk_register. Now the private data stays completely inside
> the core and noone can abuse it.

Hi Sascha,

I see the disconnect here.  For OMAP (and possibly other platforms) at
least some clock data is necessary during early boot, before the
regular allocation methods are available (timers for instance).  Due
to this my idea of static initialization was to take care of
everything that would normally require an allocator, which includes
the internals of struct clk; thus exposing struct clk is useful here
as you can still use the clock framework during very early boot.  Your
method above doesn't satisfy this requirement.  I'm not sure what the
purpose would be of statically allocating your version of struct clk,
which will ultimately need to allocate memory for the clock internals
anyways.  Can you elaborate the benefit of this approach over just
using the clk_foo_register functions?

Note that struct clk is still declared in clk.h (and clk-provider.h),
so platforms that have struct clk *clk declarations won't have a
problem.

Thanks much,
Mike

>
> With this __clk_init could be something like:
>
> struct clk_initializer {
> ? ? ? ?const char ? ? ? ? ? ? ?*name;
> ? ? ? ?const struct clk_ops ? ?*ops;
> ? ? ? ?char ? ? ? ? ? ? ? ? ? ?**parent_names;
> ? ? ? ?u8 ? ? ? ? ? ? ? ? ? ? ?num_parents;
> ? ? ? ?unsigned long ? ? ? ? ? flags;
> ? ? ? ?struct clk ? ? ? ? ? ? ?*clk;
> };
>
> void __clk_init(struct device *dev, struct clk_initializer *init);
>
> I hope I made my intention a bit clearer.
>
> Sascha
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |


From B04825 at freescale.com  Sun Mar  4 19:13:52 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Mon, 5 Mar 2012 00:13:52 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <20120305000411.GL7363@n2100.arm.linux.org.uk>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
Message-ID: <4F54053F.9070502@freescale.com>

Russell King - ARM Linux wrote:
> On Sun, Mar 04, 2012 at 11:32:50PM +0000, Tabi Timur-B04825 wrote:
>> Russell King - ARM Linux wrote:
>>> Is the SCR shared between capture and playback?  In that case, what
>>> makes this read-modify-write thread safe?
>>
>> What's "SCR"?
>
> I assumed you knew the code you were commenting on.
>
>                  clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
>
> The register these functions seem to be used on appears to be called
> 'SCR'.

Oh, I didn't know you were referencing a specific register on the part. 
There are multiple uses of clrsetbits_be32 (and its variants) in the function.

To answer your question: I was lead to believe that the individual ALSA 
callback functions are atomic.  So one thread should not be trying to 
start playback while another thread is simultaneously trying to stop it.

> Why do you say "can't" - what prevents it?  If nothing, then this stuff
> is buggy when preempt is enabled, or you're running on SMP.

Sorry, let me rephrase the sentence to be more clear.

"You can't have two threads attempt to initialize the hardware at the same 
time, and expect it to work."

Since I expect ALSA callback functions to be atomic, I'm not concerned 
about one two threads trying to use SCR at the same time.

-- 
Timur Tabi
Linux kernel developer at Freescale


From mturquette at ti.com  Sun Mar  4 19:15:03 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Sun, 4 Mar 2012 16:15:03 -0800
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <20120304143502.GC11546@lunn.ch>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
 <20120304143502.GC11546@lunn.ch>
Message-ID: <CAJOA=zM9Qo=V1He=HfL-6KaFV_Yai=KyC5hbca5iQ3uMO_pZzQ@mail.gmail.com>

On Sun, Mar 4, 2012 at 6:35 AM, Andrew Lunn <andrew at lunn.ch> wrote:
>> +#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, ? ?\
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? _flags, _reg, _bit_idx, ? ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? _gate_flags, _lock) ? ? ? ? ? ? \
>> + ? ? static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static char *_name##_parent_names[] = { ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? _parent_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk *_name##_parents[] = { ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? _parent_ptr, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk_gate _name##_hw = { ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? .clk = &_name, ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .reg = _reg, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .bit_idx = _bit_idx, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .flags = _gate_flags ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .lock = _lock, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .ops = &clk_gate_ops, ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .parent_names = _name##_parent_names, ? ? ? ? ? \
>> + ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##parent_names), ? ? ? ?\
>
> Hi Mike
>
> This should be _name##_parent_names, i.e. you are missing a _.
>
> With this and the previous change, i get something which at least
> compiles...

The gate clock is the only type of the basic clocks that I do not
(currently) use in my OMAP port and it's test coverage has suffered as
a result.  My bad.

Thanks for the review and the patch in the separate thread.  I'll take
the changes in.

Regards,
Mike

>
> ? ? ? ?Andrew

From jason at lakedaemon.net  Sun Mar  4 19:17:13 2012
From: jason at lakedaemon.net (Jason)
Date: Sun, 4 Mar 2012 19:17:13 -0500
Subject: [PATCH 4/5 v2] ARM: kirkwood: convert rtc-mv to fdt.
In-Reply-To: <201203041650.52217.arnd@arndb.de>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <4de611961e8210a0a2c3b56fe72b40dba638752a.1330709314.git.jason@lakedaemon.net>
 <201203041612.44966.michael@walle.cc>
 <201203041650.52217.arnd@arndb.de>
Message-ID: <20120305001713.GU11986@titan.lakedaemon.net>

On Sun, Mar 04, 2012 at 04:50:52PM +0000, Arnd Bergmann wrote:
> On Sunday 04 March 2012, Michael Walle wrote:
> > > @@ -294,11 +295,17 @@ static int __exit mv_rtc_remove(struct
> > > platform_device *pdev) return 0;
> > >  }
> > > 
> > > +static struct of_device_id rtc_mv_of_match_table[] = {
> > > +     { .compatible = "marvell,rtc", },
> > > +     {}
> > > +};
> > > +
> > Isn't here an ifdef CONFIG_OF missing to prevent compiler warnings?
> > 
> 
> Yes, I guess so. I keep thinking that an __unused attribute would
> actually be more helpful here because it lets the compiler automatically
> discard the symbol when it's not used, but we still get potential
> compiler errors and warnings if something inside of the unused data
> is broken.

Hmmm, in the process of responding, I looked up Grant's original email
[1] to show justification.  However, rereading it shows I was
overzealous in my desire to remove #ifdef's.  :-P  Grant only said
adding of_match_ptr() would remove the #else portion of my original
code:

#ifdef CONFIG_OF
...
#else
#define rtc_mv_of_match_table = NULL;
#endif

I'll restore the #ifdef/#endif across the kirkwood code I've changed so
far, without the #else.  __unused shouldn't be necessary, then.

Thanks for the review, Michael.

thx,

Jason.

[1] http://www.spinics.net/lists/arm-kernel/msg162595.html


From B04825 at freescale.com  Sun Mar  4 19:22:07 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Mon, 5 Mar 2012 00:22:07 +0000
Subject: [PATCH 03/20] ARM: imx: merge audmux-v1 and audmux-v2
In-Reply-To: <1330788001-10158-4-git-send-email-shawn.guo@linaro.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-4-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F54072E.6040407@freescale.com>

Shawn Guo wrote:
> +static unsigned char port_mapping[] = {
> +	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
> +};

May as well make this a 'const' array while you're at it.  And perhaps 
uint8_t is a better choice than "unsigned char".

-- 
Timur Tabi
Linux kernel developer at Freescale


From broonie at opensource.wolfsonmicro.com  Sun Mar  4 19:26:36 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 00:26:36 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <4F54053F.9070502@freescale.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
Message-ID: <20120305002635.GA23798@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 12:13:52AM +0000, Tabi Timur-B04825 wrote:

> To answer your question: I was lead to believe that the individual ALSA 
> callback functions are atomic.  So one thread should not be trying to 
> start playback while another thread is simultaneously trying to stop it.

That's correct, there's ALSA level locking.
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From mturquette at ti.com  Sun Mar  4 19:30:08 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Sun, 4 Mar 2012 16:30:08 -0800
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <20120304174229.GD11546@lunn.ch>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
 <20120304174229.GD11546@lunn.ch>
Message-ID: <CAJOA=zNWN6L+-YEkNKoQnjnrrswNpCBmtnhKBm04HekWP46i5w@mail.gmail.com>

On Sun, Mar 4, 2012 at 9:42 AM, Andrew Lunn <andrew at lunn.ch> wrote:
> On Sat, Mar 03, 2012 at 12:29:01AM -0800, Mike Turquette wrote:
>> Many platforms support simple gateable clocks, fixed-rate clocks,
>> adjustable divider clocks and multi-parent multiplexer clocks.
>>
>> This patch introduces basic clock types for the above-mentioned hardware
>> which share some common characteristics.
>
> Hi Mike
>
> These basic clocks don't allow the use of prepare/unprepare, from the
> side of the clock provider. I think i need this.

This is an interesting point and might help us nail down exactly what
we expect from clk_prepare/clk_unprepare.

>
> The Orion Kirkwood SoC has clock gating for most of its on chip
> peripherals, which the other older Orion devices don't have. The SATA
> and PCIe also allows the PHY to be shut down, again which older Orion
> devices don't have. The current code links the clock and the PHY
> together, shutting both down are the same time. So i would like to
> perform the PHY shutdown in the unprepare() function of the clk
> driver.

Do you feel it is The Right Thing to enable/disable the phy from
clk_prepare/clk_unprepare?  I had always imagined that clk_prepare's
purpose was always specific to clock-related activities; for example
maybe turn on a parent PLL that takes a long time to lock, as well as
for the sleepable cases such as clocks over i2c, etc.

However, I know that some others have already started performing
voltage scaling from clk_prepare, so clearly the api is not strict in
it's purpose.

Have you investigated powering up/down the phy from a different layer
such pm_runtime?  That might create a better layer of separation
between other resources needed by an IP block and the clock framework.
 For instance on OMAP we use pm_runtime_get(_sync) to call clk_prepare
& clk_enable and handle other power management-related resources.
Perhaps using the clock framework to power up/down your IP block is
not the right tool for the job.

>
> Is allowing to pass prepare/unprepare functions to basic clocks
> something you want to support? If i prepare a patch would you consider
> it?

My original instinct was "no".  The simple gate clock was always
supposed to be "simple" and if you need more than it provides then it
might be best for your platform to implement a specific clock type.
Especially since the purpose of clk_prepare is still up in the air.

But I'll keep an open mind and hopefully others can chime in.  Please
let me know what you think about my pm_runtime suggestion.  I've Cc'd
Rafael just in case he has something to add here from a design
perspective.

Regards,
Mike

>
> ? ? ? ?Thanks
> ? ? ? ? ? ? ? ?Andrew


From mturquette at ti.com  Sun Mar  4 19:31:31 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Sun, 4 Mar 2012 16:31:31 -0800
Subject: [PATCH] clk: Fix compile errors in DEFINE_CLK_GATE
In-Reply-To: <20120304203359.GE11546@lunn.ch>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
 <20120304203359.GE11546@lunn.ch>
Message-ID: <CAJOA=zNcyvfEmYtbSKFwyLniFbOnQvG4YPb9wbh1ajNATGoPsQ@mail.gmail.com>

On Sun, Mar 4, 2012 at 12:33 PM, Andrew Lunn <andrew at lunn.ch> wrote:
> From 71e9a676b2b2f0dc2bb0cc395e8325cf38f4808b Mon Sep 17 00:00:00 2001
> From: Andrew Lunn <andrew at lunn.ch>
> Date: Sun, 4 Mar 2012 16:31:14 +0100
> Subject: [PATCH] [clk] Fix compile errors in DEFINE_CLK_GATE()
>
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>

Thanks Andrew.  Will roll this fix in.

Regards,
Mike

> ---
> ?include/linux/clk-private.h | ? ?4 ++--
> ?1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> index d06e6fb..9d5c4b1 100644
> --- a/include/linux/clk-private.h
> +++ b/include/linux/clk-private.h
> @@ -95,7 +95,7 @@ extern struct clk_ops clk_gate_ops;
> ? ? ? ? ? ? ? ?}, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?.reg = _reg, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?.bit_idx = _bit_idx, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? ? ? ? ? .flags = _gate_flags ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .flags = _gate_flags, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ? ? ? ? ?.lock = _lock, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?}; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> @@ -104,7 +104,7 @@ extern struct clk_ops clk_gate_ops;
> ? ? ? ? ? ? ? ?.hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ? ? ? ? ?.parent_names = _name##_parent_names, ? ? ? ? ? \
> ? ? ? ? ? ? ? ?.num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> - ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##parent_names), ? ? ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##_parent_names), ? ? ? \
> ? ? ? ? ? ? ? ?.parents = _name##_parents, ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ? ? ? ? ?.flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?};
> --
> 1.7.2.5
>

From jg1.han at samsung.com  Sun Mar  4 20:18:00 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Mon, 05 Mar 2012 10:18:00 +0900
Subject: [PATCH v2 1/2] ARM: EXYNOS: Add USB HOST register definitions
In-Reply-To: <201203011624.04551.heiko@sntech.de>
References: <000701ccf76d$8316b0a0$894411e0$%han@samsung.com>
 <201203011624.04551.heiko@sntech.de>
Message-ID: <006001ccfa6d$ce97b5d0$6bc72170$%han@samsung.com>

> -----Original Message-----
> From: Heiko Stubner
> Sent: Friday, March 02, 2012 12:24 AM
> To: linux-arm-kernel at lists.infradead.org
> Cc: Jingoo Han; linux-usb at vger.kernel.org; linux-samsung-soc at vger.kernel.org; 'Kukjin Kim'; linaro-
> dev at lists.linaro.org; 'Joonyoung Shim'; patches at linaro.org; 'Greg Kroah-Hartman'; 'Sangwook Lee'; 'Alan
> Stern'; 'Thomas Abraham'
> Subject: Re: [PATCH v2 1/2] ARM: EXYNOS: Add USB HOST register definitions
> 
> Am Donnerstag, 1. M?rz 2012, 06:38:20 schrieb Jingoo Han:
> > This patch adds USB HOST register definitions. The definition for
> > EHCI INSNREG00 regiser and corresponding bit field definitions are
> > added.
> >
> > Signed-off-by: Sangwook Lee <sangwook.lee at linaro.org>
> > Signed-off-by: Jingoo Han <jg1.han at samsung.com>
> > ---
> > v2: change the definition name from EHCI_ENA_xxx to EHCI_INSNREG00_ENA_xxx.
> >
> > arch/arm/mach-exynos/include/mach/regs-usb-host.h |   24
> > +++++++++++++++++++++ 1 files changed, 24 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/mach-exynos/include/mach/regs-usb-host.h
> Isn't the general idea to depopulate the mach directories and make drivers
> buildable across architectures?
> 
> The definitions are only used in drivers/usb/host/ehci-s5p.c [in the second
> patch], so there should be no need to add another arch-header and they could
> simply be included in the driver itself or if necessary a
> drivers/usb/host/ehci-s5p.h 
Hi, Heiko St?bner.

OK, I will move the register definitions from arch/arm/mach-exynos/include/mach to
drivers/usb/host/ehci-s5p.c.

Thank you for your suggestion.

> 
> 
> Heiko
> 
> > diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-host.h
> > b/arch/arm/mach-exynos/include/mach/regs-usb-host.h new file mode 100644
> > index 0000000..572b7d4
> > --- /dev/null
> > +++ b/arch/arm/mach-exynos/include/mach/regs-usb-host.h
> > @@ -0,0 +1,24 @@
> > +/*
> > + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> > + *		http://www.samsung.com
> > + *
> > + * EXYNOS - USB HOST register definitions
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#ifndef __REGS_USB_HOST_H
> > +#define __REGS_USB_HOST_H __FILE__
> > +
> > +#define EHCI_INSNREG00(base)			(base + 0x90)
> > +#define EHCI_INSNREG00_ENA_INCR16		(0x1 << 25)
> > +#define EHCI_INSNREG00_ENA_INCR8		(0x1 << 24)
> > +#define EHCI_INSNREG00_ENA_INCR4		(0x1 << 23)
> > +#define EHCI_INSNREG00_ENA_INCRX_ALIGN		(0x1 << 22)
> > +#define EHCI_INSNREG00_ENABLE_DMA_BURST	\
> > +	(EHCI_INSNREG00_ENA_INCR16 | EHCI_INSNREG00_ENA_INCR8 |	\
> > +	 EHCI_INSNREG00_ENA_INCR4 | EHCI_INSNREG00_ENA_INCRX_ALIGN)
> > +
> > +#endif /* __REGS_USB_HOST_H */
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From jg1.han at samsung.com  Sun Mar  4 20:40:14 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Mon, 05 Mar 2012 10:40:14 +0900
Subject: [PATCH v3] USB: ehci-s5p: add DMA burst support
Message-ID: <006101ccfa70$e94e5d90$bbeb18b0$%han@samsung.com>

DMA burst support is added to improve performance in EHCI data
transfer. The USB EHCI controller on Exynos SoCs can use INCR16,
INCR8, and INCR4 mode. These modes of INSNREG00 register should
be set in order to enable DMA burst transfer. This feature is
also related to AHB spec.

Signed-off-by: Jingoo Han <jg1.han at samsung.com>
Signed-off-by: Sangwook Lee <sangwook.lee at linaro.org>
---
v3: move the register definitions to ehci-s5p.c
v2: change the definition name from EHCI_ENA_xxx to EHCI_INSNREG00_ENA_xxx.

 drivers/usb/host/ehci-s5p.c |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 293f741..f098e2a 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -17,6 +17,15 @@
 #include <plat/ehci.h>
 #include <plat/usb-phy.h>
 
+#define EHCI_INSNREG00(base)			(base + 0x90)
+#define EHCI_INSNREG00_ENA_INCR16		(0x1 << 25)
+#define EHCI_INSNREG00_ENA_INCR8		(0x1 << 24)
+#define EHCI_INSNREG00_ENA_INCR4		(0x1 << 23)
+#define EHCI_INSNREG00_ENA_INCRX_ALIGN		(0x1 << 22)
+#define EHCI_INSNREG00_ENABLE_DMA_BURST	\
+	(EHCI_INSNREG00_ENA_INCR16 | EHCI_INSNREG00_ENA_INCR8 |	\
+	 EHCI_INSNREG00_ENA_INCR4 | EHCI_INSNREG00_ENA_INCRX_ALIGN)
+
 struct s5p_ehci_hcd {
 	struct device *dev;
 	struct usb_hcd *hcd;
@@ -128,6 +137,9 @@ static int __devinit s5p_ehci_probe(struct platform_device *pdev)
 	ehci->regs = hcd->regs +
 		HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
 
+	/* DMA burst Enable */
+	writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
+
 	dbg_hcs_params(ehci, "reset");
 	dbg_hcc_params(ehci, "reset");
 
@@ -234,6 +246,9 @@ static int s5p_ehci_resume(struct device *dev)
 	if (pdata && pdata->phy_init)
 		pdata->phy_init(pdev, S5P_USB_PHY_HOST);
 
+	/* DMA burst Enable */
+	writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
+
 	if (time_before(jiffies, ehci->next_statechange))
 		msleep(100);
 
-- 
1.7.1




From richard.zhao at freescale.com  Sun Mar  4 21:04:11 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Mon, 5 Mar 2012 10:04:11 +0800
Subject: [PATCH v5 2/4] clk: Kconfig: add entry for HAVE_CLK_PREPARE
In-Reply-To: <1330763341-3437-3-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-3-git-send-email-mturquette@linaro.org>
Message-ID: <20120305020410.GB3261@b20223-02.ap.freescale.net>

On Sat, Mar 03, 2012 at 12:28:59AM -0800, Mike Turquette wrote:
> The common clk framework provides clk_prepare and clk_unprepare
> implementations.  Create an entry for HAVE_CLK_PREPARE so that
> COMMON_CLK can select it.
> 
> Signed-off-by: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Mike Turquette <mturquette at ti.com>
> Acked-by: Shawn Guo <shawn.guo at linaro.org>
> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Richard Zhao <richard.zhao at linaro.org>
> Cc: Saravana Kannan <skannan at codeaurora.org>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Stephen Boyd <sboyd at codeaurora.org>
> Cc: Amit Kucheria <amit.kucheria at linaro.org>
> Cc: Deepak Saxena <dsaxena at linaro.org>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Andrew Lunn <andrew at lunn.ch>
> ---
>  drivers/clk/Kconfig |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 9b3cd08..3912576 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -8,3 +8,6 @@ config HAVE_CLK_PREPARE
>  
>  config HAVE_MACH_CLKDEV
>  	bool
> +
> +config HAVE_CLK_PREPARE
> +	bool
We've already had it. redundant?

Thanks
Richard
> -- 
> 1.7.5.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From olof at lixom.net  Sun Mar  4 22:39:35 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 19:39:35 -0800
Subject: [PATCH v3 06/10] pwm: Add NVIDIA Tegra SoC support
In-Reply-To: <20120303224212.GA6661@avionic-0098.mockup.avionic-design.de>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <1329923841-32017-7-git-send-email-thierry.reding@avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E63@HQMAIL01.nvidia.com>
 <20120303224212.GA6661@avionic-0098.mockup.avionic-design.de>
Message-ID: <20120305033935.GA32675@quad.lixom.net>

On Sat, Mar 03, 2012 at 11:42:12PM +0100, Thierry Reding wrote:

> Those probably weren't there yet when I prepared the first series. I'll have
> another look will sync up with it after testing that it still works.


Yep, the patch in question is from Simon, and it's at:

http://git.chromium.org/gitweb/?p=chromiumos/third_party/kernel.git;a=commitdiff;h=7778c724bf3211c534f9bcef7b26afc6cb067a82

Essentially, the driver accidentally rounded down a backlight setting of
'1' which is how it was found.


-Olof


From jason at lakedaemon.net  Sun Mar  4 22:41:13 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 4 Mar 2012 22:41:13 -0500
Subject: [GIT PULL v3] ARM: kirkwood: fdt: convert kirkwood init funcs to fdt
Message-ID: <20120305034113.GB5050@titan.lakedaemon.net>

The following changes since commit 759a45185ac0e4dfaf8bbfcb390ec73aca4b7a34:

  ARM: kirkwood: convert uart0 to devicetree. (2012-02-27 16:21:44 +0000)

are available in the git repository at:
  git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt

Arnd,

Sorry for the redo, here's what changed:
	orion-spi: put #ifdef CONFIG_OF around of_device_id
	rtc-mv: put #ifdef CONFIG_OF around of_device_id
	rtc-mv: more accurate compatible strings
	orion-wdt: put #ifdef CONFIG_OF around of_device_id
	orion-wdt: more accurate compatible strings

Jason Cooper (5):
      ARM: kirkwood: covert orion-spi to fdt.
      ARM: kirkwood: move var setting to correct location.
      ARM: kirkwood: fdt: absorb kirkwood_init()
      ARM: kirkwood: convert rtc-mv to fdt.
      ARM: kirkwood: convert orion-wdt to fdt.

 arch/arm/boot/dts/kirkwood-dreamplug.dts |   34 +++++++++++++++
 arch/arm/boot/dts/kirkwood.dtsi          |   12 +++++
 arch/arm/mach-kirkwood/board-dt.c        |   67 +++++++++++------------------
 arch/arm/mach-kirkwood/common.c          |   21 +++++++--
 arch/arm/mach-kirkwood/common.h          |    6 +++
 arch/arm/plat-orion/common.c             |    7 +++-
 drivers/rtc/rtc-mv.c                     |   10 ++++
 drivers/spi/spi-orion.c                  |   39 +++++++++++++++--
 drivers/watchdog/orion_wdt.c             |   49 ++++++++++++++++-----
 9 files changed, 182 insertions(+), 63 deletions(-)


From robherring2 at gmail.com  Sun Mar  4 22:50:22 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sun, 04 Mar 2012 21:50:22 -0600
Subject: [PULL] generic irq chip and pl061 irqdomain support
In-Reply-To: <4F3ADFE7.4090409@gmail.com>
References: <4F3ADFE7.4090409@gmail.com>
Message-ID: <4F5437FE.2000306@gmail.com>

Grant,

On 02/14/2012 04:27 PM, Rob Herring wrote:
> Grant,
> 
> Please pull. This is based on your current branch which you have said
> you plan to rebase, so feel free to rebase these as you need to. This
> has been tested on highbank and i.MX5.
> 

Ping.

I've rebased onto your current tree. Updated pull request:

The following changes since commit 280ad7fda5f95211857fda38960f2b6fdf6edd3e:

  mfd: twl-core: Add IRQ_DOMAIN dependency (2012-02-26 16:48:06 -0700)

are available in the git repository at:
  git://sources.calxeda.com/kernel/linux.git irqdomain-for-grant

Rob Herring (3):
      ARM: kconfig: always select IRQ_DOMAIN
      irq: add irq_domain support to generic-chip
      gpio: pl061: enable interrupts with DT style binding

 .../devicetree/bindings/gpio/pl061-gpio.txt        |   15 ++
 arch/arm/Kconfig                                   |    2 +-
 arch/arm/common/Kconfig                            |    2 -
 drivers/gpio/gpio-pl061.c                          |   48 ++++---
 include/linux/irq.h                                |   15 ++
 kernel/irq/generic-chip.c                          |  152
+++++++++++++++++---
 6 files changed, 186 insertions(+), 48 deletions(-)

Rob

> 
> The following changes since commit 98ecf5260207e45ad587a5dc16c39f5ede467a45:
> 
>   irq_domain/microblaze: Convert microblaze to use irq_domains
> (2012-02-05 23:02:26 -0700)
> 
> are available in the git repository at:
>   git://sources.calxeda.com/kernel/linux.git irqdomain-for-grant
> 
> Rob Herring (3):
>       ARM: kconfig: always select IRQ_DOMAIN
>       irq: add irq_domain support to generic-chip
>       gpio: pl061: enable interrupts with DT style binding
> 
>  .../devicetree/bindings/gpio/pl061-gpio.txt        |   15 ++
>  arch/arm/Kconfig                                   |    2 +-
>  arch/arm/common/Kconfig                            |    2 -
>  drivers/gpio/gpio-pl061.c                          |   48 ++++---
>  include/linux/irq.h                                |   15 ++
>  kernel/irq/generic-chip.c                          |  152
> +++++++++++++++++---
>  6 files changed, 186 insertions(+), 48 deletions(-)
> 
> Rob



From olof at lixom.net  Sun Mar  4 23:21:07 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 4 Mar 2012 20:21:07 -0800
Subject: [PATCH 1/2] ARM: Add Kconfig option to use mkimage -T
 kernel_noload
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE861683@HQMAIL01.nvidia.com>
References: <1330473804-23348-1-git-send-email-swarren@nvidia.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861683@HQMAIL01.nvidia.com>
Message-ID: <20120305042107.GA31142@quad.lixom.net>

On Thu, Mar 01, 2012 at 09:01:04AM -0800, Stephen Warren wrote:
> Stephen Warren wrote at Tuesday, February 28, 2012 5:03 PM:
> > uImage files typically encode a single absolute load and entry address.
> > This is inconvenient when attempting to share that uImage across multiple
> > SoCs with different physical RAM addresses. Recent versions of mkimage
> > implement a "kernel_noload" image type which encodes no absolute load
> > address, and a relative entry address. This works well for uImage-wrapped
> > ARM zImages, since they are relocatable.
> > 
> > This is enabled by commit b9b50e89d317c58becd0e2d7fac2e21e3a81dd0a
> > "image: Implement IH_TYPE_KERNEL_NOLOAD" in U-Boot.
> 
> So Russell, are you NAKing this patch then?
> 
> If so, I guess I'll just go and add more cruft to my copy-a-kernel-to-
> an-sd-card script. Which is a pity since every other person will have
> to do the same, but oh well.

I'd say send them on to his patch tracker and he can decide from there?

Feel free to add:

Acked-by: Olof Johansson <olof at lixom.net>

Some people seem to have a bone to pick with u-boot, and apparantly want us to
make it harder to use the kernel with the firmware that is already out there.
I personally disagree, but as you said, I'll just add my own wrapper script if
it comes to it. So will everyone else though, and that just seems wasteful.

There hasn't been much churn lately around boot images (unlike the situation
back 5 years ago in the thread that was referenced earlier in this thread, as
far as I can tell).

So while the churn in this case is compensated by added convenience
and productivity for me personally, it's up to Russell to decide if it
goes in.


-Olof


From vinod.koul at intel.com  Sun Mar  4 23:47:10 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Mon, 05 Mar 2012 10:17:10 +0530
Subject: [PATCH v6 0/2] patch set about the MXS-DMA
In-Reply-To: <CAMiH66HmV+58w36DGCt+e=ihTrYUwXf1Cur+678YX2GKcB1-jA@mail.gmail.com>
References: <1329373053-19494-1-git-send-email-b32955@freescale.com>
 <4F4D9725.3090100@freescale.com>
 <1330502098.3545.78.camel@sauron.fi.intel.com>
 <4F4DE0E5.8070808@freescale.com>
 <1330516974.3545.104.camel@sauron.fi.intel.com>
 <CAMiH66HmV+58w36DGCt+e=ihTrYUwXf1Cur+678YX2GKcB1-jA@mail.gmail.com>
Message-ID: <1330922830.24656.137.camel@vkoul-udesk3>

On Wed, 2012-02-29 at 08:13 -0500, Huang Shijie wrote:
> Hi Artem:
> 
> On Wed, Feb 29, 2012 at 7:00 AM, Bityutskiy, Artem
> <artem.bityutskiy at intel.com> wrote:
> > On Wed, 2012-02-29 at 16:25 +0800, Huang Shijie wrote:
> >> Hi Artem:
> >> > On Wed, 2012-02-29 at 11:10 +0800, Huang Shijie wrote:
> >> >> Hi:
> >> >>
> >> >> ping.
> >> > Is this patch-set independent or requires something like gpma patches?
> >> >
> >> This patch set is independent, and it does not depend upon any other
> >> patches.
> >
> > Pushed both to l2-mtd.git tree, thanks. I am worried that it touches
> > other subsystems like dma, sound, and mmc and there are no acks for
> > those. Would be nice to get them somehow.
> >
> 
> I ever thought Vinod could accept this patch set.
> 
> To Vinod & Chris:
>       Could you give the ack to the first patch?
Both,
Acked-by: Vinod Koul <vinod.koul at linux.intel.com>
Although the second patch overloads the dmaengine flags but for lack of
any other suitable alternative, this looks okay...
> 
> Does the second patch need  extra acks beside Shawn's?
> 
> BR
> Huang Shijie
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/


-- 
~Vinod



From thierry.reding at avionic-design.de  Mon Mar  5 02:00:50 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Mon, 5 Mar 2012 08:00:50 +0100
Subject: [PATCH v3 06/10] pwm: Add NVIDIA Tegra SoC support
In-Reply-To: <20120305033935.GA32675@quad.lixom.net>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <1329923841-32017-7-git-send-email-thierry.reding@avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E63@HQMAIL01.nvidia.com>
 <20120303224212.GA6661@avionic-0098.mockup.avionic-design.de>
 <20120305033935.GA32675@quad.lixom.net>
Message-ID: <20120305070050.GA10914@avionic-0098.mockup.avionic-design.de>

* Olof Johansson wrote:
> On Sat, Mar 03, 2012 at 11:42:12PM +0100, Thierry Reding wrote:
> 
> > Those probably weren't there yet when I prepared the first series. I'll have
> > another look will sync up with it after testing that it still works.
> 
> 
> Yep, the patch in question is from Simon, and it's at:
> 
> http://git.chromium.org/gitweb/?p=chromiumos/third_party/kernel.git;a=commitdiff;h=7778c724bf3211c534f9bcef7b26afc6cb067a82
> 
> Essentially, the driver accidentally rounded down a backlight setting of
> '1' which is how it was found.

Thanks for the link, I'll squash it into this patch in the next version.

Thierry
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From Barry.Song at csr.com  Mon Mar  5 02:13:46 2012
From: Barry.Song at csr.com (Barry Song)
Date: Mon, 5 Mar 2012 15:13:46 +0800
Subject: [PATCH v2] MM: CMA: add a simple kernel module as the helper to test
 CMA
Message-ID: <1330931626-30855-1-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

Any write request to /dev/cma_test will let the module to allocate memory from
CMA, for example:

1st time
$ echo 1024 > /dev/cma_test
will require cma_test to request 1MB(1024KB)
2nd time
$ echo 2048 > /dev/cma_test
will require cma_test to request 2MB(2048KB)

Any read request to /dev/cma_test will let the module to free the 1st valid
memory from CMA, for example:

1st time
$ cat /dev/cma_test
will require cma_test to free the 1MB allocated in the first write request
2nd time
$ cat /dev/cma_test
will require cma_test to free the 2MB allocated in the second write request

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 -v2:
 move to support multiple allocation and permit users to set alloc size
 (pointed out by Michal Nazarewicz)

 tools/cma/Makefile   |   13 +++++
 tools/cma/cma_test.c |  140 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 153 insertions(+), 0 deletions(-)
 create mode 100644 tools/cma/Makefile
 create mode 100644 tools/cma/cma_test.c

diff --git a/tools/cma/Makefile b/tools/cma/Makefile
new file mode 100644
index 0000000..d15c2c0
--- /dev/null
+++ b/tools/cma/Makefile
@@ -0,0 +1,13 @@
+# Kernel modules
+#
+# To compile for ARM:
+# make ARCH=arm CC=arm-none-linux-gnueabi-gcc
+#
+obj-m	+= cma_test.o
+
+build: kernel_modules
+
+kernel_modules:
+	${MAKE} -C $(CURDIR)/../.. M=$(CURDIR)
+clean:
+	${MAKE} -C $(CURDIR)/../.. M=$(CURDIR) clean
diff --git a/tools/cma/cma_test.c b/tools/cma/cma_test.c
new file mode 100644
index 0000000..46af250
--- /dev/null
+++ b/tools/cma/cma_test.c
@@ -0,0 +1,140 @@
+/*
+ * kernel module helper for testing CMA
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+struct cma_allocation {
+	struct list_head list;
+	unsigned long size;
+	dma_addr_t dma;
+	void *virt;
+};
+
+static struct device *cma_dev;
+static LIST_HEAD(cma_allocations);
+static DEFINE_SPINLOCK(cma_lock);
+
+/*
+ * any read request will free the 1st allocated coherent memory, eg.
+ * cat /dev/cma_test
+ */
+static ssize_t
+cma_test_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
+{
+	struct cma_allocation *alloc = NULL;
+
+	spin_lock(&cma_lock);
+	if (!list_empty(&cma_allocations)) {
+		alloc = list_first_entry(&cma_allocations,
+			struct cma_allocation, list);
+		list_del(&alloc->list);
+	}
+	spin_unlock(&cma_lock);
+
+	if (alloc) {
+		dma_free_coherent(cma_dev, alloc->size, alloc->virt,
+			alloc->dma);
+
+		_dev_info(cma_dev, "free CM at virtual address: 0x%p dma address: 0x%p size:%luKiB\n",
+			alloc->virt, (void *)alloc->dma, alloc->size / SZ_1K);
+		kfree(alloc);
+	}
+
+	return 0;
+}
+
+/*
+ * any write request will alloc a new coherent memory, eg.
+ * echo 1024 > /dev/cma_test
+ * will request 1024KiB by CMA
+ */
+static ssize_t
+cma_test_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
+{
+	struct cma_allocation *alloc;
+	int ret;
+
+	alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
+	if (!alloc)
+		return -ENOMEM;
+
+	ret = kstrtoul_from_user(buf, count, 0, &alloc->size);
+	if (ret)
+		return ret;
+
+	if (!alloc->size)
+		return -EINVAL;
+
+	if (alloc->size > (ULONG_MAX << PAGE_SHIFT))
+		return -EOVERFLOW;
+
+	alloc->size *= SZ_1K;
+	alloc->virt = dma_alloc_coherent(cma_dev, alloc->size,
+		&alloc->dma, GFP_KERNEL);
+
+	if (alloc->virt) {
+		_dev_info(cma_dev, "allocate CM at virtual address: 0x%p"
+			"address: 0x%p size:%luKiB\n", alloc->virt,
+			(void *)alloc->dma, alloc->size / SZ_1K);
+
+		spin_lock(&cma_lock);
+		list_add_tail(&alloc->list, &cma_allocations);
+		spin_unlock(&cma_lock);
+
+		return count;
+	} else {
+		dev_err(cma_dev, "no mem in CMA area\n");
+		kfree(alloc);
+		return -ENOSPC;
+	}
+}
+
+static const struct file_operations cma_test_fops = {
+	.owner =    THIS_MODULE,
+	.read  =    cma_test_read,
+	.write =    cma_test_write,
+};
+
+static struct miscdevice cma_test_misc = {
+	.name = "cma_test",
+	.fops = &cma_test_fops,
+};
+
+static int __init cma_test_init(void)
+{
+	int ret = 0;
+
+	ret = misc_register(&cma_test_misc);
+	if (unlikely(ret)) {
+		pr_err("failed to register cma test misc device!\n");
+		return ret;
+	}
+	cma_dev = cma_test_misc.this_device;
+	cma_dev->coherent_dma_mask = ~0;
+	_dev_info(cma_dev, "registered.\n");
+
+	return ret;
+}
+module_init(cma_test_init);
+
+static void __exit cma_test_exit(void)
+{
+	misc_deregister(&cma_test_misc);
+}
+module_exit(cma_test_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Barry Song <Baohua.Song at csr.com>");
+MODULE_DESCRIPTION("kernel module to help the test of CMA");
+MODULE_ALIAS("CMA test");
-- 
1.7.1



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From shawn.guo at linaro.org  Mon Mar  5 02:33:47 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 5 Mar 2012 15:33:47 +0800
Subject: [PATCH 03/20] ARM: imx: merge audmux-v1 and audmux-v2
In-Reply-To: <4F54072E.6040407@freescale.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-4-git-send-email-shawn.guo@linaro.org>
 <4F54072E.6040407@freescale.com>
Message-ID: <20120305073345.GA16232@S2101-09.ap.freescale.net>

On Mon, Mar 05, 2012 at 12:22:07AM +0000, Tabi Timur-B04825 wrote:
> Shawn Guo wrote:
> > +static unsigned char port_mapping[] = {
> > +	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
> > +};
> 
> May as well make this a 'const' array while you're at it.  And perhaps 
> uint8_t is a better choice than "unsigned char".
> 
Okay, will do.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Mon Mar  5 02:35:41 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 5 Mar 2012 15:35:41 +0800
Subject: [PATCH 04/20] ARM: imx: convert audmux to a platform driver
In-Reply-To: <20120304190031.GT3852@pengutronix.de>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-5-git-send-email-shawn.guo@linaro.org>
 <20120304190031.GT3852@pengutronix.de>
Message-ID: <20120305073538.GB16232@S2101-09.ap.freescale.net>

On Sun, Mar 04, 2012 at 08:00:31PM +0100, Sascha Hauer wrote:
...
> The audmux is a device completely internal to the i.MX and is registered
> without platform_data. I think we should do the device registration
> somewhere in the SoC specific code and not do it in each board.
> Also we now have platform_device_register_simple, we shouldn't use the
> imx_ variant in new code.
> 
Good point.  Then we do not need to add audmux device board by board.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Mon Mar  5 02:39:32 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 5 Mar 2012 15:39:32 +0800
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <4F53F704.8080703@freescale.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
Message-ID: <20120305073930.GC16232@S2101-09.ap.freescale.net>

On Sun, Mar 04, 2012 at 11:13:09PM +0000, Tabi Timur-B04825 wrote:
> Shawn Guo wrote:
> > +#ifdef PPC
> > +#define read_ssi(addr)		in_be32(addr)
> > +#define write_ssi(val, addr)	out_be32(addr, val)
> > +#elif defined ARM
> > +#define read_ssi(addr)		readl(addr)
> > +#define write_ssi(val, addr)	writel(val, addr)
> > +#endif
> 
> Can you also add an ARM version of clrsetbits_be32()?  Something like this:
> 
> #ifdef PPC
> #define read_ssi(addr)		in_be32(addr)
> #define write_ssi(val, addr)	out_be32(addr, val)
> #define write_ssi_mask(addr, clear, set)	clrsetbits_be32(addr, clear, set)
> #elif defined ARM
> #define read_ssi(addr)		readl(addr)
> #define write_ssi(val, addr)	writel(val, addr)
> #define write_ssi_mask(addr, clear, set) \
> 	{ u32 __val; \
> 	val = readl(&ssi->scr); \
> 	val = (val & ~(clear) | (set); \
> 	writel(val, addr)
> #endif
> 
Yeah, it makes the diff neat.  However I would make it an inline
function which is easier to play.

#ifdef PPC
#define read_ssi(addr)                   in_be32(addr)
#define write_ssi(val, addr)             out_be32(addr, val)
#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
#elif defined ARM
#define read_ssi(addr)                   readl(addr)
#define write_ssi(val, addr)             writel(val, addr)
static inline void write_ssi_mask(void __iomem *addr, u32 clear, u32 set)
{
        u32 val = readl(addr);
        val = (val & ~clear) | set;
        writel(val, addr);
}
#endif

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Mon Mar  5 03:06:25 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 5 Mar 2012 16:06:25 +0800
Subject: [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120304133818.GE3083@opensource.wolfsonmicro.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
 <20120304133818.GE3083@opensource.wolfsonmicro.com>
Message-ID: <20120305080623.GD16232@S2101-09.ap.freescale.net>

On Sun, Mar 04, 2012 at 01:38:18PM +0000, Mark Brown wrote:
> On Sat, Mar 03, 2012 at 11:20:01PM +0800, Shawn Guo wrote:
> 
> > +	ret = snd_soc_dai_set_fmt(rtd->codec_dai, SND_SOC_DAIFMT_I2S |
> > +						  SND_SOC_DAIFMT_NB_NF |
> > +						  SND_SOC_DAIFMT_CBM_CFM);
> 
> Initialise this from the card.  
> 
> Since none of the startup is dynamic it should all be done on DAI init
> rather than rerun each time audio is started.
> 
Ok, will move imx_sgtl5000_startup over to snd_soc_dai_link init hook.
Please let me know if this is not what you are asking for.

> > +	/* Add soc-audio device */
> > +	data->soc_audio_pdev = platform_device_alloc("soc-audio", -1);
> > +	if (!data->soc_audio_pdev) {
> > +		ret = -ENOMEM;
> > +		goto err;
> > +	}
> 
> No, use snd_soc_register_card().  soc-audio has been deprecated since
> 2.6.38.
> 
I copied it from mpc8610_hpcd driver.  Will change.

> > +static int __devexit imx_sgtl5000_remove(struct platform_device *pdev)
> > +{
> > +	struct imx_sgtl5000_data *data = dev_get_drvdata(&pdev->dev);
> > +
> > +	platform_device_unregister(data->pcm_audio_pdev);
> 
> This looks like there's a problem with the bindings, why are you
> registering the DMA device from the card?

There is a dma node in the device tree to instantiate the dma device
backed by a dmaengine driver.  As a client peripheral of that dmaengine
device, the SSI owns just a dma request/event number.  With the number
encoded in SSI node, there is no hardware resource to be claimed by
that pcm-device, so we do not have it in device tree.  Then we have
to register this device in either fsl_ssi driver or machine driver.
I chose to do something that tegra is doing, registering the pcm device
in machine driver, to keep fsl_ssi away from imx specific bits as much
as possible.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Mon Mar  5 03:07:59 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 5 Mar 2012 16:07:59 +0800
Subject: [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <4F53FC06.1020805@freescale.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
 <4F53FC06.1020805@freescale.com>
Message-ID: <20120305080757.GE16232@S2101-09.ap.freescale.net>

On Sun, Mar 04, 2012 at 11:34:31PM +0000, Tabi Timur-B04825 wrote:
> Shawn Guo wrote:
> > +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
> 
> I encourage developers to put their own name in the MODULE_AUTHOR macro.
> 
Seems you get a strong opinion on this.  Okay, will put my name there.

-- 
Regards,
Shawn


From rnayak at ti.com  Mon Mar  5 02:54:54 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 05 Mar 2012 13:24:54 +0530
Subject: [PATCH v2 0/6] mmc: omap_hsmmc: Clean up use/abuse of pdev->id
In-Reply-To: <4F476228.7060607@ti.com>
References: <1329996409-26861-1-git-send-email-rnayak@ti.com>
 <4F476228.7060607@ti.com>
Message-ID: <4F54714E.6080805@ti.com>

On Friday 24 February 2012 03:40 PM, Rajendra Nayak wrote:
> Chris,
>
> On Thursday 23 February 2012 04:56 PM, Rajendra Nayak wrote:
>> Re-sending as these patches did not make it to the lists due to
>> issues with my 'git send-email'
>>
>> This series mainly cleans up all instances of hardcoding's in
>> the driver based on pdev->id. This is cleanup leading to the
>> DT adaptation of omap_hsmmc driver.
>>
>> v2 mainly has some minor changes to get rid of a debug print
>> which was still using host->id and getting rid of 'id' field
>> entirely from omap_hsmmc_host struct.
>>
>> The series is tested on OMAP4SDP, OMAP4panda, OMAP3beagle and OMAP2430SDP
>> boards.
>
> This series is reviewed/tested and acked by Balaji and Venkat.
> Care to pull this in for 3.4?
>
> I have one other cleanup patch on top of this series to make all
> remaining pr_* prints in the driver to dev_* [1].
> It would be great if you could pick that up as well.
>
> These patches are cleanups leading to the DT conversion of omap_hsmmc
> driver.

Chris, Ping. I am basing my DT support patches on top of these cleanups.
Would be great if you can have a look and pull them in.

>
> regards,
> Rajendra
>
> [1] http://marc.info/?l=linux-mmc&m=132999677405098&w=3
>
>>
>> regards,
>> Rajendra
>>
>> Balaji T K (3):
>> mmc: omap_hsmmc: use platform_get_resource_byname for tx/rx DMA
>> channels
>> mmc: omap_hsmmc: remove unused .set_sleep function
>> mmc: omap_hsmmc: Use OMAP_HSMMC_SUPPORTS_DUAL_VOLT flag to remove
>> host->id based hardcoding
>>
>> Rajendra Nayak (3):
>> mmc: omap_hsmmc: Get rid of omap_hsmmc_1_set_power function
>> mmc: omap_hsmmc: Get rid of omap_hsmmc_4_set_power function
>> mmc: omap_hsmmc: Don't expect MMC1 to always have vmmc supply
>>
>> arch/arm/plat-omap/include/plat/mmc.h | 2 -
>> drivers/mmc/host/omap_hsmmc.c | 175 +++------------------------------
>> 2 files changed, 16 insertions(+), 161 deletions(-)
>>
>



From rnayak at ti.com  Mon Mar  5 03:19:45 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 05 Mar 2012 13:49:45 +0530
Subject: [PATCH 11/12] mfd: twl4030-irq: Return twl6030_mmc_card_detect
 IRQ for board setup
In-Reply-To: <20120302181522.GC13967@legolas.emea.dhcp.ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-12-git-send-email-b-cousson@ti.com>
 <20120302181522.GC13967@legolas.emea.dhcp.ti.com>
Message-ID: <4F547721.4010107@ti.com>

On Friday 02 March 2012 11:45 PM, Felipe Balbi wrote:
> Hi,
>
> On Fri, Mar 02, 2012 at 05:50:23PM +0100, Benoit Cousson wrote:
>> Card detect IRQ from the TWL6030 used to be provided to the MMC
>> controller code using a statically allocated IRQ scheme:
>>
>>    card_detect_irq = TWL6030_IRQ_BASE + MMCDETECT_INTR_OFFSET;
>>
>> This is no longer valid in a SPARSE_IRQ context since there is no more
>> pre-defined TWL6030_IRQ_BASE.
>>
>> Return the proper card detect IRQ value in the twl6030_mmc_card_detect_config
>> that will be called from the MMC controller.
>>
>> Signed-off-by: Benoit Cousson<b-cousson at ti.com>
>> Cc: Felipe Balbi<balbi at ti.com>
>> Cc: Tony Lindgren<tony at atomide.com>
>> Cc: Rajendra Nayak<rnayak at ti.com>
>
> Reviewed-by: Felipe Balbi<balbi at ti.com>
>
>> ---
>>   drivers/mfd/twl6030-irq.c |    3 ++-
>>   1 files changed, 2 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
>> index a1c7183..4a63de2 100644
>> --- a/drivers/mfd/twl6030-irq.c
>> +++ b/drivers/mfd/twl6030-irq.c
>> @@ -308,7 +308,8 @@ int twl6030_mmc_card_detect_config(void)
>>   									ret);
>>   		return ret;
>>   	}
>> -	return 0;
>> +
>> +	return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
>>   }
>>   EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
>
> At some point this twl6030_mmc_card_detect_config() needs to vanish in
> favor of a better mechanism. Maybe passing the GPIO number an requiring
> the driver to request the GPIO, set its direction and use it as IRQ
> line.
>
> the only problem would arise if we end up hooking the Card Detect pin to
> a real IRQ line, but then we can use a flag to differentiate.

Shouldn't this be hidden from the driver completely if the card detect
pin is a GPIO or connected to a real IRQ line? And the board/DT handle 
this instead of the driver knowing when to do a gpio_to_irq()?
But I see thats not the case with most mmc drivers, not just OMAP, I
wonder why.

>



From b-cousson at ti.com  Mon Mar  5 03:29:54 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 5 Mar 2012 09:29:54 +0100
Subject: [PATCH 11/12] mfd: twl4030-irq: Return twl6030_mmc_card_detect
 IRQ for board setup
In-Reply-To: <4F523419.3080100@ru.mvista.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-12-git-send-email-b-cousson@ti.com>
 <4F523419.3080100@ru.mvista.com>
Message-ID: <4F547982.9040900@ti.com>

Hi Sergei,

On 3/3/2012 4:09 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 02-03-2012 20:50, Benoit Cousson wrote:
>
>> Card detect IRQ from the TWL6030 used to be provided to the MMC
>
>> controller code using a statically allocated IRQ scheme:
>>
>> card_detect_irq = TWL6030_IRQ_BASE + MMCDETECT_INTR_OFFSET;
>>
>> This is no longer valid in a SPARSE_IRQ context since there is no more
>> pre-defined TWL6030_IRQ_BASE.
>>
>> Return the proper card detect IRQ value in the
>> twl6030_mmc_card_detect_config
>> that will be called from the MMC controller.
>>
>> Signed-off-by: Benoit Cousson<b-cousson at ti.com>
>> Cc: Felipe Balbi<balbi at ti.com>
>> Cc: Tony Lindgren<tony at atomide.com>
>> Cc: Rajendra Nayak<rnayak at ti.com>
>> ---
>> drivers/mfd/twl6030-irq.c | 3 ++-
>
> Subject talks about twl4030-irq.

Oops, good catch. thanks.

I guess that Tony's patch (mmc: omap_hsmmc: Simplify init for twl6030 
MMC card detect) will supersede that one.

Thanks,
Benoit


From linus.walleij at stericsson.com  Mon Mar  5 03:33:13 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 5 Mar 2012 09:33:13 +0100
Subject: [PATCH] ARM: ux500: wake secondary cpu via resched
Message-ID: <1330936393-14105-1-git-send-email-linus.walleij@stericsson.com>

From: Jonas Aaberg <jonas.aberg at stericsson.com>

Wake secondary cpu via resched instead of
"Unknown IPI message 0x1"

Signed-off-by: Jonas Aaberg <jonas.aberg at stericsson.com>
Reviewed-by: Rickard Andersson <rickard.andersson at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-ux500/platsmp.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index d2058ef..eff5842 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -99,7 +99,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 */
 	write_pen_release(cpu_logical_map(cpu));
 
-	gic_raise_softirq(cpumask_of(cpu), 1);
+	smp_send_reschedule(cpu);
 
 	timeout = jiffies + (1 * HZ);
 	while (time_before(jiffies, timeout)) {
-- 
1.7.8



From andrew at lunn.ch  Mon Mar  5 03:48:23 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 5 Mar 2012 09:48:23 +0100
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <CAJOA=zNWN6L+-YEkNKoQnjnrrswNpCBmtnhKBm04HekWP46i5w@mail.gmail.com>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
 <20120304174229.GD11546@lunn.ch>
 <CAJOA=zNWN6L+-YEkNKoQnjnrrswNpCBmtnhKBm04HekWP46i5w@mail.gmail.com>
Message-ID: <20120305084823.GD24858@lunn.ch>

On Sun, Mar 04, 2012 at 04:30:08PM -0800, Turquette, Mike wrote:
> On Sun, Mar 4, 2012 at 9:42 AM, Andrew Lunn <andrew at lunn.ch> wrote:
> > On Sat, Mar 03, 2012 at 12:29:01AM -0800, Mike Turquette wrote:
> >> Many platforms support simple gateable clocks, fixed-rate clocks,
> >> adjustable divider clocks and multi-parent multiplexer clocks.
> >>
> >> This patch introduces basic clock types for the above-mentioned hardware
> >> which share some common characteristics.
> >
> > Hi Mike
> >
> > These basic clocks don't allow the use of prepare/unprepare, from the
> > side of the clock provider. I think i need this.
> 
> This is an interesting point and might help us nail down exactly what
> we expect from clk_prepare/clk_unprepare.
> 
> >
> > The Orion Kirkwood SoC has clock gating for most of its on chip
> > peripherals, which the other older Orion devices don't have. The SATA
> > and PCIe also allows the PHY to be shut down, again which older Orion
> > devices don't have. The current code links the clock and the PHY
> > together, shutting both down are the same time. So i would like to
> > perform the PHY shutdown in the unprepare() function of the clk
> > driver.
> 
> Do you feel it is The Right Thing to enable/disable the phy from
> clk_prepare/clk_unprepare?  

Humm, not sure yet. I don't know all the different possibilities,
which is why i tried to describe my use case, rather than just assume
i need prepare/unprepare.

I also realized i did not explain my use case properly. 

At boot, uboot is turning on various clocks and SATA/PCIe PHYs etc, in
order to get the device booted. Linux takes over, and the
Orion/kirkwood board files, ask the kirkwood or generic Orion code to
create platform_data structures for the different devices that the
board uses. The kirkwood code keeps a bitmap of devices for which it
creates platform data for which there is a gated clock. Then in a
lateinit call, it turns on clocks which are needed, and also turns off
clocks which are no longer needed, because the board did not ask for a
driver binding for that device. If it turns off a SATA or PCIe clock,
it also turns off the PHY associated with it.

So we are talking about turning off hardware for which there is no
driver. This seems to exclude pm_runtime_get(_sync), which is about
hardware with drivers.

We touched on this subject a couple of months ago, at least with
respect to clocks. You said that is what the flag CLK_IGNORE_UNUSED
will be used for. In a lateinit call, you plan to iterate over all
clocks and turn off any which don't have CLK_IGNORE_UNUSED and have
not been enabled. I assume you will call both disable() and
unprepare(), and if i've can put code into the unprepare to turn the
PHY off, all is good.

> > Is allowing to pass prepare/unprepare functions to basic clocks
> > something you want to support? If i prepare a patch would you consider
> > it?
> 
> My original instinct was "no".  The simple gate clock was always
> supposed to be "simple" and if you need more than it provides then it
> might be best for your platform to implement a specific clock type.
> Especially since the purpose of clk_prepare is still up in the air.

I think i can wrap your simple gate clock, to make my "complex" gate
clock. What would help is if you would EXPORT_SYMBOL_GPL
clk_gate_enable() and clk_gate_disable(), since they do exactly what i
want. I can then build my own clk_ops structure, with my own
unprepare() function. I would probably use DEFINE_CLK_GATE as is, and
then at run time, before calling __clk_init() overwrite the .ops with
my own version.

However, if others have the need for {un}prepare(), it would be good
to have a generic solution.

   Andrew


From b-cousson at ti.com  Mon Mar  5 03:58:37 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 5 Mar 2012 09:58:37 +0100
Subject: [PATCH 11/12] mfd: twl4030-irq: Return twl6030_mmc_card_detect
 IRQ for board setup
In-Reply-To: <4F547721.4010107@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-12-git-send-email-b-cousson@ti.com>
 <20120302181522.GC13967@legolas.emea.dhcp.ti.com> <4F547721.4010107@ti.com>
Message-ID: <4F54803D.3010102@ti.com>

On 3/5/2012 9:19 AM, Rajendra Nayak wrote:
> On Friday 02 March 2012 11:45 PM, Felipe Balbi wrote:
>> Hi,
>>
>> On Fri, Mar 02, 2012 at 05:50:23PM +0100, Benoit Cousson wrote:
>>> Card detect IRQ from the TWL6030 used to be provided to the MMC
>>> controller code using a statically allocated IRQ scheme:
>>>
>>> card_detect_irq = TWL6030_IRQ_BASE + MMCDETECT_INTR_OFFSET;
>>>
>>> This is no longer valid in a SPARSE_IRQ context since there is no more
>>> pre-defined TWL6030_IRQ_BASE.
>>>
>>> Return the proper card detect IRQ value in the
>>> twl6030_mmc_card_detect_config
>>> that will be called from the MMC controller.
>>>
>>> Signed-off-by: Benoit Cousson<b-cousson at ti.com>
>>> Cc: Felipe Balbi<balbi at ti.com>
>>> Cc: Tony Lindgren<tony at atomide.com>
>>> Cc: Rajendra Nayak<rnayak at ti.com>
>>
>> Reviewed-by: Felipe Balbi<balbi at ti.com>
>>
>>> ---
>>> drivers/mfd/twl6030-irq.c | 3 ++-
>>> 1 files changed, 2 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
>>> index a1c7183..4a63de2 100644
>>> --- a/drivers/mfd/twl6030-irq.c
>>> +++ b/drivers/mfd/twl6030-irq.c
>>> @@ -308,7 +308,8 @@ int twl6030_mmc_card_detect_config(void)
>>> ret);
>>> return ret;
>>> }
>>> - return 0;
>>> +
>>> + return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
>>> }
>>> EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
>>
>> At some point this twl6030_mmc_card_detect_config() needs to vanish in
>> favor of a better mechanism. Maybe passing the GPIO number an requiring
>> the driver to request the GPIO, set its direction and use it as IRQ
>> line.
>>
>> the only problem would arise if we end up hooking the Card Detect pin to
>> a real IRQ line, but then we can use a flag to differentiate.
>
> Shouldn't this be hidden from the driver completely if the card detect
> pin is a GPIO or connected to a real IRQ line? And the board/DT handle
> this instead of the driver knowing when to do a gpio_to_irq()?

It work fine for a pure GPIO, but in this case, this is an IRQ handled 
by twl6030. So I'm not sure we have any API for the non-DT case.

DT will clearly help getting rid of such hacks.

Regards,
Benoit


From rnayak at ti.com  Mon Mar  5 04:16:07 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 05 Mar 2012 14:46:07 +0530
Subject: [PATCH 4/4] mmc: omap_hsmmc: Simplify init for twl6030 MMC card
 detect
In-Reply-To: <20120302172251.GJ18901@atomide.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185535.29210.71546.stgit@kaulin.local> <4F50643B.9050500@ti.com>
 <20120302172251.GJ18901@atomide.com>
Message-ID: <4F548457.5050205@ti.com>

On Friday 02 March 2012 10:52 PM, Tony Lindgren wrote:
> BTW, with -rc5, looks like re-inserting omap_hsmmc on omap4 fails
> to detect any cards, and then fails to unload. This works on omap3
> just fine. Any ideas why that would be?

Yeah, looks like thats broken. I am not sure whats going wrong though.
I just enabled CONFIG_MMC_DEBUG and saw these logs below.

Venkat/Balaji, care to look at this one?

# insmod omap_hsmmc.ko
[   43.358398] omap_hsmmc omap_hsmmc.0: context was not lost
[   43.364105] omap_hsmmc omap_hsmmc.0: enabled
[   44.434661] mmc0: clock 0Hz busmode 1 powermode 0 cs 0 Vdd 0 width 0 
timing 0
[   44.442352] omap_hsmmc omap_hsmmc.0: Set clock to 0Hz
[   44.474365] omap_hsmmc omap_hsmmc.0: disabled
[   44.482208] omap_hsmmc omap_hsmmc.4: context was not lost
[   44.482208] omap_hsmmc omap_hsmmc.4: enabled
[   44.546600] omap_hsmmc omap_hsmmc.0: context was not lost
[   44.552276] omap_hsmmc omap_hsmmc.0: enabled
[   44.552276] mmc0: mmc_rescan_try_freq: trying to init card at 400000 Hz
[   44.563720] mmc0: clock 0Hz busmode 2 powermode 1 cs 0 Vdd 18 width 0 
timing 0
[   44.572174] omap_hsmmc omap_hsmmc.0: Set clock to 0Hz
[   44.613800] mmc0: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 18 
width 0 timing 0
[   44.621887] omap_hsmmc omap_hsmmc.0: Set clock to 400000Hz
[   44.735290] mmc0: starting CMD52 arg 00000c00 flags 00000195
[   44.741271] omap_hsmmc omap_hsmmc.0: mmc0: CMD52, argument 0x00000c00
[   45.560241] mmc1: clock 0Hz busmode 1 powermode 0 cs 0 Vdd 0 width 0 
timing 0
[   45.567871] omap_hsmmc omap_hsmmc.4: Set clock to 0Hz
[   45.591491] omap_hsmmc omap_hsmmc.4: disabled
#
#
# rmmod omap_hsmmc
[  607.302307] omap_hsmmc omap_hsmmc.4: context was not lost
[  607.308044] omap_hsmmc omap_hsmmc.4: enabled
[  607.312591] omap_hsmmc omap_hsmmc.4: disabled
[  607.317199] omap_hsmmc omap_hsmmc.4: context was not lost
[  607.322875] omap_hsmmc omap_hsmmc.4: enabled



From richard.zhao at freescale.com  Mon Mar  5 04:22:04 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Mon, 5 Mar 2012 17:22:04 +0800
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <1330763341-3437-4-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
Message-ID: <20120305092202.GC3261@b20223-02.ap.freescale.net>

Hi Mike,

On Sat, Mar 03, 2012 at 12:29:00AM -0800, Mike Turquette wrote:

[snip]

> +static void __clk_disable(struct clk *clk)
> +{
> +	if (!clk)
> +		return;
> +
> +	if (WARN_ON(clk->enable_count == 0))
> +		return;
> +
> +	if (--clk->enable_count > 0)
> +		return;
> +
> +	if (clk->ops->disable)
> +		clk->ops->disable(clk->hw);
> +
> +	if (clk->parent)
> +		__clk_disable(clk->parent);
if __clk_xxx handle NULL clk, we might not need to check parent here?
There're also many places that checks parent below.
> +}
> +
> +/**
> + * clk_disable - gate a clock
> + * @clk: the clk being gated
> + *
> + * clk_disable must not sleep, which differentiates it from clk_unprepare.  In
> + * a simple case, clk_disable can be used instead of clk_unprepare to gate a
> + * clk if the operation is fast and will never sleep.  One example is a
> + * SoC-internal clk which is controlled via simple register writes.  In the
> + * complex case a clk gate operation may require a fast and a slow part.  It is
> + * this reason that clk_unprepare and clk_disable are not mutually exclusive.
> + * In fact clk_disable must be called before clk_unprepare.
> + */
> +void clk_disable(struct clk *clk)
> +{
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&enable_lock, flags);
> +	__clk_disable(clk);
> +	spin_unlock_irqrestore(&enable_lock, flags);
> +}
> +EXPORT_SYMBOL_GPL(clk_disable);
> +
> +static int __clk_enable(struct clk *clk)
> +{
> +	int ret = 0;
> +
> +	if (!clk)
> +		return 0;
> +
> +	if (WARN_ON(clk->prepare_count == 0))
> +		return -ESHUTDOWN;
> +
> +	if (clk->enable_count == 0) {
> +		if (clk->parent)
> +			ret = __clk_enable(clk->parent);
ditto
> +
> +		if (ret)
> +			return ret;
> +
> +		if (clk->ops->enable) {
> +			ret = clk->ops->enable(clk->hw);
> +			if (ret) {
> +				__clk_disable(clk->parent);
it's good case that don't check parent is NULL.
> +				return ret;
> +			}
> +		}
> +	}
> +
> +	clk->enable_count++;
> +	return 0;
> +}
> +
> +/**
> + * clk_enable - ungate a clock
> + * @clk: the clk being ungated
> + *
> + * clk_enable must not sleep, which differentiates it from clk_prepare.  In a
> + * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
> + * if the operation will never sleep.  One example is a SoC-internal clk which
> + * is controlled via simple register writes.  In the complex case a clk ungate
> + * operation may require a fast and a slow part.  It is this reason that
> + * clk_enable and clk_prepare are not mutually exclusive.  In fact clk_prepare
> + * must be called before clk_enable.  Returns 0 on success, -EERROR
> + * otherwise.
> + */
> +int clk_enable(struct clk *clk)
> +{
> +	unsigned long flags;
> +	int ret;
> +
> +	spin_lock_irqsave(&enable_lock, flags);
> +	ret = __clk_enable(clk);
> +	spin_unlock_irqrestore(&enable_lock, flags);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_enable);
> +
> +/**
> + * clk_get_rate - return the rate of clk
> + * @clk: the clk whose rate is being returned
> + *
> + * Simply returns the cached rate of the clk.  Does not query the hardware.  If
> + * clk is NULL then returns -EINVAL.
> + */
> +unsigned long clk_get_rate(struct clk *clk)
> +{
> +	unsigned long rate;
> +
> +	mutex_lock(&prepare_lock);
> +	rate = __clk_get_rate(clk);
> +	mutex_unlock(&prepare_lock);
> +
> +	return rate;
> +}
> +EXPORT_SYMBOL_GPL(clk_get_rate);
> +
> +/**
> + * __clk_round_rate - round the given rate for a clk
> + * @clk: round the rate of this clock
> + *
> + * Caller must hold prepare_lock.  Useful for clk_ops such as .set_rate
> + */
> +unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	if (!clk && !clk->ops->round_rate)
be	         || ?
> +		return -EINVAL;
> +
> +	return clk->ops->round_rate(clk->hw, rate, NULL);
> +}
> +
> +/**
> + * clk_round_rate - round the given rate for a clk
> + * @clk: the clk for which we are rounding a rate
> + * @rate: the rate which is to be rounded
> + *
> + * Takes in a rate as input and rounds it to a rate that the clk can actually
> + * use which is then returned.  If clk doesn't support round_rate operation
> + * then the rate passed in is returned.
> + */
> +long clk_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	unsigned long ret = rate;
> +
> +	mutex_lock(&prepare_lock);
> +	if (clk && clk->ops->round_rate)
> +		ret = __clk_round_rate(clk, rate);
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
If clk is NULL, clk_round_rate and __clk_round_rate return different
values. Do you mean it?
> +}
> +EXPORT_SYMBOL_GPL(clk_round_rate);
> +
> +/**
> + * __clk_notify - call clk notifier chain
> + * @clk: struct clk * that is changing rate
> + * @msg: clk notifier type (see include/linux/clk.h)
> + * @old_rate: old clk rate
> + * @new_rate: new clk rate
> + *
> + * Triggers a notifier call chain on the clk rate-change notification
> + * for 'clk'.  Passes a pointer to the struct clk and the previous
> + * and current rates to the notifier callback.  Intended to be called by
> + * internal clock code only.  Returns NOTIFY_DONE from the last driver
> + * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
> + * a driver returns that.
> + */
> +static int __clk_notify(struct clk *clk, unsigned long msg,
> +		unsigned long old_rate, unsigned long new_rate)
> +{
> +	struct clk_notifier *cn;
> +	struct clk_notifier_data cnd;
> +	int ret = NOTIFY_DONE;
> +
> +	cnd.clk = clk;
> +	cnd.old_rate = old_rate;
> +	cnd.new_rate = new_rate;
> +
> +	list_for_each_entry(cn, &clk_notifier_list, node) {
> +		if (cn->clk == clk) {
> +			ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
> +					&cnd);
> +			break;
> +		}
> +	}
> +
> +	return ret;
> +}
> +
> +/**
> + * __clk_recalc_rates
> + * @clk: first clk in the subtree
> + * @msg: notification type (see include/linux/clk.h)
> + *
> + * Walks the subtree of clks starting with clk and recalculates rates as it
> + * goes.  Note that if a clk does not implement the recalc_rate operation then
> + * propagation of that subtree stops and all of that clks children will not
> + * have their rates updated.
> + *
> + * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
> + * if necessary.
> + *
> + * Caller must hold prepare_lock.
> + */
> +static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
> +{
> +	unsigned long old_rate;
> +	unsigned long parent_rate = 0;
> +	struct hlist_node *tmp;
> +	struct clk *child;
> +
> +	old_rate = clk->rate;
> +
> +	if (clk->parent)
> +		parent_rate = clk->parent->rate;
> +
> +	if (clk->ops->recalc_rate)
> +		clk->rate = clk->ops->recalc_rate(clk->hw, parent_rate);
> +	else
> +		clk->rate = parent_rate;
> +
> +	/*
> +	 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
> +	 * & ABORT_RATE_CHANGE notifiers
> +	 */
> +	if (clk->notifier_count && msg)
> +		__clk_notify(clk, msg, old_rate, clk->rate);
> +
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node)
> +		__clk_recalc_rates(child, msg);
> +}
> +
> +/**
> + * __clk_speculate_rates
> + * @clk: first clk in the subtree
> + * @parent_rate: the "future" rate of clk's parent
> + *
> + * Walks the subtree of clks starting with clk, speculating rates as it
> + * goes and firing off PRE_RATE_CHANGE notifications as necessary.
> + *
> + * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
> + * pre-rate change notifications and returns early if no clks in the
> + * subtree have subscribed to the notifications.
> + *
> + * Caller must hold prepare_lock.
> + */
> +static int __clk_speculate_rates(struct clk *clk, unsigned long parent_rate)
> +{
> +	struct hlist_node *tmp;
> +	struct clk *child;
> +	unsigned long new_rate;
> +	int ret = NOTIFY_DONE;
> +
> +	if (!clk->ops->recalc_rate)
> +		goto out;
When recalc_rate is NULL, it's possible for it and its children to have
notifier too.
> +
> +	new_rate = clk->ops->recalc_rate(clk->hw, parent_rate);
> +
> +	/* abort the rate change if a driver returns NOTIFY_BAD */
> +	if (clk->notifier_count)
> +		ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
> +
> +	if (ret == NOTIFY_BAD)
> +		goto out;
> +
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
> +		ret = __clk_speculate_rates(child, new_rate);
> +		if (ret == NOTIFY_BAD)
> +			break;
> +	}
Tell the notifier that already receive PRE_RATE_CHANGE abort?
> +
> +out:
> +	return ret;
> +}
> +
> +/**
> + * DOC: Using the CLK_SET_RATE_PARENT flag
> + *
> + * __clk_set_rate changes the child's rate before the parent's to more
> + * easily handle failure conditions.
> + *
> + * This means clk might run out of spec for a short time if its rate is
> + * increased before the parent's rate is updated.
> + *
> + * To prevent this consider setting the CLK_SET_RATE_GATE flag on any
> + * clk where you also set the CLK_SET_RATE_PARENT flag
> + *
> + * PRE_RATE_CHANGE notifications are supposed to stack as a rate change
> + * request propagates up the clk tree.  This reflects the different
> + * rates that a downstream clk might experience if left enabled while
> + * upstream parents change their rates.
> + */
> +static struct clk *__clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	struct clk *fail_clk = NULL;
> +	int ret = NOTIFY_DONE;
> +	unsigned long old_rate = clk->rate;
> +	unsigned long new_rate;
> +	unsigned long parent_old_rate;
> +	unsigned long parent_new_rate = 0;
> +	struct clk *child;
> +	struct hlist_node *tmp;
> +
> +	/* bail early if we can't change rate while clk is enabled */
> +	if ((clk->flags & CLK_SET_RATE_GATE) && clk->enable_count)
> +		return clk;
> +
> +	/* find the new rate and see if parent rate should change too */
> +	WARN_ON(!clk->ops->round_rate);
> +
> +	new_rate = clk->ops->round_rate(clk->hw, rate, &parent_new_rate);
> +
> +	/* NOTE: pre-rate change notifications will stack */
> +	if (clk->notifier_count)
> +		ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);

if ((clk->flags & CLK_SET_RATE_PARENT) && parent_new_rate)
	dowstream notify from parent clk?
> +
> +	if (ret == NOTIFY_BAD)
> +		return clk;
> +
> +	/* speculate rate changes down the tree */
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
> +		ret = __clk_speculate_rates(child, new_rate);
> +		if (ret == NOTIFY_BAD)
roll back?
> +			return clk;
> +	}
> +
> +	/* change the rate of this clk */
> +	if (clk->ops->set_rate)
If set_rate is NULL, it can fail at the beginning of this function.
> +		ret = clk->ops->set_rate(clk->hw, new_rate);
> +
> +	if (ret == NOTIFY_BAD)
you mean to check set_rate fail? Notify ABORT_RATE_CHANGE?
> +		return clk;
> +
> +	/*
> +	 * change the rate of the parent clk if necessary
> +	 *
> +	 * hitting the nested 'if' path implies we have hit a .set_rate
> +	 * failure somewhere upstream while propagating __clk_set_rate
> +	 * up the clk tree.  roll back the clk rates one by one and
> +	 * return the pointer to the clk that failed.  clk_set_rate will
> +	 * use the pointer to propagate a rate-change abort notifier
> +	 * from the "highest" point.
> +	 */
> +	if ((clk->flags & CLK_SET_RATE_PARENT) && parent_new_rate) {
> +		parent_old_rate = clk->parent->rate;
> +		fail_clk = __clk_set_rate(clk->parent, parent_new_rate);
> +
> +		/* roll back changes if parent rate change failed */
> +		if (fail_clk) {
> +			pr_warn("%s: failed to set parent %s rate to %lu\n",
> +					__func__, fail_clk->name,
> +					parent_new_rate);
> +
> +			/*
> +			 * Send PRE_RATE_CHANGE notifiers down the tree
> +			 * again, since we're rolling back the rate
> +			 * changes due to the abort.
> +			 *
> +			 * Ignore any NOTIFY_BAD's since this *is* the
> +			 * exception handler.
> +			 *
> +			 * NOTE: pre-rate change notifications will stack
> +			 */
> +			__clk_speculate_rates(clk, clk->parent->rate);
IMHO, driver can not be happy to receive multiple PRE_RATE_CHANGE.
Notify ABORT_RATE_CHANGE?

> +
> +			clk->ops->set_rate(clk->hw, old_rate);
> +		}
> +		return fail_clk;
> +	}
> +
> +	/*
> +	 * set clk's rate & recalculate the rates of clk's children
> +	 *
> +	 * hitting this path implies we have successfully finished
> +	 * propagating recursive calls to __clk_set_rate up the clk tree
> +	 * (if necessary) and it is safe to propagate __clk_recalc_rates
> +	 * and post-rate change notifiers down the clk tree from this
> +	 * point.
> +	 */
> +	__clk_recalc_rates(clk, POST_RATE_CHANGE);
> +
> +	return NULL;
> +}
> +
> +/**
> + * clk_set_rate - specify a new rate for clk
> + * @clk: the clk whose rate is being changed
> + * @rate: the new rate for clk
> + *
> + * In the simplest case clk_set_rate will only change the rate of clk.
> + *
> + * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call
> + * will fail; only when the clk is disabled will it be able to change
> + * its rate.
> + *
> + * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to
> + * recursively propagate up to clk's parent; whether or not this happens
> + * depends on the outcome of clk's .round_rate implementation.  If
> + * *parent_rate is 0 after calling .round_rate then upstream parent
> + * propagation is ignored.  If *parent_rate comes back with a new rate
> + * for clk's parent then we propagate up to clk's parent and set it's
> + * rate.  Upward propagation will continue until either a clk does not
> + * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting
> + * changes to clk's parent_rate.  If there is a failure during upstream
> + * propagation then clk_set_rate will unwind and restore each clk's rate
> + * that had been successfully changed.  Afterwards a rate change abort
> + * notification will be propagated downstream, starting from the clk
> + * that failed.
> + *
> + * At the end of all of the rate setting, clk_set_rate internally calls
> + * __clk_recalc_rates and propagates the rate changes downstream,
> + * starting from the highest clk whose rate was changed.  This has the
> + * added benefit of propagating post-rate change notifiers.
> + *
> + * Note that while post-rate change and rate change abort notifications
> + * are guaranteed to be sent to a clk only once per call to
> + * clk_set_rate, pre-change notifications will be sent for every clk
> + * whose rate is changed.  Stacking pre-change notifications is noisy
> + * for the drivers subscribed to them, but this allows drivers to react
> + * to intermediate clk rate changes up until the point where the final
> + * rate is achieved at the end of upstream propagation.
> + *
> + * Returns 0 on success, -EERROR otherwise.
> + */
> +int clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	struct clk *fail_clk;
> +	int ret = 0;
> +
> +	/* prevent racing with updates to the clock topology */
> +	mutex_lock(&prepare_lock);
> +
> +	/* bail early if nothing to do */
> +	if (rate == clk->rate)
> +		goto out;
> +
> +	fail_clk = __clk_set_rate(clk, rate);
> +	if (fail_clk) {
> +		pr_warn("%s: failed to set %s rate\n", __func__,
> +				fail_clk->name);
> +		__clk_recalc_rates(clk, ABORT_RATE_CHANGE);
It might need to begin from parent clk. move it to __clk_set_rate?
> +		ret = -EIO;
> +	}
> +
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_set_rate);
> +
> +/**
> + * clk_get_parent - return the parent of a clk
> + * @clk: the clk whose parent gets returned
> + *
> + * Simply returns clk->parent.  Returns NULL if clk is NULL.
> + */
> +struct clk *clk_get_parent(struct clk *clk)
> +{
> +	struct clk *parent;
> +
> +	mutex_lock(&prepare_lock);
> +	parent = __clk_get_parent(clk);
> +	mutex_unlock(&prepare_lock);
> +
> +	return parent;
> +}
> +EXPORT_SYMBOL_GPL(clk_get_parent);
> +
> +/*
> + * .get_parent is mandatory for clocks with multiple possible parents.  It is
> + * optional for single-parent clocks.  Always call .get_parent if it is
> + * available and WARN if it is missing for multi-parent clocks.
> + *
> + * For single-parent clocks without .get_parent, first check to see if the
> + * .parents array exists, and if so use it to avoid an expensive tree
> + * traversal.  If .parents does not exist then walk the tree with __clk_lookup.
> + */
> +static struct clk *__clk_init_parent(struct clk *clk)
> +{
> +	struct clk *ret = NULL;
> +	u8 index;
> +
> +	/* handle the trivial cases */
> +
> +	if (!clk->num_parents)
> +		goto out;
> +
> +	if (clk->num_parents == 1) {
> +		if (IS_ERR_OR_NULL(clk->parent))
> +			ret = clk->parent = __clk_lookup(clk->parent_names[0]);
> +		ret = clk->parent;
> +		goto out;
> +	}
> +
> +	if (!clk->ops->get_parent) {
> +		WARN(!clk->ops->get_parent,
> +			"%s: multi-parent clocks must implement .get_parent\n",
> +			__func__);
> +		goto out;
> +	};
> +
> +	/*
> +	 * Do our best to cache parent clocks in clk->parents.  This prevents
> +	 * unnecessary and expensive calls to __clk_lookup.  We don't set
> +	 * clk->parent here; that is done by the calling function
> +	 */
> +
> +	index = clk->ops->get_parent(clk->hw);
> +
> +	if (!clk->parents)
> +		clk->parents =
> +			kmalloc((sizeof(struct clk*) * clk->num_parents),
> +					GFP_KERNEL);
> +
> +	if (!clk->parents)
> +		ret = __clk_lookup(clk->parent_names[index]);
> +	else if (!clk->parents[index])
> +		ret = clk->parents[index] =
> +			__clk_lookup(clk->parent_names[index]);
> +	else
> +		ret = clk->parents[index];
> +
> +out:
> +	return ret;
> +}
> +
> +void __clk_reparent(struct clk *clk, struct clk *new_parent)
> +{
> +#ifdef CONFIG_COMMON_CLK_DEBUG
> +	struct dentry *d;
> +	struct dentry *new_parent_d;
> +#endif
> +
> +	if (!clk || !new_parent)
> +		return;
> +
> +	hlist_del(&clk->child_node);
> +
> +	if (new_parent)
> +		hlist_add_head(&clk->child_node, &new_parent->children);
> +	else
> +		hlist_add_head(&clk->child_node, &clk_orphan_list);
> +
> +#ifdef CONFIG_COMMON_CLK_DEBUG
> +	if (!inited)
> +		goto out;
> +
> +	if (new_parent)
> +		new_parent_d = new_parent->dentry;
> +	else
> +		new_parent_d = orphandir;
> +
> +	d = debugfs_rename(clk->dentry->d_parent, clk->dentry,
> +			new_parent_d, clk->name);
> +	if (d)
> +		clk->dentry = d;
> +	else
> +		pr_debug("%s: failed to rename debugfs entry for %s\n",
> +				__func__, clk->name);
> +out:
> +#endif
> +
> +	clk->parent = new_parent;
> +
> +	__clk_recalc_rates(clk, POST_RATE_CHANGE);
> +}
> +
> +static int __clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> +	struct clk *old_parent;
> +	unsigned long flags;
> +	int ret = -EINVAL;
> +	u8 i;
> +
> +	old_parent = clk->parent;
> +
> +	/* find index of new parent clock using cached parent ptrs */
> +	for (i = 0; i < clk->num_parents; i++)
> +		if (clk->parents[i] == parent)
> +			break;
> +
> +	/*
> +	 * find index of new parent clock using string name comparison
> +	 * also try to cache the parent to avoid future calls to __clk_lookup
> +	 */
> +	if (i == clk->num_parents)
> +		for (i = 0; i < clk->num_parents; i++)
> +			if (!strcmp(clk->parent_names[i], parent->name)) {
> +				clk->parents[i] = __clk_lookup(parent->name);
> +				break;
> +			}
> +
> +	if (i == clk->num_parents) {
> +		pr_debug("%s: clock %s is not a possible parent of clock %s\n",
> +				__func__, parent->name, clk->name);
> +		goto out;
> +	}
> +
> +	/* migrate prepare and enable */
> +	if (clk->prepare_count)
> +		__clk_prepare(parent);
> +
> +	/* FIXME replace with clk_is_enabled(clk) someday */
> +	spin_lock_irqsave(&enable_lock, flags);
> +	if (clk->enable_count)
> +		__clk_enable(parent);
> +	spin_unlock_irqrestore(&enable_lock, flags);
> +
> +	/* change clock input source */
> +	ret = clk->ops->set_parent(clk->hw, i);
> +
> +	/* clean up old prepare and enable */
> +	spin_lock_irqsave(&enable_lock, flags);
> +	if (clk->enable_count)
> +		__clk_disable(old_parent);
> +	spin_unlock_irqrestore(&enable_lock, flags);
> +
> +	if (clk->prepare_count)
> +		__clk_unprepare(old_parent);
> +
> +out:
> +	return ret;
> +}
> +
> +/**
> + * clk_set_parent - switch the parent of a mux clk
> + * @clk: the mux clk whose input we are switching
> + * @parent: the new input to clk
> + *
> + * Re-parent clk to use parent as it's new input source.  If clk has the
> + * CLK_SET_PARENT_GATE flag set then clk must be gated for this
> + * operation to succeed.  After successfully changing clk's parent
> + * clk_set_parent will update the clk topology, sysfs topology and
> + * propagate rate recalculation via __clk_recalc_rates.  Returns 0 on
> + * success, -EERROR otherwise.
> + */
> +int clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> +	int ret = 0;
> +
> +	if (!clk || !clk->ops)
> +		return -EINVAL;
> +
> +	if (!clk->ops->set_parent)
> +		return -ENOSYS;
> +
> +	/* prevent racing with updates to the clock topology */
> +	mutex_lock(&prepare_lock);
> +
> +	if (clk->parent == parent)
> +		goto out;
> +
> +	/* propagate PRE_RATE_CHANGE notifications */
> +	if (clk->notifier_count)
> +		ret = __clk_speculate_rates(clk, parent->rate);
> +
> +	/* abort if a driver objects */
> +	if (ret == NOTIFY_STOP)
> +		goto out;
> +
> +	/* only re-parent if the clock is not in use */
> +	if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count)
> +		ret = -EBUSY;
> +	else
> +		ret = __clk_set_parent(clk, parent);
> +
> +	/* propagate ABORT_RATE_CHANGE if .set_parent failed */
> +	if (ret) {
> +		__clk_recalc_rates(clk, ABORT_RATE_CHANGE);
> +		goto out;
> +	}
> +
> +	/* propagate rate recalculation downstream */
> +	__clk_reparent(clk, parent);
> +
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_set_parent);
> +
> +/**
> + * __clk_init - initialize the data structures in a struct clk
> + * @dev:	device initializing this clk, placeholder for now
> + * @clk:	clk being initialized
> + *
> + * Initializes the lists in struct clk, queries the hardware for the
> + * parent and rate and sets them both.
> + *
> + * Any struct clk passed into __clk_init must have the following members
> + * populated:
> + * 	.name
> + * 	.ops
> + * 	.hw
> + * 	.parent_names
> + * 	.num_parents
> + * 	.flags
> + *
> + * Essentially, everything that would normally be passed into clk_register is
> + * assumed to be initialized already in __clk_init.  The other members may be
> + * populated, but are optional.
> + *
> + * __clk_init is only exposed via clk-private.h and is intended for use with
> + * very large numbers of clocks that need to be statically initialized.  It is
> + * a layering violation to include clk-private.h from any code which implements
> + * a clock's .ops; as such any statically initialized clock data MUST be in a
> + * separate C file from the logic that implements it's operations.
> + */
> +void __clk_init(struct device *dev, struct clk *clk)
> +{
> +	int i;
> +	struct clk *orphan;
> +	struct hlist_node *tmp;
> +
> +	if (!clk)
> +		return;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	/* check to see if a clock with this name is already registered */
> +	if (__clk_lookup(clk->name))
> +		goto out;
> +
> +	/*
> +	 * Allocate an array of struct clk *'s to avoid unnecessary string
> +	 * look-ups of clk's possible parents.  This can fail for clocks passed
> +	 * in to clk_init during early boot; thus any access to clk->parents[]
> +	 * must always check for a NULL pointer and try to populate it if
> +	 * necessary.
> +	 *
> +	 * If clk->parents is not NULL we skip this entire block.  This allows
> +	 * for clock drivers to statically initialize clk->parents.
> +	 */
> +	if (clk->num_parents && !clk->parents) {
> +		clk->parents = kmalloc((sizeof(struct clk*) * clk->num_parents),
> +				GFP_KERNEL);
> +		/*
> +		 * __clk_lookup returns NULL for parents that have not been
> +		 * clk_init'd; thus any access to clk->parents[] must check
> +		 * for a NULL pointer.  We can always perform lazy lookups for
> +		 * missing parents later on.
> +		 */
> +		if (clk->parents)
> +			for (i = 0; i < clk->num_parents; i++)
> +				clk->parents[i] =
> +					__clk_lookup(clk->parent_names[i]);
> +	}
> +
> +	clk->parent = __clk_init_parent(clk);
> +
> +	/*
> +	 * Populate clk->parent if parent has already been __clk_init'd.  If
> +	 * parent has not yet been __clk_init'd then place clk in the orphan
> +	 * list.  If clk has set the CLK_IS_ROOT flag then place it in the root
> +	 * clk list.
> +	 *
> +	 * Every time a new clk is clk_init'd then we walk the list of orphan
> +	 * clocks and re-parent any that are children of the clock currently
> +	 * being clk_init'd.
> +	 */
> +	if (clk->parent)
> +		hlist_add_head(&clk->child_node,
> +				&clk->parent->children);
> +	else if (clk->flags & CLK_IS_ROOT)
> +		hlist_add_head(&clk->child_node, &clk_root_list);
> +	else
> +		hlist_add_head(&clk->child_node, &clk_orphan_list);
> +
> +	/*
> +	 * Set clk's rate.  The preferred method is to use .recalc_rate.  For
> +	 * simple clocks and lazy developers the default fallback is to use the
> +	 * parent's rate.  If a clock doesn't have a parent (or is orphaned)
> +	 * then rate is set to zero.
> +	 */
> +	if (clk->ops->recalc_rate)
> +		clk->rate = clk->ops->recalc_rate(clk->hw,
> +				__clk_get_rate(clk->parent));
> +	else if (clk->parent)
> +		clk->rate = clk->parent->rate;
> +	else
> +		clk->rate = 0;
> +
> +	/*
> +	 * walk the list of orphan clocks and reparent any that are children of
> +	 * this clock
> +	 */
> +	hlist_for_each_entry(orphan, tmp, &clk_orphan_list, child_node)
> +		__clk_reparent(orphan, __clk_init_parent(orphan));
check whether orphan->parent is the value of  __clk_init_parent(orphan)
before reparent?
> +
> +	/*
> +	 * optional platform-specific magic
> +	 *
> +	 * The .init callback is not used by any of the basic clock types, but
> +	 * exists for weird hardware that must perform initialization magic.
> +	 * Please consider other ways of solving initialization problems before
> +	 * using this callback, as it's use is discouraged.
> +	 */
> +	if (clk->ops->init)
> +		clk->ops->init(clk->hw);
> +
> +	clk_debug_register(clk);
> +
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return;
> +}
> +
> +/**
> + * clk_register - allocate a new clock, register it and return an opaque cookie
> + * @dev: device that is registering this clock
> + * @name: clock name
> + * @ops: operations this clock supports
> + * @hw: link to hardware-specific clock data
> + * @parent_names: array of string names for all possible parents
> + * @num_parents: number of possible parents
> + * @flags: framework-level hints and quirks
> + *
> + * clk_register is the primary interface for populating the clock tree with new
> + * clock nodes.  It returns a pointer to the newly allocated struct clk which
> + * cannot be dereferenced by driver code but may be used in conjuction with the
> + * rest of the clock API.
> + */
> +struct clk *clk_register(struct device *dev, const char *name,
> +		const struct clk_ops *ops, struct clk_hw *hw,
> +		char **parent_names, u8 num_parents, unsigned long flags)
> +{
> +	struct clk *clk;
> +
> +	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
> +	if (!clk)
> +		return NULL;
> +
> +	clk->name = name;
> +	clk->ops = ops;
> +	clk->hw = hw;
> +	clk->flags = flags;
> +	clk->parent_names = parent_names;
> +	clk->num_parents = num_parents;
> +	hw->clk = clk;
> +
> +	__clk_init(dev, clk);
> +
> +	return clk;
> +}
> +EXPORT_SYMBOL_GPL(clk_register);
> +
> +/***        clk rate change notifiers        ***/
> +
> +/**
> + * clk_notifier_register - add a clk rate change notifier
> + * @clk: struct clk * to watch
> + * @nb: struct notifier_block * with callback info
> + *
> + * Request notification when clk's rate changes.  This uses an SRCU
> + * notifier because we want it to block and notifier unregistrations are
> + * uncommon.  The callbacks associated with the notifier must not
> + * re-enter into the clk framework by calling any top-level clk APIs;
> + * this will cause a nested prepare_lock mutex.
> + *
> + * Pre-change notifier callbacks will be passed the current, pre-change
> + * rate of the clk via struct clk_notifier_data.old_rate.  The new,
> + * post-change rate of the clk is passed via struct
> + * clk_notifier.new_rate.
clk_notifier_data ?
> + *
> + * Post-change notifiers will pass the now-current, post-change rate of
> + * the clk in both struct clk_notifier_data.old_rate and struct
> + * clk_notifier_data.new_rate.
> + *
> + * Abort-change notifiers are effectively the opposite of pre-change
> + * notifiers: the original pre-change clk rate is passed in via struct
> + * clk_notifier_data.new_rate and the failed post-change rate is passed
> + * in via struct clk_notifier_data.old_rate.
> + *
> + * clk_notifier_register() must be called from non-atomic context.
> + * Returns -EINVAL if called with null arguments, -ENOMEM upon
> + * allocation failure; otherwise, passes along the return value of
> + * srcu_notifier_chain_register().
> + */
> +int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
> +{
> +	struct clk_notifier *cn;
> +	int ret = -ENOMEM;
> +
> +	if (!clk || !nb)
> +		return -EINVAL;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	/* search the list of notifiers for this clk */
> +	list_for_each_entry(cn, &clk_notifier_list, node)
> +		if (cn->clk == clk)
> +			break;
> +
> +	/* if clk wasn't in the notifier list, allocate new clk_notifier */
> +	if (cn->clk != clk) {
> +		cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
> +		if (!cn)
> +			goto out;
> +
> +		cn->clk = clk;
> +		srcu_init_notifier_head(&cn->notifier_head);
> +
> +		list_add(&cn->node, &clk_notifier_list);
> +	}
why not embedd notifier_head to struct clk?
> +
> +	ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
> +
> +	clk->notifier_count++;
> +
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_notifier_register);
> +
> +/**
> + * clk_notifier_unregister - remove a clk rate change notifier
> + * @clk: struct clk *
> + * @nb: struct notifier_block * with callback info
> + *
> + * Request no further notification for changes to 'clk' and frees memory
> + * allocated in clk_notifier_register.
> + *
> + * Returns -EINVAL if called with null arguments; otherwise, passes
> + * along the return value of srcu_notifier_chain_unregister().
> + */
> +int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
> +{
> +	struct clk_notifier *cn = NULL;
> +	int ret = -EINVAL;
> +
> +	if (!clk || !nb)
> +		return -EINVAL;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	list_for_each_entry(cn, &clk_notifier_list, node)
> +		if (cn->clk == clk)
> +			break;
> +
> +	if (cn->clk == clk) {
> +		ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
> +
> +		clk->notifier_count--;
> +
> +		/* XXX the notifier code should handle this better */
> +		if (!cn->notifier_head.head) {
> +			srcu_cleanup_notifier_head(&cn->notifier_head);
> +			kfree(cn);
> +		}
> +
> +	} else {
> +		ret = -ENOENT;
> +	}
> +
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_notifier_unregister);
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> new file mode 100644
> index 0000000..33bf6a7
> --- /dev/null
> +++ b/include/linux/clk-private.h
> @@ -0,0 +1,68 @@
> +/*
> + *  linux/include/linux/clk-private.h
> + *
> + *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr at canonical.com>
> + *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef __LINUX_CLK_PRIVATE_H
> +#define __LINUX_CLK_PRIVATE_H
> +
> +#include <linux/clk-provider.h>
> +#include <linux/list.h>
> +
> +/*
> + * WARNING: Do not include clk-private.h from any file that implements struct
> + * clk_ops.  Doing so is a layering violation!
> + *
> + * This header exists only to allow for statically initialized clock data.  Any
> + * static clock data must be defined in a separate file from the logic that
> + * implements the clock operations for that same data.
> + */
> +
> +#ifdef CONFIG_COMMON_CLK
> +
> +struct clk {
> +	const char		*name;
> +	const struct clk_ops	*ops;
> +	struct clk_hw		*hw;
> +	struct clk		*parent;
> +	char			**parent_names;
> +	struct clk		**parents;
> +	u8			num_parents;
> +	unsigned long		rate;
> +	unsigned long		flags;
> +	unsigned int		enable_count;
> +	unsigned int		prepare_count;
> +	struct hlist_head	children;
> +	struct hlist_node	child_node;
> +	unsigned int		notifier_count;
> +#ifdef CONFIG_COMMON_CLK_DEBUG
> +	struct dentry		*dentry;
> +#endif
> +};
> +
> +/**
> + * __clk_init - initialize the data structures in a struct clk
> + * @dev:	device initializing this clk, placeholder for now
> + * @clk:	clk being initialized
> + *
> + * Initializes the lists in struct clk, queries the hardware for the
> + * parent and rate and sets them both.
Add: clocks that call __clk_init don't need to call clk_register.
> + *
> + * Any struct clk passed into __clk_init must have the following members
> + * populated:
> + * 	.name
> + * 	.ops
> + * 	.hw
> + * 	.parent_names
> + * 	.num_parents
> + * 	.flags
> + */
> +void __clk_init(struct device *dev, struct clk *clk);
> +
> +#endif /* CONFIG_COMMON_CLK */
> +#endif /* CLK_PRIVATE_H */
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> new file mode 100644
> index 0000000..c9ed582
> --- /dev/null
> +++ b/include/linux/clk-provider.h
> @@ -0,0 +1,169 @@
> +/*
> + *  linux/include/linux/clk-provider.h
> + *
> + *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr at canonical.com>
> + *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef __LINUX_CLK_PROVIDER_H
> +#define __LINUX_CLK_PROVIDER_H
> +
> +#include <linux/clk.h>
> +
> +#ifdef CONFIG_COMMON_CLK
> +
> +/**
> + * struct clk_hw - handle for traversing from a struct clk to its corresponding
> + * hardware-specific structure.  struct clk_hw should be declared within struct
> + * clk_foo and then referenced by the struct clk instance that uses struct
> + * clk_foo's clk_ops
> + *
> + * clk: pointer to the struct clk instance that points back to this struct
> + * clk_hw instance
> + */
> +struct clk_hw {
> +	struct clk *clk;
> +};
> +
> +/*
> + * flags used across common struct clk.  these flags should only affect the
> + * top-level framework.  custom flags for dealing with hardware specifics
> + * belong in struct clk_foo
> + */
> +#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
> +#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
> +#define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
> +#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
I can not find anywhere check it.
> +#define CLK_IS_ROOT		BIT(4) /* root clk, has no parent */
> +
> +/**
> + * struct clk_ops -  Callback operations for hardware clocks; these are to
> + * be provided by the clock implementation, and will be called by drivers
> + * through the clk_* api.
> + *
> + * @prepare:	Prepare the clock for enabling. This must not return until
> + * 		the clock is fully prepared, and it's safe to call clk_enable.
> + * 		This callback is intended to allow clock implementations to
> + * 		do any initialisation that may sleep. Called with
> + * 		prepare_lock held.
> + *
> + * @unprepare:	Release the clock from its prepared state. This will typically
> + * 		undo any work done in the @prepare callback. Called with
> + * 		prepare_lock held.
> + *
> + * @enable:	Enable the clock atomically. This must not return until the
> + * 		clock is generating a valid clock signal, usable by consumer
> + * 		devices. Called with enable_lock held. This function must not
> + * 		sleep.
> + *
> + * @disable:	Disable the clock atomically. Called with enable_lock held.
> + * 		This function must not sleep.
> + *
> + * @recalc_rate	Recalculate the rate of this clock, by quering hardware.  The
> + * 		parent rate is an input parameter.  It is up to the caller to
> + * 		insure that the prepare_mutex is held across this call.
> + * 		Returns the calculated rate.  Optional, but recommended - if
> + * 		this op is not set then clock rate will be initialized to 0.
> + *
> + * @round_rate:	Given a target rate as input, returns the closest rate actually
> + * 		supported by the clock.
> + *
> + * @get_parent:	Queries the hardware to determine the parent of a clock.  The
> + * 		return value is a u8 which specifies the index corresponding to
> + * 		the parent clock.  This index can be applied to either the
> + * 		.parent_names or .parents arrays.  In short, this function
> + * 		translates the parent value read from hardware into an array
> + * 		index.  Currently only called when the clock is initialized by
> + * 		__clk_init.  This callback is mandatory for clocks with
> + * 		multiple parents.  It is optional (and unnecessary) for clocks
> + * 		with 0 or 1 parents.
> + *
> + * @set_parent:	Change the input source of this clock; for clocks with multiple
> + * 		possible parents specify a new parent by passing in the index
> + * 		as a u8 corresponding to the parent in either the .parent_names
> + * 		or .parents arrays.  This function in affect translates an
> + * 		array index into the value programmed into the hardware.
> + * 		Returns 0 on success, -EERROR otherwise.
> + *
> + * @set_rate:	Change the rate of this clock. If this callback returns
> + * 		CLK_SET_RATE_PARENT, the rate change will be propagated to the
> + * 		parent clock (which may propagate again if the parent clock
> + * 		also sets this flag). The requested rate of the parent is
> + * 		passed back from the callback in the second 'unsigned long *'
> + * 		argument.  Note that it is up to the hardware clock's set_rate
> + * 		implementation to insure that clocks do not run out of spec
> + * 		when propgating the call to set_rate up to the parent.  One way
> + * 		to do this is to gate the clock (via clk_disable and/or
> + * 		clk_unprepare) before calling clk_set_rate, then ungating it
> + * 		afterward.  If your clock also has the CLK_GATE_SET_RATE flag
> + * 		set then this will insure safety.  Returns 0 on success,
> + * 		-EERROR otherwise.
> + *
> + * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
> + * implementations to split any work between atomic (enable) and sleepable
> + * (prepare) contexts.  If enabling a clock requires code that might sleep,
> + * this must be done in clk_prepare.  Clock enable code that will never be
> + * called in a sleepable context may be implement in clk_enable.
> + *
> + * Typically, drivers will call clk_prepare when a clock may be needed later
> + * (eg. when a device is opened), and clk_enable when the clock is actually
> + * required (eg. from an interrupt). Note that clk_prepare MUST have been
> + * called before clk_enable.
> + */
> +struct clk_ops {
> +	int		(*prepare)(struct clk_hw *hw);
> +	void		(*unprepare)(struct clk_hw *hw);
> +	int		(*enable)(struct clk_hw *hw);
> +	void		(*disable)(struct clk_hw *hw);
> +	unsigned long	(*recalc_rate)(struct clk_hw *hw,
> +					unsigned long parent_rate);
> +	long		(*round_rate)(struct clk_hw *hw, unsigned long,
> +					unsigned long *);
> +	int		(*set_parent)(struct clk_hw *hw, u8 index);
> +	u8		(*get_parent)(struct clk_hw *hw);
> +	int		(*set_rate)(struct clk_hw *hw, unsigned long);
> +	void		(*init)(struct clk_hw *hw);
> +};
> +
> +
> +/**
> + * clk_register - allocate a new clock, register it and return an opaque cookie
> + * @dev: device that is registering this clock
> + * @name: clock name
> + * @ops: operations this clock supports
> + * @hw: link to hardware-specific clock data
> + * @parent_names: array of string names for all possible parents
> + * @num_parents: number of possible parents
> + * @flags: framework-level hints and quirks
> + *
> + * clk_register is the primary interface for populating the clock tree with new
> + * clock nodes.  It returns a pointer to the newly allocated struct clk which
> + * cannot be dereferenced by driver code but may be used in conjuction with the
> + * rest of the clock API.
> + */
> +struct clk *clk_register(struct device *dev, const char *name,
> +		const struct clk_ops *ops, struct clk_hw *hw,
> +		char **parent_names, u8 num_parents, unsigned long flags);
> +
> +/* helper functions */
> +const char *__clk_get_name(struct clk *clk);
> +struct clk_hw *__clk_get_hw(struct clk *clk);
> +u8 __clk_get_num_parents(struct clk *clk);
> +struct clk *__clk_get_parent(struct clk *clk);
> +unsigned long __clk_get_rate(struct clk *clk);
> +unsigned long __clk_get_flags(struct clk *clk);
> +struct clk *__clk_lookup(const char *name);
> +
> +/*
> + * FIXME clock api without lock protection
> + */
> +int __clk_prepare(struct clk *clk);
> +void __clk_unprepare(struct clk *clk);
> +void __clk_reparent(struct clk *clk, struct clk *new_parent);
It only notify POST_RATE_CHANGE without PRE_RATE_CHANGE. Mabe we need
to move PRE_RATE_CHANGE to __clk_reparent too?
> +unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
why're there no enable/disable functions?
> +
> +#endif /* CONFIG_COMMON_CLK */
> +#endif /* CLK_PROVIDER_H */
> diff --git a/include/linux/clk.h b/include/linux/clk.h
> index b9d46fa..b025272 100644
> --- a/include/linux/clk.h
> +++ b/include/linux/clk.h
> @@ -3,6 +3,7 @@
>   *
>   *  Copyright (C) 2004 ARM Limited.
>   *  Written by Deep Blue Solutions Limited.
> + *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
> @@ -12,18 +13,75 @@
>  #define __LINUX_CLK_H
>  
>  #include <linux/kernel.h>
> +#include <linux/notifier.h>
>  
>  struct device;
>  
> -/*
> - * The base API.
> +struct clk;
> +
> +#ifdef CONFIG_COMMON_CLK
> +
> +/**
> + * DOC: clk notifier callback types
> + *
> + * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
> + *     to indicate that the rate change will proceed.  Drivers must
> + *     immediately terminate any operations that will be affected by the
> + *     rate change.  Callbacks may either return NOTIFY_DONE or
> + *     NOTIFY_STOP.
> + *
> + * ABORT_RATE_CHANGE: called if the rate change failed for some reason
> + *     after PRE_RATE_CHANGE.  In this case, all registered notifiers on
> + *     the clk will be called with ABORT_RATE_CHANGE. Callbacks must
> + *     always return NOTIFY_DONE.
> + *
> + * POST_RATE_CHANGE - called after the clk rate change has successfully
> + *     completed.  Callbacks must always return NOTIFY_DONE.
> + *
>   */
> +#define PRE_RATE_CHANGE			BIT(0)
> +#define POST_RATE_CHANGE		BIT(1)
> +#define ABORT_RATE_CHANGE		BIT(2)
>  
> +/**
> + * struct clk_notifier - associate a clk with a notifier
> + * @clk: struct clk * to associate the notifier with
> + * @notifier_head: a blocking_notifier_head for this clk
> + * @node: linked list pointers
> + *
> + * A list of struct clk_notifier is maintained by the notifier code.
> + * An entry is created whenever code registers the first notifier on a
> + * particular @clk.  Future notifiers on that @clk are added to the
> + * @notifier_head.
> + */
> +struct clk_notifier {
> +	struct clk			*clk;
> +	struct srcu_notifier_head	notifier_head;
> +	struct list_head		node;
> +};
>  
> -/*
> - * struct clk - an machine class defined object / cookie.
> +/**
> + * struct clk_notifier_data - rate data to pass to the notifier callback
> + * @clk: struct clk * being changed
> + * @old_rate: previous rate of this clk
> + * @new_rate: new rate of this clk
> + *
> + * For a pre-notifier, old_rate is the clk's rate before this rate
> + * change, and new_rate is what the rate will be in the future.  For a
> + * post-notifier, old_rate and new_rate are both set to the clk's
> + * current rate (this was done to optimize the implementation).
>   */
> -struct clk;
> +struct clk_notifier_data {
> +	struct clk		*clk;
> +	unsigned long		old_rate;
> +	unsigned long		new_rate;
> +};
> +
> +int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
> +
> +int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
> +
> +#endif /* !CONFIG_COMMON_CLK */
>  
>  /**
>   * clk_get - lookup and obtain a reference to a clock producer.

Thanks
Richard



From s.hauer at pengutronix.de  Mon Mar  5 04:29:48 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 5 Mar 2012 10:29:48 +0100
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <20120305084823.GD24858@lunn.ch>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
 <20120304174229.GD11546@lunn.ch>
 <CAJOA=zNWN6L+-YEkNKoQnjnrrswNpCBmtnhKBm04HekWP46i5w@mail.gmail.com>
 <20120305084823.GD24858@lunn.ch>
Message-ID: <20120305092948.GV3852@pengutronix.de>

On Mon, Mar 05, 2012 at 09:48:23AM +0100, Andrew Lunn wrote:
> On Sun, Mar 04, 2012 at 04:30:08PM -0800, Turquette, Mike wrote:
> > On Sun, Mar 4, 2012 at 9:42 AM, Andrew Lunn <andrew at lunn.ch> wrote:
> > > On Sat, Mar 03, 2012 at 12:29:01AM -0800, Mike Turquette wrote:
> > >> Many platforms support simple gateable clocks, fixed-rate clocks,
> > >> adjustable divider clocks and multi-parent multiplexer clocks.
> > >>
> > >> This patch introduces basic clock types for the above-mentioned hardware
> > >> which share some common characteristics.
> > >
> > > Hi Mike
> > >
> > > These basic clocks don't allow the use of prepare/unprepare, from the
> > > side of the clock provider. I think i need this.
> > 
> > This is an interesting point and might help us nail down exactly what
> > we expect from clk_prepare/clk_unprepare.
> > 
> > >
> > > The Orion Kirkwood SoC has clock gating for most of its on chip
> > > peripherals, which the other older Orion devices don't have. The SATA
> > > and PCIe also allows the PHY to be shut down, again which older Orion
> > > devices don't have. The current code links the clock and the PHY
> > > together, shutting both down are the same time. So i would like to
> > > perform the PHY shutdown in the unprepare() function of the clk
> > > driver.
> > 
> > Do you feel it is The Right Thing to enable/disable the phy from
> > clk_prepare/clk_unprepare?  
> 
> Humm, not sure yet. I don't know all the different possibilities,
> which is why i tried to describe my use case, rather than just assume
> i need prepare/unprepare.
> 
> I also realized i did not explain my use case properly. 
> 
> At boot, uboot is turning on various clocks and SATA/PCIe PHYs etc, in
> order to get the device booted. Linux takes over, and the
> Orion/kirkwood board files, ask the kirkwood or generic Orion code to
> create platform_data structures for the different devices that the
> board uses. The kirkwood code keeps a bitmap of devices for which it
> creates platform data for which there is a gated clock. Then in a
> lateinit call, it turns on clocks which are needed, and also turns off
> clocks which are no longer needed, because the board did not ask for a
> driver binding for that device. If it turns off a SATA or PCIe clock,
> it also turns off the PHY associated with it.
> 
> So we are talking about turning off hardware for which there is no
> driver. This seems to exclude pm_runtime_get(_sync), which is about
> hardware with drivers.
> 
> We touched on this subject a couple of months ago, at least with
> respect to clocks. You said that is what the flag CLK_IGNORE_UNUSED
> will be used for. In a lateinit call, you plan to iterate over all
> clocks and turn off any which don't have CLK_IGNORE_UNUSED and have
> not been enabled. I assume you will call both disable() and
> unprepare(), and if i've can put code into the unprepare to turn the
> PHY off, all is good.
> 
> > > Is allowing to pass prepare/unprepare functions to basic clocks
> > > something you want to support? If i prepare a patch would you consider
> > > it?
> > 
> > My original instinct was "no".  The simple gate clock was always
> > supposed to be "simple" and if you need more than it provides then it
> > might be best for your platform to implement a specific clock type.
> > Especially since the purpose of clk_prepare is still up in the air.
> 
> I think i can wrap your simple gate clock, to make my "complex" gate
> clock. What would help is if you would EXPORT_SYMBOL_GPL
> clk_gate_enable() and clk_gate_disable(), since they do exactly what i
> want. I can then build my own clk_ops structure, with my own
> unprepare() function. I would probably use DEFINE_CLK_GATE as is, and
> then at run time, before calling __clk_init() overwrite the .ops with
> my own version.

Maybe I don't get your point, but clk_unprepare should be used when
you have to sleep to disable your clock. When clk_gate_disable() is
exactly why do you want to use clk_unprepare instead of clk_disable?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From mina86 at mina86.com  Mon Mar  5 04:40:09 2012
From: mina86 at mina86.com (Michal Nazarewicz)
Date: Mon, 05 Mar 2012 10:40:09 +0100
Subject: [PATCH v2] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <1330931626-30855-1-git-send-email-Barry.Song@csr.com>
References: <1330931626-30855-1-git-send-email-Barry.Song@csr.com>
Message-ID: <op.waoyg7dp3l0zgt@mpn-glaptop>

On Mon, 05 Mar 2012 08:13:46 +0100, Barry Song <Barry.Song at csr.com> wrote:
> Any write request to /dev/cma_test will let the module to allocate memory from
> CMA, for example:
>
> 1st time
> $ echo 1024 > /dev/cma_test
> will require cma_test to request 1MB(1024KB)
> 2nd time
> $ echo 2048 > /dev/cma_test
> will require cma_test to request 2MB(2048KB)
>
> Any read request to /dev/cma_test will let the module to free the 1st valid
> memory from CMA, for example:
>
> 1st time
> $ cat /dev/cma_test
> will require cma_test to free the 1MB allocated in the first write request
> 2nd time
> $ cat /dev/cma_test
> will require cma_test to free the 2MB allocated in the second write request
>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>

> diff --git a/tools/cma/cma_test.c b/tools/cma/cma_test.c
> new file mode 100644
> index 0000000..46af250
> --- /dev/null
> +++ b/tools/cma/cma_test.c
> @@ -0,0 +1,140 @@
> +/*
> + * kernel module helper for testing CMA
> + *
> + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.

It's 2012.

> + *
> + * Licensed under GPLv2 or later.
> + */
> +
> +#include <linux/device.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/fs.h>
> +#include <linux/miscdevice.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +struct cma_allocation {
> +	struct list_head list;
> +	unsigned long size;
> +	dma_addr_t dma;
> +	void *virt;
> +};
> +
> +static struct device *cma_dev;
> +static LIST_HEAD(cma_allocations);
> +static DEFINE_SPINLOCK(cma_lock);
> +
> +/*
> + * any read request will free the 1st allocated coherent memory, eg.
> + * cat /dev/cma_test
> + */
> +static ssize_t
> +cma_test_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
> +{
> +	struct cma_allocation *alloc = NULL;
> +
> +	spin_lock(&cma_lock);
> +	if (!list_empty(&cma_allocations)) {
> +		alloc = list_first_entry(&cma_allocations,
> +			struct cma_allocation, list);
> +		list_del(&alloc->list);
> +	}
> +	spin_unlock(&cma_lock);
> +

Come to think of it, how about putting:

	if (!alloc)
		return -EIDRM;

here and then removing one indention level later:

> +	if (alloc) {
> +		dma_free_coherent(cma_dev, alloc->size, alloc->virt,
> +			alloc->dma);
> +
> +		_dev_info(cma_dev, "free CM at virtual address: 0x%p dma address: 0x%p size:%luKiB\n",

This message seem overly long and ?0x? seem redundant.  How about something like:

		_dev_info(cma_dev, "free: virt:%p dma:%p size:%luK\n",

which has all the same information but is shorter?

> +			alloc->virt, (void *)alloc->dma, alloc->size / SZ_1K);
> +		kfree(alloc);
> +	}
> +
> +	return 0;
> +}
> +
> +/*
> + * any write request will alloc a new coherent memory, eg.
> + * echo 1024 > /dev/cma_test
> + * will request 1024KiB by CMA
> + */
> +static ssize_t
> +cma_test_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
> +{
> +	struct cma_allocation *alloc;
> +	int ret;
> +
> +	alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
> +	if (!alloc)
> +		return -ENOMEM;
> +
> +	ret = kstrtoul_from_user(buf, count, 0, &alloc->size);
> +	if (ret)
> +		return ret;
> +
> +	if (!alloc->size)
> +		return -EINVAL;
> +
> +	if (alloc->size > (ULONG_MAX << PAGE_SHIFT))

You've changed units from pages to KiBs and, I've just realised that, since
dma_alloc_coherent accepts ?size_t? as argument, this should read:

	if (alloc->size > ~(size_t)0 / SZ_1K)

(?<<? was in fact a bug in my code from the beginning.)

> +		return -EOVERFLOW;

Most importantly, there was a memory leak in my original suggestion, and
it got carried over to this patch.  The above code should look
something like that:

	ret = kstrtoul_from_user(buf, count, 0, &alloc->size);
	if (ret)
		return ret;

	if (!alloc->size)
		return -EINVAL;

	if (alloc->size > ~(size_t)0 / SZ_1K)
		return -EOVERFLOW;

	alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
	if (!alloc)
		return -ENOMEM;

> +	alloc->size *= SZ_1K;
> +	alloc->virt = dma_alloc_coherent(cma_dev, alloc->size,
> +		&alloc->dma, GFP_KERNEL);
> +
> +	if (alloc->virt) {
> +		_dev_info(cma_dev, "allocate CM at virtual address: 0x%p"
> +			"address: 0x%p size:%luKiB\n", alloc->virt,

Similarly to message earlier, how about:

		_dev_info(cma_dev, "alloc: virt:%p dma:%p size:%luK\n",

> +			(void *)alloc->dma, alloc->size / SZ_1K);
> +
> +		spin_lock(&cma_lock);
> +		list_add_tail(&alloc->list, &cma_allocations);
> +		spin_unlock(&cma_lock);
> +
> +		return count;
> +	} else {
> +		dev_err(cma_dev, "no mem in CMA area\n");
> +		kfree(alloc);
> +		return -ENOSPC;
> +	}
> +}
> +
> +static const struct file_operations cma_test_fops = {
> +	.owner =    THIS_MODULE,
> +	.read  =    cma_test_read,
> +	.write =    cma_test_write,
> +};
> +
> +static struct miscdevice cma_test_misc = {
> +	.name = "cma_test",
> +	.fops = &cma_test_fops,
> +};
> +
> +static int __init cma_test_init(void)
> +{
> +	int ret = 0;

Drop ?= 0?, or better yet, combain this declaration with the next line.

> +
> +	ret = misc_register(&cma_test_misc);
> +	if (unlikely(ret)) {
> +		pr_err("failed to register cma test misc device!\n");
> +		return ret;
> +	}
> +	cma_dev = cma_test_misc.this_device;
> +	cma_dev->coherent_dma_mask = ~0;
> +	_dev_info(cma_dev, "registered.\n");
> +
> +	return ret;

	return 0;

> +}
> +module_init(cma_test_init);
> +
> +static void __exit cma_test_exit(void)
> +{
> +	misc_deregister(&cma_test_misc);
> +}
> +module_exit(cma_test_exit);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Barry Song <Baohua.Song at csr.com>");
> +MODULE_DESCRIPTION("kernel module to help the test of CMA");
> +MODULE_ALIAS("CMA test");

Can module alias contain spaces?  I don't think this declaration even
adds anything useful. ?cma_test? as module name should be good enough.

-- 
Best regards,                                         _     _
.o. | Liege of Serenely Enlightened Majesty of      o' \,=./ `o
..o | Computer Science,  Micha? ?mina86? Nazarewicz    (o o)
ooo +----<email/xmpp: mpn at google.com>--------------ooO--(_)--Ooo--


From t-kristo at ti.com  Mon Mar  5 04:41:27 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Mon, 5 Mar 2012 11:41:27 +0200
Subject: [PATCH] ARM: OMAP2+: voltage: ensure voltage used is exact
 voltage from OPP table
In-Reply-To: <1330728121-26664-1-git-send-email-khilman@ti.com>
References: <1330728121-26664-1-git-send-email-khilman@ti.com>
Message-ID: <1330940487.2116.119.camel@sokoban>

On Fri, 2012-03-02 at 14:42 -0800, Kevin Hilman wrote:
> When using the SMPS regulators to scale voltages, the regulator
> framework may pass a minimum voltage that is not an exact OPP voltage.
> For the VC/VP controlled voltage domains, we must ensure that the
> voltage requested is the exact voltage from the OPP table.  This is
> especially critical when using SR.
> 
> To fix, voltdm_scale() uses the target voltage passed to walk through
> the OPP voltages until it finds a voltage that is >= one of the OPP
> voltages.

I have just one question to this, how about smartreflex class1p5? Do we
have any plans for that one? The old implementation at least was using
voltdm_scale, so if we modify this function, smartreflex class1p5
doesn't work anymore.

Otherwise this patch looks good to me.

-Tero

> 
> Cc: Tero Kristo <t-kristo at ti.com>
> Cc: Nishanth Menon <nm at ti.com>
> Signed-off-by: Kevin Hilman <khilman at ti.com>
> ---
> Unless there are any objections, this will be queued along with the
> rest of the SMPS regulator series from Tero.  Currently availble in
> my for_3.4/pm/smps-regulator branch at
> git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git
> 
>  arch/arm/mach-omap2/voltage.c |   21 ++++++++++++++++++---
>  1 file changed, 18 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
> index 8a36342..4dc60e8 100644
> --- a/arch/arm/mach-omap2/voltage.c
> +++ b/arch/arm/mach-omap2/voltage.c
> @@ -73,7 +73,8 @@ unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
>  int voltdm_scale(struct voltagedomain *voltdm,
>  		 unsigned long target_volt)
>  {
> -	int ret;
> +	int ret, i;
> +	unsigned long volt = 0;
>  
>  	if (!voltdm || IS_ERR(voltdm)) {
>  		pr_warning("%s: VDD specified does not exist!\n", __func__);
> @@ -86,9 +87,23 @@ int voltdm_scale(struct voltagedomain *voltdm,
>  		return -ENODATA;
>  	}
>  
> -	ret = voltdm->scale(voltdm, target_volt);
> +	/* Adjust voltage to the exact voltage from the OPP table */
> +	for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) {
> +		if (voltdm->volt_data[i].volt_nominal >= target_volt) {
> +			volt = voltdm->volt_data[i].volt_nominal;
> +			break;
> +		}
> +	}
> +
> +	if (!volt) {
> +		pr_warning("%s: not scaling. OPP voltage for %lu, not found.\n",
> +			   __func__, target_volt);
> +		return -EINVAL;
> +	}
> +
> +	ret = voltdm->scale(voltdm, volt);
>  	if (!ret)
> -		voltdm->nominal_volt = target_volt;
> +		voltdm->nominal_volt = volt;
>  
>  	return ret;
>  }




From s.hauer at pengutronix.de  Mon Mar  5 02:38:36 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 5 Mar 2012 08:38:36 +0100
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
Message-ID: <20120305073836.GU3852@pengutronix.de>

On Sun, Mar 04, 2012 at 04:12:21PM -0800, Turquette, Mike wrote:
> >>
> >> I believe this patch already does what you suggest, but I might be
> >> missing your point.
> >
> > In include/linux/clk-private.h you expose struct clk outside the core.
> > This has to be done to make static initializers possible. There is a big
> > warning in this file that it must not be included from files implementing
> > struct clk_ops. You can simply avoid this warning by declaring struct clk
> > with only a single member:
> >
> > include/linux/clk.h:
> >
> > struct clk {
> > ? ? ? ?struct clk_internal *internal;
> > };
> >
> > This way everybody knows struct clk (thus can embed it in their static
> > initializers), but doesn't know anything about the internal members. Now
> > in drivers/clk/clk.c you declare struct clk_internal exactly like struct
> > clk was declared before:
> >
> > struct clk_internal {
> > ? ? ? ?const char ? ? ? ? ? ? ?*name;
> > ? ? ? ?const struct clk_ops ? ?*ops;
> > ? ? ? ?struct clk_hw ? ? ? ? ? *hw;
> > ? ? ? ?struct clk ? ? ? ? ? ? ?*parent;
> > ? ? ? ?char ? ? ? ? ? ? ? ? ? ?**parent_names;
> > ? ? ? ?struct clk ? ? ? ? ? ? ?**parents;
> > ? ? ? ?u8 ? ? ? ? ? ? ? ? ? ? ?num_parents;
> > ? ? ? ?unsigned long ? ? ? ? ? rate;
> > ? ? ? ?unsigned long ? ? ? ? ? flags;
> > ? ? ? ?unsigned int ? ? ? ? ? ?enable_count;
> > ? ? ? ?unsigned int ? ? ? ? ? ?prepare_count;
> > ? ? ? ?struct hlist_head ? ? ? children;
> > ? ? ? ?struct hlist_node ? ? ? child_node;
> > ? ? ? ?unsigned int ? ? ? ? ? ?notifier_count;
> > #ifdef CONFIG_COMMON_CLK_DEBUG
> > ? ? ? ?struct dentry ? ? ? ? ? *dentry;
> > #endif
> > };
> >
> > An instance of struct clk_internal will be allocated in
> > __clk_init/clk_register. Now the private data stays completely inside
> > the core and noone can abuse it.
> 
> Hi Sascha,
> 
> I see the disconnect here.  For OMAP (and possibly other platforms) at
> least some clock data is necessary during early boot, before the
> regular allocation methods are available (timers for instance).

We had this problem on i.MX aswell. It turned out that the timer clock
is the only clock that is needed so early. We solved this by moving the
clock init to the system timer init function.

> Due
> to this my idea of static initialization was to take care of
> everything that would normally require an allocator, which includes
> the internals of struct clk; thus exposing struct clk is useful here
> as you can still use the clock framework during very early boot.  Your
> method above doesn't satisfy this requirement.  I'm not sure what the
> purpose would be of statically allocating your version of struct clk,
> which will ultimately need to allocate memory for the clock internals
> anyways.  Can you elaborate the benefit of this approach over just
> using the clk_foo_register functions?

As said the benefit is that you do not have to expose the internal
layout of struct clk outside the clock framework. Note that in the
file you referenced here:

http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=arch/arm/mach-omap2/clock44xx_data.c;h=7f833a7b2dca84a52c2bd1e7c8d9cfe560771258;hb=v3.3-rc5-clkv5-omap#l205

You violate what you have in a comment above clk-private.h:

/* __clk_init is only exposed via clk-private.h and is intended for use with
 * very large numbers of clocks that need to be statically initialized. It is
 * a layering violation to include clk-private.h from any code which implements
 * a clock's .ops; as such any statically initialized clock data MUST be in
 * separate C file from the logic that implements it's operations.
 */

Well, the file is work in progress, you probably fix this before sending
it out, but I bet people will include clk-private.h and nobody else
notices it.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From rnayak at ti.com  Mon Mar  5 05:01:13 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 05 Mar 2012 15:31:13 +0530
Subject: [PATCHv4 0/6] ARM: OMAP3+: IO daisychain support fixes
In-Reply-To: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
Message-ID: <4F548EE9.6050805@ti.com>

On Friday 02 March 2012 08:47 PM, Tero Kristo wrote:
> Hi,
>
> Changes compared to previous version:
>
> - patch2:
>   * changed timeout value to 100us (from 1000)
>   * added poll for the IO status == 0 at the end of trigger sequence
> - patch4:
>   * omap3: global wakeup done in PRM init instead of OMAP3 PM init
>   * omap4: moved global wakeup enable from trigger func to PRM init
>
> Tested on omap3beagle / omap4blaze, suspend / resume works with io chain.

for the full series,
Reviewed-by: Rajendra Nayak <rnayak at ti.com>

>
> -Tero
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From linus.walleij at linaro.org  Mon Mar  5 05:15:32 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 5 Mar 2012 11:15:32 +0100
Subject: [PATCH] pinctrl: resurrect verbose pinmux-pins
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE8619C2@HQMAIL01.nvidia.com>
References: <1330705873-10798-1-git-send-email-linus.walleij@stericsson.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861978@HQMAIL01.nvidia.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861991@HQMAIL01.nvidia.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE8619C2@HQMAIL01.nvidia.com>
Message-ID: <CACRpkdYrj2ay=k2MgYOekQtcfbP9FiY5Rju8VznJHrxG81Y7SQ@mail.gmail.com>

On Fri, Mar 2, 2012 at 7:24 PM, Stephen Warren <swarren at nvidia.com> wrote:
> Stephen Warren wrote at Friday, March 02, 2012 10:41 AM:
>> Stephen Warren wrote at Friday, March 02, 2012 10:22 AM:
>> > Linus Walleij wrote at riday, March 02, 2012 9:31 AM:
>> > > From: Linus Walleij <linus.walleij at linaro.org>
>> > >
>> > > This reintroduces the verbosity in the pinmux-pins file, now this
>> > > file will list all pins, their names, owning device (and if it's
>> > > a hog) and also in applicable cases the function and group making
>> > > use of that pin right now.
>> > >
>> > > Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
>> >
>> > It'd be nice if we could defer this fix until after all the API rework,
>> > because it'll cause all kinds of conflicts otherwise.
>>
>> Oh, I see this patch is in your for-next branch already before I had a chance
>> to comment on it. I guess I'll have write a patch to convert the removed struct
>> type to char*s and rebase on top of it:-(

Mainly because I saw it as a regression fix.

> I take that back. Can we please drop this patch and I'll provide an
> equivalent in my API rework series?

Yeah no problem, if the rest of the v3 patch set is OK I'll just
remove that patch.

Yours,
Linus Walleij


From andrew at lunn.ch  Mon Mar  5 05:17:08 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Mon, 5 Mar 2012 11:17:08 +0100
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <20120305092948.GV3852@pengutronix.de>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
 <20120304174229.GD11546@lunn.ch>
 <CAJOA=zNWN6L+-YEkNKoQnjnrrswNpCBmtnhKBm04HekWP46i5w@mail.gmail.com>
 <20120305084823.GD24858@lunn.ch>
 <20120305092948.GV3852@pengutronix.de>
Message-ID: <20120305101708.GF24858@lunn.ch>

> > I think i can wrap your simple gate clock, to make my "complex" gate
> > clock. What would help is if you would EXPORT_SYMBOL_GPL
> > clk_gate_enable() and clk_gate_disable(), since they do exactly what i
> > want. I can then build my own clk_ops structure, with my own
> > unprepare() function. I would probably use DEFINE_CLK_GATE as is, and
> > then at run time, before calling __clk_init() overwrite the .ops with
> > my own version.
> 
> Maybe I don't get your point, but clk_unprepare should be used when
> you have to sleep to disable your clock. When clk_gate_disable() is
> exactly why do you want to use clk_unprepare instead of clk_disable?

I'm trying to avoid having to implement a new clock provider. The
whole point of the generic clk code is to consolidate code. It seems
silly to create a new clk provider which is 95% identical to Mike's
gated provider, if i can avoid it.

If i stuff it into clk_disable(), it means i cannot use the basic gate
clock Mike provides in the generic clock framework. Which is a shame,
since it does exactly what i want in terms of gating the clock.

If i can use unprepare(), which basic gate does not use, i can use
Mikes code, and just extend it. It is there, it is unused, so why not
use it?

    Andrew


From jh80.chung at samsung.com  Mon Mar  5 05:24:38 2012
From: jh80.chung at samsung.com (Jaehoon Chung)
Date: Mon, 05 Mar 2012 19:24:38 +0900
Subject: [PATCH 1/2] mmc: sdhci-s3c: Use CONFIG_PM_SLEEP to ifdef system
 suspend
In-Reply-To: <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <4F51697C.40408@samsung.com>
 <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <4F549466.5090708@samsung.com>

Acked-by: Jaehoon Chung <jh80.chung at samsung.com>

On 03/03/2012 09:46 AM, Mark Brown wrote:

> This matches current best practice as one can have runtime PM enabled
> without system sleep and CONFIG_PM is defined for both.
> 
> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---
>  drivers/mmc/host/sdhci-s3c.c |    9 +++++----
>  1 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index ea0767e..46152d6 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -22,6 +22,7 @@
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/of_gpio.h>
> +#include <linux/pm.h>
>  
>  #include <linux/mmc/host.h>
>  
> @@ -807,8 +808,7 @@ static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -#ifdef CONFIG_PM
> -
> +#ifdef CONFIG_PM_SLEEP
>  static int sdhci_s3c_suspend(struct device *dev)
>  {
>  	struct sdhci_host *host = dev_get_drvdata(dev);
> @@ -822,10 +822,11 @@ static int sdhci_s3c_resume(struct device *dev)
>  
>  	return sdhci_resume_host(host);
>  }
> +#endif
>  
> +#ifdef CONFIG_PM
>  static const struct dev_pm_ops sdhci_s3c_pmops = {
> -	.suspend	= sdhci_s3c_suspend,
> -	.resume		= sdhci_s3c_resume,
> +	SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
>  };
>  
>  #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)




From balajitk at ti.com  Mon Mar  5 05:25:56 2012
From: balajitk at ti.com (T Krishnamoorthy, Balaji)
Date: Mon, 5 Mar 2012 15:55:56 +0530
Subject: [PATCH 4/4] mmc: omap_hsmmc: Simplify init for twl6030 MMC card
 detect
In-Reply-To: <4F548457.5050205@ti.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185535.29210.71546.stgit@kaulin.local>
 <4F50643B.9050500@ti.com> <20120302172251.GJ18901@atomide.com>
 <4F548457.5050205@ti.com>
Message-ID: <CANrkHUZysOnHKKUuLm0Vbo1KsNp0yUd=udjGvQ43=gTTXbWeCw@mail.gmail.com>

On Mon, Mar 5, 2012 at 2:46 PM, Rajendra Nayak <rnayak at ti.com> wrote:
> On Friday 02 March 2012 10:52 PM, Tony Lindgren wrote:
>>
>> BTW, with -rc5, looks like re-inserting omap_hsmmc on omap4 fails
>> to detect any cards, and then fails to unload. This works on omap3
>> just fine. Any ideas why that would be?
>
>
> Yeah, looks like thats broken. I am not sure whats going wrong though.
> I just enabled CONFIG_MMC_DEBUG and saw these logs below.
>
> Venkat/Balaji, care to look at this one?
>

Let me check this

> # insmod omap_hsmmc.ko
> [ ? 43.358398] omap_hsmmc omap_hsmmc.0: context was not lost
> [ ? 43.364105] omap_hsmmc omap_hsmmc.0: enabled
> [ ? 44.434661] mmc0: clock 0Hz busmode 1 powermode 0 cs 0 Vdd 0 width 0
> timing 0
> [ ? 44.442352] omap_hsmmc omap_hsmmc.0: Set clock to 0Hz
> [ ? 44.474365] omap_hsmmc omap_hsmmc.0: disabled
> [ ? 44.482208] omap_hsmmc omap_hsmmc.4: context was not lost
> [ ? 44.482208] omap_hsmmc omap_hsmmc.4: enabled
> [ ? 44.546600] omap_hsmmc omap_hsmmc.0: context was not lost
> [ ? 44.552276] omap_hsmmc omap_hsmmc.0: enabled
> [ ? 44.552276] mmc0: mmc_rescan_try_freq: trying to init card at 400000 Hz
> [ ? 44.563720] mmc0: clock 0Hz busmode 2 powermode 1 cs 0 Vdd 18 width 0
> timing 0
> [ ? 44.572174] omap_hsmmc omap_hsmmc.0: Set clock to 0Hz
> [ ? 44.613800] mmc0: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 18 width
> 0 timing 0
> [ ? 44.621887] omap_hsmmc omap_hsmmc.0: Set clock to 400000Hz
> [ ? 44.735290] mmc0: starting CMD52 arg 00000c00 flags 00000195
> [ ? 44.741271] omap_hsmmc omap_hsmmc.0: mmc0: CMD52, argument 0x00000c00
> [ ? 45.560241] mmc1: clock 0Hz busmode 1 powermode 0 cs 0 Vdd 0 width 0
> timing 0
> [ ? 45.567871] omap_hsmmc omap_hsmmc.4: Set clock to 0Hz
> [ ? 45.591491] omap_hsmmc omap_hsmmc.4: disabled
> #
> #
> # rmmod omap_hsmmc
> [ ?607.302307] omap_hsmmc omap_hsmmc.4: context was not lost
> [ ?607.308044] omap_hsmmc omap_hsmmc.4: enabled
> [ ?607.312591] omap_hsmmc omap_hsmmc.4: disabled
> [ ?607.317199] omap_hsmmc omap_hsmmc.4: context was not lost
> [ ?607.322875] omap_hsmmc omap_hsmmc.4: enabled
>


From will.deacon at arm.com  Mon Mar  5 05:32:45 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 5 Mar 2012 10:32:45 +0000
Subject: [PATCH] Add the Performance Monitoring Unit to the Trimslice
 device tree
In-Reply-To: <1330740413-29260-1-git-send-email-wcohen@redhat.com>
References: <1330740413-29260-1-git-send-email-wcohen@redhat.com>
Message-ID: <20120305103245.GC31189@mudshark.cambridge.arm.com>

On Sat, Mar 03, 2012 at 02:06:53AM +0000, William Cohen wrote:
> The tegra processor has a performance monitoring unit. However, this
> was not listed on the board-trimslice.c devices. This patch adds
> it to the list of devices and allows one to use hardware performance
> monitoring events on the trimslice machine.
> 
> Signed-off-by: William Cohen <wcohen at redhat.com>
> ---
>  arch/arm/mach-tegra/board-trimslice.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
> index cd52820..0484903 100644
> --- a/arch/arm/mach-tegra/board-trimslice.c
> +++ b/arch/arm/mach-tegra/board-trimslice.c
> @@ -82,6 +82,7 @@ static struct platform_device trimslice_audio_device = {
>  
>  static struct platform_device *trimslice_devices[] __initdata = {
>  	&debug_uart,
> +	&tegra_pmu_device,
>  	&tegra_sdhci_device1,
>  	&tegra_sdhci_device4,
>  	&tegra_i2s_device1,
> -- 
> 1.7.5.2

Olof - would you be able to pick this up please? I've not been able to test
it, but since the device is already defined I'm assuming the IRQ numbers are
correct.

Cheers,

Will


From tim.schendekehl at egnite.de  Mon Mar  5 05:34:58 2012
From: tim.schendekehl at egnite.de (Tim Schendekehl)
Date: Mon, 05 Mar 2012 11:34:58 +0100
Subject: [PATCH] ARM: at91: Ethernut 5 board support
Message-ID: <4F5496D2.8090702@egnite.de>

Add support for the Ethernut 5 open hardware design, based
on Atmel's AT91SAM9XE512 SoC.

Signed-off-by: Tim Schendekehl <tim.schendekehl at egnite.de>
---
 arch/arm/mach-at91/Kconfig           |    7 +
 arch/arm/mach-at91/Makefile          |    1 +
 arch/arm/mach-at91/board-ethernut5.c |  280 ++++++++++++++++++++++++++++++++++
 3 files changed, 288 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-at91/board-ethernut5.c

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 71feb00..88ee70a 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -239,6 +239,13 @@ config MACH_CAM60
 	  Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
 	  <http://www.kwikbyte.com/KB9260.html>
 
+config MACH_ETHERNUT5
+	bool "Ethernut 5 board"
+	select HAVE_AT91_DATAFLASH_CARD
+	help
+	  Select this if you are using an Ethernut 5 board
+	  <http://www.ethernut.de/en/hardware/enut5/>
+
 config MACH_SAM9_L9260
 	bool "Olimex SAM9-L9260 board"
 	select HAVE_AT91_DATAFLASH_CARD
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 705e1fb..e8ef87d 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_MACH_RSI_EWS)	+= board-rsi-ews.o
 # AT91SAM9260 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
 obj-$(CONFIG_MACH_CAM60)	+= board-cam60.o
+obj-$(CONFIG_MACH_ETHERNUT5)	+= board-ethernut5.o
 obj-$(CONFIG_MACH_SAM9_L9260)	+= board-sam9-l9260.o
 obj-$(CONFIG_MACH_USB_A9260)	+= board-usb-a926x.o
 obj-$(CONFIG_MACH_QIL_A9260)	+= board-qil-a9260.o
diff --git a/arch/arm/mach-at91/board-ethernut5.c b/arch/arm/mach-at91/board-ethernut5.c
new file mode 100644
index 0000000..d1e01b1
--- /dev/null
+++ b/arch/arm/mach-at91/board-ethernut5.c
@@ -0,0 +1,280 @@
+/*
+ * linux/arch/arm/mach-at91/board-ethernut5.c
+ *
+ *  Copyright (C) 2008 Ole Reinhardt <ole.reinhardt at thermotemp.de>
+ *  Copyright (C) 2012 egnite GmbH <info at egnite.de>
+ *
+ * linux/arch/arm/mach-at91/board-sam9260ek.c
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/clk.h>
+#include <linux/i2c-gpio.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91_shdwc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+static void __init ethernut5_init_early(void)
+{
+	/* Initialize processor: 18.432 MHz crystal */
+	at91_initialize(18432000);
+	/* DBGU on ttyS0. (Rx & Tx only) */
+	at91_register_uart(0, 0, 0);
+	/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+	at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
+			   | ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR
+			   | ATMEL_UART_DCD | ATMEL_UART_RI);
+	/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+	at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS
+			   | ATMEL_UART_RTS);
+	/* set serial console to ttyS0 (ie, DBGU) */
+	at91_set_serial_console(0);
+}
+
+/*
+ * USB host port
+ */
+static struct at91_usbh_data __initdata ethernut5_usbh_data = {
+	.ports		= 2,
+	.vbus_pin	= {-EINVAL, -EINVAL},
+};
+
+/*
+ * USB device port
+ */
+static struct at91_udc_data __initdata ethernut5_udc_data = {
+	.vbus_pin	= AT91_PIN_PC5,
+	.pullup_pin	= -EINVAL,		/* pull-up driven by UDC */
+};
+
+/*
+ * SPI flash
+ */
+static struct mtd_partition ethernut5_spi_dataflash_partitions[] = {
+	{
+		.name	= "user",
+		.size	= 0x021000,
+		.offset	= 0x000000,
+	},
+	{
+		.name	= "setup",
+		.size	= 0x021000,
+		.offset	= 0x021000,
+	},
+	{
+		.name	= "uboot",
+		.size	= 0x084000,
+		.offset	= 0x042000,
+	},
+	{
+		.name	= "kernel",
+		.size	= 0x0C6000,
+		.offset	= 0x294000,
+	},
+	{
+		.name	= "nutos",
+		.size	= 0x35A000,
+		.offset	= 0x084000,
+	},
+	{
+		.name	= "env",
+		.size	= 0x3DE000,
+		.offset	= 0x021000,
+	}
+};
+
+static struct flash_platform_data ethernut5_spi_dataflash_data = {
+	.name = "mtd_dataflash",
+	.parts = ethernut5_spi_dataflash_partitions,
+	.nr_parts = ARRAY_SIZE(ethernut5_spi_dataflash_partitions),
+	.type = "mtd_dataflash",
+};
+
+static struct spi_board_info ethernut5_spi_devices[] = {
+	{
+		.modalias	= "mtd_dataflash",
+		.chip_select	= 0,
+		.max_speed_hz	= 15 * 1000 * 1000,
+		.bus_num	= 0,
+		.platform_data	= &ethernut5_spi_dataflash_data,
+	},
+};
+
+/*
+ * NAND flash
+ */
+static struct sam9_smc_config __initdata ethernut5_nand_smc_config = {
+	.ncs_read_setup		= 0,
+	.nrd_setup		= 1,
+	.ncs_write_setup	= 0,
+	.nwe_setup		= 1,
+
+	.ncs_read_pulse		= 3,
+	.nrd_pulse		= 3,
+	.ncs_write_pulse	= 3,
+	.nwe_pulse		= 3,
+
+	.read_cycle		= 5,
+	.write_cycle		= 5,
+
+	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+					AT91_SMC_EXNWMODE_DISABLE,
+	.tdf_cycles		= 1,
+};
+
+static struct mtd_partition __initdata ethernut5_nand_partition[] = {
+	{
+		.name	= "root",
+		.offset	= 0,
+		.size	= 0x08000000,
+	},
+	{
+		.name	= "data",
+		.offset	= 0x08000000,
+		.size	= MTDPART_SIZ_FULL,
+	}
+};
+
+static struct atmel_nand_data __initdata ethernut5_nand_data = {
+	.ale		= 21,
+	.cle		= 22,
+	.det_pin	= -EINVAL,
+	.rdy_pin	= -EINVAL,
+	.enable_pin	= AT91_PIN_PC14,
+	.parts = ethernut5_nand_partition,
+	.num_parts	= ARRAY_SIZE(ethernut5_nand_partition),
+	.bus_width_16	= 0,
+};
+
+static void __init ethernut5_add_device_nand(void)
+{
+	ethernut5_nand_smc_config.mode |= AT91_SMC_DBW_8;
+	sam9_smc_configure(0, 3, &ethernut5_nand_smc_config);
+	at91_add_device_nand(&ethernut5_nand_data);
+}
+
+/*
+ * MACB Ethernet device
+ */
+static struct macb_platform_data __initdata ethernut5_macb_data = {
+	.phy_irq_pin	= AT91_PIN_PA7,
+	.is_rmii	= 1,
+};
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata ethernut5_mmc_data = {
+	.slot_b		= 0,
+	.wire4		= 1,
+	.det_pin	= AT91_PIN_PC8,
+	.wp_pin		= AT91_PIN_PC9,
+	.vcc_pin	= -EINVAL,
+};
+
+/*
+ * I2C devices
+ */
+static struct i2c_board_info __initdata ethernut5_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("pcf8563", 0x51),
+	},
+	{
+		I2C_BOARD_INFO("pmmc", 0x22),
+	}
+};
+
+static struct i2c_gpio_platform_data ethernut5_i2c_pdata = {
+	.sda_pin		= AT91_PIN_PA23,
+	.sda_is_open_drain	= 1,
+	.scl_pin		= AT91_PIN_PA24,
+	.scl_is_open_drain	= 1,
+	.udelay			= 10,
+};
+
+static struct platform_device ethernut5_twi_device = {
+	.name			= "i2c-gpio",
+	.id			= -1,
+	.dev.platform_data	= &ethernut5_i2c_pdata,
+};
+
+static void __init ethernut5_add_device_i2c(struct i2c_board_info *devices,
+						int nr_devices)
+{
+	at91_set_GPIO_periph(AT91_PIN_PA23, 1);
+	at91_set_multi_drive(AT91_PIN_PA23, 1);
+
+	at91_set_GPIO_periph(AT91_PIN_PA24, 1);
+	at91_set_multi_drive(AT91_PIN_PA24, 1);
+
+	i2c_register_board_info(0, devices, nr_devices);
+	platform_device_register(&ethernut5_twi_device);
+}
+
+static void __init ethernut5_board_init(void)
+{
+	/* I2C needed for power management of other devices */
+	ethernut5_add_device_i2c(ethernut5_i2c_devices,
+				ARRAY_SIZE(ethernut5_i2c_devices));
+	/* Serial */
+	at91_add_device_serial();
+	/* USB Host */
+	at91_add_device_usbh(&ethernut5_usbh_data);
+	/* USB Device */
+	at91_add_device_udc(&ethernut5_udc_data);
+	/* SPI */
+	at91_add_device_spi(ethernut5_spi_devices,
+				ARRAY_SIZE(ethernut5_spi_devices));
+	/* NAND */
+	ethernut5_add_device_nand();
+	/* Ethernet */
+	at91_add_device_eth(&ethernut5_macb_data);
+	/* MMC */
+	at91_add_device_mmc(0, &ethernut5_mmc_data);
+}
+
+MACHINE_START(ETHERNUT5, "Ethernut 5")
+	/* Maintainer: egnite GmbH <info at egnite.de> */
+	.atag_offset = 0x100,
+	.timer		= &at91sam926x_timer,
+	.init_early	= ethernut5_init_early,
+	.init_machine	= ethernut5_board_init,
+	.map_io		= at91_map_io,
+	.init_irq	= at91_init_irq_default,
+MACHINE_END
-- 
1.7.1




From jh80.chung at samsung.com  Mon Mar  5 05:48:42 2012
From: jh80.chung at samsung.com (Jaehoon Chung)
Date: Mon, 05 Mar 2012 19:48:42 +0900
Subject: [PATCH 2/2] mmc: sdhci-s3c: Enable runtime power management
In-Reply-To: <1330735602-22409-2-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <4F51697C.40408@samsung.com>
 <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1330735602-22409-2-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <4F549A0A.5020402@samsung.com>

Hi Mark,

On 03/03/2012 09:46 AM, Mark Brown wrote:

> Since most of the work is already done by the core we just need to add
> runtime suspend methods and tell the PM core that runtime PM is enabled
> for this device.
> 
> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---
>  drivers/mmc/host/sdhci-s3c.c |   28 ++++++++++++++++++++++++++++
>  1 files changed, 28 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index 46152d6..6926ac9 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -23,6 +23,7 @@
>  #include <linux/of.h>
>  #include <linux/of_gpio.h>
>  #include <linux/pm.h>
> +#include <linux/pm_runtime.h>
>  
>  #include <linux/mmc/host.h>
>  
> @@ -721,6 +722,11 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>  	if (pdata->host_caps2)
>  		host->mmc->caps2 |= pdata->host_caps2;
>  
> +	pm_runtime_enable(&pdev->dev);
> +	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);

Could you explain why use 50ms? 

> +	pm_runtime_use_autosuspend(&pdev->dev);
> +	pm_suspend_ignore_children(&pdev->dev, 1);

Is there reason that ignore_children use to set the true?

> +
>  	ret = sdhci_add_host(host);
>  	if (ret) {
>  		dev_err(dev, "sdhci_add_host() failed\n");
> @@ -740,6 +746,8 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>  
>   err_add_host:
>  	release_resource(sc->ioarea);
> +	pm_runtime_forbid(&pdev->dev);
> +	pm_runtime_get_noresume(&pdev->dev);
>  	kfree(sc->ioarea);
>  
>   err_req_regs:
> @@ -784,6 +792,8 @@ static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
>  
>  	sdhci_remove_host(host, 1);
>  
> +	pm_runtime_disable(&pdev->dev);
> +
>  	for (ptr = 0; ptr < 3; ptr++) {
>  		if (sc->clk_bus[ptr]) {
>  			clk_disable(sc->clk_bus[ptr]);
> @@ -824,9 +834,27 @@ static int sdhci_s3c_resume(struct device *dev)
>  }
>  #endif
>  
> +#ifdef CONFIG_PM_RUNTIME
> +static int sdhci_s3c_runtime_suspend(struct device *dev)
> +{
> +	struct sdhci_host *host = dev_get_drvdata(dev);
> +
> +	return sdhci_runtime_suspend_host(host);
> +}
> +
> +static int sdhci_s3c_runtime_resume(struct device *dev)
> +{
> +	struct sdhci_host *host = dev_get_drvdata(dev);
> +
> +	return sdhci_runtime_resume_host(host);
> +}
> +#endif
> +
>  #ifdef CONFIG_PM
>  static const struct dev_pm_ops sdhci_s3c_pmops = {
>  	SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
> +	SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
> +			   NULL)
>  };
>  
>  #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)




From b-cousson at ti.com  Mon Mar  5 05:55:13 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 5 Mar 2012 11:55:13 +0100
Subject: [RFC PATCH] of: DMA helpers: manage generic requests specification
In-Reply-To: <1330527248-4350-1-git-send-email-nicolas.ferre@atmel.com>
References: <4F22DEF2.5000807@ti.com>
 <1330527248-4350-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <4F549B91.4080601@ti.com>

Hi Nico,

On 2/29/2012 3:54 PM, Nicolas Ferre wrote:
> By making DMA controllers register a generic translation
> function, we allow the management of any type of DMA requests
> specification.
> The void * output of an of_dma_xlate() function that will be implemented
> by the DMA controller can carry any type of "dma-request" argument.
>
> The DMA client will search its associated DMA controller in the list
> and call the registered of_dam_xlate() function to retrieve the
> request values.
>
> One simple xlate function is provided for the "single number" type
> of request biding.
>
> This implementation is independent from dmaengine so it can also be
> used by legacy drivers.
>
> Signed-off-by: Nicolas Ferre<nicolas.ferre at atmel.com>
> Cc: Benoit Cousson<b-cousson at ti.com>
> Cc: Stephen Warren<swarren at nvidia.com>
> Cc: Grant Likely<grant.likely at secretlab.ca>
> Cc: Russell King<linux at arm.linux.org.uk>
> Cc: Rob Herring<rob.herring at calxeda.com>
> ---
> Hi all,
>
> Here are my thoughts about the DMA helpers for device tree.
> This patch goes on top of Benoit's ones. My goal was to keep this separated
> from any DMA infrastructure (dmaengine not needed, nor any other DMA
> implementation).

Thanks for taking the ball on that.

> It is to keep the ball rolling, so do not hesitate to comment.

That looks pretty good.

My only question to the whole audience who care about that is:
Do we want to enforce the usage of dmaengine and thus add the DT support 
into dmaengine or do we want to go add some infrastructure in DT core 
like it is done here?

To be honest, I'm fine with that approach because OMAP DMA is still not 
using dmaengine. But potentially I can easily add a dummy dmaengine into 
the OMAP DMA driver just to support the OF code if needed.

>   Documentation/devicetree/bindings/dma/dma.txt |   29 +++--
>   drivers/of/dma.c                              |  161 ++++++++++++++++++++++---
>   include/linux/of_dma.h                        |   33 +++++-
>   3 files changed, 186 insertions(+), 37 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/dma.txt b/Documentation/devicetree/bindings/dma/dma.txt
> index 7f2a301..c49e98d 100644
> --- a/Documentation/devicetree/bindings/dma/dma.txt
> +++ b/Documentation/devicetree/bindings/dma/dma.txt
> @@ -6,9 +6,8 @@ DMA request line that goes from an IP to a DMA controller.
>
>   * DMA controller
>
> -Required properties:
> -    - dma-controller: Mark the device as a DMA controller
> -    - #dma-cells: Number of cell for each DMA line, must be one.
> +Required property:
> +    - #dma-cells: Number of cells for each DMA line.
>
>
>   Example:
> @@ -17,7 +16,6 @@ Example:
>   		compatible = "ti,sdma-omap4"
>   		reg =<0x48000000 0x1000>;
>   		interrupts =<12>;
> -        dma-controller;
>   		#dma-cells =<1>;
>   	};
>
> @@ -25,20 +23,23 @@ Example:
>
>   * DMA client
>
> -Client drivers should specify the DMA request numbers using a phandle to
> -the controller + the DMA request number on that controller.
> +Client drivers should specify the DMA request property using a phandle to
> +the controller. If needed, the DMA request identity on that controller is then
> +added followed by optional request specifications.
>
> -Required properties:
> -    - dma-request: List of pair phandle + dma-request per line
> +Required property:
> +    - dma-request: List of phandle + dma-request + request specifications,
> +      one group per request "line".
> +Optional property:
>       - dma-request-names: list of strings in the same order as the dma-request
>         in the dma-request property.
>
>
>   Example:
>
> -    i2c1: i2c at 1 {
> -        ...
> -        dma-request =<&sdma 2&sdma 3>;
> -        dma-request-names = "tx", "rx";
> -        ...
> -    };
> +	i2c1: i2c at 1 {
> +		...
> +		dma-request =<&sdma 2&sdma 3>;
> +		dma-request-names = "tx", "rx";
> +		...
> +	};
> diff --git a/drivers/of/dma.c b/drivers/of/dma.c
> index d4927e2..e0c6fd9 100644
> --- a/drivers/of/dma.c
> +++ b/drivers/of/dma.c
> @@ -13,41 +13,145 @@
>   #include<linux/device.h>
>   #include<linux/err.h>
>   #include<linux/module.h>
> +#include<linux/rculist.h>
> +#include<linux/slab.h>
>   #include<linux/of.h>
>   #include<linux/of_dma.h>
>
> +static LIST_HEAD(of_dma_list);
> +
> +/**
> + * of_dma_find_controller() - Find a DMA controller in DT DMA helpers list
> + * @np:		device node of DMA controller
> + */
> +static struct of_dma *of_dma_find_controller(struct device_node *np)
> +{
> +	struct of_dma	*ofdma;
> +
> +	list_for_each_entry_rcu(ofdma,&of_dma_list, of_dma_controllers) {
> +		if (ofdma->of_node == np)
> +			return ofdma;
> +	}
> +
> +	return NULL;
> +}
> +
>   /**
> - * of_get_dma_request() - Get a DMA request number and dma-controller node
> + * of_dma_controller_register() - Register a DMA controller to DT DMA helpers
> + * @np:			device node of DMA controller
> + * @of_dma_xlate:	generic translation function which converts a phandle
> + *			arguments list into a generic output value
> + *
> + * Returns 0 on success or appropriate errno value on error.
> + *
> + * If #dma-cells is not specified in DMA controller device tree node, we assume
> + * that the DMA controller phandle will come without argument.
> + *
> + * Allocated memory sould be freed with apropriate of_dma_controller_free()

Nit: typos:            should              appropriate

> + * call.
> + */
> +int of_dma_controller_register(struct device_node *np,
> +			int (*of_dma_xlate)(struct of_phandle_args *, void *))
> +{
> +	struct of_dma	*ofdma;
> +	int		*nbcells;
> +
> +	if (!np || !of_dma_xlate) {
> +		pr_err("%s: not enouth information provided\n", __func__);

Nit: typo:                      enough

> +		return -EINVAL;
> +	}
> +
> +	ofdma = kzalloc(sizeof(*ofdma), GFP_KERNEL);
> +	if (!ofdma)
> +		return -ENOMEM;
> +
> +	nbcells = (int *)of_get_property(np, "#dma-cells", NULL);
> +	if (!nbcells)
> +		/*
> +		 * no #dma-cells properties: assume no argument to
> +		 * dma-request property on slave side
> +		 */
> +		ofdma->of_dma_n_cells = 0;
> +	else
> +		ofdma->of_dma_n_cells = be32_to_cpup(nbcells);
> +
> +	ofdma->of_node = np;
> +	ofdma->of_dma_xlate = of_dma_xlate;
> +
> +	/* Now queue of_dma controller structure in list */
> +	list_add_tail_rcu(&ofdma->of_dma_controllers,&of_dma_list);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(of_dma_controller_register);
> +
> +/**
> + * of_dma_controller_free() - Remove a DMA controller from DT DMA helpers list
> + * @np:		device node of DMA controller
> + *
> + * Memory allocated by of_dma_controller_register() is freed here.
> + */
> +void of_dma_controller_free(struct device_node *np)
> +{
> +	struct of_dma	*ofdma;
> +
> +	ofdma = of_dma_find_controller(np);
> +	if (ofdma) {
> +		list_del_rcu(&ofdma->of_dma_controllers);
> +		kfree(ofdma);
> +	}
> +}
> +EXPORT_SYMBOL(of_dma_controller_free);
> +
> +/**
> + * of_get_dma_request() - Get the associated DMA request data
>    * @np:		device node to get DMA request from
> - * @propname:	property name containing DMA specifier(s)
>    * @index:	index of the DMA request
> - * @ctrl_np:	a device_node pointer to fill in
> + * @out_data:	a output that can be filled in by the of_dma_xlate() function
>    *
> - * Returns DMA number along to the dma controller node, or one of the errno
> - * value on the error condition. If @ctrl_np is not NULL the function also
> - * fills in the DMA controller device_node pointer.
> + * Returns return value of of_dma_xlate() and fills out_data (if provided).
> + * On error returns the appropriate errno value.
>    */
>   int of_get_dma_request(struct device_node *np, int index,
> -		       struct device_node **ctrl_np)
> +		       void *out_data)
>   {
> -	int ret = -EINVAL;
> -	struct of_phandle_args dma_spec;
> +	struct of_phandle_args	dma_spec;
> +	struct of_dma		*ofdma;
> +	int			ret;
>
>   	ret = of_parse_phandle_with_args(np, "dma-request", "#dma-cells",
>   					 index,&dma_spec);
>   	if (ret) {
> -		pr_debug("%s: can't parse dma property\n", __func__);
> +		pr_err("%s: can't parse dma property\n", np->full_name);
>   		goto err0;
>   	}
>
> -	if (dma_spec.args_count>  0)
> -		ret = dma_spec.args[0];
> +	if (list_empty(&of_dma_list)) {
> +		pr_debug("%s: empty DMA controller list\n",
> +			 np->full_name);
> +		ret = -ENOENT;
> +		goto err1;
> +	}
>
> -	if (ctrl_np)
> -		*ctrl_np = dma_spec.np;
> -	else
> -		of_node_put(dma_spec.np);
> +	ofdma = of_dma_find_controller(dma_spec.np);
> +	if (!ofdma) {
> +		pr_debug("%s: DMA controller %s isn't registered\n",
> +			 np->full_name, dma_spec.np->full_name);
> +		ret = -ENODEV;
> +		goto err1;
> +	}
>
> +	if (dma_spec.args_count != ofdma->of_dma_n_cells) {
> +		pr_debug("%s: wrong #dma-cells for %s\n",
> +			 np->full_name, dma_spec.np->full_name);
> +		ret = -EINVAL;
> +		goto err1;
> +	}
> +
> +	ret = ofdma->of_dma_xlate(&dma_spec, out_data);
> +
> +err1:
> +	of_node_put(dma_spec.np);
>   err0:
>   	pr_debug("%s exited with status %d\n", __func__, ret);
>   	return ret;
> @@ -55,6 +159,24 @@ err0:
>   EXPORT_SYMBOL(of_get_dma_request);
>
>   /**
> + * of_dma_xlate_onenumbercell() - Generic DMA xlate for direct one cell bindings
> + *
> + * Device Tree DMA translation function which works with one cell bindings
> + * where the cell values map directly to the hardware request number understood
> + * by the DMA controller.
> + */
> +int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec, void *req_nbr)

Nit: I'd rather use dma_req instead of req_nbr that can be understood as 
number of request lines.

> +{
> +	if (!dma_spec)
> +		return -EINVAL;
> +	if (WARN_ON(dma_spec->args_count != 1))
> +		return -EINVAL;
> +	*(int *)req_nbr = dma_spec->args[0];
> +	return 0;
> +}
> +EXPORT_SYMBOL(of_dma_xlate_onenumbercell);
> +
> +/**
>    * of_dma_count - Count DMA requests for a device
>    * @np:		device node to count DMAs for
>    *
> @@ -105,13 +227,14 @@ int of_dma_to_resource(struct device_node *dev, int index, struct resource *r)
>   {
>   	const char *name = NULL;
>   	int dma;
> +	int ret;
>
>   	if (!r)
>   		return -EINVAL;
>
> -	dma = of_get_dma_request(dev, index, NULL);
> -	if (dma<  0)
> -		return dma;
> +	ret = of_get_dma_request(dev, index,&dma);
> +	if (ret<  0)
> +		return ret;
>
>   	/*
>   	 * Get optional "dma-request-names" property to add a name
> diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
> index 575163d..fbf98de 100644
> --- a/include/linux/of_dma.h
> +++ b/include/linux/of_dma.h
> @@ -17,18 +17,38 @@
>
>   struct device_node;
>
> -#ifdef CONFIG_OF_GPIO
> +#ifdef CONFIG_OF_DMA
>
> +struct of_dma {
> +	struct list_head of_dma_controllers;
> +	struct device_node *of_node;
> +	int of_dma_n_cells;
> +	int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
> +};
> +
> +extern int of_dma_controller_register(struct device_node *np,
> +			int (*of_dma_xlate)(struct of_phandle_args *, void *));
> +extern void of_dma_controller_free(struct device_node *np);
>   extern int of_get_dma_request(struct device_node *np, int index,
> -		       struct device_node **ctrl_np);
> +			      void *out_data);
>   extern unsigned int of_dma_count(struct device_node *np);
>   extern int of_dma_to_resource(struct device_node *dev, int index,
>   			      struct resource *r);
>
> +extern int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
> +				      void *req_nbr);
>   #else /* CONFIG_OF_DMA */
>
> -static int of_get_dma_request(struct device_node *np, int index,
> -			      struct device_node **ctrl_np);
> +static int of_dma_controller_register(struct device_node *np,
> +			int (*of_dma_xlate)(struct of_phandle_args *, void *))
> +{
> +	return -ENOSYS;
> +}
> +
> +static void of_dma_controller_free(struct device_node *np) {}
> +
> +extern int of_get_dma_request(struct device_node *np, int index,
> +			      void *out_data)
>   {
>   	return -ENOSYS;
>   }
> @@ -44,6 +64,11 @@ static int of_dma_to_resource(struct device_node *dev, int index,
>   	return -ENOSYS;
>   }
>
> +static int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
> +				      void *req_nbr)
> +{
> +	return -ENOSYS;
> +}
>   #endif /* CONFIG_OF_DMA */
>
>   #endif /* __LINUX_OF_DMA_H */

Regards,
Benoit


From hs at denx.de  Mon Mar  5 06:09:57 2012
From: hs at denx.de (Heiko Schocher)
Date: Mon,  5 Mar 2012 12:09:57 +0100
Subject: [PATCH v3 0/7] ARM: davinci: add support for the am1808 based
 enbw_cmc board
Message-ID: <1330945804-3379-1-git-send-email-hs@denx.de>

This patchserie add support for the davinci am1808 based
enbw_cmc board.

Important: I rebased this patchserie against the irqdomain/next
branch from grant likely, as he suggested to rework the OF
intcontroller changes to the irqdomain work, branch found here:

http://git.secretlab.ca/?p=linux-2.6.git;a=shortlog;h=refs/heads/irqdomain/next

    git://git.secretlab.ca/git/linux-2.6.git irqdomain/next

    commit 280ad7fda5f95211857fda38960f2b6fdf6edd3e
    Author: Grant Likely <grant.likely at secretlab.ca>
    Date:   Fri Feb 24 14:58:54 2012 -0700

    mfd: twl-core: Add IRQ_DOMAIN dependency

changes for v2:
Post this patchserie now as v2, as reworked in the
comments I got for the RFC serie.

changes for v3:
- Interrupt Controller:
  - comment from Sergei Shtylyov:
    - rename compatible" prop to "ti,cp_intc"
    - cp_intc_init() is now also for the of case
      the name of the init function (it calls the
      "new" __cp_intc_init() function, which was
      the "old" cp_intc_init()). Through this
      rework the changes for OF is better visible.
      As the OF case uses the irq_domain rework from
      Grant Likely, maybe the none OF case can use
      this also, but this should be tested on a hw ...
 
Got no comments to the following points, I noted in the
RFC series, so posting this patchseries with them:

- ARM: davinci: configure davinci aemif chipselects through OF
  not moved to mfd, as mentioned in this discussion:
  http://davinci-linux-open-source.1494791.n2.nabble.com/PATCH-arm-davinci-configure-davinci-aemif-chipselects-through-OF-td7059739.html
  instead use a phandle in the DTS, so drivers which
  uses the davinci aemif, can call davinci_aemif_setup_timing_of()

  This is just thought as an RFC ... The enbw_cmc board
  support not really need to setup this bus timings, as
  they are setup in U-Boot ... but I want to post this,
  as I think, it is a nice to have, and I am not really
  sure, if this has to be a MFD device (If so, all bus
  interfaces for other SoCs should be converted also to
  MFD devices) ... as an example how this can be used
  I add this to the davinci nand controller OF support
  patch, in this patchserie.

- ARM: davinci: mux: add OF support
  I want to get rid of the pin setup code in board code ...
  This patch introduces a davinci_cfg_reg_of() function,
  which davinci drivers can call, if they found a
  "pinmux-handle", so used in the following drivers in
  this patchserie:

  drivers/net/ethernet/ti/davinci_emac
  drivers/i2c/busses/i2c-davinci.c
  drivers/mtd/nand/davinci_nand.c

- post this board support with USB support, even though
  USB is only working with the 10 ms "workaround", posted here:
  http://comments.gmane.org/gmane.linux.usb.general/54505
  I see this issue also on the AM1808 TMDXEXP1808L evalboard.

- MMC and USB are not using OF support yet, ideas how to port
  this are welcome. I need for USB and MMC board specific
  callbacks, how to solve this with OF support?

Signed-off-by: Heiko Schocher <hs at denx.de>
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: davinci-linux-open-source at linux.davincidsp.com
Cc: linux-mtd at lists.infradead.org
Cc: linux-i2c at vger.kernel.org
Cc: netdev at vger.kernel.org
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Wolfram Sang <w.sang at pengutronix.de>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Wolfgang Denk <wd at denx.de>
Cc: Sergei Shtylyov <sshtylyov at mvista.com>

Heiko Schocher (7):
  ARM: davinci, intc: Add OF support for TI interrupt controller
  ARM: davinci: configure davinci aemif chipselects through OF
  ARM: davinci: mux: add OF support
  ARM: davinci: net: davinci_emac: add OF support
  ARM: davinci: i2c: add OF support
  ARM: mtd: nand: davinci: add OF support for davinci nand controller
  ARM: davinci: add support for the am1808 based enbw_cmc board

 .../devicetree/bindings/arm/davinci/aemif.txt      |  119 ++++++
 .../bindings/arm/davinci/davinci_emac.txt          |   43 +++
 .../devicetree/bindings/arm/davinci/i2c.txt        |   33 ++
 .../devicetree/bindings/arm/davinci/intc.txt       |   27 ++
 .../devicetree/bindings/arm/davinci/mux.txt        |   40 ++
 .../devicetree/bindings/arm/davinci/nand.txt       |   74 ++++
 arch/arm/boot/dts/enbw_cmc.dts                     |  268 ++++++++++++++
 arch/arm/configs/enbw_cmc_defconfig                |  123 +++++++
 arch/arm/mach-davinci/Kconfig                      |    9 +
 arch/arm/mach-davinci/Makefile                     |    1 +
 arch/arm/mach-davinci/aemif.c                      |   86 +++++-
 arch/arm/mach-davinci/board-enbw-cmc.c             |  380 ++++++++++++++++++++
 arch/arm/mach-davinci/cp_intc.c                    |   87 ++++-
 arch/arm/mach-davinci/include/mach/aemif.h         |    1 +
 arch/arm/mach-davinci/include/mach/mux.h           |    2 +
 arch/arm/mach-davinci/include/mach/uncompress.h    |    1 +
 arch/arm/mach-davinci/mux.c                        |   73 ++++-
 drivers/i2c/busses/i2c-davinci.c                   |   37 ++
 drivers/mtd/nand/davinci_nand.c                    |   85 +++++-
 drivers/net/ethernet/ti/davinci_emac.c             |   94 +++++-
 20 files changed, 1569 insertions(+), 14 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/aemif.txt
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/davinci_emac.txt
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/i2c.txt
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/intc.txt
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/mux.txt
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/nand.txt
 create mode 100644 arch/arm/boot/dts/enbw_cmc.dts
 create mode 100644 arch/arm/configs/enbw_cmc_defconfig
 create mode 100644 arch/arm/mach-davinci/board-enbw-cmc.c

-- 
1.7.7.6



From hs at denx.de  Mon Mar  5 06:09:58 2012
From: hs at denx.de (Heiko Schocher)
Date: Mon,  5 Mar 2012 12:09:58 +0100
Subject: [PATCH v3 1/7] ARM: davinci,
 intc: Add OF support for TI interrupt controller
In-Reply-To: <1330945804-3379-1-git-send-email-hs@denx.de>
References: <1330945804-3379-1-git-send-email-hs@denx.de>
Message-ID: <1330945804-3379-2-git-send-email-hs@denx.de>

Add a function to initialize the Common Platform Interrupt Controller
(cp_intc) from TI used on OMAP-L1x SoCs using a device tree node.

Signed-off-by: Heiko Schocher <hs at denx.de>
Cc: davinci-linux-open-source at linux.davincidsp.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Wolfgang Denk <wd at denx.de>
Cc: Sergei Shtylyov <sshtylyov at mvista.com>

---
- changes for v2:
- add comment from Grant Likely:
  - migrate the whole interrupt controller to natively use an
    irq_domain. Rebased complete patchserie to:
    git://git.secretlab.ca/git/linux-2.6.git irqdomain/next

    commit 3a806bfcde2cc3e4853f2807b2e3c94e7ccaf450
    Author: Grant Likely <grant.likely at secretlab.ca>
    Date:   Fri Jan 27 06:44:34 2012 -0700

    irq_domain: mostly eliminate slow-path revmap lookups
- changes for v3:
  - add comments from Sergei Shtylyov:
    - rename compatible" prop to "ti,cp_intc"
    - cp_intc_init() is now also for the of case
      the name of the init function (it calls the
      "new" __cp_intc_init() function, which was
      the "old" cp_intc_init()). Through this
      rework the changes for OF is better visible.
      As the OF case uses the irq_domain rework from
      Grant Likely, maybe the none OF case can use
      this also, but this should be tested on a hw ...
  - rebased to:
    git://git.secretlab.ca/git/linux-2.6.git irqdomain/next

    commit 280ad7fda5f95211857fda38960f2b6fdf6edd3e
    Author: Grant Likely <grant.likely at secretlab.ca>
    Date:   Fri Feb 24 14:58:54 2012 -0700

    mfd: twl-core: Add IRQ_DOMAIN dependency

 .../devicetree/bindings/arm/davinci/intc.txt       |   27 ++++++
 arch/arm/mach-davinci/cp_intc.c                    |   87 +++++++++++++++++--
 2 files changed, 104 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/intc.txt

diff --git a/Documentation/devicetree/bindings/arm/davinci/intc.txt b/Documentation/devicetree/bindings/arm/davinci/intc.txt
new file mode 100644
index 0000000..dfd6a560
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/davinci/intc.txt
@@ -0,0 +1,27 @@
+* TI Common Platform Interrupt Controller
+
+Common Platform Interrupt Controller (cp_intc) is used on
+OMAP-L1x SoCs and can support several configurable number
+of interrupts.
+
+Main node required properties:
+
+- compatible : should be:
+	"ti,cp_intc"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The type shall be a <u32> and the value shall be 1.
+
+  The cell contains the interrupt number in the range [0-128].
+- ti,intc-size: Number of interrupts handled by the interrupt controller.
+- reg: physical base address and size of the intc registers map.
+
+Example:
+
+	intc: interrupt-controller at 1 {
+		compatible = "ti,cp_intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		ti,intc-size = <101>;
+		reg = <0xfffee000 0x2000>;
+	};
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index f83152d..585114a 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -9,9 +9,14 @@
  * kind, whether express or implied.
  */
 
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <mach/common.h>
 #include <mach/cp_intc.h>
@@ -99,18 +104,45 @@ static struct irq_chip cp_intc_irq_chip = {
 	.irq_set_wake	= cp_intc_set_wake,
 };
 
-void __init cp_intc_init(void)
+static struct irq_domain *cp_intc_domain;
+
+static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
+			  irq_hw_number_t hw)
 {
-	unsigned long num_irq	= davinci_soc_info.intc_irq_num;
+	pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
+
+	irq_set_chip(virq, &cp_intc_irq_chip);
+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+	irq_set_handler(virq, handle_edge_irq);
+	return 0;
+}
+
+static const struct irq_domain_ops cp_intc_host_ops = {
+	.map = cp_intc_host_map,
+	.xlate = irq_domain_xlate_onetwocell,
+};
+
+int __init __cp_intc_init(struct device_node *node,
+		struct device_node *parent)
+{
+	u32 num_irq		= davinci_soc_info.intc_irq_num;
 	u8 *irq_prio		= davinci_soc_info.intc_irq_prios;
 	u32 *host_map		= davinci_soc_info.intc_host_map;
 	unsigned num_reg	= BITS_TO_LONGS(num_irq);
-	int i;
+	int i, irq_base;
 
 	davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
-	davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
+	if (node) {
+		davinci_intc_base = of_iomap(node, 0);
+		if (of_property_read_u32(node, "ti,intc-size", &num_irq))
+			pr_warn("unable to get intc-size, default to %d\n",
+				num_irq);
+	} else {
+		davinci_intc_base = ioremap(davinci_soc_info.intc_base,
+					SZ_8K);
+	}
 	if (WARN_ON(!davinci_intc_base))
-		return;
+		return -EINVAL;
 
 	cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
 
@@ -165,13 +197,48 @@ void __init cp_intc_init(void)
 		for (i = 0; host_map[i] != -1; i++)
 			cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
 
-	/* Set up genirq dispatching for cp_intc */
-	for (i = 0; i < num_irq; i++) {
-		irq_set_chip(i, &cp_intc_irq_chip);
-		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-		irq_set_handler(i, handle_edge_irq);
+	if (node) {
+		irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
+		if (irq_base < 0) {
+			pr_warn("Couldn't allocate IRQ numbers\n");
+			irq_base = 0;
+		}
+
+		/* create a legacy host */
+		cp_intc_domain = irq_domain_add_legacy(node, num_irq,
+					irq_base, 0, &cp_intc_host_ops, NULL);
+		if (cp_intc_domain == NULL) {
+			pr_err("CP INTC: failed to allocate irq host!\n");
+			return -EINVAL;
+		}
+	} else {
+		/* Set up genirq dispatching for cp_intc */
+		for (i = 0; i < num_irq; i++) {
+			irq_set_chip(i, &cp_intc_irq_chip);
+			set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+			irq_set_handler(i, handle_edge_irq);
+		}
 	}
 
 	/* Enable global interrupt */
 	cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static struct of_device_id irq_match[] __initdata = {
+	{ .compatible = "ti,cp_intc", .data = __cp_intc_init, },
+	{ }
+};
+
+void __init cp_intc_init(void)
+{
+	of_irq_init(irq_match);
+}
+#else
+void __init cp_intc_init(void)
+{
+	__cp_intc_init(NULL, NULL);
 }
+#endif
-- 
1.7.7.6



From hs at denx.de  Mon Mar  5 06:09:59 2012
From: hs at denx.de (Heiko Schocher)
Date: Mon,  5 Mar 2012 12:09:59 +0100
Subject: [PATCH v3 2/7] ARM: davinci: configure davinci aemif chipselects
 through OF
In-Reply-To: <1330945804-3379-1-git-send-email-hs@denx.de>
References: <1330945804-3379-1-git-send-email-hs@denx.de>
Message-ID: <1330945804-3379-3-git-send-email-hs@denx.de>

Add support for configuring the aemif timing registers
through device tree. Introduce new compatible property
"ti,davinci-cs", see full description in
Documentation/devicetree/bindings/arm/davinci/aemif.txt

Signed-off-by: Heiko Schocher <hs at denx.de>
Cc: davinci-linux-open-source at linux.davincidsp.com
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Wolfgang Denk <wd at denx.de>
Cc: Sergei Shtylyov <sshtylyov at mvista.com>

---
- changes for v2
  - add comment from Sergei Shtylyov:
    - use of_property_read_u32()
    - Conding Style changes
  - add comment from Sekhar Nori:
    - add patch description
    - use davinci_aemif_setup_timing
    - change compatible node to "ti,davinci-aemif"

  - not moved to mfd, as mentioned in this discussion:
    http://davinci-linux-open-source.1494791.n2.nabble.com/PATCH-arm-davinci-configure-davinci-aemif-chipselects-through-OF-td7059739.html
    instead use a phandle in the DTS, so drivers which
    uses the davinci aemif, can call davinci_aemif_setup_timing_of()

    This is just thought as an RFC ... The enbw_cmc board
    support not really need to setup this bus timings, as
    they are setup in U-Boot ... but I want to post this,
    as I think, it is a nice to have ... as an example used
    in the davinci nand controller OF support patch, in this
    patchserie.
- no changes for v3

 .../devicetree/bindings/arm/davinci/aemif.txt      |  119 ++++++++++++++++++++
 arch/arm/mach-davinci/aemif.c                      |   86 ++++++++++++++-
 arch/arm/mach-davinci/include/mach/aemif.h         |    1 +
 3 files changed, 205 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/aemif.txt

diff --git a/Documentation/devicetree/bindings/arm/davinci/aemif.txt b/Documentation/devicetree/bindings/arm/davinci/aemif.txt
new file mode 100644
index 0000000..0dbb842
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/davinci/aemif.txt
@@ -0,0 +1,119 @@
+* Texas Instruments Davinci AEMIF
+
+This file provides information, what the device node for the
+davinci aemif interface contain.
+
+Required properties:
+- compatible: "ti,davinci-aemif";
+- #address-cells : Should be either two or three.  The first cell is the
+                   chipselect number, and the remaining cells are the
+                   offset into the chipselect.
+- #size-cells : Either one or two, depending on how large each chipselect
+                can be.
+- ranges : Each range corresponds to a single chipselect, and cover
+           the entire access window as configured.
+
+Optional properties:
+- none
+
+Optional subnodes:
+- Chipselect setup:
+	- compatible: "ti,davinci-cs";
+	- #address-cells = <1>;
+	- #size-cells = <1>;
+
+    Timing setup, all timings in nanoseconds
+	- cs:		chipselect (value 2,3,4 or 5)
+	- asize:	Asynchronous Data Bus Width.
+			value:
+			0: 8 bit
+			1: 16 bit
+	- ta:		Minimum Turn-Around time.
+	- rhold:	Read hold width
+	- rstrobe:	Read strobe width
+	- rsetup:	Read setup width
+	- whold:	Write hold width
+	- wstrobe:	Write strobe width
+	- wsetup:	Write setup width
+	- ew:		Extend Wait bit
+			value:
+			0: Extended wait cycles disabled.
+			1: Extended wait cycles enabled.
+	- ss:		Select Strobe bit.
+			value:
+			0: Normal Mode enabled.
+			1: Select Strobe Mode enabled.
+- CFI driver:
+  see: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+
+Example (enbw_cmc board):
+	aemif at 60000000 {
+		compatible = "ti,davinci-aemif";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		reg = <0x68000000 0x80000>;
+		ranges = <2 0 0x60000000 0x02000000
+			  3 0 0x62000000 0x02000000
+			  4 0 0x64000000 0x02000000
+			  5 0 0x66000000 0x02000000
+			  6 0 0x68000000 0x02000000>;
+		cs2 at 68000000 {
+			compatible = "ti,davinci-cs";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* all timings in nanoseconds */
+			cs = <2>;
+			asize = <1>;
+			ta = <0>;
+			rhold = <7>;
+			rstrobe = <42>;
+			rsetup = <14>;
+			whold = <7>;
+			wstrobe = <42>;
+			wsetup = <14>;
+			ew = <0>;
+			ss = <0>;
+		};
+		flash at 2,0 {
+			compatible = "cfi-flash";
+			reg = <2 0x0 0x400000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bank-width = <2>;
+			device-width = <2>;
+		};
+		nand_cs: cs3 at 68000000 {
+			compatible = "ti,davinci-cs";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* all timings in nanoseconds */
+			cs = <3>;
+			asize = <0>;
+			ta = <0>;
+			rhold = <7>;
+			rstrobe = <42>;
+			rsetup = <7>;
+			whold = <7>;
+			wstrobe = <14>;
+			wsetup = <7>;
+			ew = <0>;
+			ss = <0>;
+		};
+		nandflash at 3,0 {
+			compatible = "ti,davinci-nand";
+			reg = <3 0x0 0x807ff
+				6 0x0 0x8000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			mask_ale = <0>;
+			mask_cle = <0>;
+			mask_chipsel = <0>;
+			ecc_mode = <2>;
+			ecc_bits = <4>;
+			options = <0>;
+			bbt_options = <0x20000>;
+			pinmux-handle = <&nand_pins>;
+			timing-handle = <&nand_cs>;
+		};
+
+	};
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index 1ce70a9..e3d94a5 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -13,12 +13,14 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/time.h>
 
 #include <mach/aemif.h>
 
 /* Timing value configuration */
-
+#define ASIZE(x)	(x)
 #define TA(x)		((x) << 2)
 #define RHOLD(x)	((x) << 4)
 #define RSTROBE(x)	((x) << 7)
@@ -26,7 +28,10 @@
 #define WHOLD(x)	((x) << 17)
 #define WSTROBE(x)	((x) << 20)
 #define WSETUP(x)	((x) << 26)
+#define EW(x)		((x) << 30)
+#define SS(x)		((x) << 31)
 
+#define ASIZE_MAX	0x1
 #define TA_MAX		0x3
 #define RHOLD_MAX	0x7
 #define RSTROBE_MAX	0x3f
@@ -34,6 +39,8 @@
 #define WHOLD_MAX	0x7
 #define WSTROBE_MAX	0x3f
 #define WSETUP_MAX	0xf
+#define EW_MAX		0x1
+#define SS_MAX		0x1
 
 #define TIMING_MASK	(TA(TA_MAX) | \
 				RHOLD(RHOLD_MAX) | \
@@ -131,3 +138,80 @@ int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
 	return 0;
 }
 EXPORT_SYMBOL(davinci_aemif_setup_timing);
+
+#if defined(CONFIG_OF)
+static int dv_get_value(struct device_node *np, const char *name)
+{
+	u32 data;
+	int ret;
+
+	ret = of_property_read_u32(np, name, &data);
+	if (ret != 0)
+		return ret;
+
+	return data;
+}
+
+int davinci_aemif_setup_timing_of(struct device_node *np)
+{
+	struct device_node *parent;
+	struct davinci_aemif_timing t;
+	void __iomem *base;
+	unsigned val;
+	int asize, ew, ss;
+	int cs;
+	unsigned offset;
+	int ret;
+
+	if (!np)
+		return -ENODEV;
+
+	parent = np->parent;
+	if (!np)
+		return -ENODEV;
+
+	base = of_iomap(parent, 0);
+	if (!base)
+		return -EINVAL;
+
+	cs = dv_get_value(np, "cs");
+	if (cs < 2)
+		return -EINVAL;
+
+	t.ta		= dv_get_value(np, "ta");
+	t.rhold		= dv_get_value(np, "rhold");
+	t.rstrobe	= dv_get_value(np, "rstrobe");
+	t.rsetup	= dv_get_value(np, "rsetup");
+	t.whold		= dv_get_value(np, "whold");
+	t.wstrobe	= dv_get_value(np, "wstrobe");
+	t.wsetup	= dv_get_value(np, "wsetup");
+
+	ret = davinci_aemif_setup_timing(&t, base, cs);
+	if (ret != 0)
+		return ret;
+
+	/* setup none timing paramters */
+	offset = A1CR_OFFSET + cs * 4;
+	asize = dv_get_value(np, "asize");
+	ew = dv_get_value(np, "ew");
+	ss = dv_get_value(np, "ss");
+	val = __raw_readl(base + offset);
+	val &= TIMING_MASK;
+	val |= (asize & ACR_ASIZE_MASK);
+	if (ew)
+		val |= ACR_EW_MASK;
+	if (ss)
+		val |= ACR_SS_MASK;
+
+	__raw_writel(val, base + offset);
+
+	iounmap(base);
+	return 0;
+}
+#else
+int davinci_aemif_setup_timing_of(struct device_node *np)
+{
+	return 0;
+}
+#endif
+EXPORT_SYMBOL(davinci_aemif_setup_timing_of);
diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h
index 05b2934..f3bbec6 100644
--- a/arch/arm/mach-davinci/include/mach/aemif.h
+++ b/arch/arm/mach-davinci/include/mach/aemif.h
@@ -33,4 +33,5 @@ struct davinci_aemif_timing {
 
 int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
 					void __iomem *base, unsigned cs);
+int davinci_aemif_setup_timing_of(struct device_node *np);
 #endif
-- 
1.7.7.6



From hs at denx.de  Mon Mar  5 06:10:03 2012
From: hs at denx.de (Heiko Schocher)
Date: Mon,  5 Mar 2012 12:10:03 +0100
Subject: [PATCH v3 6/7] ARM: mtd: nand: davinci: add OF support for davinci
 nand controller
In-Reply-To: <1330945804-3379-1-git-send-email-hs@denx.de>
References: <1330945804-3379-1-git-send-email-hs@denx.de>
Message-ID: <1330945804-3379-7-git-send-email-hs@denx.de>

add OF support for the davinci nand controller.

Signed-off-by: Heiko Schocher <hs at denx.de>
Cc: davinci-linux-open-source at linux.davincidsp.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-mtd at lists.infradead.org
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Wolfgang Denk <wd at denx.de>
Cc: Scott Wood <scottwood at freescale.com>

---
- changes for v2:
  - add comments from Scott Wood:
    - add "ti,davinci-" prefix
    - Dashes are preferred to underscores
    - rename "nandflash" to "nand"
    - introduce new "ti,davinci" specific properties for setting
      up ecc_mode, ecc_bits, options and bbt options, instead
      using linux defines
    - readme fixes
- no changes for v3

 .../devicetree/bindings/arm/davinci/nand.txt       |   74 +++++++++++++++++
 drivers/mtd/nand/davinci_nand.c                    |   85 +++++++++++++++++++-
 2 files changed, 158 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/nand.txt

diff --git a/Documentation/devicetree/bindings/arm/davinci/nand.txt b/Documentation/devicetree/bindings/arm/davinci/nand.txt
new file mode 100644
index 0000000..e02874a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/davinci/nand.txt
@@ -0,0 +1,74 @@
+* Texas Instruments Davinci NAND
+
+This file provides information, what the device node for the
+davinci nand interface contain.
+
+Required properties:
+- compatible: "ti,davinci-nand";
+- reg : contain 2 offset/length values:
+        - offset and length for the access window
+        - offset and length for accessing the aemif control registers
+- ti,davinci-chipselect: Indicates on the davinci_nand driver which
+                         chipselect is used for accessing the nand.
+
+Recommended properties :
+- ti,davinci-mask-ale: mask for ale
+- ti,davinci-mask-cle: mask for cle
+- ti,davinci-mask-chipsel: mask for chipselect
+- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:
+		- "none"
+		- "soft"
+		- "hw"
+- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
+- ti,davinci-nand-buswidth: buswidth 8 or 16
+- ti,davinci-nand-use-bbt: use flash based bad block table support.
+
+Optional properties:
+- pinmux-handle: contains a handle to configure the pinmux settings.
+- timing-handle: contains a handle to setup aemif timing.
+
+Example (enbw_cmc board):
+aemif at 60000000 {
+	compatible = "ti,davinci-aemif";
+	#address-cells = <2>;
+	#size-cells = <1>;
+	reg = <0x68000000 0x80000>;
+	ranges = <2 0 0x60000000 0x02000000
+		  3 0 0x62000000 0x02000000
+		  4 0 0x64000000 0x02000000
+		  5 0 0x66000000 0x02000000
+		  6 0 0x68000000 0x02000000>;
+	nand_cs: cs3 at 68000000 {
+		compatible = "ti,davinci-cs";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		/* all timings in nanoseconds */
+		cs = <3>;
+		asize = <0>;
+		ta = <0>;
+		rhold = <7>;
+		rstrobe = <42>;
+		rsetup = <7>;
+		whold = <7>;
+		wstrobe = <14>;
+		wsetup = <7>;
+		ew = <0>;
+		ss = <0>;
+	};
+	nand at 3,0 {
+		compatible = "ti,davinci-nand";
+		reg = <3 0x0 0x807ff
+			6 0x0 0x8000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ti,davinci-chipselect = <1>;
+		ti,davinci-mask-ale = <0>;
+		ti,davinci-mask-cle = <0>;
+		ti,davinci-mask-chipsel = <0>;
+		ti,davinci-ecc-mode = "hw";
+		ti,davinci-ecc-bits = <4>;
+		ti,davinci-nand-use-bbt;
+		pinmux-handle = <&nand_pins>;
+		timing-handle = <&nand_cs>;
+	};
+};
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 6e56615..bdd6edc 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -33,9 +33,12 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/slab.h>
+#include <linux/of_i2c.h>
+#include <linux/of_device.h>
 
 #include <mach/nand.h>
 #include <mach/aemif.h>
+#include <mach/mux.h>
 
 /*
  * This is a device driver for the NAND flash controller found on the
@@ -518,9 +521,86 @@ static struct nand_ecclayout hwecc4_2048 __initconst = {
 	},
 };
 
+#if defined(CONFIG_OF)
+static const struct of_device_id davinci_nand_of_match[] = {
+	{.compatible = "ti,davinci-nand", },
+	{},
+}
+MODULE_DEVICE_TABLE(of, davinci_nand_of_match);
+
+static struct davinci_nand_pdata
+	*nand_davinci_get_pdata(struct platform_device *pdev)
+{
+	if ((pdev->dev.platform_data == NULL) &&
+		(pdev->dev.of_node)) {
+		struct device_node *tmp_np;
+		struct davinci_nand_pdata *pdata;
+		const char *mode;
+		u32 prop;
+		int len;
+
+		pdata =  kzalloc(sizeof(struct davinci_nand_pdata),
+				GFP_KERNEL);
+		pdev->dev.platform_data = pdata;
+		if (!pdata)
+			return NULL;
+		if (!of_property_read_u32(pdev->dev.of_node,
+			"ti,davinci-chipselect", &prop))
+			pdev->id = prop;
+		if (!of_property_read_u32(pdev->dev.of_node,
+			"ti,davinci-mask-ale", &prop))
+			pdata->mask_ale = prop;
+		if (!of_property_read_u32(pdev->dev.of_node,
+			"ti,davinci-mask-cle", &prop))
+			pdata->mask_cle = prop;
+		if (!of_property_read_u32(pdev->dev.of_node,
+			"ti,davinci-mask-chipsel", &prop))
+			pdata->mask_chipsel = prop;
+		if (!of_property_read_string(pdev->dev.of_node,
+			"ti,davinci-ecc-mode", &mode)) {
+			if (!strncmp("none", mode, 4))
+				pdata->ecc_mode = NAND_ECC_NONE;
+			if (!strncmp("soft", mode, 4))
+				pdata->ecc_mode = NAND_ECC_SOFT;
+			if (!strncmp("hw", mode, 2))
+				pdata->ecc_mode = NAND_ECC_HW;
+		}
+		if (!of_property_read_u32(pdev->dev.of_node,
+			"ti,davinci-ecc-bits", &prop))
+			pdata->ecc_bits = prop;
+		if (!of_property_read_u32(pdev->dev.of_node,
+			"ti,davinci-nand-buswidth", &prop))
+			if (prop == 16)
+				pdata->options |= NAND_BUSWIDTH_16;
+		if (of_find_property(pdev->dev.of_node,
+			"ti,davinci-nand-use-bbt", &len))
+			pdata->bbt_options = NAND_BBT_USE_FLASH;
+
+		tmp_np = of_parse_phandle(pdev->dev.of_node,
+				"pinmux-handle", 0);
+		if (tmp_np)
+			davinci_cfg_reg_of(tmp_np);
+
+		tmp_np = of_parse_phandle(pdev->dev.of_node,
+				"timing-handle", 0);
+		if (tmp_np)
+			davinci_aemif_setup_timing_of(tmp_np);
+	}
+
+	return pdev->dev.platform_data;
+}
+#else
+#define davinci_nand_of_match NULL
+static struct davinci_nand_pdata
+	*nand_davinci_get_pdata(struct platform_device *pdev)
+{
+	return pdev->dev.platform_data;
+}
+#endif
+
 static int __init nand_davinci_probe(struct platform_device *pdev)
 {
-	struct davinci_nand_pdata	*pdata = pdev->dev.platform_data;
+	struct davinci_nand_pdata	*pdata;
 	struct davinci_nand_info	*info;
 	struct resource			*res1;
 	struct resource			*res2;
@@ -530,6 +610,7 @@ static int __init nand_davinci_probe(struct platform_device *pdev)
 	uint32_t			val;
 	nand_ecc_modes_t		ecc_mode;
 
+	pdata = nand_davinci_get_pdata(pdev);
 	/* insist on board-specific configuration */
 	if (!pdata)
 		return -ENODEV;
@@ -815,6 +896,8 @@ static struct platform_driver nand_davinci_driver = {
 	.remove		= __exit_p(nand_davinci_remove),
 	.driver		= {
 		.name	= "davinci_nand",
+		.owner	= THIS_MODULE,
+		.of_match_table = davinci_nand_of_match,
 	},
 };
 MODULE_ALIAS("platform:davinci_nand");
-- 
1.7.7.6



From hs at denx.de  Mon Mar  5 06:10:00 2012
From: hs at denx.de (Heiko Schocher)
Date: Mon,  5 Mar 2012 12:10:00 +0100
Subject: [PATCH v3 3/7] ARM: davinci: mux: add OF support
In-Reply-To: <1330945804-3379-1-git-send-email-hs@denx.de>
References: <1330945804-3379-1-git-send-email-hs@denx.de>
Message-ID: <1330945804-3379-4-git-send-email-hs@denx.de>

add support for configuring the pinmux on davinci SoC
through OF.

Signed-off-by: Heiko Schocher <hs at denx.de>
Cc: davinci-linux-open-source at linux.davincidsp.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Wolfgang Denk <wd at denx.de>

---
This patch is just a RFC, as I want to get rid of the pin
setup code in board code ... This patch introduces a
davinci_cfg_reg_of() function, which davinci drivers can call,
if they found a pinmux-handle, so used in the following
drivers in this patchserie:

drivers/net/ethernet/ti/davinci_emac
drivers/i2c/busses/i2c-davinci.c
drivers/mtd/nand/davinci_nand.c

Comments are welcome.

- no changes for v2
- no changes for v3

 .../devicetree/bindings/arm/davinci/mux.txt        |   40 +++++++++++
 arch/arm/mach-davinci/include/mach/mux.h           |    2 +
 arch/arm/mach-davinci/mux.c                        |   73 +++++++++++++++++++-
 3 files changed, 114 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/mux.txt

diff --git a/Documentation/devicetree/bindings/arm/davinci/mux.txt b/Documentation/devicetree/bindings/arm/davinci/mux.txt
new file mode 100644
index 0000000..ecb026a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/davinci/mux.txt
@@ -0,0 +1,40 @@
+* Texas Instruments Davinci pinmux
+
+This file provides information, what the device node for the
+davinci pinmux interface contain.
+
+Required properties:
+- compatible: "ti,davinci-pinmux";
+- pins : contains a table with the following colums:
+   mux register: pinmux register
+   register offset: offset in register, which to change
+   mode mask: mode mask
+   mode value: mode value
+
+Optional properties:
+- none
+
+Example (enbw_cmc board):
+	emac_pins: pinmux at 1c14120 {
+		compatible = "ti,davinci-pinmux";
+		reg = <0x14120 0x1000>;
+		pins = < /*	muxreg	maskoff	modemsk muxmode */
+				2	4	15	8 /* MII TXEN */
+				2	8	15	8 /* MII TXCLK */
+				2	12	15	8 /* MII COL */
+				2	16	15	8 /* MII TXD_3 */
+				2	20	15	8 /* MII TXD_2 */
+				2	24	15	8 /* MII TXD_1 */
+				2	28	15	8 /* MII TXD_0 */
+				3	8	15	8 /* MII RXER */
+				3	12	15	8 /* MII CRS */
+				3	0	15	8 /* MII RXCLK */
+				3	4	15	8 /* MII RXDV */
+				3	16	15	8 /* MII RXD_3 */
+				3	20	15	8 /* MII RXD_2 */
+				3	24	15	8 /* MII RXD_1 */
+				3	28	15	8 /* MII RXD_0 */
+				4	0	15	8 /* MDIO CLK */
+				4	4	15	8 /* MDIO D */
+			>;
+	};
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index a7e92fc..3a62857 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -1205,6 +1205,7 @@ enum davinci_tnetv107x_index {
 /* setup pin muxing */
 extern int davinci_cfg_reg(unsigned long reg_cfg);
 extern int davinci_cfg_reg_list(const short pins[]);
+extern int davinci_cfg_reg_of(struct device_node *);
 #else
 /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
 static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
@@ -1212,6 +1213,7 @@ static inline int davinci_cfg_reg_list(const short pins[])
 {
 	return 0;
 }
+static int davinci_cfg_reg_of(struct device_node *) { return 0; };
 #endif
 
 #endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index f34a8dc..6b38072 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -18,18 +18,21 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/spinlock.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
 
 #include <mach/mux.h>
 #include <mach/common.h>
 
 static void __iomem *pinmux_base;
+static DEFINE_SPINLOCK(mux_spin_lock);
 
 /*
  * Sets the DAVINCI MUX register based on the table
  */
 int __init_or_module davinci_cfg_reg(const unsigned long index)
 {
-	static DEFINE_SPINLOCK(mux_spin_lock);
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	unsigned long flags;
 	const struct mux_config *cfg;
@@ -98,6 +101,74 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
 }
 EXPORT_SYMBOL(davinci_cfg_reg);
 
+#ifdef CONFIG_OF
+int davinci_cfg_reg_of(struct device_node *np)
+{
+	unsigned long flags;
+	int pinmux_map_len;
+	const unsigned int *pinmux_map;
+	u32 muxreg, maskoff, modemsk, muxmode;
+	unsigned int reg_orig = 0, reg = 0;
+	unsigned int mask, warn = 0;
+
+	pinmux_map = of_get_property(np, "pins", &pinmux_map_len);
+	if (pinmux_map == NULL) {
+		printk(KERN_ERR "pins is not set!\n");
+		return -EINVAL;
+	}
+
+	pinmux_map_len /= sizeof(unsigned int);
+	if ((pinmux_map_len % 4) != 0) {
+		printk(KERN_ERR "pins format wrong!\n");
+		return -EINVAL;
+	}
+
+	if (!pinmux_base) {
+		pinmux_base = of_iomap(np, 0);
+		if (WARN_ON(!pinmux_base))
+			return -ENOMEM;
+	}
+
+	while (pinmux_map_len > 0) {
+		muxreg = be32_to_cpu(pinmux_map[0]);
+		maskoff = be32_to_cpu(pinmux_map[1]);
+		modemsk = be32_to_cpu(pinmux_map[2]);
+		muxmode = be32_to_cpu(pinmux_map[3]);
+
+		/* Update the mux register in question */
+		if (modemsk) {
+			unsigned	tmp1, tmp2;
+
+			spin_lock_irqsave(&mux_spin_lock, flags);
+			reg_orig = __raw_readl(pinmux_base + muxreg);
+
+			mask = (modemsk << maskoff);
+			tmp1 = reg_orig & mask;
+			reg = reg_orig & ~mask;
+
+			tmp2 = (muxmode << maskoff);
+			reg |= tmp2;
+
+			if (tmp1 != tmp2)
+				warn = 1;
+
+			__raw_writel(reg, pinmux_base + muxreg);
+			spin_unlock_irqrestore(&mux_spin_lock, flags);
+		}
+		pinmux_map += 4;
+		pinmux_map_len -= 4;
+	}
+
+	return 0;
+}
+#else
+int davinci_cfg_reg_of(struct device_node *np)
+{
+	return 0;
+}
+#endif
+EXPORT_SYMBOL(davinci_cfg_reg_of);
+
 int __init_or_module davinci_cfg_reg_list(const short pins[])
 {
 	int i, error = -EINVAL;
-- 
1.7.7.6



From hs at denx.de  Mon Mar  5 06:10:02 2012
From: hs at denx.de (Heiko Schocher)
Date: Mon,  5 Mar 2012 12:10:02 +0100
Subject: [PATCH v3 5/7] ARM: davinci: i2c: add OF support
In-Reply-To: <1330945804-3379-1-git-send-email-hs@denx.de>
References: <1330945804-3379-1-git-send-email-hs@denx.de>
Message-ID: <1330945804-3379-6-git-send-email-hs@denx.de>

add of support for the davinci i2c driver.

Signed-off-by: Heiko Schocher <hs at denx.de>
Cc: davinci-linux-open-source at linux.davincidsp.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-i2c at vger.kernel.org
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Wolfram Sang <w.sang at pengutronix.de>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Wolfgang Denk <wd at denx.de>
Cc: Sylwester Nawrocki <s.nawrocki at samsung.com>

---
- changes for v2:
- add comments from Sylwester Nawrocki <s.nawrocki at samsung.com>:
  - use "cell-index" instead "id"
  - OF_DEV_AUXDATA in the machine code, instead pre-define platform
    device name
- add comment from Grant Likely:
  - removed "id" resp. "cell-index" completely
  - fixed documentation
  - use of_match_ptr()
  - use devm_kzalloc() for allocating plattform data mem
  - fixed a whitespace issue
- no changes for v3

 .../devicetree/bindings/arm/davinci/i2c.txt        |   33 +++++++++++++++++
 drivers/i2c/busses/i2c-davinci.c                   |   37 ++++++++++++++++++++
 2 files changed, 70 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/i2c.txt

diff --git a/Documentation/devicetree/bindings/arm/davinci/i2c.txt b/Documentation/devicetree/bindings/arm/davinci/i2c.txt
new file mode 100644
index 0000000..ba00d7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/davinci/i2c.txt
@@ -0,0 +1,33 @@
+* Texas Instruments Davinci I2C
+
+This file provides information, what the device node for the
+davinci i2c interface contain.
+
+Required properties:
+- compatible: "ti,davinci-i2c";
+- reg : Offset and length of the register set for the device
+
+Recommended properties :
+- interrupts : <a> standard interrupt property.
+- clock-frequency : desired I2C bus clock frequency in Hz.
+
+Optional properties:
+- bus-delay: bus delay in usec
+- pinmux-handle: Contains a handle to configure the pinmux settings.
+
+Example (enbw_cmc board):
+	i2c at 1c22000 {
+		compatible = "ti,davinci-i2c";
+		reg = <0x22000 0x1000>;
+		clock-frequency = <100000>;
+		interrupts = <15>;
+		interrupt-parent = <&intc>;
+		pinmux-handle = <&i2c1_pins>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dtt at 48 {
+				compatible = "national,lm75";
+				reg = <0x48>;
+			};
+	};
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index a76d85f..0d07d02 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -38,9 +38,12 @@
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
 #include <linux/gpio.h>
+#include <linux/of_i2c.h>
+#include <linux/of_device.h>
 
 #include <mach/hardware.h>
 #include <mach/i2c.h>
+#include <mach/mux.h>
 
 /* ----- global defines ----------------------------------------------- */
 
@@ -635,6 +638,12 @@ static struct i2c_algorithm i2c_davinci_algo = {
 	.functionality	= i2c_davinci_func,
 };
 
+static const struct of_device_id davinci_i2c_of_match[] = {
+	{.compatible = "ti,davinci-i2c", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
+
 static int davinci_i2c_probe(struct platform_device *pdev)
 {
 	struct davinci_i2c_dev *dev;
@@ -676,6 +685,31 @@ static int davinci_i2c_probe(struct platform_device *pdev)
 	dev->irq = irq->start;
 	platform_set_drvdata(pdev, dev);
 
+	if ((dev->dev->platform_data == NULL) &&
+		(pdev->dev.of_node)) {
+		struct device_node *pinmux_np;
+		struct davinci_i2c_platform_data *pdata;
+		u32 prop;
+
+		pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+		if (!pdata) {
+			r = -ENOMEM;
+			goto err_free_mem;
+		}
+		memcpy(pdata, &davinci_i2c_platform_data_default,
+			sizeof(*pdata));
+		dev->dev->platform_data = pdata;
+		if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
+			&prop))
+			pdata->bus_freq = prop / 1000;
+		if (!of_property_read_u32(pdev->dev.of_node, "bus-delay",
+			&prop))
+			pdata->bus_delay = prop;
+		pinmux_np = of_parse_phandle(pdev->dev.of_node,
+				"pinmux-handle", 0);
+		if (pinmux_np)
+			davinci_cfg_reg_of(pinmux_np);
+	}
 	dev->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(dev->clk)) {
 		r = -ENODEV;
@@ -711,6 +745,7 @@ static int davinci_i2c_probe(struct platform_device *pdev)
 	adap->algo = &i2c_davinci_algo;
 	adap->dev.parent = &pdev->dev;
 	adap->timeout = DAVINCI_I2C_TIMEOUT;
+	adap->dev.of_node = pdev->dev.of_node;
 
 	adap->nr = pdev->id;
 	r = i2c_add_numbered_adapter(adap);
@@ -718,6 +753,7 @@ static int davinci_i2c_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "failure adding adapter\n");
 		goto err_free_irq;
 	}
+	of_i2c_register_devices(adap);
 
 	return 0;
 
@@ -809,6 +845,7 @@ static struct platform_driver davinci_i2c_driver = {
 		.name	= "i2c_davinci",
 		.owner	= THIS_MODULE,
 		.pm	= davinci_i2c_pm_ops,
+		.of_match_table = of_match_ptr(davinci_i2c_of_match),
 	},
 };
 
-- 
1.7.7.6



From hs at denx.de  Mon Mar  5 06:10:01 2012
From: hs at denx.de (Heiko Schocher)
Date: Mon,  5 Mar 2012 12:10:01 +0100
Subject: [PATCH v3 4/7] ARM: davinci: net: davinci_emac: add OF support
In-Reply-To: <1330945804-3379-1-git-send-email-hs@denx.de>
References: <1330945804-3379-1-git-send-email-hs@denx.de>
Message-ID: <1330945804-3379-5-git-send-email-hs@denx.de>

add of support for the davinci_emac driver.

Signed-off-by: Heiko Schocher <hs at denx.de>
Cc: davinci-linux-open-source at linux.davincidsp.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: netdev at vger.kernel.org
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Wolfgang Denk <wd at denx.de>
Cc: Anatoly Sivov <mm05 at mail.ru>

---
- changes for v2:
  - add comment from Anatoly Sivov
    - fix typo in davinci_emac.txt
  - add comment from Grant Likely:
    - add prefix "ti,davinci-" to davinci specific property names
    - remove version property
    - use compatible name "ti,davinci-dm6460-emac"
    - use devm_kzalloc()
    - use of_match_ptr()
    - document all new properties
    - remove of_address_to_resource() and do not overwrite
      resource table
    - whitespace fixes
    - remove hw_ram_addr as it is not used in current
      board code
- no changes for v3

 .../bindings/arm/davinci/davinci_emac.txt          |   43 +++++++++
 drivers/net/ethernet/ti/davinci_emac.c             |   94 +++++++++++++++++++-
 2 files changed, 136 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/davinci/davinci_emac.txt

diff --git a/Documentation/devicetree/bindings/arm/davinci/davinci_emac.txt b/Documentation/devicetree/bindings/arm/davinci/davinci_emac.txt
new file mode 100644
index 0000000..a7b0911
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/davinci/davinci_emac.txt
@@ -0,0 +1,43 @@
+* Texas Instruments Davinci EMAC
+
+This file provides information, what the device node
+for the davinci_emac interface contain.
+
+Required properties:
+- compatible: "ti,davinci-dm6460-emac";
+- reg: Offset and length of the register set for the device
+- ti,davinci-ctrl-reg-offset: offset to control register
+- ti,davinci-ctrl-mod-reg-offset: offset to control module register
+- ti,davinci-ctrl-ram-offset: offset to control module ram
+- ti,davinci-ctrl-ram-size: size of control module ram
+- ti,davinci-rmii-en: use RMII
+- ti,davinci-no-bd-ram: has the emac controller BD RAM
+- phy-handle: Contains a phandle to an Ethernet PHY.
+              if not, davinci_emac driver defaults to 100/FULL
+- interrupts: interrupt mapping for the davinci emac interrupts sources:
+              4 sources: <Receive Threshold Interrupt
+			  Receive Interrupt
+			  Transmit Interrupt
+			  Miscellaneous Interrupt>
+- pinmux-handle: Contains a handle to configure the pinmux settings.
+
+Optional properties:
+- local-mac-address : 6 bytes, mac address
+
+Example (enbw_cmc board):
+	eth0: emac at 1e20000 {
+		compatible = "ti,davinci-dm6460-emac";
+		reg = <0x220000 0x4000>;
+		ti,davinci-ctrl-reg-offset = <0x3000>;
+		ti,davinci-ctrl-mod-reg-offset = <0x2000>;
+		ti,davinci-ctrl-ram-offset = <0>;
+		ti,davinci-ctrl-ram-size = <0x2000>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		interrupts = <33
+				34
+				35
+				36
+				>;
+		interrupt-parent = <&intc>;
+		pinmux-handle = <&emac_pins>;
+	};
diff --git a/drivers/net/ethernet/ti/davinci_emac.c b/drivers/net/ethernet/ti/davinci_emac.c
index 4fa0bcb..56e1c35 100644
--- a/drivers/net/ethernet/ti/davinci_emac.c
+++ b/drivers/net/ethernet/ti/davinci_emac.c
@@ -58,6 +58,12 @@
 #include <linux/io.h>
 #include <linux/uaccess.h>
 #include <linux/davinci_emac.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_net.h>
+
+#include <mach/mux.h>
 
 #include <asm/irq.h>
 #include <asm/page.h>
@@ -339,6 +345,9 @@ struct emac_priv {
 	u32 rx_addr_type;
 	atomic_t cur_tx;
 	const char *phy_id;
+#ifdef CONFIG_OF
+	struct device_node *phy_node;
+#endif
 	struct phy_device *phydev;
 	spinlock_t lock;
 	/*platform specific members*/
@@ -1760,6 +1769,82 @@ static const struct net_device_ops emac_netdev_ops = {
 #endif
 };
 
+#ifdef CONFIG_OF
+static struct emac_platform_data
+	*davinci_emac_of_get_pdata(struct platform_device *pdev,
+	struct emac_priv *priv)
+{
+	struct device_node *np;
+	struct device_node *pinmux_np;
+	struct emac_platform_data *pdata = NULL;
+	const u8 *mac_addr;
+	u32 data;
+	int ret;
+	int version;
+
+	np = pdev->dev.of_node;
+	if (!np)
+		goto nodata;
+	else
+		version = EMAC_VERSION_2;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+		if (!pdata)
+			goto nodata;
+	}
+	pdata->version = version;
+
+	mac_addr = of_get_mac_address(np);
+	if (mac_addr)
+		memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
+
+	ret = of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", &data);
+	if (!ret)
+		pdata->ctrl_reg_offset = data;
+
+	ret = of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
+		&data);
+	if (!ret)
+		pdata->ctrl_mod_reg_offset = data;
+
+	ret = of_property_read_u32(np, "ti,davinci-ctrl-ram-offset", &data);
+	if (!ret)
+		pdata->ctrl_ram_offset = data;
+
+	ret = of_property_read_u32(np, "ti,davinci-ctrl-ram-size", &data);
+	if (!ret)
+		pdata->ctrl_ram_size = data;
+
+	ret = of_property_read_u32(np, "ti,davinci-rmii-en", &data);
+	if (!ret)
+		pdata->rmii_en = data;
+
+	ret = of_property_read_u32(np, "ti,davinci-no-bd-ram", &data);
+	if (!ret)
+		pdata->no_bd_ram = data;
+
+	priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
+	if (!priv->phy_node)
+		pdata->phy_id = "";
+
+	pinmux_np = of_parse_phandle(np, "pinmux-handle", 0);
+	if (pinmux_np)
+		davinci_cfg_reg_of(pinmux_np);
+
+	pdev->dev.platform_data = pdata;
+nodata:
+	return  pdata;
+}
+#else
+static struct emac_platform_data
+	*davinci_emac_of_get_pdata(struct platform_device *pdev,
+	struct emac_priv *priv)
+{
+	return  pdev->dev.platform_data;
+}
+#endif
 /**
  * davinci_emac_probe: EMAC device probe
  * @pdev: The DaVinci EMAC device that we are removing
@@ -1803,7 +1888,7 @@ static int __devinit davinci_emac_probe(struct platform_device *pdev)
 
 	spin_lock_init(&priv->lock);
 
-	pdata = pdev->dev.platform_data;
+	pdata = davinci_emac_of_get_pdata(pdev, priv);
 	if (!pdata) {
 		dev_err(&pdev->dev, "no platform data\n");
 		rc = -ENODEV;
@@ -2013,6 +2098,12 @@ static const struct dev_pm_ops davinci_emac_pm_ops = {
 	.resume		= davinci_emac_resume,
 };
 
+static const struct of_device_id davinci_emac_of_match[] = {
+	{.compatible = "ti,davinci-dm6460-emac", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
+
 /**
  * davinci_emac_driver: EMAC platform driver structure
  */
@@ -2021,6 +2112,7 @@ static struct platform_driver davinci_emac_driver = {
 		.name	 = "davinci_emac",
 		.owner	 = THIS_MODULE,
 		.pm	 = &davinci_emac_pm_ops,
+		.of_match_table = of_match_ptr(davinci_emac_of_match),
 	},
 	.probe = davinci_emac_probe,
 	.remove = __devexit_p(davinci_emac_remove),
-- 
1.7.7.6



From hs at denx.de  Mon Mar  5 06:10:04 2012
From: hs at denx.de (Heiko Schocher)
Date: Mon,  5 Mar 2012 12:10:04 +0100
Subject: [PATCH v3 7/7] ARM: davinci: add support for the am1808 based
 enbw_cmc board
In-Reply-To: <1330945804-3379-1-git-send-email-hs@denx.de>
References: <1330945804-3379-1-git-send-email-hs@denx.de>
Message-ID: <1330945804-3379-8-git-send-email-hs@denx.de>

- AM1808 based board
- 64 MiB DDR ram
- 2 MiB Nor flash
- 128 MiB NAND flash
- use internal RTC
- I2C support
- hwmon lm75 support
- UBI/UBIFS support
- MMC support
- USB OTG support

Signed-off-by: Heiko Schocher <hs at denx.de>
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree-discuss at lists.ozlabs.org
Cc: davinci-linux-open-source at linux.davincidsp.com
Cc: linux-mtd at lists.infradead.org
Cc: linux-i2c at vger.kernel.org
Cc: netdev at vger.kernel.org
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Wolfram Sang <w.sang at pengutronix.de>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Wolfgang Denk <wd at denx.de>
Cc: Scott Wood <scottwood at freescale.com>
Cc: Sylwester Nawrocki <s.nawrocki at samsung.com>

---
- post this board support with USB support, even though
  USB is only working with the 10 ms "workaround", posted here:
  http://comments.gmane.org/gmane.linux.usb.general/54505
  I see this issue also on the AM1808 TMDXEXP1808L evalboard.
- MMC and USB are not using OF support yet, ideas how to port
  this are welcome. I need for USB and MMC boards board
  specific callbacks, how to solve this with OF support?

- changes for v2:
  - changes in the nand node due to comments from Scott Wood:
    - add "ti,davinci-" prefix
    - Dashes are preferred to underscores
    - rename "nandflash" to "nand"
    - introduce new "ti,davinci" specific properties for setting
      up ecc_mode, ecc_bits, options and bbt options, instead
      using linux defines
  - changes for i2c due to comments from Sylwester Nawrocki:
    - use "cell-index" instead "id"
    - OF_DEV_AUXDATA in the machine code, instead pre-define
      platform device name
  - add comment from Grant Likely for i2c:
    - removed "id" resp. "cell-index" completely
    - fixed documentation
    - use of_match_ptr()
    - use devm_kzalloc() for allocating plattform data mem
    - fixed a whitespace issue
  - add net comments from Grant Likely:
    - add prefix "ti,davinci-" to davinci specific property names
    - remove version property
    - use compatible name "ti,davinci-dm6460-emac"
  - add comment from Grant Likely:
    - rename compatible node
    - do not use cell-index
    - CONFIG_OF required for this board
    TODO:
    - create a generic board support file, as I got no
      answer to my ping to grant, maybe this could be done
      in a second step?
- changes for v3:
  - add comments from Sergei Shtylyov:
    - rename compatible" prop to "ti,cp_intc"
    - cp_intc_init now used for Interrupt controller init

 arch/arm/boot/dts/enbw_cmc.dts                  |  268 ++++++++++++++++
 arch/arm/configs/enbw_cmc_defconfig             |  123 ++++++++
 arch/arm/mach-davinci/Kconfig                   |    9 +
 arch/arm/mach-davinci/Makefile                  |    1 +
 arch/arm/mach-davinci/board-enbw-cmc.c          |  380 +++++++++++++++++++++++
 arch/arm/mach-davinci/include/mach/uncompress.h |    1 +
 6 files changed, 782 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/enbw_cmc.dts
 create mode 100644 arch/arm/configs/enbw_cmc_defconfig
 create mode 100644 arch/arm/mach-davinci/board-enbw-cmc.c

diff --git a/arch/arm/boot/dts/enbw_cmc.dts b/arch/arm/boot/dts/enbw_cmc.dts
new file mode 100644
index 0000000..143b2e2
--- /dev/null
+++ b/arch/arm/boot/dts/enbw_cmc.dts
@@ -0,0 +1,268 @@
+/*
+ * Device Tree for the EnBW CMC plattform
+ *
+ * Copyright 2011 DENX Software Engineering GmbH
+ * Heiko Schocher <hs at denx.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "EnBW CMC";
+	compatible = "enbw,cmc";
+
+	aliases {
+		ethernet0 = &eth0;
+	};
+
+	arm {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xfffee000 0x00020000>;
+		intc: interrupt-controller at 1 {
+			compatible = "ti,cp_intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			ti,intc-size = <101>;
+			reg = <0x0 0x2000>;
+		};
+	};
+	soc at 1c00000 {
+		compatible = "ti,da850";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x01c00000 0x400000>;
+
+		serial0: serial at 1c42000 {
+			compatible = "ti,da850", "ns16550a";
+			reg = <0x42000 0x100>;
+			clock-frequency = <150000000>;
+			reg-shift = <2>;
+			interrupts = <25>;
+			interrupt-parent = <&intc>;
+		};
+		serial1: serial at 1d0c000 {
+			compatible = "ti,da850", "ns16550a";
+			reg = <0x10c000 0x100>;
+			clock-frequency = <150000000>;
+			reg-shift = <2>;
+			interrupts = <53>;
+			interrupt-parent = <&intc>;
+		};
+		serial2: serial at 1d0d000 {
+			compatible = "ti,da850", "ns16550a";
+			reg = <0x10d000 0x100>;
+			clock-frequency = <150000000>;
+			reg-shift = <2>;
+			interrupts = <61>;
+			interrupt-parent = <&intc>;
+		};
+
+		nor_pins: nor_pinmux at 1c14120 {
+			compatible = "ti,davinci-pinmux";
+			reg = <0x14120 0x1000>;
+			pins = < /*	muxreg	maskoff	modemsk muxmode */
+					5	24	15	1 /* EMA_BA_1 */
+					6	0	15	1 /* EMA CLK */
+					6	24	15	1 /* EMA_WAIT_1 */
+					7	0	15	1 /* NEMA_CS_2 */
+					7	16	15	1 /* NEMA_WE */
+					7	20	15	1 /* NEMA_OE */
+					9	28	15	1 /* EMA_D_0 */
+					9	24	15	1 /* EMA_D_1 */
+					9	20	15	1 /* EMA_D_2 */
+					9	16	15	1 /* EMA_D_3 */
+					9	12	15	1 /* EMA_D_4 */
+					9	8	15	1 /* EMA_D_5 */
+					9	4	15	1 /* EMA_D_6 */
+					9	0	15	1 /* EMA_D_7 */
+					8	28	15	1 /* EMA_D_8 */
+					8	24	15	1 /* EMA_D_9 */
+					8	20	15	1 /* EMA_D_10 */
+					8	16	15	1 /* EMA_D_11 */
+					8	12	15	1 /* EMA_D_12 */
+					8	8	15	1 /* EMA_D_13 */
+					8	4	15	1 /* EMA_D_14 */
+					8	0	15	1 /* EMA_D_15 */
+					12	28	15	1 /* EMA_A_0 */
+					12	24	15	1 /* EMA_A_1 */
+					12	20	15	1 /* EMA_A_2 */
+					12	16	15	1 /* EMA_A_3 */
+					12	12	15	1 /* EMA_A_4 */
+					12	8	15	1 /* EMA_A_5 */
+					12	4	15	1 /* EMA_A_6 */
+					12	0	15	1 /* EMA_A_7 */
+					11	28	15	1 /* EMA_A_8 */
+					11	24	15	1 /* EMA_A_9 */
+					11	20	15	1 /* EMA_A_10 */
+					11	16	15	1 /* EMA_A_11 */
+					11	12	15	1 /* EMA_A_12 */
+					11	8	15	1 /* EMA_A_13 */
+					11	4	15	1 /* EMA_A_14 */
+					11	0	15	1 /* EMA_A_15 */
+					10	28	15	1 /* EMA_A_16 */
+					10	24	15	1 /* EMA_A_17 */
+					10	20	15	1 /* EMA_A_18 */
+					10	16	15	1 /* EMA_A_19 */
+					10	12	15	1 /* EMA_A_20 */
+					10	8	15	1 /* EMA_A_21 */
+					10	4	15	1 /* EMA_A_22 */
+					10	0	15	1 /* EMA_A_23 */
+				>;
+		};
+		nand_pins: nand_pinmux at 1c14120 {
+			compatible = "ti,davinci-pinmux";
+			reg = <0x14120 0x1000>;
+			pins = < /*	muxreg	maskoff	modemsk muxmode */
+					7	4	15	1 /* NEMA_CS_3 */
+				>;
+		};
+
+		emac_pins: pinmux at 1c14120 {
+			compatible = "ti,davinci-pinmux";
+			reg = <0x14120 0x1000>;
+			pins = < /*	muxreg	maskoff	modemsk muxmode */
+					2	4	15	8 /* MII TXEN */
+					2	8	15	8 /* MII TXCLK */
+					2	12	15	8 /* MII COL */
+					2	16	15	8 /* MII TXD_3 */
+					2	20	15	8 /* MII TXD_2 */
+					2	24	15	8 /* MII TXD_1 */
+					2	28	15	8 /* MII TXD_0 */
+					3	8	15	8 /* MII RXER */
+					3	12	15	8 /* MII CRS */
+					3	0	15	8 /* MII RXCLK */
+					3	4	15	8 /* MII RXDV */
+					3	16	15	8 /* MII RXD_3 */
+					3	20	15	8 /* MII RXD_2 */
+					3	24	15	8 /* MII RXD_1 */
+					3	28	15	8 /* MII RXD_0 */
+					4	0	15	8 /* MDIO CLK */
+					4	4	15	8 /* MDIO D */
+				>;
+		};
+
+		i2c1_pins: i2c_pinmux at 1c14120 {
+			compatible = "ti,davinci-pinmux";
+			reg = <0x14120 0x1000>;
+			pins = < /*	muxreg	maskoff	modemsk muxmode */
+					4	12	15	2 /* I2C0 SDA */
+					4	8	15	2 /* I2C0 SCL */
+				>;
+		};
+
+		eth0: emac at 1e20000 {
+			compatible = "ti,davinci-dm6460-emac";
+			reg = <0x220000 0x4000>;
+			ti,davinci-ctrl-reg-offset = <0x3000>;
+			ti,davinci-ctrl-mod-reg-offset = <0x2000>;
+			ti,davinci-ctrl-ram-offset = <0>;
+			ti,davinci-ctrl-ram-size = <0x2000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <33
+					34
+					35
+					36
+					>;
+			interrupt-parent = <&intc>;
+			pinmux-handle = <&emac_pins>;
+		};
+
+		i2c at 1c22000 {
+			compatible = "ti,davinci-i2c";
+			reg = <0x22000 0x1000>;
+			clock-frequency = <100000>;
+			interrupts = <15>;
+			interrupt-parent = <&intc>;
+			pinmux-handle = <&i2c1_pins>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dtt at 48 {
+				compatible = "national,lm75";
+				reg = <0x48>;
+			};
+		};
+	};
+	onchipram at 8000000 {
+		compatible = "ti,davinci-onchipram";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x80000000 0x20000>;
+	};
+	aemif at 60000000 {
+		compatible = "ti,davinci-aemif";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		reg = <0x68000000 0x80000>;
+		ranges = <2 0 0x60000000 0x02000000
+			  3 0 0x62000000 0x02000000
+			  4 0 0x64000000 0x02000000
+			  5 0 0x66000000 0x02000000
+			  6 0 0x68000000 0x02000000>;
+		cs2 at 68000000 {
+			compatible = "ti,davinci-cs";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* all timings in nanoseconds */
+			cs = <2>;
+			asize = <1>;
+			ta = <0>;
+			rhold = <7>;
+			rstrobe = <42>;
+			rsetup = <14>;
+			whold = <7>;
+			wstrobe = <42>;
+			wsetup = <14>;
+			ew = <0>;
+			ss = <0>;
+		};
+		flash at 2,0 {
+			compatible = "cfi-flash";
+			reg = <2 0x0 0x400000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bank-width = <2>;
+			device-width = <2>;
+		};
+		nand_cs: cs3 at 68000000 {
+			compatible = "ti,davinci-cs";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* all timings in nanoseconds */
+			cs = <3>;
+			asize = <0>;
+			ta = <0>;
+			rhold = <7>;
+			rstrobe = <42>;
+			rsetup = <7>;
+			whold = <7>;
+			wstrobe = <14>;
+			wsetup = <7>;
+			ew = <0>;
+			ss = <0>;
+		};
+		nand at 3,0 {
+			compatible = "ti,davinci-nand";
+			reg = <3 0x0 0x807ff
+				6 0x0 0x8000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ti,davinci-chipselect = <1>;
+			ti,davinci-mask-ale = <0>;
+			ti,davinci-mask-cle = <0>;
+			ti,davinci-mask-chipsel = <0>;
+			ti,davinci-ecc-mode = "hw";
+			ti,davinci-ecc-bits = <4>;
+			ti,davinci-nand-use-bbt;
+			pinmux-handle = <&nand_pins>;
+			timing-handle = <&nand_cs>;
+		};
+
+	};
+};
diff --git a/arch/arm/configs/enbw_cmc_defconfig b/arch/arm/configs/enbw_cmc_defconfig
new file mode 100644
index 0000000..9d98e7f
--- /dev/null
+++ b/arch/arm/configs/enbw_cmc_defconfig
@@ -0,0 +1,123 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_DAVINCI=y
+CONFIG_ARCH_DAVINCI_DA850=y
+# CONFIG_MACH_DAVINCI_DA850_EVM is not set
+CONFIG_GPIO_PCA953X=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_USE_OF=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6=y
+CONFIG_NETFILTER=y
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_DAVINCI=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=32768
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_TI_DAVINCI_EMAC=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DAVINCI=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_SENSORS_LM75=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_DAVINCI_WATCHDOG=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_DA8XX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_UAS=y
+CONFIG_USB_LIBUSUAL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FUSB300=y
+CONFIG_USB_ETH=y
+CONFIG_MMC=y
+CONFIG_MMC_DAVINCI=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_OMAP=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_UBIFS_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_DEBUG_FS=y
+CONFIG_TIMER_STATS=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_T10DIF=m
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 32d837d..4cb0469 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -202,6 +202,15 @@ config DA850_WL12XX
 	  Say Y if you want to use a wl1271 expansion card connected to the
 	  AM18x EVM.
 
+config MACH_ENBW_CMC
+	bool "EnBW Communication Module Compact"
+	default ARCH_DAVINCI_DA850
+	depends on ARCH_DAVINCI_DA850
+	select OF
+	help
+	  Say Y here to select the EnBW Communication Module Compact
+	  board.
+
 config GPIO_PCA953X
 	default MACH_DAVINCI_DA850_EVM
 
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 2db78bd..12f3166 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= board-da850-evm.o
 obj-$(CONFIG_MACH_TNETV107X)		+= board-tnetv107x-evm.o
 obj-$(CONFIG_MACH_MITYOMAPL138)		+= board-mityomapl138.o
 obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD)	+= board-omapl138-hawk.o
+obj-$(CONFIG_MACH_ENBW_CMC)		+= board-enbw-cmc.o
 
 # Power Management
 obj-$(CONFIG_CPU_FREQ)			+= cpufreq.o
diff --git a/arch/arm/mach-davinci/board-enbw-cmc.c b/arch/arm/mach-davinci/board-enbw-cmc.c
new file mode 100644
index 0000000..8cb60fb
--- /dev/null
+++ b/arch/arm/mach-davinci/board-enbw-cmc.c
@@ -0,0 +1,380 @@
+/*
+ * EnBW Communication Module Compact board
+ * Copyright 2011 DENX Software Engineering GmbH
+ * Author: Heiko Schocher <hs at denx.de>
+ *
+ * based on:
+ * TI DA850/OMAP-L138 EVM board
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Derived from: arch/arm/mach-davinci/board-da850-evm.c
+ * Original Copyrights follow:
+ *
+ * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/console.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/phy.h>
+#include <linux/phy_fixed.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/aemif.h>
+#include <mach/cp_intc.h>
+#include <mach/da8xx.h>
+#include <mach/mux.h>
+#include <mach/nand.h>
+#include <mach/spi.h>
+
+#define ENBW_CMC_MMCSD_CD_PIN          GPIO_TO_PIN(3, 13)
+
+/*
+ * USB1 VBUS is controlled by GPIO7[12], over-current is reported on GPIO7[8].
+ */
+#define DA850_USB_VBUS_PIN	GPIO_TO_PIN(7, 12)
+#define ON_BD_USB_OVC		GPIO_TO_PIN(7, 8)
+
+#if defined(CONFIG_USB_OHCI_HCD)
+static irqreturn_t enbw_cmc_usb_ocic_irq(int irq, void *dev_id);
+static da8xx_ocic_handler_t enbw_cmc_usb_ocic_handler;
+
+static int enbw_cmc_usb_set_power(unsigned port, int on)
+{
+	gpio_set_value(DA850_USB_VBUS_PIN, on);
+	return 0;
+}
+
+static int enbw_cmc_usb_get_power(unsigned port)
+{
+	return gpio_get_value(DA850_USB_VBUS_PIN);
+}
+
+static int enbw_cmc_usb_get_oci(unsigned port)
+{
+	return !gpio_get_value(ON_BD_USB_OVC);
+}
+
+static irqreturn_t enbw_cmc_usb_ocic_irq(int, void *);
+
+static int enbw_cmc_usb_ocic_notify(da8xx_ocic_handler_t handler)
+{
+	int irq         = gpio_to_irq(ON_BD_USB_OVC);
+	int error       = 0;
+
+	if (handler != NULL) {
+		enbw_cmc_usb_ocic_handler = handler;
+
+		error = request_irq(irq, enbw_cmc_usb_ocic_irq,
+					IRQF_DISABLED | IRQF_TRIGGER_RISING |
+					IRQF_TRIGGER_FALLING,
+					"OHCI over-current indicator", NULL);
+		if (error)
+			pr_err("%s: could not request IRQ to watch "
+				"over-current indicator changes\n", __func__);
+	} else {
+		free_irq(irq, NULL);
+	}
+	return error;
+}
+
+static struct da8xx_ohci_root_hub enbw_cmc_usb11_pdata = {
+	.set_power      = enbw_cmc_usb_set_power,
+	.get_power      = enbw_cmc_usb_get_power,
+	.get_oci        = enbw_cmc_usb_get_oci,
+	.ocic_notify    = enbw_cmc_usb_ocic_notify,
+	.potpgt         = (10 + 1) / 2,  /* 10 ms max */
+};
+
+static irqreturn_t enbw_cmc_usb_ocic_irq(int irq, void *dev_id)
+{
+	enbw_cmc_usb_ocic_handler(&enbw_cmc_usb11_pdata, 1);
+	return IRQ_HANDLED;
+}
+#endif
+
+static __init void enbw_cmc_usb_init(void)
+{
+	int ret;
+	u32 cfgchip2;
+
+	/* Set up USB clock/mode in the CFGCHIP2 register. */
+	cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
+
+	/* USB2.0 PHY reference clock is AUXCLK with 24MHz */
+	cfgchip2 &= ~CFGCHIP2_REFFREQ;
+	cfgchip2 |=  CFGCHIP2_REFFREQ_24MHZ;
+
+	/*
+	 * Select internal reference clock for USB 2.0 PHY
+	 * and use it as a clock source for USB 1.1 PHY
+	 * (this is the default setting anyway).
+	 */
+	cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX;
+	cfgchip2 |=  CFGCHIP2_USB2PHYCLKMUX;
+
+	cfgchip2 &= ~CFGCHIP2_OTGMODE;
+	cfgchip2 |=  CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
+
+	__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
+
+	ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
+	if (ret)
+		pr_warning("%s: USB 2.0 PinMux setup failed: %d\n",
+			   __func__, ret);
+	else {
+		/*
+		 * SP2525A @ 5V supplies 500mA,
+		 * with the power on to power good time of 10 ms.
+		 */
+		ret = da8xx_register_usb20(500, 10);
+		if (ret)
+			pr_warning("%s: USB 2.0 registration failed: %d\n",
+				   __func__, ret);
+	}
+
+#if defined(CONFIG_USB_OHCI_HCD)
+	ret = gpio_request_one(DA850_USB_VBUS_PIN,
+			GPIOF_DIR_OUT, "USB 1.1 VBUS");
+	if (ret < 0) {
+		pr_err("%s: failed to request GPIO for USB 1.1 port "
+			"power control: %d\n", __func__, ret);
+		return;
+	}
+	gpio_direction_input(DA850_USB_VBUS_PIN);
+
+	ret = gpio_request(ON_BD_USB_OVC, "ON_BD_USB_OVC");
+	if (ret) {
+		printk(KERN_ERR "%s: failed to request GPIO for USB 1.1 port "
+		       "over-current indicator: %d\n", __func__, ret);
+		gpio_free(DA850_USB_VBUS_PIN);
+		return;
+	}
+	gpio_direction_input(ON_BD_USB_OVC);
+
+	ret = da8xx_register_usb11(&enbw_cmc_usb11_pdata);
+	if (ret) {
+		pr_warning("%s: USB 1.1 registration failed: %d\n",
+			   __func__, ret);
+		gpio_free(ON_BD_USB_OVC);
+		gpio_free(DA850_USB_VBUS_PIN);
+	}
+#endif
+
+	return;
+}
+
+static int enbw_cmc_mmc_get_ro(int index)
+{
+	return 0;
+}
+
+static int enbw_cmc_mmc_get_cd(int index)
+{
+	return gpio_get_value(ENBW_CMC_MMCSD_CD_PIN) ? 1 : 0;
+}
+
+static struct davinci_mmc_config enbw_cmc_mmc_config = {
+	.get_ro		= enbw_cmc_mmc_get_ro,
+	.get_cd		= enbw_cmc_mmc_get_cd,
+	.wires		= 4,
+	.max_freq	= 50000000,
+	.caps		= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
+	.version	= MMC_CTLR_VERSION_2,
+};
+
+static int __init enbw_cmc_config_emac(void)
+{
+	void __iomem *cfg_chip3_base;
+	u32 val;
+	struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+	if (!machine_is_enbw_cmc())
+		return 0;
+
+	cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
+	val = __raw_readl(cfg_chip3_base);
+	val &= ~BIT(8);
+	pr_info("EMAC: MII PHY configured, RMII PHY will not be"
+						" functional\n");
+
+	/* configure the CFGCHIP3 register for MII */
+	__raw_writel(val, cfg_chip3_base);
+
+	/* use complete info from OF */
+	soc_info->emac_pdata = NULL;
+
+	return 0;
+}
+device_initcall(enbw_cmc_config_emac);
+
+static const s16 da850_dma0_rsv_chans[][2] = {
+	/* (offset, number) */
+	{-1, -1}
+};
+
+static const s16 da850_dma0_rsv_slots[][2] = {
+	/* (offset, number) */
+	{-1, -1}
+};
+
+static const s16 da850_dma1_rsv_chans[][2] = {
+	/* (offset, number) */
+	{-1, -1}
+};
+
+static const s16 da850_dma1_rsv_slots[][2] = {
+	/* (offset, number) */
+	{-1, -1}
+};
+
+static struct edma_rsv_info da850_edma_cc0_rsv = {
+	.rsv_chans	= da850_dma0_rsv_chans,
+	.rsv_slots	= da850_dma0_rsv_slots,
+};
+
+static struct edma_rsv_info da850_edma_cc1_rsv = {
+	.rsv_chans	= da850_dma1_rsv_chans,
+	.rsv_slots	= da850_dma1_rsv_slots,
+};
+
+static struct edma_rsv_info *da850_edma_rsv[2] = {
+	&da850_edma_cc0_rsv,
+	&da850_edma_cc1_rsv,
+};
+
+#ifdef CONFIG_CPU_FREQ
+static __init int da850_evm_init_cpufreq(void)
+{
+	switch (system_rev & 0xF) {
+	case 3:
+		da850_max_speed = 456000;
+		break;
+	case 2:
+		da850_max_speed = 408000;
+		break;
+	case 1:
+		da850_max_speed = 372000;
+		break;
+	}
+
+	return da850_register_cpufreq("pll0_sysclk3");
+}
+#else
+static __init int da850_evm_init_cpufreq(void) { return 0; }
+#endif
+
+struct of_dev_auxdata enbw_cmc_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "ti,davinci-wdt", NULL),
+	OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
+	OF_DEV_AUXDATA("ti,davinci-i2c", 0x01e28000, "i2c_davinci.2", NULL),
+	OF_DEV_AUXDATA("ti,davinci-dm6460-emac", 0x01e20000, "davinci_emac.1",
+			NULL),
+	{}
+};
+
+const struct of_device_id enbw_cmc_bus_match_table[] = {
+	{ .compatible = "simple-bus", },
+	{ .compatible = "ti,da850", },
+	{ .compatible = "ti,davinci-onchipram", },
+	{ .compatible = "ti,davinci-aemif", },
+	{} /* Empty terminated list */
+};
+
+static __init void enbw_cmc_init(void)
+{
+	int ret;
+
+	of_platform_populate(NULL, enbw_cmc_bus_match_table,
+		enbw_cmc_auxdata_lookup, NULL);
+
+	ret = da8xx_register_watchdog();
+	if (ret)
+		pr_warning("enbw_cmc_init: watchdog registration failed: %d\n",
+				ret);
+
+	ret = da850_register_edma(da850_edma_rsv);
+	if (ret)
+		pr_warning("enbw_cmc_init: edma registration failed: %d\n",
+				ret);
+
+	/*
+	 * shut down uart 0 this port is not used on the board
+	 */
+	__raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30);
+
+	ret = da8xx_register_rtc();
+	if (ret)
+		pr_warning("enbw_cmc_init: rtc setup failed: %d\n", ret);
+
+	ret = da850_evm_init_cpufreq();
+	if (ret)
+		pr_warning("enbw_cmc_init: cpufreq registration failed: %d\n",
+				ret);
+
+	ret = da8xx_register_cpuidle();
+	if (ret)
+		pr_warning("enbw_cmc_init: cpuidle registration failed: %d\n",
+				ret);
+
+	ret = gpio_request(ENBW_CMC_MMCSD_CD_PIN, "MMC CD\n");
+	if (ret)
+		pr_warning("enbw_cmc_init: can not open GPIO %d\n",
+				ENBW_CMC_MMCSD_CD_PIN);
+	gpio_direction_input(ENBW_CMC_MMCSD_CD_PIN);
+
+	ret = da850_register_mmcsd1(&enbw_cmc_mmc_config);
+	if (ret)
+		pr_warning("enbw_cmc_init: mmcsd1 registration failed:"
+				" %d\n", ret);
+
+	enbw_cmc_usb_init();
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+static int __init enbw_cmc_console_init(void)
+{
+	if (!machine_is_enbw_cmc())
+		return 0;
+
+	return add_preferred_console("ttyS", 2, "115200");
+}
+console_initcall(enbw_cmc_console_init);
+#endif
+
+static void __init enbw_cmc_map_io(void)
+{
+	da850_init();
+}
+
+static const char *enbw_cmc_board_compat[] __initconst = {
+	"enbw,cmc",
+	NULL
+};
+
+MACHINE_START(ENBW_CMC, "EnBW CMC")
+	.map_io		= enbw_cmc_map_io,
+	.init_irq	= cp_intc_init,
+	.timer		= &davinci_timer,
+	.init_machine	= enbw_cmc_init,
+	.dt_compat	= enbw_cmc_board_compat,
+	.dma_zone_size	= SZ_128M,
+	.restart	= da8xx_restart,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 9dc7cf9..2f21384 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -96,6 +96,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 		DEBUG_LL_DA8XX(davinci_da850_evm,	2);
 		DEBUG_LL_DA8XX(mityomapl138,		1);
 		DEBUG_LL_DA8XX(omapl138_hawkboard,	2);
+		DEBUG_LL_DA8XX(enbw_cmc,		2);
 
 		/* TNETV107x boards */
 		DEBUG_LL_TNETV107X(tnetv107x,		1);
-- 
1.7.7.6



From govindraj.raja at ti.com  Mon Mar  5 06:12:32 2012
From: govindraj.raja at ti.com (Govindraj.R)
Date: Mon, 5 Mar 2012 16:42:32 +0530
Subject: [PATCH] omap3_beagle: Init only uart3 used for console
Message-ID: <1330945952-14714-1-git-send-email-govindraj.raja@ti.com>

From: "Govindraj.R" <govindraj.raja at ti.com>

On beagle some of uart mux lines are used for other
purpose so init only uart3.

Uart2 rx line clashes with gpio_147 used for usb ehci
phy reset. Initializing uart2 pad_mux lines can break
ehci module on beagle xm.
(gpio_147 is available on uart2_rx in mode4 reference 
mux34xx.c -> uart2_rx.gpio_147)

Cc: Tony Lindgren <tony at atomide.com>
Cc: Kevin Hilman <khilman at ti.com>
Tested-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Tested-by: Robert Nelson <robertcnelson at gmail.com>
Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
---
 arch/arm/mach-omap2/board-omap3beagle.c |   50 ++++++++++++++++++++++++++++++-
 1 files changed, 49 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 817be06..a2e0052 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -493,6 +493,54 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
 	{ .reg_offset = OMAP_MUX_TERMINATOR },
 };
+
+static struct omap_device_pad uart3_pads[] __initdata = {
+	{
+		.name	= "uart3_cts_rctx.uart3_cts_rctx",
+		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+	},
+	{
+		.name	= "uart3_rts_sd.uart3_rts_sd",
+		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+	},
+	{
+		.name	= "uart3_tx_irtx.uart3_tx_irtx",
+		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+	},
+	{
+		.name	= "uart3_rx_irrx.uart3_rx_irrx",
+		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+	},
+};
+
+static inline void board_serial_init(void)
+{
+	struct omap_board_data uart3_bdata;
+	uart3_bdata.flags     = 0;
+	uart3_bdata.pads      = uart3_pads;
+	uart3_bdata.pads_cnt  = ARRAY_SIZE(uart3_pads);
+	uart3_bdata.id        = 2;
+
+	/*
+	 * Init only uart3 used as console
+	 * don't init other uarts as uart mux lines
+	 * might be used for other purpose on beagle board
+	 * ex: uart2_rx used by gpio_147 for usb_ehci phy reset.
+	 */
+	omap_serial_init_port(&uart3_bdata, NULL);
+}
+#else
+
+/*
+ * If mux is disabled from kernel probably we
+ * are relying on boot-loaders so we init all uarts
+ */
+static inline void board_serial_init(void)
+{
+	omap_serial_init();
+}
 #endif
 
 static void __init beagle_opp_init(void)
@@ -549,7 +597,7 @@ static void __init omap3_beagle_init(void)
 	platform_add_devices(omap3_beagle_devices,
 			ARRAY_SIZE(omap3_beagle_devices));
 	omap_display_init(&beagle_dss_data);
-	omap_serial_init();
+	board_serial_init();
 	omap_sdrc_init(mt46h32m32lf6_sdrc_params,
 				  mt46h32m32lf6_sdrc_params);
 
-- 
1.7.5.4



From hunold at linuxtv.org  Mon Mar  5 06:34:09 2012
From: hunold at linuxtv.org (Michael Hunold)
Date: Mon, 05 Mar 2012 12:34:09 +0100
Subject: iMX53 quick start board and SATA
In-Reply-To: <20120304083258.GE10743@S2101-09.ap.freescale.net>
References: <4F50C734.90302@linuxtv.org>
 <20120304083258.GE10743@S2101-09.ap.freescale.net>
Message-ID: <4F54A4B1.5000807@linuxtv.org>

Hello Shawn,

on 04.03.2012 09:33 Shawn Guo said the following:
> I think with the following patches in Linux 3.2, the i.MX53 SATA
> support should be there, though I never played with it.

> 904c04f [libata] ahci_platform: Add the board_ids and pi refer to different features
> d870ea1 MX53 Enable the AHCI SATA on MX53 SMD board
> 0661b82 MX53 Enable the AHCI SATA on MX53 LOCO board
> e97e303 MX53 Enable the AHCI SATA on MX53 ARD board
> 97915bd AHCI Add the AHCI SATA feature on the MX53 platforms

thank you very much for your answer.

I checked that the code is present in the kernel tree that I have used
and indeed it is.

After further investigation, I could see that imx53_add_ahci_imx() is
called correctly, but then imx_sata_init() was not called. This means
that the platform driver was not present.

I noticed that the AHCI platform driver in drivers/ata/ahci_platform.c
is only compiled when CONFIG_SATA_AHCI_PLATFORM=y is set and this was
not the case when the default config was used.

After enabling the necessary config option, the SATA port is now found
correctly:

ahci: SSS flag set, parallel bus scan disabled
ahci imx53-ahci.0: AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl
platform mode
ahci imx53-ahci.0: flags: ncq sntf stag pm led clo only pmp pio slum
part ccc
scsi0 : ahci_platform
ata1: SATA max UDMA/133 mmio [mem 0x10000000-0x10000fff] port 0x100 irq 28

Probably it would be a good idea to unconditionally select
CONFIG_SATA_AHCI_PLATFORM when MACH_MX53_LOCO is selected.

Best regards
Michael.


From hdoyu at nvidia.com  Mon Mar  5 06:47:21 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Mon, 5 Mar 2012 13:47:21 +0200
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
Message-ID: <20120305134721.0ab0d0e6de56fa30250059b1@nvidia.com>

Hi Marek,

On Wed, 29 Feb 2012 16:04:22 +0100
Marek Szyprowski <m.szyprowski at samsung.com> wrote:

> This patch add a complete implementation of DMA-mapping API for
> devices that have IOMMU support. All DMA-mapping calls are supported.
>
> This patch contains some of the code kindly provided by Krishna Reddy
> <vdumpa at nvidia.com> and Andrzej Pietrasiewicz <andrzej.p at samsung.com>
>
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
> ---
>  arch/arm/Kconfig                 |    8 +
>  arch/arm/include/asm/device.h    |    3 +
>  arch/arm/include/asm/dma-iommu.h |   34 ++
>  arch/arm/mm/dma-mapping.c        |  726 +++++++++++++++++++++++++++++++++++++-
>  arch/arm/mm/vmregion.h           |    2 +-
>  5 files changed, 758 insertions(+), 15 deletions(-)
>  create mode 100644 arch/arm/include/asm/dma-iommu.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 59102fb..5d9a0b6 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -44,6 +44,14 @@ config ARM
>  config ARM_HAS_SG_CHAIN
>         bool
>
> +config NEED_SG_DMA_LENGTH
> +       bool
> +
> +config ARM_DMA_USE_IOMMU
> +       select NEED_SG_DMA_LENGTH
> +       select ARM_HAS_SG_CHAIN
> +       bool
> +
>  config HAVE_PWM
>         bool
>
> diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
> index 6e2cb0e..b69c0d3 100644
> --- a/arch/arm/include/asm/device.h
> +++ b/arch/arm/include/asm/device.h
> @@ -14,6 +14,9 @@ struct dev_archdata {
>  #ifdef CONFIG_IOMMU_API
>         void *iommu; /* private IOMMU data */
>  #endif
> +#ifdef CONFIG_ARM_DMA_USE_IOMMU
> +       struct dma_iommu_mapping        *mapping;
> +#endif
>  };
>
>  struct omap_device;
> diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h
> new file mode 100644
> index 0000000..799b094
> --- /dev/null
> +++ b/arch/arm/include/asm/dma-iommu.h
> @@ -0,0 +1,34 @@
> +#ifndef ASMARM_DMA_IOMMU_H
> +#define ASMARM_DMA_IOMMU_H
> +
> +#ifdef __KERNEL__
> +
> +#include <linux/mm_types.h>
> +#include <linux/scatterlist.h>
> +#include <linux/dma-debug.h>
> +#include <linux/kmemcheck.h>
> +
> +struct dma_iommu_mapping {
> +       /* iommu specific data */
> +       struct iommu_domain     *domain;
> +
> +       void                    *bitmap;
> +       size_t                  bits;
> +       unsigned int            order;
> +       dma_addr_t              base;
> +
> +       spinlock_t              lock;
> +       struct kref             kref;
> +};
> +
> +struct dma_iommu_mapping *
> +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
> +                        int order);
> +
> +void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping);
> +
> +int arm_iommu_attach_device(struct device *dev,
> +                                       struct dma_iommu_mapping *mapping);
> +
> +#endif /* __KERNEL__ */
> +#endif
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index 67fe7e2..9b0db81 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -19,6 +19,8 @@
>  #include <linux/dma-mapping.h>
>  #include <linux/highmem.h>
>  #include <linux/slab.h>
> +#include <linux/iommu.h>
> +#include <linux/vmalloc.h>
>
>  #include <asm/memory.h>
>  #include <asm/highmem.h>
> @@ -26,6 +28,7 @@
>  #include <asm/tlbflush.h>
>  #include <asm/sizes.h>
>  #include <asm/mach/arch.h>
> +#include <asm/dma-iommu.h>
>
>  #include "mm.h"
>
> @@ -155,6 +158,21 @@ static u64 get_coherent_dma_mask(struct device *dev)
>         return mask;
>  }
>
> +static void __dma_clear_buffer(struct page *page, size_t size)
> +{
> +       void *ptr;
> +       /*
> +        * Ensure that the allocated pages are zeroed, and that any data
> +        * lurking in the kernel direct-mapped region is invalidated.
> +        */
> +       ptr = page_address(page);
> +       if (ptr) {
> +               memset(ptr, 0, size);
> +               dmac_flush_range(ptr, ptr + size);
> +               outer_flush_range(__pa(ptr), __pa(ptr) + size);
> +       }
> +}
> +
>  /*
>   * Allocate a DMA buffer for 'dev' of size 'size' using the
>   * specified gfp mask.  Note that 'size' must be page aligned.
> @@ -163,7 +181,6 @@ static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gf
>  {
>         unsigned long order = get_order(size);
>         struct page *page, *p, *e;
> -       void *ptr;
>         u64 mask = get_coherent_dma_mask(dev);
>
>  #ifdef CONFIG_DMA_API_DEBUG
> @@ -192,14 +209,7 @@ static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gf
>         for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
>                 __free_page(p);
>
> -       /*
> -        * Ensure that the allocated pages are zeroed, and that any data
> -        * lurking in the kernel direct-mapped region is invalidated.
> -        */
> -       ptr = page_address(page);
> -       memset(ptr, 0, size);
> -       dmac_flush_range(ptr, ptr + size);
> -       outer_flush_range(__pa(ptr), __pa(ptr) + size);
> +       __dma_clear_buffer(page, size);
>
>         return page;
>  }
> @@ -347,7 +357,7 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
>                 u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
>
>                 pte = consistent_pte[idx] + off;
> -               c->vm_pages = page;
> +               c->priv = page;
>
>                 do {
>                         BUG_ON(!pte_none(*pte));
> @@ -460,6 +470,14 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
>         return addr;
>  }
>
> +static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
> +{
> +       prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
> +                           pgprot_writecombine(prot) :
> +                           pgprot_dmacoherent(prot);
> +       return prot;
> +}
> +
>  /*
>   * Allocate DMA-coherent memory space and return both the kernel remapped
>   * virtual and bus address for that space.
> @@ -467,9 +485,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
>  void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
>                     gfp_t gfp, struct dma_attrs *attrs)
>  {
> -       pgprot_t prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
> -                       pgprot_writecombine(pgprot_kernel) :
> -                       pgprot_dmacoherent(pgprot_kernel);
> +       pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
>         void *memory;
>
>         if (dma_alloc_from_coherent(dev, size, handle, &memory))
> @@ -498,13 +514,14 @@ int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
>         c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
>         if (c) {
>                 unsigned long off = vma->vm_pgoff;
> +               struct page *pages = c->priv;
>
>                 kern_size = (c->vm_end - c->vm_start) >> PAGE_SHIFT;
>
>                 if (off < kern_size &&
>                     user_size <= (kern_size - off)) {
>                         ret = remap_pfn_range(vma, vma->vm_start,
> -                                             page_to_pfn(c->vm_pages) + off,
> +                                             page_to_pfn(pages) + off,
>                                               user_size << PAGE_SHIFT,
>                                               vma->vm_page_prot);
>                 }
> @@ -643,6 +660,9 @@ int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
>         int i, j;
>
>         for_each_sg(sg, s, nents, i) {
> +#ifdef CONFIG_NEED_SG_DMA_LENGTH
> +               s->dma_length = s->length;
> +#endif
>                 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
>                                                 s->length, dir, attrs);
>                 if (dma_mapping_error(dev, s->dma_address))
> @@ -748,3 +768,681 @@ static int __init dma_debug_do_init(void)
>         return 0;
>  }
>  fs_initcall(dma_debug_do_init);
> +
> +#ifdef CONFIG_ARM_DMA_USE_IOMMU
> +
> +/* IOMMU */
> +
> +static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
> +                                     size_t size)
> +{
> +       unsigned int order = get_order(size);
> +       unsigned int align = 0;
> +       unsigned int count, start;
> +       unsigned long flags;
> +
> +       count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
> +                (1 << mapping->order) - 1) >> mapping->order;
> +
> +       if (order > mapping->order)
> +               align = (1 << (order - mapping->order)) - 1;
> +
> +       spin_lock_irqsave(&mapping->lock, flags);
> +       start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
> +                                          count, align);
> +       if (start > mapping->bits) {
> +               spin_unlock_irqrestore(&mapping->lock, flags);
> +               return ARM_DMA_ERROR;
> +       }
> +
> +       bitmap_set(mapping->bitmap, start, count);
> +       spin_unlock_irqrestore(&mapping->lock, flags);
> +
> +       return mapping->base + (start << (mapping->order + PAGE_SHIFT));
> +}
> +
> +static inline void __free_iova(struct dma_iommu_mapping *mapping,
> +                              dma_addr_t addr, size_t size)
> +{
> +       unsigned int start = (addr - mapping->base) >>
> +                            (mapping->order + PAGE_SHIFT);
> +       unsigned int count = ((size >> PAGE_SHIFT) +
> +                             (1 << mapping->order) - 1) >> mapping->order;
> +       unsigned long flags;
> +
> +       spin_lock_irqsave(&mapping->lock, flags);
> +       bitmap_clear(mapping->bitmap, start, count);
> +       spin_unlock_irqrestore(&mapping->lock, flags);
> +}
> +
> +static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
> +{
> +       struct page **pages;
> +       int count = size >> PAGE_SHIFT;
> +       int array_size = count * sizeof(struct page *);
> +       int i=0;
> +
> +       if (array_size <= PAGE_SIZE)
> +               pages = kzalloc(array_size, gfp);
> +       else
> +               pages = vzalloc(array_size);
> +       if (!pages)
> +               return NULL;
> +
> +       while (count) {
> +               int j, order = __ffs(count);
> +
> +               pages[i] = alloc_pages(gfp | __GFP_NOWARN, order);
> +               while (!pages[i] && order)
> +                       pages[i] = alloc_pages(gfp | __GFP_NOWARN, --order);
> +               if (!pages[i])
> +                       goto error;
> +
> +               if (order)
> +                       split_page(pages[i], order);
> +               j = 1 << order;
> +               while (--j)
> +                       pages[i + j] = pages[i] + j;
> +
> +               __dma_clear_buffer(pages[i], PAGE_SIZE << order);
> +               i += 1 << order;
> +               count -= 1 << order;
> +       }
> +
> +       return pages;
> +error:
> +       while (--i)
> +               if (pages[i])
> +                       __free_pages(pages[i], 0);
> +       if (array_size < PAGE_SIZE)
> +               kfree(pages);
> +       else
> +               vfree(pages);
> +       return NULL;
> +}
> +
> +static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t size)
> +{
> +       int count = size >> PAGE_SHIFT;
> +       int array_size = count * sizeof(struct page *);
> +       int i;
> +       for (i=0; i < count; i++)
> +               if (pages[i])
> +                       __free_pages(pages[i], 0);
> +       if (array_size < PAGE_SIZE)
> +               kfree(pages);
> +       else
> +               vfree(pages);
> +       return 0;
> +}
> +
> +/*
> + * Create a CPU mapping for a specified pages
> + */
> +static void *
> +__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot)
> +{
> +       struct arm_vmregion *c;
> +       size_t align;
> +       size_t count = size >> PAGE_SHIFT;
> +       int bit;
> +
> +       if (!consistent_pte[0]) {
> +               pr_err("%s: not initialised\n", __func__);
> +               dump_stack();
> +               return NULL;
> +       }
> +
> +       /*
> +        * Align the virtual region allocation - maximum alignment is
> +        * a section size, minimum is a page size.  This helps reduce
> +        * fragmentation of the DMA space, and also prevents allocations
> +        * smaller than a section from crossing a section boundary.
> +        */
> +       bit = fls(size - 1);
> +       if (bit > SECTION_SHIFT)
> +               bit = SECTION_SHIFT;
> +       align = 1 << bit;
> +
> +       /*
> +        * Allocate a virtual address in the consistent mapping region.
> +        */
> +       c = arm_vmregion_alloc(&consistent_head, align, size,
> +                           gfp & ~(__GFP_DMA | __GFP_HIGHMEM));
> +       if (c) {
> +               pte_t *pte;
> +               int idx = CONSISTENT_PTE_INDEX(c->vm_start);
> +               int i = 0;
> +               u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
> +
> +               pte = consistent_pte[idx] + off;
> +               c->priv = pages;
> +
> +               do {
> +                       BUG_ON(!pte_none(*pte));
> +
> +                       set_pte_ext(pte, mk_pte(pages[i], prot), 0);
> +                       pte++;
> +                       off++;
> +                       i++;
> +                       if (off >= PTRS_PER_PTE) {
> +                               off = 0;
> +                               pte = consistent_pte[++idx];
> +                       }
> +               } while (i < count);
> +
> +               dsb();
> +
> +               return (void *)c->vm_start;
> +       }
> +       return NULL;
> +}
> +
> +/*
> + * Create a mapping in device IO address space for specified pages
> + */
> +static dma_addr_t
> +__iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
> +{
> +       struct dma_iommu_mapping *mapping = dev->archdata.mapping;
> +       unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
> +       dma_addr_t dma_addr, iova;
> +       int i, ret = ARM_DMA_ERROR;
> +
> +       dma_addr = __alloc_iova(mapping, size);
> +       if (dma_addr == ARM_DMA_ERROR)
> +               return dma_addr;
> +
> +       iova = dma_addr;
> +       for (i=0; i<count; ) {
> +               unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
> +               phys_addr_t phys = page_to_phys(pages[i]);
> +               unsigned int len, j;
> +
> +               for (j = i + 1; j < count; j++, next_pfn++)
> +                       if (page_to_pfn(pages[j]) != next_pfn)
> +                               break;
> +
> +               len = (j - i) << PAGE_SHIFT;
> +               ret = iommu_map(mapping->domain, iova, phys, len, 0);
> +               if (ret < 0)
> +                       goto fail;
> +               iova += len;
> +               i = j;
> +       }
> +       return dma_addr;
> +fail:
> +       iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
> +       __free_iova(mapping, dma_addr, size);
> +       return ARM_DMA_ERROR;
> +}
> +
> +static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
> +{
> +       struct dma_iommu_mapping *mapping = dev->archdata.mapping;
> +
> +       /*
> +        * add optional in-page offset from iova to size and align
> +        * result to page size
> +        */
> +       size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
> +       iova &= PAGE_MASK;
> +
> +       iommu_unmap(mapping->domain, iova, size);
> +       __free_iova(mapping, iova, size);
> +       return 0;
> +}
> +
> +static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
> +           dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
> +{
> +       pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
> +       struct page **pages;
> +       void *addr = NULL;
> +
> +       *handle = ARM_DMA_ERROR;
> +       size = PAGE_ALIGN(size);
> +
> +       pages = __iommu_alloc_buffer(dev, size, gfp);
> +       if (!pages)
> +               return NULL;
> +
> +       *handle = __iommu_create_mapping(dev, pages, size);
> +       if (*handle == ARM_DMA_ERROR)
> +               goto err_buffer;
> +
> +       addr = __iommu_alloc_remap(pages, size, gfp, prot);
> +       if (!addr)
> +               goto err_mapping;
> +
> +       return addr;
> +
> +err_mapping:
> +       __iommu_remove_mapping(dev, *handle, size);
> +err_buffer:
> +       __iommu_free_buffer(dev, pages, size);
> +       return NULL;
> +}
> +
> +static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
> +                   void *cpu_addr, dma_addr_t dma_addr, size_t size,
> +                   struct dma_attrs *attrs)
> +{
> +       struct arm_vmregion *c;
> +
> +       vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
> +       c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
> +
> +       if (c) {
> +               struct page **pages = c->priv;
> +
> +               unsigned long uaddr = vma->vm_start;
> +               unsigned long usize = vma->vm_end - vma->vm_start;
> +               int i = 0;
> +
> +               do {
> +                       int ret;
> +
> +                       ret = vm_insert_page(vma, uaddr, pages[i++]);
> +                       if (ret) {
> +                               pr_err("Remapping memory, error: %d\n", ret);
> +                               return ret;
> +                       }
> +
> +                       uaddr += PAGE_SIZE;
> +                       usize -= PAGE_SIZE;
> +               } while (usize > 0);
> +       }
> +       return 0;
> +}
> +
> +/*
> + * free a page as defined by the above mapping.
> + * Must not be called with IRQs disabled.
> + */
> +void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
> +                         dma_addr_t handle, struct dma_attrs *attrs)
> +{
> +       struct arm_vmregion *c;
> +       size = PAGE_ALIGN(size);
> +
> +       c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
> +       if (c) {
> +               struct page **pages = c->priv;
> +               __dma_free_remap(cpu_addr, size);
> +               __iommu_remove_mapping(dev, handle, size);
> +               __iommu_free_buffer(dev, pages, size);
> +       }
> +}
> +
> +/*
> + * Map a part of the scatter-gather list into contiguous io address space
> + */
> +static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
> +                         size_t size, dma_addr_t *handle,
> +                         enum dma_data_direction dir)
> +{
> +       struct dma_iommu_mapping *mapping = dev->archdata.mapping;
> +       dma_addr_t iova, iova_base;
> +       int ret = 0;
> +       unsigned int count;
> +       struct scatterlist *s;
> +
> +       size = PAGE_ALIGN(size);
> +       *handle = ARM_DMA_ERROR;
> +
> +       iova_base = iova = __alloc_iova(mapping, size);
> +       if (iova == ARM_DMA_ERROR)
> +               return -ENOMEM;
> +
> +       for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s))
> +       {
> +               phys_addr_t phys = page_to_phys(sg_page(s));
> +               unsigned int len = PAGE_ALIGN(s->offset + s->length);
> +
> +               if (!arch_is_coherent())
> +                       __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
> +
> +               ret = iommu_map(mapping->domain, iova, phys, len, 0);
> +               if (ret < 0)
> +                       goto fail;
> +               count += len >> PAGE_SHIFT;
> +               iova += len;
> +       }
> +       *handle = iova_base;
> +
> +       return 0;
> +fail:
> +       iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
> +       __free_iova(mapping, iova_base, size);
> +       return ret;
> +}
> +
> +/**
> + * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
> + * @dev: valid struct device pointer
> + * @sg: list of buffers
> + * @nents: number of buffers to map
> + * @dir: DMA transfer direction
> + *
> + * Map a set of buffers described by scatterlist in streaming mode for DMA.
> + * The scatter gather list elements are merged together (if possible) and
> + * tagged with the appropriate dma address and length. They are obtained via
> + * sg_dma_{address,length}.
> + */
> +int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
> +                    enum dma_data_direction dir, struct dma_attrs *attrs)
> +{
> +       struct scatterlist *s = sg, *dma = sg, *start = sg;
> +       int i, count = 0;
> +       unsigned int offset = s->offset;
> +       unsigned int size = s->offset + s->length;
> +       unsigned int max = dma_get_max_seg_size(dev);
> +
> +       for (i = 1; i < nents; i++) {
> +               s->dma_address = ARM_DMA_ERROR;
> +               s->dma_length = 0;
> +
> +               s = sg_next(s);
> +
> +               if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
> +                       if (__map_sg_chunk(dev, start, size, &dma->dma_address,
> +                           dir) < 0)
> +                               goto bad_mapping;
> +
> +                       dma->dma_address += offset;
> +                       dma->dma_length = size - offset;
> +
> +                       size = offset = s->offset;
> +                       start = s;
> +                       dma = sg_next(dma);
> +                       count += 1;
> +               }
> +               size += s->length;
> +       }
> +       if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir) < 0)
> +               goto bad_mapping;
> +
> +       dma->dma_address += offset;
> +       dma->dma_length = size - offset;
> +
> +       return count+1;
> +
> +bad_mapping:
> +       for_each_sg(sg, s, count, i)
> +               __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
> +       return 0;
> +}
> +
> +/**
> + * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
> + * @dev: valid struct device pointer
> + * @sg: list of buffers
> + * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
> + * @dir: DMA transfer direction (same as was passed to dma_map_sg)
> + *
> + * Unmap a set of streaming mode DMA translations.  Again, CPU access
> + * rules concerning calls here are the same as for dma_unmap_single().
> + */
> +void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
> +                       enum dma_data_direction dir, struct dma_attrs *attrs)
> +{
> +       struct scatterlist *s;
> +       int i;
> +
> +       for_each_sg(sg, s, nents, i) {
> +               if (sg_dma_len(s))
> +                       __iommu_remove_mapping(dev, sg_dma_address(s),
> +                                              sg_dma_len(s));
> +               if (!arch_is_coherent())
> +                       __dma_page_dev_to_cpu(sg_page(s), s->offset,
> +                                             s->length, dir);
> +       }
> +}
> +
> +/**
> + * arm_iommu_sync_sg_for_cpu
> + * @dev: valid struct device pointer
> + * @sg: list of buffers
> + * @nents: number of buffers to map (returned from dma_map_sg)
> + * @dir: DMA transfer direction (same as was passed to dma_map_sg)
> + */
> +void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
> +                       int nents, enum dma_data_direction dir)
> +{
> +       struct scatterlist *s;
> +       int i;
> +
> +       for_each_sg(sg, s, nents, i)
> +               if (!arch_is_coherent())
> +                       __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
> +
> +}
> +
> +/**
> + * arm_iommu_sync_sg_for_device
> + * @dev: valid struct device pointer
> + * @sg: list of buffers
> + * @nents: number of buffers to map (returned from dma_map_sg)
> + * @dir: DMA transfer direction (same as was passed to dma_map_sg)
> + */
> +void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
> +                       int nents, enum dma_data_direction dir)
> +{
> +       struct scatterlist *s;
> +       int i;
> +
> +       for_each_sg(sg, s, nents, i)
> +               if (!arch_is_coherent())
> +                       __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
> +}
> +
> +
> +/**
> + * arm_iommu_map_page
> + * @dev: valid struct device pointer
> + * @page: page that buffer resides in
> + * @offset: offset into page for start of buffer
> + * @size: size of buffer to map
> + * @dir: DMA transfer direction
> + *
> + * IOMMU aware version of arm_dma_map_page()
> + */
> +static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
> +            unsigned long offset, size_t size, enum dma_data_direction dir,
> +            struct dma_attrs *attrs)
> +{
> +       struct dma_iommu_mapping *mapping = dev->archdata.mapping;
> +       dma_addr_t dma_addr;
> +       int ret, len = PAGE_ALIGN(size + offset);
> +
> +       if (!arch_is_coherent())
> +               __dma_page_cpu_to_dev(page, offset, size, dir);
> +
> +       dma_addr = __alloc_iova(mapping, len);
> +       if (dma_addr == ARM_DMA_ERROR)
> +               return dma_addr;
> +
> +       ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0);
> +       if (ret < 0)
> +               goto fail;
> +
> +       return dma_addr + offset;
> +fail:
> +       __free_iova(mapping, dma_addr, len);
> +       return ARM_DMA_ERROR;
> +}
> +
> +/**
> + * arm_iommu_unmap_page
> + * @dev: valid struct device pointer
> + * @handle: DMA address of buffer
> + * @size: size of buffer (same as passed to dma_map_page)
> + * @dir: DMA transfer direction (same as passed to dma_map_page)
> + *
> + * IOMMU aware version of arm_dma_unmap_page()
> + */
> +static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
> +               size_t size, enum dma_data_direction dir,
> +               struct dma_attrs *attrs)
> +{
> +       struct dma_iommu_mapping *mapping = dev->archdata.mapping;
> +       dma_addr_t iova = handle & PAGE_MASK;
> +       struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
> +       int offset = handle & ~PAGE_MASK;
> +       int len = PAGE_ALIGN(size + offset);
> +
> +       if (!iova)
> +               return;
> +
> +       if (!arch_is_coherent())
> +               __dma_page_dev_to_cpu(page, offset, size, dir);
> +
> +       iommu_unmap(mapping->domain, iova, len);
> +       __free_iova(mapping, iova, len);
> +}
> +
> +static void arm_iommu_sync_single_for_cpu(struct device *dev,
> +               dma_addr_t handle, size_t size, enum dma_data_direction dir)
> +{
> +       struct dma_iommu_mapping *mapping = dev->archdata.mapping;
> +       dma_addr_t iova = handle & PAGE_MASK;
> +       struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
> +       unsigned int offset = handle & ~PAGE_MASK;
> +
> +       if (!iova)
> +               return;
> +
> +       if (!arch_is_coherent())
> +               __dma_page_dev_to_cpu(page, offset, size, dir);
> +}
> +
> +static void arm_iommu_sync_single_for_device(struct device *dev,
> +               dma_addr_t handle, size_t size, enum dma_data_direction dir)
> +{
> +       struct dma_iommu_mapping *mapping = dev->archdata.mapping;
> +       dma_addr_t iova = handle & PAGE_MASK;
> +       struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
> +       unsigned int offset = handle & ~PAGE_MASK;
> +
> +       if (!iova)
> +               return;
> +
> +       __dma_page_cpu_to_dev(page, offset, size, dir);
> +}
> +
> +struct dma_map_ops iommu_ops = {
> +       .alloc          = arm_iommu_alloc_attrs,
> +       .free           = arm_iommu_free_attrs,
> +       .mmap           = arm_iommu_mmap_attrs,
> +
> +       .map_page               = arm_iommu_map_page,
> +       .unmap_page             = arm_iommu_unmap_page,
> +       .sync_single_for_cpu    = arm_iommu_sync_single_for_cpu,
> +       .sync_single_for_device = arm_iommu_sync_single_for_device,
> +
> +       .map_sg                 = arm_iommu_map_sg,
> +       .unmap_sg               = arm_iommu_unmap_sg,
> +       .sync_sg_for_cpu        = arm_iommu_sync_sg_for_cpu,
> +       .sync_sg_for_device     = arm_iommu_sync_sg_for_device,
> +};
> +
> +/**
> + * arm_iommu_create_mapping
> + * @bus: pointer to the bus holding the client device (for IOMMU calls)
> + * @base: start address of the valid IO address space
> + * @size: size of the valid IO address space
> + * @order: accuracy of the IO addresses allocations
> + *
> + * Creates a mapping structure which holds information about used/unused
> + * IO address ranges, which is required to perform memory allocation and
> + * mapping with IOMMU aware functions.
> + *
> + * The client device need to be attached to the mapping with
> + * arm_iommu_attach_device function.
> + */
> +struct dma_iommu_mapping *
> +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
> +                        int order)
> +{
> +       unsigned int count = (size >> PAGE_SHIFT) - order;
> +       unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
> +       struct dma_iommu_mapping *mapping;
> +       int err = -ENOMEM;
> +
> +       mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
> +       if (!mapping)
> +               goto err;
> +
> +       mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
> +       if (!mapping->bitmap)
> +               goto err2;
> +
> +       mapping->base = base;
> +       mapping->bits = bitmap_size;

Shouldn't the above be as below?

>From 093c77ac6f19899679f2f2447a9d2c684eab7b2e Mon Sep 17 00:00:00 2001
From: Hiroshi DOYU <hdoyu at nvidia.com>
Date: Mon, 5 Mar 2012 13:04:38 +0200
Subject: [PATCH 1/1] dma-mapping: Fix mapping->bits size

Amount of bits should be mutiplied by BITS_PER_BITE.

Signed-off-by: Hiroshi DOYU <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index e55f425..5ec7747 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1495,7 +1495,7 @@ arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
 		goto err2;
 
 	mapping->base = base;
-	mapping->bits = bitmap_size;
+	mapping->bits = BITS_PER_BYTE * bitmap_size;
 	mapping->order = order;
 	spin_lock_init(&mapping->lock);
 
-- 
1.7.5.4



From broonie at opensource.wolfsonmicro.com  Mon Mar  5 06:52:10 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 11:52:10 +0000
Subject: [PATCH 2/2] mmc: sdhci-s3c: Enable runtime power management
In-Reply-To: <4F549A0A.5020402@samsung.com>
References: <4F51697C.40408@samsung.com>
 <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1330735602-22409-2-git-send-email-broonie@opensource.wolfsonmicro.com>
 <4F549A0A.5020402@samsung.com>
Message-ID: <20120305115209.GA3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 07:48:42PM +0900, Jaehoon Chung wrote:
> On 03/03/2012 09:46 AM, Mark Brown wrote:

> > +	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);

> Could you explain why use 50ms? 

It's essentially a random number, some other devices use the same one.
We're just trying to avoid suspending between back to back requests.

> > +	pm_runtime_use_autosuspend(&pdev->dev);
> > +	pm_suspend_ignore_children(&pdev->dev, 1);

> Is there reason that ignore_children use to set the true?

So that we can suspend the host without having to have the MMC card
suspended (the host suspend is not visible to the card).
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From broonie at opensource.wolfsonmicro.com  Mon Mar  5 06:56:12 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 11:56:12 +0000
Subject: [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120305080623.GD16232@S2101-09.ap.freescale.net>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
 <20120304133818.GE3083@opensource.wolfsonmicro.com>
 <20120305080623.GD16232@S2101-09.ap.freescale.net>
Message-ID: <20120305115612.GB3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 04:06:25PM +0800, Shawn Guo wrote:
> On Sun, Mar 04, 2012 at 01:38:18PM +0000, Mark Brown wrote:

> > This looks like there's a problem with the bindings, why are you
> > registering the DMA device from the card?

> There is a dma node in the device tree to instantiate the dma device
> backed by a dmaengine driver.  As a client peripheral of that dmaengine
> device, the SSI owns just a dma request/event number.  With the number
> encoded in SSI node, there is no hardware resource to be claimed by
> that pcm-device, so we do not have it in device tree.  Then we have
> to register this device in either fsl_ssi driver or machine driver.
> I chose to do something that tegra is doing, registering the pcm device
> in machine driver, to keep fsl_ssi away from imx specific bits as much
> as possible.

The above sounds like you have a unified DAI and PCM driver.  In that
case they should either both be using the same device or should have
some sort of parent/child/sibling relationship.  Either way the machine
driver really shouldn't be involved in instantiating things, perhaps
arch/arm but not the audio machine driver.
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From haojian.zhuang at marvell.com  Mon Mar  5 07:21:45 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Mon,  5 Mar 2012 20:21:45 +0800
Subject: [PATCH v2 1/7] serial: pxa: add OF support
In-Reply-To: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330950111-30797-2-git-send-email-haojian.zhuang@marvell.com>

Parse uart device id from alias in DTS file.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/tty/serial/pxa.c |   65 +++++++++++++++++++++++++++++++++++++--------
 1 files changed, 53 insertions(+), 12 deletions(-)

diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
index 5c8e3bb..a71855b 100644
--- a/drivers/tty/serial/pxa.c
+++ b/drivers/tty/serial/pxa.c
@@ -36,6 +36,7 @@
 #include <linux/circ_buf.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
@@ -44,6 +45,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
+#define PXA_NAME_LEN		8
+
 struct uart_pxa_port {
 	struct uart_port        port;
 	unsigned char           ier;
@@ -781,6 +784,39 @@ static const struct dev_pm_ops serial_pxa_pm_ops = {
 };
 #endif
 
+static struct of_device_id serial_pxa_dt_ids[] = {
+	{ .compatible = "mrvl,pxa-uart", },
+	{ .compatible = "mrvl,mmp-uart", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids);
+
+#ifdef CONFIG_OF
+static int serial_pxa_probe_dt(struct platform_device *pdev,
+			       struct uart_pxa_port *sport)
+{
+	struct device_node *np = pdev->dev.of_node;
+	int ret;
+
+	if (!np)
+		return 1;
+
+	ret = of_alias_get_id(np, "serial");
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+		return ret;
+	}
+	sport->port.line = ret;
+	return 0;
+}
+#else
+static int serial_pxa_probe_dt(struct platform_device *pdev,
+			       struct uart_pxa_port *sport)
+{
+	return 1;
+}
+#endif
+
 static int serial_pxa_probe(struct platform_device *dev)
 {
 	struct uart_pxa_port *sport;
@@ -808,34 +844,37 @@ static int serial_pxa_probe(struct platform_device *dev)
 	sport->port.irq = irqres->start;
 	sport->port.fifosize = 64;
 	sport->port.ops = &serial_pxa_pops;
-	sport->port.line = dev->id;
 	sport->port.dev = &dev->dev;
 	sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
 	sport->port.uartclk = clk_get_rate(sport->clk);
-
-	switch (dev->id) {
-	case 0: sport->name = "FFUART"; break;
-	case 1: sport->name = "BTUART"; break;
-	case 2: sport->name = "STUART"; break;
-	case 3: sport->name = "HWUART"; break;
-	default:
-		sport->name = "???";
-		break;
+	sport->name = kzalloc(PXA_NAME_LEN, GFP_KERNEL);
+	if (!sport->name) {
+		ret = -ENOMEM;
+		goto err_clk;
 	}
 
+	ret = serial_pxa_probe_dt(dev, sport);
+	if (ret > 0)
+		sport->port.line = dev->id;
+	else if (ret < 0)
+		goto err_clk;
+	snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
+
 	sport->port.membase = ioremap(mmres->start, resource_size(mmres));
 	if (!sport->port.membase) {
 		ret = -ENOMEM;
-		goto err_clk;
+		goto err_name;
 	}
 
-	serial_pxa_ports[dev->id] = sport;
+	serial_pxa_ports[sport->port.line] = sport;
 
 	uart_add_one_port(&serial_pxa_reg, &sport->port);
 	platform_set_drvdata(dev, sport);
 
 	return 0;
 
+ err_name:
+	kfree(sport->name);
  err_clk:
 	clk_put(sport->clk);
  err_free:
@@ -850,6 +889,7 @@ static int serial_pxa_remove(struct platform_device *dev)
 	platform_set_drvdata(dev, NULL);
 
 	uart_remove_one_port(&serial_pxa_reg, &sport->port);
+	kfree(sport->name);
 	clk_put(sport->clk);
 	kfree(sport);
 
@@ -866,6 +906,7 @@ static struct platform_driver serial_pxa_driver = {
 #ifdef CONFIG_PM
 		.pm	= &serial_pxa_pm_ops,
 #endif
+		.of_match_table = serial_pxa_dt_ids,
 	},
 };
 
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Mon Mar  5 07:21:44 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Mon,  5 Mar 2012 20:21:44 +0800
Subject: [PATCH v2 0/7] ARM: mmp: support OF on pxa168
Message-ID: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>

Add OF support on gpio/serial/rtc/i2c components in pxa168 aspenite.

Changelog v2:
1. Append interrupt-names property in rtc-sa1100, gpio-pxa driver.
2. Append alias in i2c-pxa driver.
3. Avoid embed CONFIG_OF in i2c-pxa driver.



From haojian.zhuang at marvell.com  Mon Mar  5 07:21:46 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Mon,  5 Mar 2012 20:21:46 +0800
Subject: [PATCH v2 2/7] rtc: sa1100: add OF support
In-Reply-To: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330950111-30797-3-git-send-email-haojian.zhuang@marvell.com>

Add OF support on rtc-sa1100.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/rtc/rtc-sa1100.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index 962510c..e443b78 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -30,6 +30,7 @@
 #include <linux/interrupt.h>
 #include <linux/slab.h>
 #include <linux/string.h>
+#include <linux/of.h>
 #include <linux/pm.h>
 #include <linux/bitops.h>
 
@@ -349,6 +350,13 @@ static const struct dev_pm_ops sa1100_rtc_pm_ops = {
 };
 #endif
 
+static struct of_device_id sa1100_rtc_dt_ids[] = {
+	{ .compatible = "mrvl,sa1100-rtc", },
+	{ .compatible = "mrvl,mmp-rtc", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids);
+
 static struct platform_driver sa1100_rtc_driver = {
 	.probe		= sa1100_rtc_probe,
 	.remove		= sa1100_rtc_remove,
@@ -357,6 +365,7 @@ static struct platform_driver sa1100_rtc_driver = {
 #ifdef CONFIG_PM
 		.pm	= &sa1100_rtc_pm_ops,
 #endif
+		.of_match_table = sa1100_rtc_dt_ids,
 	},
 };
 
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Mon Mar  5 07:21:48 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Mon,  5 Mar 2012 20:21:48 +0800
Subject: [PATCH v2 4/7] ARM: mmp: enable rtc clk in pxa168
In-Reply-To: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330950111-30797-5-git-send-email-haojian.zhuang@marvell.com>

Enable clk of rtc-sa1100 device in pxa168.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/mach-mmp/pxa168.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 9f61256..aa62d0c 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -65,6 +65,7 @@ static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
 static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
 static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
+static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
 
 static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(lcd, LCD, 0x7f, 312000000);
@@ -93,6 +94,7 @@ static struct clk_lookup pxa168_clkregs[] = {
 	INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
 	INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
 	INIT_CLKREG(&clk_usb, "pxa168-ehci", "PXA168-USBCLK"),
+	INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
 };
 
 static int __init pxa168_init(void)
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Mon Mar  5 07:21:47 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Mon,  5 Mar 2012 20:21:47 +0800
Subject: [PATCH v2 3/7] i2c: pxa: add OF support
In-Reply-To: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330950111-30797-4-git-send-email-haojian.zhuang@marvell.com>

Append these properties in below.
mrvl,i2c-polling
mrvl,i2c-fast-mode

Still keep slave, slave_addr and class in platform data.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/i2c/busses/i2c-pxa.c |   95 ++++++++++++++++++++++++++++++++---------
 1 files changed, 74 insertions(+), 21 deletions(-)

diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index d603646..f673326 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -29,6 +29,8 @@
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/i2c-pxa.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/of_i2c.h>
 #include <linux/platform_device.h>
 #include <linux/err.h>
@@ -1044,23 +1046,60 @@ static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
 	.functionality	= i2c_pxa_functionality,
 };
 
-static int i2c_pxa_probe(struct platform_device *dev)
+static struct of_device_id i2c_pxa_dt_ids[] = {
+	{ .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
+	{ .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
+	{ .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA2XX },
+	{}
+};
+MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
+
+static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
+			    enum pxa_i2c_types *i2c_types)
 {
-	struct pxa_i2c *i2c;
-	struct resource *res;
-	struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
-	const struct platform_device_id *id = platform_get_device_id(dev);
-	enum pxa_i2c_types i2c_type = id->driver_data;
+	struct device_node *np = pdev->dev.of_node;
+	const struct of_device_id *of_id =
+			of_match_device(i2c_pxa_dt_ids, &pdev->dev);
 	int ret;
-	int irq;
 
-	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-	irq = platform_get_irq(dev, 0);
-	if (res == NULL || irq < 0)
-		return -ENODEV;
+	if (!of_id)
+		return 1;
+	ret = of_alias_get_id(np, "i2c");
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+		return ret;
+	}
+	pdev->id = ret;
+	if (of_get_property(np, "mrvl,i2c-polling", NULL))
+		i2c->use_pio = 1;
+	if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
+		i2c->fast_mode = 1;
+	*i2c_types = (u32)(of_id->data);
+	return 0;
+}
 
-	if (!request_mem_region(res->start, resource_size(res), res->name))
-		return -ENOMEM;
+static int i2c_pxa_probe_pdata(struct platform_device *pdev,
+			       struct pxa_i2c *i2c,
+			       enum pxa_i2c_types *i2c_types)
+{
+	struct i2c_pxa_platform_data *plat = pdev->dev.platform_data;
+	const struct platform_device_id *id = platform_get_device_id(pdev);
+
+	*i2c_types = id->driver_data;
+	if (plat) {
+		i2c->use_pio = plat->use_pio;
+		i2c->fast_mode = plat->fast_mode;
+	}
+	return 0;
+}
+
+static int i2c_pxa_probe(struct platform_device *dev)
+{
+	struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
+	enum pxa_i2c_types i2c_type;
+	struct pxa_i2c *i2c;
+	struct resource *res = NULL;
+	int ret, irq;
 
 	i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
 	if (!i2c) {
@@ -1068,6 +1107,24 @@ static int i2c_pxa_probe(struct platform_device *dev)
 		goto emalloc;
 	}
 
+	ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
+	if (ret > 0)
+		ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
+	if (ret < 0)
+		goto eclk;
+
+	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(dev, 0);
+	if (res == NULL || irq < 0) {
+		ret = -ENODEV;
+		goto eclk;
+	}
+
+	if (!request_mem_region(res->start, resource_size(res), res->name)) {
+		ret = -ENOMEM;
+		goto eclk;
+	}
+
 	i2c->adap.owner   = THIS_MODULE;
 	i2c->adap.retries = 5;
 
@@ -1109,21 +1166,16 @@ static int i2c_pxa_probe(struct platform_device *dev)
 
 	i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
 
-#ifdef CONFIG_I2C_PXA_SLAVE
 	if (plat) {
+#ifdef CONFIG_I2C_PXA_SLAVE
 		i2c->slave_addr = plat->slave_addr;
 		i2c->slave = plat->slave;
-	}
 #endif
-
-	clk_enable(i2c->clk);
-
-	if (plat) {
 		i2c->adap.class = plat->class;
-		i2c->use_pio = plat->use_pio;
-		i2c->fast_mode = plat->fast_mode;
 	}
 
+	clk_enable(i2c->clk);
+
 	if (i2c->use_pio) {
 		i2c->adap.algo = &i2c_pxa_pio_algorithm;
 	} else {
@@ -1234,6 +1286,7 @@ static struct platform_driver i2c_pxa_driver = {
 		.name	= "pxa2xx-i2c",
 		.owner	= THIS_MODULE,
 		.pm	= I2C_PXA_DEV_PM_OPS,
+		.of_match_table = i2c_pxa_dt_ids,
 	},
 	.id_table	= i2c_pxa_id_table,
 };
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Mon Mar  5 07:21:49 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Mon,  5 Mar 2012 20:21:49 +0800
Subject: [PATCH v2 5/7] ARM: mmp: append OF support on pxa168
In-Reply-To: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330950111-30797-6-git-send-email-haojian.zhuang@marvell.com>

Enable PXA168 and aspenite support.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/mach-mmp/Kconfig  |   10 ++++++
 arch/arm/mach-mmp/Makefile |    1 +
 arch/arm/mach-mmp/mmp-dt.c |   75 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 86 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-mmp/mmp-dt.c

diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 323d4c9..5a90b9a 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -2,6 +2,16 @@ if ARCH_MMP
 
 menu "Marvell PXA168/910/MMP2 Implmentations"
 
+config MACH_MMP_DT
+	bool "Support MMP2 platforms from device tree"
+	select CPU_PXA168
+	select CPU_PXA910
+	select USE_OF
+	help
+	  Include support for Marvell MMP2 based platforms using
+	  the device tree. Needn't select any other machine while
+	  MACH_MMP_DT is enabled.
+
 config MACH_ASPENITE
 	bool "Marvell's PXA168 Aspenite Development Board"
 	select CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index ba254a7..4fc0ff5 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_MACH_TTC_DKB)	+= ttc_dkb.o
 obj-$(CONFIG_MACH_BROWNSTONE)	+= brownstone.o
 obj-$(CONFIG_MACH_FLINT)	+= flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
+obj-$(CONFIG_MACH_MMP_DT)	+= mmp-dt.o
 obj-$(CONFIG_MACH_TETON_BGA)	+= teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)	+= gplugd.o
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
new file mode 100644
index 0000000..6707539
--- /dev/null
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -0,0 +1,75 @@
+/*
+ *  linux/arch/arm/mach-mmp/mmp-dt.c
+ *
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+extern struct sys_timer pxa168_timer;
+extern void __init icu_init_irq(void);
+
+static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+	OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+	{}
+};
+
+static int __init mmp_intc_add_irq_domain(struct device_node *np,
+					   struct device_node *parent)
+{
+	irq_domain_add_simple(np, 0);
+	return 0;
+}
+
+static int __init mmp_gpio_add_irq_domain(struct device_node *np,
+					   struct device_node *parent)
+{
+	irq_domain_add_simple(np, IRQ_GPIO_START);
+	return 0;
+}
+
+static const struct of_device_id mmp_irq_match[] __initconst = {
+	{ .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
+	{ .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
+	{}
+};
+
+static void __init mmp_dt_init(void)
+{
+
+	of_irq_init(mmp_irq_match);
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     mmp_auxdata_lookup, NULL);
+}
+
+static const char *pxa168_dt_board_compat[] __initdata = {
+	"mrvl,pxa168-aspenite",
+	NULL,
+};
+
+DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
+	.map_io		= mmp_map_io,
+	.init_irq	= icu_init_irq,
+	.timer		= &pxa168_timer,
+	.init_machine	= mmp_dt_init,
+	.dt_compat	= pxa168_dt_board_compat,
+MACHINE_END
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Mon Mar  5 07:21:50 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Mon,  5 Mar 2012 20:21:50 +0800
Subject: [PATCH v2 6/7] ARM: dts: append DTS file of pxa168
In-Reply-To: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330950111-30797-7-git-send-email-haojian.zhuang@marvell.com>

DTS files of both PXA168 and aspenite are appended.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/boot/dts/pxa168-aspenite.dts |   38 +++++++++++++
 arch/arm/boot/dts/pxa168.dtsi         |   98 +++++++++++++++++++++++++++++++++
 2 files changed, 136 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/pxa168-aspenite.dts
 create mode 100644 arch/arm/boot/dts/pxa168.dtsi

diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
new file mode 100644
index 0000000..e762fac
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168-aspenite.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "pxa168.dtsi"
+
+/ {
+	model = "Marvell PXA168 Aspenite Development Board";
+	compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+	};
+
+	memory {
+		reg = <0x00000000 0x04000000>;
+	};
+
+	soc {
+		apb at d4000000 {
+			uart1: uart at d4017000 {
+				status = "okay";
+			};
+			twsi1: i2c at d4011000 {
+				status = "okay";
+			};
+			rtc: rtc at d4010000 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
new file mode 100644
index 0000000..d32d512
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -0,0 +1,98 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		i2c0 = &twsi1;
+		i2c1 = &twsi2;
+	};
+
+	intc: intc-interrupt-controller at d4282000 {
+		compatible = "mrvl,mmp-intc", "mrvl,intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0xd4282000 0x1000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&intc>;
+		ranges;
+
+		apb at d4000000 {	/* APB */
+			compatible = "mrvl,apb-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd4000000 0x00200000>;
+			ranges;
+
+			uart1: uart at d4017000 {
+				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				reg = <0xd4017000 0x1000>;
+				interrupts = <27>;
+				status = "disabled";
+			};
+
+			uart2: uart at d4018000 {
+				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				reg = <0xd4018000 0x1000>;
+				interrupts = <28>;
+				status = "disabled";
+			};
+
+			uart3: uart at d4026000 {
+				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				reg = <0xd4026000 0x1000>;
+				interrupts = <29>;
+				status = "disabled";
+			};
+
+			gpio: gpio at d4019000 {
+				compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+				reg = <0xd4019000 0x1000>;
+				interrupts = <49>;
+				interrupt-names = "gpio_mux";
+				gpio-controller;
+				#gpio-cells = <1>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			twsi1: i2c at d4011000 {
+				compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+				reg = <0xd4011000 0x1000>;
+				interrupts = <7>;
+				mrvl,i2c-fast-mode;
+				status = "disabled";
+			};
+
+			twsi2: i2c at d4025000 {
+				compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+				reg = <0xd4025000 0x1000>;
+				interrupts = <58>;
+				status = "disabled";
+			};
+
+			rtc: rtc at d4010000 {
+				compatible = "mrvl,mmp-rtc";
+				reg = <0xd4010000 0x1000>;
+				interrupts = <5 6>;
+				interrupt-names = "rtc 1Hz", "rtc alarm";
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
1.7.0.4



From haojian.zhuang at marvell.com  Mon Mar  5 07:21:51 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Mon,  5 Mar 2012 20:21:51 +0800
Subject: [PATCH v2 7/7] Document: devicetree: add OF documents for arch-mmp
In-Reply-To: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <1330950111-30797-8-git-send-email-haojian.zhuang@marvell.com>

Add OF support in Document/devicetree directory.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 Documentation/devicetree/bindings/arm/mrvl.txt     |    6 +++
 .../devicetree/bindings/gpio/mrvl-gpio.txt         |   23 ++++++++++++
 Documentation/devicetree/bindings/i2c/mrvl-i2c.txt |   37 ++++++++++++++++++++
 .../devicetree/bindings/rtc/sa1100-rtc.txt         |   17 +++++++++
 .../devicetree/bindings/serial/mrvl-serial.txt     |    4 ++
 5 files changed, 87 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
 create mode 100644 Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
 create mode 100644 Documentation/devicetree/bindings/serial/mrvl-serial.txt

diff --git a/Documentation/devicetree/bindings/arm/mrvl.txt b/Documentation/devicetree/bindings/arm/mrvl.txt
new file mode 100644
index 0000000..d8de933
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl.txt
@@ -0,0 +1,6 @@
+Marvell Platforms Device Tree Bindings
+----------------------------------------------------
+
+PXA168 Aspenite Board
+Required root node properties:
+	- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
new file mode 100644
index 0000000..1e34cfe
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
@@ -0,0 +1,23 @@
+* Marvell PXA GPIO controller
+
+Required properties:
+- compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
+- reg : Address and length of the register set for the device
+- interrupts : Should be the port interrupt shared by all gpio pins, if
+- interrupt-name : Should be the name of irq resource.
+  one number.
+- gpio-controller : Marks the device node as a gpio controller.
+- #gpio-cells : Should be one.  It is the pin number.
+
+Example:
+
+	gpio: gpio at d4019000 {
+		compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+		reg = <0xd4019000 0x1000>;
+		interrupts = <49>, <17>, <18>;
+		interrupt-name = "gpio_mux", "gpio0", "gpio1";
+		gpio-controller;
+		#gpio-cells = <1>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+      };
diff --git a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
new file mode 100644
index 0000000..071eb3c
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
@@ -0,0 +1,37 @@
+* I2C
+
+Required properties :
+
+ - reg : Offset and length of the register set for the device
+ - compatible : should be "mrvl,mmp-twsi" where CHIP is the name of a
+   compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
+   For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
+   as shown in the example below.
+
+Recommended properties :
+
+ - interrupts : <a b> where a is the interrupt number and b is a
+   field that represents an encoding of the sense and level
+   information for the interrupt.  This should be encoded based on
+   the information in section 2) depending on the type of interrupt
+   controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+   services interrupts for this device.
+ - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
+   status register of i2c controller instead.
+ - mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
+
+Examples:
+	twsi1: i2c at d4011000 {
+		compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+		reg = <0xd4011000 0x1000>;
+		interrupts = <7>;
+		mrvl,i2c-fast-mode;
+	};
+	
+	twsi2: i2c at d4025000 {
+		compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+		reg = <0xd4025000 0x1000>;
+		interrupts = <58>;
+	};
+
diff --git a/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt b/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
new file mode 100644
index 0000000..0cda19a
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
@@ -0,0 +1,17 @@
+* Marvell Real Time Clock controller
+
+Required properties:
+- compatible: should be "mrvl,sa1100-rtc"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: Should be two. The first interrupt number is the rtc alarm
+  interrupt and the second interrupt number is the rtc hz interrupt.
+- interrupt-names: Assign name of irq resource.
+
+Example:
+	rtc: rtc at d4010000 {
+		compatible = "mrvl,mmp-rtc";
+		reg = <0xd4010000 0x1000>;
+		interrupts = <5>, <6>;
+		interrupt-name = "rtc 1Hz", "rtc alarm";
+	};
diff --git a/Documentation/devicetree/bindings/serial/mrvl-serial.txt b/Documentation/devicetree/bindings/serial/mrvl-serial.txt
new file mode 100644
index 0000000..d744340
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/mrvl-serial.txt
@@ -0,0 +1,4 @@
+PXA UART controller
+
+Required properties:
+- compatible : should be "mrvl,mmp-uart" or "mrvl,pxa-uart".
-- 
1.7.0.4



From haojian.zhuang at gmail.com  Mon Mar  5 07:22:41 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Mon, 5 Mar 2012 20:22:41 +0800
Subject: Status of gpio-pxa driver and dummy clock
In-Reply-To: <1330885571.28077.YahooMailClassic@web29015.mail.ird.yahoo.com>
References: <87aa3wu0hp.fsf@free.fr>
 <1330885571.28077.YahooMailClassic@web29015.mail.ird.yahoo.com>
Message-ID: <CAN1soZxkVSFbNG4QaCxxxbNMB255JeNCK+=YqBzvmAAXdCRYyQ@mail.gmail.com>

On Mon, Mar 5, 2012 at 2:26 AM, Paul Parsons <lost.distance at yahoo.com> wrote:
> --- On Sun, 4/3/12, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
>> From: Robert Jarzmik <robert.jarzmik at free.fr>
>> Subject: Re: Status of gpio-pxa driver and dummy clock
>> To: "Haojian Zhuang" <haojian.zhuang at gmail.com>
>> Cc: "Arnd Bergmann" <arnd at arndb.de>, linux-arm-kernel at lists.infradead.org
>> Date: Sunday, 4 March, 2012, 10:25
>> Haojian Zhuang <haojian.zhuang at gmail.com>
>> writes:
>>
>> > On Sun, Mar 4, 2012 at 5:34 AM, Robert Jarzmik <robert.jarzmik at free.fr>
>> wrote:
>> >> Hi Haojian,
>> >>
>> >> As you certainly know, Russell reverted the patch
>> "ARM: pxa: add dummy clock for
>> >> sa1100-rtc", id
>> a55b5adaf403c4d032e0871ad4ee3367782f4db6. As a consequence,
>> the
>> >> dummy clock for gpio-pxa was removed, causing
>> breakage of gpio-pxa driver.
>> >>
>> >> I wonder if you (or somebody through you) sent an
>> update to fix the gpio-pxa by
>> >> either fixing gpio-pxa or adding back "pxa-gpio"
>> clock. As of today, I see no
>> >> fix in 3.3-rc free (Linus tree).
>> >>
>> >
>> > This patch is already merged into arm-soc tree for
>> v3.4. I don't have
>> > a plan to push it into
>> > v3.3.
>>
>> Oh, you should push it to 3.3. It's a fix, and the mioa701
>> board is broken (and
>> probably many others PXA based boards too) because no GPIO
>> is available (as
>> probe function of pxa-gpio always fail on clk_get()).
>>
>> If you don't want to push it to 3.3, I'll have to send a fix
>> to Arnd to fix the
>> breakage.
>>
>> Without it, a PXA based kernel (pxa2xx) will hang in its
>> boot phase, on the
>> first gpio_get_* or gpio_set_*, which is called by many
>> drivers.
>
> There are two further pxa gpio regressions still present in
> linux-3.3-rc5:
>
> mfp/gpio regression: pxa_last_gpio used before initialized
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/082624.html
>
> reboot/suspend regression: hx4700 freezes under linux-3.3-rc1
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/082873.html
> (2 regressions are reported here; the reboot regression is still present in
> linux-3.3-rc5 while the suspend regression has now been fixed).

I missed them. Maybe I was not in the Cc list. I'll append the patches
to fix them.

Best Regards
Haojian


From B04825 at freescale.com  Mon Mar  5 07:28:52 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Mon, 5 Mar 2012 12:28:52 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <20120305073930.GC16232@S2101-09.ap.freescale.net>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120305073930.GC16232@S2101-09.ap.freescale.net>
Message-ID: <4F54B183.4080607@freescale.com>

Shawn Guo wrote:
> Yeah, it makes the diff neat.  However I would make it an inline
> function which is easier to play.

However you want to do it is fine with me, although I would use "u32 
__iomem *addr" instead of "void __iomem *addr".

-- 
Timur Tabi
Linux kernel developer at Freescale


From shawn.guo at linaro.org  Mon Mar  5 08:07:09 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 5 Mar 2012 21:07:09 +0800
Subject: [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120305115612.GB3224@opensource.wolfsonmicro.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
 <20120304133818.GE3083@opensource.wolfsonmicro.com>
 <20120305080623.GD16232@S2101-09.ap.freescale.net>
 <20120305115612.GB3224@opensource.wolfsonmicro.com>
Message-ID: <20120305130707.GF16232@S2101-09.ap.freescale.net>

On Mon, Mar 05, 2012 at 11:56:12AM +0000, Mark Brown wrote:
> On Mon, Mar 05, 2012 at 04:06:25PM +0800, Shawn Guo wrote:
> > On Sun, Mar 04, 2012 at 01:38:18PM +0000, Mark Brown wrote:
> 
> > > This looks like there's a problem with the bindings, why are you
> > > registering the DMA device from the card?
> 
> > There is a dma node in the device tree to instantiate the dma device
> > backed by a dmaengine driver.  As a client peripheral of that dmaengine
> > device, the SSI owns just a dma request/event number.  With the number
> > encoded in SSI node, there is no hardware resource to be claimed by
> > that pcm-device, so we do not have it in device tree.  Then we have
> > to register this device in either fsl_ssi driver or machine driver.
> > I chose to do something that tegra is doing, registering the pcm device
> > in machine driver, to keep fsl_ssi away from imx specific bits as much
> > as possible.
> 
> The above sounds like you have a unified DAI and PCM driver.

The pcm-dma driver is being shared across several i.MX SoCs, and we
are trying to reuse fsl_ssi driver between PowerPC and IMX.

> In that
> case they should either both be using the same device or should have
> some sort of parent/child/sibling relationship.

Sorry, I do not understand it.  Can you elaborate it a little bit?

> Either way the machine
> driver really shouldn't be involved in instantiating things, perhaps
> arch/arm but not the audio machine driver.

So you are saying neither what tegra_wm8903 and tegra_alc5632 are doing
(registering pcm device in machine driver) nor what imx-ssi is doing
(registering pcm device in DAI driver) is correct?  Can you please make
it clear what's the right thing to do?

-- 
Regards,
Shawn


From arnd at arndb.de  Mon Mar  5 07:55:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 5 Mar 2012 12:55:37 +0000
Subject: [PATCH v2 1/7] serial: pxa: add OF support
In-Reply-To: <1330950111-30797-2-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
 <1330950111-30797-2-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203051255.37311.arnd@arndb.de>

On Monday 05 March 2012, Haojian Zhuang wrote:

>  
> +#define PXA_NAME_LEN		8
> +
>  struct uart_pxa_port {
>  	struct uart_port        port;
>  	unsigned char           ier;

Why didn't you just add a field here with that length?

> @@ -781,6 +784,39 @@ static const struct dev_pm_ops serial_pxa_pm_ops = {
>  };
>  #endif
>  
> +static struct of_device_id serial_pxa_dt_ids[] = {
> +	{ .compatible = "mrvl,pxa-uart", },
> +	{ .compatible = "mrvl,mmp-uart", },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids);

This one should have an #ifdef CONFIG_OF

> +#ifdef CONFIG_OF
> +static int serial_pxa_probe_dt(struct platform_device *pdev,
> +			       struct uart_pxa_port *sport)
> +{

While this one does not need it: it will already compile to nothing
if you check the error value correctly.

> +	sport->name = kzalloc(PXA_NAME_LEN, GFP_KERNEL);
> +	if (!sport->name) {
> +		ret = -ENOMEM;
> +		goto err_clk;
>  	}

No need for this allocation if you put the name into uart_pxa_port
as a member instead of a pointer.

> +		.of_match_table = serial_pxa_dt_ids,
>  	},
>  };

		.of_match_table = of_match_ptr(serial_pxa_dt_ids),

	Arnd



From broonie at opensource.wolfsonmicro.com  Mon Mar  5 08:13:32 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 13:13:32 +0000
Subject: [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120305130707.GF16232@S2101-09.ap.freescale.net>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
 <20120304133818.GE3083@opensource.wolfsonmicro.com>
 <20120305080623.GD16232@S2101-09.ap.freescale.net>
 <20120305115612.GB3224@opensource.wolfsonmicro.com>
 <20120305130707.GF16232@S2101-09.ap.freescale.net>
Message-ID: <20120305131332.GM3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 09:07:09PM +0800, Shawn Guo wrote:
> On Mon, Mar 05, 2012 at 11:56:12AM +0000, Mark Brown wrote:

> > In that
> > case they should either both be using the same device or should have
> > some sort of parent/child/sibling relationship.

> Sorry, I do not understand it.  Can you elaborate it a little bit?

The DMA and SSI drivers should have some relationship with each other if
they're the same piece of hardware.  The machine driver certainly
shouldn't be creating either of them.

> > Either way the machine
> > driver really shouldn't be involved in instantiating things, perhaps
> > arch/arm but not the audio machine driver.

> So you are saying neither what tegra_wm8903 and tegra_alc5632 are doing
> (registering pcm device in machine driver) nor what imx-ssi is doing
> (registering pcm device in DAI driver) is correct?  Can you please make
> it clear what's the right thing to do?

The above.
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From b-cousson at ti.com  Mon Mar  5 08:14:22 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 5 Mar 2012 14:14:22 +0100
Subject: [RFC PATCH] of: DMA helpers: manage generic requests specification
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BDDF217B@HQMAIL01.nvidia.com>
References: <4F22DEF2.5000807@ti.com>
 <1330527248-4350-1-git-send-email-nicolas.ferre@atmel.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF217B@HQMAIL01.nvidia.com>
Message-ID: <4F54BC2E.3040702@ti.com>

On 2/29/2012 9:54 PM, Stephen Warren wrote:
> Nicolas Ferre wrote at Wednesday, February 29, 2012 7:54 AM:
>> By making DMA controllers register a generic translation
>> function, we allow the management of any type of DMA requests
>> specification.
>> The void * output of an of_dma_xlate() function that will be implemented
>> by the DMA controller can carry any type of "dma-request" argument.
>>
>> The DMA client will search its associated DMA controller in the list
>> and call the registered of_dam_xlate() function to retrieve the
>> request values.
>>
>> One simple xlate function is provided for the "single number" type
>> of request biding.
>>
>> This implementation is independent from dmaengine so it can also be
>> used by legacy drivers.
>
> At a high level this seems along the right lines.
>
> The big issue I see is the lack of type-safety in of_get_dma_request()'s
> out_data pointer: The DMA xlate function will assume it points at some
> particular type, and the client is responsible for allocating that
> correct type. However, it's "user"-supplied device tree data that hooks
> the two together, and there could easily be mismatches, thus causing
> the xlate function to trash memory.
>
> Could each DMA controller (or type of out_data) have some enum in the
> kernel that the client passes in, and the DMA engine validates matches
> its expectations, to prevent this kind of thing?

Beside u32 and string, do we know what kind of parameters we can expect 
to retrieve?
Because we can potentially reduce the scope to these two types only.

> enum DMA_PARAMS_TYPE {
>      FOO_DMA_PARAMS,
>      BAR_DMA_PARAMS,
>      ...
> };
>
> struct foo_dma_params { ... };
>
> struct foo_dma_params params;
>
> of_get_dma_request(np, 0,&params, FOO_DMA_PARAMS);
>
> and inside xlate():
>
> if (params_type != FOO_DMA_PARAMS)
>      return -EINVAL;
>
> For the dmaengine case, I assume there'd be a single DMA_PARAMS_TYPE
> value for the dmaengine specifier type, and the dmaengine core would
> take care of making sure everything matched somehow.

Regards,
Benoit


From shawn.guo at linaro.org  Mon Mar  5 08:40:51 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 5 Mar 2012 21:40:51 +0800
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <4F54B183.4080607@freescale.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120305073930.GC16232@S2101-09.ap.freescale.net>
 <4F54B183.4080607@freescale.com>
Message-ID: <20120305134048.GG16232@S2101-09.ap.freescale.net>

On Mon, Mar 05, 2012 at 12:28:52PM +0000, Tabi Timur-B04825 wrote:
> Shawn Guo wrote:
> > Yeah, it makes the diff neat.  However I would make it an inline
> > function which is easier to play.
> 
> However you want to do it is fine with me, although I would use "u32 
> __iomem *addr" instead of "void __iomem *addr".
> 
Right, will make the change. 

-- 
Regards,
Shawn


From jason at lakedaemon.net  Mon Mar  5 08:32:42 2012
From: jason at lakedaemon.net (Jason)
Date: Mon, 5 Mar 2012 08:32:42 -0500
Subject: [GIT PULL v3] ARM: kirkwood: fdt: convert kirkwood init funcs
 to fdt
In-Reply-To: <20120305034113.GB5050@titan.lakedaemon.net>
References: <20120305034113.GB5050@titan.lakedaemon.net>
Message-ID: <20120305133242.GD5050@titan.lakedaemon.net>

On Sun, Mar 04, 2012 at 10:41:13PM -0500, Jason Cooper wrote:
> 	rtc-mv: more accurate compatible strings
> 	orion-wdt: more accurate compatible strings
...
>  arch/arm/boot/dts/kirkwood-dreamplug.dts |   34 +++++++++++++++
>  arch/arm/boot/dts/kirkwood.dtsi          |   12 +++++

This is still bugging me.  If, say, orion_wdt.c is common to all of
plat-orion/ shouldn't it be in an 'orion.dtsi'?  With compatible =
"marvell,orion-wdt"?  Then, if hypothetically, kirkwood used the same
driver but had a small tweak, then kirkwood.dtsi would have
"marvell,kirkwood-wdt"?  Which would let the driver know that it needed
to apply the tweak because it was kirkwood.

In this scenario, since kirkwood and dreamplug currently need no
modifications to the default wdt driver, they would just inherit
orion.dtsi's "marvell,orion-wdt", right?

On the driver side, since it currently has no subarch or board specific
tweaks, then it is *only* good for the generic case,
"marvell,orion-wdt", and thus should only match it for now.

If the above is correct, then I should create orion.dtsi, which is
included by kirkwood.dtsi.  orion.dtsi should hold "marvell,orion-wdt"
and "marvell,orion-rtc".  The corresponding drivers should only match
those generic strings, since there are no specific tweaks.

I hate to keep kicking this horse, but I want to make sure I grok it.

thx,

Jason.


From jhovold at gmail.com  Mon Mar  5 08:58:38 2012
From: jhovold at gmail.com (Johan Hovold)
Date: Mon, 5 Mar 2012 14:58:38 +0100
Subject: [GIT PULL] ARM: OMAP: IRQ domain support for INTC
In-Reply-To: <4F4E4F1D.7020109@ti.com>
References: <4F4BB0FB.3040308@ti.com> <20120228234837.GH18901@atomide.com>
 <4F4E4F1D.7020109@ti.com>
Message-ID: <20120305135838.GA2108@localhost>

On Wed, Feb 29, 2012 at 05:15:25PM +0100, Cousson, Benoit wrote:
> On 2/29/2012 12:48 AM, Tony Lindgren wrote:
> > * Cousson, Benoit<b-cousson at ti.com>  [120227 08:04]:
> >> Hi Tony
> >>
> >> This series is based on the lo/dt + the irqdomain/next branch merged on top of it.
> >>
> >> Grant confirmed that the irqdomain/next is a stable branch and thus can be referenced for dependency.
> >>
> >> Please note that I will need that branch to base all the remaining OMAP DT stuff.
> >>
> >> Thanks,
> >> Benoit
> >>
> >>
> >> The following changes since commit 1f52299ec000e2161635b263d81ab92ea7f1f0a7:
> >>    Benoit Cousson (1):
> >>          Merge branch 'irqdomain/next' of git://git.secretlab.ca/git/linux-2.6 into for_3.4/dt_irq_domain2
> >>
> >> are available in the git repository at:
> >>
> >>    git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/dt_irq_domain
> >>
> >> Benoit Cousson (3):
> >>        ARM: OMAP2/3: intc: Add DT support for TI interrupt controller
> >>        arm/dts: OMAP3: Add interrupt-controller bindings for INTC
> >>        ARM: OMAP2+: board-generic: Use of_irq_init API
> >>
> >>   .../devicetree/bindings/arm/omap/intc.txt          |   27 +++++++++
> >>   arch/arm/boot/dts/omap3.dtsi                       |    6 +-
> >>   arch/arm/mach-omap2/board-generic.c                |   30 +++++-----
> >>   arch/arm/mach-omap2/common.h                       |   12 ++++
> >>   arch/arm/mach-omap2/irq.c                          |   60 ++++++++++++++++---
> >>   5 files changed, 109 insertions(+), 26 deletions(-)
> >>   create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt
> > 
> > Hmm, looks like this now produces the following warning at least on omap3:
> 
> Yes, Rajendra has just reported that issue with linux-next.

I'm getting the same warning and initialisation failure with 3.3-rc6 on
overo. Are these fixes queued up for 3.3 (and not just 3.4) somewhere?

Thanks,
Johan


From haojian.zhuang at gmail.com  Mon Mar  5 09:03:49 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Mon, 5 Mar 2012 22:03:49 +0800
Subject: [PATCH v2 1/7] serial: pxa: add OF support
In-Reply-To: <201203051255.37311.arnd@arndb.de>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
 <1330950111-30797-2-git-send-email-haojian.zhuang@marvell.com>
 <201203051255.37311.arnd@arndb.de>
Message-ID: <CAN1soZwHr50+F7-hO=U24U=zrv9C7gxnhzSYgrziaeMYuqRVXA@mail.gmail.com>

On Mon, Mar 5, 2012 at 8:55 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Monday 05 March 2012, Haojian Zhuang wrote:
>
>>
>> +#define PXA_NAME_LEN ? ? ? ? 8
>> +
>> ?struct uart_pxa_port {
>> ? ? ? struct uart_port ? ? ? ?port;
>> ? ? ? unsigned char ? ? ? ? ? ier;
>
> Why didn't you just add a field here with that length?
>
>> @@ -781,6 +784,39 @@ static const struct dev_pm_ops serial_pxa_pm_ops = {
>> ?};
>> ?#endif
>>
>> +static struct of_device_id serial_pxa_dt_ids[] = {
>> + ? ? { .compatible = "mrvl,pxa-uart", },
>> + ? ? { .compatible = "mrvl,mmp-uart", },
>> + ? ? {}
>> +};
>> +MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids);
>
> This one should have an #ifdef CONFIG_OF
>
>> +#ifdef CONFIG_OF
>> +static int serial_pxa_probe_dt(struct platform_device *pdev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct uart_pxa_port *sport)
>> +{
>
> While this one does not need it: it will already compile to nothing
> if you check the error value correctly.
>
>> + ? ? sport->name = kzalloc(PXA_NAME_LEN, GFP_KERNEL);
>> + ? ? if (!sport->name) {
>> + ? ? ? ? ? ? ret = -ENOMEM;
>> + ? ? ? ? ? ? goto err_clk;
>> ? ? ? }
>
> No need for this allocation if you put the name into uart_pxa_port
> as a member instead of a pointer.
>
>> + ? ? ? ? ? ? .of_match_table = serial_pxa_dt_ids,
>> ? ? ? },
>> ?};
>
> ? ? ? ? ? ? ? ?.of_match_table = of_match_ptr(serial_pxa_dt_ids),
>
> ? ? ? ?Arnd
>
Thanks. I'll update it.

Best Regards
Haojian


From koen at dominion.thruhere.net  Mon Mar  5 09:06:19 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Mon, 5 Mar 2012 15:06:19 +0100
Subject: [PATCH] omap3_beagle: Init only uart3 used for console
In-Reply-To: <1330945952-14714-1-git-send-email-govindraj.raja@ti.com>
References: <1330945952-14714-1-git-send-email-govindraj.raja@ti.com>
Message-ID: <12976EFB-912D-44E2-825C-63034F117635@dominion.thruhere.net>


Op 5 mrt. 2012, om 12:12 heeft Govindraj.R het volgende geschreven:

> From: "Govindraj.R" <govindraj.raja at ti.com>
> 
> On beagle some of uart mux lines are used for other
> purpose so init only uart3.
> 
> Uart2 rx line clashes with gpio_147 used for usb ehci
> phy reset. Initializing uart2 pad_mux lines can break
> ehci module on beagle xm.
> (gpio_147 is available on uart2_rx in mode4 reference 
> mux34xx.c -> uart2_rx.gpio_147)

That's only on xM revision C, right?

regards,

Koen


From shawn.guo at linaro.org  Mon Mar  5 09:30:48 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:48 +0800
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working with
 fsl_ssi
Message-ID: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>

Changes since v1:
 * Address comments from Mark, Timur, and Sascha (Thanks for review).
 * Drop patches that have been applied by Mark.

Richard Zhao (2):
      ARM: imx: convert audmux to a platform driver
      ASoC: fsl: add dt support for imx-audmux

Shawn Guo (15):
      ASoC: imx: move eukrea audmux call into ASoC machine driver
      ASoC: imx: move phycore audmux call into ASoC machine driver
      ARM: imx: merge audmux-v1 and audmux-v2
      ASoC: imx: move audmux driver into sound/soc/imx
      ASoC: imx: rename audmux prefix mxc to imx
      ASoC: imx: separate imx-pcm bits from imx-ssi driver
      ASoC: imx: add an explicit Kconfig option for imx-ssi driver
      ASoC: fsl: separate SSI and DMA Kconfig options
      ASoC: imx: merge sound/soc/imx into sound/soc/fsl
      ASoC: fsl: create fsl_utils to accommodate the common functions
      ASoC: fsl: check property 'compatible' for the machine name
      ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
      ASoC: fsl: remove the fatal error checking on codec-handle
      ASoC: fsl: let fsl_ssi work with imx pcm and machine drivers
      ASoC: fsl: add imx-sgtl5000 machine driver

 .../bindings/sound/imx-audio-sgtl5000.txt          |   24 +++
 .../devicetree/bindings/sound/imx-audmux.txt       |   13 ++
 arch/arm/mach-imx/Kconfig                          |    6 -
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c       |   20 --
 arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c       |    1 -
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c     |   17 --
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c     |   17 --
 arch/arm/mach-imx/mach-pca100.c                    |   13 --
 arch/arm/mach-imx/mach-pcm043.c                    |   13 --
 arch/arm/mach-imx/mm-imx21.c                       |    6 +
 arch/arm/mach-imx/mm-imx25.c                       |    7 +
 arch/arm/mach-imx/mm-imx27.c                       |    7 +
 arch/arm/mach-imx/mm-imx3.c                        |   13 ++
 arch/arm/mach-imx/mm-imx5.c                        |   22 +++
 arch/arm/plat-mxc/Kconfig                          |    6 -
 arch/arm/plat-mxc/Makefile                         |    2 -
 arch/arm/plat-mxc/audmux-v1.c                      |   64 -------
 arch/arm/plat-mxc/include/mach/audmux.h            |   60 -------
 sound/soc/Kconfig                                  |    1 -
 sound/soc/Makefile                                 |    1 -
 sound/soc/fsl/Kconfig                              |  124 +++++++++++++-
 sound/soc/fsl/Makefile                             |   29 +++-
 sound/soc/{imx => fsl}/eukrea-tlv320.c             |   42 ++++-
 sound/soc/fsl/fsl_ssi.c                            |  139 ++++++++++++----
 sound/soc/fsl/fsl_utils.c                          |  135 ++++++++++++++
 sound/soc/fsl/fsl_utils.h                          |   27 +++
 .../audmux-v2.c => sound/soc/fsl/imx-audmux.c      |  185 +++++++++++++++-----
 sound/soc/fsl/imx-audmux.h                         |   60 +++++++
 sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c           |    2 +-
 sound/soc/{imx => fsl}/imx-pcm-fiq.c               |    0
 sound/soc/fsl/imx-pcm.c                            |  105 +++++++++++
 sound/soc/fsl/imx-pcm.h                            |   32 ++++
 sound/soc/fsl/imx-sgtl5000.c                       |  181 +++++++++++++++++++
 sound/soc/{imx => fsl}/imx-ssi.c                   |   90 +----------
 sound/soc/{imx => fsl}/imx-ssi.h                   |   16 +--
 sound/soc/fsl/mpc8610_hpcd.c                       |  159 ++----------------
 sound/soc/{imx => fsl}/mx27vis-aic32x4.c           |   20 +-
 sound/soc/fsl/p1022_ds.c                           |  181 ++------------------
 sound/soc/{imx => fsl}/phycore-ac97.c              |   27 +++-
 sound/soc/{imx => fsl}/wm1133-ev1.c                |   25 ++--
 sound/soc/imx/Kconfig                              |   60 -------
 sound/soc/imx/Makefile                             |   19 --
 42 files changed, 1140 insertions(+), 831 deletions(-)


From shawn.guo at linaro.org  Mon Mar  5 09:30:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:49 +0800
Subject: [PATCH v2 01/17] ASoC: imx: move eukrea audmux call into ASoC machine
 driver
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-2-git-send-email-shawn.guo@linaro.org>

It moves eukrea audmux configuration call from board file into ASoC
machine driver eukrea-tlv320, so that it gets aligned wm1133-ev1 and
mx27vis-aic32x4, and more importantly it will ease the moving of audmux
into sound/soc/imx as a platform driver later.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c   |   20 ------------
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c |   17 ----------
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c |   17 ----------
 sound/soc/imx/eukrea-tlv320.c                  |   40 +++++++++++++++++++++--
 4 files changed, 36 insertions(+), 58 deletions(-)

diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 5db3e14..5f2f91d 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -32,7 +32,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx27.h>
 #include <mach/hardware.h>
-#include <mach/audmux.h>
 
 #include "devices-imx27.h"
 
@@ -306,25 +305,6 @@ void __init eukrea_mbimx27_baseboard_init(void)
 	mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
 		ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
 
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
-	|| defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
-	/* SSI unit master I2S codec connected to SSI_PINS_4*/
-	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_TFSDIR |
-			MXC_AUDMUX_V1_PCR_TCLKDIR |
-			MXC_AUDMUX_V1_PCR_RFSDIR |
-			MXC_AUDMUX_V1_PCR_RCLKDIR |
-			MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
-			MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
-	);
-	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
-	);
-#endif
-
 	imx27_add_imx_uart1(&uart_pdata);
 	imx27_add_imx_uart2(&uart_pdata);
 #if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 66e8726..2cf603e 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -31,7 +31,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/mx25.h>
-#include <mach/audmux.h>
 
 #include "devices-imx25.h"
 
@@ -241,22 +240,6 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
 			ARRAY_SIZE(eukrea_mbimxsd_pads)))
 		printk(KERN_ERR "error setting mbimxsd pads !\n");
 
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
-	/* SSI unit master I2S codec connected to SSI_AUD5*/
-	mxc_audmux_v2_configure_port(0,
-			MXC_AUDMUX_V2_PTCR_SYN |
-			MXC_AUDMUX_V2_PTCR_TFSDIR |
-			MXC_AUDMUX_V2_PTCR_TFSEL(4) |
-			MXC_AUDMUX_V2_PTCR_TCLKDIR |
-			MXC_AUDMUX_V2_PTCR_TCSEL(4),
-			MXC_AUDMUX_V2_PDCR_RXDSEL(4)
-	);
-	mxc_audmux_v2_configure_port(4,
-			MXC_AUDMUX_V2_PTCR_SYN,
-			MXC_AUDMUX_V2_PDCR_RXDSEL(0)
-	);
-#endif
-
 	imx25_add_imx_uart1(&uart_pdata);
 	imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
 	imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 0f0af02..fd8bf8a 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -38,7 +38,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
-#include <mach/audmux.h>
 
 #include "devices-imx35.h"
 
@@ -252,22 +251,6 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
 			ARRAY_SIZE(eukrea_mbimxsd_pads)))
 		printk(KERN_ERR "error setting mbimxsd pads !\n");
 
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
-	/* SSI unit master I2S codec connected to SSI_AUD4 */
-	mxc_audmux_v2_configure_port(0,
-			MXC_AUDMUX_V2_PTCR_SYN |
-			MXC_AUDMUX_V2_PTCR_TFSDIR |
-			MXC_AUDMUX_V2_PTCR_TFSEL(3) |
-			MXC_AUDMUX_V2_PTCR_TCLKDIR |
-			MXC_AUDMUX_V2_PTCR_TCSEL(3),
-			MXC_AUDMUX_V2_PDCR_RXDSEL(3)
-	);
-	mxc_audmux_v2_configure_port(3,
-			MXC_AUDMUX_V2_PTCR_SYN,
-			MXC_AUDMUX_V2_PDCR_RXDSEL(0)
-	);
-#endif
-
 	imx35_add_imx_uart1(&uart_pdata);
 	imx35_add_ipu_core(&mx3_ipu_data);
 	imx35_add_mx3_sdc_fb(&mx3fb_pdata);
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/imx/eukrea-tlv320.c
index 1c1fdd1..bfcb6d9 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/imx/eukrea-tlv320.c
@@ -23,6 +23,7 @@
 #include <sound/pcm.h>
 #include <sound/soc.h>
 #include <asm/mach-types.h>
+#include <mach/audmux.h>
 
 #include "../codecs/tlv320aic23.h"
 #include "imx-ssi.h"
@@ -97,12 +98,43 @@ static struct platform_device *eukrea_tlv320_snd_device;
 static int __init eukrea_tlv320_init(void)
 {
 	int ret;
-
-	if (!machine_is_eukrea_cpuimx27() && !machine_is_eukrea_cpuimx25sd()
-		&& !machine_is_eukrea_cpuimx35sd()
-		&& !machine_is_eukrea_cpuimx51sd())
+	int int_port = 0, ext_port;
+
+	if (machine_is_eukrea_cpuimx27()) {
+		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+			MXC_AUDMUX_V1_PCR_SYN |
+			MXC_AUDMUX_V1_PCR_TFSDIR |
+			MXC_AUDMUX_V1_PCR_TCLKDIR |
+			MXC_AUDMUX_V1_PCR_RFSDIR |
+			MXC_AUDMUX_V1_PCR_RCLKDIR |
+			MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+			MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
+		);
+		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
+			MXC_AUDMUX_V1_PCR_SYN |
+			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+		);
+	} else if (machine_is_eukrea_cpuimx25sd() ||
+		   machine_is_eukrea_cpuimx35sd() ||
+		   machine_is_eukrea_cpuimx51sd()) {
+		ext_port = machine_is_eukrea_cpuimx25sd() ? 4 : 3;
+		mxc_audmux_v2_configure_port(int_port,
+			MXC_AUDMUX_V2_PTCR_SYN |
+			MXC_AUDMUX_V2_PTCR_TFSDIR |
+			MXC_AUDMUX_V2_PTCR_TFSEL(ext_port) |
+			MXC_AUDMUX_V2_PTCR_TCLKDIR |
+			MXC_AUDMUX_V2_PTCR_TCSEL(ext_port),
+			MXC_AUDMUX_V2_PDCR_RXDSEL(ext_port)
+		);
+		mxc_audmux_v2_configure_port(ext_port,
+			MXC_AUDMUX_V2_PTCR_SYN,
+			MXC_AUDMUX_V2_PDCR_RXDSEL(int_port)
+		);
+	} else {
 		/* return happy. We might run on a totally different machine */
 		return 0;
+	}
 
 	eukrea_tlv320_snd_device = platform_device_alloc("soc-audio", -1);
 	if (!eukrea_tlv320_snd_device)
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:30:50 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:50 +0800
Subject: [PATCH v2 02/17] ASoC: imx: move phycore audmux call into ASoC
 machine driver
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-3-git-send-email-shawn.guo@linaro.org>

It moves phycore audmux configuration call from board file into ASoC
machine driver phycore-ac97 to ease converting audmux into a platform
driver later.
It moves phycore audmux configuration call from board file into ASoC
machine driver phycore-ac97, so that it gets aligned with wm1133-ev1
and mx27vis-aic32x4, and more importantly it will ease the moving of
audmux into sound/soc/imx as a platform driver later.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/mach-pca100.c |   13 -------------
 arch/arm/mach-imx/mach-pcm043.c |   13 -------------
 sound/soc/imx/phycore-ac97.c    |   26 +++++++++++++++++++++++++-
 3 files changed, 25 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index d3b9c6b..541152e 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,7 +36,6 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
 #include <asm/mach/time.h>
-#include <mach/audmux.h>
 #include <mach/irqs.h>
 #include <mach/ulpi.h>
 
@@ -359,18 +358,6 @@ static void __init pca100_init(void)
 
 	imx27_soc_init();
 
-	/* SSI unit */
-	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-				  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-				  MXC_AUDMUX_V1_PCR_TFCSEL(3) |
-				  MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
-				  MXC_AUDMUX_V1_PCR_RXDSEL(3));
-	mxc_audmux_v1_configure_port(3,
-				  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-				  MXC_AUDMUX_V1_PCR_TFCSEL(0) |
-				  MXC_AUDMUX_V1_PCR_TFSDIR |
-				  MXC_AUDMUX_V1_PCR_RXDSEL(0));
-
 	ret = mxc_gpio_setup_multiple_pins(pca100_pins,
 			ARRAY_SIZE(pca100_pins), "PCA100");
 	if (ret)
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 06dc106..237474f 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -37,7 +37,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
 #include <mach/ulpi.h>
-#include <mach/audmux.h>
 
 #include "devices-imx35.h"
 
@@ -362,18 +361,6 @@ static void __init pcm043_init(void)
 
 	mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
 
-	mxc_audmux_v2_configure_port(3,
-			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V2_PTCR_TFSEL(0) |
-			MXC_AUDMUX_V2_PTCR_TFSDIR,
-			MXC_AUDMUX_V2_PDCR_RXDSEL(0));
-
-	mxc_audmux_v2_configure_port(0,
-			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V2_PTCR_TCSEL(3) |
-			MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
-			MXC_AUDMUX_V2_PDCR_RXDSEL(3));
-
 	imx35_add_fec(NULL);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 	imx35_add_imx2_wdt(NULL);
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/imx/phycore-ac97.c
index 6ac1211..a59692e 100644
--- a/sound/soc/imx/phycore-ac97.c
+++ b/sound/soc/imx/phycore-ac97.c
@@ -18,6 +18,7 @@
 #include <sound/pcm.h>
 #include <sound/soc.h>
 #include <asm/mach-types.h>
+#include <mach/audmux.h>
 
 static struct snd_soc_card imx_phycore;
 
@@ -50,9 +51,32 @@ static int __init imx_phycore_init(void)
 {
 	int ret;
 
-	if (!machine_is_pcm043() && !machine_is_pca100())
+	if (machine_is_pca100()) {
+		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+			MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+			MXC_AUDMUX_V1_PCR_TFCSEL(3) |
+			MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
+			MXC_AUDMUX_V1_PCR_RXDSEL(3));
+		mxc_audmux_v1_configure_port(3,
+			MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+			MXC_AUDMUX_V1_PCR_TFCSEL(0) |
+			MXC_AUDMUX_V1_PCR_TFSDIR |
+			MXC_AUDMUX_V1_PCR_RXDSEL(0));
+	} else if (machine_is_pcm043()) {
+		mxc_audmux_v2_configure_port(3,
+			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+			MXC_AUDMUX_V2_PTCR_TFSEL(0) |
+			MXC_AUDMUX_V2_PTCR_TFSDIR,
+			MXC_AUDMUX_V2_PDCR_RXDSEL(0));
+		mxc_audmux_v2_configure_port(0,
+			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+			MXC_AUDMUX_V2_PTCR_TCSEL(3) |
+			MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
+			MXC_AUDMUX_V2_PDCR_RXDSEL(3));
+	} else {
 		/* return happy. We might run on a totally different machine */
 		return 0;
+	}
 
 	imx_phycore_snd_ac97_device = platform_device_alloc("soc-audio", -1);
 	if (!imx_phycore_snd_ac97_device)
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:30:51 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:51 +0800
Subject: [PATCH v2 03/17] ARM: imx: merge audmux-v1 and audmux-v2
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-4-git-send-email-shawn.guo@linaro.org>

It merges audmux-v1 and audmux-v2 under arch/arm/plat-mxc into one.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/Kconfig                   |   12 +++---
 arch/arm/plat-mxc/Kconfig                   |    5 +--
 arch/arm/plat-mxc/Makefile                  |    3 +-
 arch/arm/plat-mxc/audmux-v1.c               |   64 ---------------------------
 arch/arm/plat-mxc/{audmux-v2.c => audmux.c} |   29 +++++++++++-
 5 files changed, 34 insertions(+), 79 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/audmux-v1.c
 rename arch/arm/plat-mxc/{audmux-v2.c => audmux.c} (89%)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4defb97..495a854 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -46,7 +46,7 @@ config SOC_IMX21
 	bool
 	select MACH_MX21
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX_V1
+	select ARCH_MXC_AUDMUX
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
@@ -55,7 +55,7 @@ config SOC_IMX25
 	bool
 	select ARCH_MX25
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX_V2
+	select ARCH_MXC_AUDMUX
 	select ARCH_MXC_IOMUX_V3
 	select MXC_AVIC
 
@@ -63,7 +63,7 @@ config SOC_IMX27
 	bool
 	select MACH_MX27
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX_V1
+	select ARCH_MXC_AUDMUX
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
@@ -72,7 +72,7 @@ config SOC_IMX31
 	bool
 	select CPU_V6
 	select IMX_HAVE_PLATFORM_MXC_RNGA
-	select ARCH_MXC_AUDMUX_V2
+	select ARCH_MXC_AUDMUX
 	select MXC_AVIC
 	select SMP_ON_UP if SMP
 
@@ -80,7 +80,7 @@ config SOC_IMX35
 	bool
 	select CPU_V6
 	select ARCH_MXC_IOMUX_V3
-	select ARCH_MXC_AUDMUX_V2
+	select ARCH_MXC_AUDMUX
 	select HAVE_EPIT
 	select MXC_AVIC
 	select SMP_ON_UP if SMP
@@ -89,7 +89,7 @@ config SOC_IMX5
 	select CPU_V7
 	select MXC_TZIC
 	select ARCH_MXC_IOMUX_V3
-	select ARCH_MXC_AUDMUX_V2
+	select ARCH_MXC_AUDMUX
 	select ARCH_HAS_CPUFREQ
 	select ARCH_MX5
 	bool
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index dcebb12..0461d16 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -88,10 +88,7 @@ config IMX_HAVE_IOMUX_V1
 config ARCH_MXC_IOMUX_V3
 	bool
 
-config ARCH_MXC_AUDMUX_V1
-	bool
-
-config ARCH_MXC_AUDMUX_V2
+config ARCH_MXC_AUDMUX
 	bool
 
 config IRAM_ALLOC
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 076db84f..530c81d 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -14,8 +14,7 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
-obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
-obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+obj-$(CONFIG_ARCH_MXC_AUDMUX) += audmux.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
 ifdef CONFIG_SND_IMX_SOC
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
deleted file mode 100644
index 1180bef..0000000
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer at pengutronix.de>
- *
- * Initial development of this code was funded by
- * Phytec Messtechnik GmbH, http://www.phytec.de
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <mach/audmux.h>
-#include <mach/hardware.h>
-
-static void __iomem *audmux_base;
-
-static unsigned char port_mapping[] = {
-	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
-};
-
-int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
-{
-	if (!audmux_base) {
-		printk("%s: not configured\n", __func__);
-		return -ENOSYS;
-	}
-
-	if (port >= ARRAY_SIZE(port_mapping))
-		return -EINVAL;
-
-	writel(pcr, audmux_base + port_mapping[port]);
-
-	return 0;
-}
-EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
-
-static int mxc_audmux_v1_init(void)
-{
-#ifdef CONFIG_MACH_MX21
-	if (cpu_is_mx21())
-		audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR);
-	else
-#endif
-#ifdef CONFIG_MACH_MX27
-	if (cpu_is_mx27())
-		audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR);
-	else
-#endif
-		(void)0;
-	
-	return 0;
-}
-
-postcore_initcall(mxc_audmux_v1_init);
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux.c
similarity index 89%
rename from arch/arm/plat-mxc/audmux-v2.c
rename to arch/arm/plat-mxc/audmux.c
index 8cced35..b49a39f 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux.c
@@ -165,6 +165,24 @@ static inline void audmux_debugfs_init(void)
 }
 #endif
 
+static const uint8_t port_mapping[] = {
+	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
+};
+
+int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
+{
+	if (!audmux_base)
+		return -ENOSYS;
+
+	if (port >= ARRAY_SIZE(port_mapping))
+		return -EINVAL;
+
+	writel(pcr, audmux_base + port_mapping[port]);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
+
 int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 		unsigned int pdcr)
 {
@@ -184,7 +202,7 @@ int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 }
 EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
 
-static int mxc_audmux_v2_init(void)
+static int mxc_audmux_init(void)
 {
 	int ret;
 	if (cpu_is_mx51()) {
@@ -209,11 +227,16 @@ static int mxc_audmux_v2_init(void)
 			return ret;
 		}
 		audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
+	} else if (cpu_is_mx27()) {
+		audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR);
+	} else if (cpu_is_mx21()) {
+		audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR);
 	}
 
-	audmux_debugfs_init();
+	if (!cpu_is_mx2())
+		audmux_debugfs_init();
 
 	return 0;
 }
 
-postcore_initcall(mxc_audmux_v2_init);
+postcore_initcall(mxc_audmux_init);
-- 
1.7.5.4



From broonie at opensource.wolfsonmicro.com  Mon Mar  5 09:20:10 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 14:20:10 +0000
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120305142009.GO3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 10:30:48PM +0800, Shawn Guo wrote:
> Changes since v1:
>  * Address comments from Mark, Timur, and Sascha (Thanks for review).
>  * Drop patches that have been applied by Mark.

I see you've ignored my comments about reordering the patches so they
can be applied more easily :(
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From shawn.guo at linaro.org  Mon Mar  5 09:30:52 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:52 +0800
Subject: [PATCH v2 04/17] ARM: imx: convert audmux to a platform driver
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-5-git-send-email-shawn.guo@linaro.org>

From: Richard Zhao <richard.zhao at linaro.org>

It coverts audmux to a platform driver, so that it can be moved into
sound/soc/imx and adopt device tree support later.

Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/mm-imx21.c |    6 ++
 arch/arm/mach-imx/mm-imx25.c |    7 ++
 arch/arm/mach-imx/mm-imx27.c |    7 ++
 arch/arm/mach-imx/mm-imx3.c  |   13 ++++
 arch/arm/mach-imx/mm-imx5.c  |   22 +++++++
 arch/arm/plat-mxc/audmux.c   |  127 ++++++++++++++++++++++++++++++------------
 6 files changed, 147 insertions(+), 35 deletions(-)

diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 3f05dfe..14d540e 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -75,6 +75,10 @@ void __init mx21_init_irq(void)
 	mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
 }
 
+static const struct resource imx21_audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K),
+};
+
 void __init imx21_soc_init(void)
 {
 	mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
@@ -85,4 +89,6 @@ void __init imx21_soc_init(void)
 	mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
 
 	imx_add_imx_dma();
+	platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
+					ARRAY_SIZE(imx21_audmux_res));
 }
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index cc4d152..153b457 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -83,6 +83,10 @@ static struct sdma_platform_data imx25_sdma_pdata __initdata = {
 	.script_addrs = &imx25_sdma_script,
 };
 
+static const struct resource imx25_audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 void __init imx25_soc_init(void)
 {
 	/* i.mx25 has the i.mx31 type gpio */
@@ -93,4 +97,7 @@ void __init imx25_soc_init(void)
 
 	/* i.mx25 has the i.mx35 type sdma */
 	imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
+	/* i.mx25 has the i.mx31 type audmux */
+	platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res,
+					ARRAY_SIZE(imx25_audmux_res));
 }
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 96dd1f5..8cb3f5e 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -75,6 +75,10 @@ void __init mx27_init_irq(void)
 	mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
 }
 
+static const struct resource imx27_audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K),
+};
+
 void __init imx27_soc_init(void)
 {
 	/* i.mx27 has the i.mx21 type gpio */
@@ -86,4 +90,7 @@ void __init imx27_soc_init(void)
 	mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
 
 	imx_add_imx_dma();
+	/* imx27 has the imx21 type audmux */
+	platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
+					ARRAY_SIZE(imx27_audmux_res));
 }
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 31807d2..2530c15 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -158,6 +158,10 @@ static struct sdma_platform_data imx31_sdma_pdata __initdata = {
 	.script_addrs = &imx31_to2_sdma_script,
 };
 
+static const struct resource imx31_audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 void __init imx31_soc_init(void)
 {
 	int to_version = mx31_revision() >> 4;
@@ -175,6 +179,8 @@ void __init imx31_soc_init(void)
 	}
 
 	imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
+	platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
+					ARRAY_SIZE(imx31_audmux_res));
 }
 #endif /* ifdef CONFIG_SOC_IMX31 */
 
@@ -241,6 +247,10 @@ static struct sdma_platform_data imx35_sdma_pdata __initdata = {
 	.script_addrs = &imx35_to2_sdma_script,
 };
 
+static const struct resource imx35_audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 void __init imx35_soc_init(void)
 {
 	int to_version = mx35_revision() >> 4;
@@ -259,5 +269,8 @@ void __init imx35_soc_init(void)
 	}
 
 	imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
+	/* i.mx35 has the i.mx31 type audmux */
+	platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
+					ARRAY_SIZE(imx35_audmux_res));
 }
 #endif /* ifdef CONFIG_SOC_IMX35 */
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index bc17dfe..90d7880 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -170,6 +170,18 @@ static struct sdma_platform_data imx53_sdma_pdata __initdata = {
 	.script_addrs = &imx53_sdma_script,
 };
 
+static const struct resource imx50_audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
+static const struct resource imx51_audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
+static const struct resource imx53_audmux_res[] __initconst = {
+	DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 void __init imx50_soc_init(void)
 {
 	/* i.mx50 has the i.mx31 type gpio */
@@ -179,6 +191,10 @@ void __init imx50_soc_init(void)
 	mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
 	mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
 	mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
+
+	/* i.mx50 has the i.mx31 type audmux */
+	platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
+					ARRAY_SIZE(imx50_audmux_res));
 }
 
 void __init imx51_soc_init(void)
@@ -191,6 +207,9 @@ void __init imx51_soc_init(void)
 
 	/* i.mx51 has the i.mx35 type sdma */
 	imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
+	/* i.mx51 has the i.mx31 type audmux */
+	platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
+					ARRAY_SIZE(imx51_audmux_res));
 }
 
 void __init imx53_soc_init(void)
@@ -206,4 +225,7 @@ void __init imx53_soc_init(void)
 
 	/* i.mx53 has the i.mx35 type sdma */
 	imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
+	/* i.mx53 has the i.mx31 type audmux */
+	platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
+					ARRAY_SIZE(imx53_audmux_res));
 }
diff --git a/arch/arm/plat-mxc/audmux.c b/arch/arm/plat-mxc/audmux.c
index b49a39f..a8c9e04 100644
--- a/arch/arm/plat-mxc/audmux.c
+++ b/arch/arm/plat-mxc/audmux.c
@@ -1,4 +1,6 @@
 /*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
  * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer at pengutronix.de>
  *
  * Initial development of this code was funded by
@@ -15,14 +17,16 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/debugfs.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <mach/audmux.h>
-#include <mach/hardware.h>
+
+#define DRIVER_NAME "imx-audmux"
 
 static struct clk *audmux_clk;
 static void __iomem *audmux_base;
@@ -140,7 +144,7 @@ static const struct file_operations audmux_debugfs_fops = {
 	.llseek = default_llseek,
 };
 
-static void audmux_debugfs_init(void)
+static void __init audmux_debugfs_init(void)
 {
 	int i;
 	char buf[20];
@@ -159,18 +163,48 @@ static void audmux_debugfs_init(void)
 				   i);
 	}
 }
+
+static void __exit audmux_debugfs_remove(void)
+{
+	debugfs_remove_recursive(audmux_debugfs_root);
+}
 #else
 static inline void audmux_debugfs_init(void)
 {
 }
+
+static inline void audmux_debugfs_remove(void)
+{
+}
 #endif
 
+enum imx_audmux_type {
+	IMX21_AUDMUX,
+	IMX31_AUDMUX,
+} audmux_type;
+
+static struct platform_device_id imx_audmux_ids[] = {
+	{
+		.name = "imx21-audmux",
+		.driver_data = IMX21_AUDMUX,
+	}, {
+		.name = "imx31-audmux",
+		.driver_data = IMX31_AUDMUX,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(platform, imx_audmux_ids);
+
 static const uint8_t port_mapping[] = {
 	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
 };
 
 int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
 {
+	if (audmux_type != IMX21_AUDMUX)
+		return -EINVAL;
+
 	if (!audmux_base)
 		return -ENOSYS;
 
@@ -186,6 +220,9 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
 int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 		unsigned int pdcr)
 {
+	if (audmux_type != IMX31_AUDMUX)
+		return -EINVAL;
+
 	if (!audmux_base)
 		return -ENOSYS;
 
@@ -202,41 +239,61 @@ int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 }
 EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
 
-static int mxc_audmux_init(void)
+static int __init imx_audmux_probe(struct platform_device *pdev)
 {
-	int ret;
-	if (cpu_is_mx51()) {
-		audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR);
-	} else if (cpu_is_mx31()) {
-		audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
-	} else if (cpu_is_mx35()) {
-		audmux_clk = clk_get(NULL, "audmux");
-		if (IS_ERR(audmux_clk)) {
-			ret = PTR_ERR(audmux_clk);
-			printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
-					ret);
-			return ret;
-		}
-		audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
-	} else if (cpu_is_mx25()) {
-		audmux_clk = clk_get(NULL, "audmux");
-		if (IS_ERR(audmux_clk)) {
-			ret = PTR_ERR(audmux_clk);
-			printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
-					ret);
-			return ret;
-		}
-		audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
-	} else if (cpu_is_mx27()) {
-		audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR);
-	} else if (cpu_is_mx21()) {
-		audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR);
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	audmux_base = devm_request_and_ioremap(&pdev->dev, res);
+	if (!audmux_base)
+		return -EADDRNOTAVAIL;
+
+	audmux_clk = clk_get(&pdev->dev, "audmux");
+	if (IS_ERR(audmux_clk)) {
+		dev_dbg(&pdev->dev, "cannot get clock: %ld\n",
+				PTR_ERR(audmux_clk));
+		audmux_clk = NULL;
 	}
 
-	if (!cpu_is_mx2())
+	audmux_type = pdev->id_entry->driver_data;
+	if (audmux_type == IMX31_AUDMUX)
 		audmux_debugfs_init();
 
 	return 0;
 }
 
-postcore_initcall(mxc_audmux_init);
+static int __exit imx_audmux_remove(struct platform_device *pdev)
+{
+	if (audmux_type == IMX31_AUDMUX)
+		audmux_debugfs_remove();
+	clk_put(audmux_clk);
+
+	return 0;
+}
+
+static struct platform_driver imx_audmux_driver = {
+	.probe		= imx_audmux_probe,
+	.remove		= __exit_p(imx_audmux_remove),
+	.id_table	= imx_audmux_ids,
+	.driver	= {
+		.name	= DRIVER_NAME,
+		.owner	= THIS_MODULE,
+	}
+};
+
+static int __init imx_audmux_init(void)
+{
+	return platform_driver_register(&imx_audmux_driver);
+}
+subsys_initcall(imx_audmux_init);
+
+static void __exit imx_audmux_exit(void)
+{
+	platform_driver_unregister(&imx_audmux_driver);
+}
+module_exit(imx_audmux_exit);
+
+MODULE_DESCRIPTION("Freescale i.MX AUDMUX driver");
+MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:30:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:53 +0800
Subject: [PATCH v2 05/17] ASoC: imx: move audmux driver into sound/soc/imx
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-6-git-send-email-shawn.guo@linaro.org>

As audmux becomes a platform driver and its callers are all ASoC
machine drivers, there is no reason to keep it in arch folder, so
move it to sound/soc/imx.

One bonus point would be those ASoC machine drivers stop including
mach/audmux.h, since it's been moved to sound/soc/imx/imx-audmux.h.
This should be a move to the right direction in terms of single kernel
image goal.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/Kconfig                          |    6 ------
 arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c       |    1 -
 arch/arm/plat-mxc/Kconfig                          |    3 ---
 arch/arm/plat-mxc/Makefile                         |    1 -
 sound/soc/imx/Kconfig                              |    7 +++++++
 sound/soc/imx/Makefile                             |    2 ++
 sound/soc/imx/eukrea-tlv320.c                      |    2 +-
 .../audmux.c => sound/soc/imx/imx-audmux.c         |    3 ++-
 .../mach/audmux.h => sound/soc/imx/imx-audmux.h    |    6 +++---
 sound/soc/imx/mx27vis-aic32x4.c                    |    2 +-
 sound/soc/imx/phycore-ac97.c                       |    3 ++-
 sound/soc/imx/wm1133-ev1.c                         |    3 +--
 12 files changed, 19 insertions(+), 20 deletions(-)
 rename arch/arm/plat-mxc/audmux.c => sound/soc/imx/imx-audmux.c (99%)
 rename arch/arm/plat-mxc/include/mach/audmux.h => sound/soc/imx/imx-audmux.h (96%)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 495a854..3919fba 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -46,7 +46,6 @@ config SOC_IMX21
 	bool
 	select MACH_MX21
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
@@ -55,7 +54,6 @@ config SOC_IMX25
 	bool
 	select ARCH_MX25
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX
 	select ARCH_MXC_IOMUX_V3
 	select MXC_AVIC
 
@@ -63,7 +61,6 @@ config SOC_IMX27
 	bool
 	select MACH_MX27
 	select CPU_ARM926T
-	select ARCH_MXC_AUDMUX
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
@@ -72,7 +69,6 @@ config SOC_IMX31
 	bool
 	select CPU_V6
 	select IMX_HAVE_PLATFORM_MXC_RNGA
-	select ARCH_MXC_AUDMUX
 	select MXC_AVIC
 	select SMP_ON_UP if SMP
 
@@ -80,7 +76,6 @@ config SOC_IMX35
 	bool
 	select CPU_V6
 	select ARCH_MXC_IOMUX_V3
-	select ARCH_MXC_AUDMUX
 	select HAVE_EPIT
 	select MXC_AVIC
 	select SMP_ON_UP if SMP
@@ -89,7 +84,6 @@ config SOC_IMX5
 	select CPU_V7
 	select MXC_TZIC
 	select ARCH_MXC_IOMUX_V3
-	select ARCH_MXC_AUDMUX
 	select ARCH_HAS_CPUFREQ
 	select ARCH_MX5
 	bool
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
index d817fc8..aaa592f 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
@@ -37,7 +37,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx51.h>
-#include <mach/audmux.h>
 
 #include "devices-imx51.h"
 
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 0461d16..c722f9c 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -88,9 +88,6 @@ config IMX_HAVE_IOMUX_V1
 config ARCH_MXC_IOMUX_V3
 	bool
 
-config ARCH_MXC_AUDMUX
-	bool
-
 config IRAM_ALLOC
 	bool
 	select GENERIC_ALLOCATOR
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 530c81d..e81290c 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
-obj-$(CONFIG_ARCH_MXC_AUDMUX) += audmux.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
 ifdef CONFIG_SND_IMX_SOC
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index aa4294b..d3b7166 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -16,11 +16,15 @@ config SND_MXC_SOC_MX2
 	select SND_SOC_DMAENGINE_PCM
 	tristate
 
+config SND_SOC_IMX_AUDMUX
+	tristate
+
 config SND_MXC_SOC_WM1133_EV1
 	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
 	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
 	select SND_SOC_WM8350
 	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
 	help
 	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
 	  PMIC board with WM8835x fitted.
@@ -30,6 +34,7 @@ config SND_SOC_MX27VIS_AIC32X4
 	depends on MACH_IMX27_VISSTRIM_M10 && I2C
 	select SND_SOC_TLV320AIC32X4
 	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_AUDMUX
 	help
 	  Say Y if you want to add support for SoC audio on Visstrim SM10
 	  board with TLV320AIC32X4 codec.
@@ -40,6 +45,7 @@ config SND_SOC_PHYCORE_AC97
 	select SND_SOC_AC97_BUS
 	select SND_SOC_WM9712
 	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
 	help
 	  Say Y if you want to add support for SoC audio on Phytec phyCORE
 	  and phyCARD boards in AC97 mode
@@ -53,6 +59,7 @@ config SND_SOC_EUKREA_TLV320
 	depends on I2C
 	select SND_SOC_TLV320AIC23
 	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
 	help
 	  Enable I2S based access to the TLV320AIC23B codec attached
 	  to the SSI interface
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
index d6d609b..5c40541 100644
--- a/sound/soc/imx/Makefile
+++ b/sound/soc/imx/Makefile
@@ -2,10 +2,12 @@
 snd-soc-imx-objs := imx-ssi.o
 snd-soc-imx-fiq-objs := imx-pcm-fiq.o
 snd-soc-imx-mx2-objs := imx-pcm-dma-mx2.o
+snd-soc-imx-audmux-objs := imx-audmux.o
 
 obj-$(CONFIG_SND_IMX_SOC) += snd-soc-imx.o
 obj-$(CONFIG_SND_MXC_SOC_FIQ) += snd-soc-imx-fiq.o
 obj-$(CONFIG_SND_MXC_SOC_MX2) += snd-soc-imx-mx2.o
+obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
 
 # i.MX Machine Support
 snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/imx/eukrea-tlv320.c
index bfcb6d9..b375ed4 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/imx/eukrea-tlv320.c
@@ -23,10 +23,10 @@
 #include <sound/pcm.h>
 #include <sound/soc.h>
 #include <asm/mach-types.h>
-#include <mach/audmux.h>
 
 #include "../codecs/tlv320aic23.h"
 #include "imx-ssi.h"
+#include "imx-audmux.h"
 
 #define CODEC_CLOCK 12000000
 
diff --git a/arch/arm/plat-mxc/audmux.c b/sound/soc/imx/imx-audmux.c
similarity index 99%
rename from arch/arm/plat-mxc/audmux.c
rename to sound/soc/imx/imx-audmux.c
index a8c9e04..7b16266 100644
--- a/arch/arm/plat-mxc/audmux.c
+++ b/sound/soc/imx/imx-audmux.c
@@ -24,7 +24,8 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
-#include <mach/audmux.h>
+
+#include "imx-audmux.h"
 
 #define DRIVER_NAME "imx-audmux"
 
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/sound/soc/imx/imx-audmux.h
similarity index 96%
rename from arch/arm/plat-mxc/include/mach/audmux.h
rename to sound/soc/imx/imx-audmux.h
index 6fda788..5136d948 100644
--- a/arch/arm/plat-mxc/include/mach/audmux.h
+++ b/sound/soc/imx/imx-audmux.h
@@ -1,5 +1,5 @@
-#ifndef __MACH_AUDMUX_H
-#define __MACH_AUDMUX_H
+#ifndef __IMX_AUDMUX_H
+#define __IMX_AUDMUX_H
 
 #define MX27_AUDMUX_HPCR1_SSI0		0
 #define MX27_AUDMUX_HPCR2_SSI1		1
@@ -57,4 +57,4 @@ int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
 int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 		unsigned int pdcr);
 
-#endif /* __MACH_AUDMUX_H */
+#endif /* __IMX_AUDMUX_H */
diff --git a/sound/soc/imx/mx27vis-aic32x4.c b/sound/soc/imx/mx27vis-aic32x4.c
index 155899c..dbfad0f 100644
--- a/sound/soc/imx/mx27vis-aic32x4.c
+++ b/sound/soc/imx/mx27vis-aic32x4.c
@@ -32,11 +32,11 @@
 #include <sound/soc-dapm.h>
 #include <sound/tlv.h>
 #include <asm/mach-types.h>
-#include <mach/audmux.h>
 #include <mach/iomux-mx27.h>
 
 #include "../codecs/tlv320aic32x4.h"
 #include "imx-ssi.h"
+#include "imx-audmux.h"
 
 #define MX27VIS_AMP_GAIN	0
 #define MX27VIS_AMP_MUTE	1
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/imx/phycore-ac97.c
index a59692e..7dab077 100644
--- a/sound/soc/imx/phycore-ac97.c
+++ b/sound/soc/imx/phycore-ac97.c
@@ -18,7 +18,8 @@
 #include <sound/pcm.h>
 #include <sound/soc.h>
 #include <asm/mach-types.h>
-#include <mach/audmux.h>
+
+#include "imx-audmux.h"
 
 static struct snd_soc_card imx_phycore;
 
diff --git a/sound/soc/imx/wm1133-ev1.c b/sound/soc/imx/wm1133-ev1.c
index 37480c9..15056d6 100644
--- a/sound/soc/imx/wm1133-ev1.c
+++ b/sound/soc/imx/wm1133-ev1.c
@@ -21,10 +21,9 @@
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 
-#include <mach/audmux.h>
-
 #include "imx-ssi.h"
 #include "../codecs/wm8350.h"
+#include "imx-audmux.h"
 
 /* There is a silicon mic on the board optionally connected via a solder pad
  * SP1.  Define this to enable it.
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:30:54 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:54 +0800
Subject: [PATCH v2 06/17] ASoC: imx: rename audmux prefix mxc to imx
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-7-git-send-email-shawn.guo@linaro.org>

It renames the legacy name mxc used in audmux function and macro
to imx.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/imx/eukrea-tlv320.c   |   44 +++++++++++++++---------------
 sound/soc/imx/imx-audmux.c      |   30 ++++++++++----------
 sound/soc/imx/imx-audmux.h      |   58 +++++++++++++++++++-------------------
 sound/soc/imx/mx27vis-aic32x4.c |   18 ++++++------
 sound/soc/imx/phycore-ac97.c    |   40 +++++++++++++-------------
 sound/soc/imx/wm1133-ev1.c      |   22 +++++++-------
 6 files changed, 106 insertions(+), 106 deletions(-)

diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/imx/eukrea-tlv320.c
index b375ed4..7d4475c 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/imx/eukrea-tlv320.c
@@ -101,35 +101,35 @@ static int __init eukrea_tlv320_init(void)
 	int int_port = 0, ext_port;
 
 	if (machine_is_eukrea_cpuimx27()) {
-		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_TFSDIR |
-			MXC_AUDMUX_V1_PCR_TCLKDIR |
-			MXC_AUDMUX_V1_PCR_RFSDIR |
-			MXC_AUDMUX_V1_PCR_RCLKDIR |
-			MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
-			MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
+		imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+			IMX_AUDMUX_V1_PCR_SYN |
+			IMX_AUDMUX_V1_PCR_TFSDIR |
+			IMX_AUDMUX_V1_PCR_TCLKDIR |
+			IMX_AUDMUX_V1_PCR_RFSDIR |
+			IMX_AUDMUX_V1_PCR_RCLKDIR |
+			IMX_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+			IMX_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+			IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
 		);
-		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+		imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
+			IMX_AUDMUX_V1_PCR_SYN |
+			IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
 		);
 	} else if (machine_is_eukrea_cpuimx25sd() ||
 		   machine_is_eukrea_cpuimx35sd() ||
 		   machine_is_eukrea_cpuimx51sd()) {
 		ext_port = machine_is_eukrea_cpuimx25sd() ? 4 : 3;
-		mxc_audmux_v2_configure_port(int_port,
-			MXC_AUDMUX_V2_PTCR_SYN |
-			MXC_AUDMUX_V2_PTCR_TFSDIR |
-			MXC_AUDMUX_V2_PTCR_TFSEL(ext_port) |
-			MXC_AUDMUX_V2_PTCR_TCLKDIR |
-			MXC_AUDMUX_V2_PTCR_TCSEL(ext_port),
-			MXC_AUDMUX_V2_PDCR_RXDSEL(ext_port)
+		imx_audmux_v2_configure_port(int_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TFSDIR |
+			IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TCLKDIR |
+			IMX_AUDMUX_V2_PTCR_TCSEL(ext_port),
+			IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port)
 		);
-		mxc_audmux_v2_configure_port(ext_port,
-			MXC_AUDMUX_V2_PTCR_SYN,
-			MXC_AUDMUX_V2_PDCR_RXDSEL(int_port)
+		imx_audmux_v2_configure_port(ext_port,
+			IMX_AUDMUX_V2_PTCR_SYN,
+			IMX_AUDMUX_V2_PDCR_RXDSEL(int_port)
 		);
 	} else {
 		/* return happy. We might run on a totally different machine */
diff --git a/sound/soc/imx/imx-audmux.c b/sound/soc/imx/imx-audmux.c
index 7b16266..87f8768 100644
--- a/sound/soc/imx/imx-audmux.c
+++ b/sound/soc/imx/imx-audmux.c
@@ -32,8 +32,8 @@
 static struct clk *audmux_clk;
 static void __iomem *audmux_base;
 
-#define MXC_AUDMUX_V2_PTCR(x)		((x) * 8)
-#define MXC_AUDMUX_V2_PDCR(x)		((x) * 8 + 4)
+#define IMX_AUDMUX_V2_PTCR(x)		((x) * 8)
+#define IMX_AUDMUX_V2_PDCR(x)		((x) * 8 + 4)
 
 #ifdef CONFIG_DEBUG_FS
 static struct dentry *audmux_debugfs_root;
@@ -80,8 +80,8 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 	if (audmux_clk)
 		clk_enable(audmux_clk);
 
-	ptcr = readl(audmux_base + MXC_AUDMUX_V2_PTCR(port));
-	pdcr = readl(audmux_base + MXC_AUDMUX_V2_PDCR(port));
+	ptcr = readl(audmux_base + IMX_AUDMUX_V2_PTCR(port));
+	pdcr = readl(audmux_base + IMX_AUDMUX_V2_PDCR(port));
 
 	if (audmux_clk)
 		clk_disable(audmux_clk);
@@ -89,7 +89,7 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 	ret = snprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n",
 		       pdcr, ptcr);
 
-	if (ptcr & MXC_AUDMUX_V2_PTCR_TFSDIR)
+	if (ptcr & IMX_AUDMUX_V2_PTCR_TFSDIR)
 		ret += snprintf(buf + ret, PAGE_SIZE - ret,
 				"TxFS output from %s, ",
 				audmux_port_string((ptcr >> 27) & 0x7));
@@ -97,7 +97,7 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 		ret += snprintf(buf + ret, PAGE_SIZE - ret,
 				"TxFS input, ");
 
-	if (ptcr & MXC_AUDMUX_V2_PTCR_TCLKDIR)
+	if (ptcr & IMX_AUDMUX_V2_PTCR_TCLKDIR)
 		ret += snprintf(buf + ret, PAGE_SIZE - ret,
 				"TxClk output from %s",
 				audmux_port_string((ptcr >> 22) & 0x7));
@@ -107,11 +107,11 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 
 	ret += snprintf(buf + ret, PAGE_SIZE - ret, "\n");
 
-	if (ptcr & MXC_AUDMUX_V2_PTCR_SYN) {
+	if (ptcr & IMX_AUDMUX_V2_PTCR_SYN) {
 		ret += snprintf(buf + ret, PAGE_SIZE - ret,
 				"Port is symmetric");
 	} else {
-		if (ptcr & MXC_AUDMUX_V2_PTCR_RFSDIR)
+		if (ptcr & IMX_AUDMUX_V2_PTCR_RFSDIR)
 			ret += snprintf(buf + ret, PAGE_SIZE - ret,
 					"RxFS output from %s, ",
 					audmux_port_string((ptcr >> 17) & 0x7));
@@ -119,7 +119,7 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
 			ret += snprintf(buf + ret, PAGE_SIZE - ret,
 					"RxFS input, ");
 
-		if (ptcr & MXC_AUDMUX_V2_PTCR_RCLKDIR)
+		if (ptcr & IMX_AUDMUX_V2_PTCR_RCLKDIR)
 			ret += snprintf(buf + ret, PAGE_SIZE - ret,
 					"RxClk output from %s",
 					audmux_port_string((ptcr >> 12) & 0x7));
@@ -201,7 +201,7 @@ static const uint8_t port_mapping[] = {
 	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
 };
 
-int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
+int imx_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
 {
 	if (audmux_type != IMX21_AUDMUX)
 		return -EINVAL;
@@ -216,9 +216,9 @@ int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
+EXPORT_SYMBOL_GPL(imx_audmux_v1_configure_port);
 
-int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
+int imx_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 		unsigned int pdcr)
 {
 	if (audmux_type != IMX31_AUDMUX)
@@ -230,15 +230,15 @@ int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 	if (audmux_clk)
 		clk_enable(audmux_clk);
 
-	writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port));
-	writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port));
+	writel(ptcr, audmux_base + IMX_AUDMUX_V2_PTCR(port));
+	writel(pdcr, audmux_base + IMX_AUDMUX_V2_PDCR(port));
 
 	if (audmux_clk)
 		clk_disable(audmux_clk);
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
+EXPORT_SYMBOL_GPL(imx_audmux_v2_configure_port);
 
 static int __init imx_audmux_probe(struct platform_device *pdev)
 {
diff --git a/sound/soc/imx/imx-audmux.h b/sound/soc/imx/imx-audmux.h
index 5136d948..04ebbab 100644
--- a/sound/soc/imx/imx-audmux.h
+++ b/sound/soc/imx/imx-audmux.h
@@ -24,37 +24,37 @@
 #define MX51_AUDMUX_PORT7		6
 
 /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
-#define MXC_AUDMUX_V1_PCR_INMMASK(x)	((x) & 0xff)
-#define MXC_AUDMUX_V1_PCR_INMEN		(1 << 8)
-#define MXC_AUDMUX_V1_PCR_TXRXEN	(1 << 10)
-#define MXC_AUDMUX_V1_PCR_SYN		(1 << 12)
-#define MXC_AUDMUX_V1_PCR_RXDSEL(x)	(((x) & 0x7) << 13)
-#define MXC_AUDMUX_V1_PCR_RFCSEL(x)	(((x) & 0xf) << 20)
-#define MXC_AUDMUX_V1_PCR_RCLKDIR	(1 << 24)
-#define MXC_AUDMUX_V1_PCR_RFSDIR	(1 << 25)
-#define MXC_AUDMUX_V1_PCR_TFCSEL(x)	(((x) & 0xf) << 26)
-#define MXC_AUDMUX_V1_PCR_TCLKDIR	(1 << 30)
-#define MXC_AUDMUX_V1_PCR_TFSDIR	(1 << 31)
+#define IMX_AUDMUX_V1_PCR_INMMASK(x)	((x) & 0xff)
+#define IMX_AUDMUX_V1_PCR_INMEN		(1 << 8)
+#define IMX_AUDMUX_V1_PCR_TXRXEN	(1 << 10)
+#define IMX_AUDMUX_V1_PCR_SYN		(1 << 12)
+#define IMX_AUDMUX_V1_PCR_RXDSEL(x)	(((x) & 0x7) << 13)
+#define IMX_AUDMUX_V1_PCR_RFCSEL(x)	(((x) & 0xf) << 20)
+#define IMX_AUDMUX_V1_PCR_RCLKDIR	(1 << 24)
+#define IMX_AUDMUX_V1_PCR_RFSDIR	(1 << 25)
+#define IMX_AUDMUX_V1_PCR_TFCSEL(x)	(((x) & 0xf) << 26)
+#define IMX_AUDMUX_V1_PCR_TCLKDIR	(1 << 30)
+#define IMX_AUDMUX_V1_PCR_TFSDIR	(1 << 31)
 
 /* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */
-#define MXC_AUDMUX_V2_PTCR_TFSDIR	(1 << 31)
-#define MXC_AUDMUX_V2_PTCR_TFSEL(x)	(((x) & 0xf) << 27)
-#define MXC_AUDMUX_V2_PTCR_TCLKDIR	(1 << 26)
-#define MXC_AUDMUX_V2_PTCR_TCSEL(x)	(((x) & 0xf) << 22)
-#define MXC_AUDMUX_V2_PTCR_RFSDIR	(1 << 21)
-#define MXC_AUDMUX_V2_PTCR_RFSEL(x)	(((x) & 0xf) << 17)
-#define MXC_AUDMUX_V2_PTCR_RCLKDIR	(1 << 16)
-#define MXC_AUDMUX_V2_PTCR_RCSEL(x)	(((x) & 0xf) << 12)
-#define MXC_AUDMUX_V2_PTCR_SYN		(1 << 11)
-
-#define MXC_AUDMUX_V2_PDCR_RXDSEL(x)	(((x) & 0x7) << 13)
-#define MXC_AUDMUX_V2_PDCR_TXRXEN	(1 << 12)
-#define MXC_AUDMUX_V2_PDCR_MODE(x)	(((x) & 0x3) << 8)
-#define MXC_AUDMUX_V2_PDCR_INMMASK(x)	((x) & 0xff)
-
-int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
-
-int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
+#define IMX_AUDMUX_V2_PTCR_TFSDIR	(1 << 31)
+#define IMX_AUDMUX_V2_PTCR_TFSEL(x)	(((x) & 0xf) << 27)
+#define IMX_AUDMUX_V2_PTCR_TCLKDIR	(1 << 26)
+#define IMX_AUDMUX_V2_PTCR_TCSEL(x)	(((x) & 0xf) << 22)
+#define IMX_AUDMUX_V2_PTCR_RFSDIR	(1 << 21)
+#define IMX_AUDMUX_V2_PTCR_RFSEL(x)	(((x) & 0xf) << 17)
+#define IMX_AUDMUX_V2_PTCR_RCLKDIR	(1 << 16)
+#define IMX_AUDMUX_V2_PTCR_RCSEL(x)	(((x) & 0xf) << 12)
+#define IMX_AUDMUX_V2_PTCR_SYN		(1 << 11)
+
+#define IMX_AUDMUX_V2_PDCR_RXDSEL(x)	(((x) & 0x7) << 13)
+#define IMX_AUDMUX_V2_PDCR_TXRXEN	(1 << 12)
+#define IMX_AUDMUX_V2_PDCR_MODE(x)	(((x) & 0x3) << 8)
+#define IMX_AUDMUX_V2_PDCR_INMMASK(x)	((x) & 0xff)
+
+int imx_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
+
+int imx_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
 		unsigned int pdcr);
 
 #endif /* __IMX_AUDMUX_H */
diff --git a/sound/soc/imx/mx27vis-aic32x4.c b/sound/soc/imx/mx27vis-aic32x4.c
index dbfad0f..976f857 100644
--- a/sound/soc/imx/mx27vis-aic32x4.c
+++ b/sound/soc/imx/mx27vis-aic32x4.c
@@ -207,16 +207,16 @@ static int __init mx27vis_aic32x4_init(void)
 	}
 
 	/* Connect SSI0 as clock slave to SSI1 external pins */
-	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_TFSDIR |
-			MXC_AUDMUX_V1_PCR_TCLKDIR |
-			MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1) |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1)
+	imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+			IMX_AUDMUX_V1_PCR_SYN |
+			IMX_AUDMUX_V1_PCR_TFSDIR |
+			IMX_AUDMUX_V1_PCR_TCLKDIR |
+			IMX_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1) |
+			IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_PPCR1_SSI_PINS_1)
 	);
-	mxc_audmux_v1_configure_port(MX27_AUDMUX_PPCR1_SSI_PINS_1,
-			MXC_AUDMUX_V1_PCR_SYN |
-			MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+	imx_audmux_v1_configure_port(MX27_AUDMUX_PPCR1_SSI_PINS_1,
+			IMX_AUDMUX_V1_PCR_SYN |
+			IMX_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
 	);
 
 	ret = mxc_gpio_setup_multiple_pins(mx27vis_amp_pins,
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/imx/phycore-ac97.c
index 7dab077..f8da6dd 100644
--- a/sound/soc/imx/phycore-ac97.c
+++ b/sound/soc/imx/phycore-ac97.c
@@ -53,27 +53,27 @@ static int __init imx_phycore_init(void)
 	int ret;
 
 	if (machine_is_pca100()) {
-		mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-			MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V1_PCR_TFCSEL(3) |
-			MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
-			MXC_AUDMUX_V1_PCR_RXDSEL(3));
-		mxc_audmux_v1_configure_port(3,
-			MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V1_PCR_TFCSEL(0) |
-			MXC_AUDMUX_V1_PCR_TFSDIR |
-			MXC_AUDMUX_V1_PCR_RXDSEL(0));
+		imx_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+			IMX_AUDMUX_V1_PCR_TFCSEL(3) |
+			IMX_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
+			IMX_AUDMUX_V1_PCR_RXDSEL(3));
+		imx_audmux_v1_configure_port(3,
+			IMX_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+			IMX_AUDMUX_V1_PCR_TFCSEL(0) |
+			IMX_AUDMUX_V1_PCR_TFSDIR |
+			IMX_AUDMUX_V1_PCR_RXDSEL(0));
 	} else if (machine_is_pcm043()) {
-		mxc_audmux_v2_configure_port(3,
-			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V2_PTCR_TFSEL(0) |
-			MXC_AUDMUX_V2_PTCR_TFSDIR,
-			MXC_AUDMUX_V2_PDCR_RXDSEL(0));
-		mxc_audmux_v2_configure_port(0,
-			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-			MXC_AUDMUX_V2_PTCR_TCSEL(3) |
-			MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
-			MXC_AUDMUX_V2_PDCR_RXDSEL(3));
+		imx_audmux_v2_configure_port(3,
+			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+			IMX_AUDMUX_V2_PTCR_TFSEL(0) |
+			IMX_AUDMUX_V2_PTCR_TFSDIR,
+			IMX_AUDMUX_V2_PDCR_RXDSEL(0));
+		imx_audmux_v2_configure_port(0,
+			IMX_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+			IMX_AUDMUX_V2_PTCR_TCSEL(3) |
+			IMX_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
+			IMX_AUDMUX_V2_PDCR_RXDSEL(3));
 	} else {
 		/* return happy. We might run on a totally different machine */
 		return 0;
diff --git a/sound/soc/imx/wm1133-ev1.c b/sound/soc/imx/wm1133-ev1.c
index 15056d6..fe54a69 100644
--- a/sound/soc/imx/wm1133-ev1.c
+++ b/sound/soc/imx/wm1133-ev1.c
@@ -267,17 +267,17 @@ static int __init wm1133_ev1_audio_init(void)
 	unsigned int ptcr, pdcr;
 
 	/* SSI0 mastered by port 5 */
-	ptcr = MXC_AUDMUX_V2_PTCR_SYN |
-		MXC_AUDMUX_V2_PTCR_TFSDIR |
-		MXC_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT5_SSI_PINS_5) |
-		MXC_AUDMUX_V2_PTCR_TCLKDIR |
-		MXC_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT5_SSI_PINS_5);
-	pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT5_SSI_PINS_5);
-	mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT1_SSI0, ptcr, pdcr);
-
-	ptcr = MXC_AUDMUX_V2_PTCR_SYN;
-	pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0);
-	mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT5_SSI_PINS_5, ptcr, pdcr);
+	ptcr = IMX_AUDMUX_V2_PTCR_SYN |
+		IMX_AUDMUX_V2_PTCR_TFSDIR |
+		IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT5_SSI_PINS_5) |
+		IMX_AUDMUX_V2_PTCR_TCLKDIR |
+		IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT5_SSI_PINS_5);
+	pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT5_SSI_PINS_5);
+	imx_audmux_v2_configure_port(MX31_AUDMUX_PORT1_SSI0, ptcr, pdcr);
+
+	ptcr = IMX_AUDMUX_V2_PTCR_SYN;
+	pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0);
+	imx_audmux_v2_configure_port(MX31_AUDMUX_PORT5_SSI_PINS_5, ptcr, pdcr);
 
 	wm1133_ev1_snd_device = platform_device_alloc("soc-audio", -1);
 	if (!wm1133_ev1_snd_device)
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:30:55 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:55 +0800
Subject: [PATCH v2 07/17] ASoC: imx: separate imx-pcm bits from imx-ssi driver
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-8-git-send-email-shawn.guo@linaro.org>

Currently the imx-ssi.c[h] accommodates the imx-pcm common bits which
are shared between imx-pcm-dma-mx2 and imx-pcm-fiq drivers.  It assumes
that imx-pcm-dma-mx2 and imx-pcm-fiq will always be used together with
imx-ssi driver.  However this becomes untrue when we see that driver
sound/soc/fsl/fsl_ssi could possibly work with imx-pcm-dma-mx2 too.

The patch moves the imx-pcm common bits from imx-ssi.c[h] into new
files imx-pcm.c[h], and let imx-pcm-dma-mx2 and imx-pcm-fiq drivers
build it in, so that imx-pcm-dma-mx2 can work with no dependency on
imx-ssi driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/imx/Kconfig           |    7 ++-
 sound/soc/imx/Makefile          |    9 ++--
 sound/soc/imx/imx-pcm-dma-mx2.c |    2 +-
 sound/soc/imx/imx-pcm.c         |  105 +++++++++++++++++++++++++++++++++++++++
 sound/soc/imx/imx-pcm.h         |   32 ++++++++++++
 sound/soc/imx/imx-ssi.c         |   88 --------------------------------
 sound/soc/imx/imx-ssi.h         |   16 +------
 7 files changed, 150 insertions(+), 109 deletions(-)
 create mode 100644 sound/soc/imx/imx-pcm.c
 create mode 100644 sound/soc/imx/imx-pcm.h

diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index d3b7166..2566032 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -8,13 +8,18 @@ menuconfig SND_IMX_SOC
 
 if SND_IMX_SOC
 
+config SND_SOC_IMX_PCM
+	tristate
+
 config SND_MXC_SOC_FIQ
-	select FIQ
 	tristate
+	select FIQ
+	select SND_SOC_IMX_PCM
 
 config SND_MXC_SOC_MX2
 	select SND_SOC_DMAENGINE_PCM
 	tristate
+	select SND_SOC_IMX_PCM
 
 config SND_SOC_IMX_AUDMUX
 	tristate
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
index 5c40541..e9ed362 100644
--- a/sound/soc/imx/Makefile
+++ b/sound/soc/imx/Makefile
@@ -1,14 +1,15 @@
 # i.MX Platform Support
 snd-soc-imx-objs := imx-ssi.o
-snd-soc-imx-fiq-objs := imx-pcm-fiq.o
-snd-soc-imx-mx2-objs := imx-pcm-dma-mx2.o
 snd-soc-imx-audmux-objs := imx-audmux.o
 
 obj-$(CONFIG_SND_IMX_SOC) += snd-soc-imx.o
-obj-$(CONFIG_SND_MXC_SOC_FIQ) += snd-soc-imx-fiq.o
-obj-$(CONFIG_SND_MXC_SOC_MX2) += snd-soc-imx-mx2.o
 obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
 
+obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
+snd-soc-imx-pcm-y := imx-pcm.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
+
 # i.MX Machine Support
 snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
 snd-soc-phycore-ac97-objs := phycore-ac97.o
diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/imx/imx-pcm-dma-mx2.c
index 471e221..e43c8fa 100644
--- a/sound/soc/imx/imx-pcm-dma-mx2.c
+++ b/sound/soc/imx/imx-pcm-dma-mx2.c
@@ -31,7 +31,7 @@
 
 #include <mach/dma.h>
 
-#include "imx-ssi.h"
+#include "imx-pcm.h"
 
 static bool filter(struct dma_chan *chan, void *param)
 {
diff --git a/sound/soc/imx/imx-pcm.c b/sound/soc/imx/imx-pcm.c
new file mode 100644
index 0000000..93dc360
--- /dev/null
+++ b/sound/soc/imx/imx-pcm.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2009 Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This code is based on code copyrighted by Freescale,
+ * Liam Girdwood, Javier Martin and probably others.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include "imx-pcm.h"
+
+int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
+		struct vm_area_struct *vma)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	int ret;
+
+	ret = dma_mmap_writecombine(substream->pcm->card->dev, vma,
+		runtime->dma_area, runtime->dma_addr, runtime->dma_bytes);
+
+	pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
+			runtime->dma_area,
+			runtime->dma_addr,
+			runtime->dma_bytes);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(snd_imx_pcm_mmap);
+
+static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
+{
+	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+	struct snd_dma_buffer *buf = &substream->dma_buffer;
+	size_t size = IMX_SSI_DMABUF_SIZE;
+
+	buf->dev.type = SNDRV_DMA_TYPE_DEV;
+	buf->dev.dev = pcm->card->dev;
+	buf->private_data = NULL;
+	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
+					   &buf->addr, GFP_KERNEL);
+	if (!buf->area)
+		return -ENOMEM;
+	buf->bytes = size;
+
+	return 0;
+}
+
+static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
+
+int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
+{
+	struct snd_card *card = rtd->card->snd_card;
+	struct snd_pcm *pcm = rtd->pcm;
+	int ret = 0;
+
+	if (!card->dev->dma_mask)
+		card->dev->dma_mask = &imx_pcm_dmamask;
+	if (!card->dev->coherent_dma_mask)
+		card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
+	if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
+		ret = imx_pcm_preallocate_dma_buffer(pcm,
+			SNDRV_PCM_STREAM_PLAYBACK);
+		if (ret)
+			goto out;
+	}
+
+	if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
+		ret = imx_pcm_preallocate_dma_buffer(pcm,
+			SNDRV_PCM_STREAM_CAPTURE);
+		if (ret)
+			goto out;
+	}
+
+out:
+	return ret;
+}
+EXPORT_SYMBOL_GPL(imx_pcm_new);
+
+void imx_pcm_free(struct snd_pcm *pcm)
+{
+	struct snd_pcm_substream *substream;
+	struct snd_dma_buffer *buf;
+	int stream;
+
+	for (stream = 0; stream < 2; stream++) {
+		substream = pcm->streams[stream].substream;
+		if (!substream)
+			continue;
+
+		buf = &substream->dma_buffer;
+		if (!buf->area)
+			continue;
+
+		dma_free_writecombine(pcm->card->dev, buf->bytes,
+				      buf->area, buf->addr);
+		buf->area = NULL;
+	}
+}
+EXPORT_SYMBOL_GPL(imx_pcm_free);
diff --git a/sound/soc/imx/imx-pcm.h b/sound/soc/imx/imx-pcm.h
new file mode 100644
index 0000000..b5f5c3a
--- /dev/null
+++ b/sound/soc/imx/imx-pcm.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2009 Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This code is based on code copyrighted by Freescale,
+ * Liam Girdwood, Javier Martin and probably others.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _IMX_PCM_H
+#define _IMX_PCM_H
+
+/*
+ * Do not change this as the FIQ handler depends on this size
+ */
+#define IMX_SSI_DMABUF_SIZE	(64 * 1024)
+
+struct imx_pcm_dma_params {
+	int dma;
+	unsigned long dma_addr;
+	int burstsize;
+};
+
+int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
+		     struct vm_area_struct *vma);
+int imx_pcm_new(struct snd_soc_pcm_runtime *rtd);
+void imx_pcm_free(struct snd_pcm *pcm);
+
+#endif /* _IMX_PCM_H */
diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/imx/imx-ssi.c
index 9af3a5b..4f81ed4 100644
--- a/sound/soc/imx/imx-ssi.c
+++ b/sound/soc/imx/imx-ssi.c
@@ -363,94 +363,6 @@ static const struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
 	.trigger	= imx_ssi_trigger,
 };
 
-int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
-		struct vm_area_struct *vma)
-{
-	struct snd_pcm_runtime *runtime = substream->runtime;
-	int ret;
-
-	ret = dma_mmap_writecombine(substream->pcm->card->dev, vma,
-		runtime->dma_area, runtime->dma_addr, runtime->dma_bytes);
-
-	pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
-			runtime->dma_area,
-			runtime->dma_addr,
-			runtime->dma_bytes);
-	return ret;
-}
-EXPORT_SYMBOL_GPL(snd_imx_pcm_mmap);
-
-static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
-{
-	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
-	struct snd_dma_buffer *buf = &substream->dma_buffer;
-	size_t size = IMX_SSI_DMABUF_SIZE;
-
-	buf->dev.type = SNDRV_DMA_TYPE_DEV;
-	buf->dev.dev = pcm->card->dev;
-	buf->private_data = NULL;
-	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
-					   &buf->addr, GFP_KERNEL);
-	if (!buf->area)
-		return -ENOMEM;
-	buf->bytes = size;
-
-	return 0;
-}
-
-static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
-
-int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
-{
-	struct snd_card *card = rtd->card->snd_card;
-	struct snd_pcm *pcm = rtd->pcm;
-	int ret = 0;
-
-	if (!card->dev->dma_mask)
-		card->dev->dma_mask = &imx_pcm_dmamask;
-	if (!card->dev->coherent_dma_mask)
-		card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
-	if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
-		ret = imx_pcm_preallocate_dma_buffer(pcm,
-			SNDRV_PCM_STREAM_PLAYBACK);
-		if (ret)
-			goto out;
-	}
-
-	if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
-		ret = imx_pcm_preallocate_dma_buffer(pcm,
-			SNDRV_PCM_STREAM_CAPTURE);
-		if (ret)
-			goto out;
-	}
-
-out:
-	return ret;
-}
-EXPORT_SYMBOL_GPL(imx_pcm_new);
-
-void imx_pcm_free(struct snd_pcm *pcm)
-{
-	struct snd_pcm_substream *substream;
-	struct snd_dma_buffer *buf;
-	int stream;
-
-	for (stream = 0; stream < 2; stream++) {
-		substream = pcm->streams[stream].substream;
-		if (!substream)
-			continue;
-
-		buf = &substream->dma_buffer;
-		if (!buf->area)
-			continue;
-
-		dma_free_writecombine(pcm->card->dev, buf->bytes,
-				      buf->area, buf->addr);
-		buf->area = NULL;
-	}
-}
-EXPORT_SYMBOL_GPL(imx_pcm_free);
-
 static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
 {
 	struct imx_ssi *ssi = dev_get_drvdata(dai->dev);
diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/imx/imx-ssi.h
index 1072dfb..5744e86 100644
--- a/sound/soc/imx/imx-ssi.h
+++ b/sound/soc/imx/imx-ssi.h
@@ -187,12 +187,7 @@
 
 #include <linux/dmaengine.h>
 #include <mach/dma.h>
-
-struct imx_pcm_dma_params {
-	int dma;
-	unsigned long dma_addr;
-	int burstsize;
-};
+#include "imx-pcm.h"
 
 struct imx_ssi {
 	struct platform_device *ac97_dev;
@@ -218,13 +213,4 @@ struct imx_ssi {
 	struct platform_device *soc_platform_pdev_fiq;
 };
 
-int snd_imx_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma);
-int imx_pcm_new(struct snd_soc_pcm_runtime *rtd);
-void imx_pcm_free(struct snd_pcm *pcm);
-
-/*
- * Do not change this as the FIQ handler depends on this size
- */
-#define IMX_SSI_DMABUF_SIZE	(64 * 1024)
-
 #endif /* _IMX_SSI_H */
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:30:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:56 +0800
Subject: [PATCH v2 08/17] ASoC: imx: add an explicit Kconfig option for
 imx-ssi driver
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-9-git-send-email-shawn.guo@linaro.org>

Currently ASoC:imx uses menuconfig option SND_IMX_SOC selects imx-ssi
driver, and it works because all the machine driver covered by the
menuconfig need to build imx-ssi driver in.  However, it will not work
any more if we have a imx based machine driver going into the menuconfig
while working with fsl_ssi driver (sound/soc/fsl/fsl_ssi.c) rather than
imx-ssi one.

The patch adds an explicit Kconfig option SND_SOC_IMX_SSI for imx-ssi
driver, so that it can be selected independently from the menuconfig
option SND_IMX_SOC.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/imx/Kconfig  |    7 +++++++
 sound/soc/imx/Makefile |    4 ++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index 2566032..810acaa 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -8,6 +8,9 @@ menuconfig SND_IMX_SOC
 
 if SND_IMX_SOC
 
+config SND_SOC_IMX_SSI
+	tristate
+
 config SND_SOC_IMX_PCM
 	tristate
 
@@ -30,6 +33,7 @@ config SND_MXC_SOC_WM1133_EV1
 	select SND_SOC_WM8350
 	select SND_MXC_SOC_FIQ
 	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
 	help
 	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
 	  PMIC board with WM8835x fitted.
@@ -40,6 +44,7 @@ config SND_SOC_MX27VIS_AIC32X4
 	select SND_SOC_TLV320AIC32X4
 	select SND_MXC_SOC_MX2
 	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
 	help
 	  Say Y if you want to add support for SoC audio on Visstrim SM10
 	  board with TLV320AIC32X4 codec.
@@ -51,6 +56,7 @@ config SND_SOC_PHYCORE_AC97
 	select SND_SOC_WM9712
 	select SND_MXC_SOC_FIQ
 	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
 	help
 	  Say Y if you want to add support for SoC audio on Phytec phyCORE
 	  and phyCARD boards in AC97 mode
@@ -65,6 +71,7 @@ config SND_SOC_EUKREA_TLV320
 	select SND_SOC_TLV320AIC23
 	select SND_MXC_SOC_FIQ
 	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
 	help
 	  Enable I2S based access to the TLV320AIC23B codec attached
 	  to the SSI interface
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
index e9ed362..f5db3e9 100644
--- a/sound/soc/imx/Makefile
+++ b/sound/soc/imx/Makefile
@@ -1,8 +1,8 @@
 # i.MX Platform Support
-snd-soc-imx-objs := imx-ssi.o
+snd-soc-imx-ssi-objs := imx-ssi.o
 snd-soc-imx-audmux-objs := imx-audmux.o
 
-obj-$(CONFIG_SND_IMX_SOC) += snd-soc-imx.o
+obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
 obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
 
 obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:30:57 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:57 +0800
Subject: [PATCH v2 09/17] ASoC: fsl: separate SSI and DMA Kconfig options
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-10-git-send-email-shawn.guo@linaro.org>

The fsl_ssi driver will possibly be shared between Freescale PowerPC
and ARM/IMX families, so give it a separate Kconfig option.  Then
fsl_ssi driver can possibly be selected independently from selecting
PowerPC DMA based PCM driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/Kconfig  |   15 +++++++++------
 sound/soc/fsl/Makefile |    3 ++-
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index d754d34..ca693b2 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,10 +1,11 @@
 config SND_MPC52xx_DMA
 	tristate
 
-# ASoC platform support for the Freescale PowerPC SOCs that have an SSI and
-# an Elo DMA controller, such as the MPC8610 and P1022.  You will still need to
-# select a platform driver and a codec driver.
-config SND_SOC_POWERPC_SSI
+config SND_SOC_FSL_SSI
+	tristate
+	depends on FSL_SOC
+
+config SND_SOC_POWERPC_DMA
 	tristate
 	depends on FSL_SOC
 
@@ -12,7 +13,8 @@ config SND_SOC_MPC8610_HPCD
 	tristate "ALSA SoC support for the Freescale MPC8610 HPCD board"
 	# I2C is necessary for the CS4270 driver
 	depends on MPC8610_HPCD && I2C
-	select SND_SOC_POWERPC_SSI
+	select SND_SOC_FSL_SSI
+	select SND_SOC_POWERPC_DMA
 	select SND_SOC_CS4270
 	select SND_SOC_CS4270_VD33_ERRATA
 	default y if MPC8610_HPCD
@@ -23,7 +25,8 @@ config SND_SOC_P1022_DS
 	tristate "ALSA SoC support for the Freescale P1022 DS board"
 	# I2C is necessary for the WM8776 driver
 	depends on P1022_DS && I2C
-	select SND_SOC_POWERPC_SSI
+	select SND_SOC_FSL_SSI
+	select SND_SOC_POWERPC_DMA
 	select SND_SOC_WM8776
 	default y if P1022_DS
 	help
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index b4a38c0..95d483f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -9,7 +9,8 @@ obj-$(CONFIG_SND_SOC_P1022_DS) += snd-soc-p1022-ds.o
 # Freescale PowerPC SSI/DMA Platform Support
 snd-soc-fsl-ssi-objs := fsl_ssi.o
 snd-soc-fsl-dma-objs := fsl_dma.o
-obj-$(CONFIG_SND_SOC_POWERPC_SSI) += snd-soc-fsl-ssi.o snd-soc-fsl-dma.o
+obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 
 # MPC5200 Platform Support
 obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:30:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:58 +0800
Subject: [PATCH v2 10/17] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-11-git-send-email-shawn.guo@linaro.org>

Freescale PowerPC and ARM/IMX families share the same SSI IP block.
The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
code sharing and consolidation can happen.

This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
IMX platform.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/Kconfig                        |    1 -
 sound/soc/Makefile                       |    1 -
 sound/soc/fsl/Kconfig                    |   92 ++++++++++++++++++++++++++++++
 sound/soc/fsl/Makefile                   |   22 +++++++
 sound/soc/{imx => fsl}/eukrea-tlv320.c   |    2 +-
 sound/soc/{imx => fsl}/imx-audmux.c      |    0
 sound/soc/{imx => fsl}/imx-audmux.h      |    0
 sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c |    0
 sound/soc/{imx => fsl}/imx-pcm-fiq.c     |    0
 sound/soc/{imx => fsl}/imx-pcm.c         |    0
 sound/soc/{imx => fsl}/imx-pcm.h         |    0
 sound/soc/{imx => fsl}/imx-ssi.c         |    2 +-
 sound/soc/{imx => fsl}/imx-ssi.h         |    0
 sound/soc/{imx => fsl}/mx27vis-aic32x4.c |    0
 sound/soc/{imx => fsl}/phycore-ac97.c    |    0
 sound/soc/{imx => fsl}/wm1133-ev1.c      |    0
 sound/soc/imx/Kconfig                    |   79 -------------------------
 sound/soc/imx/Makefile                   |   22 -------
 18 files changed, 116 insertions(+), 105 deletions(-)
 rename sound/soc/{imx => fsl}/eukrea-tlv320.c (99%)
 rename sound/soc/{imx => fsl}/imx-audmux.c (100%)
 rename sound/soc/{imx => fsl}/imx-audmux.h (100%)
 rename sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm-fiq.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm.h (100%)
 rename sound/soc/{imx => fsl}/imx-ssi.c (99%)
 rename sound/soc/{imx => fsl}/imx-ssi.h (100%)
 rename sound/soc/{imx => fsl}/mx27vis-aic32x4.c (100%)
 rename sound/soc/{imx => fsl}/phycore-ac97.c (100%)
 rename sound/soc/{imx => fsl}/wm1133-ev1.c (100%)
 delete mode 100644 sound/soc/imx/Kconfig
 delete mode 100644 sound/soc/imx/Makefile

diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 91c9855..0f85f6d 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -35,7 +35,6 @@ source "sound/soc/blackfin/Kconfig"
 source "sound/soc/davinci/Kconfig"
 source "sound/soc/ep93xx/Kconfig"
 source "sound/soc/fsl/Kconfig"
-source "sound/soc/imx/Kconfig"
 source "sound/soc/jz4740/Kconfig"
 source "sound/soc/nuc900/Kconfig"
 source "sound/soc/omap/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 2feaf37..363dfd6 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_SND_SOC)	+= blackfin/
 obj-$(CONFIG_SND_SOC)	+= davinci/
 obj-$(CONFIG_SND_SOC)	+= ep93xx/
 obj-$(CONFIG_SND_SOC)	+= fsl/
-obj-$(CONFIG_SND_SOC)   += imx/
 obj-$(CONFIG_SND_SOC)	+= jz4740/
 obj-$(CONFIG_SND_SOC)	+= mid-x86/
 obj-$(CONFIG_SND_SOC)	+= mxs/
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index ca693b2..19856a0 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,3 +1,15 @@
+config SND_SOC_FSL_SSI
+	tristate
+
+menuconfig SND_POWERPC_SOC
+	tristate "SoC Audio for Freescale PowerPC CPUs"
+	depends on FSL_SOC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the PowerPC CPUs.
+
+if SND_POWERPC_SOC
+
 config SND_MPC52xx_DMA
 	tristate
 
@@ -68,3 +80,83 @@ config SND_MPC52xx_SOC_EFIKA
 	help
 	  Say Y if you want to add support for sound on the Efika.
 
+endif # SND_POWERPC_SOC
+
+menuconfig SND_IMX_SOC
+	tristate "SoC Audio for Freescale i.MX CPUs"
+	depends on ARCH_MXC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the i.MX CPUs.
+
+if SND_IMX_SOC
+
+config SND_SOC_IMX_SSI
+	tristate
+
+config SND_SOC_IMX_PCM
+	tristate
+
+config SND_MXC_SOC_FIQ
+	tristate
+	select FIQ
+	select SND_SOC_IMX_PCM
+
+config SND_MXC_SOC_MX2
+	tristate
+	select SND_SOC_DMAENGINE_PCM
+	select SND_SOC_IMX_PCM
+
+config SND_SOC_IMX_AUDMUX
+	tristate
+
+config SND_MXC_SOC_WM1133_EV1
+	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
+	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
+	select SND_SOC_WM8350
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
+	  PMIC board with WM8835x fitted.
+
+config SND_SOC_MX27VIS_AIC32X4
+	tristate "SoC audio support for Visstrim M10 boards"
+	depends on MACH_IMX27_VISSTRIM_M10 && I2C
+	select SND_SOC_TLV320AIC32X4
+	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Say Y if you want to add support for SoC audio on Visstrim SM10
+	  board with TLV320AIC32X4 codec.
+
+config SND_SOC_PHYCORE_AC97
+	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
+	depends on MACH_PCM043 || MACH_PCA100
+	select SND_SOC_AC97_BUS
+	select SND_SOC_WM9712
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Say Y if you want to add support for SoC audio on Phytec phyCORE
+	  and phyCARD boards in AC97 mode
+
+config SND_SOC_EUKREA_TLV320
+	tristate "Eukrea TLV320"
+	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
+	depends on I2C
+	select SND_SOC_TLV320AIC23
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Enable I2S based access to the TLV320AIC23B codec attached
+	  to the SSI interface
+
+endif # SND_IMX_SOC
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 95d483f..36c257f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -21,3 +21,25 @@ obj-$(CONFIG_SND_SOC_MPC5200_AC97) += mpc5200_psc_ac97.o
 obj-$(CONFIG_SND_MPC52xx_SOC_PCM030) += pcm030-audio-fabric.o
 obj-$(CONFIG_SND_MPC52xx_SOC_EFIKA) += efika-audio-fabric.o
 
+# i.MX Platform Support
+snd-soc-imx-ssi-objs := imx-ssi.o
+snd-soc-imx-audmux-objs := imx-audmux.o
+
+obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
+obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
+
+obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
+snd-soc-imx-pcm-y := imx-pcm.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
+
+# i.MX Machine Support
+snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
+snd-soc-phycore-ac97-objs := phycore-ac97.o
+snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
+snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+
+obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
+obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
+obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
+obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/fsl/eukrea-tlv320.c
similarity index 99%
rename from sound/soc/imx/eukrea-tlv320.c
rename to sound/soc/fsl/eukrea-tlv320.c
index 7d4475c..efb9ede 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/fsl/eukrea-tlv320.c
@@ -7,7 +7,7 @@
  * which is Copyright 2009 Simtec Electronics
  * and on sound/soc/imx/phycore-ac97.c which is
  * Copyright 2009 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
- * 
+ *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
  *  Free Software Foundation;  either version 2 of the  License, or (at your
diff --git a/sound/soc/imx/imx-audmux.c b/sound/soc/fsl/imx-audmux.c
similarity index 100%
rename from sound/soc/imx/imx-audmux.c
rename to sound/soc/fsl/imx-audmux.c
diff --git a/sound/soc/imx/imx-audmux.h b/sound/soc/fsl/imx-audmux.h
similarity index 100%
rename from sound/soc/imx/imx-audmux.h
rename to sound/soc/fsl/imx-audmux.h
diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/fsl/imx-pcm-dma-mx2.c
similarity index 100%
rename from sound/soc/imx/imx-pcm-dma-mx2.c
rename to sound/soc/fsl/imx-pcm-dma-mx2.c
diff --git a/sound/soc/imx/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
similarity index 100%
rename from sound/soc/imx/imx-pcm-fiq.c
rename to sound/soc/fsl/imx-pcm-fiq.c
diff --git a/sound/soc/imx/imx-pcm.c b/sound/soc/fsl/imx-pcm.c
similarity index 100%
rename from sound/soc/imx/imx-pcm.c
rename to sound/soc/fsl/imx-pcm.c
diff --git a/sound/soc/imx/imx-pcm.h b/sound/soc/fsl/imx-pcm.h
similarity index 100%
rename from sound/soc/imx/imx-pcm.h
rename to sound/soc/fsl/imx-pcm.h
diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
similarity index 99%
rename from sound/soc/imx/imx-ssi.c
rename to sound/soc/fsl/imx-ssi.c
index 4f81ed4..cf3ed03 100644
--- a/sound/soc/imx/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -28,7 +28,7 @@
  * value. When we read the same register two times (and the register still
  * contains the same value) these status bits are not set. We work
  * around this by not polling these bits but only wait a fixed delay.
- * 
+ *
  */
 
 #include <linux/clk.h>
diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/fsl/imx-ssi.h
similarity index 100%
rename from sound/soc/imx/imx-ssi.h
rename to sound/soc/fsl/imx-ssi.h
diff --git a/sound/soc/imx/mx27vis-aic32x4.c b/sound/soc/fsl/mx27vis-aic32x4.c
similarity index 100%
rename from sound/soc/imx/mx27vis-aic32x4.c
rename to sound/soc/fsl/mx27vis-aic32x4.c
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/fsl/phycore-ac97.c
similarity index 100%
rename from sound/soc/imx/phycore-ac97.c
rename to sound/soc/fsl/phycore-ac97.c
diff --git a/sound/soc/imx/wm1133-ev1.c b/sound/soc/fsl/wm1133-ev1.c
similarity index 100%
rename from sound/soc/imx/wm1133-ev1.c
rename to sound/soc/fsl/wm1133-ev1.c
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
deleted file mode 100644
index 810acaa..0000000
--- a/sound/soc/imx/Kconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-menuconfig SND_IMX_SOC
-	tristate "SoC Audio for Freescale i.MX CPUs"
-	depends on ARCH_MXC
-	help
-	  Say Y or M if you want to add support for codecs attached to
-	  the i.MX SSI interface.
-
-
-if SND_IMX_SOC
-
-config SND_SOC_IMX_SSI
-	tristate
-
-config SND_SOC_IMX_PCM
-	tristate
-
-config SND_MXC_SOC_FIQ
-	tristate
-	select FIQ
-	select SND_SOC_IMX_PCM
-
-config SND_MXC_SOC_MX2
-	select SND_SOC_DMAENGINE_PCM
-	tristate
-	select SND_SOC_IMX_PCM
-
-config SND_SOC_IMX_AUDMUX
-	tristate
-
-config SND_MXC_SOC_WM1133_EV1
-	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
-	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
-	select SND_SOC_WM8350
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
-	  PMIC board with WM8835x fitted.
-
-config SND_SOC_MX27VIS_AIC32X4
-	tristate "SoC audio support for Visstrim M10 boards"
-	depends on MACH_IMX27_VISSTRIM_M10 && I2C
-	select SND_SOC_TLV320AIC32X4
-	select SND_MXC_SOC_MX2
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Say Y if you want to add support for SoC audio on Visstrim SM10
-	  board with TLV320AIC32X4 codec.
-
-config SND_SOC_PHYCORE_AC97
-	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
-	depends on MACH_PCM043 || MACH_PCA100
-	select SND_SOC_AC97_BUS
-	select SND_SOC_WM9712
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Say Y if you want to add support for SoC audio on Phytec phyCORE
-	  and phyCARD boards in AC97 mode
-
-config SND_SOC_EUKREA_TLV320
-	tristate "Eukrea TLV320"
-	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
-	depends on I2C
-	select SND_SOC_TLV320AIC23
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Enable I2S based access to the TLV320AIC23B codec attached
-	  to the SSI interface
-
-endif	# SND_IMX_SOC
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
deleted file mode 100644
index f5db3e9..0000000
--- a/sound/soc/imx/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-# i.MX Platform Support
-snd-soc-imx-ssi-objs := imx-ssi.o
-snd-soc-imx-audmux-objs := imx-audmux.o
-
-obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
-obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
-
-obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
-snd-soc-imx-pcm-y := imx-pcm.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
-
-# i.MX Machine Support
-snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
-snd-soc-phycore-ac97-objs := phycore-ac97.o
-snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
-snd-soc-wm1133-ev1-objs := wm1133-ev1.o
-
-obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
-obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
-obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
-obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:30:59 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:30:59 +0800
Subject: [PATCH v2 11/17] ASoC: fsl: create fsl_utils to accommodate the
 common functions
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-12-git-send-email-shawn.guo@linaro.org>

There is some amount of code duplication between mpc8610_hpcd and
p1022_ds machine drivers, and the same code will be duplicated again
when another new machine driver is added.  The patch creates fsl_utils
to accommodate the common functions to stop the code duplication.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/Kconfig        |    5 ++
 sound/soc/fsl/Makefile       |    2 +
 sound/soc/fsl/fsl_utils.c    |  135 ++++++++++++++++++++++++++++++++++++
 sound/soc/fsl/fsl_utils.h    |   27 +++++++
 sound/soc/fsl/mpc8610_hpcd.c |  157 +++---------------------------------------
 sound/soc/fsl/p1022_ds.c     |  149 +++-------------------------------------
 6 files changed, 189 insertions(+), 286 deletions(-)
 create mode 100644 sound/soc/fsl/fsl_utils.c
 create mode 100644 sound/soc/fsl/fsl_utils.h

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 19856a0..e579671 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,6 +1,9 @@
 config SND_SOC_FSL_SSI
 	tristate
 
+config SND_SOC_FSL_UTILS
+	tristate
+
 menuconfig SND_POWERPC_SOC
 	tristate "SoC Audio for Freescale PowerPC CPUs"
 	depends on FSL_SOC
@@ -26,6 +29,7 @@ config SND_SOC_MPC8610_HPCD
 	# I2C is necessary for the CS4270 driver
 	depends on MPC8610_HPCD && I2C
 	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
 	select SND_SOC_POWERPC_DMA
 	select SND_SOC_CS4270
 	select SND_SOC_CS4270_VD33_ERRATA
@@ -38,6 +42,7 @@ config SND_SOC_P1022_DS
 	# I2C is necessary for the WM8776 driver
 	depends on P1022_DS && I2C
 	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
 	select SND_SOC_POWERPC_DMA
 	select SND_SOC_WM8776
 	default y if P1022_DS
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 36c257f..02b3e53 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -8,8 +8,10 @@ obj-$(CONFIG_SND_SOC_P1022_DS) += snd-soc-p1022-ds.o
 
 # Freescale PowerPC SSI/DMA Platform Support
 snd-soc-fsl-ssi-objs := fsl_ssi.o
+snd-soc-fsl-utils-objs := fsl_utils.o
 snd-soc-fsl-dma-objs := fsl_dma.o
 obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
 obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 
 # MPC5200 Platform Support
diff --git a/sound/soc/fsl/fsl_utils.c b/sound/soc/fsl/fsl_utils.c
new file mode 100644
index 0000000..4370c28
--- /dev/null
+++ b/sound/soc/fsl/fsl_utils.c
@@ -0,0 +1,135 @@
+/**
+ * Freescale ALSA SoC Machine driver utility
+ *
+ * Author: Timur Tabi <timur at freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_i2c.h>
+#include <sound/soc.h>
+
+#include "fsl_utils.h"
+
+/**
+ * fsl_asoc_get_codec_dev_name - determine the dev_name for a codec node
+ *
+ * @np: pointer to the I2C device tree node
+ * @buf: buffer to be filled with the dev_name of the I2C device
+ * @len: the length of the buffer
+ *
+ * This function determines the dev_name for an I2C node.  This is the name
+ * that would be returned by dev_name() if this device_node were part of a
+ * 'struct device'  It's ugly and hackish, but it works.
+ *
+ * The dev_name for such devices include the bus number and I2C address. For
+ * example, "cs4270.0-004f".
+ */
+int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len)
+{
+	const u32 *iprop;
+	u32 addr;
+	char temp[DAI_NAME_SIZE];
+	struct i2c_client *i2c;
+
+	of_modalias_node(np, temp, DAI_NAME_SIZE);
+
+	iprop = of_get_property(np, "reg", NULL);
+	if (!iprop)
+		return -EINVAL;
+
+	addr = be32_to_cpup(iprop);
+
+	/* We need the adapter number */
+	i2c = of_find_i2c_device_by_node(np);
+	if (!i2c) {
+		put_device(&i2c->dev);
+		return -ENODEV;
+	}
+
+	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
+	put_device(&i2c->dev);
+
+	return 0;
+}
+EXPORT_SYMBOL(fsl_asoc_get_codec_dev_name);
+
+/**
+ * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
+ *
+ * @ssi_np: pointer to the SSI device tree node
+ * @name: name of the phandle pointing to the dma channel
+ * @dai: ASoC DAI link pointer to be filled with platform_name
+ * @dma_channel_id: dma channel id to be returned
+ * @dma_id: dma id to be returned
+ *
+ * This function determines the dma and channel id for given SSI node.  It
+ * also discovers the platform_name for the ASoC DAI link.
+ */
+int fsl_asoc_get_dma_channel(struct device_node *ssi_np,
+			     const char *name,
+			     struct snd_soc_dai_link *dai,
+			     unsigned int *dma_channel_id,
+			     unsigned int *dma_id)
+{
+	struct resource res;
+	struct device_node *dma_channel_np, *dma_np;
+	const u32 *iprop;
+	int ret;
+
+	dma_channel_np = of_parse_phandle(ssi_np, name, 0);
+	if (!dma_channel_np)
+		return -EINVAL;
+
+	if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) {
+		of_node_put(dma_channel_np);
+		return -EINVAL;
+	}
+
+	/* Determine the dev_name for the device_node.  This code mimics the
+	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
+	 * the dev_name() of the device to match the platform (DMA) device with
+	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
+	 * now).
+	 *
+	 * dai->platform name should already point to an allocated buffer.
+	 */
+	ret = of_address_to_resource(dma_channel_np, 0, &res);
+	if (ret) {
+		of_node_put(dma_channel_np);
+		return ret;
+	}
+	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
+		 (unsigned long long) res.start, dma_channel_np->name);
+
+	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
+	if (!iprop) {
+		of_node_put(dma_channel_np);
+		return -EINVAL;
+	}
+	*dma_channel_id = be32_to_cpup(iprop);
+
+	dma_np = of_get_parent(dma_channel_np);
+	iprop = of_get_property(dma_np, "cell-index", NULL);
+	if (!iprop) {
+		of_node_put(dma_np);
+		return -EINVAL;
+	}
+	*dma_id = be32_to_cpup(iprop);
+
+	of_node_put(dma_np);
+	of_node_put(dma_channel_np);
+
+	return 0;
+}
+EXPORT_SYMBOL(fsl_asoc_get_dma_channel);
+
+MODULE_AUTHOR("Timur Tabi <timur at freescale.com>");
+MODULE_DESCRIPTION("Freescale ASoC utility code");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/fsl/fsl_utils.h b/sound/soc/fsl/fsl_utils.h
new file mode 100644
index 0000000..44d1436
--- /dev/null
+++ b/sound/soc/fsl/fsl_utils.h
@@ -0,0 +1,27 @@
+/**
+ * Freescale ALSA SoC Machine driver utility
+ *
+ * Author: Timur Tabi <timur at freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef _FSL_UTILS_H
+#define _FSL_UTILS_H
+
+#define DAI_NAME_SIZE	32
+
+struct snd_soc_dai_link;
+struct device_node;
+
+int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len);
+int fsl_asoc_get_dma_channel(struct device_node *ssi_np, const char *name,
+			     struct snd_soc_dai_link *dai,
+			     unsigned int *dma_channel_id,
+			     unsigned int *dma_id);
+
+#endif /* _FSL_UTILS_H */
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index fcf9302..7ead1e5 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -14,18 +14,16 @@
 #include <linux/interrupt.h>
 #include <linux/of_device.h>
 #include <linux/slab.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 #include <asm/fsl_guts.h>
 
 #include "fsl_dma.h"
 #include "fsl_ssi.h"
+#include "fsl_utils.h"
 
 /* There's only one global utilities register */
 static phys_addr_t guts_phys;
 
-#define DAI_NAME_SIZE	32
-
 /**
  * mpc8610_hpcd_data: machine-specific ASoC device data
  *
@@ -181,141 +179,6 @@ static struct snd_soc_ops mpc8610_hpcd_ops = {
 };
 
 /**
- * get_node_by_phandle_name - get a node by its phandle name
- *
- * This function takes a node, the name of a property in that node, and a
- * compatible string.  Assuming the property is a phandle to another node,
- * it returns that node, (optionally) if that node is compatible.
- *
- * If the property is not a phandle, or the node it points to is not compatible
- * with the specific string, then NULL is returned.
- */
-static struct device_node *get_node_by_phandle_name(struct device_node *np,
-					       const char *name,
-					       const char *compatible)
-{
-	const phandle *ph;
-	int len;
-
-	ph = of_get_property(np, name, &len);
-	if (!ph || (len != sizeof(phandle)))
-		return NULL;
-
-	np = of_find_node_by_phandle(*ph);
-	if (!np)
-		return NULL;
-
-	if (compatible && !of_device_is_compatible(np, compatible)) {
-		of_node_put(np);
-		return NULL;
-	}
-
-	return np;
-}
-
-/**
- * get_parent_cell_index -- return the cell-index of the parent of a node
- *
- * Return the value of the cell-index property of the parent of the given
- * node.  This is used for DMA channel nodes that need to know the DMA ID
- * of the controller they are on.
- */
-static int get_parent_cell_index(struct device_node *np)
-{
-	struct device_node *parent = of_get_parent(np);
-	const u32 *iprop;
-
-	if (!parent)
-		return -1;
-
-	iprop = of_get_property(parent, "cell-index", NULL);
-	of_node_put(parent);
-
-	if (!iprop)
-		return -1;
-
-	return be32_to_cpup(iprop);
-}
-
-/**
- * codec_node_dev_name - determine the dev_name for a codec node
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270.0-004f".
- */
-static int codec_node_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	int addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c)
-		return -ENODEV;
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-
-	return 0;
-}
-
-static int get_dma_channel(struct device_node *ssi_np,
-			   const char *name,
-			   struct snd_soc_dai_link *dai,
-			   unsigned int *dma_channel_id,
-			   unsigned int *dma_id)
-{
-	struct resource res;
-	struct device_node *dma_channel_np;
-	const u32 *iprop;
-	int ret;
-
-	dma_channel_np = get_node_by_phandle_name(ssi_np, name,
-						  "fsl,ssi-dma-channel");
-	if (!dma_channel_np)
-		return -EINVAL;
-
-	/* Determine the dev_name for the device_node.  This code mimics the
-	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
-	 * the dev_name() of the device to match the platform (DMA) device with
-	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
-	 * now).
-	 *
-	 * dai->platform name should already point to an allocated buffer.
-	 */
-	ret = of_address_to_resource(dma_channel_np, 0, &res);
-	if (ret)
-		return ret;
-	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
-		 (unsigned long long) res.start, dma_channel_np->name);
-
-	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
-	if (!iprop) {
-		of_node_put(dma_channel_np);
-		return -EINVAL;
-	}
-
-	*dma_channel_id = be32_to_cpup(iprop);
-	*dma_id = get_parent_cell_index(dma_channel_np);
-	of_node_put(dma_channel_np);
-
-	return 0;
-}
-
-/**
  * mpc8610_hpcd_probe: platform probe function for the machine driver
  *
  * Although this is a machine driver, the SSI node is the "master" node with
@@ -353,8 +216,8 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 	machine_data->dai[0].ops = &mpc8610_hpcd_ops;
 
 	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = codec_node_dev_name(codec_np, machine_data->codec_name,
-				  DAI_NAME_SIZE);
+	ret = fsl_asoc_get_codec_dev_name(codec_np, machine_data->codec_name,
+					  DAI_NAME_SIZE);
 	if (ret) {
 		dev_err(&pdev->dev, "invalid codec node %s\n",
 			codec_np->full_name);
@@ -458,9 +321,10 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 
 	/* Find the playback DMA channel to use. */
 	machine_data->dai[0].platform_name = machine_data->platform_name[0];
-	ret = get_dma_channel(np, "fsl,playback-dma", &machine_data->dai[0],
-			      &machine_data->dma_channel_id[0],
-			      &machine_data->dma_id[0]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma",
+				       &machine_data->dai[0],
+				       &machine_data->dma_channel_id[0],
+				       &machine_data->dma_id[0]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
 		goto error;
@@ -468,9 +332,10 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 
 	/* Find the capture DMA channel to use. */
 	machine_data->dai[1].platform_name = machine_data->platform_name[1];
-	ret = get_dma_channel(np, "fsl,capture-dma", &machine_data->dai[1],
-			      &machine_data->dma_channel_id[1],
-			      &machine_data->dma_id[1]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma",
+				       &machine_data->dai[1],
+				       &machine_data->dma_channel_id[1],
+				       &machine_data->dma_id[1]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
 		goto error;
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index d32ec46..60f7bb8 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -14,12 +14,12 @@
 #include <linux/interrupt.h>
 #include <linux/of_device.h>
 #include <linux/slab.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 #include <asm/fsl_guts.h>
 
 #include "fsl_dma.h"
 #include "fsl_ssi.h"
+#include "fsl_utils.h"
 
 /* P1022-specific PMUXCR and DMUXCR bit definitions */
 
@@ -57,8 +57,6 @@ static inline void guts_set_dmuxcr(struct ccsr_guts_85xx __iomem *guts,
 /* There's only one global utilities register */
 static phys_addr_t guts_phys;
 
-#define DAI_NAME_SIZE	32
-
 /**
  * machine_data: machine-specific ASoC device data
  *
@@ -191,136 +189,6 @@ static struct snd_soc_ops p1022_ds_ops = {
 };
 
 /**
- * get_node_by_phandle_name - get a node by its phandle name
- *
- * This function takes a node, the name of a property in that node, and a
- * compatible string.  Assuming the property is a phandle to another node,
- * it returns that node, (optionally) if that node is compatible.
- *
- * If the property is not a phandle, or the node it points to is not compatible
- * with the specific string, then NULL is returned.
- */
-static struct device_node *get_node_by_phandle_name(struct device_node *np,
-	const char *name, const char *compatible)
-{
-	np = of_parse_phandle(np, name, 0);
-	if (!np)
-		return NULL;
-
-	if (!of_device_is_compatible(np, compatible)) {
-		of_node_put(np);
-		return NULL;
-	}
-
-	return np;
-}
-
-/**
- * get_parent_cell_index -- return the cell-index of the parent of a node
- *
- * Return the value of the cell-index property of the parent of the given
- * node.  This is used for DMA channel nodes that need to know the DMA ID
- * of the controller they are on.
- */
-static int get_parent_cell_index(struct device_node *np)
-{
-	struct device_node *parent = of_get_parent(np);
-	const u32 *iprop;
-	int ret = -1;
-
-	if (!parent)
-		return -1;
-
-	iprop = of_get_property(parent, "cell-index", NULL);
-	if (iprop)
-		ret = be32_to_cpup(iprop);
-
-	of_node_put(parent);
-
-	return ret;
-}
-
-/**
- * codec_node_dev_name - determine the dev_name for a codec node
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270-codec.0-004f".
- */
-static int codec_node_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	int addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c)
-		return -ENODEV;
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-
-	return 0;
-}
-
-static int get_dma_channel(struct device_node *ssi_np,
-			   const char *name,
-			   struct snd_soc_dai_link *dai,
-			   unsigned int *dma_channel_id,
-			   unsigned int *dma_id)
-{
-	struct resource res;
-	struct device_node *dma_channel_np;
-	const u32 *iprop;
-	int ret;
-
-	dma_channel_np = get_node_by_phandle_name(ssi_np, name,
-						  "fsl,ssi-dma-channel");
-	if (!dma_channel_np)
-		return -EINVAL;
-
-	/* Determine the dev_name for the device_node.  This code mimics the
-	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
-	 * the dev_name() of the device to match the platform (DMA) device with
-	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
-	 * now).
-	 *
-	 * dai->platform name should already point to an allocated buffer.
-	 */
-	ret = of_address_to_resource(dma_channel_np, 0, &res);
-	if (ret) {
-		of_node_put(dma_channel_np);
-		return ret;
-	}
-	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
-		 (unsigned long long) res.start, dma_channel_np->name);
-
-	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
-	if (!iprop) {
-		of_node_put(dma_channel_np);
-		return -EINVAL;
-	}
-
-	*dma_channel_id = be32_to_cpup(iprop);
-	*dma_id = get_parent_cell_index(dma_channel_np);
-	of_node_put(dma_channel_np);
-
-	return 0;
-}
-
-/**
  * p1022_ds_probe: platform probe function for the machine driver
  *
  * Although this is a machine driver, the SSI node is the "master" node with
@@ -358,7 +226,8 @@ static int p1022_ds_probe(struct platform_device *pdev)
 	mdata->dai[0].ops = &p1022_ds_ops;
 
 	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = codec_node_dev_name(codec_np, mdata->codec_name, DAI_NAME_SIZE);
+	ret = fsl_asoc_get_codec_dev_name(codec_np, mdata->codec_name,
+					  DAI_NAME_SIZE);
 	if (ret) {
 		dev_err(&pdev->dev, "invalid codec node %s\n",
 			codec_np->full_name);
@@ -454,9 +323,9 @@ static int p1022_ds_probe(struct platform_device *pdev)
 
 	/* Find the playback DMA channel to use. */
 	mdata->dai[0].platform_name = mdata->platform_name[0];
-	ret = get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
-			      &mdata->dma_channel_id[0],
-			      &mdata->dma_id[0]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
+				       &mdata->dma_channel_id[0],
+				       &mdata->dma_id[0]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
 		goto error;
@@ -464,9 +333,9 @@ static int p1022_ds_probe(struct platform_device *pdev)
 
 	/* Find the capture DMA channel to use. */
 	mdata->dai[1].platform_name = mdata->platform_name[1];
-	ret = get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
-			      &mdata->dma_channel_id[1],
-			      &mdata->dma_id[1]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
+				       &mdata->dma_channel_id[1],
+				       &mdata->dma_id[1]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
 		goto error;
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:31:00 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:31:00 +0800
Subject: [PATCH v2 12/17] ASoC: fsl: check property 'compatible' for the
 machine name
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-13-git-send-email-shawn.guo@linaro.org>

Check /compatible rather than /model to determine the machine name.
The p1022ds older device trees get a different /model from the new
ones, while /compatible is consistent there, so checking /compatible
will save the bother of detecting older p1022ds device trees.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c      |    6 +++---
 sound/soc/fsl/mpc8610_hpcd.c |    2 +-
 sound/soc/fsl/p1022_ds.c     |   32 +++++---------------------------
 3 files changed, 9 insertions(+), 31 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 3e06696..2eb407f 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -716,12 +716,12 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 	}
 
 	/* Trigger the machine driver's probe function.  The platform driver
-	 * name of the machine driver is taken from the /model property of the
+	 * name of the machine driver is taken from /compatible property of the
 	 * device tree.  We also pass the address of the CPU DAI driver
 	 * structure.
 	 */
-	sprop = of_get_property(of_find_node_by_path("/"), "model", NULL);
-	/* Sometimes the model name has a "fsl," prefix, so we strip that. */
+	sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
+	/* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
 	p = strrchr(sprop, ',');
 	if (p)
 		sprop = p + 1;
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index 7ead1e5..4195182 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -411,7 +411,7 @@ static struct platform_driver mpc8610_hpcd_driver = {
 	.probe = mpc8610_hpcd_probe,
 	.remove = __devexit_p(mpc8610_hpcd_remove),
 	.driver = {
-		/* The name must match the 'model' property in the device tree,
+		/* The name must match 'compatible' property in the device tree,
 		 * in lowercase letters.
 		 */
 		.name = "snd-soc-mpc8610hpcd",
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index 60f7bb8..e3680ce 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -412,6 +412,11 @@ static struct platform_driver p1022_ds_driver = {
 	.probe = p1022_ds_probe,
 	.remove = __devexit_p(p1022_ds_remove),
 	.driver = {
+		/*
+		 * The name must match 'compatible' property in the device tree,
+		 * in lowercase letters.
+		 */
+		.name = "snd-soc-p1022ds",
 		.owner = THIS_MODULE,
 	},
 };
@@ -425,33 +430,6 @@ static int __init p1022_ds_init(void)
 {
 	struct device_node *guts_np;
 	struct resource res;
-	const char *sprop;
-
-	/*
-	 * Check if we're actually running on a P1022DS.  Older device trees
-	 * have a model of "fsl,P1022" and newer ones use "fsl,P1022DS", so we
-	 * need to support both.  The SSI driver uses that property to link to
-	 * the machine driver, so have to match it.
-	 */
-	sprop = of_get_property(of_find_node_by_path("/"), "model", NULL);
-	if (!sprop) {
-		pr_err("snd-soc-p1022ds: missing /model node");
-		return -ENODEV;
-	}
-
-	pr_debug("snd-soc-p1022ds: board model name is %s\n", sprop);
-
-	/*
-	 * The name of this board, taken from the device tree.  Normally, this is a*
-	 * fixed string, but some P1022DS device trees have a /model property of
-	 * "fsl,P1022", and others have "fsl,P1022DS".
-	 */
-	if (strcasecmp(sprop, "fsl,p1022ds") == 0)
-		p1022_ds_driver.driver.name = "snd-soc-p1022ds";
-	else if (strcasecmp(sprop, "fsl,p1022") == 0)
-		p1022_ds_driver.driver.name = "snd-soc-p1022";
-	else
-		return -ENODEV;
 
 	/* Get the physical address of the global utilities registers */
 	guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:31:01 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:31:01 +0800
Subject: [PATCH v2 13/17] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-14-git-send-email-shawn.guo@linaro.org>

Provide different pair of accessors for accessing SSI registers on
PowerPC and ARM/IMX, so that fsl_ssi driver can be built on both
architectures.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |   60 +++++++++++++++++++++++++++++-----------------
 1 files changed, 38 insertions(+), 22 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 2eb407f..d31d1ba 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -11,11 +11,14 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 
 #include <sound/core.h>
@@ -26,6 +29,21 @@
 
 #include "fsl_ssi.h"
 
+#ifdef PPC
+#define read_ssi(addr)			 in_be32(addr)
+#define write_ssi(val, addr)		 out_be32(addr, val)
+#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
+#elif defined ARM
+#define read_ssi(addr)			 readl(addr)
+#define write_ssi(val, addr)		 writel(val, addr)
+static inline void write_ssi_mask(void __iomem *addr, u32 clear, u32 set)
+{
+	u32 val = readl(addr);
+	val = (val & ~clear) | set;
+	writel(val, addr);
+}
+#endif
+
 /**
  * FSLSSI_I2S_RATES: sample rates supported by the I2S
  *
@@ -145,7 +163,7 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 	   were interrupted for.  We mask it with the Interrupt Enable register
 	   so that we only check for events that we're interested in.
 	 */
-	sisr = in_be32(&ssi->sisr) & SIER_FLAGS;
+	sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
 
 	if (sisr & CCSR_SSI_SISR_RFRC) {
 		ssi_private->stats.rfrc++;
@@ -260,7 +278,7 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 
 	/* Clear the bits that we set */
 	if (sisr2)
-		out_be32(&ssi->sisr, sisr2);
+		write_ssi(sisr2, &ssi->sisr);
 
 	return ret;
 }
@@ -295,7 +313,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 * SSI needs to be disabled before updating the registers we set
 		 * here.
 		 */
-		clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
+		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
 
 		/*
 		 * Program the SSI into I2S Slave Non-Network Synchronous mode.
@@ -303,20 +321,18 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 *
 		 * FIXME: Little-endian samples require a different shift dir
 		 */
-		clrsetbits_be32(&ssi->scr,
+		write_ssi_mask(&ssi->scr,
 			CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
 			CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE
 			| (synchronous ? CCSR_SSI_SCR_SYN : 0));
 
-		out_be32(&ssi->stcr,
-			 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
+		write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
 			 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
-			 CCSR_SSI_STCR_TSCKP);
+			 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
 
-		out_be32(&ssi->srcr,
-			 CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
+		write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
 			 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
-			 CCSR_SSI_SRCR_RSCKP);
+			 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
 
 		/*
 		 * The DC and PM bits are only used if the SSI is the clock
@@ -324,7 +340,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 */
 
 		/* Enable the interrupts and DMA requests */
-		out_be32(&ssi->sier, SIER_FLAGS);
+		write_ssi(SIER_FLAGS, &ssi->sier);
 
 		/*
 		 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
@@ -339,9 +355,9 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 * make this value larger (and maybe we should), but this way
 		 * data will be written to memory as soon as it's available.
 		 */
-		out_be32(&ssi->sfcsr,
-			CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
-			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2));
+		write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
+			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2),
+			&ssi->sfcsr);
 
 		/*
 		 * We keep the SSI disabled because if we enable it, then the
@@ -417,7 +433,7 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 	unsigned int sample_size =
 		snd_pcm_format_width(params_format(hw_params));
 	u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
-	int enabled = in_be32(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
+	int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
 
 	/*
 	 * If we're in synchronous mode, and the SSI is already enabled,
@@ -439,9 +455,9 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 	/* In synchronous mode, the SSI uses STCCR for capture */
 	if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
 	    ssi_private->cpu_dai_drv.symmetric_rates)
-		clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+		write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
 	else
-		clrsetbits_be32(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+		write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
 
 	return 0;
 }
@@ -466,19 +482,19 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-			setbits32(&ssi->scr,
+			write_ssi_mask(&ssi->scr, 0,
 				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
 		else
-			setbits32(&ssi->scr,
+			write_ssi_mask(&ssi->scr, 0,
 				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
 		break;
 
 	case SNDRV_PCM_TRIGGER_STOP:
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-			clrbits32(&ssi->scr, CCSR_SSI_SCR_TE);
+			write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
 		else
-			clrbits32(&ssi->scr, CCSR_SSI_SCR_RE);
+			write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
 		break;
 
 	default:
@@ -510,7 +526,7 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
 	if (!ssi_private->first_stream) {
 		struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 
-		clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
+		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
 	}
 }
 
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:31:02 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:31:02 +0800
Subject: [PATCH v2 14/17] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-15-git-send-email-shawn.guo@linaro.org>

As Documentation/devicetree/bindings/powerpc/fsl/ssi.txt documented,
codec-handle is an optional property, so missing it should not be a
fatal error.

More importantly, the imx machine drivers to be added working with
fsl_ssi will not have this property, as they use new ASoC machine
driver binding mechanism.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index d31d1ba..290728d 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -638,12 +638,6 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 	if (!of_device_is_available(np))
 		return -ENODEV;
 
-	/* Check for a codec-handle property. */
-	if (!of_get_property(np, "codec-handle", NULL)) {
-		dev_err(&pdev->dev, "missing codec-handle property\n");
-		return -ENODEV;
-	}
-
 	/* We only support the SSI in "I2S Slave" mode */
 	sprop = of_get_property(np, "fsl,mode", NULL);
 	if (!sprop || strcmp(sprop, "i2s-slave")) {
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:31:03 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:31:03 +0800
Subject: [PATCH v2 15/17] ASoC: fsl: let fsl_ssi work with imx pcm and machine
 drivers
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-16-git-send-email-shawn.guo@linaro.org>

Makes necessary changes on fsl_ssi to let it work with imx pcm and
machine drivers.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |   69 ++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 68 insertions(+), 1 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 290728d..8c8ca9c 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -28,6 +28,7 @@
 #include <sound/soc.h>
 
 #include "fsl_ssi.h"
+#include "imx-pcm.h"
 
 #ifdef PPC
 #define read_ssi(addr)			 in_be32(addr)
@@ -36,7 +37,7 @@
 #elif defined ARM
 #define read_ssi(addr)			 readl(addr)
 #define write_ssi(val, addr)		 writel(val, addr)
-static inline void write_ssi_mask(void __iomem *addr, u32 clear, u32 set)
+static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
 {
 	u32 val = readl(addr);
 	val = (val & ~clear) | set;
@@ -112,6 +113,11 @@ struct fsl_ssi_private {
 	struct device_attribute dev_attr;
 	struct platform_device *pdev;
 
+	int ssi_on_imx;
+	struct platform_device *imx_pcm_pdev;
+	struct imx_pcm_dma_params dma_params_tx;
+	struct imx_pcm_dma_params dma_params_rx;
+
 	struct {
 		unsigned int rfrc;
 		unsigned int tfrc;
@@ -409,6 +415,12 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		ssi_private->second_stream = substream;
 	}
 
+	if (ssi_private->ssi_on_imx)
+		snd_soc_dai_set_dma_data(dai, substream,
+			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+				&ssi_private->dma_params_tx :
+				&ssi_private->dma_params_rx);
+
 	return 0;
 }
 
@@ -702,6 +714,38 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
                 /* Older 8610 DTs didn't have the fifo-depth property */
 		ssi_private->fifo_depth = 8;
 
+	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx1-ssi")) {
+		u32 dma_events[2];
+		ssi_private->ssi_on_imx = 1;
+		/*
+		 * FIXME: The dma burst size must equal to ssi watermark
+		 * setting on imx.  We have burstsize be "fifo_depth - 2"
+		 * here because "fifo_depth - 2" rather than fifo_depth is
+		 * being written into watermark register in fsl_ssi_startup().
+		 * Is this something needs to be fixed for PowerPC?
+		 */
+		ssi_private->dma_params_tx.burstsize =
+			ssi_private->fifo_depth - 2;
+		ssi_private->dma_params_rx.burstsize =
+			ssi_private->fifo_depth - 2;
+		ssi_private->dma_params_tx.dma_addr =
+			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
+		ssi_private->dma_params_rx.dma_addr =
+			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
+		/*
+		 * TODO: This is a temporary solution and should be changed
+		 * to use generic DMA binding later when the helplers get in.
+		 */
+		ret = of_property_read_u32_array(pdev->dev.of_node,
+					"fsl,ssi-dma-events", dma_events, 2);
+		if (ret) {
+			dev_err(&pdev->dev, "could not get dma events\n");
+			goto error_irq;
+		}
+		ssi_private->dma_params_tx.dma = dma_events[0];
+		ssi_private->dma_params_rx.dma = dma_events[1];
+	}
+
 	/* Initialize the the device_attribute structure */
 	dev_attr = &ssi_private->dev_attr;
 	sysfs_attr_init(&dev_attr->attr);
@@ -725,6 +769,24 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 		goto error_dev;
 	}
 
+	/*
+	 * In case of imx, the machine driver uses new binding which does
+	 * not require SSI driver to trigger machine driver's probe, but
+	 * the pcm device needs to be registered here.
+	 */
+	if (ssi_private->ssi_on_imx) {
+		ssi_private->imx_pcm_pdev =
+			platform_device_register_simple("imx-pcm-audio",
+							-1, NULL, 0);
+		if (IS_ERR(ssi_private->imx_pcm_pdev)) {
+			ret = PTR_ERR(ssi_private->imx_pcm_pdev);
+			goto error_dev;
+		} else {
+			/* success for imx */
+			return 0;
+		}
+	}
+
 	/* Trigger the machine driver's probe function.  The platform driver
 	 * name of the machine driver is taken from /compatible property of the
 	 * device tree.  We also pass the address of the CPU DAI driver
@@ -750,6 +812,8 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 
 error_dai:
 	snd_soc_unregister_dai(&pdev->dev);
+	if (ssi_private->ssi_on_imx)
+		platform_device_unregister(ssi_private->imx_pcm_pdev);
 
 error_dev:
 	dev_set_drvdata(&pdev->dev, NULL);
@@ -776,6 +840,8 @@ static int fsl_ssi_remove(struct platform_device *pdev)
 
 	platform_device_unregister(ssi_private->pdev);
 	snd_soc_unregister_dai(&pdev->dev);
+	if (ssi_private->ssi_on_imx)
+		platform_device_unregister(ssi_private->imx_pcm_pdev);
 	device_remove_file(&pdev->dev, &ssi_private->dev_attr);
 
 	free_irq(ssi_private->irq, ssi_private);
@@ -789,6 +855,7 @@ static int fsl_ssi_remove(struct platform_device *pdev)
 
 static const struct of_device_id fsl_ssi_ids[] = {
 	{ .compatible = "fsl,mpc8610-ssi", },
+	{ .compatible = "fsl,imx1-ssi", },
 	{}
 };
 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:31:04 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:31:04 +0800
Subject: [PATCH v2 16/17] ASoC: fsl: add dt support for imx-audmux
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-17-git-send-email-shawn.guo@linaro.org>

From: Richard Zhao <richard.zhao at linaro.org>

It adds device tree probe support for imx-audmux driver.

Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../devicetree/bindings/sound/imx-audmux.txt       |   13 +++++++++++++
 sound/soc/fsl/imx-audmux.c                         |   14 ++++++++++++++
 2 files changed, 27 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/imx-audmux.txt

diff --git a/Documentation/devicetree/bindings/sound/imx-audmux.txt b/Documentation/devicetree/bindings/sound/imx-audmux.txt
new file mode 100644
index 0000000..215aa98
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audmux.txt
@@ -0,0 +1,13 @@
+Freescale Digital Audio Mux (AUDMUX) device
+
+Required properties:
+- compatible : "fsl,imx21-audmux" for AUDMUX version firstly used on i.MX21,
+  or "fsl,imx31-audmux" for the version firstly used on i.MX31.
+- reg : Should contain AUDMUX registers location and length
+
+Example:
+
+audmux at 021d8000 {
+	compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
+	reg = <0x021d8000 0x4000>;
+};
diff --git a/sound/soc/fsl/imx-audmux.c b/sound/soc/fsl/imx-audmux.c
index 87f8768..b83699d 100644
--- a/sound/soc/fsl/imx-audmux.c
+++ b/sound/soc/fsl/imx-audmux.c
@@ -22,6 +22,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
@@ -197,6 +199,13 @@ static struct platform_device_id imx_audmux_ids[] = {
 };
 MODULE_DEVICE_TABLE(platform, imx_audmux_ids);
 
+static const struct of_device_id imx_audmux_dt_ids[] = {
+	{ .compatible = "fsl,imx21-audmux", .data = &imx_audmux_ids[0], },
+	{ .compatible = "fsl,imx31-audmux", .data = &imx_audmux_ids[1], },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_audmux_dt_ids);
+
 static const uint8_t port_mapping[] = {
 	0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
 };
@@ -243,6 +252,8 @@ EXPORT_SYMBOL_GPL(imx_audmux_v2_configure_port);
 static int __init imx_audmux_probe(struct platform_device *pdev)
 {
 	struct resource *res;
+	const struct of_device_id *of_id =
+			of_match_device(imx_audmux_dt_ids, &pdev->dev);
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	audmux_base = devm_request_and_ioremap(&pdev->dev, res);
@@ -256,6 +267,8 @@ static int __init imx_audmux_probe(struct platform_device *pdev)
 		audmux_clk = NULL;
 	}
 
+	if (of_id)
+		pdev->id_entry = of_id->data;
 	audmux_type = pdev->id_entry->driver_data;
 	if (audmux_type == IMX31_AUDMUX)
 		audmux_debugfs_init();
@@ -279,6 +292,7 @@ static struct platform_driver imx_audmux_driver = {
 	.driver	= {
 		.name	= DRIVER_NAME,
 		.owner	= THIS_MODULE,
+		.of_match_table = imx_audmux_dt_ids,
 	}
 };
 
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar  5 09:31:05 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon,  5 Mar 2012 22:31:05 +0800
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>

This is the initial imx-sgtl5000 machine driver support with only
playback dai link implemented.  More features can be added on top
of it later.

It's a device tree only machine driver working with fsl_ssi driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../bindings/sound/imx-audio-sgtl5000.txt          |   24 +++
 sound/soc/fsl/Kconfig                              |   12 ++
 sound/soc/fsl/Makefile                             |    2 +
 sound/soc/fsl/imx-sgtl5000.c                       |  181 ++++++++++++++++++++
 4 files changed, 219 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
 create mode 100644 sound/soc/fsl/imx-sgtl5000.c

diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
new file mode 100644
index 0000000..22b3f03
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
@@ -0,0 +1,24 @@
+Freescale i.MX audio complex with SGTL5000 codec
+
+Required properties:
+- compatible : "fsl,imx-audio-sgtl5000"
+- fsl,model : The user-visible name of this sound complex
+- fsl,ssi-controller : The phandle of the i.MX SSI controller
+- fsl,audio-codec : The phandle of the SGTL5000 audio codec
+- fsl,mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
+- fsl,mux-ext-port : The external port of the i.MX audio muxer
+
+Note: The AUDMUX port numbering should start at 1, which is consistent with
+hardware manual.
+
+Example:
+
+sound {
+	compatible = "fsl,imx51-babbage-sgtl5000",
+		     "fsl,imx-audio-sgtl5000";
+	fsl,model = "imx51-babbage-sgtl5000";
+	fsl,ssi-controller = <&ssi1>;
+	fsl,audio-codec = <&sgtl5000>;
+	fsl,mux-int-port = <1>;
+	fsl,mux-ext-port = <3>;
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index e579671..42a3842 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -164,4 +164,16 @@ config SND_SOC_EUKREA_TLV320
 	  Enable I2S based access to the TLV320AIC23B codec attached
 	  to the SSI interface
 
+config SND_SOC_IMX_SGTL5000
+	tristate "SoC Audio support for i.MX boards with sgtl5000"
+	depends on OF && I2C
+	select SND_SOC_SGTL5000
+	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
+	help
+	  Say Y if you want to add support for SoC audio on an i.MX board with
+	  a sgtl5000 codec.
+
 endif # SND_IMX_SOC
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 02b3e53..5ae854b 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -40,8 +40,10 @@ snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
 snd-soc-phycore-ac97-objs := phycore-ac97.o
 snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
 snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
 
 obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
 obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
 obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
 obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
+obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
diff --git a/sound/soc/fsl/imx-sgtl5000.c b/sound/soc/fsl/imx-sgtl5000.c
new file mode 100644
index 0000000..f34ebd8
--- /dev/null
+++ b/sound/soc/fsl/imx-sgtl5000.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <sound/soc.h>
+
+#include "../codecs/sgtl5000.h"
+#include "fsl_utils.h"
+#include "imx-audmux.h"
+
+struct imx_sgtl5000_data {
+	struct snd_soc_dai_link dai[2];
+	struct snd_soc_card card;
+	char codec_name[DAI_NAME_SIZE];
+	char codec_dai_name[DAI_NAME_SIZE];
+	char platform_name[DAI_NAME_SIZE];
+	unsigned int clk_frequency;
+};
+
+static int imx_sgtl5000_dai_init(struct snd_soc_pcm_runtime *rtd)
+{
+	struct imx_sgtl5000_data *data = container_of(rtd->card,
+					struct imx_sgtl5000_data, card);
+	struct device *dev = rtd->card->dev;
+	int ret;
+
+	ret = snd_soc_dai_set_fmt(rtd->codec_dai, SND_SOC_DAIFMT_I2S |
+						  SND_SOC_DAIFMT_NB_NF |
+						  SND_SOC_DAIFMT_CBM_CFM);
+	if (ret) {
+		dev_err(dev, "could not set codec driver audio format\n");
+		return ret;
+	}
+
+	ret = snd_soc_dai_set_sysclk(rtd->codec_dai, SGTL5000_SYSCLK,
+				     data->clk_frequency, SND_SOC_CLOCK_IN);
+	if (ret) {
+		dev_err(dev, "could not set codec driver clock params\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __devinit imx_sgtl5000_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *ssi_np, *codec_np;
+	struct platform_device *ssi_pdev;
+	struct imx_sgtl5000_data *data;
+	int int_port, ext_port;
+	int ret;
+
+	ret = of_property_read_u32(np, "fsl,mux-int-port", &int_port);
+	if (ret) {
+		dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
+		return -EINVAL;
+	}
+	ret = of_property_read_u32(np, "fsl,mux-ext-port", &ext_port);
+	if (ret) {
+		dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * The port numbering in the hardware manual starts at 1, while
+	 * the audmux API expects it starts at 0.
+	 */
+	int_port--;
+	ext_port--;
+	imx_audmux_v2_configure_port(int_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TFSDIR |
+			IMX_AUDMUX_V2_PTCR_TCLKDIR,
+			IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
+	imx_audmux_v2_configure_port(ext_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TCSEL(int_port),
+			IMX_AUDMUX_V2_PDCR_RXDSEL(int_port));
+
+	ssi_np = of_parse_phandle(pdev->dev.of_node, "fsl,ssi-controller", 0);
+	codec_np = of_parse_phandle(pdev->dev.of_node, "fsl,audio-codec", 0);
+	if (!ssi_np || !codec_np) {
+		dev_err(&pdev->dev, "phandle missing or invalid\n");
+		return -EINVAL;
+	}
+
+	ssi_pdev = of_find_device_by_node(ssi_np);
+	if (!ssi_pdev) {
+		dev_err(&pdev->dev, "failed to find SSI platform device\n");
+		return -EINVAL;
+	}
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	ret = of_property_read_u32(codec_np, "clock-frequency",
+				   &data->clk_frequency);
+	if (ret) {
+		dev_err(&pdev->dev, "clock-frequency missing or invalid\n");
+		return -EINVAL;
+	}
+
+	ret = fsl_asoc_get_codec_dev_name(codec_np, data->codec_name,
+					  DAI_NAME_SIZE);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to get codec name\n");
+		return -EINVAL;
+	}
+
+	data->dai[0].name = "HiFi Tx";
+	data->dai[0].stream_name = "HiFi Playback";
+	data->dai[0].codec_dai_name = "sgtl5000";
+	data->dai[0].codec_name = data->codec_name;
+	data->dai[0].cpu_dai_name = dev_name(&ssi_pdev->dev);
+	data->dai[0].platform_name = "imx-pcm-audio";
+	data->dai[0].init = &imx_sgtl5000_dai_init;
+
+	data->card.dev = &pdev->dev;
+	ret = snd_soc_of_parse_card_name(&data->card, "fsl,model");
+	if (ret)
+		return ret;
+	data->card.num_links = 1;
+	data->card.dai_link = data->dai;
+
+	ret = snd_soc_register_card(&data->card);
+	if (ret) {
+		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, data);
+	of_node_put(codec_np);
+
+	return 0;
+}
+
+static int __devexit imx_sgtl5000_remove(struct platform_device *pdev)
+{
+	struct imx_sgtl5000_data *data = platform_get_drvdata(pdev);
+
+	snd_soc_unregister_card(&data->card);
+
+	return 0;
+}
+
+static const struct of_device_id imx_sgtl5000_dt_ids[] = {
+	{ .compatible = "fsl,imx-audio-sgtl5000", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_sgtl5000_dt_ids);
+
+static struct platform_driver imx_sgtl5000_driver = {
+	.driver = {
+		.name = "imx-sgtl5000",
+		.owner = THIS_MODULE,
+		.of_match_table = imx_sgtl5000_dt_ids,
+	},
+	.probe = imx_sgtl5000_probe,
+	.remove = __devexit_p(imx_sgtl5000_remove),
+};
+module_platform_driver(imx_sgtl5000_driver);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo at linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX SGTL5000 ASoC machine driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx-sgtl5000");
-- 
1.7.5.4



From b-cousson at ti.com  Mon Mar  5 09:25:01 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 5 Mar 2012 15:25:01 +0100
Subject: [GIT PULL] ARM: OMAP: IRQ domain support for INTC
In-Reply-To: <20120305135838.GA2108@localhost>
References: <4F4BB0FB.3040308@ti.com> <20120228234837.GH18901@atomide.com>
 <4F4E4F1D.7020109@ti.com> <20120305135838.GA2108@localhost>
Message-ID: <4F54CCBD.2080802@ti.com>

On 3/5/2012 2:58 PM, Johan Hovold wrote:
> On Wed, Feb 29, 2012 at 05:15:25PM +0100, Cousson, Benoit wrote:
>> On 2/29/2012 12:48 AM, Tony Lindgren wrote:
>>> * Cousson, Benoit<b-cousson at ti.com>   [120227 08:04]:
>>>> Hi Tony
>>>>
>>>> This series is based on the lo/dt + the irqdomain/next branch merged on top of it.
>>>>
>>>> Grant confirmed that the irqdomain/next is a stable branch and thus can be referenced for dependency.
>>>>
>>>> Please note that I will need that branch to base all the remaining OMAP DT stuff.
>>>>
>>>> Thanks,
>>>> Benoit
>>>>
>>>>
>>>> The following changes since commit 1f52299ec000e2161635b263d81ab92ea7f1f0a7:
>>>>     Benoit Cousson (1):
>>>>           Merge branch 'irqdomain/next' of git://git.secretlab.ca/git/linux-2.6 into for_3.4/dt_irq_domain2
>>>>
>>>> are available in the git repository at:
>>>>
>>>>     git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/dt_irq_domain
>>>>
>>>> Benoit Cousson (3):
>>>>         ARM: OMAP2/3: intc: Add DT support for TI interrupt controller
>>>>         arm/dts: OMAP3: Add interrupt-controller bindings for INTC
>>>>         ARM: OMAP2+: board-generic: Use of_irq_init API
>>>>
>>>>    .../devicetree/bindings/arm/omap/intc.txt          |   27 +++++++++
>>>>    arch/arm/boot/dts/omap3.dtsi                       |    6 +-
>>>>    arch/arm/mach-omap2/board-generic.c                |   30 +++++-----
>>>>    arch/arm/mach-omap2/common.h                       |   12 ++++
>>>>    arch/arm/mach-omap2/irq.c                          |   60 ++++++++++++++++---
>>>>    5 files changed, 109 insertions(+), 26 deletions(-)
>>>>    create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt
>>>
>>> Hmm, looks like this now produces the following warning at least on omap3:
>>
>> Yes, Rajendra has just reported that issue with linux-next.
>
> I'm getting the same warning and initialisation failure with 3.3-rc6 on
> overo. Are these fixes queued up for 3.3 (and not just 3.4) somewhere?

It is under review, I posted the series last Friday:
mfd: twl: Fix for irqdomain/next + SPARSE_IRQ + MMC card detect

It will be anyway material for 3.4 since it is in linux-next.

Regards,
Benoit


From shawn.guo at linaro.org  Mon Mar  5 09:44:03 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 5 Mar 2012 22:44:03 +0800
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <20120305142009.GO3224@opensource.wolfsonmicro.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <20120305142009.GO3224@opensource.wolfsonmicro.com>
Message-ID: <20120305144400.GH16232@S2101-09.ap.freescale.net>

On Mon, Mar 05, 2012 at 02:20:10PM +0000, Mark Brown wrote:
> On Mon, Mar 05, 2012 at 10:30:48PM +0800, Shawn Guo wrote:
> > Changes since v1:
> >  * Address comments from Mark, Timur, and Sascha (Thanks for review).
> >  * Drop patches that have been applied by Mark.
> 
> I see you've ignored my comments about reordering the patches so they
> can be applied more easily :(

Sorry, if it makes your life hard.  But I hope I can win ack from Sascha
and Timur soon, so that the series can be applied as a whole anyway.

-- 
Regards,
Shawn


From arnd at arndb.de  Mon Mar  5 09:34:34 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 5 Mar 2012 14:34:34 +0000
Subject: [GIT PULL v3] ARM: kirkwood: fdt: convert kirkwood init funcs to
 fdt
In-Reply-To: <20120305133242.GD5050@titan.lakedaemon.net>
References: <20120305034113.GB5050@titan.lakedaemon.net>
 <20120305133242.GD5050@titan.lakedaemon.net>
Message-ID: <201203051434.35132.arnd@arndb.de>

On Monday 05 March 2012, Jason wrote:
> This is still bugging me.  If, say, orion_wdt.c is common to all of
> plat-orion/ shouldn't it be in an 'orion.dtsi'?  With compatible =
> "marvell,orion-wdt"?  Then, if hypothetically, kirkwood used the same
> driver but had a small tweak, then kirkwood.dtsi would have
> "marvell,kirkwood-wdt"?  Which would let the driver know that it needed
> to apply the tweak because it was kirkwood.

Some drivers are common to all orion, but others are only used in some
out of {orion5k,kirkwood,mv78xx0,dove}. You could of course have
an orion.dtsi that is included in kirkwood.dtsi.

BTW, I just realized that the patches that Haojian Zhuang sent for
pxa/mmp are using mrvl instead of marvell, and you should definitely
be using the same identifier both both. By convention we use the
stock ticker symbol as a unique identifier, which would be mrvl here.

> In this scenario, since kirkwood and dreamplug currently need no
> modifications to the default wdt driver, they would just inherit
> orion.dtsi's "marvell,orion-wdt", right?

I would still list both, so we are future-proof in case we need
to modify the driver in the future but don't want to modify
the device tree.

> On the driver side, since it currently has no subarch or board specific
> tweaks, then it is only good for the generic case,
> "marvell,orion-wdt", and thus should only match it for now.

Yes.

> If the above is correct, then I should create orion.dtsi, which is
> included by kirkwood.dtsi.  orion.dtsi should hold "marvell,orion-wdt"
> and "marvell,orion-rtc".  The corresponding drivers should only match
> those generic strings, since there are no specific tweaks.
> 
> I hate to keep kicking this horse, but I want to make sure I grok it.

Sounds right to me.

	Arnd


From broonie at opensource.wolfsonmicro.com  Mon Mar  5 09:35:04 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 14:35:04 +0000
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <20120305144400.GH16232@S2101-09.ap.freescale.net>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <20120305142009.GO3224@opensource.wolfsonmicro.com>
 <20120305144400.GH16232@S2101-09.ap.freescale.net>
Message-ID: <20120305143504.GP3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 10:44:03PM +0800, Shawn Guo wrote:
> On Mon, Mar 05, 2012 at 02:20:10PM +0000, Mark Brown wrote:

> > I see you've ignored my comments about reordering the patches so they
> > can be applied more easily :(

> Sorry, if it makes your life hard.  But I hope I can win ack from Sascha
> and Timur soon, so that the series can be applied as a whole anyway.

If you resend again please do pull out those two commits, in general
smaller serieses doing one thing are much better.
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From arnd at arndb.de  Mon Mar  5 09:35:58 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 5 Mar 2012 14:35:58 +0000
Subject: [PATCH v2 6/7] ARM: dts: append DTS file of pxa168
In-Reply-To: <1330950111-30797-7-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
 <1330950111-30797-7-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203051435.58701.arnd@arndb.de>

On Monday 05 March 2012, Haojian Zhuang wrote:
> 
> DTS files of both PXA168 and aspenite are appended.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Mon Mar  5 09:37:48 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 5 Mar 2012 14:37:48 +0000
Subject: [PATCH v2 5/7] ARM: mmp: append OF support on pxa168
In-Reply-To: <1330950111-30797-6-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
 <1330950111-30797-6-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203051437.48176.arnd@arndb.de>

On Monday 05 March 2012, Haojian Zhuang wrote:
> Enable PXA168 and aspenite support.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Mon Mar  5 09:38:06 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 5 Mar 2012 14:38:06 +0000
Subject: [PATCH v2 4/7] ARM: mmp: enable rtc clk in pxa168
In-Reply-To: <1330950111-30797-5-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
 <1330950111-30797-5-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203051438.06270.arnd@arndb.de>

On Monday 05 March 2012, Haojian Zhuang wrote:
> Enable clk of rtc-sa1100 device in pxa168.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From jason at lakedaemon.net  Mon Mar  5 09:38:19 2012
From: jason at lakedaemon.net (Jason)
Date: Mon, 5 Mar 2012 09:38:19 -0500
Subject: [GIT PULL v3] ARM: kirkwood: fdt: convert kirkwood init funcs
 to fdt
In-Reply-To: <20120305141656.GA14449@lunn.ch>
References: <20120305141656.GA14449@lunn.ch>
Message-ID: <20120305143819.GE5050@titan.lakedaemon.net>

On Mon, Mar 05, 2012 at 03:16:56PM +0100, Andrew Lunn wrote:
> > On Sun, Mar 04, 2012 at 10:41:13PM -0500, Jason Cooper wrote:
> > >       rtc-mv: more accurate compatible strings
> > >       orion-wdt: more accurate compatible strings
> > ...
> > >  arch/arm/boot/dts/kirkwood-dreamplug.dts |   34 +++++++++++++++
> > >  arch/arm/boot/dts/kirkwood.dtsi          |   12 +++++
> > 
> > This is still bugging me.  If, say, orion_wdt.c is common to all of
> > plat-orion/ shouldn't it be in an 'orion.dtsi'?  With compatible =
> > "marvell,orion-wdt"?  Then, if hypothetically, kirkwood used the same
> > driver but had a small tweak, then kirkwood.dtsi would have
> > "marvell,kirkwood-wdt"?  Which would let the driver know that it needed
> > to apply the tweak because it was kirkwood.
> > 
> > In this scenario, since kirkwood and dreamplug currently need no
> > modifications to the default wdt driver, they would just inherit
> > orion.dtsi's "marvell,orion-wdt", right?
> > 
> > On the driver side, since it currently has no subarch or board specific
> > tweaks, then it is *only* good for the generic case,
> > "marvell,orion-wdt", and thus should only match it for now.
> > 
> > If the above is correct, then I should create orion.dtsi, which is
> > included by kirkwood.dtsi.  orion.dtsi should hold "marvell,orion-wdt"
> > and "marvell,orion-rtc".  The corresponding drivers should only match
> > those generic strings, since there are no specific tweaks.
> 
> Hi Jason
> 
> I would agree with you in principal, that most of the drivers used by
> kirkwood are generic orion drivers. There is one clear exception to
> this, and that is the audio driver, which is specific to Kirkwood.
> 
> However, what differs between all the different plat-orion SoC is the
> address map and interrupts. So the dove wdt is in a different place to
> the orion5x wdt, and uses a different interrupt line, etc.

Yes, I was just checking into that.  Seems to me then, it should be
defined at the lowest level where everything is the same.  So, since
kirkwood uses the same registers and irq lines across kirkwood boards,
placing orion_wdt in kirkwood.dtsi would be appropriate.

orion.dtsi doesn't make much sense unless there is something in common
across all the subarchs, attributes included.

Also, only devices which are common to *all* boards, and active would go
in kirkwood.dtsi.  Which is why we decided to place uart0 in
kirkwood-dreamplug.dts.  The serial port doesn't need to be enabled in
a production system, so including kirkwood.dtsi shouldn't enable it.

> So i expect in the end we have a dove.dtsi, a orion5x.dtsi, a
> mv78xx0.dtsi and a kirkwood.dtsi which all look very similar, but have
> different values for addresses and interrupts.

I'm coming to the same conclusion.

> Maybe DT has some why to handle this? 

I think this is the way it is Supposed To Be.

> As to naming, i think you are correct. It should be
> "marvell,orion-wdt" in all the different .dtsi files, since its the
> same SoC IP in all Orion devices. Same with "marvell,orion-rtc" since
> all orion based SoC have the same built in RTC IP.

Agreed.

thx,

Jason.


From Joerg.Roedel at amd.com  Mon Mar  5 09:39:58 2012
From: Joerg.Roedel at amd.com (Joerg Roedel)
Date: Mon, 5 Mar 2012 15:39:58 +0100
Subject: [PATCH] ARM: OMAP: fix iommu, not mailbox
In-Reply-To: <1330855271-28820-1-git-send-email-ohad@wizery.com>
References: <1330855271-28820-1-git-send-email-ohad@wizery.com>
Message-ID: <20120305143957.GK10684@amd.com>

On Sun, Mar 04, 2012 at 12:01:11PM +0200, Ohad Ben-Cohen wrote:
> For some weird (freudian?) reason, commit 435792d "ARM: OMAP: make
> iommu subsys_initcall to fix builtin omap3isp" unintentionally changed
> the mailbox's initcall instead of the iommu's.
> 
> Fix that.

Applied, thanks.

-- 
AMD Operating System Research Center

Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632



From arnd at arndb.de  Mon Mar  5 09:41:26 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 5 Mar 2012 14:41:26 +0000
Subject: [PATCH v2 3/7] i2c: pxa: add OF support
In-Reply-To: <1330950111-30797-4-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
 <1330950111-30797-4-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203051441.26774.arnd@arndb.de>

On Monday 05 March 2012, Haojian Zhuang wrote:
> Append these properties in below.
> mrvl,i2c-polling
> mrvl,i2c-fast-mode
> 
> Still keep slave, slave_addr and class in platform data.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>

Just one tiny detail:

> +       *i2c_types = (u32)(of_id->data);

By convention, please use (unsigned long) as the cast from pointer to an
integer type. While this doesn't make any difference on 32 bit systems,
it's better to always write code that is 64-bit clean.

	Arnd


From arnd at arndb.de  Mon Mar  5 09:41:46 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 5 Mar 2012 14:41:46 +0000
Subject: [PATCH v2 2/7] rtc: sa1100: add OF support
In-Reply-To: <1330950111-30797-3-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
 <1330950111-30797-3-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203051441.47062.arnd@arndb.de>

On Monday 05 March 2012, Haojian Zhuang wrote:
> Add OF support on rtc-sa1100.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From wade_farnsworth at mentor.com  Mon Mar  5 09:42:28 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Mon, 5 Mar 2012 07:42:28 -0700
Subject: [PATCH v3 0/3] ARM support for syscall tracing
In-Reply-To: <4F4E3780.4060904@mentor.com>
References: <4F44FF58.3060907@mentor.com> <4F4E3780.4060904@mentor.com>
Message-ID: <4F54D0D4.7070905@mentor.com>

This is a rework of Steven Walter's syscall tracing patches first
posted here:

http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074454.html

I've rebased the patches against the current mainline master branch, as well
as implemented several changes based on feedback from Will Deacon and
Russell King.

v2: - Tested on EABI and OABI.
    - Removed an instance of the ?: operator in syscall_set_return_value()
    - Moved #define of NR_syscalls to syscall.h
    - Changed the test of NR_syscalls vs __NR_syscalls in entry-common.S
      to .ifne
v3: - Added Will Deacon's Reviewed-by line.  Code is identical to v2.

Wade Farnsworth (3):
  ARM: add support for the generic syscall.h interface
  ARM: add TRACEHOOK support
  ARM: support syscall tracing

 arch/arm/Kconfig                   |    2 +
 arch/arm/include/asm/ptrace.h      |    5 ++
 arch/arm/include/asm/syscall.h     |   97 ++++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/thread_info.h |    2 +
 arch/arm/include/asm/unistd.h      |    8 +++
 arch/arm/kernel/entry-common.S     |   16 +++++-
 arch/arm/kernel/ptrace.c           |   34 +++++++------
 arch/arm/kernel/signal.c           |    2 +
 8 files changed, 149 insertions(+), 17 deletions(-)
 create mode 100644 arch/arm/include/asm/syscall.h



From wade_farnsworth at mentor.com  Mon Mar  5 09:43:08 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Mon, 5 Mar 2012 07:43:08 -0700
Subject: [PATCH v3 1/3] ARM: add support for the generic syscall.h interface
In-Reply-To: <4F54D0D4.7070905@mentor.com>
References: <4F44FF58.3060907@mentor.com> <4F4E3780.4060904@mentor.com>
 <4F54D0D4.7070905@mentor.com>
Message-ID: <4F54D0FC.5070205@mentor.com>

Supplying the asm-generic/syscall.h interface is a
pre-requisite for HAVE_ARCH_TRACEHOOK

Signed-off-by: Steven Walter <stevenrwalter at gmail.com>
Signed-off-by: Wade Farnsworth <wade_farnsworth at mentor.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/syscall.h |   93 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 93 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/syscall.h

diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
new file mode 100644
index 0000000..c334a23
--- /dev/null
+++ b/arch/arm/include/asm/syscall.h
@@ -0,0 +1,93 @@
+/*
+ * Access to user system call parameters and results
+ *
+ * See asm-generic/syscall.h for descriptions of what we must do here.
+ */
+
+#ifndef _ASM_ARM_SYSCALL_H
+#define _ASM_ARM_SYSCALL_H
+
+#include <linux/err.h>
+
+extern const unsigned long sys_call_table[];
+
+static inline int syscall_get_nr(struct task_struct *task,
+				 struct pt_regs *regs)
+{
+	return task_thread_info(task)->syscall;
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+				    struct pt_regs *regs)
+{
+	regs->ARM_r0 = regs->ARM_ORIG_r0;
+}
+
+static inline long syscall_get_error(struct task_struct *task,
+				     struct pt_regs *regs)
+{
+	unsigned long error = regs->ARM_r0;
+	return IS_ERR_VALUE(error) ? error : 0;
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+					    struct pt_regs *regs)
+{
+	return regs->ARM_r0;
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+					    struct pt_regs *regs,
+					    int error, long val)
+{
+	regs->ARM_r0 = (long) error ? error : val;
+}
+
+#define SYSCALL_MAX_ARGS 7
+
+static inline void syscall_get_arguments(struct task_struct *task,
+					 struct pt_regs *regs,
+					 unsigned int i, unsigned int n,
+					 unsigned long *args)
+{
+	if (i + n > SYSCALL_MAX_ARGS) {
+		unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
+		unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
+		pr_warning("%s called with max args %d, handling only %d\n",
+			   __func__, i + n, SYSCALL_MAX_ARGS);
+		memset(args_bad, 0, n_bad * sizeof(args[0]));
+		n = SYSCALL_MAX_ARGS - i;
+	}
+
+	if (i == 0) {
+		args[0] = regs->ARM_ORIG_r0;
+		args++;
+		i++;
+		n--;
+	}
+
+	memcpy(args, &regs->ARM_r0 + i, n * sizeof(args[0]));
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+					 struct pt_regs *regs,
+					 unsigned int i, unsigned int n,
+					 const unsigned long *args)
+{
+	if (i + n > SYSCALL_MAX_ARGS) {
+		pr_warning("%s called with max args %d, handling only %d\n",
+			   __func__, i + n, SYSCALL_MAX_ARGS);
+		n = SYSCALL_MAX_ARGS - i;
+	}
+
+	if (i == 0) {
+		regs->ARM_ORIG_r0 = args[0];
+		args++;
+		i++;
+		n--;
+	}
+
+	memcpy(&regs->ARM_r0 + i, args, n * sizeof(args[0]));
+}
+
+#endif /* _ASM_ARM_SYSCALL_H */
-- 
1.7.0.4



From wade_farnsworth at mentor.com  Mon Mar  5 09:43:49 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Mon, 5 Mar 2012 07:43:49 -0700
Subject: [PATCH v3 2/3] ARM: add TRACEHOOK support
In-Reply-To: <4F54D0D4.7070905@mentor.com>
References: <4F44FF58.3060907@mentor.com> <4F4E3780.4060904@mentor.com>
 <4F54D0D4.7070905@mentor.com>
Message-ID: <4F54D125.3050405@mentor.com>

Add calls to tracehook_report_syscall_{entry,exit} and tracehook_signal_handler

Signed-off-by: Steven Walter <stevenrwalter at gmail.com>
Signed-off-by: Wade Farnsworth <wade_farnsworth at mentor.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig              |    1 +
 arch/arm/include/asm/ptrace.h |    5 +++++
 arch/arm/kernel/ptrace.c      |   21 ++++++---------------
 arch/arm/kernel/signal.c      |    2 ++
 4 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a48aecc..0faad0c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -10,6 +10,7 @@ config ARM
 	select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
 	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
 	select HAVE_ARCH_KGDB
+	select HAVE_ARCH_TRACEHOOK
 	select HAVE_KPROBES if !XIP_KERNEL
 	select HAVE_KRETPROBES if (HAVE_KPROBES)
 	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 451808b..355ece5 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -249,6 +249,11 @@ static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
 	return regs->ARM_sp;
 }
 
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+	return regs->ARM_sp;
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index ede6443..46f4b41 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -24,6 +24,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/regset.h>
 #include <linux/audit.h>
+#include <linux/tracehook.h>
 
 #include <asm/pgtable.h>
 #include <asm/system.h>
@@ -930,24 +931,14 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
 
 	if (!test_thread_flag(TIF_SYSCALL_TRACE))
 		return scno;
-	if (!(current->ptrace & PT_PTRACED))
-		return scno;
 
 	current_thread_info()->syscall = scno;
 
-	/* the 0x80 provides a way for the tracing parent to distinguish
-	   between a syscall stop and SIGTRAP delivery */
-	ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
-				 ? 0x80 : 0));
-	/*
-	 * this isn't the same as continuing with a signal, but it will do
-	 * for normal use.  strace only continues with a signal if the
-	 * stopping signal is not SIGTRAP.  -brl
-	 */
-	if (current->exit_code) {
-		send_sig(current->exit_code, current, 1);
-		current->exit_code = 0;
-	}
+	if (why)
+		tracehook_report_syscall_exit(regs, 0);
+	else if (tracehook_report_syscall_entry(regs))
+		current_thread_info()->syscall = -1;
+
 	regs->ARM_ip = ip;
 
 	return current_thread_info()->syscall;
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 9e617bd..6f084c1 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -644,6 +644,8 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
 	recalc_sigpending();
 	spin_unlock_irq(&tsk->sighand->siglock);
 
+	tracehook_signal_handler(sig, info, ka, regs, 0);
+
 	return 0;
 }
 
-- 
1.7.0.4



From wade_farnsworth at mentor.com  Mon Mar  5 09:44:27 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Mon, 5 Mar 2012 07:44:27 -0700
Subject: [PATCH v3 3/3] ARM: support syscall tracing
In-Reply-To: <4F54D0D4.7070905@mentor.com>
References: <4F44FF58.3060907@mentor.com> <4F4E3780.4060904@mentor.com>
 <4F54D0D4.7070905@mentor.com>
Message-ID: <4F54D14B.8070201@mentor.com>

As specified by ftrace-design.txt, TIF_SYSCALL_TRACEPOINT was
added, as well as NR_syscalls in asm/unistd.h.  Additionally,
__sys_trace was modified to call trace_sys_enter and
trace_sys_exit when appropriate.

Tests #2 - #4 of "perf test" now complete successfully.

Signed-off-by: Steven Walter <stevenrwalter at gmail.com>
Signed-off-by: Wade Farnsworth <wade_farnsworth at mentor.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig                   |    1 +
 arch/arm/include/asm/syscall.h     |    4 ++++
 arch/arm/include/asm/thread_info.h |    2 ++
 arch/arm/include/asm/unistd.h      |    8 ++++++++
 arch/arm/kernel/entry-common.S     |   16 ++++++++++++++--
 arch/arm/kernel/ptrace.c           |   23 ++++++++++++++++++-----
 6 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0faad0c..b1d9396 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -11,6 +11,7 @@ config ARM
 	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
 	select HAVE_ARCH_KGDB
 	select HAVE_ARCH_TRACEHOOK
+	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_KPROBES if !XIP_KERNEL
 	select HAVE_KRETPROBES if (HAVE_KPROBES)
 	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index c334a23..47486a4 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -9,6 +9,10 @@
 
 #include <linux/err.h>
 
+#include <asm/unistd.h>
+
+#define NR_syscalls (__NR_syscalls)
+
 extern const unsigned long sys_call_table[];
 
 static inline int syscall_get_nr(struct task_struct *task,
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index d4c24d4..f2ff2de 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -146,6 +146,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define TIF_MEMDIE		18	/* is terminating due to OOM killer */
 #define TIF_RESTORE_SIGMASK	20
 #define TIF_SECCOMP		21
+#define TIF_SYSCALL_TRACEPOINT	22
 
 #define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
@@ -156,6 +157,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define _TIF_USING_IWMMXT	(1 << TIF_USING_IWMMXT)
 #define _TIF_RESTORE_SIGMASK	(1 << TIF_RESTORE_SIGMASK)
 #define _TIF_SECCOMP		(1 << TIF_SECCOMP)
+#define _TIF_SYSCALL_TRACEPOINT	(1 << TIF_SYSCALL_TRACEPOINT)
 
 /* Checks for any syscall work in entry-common.S */
 #define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 512cd14..d27d7d7 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -406,6 +406,14 @@
 #define __NR_process_vm_writev		(__NR_SYSCALL_BASE+377)
 
 /*
+ * This may need to be greater than __NR_last_syscall+1 in order to
+ * account for the padding in the syscall table
+ */
+#ifdef __KERNEL__
+#define __NR_syscalls  (380)
+#endif /* __KERNEL__ */
+
+/*
  * The following SWIs are ARM private.
  */
 #define __ARM_NR_BASE			(__NR_SYSCALL_BASE+0x0f0000)
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 9fd0ba9..01686b2 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -79,6 +79,11 @@ no_work_pending:
 ENDPROC(ret_to_user_from_irq)
 ENDPROC(ret_to_user)
 
+.macro test_syscall_tracing reg
+       tst     \reg, #_TIF_SYSCALL_WORK
+       tsteq   \reg, #_TIF_SYSCALL_TRACEPOINT
+.endm
+
 /*
  * This is how we return from a fork.
  */
@@ -87,7 +92,7 @@ ENTRY(ret_from_fork)
 	get_thread_info tsk
 	ldr	r1, [tsk, #TI_FLAGS]		@ check for syscall tracing
 	mov	why, #1
-	tst	r1, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
+	test_syscall_tracing r1
 	beq	ret_slow_syscall
 	mov	r1, sp
 	mov	r0, #1				@ trace exit [IP = 1]
@@ -98,6 +103,13 @@ ENDPROC(ret_from_fork)
 	.equ NR_syscalls,0
 #define CALL(x) .equ NR_syscalls,NR_syscalls+1
 #include "calls.S"
+
+/* Ensure that the system call table is not larger than __NR_syscalls,
+ * which is the value the rest of the system sees */
+.ifne NR_syscalls - __NR_syscalls
+.error "__NR_syscalls is less than the size of the syscall table"
+.endif
+
 #undef CALL
 #define CALL(x) .long x
 
@@ -446,7 +458,7 @@ ENTRY(vector_swi)
 1:
 #endif
 
-	tst	r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
+	test_syscall_tracing r10
 	bne	__sys_trace
 
 	cmp	scno, #NR_syscalls		@ check upper syscall limit
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 46f4b41..dbbf4ce 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -30,6 +30,9 @@
 #include <asm/system.h>
 #include <asm/traps.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
 #define REG_PC	15
 #define REG_PSR	16
 /*
@@ -929,15 +932,25 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
 		audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0,
 				    regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
 
-	if (!test_thread_flag(TIF_SYSCALL_TRACE))
+	if (!test_thread_flag(TIF_SYSCALL_TRACE) &&
+	    !test_thread_flag(TIF_SYSCALL_TRACEPOINT))
 		return scno;
 
 	current_thread_info()->syscall = scno;
 
-	if (why)
-		tracehook_report_syscall_exit(regs, 0);
-	else if (tracehook_report_syscall_entry(regs))
-		current_thread_info()->syscall = -1;
+	if (test_thread_flag(TIF_SYSCALL_TRACE)) {
+		if (why)
+			tracehook_report_syscall_exit(regs, 0);
+		else if (tracehook_report_syscall_entry(regs))
+			current_thread_info()->syscall = -1;
+	}
+
+	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) {
+		if (why)
+			trace_sys_exit(regs, scno);
+		else
+			trace_sys_enter(regs, scno);
+	}
 
 	regs->ARM_ip = ip;
 
-- 
1.7.0.4



From broonie at opensource.wolfsonmicro.com  Mon Mar  5 09:46:01 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 14:46:01 +0000
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120305144601.GQ3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 10:31:05PM +0800, Shawn Guo wrote:

> +	ret = snd_soc_dai_set_fmt(rtd->codec_dai, SND_SOC_DAIFMT_I2S |
> +						  SND_SOC_DAIFMT_NB_NF |
> +						  SND_SOC_DAIFMT_CBM_CFM);
> +	if (ret) {
> +		dev_err(dev, "could not set codec driver audio format\n");
> +		return ret;
> +	}

This you can just set in the card struct, no need for explicit code at
all.

> +	ret = of_property_read_u32(np, "fsl,mux-int-port", &int_port);
> +	if (ret) {
> +		dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
> +		return -EINVAL;
> +	}
> +	ret = of_property_read_u32(np, "fsl,mux-ext-port", &ext_port);
> +	if (ret) {
> +		dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
> +		return -EINVAL;
> +	}

It seems very odd to have namespacing on the individual property names.
Why are you doing that?  The properties are already defined in terms of
the device binding.  Though everyone else is doing it so not really a
problem.

> +	/*
> +	 * The port numbering in the hardware manual starts at 1, while
> +	 * the audmux API expects it starts at 0.
> +	 */
> +	int_port--;
> +	ext_port--;

Should have error checking somewhere to make sure that the user
remembered this.

> +	imx_audmux_v2_configure_port(int_port,
> +			IMX_AUDMUX_V2_PTCR_SYN |
> +			IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
> +			IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
> +			IMX_AUDMUX_V2_PTCR_TFSDIR |
> +			IMX_AUDMUX_V2_PTCR_TCLKDIR,
> +			IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));

I'm not sure we've really gained much from converting to a platform
driver given that the device just registers something globally...
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From arnd at arndb.de  Mon Mar  5 09:46:14 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 5 Mar 2012 14:46:14 +0000
Subject: [PATCH v2 7/7] Document: devicetree: add OF documents for arch-mmp
In-Reply-To: <1330950111-30797-8-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
 <1330950111-30797-8-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203051446.14600.arnd@arndb.de>

On Monday 05 March 2012, Haojian Zhuang wrote:
> Add OF support in Document/devicetree directory.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>

One question for Benoit, Grant or Rob:

> +Required properties:
> +- compatible: should be "mrvl,sa1100-rtc"
> +- reg: physical base address of the controller and length of memory mapped
> +  region.
> +- interrupts: Should be two. The first interrupt number is the rtc alarm
> +  interrupt and the second interrupt number is the rtc hz interrupt.
> +- interrupt-names: Assign name of irq resource.
> +
> +Example:
> +	rtc: rtc at d4010000 {
> +		compatible = "mrvl,mmp-rtc";
> +		reg = <0xd4010000 0x1000>;
> +		interrupts = <5>, <6>;
> +		interrupt-name = "rtc 1Hz", "rtc alarm";
> +	};

When the binding for a device lists the interrupt-names property, should it
also list the specific values for it? This one says that which ones they are,
but I think we should actually mandate the exact string in the binding if
we want to allow drivers to get the resource by its name.

	Arnd


From broonie at opensource.wolfsonmicro.com  Mon Mar  5 09:49:20 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 14:49:20 +0000
Subject: [PATCH v2 11/17] ASoC: fsl: create fsl_utils to accommodate the
 common functions
In-Reply-To: <1330957865-19085-12-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-12-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120305144920.GR3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 10:30:59PM +0800, Shawn Guo wrote:

> +/**
> + * fsl_asoc_get_codec_dev_name - determine the dev_name for a codec node
> + *
> + * @np: pointer to the I2C device tree node
> + * @buf: buffer to be filled with the dev_name of the I2C device
> + * @len: the length of the buffer
> + *
> + * This function determines the dev_name for an I2C node.  This is the name
> + * that would be returned by dev_name() if this device_node were part of a
> + * 'struct device'  It's ugly and hackish, but it works.
> + *
> + * The dev_name for such devices include the bus number and I2C address. For
> + * example, "cs4270.0-004f".
> + */
> +int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len)

This doesn't seem at all Freescale specific, it should be a generic
helper, and in fact there already is one - the machine driver can set
codec_of_node in the card structure to point to the device node and then
the core should figure out binding to the device for you.  If it doesn't
we should fix the core.
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From jason at lakedaemon.net  Mon Mar  5 09:51:50 2012
From: jason at lakedaemon.net (Jason)
Date: Mon, 5 Mar 2012 09:51:50 -0500
Subject: [GIT PULL v3] ARM: kirkwood: fdt: convert kirkwood init funcs
 to fdt
In-Reply-To: <201203051434.35132.arnd@arndb.de>
References: <20120305034113.GB5050@titan.lakedaemon.net>
 <20120305133242.GD5050@titan.lakedaemon.net>
 <201203051434.35132.arnd@arndb.de>
Message-ID: <20120305145150.GF5050@titan.lakedaemon.net>

On Mon, Mar 05, 2012 at 02:34:34PM +0000, Arnd Bergmann wrote:
> On Monday 05 March 2012, Jason wrote:
> > This is still bugging me.  If, say, orion_wdt.c is common to all of
> > plat-orion/ shouldn't it be in an 'orion.dtsi'?  With compatible =
> > "marvell,orion-wdt"?  Then, if hypothetically, kirkwood used the same
> > driver but had a small tweak, then kirkwood.dtsi would have
> > "marvell,kirkwood-wdt"?  Which would let the driver know that it needed
> > to apply the tweak because it was kirkwood.
> 
> Some drivers are common to all orion, but others are only used in some
> out of {orion5k,kirkwood,mv78xx0,dove}. You could of course have
> an orion.dtsi that is included in kirkwood.dtsi.

As Andrew just brought up, the drivers are common across all of them,
but the registers and irqs are different.  Which would seem to shoot
down the need for an orion.dtsi.

The registers/irqs are common across kirkwood, so the best place
probably is kirkwood.dtsi.

However, if they are placed in kirkwood.dtsi, having compatible =
"mrvl,88f6821-rtc" probably is not a good idea.  Not all kirkwoods have
the same dev_id.

> BTW, I just realized that the patches that Haojian Zhuang sent for
> pxa/mmp are using mrvl instead of marvell, and you should definitely
> be using the same identifier both both. By convention we use the
> stock ticker symbol as a unique identifier, which would be mrvl here.

Hehehe that was in the Manual, right?  ;-)

> > In this scenario, since kirkwood and dreamplug currently need no
> > modifications to the default wdt driver, they would just inherit
> > orion.dtsi's "marvell,orion-wdt", right?
> 
> I would still list both, so we are future-proof in case we need
> to modify the driver in the future but don't want to modify
> the device tree.

So, in kirkwood.dtsi, compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc";

and, drivers without tweaks would match "mrvl,orion-rtc".

> > On the driver side, since it currently has no subarch or board specific
> > tweaks, then it is only good for the generic case,
> > "marvell,orion-wdt", and thus should only match it for now.
> 
> Yes.

Okay.

thx,

Jason.


From jhovold at gmail.com  Mon Mar  5 10:03:51 2012
From: jhovold at gmail.com (Johan Hovold)
Date: Mon, 5 Mar 2012 16:03:51 +0100
Subject: [GIT PULL] ARM: OMAP: IRQ domain support for INTC
In-Reply-To: <4F54CCBD.2080802@ti.com>
References: <4F4BB0FB.3040308@ti.com> <20120228234837.GH18901@atomide.com>
 <4F4E4F1D.7020109@ti.com> <20120305135838.GA2108@localhost>
 <4F54CCBD.2080802@ti.com>
Message-ID: <20120305150351.GB2108@localhost>

On Mon, Mar 05, 2012 at 03:25:01PM +0100, Cousson, Benoit wrote:
> On 3/5/2012 2:58 PM, Johan Hovold wrote:
> > On Wed, Feb 29, 2012 at 05:15:25PM +0100, Cousson, Benoit wrote:
> >> On 2/29/2012 12:48 AM, Tony Lindgren wrote:
> >>> * Cousson, Benoit<b-cousson at ti.com>   [120227 08:04]:
> >>> Hmm, looks like this now produces the following warning at least on omap3:
> >>
> >> Yes, Rajendra has just reported that issue with linux-next.
> >
> > I'm getting the same warning and initialisation failure with 3.3-rc6 on
> > overo. Are these fixes queued up for 3.3 (and not just 3.4) somewhere?
> 
> It is under review, I posted the series last Friday:
> mfd: twl: Fix for irqdomain/next + SPARSE_IRQ + MMC card detect
> 
> It will be anyway material for 3.4 since it is in linux-next.

Yes, I noted that there was a fix against linux-next. My question was
whether any fix is planned for 3.3 as twl4030 is broken with SPARSE_IRQ
enabled.

Disabling SPARSE_IRQ will be the only workaround until 3.4 is out then?

Thanks,
Johan


From robherring2 at gmail.com  Mon Mar  5 10:07:00 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 05 Mar 2012 09:07:00 -0600
Subject: [PATCH v2 7/7] Document: devicetree: add OF documents for arch-mmp
In-Reply-To: <201203051446.14600.arnd@arndb.de>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
 <1330950111-30797-8-git-send-email-haojian.zhuang@marvell.com>
 <201203051446.14600.arnd@arndb.de>
Message-ID: <4F54D694.80808@gmail.com>

On 03/05/2012 08:46 AM, Arnd Bergmann wrote:
> On Monday 05 March 2012, Haojian Zhuang wrote:
>> Add OF support in Document/devicetree directory.
>>
>> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
> 
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> 
> One question for Benoit, Grant or Rob:
> 
>> +Required properties:
>> +- compatible: should be "mrvl,sa1100-rtc"
>> +- reg: physical base address of the controller and length of memory mapped
>> +  region.
>> +- interrupts: Should be two. The first interrupt number is the rtc alarm
>> +  interrupt and the second interrupt number is the rtc hz interrupt.
>> +- interrupt-names: Assign name of irq resource.
>> +
>> +Example:
>> +	rtc: rtc at d4010000 {
>> +		compatible = "mrvl,mmp-rtc";
>> +		reg = <0xd4010000 0x1000>;
>> +		interrupts = <5>, <6>;
>> +		interrupt-name = "rtc 1Hz", "rtc alarm";
>> +	};
> 
> When the binding for a device lists the interrupt-names property, should it
> also list the specific values for it? This one says that which ones they are,
> but I think we should actually mandate the exact string in the binding if
> we want to allow drivers to get the resource by its name.

Sounds good to me. Requiring documentation is a good way to discourage
its use. :)

Ideally we would discourage spaces in the names, but since the whole
point is using the existing names from Linux we can't really enforce that.

Rob


From paul.liu at linaro.org  Mon Mar  5 10:07:27 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Mon,  5 Mar 2012 23:07:27 +0800
Subject: [PATCH v8 1/2] mfd: Add anatop mfd driver
Message-ID: <1330960049-28170-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
Anatop provides regulators and thermal.
This driver handles the address space and the operation of the mfd device.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Venu Byravarasu <vbyravarasu at nvidia.com>
Cc: Peter Korsgaard <jacmet at sunsite.dk>
---
 drivers/mfd/Kconfig        |    8 +++
 drivers/mfd/Makefile       |    1 +
 drivers/mfd/anatop-mfd.c   |  142 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/anatop.h |   40 ++++++++++++
 4 files changed, 191 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mfd/anatop-mfd.c
 create mode 100644 include/linux/mfd/anatop.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index f147395..f7e2f61 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -830,6 +830,14 @@ config MFD_INTEL_MSIC
 	  Passage) chip. This chip embeds audio, battery, GPIO, etc.
 	  devices used in Intel Medfield platforms.
 
+config MFD_ANATOP
+	bool "Support for Freescale i.MX on-chip ANATOP controller"
+	depends on SOC_IMX6Q
+	help
+	  Select this option to enable Freescale i.MX on-chip ANATOP
+	  MFD controller. This controller embeds regulator and
+	  thermal devices for Freescale i.MX platforms.
+
 endmenu
 endif
 
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b953bab..8e11060 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -112,3 +112,4 @@ obj-$(CONFIG_TPS65911_COMPARATOR)	+= tps65911-comparator.o
 obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
 obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
 obj-$(CONFIG_MFD_S5M_CORE)	+= s5m-core.o s5m-irq.o
+obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
new file mode 100644
index 0000000..d9bc63c
--- /dev/null
+++ b/drivers/mfd/anatop-mfd.c
@@ -0,0 +1,142 @@
+/*
+ * Anatop MFD driver
+ *
+ * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ * Copyright (C) 2012 Linaro
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+
+u32 anatop_get_bits(struct anatop *adata, u32 addr, int bit_shift,
+		    int bit_width)
+{
+	u32 val, mask;
+
+	if (bit_width == 32)
+		mask = ~0;
+	else
+		mask = (1 << bit_width) - 1;
+
+	val = readl(adata->ioreg + addr);
+	val = (val >> bit_shift) & mask;
+
+	return val;
+}
+EXPORT_SYMBOL(anatop_get_bits);
+
+void anatop_set_bits(struct anatop *adata, u32 addr, int bit_shift,
+		     int bit_width, u32 data)
+{
+	u32 val, mask;
+
+	if (bit_width == 32)
+		mask = ~0;
+	else
+		mask = (1 << bit_width) - 1;
+
+	spin_lock(&adata->reglock);
+	val = readl(adata->ioreg + addr) & ~(mask << bit_shift);
+	writel((data << bit_shift) | val, adata->ioreg);
+	spin_unlock(&adata->reglock);
+}
+EXPORT_SYMBOL(anatop_set_bits);
+
+static const struct of_device_id of_anatop_subdevice_match[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ .compatible = "fsl,anatop-thermal", },
+	{ },
+};
+
+static int __devinit of_anatop_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	void *ioreg;
+	struct anatop *drvdata;
+
+	ioreg = of_iomap(np, 0);
+	if (!ioreg)
+		return -EADDRNOTAVAIL;
+	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+	if (!drvdata)
+		return -ENOMEM;
+	drvdata->ioreg = ioreg;
+	spin_lock_init(&drvdata->reglock);
+	platform_set_drvdata(pdev, drvdata);
+	of_platform_bus_probe(np, of_anatop_subdevice_match, dev);
+
+	return 0;
+}
+
+static int __devexit of_anatop_remove(struct platform_device *pdev)
+{
+	struct anatop *drvdata;
+	drvdata = platform_get_drvdata(pdev);
+	iounmap(drvdata->ioreg);
+	return 0;
+}
+
+static const struct of_device_id of_anatop_match[] = {
+	{ .compatible = "fsl,imx6q-anatop", },
+	{ },
+};
+
+static struct platform_driver anatop_of_driver = {
+	.driver = {
+		.name = "anatop-mfd",
+		.owner = THIS_MODULE,
+		.of_match_table = of_anatop_match,
+	},
+	.probe		= of_anatop_probe,
+	.remove		= of_anatop_remove,
+};
+
+static int __init anatop_init(void)
+{
+	return platform_driver_register(&anatop_of_driver);
+}
+postcore_initcall(anatop_init);
+
+static void __exit anatop_exit(void)
+{
+	platform_driver_unregister(&anatop_of_driver);
+}
+module_exit(anatop_exit);
+
+MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP MFD driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
new file mode 100644
index 0000000..22c1007
--- /dev/null
+++ b/include/linux/mfd/anatop.h
@@ -0,0 +1,40 @@
+/*
+ * anatop.h - Anatop MFD driver
+ *
+ *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ *  Copyright (C) 2012 Linaro
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_MFD_ANATOP_H
+#define __LINUX_MFD_ANATOP_H
+
+#include <linux/spinlock.h>
+
+/**
+ * anatop - MFD data
+ * @ioreg: ioremap register
+ * @reglock: spinlock for register read/write
+ */
+struct anatop {
+	void *ioreg;
+	spinlock_t reglock;
+};
+
+extern u32 anatop_get_bits(struct anatop *, u32, int, int);
+extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
+
+#endif /*  __LINUX_MFD_ANATOP_H */
-- 
1.7.9.1



From paul.liu at linaro.org  Mon Mar  5 10:07:28 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Mon,  5 Mar 2012 23:07:28 +0800
Subject: [PATCH v8 2/2] Regulator: Add Anatop regulator driver
In-Reply-To: <1330960049-28170-1-git-send-email-paul.liu@linaro.org>
References: <1330960049-28170-1-git-send-email-paul.liu@linaro.org>
Message-ID: <1330960049-28170-2-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.

Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Liam Girdwood <lrg at ti.com>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 .../bindings/regulator/anatop-regulator.txt        |   28 +++
 drivers/regulator/Kconfig                          |    8 +
 drivers/regulator/Makefile                         |    1 +
 drivers/regulator/anatop-regulator.c               |  231 ++++++++++++++++++++
 4 files changed, 268 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.txt
 create mode 100644 drivers/regulator/anatop-regulator.c

diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
new file mode 100644
index 0000000..500463e
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -0,0 +1,28 @@
+Anatop Voltage regulators
+
+Required properties:
+- compatible: Must be "fsl,anatop-regulator"
+- vol-bit-shift: Bit shift for the register
+- vol-bit-width: Number of bits used in the register
+- min-bit-val: Minimum value of this register
+- min-voltage: Minimum voltage of this regulator
+- max-voltage: Maximum voltage of this regulator
+
+Any property defined as part of the core regulator
+binding, defined in regulator.txt, can also be used.
+
+Example:
+
+	reg_vddpu: regulator-vddpu at 140 {
+		compatible = "fsl,anatop-regulator";
+		regulator-name = "vddpu";
+		regulator-min-microvolt = <725000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-always-on;
+		reg = <0x140>;
+		vol-bit-shift = <9>;
+		vol-bit-width = <5>;
+		min-bit-val = <1>;
+		min-voltage = <725000>;
+		max-voltage = <1300000>;
+	};
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 7a61b17..5366991 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -335,5 +335,13 @@ config REGULATOR_AAT2870
 	  If you have a AnalogicTech AAT2870 say Y to enable the
 	  regulator driver.
 
+config REGULATOR_ANATOP
+	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
+	depends on MFD_ANATOP
+	help
+	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
+	  regulators. It is recommended that this option be
+	  enabled on i.MX6 platform.
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 503bac8..8440871 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -48,5 +48,6 @@ obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
 obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
 obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
 obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
+obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
new file mode 100644
index 0000000..e9917c6
--- /dev/null
+++ b/drivers/regulator/anatop-regulator.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+
+struct anatop_regulator {
+	const char *name;
+	u32 control_reg;
+	struct anatop *mfd;
+	int vol_bit_shift;
+	int vol_bit_width;
+	int min_bit_val;
+	int min_voltage;
+	int max_voltage;
+	struct regulator_desc rdesc;
+	struct regulator_init_data *initdata;
+};
+
+static int anatop_set_voltage(struct regulator_dev *reg, int min_uV,
+				  int max_uV, unsigned *selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	u32 val, sel;
+	int uv;
+
+	uv = min_uV;
+	dev_dbg(&reg->dev, "%s: uv %d, min %d, max %d\n", __func__,
+		uv, anatop_reg->min_voltage,
+		anatop_reg->max_voltage);
+
+	if (uv < anatop_reg->min_voltage) {
+		if (max_uV > anatop_reg->min_voltage)
+			uv = anatop_reg->min_voltage;
+		else
+			return -EINVAL;
+	}
+
+	if (anatop_reg->control_reg) {
+		sel = (uv - anatop_reg->min_voltage) / 25000;
+		if (sel * 25000 + anatop_reg->min_voltage
+		    > anatop_reg->max_voltage)
+			return -EINVAL;
+		val = anatop_reg->min_bit_val + sel;
+		*selector = sel;
+		dev_dbg(&reg->dev, "%s: calculated val %d\n", __func__, val);
+		anatop_set_bits(anatop_reg->mfd,
+				anatop_reg->control_reg,
+				anatop_reg->vol_bit_shift,
+				anatop_reg->vol_bit_width,
+				val);
+		return 0;
+	} else {
+		return -ENOTSUPP;
+	}
+}
+
+static int anatop_get_voltage_sel(struct regulator_dev *reg)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int selector;
+
+	if (anatop_reg->control_reg) {
+		u32 val = anatop_get_bits(anatop_reg->mfd,
+					  anatop_reg->control_reg,
+					  anatop_reg->vol_bit_shift,
+					  anatop_reg->vol_bit_width);
+		selector = val - anatop_reg->min_bit_val;
+		return selector;
+	} else {
+		return -ENOTSUPP;
+	}
+}
+
+static int anatop_list_voltage(struct regulator_dev *reg, unsigned selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int uv;
+
+	uv = anatop_reg->min_voltage + selector * 25000;
+	dev_dbg(&reg->dev, "vddio = %d, selector = %u\n", uv, selector);
+
+	return uv;
+}
+
+static struct regulator_ops anatop_rops = {
+	.set_voltage     = anatop_set_voltage,
+	.get_voltage_sel = anatop_get_voltage_sel,
+	.list_voltage    = anatop_list_voltage,
+};
+
+static int __devinit anatop_regulator_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct regulator_desc *rdesc;
+	struct regulator_dev *rdev;
+	struct anatop_regulator *sreg;
+	struct regulator_init_data *initdata;
+	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
+	int ret = 0;
+
+	initdata = of_get_regulator_init_data(dev, np);
+	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
+	if (!sreg)
+		return -ENOMEM;
+	sreg->initdata = initdata;
+	sreg->name = kstrdup(of_get_property(np, "regulator-name", NULL),
+			     GFP_KERNEL);
+	rdesc = &sreg->rdesc;
+	memset(rdesc, 0, sizeof(*rdesc));
+	rdesc->name = sreg->name;
+	rdesc->ops = &anatop_rops;
+	rdesc->type = REGULATOR_VOLTAGE;
+	rdesc->owner = THIS_MODULE;
+	sreg->mfd = anatopmfd;
+	if (of_property_read_u32(np, "reg", &sreg->control_reg)) {
+		dev_err(&pdev->dev, "no reg property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "vol-bit-width", &sreg->vol_bit_width)) {
+		dev_err(&pdev->dev, "no vol-bit-width property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "vol-bit-shift", &sreg->vol_bit_shift)) {
+		dev_err(&pdev->dev, "no vol-bit-shift property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "min-bit-val", &sreg->min_bit_val)) {
+		dev_err(&pdev->dev, "no min-bit-val property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "min-voltage", &sreg->min_voltage)) {
+		dev_err(&pdev->dev, "no min-voltage property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "max-voltage", &sreg->max_voltage)) {
+		dev_err(&pdev->dev, "no max-voltage property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+
+	/* register regulator */
+	rdev = regulator_register(rdesc, &pdev->dev,
+				  initdata, sreg, pdev->dev.of_node);
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			rdesc->name);
+		ret = PTR_ERR(rdev);
+		goto anatop_probe_end;
+	}
+
+	platform_set_drvdata(pdev, rdev);
+
+anatop_probe_end:
+	if (ret != 0 && sreg->name)
+		kfree(sreg->name);
+	return ret;
+}
+
+static int __devexit anatop_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
+	kfree(sreg->name);
+	regulator_unregister(rdev);
+	return 0;
+}
+
+static struct of_device_id __devinitdata of_anatop_regulator_match_tbl[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ /* end */ }
+};
+
+static struct platform_driver anatop_regulator = {
+	.driver = {
+		.name	= "anatop_regulator",
+		.owner  = THIS_MODULE,
+		.of_match_table = of_anatop_regulator_match_tbl,
+	},
+	.probe	= anatop_regulator_probe,
+	.remove	= anatop_regulator_remove,
+};
+
+static int __init anatop_regulator_init(void)
+{
+	return platform_driver_register(&anatop_regulator);
+}
+postcore_initcall(anatop_regulator_init);
+
+static void __exit anatop_regulator_exit(void)
+{
+	platform_driver_unregister(&anatop_regulator);
+}
+module_exit(anatop_regulator_exit);
+
+MODULE_AUTHOR("Nancy Chen <Nancy.Chen at freescale.com>");
+MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP Regulator driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.1



From b-cousson at ti.com  Mon Mar  5 10:08:37 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 5 Mar 2012 16:08:37 +0100
Subject: [PATCH v2 7/7] Document: devicetree: add OF documents for arch-mmp
In-Reply-To: <201203051446.14600.arnd@arndb.de>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
 <1330950111-30797-8-git-send-email-haojian.zhuang@marvell.com>
 <201203051446.14600.arnd@arndb.de>
Message-ID: <4F54D6F5.8050805@ti.com>

On 3/5/2012 3:46 PM, Arnd Bergmann wrote:
> On Monday 05 March 2012, Haojian Zhuang wrote:
>> Add OF support in Document/devicetree directory.
>>
>> Signed-off-by: Haojian Zhuang<haojian.zhuang at marvell.com>
>
> Acked-by: Arnd Bergmann<arnd at arndb.de>
>
> One question for Benoit, Grant or Rob:
>
>> +Required properties:
>> +- compatible: should be "mrvl,sa1100-rtc"
>> +- reg: physical base address of the controller and length of memory mapped
>> +  region.
>> +- interrupts: Should be two. The first interrupt number is the rtc alarm
>> +  interrupt and the second interrupt number is the rtc hz interrupt.
>> +- interrupt-names: Assign name of irq resource.
>> +
>> +Example:
>> +	rtc: rtc at d4010000 {
>> +		compatible = "mrvl,mmp-rtc";
>> +		reg =<0xd4010000 0x1000>;
>> +		interrupts =<5>,<6>;
>> +		interrupt-name = "rtc 1Hz", "rtc alarm";
>> +	};
>
> When the binding for a device lists the interrupt-names property, should it
> also list the specific values for it? This one says that which ones they are,
> but I think we should actually mandate the exact string in the binding if
> we want to allow drivers to get the resource by its name.

Yes, indeed. The names are not some random strings, the driver will use 
get_resource_by_name and expect the name to be aligned with HW 
documentation and thus should be well documented in the binding.

Regards,
Benoit


From b-cousson at ti.com  Mon Mar  5 10:19:26 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 5 Mar 2012 16:19:26 +0100
Subject: [GIT PULL] ARM: OMAP: IRQ domain support for INTC
In-Reply-To: <20120305150351.GB2108@localhost>
References: <4F4BB0FB.3040308@ti.com> <20120228234837.GH18901@atomide.com>
 <4F4E4F1D.7020109@ti.com> <20120305135838.GA2108@localhost>
 <4F54CCBD.2080802@ti.com> <20120305150351.GB2108@localhost>
Message-ID: <4F54D97E.4070805@ti.com>

On 3/5/2012 4:03 PM, Johan Hovold wrote:
> On Mon, Mar 05, 2012 at 03:25:01PM +0100, Cousson, Benoit wrote:
>> On 3/5/2012 2:58 PM, Johan Hovold wrote:
>>> On Wed, Feb 29, 2012 at 05:15:25PM +0100, Cousson, Benoit wrote:
>>>> On 2/29/2012 12:48 AM, Tony Lindgren wrote:
>>>>> * Cousson, Benoit<b-cousson at ti.com>    [120227 08:04]:
>>>>> Hmm, looks like this now produces the following warning at least on omap3:
>>>>
>>>> Yes, Rajendra has just reported that issue with linux-next.
>>>
>>> I'm getting the same warning and initialisation failure with 3.3-rc6 on
>>> overo. Are these fixes queued up for 3.3 (and not just 3.4) somewhere?
>>
>> It is under review, I posted the series last Friday:
>> mfd: twl: Fix for irqdomain/next + SPARSE_IRQ + MMC card detect
>>
>> It will be anyway material for 3.4 since it is in linux-next.
>
> Yes, I noted that there was a fix against linux-next. My question was
> whether any fix is planned for 3.3 as twl4030 is broken with SPARSE_IRQ
> enabled.
>
> Disabling SPARSE_IRQ will be the only workaround until 3.4 is out then?

Mmm, but is SPARSE_IRQ used to work before on OMAP3?

Benoit


From khilman at ti.com  Mon Mar  5 10:21:39 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 05 Mar 2012 07:21:39 -0800
Subject: [PATCH] ARM: OMAP2+: omap_device: call all suspend,
 resume callbacks when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set
In-Reply-To: <alpine.DEB.2.00.1203031314050.10611@utopia.booyaka.com> (Paul
 Walmsley's message of "Sat, 3 Mar 2012 13:15:33 -0700 (MST)")
References: <alpine.DEB.2.00.1203031314050.10611@utopia.booyaka.com>
Message-ID: <877gyzoyyk.fsf@ti.com>

Paul Walmsley <paul at pwsan.com> writes:

> During system suspend, when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set on
> an omap_device, call the corresponding driver's ->suspend() and
> ->suspend_noirq() callbacks (if present).  Similarly, during resume,
> the driver's ->resume() and ->resume_noirq() callbacks must both be
> called, if present.  (The previous code only called ->suspend_noirq()
> and ->resume_noirq().)
>
> If all of these callbacks aren't called, some important driver
> suspend/resume code may not get executed.
>
> In current mainline, the bug fixed by this patch is only a problem
> under the following conditions:
>
> - the kernel is running on an OMAP4
>
> - an OMAP UART is used as a console
>
> - the kernel command line parameter 'no_console_suspend' is specified
>
> - and the system enters suspend ("echo mem > /sys/power/state").
>
> Under this combined circumstance, the system cannot be awakened via
> the serial port after commit be4b0281956c5cae4f63f31f11d07625a6988766c
> ("tty: serial: OMAP: block idle while the UART is transferring data in
> PIO mode").  This is because the OMAP UART driver's ->suspend()
> callback is never called.  The ->suspend() callback would have called
> uart_suspend_port() which in turn would call enable_irq_wake().  Since
> enable_irq_wake() isn't called for the UART's IRQ, check_wakeup_irqs()
> would mask off the UART IRQ in the GIC.
>
> On v3.3 kernels prior to the above commit, serial resume from suspend
> presumably occurred via the PRCM interrupt.  The UART was in
> smart-idle mode, so it was able to send a PRCM wakeup which in turn
> would be converted into a PRCM interrupt to the GIC, waking up the
> kernel.  But after the above commit, when the system is suspended in
> the middle of a UART transmit, the UART IP block would be in no-idle
> mode.  In no-idle mode, the UART won't generate wakeups to the PRCM
> when incoming characters are received; only GIC interrupts.  But since
> the UART driver's ->suspend() callback is never called,
> uart_suspend_port() and enable_irq_wake() is never called; so the UART
> interrupt is masked by check_wakeup_irqs() and the UART can't wake up
> the MPU.
>
> The remaining mechanism that could have awakened the system would have
> been I/O chain wakeups.  These wouldn't be active because the console
> UART's clocks are never disabled when no_console_suspend is used,
> preventing the full chip from idling.  Also, current mainline doesn't
> yet support full chip idle states for OMAP4, so I/O chain wakeups are
> not enabled.
>
> This patch is the result of a collaboration.  John Stultz
> <johnstul at us.ibm.com> and Andy Green <andy.green at linaro.org> reported
> the serial wakeup problem that led to the discovery of this problem.
> Kevin Hilman <khilman at ti.com> narrowed the problem down to the use of
> no_console_suspend.
>
> Signed-off-by: Paul Walmsley <paul at pwsan.com>
> Cc: John Stultz <johnstul at us.ibm.com>
> Cc: Andy Green <andy.green at linaro.org>
> Cc: Kevin Hilman <khilman at ti.com>

Looks right.

Acked-by: Kevin Hilman <khilman at ti.com>

Tony, this fix is needed for v3.3.

Kevin


From grant.likely at secretlab.ca  Mon Mar  5 10:36:48 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 5 Mar 2012 08:36:48 -0700
Subject: [RFC PATCH] of: DMA helpers: manage generic requests specification
In-Reply-To: <1330527248-4350-1-git-send-email-nicolas.ferre@atmel.com>
References: <4F22DEF2.5000807@ti.com>
 <1330527248-4350-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <20120305153648.GG27229@ponder.secretlab.ca>

On Wed, Feb 29, 2012 at 03:54:08PM +0100, Nicolas Ferre wrote:
> By making DMA controllers register a generic translation
> function, we allow the management of any type of DMA requests
> specification.
> The void * output of an of_dma_xlate() function that will be implemented
> by the DMA controller can carry any type of "dma-request" argument.
> 
> The DMA client will search its associated DMA controller in the list
> and call the registered of_dam_xlate() function to retrieve the
> request values.
> 
> One simple xlate function is provided for the "single number" type
> of request biding.
> 
> This implementation is independent from dmaengine so it can also be
> used by legacy drivers.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Stephen Warren <swarren at nvidia.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Rob Herring <rob.herring at calxeda.com>
> ---
> Hi all,
> 
> Here are my thoughts about the DMA helpers for device tree.
> This patch goes on top of Benoit's ones. My goal was to keep this separated
> from any DMA infrastructure (dmaengine not needed, nor any other DMA
> implementation).
> 
> It is to keep the ball rolling, so do not hesitate to comment.
> 
> Best regards,
> 
> 
>  Documentation/devicetree/bindings/dma/dma.txt |   29 +++--
>  drivers/of/dma.c                              |  161 ++++++++++++++++++++++---
>  include/linux/of_dma.h                        |   33 +++++-
>  3 files changed, 186 insertions(+), 37 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/dma.txt b/Documentation/devicetree/bindings/dma/dma.txt
> index 7f2a301..c49e98d 100644
> --- a/Documentation/devicetree/bindings/dma/dma.txt
> +++ b/Documentation/devicetree/bindings/dma/dma.txt
> @@ -6,9 +6,8 @@ DMA request line that goes from an IP to a DMA controller.
>  
>  * DMA controller
>  
> -Required properties:
> -    - dma-controller: Mark the device as a DMA controller
> -    - #dma-cells: Number of cell for each DMA line, must be one.
> +Required property:
> +    - #dma-cells: Number of cells for each DMA line.
>  
>  
>  Example:
> @@ -17,7 +16,6 @@ Example:
>  		compatible = "ti,sdma-omap4"
>  		reg = <0x48000000 0x1000>;
>  		interrupts = <12>;
> -        dma-controller;
>  		#dma-cells = <1>;
>  	};
>  
> @@ -25,20 +23,23 @@ Example:
>  
>  * DMA client
>  
> -Client drivers should specify the DMA request numbers using a phandle to
> -the controller + the DMA request number on that controller.
> +Client drivers should specify the DMA request property using a phandle to
> +the controller. If needed, the DMA request identity on that controller is then
> +added followed by optional request specifications.
>  
> -Required properties:
> -    - dma-request: List of pair phandle + dma-request per line
> +Required property:
> +    - dma-request: List of phandle + dma-request + request specifications,
> +      one group per request "line".
> +Optional property:
>      - dma-request-names: list of strings in the same order as the dma-request
>        in the dma-request property.
>  
>  
>  Example:
>  
> -    i2c1: i2c at 1 {
> -        ...
> -        dma-request = <&sdma 2 &sdma 3>;
> -        dma-request-names = "tx", "rx";
> -        ...
> -    };
> +	i2c1: i2c at 1 {
> +		...
> +		dma-request = <&sdma 2 &sdma 3>;
> +		dma-request-names = "tx", "rx";
> +		...
> +	};
> diff --git a/drivers/of/dma.c b/drivers/of/dma.c
> index d4927e2..e0c6fd9 100644
> --- a/drivers/of/dma.c
> +++ b/drivers/of/dma.c
> @@ -13,41 +13,145 @@
>  #include <linux/device.h>
>  #include <linux/err.h>
>  #include <linux/module.h>
> +#include <linux/rculist.h>
> +#include <linux/slab.h>
>  #include <linux/of.h>
>  #include <linux/of_dma.h>
>  
> +static LIST_HEAD(of_dma_list);
> +
> +/**
> + * of_dma_find_controller() - Find a DMA controller in DT DMA helpers list
> + * @np:		device node of DMA controller
> + */
> +static struct of_dma *of_dma_find_controller(struct device_node *np)
> +{
> +	struct of_dma	*ofdma;
> +
> +	list_for_each_entry_rcu(ofdma, &of_dma_list, of_dma_controllers) {
> +		if (ofdma->of_node == np)
> +			return ofdma;
> +	}
> +
> +	return NULL;
> +}
> +
>  /**
> - * of_get_dma_request() - Get a DMA request number and dma-controller node
> + * of_dma_controller_register() - Register a DMA controller to DT DMA helpers
> + * @np:			device node of DMA controller
> + * @of_dma_xlate:	generic translation function which converts a phandle
> + *			arguments list into a generic output value
> + *
> + * Returns 0 on success or appropriate errno value on error.
> + *
> + * If #dma-cells is not specified in DMA controller device tree node, we assume
> + * that the DMA controller phandle will come without argument.
> + *
> + * Allocated memory sould be freed with apropriate of_dma_controller_free()
> + * call.
> + */
> +int of_dma_controller_register(struct device_node *np,
> +			int (*of_dma_xlate)(struct of_phandle_args *, void *))
> +{
> +	struct of_dma	*ofdma;
> +	int		*nbcells;
> +
> +	if (!np || !of_dma_xlate) {
> +		pr_err("%s: not enouth information provided\n", __func__);
> +		return -EINVAL;
> +	}
> +
> +	ofdma = kzalloc(sizeof(*ofdma), GFP_KERNEL);
> +	if (!ofdma)
> +		return -ENOMEM;
> +
> +	nbcells = (int *)of_get_property(np, "#dma-cells", NULL);

No cast required; but nbcells should be a (const __be32 *) instead of an int*.

> +	if (!nbcells)
> +		/*
> +		 * no #dma-cells properties: assume no argument to
> +		 * dma-request property on slave side
> +		 */
> +		ofdma->of_dma_n_cells = 0;
> +	else
> +		ofdma->of_dma_n_cells = be32_to_cpup(nbcells);
> +
> +	ofdma->of_node = np;
> +	ofdma->of_dma_xlate = of_dma_xlate;
> +
> +	/* Now queue of_dma controller structure in list */
> +	list_add_tail_rcu(&ofdma->of_dma_controllers, &of_dma_list);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(of_dma_controller_register);

EXPORT_SYMBOL_GPL

> +
> +/**
> + * of_dma_controller_free() - Remove a DMA controller from DT DMA helpers list
> + * @np:		device node of DMA controller
> + *
> + * Memory allocated by of_dma_controller_register() is freed here.
> + */
> +void of_dma_controller_free(struct device_node *np)
> +{
> +	struct of_dma	*ofdma;
> +
> +	ofdma = of_dma_find_controller(np);
> +	if (ofdma) {
> +		list_del_rcu(&ofdma->of_dma_controllers);
> +		kfree(ofdma);
> +	}
> +}
> +EXPORT_SYMBOL(of_dma_controller_free);
> +
> +/**
> + * of_get_dma_request() - Get the associated DMA request data
>   * @np:		device node to get DMA request from
> - * @propname:	property name containing DMA specifier(s)
>   * @index:	index of the DMA request
> - * @ctrl_np:	a device_node pointer to fill in
> + * @out_data:	a output that can be filled in by the of_dma_xlate() function
>   *
> - * Returns DMA number along to the dma controller node, or one of the errno
> - * value on the error condition. If @ctrl_np is not NULL the function also
> - * fills in the DMA controller device_node pointer.
> + * Returns return value of of_dma_xlate() and fills out_data (if provided).
> + * On error returns the appropriate errno value.
>   */
>  int of_get_dma_request(struct device_node *np, int index,
> -		       struct device_node **ctrl_np)
> +		       void *out_data)
>  {
> -	int ret = -EINVAL;
> -	struct of_phandle_args dma_spec;
> +	struct of_phandle_args	dma_spec;
> +	struct of_dma		*ofdma;
> +	int			ret;
>  
>  	ret = of_parse_phandle_with_args(np, "dma-request", "#dma-cells",
>  					 index, &dma_spec);
>  	if (ret) {
> -		pr_debug("%s: can't parse dma property\n", __func__);
> +		pr_err("%s: can't parse dma property\n", np->full_name);
>  		goto err0;
>  	}
>  
> -	if (dma_spec.args_count > 0)
> -		ret = dma_spec.args[0];
> +	if (list_empty(&of_dma_list)) {
> +		pr_debug("%s: empty DMA controller list\n",
> +			 np->full_name);
> +		ret = -ENOENT;
> +		goto err1;
> +	}
>  
> -	if (ctrl_np)
> -		*ctrl_np = dma_spec.np;
> -	else
> -		of_node_put(dma_spec.np);
> +	ofdma = of_dma_find_controller(dma_spec.np);
> +	if (!ofdma) {
> +		pr_debug("%s: DMA controller %s isn't registered\n",
> +			 np->full_name, dma_spec.np->full_name);
> +		ret = -ENODEV;
> +		goto err1;
> +	}
>  
> +	if (dma_spec.args_count != ofdma->of_dma_n_cells) {
> +		pr_debug("%s: wrong #dma-cells for %s\n",
> +			 np->full_name, dma_spec.np->full_name);
> +		ret = -EINVAL;
> +		goto err1;
> +	}
> +
> +	ret = ofdma->of_dma_xlate(&dma_spec, out_data);
> +
> +err1:
> +	of_node_put(dma_spec.np);
>  err0:
>  	pr_debug("%s exited with status %d\n", __func__, ret);
>  	return ret;
> @@ -55,6 +159,24 @@ err0:
>  EXPORT_SYMBOL(of_get_dma_request);
>  
>  /**
> + * of_dma_xlate_onenumbercell() - Generic DMA xlate for direct one cell bindings
> + *
> + * Device Tree DMA translation function which works with one cell bindings
> + * where the cell values map directly to the hardware request number understood
> + * by the DMA controller.
> + */
> +int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec, void *req_nbr)
> +{
> +	if (!dma_spec)
> +		return -EINVAL;
> +	if (WARN_ON(dma_spec->args_count != 1))
> +		return -EINVAL;
> +	*(int *)req_nbr = dma_spec->args[0];
> +	return 0;
> +}
> +EXPORT_SYMBOL(of_dma_xlate_onenumbercell);
> +
> +/**
>   * of_dma_count - Count DMA requests for a device
>   * @np:		device node to count DMAs for
>   *
> @@ -105,13 +227,14 @@ int of_dma_to_resource(struct device_node *dev, int index, struct resource *r)
>  {
>  	const char *name = NULL;
>  	int dma;
> +	int ret;
>  
>  	if (!r)
>  		return -EINVAL;
>  
> -	dma = of_get_dma_request(dev, index, NULL);
> -	if (dma < 0)
> -		return dma;
> +	ret = of_get_dma_request(dev, index, &dma);
> +	if (ret < 0)
> +		return ret;
>  
>  	/*
>  	 * Get optional "dma-request-names" property to add a name
> diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
> index 575163d..fbf98de 100644
> --- a/include/linux/of_dma.h
> +++ b/include/linux/of_dma.h
> @@ -17,18 +17,38 @@
>  
>  struct device_node;
>  
> -#ifdef CONFIG_OF_GPIO
> +#ifdef CONFIG_OF_DMA
>  
> +struct of_dma {
> +	struct list_head of_dma_controllers;
> +	struct device_node *of_node;
> +	int of_dma_n_cells;
> +	int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
> +};

The api makes struct of_dma private; so this should be moved to the .c
file.

Otherwise, this looks okay to me.

g.


> +
> +extern int of_dma_controller_register(struct device_node *np,
> +			int (*of_dma_xlate)(struct of_phandle_args *, void *));
> +extern void of_dma_controller_free(struct device_node *np);
>  extern int of_get_dma_request(struct device_node *np, int index,
> -		       struct device_node **ctrl_np);
> +			      void *out_data);
>  extern unsigned int of_dma_count(struct device_node *np);
>  extern int of_dma_to_resource(struct device_node *dev, int index,
>  			      struct resource *r);
>  
> +extern int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
> +				      void *req_nbr);
>  #else /* CONFIG_OF_DMA */
>  
> -static int of_get_dma_request(struct device_node *np, int index,
> -			      struct device_node **ctrl_np);
> +static int of_dma_controller_register(struct device_node *np,
> +			int (*of_dma_xlate)(struct of_phandle_args *, void *))
> +{
> +	return -ENOSYS;
> +}
> +
> +static void of_dma_controller_free(struct device_node *np) {}
> +
> +extern int of_get_dma_request(struct device_node *np, int index,
> +			      void *out_data)
>  {
>  	return -ENOSYS;
>  }
> @@ -44,6 +64,11 @@ static int of_dma_to_resource(struct device_node *dev, int index,
>  	return -ENOSYS;
>  }
>  
> +static int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
> +				      void *req_nbr)
> +{
> +	return -ENOSYS;
> +}
>  #endif /* CONFIG_OF_DMA */
>  
>  #endif /* __LINUX_OF_DMA_H */
> -- 
> 1.7.9
> 


From timur at freescale.com  Mon Mar  5 10:48:53 2012
From: timur at freescale.com (Timur Tabi)
Date: Mon, 5 Mar 2012 09:48:53 -0600
Subject: [PATCH v2 11/17] ASoC: fsl: create fsl_utils to accommodate the
 common functions
In-Reply-To: <20120305144920.GR3224@opensource.wolfsonmicro.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-12-git-send-email-shawn.guo@linaro.org>
 <20120305144920.GR3224@opensource.wolfsonmicro.com>
Message-ID: <4F54E065.8060905@freescale.com>

Mark Brown wrote:
> This doesn't seem at all Freescale specific, it should be a generic
> helper, and in fact there already is one - the machine driver can set
> codec_of_node in the card structure to point to the device node and then
> the core should figure out binding to the device for you.  If it doesn't
> we should fix the core.

Can we do that in another patch set, so that it doesn't hold up Shawn's
work?  All this patch does is move the code from one file to another, so
it's not like he's adding a feature incorrectly.

-- 
Timur Tabi
Linux kernel developer at Freescale



From shijie8 at gmail.com  Tue Mar  6 00:07:16 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Tue,  6 Mar 2012 00:07:16 -0500
Subject: [PATCH] ARM: move mem_type's real definition to asm/mach/map.h
Message-ID: <1331010436-31576-1-git-send-email-shijie8@gmail.com>

If we use the mem_type in the driver. We will meet the compiler error:
"error: dereferencing pointer to incomplete type"

Move mem_type's real definition to asm/mach/map.h to fix it.

Signed-off-by: Huang Shijie <shijie8 at gmail.com>
---
 arch/arm/include/asm/mach/map.h |    8 +++++++-
 arch/arm/mm/mm.h                |    7 +------
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index b36f365..a5ee07d 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -34,7 +34,13 @@ struct map_desc {
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
 
-struct mem_type;
+struct mem_type {
+	pteval_t prot_pte;
+	pmdval_t prot_l1;
+	pmdval_t prot_sect;
+	unsigned int domain;
+};
+
 extern const struct mem_type *get_mem_type(unsigned int type);
 /*
  * external interface to remap single page with appropriate type
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 70f6d3ea..1930bc9 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -10,12 +10,7 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
 	return pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
 }
 
-struct mem_type {
-	pteval_t prot_pte;
-	pmdval_t prot_l1;
-	pmdval_t prot_sect;
-	unsigned int domain;
-};
+struct mem_type;
 
 const struct mem_type *get_mem_type(unsigned int type);
 
-- 
1.7.4.4



From jkrzyszt at tis.icnet.pl  Mon Mar  5 11:05:09 2012
From: jkrzyszt at tis.icnet.pl (Janusz Krzysztofik)
Date: Mon,  5 Mar 2012 17:05:09 +0100
Subject: [PATCH v3 0/3] Amstrad Delta: access MODEM_RESET GPIO pin over a
 regulator
Message-ID: <1330963512-20413-1-git-send-email-jkrzyszt@tis.icnet.pl>

The Amstrad Delta on-board latch2 bit named MODEM_NRESET, now available
as a GPIO pin AMS_DELTA_GPIO_PIN_NMODEM_RESET, is used to power up/down
(bring into/out of a reset state) two distinct on-board devices
simultaneously: the modem, and the voice codec. As a consequence, that
bit is, or can be, manipulated concurrently by two drivers, or their
platform provided hooks.

Instead of updating those drivers to use the gpiolib API as a new method
of controlling the MODEM_NRESET pin state, like it was done to other
drivers accessing latch2 pins, and still being vulnerable to potential
concurrency conflicts, or trying to solve that sharing issue with a
custom piece of code, set up a fixed regulator device on top of that
GPIO pin and update both drivers to manipulate that regulator, not the
GPIO pin directly.

This is v3 of this series, with Mark's Ack for ASoC subtree touching
changes already collected, rebased on top of linux-omap/ams-delta tip,
commit da564a05b3aefe403062411b67d64b7e992718f7.

There were initially 4 patches in the series, but patch 2/4, "ASoC:
cx20442: add bias control over a platform provided regulator", has been
since then applied by Liam to the ASoC tree (thanks!) and is already
present in mainline (commit f75a8ff67d161b5166a2c2360bb2ffaefd5eb853),
hence omitted from this submission.

v2 -> v3 changes:
* fix section mismatch issue present in previous versions of patch 1/3.

v2 changes against initial version:
* in both the codec and the modem callbacks, don't track the regulator
  enable/disable state, compare new target bias level (the codec case)
  or power state (the modem case) with the old value instead; thanks to
  Mark Brown who suggested this solution,
* a few other minor changes, mostly stylistic.

Janusz Krzysztofik (3):
  ARM: OMAP1: ams-delta: set up regulator over modem reset GPIO pin
  ARM: OMAP1: ams-delta: update the modem to use regulator API
  ASoC: OMAP: ams-delta: drop .set_bias_level callback

 arch/arm/mach-omap1/Kconfig                       |    2 +
 arch/arm/mach-omap1/board-ams-delta.c             |   94 +++++++++++++++++++--
 arch/arm/plat-omap/include/plat/board-ams-delta.h |    1 -
 sound/soc/omap/ams-delta.c                        |   32 -------
 4 files changed, 87 insertions(+), 42 deletions(-)

-- 
1.7.3.4



From jkrzyszt at tis.icnet.pl  Mon Mar  5 11:05:10 2012
From: jkrzyszt at tis.icnet.pl (Janusz Krzysztofik)
Date: Mon,  5 Mar 2012 17:05:10 +0100
Subject: [PATCH v3 1/3] ARM: OMAP1: ams-delta: set up regulator over modem
 reset GPIO pin
In-Reply-To: <1330963512-20413-1-git-send-email-jkrzyszt@tis.icnet.pl>
References: <1330963512-20413-1-git-send-email-jkrzyszt@tis.icnet.pl>
Message-ID: <1330963512-20413-2-git-send-email-jkrzyszt@tis.icnet.pl>

The Amstrad Delta on-board latch2 bit named MODEM_NRESET, now available
as a GPIO pin AMS_DELTA_GPIO_PIN_NMODEM_RESET, is used to power up/down
(bring into/out of a reset state) two distinct on-board devices
simultaneously: the modem, and the voice codec. As a consequence, that
bit is, or can be, manipulated concurrently by two drivers, or their
platform provided hooks.

Instead of updating those drivers to use the gpiolib API as a new method
of controlling the MODEM_NRESET pin state, like it was done to other
drivers accessing latch2 pins, and still being vulnerable to potential
concurrency conflicts, or trying to solve that sharing issue with a
custom piece of code, set up a fixed regulator device on top of that
GPIO pin, with the intention of updating both drivers to manipulate that
regulator, not the GPIO pin directly.

Before the ASoC driver is updated and the modem platform data expanded
with a power management callback for switching its power, the
ams_delta_latch_write() function, which still provides the old API for
accessing latch2 functionality from not updated drivers, is modified to
toggle the regulator instead of the MODEM_NRESET GPIO pin.  A helper
function provided for balancing the regulator enable/disable operations,
together with the consumer data needed for tracking the regulator state,
will be removed once the drivers are updated.

Depends on patch series "ARM: OMAP1: ams-delta: replace custom I/O with
GPIO".

Signed-off-by: Janusz Krzysztofik <jkrzyszt at tis.icnet.pl>
---
v2 -> v3 changes:
* fix section mismatch isue.

Changes against initial version:
* rename consumer setup elements to match their final, modem only
  related purpose,
* initialize the regulator pointer and mutex before first use, then
  omit testing that pointer against NULL value

 arch/arm/mach-omap1/Kconfig           |    2 +
 arch/arm/mach-omap1/board-ams-delta.c |  104 +++++++++++++++++++++++++++++++--
 2 files changed, 100 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 5b1edba..4b6a774 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -157,6 +157,8 @@ config MACH_AMS_DELTA
 	select FIQ
 	select GPIO_GENERIC_PLATFORM
 	select LEDS_GPIO_REGISTER
+	select REGULATOR
+	select REGULATOR_FIXED_VOLTAGE
 	help
 	  Support for the Amstrad E3 (codename Delta) videophone. Say Y here
 	  if you have such a device.
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index ce50fe1..949997c 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -18,7 +18,11 @@
 #include <linux/input.h>
 #include <linux/interrupt.h>
 #include <linux/leds.h>
+#include <linux/mutex.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/serial_8250.h>
 #include <linux/export.h>
 
@@ -237,11 +241,6 @@ static const struct gpio latch_gpios[] __initconst = {
 		.label	= "scard_cmdvcc",
 	},
 	{
-		.gpio	= AMS_DELTA_GPIO_PIN_MODEM_NRESET,
-		.flags	= GPIOF_OUT_INIT_LOW,
-		.label	= "modem_nreset",
-	},
-	{
 		.gpio	= AMS_DELTA_GPIO_PIN_MODEM_CODEC,
 		.flags	= GPIOF_OUT_INIT_LOW,
 		.label	= "modem_codec",
@@ -258,6 +257,71 @@ static const struct gpio latch_gpios[] __initconst = {
 	},
 };
 
+static struct regulator_consumer_supply modem_nreset_consumers[] = {
+	REGULATOR_SUPPLY("RESET#", "serial8250.1"),
+	REGULATOR_SUPPLY("POR", "cx20442-codec"),
+};
+
+static struct regulator_init_data modem_nreset_data = {
+	.constraints		= {
+		.valid_ops_mask		= REGULATOR_CHANGE_STATUS,
+		.boot_on		= 1,
+	},
+	.num_consumer_supplies	= ARRAY_SIZE(modem_nreset_consumers),
+	.consumer_supplies	= modem_nreset_consumers,
+};
+
+static struct fixed_voltage_config modem_nreset_config = {
+	.supply_name		= "modem_nreset",
+	.microvolts		= 3300000,
+	.gpio			= AMS_DELTA_GPIO_PIN_MODEM_NRESET,
+	.startup_delay		= 25000,
+	.enable_high		= 1,
+	.enabled_at_boot	= 1,
+	.init_data		= &modem_nreset_data,
+};
+
+static struct platform_device modem_nreset_device = {
+	.name	= "reg-fixed-voltage",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &modem_nreset_config,
+	},
+};
+
+struct modem_private_data {
+	struct regulator *regulator;
+	struct {
+		struct mutex lock;
+		bool enabled;
+	} consumer;
+};
+
+static int regulator_toggle(struct modem_private_data *priv, bool enable)
+{
+	int err = 0;
+
+	mutex_lock(&priv->consumer.lock);
+	if (IS_ERR(priv->regulator)) {
+		err = PTR_ERR(priv->regulator);
+	} else if (enable) {
+		if (!priv->consumer.enabled) {
+			err = regulator_enable(priv->regulator);
+			priv->consumer.enabled = true;
+		}
+	} else {
+		if (priv->consumer.enabled) {
+			err = regulator_disable(priv->regulator);
+			priv->consumer.enabled = false;
+		}
+	}
+	mutex_unlock(&priv->consumer.lock);
+
+	return err;
+}
+
+static struct modem_private_data modem_priv;
+
 void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value)
 {
 	int bit = 0;
@@ -266,7 +330,10 @@ void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value)
 	for (; bit < ngpio; bit++, bitpos = bitpos << 1) {
 		if (!(mask & bitpos))
 			continue;
-		gpio_set_value(base + bit, (value & bitpos) != 0);
+		else if (base + bit == AMS_DELTA_GPIO_PIN_MODEM_NRESET)
+			regulator_toggle(&modem_priv, (value & bitpos) != 0);
+		else
+			gpio_set_value(base + bit, (value & bitpos) != 0);
 	}
 }
 EXPORT_SYMBOL(ams_delta_latch_write);
@@ -496,6 +563,12 @@ static int __init late_init(void)
 
 	platform_add_devices(late_devices, ARRAY_SIZE(late_devices));
 
+	err = platform_device_register(&modem_nreset_device);
+	if (err) {
+		pr_err("Couldn't register the modem regulator device\n");
+		return err;
+	}
+
 	omap_cfg_reg(M14_1510_GPIO2);
 	ams_delta_modem_ports[0].irq =
 			gpio_to_irq(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
@@ -507,6 +580,10 @@ static int __init late_init(void)
 	}
 	gpio_direction_input(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
 
+	/* Initialize the modem_nreset regulator consumer before use */
+	mutex_init(&modem_priv.consumer.lock);
+	modem_priv.regulator = ERR_PTR(-ENODEV);
+
 	ams_delta_latch2_write(
 		AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC,
 		AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC);
@@ -514,8 +591,23 @@ static int __init late_init(void)
 	err = platform_device_register(&ams_delta_modem_device);
 	if (err)
 		goto gpio_free;
+
+	/*
+	 * Once the modem device is registered, the modem_nreset
+	 * regulator can be requested on behalf of that device.
+	 * The regulator is used via ams_delta_latch_write()
+	 * by the modem and ASoC drivers until updated.
+	 */
+	modem_priv.regulator = regulator_get(&ams_delta_modem_device.dev,
+			"RESET#");
+	if (IS_ERR(modem_priv.regulator)) {
+		err = PTR_ERR(modem_priv.regulator);
+		goto unregister;
+	}
 	return 0;
 
+unregister:
+	platform_device_unregister(&ams_delta_modem_device);
 gpio_free:
 	gpio_free(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
 	return err;
-- 
1.7.3.4



From jkrzyszt at tis.icnet.pl  Mon Mar  5 11:05:11 2012
From: jkrzyszt at tis.icnet.pl (Janusz Krzysztofik)
Date: Mon,  5 Mar 2012 17:05:11 +0100
Subject: [PATCH v3 2/3] ARM: OMAP1: ams-delta: update the modem to use
 regulator API
In-Reply-To: <1330963512-20413-1-git-send-email-jkrzyszt@tis.icnet.pl>
References: <1330963512-20413-1-git-send-email-jkrzyszt@tis.icnet.pl>
Message-ID: <1330963512-20413-3-git-send-email-jkrzyszt@tis.icnet.pl>

After the CX20442 codec driver already takes care of enabling the codec
power for itself (commit f75a8ff67d161b5166a2c2360bb2ffaefd5eb853,
"ASoC: cx20442: add bias control over a platform provided regulator"),
but before dropping the old bias control method from the Amstrad Delta
ASoC sound card file, which in fact keeps the modem power always on,
even on the ASoC device close for now, extend the modem setup with a
power management callback which toggles the regulator up to the modem's
needs, reusing the previously set up regulator consumer for this. Also,
drop the MODEM_NRESET pin setup from the modem initialization procedure,
as this operation was already ineffective since patch 1/3, and not
needed because the regulator is set up as initially enabled.

Depends on patch 1/3 "ARM: OMAP1: ams-delta: set up regulator over modem
reset GPIO pin" to apply cleanly.

Signed-off-by: Janusz Krzysztofik <jkrzyszt at tis.icnet.pl>
Cc: Tony Lindgren <tony at atomide.com>
---
No functional changes against initial version.

 arch/arm/mach-omap1/board-ams-delta.c |   22 +++++++++++++++++-----
 1 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 949997c..2fb2cbb 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -526,6 +526,16 @@ static void __init ams_delta_init(void)
 	omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
 }
 
+static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
+{
+	struct modem_private_data *priv = port->private_data;
+
+	if (state == old)
+		return;
+
+	regulator_toggle(priv, state == 0);
+}
+
 static struct plat_serial8250_port ams_delta_modem_ports[] = {
 	{
 		.membase	= IOMEM(MODEM_VIRT),
@@ -536,6 +546,8 @@ static struct plat_serial8250_port ams_delta_modem_ports[] = {
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
 		.uartclk	= BASE_BAUD * 16,
+		.pm		= modem_pm,
+		.private_data	= &modem_priv,
 	},
 	{ },
 };
@@ -584,9 +596,8 @@ static int __init late_init(void)
 	mutex_init(&modem_priv.consumer.lock);
 	modem_priv.regulator = ERR_PTR(-ENODEV);
 
-	ams_delta_latch2_write(
-		AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC,
-		AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC);
+	ams_delta_latch2_write(AMS_DELTA_LATCH2_MODEM_CODEC,
+			AMS_DELTA_LATCH2_MODEM_CODEC);
 
 	err = platform_device_register(&ams_delta_modem_device);
 	if (err)
@@ -595,8 +606,9 @@ static int __init late_init(void)
 	/*
 	 * Once the modem device is registered, the modem_nreset
 	 * regulator can be requested on behalf of that device.
-	 * The regulator is used via ams_delta_latch_write()
-	 * by the modem and ASoC drivers until updated.
+	 * In addition to the modem .pm callback, that regulator
+	 * is still used via the ams_delta_latch_write() wrapper
+	 * by the ASoC driver until updated.
 	 */
 	modem_priv.regulator = regulator_get(&ams_delta_modem_device.dev,
 			"RESET#");
-- 
1.7.3.4



From jkrzyszt at tis.icnet.pl  Mon Mar  5 11:05:12 2012
From: jkrzyszt at tis.icnet.pl (Janusz Krzysztofik)
Date: Mon,  5 Mar 2012 17:05:12 +0100
Subject: [PATCH v3 3/3] ASoC: OMAP: ams-delta: drop .set_bias_level callback
In-Reply-To: <1330963512-20413-1-git-send-email-jkrzyszt@tis.icnet.pl>
References: <1330963512-20413-1-git-send-email-jkrzyszt@tis.icnet.pl>
Message-ID: <1330963512-20413-4-git-send-email-jkrzyszt@tis.icnet.pl>

This functionality has already been implemented in the cx20442 codec
driver (commit f75a8ff67d161b5166a2c2360bb2ffaefd5eb853, "ASoC: cx20442:
add bias control over a platform provided regulator"), no need to keep
it here duplicated.

Once done, remove the no longer used AMS_DELTA_LATCH2_MODEM_NRESET
symbol from the board header file and a call to the regulator_toggle()
helper function from the old API wrapper found in the board file.  While
being at it, simplify the way the modem .pm callback handles the
regulator and drop that helper function and its related consumer setup
completely.

Depends on patches 1/3 and 2/3 for clean apply and keep things working.

Signed-off-by: Janusz Krzysztofik <jkrzyszt at tis.icnet.pl>
Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Tony Lindgren <tony at atomide.com>
---
v2 -> v3 changes: none.

Changes against initial version:
* don't move consumer setup elements, now named to indicated their
  modem related purpose, down the file,
* don't track the regulator enable/disable state, compare new target
  power state with the old one instead; thanks to Mark Brown for
  suggesting this simplification,
* actually drop all references to AMS_DELTA_LATCH2_MODEM_NRESET.

 arch/arm/mach-omap1/board-ams-delta.c             |   42 +++-----------------
 arch/arm/plat-omap/include/plat/board-ams-delta.h |    1 -
 sound/soc/omap/ams-delta.c                        |   32 ----------------
 3 files changed, 7 insertions(+), 68 deletions(-)

diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 2fb2cbb..cb6afe6 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -18,7 +18,6 @@
 #include <linux/input.h>
 #include <linux/interrupt.h>
 #include <linux/leds.h>
-#include <linux/mutex.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/consumer.h>
 #include <linux/regulator/fixed.h>
@@ -291,35 +290,8 @@ static struct platform_device modem_nreset_device = {
 
 struct modem_private_data {
 	struct regulator *regulator;
-	struct {
-		struct mutex lock;
-		bool enabled;
-	} consumer;
 };
 
-static int regulator_toggle(struct modem_private_data *priv, bool enable)
-{
-	int err = 0;
-
-	mutex_lock(&priv->consumer.lock);
-	if (IS_ERR(priv->regulator)) {
-		err = PTR_ERR(priv->regulator);
-	} else if (enable) {
-		if (!priv->consumer.enabled) {
-			err = regulator_enable(priv->regulator);
-			priv->consumer.enabled = true;
-		}
-	} else {
-		if (priv->consumer.enabled) {
-			err = regulator_disable(priv->regulator);
-			priv->consumer.enabled = false;
-		}
-	}
-	mutex_unlock(&priv->consumer.lock);
-
-	return err;
-}
-
 static struct modem_private_data modem_priv;
 
 void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value)
@@ -330,8 +302,6 @@ void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value)
 	for (; bit < ngpio; bit++, bitpos = bitpos << 1) {
 		if (!(mask & bitpos))
 			continue;
-		else if (base + bit == AMS_DELTA_GPIO_PIN_MODEM_NRESET)
-			regulator_toggle(&modem_priv, (value & bitpos) != 0);
 		else
 			gpio_set_value(base + bit, (value & bitpos) != 0);
 	}
@@ -530,10 +500,16 @@ static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
 {
 	struct modem_private_data *priv = port->private_data;
 
+	if (IS_ERR(priv->regulator))
+		return;
+
 	if (state == old)
 		return;
 
-	regulator_toggle(priv, state == 0);
+	if (state == 0)
+		regulator_enable(priv->regulator);
+	else if (old == 0)
+		regulator_disable(priv->regulator);
 }
 
 static struct plat_serial8250_port ams_delta_modem_ports[] = {
@@ -593,7 +569,6 @@ static int __init late_init(void)
 	gpio_direction_input(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
 
 	/* Initialize the modem_nreset regulator consumer before use */
-	mutex_init(&modem_priv.consumer.lock);
 	modem_priv.regulator = ERR_PTR(-ENODEV);
 
 	ams_delta_latch2_write(AMS_DELTA_LATCH2_MODEM_CODEC,
@@ -606,9 +581,6 @@ static int __init late_init(void)
 	/*
 	 * Once the modem device is registered, the modem_nreset
 	 * regulator can be requested on behalf of that device.
-	 * In addition to the modem .pm callback, that regulator
-	 * is still used via the ams_delta_latch_write() wrapper
-	 * by the ASoC driver until updated.
 	 */
 	modem_priv.regulator = regulator_get(&ams_delta_modem_device.dev,
 			"RESET#");
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
index 027e79e..ad6f865 100644
--- a/arch/arm/plat-omap/include/plat/board-ams-delta.h
+++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h
@@ -30,7 +30,6 @@
 
 #define AMD_DELTA_LATCH2_SCARD_RSTIN	0x0400
 #define AMD_DELTA_LATCH2_SCARD_CMDVCC	0x0800
-#define AMS_DELTA_LATCH2_MODEM_NRESET	0x1000
 #define AMS_DELTA_LATCH2_MODEM_CODEC	0x2000
 
 #define AMS_DELTA_GPIO_PIN_KEYBRD_DATA	0
diff --git a/sound/soc/omap/ams-delta.c b/sound/soc/omap/ams-delta.c
index da6e005..f610260 100644
--- a/sound/soc/omap/ams-delta.c
+++ b/sound/soc/omap/ams-delta.c
@@ -426,29 +426,6 @@ static struct snd_soc_ops ams_delta_ops = {
 };
 
 
-/* Board specific codec bias level control */
-static int ams_delta_set_bias_level(struct snd_soc_card *card,
-				    struct snd_soc_dapm_context *dapm,
-				    enum snd_soc_bias_level level)
-{
-	switch (level) {
-	case SND_SOC_BIAS_ON:
-	case SND_SOC_BIAS_PREPARE:
-	case SND_SOC_BIAS_STANDBY:
-		if (card->dapm.bias_level == SND_SOC_BIAS_OFF)
-			ams_delta_latch2_write(AMS_DELTA_LATCH2_MODEM_NRESET,
-						AMS_DELTA_LATCH2_MODEM_NRESET);
-		break;
-	case SND_SOC_BIAS_OFF:
-		if (card->dapm.bias_level != SND_SOC_BIAS_OFF)
-			ams_delta_latch2_write(AMS_DELTA_LATCH2_MODEM_NRESET,
-						0);
-	}
-	card->dapm.bias_level = level;
-
-	return 0;
-}
-
 /* Digital mute implemented using modem/CPU multiplexer.
  * Shares hardware with codec config pulse generation */
 static bool ams_delta_muted = 1;
@@ -512,9 +489,6 @@ static int ams_delta_cx20442_init(struct snd_soc_pcm_runtime *rtd)
 		ams_delta_ops.shutdown = ams_delta_shutdown;
 	}
 
-	/* Set codec bias level */
-	ams_delta_set_bias_level(card, dapm, SND_SOC_BIAS_STANDBY);
-
 	/* Add hook switch - can be used to control the codec from userspace
 	 * even if line discipline fails */
 	ret = snd_soc_jack_new(rtd->codec, "hook_switch",
@@ -598,7 +572,6 @@ static struct snd_soc_card ams_delta_audio_card = {
 	.owner = THIS_MODULE,
 	.dai_link = &ams_delta_dai_link,
 	.num_links = 1,
-	.set_bias_level = ams_delta_set_bias_level,
 };
 
 /* Module init/exit */
@@ -647,11 +620,6 @@ static void __exit ams_delta_module_exit(void)
 			ARRAY_SIZE(ams_delta_hook_switch_gpios),
 			ams_delta_hook_switch_gpios);
 
-	/* Keep modem power on */
-	ams_delta_set_bias_level(&ams_delta_audio_card,
-				 &ams_delta_audio_card.rtd[0].codec->dapm,
-				 SND_SOC_BIAS_STANDBY);
-
 	platform_device_unregister(cx20442_platform_device);
 	platform_device_unregister(ams_delta_audio_platform_device);
 }
-- 
1.7.3.4



From m.szyprowski at samsung.com  Mon Mar  5 11:07:02 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 05 Mar 2012 17:07:02 +0100
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <20120305134721.0ab0d0e6de56fa30250059b1@nvidia.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <20120305134721.0ab0d0e6de56fa30250059b1@nvidia.com>
Message-ID: <000001ccfaea$00c16f70$02444e50$%szyprowski@samsung.com>

Hello,

On Monday, March 05, 2012 12:47 PM Hiroshi Doyu wrote:

> On Wed, 29 Feb 2012 16:04:22 +0100
> Marek Szyprowski <m.szyprowski at samsung.com> wrote:
> 
> > This patch add a complete implementation of DMA-mapping API for
> > devices that have IOMMU support. All DMA-mapping calls are supported.
> >
> > This patch contains some of the code kindly provided by Krishna Reddy
> > <vdumpa at nvidia.com> and Andrzej Pietrasiewicz <andrzej.p at samsung.com>
> >
> > Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
> > ---

(snipped)

> > +/**
> > + * arm_iommu_create_mapping
> > + * @bus: pointer to the bus holding the client device (for IOMMU calls)
> > + * @base: start address of the valid IO address space
> > + * @size: size of the valid IO address space
> > + * @order: accuracy of the IO addresses allocations
> > + *
> > + * Creates a mapping structure which holds information about used/unused
> > + * IO address ranges, which is required to perform memory allocation and
> > + * mapping with IOMMU aware functions.
> > + *
> > + * The client device need to be attached to the mapping with
> > + * arm_iommu_attach_device function.
> > + */
> > +struct dma_iommu_mapping *
> > +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
> > +                        int order)
> > +{
> > +       unsigned int count = (size >> PAGE_SHIFT) - order;
> > +       unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
> > +       struct dma_iommu_mapping *mapping;
> > +       int err = -ENOMEM;
> > +
> > +       mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
> > +       if (!mapping)
> > +               goto err;
> > +
> > +       mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
> > +       if (!mapping->bitmap)
> > +               goto err2;
> > +
> > +       mapping->base = base;
> > +       mapping->bits = bitmap_size;
> 
> Shouldn't the above be as below?
> 
> From 093c77ac6f19899679f2f2447a9d2c684eab7b2e Mon Sep 17 00:00:00 2001
> From: Hiroshi DOYU <hdoyu at nvidia.com>
> Date: Mon, 5 Mar 2012 13:04:38 +0200
> Subject: [PATCH 1/1] dma-mapping: Fix mapping->bits size
> 
> Amount of bits should be mutiplied by BITS_PER_BITE.
> 
> Signed-off-by: Hiroshi DOYU <hdoyu at nvidia.com>
> ---
>  arch/arm/mm/dma-mapping.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index e55f425..5ec7747 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -1495,7 +1495,7 @@ arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t
> size,
>  		goto err2;
> 
>  	mapping->base = base;
> -	mapping->bits = bitmap_size;
> +	mapping->bits = BITS_PER_BYTE * bitmap_size;
>  	mapping->order = order;
>  	spin_lock_init(&mapping->lock);

You are right, thanks for spotting this issue!

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center



From broonie at opensource.wolfsonmicro.com  Mon Mar  5 11:15:20 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 16:15:20 +0000
Subject: [PATCH v2 11/17] ASoC: fsl: create fsl_utils to accommodate the
 common functions
In-Reply-To: <4F54E065.8060905@freescale.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-12-git-send-email-shawn.guo@linaro.org>
 <20120305144920.GR3224@opensource.wolfsonmicro.com>
 <4F54E065.8060905@freescale.com>
Message-ID: <20120305161520.GT3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 09:48:53AM -0600, Timur Tabi wrote:
> Mark Brown wrote:

> > This doesn't seem at all Freescale specific, it should be a generic
> > helper, and in fact there already is one - the machine driver can set
> > codec_of_node in the card structure to point to the device node and then
> > the core should figure out binding to the device for you.  If it doesn't
> > we should fix the core.

> Can we do that in another patch set, so that it doesn't hold up Shawn's
> work?  All this patch does is move the code from one file to another, so
> it's not like he's adding a feature incorrectly.

Well, it shouldn't be much effort - instead of removing the code just
delete it mostly - and there's other issues that need to be looked at
anyway.  There's also the arch/arm stuff that needs review...
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From javier.martin at vista-silicon.com  Mon Mar  5 11:16:22 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:22 +0100
Subject: [PATCH 00/14] dmaengine: imx-dma: merge dma arch code into dmaengine.
Message-ID: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>

The following series have to be applied on top of the following patches:
[PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
[PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.

As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
is deprecated and no new patches are accepted for it.

This series merges this code into the imx-dma.c dmaengine driver.

[PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
[PATCH 02/14] dmaengine: imx-dma: remove data member form internal structure.
[PATCH 03/14] dmaengine: imx-dma: remove dma_mode member of internal structure.
[PATCH 04/14] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
[PATCH 05/14] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
[PATCH 06/14] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
[PATCH 07/14] dmaengine: imx-dma: remove sg member from internal structure.
[PATCH 08/14] dmaengine: imx-dma: remove in_use field of internal structure.
[PATCH 09/14] dmaengine: imx-dma: remove resbytes field of internal structure.
[PATCH 10/14] dmaengine: imx-dma: remove internal structure.
[PATCH 11/14] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
[PATCH 12/14] dmaengine: imx-dma: integrate 'imx_dmav1_baseaddr' and 'dma_clk' inside dmaengine structure.
[PATCH 13/14] dmaengine: imx-dma: use dev_dbg and dev_warn for messages.
[PATCH 14/14] dmaengine: imx-dma: remove  dma-v1.c and dma-v1.h


From javier.martin at vista-silicon.com  Mon Mar  5 11:16:23 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:23 +0100
Subject: [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-2-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/mach-imx/Kconfig  |    6 -
 arch/arm/mach-imx/Makefile |    2 -
 drivers/dma/Kconfig        |    1 -
 drivers/dma/imx-dma.c      |  591 ++++++++++++++++++++++++++++++++++++++++----
 4 files changed, 541 insertions(+), 59 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0e6de36..3da1421 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,6 +1,3 @@
-config IMX_HAVE_DMA_V1
-	bool
-
 config HAVE_IMX_GPC
 	bool
 
@@ -26,7 +23,6 @@ config SOC_IMX1
 	bool
 	select ARCH_MX1
 	select CPU_ARM920T
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
@@ -35,7 +31,6 @@ config SOC_IMX21
 	select MACH_MX21
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
@@ -52,7 +47,6 @@ config SOC_IMX27
 	select MACH_MX27
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f5920c2..a62dc3a 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,5 +1,3 @@
-obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
-
 obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
 obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
 
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f1a2749..eb58b91 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -231,7 +231,6 @@ config IMX_SDMA
 
 config IMX_DMA
 	tristate "i.MX DMA support"
-	depends on IMX_HAVE_DMA_V1
 	select DMA_ENGINE
 	help
 	  Support the i.MX DMA engine. This engine is integrated into
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index c32103f..28d716c 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -14,7 +14,6 @@
  * http://www.opensource.org/licenses/gpl-license.html
  * http://www.gnu.org/copyleft/gpl.html
  */
-
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/types.h>
@@ -25,14 +24,88 @@
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 #include <linux/dmaengine.h>
 #include <linux/module.h>
 
 #include <asm/irq.h>
-#include <mach/dma-v1.h>
+#include <mach/dma.h>
 #include <mach/hardware.h>
 
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
+#define IMX_DMA_CHANNELS  16
+
+#define DMA_MODE_READ		0
+#define DMA_MODE_WRITE		1
+#define DMA_MODE_MASK		1
+
+#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
+#define IMX_DMA_MEMSIZE_32	(0 << 4)
+#define IMX_DMA_MEMSIZE_8	(1 << 4)
+#define IMX_DMA_MEMSIZE_16	(2 << 4)
+#define IMX_DMA_TYPE_LINEAR	(0 << 10)
+#define IMX_DMA_TYPE_2D		(1 << 10)
+#define IMX_DMA_TYPE_FIFO	(2 << 10)
+
+#define IMX_DMA_ERR_BURST     (1 << 0)
+#define IMX_DMA_ERR_REQUEST   (1 << 1)
+#define IMX_DMA_ERR_TRANSFER  (1 << 2)
+#define IMX_DMA_ERR_BUFFER    (1 << 3)
+#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
+
+#define DMA_DCR     0x00		/* Control Register */
+#define DMA_DISR    0x04		/* Interrupt status Register */
+#define DMA_DIMR    0x08		/* Interrupt mask Register */
+#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
+#define DMA_DRTOSR  0x10		/* Request timeout Register */
+#define DMA_DSESR   0x14		/* Transfer Error Status Register */
+#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
+#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
+#define DMA_WSRA    0x40		/* W-Size Register A */
+#define DMA_XSRA    0x44		/* X-Size Register A */
+#define DMA_YSRA    0x48		/* Y-Size Register A */
+#define DMA_WSRB    0x4c		/* W-Size Register B */
+#define DMA_XSRB    0x50		/* X-Size Register B */
+#define DMA_YSRB    0x54		/* Y-Size Register B */
+#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
+#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
+#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
+#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
+#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
+#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
+#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
+#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
+#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff)
+#define CNTR_CNT(x)        ((x) & 0xffffff)
+#define CCR_ACRPT          (1<<14)
+#define CCR_DMOD_LINEAR    (0x0 << 12)
+#define CCR_DMOD_2D        (0x1 << 12)
+#define CCR_DMOD_FIFO      (0x2 << 12)
+#define CCR_DMOD_EOBFIFO   (0x3 << 12)
+#define CCR_SMOD_LINEAR    (0x0 << 10)
+#define CCR_SMOD_2D        (0x1 << 10)
+#define CCR_SMOD_FIFO      (0x2 << 10)
+#define CCR_SMOD_EOBFIFO   (0x3 << 10)
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        (0x0 << 6)
+#define CCR_DSIZ_8         (0x1 << 6)
+#define CCR_DSIZ_16        (0x2 << 6)
+#define CCR_SSIZ_32        (0x0 << 4)
+#define CCR_SSIZ_8         (0x1 << 4)
+#define CCR_SSIZ_16        (0x2 << 4)
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
 
 enum  imxdma_prep_type {
 	IMXDMA_DESC_MEMCPY,
@@ -41,6 +114,39 @@ enum  imxdma_prep_type {
 	IMXDMA_DESC_CYCLIC,
 };
 
+/*
+ * struct imxdma_channel_internal - i.MX specific DMA extension
+ * @name: name specified by DMA client
+ * @irq_handler: client callback for end of transfer
+ * @err_handler: client callback for error condition
+ * @data: clients context data for callbacks
+ * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
+ * @sg: pointer to the actual read/written chunk for scatter-gather emulation
+ * @resbytes: total residual number of bytes to transfer
+ *            (it can be lower or same as sum of SG mapped chunk sizes)
+ * @sgcount: number of chunks to be read/written
+ *
+ * Structure is used for IMX DMA processing. It would be probably good
+ * @struct dma_struct in the future for external interfacing and use
+ * @struct imxdma_channel_internal only as extension to it.
+ */
+
+struct imxdma_channel_internal {
+	void *data;
+	unsigned int dma_mode;
+	struct scatterlist *sg;
+	unsigned int resbytes;
+
+	int in_use;
+
+	u32 ccr_from_device;
+	u32 ccr_to_device;
+
+	struct timer_list watchdog;
+
+	int hw_chaining;
+};
+
 struct imxdma_desc {
 	struct list_head		node;
 	struct dma_async_tx_descriptor	desc;
@@ -63,9 +169,9 @@ struct imxdma_desc {
 };
 
 struct imxdma_channel {
+	struct imxdma_channel_internal	internal;
 	struct imxdma_engine		*imxdma;
 	unsigned int			channel;
-	unsigned int			imxdma_channel;
 
 	struct tasklet_struct		dma_tasklet;
 	struct list_head		ld_free;
@@ -109,28 +215,381 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 	return false;
 }
 
-static void imxdma_irq_handler(int channel, void *data)
+/* TODO: put this inside any struct */
+static void __iomem *imx_dmav1_baseaddr;
+static struct clk *dma_clk;
+
+static void imx_dmav1_writel(unsigned val, unsigned offset)
 {
-	struct imxdma_channel *imxdmac = data;
+	__raw_writel(val, imx_dmav1_baseaddr + offset);
+}
 
-	tasklet_schedule(&imxdmac->dma_tasklet);
+static unsigned imx_dmav1_readl(unsigned offset)
+{
+	return __raw_readl(imx_dmav1_baseaddr + offset);
 }
 
-static void imxdma_err_handler(int channel, void *data, int error)
+static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
 {
-	struct imxdma_channel *imxdmac = data;
+	if (cpu_is_mx27())
+		return imxdma->hw_chaining;
+	else
+		return 0;
+}
+
+/*
+ * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
+ */
+static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+{
+	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+	unsigned long now;
+
+	now = min(imxdma->resbytes, sg->length);
+	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
+		imxdma->resbytes -= now;
+
+	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+	else
+		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+
+	imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+
+	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
+		"size 0x%08x\n", imxdmac->channel,
+		 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
+		 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
+		 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+
+	return now;
+}
+
+static int
+imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+		     unsigned int dma_length, unsigned int dev_addr,
+		     unsigned int dmamode)
+{
+	int channel = imxdmac->channel;
+
+	imxdmac->internal.sg = NULL;
+	imxdmac->internal.dma_mode = dmamode;
+
+	if (!dma_address) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if (!dma_length) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+			"dev_addr=0x%08x for read\n",
+			channel, __func__, (unsigned int)dma_address,
+			dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+		imx_dmav1_writel(dma_address, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+			"dev_addr=0x%08x for write\n",
+			channel, __func__, (unsigned int)dma_address,
+			dma_length, dev_addr);
+
+		imx_dmav1_writel(dma_address, DMA_SAR(channel));
+		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+				DMA_CCR(channel));
+	} else {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
+		       channel);
+		return -EINVAL;
+	}
 
+	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
+
+	return 0;
+}
+
+static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+{
+	int channel = imxdmac->channel;
+	unsigned long flags;
+
+	pr_debug("imxdma%d: imx_dma_enable\n", channel);
+
+	if (imxdmac->internal.in_use)
+		return;
+
+	local_irq_save(flags);
+
+	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
+		CCR_ACRPT, DMA_CCR(channel));
+
+	if ((cpu_is_mx21() || cpu_is_mx27()) &&
+			imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
+		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
+		if (imxdmac->internal.sg) {
+			u32 tmp;
+			imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+			tmp = imx_dmav1_readl(DMA_CCR(channel));
+			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
+				DMA_CCR(channel));
+		}
+	}
+	imxdmac->internal.in_use = 1;
+
+	local_irq_restore(flags);
+}
+
+static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
+{
+	int channel = imxdmac->channel;
+	unsigned long flags;
+
+	pr_debug("imxdma%d: imx_dma_disable\n", channel);
+
+	if (imxdma_hw_chain(&imxdmac->internal))
+		del_timer(&imxdmac->internal.watchdog);
+
+	local_irq_save(flags);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
+			DMA_CCR(channel));
+	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imxdmac->internal.in_use = 0;
+	local_irq_restore(flags);
+}
+
+static int
+imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
+	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
+{
+	int channel = imxdmac->channel;
+	u32 dreq = 0;
+
+	imxdmac->internal.hw_chaining = 0;
+
+	if (hw_chaining) {
+		imxdmac->internal.hw_chaining = 1;
+		if (!imxdma_hw_chain(&imxdmac->internal))
+			return -EINVAL;
+	}
+
+	if (dmareq)
+		dreq = CCR_REN;
+
+	imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
+	imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
+
+	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
+
+	return 0;
+}
+
+static int
+imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+		 struct scatterlist *sg, unsigned int sgcount,
+		 unsigned int dma_length, unsigned int dev_addr,
+		 unsigned int dmamode)
+{
+	int channel = imxdmac->channel;
+
+	if (imxdmac->internal.in_use)
+		return -EBUSY;
+
+	imxdmac->internal.sg = sg;
+	imxdmac->internal.dma_mode = dmamode;
+	imxdmac->internal.resbytes = dma_length;
+
+	if (!sg || !sgcount) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if (!sg->length) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+			"dev_addr=0x%08x for read\n",
+			channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+			"dev_addr=0x%08x for write\n",
+			channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
+	} else {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	imxdma_sg_next(imxdmac, sg);
+
+	return 0;
+}
+
+static void imxdma_watchdog(unsigned long data)
+{
+	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+	int channel = imxdmac->channel;
+
+	imx_dmav1_writel(0, DMA_CCR(channel));
+	imxdmac->internal.in_use = 0;
+	imxdmac->internal.sg = NULL;
+
+	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
+	pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+}
+
+static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
+{
+	struct imxdma_engine *imxdma = dev_id;
+	struct imxdma_channel_internal *internal;
+	unsigned int err_mask;
+	int i, disr;
+	int errcode;
+
+	disr = imx_dmav1_readl(DMA_DISR);
+
+	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
+		   imx_dmav1_readl(DMA_DRTOSR) |
+		   imx_dmav1_readl(DMA_DSESR)  |
+		   imx_dmav1_readl(DMA_DBOSR);
+
+	if (!err_mask)
+		return IRQ_HANDLED;
+
+	imx_dmav1_writel(disr & err_mask, DMA_DISR);
+
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+		if (!(err_mask & (1 << i)))
+			continue;
+		internal = &imxdma->channel[i].internal;
+		errcode = 0;
+
+		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DBTOSR);
+			errcode |= IMX_DMA_ERR_BURST;
+		}
+		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DRTOSR);
+			errcode |= IMX_DMA_ERR_REQUEST;
+		}
+		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DSESR);
+			errcode |= IMX_DMA_ERR_TRANSFER;
+		}
+		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DBOSR);
+			errcode |= IMX_DMA_ERR_BUFFER;
+		}
+		/* Tasklet error handler */
+		tasklet_schedule(&imxdma->channel[i].dma_tasklet);
+
+		printk(KERN_WARNING
+		       "DMA timeout on channel %d -%s%s%s%s\n", i,
+		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
+		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
+		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
+		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
+	}
+	return IRQ_HANDLED;
 }
 
-static void imxdma_progression(int channel, void *data,
-		struct scatterlist *sg)
+static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
-	struct imxdma_channel *imxdmac = data;
+	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+	int chno = imxdmac->channel;
+
+	if (imxdma->sg) {
+		u32 tmp;
+		imxdma->sg = sg_next(imxdma->sg);
+
+		if (imxdma->sg) {
+			imxdma_sg_next(imxdmac, imxdma->sg);
+
+			tmp = imx_dmav1_readl(DMA_CCR(chno));
+
+			if (imxdma_hw_chain(imxdma)) {
+				/* FIXME: The timeout should probably be
+				 * configurable
+				 */
+				mod_timer(&imxdma->watchdog,
+					jiffies + msecs_to_jiffies(500));
+
+				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
+				imx_dmav1_writel(tmp, DMA_CCR(chno));
+			} else {
+				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+				tmp |= CCR_CEN;
+			}
+
+			imx_dmav1_writel(tmp, DMA_CCR(chno));
+
+			if (imxdma_chan_is_doing_cyclic(imxdmac))
+				/* Tasklet progression */
+				tasklet_schedule(&imxdmac->dma_tasklet);
+
+			return;
+		}
 
+		if (imxdma_hw_chain(imxdma)) {
+			del_timer(&imxdma->watchdog);
+			return;
+		}
+	}
+
+	imx_dmav1_writel(0, DMA_CCR(chno));
+	imxdma->in_use = 0;
+	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
 
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+	struct imxdma_engine *imxdma = dev_id;
+	struct imxdma_channel_internal *internal;
+	int i, disr;
+
+	if (cpu_is_mx21() || cpu_is_mx27())
+		imxdma_err_handler(irq, dev_id);
+
+	disr = imx_dmav1_readl(DMA_DISR);
+
+	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
+		     disr);
+
+	imx_dmav1_writel(disr, DMA_DISR);
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+		if (disr & (1 << i)) {
+			internal = &imxdma->channel[i].internal;
+			dma_irq_handle_channel(&imxdma->channel[i]);
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
 static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -139,31 +598,24 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+		ret = imxdma_config_channel_hw(imxdmac,
 					  d->config_port, d->config_mem, 0, 0);
 		if (ret < 0)
 			return ret;
-		ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
+		ret = imxdma_setup_single_hw(imxdmac, d->src,
 					   d->len, d->dest, d->dmamode);
 		if (ret < 0)
 			return ret;
 		break;
+
+	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
-		ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
-							imxdma_progression);
-		if (ret < 0)
-			return ret;
-		/*
-		 * We fall through here since cyclic transfer is the same as
-		 * slave_sg adding a progression handler and a specific sg
-		 * configuration which is done in 'imxdma_prep_dma_cyclic'.
-		 */
 	case IMXDMA_DESC_SLAVE_SG:
 		if (d->dmamode == DMA_MODE_READ)
-			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
 				       d->sgcount, d->len, d->src, d->dmamode);
 		else
-			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
 				      d->sgcount, d->len, d->dest, d->dmamode);
 		if (ret < 0)
 			return ret;
@@ -171,7 +623,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	default:
 		return -EINVAL;
 	}
-	imx_dma_enable(imxdmac->imxdma_channel);
+	imxdma_enable_hw(imxdmac);
 	return 0;
 }
 
@@ -223,7 +675,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 
 	switch (cmd) {
 	case DMA_TERMINATE_ALL:
-		imx_dma_disable(imxdmac->imxdma_channel);
+		imxdma_disable_hw(imxdmac);
 
 		spin_lock_irqsave(&imxdmac->lock, flags);
 		list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
@@ -253,16 +705,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			mode = IMX_DMA_MEMSIZE_32;
 			break;
 		}
-		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+		ret = imxdma_config_channel_hw(imxdmac,
 				mode | IMX_DMA_TYPE_FIFO,
 				IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
 				imxdmac->dma_request, 1);
 
 		if (ret)
 			return ret;
-
-		imx_dma_config_burstlen(imxdmac->imxdma_channel,
-				imxdmac->watermark_level * imxdmac->word_size);
+		/* Set burst length */
+		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
+				 DMA_BLR(imxdmac->channel));
 
 		return 0;
 	default:
@@ -359,7 +811,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
 
 	spin_lock_irqsave(&imxdmac->lock, flags);
 
-	imx_dma_disable(imxdmac->imxdma_channel);
+	imxdma_disable_hw(imxdmac);
 	list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 	list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 
@@ -545,10 +997,51 @@ static void imxdma_issue_pending(struct dma_chan *chan)
 }
 
 static int __init imxdma_probe(struct platform_device *pdev)
-{
+	{
 	struct imxdma_engine *imxdma;
 	int ret, i;
 
+	if (cpu_is_mx1())
+		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+	else if (cpu_is_mx21())
+		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+	else if (cpu_is_mx27())
+		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+	else
+		return 0;
+
+	dma_clk = clk_get(NULL, "dma");
+	if (IS_ERR(dma_clk))
+		return PTR_ERR(dma_clk);
+	clk_enable(dma_clk);
+
+	/* reset DMA module */
+	imx_dmav1_writel(DCR_DRST, DMA_DCR);
+
+	if (cpu_is_mx1()) {
+		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
+		if (ret) {
+			pr_crit("Can't register IRQ for DMA\n");
+			return ret;
+		}
+
+		ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
+		if (ret) {
+			pr_crit("Can't register ERRIRQ for DMA\n");
+			free_irq(MX1_DMA_INT, NULL);
+			return ret;
+		}
+	}
+
+	/* enable DMA module */
+	imx_dmav1_writel(DCR_DEN, DMA_DCR);
+
+	/* clear all interrupts */
+	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+
+	/* disable interrupts */
+	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
+
 	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
 	if (!imxdma)
 		return -ENOMEM;
@@ -562,17 +1055,20 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	/* Initialize channel parameters */
 	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
 		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
-		imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
-				DMA_PRIO_MEDIUM);
-		if ((int)imxdmac->channel < 0) {
-			ret = -ENODEV;
-			goto err_init;
+		memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+		if (cpu_is_mx21() || cpu_is_mx27()) {
+			ret = request_irq(MX2x_INT_DMACH0 + i,
+					dma_irq_handler, 0, "DMA", imxdma);
+			if (ret) {
+				pr_crit("Can't register IRQ %d for DMA channel %d\n",
+						MX2x_INT_DMACH0 + i, i);
+				goto err_init;
+			}
+			init_timer(&imxdmac->internal.watchdog);
+			imxdmac->internal.watchdog.function = &imxdma_watchdog;
+			imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
 		}
 
-		imx_dma_setup_handlers(imxdmac->imxdma_channel,
-		       imxdma_irq_handler, imxdma_err_handler, imxdmac);
-
 		imxdmac->imxdma = imxdma;
 		spin_lock_init(&imxdmac->lock);
 
@@ -617,10 +1113,8 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	return 0;
 
 err_init:
-	while (--i >= 0) {
-		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-		imx_dma_free(imxdmac->imxdma_channel);
-	}
+	while (--i >= 0)
+		free_irq(MX2x_INT_DMACH0 + i, NULL);
 
 	kfree(imxdma);
 	return ret;
@@ -633,11 +1127,8 @@ static int __exit imxdma_remove(struct platform_device *pdev)
 
         dma_async_device_unregister(&imxdma->dma_device);
 
-	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
-		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
-		 imx_dma_free(imxdmac->imxdma_channel);
-	}
+	for (i = 0; i < MAX_DMA_CHANNELS; i++)
+		free_irq(MX2x_INT_DMACH0 + i, NULL);
 
         kfree(imxdma);
 
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:24 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:24 +0100
Subject: [PATCH 02/14] dmaengine: imx-dma: remove data member form internal
 structure.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-3-git-send-email-javier.martin@vista-silicon.com>

It is not used anywhere in the driver.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 28d716c..1a9be6d 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -132,7 +132,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	void *data;
 	unsigned int dma_mode;
 	struct scatterlist *sg;
 	unsigned int resbytes;
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:25 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:25 +0100
Subject: [PATCH 03/14] dmaengine: imx-dma: remove dma_mode member of internal
 structure.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-4-git-send-email-javier.martin@vista-silicon.com>

Use direction field which is embedded in the descriptor structure
instead.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |  103 +++++++++++++++++++++---------------------------
 1 files changed, 45 insertions(+), 58 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 1a9be6d..2c524e1 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -35,10 +35,6 @@
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
 #define IMX_DMA_CHANNELS  16
 
-#define DMA_MODE_READ		0
-#define DMA_MODE_WRITE		1
-#define DMA_MODE_MASK		1
-
 #define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
 #define IMX_DMA_MEMSIZE_32	(0 << 4)
 #define IMX_DMA_MEMSIZE_8	(1 << 4)
@@ -132,7 +128,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	unsigned int dma_mode;
 	struct scatterlist *sg;
 	unsigned int resbytes;
 
@@ -153,7 +148,7 @@ struct imxdma_desc {
 	dma_addr_t			src;
 	dma_addr_t			dest;
 	size_t				len;
-	unsigned int			dmamode;
+	enum dma_transfer_direction	direction;
 	enum imxdma_prep_type		type;
 	/* For memcpy and interleaved */
 	unsigned int			config_port;
@@ -239,8 +234,9 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
 /*
  * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
  */
-static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	unsigned long now;
 
@@ -248,7 +244,7 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
 	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
 		imxdma->resbytes -= now;
 
-	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+	if (d->direction == DMA_DEV_TO_MEM)
 		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
 	else
 		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
@@ -265,14 +261,12 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
 }
 
 static int
-imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr,
-		     unsigned int dmamode)
+imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+		     unsigned int dma_length, unsigned int dev_addr)
 {
 	int channel = imxdmac->channel;
 
 	imxdmac->internal.sg = NULL;
-	imxdmac->internal.dma_mode = dmamode;
 
 	if (!dma_address) {
 		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
@@ -286,38 +280,24 @@ imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
 		return -EINVAL;
 	}
 
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
+	pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+		"dev_addr=0x%08x for write\n",
+		channel, __func__, (unsigned int)dma_address,
+		dma_length, dev_addr);
 
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(dma_address, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dma_address, DMA_SAR(channel));
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_to_device,
-				DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
+	imx_dmav1_writel(dma_address, DMA_SAR(channel));
+	imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+	imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+			 DMA_CCR(channel));
 
 	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
 
 	return 0;
 }
 
-static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+static void imxdma_enable_hw(struct imxdma_desc *d)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -338,7 +318,7 @@ static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
 		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
 		if (imxdmac->internal.sg) {
 			u32 tmp;
-			imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+			imxdma_sg_next(d, imxdmac->internal.sg);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -395,18 +375,18 @@ imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_por
 }
 
 static int
-imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+imxdma_setup_sg_hw(struct imxdma_desc *d,
 		 struct scatterlist *sg, unsigned int sgcount,
 		 unsigned int dma_length, unsigned int dev_addr,
-		 unsigned int dmamode)
+		 enum dma_transfer_direction direction)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	int channel = imxdmac->channel;
 
 	if (imxdmac->internal.in_use)
 		return -EBUSY;
 
 	imxdmac->internal.sg = sg;
-	imxdmac->internal.dma_mode = dmamode;
 	imxdmac->internal.resbytes = dma_length;
 
 	if (!sg || !sgcount) {
@@ -421,14 +401,14 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
 		return -EINVAL;
 	}
 
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+	if (direction == DMA_DEV_TO_MEM) {
 		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
 			"dev_addr=0x%08x for read\n",
 			channel, __func__, sg, sgcount, dma_length, dev_addr);
 
 		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
 		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+	} else if (direction == DMA_MEM_TO_DEV) {
 		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
 			"dev_addr=0x%08x for write\n",
 			channel, __func__, sg, sgcount, dma_length, dev_addr);
@@ -441,7 +421,7 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
 		return -EINVAL;
 	}
 
-	imxdma_sg_next(imxdmac, sg);
+	imxdma_sg_next(d, sg);
 
 	return 0;
 }
@@ -519,13 +499,26 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
 	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	int chno = imxdmac->channel;
+	struct imxdma_desc *desc;
 
 	if (imxdma->sg) {
 		u32 tmp;
 		imxdma->sg = sg_next(imxdma->sg);
 
 		if (imxdma->sg) {
-			imxdma_sg_next(imxdmac, imxdma->sg);
+
+			spin_lock(&imxdmac->lock);
+			if (list_empty(&imxdmac->ld_active)) {
+				spin_unlock(&imxdmac->lock);
+				goto out;
+			}
+
+			desc = list_first_entry(&imxdmac->ld_active,
+						struct imxdma_desc,
+						node);
+			spin_unlock(&imxdmac->lock);
+
+			imxdma_sg_next(desc, imxdma->sg);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -558,6 +551,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		}
 	}
 
+out:
 	imx_dmav1_writel(0, DMA_CCR(chno));
 	imxdma->in_use = 0;
 	/* Tasklet irq */
@@ -601,8 +595,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 					  d->config_port, d->config_mem, 0, 0);
 		if (ret < 0)
 			return ret;
-		ret = imxdma_setup_single_hw(imxdmac, d->src,
-					   d->len, d->dest, d->dmamode);
+		ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
 		if (ret < 0)
 			return ret;
 		break;
@@ -610,19 +603,15 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		if (d->dmamode == DMA_MODE_READ)
-			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
-				       d->sgcount, d->len, d->src, d->dmamode);
-		else
-			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
-				      d->sgcount, d->len, d->dest, d->dmamode);
+		ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
+					 imxdmac->per_address, d->direction);
 		if (ret < 0)
 			return ret;
 		break;
 	default:
 		return -EINVAL;
 	}
-	imxdma_enable_hw(imxdmac);
+	imxdma_enable_hw(d);
 	return 0;
 }
 
@@ -867,11 +856,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
 	desc->sg = sgl;
 	desc->sgcount = sg_len;
 	desc->len = dma_length;
+	desc->direction = direction;
 	if (direction == DMA_DEV_TO_MEM) {
-		desc->dmamode = DMA_MODE_READ;
 		desc->src = imxdmac->per_address;
 	} else {
-		desc->dmamode = DMA_MODE_WRITE;
 		desc->dest = imxdmac->per_address;
 	}
 	desc->desc.callback = NULL;
@@ -927,11 +915,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
 	desc->sg = imxdmac->sg_list;
 	desc->sgcount = periods;
 	desc->len = IMX_DMA_LENGTH_LOOP;
+	desc->direction = direction;
 	if (direction == DMA_DEV_TO_MEM) {
-		desc->dmamode = DMA_MODE_READ;
 		desc->src = imxdmac->per_address;
 	} else {
-		desc->dmamode = DMA_MODE_WRITE;
 		desc->dest = imxdmac->per_address;
 	}
 	desc->desc.callback = NULL;
@@ -961,7 +948,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
 	desc->src = src;
 	desc->dest = dest;
 	desc->len = len;
-	desc->dmamode = DMA_MODE_WRITE;
+	desc->direction = DMA_MEM_TO_MEM;
 	desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 	desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 	desc->desc.callback = NULL;
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:26 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:26 +0100
Subject: [PATCH 04/14] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw'
 function.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-5-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   57 ++++++++++++-------------------------------------
 1 files changed, 14 insertions(+), 43 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 2c524e1..8a0afb1 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -260,41 +260,6 @@ static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 	return now;
 }
 
-static int
-imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr)
-{
-	int channel = imxdmac->channel;
-
-	imxdmac->internal.sg = NULL;
-
-	if (!dma_address) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!dma_length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-		"dev_addr=0x%08x for write\n",
-		channel, __func__, (unsigned int)dma_address,
-		dma_length, dev_addr);
-
-	imx_dmav1_writel(dma_address, DMA_SAR(channel));
-	imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-	imx_dmav1_writel(imxdmac->internal.ccr_to_device,
-			 DMA_CCR(channel));
-
-	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
-	return 0;
-}
-
 static void imxdma_enable_hw(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -586,20 +551,26 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int ret;
 
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		ret = imxdma_config_channel_hw(imxdmac,
-					  d->config_port, d->config_mem, 0, 0);
-		if (ret < 0)
-			return ret;
-		ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
-		if (ret < 0)
-			return ret;
-		break;
+		imxdmac->internal.sg = NULL;
+
+		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+			 DMA_CCR(imxdmac->channel));
 
+		imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+
+		dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
+			"dma_length=%d\n", __func__, imxdmac->channel,
+			d->dest, d->src, d->len);
+
+		break;
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:27 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:27 +0100
Subject: [PATCH 05/14] dmaengine: imx-dma: remove 'imxdma_config_channel_hw'
 function.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-6-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   46 +++++++++++++---------------------------------
 1 files changed, 13 insertions(+), 33 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 8a0afb1..5432b04 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -314,32 +314,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 }
 
 static int
-imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
-	int channel = imxdmac->channel;
-	u32 dreq = 0;
-
-	imxdmac->internal.hw_chaining = 0;
-
-	if (hw_chaining) {
-		imxdmac->internal.hw_chaining = 1;
-		if (!imxdma_hw_chain(&imxdmac->internal))
-			return -EINVAL;
-	}
-
-	if (dmareq)
-		dreq = CCR_REN;
-
-	imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
-	imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
-
-	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
-	return 0;
-}
-
-static int
 imxdma_setup_sg_hw(struct imxdma_desc *d,
 		 struct scatterlist *sg, unsigned int sgcount,
 		 unsigned int dma_length, unsigned int dev_addr,
@@ -628,7 +602,6 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct dma_slave_config *dmaengine_cfg = (void *)arg;
-	int ret;
 	unsigned long flags;
 	unsigned int mode = 0;
 
@@ -664,13 +637,20 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			mode = IMX_DMA_MEMSIZE_32;
 			break;
 		}
-		ret = imxdma_config_channel_hw(imxdmac,
-				mode | IMX_DMA_TYPE_FIFO,
-				IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
-				imxdmac->dma_request, 1);
 
-		if (ret)
-			return ret;
+		imxdmac->internal.hw_chaining = 1;
+		if (!imxdma_hw_chain(&imxdmac->internal))
+			return -EINVAL;
+		imxdmac->internal.ccr_from_device =
+			(mode | IMX_DMA_TYPE_FIFO) |
+			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
+			CCR_REN;
+		imxdmac->internal.ccr_to_device =
+			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
+			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
+		imx_dmav1_writel(imxdmac->dma_request,
+				 DMA_RSSR(imxdmac->channel));
+
 		/* Set burst length */
 		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
 				 DMA_BLR(imxdmac->channel));
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:28 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:28 +0100
Subject: [PATCH 06/14] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw'
 function.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-7-git-send-email-javier.martin@vista-silicon.com>

Removing this function allows moving 'ccr_to_device' and
'ccr_from_device' from internal struct to channel struct.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   97 ++++++++++++++++++-------------------------------
 1 files changed, 35 insertions(+), 62 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 5432b04..cb45aff 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -133,9 +133,6 @@ struct imxdma_channel_internal {
 
 	int in_use;
 
-	u32 ccr_from_device;
-	u32 ccr_to_device;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -180,6 +177,8 @@ struct imxdma_channel {
 	dma_cookie_t			last_completed;
 	int				dma_request;
 	struct scatterlist		*sg_list;
+	u32				ccr_from_device;
+	u32				ccr_to_device;
 };
 
 #define MAX_DMA_CHANNELS 8
@@ -313,58 +312,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	local_irq_restore(flags);
 }
 
-static int
-imxdma_setup_sg_hw(struct imxdma_desc *d,
-		 struct scatterlist *sg, unsigned int sgcount,
-		 unsigned int dma_length, unsigned int dev_addr,
-		 enum dma_transfer_direction direction)
-{
-	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
-	int channel = imxdmac->channel;
-
-	if (imxdmac->internal.in_use)
-		return -EBUSY;
-
-	imxdmac->internal.sg = sg;
-	imxdmac->internal.resbytes = dma_length;
-
-	if (!sg || !sgcount) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!sg->length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (direction == DMA_DEV_TO_MEM) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if (direction == DMA_MEM_TO_DEV) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imxdma_sg_next(d, sg);
-
-	return 0;
-}
-
 static void imxdma_watchdog(unsigned long data)
 {
 	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
@@ -548,10 +495,37 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
-					 imxdmac->per_address, d->direction);
-		if (ret < 0)
-			return ret;
+		imxdmac->internal.sg = d->sg;
+		imxdmac->internal.resbytes = d->len;
+
+		if (d->direction == DMA_DEV_TO_MEM) {
+			imx_dmav1_writel(imxdmac->per_address,
+					 DMA_SAR(imxdmac->channel));
+			imx_dmav1_writel(imxdmac->ccr_from_device,
+					 DMA_CCR(imxdmac->channel));
+
+			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+				"total length=%d dev_addr=0x%08x (dev2mem)\n",
+				__func__, imxdmac->channel, d->sg, d->sgcount,
+				d->len, imxdmac->per_address);
+		} else if (d->direction == DMA_MEM_TO_DEV) {
+			imx_dmav1_writel(imxdmac->per_address,
+					 DMA_DAR(imxdmac->channel));
+			imx_dmav1_writel(imxdmac->ccr_to_device,
+					 DMA_CCR(imxdmac->channel));
+
+			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+				"total length=%d dev_addr=0x%08x (mem2dev)\n",
+				__func__, imxdmac->channel, d->sg, d->sgcount,
+				d->len, imxdmac->per_address);
+		} else {
+			dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
+				__func__, imxdmac->channel);
+			return -EINVAL;
+		}
+
+		imxdma_sg_next(d, d->sg);
+
 		break;
 	default:
 		return -EINVAL;
@@ -641,11 +615,10 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		imxdmac->internal.hw_chaining = 1;
 		if (!imxdma_hw_chain(&imxdmac->internal))
 			return -EINVAL;
-		imxdmac->internal.ccr_from_device =
-			(mode | IMX_DMA_TYPE_FIFO) |
+		imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
 			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
 			CCR_REN;
-		imxdmac->internal.ccr_to_device =
+		imxdmac->ccr_to_device =
 			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
 			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
 		imx_dmav1_writel(imxdmac->dma_request,
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:29 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:29 +0100
Subject: [PATCH 07/14] dmaengine: imx-dma: remove sg member from internal
 structure.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-8-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   42 ++++++++++++++++++------------------------
 1 files changed, 18 insertions(+), 24 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index cb45aff..ed94207 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -128,7 +128,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	struct scatterlist *sg;
 	unsigned int resbytes;
 
 	int in_use;
@@ -278,11 +277,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
-		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
-		if (imxdmac->internal.sg) {
+			d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+		d->sg = sg_next(d->sg);
+		if (d->sg) {
 			u32 tmp;
-			imxdma_sg_next(d, imxdmac->internal.sg);
+			imxdma_sg_next(d, d->sg);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -319,7 +318,6 @@ static void imxdma_watchdog(unsigned long data)
 
 	imx_dmav1_writel(0, DMA_CCR(channel));
 	imxdmac->internal.in_use = 0;
-	imxdmac->internal.sg = NULL;
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -387,24 +385,23 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
-	if (imxdma->sg) {
-		u32 tmp;
-		imxdma->sg = sg_next(imxdma->sg);
-
-		if (imxdma->sg) {
+	spin_lock(&imxdmac->lock);
+	if (list_empty(&imxdmac->ld_active)) {
+		spin_unlock(&imxdmac->lock);
+		goto out;
+	}
 
-			spin_lock(&imxdmac->lock);
-			if (list_empty(&imxdmac->ld_active)) {
-				spin_unlock(&imxdmac->lock);
-				goto out;
-			}
+	desc = list_first_entry(&imxdmac->ld_active,
+				struct imxdma_desc,
+				node);
+	spin_unlock(&imxdmac->lock);
 
-			desc = list_first_entry(&imxdmac->ld_active,
-						struct imxdma_desc,
-						node);
-			spin_unlock(&imxdmac->lock);
+	if (desc->sg) {
+		u32 tmp;
+		desc->sg = sg_next(desc->sg);
 
-			imxdma_sg_next(desc, imxdma->sg);
+		if (desc->sg) {
+			imxdma_sg_next(desc, desc->sg);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -478,8 +475,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		imxdmac->internal.sg = NULL;
-
 		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
 		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
 		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
@@ -495,7 +490,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		imxdmac->internal.sg = d->sg;
 		imxdmac->internal.resbytes = d->len;
 
 		if (d->direction == DMA_DEV_TO_MEM) {
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:30 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:30 +0100
Subject: [PATCH 08/14] dmaengine: imx-dma: remove in_use field of internal
 structure.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-9-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   10 ----------
 1 files changed, 0 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index ed94207..1e66ee6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -130,8 +130,6 @@ enum  imxdma_prep_type {
 struct imxdma_channel_internal {
 	unsigned int resbytes;
 
-	int in_use;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -266,9 +264,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 	pr_debug("imxdma%d: imx_dma_enable\n", channel);
 
-	if (imxdmac->internal.in_use)
-		return;
-
 	local_irq_save(flags);
 
 	imx_dmav1_writel(1 << channel, DMA_DISR);
@@ -287,7 +282,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 				DMA_CCR(channel));
 		}
 	}
-	imxdmac->internal.in_use = 1;
 
 	local_irq_restore(flags);
 }
@@ -307,7 +301,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
 			DMA_CCR(channel));
 	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdmac->internal.in_use = 0;
 	local_irq_restore(flags);
 }
 
@@ -317,7 +310,6 @@ static void imxdma_watchdog(unsigned long data)
 	int channel = imxdmac->channel;
 
 	imx_dmav1_writel(0, DMA_CCR(channel));
-	imxdmac->internal.in_use = 0;
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -436,7 +428,6 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 
 out:
 	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
 	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
@@ -470,7 +461,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
-	int ret;
 
 	/* Configure and enable */
 	switch (d->type) {
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:31 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:31 +0100
Subject: [PATCH 09/14] dmaengine: imx-dma: remove resbytes field of internal
 structure.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-10-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   11 +++--------
 1 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 1e66ee6..d525f1e 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -128,8 +128,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	unsigned int resbytes;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -233,12 +231,11 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
 static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
-	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	unsigned long now;
 
-	now = min(imxdma->resbytes, sg->length);
-	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
-		imxdma->resbytes -= now;
+	now = min(d->len, sg->length);
+	if (d->len != IMX_DMA_LENGTH_LOOP)
+		d->len -= now;
 
 	if (d->direction == DMA_DEV_TO_MEM)
 		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
@@ -480,8 +477,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		imxdmac->internal.resbytes = d->len;
-
 		if (d->direction == DMA_DEV_TO_MEM) {
 			imx_dmav1_writel(imxdmac->per_address,
 					 DMA_SAR(imxdmac->channel));
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:32 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:32 +0100
Subject: [PATCH 10/14] dmaengine: imx-dma: remove internal structure.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-11-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   64 +++++++++++++-----------------------------------
 1 files changed, 18 insertions(+), 46 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index d525f1e..2f72447 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -110,29 +110,6 @@ enum  imxdma_prep_type {
 	IMXDMA_DESC_CYCLIC,
 };
 
-/*
- * struct imxdma_channel_internal - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- *            (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imxdma_channel_internal only as extension to it.
- */
-
-struct imxdma_channel_internal {
-	struct timer_list watchdog;
-
-	int hw_chaining;
-};
-
 struct imxdma_desc {
 	struct list_head		node;
 	struct dma_async_tx_descriptor	desc;
@@ -155,7 +132,8 @@ struct imxdma_desc {
 };
 
 struct imxdma_channel {
-	struct imxdma_channel_internal	internal;
+	int				hw_chaining;
+	struct timer_list		watchdog;
 	struct imxdma_engine		*imxdma;
 	unsigned int			channel;
 
@@ -217,10 +195,10 @@ static unsigned imx_dmav1_readl(unsigned offset)
 	return __raw_readl(imx_dmav1_baseaddr + offset);
 }
 
-static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
+static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 {
 	if (cpu_is_mx27())
-		return imxdma->hw_chaining;
+		return imxdmac->hw_chaining;
 	else
 		return 0;
 }
@@ -269,7 +247,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+			d->sg && imxdma_hw_chain(imxdmac)) {
 		d->sg = sg_next(d->sg);
 		if (d->sg) {
 			u32 tmp;
@@ -290,8 +268,8 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 
 	pr_debug("imxdma%d: imx_dma_disable\n", channel);
 
-	if (imxdma_hw_chain(&imxdmac->internal))
-		del_timer(&imxdmac->internal.watchdog);
+	if (imxdma_hw_chain(imxdmac))
+		del_timer(&imxdmac->watchdog);
 
 	local_irq_save(flags);
 	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
@@ -316,7 +294,6 @@ static void imxdma_watchdog(unsigned long data)
 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 {
 	struct imxdma_engine *imxdma = dev_id;
-	struct imxdma_channel_internal *internal;
 	unsigned int err_mask;
 	int i, disr;
 	int errcode;
@@ -336,7 +313,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (!(err_mask & (1 << i)))
 			continue;
-		internal = &imxdma->channel[i].internal;
 		errcode = 0;
 
 		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
@@ -370,7 +346,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 
 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
-	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
@@ -394,11 +369,11 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
-			if (imxdma_hw_chain(imxdma)) {
+			if (imxdma_hw_chain(imxdmac)) {
 				/* FIXME: The timeout should probably be
 				 * configurable
 				 */
-				mod_timer(&imxdma->watchdog,
+				mod_timer(&imxdmac->watchdog,
 					jiffies + msecs_to_jiffies(500));
 
 				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
@@ -417,8 +392,8 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 			return;
 		}
 
-		if (imxdma_hw_chain(imxdma)) {
-			del_timer(&imxdma->watchdog);
+		if (imxdma_hw_chain(imxdmac)) {
+			del_timer(&imxdmac->watchdog);
 			return;
 		}
 	}
@@ -432,7 +407,6 @@ out:
 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 {
 	struct imxdma_engine *imxdma = dev_id;
-	struct imxdma_channel_internal *internal;
 	int i, disr;
 
 	if (cpu_is_mx21() || cpu_is_mx27())
@@ -445,10 +419,8 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 
 	imx_dmav1_writel(disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (disr & (1 << i)) {
-			internal = &imxdma->channel[i].internal;
+		if (disr & (1 << i))
 			dma_irq_handle_channel(&imxdma->channel[i]);
-		}
 	}
 
 	return IRQ_HANDLED;
@@ -591,8 +563,8 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			break;
 		}
 
-		imxdmac->internal.hw_chaining = 1;
-		if (!imxdma_hw_chain(&imxdmac->internal))
+		imxdmac->hw_chaining = 1;
+		if (!imxdma_hw_chain(imxdmac))
 			return -EINVAL;
 		imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
 			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
@@ -944,7 +916,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	/* Initialize channel parameters */
 	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
 		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-		memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+
 		if (cpu_is_mx21() || cpu_is_mx27()) {
 			ret = request_irq(MX2x_INT_DMACH0 + i,
 					dma_irq_handler, 0, "DMA", imxdma);
@@ -953,9 +925,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
 						MX2x_INT_DMACH0 + i, i);
 				goto err_init;
 			}
-			init_timer(&imxdmac->internal.watchdog);
-			imxdmac->internal.watchdog.function = &imxdma_watchdog;
-			imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
+			init_timer(&imxdmac->watchdog);
+			imxdmac->watchdog.function = &imxdma_watchdog;
+			imxdmac->watchdog.data = (unsigned long)imxdmac;
 		}
 
 		imxdmac->imxdma = imxdma;
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:33 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:33 +0100
Subject: [PATCH 11/14] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-12-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 2f72447..d65eec6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -206,9 +206,10 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 /*
  * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
  */
-static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct scatterlist *sg = d->sg;
 	unsigned long now;
 
 	now = min(d->len, sg->length);
@@ -251,7 +252,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		d->sg = sg_next(d->sg);
 		if (d->sg) {
 			u32 tmp;
-			imxdma_sg_next(d, d->sg);
+			imxdma_sg_next(d);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -365,7 +366,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		desc->sg = sg_next(desc->sg);
 
 		if (desc->sg) {
-			imxdma_sg_next(desc, desc->sg);
+			imxdma_sg_next(desc);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -475,7 +476,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 			return -EINVAL;
 		}
 
-		imxdma_sg_next(d, d->sg);
+		imxdma_sg_next(d);
 
 		break;
 	default:
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:34 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:34 +0100
Subject: [PATCH 12/14] dmaengine: imx-dma: integrate 'imx_dmav1_baseaddr' and
 'dma_clk' inside dmaengine structure.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-13-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |  169 +++++++++++++++++++++++++++----------------------
 1 files changed, 93 insertions(+), 76 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index d65eec6..fe0f126 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -160,6 +160,8 @@ struct imxdma_engine {
 	struct device			*dev;
 	struct device_dma_parameters	dma_parms;
 	struct dma_device		dma_device;
+	void __iomem			*base;
+	struct clk			*dma_clk;
 	struct imxdma_channel		channel[MAX_DMA_CHANNELS];
 };
 
@@ -181,18 +183,17 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 	return false;
 }
 
-/* TODO: put this inside any struct */
-static void __iomem *imx_dmav1_baseaddr;
-static struct clk *dma_clk;
 
-static void imx_dmav1_writel(unsigned val, unsigned offset)
+
+static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
+			     unsigned offset)
 {
-	__raw_writel(val, imx_dmav1_baseaddr + offset);
+	__raw_writel(val, imxdma->base + offset);
 }
 
-static unsigned imx_dmav1_readl(unsigned offset)
+static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
 {
-	return __raw_readl(imx_dmav1_baseaddr + offset);
+	return __raw_readl(imxdma->base + offset);
 }
 
 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
@@ -209,6 +210,7 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 static inline int imxdma_sg_next(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	struct scatterlist *sg = d->sg;
 	unsigned long now;
 
@@ -217,17 +219,19 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 		d->len -= now;
 
 	if (d->direction == DMA_DEV_TO_MEM)
-		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, sg->dma_address,
+				 DMA_DAR(imxdmac->channel));
 	else
-		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, sg->dma_address,
+				 DMA_SAR(imxdmac->channel));
 
-	imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+	imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
 
 	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
 		"size 0x%08x\n", imxdmac->channel,
-		 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
-		 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
-		 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
+		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
+		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
 
 	return now;
 }
@@ -235,6 +239,7 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 static void imxdma_enable_hw(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -242,10 +247,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 	local_irq_save(flags);
 
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
-		CCR_ACRPT, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
+			 ~(1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
+			 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
 			d->sg && imxdma_hw_chain(imxdmac)) {
@@ -253,9 +259,9 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		if (d->sg) {
 			u32 tmp;
 			imxdma_sg_next(d);
-			tmp = imx_dmav1_readl(DMA_CCR(channel));
-			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
-				DMA_CCR(channel));
+			tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
+			imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
+					 DMA_CCR(channel));
 		}
 	}
 
@@ -264,6 +270,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 {
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -273,19 +280,21 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 		del_timer(&imxdmac->watchdog);
 
 	local_irq_save(flags);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
-			DMA_CCR(channel));
-	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
+			 (1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
+			 ~CCR_CEN, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
 	local_irq_restore(flags);
 }
 
 static void imxdma_watchdog(unsigned long data)
 {
 	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 
-	imx_dmav1_writel(0, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -299,37 +308,37 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 	int i, disr;
 	int errcode;
 
-	disr = imx_dmav1_readl(DMA_DISR);
+	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
-	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
-		   imx_dmav1_readl(DMA_DRTOSR) |
-		   imx_dmav1_readl(DMA_DSESR)  |
-		   imx_dmav1_readl(DMA_DBOSR);
+	err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
+		   imx_dmav1_readl(imxdma, DMA_DRTOSR) |
+		   imx_dmav1_readl(imxdma, DMA_DSESR)  |
+		   imx_dmav1_readl(imxdma, DMA_DBOSR);
 
 	if (!err_mask)
 		return IRQ_HANDLED;
 
-	imx_dmav1_writel(disr & err_mask, DMA_DISR);
+	imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
 
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (!(err_mask & (1 << i)))
 			continue;
 		errcode = 0;
 
-		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBTOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
 			errcode |= IMX_DMA_ERR_BURST;
 		}
-		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DRTOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
 			errcode |= IMX_DMA_ERR_REQUEST;
 		}
-		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DSESR);
+		if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
 			errcode |= IMX_DMA_ERR_TRANSFER;
 		}
-		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
 			errcode |= IMX_DMA_ERR_BUFFER;
 		}
 		/* Tasklet error handler */
@@ -347,6 +356,7 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 
 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
@@ -368,7 +378,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		if (desc->sg) {
 			imxdma_sg_next(desc);
 
-			tmp = imx_dmav1_readl(DMA_CCR(chno));
+			tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
 
 			if (imxdma_hw_chain(imxdmac)) {
 				/* FIXME: The timeout should probably be
@@ -378,13 +388,14 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 					jiffies + msecs_to_jiffies(500));
 
 				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
-				imx_dmav1_writel(tmp, DMA_CCR(chno));
+				imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 			} else {
-				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+				imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
+						 DMA_CCR(chno));
 				tmp |= CCR_CEN;
 			}
 
-			imx_dmav1_writel(tmp, DMA_CCR(chno));
+			imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 
 			if (imxdma_chan_is_doing_cyclic(imxdmac))
 				/* Tasklet progression */
@@ -400,7 +411,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 	}
 
 out:
-	imx_dmav1_writel(0, DMA_CCR(chno));
+	imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
 	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
@@ -413,12 +424,12 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 	if (cpu_is_mx21() || cpu_is_mx27())
 		imxdma_err_handler(irq, dev_id);
 
-	disr = imx_dmav1_readl(DMA_DISR);
+	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
 	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
 		     disr);
 
-	imx_dmav1_writel(disr, DMA_DISR);
+	imx_dmav1_writel(imxdma, disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (disr & (1 << i))
 			dma_irq_handle_channel(&imxdma->channel[i]);
@@ -435,12 +446,12 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
-		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
-		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+		imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
 			 DMA_CCR(imxdmac->channel));
 
-		imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
 
 		dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
 			"dma_length=%d\n", __func__, imxdmac->channel,
@@ -451,9 +462,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
 		if (d->direction == DMA_DEV_TO_MEM) {
-			imx_dmav1_writel(imxdmac->per_address,
+			imx_dmav1_writel(imxdma, imxdmac->per_address,
 					 DMA_SAR(imxdmac->channel));
-			imx_dmav1_writel(imxdmac->ccr_from_device,
+			imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
 					 DMA_CCR(imxdmac->channel));
 
 			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -461,9 +472,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 				__func__, imxdmac->channel, d->sg, d->sgcount,
 				d->len, imxdmac->per_address);
 		} else if (d->direction == DMA_MEM_TO_DEV) {
-			imx_dmav1_writel(imxdmac->per_address,
+			imx_dmav1_writel(imxdma, imxdmac->per_address,
 					 DMA_DAR(imxdmac->channel));
-			imx_dmav1_writel(imxdmac->ccr_to_device,
+			imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
 					 DMA_CCR(imxdmac->channel));
 
 			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -528,6 +539,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct dma_slave_config *dmaengine_cfg = (void *)arg;
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	unsigned long flags;
 	unsigned int mode = 0;
 
@@ -573,12 +585,12 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		imxdmac->ccr_to_device =
 			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
 			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
-		imx_dmav1_writel(imxdmac->dma_request,
+		imx_dmav1_writel(imxdma, imxdmac->dma_request,
 				 DMA_RSSR(imxdmac->channel));
 
 		/* Set burst length */
-		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
-				 DMA_BLR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, imxdmac->watermark_level *
+				imxdmac->word_size, DMA_BLR(imxdmac->channel));
 
 		return 0;
 	default:
@@ -863,27 +875,35 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	struct imxdma_engine *imxdma;
 	int ret, i;
 
-	if (cpu_is_mx1())
-		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
-	else if (cpu_is_mx21())
-		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
-	else if (cpu_is_mx27())
-		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
-	else
+
+	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
+	if (!imxdma)
+		return -ENOMEM;
+
+	if (cpu_is_mx1()) {
+		imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+	} else if (cpu_is_mx21()) {
+		imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+	} else if (cpu_is_mx27()) {
+		imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+	} else {
+		kfree(imxdma);
 		return 0;
+	}
 
-	dma_clk = clk_get(NULL, "dma");
-	if (IS_ERR(dma_clk))
-		return PTR_ERR(dma_clk);
-	clk_enable(dma_clk);
+	imxdma->dma_clk = clk_get(NULL, "dma");
+	if (IS_ERR(imxdma->dma_clk))
+		return PTR_ERR(imxdma->dma_clk);
+	clk_enable(imxdma->dma_clk);
 
 	/* reset DMA module */
-	imx_dmav1_writel(DCR_DRST, DMA_DCR);
+	imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
 
 	if (cpu_is_mx1()) {
 		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
 		if (ret) {
 			pr_crit("Can't register IRQ for DMA\n");
+			kfree(imxdma);
 			return ret;
 		}
 
@@ -891,22 +911,19 @@ static int __init imxdma_probe(struct platform_device *pdev)
 		if (ret) {
 			pr_crit("Can't register ERRIRQ for DMA\n");
 			free_irq(MX1_DMA_INT, NULL);
+			kfree(imxdma);
 			return ret;
 		}
 	}
 
 	/* enable DMA module */
-	imx_dmav1_writel(DCR_DEN, DMA_DCR);
+	imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
 
 	/* clear all interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
 
 	/* disable interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
-	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
-	if (!imxdma)
-		return -ENOMEM;
+	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
 
 	INIT_LIST_HEAD(&imxdma->dma_device.channels);
 
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:36 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:36 +0100
Subject: [PATCH 14/14] dmaengine: imx-dma: remove  dma-v1.c and dma-v1.h
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-15-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/mach-imx/dma-v1.c              |  846 -------------------------------
 arch/arm/mach-imx/include/mach/dma-v1.h |  103 ----
 2 files changed, 0 insertions(+), 949 deletions(-)
 delete mode 100644 arch/arm/mach-imx/dma-v1.c
 delete mode 100644 arch/arm/mach-imx/include/mach/dma-v1.h

diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
deleted file mode 100644
index 42afc29..0000000
--- a/arch/arm/mach-imx/dma-v1.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/*
- *  linux/arch/arm/plat-mxc/dma-v1.c
- *
- *  i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/scatterlist.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/dma-v1.h>
-
-#define DMA_DCR     0x00		/* Control Register */
-#define DMA_DISR    0x04		/* Interrupt status Register */
-#define DMA_DIMR    0x08		/* Interrupt mask Register */
-#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
-#define DMA_DRTOSR  0x10		/* Request timeout Register */
-#define DMA_DSESR   0x14		/* Transfer Error Status Register */
-#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
-#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
-#define DMA_WSRA    0x40		/* W-Size Register A */
-#define DMA_XSRA    0x44		/* X-Size Register A */
-#define DMA_YSRA    0x48		/* Y-Size Register A */
-#define DMA_WSRB    0x4c		/* W-Size Register B */
-#define DMA_XSRB    0x50		/* X-Size Register B */
-#define DMA_YSRB    0x54		/* Y-Size Register B */
-#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
-#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
-#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
-#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
-#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
-#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
-#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
-#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
-#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */
-
-#define DCR_DRST           (1<<1)
-#define DCR_DEN            (1<<0)
-#define DBTOCR_EN          (1<<15)
-#define DBTOCR_CNT(x)      ((x) & 0x7fff)
-#define CNTR_CNT(x)        ((x) & 0xffffff)
-#define CCR_ACRPT          (1<<14)
-#define CCR_DMOD_LINEAR    (0x0 << 12)
-#define CCR_DMOD_2D        (0x1 << 12)
-#define CCR_DMOD_FIFO      (0x2 << 12)
-#define CCR_DMOD_EOBFIFO   (0x3 << 12)
-#define CCR_SMOD_LINEAR    (0x0 << 10)
-#define CCR_SMOD_2D        (0x1 << 10)
-#define CCR_SMOD_FIFO      (0x2 << 10)
-#define CCR_SMOD_EOBFIFO   (0x3 << 10)
-#define CCR_MDIR_DEC       (1<<9)
-#define CCR_MSEL_B         (1<<8)
-#define CCR_DSIZ_32        (0x0 << 6)
-#define CCR_DSIZ_8         (0x1 << 6)
-#define CCR_DSIZ_16        (0x2 << 6)
-#define CCR_SSIZ_32        (0x0 << 4)
-#define CCR_SSIZ_8         (0x1 << 4)
-#define CCR_SSIZ_16        (0x2 << 4)
-#define CCR_REN            (1<<3)
-#define CCR_RPT            (1<<2)
-#define CCR_FRC            (1<<1)
-#define CCR_CEN            (1<<0)
-#define RTOR_EN            (1<<15)
-#define RTOR_CLK           (1<<14)
-#define RTOR_PSC           (1<<13)
-
-/*
- * struct imx_dma_channel - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- *            (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imx_dma_channel only as extension to it.
- */
-
-struct imx_dma_channel {
-	const char *name;
-	void (*irq_handler) (int, void *);
-	void (*err_handler) (int, void *, int errcode);
-	void (*prog_handler) (int, void *, struct scatterlist *);
-	void *data;
-	unsigned int dma_mode;
-	struct scatterlist *sg;
-	unsigned int resbytes;
-	int dma_num;
-
-	int in_use;
-
-	u32 ccr_from_device;
-	u32 ccr_to_device;
-
-	struct timer_list watchdog;
-
-	int hw_chaining;
-};
-
-static void __iomem *imx_dmav1_baseaddr;
-
-static void imx_dmav1_writel(unsigned val, unsigned offset)
-{
-	__raw_writel(val, imx_dmav1_baseaddr + offset);
-}
-
-static unsigned imx_dmav1_readl(unsigned offset)
-{
-	return __raw_readl(imx_dmav1_baseaddr + offset);
-}
-
-static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
-
-static struct clk *dma_clk;
-
-static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
-{
-	if (cpu_is_mx27())
-		return imxdma->hw_chaining;
-	else
-		return 0;
-}
-
-/*
- * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
- */
-static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long now;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return 0;
-	}
-
-	now = min(imxdma->resbytes, sg->length);
-	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
-		imxdma->resbytes -= now;
-
-	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
-		imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
-	else
-		imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
-
-	imx_dmav1_writel(now, DMA_CNTR(channel));
-
-	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
-		"size 0x%08x\n", channel,
-		 imx_dmav1_readl(DMA_DAR(channel)),
-		 imx_dmav1_readl(DMA_SAR(channel)),
-		 imx_dmav1_readl(DMA_CNTR(channel)));
-
-	return now;
-}
-
-/**
- * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
- * device transfer
- *
- * @channel: i.MX DMA channel number
- * @dma_address: the DMA/physical memory address of the linear data block
- *		to transfer
- * @dma_length: length of the data block in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- *		Zero indicates success.
- */
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr,
-		     unsigned int dmamode)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	imxdma->sg = NULL;
-	imxdma->dma_mode = dmamode;
-
-	if (!dma_address) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!dma_length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(dma_address, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dma_address, DMA_SAR(channel));
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_to_device,
-				DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_single);
-
-/**
- * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
- * @channel: i.MX DMA channel number
- * @sg: pointer to the scatter-gather list/vector
- * @sgcount: scatter-gather list hungs count
- * @dma_length: total length of the transfer request in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * The function sets up DMA channel state and registers to be ready for
- * transfer specified by provided parameters. The scatter-gather emulation
- * is set up according to the parameters.
- *
- * The full preparation of the transfer requires setup of more register
- * by the caller before imx_dma_enable() can be called.
- *
- * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
- *
- * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
- *
- * %CCR(channel) has to specify transfer parameters, the next settings is
- * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
- * specified
- *
- * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
- *
- * The typical setup for %DMA_MODE_WRITE is specified by next options
- * combination
- *
- * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
- *
- * Be careful here and do not mistakenly mix source and target device
- * port sizes constants, they are really different:
- * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
- * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- * Zero indicates success.
- */
-int
-imx_dma_setup_sg(int channel,
-		 struct scatterlist *sg, unsigned int sgcount,
-		 unsigned int dma_length, unsigned int dev_addr,
-		 unsigned int dmamode)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	if (imxdma->in_use)
-		return -EBUSY;
-
-	imxdma->sg = sg;
-	imxdma->dma_mode = dmamode;
-	imxdma->resbytes = dma_length;
-
-	if (!sg || !sgcount) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!sg->length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imx_dma_sg_next(channel, sg);
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_sg);
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	u32 dreq = 0;
-
-	imxdma->hw_chaining = 0;
-
-	if (hw_chaining) {
-		imxdma->hw_chaining = 1;
-		if (!imx_dma_hw_chain(imxdma))
-			return -EINVAL;
-	}
-
-	if (dmareq)
-		dreq = CCR_REN;
-
-	imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
-	imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
-
-	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_config_channel);
-
-void imx_dma_config_burstlen(int channel, unsigned int burstlen)
-{
-	imx_dmav1_writel(burstlen, DMA_BLR(channel));
-}
-EXPORT_SYMBOL(imx_dma_config_burstlen);
-
-/**
- * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
- * handlers
- * @channel: i.MX DMA channel number
- * @irq_handler: the pointer to the function called if the transfer
- *		ends successfully
- * @err_handler: the pointer to the function called if the premature
- *		end caused by error occurs
- * @data: user specified value to be passed to the handlers
- */
-int
-imx_dma_setup_handlers(int channel,
-		       void (*irq_handler) (int, void *),
-		       void (*err_handler) (int, void *, int),
-		       void *data)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return -ENODEV;
-	}
-
-	local_irq_save(flags);
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdma->irq_handler = irq_handler;
-	imxdma->err_handler = err_handler;
-	imxdma->data = data;
-	local_irq_restore(flags);
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_handlers);
-
-/**
- * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
- * handlers
- * @channel: i.MX DMA channel number
- * @prog_handler: the pointer to the function called if the transfer progresses
- */
-int
-imx_dma_setup_progression_handler(int channel,
-			void (*prog_handler) (int, void*, struct scatterlist*))
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return -ENODEV;
-	}
-
-	local_irq_save(flags);
-	imxdma->prog_handler = prog_handler;
-	local_irq_restore(flags);
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_progression_handler);
-
-/**
- * imx_dma_enable - function to start i.MX DMA channel operation
- * @channel: i.MX DMA channel number
- *
- * The channel has to be allocated by driver through imx_dma_request()
- * or imx_dma_request_by_prio() function.
- * The transfer parameters has to be set to the channel registers through
- * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
- * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
- * be set prior this function call by the channel user.
- */
-void imx_dma_enable(int channel)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	pr_debug("imxdma%d: imx_dma_enable\n", channel);
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return;
-	}
-
-	if (imxdma->in_use)
-		return;
-
-	local_irq_save(flags);
-
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
-		CCR_ACRPT, DMA_CCR(channel));
-
-	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			imxdma->sg && imx_dma_hw_chain(imxdma)) {
-		imxdma->sg = sg_next(imxdma->sg);
-		if (imxdma->sg) {
-			u32 tmp;
-			imx_dma_sg_next(channel, imxdma->sg);
-			tmp = imx_dmav1_readl(DMA_CCR(channel));
-			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
-				DMA_CCR(channel));
-		}
-	}
-	imxdma->in_use = 1;
-
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_enable);
-
-/**
- * imx_dma_disable - stop, finish i.MX DMA channel operatin
- * @channel: i.MX DMA channel number
- */
-void imx_dma_disable(int channel)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	pr_debug("imxdma%d: imx_dma_disable\n", channel);
-
-	if (imx_dma_hw_chain(imxdma))
-		del_timer(&imxdma->watchdog);
-
-	local_irq_save(flags);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
-			DMA_CCR(channel));
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdma->in_use = 0;
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_disable);
-
-static void imx_dma_watchdog(unsigned long chno)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
-	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
-	imxdma->sg = NULL;
-
-	if (imxdma->err_handler)
-		imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
-}
-
-static irqreturn_t dma_err_handler(int irq, void *dev_id)
-{
-	int i, disr;
-	struct imx_dma_channel *imxdma;
-	unsigned int err_mask;
-	int errcode;
-
-	disr = imx_dmav1_readl(DMA_DISR);
-
-	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
-		   imx_dmav1_readl(DMA_DRTOSR) |
-		   imx_dmav1_readl(DMA_DSESR)  |
-		   imx_dmav1_readl(DMA_DBOSR);
-
-	if (!err_mask)
-		return IRQ_HANDLED;
-
-	imx_dmav1_writel(disr & err_mask, DMA_DISR);
-
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (!(err_mask & (1 << i)))
-			continue;
-		imxdma = &imx_dma_channels[i];
-		errcode = 0;
-
-		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBTOSR);
-			errcode |= IMX_DMA_ERR_BURST;
-		}
-		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DRTOSR);
-			errcode |= IMX_DMA_ERR_REQUEST;
-		}
-		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DSESR);
-			errcode |= IMX_DMA_ERR_TRANSFER;
-		}
-		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBOSR);
-			errcode |= IMX_DMA_ERR_BUFFER;
-		}
-		if (imxdma->name && imxdma->err_handler) {
-			imxdma->err_handler(i, imxdma->data, errcode);
-			continue;
-		}
-
-		imx_dma_channels[i].sg = NULL;
-
-		printk(KERN_WARNING
-		       "DMA timeout on channel %d (%s) -%s%s%s%s\n",
-		       i, imxdma->name,
-		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
-		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
-		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
-		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
-	}
-	return IRQ_HANDLED;
-}
-
-static void dma_irq_handle_channel(int chno)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
-	if (!imxdma->name) {
-		/*
-		 * IRQ for an unregistered DMA channel:
-		 * let's clear the interrupts and disable it.
-		 */
-		printk(KERN_WARNING
-		       "spurious IRQ for DMA channel %d\n", chno);
-		return;
-	}
-
-	if (imxdma->sg) {
-		u32 tmp;
-		struct scatterlist *current_sg = imxdma->sg;
-		imxdma->sg = sg_next(imxdma->sg);
-
-		if (imxdma->sg) {
-			imx_dma_sg_next(chno, imxdma->sg);
-
-			tmp = imx_dmav1_readl(DMA_CCR(chno));
-
-			if (imx_dma_hw_chain(imxdma)) {
-				/* FIXME: The timeout should probably be
-				 * configurable
-				 */
-				mod_timer(&imxdma->watchdog,
-					jiffies + msecs_to_jiffies(500));
-
-				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
-				imx_dmav1_writel(tmp, DMA_CCR(chno));
-			} else {
-				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
-				tmp |= CCR_CEN;
-			}
-
-			imx_dmav1_writel(tmp, DMA_CCR(chno));
-
-			if (imxdma->prog_handler)
-				imxdma->prog_handler(chno, imxdma->data,
-						current_sg);
-
-			return;
-		}
-
-		if (imx_dma_hw_chain(imxdma)) {
-			del_timer(&imxdma->watchdog);
-			return;
-		}
-	}
-
-	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
-	if (imxdma->irq_handler)
-		imxdma->irq_handler(chno, imxdma->data);
-}
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-	int i, disr;
-
-	if (cpu_is_mx21() || cpu_is_mx27())
-		dma_err_handler(irq, dev_id);
-
-	disr = imx_dmav1_readl(DMA_DISR);
-
-	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
-		     disr);
-
-	imx_dmav1_writel(disr, DMA_DISR);
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (disr & (1 << i))
-			dma_irq_handle_channel(i);
-	}
-
-	return IRQ_HANDLED;
-}
-
-/**
- * imx_dma_request - request/allocate specified channel number
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- */
-int imx_dma_request(int channel, const char *name)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-	int ret = 0;
-
-	/* basic sanity checks */
-	if (!name)
-		return -EINVAL;
-
-	if (channel >= IMX_DMA_CHANNELS) {
-		printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
-		       __func__, channel);
-		return -EINVAL;
-	}
-
-	local_irq_save(flags);
-	if (imxdma->name) {
-		local_irq_restore(flags);
-		return -EBUSY;
-	}
-	memset(imxdma, 0, sizeof(*imxdma));
-	imxdma->name = name;
-	local_irq_restore(flags); /* request_irq() can block */
-
-	if (cpu_is_mx21() || cpu_is_mx27()) {
-		ret = request_irq(MX2x_INT_DMACH0 + channel,
-				dma_irq_handler, 0, "DMA", NULL);
-		if (ret) {
-			imxdma->name = NULL;
-			pr_crit("Can't register IRQ %d for DMA channel %d\n",
-					MX2x_INT_DMACH0 + channel, channel);
-			return ret;
-		}
-		init_timer(&imxdma->watchdog);
-		imxdma->watchdog.function = &imx_dma_watchdog;
-		imxdma->watchdog.data = channel;
-	}
-
-	return ret;
-}
-EXPORT_SYMBOL(imx_dma_request);
-
-/**
- * imx_dma_free - release previously acquired channel
- * @channel: i.MX DMA channel number
- */
-void imx_dma_free(int channel)
-{
-	unsigned long flags;
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT
-		       "%s: trying to free free channel %d\n",
-		       __func__, channel);
-		return;
-	}
-
-	local_irq_save(flags);
-	/* Disable interrupts */
-	imx_dma_disable(channel);
-	imxdma->name = NULL;
-
-	if (cpu_is_mx21() || cpu_is_mx27())
-		free_irq(MX2x_INT_DMACH0 + channel, NULL);
-
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_free);
-
-/**
- * imx_dma_request_by_prio - find and request some of free channels best
- * suiting requested priority
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- *
- * This function tries to find a free channel in the specified priority group
- * if the priority cannot be achieved it tries to look for free channel
- * in the higher and then even lower priority groups.
- *
- * Return value: If there is no free channel to allocate, -%ENODEV is returned.
- *               On successful allocation channel is returned.
- */
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
-{
-	int i;
-	int best;
-
-	switch (prio) {
-	case (DMA_PRIO_HIGH):
-		best = 8;
-		break;
-	case (DMA_PRIO_MEDIUM):
-		best = 4;
-		break;
-	case (DMA_PRIO_LOW):
-	default:
-		best = 0;
-		break;
-	}
-
-	for (i = best; i < IMX_DMA_CHANNELS; i++)
-		if (!imx_dma_request(i, name))
-			return i;
-
-	for (i = best - 1; i >= 0; i--)
-		if (!imx_dma_request(i, name))
-			return i;
-
-	printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
-
-	return -ENODEV;
-}
-EXPORT_SYMBOL(imx_dma_request_by_prio);
-
-static int __init imx_dma_init(void)
-{
-	int ret = 0;
-	int i;
-
-	if (cpu_is_mx1())
-		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
-	else if (cpu_is_mx21())
-		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
-	else if (cpu_is_mx27())
-		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
-	else
-		return 0;
-
-	dma_clk = clk_get(NULL, "dma");
-	if (IS_ERR(dma_clk))
-		return PTR_ERR(dma_clk);
-	clk_enable(dma_clk);
-
-	/* reset DMA module */
-	imx_dmav1_writel(DCR_DRST, DMA_DCR);
-
-	if (cpu_is_mx1()) {
-		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
-		if (ret) {
-			pr_crit("Wow!  Can't register IRQ for DMA\n");
-			return ret;
-		}
-
-		ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
-		if (ret) {
-			pr_crit("Wow!  Can't register ERRIRQ for DMA\n");
-			free_irq(MX1_DMA_INT, NULL);
-			return ret;
-		}
-	}
-
-	/* enable DMA module */
-	imx_dmav1_writel(DCR_DEN, DMA_DCR);
-
-	/* clear all interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
-
-	/* disable interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		imx_dma_channels[i].sg = NULL;
-		imx_dma_channels[i].dma_num = i;
-	}
-
-	return ret;
-}
-
-arch_initcall(imx_dma_init);
diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h
deleted file mode 100644
index ac6fd71..0000000
--- a/arch/arm/mach-imx/include/mach/dma-v1.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- *  linux/arch/arm/mach-imx/include/mach/dma-v1.h
- *
- *  i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_DMA_V1_H__
-#define __MACH_DMA_V1_H__
-
-#define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
-
-#include <mach/dma.h>
-
-#define IMX_DMA_CHANNELS  16
-
-#define DMA_MODE_READ		0
-#define DMA_MODE_WRITE		1
-#define DMA_MODE_MASK		1
-
-#define MX1_DMA_REG(offset)	MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
-
-/* DMA Interrupt Mask Register */
-#define MX1_DMA_DIMR		MX1_DMA_REG(0x08)
-
-/* Channel Control Register */
-#define MX1_DMA_CCR(x)		MX1_DMA_REG(0x8c + ((x) << 6))
-
-#define IMX_DMA_MEMSIZE_32	(0 << 4)
-#define IMX_DMA_MEMSIZE_8	(1 << 4)
-#define IMX_DMA_MEMSIZE_16	(2 << 4)
-#define IMX_DMA_TYPE_LINEAR	(0 << 10)
-#define IMX_DMA_TYPE_2D		(1 << 10)
-#define IMX_DMA_TYPE_FIFO	(2 << 10)
-
-#define IMX_DMA_ERR_BURST     (1 << 0)
-#define IMX_DMA_ERR_REQUEST   (1 << 1)
-#define IMX_DMA_ERR_TRANSFER  (1 << 2)
-#define IMX_DMA_ERR_BUFFER    (1 << 3)
-#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining);
-
-void
-imx_dma_config_burstlen(int channel, unsigned int burstlen);
-
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
-		unsigned int dma_length, unsigned int dev_addr,
-		unsigned int dmamode);
-
-
-/*
- * Use this flag as the dma_length argument to imx_dma_setup_sg()
- * to create an endless running dma loop. The end of the scatterlist
- * must be linked to the beginning for this to work.
- */
-#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
-
-int
-imx_dma_setup_sg(int channel, struct scatterlist *sg,
-		unsigned int sgcount, unsigned int dma_length,
-		unsigned int dev_addr, unsigned int dmamode);
-
-int
-imx_dma_setup_handlers(int channel,
-		void (*irq_handler) (int, void *),
-		void (*err_handler) (int, void *, int), void *data);
-
-int
-imx_dma_setup_progression_handler(int channel,
-		void (*prog_handler) (int, void*, struct scatterlist*));
-
-void imx_dma_enable(int channel);
-
-void imx_dma_disable(int channel);
-
-int imx_dma_request(int channel, const char *name);
-
-void imx_dma_free(int channel);
-
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
-
-#endif	/* __MACH_DMA_V1_H__ */
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar  5 11:16:35 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon,  5 Mar 2012 17:16:35 +0100
Subject: [PATCH 13/14] dmaengine: imx-dma: use dev_dbg and dev_warn for
 messages.
In-Reply-To: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1330964196-32623-14-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   23 ++++++++++++-----------
 1 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index fe0f126..da7cecc 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -227,8 +227,8 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 
 	imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
 
-	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
-		"size 0x%08x\n", imxdmac->channel,
+	dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
+		"size 0x%08x\n", __func__, imxdmac->channel,
 		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
 		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
 		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
@@ -243,7 +243,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
-	pr_debug("imxdma%d: imx_dma_enable\n", channel);
+	dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
 
 	local_irq_save(flags);
 
@@ -274,7 +274,7 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
-	pr_debug("imxdma%d: imx_dma_disable\n", channel);
+	pr_debug("%s channel %d\n", __func__, channel);
 
 	if (imxdma_hw_chain(imxdmac))
 		del_timer(&imxdmac->watchdog);
@@ -298,7 +298,8 @@ static void imxdma_watchdog(unsigned long data)
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
-	pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+	dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
+		imxdmac->channel);
 }
 
 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
@@ -426,8 +427,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 
 	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
-	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
-		     disr);
+	dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
 
 	imx_dmav1_writel(imxdma, disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
@@ -902,14 +902,14 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	if (cpu_is_mx1()) {
 		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
 		if (ret) {
-			pr_crit("Can't register IRQ for DMA\n");
+			dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
 			kfree(imxdma);
 			return ret;
 		}
 
 		ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
 		if (ret) {
-			pr_crit("Can't register ERRIRQ for DMA\n");
+			dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
 			free_irq(MX1_DMA_INT, NULL);
 			kfree(imxdma);
 			return ret;
@@ -939,8 +939,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
 			ret = request_irq(MX2x_INT_DMACH0 + i,
 					dma_irq_handler, 0, "DMA", imxdma);
 			if (ret) {
-				pr_crit("Can't register IRQ %d for DMA channel %d\n",
-						MX2x_INT_DMACH0 + i, i);
+				dev_warn(imxdma->dev, "Can't register IRQ %d "
+					 "for DMA channel %d\n",
+					 MX2x_INT_DMACH0 + i, i);
 				goto err_init;
 			}
 			init_timer(&imxdmac->watchdog);
-- 
1.7.0.4



From daniel.lezcano at linaro.org  Mon Mar  5 11:43:07 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Mon, 05 Mar 2012 17:43:07 +0100
Subject: [PATCH v7 0/9] Consolidate cpuidle functionality
In-Reply-To: <CAMXH7KGJtSyeGwEN4jz9TRPxHUjtreMHRG-4WDChB0BC88P=OA@mail.gmail.com>
References: <1330562578-3410-1-git-send-email-rob.lee@linaro.org>
 <CAMXH7KGJtSyeGwEN4jz9TRPxHUjtreMHRG-4WDChB0BC88P=OA@mail.gmail.com>
Message-ID: <4F54ED1B.3070404@linaro.org>

On 03/01/2012 09:57 PM, Rob Lee wrote:
> On Wed, Feb 29, 2012 at 6:42 PM, Robert Lee<rob.lee at linaro.org>  wrote:
>> This patch series moves various functionality duplicated in platform
>> cpuidle drivers to the core cpuidle driver. Also, the platform irq
>> disabling was removed as it appears that all calls into
>> cpuidle_call_idle will have already called local_irq_disable().
>>
>
> I'm told that I forgot to add the Acks from the previous v6 to this version:
>
> Acked-by: Jean Pihet<j-pihet at ti.com>  (v6)
> Tested-by: Jean Pihet<j-pihet at ti.com>  (v6, omap3)
> Tested-by: Amit Daniel<amit.kachhap at linaro.org>  (v6, Exynos4)
> For the generic cpuidle changes:
> Reviewed-by: Deepthi Dharwar<deepthi at linux.vnet.ibm.com>

Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>


From will.deacon at arm.com  Mon Mar  5 11:54:05 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon,  5 Mar 2012 16:54:05 +0000
Subject: [PATCH v2] ARM: perf: add PMU hotplug notifier
Message-ID: <1330966445-4703-1-git-send-email-will.deacon@arm.com>

From: Lorenzo Pieralisi <Lorenzo.Pieralisi at arm.com>

When a CPU is taken out of reset, either cold booted or hotplugged in,
some of its PMU registers can contain UNKNOWN values.

This patch adds a hotplug notifier to ARM core perf code so that upon
CPU restart the PMU unit is reset and becomes ready to use again.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---

v2: Use CPU_STARTING instead of CPU_UP_PREPARE, since the latter does
    not run on the CPU coming up.

 arch/arm/kernel/perf_event.c |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index ab59c3b..5300537 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -680,6 +680,28 @@ static void __init cpu_pmu_init(struct arm_pmu *armpmu)
 }
 
 /*
+ * PMU hardware loses all context when a CPU goes offline.
+ * When a CPU is hotplugged back in, since some hardware registers are
+ * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
+ * junk values out of them.
+ */
+static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
+					unsigned long action, void *hcpu)
+{
+	if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
+		return NOTIFY_DONE;
+
+	if (cpu_pmu && cpu_pmu->reset)
+		cpu_pmu->reset(NULL);
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
+	.notifier_call = pmu_cpu_notify,
+};
+
+/*
  * CPU PMU identification and registration.
  */
 static int __init
@@ -733,6 +755,7 @@ init_hw_perf_events(void)
 		pr_info("enabled with %s PMU driver, %d counters available\n",
 			cpu_pmu->name, cpu_pmu->num_events);
 		cpu_pmu_init(cpu_pmu);
+		register_cpu_notifier(&pmu_cpu_notifier);
 		armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
 	} else {
 		pr_info("no hardware support available\n");
-- 
1.7.4.1



From swarren at nvidia.com  Mon Mar  5 11:55:22 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon, 5 Mar 2012 08:55:22 -0800
Subject: [alsa-devel] [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine
 driver
In-Reply-To: <20120305131332.GM3224@opensource.wolfsonmicro.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
 <20120304133818.GE3083@opensource.wolfsonmicro.com>
 <20120305080623.GD16232@S2101-09.ap.freescale.net>
 <20120305115612.GB3224@opensource.wolfsonmicro.com>
 <20120305130707.GF16232@S2101-09.ap.freescale.net>
 <20120305131332.GM3224@opensource.wolfsonmicro.com>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861C14@HQMAIL01.nvidia.com>

Mark Brown wrote at Monday, March 05, 2012 6:14 AM:
> On Mon, Mar 05, 2012 at 09:07:09PM +0800, Shawn Guo wrote:
> > On Mon, Mar 05, 2012 at 11:56:12AM +0000, Mark Brown wrote:
> 
> > > In that
> > > case they should either both be using the same device or should have
> > > some sort of parent/child/sibling relationship.
> 
> > Sorry, I do not understand it.  Can you elaborate it a little bit?
> 
> The DMA and SSI drivers should have some relationship with each other if
> they're the same piece of hardware.  The machine driver certainly
> shouldn't be creating either of them.

Note that in Tegra's case, the DMA HW and the DAI (I2S/SPDIF) HW are
entirely separate HW blocks and have entirely separate drivers. The DMA
engine is generic and not audio specific, so has a node that instantiates
just a standalone DMA device which has its own API. This doesn't
instantiate any kind of ALSA PCM driver. It doesn't make sense to have a
DT node to instantiate the ALSA PCM driver since the PCM driver is more
of an API bridge to the real DMA HW, and certainly not an actual HW
module. It doesn't make sense to have either the I2S or SPDIF DAI drivers
instantiate the PCM driver, since they both share the same one. Hence,
the machine driver instantiates the PCM driver.

Perhaps our regular DMA module driver should expose both its custom
interface for other clients, and register an ASoC PCM driver? That way
we could remove the PCM device registration from the ASoC machine
drivers.

> > > Either way the machine
> > > driver really shouldn't be involved in instantiating things, perhaps
> > > arch/arm but not the audio machine driver.
> 
> > So you are saying neither what tegra_wm8903 and tegra_alc5632 are doing
> > (registering pcm device in machine driver) nor what imx-ssi is doing
> > (registering pcm device in DAI driver) is correct?  Can you please make
> > it clear what's the right thing to do?
> 
> The above.

-- 
nvpublic



From aaro.koskinen at nokia.com  Mon Mar  5 12:08:57 2012
From: aaro.koskinen at nokia.com (Aaro Koskinen)
Date: Mon,  5 Mar 2012 19:08:57 +0200
Subject: [PATCH] arm: omap: add minimal support for Nokia RM-696
Message-ID: <1330967337-9634-1-git-send-email-aaro.koskinen@nokia.com>

Add minimal support for Nokia RM-696 board.

Signed-off-by: Aaro Koskinen <aaro.koskinen at nokia.com>
---

	The patch is based & boot-tested with 3.3-rc6.


 arch/arm/mach-omap2/Kconfig                  |    3 ++-
 arch/arm/mach-omap2/board-rm680.c            |   14 +++++++++++++-
 arch/arm/plat-omap/include/plat/uncompress.h |    1 +
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index e20c8ab..b740c2e 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -245,10 +245,11 @@ config MACH_NOKIA_N8X0
 	select MACH_NOKIA_N810_WIMAX
 
 config MACH_NOKIA_RM680
-	bool "Nokia RM-680 board"
+	bool "Nokia RM-680/696 board"
 	depends on ARCH_OMAP3
 	default y
 	select OMAP_PACKAGE_CBB
+	select MACH_NOKIA_RM696
 
 config MACH_NOKIA_RX51
 	bool "Nokia RX-51 board"
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 8678b38..094473e 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -1,5 +1,5 @@
 /*
- * Board support file for Nokia RM-680.
+ * Board support file for Nokia RM-680/696.
  *
  * Copyright (C) 2010 Nokia
  *
@@ -154,3 +154,15 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
 	.timer		= &omap3_timer,
 	.restart	= omap_prcm_restart,
 MACHINE_END
+
+MACHINE_START(NOKIA_RM696, "Nokia RM-696 board")
+	.atag_offset	= 0x100,
+	.reserve	= omap_reserve,
+	.map_io		= omap3_map_io,
+	.init_early	= omap3630_init_early,
+	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
+	.init_machine	= rm680_init,
+	.timer		= &omap3_timer,
+	.restart	= omap_prcm_restart,
+MACHINE_END
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 6ee9049..cc3f11b 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -160,6 +160,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 		DEBUG_LL_OMAP3(3, igep0020);
 		DEBUG_LL_OMAP3(3, igep0030);
 		DEBUG_LL_OMAP3(3, nokia_rm680);
+		DEBUG_LL_OMAP3(3, nokia_rm696);
 		DEBUG_LL_OMAP3(3, nokia_rx51);
 		DEBUG_LL_OMAP3(3, omap3517evm);
 		DEBUG_LL_OMAP3(3, omap3_beagle);
-- 
1.7.2.5



From alexg at meprolight.com  Mon Mar  5 11:57:45 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Mon, 5 Mar 2012 18:57:45 +0200
Subject: 0001-i.MX35-PDK-Chunghwa-CLAA070VC01-7-WVGA-TFT-Display-s.patch
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8904@MEP-EXCH.meprolight.com>

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From timur at freescale.com  Mon Mar  5 11:58:54 2012
From: timur at freescale.com (Timur Tabi)
Date: Mon, 5 Mar 2012 10:58:54 -0600
Subject: [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120305131332.GM3224@opensource.wolfsonmicro.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
 <20120304133818.GE3083@opensource.wolfsonmicro.com>
 <20120305080623.GD16232@S2101-09.ap.freescale.net>
 <20120305115612.GB3224@opensource.wolfsonmicro.com>
 <20120305130707.GF16232@S2101-09.ap.freescale.net>
 <20120305131332.GM3224@opensource.wolfsonmicro.com>
Message-ID: <4F54F0CE.60706@freescale.com>

Mark Brown wrote:
> The DMA and SSI drivers should have some relationship with each other if
> they're the same piece of hardware.  

The DMA and SSI are completely separate blocks in the SOC.  On PowerPC,
the P1022 SOC has an SSI and the standard FSL PPC DMA controller (we call
it the Elo controller).  On i.MX, there is a completely different DMA
controller (I'm not familiar with it), but the same exact SSI.

-- 
Timur Tabi
Linux kernel developer at Freescale



From arnd at arndb.de  Mon Mar  5 12:02:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 5 Mar 2012 17:02:37 +0000
Subject: [GIT PULL 0/6] Tegra branches for 3.4
In-Reply-To: <CAOesGMgahK_wkM1PGb55D1gEzbYfJVQKO_XSqMPbw5wTP09Fag@mail.gmail.com>
References: <1330892042-32065-1-git-send-email-olof@lixom.net>
 <CAOesGMgahK_wkM1PGb55D1gEzbYfJVQKO_XSqMPbw5wTP09Fag@mail.gmail.com>
Message-ID: <201203051702.38188.arnd@arndb.de>

On Sunday 04 March 2012, Olof Johansson wrote:
> On Sun, Mar 4, 2012 at 12:13 PM, Olof Johansson <olof at lixom.net> wrote:
> > Hi Arnd,
> >
> > Below are the 6 pull requests for Tegra platforms for 3.4. This is also
> > likely my last merge request for tegra material (besides possibly some
> > stray patches between now and the merge window), since I am handing off
> > main maintainership to Stephen Warren for the next merge window.
> >
> > Each branch is documented in the tag (they are all tag pull requests), as
> > well as in the emails below. Nothing too controversial.
> 
> Oh, I did forget to mention one added dependency: The soc-drivers
> branch has a dependency on Grant's irq_domain branch -- not for
> merging but for building.

Yes, I saw that in the tag description. I had included it in the tegra/soc-drivers
branch, but not in the next/drivers branch, which I did now.

	Arnd


From broonie at opensource.wolfsonmicro.com  Mon Mar  5 12:03:18 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 17:03:18 +0000
Subject: [alsa-devel] [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine
 driver
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE861C14@HQMAIL01.nvidia.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
 <20120304133818.GE3083@opensource.wolfsonmicro.com>
 <20120305080623.GD16232@S2101-09.ap.freescale.net>
 <20120305115612.GB3224@opensource.wolfsonmicro.com>
 <20120305130707.GF16232@S2101-09.ap.freescale.net>
 <20120305131332.GM3224@opensource.wolfsonmicro.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861C14@HQMAIL01.nvidia.com>
Message-ID: <20120305170317.GV3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 08:55:22AM -0800, Stephen Warren wrote:
> Mark Brown wrote at Monday, March 05, 2012 6:14 AM:

> > The DMA and SSI drivers should have some relationship with each other if
> > they're the same piece of hardware.  The machine driver certainly
> > shouldn't be creating either of them.

> Note that in Tegra's case, the DMA HW and the DAI (I2S/SPDIF) HW are
> entirely separate HW blocks and have entirely separate drivers. The DMA
> engine is generic and not audio specific, so has a node that instantiates
> just a standalone DMA device which has its own API. This doesn't
> instantiate any kind of ALSA PCM driver. It doesn't make sense to have a

In this case (and probably in the i.MX case, at a guess the structure is
the same) I'd just have the DAI drivers kick off registration of the
ASoC DMA stuff, it's all part of the ASoC driver for the hardware really.

> DT node to instantiate the ALSA PCM driver since the PCM driver is more
> of an API bridge to the real DMA HW, and certainly not an actual HW

Yes, and a Linux driver model device is questionable too.

> Perhaps our regular DMA module driver should expose both its custom
> interface for other clients, and register an ASoC PCM driver? That way
> we could remove the PCM device registration from the ASoC machine
> drivers.

That's another option, do it from the DMA driver instead of the DAI
driver.  My main concern here is that it shouldn't be the machine driver
as it's all internal to the CPU and not machine specific.
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From u.kleine-koenig at pengutronix.de  Mon Mar  5 12:04:02 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Mon,  5 Mar 2012 18:04:02 +0100
Subject: [PATCH v2 5/5] Cortex-M3: Add support for exception handling
In-Reply-To: <1330967042-25612-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <CAHkRjk70x+Fn+Z4iUxSMc7Zq2cKBo_ka0tNhV0i5JWmEixpRrA@mail.gmail.com>
 <1330967042-25612-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1330967042-25612-2-git-send-email-u.kleine-koenig@pengutronix.de>

This patch implements the exception handling for the ARMv7-M
architecture (pretty different from the A or R profiles).

Initially this based on a patch by Catalin Marinas but was completely
reworked to use a pt_regs layout similar to the A profile.

Note this is broken in at least two ways:
 - r0 isn't saved for signal restarting (should be easy)
 - crashes early after reaching userspace.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
Hello,

To save r0, I'd readd OLD_R0 at the end of pt_regs (plus one buffer word
to get even alignment). Or would that already be unacceptable because
it's an ABI change, too?

Anyhow, this is (once more :-) a great opportunity for you to blame me
in public by pointing out why my machine crashes with this patch. But to
be honest this time I wouldn't mind because hopefully after describing
your findings I'd be able to fix the problem.

Best regards
Uwe

 arch/arm/kernel/entry-common.S |    9 ++-
 arch/arm/kernel/entry-header.S |  149 +++++++++++++++++++++++++++++++++++++++-
 arch/arm/kernel/entry-v7m.S    |  135 ++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/process.c      |    8 ++
 4 files changed, 299 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/kernel/entry-v7m.S

diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 9fd0ba9..953e517 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -345,6 +345,9 @@ ENDPROC(ftrace_stub)
 
 	.align	5
 ENTRY(vector_swi)
+#ifdef CONFIG_CPU_V7M
+	v7m_exception_entry
+#else
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0 - r12
  ARM(	add	r8, sp, #S_PC		)
@@ -354,7 +357,11 @@ ENTRY(vector_swi)
 	mrs	r8, spsr			@ called from non-FIQ mode, so ok.
 	str	lr, [sp, #S_PC]			@ Save calling PC
 	str	r8, [sp, #S_PSR]		@ Save CPSR
+#endif
+#if XXX
+	/* XXX: fixme: we need to preserve r0 somewhere for signal stuff */
 	str	r0, [sp, #S_OLD_R0]		@ Save OLD_R0
+#endif
 	zero_fp
 
 	/*
@@ -473,7 +480,7 @@ __sys_trace:
 
 	adr	lr, BSYM(__sys_trace_return)	@ return address
 	mov	scno, r0			@ syscall number (possibly new)
-	add	r1, sp, #S_R0 + S_OFF		@ pointer to regs
+	add	r1, sp, #S_OFF			@ pointer to regs
 	cmp	scno, #NR_syscalls		@ check upper syscall limit
 	ldmccia	r1, {r0 - r3}			@ have to reload r0 - r3
 	ldrcc	pc, [tbl, scno, lsl #2]		@ call sys_* routine
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 9a8531e..6e03c8b 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -26,7 +26,7 @@
  * The SWI code relies on the fact that R0 is at the bottom of the stack
  * (due to slow/fast restore user regs).
  */
-#if S_R0 != 0
+#if S_R0 != 0 && !defined(CONFIG_CPU_V7M)
 #error "Please fix"
 #endif
 
@@ -44,6 +44,144 @@
 #endif
 	.endm
 
+#ifdef CONFIG_CPU_V7M
+/*
+ * ARMv7-M exception entry/exit macros.
+ *
+ * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
+ * automatically saved on the current stack (32 words) before
+ * switching to the exception stack (SP_main).
+ *
+ * If exception is taken while in user mode, SP_main is
+ * empty. Otherwise, SP_main is aligned to 64 bit automatically
+ * (CCR.STKALIGN set).
+ *
+ * Linux assumes that the interrupts are disabled when entering an
+ * exception handler and it may BUG if this is not the case. Interrupts
+ * are disabled during entry and reenabled in the exit macro.
+ *
+ * v7m_exception_fast_exit is used when returning from interrupts.
+ *
+ * v7m_exception_slow_exit is used when returning from SVC or PendSV.
+ * When returning to kernel mode, we don't return from exception.
+ */
+	.macro	v7m_exception_entry
+	cpsid	i
+	sub	sp, #S_FRAME_SIZE
+	stmia	sp, {r0-r12}
+
+	@ set r0 to the location of the registers saved by the core during
+	@ exception entry. Depending on the mode the cpu was in when the
+	@ exception happend that is either on the main or the process stack.
+	@ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
+	@ was used.
+	tst	lr, #0x4
+	mrsne	r0, psp
+	addeq	r0, sp, #S_FRAME_SIZE
+
+	add	r0, r0, #20		@ skip over r0-r3, r12
+	ldmia	r0!, {r1-r3}		@ load saved lr, return address and xPSR
+
+	@ calculate the orignal stack pointer value.
+	@ r0 currently points to the memory location just above the auto saved
+	@ xPSR. If the FP extension is implemented and bit 4 of EXC_RETURN is 0
+	@ then space was allocated for FP state. That is space for 18 32-bit
+	@ values. (If FP extension is unimplemented, bit 4 is 1.)
+	@ Additionally the cpu might automatically 8-byte align the stack. Bit 9
+	@ of the saved xPSR specifies if stack aligning took place. In this case
+	@ another 32-bit value is included in the stack.
+
+	tst	lr, #0x10
+	addeq	r0, r0, #576
+
+	tst	r3, #0x100
+	addne	r0, r0, #4
+
+	@ save original sp, lr, return address, xPSR and EXC_RETURN
+	add	r12, sp, #52
+	stmia	r12, {r0-r3, lr}
+
+	@ restore registers for system calls
+	ldmia	sp, {r0-r12}
+	.endm
+
+	.macro	v7m_exception_fast_exit
+	@ read r12, sp, lr, return address, xPSR and EXC_RETURN
+	add	r12, sp, #48
+	ldmia	r12, {r1-r5, lr}
+
+	tst     r5, #0x100
+	subne   r2, r2, #4
+
+	tst	lr, #0x10
+	subeq	r2, r2, #576
+
+	stmdb	r2!, {r1, r3-r5}		@ write saved r12, lr, return address and xPSR
+
+	ldmia	sp, {r1, r3-r5}			@ read saved r0-r3
+	stmdb	r2!, {r1, r3-r5}		@ write r0-r3 to basic exception frame
+
+	tst	lr, #0x4
+	msrne	psp, r2
+
+	ldmia	sp, {r0-r12}
+	add	sp, #S_FRAME_SIZE
+	cpsie	i
+	bx	lr
+	.endm
+
+	.macro	v7m_exception_slow_exit ret_r0
+	cpsid	i
+	ldr	lr, [sp, #S_EXCRET]		@ read exception LR
+	tst     lr, #0x8
+	bne	1f				@ go to thread mode using exception return
+
+	/*
+	 * return to kernel thread
+	 * sp is already set up (and might be unset in pt_regs), so only
+	 * restore r0-r12 and pc
+	 */
+	ldmia	sp, {r0-r12}
+	ldr	lr, [sp, #S_PC]
+	add	sp, sp, #S_FRAME_SIZE
+	cpsie	i
+	bx	lr
+
+	/*
+	 * return to userspace
+	 */
+1:
+	@ read original r12, sp, lr, pc, xPSR
+	add	r12, sp, #48
+	ldmia	r12, {r1-r5}
+
+	/* stack aligning */
+	tst	r5, #0x100
+	subne	r2, r2, #4
+
+	/* skip over stack space for fp extension */
+	tst	lr, #0x10
+	subeq	r2, r2, #576
+
+	/* write basic exception frame */
+	stmdb	r2!, {r1, r3-r5}		@ saved r12, lr, return address and xPSR
+	ldmia	sp, {r1, r3-r5}			@ read saved r0-r3
+	.if	\ret_r0
+	stmdb	r2!, {r0, r3-r5}		@ restore r0-r3
+	.else
+	stmdb	r2!, {r1, r3-r5}		@ restore r0-r3
+	.endif
+
+	msr	psp, r2
+
+	ldmia	sp, {r0-r12}			@ restore original r4-r11
+
+	add	sp, #S_FRAME_SIZE		@ restore the original MSP
+	cpsie	i
+	bx	lr
+	.endm
+#endif	/* CONFIG_CPU_V7M */
+
 	@
 	@ Store/load the USER SP and LR registers by switching to the SYS
 	@ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
@@ -131,6 +269,14 @@
 	rfeia	sp!
 	.endm
 
+#ifdef CONFIG_CPU_V7M
+	.macro	restore_user_regs, fast = 0, offset = 0
+	.if	\offset
+	add	sp, #\offset
+	.endif
+	v7m_exception_slow_exit ret_r0 = \fast
+	.endm
+#else	/* !CONFIG_CPU_V7M */
 	.macro	restore_user_regs, fast = 0, offset = 0
 	clrex					@ clear the exclusive monitor
 	mov	r2, sp
@@ -147,6 +293,7 @@
 	add	sp, sp, #S_FRAME_SIZE - S_SP
 	movs	pc, lr				@ return & move spsr_svc into cpsr
 	.endm
+#endif	/* CONFIG_CPU_V7M */
 
 	.macro	get_thread_info, rd
 	mov	\rd, sp
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
new file mode 100644
index 0000000..5bca10b
--- /dev/null
+++ b/arch/arm/kernel/entry-v7m.S
@@ -0,0 +1,135 @@
+/*
+ * linux/arch/arm/kernel/entry-v7m.S
+ *
+ * Copyright (C) 2008 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Low-level vector interface routines for the ARMv7-M architecture
+ */
+#include <asm/memory.h>
+#include <asm/glue.h>
+#include <asm/thread_notify.h>
+
+#include <mach/entry-macro.S>
+
+#include "entry-header.S"
+
+#ifdef CONFIG_PREEMPT
+#error "CONFIG_PREEMPT not supported on the current ARMv7M implementation"
+#endif
+#ifdef CONFIG_TRACE_IRQFLAGS
+#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
+#endif
+
+__invalid_entry:
+	v7m_exception_entry
+	adr	r0, strerr
+	mrs	r1, ipsr
+	mov	r2, lr
+	mov	r3, sp
+	bl	printk
+	mov	r0, sp
+	bl	__show_regs
+1:	b	1b
+ENDPROC(__invalid_entry)
+
+strerr:	.asciz	"\nUnhandled exception: IPSR = %08lx LR = %08lx SP = %08lx\n"
+
+	.align	2
+__irq_entry:
+	v7m_exception_entry
+
+	@
+	@ Invoke the IRQ handler
+	@
+	mrs	r0, ipsr
+	and	r0, #0xff
+	sub	r0, #16			@ IRQ number
+	mov	r1, sp
+	@ routine called with r0 = irq number, r1 = struct pt_regs *
+	bl	asm_do_IRQ
+
+	@
+	@ Check for any pending work if returning to user
+	@
+	ldr	lr, [sp, #S_EXCRET]
+	tst	lr, #0x8		@ check the return stack
+	beq	2f			@ returning to handler mode
+	get_thread_info tsk
+	ldr	r1, [tsk, #TI_FLAGS]
+	tst	r1, #_TIF_WORK_MASK
+	beq	2f			@ no work pending
+	ldr	r1, =0xe000ed04		@ ICSR
+	mov	r0, #1 << 28		@ ICSR.PENDSVSET
+	str	r0, [r1]		@ raise PendSV
+
+2:
+	v7m_exception_fast_exit
+ENDPROC(__irq_entry)
+
+__pendsv_entry:
+	v7m_exception_entry
+
+	ldr	r1, =0xe000ed04		@ ICSR
+	mov	r0, #1 << 27		@ ICSR.PENDSVCLR
+	str	r0, [r1]		@ clear PendSV
+
+	@ execute the pending work, including reschedule
+	get_thread_info tsk
+	mov	why, #0
+	b	ret_to_user
+ENDPROC(__pendsv_entry)
+
+/*
+ * Register switch for ARMv7-M processors.
+ * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
+ * previous and next are guaranteed not to be the same.
+ */
+ENTRY(__switch_to)
+	.fnstart
+	.cantunwind
+	add	ip, r1, #TI_CPU_SAVE
+	stmia	ip!, {r4 - r11}		@ Store most regs on stack
+	str	sp, [ip], #4
+	str	lr, [ip], #4
+	mov	r5, r0
+	add	r4, r2, #TI_CPU_SAVE
+	ldr	r0, =thread_notify_head
+	mov	r1, #THREAD_NOTIFY_SWITCH
+	bl	atomic_notifier_call_chain
+	mov	ip, r4
+	mov	r0, r5
+	ldmia	ip!, {r4 - r11}		@ Load all regs saved previously
+	ldr	sp, [ip], #4
+	ldr	pc, [ip]
+	.fnend
+ENDPROC(__switch_to)
+
+	.data
+	.align	8
+/*
+ * Vector table (64 words => 256 bytes natural alignment)
+ */
+ENTRY(vector_table)
+	.long	0			@ 0 - Reset stack pointer
+	.long	__invalid_entry		@ 1 - Reset
+	.long	__invalid_entry		@ 2 - NMI
+	.long	__invalid_entry		@ 3 - HardFault
+	.long	__invalid_entry		@ 4 - MemManage
+	.long	__invalid_entry		@ 5 - BusFault
+	.long	__invalid_entry		@ 6 - UsageFault
+	.long	__invalid_entry		@ 7 - Reserved
+	.long	__invalid_entry		@ 8 - Reserved
+	.long	__invalid_entry		@ 9 - Reserved
+	.long	__invalid_entry		@ 10 - Reserved
+	.long	vector_swi		@ 11 - SVCall
+	.long	__invalid_entry		@ 12 - Debug Monitor
+	.long	__invalid_entry		@ 13 - Reserved
+	.long	__pendsv_entry		@ 14 - PendSV
+	.long	__invalid_entry		@ 15 - SysTick
+	.rept	64 - 16
+	.long	__irq_entry		@ 16..64 - External Interrupts
+	.endr
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 971d65c..bdccb8f 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -452,7 +452,11 @@ asm(	".pushsection .text\n"
 #ifdef CONFIG_TRACE_IRQFLAGS
 "	bl	trace_hardirqs_on\n"
 #endif
+#ifdef CONFIG_CPU_V7M
+"	msr	primask, r7\n"
+#else
 "	msr	cpsr_c, r7\n"
+#endif
 "	mov	r0, r4\n"
 "	mov	lr, r6\n"
 "	mov	pc, r5\n"
@@ -491,6 +495,10 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
 	regs.ARM_r7 = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;
 	regs.ARM_pc = (unsigned long)kernel_thread_helper;
 	regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT;
+#ifdef CONFIG_CPU_V7M
+	/* Return to Handler mode */
+	regs.ARM_EXCRET = 0xfffffff1L;
+#endif
 
 	return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 }
-- 
1.7.9.1



From u.kleine-koenig at pengutronix.de  Mon Mar  5 12:04:01 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Mon,  5 Mar 2012 18:04:01 +0100
Subject: [PATCH v2 4/5] Cortex-M3: Add base support for Cortex-M3
In-Reply-To: <CAHkRjk70x+Fn+Z4iUxSMc7Zq2cKBo_ka0tNhV0i5JWmEixpRrA@mail.gmail.com>
References: <CAHkRjk70x+Fn+Z4iUxSMc7Zq2cKBo_ka0tNhV0i5JWmEixpRrA@mail.gmail.com>
Message-ID: <1330967042-25612-1-git-send-email-u.kleine-koenig@pengutronix.de>

From: Catalin Marinas <catalin.marinas at arm.com>

This patch adds the base support for the Cortex-M3 processor (ARMv7-M
architecture). It consists of the corresponding arch/arm/mm/ files and
various #ifdef's around the kernel. Exception handling is implemented by
a subsequent patch.

[ukleinek: squash in some changes originating from commit

b5717ba (Cortex-M3: Add support for the Microcontroller Prototyping System)

from the v2.6.33-arm1 patch stack, port to post 3.2, drop zImage
support, and a few cosmetic changes, rework to preserve layout of
pt_regs]

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/include/asm/assembler.h  |   13 +++-
 arch/arm/include/asm/cputype.h    |    3 +
 arch/arm/include/asm/glue-cache.h |   24 +++++
 arch/arm/include/asm/glue-df.h    |    8 ++
 arch/arm/include/asm/glue-proc.h  |    9 ++
 arch/arm/include/asm/irqflags.h   |   51 +++++++++++-
 arch/arm/include/asm/processor.h  |    8 ++
 arch/arm/include/asm/ptrace.h     |   21 ++++-
 arch/arm/include/asm/system.h     |    3 +
 arch/arm/kernel/asm-offsets.c     |    4 +
 arch/arm/kernel/head-common.S     |    2 +-
 arch/arm/kernel/head-nommu.S      |    9 ++-
 arch/arm/kernel/ptrace.c          |    4 +
 arch/arm/kernel/setup.c           |   13 +++-
 arch/arm/kernel/signal.c          |    5 +
 arch/arm/kernel/traps.c           |    2 +
 arch/arm/mm/nommu.c               |    2 +
 arch/arm/mm/proc-v7m.S            |  168 +++++++++++++++++++++++++++++++++++++
 18 files changed, 339 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/mm/proc-v7m.S

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 62f8095..1bafa39 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -133,7 +133,11 @@
  * assumes FIQs are enabled, and that the processor is in SVC mode.
  */
 	.macro	save_and_disable_irqs, oldcpsr
+#ifdef CONFIG_CPU_V7M
+	mrs	\oldcpsr, primask
+#else
 	mrs	\oldcpsr, cpsr
+#endif
 	disable_irq
 	.endm
 
@@ -142,7 +146,11 @@
  * guarantee that this will preserve the flags.
  */
 	.macro	restore_irqs_notrace, oldcpsr
+#ifdef CONFIG_CPU_V7M
+	msr	primask, \oldcpsr
+#else
 	msr	cpsr_c, \oldcpsr
+#endif
 	.endm
 
 	.macro restore_irqs, oldcpsr
@@ -221,7 +229,10 @@
 #endif
 	.endm
 
-#ifdef CONFIG_THUMB2_KERNEL
+#if defined(CONFIG_CPU_V7M)
+	.macro	setmode, mode, reg
+	.endm
+#elif defined(CONFIG_THUMB2_KERNEL)
 	.macro	setmode, mode, reg
 	mov	\reg, #\mode
 	msr	cpsr_c, \reg
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cb47d28..5bd8cb6 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -46,6 +46,9 @@ extern unsigned int processor_id;
 		    : "cc");						\
 		__val;							\
 	})
+#elif defined(CONFIG_CPU_V7M)
+#define read_cpuid(reg) (*(unsigned int *)0xe000ed00)
+#define read_cpuid_ext(reg) 0
 #else
 #define read_cpuid(reg) (processor_id)
 #define read_cpuid_ext(reg) 0
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index 7e30874..6a5fd0b 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -125,10 +125,34 @@
 //# endif
 #endif
 
+#if defined(CONFIG_CPU_V7M)
+# ifdef _CACHE
+#  error "Multi-cache not supported on ARMv7-M"
+# else
+#  define _CACHE nop
+# endif
+#endif
+
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 #error Unknown cache maintenance model
 #endif
 
+#ifndef __ASSEMBLER__
+static inline void nop_flush_icache_all(void) { }
+static inline void nop_flush_kern_cache_all(void) { }
+static inline void nop_flush_user_cache_all(void) { }
+static inline void nop_flush_user_cache_range(unsigned long a, unsigned long b, unsigned int c) { }
+
+static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
+static inline void nop_coherent_user_range(unsigned long a, unsigned long b) { }
+static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
+
+static inline void nop_dma_flush_range(const void *a, const void *b) { }
+
+static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
+static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
+#endif
+
 #ifndef MULTI_CACHE
 #define __cpuc_flush_icache_all		__glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index 354d571..26be71c 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -103,6 +103,14 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_ABRT_NOMMU
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
+# else
+#  define CPU_DABORT_HANDLER nommu_early_abort
+# endif
+#endif
+
 #ifndef CPU_DABORT_HANDLER
 #error Unknown data abort handler type
 #endif
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index e2be7f1..8f9991b 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -248,6 +248,15 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_V7M
+# ifdef CPU_NAME
+#  undef  MULTI_CPU
+#  define MULTI_CPU
+# else
+#  define CPU_NAME cpu_v7m
+# endif
+#endif
+
 #ifndef MULTI_CPU
 #define cpu_proc_init			__glue(CPU_NAME,_proc_init)
 #define cpu_proc_fin			__glue(CPU_NAME,_proc_fin)
diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h
index 1e6cca5..ac4d548 100644
--- a/arch/arm/include/asm/irqflags.h
+++ b/arch/arm/include/asm/irqflags.h
@@ -10,6 +10,18 @@
  */
 #if __LINUX_ARM_ARCH__ >= 6
 
+#ifdef CONFIG_CPU_V7M
+static inline unsigned long arch_local_irq_save(void)
+{
+	unsigned long flags;
+
+	asm volatile(
+		"	mrs	%0, primask	@ arch_local_irq_save\n"
+		"	cpsid	i"
+		: "=r" (flags) : : "memory", "cc");
+	return flags;
+}
+#else
 static inline unsigned long arch_local_irq_save(void)
 {
 	unsigned long flags;
@@ -20,6 +32,7 @@ static inline unsigned long arch_local_irq_save(void)
 		: "=r" (flags) : : "memory", "cc");
 	return flags;
 }
+#endif
 
 static inline void arch_local_irq_enable(void)
 {
@@ -122,6 +135,38 @@ static inline void arch_local_irq_disable(void)
 
 #endif
 
+#ifdef CONFIG_CPU_V7M
+/*
+ * Save the current interrupt enable state.
+ */
+static inline unsigned long arch_local_save_flags(void)
+{
+	unsigned long flags;
+	asm volatile(
+		"	mrs	%0, primask	@ local_save_flags"
+		: "=r" (flags) : : "memory", "cc");
+	return flags;
+}
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+	asm volatile(
+		"	msr	primask, %0	@ local_irq_restore"
+		:
+		: "r" (flags)
+		: "memory", "cc");
+}
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+	return flags & 1;
+}
+
+#else /* ifdef CONFIG_CPU_V7M */
+
 /*
  * Save the current interrupt enable state.
  */
@@ -151,5 +196,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags)
 	return flags & PSR_I_BIT;
 }
 
-#endif
-#endif
+#endif /* ifdef CONFIG_CPU_V7M / else */
+
+#endif /* ifdef __KERNEL__ */
+#endif /* ifndef __ASM_ARM_IRQFLAGS_H */
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index ce280b8..18ec6b6 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -49,7 +49,15 @@ struct thread_struct {
 #ifdef CONFIG_MMU
 #define nommu_start_thread(regs) do { } while (0)
 #else
+#ifndef CONFIG_CPU_V7M
 #define nommu_start_thread(regs) regs->ARM_r10 = current->mm->start_data
+#else
+#define nommu_start_thread(regs) do {					\
+	regs->ARM_r10 = current->mm->start_data;			\
+	regs->ARM_sp -= 32;		/* exception return state */	\
+	regs->ARM_EXCRET = 0xfffffffdL;					\
+} while (0)
+#endif
 #endif
 
 #define start_thread(regs,pc,sp)					\
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 451808b..154d442 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -39,16 +39,25 @@
 #define FIQ26_MODE	0x00000001
 #define IRQ26_MODE	0x00000002
 #define SVC26_MODE	0x00000003
+#ifndef CONFIG_CPU_V7M
 #define USR_MODE	0x00000010
+#define SVC_MODE	0x00000013
+#else
+#define USR_MODE	0x00000000
+#define SVC_MODE	0x00000000
+#endif
 #define FIQ_MODE	0x00000011
 #define IRQ_MODE	0x00000012
-#define SVC_MODE	0x00000013
 #define ABT_MODE	0x00000017
 #define UND_MODE	0x0000001b
 #define SYSTEM_MODE	0x0000001f
 #define MODE32_BIT	0x00000010
 #define MODE_MASK	0x0000001f
+#ifndef CONFIG_CPU_V7M
 #define PSR_T_BIT	0x00000020
+#else
+#define PSR_T_BIT	0x01000000
+#endif
 #define PSR_F_BIT	0x00000040
 #define PSR_I_BIT	0x00000080
 #define PSR_A_BIT	0x00000100
@@ -127,7 +136,11 @@ struct pt_regs {
 #define ARM_r2		uregs[2]
 #define ARM_r1		uregs[1]
 #define ARM_r0		uregs[0]
+#if defined CONFIG_CPU_V7M
+#define ARM_EXCRET	uregs[17]
+#else
 #define ARM_ORIG_r0	uregs[17]
+#endif
 
 /*
  * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
@@ -165,6 +178,7 @@ struct pt_regs {
  */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
+#ifndef CONFIG_CPU_V7M
 	unsigned long mode = regs->ARM_cpsr & MODE_MASK;
 
 	/*
@@ -187,6 +201,9 @@ static inline int valid_user_regs(struct pt_regs *regs)
 		regs->ARM_cpsr |= USR_MODE;
 
 	return 0;
+#else /* ifndef CONFIG_CPU_V7M */
+	return 1;
+#endif
 }
 
 static inline long regs_return_value(struct pt_regs *regs)
@@ -218,7 +235,7 @@ extern unsigned long profile_pc(struct pt_regs *regs);
  */
 #include <linux/stddef.h>
 #include <linux/types.h>
-#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
+#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_cpsr) + 4)
 
 extern int regs_query_register_offset(const char *name);
 extern const char *regs_query_register_name(unsigned int offset);
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index de46477..16117ed 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -13,6 +13,7 @@
 #define CPU_ARCH_ARMv5TEJ	7
 #define CPU_ARCH_ARMv6		8
 #define CPU_ARCH_ARMv7		9
+#define CPU_ARCH_ARMv7M		10
 
 /*
  * CR1 bits (CP#15 CR1)
@@ -232,7 +233,9 @@ static inline void set_copro_access(unsigned int val)
  * so enable interrupts over the context switch to avoid high
  * latency.
  */
+#ifndef CONFIG_CPU_V7M
 #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
+#endif
 
 /*
  * switch_to(prev, next) should switch from task `prev' to `next'
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 1429d89..da2ce93 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -90,7 +90,11 @@ int main(void)
   DEFINE(S_LR,			offsetof(struct pt_regs, ARM_lr));
   DEFINE(S_PC,			offsetof(struct pt_regs, ARM_pc));
   DEFINE(S_PSR,			offsetof(struct pt_regs, ARM_cpsr));
+#ifdef CONFIG_CPU_V7M
+  DEFINE(S_EXCRET,		offsetof(struct pt_regs, ARM_EXCRET));
+#else
   DEFINE(S_OLD_R0,		offsetof(struct pt_regs, ARM_ORIG_r0));
+#endif
   DEFINE(S_FRAME_SIZE,		sizeof(struct pt_regs));
   BLANK();
 #ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 5ca01bb..efeb2d0 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -118,7 +118,7 @@ __mmap_switched_data:
 #ifdef CONFIG_CPU_CP15
 	.long	cr_alignment			@ r7
 #else
-	.long	0
+	.long	0				@ r7
 #endif
 	.long	init_thread_union + THREAD_START_SP @ sp
 	.size	__mmap_switched_data, . - __mmap_switched_data
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 1aca35d..61ba029 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -44,10 +44,13 @@ ENTRY(stext)
 
 	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
 						@ and irqs disabled
-#ifndef CONFIG_CPU_CP15
-	ldr	r9, =CONFIG_PROCESSOR_ID
-#else
+#if defined(CONFIG_CPU_CP15)
 	mrc	p15, 0, r9, c0, c0		@ get processor id
+#elif defined(CONFIG_CPU_V7M)
+	ldr	r9, =0xe000ed00			@ CPUID register address
+	ldr	r9, [r9]
+#else
+	ldr	r9, =CONFIG_PROCESSOR_ID
 #endif
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index e33870f..9ba31f8 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -81,7 +81,11 @@ static const struct pt_regs_offset regoffset_table[] = {
 	REG_OFFSET_NAME(lr),
 	REG_OFFSET_NAME(pc),
 	REG_OFFSET_NAME(cpsr),
+#ifdef CONFIG_CPU_V7M
+	REG_OFFSET_NAME(EXCRET),
+#else
 	REG_OFFSET_NAME(ORIG_r0),
+#endif
 	REG_OFFSET_END,
 };
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 23893b1..d0fc5b8 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -132,7 +132,9 @@ struct stack {
 	u32 und[3];
 } ____cacheline_aligned;
 
+#ifndef CONFIG_CPU_V7M
 static struct stack stacks[NR_CPUS];
+#endif
 
 char elf_platform[ELF_PLATFORM_SIZE];
 EXPORT_SYMBOL(elf_platform);
@@ -212,7 +214,7 @@ static const char *proc_arch[] = {
 	"5TEJ",
 	"6TEJ",
 	"7",
-	"?(11)",
+	"7M",
 	"?(12)",
 	"?(13)",
 	"?(14)",
@@ -221,6 +223,12 @@ static const char *proc_arch[] = {
 	"?(17)",
 };
 
+#ifdef CONFIG_CPU_V7M
+static int __get_cpu_architecture(void)
+{
+	return CPU_ARCH_ARMv7M;
+}
+#else
 static int __get_cpu_architecture(void)
 {
 	int cpu_arch;
@@ -253,6 +261,7 @@ static int __get_cpu_architecture(void)
 
 	return cpu_arch;
 }
+#endif
 
 int __pure cpu_architecture(void)
 {
@@ -380,6 +389,7 @@ static void __init feat_v6_fixup(void)
  */
 void cpu_init(void)
 {
+#ifndef CONFIG_CPU_V7M
 	unsigned int cpu = smp_processor_id();
 	struct stack *stk = &stacks[cpu];
 
@@ -424,6 +434,7 @@ void cpu_init(void)
 	      "I" (offsetof(struct stack, und[0])),
 	      PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
 	    : "r14");
+#endif
 }
 
 int __cpu_logical_map[NR_CPUS];
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 9e617bd..8407c17 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -688,7 +688,12 @@ static void do_signal(struct pt_regs *regs, int syscall)
 		case -ERESTARTNOHAND:
 		case -ERESTARTSYS:
 		case -ERESTARTNOINTR:
+#ifdef CONFIG_CPU_V7M
+			pr_info("%s: cannot restart yet!\n", __func__);
+			while(1);
+#else
 			regs->ARM_r0 = regs->ARM_ORIG_r0;
+#endif
 			regs->ARM_pc = restart_addr;
 			break;
 		case -ERESTART_RESTARTBLOCK:
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 99a5727..8956d08 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -783,6 +783,7 @@ static void __init kuser_get_tls_init(unsigned long vectors)
 
 void __init early_trap_init(void)
 {
+#ifndef CONFIG_CPU_V7M
 #if defined(CONFIG_CPU_USE_DOMAINS)
 	unsigned long vectors = CONFIG_VECTORS_BASE;
 #else
@@ -818,4 +819,5 @@ void __init early_trap_init(void)
 
 	flush_icache_range(vectors, vectors + PAGE_SIZE);
 	modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
+#endif
 }
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 4fc6794..fdd49ac 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -19,12 +19,14 @@
 
 void __init arm_mm_memblock_reserve(void)
 {
+#ifndef CONFIG_CPU_V7M
 	/*
 	 * Register the exception vector page.
 	 * some architectures which the DRAM is the exception vector to trap,
 	 * alloc_page breaks with error, although it is not NULL, but "0."
 	 */
 	memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
+#endif
 }
 
 void __init sanity_check_meminfo(void)
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
new file mode 100644
index 0000000..51404d9
--- /dev/null
+++ b/arch/arm/mm/proc-v7m.S
@@ -0,0 +1,168 @@
+/*
+ *  linux/arch/arm/mm/proc-v7m.S
+ *
+ *  Copyright (C) 2008 ARM Ltd.
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7-M processor support.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(cpu_v7m_proc_init)
+	mov	pc, lr
+ENDPROC(cpu_v7m_proc_init)
+
+ENTRY(cpu_v7m_proc_fin)
+	mov	pc, lr
+ENDPROC(cpu_v7m_proc_fin)
+
+/*
+ *	cpu_v7m_reset(loc)
+ *
+ *	Perform a soft reset of the system.  Put the CPU into the
+ *	same state as it would be if it had been reset, and branch
+ *	to what would be the reset vector.
+ *
+ *	- loc   - location to jump to for soft reset
+ */
+	.align	5
+ENTRY(cpu_v7m_reset)
+	mov	pc, r0
+ENDPROC(cpu_v7m_reset)
+
+/*
+ *	cpu_v7m_do_idle()
+ *
+ *	Idle the processor (eg, wait for interrupt).
+ *
+ *	IRQs are already disabled.
+ */
+ENTRY(cpu_v7m_do_idle)
+	wfi
+	mov	pc, lr
+ENDPROC(cpu_v7m_do_idle)
+
+ENTRY(cpu_v7m_dcache_clean_area)
+	mov	pc, lr
+ENDPROC(cpu_v7m_dcache_clean_area)
+
+/*
+ *	cpu_v7m_switch_mm(pgd_phys, tsk)
+ *
+ *	Set the translation table base pointer to be pgd_phys
+ *
+ *	- pgd_phys - physical address of new TTB
+ *
+ *	It is assumed that:
+ *	- we are not using split page tables
+ */
+ENTRY(cpu_v7m_switch_mm)
+	mov	pc, lr
+ENDPROC(cpu_v7m_switch_mm)
+
+cpu_v7m_name:
+	.ascii	"ARMv7-M Processor"
+	.align
+
+	.section ".text.init", #alloc, #execinstr
+
+/*
+ *	__v7m_setup
+ *
+ *	This should be able to cover all ARMv7-M cores.
+ */
+__v7m_setup:
+	@ Configure the vector table base address
+	ldr	r0, =0xe000ed08		@ vector table base address
+	ldr	r12, =vector_table
+	str	r12, [r0]
+
+	@ Lower the priority of the SVC and PendSV exceptions
+	ldr	r0, =0xe000ed1c
+	mov	r5, #0x80000000
+	str	r5, [r0]		@ set SVC priority
+	ldr	r0, =0xe000ed20
+	mov	r5, #0x00800000
+	str	r5, [r0]		@ set PendSV priority
+
+	@ SVC to run the kernel in this mode
+	adr	r0, BSYM(1f)
+	ldr	r5, [r12, #11 * 4]	@ read the SVC vector entry
+	str	r0, [r12, #11 * 4]	@ write the temporary SVC vector entry
+	mov	r6, lr			@ save LR
+	mov	r7, sp			@ save SP
+	ldr	sp, =__v7m_setup_stack_top
+	cpsie	i
+	svc	#0
+1:	cpsid	i
+	str	r5, [r12, #11 * 4]	@ restore the original SVC vector entry
+	mov	lr, r6			@ restore LR
+	mov	sp, r7			@ restore SP
+
+	@ Special-purpose control register
+	mov	r0, #1
+	msr	control, r0		@ Thread mode has unpriviledged access
+
+	@ Configure the System Control Register
+	ldr	r0, =0xe000ed14		@ system control register
+	ldr	r12, [r0]
+	orr	r12, #1 << 9		@ STKALIGN
+	str	r12, [r0]
+	mov	pc, lr
+ENDPROC(__v7m_setup)
+
+	.align	2
+	.type	v7m_processor_functions, #object
+ENTRY(v7m_processor_functions)
+	.word	nommu_early_abort
+	.word	cpu_v7m_proc_init
+	.word	cpu_v7m_proc_fin
+	.word	cpu_v7m_reset
+	.word	cpu_v7m_do_idle
+	.word	cpu_v7m_dcache_clean_area
+	.word	cpu_v7m_switch_mm
+	.word	0			@ cpu_v7m_set_pte_ext
+	.word	legacy_pabort
+	.size	v7m_processor_functions, . - v7m_processor_functions
+
+	.type	cpu_arch_name, #object
+cpu_arch_name:
+	.asciz	"armv7m"
+	.size	cpu_arch_name, . - cpu_arch_name
+
+	.type	cpu_elf_name, #object
+cpu_elf_name:
+	.asciz	"v7m"
+	.size	cpu_elf_name, . - cpu_elf_name
+	.align
+
+	.section ".proc.info.init", #alloc, #execinstr
+
+	/*
+	 * Match any ARMv7-M processor core.
+	 */
+	.type	__v7m_proc_info, #object
+__v7m_proc_info:
+	.long	0x000f0000		@ Required ID value
+	.long	0x000f0000		@ Mask for ID
+	.long   0			@ proc_info_list.__cpu_mm_mmu_flags
+	.long   0			@ proc_info_list.__cpu_io_mmu_flags
+	b	__v7m_setup		@ proc_info_list.__cpu_flush
+	.long	cpu_arch_name
+	.long	cpu_elf_name
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+	.long	cpu_v7m_name
+	.long	v7m_processor_functions	@ proc_info_list.proc
+	.long	0			@ proc_info_list.tlb
+	.long	0			@ proc_info_list.user
+	.long	0			@ proc_info_list.cache
+	.size	__v7m_proc_info, . - __v7m_proc_info
+
+__v7m_setup_stack:
+	.space	4 * 8				@ 8 registers
+__v7m_setup_stack_top:
-- 
1.7.9.1



From festevam at gmail.com  Mon Mar  5 12:10:54 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 5 Mar 2012 14:10:54 -0300
Subject: 0001-i.MX35-PDK-Chunghwa-CLAA070VC01-7-WVGA-TFT-Display-s.patch
In-Reply-To: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8904@MEP-EXCH.meprolight.com>
References: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8904@MEP-EXCH.meprolight.com>
Message-ID: <CAOMZO5Bdq_LuwUtsuv2kWrdGPHB3Q9hqvj3JyP0q53BLwZD3FQ@mail.gmail.com>

Hi Alex,

Thanks for your patch.

This has already been submitted previously:
http://patchwork.ozlabs.org/patch/123404/

Also, please read Documentation/SubmittingPatches and do not attach
your patch next time.

You can use "git send-email" for example.

Regards,

Fabio Estevam

On Mon, Mar 5, 2012 at 1:57 PM, Alex Gershgorin <alexg at meprolight.com> wrote:
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From broonie at opensource.wolfsonmicro.com  Mon Mar  5 12:32:30 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 17:32:30 +0000
Subject: [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <4F54F0CE.60706@freescale.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
 <20120304133818.GE3083@opensource.wolfsonmicro.com>
 <20120305080623.GD16232@S2101-09.ap.freescale.net>
 <20120305115612.GB3224@opensource.wolfsonmicro.com>
 <20120305130707.GF16232@S2101-09.ap.freescale.net>
 <20120305131332.GM3224@opensource.wolfsonmicro.com>
 <4F54F0CE.60706@freescale.com>
Message-ID: <20120305173230.GW3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 10:58:54AM -0600, Timur Tabi wrote:
> Mark Brown wrote:

> > The DMA and SSI drivers should have some relationship with each other if
> > they're the same piece of hardware.  

> The DMA and SSI are completely separate blocks in the SOC.  On PowerPC,
> the P1022 SOC has an SSI and the standard FSL PPC DMA controller (we call
> it the Elo controller).  On i.MX, there is a completely different DMA
> controller (I'm not familiar with it), but the same exact SSI.

Right, but in both cases we're talking about the adaption layer from
ASoC to the support for the controller which is shared between
everything on the SoC (though currently the PowerPC one just talks to
the registers directly) so logically from a system perspective it's a
part of the SSI driver.

Possibly the way to go here is to just call the DMA driver something
generic (though you don't really need a separate Linux level device from
a subsystem point of view) or have a library function which is
implemented differently on each platform then have the SSI driver either
create the device or do the call.

Either way it's something the SoC code ought to be handling, individual
machine drivers shouldn't have to worry themselves about it.
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From swarren at nvidia.com  Mon Mar  5 12:33:51 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon, 5 Mar 2012 09:33:51 -0800
Subject: [PATCH v3 04/10] arm/tegra: Fix PWM clock programming
In-Reply-To: <20120303224751.GB6661@avionic-0098.mockup.avionic-design.de>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <1329923841-32017-5-git-send-email-thierry.reding@avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E52@HQMAIL01.nvidia.com>
 <20120303224751.GB6661@avionic-0098.mockup.avionic-design.de>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861C2E@HQMAIL01.nvidia.com>

Thierry Reding wrote at Saturday, March 03, 2012 3:48 PM:
> * Stephen Warren wrote:
> > Thierry Reding wrote at Wednesday, February 22, 2012 8:17 AM:
> > > PWM clock source registers in Tegra 2 have different clock source selection bit
> > > fields than other registers.  PWM clock source bits in CLK_SOURCE_PWM_0 register
> > > are located at bit field bit[30:28] while others are at bit field bit[31:30] in
> > > their respective clock source register.
> > >
> > > This patch updates the clock programming to correctly reflect that, by adding a
> > > flag to indicate the alternate bit field format and checking for it when
> > > selecting a clock source (parent clock).
> >
> > tegra30_clocks.c needs this change too, although on Tegra30, it's bits
> > 29:28 for the PWM, and bits 31:30 for non-PWM.
> 
> Okay, I'll add code for Tegra30 in the next version. I won't be able to test
> that at all because I don't have any Tegra30 hardware.

It looks like Tegra30 is already taken care of; see periph_clk_source_mask()
in tegra30_clocks.c, assuming that tegra_list_clks[] has the correct flags
set of each entry anyway. PWM does at least.

> > > diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
> >
> > +#define PERIPH_CLK_SOURCE_4BIT_MASK	(7<<28)
> > +#define PERIPH_CLK_SOURCE_4BIT_SHIFT	28
> >
> > Why is this (and the flag that enables it) called "4 bit"; the existing
> > code supports a 2-bit mux field (4-values), whereas this new code supports
> > a 3-bit field (potentially 8 values, but only 5 actually assigned).
> > Can this be renamed something more accurate, especially since on Tegra30
> > the difference is only the bit position of the field, not the number of
> > bits in the field.
> 
> This is taken directly from the Chromium tree, so I don't really know why
> that name was chosen. But since the PWM clock source register seems to be the
> only exception, how about calling the flag PWM_CLK and prefix the shift and
> mask with PWM_CLK_SOURCE_ instead?

That sounds reasonable.

-- 
nvpublic



From linux at arm.linux.org.uk  Mon Mar  5 12:37:39 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 5 Mar 2012 17:37:39 +0000
Subject: [PATCH] ARM: move mem_type's real definition to asm/mach/map.h
In-Reply-To: <1331010436-31576-1-git-send-email-shijie8@gmail.com>
References: <1331010436-31576-1-git-send-email-shijie8@gmail.com>
Message-ID: <20120305173739.GA17370@n2100.arm.linux.org.uk>

On Tue, Mar 06, 2012 at 12:07:16AM -0500, Huang Shijie wrote:
> If we use the mem_type in the driver. We will meet the compiler error:
> "error: dereferencing pointer to incomplete type"

That's a hint - you're not supposed to be using anything within this
type.  That's why it's *not* in map.h and its private to arch/arm/mm.


From s.hauer at pengutronix.de  Mon Mar  5 12:39:10 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 5 Mar 2012 18:39:10 +0100
Subject: [PATCH v2 10/17] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <1330957865-19085-11-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-11-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120305173910.GZ3852@pengutronix.de>

On Mon, Mar 05, 2012 at 10:30:58PM +0800, Shawn Guo wrote:
> Freescale PowerPC and ARM/IMX families share the same SSI IP block.
> The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
> code sharing and consolidation can happen.
> 
> This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
> in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
> IMX platform.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  sound/soc/Kconfig                        |    1 -
>  sound/soc/Makefile                       |    1 -
>  sound/soc/fsl/Kconfig                    |   92 ++++++++++++++++++++++++++++++
>  sound/soc/fsl/Makefile                   |   22 +++++++
>  sound/soc/{imx => fsl}/eukrea-tlv320.c   |    2 +-
>  sound/soc/{imx => fsl}/imx-audmux.c      |    0
>  sound/soc/{imx => fsl}/imx-audmux.h      |    0
>  sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c |    0

Maybe this is the right time to rename this file to something like
imx-pcm-dma.c since it has nothing to do with mx2 anymore.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From alexg at meprolight.com  Mon Mar  5 12:39:57 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Mon, 5 Mar 2012 19:39:57 +0200
Subject: 0001-i.MX35-PDK-Chunghwa-CLAA070VC01-7-WVGA-TFT-Display-s.patch
In-Reply-To: <CAOMZO5Bdq_LuwUtsuv2kWrdGPHB3Q9hqvj3JyP0q53BLwZD3FQ@mail.gmail.com>
References: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8904@MEP-EXCH.meprolight.com>,
 <CAOMZO5Bdq_LuwUtsuv2kWrdGPHB3Q9hqvj3JyP0q53BLwZD3FQ@mail.gmail.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8905@MEP-EXCH.meprolight.com>


Hi Fabio,

Thanks for you comment.

>Thanks for your patch.

>This has already been submitted previously:
>http://patchwork.ozlabs.org/patch/123404/

>Also, please read Documentation/SubmittingPatches and do not attach
>your patch next time.

>You can use "git send-email" for example.

I always used git send-email, my problem is the SMTP server does not exit out.
I think it will be solved by tomorrow.

Thanks,
Alex Gershgorin 

 


From s.hauer at pengutronix.de  Mon Mar  5 12:42:32 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 5 Mar 2012 18:42:32 +0100
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120305174232.GA3852@pengutronix.de>

On Mon, Mar 05, 2012 at 10:31:05PM +0800, Shawn Guo wrote:
> This is the initial imx-sgtl5000 machine driver support with only
> playback dai link implemented.  More features can be added on top
> of it later.

Are there problems with capturing? It should be trivial to add and
it would be much more confident that this series as a whole works as
expected.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From broonie at opensource.wolfsonmicro.com  Mon Mar  5 12:46:13 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 17:46:13 +0000
Subject: [PATCH v2 01/17] ASoC: imx: move eukrea audmux call into ASoC
 machine driver
In-Reply-To: <1330957865-19085-2-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120305174612.GY3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 10:30:49PM +0800, Shawn Guo wrote:
> It moves eukrea audmux configuration call from board file into ASoC
> machine driver eukrea-tlv320, so that it gets aligned wm1133-ev1 and
> mx27vis-aic32x4, and more importantly it will ease the moving of audmux
> into sound/soc/imx as a platform driver later.

Sascha, this and the second patch look totally uncontroversial - can we
just apply them now so we don't need to keep reviewing them?
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From swarren at nvidia.com  Mon Mar  5 12:51:15 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon, 5 Mar 2012 09:51:15 -0800
Subject: [PATCH v3 07/10] arm/tegra: Add PWFM controller device tree
 probing
In-Reply-To: <20120303225404.GC6661@avionic-0098.mockup.avionic-design.de>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <1329923841-32017-8-git-send-email-thierry.reding@avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E67@HQMAIL01.nvidia.com>
 <20120303225404.GC6661@avionic-0098.mockup.avionic-design.de>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861C46@HQMAIL01.nvidia.com>

Thierry Reding wrote at Saturday, March 03, 2012 3:54 PM:
> * Stephen Warren wrote:
> > Thierry Reding wrote at Wednesday, February 22, 2012 8:17 AM:
> > > Add auxdata to instantiate a device tree for the PWFM controller and
> > > include a corresponding node in the device tree.
> >
> > > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> >
> > > +	pwm: pwm at 7000a000 {
> > > +		compatible = "nvidia,tegra20-pwm";
> > > +		reg = <0x7000a000 0x100>;
> > > +		#pwm-cells = <2>;
> > > +	};
> >
> > The compatible value probably should list both Tegra30 and Tegra20, so
> > we can know exactly which HW is present, just in case we need to turn
> > on some bug-fix only for one of the variants:
> >
> >     compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
> 
> I'm confused. If I know exactly that the hardware is Tegra30 (which it
> definitely should be if I include tegra30.dtsi), then why list "tegra20-pwm"
> as compatible?
> 
> Or did you mean to list tegra30-pwm as compatible value in the PWM driver?

Standard practice is to list the exact model of the HW as the first entry
in compatible in the .dts file:

    nvidia,tegra30-pwm

This is so that the DT always describes exactly which HW model is actually
present, so that if HW-model-specific WARs/... are required in the future,
the DT already lists that information up-front.

Then additionally list any older HW models that this HW is also compatible
with:

    nvidia,tegra20-pwm


This allows the driver to list just nvidia,tegra20-pwm but still bind
to DT nodes that are for later HW.

So, in other words, you end up with the following in the .dts/.dtsi file:

    compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";

> > Could you also write binding documentation, in particular explaining
> > what the two pwm-cells are specifically for Tegra:
> >
> > Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> >
> > (although perhaps that'd be part of the previous patch which implements
> > the driver)
> 
> Actually for Tegra the values would be those documented in the generic
> binding because Tegra uses of_pwm_simple_xlate(). Does it still make sense to
> add a Tegra-specific binding?

There should still be a Tegra-specific binding. Without it, there's no
definite way to know whether the "standard" properties actually apply,
or someone simply forgot to document it.

-- 
nvpublic



From matt at genesi-usa.com  Mon Mar  5 12:55:07 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 5 Mar 2012 11:55:07 -0600
Subject: [PATCH v2 01/17] ASoC: imx: move eukrea audmux call into ASoC
 machine driver
In-Reply-To: <20120305174612.GY3224@opensource.wolfsonmicro.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-2-git-send-email-shawn.guo@linaro.org>
 <20120305174612.GY3224@opensource.wolfsonmicro.com>
Message-ID: <CAKGA1b=4X+ccQXjZVa1DYpRYC0NT0A9AqwgG-ApkzboRkC3sJg@mail.gmail.com>

How will this stand up to an machine audio fabric that, like
imx-sgtl5000 going around BSPs and Linaro and so on since the dawn of
time, supports multiple boards but very different audmux
configurations? Is this just a stopgap until the DT properly describes
it?

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.



On Mon, Mar 5, 2012 at 11:46 AM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Mon, Mar 05, 2012 at 10:30:49PM +0800, Shawn Guo wrote:
>> It moves eukrea audmux configuration call from board file into ASoC
>> machine driver eukrea-tlv320, so that it gets aligned wm1133-ev1 and
>> mx27vis-aic32x4, and more importantly it will ease the moving of audmux
>> into sound/soc/imx as a platform driver later.
>
> Sascha, this and the second patch look totally uncontroversial - can we
> just apply them now so we don't need to keep reviewing them?
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From tony at atomide.com  Mon Mar  5 13:07:29 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 10:07:29 -0800
Subject: [PATCH] Linux OMAP: Add omap_reserve functionality
In-Reply-To: <1323867028-8496-1-git-send-email-alexg@meprolight.com>
References: <1323867028-8496-1-git-send-email-alexg@meprolight.com>
Message-ID: <20120305180728.GA12083@atomide.com>

* Alex <alexg at meprolight.com> [111214 04:23]:
> This patch adds omap_reserve functionality to board-omap3logic.c

Thanks applying into board branch.

Regards,

Tony


From matt at genesi-usa.com  Mon Mar  5 13:09:13 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 5 Mar 2012 12:09:13 -0600
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120305174232.GA3852@pengutronix.de>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
 <20120305174232.GA3852@pengutronix.de>
Message-ID: <CAKGA1bn7y8xQn-o=8CZj5nwcvaBvHwxqM0Q2wzFAwJsSgi1sfA@mail.gmail.com>

There is in the BSP but the BSP driver is trying to be way too fancy
with I2S settings on the imx-ssi driver you wrote (it works well for
AC97, but for SSI in I2S slave mode there are so many hacks upon hacks
"they" have presented, it'd never mainline)

Having the codec provide clocks in slave mode works great in fsl-ssi
because it doesn't set the chip up any other way, but I've had serious
problems here whereby playing back a 48khz, 16-bit audio stream and
recording in ANYTHING else seems to make the playback stream slow
motion, but I can't trace whether it's the SSI config (seems unlikely
as the only valid STXCCR bit in slave mode is the word length) or the
codec config. In theory the playback and capture should be serialized
by the driver, though, right? It wouldn't be possible to be a slave to
the codec if it had to run the clock two different rates at the same
time.. app1 sends a sample buffer, codec does dma, app2 requests
capture buffer, codec does dma, they can't happen at the same time,
maybe we are missing an important mutex or spinlock here that would
enforce this and stop the configuration changing mid-stream.. I'm far
from the ALSA expert though)

If adding capture support means having to make the SSI driver work in
I2S master mode and do the laborious work of actually dividing the SSI
clock, configuring the external PLL etc. so it can clock the codec
appropriately for this mode then that's what will have to be done, and
I agree with Sascha, whatever the solution it should be something that
gets done now (not least because I kind of want audio here.. :) along
with quite possibly adapting the current imx-ssi driver (as opposed to
the fsl-ssi driver) to be fsl-ssi-ac97 vs fsl-ssi-imx so we have
dedicated operation (which will make the AC97/FIQ select much easier
to determine).

While we're at it; did anyone patch arch/arm/mach-imx/ssi-fiq.S to be
compiled in .arm mode yet? I can't find it in a tree or the list but I
could be wrong. I am sure we mutually agreed (or at least Russell
decided) on this to get thumb kernels to build again since none of the
dependent processors/config selections are M-profile?

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.



On Mon, Mar 5, 2012 at 11:42 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Mon, Mar 05, 2012 at 10:31:05PM +0800, Shawn Guo wrote:
>> This is the initial imx-sgtl5000 machine driver support with only
>> playback dai link implemented. ?More features can be added on top
>> of it later.
>
> Are there problems with capturing? It should be trivial to add and
> it would be much more confident that this series as a whole works as
> expected.
>
> Sascha
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From swarren at nvidia.com  Mon Mar  5 13:10:22 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon, 5 Mar 2012 10:10:22 -0800
Subject: What's in tegra.git for 3.4
In-Reply-To: <20120304185901.GI31064@quad.lixom.net>
References: <CAOesGMjnWPgSa44hgRu+d0jrQLm9KuOcuufg9V8fYZ8TytsbPw@mail.gmail.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BD8BCF6A@HQMAIL01.nvidia.com>
 <20120304185901.GI31064@quad.lixom.net>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861C59@HQMAIL01.nvidia.com>

Olof Johansson wrote at Sunday, March 04, 2012 11:59 AM:
> On Mon, Feb 27, 2012 at 09:41:56AM -0800, Stephen Warren wrote:
> > Olof Johansson wrote at Sunday, February 26, 2012 3:51 PM:
> > > We're closing in on when things need to be in the sub-arch trees in
> > > time to get merged for the next merge window. The shortlog below is
> > > what i have queued up today.
> >
> > The following are in patchwork and should probably be picked up:
> 
> Btw, patchwork is down, so I had to guess which patches were being referred to.
> While it's convenient to have the links, also having the patch subject would be
> good. :-)
...
> > I need to ping Ben on:
> > http://patchwork.ozlabs.org/patch/139494/

i2c: tegra: Remove unnecessary write to INT_STATUS

> Yeah, we can take it through tegra if needed, we've done it in the past.

For reference, Wolfram Sang has applied this to his i2c-embedded tree,
so it's going in through there.

-- 
nvpublic



From khilman at ti.com  Mon Mar  5 13:12:15 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 05 Mar 2012 10:12:15 -0800
Subject: [PATCH] ARM: OMAP2+: voltage: ensure voltage used is exact
 voltage from OPP table
In-Reply-To: <1330940487.2116.119.camel@sokoban> (Tero Kristo's message of
 "Mon, 5 Mar 2012 11:41:27 +0200")
References: <1330728121-26664-1-git-send-email-khilman@ti.com>
 <1330940487.2116.119.camel@sokoban>
Message-ID: <877gyyor28.fsf@ti.com>

Tero Kristo <t-kristo at ti.com> writes:

> On Fri, 2012-03-02 at 14:42 -0800, Kevin Hilman wrote:
>> When using the SMPS regulators to scale voltages, the regulator
>> framework may pass a minimum voltage that is not an exact OPP voltage.
>> For the VC/VP controlled voltage domains, we must ensure that the
>> voltage requested is the exact voltage from the OPP table.  This is
>> especially critical when using SR.
>> 
>> To fix, voltdm_scale() uses the target voltage passed to walk through
>> the OPP voltages until it finds a voltage that is >= one of the OPP
>> voltages.
>
> I have just one question to this, how about smartreflex class1p5? Do we
> have any plans for that one? The old implementation at least was using
> voltdm_scale, so if we modify this function, smartreflex class1p5
> doesn't work anymore.

Since it's not in mainline, that is not my concern at the moment.  We
can worry about SR1.5 when I someone is motivated to push it upstream.

> Otherwise this patch looks good to me.

Thanks for looking.

Kevin


From thierry.reding at avionic-design.de  Mon Mar  5 13:15:55 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Mon, 5 Mar 2012 19:15:55 +0100
Subject: [PATCH v3 07/10] arm/tegra: Add PWFM controller device tree
 probing
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE861C46@HQMAIL01.nvidia.com>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <1329923841-32017-8-git-send-email-thierry.reding@avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E67@HQMAIL01.nvidia.com>
 <20120303225404.GC6661@avionic-0098.mockup.avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861C46@HQMAIL01.nvidia.com>
Message-ID: <20120305181555.GA22459@avionic-0098.adnet.avionic-design.de>

* Stephen Warren wrote:
> Thierry Reding wrote at Saturday, March 03, 2012 3:54 PM:
> > I'm confused. If I know exactly that the hardware is Tegra30 (which it
> > definitely should be if I include tegra30.dtsi), then why list "tegra20-pwm"
> > as compatible?
> > 
> > Or did you mean to list tegra30-pwm as compatible value in the PWM driver?
> 
> Standard practice is to list the exact model of the HW as the first entry
> in compatible in the .dts file:
> 
>     nvidia,tegra30-pwm
> 
> This is so that the DT always describes exactly which HW model is actually
> present, so that if HW-model-specific WARs/... are required in the future,
> the DT already lists that information up-front.
> 
> Then additionally list any older HW models that this HW is also compatible
> with:
> 
>     nvidia,tegra20-pwm
> 
> 
> This allows the driver to list just nvidia,tegra20-pwm but still bind
> to DT nodes that are for later HW.
> 
> So, in other words, you end up with the following in the .dts/.dtsi file:
> 
>     compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";

Okay, that makes sense now. For some reason I thought you were suggesting to
put the same into tegra20.dtsi as well. I'll add nvidia,tegra30-pwm to the
compatible list in the driver and list both values in the tegra30.dtsi.
Thanks for explaining.

> > > Could you also write binding documentation, in particular explaining
> > > what the two pwm-cells are specifically for Tegra:
> > >
> > > Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> > >
> > > (although perhaps that'd be part of the previous patch which implements
> > > the driver)
> > 
> > Actually for Tegra the values would be those documented in the generic
> > binding because Tegra uses of_pwm_simple_xlate(). Does it still make sense to
> > add a Tegra-specific binding?
> 
> There should still be a Tegra-specific binding. Without it, there's no
> definite way to know whether the "standard" properties actually apply,
> or someone simply forgot to document it.

Understood. I assume that both the Tegra20 and Tegra30 variants should have
explicit bindings then as well, right?

Thierry
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From khilman at ti.com  Mon Mar  5 13:18:13 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 05 Mar 2012 10:18:13 -0800
Subject: [PATCH v3] ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
 regulators
In-Reply-To: <20120301204553.GA21841@legolas.emea.dhcp.ti.com> (Felipe Balbi's
 message of "Thu, 1 Mar 2012 22:45:54 +0200")
References: <1330006564-13290-1-git-send-email-mporter@ti.com>
 <87wr74gis6.fsf@ti.com>
 <20120301204553.GA21841@legolas.emea.dhcp.ti.com>
Message-ID: <87pqcqnc7u.fsf@ti.com>

Felipe Balbi <balbi at ti.com> writes:

> Hi,
>
> On Thu, Mar 01, 2012 at 12:36:57PM -0800, Kevin Hilman wrote:
>> Matt Porter <mporter at ti.com> writes:
>> 
>> > This fixes smsc911x support on platforms using gpmc_smsc911x_init().
>> >
>> > Commit c7e963f6888816 (net/smsc911x: Add regulator support) added
>> > the requirement that platforms provide vdd33a and vddvario supplies.
>> >
>> > Signed-off-by: Matt Porter <mporter at ti.com>
>> 
>> [...]
>> 
>> >  /*
>> >   * Initialize smsc911x device connected to the GPMC. Note that we
>> >   * assume that pin multiplexing is done in the board-*.c file,
>> > @@ -55,6 +101,12 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
>> >  
>> >  	gpmc_cfg = board_data;
>> >  
>> > +	ret = platform_device_register(&gpmc_smsc911x_regulator);
>> > +	if (ret < 0) {
>> > +		pr_err("Unable to register smsc911x regulators: %d\n", ret);
>> > +		return;
>> > +	}
>> > +
>> 
>> Boards that have more than one instance of the smsc911x (OMAP3/Overo)
>> barf here because of trying to register the same device twice.
>> 
>> We need something like the patch below to make Overo boot again.
>> 
>> Kevin
>> 
>> 
>> 
>> From 4114dea2fb897ab75d05eaa943d29454034fc025 Mon Sep 17 00:00:00 2001
>> From: Kevin Hilman <khilman at ti.com>
>> Date: Thu, 1 Mar 2012 12:30:42 -0800
>> Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulators once
>> 
>> commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
>> regulators) added regulators which are registered during
>> gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
>> than one instance of the SMSC911x and result in attempting to register
>> the same regulator more than once which causes a panic().  Fix this by
>> tracking the regulator registration ensuring only a single device is
>> registered.
>> 
>> Cc: Matt Porter <mporter at ti.com>
>> Signed-off-by: Kevin Hilman <khilman at ti.com>
>> ---
>>  arch/arm/mach-omap2/gpmc-smsc911x.c |   14 ++++++++++----
>>  1 file changed, 10 insertions(+), 4 deletions(-)
>> 
>> diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
>> index bbb870c..95e6c7d 100644
>> --- a/arch/arm/mach-omap2/gpmc-smsc911x.c
>> +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
>> @@ -88,6 +88,8 @@ static struct platform_device gpmc_smsc911x_regulator = {
>>  	},
>>  };
>>  
>> +static bool regulator_registered;
>> +
>>  /*
>>   * Initialize smsc911x device connected to the GPMC. Note that we
>>   * assume that pin multiplexing is done in the board-*.c file,
>> @@ -101,10 +103,14 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
>>  
>>  	gpmc_cfg = board_data;
>>  
>> -	ret = platform_device_register(&gpmc_smsc911x_regulator);
>> -	if (ret < 0) {
>> -		pr_err("Unable to register smsc911x regulators: %d\n", ret);
>> -		return;
>> +	if (!regulator_registered) {
>> +		ret = platform_device_register(&gpmc_smsc911x_regulator);
>> +		if (ret < 0) {
>> +			pr_err("Unable to register smsc911x regulators: %d\n",
>> +			       ret);
>> +			return;
>> +		}
>> +		regulator_registered = true;
>
> Wow, this is quite a hack. Is the regulator part of the SMSC911x
> device or is it outside ? If it's outside the SMSC91xx (which I
> believe it is) there should be a regulator driver instead of this
> hack.  For boards which don't provide such a regulator (and tie the
> supply pin to some constant voltage source) there should be a constant
> regulator supplying the pin. But this patch is quite hacky.

Are you referring to my patch or to the original $SUBJECT patch?  It's
not terribly clear.

My patch doesn't add any regulators, it just fixes a bug when this init
function is called more than once.

The addition of the regulators was done in $SUBJECT patch, not my fix.

In either case $SUBJECT patch is already in Tony's fixes queue, so if it
is going be merged, then my fix above is needed also to not break
Overo and any other platform that has more than one smsc911x instance.

Kevin


From tony at atomide.com  Mon Mar  5 13:19:32 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 10:19:32 -0800
Subject: [PATCH v3 1/2] ARM: OMAP: move generic EMAC init to separate file
In-Reply-To: <1330593544-25411-1-git-send-email-grinberg@compulab.co.il>
References: <1324423590-32489-1-git-send-email-yanok@emcraft.com>
 <1330593544-25411-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <20120305181932.GC12083@atomide.com>

* Igor Grinberg <grinberg at compulab.co.il> [120301 00:47]:
> From: Ilya Yanok <yanok at emcraft.com>
> 
> AM35xx SoCs include DaVinci EMAC IP. Initialization code in
> board-am3517evm.c is pretty board independent and will work for any
> AM35xx based board so move this code to it's own file to be reused by
> other boards.
> 
> Signed-off-by: Ilya Yanok <yanok at emcraft.com>
> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
> ---
> v3:	- use DEFINE_RES_* macros
> 	- check error of platform_device_register()
> 	- introduce a default MDIO bus frequency define
> 
> Tony, this patch has been floating for about two months:
> http://www.spinics.net/lists/linux-omap/msg62160.html
> can it be applied for 3.4?

Yes sorry for the delays, applying this and the related
cm-t3517 patch to board branch.

Regards,

Tony


From tony at atomide.com  Mon Mar  5 13:23:11 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 10:23:11 -0800
Subject: [PATCH] RM: OMAP4: board-4430sdp: don't initialize value that
 is never used
In-Reply-To: <1328823034-9668-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1328823034-9668-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120305182311.GD12083@atomide.com>

* Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de> [120209 13:00]:
> sdp4430_spi_board_info.irq was initialized to ETH_KS8851_IRQ and in
> omap_4430sdp_init() overwritten with gpio_to_irq(ETH_KS8851_IRQ) before
> sdp4430_spi_board_info was registered. This is a bit confusing, so
> better don't initialize .irq and document that it is set later.

Thanks applying into board branch.

Regards,

Tony


From swarren at nvidia.com  Mon Mar  5 13:30:43 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon, 5 Mar 2012 10:30:43 -0800
Subject: [RFC PATCH] of: DMA helpers: manage generic requests specification
In-Reply-To: <4F54BC2E.3040702@ti.com>
References: <4F22DEF2.5000807@ti.com>
 <1330527248-4350-1-git-send-email-nicolas.ferre@atmel.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF217B@HQMAIL01.nvidia.com>
 <4F54BC2E.3040702@ti.com>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861C6E@HQMAIL01.nvidia.com>

Cousson, Benoit wrote at Monday, March 05, 2012 6:14 AM:
> On 2/29/2012 9:54 PM, Stephen Warren wrote:
> > Nicolas Ferre wrote at Wednesday, February 29, 2012 7:54 AM:
> >> By making DMA controllers register a generic translation
> >> function, we allow the management of any type of DMA requests
> >> specification.
> >> The void * output of an of_dma_xlate() function that will be implemented
> >> by the DMA controller can carry any type of "dma-request" argument.
> >>
> >> The DMA client will search its associated DMA controller in the list
> >> and call the registered of_dam_xlate() function to retrieve the
> >> request values.
> >>
> >> One simple xlate function is provided for the "single number" type
> >> of request biding.
> >>
> >> This implementation is independent from dmaengine so it can also be
> >> used by legacy drivers.
> >
> > At a high level this seems along the right lines.
> >
> > The big issue I see is the lack of type-safety in of_get_dma_request()'s
> > out_data pointer: The DMA xlate function will assume it points at some
> > particular type, and the client is responsible for allocating that
> > correct type. However, it's "user"-supplied device tree data that hooks
> > the two together, and there could easily be mismatches, thus causing
> > the xlate function to trash memory.
> >
> > Could each DMA controller (or type of out_data) have some enum in the
> > kernel that the client passes in, and the DMA engine validates matches
> > its expectations, to prevent this kind of thing?
> 
> Beside u32 and string, do we know what kind of parameters we can expect
> to retrieve?
> Because we can potentially reduce the scope to these two types only.

I wondered whether different drivers would return arbitrary driver-specific
structs, so that the DT specific would encode not only the DMA request
number, but perhaps some/all of the DMA parameters like transfer size,
wrap, even DMA FIFO address, ...

Still, there might not be much point in doing that, since drivers (at
least on Tegra) are already manually passing this information to the DMA
driver in the non-DT case, so we can just continue doing that same thing.

-- 
nvpublic



From tony at atomide.com  Mon Mar  5 13:32:35 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 10:32:35 -0800
Subject: [PATCH] ARM: omap: pandora: add support for backlight and poweroff
In-Reply-To: <1329605180-24939-1-git-send-email-notasas@gmail.com>
References: <1329605180-24939-1-git-send-email-notasas@gmail.com>
Message-ID: <20120305183235.GF12083@atomide.com>

* Grazvydas Ignotas <notasas at gmail.com> [120218 14:15]:
> Add platform data for drivers that recently appeared in kernel:
> backlight and TWL4030 poweroff support.

Thanks applying into board branch.

Regards,

Tony


From tony at atomide.com  Mon Mar  5 13:35:59 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 10:35:59 -0800
Subject: [PATCH RESEND] ARM: OMAP: enable Bluetooth on the PandaBoard
In-Reply-To: <1330019577-2106-1-git-send-email-mgherzan@gmail.com>
References: <1330019577-2106-1-git-send-email-mgherzan@gmail.com>
Message-ID: <20120305183558.GG12083@atomide.com>

* Mircea Gherzan <mgherzan at gmail.com> [120223 09:21]:
> The PandaBoard features a Texas Instruments WiLink7 Bluetooth
> chip, supported by the "btwilink" driver.

Thanks applying into board branch.

Regards,

Tony


From tony at atomide.com  Mon Mar  5 13:38:42 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 10:38:42 -0800
Subject: [PATCH] arm: omap: add minimal support for Nokia RM-696
In-Reply-To: <1330967337-9634-1-git-send-email-aaro.koskinen@nokia.com>
References: <1330967337-9634-1-git-send-email-aaro.koskinen@nokia.com>
Message-ID: <20120305183841.GH12083@atomide.com>

* Aaro Koskinen <aaro.koskinen at nokia.com> [120305 08:25]:
> Add minimal support for Nokia RM-696 board.

Thanks applying into board branch.

Regards,

Tony


From swarren at nvidia.com  Mon Mar  5 13:39:22 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon, 5 Mar 2012 10:39:22 -0800
Subject: [PATCH v3 07/10] arm/tegra: Add PWFM controller device tree
 probing
In-Reply-To: <20120305181555.GA22459@avionic-0098.adnet.avionic-design.de>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <1329923841-32017-8-git-send-email-thierry.reding@avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF1E67@HQMAIL01.nvidia.com>
 <20120303225404.GC6661@avionic-0098.mockup.avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861C46@HQMAIL01.nvidia.com>
 <20120305181555.GA22459@avionic-0098.adnet.avionic-design.de>
Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF17BE861C74@HQMAIL01.nvidia.com>

Thierry Reding wrote at Monday, March 05, 2012 11:16 AM:
> * Stephen Warren wrote:
> > Thierry Reding wrote at Saturday, March 03, 2012 3:54 PM:
...
> > > > Could you also write binding documentation, in particular explaining
> > > > what the two pwm-cells are specifically for Tegra:
> > > >
> > > > Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
> > > >
> > > > (although perhaps that'd be part of the previous patch which implements
> > > > the driver)
> > >
> > > Actually for Tegra the values would be those documented in the generic
> > > binding because Tegra uses of_pwm_simple_xlate(). Does it still make sense to
> > > add a Tegra-specific binding?
> >
> > There should still be a Tegra-specific binding. Without it, there's no
> > definite way to know whether the "standard" properties actually apply,
> > or someone simply forgot to document it.
> 
> Understood. I assume that both the Tegra20 and Tegra30 variants should have
> explicit bindings then as well, right?

To date, the bindings for the two chips have been similar enough we've
only written a single bindings document that covers both. For the
different compatible values, I've been assuming that's such a base part
of standard DT usage that those differences didn't even require
documenting in the individual bindings. For example, I've written e.g.:

Required properties:
- compatible : "nvidia,tegra20-i2s"

Or:

Required properties:
- compatible: Should be "nvidia,<chip>-apbdma"

And assumed these would be expanded as appropriate by the DT author.

Of course, if there were significant bindings differences (rather than
HW differences that were largely transparent to bindings) then yes I'd
expected separate nvidia,tegra20-foo.txt and nvidia,tegra30-foo.txt.

-- 
nvpublic



From tony at atomide.com  Mon Mar  5 13:41:42 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 10:41:42 -0800
Subject: [PATCH] ARM: OMAP4: Add support for Variscite OMAP4460
 System-On-Module
In-Reply-To: <1326898096-4899-1-git-send-email-uri.y@variscite.com>
References: <1326898096-4899-1-git-send-email-uri.y@variscite.com>
Message-ID: <20120305184142.GI12083@atomide.com>

Hi,

* Uri Yosef <uri.y at variscite.com> [120118 06:13]:
> From: Uri Yosef <uri at embedox.com>
> 
> Add support for Variscite OMAP4460 System-On-Module and development kit board.
> Working: LCD, HDMI, USB, UART, Ethernet.

For reference, we're trying to remove board-*.c files by
changing over to device tree. So new board-*.c files will
be merged. You might want to look at booting your board
using board-generic.c and a related .dts file.

While this transition is happening, I can carry some
board-*.c files in the testing-board branch until devices
start working sufficiently for board-generic.c to be
usable.

Regards,

Tony


From nicolas.pitre at linaro.org  Mon Mar  5 13:49:35 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Mon, 5 Mar 2012 13:49:35 -0500 (EST)
Subject: [PULL REQUEST v2] ARM: kirkwood: fdt: convert kirkwood init
 funcs to fdt
In-Reply-To: <201203022118.05796.arnd@arndb.de>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <20120302200034.GQ11986@titan.lakedaemon.net>
 <201203022035.44672.arnd@arndb.de> <201203022118.05796.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1203051344130.31242@xanadu.home>

On Fri, 2 Mar 2012, Arnd Bergmann wrote:

> On Friday 02 March 2012, Arnd Bergmann wrote:
> > On Friday 02 March 2012, Jason wrote:
> > > The following changes since commit 759a45185ac0e4dfaf8bbfcb390ec73aca4b7a34:
> > > 
> > >   ARM: kirkwood: convert uart0 to devicetree. (2012-02-27 16:21:44 +0000)
> > > 
> > > are available in the git repository at:
> > >   git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_test
> > > 
> > 
> > Applied to next/dt branch.
> 
> On second thought, I should probably wait for the maintainer to comment
> as well ;-)
> 
> Nico, does this look ok to you?

The clock frequency part being hardcoded to 200000 in the common .dtsi 
file looks wrong.  The clock may differ, and it used to (and should) be 
probed at run time, please see kirkwood_find_tclk().


Nicolas


From jason at lakedaemon.net  Mon Mar  5 14:15:46 2012
From: jason at lakedaemon.net (Jason)
Date: Mon, 5 Mar 2012 14:15:46 -0500
Subject: [PULL REQUEST v2] ARM: kirkwood: fdt: convert kirkwood init
 funcs to fdt
In-Reply-To: <alpine.LFD.2.02.1203051344130.31242@xanadu.home>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <20120302200034.GQ11986@titan.lakedaemon.net>
 <201203022035.44672.arnd@arndb.de>
 <201203022118.05796.arnd@arndb.de>
 <alpine.LFD.2.02.1203051344130.31242@xanadu.home>
Message-ID: <20120305191546.GK5050@titan.lakedaemon.net>

On Mon, Mar 05, 2012 at 01:49:35PM -0500, Nicolas Pitre wrote:
> On Fri, 2 Mar 2012, Arnd Bergmann wrote:
> 
> > On Friday 02 March 2012, Arnd Bergmann wrote:
> > > On Friday 02 March 2012, Jason wrote:
> > > > The following changes since commit 759a45185ac0e4dfaf8bbfcb390ec73aca4b7a34:
> > > > 
> > > >   ARM: kirkwood: convert uart0 to devicetree. (2012-02-27 16:21:44 +0000)
> > > > 
> > > > are available in the git repository at:
> > > >   git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_test
> > > > 
> > > 
> > > Applied to next/dt branch.
> > 
> > On second thought, I should probably wait for the maintainer to comment
> > as well ;-)
> > 
> > Nico, does this look ok to you?
> 
> The clock frequency part being hardcoded to 200000 in the common .dtsi 
> file looks wrong.  The clock may differ, and it used to (and should) be 
> probed at run time, please see kirkwood_find_tclk().

So, should I EXPORT_SYMBOL_GPL(kirkwood_find_tclk); and have each driver
call it?

One alternate idea I had was to have kirkwood-dreamplug.dts root hold

tclk: clock-frequency = <200000000>;

and then have the drivers ask for it.  afaict, tclk is constant per
board.

I'm fine with either way, but I'd rather have it in the dt.

thx,

Jason.


From nico at fluxnic.net  Mon Mar  5 14:21:47 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 14:21:47 -0500 (EST)
Subject: [PATCH v3 02/30] ARM: provide runtime hook for ioremap/iounmap
In-Reply-To: <1330658022-14559-3-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-3-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203051415150.31242@xanadu.home>

On Thu, 1 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> We have compile time over-ride of ioremap and iounmap, but an run-time
> override is needed for multi-platform builds.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>

Acked-by: Nicolas Pitre <nico at linaro.org>

I was hoping that the number of platform requiring this would have been 
small enough to just leave them with a compile time override and simply 
keep them out of a multi-SOC kernel.  But it looks like even some modern 
architectures require this.

Given that the majority of existing platforms don't need the 
indirection, should we make this indirection conditional on 
CONFIG_NEED_IOREMAP_HOOK and let those who need it select it?  Or maybe 
this isn't performance critical and we just don't care?  In any case I'd 
like to see such reasoning captured in the commit log.

> ---
>  arch/arm/include/asm/io.h |    8 ++++++--
>  arch/arm/mm/ioremap.c     |    6 ++++++
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
> index 9275828..9bf9d00 100644
> --- a/arch/arm/include/asm/io.h
> +++ b/arch/arm/include/asm/io.h
> @@ -264,9 +264,13 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
>   * Documentation/io-mapping.txt.
>   *
>   */
> +
> +extern void __iomem * (*arch_ioremap)(unsigned long, size_t, unsigned int);
> +extern void (*arch_iounmap)(volatile void __iomem *);
> +
>  #ifndef __arch_ioremap
> -#define __arch_ioremap			__arm_ioremap
> -#define __arch_iounmap			__iounmap
> +#define __arch_ioremap			arch_ioremap
> +#define __arch_iounmap			arch_iounmap
>  #endif
>  
>  #define ioremap(cookie,size)		__arch_ioremap((cookie), (size), MT_DEVICE)
> diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
> index 80632e8..d164dea 100644
> --- a/arch/arm/mm/ioremap.c
> +++ b/arch/arm/mm/ioremap.c
> @@ -314,6 +314,9 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
>  }
>  EXPORT_SYMBOL(__arm_ioremap);
>  
> +void __iomem * (*arch_ioremap)(unsigned long , size_t , unsigned int ) = __arm_ioremap;
> +EXPORT_SYMBOL(arch_ioremap);
> +
>  /*
>   * Remap an arbitrary physical address space into the kernel virtual
>   * address space as memory. Needed when the kernel wants to execute
> @@ -370,3 +373,6 @@ void __iounmap(volatile void __iomem *io_addr)
>  	vunmap(addr);
>  }
>  EXPORT_SYMBOL(__iounmap);
> +
> +void (*arch_iounmap)(volatile void __iomem *) = __iounmap;
> +EXPORT_SYMBOL(arch_iounmap);
> -- 
> 1.7.5.4
> 


From nico at fluxnic.net  Mon Mar  5 14:26:33 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 14:26:33 -0500 (EST)
Subject: [PATCH v3 15/30] ARM: dove: add explicit include of dove.h to
 addr-map.c
In-Reply-To: <1330658022-14559-16-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-16-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203051426110.31242@xanadu.home>

On Thu, 1 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> In preparation to remove mach/io.h, add explicit include of mach/dove.h
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/mach-dove/addr-map.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
> index 98b8c83..2a06c01 100644
> --- a/arch/arm/mach-dove/addr-map.c
> +++ b/arch/arm/mach-dove/addr-map.c
> @@ -14,6 +14,7 @@
>  #include <linux/io.h>
>  #include <asm/mach/arch.h>
>  #include <asm/setup.h>
> +#include <mach/dove.h>
>  #include <plat/addr-map.h>
>  #include "common.h"
>  
> -- 
> 1.7.5.4
> 


From tony at atomide.com  Mon Mar  5 14:27:43 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 11:27:43 -0800
Subject: [PATCH v3 1/3] ARM: OMAP1: ams-delta: set up regulator over
 modem reset GPIO pin
In-Reply-To: <1330963512-20413-2-git-send-email-jkrzyszt@tis.icnet.pl>
References: <1330963512-20413-1-git-send-email-jkrzyszt@tis.icnet.pl>
 <1330963512-20413-2-git-send-email-jkrzyszt@tis.icnet.pl>
Message-ID: <20120305192742.GK12083@atomide.com>

* Janusz Krzysztofik <jkrzyszt at tis.icnet.pl> [120305 07:35]:
> The Amstrad Delta on-board latch2 bit named MODEM_NRESET, now available
> as a GPIO pin AMS_DELTA_GPIO_PIN_NMODEM_RESET, is used to power up/down
> (bring into/out of a reset state) two distinct on-board devices
> simultaneously: the modem, and the voice codec. As a consequence, that
> bit is, or can be, manipulated concurrently by two drivers, or their
> platform provided hooks.
> 
> Instead of updating those drivers to use the gpiolib API as a new method
> of controlling the MODEM_NRESET pin state, like it was done to other
> drivers accessing latch2 pins, and still being vulnerable to potential
> concurrency conflicts, or trying to solve that sharing issue with a
> custom piece of code, set up a fixed regulator device on top of that
> GPIO pin, with the intention of updating both drivers to manipulate that
> regulator, not the GPIO pin directly.
> 
> Before the ASoC driver is updated and the modem platform data expanded
> with a power management callback for switching its power, the
> ams_delta_latch_write() function, which still provides the old API for
> accessing latch2 functionality from not updated drivers, is modified to
> toggle the regulator instead of the MODEM_NRESET GPIO pin.  A helper
> function provided for balancing the regulator enable/disable operations,
> together with the consumer data needed for tracking the regulator state,
> will be removed once the drivers are updated.
> 
> Depends on patch series "ARM: OMAP1: ams-delta: replace custom I/O with
> GPIO".
> 
> Signed-off-by: Janusz Krzysztofik <jkrzyszt at tis.icnet.pl>
> ---
> v2 -> v3 changes:
> * fix section mismatch isue.
> 
> Changes against initial version:
> * rename consumer setup elements to match their final, modem only
>   related purpose,
> * initialize the regulator pointer and mutex before first use, then
>   omit testing that pointer against NULL value

Thanks, applying all three into ams-delta branch.

Regards,

Tony


From s.hauer at pengutronix.de  Mon Mar  5 14:27:59 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 5 Mar 2012 20:27:59 +0100
Subject: [PATCH v2 01/17] ASoC: imx: move eukrea audmux call into ASoC
 machine driver
In-Reply-To: <20120305174612.GY3224@opensource.wolfsonmicro.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-2-git-send-email-shawn.guo@linaro.org>
 <20120305174612.GY3224@opensource.wolfsonmicro.com>
Message-ID: <20120305192759.GB3852@pengutronix.de>

On Mon, Mar 05, 2012 at 05:46:13PM +0000, Mark Brown wrote:
> On Mon, Mar 05, 2012 at 10:30:49PM +0800, Shawn Guo wrote:
> > It moves eukrea audmux configuration call from board file into ASoC
> > machine driver eukrea-tlv320, so that it gets aligned wm1133-ev1 and
> > mx27vis-aic32x4, and more importantly it will ease the moving of audmux
> > into sound/soc/imx as a platform driver later.
> 
> Sascha, this and the second patch look totally uncontroversial - can we
> just apply them now so we don't need to keep reviewing them?

For patches 01-08 I can give my:

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

The rest I would like to test. Shawn, on what is this series based? It
neither applies on v3.3-rc6 nor on arm-soc/for-next.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From nico at fluxnic.net  Mon Mar  5 14:31:00 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 14:31:00 -0500 (EST)
Subject: [PATCH v3 17/30] ARM: make mach/io.h include optional
In-Reply-To: <1330658022-14559-18-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-18-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203051428220.31242@xanadu.home>

On Thu, 1 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> Add a kconfig option NEED_MACH_IO_H to conditionally include mach/io.h.
> 
> Basing this on CONFIG_PCI and CONFIG_ISA doesn't quite work. Most ISA
> platforms don't need mach/io.h, but ebsa110 does. Most PCI platforms need
> mach/io.h for now, but ks8695 doesn't which means it's broken? omap has a
> lot of other stuff in its io.h, so it also needs io.h until it is cleaned
> up.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>
> ---
>  arch/arm/Kconfig          |   19 +++++++++++++++++++
>  arch/arm/include/asm/io.h |    5 +++++
>  2 files changed, 24 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 92c9c79..ae016cd 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -186,6 +186,9 @@ config GENERIC_ISA_DMA
>  config FIQ
>  	bool
>  
> +config NEED_MACH_IO_H
> +	bool
> +
>  config ARCH_MTD_XIP
>  	bool
>  

I'd locate this next to the NEED_MACH_MEMORY_H definition as they have 
identical purposes.  Other than that:

Acked-by: Nicolas Pitre <nico at linaro.org>

> @@ -265,6 +268,7 @@ config ARCH_INTEGRATOR
>  	select GENERIC_CLOCKEVENTS
>  	select PLAT_VERSATILE
>  	select PLAT_VERSATILE_FPGA_IRQ
> +	select NEED_MACH_IO_H
>  	select NEED_MACH_MEMORY_H
>  	help
>  	  Support for ARM's Integrator platform.
> @@ -400,6 +404,7 @@ config ARCH_EBSA110
>  	select ISA
>  	select NO_IOPORT
>  	select ARCH_USES_GETTIMEOFFSET
> +	select NEED_MACH_IO_H
>  	select NEED_MACH_MEMORY_H
>  	help
>  	  This is an evaluation board for the StrongARM processor available
> @@ -426,6 +431,7 @@ config ARCH_FOOTBRIDGE
>  	select FOOTBRIDGE
>  	select GENERIC_CLOCKEVENTS
>  	select HAVE_IDE
> +	select NEED_MACH_IO_H
>  	select NEED_MACH_MEMORY_H
>  	help
>  	  Support for systems based on the DC21285 companion chip
> @@ -478,6 +484,7 @@ config ARCH_IOP13XX
>  	select PCI
>  	select ARCH_SUPPORTS_MSI
>  	select VMSPLIT_1G
> +	select NEED_MACH_IO_H
>  	select NEED_MACH_MEMORY_H
>  	help
>  	  Support for Intel's IOP13XX (XScale) family of processors.
> @@ -486,6 +493,7 @@ config ARCH_IOP32X
>  	bool "IOP32x-based"
>  	depends on MMU
>  	select CPU_XSCALE
> +	select NEED_MACH_IO_H
>  	select PLAT_IOP
>  	select PCI
>  	select ARCH_REQUIRE_GPIOLIB
> @@ -497,6 +505,7 @@ config ARCH_IOP33X
>  	bool "IOP33x-based"
>  	depends on MMU
>  	select CPU_XSCALE
> +	select NEED_MACH_IO_H
>  	select PLAT_IOP
>  	select PCI
>  	select ARCH_REQUIRE_GPIOLIB
> @@ -509,6 +518,7 @@ config ARCH_IXP23XX
>  	select CPU_XSC3
>   	select PCI
>  	select ARCH_USES_GETTIMEOFFSET
> +	select NEED_MACH_IO_H
>  	select NEED_MACH_MEMORY_H
>  	help
>  	  Support for Intel's IXP23xx (XScale) family of processors.
> @@ -519,6 +529,7 @@ config ARCH_IXP2000
>  	select CPU_XSCALE
>  	select PCI
>  	select ARCH_USES_GETTIMEOFFSET
> +	select NEED_MACH_IO_H
>  	select NEED_MACH_MEMORY_H
>  	help
>  	  Support for Intel's IXP2400/2800 (XScale) family of processors.
> @@ -532,6 +543,7 @@ config ARCH_IXP4XX
>  	select GENERIC_CLOCKEVENTS
>  	select HAVE_SCHED_CLOCK
>  	select MIGHT_HAVE_PCI
> +	select NEED_MACH_IO_H
>  	select DMABOUNCE if PCI
>  	help
>  	  Support for Intel's IXP4XX (XScale) family of processors.
> @@ -542,6 +554,7 @@ config ARCH_DOVE
>  	select PCI
>  	select ARCH_REQUIRE_GPIOLIB
>  	select GENERIC_CLOCKEVENTS
> +	select NEED_MACH_IO_H
>  	select PLAT_ORION
>  	help
>  	  Support for the Marvell Dove SoC 88AP510
> @@ -552,6 +565,7 @@ config ARCH_KIRKWOOD
>  	select PCI
>  	select ARCH_REQUIRE_GPIOLIB
>  	select GENERIC_CLOCKEVENTS
> +	select NEED_MACH_IO_H
>  	select PLAT_ORION
>  	help
>  	  Support for the following Marvell Kirkwood series SoCs:
> @@ -576,6 +590,7 @@ config ARCH_MV78XX0
>  	select PCI
>  	select ARCH_REQUIRE_GPIOLIB
>  	select GENERIC_CLOCKEVENTS
> +	select NEED_MACH_IO_H
>  	select PLAT_ORION
>  	help
>  	  Support for the following Marvell MV78xx0 series SoCs:
> @@ -645,6 +660,7 @@ config ARCH_TEGRA
>  	select HAVE_SCHED_CLOCK
>  	select HAVE_SMP
>  	select MIGHT_HAVE_CACHE_L2X0
> +	select NEED_MACH_IO_H if PCI
>  	select ARCH_HAS_CPUFREQ
>  	help
>  	  This enables support for NVIDIA Tegra based systems (Tegra APX,
> @@ -739,6 +755,7 @@ config ARCH_RPC
>  	select ARCH_SPARSEMEM_ENABLE
>  	select ARCH_USES_GETTIMEOFFSET
>  	select HAVE_IDE
> +	select NEED_MACH_IO_H
>  	select NEED_MACH_MEMORY_H
>  	help
>  	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
> @@ -771,6 +788,7 @@ config ARCH_S3C2410
>  	select CLKDEV_LOOKUP
>  	select ARCH_USES_GETTIMEOFFSET
>  	select HAVE_S3C2410_I2C if I2C
> +	select NEED_MACH_IO_H
>  	help
>  	  Samsung S3C2410X CPU based systems, such as the Simtec Electronics
>  	  BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
> @@ -877,6 +895,7 @@ config ARCH_SHARK
>  	select PCI
>  	select ARCH_USES_GETTIMEOFFSET
>  	select NEED_MACH_MEMORY_H
> +	select NEED_MACH_IO_H
>  	help
>  	  Support for the StrongARM based Digital DNARD machine, also known
>  	  as "Shark" (<http://www.shark-linux.de/shark.html>).
> diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
> index 9bf9d00..cd8c125 100644
> --- a/arch/arm/include/asm/io.h
> +++ b/arch/arm/include/asm/io.h
> @@ -109,7 +109,12 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
>  /*
>   * Now, pick up the machine-defined IO definitions
>   */
> +#ifdef CONFIG_NEED_MACH_IO_H
>  #include <mach/io.h>
> +#else
> +#define __io(a)		({ (void)(a); __typesafe_io(0); })
> +#define __mem_pci(a)	(a)
> +#endif
>  
>  /*
>   * This is the limit of PC card/PCI/ISA IO space, which is by default
> -- 
> 1.7.5.4
> 


From s.hauer at pengutronix.de  Mon Mar  5 14:32:10 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 5 Mar 2012 20:32:10 +0100
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <CAKGA1bn7y8xQn-o=8CZj5nwcvaBvHwxqM0Q2wzFAwJsSgi1sfA@mail.gmail.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
 <20120305174232.GA3852@pengutronix.de>
 <CAKGA1bn7y8xQn-o=8CZj5nwcvaBvHwxqM0Q2wzFAwJsSgi1sfA@mail.gmail.com>
Message-ID: <20120305193210.GC3852@pengutronix.de>

On Mon, Mar 05, 2012 at 12:09:13PM -0600, Matt Sealey wrote:
> There is in the BSP but the BSP driver is trying to be way too fancy
> with I2S settings on the imx-ssi driver you wrote (it works well for
> AC97, but for SSI in I2S slave mode there are so many hacks upon hacks
> "they" have presented, it'd never mainline)
> 
> Having the codec provide clocks in slave mode works great in fsl-ssi
> because it doesn't set the chip up any other way, but I've had serious
> problems here whereby playing back a 48khz, 16-bit audio stream and
> recording in ANYTHING else seems to make the playback stream slow
> motion, but I can't trace whether it's the SSI config (seems unlikely
> as the only valid STXCCR bit in slave mode is the word length) or the
> codec config. In theory the playback and capture should be serialized
> by the driver, though, right? It wouldn't be possible to be a slave to
> the codec if it had to run the clock two different rates at the same
> time.. app1 sends a sample buffer, codec does dma, app2 requests
> capture buffer, codec does dma, they can't happen at the same time,
> maybe we are missing an important mutex or spinlock here that would
> enforce this and stop the configuration changing mid-stream.. I'm far
> from the ALSA expert though)
> 
> If adding capture support means having to make the SSI driver work in
> I2S master mode and do the laborious work of actually dividing the SSI
> clock, configuring the external PLL etc. so it can clock the codec
> appropriately for this mode then that's what will have to be done, and
> I agree with Sascha, whatever the solution it should be something that
> gets done now (not least because I kind of want audio here.. :) along
> with quite possibly adapting the current imx-ssi driver (as opposed to
> the fsl-ssi driver) to be fsl-ssi-ac97 vs fsl-ssi-imx so we have
> dedicated operation (which will make the AC97/FIQ select much easier
> to determine).

master mode shouldn't be necessary to get the sgtl5000 work with both
recording and playback. I have seen it working on the babbage board in
slave mode on some internal branch. I never got the sgtl5000 mainline
driver to work though.

> 
> While we're at it; did anyone patch arch/arm/mach-imx/ssi-fiq.S to be
> compiled in .arm mode yet? I can't find it in a tree or the list but I
> could be wrong. I am sure we mutually agreed (or at least Russell
> decided) on this to get thumb kernels to build again since none of the
> dependent processors/config selections are M-profile?

I think we agreed on compiliing this in arm mode but nobody has sent a
patch yet.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From nico at fluxnic.net  Mon Mar  5 14:33:50 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 14:33:50 -0500 (EST)
Subject: [PATCH v3 18/30] ARM: remove bunch of now unused mach/io.h files
In-Reply-To: <1330658022-14559-19-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-19-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203051433000.31242@xanadu.home>

On Thu, 1 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> Now that many platforms don't need mach/io.h, remove the usused ones.

unused*

> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Acked-by: Shawn Guo <shawn.guo at linaro.org>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Acked-by: Jamie Iles <jamie at jamieiles.com>
> Acked-by: Pawel Moll <pawel.moll at arm.com>

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/mach-at91/include/mach/io.h      |   31 ------------------
>  arch/arm/mach-bcmring/include/mach/io.h   |   33 -------------------
>  arch/arm/mach-clps711x/include/mach/io.h  |   36 ---------------------
>  arch/arm/mach-cns3xxx/include/mach/io.h   |   17 ----------
>  arch/arm/mach-davinci/include/mach/io.h   |   24 --------------
>  arch/arm/mach-ep93xx/include/mach/io.h    |   13 --------
>  arch/arm/mach-exynos/include/mach/io.h    |   26 ---------------
>  arch/arm/mach-gemini/include/mach/io.h    |   18 ----------
>  arch/arm/mach-h720x/include/mach/io.h     |   22 -------------
>  arch/arm/mach-highbank/include/mach/io.h  |    7 ----
>  arch/arm/mach-ks8695/include/mach/io.h    |   19 -----------
>  arch/arm/mach-lpc32xx/include/mach/io.h   |   27 ----------------
>  arch/arm/mach-mmp/include/mach/io.h       |   21 ------------
>  arch/arm/mach-msm/include/mach/io.h       |   24 --------------
>  arch/arm/mach-mxs/include/mach/io.h       |   22 -------------
>  arch/arm/mach-netx/include/mach/io.h      |   28 ----------------
>  arch/arm/mach-nomadik/include/mach/io.h   |   22 -------------
>  arch/arm/mach-omap1/include/mach/io.h     |   46 ---------------------------
>  arch/arm/mach-omap2/include/mach/io.h     |   49 -----------------------------
>  arch/arm/mach-orion5x/include/mach/io.h   |   21 ------------
>  arch/arm/mach-picoxcell/include/mach/io.h |   22 -------------
>  arch/arm/mach-pnx4008/include/mach/io.h   |   21 ------------
>  arch/arm/mach-prima2/include/mach/io.h    |   16 ---------
>  arch/arm/mach-pxa/include/mach/io.h       |   20 ------------
>  arch/arm/mach-realview/include/mach/io.h  |   28 ----------------
>  arch/arm/mach-s3c64xx/include/mach/io.h   |   18 ----------
>  arch/arm/mach-s5p64x0/include/mach/io.h   |   25 ---------------
>  arch/arm/mach-s5pc100/include/mach/io.h   |   18 ----------
>  arch/arm/mach-s5pv210/include/mach/io.h   |   26 ---------------
>  arch/arm/mach-sa1100/include/mach/io.h    |   20 ------------
>  arch/arm/mach-shmobile/include/mach/io.h  |    9 -----
>  arch/arm/mach-spear3xx/include/mach/io.h  |   19 -----------
>  arch/arm/mach-spear6xx/include/mach/io.h  |   20 ------------
>  arch/arm/mach-u300/include/mach/io.h      |   20 ------------
>  arch/arm/mach-ux500/include/mach/io.h     |   22 -------------
>  arch/arm/mach-versatile/include/mach/io.h |   28 ----------------
>  arch/arm/mach-vexpress/include/mach/io.h  |   26 ---------------
>  arch/arm/mach-vt8500/include/mach/io.h    |   26 ---------------
>  arch/arm/mach-w90x900/include/mach/io.h   |   30 -----------------
>  arch/arm/mach-zynq/include/mach/io.h      |   33 -------------------
>  arch/arm/plat-mxc/include/mach/io.h       |   22 -------------
>  arch/arm/plat-spear/include/plat/io.h     |   22 -------------
>  42 files changed, 0 insertions(+), 997 deletions(-)
>  delete mode 100644 arch/arm/mach-at91/include/mach/io.h
>  delete mode 100644 arch/arm/mach-bcmring/include/mach/io.h
>  delete mode 100644 arch/arm/mach-clps711x/include/mach/io.h
>  delete mode 100644 arch/arm/mach-cns3xxx/include/mach/io.h
>  delete mode 100644 arch/arm/mach-davinci/include/mach/io.h
>  delete mode 100644 arch/arm/mach-ep93xx/include/mach/io.h
>  delete mode 100644 arch/arm/mach-exynos/include/mach/io.h
>  delete mode 100644 arch/arm/mach-gemini/include/mach/io.h
>  delete mode 100644 arch/arm/mach-h720x/include/mach/io.h
>  delete mode 100644 arch/arm/mach-highbank/include/mach/io.h
>  delete mode 100644 arch/arm/mach-ks8695/include/mach/io.h
>  delete mode 100644 arch/arm/mach-lpc32xx/include/mach/io.h
>  delete mode 100644 arch/arm/mach-mmp/include/mach/io.h
>  delete mode 100644 arch/arm/mach-msm/include/mach/io.h
>  delete mode 100644 arch/arm/mach-mxs/include/mach/io.h
>  delete mode 100644 arch/arm/mach-netx/include/mach/io.h
>  delete mode 100644 arch/arm/mach-nomadik/include/mach/io.h
>  delete mode 100644 arch/arm/mach-omap1/include/mach/io.h
>  delete mode 100644 arch/arm/mach-omap2/include/mach/io.h
>  delete mode 100644 arch/arm/mach-orion5x/include/mach/io.h
>  delete mode 100644 arch/arm/mach-picoxcell/include/mach/io.h
>  delete mode 100644 arch/arm/mach-pnx4008/include/mach/io.h
>  delete mode 100644 arch/arm/mach-prima2/include/mach/io.h
>  delete mode 100644 arch/arm/mach-pxa/include/mach/io.h
>  delete mode 100644 arch/arm/mach-realview/include/mach/io.h
>  delete mode 100644 arch/arm/mach-s3c64xx/include/mach/io.h
>  delete mode 100644 arch/arm/mach-s5p64x0/include/mach/io.h
>  delete mode 100644 arch/arm/mach-s5pc100/include/mach/io.h
>  delete mode 100644 arch/arm/mach-s5pv210/include/mach/io.h
>  delete mode 100644 arch/arm/mach-sa1100/include/mach/io.h
>  delete mode 100644 arch/arm/mach-shmobile/include/mach/io.h
>  delete mode 100644 arch/arm/mach-spear3xx/include/mach/io.h
>  delete mode 100644 arch/arm/mach-spear6xx/include/mach/io.h
>  delete mode 100644 arch/arm/mach-u300/include/mach/io.h
>  delete mode 100644 arch/arm/mach-ux500/include/mach/io.h
>  delete mode 100644 arch/arm/mach-versatile/include/mach/io.h
>  delete mode 100644 arch/arm/mach-vexpress/include/mach/io.h
>  delete mode 100644 arch/arm/mach-vt8500/include/mach/io.h
>  delete mode 100644 arch/arm/mach-w90x900/include/mach/io.h
>  delete mode 100644 arch/arm/mach-zynq/include/mach/io.h
>  delete mode 100644 arch/arm/plat-mxc/include/mach/io.h
>  delete mode 100644 arch/arm/plat-spear/include/plat/io.h
> 
> diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
> deleted file mode 100644
> index 4003001..0000000
> --- a/arch/arm/mach-at91/include/mach/io.h
> +++ /dev/null
> @@ -1,31 +0,0 @@
> -/*
> - * arch/arm/mach-at91/include/mach/io.h
> - *
> - *  Copyright (C) 2003 SAN People
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> - */
> -
> -#ifndef __ASM_ARCH_IO_H
> -#define __ASM_ARCH_IO_H
> -
> -#include <mach/hardware.h>
> -
> -#define IO_SPACE_LIMIT		0xFFFFFFFF
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-bcmring/include/mach/io.h b/arch/arm/mach-bcmring/include/mach/io.h
> deleted file mode 100644
> index dae5e9b..0000000
> --- a/arch/arm/mach-bcmring/include/mach/io.h
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -/*
> - *
> - *  Copyright (C) 1999 ARM Limited
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#include <mach/hardware.h>
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -/*
> - * We don't actually have real ISA nor PCI buses, but there is so many
> - * drivers out there that might just work if we fake them...
> - */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-clps711x/include/mach/io.h b/arch/arm/mach-clps711x/include/mach/io.h
> deleted file mode 100644
> index 2e0b3ce..0000000
> --- a/arch/arm/mach-clps711x/include/mach/io.h
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -/*
> - *  arch/arm/mach-clps711x/include/mach/io.h
> - *
> - *  Copyright (C) 1999 ARM Limited
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -/*
> - * We don't support ins[lb]/outs[lb].  Make them fault.
> - */
> -#define __raw_readsb(p,d,l)	do { *(int *)0 = 0; } while (0)
> -#define __raw_readsl(p,d,l)	do { *(int *)0 = 0; } while (0)
> -#define __raw_writesb(p,d,l)	do { *(int *)0 = 0; } while (0)
> -#define __raw_writesl(p,d,l)	do { *(int *)0 = 0; } while (0)
> -
> -#endif
> diff --git a/arch/arm/mach-cns3xxx/include/mach/io.h b/arch/arm/mach-cns3xxx/include/mach/io.h
> deleted file mode 100644
> index 33b6fc1..0000000
> --- a/arch/arm/mach-cns3xxx/include/mach/io.h
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -/*
> - * Copyright 2008 Cavium Networks
> - * Copyright 2003 ARM Limited
> - *
> - * This file is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License, Version 2, as
> - * published by the Free Software Foundation.
> - */
> -#ifndef __MACH_IO_H
> -#define __MACH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -#define __io(a)			__typesafe_io(a)
> -#define __mem_pci(a)		(a)
> -
> -#endif
> diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
> deleted file mode 100644
> index b2267d1..0000000
> --- a/arch/arm/mach-davinci/include/mach/io.h
> +++ /dev/null
> @@ -1,24 +0,0 @@
> -/*
> - * DaVinci IO address definitions
> - *
> - * Copied from include/asm/arm/arch-omap/io.h
> - *
> - * 2007 (c) MontaVista Software, Inc. This file is licensed under
> - * the terms of the GNU General Public License version 2. This program
> - * is licensed "as is" without any warranty of any kind, whether express
> - * or implied.
> - */
> -#ifndef __ASM_ARCH_IO_H
> -#define __ASM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -/*
> - * We don't actually have real ISA nor PCI buses, but there is so many
> - * drivers out there that might just work if we fake them...
> - */
> -#define __io(a)			__typesafe_io(a)
> -#define __mem_pci(a)		(a)
> -#define __mem_isa(a)		(a)
> -
> -#endif /* __ASM_ARCH_IO_H */
> diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
> deleted file mode 100644
> index 17e76ef..0000000
> --- a/arch/arm/mach-ep93xx/include/mach/io.h
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/*
> - * arch/arm/mach-ep93xx/include/mach/io.h
> - */
> -
> -#ifndef __ASM_MACH_IO_H
> -#define __ASM_MACH_IO_H
> -
> -#define IO_SPACE_LIMIT		0xffffffff
> -
> -#define __io(p)			__typesafe_io(p)
> -#define __mem_pci(p)		(p)
> -
> -#endif /* __ASM_MACH_IO_H */
> diff --git a/arch/arm/mach-exynos/include/mach/io.h b/arch/arm/mach-exynos/include/mach/io.h
> deleted file mode 100644
> index d5478d2..0000000
> --- a/arch/arm/mach-exynos/include/mach/io.h
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -/* linux/arch/arm/mach-exynos4/include/mach/io.h
> - *
> - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> - *		http://www.samsung.com
> - *
> - * Copyright 2008-2010 Ben Dooks <ben-linux at fluff.org>
> - *
> - * Based on arch/arm/mach-s5p6442/include/mach/io.h
> - *
> - * Default IO routines for EXYNOS4
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> -*/
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H __FILE__
> -
> -/* No current ISA/PCI bus support. */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#define IO_SPACE_LIMIT (0xFFFFFFFF)
> -
> -#endif /* __ASM_ARM_ARCH_IO_H */
> diff --git a/arch/arm/mach-gemini/include/mach/io.h b/arch/arm/mach-gemini/include/mach/io.h
> deleted file mode 100644
> index c548056..0000000
> --- a/arch/arm/mach-gemini/include/mach/io.h
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -/*
> - *  Copyright (C) 2001-2006 Storlink, Corp.
> - *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas at teltonika.lt>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - */
> -#ifndef __MACH_IO_H
> -#define __MACH_IO_H
> -
> -#define IO_SPACE_LIMIT	0xffffffff
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif /* __MACH_IO_H */
> diff --git a/arch/arm/mach-h720x/include/mach/io.h b/arch/arm/mach-h720x/include/mach/io.h
> deleted file mode 100644
> index 2c8659c..0000000
> --- a/arch/arm/mach-h720x/include/mach/io.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/*
> - * arch/arm/mach-h720x/include/mach/io.h
> - *
> - * Copyright (C) 2000 Steve Hill (sjhill at cotw.com)
> - *
> - * Changelog:
> - *
> - *  09-19-2001	JJKIM
> - *  		Created from arch/arm/mach-l7200/include/mach/io.h
> - *
> - *  03-27-2003  Robert Schwebel <r.schwebel at pengutronix.de>:
> - *  		re-unified header files for h720x
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-highbank/include/mach/io.h b/arch/arm/mach-highbank/include/mach/io.h
> deleted file mode 100644
> index 70cfa3b..0000000
> --- a/arch/arm/mach-highbank/include/mach/io.h
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -#ifndef __MACH_IO_H
> -#define __MACH_IO_H
> -
> -#define __io(a)		({ (void)(a); __typesafe_io(0); })
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-ks8695/include/mach/io.h b/arch/arm/mach-ks8695/include/mach/io.h
> deleted file mode 100644
> index a7a63ac..0000000
> --- a/arch/arm/mach-ks8695/include/mach/io.h
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -/*
> - * arch/arm/mach-ks8695/include/mach/io.h
> - *
> - * Copyright (C) 2006 Andrew Victor
> - *
> - * This file is licensed under  the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef __ASM_ARCH_IO_H
> -#define __ASM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT		0xffffffff
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-lpc32xx/include/mach/io.h b/arch/arm/mach-lpc32xx/include/mach/io.h
> deleted file mode 100644
> index 9b59ab5..0000000
> --- a/arch/arm/mach-lpc32xx/include/mach/io.h
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -/*
> - * arch/arm/mach-lpc32xx/include/mach/io.h
> - *
> - * Author: Kevin Wells <kevin.wells at nxp.com>
> - *
> - * Copyright (C) 2010 NXP Semiconductors
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - */
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT	0xffffffff
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h
> deleted file mode 100644
> index e7adf3d..0000000
> --- a/arch/arm/mach-mmp/include/mach/io.h
> +++ /dev/null
> @@ -1,21 +0,0 @@
> -/*
> - * linux/arch/arm/mach-mmp/include/mach/io.h
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#ifndef __ASM_MACH_IO_H
> -#define __ASM_MACH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -/*
> - * We don't actually have real ISA nor PCI buses, but there is so many
> - * drivers out there that might just work if we fake them...
> - */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif /* __ASM_MACH_IO_H */
> diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
> deleted file mode 100644
> index 1071f98..0000000
> --- a/arch/arm/mach-msm/include/mach/io.h
> +++ /dev/null
> @@ -1,24 +0,0 @@
> -/* arch/arm/mach-msm/include/mach/io.h
> - *
> - * Copyright (C) 2007 Google, Inc.
> - *
> - * This software is licensed under the terms of the GNU General Public
> - * License version 2, as published by the Free Software Foundation, and
> - * may be copied, distributed, and modified under those terms.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - */
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)    (a)
> -
> -#endif
> diff --git a/arch/arm/mach-mxs/include/mach/io.h b/arch/arm/mach-mxs/include/mach/io.h
> deleted file mode 100644
> index 289b722..0000000
> --- a/arch/arm/mach-mxs/include/mach/io.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/*
> - *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
> - */
> -
> -/*
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#ifndef __MACH_MXS_IO_H__
> -#define __MACH_MXS_IO_H__
> -
> -/* Allow IO space to be anywhere in the memory */
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -/* io address mapping macro */
> -#define __io(a)		__typesafe_io(a)
> -
> -#define __mem_pci(a)	(a)
> -
> -#endif /* __MACH_MXS_IO_H__ */
> diff --git a/arch/arm/mach-netx/include/mach/io.h b/arch/arm/mach-netx/include/mach/io.h
> deleted file mode 100644
> index c3921cb..0000000
> --- a/arch/arm/mach-netx/include/mach/io.h
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -/*
> - *  arch/arm/mach-netx/include/mach/io.h
> - *
> - * Copyright (C) 2005 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2
> - * as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> - */
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)            (a)
> -
> -#endif
> diff --git a/arch/arm/mach-nomadik/include/mach/io.h b/arch/arm/mach-nomadik/include/mach/io.h
> deleted file mode 100644
> index 2e1eca1..0000000
> --- a/arch/arm/mach-nomadik/include/mach/io.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/*
> - * arch/arm/mach-nomadik/include/mach/io.h   (copied from mach-sa1100)
> - *
> - * Copyright (C) 1997-1999 Russell King
> - *
> - * Modifications:
> - *  06-12-1997  RMK     Created.
> - *  07-04-1999  RMK     Major cleanup
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -/*
> - * We don't actually have real ISA nor PCI buses, but there is so many
> - * drivers out there that might just work if we fake them...
> - */
> -#define __io(a)         __typesafe_io(a)
> -#define __mem_pci(a)    (a)
> -
> -#endif
> diff --git a/arch/arm/mach-omap1/include/mach/io.h b/arch/arm/mach-omap1/include/mach/io.h
> deleted file mode 100644
> index 37b12e1..0000000
> --- a/arch/arm/mach-omap1/include/mach/io.h
> +++ /dev/null
> @@ -1,46 +0,0 @@
> -/*
> - * arch/arm/mach-omap1/include/mach/io.h
> - *
> - * IO definitions for TI OMAP processors and boards
> - *
> - * Copied from arch/arm/mach-sa1100/include/mach/io.h
> - * Copyright (C) 1997-1999 Russell King
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms of the GNU General Public License as published by the
> - * Free Software Foundation; either version 2 of the License, or (at your
> - * option) any later version.
> - *
> - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
> - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
> - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
> - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
> - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
> - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
> - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> - *
> - * You should have received a copy of the GNU General Public License along
> - * with this program; if not, write to the Free Software Foundation, Inc.,
> - * 675 Mass Ave, Cambridge, MA 02139, USA.
> - *
> - * Modifications:
> - *  06-12-1997	RMK	Created.
> - *  07-04-1999	RMK	Major cleanup
> - */
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -/*
> - * We don't actually have real ISA nor PCI buses, but there is so many
> - * drivers out there that might just work if we fake them...
> - */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-omap2/include/mach/io.h b/arch/arm/mach-omap2/include/mach/io.h
> deleted file mode 100644
> index b8758c8..0000000
> --- a/arch/arm/mach-omap2/include/mach/io.h
> +++ /dev/null
> @@ -1,49 +0,0 @@
> -/*
> - * arch/arm/mach-omap2/include/mach/io.h
> - *
> - * IO definitions for TI OMAP processors and boards
> - *
> - * Copied from arch/arm/mach-sa1100/include/mach/io.h
> - * Copyright (C) 1997-1999 Russell King
> - *
> - * Copyright (C) 2009 Texas Instruments
> - * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar at ti.com>
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms of the GNU General Public License as published by the
> - * Free Software Foundation; either version 2 of the License, or (at your
> - * option) any later version.
> - *
> - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
> - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
> - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
> - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
> - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
> - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
> - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
> - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
> - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> - *
> - * You should have received a copy of the GNU General Public License along
> - * with this program; if not, write to the Free Software Foundation, Inc.,
> - * 675 Mass Ave, Cambridge, MA 02139, USA.
> - *
> - * Modifications:
> - *  06-12-1997	RMK	Created.
> - *  07-04-1999	RMK	Major cleanup
> - */
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -/*
> - * We don't actually have real ISA nor PCI buses, but there is so many
> - * drivers out there that might just work if we fake them...
> - */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
> deleted file mode 100644
> index 444136d..0000000
> --- a/arch/arm/mach-orion5x/include/mach/io.h
> +++ /dev/null
> @@ -1,21 +0,0 @@
> -/*
> - * arch/arm/mach-orion5x/include/mach/io.h
> - *
> - * Tzachi Perelstein <tzachi at marvell.com>
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2.  This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef __ASM_ARCH_IO_H
> -#define __ASM_ARCH_IO_H
> -
> -#include "orion5x.h"
> -
> -#define IO_SPACE_LIMIT		0xffffffff
> -
> -#define __io(a)			__typesafe_io(a)
> -#define __mem_pci(a)		(a)
> -
> -#endif
> diff --git a/arch/arm/mach-picoxcell/include/mach/io.h b/arch/arm/mach-picoxcell/include/mach/io.h
> deleted file mode 100644
> index 7573ec7..0000000
> --- a/arch/arm/mach-picoxcell/include/mach/io.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/*
> - * Copyright (c) 2011 Picochip Ltd., Jamie Iles
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -/* No ioports, but needed for driver compatibility. */
> -#define __io(a)			__typesafe_io(a)
> -/* No PCI possible on picoxcell. */
> -#define __mem_pci(a)		(a)
> -
> -#endif /* __ASM_ARM_ARCH_IO_H */
> diff --git a/arch/arm/mach-pnx4008/include/mach/io.h b/arch/arm/mach-pnx4008/include/mach/io.h
> deleted file mode 100644
> index cbf0904..0000000
> --- a/arch/arm/mach-pnx4008/include/mach/io.h
> +++ /dev/null
> @@ -1,21 +0,0 @@
> -
> -/*
> - *  arch/arm/mach-pnx4008/include/mach/io.h
> - *
> - * Author: Dmitry Chigirev <chigirev at ru.mvista.com>
> - *
> - * 2005 (c) MontaVista Software, Inc. This file is licensed under
> - * the terms of the GNU General Public License version 2. This program
> - * is licensed "as is" without any warranty of any kind, whether express
> - * or implied.
> - */
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-prima2/include/mach/io.h b/arch/arm/mach-prima2/include/mach/io.h
> deleted file mode 100644
> index 6c31e9e..0000000
> --- a/arch/arm/mach-prima2/include/mach/io.h
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -/*
> - * arch/arm/mach-prima2/include/mach/io.h
> - *
> - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
> - *
> - * Licensed under GPLv2 or later.
> - */
> -
> -#ifndef __MACH_PRIMA2_IO_H
> -#define __MACH_PRIMA2_IO_H
> -
> -#define IO_SPACE_LIMIT ((resource_size_t)0)
> -
> -#define __mem_pci(a)            (a)
> -
> -#endif
> diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
> deleted file mode 100644
> index fdca3be..0000000
> --- a/arch/arm/mach-pxa/include/mach/io.h
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -/*
> - * arch/arm/mach-pxa/include/mach/io.h
> - *
> - * Copied from asm/arch/sa1100/io.h
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#include <mach/hardware.h>
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -/*
> - * We don't actually have real ISA nor PCI buses, but there is so many
> - * drivers out there that might just work if we fake them...
> - */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-realview/include/mach/io.h b/arch/arm/mach-realview/include/mach/io.h
> deleted file mode 100644
> index f05bcdf..0000000
> --- a/arch/arm/mach-realview/include/mach/io.h
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -/*
> - *  arch/arm/mach-realview/include/mach/io.h
> - *
> - *  Copyright (C) 2003 ARM Limited
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-s3c64xx/include/mach/io.h b/arch/arm/mach-s3c64xx/include/mach/io.h
> deleted file mode 100644
> index de5716d..0000000
> --- a/arch/arm/mach-s3c64xx/include/mach/io.h
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -/* arch/arm/mach-s3c64xxinclude/mach/io.h
> - *
> - * Copyright 2008 Simtec Electronics
> - *	Ben Dooks <ben-linux at fluff.org>
> - *
> - * Default IO routines for S3C64XX based
> - */
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -/* No current ISA/PCI bus support. */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#define IO_SPACE_LIMIT (0xFFFFFFFF)
> -
> -#endif
> diff --git a/arch/arm/mach-s5p64x0/include/mach/io.h b/arch/arm/mach-s5p64x0/include/mach/io.h
> deleted file mode 100644
> index a3e095c..0000000
> --- a/arch/arm/mach-s5p64x0/include/mach/io.h
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -/* linux/arch/arm/mach-s5p64x0/include/mach/io.h
> - *
> - * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> - *		http://www.samsung.com
> - *
> - * Copyright 2008 Simtec Electronics
> - *	Ben Dooks <ben-linux at fluff.org>
> - *
> - * Default IO routines for S5P64X0 based
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> -*/
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -/* No current ISA/PCI bus support. */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#define IO_SPACE_LIMIT (0xFFFFFFFF)
> -
> -#endif
> diff --git a/arch/arm/mach-s5pc100/include/mach/io.h b/arch/arm/mach-s5pc100/include/mach/io.h
> deleted file mode 100644
> index 819acf5..0000000
> --- a/arch/arm/mach-s5pc100/include/mach/io.h
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -/* arch/arm/mach-s5pc100/include/mach/io.h
> - *
> - * Copyright 2008 Simtec Electronics
> - *	Ben Dooks <ben-linux at fluff.org>
> - *
> - * Default IO routines for S5PC100 systems
> - */
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -/* No current ISA/PCI bus support. */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#define IO_SPACE_LIMIT (0xFFFFFFFF)
> -
> -#endif
> diff --git a/arch/arm/mach-s5pv210/include/mach/io.h b/arch/arm/mach-s5pv210/include/mach/io.h
> deleted file mode 100644
> index 5ab9d56..0000000
> --- a/arch/arm/mach-s5pv210/include/mach/io.h
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -/* linux/arch/arm/mach-s5pv210/include/mach/io.h
> - *
> - * Copyright 2008-2010 Ben Dooks <ben-linux at fluff.org>
> - *
> - * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> - *		http://www.samsung.com/
> - *
> - * Based on arch/arm/mach-s5p6442/include/mach/io.h
> - *
> - * Default IO routines for S5PV210
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> -*/
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H __FILE__
> -
> -/* No current ISA/PCI bus support. */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#define IO_SPACE_LIMIT (0xFFFFFFFF)
> -
> -#endif /* __ASM_ARM_ARCH_IO_H */
> diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h
> deleted file mode 100644
> index dfc27ff..0000000
> --- a/arch/arm/mach-sa1100/include/mach/io.h
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -/*
> - * arch/arm/mach-sa1100/include/mach/io.h
> - *
> - * Copyright (C) 1997-1999 Russell King
> - *
> - * Modifications:
> - *  06-12-1997	RMK	Created.
> - *  07-04-1999	RMK	Major cleanup
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -/*
> - * __io() is required to be an equivalent mapping to __mem_pci() for
> - * SOC_COMMON to work.
> - */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-shmobile/include/mach/io.h b/arch/arm/mach-shmobile/include/mach/io.h
> deleted file mode 100644
> index 7339fe4..0000000
> --- a/arch/arm/mach-shmobile/include/mach/io.h
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -#ifndef __ASM_MACH_IO_H
> -#define __ASM_MACH_IO_H
> -
> -#define IO_SPACE_LIMIT		0xffffffff
> -
> -#define __io(a)			((void __iomem *)(a))
> -#define __mem_pci(a)		(a)
> -
> -#endif /* __ASM_MACH_IO_H */
> diff --git a/arch/arm/mach-spear3xx/include/mach/io.h b/arch/arm/mach-spear3xx/include/mach/io.h
> deleted file mode 100644
> index 30cff8a..0000000
> --- a/arch/arm/mach-spear3xx/include/mach/io.h
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -/*
> - * arch/arm/mach-spear3xx/include/mach/io.h
> - *
> - * IO definitions for SPEAr3xx machine family
> - *
> - * Copyright (C) 2009 ST Microelectronics
> - * Viresh Kumar<viresh.kumar at st.com>
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef __MACH_IO_H
> -#define __MACH_IO_H
> -
> -#include <plat/io.h>
> -
> -#endif /* __MACH_IO_H */
> diff --git a/arch/arm/mach-spear6xx/include/mach/io.h b/arch/arm/mach-spear6xx/include/mach/io.h
> deleted file mode 100644
> index fb7c106..0000000
> --- a/arch/arm/mach-spear6xx/include/mach/io.h
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -/*
> - * arch/arm/mach-spear6xx/include/mach/io.h
> - *
> - * IO definitions for SPEAr6xx machine family
> - *
> - * Copyright (C) 2009 ST Microelectronics
> - * Rajeev Kumar Kumar<rajeev-dlh.kumar at st.com>
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef __MACH_IO_H
> -#define __MACH_IO_H
> -
> -#include <plat/io.h>
> -
> -#endif	/* __MACH_IO_H */
> -
> diff --git a/arch/arm/mach-u300/include/mach/io.h b/arch/arm/mach-u300/include/mach/io.h
> deleted file mode 100644
> index 5d6b4c1..0000000
> --- a/arch/arm/mach-u300/include/mach/io.h
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -/*
> - *
> - * arch/arm/mach-u300/include/mach/io.h
> - *
> - *
> - * Copyright (C) 2006-2009 ST-Ericsson AB
> - * License terms: GNU General Public License (GPL) version 2
> - * Dummy IO map for being able to use writew()/readw(),
> - * writel()/readw() and similar accessor functions.
> - * Author: Linus Walleij <linus.walleij at stericsson.com>
> - */
> -#ifndef __MACH_IO_H
> -#define __MACH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
> deleted file mode 100644
> index 1cf3f44..0000000
> --- a/arch/arm/mach-ux500/include/mach/io.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/*
> - * arch/arm/mach-u8500/include/mach/io.h
> - *
> - * Copyright (C) 1997-1999 Russell King
> - *
> - * Modifications:
> - *  06-12-1997	RMK	Created.
> - *  07-04-1999	RMK	Major cleanup
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -/*
> - * We don't actually have real ISA nor PCI buses, but there is so many
> - * drivers out there that might just work if we fake them...
> - */
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
> deleted file mode 100644
> index f067c14..0000000
> --- a/arch/arm/mach-versatile/include/mach/io.h
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -/*
> - *  arch/arm/mach-versatile/include/mach/io.h
> - *
> - *  Copyright (C) 2003 ARM Limited
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-vexpress/include/mach/io.h b/arch/arm/mach-vexpress/include/mach/io.h
> deleted file mode 100644
> index 13522d8..0000000
> --- a/arch/arm/mach-vexpress/include/mach/io.h
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -/*
> - *  arch/arm/mach-vexpress/include/mach/io.h
> - *
> - *  Copyright (C) 2003 ARM Limited
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define __io(a)		__typesafe_io(a)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-vt8500/include/mach/io.h b/arch/arm/mach-vt8500/include/mach/io.h
> deleted file mode 100644
> index 46181ee..0000000
> --- a/arch/arm/mach-vt8500/include/mach/io.h
> +++ /dev/null
> @@ -1,26 +0,0 @@
> -/*
> - *  arch/arm/mach-vt8500/include/mach/io.h
> - *
> - *  Copyright (C) 2010 Alexey Charkov
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> - */
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define __io(a)		__typesafe_io((a) + 0xf0000000)
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/mach-w90x900/include/mach/io.h b/arch/arm/mach-w90x900/include/mach/io.h
> deleted file mode 100644
> index d96ab99..0000000
> --- a/arch/arm/mach-w90x900/include/mach/io.h
> +++ /dev/null
> @@ -1,30 +0,0 @@
> -/*
> - * arch/arm/mach-w90x900/include/mach/io.h
> - *
> - * Copyright (c) 2008 Nuvoton technology corporation
> - * All rights reserved.
> - *
> - * Wan ZongShun <mcuos.com at gmail.com>
> - *
> - * Based on arch/arm/mach-s3c2410/include/mach/io.h
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - */
> -
> -#ifndef __ASM_ARM_ARCH_IO_H
> -#define __ASM_ARM_ARCH_IO_H
> -
> -#define IO_SPACE_LIMIT	0xffffffff
> -
> -/*
> - * 1:1 mapping for ioremapped regions.
> - */
> -
> -#define __mem_pci(a)	(a)
> -#define __io(a)		__typesafe_io(a)
> -
> -#endif
> diff --git a/arch/arm/mach-zynq/include/mach/io.h b/arch/arm/mach-zynq/include/mach/io.h
> deleted file mode 100644
> index 39d9885..0000000
> --- a/arch/arm/mach-zynq/include/mach/io.h
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -/* arch/arm/mach-zynq/include/mach/io.h
> - *
> - *  Copyright (C) 2011 Xilinx
> - *
> - * This software is licensed under the terms of the GNU General Public
> - * License version 2, as published by the Free Software Foundation, and
> - * may be copied, distributed, and modified under those terms.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - */
> -
> -#ifndef __MACH_IO_H__
> -#define __MACH_IO_H__
> -
> -/* Allow IO space to be anywhere in the memory */
> -
> -#define IO_SPACE_LIMIT 0xffff
> -
> -/* IO address mapping macros, nothing special at this time but required */
> -
> -#ifdef __ASSEMBLER__
> -#define IOMEM(x)		(x)
> -#else
> -#define IOMEM(x)		((void __force __iomem *)(x))
> -#endif
> -
> -#define __io(a)			__typesafe_io(a)
> -#define __mem_pci(a)		(a)
> -
> -#endif
> diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
> deleted file mode 100644
> index ea9d95e..0000000
> --- a/arch/arm/plat-mxc/include/mach/io.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/*
> - *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
> - */
> -
> -/*
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#ifndef __ASM_ARCH_MXC_IO_H__
> -#define __ASM_ARCH_MXC_IO_H__
> -
> -/* Allow IO space to be anywhere in the memory */
> -#define IO_SPACE_LIMIT 0xffffffff
> -
> -/* io address mapping macro */
> -#define __io(a)		__typesafe_io(a)
> -
> -#define __mem_pci(a)	(a)
> -
> -#endif
> diff --git a/arch/arm/plat-spear/include/plat/io.h b/arch/arm/plat-spear/include/plat/io.h
> deleted file mode 100644
> index 4d4ba82..0000000
> --- a/arch/arm/plat-spear/include/plat/io.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/*
> - * arch/arm/plat-spear/include/plat/io.h
> - *
> - * IO definitions for SPEAr platform
> - *
> - * Copyright (C) 2009 ST Microelectronics
> - * Viresh Kumar<viresh.kumar at st.com>
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef __PLAT_IO_H
> -#define __PLAT_IO_H
> -
> -#define IO_SPACE_LIMIT		0xFFFFFFFF
> -
> -#define __io(a)			__typesafe_io(a)
> -#define __mem_pci(a)		(a)
> -
> -#endif /* __PLAT_IO_H */
> -- 
> 1.7.5.4
> 


From tony at atomide.com  Mon Mar  5 14:36:35 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 11:36:35 -0800
Subject: [PATCH v2] ARM: OMAP: dmtimer: fix missing content/correction
 in low-power mode support
In-Reply-To: <1323237434-4919-1-git-send-email-tarun.kanti@ti.com>
References: <1323237434-4919-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <20120305193635.GM12083@atomide.com>

* Tarun Kanti DebBarma <tarun.kanti at ti.com> [111206 21:25]:
> Since omap_dm_timer_write_reg/__omap_dm_timer_write is now modified
> to use timer->func_base OCP_CFG should not use this wrapper anymore.
> Instead use __raw_writel() directly and use timer->io_base instead
> to write to OCP_CFG.
> 
> The timer->sys_stat is valid only if timer->revision is 1. In the
> context restore function make this correction.
> 
> Save the contexts and loss count when timer is stopped.
> Also, disable the clock. Else, clock usecount would become imbalanced.
> 
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> Tested-by: Omar Ramirez Luna <omar.ramirez at ti.com>

Thanks applying this to fixes-non-critical-part2. Sorry for the
delays, looks like I'm a bit behind with patches..

Regards,

Tony


From nico at fluxnic.net  Mon Mar  5 14:41:33 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 14:41:33 -0500 (EST)
Subject: [PATCH v3 21/30] ARM: Add fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-22-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-22-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203051439130.31242@xanadu.home>

On Thu, 1 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> This adds a fixed virtual mapping for PCI i/o addresses. The mapping is
> located at the last 1MB of vmalloc region (0xfef00000).

Please also document this in Documentation/arm/memory.txt.

> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>

With the above comment addressed:

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/include/asm/io.h       |    5 +++++
>  arch/arm/include/asm/mach/pci.h |   18 ++++++++++++++++++
>  arch/arm/kernel/bios32.c        |   23 +++++++++++++++++++++++
>  3 files changed, 46 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
> index d7861b9..5a01930 100644
> --- a/arch/arm/include/asm/io.h
> +++ b/arch/arm/include/asm/io.h
> @@ -106,11 +106,16 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
>  #define __iowmb()		do { } while (0)
>  #endif
>  
> +#define PCI_IO_VIRT_BASE	0xfef00000
> +
>  /*
>   * Now, pick up the machine-defined IO definitions
>   */
>  #ifdef CONFIG_NEED_MACH_IO_H
>  #include <mach/io.h>
> +#elif defined(CONFIG_PCI)
> +#define IO_SPACE_LIMIT	((resource_size_t)0xfffff)
> +#define __io(a)		__typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
>  #else
>  #define __io(a)		({ (void)(a); __typesafe_io(0); })
>  #endif
> diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
> index d943b7d..6d326d7 100644
> --- a/arch/arm/include/asm/mach/pci.h
> +++ b/arch/arm/include/asm/mach/pci.h
> @@ -60,6 +60,24 @@ struct pci_sys_data {
>  void pci_common_init(struct hw_pci *);
>  
>  /*
> + * Setup fixed I/O mapping. Must be called from .map_io function.
> + */
> +#ifdef CONFIG_PCI
> +extern void pci_map_io_pfn(unsigned long pfn[], int nr);
> +#else
> +static inline void pci_map_io_pfn(unsigned long pfn[], int nr) {}
> +#endif
> +static inline void __init pci_map_io_single_pfn(unsigned long pfn)
> +{
> +	pci_map_io_pfn(&pfn, 1);
> +}
> +
> +static inline void __init pci_map_io_single(unsigned long paddr)
> +{
> +	pci_map_io_single_pfn(__phys_to_pfn(paddr));
> +}
> +
> +/*
>   * PCI controllers
>   */
>  extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
> diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
> index f58ba35..199f383 100644
> --- a/arch/arm/kernel/bios32.c
> +++ b/arch/arm/kernel/bios32.c
> @@ -13,6 +13,7 @@
>  #include <linux/io.h>
>  
>  #include <asm/mach-types.h>
> +#include <asm/mach/map.h>
>  #include <asm/mach/pci.h>
>  
>  static int debug_pci;
> @@ -674,3 +675,25 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
>  
>  	return 0;
>  }
> +
> +static struct map_desc pci_io_desc __initdata = {
> +	.virtual	= PCI_IO_VIRT_BASE,
> +	.length		= SZ_1M,
> +	.type		= MT_DEVICE,
> +};
> +
> +void __init pci_map_io_pfn(unsigned long pfn[], int nr)
> +{
> +	int i;
> +
> +	if (nr > 1)
> +		pci_io_desc.length = SZ_64K;
> +
> +	for (i = 0; i < nr; i++) {
> +		pci_io_desc.pfn = pfn[i];
> +		iotable_init(&pci_io_desc, 1);
> +
> +		pci_io_desc.virtual += SZ_64K;
> +	}
> +}
> +
> -- 
> 1.7.5.4
> 


From tony at atomide.com  Mon Mar  5 14:42:15 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 11:42:15 -0800
Subject: [PATCH] ARM: omap: pandora: fix usbhs platform data
In-Reply-To: <1329604985-24740-1-git-send-email-notasas@gmail.com>
References: <1329604985-24740-1-git-send-email-notasas@gmail.com>
Message-ID: <20120305194215.GN12083@atomide.com>

* Grazvydas Ignotas <notasas at gmail.com> [120218 14:11]:
> It turned out wrong OMAP HSUSB port was configured on pandora,
> but still managed to work somehow. This was noticed after enabling
> in-kernel mux, where USB muxing was causing other devices not to work,
> because hsusb1 pins (instead of hsusb2) were wrongly remuxed, which
> are used for other things on pandora.

Thanks, adding this to fixes-non-critical-part2.

Regards,

Tony


From mturquette at ti.com  Mon Mar  5 14:46:54 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Mon, 5 Mar 2012 11:46:54 -0800
Subject: [PATCH v5 2/4] clk: Kconfig: add entry for HAVE_CLK_PREPARE
In-Reply-To: <20120305020410.GB3261@b20223-02.ap.freescale.net>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-3-git-send-email-mturquette@linaro.org>
 <20120305020410.GB3261@b20223-02.ap.freescale.net>
Message-ID: <CAJOA=zOKB-VCKFe7Oh46Wx0FEwub3d8xwSQUuzC1w_soVQXcVQ@mail.gmail.com>

On Sun, Mar 4, 2012 at 6:04 PM, Richard Zhao <richard.zhao at freescale.com> wrote:
> On Sat, Mar 03, 2012 at 12:28:59AM -0800, Mike Turquette wrote:
>> The common clk framework provides clk_prepare and clk_unprepare
>> implementations. ?Create an entry for HAVE_CLK_PREPARE so that
>> COMMON_CLK can select it.
>>
>> Signed-off-by: Mike Turquette <mturquette at linaro.org>
>> Signed-off-by: Mike Turquette <mturquette at ti.com>
>> Acked-by: Shawn Guo <shawn.guo at linaro.org>
>> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
>> Cc: Thomas Gleixner <tglx at linutronix.de>
>> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
>> Cc: Paul Walmsley <paul at pwsan.com>
>> Cc: Richard Zhao <richard.zhao at linaro.org>
>> Cc: Saravana Kannan <skannan at codeaurora.org>
>> Cc: Magnus Damm <magnus.damm at gmail.com>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
>> Cc: Linus Walleij <linus.walleij at stericsson.com>
>> Cc: Stephen Boyd <sboyd at codeaurora.org>
>> Cc: Amit Kucheria <amit.kucheria at linaro.org>
>> Cc: Deepak Saxena <dsaxena at linaro.org>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Cc: Andrew Lunn <andrew at lunn.ch>
>> ---
>> ?drivers/clk/Kconfig | ? ?3 +++
>> ?1 files changed, 3 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>> index 9b3cd08..3912576 100644
>> --- a/drivers/clk/Kconfig
>> +++ b/drivers/clk/Kconfig
>> @@ -8,3 +8,6 @@ config HAVE_CLK_PREPARE
>>
>> ?config HAVE_MACH_CLKDEV
>> ? ? ? bool
>> +
>> +config HAVE_CLK_PREPARE
>> + ? ? bool
> We've already had it. redundant?

I didn't realize that Shawn merged this in since the last posting of V4...

Will drop it.

Regards,
Mike

>
> Thanks
> Richard
>> --
>> 1.7.5.4
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>


From tony at atomide.com  Mon Mar  5 14:50:33 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 11:50:33 -0800
Subject: [PATCH] plat-omap: mcbsp: Configure wakeup in later phase
In-Reply-To: <1323941697-7902-1-git-send-email-peter.ujfalusi@ti.com>
References: <1323941697-7902-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120305195032.GO12083@atomide.com>

Peter,

* Peter Ujfalusi <peter.ujfalusi at ti.com> [111215 01:03]:
> Configure the WAKEUPEN register at the same time we configure the rest of
> the McBSP registers.
> In case of OMAP3+, if the sysclock has been reconfigured we are going to
> disable McBSP for the duration of the clock change, which will reset the
> McBSP registers. The WAKEUPEN register need to be configured later, so
> the changes will be effective during runtime.

Just checking.. I assume this one is already taken care of with your
other McBSP changes?

Tony


From tony at atomide.com  Mon Mar  5 14:53:29 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 11:53:29 -0800
Subject: [PATCH V3 1/2] mcx: very basic support for HTKW mcx board
In-Reply-To: <1324482822-24221-2-git-send-email-yanok@emcraft.com>
References: <1324482822-24221-1-git-send-email-yanok@emcraft.com>
 <1324482822-24221-2-git-send-email-yanok@emcraft.com>
Message-ID: <20120305195329.GP12083@atomide.com>

* Ilya Yanok <yanok at emcraft.com> [111221 07:22]:
> Very basic support for HTKW mcx board. Able to boot via board-generic
> and ramdisk/initramfs, however most of peripherals is unsupported.
> Produces tons of twl4030 related errors as this board doesn't have
> twl4030 installed.
> 
> Signed-off-by: Ilya Yanok <yanok at emcraft.com>

Grant, care to ack this one?

Regards,

Tony

> 
> ---
> Changes from V2:
> 
>  - None
> 
> Changes from V1:
> 
>  - device tree move to the separate patch
>  - iva node is disabled instead of using custom includes
>  - removed bootargs entry
> 
>  arch/arm/boot/dts/mcx.dts |   27 +++++++++++++++++++++++++++
>  1 files changed, 27 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/mcx.dts
> 
> diff --git a/arch/arm/boot/dts/mcx.dts b/arch/arm/boot/dts/mcx.dts
> new file mode 100644
> index 0000000..66b81bd
> --- /dev/null
> +++ b/arch/arm/boot/dts/mcx.dts
> @@ -0,0 +1,27 @@
> +/*
> + * Copyright (C) 2011 Ilya Yanok, EmCraft Systems
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +/dts-v1/;
> +
> +/include/ "omap3.dtsi"
> +
> +/ {
> +	model = "HTKW mcx";
> +	compatible = "htkw,mcx", "ti,omap3";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x80000000 0x10000000>; /* 256 MB */
> +	};
> +
> +	/* AM35xx doesn't have IVA */
> +	soc {
> +		iva {
> +			status = "disabled";
> +		};
> +	};
> +};
> -- 
> 1.7.6.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From tony at atomide.com  Mon Mar  5 14:55:18 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 11:55:18 -0800
Subject: [PATCH V3 2/2] mcx: support for HTKW mcx board
In-Reply-To: <1324482822-24221-3-git-send-email-yanok@emcraft.com>
References: <1324482822-24221-1-git-send-email-yanok@emcraft.com>
 <1324482822-24221-3-git-send-email-yanok@emcraft.com>
Message-ID: <20120305195518.GQ12083@atomide.com>

* Ilya Yanok <yanok at emcraft.com> [111221 07:21]:
> Support for the HTKW mcx board (TI AM3517 based) including serial,
> Ethernet, I2C, USB host, HSMMC, DSS and RTC.

This one I can carry in testing-board until device tree works
for us in a usable way. But probably some rebasing is needed
for this after the hsmmc stuff is cleared out of the way.

Regards,

Tony


From linux at arm.linux.org.uk  Mon Mar  5 14:57:54 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 5 Mar 2012 19:57:54 +0000
Subject: [RFC PATCH] of: DMA helpers: manage generic requests specification
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE861C6E@HQMAIL01.nvidia.com>
References: <4F22DEF2.5000807@ti.com>
 <1330527248-4350-1-git-send-email-nicolas.ferre@atmel.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BDDF217B@HQMAIL01.nvidia.com>
 <4F54BC2E.3040702@ti.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861C6E@HQMAIL01.nvidia.com>
Message-ID: <20120305195754.GA20359@n2100.arm.linux.org.uk>

On Mon, Mar 05, 2012 at 10:30:43AM -0800, Stephen Warren wrote:
> Cousson, Benoit wrote at Monday, March 05, 2012 6:14 AM:
> > Beside u32 and string, do we know what kind of parameters we can expect
> > to retrieve?
> > Because we can potentially reduce the scope to these two types only.
> 
> I wondered whether different drivers would return arbitrary driver-specific
> structs, so that the DT specific would encode not only the DMA request
> number, but perhaps some/all of the DMA parameters like transfer size,
> wrap, even DMA FIFO address, ...

Right.  The thing to consider here is: what information does the driver
already have about the device?

- physical address of the data register
- size of the data register
- it certainly should know the fifo depth (think - if it has to do PIO
  then it needs this information already.)

so, there's no point putting that information into DT because it must be
known by the driver for systems not using DMA.

We have a standardized way to pass this information to DMA engine drivers
from the peripheral device driver: struct dma_slave_config.

What is outside of the scope of the driver is knowing how a peripheral
device is connected to a set of DMA engines.  That's a much harder
problem to solve because there's many varied ways to do that in hardware,
from a static mapping between the peripheral and a DMA engine request
signal, to implementations which have some kind of front end MUX, to
there being several choices of DMA engine for the peripheral (I believe
some Samsung platforms fall into this category.)

Some of those problems can be solved by redesigning the DMA engine
drivers to have a clear way to handle DMA engines with multiple request
inputs shared between multiple channels: you treat the individual request
inputs as separate DMA engine channels, and when there is work to be
done, you allocate the DMA engine channel to a physical DMA engine and
physical channel.

That's not going to be easy to do at the moment, because every DMA
engine driver is custom written from the ground up with no commonality
between them (I've mentioned this in previous email threads.)

I think, before trying to design some kind of DT based representation
of how to bind DMA stuff to peripheral drivers, the very first thing
that needs to happen is the DMA engine drivers need sorting so that
they all work in mostly the same way in terms of how channels are
allocated to peripherals.  Only once we have a consistent way that's
done can we then start looking at what kind of representation is needed
to bind the two together.

Otherwise, we're going to end up with the OMAP way of binding channels,
the PL08x way, the SA11x0 way, etc and its going to become very very
unfunny to sort this out later.


From nico at fluxnic.net  Mon Mar  5 14:59:03 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 14:59:03 -0500 (EST)
Subject: [PATCH v3 27/30] ARM: kirkwood: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-28-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-28-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203051455080.31242@xanadu.home>

On Thu, 1 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Lennert Buytenhek <kernel at wantstofly.org>
> Cc: Nicolas Pitre <nico at fluxnic.net>

I have no PCI hardware making use of the legacy IO area to test this 
with.  But this looks fine.

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
>  arch/arm/Kconfig                               |    1 -
>  arch/arm/mach-kirkwood/common.c                |   21 +++++++++------------
>  arch/arm/mach-kirkwood/include/mach/io.h       |   24 ------------------------
>  arch/arm/mach-kirkwood/include/mach/kirkwood.h |    8 +++-----
>  arch/arm/mach-kirkwood/pcie.c                  |    8 ++++----
>  5 files changed, 16 insertions(+), 46 deletions(-)
>  delete mode 100644 arch/arm/mach-kirkwood/include/mach/io.h
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 24fe29e..50e68b6 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -563,7 +563,6 @@ config ARCH_KIRKWOOD
>  	select PCI
>  	select ARCH_REQUIRE_GPIOLIB
>  	select GENERIC_CLOCKEVENTS
> -	select NEED_MACH_IO_H
>  	select PLAT_ORION
>  	help
>  	  Support for the following Marvell Kirkwood series SoCs:
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index cc15426..db4caa3 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -20,6 +20,7 @@
>  #include <asm/timex.h>
>  #include <asm/kexec.h>
>  #include <asm/mach/map.h>
> +#include <asm/mach/pci.h>
>  #include <asm/mach/time.h>
>  #include <mach/kirkwood.h>
>  #include <mach/bridge-regs.h>
> @@ -37,16 +38,6 @@
>   ****************************************************************************/
>  static struct map_desc kirkwood_io_desc[] __initdata = {
>  	{
> -		.virtual	= KIRKWOOD_PCIE_IO_VIRT_BASE,
> -		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
> -		.length		= KIRKWOOD_PCIE_IO_SIZE,
> -		.type		= MT_DEVICE,
> -	}, {
> -		.virtual	= KIRKWOOD_PCIE1_IO_VIRT_BASE,
> -		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
> -		.length		= KIRKWOOD_PCIE1_IO_SIZE,
> -		.type		= MT_DEVICE,
> -	}, {
>  		.virtual	= KIRKWOOD_REGS_VIRT_BASE,
>  		.pfn		= __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
>  		.length		= KIRKWOOD_REGS_SIZE,
> @@ -56,6 +47,12 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
>  
>  void __init kirkwood_map_io(void)
>  {
> +	unsigned long pci_io_pfn[] = {
> +		__phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
> +		__phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
> +	};
> +	pci_map_io_pfn(pci_io_pfn, ARRAY_SIZE(pci_io_pfn));
> +
>  	iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
>  }
>  
> @@ -472,7 +469,7 @@ void __init kirkwood_init(void)
>  	kirkwood_xor1_init();
>  	kirkwood_crypto_init();
>  
> -#ifdef CONFIG_KEXEC 
> +#ifdef CONFIG_KEXEC
>  	kexec_reinit = kirkwood_enable_pcie;
>  #endif
>  }
> @@ -502,7 +499,7 @@ static int __init kirkwood_clock_gate(void)
>  		/* Disable PHY */
>  		writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
>  	}
> -	
> +
>  	/* For PCIe: first shutdown the phy */
>  	if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
>  		writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
> diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
> deleted file mode 100644
> index 5d0ab61..0000000
> --- a/arch/arm/mach-kirkwood/include/mach/io.h
> +++ /dev/null
> @@ -1,24 +0,0 @@
> -/*
> - * arch/arm/mach-kirkwood/include/mach/io.h
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2.  This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef __ASM_ARCH_IO_H
> -#define __ASM_ARCH_IO_H
> -
> -#include "kirkwood.h"
> -
> -#define IO_SPACE_LIMIT		0xffffffff
> -
> -static inline void __iomem *__io(unsigned long addr)
> -{
> -	return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE)
> -					+ KIRKWOOD_PCIE_IO_VIRT_BASE);
> -}
> -
> -#define __io(a)			__io(a)
> -
> -#endif
> diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
> index fede3d5..63565fb 100644
> --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
> +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
> @@ -37,14 +37,12 @@
>  #define KIRKWOOD_NAND_MEM_SIZE		SZ_1K
>  
>  #define KIRKWOOD_PCIE1_IO_PHYS_BASE	0xf3000000
> -#define KIRKWOOD_PCIE1_IO_VIRT_BASE	0xfef00000
> -#define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00100000
> -#define KIRKWOOD_PCIE1_IO_SIZE		SZ_1M
> +#define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00010000
> +#define KIRKWOOD_PCIE1_IO_SIZE		SZ_64K
>  
>  #define KIRKWOOD_PCIE_IO_PHYS_BASE	0xf2000000
> -#define KIRKWOOD_PCIE_IO_VIRT_BASE	0xfee00000
>  #define KIRKWOOD_PCIE_IO_BUS_BASE	0x00000000
> -#define KIRKWOOD_PCIE_IO_SIZE		SZ_1M
> +#define KIRKWOOD_PCIE_IO_SIZE		SZ_64K
>  
>  #define KIRKWOOD_REGS_PHYS_BASE		0xf1000000
>  #define KIRKWOOD_REGS_VIRT_BASE		0xfed00000
> diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
> index a066a6d..11f557e 100644
> --- a/arch/arm/mach-kirkwood/pcie.c
> +++ b/arch/arm/mach-kirkwood/pcie.c
> @@ -126,8 +126,8 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
>  	 * IORESOURCE_IO
>  	 */
>  	pp->res[0].name = "PCIe 0 I/O Space";
> -	pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
> -	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
> +	pp->res[0].start = 0;
> +	pp->res[0].end = pp->res[0].start + SZ_64K - 1;
>  	pp->res[0].flags = IORESOURCE_IO;
>  
>  	/*
> @@ -148,8 +148,8 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
>  	 * IORESOURCE_IO
>  	 */
>  	pp->res[0].name = "PCIe 1 I/O Space";
> -	pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
> -	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
> +	pp->res[0].start = SZ_64K;
> +	pp->res[0].end = pp->res[0].start + SZ_64K - 1;
>  	pp->res[0].flags = IORESOURCE_IO;
>  
>  	/*
> -- 
> 1.7.5.4
> 


From khilman at ti.com  Mon Mar  5 15:00:16 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 05 Mar 2012 12:00:16 -0800
Subject: [PATCH] omap3_beagle: Init only uart3 used for console
In-Reply-To: <1330945952-14714-1-git-send-email-govindraj.raja@ti.com>
 (Govindraj R.'s message of "Mon, 5 Mar 2012 16:42:32 +0530")
References: <1330945952-14714-1-git-send-email-govindraj.raja@ti.com>
Message-ID: <87399mkecv.fsf@ti.com>

"Govindraj.R" <govindraj.raja at ti.com> writes:

> From: "Govindraj.R" <govindraj.raja at ti.com>
>
> On beagle some of uart mux lines are used for other
> purpose so init only uart3.

OK, but you should also be clear that this patch is effectively
disabling all UARTS (except UART3) by defatul, which I'm not sure all
Beagle users will be happy about.

> Uart2 rx line clashes with gpio_147 used for usb ehci
> phy reset. Initializing uart2 pad_mux lines can break
> ehci module on beagle xm.
> (gpio_147 is available on uart2_rx in mode4 reference 
> mux34xx.c -> uart2_rx.gpio_147)

As Koen mentioned, this conflict only exists on certain boards, so
you should be clear that this is just an example.

> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Tested-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Tested-by: Robert Nelson <robertcnelson at gmail.com>
> Signed-off-by: Govindraj.R <govindraj.raja at ti.com>

[...]

> +
> +static inline void board_serial_init(void)

Should be __init

[...]

> +static inline void board_serial_init(void)

here too.

Kevin


From mturquette at ti.com  Mon Mar  5 15:03:15 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Mon, 5 Mar 2012 12:03:15 -0800
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120305073836.GU3852@pengutronix.de>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
Message-ID: <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>

On Sun, Mar 4, 2012 at 11:38 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Sun, Mar 04, 2012 at 04:12:21PM -0800, Turquette, Mike wrote:
>> >>
>> >> I believe this patch already does what you suggest, but I might be
>> >> missing your point.
>> >
>> > In include/linux/clk-private.h you expose struct clk outside the core.
>> > This has to be done to make static initializers possible. There is a big
>> > warning in this file that it must not be included from files implementing
>> > struct clk_ops. You can simply avoid this warning by declaring struct clk
>> > with only a single member:
>> >
>> > include/linux/clk.h:
>> >
>> > struct clk {
>> > ? ? ? ?struct clk_internal *internal;
>> > };
>> >
>> > This way everybody knows struct clk (thus can embed it in their static
>> > initializers), but doesn't know anything about the internal members. Now
>> > in drivers/clk/clk.c you declare struct clk_internal exactly like struct
>> > clk was declared before:
>> >
>> > struct clk_internal {
>> > ? ? ? ?const char ? ? ? ? ? ? ?*name;
>> > ? ? ? ?const struct clk_ops ? ?*ops;
>> > ? ? ? ?struct clk_hw ? ? ? ? ? *hw;
>> > ? ? ? ?struct clk ? ? ? ? ? ? ?*parent;
>> > ? ? ? ?char ? ? ? ? ? ? ? ? ? ?**parent_names;
>> > ? ? ? ?struct clk ? ? ? ? ? ? ?**parents;
>> > ? ? ? ?u8 ? ? ? ? ? ? ? ? ? ? ?num_parents;
>> > ? ? ? ?unsigned long ? ? ? ? ? rate;
>> > ? ? ? ?unsigned long ? ? ? ? ? flags;
>> > ? ? ? ?unsigned int ? ? ? ? ? ?enable_count;
>> > ? ? ? ?unsigned int ? ? ? ? ? ?prepare_count;
>> > ? ? ? ?struct hlist_head ? ? ? children;
>> > ? ? ? ?struct hlist_node ? ? ? child_node;
>> > ? ? ? ?unsigned int ? ? ? ? ? ?notifier_count;
>> > #ifdef CONFIG_COMMON_CLK_DEBUG
>> > ? ? ? ?struct dentry ? ? ? ? ? *dentry;
>> > #endif
>> > };
>> >
>> > An instance of struct clk_internal will be allocated in
>> > __clk_init/clk_register. Now the private data stays completely inside
>> > the core and noone can abuse it.
>>
>> Hi Sascha,
>>
>> I see the disconnect here. ?For OMAP (and possibly other platforms) at
>> least some clock data is necessary during early boot, before the
>> regular allocation methods are available (timers for instance).
>
> We had this problem on i.MX aswell. It turned out that the timer clock
> is the only clock that is needed so early. We solved this by moving the
> clock init to the system timer init function.

When you say "mov[ed] the clock init to the system timer init
function" do you mean that you statically allocated struct clk and
used the clk framework api, or instead you just did some direct
register writes to initialize things properly?

>
>> Due
>> to this my idea of static initialization was to take care of
>> everything that would normally require an allocator, which includes
>> the internals of struct clk; thus exposing struct clk is useful here
>> as you can still use the clock framework during very early boot. ?Your
>> method above doesn't satisfy this requirement. ?I'm not sure what the
>> purpose would be of statically allocating your version of struct clk,
>> which will ultimately need to allocate memory for the clock internals
>> anyways. ?Can you elaborate the benefit of this approach over just
>> using the clk_foo_register functions?
>
> As said the benefit is that you do not have to expose the internal
> layout of struct clk outside the clock framework. Note that in the

That is a benefit for sure, but if it does not solve the problem of
allowing for static allocation then we still have an issue.

> file you referenced here:
>
> http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=arch/arm/mach-omap2/clock44xx_data.c;h=7f833a7b2dca84a52c2bd1e7c8d9cfe560771258;hb=v3.3-rc5-clkv5-omap#l205
>
> You violate what you have in a comment above clk-private.h:
>
> /* __clk_init is only exposed via clk-private.h and is intended for use with
> ?* very large numbers of clocks that need to be statically initialized. It is
> ?* a layering violation to include clk-private.h from any code which implements
> ?* a clock's .ops; as such any statically initialized clock data MUST be in
> ?* separate C file from the logic that implements it's operations.
> ?*/
>
> Well, the file is work in progress, you probably fix this before sending
> it out, but I bet people will include clk-private.h and nobody else
> notices it.

clock44xx_data.c does not violate that rule.  None of the logic that
implements ops for those clocks is present clock44xx_data.c.  All of
the code in that file is simply initialization and registration of
OMAP4 clocks.  Many of the clocks are basic clock types (divider,
multiplexer and fixed-rate are used in that file) with protected code
drivers/clk/clk-*.c and the remaining clocks are of the struct
clk_hw_omap variety, which has code spread across several files:

arch/arm/mach-omap2/clock.c
arch/arm/mach-omap2/clock.h
arch/arm/mach-omap2/clkt_dpll.c
arch/arm/mach-omap2/clkt_clksel.c
arch/arm/mach-omap2/dpll3xxx.c
arch/arm/mach-omap2/dpll4xxx.c

All of the above files include linux/clk-provider.h, not
linux/clk-private.h.  That code makes heavy use of the
__clk_get_whatever helpers and shows how a platform might honor the
layer of separation between struct clk and stuct clk_ops/struct
clk_foo.  You are correct that the code is a work-in-progress, but
there are no layering violations that I can see.

I also think we are talking past each other to some degree.  One point
I would like to make (and maybe you already know this from code
review) is that it is unnecessary to have pointers to your parent
struct clk*'s when either initializing or registering your clocks.  In
fact the existing clk_register_foo functions don't even allow you to
pass in parent pointers and rely wholly on string name matching.  I
just wanted to point that out in case it went unnoticed, as it is a
new way of doing things from the previous series and was born out of
Thomas' review of V4 and multi-parent handling.  This also keeps
device-tree in mind where we might not know the struct clk *pointer at
compile time for "connecting" discrete devices.

Thanks,
Mike

>
> Sascha
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |


From nico at fluxnic.net  Mon Mar  5 15:12:20 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 15:12:20 -0500 (EST)
Subject: [PATCH v3 26/30] ARM: dove: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-27-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-27-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203051505230.31242@xanadu.home>

On Thu, 1 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> The i/o regions are changed from 1MB to 64KB. It's likely that the 2nd
> bus is not setup correctly.
[...]
> index ad1165d..50b9046 100644
> --- a/arch/arm/mach-dove/include/mach/dove.h
> +++ b/arch/arm/mach-dove/include/mach/dove.h
> @@ -50,14 +50,12 @@
>  #define DOVE_NB_REGS_SIZE		SZ_8M
>  
>  #define DOVE_PCIE0_IO_PHYS_BASE		0xf2000000
> -#define DOVE_PCIE0_IO_VIRT_BASE		0xfee00000
>  #define DOVE_PCIE0_IO_BUS_BASE		0x00000000
> -#define DOVE_PCIE0_IO_SIZE		SZ_1M
> +#define DOVE_PCIE0_IO_SIZE		SZ_64K
>  
>  #define DOVE_PCIE1_IO_PHYS_BASE		0xf2100000
> -#define DOVE_PCIE1_IO_VIRT_BASE		0xfef00000
> -#define DOVE_PCIE1_IO_BUS_BASE		0x00100000
> -#define DOVE_PCIE1_IO_SIZE		SZ_1M
> +#define DOVE_PCIE1_IO_BUS_BASE		0x00010000
> +#define DOVE_PCIE1_IO_SIZE		SZ_64K

You better not touch DOVE_PCIE1_IO_BUS_BASE and just leave it at 
0x00100000.  This is used for configuration of the physical window 
address, to match with DOVE_PCIE1_IO_PHYS_BASE, and that has no impact 
on the virtual address used to map that window (yes, Dove and the rest 
of the Orion based SOCs have the ability to change their physical memory 
map).

With that fixed:

Acked-by: Nicolas Pitre <nico at linaro.org>

>  
>  /*
>   * Dove Core Registers Map
> diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
> deleted file mode 100644
> index 29c8b85..0000000
> --- a/arch/arm/mach-dove/include/mach/io.h
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -/*
> - * arch/arm/mach-dove/include/mach/io.h
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2.  This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#ifndef __ASM_ARCH_IO_H
> -#define __ASM_ARCH_IO_H
> -
> -#include "dove.h"
> -
> -#define IO_SPACE_LIMIT		0xffffffff
> -
> -#define __io(a)  	((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
> -						 DOVE_PCIE0_IO_VIRT_BASE))
> -
> -#endif
> diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
> index 52e96d3..0a741bd 100644
> --- a/arch/arm/mach-dove/pcie.c
> +++ b/arch/arm/mach-dove/pcie.c
> @@ -59,13 +59,8 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
>  		 "PCIe %d I/O", pp->index);
>  	pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
>  	pp->res[0].name = pp->io_space_name;
> -	if (pp->index == 0) {
> -		pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
> -		pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
> -	} else {
> -		pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
> -		pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
> -	}
> +	pp->res[0].start = nr * SZ_64K;
> +	pp->res[0].end = pp->res[0].start + SZ_64K;
>  	pp->res[0].flags = IORESOURCE_IO;
>  	if (request_resource(&ioport_resource, &pp->res[0]))
>  		panic("Request PCIe IO resource failed\n");
> -- 
> 1.7.5.4
> 


From arnd at arndb.de  Mon Mar  5 15:13:26 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 5 Mar 2012 20:13:26 +0000
Subject: [PATCH v3 02/30] ARM: provide runtime hook for ioremap/iounmap
In-Reply-To: <alpine.LFD.2.02.1203051415150.31242@xanadu.home>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-3-git-send-email-robherring2@gmail.com>
 <alpine.LFD.2.02.1203051415150.31242@xanadu.home>
Message-ID: <201203052013.26688.arnd@arndb.de>

On Monday 05 March 2012, Nicolas Pitre wrote:
> Given that the majority of existing platforms don't need the 
> indirection, should we make this indirection conditional on 
> CONFIG_NEED_IOREMAP_HOOK and let those who need it select it?  Or maybe 
> this isn't performance critical and we just don't care?  In any case I'd 
> like to see such reasoning captured in the commit log.

It's certainly not performance critical, but there may be some space overhead
in the .text section of the kernel that we could avoid by adding another
indirection.

	Arnd


From nico at fluxnic.net  Mon Mar  5 15:13:53 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 15:13:53 -0500 (EST)
Subject: [PATCH v3 30/30] ARM: orion5x: use fixed PCI i/o mapping
In-Reply-To: <1330658022-14559-31-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-31-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203051513210.31242@xanadu.home>

On Thu, 1 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> orion5x i/o handling must have been broken as it had no __io()
> translation. It may actually work now.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Lennert Buytenhek <kernel at wantstofly.org>
> Cc: Nicolas Pitre <nico at fluxnic.net>

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/mach-orion5x/common.c |   16 ++++++----------
>  1 files changed, 6 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
> index 0e28bae..9bab4cb 100644
> --- a/arch/arm/mach-orion5x/common.c
> +++ b/arch/arm/mach-orion5x/common.c
> @@ -24,6 +24,7 @@
>  #include <asm/timex.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> +#include <asm/mach/pci.h>
>  #include <asm/mach/time.h>
>  #include <mach/bridge-regs.h>
>  #include <mach/hardware.h>
> @@ -44,16 +45,6 @@ static struct map_desc orion5x_io_desc[] __initdata = {
>  		.length		= ORION5X_REGS_SIZE,
>  		.type		= MT_DEVICE,
>  	}, {
> -		.virtual	= ORION5X_PCIE_IO_VIRT_BASE,
> -		.pfn		= __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
> -		.length		= ORION5X_PCIE_IO_SIZE,
> -		.type		= MT_DEVICE,
> -	}, {
> -		.virtual	= ORION5X_PCI_IO_VIRT_BASE,
> -		.pfn		= __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
> -		.length		= ORION5X_PCI_IO_SIZE,
> -		.type		= MT_DEVICE,
> -	}, {
>  		.virtual	= ORION5X_PCIE_WA_VIRT_BASE,
>  		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
>  		.length		= ORION5X_PCIE_WA_SIZE,
> @@ -63,6 +54,11 @@ static struct map_desc orion5x_io_desc[] __initdata = {
>  
>  void __init orion5x_map_io(void)
>  {
> +	unsigned long pci_io_pfn[] = {
> +		__phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
> +		__phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
> +	};
> +	pci_map_io_pfn(pci_io_pfn, ARRAY_SIZE(pci_io_pfn));
>  	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
>  }
>  
> -- 
> 1.7.5.4
> 


From nico at fluxnic.net  Mon Mar  5 14:14:46 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 14:14:46 -0500 (EST)
Subject: [PATCH v3 11/30] ARM: orion5x: clean-up mach/io.h
In-Reply-To: <1330658022-14559-12-git-send-email-robherring2@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-12-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203051414240.31242@xanadu.home>

On Thu, 1 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> Move orion5x specific mach/io.h parts into common.h.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Lennert Buytenhek <kernel at wantstofly.org>
> Cc: Nicolas Pitre <nico at fluxnic.net>

Acked-by: Nicolas Pitre <nico at linaro.org>



> ---
>  arch/arm/mach-orion5x/common.h          |    9 +++++++++
>  arch/arm/mach-orion5x/include/mach/io.h |   12 ------------
>  arch/arm/mach-orion5x/pci.c             |    1 +
>  arch/arm/mach-orion5x/tsx09-common.c    |    1 +
>  4 files changed, 11 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
> index d2513ac..2e6454c 100644
> --- a/arch/arm/mach-orion5x/common.h
> +++ b/arch/arm/mach-orion5x/common.h
> @@ -57,5 +57,14 @@ struct meminfo;
>  struct tag;
>  extern void __init tag_fixup_mem32(struct tag *, char **, struct meminfo *);
>  
> +/*****************************************************************************
> + * Helpers to access Orion registers
> + ****************************************************************************/
> +/*
> + * These are not preempt-safe.  Locks, if needed, must be taken
> + * care of by the caller.
> + */
> +#define orion5x_setbits(r, mask)	writel(readl(r) | (mask), (r))
> +#define orion5x_clrbits(r, mask)	writel(readl(r) & ~(mask), (r))
>  
>  #endif
> diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
> index e9d9afd..444136d 100644
> --- a/arch/arm/mach-orion5x/include/mach/io.h
> +++ b/arch/arm/mach-orion5x/include/mach/io.h
> @@ -18,16 +18,4 @@
>  #define __io(a)			__typesafe_io(a)
>  #define __mem_pci(a)		(a)
>  
> -
> -/*****************************************************************************
> - * Helpers to access Orion registers
> - ****************************************************************************/
> -/*
> - * These are not preempt-safe.  Locks, if needed, must be taken
> - * care of by the caller.
> - */
> -#define orion5x_setbits(r, mask)	writel(readl(r) | (mask), (r))
> -#define orion5x_clrbits(r, mask)	writel(readl(r) & ~(mask), (r))
> -
> -
>  #endif
> diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
> index 09a045f..a9d2151 100644
> --- a/arch/arm/mach-orion5x/pci.c
> +++ b/arch/arm/mach-orion5x/pci.c
> @@ -19,6 +19,7 @@
>  #include <asm/mach/pci.h>
>  #include <plat/pcie.h>
>  #include <plat/addr-map.h>
> +#include <mach/orion5x.h>
>  #include "common.h"
>  
>  /*****************************************************************************
> diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c
> index c9abb8f..7189827 100644
> --- a/arch/arm/mach-orion5x/tsx09-common.c
> +++ b/arch/arm/mach-orion5x/tsx09-common.c
> @@ -15,6 +15,7 @@
>  #include <linux/mv643xx_eth.h>
>  #include <linux/timex.h>
>  #include <linux/serial_reg.h>
> +#include <mach/orion5x.h>
>  #include "tsx09-common.h"
>  #include "common.h"
>  
> -- 
> 1.7.5.4
> 


From paul at pwsan.com  Mon Mar  5 15:16:23 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 5 Mar 2012 13:16:23 -0700 (MST)
Subject: [PATCH] ARM: OMAP2+: omap_device: call all suspend, resume
 callbacks when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set
In-Reply-To: <877gyzoyyk.fsf@ti.com>
References: <alpine.DEB.2.00.1203031314050.10611@utopia.booyaka.com>
 <877gyzoyyk.fsf@ti.com>
Message-ID: <alpine.DEB.2.00.1203051312390.1430@utopia.booyaka.com>

On Mon, 5 Mar 2012, Kevin Hilman wrote:

> Tony, this fix is needed for v3.3.

Of course, I don't have any objection to this patch going into the v3.3-rc 
kernels.  But given that some maintainers seem to be pushing back against 
late -rc patches, this one could probably be delayed to 3.4 if required.  
no_console_suspend is a debugging-only option and bugs involving it are 
unlikely to affect most users.


- Paul


From arnd at arndb.de  Mon Mar  5 15:16:26 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 5 Mar 2012 20:16:26 +0000
Subject: [PULL REQUEST v2] ARM: kirkwood: fdt: convert kirkwood init funcs
 to fdt
In-Reply-To: <20120305191546.GK5050@titan.lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <alpine.LFD.2.02.1203051344130.31242@xanadu.home>
 <20120305191546.GK5050@titan.lakedaemon.net>
Message-ID: <201203052016.26949.arnd@arndb.de>

On Monday 05 March 2012, Jason wrote:
> > 
> > The clock frequency part being hardcoded to 200000 in the common .dtsi 
> > file looks wrong.  The clock may differ, and it used to (and should) be 
> > probed at run time, please see kirkwood_find_tclk().
> 
> So, should I EXPORT_SYMBOL_GPL(kirkwood_find_tclk); and have each driver
> call it?

If the drivers want to use it, I think it has to be orion_find_tclk for
drivers that are shared between multiple plat-orion platforms.

> One alternate idea I had was to have kirkwood-dreamplug.dts root hold
> 
> tclk: clock-frequency = <200000000>;
> 
> and then have the drivers ask for it.  afaict, tclk is constant per
> board.
> 
> I'm fine with either way, but I'd rather have it in the dt.

IMHO it's best to leave any such hacks out of the device tree for
now, until we have the proper clk bindings in place for kirkwood,
and then we can just use those.

	Arnd


From linux at arm.linux.org.uk  Mon Mar  5 15:14:11 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 5 Mar 2012 20:14:11 +0000
Subject: [PATCH 0/9] DMA engine cookie handling cleanups
Message-ID: <20120305201411.GA17791@n2100.arm.linux.org.uk>

This patch series cleans up the handling of cookies in DMA engine drivers.
This is done by providing a set of inline library functions for common
tasks:

- moving the 'last completed cookie' into struct dma_chan - everyone
  has this in their driver private channel data structure

- consolidate allocation of cookies to DMA descriptors

- common way to update 'last completed cookie' value

- standard way to implement tx_status callback and update the residue

- consolidate initialization of cookies

- update implementations differing from the majority of DMA engine drivers
  to behave the same as the majority implementation in respect of cookies

What this means is that we get to the point where all DMA engine drivers
will hand out cookie value '2' as the first, and incrementing cookie
values up to INT_MAX, returning to cookie '1' as the next cookie.

Think of this patch series as round 1...  I am hoping over time that more
code can be consolidated between the DMA engine drivers and end up with a
consistent way to handle various common themes in DMA engine hardware
(like physical channel<->peripheral request signal selection.)

I've only build-tested this stuff on a few ARM configs, and my ability
to run-test this stuff is even more limited by all the broken useless DMA
engine hardware I have access to (mostly pl08x based) so having some
tested-bys would be a great advantage.

Overall, the diffstat looks like this:

 arch/arm/include/asm/hardware/iop_adma.h |    2 -
 drivers/dma/amba-pl08x.c                 |   38 ++++---------
 drivers/dma/at_hdmac.c                   |   48 ++++------------
 drivers/dma/at_hdmac_regs.h              |    2 -
 drivers/dma/coh901318.c                  |   39 +++----------
 drivers/dma/dmaengine.h                  |   89 ++++++++++++++++++++++++++++++
 drivers/dma/dw_dmac.c                    |   43 +++-----------
 drivers/dma/dw_dmac_regs.h               |    1 -
 drivers/dma/ep93xx_dma.c                 |   25 ++------
 drivers/dma/fsldma.c                     |   24 ++------
 drivers/dma/fsldma.h                     |    1 -
 drivers/dma/imx-dma.c                    |   32 ++---------
 drivers/dma/imx-sdma.c                   |   23 ++------
 drivers/dma/intel_mid_dma.c              |   37 +++---------
 drivers/dma/intel_mid_dma_regs.h         |    2 -
 drivers/dma/ioat/dma.c                   |   21 +++----
 drivers/dma/ioat/dma.h                   |   23 --------
 drivers/dma/ioat/dma_v2.c                |   13 ++---
 drivers/dma/ioat/dma_v3.c                |   11 ++--
 drivers/dma/iop-adma.c                   |   51 ++++-------------
 drivers/dma/ipu/ipu_idmac.c              |   22 ++-----
 drivers/dma/mpc512x_dma.c                |   25 +++------
 drivers/dma/mv_xor.c                     |   34 ++---------
 drivers/dma/mv_xor.h                     |    3 -
 drivers/dma/mxs-dma.c                    |   23 ++------
 drivers/dma/pch_dma.c                    |   34 ++---------
 drivers/dma/pl330.c                      |   36 ++----------
 drivers/dma/ppc4xx/adma.c                |   49 +++-------------
 drivers/dma/ppc4xx/adma.h                |    2 -
 drivers/dma/shdma.c                      |   30 +++-------
 drivers/dma/shdma.h                      |    1 -
 drivers/dma/sirf-dma.c                   |   23 ++------
 drivers/dma/ste_dma40.c                  |   36 +++---------
 drivers/dma/timb_dma.c                   |   28 +++-------
 drivers/dma/txx9dmac.c                   |   41 +++-----------
 drivers/dma/txx9dmac.h                   |    1 -
 include/linux/amba/pl08x.h               |    2 -
 include/linux/dmaengine.h                |    2 +
 38 files changed, 291 insertions(+), 626 deletions(-)



From linux at arm.linux.org.uk  Mon Mar  5 15:17:13 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 05 Mar 2012 20:17:13 +0000
Subject: [PATCH 7/9] dmaengine: consolidate initialization of cookies
In-Reply-To: <20120305201411.GA17791@n2100.arm.linux.org.uk>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
Message-ID: <E1S4eLJ-0000tP-Th@rmk-PC.arm.linux.org.uk>

Provide a common function to initialize a channels cookie values.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/amba-pl08x.c    |    3 +--
 drivers/dma/at_hdmac.c      |    4 ++--
 drivers/dma/coh901318.c     |    2 +-
 drivers/dma/dmaengine.h     |   10 ++++++++++
 drivers/dma/dw_dmac.c       |    4 ++--
 drivers/dma/ep93xx_dma.c    |    3 +--
 drivers/dma/intel_mid_dma.c |    4 ++--
 drivers/dma/ipu/ipu_idmac.c |    6 ++----
 drivers/dma/mpc512x_dma.c   |    3 +--
 drivers/dma/pch_dma.c       |    4 ++--
 drivers/dma/pl330.c         |    2 +-
 drivers/dma/sirf-dma.c      |    3 +--
 drivers/dma/ste_dma40.c     |    2 +-
 drivers/dma/timb_dma.c      |    5 ++---
 drivers/dma/txx9dmac.c      |    4 ++--
 15 files changed, 31 insertions(+), 28 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 2781a2b..13c4d08 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -1707,8 +1707,7 @@ static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
 			 chan->name);
 
 		chan->chan.device = dmadev;
-		chan->chan.cookie = 0;
-		chan->chan.completed_cookie = 0;
+		dma_cookie_init(&chan->chan);
 
 		spin_lock_init(&chan->lock);
 		INIT_LIST_HEAD(&chan->pend_list);
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 8a32974..5d225dd 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -1103,7 +1103,7 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
 	spin_lock_irqsave(&atchan->lock, flags);
 	atchan->descs_allocated = i;
 	list_splice(&tmp_list, &atchan->free_list);
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 	spin_unlock_irqrestore(&atchan->lock, flags);
 
 	/* channel parameters */
@@ -1303,7 +1303,7 @@ static int __init at_dma_probe(struct platform_device *pdev)
 		struct at_dma_chan	*atchan = &atdma->chan[i];
 
 		atchan->chan_common.device = &atdma->dma_common;
-		atchan->chan_common.cookie = atchan->chan_common.completed_cookie = 1;
+		dma_cookie_init(&atchan->chan_common);
 		list_add_tail(&atchan->chan_common.device_node,
 				&atdma->dma_common.channels);
 
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index f350517..187bb9e 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -915,7 +915,7 @@ static int coh901318_alloc_chan_resources(struct dma_chan *chan)
 	coh901318_config(cohc, NULL);
 
 	cohc->allocated = 1;
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 
 	spin_unlock_irqrestore(&cohc->lock, flags);
 
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
index 244a2c5..bb1b693 100644
--- a/drivers/dma/dmaengine.h
+++ b/drivers/dma/dmaengine.h
@@ -9,6 +9,16 @@
 #include <linux/dmaengine.h>
 
 /**
+ * dma_cookie_init - initialize the cookies for a DMA channel
+ * @chan: dma channel to initialize
+ */
+static inline void dma_cookie_init(struct dma_chan *chan)
+{
+	chan->cookie = DMA_MIN_COOKIE;
+	chan->completed_cookie = DMA_MIN_COOKIE;
+}
+
+/**
  * dma_cookie_assign - assign a DMA engine cookie to the descriptor
  * @tx: descriptor needing cookie
  *
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index acc3bc0..8b4be42 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -979,7 +979,7 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
 		return -EIO;
 	}
 
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 
 	/*
 	 * NOTE: some controllers may have additional features that we
@@ -1398,7 +1398,7 @@ static int __init dw_probe(struct platform_device *pdev)
 		struct dw_dma_chan	*dwc = &dw->chan[i];
 
 		dwc->chan.device = &dw->dma;
-		dwc->chan.cookie = dwc->chan.completed_cookie = 1;
+		dma_cookie_init(&dwc->chan);
 		if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
 			list_add_tail(&dwc->chan.device_node,
 					&dw->dma.channels);
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index 142ebf0..f25e83b 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -854,8 +854,7 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
 		goto fail_clk_disable;
 
 	spin_lock_irq(&edmac->lock);
-	edmac->chan.completed_cookie = 1;
-	edmac->chan.cookie = 1;
+	dma_cookie_init(&edmac->chan);
 	ret = edmac->edma->hw_setup(edmac);
 	spin_unlock_irq(&edmac->lock);
 
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index 69ed1e6..9d82a84 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -867,7 +867,7 @@ static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
 		pm_runtime_put(&mid->pdev->dev);
 		return -EIO;
 	}
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 
 	spin_lock_bh(&midc->lock);
 	while (midc->descs_allocated < DESCS_PER_CHANNEL) {
@@ -1099,7 +1099,7 @@ static int mid_setup_dma(struct pci_dev *pdev)
 		struct intel_mid_dma_chan *midch = &dma->ch[i];
 
 		midch->chan.device = &dma->common;
-		midch->chan.cookie =  1;
+		dma_cookie_init(&midch->chan);
 		midch->ch_id = dma->chan_base + i;
 		pr_debug("MDMA:Init CH %d, ID %d\n", i, midch->ch_id);
 
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index bff9250..1880274 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -1504,8 +1504,7 @@ static int idmac_alloc_chan_resources(struct dma_chan *chan)
 	BUG_ON(chan->client_count > 1);
 	WARN_ON(ichan->status != IPU_CHANNEL_FREE);
 
-	chan->cookie		= 1;
-	chan->completed_cookie	= -ENXIO;
+	dma_cookie_init(chan);
 
 	ret = ipu_irq_map(chan->chan_id);
 	if (ret < 0)
@@ -1633,8 +1632,7 @@ static int __init ipu_idmac_init(struct ipu *ipu)
 		snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
 
 		dma_chan->device	= &idmac->dma;
-		dma_chan->cookie	= 1;
-		dma_chan->completed_cookie	= -ENXIO;
+		dma_cookie_init(dma_chan);
 		dma_chan->chan_id	= i;
 		list_add_tail(&dma_chan->device_node, &dma->channels);
 	}
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index 1382715..2ab0a3d 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -733,8 +733,7 @@ static int __devinit mpc_dma_probe(struct platform_device *op)
 		mchan = &mdma->channels[i];
 
 		mchan->chan.device = dma;
-		mchan->chan.cookie = 1;
-		mchan->chan.completed_cookie = mchan->chan.cookie;
+		dma_cookie_init(&mchan->chan);
 
 		INIT_LIST_HEAD(&mchan->free);
 		INIT_LIST_HEAD(&mchan->prepared);
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index c30f63e..c93bb045 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -531,7 +531,7 @@ static int pd_alloc_chan_resources(struct dma_chan *chan)
 	spin_lock_irq(&pd_chan->lock);
 	list_splice(&tmp_list, &pd_chan->free_list);
 	pd_chan->descs_allocated = i;
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 	spin_unlock_irq(&pd_chan->lock);
 
 	pdc_enable_irq(chan, 1);
@@ -912,7 +912,7 @@ static int __devinit pch_dma_probe(struct pci_dev *pdev,
 		struct pch_dma_chan *pd_chan = &pd->channels[i];
 
 		pd_chan->chan.device = &pd->dma;
-		pd_chan->chan.cookie = 1;
+		dma_cookie_init(&pd_chan->chan);
 
 		pd_chan->membase = &regs->desc[i];
 
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 1993286..49c123f 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -304,7 +304,7 @@ static int pl330_alloc_chan_resources(struct dma_chan *chan)
 
 	spin_lock_irqsave(&pch->lock, flags);
 
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 	pch->cyclic = false;
 
 	pch->pl330_chid = pl330_request_channel(&pdmac->pif);
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index a760d98..a2cde85 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -625,8 +625,7 @@ static int __devinit sirfsoc_dma_probe(struct platform_device *op)
 		schan = &sdma->channels[i];
 
 		schan->chan.device = dma;
-		schan->chan.cookie = 1;
-		schan->chan.completed_cookie = schan->chan.cookie;
+		dma_cookie_init(&schan->chan);
 
 		INIT_LIST_HEAD(&schan->free);
 		INIT_LIST_HEAD(&schan->prepared);
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 07b82e3..1ea6d02 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2172,7 +2172,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 	bool is_free_phy;
 	spin_lock_irqsave(&d40c->lock, flags);
 
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 
 	/* If no dma configuration is set use default configuration (memcpy) */
 	if (!d40c->configured) {
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index 6383abb..7805996 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -477,8 +477,7 @@ static int td_alloc_chan_resources(struct dma_chan *chan)
 	}
 
 	spin_lock_bh(&td_chan->lock);
-	chan->completed_cookie = 1;
-	chan->cookie = 1;
+	dma_cookie_init(chan);
 	spin_unlock_bh(&td_chan->lock);
 
 	return 0;
@@ -755,7 +754,7 @@ static int __devinit td_probe(struct platform_device *pdev)
 		}
 
 		td_chan->chan.device = &td->dma;
-		td_chan->chan.cookie = 1;
+		dma_cookie_init(&td_chan->chan);
 		spin_lock_init(&td_chan->lock);
 		INIT_LIST_HEAD(&td_chan->active_list);
 		INIT_LIST_HEAD(&td_chan->queue);
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index bb7b3d9..40440f9 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -1034,7 +1034,7 @@ static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
 		return -EIO;
 	}
 
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 
 	dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
 	txx9dmac_chan_set_SMPCHN(dc);
@@ -1163,7 +1163,7 @@ static int __init txx9dmac_chan_probe(struct platform_device *pdev)
 	dc->ddev->chan[ch] = dc;
 	dc->chan.device = &dc->dma;
 	list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
-	dc->chan.cookie = dc->chan.completed_cookie = 1;
+	dma_cookie_init(&dc->chan);
 
 	if (is_dmac64(dc))
 		dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
-- 
1.7.4.4



From linux at arm.linux.org.uk  Mon Mar  5 15:15:31 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 05 Mar 2012 20:15:31 +0000
Subject: [PATCH 2/9] dmaengine: move last completed cookie into generic
 dma_chan structure
In-Reply-To: <20120305201411.GA17791@n2100.arm.linux.org.uk>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
Message-ID: <E1S4eJf-0000sq-QT@rmk-PC.arm.linux.org.uk>

Every DMA engine implementation declares a last completed dma cookie
in their private dma channel structures.  This is pointless, and
forces driver specific code.  Move this out into the common dma_chan
structure.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/include/asm/hardware/iop_adma.h |    2 --
 drivers/dma/amba-pl08x.c                 |    8 ++++----
 drivers/dma/at_hdmac.c                   |   10 +++++-----
 drivers/dma/at_hdmac_regs.h              |    2 --
 drivers/dma/coh901318.c                  |    7 +++----
 drivers/dma/dw_dmac.c                    |   10 +++++-----
 drivers/dma/dw_dmac_regs.h               |    1 -
 drivers/dma/ep93xx_dma.c                 |    8 +++-----
 drivers/dma/fsldma.c                     |    4 ++--
 drivers/dma/fsldma.h                     |    1 -
 drivers/dma/imx-dma.c                    |    7 +++----
 drivers/dma/imx-sdma.c                   |    5 ++---
 drivers/dma/intel_mid_dma.c              |    9 ++++-----
 drivers/dma/intel_mid_dma_regs.h         |    2 --
 drivers/dma/ioat/dma.c                   |    2 +-
 drivers/dma/ioat/dma.h                   |    4 +---
 drivers/dma/ioat/dma_v2.c                |    2 +-
 drivers/dma/ioat/dma_v3.c                |    2 +-
 drivers/dma/iop-adma.c                   |   10 +++++-----
 drivers/dma/ipu/ipu_idmac.c              |   10 ++++------
 drivers/dma/mpc512x_dma.c                |    7 +++----
 drivers/dma/mv_xor.c                     |    6 +++---
 drivers/dma/mv_xor.h                     |    2 --
 drivers/dma/mxs-dma.c                    |    5 ++---
 drivers/dma/pch_dma.c                    |    5 ++---
 drivers/dma/pl330.c                      |    9 +++------
 drivers/dma/ppc4xx/adma.c                |   10 +++++-----
 drivers/dma/ppc4xx/adma.h                |    2 --
 drivers/dma/shdma.c                      |   10 +++++-----
 drivers/dma/shdma.h                      |    1 -
 drivers/dma/sirf-dma.c                   |    7 +++----
 drivers/dma/ste_dma40.c                  |   10 +++-------
 drivers/dma/timb_dma.c                   |    7 +++----
 drivers/dma/txx9dmac.c                   |   10 +++++-----
 drivers/dma/txx9dmac.h                   |    1 -
 include/linux/amba/pl08x.h               |    2 --
 include/linux/dmaengine.h                |    2 ++
 37 files changed, 83 insertions(+), 119 deletions(-)

diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h
index 59b8c38..122f86d 100644
--- a/arch/arm/include/asm/hardware/iop_adma.h
+++ b/arch/arm/include/asm/hardware/iop_adma.h
@@ -49,7 +49,6 @@ struct iop_adma_device {
 /**
  * struct iop_adma_chan - internal representation of an ADMA device
  * @pending: allows batching of hardware operations
- * @completed_cookie: identifier for the most recently completed operation
  * @lock: serializes enqueue/dequeue operations to the slot pool
  * @mmr_base: memory mapped register base
  * @chain: device chain view of the descriptors
@@ -62,7 +61,6 @@ struct iop_adma_device {
  */
 struct iop_adma_chan {
 	int pending;
-	dma_cookie_t completed_cookie;
 	spinlock_t lock; /* protects the descriptor slot pool */
 	void __iomem *mmr_base;
 	struct list_head chain;
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 8a28158..2b5121f 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -971,7 +971,7 @@ static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
 	u32 bytesleft = 0;
 
 	last_used = plchan->chan.cookie;
-	last_complete = plchan->lc;
+	last_complete = plchan->chan.completed_cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
 	if (ret == DMA_SUCCESS) {
@@ -983,7 +983,7 @@ static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
 	 * This cookie not complete yet
 	 */
 	last_used = plchan->chan.cookie;
-	last_complete = plchan->lc;
+	last_complete = plchan->chan.completed_cookie;
 
 	/* Get number of bytes left in the active transactions and queue */
 	bytesleft = pl08x_getbytes_chan(plchan);
@@ -1541,7 +1541,7 @@ static void pl08x_tasklet(unsigned long data)
 
 	if (txd) {
 		/* Update last completed */
-		plchan->lc = txd->tx.cookie;
+		plchan->chan.completed_cookie = txd->tx.cookie;
 	}
 
 	/* If a new descriptor is queued, set it up plchan->at is NULL here */
@@ -1723,7 +1723,7 @@ static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
 
 		chan->chan.device = dmadev;
 		chan->chan.cookie = 0;
-		chan->lc = 0;
+		chan->chan.completed_cookie = 0;
 
 		spin_lock_init(&chan->lock);
 		INIT_LIST_HEAD(&chan->pend_list);
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index f4aed5f..6baf5d7 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -269,7 +269,7 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
 	dev_vdbg(chan2dev(&atchan->chan_common),
 		"descriptor %u complete\n", txd->cookie);
 
-	atchan->completed_cookie = txd->cookie;
+	atchan->chan_common.completed_cookie = txd->cookie;
 
 	/* move children to free_list */
 	list_splice_init(&desc->tx_list, &atchan->free_list);
@@ -1016,14 +1016,14 @@ atc_tx_status(struct dma_chan *chan,
 
 	spin_lock_irqsave(&atchan->lock, flags);
 
-	last_complete = atchan->completed_cookie;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
 	if (ret != DMA_SUCCESS) {
 		atc_cleanup_descriptors(atchan);
 
-		last_complete = atchan->completed_cookie;
+		last_complete = chan->completed_cookie;
 		last_used = chan->cookie;
 
 		ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -1129,7 +1129,7 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
 	spin_lock_irqsave(&atchan->lock, flags);
 	atchan->descs_allocated = i;
 	list_splice(&tmp_list, &atchan->free_list);
-	atchan->completed_cookie = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 	spin_unlock_irqrestore(&atchan->lock, flags);
 
 	/* channel parameters */
@@ -1329,7 +1329,7 @@ static int __init at_dma_probe(struct platform_device *pdev)
 		struct at_dma_chan	*atchan = &atdma->chan[i];
 
 		atchan->chan_common.device = &atdma->dma_common;
-		atchan->chan_common.cookie = atchan->completed_cookie = 1;
+		atchan->chan_common.cookie = atchan->chan_common.completed_cookie = 1;
 		list_add_tail(&atchan->chan_common.device_node,
 				&atdma->dma_common.channels);
 
diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
index a8d3277..08fd8a0 100644
--- a/drivers/dma/at_hdmac_regs.h
+++ b/drivers/dma/at_hdmac_regs.h
@@ -208,7 +208,6 @@ enum atc_status {
  * @save_dscr: for cyclic operations, preserve next descriptor address in
  *             the cyclic list on suspend/resume cycle
  * @lock: serializes enqueue/dequeue operations to descriptors lists
- * @completed_cookie: identifier for the most recently completed operation
  * @active_list: list of descriptors dmaengine is being running on
  * @queue: list of descriptors ready to be submitted to engine
  * @free_list: list of descriptors usable by the channel
@@ -227,7 +226,6 @@ struct at_dma_chan {
 	spinlock_t		lock;
 
 	/* these other elements are all protected by lock */
-	dma_cookie_t		completed_cookie;
 	struct list_head	active_list;
 	struct list_head	queue;
 	struct list_head	free_list;
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index d65a718..521434b 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -59,7 +59,6 @@ struct coh901318_base {
 struct coh901318_chan {
 	spinlock_t lock;
 	int allocated;
-	int completed;
 	int id;
 	int stopped;
 
@@ -705,7 +704,7 @@ static void dma_tasklet(unsigned long data)
 	callback_param = cohd_fin->desc.callback_param;
 
 	/* sign this job as completed on the channel */
-	cohc->completed = cohd_fin->desc.cookie;
+	cohc->chan.completed_cookie = cohd_fin->desc.cookie;
 
 	/* release the lli allocation and remove the descriptor */
 	coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
@@ -929,7 +928,7 @@ static int coh901318_alloc_chan_resources(struct dma_chan *chan)
 	coh901318_config(cohc, NULL);
 
 	cohc->allocated = 1;
-	cohc->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 
 	spin_unlock_irqrestore(&cohc->lock, flags);
 
@@ -1169,7 +1168,7 @@ coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 	dma_cookie_t last_complete;
 	int ret;
 
-	last_complete = cohc->completed;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 9b592b0..defe574 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -245,7 +245,7 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 	dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 
 	spin_lock_irqsave(&dwc->lock, flags);
-	dwc->completed = txd->cookie;
+	dwc->chan.completed_cookie = txd->cookie;
 	if (callback_required) {
 		callback = txd->callback;
 		param = txd->callback_param;
@@ -955,14 +955,14 @@ dwc_tx_status(struct dma_chan *chan,
 	dma_cookie_t		last_complete;
 	int			ret;
 
-	last_complete = dwc->completed;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
 	if (ret != DMA_SUCCESS) {
 		dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 
-		last_complete = dwc->completed;
+		last_complete = chan->completed_cookie;
 		last_used = chan->cookie;
 
 		ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -1004,7 +1004,7 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
 		return -EIO;
 	}
 
-	dwc->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 
 	/*
 	 * NOTE: some controllers may have additional features that we
@@ -1423,7 +1423,7 @@ static int __init dw_probe(struct platform_device *pdev)
 		struct dw_dma_chan	*dwc = &dw->chan[i];
 
 		dwc->chan.device = &dw->dma;
-		dwc->chan.cookie = dwc->completed = 1;
+		dwc->chan.cookie = dwc->chan.completed_cookie = 1;
 		if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
 			list_add_tail(&dwc->chan.device_node,
 					&dw->dma.channels);
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index 5eef694..cce1752 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -146,7 +146,6 @@ struct dw_dma_chan {
 
 	/* these other elements are all protected by lock */
 	unsigned long		flags;
-	dma_cookie_t		completed;
 	struct list_head	active_list;
 	struct list_head	queue;
 	struct list_head	free_list;
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index 59e7a96..bc45787 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -122,7 +122,6 @@ struct ep93xx_dma_desc {
  * @lock: lock protecting the fields following
  * @flags: flags for the channel
  * @buffer: which buffer to use next (0/1)
- * @last_completed: last completed cookie value
  * @active: flattened chain of descriptors currently being processed
  * @queue: pending descriptors which are handled next
  * @free_list: list of free descriptors which can be used
@@ -157,7 +156,6 @@ struct ep93xx_dma_chan {
 #define EP93XX_DMA_IS_CYCLIC		0
 
 	int				buffer;
-	dma_cookie_t			last_completed;
 	struct list_head		active;
 	struct list_head		queue;
 	struct list_head		free_list;
@@ -703,7 +701,7 @@ static void ep93xx_dma_tasklet(unsigned long data)
 	desc = ep93xx_dma_get_active(edmac);
 	if (desc) {
 		if (desc->complete) {
-			edmac->last_completed = desc->txd.cookie;
+			edmac->chan.completed_cookie = desc->txd.cookie;
 			list_splice_init(&edmac->active, &list);
 		}
 		callback = desc->txd.callback;
@@ -861,7 +859,7 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
 		goto fail_clk_disable;
 
 	spin_lock_irq(&edmac->lock);
-	edmac->last_completed = 1;
+	edmac->chan.completed_cookie = 1;
 	edmac->chan.cookie = 1;
 	ret = edmac->edma->hw_setup(edmac);
 	spin_unlock_irq(&edmac->lock);
@@ -1254,7 +1252,7 @@ static enum dma_status ep93xx_dma_tx_status(struct dma_chan *chan,
 
 	spin_lock_irqsave(&edmac->lock, flags);
 	last_used = chan->cookie;
-	last_completed = edmac->last_completed;
+	last_completed = chan->completed_cookie;
 	spin_unlock_irqrestore(&edmac->lock, flags);
 
 	ret = dma_async_is_complete(cookie, last_completed, last_used);
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index b98070c..9b5cb8a 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -990,7 +990,7 @@ static enum dma_status fsl_tx_status(struct dma_chan *dchan,
 
 	spin_lock_irqsave(&chan->desc_lock, flags);
 
-	last_complete = chan->completed_cookie;
+	last_complete = dchan->completed_cookie;
 	last_used = dchan->cookie;
 
 	spin_unlock_irqrestore(&chan->desc_lock, flags);
@@ -1088,7 +1088,7 @@ static void dma_do_tasklet(unsigned long data)
 		desc = to_fsl_desc(chan->ld_running.prev);
 		cookie = desc->async_tx.cookie;
 
-		chan->completed_cookie = cookie;
+		chan->common.completed_cookie = cookie;
 		chan_dbg(chan, "completed_cookie=%d\n", cookie);
 	}
 
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index 9cb5aa5..f5c3879 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -137,7 +137,6 @@ struct fsldma_device {
 struct fsldma_chan {
 	char name[8];			/* Channel name */
 	struct fsldma_chan_regs __iomem *regs;
-	dma_cookie_t completed_cookie;	/* The maximum cookie completed */
 	spinlock_t desc_lock;		/* Descriptor operation lock */
 	struct list_head ld_pending;	/* Link descriptors queue */
 	struct list_head ld_running;	/* Link descriptors queue */
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index e4383ee..321fc1f 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -41,7 +41,6 @@ struct imxdma_channel {
 	struct dma_chan			chan;
 	spinlock_t			lock;
 	struct dma_async_tx_descriptor	desc;
-	dma_cookie_t			last_completed;
 	enum dma_status			status;
 	int				dma_request;
 	struct scatterlist		*sg_list;
@@ -65,7 +64,7 @@ static void imxdma_handle(struct imxdma_channel *imxdmac)
 {
 	if (imxdmac->desc.callback)
 		imxdmac->desc.callback(imxdmac->desc.callback_param);
-	imxdmac->last_completed = imxdmac->desc.cookie;
+	imxdmac->chan.completed_cookie = imxdmac->desc.cookie;
 }
 
 static void imxdma_irq_handler(int channel, void *data)
@@ -158,8 +157,8 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 
 	last_used = chan->cookie;
 
-	ret = dma_async_is_complete(cookie, imxdmac->last_completed, last_used);
-	dma_set_tx_state(txstate, imxdmac->last_completed, last_used, 0);
+	ret = dma_async_is_complete(cookie, chan->completed_cookie, last_used);
+	dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
 
 	return ret;
 }
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 8bc5acf..e857904 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -266,7 +266,6 @@ struct sdma_channel {
 	struct dma_chan			chan;
 	spinlock_t			lock;
 	struct dma_async_tx_descriptor	desc;
-	dma_cookie_t			last_completed;
 	enum dma_status			status;
 	unsigned int			chn_count;
 	unsigned int			chn_real_count;
@@ -523,7 +522,7 @@ static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 	else
 		sdmac->status = DMA_SUCCESS;
 
-	sdmac->last_completed = sdmac->desc.cookie;
+	sdmac->chan.completed_cookie = sdmac->desc.cookie;
 	if (sdmac->desc.callback)
 		sdmac->desc.callback(sdmac->desc.callback_param);
 }
@@ -1129,7 +1128,7 @@ static enum dma_status sdma_tx_status(struct dma_chan *chan,
 
 	last_used = chan->cookie;
 
-	dma_set_tx_state(txstate, sdmac->last_completed, last_used,
+	dma_set_tx_state(txstate, chan->completed_cookie, last_used,
 			sdmac->chn_count - sdmac->chn_real_count);
 
 	return sdmac->status;
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index 74f70aa..a27ae45 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -288,7 +288,7 @@ static void midc_descriptor_complete(struct intel_mid_dma_chan *midc,
 	struct intel_mid_dma_lli	*llitem;
 	void *param_txd = NULL;
 
-	midc->completed = txd->cookie;
+	midc->chan.completed_cookie = txd->cookie;
 	callback_txd = txd->callback;
 	param_txd = txd->callback_param;
 
@@ -482,12 +482,11 @@ static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
 						dma_cookie_t cookie,
 						struct dma_tx_state *txstate)
 {
-	struct intel_mid_dma_chan	*midc = to_intel_mid_dma_chan(chan);
 	dma_cookie_t		last_used;
 	dma_cookie_t		last_complete;
 	int				ret;
 
-	last_complete = midc->completed;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -496,7 +495,7 @@ static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
 		midc_scan_descriptors(to_middma_device(chan->device), midc);
 		spin_unlock_bh(&midc->lock);
 
-		last_complete = midc->completed;
+		last_complete = chan->completed_cookie;
 		last_used = chan->cookie;
 
 		ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -886,7 +885,7 @@ static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
 		pm_runtime_put(&mid->pdev->dev);
 		return -EIO;
 	}
-	midc->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 
 	spin_lock_bh(&midc->lock);
 	while (midc->descs_allocated < DESCS_PER_CHANNEL) {
diff --git a/drivers/dma/intel_mid_dma_regs.h b/drivers/dma/intel_mid_dma_regs.h
index c83d35b..1bfa926 100644
--- a/drivers/dma/intel_mid_dma_regs.h
+++ b/drivers/dma/intel_mid_dma_regs.h
@@ -165,7 +165,6 @@ union intel_mid_dma_cfg_hi {
  * @dma_base: MMIO register space DMA engine base pointer
  * @ch_id: DMA channel id
  * @lock: channel spinlock
- * @completed: DMA cookie
  * @active_list: current active descriptors
  * @queue: current queued up descriptors
  * @free_list: current free descriptors
@@ -183,7 +182,6 @@ struct intel_mid_dma_chan {
 	void __iomem		*dma_base;
 	int			ch_id;
 	spinlock_t		lock;
-	dma_cookie_t		completed;
 	struct list_head	active_list;
 	struct list_head	queue;
 	struct list_head	free_list;
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index a4d6cb0..fab440a 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -603,7 +603,7 @@ static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete)
 		 */
 		dump_desc_dbg(ioat, desc);
 		if (tx->cookie) {
-			chan->completed_cookie = tx->cookie;
+			chan->common.completed_cookie = tx->cookie;
 			tx->cookie = 0;
 			ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 			ioat->active -= desc->hw->tx_cnt;
diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h
index 5216c8a..9653b6b 100644
--- a/drivers/dma/ioat/dma.h
+++ b/drivers/dma/ioat/dma.h
@@ -90,7 +90,6 @@ struct ioat_chan_common {
 	void __iomem *reg_base;
 	unsigned long last_completion;
 	spinlock_t cleanup_lock;
-	dma_cookie_t completed_cookie;
 	unsigned long state;
 	#define IOAT_COMPLETION_PENDING 0
 	#define IOAT_COMPLETION_ACK 1
@@ -153,12 +152,11 @@ static inline enum dma_status
 ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 		 struct dma_tx_state *txstate)
 {
-	struct ioat_chan_common *chan = to_chan_common(c);
 	dma_cookie_t last_used;
 	dma_cookie_t last_complete;
 
 	last_used = c->cookie;
-	last_complete = chan->completed_cookie;
+	last_complete = c->completed_cookie;
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 
diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c
index 5d65f83..d3f0aff 100644
--- a/drivers/dma/ioat/dma_v2.c
+++ b/drivers/dma/ioat/dma_v2.c
@@ -147,7 +147,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
 		dump_desc_dbg(ioat, desc);
 		if (tx->cookie) {
 			ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
-			chan->completed_cookie = tx->cookie;
+			chan->common.completed_cookie = tx->cookie;
 			tx->cookie = 0;
 			if (tx->callback) {
 				tx->callback(tx->callback_param);
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
index f519c93..d4afac7 100644
--- a/drivers/dma/ioat/dma_v3.c
+++ b/drivers/dma/ioat/dma_v3.c
@@ -277,7 +277,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
 		dump_desc_dbg(ioat, desc);
 		tx = &desc->txd;
 		if (tx->cookie) {
-			chan->completed_cookie = tx->cookie;
+			chan->common.completed_cookie = tx->cookie;
 			ioat3_dma_unmap(ioat, desc, idx + i);
 			tx->cookie = 0;
 			if (tx->callback) {
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index 04be90b..d8027c2 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -317,7 +317,7 @@ static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
 	}
 
 	if (cookie > 0) {
-		iop_chan->completed_cookie = cookie;
+		iop_chan->common.completed_cookie = cookie;
 		pr_debug("\tcompleted cookie %d\n", cookie);
 	}
 }
@@ -909,7 +909,7 @@ static enum dma_status iop_adma_status(struct dma_chan *chan,
 	enum dma_status ret;
 
 	last_used = chan->cookie;
-	last_complete = iop_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
 	if (ret == DMA_SUCCESS)
@@ -918,7 +918,7 @@ static enum dma_status iop_adma_status(struct dma_chan *chan,
 	iop_adma_slot_cleanup(iop_chan);
 
 	last_used = chan->cookie;
-	last_complete = iop_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 
 	return dma_async_is_complete(cookie, last_complete, last_used);
@@ -1650,7 +1650,7 @@ static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
 		/* initialize the completed cookie to be less than
 		 * the most recently used cookie
 		 */
-		iop_chan->completed_cookie = cookie - 1;
+		iop_chan->common.completed_cookie = cookie - 1;
 		iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
 		/* channel should not be busy */
@@ -1707,7 +1707,7 @@ static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
 		/* initialize the completed cookie to be less than
 		 * the most recently used cookie
 		 */
-		iop_chan->completed_cookie = cookie - 1;
+		iop_chan->common.completed_cookie = cookie - 1;
 		iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
 		/* channel should not be busy */
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index 6212b16..9149ade 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -1295,7 +1295,7 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
 	/* Flip the active buffer - even if update above failed */
 	ichan->active_buffer = !ichan->active_buffer;
 	if (done)
-		ichan->completed = desc->txd.cookie;
+		ichan->dma_chan.completed_cookie = desc->txd.cookie;
 
 	callback = desc->txd.callback;
 	callback_param = desc->txd.callback_param;
@@ -1511,7 +1511,7 @@ static int idmac_alloc_chan_resources(struct dma_chan *chan)
 	WARN_ON(ichan->status != IPU_CHANNEL_FREE);
 
 	chan->cookie		= 1;
-	ichan->completed	= -ENXIO;
+	chan->completed_cookie	= -ENXIO;
 
 	ret = ipu_irq_map(chan->chan_id);
 	if (ret < 0)
@@ -1600,9 +1600,7 @@ static void idmac_free_chan_resources(struct dma_chan *chan)
 static enum dma_status idmac_tx_status(struct dma_chan *chan,
 		       dma_cookie_t cookie, struct dma_tx_state *txstate)
 {
-	struct idmac_channel *ichan = to_idmac_chan(chan);
-
-	dma_set_tx_state(txstate, ichan->completed, chan->cookie, 0);
+	dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 0);
 	if (cookie != chan->cookie)
 		return DMA_ERROR;
 	return DMA_SUCCESS;
@@ -1638,11 +1636,11 @@ static int __init ipu_idmac_init(struct ipu *ipu)
 
 		ichan->status		= IPU_CHANNEL_FREE;
 		ichan->sec_chan_en	= false;
-		ichan->completed	= -ENXIO;
 		snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
 
 		dma_chan->device	= &idmac->dma;
 		dma_chan->cookie	= 1;
+		dma_chan->completed_cookie	= -ENXIO;
 		dma_chan->chan_id	= i;
 		list_add_tail(&dma_chan->device_node, &dma->channels);
 	}
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index 4d6d4cf..39a5cde 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -188,7 +188,6 @@ struct mpc_dma_chan {
 	struct list_head		completed;
 	struct mpc_dma_tcd		*tcd;
 	dma_addr_t			tcd_paddr;
-	dma_cookie_t			completed_cookie;
 
 	/* Lock for this structure */
 	spinlock_t			lock;
@@ -365,7 +364,7 @@ static void mpc_dma_process_completed(struct mpc_dma *mdma)
 		/* Free descriptors */
 		spin_lock_irqsave(&mchan->lock, flags);
 		list_splice_tail_init(&list, &mchan->free);
-		mchan->completed_cookie = last_cookie;
+		mchan->chan.completed_cookie = last_cookie;
 		spin_unlock_irqrestore(&mchan->lock, flags);
 	}
 }
@@ -568,7 +567,7 @@ mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 
 	spin_lock_irqsave(&mchan->lock, flags);
 	last_used = mchan->chan.cookie;
-	last_complete = mchan->completed_cookie;
+	last_complete = mchan->chan.completed_cookie;
 	spin_unlock_irqrestore(&mchan->lock, flags);
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
@@ -742,7 +741,7 @@ static int __devinit mpc_dma_probe(struct platform_device *op)
 
 		mchan->chan.device = dma;
 		mchan->chan.cookie = 1;
-		mchan->completed_cookie = mchan->chan.cookie;
+		mchan->chan.completed_cookie = mchan->chan.cookie;
 
 		INIT_LIST_HEAD(&mchan->free);
 		INIT_LIST_HEAD(&mchan->prepared);
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index ad7d03f..c6a84da 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -435,7 +435,7 @@ static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
 	}
 
 	if (cookie > 0)
-		mv_chan->completed_cookie = cookie;
+		mv_chan->common.completed_cookie = cookie;
 }
 
 static void
@@ -825,7 +825,7 @@ static enum dma_status mv_xor_status(struct dma_chan *chan,
 	enum dma_status ret;
 
 	last_used = chan->cookie;
-	last_complete = mv_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -836,7 +836,7 @@ static enum dma_status mv_xor_status(struct dma_chan *chan,
 	mv_xor_slot_cleanup(mv_chan);
 
 	last_used = chan->cookie;
-	last_complete = mv_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 	return dma_async_is_complete(cookie, last_complete, last_used);
diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h
index da04ac2..654876b 100644
--- a/drivers/dma/mv_xor.h
+++ b/drivers/dma/mv_xor.h
@@ -78,7 +78,6 @@ struct mv_xor_device {
 /**
  * struct mv_xor_chan - internal representation of a XOR channel
  * @pending: allows batching of hardware operations
- * @completed_cookie: identifier for the most recently completed operation
  * @lock: serializes enqueue/dequeue operations to the descriptors pool
  * @mmr_base: memory mapped register base
  * @idx: the index of the xor channel
@@ -93,7 +92,6 @@ struct mv_xor_device {
  */
 struct mv_xor_chan {
 	int			pending;
-	dma_cookie_t		completed_cookie;
 	spinlock_t		lock; /* protects the descriptor slot pool */
 	void __iomem		*mmr_base;
 	unsigned int		idx;
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index b06cd4c..3696e6e 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -111,7 +111,6 @@ struct mxs_dma_chan {
 	struct mxs_dma_ccw		*ccw;
 	dma_addr_t			ccw_phys;
 	int				desc_count;
-	dma_cookie_t			last_completed;
 	enum dma_status			status;
 	unsigned int			flags;
 #define MXS_DMA_SG_LOOP			(1 << 0)
@@ -274,7 +273,7 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
 		stat1 &= ~(1 << channel);
 
 		if (mxs_chan->status == DMA_SUCCESS)
-			mxs_chan->last_completed = mxs_chan->desc.cookie;
+			mxs_chan->chan.completed_cookie = mxs_chan->desc.cookie;
 
 		/* schedule tasklet on this channel */
 		tasklet_schedule(&mxs_chan->tasklet);
@@ -538,7 +537,7 @@ static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
 	dma_cookie_t last_used;
 
 	last_used = chan->cookie;
-	dma_set_tx_state(txstate, mxs_chan->last_completed, last_used, 0);
+	dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
 
 	return mxs_chan->status;
 }
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index 823f581..79a7185 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -105,7 +105,6 @@ struct pch_dma_chan {
 
 	spinlock_t		lock;
 
-	dma_cookie_t		completed_cookie;
 	struct list_head	active_list;
 	struct list_head	queue;
 	struct list_head	free_list;
@@ -544,7 +543,7 @@ static int pd_alloc_chan_resources(struct dma_chan *chan)
 	spin_lock_irq(&pd_chan->lock);
 	list_splice(&tmp_list, &pd_chan->free_list);
 	pd_chan->descs_allocated = i;
-	pd_chan->completed_cookie = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 	spin_unlock_irq(&pd_chan->lock);
 
 	pdc_enable_irq(chan, 1);
@@ -583,7 +582,7 @@ static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 	int ret;
 
 	spin_lock_irq(&pd_chan->lock);
-	last_completed = pd_chan->completed_cookie;
+	last_completed = chan->completed_cookie;
 	last_used = chan->cookie;
 	spin_unlock_irq(&pd_chan->lock);
 
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index b8ec03e..bdf04f1 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -51,9 +51,6 @@ struct dma_pl330_chan {
 	/* DMA-Engine Channel */
 	struct dma_chan chan;
 
-	/* Last completed cookie */
-	dma_cookie_t completed;
-
 	/* List of to be xfered descriptors */
 	struct list_head work_list;
 
@@ -234,7 +231,7 @@ static void pl330_tasklet(unsigned long data)
 	/* Pick up ripe tomatoes */
 	list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
 		if (desc->status == DONE) {
-			pch->completed = desc->txd.cookie;
+			pch->chan.completed_cookie = desc->txd.cookie;
 			list_move_tail(&desc->node, &list);
 		}
 
@@ -305,7 +302,7 @@ static int pl330_alloc_chan_resources(struct dma_chan *chan)
 
 	spin_lock_irqsave(&pch->lock, flags);
 
-	pch->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 	pch->cyclic = false;
 
 	pch->pl330_chid = pl330_request_channel(&pdmac->pif);
@@ -400,7 +397,7 @@ pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 	dma_cookie_t last_done, last_used;
 	int ret;
 
-	last_done = pch->completed;
+	last_done = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_done, last_used);
diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c
index fc457a7..f878322 100644
--- a/drivers/dma/ppc4xx/adma.c
+++ b/drivers/dma/ppc4xx/adma.c
@@ -1930,7 +1930,7 @@ static void __ppc440spe_adma_slot_cleanup(struct ppc440spe_adma_chan *chan)
 				if (end_of_chain && slot_cnt) {
 					/* Should wait for ZeroSum completion */
 					if (cookie > 0)
-						chan->completed_cookie = cookie;
+						chan->common.completed_cookie = cookie;
 					return;
 				}
 
@@ -1960,7 +1960,7 @@ static void __ppc440spe_adma_slot_cleanup(struct ppc440spe_adma_chan *chan)
 	BUG_ON(!seen_current);
 
 	if (cookie > 0) {
-		chan->completed_cookie = cookie;
+		chan->common.completed_cookie = cookie;
 		pr_debug("\tcompleted cookie %d\n", cookie);
 	}
 
@@ -3950,7 +3950,7 @@ static enum dma_status ppc440spe_adma_tx_status(struct dma_chan *chan,
 
 	ppc440spe_chan = to_ppc440spe_adma_chan(chan);
 	last_used = chan->cookie;
-	last_complete = ppc440spe_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 
@@ -3961,7 +3961,7 @@ static enum dma_status ppc440spe_adma_tx_status(struct dma_chan *chan,
 	ppc440spe_adma_slot_cleanup(ppc440spe_chan);
 
 	last_used = chan->cookie;
-	last_complete = ppc440spe_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 
@@ -4058,7 +4058,7 @@ static void ppc440spe_chan_start_null_xor(struct ppc440spe_adma_chan *chan)
 		/* initialize the completed cookie to be less than
 		 * the most recently used cookie
 		 */
-		chan->completed_cookie = cookie - 1;
+		chan->common.completed_cookie = cookie - 1;
 		chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
 		/* channel should not be busy */
diff --git a/drivers/dma/ppc4xx/adma.h b/drivers/dma/ppc4xx/adma.h
index 8ada5a8..26b7a5e 100644
--- a/drivers/dma/ppc4xx/adma.h
+++ b/drivers/dma/ppc4xx/adma.h
@@ -81,7 +81,6 @@ struct ppc440spe_adma_device {
  * @common: common dmaengine channel object members
  * @all_slots: complete domain of slots usable by the channel
  * @pending: allows batching of hardware operations
- * @completed_cookie: identifier for the most recently completed operation
  * @slots_allocated: records the actual size of the descriptor slot pool
  * @hw_chain_inited: h/w descriptor chain initialization flag
  * @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs
@@ -99,7 +98,6 @@ struct ppc440spe_adma_chan {
 	struct list_head all_slots;
 	struct ppc440spe_adma_desc_slot *last_used;
 	int pending;
-	dma_cookie_t completed_cookie;
 	int slots_allocated;
 	int hw_chain_inited;
 	struct tasklet_struct irq_tasklet;
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index 812fd76..ae84c12 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -764,12 +764,12 @@ static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all
 			cookie = tx->cookie;
 
 		if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
-			if (sh_chan->completed_cookie != desc->cookie - 1)
+			if (sh_chan->common.completed_cookie != desc->cookie - 1)
 				dev_dbg(sh_chan->dev,
 					"Completing cookie %d, expected %d\n",
 					desc->cookie,
-					sh_chan->completed_cookie + 1);
-			sh_chan->completed_cookie = desc->cookie;
+					sh_chan->common.completed_cookie + 1);
+			sh_chan->common.completed_cookie = desc->cookie;
 		}
 
 		/* Call callback on the last chunk */
@@ -823,7 +823,7 @@ static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all
 		 * Terminating and the loop completed normally: forgive
 		 * uncompleted cookies
 		 */
-		sh_chan->completed_cookie = sh_chan->common.cookie;
+		sh_chan->common.completed_cookie = sh_chan->common.cookie;
 
 	spin_unlock_irqrestore(&sh_chan->desc_lock, flags);
 
@@ -891,7 +891,7 @@ static enum dma_status sh_dmae_tx_status(struct dma_chan *chan,
 	sh_dmae_chan_ld_cleanup(sh_chan, false);
 
 	/* First read completed cookie to avoid a skew */
-	last_complete = sh_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 	rmb();
 	last_used = chan->cookie;
 	BUG_ON(last_complete < 0);
diff --git a/drivers/dma/shdma.h b/drivers/dma/shdma.h
index 2b55a27..0b1d2c1 100644
--- a/drivers/dma/shdma.h
+++ b/drivers/dma/shdma.h
@@ -30,7 +30,6 @@ enum dmae_pm_state {
 };
 
 struct sh_dmae_chan {
-	dma_cookie_t completed_cookie;	/* The maximum cookie completed */
 	spinlock_t desc_lock;		/* Descriptor operation lock */
 	struct list_head ld_queue;	/* Link descriptors queue */
 	struct list_head ld_free;	/* Link descriptors free */
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 2333810..60473f0 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -59,7 +59,6 @@ struct sirfsoc_dma_chan {
 	struct list_head		queued;
 	struct list_head		active;
 	struct list_head		completed;
-	dma_cookie_t			completed_cookie;
 	unsigned long			happened_cyclic;
 	unsigned long			completed_cyclic;
 
@@ -208,7 +207,7 @@ static void sirfsoc_dma_process_completed(struct sirfsoc_dma *sdma)
 			/* Free descriptors */
 			spin_lock_irqsave(&schan->lock, flags);
 			list_splice_tail_init(&list, &schan->free);
-			schan->completed_cookie = last_cookie;
+			schan->chan.completed_cookie = last_cookie;
 			spin_unlock_irqrestore(&schan->lock, flags);
 		} else {
 			/* for cyclic channel, desc is always in active list */
@@ -419,7 +418,7 @@ sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 
 	spin_lock_irqsave(&schan->lock, flags);
 	last_used = schan->chan.cookie;
-	last_complete = schan->completed_cookie;
+	last_complete = schan->chan.completed_cookie;
 	spin_unlock_irqrestore(&schan->lock, flags);
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
@@ -636,7 +635,7 @@ static int __devinit sirfsoc_dma_probe(struct platform_device *op)
 
 		schan->chan.device = dma;
 		schan->chan.cookie = 1;
-		schan->completed_cookie = schan->chan.cookie;
+		schan->chan.completed_cookie = schan->chan.cookie;
 
 		INIT_LIST_HEAD(&schan->free);
 		INIT_LIST_HEAD(&schan->prepared);
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index cc5ecbc..cfca2a0 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -220,8 +220,6 @@ struct d40_base;
  *
  * @lock: A spinlock to protect this struct.
  * @log_num: The logical number, if any of this channel.
- * @completed: Starts with 1, after first interrupt it is set to dma engine's
- * current cookie.
  * @pending_tx: The number of pending transfers. Used between interrupt handler
  * and tasklet.
  * @busy: Set to true when transfer is ongoing on this channel.
@@ -250,8 +248,6 @@ struct d40_base;
 struct d40_chan {
 	spinlock_t			 lock;
 	int				 log_num;
-	/* ID of the most recent completed transfer */
-	int				 completed;
 	int				 pending_tx;
 	bool				 busy;
 	struct d40_phy_res		*phy_chan;
@@ -1357,7 +1353,7 @@ static void dma_tasklet(unsigned long data)
 		goto err;
 
 	if (!d40d->cyclic)
-		d40c->completed = d40d->txd.cookie;
+		d40c->chan.completed_cookie = d40d->txd.cookie;
 
 	/*
 	 * If terminating a channel pending_tx is set to zero.
@@ -2182,7 +2178,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 	bool is_free_phy;
 	spin_lock_irqsave(&d40c->lock, flags);
 
-	d40c->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 
 	/* If no dma configuration is set use default configuration (memcpy) */
 	if (!d40c->configured) {
@@ -2351,7 +2347,7 @@ static enum dma_status d40_tx_status(struct dma_chan *chan,
 		return -EINVAL;
 	}
 
-	last_complete = d40c->completed;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	if (d40_is_paused(d40c))
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index a6f9c16..a1d1559 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -84,7 +84,6 @@ struct timb_dma_chan {
 					especially the lists and descriptors,
 					from races between the tasklet and calls
 					from above */
-	dma_cookie_t		last_completed_cookie;
 	bool			ongoing;
 	struct list_head	active_list;
 	struct list_head	queue;
@@ -284,7 +283,7 @@ static void __td_finish(struct timb_dma_chan *td_chan)
 	else
 		iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR);
 */
-	td_chan->last_completed_cookie = txd->cookie;
+	td_chan->chan.completed_cookie = txd->cookie;
 	td_chan->ongoing = false;
 
 	callback = txd->callback;
@@ -481,7 +480,7 @@ static int td_alloc_chan_resources(struct dma_chan *chan)
 	}
 
 	spin_lock_bh(&td_chan->lock);
-	td_chan->last_completed_cookie = 1;
+	chan->completed_cookie = 1;
 	chan->cookie = 1;
 	spin_unlock_bh(&td_chan->lock);
 
@@ -523,7 +522,7 @@ static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 
 	dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
 
-	last_complete = td_chan->last_completed_cookie;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index 6122c36..a917b67 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -424,7 +424,7 @@ txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
 	dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
 		 txd->cookie, desc);
 
-	dc->completed = txd->cookie;
+	dc->chan.completed_cookie = txd->cookie;
 	callback = txd->callback;
 	param = txd->callback_param;
 
@@ -976,7 +976,7 @@ txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 	dma_cookie_t last_complete;
 	int ret;
 
-	last_complete = dc->completed;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -985,7 +985,7 @@ txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 		txx9dmac_scan_descriptors(dc);
 		spin_unlock_bh(&dc->lock);
 
-		last_complete = dc->completed;
+		last_complete = chan->completed_cookie;
 		last_used = chan->cookie;
 
 		ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -1057,7 +1057,7 @@ static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
 		return -EIO;
 	}
 
-	dc->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 
 	dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
 	txx9dmac_chan_set_SMPCHN(dc);
@@ -1186,7 +1186,7 @@ static int __init txx9dmac_chan_probe(struct platform_device *pdev)
 	dc->ddev->chan[ch] = dc;
 	dc->chan.device = &dc->dma;
 	list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
-	dc->chan.cookie = dc->completed = 1;
+	dc->chan.cookie = dc->chan.completed_cookie = 1;
 
 	if (is_dmac64(dc))
 		dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
diff --git a/drivers/dma/txx9dmac.h b/drivers/dma/txx9dmac.h
index 365d423..f5a7605 100644
--- a/drivers/dma/txx9dmac.h
+++ b/drivers/dma/txx9dmac.h
@@ -172,7 +172,6 @@ struct txx9dmac_chan {
 	spinlock_t		lock;
 
 	/* these other elements are all protected by lock */
-	dma_cookie_t		completed;
 	struct list_head	active_list;
 	struct list_head	queue;
 	struct list_head	free_list;
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
index 033f6aa..1bb134b 100644
--- a/include/linux/amba/pl08x.h
+++ b/include/linux/amba/pl08x.h
@@ -176,7 +176,6 @@ enum pl08x_dma_chan_state {
  * @runtime_addr: address for RX/TX according to the runtime config
  * @runtime_direction: current direction of this channel according to
  * runtime config
- * @lc: last completed transaction on this channel
  * @pend_list: queued transactions pending on this channel
  * @at: active transaction on this channel
  * @lock: a lock for this channel data
@@ -198,7 +197,6 @@ struct pl08x_dma_chan {
 	u32 src_cctl;
 	u32 dst_cctl;
 	enum dma_transfer_direction runtime_direction;
-	dma_cookie_t lc;
 	struct list_head pend_list;
 	struct pl08x_txd *at;
 	spinlock_t lock;
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 679b349..41d0f92 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -257,6 +257,7 @@ struct dma_chan_percpu {
  * struct dma_chan - devices supply DMA channels, clients use them
  * @device: ptr to the dma device who supplies this channel, always !%NULL
  * @cookie: last cookie value returned to client
+ * @completed_cookie: last completed cookie for this channel
  * @chan_id: channel ID for sysfs
  * @dev: class device for sysfs
  * @device_node: used to add this to the device chan list
@@ -268,6 +269,7 @@ struct dma_chan_percpu {
 struct dma_chan {
 	struct dma_device *device;
 	dma_cookie_t cookie;
+	dma_cookie_t completed_cookie;
 
 	/* sysfs */
 	int chan_id;
-- 
1.7.4.4



From linux at arm.linux.org.uk  Mon Mar  5 15:15:52 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 05 Mar 2012 20:15:52 +0000
Subject: [PATCH 3/9] dmaengine: add private header file
In-Reply-To: <20120305201411.GA17791@n2100.arm.linux.org.uk>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
Message-ID: <E1S4eK0-0000sv-87@rmk-PC.arm.linux.org.uk>

Add a local private header file to contain definitions and declarations
which should only be used by DMA engine drivers.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/amba-pl08x.c    |    2 ++
 drivers/dma/at_hdmac.c      |    1 +
 drivers/dma/coh901318.c     |    1 +
 drivers/dma/dmaengine.h     |   10 ++++++++++
 drivers/dma/dw_dmac.c       |    1 +
 drivers/dma/ep93xx_dma.c    |    2 ++
 drivers/dma/fsldma.c        |    1 +
 drivers/dma/imx-dma.c       |    2 ++
 drivers/dma/imx-sdma.c      |    2 ++
 drivers/dma/intel_mid_dma.c |    2 ++
 drivers/dma/ioat/dma.c      |    2 ++
 drivers/dma/ioat/dma_v2.c   |    2 ++
 drivers/dma/iop-adma.c      |    2 ++
 drivers/dma/ipu/ipu_idmac.c |    1 +
 drivers/dma/mpc512x_dma.c   |    2 ++
 drivers/dma/mv_xor.c        |    2 ++
 drivers/dma/mxs-dma.c       |    2 ++
 drivers/dma/pch_dma.c       |    2 ++
 drivers/dma/pl330.c         |    2 ++
 drivers/dma/ppc4xx/adma.c   |    1 +
 drivers/dma/shdma.c         |    2 ++
 drivers/dma/ste_dma40.c     |    1 +
 drivers/dma/timb_dma.c      |    2 ++
 drivers/dma/txx9dmac.c      |    2 ++
 24 files changed, 49 insertions(+), 0 deletions(-)
 create mode 100644 drivers/dma/dmaengine.h

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 2b5121f..87475cb 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -85,6 +85,8 @@
 #include <linux/slab.h>
 #include <asm/hardware/pl080.h>
 
+#include "dmaengine.h"
+
 #define DRIVER_NAME	"pl08xdmac"
 
 static struct amba_driver pl08x_amba_driver;
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 6baf5d7..ce26ba3 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -27,6 +27,7 @@
 #include <linux/of_device.h>
 
 #include "at_hdmac_regs.h"
+#include "dmaengine.h"
 
 /*
  * Glossary
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 521434b..fb0d124 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -24,6 +24,7 @@
 #include <mach/coh901318.h>
 
 #include "coh901318_lli.h"
+#include "dmaengine.h"
 
 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
 
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
new file mode 100644
index 0000000..968570d
--- /dev/null
+++ b/drivers/dma/dmaengine.h
@@ -0,0 +1,10 @@
+/*
+ * The contents of this file are private to DMA engine drivers, and is not
+ * part of the API to be used by DMA engine users.
+ */
+#ifndef DMAENGINE_H
+#define DMAENGINE_H
+
+#include <linux/dmaengine.h>
+
+#endif
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index defe574..f10dbe1 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -22,6 +22,7 @@
 #include <linux/slab.h>
 
 #include "dw_dmac_regs.h"
+#include "dmaengine.h"
 
 /*
  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index bc45787..3260198 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -28,6 +28,8 @@
 
 #include <mach/dma.h>
 
+#include "dmaengine.h"
+
 /* M2P registers */
 #define M2P_CONTROL			0x0000
 #define M2P_CONTROL_STALLINT		BIT(0)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 9b5cb8a..2ebbe57 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -35,6 +35,7 @@
 #include <linux/dmapool.h>
 #include <linux/of_platform.h>
 
+#include "dmaengine.h"
 #include "fsldma.h"
 
 #define chan_dbg(chan, fmt, arg...)					\
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 321fc1f..51251a6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -30,6 +30,8 @@
 #include <mach/dma-v1.h>
 #include <mach/hardware.h>
 
+#include "dmaengine.h"
+
 struct imxdma_channel {
 	struct imxdma_engine		*imxdma;
 	unsigned int			channel;
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index e857904..9950ec3 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -42,6 +42,8 @@
 #include <mach/dma.h>
 #include <mach/hardware.h>
 
+#include "dmaengine.h"
+
 /* SDMA registers */
 #define SDMA_H_C0PTR		0x000
 #define SDMA_H_INTR		0x004
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index a27ae45..a907dd6 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -29,6 +29,8 @@
 #include <linux/intel_mid_dma.h>
 #include <linux/module.h>
 
+#include "dmaengine.h"
+
 #define MAX_CHAN	4 /*max ch across controllers*/
 #include "intel_mid_dma_regs.h"
 
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index fab440a..dfe411b 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -40,6 +40,8 @@
 #include "registers.h"
 #include "hw.h"
 
+#include "../dmaengine.h"
+
 int ioat_pending_level = 4;
 module_param(ioat_pending_level, int, 0644);
 MODULE_PARM_DESC(ioat_pending_level,
diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c
index d3f0aff..6c1e675 100644
--- a/drivers/dma/ioat/dma_v2.c
+++ b/drivers/dma/ioat/dma_v2.c
@@ -41,6 +41,8 @@
 #include "registers.h"
 #include "hw.h"
 
+#include "../dmaengine.h"
+
 int ioat_ring_alloc_order = 8;
 module_param(ioat_ring_alloc_order, int, 0644);
 MODULE_PARM_DESC(ioat_ring_alloc_order,
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index d8027c2..650bf1e 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -36,6 +36,8 @@
 
 #include <mach/adma.h>
 
+#include "dmaengine.h"
+
 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
 #define to_iop_adma_device(dev) \
 	container_of(dev, struct iop_adma_device, common)
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index 9149ade..0fcff65 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -25,6 +25,7 @@
 
 #include <mach/ipu.h>
 
+#include "../dmaengine.h"
 #include "ipu_intern.h"
 
 #define FS_VF_IN_VALID	0x00000002
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index 39a5cde..c56b3fe 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -44,6 +44,8 @@
 
 #include <linux/random.h>
 
+#include "dmaengine.h"
+
 /* Number of DMA Transfer descriptors allocated per channel */
 #define MPC_DMA_DESCRIPTORS	64
 
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index c6a84da..ee61778 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -26,6 +26,8 @@
 #include <linux/platform_device.h>
 #include <linux/memory.h>
 #include <plat/mv_xor.h>
+
+#include "dmaengine.h"
 #include "mv_xor.h"
 
 static void mv_xor_issue_pending(struct dma_chan *chan);
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 3696e6e..daa84ee 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -28,6 +28,8 @@
 #include <mach/dma.h>
 #include <mach/common.h>
 
+#include "dmaengine.h"
+
 /*
  * NOTE: The term "PIO" throughout the mxs-dma implementation means
  * PIO mode of mxs apbh-dma and apbx-dma.  With this working mode,
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index 79a7185..2b3479d 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -25,6 +25,8 @@
 #include <linux/module.h>
 #include <linux/pch_dma.h>
 
+#include "dmaengine.h"
+
 #define DRV_NAME "pch-dma"
 
 #define DMA_CTL0_DISABLE		0x0
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index bdf04f1..d7b0af2 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -21,6 +21,8 @@
 #include <linux/scatterlist.h>
 #include <linux/of.h>
 
+#include "dmaengine.h"
+
 #define NR_DEFAULT_DESC	16
 
 enum desc_status {
diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c
index f878322..40082ec 100644
--- a/drivers/dma/ppc4xx/adma.c
+++ b/drivers/dma/ppc4xx/adma.c
@@ -46,6 +46,7 @@
 #include <asm/dcr.h>
 #include <asm/dcr-regs.h>
 #include "adma.h"
+#include "../dmaengine.h"
 
 enum ppc_adma_init_code {
 	PPC_ADMA_INIT_OK = 0,
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index ae84c12..c291433 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -30,6 +30,8 @@
 #include <linux/kdebug.h>
 #include <linux/spinlock.h>
 #include <linux/rculist.h>
+
+#include "dmaengine.h"
 #include "shdma.h"
 
 /* DMA descriptor control */
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index cfca2a0..156b98f 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -21,6 +21,7 @@
 
 #include <plat/ste_dma40.h>
 
+#include "dmaengine.h"
 #include "ste_dma40_ll.h"
 
 #define D40_NAME "dma40"
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index a1d1559..4b61879 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -31,6 +31,8 @@
 
 #include <linux/timb_dma.h>
 
+#include "dmaengine.h"
+
 #define DRIVER_NAME "timb-dma"
 
 /* Global DMA registers */
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index a917b67..db6d809 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -15,6 +15,8 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/scatterlist.h>
+
+#include "dmaengine.h"
 #include "txx9dmac.h"
 
 static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
-- 
1.7.4.4



From linux at arm.linux.org.uk  Mon Mar  5 15:16:33 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 05 Mar 2012 20:16:33 +0000
Subject: [PATCH 5/9] dmaengine: provide a common function for completing a
 dma descriptor
In-Reply-To: <20120305201411.GA17791@n2100.arm.linux.org.uk>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
Message-ID: <E1S4eKf-0000t9-11@rmk-PC.arm.linux.org.uk>

Provide a common function to do the cookie mechanics for completing
a DMA descriptor.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/amba-pl08x.c    |    2 +-
 drivers/dma/at_hdmac.c      |    2 +-
 drivers/dma/coh901318.c     |    2 +-
 drivers/dma/dmaengine.h     |   18 ++++++++++++++++++
 drivers/dma/dw_dmac.c       |    2 +-
 drivers/dma/ep93xx_dma.c    |    2 +-
 drivers/dma/fsldma.c        |    2 +-
 drivers/dma/imx-dma.c       |    2 +-
 drivers/dma/imx-sdma.c      |    2 +-
 drivers/dma/intel_mid_dma.c |    2 +-
 drivers/dma/ioat/dma.c      |    3 +--
 drivers/dma/ioat/dma_v2.c   |    3 +--
 drivers/dma/ioat/dma_v3.c   |    3 +--
 drivers/dma/ipu/ipu_idmac.c |    2 +-
 drivers/dma/mxs-dma.c       |    2 +-
 drivers/dma/pl330.c         |    2 +-
 drivers/dma/ste_dma40.c     |    2 +-
 drivers/dma/timb_dma.c      |    2 +-
 drivers/dma/txx9dmac.c      |    2 +-
 19 files changed, 36 insertions(+), 21 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 5996386..f0888c1 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -1540,7 +1540,7 @@ static void pl08x_tasklet(unsigned long data)
 
 	if (txd) {
 		/* Update last completed */
-		plchan->chan.completed_cookie = txd->tx.cookie;
+		dma_cookie_complete(&txd->tx);
 	}
 
 	/* If a new descriptor is queued, set it up plchan->at is NULL here */
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index df47e7d..b282630 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -249,7 +249,7 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
 	dev_vdbg(chan2dev(&atchan->chan_common),
 		"descriptor %u complete\n", txd->cookie);
 
-	atchan->chan_common.completed_cookie = txd->cookie;
+	dma_cookie_complete(txd);
 
 	/* move children to free_list */
 	list_splice_init(&desc->tx_list, &atchan->free_list);
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 843a1a3..24837d7 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -691,7 +691,7 @@ static void dma_tasklet(unsigned long data)
 	callback_param = cohd_fin->desc.callback_param;
 
 	/* sign this job as completed on the channel */
-	cohc->chan.completed_cookie = cohd_fin->desc.cookie;
+	dma_cookie_complete(&cohd_fin->desc);
 
 	/* release the lli allocation and remove the descriptor */
 	coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
index 7692c86..47e0997 100644
--- a/drivers/dma/dmaengine.h
+++ b/drivers/dma/dmaengine.h
@@ -5,6 +5,7 @@
 #ifndef DMAENGINE_H
 #define DMAENGINE_H
 
+#include <linux/bug.h>
 #include <linux/dmaengine.h>
 
 /**
@@ -27,4 +28,21 @@ static inline dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx)
 	return cookie;
 }
 
+/**
+ * dma_cookie_complete - complete a descriptor
+ * @tx: descriptor to complete
+ *
+ * Mark this descriptor complete by updating the channels completed
+ * cookie marker.  Zero the descriptors cookie to prevent accidental
+ * repeated completions.
+ *
+ * Note: caller is expected to hold a lock to prevent concurrency.
+ */
+static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
+{
+	BUG_ON(tx->cookie < DMA_MIN_COOKIE);
+	tx->chan->completed_cookie = tx->cookie;
+	tx->cookie = 0;
+}
+
 #endif
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 5ee9498..a190c88 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -231,7 +231,7 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 	dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 
 	spin_lock_irqsave(&dwc->lock, flags);
-	dwc->chan.completed_cookie = txd->cookie;
+	dma_cookie_complete(txd);
 	if (callback_required) {
 		callback = txd->callback;
 		param = txd->callback_param;
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index e5aaae8..1c56f75 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -703,7 +703,7 @@ static void ep93xx_dma_tasklet(unsigned long data)
 	desc = ep93xx_dma_get_active(edmac);
 	if (desc) {
 		if (desc->complete) {
-			edmac->chan.completed_cookie = desc->txd.cookie;
+			dma_cookie_complete(&desc->txd);
 			list_splice_init(&edmac->active, &list);
 		}
 		callback = desc->txd.callback;
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 04b4347..f36e8b1 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -1081,8 +1081,8 @@ static void dma_do_tasklet(unsigned long data)
 
 		desc = to_fsl_desc(chan->ld_running.prev);
 		cookie = desc->async_tx.cookie;
+		dma_cookie_complete(&desc->async_tx);
 
-		chan->common.completed_cookie = cookie;
 		chan_dbg(chan, "completed_cookie=%d\n", cookie);
 	}
 
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 42154b6..f1226ad 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -66,7 +66,7 @@ static void imxdma_handle(struct imxdma_channel *imxdmac)
 {
 	if (imxdmac->desc.callback)
 		imxdmac->desc.callback(imxdmac->desc.callback_param);
-	imxdmac->chan.completed_cookie = imxdmac->desc.cookie;
+	dma_cookie_complete(&imxdmac->desc);
 }
 
 static void imxdma_irq_handler(int channel, void *data)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 4e4f40e..4406be2 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -524,7 +524,7 @@ static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 	else
 		sdmac->status = DMA_SUCCESS;
 
-	sdmac->chan.completed_cookie = sdmac->desc.cookie;
+	dma_cookie_complete(&sdmac->desc);
 	if (sdmac->desc.callback)
 		sdmac->desc.callback(sdmac->desc.callback_param);
 }
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index dfe4396..340509e 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -290,7 +290,7 @@ static void midc_descriptor_complete(struct intel_mid_dma_chan *midc,
 	struct intel_mid_dma_lli	*llitem;
 	void *param_txd = NULL;
 
-	midc->chan.completed_cookie = txd->cookie;
+	dma_cookie_complete(txd);
 	callback_txd = txd->callback;
 	param_txd = txd->callback_param;
 
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index 5c06117..b0517c8 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -600,8 +600,7 @@ static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete)
 		 */
 		dump_desc_dbg(ioat, desc);
 		if (tx->cookie) {
-			chan->common.completed_cookie = tx->cookie;
-			tx->cookie = 0;
+			dma_cookie_complete(tx);
 			ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 			ioat->active -= desc->hw->tx_cnt;
 			if (tx->callback) {
diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c
index 17ecacb..e8e110f 100644
--- a/drivers/dma/ioat/dma_v2.c
+++ b/drivers/dma/ioat/dma_v2.c
@@ -149,8 +149,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
 		dump_desc_dbg(ioat, desc);
 		if (tx->cookie) {
 			ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
-			chan->common.completed_cookie = tx->cookie;
-			tx->cookie = 0;
+			dma_cookie_complete(tx);
 			if (tx->callback) {
 				tx->callback(tx->callback_param);
 				tx->callback = NULL;
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
index d4afac7..1bda46c 100644
--- a/drivers/dma/ioat/dma_v3.c
+++ b/drivers/dma/ioat/dma_v3.c
@@ -277,9 +277,8 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
 		dump_desc_dbg(ioat, desc);
 		tx = &desc->txd;
 		if (tx->cookie) {
-			chan->common.completed_cookie = tx->cookie;
+			dma_cookie_complete(tx);
 			ioat3_dma_unmap(ioat, desc, idx + i);
-			tx->cookie = 0;
 			if (tx->callback) {
 				tx->callback(tx->callback_param);
 				tx->callback = NULL;
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index d4620c5..bff9250 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -1289,7 +1289,7 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
 	/* Flip the active buffer - even if update above failed */
 	ichan->active_buffer = !ichan->active_buffer;
 	if (done)
-		ichan->dma_chan.completed_cookie = desc->txd.cookie;
+		dma_cookie_complete(&desc->txd);
 
 	callback = desc->txd.callback;
 	callback_param = desc->txd.callback_param;
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 4d3b6ff..5f3492e 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -262,7 +262,7 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
 		stat1 &= ~(1 << channel);
 
 		if (mxs_chan->status == DMA_SUCCESS)
-			mxs_chan->chan.completed_cookie = mxs_chan->desc.cookie;
+			dma_cookie_complete(&mxs_chan->desc);
 
 		/* schedule tasklet on this channel */
 		tasklet_schedule(&mxs_chan->tasklet);
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index ec9638b..76871b8 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -233,7 +233,7 @@ static void pl330_tasklet(unsigned long data)
 	/* Pick up ripe tomatoes */
 	list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
 		if (desc->status == DONE) {
-			pch->chan.completed_cookie = desc->txd.cookie;
+			dma_cookie_complete(&desc->txd);
 			list_move_tail(&desc->node, &list);
 		}
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 23e2edc..c246375 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1347,7 +1347,7 @@ static void dma_tasklet(unsigned long data)
 		goto err;
 
 	if (!d40d->cyclic)
-		d40c->chan.completed_cookie = d40d->txd.cookie;
+		dma_cookie_complete(&d40d->txd);
 
 	/*
 	 * If terminating a channel pending_tx is set to zero.
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index b6e83fc..1845ac9 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -285,7 +285,7 @@ static void __td_finish(struct timb_dma_chan *td_chan)
 	else
 		iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR);
 */
-	td_chan->chan.completed_cookie = txd->cookie;
+	dma_cookie_complete(txd);
 	td_chan->ongoing = false;
 
 	callback = txd->callback;
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index 66f8fca..8a5225b 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -411,7 +411,7 @@ txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
 	dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
 		 txd->cookie, desc);
 
-	dc->chan.completed_cookie = txd->cookie;
+	dma_cookie_complete(txd);
 	callback = txd->callback;
 	param = txd->callback_param;
 
-- 
1.7.4.4



From linux at arm.linux.org.uk  Mon Mar  5 15:16:53 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 05 Mar 2012 20:16:53 +0000
Subject: [PATCH 6/9] dmaengine: consolidate tx_status functions
In-Reply-To: <20120305201411.GA17791@n2100.arm.linux.org.uk>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
Message-ID: <E1S4eKz-0000tE-FB@rmk-PC.arm.linux.org.uk>

Now that we have the completed cookie in the dma_chan structure, we
can consolidate the tx_status functions by providing a function to set
the txstate structure and returning the DMA status.  We also provide
a separate helper to set the residue for cookies which are still in
progress.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/amba-pl08x.c    |   22 ++++------------------
 drivers/dma/at_hdmac.c      |   18 ++++++------------
 drivers/dma/coh901318.c     |   13 ++++---------
 drivers/dma/dmaengine.h     |   31 +++++++++++++++++++++++++++++++
 drivers/dma/dw_dmac.c       |   19 ++++---------------
 drivers/dma/ep93xx_dma.c    |    7 +------
 drivers/dma/fsldma.c        |   11 +++--------
 drivers/dma/imx-dma.c       |   11 +----------
 drivers/dma/intel_mid_dma.c |   19 +++----------------
 drivers/dma/ioat/dma.c      |    8 +++++---
 drivers/dma/ioat/dma.h      |   21 ---------------------
 drivers/dma/ioat/dma_v3.c   |    8 +++++---
 drivers/dma/iop-adma.c      |   16 +++-------------
 drivers/dma/mpc512x_dma.c   |    9 +++------
 drivers/dma/mv_xor.c        |   14 ++------------
 drivers/dma/pch_dma.c       |   11 ++---------
 drivers/dma/pl330.c         |   13 +------------
 drivers/dma/ppc4xx/adma.c   |   16 ++--------------
 drivers/dma/shdma.c         |   11 +----------
 drivers/dma/sirf-dma.c      |    9 +++------
 drivers/dma/ste_dma40.c     |   14 ++++----------
 drivers/dma/timb_dma.c      |   11 ++---------
 drivers/dma/txx9dmac.c      |   16 +++-------------
 23 files changed, 93 insertions(+), 235 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index f0888c1..2781a2b 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -964,31 +964,17 @@ static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
 		dma_cookie_t cookie, struct dma_tx_state *txstate)
 {
 	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
 	enum dma_status ret;
-	u32 bytesleft = 0;
 
-	last_used = plchan->chan.cookie;
-	last_complete = plchan->chan.completed_cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
-	if (ret == DMA_SUCCESS) {
-		dma_set_tx_state(txstate, last_complete, last_used, 0);
+	ret = dma_cookie_status(chan, cookie, txstate);
+	if (ret == DMA_SUCCESS)
 		return ret;
-	}
 
 	/*
 	 * This cookie not complete yet
+	 * Get number of bytes left in the active transactions and queue
 	 */
-	last_used = plchan->chan.cookie;
-	last_complete = plchan->chan.completed_cookie;
-
-	/* Get number of bytes left in the active transactions and queue */
-	bytesleft = pl08x_getbytes_chan(plchan);
-
-	dma_set_tx_state(txstate, last_complete, last_used,
-			 bytesleft);
+	dma_set_residue(txstate, pl08x_getbytes_chan(plchan));
 
 	if (plchan->state == PL08X_CHAN_PAUSED)
 		return DMA_PAUSED;
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index b282630..8a32974 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -996,26 +996,20 @@ atc_tx_status(struct dma_chan *chan,
 
 	spin_lock_irqsave(&atchan->lock, flags);
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret != DMA_SUCCESS) {
 		atc_cleanup_descriptors(atchan);
 
-		last_complete = chan->completed_cookie;
-		last_used = chan->cookie;
-
-		ret = dma_async_is_complete(cookie, last_complete, last_used);
+		ret = dma_cookie_status(chan, cookie, txstate);
 	}
 
+	last_complete = chan->completed_cookie;
+	last_used = chan->cookie;
+
 	spin_unlock_irqrestore(&atchan->lock, flags);
 
 	if (ret != DMA_SUCCESS)
-		dma_set_tx_state(txstate, last_complete, last_used,
-			atc_first_active(atchan)->len);
-	else
-		dma_set_tx_state(txstate, last_complete, last_used, 0);
+		dma_set_residue(txstate, atc_first_active(atchan)->len);
 
 	if (atc_chan_is_paused(atchan))
 		ret = DMA_PAUSED;
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 24837d7..f350517 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -1151,17 +1151,12 @@ coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 		 struct dma_tx_state *txstate)
 {
 	struct coh901318_chan *cohc = to_coh901318_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
-	int ret;
-
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
+	enum dma_status ret;
 
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
+	/* FIXME: should be conditional on ret != DMA_SUCCESS? */
+	dma_set_residue(txstate, coh901318_get_bytes_left(chan));
 
-	dma_set_tx_state(txstate, last_complete, last_used,
-			 coh901318_get_bytes_left(chan));
 	if (ret == DMA_IN_PROGRESS && cohc->stopped)
 		ret = DMA_PAUSED;
 
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
index 47e0997..244a2c5 100644
--- a/drivers/dma/dmaengine.h
+++ b/drivers/dma/dmaengine.h
@@ -45,4 +45,35 @@ static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
 	tx->cookie = 0;
 }
 
+/**
+ * dma_cookie_status - report cookie status
+ * @chan: dma channel
+ * @cookie: cookie we are interested in
+ * @state: dma_tx_state structure to return last/used cookies
+ *
+ * Report the status of the cookie, filling in the state structure if
+ * non-NULL.  No locking is required.
+ */
+static inline enum dma_status dma_cookie_status(struct dma_chan *chan,
+	dma_cookie_t cookie, struct dma_tx_state *state)
+{
+	dma_cookie_t used, complete;
+
+	used = chan->cookie;
+	complete = chan->complete;
+	barrier();
+	if (state) {
+		state->last = complete;
+		state->used = used;
+		state->residue = 0;
+	}
+	return dma_async_is_complete(cookie, complete, used);
+}
+
+static inline void dma_set_residue(struct dma_tx_state *state, u32 residue)
+{
+	if (state)
+		state->residue = residue;
+}
+
 #endif
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index a190c88..acc3bc0 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -937,28 +937,17 @@ dwc_tx_status(struct dma_chan *chan,
 	      struct dma_tx_state *txstate)
 {
 	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
-	dma_cookie_t		last_used;
-	dma_cookie_t		last_complete;
-	int			ret;
+	enum dma_status		ret;
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret != DMA_SUCCESS) {
 		dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 
-		last_complete = chan->completed_cookie;
-		last_used = chan->cookie;
-
-		ret = dma_async_is_complete(cookie, last_complete, last_used);
+		ret = dma_cookie_status(chan, cookie, txstate);
 	}
 
 	if (ret != DMA_SUCCESS)
-		dma_set_tx_state(txstate, last_complete, last_used,
-				dwc_first_active(dwc)->len);
-	else
-		dma_set_tx_state(txstate, last_complete, last_used, 0);
+		dma_set_residue(txstate, dwc_first_active(dwc)->len);
 
 	if (dwc->paused)
 		return DMA_PAUSED;
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index 1c56f75..142ebf0 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -1241,18 +1241,13 @@ static enum dma_status ep93xx_dma_tx_status(struct dma_chan *chan,
 					    struct dma_tx_state *state)
 {
 	struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
-	dma_cookie_t last_used, last_completed;
 	enum dma_status ret;
 	unsigned long flags;
 
 	spin_lock_irqsave(&edmac->lock, flags);
-	last_used = chan->cookie;
-	last_completed = chan->completed_cookie;
+	ret = dma_cookie_status(chan, cookie, state);
 	spin_unlock_irqrestore(&edmac->lock, flags);
 
-	ret = dma_async_is_complete(cookie, last_completed, last_used);
-	dma_set_tx_state(state, last_completed, last_used, 0);
-
 	return ret;
 }
 
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index f36e8b1..2f6c806 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -978,19 +978,14 @@ static enum dma_status fsl_tx_status(struct dma_chan *dchan,
 					struct dma_tx_state *txstate)
 {
 	struct fsldma_chan *chan = to_fsl_chan(dchan);
-	dma_cookie_t last_complete;
-	dma_cookie_t last_used;
+	enum dma_status ret;
 	unsigned long flags;
 
 	spin_lock_irqsave(&chan->desc_lock, flags);
-
-	last_complete = dchan->completed_cookie;
-	last_used = dchan->cookie;
-
+	ret = dma_cookie_status(dchan, cookie, txstate);
 	spin_unlock_irqrestore(&chan->desc_lock, flags);
 
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return ret;
 }
 
 /*----------------------------------------------------------------------------*/
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index f1226ad..ba317e6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -153,16 +153,7 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 					    dma_cookie_t cookie,
 					    struct dma_tx_state *txstate)
 {
-	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
-	dma_cookie_t last_used;
-	enum dma_status ret;
-
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, chan->completed_cookie, last_used);
-	dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
-
-	return ret;
+	return dma_cookie_status(chan, cookie, txstate);
 }
 
 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index 340509e..69ed1e6 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -477,30 +477,17 @@ static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
 						dma_cookie_t cookie,
 						struct dma_tx_state *txstate)
 {
-	dma_cookie_t		last_used;
-	dma_cookie_t		last_complete;
-	int				ret;
+	enum dma_status ret;
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret != DMA_SUCCESS) {
 		spin_lock_bh(&midc->lock);
 		midc_scan_descriptors(to_middma_device(chan->device), midc);
 		spin_unlock_bh(&midc->lock);
 
-		last_complete = chan->completed_cookie;
-		last_used = chan->cookie;
-
-		ret = dma_async_is_complete(cookie, last_complete, last_used);
+		ret = dma_cookie_status(chan, cookie, txstate);
 	}
 
-	if (txstate) {
-		txstate->last = last_complete;
-		txstate->used = last_used;
-		txstate->residue = 0;
-	}
 	return ret;
 }
 
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index b0517c8..97e100c 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -729,13 +729,15 @@ ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 {
 	struct ioat_chan_common *chan = to_chan_common(c);
 	struct ioatdma_device *device = chan->device;
+	enum dma_status ret;
 
-	if (ioat_tx_status(c, cookie, txstate) == DMA_SUCCESS)
-		return DMA_SUCCESS;
+	ret = dma_cookie_status(c, cookie, txstate);
+	if (ret == DMA_SUCCESS)
+		return ret;
 
 	device->cleanup_fn((unsigned long) c);
 
-	return ioat_tx_status(c, cookie, txstate);
+	return dma_cookie_status(c, cookie, txstate);
 }
 
 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h
index 9653b6b..c7888bc 100644
--- a/drivers/dma/ioat/dma.h
+++ b/drivers/dma/ioat/dma.h
@@ -142,27 +142,6 @@ static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
 	return container_of(chan, struct ioat_dma_chan, base);
 }
 
-/**
- * ioat_tx_status - poll the status of an ioat transaction
- * @c: channel handle
- * @cookie: transaction identifier
- * @txstate: if set, updated with the transaction state
- */
-static inline enum dma_status
-ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
-		 struct dma_tx_state *txstate)
-{
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
-
-	last_used = c->cookie;
-	last_complete = c->completed_cookie;
-
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
-	return dma_async_is_complete(cookie, last_complete, last_used);
-}
-
 /* wrapper around hardware descriptor format + additional software fields */
 
 /**
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
index 1bda46c..145eda2 100644
--- a/drivers/dma/ioat/dma_v3.c
+++ b/drivers/dma/ioat/dma_v3.c
@@ -410,13 +410,15 @@ ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 		struct dma_tx_state *txstate)
 {
 	struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
+	enum dma_status ret;
 
-	if (ioat_tx_status(c, cookie, txstate) == DMA_SUCCESS)
-		return DMA_SUCCESS;
+	ret = dma_cookie_status(c, cookie, txstate);
+	if (ret == DMA_SUCCESS)
+		return ret;
 
 	ioat3_cleanup(ioat);
 
-	return ioat_tx_status(c, cookie, txstate);
+	return dma_cookie_status(c, cookie, txstate);
 }
 
 static struct dma_async_tx_descriptor *
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index f2392d5..b1e3be08 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -894,24 +894,14 @@ static enum dma_status iop_adma_status(struct dma_chan *chan,
 					struct dma_tx_state *txstate)
 {
 	struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
-	enum dma_status ret;
-
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret == DMA_SUCCESS)
 		return ret;
 
 	iop_adma_slot_cleanup(iop_chan);
 
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return dma_cookie_status(chan, cookie, txstate);
 }
 
 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index 0253d5a..1382715 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -557,17 +557,14 @@ mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 	       struct dma_tx_state *txstate)
 {
 	struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
+	enum dma_status ret;
 	unsigned long flags;
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
 
 	spin_lock_irqsave(&mchan->lock, flags);
-	last_used = mchan->chan.cookie;
-	last_complete = mchan->chan.completed_cookie;
+	ret = dma_cookie_status(chan, cookie, txstate);
 	spin_unlock_irqrestore(&mchan->lock, flags);
 
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return ret;
 }
 
 /* Prepare descriptor for memory to memory copy */
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index d9810ce..486353e 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -810,26 +810,16 @@ static enum dma_status mv_xor_status(struct dma_chan *chan,
 					  struct dma_tx_state *txstate)
 {
 	struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
 	enum dma_status ret;
 
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret == DMA_SUCCESS) {
 		mv_xor_clean_completed_slots(mv_chan);
 		return ret;
 	}
 	mv_xor_slot_cleanup(mv_chan);
 
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return dma_cookie_status(chan, cookie, txstate);
 }
 
 static void mv_dump_xor_regs(struct mv_xor_chan *chan)
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index 5218e48..c30f63e 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -565,19 +565,12 @@ static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 				    struct dma_tx_state *txstate)
 {
 	struct pch_dma_chan *pd_chan = to_pd_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_completed;
-	int ret;
+	enum dma_status ret;
 
 	spin_lock_irq(&pd_chan->lock);
-	last_completed = chan->completed_cookie;
-	last_used = chan->cookie;
+	ret = dma_cookie_status(chan, cookie, txstate);
 	spin_unlock_irq(&pd_chan->lock);
 
-	ret = dma_async_is_complete(cookie, last_completed, last_used);
-
-	dma_set_tx_state(txstate, last_completed, last_used, 0);
-
 	return ret;
 }
 
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 76871b8..1993286 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -395,18 +395,7 @@ static enum dma_status
 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 		 struct dma_tx_state *txstate)
 {
-	struct dma_pl330_chan *pch = to_pchan(chan);
-	dma_cookie_t last_done, last_used;
-	int ret;
-
-	last_done = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_done, last_used);
-
-	dma_set_tx_state(txstate, last_done, last_used, 0);
-
-	return ret;
+	return dma_cookie_status(chan, cookie, txstate);
 }
 
 static void pl330_issue_pending(struct dma_chan *chan)
diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c
index 12e94dd..86239ea 100644
--- a/drivers/dma/ppc4xx/adma.c
+++ b/drivers/dma/ppc4xx/adma.c
@@ -3928,28 +3928,16 @@ static enum dma_status ppc440spe_adma_tx_status(struct dma_chan *chan,
 			dma_cookie_t cookie, struct dma_tx_state *txstate)
 {
 	struct ppc440spe_adma_chan *ppc440spe_chan;
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
 	enum dma_status ret;
 
 	ppc440spe_chan = to_ppc440spe_adma_chan(chan);
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret == DMA_SUCCESS)
 		return ret;
 
 	ppc440spe_adma_slot_cleanup(ppc440spe_chan);
 
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return dma_cookie_status(chan, cookie, txstate);
 }
 
 /**
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index 96d0a4f..50510ef 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -879,23 +879,14 @@ static enum dma_status sh_dmae_tx_status(struct dma_chan *chan,
 					struct dma_tx_state *txstate)
 {
 	struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
 	enum dma_status status;
 	unsigned long flags;
 
 	sh_dmae_chan_ld_cleanup(sh_chan, false);
 
-	/* First read completed cookie to avoid a skew */
-	last_complete = chan->completed_cookie;
-	rmb();
-	last_used = chan->cookie;
-	BUG_ON(last_complete < 0);
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
 	spin_lock_irqsave(&sh_chan->desc_lock, flags);
 
-	status = dma_async_is_complete(cookie, last_complete, last_used);
+	status = dma_cookie_status(chan, cookie, txstate);
 
 	/*
 	 * If we don't find cookie on the queue, it has been aborted and we have
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 7bb154a..a760d98 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -407,16 +407,13 @@ sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 {
 	struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
 	unsigned long flags;
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
+	enum dma_status ret;
 
 	spin_lock_irqsave(&schan->lock, flags);
-	last_used = schan->chan.cookie;
-	last_complete = schan->chan.completed_cookie;
+	ret = dma_cookie_status(chan, cookie, txstate);
 	spin_unlock_irqrestore(&schan->lock, flags);
 
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return ret;
 }
 
 static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index c246375..07b82e3 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2332,25 +2332,19 @@ static enum dma_status d40_tx_status(struct dma_chan *chan,
 				     struct dma_tx_state *txstate)
 {
 	struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
-	int ret;
+	enum dma_status ret;
 
 	if (d40c->phy_chan == NULL) {
 		chan_err(d40c, "Cannot read status of unallocated channel\n");
 		return -EINVAL;
 	}
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
+	ret = dma_cookie_status(chan, cookie, txstate);
+	if (ret != DMA_SUCCESS)
+		dma_set_residue(txstate, stedma40_residue(chan));
 
 	if (d40_is_paused(d40c))
 		ret = DMA_PAUSED;
-	else
-		ret = dma_async_is_complete(cookie, last_complete, last_used);
-
-	dma_set_tx_state(txstate, last_complete, last_used,
-			 stedma40_residue(chan));
 
 	return ret;
 }
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index 1845ac9..6383abb 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -513,18 +513,11 @@ static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 {
 	struct timb_dma_chan *td_chan =
 		container_of(chan, struct timb_dma_chan, chan);
-	dma_cookie_t		last_used;
-	dma_cookie_t		last_complete;
-	int			ret;
+	enum dma_status ret;
 
 	dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
-
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
+	ret = dma_cookie_status(chan, cookie, txstate);
 
 	dev_dbg(chan2dev(chan),
 		"%s: exit, ret: %d, last_complete: %d, last_used: %d\n",
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index 8a5225b..bb7b3d9 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -959,27 +959,17 @@ txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 		   struct dma_tx_state *txstate)
 {
 	struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
-	int ret;
+	enum dma_status ret;
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret != DMA_SUCCESS) {
 		spin_lock_bh(&dc->lock);
 		txx9dmac_scan_descriptors(dc);
 		spin_unlock_bh(&dc->lock);
 
-		last_complete = chan->completed_cookie;
-		last_used = chan->cookie;
-
-		ret = dma_async_is_complete(cookie, last_complete, last_used);
+		ret = dma_cookie_status(chan, cookie, txstate);
 	}
 
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
 	return ret;
 }
 
-- 
1.7.4.4



From paul at pwsan.com  Mon Mar  5 15:23:16 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 5 Mar 2012 13:23:16 -0700 (MST)
Subject: [RFC PATCH] OMAP: UART: Enable tx wakeup bit in wer
In-Reply-To: <alpine.DEB.2.00.1201251217120.5324@utopia.booyaka.com>
References: <1327412249-31575-1-git-send-email-govindraj.raja@ti.com>
 <alpine.DEB.2.00.1201251217120.5324@utopia.booyaka.com>
Message-ID: <alpine.DEB.2.00.1203051321580.1430@utopia.booyaka.com>


Hello Govindraj

Do you intend to update and repost this serial patch?  Or should someone 
else deal with it?  It would be good to get support for this additional 
wakeup bit.


- Paul


From nicolas.pitre at linaro.org  Mon Mar  5 15:24:07 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Mon, 5 Mar 2012 15:24:07 -0500 (EST)
Subject: [PATCH v2 19/28] ARM: Add fixed PCI i/o mapping
In-Reply-To: <201203011825.44049.arnd@arndb.de>
References: <1330547147-22867-1-git-send-email-robherring2@gmail.com>
 <201203011352.36067.arnd@arndb.de>
 <20120301140817.GG7363@n2100.arm.linux.org.uk>
 <201203011825.44049.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1203051520080.31242@xanadu.home>

On Thu, 1 Mar 2012, Arnd Bergmann wrote:

> For Kirkwood and Dove, an easy way out would be to extend the I/O
> space window to 2MB right away and just map both as before, but we
> can also try just using the two lower 64k windows in each and see what
> breaks, as those seem to be widely available for testing still.

The Kirkwood/Dove hardware I have may accommodate 3V PCI cards only, and 
none of the the 3V PCI cards I have make use of the I/O space.  this is 
therefore a pretty much underused feature anyway.  So I think we should 
just go ahead with the cleanup in this case.


Nicolas


From linux at arm.linux.org.uk  Mon Mar  5 15:16:12 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 05 Mar 2012 20:16:12 +0000
Subject: [PATCH 4/9] dmaengine: consolidate assignment of DMA cookies
In-Reply-To: <20120305201411.GA17791@n2100.arm.linux.org.uk>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
Message-ID: <E1S4eKK-0000t2-Tw@rmk-PC.arm.linux.org.uk>

Everyone deals with assigning DMA cookies in the same way (it's part of
the API so they should be), so lets consolidate the common code into a
helper function to avoid this duplication.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/amba-pl08x.c    |    9 +++------
 drivers/dma/at_hdmac.c      |   23 +----------------------
 drivers/dma/coh901318.c     |   20 +++-----------------
 drivers/dma/dmaengine.h     |   20 ++++++++++++++++++++
 drivers/dma/dw_dmac.c       |   17 +----------------
 drivers/dma/ep93xx_dma.c    |    9 +--------
 drivers/dma/fsldma.c        |    9 +--------
 drivers/dma/imx-dma.c       |   15 +--------------
 drivers/dma/imx-sdma.c      |   15 +--------------
 drivers/dma/intel_mid_dma.c |    9 +--------
 drivers/dma/ioat/dma.c      |    7 +------
 drivers/dma/ioat/dma_v2.c   |    8 ++------
 drivers/dma/iop-adma.c      |   14 +-------------
 drivers/dma/ipu/ipu_idmac.c |    9 +--------
 drivers/dma/mpc512x_dma.c   |    8 +-------
 drivers/dma/mv_xor.c        |   14 +-------------
 drivers/dma/mxs-dma.c       |   15 +--------------
 drivers/dma/pch_dma.c       |   16 +---------------
 drivers/dma/pl330.c         |   14 ++------------
 drivers/dma/ppc4xx/adma.c   |   19 +------------------
 drivers/dma/shdma.c         |    8 +-------
 drivers/dma/sirf-dma.c      |    8 +-------
 drivers/dma/ste_dma40.c     |   13 +++----------
 drivers/dma/timb_dma.c      |    7 +------
 drivers/dma/txx9dmac.c      |   17 +----------------
 25 files changed, 52 insertions(+), 271 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 87475cb..5996386 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -921,13 +921,10 @@ static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
 	struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
 	struct pl08x_txd *txd = to_pl08x_txd(tx);
 	unsigned long flags;
+	dma_cookie_t cookie;
 
 	spin_lock_irqsave(&plchan->lock, flags);
-
-	plchan->chan.cookie += 1;
-	if (plchan->chan.cookie < 0)
-		plchan->chan.cookie = 1;
-	tx->cookie = plchan->chan.cookie;
+	cookie = dma_cookie_assign(tx);
 
 	/* Put this onto the pending list */
 	list_add_tail(&txd->node, &plchan->pend_list);
@@ -947,7 +944,7 @@ static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	spin_unlock_irqrestore(&plchan->lock, flags);
 
-	return tx->cookie;
+	return cookie;
 }
 
 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index ce26ba3..df47e7d 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -193,27 +193,6 @@ static void atc_desc_chain(struct at_desc **first, struct at_desc **prev,
 }
 
 /**
- * atc_assign_cookie - compute and assign new cookie
- * @atchan: channel we work on
- * @desc: descriptor to assign cookie for
- *
- * Called with atchan->lock held and bh disabled
- */
-static dma_cookie_t
-atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc)
-{
-	dma_cookie_t cookie = atchan->chan_common.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	atchan->chan_common.cookie = cookie;
-	desc->txd.cookie = cookie;
-
-	return cookie;
-}
-
-/**
  * atc_dostart - starts the DMA engine for real
  * @atchan: the channel we want to start
  * @first: first descriptor in the list we want to begin with
@@ -548,7 +527,7 @@ static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
 	unsigned long		flags;
 
 	spin_lock_irqsave(&atchan->lock, flags);
-	cookie = atc_assign_cookie(atchan, desc);
+	cookie = dma_cookie_assign(tx);
 
 	if (list_empty(&atchan->active_list)) {
 		dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index fb0d124..843a1a3 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -318,20 +318,6 @@ static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
 
 	return 0;
 }
-static dma_cookie_t
-coh901318_assign_cookie(struct coh901318_chan *cohc,
-			struct coh901318_desc *cohd)
-{
-	dma_cookie_t cookie = cohc->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	cohc->chan.cookie = cookie;
-	cohd->desc.cookie = cookie;
-
-	return cookie;
-}
 
 static struct coh901318_desc *
 coh901318_desc_get(struct coh901318_chan *cohc)
@@ -966,16 +952,16 @@ coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
 						   desc);
 	struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
 	unsigned long flags;
+	dma_cookie_t cookie;
 
 	spin_lock_irqsave(&cohc->lock, flags);
-
-	tx->cookie = coh901318_assign_cookie(cohc, cohd);
+	cookie = dma_cookie_assign(tx);
 
 	coh901318_desc_queue(cohc, cohd);
 
 	spin_unlock_irqrestore(&cohc->lock, flags);
 
-	return tx->cookie;
+	return cookie;
 }
 
 static struct dma_async_tx_descriptor *
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
index 968570d..7692c86 100644
--- a/drivers/dma/dmaengine.h
+++ b/drivers/dma/dmaengine.h
@@ -7,4 +7,24 @@
 
 #include <linux/dmaengine.h>
 
+/**
+ * dma_cookie_assign - assign a DMA engine cookie to the descriptor
+ * @tx: descriptor needing cookie
+ *
+ * Assign a unique non-zero per-channel cookie to the descriptor.
+ * Note: caller is expected to hold a lock to prevent concurrency.
+ */
+static inline dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx)
+{
+	struct dma_chan *chan = tx->chan;
+	dma_cookie_t cookie;
+
+	cookie = chan->cookie + 1;
+	if (cookie < DMA_MIN_COOKIE)
+		cookie = DMA_MIN_COOKIE;
+	tx->cookie = chan->cookie = cookie;
+
+	return cookie;
+}
+
 #endif
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index f10dbe1..5ee9498 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -152,21 +152,6 @@ static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 	}
 }
 
-/* Called with dwc->lock held and bh disabled */
-static dma_cookie_t
-dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc)
-{
-	dma_cookie_t cookie = dwc->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	dwc->chan.cookie = cookie;
-	desc->txd.cookie = cookie;
-
-	return cookie;
-}
-
 static void dwc_initialize(struct dw_dma_chan *dwc)
 {
 	struct dw_dma *dw = to_dw_dma(dwc->chan.device);
@@ -616,7 +601,7 @@ static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 	unsigned long		flags;
 
 	spin_lock_irqsave(&dwc->lock, flags);
-	cookie = dwc_assign_cookie(dwc, desc);
+	cookie = dma_cookie_assign(tx);
 
 	/*
 	 * REVISIT: We should attempt to chain as many descriptors as
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index 3260198..e5aaae8 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -783,17 +783,10 @@ static dma_cookie_t ep93xx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 	unsigned long flags;
 
 	spin_lock_irqsave(&edmac->lock, flags);
-
-	cookie = edmac->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
+	cookie = dma_cookie_assign(tx);
 
 	desc = container_of(tx, struct ep93xx_dma_desc, txd);
 
-	edmac->chan.cookie = cookie;
-	desc->txd.cookie = cookie;
-
 	/*
 	 * If nothing is currently prosessed, we push this descriptor
 	 * directly to the hardware. Otherwise we put the descriptor
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 2ebbe57..04b4347 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -414,17 +414,10 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 	 * assign cookies to all of the software descriptors
 	 * that make up this transaction
 	 */
-	cookie = chan->common.cookie;
 	list_for_each_entry(child, &desc->tx_list, node) {
-		cookie++;
-		if (cookie < DMA_MIN_COOKIE)
-			cookie = DMA_MIN_COOKIE;
-
-		child->async_tx.cookie = cookie;
+		cookie = dma_cookie_assign(&child->async_tx);
 	}
 
-	chan->common.cookie = cookie;
-
 	/* put this transaction onto the tail of the pending queue */
 	append_ld_queue(chan, desc);
 
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 51251a6..42154b6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -165,19 +165,6 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 	return ret;
 }
 
-static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma)
-{
-	dma_cookie_t cookie = imxdma->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	imxdma->chan.cookie = cookie;
-	imxdma->desc.cookie = cookie;
-
-	return cookie;
-}
-
 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
@@ -185,7 +172,7 @@ static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	spin_lock_irq(&imxdmac->lock);
 
-	cookie = imxdma_assign_cookie(imxdmac);
+	cookie = dma_cookie_assign(tx);
 
 	imx_dma_enable(imxdmac->imxdma_channel);
 
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 9950ec3..4e4f40e 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -817,19 +817,6 @@ static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 	__raw_writel(1 << channel, sdma->regs + SDMA_H_START);
 }
 
-static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
-{
-	dma_cookie_t cookie = sdmac->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	sdmac->chan.cookie = cookie;
-	sdmac->desc.cookie = cookie;
-
-	return cookie;
-}
-
 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 {
 	return container_of(chan, struct sdma_channel, chan);
@@ -844,7 +831,7 @@ static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	spin_lock_irqsave(&sdmac->lock, flags);
 
-	cookie = sdma_assign_cookie(sdmac);
+	cookie = dma_cookie_assign(tx);
 
 	sdma_enable_channel(sdma, sdmac->channel);
 
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index a907dd6..dfe4396 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -436,14 +436,7 @@ static dma_cookie_t intel_mid_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 	dma_cookie_t		cookie;
 
 	spin_lock_bh(&midc->lock);
-	cookie = midc->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	midc->chan.cookie = cookie;
-	desc->txd.cookie = cookie;
-
+	cookie = dma_cookie_assign(tx);
 
 	if (list_empty(&midc->active_list))
 		list_add_tail(&desc->desc_node, &midc->active_list);
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index dfe411b..5c06117 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -237,12 +237,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	spin_lock_bh(&ioat->desc_lock);
 	/* cookie incr and addition to used_list must be atomic */
-	cookie = c->cookie;
-	cookie++;
-	if (cookie < 0)
-		cookie = 1;
-	c->cookie = cookie;
-	tx->cookie = cookie;
+	cookie = dma_cookie_assign(tx);
 	dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 
 	/* write address into NextDescriptor field of last desc in chain */
diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c
index 6c1e675..17ecacb 100644
--- a/drivers/dma/ioat/dma_v2.c
+++ b/drivers/dma/ioat/dma_v2.c
@@ -400,13 +400,9 @@ static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
 	struct dma_chan *c = tx->chan;
 	struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 	struct ioat_chan_common *chan = &ioat->base;
-	dma_cookie_t cookie = c->cookie;
+	dma_cookie_t cookie;
 
-	cookie++;
-	if (cookie < 0)
-		cookie = 1;
-	tx->cookie = cookie;
-	c->cookie = cookie;
+	cookie = dma_cookie_assign(tx);
 	dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 
 	if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index 650bf1e..f2392d5 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -440,18 +440,6 @@ iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
 	return NULL;
 }
 
-static dma_cookie_t
-iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
-	struct iop_adma_desc_slot *desc)
-{
-	dma_cookie_t cookie = iop_chan->common.cookie;
-	cookie++;
-	if (cookie < 0)
-		cookie = 1;
-	iop_chan->common.cookie = desc->async_tx.cookie = cookie;
-	return cookie;
-}
-
 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
 {
 	dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
@@ -479,7 +467,7 @@ iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
 	slots_per_op = grp_start->slots_per_op;
 
 	spin_lock_bh(&iop_chan->lock);
-	cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
+	cookie = dma_cookie_assign(tx);
 
 	old_chain_tail = list_entry(iop_chan->chain.prev,
 		struct iop_adma_desc_slot, chain_node);
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index 0fcff65..d4620c5 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -867,14 +867,7 @@ static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
 
-	cookie = ichan->dma_chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	/* from dmaengine.h: "last cookie value returned to client" */
-	ichan->dma_chan.cookie = cookie;
-	tx->cookie = cookie;
+	cookie = dma_cookie_assign(tx);
 
 	/* ipu->lock can be taken under ichan->lock, but not v.v. */
 	spin_lock_irqsave(&ichan->lock, flags);
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index c56b3fe..0253d5a 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -439,13 +439,7 @@ static dma_cookie_t mpc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
 		mpc_dma_execute(mchan);
 
 	/* Update cookie */
-	cookie = mchan->chan.cookie + 1;
-	if (cookie <= 0)
-		cookie = 1;
-
-	mchan->chan.cookie = cookie;
-	mdesc->desc.cookie = cookie;
-
+	cookie = dma_cookie_assign(txd);
 	spin_unlock_irqrestore(&mchan->lock, flags);
 
 	return cookie;
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index ee61778..d9810ce 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -536,18 +536,6 @@ mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots,
 	return NULL;
 }
 
-static dma_cookie_t
-mv_desc_assign_cookie(struct mv_xor_chan *mv_chan,
-		      struct mv_xor_desc_slot *desc)
-{
-	dma_cookie_t cookie = mv_chan->common.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-	mv_chan->common.cookie = desc->async_tx.cookie = cookie;
-	return cookie;
-}
-
 /************************ DMA engine API functions ****************************/
 static dma_cookie_t
 mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
@@ -565,7 +553,7 @@ mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
 	grp_start = sw_desc->group_head;
 
 	spin_lock_bh(&mv_chan->lock);
-	cookie = mv_desc_assign_cookie(mv_chan, sw_desc);
+	cookie = dma_cookie_assign(tx);
 
 	if (list_empty(&mv_chan->chain))
 		list_splice_init(&sw_desc->tx_list, &mv_chan->chain);
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index daa84ee..4d3b6ff 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -194,19 +194,6 @@ static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
 	mxs_chan->status = DMA_IN_PROGRESS;
 }
 
-static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan)
-{
-	dma_cookie_t cookie = mxs_chan->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	mxs_chan->chan.cookie = cookie;
-	mxs_chan->desc.cookie = cookie;
-
-	return cookie;
-}
-
 static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
 {
 	return container_of(chan, struct mxs_dma_chan, chan);
@@ -218,7 +205,7 @@ static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	mxs_dma_enable_chan(mxs_chan);
 
-	return mxs_dma_assign_cookie(mxs_chan);
+	return dma_cookie_assign(tx);
 }
 
 static void mxs_dma_tasklet(unsigned long data)
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index 2b3479d..5218e48 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -417,20 +417,6 @@ static void pdc_advance_work(struct pch_dma_chan *pd_chan)
 	}
 }
 
-static dma_cookie_t pdc_assign_cookie(struct pch_dma_chan *pd_chan,
-				      struct pch_dma_desc *desc)
-{
-	dma_cookie_t cookie = pd_chan->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	pd_chan->chan.cookie = cookie;
-	desc->txd.cookie = cookie;
-
-	return cookie;
-}
-
 static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd)
 {
 	struct pch_dma_desc *desc = to_pd_desc(txd);
@@ -438,7 +424,7 @@ static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd)
 	dma_cookie_t cookie;
 
 	spin_lock(&pd_chan->lock);
-	cookie = pdc_assign_cookie(pd_chan, desc);
+	cookie = dma_cookie_assign(txd);
 
 	if (list_empty(&pd_chan->active_list)) {
 		list_add_tail(&desc->desc_node, &pd_chan->active_list);
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index d7b0af2..ec9638b 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -429,26 +429,16 @@ static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
 	spin_lock_irqsave(&pch->lock, flags);
 
 	/* Assign cookies to all nodes */
-	cookie = tx->chan->cookie;
-
 	while (!list_empty(&last->node)) {
 		desc = list_entry(last->node.next, struct dma_pl330_desc, node);
 
-		if (++cookie < 0)
-			cookie = 1;
-		desc->txd.cookie = cookie;
+		dma_cookie_assign(&desc->txd);
 
 		list_move_tail(&desc->node, &pch->work_list);
 	}
 
-	if (++cookie < 0)
-		cookie = 1;
-	last->txd.cookie = cookie;
-
+	cookie = dma_cookie_assign(&last->txd);
 	list_add_tail(&last->node, &pch->work_list);
-
-	tx->chan->cookie = cookie;
-
 	spin_unlock_irqrestore(&pch->lock, flags);
 
 	return cookie;
diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c
index 40082ec..12e94dd 100644
--- a/drivers/dma/ppc4xx/adma.c
+++ b/drivers/dma/ppc4xx/adma.c
@@ -2151,22 +2151,6 @@ static int ppc440spe_adma_alloc_chan_resources(struct dma_chan *chan)
 }
 
 /**
- * ppc440spe_desc_assign_cookie - assign a cookie
- */
-static dma_cookie_t ppc440spe_desc_assign_cookie(
-		struct ppc440spe_adma_chan *chan,
-		struct ppc440spe_adma_desc_slot *desc)
-{
-	dma_cookie_t cookie = chan->common.cookie;
-
-	cookie++;
-	if (cookie < 0)
-		cookie = 1;
-	chan->common.cookie = desc->async_tx.cookie = cookie;
-	return cookie;
-}
-
-/**
  * ppc440spe_rxor_set_region_data -
  */
 static void ppc440spe_rxor_set_region(struct ppc440spe_adma_desc_slot *desc,
@@ -2236,8 +2220,7 @@ static dma_cookie_t ppc440spe_adma_tx_submit(struct dma_async_tx_descriptor *tx)
 	slots_per_op = group_start->slots_per_op;
 
 	spin_lock_bh(&chan->lock);
-
-	cookie = ppc440spe_desc_assign_cookie(chan, sw_desc);
+	cookie = dma_cookie_assign(tx);
 
 	if (unlikely(list_empty(&chan->chain))) {
 		/* first peer */
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index c291433..96d0a4f 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -298,13 +298,7 @@ static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
 	else
 		power_up = false;
 
-	cookie = sh_chan->common.cookie;
-	cookie++;
-	if (cookie < 0)
-		cookie = 1;
-
-	sh_chan->common.cookie = cookie;
-	tx->cookie = cookie;
+	cookie = dma_cookie_assign(tx);
 
 	/* Mark all chunks of this descriptor as submitted, move to the queue */
 	list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 60473f0..7bb154a 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -257,13 +257,7 @@ static dma_cookie_t sirfsoc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
 	/* Move descriptor to queue */
 	list_move_tail(&sdesc->node, &schan->queued);
 
-	/* Update cookie */
-	cookie = schan->chan.cookie + 1;
-	if (cookie <= 0)
-		cookie = 1;
-
-	schan->chan.cookie = cookie;
-	sdesc->desc.cookie = cookie;
+	cookie = dma_cookie_assign(txd);
 
 	spin_unlock_irqrestore(&schan->lock, flags);
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 156b98f..23e2edc 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1220,21 +1220,14 @@ static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
 					     chan);
 	struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
 	unsigned long flags;
+	dma_cookie_t cookie;
 
 	spin_lock_irqsave(&d40c->lock, flags);
-
-	d40c->chan.cookie++;
-
-	if (d40c->chan.cookie < 0)
-		d40c->chan.cookie = 1;
-
-	d40d->txd.cookie = d40c->chan.cookie;
-
+	cookie = dma_cookie_assign(tx);
 	d40_desc_queue(d40c, d40d);
-
 	spin_unlock_irqrestore(&d40c->lock, flags);
 
-	return tx->cookie;
+	return cookie;
 }
 
 static int d40_start(struct d40_chan *d40c)
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index 4b61879..b6e83fc 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -350,12 +350,7 @@ static dma_cookie_t td_tx_submit(struct dma_async_tx_descriptor *txd)
 	dma_cookie_t cookie;
 
 	spin_lock_bh(&td_chan->lock);
-
-	cookie = txd->chan->cookie;
-	if (++cookie < 0)
-		cookie = 1;
-	txd->chan->cookie = cookie;
-	txd->cookie = cookie;
+	cookie = dma_cookie_assign(txd);
 
 	if (list_empty(&td_chan->active_list)) {
 		dev_dbg(chan2dev(txd->chan), "%s: started %u\n", __func__,
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index db6d809..66f8fca 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -281,21 +281,6 @@ static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
 	}
 }
 
-/* Called with dc->lock held and bh disabled */
-static dma_cookie_t
-txx9dmac_assign_cookie(struct txx9dmac_chan *dc, struct txx9dmac_desc *desc)
-{
-	dma_cookie_t cookie = dc->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	dc->chan.cookie = cookie;
-	desc->txd.cookie = cookie;
-
-	return cookie;
-}
-
 /*----------------------------------------------------------------------*/
 
 static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
@@ -740,7 +725,7 @@ static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
 	dma_cookie_t cookie;
 
 	spin_lock_bh(&dc->lock);
-	cookie = txx9dmac_assign_cookie(dc, desc);
+	cookie = dma_cookie_assign(tx);
 
 	dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
 		 desc->txd.cookie, desc);
-- 
1.7.4.4



From nico at fluxnic.net  Mon Mar  5 15:29:30 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 15:29:30 -0500 (EST)
Subject: [PATCH 1/2] ARM: Add Kconfig option to use mkimage -T
 kernel_noload
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17BE861683@HQMAIL01.nvidia.com>
References: <1330473804-23348-1-git-send-email-swarren@nvidia.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861683@HQMAIL01.nvidia.com>
Message-ID: <alpine.LFD.2.02.1203051525490.31242@xanadu.home>

On Thu, 1 Mar 2012, Stephen Warren wrote:

> Stephen Warren wrote at Tuesday, February 28, 2012 5:03 PM:
> > uImage files typically encode a single absolute load and entry address.
> > This is inconvenient when attempting to share that uImage across multiple
> > SoCs with different physical RAM addresses. Recent versions of mkimage
> > implement a "kernel_noload" image type which encodes no absolute load
> > address, and a relative entry address. This works well for uImage-wrapped
> > ARM zImages, since they are relocatable.
> > 
> > This is enabled by commit b9b50e89d317c58becd0e2d7fac2e21e3a81dd0a
> > "image: Implement IH_TYPE_KERNEL_NOLOAD" in U-Boot.
> 
> So Russell, are you NAKing this patch then?
> 
> If so, I guess I'll just go and add more cruft to my copy-a-kernel-to-
> an-sd-card script. Which is a pity since every other person will have
> to do the same, but oh well.

What about moving all the u-Boot bells and whistles to a generic 
top-level Kconfig+Makefile to be shared with all architectures?  Really, 
there is nothing very ARM specific here.


Nicolas


From jason at lakedaemon.net  Mon Mar  5 15:29:41 2012
From: jason at lakedaemon.net (Jason)
Date: Mon, 5 Mar 2012 15:29:41 -0500
Subject: [PULL REQUEST v2] ARM: kirkwood: fdt: convert kirkwood init
 funcs to fdt
In-Reply-To: <201203052016.26949.arnd@arndb.de>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <alpine.LFD.2.02.1203051344130.31242@xanadu.home>
 <20120305191546.GK5050@titan.lakedaemon.net>
 <201203052016.26949.arnd@arndb.de>
Message-ID: <20120305202941.GN5050@titan.lakedaemon.net>

On Mon, Mar 05, 2012 at 08:16:26PM +0000, Arnd Bergmann wrote:
> On Monday 05 March 2012, Jason wrote:
> > > 
> > > The clock frequency part being hardcoded to 200000 in the common .dtsi 
> > > file looks wrong.  The clock may differ, and it used to (and should) be 
> > > probed at run time, please see kirkwood_find_tclk().
> > 
> > So, should I EXPORT_SYMBOL_GPL(kirkwood_find_tclk); and have each driver
> > call it?
> 
> If the drivers want to use it, I think it has to be orion_find_tclk for
> drivers that are shared between multiple plat-orion platforms.

That's pretty much all of them  :-)

I'll rename it and move it to plat-orion/common.c.  This'll be fun.

> > One alternate idea I had was to have kirkwood-dreamplug.dts root hold
> > 
> > tclk: clock-frequency = <200000000>;
> > 
> > and then have the drivers ask for it.  afaict, tclk is constant per
> > board.
> > 
> > I'm fine with either way, but I'd rather have it in the dt.
> 
> IMHO it's best to leave any such hacks out of the device tree for
> now, until we have the proper clk bindings in place for kirkwood,
> and then we can just use those.

Ok.

thx,

Jason.


From broonie at opensource.wolfsonmicro.com  Mon Mar  5 15:36:32 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 20:36:32 +0000
Subject: [PATCH v2 01/17] ASoC: imx: move eukrea audmux call into ASoC
 machine driver
In-Reply-To: <CAKGA1b=4X+ccQXjZVa1DYpRYC0NT0A9AqwgG-ApkzboRkC3sJg@mail.gmail.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-2-git-send-email-shawn.guo@linaro.org>
 <20120305174612.GY3224@opensource.wolfsonmicro.com>
 <CAKGA1b=4X+ccQXjZVa1DYpRYC0NT0A9AqwgG-ApkzboRkC3sJg@mail.gmail.com>
Message-ID: <20120305203631.GB3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 11:55:07AM -0600, Matt Sealey wrote:
> How will this stand up to an machine audio fabric that, like

"This" would be a lot more meaningful if you'd included some context
in your reply so the reader could tell what you were talking about.

> imx-sgtl5000 going around BSPs and Linaro and so on since the dawn of
> time, supports multiple boards but very different audmux
> configurations? Is this just a stopgap until the DT properly describes
> it?

What are the limitations which you see in the new code?
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From nicolas.pitre at linaro.org  Mon Mar  5 15:43:42 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Mon, 5 Mar 2012 15:43:42 -0500 (EST)
Subject: [PULL REQUEST v2] ARM: kirkwood: fdt: convert kirkwood init
 funcs to fdt
In-Reply-To: <20120305202941.GN5050@titan.lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <alpine.LFD.2.02.1203051344130.31242@xanadu.home>
 <20120305191546.GK5050@titan.lakedaemon.net>
 <201203052016.26949.arnd@arndb.de>
 <20120305202941.GN5050@titan.lakedaemon.net>
Message-ID: <alpine.LFD.2.02.1203051542190.31242@xanadu.home>

On Mon, 5 Mar 2012, Jason wrote:

> On Mon, Mar 05, 2012 at 08:16:26PM +0000, Arnd Bergmann wrote:
> > On Monday 05 March 2012, Jason wrote:
> > > > 
> > > > The clock frequency part being hardcoded to 200000 in the common .dtsi 
> > > > file looks wrong.  The clock may differ, and it used to (and should) be 
> > > > probed at run time, please see kirkwood_find_tclk().
> > > 
> > > So, should I EXPORT_SYMBOL_GPL(kirkwood_find_tclk); and have each driver
> > > call it?
> > 
> > If the drivers want to use it, I think it has to be orion_find_tclk for
> > drivers that are shared between multiple plat-orion platforms.
> 
> That's pretty much all of them  :-)
> 
> I'll rename it and move it to plat-orion/common.c.  This'll be fun.

No no...  This is not a function which is generic at all.  The _result_ 
i.e. core clock frequency value is a generic thing, not the method to 
determine it.


Nicolas


From broonie at opensource.wolfsonmicro.com  Mon Mar  5 15:44:56 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 5 Mar 2012 20:44:56 +0000
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <CAKGA1bn7y8xQn-o=8CZj5nwcvaBvHwxqM0Q2wzFAwJsSgi1sfA@mail.gmail.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
 <20120305174232.GA3852@pengutronix.de>
 <CAKGA1bn7y8xQn-o=8CZj5nwcvaBvHwxqM0Q2wzFAwJsSgi1sfA@mail.gmail.com>
Message-ID: <20120305204456.GC3224@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 12:09:13PM -0600, Matt Sealey wrote:
> There is in the BSP but the BSP driver is trying to be way too fancy
> with I2S settings on the imx-ssi driver you wrote (it works well for
> AC97, but for SSI in I2S slave mode there are so many hacks upon hacks
> "they" have presented, it'd never mainline)

I'm really having a very hard time comprehending this paragraph, and
indeed much of the rest of your mail.  The lack of any context isn't
helping here...  There is what exactly in the BSP?

> codec config. In theory the playback and capture should be serialized
> by the driver, though, right? It wouldn't be possible to be a slave to

That would be *really* bad, simultaneous playback and record is very
widely used.

> the codec if it had to run the clock two different rates at the same
> time.. app1 sends a sample buffer, codec does dma, app2 requests
> capture buffer, codec does dma, they can't happen at the same time,
> maybe we are missing an important mutex or spinlock here that would
> enforce this and stop the configuration changing mid-stream.. I'm far
> from the ALSA expert though)

If the hardware has constraints on the sample rates the driver should be
telling the application about this.  For the very common case where you
need the same rate for playback and record there's framework support for
doing this, the relevant driver just needs to set the symmetric_rates
flag and the core will do everything.  Note that the ALSA APIs are racy
here.
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From linus.walleij at linaro.org  Mon Mar  5 15:50:51 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 5 Mar 2012 21:50:51 +0100
Subject: [PATCH 0/9] DMA engine cookie handling cleanups
In-Reply-To: <20120305201411.GA17791@n2100.arm.linux.org.uk>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
Message-ID: <CACRpkda9R3c0dt95w0N7Fe5es16CqbWtsCKMaFq-nwSYV4bk-w@mail.gmail.com>

On Mon, Mar 5, 2012 at 9:14 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:

> This patch series cleans up the handling of cookies in DMA engine drivers.
> This is done by providing a set of inline library functions for common
> tasks:

Overall this looks good, but I have a problem:
patch [1/9] does not appear in any subscribed accounts (it may be on
my @stericsson.com address, will check tomorrow)

One I get hold of an ungmangled copy I can test the series on
ux500 and U300.

Is it just stuck in moderation because of size or something like that?

Yours,
Linus Walleij


From tony at atomide.com  Mon Mar  5 15:51:49 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 12:51:49 -0800
Subject: [PATCH] omap3_beagle: Init only uart3 used for console
In-Reply-To: <87399mkecv.fsf@ti.com>
References: <1330945952-14714-1-git-send-email-govindraj.raja@ti.com>
 <87399mkecv.fsf@ti.com>
Message-ID: <20120305205149.GS12083@atomide.com>

* Kevin Hilman <khilman at ti.com> [120305 11:28]:
> "Govindraj.R" <govindraj.raja at ti.com> writes:
> 
> > From: "Govindraj.R" <govindraj.raja at ti.com>
> >
> > On beagle some of uart mux lines are used for other
> > purpose so init only uart3.
> 
> OK, but you should also be clear that this patch is effectively
> disabling all UARTS (except UART3) by defatul, which I'm not sure all
> Beagle users will be happy about.
> 
> > Uart2 rx line clashes with gpio_147 used for usb ehci
> > phy reset. Initializing uart2 pad_mux lines can break
> > ehci module on beagle xm.
> > (gpio_147 is available on uart2_rx in mode4 reference 
> > mux34xx.c -> uart2_rx.gpio_147)
> 
> As Koen mentioned, this conflict only exists on certain boards, so
> you should be clear that this is just an example.

OK, thanks for the comments. Also it's a bit clear if
this really is safe to do on all beagles.
 
> > Cc: Tony Lindgren <tony at atomide.com>
> > Cc: Kevin Hilman <khilman at ti.com>
> > Tested-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> > Tested-by: Robert Nelson <robertcnelson at gmail.com>
> > Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
> 
> [...]
> 
> > +
> > +static inline void board_serial_init(void)
> 
> Should be __init
> 
> [...]
> 
> > +static inline void board_serial_init(void)
> 
> here too.

..so dropping the patch for now until these are fixed
and we have some tested-bys for non-xm beagles too.

Regards,

Tony


From tony at atomide.com  Mon Mar  5 15:52:33 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 12:52:33 -0800
Subject: [PATCH] ARM: OMAP2+: omap_device: call all suspend, resume
 callbacks when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set
In-Reply-To: <alpine.DEB.2.00.1203051312390.1430@utopia.booyaka.com>
References: <alpine.DEB.2.00.1203031314050.10611@utopia.booyaka.com>
 <877gyzoyyk.fsf@ti.com>
 <alpine.DEB.2.00.1203051312390.1430@utopia.booyaka.com>
Message-ID: <20120305205233.GT12083@atomide.com>

* Paul Walmsley <paul at pwsan.com> [120305 11:44]:
> On Mon, 5 Mar 2012, Kevin Hilman wrote:
> 
> > Tony, this fix is needed for v3.3.
> 
> Of course, I don't have any objection to this patch going into the v3.3-rc 
> kernels.  But given that some maintainers seem to be pushing back against 
> late -rc patches, this one could probably be delayed to 3.4 if required.  
> no_console_suspend is a debugging-only option and bugs involving it are 
> unlikely to affect most users.

I'm fine with your queueing it for v3.4 merge window.

Regards,

Tomny


From linux at arm.linux.org.uk  Mon Mar  5 15:58:41 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 5 Mar 2012 20:58:41 +0000
Subject: [PATCH 0/9] DMA engine cookie handling cleanups
In-Reply-To: <CACRpkda9R3c0dt95w0N7Fe5es16CqbWtsCKMaFq-nwSYV4bk-w@mail.gmail.com>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
 <CACRpkda9R3c0dt95w0N7Fe5es16CqbWtsCKMaFq-nwSYV4bk-w@mail.gmail.com>
Message-ID: <20120305205841.GB17791@n2100.arm.linux.org.uk>

On Mon, Mar 05, 2012 at 09:50:51PM +0100, Linus Walleij wrote:
> On Mon, Mar 5, 2012 at 9:14 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> 
> > This patch series cleans up the handling of cookies in DMA engine drivers.
> > This is done by providing a set of inline library functions for common
> > tasks:
> 
> Overall this looks good, but I have a problem:
> patch [1/9] does not appear in any subscribed accounts (it may be on
> my @stericsson.com address, will check tomorrow)

Patch 1 is just a couple of line changes to mv_xor.[ch]


From timur at freescale.com  Mon Mar  5 16:08:06 2012
From: timur at freescale.com (Timur Tabi)
Date: Mon, 5 Mar 2012 15:08:06 -0600
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120305204456.GC3224@opensource.wolfsonmicro.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
 <20120305174232.GA3852@pengutronix.de>
 <CAKGA1bn7y8xQn-o=8CZj5nwcvaBvHwxqM0Q2wzFAwJsSgi1sfA@mail.gmail.com>
 <20120305204456.GC3224@opensource.wolfsonmicro.com>
Message-ID: <4F552B36.9020708@freescale.com>

Mark Brown wrote:

> That would be *really* bad, simultaneous playback and record is very
> widely used.

Especially since I already have that working on PowerPC.  I went through
great lengths to get the device tree binding and the code working in this
regard.

> If the hardware has constraints on the sample rates the driver should be
> telling the application about this.  For the very common case where you
> need the same rate for playback and record there's framework support for
> doing this, the relevant driver just needs to set the symmetric_rates
> flag and the core will do everything.  

And my driver currently does this.  If the SSI is wired up in synchronous
mode, sample rate/size locking is enabled.

-- 
Timur Tabi
Linux kernel developer at Freescale



From nico at fluxnic.net  Mon Mar  5 16:11:56 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 16:11:56 -0500 (EST)
Subject: [PATCH v3 02/30] ARM: provide runtime hook for ioremap/iounmap
In-Reply-To: <201203052013.26688.arnd@arndb.de>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-3-git-send-email-robherring2@gmail.com>
 <alpine.LFD.2.02.1203051415150.31242@xanadu.home>
 <201203052013.26688.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>

On Mon, 5 Mar 2012, Arnd Bergmann wrote:

> On Monday 05 March 2012, Nicolas Pitre wrote:
> > Given that the majority of existing platforms don't need the 
> > indirection, should we make this indirection conditional on 
> > CONFIG_NEED_IOREMAP_HOOK and let those who need it select it?  Or maybe 
> > this isn't performance critical and we just don't care?  In any case I'd 
> > like to see such reasoning captured in the commit log.
> 
> It's certainly not performance critical, but there may be some space overhead
> in the .text section of the kernel that we could avoid by adding another
> indirection.

Of course the size issue can be mitigated significantly by replacing:

extern void __iomem * (*arch_ioremap)(unsigned long, size_t, unsigned int);
extern void (*arch_iounmap)(volatile void __iomem *);

#define __arch_ioremap                 arch_ioremap
#define __arch_iounmap                 arch_iounmap

by:

extern void __iomem * (*arch_ioremap)(unsigned long, size_t, unsigned int);
extern void (*arch_iounmap)(volatile void __iomem *);

extern void __iomem * __arch_ioremap(unsigned long, size_t, unsigned int);
extern void __arch_iounmap(volatile void __iomem *);

and out of line:

void __iomem *__arch_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
{
	return arch_ioremap(phys_addr, size, mtype);
}

void __arch_iounmap(volatile void __iomem *io_addr)
{
	arch_iounmap(io_addr);
}


Nicolas


From paul at pwsan.com  Mon Mar  5 16:15:01 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 5 Mar 2012 14:15:01 -0700 (MST)
Subject: [PATCH] ARM: OMAP2+: omap_device: call all suspend, resume
 callbacks when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set
In-Reply-To: <20120305205233.GT12083@atomide.com>
References: <alpine.DEB.2.00.1203031314050.10611@utopia.booyaka.com>
 <877gyzoyyk.fsf@ti.com>
 <alpine.DEB.2.00.1203051312390.1430@utopia.booyaka.com>
 <20120305205233.GT12083@atomide.com>
Message-ID: <alpine.DEB.2.00.1203051414340.1430@utopia.booyaka.com>

On Mon, 5 Mar 2012, Tony Lindgren wrote:

> * Paul Walmsley <paul at pwsan.com> [120305 11:44]:
> > On Mon, 5 Mar 2012, Kevin Hilman wrote:
> > 
> > > Tony, this fix is needed for v3.3.
> > 
> > Of course, I don't have any objection to this patch going into the v3.3-rc 
> > kernels.  But given that some maintainers seem to be pushing back against 
> > late -rc patches, this one could probably be delayed to 3.4 if required.  
> > no_console_suspend is a debugging-only option and bugs involving it are 
> > unlikely to affect most users.
> 
> I'm fine with your queueing it for v3.4 merge window.

Just chatted with Kevin, he's going to take this one for 3.4 with some 
other omap_device patches he's got queued.


- Paul


From jason at lakedaemon.net  Mon Mar  5 16:17:37 2012
From: jason at lakedaemon.net (Jason)
Date: Mon, 5 Mar 2012 16:17:37 -0500
Subject: [PULL REQUEST v2] ARM: kirkwood: fdt: convert kirkwood init
 funcs to fdt
In-Reply-To: <alpine.LFD.2.02.1203051542190.31242@xanadu.home>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <alpine.LFD.2.02.1203051344130.31242@xanadu.home>
 <20120305191546.GK5050@titan.lakedaemon.net>
 <201203052016.26949.arnd@arndb.de>
 <20120305202941.GN5050@titan.lakedaemon.net>
 <alpine.LFD.2.02.1203051542190.31242@xanadu.home>
Message-ID: <20120305211737.GO5050@titan.lakedaemon.net>

On Mon, Mar 05, 2012 at 03:43:42PM -0500, Nicolas Pitre wrote:
> On Mon, 5 Mar 2012, Jason wrote:
> 
> > On Mon, Mar 05, 2012 at 08:16:26PM +0000, Arnd Bergmann wrote:
> > > On Monday 05 March 2012, Jason wrote:
> > > > > 
> > > > > The clock frequency part being hardcoded to 200000 in the common .dtsi 
> > > > > file looks wrong.  The clock may differ, and it used to (and should) be 
> > > > > probed at run time, please see kirkwood_find_tclk().
> > > > 
> > > > So, should I EXPORT_SYMBOL_GPL(kirkwood_find_tclk); and have each driver
> > > > call it?
> > > 
> > > If the drivers want to use it, I think it has to be orion_find_tclk for
> > > drivers that are shared between multiple plat-orion platforms.
> > 
> > That's pretty much all of them  :-)
> > 
> > I'll rename it and move it to plat-orion/common.c.  This'll be fun.
> 
> No no...  This is not a function which is generic at all.  The _result_ 
> i.e. core clock frequency value is a generic thing, not the method to 
> determine it.

How about this?  Export a global variable, orion_tclk, and a function to
read it.  Then, make sure each sub arch sets the global.  Does this
sound viable until common clk lands?

thx,

Jason.

btw - when I received your email I was in the middle of convincing
myself that I could hack together a common orion_find_tclk().  It was
rapidly becoming a bad idea.  :-)


From nicolas.pitre at linaro.org  Mon Mar  5 16:27:27 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Mon, 5 Mar 2012 16:27:27 -0500 (EST)
Subject: [PULL REQUEST v2] ARM: kirkwood: fdt: convert kirkwood init
 funcs to fdt
In-Reply-To: <20120305211737.GO5050@titan.lakedaemon.net>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <alpine.LFD.2.02.1203051344130.31242@xanadu.home>
 <20120305191546.GK5050@titan.lakedaemon.net>
 <201203052016.26949.arnd@arndb.de>
 <20120305202941.GN5050@titan.lakedaemon.net>
 <alpine.LFD.2.02.1203051542190.31242@xanadu.home>
 <20120305211737.GO5050@titan.lakedaemon.net>
Message-ID: <alpine.LFD.2.02.1203051626370.31242@xanadu.home>

On Mon, 5 Mar 2012, Jason wrote:

> On Mon, Mar 05, 2012 at 03:43:42PM -0500, Nicolas Pitre wrote:
> > On Mon, 5 Mar 2012, Jason wrote:
> > 
> > > On Mon, Mar 05, 2012 at 08:16:26PM +0000, Arnd Bergmann wrote:
> > > > On Monday 05 March 2012, Jason wrote:
> > > > > > 
> > > > > > The clock frequency part being hardcoded to 200000 in the common .dtsi 
> > > > > > file looks wrong.  The clock may differ, and it used to (and should) be 
> > > > > > probed at run time, please see kirkwood_find_tclk().
> > > > > 
> > > > > So, should I EXPORT_SYMBOL_GPL(kirkwood_find_tclk); and have each driver
> > > > > call it?
> > > > 
> > > > If the drivers want to use it, I think it has to be orion_find_tclk for
> > > > drivers that are shared between multiple plat-orion platforms.
> > > 
> > > That's pretty much all of them  :-)
> > > 
> > > I'll rename it and move it to plat-orion/common.c.  This'll be fun.
> > 
> > No no...  This is not a function which is generic at all.  The _result_ 
> > i.e. core clock frequency value is a generic thing, not the method to 
> > determine it.
> 
> How about this?  Export a global variable, orion_tclk, and a function to
> read it.  Then, make sure each sub arch sets the global.  Does this
> sound viable until common clk lands?

Yep, looks fine.


Nicolas


From khilman at ti.com  Mon Mar  5 16:33:20 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 05 Mar 2012 13:33:20 -0800
Subject: [PATCH v7 0/9] Consolidate cpuidle functionality
In-Reply-To: <1330562578-3410-1-git-send-email-rob.lee@linaro.org> (Robert
 Lee's message of "Wed, 29 Feb 2012 18:42:49 -0600")
References: <1330562578-3410-1-git-send-email-rob.lee@linaro.org>
Message-ID: <87y5reivhb.fsf@ti.com>

Robert Lee <rob.lee at linaro.org> writes:

> This patch series moves various functionality duplicated in platform 
> cpuidle drivers to the core cpuidle driver. Also, the platform irq
> disabling was removed as it appears that all calls into 
> cpuidle_call_idle will have already called local_irq_disable().

Reviewed-by: Kevin Hilman <khilman at ti.com>



From tony at atomide.com  Mon Mar  5 16:38:44 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 13:38:44 -0800
Subject: [PATCH V3 1/2] mcx: very basic support for HTKW mcx board
In-Reply-To: <20120305195329.GP12083@atomide.com>
References: <1324482822-24221-1-git-send-email-yanok@emcraft.com>
 <1324482822-24221-2-git-send-email-yanok@emcraft.com>
 <20120305195329.GP12083@atomide.com>
Message-ID: <20120305213844.GU12083@atomide.com>

* Tony Lindgren <tony at atomide.com> [120305 11:21]:
> * Ilya Yanok <yanok at emcraft.com> [111221 07:22]:
> > Very basic support for HTKW mcx board. Able to boot via board-generic
> > and ramdisk/initramfs, however most of peripherals is unsupported.
> > Produces tons of twl4030 related errors as this board doesn't have
> > twl4030 installed.
> > 
> > Signed-off-by: Ilya Yanok <yanok at emcraft.com>
> 
> Grant, care to ack this one?

Actually a version of this you already acked as
"[PATCH 1/2] mt_ventoux: very basic support for TeeJet Mt.Ventoux board"
so using that instead

Regards,

Tony

> > ---
> > Changes from V2:
> > 
> >  - None
> > 
> > Changes from V1:
> > 
> >  - device tree move to the separate patch
> >  - iva node is disabled instead of using custom includes
> >  - removed bootargs entry
> > 
> >  arch/arm/boot/dts/mcx.dts |   27 +++++++++++++++++++++++++++
> >  1 files changed, 27 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/boot/dts/mcx.dts
> > 
> > diff --git a/arch/arm/boot/dts/mcx.dts b/arch/arm/boot/dts/mcx.dts
> > new file mode 100644
> > index 0000000..66b81bd
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/mcx.dts
> > @@ -0,0 +1,27 @@
> > +/*
> > + * Copyright (C) 2011 Ilya Yanok, EmCraft Systems
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + */
> > +/dts-v1/;
> > +
> > +/include/ "omap3.dtsi"
> > +
> > +/ {
> > +	model = "HTKW mcx";
> > +	compatible = "htkw,mcx", "ti,omap3";
> > +
> > +	memory {
> > +		device_type = "memory";
> > +		reg = <0x80000000 0x10000000>; /* 256 MB */
> > +	};
> > +
> > +	/* AM35xx doesn't have IVA */
> > +	soc {
> > +		iva {
> > +			status = "disabled";
> > +		};
> > +	};
> > +};
> > -- 
> > 1.7.6.4
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From stigge at antcom.de  Mon Mar  5 16:40:41 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon,  5 Mar 2012 22:40:41 +0100
Subject: [PATCH v4] lpc32xx: Added ethernet driver
Message-ID: <1330983641-32622-1-git-send-email-stigge@antcom.de>

This patch adds an ethernet driver for the LPC32xx ARM SoC.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Applies to v3.3-rc6

Changes since v3:
 * Jiffies wraparound fix via msecs_to_jiffies() and time_after()
 * Introduces symbolic names for status and control bits of descriptors
 * Tx_errors counting only once at one event
 * Use of_get_mac_address() and dev_hw_addr_random() to get/generate mac
   address
 * Merged lpc_eth.h into lpc_eth.c since it didn't share defs with other
   C files
 * Added interrupt handling via NAPI
 * Removed net_region_start and net_region_size from struct netdata_local
 * Removed (actually unused) platform_data
 * Put LPC32XX_IRAM_* into another resource
 * Use PAGE_ALIGN() for DMA size alignment
 * Define suspend/resume conditionally
 * Use module_platform_driver()
 * Use correct pointer types (pointers, dma_addr_t, phys_addr_t) instead
   of casts

 Thanks to Arnd Bergmann, Ben Hutchings, David Miller, Kevin Wells,
 Russell King and Joe Perches for reviewing!

 drivers/net/ethernet/Kconfig       |    1 
 drivers/net/ethernet/Makefile      |    1 
 drivers/net/ethernet/nxp/Kconfig   |    8 
 drivers/net/ethernet/nxp/Makefile  |    1 
 drivers/net/ethernet/nxp/lpc_eth.c | 1642 +++++++++++++++++++++++++++++++++++++
 5 files changed, 1653 insertions(+)

--- linux-2.6.orig/drivers/net/ethernet/Kconfig
+++ linux-2.6/drivers/net/ethernet/Kconfig
@@ -126,6 +126,7 @@ config NET_NETX
 
 source "drivers/net/ethernet/nuvoton/Kconfig"
 source "drivers/net/ethernet/nvidia/Kconfig"
+source "drivers/net/ethernet/nxp/Kconfig"
 source "drivers/net/ethernet/octeon/Kconfig"
 source "drivers/net/ethernet/oki-semi/Kconfig"
 
--- linux-2.6.orig/drivers/net/ethernet/Makefile
+++ linux-2.6/drivers/net/ethernet/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_NET_VENDOR_NATSEMI) += nats
 obj-$(CONFIG_NET_NETX) += netx-eth.o
 obj-$(CONFIG_NET_VENDOR_NUVOTON) += nuvoton/
 obj-$(CONFIG_NET_VENDOR_NVIDIA) += nvidia/
+obj-$(CONFIG_LPC_ENET) += nxp/
 obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon/
 obj-$(CONFIG_NET_VENDOR_OKI) += oki-semi/
 obj-$(CONFIG_ETHOC) += ethoc.o
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/Kconfig
@@ -0,0 +1,8 @@
+config LPC_ENET
+        tristate "NXP ethernet MAC on LPC devices"
+        depends on ARCH_LPC32XX
+        select PHYLIB
+        help
+	  Say Y or M here if you want to use the NXP ethernet MAC included on
+	  some NXP LPC devices. You can safely enable this option for LPC32xx
+	  SoC. Also available as a module.
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_LPC_ENET) += lpc_eth.o
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/lpc_eth.c
@@ -0,0 +1,1642 @@
+/*
+ * drivers/net/ethernet/nxp/lpc_eth.c
+ *
+ * Author: Kevin Wells <kevin.wells at nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ * Copyright (C) 2012 Roland Stigge <stigge at antcom.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/crc32.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/clk.h>
+#include <linux/workqueue.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/phy.h>
+#include <linux/dma-mapping.h>
+#include <linux/of_net.h>
+#include <linux/types.h>
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <mach/board.h>
+#include <mach/platform.h>
+#include <mach/hardware.h>
+
+#define MODNAME "lpc-eth"
+#define DRV_VERSION "1.00"
+#define PHYDEF_ADDR 0x00
+
+#define ENET_MAXF_SIZE 1536
+#define ENET_RX_DESC 48
+#define ENET_TX_DESC 16
+
+#define NAPI_WEIGHT 16
+
+/*
+ * Ethernet MAC controller Register offsets
+ */
+#define LPC_ENET_MAC1(x)			(x + 0x000)
+#define LPC_ENET_MAC2(x)			(x + 0x004)
+#define LPC_ENET_IPGT(x)			(x + 0x008)
+#define LPC_ENET_IPGR(x)			(x + 0x00C)
+#define LPC_ENET_CLRT(x)			(x + 0x010)
+#define LPC_ENET_MAXF(x)			(x + 0x014)
+#define LPC_ENET_SUPP(x)			(x + 0x018)
+#define LPC_ENET_TEST(x)			(x + 0x01C)
+#define LPC_ENET_MCFG(x)			(x + 0x020)
+#define LPC_ENET_MCMD(x)			(x + 0x024)
+#define LPC_ENET_MADR(x)			(x + 0x028)
+#define LPC_ENET_MWTD(x)			(x + 0x02C)
+#define LPC_ENET_MRDD(x)			(x + 0x030)
+#define LPC_ENET_MIND(x)			(x + 0x034)
+#define LPC_ENET_SA0(x)				(x + 0x040)
+#define LPC_ENET_SA1(x)				(x + 0x044)
+#define LPC_ENET_SA2(x)				(x + 0x048)
+#define LPC_ENET_COMMAND(x)			(x + 0x100)
+#define LPC_ENET_STATUS(x)			(x + 0x104)
+#define LPC_ENET_RXDESCRIPTOR(x)		(x + 0x108)
+#define LPC_ENET_RXSTATUS(x)			(x + 0x10C)
+#define LPC_ENET_RXDESCRIPTORNUMBER(x)		(x + 0x110)
+#define LPC_ENET_RXPRODUCEINDEX(x)		(x + 0x114)
+#define LPC_ENET_RXCONSUMEINDEX(x)		(x + 0x118)
+#define LPC_ENET_TXDESCRIPTOR(x)		(x + 0x11C)
+#define LPC_ENET_TXSTATUS(x)			(x + 0x120)
+#define LPC_ENET_TXDESCRIPTORNUMBER(x)		(x + 0x124)
+#define LPC_ENET_TXPRODUCEINDEX(x)		(x + 0x128)
+#define LPC_ENET_TXCONSUMEINDEX(x)		(x + 0x12C)
+#define LPC_ENET_TSV0(x)			(x + 0x158)
+#define LPC_ENET_TSV1(x)			(x + 0x15C)
+#define LPC_ENET_RSV(x)				(x + 0x160)
+#define LPC_ENET_FLOWCONTROLCOUNTER(x)		(x + 0x170)
+#define LPC_ENET_FLOWCONTROLSTATUS(x)		(x + 0x174)
+#define LPC_ENET_RXFILTER_CTRL(x)		(x + 0x200)
+#define LPC_ENET_RXFILTERWOLSTATUS(x)		(x + 0x204)
+#define LPC_ENET_RXFILTERWOLCLEAR(x)		(x + 0x208)
+#define LPC_ENET_HASHFILTERL(x)			(x + 0x210)
+#define LPC_ENET_HASHFILTERH(x)			(x + 0x214)
+#define LPC_ENET_INTSTATUS(x)			(x + 0xFE0)
+#define LPC_ENET_INTENABLE(x)			(x + 0xFE4)
+#define LPC_ENET_INTCLEAR(x)			(x + 0xFE8)
+#define LPC_ENET_INTSET(x)			(x + 0xFEC)
+#define LPC_ENET_POWERDOWN(x)			(x + 0xFF4)
+
+/*
+ * mac1 register definitions
+ */
+#define LPC_MAC1_RECV_ENABLE			(1 << 0)
+#define LPC_MAC1_PASS_ALL_RX_FRAMES		(1 << 1)
+#define LPC_MAC1_RX_FLOW_CONTROL		(1 << 2)
+#define LPC_MAC1_TX_FLOW_CONTROL		(1 << 3)
+#define LPC_MAC1_LOOPBACK			(1 << 4)
+#define LPC_MAC1_RESET_TX			(1 << 8)
+#define LPC_MAC1_RESET_MCS_TX			(1 << 9)
+#define LPC_MAC1_RESET_RX			(1 << 10)
+#define LPC_MAC1_RESET_MCS_RX			(1 << 11)
+#define LPC_MAC1_SIMULATION_RESET		(1 << 14)
+#define LPC_MAC1_SOFT_RESET			(1 << 15)
+
+/*
+ * mac2 register definitions
+ */
+#define LPC_MAC2_FULL_DUPLEX			(1 << 0)
+#define LPC_MAC2_FRAME_LENGTH_CHECKING		(1 << 1)
+#define LPC_MAC2_HUGH_LENGTH_CHECKING		(1 << 2)
+#define LPC_MAC2_DELAYED_CRC			(1 << 3)
+#define LPC_MAC2_CRC_ENABLE			(1 << 4)
+#define LPC_MAC2_PAD_CRC_ENABLE			(1 << 5)
+#define LPC_MAC2_VLAN_PAD_ENABLE		(1 << 6)
+#define LPC_MAC2_AUTO_DETECT_PAD_ENABLE		(1 << 7)
+#define LPC_MAC2_PURE_PREAMBLE_ENFORCEMENT	(1 << 8)
+#define LPC_MAC2_LONG_PREAMBLE_ENFORCEMENT	(1 << 9)
+#define LPC_MAC2_NO_BACKOFF			(1 << 12)
+#define LPC_MAC2_BACK_PRESSURE			(1 << 13)
+#define LPC_MAC2_EXCESS_DEFER			(1 << 14)
+
+/*
+ * ipgt register definitions
+ */
+#define LPC_IPGT_LOAD(n)			((n) & 0x7F)
+
+/*
+ * ipgr register definitions
+ */
+#define LPC_IPGR_LOAD_PART2(n)			((n) & 0x7F)
+#define LPC_IPGR_LOAD_PART1(n)			(((n) & 0x7F) << 8)
+
+/*
+ * clrt register definitions
+ */
+#define LPC_CLRT_LOAD_RETRY_MAX(n)		((n) & 0xF)
+#define LPC_CLRT_LOAD_COLLISION_WINDOW(n)	(((n) & 0x3F) << 8)
+
+/*
+ * maxf register definitions
+ */
+#define LPC_MAXF_LOAD_MAX_FRAME_LEN(n)		((n) & 0xFFFF)
+
+/*
+ * supp register definitions
+ */
+#define LPC_SUPP_SPEED				(1 << 8)
+#define LPC_SUPP_RESET_RMII			(1 << 11)
+
+/*
+ * test register definitions
+ */
+#define LPC_TEST_SHORTCUT_PAUSE_QUANTA		(1 << 0)
+#define LPC_TEST_PAUSE				(1 << 1)
+#define LPC_TEST_BACKPRESSURE			(1 << 2)
+
+/*
+ * mcfg register definitions
+ */
+#define LPC_MCFG_SCAN_INCREMENT			(1 << 0)
+#define LPC_MCFG_SUPPRESS_PREAMBLE		(1 << 1)
+#define LPC_MCFG_CLOCK_SELECT(n)		(((n) & 0x7) << 2)
+#define LPC_MCFG_CLOCK_HOST_DIV_4		0
+#define LPC_MCFG_CLOCK_HOST_DIV_6		2
+#define LPC_MCFG_CLOCK_HOST_DIV_8		3
+#define LPC_MCFG_CLOCK_HOST_DIV_10		4
+#define LPC_MCFG_CLOCK_HOST_DIV_14		5
+#define LPC_MCFG_CLOCK_HOST_DIV_20		6
+#define LPC_MCFG_CLOCK_HOST_DIV_28		7
+#define LPC_MCFG_RESET_MII_MGMT			(1 << 15)
+
+/*
+ * mcmd register definitions
+ */
+#define LPC_MCMD_READ				(1 << 0)
+#define LPC_MCMD_SCAN				(1 << 1)
+
+/*
+ * madr register definitions
+ */
+#define LPC_MADR_REGISTER_ADDRESS(n)		((n) & 0x1F)
+#define LPC_MADR_PHY_0ADDRESS(n)		(((n) & 0x1F) << 8)
+
+/*
+ * mwtd register definitions
+ */
+#define LPC_MWDT_WRITE(n)			((n) & 0xFFFF)
+
+/*
+ * mrdd register definitions
+ */
+#define LPC_MRDD_READ_MASK			0xFFFF
+
+/*
+ * mind register definitions
+ */
+#define LPC_MIND_BUSY				(1 << 0)
+#define LPC_MIND_SCANNING			(1 << 1)
+#define LPC_MIND_NOT_VALID			(1 << 2)
+#define LPC_MIND_MII_LINK_FAIL			(1 << 3)
+
+/*
+ * command register definitions
+ */
+#define LPC_COMMAND_RXENABLE			(1 << 0)
+#define LPC_COMMAND_TXENABLE			(1 << 1)
+#define LPC_COMMAND_REG_RESET			(1 << 3)
+#define LPC_COMMAND_TXRESET			(1 << 4)
+#define LPC_COMMAND_RXRESET			(1 << 5)
+#define LPC_COMMAND_PASSRUNTFRAME		(1 << 6)
+#define LPC_COMMAND_PASSRXFILTER		(1 << 7)
+#define LPC_COMMAND_TXFLOWCONTROL		(1 << 8)
+#define LPC_COMMAND_RMII			(1 << 9)
+#define LPC_COMMAND_FULLDUPLEX			(1 << 10)
+
+/*
+ * status register definitions
+ */
+#define LPC_STATUS_RXACTIVE			(1 << 0)
+#define LPC_STATUS_TXACTIVE			(1 << 1)
+
+/*
+ * tsv0 register definitions
+ */
+#define LPC_TSV0_CRC_ERROR			(1 << 0)
+#define LPC_TSV0_LENGTH_CHECK_ERROR		(1 << 1)
+#define LPC_TSV0_LENGTH_OUT_OF_RANGE		(1 << 2)
+#define LPC_TSV0_DONE				(1 << 3)
+#define LPC_TSV0_MULTICAST			(1 << 4)
+#define LPC_TSV0_BROADCAST			(1 << 5)
+#define LPC_TSV0_PACKET_DEFER			(1 << 6)
+#define LPC_TSV0_ESCESSIVE_DEFER		(1 << 7)
+#define LPC_TSV0_ESCESSIVE_COLLISION		(1 << 8)
+#define LPC_TSV0_LATE_COLLISION			(1 << 9)
+#define LPC_TSV0_GIANT				(1 << 10)
+#define LPC_TSV0_UNDERRUN			(1 << 11)
+#define LPC_TSV0_TOTAL_BYTES(n)			(((n) >> 12) & 0xFFFF)
+#define LPC_TSV0_CONTROL_FRAME			(1 << 28)
+#define LPC_TSV0_PAUSE				(1 << 29)
+#define LPC_TSV0_BACKPRESSURE			(1 << 30)
+#define LPC_TSV0_VLAN				(1 << 31)
+
+/*
+ * tsv1 register definitions
+ */
+#define LPC_TSV1_TRANSMIT_BYTE_COUNT(n)		((n) & 0xFFFF)
+#define LPC_TSV1_COLLISION_COUNT(n)		(((n) >> 16) & 0xF)
+
+/*
+ * rsv register definitions
+ */
+#define LPC_RSV_RECEIVED_BYTE_COUNT(n)		((n) & 0xFFFF)
+#define LPC_RSV_RXDV_EVENT_IGNORED		(1 << 16)
+#define LPC_RSV_RXDV_EVENT_PREVIOUSLY_SEEN	(1 << 17)
+#define LPC_RSV_CARRIER_EVNT_PREVIOUS_SEEN	(1 << 18)
+#define LPC_RSV_RECEIVE_CODE_VIOLATION		(1 << 19)
+#define LPC_RSV_CRC_ERROR			(1 << 20)
+#define LPC_RSV_LENGTH_CHECK_ERROR		(1 << 21)
+#define LPC_RSV_LENGTH_OUT_OF_RANGE		(1 << 22)
+#define LPC_RSV_RECEIVE_OK			(1 << 23)
+#define LPC_RSV_MULTICAST			(1 << 24)
+#define LPC_RSV_BROADCAST			(1 << 25)
+#define LPC_RSV_DRIBBLE_NIBBLE			(1 << 26)
+#define LPC_RSV_CONTROL_FRAME			(1 << 27)
+#define LPC_RSV_PAUSE				(1 << 28)
+#define LPC_RSV_UNSUPPORTED_OPCODE		(1 << 29)
+#define LPC_RSV_VLAN				(1 << 30)
+
+/*
+ * flowcontrolcounter register definitions
+ */
+#define LPC_FCCR_MIRRORCOUNTER(n)		((n) & 0xFFFF)
+#define LPC_FCCR_PAUSETIMER(n)			(((n) >> 16) & 0xFFFF)
+
+/*
+ * flowcontrolstatus register definitions
+ */
+#define LPC_FCCR_MIRRORCOUNTERCURRENT(n)	((n) & 0xFFFF)
+
+/*
+ * rxfliterctrl, rxfilterwolstatus, and rxfilterwolclear shared
+ * register definitions
+ */
+#define LPC_RXFLTRW_ACCEPTUNICAST		(1 << 0)
+#define LPC_RXFLTRW_ACCEPTUBROADCAST		(1 << 1)
+#define LPC_RXFLTRW_ACCEPTUMULTICAST		(1 << 2)
+#define LPC_RXFLTRW_ACCEPTUNICASTHASH		(1 << 3)
+#define LPC_RXFLTRW_ACCEPTUMULTICASTHASH	(1 << 4)
+#define LPC_RXFLTRW_ACCEPTPERFECT		(1 << 5)
+
+/*
+ * rxfliterctrl register definitions
+ */
+#define LPC_RXFLTRWSTS_MAGICPACKETENWOL		(1 << 12)
+#define LPC_RXFLTRWSTS_RXFILTERENWOL		(1 << 13)
+
+/*
+ * rxfilterwolstatus/rxfilterwolclear register definitions
+ */
+#define LPC_RXFLTRWSTS_RXFILTERWOL		(1 << 7)
+#define LPC_RXFLTRWSTS_MAGICPACKETWOL		(1 << 8)
+
+/*
+ * intstatus, intenable, intclear, and Intset shared register
+ * definitions
+ */
+#define LPC_MACINT_RXOVERRUNINTEN		(1 << 0)
+#define LPC_MACINT_RXERRORONINT			(1 << 1)
+#define LPC_MACINT_RXFINISHEDINTEN		(1 << 2)
+#define LPC_MACINT_RXDONEINTEN			(1 << 3)
+#define LPC_MACINT_TXUNDERRUNINTEN		(1 << 4)
+#define LPC_MACINT_TXERRORINTEN			(1 << 5)
+#define LPC_MACINT_TXFINISHEDINTEN		(1 << 6)
+#define LPC_MACINT_TXDONEINTEN			(1 << 7)
+#define LPC_MACINT_SOFTINTEN			(1 << 12)
+#define LPC_MACINT_WAKEUPINTEN			(1 << 13)
+
+/*
+ * powerdown register definitions
+ */
+#define LPC_POWERDOWN_MACAHB			(1 << 31)
+
+static inline phy_interface_t lpc_phy_interface_mode(void)
+{
+#ifdef CONFIG_ARCH_LPC32XX_MII_SUPPORT
+	return PHY_INTERFACE_MODE_MII;
+#else
+	return PHY_INTERFACE_MODE_RMII;
+#endif
+}
+
+static inline int use_iram_for_net(void)
+{
+#ifdef CONFIG_ARCH_LPC32XX_IRAM_FOR_NET
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+/* Receive Status information word */
+#define RXSTATUS_SIZE			0x000007FF
+#define RXSTATUS_CONTROL		(1 << 18)
+#define RXSTATUS_VLAN			(1 << 19)
+#define RXSTATUS_FILTER			(1 << 20)
+#define RXSTATUS_MULTICAST		(1 << 21)
+#define RXSTATUS_BROADCAST		(1 << 22)
+#define RXSTATUS_CRC			(1 << 23)
+#define RXSTATUS_SYMBOL			(1 << 24)
+#define RXSTATUS_LENGTH			(1 << 25)
+#define RXSTATUS_RANGE			(1 << 26)
+#define RXSTATUS_ALIGN			(1 << 27)
+#define RXSTATUS_OVERRUN		(1 << 28)
+#define RXSTATUS_NODESC			(1 << 29)
+#define RXSTATUS_LAST			(1 << 30)
+#define RXSTATUS_ERROR			(1 << 31)
+
+#define RXSTATUS_STATUS_ERROR \
+	(RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | RXSTATUS_RANGE \
+	 | RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC)
+
+/* Receive Descriptor control word */
+#define RXDESC_CONTROL_SIZE		0x000007FF
+#define RXDESC_CONTROL_INT		(1 << 31)
+
+/* Transmit Status information word */
+#define TXSTATUS_COLLISIONS_GET(x)	(((x) >> 21) & 0xF)
+#define TXSTATUS_DEFER			(1 << 25)
+#define TXSTATUS_EXCESSDEFER		(1 << 26)
+#define TXSTATUS_EXCESSCOLL		(1 << 27)
+#define TXSTATUS_LATECOLL		(1 << 28)
+#define TXSTATUS_UNDERRUN		(1 << 29)
+#define TXSTATUS_NODESC			(1 << 30)
+#define TXSTATUS_ERROR			(1 << 31)
+
+/* Transmit Descriptor control word */
+#define TXDESC_CONTROL_SIZE		0x000007FF
+#define TXDESC_CONTROL_OVERRIDE		(1 << 26)
+#define TXDESC_CONTROL_HUGE		(1 << 27)
+#define TXDESC_CONTROL_PAD		(1 << 28)
+#define TXDESC_CONTROL_CRC		(1 << 29)
+#define TXDESC_CONTROL_LAST		(1 << 30)
+#define TXDESC_CONTROL_INT		(1 << 31)
+
+static int lpc_eth_hard_start_xmit(struct sk_buff *skb,
+	struct net_device *ndev);
+
+/*
+ * Transmit timeout, default 2.5 seconds.
+ */
+static int watchdog = 2500;
+module_param(watchdog, int, 0400);
+MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
+
+/*
+ * Structure of a TX/RX descriptors and RX status
+ */
+struct txrx_desc_t {
+	volatile u32 packet;
+	volatile u32 control;
+};
+struct rx_status_t {
+	volatile u32 statusinfo;
+	volatile u32 statushashcrc;
+};
+
+/*
+ * Device driver data structure
+ */
+struct netdata_local {
+	struct platform_device	*pdev;
+	struct net_device	*ndev;
+	spinlock_t		lock;
+	void __iomem		*net_base;
+	u32			msg_enable;
+	struct sk_buff		*skb[ENET_TX_DESC];
+	unsigned int		last_tx_idx;
+	unsigned int		num_used_tx_buffs;
+	struct mii_bus		*mii_bus;
+	struct phy_device	*phy_dev;
+	struct clk		*clk;
+	dma_addr_t		dma_buff_base_p;
+	void			*dma_buff_base_v;
+	size_t			dma_buff_size;
+	struct txrx_desc_t	*tx_desc_v[ENET_TX_DESC];
+	u32			*tx_stat_v[ENET_TX_DESC];
+	void			*tx_buff_v[ENET_TX_DESC];
+	struct txrx_desc_t	*rx_desc_v[ENET_RX_DESC];
+	struct rx_status_t	*rx_stat_v[ENET_RX_DESC];
+	void			*rx_buff_v[ENET_RX_DESC];
+	int			link;
+	int			speed;
+	int			duplex;
+	struct napi_struct	napi;
+};
+
+/*
+ * MAC support functions
+ */
+static void __lpc_set_mac(struct netdata_local *pldat, u8 *mac)
+{
+	u32 tmp;
+
+	/* Set station address */
+	tmp = mac[0] | ((u32)mac[1] << 8);
+	writel(tmp, LPC_ENET_SA2(pldat->net_base));
+	tmp = mac[2] | ((u32)mac[3] << 8);
+	writel(tmp, LPC_ENET_SA1(pldat->net_base));
+	tmp = mac[4] | ((u32)mac[5] << 8);
+	writel(tmp, LPC_ENET_SA0(pldat->net_base));
+
+	netdev_dbg(pldat->ndev, "Ethernet MAC address %pM\n", mac);
+}
+
+static void __lpc_get_mac(struct netdata_local *pldat, u8 *mac)
+{
+	u32 tmp;
+
+	/* Get station address */
+	tmp = readl(LPC_ENET_SA2(pldat->net_base));
+	mac[0] = tmp & 0xFF;
+	mac[1] = tmp >> 8;
+	tmp = readl(LPC_ENET_SA1(pldat->net_base));
+	mac[2] = tmp & 0xFF;
+	mac[3] = tmp >> 8;
+	tmp = readl(LPC_ENET_SA0(pldat->net_base));
+	mac[4] = tmp & 0xFF;
+	mac[5] = tmp >> 8;
+}
+
+static void __lpc_eth_clock_enable(struct netdata_local *pldat,
+	int enable)
+{
+	if (enable)
+		clk_enable(pldat->clk);
+	else
+		clk_disable(pldat->clk);
+}
+
+static void __lpc_params_setup(struct netdata_local *pldat)
+{
+	u32 tmp;
+
+	if (pldat->duplex == DUPLEX_FULL) {
+		tmp = readl(LPC_ENET_MAC2(pldat->net_base));
+		tmp |= LPC_MAC2_FULL_DUPLEX;
+		writel(tmp, LPC_ENET_MAC2(pldat->net_base));
+		tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+		tmp |= LPC_COMMAND_FULLDUPLEX;
+		writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base));
+	} else {
+		tmp = readl(LPC_ENET_MAC2(pldat->net_base));
+		tmp &= ~LPC_MAC2_FULL_DUPLEX;
+		writel(tmp, LPC_ENET_MAC2(pldat->net_base));
+		tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+		tmp &= ~LPC_COMMAND_FULLDUPLEX;
+		writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base));
+	}
+
+	if (pldat->speed == SPEED_100)
+		writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base));
+	else
+		writel(0, LPC_ENET_SUPP(pldat->net_base));
+}
+
+static void __lpc_eth_reset(struct netdata_local *pldat)
+{
+	/* Reset all MAC logic */
+	writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX |
+		LPC_MAC1_RESET_MCS_RX | LPC_MAC1_SIMULATION_RESET |
+		LPC_MAC1_SOFT_RESET), LPC_ENET_MAC1(pldat->net_base));
+	writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET |
+		LPC_COMMAND_RXRESET), LPC_ENET_COMMAND(pldat->net_base));
+}
+
+static int __lpc_mii_mngt_reset(struct netdata_local *pldat)
+{
+	/* Reset MII management hardware */
+	writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base));
+
+	/* Setup MII clock to slowest rate with a /28 divider */
+	writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28),
+		LPC_ENET_MCFG(pldat->net_base));
+
+	return 0;
+}
+
+static inline phys_addr_t __va_to_pa(void *addr, struct netdata_local *pldat)
+{
+	phys_addr_t phaddr;
+
+	phaddr = addr - pldat->dma_buff_base_v;
+	phaddr += pldat->dma_buff_base_p;
+
+	return phaddr;
+}
+
+static void lpc_eth_enable_int(void __iomem *regbase)
+{
+	writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN),
+		LPC_ENET_INTENABLE(regbase));
+}
+
+static void lpc_eth_disable_int(void __iomem *regbase)
+{
+	writel(0, LPC_ENET_INTENABLE(regbase));
+}
+
+/* Setup TX/RX descriptors */
+static void __lpc_txrx_desc_setup(struct netdata_local *pldat)
+{
+	u32 *ptxstat;
+	void *tbuff;
+	int i;
+	struct txrx_desc_t *ptxrxdesc;
+	struct rx_status_t *prxstat;
+
+	tbuff = PTR_ALIGN(pldat->dma_buff_base_v, 4);
+
+	/* Setup TX descriptors, status, and buffers */
+	for (i = 0; i < ENET_TX_DESC; i++) {
+		pldat->tx_desc_v[i] = tbuff;
+		tbuff += sizeof(struct txrx_desc_t);
+	}
+	for (i = 0; i < ENET_TX_DESC; i++) {
+		pldat->tx_stat_v[i] = tbuff;
+		tbuff += sizeof(u32);
+	}
+	tbuff = PTR_ALIGN(tbuff, 4);
+	for (i = 0; i < ENET_TX_DESC; i++) {
+		pldat->tx_buff_v[i] = tbuff;
+		tbuff += ENET_MAXF_SIZE;
+	}
+
+	/* Setup RX descriptors, status, and buffers */
+	for (i = 0; i < ENET_RX_DESC; i++) {
+		pldat->rx_desc_v[i] = tbuff;
+		tbuff += sizeof(struct txrx_desc_t);
+	}
+	tbuff = PTR_ALIGN(tbuff, 4);
+	for (i = 0; i < ENET_RX_DESC; i++) {
+		pldat->rx_stat_v[i] = tbuff;
+		tbuff += sizeof(struct rx_status_t);
+	}
+	tbuff = PTR_ALIGN(tbuff, 4);
+	for (i = 0; i < ENET_RX_DESC; i++) {
+		pldat->rx_buff_v[i] = tbuff;
+		tbuff += ENET_MAXF_SIZE;
+	}
+
+	/* Map the TX descriptors to the TX buffers in hardware */
+	for (i = 0; i < ENET_TX_DESC; i++) {
+		ptxstat = pldat->tx_stat_v[i];
+		ptxrxdesc = pldat->tx_desc_v[i];
+
+		ptxrxdesc->packet = __va_to_pa(pldat->tx_buff_v[i], pldat);
+		ptxrxdesc->control = 0;
+		*ptxstat = 0;
+	}
+
+	/* Map the RX descriptors to the RX buffers in hardware */
+	for (i = 0; i < ENET_RX_DESC; i++) {
+		prxstat = pldat->rx_stat_v[i];
+		ptxrxdesc = pldat->rx_desc_v[i];
+
+		ptxrxdesc->packet = __va_to_pa(pldat->rx_buff_v[i], pldat);
+		ptxrxdesc->control = RXDESC_CONTROL_INT | (ENET_MAXF_SIZE - 1);
+		prxstat->statusinfo = 0;
+		prxstat->statushashcrc = 0;
+	}
+
+	/* Setup base addresses in hardware to point to buffers and
+	   descriptors */
+	writel((ENET_TX_DESC - 1),
+		LPC_ENET_TXDESCRIPTORNUMBER(pldat->net_base));
+	writel(__va_to_pa(pldat->tx_desc_v[0], pldat),
+		LPC_ENET_TXDESCRIPTOR(pldat->net_base));
+	writel(__va_to_pa(pldat->tx_stat_v[0], pldat),
+		LPC_ENET_TXSTATUS(pldat->net_base));
+	writel((ENET_RX_DESC - 1),
+		LPC_ENET_RXDESCRIPTORNUMBER(pldat->net_base));
+	writel(__va_to_pa(pldat->rx_desc_v[0], pldat),
+		LPC_ENET_RXDESCRIPTOR(pldat->net_base));
+	writel(__va_to_pa(pldat->rx_stat_v[0], pldat),
+		LPC_ENET_RXSTATUS(pldat->net_base));
+}
+
+static void __lpc_eth_init(struct netdata_local *pldat)
+{
+	u32 tmp;
+
+	/* Disable controller and reset */
+	tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+	tmp &= ~LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
+	writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+	tmp = readl(LPC_ENET_MAC1(pldat->net_base));
+	tmp &= ~LPC_MAC1_RECV_ENABLE;
+	writel(tmp, LPC_ENET_MAC1(pldat->net_base));
+
+	/* Initial MAC setup */
+	writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base));
+	writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE),
+		LPC_ENET_MAC2(pldat->net_base));
+	writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base));
+
+	/* Collision window, gap */
+	writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) |
+		LPC_CLRT_LOAD_COLLISION_WINDOW(0x37)),
+		LPC_ENET_CLRT(pldat->net_base));
+	writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base));
+
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		writel(LPC_COMMAND_PASSRUNTFRAME,
+			LPC_ENET_COMMAND(pldat->net_base));
+	else {
+		writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
+			LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
+	}
+
+	__lpc_params_setup(pldat);
+
+	/* Setup TX and RX descriptors */
+	__lpc_txrx_desc_setup(pldat);
+
+	/* Setup packet filtering */
+	writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT),
+		LPC_ENET_RXFILTER_CTRL(pldat->net_base));
+
+	/* Clear and enable interrupts */
+	writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
+	lpc_eth_enable_int(pldat->net_base);
+
+	/* Get the next TX buffer output index */
+	pldat->num_used_tx_buffs = 0;
+	pldat->last_tx_idx =
+		readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+
+	/* Enable controller */
+	tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+	tmp |= LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
+	writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+	tmp = readl(LPC_ENET_MAC1(pldat->net_base));
+	tmp |= LPC_MAC1_RECV_ENABLE;
+	writel(tmp, LPC_ENET_MAC1(pldat->net_base));
+}
+
+static void __lpc_eth_shutdown(struct netdata_local *pldat)
+{
+	/* Reset ethernet and power down PHY */
+	__lpc_eth_reset(pldat);
+	writel(0, LPC_ENET_MAC1(pldat->net_base));
+	writel(0, LPC_ENET_MAC2(pldat->net_base));
+}
+
+/*
+ * MAC<--->PHY support functions
+ */
+static int lpc_mdio_read(struct mii_bus *bus, int phy_id, int phyreg)
+{
+	struct netdata_local *pldat = bus->priv;
+	unsigned long timeout = jiffies + msecs_to_jiffies(100);
+	int lps;
+
+	writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
+	writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base));
+
+	/* Wait for unbusy status */
+	while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
+		if (time_after(jiffies, timeout))
+			return -EIO;
+		cpu_relax();
+	}
+
+	lps = readl(LPC_ENET_MRDD(pldat->net_base));
+	writel(0, LPC_ENET_MCMD(pldat->net_base));
+
+	return lps;
+}
+
+static int lpc_mdio_write(struct mii_bus *bus, int phy_id, int phyreg,
+			u16 phydata)
+{
+	struct netdata_local *pldat = bus->priv;
+	unsigned long timeout = jiffies + msecs_to_jiffies(100);
+
+	writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
+	writel(phydata, LPC_ENET_MWTD(pldat->net_base));
+
+	/* Wait for completion */
+	while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
+		if (time_after(jiffies, timeout))
+			return -EIO;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int lpc_mdio_reset(struct mii_bus *bus)
+{
+	return __lpc_mii_mngt_reset((struct netdata_local *)bus->priv);
+}
+
+static void lpc_handle_link_change(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+	unsigned long flags;
+
+	int status_change = 0;
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	if (phydev->link) {
+		if ((pldat->speed != phydev->speed) ||
+		    (pldat->duplex != phydev->duplex)) {
+			pldat->speed = phydev->speed;
+			pldat->duplex = phydev->duplex;
+			status_change = 1;
+		}
+	}
+
+	if (phydev->link != pldat->link) {
+		if (!phydev->link) {
+			pldat->speed = 0;
+			pldat->duplex = -1;
+		}
+		pldat->link = phydev->link;
+
+		status_change = 1;
+	}
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	if (status_change)
+		__lpc_params_setup(pldat);
+}
+
+static int lpc_mii_probe(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = NULL;
+	int phy_addr;
+
+	/* find the first phy */
+	for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
+		if (pldat->mii_bus->phy_map[phy_addr]) {
+			phydev = pldat->mii_bus->phy_map[phy_addr];
+			break;
+		}
+	}
+
+	if (!phydev) {
+		netdev_err(ndev, "no PHY found\n");
+		return -ENODEV;
+	}
+
+	/* Attach to the PHY */
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		netdev_info(ndev, "using MII interface\n");
+	else
+		netdev_info(ndev, "using RMII interface\n");
+	phydev = phy_connect(ndev, dev_name(&phydev->dev),
+		&lpc_handle_link_change, 0, lpc_phy_interface_mode());
+
+	if (IS_ERR(phydev)) {
+		netdev_err(ndev, "Could not attach to PHY\n");
+		return PTR_ERR(phydev);
+	}
+
+	/* mask with MAC supported features */
+	phydev->supported &= PHY_BASIC_FEATURES;
+
+	phydev->advertising = phydev->supported;
+
+	pldat->link = 0;
+	pldat->speed = 0;
+	pldat->duplex = -1;
+	pldat->phy_dev = phydev;
+
+	return 0;
+}
+
+static int lpc_mii_init(struct netdata_local *pldat)
+{
+	int err = -ENXIO, i;
+
+	pldat->mii_bus = mdiobus_alloc();
+	if (!pldat->mii_bus) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	/* Setup MII mode */
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		writel(LPC_COMMAND_PASSRUNTFRAME,
+			LPC_ENET_COMMAND(pldat->net_base));
+	else {
+		writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
+			LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
+	}
+
+	pldat->mii_bus->name = "lpc_mii_bus";
+	pldat->mii_bus->read = &lpc_mdio_read;
+	pldat->mii_bus->write = &lpc_mdio_write;
+	pldat->mii_bus->reset = &lpc_mdio_reset;
+	snprintf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%x", pldat->pdev->id);
+	pldat->mii_bus->priv = pldat;
+	pldat->mii_bus->parent = &pldat->pdev->dev;
+	pldat->mii_bus->phy_mask = 0xFFFFFFF0;
+
+	pldat->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!pldat->mii_bus->irq) {
+		err = -ENOMEM;
+		goto err_out_1;
+	}
+
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		pldat->mii_bus->irq[i] = PHY_POLL;
+
+	platform_set_drvdata(pldat->pdev, pldat->mii_bus);
+
+	if (mdiobus_register(pldat->mii_bus))
+		goto err_out_free_mdio_irq;
+
+	if (lpc_mii_probe(pldat->ndev) != 0)
+		goto err_out_unregister_bus;
+
+	return 0;
+
+err_out_unregister_bus:
+	mdiobus_unregister(pldat->mii_bus);
+err_out_free_mdio_irq:
+	kfree(pldat->mii_bus->irq);
+err_out_1:
+	mdiobus_free(pldat->mii_bus);
+err_out:
+	return err;
+}
+
+static void __lpc_handle_xmit(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct sk_buff *skb;
+	u32 txcidx, *ptxstat, txstat;
+
+	txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+	while (pldat->last_tx_idx != txcidx) {
+		skb = pldat->skb[pldat->last_tx_idx];
+
+		/* A buffer is available, get buffer status */
+		ptxstat = pldat->tx_stat_v[pldat->last_tx_idx];
+		txstat = *ptxstat;
+
+		/* Next buffer and decrement used buffer counter */
+		pldat->num_used_tx_buffs--;
+		pldat->last_tx_idx++;
+		if (pldat->last_tx_idx >= ENET_TX_DESC)
+			pldat->last_tx_idx = 0;
+
+		/* Update collision counter */
+		ndev->stats.collisions += TXSTATUS_COLLISIONS_GET(txstat);
+
+		/* Any errors occurred? */
+		if (txstat & TXSTATUS_ERROR) {
+			if (txstat & TXSTATUS_UNDERRUN) {
+				/* FIFO underrun */
+				ndev->stats.tx_fifo_errors++;
+			}
+			if (txstat & TXSTATUS_LATECOLL) {
+				/* Late collision */
+				ndev->stats.tx_aborted_errors++;
+			}
+			if (txstat & TXSTATUS_EXCESSCOLL) {
+				/* Excessive collision */
+				ndev->stats.tx_aborted_errors++;
+			}
+			if (txstat & TXSTATUS_EXCESSDEFER) {
+				/* Defer limit */
+				ndev->stats.tx_aborted_errors++;
+			}
+			ndev->stats.tx_errors++;
+
+			/* Buffer transmit failed, requeue it */
+			lpc_eth_hard_start_xmit(skb, ndev);
+		} else {
+			/* Update stats */
+			ndev->stats.tx_packets++;
+			ndev->stats.tx_bytes += skb->len;
+
+			/* Free buffer */
+			dev_kfree_skb_irq(skb);
+		}
+
+		txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+	}
+
+	if (netif_queue_stopped(ndev))
+		netif_wake_queue(ndev);
+}
+
+static int __lpc_handle_recv(struct net_device *ndev, int budget)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct sk_buff *skb;
+	u32 rxconsidx, len, ethst;
+	struct rx_status_t *prxstat;
+	u8 *prdbuf;
+	int rx_done = 0;
+
+	/* Get the current RX buffer indexes */
+	rxconsidx = readl(LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
+	while (rx_done < budget && rxconsidx !=
+			readl(LPC_ENET_RXPRODUCEINDEX(pldat->net_base))) {
+		/* Get pointer to receive status */
+		prxstat = pldat->rx_stat_v[rxconsidx];
+		len = (prxstat->statusinfo & RXSTATUS_SIZE) + 1;
+
+		/* Status error? */
+		ethst = prxstat->statusinfo;
+		if ((ethst & (RXSTATUS_ERROR | RXSTATUS_STATUS_ERROR)) ==
+				(RXSTATUS_ERROR | RXSTATUS_RANGE))
+			ethst &= ~RXSTATUS_ERROR;
+
+		if (ethst & RXSTATUS_ERROR) {
+			int si = prxstat->statusinfo;
+			/* Check statuses */
+			if (si & RXSTATUS_OVERRUN) {
+				/* Overrun error */
+				ndev->stats.rx_fifo_errors++;
+			} else if (si & RXSTATUS_CRC) {
+				/* CRC error */
+				ndev->stats.rx_crc_errors++;
+			} else if (si & RXSTATUS_LENGTH) {
+				/* Length error */
+				ndev->stats.rx_length_errors++;
+			} else if (si & RXSTATUS_ERROR) {
+				/* Other error */
+				ndev->stats.rx_length_errors++;
+			}
+			ndev->stats.rx_errors++;
+		} else {
+			/* Packet is good */
+			skb = dev_alloc_skb(len + 8);
+			if (!skb)
+				ndev->stats.rx_dropped++;
+			else {
+				skb_reserve(skb, 8);
+				prdbuf = skb_put(skb, (len - 0));
+
+				/* Copy packet from buffer */
+				memcpy(prdbuf,
+					pldat->rx_buff_v[rxconsidx], len);
+
+				/* Pass to upper layer */
+				skb->protocol = eth_type_trans(skb, ndev);
+				netif_rx(skb);
+				ndev->last_rx = jiffies;
+				ndev->stats.rx_packets++;
+				ndev->stats.rx_bytes += len;
+			}
+		}
+
+		/* Increment consume index */
+		rxconsidx = rxconsidx + 1;
+		if (rxconsidx >= ENET_RX_DESC)
+			rxconsidx = 0;
+		writel((u32)rxconsidx,
+				LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
+		rx_done++;
+	}
+
+	return rx_done;
+}
+
+static int lpc_eth_poll(struct napi_struct *napi, int budget)
+{
+	struct netdata_local *pldat = container_of(napi,
+			struct netdata_local, napi);
+	struct net_device *ndev = pldat->ndev;
+	unsigned long flags;
+	int rx_done = 0;
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	__lpc_handle_xmit(ndev);
+	rx_done = __lpc_handle_recv(ndev, budget);
+
+	if (rx_done < budget) {
+		napi_complete(napi);
+		lpc_eth_enable_int(pldat->net_base);
+	}
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	return rx_done;
+}
+
+static irqreturn_t __lpc_eth_interrupt(int irq, void *dev_id)
+{
+	struct net_device *ndev = dev_id;
+	struct netdata_local *pldat = netdev_priv(ndev);
+	u32 tmp;
+
+	spin_lock(&pldat->lock);
+
+	tmp = readl(LPC_ENET_INTSTATUS(pldat->net_base));
+	/* Clear interrupts */
+	writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base));
+
+	if (likely(napi_schedule_prep(&pldat->napi))) {
+		lpc_eth_disable_int(pldat->net_base);
+		__napi_schedule(&pldat->napi);
+	}
+
+	spin_unlock(&pldat->lock);
+
+	return IRQ_HANDLED;
+}
+
+static int lpc_eth_close(struct net_device *ndev)
+{
+	unsigned long flags;
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	if (netif_msg_ifdown(pldat))
+		dev_dbg(&pldat->pdev->dev, "shutting down %s\n", ndev->name);
+
+	napi_disable(&pldat->napi);
+	netif_stop_queue(ndev);
+
+	if (pldat->phy_dev)
+		phy_stop(pldat->phy_dev);
+
+	spin_lock_irqsave(&pldat->lock, flags);
+	__lpc_eth_reset(pldat);
+	netif_carrier_off(ndev);
+	writel(0, LPC_ENET_MAC1(pldat->net_base));
+	writel(0, LPC_ENET_MAC2(pldat->net_base));
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	__lpc_eth_clock_enable(pldat, 0);
+
+	return 0;
+}
+
+static int lpc_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	u32 len, txidx;
+	u32 *ptxstat;
+	struct txrx_desc_t *ptxrxdesc;
+
+	len = skb->len;
+
+	spin_lock_irq(&pldat->lock);
+
+	if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) {
+		/* This function should never be called when there are no
+		   buffers, log the error */
+		netif_stop_queue(ndev);
+		spin_unlock_irq(&pldat->lock);
+		dev_err(&pldat->pdev->dev,
+			"BUG! TX request when no free TX buffers!\n");
+		return 1;
+	}
+
+	/* Get the next TX descriptor index */
+	txidx = readl(LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
+
+	/* Setup control for the transfer */
+	ptxstat = pldat->tx_stat_v[txidx];
+	*ptxstat = 0;
+	ptxrxdesc = pldat->tx_desc_v[txidx];
+	ptxrxdesc->control =
+		(len - 1) | TXDESC_CONTROL_LAST | TXDESC_CONTROL_INT;
+
+	/* Copy data to the DMA buffer */
+	memcpy(pldat->tx_buff_v[txidx], skb->data, len);
+
+	/* Save the buffer and increment the buffer counter */
+	pldat->skb[txidx] = skb;
+	pldat->num_used_tx_buffs++;
+
+	/* Start transmit */
+	txidx++;
+	if (txidx >= ENET_TX_DESC)
+		txidx = 0;
+	writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
+
+	/* Stop queue if no more TX buffers */
+	if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1))
+		netif_stop_queue(ndev);
+
+	spin_unlock_irq(&pldat->lock);
+	ndev->trans_start = jiffies;
+
+	return 0;
+}
+
+static void lpc_eth_timeout(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	/* This should never happen and indicates a problem */
+	dev_err(&pldat->pdev->dev, "BUG! TX timeout occurred!\n");
+}
+
+static int lpc_set_mac_address(struct net_device *ndev, void *p)
+{
+	struct sockaddr *addr = p;
+	struct netdata_local *pldat = netdev_priv(ndev);
+	unsigned long flags;
+
+	if (!is_valid_ether_addr(addr->sa_data))
+		return -EADDRNOTAVAIL;
+	memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	/* Set station address */
+	__lpc_set_mac(pldat, ndev->dev_addr);
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	return 0;
+}
+
+static void lpc_eth_set_multicast_list(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct netdev_hw_addr_list *mcptr = &ndev->mc;
+	struct netdev_hw_addr *ha;
+	u32 tmp32, hash_val, hashlo, hashhi;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	/* Set station address */
+	__lpc_set_mac(pldat, ndev->dev_addr);
+
+	tmp32 =  LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT;
+
+	if (ndev->flags & IFF_PROMISC)
+		tmp32 |= LPC_RXFLTRW_ACCEPTUNICAST |
+			LPC_RXFLTRW_ACCEPTUMULTICAST;
+	if (ndev->flags & IFF_ALLMULTI)
+		tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICAST;
+
+	if (netdev_hw_addr_list_count(mcptr))
+		tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICASTHASH;
+
+	writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base));
+
+
+	/* Set initial hash table */
+	hashlo = 0x0;
+	hashhi = 0x0;
+
+	/* 64 bits : multicast address in hash table */
+	netdev_hw_addr_list_for_each(ha, mcptr) {
+		hash_val = (ether_crc(6, ha->addr) >> 23) & 0x3F;
+
+		if (hash_val >= 32)
+			hashhi |= 1 << (hash_val - 32);
+		else
+			hashlo |= 1 << hash_val;
+	}
+
+	writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base));
+	writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base));
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+}
+
+static int lpc_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!netif_running(ndev))
+		return -EINVAL;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_mii_ioctl(phydev, req, cmd);
+}
+
+static int lpc_eth_open(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	/* if the phy is not yet registered, retry later*/
+	if (!pldat->phy_dev)
+		return -EAGAIN;
+
+	if (netif_msg_ifup(pldat))
+		dev_dbg(&pldat->pdev->dev, "enabling %s\n", ndev->name);
+
+	if (!is_valid_ether_addr(ndev->dev_addr))
+		return -EADDRNOTAVAIL;
+
+	__lpc_eth_clock_enable(pldat, 1);
+
+	/* Reset and initialize */
+	__lpc_eth_reset(pldat);
+	__lpc_eth_init(pldat);
+
+	/* schedule a link state check */
+	phy_start(pldat->phy_dev);
+	netif_start_queue(ndev);
+	napi_enable(&pldat->napi);
+
+	return 0;
+}
+
+/*
+ * Ethtool ops
+ */
+static void lpc_eth_ethtool_getdrvinfo(struct net_device *ndev,
+	struct ethtool_drvinfo *info)
+{
+	strcpy(info->driver, MODNAME);
+	strcpy(info->version, DRV_VERSION);
+	strcpy(info->bus_info, dev_name(ndev->dev.parent));
+}
+
+static u32 lpc_eth_ethtool_getmsglevel(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	return pldat->msg_enable;
+}
+
+static void lpc_eth_ethtool_setmsglevel(struct net_device *ndev, u32 level)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	pldat->msg_enable = level;
+}
+
+static int lpc_eth_ethtool_getsettings(struct net_device *ndev,
+	struct ethtool_cmd *cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_gset(phydev, cmd);
+}
+
+static int lpc_eth_ethtool_setsettings(struct net_device *ndev,
+	struct ethtool_cmd *cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_ethtool_sset(phydev, cmd);
+}
+
+static const struct ethtool_ops lpc_eth_ethtool_ops = {
+	.get_drvinfo	= lpc_eth_ethtool_getdrvinfo,
+	.get_settings	= lpc_eth_ethtool_getsettings,
+	.set_settings	= lpc_eth_ethtool_setsettings,
+	.get_msglevel	= lpc_eth_ethtool_getmsglevel,
+	.set_msglevel	= lpc_eth_ethtool_setmsglevel,
+	.get_link	= ethtool_op_get_link,
+};
+
+static const struct net_device_ops lpc_netdev_ops = {
+	.ndo_open		= lpc_eth_open,
+	.ndo_stop		= lpc_eth_close,
+	.ndo_start_xmit		= lpc_eth_hard_start_xmit,
+	.ndo_set_rx_mode	= lpc_eth_set_multicast_list,
+	.ndo_do_ioctl		= lpc_eth_ioctl,
+	.ndo_tx_timeout		= lpc_eth_timeout,
+	.ndo_set_mac_address	= lpc_set_mac_address,
+};
+
+static int lpc_eth_drv_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct resource *dma_res;
+	struct net_device *ndev;
+	struct netdata_local *pldat;
+	struct phy_device *phydev;
+	dma_addr_t dma_handle;
+	int irq, ret;
+
+	/* Get platform resources */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	irq = platform_get_irq(pdev, 0);
+	if ((!res) || (!dma_res) || (irq < 0) || (irq >= NR_IRQS)) {
+		dev_err(&pdev->dev, "error getting resources.\n");
+		ret = -ENXIO;
+		goto err_exit;
+	}
+
+	/* Allocate net driver data structure */
+	ndev = alloc_etherdev(sizeof(struct netdata_local));
+	if (!ndev) {
+		dev_err(&pdev->dev, "could not allocate device.\n");
+		ret = -ENOMEM;
+		goto err_exit;
+	}
+
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	pldat = netdev_priv(ndev);
+	pldat->pdev = pdev;
+	pldat->ndev = ndev;
+
+	spin_lock_init(&pldat->lock);
+
+	/* Save resources */
+	ndev->irq = irq;
+
+	/* Get clock for the device */
+	pldat->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(pldat->clk)) {
+		dev_err(&pdev->dev, "error getting clock.\n");
+		ret = PTR_ERR(pldat->clk);
+		goto err_out_free_dev;
+	}
+
+	/* Enable network clock */
+	__lpc_eth_clock_enable(pldat, 1);
+
+	/* Map IO space */
+	pldat->net_base = ioremap(res->start, res->end - res->start + 1);
+	if (!pldat->net_base) {
+		dev_err(&pdev->dev, "failed to map registers\n");
+		ret = -ENOMEM;
+		goto err_out_disable_clocks;
+	}
+	ret = request_irq(ndev->irq, __lpc_eth_interrupt, 0,
+			  ndev->name, ndev);
+	if (ret) {
+		dev_err(&pdev->dev, "error requesting interrupt.\n");
+		goto err_out_iounmap;
+	}
+
+	/* Fill in the fields of the device structure with ethernet values. */
+	ether_setup(ndev);
+
+	/* Setup driver functions */
+	ndev->netdev_ops = &lpc_netdev_ops;
+	ndev->ethtool_ops = &lpc_eth_ethtool_ops;
+	ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
+
+	/* Get size of DMA buffers/descriptors region */
+	pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE +
+		sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
+	pldat->dma_buff_base_v = 0;
+
+	if (use_iram_for_net()) {
+		dma_handle = dma_res->start;
+		if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
+			pldat->dma_buff_base_v =
+				io_p2v(dma_res->start);
+		else
+			netdev_err(ndev,
+				"IRAM not big enough for net buffers, using SDRAM instead.\n");
+	}
+
+	if (pldat->dma_buff_base_v == 0) {
+		pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size);
+
+		/* Allocate a chunk of memory for the DMA ethernet buffers
+		   and descriptors */
+		pldat->dma_buff_base_v =
+			dma_alloc_coherent(&pldat->pdev->dev,
+						pldat->dma_buff_size,
+						&dma_handle, GFP_KERNEL);
+
+		if (pldat->dma_buff_base_v == NULL) {
+			dev_err(&pdev->dev, "error getting DMA region.\n");
+			ret = -ENOMEM;
+			goto err_out_free_irq;
+		}
+	}
+	pldat->dma_buff_base_p = dma_handle;
+
+	netdev_dbg(ndev, "IO address start     :0x%08x\n",
+			res->start);
+	netdev_dbg(ndev, "IO address size      :%d\n",
+			res->end - res->start + 1);
+	netdev_err(ndev, "IO address (mapped)  :0x%p\n",
+			pldat->net_base);
+	netdev_dbg(ndev, "IRQ number           :%d\n", ndev->irq);
+	netdev_dbg(ndev, "DMA buffer size      :%d\n", pldat->dma_buff_size);
+	netdev_dbg(ndev, "DMA buffer P address :0x%08x\n",
+			pldat->dma_buff_base_p);
+	netdev_dbg(ndev, "DMA buffer V address :0x%p\n",
+			pldat->dma_buff_base_v);
+
+	/* Get MAC address from current HW setting (POR state is all zeros) */
+	__lpc_get_mac(pldat, ndev->dev_addr);
+
+#ifdef CONFIG_OF_NET
+	if (!is_valid_ether_addr(ndev->dev_addr)) {
+		const char *macaddr = of_get_mac_address(pdev->dev.of_node);
+		if (macaddr)
+			memcpy(ndev->dev_addr, macaddr, ETH_ALEN);
+	}
+#endif
+	if (!is_valid_ether_addr(ndev->dev_addr))
+		dev_hw_addr_random(ndev, ndev->dev_addr);
+
+	/* Reset the ethernet controller */
+	__lpc_eth_reset(pldat);
+
+	/* then shut everything down to save power */
+	__lpc_eth_shutdown(pldat);
+
+	/* Set default parameters */
+	pldat->msg_enable = NETIF_MSG_LINK;
+
+	/* Force an MII interface reset and clock setup */
+	__lpc_mii_mngt_reset(pldat);
+
+	/* Force default PHY interface setup in chip, this will probably be
+	   changed by the PHY driver */
+	pldat->link = 0;
+	pldat->speed = 100;
+	pldat->duplex = DUPLEX_FULL;
+	__lpc_params_setup(pldat);
+
+	netif_napi_add(ndev, &pldat->napi, lpc_eth_poll, NAPI_WEIGHT);
+
+	ret = register_netdev(ndev);
+	if (ret) {
+		dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
+		goto err_out_dma_unmap;
+	}
+	platform_set_drvdata(pdev, ndev);
+
+	if (lpc_mii_init(pldat) != 0)
+		goto err_out_unregister_netdev;
+
+	netdev_info(ndev, "LPC mac at 0x%08x irq %d\n",
+	       res->start, ndev->irq);
+
+	phydev = pldat->phy_dev;
+	netdev_info(ndev,
+		"attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
+		phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
+
+	device_init_wakeup(&pdev->dev, 1);
+	device_set_wakeup_enable(&pdev->dev, 0);
+
+	return 0;
+
+err_out_unregister_netdev:
+	platform_set_drvdata(pdev, NULL);
+	unregister_netdev(ndev);
+err_out_dma_unmap:
+	if (!use_iram_for_net() ||
+			pldat->dma_buff_size > lpc32xx_return_iram_size())
+		dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
+			pldat->dma_buff_base_v,
+			pldat->dma_buff_base_p);
+err_out_free_irq:
+	free_irq(ndev->irq, ndev);
+err_out_iounmap:
+	iounmap(pldat->net_base);
+err_out_disable_clocks:
+	clk_disable(pldat->clk);
+	clk_put(pldat->clk);
+err_out_free_dev:
+	free_netdev(ndev);
+err_exit:
+	pr_err("%s: not found (%d).\n", MODNAME, ret);
+	return ret;
+}
+
+static int lpc_eth_drv_remove(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	unregister_netdev(ndev);
+	platform_set_drvdata(pdev, NULL);
+
+	if (!use_iram_for_net() ||
+			pldat->dma_buff_size > lpc32xx_return_iram_size())
+		dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
+			pldat->dma_buff_base_v,
+			pldat->dma_buff_base_p);
+	free_irq(ndev->irq, ndev);
+	iounmap(pldat->net_base);
+	clk_disable(pldat->clk);
+	clk_put(pldat->clk);
+	free_netdev(ndev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int lpc_eth_drv_suspend(struct platform_device *pdev,
+	pm_message_t state)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	if (device_may_wakeup(&pdev->dev))
+		enable_irq_wake(ndev->irq);
+
+	if (ndev) {
+		if (netif_running(ndev)) {
+			netif_device_detach(ndev);
+			__lpc_eth_shutdown(pldat);
+			clk_disable(pldat->clk);
+
+			/*
+			 * Reset again now clock is disable to be sure
+			 * EMC_MDC is down
+			 */
+			__lpc_eth_reset(pldat);
+		}
+	}
+
+	return 0;
+}
+
+static int lpc_eth_drv_resume(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat;
+
+	if (device_may_wakeup(&pdev->dev))
+		disable_irq_wake(ndev->irq);
+
+	if (ndev) {
+		if (netif_running(ndev)) {
+			pldat = netdev_priv(ndev);
+
+			/* Enable interface clock */
+			clk_enable(pldat->clk);
+
+			/* Reset and initialize */
+			__lpc_eth_reset(pldat);
+			__lpc_eth_init(pldat);
+
+			netif_device_attach(ndev);
+		}
+	}
+
+	return 0;
+}
+#endif
+
+static struct platform_driver lpc_eth_driver = {
+	.probe		= lpc_eth_drv_probe,
+	.remove		= __devexit_p(lpc_eth_drv_remove),
+#ifdef CONFIG_PM
+	.suspend	= lpc_eth_drv_suspend,
+	.resume		= lpc_eth_drv_resume,
+#endif
+	.driver		= {
+		.name	= MODNAME,
+	},
+};
+
+module_platform_driver(lpc_eth_driver);
+
+MODULE_AUTHOR("Kevin Wells <kevin.wells at nxp.com>");
+MODULE_AUTHOR("Roland Stigge <stigge at antcom.de>");
+MODULE_DESCRIPTION("LPC Ethernet Driver");
+MODULE_LICENSE("GPL");
+


From stigge at antcom.de  Mon Mar  5 16:41:27 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon,  5 Mar 2012 22:41:27 +0100
Subject: [PATCH v4] ARM: LPC32xx: Ethernet support
Message-ID: <1330983687-32678-1-git-send-email-stigge@antcom.de>

This patch adds ethernet support to the LPC32xx ARM architecture. The actual
driver in drivers/net is contained in a separate patch.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Changes from v3:
  * Kconfig default settings adjustment (n is default)
  * Use DEFINE_RES_MEM() and DEFINE_RES_IRQ()
  * Removed platform_data to be presented to the driver (unused anyway)

 arch/arm/mach-lpc32xx/Kconfig              |   25 +++++++++++++++++++++++++
 arch/arm/mach-lpc32xx/clock.c              |    2 +-
 arch/arm/mach-lpc32xx/common.c             |   21 +++++++++++++++++++++
 arch/arm/mach-lpc32xx/common.h             |    4 ++--
 arch/arm/mach-lpc32xx/include/mach/board.h |   24 ++++++++++++++++++++++++
 arch/arm/mach-lpc32xx/irq.c                |    4 ++++
 arch/arm/mach-lpc32xx/phy3250.c            |    2 ++
 7 files changed, 79 insertions(+), 3 deletions(-)

--- linux-2.6.orig/arch/arm/mach-lpc32xx/Kconfig
+++ linux-2.6/arch/arm/mach-lpc32xx/Kconfig
@@ -29,5 +29,30 @@ config ARCH_LPC32XX_UART6_SELECT
 
 endmenu
 
+menu "LPC32XX chip components"
+
+config ARCH_LPC32XX_IRAM_FOR_NET
+	bool "Use IRAM for network buffers"
+	default y
+	help
+	  Say Y here to use the LPC internal fast IRAM (i.e. 256KB SRAM) as
+	  network buffer.  If the total combined required buffer sizes is
+	  larger than the size of IRAM, then SDRAM will be used instead.
+
+	  This can be enabled safely if the IRAM is not intended for other
+	  uses.
+
+config ARCH_LPC32XX_MII_SUPPORT
+	bool "Check to enable MII support or leave disabled for RMII support"
+	help
+	  Say Y here to enable MII support, or N for RMII support. Regardless of
+	  which support is selected, the ethernet interface driver needs to be
+	  selected in the device driver networking section.
+
+	  The PHY3250 reference board uses RMII, so users of this board should
+	  say N.
+
+endmenu
+
 endif
 
--- linux-2.6.orig/arch/arm/mach-lpc32xx/clock.c
+++ linux-2.6/arch/arm/mach-lpc32xx/clock.c
@@ -1134,7 +1134,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
 	_REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
 	_REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
-	_REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
+	_REGISTER_CLOCK("lpc-eth.0", NULL, clk_net)
 	_REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
 	_REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
 	_REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
--- linux-2.6.orig/arch/arm/mach-lpc32xx/common.c
+++ linux-2.6/arch/arm/mach-lpc32xx/common.c
@@ -186,6 +186,27 @@ struct platform_device lpc32xx_ohci_devi
 };
 
 /*
+ * Network Support
+ */
+static struct resource net_resources[] = {
+	[0] = DEFINE_RES_MEM(LPC32XX_ETHERNET_BASE, SZ_4K),
+	[1] = DEFINE_RES_MEM(LPC32XX_IRAM_BASE, SZ_128K),
+	[2] = DEFINE_RES_IRQ(IRQ_LPC32XX_ETHERNET),
+};
+
+static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
+struct platform_device lpc32xx_net_device = {
+	.name = "lpc-eth",
+	.id = 0,
+	.dev = {
+		.dma_mask = &lpc32xx_mac_dma_mask,
+		.coherent_dma_mask = 0xffffffffUL,
+	},
+	.num_resources = ARRAY_SIZE(net_resources),
+	.resource = net_resources,
+};
+
+/*
  * Returns the unique ID for the device
  */
 void lpc32xx_get_uid(u32 devid[4])
--- linux-2.6.orig/arch/arm/mach-lpc32xx/common.h
+++ linux-2.6/arch/arm/mach-lpc32xx/common.h
@@ -19,6 +19,7 @@
 #ifndef __LPC32XX_COMMON_H
 #define __LPC32XX_COMMON_H
 
+#include <mach/board.h>
 #include <linux/platform_device.h>
 
 /*
@@ -32,6 +33,7 @@ extern struct platform_device lpc32xx_ts
 extern struct platform_device lpc32xx_adc_device;
 extern struct platform_device lpc32xx_rtc_device;
 extern struct platform_device lpc32xx_ohci_device;
+extern struct platform_device lpc32xx_net_device;
 
 /*
  * Other arch specific structures and functions
@@ -67,8 +69,6 @@ extern u32 clk_get_pclk_div(void);
  */
 extern void lpc32xx_get_uid(u32 devid[4]);
 
-extern u32 lpc32xx_return_iram_size(void);
-
 /*
  * Pointers used for sizing and copying suspend function data
  */
--- /dev/null
+++ linux-2.6/arch/arm/mach-lpc32xx/include/mach/board.h
@@ -0,0 +1,24 @@
+/*
+ * arm/arch/mach-lpc32xx/include/mach/board.h
+ *
+ * Author: Kevin Wells <kevin.wells at nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_BOARD_H
+#define __ASM_ARCH_BOARD_H
+
+extern u32 lpc32xx_return_iram_size(void);
+
+#endif  /* __ASM_ARCH_BOARD_H */
--- linux-2.6.orig/arch/arm/mach-lpc32xx/irq.c
+++ linux-2.6/arch/arm/mach-lpc32xx/irq.c
@@ -150,6 +150,10 @@ static const struct lpc32xx_event_info l
 		.event_group = &lpc32xx_event_int_regs,
 		.mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
 	},
+	[IRQ_LPC32XX_ETHERNET] = {
+		.event_group = &lpc32xx_event_int_regs,
+		.mask = LPC32XX_CLKPWR_INTSRC_MAC_BIT,
+	},
 	[IRQ_LPC32XX_USB_OTG_ATX] = {
 		.event_group = &lpc32xx_event_int_regs,
 		.mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
--- linux-2.6.orig/arch/arm/mach-lpc32xx/phy3250.c
+++ linux-2.6/arch/arm/mach-lpc32xx/phy3250.c
@@ -37,6 +37,7 @@
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
+#include <mach/board.h>
 #include <mach/gpio-lpc32xx.h>
 #include "common.h"
 
@@ -278,6 +279,7 @@ static struct platform_device *phy3250_d
 	&lpc32xx_gpio_led_device,
 	&lpc32xx_adc_device,
 	&lpc32xx_ohci_device,
+	&lpc32xx_net_device,
 };
 
 static struct amba_device *amba_devs[] __initdata = {


From swarren at nvidia.com  Mon Mar  5 16:43:58 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon, 5 Mar 2012 14:43:58 -0700
Subject: [PATCH] ARM: tegra: update defconfig
Message-ID: <1330983838-25327-1-git-send-email-swarren@nvidia.com>

Refresh tegra_defconfig:

New options enabled:
* PERF_EVENTS
* Tegra EMC scaling
* Support for all 4 CPUs on Tegra30
* AUTO_ZRELADDR for unified Tegra20+Tegra30 images
* CPU_FREQ/CPU_IDLE
* BLK_DEV_SR
* INPUT_EVDEV
* Regulators, including fixed, GPIO, TPS6586x
* Audio for Tegra+ALC5632 (for Paz00/Toshiba AC100)
* NVEC (staging, for Paz00/Toshiba AC100)
* IOMMU for Tegra20's GART and Tegra30's SMMU
* TEGRA_AES

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
This is slightly late for 3.4, but hopefully can just squeak in.

 arch/arm/configs/tegra_defconfig |   31 +++++++++++++++++++++----------
 1 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index fd5d304..e7f5241 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -11,11 +11,14 @@ CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_ELF_CORE is not set
 CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
@@ -27,18 +30,20 @@ CONFIG_MACH_PAZ00=y
 CONFIG_MACH_TRIMSLICE=y
 CONFIG_MACH_WARIO=y
 CONFIG_MACH_VENTANA=y
-CONFIG_TEGRA_DEBUG_UARTD=y
-CONFIG_ARM_ERRATA_742230=y
+CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
-CONFIG_NR_CPUS=2
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -68,7 +73,6 @@ CONFIG_IPV6_MULTIPLE_TABLES=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
 CONFIG_AD525X_DPOT=y
 CONFIG_AD525X_DPOT_I2C=y
 CONFIG_ICS932S401=y
@@ -76,6 +80,7 @@ CONFIG_APDS9802ALS=y
 CONFIG_ISL29003=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
@@ -85,8 +90,7 @@ CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
 # CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
+CONFIG_INPUT_EVDEV=y
 # CONFIG_VT is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
@@ -96,13 +100,15 @@ CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
-# CONFIG_I2C_HELPER_AUTO is not set
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
 CONFIG_SPI_TEGRA=y
 CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_TPS6586X=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -116,11 +122,13 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_TEGRA=y
 CONFIG_SND_SOC_TEGRA_WM8903=y
 CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
+CONFIG_SND_SOC_TEGRA_ALC5632=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_TEGRA=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_TEGRA=y
@@ -130,6 +138,11 @@ CONFIG_STAGING=y
 CONFIG_IIO=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_AK8975=y
+CONFIG_MFD_NVEC=y
+CONFIG_KEYBOARD_NVEC=y
+CONFIG_SERIO_NVEC_PS2=y
+CONFIG_TEGRA_IOMMU_GART=y
+CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -143,8 +156,6 @@ CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
@@ -162,9 +173,9 @@ CONFIG_DEBUG_SG=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_AES=y
 CONFIG_CRYPTO_ARC4=y
 CONFIG_CRYPTO_TWOFISH=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_TEGRA_AES=y
 CONFIG_CRC_CCITT=y
 CONFIG_CRC16=y
-- 
1.7.0.4



From tony at atomide.com  Mon Mar  5 16:46:41 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 13:46:41 -0800
Subject: [PATCH V2] mt_ventoux: support for TeeJet Mt.Ventoux board
In-Reply-To: <4F291924.50702@denx.de>
References: <1324940912-18164-3-git-send-email-yanok@emcraft.com>
 <1325027377-13484-1-git-send-email-yanok@emcraft.com>
 <4F291924.50702@denx.de>
Message-ID: <20120305214641.GV12083@atomide.com>

* Stefano Babic <sbabic at denx.de> [120201 02:20]:
> On 28/12/2011 00:09, Ilya Yanok wrote:
> > This patch adds support for TeeJet Mt.Ventoux board based on TAM3517
> > SOM. Supported devices:
> >  - Serial
> >  - Ethernet
> >  - NAND
> >  - USB host
> >  - LCD
> >  - Touchscreen
> >  - CAN controller
> >  - ADC128S converter
> > 
> > Signed-off-by: Ilya Yanok <yanok at emcraft.com>
> > ---
> > 
> > Changes from V1:
> > 
> >  - Fixed indentation (use tabs not spaces)
> >  - Fixed over 80 characters lines
> >  - Added #if defined(CONFIG_SENSORS_ADCXX_MODULE) to allow adcxx to be a
> >    module.
> >  - Fixes for compilation with CONFIG_TOUCHSCREEN_ADS7846!=y
> >   - Added defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
> >   - Moved call to omap_ads7846_init to separate small function
> >   - Register fixed regulator used for touchscreen only if the driver is
> >     enabled
> >  - Changed board name (MT_VENTOUX -> Mt.Ventoux)
> 
> Hi Tony,
> 
> can I ask you about the status of these patches ? I have not seen open
> comments, do you think they can be merged in your tree ?

Yes I can carry some board-*.c files until device tree is
usable for basic features. There's still some hsmmc changes
pending that I'd like to get out of the way before adding
new ones as then it means I have to keep updating those
board files separately.

Regards,

Tony


From tony at atomide.com  Mon Mar  5 16:58:54 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 13:58:54 -0800
Subject: [PATCH] ARM: OMAP2+: GPMC: Export gpmc_enable_hwecc and
 gpmc_calculate_ecc
In-Reply-To: <1329489859-23929-1-git-send-email-walle@corscience.de>
References: <1329489859-23929-1-git-send-email-walle@corscience.de>
Message-ID: <20120305215853.GW12083@atomide.com>

* Bernhard Walle <walle at corscience.de> [120217 06:15]:
> To be able to compile kernel/drivers/mtd/nand/omap2.ko as module, that
> two symbols need to be exported. Otherwise, I get following error
> message
> 
>     ERROR: "gpmc_calculate_ecc" [drivers/mtd/nand/omap2.ko] undefined!
>     ERROR: "gpmc_enable_hwecc" [drivers/mtd/nand/omap2.ko] undefined!
> 
> Signed-off-by: Bernhard Walle <walle at corscience.de>

Thanks applying into fixes-non-critical-part2.

Regards,

Tony

> ---
>  arch/arm/mach-omap2/gpmc.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
> index dfffbbf..00d5108 100644
> --- a/arch/arm/mach-omap2/gpmc.c
> +++ b/arch/arm/mach-omap2/gpmc.c
> @@ -888,6 +888,7 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
>  	gpmc_write_reg(GPMC_ECC_CONFIG, val);
>  	return 0;
>  }
> +EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
>  
>  /**
>   * gpmc_calculate_ecc - generate non-inverted ecc bytes
> @@ -918,3 +919,4 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
>  	gpmc_ecc_used = -EINVAL;
>  	return 0;
>  }
> +EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
> -- 
> 1.7.9.1
> 


From stigge at antcom.de  Mon Mar  5 17:01:10 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon,  5 Mar 2012 23:01:10 +0100
Subject: [PATCH RESEND v3 1/2] GPIO: LPC32xx: Fix missing bit selection mask
Message-ID: <1330984871-411-1-git-send-email-stigge@antcom.de>

Add missing mask to pin bit selection in gpio-lpc32xx.c
(#define GPIO3_PIN_IN_SEL)

Signed-off-by: Roland Stigge <stigge at antcom.de>
Acked-by: Arnd Bergmann <arnd at arndb.de>

---
 drivers/gpio/gpio-lpc32xx.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- linux-2.6.orig/drivers/gpio/gpio-lpc32xx.c
+++ linux-2.6/drivers/gpio/gpio-lpc32xx.c
@@ -59,7 +59,7 @@
 #define GPO3_PIN_TO_BIT(x)			(1 << (x))
 #define GPIO012_PIN_IN_SEL(x, y)		(((x) >> (y)) & 1)
 #define GPIO3_PIN_IN_SHIFT(x)			((x) == 5 ? 24 : 10 + (x))
-#define GPIO3_PIN_IN_SEL(x, y)			((x) >> GPIO3_PIN_IN_SHIFT(y))
+#define GPIO3_PIN_IN_SEL(x, y)			(((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
 #define GPIO3_PIN5_IN_SEL(x)			(((x) >> 24) & 1)
 #define GPI3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)
 


From stigge at antcom.de  Mon Mar  5 17:01:11 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon,  5 Mar 2012 23:01:11 +0100
Subject: [PATCH RESEND v3 2/2] GPIO: LPC32xx: Add output reading to GPO P3
In-Reply-To: <1330984871-411-1-git-send-email-stigge@antcom.de>
References: <1330984871-411-1-git-send-email-stigge@antcom.de>
Message-ID: <1330984871-411-2-git-send-email-stigge@antcom.de>

The chip offers the function to detect the current state of output of the GPO
P3 pins. Useful for reading GPIO output state in Linux' GPIO API, e.g. via
sysfs.

Please note that this only reads back the currently programmed output state,
not the actual electrical level in terms of a GPI function. Finally, GPO3 is
still just an output.

Signed-off-by: Roland Stigge <stigge at antcom.de>
Acked-by: Arnd Bergmann <arnd at arndb.de>

---
 drivers/gpio/gpio-lpc32xx.c |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

--- linux-2.6.orig/drivers/gpio/gpio-lpc32xx.c
+++ linux-2.6/drivers/gpio/gpio-lpc32xx.c
@@ -62,9 +62,11 @@
 #define GPIO3_PIN_IN_SEL(x, y)			(((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
 #define GPIO3_PIN5_IN_SEL(x)			(((x) >> 24) & 1)
 #define GPI3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)
+#define GPO3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)
 
 struct gpio_regs {
 	void __iomem *inp_state;
+	void __iomem *outp_state;
 	void __iomem *outp_set;
 	void __iomem *outp_clr;
 	void __iomem *dir_set;
@@ -145,6 +147,7 @@ static struct gpio_regs gpio_grp_regs_p2
 
 static struct gpio_regs gpio_grp_regs_p3 = {
 	.inp_state	= LPC32XX_GPIO_P3_INP_STATE,
+	.outp_state	= LPC32XX_GPIO_P3_OUTP_STATE,
 	.outp_set	= LPC32XX_GPIO_P3_OUTP_SET,
 	.outp_clr	= LPC32XX_GPIO_P3_OUTP_CLR,
 	.dir_set	= LPC32XX_GPIO_P2_DIR_SET,
@@ -240,6 +243,12 @@ static int __get_gpi_state_p3(struct lpc
 	return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
 }
 
+static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
+	unsigned pin)
+{
+	return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
+}
+
 /*
  * GENERIC_GPIO primitives.
  */
@@ -340,6 +349,13 @@ static void lpc32xx_gpo_set_value(struct
 	__set_gpo_level_p3(group, pin, value);
 }
 
+static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
+{
+	struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+	return __get_gpo_state_p3(group, pin);
+}
+
 static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
 {
 	if (pin < chip->ngpio)
@@ -427,6 +443,7 @@ static struct lpc32xx_gpio_chip lpc32xx_
 			.label			= "gpo_p3",
 			.direction_output	= lpc32xx_gpio_dir_out_always,
 			.set			= lpc32xx_gpo_set_value,
+			.get			= lpc32xx_gpo_get_value,
 			.request		= lpc32xx_gpio_request,
 			.base			= LPC32XX_GPO_P3_GRP,
 			.ngpio			= LPC32XX_GPO_P3_MAX,


From khilman at ti.com  Mon Mar  5 17:02:08 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 05 Mar 2012 14:02:08 -0800
Subject: [GIT PULL] ARM: OMAP: SR cleanups for v3.4
Message-ID: <87wr6yiu5b.fsf@ti.com>

Hi Tony,

Please pull the SmartReflex cleanups for v3.4.

Due to a minor conflict with the devexit patches in your randconfig
branch, this is based there (actually randconfig~2 which is the actual
dependency.)

Special thanks to Jean Pihet for collecting and coordinating all these
fixups.

Kevin


The following changes since commit 149f1d5c8d2fd6879cdf93ca70f1cb745e698a1e:

  ARM: OMAP2+: Fix devexit for smartreflex when CONFIG_HOTPLUG is not set (2012-02-24 08:24:46 -0800)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/cleanup/sr

for you to fetch changes up to 63371faf9198302c7ebd41e7fbe78eb6b57bba86:

  ARM: OMAP3+: SmartReflex: fix error handling (2012-03-05 11:29:27 -0800)

----------------------------------------------------------------
Felipe Balbi (4):
      ARM: OMAP3+: SmartReflex: add missing platform_set_drvdata()
      ARM: OMAP3+: SmartReflex: move late_initcall() closer to its argument
      ARM: OMAP3+: SmartReflex: misc cleanups
      ARM: OMAP3+: SmartReflex: micro-optimization for sanity check

Jean Pihet (2):
      ARM: OMAP3+: SmartReflex: fix the use of debugfs_create_* API
      ARM: OMAP3+: SmartReflex: fix error handling

Nishanth Menon (6):
      ARM: OMAP3+: SmartReflex: fix err interrupt disable sequence
      ARM: OMAP3+: SmartReflex Class3: disable errorgen before disable VP
      ARM: OMAP3+: SmartReflex: Add a shutdown hook
      ARM: OMAP3+: SmartReflex: Fix status masking in ERRCONFIG register
      ARM: OMAP3+: SmartReflex: clear ERRCONFIG_VPBOUNDINTST only on a need
      ARM: OMAP3+: hwmod: add SmartReflex IRQs

Shweta Gulati (1):
      ARM: OMAP3+: SmartReflex: use voltage domain name in device attributes

 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c   |   31 +++-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c   |   19 ++-
 arch/arm/mach-omap2/smartreflex-class3.c     |    1 +
 arch/arm/mach-omap2/smartreflex.c            |  227 +++++++++++++++++++-------
 arch/arm/mach-omap2/smartreflex.h            |   10 ++
 arch/arm/mach-omap2/sr_device.c              |   11 +-
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    2 -
 7 files changed, 229 insertions(+), 72 deletions(-)



From robert.jarzmik at free.fr  Mon Mar  5 17:08:52 2012
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Mon, 05 Mar 2012 23:08:52 +0100
Subject: Status of gpio-pxa driver and dummy clock
In-Reply-To: <CAN1soZxkVSFbNG4QaCxxxbNMB255JeNCK+=YqBzvmAAXdCRYyQ@mail.gmail.com>
 (Haojian Zhuang's message of "Mon, 5 Mar 2012 20:22:41 +0800")
References: <87aa3wu0hp.fsf@free.fr>
 <1330885571.28077.YahooMailClassic@web29015.mail.ird.yahoo.com>
 <CAN1soZxkVSFbNG4QaCxxxbNMB255JeNCK+=YqBzvmAAXdCRYyQ@mail.gmail.com>
Message-ID: <87399mu2dn.fsf@free.fr>

Haojian Zhuang <haojian.zhuang at gmail.com> writes:

> I missed them. Maybe I was not in the Cc list. I'll append the patches
> to fix them.

Just to be sure, this is the patch which is missing for the dummy clock, which
was not submitted before AFAIK (Jonathan, Paul, please confirm).

I added the commit text to Paul's patch, and authored it as Paul's with
Jonathan's report. Again, Jonathan, Paul, I'd like to have your agreement here.

Haojian, if you have another patch ready, don't hesitate to drop this patch and
take your own, as long as gpio-pxa is fixed, I'll be happy.

Cheers.

--
Robert

8>----
>From 505a23475843a8fbac077e789d911ee07e1ae9cc Mon Sep 17 00:00:00 2001
From: Paul Parsons <lost.distance at yahoo.com>
Date: Sat, 3 Mar 2012 21:10:09 +0100
Subject: [PATCH] arch/arm: pxa add dummy clocks for gpio driver

Fix gpio driver by providing it a dummy clock. This
regression was introduced by the commit "ARM: pxa: add dummy
clock for sa1100-rtc", id
a55b5adaf403c4d032e0871ad4ee3367782f4db6.

Reported-by: Jonathan Cameron <jic23 at cam.ac.uk>
Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
Tested-by: Robert Jarzmik <robert.jarzmik at free.fr>
---
 arch/arm/mach-pxa/pxa25x.c |    1 +
 arch/arm/mach-pxa/pxa27x.c |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 00d6eac..d8de3e5 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -208,6 +208,7 @@ static struct clk_lookup pxa25x_clkregs[] = {
 	INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
 	INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
 	INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
+	INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
 };
 
 static struct clk_lookup pxa25x_hwuart_clkreg =
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index c1673b3..a3fabc9 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -229,6 +229,7 @@ static struct clk_lookup pxa27x_clkregs[] = {
 	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
 	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
 	INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
+	INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
 };
 
 #ifdef CONFIG_PM
-- 
1.7.5.4



From stigge at antcom.de  Mon Mar  5 17:10:03 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon,  5 Mar 2012 23:10:03 +0100
Subject: [PATCH v3] ARM: LPC32xx: Fix missing and bad LPC32XX macros
Message-ID: <1330985403-593-1-git-send-email-stigge@antcom.de>

Some of the LPC32XX_* macros were typed ("LCP32XX_*"), which is fixed by this
patch. (Besides another LCP doc typo.)

Further, the LPC32XX_GPIO_P2_MUX_SET/CLR/STATE macros were missing and are
added by this patch.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

 Applies to v3.3-6

 arch/arm/mach-lpc32xx/include/mach/platform.h |   51 +++++++++++++-------------
 arch/arm/mach-lpc32xx/pm.c                    |    2 -
 arch/arm/mach-lpc32xx/timer.c                 |   46 +++++++++++------------
 3 files changed, 51 insertions(+), 48 deletions(-)

--- linux-2.6.orig/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ linux-2.6/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -591,42 +591,42 @@
 /*
  * Timer/counter register offsets
  */
-#define LCP32XX_TIMER_IR(x)			io_p2v((x) + 0x00)
-#define LCP32XX_TIMER_TCR(x)			io_p2v((x) + 0x04)
-#define LCP32XX_TIMER_TC(x)			io_p2v((x) + 0x08)
-#define LCP32XX_TIMER_PR(x)			io_p2v((x) + 0x0C)
-#define LCP32XX_TIMER_PC(x)			io_p2v((x) + 0x10)
-#define LCP32XX_TIMER_MCR(x)			io_p2v((x) + 0x14)
-#define LCP32XX_TIMER_MR0(x)			io_p2v((x) + 0x18)
-#define LCP32XX_TIMER_MR1(x)			io_p2v((x) + 0x1C)
-#define LCP32XX_TIMER_MR2(x)			io_p2v((x) + 0x20)
-#define LCP32XX_TIMER_MR3(x)			io_p2v((x) + 0x24)
-#define LCP32XX_TIMER_CCR(x)			io_p2v((x) + 0x28)
-#define LCP32XX_TIMER_CR0(x)			io_p2v((x) + 0x2C)
-#define LCP32XX_TIMER_CR1(x)			io_p2v((x) + 0x30)
-#define LCP32XX_TIMER_CR2(x)			io_p2v((x) + 0x34)
-#define LCP32XX_TIMER_CR3(x)			io_p2v((x) + 0x38)
-#define LCP32XX_TIMER_EMR(x)			io_p2v((x) + 0x3C)
-#define LCP32XX_TIMER_CTCR(x)			io_p2v((x) + 0x70)
+#define LPC32XX_TIMER_IR(x)			io_p2v((x) + 0x00)
+#define LPC32XX_TIMER_TCR(x)			io_p2v((x) + 0x04)
+#define LPC32XX_TIMER_TC(x)			io_p2v((x) + 0x08)
+#define LPC32XX_TIMER_PR(x)			io_p2v((x) + 0x0C)
+#define LPC32XX_TIMER_PC(x)			io_p2v((x) + 0x10)
+#define LPC32XX_TIMER_MCR(x)			io_p2v((x) + 0x14)
+#define LPC32XX_TIMER_MR0(x)			io_p2v((x) + 0x18)
+#define LPC32XX_TIMER_MR1(x)			io_p2v((x) + 0x1C)
+#define LPC32XX_TIMER_MR2(x)			io_p2v((x) + 0x20)
+#define LPC32XX_TIMER_MR3(x)			io_p2v((x) + 0x24)
+#define LPC32XX_TIMER_CCR(x)			io_p2v((x) + 0x28)
+#define LPC32XX_TIMER_CR0(x)			io_p2v((x) + 0x2C)
+#define LPC32XX_TIMER_CR1(x)			io_p2v((x) + 0x30)
+#define LPC32XX_TIMER_CR2(x)			io_p2v((x) + 0x34)
+#define LPC32XX_TIMER_CR3(x)			io_p2v((x) + 0x38)
+#define LPC32XX_TIMER_EMR(x)			io_p2v((x) + 0x3C)
+#define LPC32XX_TIMER_CTCR(x)			io_p2v((x) + 0x70)
 
 /*
  * ir register definitions
  */
-#define LCP32XX_TIMER_CNTR_MTCH_BIT(n)		(1 << ((n) & 0x3))
-#define LCP32XX_TIMER_CNTR_CAPT_BIT(n)		(1 << (4 + ((n) & 0x3)))
+#define LPC32XX_TIMER_CNTR_MTCH_BIT(n)		(1 << ((n) & 0x3))
+#define LPC32XX_TIMER_CNTR_CAPT_BIT(n)		(1 << (4 + ((n) & 0x3)))
 
 /*
  * tcr register definitions
  */
-#define LCP32XX_TIMER_CNTR_TCR_EN		0x1
-#define LCP32XX_TIMER_CNTR_TCR_RESET		0x2
+#define LPC32XX_TIMER_CNTR_TCR_EN		0x1
+#define LPC32XX_TIMER_CNTR_TCR_RESET		0x2
 
 /*
  * mcr register definitions
  */
-#define LCP32XX_TIMER_CNTR_MCR_MTCH(n)		(0x1 << ((n) * 3))
-#define LCP32XX_TIMER_CNTR_MCR_RESET(n)		(0x1 << (((n) * 3) + 1))
-#define LCP32XX_TIMER_CNTR_MCR_STOP(n)		(0x1 << (((n) * 3) + 2))
+#define LPC32XX_TIMER_CNTR_MCR_MTCH(n)		(0x1 << ((n) * 3))
+#define LPC32XX_TIMER_CNTR_MCR_RESET(n)		(0x1 << (((n) * 3) + 1))
+#define LPC32XX_TIMER_CNTR_MCR_STOP(n)		(0x1 << (((n) * 3) + 2))
 
 /*
  * Standard UART register offsets
@@ -690,5 +690,8 @@
 #define LPC32XX_GPIO_P1_MUX_SET			_GPREG(0x130)
 #define LPC32XX_GPIO_P1_MUX_CLR			_GPREG(0x134)
 #define LPC32XX_GPIO_P1_MUX_STATE		_GPREG(0x138)
+#define LPC32XX_GPIO_P2_MUX_SET			_GPREG(0x028)
+#define LPC32XX_GPIO_P2_MUX_CLR			_GPREG(0x02C)
+#define LPC32XX_GPIO_P2_MUX_STATE		_GPREG(0x030)
 
 #endif
--- linux-2.6.orig/arch/arm/mach-lpc32xx/pm.c
+++ linux-2.6/arch/arm/mach-lpc32xx/pm.c
@@ -13,7 +13,7 @@
 /*
  * LPC32XX CPU and system power management
  *
- * The LCP32XX has three CPU modes for controlling system power: run,
+ * The LPC32XX has three CPU modes for controlling system power: run,
  * direct-run, and halt modes. When switching between halt and run modes,
  * the CPU transistions through direct-run mode. For Linux, direct-run
  * mode is not used in normal operation. Halt mode is used when the
--- linux-2.6.orig/arch/arm/mach-lpc32xx/timer.c
+++ linux-2.6/arch/arm/mach-lpc32xx/timer.c
@@ -34,11 +34,11 @@
 static int lpc32xx_clkevt_next_event(unsigned long delta,
     struct clock_event_device *dev)
 {
-	__raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
-		LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
-	__raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
-	__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
-		LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
+		LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+	__raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
+		LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
 
 	return 0;
 }
@@ -58,7 +58,7 @@ static void lpc32xx_clkevt_mode(enum clo
 		 * disable the timer to wait for the first call to
 		 * set_next_event().
 		 */
-		__raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+		__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
 		break;
 
 	case CLOCK_EVT_MODE_UNUSED:
@@ -81,8 +81,8 @@ static irqreturn_t lpc32xx_timer_interru
 	struct clock_event_device *evt = &lpc32xx_clkevt;
 
 	/* Clear match */
-	__raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
-		LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
+		LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
 
 	evt->event_handler(evt);
 
@@ -128,14 +128,14 @@ static void __init lpc32xx_timer_init(vo
 	clkrate = clkrate / clk_get_pclk_div();
 
 	/* Initial timer setup */
-	__raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
-	__raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
-		LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
-	__raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
-	__raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
-		LCP32XX_TIMER_CNTR_MCR_STOP(0) |
-		LCP32XX_TIMER_CNTR_MCR_RESET(0),
-		LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
+	__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
+		LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+	__raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
+		LPC32XX_TIMER_CNTR_MCR_STOP(0) |
+		LPC32XX_TIMER_CNTR_MCR_RESET(0),
+		LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
 
 	/* Setup tick interrupt */
 	setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
@@ -151,14 +151,14 @@ static void __init lpc32xx_timer_init(vo
 	clockevents_register_device(&lpc32xx_clkevt);
 
 	/* Use timer1 as clock source. */
-	__raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
-		LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
-	__raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
-	__raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
-	__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
-		LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
+		LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+	__raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
+	__raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
+		LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
 
-	clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
+	clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
 		"lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
 }
 


From tony at atomide.com  Mon Mar  5 17:12:47 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 14:12:47 -0800
Subject: [PATCH] arch/arm/plat-omap/clock.c: included linux/debugfs.h twice
In-Reply-To: <1329403433-32327-1-git-send-email-danny.kukawka@bisect.de>
References: <1329403433-32327-1-git-send-email-danny.kukawka@bisect.de>
Message-ID: <20120305221247.GZ12083@atomide.com>

* Danny Kukawka <danny.kukawka at bisect.de> [120216 06:12]:
> arch/arm/plat-omap/clock.c: included 'linux/debugfs.h' twice,
> remove the duplicate.

Thanks, applying into fixes-non-critical-part2.

Regards,

Tony


From tony at atomide.com  Mon Mar  5 17:13:57 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 14:13:57 -0800
Subject: [PATCH] arch/arm/mach-omap2/: included some headers twice
In-Reply-To: <1329403502-32494-1-git-send-email-danny.kukawka@bisect.de>
References: <1329403502-32494-1-git-send-email-danny.kukawka@bisect.de>
Message-ID: <20120305221357.GA12083@atomide.com>

* Danny Kukawka <danny.kukawka at bisect.de> [120216 06:13]:
> arch/arm/mach-omap2/: included some headers tiwce:
> - arch/arm/mach-omap2/board-ldp.c: 'linux/gpio.h'
> - arch/arm/mach-omap2/io.c: 'common.h'
> - arch/arm/mach-omap2/omap_hwmod_44xx_data.c: 'plat/i2c.h'
> 
> Remove the duplicates.

Thanks applying this too.

Regards,

Tony


From tony at atomide.com  Mon Mar  5 17:18:35 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 14:18:35 -0800
Subject: [PATCH] ARM: OMAP2+: Fix module build errors with
 CONFIG_OMAP4_ERRATA_I688
In-Reply-To: <1330686078-9478-1-git-send-email-r.sricharan@ti.com>
References: <1330686078-9478-1-git-send-email-r.sricharan@ti.com>
Message-ID: <20120305221835.GB12083@atomide.com>

* R Sricharan <r.sricharan at ti.com> [120302 02:29]:
> While building modules with randconfig the below errors are observed.
> 
> ERROR: "omap_bus_sync" [drivers/watchdog/sp805_wdt.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/watchdog/dw_wdt.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/virtio/virtio_ring.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/video/sm501fb.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/mon/usbmon.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/host/sl811-hcd.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/host/ohci-hcd.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/host/isp1760.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/host/isp1362-hcd.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/host/isp116x-hcd.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/usb/core/usbcore.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/tty/serial/altera_uart.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/tty/serial/altera_jtaguart.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/tty/serial/8250/8250_dw.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/ssb/ssb.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/rtc/rtc-cmos.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/rtc/rtc-bq4802.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/mtd/nand/tmio_nand.ko] undefined!
> ERROR: "omap_bus_sync" [drivers/mtd/nand/omap2.ko] undefined!

Thanks applying into fixes.

Regards,

Tony


From tony at atomide.com  Mon Mar  5 17:23:38 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 14:23:38 -0800
Subject: [PATCH] ARM: OMAP: don't build hwspinlock in vain
In-Reply-To: <1330859129-354-1-git-send-email-ohad@wizery.com>
References: <1330859129-354-1-git-send-email-ohad@wizery.com>
Message-ID: <20120305222337.GD12083@atomide.com>

* Ohad Ben-Cohen <ohad at wizery.com> [120304 02:34]:
> Cleanup: don't build mach-omap2/hwspinlock.c if the OMAP hwspinlock
> driver isn't configured.
> 
> This will both shorten build time and avoid registering a device
> which isn't needed.

Thanks applying into fixes-non-critical-part2.

Tony


From olof at lixom.net  Mon Mar  5 17:25:21 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 5 Mar 2012 14:25:21 -0800
Subject: [PATCH] ARM: tegra: update defconfig
In-Reply-To: <1330983838-25327-1-git-send-email-swarren@nvidia.com>
References: <1330983838-25327-1-git-send-email-swarren@nvidia.com>
Message-ID: <20120305222521.GA30240@quad.lixom.net>

On Mon, Mar 05, 2012 at 02:43:58PM -0700, Stephen Warren wrote:
> Refresh tegra_defconfig:
> 
> New options enabled:
> * PERF_EVENTS
> * Tegra EMC scaling
> * Support for all 4 CPUs on Tegra30
> * AUTO_ZRELADDR for unified Tegra20+Tegra30 images
> * CPU_FREQ/CPU_IDLE
> * BLK_DEV_SR
> * INPUT_EVDEV
> * Regulators, including fixed, GPIO, TPS6586x
> * Audio for Tegra+ALC5632 (for Paz00/Toshiba AC100)
> * NVEC (staging, for Paz00/Toshiba AC100)
> * IOMMU for Tegra20's GART and Tegra30's SMMU
> * TEGRA_AES
> 
> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> ---
> This is slightly late for 3.4, but hopefully can just squeak in.

Yeah, timing is OK for this, no worries.

I was planning on doing one patch as well, since I want to turn on EXT4 (for
eMMC/SD it's a good idea to use trim). Care to do that in your patch instead so
we only have one update?


Thanks,

-Olof


From jason at lakedaemon.net  Mon Mar  5 17:25:36 2012
From: jason at lakedaemon.net (Jason)
Date: Mon, 5 Mar 2012 17:25:36 -0500
Subject: [PULL REQUEST v2] ARM: kirkwood: fdt: convert kirkwood init
 funcs to fdt
In-Reply-To: <20120305214126.GA18513@lunn.ch>
References: <20120305214126.GA18513@lunn.ch>
Message-ID: <20120305222536.GP5050@titan.lakedaemon.net>

On Mon, Mar 05, 2012 at 10:41:26PM +0100, Andrew Lunn wrote:
> > > If the drivers want to use it, I think it has to be orion_find_tclk for
> > > drivers that are shared between multiple plat-orion platforms.
> > 
> > That's pretty much all of them  :-)
> > 
> > I'll rename it and move it to plat-orion/common.c.  This'll be fun.

This is old, see Nico's reply and my response.

> We have overlapping work going on. My adoption of Mike's generic clk
> framework overlaps a lot with your DT tclk problems. If you introduce
> orion_find_tclk() into all the drivers, we are probably going to rip
> it all out again once my patches go in. Plus we are going to have
> horrible merging conflicts between your code and my code

I'd love to deconflict but I haven't seen your RFC patches, yet.

thx,

Jason.


From b-cousson at ti.com  Mon Mar  5 17:33:32 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 5 Mar 2012 23:33:32 +0100
Subject: [PATCH v2 0/6] gpio/omap: Cleanup and adaptation to Device Tree
In-Reply-To: <1330122091-28113-1-git-send-email-b-cousson@ti.com>
References: <1330122091-28113-1-git-send-email-b-cousson@ti.com>
Message-ID: <4F553F3C.4030909@ti.com>

Hi Grant,

Do you have any comment on this latest update?

I've just seen your that your gpio/next includes irqdomain/next, so I 
guess that I can base my pull request on it directly.

Thanks,
Benoit

On 2/24/2012 11:21 PM, Benoit Cousson wrote:
> Hi Grant,
>
> Here are a couple of GPIO cleanup + the DT adaptation patches.
> This update (compared to v1 [1]) is adding an extra fix for SPARSE_IRQ support
> and add the second cell in the binding for GPIO IRQ type that was missing
> previously whereas the driver does support it.
>
> This series is based on 3.3-rc4 + for_3.4/dt_base branch to get
> the needed cleanup and fixes for OMAP.
>
> The interrupt controller support is using irq_domain_add_legacy for
> the moment and will be updated next to use irqchip irq_domain.
>
> It requires the irq_domain generalization and refinement series
> available at:
>    git://git.secretlab.ca/git/linux-2.6 irqdomain/next
>
> It requires as well Tarun's GPIO cleanup series available at:
>    git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_cleanup_fixes_v9
>
> This series is available here for reference:
>    git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/dt_gpio
>
> Regards,
> Benoit
>
> [1] http://www.spinics.net/lists/linux-omap/msg64694.html
>
>
> Benoit Cousson (6):
>    gpio/omap: Remove bank->id information and misc cleanup
>    gpio/omap: Use devm_ API and add request_mem_region
>    gpio/omap: Add DT support to GPIO driver
>    gpio/omap: Fix IRQ handling for SPARSE_IRQ
>    arm/dts: OMAP4: Add gpio nodes
>    arm/dts: OMAP3: Add gpio nodes
>
>   .../devicetree/bindings/gpio/gpio-omap.txt         |   36 ++++
>   arch/arm/boot/dts/omap3.dtsi                       |   54 +++++
>   arch/arm/boot/dts/omap4.dtsi                       |   54 +++++
>   arch/arm/mach-omap2/gpio.c                         |    8 +-
>   arch/arm/plat-omap/include/plat/gpio.h             |   22 +--
>   drivers/gpio/gpio-omap.c                           |  208 ++++++++++++++------
>   6 files changed, 304 insertions(+), 78 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/gpio/gpio-omap.txt
>



From paul.gortmaker at windriver.com  Mon Mar  5 17:41:47 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Mon,  5 Mar 2012 17:41:47 -0500
Subject: [PATCH 0/3] arm: fix build breakage in omap2plus_defconfig
 (linux-next)
Message-ID: <1330987310-8108-1-git-send-email-paul.gortmaker@windriver.com>

I decided to look at why this thing was dying in linux-next for
over two weeks now:

http://kisskb.ellerman.id.au/kisskb/target/5581/

The git bisect led me to sfr's merge (661a40a5c8 in March5th tree)
of 'arm-soc/for-next' but there was nothing suspicious there, and
the fix (commit #1) was reasonably obvious, so I didn't investigate
the root cause further.  But that wasn't where the breakage ended...

Commit #2, and especially commit #3 need to be looked at by those
who know the platform.  It looks like some sort of conversion to
better share code was done, but the omap4panda part didn't get
the full attention it needed.  I did what I think looks right,
based on what was done for the other board, but I've no knowledge
of the platform whatsoever, and hence no confidence it would
work as desired.  I've hopefully put the right people on the CC
list for those.

Paul.
---

Paul Gortmaker (3):
  arm: anticipate build breakages due in pending merge
  arm: fix compile error in mach-omap2/board-omap4panda.c
  arm: more fallout from i2c conversions in board-omap4panda.c

 arch/arm/mach-omap2/board-omap4panda.c |    7 +++----
 arch/arm/mach-omap2/cm2xxx_3xxx.c      |    2 ++
 arch/arm/mach-omap2/common.c           |    1 +
 arch/arm/mach-omap2/control.c          |    1 +
 arch/arm/mach-omap2/sdrc2xxx.c         |    1 +
 5 files changed, 8 insertions(+), 4 deletions(-)

-- 
1.7.9.1



From paul.gortmaker at windriver.com  Mon Mar  5 17:41:49 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Mon,  5 Mar 2012 17:41:49 -0500
Subject: [PATCH 2/3] arm: fix compile error in mach-omap2/board-omap4panda.c
In-Reply-To: <1330987310-8108-1-git-send-email-paul.gortmaker@windriver.com>
References: <1330987310-8108-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <1330987310-8108-3-git-send-email-paul.gortmaker@windriver.com>

The commit 3c90c98a1ebbb08d95700ce8a3b7bce6286607bd (linux-next)

    "OMAP4: omap4panda: Enable audio support"

introduced population of a new struct, but chose the wrong (but
similarly named) struct that has none of the named fields.

Change it to the struct with those fields, to fix:

arch/arm/mach-omap2/board-omap4panda.c:284: error: unknown field 'hs_left_step' specified in initializer
arch/arm/mach-omap2/board-omap4panda.c:285: error: unknown field 'hs_right_step' specified in initializer
arch/arm/mach-omap2/board-omap4panda.c:286: error: unknown field 'hf_left_step' specified in initializer
arch/arm/mach-omap2/board-omap4panda.c:287: error: unknown field 'hf_right_step' specified in initializer
arch/arm/mach-omap2/board-omap4panda.c:287: warning: large integer implicitly truncated to unsigned type

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
CC: Peter Ujfalusi <peter.ujfalusi at ti.com>
CC: Santosh Shilimkar <santosh.shilimkar at ti.com>
CC: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-omap4panda.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index c1a852d..e919153 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -279,7 +279,7 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
 	return 0;
 }
 
-static struct twl4030_codec_data twl6040_codec = {
+static struct twl6040_codec_data twl6040_codec = {
 	/* single-step ramp for headset and handsfree */
 	.hs_left_step	= 0x0f,
 	.hs_right_step	= 0x0f,
-- 
1.7.9.1



From paul.gortmaker at windriver.com  Mon Mar  5 17:41:50 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Mon,  5 Mar 2012 17:41:50 -0500
Subject: [PATCH 3/3] arm: more fallout from i2c conversions in
 board-omap4panda.c
In-Reply-To: <1330987310-8108-1-git-send-email-paul.gortmaker@windriver.com>
References: <1330987310-8108-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <1330987310-8108-4-git-send-email-paul.gortmaker@windriver.com>

Commit ded0df8510778a03a2f182a0cbfe3c25788e8852 (linux-next)

   "mfd: Convert twl6040 to an i2c driver, and separate it from twl core"

appears to have done an incomplete conversion on the board-omap4panda.c
file, leaving it with more build failures.  Comparing the changes that
were done for board-4430sdp.c it is possible for me to whack it with a
stick until it stops twitching, but someone who really understands this
code needs to take a look at the conversion, and check it is done
completely and in a way that will actually work on hardware.

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
CC: Peter Ujfalusi <peter.ujfalusi at ti.com>
CC: Mark Brown <broonie at opensource.wolfsonicro.com>
CC: Samuel Ortiz <sameo at linux.intel.com>
---
 arch/arm/mach-omap2/board-omap4panda.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index e919153..16a1814 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -287,16 +287,15 @@ static struct twl6040_codec_data twl6040_codec = {
 	.hf_right_step	= 0x1d,
 };
 
-static struct twl4030_audio_data twl6040_audio = {
+static struct twl6040_platform_data twl6040_data = {
 	.codec		= &twl6040_codec,
 	.audpwron_gpio	= 127,
-	.naudint_irq	= OMAP44XX_IRQ_SYS_2N,
 	.irq_base	= TWL6040_CODEC_IRQ_BASE,
 };
 
 /* Panda board uses the common PMIC configuration */
 static struct twl4030_platform_data omap4_panda_twldata = {
-	.audio		= &twl6040_audio,
+   /*	.audio		= &twl6040_audio,	*/
 };
 
 /*
-- 
1.7.9.1



From paul.gortmaker at windriver.com  Mon Mar  5 17:41:48 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Mon,  5 Mar 2012 17:41:48 -0500
Subject: [PATCH 1/3] arm: anticipate build breakages due in pending merge
In-Reply-To: <1330987310-8108-1-git-send-email-paul.gortmaker@windriver.com>
References: <1330987310-8108-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <1330987310-8108-2-git-send-email-paul.gortmaker@windriver.com>

Testing in linux-next has revealed that the omap2plus_defconfig
will fail upon the merge of "arm-soc/for-next" as follows:

arch/arm/mach-omap2/control.c:238: error: 'OMAP343X_CTRL_BASE' undeclared (first use in this function)
arch/arm/mach-omap2/common.c:48: error: 'OMAP2420_SDRC_BASE' undeclared here (not in a function)
arch/arm/mach-omap2/common.c:49: error: 'OMAP2420_SMS_BASE' undeclared here (not in a function)
arch/arm/mach-omap2/common.c:50: error: 'OMAP242X_CTRL_BASE' undeclared here (not in a function)
 [...]
arch/arm/mach-omap2/common.c:167: error: 'OMAP4430_CM2_BASE' undeclared here (not in a function)
arch/arm/mach-omap2/sdrc2xxx.c:108: error: 'OMAP2420_PRM_BASE' undeclared (first use in this function)
arch/arm/mach-omap2/cm2xxx_3xxx.c:310: error: 'OMAP3430_CM_BASE' undeclared (first use in this function)

It appears that a once implicit path to <plat/hardware.h> has gone
away once two of the arm streams come together.

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
---
 arch/arm/mach-omap2/cm2xxx_3xxx.c |    2 ++
 arch/arm/mach-omap2/common.c      |    1 +
 arch/arm/mach-omap2/control.c     |    1 +
 arch/arm/mach-omap2/sdrc2xxx.c    |    1 +
 4 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index c79ed63..389f9f8 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -18,6 +18,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
+#include <plat/hardware.h>
+
 #include "iomap.h"
 #include "common.h"
 #include "cm.h"
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 93419de..d620362 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -20,6 +20,7 @@
 #include <plat/board.h>
 #include <plat/mux.h>
 #include <plat/clock.h>
+#include <plat/hardware.h>
 
 #include "iomap.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 2fd5fd1..18ff359 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -16,6 +16,7 @@
 #include <linux/io.h>
 
 #include <plat/sdrc.h>
+#include <plat/hardware.h>
 
 #include "iomap.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 2c329a6..181b0c5 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -27,6 +27,7 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
+#include <plat/hardware.h>
 
 #include "iomap.h"
 #include "common.h"
-- 
1.7.9.1



From bhutchings at solarflare.com  Mon Mar  5 17:45:24 2012
From: bhutchings at solarflare.com (Ben Hutchings)
Date: Mon, 5 Mar 2012 22:45:24 +0000
Subject: [PATCH v4] lpc32xx: Added ethernet driver
In-Reply-To: <1330983641-32622-1-git-send-email-stigge@antcom.de>
References: <1330983641-32622-1-git-send-email-stigge@antcom.de>
Message-ID: <1330987524.2538.61.camel@bwh-desktop>

On Mon, 2012-03-05 at 22:40 +0100, Roland Stigge wrote:
[...]
> --- /dev/null
> +++ linux-2.6/drivers/net/ethernet/nxp/lpc_eth.c
[...]
> +/*
> + * Transmit timeout, default 2.5 seconds.
> + */
> +static int watchdog = 2500;
> +module_param(watchdog, int, 0400);
> +MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");

Why does this need to be a parameter?

> +/*
> + * Structure of a TX/RX descriptors and RX status
> + */
> +struct txrx_desc_t {
> +	volatile u32 packet;
> +	volatile u32 control;
> +};
> +struct rx_status_t {
> +	volatile u32 statusinfo;
> +	volatile u32 statushashcrc;
> +};

Use of volatile here is probably wrong; see
Documentation/volatile-considered-harmful.txt.

> +/*
> + * Device driver data structure
> + */
> +struct netdata_local {
> +	struct platform_device	*pdev;
> +	struct net_device	*ndev;
> +	spinlock_t		lock;
> +	void __iomem		*net_base;
> +	u32			msg_enable;
> +	struct sk_buff		*skb[ENET_TX_DESC];
> +	unsigned int		last_tx_idx;
> +	unsigned int		num_used_tx_buffs;
> +	struct mii_bus		*mii_bus;
> +	struct phy_device	*phy_dev;
> +	struct clk		*clk;
> +	dma_addr_t		dma_buff_base_p;
> +	void			*dma_buff_base_v;
> +	size_t			dma_buff_size;
> +	struct txrx_desc_t	*tx_desc_v[ENET_TX_DESC];
> +	u32			*tx_stat_v[ENET_TX_DESC];
> +	void			*tx_buff_v[ENET_TX_DESC];
> +	struct txrx_desc_t	*rx_desc_v[ENET_RX_DESC];
> +	struct rx_status_t	*rx_stat_v[ENET_RX_DESC];
> +	void			*rx_buff_v[ENET_RX_DESC];

Why are these 6 members defined as arrays of pointers and not single
pointers to arrays?  It appears that each array element is initialised
to point into an array and then never changed; for example
tx_desc_v[i] == tx_desc_v[0] + i.

[...]
> +static void __lpc_eth_init(struct netdata_local *pldat)
> +{
[...]
> +	/* Clear and enable interrupts */
> +	writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
> +	lpc_eth_enable_int(pldat->net_base);
> +
> +	/* Get the next TX buffer output index */
> +	pldat->num_used_tx_buffs = 0;
> +	pldat->last_tx_idx =
> +		readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));

Doesn't this need to be done *before* enabling interrupts?  Also, I
think you need an smp_wmb() so that the interrupt handler is guaranteed
to see all these writes.

[...]
> +static void lpc_handle_link_change(struct net_device *ndev)
> +{
> +	struct netdata_local *pldat = netdev_priv(ndev);
> +	struct phy_device *phydev = pldat->phy_dev;
> +	unsigned long flags;
> +
> +	int status_change = 0;

This is logically a boolean, so use bool/true/false.

[...]
> +static void __lpc_handle_xmit(struct net_device *ndev)
> +{
[...]
> +		/* Any errors occurred? */
> +		if (txstat & TXSTATUS_ERROR) {
> +			if (txstat & TXSTATUS_UNDERRUN) {
> +				/* FIFO underrun */
> +				ndev->stats.tx_fifo_errors++;
> +			}
> +			if (txstat & TXSTATUS_LATECOLL) {
> +				/* Late collision */
> +				ndev->stats.tx_aborted_errors++;
> +			}
> +			if (txstat & TXSTATUS_EXCESSCOLL) {
> +				/* Excessive collision */
> +				ndev->stats.tx_aborted_errors++;
> +			}
> +			if (txstat & TXSTATUS_EXCESSDEFER) {
> +				/* Defer limit */
> +				ndev->stats.tx_aborted_errors++;
> +			}
> +			ndev->stats.tx_errors++;
> +
> +			/* Buffer transmit failed, requeue it */
> +			lpc_eth_hard_start_xmit(skb, ndev);

It is not the responsibility of an Ethernet network driver to retry
transmission.  Also, this will deadlock on an SMP system since
lpc_eth_hard_start_xmit() will try to acquire pldat->lock which is
already held.  I suggest you test with lockdep in case there any other
such bugs which are being masked by running on a UP system.

[...]
> +static int __lpc_handle_recv(struct net_device *ndev, int budget)
> +{
[...]
> +			/* Packet is good */
> +			skb = dev_alloc_skb(len + 8);
> +			if (!skb)
> +				ndev->stats.rx_dropped++;
> +			else {
> +				skb_reserve(skb, 8);

What are you reserving this space for?

> +				prdbuf = skb_put(skb, (len - 0));

len - 0??

> +				/* Copy packet from buffer */
> +				memcpy(prdbuf,
> +					pldat->rx_buff_v[rxconsidx], len);
> +
> +				/* Pass to upper layer */
> +				skb->protocol = eth_type_trans(skb, ndev);
> +				netif_rx(skb);
> +				ndev->last_rx = jiffies;

Drivers don't need to set last_rx any more.

[...]
> +static int lpc_eth_poll(struct napi_struct *napi, int budget)
> +{
> +	struct netdata_local *pldat = container_of(napi,
> +			struct netdata_local, napi);
> +	struct net_device *ndev = pldat->ndev;
> +	unsigned long flags;
> +	int rx_done = 0;
> +
> +	spin_lock_irqsave(&pldat->lock, flags);
> +
> +	__lpc_handle_xmit(ndev);
> +	rx_done = __lpc_handle_recv(ndev, budget);
> +
> +	if (rx_done < budget) {
> +		napi_complete(napi);
> +		lpc_eth_enable_int(pldat->net_base);
> +	}
> +
> +	spin_unlock_irqrestore(&pldat->lock, flags);

This is really sad.  You implement NAPI but then take away most of the
benefits of that by disabling interrupts.

It looks like you could safely unlock pldat->lock before calling
__lpc_handle_recv - nothing else manipulates RX queue state so no lock
is required.

As for the TX side, you can probably use the TX queue lock
(__netif_tx_lock, __netif_tx_unlock) to serialise with
lpc_eth_hard_start_xmit() and avoid taking pldat->lock in either
__lpc_handle_xmit() or here.

[...]
> +	return rx_done;
> +}
> +
> +static irqreturn_t __lpc_eth_interrupt(int irq, void *dev_id)
> +{
> +	struct net_device *ndev = dev_id;
> +	struct netdata_local *pldat = netdev_priv(ndev);
> +	u32 tmp;
> +
> +	spin_lock(&pldat->lock);
> +
> +	tmp = readl(LPC_ENET_INTSTATUS(pldat->net_base));
> +	/* Clear interrupts */
> +	writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base));
> +
> +	if (likely(napi_schedule_prep(&pldat->napi))) {
> +		lpc_eth_disable_int(pldat->net_base);
> +		__napi_schedule(&pldat->napi);
> +	}

I think you need to mask the interrupt unconditionally here.  See my
next comment.

> +	spin_unlock(&pldat->lock);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int lpc_eth_close(struct net_device *ndev)
> +{
> +	unsigned long flags;
> +	struct netdata_local *pldat = netdev_priv(ndev);
> +
> +	if (netif_msg_ifdown(pldat))
> +		dev_dbg(&pldat->pdev->dev, "shutting down %s\n", ndev->name);
> +
> +	napi_disable(&pldat->napi);

If an interrupt is received after this returns, napi_schedule_prep()
will return false and the interrupt will not be masked.

There is a similar problem in lpc_eth_open() where you enable interrupts
before NAPI.

> +	netif_stop_queue(ndev);
> +
> +	if (pldat->phy_dev)
> +		phy_stop(pldat->phy_dev);
> +
> +	spin_lock_irqsave(&pldat->lock, flags);
> +	__lpc_eth_reset(pldat);
> +	netif_carrier_off(ndev);
> +	writel(0, LPC_ENET_MAC1(pldat->net_base));
> +	writel(0, LPC_ENET_MAC2(pldat->net_base));
> +	spin_unlock_irqrestore(&pldat->lock, flags);
> +
> +	__lpc_eth_clock_enable(pldat, 0);
> +
> +	return 0;
> +}
[...]
> +static int lpc_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
> +{
> +	struct netdata_local *pldat = netdev_priv(ndev);
> +	u32 len, txidx;
> +	u32 *ptxstat;
> +	struct txrx_desc_t *ptxrxdesc;
> +
> +	len = skb->len;
> +
> +	spin_lock_irq(&pldat->lock);
> +
> +	if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) {
> +		/* This function should never be called when there are no
> +		   buffers, log the error */

So use WARN to make the error really obvious.

> +		netif_stop_queue(ndev);
> +		spin_unlock_irq(&pldat->lock);
> +		dev_err(&pldat->pdev->dev,
> +			"BUG! TX request when no free TX buffers!\n");
> +		return 1;

This is not a valid return value; you need to return NETDEV_TX_BUSY.

> +	}
> +
> +	/* Get the next TX descriptor index */
> +	txidx = readl(LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
> +
> +	/* Setup control for the transfer */
> +	ptxstat = pldat->tx_stat_v[txidx];
> +	*ptxstat = 0;
> +	ptxrxdesc = pldat->tx_desc_v[txidx];
> +	ptxrxdesc->control =
> +		(len - 1) | TXDESC_CONTROL_LAST | TXDESC_CONTROL_INT;
> +
> +	/* Copy data to the DMA buffer */
> +	memcpy(pldat->tx_buff_v[txidx], skb->data, len);
> +
> +	/* Save the buffer and increment the buffer counter */
> +	pldat->skb[txidx] = skb;
> +	pldat->num_used_tx_buffs++;
> +
> +	/* Start transmit */
> +	txidx++;
> +	if (txidx >= ENET_TX_DESC)
> +		txidx = 0;
> +	writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
> +
> +	/* Stop queue if no more TX buffers */
> +	if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1))
> +		netif_stop_queue(ndev);
> +
> +	spin_unlock_irq(&pldat->lock);
> +	ndev->trans_start = jiffies;

Drivers don't need to set trans_start any more.

> +	return 0;

NETDEV_TX_OK

> +}
[...]
> +static void lpc_eth_timeout(struct net_device *ndev)
> +{
> +	struct netdata_local *pldat = netdev_priv(ndev);
> +
> +	/* This should never happen and indicates a problem */
> +	dev_err(&pldat->pdev->dev, "BUG! TX timeout occurred!\n");
> +}

The networking core will print a big fat warning before calling this
function, so this message is redundant.  Also, timeout isn't necessarily
a bug; it can be caused by a misconfigured switch.

[...]
> +static int lpc_eth_ethtool_getsettings(struct net_device *ndev,
> +	struct ethtool_cmd *cmd)
> +{
> +	struct netdata_local *pldat = netdev_priv(ndev);
> +	struct phy_device *phydev = pldat->phy_dev;
> +
> +	if (!phydev)
> +		return -ENODEV;

-EOPNOTSUPP

> +	return phy_ethtool_gset(phydev, cmd);
> +}
> +
> +static int lpc_eth_ethtool_setsettings(struct net_device *ndev,
> +	struct ethtool_cmd *cmd)
> +{
> +	struct netdata_local *pldat = netdev_priv(ndev);
> +	struct phy_device *phydev = pldat->phy_dev;
> +
> +	if (!phydev)
> +		return -ENODEV;
[...]

-EOPNOTSUPP

Ben.

-- 
Ben Hutchings, Staff Engineer, Solarflare
Not speaking for my employer; that's the marketing department's job.
They asked us to note that Solarflare product names are trademarked.



From tony at atomide.com  Mon Mar  5 17:45:35 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 14:45:35 -0800
Subject: [PATCH 1/3] arm: anticipate build breakages due in pending merge
In-Reply-To: <1330987310-8108-2-git-send-email-paul.gortmaker@windriver.com>
References: <1330987310-8108-1-git-send-email-paul.gortmaker@windriver.com>
 <1330987310-8108-2-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <20120305224534.GG12083@atomide.com>

* Paul Gortmaker <paul.gortmaker at windriver.com> [120305 14:10]:
> Testing in linux-next has revealed that the omap2plus_defconfig
> will fail upon the merge of "arm-soc/for-next" as follows:
> 
> arch/arm/mach-omap2/control.c:238: error: 'OMAP343X_CTRL_BASE' undeclared (first use in this function)
> arch/arm/mach-omap2/common.c:48: error: 'OMAP2420_SDRC_BASE' undeclared here (not in a function)
> arch/arm/mach-omap2/common.c:49: error: 'OMAP2420_SMS_BASE' undeclared here (not in a function)
> arch/arm/mach-omap2/common.c:50: error: 'OMAP242X_CTRL_BASE' undeclared here (not in a function)
>  [...]
> arch/arm/mach-omap2/common.c:167: error: 'OMAP4430_CM2_BASE' undeclared here (not in a function)
> arch/arm/mach-omap2/sdrc2xxx.c:108: error: 'OMAP2420_PRM_BASE' undeclared (first use in this function)
> arch/arm/mach-omap2/cm2xxx_3xxx.c:310: error: 'OMAP3430_CM_BASE' undeclared (first use in this function)
> 
> It appears that a once implicit path to <plat/hardware.h> has gone
> away once two of the arm streams come together.

Thanks this one is already waiting to be applied to arm-soc
tree.

Regards,

Tony


From tony at atomide.com  Mon Mar  5 17:46:28 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 14:46:28 -0800
Subject: [PATCH 2/3] arm: fix compile error in
 mach-omap2/board-omap4panda.c
In-Reply-To: <1330987310-8108-3-git-send-email-paul.gortmaker@windriver.com>
References: <1330987310-8108-1-git-send-email-paul.gortmaker@windriver.com>
 <1330987310-8108-3-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <20120305224628.GH12083@atomide.com>

* Paul Gortmaker <paul.gortmaker at windriver.com> [120305 14:10]:
> The commit 3c90c98a1ebbb08d95700ce8a3b7bce6286607bd (linux-next)
> 
>     "OMAP4: omap4panda: Enable audio support"
> 
> introduced population of a new struct, but chose the wrong (but
> similarly named) struct that has none of the named fields.
> 
> Change it to the struct with those fields, to fix:
> 
> arch/arm/mach-omap2/board-omap4panda.c:284: error: unknown field 'hs_left_step' specified in initializer
> arch/arm/mach-omap2/board-omap4panda.c:285: error: unknown field 'hs_right_step' specified in initializer
> arch/arm/mach-omap2/board-omap4panda.c:286: error: unknown field 'hf_left_step' specified in initializer
> arch/arm/mach-omap2/board-omap4panda.c:287: error: unknown field 'hf_right_step' specified in initializer
> arch/arm/mach-omap2/board-omap4panda.c:287: warning: large integer implicitly truncated to unsigned type

Thanks, this mis-merge is something Peter should take a look at
as it seems there's few other parts that got left out.

Regards,

Tony
 
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> CC: Peter Ujfalusi <peter.ujfalusi at ti.com>
> CC: Santosh Shilimkar <santosh.shilimkar at ti.com>
> CC: Tony Lindgren <tony at atomide.com>
> ---
>  arch/arm/mach-omap2/board-omap4panda.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
> index c1a852d..e919153 100644
> --- a/arch/arm/mach-omap2/board-omap4panda.c
> +++ b/arch/arm/mach-omap2/board-omap4panda.c
> @@ -279,7 +279,7 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
>  	return 0;
>  }
>  
> -static struct twl4030_codec_data twl6040_codec = {
> +static struct twl6040_codec_data twl6040_codec = {
>  	/* single-step ramp for headset and handsfree */
>  	.hs_left_step	= 0x0f,
>  	.hs_right_step	= 0x0f,
> -- 
> 1.7.9.1
> 


From lost.distance at yahoo.com  Mon Mar  5 17:48:37 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Mon, 5 Mar 2012 22:48:37 +0000 (GMT)
Subject: Status of gpio-pxa driver and dummy clock
In-Reply-To: <87399mu2dn.fsf@free.fr>
Message-ID: <1330987717.23600.YahooMailClassic@web29008.mail.ird.yahoo.com>

--- On Mon, 5/3/12, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
> Date: Monday, 5 March, 2012, 22:08
> Haojian Zhuang <haojian.zhuang at gmail.com>
> writes:
> 
> > I missed them. Maybe I was not in the Cc list. I'll
> append the patches
> > to fix them.
> 
> Just to be sure, this is the patch which is missing for the
> dummy clock, which
> was not submitted before AFAIK (Jonathan, Paul, please
> confirm).
> 
> I added the commit text to Paul's patch, and authored it as
> Paul's with
> Jonathan's report. Again, Jonathan, Paul, I'd like to have
> your agreement here.
> 
> Haojian, if you have another patch ready, don't hesitate to
> drop this patch and
> take your own, as long as gpio-pxa is fixed, I'll be happy.

I created this patch without waiting for an official fix purely to solve
the problem for myself. I then posted it in case it would be useful to
others. By all means use it or, if a better patch exists, drop it.

> Cheers.
> 
> --
> Robert
> 
> 8>----
> From 505a23475843a8fbac077e789d911ee07e1ae9cc Mon Sep 17
> 00:00:00 2001
> From: Paul Parsons <lost.distance at yahoo.com>
> Date: Sat, 3 Mar 2012 21:10:09 +0100
> Subject: [PATCH] arch/arm: pxa add dummy clocks for gpio
> driver
> 
> Fix gpio driver by providing it a dummy clock. This
> regression was introduced by the commit "ARM: pxa: add
> dummy
> clock for sa1100-rtc", id
> a55b5adaf403c4d032e0871ad4ee3367782f4db6.
> 
> Reported-by: Jonathan Cameron <jic23 at cam.ac.uk>
> Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
> Tested-by: Robert Jarzmik <robert.jarzmik at free.fr>
> ---
>  arch/arm/mach-pxa/pxa25x.c |? ? 1 +
>  arch/arm/mach-pxa/pxa27x.c |? ? 1 +
>  2 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-pxa/pxa25x.c
> b/arch/arm/mach-pxa/pxa25x.c
> index 00d6eac..d8de3e5 100644
> --- a/arch/arm/mach-pxa/pxa25x.c
> +++ b/arch/arm/mach-pxa/pxa25x.c
> @@ -208,6 +208,7 @@ static struct clk_lookup
> pxa25x_clkregs[] = {
>  ??? INIT_CLKREG(&clk_pxa25x_gpio11,
> NULL, "GPIO11_CLK"),
>  ??? INIT_CLKREG(&clk_pxa25x_gpio12,
> NULL, "GPIO12_CLK"),
>  ??? INIT_CLKREG(&clk_pxa25x_mem,
> "pxa2xx-pcmcia", NULL),
> +??? INIT_CLKREG(&clk_dummy, "pxa-gpio",
> NULL),
>  };
>  
>  static struct clk_lookup pxa25x_hwuart_clkreg =
> diff --git a/arch/arm/mach-pxa/pxa27x.c
> b/arch/arm/mach-pxa/pxa27x.c
> index c1673b3..a3fabc9 100644
> --- a/arch/arm/mach-pxa/pxa27x.c
> +++ b/arch/arm/mach-pxa/pxa27x.c
> @@ -229,6 +229,7 @@ static struct clk_lookup
> pxa27x_clkregs[] = {
>  ??? INIT_CLKREG(&clk_pxa27x_im, NULL,
> "IMCLK"),
>  ??? INIT_CLKREG(&clk_pxa27x_memc, NULL,
> "MEMCLK"),
>  ??? INIT_CLKREG(&clk_pxa27x_mem,
> "pxa2xx-pcmcia", NULL),
> +??? INIT_CLKREG(&clk_dummy, "pxa-gpio",
> NULL),
>  };
>  
>  #ifdef CONFIG_PM
> -- 
> 1.7.5.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


From tony at atomide.com  Mon Mar  5 17:55:30 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 14:55:30 -0800
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to
 check presence of 32k timer
In-Reply-To: <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
Message-ID: <20120305225530.GJ12083@atomide.com>

Hi,

* Vaibhav Hiremath <hvaibhav at ti.com> [120119 06:01]:
> OMAP device has 32k-sync timer which is currently used as a
> clocksource in the kernel (omap2plus_defconfig).
> The current implementation uses compile time selection between
> gp-timer and 32k-sync timer, which breaks multi-omap build for
> the devices like AM33xx, where 32k-sync timer is not available.
> 
> So use hwmod database lookup mechanism, through which at run-time
> we can identify availability of 32k-sync timer on the device,
> else fall back to gp-timer.
...

> --- a/arch/arm/plat-omap/counter_32k.c
> +++ b/arch/arm/plat-omap/counter_32k.c
> @@ -69,52 +69,55 @@ void read_persistent_clock(struct timespec *ts)
>  
>  int __init omap_init_clocksource_32k(void)
>  {
> -	static char err[] __initdata = KERN_ERR
> -			"%s: can't register clocksource!\n";
> -
> -	if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
> -		u32 pbase;
> -		unsigned long size = SZ_4K;
> -		void __iomem *base;
> -		struct clk *sync_32k_ick;
> -
> -		if (cpu_is_omap16xx()) {
> -			pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> -			size = SZ_1K;
> -		} else if (cpu_is_omap2420())
> -			pbase = OMAP2420_32KSYNCT_BASE + 0x10;
> -		else if (cpu_is_omap2430())
> -			pbase = OMAP2430_32KSYNCT_BASE + 0x10;
> -		else if (cpu_is_omap34xx())
> -			pbase = OMAP3430_32KSYNCT_BASE + 0x10;
> -		else if (cpu_is_omap44xx())
> -			pbase = OMAP4430_32KSYNCT_BASE + 0x10;
> -		else
> +	u32 pbase;
> +	unsigned long size = SZ_4K;
> +	void __iomem *base;
> +	struct clk *sync_32k_ick;
> +
> +	if (cpu_is_omap16xx()) {
> +		pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> +		size = SZ_1K;
> +	} else if (cpu_class_is_omap2()) {
> +		struct omap_hwmod *oh;
> +		const char *oh_name = "counter_32k";
> +
> +		oh = omap_hwmod_lookup(oh_name);
> +		if (!oh || oh->slaves_cnt == 0) {
> +			pr_err("Could not lookup %s hwmod\n", oh_name);
>  			return -ENODEV;
> +		}
> +		pbase = oh->slaves[0]->addr->pa_start + 0x10;
> +	} else {
> +		return -ENODEV;
> +	}

How about have separate omap1 and omap2+ init functions that
call a common function and passes the pbase as a parameter?

That way we can get rid of the cpu_is_omapxxxx tests here.

Regards,

Tony 


From tony at atomide.com  Mon Mar  5 17:56:40 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 14:56:40 -0800
Subject: [PATCH 2/3] ARM: OMAP2/3: Add idle_st bits for ST_32KSYNC
 timer to prcm-common header
In-Reply-To: <1326983304-14619-3-git-send-email-hvaibhav@ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-3-git-send-email-hvaibhav@ti.com>
Message-ID: <20120305225640.GK12083@atomide.com>

* Vaibhav Hiremath <hvaibhav at ti.com> [120119 06:01]:
> Add missing idle_st bit for 32k-sync timer into the prcm-common
> header file, required for hwmod data.

These should be queued by Paul when the related hwmod changes
are done.

Regards,

Tony
 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> ---
>  arch/arm/mach-omap2/prcm-common.h |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
> index 5aa5435..29955d5 100644
> --- a/arch/arm/mach-omap2/prcm-common.h
> +++ b/arch/arm/mach-omap2/prcm-common.h
> @@ -177,6 +177,8 @@
>  /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
>  #define OMAP24XX_ST_GPIOS_SHIFT				2
>  #define OMAP24XX_ST_GPIOS_MASK				(1 << 2)
> +#define OMAP24XX_ST_32KSYNC_SHIFT			1
> +#define OMAP24XX_ST_32KSYNC_MASK			(1 << 1)
>  #define OMAP24XX_ST_GPT1_SHIFT				0
>  #define OMAP24XX_ST_GPT1_MASK				(1 << 0)
>  
> @@ -307,6 +309,8 @@
>  #define OMAP3430_ST_SR1_MASK				(1 << 6)
>  #define OMAP3430_ST_GPIO1_SHIFT				3
>  #define OMAP3430_ST_GPIO1_MASK				(1 << 3)
> +#define OMAP3430_ST_32KSYNC_SHIFT			2
> +#define OMAP3430_ST_32KSYNC_MASK			(1 << 2)
>  #define OMAP3430_ST_GPT12_SHIFT				1
>  #define OMAP3430_ST_GPT12_MASK				(1 << 1)
>  #define OMAP3430_ST_GPT1_SHIFT				0
> -- 
> 1.7.0.4
> 


From tony at atomide.com  Mon Mar  5 17:57:52 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 14:57:52 -0800
Subject: [PATCH 0/3] ARM: OMAP1/2+: 32k-timer: Add hwmod lookup for
 32k-timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A8317AF2D2@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <79CD15C6BA57404B839C016229A409A8317AF2D2@DBDE01.ent.ti.com>
Message-ID: <20120305225751.GL12083@atomide.com>

* Hiremath, Vaibhav <hvaibhav at ti.com> [120123 00:16]:
> On Thu, Jan 19, 2012 at 19:58:21, Hiremath, Vaibhav wrote:
> > This patch series cleans up the existing 32k-sync timer implementation
> > without any major code change and adds hwmod lookup for omap2+ devices,
> > if lookup fails then fall back to gp-timer.
...
 
> Tony,
> 
> If there are no review comments, can this be merged?

Made a minor comment on the first patch, it would be nice to get
that clean-up merged. The other two depend on some some hwmod
data shrinkage by Paul..

Regards,

Tony


From tony at atomide.com  Mon Mar  5 18:03:34 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 15:03:34 -0800
Subject: [PATCH] GPMC: add ECC control definitions
In-Reply-To: <4F1D4CB3.5080803@visionsystems.de>
References: <4F1D4CB3.5080803@visionsystems.de>
Message-ID: <20120305230334.GM12083@atomide.com>

* Yegor Yefremov <yegor_sub1 at visionsystems.de> [120123 03:33]:
> Signed-off-by: Yegor Yefremov <yegorslists at googlemail.com>
> ---
>  arch/arm/mach-omap2/gpmc.c |   30 +++++++++++++++++++++++++-----
>  1 file changed, 25 insertions(+), 5 deletions(-)
> 
> Index: b/arch/arm/mach-omap2/gpmc.c
> ===================================================================
> --- a/arch/arm/mach-omap2/gpmc.c
> +++ b/arch/arm/mach-omap2/gpmc.c
> @@ -50,6 +50,19 @@
>  #define GPMC_ECC_SIZE_CONFIG	0x1fc
>  #define GPMC_ECC1_RESULT        0x200
>  
> +/* GPMC ECC control settings */
> +#define GPMC_ECC_CTRL_ECCCLEAR		0x100
> +#define GPMC_ECC_CTRL_ECCDISABLE	0x000
> +#define GPMC_ECC_CTRL_ECCREG1		0x001
> +#define GPMC_ECC_CTRL_ECCREG2		0x002
> +#define GPMC_ECC_CTRL_ECCREG3		0x003
> +#define GPMC_ECC_CTRL_ECCREG4		0x004
> +#define GPMC_ECC_CTRL_ECCREG5		0x005
> +#define GPMC_ECC_CTRL_ECCREG6		0x006
> +#define GPMC_ECC_CTRL_ECCREG7		0x007
> +#define GPMC_ECC_CTRL_ECCREG8		0x008
> +#define GPMC_ECC_CTRL_ECCREG9		0x009
> +
>  #define GPMC_CS0_OFFSET		0x60
>  #define GPMC_CS_SIZE		0x30
>  
> @@ -855,8 +868,9 @@
>  	gpmc_ecc_used = cs;
>  
>  	/* clear ecc and enable bits */
> -	val = ((0x00000001<<8) | 0x00000001);
> -	gpmc_write_reg(GPMC_ECC_CONTROL, val);
> +	gpmc_write_reg(GPMC_ECC_CONTROL,
> +			GPMC_ECC_CTRL_ECCCLEAR |
> +			GPMC_ECC_CTRL_ECCREG1);
>  
>  	/* program ecc and result sizes */
>  	val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
> @@ -864,13 +878,19 @@
>  
>  	switch (mode) {
>  	case GPMC_ECC_READ:
> -		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
> +		gpmc_write_reg(GPMC_ECC_CONTROL,
> +				GPMC_ECC_CTRL_ECCCLEAR |
> +				GPMC_ECC_CTRL_ECCREG1);
>  		break;
>  	case GPMC_ECC_READSYN:
> -		 gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
> +		gpmc_write_reg(GPMC_ECC_CONTROL,
> +				GPMC_ECC_CTRL_ECCCLEAR |
> +				GPMC_ECC_CTRL_ECCDISABLE);
>  		break;
>  	case GPMC_ECC_WRITE:
> -		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
> +		gpmc_write_reg(GPMC_ECC_CONTROL,
> +				GPMC_ECC_CTRL_ECCCLEAR |
> +				GPMC_ECC_CTRL_ECCREG1);
>  		break;
>  	default:
>  		printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
> 

No functional changes here, right?

Can GPMC_ECC_READ and GPMC_ECC_WRITE case be combined:

	switch (mode) {
	case GPMC_ECC_READ:
	case GPMC_ECC_WRITE:
		gpmc_write_reg(GPMC_ECC_CONTROL,
			GPMC_ECC_CTRL_ECCCLEAR |
			GPMC_ECC_CTRL_ECCREG1);
	break;
	...

Regards,

Tony


From tony at atomide.com  Mon Mar  5 18:05:34 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 15:05:34 -0800
Subject: [PATCH 2/2] omap: build am3517crane board support by default
In-Reply-To: <1328818586-7104-3-git-send-email-mporter@ti.com>
References: <1328818586-7104-1-git-send-email-mporter@ti.com>
 <1328818586-7104-3-git-send-email-mporter@ti.com>
Message-ID: <20120305230534.GN12083@atomide.com>

* Matt Porter <mporter at ti.com> [120209 11:49]:
> Set default to include support for the craneboard when
> using the omap2plus_defconfig.
> 
> Signed-off-by: Matt Porter <mporter at ti.com>
> ---
>  arch/arm/mach-omap2/Kconfig |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index d965da4..678b8ac 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -206,6 +206,7 @@ config MACH_OMAP3517EVM
>  config MACH_CRANEBOARD
>  	bool "AM3517/05 CRANE board"
>  	depends on ARCH_OMAP3
> +	default y
>  	select OMAP_PACKAGE_CBB
>  
>  config MACH_OMAP3_PANDORA

As you may have read, we should remove the "default y"
from Kconfig. So can you please update your first patch in this
series to set CONFIG_MACH_CRANEBOARD=y in omap2plus_defconfig?

Thanks,

Regards,

Tony


From tony at atomide.com  Mon Mar  5 18:08:13 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 15:08:13 -0800
Subject: [PATCH v2 1/2] ARM: OMAP2+: id: Add am33xx SoC type detection
In-Reply-To: <1329113685-7500-1-git-send-email-afzal@ti.com>
References: <1329113685-7500-1-git-send-email-afzal@ti.com>
Message-ID: <20120305230812.GO12083@atomide.com>

* Afzal Mohammed <afzal at ti.com> [120212 22:00]:
> Determine SoC type, i.e. whether GP or HS
> 
> Note: cpu_is_34xx() is true for am33xx also. Doing
> cpu_is_am33xx() check after cpu_is_34xx() will not
> achieve what we want due to the above reason.
> Hence cpu_is_am33xx() is done before cpu_is_34xx()

Thanks, applying into fixes-non-critical-part2.

Tony


From khilman at ti.com  Mon Mar  5 18:10:04 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon,  5 Mar 2012 15:10:04 -0800
Subject: [PATCH] gpio/omap: fix wakeups on level-triggered GPIOs
Message-ID: <1330989004-9855-1-git-send-email-khilman@ti.com>

While both level- and edge-triggered GPIOs are capable of generating
interrupts, only edge-triggered GPIOs are capable of generating a
module-level wakeup to the PRCM (c.f. 34xx NDA TRM section 25.5.3.2.)

In order to ensure that devices using level-triggered GPIOs as
interrupts can also cause wakeups (e.g. from idle), this patch enables
edge-triggering for wakeup-enabled, level-triggered GPIOs when a GPIO
bank is runtime-suspended (which also happens during idle.)

This fixes a problem found in GPMC-connected network cards with GPIO
interrupts (e.g. smsc911x on Zoom3, Overo, ...) where network booting
with NFSroot was very slow since the GPIO IRQs used by the NIC were
not generating PRCM wakeups, and thus not waking the system from idle.
NOTE: until v3.3, this boot-time problem was somewhat masked because
the UART init prevented WFI during boot until the full serial driver
was available.  Preventing WFI allowed regular GPIO interrupts to fire
and this problem was not seen.  After the UART runtime PM cleanups, we
no longer avoid WFI during boot, so GPIO IRQs that were not causing
wakeups resulted in very slow IRQ response times.

Tested on platforms using level-triggered GPIOs for network IRQs using
the SMSC911x NIC: 3530/Overo and 3630/Zoom3.

Reported-by: Tony Lindgren <tony at atomide.com>
Tested-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Tested-by: Tony Lindgren <tony at atomide.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
Grant, here's another one for your gpio/next branch, and applies on
top of the for_3.4/gpio/runtime-pm-cleanup branch you've already
pulled from me.  While it's a fix, it's not a regressions since
this problem has been around for awhile, so it can be for 3.4.

 drivers/gpio/gpio-omap.c |   34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f49bd6f..752ae9b 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1196,8 +1196,30 @@ static int omap_gpio_runtime_suspend(struct device *dev)
 	struct gpio_bank *bank = platform_get_drvdata(pdev);
 	u32 l1 = 0, l2 = 0;
 	unsigned long flags;
+	u32 wake_low, wake_hi;
 
 	spin_lock_irqsave(&bank->lock, flags);
+
+	/*
+	 * Only edges can generate a wakeup event to the PRCM.
+	 *
+	 * Therefore, ensure any wake-up capable GPIOs have
+	 * edge-detection enabled before going idle to ensure a wakeup
+	 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
+	 * NDA TRM 25.5.3.1)
+	 *
+	 * The normal values will be restored upon ->runtime_resume()
+	 * by writing back the values saved in bank->context.
+	 */
+	wake_low = bank->context.leveldetect0 & bank->context.wake_en;
+	if (wake_low)
+		__raw_writel(wake_low | bank->context.fallingdetect,
+			     bank->base + bank->regs->fallingdetect);
+	wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
+	if (wake_hi)
+		__raw_writel(wake_hi | bank->context.risingdetect,
+			     bank->base + bank->regs->risingdetect);
+
 	if (bank->power_mode != OFF_MODE) {
 		bank->power_mode = 0;
 		goto update_gpio_context_count;
@@ -1246,6 +1268,18 @@ static int omap_gpio_runtime_resume(struct device *dev)
 
 	spin_lock_irqsave(&bank->lock, flags);
 	_gpio_dbck_enable(bank);
+
+	/*
+	 * In ->runtime_suspend(), level-triggered, wakeup-enabled
+	 * GPIOs were set to edge trigger also in order to be able to
+	 * generate a PRCM wakeup.  Here we restore the
+	 * pre-runtime_suspend() values for edge triggering.
+	 */
+	__raw_writel(bank->context.fallingdetect,
+		     bank->base + bank->regs->fallingdetect);
+	__raw_writel(bank->context.risingdetect,
+		     bank->base + bank->regs->risingdetect);
+
 	if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
 		spin_unlock_irqrestore(&bank->lock, flags);
 		return 0;
-- 
1.7.9.2



From paul.gortmaker at windriver.com  Mon Mar  5 18:12:02 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Mon,  5 Mar 2012 18:12:02 -0500
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
Message-ID: <1330989122-6323-1-git-send-email-paul.gortmaker@windriver.com>

Commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)

  "regulator: Remove support for supplies specified by struct device"

caused this file to break, since it was still relying on the
device field to be present.  Strip them out here too.

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
CC: Mark Brown <broonie at opensource.wolfsonmicro.com>

diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index d80c0ba..c8f3293 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1083,20 +1083,19 @@ static void __init em_x270_userspace_consumers_init(void)
 }
 
 /* DA9030 related initializations */
-#define REGULATOR_CONSUMER(_name, _dev, _supply)			       \
+#define REGULATOR_CONSUMER(_name, _supply)			       \
 	static struct regulator_consumer_supply _name##_consumers[] = {	\
 		{							\
-			.dev = _dev,					\
 			.supply = _supply,				\
 		},							\
 	}
 
-REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps");
-REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
-REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
-REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
-REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
-REGULATOR_CONSUMER(buck2, NULL, "vcc_core");
+REGULATOR_CONSUMER(ldo3, "vcc gps");
+REGULATOR_CONSUMER(ldo5, "vcc cam");
+REGULATOR_CONSUMER(ldo10, "vcc sdio");
+REGULATOR_CONSUMER(ldo12, "vcc usb");
+REGULATOR_CONSUMER(ldo19, "vcc gprs");
+REGULATOR_CONSUMER(buck2, "vcc_core");
 
 #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask)		\
 	static struct regulator_init_data _ldo##_data = {		\
-- 
1.7.9.1



From tony at atomide.com  Mon Mar  5 18:14:13 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 15:14:13 -0800
Subject: [PATCH v2 2/2] ARM: OMAP: sram: Add am33xx SRAM support (minimal)
In-Reply-To: <B5906170F1614E41A8A28DE3B8D121433179FC35@DBDE01.ent.ti.com>
References: <1329113715-7634-1-git-send-email-afzal@ti.com>
 <87fweeyfp6.fsf@macbook.be.48ers.dk>
 <B5906170F1614E41A8A28DE3B8D121433179FC35@DBDE01.ent.ti.com>
Message-ID: <20120305231413.GP12083@atomide.com>

* Bedia, Vaibhav <vaibhav.bedia at ti.com> [120213 07:36]:
> On Mon, Feb 13, 2012 at 19:54:05, Peter Korsgaard wrote:
> > >>>>> "Afzal" == Afzal Mohammed <afzal at ti.com> writes:
> > 
> >  Afzal> From: Vaibhav Bedia <vaibhav.bedia at ti.com>
> >  Afzal> Update SRAM start & size for am33xx SoC's.
> > 
> 
> This is a really awkward quoting style :|
> 
> > 
> > I don't particular know the omap sram stuff, but doesn't the 33xx have
> > 2x 64K blocks of SRAM?
> > 
> 
> Yes, but since the lower 64KB will not be available on non-GP device and
> only A8 can access it, for now we make use of the higher 64KB which is referred
> to as the OCMC RAM in the TRM. This will also enable SRAM usage by other drivers
> like PRU and McASP.
> 
> >  
> >  Afzal> +static inline int am33xx_sram_init(void)
> >  Afzal> +{
> >  Afzal> +	return 0;
> > 
> > 
> > I know you mentioned it in the commit message, but it might be good with
> > a comment here as well that this dummy function is needed to not get the 34xx
> > init function called for 33xx, so it doesn't get removed when somebody
> > decides to cleanup.
> 
> You are right in saying that the dummy function is needed to avoid 34xx SRAM init.
> We'll have some PM related code coming in soon and hopefully the SRAM code won't change
> Without us noticing ;)

OK, applying into fixes-non-critical-part2. Our sram.c should get turned
into a device driver, there's been already similar sram driver posted
to LAKML. So that should allow us to remove the cpu_is_xxxx checks.

Regards,

Tony


From shawn.guo at linaro.org  Mon Mar  5 18:45:33 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 6 Mar 2012 07:45:33 +0800
Subject: [PATCH v2 01/17] ASoC: imx: move eukrea audmux call into ASoC
 machine driver
In-Reply-To: <20120305192759.GB3852@pengutronix.de>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-2-git-send-email-shawn.guo@linaro.org>
 <20120305174612.GY3224@opensource.wolfsonmicro.com>
 <20120305192759.GB3852@pengutronix.de>
Message-ID: <20120305234531.GJ16232@S2101-09.ap.freescale.net>

On Mon, Mar 05, 2012 at 08:27:59PM +0100, Sascha Hauer wrote:
...
> For patches 01-08 I can give my:
> 
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> 
> The rest I would like to test. Shawn, on what is this series based? It
> neither applies on v3.3-rc6 nor on arm-soc/for-next.
> 
As I intend to have the series go through Mark's tree, I based it on
sound/for-next.

-- 
Regards,
Shawn


From hartleys at visionengravers.com  Mon Mar  5 18:28:50 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Mon, 5 Mar 2012 17:28:50 -0600
Subject: [PATCH 3/9] dmaengine: add private header file
In-Reply-To: <E1S4eK0-0000sv-87@rmk-PC.arm.linux.org.uk>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
 <E1S4eK0-0000sv-87@rmk-PC.arm.linux.org.uk>
Message-ID: <ADE657CA350FB648AAC2C43247A983F001F41FF555A9@AUSP01VMBX24.collaborationhost.net>

On Monday, March 05, 2012 1:16 PM, Russell King wrote:
>
> Add a local private header file to contain definitions and declarations
> which should only be used by DMA engine drivers.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---
>  drivers/dma/amba-pl08x.c    |    2 ++
>  drivers/dma/at_hdmac.c      |    1 +
>  drivers/dma/coh901318.c     |    1 +
>  drivers/dma/dmaengine.h     |   10 ++++++++++
>  drivers/dma/dw_dmac.c       |    1 +
>  drivers/dma/ep93xx_dma.c    |    2 ++
>  drivers/dma/fsldma.c        |    1 +
>  drivers/dma/imx-dma.c       |    2 ++
>  drivers/dma/imx-sdma.c      |    2 ++
>  drivers/dma/intel_mid_dma.c |    2 ++
>  drivers/dma/ioat/dma.c      |    2 ++
>  drivers/dma/ioat/dma_v2.c   |    2 ++
>  drivers/dma/iop-adma.c      |    2 ++
>  drivers/dma/ipu/ipu_idmac.c |    1 +
>  drivers/dma/mpc512x_dma.c   |    2 ++
>  drivers/dma/mv_xor.c        |    2 ++
>  drivers/dma/mxs-dma.c       |    2 ++
>  drivers/dma/pch_dma.c       |    2 ++
>  drivers/dma/pl330.c         |    2 ++
>  drivers/dma/ppc4xx/adma.c   |    1 +
>  drivers/dma/shdma.c         |    2 ++
>  drivers/dma/ste_dma40.c     |    1 +
>  drivers/dma/timb_dma.c      |    2 ++
>  drivers/dma/txx9dmac.c      |    2 ++
>  24 files changed, 49 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/dma/dmaengine.h
>
> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> index 2b5121f..87475cb 100644
> --- a/drivers/dma/amba-pl08x.c
> +++ b/drivers/dma/amba-pl08x.c
> @@ -85,6 +85,8 @@
>  #include <linux/slab.h>
>  #include <asm/hardware/pl080.h>
>  
> +#include "dmaengine.h"
> +
>  #define DRIVER_NAME	"pl08xdmac"
>  
>  static struct amba_driver pl08x_amba_driver;
> diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
> index 6baf5d7..ce26ba3 100644
> --- a/drivers/dma/at_hdmac.c
> +++ b/drivers/dma/at_hdmac.c
> @@ -27,6 +27,7 @@
>  #include <linux/of_device.h>
>  
>  #include "at_hdmac_regs.h"
> +#include "dmaengine.h"
>  
>  /*
>   * Glossary
> diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
> index 521434b..fb0d124 100644
> --- a/drivers/dma/coh901318.c
> +++ b/drivers/dma/coh901318.c
> @@ -24,6 +24,7 @@
>  #include <mach/coh901318.h>
>  
>  #include "coh901318_lli.h"
> +#include "dmaengine.h"
>  
>  #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
>  
> diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
> new file mode 100644
> index 0000000..968570d
> --- /dev/null
> +++ b/drivers/dma/dmaengine.h
> @@ -0,0 +1,10 @@
> +/*
> + * The contents of this file are private to DMA engine drivers, and is not
> + * part of the API to be used by DMA engine users.
> + */
> +#ifndef DMAENGINE_H
> +#define DMAENGINE_H
> +
> +#include <linux/dmaengine.h>
> +
> +#endif

Russell,

You have an include issue here.

All the dmaengine drivers have:

#include <linux/dmaengine.h>

Which is guarded with

#ifndef DMAENGINE_H
#define DMAENGINE_H

...

#endif

This is the same guard you are using in the private "dmaengine.h". And it
also includes <linux/dmaengine.h> again...

This doesn't compile as-is because the "dmaengine.h" file is not used due
to the #ifndef...

Regards,
Hartley



From shawn.guo at linaro.org  Mon Mar  5 18:46:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 6 Mar 2012 07:46:27 +0800
Subject: [PATCH v2 10/17] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <20120305173910.GZ3852@pengutronix.de>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-11-git-send-email-shawn.guo@linaro.org>
 <20120305173910.GZ3852@pengutronix.de>
Message-ID: <20120305234626.GK16232@S2101-09.ap.freescale.net>

On Mon, Mar 05, 2012 at 06:39:10PM +0100, Sascha Hauer wrote:
> On Mon, Mar 05, 2012 at 10:30:58PM +0800, Shawn Guo wrote:
> > Freescale PowerPC and ARM/IMX families share the same SSI IP block.
> > The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
> > code sharing and consolidation can happen.
> > 
> > This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
> > in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
> > IMX platform.
> > 
> > Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> > ---
> >  sound/soc/Kconfig                        |    1 -
> >  sound/soc/Makefile                       |    1 -
> >  sound/soc/fsl/Kconfig                    |   92 ++++++++++++++++++++++++++++++
> >  sound/soc/fsl/Makefile                   |   22 +++++++
> >  sound/soc/{imx => fsl}/eukrea-tlv320.c   |    2 +-
> >  sound/soc/{imx => fsl}/imx-audmux.c      |    0
> >  sound/soc/{imx => fsl}/imx-audmux.h      |    0
> >  sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c |    0
> 
> Maybe this is the right time to rename this file to something like
> imx-pcm-dma.c since it has nothing to do with mx2 anymore.
> 
Ok, will do.

-- 
Regards,
Shawn


From hartleys at visionengravers.com  Mon Mar  5 18:35:53 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Mon, 5 Mar 2012 17:35:53 -0600
Subject: [PATCH 6/9] dmaengine: consolidate tx_status functions
In-Reply-To: <E1S4eKz-0000tE-FB@rmk-PC.arm.linux.org.uk>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
 <E1S4eKz-0000tE-FB@rmk-PC.arm.linux.org.uk>
Message-ID: <ADE657CA350FB648AAC2C43247A983F001F41FF555AF@AUSP01VMBX24.collaborationhost.net>

On Monday, March 05, 2012 1:17 PM, Russell King wrote:
>
> Now that we have the completed cookie in the dma_chan structure, we
> can consolidate the tx_status functions by providing a function to set
> the txstate structure and returning the DMA status.  We also provide
> a separate helper to set the residue for cookies which are still in
> progress.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>

<snip>

> diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
> index 47e0997..244a2c5 100644
> --- a/drivers/dma/dmaengine.h
> +++ b/drivers/dma/dmaengine.h
> @@ -45,4 +45,35 @@ static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
>  	tx->cookie = 0;
>  }
>  
> +/**
> + * dma_cookie_status - report cookie status
> + * @chan: dma channel
> + * @cookie: cookie we are interested in
> + * @state: dma_tx_state structure to return last/used cookies
> + *
> + * Report the status of the cookie, filling in the state structure if
> + * non-NULL.  No locking is required.
> + */
> +static inline enum dma_status dma_cookie_status(struct dma_chan *chan,
> +	dma_cookie_t cookie, struct dma_tx_state *state)
> +{
> +	dma_cookie_t used, complete;
> +
> +	used = chan->cookie;
> +	complete = chan->complete;

Is this supposed to be:

	complete = chan->completed_cookie;

Regards,
Hartley



From paul.gortmaker at windriver.com  Mon Mar  5 18:38:58 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Mon, 5 Mar 2012 18:38:58 -0500
Subject: [PATCH] arm: fix unresolved restart build failure in
 plat-iop/restart.c
In-Reply-To: <1327288578-30852-1-git-send-email-paul.gortmaker@windriver.com>
References: <1327288578-30852-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <CAP=VYLrEvqdL+S3a_XVQoHbAGJXS_sfQzxLs52YcresmGKOOXA@mail.gmail.com>

On Sun, Jan 22, 2012 at 10:16 PM, Paul Gortmaker
<paul.gortmaker at windriver.com> wrote:
> Upstream commit bec92b1ec67b4998b6a3bad7c2f03c846cbac71e
>
> ?"ARM: restart: iop3xx: use new restart hook"
>
> created this file, but it needs asm/system.h since upstream
> commit e879c862fb81b986095ae7a4676b2281c2f97957
>
> ?"ARM: restart: only perform setup for restart when soft-restarting"
>
> added the soft_restart() entry. ?Add in that header to resolve
> the below build failure:

Just checking that this didn't fall through the cracks, as I don't
see it in linux-next yet.  I just re-tested on today's linux-next and
it still fixes these defconfig build failures:

http://kisskb.ellerman.id.au/kisskb/target/1257/

Thanks,
Paul.
--

>
> ?CC ? ? ?arch/arm/plat-iop/restart.o
> ?arch/arm/plat-iop/restart.c: In function 'iop3xx_restart':
> ?arch/arm/plat-iop/restart.c:18: error: implicit declaration of function 'soft_restart'
> ?make[3]: *** [arch/arm/plat-iop/restart.o] Error 1
>
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
>
> diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
> index 6a85a0c..728b5c7 100644
> --- a/arch/arm/plat-iop/restart.c
> +++ b/arch/arm/plat-iop/restart.c
> @@ -7,6 +7,7 @@
> ?* it under the terms of the GNU General Public License version 2 as
> ?* published by the Free Software Foundation.
> ?*/
> +#include <asm/system.h>
> ?#include <asm/hardware/iop3xx.h>
> ?#include <mach/hardware.h>
>
> --
> 1.7.7.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From tony at atomide.com  Mon Mar  5 18:42:41 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 5 Mar 2012 15:42:41 -0800
Subject: [PATCH] mmc: omap_hsmmc: Fix Unbalanced pm_runtime_enable warning
Message-ID: <20120305234240.GQ12083@atomide.com>

mmc: omap_hsmmc: Fix Unbalanced pm_runtime_enable warning

Otherwise we can get following warning when re-loading the
omap_hsmmc driver module when gpio_twl4030 module is not
loaded:

omap_hsmmc omap_hsmmc.0: Unbalanced pm_runtime_enable!
omap_hsmmc omap_hsmmc.0: Unable to grab MMC CD IRQ
omap_hsmmc: probe of omap_hsmmc.0 failed with error -22

Signed-off-by: Tony Lindgren <tony at atomide.com>

---

Kevin, maybe take a look and see if this is correct and
fits into your PM branches?

Tony

--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -2146,6 +2146,7 @@ err_irq_cd_init:
 err_irq:
 	pm_runtime_mark_last_busy(host->dev);
 	pm_runtime_put_autosuspend(host->dev);
+	pm_runtime_disable(host->dev);
 	clk_put(host->fclk);
 	if (host->got_dbclk) {
 		clk_disable(host->dbclk);


From broonie at opensource.wolfsonmicro.com  Mon Mar  5 18:45:43 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon,  5 Mar 2012 23:45:43 +0000
Subject: [PATCH] ARM: S3C64XX: Add some more Cragganmore module IDs to the
 table
Message-ID: <1330991143-12349-1-git-send-email-broonie@opensource.wolfsonmicro.com>

Just IDs for diagnostics, nothing is actually supported. Not all of
these have board numbers assigned yet, these will be updated as the
numbers are assigned.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---

It'd be really nice to get this into 3.4 if possible, I know it's a bit
late but it's a very simple and non-invasive patch.

 arch/arm/mach-s3c64xx/mach-crag6410-module.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 317f866..e248581 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -192,10 +192,14 @@ static __devinitdata const struct {
 	{ .id = 0x02, .name = "1251-EV1 Jura" },
 	{ .id = 0x03, .name = "1252-EV1 Glenlivet" },
 	{ .id = 0x11, .name = "6249-EV2 Glenfarclas", },
+	{ .id = 0x14, .name = "6271-EV1 Lochnagar" },
+	{ .id = 0x15, .name = "XXXX-EV1 Bells" },
 	{ .id = 0x21, .name = "1275-EV1 Mortlach" },
 	{ .id = 0x25, .name = "1274-EV1 Glencadam" },
 	{ .id = 0x31, .name = "1253-EV1 Tomatin",
 	  .spi_devs = wm1253_devs, .num_spi_devs = ARRAY_SIZE(wm1253_devs) },
+	{ .id = 0x32, .name = "XXXX-EV1 Caol Illa" },
+	{ .id = 0x33, .name = "XXXX-EV1 Oban" },
 	{ .id = 0x39, .name = "1254-EV1 Dallas Dhu",
 	  .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
 	{ .id = 0x3a, .name = "1259-EV1 Tobermory",
-- 
1.7.9.1



From hartleys at visionengravers.com  Mon Mar  5 18:44:09 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Mon, 5 Mar 2012 17:44:09 -0600
Subject: [PATCH 0/9] DMA engine cookie handling cleanups
In-Reply-To: <CACRpkda9R3c0dt95w0N7Fe5es16CqbWtsCKMaFq-nwSYV4bk-w@mail.gmail.com>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
 <CACRpkda9R3c0dt95w0N7Fe5es16CqbWtsCKMaFq-nwSYV4bk-w@mail.gmail.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F001F41FF555B5@AUSP01VMBX24.collaborationhost.net>

On Monday, March 05, 2012 1:51 PM, Linus Walleij wrote:
> On Mon, Mar 5, 2012 at 9:14 PM, Russell King - ARM Linux wrote:
>
>> This patch series cleans up the handling of cookies in DMA engine drivers.
>> This is done by providing a set of inline library functions for common
>> tasks:
>
> Overall this looks good, but I have a problem:
> patch [1/9] does not appear in any subscribed accounts (it may be on
> my @stericsson.com address, will check tomorrow)

Patch 8/9 also doesn't appear to be on the mailing list.

> One I get hold of an ungmangled copy I can test the series on
> ux500 and U300.
>
> Is it just stuck in moderation because of size or something like that?

I'm also trying to test the series on ep93xx but have some compile issues
with patches [3/9] and [6/9].

Regards,
Hartley


From linux at arm.linux.org.uk  Mon Mar  5 18:54:14 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 5 Mar 2012 23:54:14 +0000
Subject: [PATCH 0/9] DMA engine cookie handling cleanups
In-Reply-To: <20120305201411.GA17791@n2100.arm.linux.org.uk>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
Message-ID: <20120305235414.GB17370@n2100.arm.linux.org.uk>

On Mon, Mar 05, 2012 at 08:14:11PM +0000, Russell King - ARM Linux wrote:
> This patch series cleans up the handling of cookies in DMA engine drivers.
> This is done by providing a set of inline library functions for common
> tasks:
> 
> - moving the 'last completed cookie' into struct dma_chan - everyone
>   has this in their driver private channel data structure
> 
> - consolidate allocation of cookies to DMA descriptors
> 
> - common way to update 'last completed cookie' value
> 
> - standard way to implement tx_status callback and update the residue
> 
> - consolidate initialization of cookies
> 
> - update implementations differing from the majority of DMA engine drivers
>   to behave the same as the majority implementation in respect of cookies
> 
> What this means is that we get to the point where all DMA engine drivers
> will hand out cookie value '2' as the first, and incrementing cookie
> values up to INT_MAX, returning to cookie '1' as the next cookie.
> 
> Think of this patch series as round 1...  I am hoping over time that more
> code can be consolidated between the DMA engine drivers and end up with a
> consistent way to handle various common themes in DMA engine hardware
> (like physical channel<->peripheral request signal selection.)
> 
> I've only build-tested this stuff on a few ARM configs, and my ability
> to run-test this stuff is even more limited by all the broken useless DMA
> engine hardware I have access to (mostly pl08x based) so having some
> tested-bys would be a great advantage.

Seems I'd misremembered what I'd done with this series.  I'll leave it
as-is for the time being if people want to provide review comments instead,
and I'll post v2 in the next couple of days.  (Quite a bit of this series
dates from August 2011...)


From swarren at nvidia.com  Mon Mar  5 19:03:53 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon, 5 Mar 2012 17:03:53 -0700
Subject: [PATCH V2] ARM: tegra: update defconfig
Message-ID: <1330992233-8493-1-git-send-email-swarren@nvidia.com>

Refresh tegra_defconfig:

New options enabled:
* PERF_EVENTS
* Tegra EMC scaling
* Support for all 4 CPUs on Tegra30
* AUTO_ZRELADDR for unified Tegra20+Tegra30 images
* CPU_FREQ/CPU_IDLE
* BLK_DEV_SR
* INPUT_EVDEV
* Regulators, including fixed, GPIO, TPS6586x
* Audio for Tegra+ALC5632 (for Paz00/Toshiba AC100)
* NVEC (staging, for Paz00/Toshiba AC100)
* IOMMU for Tegra20's GART and Tegra30's SMMU
* TEGRA_AES
* ext4, for trim support on SD/eMMC

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
v2: Added ext4 support per request from Olof

 arch/arm/configs/tegra_defconfig |   33 ++++++++++++++++++++++-----------
 1 files changed, 22 insertions(+), 11 deletions(-)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index fd5d304..351d670 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -11,11 +11,14 @@ CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_ELF_CORE is not set
 CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
@@ -27,18 +30,20 @@ CONFIG_MACH_PAZ00=y
 CONFIG_MACH_TRIMSLICE=y
 CONFIG_MACH_WARIO=y
 CONFIG_MACH_VENTANA=y
-CONFIG_TEGRA_DEBUG_UARTD=y
-CONFIG_ARM_ERRATA_742230=y
+CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
-CONFIG_NR_CPUS=2
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -68,7 +73,6 @@ CONFIG_IPV6_MULTIPLE_TABLES=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
 CONFIG_AD525X_DPOT=y
 CONFIG_AD525X_DPOT_I2C=y
 CONFIG_ICS932S401=y
@@ -76,6 +80,7 @@ CONFIG_APDS9802ALS=y
 CONFIG_ISL29003=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
@@ -85,8 +90,7 @@ CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
 # CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
+CONFIG_INPUT_EVDEV=y
 # CONFIG_VT is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
@@ -96,13 +100,15 @@ CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
-# CONFIG_I2C_HELPER_AUTO is not set
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
 CONFIG_SPI_TEGRA=y
 CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_TPS6586X=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -116,11 +122,13 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_TEGRA=y
 CONFIG_SND_SOC_TEGRA_WM8903=y
 CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
+CONFIG_SND_SOC_TEGRA_ALC5632=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_TEGRA=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_TEGRA=y
@@ -130,6 +138,11 @@ CONFIG_STAGING=y
 CONFIG_IIO=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_AK8975=y
+CONFIG_MFD_NVEC=y
+CONFIG_KEYBOARD_NVEC=y
+CONFIG_SERIO_NVEC_PS2=y
+CONFIG_TEGRA_IOMMU_GART=y
+CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -138,13 +151,12 @@ CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
@@ -162,9 +174,8 @@ CONFIG_DEBUG_SG=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_AES=y
 CONFIG_CRYPTO_ARC4=y
 CONFIG_CRYPTO_TWOFISH=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_TEGRA_AES=y
 CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-- 
1.7.0.4



From broonie at opensource.wolfsonmicro.com  Mon Mar  5 19:06:45 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 00:06:45 +0000
Subject: [PATCH v2 01/17] ASoC: imx: move eukrea audmux call into ASoC
 machine driver
In-Reply-To: <20120305192759.GB3852@pengutronix.de>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-2-git-send-email-shawn.guo@linaro.org>
 <20120305174612.GY3224@opensource.wolfsonmicro.com>
 <20120305192759.GB3852@pengutronix.de>
Message-ID: <20120306000644.GA3201@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 08:27:59PM +0100, Sascha Hauer wrote:

> For patches 01-08 I can give my:

> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Great, applied all those - thanks!
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From khilman at ti.com  Mon Mar  5 19:09:28 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 05 Mar 2012 16:09:28 -0800
Subject: [PATCH] mmc: omap_hsmmc: Fix Unbalanced pm_runtime_enable warning
In-Reply-To: <20120305234240.GQ12083@atomide.com> (Tony Lindgren's message of
 "Mon, 5 Mar 2012 15:42:41 -0800")
References: <20120305234240.GQ12083@atomide.com>
Message-ID: <87obsaio93.fsf@ti.com>

Tony Lindgren <tony at atomide.com> writes:

> mmc: omap_hsmmc: Fix Unbalanced pm_runtime_enable warning
>
> Otherwise we can get following warning when re-loading the
> omap_hsmmc driver module when gpio_twl4030 module is not
> loaded:
>
> omap_hsmmc omap_hsmmc.0: Unbalanced pm_runtime_enable!
> omap_hsmmc omap_hsmmc.0: Unable to grab MMC CD IRQ
> omap_hsmmc: probe of omap_hsmmc.0 failed with error -22
>
> Signed-off-by: Tony Lindgren <tony at atomide.com>
> ---
>
> Kevin, maybe take a look and see if this is correct and
> fits into your PM branches?

Looks right to me:

Acked-by: Kevin Hilman <khilman at ti.com>

But this is a fix to the driver itself, so Chris should queue this in
mmc-next.

Chris, can you take this one?

Kevin


>
> Tony
>
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -2146,6 +2146,7 @@ err_irq_cd_init:
>  err_irq:
>  	pm_runtime_mark_last_busy(host->dev);
>  	pm_runtime_put_autosuspend(host->dev);
> +	pm_runtime_disable(host->dev);
>  	clk_put(host->fclk);
>  	if (host->got_dbclk) {
>  		clk_disable(host->dbclk);
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From hartleys at visionengravers.com  Mon Mar  5 19:12:50 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Mon, 5 Mar 2012 18:12:50 -0600
Subject: [PATCH 6/9] dmaengine: consolidate tx_status functions
In-Reply-To: <E1S4eKz-0000tE-FB@rmk-PC.arm.linux.org.uk>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
 <E1S4eKz-0000tE-FB@rmk-PC.arm.linux.org.uk>
Message-ID: <ADE657CA350FB648AAC2C43247A983F001F41FF555BD@AUSP01VMBX24.collaborationhost.net>

On Monday, March 05, 2012 1:17 PM, Russell King wrote:
> 
> Now that we have the completed cookie in the dma_chan structure, we
> can consolidate the tx_status functions by providing a function to set
> the txstate structure and returning the DMA status.  We also provide
> a separate helper to set the residue for cookies which are still in
> progress.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---

<snip>

> diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
> index 47e0997..244a2c5 100644
> --- a/drivers/dma/dmaengine.h
> +++ b/drivers/dma/dmaengine.h
> @@ -45,4 +45,35 @@ static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
>  	tx->cookie = 0;
>  }
>  
> +/**
> + * dma_cookie_status - report cookie status
> + * @chan: dma channel
> + * @cookie: cookie we are interested in
> + * @state: dma_tx_state structure to return last/used cookies
> + *
> + * Report the status of the cookie, filling in the state structure if
> + * non-NULL.  No locking is required.
> + */
> +static inline enum dma_status dma_cookie_status(struct dma_chan *chan,
> +	dma_cookie_t cookie, struct dma_tx_state *state)
> +{
> +	dma_cookie_t used, complete;
> +
> +	used = chan->cookie;
> +	complete = chan->complete;
> +	barrier();
> +	if (state) {
> +		state->last = complete;
> +		state->used = used;
> +		state->residue = 0;
> +	}

Isn't this dma_set_tx_state()?

> +	return dma_async_is_complete(cookie, complete, used);
> +}

Regards,
Hartley



From swarren at nvidia.com  Mon Mar  5 19:22:14 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon, 5 Mar 2012 17:22:14 -0700
Subject: [PATCH V2 1/3] Documentation/gpio.txt: Explain expected pinctrl
 interaction
Message-ID: <1330993336-9538-1-git-send-email-swarren@nvidia.com>

Update gpio.txt based on recent discussions regarding interaction with the
pinctrl subsystem.

Previously, gpio_request() was described as explicitly not performing any
required mux setup operations etc.

Now, gpio_request() is explicitly as explicitly performing any required mux
setup operations where possible. In the case it isn't, platform code is
required to have set up any required muxing or other configuration prior to
gpio_request() being called, in order to maintain the same semantics.

This is achieved by gpiolib drivers calling e.g. pinctrl_request_gpio() in
their .request() operation.

Cc: Randy Dunlap <rdunlap at xenotime.net>
Cc: linux-doc at vger.kernel.org
Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
v2: Modified to state that pin multiplexing should be performed within
direction_input()/output() rather than request(), to address Russell King's
need for glitchless transition between special function and GPIO usage of
a pin. Various rewording and cleanup due to this.
---
 Documentation/gpio.txt |   23 ++++++++++++++++++++---
 1 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/Documentation/gpio.txt b/Documentation/gpio.txt
index 792faa3..e0f8799 100644
--- a/Documentation/gpio.txt
+++ b/Documentation/gpio.txt
@@ -271,9 +271,26 @@ Some platforms may also use knowledge about what GPIOs are active for
 power management, such as by powering down unused chip sectors and, more
 easily, gating off unused clocks.
 
-Note that requesting a GPIO does NOT cause it to be configured in any
-way; it just marks that GPIO as in use.  Separate code must handle any
-pin setup (e.g. controlling which pin the GPIO uses, pullup/pulldown).
+For GPIOs that use pins known to the pinctrl subsystem, that subsystem should
+be informed of their use; a gpiolib driver's .request() operation may call
+pinctrl_request_gpio(), and a gpiolib driver's .free() operation may call
+pinctrl_free_gpio(). The pinctrl subsystem allows a pinctrl_request_gpio()
+to succeed concurrently with a pin or pingroup being "owned" by a device for
+pin multiplexing.
+
+Any programming of pin multiplexing hardware that is needed to route the
+GPIO signal to the appropriate pin should occur within a GPIO driver's
+.direction_input() or .direction_output() operations, and occur after any
+setup of an output GPIO's value. This allows a glitch-free migration from a
+pin's special function to GPIO. This is sometimes required when using a GPIO
+to implement a workaround on signals typically driven by a non-GPIO HW block.
+
+Some platforms allow some or all GPIO signals to be routed to different pins.
+Similarly, other aspects of the GPIO or pin may need to be configured, such as
+pullup/pulldown. Platform software should arrange that any such details are
+configured prior to gpio_request() being called for those GPIOs, e.g. using
+the pinctrl subsystem's mapping table, so that GPIO users need not be aware
+of these details.
 
 Also note that it's your responsibility to have stopped using a GPIO
 before you free it.
-- 
1.7.0.4



From swarren at nvidia.com  Mon Mar  5 19:22:15 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon, 5 Mar 2012 17:22:15 -0700
Subject: [PATCH V2 2/3] pinctrl: allow concurrent gpio and mux function
 ownership of pins
In-Reply-To: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
References: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
Message-ID: <1330993336-9538-2-git-send-email-swarren@nvidia.com>

Per recent updates to Documentation/gpio.txt, gpiolib drivers should
inform pinctrl when a GPIO is requested. pinctrl then marks that pin as
in-use for that GPIO function.

When an SoC muxes pins in a group, it's quite possible for the group to
contain e.g. 6 pins, but only 4 of them actually be needed by the HW
module that's mux'd to them. In this case, the other 2 pins could be
used as GPIOs. However, pinctrl marks all the pins within the group as
in-use by the selected mux function. To allow the expected gpiolib
interaction, separate the concepts of pin ownership into two parts: One
for the mux function and one for GPIO usage. Finally, allow those two
ownerships to exist in parallel.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
v2: New patch.
---
 drivers/pinctrl/core.h   |   13 ++++----
 drivers/pinctrl/pinmux.c |   72 +++++++++++++++++++++++++++++++--------------
 2 files changed, 56 insertions(+), 29 deletions(-)

diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 5b3ff13..2d365a3 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -118,15 +118,15 @@ struct pinctrl_setting {
  * @name: a name for the pin, e.g. the name of the pin/pad/finger on a
  *	datasheet or such
  * @dynamic_name: if the name of this pin was dynamically allocated
- * @usecount: If zero, the pin is not claimed, and @owner should be NULL.
+ * @mux_usecount: If zero, the pin is not claimed, and @owner should be NULL.
  *	If non-zero, this pin is claimed by @owner. This field is an integer
  *	rather than a boolean, since pinctrl_get() might process multiple
  *	mapping table entries that refer to, and hence claim, the same group
  *	or pin, and each of these will increment the @usecount.
- * @owner: The name of the entity owning the pin. Typically, this is the name
- *	of the device that called pinctrl_get(). Alternatively, it may be the
- *	name of the GPIO passed to pinctrl_request_gpio().
+ * @mux_owner: The name of device that called pinctrl_get().
  * @mux_setting: The most recent selected mux setting for this pin, if any.
+ * @gpio_owner: If pinctrl_request_gpio() was called for this pin, this is
+ *	the name of the GPIO that "owns" this pin.
  */
 struct pin_desc {
 	struct pinctrl_dev *pctldev;
@@ -134,9 +134,10 @@ struct pin_desc {
 	bool dynamic_name;
 	/* These fields only added when supporting pinmux drivers */
 #ifdef CONFIG_PINMUX
-	unsigned usecount;
-	const char *owner;
+	unsigned mux_usecount;
+	const char *mux_owner;
 	const struct pinctrl_setting_mux *mux_setting;
+	const char *gpio_owner;
 #endif
 };
 
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 86e4017..4e62783 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -94,17 +94,28 @@ static int pin_request(struct pinctrl_dev *pctldev,
 		goto out;
 	}
 
-	if (desc->usecount && strcmp(desc->owner, owner)) {
-		dev_err(pctldev->dev,
-			"pin already requested\n");
-		goto out;
-	}
+	if (gpio_range) {
+		/* There's no need to support multiple GPIO requests */
+		if (desc->gpio_owner) {
+			dev_err(pctldev->dev,
+				"pin already requested\n");
+			goto out;
+		}
 
-	desc->usecount++;
-	if (desc->usecount > 1)
-		return 0;
+		desc->gpio_owner = owner;
+	} else {
+		if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) {
+			dev_err(pctldev->dev,
+				"pin already requested\n");
+			goto out;
+		}
 
-	desc->owner = owner;
+		desc->mux_usecount++;
+		if (desc->mux_usecount > 1)
+			return 0;
+
+		desc->mux_owner = owner;
+	}
 
 	/* Let each pin increase references to this module */
 	if (!try_module_get(pctldev->owner)) {
@@ -135,9 +146,13 @@ static int pin_request(struct pinctrl_dev *pctldev,
 
 out_free_pin:
 	if (status) {
-		desc->usecount--;
-		if (!desc->usecount)
-			desc->owner = NULL;
+		if (gpio_range) {
+			desc->gpio_owner = NULL;
+		} else {
+			desc->mux_usecount--;
+			if (!desc->mux_usecount)
+				desc->mux_owner = NULL;
+		}
 	}
 out:
 	if (status)
@@ -172,9 +187,11 @@ static const char *pin_free(struct pinctrl_dev *pctldev, int pin,
 		return NULL;
 	}
 
-	desc->usecount--;
-	if (desc->usecount)
-		return NULL;
+	if (!gpio_range) {
+		desc->mux_usecount--;
+		if (desc->mux_usecount)
+			return NULL;
+	}
 
 	/*
 	 * If there is no kind of request function for the pin we just assume
@@ -185,9 +202,15 @@ static const char *pin_free(struct pinctrl_dev *pctldev, int pin,
 	else if (ops->free)
 		ops->free(pctldev, pin);
 
-	owner = desc->owner;
-	desc->owner = NULL;
-	desc->mux_setting = NULL;
+	if (gpio_range) {
+		owner = desc->gpio_owner;
+		desc->gpio_owner = NULL;
+	} else {
+		owner = desc->mux_owner;
+		desc->mux_owner = NULL;
+		desc->mux_setting = NULL;
+	}
+
 	module_put(pctldev->owner);
 
 	return owner;
@@ -493,7 +516,7 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
 	unsigned i, pin;
 
 	seq_puts(s, "Pinmux settings per pin\n");
-	seq_puts(s, "Format: pin (name): owner\n");
+	seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n");
 
 	mutex_lock(&pinctrl_mutex);
 
@@ -508,13 +531,16 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
 		if (desc == NULL)
 			continue;
 
-		if (desc->owner &&
-		    !strcmp(desc->owner, pinctrl_dev_get_name(pctldev)))
+		if (desc->mux_owner &&
+		    !strcmp(desc->mux_owner, pinctrl_dev_get_name(pctldev)))
 			is_hog = true;
 
-		seq_printf(s, "pin %d (%s): %s%s", pin,
+		seq_printf(s, "pin %d (%s): %s %s%s", pin,
 			   desc->name ? desc->name : "unnamed",
-			   desc->owner ? desc->owner : "UNCLAIMED",
+			   desc->mux_owner ? desc->mux_owner
+				: "(MUX UNCLAIMED)",
+			   desc->gpio_owner ? desc->gpio_owner
+				: "(GPIO UNCLAIMED)",
 			   is_hog ? " (HOG)" : "");
 
 		if (desc->mux_setting)
-- 
1.7.0.4



From swarren at nvidia.com  Mon Mar  5 19:22:16 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon, 5 Mar 2012 17:22:16 -0700
Subject: [PATCH V2 3/3] gpio: tegra: Hide tegra_gpio_enable/disable()
In-Reply-To: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
References: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
Message-ID: <1330993336-9538-3-git-send-email-swarren@nvidia.com>

Recent pinctrl discussions concluded that gpiolib APIs should in fact do
whatever is required to mux a GPIO onto pins, by calling pinctrl APIs if
required. This change implements this for the Tegra GPIO driver, and removes
calls to the Tegra-specific APIs from drivers and board files.

Cc: Chris Ball <cjb at laptop.org>
Cc: linux-mmc at vger.kernel.org
Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
v2: Adjusted per changes to latest version of Documentation/gpio.txt.
Fixed tegra_board_pinmux_bus_notify() to still check the device name,
so it waits for the pinmux device to be registered, not just /any/ device.

Merging note: The first two (or at least the 2nd) patches can go through
the pinctrl susbsystem without issue. This patch should probably be taken
through the Tegra tree. Once patch 2 is in pinctrl, and considered stable,
I can just use that as a dependency for the branch containing this Tegra
patch. I assume that this series will go into 3.5 not 3.4, but I'm willing
to be surprised:-)

 arch/arm/mach-tegra/board-dt-tegra20.c        |    1 -
 arch/arm/mach-tegra/board-harmony-pinmux.c    |   17 -----------
 arch/arm/mach-tegra/board-paz00-pinmux.c      |   14 ---------
 arch/arm/mach-tegra/board-pinmux.c            |   33 +++--------------------
 arch/arm/mach-tegra/board-pinmux.h            |    5 ---
 arch/arm/mach-tegra/board-seaboard-pinmux.c   |   32 ----------------------
 arch/arm/mach-tegra/board-seaboard.c          |    1 -
 arch/arm/mach-tegra/board-trimslice-pinmux.c  |   12 --------
 arch/arm/mach-tegra/include/mach/gpio-tegra.h |    9 ------
 arch/arm/mach-tegra/usb_phy.c                 |    1 -
 drivers/gpio/gpio-tegra.c                     |   36 ++++++++++++------------
 drivers/mmc/host/sdhci-tegra.c                |   24 +++-------------
 12 files changed, 27 insertions(+), 158 deletions(-)

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index e20b419..89adbb8 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -55,7 +55,6 @@ void ventana_pinmux_init(void);
 
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
-	OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 465808c..77a6006 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -15,13 +15,11 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/gpio.h>
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
 #include <mach/pinmux-tegra20.h>
 
-#include "gpio-names.h"
 #include "board-harmony.h"
 #include "board-pinmux.h"
 
@@ -144,24 +142,9 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static struct tegra_gpio_table gpio_table[] = {
-	{ .gpio = TEGRA_GPIO_SD2_CD,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_SD2_WP,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_SD2_POWER,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_SD4_CD,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_SD4_WP,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_SD4_POWER,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_CDC_IRQ,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_HP_DET,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_INT_MIC_EN,	.enable = true	},
-	{ .gpio = TEGRA_GPIO_EXT_MIC_EN,	.enable = true	},
-};
-
 static struct tegra_board_pinmux_conf conf = {
 	.pgs = harmony_pinmux,
 	.pg_count = ARRAY_SIZE(harmony_pinmux),
-	.gpios = gpio_table,
-	.gpio_count = ARRAY_SIZE(gpio_table),
 };
 
 void harmony_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index c775572..f0ec466 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -15,13 +15,11 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/gpio.h>
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
 #include <mach/pinmux-tegra20.h>
 
-#include "gpio-names.h"
 #include "board-paz00.h"
 #include "board-pinmux.h"
 
@@ -144,21 +142,9 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
 	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static struct tegra_gpio_table gpio_table[] = {
-	{ .gpio = TEGRA_GPIO_SD1_CD,	.enable = true },
-	{ .gpio = TEGRA_GPIO_SD1_WP,	.enable = true },
-	{ .gpio = TEGRA_GPIO_SD1_POWER,	.enable = true },
-	{ .gpio = TEGRA_ULPI_RST,	.enable = true },
-	{ .gpio = TEGRA_WIFI_PWRN,	.enable = true },
-	{ .gpio = TEGRA_WIFI_RST,	.enable = true },
-	{ .gpio = TEGRA_WIFI_LED,	.enable = true },
-};
-
 static struct tegra_board_pinmux_conf conf = {
 	.pgs = paz00_pinmux,
 	.pg_count = ARRAY_SIZE(paz00_pinmux),
-	.gpios = gpio_table,
-	.gpio_count = ARRAY_SIZE(gpio_table),
 };
 
 void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
index adc3efe..3015b5a 100644
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -18,7 +18,6 @@
 #include <linux/of.h>
 #include <linux/string.h>
 
-#include <mach/gpio-tegra.h>
 #include <mach/pinmux.h>
 
 #include "board-pinmux.h"
@@ -26,18 +25,6 @@
 
 struct tegra_board_pinmux_conf *confs[2];
 
-static void tegra_board_pinmux_setup_gpios(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(confs); i++) {
-		if (!confs[i])
-			continue;
-
-		tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
-	}
-}
-
 static void tegra_board_pinmux_setup_pinmux(void)
 {
 	int i;
@@ -57,29 +44,17 @@ static void tegra_board_pinmux_setup_pinmux(void)
 static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
 					 unsigned long event, void *vdev)
 {
-	static bool had_gpio;
-	static bool had_pinmux;
-
 	struct device *dev = vdev;
-	const char *devname;
 
 	if (event != BUS_NOTIFY_BOUND_DRIVER)
 		return NOTIFY_DONE;
 
-	devname = dev_name(dev);
+	if (strcmp(dev_name(dev), PINMUX_DEV))
+		return NOTIFY_DONE;
 
-	if (!had_gpio && !strcmp(devname, GPIO_DEV)) {
-		tegra_board_pinmux_setup_gpios();
-		had_gpio = true;
-	} else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
-		tegra_board_pinmux_setup_pinmux();
-		had_pinmux = true;
-	}
+	tegra_board_pinmux_setup_pinmux();
 
-	if (had_gpio && had_pinmux)
-		return NOTIFY_STOP_MASK;
-	else
-		return NOTIFY_DONE;
+	return NOTIFY_STOP_MASK;
 }
 
 static struct notifier_block nb = {
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
index 4aac735..e08214d 100644
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -15,11 +15,9 @@
 #ifndef __MACH_TEGRA_BOARD_PINMUX_H
 #define __MACH_TEGRA_BOARD_PINMUX_H
 
-#define GPIO_DEV "tegra-gpio"
 #define PINMUX_DEV "tegra-pinmux"
 
 struct tegra_pingroup_config;
-struct tegra_gpio_table;
 
 struct tegra_board_pinmux_conf {
 	struct tegra_pingroup_config *pgs;
@@ -27,9 +25,6 @@ struct tegra_board_pinmux_conf {
 
 	struct tegra_drive_pingroup_config *drives;
 	int drive_count;
-
-	struct tegra_gpio_table *gpios;
-	int gpio_count;
 };
 
 void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 55e7e43..3bf7e97 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -15,13 +15,11 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/gpio.h>
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
 #include <mach/pinmux-tegra20.h>
 
-#include "gpio-names.h"
 #include "board-pinmux.h"
 #include "board-seaboard.h"
 
@@ -179,35 +177,9 @@ static struct tegra_pingroup_config ventana_pinmux[] = {
 	{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 };
 
-static struct tegra_gpio_table common_gpio_table[] = {
-	{ .gpio = TEGRA_GPIO_SD2_CD,		.enable = true },
-	{ .gpio = TEGRA_GPIO_SD2_WP,		.enable = true },
-	{ .gpio = TEGRA_GPIO_SD2_POWER,		.enable = true },
-	{ .gpio = TEGRA_GPIO_CDC_IRQ,		.enable = true },
-};
-
-static struct tegra_gpio_table seaboard_gpio_table[] = {
-	{ .gpio = TEGRA_GPIO_LIDSWITCH,		.enable = true },
-	{ .gpio = TEGRA_GPIO_POWERKEY,		.enable = true },
-	{ .gpio = TEGRA_GPIO_HP_DET,		.enable = true },
-	{ .gpio = TEGRA_GPIO_ISL29018_IRQ,	.enable = true },
-	{ .gpio = TEGRA_GPIO_USB1,		.enable = true },
-};
-
-static struct tegra_gpio_table ventana_gpio_table[] = {
-	/* hp_det */
-	{ .gpio = TEGRA_GPIO_PW2,		.enable = true },
-	/* int_mic_en */
-	{ .gpio = TEGRA_GPIO_PX0,		.enable = true },
-	/* ext_mic_en */
-	{ .gpio = TEGRA_GPIO_PX1,		.enable = true },
-};
-
 static struct tegra_board_pinmux_conf common_conf = {
 	.pgs = common_pinmux,
 	.pg_count = ARRAY_SIZE(common_pinmux),
-	.gpios = common_gpio_table,
-	.gpio_count = ARRAY_SIZE(common_gpio_table),
 };
 
 static struct tegra_board_pinmux_conf seaboard_conf = {
@@ -215,15 +187,11 @@ static struct tegra_board_pinmux_conf seaboard_conf = {
 	.pg_count = ARRAY_SIZE(seaboard_pinmux),
 	.drives = seaboard_drive_pinmux,
 	.drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
-	.gpios = seaboard_gpio_table,
-	.gpio_count = ARRAY_SIZE(seaboard_gpio_table),
 };
 
 static struct tegra_board_pinmux_conf ventana_conf = {
 	.pgs = ventana_pinmux,
 	.pg_count = ARRAY_SIZE(ventana_pinmux),
-	.gpios = ventana_gpio_table,
-	.gpio_count = ARRAY_SIZE(ventana_gpio_table),
 };
 
 void seaboard_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index d669847..74a9db8 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -261,7 +261,6 @@ static void __init tegra_kaen_init(void)
 	debug_uart_platform_data[0].irq = INT_UARTB;
 
 	seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
-	tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
 
 	seaboard_common_init();
 
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index a21a2be..a1902d4 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  *
  */
-#include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/of.h>
@@ -21,7 +20,6 @@
 #include <mach/pinmux.h>
 #include <mach/pinmux-tegra20.h>
 
-#include "gpio-names.h"
 #include "board-pinmux.h"
 #include "board-trimslice.h"
 
@@ -144,19 +142,9 @@ static struct tegra_pingroup_config trimslice_pinmux[] = {
 	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
 };
 
-static struct tegra_gpio_table gpio_table[] = {
-	{ .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true	}, /* mmc4 cd */
-	{ .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true	}, /* mmc4 wp */
-
-	{ .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */
-	{ .gpio = TRIMSLICE_GPIO_USB2_RST,  .enable = true }, /* USB2 PHY rst */
-};
-
 static struct tegra_board_pinmux_conf conf = {
 	.pgs = trimslice_pinmux,
 	.pg_count = ARRAY_SIZE(trimslice_pinmux),
-	.gpios = gpio_table,
-	.gpio_count = ARRAY_SIZE(gpio_table),
 };
 
 void trimslice_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
index 6140820..a978b3c 100644
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
@@ -25,13 +25,4 @@
 
 #define TEGRA_NR_GPIOS		INT_GPIO_NR
 
-struct tegra_gpio_table {
-	int	gpio;	/* GPIO number */
-	bool	enable;	/* Enable for GPIO at init? */
-};
-
-void tegra_gpio_config(struct tegra_gpio_table *table, int num);
-void tegra_gpio_enable(int gpio);
-void tegra_gpio_disable(int gpio);
-
 #endif
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index c5b2ac0..d71d2fe 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -711,7 +711,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
 			err = -ENXIO;
 			goto err1;
 		}
-		tegra_gpio_enable(ulpi_config->reset_gpio);
 		gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
 		gpio_direction_output(ulpi_config->reset_gpio, 0);
 		phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 6f17671..88bcf36 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -26,10 +26,10 @@
 #include <linux/platform_device.h>
 #include <linux/module.h>
 #include <linux/irqdomain.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <asm/mach/irq.h>
 
-#include <mach/gpio-tegra.h>
 #include <mach/iomap.h>
 #include <mach/suspend.h>
 
@@ -105,16 +105,27 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
 	tegra_gpio_writel(val, reg);
 }
 
-void tegra_gpio_enable(int gpio)
+static void tegra_gpio_enable(int gpio)
 {
 	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 }
 
-void tegra_gpio_disable(int gpio)
+static void tegra_gpio_disable(int gpio)
 {
 	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 }
 
+int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	return pinctrl_request_gpio(offset);
+}
+
+void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	pinctrl_free_gpio(offset);
+	tegra_gpio_disable(offset);
+}
+
 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
 	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
@@ -128,6 +139,7 @@ static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
 	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
+	tegra_gpio_enable(offset);
 	return 0;
 }
 
@@ -136,6 +148,7 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 {
 	tegra_gpio_set(chip, offset, value);
 	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
+	tegra_gpio_enable(offset);
 	return 0;
 }
 
@@ -146,13 +159,14 @@ static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 
 static struct gpio_chip tegra_gpio_chip = {
 	.label			= "tegra-gpio",
+	.request		= tegra_gpio_request,
+	.free			= tegra_gpio_free,
 	.direction_input	= tegra_gpio_direction_input,
 	.get			= tegra_gpio_get,
 	.direction_output	= tegra_gpio_direction_output,
 	.set			= tegra_gpio_set,
 	.to_irq			= tegra_gpio_to_irq,
 	.base			= 0,
-	.ngpio			= TEGRA_NR_GPIOS,
 };
 
 static void tegra_gpio_irq_ack(struct irq_data *d)
@@ -459,20 +473,6 @@ static int __init tegra_gpio_init(void)
 }
 postcore_initcall(tegra_gpio_init);
 
-void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
-{
-	int i;
-
-	for (i = 0; i < num; i++) {
-		int gpio = table[i].gpio;
-
-		if (table[i].enable)
-			tegra_gpio_enable(gpio);
-		else
-			tegra_gpio_disable(gpio);
-	}
-}
-
 #ifdef	CONFIG_DEBUG_FS
 
 #include <linux/debugfs.h>
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index ccbca0b..1f63a07 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -270,7 +270,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
 				"failed to allocate power gpio\n");
 			goto err_power_req;
 		}
-		tegra_gpio_enable(plat->power_gpio);
 		gpio_direction_output(plat->power_gpio, 1);
 	}
 
@@ -281,7 +280,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
 				"failed to allocate cd gpio\n");
 			goto err_cd_req;
 		}
-		tegra_gpio_enable(plat->cd_gpio);
 		gpio_direction_input(plat->cd_gpio);
 
 		rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
@@ -302,7 +300,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
 				"failed to allocate wp gpio\n");
 			goto err_wp_req;
 		}
-		tegra_gpio_enable(plat->wp_gpio);
 		gpio_direction_input(plat->wp_gpio);
 	}
 
@@ -330,23 +327,17 @@ err_add_host:
 	clk_disable(pltfm_host->clk);
 	clk_put(pltfm_host->clk);
 err_clk_get:
-	if (gpio_is_valid(plat->wp_gpio)) {
-		tegra_gpio_disable(plat->wp_gpio);
+	if (gpio_is_valid(plat->wp_gpio))
 		gpio_free(plat->wp_gpio);
-	}
 err_wp_req:
 	if (gpio_is_valid(plat->cd_gpio))
 		free_irq(gpio_to_irq(plat->cd_gpio), host);
 err_cd_irq_req:
-	if (gpio_is_valid(plat->cd_gpio)) {
-		tegra_gpio_disable(plat->cd_gpio);
+	if (gpio_is_valid(plat->cd_gpio))
 		gpio_free(plat->cd_gpio);
-	}
 err_cd_req:
-	if (gpio_is_valid(plat->power_gpio)) {
-		tegra_gpio_disable(plat->power_gpio);
+	if (gpio_is_valid(plat->power_gpio))
 		gpio_free(plat->power_gpio);
-	}
 err_power_req:
 err_no_plat:
 	sdhci_pltfm_free(pdev);
@@ -363,21 +354,16 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
 
 	sdhci_remove_host(host, dead);
 
-	if (gpio_is_valid(plat->wp_gpio)) {
-		tegra_gpio_disable(plat->wp_gpio);
+	if (gpio_is_valid(plat->wp_gpio))
 		gpio_free(plat->wp_gpio);
-	}
 
 	if (gpio_is_valid(plat->cd_gpio)) {
 		free_irq(gpio_to_irq(plat->cd_gpio), host);
-		tegra_gpio_disable(plat->cd_gpio);
 		gpio_free(plat->cd_gpio);
 	}
 
-	if (gpio_is_valid(plat->power_gpio)) {
-		tegra_gpio_disable(plat->power_gpio);
+	if (gpio_is_valid(plat->power_gpio))
 		gpio_free(plat->power_gpio);
-	}
 
 	clk_disable(pltfm_host->clk);
 	clk_put(pltfm_host->clk);
-- 
1.7.0.4



From khilman at ti.com  Mon Mar  5 19:32:21 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 05 Mar 2012 16:32:21 -0800
Subject: [PATCHv3 0/6] ARM: OMAP3PLUS: IO daisychain support fixes
In-Reply-To: <1330525621-29836-1-git-send-email-t-kristo@ti.com> (Tero
 Kristo's message of "Wed, 29 Feb 2012 16:26:55 +0200")
References: <1330525621-29836-1-git-send-email-t-kristo@ti.com>
Message-ID: <877gyyin6y.fsf@ti.com>

Tero Kristo <t-kristo at ti.com> writes:

> Hi,
>
> The previous version of this set was sent by Vishwanath BS, but as he
> is busy with other stuff, I am taking over.
>
> Some basic info about this set based on comments received on set v2.
> IO chain is now enabled always, and a re-trigger for the chain is
> done during hwmod enable / disable. This means that IO chain is always
> armed according to the latest pad specific WAKE_ENABLE setting, and
> if it is modified, the IO chain needs to be re-armed (thus the hooks
> within omap_hwmod code.) Having IO chain armed all the time allows us
> to receive IO event interrupts even during non-sleep states if the
> corresponding hardware module is disabled, and is unable to detect any
> IO activity itself.
>
> Version 3 contains the following changes:
>
> - global: renamed *_trigger_wuclk_ctrl funcs as *_trigger_io_chain
> - patch 3: added trigger WUCLKIN disable at the end of omap4_trigger_io_chain
>   (fix pulled from the omap4 core retention set)
> - patch 5: added function pointer for using machine specific io_chain trigger
>   function, initialized during boot
> - patch 7 dropped as the support capability for omap3 is now handled as
>   part of patch 5 init
>
> Tested on omap3 beagle + omap4 blaze boards. Suspend / resume works, and
> hwmod_io interrupts are generated. Omap4 was tested with the core retention
> support set.

Reviewed-by: Kevin Hilman <khilman at ti.com>

I also tested this on 3430/n900 and verified IO wakeups are working as
expected.

Tested-by: Kevin Hilman <khilman at ti.com>

Paul, as discussed on IRC, when you're OK with it, this can go through
your queue since it's mostly PRM core code.

Kevin


From khilman at ti.com  Mon Mar  5 19:33:31 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 05 Mar 2012 16:33:31 -0800
Subject: [PATCHv3 1/4] ARM: OMAP4: suspend: Program all domains to
 retention
In-Reply-To: <1330529106-10423-2-git-send-email-t-kristo@ti.com> (Tero
 Kristo's message of "Wed, 29 Feb 2012 17:25:03 +0200")
References: <1330529106-10423-1-git-send-email-t-kristo@ti.com>
 <1330529106-10423-2-git-send-email-t-kristo@ti.com>
Message-ID: <871up6in50.fsf@ti.com>

Tero Kristo <t-kristo at ti.com> writes:

> From: Rajendra Nayak <rnayak at ti.com>
>
> Remove the FIXME's in the suspend sequence since
> we now intend to support system level RET support.
>
> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> Signed-off-by: Tero Kristo <t-kristo at ti.com>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

So this is the only patch in this series that is still needed.  However...

It doesn't seem like this all by itself is ready for mainline as we'll
suddenly start putting all powerdomains in retention without any
additional support.

I guess at a minimum it needs working IO wakeup support from the IO
daisy chain series.  Are there other dependencies here?

If not, I can queue this when Paul is ready to merge the IO wakeup
stuff.

Kevin

> ---
>  arch/arm/mach-omap2/pm44xx.c |    6 ------
>  1 files changed, 0 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> index c264ef7..1ab30a3 100644
> --- a/arch/arm/mach-omap2/pm44xx.c
> +++ b/arch/arm/mach-omap2/pm44xx.c
> @@ -151,12 +151,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
>  	if (!strncmp(pwrdm->name, "cpu", 3))
>  		return 0;
>  
> -	/*
> -	 * FIXME: Remove this check when core retention is supported
> -	 * Only MPUSS power domain is added in the list.
> -	 */
> -	if (strcmp(pwrdm->name, "mpu_pwrdm"))
> -		return 0;
>  
>  	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
>  	if (!pwrst)


From mgherzan at gmail.com  Mon Mar  5 19:46:37 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Tue,  6 Mar 2012 01:46:37 +0100
Subject: [PATCH] ARM: OMAP: WiLink platform data for the PandaBoard
Message-ID: <1330994797-17298-1-git-send-email-mgherzan@gmail.com>

The "uim" deamon requires sysfs entries that are filled in using
this platform data.

Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
---
 arch/arm/mach-omap2/board-omap4panda.c |   23 +++++++++++++++++------
 include/linux/ti_wilink_st.h           |    2 ++
 2 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index b1d74d6..37b437f 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -27,6 +27,7 @@
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
+#include <linux/ti_wilink_st.h>
 #include <linux/wl12xx.h>
 
 #include <mach/hardware.h>
@@ -56,15 +57,29 @@
 #define HDMI_GPIO_HPD  63 /* Hotplug detect */
 
 /* wl127x BT, FM, GPS connectivity chip */
-static int wl1271_gpios[] = {46, -1, -1};
+static struct ti_st_plat_data wilink_platform_data = {
+        .nshutdown_gpio	= 46,
+        .dev_name	= "/dev/ttyO1",
+        .flow_cntrl	= 1,
+        .baud_rate	= 3000000,
+	.chip_enable	= NULL,
+        .suspend	= NULL,
+        .resume		= NULL,
+};
+
 static struct platform_device wl1271_device = {
 	.name	= "kim",
 	.id	= -1,
 	.dev	= {
-		.platform_data	= &wl1271_gpios,
+		.platform_data	= &wilink_platform_data,
 	},
 };
 
+static struct platform_device btwilink_device = {
+	.name	= "btwilink",
+	.id	= -1,
+};
+
 static struct gpio_led gpio_leds[] = {
 	{
 		.name			= "pandaboard::status1",
@@ -91,10 +106,6 @@ static struct platform_device leds_gpio = {
 	},
 };
 
-static struct platform_device btwilink_device = {
-	.name	= "btwilink",
-	.id	= -1,
-};
 
 static struct platform_device *panda_devices[] __initdata = {
 	&leds_gpio,
diff --git a/include/linux/ti_wilink_st.h b/include/linux/ti_wilink_st.h
index 2ef4385..3ca0269 100644
--- a/include/linux/ti_wilink_st.h
+++ b/include/linux/ti_wilink_st.h
@@ -25,6 +25,8 @@
 #ifndef TI_WILINK_ST_H
 #define TI_WILINK_ST_H
 
+#include <linux/skbuff.h>
+
 /**
  * enum proto-type - The protocol on WiLink chips which share a
  *	common physical interface like UART.
-- 
1.7.9.1



From eric.dumazet at gmail.com  Mon Mar  5 19:49:18 2012
From: eric.dumazet at gmail.com (Eric Dumazet)
Date: Mon, 05 Mar 2012 16:49:18 -0800
Subject: [PATCH v4] lpc32xx: Added ethernet driver
In-Reply-To: <1330987524.2538.61.camel@bwh-desktop>
References: <1330983641-32622-1-git-send-email-stigge@antcom.de>
 <1330987524.2538.61.camel@bwh-desktop>
Message-ID: <1330994958.9504.2.camel@edumazet-glaptop>

On Mon, 2012-03-05 at 22:45 +0000, Ben Hutchings wrote:
> On Mon, 2012-03-05 at 22:40 +0100, Roland Stigge wrote:
> [...]

...

> > +				/* Copy packet from buffer */
> > +				memcpy(prdbuf,
> > +					pldat->rx_buff_v[rxconsidx], len);
> > +
> > +				/* Pass to upper layer */
> > +				skb->protocol = eth_type_trans(skb, ndev);
> > +				netif_rx(skb);
> > +				ndev->last_rx = jiffies;
> 
> Drivers don't need to set last_rx any more.

Also, a NAPI driver should call netif_receive_skb() instead of
netif_rx()

netif_rx() is more expensive because of additional queue, while
netif_receive_skb() directly calls the upper stacks.





From khilman at ti.com  Mon Mar  5 19:53:29 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 05 Mar 2012 16:53:29 -0800
Subject: [GIT PULL] ARM: OMAP: PM cleanups for v3.4
Message-ID: <87mx7uh7na.fsf@ti.com>

Tony,

Please pull the following PM related cleanups for v3.4.

Note that due to conflicts with changes from both your cleanup branch
and your hsmmc branch, I created a merge base by starting at 'cleanup'
and merging hsmmc, and basing this series on top.

Let me know if you want some other baseline for this series.

Kevin


The following changes since commit 015f1e4297ad32f83251f3f4cee2389ce5516e9e:

  Merge remote-tracking branch 'omap/hsmmc' into for_3.4/cleanup/pm-base (2012-03-05 15:37:04 -0800)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/cleanup/pm

for you to fetch changes up to 1416408d31236dc2a80d269aa23ffa93aa01e833:

  ARM: OMAP2+: PM: share some suspend-related functions across OMAP2, 3, 4 (2012-03-05 16:01:19 -0800)

----------------------------------------------------------------
Jean Pihet (1):
      ARM: OMAP2+: PM debug: fix the use of debugfs_create_* API

Kevin Hilman (1):
      ARM: OMAP: omap_device: remove omap_device_parent

Paul Walmsley (5):
      ARM: OMAP3: PM: remove superfluous calls to pwrdm_clear_all_prev_pwrst()
      ARM: OMAP2+: PM: clean up omap_set_pwrdm_state()
      ARM: OMAP2+: PM: share clkdms_setup() across OMAP2, 3, 4
      ARM: OMAP2+: omap_device: call all suspend, resume callbacks when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set
      ARM: OMAP2+: PM: share some suspend-related functions across OMAP2, 3, 4

 arch/arm/mach-omap2/omap-mpuss-lowpower.c     |    2 -
 arch/arm/mach-omap2/pm-debug.c                |    6 +-
 arch/arm/mach-omap2/pm.c                      |  113 ++++++++++++++++++++-----
 arch/arm/mach-omap2/pm.h                      |    2 +
 arch/arm/mach-omap2/pm24xx.c                  |   75 ++--------------
 arch/arm/mach-omap2/pm34xx.c                  |   74 +---------------
 arch/arm/mach-omap2/pm44xx.c                  |   57 +------------
 arch/arm/plat-omap/include/plat/omap_device.h |    2 +-
 arch/arm/plat-omap/omap-pm-noop.c             |    2 +-
 arch/arm/plat-omap/omap_device.c              |   24 ++----
 10 files changed, 118 insertions(+), 239 deletions(-)


From swarren at nvidia.com  Mon Mar  5 19:58:36 2012
From: swarren at nvidia.com (Stephen Warren)
Date: Mon,  5 Mar 2012 17:58:36 -0700
Subject: [PATCH] MAINTAINERS: update my email address
Message-ID: <1330995516-22160-1-git-send-email-swarren@nvidia.com>

From: Stephen Warren <swarren at wwwdotorg.org>

My nvidia.com address is hosted by MS Exchange Server and isn't suitable
for receiving patches. Update my MAINTAINERS entry to something that is.
Note: The old address continues to work, I just want to ensure that I
receive patches at the new one where possible.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
---
 MAINTAINERS |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4e41d52..e1fb35d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6510,7 +6510,7 @@ F:	include/linux/if_team.h
 TEGRA SUPPORT
 M:	Colin Cross <ccross at android.com>
 M:	Olof Johansson <olof at lixom.net>
-M:	Stephen Warren <swarren at nvidia.com>
+M:	Stephen Warren <swarren at wwwdotorg.org>
 L:	linux-tegra at vger.kernel.org
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
 S:	Supported
-- 
1.7.0.4



From bhutchings at solarflare.com  Mon Mar  5 20:26:17 2012
From: bhutchings at solarflare.com (Ben Hutchings)
Date: Tue, 6 Mar 2012 01:26:17 +0000
Subject: [PATCH v4] lpc32xx: Added ethernet driver
In-Reply-To: <1330994958.9504.2.camel@edumazet-glaptop>
References: <1330983641-32622-1-git-send-email-stigge@antcom.de>
 <1330987524.2538.61.camel@bwh-desktop>
 <1330994958.9504.2.camel@edumazet-glaptop>
Message-ID: <1330997177.3022.51.camel@deadeye>

On Mon, 2012-03-05 at 16:49 -0800, Eric Dumazet wrote:
> On Mon, 2012-03-05 at 22:45 +0000, Ben Hutchings wrote:
> > On Mon, 2012-03-05 at 22:40 +0100, Roland Stigge wrote:
> > [...]
> 
> ...
> 
> > > +				/* Copy packet from buffer */
> > > +				memcpy(prdbuf,
> > > +					pldat->rx_buff_v[rxconsidx], len);
> > > +
> > > +				/* Pass to upper layer */
> > > +				skb->protocol = eth_type_trans(skb, ndev);
> > > +				netif_rx(skb);
> > > +				ndev->last_rx = jiffies;
> > 
> > Drivers don't need to set last_rx any more.
> 
> Also, a NAPI driver should call netif_receive_skb() instead of
> netif_rx()
> 
> netif_rx() is more expensive because of additional queue, while
> netif_receive_skb() directly calls the upper stacks.

Yes, but not until the poll function is changed to enable IRQs.

Ben.

-- 
Ben Hutchings, Staff Engineer, Solarflare
Not speaking for my employer; that's the marketing department's job.
They asked us to note that Solarflare product names are trademarked.



From nico at fluxnic.net  Mon Mar  5 20:41:51 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 05 Mar 2012 20:41:51 -0500 (EST)
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <201202281945.39419.arnd@arndb.de>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201202281945.39419.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1203052035170.31242@xanadu.home>

On Tue, 28 Feb 2012, Arnd Bergmann wrote:

> On Tuesday 28 February 2012, Rob Herring wrote:
> > ixp2000 has no commits other than tree-wide changes or refactoring since
> > 2006. No maintainer is listed for ixp2000 either.
> 
> I have this in my copy of the MAINTAINERS file:
> 
> ARM/INTEL IXP2000 ARM ARCHITECTURE
> M:      Lennert Buytenhek <kernel at wantstofly.org>
> L:      linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> S:      Maintained
> 
> It's missing an F: line, otherwise it suggests that the platform is still
> maintained by Lennert and it certainly builds just fine. Unfortunately he
> seems to have fallen off the edge of the planet at the end of last year.

FYI, here's a snippet of a conversation I just had with Lennert on IRC 
today:

13:05 < nico> do you still care about ixp2000?
13:22 < lennert> not really, no
13:58 < nico> do you think we could remove it from the kernel tree?
14:01 < lennert> go for it, and remove ixp23xx too while you're at it


Nicolas


From jh80.chung at samsung.com  Mon Mar  5 21:29:38 2012
From: jh80.chung at samsung.com (Jaehoon Chung)
Date: Tue, 06 Mar 2012 11:29:38 +0900
Subject: [PATCH] ARM: SAMSUNG: change the name from s3c-sdhci to
 exynos4-sdhci
In-Reply-To: <CAJuYYwTh8tVdA0X-TLEU-9O_M0_PmJR=i3WYAQXsaRcPF3MbJA@mail.gmail.com>
References: <4F45D343.6020409@samsung.com>
 <CAJuYYwTh8tVdA0X-TLEU-9O_M0_PmJR=i3WYAQXsaRcPF3MbJA@mail.gmail.com>
Message-ID: <4F557692.8090102@samsung.com>

Hi Kukjin.

Is it merged?

Best Regards,
Jaehoon Chung

On 02/24/2012 06:56 PM, Thomas Abraham wrote:

> On 23 February 2012 11:18, Jaehoon Chung <jh80.chung at samsung.com> wrote:
>> Thomas Arbrahams's patchset have changed the device name in sdhci-s3c.c
>> (mmc: sdhci-s3c: Rework platform data and add device tree support)
>> But didn't change the regulator_consumer name.
>> So maybe didn't initialize the mmc/sd card for exynos4.
>>
>> This patch is fixed that (based-on linux-samsung for-next branch)
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung at samsung.com>
>> Signed-off-by: kyungmin Park <kyungmin.park at samsung.com>
>> ---
>>  arch/arm/mach-exynos/mach-nuri.c           |    4 ++--
>>  arch/arm/mach-exynos/mach-universal_c210.c |    2 +-
>>  2 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
>> index a6b9162..251dd7a 100644
>> --- a/arch/arm/mach-exynos/mach-nuri.c
>> +++ b/arch/arm/mach-exynos/mach-nuri.c
>> @@ -116,7 +116,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
>>  };
>>
>>  static struct regulator_consumer_supply emmc_supplies[] = {
>> -       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
>> +       REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
>>        REGULATOR_SUPPLY("vmmc", "dw_mmc"),
>>  };
>>
>> @@ -415,7 +415,7 @@ static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
>>        REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
>>  };
>>  static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
>> -       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
>> +       REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
>>  };
>>  static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
>>        REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
>> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
>> index 6017a21..320cb1d 100644
>> --- a/arch/arm/mach-exynos/mach-universal_c210.c
>> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
>> @@ -749,7 +749,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
>>  };
>>
>>  static struct regulator_consumer_supply mmc0_supplies[] = {
>> -       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
>> +       REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
>>  };
>>
>>  static struct regulator_init_data mmc0_fixed_voltage_init_data = {
> 
> Reviewed-by: Thomas Abraham <thomas.abraham at linaro.org>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 




From shawn.guo at linaro.org  Mon Mar  5 21:50:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 6 Mar 2012 10:50:27 +0800
Subject: [PATCH v8 2/2] Regulator: Add Anatop regulator driver
In-Reply-To: <1330960049-28170-2-git-send-email-paul.liu@linaro.org>
References: <1330960049-28170-1-git-send-email-paul.liu@linaro.org>
 <1330960049-28170-2-git-send-email-paul.liu@linaro.org>
Message-ID: <20120306025025.GL16232@S2101-09.ap.freescale.net>

On Mon, Mar 05, 2012 at 11:07:28PM +0800, Ying-Chun Liu (PaulLiu) wrote:
...
> +MODULE_AUTHOR("Nancy Chen <Nancy.Chen at freescale.com>");
> +MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");

I meant something like:

MODULE_AUTHOR("Nancy Chen <Nancy.Chen at freescale.com>, "
	      "Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");

Otherwise:

Acked-by: Shawn Guo <shawn.guo at linaro.org>

> +MODULE_DESCRIPTION("ANATOP Regulator driver");
> +MODULE_LICENSE("GPL v2");

-- 
Regards,
Shawn


From robherring2 at gmail.com  Mon Mar  5 21:44:07 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 05 Mar 2012 20:44:07 -0600
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201202281945.39419.arnd@arndb.de>
 <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
Message-ID: <4F5579F7.7040603@gmail.com>

On 03/05/2012 07:41 PM, Nicolas Pitre wrote:
> On Tue, 28 Feb 2012, Arnd Bergmann wrote:
> 
>> On Tuesday 28 February 2012, Rob Herring wrote:
>>> ixp2000 has no commits other than tree-wide changes or refactoring since
>>> 2006. No maintainer is listed for ixp2000 either.
>>
>> I have this in my copy of the MAINTAINERS file:
>>
>> ARM/INTEL IXP2000 ARM ARCHITECTURE
>> M:      Lennert Buytenhek <kernel at wantstofly.org>
>> L:      linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
>> S:      Maintained
>>
>> It's missing an F: line, otherwise it suggests that the platform is still
>> maintained by Lennert and it certainly builds just fine. Unfortunately he
>> seems to have fallen off the edge of the planet at the end of last year.
> 
> FYI, here's a snippet of a conversation I just had with Lennert on IRC 
> today:
> 
> 13:05 < nico> do you still care about ixp2000?
> 13:22 < lennert> not really, no
> 13:58 < nico> do you think we could remove it from the kernel tree?
> 14:01 < lennert> go for it, and remove ixp23xx too while you're at it

So, can we do this for 3.4 or should wait for 3.5?

Rob


From dh09.lee at samsung.com  Mon Mar  5 21:44:58 2012
From: dh09.lee at samsung.com (Donghwa Lee)
Date: Tue, 06 Mar 2012 11:44:58 +0900
Subject: [PATCH] MAINTAINERS: add entry for exynos mipi display drivers
Message-ID: <4F557A2A.2080108@samsung.com>

Hi, I'd like to add Inki Dae, Donghwa Lee and Kyungmin Park as 
maintainers who developers for exynos mipi display drivers for
video/driver/exynos/exynos_mipi* and include/video/exynos_mipi*.

Signed-off-by: Donghwa Lee <dh09.lee at samsung.com>
Signed-off-by: Inki Dae <inki.dae at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 MAINTAINERS |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b087b3bc..eb5fbcb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2351,6 +2351,15 @@ S:	Supported
 F:	drivers/gpu/drm/exynos
 F:	include/drm/exynos*
 
+EXYNOS MIPI DISPLAY DRIVERS
+M:	Inki Dae <inki.dae at samsung.com>
+M:	Donghwa Lee <dh09.lee at samsung.com>
+M:	Kyungmin Park <kyungmin.park at samsung.com>
+L:	linux-fbdev at vger.kernel.org
+S:	Maintained
+F:	drivers/video/exynos/exynos_mipi*
+F:	include/video/exynos_mipi*
+
 DSCC4 DRIVER
 M:	Francois Romieu <romieu at fr.zoreil.com>
 L:	netdev at vger.kernel.org
-- 
1.7.4.1


From haojian.zhuang at marvell.com  Mon Mar  5 21:42:10 2012
From: haojian.zhuang at marvell.com (Haojian Zhuang)
Date: Tue,  6 Mar 2012 10:42:10 +0800
Subject: [PATCH v3 1/7] serial: pxa: add OF support
In-Reply-To: <201203051255.37311.arnd@arndb.de>
References: <201203051255.37311.arnd@arndb.de>
Message-ID: <1331001730-13429-1-git-send-email-haojian.zhuang@marvell.com>

Parse uart device id from alias in DTS file.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/tty/serial/pxa.c |   52 +++++++++++++++++++++++++++++++++++----------
 1 files changed, 40 insertions(+), 12 deletions(-)

diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
index 5c8e3bb..23d32f6 100644
--- a/drivers/tty/serial/pxa.c
+++ b/drivers/tty/serial/pxa.c
@@ -36,6 +36,7 @@
 #include <linux/circ_buf.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
@@ -44,6 +45,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
+#define PXA_NAME_LEN		8
+
 struct uart_pxa_port {
 	struct uart_port        port;
 	unsigned char           ier;
@@ -51,7 +54,7 @@ struct uart_pxa_port {
 	unsigned char           mcr;
 	unsigned int            lsr_break_flag;
 	struct clk		*clk;
-	char			*name;
+	char			name[PXA_NAME_LEN];
 };
 
 static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
@@ -781,6 +784,33 @@ static const struct dev_pm_ops serial_pxa_pm_ops = {
 };
 #endif
 
+#ifdef CONFIG_OF
+static struct of_device_id serial_pxa_dt_ids[] = {
+	{ .compatible = "mrvl,pxa-uart", },
+	{ .compatible = "mrvl,mmp-uart", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids);
+#endif
+
+static int serial_pxa_probe_dt(struct platform_device *pdev,
+			       struct uart_pxa_port *sport)
+{
+	struct device_node *np = pdev->dev.of_node;
+	int ret;
+
+	if (!np)
+		return 1;
+
+	ret = of_alias_get_id(np, "serial");
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+		return ret;
+	}
+	sport->port.line = ret;
+	return 0;
+}
+
 static int serial_pxa_probe(struct platform_device *dev)
 {
 	struct uart_pxa_port *sport;
@@ -808,20 +838,16 @@ static int serial_pxa_probe(struct platform_device *dev)
 	sport->port.irq = irqres->start;
 	sport->port.fifosize = 64;
 	sport->port.ops = &serial_pxa_pops;
-	sport->port.line = dev->id;
 	sport->port.dev = &dev->dev;
 	sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
 	sport->port.uartclk = clk_get_rate(sport->clk);
 
-	switch (dev->id) {
-	case 0: sport->name = "FFUART"; break;
-	case 1: sport->name = "BTUART"; break;
-	case 2: sport->name = "STUART"; break;
-	case 3: sport->name = "HWUART"; break;
-	default:
-		sport->name = "???";
-		break;
-	}
+	ret = serial_pxa_probe_dt(dev, sport);
+	if (ret > 0)
+		sport->port.line = dev->id;
+	else if (ret < 0)
+		goto err_clk;
+	snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
 
 	sport->port.membase = ioremap(mmres->start, resource_size(mmres));
 	if (!sport->port.membase) {
@@ -829,7 +855,7 @@ static int serial_pxa_probe(struct platform_device *dev)
 		goto err_clk;
 	}
 
-	serial_pxa_ports[dev->id] = sport;
+	serial_pxa_ports[sport->port.line] = sport;
 
 	uart_add_one_port(&serial_pxa_reg, &sport->port);
 	platform_set_drvdata(dev, sport);
@@ -850,6 +876,7 @@ static int serial_pxa_remove(struct platform_device *dev)
 	platform_set_drvdata(dev, NULL);
 
 	uart_remove_one_port(&serial_pxa_reg, &sport->port);
+	kfree(sport->name);
 	clk_put(sport->clk);
 	kfree(sport);
 
@@ -866,6 +893,7 @@ static struct platform_driver serial_pxa_driver = {
 #ifdef CONFIG_PM
 		.pm	= &serial_pxa_pm_ops,
 #endif
+		.of_match_table = serial_pxa_dt_ids,
 	},
 };
 
-- 
1.7.0.4



From paul at pwsan.com  Mon Mar  5 21:59:40 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 5 Mar 2012 19:59:40 -0700 (MST)
Subject: [PATCHv4 1/6] ARM: OMAP3 PM: correct enable/disable of daisy io
 chain
In-Reply-To: <1330701475-22576-2-git-send-email-t-kristo@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-2-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203051953580.6649@utopia.booyaka.com>


cc'ing Nilesh, Rajendra

Hi

On Fri, 2 Mar 2012, Tero Kristo wrote:

> From: Mohan V <mohanv at ti.com>
> 
> Currently the enabling and disabling of IO Daisy chain is not
> according to the TRM. The below steps are followed to enable/
> disable the IO chain according to the "Sec 3.5.7.2.2
> I/O Wake-Up Mechanism" in OMAP3630 Public TRM[1].
> 
> Steps to enable IO chain:
> [a] Set PM_WKEN_WKUP.EN_IO bit
> [b] Set the PM_WKEN_WKUP.EN_IO_CHAIN bit
> [c] Poll for PM_WKST_WKUP.ST_IO_CHAIN.
> [d] When ST_IO_CHAIN bit set to 1, clear PM_WKEN_WKUP.EN_IO_CHAIN

Looking at the above TRM section, it doesn't mention clearing 
PM_WKEN_WKUP.EN_IO_CHAIN at all.  This only seems to be mentioned (in a 
rather unclear way) in the OMAP4430 TRM.

Since Tero and Rajendra are reporting that this series works, I assume 
that the conclusion is that this patch description just needs to be fixed.  
Could someone confirm that this is indeed the case -- that I/O wakeups are 
expected to work when EN_IO_CHAIN/WUCLK_CTRL is 0?

Is the I/O wakeup path from the pad to the PRCM wakeup line completely 
asynchronous?


- Paul


From rnayak at ti.com  Mon Mar  5 22:53:38 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 06 Mar 2012 09:23:38 +0530
Subject: [PATCHv4 1/6] ARM: OMAP3 PM: correct enable/disable of daisy
 io chain
In-Reply-To: <alpine.DEB.2.00.1203051953580.6649@utopia.booyaka.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-2-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203051953580.6649@utopia.booyaka.com>
Message-ID: <4F558A42.1020503@ti.com>

Hi Paul,

On Tuesday 06 March 2012 08:29 AM, Paul Walmsley wrote:
>
> cc'ing Nilesh, Rajendra
>
> Hi
>
> On Fri, 2 Mar 2012, Tero Kristo wrote:
>
>> From: Mohan V<mohanv at ti.com>
>>
>> Currently the enabling and disabling of IO Daisy chain is not
>> according to the TRM. The below steps are followed to enable/
>> disable the IO chain according to the "Sec 3.5.7.2.2
>> I/O Wake-Up Mechanism" in OMAP3630 Public TRM[1].
>>
>> Steps to enable IO chain:
>> [a] Set PM_WKEN_WKUP.EN_IO bit
>> [b] Set the PM_WKEN_WKUP.EN_IO_CHAIN bit
>> [c] Poll for PM_WKST_WKUP.ST_IO_CHAIN.
>> [d] When ST_IO_CHAIN bit set to 1, clear PM_WKEN_WKUP.EN_IO_CHAIN
>
> Looking at the above TRM section, it doesn't mention clearing
> PM_WKEN_WKUP.EN_IO_CHAIN at all.  This only seems to be mentioned (in a
> rather unclear way) in the OMAP4430 TRM.
>
> Since Tero and Rajendra are reporting that this series works, I assume
> that the conclusion is that this patch description just needs to be fixed.
> Could someone confirm that this is indeed the case -- that I/O wakeups are
> expected to work when EN_IO_CHAIN/WUCLK_CTRL is 0?

Yes, thats my understanding too, again based on taking to people like
Nilesh, because the documentation just doesn't mention this clearly.
The 4430 TRM is a tad bit better like you said.

I guess your confusion of IO wakeups working with EN_IO_CHAIN set to '0'
is also probably coming from the fact that the bit itself is called
*EN_IO_CHAIN* which is a completely *wrong* name for the bit, as
compared to what it does.
That bit is actually used to send a WUCLK pulse through the chain, so
you set it to '1' and wait for it to propagate through the chain, then
you set it to '0' and again wait for it to propagate through.

The control to enable/disable is at 2 levels, a global switch which is
'EN_IO' in case of OMAP3 and the one at the individual pad level.

You can also read this thread which has some more explanation based on
my understanding of how this works
http://www.spinics.net/lists/linux-serial/msg04480.html

regards,
Rajendra

>
> Is the I/O wakeup path from the pad to the PRCM wakeup line completely
> asynchronous?
>
>
> - Paul



From rnayak at ti.com  Mon Mar  5 22:59:10 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 06 Mar 2012 09:29:10 +0530
Subject: [PATCHv4 1/6] ARM: OMAP3 PM: correct enable/disable of daisy
 io chain
In-Reply-To: <4F558A42.1020503@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-2-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203051953580.6649@utopia.booyaka.com>
 <4F558A42.1020503@ti.com>
Message-ID: <4F558B8E.2000702@ti.com>

On Tuesday 06 March 2012 09:23 AM, Rajendra Nayak wrote:
> Hi Paul,
>
> On Tuesday 06 March 2012 08:29 AM, Paul Walmsley wrote:
>>
>> cc'ing Nilesh, Rajendra

looks like you missed coping Nilesh. He's
copied in now.

>>
>> Hi
>>
>> On Fri, 2 Mar 2012, Tero Kristo wrote:
>>
>>> From: Mohan V<mohanv at ti.com>
>>>
>>> Currently the enabling and disabling of IO Daisy chain is not
>>> according to the TRM. The below steps are followed to enable/
>>> disable the IO chain according to the "Sec 3.5.7.2.2
>>> I/O Wake-Up Mechanism" in OMAP3630 Public TRM[1].
>>>
>>> Steps to enable IO chain:
>>> [a] Set PM_WKEN_WKUP.EN_IO bit
>>> [b] Set the PM_WKEN_WKUP.EN_IO_CHAIN bit
>>> [c] Poll for PM_WKST_WKUP.ST_IO_CHAIN.
>>> [d] When ST_IO_CHAIN bit set to 1, clear PM_WKEN_WKUP.EN_IO_CHAIN
>>
>> Looking at the above TRM section, it doesn't mention clearing
>> PM_WKEN_WKUP.EN_IO_CHAIN at all. This only seems to be mentioned (in a
>> rather unclear way) in the OMAP4430 TRM.
>>
>> Since Tero and Rajendra are reporting that this series works, I assume
>> that the conclusion is that this patch description just needs to be
>> fixed.
>> Could someone confirm that this is indeed the case -- that I/O wakeups
>> are
>> expected to work when EN_IO_CHAIN/WUCLK_CTRL is 0?
>
> Yes, thats my understanding too, again based on taking to people like
> Nilesh, because the documentation just doesn't mention this clearly.
> The 4430 TRM is a tad bit better like you said.
>
> I guess your confusion of IO wakeups working with EN_IO_CHAIN set to '0'
> is also probably coming from the fact that the bit itself is called
> *EN_IO_CHAIN* which is a completely *wrong* name for the bit, as
> compared to what it does.
> That bit is actually used to send a WUCLK pulse through the chain, so
> you set it to '1' and wait for it to propagate through the chain, then
> you set it to '0' and again wait for it to propagate through.
>
> The control to enable/disable is at 2 levels, a global switch which is
> 'EN_IO' in case of OMAP3 and the one at the individual pad level.
>
> You can also read this thread which has some more explanation based on
> my understanding of how this works
> http://www.spinics.net/lists/linux-serial/msg04480.html
>
> regards,
> Rajendra
>
>>
>> Is the I/O wakeup path from the pad to the PRCM wakeup line completely
>> asynchronous?
>>
>>
>> - Paul
>



From paul at pwsan.com  Mon Mar  5 23:02:36 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 5 Mar 2012 21:02:36 -0700 (MST)
Subject: [PATCHv4 5/6] ARM: OMAP3PLUS PM: Add IO Daisychain support via
 hwmod mux
In-Reply-To: <1330701475-22576-6-git-send-email-t-kristo@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-6-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203052057050.6649@utopia.booyaka.com>

Hi

a few comments:

On Fri, 2 Mar 2012, Tero Kristo wrote:

> From: Vishwanath BS <vishwanath.bs at ti.com>
> 
> IO Daisychain feature has to be triggered whenever there is a change in
> device's mux configuration (See section 3.9.4 in OMAP4 Public TRM vP).
> 
> Now devices can idle independent of the powerdomain, there can be a
> window where device is idled and corresponding powerdomain can be
> ON/INACTIVE state. In such situations, since both module wake up is
> enabled at padlevel as well as io daisychain sequence is triggered,
> there will be 2 PRCM interrupts (Module async wake up via swakeup and
> IO Pad interrupt). But as PRCM Interrupt handler clears the Module
> Padlevel WKST bit in the first interrupt, module specific interrupt
> handler will not triggered for the second time
> 
> Also look at detailed explanation given by Rajendra at
> http://www.spinics.net/lists/linux-serial/msg04480.html
> 
> Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
> Signed-off-by: Tero Kristo <t-kristo at ti.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod.c |    9 +++++++--
>  arch/arm/mach-omap2/pm.c         |   15 +++++++++++++++
>  arch/arm/mach-omap2/pm.h         |    1 +
>  3 files changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 5192cab..56adbfb 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c

...

> @@ -1535,8 +1536,10 @@ static int _enable(struct omap_hwmod *oh)
>  	/* Mux pins for device runtime if populated */
>  	if (oh->mux && (!oh->mux->enabled ||
>  			((oh->_state == _HWMOD_STATE_IDLE) &&
> -			 oh->mux->pads_dynamic)))
> +			 oh->mux->pads_dynamic))) {
>  		omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
> +		omap_trigger_io_chain();

Looks racy: if two hwmods with dynamic mux entries go idle at the same 
time, or one goes idle while another one is enabled, won't the calls to 
omap_trigger_io_chain() race?  Locking is per-hwmod and there's no locking 
in omap_trigger_io_chain() or the functions it calls.

Also, won't this result in needless resets of the I/O chain?  Seems like 
we'd only need to do this when the next power state of the enclosing 
powerdomain will enter either RETENTION or OFF.  And even then, it 
presumably should only happen when the last active device in that 
powerdomain is going idle?


- Paul


From robherring2 at gmail.com  Mon Mar  5 23:02:57 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon,  5 Mar 2012 22:02:57 -0600
Subject: [PATCH v4 1/4] ARM: provide runtime hook for ioremap/iounmap
In-Reply-To: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
Message-ID: <1331006580-3579-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

We have compile time over-ride of ioremap and iounmap, but an run-time
override is needed for multi-platform builds. This adds an extra function
pointer check, but ioremap is not peformance critical. The option for
compile time selection remains.

The caller variant is used here to provide correct caller information as
ARM can only support level 0 for __builtin_return_address.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/include/asm/io.h |    7 ++++++-
 arch/arm/mm/ioremap.c     |   16 ++++++++++++++++
 2 files changed, 22 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 9275828..6c363c1 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -83,6 +83,11 @@ extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, uns
 extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
 extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
 extern void __iounmap(volatile void __iomem *addr);
+extern void __arm_iounmap(volatile void __iomem *addr);
+
+extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+	unsigned int, void *);
+extern void (*arch_iounmap)(volatile void __iomem *);
 
 /*
  * Bad read/write accesses...
@@ -266,7 +271,7 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
  */
 #ifndef __arch_ioremap
 #define __arch_ioremap			__arm_ioremap
-#define __arch_iounmap			__iounmap
+#define __arch_iounmap			__arm_iounmap
 #endif
 
 #define ioremap(cookie,size)		__arch_ioremap((cookie), (size), MT_DEVICE)
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 80632e8..c37c67a 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -306,9 +306,16 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
 }
 EXPORT_SYMBOL(__arm_ioremap_pfn);
 
+void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *);
+EXPORT_SYMBOL(arch_ioremap_caller);
+
 void __iomem *
 __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 {
+	if (arch_ioremap_caller)
+		return arch_ioremap_caller(phys_addr, size, mtype,
+			__builtin_return_address(0));
+
 	return __arm_ioremap_caller(phys_addr, size, mtype,
 			__builtin_return_address(0));
 }
@@ -370,3 +377,12 @@ void __iounmap(volatile void __iomem *io_addr)
 	vunmap(addr);
 }
 EXPORT_SYMBOL(__iounmap);
+
+void (*arch_iounmap)(volatile void __iomem *) = __iounmap;
+EXPORT_SYMBOL(arch_iounmap);
+
+void __arm_iounmap(volatile void __iomem *io_addr)
+{
+	arch_iounmap(io_addr);
+}
+EXPORT_SYMBOL(__arm_iounmap);
-- 
1.7.5.4



From robherring2 at gmail.com  Mon Mar  5 23:02:58 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon,  5 Mar 2012 22:02:58 -0600
Subject: [PATCH v4 2/4] ARM: imx: convert to common runtime ioremap hook
In-Reply-To: <1331006580-3579-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331006580-3579-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331006580-3579-2-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert i.MX platforms to use the common run-time ioremap hook instead of
the imx specific hook.

Also, move addr_in_module out of io.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Sascha Hauer <kernel at pengutronix.de>
---
 arch/arm/mach-imx/mm-imx3.c               |   10 +++++-----
 arch/arm/plat-mxc/include/mach/hardware.h |    3 +++
 arch/arm/plat-mxc/include/mach/io.h       |   17 -----------------
 3 files changed, 8 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 8404ee7..04be18d 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -59,8 +59,8 @@ static void imx3_idle(void)
 		: "=r" (reg));
 }
 
-static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
-				  unsigned int mtype)
+static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
+					 unsigned int mtype, void *caller)
 {
 	if (mtype == MT_DEVICE) {
 		/*
@@ -73,7 +73,7 @@ static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
 			mtype = MT_DEVICE_NONSHARED;
 	}
 
-	return __arm_ioremap(phys_addr, size, mtype);
+	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
 }
 
 void imx3_init_l2x0(void)
@@ -132,7 +132,7 @@ void __init imx31_init_early(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX31);
 	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-	imx_ioremap = imx3_ioremap;
+	arch_ioremap_caller = imx3_ioremap_caller;
 	arm_pm_idle = imx3_idle;
 }
 
@@ -196,7 +196,7 @@ void __init imx35_init_early(void)
 	mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
 	mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
 	arm_pm_idle = imx3_idle;
-	imx_ioremap = imx3_ioremap;
+	arch_ioremap_caller = imx3_ioremap_caller;
 }
 
 void __init mx35_init_irq(void)
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index a599f01..ca06a68 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -28,6 +28,9 @@
 #define IOMEM(addr)	((void __force __iomem *)(addr))
 #endif
 
+#define addr_in_module(addr, mod) \
+	((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
+
 #define IMX_IO_P2V_MODULE(addr, module)					\
 	(((addr) - module ## _BASE_ADDR) < module ## _SIZE ?		\
 	 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index 338300b..ea9d95e 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -14,23 +14,6 @@
 /* Allow IO space to be anywhere in the memory */
 #define IO_SPACE_LIMIT 0xffffffff
 
-#define __arch_ioremap __imx_ioremap
-#define __arch_iounmap __iounmap
-
-#define addr_in_module(addr, mod) \
-	((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
-
-extern void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int);
-
-static inline void __iomem *
-__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
-{
-	if (imx_ioremap != NULL)
-		return imx_ioremap(phys_addr, size, mtype);
-	else
-		return __arm_ioremap(phys_addr, size, mtype);
-}
-
 /* io address mapping macro */
 #define __io(a)		__typesafe_io(a)
 
-- 
1.7.5.4



From robherring2 at gmail.com  Mon Mar  5 23:02:59 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon,  5 Mar 2012 22:02:59 -0600
Subject: [PATCH v4 3/4] ARM: msm: use runtime ioremap hook
In-Reply-To: <1331006580-3579-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331006580-3579-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331006580-3579-3-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert msm platforms to use run-time ioremap hook instead of the compile
time hook.

According to David Brown, only the msm7201 needed the ioremap hook.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Tested-by: David Brown <davidb at codeaurora.org>
Acked-by: David Brown <davidb at codeaurora.org>
Cc: Daniel Walker <dwalker at fifo99.com>
Cc: Bryan Huntsman <bryanh at codeaurora.org>
---
 arch/arm/mach-msm/board-halibut.c               |    6 ++++++
 arch/arm/mach-msm/board-trout.c                 |    6 ++++++
 arch/arm/mach-msm/include/mach/io.h             |    5 -----
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |    6 ++++++
 arch/arm/mach-msm/io.c                          |    8 +++-----
 5 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index a60ab6d..3698a37 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -68,6 +68,11 @@ static struct platform_device *devices[] __initdata = {
 
 extern struct sys_timer msm_timer;
 
+static void __init halibut_init_early(void)
+{
+	arch_ioremap_caller = __msm_ioremap_caller;
+}
+
 static void __init halibut_init_irq(void)
 {
 	msm_init_irq();
@@ -96,6 +101,7 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
 	.atag_offset	= 0x100,
 	.fixup		= halibut_fixup,
 	.map_io		= halibut_map_io,
+	.init_early	= halibut_init_early,
 	.init_irq	= halibut_init_irq,
 	.init_machine	= halibut_init,
 	.timer		= &msm_timer,
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 6b9b227..5414f76 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -43,6 +43,11 @@ static struct platform_device *devices[] __initdata = {
 
 extern struct sys_timer msm_timer;
 
+static void __init trout_init_early(void)
+{
+	arch_ioremap_caller = __msm_ioremap_caller;
+}
+
 static void __init trout_init_irq(void)
 {
 	msm_init_irq();
@@ -96,6 +101,7 @@ MACHINE_START(TROUT, "HTC Dream")
 	.atag_offset	= 0x100,
 	.fixup		= trout_fixup,
 	.map_io		= trout_map_io,
+	.init_early	= trout_init_early,
 	.init_irq	= trout_init_irq,
 	.init_machine	= trout_init,
 	.timer		= &msm_timer,
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index dc1b928..c6ff9bb 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -18,11 +18,6 @@
 
 #define IO_SPACE_LIMIT 0xffffffff
 
-#define __arch_ioremap __msm_ioremap
-#define __arch_iounmap __iounmap
-
-void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)    (a)
 
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 8af4612..152b3b7 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -111,5 +111,11 @@
 #define MSM_AD5_PHYS          0xAC000000
 #define MSM_AD5_SIZE          (SZ_1M*13)
 
+#ifndef __ASSEMBLY__
+
+extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+					  unsigned int mtype, void *caller);
+
+#endif
 
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 578b04e..a1e7b11 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -172,8 +172,8 @@ void __init msm_map_msm7x30_io(void)
 }
 #endif /* CONFIG_ARCH_MSM7X30 */
 
-void __iomem *
-__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+				   unsigned int mtype, void *caller)
 {
 	if (mtype == MT_DEVICE) {
 		/* The peripherals in the 88000000 - D0000000 range
@@ -184,7 +184,5 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 			mtype = MT_DEVICE_NONSHARED;
 	}
 
-	return __arm_ioremap_caller(phys_addr, size, mtype,
-		__builtin_return_address(0));
+	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
 }
-EXPORT_SYMBOL(__msm_ioremap);
-- 
1.7.5.4



From robherring2 at gmail.com  Mon Mar  5 23:03:00 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon,  5 Mar 2012 22:03:00 -0600
Subject: [PATCH v4 4/4] ARM: iop13xx: use runtime ioremap hook
In-Reply-To: <1331006580-3579-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331006580-3579-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331006580-3579-4-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert iop13xx platforms to use run-time ioremap hook instead of the
compile time hook. The custom ioremap is still needed for 64-bit address
handling.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/mach-iop13xx/include/mach/io.h |    7 -------
 arch/arm/mach-iop13xx/io.c              |   18 ++++++++++--------
 arch/arm/mach-iop13xx/iq81340mc.c       |    1 +
 arch/arm/mach-iop13xx/iq81340sc.c       |    1 +
 4 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index dffb234..2a69fc0 100644
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -26,16 +26,9 @@
 #define __mem_isa(a) (a)
 
 extern void __iomem * __iop13xx_io(unsigned long io_addr);
-extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
-	unsigned int mtype);
-extern void __iop13xx_iounmap(void __iomem *addr);
-
 extern u32 iop13xx_atue_mem_base;
 extern u32 iop13xx_atux_mem_base;
 extern size_t iop13xx_atue_mem_size;
 extern size_t iop13xx_atux_mem_size;
 
-#define __arch_ioremap	__iop13xx_ioremap
-#define __arch_iounmap	__iop13xx_iounmap
-
 #endif
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 48642e6..6dd5b49 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -40,8 +40,8 @@ void * __iomem __iop13xx_io(unsigned long io_addr)
 }
 EXPORT_SYMBOL(__iop13xx_io);
 
-void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
-	unsigned int mtype)
+static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
+	size_t size, unsigned int mtype, void *caller)
 {
 	void __iomem * retval;
 
@@ -76,17 +76,14 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
 		break;
 	default:
 		retval = __arm_ioremap_caller(cookie, size, mtype,
-				__builtin_return_address(0));
+				caller);
 	}
 
 	return retval;
 }
-EXPORT_SYMBOL(__iop13xx_ioremap);
 
-void __iop13xx_iounmap(void __iomem *addr)
+static void __iop13xx_iounmap(volatile void __iomem *addr)
 {
-	extern void __iounmap(volatile void __iomem *addr);
-
 	if (iop13xx_atue_mem_base)
 		if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
 	 	    addr < (void __iomem *) (iop13xx_atue_mem_base +
@@ -110,4 +107,9 @@ void __iop13xx_iounmap(void __iomem *addr)
 skip:
 	return;
 }
-EXPORT_SYMBOL(__iop13xx_iounmap);
+
+void __init iop13xx_init_early(void)
+{
+	arch_ioremap_caller = __iop13xx_ioremap_caller;
+	arch_iounmap = __iop13xx_iounmap;
+}
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index abaee88..5c96b73 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -92,6 +92,7 @@ static struct sys_timer iq81340mc_timer = {
 MACHINE_START(IQ81340MC, "Intel IQ81340MC")
 	/* Maintainer: Dan Williams <dan.j.williams at intel.com> */
 	.atag_offset    = 0x100,
+	.init_early     = iop13xx_init_early,
 	.map_io         = iop13xx_map_io,
 	.init_irq       = iop13xx_init_irq,
 	.timer          = &iq81340mc_timer,
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index 690916a..aa4dd75 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -94,6 +94,7 @@ static struct sys_timer iq81340sc_timer = {
 MACHINE_START(IQ81340SC, "Intel IQ81340SC")
 	/* Maintainer: Dan Williams <dan.j.williams at intel.com> */
 	.atag_offset    = 0x100,
+	.init_early     = iop13xx_init_early,
 	.map_io         = iop13xx_map_io,
 	.init_irq       = iop13xx_init_irq,
 	.timer          = &iq81340sc_timer,
-- 
1.7.5.4



From robherring2 at gmail.com  Mon Mar  5 23:07:37 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 05 Mar 2012 22:07:37 -0600
Subject: [PATCH v3 02/30] ARM: provide runtime hook for ioremap/iounmap
In-Reply-To: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-3-git-send-email-robherring2@gmail.com>
 <alpine.LFD.2.02.1203051415150.31242@xanadu.home>
 <201203052013.26688.arnd@arndb.de>
 <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
Message-ID: <4F558D89.7030905@gmail.com>

On 03/05/2012 03:11 PM, Nicolas Pitre wrote:
> On Mon, 5 Mar 2012, Arnd Bergmann wrote:
> 
>> On Monday 05 March 2012, Nicolas Pitre wrote:
>>> Given that the majority of existing platforms don't need the 
>>> indirection, should we make this indirection conditional on 
>>> CONFIG_NEED_IOREMAP_HOOK and let those who need it select it?  Or maybe 
>>> this isn't performance critical and we just don't care?  In any case I'd 
>>> like to see such reasoning captured in the commit log.
>>
>> It's certainly not performance critical, but there may be some space overhead
>> in the .text section of the kernel that we could avoid by adding another
>> indirection.
> 
> Of course the size issue can be mitigated significantly by replacing:
> 
> extern void __iomem * (*arch_ioremap)(unsigned long, size_t, unsigned int);
> extern void (*arch_iounmap)(volatile void __iomem *);
> 
> #define __arch_ioremap                 arch_ioremap
> #define __arch_iounmap                 arch_iounmap
> 
> by:
> 
> extern void __iomem * (*arch_ioremap)(unsigned long, size_t, unsigned int);
> extern void (*arch_iounmap)(volatile void __iomem *);
> 
> extern void __iomem * __arch_ioremap(unsigned long, size_t, unsigned int);
> extern void __arch_iounmap(volatile void __iomem *);
> 
> and out of line:
> 
> void __iomem *__arch_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
> {
> 	return arch_ioremap(phys_addr, size, mtype);
> }
> 
> void __arch_iounmap(volatile void __iomem *io_addr)
> {
> 	arch_iounmap(io_addr);
> }

This doesn't quite work if we keep the compile time option, but I came
up with something that accomplishes the same thing.

There's not much point in converting ixp4xx and ebsa110 to runtime hooks
as they still have other io.h needs.

Rob


From paul at pwsan.com  Mon Mar  5 23:13:15 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 5 Mar 2012 21:13:15 -0700 (MST)
Subject: [PATCHv4 1/6] ARM: OMAP3 PM: correct enable/disable of daisy io
 chain
In-Reply-To: <4F558A42.1020503@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-2-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203051953580.6649@utopia.booyaka.com>
 <4F558A42.1020503@ti.com>
Message-ID: <alpine.DEB.2.00.1203052103440.6649@utopia.booyaka.com>

Hi Rajendra

(thanks for adding in Nilesh, added him again here)

On Tue, 6 Mar 2012, Rajendra Nayak wrote:

> Yes, thats my understanding too, again based on taking to people like
> Nilesh, because the documentation just doesn't mention this clearly.
> The 4430 TRM is a tad bit better like you said.
> 
> I guess your confusion of IO wakeups working with EN_IO_CHAIN set to '0'
> is also probably coming from the fact that the bit itself is called
> *EN_IO_CHAIN* which is a completely *wrong* name for the bit, as
> compared to what it does.
> That bit is actually used to send a WUCLK pulse through the chain, so
> you set it to '1' and wait for it to propagate through the chain, then
> you set it to '0' and again wait for it to propagate through.

Okay.  So to confirm: EN_IO_CHAIN doesn't enable a continuous clock, it 
just controls the WUCLKIN line directly?

> The control to enable/disable is at 2 levels, a global switch which is
> 'EN_IO' in case of OMAP3 and the one at the individual pad level.

Do you happen to know what EN_IO/GLOBAL_WUEN does?  For example, if it's 
0, will the I/O chain not latch in wakeup events occuring on the pads?  
Or does it just cause the PRCM to ignore any PRCM wakeups coming from the 
I/O chain?  (Or something else, heh)

> You can also read this thread which has some more explanation based on
> my understanding of how this works
> http://www.spinics.net/lists/linux-serial/msg04480.html

I've been reading that post; it's been quite helpful.


- Paul


From paul at pwsan.com  Mon Mar  5 23:21:46 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 5 Mar 2012 21:21:46 -0700 (MST)
Subject: [PATCHv4 4/6] ARM: OMAP3+: PRM: Enable IO wake up
In-Reply-To: <1330701475-22576-5-git-send-email-t-kristo@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-5-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203052001240.6649@utopia.booyaka.com>

added Rajendra, Nilesh, Vishwa, Mohan

Hi

On Fri, 2 Mar 2012, Tero Kristo wrote:

> Enable IO Wake up for OMAP3/4 as part of PRM Init. Currently this has been
> managed in cpuidle path which is not the right place. Subsequent patch
> will remove IO Daisy chain handling in cpuidle path once daisy chain is
> handled as part of hwmod mux. This patch also moves the OMAP4 IO wakeup
> enable code from the trigger function to init time setup.
> 
> Signed-off-by: Tero Kristo <t-kristo at ti.com>

Should we keep the I/O wakeups enabled all the time?

Seems like that could result in at least one spurious wake-up event -- and 
thus a PRCM interrupt -- for each I/O pad that has WAKEUPENABLE set.  
Seems like these interrupts could recur every time the I/O chain is reset.  
And that the I/O chain is now reset in every hwmod idle and enable 
operation for an IP block that contains dynamic mux data?

Thinking about the problem na?vely... maybe you all can think through this 
with me:

Consider an IP block 'A' that has a signal (like the UART rx_irrx signal) 
that's mux'ed to a pad with WAKEUPENABLE set.  (Some examples of 'A' might 
include a UART, a GPIO, or a McBSP.)  

Shouldn't we enable I/O wakeups (by setting EN_IO/GLOBAL_WUEN) only 
immediately before the powerdomain containing IP block 'A' is going to 
transition into RETENTION or OFF?

If we do that, then we can avoid needlessly resetting the I/O chain when a 
powerdomain is not going to go into a low-power state.

I haven't measured the time it takes for the I/O chain to be reset.  
Maybe one of you have.  But that 100 microsecond timeout that was 
specified in two of the other patches in this series has me a little 
worried.


- Paul

From rnayak at ti.com  Mon Mar  5 23:21:42 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 06 Mar 2012 09:51:42 +0530
Subject: [PATCHv4 5/6] ARM: OMAP3PLUS PM: Add IO Daisychain support via
 hwmod mux
In-Reply-To: <alpine.DEB.2.00.1203052057050.6649@utopia.booyaka.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-6-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203052057050.6649@utopia.booyaka.com>
Message-ID: <4F5590D6.8030707@ti.com>

Hi Paul,

On Tuesday 06 March 2012 09:32 AM, Paul Walmsley wrote:
> Hi
>
> a few comments:
>
> On Fri, 2 Mar 2012, Tero Kristo wrote:
>
>> From: Vishwanath BS<vishwanath.bs at ti.com>
>>
>> IO Daisychain feature has to be triggered whenever there is a change in
>> device's mux configuration (See section 3.9.4 in OMAP4 Public TRM vP).
>>
>> Now devices can idle independent of the powerdomain, there can be a
>> window where device is idled and corresponding powerdomain can be
>> ON/INACTIVE state. In such situations, since both module wake up is
>> enabled at padlevel as well as io daisychain sequence is triggered,
>> there will be 2 PRCM interrupts (Module async wake up via swakeup and
>> IO Pad interrupt). But as PRCM Interrupt handler clears the Module
>> Padlevel WKST bit in the first interrupt, module specific interrupt
>> handler will not triggered for the second time
>>
>> Also look at detailed explanation given by Rajendra at
>> http://www.spinics.net/lists/linux-serial/msg04480.html
>>
>> Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com>
>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
>> ---
>>   arch/arm/mach-omap2/omap_hwmod.c |    9 +++++++--
>>   arch/arm/mach-omap2/pm.c         |   15 +++++++++++++++
>>   arch/arm/mach-omap2/pm.h         |    1 +
>>   3 files changed, 23 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
>> index 5192cab..56adbfb 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod.c
>
> ...
>
>> @@ -1535,8 +1536,10 @@ static int _enable(struct omap_hwmod *oh)
>>   	/* Mux pins for device runtime if populated */
>>   	if (oh->mux&&  (!oh->mux->enabled ||
>>   			((oh->_state == _HWMOD_STATE_IDLE)&&
>> -			 oh->mux->pads_dynamic)))
>> +			 oh->mux->pads_dynamic))) {
>>   		omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
>> +		omap_trigger_io_chain();
>
> Looks racy: if two hwmods with dynamic mux entries go idle at the same
> time, or one goes idle while another one is enabled, won't the calls to
> omap_trigger_io_chain() race?  Locking is per-hwmod and there's no locking
> in omap_trigger_io_chain() or the functions it calls.

I agree, this needs locking to avoid races.

>
> Also, won't this result in needless resets of the I/O chain?  Seems like
> we'd only need to do this when the next power state of the enclosing
> powerdomain will enter either RETENTION or OFF.  And even then, it
> presumably should only happen when the last active device in that
> powerdomain is going idle?

Yes, the module async wakeups will work as long as the power domain
enclosing the module is not in OSWR or OFF, so ideally this trigger
should happen only when all modules in the given powerdomain are
disabled and we plan to program the Powerdomain down to OSWR or
OFF state. With what we are doing today we end up with periods when we
have multiple wakeups (a module wakeup as well as an IO wakeup).
The last we discussed this with Kevin, there wasn't a better place where
we could trigger this, with no usecounting at powerdomain level you
didn't know when the last active device in the powerdomain was going
idle.
But now with Tero's series which adds usecounting at power/voltage
domain level, maybe its possible, but I need to look more.
Do you already have an idea on where this would fit better, so we
avoid this multiple wakeup scenario?

regards,
Rajendra

>
>
> - Paul



From rnayak at ti.com  Mon Mar  5 23:32:56 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 06 Mar 2012 10:02:56 +0530
Subject: [PATCHv4 1/6] ARM: OMAP3 PM: correct enable/disable of daisy
 io chain
In-Reply-To: <alpine.DEB.2.00.1203052103440.6649@utopia.booyaka.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-2-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203051953580.6649@utopia.booyaka.com>
 <4F558A42.1020503@ti.com>
 <alpine.DEB.2.00.1203052103440.6649@utopia.booyaka.com>
Message-ID: <4F559378.3010204@ti.com>

On Tuesday 06 March 2012 09:43 AM, Paul Walmsley wrote:
> Hi Rajendra
>
> (thanks for adding in Nilesh, added him again here)
>
> On Tue, 6 Mar 2012, Rajendra Nayak wrote:
>
>> Yes, thats my understanding too, again based on taking to people like
>> Nilesh, because the documentation just doesn't mention this clearly.
>> The 4430 TRM is a tad bit better like you said.
>>
>> I guess your confusion of IO wakeups working with EN_IO_CHAIN set to '0'
>> is also probably coming from the fact that the bit itself is called
>> *EN_IO_CHAIN* which is a completely *wrong* name for the bit, as
>> compared to what it does.
>> That bit is actually used to send a WUCLK pulse through the chain, so
>> you set it to '1' and wait for it to propagate through the chain, then
>> you set it to '0' and again wait for it to propagate through.
>
> Okay.  So to confirm: EN_IO_CHAIN doesn't enable a continuous clock, it
> just controls the WUCLKIN line directly?

Right.

>
>> The control to enable/disable is at 2 levels, a global switch which is
>> 'EN_IO' in case of OMAP3 and the one at the individual pad level.
>
> Do you happen to know what EN_IO/GLOBAL_WUEN does?  For example, if it's
> 0, will the I/O chain not latch in wakeup events occuring on the pads?

Yes, it wouldn't. Figure 3-74 in OMAP4430_ES2.x Public TRM vO
explains this better.

The WUEN signal to each pad (which can be used to enable IO-daisy
for the given pad) is a AND of a signal from PRCM and
one from SCM.
The signal from PRCM can be enabled by writing into
EN_IO/GLOBAL_WUEN bit.
The signal from SCM can be enabled by writing to the individual
pad registers in SCM
CONTROL.CONTROL_PADCONF_<IOpad>[14] WAKEUPENABLE0
CONTROL.CONTROL_PADCONF_<IOpad>[30] WAKEUPENABLE1.

If either one of them is not enabled the IO wakeups on the pads won't
be latched. So if EN_IO/GLOBAL_WUEN is disabled, none of the pads will
be able to generate IO wakeups.

> Or does it just cause the PRCM to ignore any PRCM wakeups coming from the
> I/O chain?  (Or something else, heh)
>
>> You can also read this thread which has some more explanation based on
>> my understanding of how this works
>> http://www.spinics.net/lists/linux-serial/msg04480.html
>
> I've been reading that post; it's been quite helpful.
>
>
> - Paul



From rnayak at ti.com  Mon Mar  5 23:50:20 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 06 Mar 2012 10:20:20 +0530
Subject: [PATCHv4 4/6] ARM: OMAP3+: PRM: Enable IO wake up
In-Reply-To: <alpine.DEB.2.00.1203052001240.6649@utopia.booyaka.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-5-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203052001240.6649@utopia.booyaka.com>
Message-ID: <4F55978C.7030407@ti.com>

On Tuesday 06 March 2012 09:51 AM, Paul Walmsley wrote:
> added Rajendra, Nilesh, Vishwa, Mohan
>
> Hi
>
> On Fri, 2 Mar 2012, Tero Kristo wrote:
>
>> Enable IO Wake up for OMAP3/4 as part of PRM Init. Currently this has been
>> managed in cpuidle path which is not the right place. Subsequent patch
>> will remove IO Daisy chain handling in cpuidle path once daisy chain is
>> handled as part of hwmod mux. This patch also moves the OMAP4 IO wakeup
>> enable code from the trigger function to init time setup.
>>
>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
>
> Should we keep the I/O wakeups enabled all the time?
>
> Seems like that could result in at least one spurious wake-up event -- and
> thus a PRCM interrupt -- for each I/O pad that has WAKEUPENABLE set.
> Seems like these interrupts could recur every time the I/O chain is reset.
> And that the I/O chain is now reset in every hwmod idle and enable
> operation for an IP block that contains dynamic mux data?
>
> Thinking about the problem na?vely... maybe you all can think through this
> with me:
>
> Consider an IP block 'A' that has a signal (like the UART rx_irrx signal)
> that's mux'ed to a pad with WAKEUPENABLE set.  (Some examples of 'A' might
> include a UART, a GPIO, or a McBSP.)
>
> Shouldn't we enable I/O wakeups (by setting EN_IO/GLOBAL_WUEN) only
> immediately before the powerdomain containing IP block 'A' is going to
> transition into RETENTION or OFF?

Hi Paul,

I completely agree with your observations and we knew we would have
additional wakeups with this design. Like I mentioned in the other
thread, we went ahead with this approach knowing we need to optimize
with some kind of powerdomain level usecounting in the future, because
it didn't exist back then when we did it this way.
But now that we already have it, maybe we can fix this and do
it such that we completely avoid an additional wakeup interrupt.

>
> If we do that, then we can avoid needlessly resetting the I/O chain when a
> powerdomain is not going to go into a low-power state.
>
> I haven't measured the time it takes for the I/O chain to be reset.
> Maybe one of you have.  But that 100 microsecond timeout that was
> specified in two of the other patches in this series has me a little
> worried.

I haven't profiled it myself but I am guessing the delay isn't much.
The 100us comes from the fact that there is no documentation on the
exact delay, so went around asking whats the *real worst case* delay,
and we got an answer, 100us should be really big enough :)

regards,
Rajendra

>
>
> - Paul



From rnayak at ti.com  Mon Mar  5 23:56:03 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 06 Mar 2012 10:26:03 +0530
Subject: [PATCHv4 4/6] ARM: OMAP3+: PRM: Enable IO wake up
In-Reply-To: <4F55978C.7030407@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-5-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203052001240.6649@utopia.booyaka.com>
 <4F55978C.7030407@ti.com>
Message-ID: <4F5598E3.4050506@ti.com>

On Tuesday 06 March 2012 10:20 AM, Rajendra Nayak wrote:
> On Tuesday 06 March 2012 09:51 AM, Paul Walmsley wrote:
>> added Rajendra, Nilesh, Vishwa, Mohan
>>
>> Hi
>>
>> On Fri, 2 Mar 2012, Tero Kristo wrote:
>>
>>> Enable IO Wake up for OMAP3/4 as part of PRM Init. Currently this has
>>> been
>>> managed in cpuidle path which is not the right place. Subsequent patch
>>> will remove IO Daisy chain handling in cpuidle path once daisy chain is
>>> handled as part of hwmod mux. This patch also moves the OMAP4 IO wakeup
>>> enable code from the trigger function to init time setup.
>>>
>>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
>>
>> Should we keep the I/O wakeups enabled all the time?
>>
>> Seems like that could result in at least one spurious wake-up event --
>> and
>> thus a PRCM interrupt -- for each I/O pad that has WAKEUPENABLE set.
>> Seems like these interrupts could recur every time the I/O chain is
>> reset.
>> And that the I/O chain is now reset in every hwmod idle and enable
>> operation for an IP block that contains dynamic mux data?
>>
>> Thinking about the problem na?vely... maybe you all can think through
>> this
>> with me:
>>
>> Consider an IP block 'A' that has a signal (like the UART rx_irrx signal)
>> that's mux'ed to a pad with WAKEUPENABLE set. (Some examples of 'A' might
>> include a UART, a GPIO, or a McBSP.)
>>
>> Shouldn't we enable I/O wakeups (by setting EN_IO/GLOBAL_WUEN) only
>> immediately before the powerdomain containing IP block 'A' is going to
>> transition into RETENTION or OFF?
>
> Hi Paul,
>
> I completely agree with your observations and we knew we would have
> additional wakeups with this design. Like I mentioned in the other
> thread, we went ahead with this approach knowing we need to optimize
> with some kind of powerdomain level usecounting in the future, because
> it didn't exist back then when we did it this way.
> But now that we already have it, maybe we can fix this and do
> it such that we completely avoid an additional wakeup interrupt.
>
>>
>> If we do that, then we can avoid needlessly resetting the I/O chain
>> when a
>> powerdomain is not going to go into a low-power state.
>>
>> I haven't measured the time it takes for the I/O chain to be reset.
>> Maybe one of you have. But that 100 microsecond timeout that was
>> specified in two of the other patches in this series has me a little
>> worried.
>
> I haven't profiled it myself but I am guessing the delay isn't much.

Having said that, I do agree with you that, however small the delay,
we end up doing needless IO trigger when the powerdomain isn't
really entering a low power state.

> The 100us comes from the fact that there is no documentation on the
> exact delay, so went around asking whats the *real worst case* delay,
> and we got an answer, 100us should be really big enough :)
>
> regards,
> Rajendra
>
>>
>>
>> - Paul
>



From haojian.zhuang at gmail.com  Tue Mar  6 00:30:08 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue,  6 Mar 2012 13:30:08 +0800
Subject: [PATCH] mfd: pcap: depend on arch-pxa
Message-ID: <1331011808-28307-1-git-send-email-haojian.zhuang@gmail.com>

drivers/mfd/ezx-pcap.c: In function ?pcap_isr_work?:
drivers/mfd/ezx-pcap.c:206:2: error: implicit declaration of function
?pxa_irq_to_gpio?
make[2]: *** [drivers/mfd/ezx-pcap.o] Error 1

PCAP driver invokes irq_to_gpio() directly. This function isn't common
function in most silicons. PCAP driver is enabled for EZX machine with
arch-pxa. Now use pxa_irq_to_gpio() instead.

It's only a workaround for this issue. Acutally the best solution is
using thread irq to fix this issue.

Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
---
 drivers/mfd/Kconfig    |    2 +-
 drivers/mfd/ezx-pcap.c |    3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index f147395..e88d315 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -619,7 +619,7 @@ config AB3100_OTP
 
 config EZX_PCAP
 	bool "PCAP Support"
-	depends on GENERIC_HARDIRQS && SPI_MASTER
+	depends on GENERIC_HARDIRQS && SPI_MASTER && ARCH_PXA
 	help
 	  This enables the PCAP ASIC present on EZX Phones. This is
 	  needed for MMC, TouchScreen, Sound, USB, etc..
diff --git a/drivers/mfd/ezx-pcap.c b/drivers/mfd/ezx-pcap.c
index 43a76c4..e9320e2 100644
--- a/drivers/mfd/ezx-pcap.c
+++ b/drivers/mfd/ezx-pcap.c
@@ -18,6 +18,7 @@
 #include <linux/mfd/ezx-pcap.h>
 #include <linux/spi/spi.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/slab.h>
 
 #define PCAP_ADC_MAXQ		8
@@ -202,7 +203,7 @@ static void pcap_isr_work(struct work_struct *work)
 		}
 		local_irq_enable();
 		ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
-	} while (gpio_get_value(irq_to_gpio(pcap->spi->irq)));
+	} while (gpio_get_value(pxa_irq_to_gpio(pcap->spi->irq)));
 }
 
 static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
-- 
1.7.5.4



From shawn.guo at linaro.org  Tue Mar  6 00:46:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 6 Mar 2012 13:46:49 +0800
Subject: [PATCH v2 10/17] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <20120305173910.GZ3852@pengutronix.de>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-11-git-send-email-shawn.guo@linaro.org>
 <20120305173910.GZ3852@pengutronix.de>
Message-ID: <20120306054648.GN16232@S2101-09.ap.freescale.net>

On Mon, Mar 05, 2012 at 06:39:10PM +0100, Sascha Hauer wrote:
> On Mon, Mar 05, 2012 at 10:30:58PM +0800, Shawn Guo wrote:
> > Freescale PowerPC and ARM/IMX families share the same SSI IP block.
> > The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
> > code sharing and consolidation can happen.
> > 
> > This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
> > in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
> > IMX platform.
> > 
> > Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> > ---
> >  sound/soc/Kconfig                        |    1 -
> >  sound/soc/Makefile                       |    1 -
> >  sound/soc/fsl/Kconfig                    |   92 ++++++++++++++++++++++++++++++
> >  sound/soc/fsl/Makefile                   |   22 +++++++
> >  sound/soc/{imx => fsl}/eukrea-tlv320.c   |    2 +-
> >  sound/soc/{imx => fsl}/imx-audmux.c      |    0
> >  sound/soc/{imx => fsl}/imx-audmux.h      |    0
> >  sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c |    0
> 
> Maybe this is the right time to rename this file to something like
> imx-pcm-dma.c since it has nothing to do with mx2 anymore.
> 
Ok, will change it in the next post.

-- 
Regards,
Shawn


From nm at ti.com  Tue Mar  6 00:44:44 2012
From: nm at ti.com (Nishanth Menon)
Date: Mon, 5 Mar 2012 23:44:44 -0600
Subject: [PATCHv4 2/6] ARM: OMAP3 PM: Move IO Daisychain function to
 omap3 prm file
In-Reply-To: <1330701475-22576-3-git-send-email-t-kristo@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-3-git-send-email-t-kristo@ti.com>
Message-ID: <20120306054443.GA5670@kobold>

On 17:17-20120302, Tero Kristo wrote:
> From: Vishwanath BS <vishwanath.bs at ti.com>
> 
> Since IO Daisychain modifies only PRM registers, it makes sense to move
> it to PRM File. Also changed the timeout value for IO chain enable to
> 100us and added a wait for status disable at the end.
> 
[...]
> +/*
> + * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
> + * the I/O ring after asserting WUCLKIN high
> + */
> +#define MAX_IOPAD_LATCH_TIME 100
> +
> +/* OMAP3 Daisychain enable sequence */
> +void omap3_trigger_io_chain(void)
> +{
> +	int i = 0;
> +
> +	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> +				   PM_WKEN);
> +	/* Do a readback to assure write has been done */
> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
> +
> +	omap_test_timeout(((omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
> +			    OMAP3430_ST_IO_CHAIN_MASK) == 1),
umm
arch/arm/mach-omap2/prm-regbits-34xx.h:#define OMAP3430_ST_IO_CHAIN_MASK
(1 << 16)
(reg & (1 << 16)) == 1
will ever be true?

-- 
Regards,
Nishanth Menon


From haojian.zhuang at gmail.com  Tue Mar  6 00:51:11 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 6 Mar 2012 13:51:11 +0800
Subject: [GIT PULL][v3.4] pull request on pxa tree for DT branch
Message-ID: <CAN1soZyA8iYJjcWRQoPEP=ksCwVfP6JYqcAdVh_qYjg2oc5XqQ@mail.gmail.com>

Hi Arnd,

Please help to pull DT patches on pxa tree. I based it on v3.3-rc6.

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

  Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:
  git://github.com/hzhuang1/linux.git dt

Haojian Zhuang (6):
      serial: pxa: add OF support
      i2c: pxa: add OF support
      ARM: mmp: enable rtc clk in pxa168
      ARM: mmp: append OF support on pxa168
      ARM: dts: append DTS file of pxa168
      Document: devicetree: add OF documents for arch-mmp

 Documentation/devicetree/bindings/arm/mrvl.txt     |    6 +
 .../devicetree/bindings/gpio/mrvl-gpio.txt         |   23 +++++
 Documentation/devicetree/bindings/i2c/mrvl-i2c.txt |   37 ++++++++
 .../devicetree/bindings/rtc/sa1100-rtc.txt         |   17 ++++
 .../devicetree/bindings/serial/mrvl-serial.txt     |    4 +
 arch/arm/boot/dts/pxa168-aspenite.dts              |   38 ++++++++
 arch/arm/boot/dts/pxa168.dtsi                      |   98 ++++++++++++++++++++
 arch/arm/mach-mmp/Kconfig                          |   10 ++
 arch/arm/mach-mmp/Makefile                         |    1 +
 arch/arm/mach-mmp/mmp-dt.c                         |   75 +++++++++++++++
 arch/arm/mach-mmp/pxa168.c                         |    2 +
 drivers/i2c/busses/i2c-pxa.c                       |   95 +++++++++++++++----
 drivers/tty/serial/pxa.c                           |   52 ++++++++---
 13 files changed, 425 insertions(+), 33 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
 create mode 100644 Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
 create mode 100644 Documentation/devicetree/bindings/serial/mrvl-serial.txt
 create mode 100644 arch/arm/boot/dts/pxa168-aspenite.dts
 create mode 100644 arch/arm/boot/dts/pxa168.dtsi
 create mode 100644 arch/arm/mach-mmp/mmp-dt.c


From rnayak at ti.com  Tue Mar  6 01:00:46 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 06 Mar 2012 11:30:46 +0530
Subject: [PATCHv4 2/6] ARM: OMAP3 PM: Move IO Daisychain function to omap3
 prm file
In-Reply-To: <20120306054443.GA5670@kobold>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-3-git-send-email-t-kristo@ti.com>
 <20120306054443.GA5670@kobold>
Message-ID: <4F55A80E.3090606@ti.com>

On Tuesday 06 March 2012 11:14 AM, Nishanth Menon wrote:
> On 17:17-20120302, Tero Kristo wrote:
>> From: Vishwanath BS<vishwanath.bs at ti.com>
>>
>> Since IO Daisychain modifies only PRM registers, it makes sense to move
>> it to PRM File. Also changed the timeout value for IO chain enable to
>> 100us and added a wait for status disable at the end.
>>
> [...]
>> +/*
>> + * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
>> + * the I/O ring after asserting WUCLKIN high
>> + */
>> +#define MAX_IOPAD_LATCH_TIME 100
>> +
>> +/* OMAP3 Daisychain enable sequence */
>> +void omap3_trigger_io_chain(void)
>> +{
>> +	int i = 0;
>> +
>> +	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
>> +				   PM_WKEN);
>> +	/* Do a readback to assure write has been done */
>> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
>> +
>> +	omap_test_timeout(((omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST)&
>> +			    OMAP3430_ST_IO_CHAIN_MASK) == 1),
> umm
> arch/arm/mach-omap2/prm-regbits-34xx.h:#define OMAP3430_ST_IO_CHAIN_MASK
> (1<<  16)
> (reg&  (1<<  16)) == 1
> will ever be true?

good catch. Its should actually be '((reg & (1 << 16)) >> 16) == 1'
This is fixed in the omap4_trigger_io() function, looks like is missed
here.

>



From haojian.zhuang at gmail.com  Tue Mar  6 01:04:46 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 6 Mar 2012 14:04:46 +0800
Subject: [PATCH 0/2] Remove bq24022 driver superseeded by gpio-regulator
In-Reply-To: <201203021355.21669.heiko@sntech.de>
References: <201203021355.21669.heiko@sntech.de>
Message-ID: <CAN1soZwTR=j6=Xi-WKSTQwkGu+58pePb1syD+2q0UhHUJnfg_Q@mail.gmail.com>

On Fri, Mar 2, 2012 at 8:55 PM, Heiko St?bner <heiko at sntech.de> wrote:
> The bq24022 regulator is simply a more specialised variant of the now
> present gpio-regulator. Therefore it probably shouldn't stay around.
>
> This series converts the two users of bq24022 pxa/hx4700 and
> pxa/magician to use the gpio-regulator instead, and after this removes
> the then unused bq24022 driver.
>
> The series was compile-tested only, but the gpio-regulator itself is
> sucessfully used on my platform for the dcdc3 of a tps650240 (voltage
> regulator with one gpio) and for a bq24075 (current regulator with two
> gpios). So I'm quite sure it should work correctly but would welcome
> testers :-) .
>
> Heiko Stuebner (2):
> ?pxa: magician/hx4700: Convert to gpio-regulator from bq24022
> ?regulator: Remove bq24022 regulator driver
>
> ?arch/arm/configs/magician_defconfig | ? ?2 +-
> ?arch/arm/mach-pxa/hx4700.c ? ? ? ? ?| ? 33 ++++++--
> ?arch/arm/mach-pxa/magician.c ? ? ? ?| ? 33 ++++++--
> ?drivers/regulator/Kconfig ? ? ? ? ? | ? ?8 --
> ?drivers/regulator/Makefile ? ? ? ? ?| ? ?1 -
> ?drivers/regulator/bq24022.c ? ? ? ? | ?162 -----------------------------------
> ?include/linux/regulator/bq24022.h ? | ? 24 -----
> ?7 files changed, 55 insertions(+), 208 deletions(-)
> ?delete mode 100644 drivers/regulator/bq24022.c
> ?delete mode 100644 include/linux/regulator/bq24022.h
>
> --
Hi Mark,

I'm planning to merge this patch into arch-pxa tree since some changes
on hx4700.c and magician.c. Is it ok fot you?

Best Regards
Haojian


From haojian.zhuang at gmail.com  Tue Mar  6 01:08:12 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 6 Mar 2012 14:08:12 +0800
Subject: [GIT PULL][v3.4] pull request on arch-pxa for regulator branch
Message-ID: <CAN1soZxJO8sGZwq5LhuEOxt3uEN=s1cAOSXfbR8L5r8Hpc+t-w@mail.gmail.com>

Hi Arnd,

Please help to pull these from arch-pxa tree.

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

  Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:
  git://github.com/hzhuang1/linux.git regulator

Heiko St?bner (2):
      pxa: magician/hx4700: Convert to gpio-regulator from bq24022
      regulator: Remove bq24022 regulator driver

 arch/arm/configs/magician_defconfig |    2 +-
 arch/arm/mach-pxa/hx4700.c          |   33 ++++++--
 arch/arm/mach-pxa/magician.c        |   33 ++++++--
 drivers/regulator/Kconfig           |    8 --
 drivers/regulator/Makefile          |    1 -
 drivers/regulator/bq24022.c         |  162 -----------------------------------
 include/linux/regulator/bq24022.h   |   24 -----
 7 files changed, 55 insertions(+), 208 deletions(-)
 delete mode 100644 drivers/regulator/bq24022.c
 delete mode 100644 include/linux/regulator/bq24022.h


From haojian.zhuang at gmail.com  Tue Mar  6 01:10:57 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 6 Mar 2012 14:10:57 +0800
Subject: [GIT revert][v3.4] revert 43de6a7dd in pxa/board branch
Message-ID: <CAN1soZzOSXbWMcJLGPyTqz1+BHHP9V=TjkM9z5+Vu75+BfwwqA@mail.gmail.com>

Hi Arnd,

Could you help to revert this commit in your pxa/board branch? I
attach the log information in below. Without this patch, gpio function
can't work in PXA25x/PXA27x. So I need to move them into fixes branch.

Best Regards
Haojian

commit 43de6a7dda6e9a7345e218e688f2092f991126f0
Author: Haojian Zhuang <haojian.zhuang at marvell.com>
Date:   Tue Feb 28 10:57:48 2012 +0800

    ARM: pxa: add dummy clock for pxa25x and pxa27x

    gpio-pxa driver is shared among arch-pxa and arch-mmp. Clock is the
    essential component on pxa3xx/pxa95x and arch-mmp. So we need to
    define dummy clock in pxa25x/pxa27x instead.

    Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>


From nm at ti.com  Tue Mar  6 01:12:35 2012
From: nm at ti.com (Nishanth Menon)
Date: Tue, 6 Mar 2012 00:12:35 -0600
Subject: [PATCH] ARM: OMAP2+: voltage: ensure voltage used is exact
 voltage from OPP table
In-Reply-To: <877gyyor28.fsf@ti.com>
References: <1330728121-26664-1-git-send-email-khilman@ti.com>
 <1330940487.2116.119.camel@sokoban> <877gyyor28.fsf@ti.com>
Message-ID: <20120306061233.GC5670@kobold>

On 10:12-20120305, Kevin Hilman wrote:
> Tero Kristo <t-kristo at ti.com> writes:
> 
> > On Fri, 2012-03-02 at 14:42 -0800, Kevin Hilman wrote:
> >> When using the SMPS regulators to scale voltages, the regulator
> >> framework may pass a minimum voltage that is not an exact OPP voltage.
> >> For the VC/VP controlled voltage domains, we must ensure that the
> >> voltage requested is the exact voltage from the OPP table.  This is
> >> especially critical when using SR.
> >> 
> >> To fix, voltdm_scale() uses the target voltage passed to walk through
> >> the OPP voltages until it finds a voltage that is >= one of the OPP
> >> voltages.
> >
> > I have just one question to this, how about smartreflex class1p5? Do we
> > have any plans for that one? The old implementation at least was using
> > voltdm_scale, so if we modify this function, smartreflex class1p5
> > doesn't work anymore.
> 
> Since it's not in mainline, that is not my concern at the moment.  We
> can worry about SR1.5 when I someone is motivated to push it upstream.
> 
> > Otherwise this patch looks good to me.

Other than the minor misgiving of having to re-verify the voltage on
every scale, I am OK with it as well.

That said, I don't see why this should break class 1.5/3.5 support.

-- 
Regards,
Nishanth Menon


From shawn.guo at linaro.org  Tue Mar  6 01:27:45 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 6 Mar 2012 14:27:45 +0800
Subject: [PATCH v2 11/17] ASoC: fsl: create fsl_utils to accommodate the
 common functions
In-Reply-To: <20120305144920.GR3224@opensource.wolfsonmicro.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-12-git-send-email-shawn.guo@linaro.org>
 <20120305144920.GR3224@opensource.wolfsonmicro.com>
Message-ID: <20120306062742.GO16232@S2101-09.ap.freescale.net>

On Mon, Mar 05, 2012 at 02:49:20PM +0000, Mark Brown wrote:
> On Mon, Mar 05, 2012 at 10:30:59PM +0800, Shawn Guo wrote:
> 
> > +/**
> > + * fsl_asoc_get_codec_dev_name - determine the dev_name for a codec node
> > + *
> > + * @np: pointer to the I2C device tree node
> > + * @buf: buffer to be filled with the dev_name of the I2C device
> > + * @len: the length of the buffer
> > + *
> > + * This function determines the dev_name for an I2C node.  This is the name
> > + * that would be returned by dev_name() if this device_node were part of a
> > + * 'struct device'  It's ugly and hackish, but it works.
> > + *
> > + * The dev_name for such devices include the bus number and I2C address. For
> > + * example, "cs4270.0-004f".
> > + */
> > +int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len)
> 
> This doesn't seem at all Freescale specific, it should be a generic
> helper, and in fact there already is one - the machine driver can set
> codec_of_node in the card structure to point to the device node and then
> the core should figure out binding to the device for you.  If it doesn't
> we should fix the core.

Yeah, the core support works, so will remove the function here and use
the core support.

-- 
Regards,
Shawn


From sfr at canb.auug.org.au  Tue Mar  6 01:21:30 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Tue, 6 Mar 2012 17:21:30 +1100
Subject: linux-next: manual merge of the arm-soc tree with the sound-asoc tree
Message-ID: <20120306172130.f5b7aae24600cbbbaf7e84e9@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-imx/mm-imx3.c between commit 3bc34a614335 ("ARM: imx:
convert audmux to a platform driver") from the sound-asoc tree and commit
bb07d7511e08 ("ARM: mx3: Setup AIPS registers") from the arm-soc tree.

Just context changes.  I fixed it up (see below) and can carry the fix as
necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-imx/mm-imx3.c
index 9c9b7f9,17963e0..0000000
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@@ -177,8 -175,9 +179,12 @@@ void __init imx31_soc_init(void
  	}
  
  	imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
+ 
+ 	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
+ 	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
++
 +	platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
 +					ARRAY_SIZE(imx31_audmux_res));
  }
  #endif /* ifdef CONFIG_SOC_IMX31 */
  
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From sfr at canb.auug.org.au  Tue Mar  6 01:24:45 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Tue, 6 Mar 2012 17:24:45 +1100
Subject: linux-next: manual merge of the arm-soc tree with the sound-asoc tree
Message-ID: <20120306172445.81a8461cb8e3b764ce148932@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/plat-mxc/audmux-v1.c between commit 2405fc9728a3 ("ARM: imx:
merge audmux-v1 and audmux-v2") from the sound-asoc tree and commit
48d795616c73 ("ARM: plat-mxc: audmux-v1: Remove unneeded ifdef's") from
the arm-soc tree.

The former removed this file, so I did that.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From andrew at lunn.ch  Tue Mar  6 01:30:56 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue,  6 Mar 2012 07:30:56 +0100
Subject: [RFC 00/14] Generic clk for Orion platforms.
Message-ID: <1331015471-28872-1-git-send-email-andrew@lunn.ch>

This patch set starts the process of changing Orion based platforms to
use the generic clk framework. The first patch fixes compile problems
with the framework, and is expected to be dropped once fixed upstream.
Then clks are added. This is a fixed rate clk for tclk and for
kirkwood, most of the gated clocks also get a clk. The following
patches then modified the drivers to make use of these clocks,
getting, prepareing, enabling at probe time, and disableing,
unprepareing, and putting at remove time. Rather than pass the clock
frequency as platform_data, the driver now uses clk_get_rate(). This
results in some platform_data structures becoming redundant, and so
are removed.

TODO:

 0) Cleanup the white space changes, and hunks in the wrong patches.
 1) PCIe needs adopting to use clks.
 2) Strip out all references to kirkwood_clk_ctrl
 3) Find a solution for turning off unused clks - Probably needs
    framework support, which Mike has already suggested.
 4) Find a solution for tuning off unused SATA and PCIe PHYs. Maybe
    use the unprepare() method, but the current basic clk providers 
    don't support this.

If we are willing to accept a regression in power usage, we could skip
3) and 4) for the moment in order to get this code into use. That
would help the device tree work which benefits from not having to deal
with clock frequencies when setting up device driver bindings.

Boot tested on kirkwood. No testing what so ever on other Orion
platforms.

Based on 

git://git.linaro.org/people/mturquette/linux.git v3.3-rc5-clkv5


Andrew Lunn (14):
  [clk] Fix compile errors in DEFINE_CLK_GATE()
  ARM: Orion: Add clocks using the generic clk infrastructure.
  Arm: Orion: spi: Add clk/clkdev support.
  orion: spi: remove enable_clock_fix which is not used
  Arm: Orion: eth: Add clk/clkdev support.
  ARM: Orion: wdt: Add clk/clkdev support
  ARM: Orion: uart: Get the clock rate via clk_get_rate().
  ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data.
  MV SATA: Add per channel clk/clkdev support.
  [Orion ehci] Add support for enabling clocks
  [Orion nand] Add support for clk, if there is one.
  [Orion sdio] Add support for clk.
  [Orion crypto] Add support for clk
  [Orion xor] Add support for clk

 arch/arm/Kconfig                                  |    3 +
 arch/arm/mach-dove/common.c                       |   37 ++++---
 arch/arm/mach-dove/dove-db-setup.c                |    1 -
 arch/arm/mach-kirkwood/common.c                   |  119 +++++++++++++++++----
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |   16 +++
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c    |    1 -
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c      |    1 -
 arch/arm/mach-kirkwood/t5325-setup.c              |    1 -
 arch/arm/mach-kirkwood/tsx1x-common.c             |    1 -
 arch/arm/mach-mv78xx0/common.c                    |   44 +++++---
 arch/arm/mach-orion5x/common.c                    |   26 ++++-
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c      |    1 -
 arch/arm/plat-orion/common.c                      |   88 ++++++++-------
 arch/arm/plat-orion/include/plat/audio.h          |    1 -
 arch/arm/plat-orion/include/plat/common.h         |   26 +++--
 arch/arm/plat-orion/include/plat/orion_wdt.h      |   18 ---
 drivers/ata/sata_mv.c                             |   43 +++++++-
 drivers/clk/clk.c                                 |    1 +
 drivers/crypto/mv_cesa.c                          |   15 +++
 drivers/dma/mv_xor.c                              |   16 +++
 drivers/dma/mv_xor.h                              |    1 +
 drivers/mmc/host/mvsdio.c                         |   14 +++
 drivers/mtd/nand/orion_nand.c                     |   18 +++
 drivers/net/ethernet/marvell/mv643xx_eth.c        |   46 ++++++--
 drivers/spi/spi-orion.c                           |   37 +++++--
 drivers/usb/host/ehci-orion.c                     |   16 +++
 drivers/watchdog/orion_wdt.c                      |   18 ++-
 include/linux/clk-private.h                       |    4 +-
 include/linux/mv643xx_eth.h                       |    1 -
 include/linux/spi/orion_spi.h                     |   18 ---
 30 files changed, 443 insertions(+), 189 deletions(-)
 delete mode 100644 arch/arm/plat-orion/include/plat/orion_wdt.h
 delete mode 100644 include/linux/spi/orion_spi.h

-- 
1.7.9.1



From linus.walleij at linaro.org  Tue Mar  6 01:32:00 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 6 Mar 2012 07:32:00 +0100
Subject: [GIT PULL] ux500 fixes for v3.4, take 3
In-Reply-To: <1330626847-3266-1-git-send-email-linus.walleij@linaro.org>
References: <1330626847-3266-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <CACRpkdYjuYEm2w6352TShfLO+yXveEWtPhVV2Wx_vF4az1GELg@mail.gmail.com>

On Thu, Mar 1, 2012 at 7:34 PM, Linus Walleij <linus.walleij at linaro.org> wrote:

> here is an updated pull request for the 3.4 merge window,

Ping on this...

Thanks,
Linus Walleij


From jh80.chung at samsung.com  Tue Mar  6 01:40:07 2012
From: jh80.chung at samsung.com (Jaehoon Chung)
Date: Tue, 06 Mar 2012 15:40:07 +0900
Subject: [PATCH 2/2] mmc: sdhci-s3c: Enable runtime power management
In-Reply-To: <20120305115209.GA3224@opensource.wolfsonmicro.com>
References: <4F51697C.40408@samsung.com>
 <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1330735602-22409-2-git-send-email-broonie@opensource.wolfsonmicro.com>
 <4F549A0A.5020402@samsung.com>
 <20120305115209.GA3224@opensource.wolfsonmicro.com>
Message-ID: <4F55B147.6010304@samsung.com>

Acked-by: Jaehoon Chung <jh80.chung at samsung.com>
 
On 03/05/2012 08:52 PM, Mark Brown wrote:

> On Mon, Mar 05, 2012 at 07:48:42PM +0900, Jaehoon Chung wrote:
>> On 03/03/2012 09:46 AM, Mark Brown wrote:
> 
>>> +	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
> 
>> Could you explain why use 50ms? 
> 
> It's essentially a random number, some other devices use the same one.
> We're just trying to avoid suspending between back to back requests.
> 
>>> +	pm_runtime_use_autosuspend(&pdev->dev);
>>> +	pm_suspend_ignore_children(&pdev->dev, 1);
> 
>> Is there reason that ignore_children use to set the true?
> 
> So that we can suspend the host without having to have the MMC card
> suspended (the host suspend is not visible to the card).
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel




From haojian.zhuang at gmail.com  Tue Mar  6 02:01:58 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 6 Mar 2012 15:01:58 +0800
Subject: [GIT PULL][v3.3] pull request on arch-pxa tree with fix branch
Message-ID: <CAN1soZzkb9qWmBRsv_wEwHwiRUW+q7zaehxnMifgEhsoXV4BZA@mail.gmail.com>

Hi Arnd,

Please help to pull these patch in fixes branch of arch-pxa tree.

Best Regards
Haojian

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

  Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:
  git://github.com/hzhuang1/linux.git fixes

Haojian Zhuang (3):
      ARM: pxa: add dummy clock for pxa25x and pxa27x
      ARM: pxa: remove duplicated registeration on pxa-gpio
      ARM: pxa: fix invalid mfp pin issue

 arch/arm/mach-pxa/generic.h    |    1 -
 arch/arm/mach-pxa/mfp-pxa2xx.c |    7 +++++++
 arch/arm/mach-pxa/pxa25x.c     |    2 +-
 arch/arm/mach-pxa/pxa27x.c     |    2 +-
 arch/arm/mach-pxa/pxa3xx.c     |    1 -
 arch/arm/mach-pxa/pxa95x.c     |    1 -
 6 files changed, 9 insertions(+), 5 deletions(-)
You have new mail in /var/spool/mail/hzhuang1


From haojian.zhuang at gmail.com  Tue Mar  6 02:06:57 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 6 Mar 2012 15:06:57 +0800
Subject: [GIT PULL][for v3.4]pull request from arch-pxa tree with rtc branch
Message-ID: <CAN1soZxSpnDJCiz-5_PiHcb+zoR+X0b2VLyANLY0om0MDo+YYg@mail.gmail.com>

Hi Arnd,

Please help to pull this patch from arch-pxa git with rtc branch. I
have to put it into rtc branch since I met patch conflict on v3.3-rc6.
It seems that putting it into rtc branch with previous rtc patches is
a better choice.

Best Regards
Haojian

The following changes since commit 4128e27584f58bce9f56a9a0346650c94a651332:

  ARM: mmp: enable rtc in pxa910 (2012-02-28 11:23:09 +0800)

are available in the git repository at:
  git://github.com/hzhuang1/linux.git rtc

Haojian Zhuang (1):
      rtc: sa1100: add OF support

 drivers/rtc/rtc-sa1100.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)


From shawn.guo at linaro.org  Tue Mar  6 02:39:02 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 6 Mar 2012 15:39:02 +0800
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120305144601.GQ3224@opensource.wolfsonmicro.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
 <20120305144601.GQ3224@opensource.wolfsonmicro.com>
Message-ID: <20120306073900.GP16232@S2101-09.ap.freescale.net>

On Mon, Mar 05, 2012 at 02:46:01PM +0000, Mark Brown wrote:
> On Mon, Mar 05, 2012 at 10:31:05PM +0800, Shawn Guo wrote:
> 
> > +	ret = snd_soc_dai_set_fmt(rtd->codec_dai, SND_SOC_DAIFMT_I2S |
> > +						  SND_SOC_DAIFMT_NB_NF |
> > +						  SND_SOC_DAIFMT_CBM_CFM);
> > +	if (ret) {
> > +		dev_err(dev, "could not set codec driver audio format\n");
> > +		return ret;
> > +	}
> 
> This you can just set in the card struct, no need for explicit code at
> all.
> 
Yes, I just tried.  It also works but a little bit differently.  We
only set_fmt for codec_dai here, while ASoC core will set_fmt for both
codec_dai and cpu_dai if dai_link->dai_fmt is set.  However, the
fsl_ssi does not provide .set_fmt implementation, and consequently we
will see error message below, which does not impact functionality
though.

  fsl-ssi-dai 83fcc000.ssi: Failed to set DAI format: -22

I hope we keep the code as it is now and improve later when fsl_ssi
gets improved.

> > +	ret = of_property_read_u32(np, "fsl,mux-int-port", &int_port);
> > +	if (ret) {
> > +		dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
> > +		return -EINVAL;
> > +	}
> > +	ret = of_property_read_u32(np, "fsl,mux-ext-port", &ext_port);
> > +	if (ret) {
> > +		dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
> > +		return -EINVAL;
> > +	}
> 
> It seems very odd to have namespacing on the individual property names.
> Why are you doing that?  The properties are already defined in terms of
> the device binding.  Though everyone else is doing it so not really a
> problem.
> 
The general device tree binding practice is we'd better have a vendor
prefix on the property name, if the property applies on specific vendor
drivers instead of common ones across different vendors.

> > +	/*
> > +	 * The port numbering in the hardware manual starts at 1, while
> > +	 * the audmux API expects it starts at 0.
> > +	 */
> > +	int_port--;
> > +	ext_port--;
> 
> Should have error checking somewhere to make sure that the user
> remembered this.
> 
Because different i.MX SoC may have different internal and external
port number, I do not think of a way to check that.  And I would not
worry about it that much, since all the hardware documents number the
port from 1, while device tree user/author will have to look at those
documents for the data.

> > +	imx_audmux_v2_configure_port(int_port,
> > +			IMX_AUDMUX_V2_PTCR_SYN |
> > +			IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
> > +			IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
> > +			IMX_AUDMUX_V2_PTCR_TFSDIR |
> > +			IMX_AUDMUX_V2_PTCR_TCLKDIR,
> > +			IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
> 
> I'm not sure we've really gained much from converting to a platform
> driver given that the device just registers something globally...

Converting audmux to a platform driver does not change anything about
that.  It makes device tree support easier, and gets the audmux users
(imx machine drivers) stay away from including <mach/audmux.h>.

-- 
Regards,
Shawn


From pullip.cho at samsung.com  Tue Mar  6 03:31:24 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Tue, 06 Mar 2012 17:31:24 +0900
Subject: [PATCH v10 0/3] iommu/exynos: Add IOMMU/System MMU driver for Samsung
 Exynos
Message-ID: <001f01ccfb73$84a2bbd0$8de83370$%cho@samsung.com>

These patches are successfully compiled
in linux-samsung.git/for-next branch
You can find  the git repo. In
http://git.kernel.org/?p=linux/kernel/git/kgene/linux-samsung.git;a=summary

Changes since v9:
- Split the first patch into 2 patches.
   One removes System MMU driver from arch/arm/plat- tree and
   the other modifies and adds platform device definitions in
   arch/arm/mach tree
- Some bug fixes
- Change "gsc" for Exynos4 to "fimc"

Changes since v8:
- exynos_iommu_map/unmap() just works for the page sizes
   that System MMU supports. (Joerg's comment)
- 1 platform device for 1 H/W though a multimedia accelerator
   with several System MMUs attached.
   This make controlling System MMU simpler.
- Information between System MMU and the accelerators:
   Shifted to accelerator's device structure from System MMU's

Changes since v7:
- Rebased with the recent commits of the following git branches
  * git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git/next
  * git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git/for-next
- Changed magic numbers into macros
- Setting owner of a System MMU in 'iommu' field of dev_archdata
- Verbose message in the default fault handler
- Some bug fixes.

Changes since v6:
- Totally rewrite exynos_iommu_map() and exynos_iommu_unmap() according
  to the change in iommu_map() and iommu_unmap().
- Change special slab for Lv2 page table to kmalloc().

Changes since v5:
- Relation between device and a domain become n:1 (Joerg's comment)
- Implements iommu_commit(). --> Removed

Changes since v4:
- exynos_iommu_unmap()returns unmapped size in page order
  (Ohad Ben-Cohen's comment)
- Fixed typo error of resource names
- Fixed missing #include<mach/sysmmu.h>
  in arch/arm/mach-exynos4/mach-armlex4210.c

Changes since v3:
- Used DEFINE_RES_MEM and DEFINE_RES_IRQ macros
  to define resources of System MMU (Russell King's comment)
- Fixed removal of CONFIG_S5P_SLEEP definition
 (Sylwester Nawrocki's comment)

Changes since v2:
- Add lock for System MMU private data.
  And fixes the following problems pointed by Joerg Rodel:
- Fix wrong argument to kmalloc() and get_free_pages()
- Merged patches into 2 due to bisectability

Changes since v1:
Fixes of the following problems pointed by Russell King.:
 - Missing unlocking a spinlock in exynos_iommu_attach_dev().
 - atomic_t -> int in sysmmu_drvdata.activations
 - sysmmu_platdata -> sysmmu_drvdata
 - Change in error messages in irq handler
 - Removed casting in format of error message
 - omap_iommu_ops -> exynos_iommu_ops in the last patch

Patch Summary:
[PATCH v10 1/3] S5P: SYSMMU: Remove System MMU device driver definitions
[PATCH v10 2/3] ARM: EXYNOS: Change System MMU platform device definitions
[PATCH v10 3/3] iommu/exynos: Add iommu driver for Exynos Platforms

The first patch removes the existing System MMU device driver
which does not conform to IOMMU API set prepared in the kernel.
 
The second patch enhances System MMU platform device definition:
 - Removed System MMU for MDMA0 in TOP block because it is not
   used. Use MDMA2 in LCD block.
 - Removed System MMU ID. Instead, a System MMU is bound to a device
   that the System MMU is dedicated during machin initialization.
   If a device driver wants to handle System MMU, it must bind its
   device with System MMU with sysmmu_set_owner().
 - clkdev
 - Added support for Exynos5

The last patch implements IOMMU API:
- New System MMU device driver that fully implements IOMMU API.

Thanks to Kyungmin Park and Marek Szyprowski for kind review.

Diffstats:
 arch/arm/mach-exynos/Kconfig                    |   11 +-
 arch/arm/mach-exynos/Makefile                   |    2 +-
 arch/arm/mach-exynos/clock-exynos4.c            |   87 +-
 arch/arm/mach-exynos/clock-exynos4.h            |    2 +
 arch/arm/mach-exynos/clock-exynos4210.c         |   11 +
 arch/arm/mach-exynos/clock-exynos4212.c         |   28 +-
 arch/arm/mach-exynos/clock-exynos5.c            |   90 ++
 arch/arm/mach-exynos/dev-sysmmu.c               |  457 ++++++-----
 arch/arm/mach-exynos/include/mach/irqs.h        |  179 ++--
 arch/arm/mach-exynos/include/mach/map.h         |   38 +
 arch/arm/mach-exynos/include/mach/regs-clock.h  |    5 +
 arch/arm/mach-exynos/include/mach/regs-sysmmu.h |   28 -
 arch/arm/mach-exynos/include/mach/sysmmu.h      |   84 +-
 arch/arm/mach-exynos/mach-armlex4210.c          |    1 -
 arch/arm/mach-exynos/mach-smdkv310.c            |    1 -
 arch/arm/plat-s5p/Kconfig                       |    8 -
 arch/arm/plat-s5p/Makefile                      |    1 -
 arch/arm/plat-s5p/sysmmu.c                      |  313 -------
 arch/arm/plat-samsung/include/plat/devs.h       |    1 -
 arch/arm/plat-samsung/include/plat/sysmmu.h     |   95 --
 drivers/iommu/Kconfig                           |   21 +
 drivers/iommu/Makefile                          |    1 +
 drivers/iommu/exynos-iommu.c                    | 1088 +++++++++++++++++++++++
 23 files changed, 1726 insertions(+), 826 deletions(-)



From pullip.cho at samsung.com  Tue Mar  6 03:31:27 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Tue, 06 Mar 2012 17:31:27 +0900
Subject: [PATCH v10 1/3] S5P: SYSMMU: Remove System MMU device driver
Message-ID: <002001ccfb73$85dee550$919caff0$%cho@samsung.com>

This patch removes System MMU device driver from arm/plat-s5p tree
for transition to implement IOMMU driver.
Although controlling System MMU in this removing driver
is similar to the new IOMMU driver in the following patch,
the new one is almost rewrite of this driver and there is no
benefit to moving the driver file from arch/arm/ to drivers/iommu.

Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
---
 arch/arm/plat-s5p/Kconfig                   |    8 -
 arch/arm/plat-s5p/Makefile                  |    1 -
 arch/arm/plat-s5p/sysmmu.c                  |  313 ---------------------------
 arch/arm/plat-samsung/include/plat/devs.h   |    1 -
 arch/arm/plat-samsung/include/plat/sysmmu.h |   95 --------
 5 files changed, 0 insertions(+), 418 deletions(-)
 delete mode 100644 arch/arm/plat-s5p/sysmmu.c
 delete mode 100644 arch/arm/plat-samsung/include/plat/sysmmu.h

diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 8490695..9451ed4 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -50,14 +50,6 @@ config S5P_PM
 	  Common code for power management support on S5P and newer SoCs
 	  Note: Do not select this for S5P6440 and S5P6450.
 
-comment "System MMU"
-
-config S5P_SYSTEM_MMU
-	bool "S5P SYSTEM MMU"
-	depends on ARCH_EXYNOS4
-	help
-	  Say Y here if you want to enable System MMU
-
 config S5P_SLEEP
 	bool
 	help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 4bd8241..4953d50 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -16,7 +16,6 @@ obj-y				+= clock.o
 obj-y				+= irq.o
 obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
 obj-$(CONFIG_S5P_GPIO_INT)	+= irq-gpioint.o
-obj-$(CONFIG_S5P_SYSTEM_MMU)	+= sysmmu.o
 obj-$(CONFIG_S5P_PM)		+= pm.o irq-pm.o
 obj-$(CONFIG_S5P_SLEEP)		+= sleep.o
 obj-$(CONFIG_S5P_HRT) 		+= s5p-time.o
diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c
deleted file mode 100644
index c8bec9c..0000000
--- a/arch/arm/plat-s5p/sysmmu.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/* linux/arch/arm/plat-s5p/sysmmu.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/export.h>
-
-#include <asm/pgtable.h>
-
-#include <mach/map.h>
-#include <mach/regs-sysmmu.h>
-#include <plat/sysmmu.h>
-
-#define CTRL_ENABLE	0x5
-#define CTRL_BLOCK	0x7
-#define CTRL_DISABLE	0x0
-
-static struct device *dev;
-
-static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
-	S5P_PAGE_FAULT_ADDR,
-	S5P_AR_FAULT_ADDR,
-	S5P_AW_FAULT_ADDR,
-	S5P_DEFAULT_SLAVE_ADDR,
-	S5P_AR_FAULT_ADDR,
-	S5P_AR_FAULT_ADDR,
-	S5P_AW_FAULT_ADDR,
-	S5P_AW_FAULT_ADDR
-};
-
-static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
-	"PAGE FAULT",
-	"AR MULTI-HIT FAULT",
-	"AW MULTI-HIT FAULT",
-	"BUS ERROR",
-	"AR SECURITY PROTECTION FAULT",
-	"AR ACCESS PROTECTION FAULT",
-	"AW SECURITY PROTECTION FAULT",
-	"AW ACCESS PROTECTION FAULT"
-};
-
-static int (*fault_handlers[S5P_SYSMMU_TOTAL_IPNUM])(
-		enum S5P_SYSMMU_INTERRUPT_TYPE itype,
-		unsigned long pgtable_base,
-		unsigned long fault_addr);
-
-/*
- * If adjacent 2 bits are true, the system MMU is enabled.
- * The system MMU is disabled, otherwise.
- */
-static unsigned long sysmmu_states;
-
-static inline void set_sysmmu_active(sysmmu_ips ips)
-{
-	sysmmu_states |= 3 << (ips * 2);
-}
-
-static inline void set_sysmmu_inactive(sysmmu_ips ips)
-{
-	sysmmu_states &= ~(3 << (ips * 2));
-}
-
-static inline int is_sysmmu_active(sysmmu_ips ips)
-{
-	return sysmmu_states & (3 << (ips * 2));
-}
-
-static void __iomem *sysmmusfrs[S5P_SYSMMU_TOTAL_IPNUM];
-
-static inline void sysmmu_block(sysmmu_ips ips)
-{
-	__raw_writel(CTRL_BLOCK, sysmmusfrs[ips] + S5P_MMU_CTRL);
-	dev_dbg(dev, "%s is blocked.\n", sysmmu_ips_name[ips]);
-}
-
-static inline void sysmmu_unblock(sysmmu_ips ips)
-{
-	__raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
-	dev_dbg(dev, "%s is unblocked.\n", sysmmu_ips_name[ips]);
-}
-
-static inline void __sysmmu_tlb_invalidate(sysmmu_ips ips)
-{
-	__raw_writel(0x1, sysmmusfrs[ips] + S5P_MMU_FLUSH);
-	dev_dbg(dev, "TLB of %s is invalidated.\n", sysmmu_ips_name[ips]);
-}
-
-static inline void __sysmmu_set_ptbase(sysmmu_ips ips, unsigned long pgd)
-{
-	if (unlikely(pgd == 0)) {
-		pgd = (unsigned long)ZERO_PAGE(0);
-		__raw_writel(0x20, sysmmusfrs[ips] + S5P_MMU_CFG); /* 4KB LV1 */
-	} else {
-		__raw_writel(0x0, sysmmusfrs[ips] + S5P_MMU_CFG); /* 16KB LV1 */
-	}
-
-	__raw_writel(pgd, sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
-
-	dev_dbg(dev, "Page table base of %s is initialized with 0x%08lX.\n",
-						sysmmu_ips_name[ips], pgd);
-	__sysmmu_tlb_invalidate(ips);
-}
-
-void sysmmu_set_fault_handler(sysmmu_ips ips,
-			int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
-					unsigned long pgtable_base,
-					unsigned long fault_addr))
-{
-	BUG_ON(!((ips >= SYSMMU_MDMA) && (ips < S5P_SYSMMU_TOTAL_IPNUM)));
-	fault_handlers[ips] = handler;
-}
-
-static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id)
-{
-	/* SYSMMU is in blocked when interrupt occurred. */
-	unsigned long base = 0;
-	sysmmu_ips ips = (sysmmu_ips)dev_id;
-	enum S5P_SYSMMU_INTERRUPT_TYPE itype;
-
-	itype = (enum S5P_SYSMMU_INTERRUPT_TYPE)
-		__ffs(__raw_readl(sysmmusfrs[ips] + S5P_INT_STATUS));
-
-	BUG_ON(!((itype >= 0) && (itype < 8)));
-
-	dev_alert(dev, "%s occurred by %s.\n", sysmmu_fault_name[itype],
-							sysmmu_ips_name[ips]);
-
-	if (fault_handlers[ips]) {
-		unsigned long addr;
-
-		base = __raw_readl(sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
-		addr = __raw_readl(sysmmusfrs[ips] + fault_reg_offset[itype]);
-
-		if (fault_handlers[ips](itype, base, addr)) {
-			__raw_writel(1 << itype,
-					sysmmusfrs[ips] + S5P_INT_CLEAR);
-			dev_notice(dev, "%s from %s is resolved."
-					" Retrying translation.\n",
-				sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
-		} else {
-			base = 0;
-		}
-	}
-
-	sysmmu_unblock(ips);
-
-	if (!base)
-		dev_notice(dev, "%s from %s is not handled.\n",
-			sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
-
-	return IRQ_HANDLED;
-}
-
-void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd)
-{
-	if (is_sysmmu_active(ips)) {
-		sysmmu_block(ips);
-		__sysmmu_set_ptbase(ips, pgd);
-		sysmmu_unblock(ips);
-	} else {
-		dev_dbg(dev, "%s is disabled. "
-			"Skipping initializing page table base.\n",
-						sysmmu_ips_name[ips]);
-	}
-}
-
-void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd)
-{
-	if (!is_sysmmu_active(ips)) {
-		sysmmu_clk_enable(ips);
-
-		__sysmmu_set_ptbase(ips, pgd);
-
-		__raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
-
-		set_sysmmu_active(ips);
-		dev_dbg(dev, "%s is enabled.\n", sysmmu_ips_name[ips]);
-	} else {
-		dev_dbg(dev, "%s is already enabled.\n", sysmmu_ips_name[ips]);
-	}
-}
-
-void s5p_sysmmu_disable(sysmmu_ips ips)
-{
-	if (is_sysmmu_active(ips)) {
-		__raw_writel(CTRL_DISABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
-		set_sysmmu_inactive(ips);
-		sysmmu_clk_disable(ips);
-		dev_dbg(dev, "%s is disabled.\n", sysmmu_ips_name[ips]);
-	} else {
-		dev_dbg(dev, "%s is already disabled.\n", sysmmu_ips_name[ips]);
-	}
-}
-
-void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips)
-{
-	if (is_sysmmu_active(ips)) {
-		sysmmu_block(ips);
-		__sysmmu_tlb_invalidate(ips);
-		sysmmu_unblock(ips);
-	} else {
-		dev_dbg(dev, "%s is disabled. "
-			"Skipping invalidating TLB.\n", sysmmu_ips_name[ips]);
-	}
-}
-
-static int s5p_sysmmu_probe(struct platform_device *pdev)
-{
-	int i, ret;
-	struct resource *res, *mem;
-
-	dev = &pdev->dev;
-
-	for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
-		int irq;
-
-		sysmmu_clk_init(dev, i);
-		sysmmu_clk_disable(i);
-
-		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-		if (!res) {
-			dev_err(dev, "Failed to get the resource of %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENODEV;
-			goto err_res;
-		}
-
-		mem = request_mem_region(res->start, resource_size(res),
-					 pdev->name);
-		if (!mem) {
-			dev_err(dev, "Failed to request the memory region of %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -EBUSY;
-			goto err_res;
-		}
-
-		sysmmusfrs[i] = ioremap(res->start, resource_size(res));
-		if (!sysmmusfrs[i]) {
-			dev_err(dev, "Failed to ioremap() for %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENXIO;
-			goto err_reg;
-		}
-
-		irq = platform_get_irq(pdev, i);
-		if (irq <= 0) {
-			dev_err(dev, "Failed to get the IRQ resource of %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENOENT;
-			goto err_map;
-		}
-
-		if (request_irq(irq, s5p_sysmmu_irq, IRQF_DISABLED,
-						pdev->name, (void *)i)) {
-			dev_err(dev, "Failed to request IRQ for %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENOENT;
-			goto err_map;
-		}
-	}
-
-	return 0;
-
-err_map:
-	iounmap(sysmmusfrs[i]);
-err_reg:
-	release_mem_region(mem->start, resource_size(mem));
-err_res:
-	return ret;
-}
-
-static int s5p_sysmmu_remove(struct platform_device *pdev)
-{
-	return 0;
-}
-int s5p_sysmmu_runtime_suspend(struct device *dev)
-{
-	return 0;
-}
-
-int s5p_sysmmu_runtime_resume(struct device *dev)
-{
-	return 0;
-}
-
-const struct dev_pm_ops s5p_sysmmu_pm_ops = {
-	.runtime_suspend	= s5p_sysmmu_runtime_suspend,
-	.runtime_resume		= s5p_sysmmu_runtime_resume,
-};
-
-static struct platform_driver s5p_sysmmu_driver = {
-	.probe		= s5p_sysmmu_probe,
-	.remove		= s5p_sysmmu_remove,
-	.driver		= {
-		.owner		= THIS_MODULE,
-		.name		= "s5p-sysmmu",
-		.pm		= &s5p_sysmmu_pm_ops,
-	}
-};
-
-static int __init s5p_sysmmu_init(void)
-{
-	return platform_driver_register(&s5p_sysmmu_driver);
-}
-arch_initcall(s5p_sysmmu_init);
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 2dd5267..a604cb8 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -132,7 +132,6 @@ extern struct platform_device exynos4_device_pcm1;
 extern struct platform_device exynos4_device_pcm2;
 extern struct platform_device exynos4_device_pd[];
 extern struct platform_device exynos4_device_spdif;
-extern struct platform_device exynos4_device_sysmmu;
 
 extern struct platform_device samsung_asoc_dma;
 extern struct platform_device samsung_asoc_idma;
diff --git a/arch/arm/plat-samsung/include/plat/sysmmu.h b/arch/arm/plat-samsung/include/plat/sysmmu.h
deleted file mode 100644
index 5fe8ee0..0000000
--- a/arch/arm/plat-samsung/include/plat/sysmmu.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * Samsung System MMU driver for S5P platform
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __PLAT_SAMSUNG_SYSMMU_H
-#define __PLAT_SAMSUNG_SYSMMU_H __FILE__
-
-enum S5P_SYSMMU_INTERRUPT_TYPE {
-	SYSMMU_PAGEFAULT,
-	SYSMMU_AR_MULTIHIT,
-	SYSMMU_AW_MULTIHIT,
-	SYSMMU_BUSERROR,
-	SYSMMU_AR_SECURITY,
-	SYSMMU_AR_ACCESS,
-	SYSMMU_AW_SECURITY,
-	SYSMMU_AW_PROTECTION, /* 7 */
-	SYSMMU_FAULTS_NUM
-};
-
-#ifdef CONFIG_S5P_SYSTEM_MMU
-
-#include <mach/sysmmu.h>
-
-/**
- * s5p_sysmmu_enable() - enable system mmu of ip
- * @ips: The ip connected system mmu.
- * #pgd: Base physical address of the 1st level page table
- *
- * This function enable system mmu to transfer address
- * from virtual address to physical address
- */
-void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd);
-
-/**
- * s5p_sysmmu_disable() - disable sysmmu mmu of ip
- * @ips: The ip connected system mmu.
- *
- * This function disable system mmu to transfer address
- * from virtual address to physical address
- */
-void s5p_sysmmu_disable(sysmmu_ips ips);
-
-/**
- * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
- * @ips: The ip connected system mmu.
- * @pgd: The page table base address.
- *
- * This function set page table base address
- * When system mmu transfer address from virtaul address to physical address,
- * system mmu refer address information from page table
- */
-void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
-
-/**
- * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
- * @ips: The ip connected system mmu.
- *
- * This function flush all TLB entry in system mmu
- */
-void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
-
-/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs
- * @itype: type of fault.
- * @pgtable_base: the physical address of page table base. This is 0 if @ips is
- *               SYSMMU_BUSERROR.
- * @fault_addr: the device (virtual) address that the System MMU tried to
- *             translated. This is 0 if @ips is SYSMMU_BUSERROR.
- * Called when interrupt occurred by the System MMUs
- * The device drivers of peripheral devices that has a System MMU can implement
- * a fault handler to resolve address translation fault by System MMU.
- * The meanings of return value and parameters are described below.
-
- * return value: non-zero if the fault is correctly resolved.
- *         zero if the fault is not handled.
- */
-void s5p_sysmmu_set_fault_handler(sysmmu_ips ips,
-			int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
-					unsigned long pgtable_base,
-					unsigned long fault_addr));
-#else
-#define s5p_sysmmu_enable(ips, pgd) do { } while (0)
-#define s5p_sysmmu_disable(ips) do { } while (0)
-#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0)
-#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0)
-#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0)
-#endif
-#endif /* __ASM_PLAT_SYSMMU_H */
-- 
1.7.1




From pullip.cho at samsung.com  Tue Mar  6 03:31:28 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Tue, 06 Mar 2012 17:31:28 +0900
Subject: [PATCH v10 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
Message-ID: <002101ccfb73$8684c240$938e46c0$%cho@samsung.com>

Handling System MMUs with an identifier is not flexible to manage
System MMU platform devices because of the following reasons:
1. A device driver which needs to handle System MMU must know the ID.
2. A System MMU may not present in some implementations of Exynos family.
3. Handling System MMU with IOMMU API does not require an ID.

This patch is the result of removing ID of System MMUs.
Instead, a device driver that needs to handle its System MMU must
use IOMMU API while its descriptor of platform device is given.

This patch also includes the following enhanclements:
- A System MMU device becomes a child if its power domain device.
- clkdev

Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
---
 arch/arm/mach-exynos/Kconfig                    |   11 +-
 arch/arm/mach-exynos/Makefile                   |    2 +-
 arch/arm/mach-exynos/clock-exynos4.c            |   79 ++--
 arch/arm/mach-exynos/clock-exynos4.h            |    2 +
 arch/arm/mach-exynos/clock-exynos4210.c         |   11 +
 arch/arm/mach-exynos/clock-exynos4212.c         |   28 ++-
 arch/arm/mach-exynos/clock-exynos5.c            |   90 +++++
 arch/arm/mach-exynos/dev-sysmmu.c               |  457 ++++++++++++----------
 arch/arm/mach-exynos/include/mach/irqs.h        |  179 +++++-----
 arch/arm/mach-exynos/include/mach/map.h         |   38 ++
 arch/arm/mach-exynos/include/mach/regs-clock.h  |    5 +
 arch/arm/mach-exynos/include/mach/regs-sysmmu.h |   28 --
 arch/arm/mach-exynos/include/mach/sysmmu.h      |   84 +++--
 arch/arm/mach-exynos/mach-armlex4210.c          |    1 -
 arch/arm/mach-exynos/mach-smdkv310.c            |    1 -
 15 files changed, 612 insertions(+), 404 deletions(-)
 delete mode 100644 arch/arm/mach-exynos/include/mach/regs-sysmmu.h

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index c49d450..d5a6a29 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -88,10 +88,10 @@ config EXYNOS4_SETUP_FIMD0
 	help
 	  Common setup code for FIMD0.
 
-config EXYNOS4_DEV_SYSMMU
+config EXYNOS_DEV_SYSMMU
 	bool
 	help
-	  Common setup code for SYSTEM MMU in EXYNOS4
+	  Common setup code for SYSTEM MMU in EXYNOS platforms
 
 config EXYNOS4_DEV_DWMCI
 	bool
@@ -201,12 +201,12 @@ config MACH_SMDKV310
 	select S3C_DEV_HSMMC2
 	select S3C_DEV_HSMMC3
 	select SAMSUNG_DEV_BACKLIGHT
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_DEV_AHCI
 	select SAMSUNG_DEV_KEYPAD
 	select EXYNOS4_DEV_DMA
 	select SAMSUNG_DEV_PWM
 	select EXYNOS4_DEV_USB_OHCI
-	select EXYNOS4_DEV_SYSMMU
 	select EXYNOS4_SETUP_FIMD0
 	select EXYNOS4_SETUP_I2C1
 	select EXYNOS4_SETUP_KEYPAD
@@ -225,7 +225,6 @@ config MACH_ARMLEX4210
 	select S3C_DEV_HSMMC3
 	select EXYNOS4_DEV_AHCI
 	select EXYNOS4_DEV_DMA
-	select EXYNOS4_DEV_SYSMMU
 	select EXYNOS4_SETUP_SDHCI
 	help
 	  Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@@ -251,6 +250,7 @@ config MACH_UNIVERSAL_C210
 	select S5P_DEV_MFC
 	select S5P_DEV_ONENAND
 	select S5P_DEV_TV
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_DEV_DMA
 	select EXYNOS4_SETUP_FIMD0
 	select EXYNOS4_SETUP_I2C1
@@ -320,6 +320,7 @@ config MACH_ORIGEN
 	select S5P_DEV_USB_EHCI
 	select SAMSUNG_DEV_BACKLIGHT
 	select SAMSUNG_DEV_PWM
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_DEV_DMA
 	select EXYNOS4_DEV_USB_OHCI
 	select EXYNOS4_SETUP_FIMD0
@@ -343,6 +344,7 @@ config MACH_SMDK4212
 	select SAMSUNG_DEV_BACKLIGHT
 	select SAMSUNG_DEV_KEYPAD
 	select SAMSUNG_DEV_PWM
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_SETUP_I2C1
 	select EXYNOS4_SETUP_I2C3
 	select EXYNOS4_SETUP_I2C7
@@ -368,6 +370,7 @@ comment "EXYNOS5250 Boards"
 config MACH_SMDK5250
 	bool "SMDK5250"
 	select SOC_EXYNOS5250
+	select EXYNOS_DEV_SYSMMU
 	help
 	  Machine support for Samsung SMDK5250
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 6fd8dd9..8b655e9 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -52,7 +52,7 @@ obj-$(CONFIG_MACH_SMDK5250)		+= mach-smdk5250.o
 obj-y					+= dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
-obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)	+= dev-sysmmu.o
+obj-$(CONFIG_EXYNOS_DEV_SYSMMU)		+= dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
 obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index d72a1fe..18c48f0 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -169,7 +169,7 @@ static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
 }
 
-static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
 }
@@ -199,6 +199,11 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
 }
 
+int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
+}
+
 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
@@ -679,61 +684,55 @@ static struct clk exynos4_init_clocks_off[] = {
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 14),
 	}, {
-		.name		= "SYSMMU_MDMA",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+		.enable		= exynos4_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+		.enable		= exynos4_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(tv, 2),
+		.enable		= exynos4_clk_ip_tv_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(rot, 4),
 		.enable		= exynos4_clk_ip_image_ctrl,
-		.ctrlbit	= (1 << 5),
+		.ctrlbit	= (1 << 4),
 	}, {
-		.name		= "SYSMMU_FIMC0",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc0, 5),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 7),
 	}, {
-		.name		= "SYSMMU_FIMC1",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc1, 6),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 8),
 	}, {
-		.name		= "SYSMMU_FIMC2",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc2, 7),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 9),
 	}, {
-		.name		= "SYSMMU_FIMC3",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc3, 8),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 10),
 	}, {
-		.name		= "SYSMMU_JPEG",
-		.enable		= exynos4_clk_ip_cam_ctrl,
-		.ctrlbit	= (1 << 11),
-	}, {
-		.name		= "SYSMMU_FIMD0",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimd0, 10),
 		.enable		= exynos4_clk_ip_lcd0_ctrl,
 		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_FIMD1",
-		.enable		= exynos4_clk_ip_lcd1_ctrl,
-		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_PCIe",
-		.enable		= exynos4_clk_ip_fsys_ctrl,
-		.ctrlbit	= (1 << 18),
-	}, {
-		.name		= "SYSMMU_G2D",
-		.enable		= exynos4_clk_ip_image_ctrl,
-		.ctrlbit	= (1 << 3),
-	}, {
-		.name		= "SYSMMU_ROTATOR",
-		.enable		= exynos4_clk_ip_image_ctrl,
-		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_TV",
-		.enable		= exynos4_clk_ip_tv_ctrl,
-		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_MFC_L",
-		.enable		= exynos4_clk_ip_mfc_ctrl,
-		.ctrlbit	= (1 << 1),
-	}, {
-		.name		= "SYSMMU_MFC_R",
-		.enable		= exynos4_clk_ip_mfc_ctrl,
-		.ctrlbit	= (1 << 2),
 	}
 };
 
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
index 9d27a56..309cc71 100644
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -28,5 +28,7 @@ extern struct clk *exynos4_clkset_group_list[];
 extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
 
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 68763b3..c1fcd2f 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -28,6 +28,7 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
 
 #include "clock-exynos4.h"
 #include "common.h"
@@ -96,6 +97,16 @@ static struct clk init_clocks_off[] = {
 		.devname	= "exynos4-fb.1",
 		.enable		= exynos4_clk_ip_lcd1_ctrl,
 		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimd1, 11),
+		.enable		= exynos4_clk_ip_lcd1_ctrl,
+		.ctrlbit	= (1 << 4),
 	},
 };
 
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index f22a0a2..e1059a2 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -28,6 +28,7 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
 
 #include "clock-exynos4.h"
 #include "common.h"
@@ -41,6 +42,16 @@ static struct sleep_save exynos4212_clock_save[] = {
 };
 #endif
 
+static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
+}
+
+static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
+}
+
 static struct clk *clk_src_mpll_user_list[] = {
 	[0] = &clk_fin_mpll,
 	[1] = &exynos4_clk_mout_mpll.clk,
@@ -68,7 +79,22 @@ static struct clksrc_clk clksrcs[] = {
 };
 
 static struct clk init_clocks_off[] = {
-	/* nothing here yet */
+	{
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (7 << 8),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME2,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 4),
+	}
 };
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index d013982..3320ad1 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
 }
 
+static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
+}
+
 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
@@ -127,6 +132,21 @@ static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
 }
 
+static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
+}
+
+static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
+}
+
+static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
+}
+
 /* Core list of CMU_CPU side */
 
 static struct clksrc_clk exynos5_clk_mout_apll = {
@@ -630,6 +650,76 @@ static struct clk exynos5_init_clocks_off[] = {
 		.parent		= &exynos5_clk_aclk_66.clk,
 		.enable		= exynos5_clk_ip_peric_ctrl,
 		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+		.enable		= &exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+		.enable		= &exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(tv, 2),
+		.enable		= &exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 9)
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+		.enable		= &exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(rot, 4),
+		.enable		= &exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 6)
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc0, 5),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc1, 6),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc2, 7),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc3, 8),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= &exynos5_clk_ip_isp0_ctrl,
+		.ctrlbit	= (0x3F << 8),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME2,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= &exynos5_clk_ip_isp1_ctrl,
+		.ctrlbit	= (0xF << 4),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(camif0, 12),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(camif1, 13),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
+		.enable		= &exynos5_clk_ip_acp_ctrl,
+		.ctrlbit	= (1 << 7)
 	}
 };
 
diff --git a/arch/arm/mach-exynos/dev-sysmmu.c b/arch/arm/mach-exynos/dev-sysmmu.c
index 781563f..c5b1ea3 100644
--- a/arch/arm/mach-exynos/dev-sysmmu.c
+++ b/arch/arm/mach-exynos/dev-sysmmu.c
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
+/* linux/arch/arm/mach-exynos/dev-sysmmu.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * EXYNOS4 - System MMU support
+ * EXYNOS - System MMU support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,222 +12,263 @@
 
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
-#include <linux/export.h>
+
+#include <plat/cpu.h>
 
 #include <mach/map.h>
 #include <mach/irqs.h>
 #include <mach/sysmmu.h>
-#include <plat/s5p-clock.h>
-
-/* These names must be equal to the clock names in mach-exynos4/clock.c */
-const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
-	"SYSMMU_MDMA"	,
-	"SYSMMU_SSS"	,
-	"SYSMMU_FIMC0"	,
-	"SYSMMU_FIMC1"	,
-	"SYSMMU_FIMC2"	,
-	"SYSMMU_FIMC3"	,
-	"SYSMMU_JPEG"	,
-	"SYSMMU_FIMD0"	,
-	"SYSMMU_FIMD1"	,
-	"SYSMMU_PCIe"	,
-	"SYSMMU_G2D"	,
-	"SYSMMU_ROTATOR",
-	"SYSMMU_MDMA2"	,
-	"SYSMMU_TV"	,
-	"SYSMMU_MFC_L"	,
-	"SYSMMU_MFC_R"	,
-};
 
-static struct resource exynos4_sysmmu_resource[] = {
-	[0] = {
-		.start	= EXYNOS4_PA_SYSMMU_MDMA,
-		.end	= EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_SYSMMU_MDMA0_0,
-		.end	= IRQ_SYSMMU_MDMA0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start	= EXYNOS4_PA_SYSMMU_SSS,
-		.end	= EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[3] = {
-		.start	= IRQ_SYSMMU_SSS_0,
-		.end	= IRQ_SYSMMU_SSS_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[4] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC0,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[5] = {
-		.start	= IRQ_SYSMMU_FIMC0_0,
-		.end	= IRQ_SYSMMU_FIMC0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[6] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC1,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[7] = {
-		.start	= IRQ_SYSMMU_FIMC1_0,
-		.end	= IRQ_SYSMMU_FIMC1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[8] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC2,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[9] = {
-		.start	= IRQ_SYSMMU_FIMC2_0,
-		.end	= IRQ_SYSMMU_FIMC2_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[10] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC3,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[11] = {
-		.start	= IRQ_SYSMMU_FIMC3_0,
-		.end	= IRQ_SYSMMU_FIMC3_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[12] = {
-		.start	= EXYNOS4_PA_SYSMMU_JPEG,
-		.end	= EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[13] = {
-		.start	= IRQ_SYSMMU_JPEG_0,
-		.end	= IRQ_SYSMMU_JPEG_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[14] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMD0,
-		.end	= EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[15] = {
-		.start	= IRQ_SYSMMU_LCD0_M0_0,
-		.end	= IRQ_SYSMMU_LCD0_M0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[16] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMD1,
-		.end	= EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[17] = {
-		.start	= IRQ_SYSMMU_LCD1_M1_0,
-		.end	= IRQ_SYSMMU_LCD1_M1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[18] = {
-		.start	= EXYNOS4_PA_SYSMMU_PCIe,
-		.end	= EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[19] = {
-		.start	= IRQ_SYSMMU_PCIE_0,
-		.end	= IRQ_SYSMMU_PCIE_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[20] = {
-		.start	= EXYNOS4_PA_SYSMMU_G2D,
-		.end	= EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[21] = {
-		.start	= IRQ_SYSMMU_2D_0,
-		.end	= IRQ_SYSMMU_2D_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[22] = {
-		.start	= EXYNOS4_PA_SYSMMU_ROTATOR,
-		.end	= EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[23] = {
-		.start	= IRQ_SYSMMU_ROTATOR_0,
-		.end	= IRQ_SYSMMU_ROTATOR_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[24] = {
-		.start	= EXYNOS4_PA_SYSMMU_MDMA2,
-		.end	= EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[25] = {
-		.start	= IRQ_SYSMMU_MDMA1_0,
-		.end	= IRQ_SYSMMU_MDMA1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[26] = {
-		.start	= EXYNOS4_PA_SYSMMU_TV,
-		.end	= EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[27] = {
-		.start	= IRQ_SYSMMU_TV_M0_0,
-		.end	= IRQ_SYSMMU_TV_M0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[28] = {
-		.start	= EXYNOS4_PA_SYSMMU_MFC_L,
-		.end	= EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[29] = {
-		.start	= IRQ_SYSMMU_MFC_M0_0,
-		.end	= IRQ_SYSMMU_MFC_M0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[30] = {
-		.start	= EXYNOS4_PA_SYSMMU_MFC_R,
-		.end	= EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[31] = {
-		.start	= IRQ_SYSMMU_MFC_M1_0,
-		.end	= IRQ_SYSMMU_MFC_M1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
+static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
+
+#define SYSMMU_PLATFORM_DEVICE(ipname, devid)				\
+static struct sysmmu_platform_data platdata_##ipname = {		\
+	.dbgname = #ipname,						\
+};									\
+struct platform_device SYSMMU_PLATDEV(ipname) =				\
+{									\
+	.name		= SYSMMU_DEVNAME_BASE,				\
+	.id		= devid,					\
+	.dev		= {						\
+		.dma_mask		= &exynos_sysmmu_dma_mask,	\
+		.coherent_dma_mask	= DMA_BIT_MASK(32),		\
+		.platform_data		= &platdata_##ipname,		\
+	},								\
+}
+
+SYSMMU_PLATFORM_DEVICE(mfc_l,	0);
+SYSMMU_PLATFORM_DEVICE(mfc_r,	1);
+SYSMMU_PLATFORM_DEVICE(tv,	2);
+SYSMMU_PLATFORM_DEVICE(jpeg,	3);
+SYSMMU_PLATFORM_DEVICE(rot,	4);
+SYSMMU_PLATFORM_DEVICE(fimc0,	5); /* fimc* and gsc* exist exclusively */
+SYSMMU_PLATFORM_DEVICE(fimc1,	6);
+SYSMMU_PLATFORM_DEVICE(fimc2,	7);
+SYSMMU_PLATFORM_DEVICE(fimc3,	8);
+SYSMMU_PLATFORM_DEVICE(gsc0,	5);
+SYSMMU_PLATFORM_DEVICE(gsc1,	6);
+SYSMMU_PLATFORM_DEVICE(gsc2,	7);
+SYSMMU_PLATFORM_DEVICE(gsc3,	8);
+SYSMMU_PLATFORM_DEVICE(isp,	9);
+SYSMMU_PLATFORM_DEVICE(fimd0,	10);
+SYSMMU_PLATFORM_DEVICE(fimd1,	11);
+SYSMMU_PLATFORM_DEVICE(camif0,	12);
+SYSMMU_PLATFORM_DEVICE(camif1,	13);
+SYSMMU_PLATFORM_DEVICE(2d,	14);
+
+#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
+
+#define SYSMMU_RESOURCE(core, ipname)					\
+	static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
+
+#define DEFINE_SYSMMU_RESOURCE(core, mem, irq)				\
+	DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem),	\
+	DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
+
+#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq)			\
+	SYSMMU_RESOURCE(core, ipname) {					\
+		DEFINE_SYSMMU_RESOURCE(core, mem, irq)			\
+	}
 
-struct platform_device exynos4_device_sysmmu = {
-	.name		= "s5p-sysmmu",
-	.id		= 32,
-	.num_resources	= ARRAY_SIZE(exynos4_sysmmu_resource),
-	.resource	= exynos4_sysmmu_resource,
+struct sysmmu_resource_map {
+	struct platform_device *pdev;
+	struct resource *res;
+	u32 rnum;
+	struct device *pdd;
+	char *clocknames;
 };
-EXPORT_SYMBOL(exynos4_device_sysmmu);
 
-static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
-void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
-{
-	sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
-	if (IS_ERR(sysmmu_clk[ips]))
-		sysmmu_clk[ips] = NULL;
-	else
-		clk_put(sysmmu_clk[ips]);
+#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) {		\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME,				\
 }
 
-void sysmmu_clk_enable(sysmmu_ips ips)
-{
-	if (sysmmu_clk[ips])
-		clk_enable(sysmmu_clk[ips]);
+#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) {	\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,		\
+}
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) {		\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME,				\
+	.pdd = &exynos##core##_device_pd[pd].dev,			\
+}
+
+#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,		\
+	.pdd = &exynos##core##_device_pd[pd].dev,			\
 }
+#else
+#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd)		\
+		SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
+#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata)	\
+		SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
+
+#endif /* CONFIG_EXYNOS_DEV_PD */
+
+#ifdef CONFIG_ARCH_EXYNOS4
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0,	FIMC0,	FIMC0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1,	FIMC1,	FIMC1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2,	FIMC2,	FIMC2);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3,	FIMC3,	FIMC3);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg,	JPEG,	JPEG);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d,	G2D,	2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv,	TV,	TV_M0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp,	2D_ACP,	2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot,	ROTATOR, ROTATOR);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0,	FIMD0,	LCD0_M0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1,	FIMD1,	LCD1_M1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0,	FIMC_LITE0, FIMC_LITE0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1,	FIMC_LITE1, FIMC_LITE1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r,	MFC_R,	MFC_M0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l,	MFC_L,	MFC_M1);
+SYSMMU_RESOURCE(EXYNOS4, isp) {
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc0,	fimc0,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc1,	fimc1,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc2,	fimc2,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc3,	fimc3,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, tv,	tv,	PD_TV),
+	SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r,	mfc_r,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l,	mfc_l,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_PD(4, rot,	rot,	PD_LCD0),
+	SYSMMU_RESOURCE_MAPPING_PD(4, jpeg,	jpeg,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimd0,	fimd0,	PD_LCD0),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING_PD(4, 2d,	2d,	PD_LCD0),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimd1,	fimd1,	PD_LCD1),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING(4,	2d,	2d_acp),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	camif0, flite0,	PD_ISP),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	camif1, flite1,	PD_ISP),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	isp,	isp,	PD_ISP),
+};
+#endif /* CONFIG_ARCH_EXYNOS4 */
 
-void sysmmu_clk_disable(sysmmu_ips ips)
+#ifdef CONFIG_ARCH_EXYNOS5
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg,	JPEG,	JPEG);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1,	FIMD1,	FIMD1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d,	2D,	2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot,	ROTATOR, ROTATOR);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv,	TV,	TV);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0,	LITE0,	LITE0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1,	LITE1,	LITE1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0,	GSC0,	GSC0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1,	GSC1,	GSC1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2,	GSC2,	GSC2);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3,	GSC3,	GSC3);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r,	MFC_R,	MFC_R);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l,	MFC_L,	MFC_L);
+SYSMMU_RESOURCE(EXYNOS5, isp) {
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5,	ODC, ODC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING(5,	jpeg,	jpeg),
+	SYSMMU_RESOURCE_MAPPING(5,	fimd1,	fimd1),
+	SYSMMU_RESOURCE_MAPPING(5,	2d,	2d),
+	SYSMMU_RESOURCE_MAPPING(5,	rot,	rot),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	tv,	tv,	PD_DISP1),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	camif0,	flite0,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	camif1,	flite1,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc0,	gsc0,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc1,	gsc1,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc2,	gsc2,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc3,	gsc3,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	mfc_r,	mfc_r,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	mfc_l,	mfc_l,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_MCPD(5,	isp,	isp,	PD_ISP, mc_platdata),
+};
+#endif /* CONFIG_ARCH_EXYNOS5 */
+
+static int __init init_sysmmu_platform_device(void)
 {
-	if (sysmmu_clk[ips])
-		clk_disable(sysmmu_clk[ips]);
+	int i, j;
+	struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
+	int nmap[2] = {0, 0};
+
+#ifdef CONFIG_ARCH_EXYNOS5
+	if (soc_is_exynos5250()) {
+		resmap[0] = sysmmu_resmap5;
+		nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
+		nmap[1] = 0;
+	}
+#endif
+
+#ifdef CONFIG_ARCH_EXYNOS4
+	if (resmap[0] == NULL) {
+		resmap[0] = sysmmu_resmap4;
+		nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
+	}
+
+	if (soc_is_exynos4210()) {
+		resmap[1] = sysmmu_resmap4210;
+		nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
+	}
+
+	if (soc_is_exynos4412() || soc_is_exynos4212()) {
+		resmap[1] = sysmmu_resmap4212;
+		nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
+	}
+#endif
+
+	for (j = 0; j < 2; j++) {
+		for (i = 0; i < nmap[j]; i++) {
+			struct sysmmu_resource_map *map;
+			struct sysmmu_platform_data *platdata;
+
+			map = &resmap[j][i];
+
+			map->pdev->dev.parent = map->pdd;
+
+			platdata = map->pdev->dev.platform_data;
+			platdata->clockname = map->clocknames;
+
+			if (platform_device_add_resources(map->pdev, map->res,
+								map->rnum)) {
+				pr_err("%s: Failed to add device resources for "
+						"%s.%d\n", __func__,
+						map->pdev->name, map->pdev->id);
+				continue;
+			}
+
+			if (platform_device_register(map->pdev)) {
+				pr_err("%s: Failed to register %s.%d\n",
+					__func__, map->pdev->name,
+						map->pdev->id);
+			}
+		}
+	}
+
+	return 0;
 }
+arch_initcall(init_sysmmu_platform_device);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 33a119c..04646a8 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -129,23 +129,30 @@
 #define COMBINER_GROUP(x)	((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
 #define COMBINER_IRQ(x, y)	(COMBINER_GROUP(x) + y)
 
-#define IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
-#define IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
-#define IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
-#define IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
-#define IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
-#define IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
-#define IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
-#define IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
-
-#define IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
-#define IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
-#define IRQ_SYSMMU_LCD0_M0_0	COMBINER_IRQ(5, 2)
-#define IRQ_SYSMMU_LCD1_M1_0	COMBINER_IRQ(5, 3)
-#define IRQ_SYSMMU_TV_M0_0	COMBINER_IRQ(5, 4)
-#define IRQ_SYSMMU_MFC_M0_0	COMBINER_IRQ(5, 5)
-#define IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
-#define IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
+#define EXYNOS4_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
+#define EXYNOS4_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
+#define EXYNOS4_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
+#define EXYNOS4_IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
+
+#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
+#define EXYNOS4_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
+#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0	COMBINER_IRQ(5, 2)
+#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0	COMBINER_IRQ(5, 3)
+#define EXYNOS4_IRQ_SYSMMU_TV_M0_0	COMBINER_IRQ(5, 4)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0	COMBINER_IRQ(5, 5)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
+#define EXYNOS4_IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
+
+#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0	COMBINER_IRQ(16, 0)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0	COMBINER_IRQ(16, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0	COMBINER_IRQ(16, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0	COMBINER_IRQ(16, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0	COMBINER_IRQ(16, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0	COMBINER_IRQ(16, 5)
 
 #define IRQ_FIMD0_FIFO		COMBINER_IRQ(11, 0)
 #define IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
@@ -275,70 +282,70 @@
 #define IRQ_PMU			COMBINER_IRQ(1, 2)
 #define IRQ_PMU_CPU1		COMBINER_IRQ(1, 6)
 
-#define IRQ_SYSMMU_GSC0_0	COMBINER_IRQ(2, 0)
-#define IRQ_SYSMMU_GSC0_1	COMBINER_IRQ(2, 1)
-#define IRQ_SYSMMU_GSC1_0	COMBINER_IRQ(2, 2)
-#define IRQ_SYSMMU_GSC1_1	COMBINER_IRQ(2, 3)
-#define IRQ_SYSMMU_GSC2_0	COMBINER_IRQ(2, 4)
-#define IRQ_SYSMMU_GSC2_1	COMBINER_IRQ(2, 5)
-#define IRQ_SYSMMU_GSC3_0	COMBINER_IRQ(2, 6)
-#define IRQ_SYSMMU_GSC3_1	COMBINER_IRQ(2, 7)
-
-#define IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(3, 2)
-#define IRQ_SYSMMU_FIMD1_1	COMBINER_IRQ(3, 3)
-#define IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(3, 4)
-#define IRQ_SYSMMU_LITE0_1	COMBINER_IRQ(3, 5)
-#define IRQ_SYSMMU_SCALERPISP_0	COMBINER_IRQ(3, 6)
-#define IRQ_SYSMMU_SCALERPISP_1	COMBINER_IRQ(3, 7)
-
-#define IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(4, 0)
-#define IRQ_SYSMMU_ROTATOR_1	COMBINER_IRQ(4, 1)
-#define IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 2)
-#define IRQ_SYSMMU_JPEG_1	COMBINER_IRQ(4, 3)
-
-#define IRQ_SYSMMU_FD_0		COMBINER_IRQ(5, 0)
-#define IRQ_SYSMMU_FD_1		COMBINER_IRQ(5, 1)
-#define IRQ_SYSMMU_SCALERCISP_0	COMBINER_IRQ(5, 2)
-#define IRQ_SYSMMU_SCALERCISP_1	COMBINER_IRQ(5, 3)
-#define IRQ_SYSMMU_MCUISP_0	COMBINER_IRQ(5, 4)
-#define IRQ_SYSMMU_MCUISP_1	COMBINER_IRQ(5, 5)
-#define IRQ_SYSMMU_3DNR_0	COMBINER_IRQ(5, 6)
-#define IRQ_SYSMMU_3DNR_1	COMBINER_IRQ(5, 7)
-
-#define IRQ_SYSMMU_ARM_0	COMBINER_IRQ(6, 0)
-#define IRQ_SYSMMU_ARM_1	COMBINER_IRQ(6, 1)
-#define IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(6, 2)
-#define IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(6, 3)
-#define IRQ_SYSMMU_RTIC_0	COMBINER_IRQ(6, 4)
-#define IRQ_SYSMMU_RTIC_1	COMBINER_IRQ(6, 5)
-#define IRQ_SYSMMU_SSS_0	COMBINER_IRQ(6, 6)
-#define IRQ_SYSMMU_SSS_1	COMBINER_IRQ(6, 7)
-
-#define IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(7, 0)
-#define IRQ_SYSMMU_MDMA0_1	COMBINER_IRQ(7, 1)
-#define IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(7, 2)
-#define IRQ_SYSMMU_MDMA1_1	COMBINER_IRQ(7, 3)
-#define IRQ_SYSMMU_TV_0		COMBINER_IRQ(7, 4)
-#define IRQ_SYSMMU_TV_1		COMBINER_IRQ(7, 5)
-#define IRQ_SYSMMU_GPSX_0	COMBINER_IRQ(7, 6)
-#define IRQ_SYSMMU_GPSX_1	COMBINER_IRQ(7, 7)
-
-#define IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(8, 5)
-#define IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(8, 6)
-
-#define IRQ_SYSMMU_DIS1_0	COMBINER_IRQ(9, 4)
-#define IRQ_SYSMMU_DIS1_1	COMBINER_IRQ(9, 5)
-
-#define IRQ_DP			COMBINER_IRQ(10, 3)
-#define IRQ_SYSMMU_DIS0_0	COMBINER_IRQ(10, 4)
-#define IRQ_SYSMMU_DIS0_1	COMBINER_IRQ(10, 5)
-#define IRQ_SYSMMU_ISP_0	COMBINER_IRQ(10, 6)
-#define IRQ_SYSMMU_ISP_1	COMBINER_IRQ(10, 7)
-
-#define IRQ_SYSMMU_ODC_0	COMBINER_IRQ(11, 0)
-#define IRQ_SYSMMU_ODC_1	COMBINER_IRQ(11, 1)
-#define IRQ_SYSMMU_DRC_0	COMBINER_IRQ(11, 6)
-#define IRQ_SYSMMU_DRC_1	COMBINER_IRQ(11, 7)
+#define EXYNOS5_IRQ_SYSMMU_GSC0_0	COMBINER_IRQ(2, 0)
+#define EXYNOS5_IRQ_SYSMMU_GSC0_1	COMBINER_IRQ(2, 1)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_0	COMBINER_IRQ(2, 2)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_1	COMBINER_IRQ(2, 3)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_0	COMBINER_IRQ(2, 4)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_1	COMBINER_IRQ(2, 5)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_0	COMBINER_IRQ(2, 6)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_1	COMBINER_IRQ(2, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(3, 2)
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_1	COMBINER_IRQ(3, 3)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(3, 4)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_1	COMBINER_IRQ(3, 5)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0	COMBINER_IRQ(3, 6)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1	COMBINER_IRQ(3, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(4, 0)
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1	COMBINER_IRQ(4, 1)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 2)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_1	COMBINER_IRQ(4, 3)
+
+#define EXYNOS5_IRQ_SYSMMU_FD_0		COMBINER_IRQ(5, 0)
+#define EXYNOS5_IRQ_SYSMMU_FD_1		COMBINER_IRQ(5, 1)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0	COMBINER_IRQ(5, 2)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1	COMBINER_IRQ(5, 3)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_0	COMBINER_IRQ(5, 4)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_1	COMBINER_IRQ(5, 5)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_0	COMBINER_IRQ(5, 6)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_1	COMBINER_IRQ(5, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ARM_0	COMBINER_IRQ(6, 0)
+#define EXYNOS5_IRQ_SYSMMU_ARM_1	COMBINER_IRQ(6, 1)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_0	COMBINER_IRQ(6, 4)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_1	COMBINER_IRQ(6, 5)
+#define EXYNOS5_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(6, 6)
+#define EXYNOS5_IRQ_SYSMMU_SSS_1	COMBINER_IRQ(6, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(7, 0)
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_1	COMBINER_IRQ(7, 1)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(7, 2)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_1	COMBINER_IRQ(7, 3)
+#define EXYNOS5_IRQ_SYSMMU_TV_0		COMBINER_IRQ(7, 4)
+#define EXYNOS5_IRQ_SYSMMU_TV_1		COMBINER_IRQ(7, 5)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_0	COMBINER_IRQ(7, 6)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_1	COMBINER_IRQ(7, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(8, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_DIS1_0	COMBINER_IRQ(9, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS1_1	COMBINER_IRQ(9, 5)
+
+#define IRQ_DP				COMBINER_IRQ(10, 3)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_0	COMBINER_IRQ(10, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_1	COMBINER_IRQ(10, 5)
+#define EXYNOS5_IRQ_SYSMMU_ISP_0	COMBINER_IRQ(10, 6)
+#define EXYNOS5_IRQ_SYSMMU_ISP_1	COMBINER_IRQ(10, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ODC_0	COMBINER_IRQ(11, 0)
+#define EXYNOS5_IRQ_SYSMMU_ODC_1	COMBINER_IRQ(11, 1)
+#define EXYNOS5_IRQ_SYSMMU_DRC_0	COMBINER_IRQ(11, 6)
+#define EXYNOS5_IRQ_SYSMMU_DRC_1	COMBINER_IRQ(11, 7)
 
 #define IRQ_FIMD1_FIFO		COMBINER_IRQ(18, 4)
 #define IRQ_FIMD1_VSYNC		COMBINER_IRQ(18, 5)
@@ -352,11 +359,11 @@
 #define IRQ_MCT_G2		COMBINER_IRQ(23, 5)
 #define IRQ_MCT_G3		COMBINER_IRQ(23, 6)
 
-#define IRQ_EINT1		COMBINER_IRQ(24, 0)
-#define IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(24, 1)
-#define IRQ_SYSMMU_LITE1_1	COMBINER_IRQ(24, 2)
-#define IRQ_SYSMMU_2D_0		COMBINER_IRQ(24, 5)
-#define IRQ_SYSMMU_2D_1		COMBINER_IRQ(24, 6)
+#define IRQ_EINT1			COMBINER_IRQ(24, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(24, 1)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_1	COMBINER_IRQ(24, 2)
+#define EXYNOS5_IRQ_SYSMMU_2D_0		COMBINER_IRQ(24, 5)
+#define EXYNOS5_IRQ_SYSMMU_2D_1		COMBINER_IRQ(24, 6)
 
 #define IRQ_EINT2		COMBINER_IRQ(25, 0)
 #define IRQ_EINT3		COMBINER_IRQ(25, 1)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 57c13f1..cc4c8da 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -87,6 +87,7 @@
 #define EXYNOS4_PA_PDMA1		0x12690000
 
 #define EXYNOS4_PA_SYSMMU_MDMA		0x10A40000
+#define EXYNOS4_PA_SYSMMU_2D_ACP	0x10A40000
 #define EXYNOS4_PA_SYSMMU_SSS		0x10A50000
 #define EXYNOS4_PA_SYSMMU_FIMC0		0x11A20000
 #define EXYNOS4_PA_SYSMMU_FIMC1		0x11A30000
@@ -95,6 +96,12 @@
 #define EXYNOS4_PA_SYSMMU_JPEG		0x11A60000
 #define EXYNOS4_PA_SYSMMU_FIMD0		0x11E20000
 #define EXYNOS4_PA_SYSMMU_FIMD1		0x12220000
+#define EXYNOS4_PA_SYSMMU_FIMC_ISP	0x12260000
+#define EXYNOS4_PA_SYSMMU_FIMC_DRC	0x12270000
+#define EXYNOS4_PA_SYSMMU_FIMC_FD	0x122A0000
+#define EXYNOS4_PA_SYSMMU_ISPCPU	0x122B0000
+#define EXYNOS4_PA_SYSMMU_FIMC_LITE0	0x123B0000
+#define EXYNOS4_PA_SYSMMU_FIMC_LITE1	0x123C0000
 #define EXYNOS4_PA_SYSMMU_PCIe		0x12620000
 #define EXYNOS4_PA_SYSMMU_G2D		0x12A20000
 #define EXYNOS4_PA_SYSMMU_ROTATOR	0x12A30000
@@ -102,6 +109,37 @@
 #define EXYNOS4_PA_SYSMMU_TV		0x12E20000
 #define EXYNOS4_PA_SYSMMU_MFC_L		0x13620000
 #define EXYNOS4_PA_SYSMMU_MFC_R		0x13630000
+
+#define EXYNOS5_PA_SYSMMU_MDMA1		0x10A40000
+#define EXYNOS5_PA_SYSMMU_SSS		0x10A50000
+#define EXYNOS5_PA_SYSMMU_2D		0x10A60000
+#define EXYNOS5_PA_SYSMMU_MFC_L		0x11200000
+#define EXYNOS5_PA_SYSMMU_MFC_R		0x11210000
+#define EXYNOS5_PA_SYSMMU_ROTATOR	0x11D40000
+#define EXYNOS5_PA_SYSMMU_MDMA2		0x11D50000
+#define EXYNOS5_PA_SYSMMU_JPEG		0x11F20000
+#define EXYNOS5_PA_SYSMMU_IOP		0x12360000
+#define EXYNOS5_PA_SYSMMU_RTIC		0x12370000
+#define EXYNOS5_PA_SYSMMU_GPS		0x12630000
+#define EXYNOS5_PA_SYSMMU_ISP		0x13260000
+#define EXYNOS5_PA_SYSMMU_DRC		0x12370000
+#define EXYNOS5_PA_SYSMMU_SCALERC	0x13280000
+#define EXYNOS5_PA_SYSMMU_SCALERP	0x13290000
+#define EXYNOS5_PA_SYSMMU_FD		0x132A0000
+#define EXYNOS5_PA_SYSMMU_ISPCPU	0x132B0000
+#define EXYNOS5_PA_SYSMMU_ODC		0x132C0000
+#define EXYNOS5_PA_SYSMMU_DIS0		0x132D0000
+#define EXYNOS5_PA_SYSMMU_DIS1		0x132E0000
+#define EXYNOS5_PA_SYSMMU_3DNR		0x132F0000
+#define EXYNOS5_PA_SYSMMU_LITE0		0x13C40000
+#define EXYNOS5_PA_SYSMMU_LITE1		0x13C50000
+#define EXYNOS5_PA_SYSMMU_GSC0		0x13E80000
+#define EXYNOS5_PA_SYSMMU_GSC1		0x13E90000
+#define EXYNOS5_PA_SYSMMU_GSC2		0x13EA0000
+#define EXYNOS5_PA_SYSMMU_GSC3		0x13EB0000
+#define EXYNOS5_PA_SYSMMU_FIMD1		0x14640000
+#define EXYNOS5_PA_SYSMMU_TV		0x14650000
+
 #define EXYNOS4_PA_SPI0			0x13920000
 #define EXYNOS4_PA_SPI1			0x13930000
 #define EXYNOS4_PA_SPI2			0x13940000
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 113836b..de42145 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -130,6 +130,9 @@
 #define EXYNOS4_CLKGATE_SCLKCPU			EXYNOS_CLKREG(0x14800)
 #define EXYNOS4_CLKGATE_IP_CPU			EXYNOS_CLKREG(0x14900)
 
+#define EXYNOS4_CLKGATE_IP_ISP0			EXYNOS_CLKREG(0x18800)
+#define EXYNOS4_CLKGATE_IP_ISP1			EXYNOS_CLKREG(0x18804)
+
 #define EXYNOS4_APLL_LOCKTIME			(0x1C20)	/* 300us */
 
 #define EXYNOS4_APLLCON0_ENABLE_SHIFT		(31)
@@ -245,6 +248,8 @@
 #define EXYNOS5_CLKDIV_PERIC0			EXYNOS_CLKREG(0x10558)
 
 #define EXYNOS5_CLKGATE_IP_ACP			EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_ISP0			EXYNOS_CLKREG(0x0C800)
+#define EXYNOS5_CLKGATE_IP_ISP1			EXYNOS_CLKREG(0x0C804)
 #define EXYNOS5_CLKGATE_IP_GSCL			EXYNOS_CLKREG(0x10920)
 #define EXYNOS5_CLKGATE_IP_DISP1		EXYNOS_CLKREG(0x10928)
 #define EXYNOS5_CLKGATE_IP_MFC			EXYNOS_CLKREG(0x1092C)
diff --git a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
deleted file mode 100644
index 68ff6ad..0000000
--- a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * EXYNOS4 - System MMU register
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_SYSMMU_H
-#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
-
-#define S5P_MMU_CTRL			0x000
-#define S5P_MMU_CFG			0x004
-#define S5P_MMU_STATUS			0x008
-#define S5P_MMU_FLUSH			0x00C
-#define S5P_PT_BASE_ADDR		0x014
-#define S5P_INT_STATUS			0x018
-#define S5P_INT_CLEAR			0x01C
-#define S5P_PAGE_FAULT_ADDR		0x024
-#define S5P_AW_FAULT_ADDR		0x028
-#define S5P_AR_FAULT_ADDR		0x02C
-#define S5P_DEFAULT_SLAVE_ADDR		0x030
-
-#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
index 6a5fbb5..7fe8527 100644
--- a/arch/arm/mach-exynos/include/mach/sysmmu.h
+++ b/arch/arm/mach-exynos/include/mach/sysmmu.h
@@ -1,46 +1,62 @@
-/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * Samsung sysmmu driver for EXYNOS4
+ * EXYNOS - System MMU support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_ARCH_SYSMMU_H
-#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
-
-enum exynos4_sysmmu_ips {
-	SYSMMU_MDMA,
-	SYSMMU_SSS,
-	SYSMMU_FIMC0,
-	SYSMMU_FIMC1,
-	SYSMMU_FIMC2,
-	SYSMMU_FIMC3,
-	SYSMMU_JPEG,
-	SYSMMU_FIMD0,
-	SYSMMU_FIMD1,
-	SYSMMU_PCIe,
-	SYSMMU_G2D,
-	SYSMMU_ROTATOR,
-	SYSMMU_MDMA2,
-	SYSMMU_TV,
-	SYSMMU_MFC_L,
-	SYSMMU_MFC_R,
-	EXYNOS4_SYSMMU_TOTAL_IPNUM,
+ */
+
+#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
+#define _ARM_MACH_EXYNOS_SYSMMU_H_
+
+struct sysmmu_platform_data {
+	char *dbgname;
+	/* comma(,) separated list of clock names for clock gating */
+	char *clockname;
 };
 
-#define S5P_SYSMMU_TOTAL_IPNUM		EXYNOS4_SYSMMU_TOTAL_IPNUM
+#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
+
+#define SYSMMU_CLOCK_NAME "sysmmu"
+#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
+
+#ifdef CONFIG_EXYNOS_DEV_SYSMMU
+#include <linux/device.h>
+struct platform_device;
+
+#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
+
+extern struct platform_device SYSMMU_PLATDEV(mfc_l);
+extern struct platform_device SYSMMU_PLATDEV(mfc_r);
+extern struct platform_device SYSMMU_PLATDEV(tv);
+extern struct platform_device SYSMMU_PLATDEV(jpeg);
+extern struct platform_device SYSMMU_PLATDEV(rot);
+extern struct platform_device SYSMMU_PLATDEV(gsc0);
+extern struct platform_device SYSMMU_PLATDEV(gsc1);
+extern struct platform_device SYSMMU_PLATDEV(gsc2);
+extern struct platform_device SYSMMU_PLATDEV(gsc3);
+extern struct platform_device SYSMMU_PLATDEV(isp);
+extern struct platform_device SYSMMU_PLATDEV(fimd0);
+extern struct platform_device SYSMMU_PLATDEV(fimd1);
+extern struct platform_device SYSMMU_PLATDEV(camif0);
+extern struct platform_device SYSMMU_PLATDEV(camif1);
+extern struct platform_device SYSMMU_PLATDEV(2d);
 
-extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
+#ifdef CONFIG_IOMMU_API
+static inline void platform_set_sysmmu(
+				struct device *sysmmu, struct device *dev)
+{
+	dev->archdata.iommu = sysmmu;
+}
+#endif
 
-typedef enum exynos4_sysmmu_ips sysmmu_ips;
+#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
+#define platform_set_sysmmu(dev, sysmmu) do { } while (0)
+#endif
 
-void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
-void sysmmu_clk_enable(sysmmu_ips ips);
-void sysmmu_clk_disable(sysmmu_ips ips);
+#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
 
-#endif /* __ASM_ARM_ARCH_SYSMMU_H */
+#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index a1e7007..6ab171c 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -154,7 +154,6 @@ static struct platform_device *armlex4210_devices[] __initdata = {
 	&s3c_device_hsmmc3,
 	&s3c_device_rtc,
 	&s3c_device_wdt,
-	&exynos4_device_sysmmu,
 	&samsung_asoc_dma,
 	&armlex4210_smsc911x,
 	&exynos4_device_ahci,
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 2b71f18..49975ad 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -275,7 +275,6 @@ static struct platform_device *smdkv310_devices[] __initdata = {
 	&s5p_device_mfc_l,
 	&s5p_device_mfc_r,
 	&exynos4_device_spdif,
-	&exynos4_device_sysmmu,
 	&samsung_asoc_dma,
 	&samsung_asoc_idma,
 	&s5p_device_fimd0,
-- 
1.7.1




From pullip.cho at samsung.com  Tue Mar  6 03:31:49 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Tue, 06 Mar 2012 17:31:49 +0900
Subject: [PATCH v10 3/3] iommu/exynos: Add iommu driver for Exynos Platforms
Message-ID: <002201ccfb73$93311520$b9933f60$%cho@samsung.com>

HAALgBjAGgAbwBAAHMAYQBtAHMAdQBuAGcALgBjAG8AbQA=;Tue,
 06 Mar 2012 08:31:29 GMT;WwBQAEEAVABDAEgAIAB2ADEAMAAgADMALwAzAF0AIABpAG8AbQBtAHUALwBlAHgAeQBuAG8AcwA6ACAAQQBkAGQAIABpAG8AbQBtAHUAIABkAHIAaQB2AGUAcgAgAGYAbwByACAARQB4AHkAbgBvAHMAIABQAGwAYQB0AGYAbwByAG0AcwA=
x-cr-puzzleid: {CF0AAF04-8639-4D69-B4E1-BF71EA1B0A70}

This is the System MMU driver and IOMMU API implementation for
Exynos SOC platforms. Exynos platforms has more than 10 System
MMUs dedicated for each multimedia accellerators.

The System MMU driver is already in arc/arm/plat-s5p but it is
moved to drivers/iommu due to Ohad Ben-Cohen gathered IOMMU drivers
there

Any device driver in Exynos platforms that needs to control its
System MMU must call platform_set_sysmmu() to inform System MMU
driver who will control it.
platform_set_sysmmu() is defined in <mach/sysmmu.h>

Cc: Joerg Roedel <joerg.roedel at amd.com>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
---
 drivers/iommu/Kconfig        |   21 +
 drivers/iommu/Makefile       |    1 +
 drivers/iommu/exynos-iommu.c | 1088 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1110 insertions(+), 0 deletions(-)
 create mode 100644 drivers/iommu/exynos-iommu.c

diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 6bea696..25d3eed 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -142,4 +142,25 @@ config OMAP_IOMMU_DEBUG
 
          Say N unless you know you need this.
 
+config EXYNOS_IOMMU
+	bool "Exynos IOMMU Support"
+	depends on EXYNOS_DEV_SYSMMU
+	select IOMMU_API
+	help
+	  Support for the IOMMU(System MMU) of Samsung Exynos application
+	  processor family. This enables H/W multimedia accellerators to see
+	  non-linear physical memory chunks as a linear memory in their
+	  address spaces
+
+	  If unsure, say N here.
+
+config EXYNOS_IOMMU_DEBUG
+	bool "Debugging log for Exynos IOMMU"
+	depends on EXYNOS_IOMMU
+	help
+	  Select this to see the detailed log message that shows what
+	  happens in the IOMMU driver
+
+	  Say N unless you need kernel log message for IOMMU debugging
+
 endif # IOMMU_SUPPORT
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 0e36b49..5a8fd97 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_IRQ_REMAP) += intr_remapping.o
 obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
 obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o
 obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
+obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
new file mode 100644
index 0000000..4c1c48a
--- /dev/null
+++ b/drivers/iommu/exynos-iommu.c
@@ -0,0 +1,1088 @@
+/* linux/drivers/iommu/exynos_iommu.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifdef CONFIG_EXYNOS_IOMMU_DEBUG
+#define DEBUG
+#endif
+
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mm.h>
+#include <linux/iommu.h>
+#include <linux/errno.h>
+#include <linux/list.h>
+#include <linux/memblock.h>
+#include <linux/export.h>
+
+#include <asm/cacheflush.h>
+#include <asm/pgtable.h>
+
+#include <mach/sysmmu.h>
+
+#define S5P_MMU_CTRL			0x000
+#define S5P_MMU_CFG			0x004
+#define S5P_MMU_STATUS			0x008
+#define S5P_MMU_FLUSH			0x00C
+#define S5P_PT_BASE_ADDR		0x014
+#define S5P_INT_STATUS			0x018
+#define S5P_INT_CLEAR			0x01C
+#define S5P_PAGE_FAULT_ADDR		0x024
+#define S5P_AW_FAULT_ADDR		0x028
+#define S5P_AR_FAULT_ADDR		0x02C
+#define S5P_DEFAULT_SLAVE_ADDR		0x030
+#define S5P_MMU_VERSION			0x034
+#define S5P_PB0_SADDR			0x04C
+#define S5P_PB0_EADDR			0x050
+#define S5P_PB1_SADDR			0x054
+#define S5P_PB1_EADDR			0x058
+
+#define SECT_ORDER 20
+#define LPAGE_ORDER 16
+#define SPAGE_ORDER 12
+
+#define SECT_SIZE (1 << SECT_ORDER)
+#define LPAGE_SIZE (1 << LPAGE_ORDER)
+#define SPAGE_SIZE (1 << SPAGE_ORDER)
+
+#define SECT_MASK (~(SECT_SIZE - 1))
+#define LPAGE_MASK (~(LPAGE_SIZE - 1))
+#define SPAGE_MASK (~(SPAGE_SIZE - 1))
+
+#define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
+#define lv1ent_page(sent) ((*(sent) & 3) == 1)
+#define lv1ent_section(sent) ((*(sent) & 3) == 2)
+
+#define lv2ent_fault(pent) ((*(pent) & 3) == 0)
+#define lv2ent_small(pent) ((*(pent) & 2) == 2)
+#define lv2ent_large(pent) ((*(pent) & 3) == 1)
+
+#define section_phys(sent) (*(sent) & SECT_MASK)
+#define section_offs(iova) ((iova) & 0xFFFFF)
+#define lpage_phys(pent) (*(pent) & LPAGE_MASK)
+#define lpage_offs(iova) ((iova) & 0xFFFF)
+#define spage_phys(pent) (*(pent) & SPAGE_MASK)
+#define spage_offs(iova) ((iova) & 0xFFF)
+
+#define lv1ent_offset(iova) ((iova) >> SECT_ORDER)
+#define lv2ent_offset(iova) (((iova) & 0xFF000) >> SPAGE_ORDER)
+
+#define NUM_LV1ENTRIES 4096
+#define NUM_LV2ENTRIES 256
+
+#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
+
+#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
+
+#define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
+
+#define mk_lv1ent_sect(pa) ((pa) | 2)
+#define mk_lv1ent_page(pa) ((pa) | 1)
+#define mk_lv2ent_lpage(pa) ((pa) | 1)
+#define mk_lv2ent_spage(pa) ((pa) | 2)
+
+#define CTRL_ENABLE	0x5
+#define CTRL_BLOCK	0x7
+#define CTRL_DISABLE	0x0
+
+#define REG_MMU_CTRL		0x000
+#define REG_MMU_CFG		0x004
+#define REG_MMU_STATUS		0x008
+#define REG_MMU_FLUSH		0x00C
+#define REG_MMU_FLUSH_ENTRY	0x010
+#define REG_PT_BASE_ADDR	0x014
+#define REG_INT_STATUS		0x018
+#define REG_INT_CLEAR		0x01C
+#define REG_MMU_VERSION		0x034
+
+#define REG_PAGE_FAULT_ADDR	0x024
+#define REG_AW_FAULT_ADDR	0x028
+#define REG_AR_FAULT_ADDR	0x02C
+#define REG_DEFAULT_SLAVE_ADDR	0x030
+
+static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
+{
+	return pgtable + lv1ent_offset(iova);
+}
+
+static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
+{
+	return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
+}
+
+enum EXYNOS_SYSMMU_INTERRUPT_TYPE {
+	SYSMMU_PAGEFAULT,
+	SYSMMU_AR_MULTIHIT,
+	SYSMMU_AW_MULTIHIT,
+	SYSMMU_BUSERROR,
+	SYSMMU_AR_SECURITY,
+	SYSMMU_AR_ACCESS,
+	SYSMMU_AW_SECURITY,
+	SYSMMU_AW_PROTECTION, /* 7 */
+	SYSMMU_FAULT_UNKNOWN,
+	SYSMMU_FAULTS_NUM
+};
+
+typedef int (*sysmmu_fault_handler_t)(enum EXYNOS_SYSMMU_INTERRUPT_TYPE itype,
+			unsigned long pgtable_base, unsigned long fault_addr);
+
+static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
+	REG_PAGE_FAULT_ADDR,
+	REG_AR_FAULT_ADDR,
+	REG_AW_FAULT_ADDR,
+	REG_DEFAULT_SLAVE_ADDR,
+	REG_AR_FAULT_ADDR,
+	REG_AR_FAULT_ADDR,
+	REG_AW_FAULT_ADDR,
+	REG_AW_FAULT_ADDR
+};
+
+static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
+	"PAGE FAULT",
+	"AR MULTI-HIT FAULT",
+	"AW MULTI-HIT FAULT",
+	"BUS ERROR",
+	"AR SECURITY PROTECTION FAULT",
+	"AR ACCESS PROTECTION FAULT",
+	"AW SECURITY PROTECTION FAULT",
+	"AW ACCESS PROTECTION FAULT",
+	"UNKNOWN FAULT"
+};
+
+/* We does not consider super section mapping (16MB) */
+struct iommu_client {
+	struct list_head node;
+	struct device *dev;
+	int refcnt;
+};
+
+struct exynos_iommu_domain {
+	struct list_head clients; /* list of iommu_client */
+	unsigned long *pgtable; /* lv1 page table, 16KB */
+	short *lv2entcnt; /* free lv2 entry counter for each section */
+	spinlock_t lock; /* lock for this structure and attached iommu_client */
+	spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
+};
+
+struct sysmmu_drvdata {
+	struct device *sysmmu;
+	char *dbgname;
+	int nsfrs;
+	void __iomem **sfrbases;
+	struct clk *clk[2];
+	bool active;
+	rwlock_t lock;
+	struct iommu_domain *domain;
+	sysmmu_fault_handler_t fault_handler;
+	unsigned long pgtable;
+	struct iommu_client client;
+};
+
+static bool set_sysmmu_active(struct sysmmu_drvdata *data)
+{
+	/* return true if the System MMU was not active previously
+	   and it needs to be initialized */
+	if (WARN_ON_ONCE(data->active))
+		return false;
+	data->active = true;
+	return true;
+}
+
+static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
+{
+	/* return true if the System MMU is needed to be disabled */
+	if (WARN_ON_ONCE(!data->active))
+		return false;
+	data->active = false;
+	return true;
+}
+
+static bool is_sysmmu_active(struct sysmmu_drvdata *data)
+{
+	return data->active;
+}
+
+static void sysmmu_block(void __iomem *sfrbase)
+{
+	__raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
+}
+
+static void sysmmu_unblock(void __iomem *sfrbase)
+{
+	__raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
+}
+
+static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
+{
+	__raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
+}
+
+static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
+						unsigned long iova)
+{
+	__raw_writel((iova & SPAGE_MASK) | 1, sfrbase + REG_MMU_FLUSH_ENTRY);
+}
+
+static void __sysmmu_set_ptbase(void __iomem *sfrbase,
+				       unsigned long pgd)
+{
+	__raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */
+	__raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
+
+	__sysmmu_tlb_invalidate(sfrbase);
+}
+
+static void __sysmmu_set_prefbuf(void __iomem *sfrbase, unsigned long base,
+						unsigned long size, int idx)
+{
+	__raw_writel(base, sfrbase + S5P_PB0_SADDR + idx * 8);
+	__raw_writel(size - 1 + base,  sfrbase + S5P_PB0_EADDR + idx * 8);
+}
+
+void exynos_sysmmu_set_prefbuf(struct device *dev,
+				unsigned long base0, unsigned long size0,
+				unsigned long base1, unsigned long size1)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	unsigned long flags;
+	int i;
+
+	BUG_ON((base0 + size0) <= base0);
+	BUG_ON((size1 > 0) && ((base1 + size1) <= base1));
+
+	read_lock_irqsave(&data->lock, flags);
+	if (!is_sysmmu_active(data))
+		goto finish;
+
+	for (i = 0; i < data->nsfrs; i++) {
+		if ((readl(data->sfrbases[i] + S5P_MMU_VERSION) >> 28) == 3) {
+			sysmmu_block(data->sfrbases[i]);
+
+			if (size1 == 0) {
+				if (size0 <= SZ_128K) {
+					base1 = base0;
+					size1 = size0;
+				} else {
+					size1 = size0 -
+						ALIGN(size0 / 2, SZ_64K);
+					size0 = size0 - size1;
+					base1 = base0 + size0;
+				}
+			}
+
+			__sysmmu_set_prefbuf(
+					data->sfrbases[i], base0, size0, 0);
+			__sysmmu_set_prefbuf(
+					data->sfrbases[i], base1, size1, 1);
+
+			sysmmu_unblock(data->sfrbases[i]);
+		}
+	}
+finish:
+	read_unlock_irqrestore(&data->lock, flags);
+}
+
+static void __set_fault_handler(struct sysmmu_drvdata *data,
+					sysmmu_fault_handler_t handler)
+{
+	unsigned long flags;
+
+	write_lock_irqsave(&data->lock, flags);
+	data->fault_handler = handler;
+	write_unlock_irqrestore(&data->lock, flags);
+}
+
+void exynos_sysmmu_set_fault_handler(struct device *dev,
+					sysmmu_fault_handler_t handler)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+
+	__set_fault_handler(data, handler);
+}
+
+static int default_fault_handler(enum EXYNOS_SYSMMU_INTERRUPT_TYPE itype,
+		     unsigned long pgtable_base, unsigned long fault_addr)
+{
+	unsigned long *ent;
+
+	if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
+		itype = SYSMMU_FAULT_UNKNOWN;
+
+	pr_err("%s occured at 0x%lx(Page table base: 0x%lx)\n",
+			sysmmu_fault_name[itype], fault_addr, pgtable_base);
+
+	ent = section_entry(__va(pgtable_base), fault_addr);
+	pr_err("\tLv1 entry: 0x%lx\n", *ent);
+
+	if (lv1ent_page(ent)) {
+		ent = page_entry(ent, fault_addr);
+		pr_err("\t Lv2 entry: 0x%lx\n", *ent);
+	}
+
+	pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
+
+	BUG();
+
+	return 0;
+}
+
+static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
+{
+	/* SYSMMU is in blocked when interrupt occurred. */
+	struct sysmmu_drvdata *data = dev_id;
+	struct resource *irqres;
+	struct platform_device *pdev;
+	enum EXYNOS_SYSMMU_INTERRUPT_TYPE itype;
+	unsigned long addr = -1;
+
+	int i, ret = -ENOSYS;
+
+	read_lock(&data->lock);
+
+	WARN_ON(!is_sysmmu_active(data));
+
+	pdev = to_platform_device(data->sysmmu);
+	for (i = 0; i < pdev->num_resources; i++) {
+		irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+		if (irqres && ((int)irqres->start == irq))
+			break;
+	}
+
+	if (i == pdev->num_resources) {
+		itype = SYSMMU_FAULT_UNKNOWN;
+	} else {
+		i /= 2;
+
+		itype = (enum EXYNOS_SYSMMU_INTERRUPT_TYPE)
+			__ffs(__raw_readl(data->sfrbases[i] + REG_INT_STATUS));
+		if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
+			itype = SYSMMU_FAULT_UNKNOWN;
+		else
+			addr = __raw_readl(
+				data->sfrbases[i] + fault_reg_offset[itype]);
+	}
+
+	if (data->domain)
+		ret = report_iommu_fault(data->domain, data->client.dev,
+				addr, itype);
+
+	if ((ret == -ENOSYS) && data->fault_handler) {
+		unsigned long base = data->pgtable;
+		if (itype != SYSMMU_FAULT_UNKNOWN)
+			base = __raw_readl(
+					data->sfrbases[i] + REG_PT_BASE_ADDR);
+		ret = data->fault_handler(itype, base, addr);
+	}
+
+	if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
+		__raw_writel(1 << itype, data->sfrbases[i] + REG_INT_CLEAR);
+	else
+		dev_dbg(data->sysmmu, "(%s) %s is not handled.\n",
+				data->dbgname, sysmmu_fault_name[itype]);
+
+	if (itype != SYSMMU_FAULT_UNKNOWN)
+		sysmmu_unblock(data->sfrbases[i]);
+
+	read_unlock(&data->lock);
+
+	return IRQ_HANDLED;
+}
+
+static bool __sysmmu_disable(struct sysmmu_drvdata *data)
+{
+	unsigned long flags;
+	bool disabled = false;
+	int i;
+
+	write_lock_irqsave(&data->lock, flags);
+
+	if (!set_sysmmu_inactive(data))
+		goto finish;
+
+	for (i = 0; i < data->nsfrs; i++) {
+		__raw_writel(CTRL_DISABLE, data->sfrbases[i] + REG_MMU_CTRL);
+		if (data->clk[1])
+			clk_disable(data->clk[1]);
+		if (data->clk[0])
+			clk_disable(data->clk[0]);
+		disabled = true;
+		data->pgtable = 0;
+		data->domain = NULL;
+		pm_runtime_put(data->sysmmu);
+	}
+
+finish:
+	write_unlock_irqrestore(&data->lock, flags);
+
+	return disabled;
+}
+
+/* __exynos_sysmmu_enable: Enables System MMU
+ *
+ * returns -error if an error occurred and System MMU is not enabled,
+ * 0 if the System MMU has been just enabled and 1 if System MMU was already
+ * enabled before.
+ */
+static int __exynos_sysmmu_enable(struct device *dev, unsigned long pgtable,
+						struct iommu_domain *domain)
+{
+	int i, ret = 0;
+	unsigned long flags;
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+
+	BUG_ON(!memblock_is_memory(pgtable));
+
+	ret = pm_runtime_get_sync(data->sysmmu);
+	if (ret < 0)
+		return ret;
+
+	write_lock_irqsave(&data->lock, flags);
+
+	if (!set_sysmmu_active(data)) {
+		/* RPM of sysmmu won't be refcounted */
+		if (ret > 0)
+			pm_runtime_put(data->sysmmu);
+
+		if (WARN_ON(pgtable != data->pgtable)) {
+			set_sysmmu_inactive(data);
+			ret = -EBUSY;
+		}
+
+		ret = 1;
+		dev_dbg(data->sysmmu, "(%s) Already enabled\n", data->dbgname);
+		goto finish;
+	}
+
+	if (data->clk[0])
+		clk_enable(data->clk[0]);
+	if (data->clk[1])
+		clk_enable(data->clk[1]);
+
+	data->pgtable = pgtable;
+
+	for (i = 0; i < data->nsfrs; i++) {
+		__sysmmu_set_ptbase(data->sfrbases[i], pgtable);
+
+		if ((readl(data->sfrbases[i] + S5P_MMU_VERSION) >> 28) == 3) {
+			/* System MMU version is 3.x */
+			__raw_writel((1 << 12) | (2 << 28),
+					data->sfrbases[i] + S5P_MMU_CFG);
+			__sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 0);
+			__sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 1);
+		}
+
+		__raw_writel(CTRL_ENABLE, data->sfrbases[i] + REG_MMU_CTRL);
+	}
+
+	data->domain = domain;
+
+	dev_dbg(data->sysmmu, "(%s) Enabled\n", data->dbgname);
+finish:
+	write_unlock_irqrestore(&data->lock, flags);
+
+	if (ret < 0) {
+		__sysmmu_disable(data);
+		dev_dbg(data->sysmmu, "(%s) Failed to enable\n", data->dbgname);
+	}
+
+	return ret;
+}
+
+static struct iommu_client *__get_enabled_iommu_client(
+				struct iommu_domain *domain, struct device *dev)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	struct exynos_iommu_domain *priv = domain->priv;
+	int ret;
+
+	ret = __exynos_sysmmu_enable(dev, __pa(priv->pgtable), domain);
+	if (ret < 0)
+		return ERR_PTR(ret);
+	else if (ret == 1)
+		return ERR_PTR(-EBUSY);
+
+	INIT_LIST_HEAD(&data->client.node);
+	data->client.dev = dev;
+	data->client.refcnt = 1;
+
+	return &data->client;
+}
+
+int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable)
+{
+	return __exynos_sysmmu_enable(dev, pgtable, NULL);
+}
+
+void exynos_sysmmu_disable(struct device *dev)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	bool disabled;
+
+	disabled = __sysmmu_disable(data);
+	dev_dbg(data->sysmmu,
+			disabled ? "(%s) Disabled.\n" :
+				"(%s) Deactivation request ignorred.\n",
+			data->dbgname);
+}
+
+static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova)
+{
+	unsigned long flags;
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+
+	read_lock_irqsave(&data->lock, flags);
+
+	if (is_sysmmu_active(data)) {
+		int i;
+		for (i = 0; i < data->nsfrs; i++) {
+			sysmmu_block(data->sfrbases[i]);
+			__sysmmu_tlb_invalidate_entry(data->sfrbases[i], iova);
+			sysmmu_unblock(data->sfrbases[i]);
+		}
+	} else {
+		dev_dbg(data->sysmmu,
+			"(%s) Disabled. Skipping invalidating TLB.\n",
+			data->dbgname);
+	}
+
+	read_unlock_irqrestore(&data->lock, flags);
+}
+
+void exynos_sysmmu_tlb_invalidate(struct device *dev)
+{
+	unsigned long flags;
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+
+	read_lock_irqsave(&data->lock, flags);
+
+	if (is_sysmmu_active(data)) {
+		int i;
+		for (i = 0; i < data->nsfrs; i++) {
+			sysmmu_block(data->sfrbases[i]);
+			__sysmmu_tlb_invalidate(data->sfrbases[i]);
+			sysmmu_unblock(data->sfrbases[i]);
+		}
+	} else {
+		dev_dbg(data->sysmmu,
+			"(%s) Disabled. Skipping invalidating TLB.\n",
+			data->dbgname);
+	}
+
+	read_unlock_irqrestore(&data->lock, flags);
+}
+
+static int exynos_sysmmu_probe(struct platform_device *pdev)
+{
+	int i, ret;
+	struct device *dev;
+	struct sysmmu_drvdata *data;
+
+	dev = &pdev->dev;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data) {
+		dev_dbg(dev, "Not enough memory\n");
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+
+	ret = dev_set_drvdata(dev, data);
+	if (ret) {
+		dev_dbg(dev, "Unabled to initialize driver data\n");
+		goto err_init;
+	}
+
+	data->nsfrs = pdev->num_resources / 2;
+	data->sfrbases = kmalloc(sizeof(*data->sfrbases) * data->nsfrs,
+								GFP_KERNEL);
+	if (data->sfrbases == NULL) {
+		dev_dbg(dev, "Not enough memory\n");
+		ret = -ENOMEM;
+		goto err_init;
+	}
+
+	for (i = 0; i < data->nsfrs; i++) {
+		struct resource *res;
+		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+		if (!res) {
+			dev_dbg(dev, "Unable to find IOMEM region\n");
+			ret = -ENOENT;
+			goto err_res;
+		}
+
+		data->sfrbases[i] = ioremap(res->start, resource_size(res));
+		if (!data->sfrbases[i]) {
+			dev_dbg(dev, "Unable to map IOMEM @ PA:%#x\n",
+							res->start);
+			ret = -ENOENT;
+			goto err_res;
+		}
+	}
+
+	for (i = 0; i < data->nsfrs; i++) {
+		ret = platform_get_irq(pdev, i);
+		if (ret <= 0) {
+			dev_dbg(dev, "Unable to find IRQ resource\n");
+			goto err_irq;
+		}
+
+		ret = request_irq(ret, exynos_sysmmu_irq, 0,
+					dev_name(dev), data);
+		if (ret) {
+			dev_dbg(dev, "Unabled to register interrupt handler\n");
+			goto err_irq;
+		}
+	}
+
+	if (dev_get_platdata(dev)) {
+		char *deli, *beg;
+		struct sysmmu_platform_data *platdata = dev_get_platdata(dev);
+
+		beg = platdata->clockname;
+
+		for (deli = beg; (*deli != '\0') && (*deli != ','); deli++)
+			/* NOTHING */;
+
+		if (*deli == '\0')
+			deli = NULL;
+		else
+			*deli = '\0';
+
+		data->clk[0] = clk_get(dev, beg);
+		if (IS_ERR(data->clk[0])) {
+			data->clk[0] = NULL;
+			dev_dbg(dev, "No clock descriptor registered\n");
+		}
+
+		if (data->clk[0] && deli) {
+			*deli = ',';
+			data->clk[1] = clk_get(dev, deli + 1);
+			if (IS_ERR(data->clk[1]))
+				data->clk[1] = NULL;
+		}
+
+		data->dbgname = platdata->dbgname;
+	}
+
+	data->sysmmu = dev;
+	rwlock_init(&data->lock);
+
+	__set_fault_handler(data, &default_fault_handler);
+
+	if (dev->parent)
+		pm_runtime_enable(dev);
+
+	dev_dbg(dev, "(%s) Initialized\n", data->dbgname);
+	return 0;
+err_irq:
+	while (i-- > 0) {
+		int irq;
+
+		irq = platform_get_irq(pdev, i);
+		free_irq(irq, data);
+	}
+err_res:
+	while (data->nsfrs-- > 0)
+		iounmap(data->sfrbases[data->nsfrs]);
+	kfree(data->sfrbases);
+err_init:
+	kfree(data);
+err_alloc:
+	dev_err(dev, "Failed to initialize\n");
+	return ret;
+}
+
+static struct platform_driver exynos_sysmmu_driver = {
+	.probe		= exynos_sysmmu_probe,
+	.driver		= {
+		.owner		= THIS_MODULE,
+		.name		= "exynos-sysmmu",
+	}
+};
+
+static inline void pgtable_flush(void *vastart, void *vaend)
+{
+	dmac_flush_range(vastart, vaend);
+	outer_flush_range(virt_to_phys(vastart),
+				virt_to_phys(vaend));
+}
+
+static int exynos_iommu_domain_init(struct iommu_domain *domain)
+{
+	struct exynos_iommu_domain *priv;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->pgtable = (unsigned long *)__get_free_pages(
+						GFP_KERNEL | __GFP_ZERO, 2);
+	if (!priv->pgtable)
+		goto err_pgtable;
+
+	priv->lv2entcnt = (short *)__get_free_pages(
+						GFP_KERNEL | __GFP_ZERO, 1);
+	if (!priv->lv2entcnt)
+		goto err_counter;
+
+	pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
+
+	spin_lock_init(&priv->lock);
+	spin_lock_init(&priv->pgtablelock);
+	INIT_LIST_HEAD(&priv->clients);
+
+	domain->priv = priv;
+	return 0;
+
+err_counter:
+	free_pages((unsigned long)priv->pgtable, 2);
+err_pgtable:
+	kfree(priv);
+	return -ENOMEM;
+}
+
+static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	struct list_head *pos, *n;
+	unsigned long flags;
+	int i;
+
+	WARN_ON(!list_empty(&priv->clients));
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	list_for_each_safe(pos, n, &priv->clients) {
+		struct iommu_client *client;
+
+		client = list_entry(pos, struct iommu_client, node);
+		exynos_sysmmu_disable(client->dev);
+		kfree(client);
+	}
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	for (i = 0; i < NUM_LV1ENTRIES; i++)
+		if (lv1ent_page(priv->pgtable + i))
+			kfree(__va(lv2table_base(priv->pgtable + i)));
+
+	free_pages((unsigned long)priv->pgtable, 2);
+	free_pages((unsigned long)priv->lv2entcnt, 1);
+	kfree(domain->priv);
+	domain->priv = NULL;
+}
+
+static int exynos_iommu_attach_device(struct iommu_domain *domain,
+				   struct device *dev)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	struct iommu_client *client = NULL;
+	struct list_head *pos;
+	unsigned long flags;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	list_for_each(pos, &priv->clients) {
+		struct iommu_client *cur;
+
+		cur = list_entry(pos, struct iommu_client, node);
+		if (cur->dev == dev) {
+			client = cur;
+			break;
+		}
+	}
+
+	if (client != NULL)
+		client->refcnt++;
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	if (client != NULL) {
+		dev_dbg(dev, "%s: IOMMU with pgtable 0x%lx already attached\n",
+					__func__, __pa(priv->pgtable));
+		return 0;
+	}
+
+	client = __get_enabled_iommu_client(domain, dev);
+	if (IS_ERR(client))
+		return PTR_ERR(client);
+
+	spin_lock_irqsave(&priv->lock, flags);
+	list_add_tail(&client->node, &priv->clients);
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	dev_dbg(dev, "%s: Attached new IOMMU with pgtable 0x%lx\n", __func__,
+						__pa(priv->pgtable));
+	return 0;
+}
+
+static void exynos_iommu_detach_device(struct iommu_domain *domain,
+				    struct device *dev)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	struct iommu_client *client = NULL;
+	struct list_head *pos;
+	unsigned long flags;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	list_for_each(pos, &priv->clients) {
+		struct iommu_client *cur;
+
+		cur = list_entry(pos, struct iommu_client, node);
+		if (cur->dev == dev) {
+			cur->refcnt--;
+			client = cur;
+			break;
+		}
+	}
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	if (WARN_ON(client == NULL))
+		return;
+
+	if (client->refcnt > 0) {
+		dev_dbg(dev,
+			"IOMMU is still attached %d times with pgtable %#lx\n",
+					client->refcnt, __pa(priv->pgtable));
+		return;
+	}
+
+	list_del(&client->node);
+	exynos_sysmmu_disable(client->dev);
+	dev_dbg(dev, "%s: Detached IOMMU with pgtable 0x%lx\n", __func__,
+						__pa(priv->pgtable));
+}
+
+static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,
+					short *pgcounter)
+{
+	if (lv1ent_fault(sent)) {
+		unsigned long *pent;
+
+		pent = kzalloc(LV2TABLE_SIZE, GFP_ATOMIC);
+		BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
+		if (!pent)
+			return NULL;
+
+		*sent = mk_lv1ent_page(__pa(pent));
+		*pgcounter = NUM_LV2ENTRIES;
+		pgtable_flush(pent, pent + NUM_LV2ENTRIES);
+		pgtable_flush(sent, sent + 1);
+	}
+
+	return page_entry(sent, iova);
+}
+
+static int lv1set_section(unsigned long *sent, phys_addr_t paddr, short *pgcnt)
+{
+	if (lv1ent_section(sent))
+		return -EADDRINUSE;
+
+	if (lv1ent_page(sent)) {
+		if (*pgcnt != NUM_LV2ENTRIES)
+			return -EADDRINUSE;
+
+		kfree(page_entry(sent, 0));
+
+		*pgcnt = 0;
+	}
+
+	*sent = mk_lv1ent_sect(paddr);
+
+	pgtable_flush(sent, sent + 1);
+
+	return 0;
+}
+
+static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
+								short *pgcnt)
+{
+	if (size == SPAGE_SIZE) {
+		if (!lv2ent_fault(pent))
+			return -EADDRINUSE;
+
+		*pent = mk_lv2ent_spage(paddr);
+		pgtable_flush(pent, pent + 1);
+		*pgcnt -= 1;
+	} else { /* size == LPAGE_SIZE */
+		int i;
+		for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
+			if (!lv2ent_fault(pent)) {
+				memset(pent, 0, sizeof(*pent) * i);
+				return -EADDRINUSE;
+			}
+
+			*pent = mk_lv2ent_lpage(paddr);
+		}
+		pgtable_flush(pent - SPAGES_PER_LPAGE, pent);
+		*pgcnt -= SPAGES_PER_LPAGE;
+	}
+
+	return 0;
+}
+
+static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova,
+			 phys_addr_t paddr, size_t size, int prot)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	unsigned long *entry;
+	unsigned long flags;
+	int ret = -ENOMEM;
+
+	BUG_ON(priv->pgtable == NULL);
+
+	spin_lock_irqsave(&priv->pgtablelock, flags);
+
+	entry = section_entry(priv->pgtable, iova);
+
+	if (size == SECT_SIZE) {
+		ret = lv1set_section(entry, paddr,
+					&priv->lv2entcnt[lv1ent_offset(iova)]);
+	} else {
+		unsigned long *pent;
+
+		pent = alloc_lv2entry(entry, iova,
+					&priv->lv2entcnt[lv1ent_offset(iova)]);
+
+		if (!pent)
+			ret = -ENOMEM;
+		else
+			ret = lv2set_page(pent, paddr, size,
+					&priv->lv2entcnt[lv1ent_offset(iova)]);
+	}
+
+	if (ret) {
+		pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n",
+							__func__, iova, size);
+	}
+
+	spin_unlock_irqrestore(&priv->pgtablelock, flags);
+
+	return ret;
+}
+
+static size_t exynos_iommu_unmap(struct iommu_domain *domain,
+					       unsigned long iova, size_t size)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	struct iommu_client *client;
+	unsigned long flags;
+	unsigned long *ent;
+
+	BUG_ON(priv->pgtable == NULL);
+
+	spin_lock_irqsave(&priv->pgtablelock, flags);
+
+	ent = section_entry(priv->pgtable, iova);
+
+	if (lv1ent_section(ent)) {
+		BUG_ON(size < SECT_SIZE);
+
+		*ent = 0;
+		pgtable_flush(ent, ent + 1);
+		size = SECT_SIZE;
+		goto done;
+	}
+
+	if (unlikely(lv1ent_fault(ent))) {
+		if (size > SECT_SIZE)
+			size = SECT_SIZE;
+		goto done;
+	}
+
+	/* lv1ent_page(sent) == true here */
+
+	ent = page_entry(ent, iova);
+
+	if (unlikely(lv2ent_fault(ent))) {
+		size = SPAGE_SIZE;
+		goto done;
+	}
+
+	if (lv2ent_small(ent)) {
+		*ent = 0;
+		size = SPAGE_SIZE;
+		priv->lv2entcnt[lv1ent_offset(iova)] -= 1;
+		goto done;
+	}
+
+	/* lv1ent_large(ent) == true here */
+	BUG_ON(size < LPAGE_SIZE);
+
+	memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
+
+	size = LPAGE_SIZE;
+	priv->lv2entcnt[lv1ent_offset(iova)] -= SPAGES_PER_LPAGE;
+done:
+	list_for_each_entry(client, &priv->clients, node)
+		sysmmu_tlb_invalidate_entry(client->dev, iova);
+
+	spin_unlock_irqrestore(&priv->pgtablelock, flags);
+
+	return size;
+}
+
+static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
+					  unsigned long iova)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	unsigned long *entry;
+	unsigned long flags;
+	phys_addr_t phys = -1;
+
+	spin_lock_irqsave(&priv->pgtablelock, flags);
+
+	entry = section_entry(priv->pgtable, iova);
+
+	if (lv1ent_section(entry)) {
+		phys = section_phys(entry) + section_offs(iova);
+	} else if (lv1ent_page(entry)) {
+		entry = page_entry(entry, iova);
+
+		if (lv2ent_large(entry))
+			phys = lpage_phys(entry) + lpage_offs(iova);
+		else if (lv2ent_small(entry))
+			phys = spage_phys(entry) + spage_offs(iova);
+	}
+
+	spin_unlock_irqrestore(&priv->pgtablelock, flags);
+
+	return phys;
+}
+
+static struct iommu_ops exynos_iommu_ops = {
+	.domain_init = &exynos_iommu_domain_init,
+	.domain_destroy = &exynos_iommu_domain_destroy,
+	.attach_dev = &exynos_iommu_attach_device,
+	.detach_dev = &exynos_iommu_detach_device,
+	.map = &exynos_iommu_map,
+	.unmap = &exynos_iommu_unmap,
+	.iova_to_phys = &exynos_iommu_iova_to_phys,
+	.pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
+};
+
+static int __init exynos_iommu_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&exynos_sysmmu_driver);
+
+	if (ret == 0)
+		bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
+
+	return ret;
+}
+arch_initcall(exynos_iommu_init);
-- 
1.7.1




From t-kristo at ti.com  Tue Mar  6 03:31:53 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 10:31:53 +0200
Subject: [PATCHv3 1/4] ARM: OMAP4: suspend: Program all domains to
 retention
In-Reply-To: <871up6in50.fsf@ti.com>
References: <1330529106-10423-1-git-send-email-t-kristo@ti.com>
 <1330529106-10423-2-git-send-email-t-kristo@ti.com> <871up6in50.fsf@ti.com>
Message-ID: <1331022713.2116.144.camel@sokoban>

On Mon, 2012-03-05 at 16:33 -0800, Kevin Hilman wrote:
> Tero Kristo <t-kristo at ti.com> writes:
> 
> > From: Rajendra Nayak <rnayak at ti.com>
> >
> > Remove the FIXME's in the suspend sequence since
> > we now intend to support system level RET support.
> >
> > Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> > Signed-off-by: Tero Kristo <t-kristo at ti.com>
> > Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> 
> So this is the only patch in this series that is still needed.  However...
> 
> It doesn't seem like this all by itself is ready for mainline as we'll
> suddenly start putting all powerdomains in retention without any
> additional support.
>
> I guess at a minimum it needs working IO wakeup support from the IO
> daisy chain series.  Are there other dependencies here?

Only IO chain is needed for wakeup capability. Actually even with the
current mainline kernel, I am unable to wake-up the device from MPU
retention, as there are no wakeup sources. So this patch doesn't really
change the behavior to worse even without any additional patches. :) But
yea, good to wait until IO chain is in.

The other dependencies are that the stuff handled by patches 2,3 and 4
have to be handled somehow:

-patch2: must be in (this patch is queued by Paul)
-patch3: will be taken care of by Paul's pwrdm fixes (I guess this is
queued by Paul himself already)
-patch4: OMAP interrupt count must be increased (this is handled by
Benoit's patch, which is queued by Tony)

-Tero

> 
> If not, I can queue this when Paul is ready to merge the IO wakeup
> stuff.
> 
> Kevin
> 
> > ---
> >  arch/arm/mach-omap2/pm44xx.c |    6 ------
> >  1 files changed, 0 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> > index c264ef7..1ab30a3 100644
> > --- a/arch/arm/mach-omap2/pm44xx.c
> > +++ b/arch/arm/mach-omap2/pm44xx.c
> > @@ -151,12 +151,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
> >  	if (!strncmp(pwrdm->name, "cpu", 3))
> >  		return 0;
> >  
> > -	/*
> > -	 * FIXME: Remove this check when core retention is supported
> > -	 * Only MPUSS power domain is added in the list.
> > -	 */
> > -	if (strcmp(pwrdm->name, "mpu_pwrdm"))
> > -		return 0;
> >  
> >  	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
> >  	if (!pwrst)




From t-kristo at ti.com  Tue Mar  6 03:41:21 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 10:41:21 +0200
Subject: [PATCHv4 2/6] ARM: OMAP3 PM: Move IO Daisychain function to
 omap3 prm file
In-Reply-To: <4F55A80E.3090606@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-3-git-send-email-t-kristo@ti.com>
 <20120306054443.GA5670@kobold>  <4F55A80E.3090606@ti.com>
Message-ID: <1331023281.2116.145.camel@sokoban>

On Tue, 2012-03-06 at 11:30 +0530, Rajendra Nayak wrote:
> On Tuesday 06 March 2012 11:14 AM, Nishanth Menon wrote:
> > On 17:17-20120302, Tero Kristo wrote:
> >> From: Vishwanath BS<vishwanath.bs at ti.com>
> >>
> >> Since IO Daisychain modifies only PRM registers, it makes sense to move
> >> it to PRM File. Also changed the timeout value for IO chain enable to
> >> 100us and added a wait for status disable at the end.
> >>
> > [...]
> >> +/*
> >> + * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
> >> + * the I/O ring after asserting WUCLKIN high
> >> + */
> >> +#define MAX_IOPAD_LATCH_TIME 100
> >> +
> >> +/* OMAP3 Daisychain enable sequence */
> >> +void omap3_trigger_io_chain(void)
> >> +{
> >> +	int i = 0;
> >> +
> >> +	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> >> +				   PM_WKEN);
> >> +	/* Do a readback to assure write has been done */
> >> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
> >> +
> >> +	omap_test_timeout(((omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST)&
> >> +			    OMAP3430_ST_IO_CHAIN_MASK) == 1),
> > umm
> > arch/arm/mach-omap2/prm-regbits-34xx.h:#define OMAP3430_ST_IO_CHAIN_MASK
> > (1<<  16)
> > (reg&  (1<<  16)) == 1
> > will ever be true?
> 
> good catch. Its should actually be '((reg & (1 << 16)) >> 16) == 1'
> This is fixed in the omap4_trigger_io() function, looks like is missed
> here.

I'll fix this for next version.

-Tero



From rnayak at ti.com  Tue Mar  6 03:43:05 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 06 Mar 2012 14:13:05 +0530
Subject: [PATCHv3 1/4] ARM: OMAP4: suspend: Program all domains to
 retention
In-Reply-To: <1331022713.2116.144.camel@sokoban>
References: <1330529106-10423-1-git-send-email-t-kristo@ti.com>	
 <1330529106-10423-2-git-send-email-t-kristo@ti.com> <871up6in50.fsf@ti.com>
 <1331022713.2116.144.camel@sokoban>
Message-ID: <4F55CE19.7000309@ti.com>

On Tuesday 06 March 2012 02:01 PM, Tero Kristo wrote:
> On Mon, 2012-03-05 at 16:33 -0800, Kevin Hilman wrote:
>> Tero Kristo<t-kristo at ti.com>  writes:
>>
>>> From: Rajendra Nayak<rnayak at ti.com>
>>>
>>> Remove the FIXME's in the suspend sequence since
>>> we now intend to support system level RET support.
>>>
>>> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
>>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
>>> Reviewed-by: Santosh Shilimkar<santosh.shilimkar at ti.com>
>>
>> So this is the only patch in this series that is still needed.  However...
>>
>> It doesn't seem like this all by itself is ready for mainline as we'll
>> suddenly start putting all powerdomains in retention without any
>> additional support.
>>
>> I guess at a minimum it needs working IO wakeup support from the IO
>> daisy chain series.  Are there other dependencies here?
>
> Only IO chain is needed for wakeup capability. Actually even with the
> current mainline kernel, I am unable to wake-up the device from MPU
> retention, as there are no wakeup sources. So this patch doesn't really

Why?, doesn't debug console wakeup work?

> change the behavior to worse even without any additional patches. :) But
> yea, good to wait until IO chain is in.

IO chain, according to documentation :) should be needed only if you
hit OSWR or OFF, async wakeups should be functional as long as you
only hit CSWR.

>
> The other dependencies are that the stuff handled by patches 2,3 and 4
> have to be handled somehow:
>
> -patch2: must be in (this patch is queued by Paul)
> -patch3: will be taken care of by Paul's pwrdm fixes (I guess this is
> queued by Paul himself already)
> -patch4: OMAP interrupt count must be increased (this is handled by
> Benoit's patch, which is queued by Tony)
>
> -Tero
>
>>
>> If not, I can queue this when Paul is ready to merge the IO wakeup
>> stuff.
>>
>> Kevin
>>
>>> ---
>>>   arch/arm/mach-omap2/pm44xx.c |    6 ------
>>>   1 files changed, 0 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
>>> index c264ef7..1ab30a3 100644
>>> --- a/arch/arm/mach-omap2/pm44xx.c
>>> +++ b/arch/arm/mach-omap2/pm44xx.c
>>> @@ -151,12 +151,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
>>>   	if (!strncmp(pwrdm->name, "cpu", 3))
>>>   		return 0;
>>>
>>> -	/*
>>> -	 * FIXME: Remove this check when core retention is supported
>>> -	 * Only MPUSS power domain is added in the list.
>>> -	 */
>>> -	if (strcmp(pwrdm->name, "mpu_pwrdm"))
>>> -		return 0;
>>>
>>>   	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
>>>   	if (!pwrst)
>
>



From t-kristo at ti.com  Tue Mar  6 03:44:16 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 10:44:16 +0200
Subject: [PATCHv4 4/6] ARM: OMAP3+: PRM: Enable IO wake up
In-Reply-To: <4F5598E3.4050506@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-5-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203052001240.6649@utopia.booyaka.com>
 <4F55978C.7030407@ti.com>  <4F5598E3.4050506@ti.com>
Message-ID: <1331023456.2116.148.camel@sokoban>

On Tue, 2012-03-06 at 10:26 +0530, Rajendra Nayak wrote:
> On Tuesday 06 March 2012 10:20 AM, Rajendra Nayak wrote:
> > On Tuesday 06 March 2012 09:51 AM, Paul Walmsley wrote:
> >> added Rajendra, Nilesh, Vishwa, Mohan
> >>
> >> Hi
> >>
> >> On Fri, 2 Mar 2012, Tero Kristo wrote:
> >>
> >>> Enable IO Wake up for OMAP3/4 as part of PRM Init. Currently this has
> >>> been
> >>> managed in cpuidle path which is not the right place. Subsequent patch
> >>> will remove IO Daisy chain handling in cpuidle path once daisy chain is
> >>> handled as part of hwmod mux. This patch also moves the OMAP4 IO wakeup
> >>> enable code from the trigger function to init time setup.
> >>>
> >>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
> >>
> >> Should we keep the I/O wakeups enabled all the time?
> >>
> >> Seems like that could result in at least one spurious wake-up event --
> >> and
> >> thus a PRCM interrupt -- for each I/O pad that has WAKEUPENABLE set.
> >> Seems like these interrupts could recur every time the I/O chain is
> >> reset.
> >> And that the I/O chain is now reset in every hwmod idle and enable
> >> operation for an IP block that contains dynamic mux data?
> >>
> >> Thinking about the problem na?vely... maybe you all can think through
> >> this
> >> with me:
> >>
> >> Consider an IP block 'A' that has a signal (like the UART rx_irrx signal)
> >> that's mux'ed to a pad with WAKEUPENABLE set. (Some examples of 'A' might
> >> include a UART, a GPIO, or a McBSP.)
> >>
> >> Shouldn't we enable I/O wakeups (by setting EN_IO/GLOBAL_WUEN) only
> >> immediately before the powerdomain containing IP block 'A' is going to
> >> transition into RETENTION or OFF?
> >
> > Hi Paul,
> >
> > I completely agree with your observations and we knew we would have
> > additional wakeups with this design. Like I mentioned in the other
> > thread, we went ahead with this approach knowing we need to optimize
> > with some kind of powerdomain level usecounting in the future, because
> > it didn't exist back then when we did it this way.
> > But now that we already have it, maybe we can fix this and do
> > it such that we completely avoid an additional wakeup interrupt.
> >
> >>
> >> If we do that, then we can avoid needlessly resetting the I/O chain
> >> when a
> >> powerdomain is not going to go into a low-power state.
> >>
> >> I haven't measured the time it takes for the I/O chain to be reset.
> >> Maybe one of you have. But that 100 microsecond timeout that was
> >> specified in two of the other patches in this series has me a little
> >> worried.
> >
> > I haven't profiled it myself but I am guessing the delay isn't much.
> 
> Having said that, I do agree with you that, however small the delay,
> we end up doing needless IO trigger when the powerdomain isn't
> really entering a low power state.

I did some measurements on this a while back and the delay was around a
few microseconds. I can redo this while doing version 5.

-Tero

> 
> > The 100us comes from the fact that there is no documentation on the
> > exact delay, so went around asking whats the *real worst case* delay,
> > and we got an answer, 100us should be really big enough :)
> >
> > regards,
> > Rajendra
> >
> >>
> >>
> >> - Paul
> >
> 




From mad_soft at inbox.ru  Tue Mar  6 03:45:42 2012
From: mad_soft at inbox.ru (Dmitry Artamonow)
Date: Tue,  6 Mar 2012 12:45:42 +0400
Subject: [PATCH/RFC 1/2] arm/tegra: fix harmony pinmux for PCIe
In-Reply-To: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>
References: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>
Message-ID: <1331023544-6439-2-git-send-email-mad_soft@inbox.ru>

Commit 6e96aca397 (arm/tegra: Harmony PCIe: Don't touch pinmux)
removed runtime tri-state toggling for PCIe related pinmux groups,
but it seems that the fact that all of them are tri-state by default
has been overlooked. Change defaults for these groups to TEGRA_TRI_NORMAL.

Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>
---
 arch/arm/mach-tegra/board-harmony-pinmux.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 465808c..1af85bccc 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -53,7 +53,7 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
@@ -112,10 +112,10 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-- 
1.7.5.1.300.gc565c



From mad_soft at inbox.ru  Tue Mar  6 03:45:41 2012
From: mad_soft at inbox.ru (Dmitry Artamonow)
Date: Tue,  6 Mar 2012 12:45:41 +0400
Subject: [PATCH/RFC 0/2] Couple of Tegra2 PCIe fixes(?)
Message-ID: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>

These are more of RFC, because I can't test if 1/2 is really fixes anything,
and not sure how much 2/2 is needed - maybe error it fixes happens just in
my setup (and also I'm not sure if 2 seconds is a good value for timeout,
because I have no idea, how much time it takes for PLL to lock when everything)
But anyway...

While trying to make PCIe work on Harmony board, I've noticed
that pinmux groups for PCIe related signals are tristated, which 
looked suspicious. So I fixed that - that's the patch 1/2.

Sadly, even with this fix and 3.3v regulator patch[1] applied, PCIe still
doesn't work for me. Usually driver just loops infinitely in PLL lock
waiting code (that was the reason for writing patch 2/2 in this
mini-series). Couple of times I observed that after about 20-30 seconds of
waiting it passed PLL lock test and continue further, but then it failed to
detect a link with PCIe card. And I can't even reproduce this anymore.

Does anyone have working PCIe on Harmony? Can you please share the details
of your setup - what bootloader are you using, which version of kernel,
some additional patches maybe? Is there some secret tricks which are needed?
I've tried several combinations of different kernels and bootloaders, but
still can't find even a one which works.

[1] http://www.spinics.net/lists/linux-tegra/msg04148.html

Dmitry Artamonow (2):
  arm/tegra: fix harmony pinmux for PCIe
  arm/tegra: add timeout to PCIe PLL lock detection loop

 arch/arm/mach-tegra/board-harmony-pinmux.c |    6 +++---
 arch/arm/mach-tegra/pcie.c                 |   14 +++++++++++---
 2 files changed, 14 insertions(+), 6 deletions(-)

-- 
1.7.5.1.300.gc565c



From mad_soft at inbox.ru  Tue Mar  6 03:45:43 2012
From: mad_soft at inbox.ru (Dmitry Artamonow)
Date: Tue,  6 Mar 2012 12:45:43 +0400
Subject: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop
In-Reply-To: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>
References: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>
Message-ID: <1331023544-6439-3-git-send-email-mad_soft@inbox.ru>

Tegra PCIe driver waits for PLL to lock using busy loop.
If PLL fails to lock for some reason, this leads to silent lockup
while booting (as PCIe code is not modular).

Fix by adding timeout, so if PLL doesn't lock in a couple
of seconds, just PCIe driver fails and machine continues to boot.

Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>
---
 arch/arm/mach-tegra/pcie.c |   14 +++++++++++---
 1 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 14b29ab..ffdfdd4 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
 	afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
 	u32 val, reg;
-	int i;
+	int i, timeout;
 
 	/* Enable slot clock and pulse the reset signals */
 	for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
+	timeout = 2000;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
+		mdelay(1);
+		if (--timeout == 0) {
+			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+			return -EBUSY;
+		}
 	} while (!(val & PADS_PLL_CTL_LOCKDET));
 
 	/* turn off IDDQ override */
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
 	if (err)
 		return err;
 
-	tegra_pcie_enable_controller();
+	err = tegra_pcie_enable_controller();
+	if (err)
+		return err;
 
 	/* setup the AFI address translations */
 	tegra_pcie_setup_translations();
-- 
1.7.5.1.300.gc565c



From grinberg at compulab.co.il  Tue Mar  6 03:46:19 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Tue, 06 Mar 2012 10:46:19 +0200
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <1330989122-6323-1-git-send-email-paul.gortmaker@windriver.com>
References: <1330989122-6323-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <4F55CEDB.90909@compulab.co.il>

Also Cc: Haojian Zhuang <haojian.zhuang at marvell.com>

On 03/06/12 01:12, Paul Gortmaker wrote:
> Commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)
> 
>   "regulator: Remove support for supplies specified by struct device"
> 
> caused this file to break, since it was still relying on the
> device field to be present.  Strip them out here too.
> 
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> CC: Mark Brown <broonie at opensource.wolfsonmicro.com>

You've missed the scissors line:
---

The patch itself:

Acked-by: Igor Grinberg <grinberg at compulab.co.il>

Thanks

> 
> diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
> index d80c0ba..c8f3293 100644
> --- a/arch/arm/mach-pxa/em-x270.c
> +++ b/arch/arm/mach-pxa/em-x270.c
> @@ -1083,20 +1083,19 @@ static void __init em_x270_userspace_consumers_init(void)
>  }
>  
>  /* DA9030 related initializations */
> -#define REGULATOR_CONSUMER(_name, _dev, _supply)			       \
> +#define REGULATOR_CONSUMER(_name, _supply)			       \
>  	static struct regulator_consumer_supply _name##_consumers[] = {	\
>  		{							\
> -			.dev = _dev,					\
>  			.supply = _supply,				\
>  		},							\
>  	}
>  
> -REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps");
> -REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
> -REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
> -REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
> -REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
> -REGULATOR_CONSUMER(buck2, NULL, "vcc_core");
> +REGULATOR_CONSUMER(ldo3, "vcc gps");
> +REGULATOR_CONSUMER(ldo5, "vcc cam");
> +REGULATOR_CONSUMER(ldo10, "vcc sdio");
> +REGULATOR_CONSUMER(ldo12, "vcc usb");
> +REGULATOR_CONSUMER(ldo19, "vcc gprs");
> +REGULATOR_CONSUMER(buck2, "vcc_core");
>  
>  #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask)		\
>  	static struct regulator_init_data _ldo##_data = {		\

-- 
Regards,
Igor.


From t-kristo at ti.com  Tue Mar  6 03:51:50 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 10:51:50 +0200
Subject: [PATCHv4 5/6] ARM: OMAP3PLUS PM: Add IO Daisychain support via
 hwmod mux
In-Reply-To: <4F5590D6.8030707@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-6-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203052057050.6649@utopia.booyaka.com>
 <4F5590D6.8030707@ti.com>
Message-ID: <1331023910.2116.155.camel@sokoban>

On Tue, 2012-03-06 at 09:51 +0530, Rajendra Nayak wrote:
> Hi Paul,
> 
> On Tuesday 06 March 2012 09:32 AM, Paul Walmsley wrote:
> > Hi
> >
> > a few comments:
> >
> > On Fri, 2 Mar 2012, Tero Kristo wrote:
> >
> >> From: Vishwanath BS<vishwanath.bs at ti.com>
> >>
> >> IO Daisychain feature has to be triggered whenever there is a change in
> >> device's mux configuration (See section 3.9.4 in OMAP4 Public TRM vP).
> >>
> >> Now devices can idle independent of the powerdomain, there can be a
> >> window where device is idled and corresponding powerdomain can be
> >> ON/INACTIVE state. In such situations, since both module wake up is
> >> enabled at padlevel as well as io daisychain sequence is triggered,
> >> there will be 2 PRCM interrupts (Module async wake up via swakeup and
> >> IO Pad interrupt). But as PRCM Interrupt handler clears the Module
> >> Padlevel WKST bit in the first interrupt, module specific interrupt
> >> handler will not triggered for the second time
> >>
> >> Also look at detailed explanation given by Rajendra at
> >> http://www.spinics.net/lists/linux-serial/msg04480.html
> >>
> >> Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com>
> >> Signed-off-by: Tero Kristo<t-kristo at ti.com>
> >> ---
> >>   arch/arm/mach-omap2/omap_hwmod.c |    9 +++++++--
> >>   arch/arm/mach-omap2/pm.c         |   15 +++++++++++++++
> >>   arch/arm/mach-omap2/pm.h         |    1 +
> >>   3 files changed, 23 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> >> index 5192cab..56adbfb 100644
> >> --- a/arch/arm/mach-omap2/omap_hwmod.c
> >> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> >
> > ...
> >
> >> @@ -1535,8 +1536,10 @@ static int _enable(struct omap_hwmod *oh)
> >>   	/* Mux pins for device runtime if populated */
> >>   	if (oh->mux&&  (!oh->mux->enabled ||
> >>   			((oh->_state == _HWMOD_STATE_IDLE)&&
> >> -			 oh->mux->pads_dynamic)))
> >> +			 oh->mux->pads_dynamic))) {
> >>   		omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
> >> +		omap_trigger_io_chain();
> >
> > Looks racy: if two hwmods with dynamic mux entries go idle at the same
> > time, or one goes idle while another one is enabled, won't the calls to
> > omap_trigger_io_chain() race?  Locking is per-hwmod and there's no locking
> > in omap_trigger_io_chain() or the functions it calls.
> 
> I agree, this needs locking to avoid races.

I'll add one for v5.

> 
> >
> > Also, won't this result in needless resets of the I/O chain?  Seems like
> > we'd only need to do this when the next power state of the enclosing
> > powerdomain will enter either RETENTION or OFF.  And even then, it
> > presumably should only happen when the last active device in that
> > powerdomain is going idle?
> 
> Yes, the module async wakeups will work as long as the power domain
> enclosing the module is not in OSWR or OFF, so ideally this trigger
> should happen only when all modules in the given powerdomain are
> disabled and we plan to program the Powerdomain down to OSWR or
> OFF state. With what we are doing today we end up with periods when we
> have multiple wakeups (a module wakeup as well as an IO wakeup).
> The last we discussed this with Kevin, there wasn't a better place where
> we could trigger this, with no usecounting at powerdomain level you
> didn't know when the last active device in the powerdomain was going
> idle.
> But now with Tero's series which adds usecounting at power/voltage
> domain level, maybe its possible, but I need to look more.
> Do you already have an idea on where this would fit better, so we
> avoid this multiple wakeup scenario?

This should be easy, we can add a hook at the pwrdm_clkdm_enable /
disable calls to check against idle / active states. However, seeing the
acceptance status for the usecounting series, we probably have to just
go ahead with the extra latency involved iochain series and make
optimizations later once the usecounting can be accepted.

Speaking of the usecounting series, Paul, did you have any time to look
at it? Also, there are still some issues seen by Kevin on that series
with omap3430 which I am unable to reproduce (I posted a couple of trial
patches for taking care of that but don't know how they behave.)

-Tero




From stigge at antcom.de  Tue Mar  6 03:53:45 2012
From: stigge at antcom.de (Roland Stigge)
Date: Tue, 06 Mar 2012 09:53:45 +0100
Subject: [PATCH v4] lpc32xx: Added ethernet driver
In-Reply-To: <1330987524.2538.61.camel@bwh-desktop>
References: <1330983641-32622-1-git-send-email-stigge@antcom.de>
 <1330987524.2538.61.camel@bwh-desktop>
Message-ID: <4F55D099.5070006@antcom.de>

Hi Ben,

thank you for your review!

On 03/05/2012 11:45 PM, Ben Hutchings wrote:
> [...]
>> +static int lpc_eth_poll(struct napi_struct *napi, int budget)
>> +{
>> +	struct netdata_local *pldat = container_of(napi,
>> +			struct netdata_local, napi);
>> +	struct net_device *ndev = pldat->ndev;
>> +	unsigned long flags;
>> +	int rx_done = 0;
>> +
>> +	spin_lock_irqsave(&pldat->lock, flags);
>> +
>> +	__lpc_handle_xmit(ndev);
>> +	rx_done = __lpc_handle_recv(ndev, budget);
>> +
>> +	if (rx_done < budget) {
>> +		napi_complete(napi);
>> +		lpc_eth_enable_int(pldat->net_base);
>> +	}
>> +
>> +	spin_unlock_irqrestore(&pldat->lock, flags);
>
> This is really sad.  You implement NAPI but then take away most of the
> benefits of that by disabling interrupts.
>
> It looks like you could safely unlock pldat->lock before calling
> __lpc_handle_recv - nothing else manipulates RX queue state so no lock
> is required.
>
> As for the TX side, you can probably use the TX queue lock
> (__netif_tx_lock, __netif_tx_unlock) to serialise with
> lpc_eth_hard_start_xmit() and avoid taking pldat->lock in either
> __lpc_handle_xmit() or here.

Sounds reasonable, and will do it.

However, I implemented it from the example of
drivers/net/ethernet/via/via-velocity.c:velocity_poll() - is there a
good reason for doing it that way in the velocity driver or is it done
incorrectly there, also?

Thanks,

Roland


From t-kristo at ti.com  Tue Mar  6 03:54:08 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 10:54:08 +0200
Subject: [PATCHv3 1/4] ARM: OMAP4: suspend: Program all domains to
 retention
In-Reply-To: <4F55CE19.7000309@ti.com>
References: <1330529106-10423-1-git-send-email-t-kristo@ti.com>
 <1330529106-10423-2-git-send-email-t-kristo@ti.com> <871up6in50.fsf@ti.com>
 <1331022713.2116.144.camel@sokoban> <4F55CE19.7000309@ti.com>
Message-ID: <1331024048.2116.157.camel@sokoban>

On Tue, 2012-03-06 at 14:13 +0530, Rajendra Nayak wrote:
> On Tuesday 06 March 2012 02:01 PM, Tero Kristo wrote:
> > On Mon, 2012-03-05 at 16:33 -0800, Kevin Hilman wrote:
> >> Tero Kristo<t-kristo at ti.com>  writes:
> >>
> >>> From: Rajendra Nayak<rnayak at ti.com>
> >>>
> >>> Remove the FIXME's in the suspend sequence since
> >>> we now intend to support system level RET support.
> >>>
> >>> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
> >>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
> >>> Reviewed-by: Santosh Shilimkar<santosh.shilimkar at ti.com>
> >>
> >> So this is the only patch in this series that is still needed.  However...
> >>
> >> It doesn't seem like this all by itself is ready for mainline as we'll
> >> suddenly start putting all powerdomains in retention without any
> >> additional support.
> >>
> >> I guess at a minimum it needs working IO wakeup support from the IO
> >> daisy chain series.  Are there other dependencies here?
> >
> > Only IO chain is needed for wakeup capability. Actually even with the
> > current mainline kernel, I am unable to wake-up the device from MPU
> > retention, as there are no wakeup sources. So this patch doesn't really
> 
> Why?, doesn't debug console wakeup work?

At least I couldn't get it to work. I tried with no_console_suspend
kernel param to no avail. Don't know if I was missing something else.

-Tero

> 
> > change the behavior to worse even without any additional patches. :) But
> > yea, good to wait until IO chain is in.
> 
> IO chain, according to documentation :) should be needed only if you
> hit OSWR or OFF, async wakeups should be functional as long as you
> only hit CSWR.
> 
> >
> > The other dependencies are that the stuff handled by patches 2,3 and 4
> > have to be handled somehow:
> >
> > -patch2: must be in (this patch is queued by Paul)
> > -patch3: will be taken care of by Paul's pwrdm fixes (I guess this is
> > queued by Paul himself already)
> > -patch4: OMAP interrupt count must be increased (this is handled by
> > Benoit's patch, which is queued by Tony)
> >
> > -Tero
> >
> >>
> >> If not, I can queue this when Paul is ready to merge the IO wakeup
> >> stuff.
> >>
> >> Kevin
> >>
> >>> ---
> >>>   arch/arm/mach-omap2/pm44xx.c |    6 ------
> >>>   1 files changed, 0 insertions(+), 6 deletions(-)
> >>>
> >>> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> >>> index c264ef7..1ab30a3 100644
> >>> --- a/arch/arm/mach-omap2/pm44xx.c
> >>> +++ b/arch/arm/mach-omap2/pm44xx.c
> >>> @@ -151,12 +151,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
> >>>   	if (!strncmp(pwrdm->name, "cpu", 3))
> >>>   		return 0;
> >>>
> >>> -	/*
> >>> -	 * FIXME: Remove this check when core retention is supported
> >>> -	 * Only MPUSS power domain is added in the list.
> >>> -	 */
> >>> -	if (strcmp(pwrdm->name, "mpu_pwrdm"))
> >>> -		return 0;
> >>>
> >>>   	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
> >>>   	if (!pwrst)
> >
> >
> 




From peter.ujfalusi at ti.com  Tue Mar  6 03:55:33 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue,  6 Mar 2012 10:55:33 +0200
Subject: [PATCH] ARM: OMAP4: clock: Add aliases for McBSP fclk clocks
Message-ID: <1331024133-18201-1-git-send-email-peter.ujfalusi@ti.com>

CLKS signal for McBSP ports can be selected from internal (PRCM) or external
(ABE_CLKS pin) source.
To be able to use existing code we need to create clock aliases consistent
among OMAP2/3/4.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---

Hi,

this patch should fix the clock reparenting on OMAP4 for McBSP ports.

Regards,
Peter

 arch/arm/mach-omap2/clock44xx_data.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 08e86d7..7e76ac3 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3120,6 +3120,10 @@ static struct clk auxclkreq5_ck = {
 static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"extalt_clkin_ck",		&extalt_clkin_ck,	CK_443X),
 	CLK(NULL,	"pad_clks_ck",			&pad_clks_ck,	CK_443X),
+	CLK("omap-mcbsp.1",	"pad_fck",		&pad_clks_ck,	CK_443X),
+	CLK("omap-mcbsp.2",	"pad_fck",		&pad_clks_ck,	CK_443X),
+	CLK("omap-mcbsp.3",	"pad_fck",		&pad_clks_ck,	CK_443X),
+	CLK("omap-mcbsp.4",	"pad_fck",		&pad_clks_ck,	CK_443X),
 	CLK(NULL,	"pad_slimbus_core_clks_ck",	&pad_slimbus_core_clks_ck,	CK_443X),
 	CLK(NULL,	"secure_32k_clk_src_ck",	&secure_32k_clk_src_ck,	CK_443X),
 	CLK(NULL,	"slimbus_clk",			&slimbus_clk,	CK_443X),
@@ -3254,12 +3258,16 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"mcasp_sync_mux_ck",		&mcasp_sync_mux_ck,	CK_443X),
 	CLK(NULL,	"mcasp_fck",			&mcasp_fck,	CK_443X),
 	CLK(NULL,	"mcbsp1_sync_mux_ck",		&mcbsp1_sync_mux_ck,	CK_443X),
+	CLK("omap-mcbsp.1",	"prcm_fck",		&mcbsp1_sync_mux_ck,	CK_443X),
 	CLK(NULL,	"mcbsp1_fck",			&mcbsp1_fck,	CK_443X),
 	CLK(NULL,	"mcbsp2_sync_mux_ck",		&mcbsp2_sync_mux_ck,	CK_443X),
+	CLK("omap-mcbsp.2",	"prcm_fck",		&mcbsp2_sync_mux_ck,	CK_443X),
 	CLK(NULL,	"mcbsp2_fck",			&mcbsp2_fck,	CK_443X),
 	CLK(NULL,	"mcbsp3_sync_mux_ck",		&mcbsp3_sync_mux_ck,	CK_443X),
+	CLK("omap-mcbsp.3",	"prcm_fck",		&mcbsp3_sync_mux_ck,	CK_443X),
 	CLK(NULL,	"mcbsp3_fck",			&mcbsp3_fck,	CK_443X),
 	CLK(NULL,	"mcbsp4_sync_mux_ck",		&mcbsp4_sync_mux_ck,	CK_443X),
+	CLK("omap-mcbsp.4",	"prcm_fck",		&mcbsp4_sync_mux_ck,	CK_443X),
 	CLK(NULL,	"mcbsp4_fck",			&mcbsp4_fck,	CK_443X),
 	CLK(NULL,	"mcpdm_fck",			&mcpdm_fck,	CK_443X),
 	CLK(NULL,	"mcspi1_fck",			&mcspi1_fck,	CK_443X),
-- 
1.7.8.5



From rnayak at ti.com  Tue Mar  6 03:59:02 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 06 Mar 2012 14:29:02 +0530
Subject: [PATCHv3 1/4] ARM: OMAP4: suspend: Program all domains to
 retention
In-Reply-To: <1331024048.2116.157.camel@sokoban>
References: <1330529106-10423-1-git-send-email-t-kristo@ti.com>	
 <1330529106-10423-2-git-send-email-t-kristo@ti.com> <871up6in50.fsf@ti.com>	
 <1331022713.2116.144.camel@sokoban> <4F55CE19.7000309@ti.com>
 <1331024048.2116.157.camel@sokoban>
Message-ID: <4F55D1D6.80909@ti.com>

On Tuesday 06 March 2012 02:24 PM, Tero Kristo wrote:
> On Tue, 2012-03-06 at 14:13 +0530, Rajendra Nayak wrote:
>> On Tuesday 06 March 2012 02:01 PM, Tero Kristo wrote:
>>> On Mon, 2012-03-05 at 16:33 -0800, Kevin Hilman wrote:
>>>> Tero Kristo<t-kristo at ti.com>   writes:
>>>>
>>>>> From: Rajendra Nayak<rnayak at ti.com>
>>>>>
>>>>> Remove the FIXME's in the suspend sequence since
>>>>> we now intend to support system level RET support.
>>>>>
>>>>> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
>>>>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
>>>>> Reviewed-by: Santosh Shilimkar<santosh.shilimkar at ti.com>
>>>>
>>>> So this is the only patch in this series that is still needed.  However...
>>>>
>>>> It doesn't seem like this all by itself is ready for mainline as we'll
>>>> suddenly start putting all powerdomains in retention without any
>>>> additional support.
>>>>
>>>> I guess at a minimum it needs working IO wakeup support from the IO
>>>> daisy chain series.  Are there other dependencies here?
>>>
>>> Only IO chain is needed for wakeup capability. Actually even with the
>>> current mainline kernel, I am unable to wake-up the device from MPU
>>> retention, as there are no wakeup sources. So this patch doesn't really
>>
>> Why?, doesn't debug console wakeup work?
>
> At least I couldn't get it to work. I tried with no_console_suspend
> kernel param to no avail. Don't know if I was missing something else.

Did you try enabling wakeup for the debug console?
echo enabled > /sys/devices/platform/omap/omap_uart.2/tty/ttyO2/power/wakeup

>
> -Tero
>
>>
>>> change the behavior to worse even without any additional patches. :) But
>>> yea, good to wait until IO chain is in.
>>
>> IO chain, according to documentation :) should be needed only if you
>> hit OSWR or OFF, async wakeups should be functional as long as you
>> only hit CSWR.
>>
>>>
>>> The other dependencies are that the stuff handled by patches 2,3 and 4
>>> have to be handled somehow:
>>>
>>> -patch2: must be in (this patch is queued by Paul)
>>> -patch3: will be taken care of by Paul's pwrdm fixes (I guess this is
>>> queued by Paul himself already)
>>> -patch4: OMAP interrupt count must be increased (this is handled by
>>> Benoit's patch, which is queued by Tony)
>>>
>>> -Tero
>>>
>>>>
>>>> If not, I can queue this when Paul is ready to merge the IO wakeup
>>>> stuff.
>>>>
>>>> Kevin
>>>>
>>>>> ---
>>>>>    arch/arm/mach-omap2/pm44xx.c |    6 ------
>>>>>    1 files changed, 0 insertions(+), 6 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
>>>>> index c264ef7..1ab30a3 100644
>>>>> --- a/arch/arm/mach-omap2/pm44xx.c
>>>>> +++ b/arch/arm/mach-omap2/pm44xx.c
>>>>> @@ -151,12 +151,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
>>>>>    	if (!strncmp(pwrdm->name, "cpu", 3))
>>>>>    		return 0;
>>>>>
>>>>> -	/*
>>>>> -	 * FIXME: Remove this check when core retention is supported
>>>>> -	 * Only MPUSS power domain is added in the list.
>>>>> -	 */
>>>>> -	if (strcmp(pwrdm->name, "mpu_pwrdm"))
>>>>> -		return 0;
>>>>>
>>>>>    	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
>>>>>    	if (!pwrst)
>>>
>>>
>>
>
>



From linux at arm.linux.org.uk  Tue Mar  6 03:59:39 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 08:59:39 +0000
Subject: [PATCH 6/9] dmaengine: consolidate tx_status functions
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F001F41FF555BD@AUSP01VMBX24.collaborationhost.net>
References: <20120305201411.GA17791@n2100.arm.linux.org.uk>
 <E1S4eKz-0000tE-FB@rmk-PC.arm.linux.org.uk>
 <ADE657CA350FB648AAC2C43247A983F001F41FF555BD@AUSP01VMBX24.collaborationhost.net>
Message-ID: <20120306085939.GC17370@n2100.arm.linux.org.uk>

On Mon, Mar 05, 2012 at 06:12:50PM -0600, H Hartley Sweeten wrote:
> On Monday, March 05, 2012 1:17 PM, Russell King wrote:
> > diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
> > index 47e0997..244a2c5 100644
> > --- a/drivers/dma/dmaengine.h
> > +++ b/drivers/dma/dmaengine.h
> > @@ -45,4 +45,35 @@ static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
> >  	tx->cookie = 0;
> >  }
> >  
> > +/**
> > + * dma_cookie_status - report cookie status
> > + * @chan: dma channel
> > + * @cookie: cookie we are interested in
> > + * @state: dma_tx_state structure to return last/used cookies
> > + *
> > + * Report the status of the cookie, filling in the state structure if
> > + * non-NULL.  No locking is required.
> > + */
> > +static inline enum dma_status dma_cookie_status(struct dma_chan *chan,
> > +	dma_cookie_t cookie, struct dma_tx_state *state)
> > +{
> > +	dma_cookie_t used, complete;
> > +
> > +	used = chan->cookie;
> > +	complete = chan->complete;
> > +	barrier();
> > +	if (state) {
> > +		state->last = complete;
> > +		state->used = used;
> > +		state->residue = 0;
> > +	}
> 
> Isn't this dma_set_tx_state()?

It's more than dma_set_tx_state().  It is my intention to get rid of
dma_set_tx_state() in favour of these implementations.

> > +	return dma_async_is_complete(cookie, complete, used);
> > +}
> 
> Regards,
> Hartley
> 


From govindraj.raja at ti.com  Tue Mar  6 04:03:16 2012
From: govindraj.raja at ti.com (Raja, Govindraj)
Date: Tue, 6 Mar 2012 14:33:16 +0530
Subject: [PATCH] omap3_beagle: Init only uart3 used for console
In-Reply-To: <12976EFB-912D-44E2-825C-63034F117635@dominion.thruhere.net>
References: <1330945952-14714-1-git-send-email-govindraj.raja@ti.com>
 <12976EFB-912D-44E2-825C-63034F117635@dominion.thruhere.net>
Message-ID: <CAMrsUdJfSeu8W+gS+HfDKw5WFXvaVK2TzXhqhr6tdRhujU18uQ@mail.gmail.com>

On Mon, Mar 5, 2012 at 7:36 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
>
> Op 5 mrt. 2012, om 12:12 heeft Govindraj.R het volgende geschreven:
>
>> From: "Govindraj.R" <govindraj.raja at ti.com>
>>
>> On beagle some of uart mux lines are used for other
>> purpose so init only uart3.
>>
>> Uart2 rx line clashes with gpio_147 used for usb ehci
>> phy reset. Initializing uart2 pad_mux lines can break
>> ehci module on beagle xm.
>> (gpio_147 is available on uart2_rx in mode4 reference
>> mux34xx.c -> uart2_rx.gpio_147)
>
> That's only on xM revision C, right?

Applicable to all beagle boards having external usb
hub (USB2HS_nRST will require uart2_rx.gpio_147)

Beagle Rev Ax/Bx doesn't seem to have external hub
module so not applicable for those boards

Will modify and post a new patch.

--
Thanks,
Govindraj.R


From govindraj.raja at ti.com  Tue Mar  6 04:05:11 2012
From: govindraj.raja at ti.com (Govindraj.R)
Date: Tue, 6 Mar 2012 14:35:11 +0530
Subject: [PATCH] omap3_beagle: init uart2 for beagle rev AX/BX only
Message-ID: <1331024711-23578-1-git-send-email-govindraj.raja@ti.com>

From: "Govindraj.R" <govindraj.raja at ti.com>

All beagle boards rev > AX/BX have external usb hubs connected to ehci
interface, external hub/peripheral uses a nreset sequence for which
uart2_rx.gpio_147 pin in mux mode4(USB2HS_nRST) is used on all beagle
boards expect rev Ax/BX.
(Reference to all beagle boards rev schematics:
http://beagleboard.org/hardware/design)

Initialising uart2 will lead to serial init taking over uart2_rx pin
so init uart2_rx pin mux only for Beagle AX/BX rev boards.
Dont init uart2 for all other boards allowing usb_ehci functionality.

To initialise individual uart port by id utilise and modify the existing
available func. omap_serial_board_init.

Cc: Tony Lindgren <tony at atomide.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Koen Kooi <koen at dominion.thruhere.net>
Tested-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Tested-by: Robert Nelson <robertcnelson at gmail.com>
Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
---
 arch/arm/mach-omap2/board-omap3beagle.c  |    6 +++-
 arch/arm/mach-omap2/serial.c             |   41 ++++++++++++++++-------------
 arch/arm/plat-omap/include/plat/serial.h |    3 +-
 3 files changed, 30 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7ffcd28..19d6fb5 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -126,6 +126,7 @@ static void __init omap3_beagle_init_rev(void)
 		beagle_config.mmc1_gpio_wp = 29;
 		beagle_config.reset_gpio = 170;
 		beagle_config.usr_button_gpio = 7;
+		omap_serial_board_init(NULL, 1);
 		break;
 	case 6:
 		printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n");
@@ -528,7 +529,10 @@ static void __init omap3_beagle_init(void)
 	platform_add_devices(omap3_beagle_devices,
 			ARRAY_SIZE(omap3_beagle_devices));
 	omap_display_init(&beagle_dss_data);
-	omap_serial_init();
+	omap_serial_board_init(NULL, 0);
+	omap_serial_board_init(NULL, 2);
+	omap_serial_board_init(NULL, 3);
+
 	omap_sdrc_init(mt46h32m32lf6_sdrc_params,
 				  mt46h32m32lf6_sdrc_params);
 
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index f590afc..e7c0462 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -393,30 +393,32 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
 /**
  * omap_serial_board_init() - initialize all supported serial ports
  * @info: platform specific data pointer
+ * @port_id: uart port number to be initialised
  *
- * Initializes all available UARTs as serial ports. Platforms
+ * Initializes individual UARTs as serial ports. Platforms
  * can call this function when they want to have default behaviour
- * for serial ports (e.g initialize them all as serial ports).
+ * for serial ports (e.g initialize individual serial ports based on port id).
  */
-void __init omap_serial_board_init(struct omap_uart_port_info *info)
+void __init omap_serial_board_init(struct omap_uart_port_info *info, u8 port_id)
 {
 	struct omap_uart_state *uart;
 	struct omap_board_data bdata;
 
-	list_for_each_entry(uart, &uart_list, node) {
-		bdata.id = uart->num;
-		bdata.flags = 0;
-		bdata.pads = NULL;
-		bdata.pads_cnt = 0;
-
-		if (cpu_is_omap44xx() || cpu_is_omap34xx())
-			omap_serial_fill_default_pads(&bdata);
-
-		if (!info)
-			omap_serial_init_port(&bdata, NULL);
-		else
-			omap_serial_init_port(&bdata, &info[uart->num]);
-	}
+	list_for_each_entry(uart, &uart_list, node)
+		if (uart->num == port_id) {
+			bdata.id = uart->num;
+			bdata.flags = 0;
+			bdata.pads = NULL;
+			bdata.pads_cnt = 0;
+
+			if (!cpu_is_omap24xx())
+				omap_serial_fill_default_pads(&bdata);
+
+			if (!info)
+				omap_serial_init_port(&bdata, NULL);
+			else
+				omap_serial_init_port(&bdata, info);
+		}
 }
 
 /**
@@ -428,5 +430,8 @@ void __init omap_serial_board_init(struct omap_uart_port_info *info)
  */
 void __init omap_serial_init(void)
 {
-	omap_serial_board_init(NULL);
+	struct omap_uart_state *uart;
+
+	list_for_each_entry(uart, &uart_list, node)
+		omap_serial_board_init(NULL, uart->num);
 }
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 198d1e6..043b251 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -111,7 +111,8 @@ struct omap_uart_port_info;
 
 extern void omap_serial_init(void);
 extern int omap_uart_can_sleep(void);
-extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
+extern void omap_serial_board_init(struct omap_uart_port_info *platform_data,
+		u8 port_id);
 extern void omap_serial_init_port(struct omap_board_data *bdata,
 		struct omap_uart_port_info *platform_data);
 #endif
-- 
1.7.5.4



From koen at dominion.thruhere.net  Tue Mar  6 04:10:13 2012
From: koen at dominion.thruhere.net (Koen Kooi)
Date: Tue, 6 Mar 2012 10:10:13 +0100
Subject: [PATCH] omap3_beagle: Init only uart3 used for console
In-Reply-To: <CAMrsUdJfSeu8W+gS+HfDKw5WFXvaVK2TzXhqhr6tdRhujU18uQ@mail.gmail.com>
References: <1330945952-14714-1-git-send-email-govindraj.raja@ti.com>
 <12976EFB-912D-44E2-825C-63034F117635@dominion.thruhere.net>
 <CAMrsUdJfSeu8W+gS+HfDKw5WFXvaVK2TzXhqhr6tdRhujU18uQ@mail.gmail.com>
Message-ID: <C67C8239-2E17-42E5-BEB4-2B7F623515B8@dominion.thruhere.net>


Op 6 mrt. 2012, om 10:03 heeft Raja, Govindraj het volgende geschreven:

> On Mon, Mar 5, 2012 at 7:36 PM, Koen Kooi <koen at dominion.thruhere.net> wrote:
>> 
>> Op 5 mrt. 2012, om 12:12 heeft Govindraj.R het volgende geschreven:
>> 
>>> From: "Govindraj.R" <govindraj.raja at ti.com>
>>> 
>>> On beagle some of uart mux lines are used for other
>>> purpose so init only uart3.
>>> 
>>> Uart2 rx line clashes with gpio_147 used for usb ehci
>>> phy reset. Initializing uart2 pad_mux lines can break
>>> ehci module on beagle xm.
>>> (gpio_147 is available on uart2_rx in mode4 reference
>>> mux34xx.c -> uart2_rx.gpio_147)
>> 
>> That's only on xM revision C, right?
> 
> Applicable to all beagle boards having external usb
> hub (USB2HS_nRST will require uart2_rx.gpio_147)

My apologies, I was confusing it with the DVI reset GPIO (which changed in between revisions) and the polarity of the USB pin (which changed during xM A -> C).

regards,

Koen

From govindraj.raja at ti.com  Tue Mar  6 04:10:57 2012
From: govindraj.raja at ti.com (Raja, Govindraj)
Date: Tue, 6 Mar 2012 14:40:57 +0530
Subject: [PATCH] omap3_beagle: Init only uart3 used for console
In-Reply-To: <87399mkecv.fsf@ti.com>
References: <1330945952-14714-1-git-send-email-govindraj.raja@ti.com>
 <87399mkecv.fsf@ti.com>
Message-ID: <CAMrsUdLWaLqSr-PCmmGxrp0qZSojr5EWAUYmuk6v2pHiVdf9kA@mail.gmail.com>

On Tue, Mar 6, 2012 at 1:30 AM, Kevin Hilman <khilman at ti.com> wrote:
> "Govindraj.R" <govindraj.raja at ti.com> writes:
>
>> From: "Govindraj.R" <govindraj.raja at ti.com>
>>
>> On beagle some of uart mux lines are used for other
>> purpose so init only uart3.
>
> OK, but you should also be clear that this patch is effectively
> disabling all UARTS (except UART3) by defatul, which I'm not sure all
> Beagle users will be happy about.
>

Okay, I have posted new version of the patch
"[PATCH] omap3_beagle: init uart2 for beagle rev AX/BX only"

which initialises uart1/3/4 on all beagle boards

and uart2 init is done for only beagle rev ax/bx
which doesn't seem to have external usb module.


>> Uart2 rx line clashes with gpio_147 used for usb ehci
>> phy reset. Initializing uart2 pad_mux lines can break
>> ehci module on beagle xm.
>> (gpio_147 is available on uart2_rx in mode4 reference
>> mux34xx.c -> uart2_rx.gpio_147)
>
> As Koen mentioned, this conflict only exists on certain boards, so
> you should be clear that this is just an example.
>

conflict exists all beagle rev's expect rev ax/bx.

--
Thanks,
Govindraj.R


From haojian.zhuang at gmail.com  Tue Mar  6 04:12:18 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 6 Mar 2012 17:12:18 +0800
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <4F55CEDB.90909@compulab.co.il>
References: <1330989122-6323-1-git-send-email-paul.gortmaker@windriver.com>
 <4F55CEDB.90909@compulab.co.il>
Message-ID: <CAN1soZxdT=N1BtK5Jf4+Qu3GGCHPuKK1BqgfEV-D7QorjnsLpg@mail.gmail.com>

On Tue, Mar 6, 2012 at 4:46 PM, Igor Grinberg <grinberg at compulab.co.il> wrote:
> Also Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
>
> On 03/06/12 01:12, Paul Gortmaker wrote:
>> Commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)
>>
>> ? "regulator: Remove support for supplies specified by struct device"
>>
>> caused this file to break, since it was still relying on the
>> device field to be present. ?Strip them out here too.
>>
>> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
>> CC: Mark Brown <broonie at opensource.wolfsonmicro.com>
>
> You've missed the scissors line:
> ---
>
> The patch itself:
>
> Acked-by: Igor Grinberg <grinberg at compulab.co.il>
>
> Thanks
>

Mark,

Could you pick up this patch since it's depend on latest change on regulator?

Best Regards
Haojian


From govindraj.raja at ti.com  Tue Mar  6 04:16:18 2012
From: govindraj.raja at ti.com (Raja, Govindraj)
Date: Tue, 6 Mar 2012 14:46:18 +0530
Subject: [PATCH] omap3_beagle: Init only uart3 used for console
In-Reply-To: <20120305205149.GS12083@atomide.com>
References: <1330945952-14714-1-git-send-email-govindraj.raja@ti.com>
 <87399mkecv.fsf@ti.com> <20120305205149.GS12083@atomide.com>
Message-ID: <CAMrsUdKAS7i1KiqU8pS7Dvt1j8uE7C-R4t=TyzxGkT3rbt6oag@mail.gmail.com>

On Tue, Mar 6, 2012 at 2:21 AM, Tony Lindgren <tony at atomide.com> wrote:
> * Kevin Hilman <khilman at ti.com> [120305 11:28]:
>> "Govindraj.R" <govindraj.raja at ti.com> writes:
>>
>> > From: "Govindraj.R" <govindraj.raja at ti.com>
>> >
>> > On beagle some of uart mux lines are used for other
>> > purpose so init only uart3.
>>
>> OK, but you should also be clear that this patch is effectively
>> disabling all UARTS (except UART3) by defatul, which I'm not sure all
>> Beagle users will be happy about.
>>
>> > Uart2 rx line clashes with gpio_147 used for usb ehci
>> > phy reset. Initializing uart2 pad_mux lines can break
>> > ehci module on beagle xm.
>> > (gpio_147 is available on uart2_rx in mode4 reference
>> > mux34xx.c -> uart2_rx.gpio_147)
>>
>> As Koen mentioned, this conflict only exists on certain boards, so
>> you should be clear that this is just an example.
>
> OK, thanks for the comments. Also it's a bit clear if
> this really is safe to do on all beagles.

I have clarified the same in reply to "Kevin Hilman" and "Koen Kooi"
in the same thread.

>
>> > Cc: Tony Lindgren <tony at atomide.com>
>> > Cc: Kevin Hilman <khilman at ti.com>
>> > Tested-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
>> > Tested-by: Robert Nelson <robertcnelson at gmail.com>
>> > Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
>>
>> [...]
>>
>> > +
>> > +static inline void board_serial_init(void)
>>
>> Should be __init
>>
>> [...]
>>
>> > +static inline void board_serial_init(void)
>>
>> here too.
>
> ..so dropping the patch for now until these are fixed
> and we have some tested-bys for non-xm beagles too.
>

Okay fine, I have new version of the patch
"[PATCH] omap3_beagle: init uart2 for beagle rev AX/BX only"

This patch shouldn't have any impact and should work on beagles.

--
Thanks,
Govindraj.R


From linux at arm.linux.org.uk  Tue Mar  6 04:16:48 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 09:16:48 +0000
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <4F5579F7.7040603@gmail.com>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201202281945.39419.arnd@arndb.de>
 <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
 <4F5579F7.7040603@gmail.com>
Message-ID: <20120306091648.GD17370@n2100.arm.linux.org.uk>

On Mon, Mar 05, 2012 at 08:44:07PM -0600, Rob Herring wrote:
> So, can we do this for 3.4 or should wait for 3.5?

I'd say wait, otherwise we're going to see delete/modify conflicts
which are a pain to deal with.


From t-kristo at ti.com  Tue Mar  6 04:23:53 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 11:23:53 +0200
Subject: [PATCHv3 1/4] ARM: OMAP4: suspend: Program all domains to
 retention
In-Reply-To: <4F55D1D6.80909@ti.com>
References: <1330529106-10423-1-git-send-email-t-kristo@ti.com>
 <1330529106-10423-2-git-send-email-t-kristo@ti.com> <871up6in50.fsf@ti.com>
 <1331022713.2116.144.camel@sokoban> <4F55CE19.7000309@ti.com>
 <1331024048.2116.157.camel@sokoban> <4F55D1D6.80909@ti.com>
Message-ID: <1331025833.2116.159.camel@sokoban>

On Tue, 2012-03-06 at 14:29 +0530, Rajendra Nayak wrote:
> On Tuesday 06 March 2012 02:24 PM, Tero Kristo wrote:
> > On Tue, 2012-03-06 at 14:13 +0530, Rajendra Nayak wrote:
> >> On Tuesday 06 March 2012 02:01 PM, Tero Kristo wrote:
> >>> On Mon, 2012-03-05 at 16:33 -0800, Kevin Hilman wrote:
> >>>> Tero Kristo<t-kristo at ti.com>   writes:
> >>>>
> >>>>> From: Rajendra Nayak<rnayak at ti.com>
> >>>>>
> >>>>> Remove the FIXME's in the suspend sequence since
> >>>>> we now intend to support system level RET support.
> >>>>>
> >>>>> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
> >>>>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
> >>>>> Reviewed-by: Santosh Shilimkar<santosh.shilimkar at ti.com>
> >>>>
> >>>> So this is the only patch in this series that is still needed.  However...
> >>>>
> >>>> It doesn't seem like this all by itself is ready for mainline as we'll
> >>>> suddenly start putting all powerdomains in retention without any
> >>>> additional support.
> >>>>
> >>>> I guess at a minimum it needs working IO wakeup support from the IO
> >>>> daisy chain series.  Are there other dependencies here?
> >>>
> >>> Only IO chain is needed for wakeup capability. Actually even with the
> >>> current mainline kernel, I am unable to wake-up the device from MPU
> >>> retention, as there are no wakeup sources. So this patch doesn't really
> >>
> >> Why?, doesn't debug console wakeup work?
> >
> > At least I couldn't get it to work. I tried with no_console_suspend
> > kernel param to no avail. Don't know if I was missing something else.
> 
> Did you try enabling wakeup for the debug console?
> echo enabled > /sys/devices/platform/omap/omap_uart.2/tty/ttyO2/power/wakeup

I think not, however I wonder why the wakeups are not enabled by default
if this helps?

> 
> >
> > -Tero
> >
> >>
> >>> change the behavior to worse even without any additional patches. :) But
> >>> yea, good to wait until IO chain is in.
> >>
> >> IO chain, according to documentation :) should be needed only if you
> >> hit OSWR or OFF, async wakeups should be functional as long as you
> >> only hit CSWR.
> >>
> >>>
> >>> The other dependencies are that the stuff handled by patches 2,3 and 4
> >>> have to be handled somehow:
> >>>
> >>> -patch2: must be in (this patch is queued by Paul)
> >>> -patch3: will be taken care of by Paul's pwrdm fixes (I guess this is
> >>> queued by Paul himself already)
> >>> -patch4: OMAP interrupt count must be increased (this is handled by
> >>> Benoit's patch, which is queued by Tony)
> >>>
> >>> -Tero
> >>>
> >>>>
> >>>> If not, I can queue this when Paul is ready to merge the IO wakeup
> >>>> stuff.
> >>>>
> >>>> Kevin
> >>>>
> >>>>> ---
> >>>>>    arch/arm/mach-omap2/pm44xx.c |    6 ------
> >>>>>    1 files changed, 0 insertions(+), 6 deletions(-)
> >>>>>
> >>>>> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> >>>>> index c264ef7..1ab30a3 100644
> >>>>> --- a/arch/arm/mach-omap2/pm44xx.c
> >>>>> +++ b/arch/arm/mach-omap2/pm44xx.c
> >>>>> @@ -151,12 +151,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
> >>>>>    	if (!strncmp(pwrdm->name, "cpu", 3))
> >>>>>    		return 0;
> >>>>>
> >>>>> -	/*
> >>>>> -	 * FIXME: Remove this check when core retention is supported
> >>>>> -	 * Only MPUSS power domain is added in the list.
> >>>>> -	 */
> >>>>> -	if (strcmp(pwrdm->name, "mpu_pwrdm"))
> >>>>> -		return 0;
> >>>>>
> >>>>>    	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
> >>>>>    	if (!pwrst)
> >>>
> >>>
> >>
> >
> >
> 




From andi.shyti at gmail.com  Tue Mar  6 04:38:12 2012
From: andi.shyti at gmail.com (Andi)
Date: Tue, 6 Mar 2012 10:38:12 +0100
Subject: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection
 loop
In-Reply-To: <1331023544-6439-3-git-send-email-mad_soft@inbox.ru>
References: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>
 <1331023544-6439-3-git-send-email-mad_soft@inbox.ru>
Message-ID: <CANndwHav6JcqNOuOXcD1dSNUmVYAV=MJ+y+ud6202q6Dh42Vgw@mail.gmail.com>

Hi,

On Tue, Mar 6, 2012 at 9:45 AM, Dmitry Artamonow <mad_soft at inbox.ru> wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (as PCIe code is not modular).
>
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
>
> Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>
> ---
> ?arch/arm/mach-tegra/pcie.c | ? 14 +++++++++++---
> ?1 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
> index 14b29ab..ffdfdd4 100644
> --- a/arch/arm/mach-tegra/pcie.c
> +++ b/arch/arm/mach-tegra/pcie.c
> @@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
> ? ? ? ?afi_writel(0, AFI_MSI_BAR_SZ);
> ?}
>
> -static void tegra_pcie_enable_controller(void)
> +static int tegra_pcie_enable_controller(void)
> ?{
> ? ? ? ?u32 val, reg;
> - ? ? ? int i;
> + ? ? ? int i, timeout;
>
> ? ? ? ?/* Enable slot clock and pulse the reset signals */
> ? ? ? ?for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
> @@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
> ? ? ? ?pads_writel(0xfa5cfa5c, 0xc8);
>
> ? ? ? ?/* Wait for the PLL to lock */
> + ? ? ? timeout = 2000;
> ? ? ? ?do {
> ? ? ? ? ? ? ? ?val = pads_readl(PADS_PLL_CTL);
> + ? ? ? ? ? ? ? mdelay(1);

why are you using an mdelay? If you need to sleep 1ms just use
usleep_range or similar

Andi

> + ? ? ? ? ? ? ? if (--timeout == 0) {
> + ? ? ? ? ? ? ? ? ? ? ? pr_err("Tegra PCIe error: timeout waiting for PLL\n");
> + ? ? ? ? ? ? ? ? ? ? ? return -EBUSY;
> + ? ? ? ? ? ? ? }
> ? ? ? ?} while (!(val & PADS_PLL_CTL_LOCKDET));
>
> ? ? ? ?/* turn off IDDQ override */
> @@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
> ? ? ? ?if (err)
> ? ? ? ? ? ? ? ?return err;
>
> - ? ? ? tegra_pcie_enable_controller();
> + ? ? ? err = tegra_pcie_enable_controller();
> + ? ? ? if (err)
> + ? ? ? ? ? ? ? return err;
>
> ? ? ? ?/* setup the AFI address translations */
> ? ? ? ?tegra_pcie_setup_translations();
> --
> 1.7.5.1.300.gc565c
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at ?http://www.tux.org/lkml/


From kgene.kim at samsung.com  Tue Mar  6 04:49:49 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 06 Mar 2012 01:49:49 -0800
Subject: [PATCH] ARM: S3C64XX: Add some more Cragganmore module IDs to
 the table
In-Reply-To: <1330991143-12349-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1330991143-12349-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <4F55DDBD.8090204@samsung.com>

On 03/05/12 15:45, Mark Brown wrote:
> Just IDs for diagnostics, nothing is actually supported. Not all of
> these have board numbers assigned yet, these will be updated as the
> numbers are assigned.
>
> Signed-off-by: Mark Brown<broonie at opensource.wolfsonmicro.com>
> ---
>
> It'd be really nice to get this into 3.4 if possible, I know it's a bit
> late but it's a very simple and non-invasive patch.
>
Looks OK, will apply.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Tue Mar  6 04:51:27 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 06 Mar 2012 01:51:27 -0800
Subject: [PATCH] ARM: SAMSUNG: change the name from s3c-sdhci to
 exynos4-sdhci
In-Reply-To: <4F557692.8090102@samsung.com>
References: <4F45D343.6020409@samsung.com>
 <CAJuYYwTh8tVdA0X-TLEU-9O_M0_PmJR=i3WYAQXsaRcPF3MbJA@mail.gmail.com>
 <4F557692.8090102@samsung.com>
Message-ID: <4F55DE1F.9010405@samsung.com>

On 03/05/12 18:29, Jaehoon Chung wrote:
> Hi Kukjin.
>
> Is it merged?
>
> Best Regards,
> Jaehoon Chung
>
> On 02/24/2012 06:56 PM, Thomas Abraham wrote:
>
>> On 23 February 2012 11:18, Jaehoon Chung<jh80.chung at samsung.com>  wrote:
>>> Thomas Arbrahams's patchset have changed the device name in sdhci-s3c.c
>>> (mmc: sdhci-s3c: Rework platform data and add device tree support)
>>> But didn't change the regulator_consumer name.
>>> So maybe didn't initialize the mmc/sd card for exynos4.
>>>
>>> This patch is fixed that (based-on linux-samsung for-next branch)
>>>
>>> Signed-off-by: Jaehoon Chung<jh80.chung at samsung.com>
>>> Signed-off-by: kyungmin Park<kyungmin.park at samsung.com>
>>> ---
>>>   arch/arm/mach-exynos/mach-nuri.c           |    4 ++--
>>>   arch/arm/mach-exynos/mach-universal_c210.c |    2 +-
>>>   2 files changed, 3 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
>>> index a6b9162..251dd7a 100644
>>> --- a/arch/arm/mach-exynos/mach-nuri.c
>>> +++ b/arch/arm/mach-exynos/mach-nuri.c
>>> @@ -116,7 +116,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
>>>   };
>>>
>>>   static struct regulator_consumer_supply emmc_supplies[] = {
>>> -       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
>>> +       REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
>>>         REGULATOR_SUPPLY("vmmc", "dw_mmc"),
>>>   };
>>>
>>> @@ -415,7 +415,7 @@ static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
>>>         REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
>>>   };
>>>   static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
>>> -       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
>>> +       REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
>>>   };
>>>   static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
>>>         REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
>>> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
>>> index 6017a21..320cb1d 100644
>>> --- a/arch/arm/mach-exynos/mach-universal_c210.c
>>> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
>>> @@ -749,7 +749,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
>>>   };
>>>
>>>   static struct regulator_consumer_supply mmc0_supplies[] = {
>>> -       REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
>>> +       REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
>>>   };
>>>
>>>   static struct regulator_init_data mmc0_fixed_voltage_init_data = {
>>
>> Reviewed-by: Thomas Abraham<thomas.abraham at linaro.org>

Looks OK, will apply.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From broonie at opensource.wolfsonmicro.com  Tue Mar  6 04:52:26 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 09:52:26 +0000
Subject: [GIT PULL][v3.4] pull request on arch-pxa for regulator branch
In-Reply-To: <CAN1soZxJO8sGZwq5LhuEOxt3uEN=s1cAOSXfbR8L5r8Hpc+t-w@mail.gmail.com>
References: <CAN1soZxJO8sGZwq5LhuEOxt3uEN=s1cAOSXfbR8L5r8Hpc+t-w@mail.gmail.com>
Message-ID: <20120306095226.GB19635@opensource.wolfsonmicro.com>

On Tue, Mar 06, 2012 at 02:08:12PM +0800, Haojian Zhuang wrote:

> Heiko St?bner (2):
>       pxa: magician/hx4700: Convert to gpio-regulator from bq24022
>       regulator: Remove bq24022 regulator driver

Please wait for some confirmation before you go deleting drivers from
other subsystems!  I don't recall replying to this thread at all...
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From heiko at sntech.de  Tue Mar  6 04:57:15 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Tue, 6 Mar 2012 10:57:15 +0100
Subject: [PATCH 0/4] S3C24XX: Another move of code to the new mach directory
Message-ID: <201203061057.15815.heiko@sntech.de>

This series contains the easy moves of common code for the SMDKs,
Simtec boards and device setup from plat-s3c24xx to mach-s3c24xx.

It also contains an extra patch to keep the Simtec code more together.

Changes to the Kconfig and Makefile will probably conflict with the
S3C2416-SPI series posted sunday, but this is ok, as the SPI series
will probably have to wait for 3.5 anyway and can be redone then.

Heiko Stuebner (4):
  ARM: S3C24XX: Move common-smdk code to mach directory
  ARM: S3C24XX: move simtec-specific code to mach directory
  ARM: S3C24XX: Consolidate Simtec extensions
  ARM: S3C24XX: Move device setup files to mach directory

 arch/arm/mach-s3c24xx/Kconfig                      |   62 +++++++++++++++-----
 arch/arm/mach-s3c24xx/Makefile                     |   12 +++-
 .../{plat-s3c24xx => mach-s3c24xx}/common-smdk.c   |    0
 arch/arm/mach-s3c24xx/mach-anubis.c                |    1 +
 arch/arm/mach-s3c24xx/mach-bast.c                  |    3 +-
 arch/arm/mach-s3c24xx/mach-vr1000.c                |    3 +-
 .../arm/{plat-s3c24xx => mach-s3c24xx}/setup-i2c.c |    0
 arch/arm/{plat-s3c24xx => mach-s3c24xx}/setup-ts.c |    0
 .../{plat-s3c24xx => mach-s3c24xx}/simtec-audio.c  |    2 +
 .../mach-s3c24xx/{nor-simtec.c => simtec-nor.c}    |    2 +-
 .../pm-simtec.c => mach-s3c24xx/simtec-pm.c}       |    0
 .../mach-s3c24xx/{usb-simtec.c => simtec-usb.c}    |    2 +-
 arch/arm/mach-s3c24xx/{nor-simtec.h => simtec.h}   |    9 +++-
 arch/arm/mach-s3c24xx/usb-simtec.h                 |   16 -----
 arch/arm/plat-s3c24xx/Kconfig                      |   23 -------
 arch/arm/plat-s3c24xx/Makefile                     |   10 ---
 arch/arm/plat-samsung/include/plat/audio-simtec.h  |    3 -
 17 files changed, 72 insertions(+), 76 deletions(-)
 rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/common-smdk.c (100%)
 rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/setup-i2c.c (100%)
 rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/setup-ts.c (100%)
 rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/simtec-audio.c (98%)
 rename arch/arm/mach-s3c24xx/{nor-simtec.c => simtec-nor.c} (98%)
 rename arch/arm/{plat-s3c24xx/pm-simtec.c => mach-s3c24xx/simtec-pm.c} (100%)
 rename arch/arm/mach-s3c24xx/{usb-simtec.c => simtec-usb.c} (99%)
 rename arch/arm/mach-s3c24xx/{nor-simtec.h => simtec.h} (63%)
 delete mode 100644 arch/arm/mach-s3c24xx/usb-simtec.h

-- 
1.7.5.4



From heiko at sntech.de  Tue Mar  6 04:58:19 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Tue, 6 Mar 2012 10:58:19 +0100
Subject: [PATCH 1/4] ARM: S3C24XX: Move common-smdk code to mach directory
In-Reply-To: <201203061057.15815.heiko@sntech.de>
References: <201203061057.15815.heiko@sntech.de>
Message-ID: <201203061058.19529.heiko@sntech.de>

This code is used by boards based on the S3C2410/S3C2440/S3C2416.
The patch includes also a rename of the option, as the smdk code
is not a mach itself, but only an extension with common code.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/Kconfig                      |   19 ++++++++++++++-----
 arch/arm/mach-s3c24xx/Makefile                     |    1 +
 .../{plat-s3c24xx => mach-s3c24xx}/common-smdk.c   |    0
 arch/arm/plat-s3c24xx/Kconfig                      |    5 -----
 arch/arm/plat-s3c24xx/Makefile                     |    1 -
 5 files changed, 15 insertions(+), 11 deletions(-)
 rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/common-smdk.c (100%)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 48af6fc..7dede07 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -81,6 +81,15 @@ config CPU_S3C2443
 	help
 	  Support for the S3C2443 SoC from the S3C24XX line
 
+# common code
+
+config S3C24XX_SMDK
+	bool
+	help
+	  Common machine code for SMDK2410 and SMDK2440
+
+# cpu-specific sections
+
 if CPU_S3C2410
 
 config S3C2410_DMA
@@ -192,7 +201,7 @@ config MACH_QT2410
 
 config ARCH_SMDK2410
 	bool "SMDK2410/A9M2410"
-	select MACH_SMDK
+	select S3C24XX_SMDK
 	help
 	  Say Y here if you are using the SMDK2410 or the derived module A9M2410
 	  <http://www.fsforth.de>
@@ -279,7 +288,7 @@ config MACH_SMDK2412
 config MACH_SMDK2413
 	bool "SMDK2413"
 	select MACH_S3C2413
-	select MACH_SMDK
+	select S3C24XX_SMDK
 	select S3C_DEV_USB_HOST
 	select S3C_DEV_NAND
 	help
@@ -317,7 +326,7 @@ comment "S3C2416 Boards"
 
 config MACH_SMDK2416
 	bool "SMDK2416"
-	select MACH_SMDK
+	select S3C24XX_SMDK
 	select S3C_DEV_FB
 	select S3C_DEV_HSMMC
 	select S3C_DEV_HSMMC1
@@ -420,7 +429,7 @@ config MACH_RX3715
 config ARCH_S3C2440
 	bool "SMDK2440"
 	select S3C2440_XTAL_16934400
-	select MACH_SMDK
+	select S3C24XX_SMDK
 	select S3C_DEV_USB_HOST
 	select S3C_DEV_NAND
 	help
@@ -492,7 +501,7 @@ comment "S3C2443 Boards"
 
 config MACH_SMDK2443
 	bool "SMDK2443"
-	select MACH_SMDK
+	select S3C24XX_SMDK
 	select S3C_DEV_HSMMC1
 	help
 	  Say Y here if you are using an SMDK2443
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 876e5e5..b1c3c6f 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_MACH_SMDK2443)		+= mach-smdk2443.o
 
 # common bits of machine support
 
+obj-$(CONFIG_S3C24XX_SMDK)		+= common-smdk.o
 obj-$(CONFIG_SIMTEC_NOR)		+= nor-simtec.o
 
 # machine additions
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
similarity index 100%
rename from arch/arm/plat-s3c24xx/common-smdk.c
rename to arch/arm/mach-s3c24xx/common-smdk.c
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 74f76e0..73ebc40 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -119,11 +119,6 @@ config S3C2412_IOTIMING
 	  Intel node to select io timing code that is common to the s3c2412
 	  and the s3c2443.
 
-config MACH_SMDK
-	bool
-	help
-	  Common machine code for SMDK2410 and SMDK2440
-
 config S3C24XX_SIMTEC_AUDIO
 	bool
 	depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS)
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index a7e8843..8dca10a 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -39,5 +39,4 @@ obj-$(CONFIG_S3C2410_SETUP_TS)	+= setup-ts.o
 
 # machine common support
 
-obj-$(CONFIG_MACH_SMDK)		+= common-smdk.o
 obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO)	+= simtec-audio.o
-- 
1.7.5.4



From heiko at sntech.de  Tue Mar  6 04:59:00 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Tue, 6 Mar 2012 10:59:00 +0100
Subject: [PATCH 2/4] ARM: S3C24XX: move simtec-specific code to mach directory
In-Reply-To: <201203061057.15815.heiko@sntech.de>
References: <201203061057.15815.heiko@sntech.de>
Message-ID: <201203061059.00751.heiko@sntech.de>

This includes a rename of the pm-simtec.c to keep the simtec
extensions together a bit and also better naming of the Kconfig
options.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/Kconfig                      |   23 +++++++++++++++----
 arch/arm/mach-s3c24xx/Makefile                     |    2 +
 .../{plat-s3c24xx => mach-s3c24xx}/simtec-audio.c  |    0
 .../pm-simtec.c => mach-s3c24xx/simtec-pm.c}       |    0
 arch/arm/plat-s3c24xx/Kconfig                      |   13 -----------
 arch/arm/plat-s3c24xx/Makefile                     |    5 ----
 6 files changed, 20 insertions(+), 23 deletions(-)
 rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/simtec-audio.c (100%)
 rename arch/arm/{plat-s3c24xx/pm-simtec.c => mach-s3c24xx/simtec-pm.c} (100%)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 7dede07..115cc50 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -88,6 +88,19 @@ config S3C24XX_SMDK
 	help
 	  Common machine code for SMDK2410 and SMDK2440
 
+config S3C24XX_SIMTEC_AUDIO
+	bool
+	depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS)
+	default y
+	help
+	  Add audio devices for common Simtec S3C24XX boards
+
+config S3C24XX_SIMTEC_PM
+	bool
+	help
+	  Common power management code for systems that are
+	  compatible with the Simtec style of power management
+
 # cpu-specific sections
 
 if CPU_S3C2410
@@ -125,7 +138,7 @@ comment "S3C2410 Boards"
 
 config MACH_AML_M5900
 	bool "AML M5900 Series"
-	select PM_SIMTEC if PM
+	select S3C24XX_SIMTEC_PM if PM
 	select S3C_DEV_USB_HOST
 	help
 	  Say Y here if you are using the American Microsystems M5900 Series
@@ -134,7 +147,7 @@ config MACH_AML_M5900
 config ARCH_BAST
 	bool "Simtec Electronics BAST (EB2410ITX)"
 	select S3C2410_IOTIMING if S3C2410_CPUFREQ
-	select PM_SIMTEC if PM
+	select S3C24XX_SIMTEC_PM if PM
 	select SIMTEC_NOR
 	select MACH_BAST_IDE
 	select S3C24XX_DCLK
@@ -215,7 +228,7 @@ config MACH_TCT_HAMMER
 
 config MACH_VR1000
 	bool "Thorcom VR1000"
-	select PM_SIMTEC if PM
+	select S3C24XX_SIMTEC_PM if PM
 	select S3C24XX_DCLK
 	select SIMTEC_NOR
 	select MACH_BAST_IDE
@@ -355,7 +368,7 @@ comment "S3C2440 Boards"
 config MACH_ANUBIS
 	bool "Simtec Electronics ANUBIS"
 	select S3C24XX_DCLK
-	select PM_SIMTEC if PM
+	select S3C24XX_SIMTEC_PM if PM
 	select HAVE_PATA_PLATFORM
 	select S3C24XX_GPIO_EXTRA64
 	select S3C2440_XTAL_12000000
@@ -395,7 +408,7 @@ config MACH_NEXCODER_2440
 config MACH_OSIRIS
 	bool "Simtec IM2440D20 (OSIRIS) module"
 	select S3C24XX_DCLK
-	select PM_SIMTEC if PM
+	select S3C24XX_SIMTEC_PM if PM
 	select S3C24XX_GPIO_EXTRA128
 	select S3C2440_XTAL_12000000
 	select S3C2410_IOTIMING if S3C2440_CPUFREQ
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index b1c3c6f..fedbdb8 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -79,6 +79,8 @@ obj-$(CONFIG_MACH_SMDK2443)		+= mach-smdk2443.o
 
 obj-$(CONFIG_S3C24XX_SMDK)		+= common-smdk.o
 obj-$(CONFIG_SIMTEC_NOR)		+= nor-simtec.o
+obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO)	+= simtec-audio.o
+obj-$(CONFIG_S3C24XX_SIMTEC_PM)		+= simtec-pm.o
 
 # machine additions
 
diff --git a/arch/arm/plat-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c24xx/simtec-audio.c
similarity index 100%
rename from arch/arm/plat-s3c24xx/simtec-audio.c
rename to arch/arm/mach-s3c24xx/simtec-audio.c
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/mach-s3c24xx/simtec-pm.c
similarity index 100%
rename from arch/arm/plat-s3c24xx/pm-simtec.c
rename to arch/arm/mach-s3c24xx/simtec-pm.c
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 73ebc40..0338d20 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -70,12 +70,6 @@ config S3C24XX_GPIO_EXTRA128
 	  Add an extra 128 gpio numbers to the available GPIO pool. This is
 	  available for boards that need extra gpios for external devices.
 
-config PM_SIMTEC
-	bool
-	help
-	  Common power management code for systems that are
-	  compatible with the Simtec style of power management
-
 config S3C24XX_DMA
 	bool "S3C2410 DMA support"
 	depends on ARCH_S3C24XX
@@ -119,13 +113,6 @@ config S3C2412_IOTIMING
 	  Intel node to select io timing code that is common to the s3c2412
 	  and the s3c2443.
 
-config S3C24XX_SIMTEC_AUDIO
-	bool
-	depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS)
-	default y
-	help
-	  Add audio devices for common Simtec S3C24XX boards
-
 config S3C2410_SETUP_TS
 	bool
 	help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 8dca10a..27dd9c5 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
 
 # Architecture dependent builds
 
-obj-$(CONFIG_PM_SIMTEC)		+= pm-simtec.o
 obj-$(CONFIG_PM)		+= pm.o
 obj-$(CONFIG_PM)		+= irq-pm.o
 obj-$(CONFIG_PM)		+= sleep.o
@@ -36,7 +35,3 @@ obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
 # device specific setup and/or initialisation
 obj-$(CONFIG_ARCH_S3C24XX)	+= setup-i2c.o
 obj-$(CONFIG_S3C2410_SETUP_TS)	+= setup-ts.o
-
-# machine common support
-
-obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO)	+= simtec-audio.o
-- 
1.7.5.4



From heiko at sntech.de  Tue Mar  6 04:59:44 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Tue, 6 Mar 2012 10:59:44 +0100
Subject: [PATCH 3/4] ARM: S3C24XX: Consolidate Simtec extensions
In-Reply-To: <201203061057.15815.heiko@sntech.de>
References: <201203061057.15815.heiko@sntech.de>
Message-ID: <201203061059.44955.heiko@sntech.de>

The Simtec extension didn't follow a specific naming scheme for files
and config options until now. This distributed the files throughout
the whole mach-s3c24xx directory.

This patch fixes the naming of files and option names and also creates
a simtec.h header instead of using many one-liners.

As the plat/audio-simtec.h only contains the platform-data struct now,
it can also move to include/sound in a later patch.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/Kconfig                      |   13 ++++++++++---
 arch/arm/mach-s3c24xx/Makefile                     |    7 ++++---
 arch/arm/mach-s3c24xx/mach-anubis.c                |    1 +
 arch/arm/mach-s3c24xx/mach-bast.c                  |    3 +--
 arch/arm/mach-s3c24xx/mach-vr1000.c                |    3 +--
 arch/arm/mach-s3c24xx/simtec-audio.c               |    2 ++
 .../mach-s3c24xx/{nor-simtec.c => simtec-nor.c}    |    2 +-
 .../mach-s3c24xx/{usb-simtec.c => simtec-usb.c}    |    2 +-
 arch/arm/mach-s3c24xx/{nor-simtec.h => simtec.h}   |    9 ++++++++-
 arch/arm/mach-s3c24xx/usb-simtec.h                 |   16 ----------------
 arch/arm/plat-samsung/include/plat/audio-simtec.h  |    3 ---
 11 files changed, 29 insertions(+), 32 deletions(-)
 rename arch/arm/mach-s3c24xx/{nor-simtec.c => simtec-nor.c} (98%)
 rename arch/arm/mach-s3c24xx/{usb-simtec.c => simtec-usb.c} (99%)
 rename arch/arm/mach-s3c24xx/{nor-simtec.h => simtec.h} (63%)
 delete mode 100644 arch/arm/mach-s3c24xx/usb-simtec.h

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 115cc50..df6f419 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -101,6 +101,11 @@ config S3C24XX_SIMTEC_PM
 	  Common power management code for systems that are
 	  compatible with the Simtec style of power management
 
+config S3C24XX_SIMTEC_USB
+	bool
+	help
+	  USB management code for common Simtec S3C24XX boards
+
 # cpu-specific sections
 
 if CPU_S3C2410
@@ -117,7 +122,7 @@ config S3C2410_PM
 	help
 	  Power Management code common to S3C2410 and better
 
-config SIMTEC_NOR
+config S3C24XX_SIMTEC_NOR
 	bool
 	help
 	  Internal node to specify machine has simtec NOR mapping
@@ -148,7 +153,8 @@ config ARCH_BAST
 	bool "Simtec Electronics BAST (EB2410ITX)"
 	select S3C2410_IOTIMING if S3C2410_CPUFREQ
 	select S3C24XX_SIMTEC_PM if PM
-	select SIMTEC_NOR
+	select S3C24XX_SIMTEC_NOR
+	select S3C24XX_SIMTEC_USB
 	select MACH_BAST_IDE
 	select S3C24XX_DCLK
 	select ISA
@@ -230,9 +236,10 @@ config MACH_VR1000
 	bool "Thorcom VR1000"
 	select S3C24XX_SIMTEC_PM if PM
 	select S3C24XX_DCLK
-	select SIMTEC_NOR
+	select S3C24XX_SIMTEC_NOR
 	select MACH_BAST_IDE
 	select S3C_DEV_USB_HOST
+	select S3C24XX_SIMTEC_USB
 	help
 	  Say Y here if you are using the Thorcom VR1000 board.
 
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index fedbdb8..2843c81 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -44,7 +44,7 @@ obj-$(CONFIG_S3C2443_COMMON)	+= common-s3c2443.o
 #
 
 obj-$(CONFIG_MACH_AML_M5900)		+= mach-amlm5900.o
-obj-$(CONFIG_ARCH_BAST)			+= mach-bast.o usb-simtec.o
+obj-$(CONFIG_ARCH_BAST)			+= mach-bast.o
 obj-$(CONFIG_BAST_PC104_IRQ)		+= bast-irq.o
 obj-$(CONFIG_ARCH_H1940)		+= mach-h1940.o
 obj-$(CONFIG_H1940BT)			+= h1940-bluetooth.o
@@ -54,7 +54,7 @@ obj-$(CONFIG_MACH_OTOM)			+= mach-otom.o
 obj-$(CONFIG_MACH_QT2410)		+= mach-qt2410.o
 obj-$(CONFIG_ARCH_SMDK2410)		+= mach-smdk2410.o
 obj-$(CONFIG_MACH_TCT_HAMMER)		+= mach-tct_hammer.o
-obj-$(CONFIG_MACH_VR1000)		+= mach-vr1000.o usb-simtec.o
+obj-$(CONFIG_MACH_VR1000)		+= mach-vr1000.o
 
 obj-$(CONFIG_MACH_JIVE)			+= mach-jive.o
 obj-$(CONFIG_MACH_SMDK2413)		+= mach-smdk2413.o
@@ -78,9 +78,10 @@ obj-$(CONFIG_MACH_SMDK2443)		+= mach-smdk2443.o
 # common bits of machine support
 
 obj-$(CONFIG_S3C24XX_SMDK)		+= common-smdk.o
-obj-$(CONFIG_SIMTEC_NOR)		+= nor-simtec.o
 obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO)	+= simtec-audio.o
+obj-$(CONFIG_S3C24XX_SIMTEC_NOR)	+= simtec-nor.o
 obj-$(CONFIG_S3C24XX_SIMTEC_PM)		+= simtec-pm.o
+obj-$(CONFIG_S3C24XX_SIMTEC_USB)	+= simtec-usb.o
 
 # machine additions
 
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 2456955..9e0f745 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -55,6 +55,7 @@
 #include <plat/cpu.h>
 #include <plat/audio-simtec.h>
 
+#include "simtec.h"
 #include "common.h"
 
 #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index feeaf73..53219c0 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -64,8 +64,7 @@
 #include <plat/gpio-cfg.h>
 #include <plat/audio-simtec.h>
 
-#include "usb-simtec.h"
-#include "nor-simtec.h"
+#include "simtec.h"
 #include "common.h"
 
 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index dbe668a..87608d4 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -51,8 +51,7 @@
 #include <plat/iic.h>
 #include <plat/audio-simtec.h>
 
-#include "usb-simtec.h"
-#include "nor-simtec.h"
+#include "simtec.h"
 #include "common.h"
 
 /* macros for virtual address mods for the io space entries */
diff --git a/arch/arm/mach-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c24xx/simtec-audio.c
index 6bc832e..11881c9 100644
--- a/arch/arm/mach-s3c24xx/simtec-audio.c
+++ b/arch/arm/mach-s3c24xx/simtec-audio.c
@@ -27,6 +27,8 @@
 #include <plat/audio-simtec.h>
 #include <plat/devs.h>
 
+#include "simtec.h"
+
 /* platform ops for audio */
 
 static void simtec_audio_startup_lrroute(void)
diff --git a/arch/arm/mach-s3c24xx/nor-simtec.c b/arch/arm/mach-s3c24xx/simtec-nor.c
similarity index 98%
rename from arch/arm/mach-s3c24xx/nor-simtec.c
rename to arch/arm/mach-s3c24xx/simtec-nor.c
index ad9f750..2119ca6 100644
--- a/arch/arm/mach-s3c24xx/nor-simtec.c
+++ b/arch/arm/mach-s3c24xx/simtec-nor.c
@@ -30,7 +30,7 @@
 #include <mach/bast-map.h>
 #include <mach/bast-cpld.h>
 
-#include "nor-simtec.h"
+#include "simtec.h"
 
 static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
 {
diff --git a/arch/arm/mach-s3c24xx/usb-simtec.c b/arch/arm/mach-s3c24xx/simtec-usb.c
similarity index 99%
rename from arch/arm/mach-s3c24xx/usb-simtec.c
rename to arch/arm/mach-s3c24xx/simtec-usb.c
index 29bd3d9..d91c1a7 100644
--- a/arch/arm/mach-s3c24xx/usb-simtec.c
+++ b/arch/arm/mach-s3c24xx/simtec-usb.c
@@ -37,7 +37,7 @@
 #include <plat/usb-control.h>
 #include <plat/devs.h>
 
-#include "usb-simtec.h"
+#include "simtec.h"
 
 /* control power and monitor over-current events on various Simtec
  * designed boards.
diff --git a/arch/arm/mach-s3c24xx/nor-simtec.h b/arch/arm/mach-s3c24xx/simtec.h
similarity index 63%
rename from arch/arm/mach-s3c24xx/nor-simtec.h
rename to arch/arm/mach-s3c24xx/simtec.h
index f619c1e..ae8f4f9 100644
--- a/arch/arm/mach-s3c24xx/nor-simtec.h
+++ b/arch/arm/mach-s3c24xx/simtec.h
@@ -4,11 +4,18 @@
  *	http://armlinux.simtec.co.uk/
  *	Ben Dooks <ben at simtec.co.uk>
  *
- * Simtec NOR mapping
+ * Simtec common functions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 
+struct s3c24xx_audio_simtec_pdata;
+
 extern void nor_simtec_init(void);
+
+extern int usb_simtec_init(void);
+
+extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
+			    struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/mach-s3c24xx/usb-simtec.h b/arch/arm/mach-s3c24xx/usb-simtec.h
deleted file mode 100644
index 03842ed..0000000
--- a/arch/arm/mach-s3c24xx/usb-simtec.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* linux/arch/arm/mach-s3c2410/usb-simtec.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *   Ben Dooks <ben at simtec.co.uk>
- *
- * http://www.simtec.co.uk/products/EB2410ITX/
- *
- * Simtec BAST and Thorcom VR1000 USB port support functions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern int usb_simtec_init(void);
-
diff --git a/arch/arm/plat-samsung/include/plat/audio-simtec.h b/arch/arm/plat-samsung/include/plat/audio-simtec.h
index 5345364..376af52 100644
--- a/arch/arm/plat-samsung/include/plat/audio-simtec.h
+++ b/arch/arm/plat-samsung/include/plat/audio-simtec.h
@@ -32,6 +32,3 @@ struct s3c24xx_audio_simtec_pdata {
 
 	void	(*startup)(void);
 };
-
-extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
-			    struct s3c24xx_audio_simtec_pdata *pdata);
-- 
1.7.5.4



From heiko at sntech.de  Tue Mar  6 05:00:32 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Tue, 6 Mar 2012 11:00:32 +0100
Subject: [PATCH 4/4] ARM: S3C24XX: Move device setup files to mach directory
In-Reply-To: <201203061057.15815.heiko@sntech.de>
References: <201203061057.15815.heiko@sntech.de>
Message-ID: <201203061100.32931.heiko@sntech.de>

Includes a small rename of the SETUP_TS option to a S3C24XX prefix.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/Kconfig                      |    7 ++++++-
 arch/arm/mach-s3c24xx/Makefile                     |    2 ++
 .../arm/{plat-s3c24xx => mach-s3c24xx}/setup-i2c.c |    0
 arch/arm/{plat-s3c24xx => mach-s3c24xx}/setup-ts.c |    0
 arch/arm/plat-s3c24xx/Kconfig                      |    5 -----
 arch/arm/plat-s3c24xx/Makefile                     |    4 ----
 6 files changed, 8 insertions(+), 10 deletions(-)
 rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/setup-i2c.c (100%)
 rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/setup-ts.c (100%)

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index df6f419..b399021 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -106,6 +106,11 @@ config S3C24XX_SIMTEC_USB
 	help
 	  USB management code for common Simtec S3C24XX boards
 
+config S3C24XX_SETUP_TS
+	bool
+	help
+	  Compile in platform device definition for Samsung TouchScreen.
+
 # cpu-specific sections
 
 if CPU_S3C2410
@@ -178,7 +183,7 @@ config ARCH_H1940
 	select PM_H1940 if PM
 	select S3C_DEV_USB_HOST
 	select S3C_DEV_NAND
-	select S3C2410_SETUP_TS
+	select S3C24XX_SETUP_TS
 	help
 	  Say Y here if you are using the HP IPAQ H1940
 
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 2843c81..3f39e6f 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -91,3 +91,5 @@ obj-$(CONFIG_MACH_OSIRIS_DVS)		+= mach-osiris-dvs.o
 # device setup
 
 obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
+obj-$(CONFIG_ARCH_S3C24XX)		+= setup-i2c.o
+obj-$(CONFIG_S3C24XX_SETUP_TS)		+= setup-ts.o
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/mach-s3c24xx/setup-i2c.c
similarity index 100%
rename from arch/arm/plat-s3c24xx/setup-i2c.c
rename to arch/arm/mach-s3c24xx/setup-i2c.c
diff --git a/arch/arm/plat-s3c24xx/setup-ts.c b/arch/arm/mach-s3c24xx/setup-ts.c
similarity index 100%
rename from arch/arm/plat-s3c24xx/setup-ts.c
rename to arch/arm/mach-s3c24xx/setup-ts.c
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 0338d20..21bf6ad 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -113,9 +113,4 @@ config S3C2412_IOTIMING
 	  Intel node to select io timing code that is common to the s3c2412
 	  and the s3c2443.
 
-config S3C2410_SETUP_TS
-	bool
-	help
-	  Compile in platform device definition for Samsung TouchScreen.
-
 endif
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 27dd9c5..2467b80 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -31,7 +31,3 @@ obj-$(CONFIG_S3C24XX_DMA)	+= dma.o
 obj-$(CONFIG_S3C2410_IOTIMING)	+= s3c2410-iotiming.o
 obj-$(CONFIG_S3C2412_IOTIMING)	+= s3c2412-iotiming.o
 obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
-
-# device specific setup and/or initialisation
-obj-$(CONFIG_ARCH_S3C24XX)	+= setup-i2c.o
-obj-$(CONFIG_S3C2410_SETUP_TS)	+= setup-ts.o
-- 
1.7.5.4



From linus.walleij at linaro.org  Tue Mar  6 05:01:06 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 6 Mar 2012 11:01:06 +0100
Subject: [PATCH V2 1/3] Documentation/gpio.txt: Explain expected pinctrl
 interaction
In-Reply-To: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
References: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
Message-ID: <CACRpkdaQCwOPG8OKHxN3N8m_A71Pf9VurB40DZUA9sJnCsxSjw@mail.gmail.com>

On Tue, Mar 6, 2012 at 1:22 AM, Stephen Warren <swarren at nvidia.com> wrote:

> Update gpio.txt based on recent discussions regarding interaction with the
> pinctrl subsystem.

Looks good to me:
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Mar  6 05:03:23 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 6 Mar 2012 11:03:23 +0100
Subject: [PATCH V2 2/3] pinctrl: allow concurrent gpio and mux function
 ownership of pins
In-Reply-To: <1330993336-9538-2-git-send-email-swarren@nvidia.com>
References: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
 <1330993336-9538-2-git-send-email-swarren@nvidia.com>
Message-ID: <CACRpkdYdSaNsrr34o2Cc4vS12ee9oY7FG0pxB92mefHZKwdEpA@mail.gmail.com>

On Tue, Mar 6, 2012 at 1:22 AM, Stephen Warren <swarren at nvidia.com> wrote:

> Per recent updates to Documentation/gpio.txt, gpiolib drivers should
> inform pinctrl when a GPIO is requested. pinctrl then marks that pin as
> in-use for that GPIO function.
>
> When an SoC muxes pins in a group, it's quite possible for the group to
> contain e.g. 6 pins, but only 4 of them actually be needed by the HW
> module that's mux'd to them. In this case, the other 2 pins could be
> used as GPIOs. However, pinctrl marks all the pins within the group as
> in-use by the selected mux function. To allow the expected gpiolib
> interaction, separate the concepts of pin ownership into two parts: One
> for the mux function and one for GPIO usage. Finally, allow those two
> ownerships to exist in parallel.
>
> Signed-off-by: Stephen Warren <swarren at nvidia.com>

Good, and 100% in accordance with earlier discussions.
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Thanks,
Linus Walleij


From kyungmin.park at samsung.com  Tue Mar  6 05:03:29 2012
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Tue, 6 Mar 2012 19:03:29 +0900
Subject: [PATCH v10 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
In-Reply-To: <002101ccfb73$8684c240$938e46c0$%cho@samsung.com>
References: <002101ccfb73$8684c240$938e46c0$%cho@samsung.com>
Message-ID: <CAH9JG2Uvc27UMcsy_Apqo+Td_td_18C6i3vvC8aroBse2=+53w@mail.gmail.com>

Hi,

On 3/6/12, KyongHo Cho <pullip.cho at samsung.com> wrote:
> Handling System MMUs with an identifier is not flexible to manage
> System MMU platform devices because of the following reasons:
> 1. A device driver which needs to handle System MMU must know the ID.
> 2. A System MMU may not present in some implementations of Exynos family.
> 3. Handling System MMU with IOMMU API does not require an ID.
>
> This patch is the result of removing ID of System MMUs.
> Instead, a device driver that needs to handle its System MMU must
> use IOMMU API while its descriptor of platform device is given.
>
> This patch also includes the following enhanclements:
> - A System MMU device becomes a child if its power domain device.
> - clkdev
>
> Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
> ---
>  arch/arm/mach-exynos/Kconfig                    |   11 +-
>  arch/arm/mach-exynos/Makefile                   |    2 +-
>  arch/arm/mach-exynos/clock-exynos4.c            |   79 ++--
>  arch/arm/mach-exynos/clock-exynos4.h            |    2 +
>  arch/arm/mach-exynos/clock-exynos4210.c         |   11 +
>  arch/arm/mach-exynos/clock-exynos4212.c         |   28 ++-
>  arch/arm/mach-exynos/clock-exynos5.c            |   90 +++++
>  arch/arm/mach-exynos/dev-sysmmu.c               |  457
> ++++++++++++----------
>  arch/arm/mach-exynos/include/mach/irqs.h        |  179 +++++-----
>  arch/arm/mach-exynos/include/mach/map.h         |   38 ++
>  arch/arm/mach-exynos/include/mach/regs-clock.h  |    5 +
>  arch/arm/mach-exynos/include/mach/regs-sysmmu.h |   28 --
>  arch/arm/mach-exynos/include/mach/sysmmu.h      |   84 +++--
>  arch/arm/mach-exynos/mach-armlex4210.c          |    1 -
>  arch/arm/mach-exynos/mach-smdkv310.c            |    1 -
>  15 files changed, 612 insertions(+), 404 deletions(-)
>  delete mode 100644 arch/arm/mach-exynos/include/mach/regs-sysmmu.h
>
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index c49d450..d5a6a29 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -88,10 +88,10 @@ config EXYNOS4_SETUP_FIMD0
>  	help
>  	  Common setup code for FIMD0.
>
> -config EXYNOS4_DEV_SYSMMU
> +config EXYNOS_DEV_SYSMMU
>  	bool
>  	help
> -	  Common setup code for SYSTEM MMU in EXYNOS4
> +	  Common setup code for SYSTEM MMU in EXYNOS platforms
>
>  config EXYNOS4_DEV_DWMCI
>  	bool
> @@ -201,12 +201,12 @@ config MACH_SMDKV310
>  	select S3C_DEV_HSMMC2
>  	select S3C_DEV_HSMMC3
>  	select SAMSUNG_DEV_BACKLIGHT
> +	select EXYNOS_DEV_SYSMMU
>  	select EXYNOS4_DEV_AHCI
>  	select SAMSUNG_DEV_KEYPAD
>  	select EXYNOS4_DEV_DMA
>  	select SAMSUNG_DEV_PWM
>  	select EXYNOS4_DEV_USB_OHCI
> -	select EXYNOS4_DEV_SYSMMU
>  	select EXYNOS4_SETUP_FIMD0
>  	select EXYNOS4_SETUP_I2C1
>  	select EXYNOS4_SETUP_KEYPAD
> @@ -225,7 +225,6 @@ config MACH_ARMLEX4210
>  	select S3C_DEV_HSMMC3
>  	select EXYNOS4_DEV_AHCI
>  	select EXYNOS4_DEV_DMA
> -	select EXYNOS4_DEV_SYSMMU
>  	select EXYNOS4_SETUP_SDHCI
>  	help
>  	  Machine support for Samsung ARMLEX4210 based on EXYNOS4210
> @@ -251,6 +250,7 @@ config MACH_UNIVERSAL_C210
>  	select S5P_DEV_MFC
>  	select S5P_DEV_ONENAND
>  	select S5P_DEV_TV
> +	select EXYNOS_DEV_SYSMMU
>  	select EXYNOS4_DEV_DMA
>  	select EXYNOS4_SETUP_FIMD0
>  	select EXYNOS4_SETUP_I2C1
> @@ -320,6 +320,7 @@ config MACH_ORIGEN
>  	select S5P_DEV_USB_EHCI
>  	select SAMSUNG_DEV_BACKLIGHT
>  	select SAMSUNG_DEV_PWM
> +	select EXYNOS_DEV_SYSMMU
>  	select EXYNOS4_DEV_DMA
>  	select EXYNOS4_DEV_USB_OHCI
>  	select EXYNOS4_SETUP_FIMD0
> @@ -343,6 +344,7 @@ config MACH_SMDK4212
>  	select SAMSUNG_DEV_BACKLIGHT
>  	select SAMSUNG_DEV_KEYPAD
>  	select SAMSUNG_DEV_PWM
> +	select EXYNOS_DEV_SYSMMU
>  	select EXYNOS4_SETUP_I2C1
>  	select EXYNOS4_SETUP_I2C3
>  	select EXYNOS4_SETUP_I2C7
> @@ -368,6 +370,7 @@ comment "EXYNOS5250 Boards"
>  config MACH_SMDK5250
>  	bool "SMDK5250"
>  	select SOC_EXYNOS5250
> +	select EXYNOS_DEV_SYSMMU
>  	help
>  	  Machine support for Samsung SMDK5250
>  endif
> diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
> index 6fd8dd9..8b655e9 100644
> --- a/arch/arm/mach-exynos/Makefile
> +++ b/arch/arm/mach-exynos/Makefile
> @@ -52,7 +52,7 @@ obj-$(CONFIG_MACH_SMDK5250)		+= mach-smdk5250.o
>  obj-y					+= dev-uart.o
>  obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
>  obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
> -obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)	+= dev-sysmmu.o
> +obj-$(CONFIG_EXYNOS_DEV_SYSMMU)		+= dev-sysmmu.o
>  obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
>  obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
>  obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o
> diff --git a/arch/arm/mach-exynos/clock-exynos4.c
> b/arch/arm/mach-exynos/clock-exynos4.c
> index d72a1fe..18c48f0 100644
> --- a/arch/arm/mach-exynos/clock-exynos4.c
> +++ b/arch/arm/mach-exynos/clock-exynos4.c
> @@ -169,7 +169,7 @@ static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int
> enable)
>  	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
>  }
>
> -static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
> +int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
>  {
>  	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
>  }
> @@ -199,6 +199,11 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk,
> int enable)
>  	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
>  }
>
> +int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
> +{
> +	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
> +}
> +
>  static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
>  {
>  	return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
> @@ -679,61 +684,55 @@ static struct clk exynos4_init_clocks_off[] = {
>  		.enable		= exynos4_clk_ip_peril_ctrl,
>  		.ctrlbit	= (1 << 14),
>  	}, {
> -		.name		= "SYSMMU_MDMA",
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
> +		.enable		= exynos4_clk_ip_mfc_ctrl,
> +		.ctrlbit	= (1 << 1),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
> +		.enable		= exynos4_clk_ip_mfc_ctrl,
> +		.ctrlbit	= (1 << 2),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(tv, 2),
> +		.enable		= exynos4_clk_ip_tv_ctrl,
> +		.ctrlbit	= (1 << 4),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(jpeg, 3),
> +		.enable		= exynos4_clk_ip_cam_ctrl,
> +		.ctrlbit	= (1 << 11),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(rot, 4),
>  		.enable		= exynos4_clk_ip_image_ctrl,
> -		.ctrlbit	= (1 << 5),
> +		.ctrlbit	= (1 << 4),
>  	}, {
> -		.name		= "SYSMMU_FIMC0",
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(fimc0, 5),
>  		.enable		= exynos4_clk_ip_cam_ctrl,
>  		.ctrlbit	= (1 << 7),
>  	}, {
> -		.name		= "SYSMMU_FIMC1",
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(fimc1, 6),
>  		.enable		= exynos4_clk_ip_cam_ctrl,
>  		.ctrlbit	= (1 << 8),
>  	}, {
> -		.name		= "SYSMMU_FIMC2",
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(fimc2, 7),
>  		.enable		= exynos4_clk_ip_cam_ctrl,
>  		.ctrlbit	= (1 << 9),
>  	}, {
> -		.name		= "SYSMMU_FIMC3",
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(fimc3, 8),
>  		.enable		= exynos4_clk_ip_cam_ctrl,
>  		.ctrlbit	= (1 << 10),
>  	}, {
> -		.name		= "SYSMMU_JPEG",
> -		.enable		= exynos4_clk_ip_cam_ctrl,
> -		.ctrlbit	= (1 << 11),
> -	}, {
> -		.name		= "SYSMMU_FIMD0",
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(fimd0, 10),
>  		.enable		= exynos4_clk_ip_lcd0_ctrl,
>  		.ctrlbit	= (1 << 4),
> -	}, {
> -		.name		= "SYSMMU_FIMD1",
> -		.enable		= exynos4_clk_ip_lcd1_ctrl,
> -		.ctrlbit	= (1 << 4),
> -	}, {
> -		.name		= "SYSMMU_PCIe",
> -		.enable		= exynos4_clk_ip_fsys_ctrl,
> -		.ctrlbit	= (1 << 18),
> -	}, {
> -		.name		= "SYSMMU_G2D",
> -		.enable		= exynos4_clk_ip_image_ctrl,
> -		.ctrlbit	= (1 << 3),
> -	}, {
> -		.name		= "SYSMMU_ROTATOR",
> -		.enable		= exynos4_clk_ip_image_ctrl,
> -		.ctrlbit	= (1 << 4),
> -	}, {
> -		.name		= "SYSMMU_TV",
> -		.enable		= exynos4_clk_ip_tv_ctrl,
> -		.ctrlbit	= (1 << 4),
> -	}, {
> -		.name		= "SYSMMU_MFC_L",
> -		.enable		= exynos4_clk_ip_mfc_ctrl,
> -		.ctrlbit	= (1 << 1),
> -	}, {
> -		.name		= "SYSMMU_MFC_R",
> -		.enable		= exynos4_clk_ip_mfc_ctrl,
> -		.ctrlbit	= (1 << 2),
>  	}
>  };
>
> diff --git a/arch/arm/mach-exynos/clock-exynos4.h
> b/arch/arm/mach-exynos/clock-exynos4.h
> index 9d27a56..309cc71 100644
> --- a/arch/arm/mach-exynos/clock-exynos4.h
> +++ b/arch/arm/mach-exynos/clock-exynos4.h
> @@ -28,5 +28,7 @@ extern struct clk *exynos4_clkset_group_list[];
>  extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
>  extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
>  extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
> +extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
> +extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
>
>  #endif /* __ASM_ARCH_CLOCK_H */
> diff --git a/arch/arm/mach-exynos/clock-exynos4210.c
> b/arch/arm/mach-exynos/clock-exynos4210.c
> index 68763b3..c1fcd2f 100644
> --- a/arch/arm/mach-exynos/clock-exynos4210.c
> +++ b/arch/arm/mach-exynos/clock-exynos4210.c
> @@ -28,6 +28,7 @@
>  #include <mach/hardware.h>
>  #include <mach/map.h>
>  #include <mach/regs-clock.h>
> +#include <mach/sysmmu.h>
>
>  #include "clock-exynos4.h"
>  #include "common.h"
> @@ -96,6 +97,16 @@ static struct clk init_clocks_off[] = {
>  		.devname	= "exynos4-fb.1",
>  		.enable		= exynos4_clk_ip_lcd1_ctrl,
>  		.ctrlbit	= (1 << 0),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
> +		.enable		= exynos4_clk_ip_image_ctrl,
> +		.ctrlbit	= (1 << 3),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(fimd1, 11),
> +		.enable		= exynos4_clk_ip_lcd1_ctrl,
> +		.ctrlbit	= (1 << 4),
>  	},
>  };
>
> diff --git a/arch/arm/mach-exynos/clock-exynos4212.c
> b/arch/arm/mach-exynos/clock-exynos4212.c
> index f22a0a2..e1059a2 100644
> --- a/arch/arm/mach-exynos/clock-exynos4212.c
> +++ b/arch/arm/mach-exynos/clock-exynos4212.c
> @@ -28,6 +28,7 @@
>  #include <mach/hardware.h>
>  #include <mach/map.h>
>  #include <mach/regs-clock.h>
> +#include <mach/sysmmu.h>
>
>  #include "clock-exynos4.h"
>  #include "common.h"
> @@ -41,6 +42,16 @@ static struct sleep_save exynos4212_clock_save[] = {
>  };
>  #endif
>
> +static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
> +{
> +	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
> +}
> +
> +static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
> +{
> +	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
> +}
> +
>  static struct clk *clk_src_mpll_user_list[] = {
>  	[0] = &clk_fin_mpll,
>  	[1] = &exynos4_clk_mout_mpll.clk,
> @@ -68,7 +79,22 @@ static struct clksrc_clk clksrcs[] = {
>  };
>
>  static struct clk init_clocks_off[] = {
> -	/* nothing here yet */
> +	{
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
> +		.enable		= exynos4_clk_ip_dmc_ctrl,
> +		.ctrlbit	= (1 << 24),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
> +		.enable		= exynos4212_clk_ip_isp0_ctrl,
> +		.ctrlbit	= (7 << 8),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME2,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
> +		.enable		= exynos4212_clk_ip_isp1_ctrl,
> +		.ctrlbit	= (1 << 4),
> +	}
>  };
>
>  #ifdef CONFIG_PM_SLEEP
> diff --git a/arch/arm/mach-exynos/clock-exynos5.c
> b/arch/arm/mach-exynos/clock-exynos5.c
> index d013982..3320ad1 100644
> --- a/arch/arm/mach-exynos/clock-exynos5.c
> +++ b/arch/arm/mach-exynos/clock-exynos5.c
> @@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk
> *clk, int enable)
>  	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
>  }
>
> +static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
> +{
> +	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
> +}
> +
>  static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
>  {
>  	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
> @@ -127,6 +132,21 @@ static int exynos5_clk_ip_peris_ctrl(struct clk *clk,
> int enable)
>  	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
>  }
>
> +static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
> +{
> +	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
> +}
> +
> +static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
> +{
> +	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
> +}
> +
> +static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
> +{
> +	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
> +}
> +
>  /* Core list of CMU_CPU side */
>
>  static struct clksrc_clk exynos5_clk_mout_apll = {
> @@ -630,6 +650,76 @@ static struct clk exynos5_init_clocks_off[] = {
>  		.parent		= &exynos5_clk_aclk_66.clk,
>  		.enable		= exynos5_clk_ip_peric_ctrl,
>  		.ctrlbit	= (1 << 14),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
> +		.enable		= &exynos5_clk_ip_mfc_ctrl,
> +		.ctrlbit	= (1 << 1),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
> +		.enable		= &exynos5_clk_ip_mfc_ctrl,
> +		.ctrlbit	= (1 << 2),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(tv, 2),
> +		.enable		= &exynos5_clk_ip_disp1_ctrl,
> +		.ctrlbit	= (1 << 9)
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(jpeg, 3),
> +		.enable		= &exynos5_clk_ip_gen_ctrl,
> +		.ctrlbit	= (1 << 7),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(rot, 4),
> +		.enable		= &exynos5_clk_ip_gen_ctrl,
> +		.ctrlbit	= (1 << 6)
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(gsc0, 5),
> +		.enable		= &exynos5_clk_ip_gscl_ctrl,
> +		.ctrlbit	= (1 << 7),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(gsc1, 6),
> +		.enable		= &exynos5_clk_ip_gscl_ctrl,
> +		.ctrlbit	= (1 << 8),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(gsc2, 7),
> +		.enable		= &exynos5_clk_ip_gscl_ctrl,
> +		.ctrlbit	= (1 << 9),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(gsc3, 8),
> +		.enable		= &exynos5_clk_ip_gscl_ctrl,
> +		.ctrlbit	= (1 << 10),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
> +		.enable		= &exynos5_clk_ip_isp0_ctrl,
> +		.ctrlbit	= (0x3F << 8),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME2,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
> +		.enable		= &exynos5_clk_ip_isp1_ctrl,
> +		.ctrlbit	= (0xF << 4),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(camif0, 12),
> +		.enable		= &exynos5_clk_ip_gscl_ctrl,
> +		.ctrlbit	= (1 << 11),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(camif1, 13),
> +		.enable		= &exynos5_clk_ip_gscl_ctrl,
> +		.ctrlbit	= (1 << 12),
> +	}, {
> +		.name		= SYSMMU_CLOCK_NAME,
> +		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
> +		.enable		= &exynos5_clk_ip_acp_ctrl,
> +		.ctrlbit	= (1 << 7)
>  	}
>  };
>
> diff --git a/arch/arm/mach-exynos/dev-sysmmu.c
> b/arch/arm/mach-exynos/dev-sysmmu.c
> index 781563f..c5b1ea3 100644
> --- a/arch/arm/mach-exynos/dev-sysmmu.c
> +++ b/arch/arm/mach-exynos/dev-sysmmu.c
> @@ -1,9 +1,9 @@
> -/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
> +/* linux/arch/arm/mach-exynos/dev-sysmmu.c
>   *
> - * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
>   *		http://www.samsung.com
>   *
> - * EXYNOS4 - System MMU support
> + * EXYNOS - System MMU support
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
> @@ -12,222 +12,263 @@
>
>  #include <linux/platform_device.h>
>  #include <linux/dma-mapping.h>
> -#include <linux/export.h>
> +
> +#include <plat/cpu.h>
>
>  #include <mach/map.h>
>  #include <mach/irqs.h>
>  #include <mach/sysmmu.h>
> -#include <plat/s5p-clock.h>
> -
> -/* These names must be equal to the clock names in mach-exynos4/clock.c */
> -const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
> -	"SYSMMU_MDMA"	,
> -	"SYSMMU_SSS"	,
> -	"SYSMMU_FIMC0"	,
> -	"SYSMMU_FIMC1"	,
> -	"SYSMMU_FIMC2"	,
> -	"SYSMMU_FIMC3"	,
> -	"SYSMMU_JPEG"	,
> -	"SYSMMU_FIMD0"	,
> -	"SYSMMU_FIMD1"	,
> -	"SYSMMU_PCIe"	,
> -	"SYSMMU_G2D"	,
> -	"SYSMMU_ROTATOR",
> -	"SYSMMU_MDMA2"	,
> -	"SYSMMU_TV"	,
> -	"SYSMMU_MFC_L"	,
> -	"SYSMMU_MFC_R"	,
> -};
>
> -static struct resource exynos4_sysmmu_resource[] = {
> -	[0] = {
> -		.start	= EXYNOS4_PA_SYSMMU_MDMA,
> -		.end	= EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[1] = {
> -		.start	= IRQ_SYSMMU_MDMA0_0,
> -		.end	= IRQ_SYSMMU_MDMA0_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[2] = {
> -		.start	= EXYNOS4_PA_SYSMMU_SSS,
> -		.end	= EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[3] = {
> -		.start	= IRQ_SYSMMU_SSS_0,
> -		.end	= IRQ_SYSMMU_SSS_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[4] = {
> -		.start	= EXYNOS4_PA_SYSMMU_FIMC0,
> -		.end	= EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[5] = {
> -		.start	= IRQ_SYSMMU_FIMC0_0,
> -		.end	= IRQ_SYSMMU_FIMC0_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[6] = {
> -		.start	= EXYNOS4_PA_SYSMMU_FIMC1,
> -		.end	= EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[7] = {
> -		.start	= IRQ_SYSMMU_FIMC1_0,
> -		.end	= IRQ_SYSMMU_FIMC1_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[8] = {
> -		.start	= EXYNOS4_PA_SYSMMU_FIMC2,
> -		.end	= EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[9] = {
> -		.start	= IRQ_SYSMMU_FIMC2_0,
> -		.end	= IRQ_SYSMMU_FIMC2_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[10] = {
> -		.start	= EXYNOS4_PA_SYSMMU_FIMC3,
> -		.end	= EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[11] = {
> -		.start	= IRQ_SYSMMU_FIMC3_0,
> -		.end	= IRQ_SYSMMU_FIMC3_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[12] = {
> -		.start	= EXYNOS4_PA_SYSMMU_JPEG,
> -		.end	= EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[13] = {
> -		.start	= IRQ_SYSMMU_JPEG_0,
> -		.end	= IRQ_SYSMMU_JPEG_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[14] = {
> -		.start	= EXYNOS4_PA_SYSMMU_FIMD0,
> -		.end	= EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[15] = {
> -		.start	= IRQ_SYSMMU_LCD0_M0_0,
> -		.end	= IRQ_SYSMMU_LCD0_M0_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[16] = {
> -		.start	= EXYNOS4_PA_SYSMMU_FIMD1,
> -		.end	= EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[17] = {
> -		.start	= IRQ_SYSMMU_LCD1_M1_0,
> -		.end	= IRQ_SYSMMU_LCD1_M1_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[18] = {
> -		.start	= EXYNOS4_PA_SYSMMU_PCIe,
> -		.end	= EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[19] = {
> -		.start	= IRQ_SYSMMU_PCIE_0,
> -		.end	= IRQ_SYSMMU_PCIE_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[20] = {
> -		.start	= EXYNOS4_PA_SYSMMU_G2D,
> -		.end	= EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[21] = {
> -		.start	= IRQ_SYSMMU_2D_0,
> -		.end	= IRQ_SYSMMU_2D_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[22] = {
> -		.start	= EXYNOS4_PA_SYSMMU_ROTATOR,
> -		.end	= EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[23] = {
> -		.start	= IRQ_SYSMMU_ROTATOR_0,
> -		.end	= IRQ_SYSMMU_ROTATOR_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[24] = {
> -		.start	= EXYNOS4_PA_SYSMMU_MDMA2,
> -		.end	= EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[25] = {
> -		.start	= IRQ_SYSMMU_MDMA1_0,
> -		.end	= IRQ_SYSMMU_MDMA1_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[26] = {
> -		.start	= EXYNOS4_PA_SYSMMU_TV,
> -		.end	= EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[27] = {
> -		.start	= IRQ_SYSMMU_TV_M0_0,
> -		.end	= IRQ_SYSMMU_TV_M0_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[28] = {
> -		.start	= EXYNOS4_PA_SYSMMU_MFC_L,
> -		.end	= EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[29] = {
> -		.start	= IRQ_SYSMMU_MFC_M0_0,
> -		.end	= IRQ_SYSMMU_MFC_M0_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -	[30] = {
> -		.start	= EXYNOS4_PA_SYSMMU_MFC_R,
> -		.end	= EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[31] = {
> -		.start	= IRQ_SYSMMU_MFC_M1_0,
> -		.end	= IRQ_SYSMMU_MFC_M1_0,
> -		.flags	= IORESOURCE_IRQ,
> -	},
> -};
> +static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
> +
> +#define SYSMMU_PLATFORM_DEVICE(ipname, devid)				\
> +static struct sysmmu_platform_data platdata_##ipname = {		\
> +	.dbgname = #ipname,						\
> +};									\
> +struct platform_device SYSMMU_PLATDEV(ipname) =				\
> +{									\
> +	.name		= SYSMMU_DEVNAME_BASE,				\
> +	.id		= devid,					\
> +	.dev		= {						\
> +		.dma_mask		= &exynos_sysmmu_dma_mask,	\
> +		.coherent_dma_mask	= DMA_BIT_MASK(32),		\
> +		.platform_data		= &platdata_##ipname,		\
> +	},								\
> +}
> +
> +SYSMMU_PLATFORM_DEVICE(mfc_l,	0);
> +SYSMMU_PLATFORM_DEVICE(mfc_r,	1);
> +SYSMMU_PLATFORM_DEVICE(tv,	2);
> +SYSMMU_PLATFORM_DEVICE(jpeg,	3);
> +SYSMMU_PLATFORM_DEVICE(rot,	4);
> +SYSMMU_PLATFORM_DEVICE(fimc0,	5); /* fimc* and gsc* exist exclusively */
> +SYSMMU_PLATFORM_DEVICE(fimc1,	6);
> +SYSMMU_PLATFORM_DEVICE(fimc2,	7);
> +SYSMMU_PLATFORM_DEVICE(fimc3,	8);
> +SYSMMU_PLATFORM_DEVICE(gsc0,	5);
> +SYSMMU_PLATFORM_DEVICE(gsc1,	6);
> +SYSMMU_PLATFORM_DEVICE(gsc2,	7);
> +SYSMMU_PLATFORM_DEVICE(gsc3,	8);
> +SYSMMU_PLATFORM_DEVICE(isp,	9);
> +SYSMMU_PLATFORM_DEVICE(fimd0,	10);
> +SYSMMU_PLATFORM_DEVICE(fimd1,	11);
> +SYSMMU_PLATFORM_DEVICE(camif0,	12);
> +SYSMMU_PLATFORM_DEVICE(camif1,	13);
> +SYSMMU_PLATFORM_DEVICE(2d,	14);
> +
> +#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
> +
> +#define SYSMMU_RESOURCE(core, ipname)					\
> +	static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
> +
> +#define DEFINE_SYSMMU_RESOURCE(core, mem, irq)				\
> +	DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem),	\
> +	DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
> +
> +#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq)			\
> +	SYSMMU_RESOURCE(core, ipname) {					\
> +		DEFINE_SYSMMU_RESOURCE(core, mem, irq)			\
> +	}
>
> -struct platform_device exynos4_device_sysmmu = {
> -	.name		= "s5p-sysmmu",
> -	.id		= 32,
> -	.num_resources	= ARRAY_SIZE(exynos4_sysmmu_resource),
> -	.resource	= exynos4_sysmmu_resource,
> +struct sysmmu_resource_map {
> +	struct platform_device *pdev;
> +	struct resource *res;
> +	u32 rnum;
> +	struct device *pdd;
> +	char *clocknames;
>  };
> -EXPORT_SYMBOL(exynos4_device_sysmmu);
>
> -static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
> -void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
> -{
> -	sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
> -	if (IS_ERR(sysmmu_clk[ips]))
> -		sysmmu_clk[ips] = NULL;
> -	else
> -		clk_put(sysmmu_clk[ips]);
> +#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) {		\
> +	.pdev = &SYSMMU_PLATDEV(ipname),				\
> +	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
> +	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
> +	.clocknames = SYSMMU_CLOCK_NAME,				\
>  }
>
> -void sysmmu_clk_enable(sysmmu_ips ips)
> -{
> -	if (sysmmu_clk[ips])
> -		clk_enable(sysmmu_clk[ips]);
> +#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) {	\
> +	.pdev = &SYSMMU_PLATDEV(ipname),				\
> +	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
> +	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
> +	.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,		\
> +}
> +
> +#ifdef CONFIG_EXYNOS_DEV_PD
> +#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) {		\
> +	.pdev = &SYSMMU_PLATDEV(ipname),				\
> +	.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
> +	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
> +	.clocknames = SYSMMU_CLOCK_NAME,				\
> +	.pdd = &exynos##core##_device_pd[pd].dev,			\
> +}
> +
> +#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
> +	.pdev = &SYSMMU_PLATDEV(ipname),				\
> +	.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
> +	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
> +	.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,		\
> +	.pdd = &exynos##core##_device_pd[pd].dev,			\
>  }
> +#else
> +#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd)		\
> +		SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
> +#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata)	\
> +		SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
> +
> +#endif /* CONFIG_EXYNOS_DEV_PD */
> +
> +#ifdef CONFIG_ARCH_EXYNOS4
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0,	FIMC0,	FIMC0);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1,	FIMC1,	FIMC1);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2,	FIMC2,	FIMC2);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3,	FIMC3,	FIMC3);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg,	JPEG,	JPEG);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d,	G2D,	2D);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv,	TV,	TV_M0);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp,	2D_ACP,	2D);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot,	ROTATOR, ROTATOR);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0,	FIMD0,	LCD0_M0);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1,	FIMD1,	LCD1_M1);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0,	FIMC_LITE0, FIMC_LITE0);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1,	FIMC_LITE1, FIMC_LITE1);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r,	MFC_R,	MFC_M0);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l,	MFC_L,	MFC_M1);
> +SYSMMU_RESOURCE(EXYNOS4, isp) {
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
> +};
> +
> +static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
> +	SYSMMU_RESOURCE_MAPPING_PD(4, fimc0,	fimc0,	PD_CAM),
> +	SYSMMU_RESOURCE_MAPPING_PD(4, fimc1,	fimc1,	PD_CAM),
> +	SYSMMU_RESOURCE_MAPPING_PD(4, fimc2,	fimc2,	PD_CAM),
> +	SYSMMU_RESOURCE_MAPPING_PD(4, fimc3,	fimc3,	PD_CAM),
> +	SYSMMU_RESOURCE_MAPPING_PD(4, tv,	tv,	PD_TV),
> +	SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r,	mfc_r,	PD_MFC),
> +	SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l,	mfc_l,	PD_MFC),
> +	SYSMMU_RESOURCE_MAPPING_PD(4, rot,	rot,	PD_LCD0),
> +	SYSMMU_RESOURCE_MAPPING_PD(4, jpeg,	jpeg,	PD_CAM),
> +	SYSMMU_RESOURCE_MAPPING_PD(4, fimd0,	fimd0,	PD_LCD0),
> +};
> +
> +static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
> +	SYSMMU_RESOURCE_MAPPING_PD(4, 2d,	2d,	PD_LCD0),
> +	SYSMMU_RESOURCE_MAPPING_PD(4, fimd1,	fimd1,	PD_LCD1),
> +};
> +
> +static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
> +	SYSMMU_RESOURCE_MAPPING(4,	2d,	2d_acp),
> +	SYSMMU_RESOURCE_MAPPING_PD(4,	camif0, flite0,	PD_ISP),
> +	SYSMMU_RESOURCE_MAPPING_PD(4,	camif1, flite1,	PD_ISP),
> +	SYSMMU_RESOURCE_MAPPING_PD(4,	isp,	isp,	PD_ISP),
> +};
> +#endif /* CONFIG_ARCH_EXYNOS4 */
>
> -void sysmmu_clk_disable(sysmmu_ips ips)
> +#ifdef CONFIG_ARCH_EXYNOS5
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg,	JPEG,	JPEG);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1,	FIMD1,	FIMD1);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d,	2D,	2D);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot,	ROTATOR, ROTATOR);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv,	TV,	TV);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0,	LITE0,	LITE0);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1,	LITE1,	LITE1);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0,	GSC0,	GSC0);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1,	GSC1,	GSC1);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2,	GSC2,	GSC2);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3,	GSC3,	GSC3);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r,	MFC_R,	MFC_R);
> +SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l,	MFC_L,	MFC_L);
> +SYSMMU_RESOURCE(EXYNOS5, isp) {
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS5,	ODC, ODC),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
> +	DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
> +};
> +
> +static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
> +	SYSMMU_RESOURCE_MAPPING(5,	jpeg,	jpeg),
> +	SYSMMU_RESOURCE_MAPPING(5,	fimd1,	fimd1),
> +	SYSMMU_RESOURCE_MAPPING(5,	2d,	2d),
> +	SYSMMU_RESOURCE_MAPPING(5,	rot,	rot),
> +	SYSMMU_RESOURCE_MAPPING_PD(5,	tv,	tv,	PD_DISP1),
> +	SYSMMU_RESOURCE_MAPPING_PD(5,	camif0,	flite0,	PD_GSCL),
> +	SYSMMU_RESOURCE_MAPPING_PD(5,	camif1,	flite1,	PD_GSCL),
> +	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc0,	gsc0,	PD_GSCL),
> +	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc1,	gsc1,	PD_GSCL),
> +	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc2,	gsc2,	PD_GSCL),
> +	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc3,	gsc3,	PD_GSCL),
> +	SYSMMU_RESOURCE_MAPPING_PD(5,	mfc_r,	mfc_r,	PD_MFC),
> +	SYSMMU_RESOURCE_MAPPING_PD(5,	mfc_l,	mfc_l,	PD_MFC),
> +	SYSMMU_RESOURCE_MAPPING_MCPD(5,	isp,	isp,	PD_ISP, mc_platdata),
> +};
> +#endif /* CONFIG_ARCH_EXYNOS5 */
> +
> +static int __init init_sysmmu_platform_device(void)
>  {
> -	if (sysmmu_clk[ips])
> -		clk_disable(sysmmu_clk[ips]);
> +	int i, j;
> +	struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
> +	int nmap[2] = {0, 0};
> +
> +#ifdef CONFIG_ARCH_EXYNOS5
> +	if (soc_is_exynos5250()) {
> +		resmap[0] = sysmmu_resmap5;
> +		nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
> +		nmap[1] = 0;
> +	}
> +#endif
> +
> +#ifdef CONFIG_ARCH_EXYNOS4
> +	if (resmap[0] == NULL) {
> +		resmap[0] = sysmmu_resmap4;
> +		nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
> +	}
> +
> +	if (soc_is_exynos4210()) {
> +		resmap[1] = sysmmu_resmap4210;
> +		nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
> +	}
> +
> +	if (soc_is_exynos4412() || soc_is_exynos4212()) {
> +		resmap[1] = sysmmu_resmap4212;
> +		nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
> +	}
> +#endif
> +
> +	for (j = 0; j < 2; j++) {
> +		for (i = 0; i < nmap[j]; i++) {
> +			struct sysmmu_resource_map *map;
> +			struct sysmmu_platform_data *platdata;
> +
> +			map = &resmap[j][i];
> +
> +			map->pdev->dev.parent = map->pdd;
> +
> +			platdata = map->pdev->dev.platform_data;
> +			platdata->clockname = map->clocknames;
> +
> +			if (platform_device_add_resources(map->pdev, map->res,
> +								map->rnum)) {
> +				pr_err("%s: Failed to add device resources for "
> +						"%s.%d\n", __func__,
> +						map->pdev->name, map->pdev->id);
> +				continue;
> +			}
> +
> +			if (platform_device_register(map->pdev)) {
> +				pr_err("%s: Failed to register %s.%d\n",
> +					__func__, map->pdev->name,
> +						map->pdev->id);
> +			}
> +		}
> +	}
> +
> +	return 0;
>  }
> +arch_initcall(init_sysmmu_platform_device);
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h
> b/arch/arm/mach-exynos/include/mach/irqs.h
> index 33a119c..04646a8 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -129,23 +129,30 @@
>  #define COMBINER_GROUP(x)	((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
>  #define COMBINER_IRQ(x, y)	(COMBINER_GROUP(x) + y)
>
> -#define IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
> -#define IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
> -#define IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
> -#define IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
> -#define IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
> -#define IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
> -#define IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
> -#define IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
> -
> -#define IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
> -#define IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
> -#define IRQ_SYSMMU_LCD0_M0_0	COMBINER_IRQ(5, 2)
> -#define IRQ_SYSMMU_LCD1_M1_0	COMBINER_IRQ(5, 3)
> -#define IRQ_SYSMMU_TV_M0_0	COMBINER_IRQ(5, 4)
> -#define IRQ_SYSMMU_MFC_M0_0	COMBINER_IRQ(5, 5)
> -#define IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
> -#define IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
> +#define EXYNOS4_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
> +#define EXYNOS4_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
> +#define EXYNOS4_IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
> +#define EXYNOS4_IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
> +#define EXYNOS4_IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
> +#define EXYNOS4_IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
> +#define EXYNOS4_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
> +#define EXYNOS4_IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
> +
> +#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
> +#define EXYNOS4_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
> +#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0	COMBINER_IRQ(5, 2)
> +#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0	COMBINER_IRQ(5, 3)
> +#define EXYNOS4_IRQ_SYSMMU_TV_M0_0	COMBINER_IRQ(5, 4)
> +#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0	COMBINER_IRQ(5, 5)
> +#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
> +#define EXYNOS4_IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
> +
> +#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0	COMBINER_IRQ(16, 0)
> +#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0	COMBINER_IRQ(16, 1)
> +#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0	COMBINER_IRQ(16, 2)
> +#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0	COMBINER_IRQ(16, 3)
> +#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0	COMBINER_IRQ(16, 4)
> +#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0	COMBINER_IRQ(16, 5)
>
>  #define IRQ_FIMD0_FIFO		COMBINER_IRQ(11, 0)
>  #define IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
> @@ -275,70 +282,70 @@
>  #define IRQ_PMU			COMBINER_IRQ(1, 2)
>  #define IRQ_PMU_CPU1		COMBINER_IRQ(1, 6)
>
> -#define IRQ_SYSMMU_GSC0_0	COMBINER_IRQ(2, 0)
> -#define IRQ_SYSMMU_GSC0_1	COMBINER_IRQ(2, 1)
> -#define IRQ_SYSMMU_GSC1_0	COMBINER_IRQ(2, 2)
> -#define IRQ_SYSMMU_GSC1_1	COMBINER_IRQ(2, 3)
> -#define IRQ_SYSMMU_GSC2_0	COMBINER_IRQ(2, 4)
> -#define IRQ_SYSMMU_GSC2_1	COMBINER_IRQ(2, 5)
> -#define IRQ_SYSMMU_GSC3_0	COMBINER_IRQ(2, 6)
> -#define IRQ_SYSMMU_GSC3_1	COMBINER_IRQ(2, 7)
> -
> -#define IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(3, 2)
> -#define IRQ_SYSMMU_FIMD1_1	COMBINER_IRQ(3, 3)
> -#define IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(3, 4)
> -#define IRQ_SYSMMU_LITE0_1	COMBINER_IRQ(3, 5)
> -#define IRQ_SYSMMU_SCALERPISP_0	COMBINER_IRQ(3, 6)
> -#define IRQ_SYSMMU_SCALERPISP_1	COMBINER_IRQ(3, 7)
> -
> -#define IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(4, 0)
> -#define IRQ_SYSMMU_ROTATOR_1	COMBINER_IRQ(4, 1)
> -#define IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 2)
> -#define IRQ_SYSMMU_JPEG_1	COMBINER_IRQ(4, 3)
> -
> -#define IRQ_SYSMMU_FD_0		COMBINER_IRQ(5, 0)
> -#define IRQ_SYSMMU_FD_1		COMBINER_IRQ(5, 1)
> -#define IRQ_SYSMMU_SCALERCISP_0	COMBINER_IRQ(5, 2)
> -#define IRQ_SYSMMU_SCALERCISP_1	COMBINER_IRQ(5, 3)
> -#define IRQ_SYSMMU_MCUISP_0	COMBINER_IRQ(5, 4)
> -#define IRQ_SYSMMU_MCUISP_1	COMBINER_IRQ(5, 5)
> -#define IRQ_SYSMMU_3DNR_0	COMBINER_IRQ(5, 6)
> -#define IRQ_SYSMMU_3DNR_1	COMBINER_IRQ(5, 7)
> -
> -#define IRQ_SYSMMU_ARM_0	COMBINER_IRQ(6, 0)
> -#define IRQ_SYSMMU_ARM_1	COMBINER_IRQ(6, 1)
> -#define IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(6, 2)
> -#define IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(6, 3)
> -#define IRQ_SYSMMU_RTIC_0	COMBINER_IRQ(6, 4)
> -#define IRQ_SYSMMU_RTIC_1	COMBINER_IRQ(6, 5)
> -#define IRQ_SYSMMU_SSS_0	COMBINER_IRQ(6, 6)
> -#define IRQ_SYSMMU_SSS_1	COMBINER_IRQ(6, 7)
> -
> -#define IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(7, 0)
> -#define IRQ_SYSMMU_MDMA0_1	COMBINER_IRQ(7, 1)
> -#define IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(7, 2)
> -#define IRQ_SYSMMU_MDMA1_1	COMBINER_IRQ(7, 3)
> -#define IRQ_SYSMMU_TV_0		COMBINER_IRQ(7, 4)
> -#define IRQ_SYSMMU_TV_1		COMBINER_IRQ(7, 5)
> -#define IRQ_SYSMMU_GPSX_0	COMBINER_IRQ(7, 6)
> -#define IRQ_SYSMMU_GPSX_1	COMBINER_IRQ(7, 7)
> -
> -#define IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(8, 5)
> -#define IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(8, 6)
> -
> -#define IRQ_SYSMMU_DIS1_0	COMBINER_IRQ(9, 4)
> -#define IRQ_SYSMMU_DIS1_1	COMBINER_IRQ(9, 5)
> -
> -#define IRQ_DP			COMBINER_IRQ(10, 3)
> -#define IRQ_SYSMMU_DIS0_0	COMBINER_IRQ(10, 4)
> -#define IRQ_SYSMMU_DIS0_1	COMBINER_IRQ(10, 5)
> -#define IRQ_SYSMMU_ISP_0	COMBINER_IRQ(10, 6)
> -#define IRQ_SYSMMU_ISP_1	COMBINER_IRQ(10, 7)
> -
> -#define IRQ_SYSMMU_ODC_0	COMBINER_IRQ(11, 0)
> -#define IRQ_SYSMMU_ODC_1	COMBINER_IRQ(11, 1)
> -#define IRQ_SYSMMU_DRC_0	COMBINER_IRQ(11, 6)
> -#define IRQ_SYSMMU_DRC_1	COMBINER_IRQ(11, 7)
> +#define EXYNOS5_IRQ_SYSMMU_GSC0_0	COMBINER_IRQ(2, 0)
> +#define EXYNOS5_IRQ_SYSMMU_GSC0_1	COMBINER_IRQ(2, 1)
> +#define EXYNOS5_IRQ_SYSMMU_GSC1_0	COMBINER_IRQ(2, 2)
> +#define EXYNOS5_IRQ_SYSMMU_GSC1_1	COMBINER_IRQ(2, 3)
> +#define EXYNOS5_IRQ_SYSMMU_GSC2_0	COMBINER_IRQ(2, 4)
> +#define EXYNOS5_IRQ_SYSMMU_GSC2_1	COMBINER_IRQ(2, 5)
> +#define EXYNOS5_IRQ_SYSMMU_GSC3_0	COMBINER_IRQ(2, 6)
> +#define EXYNOS5_IRQ_SYSMMU_GSC3_1	COMBINER_IRQ(2, 7)
> +
> +#define EXYNOS5_IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(3, 2)
> +#define EXYNOS5_IRQ_SYSMMU_FIMD1_1	COMBINER_IRQ(3, 3)
> +#define EXYNOS5_IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(3, 4)
> +#define EXYNOS5_IRQ_SYSMMU_LITE0_1	COMBINER_IRQ(3, 5)
> +#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0	COMBINER_IRQ(3, 6)
> +#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1	COMBINER_IRQ(3, 7)
> +
> +#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(4, 0)
> +#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1	COMBINER_IRQ(4, 1)
> +#define EXYNOS5_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 2)
> +#define EXYNOS5_IRQ_SYSMMU_JPEG_1	COMBINER_IRQ(4, 3)
> +
> +#define EXYNOS5_IRQ_SYSMMU_FD_0		COMBINER_IRQ(5, 0)
> +#define EXYNOS5_IRQ_SYSMMU_FD_1		COMBINER_IRQ(5, 1)
> +#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0	COMBINER_IRQ(5, 2)
> +#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1	COMBINER_IRQ(5, 3)
> +#define EXYNOS5_IRQ_SYSMMU_MCUISP_0	COMBINER_IRQ(5, 4)
> +#define EXYNOS5_IRQ_SYSMMU_MCUISP_1	COMBINER_IRQ(5, 5)
> +#define EXYNOS5_IRQ_SYSMMU_3DNR_0	COMBINER_IRQ(5, 6)
> +#define EXYNOS5_IRQ_SYSMMU_3DNR_1	COMBINER_IRQ(5, 7)
> +
> +#define EXYNOS5_IRQ_SYSMMU_ARM_0	COMBINER_IRQ(6, 0)
> +#define EXYNOS5_IRQ_SYSMMU_ARM_1	COMBINER_IRQ(6, 1)
> +#define EXYNOS5_IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(6, 2)
> +#define EXYNOS5_IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(6, 3)
> +#define EXYNOS5_IRQ_SYSMMU_RTIC_0	COMBINER_IRQ(6, 4)
> +#define EXYNOS5_IRQ_SYSMMU_RTIC_1	COMBINER_IRQ(6, 5)
> +#define EXYNOS5_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(6, 6)
> +#define EXYNOS5_IRQ_SYSMMU_SSS_1	COMBINER_IRQ(6, 7)
> +
> +#define EXYNOS5_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(7, 0)
> +#define EXYNOS5_IRQ_SYSMMU_MDMA0_1	COMBINER_IRQ(7, 1)
> +#define EXYNOS5_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(7, 2)
> +#define EXYNOS5_IRQ_SYSMMU_MDMA1_1	COMBINER_IRQ(7, 3)
> +#define EXYNOS5_IRQ_SYSMMU_TV_0		COMBINER_IRQ(7, 4)
> +#define EXYNOS5_IRQ_SYSMMU_TV_1		COMBINER_IRQ(7, 5)
> +#define EXYNOS5_IRQ_SYSMMU_GPSX_0	COMBINER_IRQ(7, 6)
> +#define EXYNOS5_IRQ_SYSMMU_GPSX_1	COMBINER_IRQ(7, 7)
> +
> +#define EXYNOS5_IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(8, 5)
> +#define EXYNOS5_IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(8, 6)
> +
> +#define EXYNOS5_IRQ_SYSMMU_DIS1_0	COMBINER_IRQ(9, 4)
> +#define EXYNOS5_IRQ_SYSMMU_DIS1_1	COMBINER_IRQ(9, 5)
> +
> +#define IRQ_DP				COMBINER_IRQ(10, 3)
> +#define EXYNOS5_IRQ_SYSMMU_DIS0_0	COMBINER_IRQ(10, 4)
> +#define EXYNOS5_IRQ_SYSMMU_DIS0_1	COMBINER_IRQ(10, 5)
> +#define EXYNOS5_IRQ_SYSMMU_ISP_0	COMBINER_IRQ(10, 6)
> +#define EXYNOS5_IRQ_SYSMMU_ISP_1	COMBINER_IRQ(10, 7)
> +
> +#define EXYNOS5_IRQ_SYSMMU_ODC_0	COMBINER_IRQ(11, 0)
> +#define EXYNOS5_IRQ_SYSMMU_ODC_1	COMBINER_IRQ(11, 1)
> +#define EXYNOS5_IRQ_SYSMMU_DRC_0	COMBINER_IRQ(11, 6)
> +#define EXYNOS5_IRQ_SYSMMU_DRC_1	COMBINER_IRQ(11, 7)
>
>  #define IRQ_FIMD1_FIFO		COMBINER_IRQ(18, 4)
>  #define IRQ_FIMD1_VSYNC		COMBINER_IRQ(18, 5)
> @@ -352,11 +359,11 @@
>  #define IRQ_MCT_G2		COMBINER_IRQ(23, 5)
>  #define IRQ_MCT_G3		COMBINER_IRQ(23, 6)
>
> -#define IRQ_EINT1		COMBINER_IRQ(24, 0)
> -#define IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(24, 1)
> -#define IRQ_SYSMMU_LITE1_1	COMBINER_IRQ(24, 2)
> -#define IRQ_SYSMMU_2D_0		COMBINER_IRQ(24, 5)
> -#define IRQ_SYSMMU_2D_1		COMBINER_IRQ(24, 6)
> +#define IRQ_EINT1			COMBINER_IRQ(24, 0)
> +#define EXYNOS5_IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(24, 1)
> +#define EXYNOS5_IRQ_SYSMMU_LITE1_1	COMBINER_IRQ(24, 2)
> +#define EXYNOS5_IRQ_SYSMMU_2D_0		COMBINER_IRQ(24, 5)
> +#define EXYNOS5_IRQ_SYSMMU_2D_1		COMBINER_IRQ(24, 6)
>
>  #define IRQ_EINT2		COMBINER_IRQ(25, 0)
>  #define IRQ_EINT3		COMBINER_IRQ(25, 1)
> diff --git a/arch/arm/mach-exynos/include/mach/map.h
> b/arch/arm/mach-exynos/include/mach/map.h
> index 57c13f1..cc4c8da 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -87,6 +87,7 @@
>  #define EXYNOS4_PA_PDMA1		0x12690000
>
>  #define EXYNOS4_PA_SYSMMU_MDMA		0x10A40000
> +#define EXYNOS4_PA_SYSMMU_2D_ACP	0x10A40000
>  #define EXYNOS4_PA_SYSMMU_SSS		0x10A50000
>  #define EXYNOS4_PA_SYSMMU_FIMC0		0x11A20000
>  #define EXYNOS4_PA_SYSMMU_FIMC1		0x11A30000
> @@ -95,6 +96,12 @@
>  #define EXYNOS4_PA_SYSMMU_JPEG		0x11A60000
>  #define EXYNOS4_PA_SYSMMU_FIMD0		0x11E20000
>  #define EXYNOS4_PA_SYSMMU_FIMD1		0x12220000
> +#define EXYNOS4_PA_SYSMMU_FIMC_ISP	0x12260000
> +#define EXYNOS4_PA_SYSMMU_FIMC_DRC	0x12270000
> +#define EXYNOS4_PA_SYSMMU_FIMC_FD	0x122A0000
> +#define EXYNOS4_PA_SYSMMU_ISPCPU	0x122B0000
> +#define EXYNOS4_PA_SYSMMU_FIMC_LITE0	0x123B0000
> +#define EXYNOS4_PA_SYSMMU_FIMC_LITE1	0x123C0000
>  #define EXYNOS4_PA_SYSMMU_PCIe		0x12620000
>  #define EXYNOS4_PA_SYSMMU_G2D		0x12A20000
>  #define EXYNOS4_PA_SYSMMU_ROTATOR	0x12A30000
> @@ -102,6 +109,37 @@
>  #define EXYNOS4_PA_SYSMMU_TV		0x12E20000
>  #define EXYNOS4_PA_SYSMMU_MFC_L		0x13620000
>  #define EXYNOS4_PA_SYSMMU_MFC_R		0x13630000
> +
> +#define EXYNOS5_PA_SYSMMU_MDMA1		0x10A40000
> +#define EXYNOS5_PA_SYSMMU_SSS		0x10A50000
> +#define EXYNOS5_PA_SYSMMU_2D		0x10A60000
> +#define EXYNOS5_PA_SYSMMU_MFC_L		0x11200000
> +#define EXYNOS5_PA_SYSMMU_MFC_R		0x11210000
> +#define EXYNOS5_PA_SYSMMU_ROTATOR	0x11D40000
> +#define EXYNOS5_PA_SYSMMU_MDMA2		0x11D50000
> +#define EXYNOS5_PA_SYSMMU_JPEG		0x11F20000
> +#define EXYNOS5_PA_SYSMMU_IOP		0x12360000
> +#define EXYNOS5_PA_SYSMMU_RTIC		0x12370000
> +#define EXYNOS5_PA_SYSMMU_GPS		0x12630000
> +#define EXYNOS5_PA_SYSMMU_ISP		0x13260000
> +#define EXYNOS5_PA_SYSMMU_DRC		0x12370000
> +#define EXYNOS5_PA_SYSMMU_SCALERC	0x13280000
> +#define EXYNOS5_PA_SYSMMU_SCALERP	0x13290000
> +#define EXYNOS5_PA_SYSMMU_FD		0x132A0000
> +#define EXYNOS5_PA_SYSMMU_ISPCPU	0x132B0000
> +#define EXYNOS5_PA_SYSMMU_ODC		0x132C0000
> +#define EXYNOS5_PA_SYSMMU_DIS0		0x132D0000
> +#define EXYNOS5_PA_SYSMMU_DIS1		0x132E0000
> +#define EXYNOS5_PA_SYSMMU_3DNR		0x132F0000
> +#define EXYNOS5_PA_SYSMMU_LITE0		0x13C40000
> +#define EXYNOS5_PA_SYSMMU_LITE1		0x13C50000
> +#define EXYNOS5_PA_SYSMMU_GSC0		0x13E80000
> +#define EXYNOS5_PA_SYSMMU_GSC1		0x13E90000
> +#define EXYNOS5_PA_SYSMMU_GSC2		0x13EA0000
> +#define EXYNOS5_PA_SYSMMU_GSC3		0x13EB0000
> +#define EXYNOS5_PA_SYSMMU_FIMD1		0x14640000
> +#define EXYNOS5_PA_SYSMMU_TV		0x14650000
> +
>  #define EXYNOS4_PA_SPI0			0x13920000
>  #define EXYNOS4_PA_SPI1			0x13930000
>  #define EXYNOS4_PA_SPI2			0x13940000
> diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h
> b/arch/arm/mach-exynos/include/mach/regs-clock.h
> index 113836b..de42145 100644
> --- a/arch/arm/mach-exynos/include/mach/regs-clock.h
> +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
> @@ -130,6 +130,9 @@
>  #define EXYNOS4_CLKGATE_SCLKCPU			EXYNOS_CLKREG(0x14800)
>  #define EXYNOS4_CLKGATE_IP_CPU			EXYNOS_CLKREG(0x14900)
>
> +#define EXYNOS4_CLKGATE_IP_ISP0			EXYNOS_CLKREG(0x18800)
> +#define EXYNOS4_CLKGATE_IP_ISP1			EXYNOS_CLKREG(0x18804)
> +
>  #define EXYNOS4_APLL_LOCKTIME			(0x1C20)	/* 300us */
>
>  #define EXYNOS4_APLLCON0_ENABLE_SHIFT		(31)
> @@ -245,6 +248,8 @@
>  #define EXYNOS5_CLKDIV_PERIC0			EXYNOS_CLKREG(0x10558)
>
>  #define EXYNOS5_CLKGATE_IP_ACP			EXYNOS_CLKREG(0x08800)
> +#define EXYNOS5_CLKGATE_IP_ISP0			EXYNOS_CLKREG(0x0C800)
> +#define EXYNOS5_CLKGATE_IP_ISP1			EXYNOS_CLKREG(0x0C804)
>  #define EXYNOS5_CLKGATE_IP_GSCL			EXYNOS_CLKREG(0x10920)
>  #define EXYNOS5_CLKGATE_IP_DISP1		EXYNOS_CLKREG(0x10928)
>  #define EXYNOS5_CLKGATE_IP_MFC			EXYNOS_CLKREG(0x1092C)
> diff --git a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
> b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
> deleted file mode 100644
> index 68ff6ad..0000000
> --- a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
> - *
> - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> - *		http://www.samsung.com
> - *
> - * EXYNOS4 - System MMU register
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> -*/
> -
> -#ifndef __ASM_ARCH_REGS_SYSMMU_H
> -#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
> -
> -#define S5P_MMU_CTRL			0x000
> -#define S5P_MMU_CFG			0x004
> -#define S5P_MMU_STATUS			0x008
> -#define S5P_MMU_FLUSH			0x00C
> -#define S5P_PT_BASE_ADDR		0x014
> -#define S5P_INT_STATUS			0x018
> -#define S5P_INT_CLEAR			0x01C
> -#define S5P_PAGE_FAULT_ADDR		0x024
> -#define S5P_AW_FAULT_ADDR		0x028
> -#define S5P_AR_FAULT_ADDR		0x02C
> -#define S5P_DEFAULT_SLAVE_ADDR		0x030
> -
> -#endif /* __ASM_ARCH_REGS_SYSMMU_H */
> diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h
> b/arch/arm/mach-exynos/include/mach/sysmmu.h
> index 6a5fbb5..7fe8527 100644
> --- a/arch/arm/mach-exynos/include/mach/sysmmu.h
> +++ b/arch/arm/mach-exynos/include/mach/sysmmu.h
> @@ -1,46 +1,62 @@
> -/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
> - *
> - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
> +/*
> + * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
>   *		http://www.samsung.com
>   *
> - * Samsung sysmmu driver for EXYNOS4
> + * EXYNOS - System MMU support
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
>   * published by the Free Software Foundation.
> -*/
> -
> -#ifndef __ASM_ARM_ARCH_SYSMMU_H
> -#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
> -
> -enum exynos4_sysmmu_ips {
> -	SYSMMU_MDMA,
> -	SYSMMU_SSS,
> -	SYSMMU_FIMC0,
> -	SYSMMU_FIMC1,
> -	SYSMMU_FIMC2,
> -	SYSMMU_FIMC3,
> -	SYSMMU_JPEG,
> -	SYSMMU_FIMD0,
> -	SYSMMU_FIMD1,
> -	SYSMMU_PCIe,
> -	SYSMMU_G2D,
> -	SYSMMU_ROTATOR,
> -	SYSMMU_MDMA2,
> -	SYSMMU_TV,
> -	SYSMMU_MFC_L,
> -	SYSMMU_MFC_R,
> -	EXYNOS4_SYSMMU_TOTAL_IPNUM,
> + */
> +
> +#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
> +#define _ARM_MACH_EXYNOS_SYSMMU_H_
> +
> +struct sysmmu_platform_data {
> +	char *dbgname;
> +	/* comma(,) separated list of clock names for clock gating */
Do you use the clock gating instead of runtime pm?
> +	char *clockname;
>  };
>
> -#define S5P_SYSMMU_TOTAL_IPNUM		EXYNOS4_SYSMMU_TOTAL_IPNUM
> +#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
> +
> +#define SYSMMU_CLOCK_NAME "sysmmu"
> +#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
What's the meaning of "mc"?
> +
> +#ifdef CONFIG_EXYNOS_DEV_SYSMMU
> +#include <linux/device.h>
> +struct platform_device;
> +
> +#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
> +
> +extern struct platform_device SYSMMU_PLATDEV(mfc_l);
> +extern struct platform_device SYSMMU_PLATDEV(mfc_r);
> +extern struct platform_device SYSMMU_PLATDEV(tv);
> +extern struct platform_device SYSMMU_PLATDEV(jpeg);
> +extern struct platform_device SYSMMU_PLATDEV(rot);
Where's the fimc platform_device?

I think you only tested it with exynos5.
> +extern struct platform_device SYSMMU_PLATDEV(gsc0);
> +extern struct platform_device SYSMMU_PLATDEV(gsc1);
> +extern struct platform_device SYSMMU_PLATDEV(gsc2);
> +extern struct platform_device SYSMMU_PLATDEV(gsc3);
> +extern struct platform_device SYSMMU_PLATDEV(isp);
> +extern struct platform_device SYSMMU_PLATDEV(fimd0);
> +extern struct platform_device SYSMMU_PLATDEV(fimd1);
> +extern struct platform_device SYSMMU_PLATDEV(camif0);
> +extern struct platform_device SYSMMU_PLATDEV(camif1);
> +extern struct platform_device SYSMMU_PLATDEV(2d);
>
> -extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
> +#ifdef CONFIG_IOMMU_API
> +static inline void platform_set_sysmmu(
> +				struct device *sysmmu, struct device *dev)
> +{
> +	dev->archdata.iommu = sysmmu;
> +}
> +#endif
>
> -typedef enum exynos4_sysmmu_ips sysmmu_ips;
> +#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
> +#define platform_set_sysmmu(dev, sysmmu) do { } while (0)
> +#endif
>
> -void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
> -void sysmmu_clk_enable(sysmmu_ips ips);
> -void sysmmu_clk_disable(sysmmu_ips ips);
> +#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
>
> -#endif /* __ASM_ARM_ARCH_SYSMMU_H */
> +#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
> diff --git a/arch/arm/mach-exynos/mach-armlex4210.c
> b/arch/arm/mach-exynos/mach-armlex4210.c
> index a1e7007..6ab171c 100644
> --- a/arch/arm/mach-exynos/mach-armlex4210.c
> +++ b/arch/arm/mach-exynos/mach-armlex4210.c
> @@ -154,7 +154,6 @@ static struct platform_device *armlex4210_devices[]
> __initdata = {
>  	&s3c_device_hsmmc3,
>  	&s3c_device_rtc,
>  	&s3c_device_wdt,
> -	&exynos4_device_sysmmu,
>  	&samsung_asoc_dma,
>  	&armlex4210_smsc911x,
>  	&exynos4_device_ahci,
> diff --git a/arch/arm/mach-exynos/mach-smdkv310.c
> b/arch/arm/mach-exynos/mach-smdkv310.c
> index 2b71f18..49975ad 100644
> --- a/arch/arm/mach-exynos/mach-smdkv310.c
> +++ b/arch/arm/mach-exynos/mach-smdkv310.c
> @@ -275,7 +275,6 @@ static struct platform_device *smdkv310_devices[]
> __initdata = {
>  	&s5p_device_mfc_l,
>  	&s5p_device_mfc_r,
>  	&exynos4_device_spdif,
> -	&exynos4_device_sysmmu,
>  	&samsung_asoc_dma,
>  	&samsung_asoc_idma,
>  	&s5p_device_fimd0,
> --
> 1.7.1
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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> Please read the FAQ at  http://www.tux.org/lkml/
>


From haojian.zhuang at gmail.com  Tue Mar  6 05:04:39 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 6 Mar 2012 18:04:39 +0800
Subject: [GIT PULL][v3.4] pull request on arch-pxa for regulator branch
In-Reply-To: <20120306095226.GB19635@opensource.wolfsonmicro.com>
References: <CAN1soZxJO8sGZwq5LhuEOxt3uEN=s1cAOSXfbR8L5r8Hpc+t-w@mail.gmail.com>
 <20120306095226.GB19635@opensource.wolfsonmicro.com>
Message-ID: <CAN1soZyedZFX-RqpFLpf2HFt8+6yMjNFnPHJjxixY6sfE9e+Cg@mail.gmail.com>

On Tue, Mar 6, 2012 at 5:52 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Tue, Mar 06, 2012 at 02:08:12PM +0800, Haojian Zhuang wrote:
>
>> Heiko St?bner (2):
>> ? ? ? pxa: magician/hx4700: Convert to gpio-regulator from bq24022
>> ? ? ? regulator: Remove bq24022 regulator driver
>
> Please wait for some confirmation before you go deleting drivers from
> other subsystems! ?I don't recall replying to this thread at all...

I'm sorry. I'll revert this pull request.

Thanks
Haojian


From haojian.zhuang at gmail.com  Tue Mar  6 05:05:43 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 6 Mar 2012 18:05:43 +0800
Subject: [GIT PULL][v3.4] pull request on arch-pxa for regulator branch
In-Reply-To: <CAN1soZxJO8sGZwq5LhuEOxt3uEN=s1cAOSXfbR8L5r8Hpc+t-w@mail.gmail.com>
References: <CAN1soZxJO8sGZwq5LhuEOxt3uEN=s1cAOSXfbR8L5r8Hpc+t-w@mail.gmail.com>
Message-ID: <CAN1soZxrEm+7wvNmS8s0HSu6VYqmK1bkvGBXzWjk8E8_27ozpQ@mail.gmail.com>

On Tue, Mar 6, 2012 at 2:08 PM, Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
> Hi Arnd,
>
> Please help to pull these from arch-pxa tree.
>
> The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
>
> ?Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)
>
> are available in the git repository at:
> ?git://github.com/hzhuang1/linux.git regulator
>
> Heiko St?bner (2):
> ? ? ?pxa: magician/hx4700: Convert to gpio-regulator from bq24022
> ? ? ?regulator: Remove bq24022 regulator driver
>
> ?arch/arm/configs/magician_defconfig | ? ?2 +-
> ?arch/arm/mach-pxa/hx4700.c ? ? ? ? ?| ? 33 ++++++--
> ?arch/arm/mach-pxa/magician.c ? ? ? ?| ? 33 ++++++--
> ?drivers/regulator/Kconfig ? ? ? ? ? | ? ?8 --
> ?drivers/regulator/Makefile ? ? ? ? ?| ? ?1 -
> ?drivers/regulator/bq24022.c ? ? ? ? | ?162 -----------------------------------
> ?include/linux/regulator/bq24022.h ? | ? 24 -----
> ?7 files changed, 55 insertions(+), 208 deletions(-)
> ?delete mode 100644 drivers/regulator/bq24022.c
> ?delete mode 100644 include/linux/regulator/bq24022.h

Hi Arnd,

Please ignore this pull request. I'm sorry on this.

Best Regards
Haojian


From govindraj.raja at ti.com  Tue Mar  6 05:05:59 2012
From: govindraj.raja at ti.com (Raja, Govindraj)
Date: Tue, 6 Mar 2012 15:35:59 +0530
Subject: [RFC PATCH] OMAP: UART: Enable tx wakeup bit in wer
In-Reply-To: <alpine.DEB.2.00.1203051321580.1430@utopia.booyaka.com>
References: <1327412249-31575-1-git-send-email-govindraj.raja@ti.com>
 <alpine.DEB.2.00.1201251217120.5324@utopia.booyaka.com>
 <alpine.DEB.2.00.1203051321580.1430@utopia.booyaka.com>
Message-ID: <CAMrsUdJqmJ75=X_Qg3vQCr7zezs0jOK8L1ri8p5K=+6ZKsRFcg@mail.gmail.com>

On Tue, Mar 6, 2012 at 1:53 AM, Paul Walmsley <paul at pwsan.com> wrote:
>
> Hello Govindraj
>
> Do you intend to update and repost this serial patch? ?Or should someone
> else deal with it? ?It would be good to get support for this additional
> wakeup bit.

Thanks for reminding.
(I had got preempted with other activities, apologies for the delay)

I see two ways of adding this tx wake-up flag.

1.) passing a feature flag from pdata and populating the feature value to wer.

2.) Duplicating the uart1/2/3 hwmod for omap3430 without dev attrib
and uart1/2/3/4
     hwmod for omap3630 with dev attribs.

Approach-2 adds unnecessary code duplication in hwmod file with and without
dev_attribs, So right now here is the patch to follow approach [1],

If its strongly recommended to use approach-2 will add it.
(My concern is the diffstat it might produce with approach-2)

--
Thanks,
Govindraj.R


[1]:

>From 867dfa7328b4219be259a204555a6baae82ec4df Mon Sep 17 00:00:00 2001
From: "Govindraj.R" <govindraj.raja at ti.com>
Date: Tue, 6 Mar 2012 15:04:47 +0530
Subject: [PATCH] OMAP: UART: enable tx wake up capability for 3630 above socs

>From omap3630 above UART wer(wakeup enable reg) has TX
wakeup capability, enable the tx wakeup bit by passing
the required feature flag from pdata.
Also add missing wer reg restore from context restore function.

Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
---
 arch/arm/mach-omap2/serial.c                  |    3 +++
 arch/arm/plat-omap/include/plat/omap-serial.h |    7 +++++++
 drivers/tty/serial/omap-serial.c              |    8 +++++++-
 3 files changed, 17 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index f590afc..eb43996 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -357,6 +357,9 @@ void __init omap_serial_init_port(struct
omap_board_data *bdata,
 	omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
 	omap_up.autosuspend_timeout = info->autosuspend_timeout;

+	if (!cpu_is_omap24xx() && !cpu_is_omap3430())
+		omap_up.has_feature = UART_FEATURE_TX_WAKEUP_EN;
+
 	/* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
 	if (!cpu_is_omap2420() && !cpu_is_ti816x())
 		omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h
b/arch/arm/plat-omap/include/plat/omap-serial.h
index 9ff4444..b4f42dc 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -61,6 +61,11 @@
 #define UART_ERRATA_i202_MDR1_ACCESS	BIT(0)
 #define UART_ERRATA_i291_DMA_FORCEIDLE	BIT(1)

+#define OMAP_UART_TX_WAKEUP_EN		BIT(7)
+
+/* Feature flags */
+#define UART_FEATURE_TX_WAKEUP_EN	BIT(0)
+
 struct omap_uart_port_info {
 	bool			dma_enabled;	/* To specify DMA Mode */
 	unsigned int		uartclk;	/* UART clock rate */
@@ -70,6 +75,7 @@ struct omap_uart_port_info {
 	unsigned int		dma_rx_timeout;
 	unsigned int		autosuspend_timeout;
 	unsigned int		dma_rx_poll_rate;
+	unsigned int		has_feature;

 	int (*get_context_loss_count)(struct device *);
 	void (*set_forceidle)(struct platform_device *);
@@ -117,6 +123,7 @@ struct uart_omap_port {
 	unsigned char		dlh;
 	unsigned char		mdr1;
 	unsigned char		scr;
+	unsigned char		wer;

 	int			use_dma;
 	/*
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index f809041..5d7330f 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -577,8 +577,10 @@ static int serial_omap_startup(struct uart_port *port)
 	up->ier = UART_IER_RLSI | UART_IER_RDI;
 	serial_out(up, UART_IER, up->ier);

+	up->wer |= OMAP_UART_WER_MOD_WKUP;
+
 	/* Enable module level wake up */
-	serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
+	serial_out(up, UART_OMAP_WER, up->wer);

 	pm_runtime_mark_last_busy(&up->pdev->dev);
 	pm_runtime_put_autosuspend(&up->pdev->dev);
@@ -1444,6 +1446,8 @@ static int serial_omap_probe(struct platform_device *pdev)
 	}
 	up->uart_dma.uart_base = mem->start;
 	up->errata = omap_up_info->errata;
+	if (omap_up_info->has_feature & UART_FEATURE_TX_WAKEUP_EN)
+		up->wer |= OMAP_UART_TX_WAKEUP_EN;

 	if (omap_up_info->dma_enabled) {
 		up->uart_dma.uart_dma_tx = dma_tx->start;
@@ -1569,6 +1573,8 @@ static void serial_omap_restore_context(struct
uart_omap_port *up)
 		serial_omap_mdr1_errataset(up, up->mdr1);
 	else
 		serial_out(up, UART_OMAP_MDR1, up->mdr1);
+
+	serial_out(up, UART_OMAP_WER, up->wer);
 }

 static int serial_omap_runtime_suspend(struct device *dev)
-- 
1.7.5.4


From linus.walleij at linaro.org  Tue Mar  6 05:08:25 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 6 Mar 2012 11:08:25 +0100
Subject: [PATCH V2 3/3] gpio: tegra: Hide tegra_gpio_enable/disable()
In-Reply-To: <1330993336-9538-3-git-send-email-swarren@nvidia.com>
References: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
 <1330993336-9538-3-git-send-email-swarren@nvidia.com>
Message-ID: <CACRpkdaZ8EBBwGis4Odh1EZS=waB0nCSZ-mtUHx48ywE81T5Ng@mail.gmail.com>

On Tue, Mar 6, 2012 at 1:22 AM, Stephen Warren <swarren at nvidia.com> wrote:

> Recent pinctrl discussions concluded that gpiolib APIs should in fact do
> whatever is required to mux a GPIO onto pins, by calling pinctrl APIs if
> required. This change implements this for the Tegra GPIO driver, and removes
> calls to the Tegra-specific APIs from drivers and board files.
>
> Cc: Chris Ball <cjb at laptop.org>
> Cc: linux-mmc at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren at nvidia.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

> Merging note: The first two (or at least the 2nd) patches can go through
> the pinctrl susbsystem without issue.

I will give Grant a chance to comment on the GPIO interaction
doc atleast, then I'll apply them.

> This patch should probably be taken
> through the Tegra tree. Once patch 2 is in pinctrl, and considered stable,
> I can just use that as a dependency for the branch containing this Tegra
> patch. I assume that this series will go into 3.5 not 3.4, but I'm willing
> to be surprised:-)

Should be possible if my pinctrl-tegra-for-next-diet branch is considered
stable and could be pulled into the Tegra tree for further augmenting
by this and other patches!

But I guess you'd need to merge some stable development base
for the rest of the pinctrl stuff as well, shall I freeze the for-next
branch with tegra diet stuff merged on top now? I can promise
to just add new patches on top of that if it helps you.

Is Olof the one to ask?

Yours,
Linus Walleij


From kgene.kim at samsung.com  Tue Mar  6 05:28:33 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 06 Mar 2012 02:28:33 -0800
Subject: [GIT PULL] Samsung fixes-4 for v3.3
Message-ID: <4F55E6D1.4080703@samsung.com>

Hi Arnd, Olof

Please pull Samsung fixes for v3.3.

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit 6b21d18ed50c7d145220b0724ea7f2613abf0f95:

   Linux 3.3-rc5 (2012-02-25 12:18:16 -0800)

are available in the git repository at:
 
ssh://gitolite at ra.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
v3.3-samsung-fixes-4

Bartlomiej Zolnierkiewicz (1):
       ARM: EXYNOS: fix touchscreen IRQ setup on Universal C210 board

Gusakov Andrey (1):
       ARM: S3C24XX: DMA resume regression fix

Heiko Stuebner (1):
       ARM: S3C24XX: Fix restart on S3C2442

Joonyoung Shim (1):
       ARM: SAMSUNG: Fix memory size for hsotg

  arch/arm/mach-exynos/mach-universal_c210.c |    2 ++
  arch/arm/mach-s3c2440/common.h             |    2 +-
  arch/arm/mach-s3c2440/mach-anubis.c        |    2 +-
  arch/arm/mach-s3c2440/mach-at2440evb.c     |    2 +-
  arch/arm/mach-s3c2440/mach-gta02.c         |    2 +-
  arch/arm/mach-s3c2440/mach-mini2440.c      |    2 +-
  arch/arm/mach-s3c2440/mach-nexcoder.c      |    2 +-
  arch/arm/mach-s3c2440/mach-osiris.c        |    2 +-
  arch/arm/mach-s3c2440/mach-rx1950.c        |    2 +-
  arch/arm/mach-s3c2440/mach-rx3715.c        |    2 +-
  arch/arm/mach-s3c2440/mach-smdk2440.c      |    2 +-
  arch/arm/mach-s3c2440/s3c2440.c            |   13 -------------
  arch/arm/mach-s3c2440/s3c244x.c            |   11 +++++++++++
  arch/arm/plat-s3c24xx/dma.c                |    2 +-
  arch/arm/plat-samsung/devs.c               |    2 +-
  15 files changed, 25 insertions(+), 25 deletions(-)


From linux at arm.linux.org.uk  Tue Mar  6 05:39:16 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 10:39:16 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <4F54053F.9070502@freescale.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
Message-ID: <20120306103916.GE17370@n2100.arm.linux.org.uk>

On Mon, Mar 05, 2012 at 12:13:52AM +0000, Tabi Timur-B04825 wrote:
> Russell King - ARM Linux wrote:
> > On Sun, Mar 04, 2012 at 11:32:50PM +0000, Tabi Timur-B04825 wrote:
> >> Russell King - ARM Linux wrote:
> >>> Is the SCR shared between capture and playback?  In that case, what
> >>> makes this read-modify-write thread safe?
> >>
> >> What's "SCR"?
> >
> > I assumed you knew the code you were commenting on.
> >
> >                  clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
> >
> > The register these functions seem to be used on appears to be called
> > 'SCR'.
> 
> Oh, I didn't know you were referencing a specific register on the part. 
> There are multiple uses of clrsetbits_be32 (and its variants) in the function.
> 
> To answer your question: I was lead to believe that the individual ALSA 
> callback functions are atomic.  So one thread should not be trying to 
> start playback while another thread is simultaneously trying to stop it.

Atomic with respect to what though?  The substream?  The PCM?  All PCMs?
Reading through the code, it turns out that the answer is the PCM, so
calls into the low level driver are serialized by a per-PCM mutex.

However, this is not true of the trigger callback - the trigger callback
does not take this mutex, but instead takes a spinlock (or two.)  Whether
this is enough to stop the capture and playback substream triggers being
called simultaneously seems to depend on whether the substreams are part
of the same group (which they probably aren't.)

So, in theory you could have the trigger method being called for the
capture device while the playback device is in the middle of being opened.
Luckily, for this case, the startup method only touches the hardware if
its the first substream being opened, and shutdown only touches the
hardware if its the last substream being closed.

However, I'm left wondering whether two trigger callbacks, one for the
playback substream and one for the capture substream could be called
simultaneously on two different CPUs.  I see nothing which prevents
this happening.


From linux at arm.linux.org.uk  Tue Mar  6 05:40:15 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 10:40:15 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <20120305002635.GA23798@opensource.wolfsonmicro.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
Message-ID: <20120306104015.GF17370@n2100.arm.linux.org.uk>

On Mon, Mar 05, 2012 at 12:26:36AM +0000, Mark Brown wrote:
> On Mon, Mar 05, 2012 at 12:13:52AM +0000, Tabi Timur-B04825 wrote:
> 
> > To answer your question: I was lead to believe that the individual ALSA 
> > callback functions are atomic.  So one thread should not be trying to 
> > start playback while another thread is simultaneously trying to stop it.
> 
> That's correct, there's ALSA level locking.

Please explain which lock prevents the capture substream trigger callback
occuring simultaneously with a playback substream trigger callback on a
SMP system.

Thanks.


From stigge at antcom.de  Tue Mar  6 05:43:57 2012
From: stigge at antcom.de (Roland Stigge)
Date: Tue, 06 Mar 2012 11:43:57 +0100
Subject: [PATCH v4] lpc32xx: Added ethernet driver: smp_wmb()
In-Reply-To: <1330987524.2538.61.camel@bwh-desktop>
References: <1330983641-32622-1-git-send-email-stigge@antcom.de>
 <1330987524.2538.61.camel@bwh-desktop>
Message-ID: <4F55EA6D.3070602@antcom.de>

On 03/05/2012 11:45 PM, Ben Hutchings wrote:
>> +	/* Clear and enable interrupts */
>> +	writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
>> +	lpc_eth_enable_int(pldat->net_base);
>> +
>> +	/* Get the next TX buffer output index */
>> +	pldat->num_used_tx_buffs = 0;
>> +	pldat->last_tx_idx =
>> +		readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
> 
> Doesn't this need to be done *before* enabling interrupts?  Also, I
> think you need an smp_wmb() so that the interrupt handler is guaranteed
> to see all these writes.

Do you mean _one_ smp_wmb() directly after lpc_eth_enable_int() (which
I'm moving behind the above code?

Note that there is no SMP in LPCs and NXP is not planning to build one
AFAIK. However, I'm fine with including smp_wmb() anyway for completeness.

Thanks in advance,

Roland


From kgene.kim at samsung.com  Tue Mar  6 05:47:08 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 06 Mar 2012 02:47:08 -0800
Subject: [GIT PULL] Samsung fixes-4 for v3.3
In-Reply-To: <4F55E6D1.4080703@samsung.com>
References: <4F55E6D1.4080703@samsung.com>
Message-ID: <4F55EB2C.6090807@samsung.com>

On 03/06/12 02:28, Kukjin Kim wrote:
> Hi Arnd, Olof
>
> Please pull Samsung fixes for v3.3.
>
> If any problems, please kindly let me know.
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> The following changes since commit
> 6b21d18ed50c7d145220b0724ea7f2613abf0f95:
>
> Linux 3.3-rc5 (2012-02-25 12:18:16 -0800)
>
> are available in the git repository at:
>
> ssh://gitolite at ra.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> v3.3-samsung-fixes-4

Oops, should be...
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git

>
> Bartlomiej Zolnierkiewicz (1):
> ARM: EXYNOS: fix touchscreen IRQ setup on Universal C210 board
>
> Gusakov Andrey (1):
> ARM: S3C24XX: DMA resume regression fix
>
> Heiko Stuebner (1):
> ARM: S3C24XX: Fix restart on S3C2442
>
> Joonyoung Shim (1):
> ARM: SAMSUNG: Fix memory size for hsotg
>
> arch/arm/mach-exynos/mach-universal_c210.c | 2 ++
> arch/arm/mach-s3c2440/common.h | 2 +-
> arch/arm/mach-s3c2440/mach-anubis.c | 2 +-
> arch/arm/mach-s3c2440/mach-at2440evb.c | 2 +-
> arch/arm/mach-s3c2440/mach-gta02.c | 2 +-
> arch/arm/mach-s3c2440/mach-mini2440.c | 2 +-
> arch/arm/mach-s3c2440/mach-nexcoder.c | 2 +-
> arch/arm/mach-s3c2440/mach-osiris.c | 2 +-
> arch/arm/mach-s3c2440/mach-rx1950.c | 2 +-
> arch/arm/mach-s3c2440/mach-rx3715.c | 2 +-
> arch/arm/mach-s3c2440/mach-smdk2440.c | 2 +-
> arch/arm/mach-s3c2440/s3c2440.c | 13 -------------
> arch/arm/mach-s3c2440/s3c244x.c | 11 +++++++++++
> arch/arm/plat-s3c24xx/dma.c | 2 +-
> arch/arm/plat-samsung/devs.c | 2 +-
> 15 files changed, 25 insertions(+), 25 deletions(-)

-- 
Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From peter.ujfalusi at ti.com  Tue Mar  6 06:03:38 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 06 Mar 2012 13:03:38 +0200
Subject: [PATCH 2/3] arm: fix compile error in
 mach-omap2/board-omap4panda.c
In-Reply-To: <1330987310-8108-3-git-send-email-paul.gortmaker@windriver.com>
References: <1330987310-8108-1-git-send-email-paul.gortmaker@windriver.com>
 <1330987310-8108-3-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <4F55EF0A.1070309@ti.com>

Hi,

On 03/06/2012 12:41 AM, Paul Gortmaker wrote:
> The commit 3c90c98a1ebbb08d95700ce8a3b7bce6286607bd (linux-next)
> 
>     "OMAP4: omap4panda: Enable audio support"
> 
> introduced population of a new struct, but chose the wrong (but
> similarly named) struct that has none of the named fields.
> 
> Change it to the struct with those fields, to fix:
> 
> arch/arm/mach-omap2/board-omap4panda.c:284: error: unknown field 'hs_left_step' specified in initializer
> arch/arm/mach-omap2/board-omap4panda.c:285: error: unknown field 'hs_right_step' specified in initializer
> arch/arm/mach-omap2/board-omap4panda.c:286: error: unknown field 'hf_left_step' specified in initializer
> arch/arm/mach-omap2/board-omap4panda.c:287: error: unknown field 'hf_right_step' specified in initializer
> arch/arm/mach-omap2/board-omap4panda.c:287: warning: large integer implicitly truncated to unsigned type

Yes, I have also noticed it.
This is because part of the twl6040 i2c conversion series has been taken
by Samuel.
He will stop carrying it further (I hope), and we are going to have a
bit different series going via audio.
Samuel did not took the panda part of the patches since it had some
other dependencies coming via audio tree.

The thing is that the panda audio support is coming via ASoC to
linux-next, so Samuel could not take the patch addressing this breakage
(mfd tree does not have the needed patches).

I'm not sure where we could apply this patch in the first place since
mfd does not have the panda audio support patches, and currently the
ASoC does not have the twl6040 i2c conversion patches either...

> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> CC: Peter Ujfalusi <peter.ujfalusi at ti.com>
> CC: Santosh Shilimkar <santosh.shilimkar at ti.com>
> CC: Tony Lindgren <tony at atomide.com>
> ---
>  arch/arm/mach-omap2/board-omap4panda.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
> index c1a852d..e919153 100644
> --- a/arch/arm/mach-omap2/board-omap4panda.c
> +++ b/arch/arm/mach-omap2/board-omap4panda.c
> @@ -279,7 +279,7 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
>  	return 0;
>  }
>  
> -static struct twl4030_codec_data twl6040_codec = {
> +static struct twl6040_codec_data twl6040_codec = {
>  	/* single-step ramp for headset and handsfree */
>  	.hs_left_step	= 0x0f,
>  	.hs_right_step	= 0x0f,


-- 
P?ter


From javier.martin at vista-silicon.com  Tue Mar  6 06:03:54 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Tue, 6 Mar 2012 12:03:54 +0100
Subject: Problems with "[PATCH 0/9] DMA engine cookie handling cleanups"
Message-ID: <CACKLOr3zFmNXYV6MW01uykp7geG=1gAkWcxYoMgLdqfzhMD9fw@mail.gmail.com>

Hi Russell,
I've just seen this series in the mailing list archives:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/087917.html

As some people already stated, patch 1/9 is missing.
In my case it is even worse: I didn't received any of the patches in
my mail-box despite being subscribed to the list.

As you'll probably have noticed, I'm doing some deep cleanup on
'imx-dma.c' file as you can see in the following patches:

[PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
[PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
[PATCH 00/14] dmaengine: imx-dma: merge dma arch code into dmaengine.

Currently, I'm waiting for Sascha and Vinod to confirm that they are
fine and merge them. However, your series seems to conflict with those
patches as it modifies imx-dma.

Regards.
-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From linux at arm.linux.org.uk  Tue Mar  6 06:07:53 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 11:07:53 +0000
Subject: Problems with "[PATCH 0/9] DMA engine cookie handling cleanups"
In-Reply-To: <CACKLOr3zFmNXYV6MW01uykp7geG=1gAkWcxYoMgLdqfzhMD9fw@mail.gmail.com>
References: <CACKLOr3zFmNXYV6MW01uykp7geG=1gAkWcxYoMgLdqfzhMD9fw@mail.gmail.com>
Message-ID: <20120306110753.GG17370@n2100.arm.linux.org.uk>

On Tue, Mar 06, 2012 at 12:03:54PM +0100, javier Martin wrote:
> Hi Russell,
> I've just seen this series in the mailing list archives:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/087917.html
> 
> As some people already stated, patch 1/9 is missing.

They weren't all sent to linux-arm-kernel - they were only sent to the
appropriate people listed in MAINTAINERS.  So if you didn't receive them,
either the patch was not touching a driver you maintain or your entries
in MAINTAINERS is incomplete.

> In my case it is even worse: I didn't received any of the patches in
> my mail-box despite being subscribed to the list.
> 
> As you'll probably have noticed, I'm doing some deep cleanup on
> 'imx-dma.c' file as you can see in the following patches:
> 
> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
> [PATCH 00/14] dmaengine: imx-dma: merge dma arch code into dmaengine.
> 
> Currently, I'm waiting for Sascha and Vinod to confirm that they are
> fine and merge them. However, your series seems to conflict with those
> patches as it modifies imx-dma.

I expect that whenever these patches get posted, there will be some kind
of conflict with some work going on somewhere else.  There's not much
which can be done to get away from that.


From mad_soft at inbox.ru  Tue Mar  6 06:19:51 2012
From: mad_soft at inbox.ru (Dmitry Artamonow)
Date: Tue, 6 Mar 2012 15:19:51 +0400
Subject: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock
 detection loop
In-Reply-To: <CANndwHav6JcqNOuOXcD1dSNUmVYAV=MJ+y+ud6202q6Dh42Vgw@mail.gmail.com>
References: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>
 <1331023544-6439-3-git-send-email-mad_soft@inbox.ru>
 <CANndwHav6JcqNOuOXcD1dSNUmVYAV=MJ+y+ud6202q6Dh42Vgw@mail.gmail.com>
Message-ID: <20120306111951.GA8494@rainbow>

On 10:38 Tue 06 Mar     , Andi wrote:
> Hi,
> 
> On Tue, Mar 6, 2012 at 9:45 AM, Dmitry Artamonow <mad_soft at inbox.ru> wrote:
> > ? ? ? ?/* Wait for the PLL to lock */
> > + ? ? ? timeout = 2000;
> > ? ? ? ?do {
> > ? ? ? ? ? ? ? ?val = pads_readl(PADS_PLL_CTL);
> > + ? ? ? ? ? ? ? mdelay(1);
> 
> why are you using an mdelay? If you need to sleep 1ms just use
> usleep_range or similar

This driver uses mdelay(1) in other places, so I just used it for the sake
of consistency. And as this code runs just one time on boot, there's not
really much harm in doing delay with busy loop instead of sleeping.

Anyway, I agree that sleeping is better than busy waiting in general, so
I can respin this patch using usleep_range, or else prepare incremental
patch on top of this, which will change all mdelay in driver to usleep_range.

-- 
Best regards,
Dmitry "MAD" Artamonow



From javier.martin at vista-silicon.com  Tue Mar  6 06:29:34 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Tue, 6 Mar 2012 12:29:34 +0100
Subject: Problems with "[PATCH 0/9] DMA engine cookie handling cleanups"
In-Reply-To: <20120306110753.GG17370@n2100.arm.linux.org.uk>
References: <CACKLOr3zFmNXYV6MW01uykp7geG=1gAkWcxYoMgLdqfzhMD9fw@mail.gmail.com>
 <20120306110753.GG17370@n2100.arm.linux.org.uk>
Message-ID: <CACKLOr2vi4HtwZKz9GXLxU7pfntPk-HLqu0mQrF7csq20a3SaA@mail.gmail.com>

On 6 March 2012 12:07, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> On Tue, Mar 06, 2012 at 12:03:54PM +0100, javier Martin wrote:
>> Hi Russell,
>> I've just seen this series in the mailing list archives:
>> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/087917.html
>>
>> As some people already stated, patch 1/9 is missing.
>
> They weren't all sent to linux-arm-kernel - they were only sent to the
> appropriate people listed in MAINTAINERS. ?So if you didn't receive them,
> either the patch was not touching a driver you maintain or your entries
> in MAINTAINERS is incomplete.

I'd like to have access to the patches in order to test them for the
imx and give you my tested-by.

>> In my case it is even worse: I didn't received any of the patches in
>> my mail-box despite being subscribed to the list.
>>
>> As you'll probably have noticed, I'm doing some deep cleanup on
>> 'imx-dma.c' file as you can see in the following patches:
>>
>> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
>> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
>> [PATCH 00/14] dmaengine: imx-dma: merge dma arch code into dmaengine.
>>
>> Currently, I'm waiting for Sascha and Vinod to confirm that they are
>> fine and merge them. However, your series seems to conflict with those
>> patches as it modifies imx-dma.
>
> I expect that whenever these patches get posted, there will be some kind
> of conflict with some work going on somewhere else. ?There's not much
> which can be done to get away from that.

Who would be in charge of solving the merge issues that may arise?
Would it be Vinod Koul, the dmaengine maintainer?

Regards.
-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From jic23 at cam.ac.uk  Tue Mar  6 06:48:32 2012
From: jic23 at cam.ac.uk (Jonathan Cameron)
Date: Tue, 06 Mar 2012 11:48:32 +0000
Subject: Status of gpio-pxa driver and dummy clock
In-Reply-To: <1330987717.23600.YahooMailClassic@web29008.mail.ird.yahoo.com>
References: <1330987717.23600.YahooMailClassic@web29008.mail.ird.yahoo.com>
Message-ID: <4F55F990.4040203@cam.ac.uk>

On 3/5/2012 10:48 PM, Paul Parsons wrote:
> --- On Mon, 5/3/12, Robert Jarzmik<robert.jarzmik at free.fr>  wrote:
>> Date: Monday, 5 March, 2012, 22:08
>> Haojian Zhuang<haojian.zhuang at gmail.com>
>> writes:
>>
>>> I missed them. Maybe I was not in the Cc list. I'll
>> append the patches
>>> to fix them.
>> Just to be sure, this is the patch which is missing for the
>> dummy clock, which
>> was not submitted before AFAIK (Jonathan, Paul, please
>> confirm).
>>
>> I added the commit text to Paul's patch, and authored it as
>> Paul's with
>> Jonathan's report. Again, Jonathan, Paul, I'd like to have
>> your agreement here.
>>
>> Haojian, if you have another patch ready, don't hesitate to
>> drop this patch and
>> take your own, as long as gpio-pxa is fixed, I'll be happy.
> I created this patch without waiting for an official fix purely to solve
> the problem for myself. I then posted it in case it would be useful to
> others. By all means use it or, if a better patch exists, drop it.
I'm carrying the exact same thing in my local tree for pxa27x so for 
that at least
I've stuck a tested-by below.  (going to loose the cam address at 
somepoint soonish
hence the kernel.org one. Really don't care though!)
>
>> Cheers.
>>
>> --
>> Robert
>>
>> 8>----
>>  From 505a23475843a8fbac077e789d911ee07e1ae9cc Mon Sep 17
>> 00:00:00 2001
>> From: Paul Parsons<lost.distance at yahoo.com>
>> Date: Sat, 3 Mar 2012 21:10:09 +0100
>> Subject: [PATCH] arch/arm: pxa add dummy clocks for gpio
>> driver
>>
>> Fix gpio driver by providing it a dummy clock. This
>> regression was introduced by the commit "ARM: pxa: add
>> dummy
>> clock for sa1100-rtc", id
>> a55b5adaf403c4d032e0871ad4ee3367782f4db6.
>>
>> Reported-by: Jonathan Cameron<jic23 at cam.ac.uk>
>> Signed-off-by: Paul Parsons<lost.distance at yahoo.com>
>> Tested-by: Robert Jarzmik<robert.jarzmik at free.fr>
Tested-by: Jonathan Cameron <jic23 at kernel.org>
>> ---
>>   arch/arm/mach-pxa/pxa25x.c |    1 +
>>   arch/arm/mach-pxa/pxa27x.c |    1 +
>>   2 files changed, 2 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-pxa/pxa25x.c
>> b/arch/arm/mach-pxa/pxa25x.c
>> index 00d6eac..d8de3e5 100644
>> --- a/arch/arm/mach-pxa/pxa25x.c
>> +++ b/arch/arm/mach-pxa/pxa25x.c
>> @@ -208,6 +208,7 @@ static struct clk_lookup
>> pxa25x_clkregs[] = {
>>       INIT_CLKREG(&clk_pxa25x_gpio11,
>> NULL, "GPIO11_CLK"),
>>       INIT_CLKREG(&clk_pxa25x_gpio12,
>> NULL, "GPIO12_CLK"),
>>       INIT_CLKREG(&clk_pxa25x_mem,
>> "pxa2xx-pcmcia", NULL),
>> +    INIT_CLKREG(&clk_dummy, "pxa-gpio",
>> NULL),
>>   };
>>
>>   static struct clk_lookup pxa25x_hwuart_clkreg =
>> diff --git a/arch/arm/mach-pxa/pxa27x.c
>> b/arch/arm/mach-pxa/pxa27x.c
>> index c1673b3..a3fabc9 100644
>> --- a/arch/arm/mach-pxa/pxa27x.c
>> +++ b/arch/arm/mach-pxa/pxa27x.c
>> @@ -229,6 +229,7 @@ static struct clk_lookup
>> pxa27x_clkregs[] = {
>>       INIT_CLKREG(&clk_pxa27x_im, NULL,
>> "IMCLK"),
>>       INIT_CLKREG(&clk_pxa27x_memc, NULL,
>> "MEMCLK"),
>>       INIT_CLKREG(&clk_pxa27x_mem,
>> "pxa2xx-pcmcia", NULL),
>> +    INIT_CLKREG(&clk_dummy, "pxa-gpio",
>> NULL),
>>   };
>>
>>   #ifdef CONFIG_PM
>> -- 
>> 1.7.5.4
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>



From vinod.koul at intel.com  Tue Mar  6 06:54:12 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Tue, 06 Mar 2012 17:24:12 +0530
Subject: [PATCH v3 2/2] dmaengine: Add support for multiple descriptors
 for imx-dma.
In-Reply-To: <1330676927-7330-1-git-send-email-javier.martin@vista-silicon.com>
References: <1330676927-7330-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331034852.24656.197.camel@vkoul-udesk3>

On Fri, 2012-03-02 at 09:28 +0100, Javier Martin wrote:
> dmaengine specifies the possibility that several descriptors
> can be queued for transfer. It also indicates that tasklets
> must be used for DMA callbacks.
> 
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> ---
Applied this and 1/2 or previous one

-- 
~Vinod



From broonie at opensource.wolfsonmicro.com  Tue Mar  6 07:02:47 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 12:02:47 +0000
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120306073900.GP16232@S2101-09.ap.freescale.net>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
 <20120305144601.GQ3224@opensource.wolfsonmicro.com>
 <20120306073900.GP16232@S2101-09.ap.freescale.net>
Message-ID: <20120306120247.GF19635@opensource.wolfsonmicro.com>

On Tue, Mar 06, 2012 at 03:39:02PM +0800, Shawn Guo wrote:
> On Mon, Mar 05, 2012 at 02:46:01PM +0000, Mark Brown wrote:

> > This you can just set in the card struct, no need for explicit code at
> > all.

> Yes, I just tried.  It also works but a little bit differently.  We
> only set_fmt for codec_dai here, while ASoC core will set_fmt for both
> codec_dai and cpu_dai if dai_link->dai_fmt is set.  However, the
> fsl_ssi does not provide .set_fmt implementation, and consequently we
> will see error message below, which does not impact functionality
> though.

>   fsl-ssi-dai 83fcc000.ssi: Failed to set DAI format: -22

> I hope we keep the code as it is now and improve later when fsl_ssi
> gets improved.

No, we should fix the core to work better in this case - not having a
DAI operation is perfectly normal and should be supported.

> > > +	ret = of_property_read_u32(np, "fsl,mux-int-port", &int_port);
> > > +	ret = of_property_read_u32(np, "fsl,mux-ext-port", &ext_port);

> > It seems very odd to have namespacing on the individual property names.
> > Why are you doing that?  The properties are already defined in terms of
> > the device binding.  Though everyone else is doing it so not really a
> > problem.

> The general device tree binding practice is we'd better have a vendor
> prefix on the property name, if the property applies on specific vendor
> drivers instead of common ones across different vendors.

There's nothing generic about this device, it only applies to a specific
combination of things and in so far as it applies to those the
properties are generic - any board combining i.MX and this CODEC is
going to have an audmux.

> > > +	/*
> > > +	 * The port numbering in the hardware manual starts at 1, while
> > > +	 * the audmux API expects it starts at 0.
> > > +	 */
> > > +	int_port--;
> > > +	ext_port--;

> > Should have error checking somewhere to make sure that the user
> > remembered this.

> Because different i.MX SoC may have different internal and external
> port number, I do not think of a way to check that.  And I would not

In that case the audmux code should be validating the arguments.

> worry about it that much, since all the hardware documents number the
> port from 1, while device tree user/author will have to look at those
> documents for the data.

OTOH the in kernel API uses a different numbering and if the user is
porting their existing code over to device tree...

> > > +	imx_audmux_v2_configure_port(int_port,
> > > +			IMX_AUDMUX_V2_PTCR_SYN |
> > > +			IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
> > > +			IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
> > > +			IMX_AUDMUX_V2_PTCR_TFSDIR |
> > > +			IMX_AUDMUX_V2_PTCR_TCLKDIR,
> > > +			IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));

> > I'm not sure we've really gained much from converting to a platform
> > driver given that the device just registers something globally...

> Converting audmux to a platform driver does not change anything about
> that.  It makes device tree support easier, and gets the audmux users
> (imx machine drivers) stay away from including <mach/audmux.h>.

It's not actually fixed anything in the APIs though and we've now also
got a race in the driver probes since the audmux now need to come up via
the device model instead of just being there - we could try to configure
the audmux with no platform driver bound.  We should really have the
audmux as at least an aux_dev in the card to make sure it's there.
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From broonie at opensource.wolfsonmicro.com  Tue Mar  6 07:06:47 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 12:06:47 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <20120306104015.GF17370@n2100.arm.linux.org.uk>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
 <20120306104015.GF17370@n2100.arm.linux.org.uk>
Message-ID: <20120306120646.GH19635@opensource.wolfsonmicro.com>

On Tue, Mar 06, 2012 at 10:40:15AM +0000, Russell King - ARM Linux wrote:
> On Mon, Mar 05, 2012 at 12:26:36AM +0000, Mark Brown wrote:
> > On Mon, Mar 05, 2012 at 12:13:52AM +0000, Tabi Timur-B04825 wrote:

> > > To answer your question: I was lead to believe that the individual ALSA 
> > > callback functions are atomic.  So one thread should not be trying to 
> > > start playback while another thread is simultaneously trying to stop it.

> > That's correct, there's ALSA level locking.

> Please explain which lock prevents the capture substream trigger callback
> occuring simultaneously with a playback substream trigger callback on a
> SMP system.

Oh, bother - that one is per substream not per stream.  Which isn't
terribly helpful.
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From eric.dumazet at gmail.com  Tue Mar  6 07:13:50 2012
From: eric.dumazet at gmail.com (Eric Dumazet)
Date: Tue, 06 Mar 2012 04:13:50 -0800
Subject: [PATCH v4] lpc32xx: Added ethernet driver
In-Reply-To: <4F55D099.5070006@antcom.de>
References: <1330983641-32622-1-git-send-email-stigge@antcom.de>
 <1330987524.2538.61.camel@bwh-desktop> <4F55D099.5070006@antcom.de>
Message-ID: <1331036030.2474.40.camel@edumazet-laptop>

Le mardi 06 mars 2012 ? 09:53 +0100, Roland Stigge a ?crit :

> Sounds reasonable, and will do it.
> 
> However, I implemented it from the example of
> drivers/net/ethernet/via/via-velocity.c:velocity_poll() - is there a
> good reason for doing it that way in the velocity driver or is it done
> incorrectly there, also?
> 

Its done in a non efficient way.

It works as is, but its not the right thing to do.
The NAPI port was very minimal on via-velocity it seems.

A better way is to hold no locks in the RX handler, allowing calls to
netif_receive_skb() [ and potential calls to xmit while handling this
incoming skbs ]

Problem of saying "we dont expect to be SMP anyway", is that this let
reference material for future drivers that will copy/paste the code,
then experience performance problems.





From broonie at opensource.wolfsonmicro.com  Tue Mar  6 07:14:30 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 12:14:30 +0000
Subject: [PATCH 2/2] regulator: Remove bq24022 regulator driver
In-Reply-To: <201203021357.44770.heiko@sntech.de>
References: <201203021355.21669.heiko@sntech.de>
 <201203021357.44770.heiko@sntech.de>
Message-ID: <20120306121429.GL19635@opensource.wolfsonmicro.com>

On Fri, Mar 02, 2012 at 01:57:44PM +0100, Heiko St?bner wrote:
> The bq24022 driver is just a specialised form of a gpio-regulator.
> 
> As all former users of it now use the gpio-regulator directly, there
> is no need to keep it around.

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
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From broonie at opensource.wolfsonmicro.com  Tue Mar  6 07:16:28 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 12:16:28 +0000
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <CAN1soZxdT=N1BtK5Jf4+Qu3GGCHPuKK1BqgfEV-D7QorjnsLpg@mail.gmail.com>
References: <1330989122-6323-1-git-send-email-paul.gortmaker@windriver.com>
 <4F55CEDB.90909@compulab.co.il>
 <CAN1soZxdT=N1BtK5Jf4+Qu3GGCHPuKK1BqgfEV-D7QorjnsLpg@mail.gmail.com>
Message-ID: <20120306121627.GM19635@opensource.wolfsonmicro.com>

On Tue, Mar 06, 2012 at 05:12:18PM +0800, Haojian Zhuang wrote:

> Could you pick up this patch since it's depend on latest change on regulator?

There's no direct dependency, there's been no need to use that struct
member for years - should be safe to just apply via the PXA tree.  If
you do want it to go via regulator please resend, I didn't keep a copy
of the patch.
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From haojian.zhuang at gmail.com  Tue Mar  6 07:22:29 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 6 Mar 2012 20:22:29 +0800
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <20120306121627.GM19635@opensource.wolfsonmicro.com>
References: <1330989122-6323-1-git-send-email-paul.gortmaker@windriver.com>
 <4F55CEDB.90909@compulab.co.il>
 <CAN1soZxdT=N1BtK5Jf4+Qu3GGCHPuKK1BqgfEV-D7QorjnsLpg@mail.gmail.com>
 <20120306121627.GM19635@opensource.wolfsonmicro.com>
Message-ID: <CAN1soZyZwi5O089WedOzX-1h4SFKHF9kf=cBxM+3J08FA1RBvA@mail.gmail.com>

On Tue, Mar 6, 2012 at 8:16 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Tue, Mar 06, 2012 at 05:12:18PM +0800, Haojian Zhuang wrote:
>
>> Could you pick up this patch since it's depend on latest change on regulator?
>
> There's no direct dependency, there's been no need to use that struct
> member for years - should be safe to just apply via the PXA tree. ?If
> you do want it to go via regulator please resend, I didn't keep a copy
> of the patch.

OK. Let me merge this patch.

Best Regards
Haojian


From linux at arm.linux.org.uk  Tue Mar  6 07:25:16 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 12:25:16 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <20120306120646.GH19635@opensource.wolfsonmicro.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
 <20120306104015.GF17370@n2100.arm.linux.org.uk>
 <20120306120646.GH19635@opensource.wolfsonmicro.com>
Message-ID: <20120306122516.GH17370@n2100.arm.linux.org.uk>

On Tue, Mar 06, 2012 at 12:06:47PM +0000, Mark Brown wrote:
> On Tue, Mar 06, 2012 at 10:40:15AM +0000, Russell King - ARM Linux wrote:
> > On Mon, Mar 05, 2012 at 12:26:36AM +0000, Mark Brown wrote:
> > > On Mon, Mar 05, 2012 at 12:13:52AM +0000, Tabi Timur-B04825 wrote:
> 
> > > > To answer your question: I was lead to believe that the individual ALSA 
> > > > callback functions are atomic.  So one thread should not be trying to 
> > > > start playback while another thread is simultaneously trying to stop it.
> 
> > > That's correct, there's ALSA level locking.
> 
> > Please explain which lock prevents the capture substream trigger callback
> > occuring simultaneously with a playback substream trigger callback on a
> > SMP system.
> 
> Oh, bother - that one is per substream not per stream.  Which isn't
> terribly helpful.

It's actually entirely right that the core shouldn't take care of this:
it's entirely possible that drivers do not have any dependencies between
the two substreams and so they should not be exposed to enforced exclusivity
between the actions of two substreams in multiprocessor systems.

Please also note that in ALSA documentation, an 'atomic' callback means
little with respect to race conditions.  All it means is that the callback
is called from a context where sleeping in the callback is not permitted.
The documentation does not say what is protected by the ALSA spinlocks and
mutexes, so without reviewing the ALSA code, driver writters have little
idea whether they need their own locks or not.


From peter.ujfalusi at ti.com  Tue Mar  6 07:27:24 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue, 06 Mar 2012 14:27:24 +0200
Subject: [PATCH 3/3] arm: more fallout from i2c conversions in
 board-omap4panda.c
In-Reply-To: <1330987310-8108-4-git-send-email-paul.gortmaker@windriver.com>
References: <1330987310-8108-1-git-send-email-paul.gortmaker@windriver.com>
 <1330987310-8108-4-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <4F5602AC.3060107@ti.com>

Hi,

On 03/06/2012 12:41 AM, Paul Gortmaker wrote:
> Commit ded0df8510778a03a2f182a0cbfe3c25788e8852 (linux-next)
> 
>    "mfd: Convert twl6040 to an i2c driver, and separate it from twl core"
> 
> appears to have done an incomplete conversion on the board-omap4panda.c
> file, leaving it with more build failures.  Comparing the changes that
> were done for board-4430sdp.c it is possible for me to whack it with a
> stick until it stops twitching, but someone who really understands this
> code needs to take a look at the conversion, and check it is done
> completely and in a way that will actually work on hardware.

This is true.
I'm sending a revert series for the twl6040 patches causing this
breakage for Samuel.
The same feature will go via audio tree because the dependencies are
queued in that feature tree.

-- 
P?ter

PS: this might fix the compile breakage with omap2_defconfig, but the
audio will not work if you enable the support for it on OMAP4.

> 
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> CC: Peter Ujfalusi <peter.ujfalusi at ti.com>
> CC: Mark Brown <broonie at opensource.wolfsonicro.com>
> CC: Samuel Ortiz <sameo at linux.intel.com>
> ---
>  arch/arm/mach-omap2/board-omap4panda.c |    5 ++---
>  1 files changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
> index e919153..16a1814 100644
> --- a/arch/arm/mach-omap2/board-omap4panda.c
> +++ b/arch/arm/mach-omap2/board-omap4panda.c
> @@ -287,16 +287,15 @@ static struct twl6040_codec_data twl6040_codec = {
>  	.hf_right_step	= 0x1d,
>  };
>  
> -static struct twl4030_audio_data twl6040_audio = {
> +static struct twl6040_platform_data twl6040_data = {
>  	.codec		= &twl6040_codec,
>  	.audpwron_gpio	= 127,
> -	.naudint_irq	= OMAP44XX_IRQ_SYS_2N,
>  	.irq_base	= TWL6040_CODEC_IRQ_BASE,
>  };
>  
>  /* Panda board uses the common PMIC configuration */
>  static struct twl4030_platform_data omap4_panda_twldata = {
> -	.audio		= &twl6040_audio,
> +   /*	.audio		= &twl6040_audio,	*/
>  };
>  
>  /*


From broonie at opensource.wolfsonmicro.com  Tue Mar  6 07:33:22 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 12:33:22 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <20120306122516.GH17370@n2100.arm.linux.org.uk>
References: <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
 <20120306104015.GF17370@n2100.arm.linux.org.uk>
 <20120306120646.GH19635@opensource.wolfsonmicro.com>
 <20120306122516.GH17370@n2100.arm.linux.org.uk>
Message-ID: <20120306123322.GP19635@opensource.wolfsonmicro.com>

On Tue, Mar 06, 2012 at 12:25:16PM +0000, Russell King - ARM Linux wrote:

> Please also note that in ALSA documentation, an 'atomic' callback means
> little with respect to race conditions.  All it means is that the callback
> is called from a context where sleeping in the callback is not permitted.
> The documentation does not say what is protected by the ALSA spinlocks and
> mutexes, so without reviewing the ALSA code, driver writters have little
> idea whether they need their own locks or not.

Well, who reads the documentation to get this stuff anyway?  As you
observe it's far from complete about what's what locked when and how so
you need to go to the code to see what's actually going on, especially
whenever you need to call back into the ALSA APIs.  Though of course I'm
pretty sure there's a bunch of uniprocessor assumptions through the body
of driver code anyway...
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From peter.ujfalusi at ti.com  Tue Mar  6 07:35:11 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue,  6 Mar 2012 14:35:11 +0200
Subject: [PATCH 0/5] MFD: Reverting twl6040 patches going for 3.4
Message-ID: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>

Hello Samuel,

this series reverts the twl6040 related patches aimed for 3.4 merge window from
MFD for-next branch.
As we already discussed the relevant patches will be going through audio since
we have some dependencies going via that route.

With this series we also fix the build breakage with omap2plus_defconfig, and
also we can make sure that the OMAP4 audio is working in linux-next.

Could you apply this series so we can push forward these changes via audio?

Thank you,
Peter
---
Peter Ujfalusi (5):
  Revert "mfd/Input/ASoC: twl6040 kconfig fixes"
  Revert "mfd: Add regulator support for twl6040 VIO, V2V1 supplies"
  Revert "ASoC: Remove twl6040 dependency on twl4030 from Kconfig"
  Revert "mfd: Convert twl6040 to an i2c driver, and separate it from
    twl core"
  Revert "mfd: Detach twl6040 from the pmic mfd driver"

 arch/arm/mach-omap2/board-4430sdp.c    |   12 ++--
 arch/arm/mach-omap2/board-generic.c    |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c |    4 +-
 arch/arm/mach-omap2/twl-common.c       |   37 +-------
 arch/arm/mach-omap2/twl-common.h       |   10 ++-
 drivers/input/misc/Kconfig             |    3 +-
 drivers/input/misc/twl6040-vibra.c     |    4 +-
 drivers/mfd/Kconfig                    |   11 +--
 drivers/mfd/twl-core.c                 |   58 +++++-------
 drivers/mfd/twl6040-core.c             |  155 ++++++++++---------------------
 include/linux/i2c/twl.h                |   12 +++
 include/linux/mfd/twl6040.h            |   29 ------
 sound/soc/codecs/Kconfig               |    3 +-
 sound/soc/codecs/twl6040.c             |    3 +-
 14 files changed, 116 insertions(+), 227 deletions(-)

-- 
1.7.8.5



From peter.ujfalusi at ti.com  Tue Mar  6 07:35:12 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue,  6 Mar 2012 14:35:12 +0200
Subject: [PATCH 1/5] Revert "mfd/Input/ASoC: twl6040 kconfig fixes"
In-Reply-To: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1331037316-7375-2-git-send-email-peter.ujfalusi@ti.com>

This reverts commit a0afdbc2665bbad5ebc81a43b820e97f56ea0582.

Reverting changes regarding to twl6040 in MFD tree since the patches will go
via the audio tree.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/input/misc/Kconfig |    2 +-
 drivers/mfd/Kconfig        |   11 ++---------
 sound/soc/codecs/Kconfig   |    3 ++-
 3 files changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 9450d4c..6a9ee24 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -368,7 +368,7 @@ config INPUT_TWL4030_VIBRA
 
 config INPUT_TWL6040_VIBRA
 	tristate "Support for TWL6040 Vibrator"
-	depends on TWL6040_CORE
+	select TWL6040_CORE
 	select INPUT_FF_MEMLESS
 	help
 	  This option enables support for TWL6040 Vibrator Driver.
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 14e1efa..880c69a 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -267,17 +267,10 @@ config TWL6030_PWM
 	  This is used to control charging LED brightness.
 
 config TWL6040_CORE
-	bool "Support for TWL6040 audio codec"
-	depends on I2C=y && GENERIC_HARDIRQS
+	bool
+	depends on I2C && GENERIC_HARDIRQS
 	select MFD_CORE
-	select REGMAP_I2C
 	default n
-	help
-	  Say yes here if you want support for Texas Instruments TWL6040 audio
-	  codec.
-	  This driver provides common support for accessing the device,
-	  additional drivers must be enabled in order to use the
-	  functionality of the device (audio, vibra).
 
 config MFD_STMPE
 	bool "Support STMicroelectronics STMPE"
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 6b4d86a..f1a1197 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -56,7 +56,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_TPA6130A2 if I2C
 	select SND_SOC_TLV320DAC33 if I2C
 	select SND_SOC_TWL4030 if TWL4030_CORE
-	select SND_SOC_TWL6040 if TWL6040_CORE
+	select SND_SOC_TWL6040 if I2C
 	select SND_SOC_UDA134X
 	select SND_SOC_UDA1380 if I2C
 	select SND_SOC_WL1273 if MFD_WL1273_CORE
@@ -274,6 +274,7 @@ config SND_SOC_TWL4030
 	tristate
 
 config SND_SOC_TWL6040
+	select TWL6040_CORE
 	tristate
 
 config SND_SOC_UDA134X
-- 
1.7.8.5



From peter.ujfalusi at ti.com  Tue Mar  6 07:35:13 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue,  6 Mar 2012 14:35:13 +0200
Subject: [PATCH 2/5] Revert "mfd: Add regulator support for twl6040 VIO,
 V2V1 supplies"
In-Reply-To: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1331037316-7375-3-git-send-email-peter.ujfalusi@ti.com>

This reverts commit c04eaf3db0589e7c9f13c992a871ae2b2eb73f4f.

Reverting changes regarding to twl6040 in MFD tree since the patches will go
via the audio tree.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/mfd/twl6040-core.c  |   41 ++++-------------------------------------
 include/linux/mfd/twl6040.h |    2 --
 2 files changed, 4 insertions(+), 39 deletions(-)

diff --git a/drivers/mfd/twl6040-core.c b/drivers/mfd/twl6040-core.c
index 58c95b4..2d6beda 100644
--- a/drivers/mfd/twl6040-core.c
+++ b/drivers/mfd/twl6040-core.c
@@ -27,7 +27,6 @@
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/kernel.h>
-#include <linux/err.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
@@ -36,10 +35,8 @@
 #include <linux/err.h>
 #include <linux/mfd/core.h>
 #include <linux/mfd/twl6040.h>
-#include <linux/regulator/consumer.h>
 
 #define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1)
-#define TWL6040_NUM_SUPPLIES	(2)
 
 int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg)
 {
@@ -527,14 +524,6 @@ static int __devinit twl6040_probe(struct i2c_client *client,
 		goto err;
 	}
 
-	twl6040->supplies = devm_kzalloc(&client->dev,
-					 sizeof(struct regulator_bulk_data) *
-					 TWL6040_NUM_SUPPLIES, GFP_KERNEL);
-	if (!twl6040->supplies) {
-		ret = -ENOMEM;
-		goto err;
-	}
-
 	twl6040->regmap = regmap_init_i2c(client, &twl6040_regmap_config);
 	if (IS_ERR(twl6040->regmap)) {
 		ret = PTR_ERR(twl6040->regmap);
@@ -543,21 +532,6 @@ static int __devinit twl6040_probe(struct i2c_client *client,
 
 	i2c_set_clientdata(client, twl6040);
 
-	twl6040->supplies[0].supply = "vio";
-	twl6040->supplies[1].supply = "v2v1";
-	ret = regulator_bulk_get(&client->dev, TWL6040_NUM_SUPPLIES,
-				 twl6040->supplies);
-	if (ret != 0) {
-		dev_err(&client->dev, "Failed to get supplies: %d\n", ret);
-		goto regulator_get_err;
-	}
-
-	ret = regulator_bulk_enable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
-	if (ret != 0) {
-		dev_err(&client->dev, "Failed to enable supplies: %d\n", ret);
-		goto power_err;
-	}
-
 	twl6040->dev = &client->dev;
 	twl6040->irq = client->irq;
 	twl6040->irq_base = pdata->irq_base;
@@ -578,13 +552,13 @@ static int __devinit twl6040_probe(struct i2c_client *client,
 		ret = gpio_request_one(twl6040->audpwron, GPIOF_OUT_INIT_LOW,
 				       "audpwron");
 		if (ret)
-			goto gpio_err;
+			goto gpio1_err;
 	}
 
 	/* codec interrupt */
 	ret = twl6040_irq_init(twl6040);
 	if (ret)
-		goto irq_init_err;
+		goto gpio2_err;
 
 	ret = request_threaded_irq(twl6040->irq_base + TWL6040_IRQ_READY,
 				   NULL, twl6040_naudint_handler, 0,
@@ -644,14 +618,10 @@ mfd_err:
 	free_irq(twl6040->irq_base + TWL6040_IRQ_READY, twl6040);
 irq_err:
 	twl6040_irq_exit(twl6040);
-irq_init_err:
+gpio2_err:
 	if (gpio_is_valid(twl6040->audpwron))
 		gpio_free(twl6040->audpwron);
-gpio_err:
-	regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
-power_err:
-	regulator_bulk_free(TWL6040_NUM_SUPPLIES, twl6040->supplies);
-regulator_get_err:
+gpio1_err:
 	i2c_set_clientdata(client, NULL);
 	regmap_exit(twl6040->regmap);
 err:
@@ -675,9 +645,6 @@ static int __devexit twl6040_remove(struct i2c_client *client)
 	i2c_set_clientdata(client, NULL);
 	regmap_exit(twl6040->regmap);
 
-	regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
-	regulator_bulk_free(TWL6040_NUM_SUPPLIES, twl6040->supplies);
-
 	return 0;
 }
 
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index bf3931e..b15b5f0 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -199,12 +199,10 @@ struct twl6040_platform_data {
 };
 
 struct regmap;
-struct regulator_bulk_data;
 
 struct twl6040 {
 	struct device *dev;
 	struct regmap *regmap;
-	struct regulator_bulk_data *supplies; /* supplies for vio, v2v1 */
 	struct mutex mutex;
 	struct mutex io_mutex;
 	struct mutex irq_mutex;
-- 
1.7.8.5



From peter.ujfalusi at ti.com  Tue Mar  6 07:35:14 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue,  6 Mar 2012 14:35:14 +0200
Subject: [PATCH 3/5] Revert "ASoC: Remove twl6040 dependency on twl4030 from
 Kconfig"
In-Reply-To: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1331037316-7375-4-git-send-email-peter.ujfalusi@ti.com>

This reverts commit 36229729d92f903a7311f1c040b33d5bab0af60b.

Reverting changes regarding to twl6040 in MFD tree since the patches will go
via the audio tree.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/codecs/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index f1a1197..7c205e7 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -56,7 +56,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_TPA6130A2 if I2C
 	select SND_SOC_TLV320DAC33 if I2C
 	select SND_SOC_TWL4030 if TWL4030_CORE
-	select SND_SOC_TWL6040 if I2C
+	select SND_SOC_TWL6040 if TWL4030_CORE
 	select SND_SOC_UDA134X
 	select SND_SOC_UDA1380 if I2C
 	select SND_SOC_WL1273 if MFD_WL1273_CORE
-- 
1.7.8.5



From peter.ujfalusi at ti.com  Tue Mar  6 07:35:15 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue,  6 Mar 2012 14:35:15 +0200
Subject: [PATCH 4/5] Revert "mfd: Convert twl6040 to an i2c driver,
 and separate it from twl core"
In-Reply-To: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1331037316-7375-5-git-send-email-peter.ujfalusi@ti.com>

This reverts commit ded0df8510778a03a2f182a0cbfe3c25788e8852.

Reverting changes regarding to twl6040 in MFD tree since the patches will go
via the audio tree.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/board-4430sdp.c    |   12 ++--
 arch/arm/mach-omap2/board-generic.c    |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c |    4 +-
 arch/arm/mach-omap2/twl-common.c       |   37 ++---------
 arch/arm/mach-omap2/twl-common.h       |   10 ++-
 drivers/input/misc/Kconfig             |    1 +
 drivers/input/misc/twl6040-vibra.c     |    4 +-
 drivers/mfd/Kconfig                    |    2 +-
 drivers/mfd/twl6040-core.c             |  114 +++++++++++++-------------------
 include/linux/i2c/twl.h                |   12 ++++
 include/linux/mfd/twl6040.h            |   27 --------
 sound/soc/codecs/twl6040.c             |    3 +-
 12 files changed, 83 insertions(+), 145 deletions(-)

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 474bcf3..4e90715 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -20,7 +20,6 @@
 #include <linux/usb/otg.h>
 #include <linux/spi/spi.h>
 #include <linux/i2c/twl.h>
-#include <linux/mfd/twl6040.h>
 #include <linux/gpio_keys.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
@@ -527,7 +526,7 @@ static struct regulator_init_data sdp4430_vusim = {
 	},
 };
 
-static struct twl6040_codec_data twl6040_codec = {
+static struct twl4030_codec_data twl6040_codec = {
 	/* single-step ramp for headset and handsfree */
 	.hs_left_step	= 0x0f,
 	.hs_right_step	= 0x0f,
@@ -535,7 +534,7 @@ static struct twl6040_codec_data twl6040_codec = {
 	.hf_right_step	= 0x1d,
 };
 
-static struct twl6040_vibra_data twl6040_vibra = {
+static struct twl4030_vibra_data twl6040_vibra = {
 	.vibldrv_res = 8,
 	.vibrdrv_res = 3,
 	.viblmotor_res = 10,
@@ -544,14 +543,16 @@ static struct twl6040_vibra_data twl6040_vibra = {
 	.vddvibr_uV = 0,	/* fixed volt supply - VBAT */
 };
 
-static struct twl6040_platform_data twl6040_data = {
+static struct twl4030_audio_data twl6040_audio = {
 	.codec		= &twl6040_codec,
 	.vibra		= &twl6040_vibra,
 	.audpwron_gpio	= 127,
+	.naudint_irq	= OMAP44XX_IRQ_SYS_2N,
 	.irq_base	= TWL6040_CODEC_IRQ_BASE,
 };
 
 static struct twl4030_platform_data sdp4430_twldata = {
+	.audio		= &twl6040_audio,
 	/* Regulators */
 	.vusim		= &sdp4430_vusim,
 	.vaux1		= &sdp4430_vaux1,
@@ -582,8 +583,7 @@ static int __init omap4_i2c_init(void)
 			TWL_COMMON_REGULATOR_VCXIO |
 			TWL_COMMON_REGULATOR_VUSB |
 			TWL_COMMON_REGULATOR_CLK32KG);
-	omap4_pmic_init("twl6030", &sdp4430_twldata,
-			&twl6040_data, OMAP44XX_IRQ_SYS_2N);
+	omap4_pmic_init("twl6030", &sdp4430_twldata);
 	omap_register_i2c_bus(2, 400, NULL, 0);
 	omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
 				ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 42f6a27..ad49762 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -36,7 +36,7 @@ static struct twl4030_platform_data sdp4430_twldata = {
 
 static void __init omap4_i2c_init(void)
 {
-	omap4_pmic_init("twl6030", &sdp4430_twldata, NULL, 0);
+	omap4_pmic_init("twl6030", &sdp4430_twldata);
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index c39d6d5..28fc271 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -25,7 +25,6 @@
 #include <linux/gpio.h>
 #include <linux/usb/otg.h>
 #include <linux/i2c/twl.h>
-#include <linux/mfd/twl6040.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/wl12xx.h>
@@ -278,8 +277,7 @@ static int __init omap4_panda_i2c_init(void)
 			TWL_COMMON_REGULATOR_VCXIO |
 			TWL_COMMON_REGULATOR_VUSB |
 			TWL_COMMON_REGULATOR_CLK32KG);
-	omap4_pmic_init("twl6030", &omap4_panda_twldata,
-			&twl6040_data, OMAP44XX_IRQ_SYS_2N);
+	omap4_pmic_init("twl6030", &omap4_panda_twldata);
 	omap_register_i2c_bus(2, 400, NULL, 0);
 	/*
 	 * Bus 3 is attached to the DVI port where devices like the pico DLP
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index bc03154..10b20c6 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -37,16 +37,6 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = {
 	.flags		= I2C_CLIENT_WAKE,
 };
 
-static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
-	{
-		.addr		= 0x48,
-		.flags		= I2C_CLIENT_WAKE,
-	},
-	{
-		I2C_BOARD_INFO("twl6040", 0x4b),
-	},
-};
-
 void __init omap_pmic_init(int bus, u32 clkrate,
 			   const char *pmic_type, int pmic_irq,
 			   struct twl4030_platform_data *pmic_data)
@@ -59,31 +49,14 @@ void __init omap_pmic_init(int bus, u32 clkrate,
 	omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
 }
 
-void omap4_pmic_init(const char *pmic_type,
-		    struct twl4030_platform_data *pmic_data,
-		    struct twl6040_platform_data *twl6040_data, int twl6040_irq)
-{
-	/* PMIC part*/
-	strncpy(omap4_i2c1_board_info[0].type, pmic_type,
-		sizeof(omap4_i2c1_board_info[0].type));
-	omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
-	omap4_i2c1_board_info[0].platform_data = pmic_data;
-
-	/* TWL6040 audio IC part */
-	omap4_i2c1_board_info[1].irq = twl6040_irq;
-	omap4_i2c1_board_info[1].platform_data = twl6040_data;
-
-	omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2);
-
-}
-
 void __init omap_pmic_late_init(void)
 {
 	/* Init the OMAP TWL parameters (if PMIC has been registerd) */
-	if (pmic_i2c_board_info.irq)
-		omap3_twl_init();
-	if (omap4_i2c1_board_info[0].irq)
-		omap4_twl_init();
+	if (!pmic_i2c_board_info.irq)
+		return;
+
+	omap3_twl_init();
+	omap4_twl_init();
 }
 
 #if defined(CONFIG_ARCH_OMAP3)
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index 0962748..275dde8 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -29,7 +29,6 @@
 
 
 struct twl4030_platform_data;
-struct twl6040_platform_data;
 
 void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
 		    struct twl4030_platform_data *pmic_data);
@@ -47,9 +46,12 @@ static inline void omap3_pmic_init(const char *pmic_type,
 	omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
 }
 
-void omap4_pmic_init(const char *pmic_type,
-		    struct twl4030_platform_data *pmic_data,
-		    struct twl6040_platform_data *audio_data, int twl6040_irq);
+static inline void omap4_pmic_init(const char *pmic_type,
+				   struct twl4030_platform_data *pmic_data)
+{
+	/* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
+	omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
+}
 
 void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 			   u32 pdata_flags, u32 regulators_flags);
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 6a9ee24..7b46781 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -368,6 +368,7 @@ config INPUT_TWL4030_VIBRA
 
 config INPUT_TWL6040_VIBRA
 	tristate "Support for TWL6040 Vibrator"
+	depends on TWL4030_CORE
 	select TWL6040_CORE
 	select INPUT_FF_MEMLESS
 	help
diff --git a/drivers/input/misc/twl6040-vibra.c b/drivers/input/misc/twl6040-vibra.c
index 14e94f5..45874fe 100644
--- a/drivers/input/misc/twl6040-vibra.c
+++ b/drivers/input/misc/twl6040-vibra.c
@@ -28,7 +28,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/workqueue.h>
-#include <linux/input.h>
+#include <linux/i2c/twl.h>
 #include <linux/mfd/twl6040.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
@@ -257,7 +257,7 @@ static SIMPLE_DEV_PM_OPS(twl6040_vibra_pm_ops, twl6040_vibra_suspend, NULL);
 
 static int __devinit twl6040_vibra_probe(struct platform_device *pdev)
 {
-	struct twl6040_vibra_data *pdata = pdev->dev.platform_data;
+	struct twl4030_vibra_data *pdata = pdev->dev.platform_data;
 	struct vibra_info *info;
 	int ret;
 
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 880c69a..82da448 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -268,7 +268,7 @@ config TWL6030_PWM
 
 config TWL6040_CORE
 	bool
-	depends on I2C && GENERIC_HARDIRQS
+	depends on TWL4030_CORE && GENERIC_HARDIRQS
 	select MFD_CORE
 	default n
 
diff --git a/drivers/mfd/twl6040-core.c b/drivers/mfd/twl6040-core.c
index 2d6beda..b2d8e51 100644
--- a/drivers/mfd/twl6040-core.c
+++ b/drivers/mfd/twl6040-core.c
@@ -30,9 +30,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/regmap.h>
-#include <linux/err.h>
+#include <linux/i2c/twl.h>
 #include <linux/mfd/core.h>
 #include <linux/mfd/twl6040.h>
 
@@ -41,7 +39,7 @@
 int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg)
 {
 	int ret;
-	unsigned int val;
+	u8 val = 0;
 
 	mutex_lock(&twl6040->io_mutex);
 	/* Vibra control registers from cache */
@@ -49,7 +47,7 @@ int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg)
 		     reg == TWL6040_REG_VIBCTLR)) {
 		val = twl6040->vibra_ctrl_cache[VIBRACTRL_MEMBER(reg)];
 	} else {
-		ret = regmap_read(twl6040->regmap, reg, &val);
+		ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg);
 		if (ret < 0) {
 			mutex_unlock(&twl6040->io_mutex);
 			return ret;
@@ -66,7 +64,7 @@ int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val)
 	int ret;
 
 	mutex_lock(&twl6040->io_mutex);
-	ret = regmap_write(twl6040->regmap, reg, val);
+	ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg);
 	/* Cache the vibra control registers */
 	if (reg == TWL6040_REG_VIBCTLL || reg == TWL6040_REG_VIBCTLR)
 		twl6040->vibra_ctrl_cache[VIBRACTRL_MEMBER(reg)] = val;
@@ -79,9 +77,16 @@ EXPORT_SYMBOL(twl6040_reg_write);
 int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
 {
 	int ret;
+	u8 val;
 
 	mutex_lock(&twl6040->io_mutex);
-	ret = regmap_update_bits(twl6040->regmap, reg, mask, mask);
+	ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg);
+	if (ret)
+		goto out;
+
+	val |= mask;
+	ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg);
+out:
 	mutex_unlock(&twl6040->io_mutex);
 	return ret;
 }
@@ -90,9 +95,16 @@ EXPORT_SYMBOL(twl6040_set_bits);
 int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
 {
 	int ret;
+	u8 val;
 
 	mutex_lock(&twl6040->io_mutex);
-	ret = regmap_update_bits(twl6040->regmap, reg, mask, 0);
+	ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg);
+	if (ret)
+		goto out;
+
+	val &= ~mask;
+	ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg);
+out:
 	mutex_unlock(&twl6040->io_mutex);
 	return ret;
 }
@@ -482,58 +494,32 @@ static struct resource twl6040_codec_rsrc[] = {
 	},
 };
 
-static bool twl6040_readable_reg(struct device *dev, unsigned int reg)
+static int __devinit twl6040_probe(struct platform_device *pdev)
 {
-	/* Register 0 is not readable */
-	if (!reg)
-		return false;
-	return true;
-}
-
-static struct regmap_config twl6040_regmap_config = {
-	.reg_bits = 8,
-	.val_bits = 8,
-	.max_register = TWL6040_REG_STATUS, /* 0x2e */
-
-	.readable_reg = twl6040_readable_reg,
-};
-
-static int __devinit twl6040_probe(struct i2c_client *client,
-				     const struct i2c_device_id *id)
-{
-	struct twl6040_platform_data *pdata = client->dev.platform_data;
+	struct twl4030_audio_data *pdata = pdev->dev.platform_data;
 	struct twl6040 *twl6040;
 	struct mfd_cell *cell = NULL;
 	int ret, children = 0;
 
 	if (!pdata) {
-		dev_err(&client->dev, "Platform data is missing\n");
+		dev_err(&pdev->dev, "Platform data is missing\n");
 		return -EINVAL;
 	}
 
 	/* In order to operate correctly we need valid interrupt config */
-	if (!client->irq || !pdata->irq_base) {
-		dev_err(&client->dev, "Invalid IRQ configuration\n");
+	if (!pdata->naudint_irq || !pdata->irq_base) {
+		dev_err(&pdev->dev, "Invalid IRQ configuration\n");
 		return -EINVAL;
 	}
 
-	twl6040 = devm_kzalloc(&client->dev, sizeof(struct twl6040),
-			       GFP_KERNEL);
-	if (!twl6040) {
-		ret = -ENOMEM;
-		goto err;
-	}
-
-	twl6040->regmap = regmap_init_i2c(client, &twl6040_regmap_config);
-	if (IS_ERR(twl6040->regmap)) {
-		ret = PTR_ERR(twl6040->regmap);
-		goto err;
-	}
+	twl6040 = kzalloc(sizeof(struct twl6040), GFP_KERNEL);
+	if (!twl6040)
+		return -ENOMEM;
 
-	i2c_set_clientdata(client, twl6040);
+	platform_set_drvdata(pdev, twl6040);
 
-	twl6040->dev = &client->dev;
-	twl6040->irq = client->irq;
+	twl6040->dev = &pdev->dev;
+	twl6040->irq = pdata->naudint_irq;
 	twl6040->irq_base = pdata->irq_base;
 
 	mutex_init(&twl6040->mutex);
@@ -602,12 +588,12 @@ static int __devinit twl6040_probe(struct i2c_client *client,
 	}
 
 	if (children) {
-		ret = mfd_add_devices(&client->dev, -1, twl6040->cells,
+		ret = mfd_add_devices(&pdev->dev, pdev->id, twl6040->cells,
 				      children, NULL, 0);
 		if (ret)
 			goto mfd_err;
 	} else {
-		dev_err(&client->dev, "No platform data found for children\n");
+		dev_err(&pdev->dev, "No platform data found for children\n");
 		ret = -ENODEV;
 		goto mfd_err;
 	}
@@ -622,15 +608,14 @@ gpio2_err:
 	if (gpio_is_valid(twl6040->audpwron))
 		gpio_free(twl6040->audpwron);
 gpio1_err:
-	i2c_set_clientdata(client, NULL);
-	regmap_exit(twl6040->regmap);
-err:
+	platform_set_drvdata(pdev, NULL);
+	kfree(twl6040);
 	return ret;
 }
 
-static int __devexit twl6040_remove(struct i2c_client *client)
+static int __devexit twl6040_remove(struct platform_device *pdev)
 {
-	struct twl6040 *twl6040 = i2c_get_clientdata(client);
+	struct twl6040 *twl6040 = platform_get_drvdata(pdev);
 
 	if (twl6040->power_count)
 		twl6040_power(twl6040, 0);
@@ -641,30 +626,23 @@ static int __devexit twl6040_remove(struct i2c_client *client)
 	free_irq(twl6040->irq_base + TWL6040_IRQ_READY, twl6040);
 	twl6040_irq_exit(twl6040);
 
-	mfd_remove_devices(&client->dev);
-	i2c_set_clientdata(client, NULL);
-	regmap_exit(twl6040->regmap);
+	mfd_remove_devices(&pdev->dev);
+	platform_set_drvdata(pdev, NULL);
+	kfree(twl6040);
 
 	return 0;
 }
 
-static const struct i2c_device_id twl6040_i2c_id[] = {
-	{ "twl6040", 0, },
-	{ },
-};
-MODULE_DEVICE_TABLE(i2c, twl6040_i2c_id);
-
-static struct i2c_driver twl6040_driver = {
-	.driver = {
-		.name = "twl6040",
-		.owner = THIS_MODULE,
-	},
+static struct platform_driver twl6040_driver = {
 	.probe		= twl6040_probe,
 	.remove		= __devexit_p(twl6040_remove),
-	.id_table	= twl6040_i2c_id,
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "twl6040",
+	},
 };
 
-module_i2c_driver(twl6040_driver);
+module_platform_driver(twl6040_driver);
 
 MODULE_DESCRIPTION("TWL6040 MFD");
 MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez at ti.com>");
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 3826a53..78d3465 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -666,11 +666,23 @@ struct twl4030_codec_data {
 	unsigned int check_defaults:1;
 	unsigned int reset_registers:1;
 	unsigned int hs_extmute:1;
+	u16 hs_left_step;
+	u16 hs_right_step;
+	u16 hf_left_step;
+	u16 hf_right_step;
 	void (*set_hs_extmute)(int mute);
 };
 
 struct twl4030_vibra_data {
 	unsigned int	coexist;
+
+	/* twl6040 */
+	unsigned int vibldrv_res;	/* left driver resistance */
+	unsigned int vibrdrv_res;	/* right driver resistance */
+	unsigned int viblmotor_res;	/* left motor resistance */
+	unsigned int vibrmotor_res;	/* right motor resistance */
+	int vddvibl_uV;			/* VDDVIBL volt, set 0 for fixed reg */
+	int vddvibr_uV;			/* VDDVIBR volt, set 0 for fixed reg */
 };
 
 struct twl4030_audio_data {
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index b15b5f0..9bc9ac6 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -174,35 +174,8 @@
 #define TWL6040_SYSCLK_SEL_LPPLL	0
 #define TWL6040_SYSCLK_SEL_HPPLL	1
 
-struct twl6040_codec_data {
-	u16 hs_left_step;
-	u16 hs_right_step;
-	u16 hf_left_step;
-	u16 hf_right_step;
-};
-
-struct twl6040_vibra_data {
-	unsigned int vibldrv_res;	/* left driver resistance */
-	unsigned int vibrdrv_res;	/* right driver resistance */
-	unsigned int viblmotor_res;	/* left motor resistance */
-	unsigned int vibrmotor_res;	/* right motor resistance */
-	int vddvibl_uV;			/* VDDVIBL volt, set 0 for fixed reg */
-	int vddvibr_uV;			/* VDDVIBR volt, set 0 for fixed reg */
-};
-
-struct twl6040_platform_data {
-	int audpwron_gpio;	/* audio power-on gpio */
-	unsigned int irq_base;
-
-	struct twl6040_codec_data *codec;
-	struct twl6040_vibra_data *vibra;
-};
-
-struct regmap;
-
 struct twl6040 {
 	struct device *dev;
-	struct regmap *regmap;
 	struct mutex mutex;
 	struct mutex io_mutex;
 	struct mutex irq_mutex;
diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c
index 406eeee..5b9c79b 100644
--- a/sound/soc/codecs/twl6040.c
+++ b/sound/soc/codecs/twl6040.c
@@ -26,6 +26,7 @@
 #include <linux/pm.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/i2c/twl.h>
 #include <linux/mfd/twl6040.h>
 
 #include <sound/core.h>
@@ -1514,7 +1515,7 @@ static int twl6040_resume(struct snd_soc_codec *codec)
 static int twl6040_probe(struct snd_soc_codec *codec)
 {
 	struct twl6040_data *priv;
-	struct twl6040_codec_data *pdata = dev_get_platdata(codec->dev);
+	struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
 	struct platform_device *pdev = container_of(codec->dev,
 						   struct platform_device, dev);
 	int ret = 0;
-- 
1.7.8.5



From peter.ujfalusi at ti.com  Tue Mar  6 07:35:16 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Tue,  6 Mar 2012 14:35:16 +0200
Subject: [PATCH 5/5] Revert "mfd: Detach twl6040 from the pmic mfd driver"
In-Reply-To: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1331037316-7375-6-git-send-email-peter.ujfalusi@ti.com>

This reverts commit 49976f5f8ec350ee0e1191237bb06325840ae5d9.

Reverting changes regarding to twl6040 in MFD tree since the patches will go
via the audio tree.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 drivers/mfd/twl-core.c |   58 ++++++++++++++++++++---------------------------
 1 files changed, 25 insertions(+), 33 deletions(-)

diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 6c236d0..c1e4f1a 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -115,8 +115,8 @@
 #define twl_has_watchdog()        false
 #endif
 
-#if defined(CONFIG_MFD_TWL4030_AUDIO) || \
-	defined(CONFIG_MFD_TWL4030_AUDIO_MODULE)
+#if defined(CONFIG_MFD_TWL4030_AUDIO) || defined(CONFIG_MFD_TWL4030_AUDIO_MODULE) ||\
+	defined(CONFIG_TWL6040_CORE) || defined(CONFIG_TWL6040_CORE_MODULE)
 #define twl_has_codec()	true
 #else
 #define twl_has_codec()	false
@@ -146,7 +146,6 @@
 #define SUB_CHIP_ID1 1
 #define SUB_CHIP_ID2 2
 #define SUB_CHIP_ID3 3
-#define SUB_CHIP_ID_INVAL 0xff
 
 #define TWL_MODULE_LAST TWL4030_MODULE_LAST
 
@@ -318,7 +317,7 @@ static struct twl_mapping twl6030_map[] = {
 	 * so they continue to match the order in this table.
 	 */
 	{ SUB_CHIP_ID1, TWL6030_BASEADD_USB },
-	{ SUB_CHIP_ID_INVAL, TWL6030_BASEADD_AUDIO },
+	{ SUB_CHIP_ID3, TWL6030_BASEADD_AUDIO },
 	{ SUB_CHIP_ID2, TWL6030_BASEADD_DIEID },
 	{ SUB_CHIP_ID2, TWL6030_BASEADD_RSV },
 	{ SUB_CHIP_ID1, TWL6030_BASEADD_PIH },
@@ -380,11 +379,6 @@ int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
 		return -EPERM;
 	}
 	sid = twl_map[mod_no].sid;
-	if (unlikely(sid == SUB_CHIP_ID_INVAL)) {
-		pr_err("%s: module %d is not part of the pmic\n",
-		       DRIVER_NAME, mod_no);
-		return -EINVAL;
-	}
 	twl = &twl_modules[sid];
 
 	mutex_lock(&twl->xfer_lock);
@@ -442,11 +436,6 @@ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
 		return -EPERM;
 	}
 	sid = twl_map[mod_no].sid;
-	if (unlikely(sid == SUB_CHIP_ID_INVAL)) {
-		pr_err("%s: module %d is not part of the pmic\n",
-		       DRIVER_NAME, mod_no);
-		return -EINVAL;
-	}
 	twl = &twl_modules[sid];
 
 	mutex_lock(&twl->xfer_lock);
@@ -847,6 +836,15 @@ add_children(struct twl4030_platform_data *pdata, unsigned long features)
 			return PTR_ERR(child);
 	}
 
+	if (twl_has_codec() && pdata->audio && twl_class_is_6030()) {
+		sub_chip_id = twl_map[TWL_MODULE_AUDIO_VOICE].sid;
+		child = add_child(sub_chip_id, "twl6040",
+				pdata->audio, sizeof(*pdata->audio),
+				false, 0, 0);
+		if (IS_ERR(child))
+			return PTR_ERR(child);
+	}
+
 	/* twl4030 regulators */
 	if (twl_has_regulator() && twl_class_is_4030()) {
 		child = add_regulator(TWL4030_REG_VPLL1, pdata->vpll1,
@@ -1167,21 +1165,18 @@ int twl6030_exit_irq(void);
 
 static int twl_remove(struct i2c_client *client)
 {
-	unsigned i, num_slaves;
+	unsigned i;
 	int status;
 
-	if (twl_class_is_4030()) {
+	if (twl_class_is_4030())
 		status = twl4030_exit_irq();
-		num_slaves = TWL_NUM_SLAVES;
-	} else {
+	else
 		status = twl6030_exit_irq();
-		num_slaves = TWL_NUM_SLAVES - 1;
-	}
 
 	if (status < 0)
 		return status;
 
-	for (i = 0; i < num_slaves; i++) {
+	for (i = 0; i < TWL_NUM_SLAVES; i++) {
 		struct twl_client	*twl = &twl_modules[i];
 
 		if (twl->client && twl->client != client)
@@ -1197,7 +1192,7 @@ static int __devinit
 twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 {
 	int				status;
-	unsigned			i, num_slaves;
+	unsigned			i;
 	struct twl4030_platform_data	*pdata = client->dev.platform_data;
 	struct device_node		*node = client->dev.of_node;
 	u8 temp;
@@ -1251,17 +1246,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		return -EBUSY;
 	}
 
-	if ((id->driver_data) & TWL6030_CLASS) {
-		twl_id = TWL6030_CLASS_ID;
-		twl_map = &twl6030_map[0];
-		num_slaves = TWL_NUM_SLAVES - 1;
-	} else {
-		twl_id = TWL4030_CLASS_ID;
-		twl_map = &twl4030_map[0];
-		num_slaves = TWL_NUM_SLAVES;
-	}
-
-	for (i = 0; i < num_slaves; i++) {
+	for (i = 0; i < TWL_NUM_SLAVES; i++) {
 		struct twl_client	*twl = &twl_modules[i];
 
 		twl->address = client->addr + i;
@@ -1280,6 +1265,13 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
 		mutex_init(&twl->xfer_lock);
 	}
 	inuse = true;
+	if ((id->driver_data) & TWL6030_CLASS) {
+		twl_id = TWL6030_CLASS_ID;
+		twl_map = &twl6030_map[0];
+	} else {
+		twl_id = TWL4030_CLASS_ID;
+		twl_map = &twl4030_map[0];
+	}
 
 	/* setup clock framework */
 	clocks_init(&client->dev, pdata->clock);
-- 
1.7.8.5



From broonie at opensource.wolfsonmicro.com  Tue Mar  6 07:49:25 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 12:49:25 +0000
Subject: [PATCH v2 16/17] ASoC: fsl: add dt support for imx-audmux
In-Reply-To: <1330957865-19085-17-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-17-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120306124925.GR19635@opensource.wolfsonmicro.com>

On Mon, Mar 05, 2012 at 10:31:04PM +0800, Shawn Guo wrote:
> From: Richard Zhao <richard.zhao at linaro.org>
> 
> It adds device tree probe support for imx-audmux driver.

Applied this one as well, thanks.  This really should've been in with
all the other audmux motion stuff, there's no dependency on it having
been moved into the fsl directory so it just makes it harder to apply
(but as it was a straight move git am figured it out).

As a general rule put bugfixes first, then minor cleanups, then things
that are internal to existing files (like this) and finally anything
invasive.  Basically, do the urgent stuff first and then work up in
terms of how big/tricky the changes are.  This makes it easier to get
things applied which is especially important with a large series like
this as it makes review easier and means you have fewer out of tree
patches to keep track of.
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From linus.walleij at stericsson.com  Tue Mar  6 07:55:57 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 6 Mar 2012 13:55:57 +0100
Subject: [PATCH] pinctrl: include machine header to core.h
Message-ID: <1331038557-1398-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

struct pinctrl_setting contains an enum pinctrl_map_type
field, so we need to include machine.h. Also fix kerneldoc
to indicate that the pinctrl_setting is about both muxing
and other config.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/core.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 5b3ff13..42fb0ea 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -12,6 +12,7 @@
 #include <linux/mutex.h>
 #include <linux/radix-tree.h>
 #include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/machine.h>
 
 struct pinctrl_gpio_range;
 
-- 
1.7.8



From B04825 at freescale.com  Tue Mar  6 08:02:35 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Tue, 6 Mar 2012 13:02:35 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <20120306123322.GP19635@opensource.wolfsonmicro.com>
References: <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
 <20120306104015.GF17370@n2100.arm.linux.org.uk>
 <20120306120646.GH19635@opensource.wolfsonmicro.com>
 <20120306122516.GH17370@n2100.arm.linux.org.uk>
 <20120306123322.GP19635@opensource.wolfsonmicro.com>
Message-ID: <4F560AE9.90502@freescale.com>

Mark Brown wrote:
> Well, who reads the documentation to get this stuff anyway?  As you
> observe it's far from complete about what's what locked when and how so
> you need to go to the code to see what's actually going on, especially
> whenever you need to call back into the ALSA APIs.  Though of course I'm
> pretty sure there's a bunch of uniprocessor assumptions through the body
> of driver code anyway...

So are you saying that it's possible for one CPU to call my trigger 
callback to start playback on one substream, while another CPU calls it to 
start capture on another substream?

If so, then I need to add locking in my trigger function.

-- 
Timur Tabi
Linux kernel developer at Freescale


From broonie at opensource.wolfsonmicro.com  Tue Mar  6 08:03:58 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 13:03:58 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <4F560AE9.90502@freescale.com>
References: <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
 <20120306104015.GF17370@n2100.arm.linux.org.uk>
 <20120306120646.GH19635@opensource.wolfsonmicro.com>
 <20120306122516.GH17370@n2100.arm.linux.org.uk>
 <20120306123322.GP19635@opensource.wolfsonmicro.com>
 <4F560AE9.90502@freescale.com>
Message-ID: <20120306130358.GT19635@opensource.wolfsonmicro.com>

On Tue, Mar 06, 2012 at 01:02:35PM +0000, Tabi Timur-B04825 wrote:

> So are you saying that it's possible for one CPU to call my trigger 
> callback to start playback on one substream, while another CPU calls it to 
> start capture on another substream?

Yes, Russell is right here.

> If so, then I need to add locking in my trigger function.

Yes.
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From prakash.pm at ti.com  Tue Mar  6 08:12:25 2012
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 6 Mar 2012 13:12:25 +0000
Subject: [PATCH v5 2/3] arm:davinci: move emif driver to mfd framework
In-Reply-To: <20120301112329.GI9008@sortiz-mobl>
References: <y> <1330005504-25321-3-git-send-email-prakash.pm@ti.com>
 <20120227142638.GN27687@sortiz-mobl>
 <A73F36158E33644199EB82C5EC81C7BC3176D103@DBDE01.ent.ti.com>
 <20120301112329.GI9008@sortiz-mobl>
Message-ID: <A73F36158E33644199EB82C5EC81C7BC317702E9@DBDE01.ent.ti.com>

Hi Samuel,

May be I did not do a good job giving complete information on this earlier.
So I have replied on top of my mail with below information (seems you missed it)

More information on AEMIF:
DaVinci AEMIF is an async memory interface, driver for which was implemented
in arch/arm/mach-davinci/aemif.c. It can be interfaced to NAND, NOR and other
asynchronous memories. Currently it just provides an API for timing value configuration.
The API is invoked by the MTD NAND driver. 

Specification here: http://www.ti.com/lit/ug/sprue20c/sprue20c.pdf

Reason for moving it to MFD frame work:
1) AEMIF is also present on devices belonging to arch-c6x and arch-omap2 architectures.
   So having the driver in architecture neutral place seems to be the way to go.
2) Other than NAND/NOR there are use cases where people are interfacing other devices,
   for eg: FPGAs through UIO framework. So MTD is not the place for AEMIF driver.

Taking above points into consideration Arnd Bergmann suggested to move AEMIF driver to
MFD framework [1], relevant portion of his mail as follows,

" If you want it to provide endpoint devices that are handled by
distinct subsystems in Linux, I would make it an mfd multifunction
device and make the common... "

[1] http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-December/010295.html

Thanks,
Prakash

On Thu, Mar 01, 2012 at 16:53:29, Samuel Ortiz wrote:
> Hi Prakash,
> 
> On Tue, Feb 28, 2012 at 05:44:39AM +0000, Manjunathappa, Prakash wrote:
> > Hi Samuel,
> > 
> > On Mon, Feb 27, 2012 at 19:56:38, Samuel Ortiz wrote:
> > [snip]
> > > So it seems you're passing a platform devices array through your mfd aemif
> > > platform data pointer. And from what I can see, it's mostly a 1 entry array
> > > (for the NAND case) or a 2 entries array (for the NAND and NOR case).
> > > In that case, adding an MFD driver in the middle brings basically nothing but
> > > confusion and overhead (and 200+ lines of code).
> > > So unless someone explains to me how this is doing any good to the kernel in
> > > general, I'm not going to take this patchset.
> > > 
> > > Cheers,
> > > Samuel.
> > >
> > 
> > In this way we trying to isolate future modification of aemif driver not to depict
> > as platform code change, the need for this is based on discussion in below thread
> > http://davinci-linux-open-source.1494791.n2.nabble.com/PATCH-arm-davinci-configure-davinci-aemif-chipselects-through-OF-tt7059739.html#none
> > 
> I fail to see how you're going to achieve that with adding an MFD platform
> device registration in the middle.
> 
> 
> > Earlier also concern was expressed to move aemif driver out of arch/arm to drivers folder.
> > Here is the link for the same: http://lists.infradead.org/pipermail/linux-mtd/2011-August/037308.html
> > Since aemif driver supports NAND/NOR devices, we feel MFD is the place holder.
> I would disagree with that. And it certainly makes sense to move many drivers
> out of arch/arm into a more appropriate place but I'd like to keep mfd as
> something else than yet another misc.
> 
> Cheers,
> Samuel.
> 
> -- 
> Intel Open Source Technology Centre
> http://oss.intel.com/
> 



From kmpark at infradead.org  Tue Mar  6 08:13:01 2012
From: kmpark at infradead.org (Kyungmin Park)
Date: Tue, 6 Mar 2012 22:13:01 +0900
Subject: [PATCH v10 3/3] iommu/exynos: Add iommu driver for Exynos
 Platforms
In-Reply-To: <002201ccfb73$93311520$b9933f60$%cho@samsung.com>
References: <002201ccfb73$93311520$b9933f60$%cho@samsung.com>
Message-ID: <CAH9JG2W=E7xmEO3o+up5a5Vm1PrPp60w0cfzN7=bYQO2BX1teA@mail.gmail.com>

Hi,

some not critical comments.

Thank you,
Kyungmin Park

On Tue, Mar 6, 2012 at 5:31 PM, KyongHo Cho <pullip.cho at samsung.com> wrote:
> HAALgBjAGgAbwBAAHMAYQBtAHMAdQBuAGcALgBjAG8AbQA=;Tue,
> ?06 Mar 2012 08:31:29 GMT;WwBQAEEAVABDAEgAIAB2ADEAMAAgADMALwAzAF0AIABpAG8AbQBtAHUALwBlAHgAeQBuAG8AcwA6ACAAQQBkAGQAIABpAG8AbQBtAHUAIABkAHIAaQB2AGUAcgAgAGYAbwByACAARQB4AHkAbgBvAHMAIABQAGwAYQB0AGYAbwByAG0AcwA=
> x-cr-puzzleid: {CF0AAF04-8639-4D69-B4E1-BF71EA1B0A70}
What's this?
>
> This is the System MMU driver and IOMMU API implementation for
> Exynos SOC platforms. Exynos platforms has more than 10 System
> MMUs dedicated for each multimedia accellerators.
>
> The System MMU driver is already in arc/arm/plat-s5p but it is
> moved to drivers/iommu due to Ohad Ben-Cohen gathered IOMMU drivers
> there
>
> Any device driver in Exynos platforms that needs to control its
> System MMU must call platform_set_sysmmu() to inform System MMU
> driver who will control it.
> platform_set_sysmmu() is defined in <mach/sysmmu.h>
Does it really required? if we can remove it. it can be compiled
without arch dependency.
>
> Cc: Joerg Roedel <joerg.roedel at amd.com>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
> ---
> ?drivers/iommu/Kconfig ? ? ? ?| ? 21 +
> ?drivers/iommu/Makefile ? ? ? | ? ?1 +
> ?drivers/iommu/exynos-iommu.c | 1088 ++++++++++++++++++++++++++++++++++++++++++
> ?3 files changed, 1110 insertions(+), 0 deletions(-)
> ?create mode 100644 drivers/iommu/exynos-iommu.c
>
> diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
> index 6bea696..25d3eed 100644
> --- a/drivers/iommu/Kconfig
> +++ b/drivers/iommu/Kconfig
> @@ -142,4 +142,25 @@ config OMAP_IOMMU_DEBUG
>
> ? ? ? ? ?Say N unless you know you need this.
>
> +config EXYNOS_IOMMU
> + ? ? ? bool "Exynos IOMMU Support"
> + ? ? ? depends on EXYNOS_DEV_SYSMMU
> + ? ? ? select IOMMU_API
> + ? ? ? help
> + ? ? ? ? Support for the IOMMU(System MMU) of Samsung Exynos application
> + ? ? ? ? processor family. This enables H/W multimedia accellerators to see
> + ? ? ? ? non-linear physical memory chunks as a linear memory in their
> + ? ? ? ? address spaces
> +
> + ? ? ? ? If unsure, say N here.
> +
> +config EXYNOS_IOMMU_DEBUG
> + ? ? ? bool "Debugging log for Exynos IOMMU"
> + ? ? ? depends on EXYNOS_IOMMU
> + ? ? ? help
> + ? ? ? ? Select this to see the detailed log message that shows what
> + ? ? ? ? happens in the IOMMU driver
> +
> + ? ? ? ? Say N unless you need kernel log message for IOMMU debugging
> +
> ?endif # IOMMU_SUPPORT
> diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
> index 0e36b49..5a8fd97 100644
> --- a/drivers/iommu/Makefile
> +++ b/drivers/iommu/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_IRQ_REMAP) += intr_remapping.o
> ?obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
> ?obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o
> ?obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
> +obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
> diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
> new file mode 100644
> index 0000000..4c1c48a
> --- /dev/null
> +++ b/drivers/iommu/exynos-iommu.c
> @@ -0,0 +1,1088 @@
> +/* linux/drivers/iommu/exynos_iommu.c
> + *
> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
> + * ? ? ? ? ? ? http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifdef CONFIG_EXYNOS_IOMMU_DEBUG
> +#define DEBUG
> +#endif
If it's used only at here. you can add it at Makefile.

ifeq ($(CONFIG_EXYNOS_IOMMU_DEBUG),y)
         CFLAGS-exynos-iommu        += -DDEBUG
endif

Of course you can select as your preference.
> +
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/mm.h>
> +#include <linux/iommu.h>
> +#include <linux/errno.h>
> +#include <linux/list.h>
> +#include <linux/memblock.h>
> +#include <linux/export.h>
> +
> +#include <asm/cacheflush.h>
> +#include <asm/pgtable.h>
> +
> +#include <mach/sysmmu.h>
> +
> +#define S5P_MMU_CTRL ? ? ? ? ? ? ? ? ? 0x000
> +#define S5P_MMU_CFG ? ? ? ? ? ? ? ? ? ?0x004
> +#define S5P_MMU_STATUS ? ? ? ? ? ? ? ? 0x008
> +#define S5P_MMU_FLUSH ? ? ? ? ? ? ? ? ?0x00C
> +#define S5P_PT_BASE_ADDR ? ? ? ? ? ? ? 0x014
> +#define S5P_INT_STATUS ? ? ? ? ? ? ? ? 0x018
> +#define S5P_INT_CLEAR ? ? ? ? ? ? ? ? ?0x01C
> +#define S5P_PAGE_FAULT_ADDR ? ? ? ? ? ?0x024
> +#define S5P_AW_FAULT_ADDR ? ? ? ? ? ? ?0x028
> +#define S5P_AR_FAULT_ADDR ? ? ? ? ? ? ?0x02C
> +#define S5P_DEFAULT_SLAVE_ADDR ? ? ? ? 0x030
> +#define S5P_MMU_VERSION ? ? ? ? ? ? ? ? ? ? ? ?0x034
> +#define S5P_PB0_SADDR ? ? ? ? ? ? ? ? ?0x04C
> +#define S5P_PB0_EADDR ? ? ? ? ? ? ? ? ?0x050
> +#define S5P_PB1_SADDR ? ? ? ? ? ? ? ? ?0x054
> +#define S5P_PB1_EADDR ? ? ? ? ? ? ? ? ?0x058
> +
> +#define SECT_ORDER 20
> +#define LPAGE_ORDER 16
> +#define SPAGE_ORDER 12
> +
> +#define SECT_SIZE (1 << SECT_ORDER)
> +#define LPAGE_SIZE (1 << LPAGE_ORDER)
> +#define SPAGE_SIZE (1 << SPAGE_ORDER)
> +
> +#define SECT_MASK (~(SECT_SIZE - 1))
> +#define LPAGE_MASK (~(LPAGE_SIZE - 1))
> +#define SPAGE_MASK (~(SPAGE_SIZE - 1))
> +
> +#define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
> +#define lv1ent_page(sent) ((*(sent) & 3) == 1)
> +#define lv1ent_section(sent) ((*(sent) & 3) == 2)
> +
> +#define lv2ent_fault(pent) ((*(pent) & 3) == 0)
> +#define lv2ent_small(pent) ((*(pent) & 2) == 2)
#define lv2ent_small(pent) ((*(pent) & 3) == 2)?
> +#define lv2ent_large(pent) ((*(pent) & 3) == 1)
> +
> +#define section_phys(sent) (*(sent) & SECT_MASK)
> +#define section_offs(iova) ((iova) & 0xFFFFF)
> +#define lpage_phys(pent) (*(pent) & LPAGE_MASK)
> +#define lpage_offs(iova) ((iova) & 0xFFFF)
> +#define spage_phys(pent) (*(pent) & SPAGE_MASK)
> +#define spage_offs(iova) ((iova) & 0xFFF)
> +
> +#define lv1ent_offset(iova) ((iova) >> SECT_ORDER)
> +#define lv2ent_offset(iova) (((iova) & 0xFF000) >> SPAGE_ORDER)
> +
> +#define NUM_LV1ENTRIES 4096
> +#define NUM_LV2ENTRIES 256
> +
> +#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
> +
> +#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
> +
> +#define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
> +
> +#define mk_lv1ent_sect(pa) ((pa) | 2)
> +#define mk_lv1ent_page(pa) ((pa) | 1)
> +#define mk_lv2ent_lpage(pa) ((pa) | 1)
> +#define mk_lv2ent_spage(pa) ((pa) | 2)
> +
> +#define CTRL_ENABLE ? ?0x5
> +#define CTRL_BLOCK ? ? 0x7
> +#define CTRL_DISABLE ? 0x0
> +
> +#define REG_MMU_CTRL ? ? ? ? ? 0x000
> +#define REG_MMU_CFG ? ? ? ? ? ?0x004
> +#define REG_MMU_STATUS ? ? ? ? 0x008
> +#define REG_MMU_FLUSH ? ? ? ? ?0x00C
> +#define REG_MMU_FLUSH_ENTRY ? ?0x010
> +#define REG_PT_BASE_ADDR ? ? ? 0x014
> +#define REG_INT_STATUS ? ? ? ? 0x018
> +#define REG_INT_CLEAR ? ? ? ? ?0x01C
> +#define REG_MMU_VERSION ? ? ? ? ? ? ? ?0x034
Please place it in order.
> +
> +#define REG_PAGE_FAULT_ADDR ? ?0x024
> +#define REG_AW_FAULT_ADDR ? ? ?0x028
> +#define REG_AR_FAULT_ADDR ? ? ?0x02C
> +#define REG_DEFAULT_SLAVE_ADDR 0x030
> +
> +static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
> +{
> + ? ? ? return pgtable + lv1ent_offset(iova);
> +}
> +
> +static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
> +{
> + ? ? ? return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
> +}
> +
> +enum EXYNOS_SYSMMU_INTERRUPT_TYPE {
> + ? ? ? SYSMMU_PAGEFAULT,
> + ? ? ? SYSMMU_AR_MULTIHIT,
> + ? ? ? SYSMMU_AW_MULTIHIT,
> + ? ? ? SYSMMU_BUSERROR,
> + ? ? ? SYSMMU_AR_SECURITY,
> + ? ? ? SYSMMU_AR_ACCESS,
> + ? ? ? SYSMMU_AW_SECURITY,
> + ? ? ? SYSMMU_AW_PROTECTION, /* 7 */
> + ? ? ? SYSMMU_FAULT_UNKNOWN,
> + ? ? ? SYSMMU_FAULTS_NUM
missing comma, "SYSMMU_FAULTS_NUM,"
> +};
> +
> +typedef int (*sysmmu_fault_handler_t)(enum EXYNOS_SYSMMU_INTERRUPT_TYPE itype,
> + ? ? ? ? ? ? ? ? ? ? ? unsigned long pgtable_base, unsigned long fault_addr);
> +
> +static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
> + ? ? ? REG_PAGE_FAULT_ADDR,
> + ? ? ? REG_AR_FAULT_ADDR,
> + ? ? ? REG_AW_FAULT_ADDR,
> + ? ? ? REG_DEFAULT_SLAVE_ADDR,
> + ? ? ? REG_AR_FAULT_ADDR,
> + ? ? ? REG_AR_FAULT_ADDR,
> + ? ? ? REG_AW_FAULT_ADDR,
> + ? ? ? REG_AW_FAULT_ADDR
ditto.
> +};
> +
> +static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
> + ? ? ? "PAGE FAULT",
> + ? ? ? "AR MULTI-HIT FAULT",
> + ? ? ? "AW MULTI-HIT FAULT",
> + ? ? ? "BUS ERROR",
> + ? ? ? "AR SECURITY PROTECTION FAULT",
> + ? ? ? "AR ACCESS PROTECTION FAULT",
> + ? ? ? "AW SECURITY PROTECTION FAULT",
> + ? ? ? "AW ACCESS PROTECTION FAULT",
> + ? ? ? "UNKNOWN FAULT"
ditto.
> +};
> +
> +/* We does not consider super section mapping (16MB) */
> +struct iommu_client {
> + ? ? ? struct list_head node;
> + ? ? ? struct device *dev;
> + ? ? ? int refcnt;
> +};
> +
> +struct exynos_iommu_domain {
> + ? ? ? struct list_head clients; /* list of iommu_client */
> + ? ? ? unsigned long *pgtable; /* lv1 page table, 16KB */
> + ? ? ? short *lv2entcnt; /* free lv2 entry counter for each section */
> + ? ? ? spinlock_t lock; /* lock for this structure and attached iommu_client */
> + ? ? ? spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
> +};
> +
> +struct sysmmu_drvdata {
> + ? ? ? struct device *sysmmu;
> + ? ? ? char *dbgname;
> + ? ? ? int nsfrs;
> + ? ? ? void __iomem **sfrbases;
> + ? ? ? struct clk *clk[2];
> + ? ? ? bool active;
> + ? ? ? rwlock_t lock;
> + ? ? ? struct iommu_domain *domain;
> + ? ? ? sysmmu_fault_handler_t fault_handler;
> + ? ? ? unsigned long pgtable;
> + ? ? ? struct iommu_client client;
> +};
> +
> +static bool set_sysmmu_active(struct sysmmu_drvdata *data)
> +{
> + ? ? ? /* return true if the System MMU was not active previously
> + ? ? ? ? ?and it needs to be initialized */
> + ? ? ? if (WARN_ON_ONCE(data->active))
> + ? ? ? ? ? ? ? return false;
> + ? ? ? data->active = true;
> + ? ? ? return true;
> +}
> +
> +static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
> +{
> + ? ? ? /* return true if the System MMU is needed to be disabled */
> + ? ? ? if (WARN_ON_ONCE(!data->active))
> + ? ? ? ? ? ? ? return false;
> + ? ? ? data->active = false;
> + ? ? ? return true;
> +}
> +
> +static bool is_sysmmu_active(struct sysmmu_drvdata *data)
> +{
> + ? ? ? return data->active;
> +}
> +
> +static void sysmmu_block(void __iomem *sfrbase)
> +{
> + ? ? ? __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
> +}
> +
> +static void sysmmu_unblock(void __iomem *sfrbase)
> +{
> + ? ? ? __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
> +}
> +
> +static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
> +{
> + ? ? ? __raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
> +}
> +
> +static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long iova)
> +{
> + ? ? ? __raw_writel((iova & SPAGE_MASK) | 1, sfrbase + REG_MMU_FLUSH_ENTRY);
> +}
> +
> +static void __sysmmu_set_ptbase(void __iomem *sfrbase,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long pgd)
> +{
> + ? ? ? __raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */
> + ? ? ? __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
> +
> + ? ? ? __sysmmu_tlb_invalidate(sfrbase);
> +}
> +
> +static void __sysmmu_set_prefbuf(void __iomem *sfrbase, unsigned long base,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long size, int idx)
> +{
> + ? ? ? __raw_writel(base, sfrbase + S5P_PB0_SADDR + idx * 8);
> + ? ? ? __raw_writel(size - 1 + base, ?sfrbase + S5P_PB0_EADDR + idx * 8);
> +}
> +
> +void exynos_sysmmu_set_prefbuf(struct device *dev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long base0, unsigned long size0,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long base1, unsigned long size1)
> +{
> + ? ? ? struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> + ? ? ? unsigned long flags;
> + ? ? ? int i;
> +
> + ? ? ? BUG_ON((base0 + size0) <= base0);
> + ? ? ? BUG_ON((size1 > 0) && ((base1 + size1) <= base1));
It's bogus check. it's impossible. Do you think overflow case?
> +
> + ? ? ? read_lock_irqsave(&data->lock, flags);
> + ? ? ? if (!is_sysmmu_active(data))
> + ? ? ? ? ? ? ? goto finish;
> +
> + ? ? ? for (i = 0; i < data->nsfrs; i++) {
> + ? ? ? ? ? ? ? if ((readl(data->sfrbases[i] + S5P_MMU_VERSION) >> 28) == 3) {
> + ? ? ? ? ? ? ? ? ? ? ? sysmmu_block(data->sfrbases[i]);
> +
> + ? ? ? ? ? ? ? ? ? ? ? if (size1 == 0) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? if (size0 <= SZ_128K) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? base1 = base0;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size1 = size0;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size1 = size0 -
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ALIGN(size0 / 2, SZ_64K);
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size0 = size0 - size1;
Umm I mis-understand this codes at first. it think size1 has 0
already. so it's meaning-less but now it re-use the size1 above.
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? base1 = base0 + size0;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? ? ? ? ? __sysmmu_set_prefbuf(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->sfrbases[i], base0, size0, 0);
> + ? ? ? ? ? ? ? ? ? ? ? __sysmmu_set_prefbuf(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->sfrbases[i], base1, size1, 1);
> +
> + ? ? ? ? ? ? ? ? ? ? ? sysmmu_unblock(data->sfrbases[i]);
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +finish:
> + ? ? ? read_unlock_irqrestore(&data->lock, flags);
> +}
> +
> +static void __set_fault_handler(struct sysmmu_drvdata *data,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sysmmu_fault_handler_t handler)
> +{
> + ? ? ? unsigned long flags;
> +
> + ? ? ? write_lock_irqsave(&data->lock, flags);
> + ? ? ? data->fault_handler = handler;
> + ? ? ? write_unlock_irqrestore(&data->lock, flags);
> +}
> +
> +void exynos_sysmmu_set_fault_handler(struct device *dev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sysmmu_fault_handler_t handler)
> +{
> + ? ? ? struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> +
> + ? ? ? __set_fault_handler(data, handler);
> +}
> +
> +static int default_fault_handler(enum EXYNOS_SYSMMU_INTERRUPT_TYPE itype,
Can you use the small letter instead of large one? do you see codes like this?
> + ? ? ? ? ? ? ? ? ? ?unsigned long pgtable_base, unsigned long fault_addr)
> +{
> + ? ? ? unsigned long *ent;
> +
> + ? ? ? if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
> + ? ? ? ? ? ? ? itype = SYSMMU_FAULT_UNKNOWN;
> +
> + ? ? ? pr_err("%s occured at 0x%lx(Page table base: 0x%lx)\n",
> + ? ? ? ? ? ? ? ? ? ? ? sysmmu_fault_name[itype], fault_addr, pgtable_base);
> +
> + ? ? ? ent = section_entry(__va(pgtable_base), fault_addr);
> + ? ? ? pr_err("\tLv1 entry: 0x%lx\n", *ent);
> +
> + ? ? ? if (lv1ent_page(ent)) {
> + ? ? ? ? ? ? ? ent = page_entry(ent, fault_addr);
> + ? ? ? ? ? ? ? pr_err("\t Lv2 entry: 0x%lx\n", *ent);
> + ? ? ? }
> +
> + ? ? ? pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
> +
> + ? ? ? BUG();
> +
> + ? ? ? return 0;
> +}
> +
> +static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
> +{
> + ? ? ? /* SYSMMU is in blocked when interrupt occurred. */
> + ? ? ? struct sysmmu_drvdata *data = dev_id;
> + ? ? ? struct resource *irqres;
> + ? ? ? struct platform_device *pdev;
> + ? ? ? enum EXYNOS_SYSMMU_INTERRUPT_TYPE itype;
> + ? ? ? unsigned long addr = -1;
> +
> + ? ? ? int i, ret = -ENOSYS;
> +
> + ? ? ? read_lock(&data->lock);
> +
> + ? ? ? WARN_ON(!is_sysmmu_active(data));
> +
> + ? ? ? pdev = to_platform_device(data->sysmmu);
> + ? ? ? for (i = 0; i < pdev->num_resources; i++) {
> + ? ? ? ? ? ? ? irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
> + ? ? ? ? ? ? ? if (irqres && ((int)irqres->start == irq))
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? }
> +
> + ? ? ? if (i == pdev->num_resources) {
> + ? ? ? ? ? ? ? itype = SYSMMU_FAULT_UNKNOWN;
> + ? ? ? } else {
> + ? ? ? ? ? ? ? i /= 2;
> +
> + ? ? ? ? ? ? ? itype = (enum EXYNOS_SYSMMU_INTERRUPT_TYPE)
> + ? ? ? ? ? ? ? ? ? ? ? __ffs(__raw_readl(data->sfrbases[i] + REG_INT_STATUS));
> + ? ? ? ? ? ? ? if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
> + ? ? ? ? ? ? ? ? ? ? ? itype = SYSMMU_FAULT_UNKNOWN;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? addr = __raw_readl(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->sfrbases[i] + fault_reg_offset[itype]);
> + ? ? ? }
> +
> + ? ? ? if (data->domain)
> + ? ? ? ? ? ? ? ret = report_iommu_fault(data->domain, data->client.dev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? addr, itype);
> +
> + ? ? ? if ((ret == -ENOSYS) && data->fault_handler) {
> + ? ? ? ? ? ? ? unsigned long base = data->pgtable;
> + ? ? ? ? ? ? ? if (itype != SYSMMU_FAULT_UNKNOWN)
> + ? ? ? ? ? ? ? ? ? ? ? base = __raw_readl(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->sfrbases[i] + REG_PT_BASE_ADDR);
> + ? ? ? ? ? ? ? ret = data->fault_handler(itype, base, addr);
> + ? ? ? }
> +
> + ? ? ? if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
> + ? ? ? ? ? ? ? __raw_writel(1 << itype, data->sfrbases[i] + REG_INT_CLEAR);
> + ? ? ? else
> + ? ? ? ? ? ? ? dev_dbg(data->sysmmu, "(%s) %s is not handled.\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->dbgname, sysmmu_fault_name[itype]);
> +
> + ? ? ? if (itype != SYSMMU_FAULT_UNKNOWN)
> + ? ? ? ? ? ? ? sysmmu_unblock(data->sfrbases[i]);
> +
> + ? ? ? read_unlock(&data->lock);
> +
> + ? ? ? return IRQ_HANDLED;
> +}
> +
> +static bool __sysmmu_disable(struct sysmmu_drvdata *data)
> +{
> + ? ? ? unsigned long flags;
> + ? ? ? bool disabled = false;
> + ? ? ? int i;
> +
> + ? ? ? write_lock_irqsave(&data->lock, flags);
> +
> + ? ? ? if (!set_sysmmu_inactive(data))
> + ? ? ? ? ? ? ? goto finish;
> +
> + ? ? ? for (i = 0; i < data->nsfrs; i++) {
> + ? ? ? ? ? ? ? __raw_writel(CTRL_DISABLE, data->sfrbases[i] + REG_MMU_CTRL);
> + ? ? ? ? ? ? ? if (data->clk[1])
> + ? ? ? ? ? ? ? ? ? ? ? clk_disable(data->clk[1]);
> + ? ? ? ? ? ? ? if (data->clk[0])
> + ? ? ? ? ? ? ? ? ? ? ? clk_disable(data->clk[0]);
> + ? ? ? ? ? ? ? disabled = true;
> + ? ? ? ? ? ? ? data->pgtable = 0;
> + ? ? ? ? ? ? ? data->domain = NULL;
> + ? ? ? ? ? ? ? pm_runtime_put(data->sysmmu);
> + ? ? ? }
> +
> +finish:
> + ? ? ? write_unlock_irqrestore(&data->lock, flags);
> +
> + ? ? ? return disabled;
> +}
> +
> +/* __exynos_sysmmu_enable: Enables System MMU
> + *
> + * returns -error if an error occurred and System MMU is not enabled,
> + * 0 if the System MMU has been just enabled and 1 if System MMU was already
> + * enabled before.
> + */
> +static int __exynos_sysmmu_enable(struct device *dev, unsigned long pgtable,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct iommu_domain *domain)
> +{
> + ? ? ? int i, ret = 0;
> + ? ? ? unsigned long flags;
> + ? ? ? struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> +
> + ? ? ? BUG_ON(!memblock_is_memory(pgtable));
> +
> + ? ? ? ret = pm_runtime_get_sync(data->sysmmu);
> + ? ? ? if (ret < 0)
> + ? ? ? ? ? ? ? return ret;
> +
> + ? ? ? write_lock_irqsave(&data->lock, flags);
> +
> + ? ? ? if (!set_sysmmu_active(data)) {
> + ? ? ? ? ? ? ? /* RPM of sysmmu won't be refcounted */
> + ? ? ? ? ? ? ? if (ret > 0)
> + ? ? ? ? ? ? ? ? ? ? ? pm_runtime_put(data->sysmmu);
> +
> + ? ? ? ? ? ? ? if (WARN_ON(pgtable != data->pgtable)) {
> + ? ? ? ? ? ? ? ? ? ? ? set_sysmmu_inactive(data);
> + ? ? ? ? ? ? ? ? ? ? ? ret = -EBUSY;
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? ret = 1;
> + ? ? ? ? ? ? ? dev_dbg(data->sysmmu, "(%s) Already enabled\n", data->dbgname);
> + ? ? ? ? ? ? ? goto finish;
> + ? ? ? }
> +
> + ? ? ? if (data->clk[0])
> + ? ? ? ? ? ? ? clk_enable(data->clk[0]);
> + ? ? ? if (data->clk[1])
> + ? ? ? ? ? ? ? clk_enable(data->clk[1]);
> +
> + ? ? ? data->pgtable = pgtable;
> +
> + ? ? ? for (i = 0; i < data->nsfrs; i++) {
> + ? ? ? ? ? ? ? __sysmmu_set_ptbase(data->sfrbases[i], pgtable);
> +
> + ? ? ? ? ? ? ? if ((readl(data->sfrbases[i] + S5P_MMU_VERSION) >> 28) == 3) {
> + ? ? ? ? ? ? ? ? ? ? ? /* System MMU version is 3.x */
> + ? ? ? ? ? ? ? ? ? ? ? __raw_writel((1 << 12) | (2 << 28),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->sfrbases[i] + S5P_MMU_CFG);
> + ? ? ? ? ? ? ? ? ? ? ? __sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 0);
> + ? ? ? ? ? ? ? ? ? ? ? __sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 1);
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? __raw_writel(CTRL_ENABLE, data->sfrbases[i] + REG_MMU_CTRL);
> + ? ? ? }
> +
> + ? ? ? data->domain = domain;
> +
> + ? ? ? dev_dbg(data->sysmmu, "(%s) Enabled\n", data->dbgname);
> +finish:
> + ? ? ? write_unlock_irqrestore(&data->lock, flags);
> +
> + ? ? ? if (ret < 0) {
> + ? ? ? ? ? ? ? __sysmmu_disable(data);
> + ? ? ? ? ? ? ? dev_dbg(data->sysmmu, "(%s) Failed to enable\n", data->dbgname);
> + ? ? ? }
> +
> + ? ? ? return ret;
> +}
> +
> +static struct iommu_client *__get_enabled_iommu_client(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct iommu_domain *domain, struct device *dev)
> +{
> + ? ? ? struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> + ? ? ? struct exynos_iommu_domain *priv = domain->priv;
> + ? ? ? int ret;
> +
> + ? ? ? ret = __exynos_sysmmu_enable(dev, __pa(priv->pgtable), domain);
> + ? ? ? if (ret < 0)
> + ? ? ? ? ? ? ? return ERR_PTR(ret);
> + ? ? ? else if (ret == 1)
> + ? ? ? ? ? ? ? return ERR_PTR(-EBUSY);
> +
> + ? ? ? INIT_LIST_HEAD(&data->client.node);
> + ? ? ? data->client.dev = dev;
> + ? ? ? data->client.refcnt = 1;
> +
> + ? ? ? return &data->client;
> +}
> +
> +int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable)
> +{
> + ? ? ? return __exynos_sysmmu_enable(dev, pgtable, NULL);
> +}
> +
> +void exynos_sysmmu_disable(struct device *dev)
> +{
> + ? ? ? struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> + ? ? ? bool disabled;
> +
> + ? ? ? disabled = __sysmmu_disable(data);
> + ? ? ? dev_dbg(data->sysmmu,
> + ? ? ? ? ? ? ? ? ? ? ? disabled ? "(%s) Disabled.\n" :
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "(%s) Deactivation request ignorred.\n",
> + ? ? ? ? ? ? ? ? ? ? ? data->dbgname);
> +}
> +
> +static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova)
> +{
> + ? ? ? unsigned long flags;
> + ? ? ? struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> +
> + ? ? ? read_lock_irqsave(&data->lock, flags);
> +
> + ? ? ? if (is_sysmmu_active(data)) {
> + ? ? ? ? ? ? ? int i;
> + ? ? ? ? ? ? ? for (i = 0; i < data->nsfrs; i++) {
> + ? ? ? ? ? ? ? ? ? ? ? sysmmu_block(data->sfrbases[i]);
> + ? ? ? ? ? ? ? ? ? ? ? __sysmmu_tlb_invalidate_entry(data->sfrbases[i], iova);
> + ? ? ? ? ? ? ? ? ? ? ? sysmmu_unblock(data->sfrbases[i]);
> + ? ? ? ? ? ? ? }
> + ? ? ? } else {
> + ? ? ? ? ? ? ? dev_dbg(data->sysmmu,
> + ? ? ? ? ? ? ? ? ? ? ? "(%s) Disabled. Skipping invalidating TLB.\n",
> + ? ? ? ? ? ? ? ? ? ? ? data->dbgname);
> + ? ? ? }
> +
> + ? ? ? read_unlock_irqrestore(&data->lock, flags);
> +}
> +
> +void exynos_sysmmu_tlb_invalidate(struct device *dev)
> +{
> + ? ? ? unsigned long flags;
> + ? ? ? struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
> +
> + ? ? ? read_lock_irqsave(&data->lock, flags);
> +
> + ? ? ? if (is_sysmmu_active(data)) {
> + ? ? ? ? ? ? ? int i;
> + ? ? ? ? ? ? ? for (i = 0; i < data->nsfrs; i++) {
> + ? ? ? ? ? ? ? ? ? ? ? sysmmu_block(data->sfrbases[i]);
> + ? ? ? ? ? ? ? ? ? ? ? __sysmmu_tlb_invalidate(data->sfrbases[i]);
> + ? ? ? ? ? ? ? ? ? ? ? sysmmu_unblock(data->sfrbases[i]);
> + ? ? ? ? ? ? ? }
> + ? ? ? } else {
> + ? ? ? ? ? ? ? dev_dbg(data->sysmmu,
> + ? ? ? ? ? ? ? ? ? ? ? "(%s) Disabled. Skipping invalidating TLB.\n",
> + ? ? ? ? ? ? ? ? ? ? ? data->dbgname);
> + ? ? ? }
> +
> + ? ? ? read_unlock_irqrestore(&data->lock, flags);
> +}
> +
> +static int exynos_sysmmu_probe(struct platform_device *pdev)
> +{
> + ? ? ? int i, ret;
> + ? ? ? struct device *dev;
> + ? ? ? struct sysmmu_drvdata *data;
> +
> + ? ? ? dev = &pdev->dev;
> +
> + ? ? ? data = kzalloc(sizeof(*data), GFP_KERNEL);
> + ? ? ? if (!data) {
> + ? ? ? ? ? ? ? dev_dbg(dev, "Not enough memory\n");
> + ? ? ? ? ? ? ? ret = -ENOMEM;
> + ? ? ? ? ? ? ? goto err_alloc;
> + ? ? ? }
> +
> + ? ? ? ret = dev_set_drvdata(dev, data);
> + ? ? ? if (ret) {
> + ? ? ? ? ? ? ? dev_dbg(dev, "Unabled to initialize driver data\n");
> + ? ? ? ? ? ? ? goto err_init;
> + ? ? ? }
> +
> + ? ? ? data->nsfrs = pdev->num_resources / 2;
> + ? ? ? data->sfrbases = kmalloc(sizeof(*data->sfrbases) * data->nsfrs,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? GFP_KERNEL);
> + ? ? ? if (data->sfrbases == NULL) {
> + ? ? ? ? ? ? ? dev_dbg(dev, "Not enough memory\n");
> + ? ? ? ? ? ? ? ret = -ENOMEM;
> + ? ? ? ? ? ? ? goto err_init;
> + ? ? ? }
> +
> + ? ? ? for (i = 0; i < data->nsfrs; i++) {
> + ? ? ? ? ? ? ? struct resource *res;
> + ? ? ? ? ? ? ? res = platform_get_resource(pdev, IORESOURCE_MEM, i);
> + ? ? ? ? ? ? ? if (!res) {
> + ? ? ? ? ? ? ? ? ? ? ? dev_dbg(dev, "Unable to find IOMEM region\n");
> + ? ? ? ? ? ? ? ? ? ? ? ret = -ENOENT;
> + ? ? ? ? ? ? ? ? ? ? ? goto err_res;
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? data->sfrbases[i] = ioremap(res->start, resource_size(res));
> + ? ? ? ? ? ? ? if (!data->sfrbases[i]) {
> + ? ? ? ? ? ? ? ? ? ? ? dev_dbg(dev, "Unable to map IOMEM @ PA:%#x\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? res->start);
> + ? ? ? ? ? ? ? ? ? ? ? ret = -ENOENT;
> + ? ? ? ? ? ? ? ? ? ? ? goto err_res;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? for (i = 0; i < data->nsfrs; i++) {
> + ? ? ? ? ? ? ? ret = platform_get_irq(pdev, i);
> + ? ? ? ? ? ? ? if (ret <= 0) {
> + ? ? ? ? ? ? ? ? ? ? ? dev_dbg(dev, "Unable to find IRQ resource\n");
> + ? ? ? ? ? ? ? ? ? ? ? goto err_irq;
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? ret = request_irq(ret, exynos_sysmmu_irq, 0,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dev_name(dev), data);
> + ? ? ? ? ? ? ? if (ret) {
> + ? ? ? ? ? ? ? ? ? ? ? dev_dbg(dev, "Unabled to register interrupt handler\n");
> + ? ? ? ? ? ? ? ? ? ? ? goto err_irq;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (dev_get_platdata(dev)) {
> + ? ? ? ? ? ? ? char *deli, *beg;
> + ? ? ? ? ? ? ? struct sysmmu_platform_data *platdata = dev_get_platdata(dev);
> +
> + ? ? ? ? ? ? ? beg = platdata->clockname;
> +
> + ? ? ? ? ? ? ? for (deli = beg; (*deli != '\0') && (*deli != ','); deli++)
> + ? ? ? ? ? ? ? ? ? ? ? /* NOTHING */;
> +
> + ? ? ? ? ? ? ? if (*deli == '\0')
> + ? ? ? ? ? ? ? ? ? ? ? deli = NULL;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? *deli = '\0';
> +
> + ? ? ? ? ? ? ? data->clk[0] = clk_get(dev, beg);
> + ? ? ? ? ? ? ? if (IS_ERR(data->clk[0])) {
> + ? ? ? ? ? ? ? ? ? ? ? data->clk[0] = NULL;
> + ? ? ? ? ? ? ? ? ? ? ? dev_dbg(dev, "No clock descriptor registered\n");
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? if (data->clk[0] && deli) {
> + ? ? ? ? ? ? ? ? ? ? ? *deli = ',';
> + ? ? ? ? ? ? ? ? ? ? ? data->clk[1] = clk_get(dev, deli + 1);
> + ? ? ? ? ? ? ? ? ? ? ? if (IS_ERR(data->clk[1]))
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->clk[1] = NULL;
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? data->dbgname = platdata->dbgname;
> + ? ? ? }
> +
> + ? ? ? data->sysmmu = dev;
> + ? ? ? rwlock_init(&data->lock);
> +
> + ? ? ? __set_fault_handler(data, &default_fault_handler);
> +
> + ? ? ? if (dev->parent)
> + ? ? ? ? ? ? ? pm_runtime_enable(dev);
> +
> + ? ? ? dev_dbg(dev, "(%s) Initialized\n", data->dbgname);
> + ? ? ? return 0;
> +err_irq:
> + ? ? ? while (i-- > 0) {
> + ? ? ? ? ? ? ? int irq;
> +
> + ? ? ? ? ? ? ? irq = platform_get_irq(pdev, i);
> + ? ? ? ? ? ? ? free_irq(irq, data);
> + ? ? ? }
> +err_res:
> + ? ? ? while (data->nsfrs-- > 0)
> + ? ? ? ? ? ? ? iounmap(data->sfrbases[data->nsfrs]);
> + ? ? ? kfree(data->sfrbases);
> +err_init:
> + ? ? ? kfree(data);
> +err_alloc:
> + ? ? ? dev_err(dev, "Failed to initialize\n");
> + ? ? ? return ret;
> +}
> +
> +static struct platform_driver exynos_sysmmu_driver = {
> + ? ? ? .probe ? ? ? ? ?= exynos_sysmmu_probe,
> + ? ? ? .driver ? ? ? ? = {
> + ? ? ? ? ? ? ? .owner ? ? ? ? ?= THIS_MODULE,
> + ? ? ? ? ? ? ? .name ? ? ? ? ? = "exynos-sysmmu",
> + ? ? ? }
> +};
> +
> +static inline void pgtable_flush(void *vastart, void *vaend)
> +{
> + ? ? ? dmac_flush_range(vastart, vaend);
> + ? ? ? outer_flush_range(virt_to_phys(vastart),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? virt_to_phys(vaend));
> +}
> +
> +static int exynos_iommu_domain_init(struct iommu_domain *domain)
> +{
> + ? ? ? struct exynos_iommu_domain *priv;
> +
> + ? ? ? priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + ? ? ? if (!priv)
> + ? ? ? ? ? ? ? return -ENOMEM;
> +
> + ? ? ? priv->pgtable = (unsigned long *)__get_free_pages(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? GFP_KERNEL | __GFP_ZERO, 2);
> + ? ? ? if (!priv->pgtable)
> + ? ? ? ? ? ? ? goto err_pgtable;
> +
> + ? ? ? priv->lv2entcnt = (short *)__get_free_pages(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? GFP_KERNEL | __GFP_ZERO, 1);
> + ? ? ? if (!priv->lv2entcnt)
> + ? ? ? ? ? ? ? goto err_counter;
> +
> + ? ? ? pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
> +
> + ? ? ? spin_lock_init(&priv->lock);
> + ? ? ? spin_lock_init(&priv->pgtablelock);
> + ? ? ? INIT_LIST_HEAD(&priv->clients);
> +
> + ? ? ? domain->priv = priv;
> + ? ? ? return 0;
> +
> +err_counter:
> + ? ? ? free_pages((unsigned long)priv->pgtable, 2);
> +err_pgtable:
> + ? ? ? kfree(priv);
> + ? ? ? return -ENOMEM;
> +}
> +
> +static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
> +{
> + ? ? ? struct exynos_iommu_domain *priv = domain->priv;
> + ? ? ? struct list_head *pos, *n;
> + ? ? ? unsigned long flags;
> + ? ? ? int i;
> +
> + ? ? ? WARN_ON(!list_empty(&priv->clients));
> +
> + ? ? ? spin_lock_irqsave(&priv->lock, flags);
> +
> + ? ? ? list_for_each_safe(pos, n, &priv->clients) {
> + ? ? ? ? ? ? ? struct iommu_client *client;
> +
> + ? ? ? ? ? ? ? client = list_entry(pos, struct iommu_client, node);
> + ? ? ? ? ? ? ? exynos_sysmmu_disable(client->dev);
> + ? ? ? ? ? ? ? kfree(client);
> + ? ? ? }
> +
> + ? ? ? spin_unlock_irqrestore(&priv->lock, flags);
> +
> + ? ? ? for (i = 0; i < NUM_LV1ENTRIES; i++)
> + ? ? ? ? ? ? ? if (lv1ent_page(priv->pgtable + i))
> + ? ? ? ? ? ? ? ? ? ? ? kfree(__va(lv2table_base(priv->pgtable + i)));
> +
> + ? ? ? free_pages((unsigned long)priv->pgtable, 2);
> + ? ? ? free_pages((unsigned long)priv->lv2entcnt, 1);
> + ? ? ? kfree(domain->priv);
> + ? ? ? domain->priv = NULL;
> +}
> +
> +static int exynos_iommu_attach_device(struct iommu_domain *domain,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct device *dev)
> +{
> + ? ? ? struct exynos_iommu_domain *priv = domain->priv;
> + ? ? ? struct iommu_client *client = NULL;
> + ? ? ? struct list_head *pos;
> + ? ? ? unsigned long flags;
> +
> + ? ? ? spin_lock_irqsave(&priv->lock, flags);
> +
> + ? ? ? list_for_each(pos, &priv->clients) {
> + ? ? ? ? ? ? ? struct iommu_client *cur;
> +
> + ? ? ? ? ? ? ? cur = list_entry(pos, struct iommu_client, node);
> + ? ? ? ? ? ? ? if (cur->dev == dev) {
> + ? ? ? ? ? ? ? ? ? ? ? client = cur;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (client != NULL)
> + ? ? ? ? ? ? ? client->refcnt++;
> +
> + ? ? ? spin_unlock_irqrestore(&priv->lock, flags);
> +
> + ? ? ? if (client != NULL) {
> + ? ? ? ? ? ? ? dev_dbg(dev, "%s: IOMMU with pgtable 0x%lx already attached\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __func__, __pa(priv->pgtable));
> + ? ? ? ? ? ? ? return 0;
> + ? ? ? }
> +
> + ? ? ? client = __get_enabled_iommu_client(domain, dev);
> + ? ? ? if (IS_ERR(client))
> + ? ? ? ? ? ? ? return PTR_ERR(client);
> +
> + ? ? ? spin_lock_irqsave(&priv->lock, flags);
> + ? ? ? list_add_tail(&client->node, &priv->clients);
> + ? ? ? spin_unlock_irqrestore(&priv->lock, flags);
> +
> + ? ? ? dev_dbg(dev, "%s: Attached new IOMMU with pgtable 0x%lx\n", __func__,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __pa(priv->pgtable));
> + ? ? ? return 0;
> +}
> +
> +static void exynos_iommu_detach_device(struct iommu_domain *domain,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct device *dev)
> +{
> + ? ? ? struct exynos_iommu_domain *priv = domain->priv;
> + ? ? ? struct iommu_client *client = NULL;
> + ? ? ? struct list_head *pos;
> + ? ? ? unsigned long flags;
> +
> + ? ? ? spin_lock_irqsave(&priv->lock, flags);
> +
> + ? ? ? list_for_each(pos, &priv->clients) {
> + ? ? ? ? ? ? ? struct iommu_client *cur;
> +
> + ? ? ? ? ? ? ? cur = list_entry(pos, struct iommu_client, node);
> + ? ? ? ? ? ? ? if (cur->dev == dev) {
> + ? ? ? ? ? ? ? ? ? ? ? cur->refcnt--;
> + ? ? ? ? ? ? ? ? ? ? ? client = cur;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? spin_unlock_irqrestore(&priv->lock, flags);
> +
> + ? ? ? if (WARN_ON(client == NULL))
> + ? ? ? ? ? ? ? return;
> +
> + ? ? ? if (client->refcnt > 0) {
> + ? ? ? ? ? ? ? dev_dbg(dev,
> + ? ? ? ? ? ? ? ? ? ? ? "IOMMU is still attached %d times with pgtable %#lx\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? client->refcnt, __pa(priv->pgtable));
> + ? ? ? ? ? ? ? return;
> + ? ? ? }
> +
> + ? ? ? list_del(&client->node);
> + ? ? ? exynos_sysmmu_disable(client->dev);
> + ? ? ? dev_dbg(dev, "%s: Detached IOMMU with pgtable 0x%lx\n", __func__,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __pa(priv->pgtable));
> +}
> +
> +static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? short *pgcounter)
> +{
> + ? ? ? if (lv1ent_fault(sent)) {
> + ? ? ? ? ? ? ? unsigned long *pent;
> +
> + ? ? ? ? ? ? ? pent = kzalloc(LV2TABLE_SIZE, GFP_ATOMIC);
> + ? ? ? ? ? ? ? BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
> + ? ? ? ? ? ? ? if (!pent)
> + ? ? ? ? ? ? ? ? ? ? ? return NULL;
> +
> + ? ? ? ? ? ? ? *sent = mk_lv1ent_page(__pa(pent));
> + ? ? ? ? ? ? ? *pgcounter = NUM_LV2ENTRIES;
> + ? ? ? ? ? ? ? pgtable_flush(pent, pent + NUM_LV2ENTRIES);
> + ? ? ? ? ? ? ? pgtable_flush(sent, sent + 1);
> + ? ? ? }
> +
> + ? ? ? return page_entry(sent, iova);
> +}
> +
> +static int lv1set_section(unsigned long *sent, phys_addr_t paddr, short *pgcnt)
> +{
> + ? ? ? if (lv1ent_section(sent))
> + ? ? ? ? ? ? ? return -EADDRINUSE;
> +
> + ? ? ? if (lv1ent_page(sent)) {
> + ? ? ? ? ? ? ? if (*pgcnt != NUM_LV2ENTRIES)
> + ? ? ? ? ? ? ? ? ? ? ? return -EADDRINUSE;
> +
> + ? ? ? ? ? ? ? kfree(page_entry(sent, 0));
> +
> + ? ? ? ? ? ? ? *pgcnt = 0;
> + ? ? ? }
> +
> + ? ? ? *sent = mk_lv1ent_sect(paddr);
> +
> + ? ? ? pgtable_flush(sent, sent + 1);
> +
> + ? ? ? return 0;
> +}
> +
> +static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? short *pgcnt)
> +{
> + ? ? ? if (size == SPAGE_SIZE) {
> + ? ? ? ? ? ? ? if (!lv2ent_fault(pent))
> + ? ? ? ? ? ? ? ? ? ? ? return -EADDRINUSE;
> +
> + ? ? ? ? ? ? ? *pent = mk_lv2ent_spage(paddr);
> + ? ? ? ? ? ? ? pgtable_flush(pent, pent + 1);
> + ? ? ? ? ? ? ? *pgcnt -= 1;
> + ? ? ? } else { /* size == LPAGE_SIZE */
> + ? ? ? ? ? ? ? int i;
> + ? ? ? ? ? ? ? for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
> + ? ? ? ? ? ? ? ? ? ? ? if (!lv2ent_fault(pent)) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memset(pent, 0, sizeof(*pent) * i);
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? return -EADDRINUSE;
> + ? ? ? ? ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? ? ? ? ? *pent = mk_lv2ent_lpage(paddr);
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? pgtable_flush(pent - SPAGES_PER_LPAGE, pent);
> + ? ? ? ? ? ? ? *pgcnt -= SPAGES_PER_LPAGE;
> + ? ? ? }
> +
> + ? ? ? return 0;
> +}
> +
> +static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova,
> + ? ? ? ? ? ? ? ? ? ? ? ?phys_addr_t paddr, size_t size, int prot)
> +{
> + ? ? ? struct exynos_iommu_domain *priv = domain->priv;
> + ? ? ? unsigned long *entry;
> + ? ? ? unsigned long flags;
> + ? ? ? int ret = -ENOMEM;
> +
> + ? ? ? BUG_ON(priv->pgtable == NULL);
> +
> + ? ? ? spin_lock_irqsave(&priv->pgtablelock, flags);
> +
> + ? ? ? entry = section_entry(priv->pgtable, iova);
> +
> + ? ? ? if (size == SECT_SIZE) {
> + ? ? ? ? ? ? ? ret = lv1set_section(entry, paddr,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &priv->lv2entcnt[lv1ent_offset(iova)]);
> + ? ? ? } else {
> + ? ? ? ? ? ? ? unsigned long *pent;
> +
> + ? ? ? ? ? ? ? pent = alloc_lv2entry(entry, iova,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &priv->lv2entcnt[lv1ent_offset(iova)]);
> +
> + ? ? ? ? ? ? ? if (!pent)
> + ? ? ? ? ? ? ? ? ? ? ? ret = -ENOMEM;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? ret = lv2set_page(pent, paddr, size,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &priv->lv2entcnt[lv1ent_offset(iova)]);
> + ? ? ? }
> +
> + ? ? ? if (ret) {
> + ? ? ? ? ? ? ? pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __func__, iova, size);
> + ? ? ? }
> +
> + ? ? ? spin_unlock_irqrestore(&priv->pgtablelock, flags);
> +
> + ? ? ? return ret;
> +}
> +
> +static size_t exynos_iommu_unmap(struct iommu_domain *domain,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long iova, size_t size)
> +{
> + ? ? ? struct exynos_iommu_domain *priv = domain->priv;
> + ? ? ? struct iommu_client *client;
> + ? ? ? unsigned long flags;
> + ? ? ? unsigned long *ent;
> +
> + ? ? ? BUG_ON(priv->pgtable == NULL);
> +
> + ? ? ? spin_lock_irqsave(&priv->pgtablelock, flags);
> +
> + ? ? ? ent = section_entry(priv->pgtable, iova);
> +
> + ? ? ? if (lv1ent_section(ent)) {
> + ? ? ? ? ? ? ? BUG_ON(size < SECT_SIZE);
> +
> + ? ? ? ? ? ? ? *ent = 0;
> + ? ? ? ? ? ? ? pgtable_flush(ent, ent + 1);
> + ? ? ? ? ? ? ? size = SECT_SIZE;
> + ? ? ? ? ? ? ? goto done;
> + ? ? ? }
> +
> + ? ? ? if (unlikely(lv1ent_fault(ent))) {
> + ? ? ? ? ? ? ? if (size > SECT_SIZE)
> + ? ? ? ? ? ? ? ? ? ? ? size = SECT_SIZE;
> + ? ? ? ? ? ? ? goto done;
> + ? ? ? }
> +
> + ? ? ? /* lv1ent_page(sent) == true here */
> +
> + ? ? ? ent = page_entry(ent, iova);
> +
> + ? ? ? if (unlikely(lv2ent_fault(ent))) {
> + ? ? ? ? ? ? ? size = SPAGE_SIZE;
> + ? ? ? ? ? ? ? goto done;
> + ? ? ? }
> +
> + ? ? ? if (lv2ent_small(ent)) {
> + ? ? ? ? ? ? ? *ent = 0;
> + ? ? ? ? ? ? ? size = SPAGE_SIZE;
> + ? ? ? ? ? ? ? priv->lv2entcnt[lv1ent_offset(iova)] -= 1;
> + ? ? ? ? ? ? ? goto done;
> + ? ? ? }
> +
> + ? ? ? /* lv1ent_large(ent) == true here */
> + ? ? ? BUG_ON(size < LPAGE_SIZE);
> +
> + ? ? ? memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
> +
> + ? ? ? size = LPAGE_SIZE;
> + ? ? ? priv->lv2entcnt[lv1ent_offset(iova)] -= SPAGES_PER_LPAGE;
> +done:
> + ? ? ? list_for_each_entry(client, &priv->clients, node)
> + ? ? ? ? ? ? ? sysmmu_tlb_invalidate_entry(client->dev, iova);
> +
> + ? ? ? spin_unlock_irqrestore(&priv->pgtablelock, flags);
> +
> + ? ? ? return size;
> +}
> +
> +static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long iova)
> +{
> + ? ? ? struct exynos_iommu_domain *priv = domain->priv;
> + ? ? ? unsigned long *entry;
> + ? ? ? unsigned long flags;
> + ? ? ? phys_addr_t phys = -1;
> +
> + ? ? ? spin_lock_irqsave(&priv->pgtablelock, flags);
> +
> + ? ? ? entry = section_entry(priv->pgtable, iova);
> +
> + ? ? ? if (lv1ent_section(entry)) {
> + ? ? ? ? ? ? ? phys = section_phys(entry) + section_offs(iova);
> + ? ? ? } else if (lv1ent_page(entry)) {
> + ? ? ? ? ? ? ? entry = page_entry(entry, iova);
> +
> + ? ? ? ? ? ? ? if (lv2ent_large(entry))
> + ? ? ? ? ? ? ? ? ? ? ? phys = lpage_phys(entry) + lpage_offs(iova);
> + ? ? ? ? ? ? ? else if (lv2ent_small(entry))
> + ? ? ? ? ? ? ? ? ? ? ? phys = spage_phys(entry) + spage_offs(iova);
> + ? ? ? }
> +
> + ? ? ? spin_unlock_irqrestore(&priv->pgtablelock, flags);
> +
> + ? ? ? return phys;
What's happened if phys has -1? I mean it can't trigger any condition at above.
> +}
> +
> +static struct iommu_ops exynos_iommu_ops = {
> + ? ? ? .domain_init = &exynos_iommu_domain_init,
> + ? ? ? .domain_destroy = &exynos_iommu_domain_destroy,
> + ? ? ? .attach_dev = &exynos_iommu_attach_device,
> + ? ? ? .detach_dev = &exynos_iommu_detach_device,
> + ? ? ? .map = &exynos_iommu_map,
> + ? ? ? .unmap = &exynos_iommu_unmap,
> + ? ? ? .iova_to_phys = &exynos_iommu_iova_to_phys,
> + ? ? ? .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
> +};
> +
> +static int __init exynos_iommu_init(void)
> +{
> + ? ? ? int ret;
> +
> + ? ? ? ret = platform_driver_register(&exynos_sysmmu_driver);
> +
> + ? ? ? if (ret == 0)
> + ? ? ? ? ? ? ? bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
> +
> + ? ? ? return ret;
> +}
> +arch_initcall(exynos_iommu_init);
> --
> 1.7.1
>
>
> --
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From shawn.guo at linaro.org  Tue Mar  6 08:13:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 6 Mar 2012 21:13:11 +0800
Subject: [PATCH v2 16/17] ASoC: fsl: add dt support for imx-audmux
In-Reply-To: <20120306124925.GR19635@opensource.wolfsonmicro.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-17-git-send-email-shawn.guo@linaro.org>
 <20120306124925.GR19635@opensource.wolfsonmicro.com>
Message-ID: <CAAQ0ZWRTrb2Epa+14i+ry0XdvFrOzaV-BYfV0ra7x5E63hzFnw@mail.gmail.com>

On 6 March 2012 20:49, Mark Brown <broonie at opensource.wolfsonmicro.com> wrote:
> On Mon, Mar 05, 2012 at 10:31:04PM +0800, Shawn Guo wrote:
>> From: Richard Zhao <richard.zhao at linaro.org>
>>
>> It adds device tree probe support for imx-audmux driver.
>
> Applied this one as well, thanks. ?This really should've been in with
> all the other audmux motion stuff, there's no dependency on it having
> been moved into the fsl directory so it just makes it harder to apply
> (but as it was a straight move git am figured it out).
>
> As a general rule put bugfixes first, then minor cleanups, then things
> that are internal to existing files (like this) and finally anything
> invasive. ?Basically, do the urgent stuff first and then work up in
> terms of how big/tricky the changes are. ?This makes it easier to get
> things applied which is especially important with a large series like
> this as it makes review easier and means you have fewer out of tree
> patches to keep track of.

Thanks for the suggestion, Mark.

Regards,
Shawn


From shawn.guo at linaro.org  Tue Mar  6 08:34:18 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 6 Mar 2012 21:34:18 +0800
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120306120247.GF19635@opensource.wolfsonmicro.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
 <20120305144601.GQ3224@opensource.wolfsonmicro.com>
 <20120306073900.GP16232@S2101-09.ap.freescale.net>
 <20120306120247.GF19635@opensource.wolfsonmicro.com>
Message-ID: <20120306133416.GQ16232@S2101-09.ap.freescale.net>

On Tue, Mar 06, 2012 at 12:02:47PM +0000, Mark Brown wrote:
> On Tue, Mar 06, 2012 at 03:39:02PM +0800, Shawn Guo wrote:
> > On Mon, Mar 05, 2012 at 02:46:01PM +0000, Mark Brown wrote:
> 
> > > This you can just set in the card struct, no need for explicit code at
> > > all.
> 
> > Yes, I just tried.  It also works but a little bit differently.  We
> > only set_fmt for codec_dai here, while ASoC core will set_fmt for both
> > codec_dai and cpu_dai if dai_link->dai_fmt is set.  However, the
> > fsl_ssi does not provide .set_fmt implementation, and consequently we
> > will see error message below, which does not impact functionality
> > though.
> 
> >   fsl-ssi-dai 83fcc000.ssi: Failed to set DAI format: -22
> 
> > I hope we keep the code as it is now and improve later when fsl_ssi
> > gets improved.
> 
> No, we should fix the core to work better in this case - not having a
> DAI operation is perfectly normal and should be supported.
> 
So something like this?

@@ -1536,12 +1536,8 @@ static void snd_soc_instantiate_card(struct snd_soc_card *card)
                                         "Failed to set DAI format: %d\n",
                                         ret);

-                       ret = snd_soc_dai_set_fmt(card->rtd[i].cpu_dai,
-                                                 dai_link->dai_fmt);
-                       if (ret != 0)
-                               dev_warn(card->rtd[i].cpu_dai->dev,
-                                        "Failed to set DAI format: %d\n",
-                                        ret);
+                       snd_soc_dai_set_fmt(card->rtd[i].cpu_dai,
+                                           dai_link->dai_fmt);
                }
        }

> > > > +	ret = of_property_read_u32(np, "fsl,mux-int-port", &int_port);
> > > > +	ret = of_property_read_u32(np, "fsl,mux-ext-port", &ext_port);
> 
> > > It seems very odd to have namespacing on the individual property names.
> > > Why are you doing that?  The properties are already defined in terms of
> > > the device binding.  Though everyone else is doing it so not really a
> > > problem.
> 
> > The general device tree binding practice is we'd better have a vendor
> > prefix on the property name, if the property applies on specific vendor
> > drivers instead of common ones across different vendors.
> 
> There's nothing generic about this device, it only applies to a specific
> combination of things and in so far as it applies to those the
> properties are generic - any board combining i.MX and this CODEC is
> going to have an audmux.
> 
Since you agreed it's not really a problem, I would like to do what
everyone else is doing.

> > > > +	/*
> > > > +	 * The port numbering in the hardware manual starts at 1, while
> > > > +	 * the audmux API expects it starts at 0.
> > > > +	 */
> > > > +	int_port--;
> > > > +	ext_port--;
> 
> > > Should have error checking somewhere to make sure that the user
> > > remembered this.
> 
> > Because different i.MX SoC may have different internal and external
> > port number, I do not think of a way to check that.  And I would not
> 
> In that case the audmux code should be validating the arguments.
> 
What we can check is only where the number starts and probably where
it ends.  That requires audmux driver have the ranges of internal port
and external port for each i.MX SoC encoded.  For DT case, we may have
the ranges defined in device tree, while for non-DT case, we then need
to introduce platform_data to pass that piece of data.  In the end,
this check does not guarantee the correctness, and developers have to
give the correct port number.  So is it really worth it?

> > worry about it that much, since all the hardware documents number the
> > port from 1, while device tree user/author will have to look at those
> > documents for the data.
> 
> OTOH the in kernel API uses a different numbering and if the user is
> porting their existing code over to device tree...
> 
Whoever is porting the code will need to look at the audmux binding
document, where we have a big note regarding this.

> > > > +	imx_audmux_v2_configure_port(int_port,
> > > > +			IMX_AUDMUX_V2_PTCR_SYN |
> > > > +			IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
> > > > +			IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
> > > > +			IMX_AUDMUX_V2_PTCR_TFSDIR |
> > > > +			IMX_AUDMUX_V2_PTCR_TCLKDIR,
> > > > +			IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
> 
> > > I'm not sure we've really gained much from converting to a platform
> > > driver given that the device just registers something globally...
> 
> > Converting audmux to a platform driver does not change anything about
> > that.  It makes device tree support easier, and gets the audmux users
> > (imx machine drivers) stay away from including <mach/audmux.h>.
> 
> It's not actually fixed anything in the APIs though

I'm not fixing the APIs.  Instead, I'm adding device tree support for
audmux driver, while converting it to platform driver make that easy.

> and we've now also got a race in the driver probes 
> since the audmux now need to come up via
> the device model instead of just being there

The race is solved by having audmux device registered in a
subsys_initcall.

> - we could try to configure
> the audmux with no platform driver bound.

Before this series, the audmux is configured with no platform driver
bound.  I'm confused here.  Are you saying we are moving to a wrong
direction?

> We should really have the
> audmux as at least an aux_dev in the card to make sure it's there.

I do not understand how aux_dev can help here.  Being a device encoded
in device tree, audmux device should have been created by DT core, and
all we need to do is registering the audmux driver to get it bound to
audmux device.

-- 
Regards,
Shawn


From tiwai at suse.de  Tue Mar  6 08:26:28 2012
From: tiwai at suse.de (Takashi Iwai)
Date: Tue, 06 Mar 2012 14:26:28 +0100
Subject: [alsa-devel] [PATCH 15/20] ASoC: fsl: make fsl_ssi driver
 compilable on ARM/IMX
In-Reply-To: <20120306123322.GP19635@opensource.wolfsonmicro.com>
References: <1330788001-10158-16-git-send-email-shawn.guo@linaro.org>
 <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
 <20120306104015.GF17370@n2100.arm.linux.org.uk>
 <20120306120646.GH19635@opensource.wolfsonmicro.com>
 <20120306122516.GH17370@n2100.arm.linux.org.uk>
 <20120306123322.GP19635@opensource.wolfsonmicro.com>
Message-ID: <s5h4nu17tdn.wl%tiwai@suse.de>

At Tue, 6 Mar 2012 12:33:22 +0000,
Mark Brown wrote:
> 
> On Tue, Mar 06, 2012 at 12:25:16PM +0000, Russell King - ARM Linux wrote:
> 
> > Please also note that in ALSA documentation, an 'atomic' callback means
> > little with respect to race conditions.  All it means is that the callback
> > is called from a context where sleeping in the callback is not permitted.
> > The documentation does not say what is protected by the ALSA spinlocks and
> > mutexes, so without reviewing the ALSA code, driver writters have little
> > idea whether they need their own locks or not.
> 
> Well, who reads the documentation to get this stuff anyway?

At least Russell has read it ;)

Indeed, the word "atomic" in that context may be misleading.
Meanwhile, it's actually protected by spinlock against the race to
change the PCM state.  But, since the PCM state is assigned to each
substream, the protection is also only for a substream.

There are other some protections, e.g. in reset and prepare callbacks,
but these are against linked streams via rw-semaphore, so that the
linked list won't be corrupted.  So, each substream instance isn't
entirely protected in these cases.

> As you
> observe it's far from complete about what's what locked when and how so
> you need to go to the code to see what's actually going on, especially
> whenever you need to call back into the ALSA APIs.  Though of course I'm
> pretty sure there's a bunch of uniprocessor assumptions through the body
> of driver code anyway...

Not that much actually.  On the contrary, because of the current
design allowing concurrent accesses, many codes have been written
rather in too complex and messy ways.  It could have been much
simplified if we didn't consider the concurrent accesses to each
substream.

In summary, it's the lowlevel driver's responsibility to protect the
concurrent hardware access.  The ALSA core protects (in some level)
the change of the PCM internal state of each substream.  But it
doesn't restrict the concurrent accesses over multiple substreams at
all.


Takashi


From broonie at opensource.wolfsonmicro.com  Tue Mar  6 08:35:07 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 13:35:07 +0000
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120306133416.GQ16232@S2101-09.ap.freescale.net>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
 <20120305144601.GQ3224@opensource.wolfsonmicro.com>
 <20120306073900.GP16232@S2101-09.ap.freescale.net>
 <20120306120247.GF19635@opensource.wolfsonmicro.com>
 <20120306133416.GQ16232@S2101-09.ap.freescale.net>
Message-ID: <20120306133506.GU19635@opensource.wolfsonmicro.com>

On Tue, Mar 06, 2012 at 09:34:18PM +0800, Shawn Guo wrote:
> On Tue, Mar 06, 2012 at 12:02:47PM +0000, Mark Brown wrote:

> > No, we should fix the core to work better in this case - not having a
> > DAI operation is perfectly normal and should be supported.

> So something like this?

> @@ -1536,12 +1536,8 @@ static void snd_soc_instantiate_card(struct snd_soc_card *card)

> -                       if (ret != 0)
> -                               dev_warn(card->rtd[i].cpu_dai->dev,
> -                                        "Failed to set DAI format: %d\n",
> -                                        ret);

It should still complain but it should check to see if there was an
actual set_fmt op and only complain then, probably we should change all
the noop error codes for the accessor functions to be -ENOTSUPP or
something and then change the check here to look for ret != 0 && ret !=
ENOTSUPP.

> > There's nothing generic about this device, it only applies to a specific
> > combination of things and in so far as it applies to those the
> > properties are generic - any board combining i.MX and this CODEC is
> > going to have an audmux.

> Since you agreed it's not really a problem, I would like to do what
> everyone else is doing.

Well, "everyone else" in this context is only Tegra right now so there's
a case for nipping this in the bud too :)

> > In that case the audmux code should be validating the arguments.

> What we can check is only where the number starts and probably where
> it ends.  That requires audmux driver have the ranges of internal port
> and external port for each i.MX SoC encoded.  For DT case, we may have
> the ranges defined in device tree, while for non-DT case, we then need
> to introduce platform_data to pass that piece of data.  In the end,
> this check does not guarantee the correctness, and developers have to
> give the correct port number.  So is it really worth it?

It does seem concerning and error prone that there's two different
numbering schemes for the audmux APIs.

> > OTOH the in kernel API uses a different numbering and if the user is
> > porting their existing code over to device tree...

> Whoever is porting the code will need to look at the audmux binding
> document, where we have a big note regarding this.

If there's one universal truth about system integrators it's that they
always read the documentation and don't ever just copy things from an
example and tweak it till it works.  :)

> > It's not actually fixed anything in the APIs though

> I'm not fixing the APIs.  Instead, I'm adding device tree support for
> audmux driver, while converting it to platform driver make that easy.

I know, that's kind of the problem.  You've moved the device
registration to the device model but not done anything on the top level
to ensure that we actually managed to do so.

> > and we've now also got a race in the driver probes 
> > since the audmux now need to come up via
> > the device model instead of just being there

> The race is solved by having audmux device registered in a
> subsys_initcall.

And hoping that it does actually get registered and successfully
loads and that it doesn't get built as a module which could get set up
in a different order, plus the edge cases where users actively unbind
the driver from the device.

> > - we could try to configure
> > the audmux with no platform driver bound.

> Before this series, the audmux is configured with no platform driver
> bound.  I'm confused here.  Are you saying we are moving to a wrong
> direction?

Previously just building the code was enough, it'd unconditionally
initialise itself in early init and we were fine.  Now there's a bunch
of different ways in which someone could break things since we're using
the device model so we need to make sure we work with those.

> > We should really have the
> > audmux as at least an aux_dev in the card to make sure it's there.

> I do not understand how aux_dev can help here.  Being a device encoded
> in device tree, audmux device should have been created by DT core, and
> all we need to do is registering the audmux driver to get it bound to
> audmux device.

None of that stuff does anything to ensure that the audmux is present
before the card comes up.
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From fabio.estevam at freescale.com  Tue Mar  6 08:35:53 2012
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Tue, 6 Mar 2012 10:35:53 -0300
Subject: [PATCH] ARM: mx35: Fix registration of camera clock
Message-ID: <1331040953-15494-1-git-send-email-fabio.estevam@freescale.com>

Fix registration of camera clock so that mx3-camera driver can get its clock
correctly.

Reported-by: Alex Gershgorin <alexg at meprolight.com>
Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-imx/clock-imx35.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
index 1e279af..e56c1a8 100644
--- a/arch/arm/mach-imx/clock-imx35.c
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -483,7 +483,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
 	_REGISTER_CLOCK(NULL, "max", max_clk)
 	_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
-	_REGISTER_CLOCK(NULL, "csi", csi_clk)
+	_REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
 	_REGISTER_CLOCK(NULL, "iim", iim_clk)
 	_REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
 	_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-- 
1.7.1




From broonie at opensource.wolfsonmicro.com  Tue Mar  6 08:38:18 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 13:38:18 +0000
Subject: [alsa-devel] [PATCH 15/20] ASoC: fsl: make fsl_ssi driver
 compilable on ARM/IMX
In-Reply-To: <s5h4nu17tdn.wl%tiwai@suse.de>
References: <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
 <20120306104015.GF17370@n2100.arm.linux.org.uk>
 <20120306120646.GH19635@opensource.wolfsonmicro.com>
 <20120306122516.GH17370@n2100.arm.linux.org.uk>
 <20120306123322.GP19635@opensource.wolfsonmicro.com>
 <s5h4nu17tdn.wl%tiwai@suse.de>
Message-ID: <20120306133818.GV19635@opensource.wolfsonmicro.com>

On Tue, Mar 06, 2012 at 02:26:28PM +0100, Takashi Iwai wrote:
> Mark Brown wrote:
> > On Tue, Mar 06, 2012 at 12:25:16PM +0000, Russell King - ARM Linux wrote:

> > whenever you need to call back into the ALSA APIs.  Though of course I'm
> > pretty sure there's a bunch of uniprocessor assumptions through the body
> > of driver code anyway...

> Not that much actually.  On the contrary, because of the current
> design allowing concurrent accesses, many codes have been written
> rather in too complex and messy ways.  It could have been much
> simplified if we didn't consider the concurrent accesses to each
> substream.

Right, but I'm fairly sure that at least some of the driver code is
relying on uniprocessor assumptions for what it's doing - there's a
bunch of things that can't happen on unipocessor that can happen on
SMP (or preempting) systems.
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From tiwai at suse.de  Tue Mar  6 08:46:24 2012
From: tiwai at suse.de (Takashi Iwai)
Date: Tue, 06 Mar 2012 14:46:24 +0100
Subject: [alsa-devel] [PATCH 15/20] ASoC: fsl: make fsl_ssi driver
 compilable on ARM/IMX
In-Reply-To: <20120306133818.GV19635@opensource.wolfsonmicro.com>
References: <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
 <20120306104015.GF17370@n2100.arm.linux.org.uk>
 <20120306120646.GH19635@opensource.wolfsonmicro.com>
 <20120306122516.GH17370@n2100.arm.linux.org.uk>
 <20120306123322.GP19635@opensource.wolfsonmicro.com>
 <s5h4nu17tdn.wl%tiwai@suse.de>
 <20120306133818.GV19635@opensource.wolfsonmicro.com>
Message-ID: <s5h1up57sgf.wl%tiwai@suse.de>

At Tue, 6 Mar 2012 13:38:18 +0000,
Mark Brown wrote:
> 
> On Tue, Mar 06, 2012 at 02:26:28PM +0100, Takashi Iwai wrote:
> > Mark Brown wrote:
> > > On Tue, Mar 06, 2012 at 12:25:16PM +0000, Russell King - ARM Linux wrote:
> 
> > > whenever you need to call back into the ALSA APIs.  Though of course I'm
> > > pretty sure there's a bunch of uniprocessor assumptions through the body
> > > of driver code anyway...
> 
> > Not that much actually.  On the contrary, because of the current
> > design allowing concurrent accesses, many codes have been written
> > rather in too complex and messy ways.  It could have been much
> > simplified if we didn't consider the concurrent accesses to each
> > substream.
> 
> Right, but I'm fairly sure that at least some of the driver code is
> relying on uniprocessor assumptions for what it's doing - there's a
> bunch of things that can't happen on unipocessor that can happen on
> SMP (or preempting) systems.

Yeah, the driver codes.  There must be handful such ones...


Takashi


From linux at arm.linux.org.uk  Tue Mar  6 08:46:44 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 13:46:44 +0000
Subject: [PATCH 15/20] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <20120306123322.GP19635@opensource.wolfsonmicro.com>
References: <4F53F704.8080703@freescale.com>
 <20120304232817.GA13516@n2100.arm.linux.org.uk>
 <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
 <20120306104015.GF17370@n2100.arm.linux.org.uk>
 <20120306120646.GH19635@opensource.wolfsonmicro.com>
 <20120306122516.GH17370@n2100.arm.linux.org.uk>
 <20120306123322.GP19635@opensource.wolfsonmicro.com>
Message-ID: <20120306134644.GI17370@n2100.arm.linux.org.uk>

On Tue, Mar 06, 2012 at 12:33:22PM +0000, Mark Brown wrote:
> On Tue, Mar 06, 2012 at 12:25:16PM +0000, Russell King - ARM Linux wrote:
> 
> > Please also note that in ALSA documentation, an 'atomic' callback means
> > little with respect to race conditions.  All it means is that the callback
> > is called from a context where sleeping in the callback is not permitted.
> > The documentation does not say what is protected by the ALSA spinlocks and
> > mutexes, so without reviewing the ALSA code, driver writters have little
> > idea whether they need their own locks or not.
> 
> Well, who reads the documentation to get this stuff anyway?

Strangely, I do, and I'd bet most people writing an ALSA driver read
the "Writing an ALSA Driver" document, even though it's seven years old.
I also tend to read the code as well, though not everyone does.

> As you
> observe it's far from complete about what's what locked when and how so
> you need to go to the code to see what's actually going on, especially
> whenever you need to call back into the ALSA APIs.

The point is, during this thread I've had this 'atomic' business quoted
at me as the reason why read-modify-write of registers is safe.  That's
also proof that people other than me read that document - but not only
that, they then go on to misunderstand it and don't bother to read the
code.


From linux at arm.linux.org.uk  Tue Mar  6 08:52:59 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 13:52:59 +0000
Subject: [alsa-devel] [PATCH 15/20] ASoC: fsl: make fsl_ssi driver
 compilable on ARM/IMX
In-Reply-To: <20120306133818.GV19635@opensource.wolfsonmicro.com>
References: <4F53FBA1.8090200@freescale.com>
 <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
 <20120306104015.GF17370@n2100.arm.linux.org.uk>
 <20120306120646.GH19635@opensource.wolfsonmicro.com>
 <20120306122516.GH17370@n2100.arm.linux.org.uk>
 <20120306123322.GP19635@opensource.wolfsonmicro.com>
 <s5h4nu17tdn.wl%tiwai@suse.de>
 <20120306133818.GV19635@opensource.wolfsonmicro.com>
Message-ID: <20120306135259.GJ17370@n2100.arm.linux.org.uk>

On Tue, Mar 06, 2012 at 01:38:18PM +0000, Mark Brown wrote:
> On Tue, Mar 06, 2012 at 02:26:28PM +0100, Takashi Iwai wrote:
> > Mark Brown wrote:
> > > On Tue, Mar 06, 2012 at 12:25:16PM +0000, Russell King - ARM Linux wrote:
> 
> > > whenever you need to call back into the ALSA APIs.  Though of course I'm
> > > pretty sure there's a bunch of uniprocessor assumptions through the body
> > > of driver code anyway...
> 
> > Not that much actually.  On the contrary, because of the current
> > design allowing concurrent accesses, many codes have been written
> > rather in too complex and messy ways.  It could have been much
> > simplified if we didn't consider the concurrent accesses to each
> > substream.
> 
> Right, but I'm fairly sure that at least some of the driver code is
> relying on uniprocessor assumptions for what it's doing

Mark,

Stop using the term "uniprocessor assmptions".

Thinking that something is safe because you're running on a uniprocessor
system is total bollocks at every level.

You can get other threads scheduled on a uniprocessor system because you
happen to have called a function which has slept beneath you.  As you
later mention in your reply, preempt.  Preempt will effectively turn a
UP system into an effective SMP system as far as proper locking goes.

So, to talk about "uniprocessor assumptions" is at best misleading, but
is totally and utterly wrong.  Please stop mudding the issue with your
system programming misunderstandings.

What you mean is "single threaded assumptions".  Please use this term
instead - it's what you actually mean.


From bhutchings at solarflare.com  Tue Mar  6 09:03:28 2012
From: bhutchings at solarflare.com (Ben Hutchings)
Date: Tue, 6 Mar 2012 14:03:28 +0000
Subject: [PATCH v4] lpc32xx: Added ethernet driver: smp_wmb()
In-Reply-To: <4F55EA6D.3070602@antcom.de>
References: <1330983641-32622-1-git-send-email-stigge@antcom.de>
 <1330987524.2538.61.camel@bwh-desktop> <4F55EA6D.3070602@antcom.de>
Message-ID: <1331042608.2347.1.camel@bwh-desktop>

On Tue, 2012-03-06 at 11:43 +0100, Roland Stigge wrote:
> On 03/05/2012 11:45 PM, Ben Hutchings wrote:
> >> +	/* Clear and enable interrupts */
> >> +	writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
> >> +	lpc_eth_enable_int(pldat->net_base);
> >> +
> >> +	/* Get the next TX buffer output index */
> >> +	pldat->num_used_tx_buffs = 0;
> >> +	pldat->last_tx_idx =
> >> +		readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
> > 
> > Doesn't this need to be done *before* enabling interrupts?  Also, I
> > think you need an smp_wmb() so that the interrupt handler is guaranteed
> > to see all these writes.
> 
> Do you mean _one_ smp_wmb() directly after lpc_eth_enable_int() (which
> I'm moving behind the above code?

The sequence should be

	pldat->state = values...;
	smp_wmb();
	enable_interrupts();

> Note that there is no SMP in LPCs and NXP is not planning to build one
> AFAIK.

Never say never!

> However, I'm fine with including smp_wmb() anyway for completeness.

Ben.

-- 
Ben Hutchings, Staff Engineer, Solarflare
Not speaking for my employer; that's the marketing department's job.
They asked us to note that Solarflare product names are trademarked.



From t-kristo at ti.com  Tue Mar  6 09:10:58 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 16:10:58 +0200
Subject: [PATCHv4 4/6] ARM: OMAP3+: PRM: Enable IO wake up
In-Reply-To: <4F5598E3.4050506@ti.com>
References: <1330701475-22576-1-git-send-email-t-kristo@ti.com>
 <1330701475-22576-5-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203052001240.6649@utopia.booyaka.com>
 <4F55978C.7030407@ti.com>  <4F5598E3.4050506@ti.com>
Message-ID: <1331043058.2116.166.camel@sokoban>

On Tue, 2012-03-06 at 10:26 +0530, Rajendra Nayak wrote:
> On Tuesday 06 March 2012 10:20 AM, Rajendra Nayak wrote:
> > On Tuesday 06 March 2012 09:51 AM, Paul Walmsley wrote:
> >> added Rajendra, Nilesh, Vishwa, Mohan
> >>
> >> Hi
> >>
> >> On Fri, 2 Mar 2012, Tero Kristo wrote:
> >>
> >>> Enable IO Wake up for OMAP3/4 as part of PRM Init. Currently this has
> >>> been
> >>> managed in cpuidle path which is not the right place. Subsequent patch
> >>> will remove IO Daisy chain handling in cpuidle path once daisy chain is
> >>> handled as part of hwmod mux. This patch also moves the OMAP4 IO wakeup
> >>> enable code from the trigger function to init time setup.
> >>>
> >>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
> >>
> >> Should we keep the I/O wakeups enabled all the time?
> >>
> >> Seems like that could result in at least one spurious wake-up event --
> >> and
> >> thus a PRCM interrupt -- for each I/O pad that has WAKEUPENABLE set.
> >> Seems like these interrupts could recur every time the I/O chain is
> >> reset.
> >> And that the I/O chain is now reset in every hwmod idle and enable
> >> operation for an IP block that contains dynamic mux data?
> >>
> >> Thinking about the problem na?vely... maybe you all can think through
> >> this
> >> with me:
> >>
> >> Consider an IP block 'A' that has a signal (like the UART rx_irrx signal)
> >> that's mux'ed to a pad with WAKEUPENABLE set. (Some examples of 'A' might
> >> include a UART, a GPIO, or a McBSP.)
> >>
> >> Shouldn't we enable I/O wakeups (by setting EN_IO/GLOBAL_WUEN) only
> >> immediately before the powerdomain containing IP block 'A' is going to
> >> transition into RETENTION or OFF?
> >
> > Hi Paul,
> >
> > I completely agree with your observations and we knew we would have
> > additional wakeups with this design. Like I mentioned in the other
> > thread, we went ahead with this approach knowing we need to optimize
> > with some kind of powerdomain level usecounting in the future, because
> > it didn't exist back then when we did it this way.
> > But now that we already have it, maybe we can fix this and do
> > it such that we completely avoid an additional wakeup interrupt.
> >
> >>
> >> If we do that, then we can avoid needlessly resetting the I/O chain
> >> when a
> >> powerdomain is not going to go into a low-power state.
> >>
> >> I haven't measured the time it takes for the I/O chain to be reset.
> >> Maybe one of you have. But that 100 microsecond timeout that was
> >> specified in two of the other patches in this series has me a little
> >> worried.
> >
> > I haven't profiled it myself but I am guessing the delay isn't much.
> 
> Having said that, I do agree with you that, however small the delay,
> we end up doing needless IO trigger when the powerdomain isn't
> really entering a low power state.

After some measurements (used ARM performance counters for this), it
looks like omap4 takes between 2...4us for the IO chain trigger. omap3
takes 7...8us, most of which appears to be delay caused by interconnect,
the poll loops don't actually have time to do anything. Speaking of
which, the trigger function was pretty broken for omap3 on this set, I
noticed that while doing the profiling. The fixed one takes this time,
I'll post a new version of the whole set shortly.

-Tero

> 
> > The 100us comes from the fact that there is no documentation on the
> > exact delay, so went around asking whats the *real worst case* delay,
> > and we got an answer, 100us should be really big enough :)
> >
> > regards,
> > Rajendra
> >
> >>
> >>
> >> - Paul
> >
> 




From arnd at arndb.de  Tue Mar  6 09:11:59 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 14:11:59 +0000
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201202281945.39419.arnd@arndb.de>
 <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
Message-ID: <201203061412.00073.arnd@arndb.de>

On Tuesday 06 March 2012, Nicolas Pitre wrote:
> On Tue, 28 Feb 2012, Arnd Bergmann wrote:
> 
> > On Tuesday 28 February 2012, Rob Herring wrote:
> > > ixp2000 has no commits other than tree-wide changes or refactoring since
> > > 2006. No maintainer is listed for ixp2000 either.
> > 
> > I have this in my copy of the MAINTAINERS file:
> > 
> > ARM/INTEL IXP2000 ARM ARCHITECTURE
> > M:      Lennert Buytenhek <kernel at wantstofly.org>
> > L:      linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> > S:      Maintained
> > 
> > It's missing an F: line, otherwise it suggests that the platform is still
> > maintained by Lennert and it certainly builds just fine. Unfortunately he
> > seems to have fallen off the edge of the planet at the end of last year.
> 
> FYI, here's a snippet of a conversation I just had with Lennert on IRC 
> today:
> 
> 13:05 < nico> do you still care about ixp2000?
> 13:22 < lennert> not really, no
> 13:58 < nico> do you think we could remove it from the kernel tree?
> 14:01 < lennert> go for it, and remove ixp23xx too while you're at it

Ah, good to know that Lennert is actually still alive somewhere.

And removing ixp2xxx in 3.5 will certainly help us, too. 

Interestingly, that leaves ixp4xx as the only big-endian ARM platform.
I believe that ixp4xx is still being actively used quite a bit, but does
that include the big-endian ones? There is no immediate reason why we
would want to drop support for big-endian, but if it's not used at all,
that would be an interesting cleanup opportunity.

	Arnd


From festevam at gmail.com  Tue Mar  6 09:18:46 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Tue, 6 Mar 2012 11:18:46 -0300
Subject: [PATCH v3] ARM : mx35: 3ds-board: add framebuffer device
In-Reply-To: <1320401632-21444-1-git-send-email-b39297@freescale.com>
References: <1320401632-21444-1-git-send-email-b39297@freescale.com>
Message-ID: <CAOMZO5DYO2xCeHTAr=rVtO2PD8VhxQm2u5TtWUU2fBdB5K5NxA@mail.gmail.com>

Hi Sascha,

On Fri, Nov 4, 2011 at 8:13 AM, wu guoxing <b39297 at freescale.com> wrote:
> This patch adds framebuffer support for freescale mx35 3ds board
>
> Signed-off-by: Wu Guoxing <b39297 at freescale.com>
> ---
> Changes since v2:
> ? ? ? ?1. use gpio_set_value_cansleep instead of gpio_set_value
> Changes since v1:
> ? ? ? ?1. use gpio driver for mc9s08dz60

Could this one be applied now?

Regards,

Fabio Estevam


From linux at arm.linux.org.uk  Tue Mar  6 09:17:45 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 14:17:45 +0000
Subject: [PATCH v4] lpc32xx: Added ethernet driver: smp_wmb()
In-Reply-To: <1331042608.2347.1.camel@bwh-desktop>
References: <1330983641-32622-1-git-send-email-stigge@antcom.de>
 <1330987524.2538.61.camel@bwh-desktop> <4F55EA6D.3070602@antcom.de>
 <1331042608.2347.1.camel@bwh-desktop>
Message-ID: <20120306141745.GA15201@n2100.arm.linux.org.uk>

On Tue, Mar 06, 2012 at 02:03:28PM +0000, Ben Hutchings wrote:
> On Tue, 2012-03-06 at 11:43 +0100, Roland Stigge wrote:
> > On 03/05/2012 11:45 PM, Ben Hutchings wrote:
> > >> +	/* Clear and enable interrupts */
> > >> +	writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
> > >> +	lpc_eth_enable_int(pldat->net_base);
> > >> +
> > >> +	/* Get the next TX buffer output index */
> > >> +	pldat->num_used_tx_buffs = 0;
> > >> +	pldat->last_tx_idx =
> > >> +		readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
> > > 
> > > Doesn't this need to be done *before* enabling interrupts?  Also, I
> > > think you need an smp_wmb() so that the interrupt handler is guaranteed
> > > to see all these writes.
> > 
> > Do you mean _one_ smp_wmb() directly after lpc_eth_enable_int() (which
> > I'm moving behind the above code?
> 
> The sequence should be
> 
> 	pldat->state = values...;
> 	smp_wmb();
> 	enable_interrupts();

Is this correct?

"SMP BARRIER PAIRING" and "EXAMPLES OF MEMORY BARRIER SEQUENCES" in
Documentation/memory-barriers.txt suggest that there should be some kind
of pairing with smp_wmb() to ensure correctness.



From jason at lakedaemon.net  Tue Mar  6 09:29:20 2012
From: jason at lakedaemon.net (Jason)
Date: Tue, 6 Mar 2012 09:29:20 -0500
Subject: [PULL REQUEST v2] ARM: kirkwood: fdt: convert kirkwood init
 funcs to fdt
In-Reply-To: <alpine.LFD.2.02.1203051626370.31242@xanadu.home>
References: <cover.1330709314.git.jason@lakedaemon.net>
 <alpine.LFD.2.02.1203051344130.31242@xanadu.home>
 <20120305191546.GK5050@titan.lakedaemon.net>
 <201203052016.26949.arnd@arndb.de>
 <20120305202941.GN5050@titan.lakedaemon.net>
 <alpine.LFD.2.02.1203051542190.31242@xanadu.home>
 <20120305211737.GO5050@titan.lakedaemon.net>
 <alpine.LFD.2.02.1203051626370.31242@xanadu.home>
Message-ID: <20120306142920.GQ5050@titan.lakedaemon.net>

On Mon, Mar 05, 2012 at 04:27:27PM -0500, Nicolas Pitre wrote:
> On Mon, 5 Mar 2012, Jason wrote:
> 
> > On Mon, Mar 05, 2012 at 03:43:42PM -0500, Nicolas Pitre wrote:
> > > On Mon, 5 Mar 2012, Jason wrote:
> > > 
> > > > On Mon, Mar 05, 2012 at 08:16:26PM +0000, Arnd Bergmann wrote:
> > > > > On Monday 05 March 2012, Jason wrote:
> > > > > > > 
> > > > > > > The clock frequency part being hardcoded to 200000 in the common .dtsi 
> > > > > > > file looks wrong.  The clock may differ, and it used to (and should) be 
> > > > > > > probed at run time, please see kirkwood_find_tclk().
> > > > > > 
> > > > > > So, should I EXPORT_SYMBOL_GPL(kirkwood_find_tclk); and have each driver
> > > > > > call it?
> > > > > 
> > > > > If the drivers want to use it, I think it has to be orion_find_tclk for
> > > > > drivers that are shared between multiple plat-orion platforms.
> > > > 
> > > > That's pretty much all of them  :-)
> > > > 
> > > > I'll rename it and move it to plat-orion/common.c.  This'll be fun.
> > > 
> > > No no...  This is not a function which is generic at all.  The _result_ 
> > > i.e. core clock frequency value is a generic thing, not the method to 
> > > determine it.
> > 
> > How about this?  Export a global variable, orion_tclk, and a function to
> > read it.  Then, make sure each sub arch sets the global.  Does this
> > sound viable until common clk lands?
> 
> Yep, looks fine.

I just got a first look at Andrew's patches for using the generic clk
across plat/orion.  There's a lot of good stuff in there.  I'll start
building my series on top of his (and obviously Mike's clk series).

thx,

Jason.


From jason at lakedaemon.net  Tue Mar  6 09:44:15 2012
From: jason at lakedaemon.net (Jason)
Date: Tue, 6 Mar 2012 09:44:15 -0500
Subject: revert merge commit de68f28 in for-next?
Message-ID: <20120306144415.GR5050@titan.lakedaemon.net>

Arnd,

As much as I'd love to see this go in right now, I don't think it's the
correct version (from Mar 2).  This is the merge commit in question:

de68f2847fa759df54e9d8eb0013a0f8ea959c22

It's missing several fixes, #ifdef CONFIG_OF around struct of_device_id,
marvell -> mrvl in compatible properties, etc.

Would you like me to submit a new pull request, or base my fixes off of
this and submit new patches?

Thanks and sorry for the confusion,

Jason.


From arnd at arndb.de  Tue Mar  6 10:02:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 15:02:07 +0000
Subject: [PATCH v3 1/7] serial: pxa: add OF support
In-Reply-To: <1331001730-13429-1-git-send-email-haojian.zhuang@marvell.com>
References: <201203051255.37311.arnd@arndb.de>
 <1331001730-13429-1-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <201203061502.08097.arnd@arndb.de>

On Tuesday 06 March 2012, Haojian Zhuang wrote:

> @@ -51,7 +54,7 @@ struct uart_pxa_port {
>  	unsigned char           mcr;
>  	unsigned int            lsr_break_flag;
>  	struct clk		*clk;
> -	char			*name;
> +	char			name[PXA_NAME_LEN];
>  };

This looks better now

>  static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
> @@ -781,6 +784,33 @@ static const struct dev_pm_ops serial_pxa_pm_ops = {
>  };
>  #endif
>  
> +#ifdef CONFIG_OF
> +static struct of_device_id serial_pxa_dt_ids[] = {
> +	{ .compatible = "mrvl,pxa-uart", },
> +	{ .compatible = "mrvl,mmp-uart", },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids);
> +#endif

If you do this, you have to use of_match_ptr for referencing
serial_pxa_dt_ids or you will get a link error when CONFIG_OF is
disabled.

> @@ -850,6 +876,7 @@ static int serial_pxa_remove(struct platform_device *dev)
>  	platform_set_drvdata(dev, NULL);
>  
>  	uart_remove_one_port(&serial_pxa_reg, &sport->port);
> +	kfree(sport->name);
>  	clk_put(sport->clk);
>  	kfree(sport);
>  

And this must be removed now that sport->name is allocated as part of sport.

	Arnd


From haojian.zhuang at gmail.com  Tue Mar  6 10:04:40 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Tue, 6 Mar 2012 23:04:40 +0800
Subject: [PATCH v3 1/7] serial: pxa: add OF support
In-Reply-To: <201203061502.08097.arnd@arndb.de>
References: <201203051255.37311.arnd@arndb.de>
 <1331001730-13429-1-git-send-email-haojian.zhuang@marvell.com>
 <201203061502.08097.arnd@arndb.de>
Message-ID: <CAN1soZwatL=O6iTVaOn+seHPrLH1r1yhvDKM=YCjzuprcbAvOw@mail.gmail.com>

On Tue, Mar 6, 2012 at 11:02 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Tuesday 06 March 2012, Haojian Zhuang wrote:
>
>> @@ -51,7 +54,7 @@ struct uart_pxa_port {
>> ? ? ? unsigned char ? ? ? ? ? mcr;
>> ? ? ? unsigned int ? ? ? ? ? ?lsr_break_flag;
>> ? ? ? struct clk ? ? ? ? ? ? ?*clk;
>> - ? ? char ? ? ? ? ? ? ? ? ? ?*name;
>> + ? ? char ? ? ? ? ? ? ? ? ? ?name[PXA_NAME_LEN];
>> ?};
>
> This looks better now
>
>> ?static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
>> @@ -781,6 +784,33 @@ static const struct dev_pm_ops serial_pxa_pm_ops = {
>> ?};
>> ?#endif
>>
>> +#ifdef CONFIG_OF
>> +static struct of_device_id serial_pxa_dt_ids[] = {
>> + ? ? { .compatible = "mrvl,pxa-uart", },
>> + ? ? { .compatible = "mrvl,mmp-uart", },
>> + ? ? {}
>> +};
>> +MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids);
>> +#endif
>
> If you do this, you have to use of_match_ptr for referencing
> serial_pxa_dt_ids or you will get a link error when CONFIG_OF is
> disabled.
>
>> @@ -850,6 +876,7 @@ static int serial_pxa_remove(struct platform_device *dev)
>> ? ? ? platform_set_drvdata(dev, NULL);
>>
>> ? ? ? uart_remove_one_port(&serial_pxa_reg, &sport->port);
>> + ? ? kfree(sport->name);
>> ? ? ? clk_put(sport->clk);
>> ? ? ? kfree(sport);
>>
>
> And this must be removed now that sport->name is allocated as part of sport.
>
> ? ? ? ?Arnd
>
Ah. It's a bug. I'll fix it tomorrow.

Thanks
Haojian


From t-kristo at ti.com  Tue Mar  6 10:11:36 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 17:11:36 +0200
Subject: [PATCHv5 0/6] ARM: OMAP3+: IO daisy chain support fixes
Message-ID: <1331046702-2472-1-git-send-email-t-kristo@ti.com>

Hi,

Changes compared to previous version:

- patch2:
  * fixed the timeout for waiting for ST_IO_CHAIN == 1
  * added clear for ST_IO_CHAIN bit (as per spec + implementation in patch 1)
  * replaced the timeout at the end of function with a simple register
    readback (timing out on a register value that we are clearing does
    not make that much sense, the bit is cleared the very first time CPU
    manages to read it)
- patch5:
  * added spinlock for protecting io_chain_trigger operation

Tested on omap3 beagle + omap4 blaze. Also did measurements for the
cost of IO chain trigger operation with ARM performance counters:

- omap3 approx 7...8us
- omap4 approx 2...4us

-Tero




From t-kristo at ti.com  Tue Mar  6 10:11:37 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 17:11:37 +0200
Subject: [PATCHv5 1/6] ARM: OMAP3 PM: correct enable/disable of daisy io chain
In-Reply-To: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
Message-ID: <1331046702-2472-2-git-send-email-t-kristo@ti.com>

From: Mohan V <mohanv at ti.com>

Currently the enabling and disabling of IO Daisy chain is not
according to the TRM. The below steps are followed to enable/
disable the IO chain according to the "Sec 3.5.7.2.2
I/O Wake-Up Mechanism" in OMAP3630 Public TRM[1].

Steps to enable IO chain:
[a] Set PM_WKEN_WKUP.EN_IO bit
[b] Set the PM_WKEN_WKUP.EN_IO_CHAIN bit
[c] Poll for PM_WKST_WKUP.ST_IO_CHAIN.
[d] When ST_IO_CHAIN bit set to 1, clear PM_WKEN_WKUP.EN_IO_CHAIN
[e] Clear ST_IO_CHAIN bit.

Steps to disable IO chain:
[a] Clear PM_WKEN_WKUP.EN_IO_CHAIN bit
[b] Clear PM_WKEN_WKUP.EN_IO bit
[c] Clear PM_WKST_WKUP.ST_IO bit by writing 1 to it.

Step [e] & [c] in each case can be skipped, as these are handled
by the PRCM interrupt handler later.

[1] http://focus.ti.com/pdfs/wtbu/OMAP36xx_ES1.x_PUBLIC_TRM_vV.zip

Signed-off-by: Mohan V <mohanv at ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Reviewed-by: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc69875..b0821a8 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -94,16 +94,17 @@ static void omap3_enable_io_chain(void)
 	/* Do a readback to assure write has been done */
 	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 
-	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
+	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
 		 OMAP3430_ST_IO_CHAIN_MASK)) {
 		timeout++;
 		if (timeout > 1000) {
 			pr_err("Wake up daisy chain activation failed.\n");
 			return;
 		}
-		omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
-					   WKUP_MOD, PM_WKEN);
 	}
+	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+			PM_WKEN);
+
 }
 
 static void omap3_disable_io_chain(void)
-- 
1.7.4.1



From t-kristo at ti.com  Tue Mar  6 10:11:38 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 17:11:38 +0200
Subject: [PATCHv5 2/6] ARM: OMAP3 PM: Move IO Daisychain function to omap3 prm
 file
In-Reply-To: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
Message-ID: <1331046702-2472-3-git-send-email-t-kristo@ti.com>

From: Vishwanath BS <vishwanath.bs at ti.com>

Since IO Daisychain modifies only PRM registers, it makes sense to move
it to PRM File. Also changed the timeout value for IO chain enable to
100us and added a wait for status disable at the end.

Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
---
 arch/arm/mach-omap2/pm34xx.c       |   30 +----------------------------
 arch/arm/mach-omap2/prm2xxx_3xxx.c |   37 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm2xxx_3xxx.h |   14 +++++++++++++
 3 files changed, 52 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b0821a8..e97ec3f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -85,34 +85,6 @@ static inline void omap3_per_restore_context(void)
 	omap_gpio_restore_context();
 }
 
-static void omap3_enable_io_chain(void)
-{
-	int timeout = 0;
-
-	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-				   PM_WKEN);
-	/* Do a readback to assure write has been done */
-	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
-
-	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
-		 OMAP3430_ST_IO_CHAIN_MASK)) {
-		timeout++;
-		if (timeout > 1000) {
-			pr_err("Wake up daisy chain activation failed.\n");
-			return;
-		}
-	}
-	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-			PM_WKEN);
-
-}
-
-static void omap3_disable_io_chain(void)
-{
-	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-				     PM_WKEN);
-}
-
 static void omap3_core_save_context(void)
 {
 	omap3_ctrl_save_padconf();
@@ -324,7 +296,7 @@ void omap_sram_idle(void)
 	     core_next_state < PWRDM_POWER_ON)) {
 		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 		if (omap3_has_io_chain_ctrl())
-			omap3_enable_io_chain();
+			omap3_trigger_io_chain();
 	}
 
 	pwrdm_pre_transition();
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 9ce7654..2f45b96 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -301,6 +301,43 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 }
 
+/*
+ * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
+ * the I/O ring after asserting WUCLKIN high
+ */
+#define MAX_IOPAD_LATCH_TIME 100
+
+/* OMAP3 Daisychain enable sequence */
+void omap3_trigger_io_chain(void)
+{
+	int i = 0;
+
+	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+				   PM_WKEN);
+	/* Do a readback to assure write has been done */
+	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+
+	omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
+			  OMAP3430_ST_IO_CHAIN_MASK,
+			  MAX_IOPAD_LATCH_TIME, i);
+
+	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+				     PM_WKEN);
+
+	omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
+				     PM_WKST);
+
+	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
+}
+
+/* OMAP3 Daisychain disable sequence */
+void omap3_disable_io_chain(void)
+{
+	if (omap_rev() >= OMAP3430_REV_ES3_1)
+		omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK,
+					     WKUP_MOD, PM_WKEN);
+}
+
 static int __init omap3xxx_prcm_init(void)
 {
 	if (cpu_is_omap34xx())
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 70ac2a1..15973aa 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -289,6 +289,18 @@ static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
 		"not suppose to be used on omap4\n");
 	return 0;
 }
+static inline void omap3_trigger_io_chain(void)
+{
+	WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+		"not suppose to be used on omap4\n");
+	return 0;
+}
+static inline void omap3_disable_io_chain(void)
+{
+	WARN(1, "prm: omap2xxx/omap3xxx specific function and "
+		"not suppose to be used on omap4\n");
+	return 0;
+}
 #else
 /* Power/reset management domain register get/set */
 extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
@@ -302,6 +314,8 @@ extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
 extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
 extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
 extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
+extern void omap3_trigger_io_chain(void);
+extern void omap3_disable_io_chain(void);
 
 /* OMAP3-specific VP functions */
 u32 omap3_prm_vp_check_txdone(u8 vp_id);
-- 
1.7.4.1



From t-kristo at ti.com  Tue Mar  6 10:11:39 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 17:11:39 +0200
Subject: [PATCHv5 3/6] ARM: OMAP4 PM: Add IO Daisychain support
In-Reply-To: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
Message-ID: <1331046702-2472-4-git-send-email-t-kristo@ti.com>

From: Rajendra Nayak <rnayak at ti.com>

IO daisychain is a mechanism that allows individual IO pads to generate
wakeup events on their own based on a switch of an input signal level.
This allows the hardware module behind the pad to be powered down, but
still have device level capability to detect IO events, and once this
happens the module can be powered back up to resume IO. See section
3.9.4 in OMAP4430 Public TRM for details.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
---
 arch/arm/mach-omap2/prm44xx.c |   41 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm44xx.h |    1 +
 2 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a37bfd4..caa5e0f 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -231,6 +231,47 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
 				 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
 }
 
+/*
+ * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
+ * the I/O ring after asserting WUCLKIN high
+ */
+#define MAX_IOPAD_LATCH_TIME 100
+
+/* OMAP4 IO Daisychain trigger sequence */
+void omap4_trigger_io_chain(void)
+{
+	int i = 0;
+
+	/* Enable GLOBAL_WUEN */
+	if (!(omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+		OMAP4_PRM_IO_PMCTRL_OFFSET) & OMAP4430_GLOBAL_WUEN_MASK))
+		omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
+			OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET);
+
+	/* Trigger WUCLKIN enable */
+	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
+			OMAP4430_WUCLK_CTRL_MASK, OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET);
+	omap_test_timeout(
+		(((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET) &
+			OMAP4430_WUCLK_STATUS_MASK) >>
+			OMAP4430_WUCLK_STATUS_SHIFT) == 1),
+		MAX_IOPAD_LATCH_TIME, i);
+
+	/* Trigger WUCLKIN disable */
+	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
+			OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_IO_PMCTRL_OFFSET);
+	omap_test_timeout(
+		(((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET) &
+			OMAP4430_WUCLK_STATUS_MASK) >>
+			OMAP4430_WUCLK_STATUS_SHIFT) == 0),
+		MAX_IOPAD_LATCH_TIME, i);
+	return;
+}
+
 static int __init omap4xxx_prcm_init(void)
 {
 	if (cpu_is_omap44xx())
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7978092..54a057e 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -762,6 +762,7 @@ void omap4_prm_vp_clear_txdone(u8 vp_id);
 extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+extern void omap4_trigger_io_chain(void);
 
 /* PRM interrupt-related functions */
 extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
-- 
1.7.4.1



From t-kristo at ti.com  Tue Mar  6 10:11:40 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 17:11:40 +0200
Subject: [PATCHv5 4/6] ARM: OMAP3+: PRM: Enable IO wake up
In-Reply-To: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
Message-ID: <1331046702-2472-5-git-send-email-t-kristo@ti.com>

Enable IO Wake up for OMAP3/4 as part of PRM Init. Currently this has been
managed in cpuidle path which is not the right place. Subsequent patch
will remove IO Daisy chain handling in cpuidle path once daisy chain is
handled as part of hwmod mux. This patch also moves the OMAP4 IO wakeup
enable code from the trigger function to init time setup.

Signed-off-by: Tero Kristo <t-kristo at ti.com>
Reviewed-by: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/prm2xxx_3xxx.c |   11 ++++++++++-
 arch/arm/mach-omap2/prm44xx.c      |   18 ++++++++++--------
 2 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 2f45b96..f0179f6 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -338,10 +338,19 @@ void omap3_disable_io_chain(void)
 					     WKUP_MOD, PM_WKEN);
 }
 
+static void __init omap3_enable_io_wakeup(void)
+{
+	if (omap3_has_io_wakeup())
+		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+					   PM_WKEN);
+}
+
 static int __init omap3xxx_prcm_init(void)
 {
-	if (cpu_is_omap34xx())
+	if (cpu_is_omap34xx()) {
+		omap3_enable_io_wakeup();
 		return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
+	}
 	return 0;
 }
 subsys_initcall(omap3xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index caa5e0f..4ce6f08 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -242,13 +242,6 @@ void omap4_trigger_io_chain(void)
 {
 	int i = 0;
 
-	/* Enable GLOBAL_WUEN */
-	if (!(omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
-		OMAP4_PRM_IO_PMCTRL_OFFSET) & OMAP4430_GLOBAL_WUEN_MASK))
-		omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
-			OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_PRM_DEVICE_INST,
-			OMAP4_PRM_IO_PMCTRL_OFFSET);
-
 	/* Trigger WUCLKIN enable */
 	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
 			OMAP4430_WUCLK_CTRL_MASK, OMAP4430_PRM_DEVICE_INST,
@@ -272,10 +265,19 @@ void omap4_trigger_io_chain(void)
 	return;
 }
 
+static void __init omap4_enable_io_wakeup(void)
+{
+	omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
+			OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET);
+}
+
 static int __init omap4xxx_prcm_init(void)
 {
-	if (cpu_is_omap44xx())
+	if (cpu_is_omap44xx()) {
+		omap4_enable_io_wakeup();
 		return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+	}
 	return 0;
 }
 subsys_initcall(omap4xxx_prcm_init);
-- 
1.7.4.1



From t-kristo at ti.com  Tue Mar  6 10:11:42 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 17:11:42 +0200
Subject: [PATCHv5 6/6] ARM: OMAP3 PM: Remove IO Daisychain control from cpuidle
In-Reply-To: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
Message-ID: <1331046702-2472-7-git-send-email-t-kristo@ti.com>

From: Vishwanath BS <vishwanath.bs at ti.com>

As IO Daisy chain sequence is triggered via hwmod mux, there is no need to
control it from cpuidle path for OMAP3.

Also as omap3_disable_io_chain is no longer being used, just remove the
function.

Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
Reviewed-by: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/pm34xx.c       |   17 -----------------
 arch/arm/mach-omap2/prm2xxx_3xxx.c |    8 --------
 arch/arm/mach-omap2/prm2xxx_3xxx.h |    7 -------
 3 files changed, 0 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e97ec3f..ed12bb4 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -291,13 +291,6 @@ void omap_sram_idle(void)
 	/* Enable IO-PAD and IO-CHAIN wakeups */
 	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
-	if (omap3_has_io_wakeup() &&
-	    (per_next_state < PWRDM_POWER_ON ||
-	     core_next_state < PWRDM_POWER_ON)) {
-		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
-		if (omap3_has_io_chain_ctrl())
-			omap3_trigger_io_chain();
-	}
 
 	pwrdm_pre_transition();
 
@@ -376,16 +369,6 @@ void omap_sram_idle(void)
 			omap3_per_restore_context();
 	}
 
-	/* Disable IO-PAD and IO-CHAIN wakeup */
-	if (omap3_has_io_wakeup() &&
-	    (per_next_state < PWRDM_POWER_ON ||
-	     core_next_state < PWRDM_POWER_ON)) {
-		omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
-					     PM_WKEN);
-		if (omap3_has_io_chain_ctrl())
-			omap3_disable_io_chain();
-	}
-
 	clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 }
 
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index f0179f6..b8962fe 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -330,14 +330,6 @@ void omap3_trigger_io_chain(void)
 	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
 }
 
-/* OMAP3 Daisychain disable sequence */
-void omap3_disable_io_chain(void)
-{
-	if (omap_rev() >= OMAP3430_REV_ES3_1)
-		omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK,
-					     WKUP_MOD, PM_WKEN);
-}
-
 static void __init omap3_enable_io_wakeup(void)
 {
 	if (omap3_has_io_wakeup())
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 15973aa..391b844 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -295,12 +295,6 @@ static inline void omap3_trigger_io_chain(void)
 		"not suppose to be used on omap4\n");
 	return 0;
 }
-static inline void omap3_disable_io_chain(void)
-{
-	WARN(1, "prm: omap2xxx/omap3xxx specific function and "
-		"not suppose to be used on omap4\n");
-	return 0;
-}
 #else
 /* Power/reset management domain register get/set */
 extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
@@ -315,7 +309,6 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
 extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
 extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
 extern void omap3_trigger_io_chain(void);
-extern void omap3_disable_io_chain(void);
 
 /* OMAP3-specific VP functions */
 u32 omap3_prm_vp_check_txdone(u8 vp_id);
-- 
1.7.4.1



From t-kristo at ti.com  Tue Mar  6 10:11:41 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 17:11:41 +0200
Subject: [PATCHv5 5/6] ARM: OMAP3PLUS PM: Add IO Daisychain support via hwmod
 mux
In-Reply-To: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
Message-ID: <1331046702-2472-6-git-send-email-t-kristo@ti.com>

From: Vishwanath BS <vishwanath.bs at ti.com>

IO Daisychain feature has to be triggered whenever there is a change in
device's mux configuration (See section 3.9.4 in OMAP4 Public TRM vP).

Now devices can idle independent of the powerdomain, there can be a
window where device is idled and corresponding powerdomain can be
ON/INACTIVE state. In such situations, since both module wake up is
enabled at padlevel as well as io daisychain sequence is triggered,
there will be 2 PRCM interrupts (Module async wake up via swakeup and
IO Pad interrupt). But as PRCM Interrupt handler clears the Module
Padlevel WKST bit in the first interrupt, module specific interrupt
handler will not triggered for the second time

Also look at detailed explanation given by Rajendra at
http://www.spinics.net/lists/linux-serial/msg04480.html

Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    9 +++++++--
 arch/arm/mach-omap2/pm.c         |   21 +++++++++++++++++++++
 arch/arm/mach-omap2/pm.h         |    1 +
 3 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5192cab..56adbfb 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -152,6 +152,7 @@
 #include "prm44xx.h"
 #include "prminst44xx.h"
 #include "mux.h"
+#include "pm.h"
 
 /* Maximum microseconds to wait for OMAP module to softreset */
 #define MAX_MODULE_SOFTRESET_WAIT	10000
@@ -1535,8 +1536,10 @@ static int _enable(struct omap_hwmod *oh)
 	/* Mux pins for device runtime if populated */
 	if (oh->mux && (!oh->mux->enabled ||
 			((oh->_state == _HWMOD_STATE_IDLE) &&
-			 oh->mux->pads_dynamic)))
+			 oh->mux->pads_dynamic))) {
 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+		omap_trigger_io_chain();
+	}
 
 	_add_initiator_dep(oh, mpu_oh);
 
@@ -1622,8 +1625,10 @@ static int _idle(struct omap_hwmod *oh)
 		clkdm_hwmod_disable(oh->clkdm, oh);
 
 	/* Mux pins for device idle if populated */
-	if (oh->mux && oh->mux->pads_dynamic)
+	if (oh->mux && oh->mux->pads_dynamic) {
 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+		omap_trigger_io_chain();
+	}
 
 	oh->_state = _HWMOD_STATE_IDLE;
 
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 1881fe9..b7ac0f4 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -25,8 +25,12 @@
 #include "clockdomain.h"
 #include "pm.h"
 #include "twl-common.h"
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
 
 static struct omap_device_pm_latency *pm_lats;
+static void (*io_chain_trigger_func) (void);
+static DEFINE_SPINLOCK(io_chain_lock);
 
 static int _init_omap_device(char *name)
 {
@@ -64,6 +68,17 @@ static void omap2_init_processor_devices(void)
 	}
 }
 
+void omap_trigger_io_chain(void)
+{
+	unsigned long flags;
+
+	if (io_chain_trigger_func) {
+		spin_lock_irqsave(&io_chain_lock, flags);
+		io_chain_trigger_func();
+		spin_unlock_irqrestore(&io_chain_lock, flags);
+	}
+}
+
 /* Types of sleep_switch used in omap_set_pwrdm_state */
 #define FORCEWAKEUP_SWITCH	0
 #define LOWPOWERSTATE_SWITCH	1
@@ -221,6 +236,12 @@ static int __init omap2_common_pm_init(void)
 		omap2_init_processor_devices();
 	omap_pm_if_init();
 
+	if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl())
+		io_chain_trigger_func = omap3_trigger_io_chain;
+
+	if (cpu_is_omap44xx())
+		io_chain_trigger_func = omap4_trigger_io_chain;
+
 	return 0;
 }
 postcore_initcall(omap2_common_pm_init);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index b737b11..f9dac40 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -22,6 +22,7 @@ extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
 extern int omap4_idle_init(void);
+extern void omap_trigger_io_chain(void);
 
 #if defined(CONFIG_PM_OPP)
 extern int omap3_opp_init(void);
-- 
1.7.4.1



From fabio.estevam at freescale.com  Tue Mar  6 10:26:08 2012
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Tue, 6 Mar 2012 12:26:08 -0300
Subject: I.MX35 PDK
In-Reply-To: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A26@MEP-EXCH.meprolight.com>
References: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A26@MEP-EXCH.meprolight.com>
Message-ID: <4F562C90.6090103@freescale.com>

Alex Gershgorin wrote:
> Hi Fabio,
> 
>  
> 
> How I can get information about accesses to CMOS_RST_B and CSI_PWDN bits
> of MC9S08DZ60 processor.
> 
> I need address of this register and bits mapping in this register.  

You can check Freescale kernel to get this information:
http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=shortlog;h=refs/heads/imx_2.6.31

Search for "pmic_gpio_set_bit_val"

Wu Guoxing submitted the mc9s08dz60 driver patch to mainline:
drivers/gpio/gpio-mc9s08dz60.c

Regards,

Fabio Estevam




From monstr at monstr.eu  Tue Mar  6 10:22:06 2012
From: monstr at monstr.eu (Michal Simek)
Date: Tue, 06 Mar 2012 16:22:06 +0100
Subject: remoteproc: Load coprocessor code to the specific main memory
 location
In-Reply-To: <CAK=Wgbaa9rv1pg19sWYFVX_Dvt0J0AzbRtKhPVnhP6WGdMeT9A@mail.gmail.com>
References: <4F1EE861.4030405@monstr.eu> <4F200F64.9060203@monstr.eu>
 <CAK=WgbZDADRf1OF=uWbbsF+t2dx36tqj=kRftn5nd4RA7DtEnA@mail.gmail.com>
 <4F212E9E.9060807@monstr.eu>
 <CAK=WgbYMBDp3Qm8TErNrnDwn2ZTFt62+OuyyQvVE-jrnNsL6kg@mail.gmail.com>
 <4F391C1D.9020402@monstr.eu>
 <CAK=WgbYn6hrS4YLEdfp=0jSEfEwy-HkJmt5S06_j6gZFf0UTmQ@mail.gmail.com>
 <4F3BA962.9040109@monstr.eu> <4F3BC30A.4030301@monstr.eu>
 <4F3CC899.4070302@monstr.eu>
 <CAK=WgbaRF-L7M3VMZQdqFLUFOJuwFVkBH1hUNuJ51kSrzkaVjA@mail.gmail.com>
 <4F3CFFAD.9030402@monstr.eu> <4F3D032B.6090700@monstr.eu>
 <CAK=WgbZ3oXc+NQscdShqmu2wkzv=M-qBDCH2-k=5qSRX9W=z3Q@mail.gmail.com>
 <CAHTX3dJ4PruKO-wJLJU8W0boHFL0f6eoF+QNaoNjm5hu26YEow@mail.gmail.com>
 <CAK=WgbZBJJbFcoeZ+hY=BgyW_4yvOJPVNMZ18_9o+zY7tEc_pQ@mail.gmail.com>
 <4F425711.80102@monstr.eu>
 <CAK=WgbbNJMpndKqgW4SJjE=H-BqT7yVsB+F-kEfJWmW+ikJM+A@mail.gmail.com>
 <4F44DB23.4010303@monstr.eu>
 <CAK=Wgbaa9rv1pg19sWYFVX_Dvt0J0AzbRtKhPVnhP6WGdMeT9A@mail.gmail.com>
Message-ID: <4F562B9E.7060302@monstr.eu>

Hi Ohad,

Ohad Ben-Cohen wrote:
> On Wed, Feb 22, 2012 at 2:10 PM, Michal Simek <monstr at monstr.eu> wrote:
>> That will be great to get it. Please let me know when you have them.
> 
> Will do.

I have got the pandaboard (revision A3). u-boot and linux is running on it.
I just need to compile ducati-m3-core0.xem3

I have found the manual at https://github.com/GAnthony/syslink3

In sysbios-rpmsg readme I have found some TI tools which are required
and there is any compilation failure. I think it is because of missing CGT tools

        3) CGT TMS470: 4.9.0
           Public Links:-
             TMS470 Compiler is not available for free publicly. Please contact your TI representative.

Is it possible to compile firmware with this compiler?


I have also tried your bios version at
git://github.com/ohadbc/sysbios-rpmsg.git
branch: rpmsg_3.3_rc1_TLV

compilation passed but it doesn't generate bin file. :-(
I will investigate it tmr.

I would like to compile that bin file myself to be able to add some debug messages.

Thanks for your help,
Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian


From arnd at arndb.de  Tue Mar  6 10:29:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 15:29:37 +0000
Subject: [PATCH v4] ARM: LPC32xx: Ethernet support
In-Reply-To: <1330983687-32678-1-git-send-email-stigge@antcom.de>
References: <1330983687-32678-1-git-send-email-stigge@antcom.de>
Message-ID: <201203061529.37551.arnd@arndb.de>

On Monday 05 March 2012, Roland Stigge wrote:
> 
> This patch adds ethernet support to the LPC32xx ARM architecture. The actual
> driver in drivers/net is contained in a separate patch.
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>
> 

Acked-by: Arnd Bergmann <arnd at arndb.de>


From alexg at meprolight.com  Tue Mar  6 10:35:51 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Tue, 6 Mar 2012 17:35:51 +0200
Subject: I.MX35 PDK
In-Reply-To: <4F562C90.6090103@freescale.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A27@MEP-EXCH.meprolight.com>

Thanks Fabio :-) 

-----Original Message-----
From: Fabio Estevam [mailto:fabio.estevam at freescale.com] 
Sent: Tuesday, March 06, 2012 5:26 PM
To: Alex Gershgorin
Cc: linux-arm-kernel at lists.infradead.org; kernel at pengutronix.de; festevam at gmail.com
Subject: Re: I.MX35 PDK

Alex Gershgorin wrote:
> Hi Fabio,
> 
>  
> 
> How I can get information about accesses to CMOS_RST_B and CSI_PWDN bits
> of MC9S08DZ60 processor.
> 
> I need address of this register and bits mapping in this register.  

You can check Freescale kernel to get this information:
http://opensource.freescale.com/git?p=imx/linux-2.6-imx.git;a=shortlog;h=refs/heads/imx_2.6.31

Search for "pmic_gpio_set_bit_val"

Wu Guoxing submitted the mc9s08dz60 driver patch to mainline:
drivers/gpio/gpio-mc9s08dz60.c

Regards,

Alex Gershgorin




From shawn.guo at linaro.org  Tue Mar  6 10:50:57 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 6 Mar 2012 23:50:57 +0800
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120305174232.GA3852@pengutronix.de>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
 <20120305174232.GA3852@pengutronix.de>
Message-ID: <20120306155055.GA13802@S2101-09.ap.freescale.net>

On Mon, Mar 05, 2012 at 06:42:32PM +0100, Sascha Hauer wrote:
> On Mon, Mar 05, 2012 at 10:31:05PM +0800, Shawn Guo wrote:
> > This is the initial imx-sgtl5000 machine driver support with only
> > playback dai link implemented.  More features can be added on top
> > of it later.
> 
> Are there problems with capturing? It should be trivial to add and
> it would be much more confident that this series as a whole works as
> expected.
> 
I worked all day long to try to give that answer.  Here it is.

No, there is no problem with capturing on fsl_ssi + imx_pcm_dma +
imx_sgtl5000 side.  But there is a problem with sgtl5000 codec driver.
With that problem fixed in sgtl5000, this series works just fine with
capturing.  (I'm not sure I want to fix it within this series though,
as it's already big enough.)

-- 
Regards,
Shawn


From bhutchings at solarflare.com  Tue Mar  6 10:37:37 2012
From: bhutchings at solarflare.com (Ben Hutchings)
Date: Tue, 6 Mar 2012 15:37:37 +0000
Subject: [PATCH v4] lpc32xx: Added ethernet driver: smp_wmb()
In-Reply-To: <20120306141745.GA15201@n2100.arm.linux.org.uk>
References: <1330983641-32622-1-git-send-email-stigge@antcom.de>
 <1330987524.2538.61.camel@bwh-desktop> <4F55EA6D.3070602@antcom.de>
 <1331042608.2347.1.camel@bwh-desktop>
 <20120306141745.GA15201@n2100.arm.linux.org.uk>
Message-ID: <1331048257.2333.4.camel@bwh-desktop>

On Tue, 2012-03-06 at 14:17 +0000, Russell King - ARM Linux wrote:
> On Tue, Mar 06, 2012 at 02:03:28PM +0000, Ben Hutchings wrote:
> > On Tue, 2012-03-06 at 11:43 +0100, Roland Stigge wrote:
> > > On 03/05/2012 11:45 PM, Ben Hutchings wrote:
> > > >> +	/* Clear and enable interrupts */
> > > >> +	writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
> > > >> +	lpc_eth_enable_int(pldat->net_base);
> > > >> +
> > > >> +	/* Get the next TX buffer output index */
> > > >> +	pldat->num_used_tx_buffs = 0;
> > > >> +	pldat->last_tx_idx =
> > > >> +		readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
> > > > 
> > > > Doesn't this need to be done *before* enabling interrupts?  Also, I
> > > > think you need an smp_wmb() so that the interrupt handler is guaranteed
> > > > to see all these writes.
> > > 
> > > Do you mean _one_ smp_wmb() directly after lpc_eth_enable_int() (which
> > > I'm moving behind the above code?
> > 
> > The sequence should be
> > 
> > 	pldat->state = values...;
> > 	smp_wmb();
> > 	enable_interrupts();
> 
> Is this correct?
> 
> "SMP BARRIER PAIRING" and "EXAMPLES OF MEMORY BARRIER SEQUENCES" in
> Documentation/memory-barriers.txt suggest that there should be some kind
> of pairing with smp_wmb() to ensure correctness.

The thread we're synchronising with (the interrupt handler) starts
*after* the smp_wmb().  Therefore there is no need for a second barrier.

Ben.

-- 
Ben Hutchings, Staff Engineer, Solarflare
Not speaking for my employer; that's the marketing department's job.
They asked us to note that Solarflare product names are trademarked.




From arnd at arndb.de  Tue Mar  6 10:38:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 15:38:11 +0000
Subject: [PATCH v3 02/10] pwm: Allow chips to support multiple PWMs.
In-Reply-To: <20120303193249.GA22021@avionic-0098.mockup.avionic-design.de>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <20120223160420.GA9899@avionic-0098.mockup.avionic-design.de>
 <20120303193249.GA22021@avionic-0098.mockup.avionic-design.de>
Message-ID: <201203061538.11709.arnd@arndb.de>

On Saturday 03 March 2012, Thierry Reding wrote:
>   * Thierry Reding wrote:
> > * Arnd Bergmann wrote:
> > > On Thursday 23 February 2012, Thierry Reding wrote:
> > > > > Is this only used for the device tree functions? If so, I would recommend
> > > > > making it less generic and always search for a device node.
> > > > 
> > > > It is currently only used to look up a struct pwm_chip for a given struct
> > > > device_node, yes. But I can see other uses for this. For instance this could
> > > > be useful if we ever want to provide an alternative way of requesting a PWM
> > > > on a per-chip basis.
> > > 
> > > Nah, just keep it simple for now. If we need it later, we can still
> > > add something like this back, but for now it's just a source of
> > > confusion and possible bugs.
> > 
> > Will do.
> 
> I turns out that this is not as easy to do as I thought. The problem is that
> if I remove the pwmchip_find() from the core and move the lookup
> functionality into the OF support code I no longer have access to the list of
> PWM chips. So I guess it will have to stay in to keep things encapsulated
> properly.

Well, or you move everything into the one file. If you have the device tree
support function in the same file as everything else, you no longer need
the additional complexity.

	Arnd


From arnd at arndb.de  Tue Mar  6 10:45:58 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 15:45:58 +0000
Subject: [GIT PULL] ux500 fixes for v3.4, take 3
In-Reply-To: <1330626847-3266-1-git-send-email-linus.walleij@linaro.org>
References: <1330626847-3266-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <201203061545.59032.arnd@arndb.de>

On Thursday 01 March 2012, Linus Walleij wrote:
> Hi ARM-SoC maintainers,
> 
> here is an updated pull request for the 3.4 merge window, and I
> still expect it to be pretty orthogonal to most other stuff going on
> except for maybe Lee Jones' SoC bus patches.
> 
> I've left the two U9540 patches off this pull request, I may
> present these separately if I get to test the fix suggested
> by Arnd, in the meantime this is up for grabs.
> 
> The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:
> 
>   Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)
> 
> are available in the git repository at:
>   git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git/ ux500-fixes-20120301

Sorry for the delay and thanks for the reminder, I pulled it into
next/fixes-non-critical now.

	Arnd


From nm at ti.com  Tue Mar  6 10:57:27 2012
From: nm at ti.com (Nishanth Menon)
Date: Tue, 6 Mar 2012 09:57:27 -0600
Subject: [PATCHv5 2/6] ARM: OMAP3 PM: Move IO Daisychain function to
 omap3 prm file
In-Reply-To: <1331046702-2472-3-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-3-git-send-email-t-kristo@ti.com>
Message-ID: <20120306155725.GA30895@senorita.am.dhcp.ti.com>

On 17:11-20120306, Tero Kristo wrote:
> From: Vishwanath BS <vishwanath.bs at ti.com>
> 
> Since IO Daisychain modifies only PRM registers, it makes sense to move
> it to PRM File. Also changed the timeout value for IO chain enable to
> 100us and added a wait for status disable at the end.
[...]
> diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> index 9ce7654..2f45b96 100644
> --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
> +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> @@ -301,6 +301,43 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
>  				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
>  }
>  
> +/*
> + * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
> + * the I/O ring after asserting WUCLKIN high
> + */
> +#define MAX_IOPAD_LATCH_TIME 100
> +
> +/* OMAP3 Daisychain enable sequence */
> +void omap3_trigger_io_chain(void)
> +{
> +	int i = 0;
> +
> +	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> +				   PM_WKEN);
> +	/* Do a readback to assure write has been done */
> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
> +
> +	omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
> +			  OMAP3430_ST_IO_CHAIN_MASK,
> +			  MAX_IOPAD_LATCH_TIME, i);
probably a nitpick, but would'nt you like to keep the OMAP3 and OMAP4
style consistent?
> +
> +	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> +				     PM_WKEN);
> +
> +	omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
> +				     PM_WKST);
> +
> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
in the previous iteration it had:
omap_test_timeout(((omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
OMAP3430_ST_IO_CHAIN_MASK) == 0),
MAX_IOPAD_LATCH_TIME,
i);
gone now?
-- 
Regards,
Nishanth Menon


From jason at lakedaemon.net  Tue Mar  6 10:58:40 2012
From: jason at lakedaemon.net (Jason)
Date: Tue, 6 Mar 2012 10:58:40 -0500
Subject: [RFC 00/14] Generic clk for Orion platforms.
In-Reply-To: <1331015471-28872-1-git-send-email-andrew@lunn.ch>
References: <1331015471-28872-1-git-send-email-andrew@lunn.ch>
Message-ID: <20120306155840.GS5050@titan.lakedaemon.net>

On Tue, Mar 06, 2012 at 07:30:56AM +0100, Andrew Lunn wrote:
> This patch set starts the process of changing Orion based platforms to
> use the generic clk framework. The first patch fixes compile problems
> with the framework, and is expected to be dropped once fixed upstream.
> Then clks are added. This is a fixed rate clk for tclk and for
> kirkwood, most of the gated clocks also get a clk. The following
> patches then modified the drivers to make use of these clocks,
> getting, prepareing, enabling at probe time, and disableing,
> unprepareing, and putting at remove time. Rather than pass the clock
> frequency as platform_data, the driver now uses clk_get_rate(). This
> results in some platform_data structures becoming redundant, and so
> are removed.

Awesome, thanks for posting!

> TODO:
> 
>  0) Cleanup the white space changes, and hunks in the wrong patches.

It would be helpful to break out code cleanup as well.  eg spi_clock_fix
removal, sound platform data removal, and anything else I didn't see on
initial read through.

>  1) PCIe needs adopting to use clks.
>  2) Strip out all references to kirkwood_clk_ctrl
>  3) Find a solution for turning off unused clks - Probably needs
>     framework support, which Mike has already suggested.

I'm assuming the driver(s) will increment a reference, so when it
reaches zero, the framework would call a clk_gate hook.

>  4) Find a solution for tuning off unused SATA and PCIe PHYs. Maybe
>     use the unprepare() method, but the current basic clk providers 
>     don't support this.

It looks like each SATA and PCIe PHY has it's own clock and it's own
shutdown (kirkwood_clock_gate()).  If the return value of unprepare
indicated a clock was gated (all references gone), then the driver could
shut down the PHY.  Or, am I missing something?

> If we are willing to accept a regression in power usage, we could skip
> 3) and 4) for the moment in order to get this code into use. That
> would help the device tree work which benefits from not having to deal
> with clock frequencies when setting up device driver bindings.
> 
> Boot tested on kirkwood. No testing what so ever on other Orion
> platforms.
> 
> Based on 
> 
> git://git.linaro.org/people/mturquette/linux.git v3.3-rc5-clkv5
> 
> 
> Andrew Lunn (14):
>   [clk] Fix compile errors in DEFINE_CLK_GATE()
>   ARM: Orion: Add clocks using the generic clk infrastructure.
>   Arm: Orion: spi: Add clk/clkdev support.
>   orion: spi: remove enable_clock_fix which is not used
>   Arm: Orion: eth: Add clk/clkdev support.
>   ARM: Orion: wdt: Add clk/clkdev support
>   ARM: Orion: uart: Get the clock rate via clk_get_rate().
>   ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data.
>   MV SATA: Add per channel clk/clkdev support.
>   [Orion ehci] Add support for enabling clocks
>   [Orion nand] Add support for clk, if there is one.
>   [Orion sdio] Add support for clk.
>   [Orion crypto] Add support for clk
>   [Orion xor] Add support for clk
> 
>  arch/arm/Kconfig                                  |    3 +
>  arch/arm/mach-dove/common.c                       |   37 ++++---
>  arch/arm/mach-dove/dove-db-setup.c                |    1 -
>  arch/arm/mach-kirkwood/common.c                   |  119 +++++++++++++++++----
>  arch/arm/mach-kirkwood/include/mach/bridge-regs.h |   16 +++
>  arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c    |    1 -
>  arch/arm/mach-kirkwood/rd88f6192-nas-setup.c      |    1 -
>  arch/arm/mach-kirkwood/t5325-setup.c              |    1 -
>  arch/arm/mach-kirkwood/tsx1x-common.c             |    1 -
>  arch/arm/mach-mv78xx0/common.c                    |   44 +++++---
>  arch/arm/mach-orion5x/common.c                    |   26 ++++-
>  arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c      |    1 -
>  arch/arm/plat-orion/common.c                      |   88 ++++++++-------
>  arch/arm/plat-orion/include/plat/audio.h          |    1 -
>  arch/arm/plat-orion/include/plat/common.h         |   26 +++--
>  arch/arm/plat-orion/include/plat/orion_wdt.h      |   18 ---
>  drivers/ata/sata_mv.c                             |   43 +++++++-
>  drivers/clk/clk.c                                 |    1 +
>  drivers/crypto/mv_cesa.c                          |   15 +++
>  drivers/dma/mv_xor.c                              |   16 +++
>  drivers/dma/mv_xor.h                              |    1 +
>  drivers/mmc/host/mvsdio.c                         |   14 +++
>  drivers/mtd/nand/orion_nand.c                     |   18 +++
>  drivers/net/ethernet/marvell/mv643xx_eth.c        |   46 ++++++--
>  drivers/spi/spi-orion.c                           |   37 +++++--
>  drivers/usb/host/ehci-orion.c                     |   16 +++
>  drivers/watchdog/orion_wdt.c                      |   18 ++-
>  include/linux/clk-private.h                       |    4 +-
>  include/linux/mv643xx_eth.h                       |    1 -
>  include/linux/spi/orion_spi.h                     |   18 ---
>  30 files changed, 443 insertions(+), 189 deletions(-)
>  delete mode 100644 arch/arm/plat-orion/include/plat/orion_wdt.h
>  delete mode 100644 include/linux/spi/orion_spi.h
> 
> -- 
> 1.7.9.1
> 


From arnd at arndb.de  Tue Mar  6 10:58:41 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 15:58:41 +0000
Subject: ep93xx: convert vision_ep9307 to MULTI_IRQ_HANDLER
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F001F41FF55112@AUSP01VMBX24.collaborationhost.net>
References: <201203011713.59663.hartleys@visionengravers.com>
 <ADE657CA350FB648AAC2C43247A983F001F41FF55112@AUSP01VMBX24.collaborationhost.net>
Message-ID: <201203061558.41730.arnd@arndb.de>

On Saturday 03 March 2012, H Hartley Sweeten wrote:
> On Thursday, March 01, 2012 5:14 PM, H Hartley Sweeten wrote:
> > As done for the other ep93xx machines in:
> >
> > commit 9a6879bd902e2ec605fff4d9fb3247b440a1f66a
> > ARM: ep93xx: convert to MULTI_IRQ_HANDLER
> >
> > Now that there is a generic IRQ handler for multiple VIC devices use it
> > for vision_ep9307 to help building multi platform kernels.
> >
> > Signed-off-by: Hartley Sweeten <hsweeten at visionengravers.com>
> > Acked-by: Ryan Mallon <rmallon at gmail.com>
> > Reviewed-by: Jamie Iles <jamie at jamieiles.com>
> 
> Arnd,
> 
> Could you merge this into linux-next?
> 
> It needs to go in when commit 9a6879bd902e2ec605fff4d9fb3247b440a1f66a
> is merged into mainline. Otherwise the vision_ep9307 machine will not work.

Applied to the fixes branch now, will send it out soon.

Thanks,

	Arnd


From arnd at arndb.de  Tue Mar  6 11:04:53 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 16:04:53 +0000
Subject: revert merge commit de68f28 in for-next?
In-Reply-To: <20120306144415.GR5050@titan.lakedaemon.net>
References: <20120306144415.GR5050@titan.lakedaemon.net>
Message-ID: <201203061604.53412.arnd@arndb.de>

On Tuesday 06 March 2012, Jason wrote:
> As much as I'd love to see this go in right now, I don't think it's the
> correct version (from Mar 2).  This is the merge commit in question:
> 
> de68f2847fa759df54e9d8eb0013a0f8ea959c22
> 
> It's missing several fixes, #ifdef CONFIG_OF around struct of_device_id,
> marvell -> mrvl in compatible properties, etc.
> 
> Would you like me to submit a new pull request, or base my fixes off of
> this and submit new patches?
> 
> Thanks and sorry for the confusion,
> 

I've marked that branch a 'staging/' branch, which means that it's not
intended for being sent to Linus. Please send a replacement branch instead.

Once something is merged into a next/* branch instead of staging/*, you
should send further patches on top.

	Arnd


From t-kristo at ti.com  Tue Mar  6 11:05:37 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Tue, 6 Mar 2012 18:05:37 +0200
Subject: [PATCHv5 2/6] ARM: OMAP3 PM: Move IO Daisychain function to
 omap3 prm file
In-Reply-To: <20120306155725.GA30895@senorita.am.dhcp.ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-3-git-send-email-t-kristo@ti.com>
 <20120306155725.GA30895@senorita.am.dhcp.ti.com>
Message-ID: <1331049937.2116.168.camel@sokoban>

On Tue, 2012-03-06 at 09:57 -0600, Nishanth Menon wrote:
> On 17:11-20120306, Tero Kristo wrote:
> > From: Vishwanath BS <vishwanath.bs at ti.com>
> > 
> > Since IO Daisychain modifies only PRM registers, it makes sense to move
> > it to PRM File. Also changed the timeout value for IO chain enable to
> > 100us and added a wait for status disable at the end.
> [...]
> > diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> > index 9ce7654..2f45b96 100644
> > --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
> > +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
> > @@ -301,6 +301,43 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
> >  				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
> >  }
> >  
> > +/*
> > + * Maximum time(us) it takes to output the signal WUCLKOUT of the last pad of
> > + * the I/O ring after asserting WUCLKIN high
> > + */
> > +#define MAX_IOPAD_LATCH_TIME 100
> > +
> > +/* OMAP3 Daisychain enable sequence */
> > +void omap3_trigger_io_chain(void)
> > +{
> > +	int i = 0;
> > +
> > +	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> > +				   PM_WKEN);
> > +	/* Do a readback to assure write has been done */
> > +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
> > +
> > +	omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
> > +			  OMAP3430_ST_IO_CHAIN_MASK,
> > +			  MAX_IOPAD_LATCH_TIME, i);
> probably a nitpick, but would'nt you like to keep the OMAP3 and OMAP4
> style consistent?
> > +
> > +	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> > +				     PM_WKEN);
> > +
> > +	omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
> > +				     PM_WKST);
> > +
> > +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
> in the previous iteration it had:
> omap_test_timeout(((omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
> OMAP3430_ST_IO_CHAIN_MASK) == 0),
> MAX_IOPAD_LATCH_TIME,
> i);
> gone now?

Yea, according to TRM this is not what should be done on omap3,
apparently one of the comments I received was in error for one of the
previous versions. Also, the implementation in patch 1 is closer to what
is here now.

-Tero



From andrew at lunn.ch  Tue Mar  6 11:17:43 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 6 Mar 2012 17:17:43 +0100
Subject: [RFC 00/14] Generic clk for Orion platforms.
In-Reply-To: <20120306155840.GS5050@titan.lakedaemon.net>
References: <1331015471-28872-1-git-send-email-andrew@lunn.ch>
 <20120306155840.GS5050@titan.lakedaemon.net>
Message-ID: <20120306161743.GI24858@lunn.ch>

On Tue, Mar 06, 2012 at 10:58:40AM -0500, Jason wrote:
> On Tue, Mar 06, 2012 at 07:30:56AM +0100, Andrew Lunn wrote:
> > This patch set starts the process of changing Orion based platforms to
> > use the generic clk framework. The first patch fixes compile problems
> > with the framework, and is expected to be dropped once fixed upstream.
> > Then clks are added. This is a fixed rate clk for tclk and for
> > kirkwood, most of the gated clocks also get a clk. The following
> > patches then modified the drivers to make use of these clocks,
> > getting, prepareing, enabling at probe time, and disableing,
> > unprepareing, and putting at remove time. Rather than pass the clock
> > frequency as platform_data, the driver now uses clk_get_rate(). This
> > results in some platform_data structures becoming redundant, and so
> > are removed.
> 
> Awesome, thanks for posting!
> 
> > TODO:
> > 
> >  0) Cleanup the white space changes, and hunks in the wrong patches.
> 
> It would be helpful to break out code cleanup as well.  eg spi_clock_fix
> removal, sound platform data removal, and anything else I didn't see on
> initial read through.

I could move these out, but they actually help you. It means there is
less for you to add DT support for. If they are left in, you need to
add a DT property for spi_clock_fix, etc.
 
> >  1) PCIe needs adopting to use clks.
> >  2) Strip out all references to kirkwood_clk_ctrl
> >  3) Find a solution for turning off unused clks - Probably needs
> >     framework support, which Mike has already suggested.
> 
> I'm assuming the driver(s) will increment a reference, so when it
> reaches zero, the framework would call a clk_gate hook.

You missed an important point. No driver has claimed these, but u-boot
has turned them on. So we want linux to turn off all clocks for which
there is no driver using them, in order to save power.
kirkwood_clk_ctrl is dual purpose. It turns on needed clocks, but it
also turns off unneeded clocks.
 
> >  4) Find a solution for tuning off unused SATA and PCIe PHYs. Maybe
> >     use the unprepare() method, but the current basic clk providers 
> >     don't support this.
> 
> It looks like each SATA and PCIe PHY has it's own clock and it's own
> shutdown (kirkwood_clock_gate()).  If the return value of unprepare
> indicated a clock was gated (all references gone), then the driver could
> shut down the PHY.  Or, am I missing something?

Yes, same comment as above. We want to turn off PHYs which don't have
a driver.

  Andrew


From ohad at wizery.com  Tue Mar  6 11:26:16 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Tue, 6 Mar 2012 18:26:16 +0200
Subject: remoteproc: Load coprocessor code to the specific main memory
 location
In-Reply-To: <4F562B9E.7060302@monstr.eu>
References: <4F1EE861.4030405@monstr.eu> <4F200F64.9060203@monstr.eu>
 <CAK=WgbZDADRf1OF=uWbbsF+t2dx36tqj=kRftn5nd4RA7DtEnA@mail.gmail.com>
 <4F212E9E.9060807@monstr.eu>
 <CAK=WgbYMBDp3Qm8TErNrnDwn2ZTFt62+OuyyQvVE-jrnNsL6kg@mail.gmail.com>
 <4F391C1D.9020402@monstr.eu>
 <CAK=WgbYn6hrS4YLEdfp=0jSEfEwy-HkJmt5S06_j6gZFf0UTmQ@mail.gmail.com>
 <4F3BA962.9040109@monstr.eu> <4F3BC30A.4030301@monstr.eu>
 <4F3CC899.4070302@monstr.eu>
 <CAK=WgbaRF-L7M3VMZQdqFLUFOJuwFVkBH1hUNuJ51kSrzkaVjA@mail.gmail.com>
 <4F3CFFAD.9030402@monstr.eu> <4F3D032B.6090700@monstr.eu>
 <CAK=WgbZ3oXc+NQscdShqmu2wkzv=M-qBDCH2-k=5qSRX9W=z3Q@mail.gmail.com>
 <CAHTX3dJ4PruKO-wJLJU8W0boHFL0f6eoF+QNaoNjm5hu26YEow@mail.gmail.com>
 <CAK=WgbZBJJbFcoeZ+hY=BgyW_4yvOJPVNMZ18_9o+zY7tEc_pQ@mail.gmail.com>
 <4F425711.80102@monstr.eu>
 <CAK=WgbbNJMpndKqgW4SJjE=H-BqT7yVsB+F-kEfJWmW+ikJM+A@mail.gmail.com>
 <4F44DB23.4010303@monstr.eu>
 <CAK=Wgbaa9rv1pg19sWYFVX_Dvt0J0AzbRtKhPVnhP6WGdMeT9A@mail.gmail.com>
 <4F562B9E.7060302@monstr.eu>
Message-ID: <CAK=WgbbZwuqmjvY13M83CPsUFv0+DXxCHvnL5S3WpmDW_Qco3A@mail.gmail.com>

Hi Michal,

On Tue, Mar 6, 2012 at 5:22 PM, Michal Simek <monstr at monstr.eu> wrote:
> ? ? ? 3) CGT TMS470: 4.9.0
> ? ? ? ? ?Public Links:-
> ? ? ? ? ? ?TMS470 Compiler is not available for free publicly. Please
> contact your TI representative.

I think you need those tools and can't build the image without them
(Mark/Suman/Fernando, PCMIIW).

Btw I was also told that it will soon be possible to build the
firmware with gcc. Mark will know more details about this.

Thanks,
Ohad.


From jason at lakedaemon.net  Tue Mar  6 11:29:47 2012
From: jason at lakedaemon.net (Jason)
Date: Tue, 6 Mar 2012 11:29:47 -0500
Subject: revert merge commit de68f28 in for-next?
In-Reply-To: <201203061604.53412.arnd@arndb.de>
References: <20120306144415.GR5050@titan.lakedaemon.net>
 <201203061604.53412.arnd@arndb.de>
Message-ID: <20120306162947.GT5050@titan.lakedaemon.net>

On Tue, Mar 06, 2012 at 04:04:53PM +0000, Arnd Bergmann wrote:
> On Tuesday 06 March 2012, Jason wrote:
> > As much as I'd love to see this go in right now, I don't think it's the
> > correct version (from Mar 2).  This is the merge commit in question:
> > 
> > de68f2847fa759df54e9d8eb0013a0f8ea959c22
> > 
> > It's missing several fixes, #ifdef CONFIG_OF around struct of_device_id,
> > marvell -> mrvl in compatible properties, etc.
> > 
> > Would you like me to submit a new pull request, or base my fixes off of
> > this and submit new patches?
> > 
> > Thanks and sorry for the confusion,
> > 
> 
> I've marked that branch a 'staging/' branch, which means that it's not
> intended for being sent to Linus. Please send a replacement branch instead.
> 
> Once something is merged into a next/* branch instead of staging/*, you
> should send further patches on top.

Thanks for the clarification, I was fired up and crapping my pants at
the same time.

I'll put together a new pull request.

thx,

Jason.
> 
> 	Arnd


From paul.gortmaker at windriver.com  Tue Mar  6 11:31:42 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Tue,  6 Mar 2012 11:31:42 -0500
Subject: [PATCH] ARM: fix lcd power build failure in collie_defconfig
Message-ID: <1331051502-22361-1-git-send-email-paul.gortmaker@windriver.com>

Commit 086ada54abaa4316e8603f02410fe8ebc9ba2de1 (linux-next)

  "FB: sa1100: remove global sa1100fb_.*_power function pointers"

got rid of all instances but one in locomolcd.c -- which was
conditional on CONFIG_SA1100_COLLIE.  The associated .power
field which replaces the global is populated in mach-sa1100/collie.c
so move the assignment there, but make it conditional on the
locomolcd support, so use CONFIG_BACKLIGHT_LOCOMO in that file.

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>

diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 48885b7..c7f418b 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -313,6 +313,10 @@ static struct sa1100fb_mach_info collie_lcd_info = {
 
 	.lccr0		= LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
 	.lccr3		= LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
+
+#ifdef CONFIG_BACKLIGHT_LOCOMO
+	.lcd_power	= locomolcd_power
+#endif
 };
 
 static void __init collie_init(void)
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
index 52acda7..f33679d 100644
--- a/arch/arm/mach-sa1100/include/mach/collie.h
+++ b/arch/arm/mach-sa1100/include/mach/collie.h
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-sa1100/include/mach/collie.h
  *
- * This file contains the hardware specific definitions for Assabet
+ * This file contains the hardware specific definitions for Collie
  * Only include this file from SA1100-specific files.
  *
  * ChangeLog:
@@ -13,6 +13,7 @@
 #ifndef __ASM_ARCH_COLLIE_H
 #define __ASM_ARCH_COLLIE_H
 
+extern void locomolcd_power(int on);
 
 #define COLLIE_SCOOP_GPIO_BASE	(GPIO_MAX + 1)
 #define COLLIE_GPIO_CHARGE_ON	(COLLIE_SCOOP_GPIO_BASE + 0)
diff --git a/drivers/video/backlight/locomolcd.c b/drivers/video/backlight/locomolcd.c
index be20b5c..3a6d541 100644
--- a/drivers/video/backlight/locomolcd.c
+++ b/drivers/video/backlight/locomolcd.c
@@ -229,14 +229,7 @@ static struct locomo_driver poodle_lcd_driver = {
 
 static int __init locomolcd_init(void)
 {
-	int ret = locomo_driver_register(&poodle_lcd_driver);
-	if (ret)
-		return ret;
-
-#ifdef CONFIG_SA1100_COLLIE
-	sa1100fb_lcd_power = locomolcd_power;
-#endif
-	return 0;
+	return locomo_driver_register(&poodle_lcd_driver);
 }
 
 static void __exit locomolcd_exit(void)
-- 
1.7.9.1



From arnd at arndb.de  Tue Mar  6 11:37:44 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 16:37:44 +0000
Subject: [GIT PULL] arm-soc bug fixes
Message-ID: <201203061637.45150.arnd@arndb.de>

Hi Linus,

Here are all the fixes I got after sending the last pull request.
These fix mostly regressions on exynos, at91, pxa and ep93xx.
They are available in the 'fixes' branch or the 'fixes-3.3-rc7'
tag.

	Arnd

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

  Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:
  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/fixes-3.3-rc7

Arnd Bergmann (3):
      Merge branch 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixes
      Merge branch 'v3.3-samsung-fixes-4' of git://git.kernel.org/.../kgene/linux-samsung into fixes
      Merge branch 'fixes' of git://github.com/hzhuang1/linux into fixes

Bartlomiej Zolnierkiewicz (1):
      ARM: EXYNOS: fix touchscreen IRQ setup on Universal C210 board

Gusakov Andrey (1):
      ARM: S3C24XX: DMA resume regression fix

H Hartley Sweeten (1):
      ARM: ep93xx: convert vision_ep9307 to MULTI_IRQ_HANDLER

Haojian Zhuang (3):
      ARM: pxa: add dummy clock for pxa25x and pxa27x
      ARM: pxa: remove duplicated registeration on pxa-gpio
      ARM: pxa: fix invalid mfp pin issue

Heiko Stuebner (1):
      ARM: S3C24XX: Fix restart on S3C2442

Joonyoung Shim (1):
      ARM: SAMSUNG: Fix memory size for hsotg

Nicolas Ferre (2):
      ARM: at91/dma: remove platform data from DMA controller
      ARM: at91/dma: DMA controller registering with DT support

 arch/arm/mach-at91/at91sam9g45_devices.c   |   19 ++++++++++---------
 arch/arm/mach-at91/at91sam9rl_devices.c    |    8 +-------
 arch/arm/mach-ep93xx/vision_ep9307.c       |    2 ++
 arch/arm/mach-exynos/mach-universal_c210.c |    2 ++
 arch/arm/mach-pxa/generic.h                |    1 -
 arch/arm/mach-pxa/mfp-pxa2xx.c             |    7 +++++++
 arch/arm/mach-pxa/pxa25x.c                 |    2 +-
 arch/arm/mach-pxa/pxa27x.c                 |    2 +-
 arch/arm/mach-pxa/pxa3xx.c                 |    1 -
 arch/arm/mach-pxa/pxa95x.c                 |    1 -
 arch/arm/mach-s3c2440/common.h             |    2 +-
 arch/arm/mach-s3c2440/mach-anubis.c        |    2 +-
 arch/arm/mach-s3c2440/mach-at2440evb.c     |    2 +-
 arch/arm/mach-s3c2440/mach-gta02.c         |    2 +-
 arch/arm/mach-s3c2440/mach-mini2440.c      |    2 +-
 arch/arm/mach-s3c2440/mach-nexcoder.c      |    2 +-
 arch/arm/mach-s3c2440/mach-osiris.c        |    2 +-
 arch/arm/mach-s3c2440/mach-rx1950.c        |    2 +-
 arch/arm/mach-s3c2440/mach-rx3715.c        |    2 +-
 arch/arm/mach-s3c2440/mach-smdk2440.c      |    2 +-
 arch/arm/mach-s3c2440/s3c2440.c            |   13 -------------
 arch/arm/mach-s3c2440/s3c244x.c            |   11 +++++++++++
 arch/arm/plat-s3c24xx/dma.c                |    2 +-
 arch/arm/plat-samsung/devs.c               |    2 +-
 24 files changed, 47 insertions(+), 46 deletions(-)


From nico at fluxnic.net  Tue Mar  6 11:51:07 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 06 Mar 2012 11:51:07 -0500 (EST)
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <201203061412.00073.arnd@arndb.de>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201202281945.39419.arnd@arndb.de>
 <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
 <201203061412.00073.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1203061146210.31242@xanadu.home>

On Tue, 6 Mar 2012, Arnd Bergmann wrote:

> On Tuesday 06 March 2012, Nicolas Pitre wrote:
> > FYI, here's a snippet of a conversation I just had with Lennert on IRC 
> > today:
> > 
> > 13:05 < nico> do you still care about ixp2000?
> > 13:22 < lennert> not really, no
> > 13:58 < nico> do you think we could remove it from the kernel tree?
> > 14:01 < lennert> go for it, and remove ixp23xx too while you're at it
> 
> Ah, good to know that Lennert is actually still alive somewhere.
> 
> And removing ixp2xxx in 3.5 will certainly help us, too. 
> 
> Interestingly, that leaves ixp4xx as the only big-endian ARM platform.
> I believe that ixp4xx is still being actively used quite a bit, but does
> that include the big-endian ones? There is no immediate reason why we
> would want to drop support for big-endian, but if it's not used at all,
> that would be an interesting cleanup opportunity.

The NSLU2 is (was) a quite popular NAS device and it is used in big 
endian by default.

The BE support isn't getting in the way of anything, so there is no 
reason to remove it, even if it isn't being used much.


Nicolas


From arnd at arndb.de  Tue Mar  6 11:53:10 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 16:53:10 +0000
Subject: [PATCH v4 1/4] ARM: provide runtime hook for ioremap/iounmap
In-Reply-To: <1331006580-3579-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331006580-3579-1-git-send-email-robherring2@gmail.com>
Message-ID: <201203061653.11049.arnd@arndb.de>

On Tuesday 06 March 2012, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> We have compile time over-ride of ioremap and iounmap, but an run-time
> override is needed for multi-platform builds. This adds an extra function
> pointer check, but ioremap is not peformance critical. The option for
> compile time selection remains.
> 
> The caller variant is used here to provide correct caller information as
> ARM can only support level 0 for __builtin_return_address.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>

Very nice!

Just one small comment:

> --- a/arch/arm/mm/ioremap.c
> +++ b/arch/arm/mm/ioremap.c
> @@ -306,9 +306,16 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
>  }
>  EXPORT_SYMBOL(__arm_ioremap_pfn);
>  
> +void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *);
> +EXPORT_SYMBOL(arch_ioremap_caller);
> +
>  void __iomem *
>  __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
>  {
> +	if (arch_ioremap_caller)
> +		return arch_ioremap_caller(phys_addr, size, mtype,
> +			__builtin_return_address(0));
> +
>  	return __arm_ioremap_caller(phys_addr, size, mtype,
>  			__builtin_return_address(0));
>  }
> @@ -370,3 +377,12 @@ void __iounmap(volatile void __iomem *io_addr)
>  	vunmap(addr);
>  }
>  EXPORT_SYMBOL(__iounmap);
> +
> +void (*arch_iounmap)(volatile void __iomem *) = __iounmap;
> +EXPORT_SYMBOL(arch_iounmap);
> +
> +void __arm_iounmap(volatile void __iomem *io_addr)
> +{
> +	arch_iounmap(io_addr);
> +}
> +EXPORT_SYMBOL(__arm_iounmap);

The EXPORT_SYMBOL() statements for arch_ioremap_caller and arch_iounmap
seem to be leftover from a previous version of this patch and can be removed
now. Other than that:

Reviewed-by: Arnd Bergmann <arnd at arndb.de>


From will.deacon at arm.com  Tue Mar  6 11:54:00 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue,  6 Mar 2012 16:54:00 +0000
Subject: [PATCH 0/6] Miscellaneous nommu fixes
Message-ID: <1331052846-19144-1-git-send-email-will.deacon@arm.com>

Hello,

This set of patches is a series of fixes for kernels built without
CONFIG_MMU selected. It seems that this isn't a particularly popular
choice amongst users of mainline kernels, but I was feeling brave and
gave it a go.

The first patch is already in the patch system as 7337/1 but is unlikely
to be merged unless it can be shown to work correctly. I tried the latest
Codesourcery / Mentor uclinux GDB but that doesn't appear to issue the
relevant ptrace requests:

http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086219.html

If anybody has a working uclinux environment, it would *make my day* if
they could take GDB for a spin.

The second patch has been picked up by Andrew Morton from the kexec list.

The remaining patches are largely straightforward with the exception of
the CPU suspend changes. I actually managed to test this with a rather
weird and wonderful configuration, although this was using software
models which tend to hide some of the issues you may experience with
real hardware.

All feedback welcome.

Will


Jonathan Austin (1):
  ARM: nommu: Use VECTORS_BASE for vector copying with !MMU

Will Deacon (5):
  ARM: ptrace: fix ptrace_read_user for !CONFIG_MMU platforms
  kexec: crash: don't save swapper_pg_dir for !CONFIG_MMU
    configurations
  ARM: nommu: fix typo in mm/Kconfig
  ARM: suspend: fix CPU suspend code for !CONFIG_MMU configurations
  ARM: mm: truncate memory banks to fit in 4GB space for classic MMU

 arch/arm/kernel/ptrace.c  |    4 ++-
 arch/arm/kernel/setup.c   |   11 ++++++++-
 arch/arm/kernel/suspend.c |   52 ++++++++++++++++++++++++++-------------------
 arch/arm/kernel/traps.c   |    2 +-
 arch/arm/mm/Kconfig       |    2 +-
 arch/arm/mm/proc-v6.S     |    6 ++++-
 arch/arm/mm/proc-v7.S     |   14 +++++++----
 kernel/kexec.c            |    2 +
 8 files changed, 61 insertions(+), 32 deletions(-)

-- 
1.7.4.1



From will.deacon at arm.com  Tue Mar  6 11:54:01 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue,  6 Mar 2012 16:54:01 +0000
Subject: [PATCH 1/6] ARM: ptrace: fix ptrace_read_user for !CONFIG_MMU
 platforms
In-Reply-To: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
References: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
Message-ID: <1331052846-19144-2-git-send-email-will.deacon@arm.com>

Commit 68b7f715 ("nommu: ptrace support") added definitions for
PT_TEXT_ADDR and friends, as well as adding ptrace support for reading
from these magic offsets.

Unfortunately, this has probably never worked, since ptrace_read_user
predicates reading on off < sizeof(struct user), returning -EIO
otherwise.

This patch moves the offset size check until after we have tried to
match it against either a magic value or an offset into pt_regs.

Cc: Paul Brook <paul at codesourcery.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/ptrace.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index ede6443..4fe2d598 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -257,7 +257,7 @@ static int ptrace_read_user(struct task_struct *tsk, unsigned long off,
 {
 	unsigned long tmp;
 
-	if (off & 3 || off >= sizeof(struct user))
+	if (off & 3)
 		return -EIO;
 
 	tmp = 0;
@@ -269,6 +269,8 @@ static int ptrace_read_user(struct task_struct *tsk, unsigned long off,
 		tmp = tsk->mm->end_code;
 	else if (off < sizeof(struct pt_regs))
 		tmp = get_user_reg(tsk, off >> 2);
+	else if (off >= sizeof(struct user))
+		return -EIO;
 
 	return put_user(tmp, ret);
 }
-- 
1.7.4.1



From will.deacon at arm.com  Tue Mar  6 11:54:02 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue,  6 Mar 2012 16:54:02 +0000
Subject: [PATCH 2/6] kexec: crash: don't save swapper_pg_dir for !CONFIG_MMU
 configurations
In-Reply-To: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
References: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
Message-ID: <1331052846-19144-3-git-send-email-will.deacon@arm.com>

nommu platforms don't have very interesting swapper_pg_dir pointers and
usually just #define them to NULL, meaning that we can't include them in
the vmcoreinfo on the kexec crash path.

This patch only saves the swapper_pg_dir if we have an MMU.

Reviewed-by: Simon Horman <horms at verge.net.au>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 kernel/kexec.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/kernel/kexec.c b/kernel/kexec.c
index 7b08867..cb5d13c 100644
--- a/kernel/kexec.c
+++ b/kernel/kexec.c
@@ -1462,7 +1462,9 @@ static int __init crash_save_vmcoreinfo_init(void)
 
 	VMCOREINFO_SYMBOL(init_uts_ns);
 	VMCOREINFO_SYMBOL(node_online_map);
+#ifdef CONFIG_MMU
 	VMCOREINFO_SYMBOL(swapper_pg_dir);
+#endif
 	VMCOREINFO_SYMBOL(_stext);
 	VMCOREINFO_SYMBOL(vmlist);
 
-- 
1.7.4.1



From will.deacon at arm.com  Tue Mar  6 11:54:03 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue,  6 Mar 2012 16:54:03 +0000
Subject: [PATCH 3/6] ARM: nommu: fix typo in mm/Kconfig
In-Reply-To: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
References: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
Message-ID: <1331052846-19144-4-git-send-email-will.deacon@arm.com>

The description for the CPU_HIGH_VECTOR Kconfig option for nommu builds
doesn't make any sense.

This patch fixes up the trivial grammatical error.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/mm/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 7edef91..7c8a7d8 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -723,7 +723,7 @@ config CPU_HIGH_VECTOR
 	bool "Select the High exception vector"
 	help
 	  Say Y here to select high exception vector(0xFFFF0000~).
-	  The exception vector can be vary depending on the platform
+	  The exception vector can vary depending on the platform
 	  design in nommu mode. If your platform needs to select
 	  high exception vector, say Y.
 	  Otherwise or if you are unsure, say N, and the low exception
-- 
1.7.4.1



From will.deacon at arm.com  Tue Mar  6 11:54:06 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue,  6 Mar 2012 16:54:06 +0000
Subject: [PATCH 6/6] ARM: mm: truncate memory banks to fit in 4GB space for
 classic MMU
In-Reply-To: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
References: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
Message-ID: <1331052846-19144-7-git-send-email-will.deacon@arm.com>

If a bank of memory spanning the 4GB boundary is added on a !CONFIG_LPAE
kernel then we will hang early during boot since the memory bank will
have wrapped around to zero.

This patch truncates memory banks for !LPAE configurations when the end
address is not representable in 32 bits.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/setup.c |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index a255c39..aeaa048 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -521,7 +521,16 @@ int __init arm_add_memory(phys_addr_t start, unsigned long size)
 	 */
 	size -= start & ~PAGE_MASK;
 	bank->start = PAGE_ALIGN(start);
-	bank->size  = size & PAGE_MASK;
+
+#ifndef CONFIG_LPAE
+	if (bank->start + size < bank->start) {
+		printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
+			"32-bit physical address space\n", (long long)start);
+		size = ULONG_MAX - bank->start;
+	}
+#endif
+
+	bank->size = size & PAGE_MASK;
 
 	/*
 	 * Check whether this memory region has non-zero size or
-- 
1.7.4.1



From will.deacon at arm.com  Tue Mar  6 11:54:04 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue,  6 Mar 2012 16:54:04 +0000
Subject: [PATCH 4/6] ARM: suspend: fix CPU suspend code for !CONFIG_MMU
 configurations
In-Reply-To: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
References: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
Message-ID: <1331052846-19144-5-git-send-email-will.deacon@arm.com>

The ARM CPU suspend code can be selected even for a !CONFIG_MMU
configuration. The resulting kernel will not compile and, even if it did,
would access undefined co-processor registers when executing.

This patch fixes the v6 and v7 CPU suspend code for the nommu case.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/suspend.c |   52 ++++++++++++++++++++++++++-------------------
 arch/arm/mm/proc-v6.S     |    6 ++++-
 arch/arm/mm/proc-v7.S     |   14 +++++++----
 3 files changed, 44 insertions(+), 28 deletions(-)

diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
index 1794cc3..073601e 100644
--- a/arch/arm/kernel/suspend.c
+++ b/arch/arm/kernel/suspend.c
@@ -10,28 +10,7 @@
 extern int __cpu_suspend(unsigned long, int (*)(unsigned long));
 extern void cpu_resume_mmu(void);
 
-/*
- * This is called by __cpu_suspend() to save the state, and do whatever
- * flushing is required to ensure that when the CPU goes to sleep we have
- * the necessary data available when the caches are not searched.
- */
-void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
-{
-	*save_ptr = virt_to_phys(ptr);
-
-	/* This must correspond to the LDM in cpu_resume() assembly */
-	*ptr++ = virt_to_phys(idmap_pgd);
-	*ptr++ = sp;
-	*ptr++ = virt_to_phys(cpu_do_resume);
-
-	cpu_do_suspend(ptr);
-
-	flush_cache_all();
-	outer_clean_range(*save_ptr, *save_ptr + ptrsz);
-	outer_clean_range(virt_to_phys(save_ptr),
-			  virt_to_phys(save_ptr) + sizeof(*save_ptr));
-}
-
+#ifdef CONFIG_MMU
 /*
  * Hide the first two arguments to __cpu_suspend - these are an implementation
  * detail which platform code shouldn't have to know about.
@@ -58,3 +37,32 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
 
 	return ret;
 }
+#else
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+	return __cpu_suspend(arg, fn);
+}
+#define	idmap_pgd	NULL
+#endif
+
+/*
+ * This is called by __cpu_suspend() to save the state, and do whatever
+ * flushing is required to ensure that when the CPU goes to sleep we have
+ * the necessary data available when the caches are not searched.
+ */
+void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
+{
+	*save_ptr = virt_to_phys(ptr);
+
+	/* This must correspond to the LDM in cpu_resume() assembly */
+	*ptr++ = virt_to_phys(idmap_pgd);
+	*ptr++ = sp;
+	*ptr++ = virt_to_phys(cpu_do_resume);
+
+	cpu_do_suspend(ptr);
+
+	flush_cache_all();
+	outer_clean_range(*save_ptr, *save_ptr + ptrsz);
+	outer_clean_range(virt_to_phys(save_ptr),
+			  virt_to_phys(save_ptr) + sizeof(*save_ptr));
+}
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 5900cd5..2f702fd 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -136,8 +136,10 @@ ENTRY(cpu_v6_set_pte_ext)
 ENTRY(cpu_v6_do_suspend)
 	stmfd	sp!, {r4 - r9, lr}
 	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
+#ifdef CONFIG_MMU
 	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
 	mrc	p15, 0, r6, c2, c0, 1	@ Translation table base 1
+#endif
 	mrc	p15, 0, r7, c1, c0, 1	@ auxiliary control register
 	mrc	p15, 0, r8, c1, c0, 2	@ co-processor access control
 	mrc	p15, 0, r9, c1, c0, 0	@ control register
@@ -154,14 +156,16 @@ ENTRY(cpu_v6_do_resume)
 	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
 	ldmia	r0, {r4 - r9}
 	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
+#ifdef CONFIG_MMU
 	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
 	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
 	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
 	mcr	p15, 0, r1, c2, c0, 0	@ Translation table base 0
 	mcr	p15, 0, r6, c2, c0, 1	@ Translation table base 1
+	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
+#endif
 	mcr	p15, 0, r7, c1, c0, 1	@ auxiliary control register
 	mcr	p15, 0, r8, c1, c0, 2	@ co-processor access control
-	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
 	mcr	p15, 0, ip, c7, c5, 4	@ ISB
 	mov	r0, r9			@ control register
 	b	cpu_resume_mmu
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 0404ccb..5903ceb 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -98,9 +98,11 @@ ENTRY(cpu_v7_do_suspend)
 	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
 	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
 	stmia	r0!, {r4 - r5}
+#ifdef CONFIG_MMU
 	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
 	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
 	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
+#endif
 	mrc	p15, 0, r8, c1, c0, 0	@ Control register
 	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
 	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
@@ -110,13 +112,14 @@ ENDPROC(cpu_v7_do_suspend)
 
 ENTRY(cpu_v7_do_resume)
 	mov	ip, #0
-	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
 	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
 	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
 	ldmia	r0!, {r4 - r5}
 	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
 	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
 	ldmia	r0, {r6 - r11}
+#ifdef CONFIG_MMU
+	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
 	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
 #ifndef CONFIG_ARM_LPAE
 	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
@@ -125,14 +128,15 @@ ENTRY(cpu_v7_do_resume)
 	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
 	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
 	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
-	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
-	teq	r4, r9			@ Is it already set?
-	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
-	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
 	ldr	r4, =PRRR		@ PRRR
 	ldr	r5, =NMRR		@ NMRR
 	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
 	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
+#endif	/* CONFIG_MMU */
+	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
+	teq	r4, r9			@ Is it already set?
+	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
+	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
 	isb
 	dsb
 	mov	r0, r8			@ control register
-- 
1.7.4.1



From will.deacon at arm.com  Tue Mar  6 11:54:05 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue,  6 Mar 2012 16:54:05 +0000
Subject: [PATCH 5/6] ARM: nommu: Use VECTORS_BASE for vector copying with !MMU
In-Reply-To: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
References: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
Message-ID: <1331052846-19144-6-git-send-email-will.deacon@arm.com>

From: Jonathan Austin <jonathan.austin at arm.com>

When compiling with !CONFIG_MMU the vectors_page pointer does not get
initialised. In the high vectors case, this results in copying to the
wrong address (0x0) and hence a failure to boot.

This patch instead uses CONFIG_VECTORS_BASE as the destination address
when !CONFIG_MMU.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/kernel/traps.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index f84dfe6..f1ab393 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -786,7 +786,7 @@ static void __init kuser_get_tls_init(unsigned long vectors)
 
 void __init early_trap_init(void)
 {
-#if defined(CONFIG_CPU_USE_DOMAINS)
+#if defined(CONFIG_CPU_USE_DOMAINS) || !defined(CONFIG_MMU)
 	unsigned long vectors = CONFIG_VECTORS_BASE;
 #else
 	unsigned long vectors = (unsigned long)vectors_page;
-- 
1.7.4.1



From broonie at opensource.wolfsonmicro.com  Tue Mar  6 11:54:27 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 16:54:27 +0000
Subject: [alsa-devel] [PATCH 15/20] ASoC: fsl: make fsl_ssi driver
 compilable on ARM/IMX
In-Reply-To: <20120306135259.GJ17370@n2100.arm.linux.org.uk>
References: <20120305000411.GL7363@n2100.arm.linux.org.uk>
 <4F54053F.9070502@freescale.com>
 <20120305002635.GA23798@opensource.wolfsonmicro.com>
 <20120306104015.GF17370@n2100.arm.linux.org.uk>
 <20120306120646.GH19635@opensource.wolfsonmicro.com>
 <20120306122516.GH17370@n2100.arm.linux.org.uk>
 <20120306123322.GP19635@opensource.wolfsonmicro.com>
 <s5h4nu17tdn.wl%tiwai@suse.de>
 <20120306133818.GV19635@opensource.wolfsonmicro.com>
 <20120306135259.GJ17370@n2100.arm.linux.org.uk>
Message-ID: <20120306165427.GY19635@opensource.wolfsonmicro.com>

On Tue, Mar 06, 2012 at 01:52:59PM +0000, Russell King - ARM Linux wrote:

> Stop using the term "uniprocessor assmptions".

> Thinking that something is safe because you're running on a uniprocessor
> system is total bollocks at every level.

Feh, it's hardly a new term - it dates back to when those crazy x86 kids
first got their hands on this fancy new SMP stuff and started running
into issues.  It's coming from the fact that that was the first case to
change the assumptions that had previously existed so things broke on
SMP systems.

> What you mean is "single threaded assumptions".  Please use this term
> instead - it's what you actually mean.

If we're concerned about the name I'd not mention threads as that's
often confusing for people in these contexts as it's not always obvious
to everyone if or how interrupts count.  "Single execution context" or
even "old school Linux" are probably less ambiguous.
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From swarren at wwwdotorg.org  Tue Mar  6 11:55:12 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 06 Mar 2012 09:55:12 -0700
Subject: [PATCH/RFC 1/2] arm/tegra: fix harmony pinmux for PCIe
In-Reply-To: <1331023544-6439-2-git-send-email-mad_soft@inbox.ru>
References: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>
 <1331023544-6439-2-git-send-email-mad_soft@inbox.ru>
Message-ID: <4F564170.7000209@wwwdotorg.org>

On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> Commit 6e96aca397 (arm/tegra: Harmony PCIe: Don't touch pinmux)
> removed runtime tri-state toggling for PCIe related pinmux groups,
> but it seems that the fact that all of them are tri-state by default
> has been overlooked. Change defaults for these groups to TEGRA_TRI_NORMAL.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>

Crap, why didn't I check that? Anyway,

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From swarren at wwwdotorg.org  Tue Mar  6 11:58:50 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 06 Mar 2012 09:58:50 -0700
Subject: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock detection
 loop
In-Reply-To: <1331023544-6439-3-git-send-email-mad_soft@inbox.ru>
References: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>
 <1331023544-6439-3-git-send-email-mad_soft@inbox.ru>
Message-ID: <4F56424A.3020305@wwwdotorg.org>

On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (as PCIe code is not modular).
> 
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>

That seems reasonable. So once the mdelay discussion is resolved,

Acked-by: Stephen Warren <swarren at wwwdotorg.org>

Any idea why the PLL doesn't lock sometimes?


From swarren at wwwdotorg.org  Tue Mar  6 12:01:11 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 06 Mar 2012 10:01:11 -0700
Subject: [PATCH V2 3/3] gpio: tegra: Hide tegra_gpio_enable/disable()
In-Reply-To: <CACRpkdaZ8EBBwGis4Odh1EZS=waB0nCSZ-mtUHx48ywE81T5Ng@mail.gmail.com>
References: <1330993336-9538-1-git-send-email-swarren@nvidia.com>	<1330993336-9538-3-git-send-email-swarren@nvidia.com>
 <CACRpkdaZ8EBBwGis4Odh1EZS=waB0nCSZ-mtUHx48ywE81T5Ng@mail.gmail.com>
Message-ID: <4F5642D7.4090800@wwwdotorg.org>

On 03/06/2012 03:08 AM, Linus Walleij wrote:
> On Tue, Mar 6, 2012 at 1:22 AM, Stephen Warren <swarren at nvidia.com> wrote:
> 
>> Recent pinctrl discussions concluded that gpiolib APIs should in fact do
>> whatever is required to mux a GPIO onto pins, by calling pinctrl APIs if
>> required. This change implements this for the Tegra GPIO driver, and removes
>> calls to the Tegra-specific APIs from drivers and board files.
...
>> This patch should probably be taken
>> through the Tegra tree. Once patch 2 is in pinctrl, and considered stable,
>> I can just use that as a dependency for the branch containing this Tegra
>> patch. I assume that this series will go into 3.5 not 3.4, but I'm willing
>> to be surprised:-)
> 
> Should be possible if my pinctrl-tegra-for-next-diet branch is considered
> stable and could be pulled into the Tegra tree for further augmenting
> by this and other patches!
> 
> But I guess you'd need to merge some stable development base
> for the rest of the pinctrl stuff as well, shall I freeze the for-next
> branch with tegra diet stuff merged on top now? I can promise
> to just add new patches on top of that if it helps you.
> 
> Is Olof the one to ask?

For 3.4 yes Olof, but since this is probably going into 3.5, it's me!

At this point, I expect picking up a stable commit from pinctrl's
for-next branch would be the easiest for 3.5. Probably the same is true
for 3.4 too, since "everything" is in pinctrl's for-next now.


From sshtylyov at ru.mvista.com  Tue Mar  6 13:06:40 2012
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Tue, 06 Mar 2012 21:06:40 +0300
Subject: [PATCH 6/6] ARM: mm: truncate memory banks to fit in 4GB space
 for classic MMU
In-Reply-To: <1331052846-19144-7-git-send-email-will.deacon@arm.com>
References: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
 <1331052846-19144-7-git-send-email-will.deacon@arm.com>
Message-ID: <4F565230.6030800@ru.mvista.com>

Hello.

On 03/06/2012 07:54 PM, Will Deacon wrote:

> If a bank of memory spanning the 4GB boundary is added on a !CONFIG_LPAE
> kernel then we will hang early during boot since the memory bank will
> have wrapped around to zero.

> This patch truncates memory banks for !LPAE configurations when the end
> address is not representable in 32 bits.

> Signed-off-by: Will Deacon<will.deacon at arm.com>
> ---
>   arch/arm/kernel/setup.c |   11 ++++++++++-
>   1 files changed, 10 insertions(+), 1 deletions(-)

> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index a255c39..aeaa048 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -521,7 +521,16 @@ int __init arm_add_memory(phys_addr_t start, unsigned long size)
>   	 */
>   	size -= start&  ~PAGE_MASK;
>   	bank->start = PAGE_ALIGN(start);
> -	bank->size  = size&  PAGE_MASK;
> +
> +#ifndef CONFIG_LPAE
> +	if (bank->start + size<  bank->start) {
> +		printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
> +			"32-bit physical address space\n", (long long)start);
> +		size = ULONG_MAX - bank->start;

    I think you forgot to add one here.

WBR, Sergei


From arnd at arndb.de  Tue Mar  6 12:10:53 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 17:10:53 +0000
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <alpine.LFD.2.02.1203061146210.31242@xanadu.home>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201203061412.00073.arnd@arndb.de>
 <alpine.LFD.2.02.1203061146210.31242@xanadu.home>
Message-ID: <201203061710.54171.arnd@arndb.de>

On Tuesday 06 March 2012, Nicolas Pitre wrote:
> The NSLU2 is (was) a quite popular NAS device and it is used in big 
> endian by default.
> 
> The BE support isn't getting in the way of anything, so there is no 
> reason to remove it, even if it isn't being used much.

Ok, that's what I thought, just making sure. If it was completely
dead code, things would be different.

	Arnd


From nico at fluxnic.net  Tue Mar  6 12:18:53 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 06 Mar 2012 12:18:53 -0500 (EST)
Subject: [PATCH v4 1/4] ARM: provide runtime hook for ioremap/iounmap
In-Reply-To: <1331006580-3579-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331006580-3579-1-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203061210430.31242@xanadu.home>

On Mon, 5 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> We have compile time over-ride of ioremap and iounmap, but an run-time
> override is needed for multi-platform builds. This adds an extra function
> pointer check, but ioremap is not peformance critical. The option for
> compile time selection remains.
> 
> The caller variant is used here to provide correct caller information as
> ARM can only support level 0 for __builtin_return_address.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> ---
[...]
> index 80632e8..c37c67a 100644
> --- a/arch/arm/mm/ioremap.c
> +++ b/arch/arm/mm/ioremap.c
> @@ -306,9 +306,16 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
>  }
>  EXPORT_SYMBOL(__arm_ioremap_pfn);
>  
> +void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *);
> +EXPORT_SYMBOL(arch_ioremap_caller);

We don't want modules to mess with this, so the export can go.

>  void __iomem *
>  __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
>  {
> +	if (arch_ioremap_caller)
> +		return arch_ioremap_caller(phys_addr, size, mtype,
> +			__builtin_return_address(0));
> +
>  	return __arm_ioremap_caller(phys_addr, size, mtype,
>  			__builtin_return_address(0));

Why not initializing arch_ioremap_caller with __arm_ioremap_caller like 
the iounmap case?  That would remove the need for a runtime test.

> @@ -370,3 +377,12 @@ void __iounmap(volatile void __iomem *io_addr)
>  	vunmap(addr);
>  }
>  EXPORT_SYMBOL(__iounmap);
> +
> +void (*arch_iounmap)(volatile void __iomem *) = __iounmap;
> +EXPORT_SYMBOL(arch_iounmap);

Same comment as above about the export.

> +void __arm_iounmap(volatile void __iomem *io_addr)
> +{
> +	arch_iounmap(io_addr);
> +}
> +EXPORT_SYMBOL(__arm_iounmap);
> -- 
> 1.7.5.4
> 


From nico at fluxnic.net  Tue Mar  6 12:20:13 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 06 Mar 2012 12:20:13 -0500 (EST)
Subject: [PATCH v3 02/30] ARM: provide runtime hook for ioremap/iounmap
In-Reply-To: <4F558D89.7030905@gmail.com>
References: <1330658022-14559-1-git-send-email-robherring2@gmail.com>
 <1330658022-14559-3-git-send-email-robherring2@gmail.com>
 <alpine.LFD.2.02.1203051415150.31242@xanadu.home>
 <201203052013.26688.arnd@arndb.de>
 <alpine.LFD.2.02.1203051545200.31242@xanadu.home> <4F558D89.7030905@gmail.com>
Message-ID: <alpine.LFD.2.02.1203061219220.31242@xanadu.home>

On Mon, 5 Mar 2012, Rob Herring wrote:

> There's not much point in converting ixp4xx and ebsa110 to runtime hooks
> as they still have other io.h needs.

I think there is.  Uniformity is highly valuable.


Nicolas


From swarren at wwwdotorg.org  Tue Mar  6 12:21:40 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 06 Mar 2012 10:21:40 -0700
Subject: obtaining a regulator from a phandle
In-Reply-To: <20120306113947.GA22769@avionic-0098.mockup.avionic-design.de>
References: <20120305152157.GA12927@avionic-0098.adnet.avionic-design.de>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861C09@HQMAIL01.nvidia.com>
 <20120305165514.GA21298@avionic-0098.adnet.avionic-design.de>
 <20120306113947.GA22769@avionic-0098.mockup.avionic-design.de>
Message-ID: <4F5647A4.2060205@wwwdotorg.org>

On 03/06/2012 04:39 AM, Thierry Reding wrote:
...
> And this is precisely where things get ugly. Now there is a dependency
> problem between the fixed regulator and the PMU which provides the GPIO. Both
> the PMU and the fixed regulator are setup via subsys_initcall(), and the
> regulator beats the PMU, resulting in the fixed regulator being unable to get
> the GPIO because it hasn't been setup yet. So I remembered Grant's deferred
> probing patch from yesterday and thought I'd try it out. This worked great,
> and the fixed regulator was properly set up after all other devices had been
> probed.

It's great that worked out.

> The PCIe driver now also needs deferred probing until the fixed regulator is
> present, which also works as expected. But then the problems start. Since now
> we're so far into the boot process that all __init{,data} is gone, therefore
> pci_common_init() is no longer present, resulting in an ugly crash.
> 
> So the only way I see out of this is patch up everything so that PCI
> initialization can actually be done after init memory is freed. This would
> have the added benefit that the driver could actually be built as a module.
> 
> Does anyone see another (easier) way out of this?

To me, that sounds like exactly how to solve it. You can probably mark
the code __devinit rather than just removing all the decorations
completely. You probably want to run this by the core ARM maintainers
though; I CC'd Russell and the ARM mailing list for comment.


From jason at lakedaemon.net  Tue Mar  6 12:23:42 2012
From: jason at lakedaemon.net (Jason)
Date: Tue, 6 Mar 2012 12:23:42 -0500
Subject: [RFC 00/14] Generic clk for Orion platforms.
In-Reply-To: <20120306161743.GI24858@lunn.ch>
References: <1331015471-28872-1-git-send-email-andrew@lunn.ch>
 <20120306155840.GS5050@titan.lakedaemon.net>
 <20120306161743.GI24858@lunn.ch>
Message-ID: <20120306172341.GU5050@titan.lakedaemon.net>

On Tue, Mar 06, 2012 at 05:17:43PM +0100, Andrew Lunn wrote:
> On Tue, Mar 06, 2012 at 10:58:40AM -0500, Jason wrote:
> > On Tue, Mar 06, 2012 at 07:30:56AM +0100, Andrew Lunn wrote:
> > > This patch set starts the process of changing Orion based platforms to
> > > use the generic clk framework. The first patch fixes compile problems
> > > with the framework, and is expected to be dropped once fixed upstream.
> > > Then clks are added. This is a fixed rate clk for tclk and for
> > > kirkwood, most of the gated clocks also get a clk. The following
> > > patches then modified the drivers to make use of these clocks,
> > > getting, prepareing, enabling at probe time, and disableing,
> > > unprepareing, and putting at remove time. Rather than pass the clock
> > > frequency as platform_data, the driver now uses clk_get_rate(). This
> > > results in some platform_data structures becoming redundant, and so
> > > are removed.
> > 
> > Awesome, thanks for posting!
> > 
> > > TODO:
> > > 
> > >  0) Cleanup the white space changes, and hunks in the wrong patches.
> > 
> > It would be helpful to break out code cleanup as well.  eg spi_clock_fix
> > removal, sound platform data removal, and anything else I didn't see on
> > initial read through.
> 
> I could move these out, but they actually help you. It means there is
> less for you to add DT support for. If they are left in, you need to
> add a DT property for spi_clock_fix, etc.

Oops, #4 and #8 are what I wanted to pull in separately.  I could've
sworn I saw something else that went in the same catagory as those
two...

> > >  1) PCIe needs adopting to use clks.
> > >  2) Strip out all references to kirkwood_clk_ctrl
> > >  3) Find a solution for turning off unused clks - Probably needs
> > >     framework support, which Mike has already suggested.
> > 
> > I'm assuming the driver(s) will increment a reference, so when it
> > reaches zero, the framework would call a clk_gate hook.
> 
> You missed an important point. No driver has claimed these, but u-boot
> has turned them on.

This sounds like a bug in u-boot.

> So we want linux to turn off all clocks for which
> there is no driver using them, in order to save power.
> kirkwood_clk_ctrl is dual purpose. It turns on needed clocks, but it
> also turns off unneeded clocks.

This is creating a lot of complexity where the real answer seems to be
to get u-boot to shutoff all peripheral clocks before handing over
control to linux.

Until that happens, could we walk across kirkwood_clks[] in
kirkwood_clock_gate() to determine what is in use?  eg:

#########
curr = readl(CLOCK_GATING_CTRL);
...
used = CGC_DUNIT | CGC_RESERVED;

for (i = 0; i < ARRAY_SIZE(kirkwood_clks); i++) {
	if (kirkwood_clks[i]->enable_count)
		used |= kirkwood_clks[i]->/*PFM*/->mask;
}

/* disable anything in curr, but not in used */
if (CGC_SATA0 & (curr & ~used)) {
	/* disable sata0 logic */
}

...
#########

This would handle both fdt and non-fdt use cases.

thx,

Jason.


From swarren at wwwdotorg.org  Tue Mar  6 12:28:26 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 06 Mar 2012 10:28:26 -0700
Subject: [PATCH] pinctrl: include machine header to core.h
In-Reply-To: <1331038557-1398-1-git-send-email-linus.walleij@stericsson.com>
References: <1331038557-1398-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <4F56493A.1090700@wwwdotorg.org>

On 03/06/2012 05:55 AM, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> struct pinctrl_setting contains an enum pinctrl_map_type
> field, so we need to include machine.h. Also fix kerneldoc
> to indicate that the pinctrl_setting is about both muxing
> and other config.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From richardcochran at gmail.com  Tue Mar  6 12:38:44 2012
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 6 Mar 2012 18:38:44 +0100
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <201203061710.54171.arnd@arndb.de>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201203061412.00073.arnd@arndb.de>
 <alpine.LFD.2.02.1203061146210.31242@xanadu.home>
 <201203061710.54171.arnd@arndb.de>
Message-ID: <20120306173844.GC3005@netboy.at.omicron.at>

On Tue, Mar 06, 2012 at 05:10:53PM +0000, Arnd Bergmann wrote:
> On Tuesday 06 March 2012, Nicolas Pitre wrote:
> > The NSLU2 is (was) a quite popular NAS device and it is used in big 
> > endian by default.
> > 
> > The BE support isn't getting in the way of anything, so there is no 
> > reason to remove it, even if it isn't being used much.
> 
> Ok, that's what I thought, just making sure. If it was completely
> dead code, things would be different.

Obligatory Monty Python quote:

    "I'm not dead."
    "'Ere, he says he's not dead."
    "Yes he is."

Even though Intel dropped the IXP like a hot potato, people are still
actively using Linux on it, and in big endian mode.

Thanks,
Richard


From sameo at linux.intel.com  Tue Mar  6 12:42:13 2012
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Tue, 6 Mar 2012 18:42:13 +0100
Subject: [PATCH 0/5] MFD: Reverting twl6040 patches going for 3.4
In-Reply-To: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331037316-7375-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120306174213.GY9008@sortiz-mobl>

Hi Peter,

On Tue, Mar 06, 2012 at 02:35:11PM +0200, Peter Ujfalusi wrote:
> Hello Samuel,
> 
> this series reverts the twl6040 related patches aimed for 3.4 merge window from
> MFD for-next branch.
> As we already discussed the relevant patches will be going through audio since
> we have some dependencies going via that route.
I removed all 5 patches from my for-next branch.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From sshtylyov at ru.mvista.com  Tue Mar  6 13:48:36 2012
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Tue, 06 Mar 2012 21:48:36 +0300
Subject: [PATCH] pinctrl: include machine header to core.h
In-Reply-To: <1331038557-1398-1-git-send-email-linus.walleij@stericsson.com>
References: <1331038557-1398-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <4F565C04.1030202@ru.mvista.com>

Hello.

On 03/06/2012 03:55 PM, Linus Walleij wrote:

> From: Linus Walleij<linus.walleij at linaro.org>

> struct pinctrl_setting contains an enum pinctrl_map_type
> field, so we need to include machine.h. Also fix kerneldoc
> to indicate that the pinctrl_setting is about both muxing
> and other config.

    I don't see where you touch kernel-doc...

> Signed-off-by: Linus Walleij<linus.walleij at linaro.org>
> ---
>   drivers/pinctrl/core.h |    1 +
>   1 files changed, 1 insertions(+), 0 deletions(-)

> diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
> index 5b3ff13..42fb0ea 100644
> --- a/drivers/pinctrl/core.h
> +++ b/drivers/pinctrl/core.h
> @@ -12,6 +12,7 @@
>   #include<linux/mutex.h>
>   #include<linux/radix-tree.h>
>   #include<linux/pinctrl/pinconf.h>
> +#include<linux/pinctrl/machine.h>
>
>   struct pinctrl_gpio_range;

WBR, Sergei


From andrew at lunn.ch  Tue Mar  6 12:53:33 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Tue, 6 Mar 2012 18:53:33 +0100
Subject: [RFC 00/14] Generic clk for Orion platforms.
In-Reply-To: <20120306172341.GU5050@titan.lakedaemon.net>
References: <1331015471-28872-1-git-send-email-andrew@lunn.ch>
 <20120306155840.GS5050@titan.lakedaemon.net>
 <20120306161743.GI24858@lunn.ch>
 <20120306172341.GU5050@titan.lakedaemon.net>
Message-ID: <20120306175333.GA16608@lunn.ch>

> > You missed an important point. No driver has claimed these, but u-boot
> > has turned them on.
> 
> This sounds like a bug in u-boot.

Is it? Even if it is, we have to live with it. Otherwise we introduce
a regression, which is a big no-no. Also, how many users know how to
upgrade u-boot? I don't have the necessary JTAG setup for my boxes, so
i'm not going to risk bricking them by trying to upgrade u-boot.

> Until that happens, could we walk across kirkwood_clks[] in
> kirkwood_clock_gate() to determine what is in use?  eg:
> 
> #########
> curr = readl(CLOCK_GATING_CTRL);
> ...
> used = CGC_DUNIT | CGC_RESERVED;
> 
> for (i = 0; i < ARRAY_SIZE(kirkwood_clks); i++) {
> 	if (kirkwood_clks[i]->enable_count)
> 		used |= kirkwood_clks[i]->/*PFM*/->mask;
> }
> 
> /* disable anything in curr, but not in used */
> if (CGC_SATA0 & (curr & ~used)) {
> 	/* disable sata0 logic */
> }
> 
> ...
> #########

NO! clk is opaque. You should not be accessing members inside it. The
clk struct members are not even declared when using the normal include
files.

Probably the short term solution is to simply add a deliberate
regression, and not turn them off. Then help Mike implement generic
code to handle this. We probably have three months to do this, since i
doubt the clock code is going to be part of the next merge.

      Andrew


From will.deacon at arm.com  Tue Mar  6 12:58:53 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 6 Mar 2012 17:58:53 +0000
Subject: [PATCH 6/6] ARM: mm: truncate memory banks to fit in 4GB space
 for classic MMU
In-Reply-To: <4F565230.6030800@ru.mvista.com>
References: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
 <1331052846-19144-7-git-send-email-will.deacon@arm.com>
 <4F565230.6030800@ru.mvista.com>
Message-ID: <20120306175853.GB17518@mudshark.cambridge.arm.com>

On Tue, Mar 06, 2012 at 06:06:40PM +0000, Sergei Shtylyov wrote:
> Hello.

Hi Sergei,

> On 03/06/2012 07:54 PM, Will Deacon wrote:
> 
> > If a bank of memory spanning the 4GB boundary is added on a !CONFIG_LPAE
> > kernel then we will hang early during boot since the memory bank will
> > have wrapped around to zero.
> 
> > This patch truncates memory banks for !LPAE configurations when the end
> > address is not representable in 32 bits.
> 
> > Signed-off-by: Will Deacon<will.deacon at arm.com>
> > ---
> >   arch/arm/kernel/setup.c |   11 ++++++++++-
> >   1 files changed, 10 insertions(+), 1 deletions(-)
> 
> > diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> > index a255c39..aeaa048 100644
> > --- a/arch/arm/kernel/setup.c
> > +++ b/arch/arm/kernel/setup.c
> > @@ -521,7 +521,16 @@ int __init arm_add_memory(phys_addr_t start, unsigned long size)
> >   	 */
> >   	size -= start&  ~PAGE_MASK;
> >   	bank->start = PAGE_ALIGN(start);
> > -	bank->size  = size&  PAGE_MASK;
> > +
> > +#ifndef CONFIG_LPAE
> > +	if (bank->start + size<  bank->start) {
> > +		printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
> > +			"32-bit physical address space\n", (long long)start);
> > +		size = ULONG_MAX - bank->start;
> 
>     I think you forgot to add one here.

No, I deliberately omit the last page because otherwise we end up with the
end address of the bank being calculated as 0, which leads to boot failure.

Will


From ohad at wizery.com  Tue Mar  6 13:09:38 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Tue, 6 Mar 2012 20:09:38 +0200
Subject: [GIT PULL] fixing and cleaning up rpmsg/remoteproc for 3.4
Message-ID: <CAK=WgbYsZUzTos_sXd+ZayKfPc=sxL7v0Q_==bTMh-_4XiMWiw@mail.gmail.com>

Hi Arnd,

Please pull:

git://git.kernel.org/pub/scm/linux/kernel/git/ohad/remoteproc.git
rpmsg-fixes-and-more-for-3.4

To get a few rpmsg/remoteproc fixes, cleanups and some generalization
work for 3.4.

Again, I should have sent the Kconfig patch earlier in a separate pull
request. Sorry about that.

Thanks!
Ohad.

The following changes since commit e12bc14b88d44e5c1456dccb59ff58103f6c6edc:

  remoteproc: s/big switch/lookup table/ (2012-02-22 18:28:49 +0200)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/ohad/remoteproc.git
rpmsg-fixes-and-more-for-3.4

for you to fetch changes up to 1e3e2c7c46b2e6e90f3a26ba9be6326c00ca31e4:

  remoteproc: cleanup resource table parsing paths (2012-03-06 19:14:44 +0200)

----------------------------------------------------------------
Fixing and cleaning up several remoteproc and rpmsg issues.

In addition, remoteproc's resource table is converted to a collection
of type-value members, instead of a rigid array of homogeneous structs.

This enables remoteproc to support registration of generic virtio devices,
and not only a single VIRTIO_ID_RPMSG virtio device.

But perhaps more importantly, the resource table overhaul makes it possible
to easily extend it in the future without breaking older images (simply by
defining a new member type, while continuing to support older types).

----------------------------------------------------------------
Mark Asselstine (1):
      rpmsg: fix build warning when dma_addr_t is 64-bit

Ohad Ben-Cohen (12):
      remoteproc: make sure we're parsing a 32bit firmware
      remoteproc/omap: two Kconfig fixes
      rpmsg: fix name service endpoint leak
      rpmsg: validate incoming message length before propagating
      rpmsg: fix published buffer length in rpmsg_recv_done
      remoteproc: resource table overhaul
      remoteproc: remoteproc_rpmsg -> remoteproc_virtio
      remoteproc: safer boot/shutdown order
      remoteproc: remove the single rpmsg vdev limitation
      remoteproc/omap: remove the mbox_callback limitation
      remoteproc: remove the hardcoded vring alignment
      remoteproc: cleanup resource table parsing paths

 Documentation/remoteproc.txt                       |  136 +++---
 drivers/remoteproc/Kconfig                         |    3 +-
 drivers/remoteproc/Makefile                        |    2 +-
 drivers/remoteproc/omap_remoteproc.c               |   11 +-
 drivers/remoteproc/remoteproc_core.c               |  532 ++++++++++++--------
 drivers/remoteproc/remoteproc_internal.h           |    6 +-
 .../{remoteproc_rpmsg.c => remoteproc_virtio.c}    |  162 +++----
 drivers/rpmsg/virtio_rpmsg_bus.c                   |   46 ++-
 include/linux/remoteproc.h                         |  339 ++++++++++---
 9 files changed, 793 insertions(+), 444 deletions(-)
 rename drivers/remoteproc/{remoteproc_rpmsg.c => remoteproc_virtio.c} (65%)


From tony at atomide.com  Tue Mar  6 13:19:01 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 6 Mar 2012 10:19:01 -0800
Subject: [PATCH] ARM: OMAP1: Fix section mismatch for omap1_init_early()
Message-ID: <20120306181901.GS12083@atomide.com>

Fix the following warning:

WARNING: vmlinux.o(.text+0x1286c): Section mismatch in reference
from the function omap1_init_early() to the function .init.text:omap1_clk_init()
The function omap1_init_early() references
the function __init omap1_clk_init().
This is often because omap1_init_early lacks a __init
annotation or the annotation of omap1_clk_init is wrong.

Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -118,7 +118,7 @@ void __init omap16xx_map_io(void)
 /*
  * Common low-level hardware init for omap1.
  */
-void omap1_init_early(void)
+void __init omap1_init_early(void)
 {
 	omap_check_revision();
 


From swarren at wwwdotorg.org  Tue Mar  6 13:19:20 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 06 Mar 2012 11:19:20 -0700
Subject: [alsa-devel] [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine
 driver
In-Reply-To: <20120305170317.GV3224@opensource.wolfsonmicro.com>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
 <20120304133818.GE3083@opensource.wolfsonmicro.com>
 <20120305080623.GD16232@S2101-09.ap.freescale.net>
 <20120305115612.GB3224@opensource.wolfsonmicro.com>
 <20120305130707.GF16232@S2101-09.ap.freescale.net>
 <20120305131332.GM3224@opensource.wolfsonmicro.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861C14@HQMAIL01.nvidia.com>
 <20120305170317.GV3224@opensource.wolfsonmicro.com>
Message-ID: <4F565528.1090505@wwwdotorg.org>

On 03/05/2012 10:03 AM, Mark Brown wrote:
> * PGP Signed by an unknown key
> 
> On Mon, Mar 05, 2012 at 08:55:22AM -0800, Stephen Warren wrote:
>> Mark Brown wrote at Monday, March 05, 2012 6:14 AM:
> 
>>> The DMA and SSI drivers should have some relationship with each other if
>>> they're the same piece of hardware.  The machine driver certainly
>>> shouldn't be creating either of them.
> 
>> Note that in Tegra's case, the DMA HW and the DAI (I2S/SPDIF) HW are
>> entirely separate HW blocks and have entirely separate drivers. The DMA
>> engine is generic and not audio specific, so has a node that instantiates
>> just a standalone DMA device which has its own API. This doesn't
>> instantiate any kind of ALSA PCM driver. It doesn't make sense to have a
> 
> In this case (and probably in the i.MX case, at a guess the structure is
> the same) I'd just have the DAI drivers kick off registration of the
> ASoC DMA stuff, it's all part of the ASoC driver for the hardware really.

How would that work when there are multiple DAIs, e.g. on a system with
2 I2S and 1 SPDIF DAI and they all want to register the PCM driver? I
guess I could just add some utility function in the PCM driver file to
ensure that the platform device only gets created once, and probably
would also need to refcount it for when the DAIs get unloaded etc.

>> DT node to instantiate the ALSA PCM driver since the PCM driver is more
>> of an API bridge to the real DMA HW, and certainly not an actual HW
> 
> Yes, and a Linux driver model device is questionable too.
> 
>> Perhaps our regular DMA module driver should expose both its custom
>> interface for other clients, and register an ASoC PCM driver? That way
>> we could remove the PCM device registration from the ASoC machine
>> drivers.
> 
> That's another option, do it from the DMA driver instead of the DAI
> driver.  My main concern here is that it shouldn't be the machine driver
> as it's all internal to the CPU and not machine specific.

OK, not sure which way I prefer yet.

I'll file a bug internally for this so I don't forget about it...


From jason at lakedaemon.net  Tue Mar  6 13:22:33 2012
From: jason at lakedaemon.net (Jason)
Date: Tue, 6 Mar 2012 13:22:33 -0500
Subject: [RFC 00/14] Generic clk for Orion platforms.
In-Reply-To: <20120306175333.GA16608@lunn.ch>
References: <1331015471-28872-1-git-send-email-andrew@lunn.ch>
 <20120306155840.GS5050@titan.lakedaemon.net>
 <20120306161743.GI24858@lunn.ch>
 <20120306172341.GU5050@titan.lakedaemon.net>
 <20120306175333.GA16608@lunn.ch>
Message-ID: <20120306182233.GV5050@titan.lakedaemon.net>

On Tue, Mar 06, 2012 at 06:53:33PM +0100, Andrew Lunn wrote:
> > > You missed an important point. No driver has claimed these, but u-boot
> > > has turned them on.
> > 
> > This sounds like a bug in u-boot.
> 
> Is it? Even if it is, we have to live with it. Otherwise we introduce
> a regression, which is a big no-no. Also, how many users know how to
> upgrade u-boot? I don't have the necessary JTAG setup for my boxes, so
> i'm not going to risk bricking them by trying to upgrade u-boot.

Wrong is wrong.  if u-boot is enabling things that aren't needed
immediately after handoff, that needs to be fixed.  If the kernel is
depending on that error and not checking the state of the clocks before
performing actions, that also is broken.

Upgrading u-boot is necessary to support devicetree on kirkwood.  At
least, in any real fashion.  You could append the blob, but that is
Discouraged. ;-)

What kirkwood boards do you have?

> > Until that happens, could we walk across kirkwood_clks[] in
> > kirkwood_clock_gate() to determine what is in use?  eg:
> > 
> > #########
> > curr = readl(CLOCK_GATING_CTRL);
> > ...
> > used = CGC_DUNIT | CGC_RESERVED;
> > 
> > for (i = 0; i < ARRAY_SIZE(kirkwood_clks); i++) {
> > 	if (kirkwood_clks[i]->enable_count)
> > 		used |= kirkwood_clks[i]->/*PFM*/->mask;
> > }
> > 
> > /* disable anything in curr, but not in used */
> > if (CGC_SATA0 & (curr & ~used)) {
> > 	/* disable sata0 logic */
> > }
> > 
> > ...
> > #########
> 
> NO! clk is opaque. You should not be accessing members inside it. The
> clk struct members are not even declared when using the normal include
> files.

Ok, then how about:

	if (clk_is_enabled(kirkwood_clks[i])
		used |= 1 << clk_gate_bit_idx(kirkwood_clks[i]);

> Probably the short term solution is to simply add a deliberate
> regression, and not turn them off. Then help Mike implement generic
> code to handle this. We probably have three months to do this, since i
> doubt the clock code is going to be part of the next merge.

Good point.  I'd like to get it stabilized sooner rather than later,
though.

thx,

Jason.


From nm at ti.com  Tue Mar  6 13:32:47 2012
From: nm at ti.com (Nishanth Menon)
Date: Tue,  6 Mar 2012 12:32:47 -0600
Subject: [PATCH] OMAP3+: PM: VP: fix integer truncation error
Message-ID: <1331058767-28933-1-git-send-email-nm@ti.com>

From: Yuan Jiangli <jlyuan at motorola.com>

commit 2f34ce81b8c05c900e45bd88595cc154f7bb5957
(OMAP3: PM: Adding voltage driver support.)
introduced runtime computation of waittime to handle all potential
sys clocks available.

In the voltage processor, the SPMSUpdateWait is calculated based on
the slew rate and the voltage step (SMPSUpdateWait = slew rate *
Voltage Step). After the voltage processor receives the SMPS_Ack
signal, the Voltage Controller will wait for SMPSUpdateWait clock
cycles for the voltage to settle to the new value. For all
practical purposes, the waittime parameter is the OMAP hardware
translation of what the slew rate on the PMIC is.

As an example, with TPS62361 on OMAP4460,
step_size = 10000
slew_rate = 32000
sys_clk_rate = 38400

Our current computation results in the following:
 = ((step_size / slew_rate) * sys_clk_rate) / 1000
 = ((10000 / 32000) * 38400 / 1000
 = 0

Fix the same using DIV_ROUND_UP as an extra wait clock cycle
is better than lesser clock cycle. For the above example, this
translates to:
 = (10000 * 38400) / (1000 * 32000)
 = 12

Change-Id: I0ee22e60555e1cfd6cc3dea7ee44d0584ce182b6
Acked-by: Jon Hunter <jon-hunter at ti.com>
[nm at ti.com: slightly better implementation]
Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Yuan Jiangli <jlyuan at motorola.com>
---
 arch/arm/mach-omap2/vp.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index 0df8882..f95c1ba 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -61,8 +61,8 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
 	vddmin = voltdm->pmic->vp_vddmin;
 	vddmax = voltdm->pmic->vp_vddmax;
 
-	waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
-		    sys_clk_rate) / 1000;
+	waittime = DIV_ROUND_UP(voltdm->pmic->step_size * sys_clk_rate,
+				1000 * voltdm->pmic->slew_rate);
 	vstepmin = voltdm->pmic->vp_vstepmin;
 	vstepmax = voltdm->pmic->vp_vstepmax;
 
-- 
1.7.5.4



From santosh.shilimkar at ti.com  Tue Mar  6 13:36:29 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 6 Mar 2012 19:36:29 +0100
Subject: [PATCH] OMAP3+: PM: VP: fix integer truncation error
In-Reply-To: <1331058767-28933-1-git-send-email-nm@ti.com>
References: <1331058767-28933-1-git-send-email-nm@ti.com>
Message-ID: <CAMQu2gw5bZg1kw2-jrtAs4MTkaPPfDsimhwCWmZUCCe3rOu8rw@mail.gmail.com>

On Tue, Mar 6, 2012 at 7:32 PM, Nishanth Menon <nm at ti.com> wrote:
> From: Yuan Jiangli <jlyuan at motorola.com>
>
> commit 2f34ce81b8c05c900e45bd88595cc154f7bb5957
> (OMAP3: PM: Adding voltage driver support.)
> introduced runtime computation of waittime to handle all potential
> sys clocks available.
>
> In the voltage processor, the SPMSUpdateWait is calculated based on
> the slew rate and the voltage step (SMPSUpdateWait = slew rate *
> Voltage Step). After the voltage processor receives the SMPS_Ack
> signal, the Voltage Controller will wait for SMPSUpdateWait clock
> cycles for the voltage to settle to the new value. For all
> practical purposes, the waittime parameter is the OMAP hardware
> translation of what the slew rate on the PMIC is.
>
> As an example, with TPS62361 on OMAP4460,
> step_size = 10000
> slew_rate = 32000
> sys_clk_rate = 38400
>
> Our current computation results in the following:
> ?= ((step_size / slew_rate) * sys_clk_rate) / 1000
> ?= ((10000 / 32000) * 38400 / 1000
> ?= 0
>
> Fix the same using DIV_ROUND_UP as an extra wait clock cycle
> is better than lesser clock cycle. For the above example, this
> translates to:
> ?= (10000 * 38400) / (1000 * 32000)
> ?= 12
>
> Change-Id: I0ee22e60555e1cfd6cc3dea7ee44d0584ce182b6
You don't need above gerrit change id in commit message.

Regardas
Santosh


From nm at ti.com  Tue Mar  6 13:50:09 2012
From: nm at ti.com (Menon, Nishanth)
Date: Tue, 6 Mar 2012 12:50:09 -0600
Subject: [PATCH] OMAP3+: PM: VP: fix integer truncation error
In-Reply-To: <CAMQu2gw5bZg1kw2-jrtAs4MTkaPPfDsimhwCWmZUCCe3rOu8rw@mail.gmail.com>
References: <1331058767-28933-1-git-send-email-nm@ti.com>
 <CAMQu2gw5bZg1kw2-jrtAs4MTkaPPfDsimhwCWmZUCCe3rOu8rw@mail.gmail.com>
Message-ID: <CAOMWX4dMepOb-Vri-G7k0VfMnmApcHXxTGeAUJVjE3aHUQFLSQ@mail.gmail.com>

On Tue, Mar 6, 2012 at 12:36, Shilimkar, Santosh
<santosh.shilimkar at ti.com> wrote:
> > Change-Id: I0ee22e60555e1cfd6cc3dea7ee44d0584ce182b6
> You don't need above gerrit change id in commit message.
yow.. thanks for catching it, my bad.. thought i fixed it..
Regards,

Nishanth Menon


From nm at ti.com  Tue Mar  6 13:51:12 2012
From: nm at ti.com (Nishanth Menon)
Date: Tue,  6 Mar 2012 12:51:12 -0600
Subject: [PATCH V2] OMAP3+: PM: VP: fix integer truncation error
Message-ID: <1331059872-29011-1-git-send-email-nm@ti.com>

From: Yuan Jiangli <jlyuan at motorola.com>

commit 2f34ce81b8c05c900e45bd88595cc154f7bb5957
(OMAP3: PM: Adding voltage driver support.)
introduced runtime computation of waittime to handle all potential
sys clocks available.

In the voltage processor, the SPMSUpdateWait is calculated based on
the slew rate and the voltage step (SMPSUpdateWait = slew rate *
Voltage Step). After the voltage processor receives the SMPS_Ack
signal, the Voltage Controller will wait for SMPSUpdateWait clock
cycles for the voltage to settle to the new value. For all
practical purposes, the waittime parameter is the OMAP hardware
translation of what the slew rate on the PMIC is.

As an example, with TPS62361 on OMAP4460,
step_size = 10000
slew_rate = 32000
sys_clk_rate = 38400

Our current computation results in the following:
 = ((step_size / slew_rate) * sys_clk_rate) / 1000
 = ((10000 / 32000) * 38400 / 1000
 = 0

Fix the same using DIV_ROUND_UP as an extra wait clock cycle
is better than lesser clock cycle. For the above example, this
translates to:
 = (10000 * 38400) / (1000 * 32000)
 = 12

Acked-by: Jon Hunter <jon-hunter at ti.com>
[nm at ti.com: slightly better implementation]
Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Yuan Jiangli <jlyuan at motorola.com>
---
 arch/arm/mach-omap2/vp.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index 0df8882..f95c1ba 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -61,8 +61,8 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
 	vddmin = voltdm->pmic->vp_vddmin;
 	vddmax = voltdm->pmic->vp_vddmax;
 
-	waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
-		    sys_clk_rate) / 1000;
+	waittime = DIV_ROUND_UP(voltdm->pmic->step_size * sys_clk_rate,
+				1000 * voltdm->pmic->slew_rate);
 	vstepmin = voltdm->pmic->vp_vstepmin;
 	vstepmax = voltdm->pmic->vp_vstepmax;
 
-- 
1.7.5.4



From olof at lixom.net  Tue Mar  6 13:55:53 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 6 Mar 2012 10:55:53 -0800
Subject: [PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for
 EXYNOS5250
In-Reply-To: <00a901ccf084$90460900$b0d21b00$%kim@samsung.com>
References: <1328981685-8602-1-git-send-email-kgene.kim@samsung.com>
 <1328981685-8602-5-git-send-email-kgene.kim@samsung.com>
 <CAOesGMhmcnt6LPb9O+3420VgG=PiCnOjzZA3JqsA=4OdHN-R-g@mail.gmail.com>
 <00a901ccf084$90460900$b0d21b00$%kim@samsung.com>
Message-ID: <CAOesGMgedngJKRVCYwK=+xRnchXj4StGLTVqvv9BMqVhtM=5RA@mail.gmail.com>

Hi,

On Tue, Feb 21, 2012 at 2:35 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:

> Yes, as you said, it brakes single zImage for EXYNOS4 + EXYNOS5
> (mach-exynos). So I'm working on regarding resource for EXYNOS SoCs and I
> think, it can resolve the problem you said before v3.4 merge window.
>
> If any updates, let you know.

Just a friendly reminder; the time is close to running out for staging
new code for 3.4.


-Olof


From s.hauer at pengutronix.de  Tue Mar  6 14:00:39 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 6 Mar 2012 20:00:39 +0100
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
Message-ID: <20120306190039.GJ3852@pengutronix.de>

On Mon, Mar 05, 2012 at 12:03:15PM -0800, Turquette, Mike wrote:
> On Sun, Mar 4, 2012 at 11:38 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > On Sun, Mar 04, 2012 at 04:12:21PM -0800, Turquette, Mike wrote:
> >> >>
> >> >> I believe this patch already does what you suggest, but I might be
> >> >> missing your point.
> >> >
> >> > In include/linux/clk-private.h you expose struct clk outside the core.
> >> > This has to be done to make static initializers possible. There is a big
> >> > warning in this file that it must not be included from files implementing
> >> > struct clk_ops. You can simply avoid this warning by declaring struct clk
> >> > with only a single member:
> >> >
> >> > include/linux/clk.h:
> >> >
> >> > struct clk {
> >> > ? ? ? ?struct clk_internal *internal;
> >> > };
> >> >
> >> > This way everybody knows struct clk (thus can embed it in their static
> >> > initializers), but doesn't know anything about the internal members. Now
> >> > in drivers/clk/clk.c you declare struct clk_internal exactly like struct
> >> > clk was declared before:
> >> >
> >> > struct clk_internal {
> >> > ? ? ? ?const char ? ? ? ? ? ? ?*name;
> >> > ? ? ? ?const struct clk_ops ? ?*ops;
> >> > ? ? ? ?struct clk_hw ? ? ? ? ? *hw;
> >> > ? ? ? ?struct clk ? ? ? ? ? ? ?*parent;
> >> > ? ? ? ?char ? ? ? ? ? ? ? ? ? ?**parent_names;
> >> > ? ? ? ?struct clk ? ? ? ? ? ? ?**parents;
> >> > ? ? ? ?u8 ? ? ? ? ? ? ? ? ? ? ?num_parents;
> >> > ? ? ? ?unsigned long ? ? ? ? ? rate;
> >> > ? ? ? ?unsigned long ? ? ? ? ? flags;
> >> > ? ? ? ?unsigned int ? ? ? ? ? ?enable_count;
> >> > ? ? ? ?unsigned int ? ? ? ? ? ?prepare_count;
> >> > ? ? ? ?struct hlist_head ? ? ? children;
> >> > ? ? ? ?struct hlist_node ? ? ? child_node;
> >> > ? ? ? ?unsigned int ? ? ? ? ? ?notifier_count;
> >> > #ifdef CONFIG_COMMON_CLK_DEBUG
> >> > ? ? ? ?struct dentry ? ? ? ? ? *dentry;
> >> > #endif
> >> > };
> >> >
> >> > An instance of struct clk_internal will be allocated in
> >> > __clk_init/clk_register. Now the private data stays completely inside
> >> > the core and noone can abuse it.
> >>
> >> Hi Sascha,
> >>
> >> I see the disconnect here. ?For OMAP (and possibly other platforms) at
> >> least some clock data is necessary during early boot, before the
> >> regular allocation methods are available (timers for instance).
> >
> > We had this problem on i.MX aswell. It turned out that the timer clock
> > is the only clock that is needed so early. We solved this by moving the
> > clock init to the system timer init function.
> 
> When you say "mov[ed] the clock init to the system timer init
> function" do you mean that you statically allocated struct clk and
> used the clk framework api, or instead you just did some direct
> register writes to initialize things properly?

I meant that on i.MX we do the clock tree initialization when kmalloc is
available, see the attached patch for omap4 based on your branch which
does the same for Omap. The first clock you need is the one for the
timer, so you can initialize the clocktree at the beginning of
time_init() and don't need statically initialized clocks anymore.

> >
> > Well, the file is work in progress, you probably fix this before sending
> > it out, but I bet people will include clk-private.h and nobody else
> > notices it.
> 
> clock44xx_data.c does not violate that rule.  None of the logic that
> implements ops for those clocks is present clock44xx_data.c.

Indeed, I missed that. It only has the ops but not the individual
functions.

> All of
> the code in that file is simply initialization and registration of
> OMAP4 clocks.  Many of the clocks are basic clock types (divider,
> multiplexer and fixed-rate are used in that file) with protected code
> drivers/clk/clk-*.c and the remaining clocks are of the struct
> clk_hw_omap variety, which has code spread across several files:
> 
> arch/arm/mach-omap2/clock.c
> arch/arm/mach-omap2/clock.h
> arch/arm/mach-omap2/clkt_dpll.c
> arch/arm/mach-omap2/clkt_clksel.c
> arch/arm/mach-omap2/dpll3xxx.c
> arch/arm/mach-omap2/dpll4xxx.c
> 
> All of the above files include linux/clk-provider.h, not
> linux/clk-private.h.  That code makes heavy use of the
> __clk_get_whatever helpers and shows how a platform might honor the
> layer of separation between struct clk and stuct clk_ops/struct
> clk_foo.  You are correct that the code is a work-in-progress, but
> there are no layering violations that I can see.
> 
> I also think we are talking past each other to some degree.  One point
> I would like to make (and maybe you already know this from code
> review) is that it is unnecessary to have pointers to your parent
> struct clk*'s when either initializing or registering your clocks.  In
> fact the existing clk_register_foo functions don't even allow you to
> pass in parent pointers and rely wholly on string name matching.  I
> just wanted to point that out in case it went unnoticed, as it is a
> new way of doing things from the previous series and was born out of
> Thomas' review of V4 and multi-parent handling.  This also keeps
> device-tree in mind where we might not know the struct clk *pointer at
> compile time for "connecting" discrete devices.

Yes, I've seen this and I really like it. Also the change that
multiplexers return an index to an array instead of the parent
clock is very nice.

Sascha


8<-----------------------------------------------------

ARM omap4: move clocktree init to timer init time so we don't need static clocks

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-omap2/clock44xx_data.c |    4 +++-
 arch/arm/mach-omap2/io.c             |    1 -
 arch/arm/mach-omap2/timer.c          |    3 +++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 7f833a7..5aa8dd2 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -6032,7 +6032,9 @@ int __init omap4xxx_clk_init(void)
 		}
 # else
 		clkdev_add(c);
-		__clk_init(NULL, c->clk);
+
+		clk_register(NULL, c->clk->name, c->clk->ops, c->clk->hw,
+			c->clk->parent_names, c->clk->num_parents, c->clk->flags);
 #endif
 	}
 
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index eb50c29..8db4380 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -476,7 +476,6 @@ void __init omap4430_init_early(void)
 	omap44xx_clockdomains_init();
 	omap44xx_hwmod_init();
 	omap_hwmod_init_postsetup();
-	omap4xxx_clk_init();
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5c9acea..2cca796 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -323,9 +323,12 @@ OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 OMAP_SYS_TIMER(3_secure)
 #endif
 
+int __init omap4xxx_clk_init(void);
+
 #ifdef CONFIG_ARCH_OMAP4
 static void __init omap4_timer_init(void)
 {
+	omap4xxx_clk_init();
 #ifdef CONFIG_LOCAL_TIMERS
 	twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
 	BUG_ON(!twd_base);
-- 
1.7.9.1

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From jason at lakedaemon.net  Tue Mar  6 14:01:39 2012
From: jason at lakedaemon.net (Jason)
Date: Tue, 6 Mar 2012 14:01:39 -0500
Subject: [RFC 09/14] MV SATA: Add per channel clk/clkdev support.
In-Reply-To: <1331015471-28872-10-git-send-email-andrew@lunn.ch>
References: <1331015471-28872-1-git-send-email-andrew@lunn.ch>
 <1331015471-28872-10-git-send-email-andrew@lunn.ch>
Message-ID: <20120306190139.GW5050@titan.lakedaemon.net>

On Tue, Mar 06, 2012 at 07:31:05AM +0100, Andrew Lunn wrote:
> The Orion kirkwood chips have a gatable clock per SATA channel. Add
> code to get and enable this clk if it exists.
> 
> Signed-of-by: Andrew Lunn <andrew at lunn.ch>
> ---
>  arch/arm/mach-kirkwood/common.c           |    3 ++
>  arch/arm/plat-orion/common.c              |    4 +-
>  arch/arm/plat-orion/include/plat/common.h |    3 ++
>  drivers/ata/sata_mv.c                     |   43 +++++++++++++++++++++++++---
>  4 files changed, 46 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index 7588812..855540a 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -244,6 +244,9 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
>  	if (sata_data->n_ports > 1)
>  		kirkwood_clk_ctrl |= CGC_SATA1;
>  
> +	orion_clkdev_add("0", "sata_mv.0", &clk_sata0);
> +	orion_clkdev_add("1", "sata_mv.0", &clk_sata1);
> +

This is a problem for devicetree.  With devicetree, neither
kirkwood_sata_init(), nor orion_sata_init() are ever called.  The same
is true for all the other drivers as well.

Could this be moved into the driver's _probe() function?

thx,

Jason.

>  	orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
>  }
>  
> diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
> index 05f078a..06f1e7a 100644
> --- a/arch/arm/plat-orion/common.c
> +++ b/arch/arm/plat-orion/common.c
> @@ -23,8 +23,8 @@
>  #include <plat/ehci-orion.h>
>  
>  /* Create a clkdev entry for a given device/clk */
> -static void orion_clkdev_add(const char *con_id, const char *dev_id,
> -			     struct clk *clk)
> +void orion_clkdev_add(const char *con_id, const char *dev_id,
> +		      struct clk *clk)
>  {
>  	struct clk_lookup *cl;
>  
> diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
> index a70976e..b739343 100644
> --- a/arch/arm/plat-orion/include/plat/common.h
> +++ b/arch/arm/plat-orion/include/plat/common.h
> @@ -107,4 +107,7 @@ void __init orion_crypto_init(unsigned long mapbase,
>  			      unsigned long srambase,
>  			      unsigned long sram_size,
>  			      unsigned long irq);
> +
> +void orion_clkdev_add(const char *con_id, const char *dev_id,
> +		      struct clk *clk);
>  #endif
> diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
> index 38950ea..0f4a7e9 100644
> --- a/drivers/ata/sata_mv.c
> +++ b/drivers/ata/sata_mv.c
> @@ -553,6 +553,7 @@ struct mv_host_priv {
>  
>  #if defined(CONFIG_HAVE_CLK)
>  	struct clk		*clk;
> +	struct clk              **port_clks;
>  #endif
>  	/*
>  	 * These consistent DMA memory pools give us guaranteed
> @@ -4026,6 +4027,9 @@ static int mv_platform_probe(struct platform_device *pdev)
>  	struct mv_host_priv *hpriv;
>  	struct resource *res;
>  	int n_ports, rc;
> +#if defined(CONFIG_HAVE_CLK)
> +	int port;
> +#endif
>  
>  	ata_print_version_once(&pdev->dev, DRV_VERSION);
>  
> @@ -4053,6 +4057,13 @@ static int mv_platform_probe(struct platform_device *pdev)
>  
>  	if (!host || !hpriv)
>  		return -ENOMEM;
> +#if defined(CONFIG_HAVE_CLK)
> +	hpriv->port_clks = devm_kzalloc(&pdev->dev,
> +					sizeof(struct clk *) * n_ports,
> +					GFP_KERNEL);
> +	if (!hpriv->port_clks)
> +		return -ENOMEM;
> +#endif
>  	host->private_data = hpriv;
>  	hpriv->n_ports = n_ports;
>  	hpriv->board_idx = chip_soc;
> @@ -4065,9 +4076,18 @@ static int mv_platform_probe(struct platform_device *pdev)
>  #if defined(CONFIG_HAVE_CLK)
>  	hpriv->clk = clk_get(&pdev->dev, NULL);
>  	if (IS_ERR(hpriv->clk))
> -		dev_notice(&pdev->dev, "cannot get clkdev\n");
> -	else
> -		clk_enable(hpriv->clk);
> +		dev_notice(&pdev->dev, "cannot get optional clkdev\n");
> +	else {
> +		clk_prepare_enable(hpriv->clk);
> +	}
> +	for (port = 0; port < n_ports; port++) {
> +		char port_number[16];
> +		sprintf(port_number, "%d", port);
> +		hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
> +		if (!IS_ERR(hpriv->port_clks[port])) {
> +			clk_prepare_enable(hpriv->port_clks[port]);
> +		}
> +	}
>  #endif
>  
>  	/*
> @@ -4097,9 +4117,15 @@ static int mv_platform_probe(struct platform_device *pdev)
>  err:
>  #if defined(CONFIG_HAVE_CLK)
>  	if (!IS_ERR(hpriv->clk)) {
> -		clk_disable(hpriv->clk);
> +		clk_disable_unprepare(hpriv->clk);
>  		clk_put(hpriv->clk);
>  	}
> +	for (port = 0; port < n_ports; port++) {
> +		if (!IS_ERR(hpriv->port_clks[port])) {
> +			clk_disable_unprepare(hpriv->port_clks[port]);
> +			clk_put(hpriv->port_clks[port]);
> +		}
> +	}
>  #endif
>  
>  	return rc;
> @@ -4118,14 +4144,21 @@ static int __devexit mv_platform_remove(struct platform_device *pdev)
>  	struct ata_host *host = platform_get_drvdata(pdev);
>  #if defined(CONFIG_HAVE_CLK)
>  	struct mv_host_priv *hpriv = host->private_data;
> +	int port;
>  #endif
>  	ata_host_detach(host);
>  
>  #if defined(CONFIG_HAVE_CLK)
>  	if (!IS_ERR(hpriv->clk)) {
> -		clk_disable(hpriv->clk);
> +		clk_disable_unprepare(hpriv->clk);
>  		clk_put(hpriv->clk);
>  	}
> +	for (port = 0; port < host->n_ports; port++) {
> +		if (!IS_ERR(hpriv->port_clks[port])) {
> +			clk_disable_unprepare(hpriv->port_clks[port]);
> +			clk_put(hpriv->port_clks[port]);
> +		}
> +	}
>  #endif
>  	return 0;
>  }
> -- 
> 1.7.9.1
> 


From thierry.reding at avionic-design.de  Tue Mar  6 14:09:12 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 6 Mar 2012 20:09:12 +0100
Subject: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock
 detection loop
In-Reply-To: <4F56424A.3020305@wwwdotorg.org>
References: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>
 <1331023544-6439-3-git-send-email-mad_soft@inbox.ru>
 <4F56424A.3020305@wwwdotorg.org>
Message-ID: <20120306190912.GA13882@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> > Tegra PCIe driver waits for PLL to lock using busy loop.
> > If PLL fails to lock for some reason, this leads to silent lockup
> > while booting (as PCIe code is not modular).
> > 
> > Fix by adding timeout, so if PLL doesn't lock in a couple
> > of seconds, just PCIe driver fails and machine continues to boot.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>
> 
> That seems reasonable. So once the mdelay discussion is resolved,
> 
> Acked-by: Stephen Warren <swarren at wwwdotorg.org>
> 
> Any idea why the PLL doesn't lock sometimes?

I've seen this happen when the 1.05V regulator (GPIO#2 of the PMU on Harmony)
isn't enabled.

Thierry
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From tony at atomide.com  Tue Mar  6 14:10:59 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 6 Mar 2012 11:10:59 -0800
Subject: [PATCH] ARM: OMAP2: Fix section warning for n8x0 when
 CONFIG_MMC_OMAP is not set
Message-ID: <20120306191059.GT12083@atomide.com>

Otherwise we get:

arch/arm/mach-omap2/board-n8x0.c:39:12: warning:
'slot1_cover_open' defined but not used [-Wunused-variable]
arch/arm/mach-omap2/board-n8x0.c:40:12: warning:
'slot2_cover_open' defined but not used [-Wunused-variable]
arch/arm/mach-omap2/board-n8x0.c:41:23: warning:
'mmc_device' defined but not used [-Wunused-variable]

Reported-by: Russell King <linux at arm.linux.org.uk>
Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -36,10 +36,6 @@
 
 #include "mux.h"
 
-static int slot1_cover_open;
-static int slot2_cover_open;
-static struct device *mmc_device;
-
 #define TUSB6010_ASYNC_CS	1
 #define TUSB6010_SYNC_CS	4
 #define TUSB6010_GPIO_INT	58
@@ -211,6 +207,10 @@ static struct omap_onenand_platform_data board_onenand_data[] = {
 #define N810_EMMC_VSD_GPIO	23
 #define N810_EMMC_VIO_GPIO	9
 
+static int slot1_cover_open;
+static int slot2_cover_open;
+static struct device *mmc_device;
+
 static int n8x0_mmc_switch_slot(struct device *dev, int slot)
 {
 #ifdef CONFIG_MMC_DEBUG


From thierry.reding at avionic-design.de  Tue Mar  6 14:17:12 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 6 Mar 2012 20:17:12 +0100
Subject: [PATCH v3 02/10] pwm: Allow chips to support multiple PWMs.
In-Reply-To: <201203061538.11709.arnd@arndb.de>
References: <1329923841-32017-1-git-send-email-thierry.reding@avionic-design.de>
 <20120223160420.GA9899@avionic-0098.mockup.avionic-design.de>
 <20120303193249.GA22021@avionic-0098.mockup.avionic-design.de>
 <201203061538.11709.arnd@arndb.de>
Message-ID: <20120306191712.GB13882@avionic-0098.mockup.avionic-design.de>

* Arnd Bergmann wrote:
> On Saturday 03 March 2012, Thierry Reding wrote:
> > I turns out that this is not as easy to do as I thought. The problem is that
> > if I remove the pwmchip_find() from the core and move the lookup
> > functionality into the OF support code I no longer have access to the list of
> > PWM chips. So I guess it will have to stay in to keep things encapsulated
> > properly.
> 
> Well, or you move everything into the one file. If you have the device tree
> support function in the same file as everything else, you no longer need
> the additional complexity.

Okay, I think it makes the most sense to move all of the OF support code into
drivers/pwm/core.c. That way we can also check off the discussion about the
OF support code's location.

Thierry
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From nico at fluxnic.net  Tue Mar  6 14:45:23 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 06 Mar 2012 14:45:23 -0500 (EST)
Subject: [RFC 00/14] Generic clk for Orion platforms.
In-Reply-To: <20120306172341.GU5050@titan.lakedaemon.net>
References: <1331015471-28872-1-git-send-email-andrew@lunn.ch>
 <20120306155840.GS5050@titan.lakedaemon.net> <20120306161743.GI24858@lunn.ch>
 <20120306172341.GU5050@titan.lakedaemon.net>
Message-ID: <alpine.LFD.2.02.1203061439190.31242@xanadu.home>

On Tue, 6 Mar 2012, Jason wrote:
> On Tue, Mar 06, 2012 at 05:17:43PM +0100, Andrew Lunn wrote:
> > On Tue, Mar 06, 2012 at 10:58:40AM -0500, Jason wrote:
> > > I'm assuming the driver(s) will increment a reference, so when it
> > > reaches zero, the framework would call a clk_gate hook.
> > 
> > You missed an important point. No driver has claimed these, but u-boot
> > has turned them on.
> 
> This sounds like a bug in u-boot.
> 
> > So we want linux to turn off all clocks for which
> > there is no driver using them, in order to save power.
> > kirkwood_clk_ctrl is dual purpose. It turns on needed clocks, but it
> > also turns off unneeded clocks.
> 
> This is creating a lot of complexity where the real answer seems to be
> to get u-boot to shutoff all peripheral clocks before handing over
> control to linux.

No.

Yes, u-Boot might be wrong.  But the kernel should always distrust as 
much as possible from the bootloader.  Instead of presuming some initial 
state from the bootloader, it is best to simply set that state up front.

The fewer ties you have with any bootloaders, the fewer bugs you'll have 
in the end.  Otherwise you might enter into a game of requiring a 
specific version of a specific bootloader to go with a given kernel, and 
that is far more complex to deal with than the complexity you are 
referring to above.


Nicolas


From paul.gortmaker at windriver.com  Tue Mar  6 14:46:43 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Tue,  6 Mar 2012 14:46:43 -0500
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
Message-ID: <1331063203-21188-1-git-send-email-paul.gortmaker@windriver.com>

commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)

  "regulator: Remove support for supplies specified by struct device"

deletes the field from the struct, but this platform was still trying
to set those fields.  Delete the assignments.

arch/arm/mach-pxa/magician.c:581: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/magician.c:581: warning: initialization from incompatible pointer type
arch/arm/mach-pxa/magician.c:585: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/magician.c:585: warning: initialization from incompatible pointer type

arch/arm/mach-pxa/hx4700.c:683: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/hx4700.c:683: warning: initialization from incompatible pointer type
arch/arm/mach-pxa/hx4700.c:687: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/hx4700.c:687: warning: initialization from incompatible pointer type

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>

diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index f2c23ea..76de30c 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -680,11 +680,9 @@ static struct platform_device power_supply = {
 
 static struct regulator_consumer_supply bq24022_consumers[] = {
 	{
-		.dev = &gpio_vbus.dev,
 		.supply = "vbus_draw",
 	},
 	{
-		.dev = &power_supply.dev,
 		.supply = "ac_draw",
 	},
 };
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 3d6baf9..bd0f86a 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -578,11 +578,9 @@ static struct platform_device power_supply = {
 
 static struct regulator_consumer_supply bq24022_consumers[] = {
 	{
-		.dev = &gpio_vbus.dev,
 		.supply = "vbus_draw",
 	},
 	{
-		.dev = &power_supply.dev,
 		.supply = "ac_draw",
 	},
 };
-- 
1.7.9.1



From tony at atomide.com  Tue Mar  6 14:47:48 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 6 Mar 2012 11:47:48 -0800
Subject: [PATCH] ARM: OMAP2+: Fix omap24xx_io_desc warning if SoC subtypes
 are not selected
Message-ID: <20120306194748.GU12083@atomide.com>

Otherwise we get the following warning:

arch/arm/mach-omap2/io.c:53:24: warning:
'omap24xx_io_desc' defined but not used [-Wunused-variable]

Reported-by: Russell King <linux at arm.linux.org.uk>
Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -49,7 +49,7 @@
  * default mapping provided here.
  */
 
-#ifdef CONFIG_ARCH_OMAP2
+#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
 static struct map_desc omap24xx_io_desc[] __initdata = {
 	{
 		.virtual	= L3_24XX_VIRT,


From nico at fluxnic.net  Tue Mar  6 14:49:43 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 06 Mar 2012 14:49:43 -0500 (EST)
Subject: [PATCH 6/6] ARM: mm: truncate memory banks to fit in 4GB space for
 classic MMU
In-Reply-To: <20120306175853.GB17518@mudshark.cambridge.arm.com>
References: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
 <1331052846-19144-7-git-send-email-will.deacon@arm.com>
 <4F565230.6030800@ru.mvista.com>
 <20120306175853.GB17518@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1203061448540.31242@xanadu.home>

On Tue, 6 Mar 2012, Will Deacon wrote:

> On Tue, Mar 06, 2012 at 06:06:40PM +0000, Sergei Shtylyov wrote:
> > Hello.
> 
> Hi Sergei,
> 
> > On 03/06/2012 07:54 PM, Will Deacon wrote:
> > 
> > > If a bank of memory spanning the 4GB boundary is added on a !CONFIG_LPAE
> > > kernel then we will hang early during boot since the memory bank will
> > > have wrapped around to zero.
> > 
> > > This patch truncates memory banks for !LPAE configurations when the end
> > > address is not representable in 32 bits.
> > 
> > > Signed-off-by: Will Deacon<will.deacon at arm.com>
> > > ---
> > >   arch/arm/kernel/setup.c |   11 ++++++++++-
> > >   1 files changed, 10 insertions(+), 1 deletions(-)
> > 
> > > diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> > > index a255c39..aeaa048 100644
> > > --- a/arch/arm/kernel/setup.c
> > > +++ b/arch/arm/kernel/setup.c
> > > @@ -521,7 +521,16 @@ int __init arm_add_memory(phys_addr_t start, unsigned long size)
> > >   	 */
> > >   	size -= start&  ~PAGE_MASK;
> > >   	bank->start = PAGE_ALIGN(start);
> > > -	bank->size  = size&  PAGE_MASK;
> > > +
> > > +#ifndef CONFIG_LPAE
> > > +	if (bank->start + size<  bank->start) {
> > > +		printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
> > > +			"32-bit physical address space\n", (long long)start);
> > > +		size = ULONG_MAX - bank->start;
> > 
> >     I think you forgot to add one here.
> 
> No, I deliberately omit the last page because otherwise we end up with the
> end address of the bank being calculated as 0, which leads to boot failure.

What this mentioned in the code, or at least in the patch log?


Nicolas


From broonie at opensource.wolfsonmicro.com  Tue Mar  6 15:01:57 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 20:01:57 +0000
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <1331063203-21188-1-git-send-email-paul.gortmaker@windriver.com>
References: <1331063203-21188-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <20120306200156.GA19635@opensource.wolfsonmicro.com>

On Tue, Mar 06, 2012 at 02:46:43PM -0500, Paul Gortmaker wrote:

>  static struct regulator_consumer_supply bq24022_consumers[] = {
>  	{
> -		.dev = &gpio_vbus.dev,
>  		.supply = "vbus_draw",

No, this isn't a good fix - it will break the user.  You need to replace
dev with the equivalent dev_name.
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From mturquette at ti.com  Tue Mar  6 15:02:39 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 6 Mar 2012 12:02:39 -0800
Subject: [RFC 00/14] Generic clk for Orion platforms.
In-Reply-To: <alpine.LFD.2.02.1203061439190.31242@xanadu.home>
References: <1331015471-28872-1-git-send-email-andrew@lunn.ch>
 <20120306155840.GS5050@titan.lakedaemon.net> <20120306161743.GI24858@lunn.ch>
 <20120306172341.GU5050@titan.lakedaemon.net>
 <alpine.LFD.2.02.1203061439190.31242@xanadu.home>
Message-ID: <CAJOA=zO6wKPZ4LPusK=cPhH2AxN+piV7MGx=Lj8koXni2hMPFQ@mail.gmail.com>

On Tue, Mar 6, 2012 at 11:45 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Tue, 6 Mar 2012, Jason wrote:
>> On Tue, Mar 06, 2012 at 05:17:43PM +0100, Andrew Lunn wrote:
>> > On Tue, Mar 06, 2012 at 10:58:40AM -0500, Jason wrote:
>> > > I'm assuming the driver(s) will increment a reference, so when it
>> > > reaches zero, the framework would call a clk_gate hook.
>> >
>> > You missed an important point. No driver has claimed these, but u-boot
>> > has turned them on.
>>
>> This sounds like a bug in u-boot.
>>
>> > So we want linux to turn off all clocks for which
>> > there is no driver using them, in order to save power.
>> > kirkwood_clk_ctrl is dual purpose. It turns on needed clocks, but it
>> > also turns off unneeded clocks.
>>
>> This is creating a lot of complexity where the real answer seems to be
>> to get u-boot to shutoff all peripheral clocks before handing over
>> control to linux.
>
> No.
>
> Yes, u-Boot might be wrong. ?But the kernel should always distrust as
> much as possible from the bootloader. ?Instead of presuming some initial
> state from the bootloader, it is best to simply set that state up front.
>
> The fewer ties you have with any bootloaders, the fewer bugs you'll have
> in the end. ?Otherwise you might enter into a game of requiring a
> specific version of a specific bootloader to go with a given kernel, and
> that is far more complex to deal with than the complexity you are
> referring to above.

+1 to the above.

Let's not forget that the type of devices you would buy in a store
typically don't use u-boot, so having a u-boot-centric point of view
is simply too narrowly focused.  The greater the burden we add to
u-boot then the greater the burden we add to every bootloader out
there in the world.  The kernel should manage system resources, simple
as that.

The current clk series does have a flag that can be set per clk,
CLK_IGNORE_UNUSED, which allows platform clock data to NOT
automatically disable unused clocks.  Otherwise in a future revision
of the clock code there will be a late_initcall which walks the tree
disabling clocks that are enabled in hardware, but have prepare_count
== 0.  That didn't go in this time since I'm trying to get the current
stuff merged and adding features tends to slow that process down...

Regards,
Mike

>
>
> Nicolas
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From broonie at opensource.wolfsonmicro.com  Tue Mar  6 15:11:53 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 6 Mar 2012 20:11:53 +0000
Subject: [alsa-devel] [PATCH 20/20] ASoC: fsl: add imx-sgtl5000 machine
 driver
In-Reply-To: <4F565528.1090505@wwwdotorg.org>
References: <1330788001-10158-1-git-send-email-shawn.guo@linaro.org>
 <1330788001-10158-21-git-send-email-shawn.guo@linaro.org>
 <20120304133818.GE3083@opensource.wolfsonmicro.com>
 <20120305080623.GD16232@S2101-09.ap.freescale.net>
 <20120305115612.GB3224@opensource.wolfsonmicro.com>
 <20120305130707.GF16232@S2101-09.ap.freescale.net>
 <20120305131332.GM3224@opensource.wolfsonmicro.com>
 <74CDBE0F657A3D45AFBB94109FB122FF17BE861C14@HQMAIL01.nvidia.com>
 <20120305170317.GV3224@opensource.wolfsonmicro.com>
 <4F565528.1090505@wwwdotorg.org>
Message-ID: <20120306201153.GF19635@opensource.wolfsonmicro.com>

On Tue, Mar 06, 2012 at 11:19:20AM -0700, Stephen Warren wrote:

> > In this case (and probably in the i.MX case, at a guess the structure is
> > the same) I'd just have the DAI drivers kick off registration of the
> > ASoC DMA stuff, it's all part of the ASoC driver for the hardware really.
> 
> How would that work when there are multiple DAIs, e.g. on a system with
> 2 I2S and 1 SPDIF DAI and they all want to register the PCM driver? I
> guess I could just add some utility function in the PCM driver file to
> ensure that the platform device only gets created once, and probably
> would also need to refcount it for when the DAIs get unloaded etc.

You could just create a DMA device per DAI since it's just a wrapper,
you shouldn't even need to allocate a new struct device but just use the
DAI device when registering the ASoC DMA driver.
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From mad_soft at inbox.ru  Tue Mar  6 15:15:38 2012
From: mad_soft at inbox.ru (Dmitry Artamonow)
Date: Wed, 7 Mar 2012 00:15:38 +0400
Subject: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock
 detection loop
In-Reply-To: <4F56424A.3020305@wwwdotorg.org>
References: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>
 <1331023544-6439-3-git-send-email-mad_soft@inbox.ru>
 <4F56424A.3020305@wwwdotorg.org>
Message-ID: <20120306201538.GA14350@rainbow>

On 09:58 Tue 06 Mar     , Stephen Warren wrote:
> On 03/06/2012 01:45 AM, Dmitry Artamonow wrote:
> > Tegra PCIe driver waits for PLL to lock using busy loop.
> > If PLL fails to lock for some reason, this leads to silent lockup
> > while booting (as PCIe code is not modular).
> > 
> > Fix by adding timeout, so if PLL doesn't lock in a couple
> > of seconds, just PCIe driver fails and machine continues to boot.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>
> 
> That seems reasonable. So once the mdelay discussion is resolved,
> 
> Acked-by: Stephen Warren <swarren at wwwdotorg.org>
> 
> Any idea why the PLL doesn't lock sometimes?


Please dismiss this patch - I forgot to turn 'return' to 'return 0' at
the end of the function, while converting it's type from void to int,
and it causes driver to fail always now. I'll send updated version shortly.

Also I've managed to get another Harmony board today, and it doesn't have
problems with PLL locking (PLL locks on it in about 2ms), so probably the
issue I've seen is caused by some hardware fault on the first board,
or is specific to some particular revision of the board and/or Tegra2 chip.

I'll do more testing tomorrow and re-spin the patches.
-- 
Best regards,
Dmitry "MAD" Artamonow



From will.deacon at arm.com  Tue Mar  6 15:17:52 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 6 Mar 2012 20:17:52 +0000
Subject: [PATCH 6/6] ARM: mm: truncate memory banks to fit in 4GB space
 for classic MMU
In-Reply-To: <alpine.LFD.2.02.1203061448540.31242@xanadu.home>
References: <1331052846-19144-1-git-send-email-will.deacon@arm.com>
 <1331052846-19144-7-git-send-email-will.deacon@arm.com>
 <4F565230.6030800@ru.mvista.com>
 <20120306175853.GB17518@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1203061448540.31242@xanadu.home>
Message-ID: <20120306201752.GA18151@mudshark.cambridge.arm.com>

Hi Nicolas,

On Tue, Mar 06, 2012 at 07:49:43PM +0000, Nicolas Pitre wrote:
> On Tue, 6 Mar 2012, Will Deacon wrote:
> > On Tue, Mar 06, 2012 at 06:06:40PM +0000, Sergei Shtylyov wrote:
> > > On 03/06/2012 07:54 PM, Will Deacon wrote:
> > > 
> > > > +#ifndef CONFIG_LPAE
> > > > +	if (bank->start + size<  bank->start) {
> > > > +		printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
> > > > +			"32-bit physical address space\n", (long long)start);
> > > > +		size = ULONG_MAX - bank->start;
> > > 
> > >     I think you forgot to add one here.
> > 
> > No, I deliberately omit the last page because otherwise we end up with the
> > end address of the bank being calculated as 0, which leads to boot failure.
> 
> What this mentioned in the code, or at least in the patch log?

Good idea - I'll add a comment to the code when we assign size.

Will


From jason at lakedaemon.net  Tue Mar  6 15:32:22 2012
From: jason at lakedaemon.net (Jason)
Date: Tue, 6 Mar 2012 15:32:22 -0500
Subject: [RFC 00/14] Generic clk for Orion platforms.
In-Reply-To: <alpine.LFD.2.02.1203061439190.31242@xanadu.home>
References: <1331015471-28872-1-git-send-email-andrew@lunn.ch>
 <20120306155840.GS5050@titan.lakedaemon.net>
 <20120306161743.GI24858@lunn.ch>
 <20120306172341.GU5050@titan.lakedaemon.net>
 <alpine.LFD.2.02.1203061439190.31242@xanadu.home>
Message-ID: <20120306203222.GX5050@titan.lakedaemon.net>

On Tue, Mar 06, 2012 at 02:45:23PM -0500, Nicolas Pitre wrote:
> On Tue, 6 Mar 2012, Jason wrote:
> > On Tue, Mar 06, 2012 at 05:17:43PM +0100, Andrew Lunn wrote:
> > > On Tue, Mar 06, 2012 at 10:58:40AM -0500, Jason wrote:
> > > > I'm assuming the driver(s) will increment a reference, so when it
> > > > reaches zero, the framework would call a clk_gate hook.
> > > 
> > > You missed an important point. No driver has claimed these, but u-boot
> > > has turned them on.
> > 
> > This sounds like a bug in u-boot.
> > 
> > > So we want linux to turn off all clocks for which
> > > there is no driver using them, in order to save power.
> > > kirkwood_clk_ctrl is dual purpose. It turns on needed clocks, but it
> > > also turns off unneeded clocks.
> > 
> > This is creating a lot of complexity where the real answer seems to be
> > to get u-boot to shutoff all peripheral clocks before handing over
> > control to linux.
> 
> No.
> 
> Yes, u-Boot might be wrong.  But the kernel should always distrust as 
> much as possible from the bootloader.  Instead of presuming some initial 
> state from the bootloader, it is best to simply set that state up front.

Yes, I clarified this in my response to Andrew:

Wrong is wrong.  if u-boot is enabling things that aren't needed
immediately after handoff, that needs to be fixed.  If the kernel is
depending on that error and not checking the state of the clocks before
performing actions, that also is broken.

> The fewer ties you have with any bootloaders, the fewer bugs you'll have 
> in the end.  Otherwise you might enter into a game of requiring a 
> specific version of a specific bootloader to go with a given kernel, and 
> that is far more complex to deal with than the complexity you are 
> referring to above.

Agreed.

thx,

Jason.


From paul.gortmaker at windriver.com  Tue Mar  6 15:49:38 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Tue,  6 Mar 2012 15:49:38 -0500
Subject: [PATCH v2] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <20120306200156.GA19635@opensource.wolfsonmicro.com>
References: <20120306200156.GA19635@opensource.wolfsonmicro.com>
Message-ID: <1331066978-24774-1-git-send-email-paul.gortmaker@windriver.com>

commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)

  "regulator: Remove support for supplies specified by struct device"

deletes the field from the struct, but this platform was still trying
to set those fields.  Convert them to use the REGULATOR_SUPPLY macro
so as to fix this failure:

arch/arm/mach-pxa/magician.c:581: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/magician.c:581: warning: initialization from incompatible pointer type
arch/arm/mach-pxa/magician.c:585: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/magician.c:585: warning: initialization from incompatible pointer type

arch/arm/mach-pxa/hx4700.c:683: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/hx4700.c:683: warning: initialization from incompatible pointer type
arch/arm/mach-pxa/hx4700.c:687: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/hx4700.c:687: warning: initialization from incompatible pointer type

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
---

[v2: convert to using REGULATOR_SUPPLY instead of just deleting the
 instances of setting the .dev field ]

diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index f2c23ea..53c3366 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -679,14 +679,8 @@ static struct platform_device power_supply = {
  */
 
 static struct regulator_consumer_supply bq24022_consumers[] = {
-	{
-		.dev = &gpio_vbus.dev,
-		.supply = "vbus_draw",
-	},
-	{
-		.dev = &power_supply.dev,
-		.supply = "ac_draw",
-	},
+	REGULATOR_SUPPLY("vbus_draw", "gpio_vbus"),
+	REGULATOR_SUPPLY("ac_draw", "power_supply"),
 };
 
 static struct regulator_init_data bq24022_init_data = {
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 3d6baf9..71a3a3d 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -577,14 +577,8 @@ static struct platform_device power_supply = {
  */
 
 static struct regulator_consumer_supply bq24022_consumers[] = {
-	{
-		.dev = &gpio_vbus.dev,
-		.supply = "vbus_draw",
-	},
-	{
-		.dev = &power_supply.dev,
-		.supply = "ac_draw",
-	},
+	REGULATOR_SUPPLY("vbus_draw", "gpio_vbus"),
+	REGULATOR_SUPPLY("ac_draw", "power_supply"),
 };
 
 static struct regulator_init_data bq24022_init_data = {
-- 
1.7.9.1



From arnd at arndb.de  Tue Mar  6 15:54:55 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 20:54:55 +0000
Subject: Pre-merge-window status of the arm-soc tree
Message-ID: <201203062054.55434.arnd@arndb.de>

This is a summary of what we have today in the arm-soc tree, queued up for
v3.4, as I expect the merge window to open soon. We currently have exactly
50 topic branches merged into the for-next tree, with a total of 331
non-merge changesets. There are a few more pull requests outstanding for
the pxa and exynos platforms.

About half the patches are cleanups and device tree conversion, which
is a good indication that we're making progress there. There also seems
to be an increased interest in ARMv5 and earlier platforms (pxa, at91,
omap1, kirkwood, lpc32xx, sa1100), some of which are now moving over
to device tree probing (at91 rapidly, in fact).

Top contributors so far are:
     27 Nicolas Ferre
     25 Stephen Warren
     25 Jean-Christophe PLAGNIOL-VILLARD
     20 Peter De Schrijver
     19 Tony Lindgren
     17 Ohad Ben-Cohen
     15 Richard Zhao
     14 Fabio Estevam
     10 Benoit Cousson
      9 Roland Stigge

A few things have changed since the last merge window:

* We now have staging branches, to let subarch maintainers get their
patches into arm-soc early on, without having the actual commits
being stable yet. Right now the only one there is the kirkwood/dt
branch from Jason Cooper, but there can be more. These staging
branches will not be sent to Linus during the merge window,
the idea is that they get replaced with a final version that gets
merged into one of the next/* topic branches.

* Russell now has a branch that contains patches from his tree that
directly impact stuff in arm-soc. We had a lot of nasty conflicts
the last time around, which resulted in some of the patches from
arm-soc not making it in during the merge window. Pulling the
rmk/for-armsoc branch into arm-soc hopefully lets us avoid this
situation in the future because we will fix the conflicts much
earlier.

* I have taken the rpmsg branch from Ohad Ben-Cohen into arm-soc.
While this is not strictly what arm-soc is for, a lot of us are
waiting for the branch to get in, and we hope that Linus will take
it from us, while he was cautious the last time when Ohad was sending
it as a new subsystem himself. Merging new subsystems through arm-soc
should not become the norm, but we can do it when it's really needed.

* There is some renewed interest in fixing 'make randconfig'. I
worked on this quite a bit last year but then didn't have the
energy to get all the patches integrated besides doing the
amr-soc maintainance. Russell has gotten more serious about it now,
and a few other people are helping out getting my original patches
integrated. If all goes well, we will soon get to the point where
we can use randconfig builds for automated regression testing and
just refuse to take pull requests into arm-soc if they break builds.

We are mostly converging on a set of topic branches that work for
all platforms, right now we have:

  fixes				bug fixes for 3.3
  next/fixes-non-critical       bug fixes for 3.4
  next/maintainers              updates to MAINTAINERS file
  next/cleanup                  any global cleanups
  next/soc                      soc-wide changes
  next/drivers                  driver related changes
  next/cleanup2                 cleanups depending on the former
  next/dt                       device-tree related changes
  next/boards                   board-specific changes
  next/soc2                     soc-wide changes with other dependencies
  next/rpmsg                    remoteproc and rpmsg
  staging/*			anything that is not quite ready

We can always add more if needed, just be careful not to introduce
any circular dependencies. E.g. today the next/dt branch depends on
patches in the next/drivers branch, so if you want to have other
conflicting patches in both branches, make sure that we can resolve
the branches in a way that lets the driver stuff come first. You will
find a list of the dependencies in the linux-next tree or in
arm-soc/for-next in the arch/arm/arm-soc-for-next-contents.txt file.

The overall changes today are
$ git diff for-next --dirstat=1                                                                                                                                                            
   1.4% Documentation/devicetree/bindings/arm/                                                                                                                                                                     
   4.1% Documentation/                                                                                                                                                                                             
   6.2% arch/arm/boot/dts/                                                                                                                                                                                         
   7.6% arch/arm/mach-at91/include/mach/                                                                                                                                                                           
  15.6% arch/arm/mach-at91/                                                                                                                                                                                        
   1.9% arch/arm/mach-davinci/                                                                                                                                                                                     
   5.6% arch/arm/mach-imx/                                                                                                                                                                                         
   2.2% arch/arm/mach-mxs/                                                                                                                                                                                         
   1.3% arch/arm/mach-omap1/                                                                                                                                                                                       
   3.0% arch/arm/mach-omap2/                                                                                                                                                                                       
   1.0% arch/arm/mach-tegra/include/mach/                                                                                                                                                                          
  17.0% arch/arm/mach-tegra/                                                                                                                                                                                       
   3.9% arch/arm/mach-ux500/                                                                                                                                                                                       
   2.2% arch/arm/mach-vexpress/                                                                                                                                                                                    
   1.9% arch/arm/plat-omap/include/plat/                                                                                                                                                                           
   5.4% arch/arm/                                                                                                                                                                                                  
   8.0% drivers/remoteproc/                                                                                                                                                                                        
   3.6% drivers/rpmsg/                                                                                                                                                                                             
   1.2% drivers/rtc/                                                                                                                                                                                               
   2.8% drivers/
   2.7% include/linux/

Notably absent here are still mach-msm and mach-shmobile and some
platforms have more patches pending. If you have anything that you
want to get included in 3.4, then now would be a good time to send
that. Anything that is not in arm-soc by the time the merge window
opens is not going to make it into the release, and you should allow
a little bit of time to sort out any conflicts between sending pull
requests and having them in the branch.

After Olof has handled the initial merges for v3.4 and I've been busy
doing the same in the last few -rc releases, I'm handing back over
to him now for the next week or two so I can work on some patches
of my own for a while.

	Arnd


From davidb at codeaurora.org  Tue Mar  6 15:59:54 2012
From: davidb at codeaurora.org (David Brown)
Date: Tue, 6 Mar 2012 12:59:54 -0800
Subject: [PATCH v4 3/4] ARM: msm: use runtime ioremap hook
In-Reply-To: <1331006580-3579-3-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331006580-3579-1-git-send-email-robherring2@gmail.com>
 <1331006580-3579-3-git-send-email-robherring2@gmail.com>
Message-ID: <20120306205954.GA21912@codeaurora.org>

On Mon, Mar 05, 2012 at 10:02:59PM -0600, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> Convert msm platforms to use run-time ioremap hook instead of the compile
> time hook.
> 
> According to David Brown, only the msm7201 needed the ioremap hook.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Tested-by: David Brown <davidb at codeaurora.org>
> Acked-by: David Brown <davidb at codeaurora.org>
> Cc: Daniel Walker <dwalker at fifo99.com>
> Cc: Bryan Huntsman <bryanh at codeaurora.org>

This still is working on 8660.

BTW, I'm not able to cleanly apply the IMX patches.  What tree are you
basing that off of?

Thanks,
David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From stigge at antcom.de  Tue Mar  6 16:01:04 2012
From: stigge at antcom.de (Roland Stigge)
Date: Tue,  6 Mar 2012 22:01:04 +0100
Subject: [PATCH v5] lpc32xx: Added ethernet driver
Message-ID: <1331067664-9124-1-git-send-email-stigge@antcom.de>

This patch adds an ethernet driver for the LPC32xx ARM SoC.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Applies to v3.3-rc6

Changes since v4:
 * Removed module parameter (watchdog)
 * Removed "volatile" in DMA descriptors
 * Fixed DMA descriptor and buffer alignment to 16 bytes
 * Fixed arrays of pointers in netdata_local to be pointers to arrays
 * Fixed timing of interrupt enabling upon init
 * Added smp_wmb()
 * Use bool for status_change
 * Don't requeue on tx error (and lockdep doesn't find any further bugs)
 * Removed unnecessary skb_reserve() and (len - 0) style issue
 * Removed setting of last_rx
 * Enable interrupts in lpc_eth_poll(), use __netif_tx_lock/__netif_tx_unlock
 * Disable interrupt unconditionally in __lpc_eth_interrupt()
 * Use WARN in lpc_eth_hard_start_xmit() to make problem more obvious
 * Return NETDEV_TX_BUSY in lpc_eth_hard_start_xmit() on error and
   NETDEV_TX_OK on success
 * Removed setting of trans_start
 * Removed unnecessary / empty lpc_eth_timeout()
 * Fixed error return values of lpc_eth_ethtool_getsettings() and
   lpc_eth_ethtool_setsettings() (-EOPNOTSUPP)
 * Use netif_receive_skb() instead of netif_rx()

 Thanks to Ben Hutchings, Kevin Wells, Russell King and Eric Dumazet for
 reviewing the last version!

 drivers/net/ethernet/Kconfig       |    1 
 drivers/net/ethernet/Makefile      |    1 
 drivers/net/ethernet/nxp/Kconfig   |    8 
 drivers/net/ethernet/nxp/Makefile  |    1 
 drivers/net/ethernet/nxp/lpc_eth.c | 1611 +++++++++++++++++++++++++++++++++++++
 5 files changed, 1622 insertions(+)

--- linux-2.6.orig/drivers/net/ethernet/Kconfig
+++ linux-2.6/drivers/net/ethernet/Kconfig
@@ -126,6 +126,7 @@ config NET_NETX
 
 source "drivers/net/ethernet/nuvoton/Kconfig"
 source "drivers/net/ethernet/nvidia/Kconfig"
+source "drivers/net/ethernet/nxp/Kconfig"
 source "drivers/net/ethernet/octeon/Kconfig"
 source "drivers/net/ethernet/oki-semi/Kconfig"
 
--- linux-2.6.orig/drivers/net/ethernet/Makefile
+++ linux-2.6/drivers/net/ethernet/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_NET_VENDOR_NATSEMI) += nats
 obj-$(CONFIG_NET_NETX) += netx-eth.o
 obj-$(CONFIG_NET_VENDOR_NUVOTON) += nuvoton/
 obj-$(CONFIG_NET_VENDOR_NVIDIA) += nvidia/
+obj-$(CONFIG_LPC_ENET) += nxp/
 obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon/
 obj-$(CONFIG_NET_VENDOR_OKI) += oki-semi/
 obj-$(CONFIG_ETHOC) += ethoc.o
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/Kconfig
@@ -0,0 +1,8 @@
+config LPC_ENET
+        tristate "NXP ethernet MAC on LPC devices"
+        depends on ARCH_LPC32XX
+        select PHYLIB
+        help
+	  Say Y or M here if you want to use the NXP ethernet MAC included on
+	  some NXP LPC devices. You can safely enable this option for LPC32xx
+	  SoC. Also available as a module.
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_LPC_ENET) += lpc_eth.o
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/lpc_eth.c
@@ -0,0 +1,1611 @@
+/*
+ * drivers/net/ethernet/nxp/lpc_eth.c
+ *
+ * Author: Kevin Wells <kevin.wells at nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ * Copyright (C) 2012 Roland Stigge <stigge at antcom.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/crc32.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/clk.h>
+#include <linux/workqueue.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/phy.h>
+#include <linux/dma-mapping.h>
+#include <linux/of_net.h>
+#include <linux/types.h>
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <mach/board.h>
+#include <mach/platform.h>
+#include <mach/hardware.h>
+
+#define MODNAME "lpc-eth"
+#define DRV_VERSION "1.00"
+#define PHYDEF_ADDR 0x00
+
+#define ENET_MAXF_SIZE 1536
+#define ENET_RX_DESC 48
+#define ENET_TX_DESC 16
+
+#define NAPI_WEIGHT 16
+
+/*
+ * Ethernet MAC controller Register offsets
+ */
+#define LPC_ENET_MAC1(x)			(x + 0x000)
+#define LPC_ENET_MAC2(x)			(x + 0x004)
+#define LPC_ENET_IPGT(x)			(x + 0x008)
+#define LPC_ENET_IPGR(x)			(x + 0x00C)
+#define LPC_ENET_CLRT(x)			(x + 0x010)
+#define LPC_ENET_MAXF(x)			(x + 0x014)
+#define LPC_ENET_SUPP(x)			(x + 0x018)
+#define LPC_ENET_TEST(x)			(x + 0x01C)
+#define LPC_ENET_MCFG(x)			(x + 0x020)
+#define LPC_ENET_MCMD(x)			(x + 0x024)
+#define LPC_ENET_MADR(x)			(x + 0x028)
+#define LPC_ENET_MWTD(x)			(x + 0x02C)
+#define LPC_ENET_MRDD(x)			(x + 0x030)
+#define LPC_ENET_MIND(x)			(x + 0x034)
+#define LPC_ENET_SA0(x)				(x + 0x040)
+#define LPC_ENET_SA1(x)				(x + 0x044)
+#define LPC_ENET_SA2(x)				(x + 0x048)
+#define LPC_ENET_COMMAND(x)			(x + 0x100)
+#define LPC_ENET_STATUS(x)			(x + 0x104)
+#define LPC_ENET_RXDESCRIPTOR(x)		(x + 0x108)
+#define LPC_ENET_RXSTATUS(x)			(x + 0x10C)
+#define LPC_ENET_RXDESCRIPTORNUMBER(x)		(x + 0x110)
+#define LPC_ENET_RXPRODUCEINDEX(x)		(x + 0x114)
+#define LPC_ENET_RXCONSUMEINDEX(x)		(x + 0x118)
+#define LPC_ENET_TXDESCRIPTOR(x)		(x + 0x11C)
+#define LPC_ENET_TXSTATUS(x)			(x + 0x120)
+#define LPC_ENET_TXDESCRIPTORNUMBER(x)		(x + 0x124)
+#define LPC_ENET_TXPRODUCEINDEX(x)		(x + 0x128)
+#define LPC_ENET_TXCONSUMEINDEX(x)		(x + 0x12C)
+#define LPC_ENET_TSV0(x)			(x + 0x158)
+#define LPC_ENET_TSV1(x)			(x + 0x15C)
+#define LPC_ENET_RSV(x)				(x + 0x160)
+#define LPC_ENET_FLOWCONTROLCOUNTER(x)		(x + 0x170)
+#define LPC_ENET_FLOWCONTROLSTATUS(x)		(x + 0x174)
+#define LPC_ENET_RXFILTER_CTRL(x)		(x + 0x200)
+#define LPC_ENET_RXFILTERWOLSTATUS(x)		(x + 0x204)
+#define LPC_ENET_RXFILTERWOLCLEAR(x)		(x + 0x208)
+#define LPC_ENET_HASHFILTERL(x)			(x + 0x210)
+#define LPC_ENET_HASHFILTERH(x)			(x + 0x214)
+#define LPC_ENET_INTSTATUS(x)			(x + 0xFE0)
+#define LPC_ENET_INTENABLE(x)			(x + 0xFE4)
+#define LPC_ENET_INTCLEAR(x)			(x + 0xFE8)
+#define LPC_ENET_INTSET(x)			(x + 0xFEC)
+#define LPC_ENET_POWERDOWN(x)			(x + 0xFF4)
+
+/*
+ * mac1 register definitions
+ */
+#define LPC_MAC1_RECV_ENABLE			(1 << 0)
+#define LPC_MAC1_PASS_ALL_RX_FRAMES		(1 << 1)
+#define LPC_MAC1_RX_FLOW_CONTROL		(1 << 2)
+#define LPC_MAC1_TX_FLOW_CONTROL		(1 << 3)
+#define LPC_MAC1_LOOPBACK			(1 << 4)
+#define LPC_MAC1_RESET_TX			(1 << 8)
+#define LPC_MAC1_RESET_MCS_TX			(1 << 9)
+#define LPC_MAC1_RESET_RX			(1 << 10)
+#define LPC_MAC1_RESET_MCS_RX			(1 << 11)
+#define LPC_MAC1_SIMULATION_RESET		(1 << 14)
+#define LPC_MAC1_SOFT_RESET			(1 << 15)
+
+/*
+ * mac2 register definitions
+ */
+#define LPC_MAC2_FULL_DUPLEX			(1 << 0)
+#define LPC_MAC2_FRAME_LENGTH_CHECKING		(1 << 1)
+#define LPC_MAC2_HUGH_LENGTH_CHECKING		(1 << 2)
+#define LPC_MAC2_DELAYED_CRC			(1 << 3)
+#define LPC_MAC2_CRC_ENABLE			(1 << 4)
+#define LPC_MAC2_PAD_CRC_ENABLE			(1 << 5)
+#define LPC_MAC2_VLAN_PAD_ENABLE		(1 << 6)
+#define LPC_MAC2_AUTO_DETECT_PAD_ENABLE		(1 << 7)
+#define LPC_MAC2_PURE_PREAMBLE_ENFORCEMENT	(1 << 8)
+#define LPC_MAC2_LONG_PREAMBLE_ENFORCEMENT	(1 << 9)
+#define LPC_MAC2_NO_BACKOFF			(1 << 12)
+#define LPC_MAC2_BACK_PRESSURE			(1 << 13)
+#define LPC_MAC2_EXCESS_DEFER			(1 << 14)
+
+/*
+ * ipgt register definitions
+ */
+#define LPC_IPGT_LOAD(n)			((n) & 0x7F)
+
+/*
+ * ipgr register definitions
+ */
+#define LPC_IPGR_LOAD_PART2(n)			((n) & 0x7F)
+#define LPC_IPGR_LOAD_PART1(n)			(((n) & 0x7F) << 8)
+
+/*
+ * clrt register definitions
+ */
+#define LPC_CLRT_LOAD_RETRY_MAX(n)		((n) & 0xF)
+#define LPC_CLRT_LOAD_COLLISION_WINDOW(n)	(((n) & 0x3F) << 8)
+
+/*
+ * maxf register definitions
+ */
+#define LPC_MAXF_LOAD_MAX_FRAME_LEN(n)		((n) & 0xFFFF)
+
+/*
+ * supp register definitions
+ */
+#define LPC_SUPP_SPEED				(1 << 8)
+#define LPC_SUPP_RESET_RMII			(1 << 11)
+
+/*
+ * test register definitions
+ */
+#define LPC_TEST_SHORTCUT_PAUSE_QUANTA		(1 << 0)
+#define LPC_TEST_PAUSE				(1 << 1)
+#define LPC_TEST_BACKPRESSURE			(1 << 2)
+
+/*
+ * mcfg register definitions
+ */
+#define LPC_MCFG_SCAN_INCREMENT			(1 << 0)
+#define LPC_MCFG_SUPPRESS_PREAMBLE		(1 << 1)
+#define LPC_MCFG_CLOCK_SELECT(n)		(((n) & 0x7) << 2)
+#define LPC_MCFG_CLOCK_HOST_DIV_4		0
+#define LPC_MCFG_CLOCK_HOST_DIV_6		2
+#define LPC_MCFG_CLOCK_HOST_DIV_8		3
+#define LPC_MCFG_CLOCK_HOST_DIV_10		4
+#define LPC_MCFG_CLOCK_HOST_DIV_14		5
+#define LPC_MCFG_CLOCK_HOST_DIV_20		6
+#define LPC_MCFG_CLOCK_HOST_DIV_28		7
+#define LPC_MCFG_RESET_MII_MGMT			(1 << 15)
+
+/*
+ * mcmd register definitions
+ */
+#define LPC_MCMD_READ				(1 << 0)
+#define LPC_MCMD_SCAN				(1 << 1)
+
+/*
+ * madr register definitions
+ */
+#define LPC_MADR_REGISTER_ADDRESS(n)		((n) & 0x1F)
+#define LPC_MADR_PHY_0ADDRESS(n)		(((n) & 0x1F) << 8)
+
+/*
+ * mwtd register definitions
+ */
+#define LPC_MWDT_WRITE(n)			((n) & 0xFFFF)
+
+/*
+ * mrdd register definitions
+ */
+#define LPC_MRDD_READ_MASK			0xFFFF
+
+/*
+ * mind register definitions
+ */
+#define LPC_MIND_BUSY				(1 << 0)
+#define LPC_MIND_SCANNING			(1 << 1)
+#define LPC_MIND_NOT_VALID			(1 << 2)
+#define LPC_MIND_MII_LINK_FAIL			(1 << 3)
+
+/*
+ * command register definitions
+ */
+#define LPC_COMMAND_RXENABLE			(1 << 0)
+#define LPC_COMMAND_TXENABLE			(1 << 1)
+#define LPC_COMMAND_REG_RESET			(1 << 3)
+#define LPC_COMMAND_TXRESET			(1 << 4)
+#define LPC_COMMAND_RXRESET			(1 << 5)
+#define LPC_COMMAND_PASSRUNTFRAME		(1 << 6)
+#define LPC_COMMAND_PASSRXFILTER		(1 << 7)
+#define LPC_COMMAND_TXFLOWCONTROL		(1 << 8)
+#define LPC_COMMAND_RMII			(1 << 9)
+#define LPC_COMMAND_FULLDUPLEX			(1 << 10)
+
+/*
+ * status register definitions
+ */
+#define LPC_STATUS_RXACTIVE			(1 << 0)
+#define LPC_STATUS_TXACTIVE			(1 << 1)
+
+/*
+ * tsv0 register definitions
+ */
+#define LPC_TSV0_CRC_ERROR			(1 << 0)
+#define LPC_TSV0_LENGTH_CHECK_ERROR		(1 << 1)
+#define LPC_TSV0_LENGTH_OUT_OF_RANGE		(1 << 2)
+#define LPC_TSV0_DONE				(1 << 3)
+#define LPC_TSV0_MULTICAST			(1 << 4)
+#define LPC_TSV0_BROADCAST			(1 << 5)
+#define LPC_TSV0_PACKET_DEFER			(1 << 6)
+#define LPC_TSV0_ESCESSIVE_DEFER		(1 << 7)
+#define LPC_TSV0_ESCESSIVE_COLLISION		(1 << 8)
+#define LPC_TSV0_LATE_COLLISION			(1 << 9)
+#define LPC_TSV0_GIANT				(1 << 10)
+#define LPC_TSV0_UNDERRUN			(1 << 11)
+#define LPC_TSV0_TOTAL_BYTES(n)			(((n) >> 12) & 0xFFFF)
+#define LPC_TSV0_CONTROL_FRAME			(1 << 28)
+#define LPC_TSV0_PAUSE				(1 << 29)
+#define LPC_TSV0_BACKPRESSURE			(1 << 30)
+#define LPC_TSV0_VLAN				(1 << 31)
+
+/*
+ * tsv1 register definitions
+ */
+#define LPC_TSV1_TRANSMIT_BYTE_COUNT(n)		((n) & 0xFFFF)
+#define LPC_TSV1_COLLISION_COUNT(n)		(((n) >> 16) & 0xF)
+
+/*
+ * rsv register definitions
+ */
+#define LPC_RSV_RECEIVED_BYTE_COUNT(n)		((n) & 0xFFFF)
+#define LPC_RSV_RXDV_EVENT_IGNORED		(1 << 16)
+#define LPC_RSV_RXDV_EVENT_PREVIOUSLY_SEEN	(1 << 17)
+#define LPC_RSV_CARRIER_EVNT_PREVIOUS_SEEN	(1 << 18)
+#define LPC_RSV_RECEIVE_CODE_VIOLATION		(1 << 19)
+#define LPC_RSV_CRC_ERROR			(1 << 20)
+#define LPC_RSV_LENGTH_CHECK_ERROR		(1 << 21)
+#define LPC_RSV_LENGTH_OUT_OF_RANGE		(1 << 22)
+#define LPC_RSV_RECEIVE_OK			(1 << 23)
+#define LPC_RSV_MULTICAST			(1 << 24)
+#define LPC_RSV_BROADCAST			(1 << 25)
+#define LPC_RSV_DRIBBLE_NIBBLE			(1 << 26)
+#define LPC_RSV_CONTROL_FRAME			(1 << 27)
+#define LPC_RSV_PAUSE				(1 << 28)
+#define LPC_RSV_UNSUPPORTED_OPCODE		(1 << 29)
+#define LPC_RSV_VLAN				(1 << 30)
+
+/*
+ * flowcontrolcounter register definitions
+ */
+#define LPC_FCCR_MIRRORCOUNTER(n)		((n) & 0xFFFF)
+#define LPC_FCCR_PAUSETIMER(n)			(((n) >> 16) & 0xFFFF)
+
+/*
+ * flowcontrolstatus register definitions
+ */
+#define LPC_FCCR_MIRRORCOUNTERCURRENT(n)	((n) & 0xFFFF)
+
+/*
+ * rxfliterctrl, rxfilterwolstatus, and rxfilterwolclear shared
+ * register definitions
+ */
+#define LPC_RXFLTRW_ACCEPTUNICAST		(1 << 0)
+#define LPC_RXFLTRW_ACCEPTUBROADCAST		(1 << 1)
+#define LPC_RXFLTRW_ACCEPTUMULTICAST		(1 << 2)
+#define LPC_RXFLTRW_ACCEPTUNICASTHASH		(1 << 3)
+#define LPC_RXFLTRW_ACCEPTUMULTICASTHASH	(1 << 4)
+#define LPC_RXFLTRW_ACCEPTPERFECT		(1 << 5)
+
+/*
+ * rxfliterctrl register definitions
+ */
+#define LPC_RXFLTRWSTS_MAGICPACKETENWOL		(1 << 12)
+#define LPC_RXFLTRWSTS_RXFILTERENWOL		(1 << 13)
+
+/*
+ * rxfilterwolstatus/rxfilterwolclear register definitions
+ */
+#define LPC_RXFLTRWSTS_RXFILTERWOL		(1 << 7)
+#define LPC_RXFLTRWSTS_MAGICPACKETWOL		(1 << 8)
+
+/*
+ * intstatus, intenable, intclear, and Intset shared register
+ * definitions
+ */
+#define LPC_MACINT_RXOVERRUNINTEN		(1 << 0)
+#define LPC_MACINT_RXERRORONINT			(1 << 1)
+#define LPC_MACINT_RXFINISHEDINTEN		(1 << 2)
+#define LPC_MACINT_RXDONEINTEN			(1 << 3)
+#define LPC_MACINT_TXUNDERRUNINTEN		(1 << 4)
+#define LPC_MACINT_TXERRORINTEN			(1 << 5)
+#define LPC_MACINT_TXFINISHEDINTEN		(1 << 6)
+#define LPC_MACINT_TXDONEINTEN			(1 << 7)
+#define LPC_MACINT_SOFTINTEN			(1 << 12)
+#define LPC_MACINT_WAKEUPINTEN			(1 << 13)
+
+/*
+ * powerdown register definitions
+ */
+#define LPC_POWERDOWN_MACAHB			(1 << 31)
+
+static inline phy_interface_t lpc_phy_interface_mode(void)
+{
+#ifdef CONFIG_ARCH_LPC32XX_MII_SUPPORT
+	return PHY_INTERFACE_MODE_MII;
+#else
+	return PHY_INTERFACE_MODE_RMII;
+#endif
+}
+
+static inline int use_iram_for_net(void)
+{
+#ifdef CONFIG_ARCH_LPC32XX_IRAM_FOR_NET
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+/* Receive Status information word */
+#define RXSTATUS_SIZE			0x000007FF
+#define RXSTATUS_CONTROL		(1 << 18)
+#define RXSTATUS_VLAN			(1 << 19)
+#define RXSTATUS_FILTER			(1 << 20)
+#define RXSTATUS_MULTICAST		(1 << 21)
+#define RXSTATUS_BROADCAST		(1 << 22)
+#define RXSTATUS_CRC			(1 << 23)
+#define RXSTATUS_SYMBOL			(1 << 24)
+#define RXSTATUS_LENGTH			(1 << 25)
+#define RXSTATUS_RANGE			(1 << 26)
+#define RXSTATUS_ALIGN			(1 << 27)
+#define RXSTATUS_OVERRUN		(1 << 28)
+#define RXSTATUS_NODESC			(1 << 29)
+#define RXSTATUS_LAST			(1 << 30)
+#define RXSTATUS_ERROR			(1 << 31)
+
+#define RXSTATUS_STATUS_ERROR \
+	(RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | RXSTATUS_RANGE \
+	 | RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC)
+
+/* Receive Descriptor control word */
+#define RXDESC_CONTROL_SIZE		0x000007FF
+#define RXDESC_CONTROL_INT		(1 << 31)
+
+/* Transmit Status information word */
+#define TXSTATUS_COLLISIONS_GET(x)	(((x) >> 21) & 0xF)
+#define TXSTATUS_DEFER			(1 << 25)
+#define TXSTATUS_EXCESSDEFER		(1 << 26)
+#define TXSTATUS_EXCESSCOLL		(1 << 27)
+#define TXSTATUS_LATECOLL		(1 << 28)
+#define TXSTATUS_UNDERRUN		(1 << 29)
+#define TXSTATUS_NODESC			(1 << 30)
+#define TXSTATUS_ERROR			(1 << 31)
+
+/* Transmit Descriptor control word */
+#define TXDESC_CONTROL_SIZE		0x000007FF
+#define TXDESC_CONTROL_OVERRIDE		(1 << 26)
+#define TXDESC_CONTROL_HUGE		(1 << 27)
+#define TXDESC_CONTROL_PAD		(1 << 28)
+#define TXDESC_CONTROL_CRC		(1 << 29)
+#define TXDESC_CONTROL_LAST		(1 << 30)
+#define TXDESC_CONTROL_INT		(1 << 31)
+
+static int lpc_eth_hard_start_xmit(struct sk_buff *skb,
+	struct net_device *ndev);
+
+/*
+ * Structure of a TX/RX descriptors and RX status
+ */
+struct txrx_desc_t {
+	u32 packet;
+	u32 control;
+};
+struct rx_status_t {
+	u32 statusinfo;
+	u32 statushashcrc;
+};
+
+/*
+ * Device driver data structure
+ */
+struct netdata_local {
+	struct platform_device	*pdev;
+	struct net_device	*ndev;
+	spinlock_t		lock;
+	void __iomem		*net_base;
+	u32			msg_enable;
+	struct sk_buff		*skb[ENET_TX_DESC];
+	unsigned int		last_tx_idx;
+	unsigned int		num_used_tx_buffs;
+	struct mii_bus		*mii_bus;
+	struct phy_device	*phy_dev;
+	struct clk		*clk;
+	dma_addr_t		dma_buff_base_p;
+	void			*dma_buff_base_v;
+	size_t			dma_buff_size;
+	struct txrx_desc_t	*tx_desc_v;
+	u32			*tx_stat_v;
+	void			*tx_buff_v;
+	struct txrx_desc_t	*rx_desc_v;
+	struct rx_status_t	*rx_stat_v;
+	void			*rx_buff_v;
+	int			link;
+	int			speed;
+	int			duplex;
+	struct napi_struct	napi;
+};
+
+/*
+ * MAC support functions
+ */
+static void __lpc_set_mac(struct netdata_local *pldat, u8 *mac)
+{
+	u32 tmp;
+
+	/* Set station address */
+	tmp = mac[0] | ((u32)mac[1] << 8);
+	writel(tmp, LPC_ENET_SA2(pldat->net_base));
+	tmp = mac[2] | ((u32)mac[3] << 8);
+	writel(tmp, LPC_ENET_SA1(pldat->net_base));
+	tmp = mac[4] | ((u32)mac[5] << 8);
+	writel(tmp, LPC_ENET_SA0(pldat->net_base));
+
+	netdev_dbg(pldat->ndev, "Ethernet MAC address %pM\n", mac);
+}
+
+static void __lpc_get_mac(struct netdata_local *pldat, u8 *mac)
+{
+	u32 tmp;
+
+	/* Get station address */
+	tmp = readl(LPC_ENET_SA2(pldat->net_base));
+	mac[0] = tmp & 0xFF;
+	mac[1] = tmp >> 8;
+	tmp = readl(LPC_ENET_SA1(pldat->net_base));
+	mac[2] = tmp & 0xFF;
+	mac[3] = tmp >> 8;
+	tmp = readl(LPC_ENET_SA0(pldat->net_base));
+	mac[4] = tmp & 0xFF;
+	mac[5] = tmp >> 8;
+}
+
+static void __lpc_eth_clock_enable(struct netdata_local *pldat,
+	int enable)
+{
+	if (enable)
+		clk_enable(pldat->clk);
+	else
+		clk_disable(pldat->clk);
+}
+
+static void __lpc_params_setup(struct netdata_local *pldat)
+{
+	u32 tmp;
+
+	if (pldat->duplex == DUPLEX_FULL) {
+		tmp = readl(LPC_ENET_MAC2(pldat->net_base));
+		tmp |= LPC_MAC2_FULL_DUPLEX;
+		writel(tmp, LPC_ENET_MAC2(pldat->net_base));
+		tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+		tmp |= LPC_COMMAND_FULLDUPLEX;
+		writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base));
+	} else {
+		tmp = readl(LPC_ENET_MAC2(pldat->net_base));
+		tmp &= ~LPC_MAC2_FULL_DUPLEX;
+		writel(tmp, LPC_ENET_MAC2(pldat->net_base));
+		tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+		tmp &= ~LPC_COMMAND_FULLDUPLEX;
+		writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base));
+	}
+
+	if (pldat->speed == SPEED_100)
+		writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base));
+	else
+		writel(0, LPC_ENET_SUPP(pldat->net_base));
+}
+
+static void __lpc_eth_reset(struct netdata_local *pldat)
+{
+	/* Reset all MAC logic */
+	writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX |
+		LPC_MAC1_RESET_MCS_RX | LPC_MAC1_SIMULATION_RESET |
+		LPC_MAC1_SOFT_RESET), LPC_ENET_MAC1(pldat->net_base));
+	writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET |
+		LPC_COMMAND_RXRESET), LPC_ENET_COMMAND(pldat->net_base));
+}
+
+static int __lpc_mii_mngt_reset(struct netdata_local *pldat)
+{
+	/* Reset MII management hardware */
+	writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base));
+
+	/* Setup MII clock to slowest rate with a /28 divider */
+	writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28),
+		LPC_ENET_MCFG(pldat->net_base));
+
+	return 0;
+}
+
+static inline phys_addr_t __va_to_pa(void *addr, struct netdata_local *pldat)
+{
+	phys_addr_t phaddr;
+
+	phaddr = addr - pldat->dma_buff_base_v;
+	phaddr += pldat->dma_buff_base_p;
+
+	return phaddr;
+}
+
+static void lpc_eth_enable_int(void __iomem *regbase)
+{
+	writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN),
+		LPC_ENET_INTENABLE(regbase));
+}
+
+static void lpc_eth_disable_int(void __iomem *regbase)
+{
+	writel(0, LPC_ENET_INTENABLE(regbase));
+}
+
+/* Setup TX/RX descriptors */
+static void __lpc_txrx_desc_setup(struct netdata_local *pldat)
+{
+	u32 *ptxstat;
+	void *tbuff;
+	int i;
+	struct txrx_desc_t *ptxrxdesc;
+	struct rx_status_t *prxstat;
+
+	tbuff = PTR_ALIGN(pldat->dma_buff_base_v, 16);
+
+	/* Setup TX descriptors, status, and buffers */
+	pldat->tx_desc_v = tbuff;
+	tbuff += sizeof(struct txrx_desc_t) * ENET_TX_DESC;
+
+	pldat->tx_stat_v = tbuff;
+	tbuff += sizeof(u32) * ENET_TX_DESC;
+
+	tbuff = PTR_ALIGN(tbuff, 16);
+	pldat->tx_buff_v = tbuff;
+	tbuff += ENET_MAXF_SIZE * ENET_TX_DESC;
+
+	/* Setup RX descriptors, status, and buffers */
+	pldat->rx_desc_v = tbuff;
+	tbuff += sizeof(struct txrx_desc_t) * ENET_RX_DESC;
+
+	tbuff = PTR_ALIGN(tbuff, 16);
+	pldat->rx_stat_v = tbuff;
+	tbuff += sizeof(struct rx_status_t) * ENET_RX_DESC;
+
+	tbuff = PTR_ALIGN(tbuff, 16);
+	pldat->rx_buff_v = tbuff;
+	tbuff += ENET_MAXF_SIZE * ENET_RX_DESC;
+
+	/* Map the TX descriptors to the TX buffers in hardware */
+	for (i = 0; i < ENET_TX_DESC; i++) {
+		ptxstat = &pldat->tx_stat_v[i];
+		ptxrxdesc = &pldat->tx_desc_v[i];
+
+		ptxrxdesc->packet = __va_to_pa(
+				pldat->tx_buff_v + i * ENET_MAXF_SIZE, pldat);
+		ptxrxdesc->control = 0;
+		*ptxstat = 0;
+	}
+
+	/* Map the RX descriptors to the RX buffers in hardware */
+	for (i = 0; i < ENET_RX_DESC; i++) {
+		prxstat = &pldat->rx_stat_v[i];
+		ptxrxdesc = &pldat->rx_desc_v[i];
+
+		ptxrxdesc->packet = __va_to_pa(
+				pldat->rx_buff_v + i * ENET_MAXF_SIZE, pldat);
+		ptxrxdesc->control = RXDESC_CONTROL_INT | (ENET_MAXF_SIZE - 1);
+		prxstat->statusinfo = 0;
+		prxstat->statushashcrc = 0;
+	}
+
+	/* Setup base addresses in hardware to point to buffers and
+	   descriptors */
+	writel((ENET_TX_DESC - 1),
+		LPC_ENET_TXDESCRIPTORNUMBER(pldat->net_base));
+	writel(__va_to_pa(pldat->tx_desc_v, pldat),
+		LPC_ENET_TXDESCRIPTOR(pldat->net_base));
+	writel(__va_to_pa(pldat->tx_stat_v, pldat),
+		LPC_ENET_TXSTATUS(pldat->net_base));
+	writel((ENET_RX_DESC - 1),
+		LPC_ENET_RXDESCRIPTORNUMBER(pldat->net_base));
+	writel(__va_to_pa(pldat->rx_desc_v, pldat),
+		LPC_ENET_RXDESCRIPTOR(pldat->net_base));
+	writel(__va_to_pa(pldat->rx_stat_v, pldat),
+		LPC_ENET_RXSTATUS(pldat->net_base));
+}
+
+static void __lpc_eth_init(struct netdata_local *pldat)
+{
+	u32 tmp;
+
+	/* Disable controller and reset */
+	tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+	tmp &= ~LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
+	writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+	tmp = readl(LPC_ENET_MAC1(pldat->net_base));
+	tmp &= ~LPC_MAC1_RECV_ENABLE;
+	writel(tmp, LPC_ENET_MAC1(pldat->net_base));
+
+	/* Initial MAC setup */
+	writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base));
+	writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE),
+		LPC_ENET_MAC2(pldat->net_base));
+	writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base));
+
+	/* Collision window, gap */
+	writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) |
+		LPC_CLRT_LOAD_COLLISION_WINDOW(0x37)),
+		LPC_ENET_CLRT(pldat->net_base));
+	writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base));
+
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		writel(LPC_COMMAND_PASSRUNTFRAME,
+			LPC_ENET_COMMAND(pldat->net_base));
+	else {
+		writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
+			LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
+	}
+
+	__lpc_params_setup(pldat);
+
+	/* Setup TX and RX descriptors */
+	__lpc_txrx_desc_setup(pldat);
+
+	/* Setup packet filtering */
+	writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT),
+		LPC_ENET_RXFILTER_CTRL(pldat->net_base));
+
+	/* Get the next TX buffer output index */
+	pldat->num_used_tx_buffs = 0;
+	pldat->last_tx_idx =
+		readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+
+	/* Clear and enable interrupts */
+	writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
+	smp_wmb();
+	lpc_eth_enable_int(pldat->net_base);
+
+	/* Enable controller */
+	tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+	tmp |= LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
+	writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+	tmp = readl(LPC_ENET_MAC1(pldat->net_base));
+	tmp |= LPC_MAC1_RECV_ENABLE;
+	writel(tmp, LPC_ENET_MAC1(pldat->net_base));
+}
+
+static void __lpc_eth_shutdown(struct netdata_local *pldat)
+{
+	/* Reset ethernet and power down PHY */
+	__lpc_eth_reset(pldat);
+	writel(0, LPC_ENET_MAC1(pldat->net_base));
+	writel(0, LPC_ENET_MAC2(pldat->net_base));
+}
+
+/*
+ * MAC<--->PHY support functions
+ */
+static int lpc_mdio_read(struct mii_bus *bus, int phy_id, int phyreg)
+{
+	struct netdata_local *pldat = bus->priv;
+	unsigned long timeout = jiffies + msecs_to_jiffies(100);
+	int lps;
+
+	writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
+	writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base));
+
+	/* Wait for unbusy status */
+	while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
+		if (time_after(jiffies, timeout))
+			return -EIO;
+		cpu_relax();
+	}
+
+	lps = readl(LPC_ENET_MRDD(pldat->net_base));
+	writel(0, LPC_ENET_MCMD(pldat->net_base));
+
+	return lps;
+}
+
+static int lpc_mdio_write(struct mii_bus *bus, int phy_id, int phyreg,
+			u16 phydata)
+{
+	struct netdata_local *pldat = bus->priv;
+	unsigned long timeout = jiffies + msecs_to_jiffies(100);
+
+	writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
+	writel(phydata, LPC_ENET_MWTD(pldat->net_base));
+
+	/* Wait for completion */
+	while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
+		if (time_after(jiffies, timeout))
+			return -EIO;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int lpc_mdio_reset(struct mii_bus *bus)
+{
+	return __lpc_mii_mngt_reset((struct netdata_local *)bus->priv);
+}
+
+static void lpc_handle_link_change(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+	unsigned long flags;
+
+	bool status_change = false;
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	if (phydev->link) {
+		if ((pldat->speed != phydev->speed) ||
+		    (pldat->duplex != phydev->duplex)) {
+			pldat->speed = phydev->speed;
+			pldat->duplex = phydev->duplex;
+			status_change = true;
+		}
+	}
+
+	if (phydev->link != pldat->link) {
+		if (!phydev->link) {
+			pldat->speed = 0;
+			pldat->duplex = -1;
+		}
+		pldat->link = phydev->link;
+
+		status_change = true;
+	}
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	if (status_change)
+		__lpc_params_setup(pldat);
+}
+
+static int lpc_mii_probe(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = NULL;
+	int phy_addr;
+
+	/* find the first phy */
+	for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
+		if (pldat->mii_bus->phy_map[phy_addr]) {
+			phydev = pldat->mii_bus->phy_map[phy_addr];
+			break;
+		}
+	}
+
+	if (!phydev) {
+		netdev_err(ndev, "no PHY found\n");
+		return -ENODEV;
+	}
+
+	/* Attach to the PHY */
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		netdev_info(ndev, "using MII interface\n");
+	else
+		netdev_info(ndev, "using RMII interface\n");
+	phydev = phy_connect(ndev, dev_name(&phydev->dev),
+		&lpc_handle_link_change, 0, lpc_phy_interface_mode());
+
+	if (IS_ERR(phydev)) {
+		netdev_err(ndev, "Could not attach to PHY\n");
+		return PTR_ERR(phydev);
+	}
+
+	/* mask with MAC supported features */
+	phydev->supported &= PHY_BASIC_FEATURES;
+
+	phydev->advertising = phydev->supported;
+
+	pldat->link = 0;
+	pldat->speed = 0;
+	pldat->duplex = -1;
+	pldat->phy_dev = phydev;
+
+	return 0;
+}
+
+static int lpc_mii_init(struct netdata_local *pldat)
+{
+	int err = -ENXIO, i;
+
+	pldat->mii_bus = mdiobus_alloc();
+	if (!pldat->mii_bus) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	/* Setup MII mode */
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		writel(LPC_COMMAND_PASSRUNTFRAME,
+			LPC_ENET_COMMAND(pldat->net_base));
+	else {
+		writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
+			LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
+	}
+
+	pldat->mii_bus->name = "lpc_mii_bus";
+	pldat->mii_bus->read = &lpc_mdio_read;
+	pldat->mii_bus->write = &lpc_mdio_write;
+	pldat->mii_bus->reset = &lpc_mdio_reset;
+	snprintf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%x", pldat->pdev->id);
+	pldat->mii_bus->priv = pldat;
+	pldat->mii_bus->parent = &pldat->pdev->dev;
+	pldat->mii_bus->phy_mask = 0xFFFFFFF0;
+
+	pldat->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!pldat->mii_bus->irq) {
+		err = -ENOMEM;
+		goto err_out_1;
+	}
+
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		pldat->mii_bus->irq[i] = PHY_POLL;
+
+	platform_set_drvdata(pldat->pdev, pldat->mii_bus);
+
+	if (mdiobus_register(pldat->mii_bus))
+		goto err_out_free_mdio_irq;
+
+	if (lpc_mii_probe(pldat->ndev) != 0)
+		goto err_out_unregister_bus;
+
+	return 0;
+
+err_out_unregister_bus:
+	mdiobus_unregister(pldat->mii_bus);
+err_out_free_mdio_irq:
+	kfree(pldat->mii_bus->irq);
+err_out_1:
+	mdiobus_free(pldat->mii_bus);
+err_out:
+	return err;
+}
+
+static void __lpc_handle_xmit(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct sk_buff *skb;
+	u32 txcidx, *ptxstat, txstat;
+
+	txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+	while (pldat->last_tx_idx != txcidx) {
+		skb = pldat->skb[pldat->last_tx_idx];
+
+		/* A buffer is available, get buffer status */
+		ptxstat = &pldat->tx_stat_v[pldat->last_tx_idx];
+		txstat = *ptxstat;
+
+		/* Next buffer and decrement used buffer counter */
+		pldat->num_used_tx_buffs--;
+		pldat->last_tx_idx++;
+		if (pldat->last_tx_idx >= ENET_TX_DESC)
+			pldat->last_tx_idx = 0;
+
+		/* Update collision counter */
+		ndev->stats.collisions += TXSTATUS_COLLISIONS_GET(txstat);
+
+		/* Any errors occurred? */
+		if (txstat & TXSTATUS_ERROR) {
+			if (txstat & TXSTATUS_UNDERRUN) {
+				/* FIFO underrun */
+				ndev->stats.tx_fifo_errors++;
+			}
+			if (txstat & TXSTATUS_LATECOLL) {
+				/* Late collision */
+				ndev->stats.tx_aborted_errors++;
+			}
+			if (txstat & TXSTATUS_EXCESSCOLL) {
+				/* Excessive collision */
+				ndev->stats.tx_aborted_errors++;
+			}
+			if (txstat & TXSTATUS_EXCESSDEFER) {
+				/* Defer limit */
+				ndev->stats.tx_aborted_errors++;
+			}
+			ndev->stats.tx_errors++;
+		} else {
+			/* Update stats */
+			ndev->stats.tx_packets++;
+			ndev->stats.tx_bytes += skb->len;
+
+			/* Free buffer */
+			dev_kfree_skb_irq(skb);
+		}
+
+		txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+	}
+
+	if (netif_queue_stopped(ndev))
+		netif_wake_queue(ndev);
+}
+
+static int __lpc_handle_recv(struct net_device *ndev, int budget)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct sk_buff *skb;
+	u32 rxconsidx, len, ethst;
+	struct rx_status_t *prxstat;
+	u8 *prdbuf;
+	int rx_done = 0;
+
+	/* Get the current RX buffer indexes */
+	rxconsidx = readl(LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
+	while (rx_done < budget && rxconsidx !=
+			readl(LPC_ENET_RXPRODUCEINDEX(pldat->net_base))) {
+		/* Get pointer to receive status */
+		prxstat = &pldat->rx_stat_v[rxconsidx];
+		len = (prxstat->statusinfo & RXSTATUS_SIZE) + 1;
+
+		/* Status error? */
+		ethst = prxstat->statusinfo;
+		if ((ethst & (RXSTATUS_ERROR | RXSTATUS_STATUS_ERROR)) ==
+				(RXSTATUS_ERROR | RXSTATUS_RANGE))
+			ethst &= ~RXSTATUS_ERROR;
+
+		if (ethst & RXSTATUS_ERROR) {
+			int si = prxstat->statusinfo;
+			/* Check statuses */
+			if (si & RXSTATUS_OVERRUN) {
+				/* Overrun error */
+				ndev->stats.rx_fifo_errors++;
+			} else if (si & RXSTATUS_CRC) {
+				/* CRC error */
+				ndev->stats.rx_crc_errors++;
+			} else if (si & RXSTATUS_LENGTH) {
+				/* Length error */
+				ndev->stats.rx_length_errors++;
+			} else if (si & RXSTATUS_ERROR) {
+				/* Other error */
+				ndev->stats.rx_length_errors++;
+			}
+			ndev->stats.rx_errors++;
+		} else {
+			/* Packet is good */
+			skb = dev_alloc_skb(len + 8);
+			if (!skb)
+				ndev->stats.rx_dropped++;
+			else {
+				prdbuf = skb_put(skb, len);
+
+				/* Copy packet from buffer */
+				memcpy(prdbuf, pldat->rx_buff_v +
+					rxconsidx * ENET_MAXF_SIZE, len);
+
+				/* Pass to upper layer */
+				skb->protocol = eth_type_trans(skb, ndev);
+				netif_receive_skb(skb);
+				ndev->stats.rx_packets++;
+				ndev->stats.rx_bytes += len;
+			}
+		}
+
+		/* Increment consume index */
+		rxconsidx = rxconsidx + 1;
+		if (rxconsidx >= ENET_RX_DESC)
+			rxconsidx = 0;
+		writel((u32)rxconsidx,
+				LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
+		rx_done++;
+	}
+
+	return rx_done;
+}
+
+static int lpc_eth_poll(struct napi_struct *napi, int budget)
+{
+	struct netdata_local *pldat = container_of(napi,
+			struct netdata_local, napi);
+	struct net_device *ndev = pldat->ndev;
+	int rx_done = 0;
+	struct netdev_queue *txq = netdev_get_tx_queue(ndev, 0);
+
+	__netif_tx_lock(txq, smp_processor_id());
+	__lpc_handle_xmit(ndev);
+	__netif_tx_unlock(txq);
+	rx_done = __lpc_handle_recv(ndev, budget);
+
+	if (rx_done < budget) {
+		napi_complete(napi);
+		lpc_eth_enable_int(pldat->net_base);
+	}
+
+	return rx_done;
+}
+
+static irqreturn_t __lpc_eth_interrupt(int irq, void *dev_id)
+{
+	struct net_device *ndev = dev_id;
+	struct netdata_local *pldat = netdev_priv(ndev);
+	u32 tmp;
+
+	spin_lock(&pldat->lock);
+
+	tmp = readl(LPC_ENET_INTSTATUS(pldat->net_base));
+	/* Clear interrupts */
+	writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base));
+
+	lpc_eth_disable_int(pldat->net_base);
+	if (likely(napi_schedule_prep(&pldat->napi)))
+		__napi_schedule(&pldat->napi);
+
+	spin_unlock(&pldat->lock);
+
+	return IRQ_HANDLED;
+}
+
+static int lpc_eth_close(struct net_device *ndev)
+{
+	unsigned long flags;
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	if (netif_msg_ifdown(pldat))
+		dev_dbg(&pldat->pdev->dev, "shutting down %s\n", ndev->name);
+
+	napi_disable(&pldat->napi);
+	netif_stop_queue(ndev);
+
+	if (pldat->phy_dev)
+		phy_stop(pldat->phy_dev);
+
+	spin_lock_irqsave(&pldat->lock, flags);
+	__lpc_eth_reset(pldat);
+	netif_carrier_off(ndev);
+	writel(0, LPC_ENET_MAC1(pldat->net_base));
+	writel(0, LPC_ENET_MAC2(pldat->net_base));
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	__lpc_eth_clock_enable(pldat, 0);
+
+	return 0;
+}
+
+static int lpc_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	u32 len, txidx;
+	u32 *ptxstat;
+	struct txrx_desc_t *ptxrxdesc;
+
+	len = skb->len;
+
+	spin_lock_irq(&pldat->lock);
+
+	if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) {
+		/* This function should never be called when there are no
+		   buffers */
+		netif_stop_queue(ndev);
+		spin_unlock_irq(&pldat->lock);
+		WARN(1, "BUG! TX request when no free TX buffers!\n");
+		return NETDEV_TX_BUSY;
+	}
+
+	/* Get the next TX descriptor index */
+	txidx = readl(LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
+
+	/* Setup control for the transfer */
+	ptxstat = &pldat->tx_stat_v[txidx];
+	*ptxstat = 0;
+	ptxrxdesc = &pldat->tx_desc_v[txidx];
+	ptxrxdesc->control =
+		(len - 1) | TXDESC_CONTROL_LAST | TXDESC_CONTROL_INT;
+
+	/* Copy data to the DMA buffer */
+	memcpy(pldat->tx_buff_v + txidx * ENET_MAXF_SIZE, skb->data, len);
+
+	/* Save the buffer and increment the buffer counter */
+	pldat->skb[txidx] = skb;
+	pldat->num_used_tx_buffs++;
+
+	/* Start transmit */
+	txidx++;
+	if (txidx >= ENET_TX_DESC)
+		txidx = 0;
+	writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
+
+	/* Stop queue if no more TX buffers */
+	if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1))
+		netif_stop_queue(ndev);
+
+	spin_unlock_irq(&pldat->lock);
+
+	return NETDEV_TX_OK;
+}
+
+static int lpc_set_mac_address(struct net_device *ndev, void *p)
+{
+	struct sockaddr *addr = p;
+	struct netdata_local *pldat = netdev_priv(ndev);
+	unsigned long flags;
+
+	if (!is_valid_ether_addr(addr->sa_data))
+		return -EADDRNOTAVAIL;
+	memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	/* Set station address */
+	__lpc_set_mac(pldat, ndev->dev_addr);
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	return 0;
+}
+
+static void lpc_eth_set_multicast_list(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct netdev_hw_addr_list *mcptr = &ndev->mc;
+	struct netdev_hw_addr *ha;
+	u32 tmp32, hash_val, hashlo, hashhi;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	/* Set station address */
+	__lpc_set_mac(pldat, ndev->dev_addr);
+
+	tmp32 =  LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT;
+
+	if (ndev->flags & IFF_PROMISC)
+		tmp32 |= LPC_RXFLTRW_ACCEPTUNICAST |
+			LPC_RXFLTRW_ACCEPTUMULTICAST;
+	if (ndev->flags & IFF_ALLMULTI)
+		tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICAST;
+
+	if (netdev_hw_addr_list_count(mcptr))
+		tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICASTHASH;
+
+	writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base));
+
+
+	/* Set initial hash table */
+	hashlo = 0x0;
+	hashhi = 0x0;
+
+	/* 64 bits : multicast address in hash table */
+	netdev_hw_addr_list_for_each(ha, mcptr) {
+		hash_val = (ether_crc(6, ha->addr) >> 23) & 0x3F;
+
+		if (hash_val >= 32)
+			hashhi |= 1 << (hash_val - 32);
+		else
+			hashlo |= 1 << hash_val;
+	}
+
+	writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base));
+	writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base));
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+}
+
+static int lpc_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!netif_running(ndev))
+		return -EINVAL;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_mii_ioctl(phydev, req, cmd);
+}
+
+static int lpc_eth_open(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	/* if the phy is not yet registered, retry later*/
+	if (!pldat->phy_dev)
+		return -EAGAIN;
+
+	if (netif_msg_ifup(pldat))
+		dev_dbg(&pldat->pdev->dev, "enabling %s\n", ndev->name);
+
+	if (!is_valid_ether_addr(ndev->dev_addr))
+		return -EADDRNOTAVAIL;
+
+	__lpc_eth_clock_enable(pldat, 1);
+
+	/* Reset and initialize */
+	__lpc_eth_reset(pldat);
+	__lpc_eth_init(pldat);
+
+	/* schedule a link state check */
+	phy_start(pldat->phy_dev);
+	netif_start_queue(ndev);
+	napi_enable(&pldat->napi);
+
+	return 0;
+}
+
+/*
+ * Ethtool ops
+ */
+static void lpc_eth_ethtool_getdrvinfo(struct net_device *ndev,
+	struct ethtool_drvinfo *info)
+{
+	strcpy(info->driver, MODNAME);
+	strcpy(info->version, DRV_VERSION);
+	strcpy(info->bus_info, dev_name(ndev->dev.parent));
+}
+
+static u32 lpc_eth_ethtool_getmsglevel(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	return pldat->msg_enable;
+}
+
+static void lpc_eth_ethtool_setmsglevel(struct net_device *ndev, u32 level)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	pldat->msg_enable = level;
+}
+
+static int lpc_eth_ethtool_getsettings(struct net_device *ndev,
+	struct ethtool_cmd *cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!phydev)
+		return -EOPNOTSUPP;
+
+	return phy_ethtool_gset(phydev, cmd);
+}
+
+static int lpc_eth_ethtool_setsettings(struct net_device *ndev,
+	struct ethtool_cmd *cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!phydev)
+		return -EOPNOTSUPP;
+
+	return phy_ethtool_sset(phydev, cmd);
+}
+
+static const struct ethtool_ops lpc_eth_ethtool_ops = {
+	.get_drvinfo	= lpc_eth_ethtool_getdrvinfo,
+	.get_settings	= lpc_eth_ethtool_getsettings,
+	.set_settings	= lpc_eth_ethtool_setsettings,
+	.get_msglevel	= lpc_eth_ethtool_getmsglevel,
+	.set_msglevel	= lpc_eth_ethtool_setmsglevel,
+	.get_link	= ethtool_op_get_link,
+};
+
+static const struct net_device_ops lpc_netdev_ops = {
+	.ndo_open		= lpc_eth_open,
+	.ndo_stop		= lpc_eth_close,
+	.ndo_start_xmit		= lpc_eth_hard_start_xmit,
+	.ndo_set_rx_mode	= lpc_eth_set_multicast_list,
+	.ndo_do_ioctl		= lpc_eth_ioctl,
+	.ndo_set_mac_address	= lpc_set_mac_address,
+};
+
+static int lpc_eth_drv_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct resource *dma_res;
+	struct net_device *ndev;
+	struct netdata_local *pldat;
+	struct phy_device *phydev;
+	dma_addr_t dma_handle;
+	int irq, ret;
+
+	/* Get platform resources */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	irq = platform_get_irq(pdev, 0);
+	if ((!res) || (!dma_res) || (irq < 0) || (irq >= NR_IRQS)) {
+		dev_err(&pdev->dev, "error getting resources.\n");
+		ret = -ENXIO;
+		goto err_exit;
+	}
+
+	/* Allocate net driver data structure */
+	ndev = alloc_etherdev(sizeof(struct netdata_local));
+	if (!ndev) {
+		dev_err(&pdev->dev, "could not allocate device.\n");
+		ret = -ENOMEM;
+		goto err_exit;
+	}
+
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	pldat = netdev_priv(ndev);
+	pldat->pdev = pdev;
+	pldat->ndev = ndev;
+
+	spin_lock_init(&pldat->lock);
+
+	/* Save resources */
+	ndev->irq = irq;
+
+	/* Get clock for the device */
+	pldat->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(pldat->clk)) {
+		dev_err(&pdev->dev, "error getting clock.\n");
+		ret = PTR_ERR(pldat->clk);
+		goto err_out_free_dev;
+	}
+
+	/* Enable network clock */
+	__lpc_eth_clock_enable(pldat, 1);
+
+	/* Map IO space */
+	pldat->net_base = ioremap(res->start, res->end - res->start + 1);
+	if (!pldat->net_base) {
+		dev_err(&pdev->dev, "failed to map registers\n");
+		ret = -ENOMEM;
+		goto err_out_disable_clocks;
+	}
+	ret = request_irq(ndev->irq, __lpc_eth_interrupt, 0,
+			  ndev->name, ndev);
+	if (ret) {
+		dev_err(&pdev->dev, "error requesting interrupt.\n");
+		goto err_out_iounmap;
+	}
+
+	/* Fill in the fields of the device structure with ethernet values. */
+	ether_setup(ndev);
+
+	/* Setup driver functions */
+	ndev->netdev_ops = &lpc_netdev_ops;
+	ndev->ethtool_ops = &lpc_eth_ethtool_ops;
+	ndev->watchdog_timeo = msecs_to_jiffies(2500);
+
+	/* Get size of DMA buffers/descriptors region */
+	pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE +
+		sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
+	pldat->dma_buff_base_v = 0;
+
+	if (use_iram_for_net()) {
+		dma_handle = dma_res->start;
+		if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
+			pldat->dma_buff_base_v =
+				io_p2v(dma_res->start);
+		else
+			netdev_err(ndev,
+				"IRAM not big enough for net buffers, using SDRAM instead.\n");
+	}
+
+	if (pldat->dma_buff_base_v == 0) {
+		pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size);
+
+		/* Allocate a chunk of memory for the DMA ethernet buffers
+		   and descriptors */
+		pldat->dma_buff_base_v =
+			dma_alloc_coherent(&pldat->pdev->dev,
+						pldat->dma_buff_size,
+						&dma_handle, GFP_KERNEL);
+
+		if (pldat->dma_buff_base_v == NULL) {
+			dev_err(&pdev->dev, "error getting DMA region.\n");
+			ret = -ENOMEM;
+			goto err_out_free_irq;
+		}
+	}
+	pldat->dma_buff_base_p = dma_handle;
+
+	netdev_dbg(ndev, "IO address start     :0x%08x\n",
+			res->start);
+	netdev_dbg(ndev, "IO address size      :%d\n",
+			res->end - res->start + 1);
+	netdev_err(ndev, "IO address (mapped)  :0x%p\n",
+			pldat->net_base);
+	netdev_dbg(ndev, "IRQ number           :%d\n", ndev->irq);
+	netdev_dbg(ndev, "DMA buffer size      :%d\n", pldat->dma_buff_size);
+	netdev_dbg(ndev, "DMA buffer P address :0x%08x\n",
+			pldat->dma_buff_base_p);
+	netdev_dbg(ndev, "DMA buffer V address :0x%p\n",
+			pldat->dma_buff_base_v);
+
+	/* Get MAC address from current HW setting (POR state is all zeros) */
+	__lpc_get_mac(pldat, ndev->dev_addr);
+
+#ifdef CONFIG_OF_NET
+	if (!is_valid_ether_addr(ndev->dev_addr)) {
+		const char *macaddr = of_get_mac_address(pdev->dev.of_node);
+		if (macaddr)
+			memcpy(ndev->dev_addr, macaddr, ETH_ALEN);
+	}
+#endif
+	if (!is_valid_ether_addr(ndev->dev_addr))
+		dev_hw_addr_random(ndev, ndev->dev_addr);
+
+	/* Reset the ethernet controller */
+	__lpc_eth_reset(pldat);
+
+	/* then shut everything down to save power */
+	__lpc_eth_shutdown(pldat);
+
+	/* Set default parameters */
+	pldat->msg_enable = NETIF_MSG_LINK;
+
+	/* Force an MII interface reset and clock setup */
+	__lpc_mii_mngt_reset(pldat);
+
+	/* Force default PHY interface setup in chip, this will probably be
+	   changed by the PHY driver */
+	pldat->link = 0;
+	pldat->speed = 100;
+	pldat->duplex = DUPLEX_FULL;
+	__lpc_params_setup(pldat);
+
+	netif_napi_add(ndev, &pldat->napi, lpc_eth_poll, NAPI_WEIGHT);
+
+	ret = register_netdev(ndev);
+	if (ret) {
+		dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
+		goto err_out_dma_unmap;
+	}
+	platform_set_drvdata(pdev, ndev);
+
+	if (lpc_mii_init(pldat) != 0)
+		goto err_out_unregister_netdev;
+
+	netdev_info(ndev, "LPC mac at 0x%08x irq %d\n",
+	       res->start, ndev->irq);
+
+	phydev = pldat->phy_dev;
+	netdev_info(ndev,
+		"attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
+		phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
+
+	device_init_wakeup(&pdev->dev, 1);
+	device_set_wakeup_enable(&pdev->dev, 0);
+
+	return 0;
+
+err_out_unregister_netdev:
+	platform_set_drvdata(pdev, NULL);
+	unregister_netdev(ndev);
+err_out_dma_unmap:
+	if (!use_iram_for_net() ||
+			pldat->dma_buff_size > lpc32xx_return_iram_size())
+		dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
+			pldat->dma_buff_base_v,
+			pldat->dma_buff_base_p);
+err_out_free_irq:
+	free_irq(ndev->irq, ndev);
+err_out_iounmap:
+	iounmap(pldat->net_base);
+err_out_disable_clocks:
+	clk_disable(pldat->clk);
+	clk_put(pldat->clk);
+err_out_free_dev:
+	free_netdev(ndev);
+err_exit:
+	pr_err("%s: not found (%d).\n", MODNAME, ret);
+	return ret;
+}
+
+static int lpc_eth_drv_remove(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	unregister_netdev(ndev);
+	platform_set_drvdata(pdev, NULL);
+
+	if (!use_iram_for_net() ||
+			pldat->dma_buff_size > lpc32xx_return_iram_size())
+		dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
+			pldat->dma_buff_base_v,
+			pldat->dma_buff_base_p);
+	free_irq(ndev->irq, ndev);
+	iounmap(pldat->net_base);
+	clk_disable(pldat->clk);
+	clk_put(pldat->clk);
+	free_netdev(ndev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int lpc_eth_drv_suspend(struct platform_device *pdev,
+	pm_message_t state)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	if (device_may_wakeup(&pdev->dev))
+		enable_irq_wake(ndev->irq);
+
+	if (ndev) {
+		if (netif_running(ndev)) {
+			netif_device_detach(ndev);
+			__lpc_eth_shutdown(pldat);
+			clk_disable(pldat->clk);
+
+			/*
+			 * Reset again now clock is disable to be sure
+			 * EMC_MDC is down
+			 */
+			__lpc_eth_reset(pldat);
+		}
+	}
+
+	return 0;
+}
+
+static int lpc_eth_drv_resume(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat;
+
+	if (device_may_wakeup(&pdev->dev))
+		disable_irq_wake(ndev->irq);
+
+	if (ndev) {
+		if (netif_running(ndev)) {
+			pldat = netdev_priv(ndev);
+
+			/* Enable interface clock */
+			clk_enable(pldat->clk);
+
+			/* Reset and initialize */
+			__lpc_eth_reset(pldat);
+			__lpc_eth_init(pldat);
+
+			netif_device_attach(ndev);
+		}
+	}
+
+	return 0;
+}
+#endif
+
+static struct platform_driver lpc_eth_driver = {
+	.probe		= lpc_eth_drv_probe,
+	.remove		= __devexit_p(lpc_eth_drv_remove),
+#ifdef CONFIG_PM
+	.suspend	= lpc_eth_drv_suspend,
+	.resume		= lpc_eth_drv_resume,
+#endif
+	.driver		= {
+		.name	= MODNAME,
+	},
+};
+
+module_platform_driver(lpc_eth_driver);
+
+MODULE_AUTHOR("Kevin Wells <kevin.wells at nxp.com>");
+MODULE_AUTHOR("Roland Stigge <stigge at antcom.de>");
+MODULE_DESCRIPTION("LPC Ethernet Driver");
+MODULE_LICENSE("GPL");
+


From robherring2 at gmail.com  Tue Mar  6 16:10:43 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 06 Mar 2012 15:10:43 -0600
Subject: [PATCH v4 3/4] ARM: msm: use runtime ioremap hook
In-Reply-To: <20120306205954.GA21912@codeaurora.org>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331006580-3579-1-git-send-email-robherring2@gmail.com>
 <1331006580-3579-3-git-send-email-robherring2@gmail.com>
 <20120306205954.GA21912@codeaurora.org>
Message-ID: <4F567D53.9040204@gmail.com>

On 03/06/2012 02:59 PM, David Brown wrote:
> On Mon, Mar 05, 2012 at 10:02:59PM -0600, Rob Herring wrote:
>> From: Rob Herring <rob.herring at calxeda.com>
>>
>> Convert msm platforms to use run-time ioremap hook instead of the compile
>> time hook.
>>
>> According to David Brown, only the msm7201 needed the ioremap hook.
>>
>> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
>> Tested-by: David Brown <davidb at codeaurora.org>
>> Acked-by: David Brown <davidb at codeaurora.org>
>> Cc: Daniel Walker <dwalker at fifo99.com>
>> Cc: Bryan Huntsman <bryanh at codeaurora.org>
> 
> This still is working on 8660.
> 
> BTW, I'm not able to cleanly apply the IMX patches.  What tree are you
> basing that off of?
> 

That would be the restart clean-up branch which I don't need, but the
at91 and omap clean-up branches I'm based on have pulled that branch in.

Rob


From linus.walleij at stericsson.com  Tue Mar  6 16:15:52 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 6 Mar 2012 22:15:52 +0100
Subject: [PATCH] pinctrl: split pincontrol states into its own header
Message-ID: <1331068552-16988-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Move the pin control state defines into its own header file,
since it is used both by machine.h which is facing the platform
and by consumer.h which is facing the drivers, and pinctrl.h
which is pinctrl-driver internal, let's not have each and every
.h file include all others, then isolation is moot.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 include/linux/pinctrl/consumer.h      |    2 +-
 include/linux/pinctrl/machine.h       |    2 +-
 include/linux/pinctrl/pinctrl-state.h |    6 ++++++
 include/linux/pinctrl/pinctrl.h       |    3 +--
 4 files changed, 9 insertions(+), 4 deletions(-)
 create mode 100644 include/linux/pinctrl/pinctrl-state.h

diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h
index 9ad5896..191e726 100644
--- a/include/linux/pinctrl/consumer.h
+++ b/include/linux/pinctrl/consumer.h
@@ -15,7 +15,7 @@
 #include <linux/err.h>
 #include <linux/list.h>
 #include <linux/seq_file.h>
-#include "pinctrl.h"
+#include "pinctrl-state.h"
 
 /* This struct is private to the core and should be regarded as a cookie */
 struct pinctrl;
diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h
index 3fd2f9d..fee4349 100644
--- a/include/linux/pinctrl/machine.h
+++ b/include/linux/pinctrl/machine.h
@@ -12,7 +12,7 @@
 #ifndef __LINUX_PINCTRL_MACHINE_H
 #define __LINUX_PINCTRL_MACHINE_H
 
-#include "pinctrl.h"
+#include "pinctrl-state.h"
 
 enum pinctrl_map_type {
 	PIN_MAP_TYPE_INVALID,
diff --git a/include/linux/pinctrl/pinctrl-state.h b/include/linux/pinctrl/pinctrl-state.h
new file mode 100644
index 0000000..3920e28
--- /dev/null
+++ b/include/linux/pinctrl/pinctrl-state.h
@@ -0,0 +1,6 @@
+/*
+ * Standard pin control state definitions
+ */
+
+#define PINCTRL_STATE_DEFAULT "default"
+#define PINCTRL_STATE_IDLE "idle"
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index bbdd7e1..e9e94eb 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -17,8 +17,7 @@
 #include <linux/radix-tree.h>
 #include <linux/list.h>
 #include <linux/seq_file.h>
-
-#define PINCTRL_STATE_DEFAULT "default"
+#include "pinctrl-state.h"
 
 struct pinctrl_dev;
 struct pinmux_ops;
-- 
1.7.8



From swarren at wwwdotorg.org  Tue Mar  6 16:21:43 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 06 Mar 2012 14:21:43 -0700
Subject: [PATCH] pinctrl: split pincontrol states into its own header
In-Reply-To: <1331068552-16988-1-git-send-email-linus.walleij@stericsson.com>
References: <1331068552-16988-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <4F567FE7.4020507@wwwdotorg.org>

On 03/06/2012 02:15 PM, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> Move the pin control state defines into its own header file,
> since it is used both by machine.h which is facing the platform
> and by consumer.h which is facing the drivers, and pinctrl.h
> which is pinctrl-driver internal, let's not have each and every
> .h file include all others, then isolation is moot.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Sure. I'm not quite sure how many (or how many standardized) states we
expect to have such that it warrants 'pinctrl-state.h' vs. say
'pinctrl-common.h', but it's probably fine.

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From stigge at antcom.de  Tue Mar  6 16:21:53 2012
From: stigge at antcom.de (Roland Stigge)
Date: Tue,  6 Mar 2012 22:21:53 +0100
Subject: [PATCH RESEND v3] USB: Support for LPC32xx SoC
Message-ID: <1331068913-9321-1-git-send-email-stigge@antcom.de>

This patch adds OHCI support to the LPC32xx ARM platform

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 drivers/usb/host/ohci-hcd.c     |    5 +++
 drivers/usb/host/ohci-pnx4008.c |   66 +++++++++++++++++++++++++++++++++++++---
 2 files changed, 67 insertions(+), 4 deletions(-)

--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1055,6 +1055,11 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
 #endif
 
+#ifdef CONFIG_ARCH_LPC32XX
+#include "ohci-pnx4008.c"
+#define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
+#endif
+
 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
 #include "ohci-da8xx.c"
 #define PLATFORM_DRIVER		ohci_hcd_da8xx_driver
--- linux-2.6.orig/drivers/usb/host/ohci-pnx4008.c
+++ linux-2.6/drivers/usb/host/ohci-pnx4008.c
@@ -22,6 +22,7 @@
 #include <linux/i2c.h>
 
 #include <mach/hardware.h>
+#include <asm/mach-types.h>
 #include <asm/io.h>
 
 #include <mach/platform.h>
@@ -143,7 +144,17 @@ static void i2c_write(u8 buf, u8 subaddr
 	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
 }
 
-static void isp1301_configure(void)
+static u16 i2c_read16(u8 subaddr)
+{
+	u16 data;
+
+	i2c_master_send(isp1301_i2c_client, &subaddr, 1);
+	i2c_master_recv(isp1301_i2c_client, (u8 *) &data, 2);
+
+	return data;
+}
+
+static void isp1301_configure_pnx4008(void)
 {
 	/* PNX4008 only supports DAT_SE0 USB mode */
 	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
@@ -166,7 +177,51 @@ static void isp1301_configure(void)
 		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
 	i2c_write(0xFF,
 		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+}
 
+static void isp1301_configure_lpc32xx(void)
+{
+	/* LPC32XX only supports DAT_SE0 USB mode */
+	/* This sequence is important */
+
+	/* Disable transparent UART mode first */
+	i2c_write(MC1_UART_EN, (ISP1301_I2C_MODE_CONTROL_1 |
+		ISP1301_I2C_REG_CLEAR_ADDR));
+
+	i2c_write(~MC1_SPEED_REG, (ISP1301_I2C_MODE_CONTROL_1 |
+		ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
+	i2c_write(~0,
+		(ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write((MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
+		ISP1301_I2C_MODE_CONTROL_2);
+	i2c_write(~0, (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(MC1_DAT_SE0, ISP1301_I2C_MODE_CONTROL_1);
+	i2c_write((OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
+		ISP1301_I2C_OTG_CONTROL_1);
+	i2c_write((OTG1_DM_PULLUP | OTG1_DP_PULLUP),
+		(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(~0,
+		 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(~0,
+		ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(~0,
+		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+
+	/* Enable usb_need_clk clock after transceiver is initialized */
+	__raw_writel((__raw_readl(USB_CTRL) | (1 << 22)), USB_CTRL);
+
+	printk(KERN_INFO "ISP1301 Vendor ID  : 0x%04x\n", i2c_read16(0x00));
+	printk(KERN_INFO "ISP1301 Product ID : 0x%04x\n", i2c_read16(0x02));
+	printk(KERN_INFO "ISP1301 Version ID : 0x%04x\n", i2c_read16(0x14));
+}
+
+static void isp1301_configure(void)
+{
+	if (machine_is_pnx4008())
+		isp1301_configure_pnx4008();
+	else
+		isp1301_configure_lpc32xx();
 }
 
 static inline void isp1301_vbus_on(void)
@@ -375,7 +430,8 @@ static int __devinit usb_hcd_pnx4008_pro
 	}
 
 	/* Set all USB bits in the Start Enable register */
-	pnx4008_set_usb_bits();
+	if (machine_is_pnx4008())
+		pnx4008_set_usb_bits();
 
 	hcd->rsrc_start = pdev->resource[0].start;
 	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
@@ -404,7 +460,8 @@ static int __devinit usb_hcd_pnx4008_pro
 
 	pnx4008_stop_hc();
 out4:
-	pnx4008_unset_usb_bits();
+	if (machine_is_pnx4008())
+		pnx4008_unset_usb_bits();
 	usb_put_hcd(hcd);
 out3:
 	clk_disable(usb_clk);
@@ -427,7 +484,8 @@ static int usb_hcd_pnx4008_remove(struct
 	pnx4008_stop_hc();
 	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 	usb_put_hcd(hcd);
-	pnx4008_unset_usb_bits();
+	if (machine_is_pnx4008())
+		pnx4008_unset_usb_bits();
 	clk_disable(usb_clk);
 	clk_put(usb_clk);
 	i2c_unregister_device(isp1301_i2c_client);


From davem at davemloft.net  Tue Mar  6 16:20:17 2012
From: davem at davemloft.net (David Miller)
Date: Tue, 06 Mar 2012 16:20:17 -0500 (EST)
Subject: [PATCH v5] lpc32xx: Added ethernet driver
In-Reply-To: <1331067664-9124-1-git-send-email-stigge@antcom.de>
References: <1331067664-9124-1-git-send-email-stigge@antcom.de>
Message-ID: <20120306.162017.761246743182346842.davem@davemloft.net>

From: Roland Stigge <stigge at antcom.de>
Date: Tue,  6 Mar 2012 22:01:04 +0100

> +#define RXSTATUS_STATUS_ERROR \
> +	(RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | RXSTATUS_RANGE \
> +	 | RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC)

Should be:

#define RXSTATUS_STATUS_ERROR \
	(RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | RXSTATUS_RANGE | \
	 RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC)

> +static int lpc_eth_hard_start_xmit(struct sk_buff *skb,
> +	struct net_device *ndev);

Should be:

static int lpc_eth_hard_start_xmit(struct sk_buff *skb,
				   struct net_device *ndev);

> +struct txrx_desc_t {
> +	u32 packet;
> +	u32 control;
> +};
> +struct rx_status_t {
> +	u32 statusinfo;
> +	u32 statushashcrc;
> +};

What is the endianness of these descriptors?  Based upon the answer to
that question use __be32 or __le32  instead of u32.

> +static void __lpc_eth_clock_enable(struct netdata_local *pldat,
> +	int enable)

Should be:

static void __lpc_eth_clock_enable(struct netdata_local *pldat,
				   int enable)

And you should also use "bool" for enable and pass in true/false
at the call sites.

> +	writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN),
> +		LPC_ENET_INTENABLE(regbase));

Should be:

	writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN),
	       LPC_ENET_INTENABLE(regbase));

> +	/* Setup base addresses in hardware to point to buffers and
> +	   descriptors */

Should be:

	/* Setup base addresses in hardware to point to buffers and
	 * descriptors.
	 */

> +	writel((ENET_TX_DESC - 1),
> +		LPC_ENET_TXDESCRIPTORNUMBER(pldat->net_base));

All of these writel() calls are improperly indented on the second and
any subsequent lines just like the one I pointed out above, fix them
all.

> +MODULE_LICENSE("GPL");
> +

Tailing empty line in this file, please remove.


From stigge at antcom.de  Tue Mar  6 16:25:11 2012
From: stigge at antcom.de (Roland Stigge)
Date: Tue,  6 Mar 2012 22:25:11 +0100
Subject: [PATCH RESEND v3] ARM: LPC32xx: USB Support
Message-ID: <1331069111-9374-1-git-send-email-stigge@antcom.de>

This patch adds OHCI support to the LPC32xx ARM platform. Besides the trivial
addition of platform "usb-ohci" support, fixes for the USB PLL have been added
to arch/arm/mach-lpc32xx/clock.c, ported from NXP's lpclinux.com.

(This is the mach-lpc32xx specific part, the USB subsystem specific changes are
in a separate patch for the USB maintainers.)

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 arch/arm/mach-lpc32xx/clock.c                 |   87 ++++++++++++++++++--------
 arch/arm/mach-lpc32xx/common.c                |   26 +++++++
 arch/arm/mach-lpc32xx/common.h                |    1 
 arch/arm/mach-lpc32xx/include/mach/platform.h |   10 ++
 arch/arm/mach-lpc32xx/phy3250.c               |    1 
 5 files changed, 101 insertions(+), 24 deletions(-)

--- linux-2.6.orig/arch/arm/mach-lpc32xx/clock.c
+++ linux-2.6/arch/arm/mach-lpc32xx/clock.c
@@ -87,6 +87,7 @@
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/device.h>
+#include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/amba/bus.h>
@@ -100,6 +101,8 @@
 
 static DEFINE_SPINLOCK(global_clkregs_lock);
 
+static int usb_pll_enable, usb_pll_valid;
+
 static struct clk clk_armpll;
 static struct clk clk_usbpll;
 
@@ -384,30 +387,62 @@ static u32 local_clk_usbpll_setup(struct
 static int local_usbpll_enable(struct clk *clk, int enable)
 {
 	u32 reg;
-	int ret = -ENODEV;
-	unsigned long timeout = jiffies + msecs_to_jiffies(10);
+	int ret = 0;
+	unsigned long timeout = jiffies + msecs_to_jiffies(20);
 
 	reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 
-	if (enable == 0) {
-		reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
-			LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
-		__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
-	} else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
+	__raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2 |
+		LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
+		LPC32XX_CLKPWR_USB_CTRL);
+	__raw_writel(reg & ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1,
+		LPC32XX_CLKPWR_USB_CTRL);
+
+	if (enable && usb_pll_valid && usb_pll_enable) {
+		ret = -ENODEV;
+		/*
+		 * If the PLL rate has been previously set, then the rate
+		 * in the PLL register is valid and can be enabled here.
+		 * Otherwise, it needs to be enabled as part of setrate.
+		 */
+
+		/*
+		 * Gate clock into PLL
+		 */
 		reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
 		__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 
-		/* Wait for PLL lock */
+		/*
+		 * Enable PLL
+		 */
+		reg |= LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP;
+		__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+		/*
+		 * Wait for PLL to lock
+		 */
 		while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
 			reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 			if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
 				ret = 0;
+			else
+				udelay(10);
 		}
 
+		/*
+		 * Gate clock from PLL if PLL is locked
+		 */
 		if (ret == 0) {
-			reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
-			__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+			__raw_writel(reg | LPC32XX_CLKPWR_USBCTRL_CLK_EN2,
+				LPC32XX_CLKPWR_USB_CTRL);
+		} else {
+			__raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
+				LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
+				LPC32XX_CLKPWR_USB_CTRL);
 		}
+	} else if ((enable == 0) && usb_pll_valid  && usb_pll_enable) {
+		usb_pll_valid = 0;
+		usb_pll_enable = 0;
 	}
 
 	return ret;
@@ -425,7 +460,7 @@ static unsigned long local_usbpll_round_
 	 */
 	rate = rate * 1000;
 
-	clkin = clk->parent->rate;
+	clkin = clk->get_rate(clk);
 	usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
 		LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
 	clkin = clkin / usbdiv;
@@ -439,7 +474,8 @@ static unsigned long local_usbpll_round_
 
 static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
 {
-	u32 clkin, reg, usbdiv;
+	int ret = -ENODEV;
+	u32 clkin, usbdiv;
 	struct clk_pll_setup pllsetup;
 
 	/*
@@ -448,7 +484,7 @@ static int local_usbpll_set_rate(struct
 	 */
 	rate = rate * 1000;
 
-	clkin = clk->get_rate(clk);
+	clkin = clk->get_rate(clk->parent);
 	usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
 		LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
 	clkin = clkin / usbdiv;
@@ -457,22 +493,25 @@ static int local_usbpll_set_rate(struct
 	if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
 		return -EINVAL;
 
+	/*
+	 * Disable PLL clocks during PLL change
+	 */
 	local_usbpll_enable(clk, 0);
-
-	reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
-	reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
-	__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
-
-	pllsetup.analog_on = 1;
+	pllsetup.analog_on = 0;
 	local_clk_usbpll_setup(&pllsetup);
 
-	clk->rate = clk_check_pll_setup(clkin, &pllsetup);
+	/*
+	 * Start USB PLL and check PLL status
+	 */
+
+	usb_pll_valid = 1;
+	usb_pll_enable = 1;
 
-	reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
-	reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
-	__raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+	ret = local_usbpll_enable(clk, 1);
+	if (ret >= 0)
+		clk->rate = clk_check_pll_setup(clkin, &pllsetup);
 
-	return 0;
+	return ret;
 }
 
 static struct clk clk_usbpll = {
--- linux-2.6.orig/arch/arm/mach-lpc32xx/common.c
+++ linux-2.6/arch/arm/mach-lpc32xx/common.c
@@ -160,6 +160,32 @@ struct platform_device lpc32xx_adc_devic
 };
 
 /*
+ * USB support
+ */
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32) 0;
+static struct resource ohci_resources[] = {
+	{
+		.start = IO_ADDRESS(LPC32XX_USB_BASE),
+		.end = IO_ADDRESS(LPC32XX_USB_BASE + 0x100 - 1),
+		.flags = IORESOURCE_MEM,
+	}, {
+		.start = IRQ_LPC32XX_USB_HOST,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+struct platform_device lpc32xx_ohci_device = {
+	.name = "usb-ohci",
+	.id = -1,
+	.dev = {
+		.dma_mask = &ohci_dmamask,
+		.coherent_dma_mask = 0xFFFFFFFF,
+	},
+	.num_resources = ARRAY_SIZE(ohci_resources),
+	.resource = ohci_resources,
+};
+
+/*
  * Returns the unique ID for the device
  */
 void lpc32xx_get_uid(u32 devid[4])
--- linux-2.6.orig/arch/arm/mach-lpc32xx/common.h
+++ linux-2.6/arch/arm/mach-lpc32xx/common.h
@@ -31,6 +31,7 @@ extern struct platform_device lpc32xx_i2
 extern struct platform_device lpc32xx_tsc_device;
 extern struct platform_device lpc32xx_adc_device;
 extern struct platform_device lpc32xx_rtc_device;
+extern struct platform_device lpc32xx_ohci_device;
 
 /*
  * Other arch specific structures and functions
--- linux-2.6.orig/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ linux-2.6/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -694,4 +694,14 @@
 #define LPC32XX_GPIO_P2_MUX_CLR			_GPREG(0x02C)
 #define LPC32XX_GPIO_P2_MUX_STATE		_GPREG(0x030)
 
+#ifdef CONFIG_USB_OHCI_HCD
+#define PNX4008_PWRMAN_BASE			LPC32XX_CLK_PM_BASE
+#define PNX4008_USB_CONFIG_BASE			LPC32XX_USB_BASE
+#define start_int_set_falling_edge(irq)
+#define start_int_set_rising_edge(irq)
+#define start_int_ack(irq)
+#define start_int_mask(irq)
+#define start_int_umask(irq)
+#endif
+
 #endif
--- linux-2.6.orig/arch/arm/mach-lpc32xx/phy3250.c
+++ linux-2.6/arch/arm/mach-lpc32xx/phy3250.c
@@ -277,6 +277,7 @@ static struct platform_device *phy3250_d
 	&lpc32xx_watchdog_device,
 	&lpc32xx_gpio_led_device,
 	&lpc32xx_adc_device,
+	&lpc32xx_ohci_device,
 };
 
 static struct amba_device *amba_devs[] __initdata = {


From tony at atomide.com  Tue Mar  6 16:26:06 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 6 Mar 2012 13:26:06 -0800
Subject: [PATCH] gpio/omap: Fix section warning for omap_mpuio_alloc_gc()
Message-ID: <20120306212605.GY12083@atomide.com>

From: Tony Lindgren <tony at atomide.com>
Date: Mon, 5 Mar 2012 15:32:38 -0800
Subject: [PATCH] gpio/omap: Fix section warning for omap_mpuio_alloc_gc()

Make omap_mpuio_alloc_gc() __devinit as omap_gpio_chip_init()
is __devinit. Otherwise we get:

WARNING: vmlinux.o(.devinit.text+0xa10): Section mismatch in reference
from the function omap_gpio_chip_init() to the function .init.text:omap_mpuio_alloc_gc()
The function __devinit omap_gpio_chip_init() references
a function __init omap_mpuio_alloc_gc().
If omap_mpuio_alloc_gc is only used by omap_gpio_chip_init then
annotate omap_mpuio_alloc_gc with a matching annotation.

Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1081,7 +1081,7 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
 	}
 }
 
-static __init void
+static __devinit void
 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
 		    unsigned int num)
 {


From arnd at arndb.de  Tue Mar  6 16:34:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 6 Mar 2012 21:34:37 +0000
Subject: [PATCH v5] lpc32xx: Added ethernet driver
In-Reply-To: <1331067664-9124-1-git-send-email-stigge@antcom.de>
References: <1331067664-9124-1-git-send-email-stigge@antcom.de>
Message-ID: <201203062134.38077.arnd@arndb.de>

Hi Roland,

One more thing I noticed this time:

On Tuesday 06 March 2012, Roland Stigge wrote:
> +static inline phy_interface_t lpc_phy_interface_mode(void)
> +{
> +#ifdef CONFIG_ARCH_LPC32XX_MII_SUPPORT
> +       return PHY_INTERFACE_MODE_MII;
> +#else
> +       return PHY_INTERFACE_MODE_RMII;
> +#endif
> +}
> +
> +static inline int use_iram_for_net(void)
> +{
> +#ifdef CONFIG_ARCH_LPC32XX_IRAM_FOR_NET
> +       return 1;
> +#else
> +       return 0;
> +#endif
> +}

This should eventually both become run-time options based on the device tree.
I don't know if you planned to do that anyway, but if you want the same kernel
binary to be used for systems in different configurations, you cannot have
compile-time decisions that are exclusive-or. Since you don't support device
tree yet but plan to do that in the future, you could add a comment here
about it, or you could even prepare it for that case already by passing the
device into the functions that will be required for reading the properties.

	Arnd


From tony at atomide.com  Tue Mar  6 16:38:00 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 6 Mar 2012 13:38:00 -0800
Subject: [PATCH] ARM: OMAP: WiLink platform data for the PandaBoard
In-Reply-To: <1330994797-17298-1-git-send-email-mgherzan@gmail.com>
References: <1330994797-17298-1-git-send-email-mgherzan@gmail.com>
Message-ID: <20120306213800.GZ12083@atomide.com>

Hi,

* Mircea Gherzan <mgherzan at gmail.com> [120305 16:15]:
> The "uim" deamon requires sysfs entries that are filled in using
> this platform data.
> 
> Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
> ---
>  arch/arm/mach-omap2/board-omap4panda.c |   23 +++++++++++++++++------
>  include/linux/ti_wilink_st.h           |    2 ++
>  2 files changed, 19 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
> index b1d74d6..37b437f 100644
> --- a/arch/arm/mach-omap2/board-omap4panda.c
> +++ b/arch/arm/mach-omap2/board-omap4panda.c
> @@ -27,6 +27,7 @@
>  #include <linux/i2c/twl.h>
>  #include <linux/regulator/machine.h>
>  #include <linux/regulator/fixed.h>
> +#include <linux/ti_wilink_st.h>
>  #include <linux/wl12xx.h>
>  
>  #include <mach/hardware.h>
> @@ -56,15 +57,29 @@
>  #define HDMI_GPIO_HPD  63 /* Hotplug detect */
>  
>  /* wl127x BT, FM, GPS connectivity chip */
> -static int wl1271_gpios[] = {46, -1, -1};
> +static struct ti_st_plat_data wilink_platform_data = {
> +        .nshutdown_gpio	= 46,
> +        .dev_name	= "/dev/ttyO1",
> +        .flow_cntrl	= 1,
> +        .baud_rate	= 3000000,
> +	.chip_enable	= NULL,
> +        .suspend	= NULL,
> +        .resume		= NULL,
> +};
> +

Please use tabs above before .xxx instead of spaces.

> +static struct platform_device btwilink_device = {
> +	.name	= "btwilink",
> +	.id	= -1,
> +};
> +
>  static struct gpio_led gpio_leds[] = {
>  	{
>  		.name			= "pandaboard::status1",
> @@ -91,10 +106,6 @@ static struct platform_device leds_gpio = {
>  	},
>  };
>  
> -static struct platform_device btwilink_device = {
> -	.name	= "btwilink",
> -	.id	= -1,
> -};

This change is probably not needed, right?

Regards,

Tony


From tony at atomide.com  Tue Mar  6 16:38:59 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 6 Mar 2012 13:38:59 -0800
Subject: [PATCH] omap3_beagle: init uart2 for beagle rev AX/BX only
In-Reply-To: <1331024711-23578-1-git-send-email-govindraj.raja@ti.com>
References: <1331024711-23578-1-git-send-email-govindraj.raja@ti.com>
Message-ID: <20120306213859.GA12083@atomide.com>

* Govindraj.R <govindraj.raja at ti.com> [120306 00:34]:
> From: "Govindraj.R" <govindraj.raja at ti.com>
> 
> All beagle boards rev > AX/BX have external usb hubs connected to ehci
> interface, external hub/peripheral uses a nreset sequence for which
> uart2_rx.gpio_147 pin in mux mode4(USB2HS_nRST) is used on all beagle
> boards expect rev Ax/BX.
> (Reference to all beagle boards rev schematics:
> http://beagleboard.org/hardware/design)
> 
> Initialising uart2 will lead to serial init taking over uart2_rx pin
> so init uart2_rx pin mux only for Beagle AX/BX rev boards.
> Dont init uart2 for all other boards allowing usb_ehci functionality.
> 
> To initialise individual uart port by id utilise and modify the existing
> available func. omap_serial_board_init.
> 
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Koen Kooi <koen at dominion.thruhere.net>
> Tested-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Tested-by: Robert Nelson <robertcnelson at gmail.com>
> Signed-off-by: Govindraj.R <govindraj.raja at ti.com>

Can somebody please test this on non-xm beagle too and
reply with a Tested-by?

Thanks,

Tony

> ---
>  arch/arm/mach-omap2/board-omap3beagle.c  |    6 +++-
>  arch/arm/mach-omap2/serial.c             |   41 ++++++++++++++++-------------
>  arch/arm/plat-omap/include/plat/serial.h |    3 +-
>  3 files changed, 30 insertions(+), 20 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
> index 7ffcd28..19d6fb5 100644
> --- a/arch/arm/mach-omap2/board-omap3beagle.c
> +++ b/arch/arm/mach-omap2/board-omap3beagle.c
> @@ -126,6 +126,7 @@ static void __init omap3_beagle_init_rev(void)
>  		beagle_config.mmc1_gpio_wp = 29;
>  		beagle_config.reset_gpio = 170;
>  		beagle_config.usr_button_gpio = 7;
> +		omap_serial_board_init(NULL, 1);
>  		break;
>  	case 6:
>  		printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n");
> @@ -528,7 +529,10 @@ static void __init omap3_beagle_init(void)
>  	platform_add_devices(omap3_beagle_devices,
>  			ARRAY_SIZE(omap3_beagle_devices));
>  	omap_display_init(&beagle_dss_data);
> -	omap_serial_init();
> +	omap_serial_board_init(NULL, 0);
> +	omap_serial_board_init(NULL, 2);
> +	omap_serial_board_init(NULL, 3);
> +
>  	omap_sdrc_init(mt46h32m32lf6_sdrc_params,
>  				  mt46h32m32lf6_sdrc_params);
>  
> diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
> index f590afc..e7c0462 100644
> --- a/arch/arm/mach-omap2/serial.c
> +++ b/arch/arm/mach-omap2/serial.c
> @@ -393,30 +393,32 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
>  /**
>   * omap_serial_board_init() - initialize all supported serial ports
>   * @info: platform specific data pointer
> + * @port_id: uart port number to be initialised
>   *
> - * Initializes all available UARTs as serial ports. Platforms
> + * Initializes individual UARTs as serial ports. Platforms
>   * can call this function when they want to have default behaviour
> - * for serial ports (e.g initialize them all as serial ports).
> + * for serial ports (e.g initialize individual serial ports based on port id).
>   */
> -void __init omap_serial_board_init(struct omap_uart_port_info *info)
> +void __init omap_serial_board_init(struct omap_uart_port_info *info, u8 port_id)
>  {
>  	struct omap_uart_state *uart;
>  	struct omap_board_data bdata;
>  
> -	list_for_each_entry(uart, &uart_list, node) {
> -		bdata.id = uart->num;
> -		bdata.flags = 0;
> -		bdata.pads = NULL;
> -		bdata.pads_cnt = 0;
> -
> -		if (cpu_is_omap44xx() || cpu_is_omap34xx())
> -			omap_serial_fill_default_pads(&bdata);
> -
> -		if (!info)
> -			omap_serial_init_port(&bdata, NULL);
> -		else
> -			omap_serial_init_port(&bdata, &info[uart->num]);
> -	}
> +	list_for_each_entry(uart, &uart_list, node)
> +		if (uart->num == port_id) {
> +			bdata.id = uart->num;
> +			bdata.flags = 0;
> +			bdata.pads = NULL;
> +			bdata.pads_cnt = 0;
> +
> +			if (!cpu_is_omap24xx())
> +				omap_serial_fill_default_pads(&bdata);
> +
> +			if (!info)
> +				omap_serial_init_port(&bdata, NULL);
> +			else
> +				omap_serial_init_port(&bdata, info);
> +		}
>  }
>  
>  /**
> @@ -428,5 +430,8 @@ void __init omap_serial_board_init(struct omap_uart_port_info *info)
>   */
>  void __init omap_serial_init(void)
>  {
> -	omap_serial_board_init(NULL);
> +	struct omap_uart_state *uart;
> +
> +	list_for_each_entry(uart, &uart_list, node)
> +		omap_serial_board_init(NULL, uart->num);
>  }
> diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
> index 198d1e6..043b251 100644
> --- a/arch/arm/plat-omap/include/plat/serial.h
> +++ b/arch/arm/plat-omap/include/plat/serial.h
> @@ -111,7 +111,8 @@ struct omap_uart_port_info;
>  
>  extern void omap_serial_init(void);
>  extern int omap_uart_can_sleep(void);
> -extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
> +extern void omap_serial_board_init(struct omap_uart_port_info *platform_data,
> +		u8 port_id);
>  extern void omap_serial_init_port(struct omap_board_data *bdata,
>  		struct omap_uart_port_info *platform_data);
>  #endif
> -- 
> 1.7.5.4
> 


From robherring2 at gmail.com  Tue Mar  6 16:45:11 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue,  6 Mar 2012 15:45:11 -0600
Subject: [PATCH v5 1/7] ARM: provide runtime hook for ioremap/iounmap
In-Reply-To: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
Message-ID: <1331070317-9598-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

We have compile time over-ride of ioremap and iounmap, but an run-time
override is needed for multi-platform builds. This adds an extra function
pointer check, but ioremap is not peformance critical. The option for
compile time selection remains.

The caller variant is used here to provide correct caller information as
ARM can only support level 0 for __builtin_return_address.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/include/asm/io.h |    7 ++++++-
 arch/arm/mm/ioremap.c     |   17 ++++++++++++++---
 2 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 9275828..6c363c1 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -83,6 +83,11 @@ extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, uns
 extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
 extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
 extern void __iounmap(volatile void __iomem *addr);
+extern void __arm_iounmap(volatile void __iomem *addr);
+
+extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+	unsigned int, void *);
+extern void (*arch_iounmap)(volatile void __iomem *);
 
 /*
  * Bad read/write accesses...
@@ -266,7 +271,7 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
  */
 #ifndef __arch_ioremap
 #define __arch_ioremap			__arm_ioremap
-#define __arch_iounmap			__iounmap
+#define __arch_iounmap			__arm_iounmap
 #endif
 
 #define ioremap(cookie,size)		__arch_ioremap((cookie), (size), MT_DEVICE)
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 80632e8..0246290 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -306,11 +306,15 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
 }
 EXPORT_SYMBOL(__arm_ioremap_pfn);
 
+void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+				      unsigned int, void *) =
+	__arm_ioremap_caller;
+
 void __iomem *
 __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 {
-	return __arm_ioremap_caller(phys_addr, size, mtype,
-			__builtin_return_address(0));
+	return arch_ioremap_caller(phys_addr, size, mtype,
+		__builtin_return_address(0));
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
@@ -369,4 +373,11 @@ void __iounmap(volatile void __iomem *io_addr)
 
 	vunmap(addr);
 }
-EXPORT_SYMBOL(__iounmap);
+
+void (*arch_iounmap)(volatile void __iomem *) = __iounmap;
+
+void __arm_iounmap(volatile void __iomem *io_addr)
+{
+	arch_iounmap(io_addr);
+}
+EXPORT_SYMBOL(__arm_iounmap);
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar  6 16:45:12 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue,  6 Mar 2012 15:45:12 -0600
Subject: [PATCH v5 2/7] ARM: imx: convert to common runtime ioremap hook
In-Reply-To: <1331070317-9598-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331070317-9598-2-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert i.MX platforms to use the common run-time ioremap hook instead of
the imx specific hook.

Also, move addr_in_module out of io.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Sascha Hauer <kernel at pengutronix.de>
---
 arch/arm/mach-imx/mm-imx3.c               |   10 +++++-----
 arch/arm/plat-mxc/include/mach/hardware.h |    3 +++
 arch/arm/plat-mxc/include/mach/io.h       |   17 -----------------
 3 files changed, 8 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 8404ee7..04be18d 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -59,8 +59,8 @@ static void imx3_idle(void)
 		: "=r" (reg));
 }
 
-static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
-				  unsigned int mtype)
+static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
+					 unsigned int mtype, void *caller)
 {
 	if (mtype == MT_DEVICE) {
 		/*
@@ -73,7 +73,7 @@ static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
 			mtype = MT_DEVICE_NONSHARED;
 	}
 
-	return __arm_ioremap(phys_addr, size, mtype);
+	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
 }
 
 void imx3_init_l2x0(void)
@@ -132,7 +132,7 @@ void __init imx31_init_early(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX31);
 	mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-	imx_ioremap = imx3_ioremap;
+	arch_ioremap_caller = imx3_ioremap_caller;
 	arm_pm_idle = imx3_idle;
 }
 
@@ -196,7 +196,7 @@ void __init imx35_init_early(void)
 	mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
 	mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
 	arm_pm_idle = imx3_idle;
-	imx_ioremap = imx3_ioremap;
+	arch_ioremap_caller = imx3_ioremap_caller;
 }
 
 void __init mx35_init_irq(void)
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index a599f01..ca06a68 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -28,6 +28,9 @@
 #define IOMEM(addr)	((void __force __iomem *)(addr))
 #endif
 
+#define addr_in_module(addr, mod) \
+	((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
+
 #define IMX_IO_P2V_MODULE(addr, module)					\
 	(((addr) - module ## _BASE_ADDR) < module ## _SIZE ?		\
 	 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index 338300b..ea9d95e 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -14,23 +14,6 @@
 /* Allow IO space to be anywhere in the memory */
 #define IO_SPACE_LIMIT 0xffffffff
 
-#define __arch_ioremap __imx_ioremap
-#define __arch_iounmap __iounmap
-
-#define addr_in_module(addr, mod) \
-	((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
-
-extern void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int);
-
-static inline void __iomem *
-__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
-{
-	if (imx_ioremap != NULL)
-		return imx_ioremap(phys_addr, size, mtype);
-	else
-		return __arm_ioremap(phys_addr, size, mtype);
-}
-
 /* io address mapping macro */
 #define __io(a)		__typesafe_io(a)
 
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar  6 16:45:13 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue,  6 Mar 2012 15:45:13 -0600
Subject: [PATCH v5 3/7] ARM: msm: use runtime ioremap hook
In-Reply-To: <1331070317-9598-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331070317-9598-3-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert msm platforms to use run-time ioremap hook instead of the compile
time hook.

According to David Brown, only the msm7201 needed the ioremap hook.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Tested-by: David Brown <davidb at codeaurora.org>
Acked-by: David Brown <davidb at codeaurora.org>
Cc: Daniel Walker <dwalker at fifo99.com>
Cc: Bryan Huntsman <bryanh at codeaurora.org>
---
 arch/arm/mach-msm/board-halibut.c               |    6 ++++++
 arch/arm/mach-msm/board-trout.c                 |    6 ++++++
 arch/arm/mach-msm/include/mach/io.h             |    5 -----
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |    6 ++++++
 arch/arm/mach-msm/io.c                          |    8 +++-----
 5 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index a60ab6d..3698a37 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -68,6 +68,11 @@ static struct platform_device *devices[] __initdata = {
 
 extern struct sys_timer msm_timer;
 
+static void __init halibut_init_early(void)
+{
+	arch_ioremap_caller = __msm_ioremap_caller;
+}
+
 static void __init halibut_init_irq(void)
 {
 	msm_init_irq();
@@ -96,6 +101,7 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
 	.atag_offset	= 0x100,
 	.fixup		= halibut_fixup,
 	.map_io		= halibut_map_io,
+	.init_early	= halibut_init_early,
 	.init_irq	= halibut_init_irq,
 	.init_machine	= halibut_init,
 	.timer		= &msm_timer,
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 6b9b227..5414f76 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -43,6 +43,11 @@ static struct platform_device *devices[] __initdata = {
 
 extern struct sys_timer msm_timer;
 
+static void __init trout_init_early(void)
+{
+	arch_ioremap_caller = __msm_ioremap_caller;
+}
+
 static void __init trout_init_irq(void)
 {
 	msm_init_irq();
@@ -96,6 +101,7 @@ MACHINE_START(TROUT, "HTC Dream")
 	.atag_offset	= 0x100,
 	.fixup		= trout_fixup,
 	.map_io		= trout_map_io,
+	.init_early	= trout_init_early,
 	.init_irq	= trout_init_irq,
 	.init_machine	= trout_init,
 	.timer		= &msm_timer,
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index dc1b928..c6ff9bb 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -18,11 +18,6 @@
 
 #define IO_SPACE_LIMIT 0xffffffff
 
-#define __arch_ioremap __msm_ioremap
-#define __arch_iounmap __iounmap
-
-void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)    (a)
 
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 8af4612..152b3b7 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -111,5 +111,11 @@
 #define MSM_AD5_PHYS          0xAC000000
 #define MSM_AD5_SIZE          (SZ_1M*13)
 
+#ifndef __ASSEMBLY__
+
+extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+					  unsigned int mtype, void *caller);
+
+#endif
 
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 578b04e..a1e7b11 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -172,8 +172,8 @@ void __init msm_map_msm7x30_io(void)
 }
 #endif /* CONFIG_ARCH_MSM7X30 */
 
-void __iomem *
-__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+				   unsigned int mtype, void *caller)
 {
 	if (mtype == MT_DEVICE) {
 		/* The peripherals in the 88000000 - D0000000 range
@@ -184,7 +184,5 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 			mtype = MT_DEVICE_NONSHARED;
 	}
 
-	return __arm_ioremap_caller(phys_addr, size, mtype,
-		__builtin_return_address(0));
+	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
 }
-EXPORT_SYMBOL(__msm_ioremap);
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar  6 16:45:14 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue,  6 Mar 2012 15:45:14 -0600
Subject: [PATCH v5 4/7] ARM: iop13xx: use runtime ioremap hook
In-Reply-To: <1331070317-9598-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331070317-9598-4-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert iop13xx platforms to use run-time ioremap hook instead of the
compile time hook. The custom ioremap is still needed for 64-bit address
handling.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/mach-iop13xx/include/mach/io.h |    7 -------
 arch/arm/mach-iop13xx/io.c              |   18 ++++++++++--------
 arch/arm/mach-iop13xx/iq81340mc.c       |    1 +
 arch/arm/mach-iop13xx/iq81340sc.c       |    1 +
 4 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index dffb234..2a69fc0 100644
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -26,16 +26,9 @@
 #define __mem_isa(a) (a)
 
 extern void __iomem * __iop13xx_io(unsigned long io_addr);
-extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
-	unsigned int mtype);
-extern void __iop13xx_iounmap(void __iomem *addr);
-
 extern u32 iop13xx_atue_mem_base;
 extern u32 iop13xx_atux_mem_base;
 extern size_t iop13xx_atue_mem_size;
 extern size_t iop13xx_atux_mem_size;
 
-#define __arch_ioremap	__iop13xx_ioremap
-#define __arch_iounmap	__iop13xx_iounmap
-
 #endif
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 48642e6..6dd5b49 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -40,8 +40,8 @@ void * __iomem __iop13xx_io(unsigned long io_addr)
 }
 EXPORT_SYMBOL(__iop13xx_io);
 
-void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
-	unsigned int mtype)
+static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
+	size_t size, unsigned int mtype, void *caller)
 {
 	void __iomem * retval;
 
@@ -76,17 +76,14 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
 		break;
 	default:
 		retval = __arm_ioremap_caller(cookie, size, mtype,
-				__builtin_return_address(0));
+				caller);
 	}
 
 	return retval;
 }
-EXPORT_SYMBOL(__iop13xx_ioremap);
 
-void __iop13xx_iounmap(void __iomem *addr)
+static void __iop13xx_iounmap(volatile void __iomem *addr)
 {
-	extern void __iounmap(volatile void __iomem *addr);
-
 	if (iop13xx_atue_mem_base)
 		if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
 	 	    addr < (void __iomem *) (iop13xx_atue_mem_base +
@@ -110,4 +107,9 @@ void __iop13xx_iounmap(void __iomem *addr)
 skip:
 	return;
 }
-EXPORT_SYMBOL(__iop13xx_iounmap);
+
+void __init iop13xx_init_early(void)
+{
+	arch_ioremap_caller = __iop13xx_ioremap_caller;
+	arch_iounmap = __iop13xx_iounmap;
+}
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index abaee88..5c96b73 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -92,6 +92,7 @@ static struct sys_timer iq81340mc_timer = {
 MACHINE_START(IQ81340MC, "Intel IQ81340MC")
 	/* Maintainer: Dan Williams <dan.j.williams at intel.com> */
 	.atag_offset    = 0x100,
+	.init_early     = iop13xx_init_early,
 	.map_io         = iop13xx_map_io,
 	.init_irq       = iop13xx_init_irq,
 	.timer          = &iq81340mc_timer,
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index 690916a..aa4dd75 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -94,6 +94,7 @@ static struct sys_timer iq81340sc_timer = {
 MACHINE_START(IQ81340SC, "Intel IQ81340SC")
 	/* Maintainer: Dan Williams <dan.j.williams at intel.com> */
 	.atag_offset    = 0x100,
+	.init_early     = iop13xx_init_early,
 	.map_io         = iop13xx_map_io,
 	.init_irq       = iop13xx_init_irq,
 	.timer          = &iq81340sc_timer,
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar  6 16:45:16 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue,  6 Mar 2012 15:45:16 -0600
Subject: [PATCH v5 6/7] ARM: ebsa110: use runtime ioremap hook
In-Reply-To: <1331070317-9598-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331070317-9598-6-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert ebsa110 platforms to use run-time ioremap hook instead of the
compile time hook.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/mach-ebsa110/core.c            |   15 +++++++++++++++
 arch/arm/mach-ebsa110/include/mach/io.h |    9 ---------
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 804c912..e0b831e 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -119,6 +119,20 @@ static void __init ebsa110_map_io(void)
 	iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
 }
 
+static void __iomem *ebsa110_ioremap(unsigned long cookie, size_t size,
+				     unsigned int flags)
+{
+	return (void __iomem *)cookie;
+}
+
+static void ebsa110_iounmap(volatile void __iomem *io_addr)
+{}
+
+static void __init ebsa110_init_early(void)
+{
+	arch_ioremap_caller = ebsa110_ioremap;
+	arch_iounmap = ebsa110_iounmap;
+}
 
 #define PIT_CTRL		(PIT_BASE + 0x0d)
 #define PIT_T2			(PIT_BASE + 0x09)
@@ -315,6 +329,7 @@ MACHINE_START(EBSA110, "EBSA110")
 	.reserve_lp2	= 1,
 	.restart_mode	= 's',
 	.map_io		= ebsa110_map_io,
+	.init_early	= ebsa110_init_early,
 	.init_irq	= ebsa110_init_irq,
 	.timer		= &ebsa110_timer,
 	.restart	= ebsa110_restart,
diff --git a/arch/arm/mach-ebsa110/include/mach/io.h b/arch/arm/mach-ebsa110/include/mach/io.h
index 44679db..11bb079 100644
--- a/arch/arm/mach-ebsa110/include/mach/io.h
+++ b/arch/arm/mach-ebsa110/include/mach/io.h
@@ -62,15 +62,6 @@ void __writel(u32 val, void __iomem *addr);
 #define writew(v,b)		__writew(v,b)
 #define writel(v,b)		__writel(v,b)
 
-static inline void __iomem *__arch_ioremap(unsigned long cookie, size_t size,
-					   unsigned int flags)
-{
-	return (void __iomem *)cookie;
-}
-
-#define __arch_ioremap		__arch_ioremap
-#define __arch_iounmap(cookie)	do { } while (0)
-
 extern void insb(unsigned int port, void *buf, int sz);
 extern void insw(unsigned int port, void *buf, int sz);
 extern void insl(unsigned int port, void *buf, int sz);
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar  6 16:45:15 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue,  6 Mar 2012 15:45:15 -0600
Subject: [PATCH v5 5/7] ARM: ixp4xx: use runtime ioremap hook
In-Reply-To: <1331070317-9598-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331070317-9598-5-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert ixp4xx platforms to use run-time ioremap hook instead of the
compile time hook.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Imre Kaloz <kaloz at openwrt.org>
Cc: Krzysztof Halasa <khc at pm.waw.pl>
---
 arch/arm/mach-ixp4xx/avila-setup.c           |    2 +
 arch/arm/mach-ixp4xx/common.c                |   33 ++++++++++++++++++++++++++
 arch/arm/mach-ixp4xx/coyote-setup.c          |    2 +
 arch/arm/mach-ixp4xx/dsmg600-setup.c         |    1 +
 arch/arm/mach-ixp4xx/fsg-setup.c             |    1 +
 arch/arm/mach-ixp4xx/gateway7001-setup.c     |    1 +
 arch/arm/mach-ixp4xx/goramo_mlr.c            |    1 +
 arch/arm/mach-ixp4xx/gtwx5715-setup.c        |    1 +
 arch/arm/mach-ixp4xx/include/mach/io.h       |   18 --------------
 arch/arm/mach-ixp4xx/include/mach/platform.h |    1 +
 arch/arm/mach-ixp4xx/ixdp425-setup.c         |    4 +++
 arch/arm/mach-ixp4xx/nas100d-setup.c         |    1 +
 arch/arm/mach-ixp4xx/nslu2-setup.c           |    1 +
 arch/arm/mach-ixp4xx/omixp-setup.c           |    3 ++
 arch/arm/mach-ixp4xx/vulcan-setup.c          |    1 +
 arch/arm/mach-ixp4xx/wg302v2-setup.c         |    1 +
 16 files changed, 54 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index a7277ad..90e42e9 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -165,6 +165,7 @@ static void __init avila_init(void)
 MACHINE_START(AVILA, "Gateworks Avila Network Platform")
 	/* Maintainer: Deepak Saxena <dsaxena at plexity.net> */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
@@ -184,6 +185,7 @@ MACHINE_END
 MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
 	/* Maintainer: Tom Billman <kernel at giantshoulderinc.com> */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index a6329a0..c60e7b8 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -31,6 +31,7 @@
 
 #include <mach/udc.h>
 #include <mach/hardware.h>
+#include <mach/io.h>
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -517,3 +518,35 @@ void ixp4xx_restart(char mode, const char *cmd)
 		*IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
 	}
 }
+
+#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+/*
+ * In the case of using indirect PCI, we simply return the actual PCI
+ * address and our read/write implementation use that to drive the
+ * access registers. If something outside of PCI is ioremap'd, we
+ * fallback to the default.
+ */
+
+static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
+					   unsigned int mtype, void *caller)
+{
+	if (!is_pci_memory(addr))
+		return __arm_ioremap_caller(addr, size, mtype, caller);
+
+	return (void __iomem *)addr;
+}
+
+static void ixp4xx_iounmap(void __iomem *addr)
+{
+	if (!is_pci_memory((__force u32)addr))
+		__iounmap(addr);
+}
+
+void __init ixp4xx_init_early(void)
+{
+	arch_ioremap_caller = ixp4xx_ioremap_caller;
+	arch_iounmap = ixp4xx_iounmap;
+}
+#else
+void __init ixp4xx_init_early(void) {}
+#endif
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index a74f86c..1b83110 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -110,6 +110,7 @@ static void __init coyote_init(void)
 MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
 	/* Maintainer: MontaVista Software, Inc. */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
@@ -129,6 +130,7 @@ MACHINE_END
 MACHINE_START(IXDPG425, "Intel IXDPG425")
 	/* Maintainer: MontaVista Software, Inc. */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 67be177..97a0af8 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -280,6 +280,7 @@ MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
 	/* Maintainer: www.nslu2-linux.org */
 	.atag_offset	= 0x100,
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer          = &dsmg600_timer,
 	.init_machine	= dsmg600_init,
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 6d58182..9175a25 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -270,6 +270,7 @@ static void __init fsg_init(void)
 MACHINE_START(FSG, "Freecom FSG-3")
 	/* Maintainer: www.nslu2-linux.org */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index 7ecf9b2..033c717 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -97,6 +97,7 @@ static void __init gateway7001_init(void)
 MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
 	/* Maintainer: Imre Kaloz <kaloz at openwrt.org> */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index c0e3d69..0dda8f6 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -497,6 +497,7 @@ subsys_initcall(gmlr_pci_init);
 MACHINE_START(GORAMO_MLR, "MultiLink")
 	/* Maintainer: Krzysztof Halasa */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index a23f893..18ebc6b 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -165,6 +165,7 @@ static void __init gtwx5715_init(void)
 MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
 	/* Maintainer: George Joseph */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index ffb9d6a..6a52076 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -57,24 +57,6 @@ static inline int is_pci_memory(u32 addr)
 	return (addr >= PCIBIOS_MIN_MEM) && (addr <= 0x4FFFFFFF);
 }
 
-static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size,
-						unsigned int mtype)
-{
-	if (!is_pci_memory(addr))
-		return __arm_ioremap(addr, size, mtype);
-
-	return (void __iomem *)addr;
-}
-
-static inline void __indirect_iounmap(void __iomem *addr)
-{
-	if (!is_pci_memory((__force u32)addr))
-		__iounmap(addr);
-}
-
-#define __arch_ioremap			__indirect_ioremap
-#define __arch_iounmap			__indirect_iounmap
-
 #define writeb(v, p)			__indirect_writeb(v, p)
 #define writew(v, p)			__indirect_writew(v, p)
 #define writel(v, p)			__indirect_writel(v, p)
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index df9250b..b66bedc 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -121,6 +121,7 @@ extern unsigned long ixp4xx_timer_freq;
  * Functions used by platform-level setup code
  */
 extern void ixp4xx_map_io(void);
+extern void ixp4xx_init_early(void);
 extern void ixp4xx_init_irq(void);
 extern void ixp4xx_sys_init(void);
 extern void ixp4xx_timer_init(void);
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 8a38b39..3d742ae 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -254,6 +254,7 @@ static void __init ixdp425_init(void)
 MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
 	/* Maintainer: MontaVista Software, Inc. */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
@@ -269,6 +270,7 @@ MACHINE_END
 MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
 	/* Maintainer: MontaVista Software, Inc. */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
@@ -283,6 +285,7 @@ MACHINE_END
 MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
 	/* Maintainer: MontaVista Software, Inc. */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
@@ -297,6 +300,7 @@ MACHINE_END
 MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
 	/* Maintainer: MontaVista Software, Inc. */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index 1010eb7..33cb095 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -315,6 +315,7 @@ MACHINE_START(NAS100D, "Iomega NAS 100d")
 	/* Maintainer: www.nslu2-linux.org */
 	.atag_offset	= 0x100,
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer          = &ixp4xx_timer,
 	.init_machine	= nas100d_init,
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index aa355c3..e2903fa 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -301,6 +301,7 @@ MACHINE_START(NSLU2, "Linksys NSLU2")
 	/* Maintainer: www.nslu2-linux.org */
 	.atag_offset	= 0x100,
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer          = &nslu2_timer,
 	.init_machine	= nslu2_init,
diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c
index 0940869..158ddb7 100644
--- a/arch/arm/mach-ixp4xx/omixp-setup.c
+++ b/arch/arm/mach-ixp4xx/omixp-setup.c
@@ -243,6 +243,7 @@ static void __init omixp_init(void)
 MACHINE_START(DEVIXP, "Omicron DEVIXP")
 	.atag_offset    = 0x100,
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer          = &ixp4xx_timer,
 	.init_machine	= omixp_init,
@@ -254,6 +255,7 @@ MACHINE_END
 MACHINE_START(MICCPT, "Omicron MICCPT")
 	.atag_offset    = 0x100,
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer          = &ixp4xx_timer,
 	.init_machine	= omixp_init,
@@ -268,6 +270,7 @@ MACHINE_END
 MACHINE_START(MIC256, "Omicron MIC256")
 	.atag_offset    = 0x100,
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer          = &ixp4xx_timer,
 	.init_machine	= omixp_init,
diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c
index 9dec206..2798f43 100644
--- a/arch/arm/mach-ixp4xx/vulcan-setup.c
+++ b/arch/arm/mach-ixp4xx/vulcan-setup.c
@@ -237,6 +237,7 @@ static void __init vulcan_init(void)
 MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
 	/* Maintainer: Marc Zyngier <maz at misterjones.org> */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index 5ac0f0a..a785175 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -98,6 +98,7 @@ static void __init wg302v2_init(void)
 MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
 	/* Maintainer: Imre Kaloz <kaloz at openwrt.org> */
 	.map_io		= ixp4xx_map_io,
+	.init_early	= ixp4xx_init_early,
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.atag_offset	= 0x100,
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar  6 16:45:17 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue,  6 Mar 2012 15:45:17 -0600
Subject: [PATCH v5 7/7] ARM: remove compile time __arch_ioremap/__arch_iounmap
In-Reply-To: <1331070317-9598-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331070317-9598-7-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Now that all custom ioremap/iounmap users are converted to runtime hook,
remove the compile time defines.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/include/asm/io.h |   15 +++++----------
 1 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 6c363c1..6f7555d 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -269,16 +269,11 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
  * Documentation/io-mapping.txt.
  *
  */
-#ifndef __arch_ioremap
-#define __arch_ioremap			__arm_ioremap
-#define __arch_iounmap			__arm_iounmap
-#endif
-
-#define ioremap(cookie,size)		__arch_ioremap((cookie), (size), MT_DEVICE)
-#define ioremap_nocache(cookie,size)	__arch_ioremap((cookie), (size), MT_DEVICE)
-#define ioremap_cached(cookie,size)	__arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
-#define ioremap_wc(cookie,size)		__arch_ioremap((cookie), (size), MT_DEVICE_WC)
-#define iounmap				__arch_iounmap
+#define ioremap(cookie,size)		__arm_ioremap((cookie), (size), MT_DEVICE)
+#define ioremap_nocache(cookie,size)	__arm_ioremap((cookie), (size), MT_DEVICE)
+#define ioremap_cached(cookie,size)	__arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
+#define ioremap_wc(cookie,size)		__arm_ioremap((cookie), (size), MT_DEVICE_WC)
+#define iounmap				__arm_iounmap
 
 /*
  * io{read,write}{8,16,32} macros
-- 
1.7.5.4



From nico at fluxnic.net  Tue Mar  6 16:57:21 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 06 Mar 2012 16:57:21 -0500 (EST)
Subject: [PATCH v5 1/7] ARM: provide runtime hook for ioremap/iounmap
In-Reply-To: <1331070317-9598-1-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203061656380.31242@xanadu.home>

On Tue, 6 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> We have compile time over-ride of ioremap and iounmap, but an run-time
> override is needed for multi-platform builds. This adds an extra function
> pointer check, but ioremap is not peformance critical. The option for
> compile time selection remains.
> 
> The caller variant is used here to provide correct caller information as
> ARM can only support level 0 for __builtin_return_address.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>

Reviewed-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/include/asm/io.h |    7 ++++++-
>  arch/arm/mm/ioremap.c     |   17 ++++++++++++++---
>  2 files changed, 20 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
> index 9275828..6c363c1 100644
> --- a/arch/arm/include/asm/io.h
> +++ b/arch/arm/include/asm/io.h
> @@ -83,6 +83,11 @@ extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, uns
>  extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
>  extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
>  extern void __iounmap(volatile void __iomem *addr);
> +extern void __arm_iounmap(volatile void __iomem *addr);
> +
> +extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
> +	unsigned int, void *);
> +extern void (*arch_iounmap)(volatile void __iomem *);
>  
>  /*
>   * Bad read/write accesses...
> @@ -266,7 +271,7 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
>   */
>  #ifndef __arch_ioremap
>  #define __arch_ioremap			__arm_ioremap
> -#define __arch_iounmap			__iounmap
> +#define __arch_iounmap			__arm_iounmap
>  #endif
>  
>  #define ioremap(cookie,size)		__arch_ioremap((cookie), (size), MT_DEVICE)
> diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
> index 80632e8..0246290 100644
> --- a/arch/arm/mm/ioremap.c
> +++ b/arch/arm/mm/ioremap.c
> @@ -306,11 +306,15 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
>  }
>  EXPORT_SYMBOL(__arm_ioremap_pfn);
>  
> +void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
> +				      unsigned int, void *) =
> +	__arm_ioremap_caller;
> +
>  void __iomem *
>  __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
>  {
> -	return __arm_ioremap_caller(phys_addr, size, mtype,
> -			__builtin_return_address(0));
> +	return arch_ioremap_caller(phys_addr, size, mtype,
> +		__builtin_return_address(0));
>  }
>  EXPORT_SYMBOL(__arm_ioremap);
>  
> @@ -369,4 +373,11 @@ void __iounmap(volatile void __iomem *io_addr)
>  
>  	vunmap(addr);
>  }
> -EXPORT_SYMBOL(__iounmap);
> +
> +void (*arch_iounmap)(volatile void __iomem *) = __iounmap;
> +
> +void __arm_iounmap(volatile void __iomem *io_addr)
> +{
> +	arch_iounmap(io_addr);
> +}
> +EXPORT_SYMBOL(__arm_iounmap);
> -- 
> 1.7.5.4
> 


From nico at fluxnic.net  Tue Mar  6 17:01:11 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 06 Mar 2012 17:01:11 -0500 (EST)
Subject: [PATCH v5 7/7] ARM: remove compile time
 __arch_ioremap/__arch_iounmap
In-Reply-To: <1331070317-9598-7-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
 <1331070317-9598-7-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203061700490.31242@xanadu.home>

On Tue, 6 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> Now that all custom ioremap/iounmap users are converted to runtime hook,
> remove the compile time defines.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/include/asm/io.h |   15 +++++----------
>  1 files changed, 5 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
> index 6c363c1..6f7555d 100644
> --- a/arch/arm/include/asm/io.h
> +++ b/arch/arm/include/asm/io.h
> @@ -269,16 +269,11 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
>   * Documentation/io-mapping.txt.
>   *
>   */
> -#ifndef __arch_ioremap
> -#define __arch_ioremap			__arm_ioremap
> -#define __arch_iounmap			__arm_iounmap
> -#endif
> -
> -#define ioremap(cookie,size)		__arch_ioremap((cookie), (size), MT_DEVICE)
> -#define ioremap_nocache(cookie,size)	__arch_ioremap((cookie), (size), MT_DEVICE)
> -#define ioremap_cached(cookie,size)	__arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
> -#define ioremap_wc(cookie,size)		__arch_ioremap((cookie), (size), MT_DEVICE_WC)
> -#define iounmap				__arch_iounmap
> +#define ioremap(cookie,size)		__arm_ioremap((cookie), (size), MT_DEVICE)
> +#define ioremap_nocache(cookie,size)	__arm_ioremap((cookie), (size), MT_DEVICE)
> +#define ioremap_cached(cookie,size)	__arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
> +#define ioremap_wc(cookie,size)		__arm_ioremap((cookie), (size), MT_DEVICE_WC)
> +#define iounmap				__arm_iounmap
>  
>  /*
>   * io{read,write}{8,16,32} macros
> -- 
> 1.7.5.4
> 


From linus.walleij at stericsson.com  Tue Mar  6 17:05:09 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 6 Mar 2012 23:05:09 +0100
Subject: [PATCH 1/4] pinctrl: introduce generic pin config
Message-ID: <1331071509-24661-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This is a split-off from the earlier patch set which adds generic
pin configuration for the pin controllers that want it. Since
we may have a system with mixed generic and custom pin controllers,
we pass a boolean in the pin controller ops vtable to indicate
if it is generic.

ChangeLog v1->v5:
- Follow parent patch versioning number system.
- Document the semantic meaning of return values from pin config
  get functions, so we can iterate over pins and check their
  properties from debugfs as part of the generic config code.
- Use proper cast functions in the generic debugfs pin config
  file.
- Expand generic config to optionally cover groups too.
ChangeLog v5->v6:
- Update to match underlying changes.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/Kconfig                 |    4 +
 drivers/pinctrl/Makefile                |    1 +
 drivers/pinctrl/pinconf-generic.c       |  123 ++++++++++++++++++++++++++
 drivers/pinctrl/pinconf.c               |    6 +-
 drivers/pinctrl/pinconf.h               |   43 +++++++++-
 include/linux/pinctrl/pinconf-generic.h |  147 +++++++++++++++++++++++++++++++
 include/linux/pinctrl/pinconf.h         |    5 +
 7 files changed, 325 insertions(+), 4 deletions(-)
 create mode 100644 drivers/pinctrl/pinconf-generic.c
 create mode 100644 include/linux/pinctrl/pinconf-generic.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 3bea79f..ef197cc 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -17,6 +17,10 @@ config PINMUX
 config PINCONF
 	bool "Support pin configuration controllers"
 
+config GENERIC_PINCONF
+	bool
+	select PINCONF
+
 config DEBUG_PINCTRL
 	bool "Debug PINCTRL calls"
 	depends on DEBUG_KERNEL
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index c95d91e..5a46679 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -5,6 +5,7 @@ ccflags-$(CONFIG_DEBUG_PINCTRL)	+= -DDEBUG
 obj-$(CONFIG_PINCTRL)		+= core.o
 obj-$(CONFIG_PINMUX)		+= pinmux.o
 obj-$(CONFIG_PINCONF)		+= pinconf.o
+obj-$(CONFIG_GENERIC_PINCONF)	+= pinconf-generic.o
 obj-$(CONFIG_PINCTRL_PXA3xx)	+= pinctrl-pxa3xx.o
 obj-$(CONFIG_PINCTRL_MMP2)	+= pinctrl-mmp2.o
 obj-$(CONFIG_PINCTRL_PXA168)	+= pinctrl-pxa168.o
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
new file mode 100644
index 0000000..594b820
--- /dev/null
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -0,0 +1,123 @@
+/*
+ * Core driver for the generic pin config portions of the pin control subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ *
+ * Author: Linus Walleij <linus.walleij at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#define pr_fmt(fmt) "generic pinconfig core: " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include "core.h"
+#include "pinconf.h"
+
+#ifdef CONFIG_DEBUG_FS
+
+struct pin_config_item {
+	const enum pin_config_param param;
+	const char * const display;
+	const char * const format;
+};
+
+#define PCONFDUMP(a, b, c) { .param = a, .display = b, .format = c }
+
+struct pin_config_item conf_items[] = {
+	PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL),
+	PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL),
+	PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", "Ohm"),
+	PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", "Ohm"),
+	PCONFDUMP(PIN_CONFIG_BIAS_HIGH, "input bias high", NULL),
+	PCONFDUMP(PIN_CONFIG_BIAS_GROUND, "input bias ground", NULL),
+	PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", "X stages"),
+	PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", "X stages"),
+	PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", "X stages"),
+	PCONFDUMP(PIN_CONFIG_DRIVE_OFF, "output drive off", NULL),
+	PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL),
+	PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "time units"),
+	PCONFDUMP(PIN_CONFIG_SLEW_RATE_RISING, "output slew rate rising", "of max"),
+	PCONFDUMP(PIN_CONFIG_SLEW_RATE_FALLING, "output slew rate falling", "of max"),
+	PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector"),
+	PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode"),
+	PCONFDUMP(PIN_CONFIG_WAKEUP, "input wakeup", NULL),
+};
+
+void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
+			      struct seq_file *s, unsigned pin)
+{
+	const struct pinconf_ops *ops = pctldev->desc->confops;
+	int i;
+
+	if (!ops->is_generic)
+		return;
+
+	for(i = 0; i < ARRAY_SIZE(conf_items); i++) {
+		unsigned long config;
+		int ret;
+
+		/* We want to check out this parameter */
+		config = to_config_packed(conf_items[i].param, 0);
+		ret = pin_config_get_for_pin(pctldev, pin, &config);
+		/* These are legal errors */
+		if (ret == -EINVAL || ret == -ENOTSUPP)
+			continue;
+		if (ret) {
+			seq_printf(s, "ERROR READING CONFIG SETTING %d ", i);
+			continue;
+		}
+		/* Space between multiple configs */
+		seq_puts(s, " ");
+		seq_puts(s, conf_items[i].display);
+		/* Print unit if available */
+		if (conf_items[i].format && to_config_argument(config) != 0)
+			seq_printf(s, " (%u %s)", to_config_argument(config),
+				   conf_items[i].format);
+	}
+}
+
+void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
+			      struct seq_file *s, const char *gname)
+{
+	const struct pinconf_ops *ops = pctldev->desc->confops;
+	int i;
+
+	if (!ops->is_generic)
+		return;
+
+	for(i = 0; i < ARRAY_SIZE(conf_items); i++) {
+		unsigned long config;
+		int ret;
+
+		/* We want to check out this parameter */
+		config = to_config_packed(conf_items[i].param, 0);
+		ret = pin_config_group_get(dev_name(pctldev->dev), gname,
+					   &config);
+		/* These are legal errors */
+		if (ret == -EINVAL || ret == -ENOTSUPP)
+			continue;
+		if (ret) {
+			seq_printf(s, "ERROR READING CONFIG SETTING %d ", i);
+			continue;
+		}
+		/* Space between multiple configs */
+		seq_puts(s, " ");
+		seq_puts(s, conf_items[i].display);
+		/* Print unit if available */
+		if (conf_items[i].format && config != 0)
+			seq_printf(s, " (%u %s)", to_config_argument(config),
+				   conf_items[i].format);
+	}
+}
+
+#endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 84869f2..247b9f2 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -54,7 +54,7 @@ int pinconf_validate_map(struct pinctrl_map const *map, int i)
 	return 0;
 }
 
-static int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
+int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
 			   unsigned long *config)
 {
 	const struct pinconf_ops *ops = pctldev->desc->confops;
@@ -432,6 +432,8 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
 {
 	const struct pinconf_ops *ops = pctldev->desc->confops;
 
+	/* no-op when not using generic pin config */
+	pinconf_generic_dump_pin(pctldev, s, pin);
 	if (ops && ops->pin_config_dbg_show)
 		ops->pin_config_dbg_show(pctldev, s, pin);
 }
@@ -475,6 +477,8 @@ static void pinconf_dump_group(struct pinctrl_dev *pctldev,
 {
 	const struct pinconf_ops *ops = pctldev->desc->confops;
 
+	/* no-op when not using generic pin config */
+	pinconf_generic_dump_group(pctldev, s, gname);
 	if (ops && ops->pin_config_group_dbg_show)
 		ops->pin_config_group_dbg_show(pctldev, s, selector);
 }
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index 0ded227..54510de 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -14,20 +14,26 @@
 #ifdef CONFIG_PINCONF
 
 int pinconf_check_ops(struct pinctrl_dev *pctldev);
-
 int pinconf_validate_map(struct pinctrl_map const *map, int i);
-
 int pinconf_map_to_setting(struct pinctrl_map const *map,
 			  struct pinctrl_setting *setting);
 void pinconf_free_setting(struct pinctrl_setting const *setting);
 int pinconf_apply_setting(struct pinctrl_setting const *setting);
-
 void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
 void pinconf_show_setting(struct seq_file *s,
 			  struct pinctrl_setting const *setting);
 void pinconf_init_device_debugfs(struct dentry *devroot,
 				 struct pinctrl_dev *pctldev);
 
+/*
+ * You will only be interested in these if you're using PINCONF
+ * so don't supply any stubs for these.
+ */
+int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
+			   unsigned long *config);
+int pin_config_group_get(const char *dev_name, const char *pin_group,
+			 unsigned long *config);
+
 #else
 
 static inline int pinconf_check_ops(struct pinctrl_dev *pctldev)
@@ -71,3 +77,34 @@ static inline void pinconf_init_device_debugfs(struct dentry *devroot,
 }
 
 #endif
+
+/*
+ * The following functions are available if the driver uses the generic
+ * pin config.
+ */
+
+#ifdef CONFIG_GENERIC_PINCONF
+
+void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
+			      struct seq_file *s, unsigned pin);
+
+void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
+			      struct seq_file *s, const char *gname);
+
+#else
+
+static inline void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
+					    struct seq_file *s,
+					    unsigned pin)
+{
+	return;
+}
+
+static inline void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
+					      struct seq_file *s,
+					      const char *gname)
+{
+	return;
+}
+
+#endif
diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
new file mode 100644
index 0000000..a47613b
--- /dev/null
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -0,0 +1,147 @@
+/*
+ * Interface the generic pinconfig portions of the pinctrl subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * This interface is used in the core to keep track of pins.
+ *
+ * Author: Linus Walleij <linus.walleij at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __LINUX_PINCTRL_PINCONF_GENERIC_H
+#define __LINUX_PINCTRL_PINCONF_GENERIC_H
+
+/*
+ * You shouldn't even be able to compile with these enums etc unless you're
+ * using generic pin config. That is why this is defined out.
+ */
+#ifdef CONFIG_GENERIC_PINCONF
+
+/**
+ * enum pin_config_param - possible pin configuration parameters
+ * @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a
+ *	transition from say pull-up to pull-down implies that you disable
+ *	pull-up in the process, this setting disables all biasing.
+ * @PIN_CONFIG_BIAS_HIGH_IMPEDANCE: the pin will be set to a high impedance
+ *	mode, also know as "third-state" (tristate) or "high-Z" or "floating".
+ *	On output pins this effectively disconnects the pin, which is useful
+ *	if for example some other pin is going to drive the signal connected
+ *	to it for a while. Pins used for input are usually always high
+ *	impedance.
+ * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
+ *	impedance to VDD), if the controller supports specifying a certain
+ *	pull-up resistance, this is given as an argument (in Ohms) when
+ *	setting this parameter.
+ * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
+ *	impedance to GROUND), if the controller supports specifying a certain
+ *	pull-down resistance, this is given as an argument (in Ohms) when
+ *	setting this parameter.
+ * @PIN_CONFIG_BIAS_HIGH: the pin will be wired high, connected to VDD
+ * @PIN_CONFIG_BIAS_GROUND: the pin will be grounded, connected to GROUND
+ * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
+ *	low, this is the most typical case and is typically achieved with two
+ *	active transistors on the output. If the pin can support different
+ *	drive strengths for push/pull, the strength is given in the argument
+ *	as the number of driving stages vs nominal load impedance, so say
+ *	quadruple driving stages (usually 8 transistors rather than two) will
+ *	be configured with the 8 passed as argument.
+ * @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open
+ *	collector) which means it is usually wired with other output ports
+ *	which are then pulled up with an external resistor. If the pin can
+ *	support different drive strengths for the open drain pin, the format
+ *	is the same as for PIN_CONFIG_DRIVE_PUSH_PULL.
+ * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open drain
+ *	(open emitter) which is the same as open drain but pulled to ground.
+ *	If the pin can support different drive strengths for the open drain
+ *	pin, the format is the same as for PIN_CONFIG_DRIVE_PUSH_PULL.
+ * @PIN_CONFIG_DRIVE_OFF: the pin is set to inactive drive mode, off.
+ * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in
+ *	schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis,
+ *	the threshold value is given on a custom format as argument when
+ *	setting pins to this mode. The argument zero turns the schmitt trigger
+ *	off.
+ * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
+ *	which means it will wait for signals to settle when reading inputs. The
+ *	argument gives the debounce time on a custom format. Setting the
+ *	argument to zero turns debouncing off.
+ * @PIN_CONFIG_SLEW_RATE_RISING: this will configure the slew rate for rising
+ *	signals on the pin. The argument gives the rise time in fractions
+ *	compared to maximum rise time, 0 means nominal rise time. If you can
+ *	control slew rate in 4 steps these will likely be equidistant like
+ *	1/4, 1/2, 3/4 or full nominal slew rate, which means argument 4 gives
+ *	you 1/4 of nominal slew rate and the argument 4 has the same meaning
+ *	as 0 - nominal slew rate (fastest possible, steep edges). You may want
+ *	to adjust slew rates so that signal edges don't get too steep, causing
+ *	disturbances in surrounding electronics known as electromagnetic
+ *	interference (EMI) for example.
+ * @PIN_CONFIG_SLEW_RATE_FALLING: this will configure the slew rate for falling
+ *	signals on the pin. The argument gives the fall time in fractions
+ *	compared to nominal fall time.
+ * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
+ *	supplies, the argument to this parameter (on a custom format) tells
+ *	the driver which alternative power source to use.
+ * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
+ *	operation, if several modes of operation are supported these can be
+ *	passed in the argument on a custom form, else just use argument 1
+ *	to indicate low power mode, argument 0 turns low power mode off.
+ * @PIN_CONFIG_WAKEUP: this will configure an input pin such that if a
+ *	signal transition arrives at the pin when the pin controller/system
+ *	is sleeping, it will wake up the system if argument 1 is passed along.
+ *	Pass argument 0 to turn wakeup enablement off.
+ * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
+ *	you need to pass in custom configurations to the pin controller, use
+ *	PIN_CONFIG_END+1 as the base offset.
+ */
+enum pin_config_param {
+	PIN_CONFIG_BIAS_DISABLE,
+	PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
+	PIN_CONFIG_BIAS_PULL_UP,
+	PIN_CONFIG_BIAS_PULL_DOWN,
+	PIN_CONFIG_BIAS_HIGH,
+	PIN_CONFIG_BIAS_GROUND,
+	PIN_CONFIG_DRIVE_PUSH_PULL,
+	PIN_CONFIG_DRIVE_OPEN_DRAIN,
+	PIN_CONFIG_DRIVE_OPEN_SOURCE,
+	PIN_CONFIG_DRIVE_OFF,
+	PIN_CONFIG_INPUT_SCHMITT,
+	PIN_CONFIG_INPUT_DEBOUNCE,
+	PIN_CONFIG_SLEW_RATE_RISING,
+	PIN_CONFIG_SLEW_RATE_FALLING,
+	PIN_CONFIG_POWER_SOURCE,
+	PIN_CONFIG_LOW_POWER_MODE,
+	PIN_CONFIG_WAKEUP,
+	PIN_CONFIG_END,
+};
+
+/*
+ * The following inlines stuffs a configuration parameter and data value
+ * into and out of an unsigned long argument, as used by the generic pin config
+ * system. We put the parameter in the lower 16 bits and the argument in the
+ * upper 16 bits.
+ */
+
+static inline enum pin_config_param to_config_param(unsigned long config)
+{
+	return (enum pin_config_param) (config & 0xffffUL);
+}
+
+static inline u16 to_config_argument(unsigned long config)
+{
+	return (enum pin_config_param) ((config >> 16) & 0xffffUL);
+}
+
+static inline unsigned long to_config_packed(enum pin_config_param param,
+					     u16 argument)
+{
+	return (argument << 16) | ((unsigned long) param & 0xffffUL);
+}
+
+/*
+ * Helpful configuration macro to be used in tables etc.
+ */
+#define PIN_CONF_PACKED(p, a) ((a << 16) | ((unsigned long) p & 0xffffUL))
+
+#endif /* CONFIG_GENERIC_PINCONF */
+
+#endif /* __LINUX_PINCTRL_PINCONF_GENERIC_H */
diff --git a/include/linux/pinctrl/pinconf.h b/include/linux/pinctrl/pinconf.h
index f8cf156..ec431f0 100644
--- a/include/linux/pinctrl/pinconf.h
+++ b/include/linux/pinctrl/pinconf.h
@@ -20,6 +20,8 @@ struct seq_file;
 /**
  * struct pinconf_ops - pin config operations, to be implemented by
  * pin configuration capable drivers.
+ * @is_generic: for pin controllers that want to use the generic interface,
+ *	this flag tells the framework that it's generic.
  * @pin_config_get: get the config of a certain pin, if the requested config
  *	is not available on this controller this should return -ENOTSUPP
  *	and if it is available but disabled it should return -EINVAL
@@ -33,6 +35,9 @@ struct seq_file;
  *	per-device info for a certain group in debugfs
  */
 struct pinconf_ops {
+#ifdef CONFIG_GENERIC_PINCONF
+	bool is_generic;
+#endif
 	int (*pin_config_get) (struct pinctrl_dev *pctldev,
 			       unsigned pin,
 			       unsigned long *config);
-- 
1.7.8



From linus.walleij at stericsson.com  Tue Mar  6 17:05:33 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 6 Mar 2012 23:05:33 +0100
Subject: [PATCH 3/4] pinctrl: support pinconfig on the U300
Message-ID: <1331071533-24789-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds pin configuration support for the U300 driver pair,
we can now read out the biasing and drive mode in debugfs and
configure it using the new configuration API.

ChangeLog v1->v2:
- Migrate to pin config and generic pin config changes.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/Kconfig          |    1 +
 drivers/pinctrl/pinctrl-coh901.c |   77 ++++++++++++++++++++++++++++++++++----
 drivers/pinctrl/pinctrl-coh901.h |    5 ++
 drivers/pinctrl/pinctrl-u300.c   |   60 +++++++++++++++++++++++++++++
 4 files changed, 135 insertions(+), 8 deletions(-)
 create mode 100644 drivers/pinctrl/pinctrl-coh901.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ef197cc..d2412b1 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -58,6 +58,7 @@ config PINCTRL_U300
 	bool "U300 pin controller driver"
 	depends on ARCH_U300
 	select PINMUX
+	select GENERIC_PINCONF
 
 config PINCTRL_COH901
 	bool "ST-Ericsson U300 COH 901 335/571 GPIO"
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 724234c..0797eba 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -23,7 +23,9 @@
 #include <linux/list.h>
 #include <linux/slab.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <mach/gpio-u300.h>
+#include "pinctrl-coh901.h"
 
 /*
  * Register definitions for COH 901 335 variant
@@ -418,8 +420,68 @@ static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 	return retirq;
 }
 
-static int u300_gpio_config(struct gpio_chip *chip, unsigned offset,
-			    enum pin_config_param param, unsigned long data)
+/* Returning -EINVAL means "supported but not available" */
+int u300_gpio_config_get(struct gpio_chip *chip,
+			 unsigned offset,
+			 unsigned long *config)
+{
+	struct u300_gpio *gpio = to_u300_gpio(chip);
+	enum pin_config_param param = (enum pin_config_param) *config;
+	bool biasmode;
+	u32 drmode;
+
+	/* One bit per pin, clamp to bool range */
+	biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
+
+	/* Mask out the two bits for this pin and shift to bits 0,1 */
+	drmode = readl(U300_PIN_REG(offset, pcr));
+	drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
+	drmode >>= ((offset & 0x07) << 1);
+
+	switch(param) {
+	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+		*config = 0;
+		if (biasmode)
+			return 0;
+		else
+			return -EINVAL;
+		break;
+	case PIN_CONFIG_BIAS_PULL_UP:
+		*config = 0;
+		if (!biasmode)
+			return 0;
+		else
+			return -EINVAL;
+		break;
+	case PIN_CONFIG_DRIVE_PUSH_PULL:
+		*config = 0;
+		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
+			return 0;
+		else
+			return -EINVAL;
+		break;
+	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+		*config = 0;
+		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
+			return 0;
+		else
+			return -EINVAL;
+		break;
+	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
+		*config = 0;
+		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
+			return 0;
+		else
+			return -EINVAL;
+		break;
+	default:
+		break;
+	}
+	return -ENOTSUPP;
+}
+
+int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
+			 enum pin_config_param param)
 {
 	struct u300_gpio *gpio = to_u300_gpio(chip);
 	unsigned long flags;
@@ -620,13 +682,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
 		u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
 
 		/* Deactivate bias mode for output */
-		u300_gpio_config(&gpio->chip, offset,
-				 PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
-				 0);
+		u300_gpio_config_set(&gpio->chip, offset,
+				     PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
 
 		/* Set drive mode for output */
-		u300_gpio_config(&gpio->chip, offset,
-				 PIN_CONFIG_DRIVE_PUSH_PULL, 0);
+		u300_gpio_config_set(&gpio->chip, offset,
+				     PIN_CONFIG_DRIVE_PUSH_PULL);
 
 		dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
 			offset, conf->outval);
@@ -637,7 +698,7 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
 		u300_gpio_set(&gpio->chip, offset, 0);
 
 		/* Set bias mode for input */
-		u300_gpio_config(&gpio->chip, offset, conf->bias_mode, 0);
+		u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
 
 		dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
 			offset, conf->bias_mode);
diff --git a/drivers/pinctrl/pinctrl-coh901.h b/drivers/pinctrl/pinctrl-coh901.h
new file mode 100644
index 0000000..8729422
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-coh901.h
@@ -0,0 +1,5 @@
+int u300_gpio_config_get(struct gpio_chip *chip,
+			 unsigned offset,
+			 unsigned long *config);
+int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
+			 enum pin_config_param param);
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index fc4a281..b18101a 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -19,6 +19,9 @@
 #include <linux/err.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include "pinctrl-coh901.h"
 
 /*
  * Register definitions for the U300 Padmux control registers in the
@@ -1044,12 +1047,69 @@ static struct pinctrl_gpio_range u300_gpio_ranges[] = {
 	U300_GPIO_RANGE(25, 181, 1),
 };
 
+static struct pinctrl_gpio_range *u300_match_gpio_range(unsigned pin)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++) {
+		struct pinctrl_gpio_range *range;
+
+		range = &u300_gpio_ranges[i];
+		if (pin >= range->pin_base &&
+		    pin <= (range->pin_base + range->npins - 1))
+			return range;
+	}
+	return NULL;
+}
+
+int u300_pin_config_get(struct pinctrl_dev *pctldev,
+			unsigned pin,
+			unsigned long *config)
+{
+	struct pinctrl_gpio_range *range = u300_match_gpio_range(pin);
+
+	/* We get config for those pins we CAN get it for and that's it */
+	if (!range)
+		return -ENOTSUPP;
+
+	return u300_gpio_config_get(range->gc,
+				    (pin - range->pin_base + range->base),
+				    config);
+}
+
+int u300_pin_config_set(struct pinctrl_dev *pctldev,
+			unsigned pin,
+			unsigned long config)
+{
+	struct pinctrl_gpio_range *range = u300_match_gpio_range(pin);
+	int ret;
+
+	if (!range)
+		return -EINVAL;
+
+	/* Note: none of these configurations take any argument */
+	ret = u300_gpio_config_set(range->gc,
+				   (pin - range->pin_base + range->base),
+				   to_config_param(config));
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static struct pinconf_ops u300_pconf_ops = {
+	.is_generic = true,
+	.pin_config_get = u300_pin_config_get,
+	.pin_config_set = u300_pin_config_set,
+};
+
 static struct pinctrl_desc u300_pmx_desc = {
 	.name = DRIVER_NAME,
 	.pins = u300_pads,
 	.npins = ARRAY_SIZE(u300_pads),
 	.pctlops = &u300_pctrl_ops,
 	.pmxops = &u300_pmx_ops,
+	.confops = &u300_pconf_ops,
 	.owner = THIS_MODULE,
 };
 
-- 
1.7.8



From linus.walleij at stericsson.com  Tue Mar  6 17:05:47 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 6 Mar 2012 23:05:47 +0100
Subject: [PATCH 4/4] ARM: u300: configure some pins as an example
Message-ID: <1331071547-25109-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

To show how the pin configuration is used on the U300, let's
include some configs for two GPIO pins.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/core.c |   25 +++++++++++++++++++++++--
 1 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index f326d31..ab48547 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -27,6 +27,7 @@
 #include <linux/mtd/fsmc.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/dma-mapping.h>
 
 #include <asm/types.h>
@@ -1605,7 +1606,23 @@ static struct platform_device dma_device = {
 	},
 };
 
-/* Pinmux settings */
+static unsigned long g0d_conf[] = {
+	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static unsigned long g1d_conf[] = {
+	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static unsigned long g0i_conf[] = {
+	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static unsigned long g1i_conf[] = {
+	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+/* Pin control settings */
 static struct pinctrl_map __initdata u300_pinmux_map[] = {
 	/* anonymous maps for chip power and EMIFs */
 	PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
@@ -1615,6 +1632,11 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
 	PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
+	/* some pin configurations */
+	PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "GPIO0", g0d_conf),
+	PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "GPIO1", g1d_conf),
+	PIN_MAP_CONFIGS_PIN("mmci", "idle", "pinctrl-u300", "GPIO0", g0i_conf),
+	PIN_MAP_CONFIGS_PIN("mmci", "idle", "pinctrl-u300", "GPIO1", g1i_conf),
 };
 
 struct u300_mux_hog {
@@ -1640,7 +1662,6 @@ static int __init u300_pinctrl_fetch(void)
 
 	for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
 		struct pinctrl *p;
-		int ret;
 
 		p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
 		if (IS_ERR(p)) {
-- 
1.7.8



From nico at fluxnic.net  Tue Mar  6 17:06:34 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 06 Mar 2012 17:06:34 -0500 (EST)
Subject: [PATCH v5 6/7] ARM: ebsa110: use runtime ioremap hook
In-Reply-To: <1331070317-9598-6-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
 <1331070317-9598-6-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203061704180.31242@xanadu.home>

On Tue, 6 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> Convert ebsa110 platforms to use run-time ioremap hook instead of the
> compile time hook.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> ---
>  arch/arm/mach-ebsa110/core.c            |   15 +++++++++++++++
>  arch/arm/mach-ebsa110/include/mach/io.h |    9 ---------
>  2 files changed, 15 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
> index 804c912..e0b831e 100644
> --- a/arch/arm/mach-ebsa110/core.c
> +++ b/arch/arm/mach-ebsa110/core.c
> @@ -119,6 +119,20 @@ static void __init ebsa110_map_io(void)
>  	iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
>  }
>  
> +static void __iomem *ebsa110_ioremap(unsigned long cookie, size_t size,
> +				     unsigned int flags)
> +{
> +	return (void __iomem *)cookie;
> +}
> +
> +static void ebsa110_iounmap(volatile void __iomem *io_addr)
> +{}
> +
> +static void __init ebsa110_init_early(void)
> +{
> +	arch_ioremap_caller = ebsa110_ioremap;

ebsa110_ioremap() appears to lack the caller argument, so this will 
generate a pointer mismatch error.


Nicolas


From linus.walleij at linaro.org  Tue Mar  6 17:09:47 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 6 Mar 2012 23:09:47 +0100
Subject: [PATCH] pinctrl: split pincontrol states into its own header
In-Reply-To: <4F567FE7.4020507@wwwdotorg.org>
References: <1331068552-16988-1-git-send-email-linus.walleij@stericsson.com>
 <4F567FE7.4020507@wwwdotorg.org>
Message-ID: <CACRpkdYQUmPLdc-cZN80bEgfjNALDQ-gfaHy5d6Hrn_HsHMvtA@mail.gmail.com>

On Tue, Mar 6, 2012 at 10:21 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:

> Sure. I'm not quite sure how many (or how many standardized) states we
> expect to have such that it warrants 'pinctrl-state.h' vs. say
> 'pinctrl-common.h', but it's probably fine.

We can just rename it as seems fit I guess...

> Acked-by: Stephen Warren <swarren at wwwdotorg.org>

I really like your new email address!

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Tue Mar  6 17:11:52 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 22:11:52 +0000
Subject: [PATCH v5 5/7] ARM: ixp4xx: use runtime ioremap hook
In-Reply-To: <1331070317-9598-5-git-send-email-robherring2@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
 <1331070317-9598-5-git-send-email-robherring2@gmail.com>
Message-ID: <20120306221152.GC15201@n2100.arm.linux.org.uk>

On Tue, Mar 06, 2012 at 03:45:15PM -0600, Rob Herring wrote:
> diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
> index a6329a0..c60e7b8 100644
> --- a/arch/arm/mach-ixp4xx/common.c
> +++ b/arch/arm/mach-ixp4xx/common.c
> @@ -31,6 +31,7 @@
>  
>  #include <mach/udc.h>
>  #include <mach/hardware.h>
> +#include <mach/io.h>

I'll assume you have a good reason for this, inspite of there being
no mention of it in the commit log...


From linus.walleij at linaro.org  Tue Mar  6 17:25:36 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 6 Mar 2012 23:25:36 +0100
Subject: [PATCH] pinctrl: include machine header to core.h
In-Reply-To: <4F565C04.1030202@ru.mvista.com>
References: <1331038557-1398-1-git-send-email-linus.walleij@stericsson.com>
 <4F565C04.1030202@ru.mvista.com>
Message-ID: <CACRpkdYdzTBiHKod+tzM4tPbYgRaNU=aRdqCnTQ6urqbT4vayQ@mail.gmail.com>

On Tue, Mar 6, 2012 at 7:48 PM, Sergei Shtylyov <sshtylyov at ru.mvista.com> wrote:

> ? I don't see where you touch kernel-doc...

Bah, missed to git add it. Here is the new patch:

>From 872acc322c74bb06b7ceb61fe93314e2da32362c Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij at linaro.org>
Date: Tue, 6 Mar 2012 13:52:22 +0100
Subject: [PATCH] pinctrl: include machine header to core.h

struct pinctrl_setting contains an enum pinctrl_map_type
field, so we need to include machine.h. Also fix kerneldoc
to indicate that the pinctrl_setting is about both muxing
and other config.

Acked-by: Stephen Warren <swarren at wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/core.h |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 5b3ff13..efbfb62 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -12,6 +12,7 @@
 #include <linux/mutex.h>
 #include <linux/radix-tree.h>
 #include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/machine.h>

 struct pinctrl_gpio_range;

@@ -96,7 +97,7 @@ struct pinctrl_setting_configs {
 };

 /**
- * struct pinctrl_setting - an individual mux setting
+ * struct pinctrl_setting - an individual mux or config setting
  * @node: list node for struct pinctrl_settings's @settings field
  * @type: the type of setting
  * @pctldev: pin control device handling to be programmed
-- 
1.7.8


From linus.walleij at stericsson.com  Tue Mar  6 17:05:25 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 6 Mar 2012 23:05:25 +0100
Subject: [PATCH 2/4] pinctrl/coh901: use generic pinconf enums and parameters
Message-ID: <1331071525-24699-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Adjust the COH 901 driver to use the standard enums for
biasing and driving pins, alter signature of config function
to suit the framework.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/pinctrl-coh901.c |   56 +++++++++-----------------------------
 1 files changed, 13 insertions(+), 43 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index b90c011..724234c 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -26,36 +26,6 @@
 #include <mach/gpio-u300.h>
 
 /*
- * Bias modes for U300 GPIOs
- *
- * GPIO_U300_CONFIG_BIAS_UNKNOWN: this bias mode is not known to us
- * GPIO_U300_CONFIG_BIAS_FLOAT: no specific bias, the GPIO will float or state
- *	is not controlled by software
- * GPIO_U300_CONFIG_BIAS_PULL_UP: the GPIO will be pulled up (usually with high
- *	impedance to VDD)
- */
-#define GPIO_U300_CONFIG_BIAS_UNKNOWN	0x1000
-#define GPIO_U300_CONFIG_BIAS_FLOAT	0x1001
-#define GPIO_U300_CONFIG_BIAS_PULL_UP	0x1002
-
-/*
- * Drive modes for U300 GPIOs (output)
- *
- * GPIO_U300_CONFIG_DRIVE_PUSH_PULL: the GPIO will be driven actively high and
- *	low, this is the most typical case and is typically achieved with two
- *	active transistors on the output
- * GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN: the GPIO will be driven with open drain
- *	(open collector) which means it is usually wired with other output
- *	ports which are then pulled up with an external resistor
- * GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE: the GPIO will be driven with open drain
- *	(open emitter) which is the same as open drain mutatis mutandis but
- *	pulled to ground
- */
-#define GPIO_U300_CONFIG_DRIVE_PUSH_PULL	0x2000
-#define GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN	0x2001
-#define GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE	0x2002
-
-/*
  * Register definitions for COH 901 335 variant
  */
 #define U300_335_PORT_STRIDE				(0x1C)
@@ -181,12 +151,12 @@ struct u300_gpio_confdata {
 #define BS365_GPIO_NUM_PORTS 5
 
 #define U300_FLOATING_INPUT { \
-	.bias_mode = GPIO_U300_CONFIG_BIAS_FLOAT, \
+	.bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
 	.output = false, \
 }
 
 #define U300_PULL_UP_INPUT { \
-	.bias_mode = GPIO_U300_CONFIG_BIAS_PULL_UP, \
+	.bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
 	.output = false, \
 }
 
@@ -449,7 +419,7 @@ static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 }
 
 static int u300_gpio_config(struct gpio_chip *chip, unsigned offset,
-		     u16 param, unsigned long *data)
+			    enum pin_config_param param, unsigned long data)
 {
 	struct u300_gpio *gpio = to_u300_gpio(chip);
 	unsigned long flags;
@@ -457,16 +427,16 @@ static int u300_gpio_config(struct gpio_chip *chip, unsigned offset,
 
 	local_irq_save(flags);
 	switch (param) {
-	case GPIO_U300_CONFIG_BIAS_UNKNOWN:
-	case GPIO_U300_CONFIG_BIAS_FLOAT:
+	case PIN_CONFIG_BIAS_DISABLE:
+	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 		val = readl(U300_PIN_REG(offset, per));
 		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
 		break;
-	case GPIO_U300_CONFIG_BIAS_PULL_UP:
+	case PIN_CONFIG_BIAS_PULL_UP:
 		val = readl(U300_PIN_REG(offset, per));
 		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
 		break;
-	case GPIO_U300_CONFIG_DRIVE_PUSH_PULL:
+	case PIN_CONFIG_DRIVE_PUSH_PULL:
 		val = readl(U300_PIN_REG(offset, pcr));
 		val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 			 << ((offset & 0x07) << 1));
@@ -474,7 +444,7 @@ static int u300_gpio_config(struct gpio_chip *chip, unsigned offset,
 			<< ((offset & 0x07) << 1));
 		writel(val, U300_PIN_REG(offset, pcr));
 		break;
-	case GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN:
+	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 		val = readl(U300_PIN_REG(offset, pcr));
 		val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 			 << ((offset & 0x07) << 1));
@@ -482,7 +452,7 @@ static int u300_gpio_config(struct gpio_chip *chip, unsigned offset,
 			<< ((offset & 0x07) << 1));
 		writel(val, U300_PIN_REG(offset, pcr));
 		break;
-	case GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE:
+	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 		val = readl(U300_PIN_REG(offset, pcr));
 		val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 			 << ((offset & 0x07) << 1));
@@ -651,12 +621,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
 
 		/* Deactivate bias mode for output */
 		u300_gpio_config(&gpio->chip, offset,
-				 GPIO_U300_CONFIG_BIAS_FLOAT,
-				 NULL);
+				 PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
+				 0);
 
 		/* Set drive mode for output */
 		u300_gpio_config(&gpio->chip, offset,
-				 GPIO_U300_CONFIG_DRIVE_PUSH_PULL, NULL);
+				 PIN_CONFIG_DRIVE_PUSH_PULL, 0);
 
 		dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
 			offset, conf->outval);
@@ -667,7 +637,7 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
 		u300_gpio_set(&gpio->chip, offset, 0);
 
 		/* Set bias mode for input */
-		u300_gpio_config(&gpio->chip, offset, conf->bias_mode, NULL);
+		u300_gpio_config(&gpio->chip, offset, conf->bias_mode, 0);
 
 		dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
 			offset, conf->bias_mode);
-- 
1.7.8



From festevam at gmail.com  Tue Mar  6 17:33:33 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Tue,  6 Mar 2012 19:33:33 -0300
Subject: [PATCH] ARM: mach-versatile: Fix PCI build error
Message-ID: <1331073213-16502-1-git-send-email-festevam@gmail.com>

Fix the following build error that happened on a "make randconfig":

arch/arm/mach-versatile/pci.c: In function 'pci_versatile_setup_resources':
arch/arm/mach-versatile/pci.c:222: error: 'sys' undeclared (first use in this function)

since commit 9f786d033d (arm/PCI: get rid of device resource fixups)
pci_add_resource_offset() has an extra parameter.

Pass the sys struct parameter to pci_versatile_setup_resources() in order to fix
the build.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-versatile/pci.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 51733b0..4f41cb8 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -191,7 +191,8 @@ static struct resource pre_mem = {
 	.flags	= IORESOURCE_MEM | IORESOURCE_PREFETCH,
 };
 
-static int __init pci_versatile_setup_resources(struct list_head *resources)
+static int __init pci_versatile_setup_resources(struct list_head *resources,
+						struct pci_sys_data *sys)
 {
 	int ret = 0;
 
@@ -250,7 +251,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 
 	if (nr == 0) {
 		sys->mem_offset = 0;
-		ret = pci_versatile_setup_resources(&sys->resources);
+		ret = pci_versatile_setup_resources(&sys->resources, sys);
 		if (ret < 0) {
 			printk("pci_versatile_setup: resources... oops?\n");
 			goto out;
-- 
1.7.1



From linux at arm.linux.org.uk  Tue Mar  6 17:33:21 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 22:33:21 +0000
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
Message-ID: <20120306223321.GD15201@n2100.arm.linux.org.uk>

[v2 - more or less same description.  Including lakml in cc for the full
set]

This patch series cleans up the handling of cookies in DMA engine drivers.
This is done by providing a set of inline library functions for common
tasks:

- moving the 'last completed cookie' into struct dma_chan - everyone
  has this in their driver private channel data structure

- consolidate allocation of cookies to DMA descriptors

- common way to update 'last completed cookie' value

- standard way to implement tx_status callback and update the residue

- consolidate initialization of cookies

- update implementations differing from the majority of DMA engine drivers
  to behave the same as the majority implementation in respect of cookies

What this means is that we get to the point where all DMA engine drivers
will hand out cookie value '2' as the first, and incrementing cookie
values up to INT_MAX, returning to cookie '1' as the next cookie.

Think of this patch series as round 1...  I am hoping over time that more
code can be consolidated between the DMA engine drivers and end up with a
consistent way to handle various common themes in DMA engine hardware
(like physical channel<->peripheral request signal selection.)

Overall, the diffstat looks like this:

 arch/arm/include/asm/hardware/iop_adma.h |    2 -
 drivers/dma/amba-pl08x.c                 |   38 ++++---------
 drivers/dma/at_hdmac.c                   |   48 ++++------------
 drivers/dma/at_hdmac_regs.h              |    2 -
 drivers/dma/coh901318.c                  |   39 +++----------
 drivers/dma/dmaengine.h                  |   89 ++++++++++++++++++++++++++++++
 drivers/dma/dw_dmac.c                    |   43 +++-----------
 drivers/dma/dw_dmac_regs.h               |    1 -
 drivers/dma/ep93xx_dma.c                 |   25 ++------
 drivers/dma/fsldma.c                     |   24 ++------
 drivers/dma/fsldma.h                     |    1 -
 drivers/dma/imx-dma.c                    |   32 ++---------
 drivers/dma/imx-sdma.c                   |   23 ++------
 drivers/dma/intel_mid_dma.c              |   37 +++---------
 drivers/dma/intel_mid_dma_regs.h         |    2 -
 drivers/dma/ioat/dma.c                   |   21 +++----
 drivers/dma/ioat/dma.h                   |   23 --------
 drivers/dma/ioat/dma_v2.c                |   13 ++---
 drivers/dma/ioat/dma_v3.c                |   11 ++--
 drivers/dma/iop-adma.c                   |   51 ++++-------------
 drivers/dma/ipu/ipu_idmac.c              |   22 ++-----
 drivers/dma/mpc512x_dma.c                |   25 +++------
 drivers/dma/mv_xor.c                     |   34 ++---------
 drivers/dma/mv_xor.h                     |    3 -
 drivers/dma/mxs-dma.c                    |   23 ++------
 drivers/dma/pch_dma.c                    |   34 ++---------
 drivers/dma/pl330.c                      |   36 ++----------
 drivers/dma/ppc4xx/adma.c                |   49 +++-------------
 drivers/dma/ppc4xx/adma.h                |    2 -
 drivers/dma/shdma.c                      |   30 +++-------
 drivers/dma/shdma.h                      |    1 -
 drivers/dma/sirf-dma.c                   |   23 ++------
 drivers/dma/ste_dma40.c                  |   36 +++---------
 drivers/dma/timb_dma.c                   |   28 +++-------
 drivers/dma/txx9dmac.c                   |   41 +++-----------
 drivers/dma/txx9dmac.h                   |    1 -
 include/linux/amba/pl08x.h               |    2 -
 include/linux/dmaengine.h                |    6 +-
 38 files changed, 293 insertions(+), 628 deletions(-)



From linux at arm.linux.org.uk  Tue Mar  6 17:34:06 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 06 Mar 2012 22:34:06 +0000
Subject: [PATCH 2/9] dmaengine: move last completed cookie into generic
 dma_chan structure
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <E1S52xK-0002Mj-Af@rmk-PC.arm.linux.org.uk>

Every DMA engine implementation declares a last completed dma cookie
in their private dma channel structures.  This is pointless, and
forces driver specific code.  Move this out into the common dma_chan
structure.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/include/asm/hardware/iop_adma.h |    2 --
 drivers/dma/amba-pl08x.c                 |    8 ++++----
 drivers/dma/at_hdmac.c                   |   10 +++++-----
 drivers/dma/at_hdmac_regs.h              |    2 --
 drivers/dma/coh901318.c                  |    7 +++----
 drivers/dma/dw_dmac.c                    |   10 +++++-----
 drivers/dma/dw_dmac_regs.h               |    1 -
 drivers/dma/ep93xx_dma.c                 |    8 +++-----
 drivers/dma/fsldma.c                     |    4 ++--
 drivers/dma/fsldma.h                     |    1 -
 drivers/dma/imx-dma.c                    |    7 +++----
 drivers/dma/imx-sdma.c                   |    5 ++---
 drivers/dma/intel_mid_dma.c              |    9 ++++-----
 drivers/dma/intel_mid_dma_regs.h         |    2 --
 drivers/dma/ioat/dma.c                   |    2 +-
 drivers/dma/ioat/dma.h                   |    4 +---
 drivers/dma/ioat/dma_v2.c                |    2 +-
 drivers/dma/ioat/dma_v3.c                |    2 +-
 drivers/dma/iop-adma.c                   |   10 +++++-----
 drivers/dma/ipu/ipu_idmac.c              |   10 ++++------
 drivers/dma/mpc512x_dma.c                |    7 +++----
 drivers/dma/mv_xor.c                     |    6 +++---
 drivers/dma/mv_xor.h                     |    2 --
 drivers/dma/mxs-dma.c                    |    5 ++---
 drivers/dma/pch_dma.c                    |    5 ++---
 drivers/dma/pl330.c                      |    9 +++------
 drivers/dma/ppc4xx/adma.c                |   10 +++++-----
 drivers/dma/ppc4xx/adma.h                |    2 --
 drivers/dma/shdma.c                      |   10 +++++-----
 drivers/dma/shdma.h                      |    1 -
 drivers/dma/sirf-dma.c                   |    7 +++----
 drivers/dma/ste_dma40.c                  |   10 +++-------
 drivers/dma/timb_dma.c                   |    7 +++----
 drivers/dma/txx9dmac.c                   |   10 +++++-----
 drivers/dma/txx9dmac.h                   |    1 -
 include/linux/amba/pl08x.h               |    2 --
 include/linux/dmaengine.h                |    2 ++
 37 files changed, 83 insertions(+), 119 deletions(-)

diff --git a/arch/arm/include/asm/hardware/iop_adma.h b/arch/arm/include/asm/hardware/iop_adma.h
index 59b8c38..122f86d 100644
--- a/arch/arm/include/asm/hardware/iop_adma.h
+++ b/arch/arm/include/asm/hardware/iop_adma.h
@@ -49,7 +49,6 @@ struct iop_adma_device {
 /**
  * struct iop_adma_chan - internal representation of an ADMA device
  * @pending: allows batching of hardware operations
- * @completed_cookie: identifier for the most recently completed operation
  * @lock: serializes enqueue/dequeue operations to the slot pool
  * @mmr_base: memory mapped register base
  * @chain: device chain view of the descriptors
@@ -62,7 +61,6 @@ struct iop_adma_device {
  */
 struct iop_adma_chan {
 	int pending;
-	dma_cookie_t completed_cookie;
 	spinlock_t lock; /* protects the descriptor slot pool */
 	void __iomem *mmr_base;
 	struct list_head chain;
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 8a28158..2b5121f 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -971,7 +971,7 @@ static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
 	u32 bytesleft = 0;
 
 	last_used = plchan->chan.cookie;
-	last_complete = plchan->lc;
+	last_complete = plchan->chan.completed_cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
 	if (ret == DMA_SUCCESS) {
@@ -983,7 +983,7 @@ static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
 	 * This cookie not complete yet
 	 */
 	last_used = plchan->chan.cookie;
-	last_complete = plchan->lc;
+	last_complete = plchan->chan.completed_cookie;
 
 	/* Get number of bytes left in the active transactions and queue */
 	bytesleft = pl08x_getbytes_chan(plchan);
@@ -1541,7 +1541,7 @@ static void pl08x_tasklet(unsigned long data)
 
 	if (txd) {
 		/* Update last completed */
-		plchan->lc = txd->tx.cookie;
+		plchan->chan.completed_cookie = txd->tx.cookie;
 	}
 
 	/* If a new descriptor is queued, set it up plchan->at is NULL here */
@@ -1723,7 +1723,7 @@ static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
 
 		chan->chan.device = dmadev;
 		chan->chan.cookie = 0;
-		chan->lc = 0;
+		chan->chan.completed_cookie = 0;
 
 		spin_lock_init(&chan->lock);
 		INIT_LIST_HEAD(&chan->pend_list);
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index f4aed5f..6baf5d7 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -269,7 +269,7 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
 	dev_vdbg(chan2dev(&atchan->chan_common),
 		"descriptor %u complete\n", txd->cookie);
 
-	atchan->completed_cookie = txd->cookie;
+	atchan->chan_common.completed_cookie = txd->cookie;
 
 	/* move children to free_list */
 	list_splice_init(&desc->tx_list, &atchan->free_list);
@@ -1016,14 +1016,14 @@ atc_tx_status(struct dma_chan *chan,
 
 	spin_lock_irqsave(&atchan->lock, flags);
 
-	last_complete = atchan->completed_cookie;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
 	if (ret != DMA_SUCCESS) {
 		atc_cleanup_descriptors(atchan);
 
-		last_complete = atchan->completed_cookie;
+		last_complete = chan->completed_cookie;
 		last_used = chan->cookie;
 
 		ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -1129,7 +1129,7 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
 	spin_lock_irqsave(&atchan->lock, flags);
 	atchan->descs_allocated = i;
 	list_splice(&tmp_list, &atchan->free_list);
-	atchan->completed_cookie = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 	spin_unlock_irqrestore(&atchan->lock, flags);
 
 	/* channel parameters */
@@ -1329,7 +1329,7 @@ static int __init at_dma_probe(struct platform_device *pdev)
 		struct at_dma_chan	*atchan = &atdma->chan[i];
 
 		atchan->chan_common.device = &atdma->dma_common;
-		atchan->chan_common.cookie = atchan->completed_cookie = 1;
+		atchan->chan_common.cookie = atchan->chan_common.completed_cookie = 1;
 		list_add_tail(&atchan->chan_common.device_node,
 				&atdma->dma_common.channels);
 
diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
index a8d3277..08fd8a0 100644
--- a/drivers/dma/at_hdmac_regs.h
+++ b/drivers/dma/at_hdmac_regs.h
@@ -208,7 +208,6 @@ enum atc_status {
  * @save_dscr: for cyclic operations, preserve next descriptor address in
  *             the cyclic list on suspend/resume cycle
  * @lock: serializes enqueue/dequeue operations to descriptors lists
- * @completed_cookie: identifier for the most recently completed operation
  * @active_list: list of descriptors dmaengine is being running on
  * @queue: list of descriptors ready to be submitted to engine
  * @free_list: list of descriptors usable by the channel
@@ -227,7 +226,6 @@ struct at_dma_chan {
 	spinlock_t		lock;
 
 	/* these other elements are all protected by lock */
-	dma_cookie_t		completed_cookie;
 	struct list_head	active_list;
 	struct list_head	queue;
 	struct list_head	free_list;
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index d65a718..521434b 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -59,7 +59,6 @@ struct coh901318_base {
 struct coh901318_chan {
 	spinlock_t lock;
 	int allocated;
-	int completed;
 	int id;
 	int stopped;
 
@@ -705,7 +704,7 @@ static void dma_tasklet(unsigned long data)
 	callback_param = cohd_fin->desc.callback_param;
 
 	/* sign this job as completed on the channel */
-	cohc->completed = cohd_fin->desc.cookie;
+	cohc->chan.completed_cookie = cohd_fin->desc.cookie;
 
 	/* release the lli allocation and remove the descriptor */
 	coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
@@ -929,7 +928,7 @@ static int coh901318_alloc_chan_resources(struct dma_chan *chan)
 	coh901318_config(cohc, NULL);
 
 	cohc->allocated = 1;
-	cohc->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 
 	spin_unlock_irqrestore(&cohc->lock, flags);
 
@@ -1169,7 +1168,7 @@ coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 	dma_cookie_t last_complete;
 	int ret;
 
-	last_complete = cohc->completed;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 9b592b0..defe574 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -245,7 +245,7 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 	dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 
 	spin_lock_irqsave(&dwc->lock, flags);
-	dwc->completed = txd->cookie;
+	dwc->chan.completed_cookie = txd->cookie;
 	if (callback_required) {
 		callback = txd->callback;
 		param = txd->callback_param;
@@ -955,14 +955,14 @@ dwc_tx_status(struct dma_chan *chan,
 	dma_cookie_t		last_complete;
 	int			ret;
 
-	last_complete = dwc->completed;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
 	if (ret != DMA_SUCCESS) {
 		dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 
-		last_complete = dwc->completed;
+		last_complete = chan->completed_cookie;
 		last_used = chan->cookie;
 
 		ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -1004,7 +1004,7 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
 		return -EIO;
 	}
 
-	dwc->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 
 	/*
 	 * NOTE: some controllers may have additional features that we
@@ -1423,7 +1423,7 @@ static int __init dw_probe(struct platform_device *pdev)
 		struct dw_dma_chan	*dwc = &dw->chan[i];
 
 		dwc->chan.device = &dw->dma;
-		dwc->chan.cookie = dwc->completed = 1;
+		dwc->chan.cookie = dwc->chan.completed_cookie = 1;
 		if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
 			list_add_tail(&dwc->chan.device_node,
 					&dw->dma.channels);
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index 5eef694..cce1752 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -146,7 +146,6 @@ struct dw_dma_chan {
 
 	/* these other elements are all protected by lock */
 	unsigned long		flags;
-	dma_cookie_t		completed;
 	struct list_head	active_list;
 	struct list_head	queue;
 	struct list_head	free_list;
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index 59e7a96..bc45787 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -122,7 +122,6 @@ struct ep93xx_dma_desc {
  * @lock: lock protecting the fields following
  * @flags: flags for the channel
  * @buffer: which buffer to use next (0/1)
- * @last_completed: last completed cookie value
  * @active: flattened chain of descriptors currently being processed
  * @queue: pending descriptors which are handled next
  * @free_list: list of free descriptors which can be used
@@ -157,7 +156,6 @@ struct ep93xx_dma_chan {
 #define EP93XX_DMA_IS_CYCLIC		0
 
 	int				buffer;
-	dma_cookie_t			last_completed;
 	struct list_head		active;
 	struct list_head		queue;
 	struct list_head		free_list;
@@ -703,7 +701,7 @@ static void ep93xx_dma_tasklet(unsigned long data)
 	desc = ep93xx_dma_get_active(edmac);
 	if (desc) {
 		if (desc->complete) {
-			edmac->last_completed = desc->txd.cookie;
+			edmac->chan.completed_cookie = desc->txd.cookie;
 			list_splice_init(&edmac->active, &list);
 		}
 		callback = desc->txd.callback;
@@ -861,7 +859,7 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
 		goto fail_clk_disable;
 
 	spin_lock_irq(&edmac->lock);
-	edmac->last_completed = 1;
+	edmac->chan.completed_cookie = 1;
 	edmac->chan.cookie = 1;
 	ret = edmac->edma->hw_setup(edmac);
 	spin_unlock_irq(&edmac->lock);
@@ -1254,7 +1252,7 @@ static enum dma_status ep93xx_dma_tx_status(struct dma_chan *chan,
 
 	spin_lock_irqsave(&edmac->lock, flags);
 	last_used = chan->cookie;
-	last_completed = edmac->last_completed;
+	last_completed = chan->completed_cookie;
 	spin_unlock_irqrestore(&edmac->lock, flags);
 
 	ret = dma_async_is_complete(cookie, last_completed, last_used);
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index b98070c..9b5cb8a 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -990,7 +990,7 @@ static enum dma_status fsl_tx_status(struct dma_chan *dchan,
 
 	spin_lock_irqsave(&chan->desc_lock, flags);
 
-	last_complete = chan->completed_cookie;
+	last_complete = dchan->completed_cookie;
 	last_used = dchan->cookie;
 
 	spin_unlock_irqrestore(&chan->desc_lock, flags);
@@ -1088,7 +1088,7 @@ static void dma_do_tasklet(unsigned long data)
 		desc = to_fsl_desc(chan->ld_running.prev);
 		cookie = desc->async_tx.cookie;
 
-		chan->completed_cookie = cookie;
+		chan->common.completed_cookie = cookie;
 		chan_dbg(chan, "completed_cookie=%d\n", cookie);
 	}
 
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index 9cb5aa5..f5c3879 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -137,7 +137,6 @@ struct fsldma_device {
 struct fsldma_chan {
 	char name[8];			/* Channel name */
 	struct fsldma_chan_regs __iomem *regs;
-	dma_cookie_t completed_cookie;	/* The maximum cookie completed */
 	spinlock_t desc_lock;		/* Descriptor operation lock */
 	struct list_head ld_pending;	/* Link descriptors queue */
 	struct list_head ld_running;	/* Link descriptors queue */
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index e4383ee..321fc1f 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -41,7 +41,6 @@ struct imxdma_channel {
 	struct dma_chan			chan;
 	spinlock_t			lock;
 	struct dma_async_tx_descriptor	desc;
-	dma_cookie_t			last_completed;
 	enum dma_status			status;
 	int				dma_request;
 	struct scatterlist		*sg_list;
@@ -65,7 +64,7 @@ static void imxdma_handle(struct imxdma_channel *imxdmac)
 {
 	if (imxdmac->desc.callback)
 		imxdmac->desc.callback(imxdmac->desc.callback_param);
-	imxdmac->last_completed = imxdmac->desc.cookie;
+	imxdmac->chan.completed_cookie = imxdmac->desc.cookie;
 }
 
 static void imxdma_irq_handler(int channel, void *data)
@@ -158,8 +157,8 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 
 	last_used = chan->cookie;
 
-	ret = dma_async_is_complete(cookie, imxdmac->last_completed, last_used);
-	dma_set_tx_state(txstate, imxdmac->last_completed, last_used, 0);
+	ret = dma_async_is_complete(cookie, chan->completed_cookie, last_used);
+	dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
 
 	return ret;
 }
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 8bc5acf..e857904 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -266,7 +266,6 @@ struct sdma_channel {
 	struct dma_chan			chan;
 	spinlock_t			lock;
 	struct dma_async_tx_descriptor	desc;
-	dma_cookie_t			last_completed;
 	enum dma_status			status;
 	unsigned int			chn_count;
 	unsigned int			chn_real_count;
@@ -523,7 +522,7 @@ static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 	else
 		sdmac->status = DMA_SUCCESS;
 
-	sdmac->last_completed = sdmac->desc.cookie;
+	sdmac->chan.completed_cookie = sdmac->desc.cookie;
 	if (sdmac->desc.callback)
 		sdmac->desc.callback(sdmac->desc.callback_param);
 }
@@ -1129,7 +1128,7 @@ static enum dma_status sdma_tx_status(struct dma_chan *chan,
 
 	last_used = chan->cookie;
 
-	dma_set_tx_state(txstate, sdmac->last_completed, last_used,
+	dma_set_tx_state(txstate, chan->completed_cookie, last_used,
 			sdmac->chn_count - sdmac->chn_real_count);
 
 	return sdmac->status;
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index 74f70aa..a27ae45 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -288,7 +288,7 @@ static void midc_descriptor_complete(struct intel_mid_dma_chan *midc,
 	struct intel_mid_dma_lli	*llitem;
 	void *param_txd = NULL;
 
-	midc->completed = txd->cookie;
+	midc->chan.completed_cookie = txd->cookie;
 	callback_txd = txd->callback;
 	param_txd = txd->callback_param;
 
@@ -482,12 +482,11 @@ static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
 						dma_cookie_t cookie,
 						struct dma_tx_state *txstate)
 {
-	struct intel_mid_dma_chan	*midc = to_intel_mid_dma_chan(chan);
 	dma_cookie_t		last_used;
 	dma_cookie_t		last_complete;
 	int				ret;
 
-	last_complete = midc->completed;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -496,7 +495,7 @@ static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
 		midc_scan_descriptors(to_middma_device(chan->device), midc);
 		spin_unlock_bh(&midc->lock);
 
-		last_complete = midc->completed;
+		last_complete = chan->completed_cookie;
 		last_used = chan->cookie;
 
 		ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -886,7 +885,7 @@ static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
 		pm_runtime_put(&mid->pdev->dev);
 		return -EIO;
 	}
-	midc->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 
 	spin_lock_bh(&midc->lock);
 	while (midc->descs_allocated < DESCS_PER_CHANNEL) {
diff --git a/drivers/dma/intel_mid_dma_regs.h b/drivers/dma/intel_mid_dma_regs.h
index c83d35b..1bfa926 100644
--- a/drivers/dma/intel_mid_dma_regs.h
+++ b/drivers/dma/intel_mid_dma_regs.h
@@ -165,7 +165,6 @@ union intel_mid_dma_cfg_hi {
  * @dma_base: MMIO register space DMA engine base pointer
  * @ch_id: DMA channel id
  * @lock: channel spinlock
- * @completed: DMA cookie
  * @active_list: current active descriptors
  * @queue: current queued up descriptors
  * @free_list: current free descriptors
@@ -183,7 +182,6 @@ struct intel_mid_dma_chan {
 	void __iomem		*dma_base;
 	int			ch_id;
 	spinlock_t		lock;
-	dma_cookie_t		completed;
 	struct list_head	active_list;
 	struct list_head	queue;
 	struct list_head	free_list;
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index a4d6cb0..fab440a 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -603,7 +603,7 @@ static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete)
 		 */
 		dump_desc_dbg(ioat, desc);
 		if (tx->cookie) {
-			chan->completed_cookie = tx->cookie;
+			chan->common.completed_cookie = tx->cookie;
 			tx->cookie = 0;
 			ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 			ioat->active -= desc->hw->tx_cnt;
diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h
index 5216c8a..9653b6b 100644
--- a/drivers/dma/ioat/dma.h
+++ b/drivers/dma/ioat/dma.h
@@ -90,7 +90,6 @@ struct ioat_chan_common {
 	void __iomem *reg_base;
 	unsigned long last_completion;
 	spinlock_t cleanup_lock;
-	dma_cookie_t completed_cookie;
 	unsigned long state;
 	#define IOAT_COMPLETION_PENDING 0
 	#define IOAT_COMPLETION_ACK 1
@@ -153,12 +152,11 @@ static inline enum dma_status
 ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 		 struct dma_tx_state *txstate)
 {
-	struct ioat_chan_common *chan = to_chan_common(c);
 	dma_cookie_t last_used;
 	dma_cookie_t last_complete;
 
 	last_used = c->cookie;
-	last_complete = chan->completed_cookie;
+	last_complete = c->completed_cookie;
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 
diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c
index 5d65f83..d3f0aff 100644
--- a/drivers/dma/ioat/dma_v2.c
+++ b/drivers/dma/ioat/dma_v2.c
@@ -147,7 +147,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
 		dump_desc_dbg(ioat, desc);
 		if (tx->cookie) {
 			ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
-			chan->completed_cookie = tx->cookie;
+			chan->common.completed_cookie = tx->cookie;
 			tx->cookie = 0;
 			if (tx->callback) {
 				tx->callback(tx->callback_param);
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
index f519c93..d4afac7 100644
--- a/drivers/dma/ioat/dma_v3.c
+++ b/drivers/dma/ioat/dma_v3.c
@@ -277,7 +277,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
 		dump_desc_dbg(ioat, desc);
 		tx = &desc->txd;
 		if (tx->cookie) {
-			chan->completed_cookie = tx->cookie;
+			chan->common.completed_cookie = tx->cookie;
 			ioat3_dma_unmap(ioat, desc, idx + i);
 			tx->cookie = 0;
 			if (tx->callback) {
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index 04be90b..d8027c2 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -317,7 +317,7 @@ static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
 	}
 
 	if (cookie > 0) {
-		iop_chan->completed_cookie = cookie;
+		iop_chan->common.completed_cookie = cookie;
 		pr_debug("\tcompleted cookie %d\n", cookie);
 	}
 }
@@ -909,7 +909,7 @@ static enum dma_status iop_adma_status(struct dma_chan *chan,
 	enum dma_status ret;
 
 	last_used = chan->cookie;
-	last_complete = iop_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
 	if (ret == DMA_SUCCESS)
@@ -918,7 +918,7 @@ static enum dma_status iop_adma_status(struct dma_chan *chan,
 	iop_adma_slot_cleanup(iop_chan);
 
 	last_used = chan->cookie;
-	last_complete = iop_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 
 	return dma_async_is_complete(cookie, last_complete, last_used);
@@ -1650,7 +1650,7 @@ static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
 		/* initialize the completed cookie to be less than
 		 * the most recently used cookie
 		 */
-		iop_chan->completed_cookie = cookie - 1;
+		iop_chan->common.completed_cookie = cookie - 1;
 		iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
 		/* channel should not be busy */
@@ -1707,7 +1707,7 @@ static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
 		/* initialize the completed cookie to be less than
 		 * the most recently used cookie
 		 */
-		iop_chan->completed_cookie = cookie - 1;
+		iop_chan->common.completed_cookie = cookie - 1;
 		iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
 		/* channel should not be busy */
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index 6212b16..9149ade 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -1295,7 +1295,7 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
 	/* Flip the active buffer - even if update above failed */
 	ichan->active_buffer = !ichan->active_buffer;
 	if (done)
-		ichan->completed = desc->txd.cookie;
+		ichan->dma_chan.completed_cookie = desc->txd.cookie;
 
 	callback = desc->txd.callback;
 	callback_param = desc->txd.callback_param;
@@ -1511,7 +1511,7 @@ static int idmac_alloc_chan_resources(struct dma_chan *chan)
 	WARN_ON(ichan->status != IPU_CHANNEL_FREE);
 
 	chan->cookie		= 1;
-	ichan->completed	= -ENXIO;
+	chan->completed_cookie	= -ENXIO;
 
 	ret = ipu_irq_map(chan->chan_id);
 	if (ret < 0)
@@ -1600,9 +1600,7 @@ static void idmac_free_chan_resources(struct dma_chan *chan)
 static enum dma_status idmac_tx_status(struct dma_chan *chan,
 		       dma_cookie_t cookie, struct dma_tx_state *txstate)
 {
-	struct idmac_channel *ichan = to_idmac_chan(chan);
-
-	dma_set_tx_state(txstate, ichan->completed, chan->cookie, 0);
+	dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, 0);
 	if (cookie != chan->cookie)
 		return DMA_ERROR;
 	return DMA_SUCCESS;
@@ -1638,11 +1636,11 @@ static int __init ipu_idmac_init(struct ipu *ipu)
 
 		ichan->status		= IPU_CHANNEL_FREE;
 		ichan->sec_chan_en	= false;
-		ichan->completed	= -ENXIO;
 		snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
 
 		dma_chan->device	= &idmac->dma;
 		dma_chan->cookie	= 1;
+		dma_chan->completed_cookie	= -ENXIO;
 		dma_chan->chan_id	= i;
 		list_add_tail(&dma_chan->device_node, &dma->channels);
 	}
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index 4d6d4cf..39a5cde 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -188,7 +188,6 @@ struct mpc_dma_chan {
 	struct list_head		completed;
 	struct mpc_dma_tcd		*tcd;
 	dma_addr_t			tcd_paddr;
-	dma_cookie_t			completed_cookie;
 
 	/* Lock for this structure */
 	spinlock_t			lock;
@@ -365,7 +364,7 @@ static void mpc_dma_process_completed(struct mpc_dma *mdma)
 		/* Free descriptors */
 		spin_lock_irqsave(&mchan->lock, flags);
 		list_splice_tail_init(&list, &mchan->free);
-		mchan->completed_cookie = last_cookie;
+		mchan->chan.completed_cookie = last_cookie;
 		spin_unlock_irqrestore(&mchan->lock, flags);
 	}
 }
@@ -568,7 +567,7 @@ mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 
 	spin_lock_irqsave(&mchan->lock, flags);
 	last_used = mchan->chan.cookie;
-	last_complete = mchan->completed_cookie;
+	last_complete = mchan->chan.completed_cookie;
 	spin_unlock_irqrestore(&mchan->lock, flags);
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
@@ -742,7 +741,7 @@ static int __devinit mpc_dma_probe(struct platform_device *op)
 
 		mchan->chan.device = dma;
 		mchan->chan.cookie = 1;
-		mchan->completed_cookie = mchan->chan.cookie;
+		mchan->chan.completed_cookie = mchan->chan.cookie;
 
 		INIT_LIST_HEAD(&mchan->free);
 		INIT_LIST_HEAD(&mchan->prepared);
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index ad7d03f..c6a84da 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -435,7 +435,7 @@ static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
 	}
 
 	if (cookie > 0)
-		mv_chan->completed_cookie = cookie;
+		mv_chan->common.completed_cookie = cookie;
 }
 
 static void
@@ -825,7 +825,7 @@ static enum dma_status mv_xor_status(struct dma_chan *chan,
 	enum dma_status ret;
 
 	last_used = chan->cookie;
-	last_complete = mv_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -836,7 +836,7 @@ static enum dma_status mv_xor_status(struct dma_chan *chan,
 	mv_xor_slot_cleanup(mv_chan);
 
 	last_used = chan->cookie;
-	last_complete = mv_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 	return dma_async_is_complete(cookie, last_complete, last_used);
diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h
index da04ac2..654876b 100644
--- a/drivers/dma/mv_xor.h
+++ b/drivers/dma/mv_xor.h
@@ -78,7 +78,6 @@ struct mv_xor_device {
 /**
  * struct mv_xor_chan - internal representation of a XOR channel
  * @pending: allows batching of hardware operations
- * @completed_cookie: identifier for the most recently completed operation
  * @lock: serializes enqueue/dequeue operations to the descriptors pool
  * @mmr_base: memory mapped register base
  * @idx: the index of the xor channel
@@ -93,7 +92,6 @@ struct mv_xor_device {
  */
 struct mv_xor_chan {
 	int			pending;
-	dma_cookie_t		completed_cookie;
 	spinlock_t		lock; /* protects the descriptor slot pool */
 	void __iomem		*mmr_base;
 	unsigned int		idx;
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index b06cd4c..3696e6e 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -111,7 +111,6 @@ struct mxs_dma_chan {
 	struct mxs_dma_ccw		*ccw;
 	dma_addr_t			ccw_phys;
 	int				desc_count;
-	dma_cookie_t			last_completed;
 	enum dma_status			status;
 	unsigned int			flags;
 #define MXS_DMA_SG_LOOP			(1 << 0)
@@ -274,7 +273,7 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
 		stat1 &= ~(1 << channel);
 
 		if (mxs_chan->status == DMA_SUCCESS)
-			mxs_chan->last_completed = mxs_chan->desc.cookie;
+			mxs_chan->chan.completed_cookie = mxs_chan->desc.cookie;
 
 		/* schedule tasklet on this channel */
 		tasklet_schedule(&mxs_chan->tasklet);
@@ -538,7 +537,7 @@ static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
 	dma_cookie_t last_used;
 
 	last_used = chan->cookie;
-	dma_set_tx_state(txstate, mxs_chan->last_completed, last_used, 0);
+	dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
 
 	return mxs_chan->status;
 }
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index 823f581..79a7185 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -105,7 +105,6 @@ struct pch_dma_chan {
 
 	spinlock_t		lock;
 
-	dma_cookie_t		completed_cookie;
 	struct list_head	active_list;
 	struct list_head	queue;
 	struct list_head	free_list;
@@ -544,7 +543,7 @@ static int pd_alloc_chan_resources(struct dma_chan *chan)
 	spin_lock_irq(&pd_chan->lock);
 	list_splice(&tmp_list, &pd_chan->free_list);
 	pd_chan->descs_allocated = i;
-	pd_chan->completed_cookie = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 	spin_unlock_irq(&pd_chan->lock);
 
 	pdc_enable_irq(chan, 1);
@@ -583,7 +582,7 @@ static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 	int ret;
 
 	spin_lock_irq(&pd_chan->lock);
-	last_completed = pd_chan->completed_cookie;
+	last_completed = chan->completed_cookie;
 	last_used = chan->cookie;
 	spin_unlock_irq(&pd_chan->lock);
 
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index b8ec03e..bdf04f1 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -51,9 +51,6 @@ struct dma_pl330_chan {
 	/* DMA-Engine Channel */
 	struct dma_chan chan;
 
-	/* Last completed cookie */
-	dma_cookie_t completed;
-
 	/* List of to be xfered descriptors */
 	struct list_head work_list;
 
@@ -234,7 +231,7 @@ static void pl330_tasklet(unsigned long data)
 	/* Pick up ripe tomatoes */
 	list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
 		if (desc->status == DONE) {
-			pch->completed = desc->txd.cookie;
+			pch->chan.completed_cookie = desc->txd.cookie;
 			list_move_tail(&desc->node, &list);
 		}
 
@@ -305,7 +302,7 @@ static int pl330_alloc_chan_resources(struct dma_chan *chan)
 
 	spin_lock_irqsave(&pch->lock, flags);
 
-	pch->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 	pch->cyclic = false;
 
 	pch->pl330_chid = pl330_request_channel(&pdmac->pif);
@@ -400,7 +397,7 @@ pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 	dma_cookie_t last_done, last_used;
 	int ret;
 
-	last_done = pch->completed;
+	last_done = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_done, last_used);
diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c
index fc457a7..f878322 100644
--- a/drivers/dma/ppc4xx/adma.c
+++ b/drivers/dma/ppc4xx/adma.c
@@ -1930,7 +1930,7 @@ static void __ppc440spe_adma_slot_cleanup(struct ppc440spe_adma_chan *chan)
 				if (end_of_chain && slot_cnt) {
 					/* Should wait for ZeroSum completion */
 					if (cookie > 0)
-						chan->completed_cookie = cookie;
+						chan->common.completed_cookie = cookie;
 					return;
 				}
 
@@ -1960,7 +1960,7 @@ static void __ppc440spe_adma_slot_cleanup(struct ppc440spe_adma_chan *chan)
 	BUG_ON(!seen_current);
 
 	if (cookie > 0) {
-		chan->completed_cookie = cookie;
+		chan->common.completed_cookie = cookie;
 		pr_debug("\tcompleted cookie %d\n", cookie);
 	}
 
@@ -3950,7 +3950,7 @@ static enum dma_status ppc440spe_adma_tx_status(struct dma_chan *chan,
 
 	ppc440spe_chan = to_ppc440spe_adma_chan(chan);
 	last_used = chan->cookie;
-	last_complete = ppc440spe_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 
@@ -3961,7 +3961,7 @@ static enum dma_status ppc440spe_adma_tx_status(struct dma_chan *chan,
 	ppc440spe_adma_slot_cleanup(ppc440spe_chan);
 
 	last_used = chan->cookie;
-	last_complete = ppc440spe_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 
@@ -4058,7 +4058,7 @@ static void ppc440spe_chan_start_null_xor(struct ppc440spe_adma_chan *chan)
 		/* initialize the completed cookie to be less than
 		 * the most recently used cookie
 		 */
-		chan->completed_cookie = cookie - 1;
+		chan->common.completed_cookie = cookie - 1;
 		chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
 		/* channel should not be busy */
diff --git a/drivers/dma/ppc4xx/adma.h b/drivers/dma/ppc4xx/adma.h
index 8ada5a8..26b7a5e 100644
--- a/drivers/dma/ppc4xx/adma.h
+++ b/drivers/dma/ppc4xx/adma.h
@@ -81,7 +81,6 @@ struct ppc440spe_adma_device {
  * @common: common dmaengine channel object members
  * @all_slots: complete domain of slots usable by the channel
  * @pending: allows batching of hardware operations
- * @completed_cookie: identifier for the most recently completed operation
  * @slots_allocated: records the actual size of the descriptor slot pool
  * @hw_chain_inited: h/w descriptor chain initialization flag
  * @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs
@@ -99,7 +98,6 @@ struct ppc440spe_adma_chan {
 	struct list_head all_slots;
 	struct ppc440spe_adma_desc_slot *last_used;
 	int pending;
-	dma_cookie_t completed_cookie;
 	int slots_allocated;
 	int hw_chain_inited;
 	struct tasklet_struct irq_tasklet;
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index 812fd76..ae84c12 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -764,12 +764,12 @@ static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all
 			cookie = tx->cookie;
 
 		if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
-			if (sh_chan->completed_cookie != desc->cookie - 1)
+			if (sh_chan->common.completed_cookie != desc->cookie - 1)
 				dev_dbg(sh_chan->dev,
 					"Completing cookie %d, expected %d\n",
 					desc->cookie,
-					sh_chan->completed_cookie + 1);
-			sh_chan->completed_cookie = desc->cookie;
+					sh_chan->common.completed_cookie + 1);
+			sh_chan->common.completed_cookie = desc->cookie;
 		}
 
 		/* Call callback on the last chunk */
@@ -823,7 +823,7 @@ static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all
 		 * Terminating and the loop completed normally: forgive
 		 * uncompleted cookies
 		 */
-		sh_chan->completed_cookie = sh_chan->common.cookie;
+		sh_chan->common.completed_cookie = sh_chan->common.cookie;
 
 	spin_unlock_irqrestore(&sh_chan->desc_lock, flags);
 
@@ -891,7 +891,7 @@ static enum dma_status sh_dmae_tx_status(struct dma_chan *chan,
 	sh_dmae_chan_ld_cleanup(sh_chan, false);
 
 	/* First read completed cookie to avoid a skew */
-	last_complete = sh_chan->completed_cookie;
+	last_complete = chan->completed_cookie;
 	rmb();
 	last_used = chan->cookie;
 	BUG_ON(last_complete < 0);
diff --git a/drivers/dma/shdma.h b/drivers/dma/shdma.h
index 2b55a27..0b1d2c1 100644
--- a/drivers/dma/shdma.h
+++ b/drivers/dma/shdma.h
@@ -30,7 +30,6 @@ enum dmae_pm_state {
 };
 
 struct sh_dmae_chan {
-	dma_cookie_t completed_cookie;	/* The maximum cookie completed */
 	spinlock_t desc_lock;		/* Descriptor operation lock */
 	struct list_head ld_queue;	/* Link descriptors queue */
 	struct list_head ld_free;	/* Link descriptors free */
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 2333810..60473f0 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -59,7 +59,6 @@ struct sirfsoc_dma_chan {
 	struct list_head		queued;
 	struct list_head		active;
 	struct list_head		completed;
-	dma_cookie_t			completed_cookie;
 	unsigned long			happened_cyclic;
 	unsigned long			completed_cyclic;
 
@@ -208,7 +207,7 @@ static void sirfsoc_dma_process_completed(struct sirfsoc_dma *sdma)
 			/* Free descriptors */
 			spin_lock_irqsave(&schan->lock, flags);
 			list_splice_tail_init(&list, &schan->free);
-			schan->completed_cookie = last_cookie;
+			schan->chan.completed_cookie = last_cookie;
 			spin_unlock_irqrestore(&schan->lock, flags);
 		} else {
 			/* for cyclic channel, desc is always in active list */
@@ -419,7 +418,7 @@ sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 
 	spin_lock_irqsave(&schan->lock, flags);
 	last_used = schan->chan.cookie;
-	last_complete = schan->completed_cookie;
+	last_complete = schan->chan.completed_cookie;
 	spin_unlock_irqrestore(&schan->lock, flags);
 
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
@@ -636,7 +635,7 @@ static int __devinit sirfsoc_dma_probe(struct platform_device *op)
 
 		schan->chan.device = dma;
 		schan->chan.cookie = 1;
-		schan->completed_cookie = schan->chan.cookie;
+		schan->chan.completed_cookie = schan->chan.cookie;
 
 		INIT_LIST_HEAD(&schan->free);
 		INIT_LIST_HEAD(&schan->prepared);
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index cc5ecbc..cfca2a0 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -220,8 +220,6 @@ struct d40_base;
  *
  * @lock: A spinlock to protect this struct.
  * @log_num: The logical number, if any of this channel.
- * @completed: Starts with 1, after first interrupt it is set to dma engine's
- * current cookie.
  * @pending_tx: The number of pending transfers. Used between interrupt handler
  * and tasklet.
  * @busy: Set to true when transfer is ongoing on this channel.
@@ -250,8 +248,6 @@ struct d40_base;
 struct d40_chan {
 	spinlock_t			 lock;
 	int				 log_num;
-	/* ID of the most recent completed transfer */
-	int				 completed;
 	int				 pending_tx;
 	bool				 busy;
 	struct d40_phy_res		*phy_chan;
@@ -1357,7 +1353,7 @@ static void dma_tasklet(unsigned long data)
 		goto err;
 
 	if (!d40d->cyclic)
-		d40c->completed = d40d->txd.cookie;
+		d40c->chan.completed_cookie = d40d->txd.cookie;
 
 	/*
 	 * If terminating a channel pending_tx is set to zero.
@@ -2182,7 +2178,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 	bool is_free_phy;
 	spin_lock_irqsave(&d40c->lock, flags);
 
-	d40c->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 
 	/* If no dma configuration is set use default configuration (memcpy) */
 	if (!d40c->configured) {
@@ -2351,7 +2347,7 @@ static enum dma_status d40_tx_status(struct dma_chan *chan,
 		return -EINVAL;
 	}
 
-	last_complete = d40c->completed;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	if (d40_is_paused(d40c))
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index a6f9c16..a1d1559 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -84,7 +84,6 @@ struct timb_dma_chan {
 					especially the lists and descriptors,
 					from races between the tasklet and calls
 					from above */
-	dma_cookie_t		last_completed_cookie;
 	bool			ongoing;
 	struct list_head	active_list;
 	struct list_head	queue;
@@ -284,7 +283,7 @@ static void __td_finish(struct timb_dma_chan *td_chan)
 	else
 		iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR);
 */
-	td_chan->last_completed_cookie = txd->cookie;
+	td_chan->chan.completed_cookie = txd->cookie;
 	td_chan->ongoing = false;
 
 	callback = txd->callback;
@@ -481,7 +480,7 @@ static int td_alloc_chan_resources(struct dma_chan *chan)
 	}
 
 	spin_lock_bh(&td_chan->lock);
-	td_chan->last_completed_cookie = 1;
+	chan->completed_cookie = 1;
 	chan->cookie = 1;
 	spin_unlock_bh(&td_chan->lock);
 
@@ -523,7 +522,7 @@ static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 
 	dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
 
-	last_complete = td_chan->last_completed_cookie;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index 6122c36..a917b67 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -424,7 +424,7 @@ txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
 	dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
 		 txd->cookie, desc);
 
-	dc->completed = txd->cookie;
+	dc->chan.completed_cookie = txd->cookie;
 	callback = txd->callback;
 	param = txd->callback_param;
 
@@ -976,7 +976,7 @@ txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 	dma_cookie_t last_complete;
 	int ret;
 
-	last_complete = dc->completed;
+	last_complete = chan->completed_cookie;
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -985,7 +985,7 @@ txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 		txx9dmac_scan_descriptors(dc);
 		spin_unlock_bh(&dc->lock);
 
-		last_complete = dc->completed;
+		last_complete = chan->completed_cookie;
 		last_used = chan->cookie;
 
 		ret = dma_async_is_complete(cookie, last_complete, last_used);
@@ -1057,7 +1057,7 @@ static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
 		return -EIO;
 	}
 
-	dc->completed = chan->cookie = 1;
+	chan->completed_cookie = chan->cookie = 1;
 
 	dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
 	txx9dmac_chan_set_SMPCHN(dc);
@@ -1186,7 +1186,7 @@ static int __init txx9dmac_chan_probe(struct platform_device *pdev)
 	dc->ddev->chan[ch] = dc;
 	dc->chan.device = &dc->dma;
 	list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
-	dc->chan.cookie = dc->completed = 1;
+	dc->chan.cookie = dc->chan.completed_cookie = 1;
 
 	if (is_dmac64(dc))
 		dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
diff --git a/drivers/dma/txx9dmac.h b/drivers/dma/txx9dmac.h
index 365d423..f5a7605 100644
--- a/drivers/dma/txx9dmac.h
+++ b/drivers/dma/txx9dmac.h
@@ -172,7 +172,6 @@ struct txx9dmac_chan {
 	spinlock_t		lock;
 
 	/* these other elements are all protected by lock */
-	dma_cookie_t		completed;
 	struct list_head	active_list;
 	struct list_head	queue;
 	struct list_head	free_list;
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
index 033f6aa..1bb134b 100644
--- a/include/linux/amba/pl08x.h
+++ b/include/linux/amba/pl08x.h
@@ -176,7 +176,6 @@ enum pl08x_dma_chan_state {
  * @runtime_addr: address for RX/TX according to the runtime config
  * @runtime_direction: current direction of this channel according to
  * runtime config
- * @lc: last completed transaction on this channel
  * @pend_list: queued transactions pending on this channel
  * @at: active transaction on this channel
  * @lock: a lock for this channel data
@@ -198,7 +197,6 @@ struct pl08x_dma_chan {
 	u32 src_cctl;
 	u32 dst_cctl;
 	enum dma_transfer_direction runtime_direction;
-	dma_cookie_t lc;
 	struct list_head pend_list;
 	struct pl08x_txd *at;
 	spinlock_t lock;
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 679b349..41d0f92 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -257,6 +257,7 @@ struct dma_chan_percpu {
  * struct dma_chan - devices supply DMA channels, clients use them
  * @device: ptr to the dma device who supplies this channel, always !%NULL
  * @cookie: last cookie value returned to client
+ * @completed_cookie: last completed cookie for this channel
  * @chan_id: channel ID for sysfs
  * @dev: class device for sysfs
  * @device_node: used to add this to the device chan list
@@ -268,6 +269,7 @@ struct dma_chan_percpu {
 struct dma_chan {
 	struct dma_device *device;
 	dma_cookie_t cookie;
+	dma_cookie_t completed_cookie;
 
 	/* sysfs */
 	int chan_id;
-- 
1.7.4.4



From linux at arm.linux.org.uk  Tue Mar  6 17:34:46 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 06 Mar 2012 22:34:46 +0000
Subject: [PATCH 4/9] dmaengine: consolidate assignment of DMA cookies
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <E1S52xy-0002Ms-Ud@rmk-PC.arm.linux.org.uk>

Everyone deals with assigning DMA cookies in the same way (it's part of
the API so they should be), so lets consolidate the common code into a
helper function to avoid this duplication.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/amba-pl08x.c    |    9 +++------
 drivers/dma/at_hdmac.c      |   23 +----------------------
 drivers/dma/coh901318.c     |   20 +++-----------------
 drivers/dma/dmaengine.h     |   20 ++++++++++++++++++++
 drivers/dma/dw_dmac.c       |   17 +----------------
 drivers/dma/ep93xx_dma.c    |    9 +--------
 drivers/dma/fsldma.c        |    9 +--------
 drivers/dma/imx-dma.c       |   15 +--------------
 drivers/dma/imx-sdma.c      |   15 +--------------
 drivers/dma/intel_mid_dma.c |    9 +--------
 drivers/dma/ioat/dma.c      |    7 +------
 drivers/dma/ioat/dma_v2.c   |    8 ++------
 drivers/dma/iop-adma.c      |   14 +-------------
 drivers/dma/ipu/ipu_idmac.c |    9 +--------
 drivers/dma/mpc512x_dma.c   |    8 +-------
 drivers/dma/mv_xor.c        |   14 +-------------
 drivers/dma/mxs-dma.c       |   15 +--------------
 drivers/dma/pch_dma.c       |   16 +---------------
 drivers/dma/pl330.c         |   14 ++------------
 drivers/dma/ppc4xx/adma.c   |   19 +------------------
 drivers/dma/shdma.c         |    8 +-------
 drivers/dma/sirf-dma.c      |    8 +-------
 drivers/dma/ste_dma40.c     |   13 +++----------
 drivers/dma/timb_dma.c      |    7 +------
 drivers/dma/txx9dmac.c      |   17 +----------------
 25 files changed, 52 insertions(+), 271 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 87475cb..5996386 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -921,13 +921,10 @@ static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
 	struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
 	struct pl08x_txd *txd = to_pl08x_txd(tx);
 	unsigned long flags;
+	dma_cookie_t cookie;
 
 	spin_lock_irqsave(&plchan->lock, flags);
-
-	plchan->chan.cookie += 1;
-	if (plchan->chan.cookie < 0)
-		plchan->chan.cookie = 1;
-	tx->cookie = plchan->chan.cookie;
+	cookie = dma_cookie_assign(tx);
 
 	/* Put this onto the pending list */
 	list_add_tail(&txd->node, &plchan->pend_list);
@@ -947,7 +944,7 @@ static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	spin_unlock_irqrestore(&plchan->lock, flags);
 
-	return tx->cookie;
+	return cookie;
 }
 
 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index ce26ba3..df47e7d 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -193,27 +193,6 @@ static void atc_desc_chain(struct at_desc **first, struct at_desc **prev,
 }
 
 /**
- * atc_assign_cookie - compute and assign new cookie
- * @atchan: channel we work on
- * @desc: descriptor to assign cookie for
- *
- * Called with atchan->lock held and bh disabled
- */
-static dma_cookie_t
-atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc)
-{
-	dma_cookie_t cookie = atchan->chan_common.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	atchan->chan_common.cookie = cookie;
-	desc->txd.cookie = cookie;
-
-	return cookie;
-}
-
-/**
  * atc_dostart - starts the DMA engine for real
  * @atchan: the channel we want to start
  * @first: first descriptor in the list we want to begin with
@@ -548,7 +527,7 @@ static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
 	unsigned long		flags;
 
 	spin_lock_irqsave(&atchan->lock, flags);
-	cookie = atc_assign_cookie(atchan, desc);
+	cookie = dma_cookie_assign(tx);
 
 	if (list_empty(&atchan->active_list)) {
 		dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index fb0d124..843a1a3 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -318,20 +318,6 @@ static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
 
 	return 0;
 }
-static dma_cookie_t
-coh901318_assign_cookie(struct coh901318_chan *cohc,
-			struct coh901318_desc *cohd)
-{
-	dma_cookie_t cookie = cohc->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	cohc->chan.cookie = cookie;
-	cohd->desc.cookie = cookie;
-
-	return cookie;
-}
 
 static struct coh901318_desc *
 coh901318_desc_get(struct coh901318_chan *cohc)
@@ -966,16 +952,16 @@ coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
 						   desc);
 	struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
 	unsigned long flags;
+	dma_cookie_t cookie;
 
 	spin_lock_irqsave(&cohc->lock, flags);
-
-	tx->cookie = coh901318_assign_cookie(cohc, cohd);
+	cookie = dma_cookie_assign(tx);
 
 	coh901318_desc_queue(cohc, cohd);
 
 	spin_unlock_irqrestore(&cohc->lock, flags);
 
-	return tx->cookie;
+	return cookie;
 }
 
 static struct dma_async_tx_descriptor *
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
index 968570d..7692c86 100644
--- a/drivers/dma/dmaengine.h
+++ b/drivers/dma/dmaengine.h
@@ -7,4 +7,24 @@
 
 #include <linux/dmaengine.h>
 
+/**
+ * dma_cookie_assign - assign a DMA engine cookie to the descriptor
+ * @tx: descriptor needing cookie
+ *
+ * Assign a unique non-zero per-channel cookie to the descriptor.
+ * Note: caller is expected to hold a lock to prevent concurrency.
+ */
+static inline dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx)
+{
+	struct dma_chan *chan = tx->chan;
+	dma_cookie_t cookie;
+
+	cookie = chan->cookie + 1;
+	if (cookie < DMA_MIN_COOKIE)
+		cookie = DMA_MIN_COOKIE;
+	tx->cookie = chan->cookie = cookie;
+
+	return cookie;
+}
+
 #endif
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index f10dbe1..5ee9498 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -152,21 +152,6 @@ static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 	}
 }
 
-/* Called with dwc->lock held and bh disabled */
-static dma_cookie_t
-dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc)
-{
-	dma_cookie_t cookie = dwc->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	dwc->chan.cookie = cookie;
-	desc->txd.cookie = cookie;
-
-	return cookie;
-}
-
 static void dwc_initialize(struct dw_dma_chan *dwc)
 {
 	struct dw_dma *dw = to_dw_dma(dwc->chan.device);
@@ -616,7 +601,7 @@ static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 	unsigned long		flags;
 
 	spin_lock_irqsave(&dwc->lock, flags);
-	cookie = dwc_assign_cookie(dwc, desc);
+	cookie = dma_cookie_assign(tx);
 
 	/*
 	 * REVISIT: We should attempt to chain as many descriptors as
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index 3260198..e5aaae8 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -783,17 +783,10 @@ static dma_cookie_t ep93xx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 	unsigned long flags;
 
 	spin_lock_irqsave(&edmac->lock, flags);
-
-	cookie = edmac->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
+	cookie = dma_cookie_assign(tx);
 
 	desc = container_of(tx, struct ep93xx_dma_desc, txd);
 
-	edmac->chan.cookie = cookie;
-	desc->txd.cookie = cookie;
-
 	/*
 	 * If nothing is currently prosessed, we push this descriptor
 	 * directly to the hardware. Otherwise we put the descriptor
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 2ebbe57..04b4347 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -414,17 +414,10 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 	 * assign cookies to all of the software descriptors
 	 * that make up this transaction
 	 */
-	cookie = chan->common.cookie;
 	list_for_each_entry(child, &desc->tx_list, node) {
-		cookie++;
-		if (cookie < DMA_MIN_COOKIE)
-			cookie = DMA_MIN_COOKIE;
-
-		child->async_tx.cookie = cookie;
+		cookie = dma_cookie_assign(&child->async_tx);
 	}
 
-	chan->common.cookie = cookie;
-
 	/* put this transaction onto the tail of the pending queue */
 	append_ld_queue(chan, desc);
 
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 51251a6..42154b6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -165,19 +165,6 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 	return ret;
 }
 
-static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma)
-{
-	dma_cookie_t cookie = imxdma->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	imxdma->chan.cookie = cookie;
-	imxdma->desc.cookie = cookie;
-
-	return cookie;
-}
-
 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
@@ -185,7 +172,7 @@ static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	spin_lock_irq(&imxdmac->lock);
 
-	cookie = imxdma_assign_cookie(imxdmac);
+	cookie = dma_cookie_assign(tx);
 
 	imx_dma_enable(imxdmac->imxdma_channel);
 
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 9950ec3..4e4f40e 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -817,19 +817,6 @@ static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 	__raw_writel(1 << channel, sdma->regs + SDMA_H_START);
 }
 
-static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
-{
-	dma_cookie_t cookie = sdmac->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	sdmac->chan.cookie = cookie;
-	sdmac->desc.cookie = cookie;
-
-	return cookie;
-}
-
 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 {
 	return container_of(chan, struct sdma_channel, chan);
@@ -844,7 +831,7 @@ static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	spin_lock_irqsave(&sdmac->lock, flags);
 
-	cookie = sdma_assign_cookie(sdmac);
+	cookie = dma_cookie_assign(tx);
 
 	sdma_enable_channel(sdma, sdmac->channel);
 
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index a907dd6..dfe4396 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -436,14 +436,7 @@ static dma_cookie_t intel_mid_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 	dma_cookie_t		cookie;
 
 	spin_lock_bh(&midc->lock);
-	cookie = midc->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	midc->chan.cookie = cookie;
-	desc->txd.cookie = cookie;
-
+	cookie = dma_cookie_assign(tx);
 
 	if (list_empty(&midc->active_list))
 		list_add_tail(&desc->desc_node, &midc->active_list);
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index dfe411b..5c06117 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -237,12 +237,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	spin_lock_bh(&ioat->desc_lock);
 	/* cookie incr and addition to used_list must be atomic */
-	cookie = c->cookie;
-	cookie++;
-	if (cookie < 0)
-		cookie = 1;
-	c->cookie = cookie;
-	tx->cookie = cookie;
+	cookie = dma_cookie_assign(tx);
 	dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 
 	/* write address into NextDescriptor field of last desc in chain */
diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c
index 6c1e675..17ecacb 100644
--- a/drivers/dma/ioat/dma_v2.c
+++ b/drivers/dma/ioat/dma_v2.c
@@ -400,13 +400,9 @@ static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
 	struct dma_chan *c = tx->chan;
 	struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
 	struct ioat_chan_common *chan = &ioat->base;
-	dma_cookie_t cookie = c->cookie;
+	dma_cookie_t cookie;
 
-	cookie++;
-	if (cookie < 0)
-		cookie = 1;
-	tx->cookie = cookie;
-	c->cookie = cookie;
+	cookie = dma_cookie_assign(tx);
 	dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 
 	if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index 650bf1e..f2392d5 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -440,18 +440,6 @@ iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
 	return NULL;
 }
 
-static dma_cookie_t
-iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
-	struct iop_adma_desc_slot *desc)
-{
-	dma_cookie_t cookie = iop_chan->common.cookie;
-	cookie++;
-	if (cookie < 0)
-		cookie = 1;
-	iop_chan->common.cookie = desc->async_tx.cookie = cookie;
-	return cookie;
-}
-
 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
 {
 	dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
@@ -479,7 +467,7 @@ iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
 	slots_per_op = grp_start->slots_per_op;
 
 	spin_lock_bh(&iop_chan->lock);
-	cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
+	cookie = dma_cookie_assign(tx);
 
 	old_chain_tail = list_entry(iop_chan->chain.prev,
 		struct iop_adma_desc_slot, chain_node);
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index 0fcff65..d4620c5 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -867,14 +867,7 @@ static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
 
-	cookie = ichan->dma_chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	/* from dmaengine.h: "last cookie value returned to client" */
-	ichan->dma_chan.cookie = cookie;
-	tx->cookie = cookie;
+	cookie = dma_cookie_assign(tx);
 
 	/* ipu->lock can be taken under ichan->lock, but not v.v. */
 	spin_lock_irqsave(&ichan->lock, flags);
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index c56b3fe..0253d5a 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -439,13 +439,7 @@ static dma_cookie_t mpc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
 		mpc_dma_execute(mchan);
 
 	/* Update cookie */
-	cookie = mchan->chan.cookie + 1;
-	if (cookie <= 0)
-		cookie = 1;
-
-	mchan->chan.cookie = cookie;
-	mdesc->desc.cookie = cookie;
-
+	cookie = dma_cookie_assign(txd);
 	spin_unlock_irqrestore(&mchan->lock, flags);
 
 	return cookie;
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index ee61778..d9810ce 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -536,18 +536,6 @@ mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots,
 	return NULL;
 }
 
-static dma_cookie_t
-mv_desc_assign_cookie(struct mv_xor_chan *mv_chan,
-		      struct mv_xor_desc_slot *desc)
-{
-	dma_cookie_t cookie = mv_chan->common.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-	mv_chan->common.cookie = desc->async_tx.cookie = cookie;
-	return cookie;
-}
-
 /************************ DMA engine API functions ****************************/
 static dma_cookie_t
 mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
@@ -565,7 +553,7 @@ mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
 	grp_start = sw_desc->group_head;
 
 	spin_lock_bh(&mv_chan->lock);
-	cookie = mv_desc_assign_cookie(mv_chan, sw_desc);
+	cookie = dma_cookie_assign(tx);
 
 	if (list_empty(&mv_chan->chain))
 		list_splice_init(&sw_desc->tx_list, &mv_chan->chain);
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index daa84ee..4d3b6ff 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -194,19 +194,6 @@ static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
 	mxs_chan->status = DMA_IN_PROGRESS;
 }
 
-static dma_cookie_t mxs_dma_assign_cookie(struct mxs_dma_chan *mxs_chan)
-{
-	dma_cookie_t cookie = mxs_chan->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	mxs_chan->chan.cookie = cookie;
-	mxs_chan->desc.cookie = cookie;
-
-	return cookie;
-}
-
 static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
 {
 	return container_of(chan, struct mxs_dma_chan, chan);
@@ -218,7 +205,7 @@ static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 
 	mxs_dma_enable_chan(mxs_chan);
 
-	return mxs_dma_assign_cookie(mxs_chan);
+	return dma_cookie_assign(tx);
 }
 
 static void mxs_dma_tasklet(unsigned long data)
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index 2b3479d..5218e48 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -417,20 +417,6 @@ static void pdc_advance_work(struct pch_dma_chan *pd_chan)
 	}
 }
 
-static dma_cookie_t pdc_assign_cookie(struct pch_dma_chan *pd_chan,
-				      struct pch_dma_desc *desc)
-{
-	dma_cookie_t cookie = pd_chan->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	pd_chan->chan.cookie = cookie;
-	desc->txd.cookie = cookie;
-
-	return cookie;
-}
-
 static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd)
 {
 	struct pch_dma_desc *desc = to_pd_desc(txd);
@@ -438,7 +424,7 @@ static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd)
 	dma_cookie_t cookie;
 
 	spin_lock(&pd_chan->lock);
-	cookie = pdc_assign_cookie(pd_chan, desc);
+	cookie = dma_cookie_assign(txd);
 
 	if (list_empty(&pd_chan->active_list)) {
 		list_add_tail(&desc->desc_node, &pd_chan->active_list);
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index d7b0af2..ec9638b 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -429,26 +429,16 @@ static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
 	spin_lock_irqsave(&pch->lock, flags);
 
 	/* Assign cookies to all nodes */
-	cookie = tx->chan->cookie;
-
 	while (!list_empty(&last->node)) {
 		desc = list_entry(last->node.next, struct dma_pl330_desc, node);
 
-		if (++cookie < 0)
-			cookie = 1;
-		desc->txd.cookie = cookie;
+		dma_cookie_assign(&desc->txd);
 
 		list_move_tail(&desc->node, &pch->work_list);
 	}
 
-	if (++cookie < 0)
-		cookie = 1;
-	last->txd.cookie = cookie;
-
+	cookie = dma_cookie_assign(&last->txd);
 	list_add_tail(&last->node, &pch->work_list);
-
-	tx->chan->cookie = cookie;
-
 	spin_unlock_irqrestore(&pch->lock, flags);
 
 	return cookie;
diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c
index 40082ec..12e94dd 100644
--- a/drivers/dma/ppc4xx/adma.c
+++ b/drivers/dma/ppc4xx/adma.c
@@ -2151,22 +2151,6 @@ static int ppc440spe_adma_alloc_chan_resources(struct dma_chan *chan)
 }
 
 /**
- * ppc440spe_desc_assign_cookie - assign a cookie
- */
-static dma_cookie_t ppc440spe_desc_assign_cookie(
-		struct ppc440spe_adma_chan *chan,
-		struct ppc440spe_adma_desc_slot *desc)
-{
-	dma_cookie_t cookie = chan->common.cookie;
-
-	cookie++;
-	if (cookie < 0)
-		cookie = 1;
-	chan->common.cookie = desc->async_tx.cookie = cookie;
-	return cookie;
-}
-
-/**
  * ppc440spe_rxor_set_region_data -
  */
 static void ppc440spe_rxor_set_region(struct ppc440spe_adma_desc_slot *desc,
@@ -2236,8 +2220,7 @@ static dma_cookie_t ppc440spe_adma_tx_submit(struct dma_async_tx_descriptor *tx)
 	slots_per_op = group_start->slots_per_op;
 
 	spin_lock_bh(&chan->lock);
-
-	cookie = ppc440spe_desc_assign_cookie(chan, sw_desc);
+	cookie = dma_cookie_assign(tx);
 
 	if (unlikely(list_empty(&chan->chain))) {
 		/* first peer */
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index c291433..96d0a4f 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -298,13 +298,7 @@ static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
 	else
 		power_up = false;
 
-	cookie = sh_chan->common.cookie;
-	cookie++;
-	if (cookie < 0)
-		cookie = 1;
-
-	sh_chan->common.cookie = cookie;
-	tx->cookie = cookie;
+	cookie = dma_cookie_assign(tx);
 
 	/* Mark all chunks of this descriptor as submitted, move to the queue */
 	list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 60473f0..7bb154a 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -257,13 +257,7 @@ static dma_cookie_t sirfsoc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
 	/* Move descriptor to queue */
 	list_move_tail(&sdesc->node, &schan->queued);
 
-	/* Update cookie */
-	cookie = schan->chan.cookie + 1;
-	if (cookie <= 0)
-		cookie = 1;
-
-	schan->chan.cookie = cookie;
-	sdesc->desc.cookie = cookie;
+	cookie = dma_cookie_assign(txd);
 
 	spin_unlock_irqrestore(&schan->lock, flags);
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 156b98f..23e2edc 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1220,21 +1220,14 @@ static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
 					     chan);
 	struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
 	unsigned long flags;
+	dma_cookie_t cookie;
 
 	spin_lock_irqsave(&d40c->lock, flags);
-
-	d40c->chan.cookie++;
-
-	if (d40c->chan.cookie < 0)
-		d40c->chan.cookie = 1;
-
-	d40d->txd.cookie = d40c->chan.cookie;
-
+	cookie = dma_cookie_assign(tx);
 	d40_desc_queue(d40c, d40d);
-
 	spin_unlock_irqrestore(&d40c->lock, flags);
 
-	return tx->cookie;
+	return cookie;
 }
 
 static int d40_start(struct d40_chan *d40c)
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index 4b61879..b6e83fc 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -350,12 +350,7 @@ static dma_cookie_t td_tx_submit(struct dma_async_tx_descriptor *txd)
 	dma_cookie_t cookie;
 
 	spin_lock_bh(&td_chan->lock);
-
-	cookie = txd->chan->cookie;
-	if (++cookie < 0)
-		cookie = 1;
-	txd->chan->cookie = cookie;
-	txd->cookie = cookie;
+	cookie = dma_cookie_assign(txd);
 
 	if (list_empty(&td_chan->active_list)) {
 		dev_dbg(chan2dev(txd->chan), "%s: started %u\n", __func__,
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index db6d809..66f8fca 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -281,21 +281,6 @@ static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
 	}
 }
 
-/* Called with dc->lock held and bh disabled */
-static dma_cookie_t
-txx9dmac_assign_cookie(struct txx9dmac_chan *dc, struct txx9dmac_desc *desc)
-{
-	dma_cookie_t cookie = dc->chan.cookie;
-
-	if (++cookie < 0)
-		cookie = 1;
-
-	dc->chan.cookie = cookie;
-	desc->txd.cookie = cookie;
-
-	return cookie;
-}
-
 /*----------------------------------------------------------------------*/
 
 static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
@@ -740,7 +725,7 @@ static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
 	dma_cookie_t cookie;
 
 	spin_lock_bh(&dc->lock);
-	cookie = txx9dmac_assign_cookie(dc, desc);
+	cookie = dma_cookie_assign(tx);
 
 	dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
 		 desc->txd.cookie, desc);
-- 
1.7.4.4



From linux at arm.linux.org.uk  Tue Mar  6 17:35:07 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 06 Mar 2012 22:35:07 +0000
Subject: [PATCH 5/9] dmaengine: provide a common function for completing a
 dma descriptor
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <E1S52yJ-0002Mx-2e@rmk-PC.arm.linux.org.uk>

Provide a common function to do the cookie mechanics for completing
a DMA descriptor.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/amba-pl08x.c    |    2 +-
 drivers/dma/at_hdmac.c      |    2 +-
 drivers/dma/coh901318.c     |    2 +-
 drivers/dma/dmaengine.h     |   18 ++++++++++++++++++
 drivers/dma/dw_dmac.c       |    2 +-
 drivers/dma/ep93xx_dma.c    |    2 +-
 drivers/dma/fsldma.c        |    2 +-
 drivers/dma/imx-dma.c       |    2 +-
 drivers/dma/imx-sdma.c      |    2 +-
 drivers/dma/intel_mid_dma.c |    2 +-
 drivers/dma/ioat/dma.c      |    3 +--
 drivers/dma/ioat/dma_v2.c   |    3 +--
 drivers/dma/ioat/dma_v3.c   |    3 +--
 drivers/dma/ipu/ipu_idmac.c |    2 +-
 drivers/dma/mxs-dma.c       |    2 +-
 drivers/dma/pl330.c         |    2 +-
 drivers/dma/ste_dma40.c     |    2 +-
 drivers/dma/timb_dma.c      |    2 +-
 drivers/dma/txx9dmac.c      |    2 +-
 19 files changed, 36 insertions(+), 21 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 5996386..f0888c1 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -1540,7 +1540,7 @@ static void pl08x_tasklet(unsigned long data)
 
 	if (txd) {
 		/* Update last completed */
-		plchan->chan.completed_cookie = txd->tx.cookie;
+		dma_cookie_complete(&txd->tx);
 	}
 
 	/* If a new descriptor is queued, set it up plchan->at is NULL here */
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index df47e7d..b282630 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -249,7 +249,7 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
 	dev_vdbg(chan2dev(&atchan->chan_common),
 		"descriptor %u complete\n", txd->cookie);
 
-	atchan->chan_common.completed_cookie = txd->cookie;
+	dma_cookie_complete(txd);
 
 	/* move children to free_list */
 	list_splice_init(&desc->tx_list, &atchan->free_list);
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 843a1a3..24837d7 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -691,7 +691,7 @@ static void dma_tasklet(unsigned long data)
 	callback_param = cohd_fin->desc.callback_param;
 
 	/* sign this job as completed on the channel */
-	cohc->chan.completed_cookie = cohd_fin->desc.cookie;
+	dma_cookie_complete(&cohd_fin->desc);
 
 	/* release the lli allocation and remove the descriptor */
 	coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
index 7692c86..47e0997 100644
--- a/drivers/dma/dmaengine.h
+++ b/drivers/dma/dmaengine.h
@@ -5,6 +5,7 @@
 #ifndef DMAENGINE_H
 #define DMAENGINE_H
 
+#include <linux/bug.h>
 #include <linux/dmaengine.h>
 
 /**
@@ -27,4 +28,21 @@ static inline dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx)
 	return cookie;
 }
 
+/**
+ * dma_cookie_complete - complete a descriptor
+ * @tx: descriptor to complete
+ *
+ * Mark this descriptor complete by updating the channels completed
+ * cookie marker.  Zero the descriptors cookie to prevent accidental
+ * repeated completions.
+ *
+ * Note: caller is expected to hold a lock to prevent concurrency.
+ */
+static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
+{
+	BUG_ON(tx->cookie < DMA_MIN_COOKIE);
+	tx->chan->completed_cookie = tx->cookie;
+	tx->cookie = 0;
+}
+
 #endif
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 5ee9498..a190c88 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -231,7 +231,7 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 	dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 
 	spin_lock_irqsave(&dwc->lock, flags);
-	dwc->chan.completed_cookie = txd->cookie;
+	dma_cookie_complete(txd);
 	if (callback_required) {
 		callback = txd->callback;
 		param = txd->callback_param;
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index e5aaae8..1c56f75 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -703,7 +703,7 @@ static void ep93xx_dma_tasklet(unsigned long data)
 	desc = ep93xx_dma_get_active(edmac);
 	if (desc) {
 		if (desc->complete) {
-			edmac->chan.completed_cookie = desc->txd.cookie;
+			dma_cookie_complete(&desc->txd);
 			list_splice_init(&edmac->active, &list);
 		}
 		callback = desc->txd.callback;
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 04b4347..f36e8b1 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -1081,8 +1081,8 @@ static void dma_do_tasklet(unsigned long data)
 
 		desc = to_fsl_desc(chan->ld_running.prev);
 		cookie = desc->async_tx.cookie;
+		dma_cookie_complete(&desc->async_tx);
 
-		chan->common.completed_cookie = cookie;
 		chan_dbg(chan, "completed_cookie=%d\n", cookie);
 	}
 
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 42154b6..f1226ad 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -66,7 +66,7 @@ static void imxdma_handle(struct imxdma_channel *imxdmac)
 {
 	if (imxdmac->desc.callback)
 		imxdmac->desc.callback(imxdmac->desc.callback_param);
-	imxdmac->chan.completed_cookie = imxdmac->desc.cookie;
+	dma_cookie_complete(&imxdmac->desc);
 }
 
 static void imxdma_irq_handler(int channel, void *data)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 4e4f40e..4406be2 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -524,7 +524,7 @@ static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 	else
 		sdmac->status = DMA_SUCCESS;
 
-	sdmac->chan.completed_cookie = sdmac->desc.cookie;
+	dma_cookie_complete(&sdmac->desc);
 	if (sdmac->desc.callback)
 		sdmac->desc.callback(sdmac->desc.callback_param);
 }
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index dfe4396..340509e 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -290,7 +290,7 @@ static void midc_descriptor_complete(struct intel_mid_dma_chan *midc,
 	struct intel_mid_dma_lli	*llitem;
 	void *param_txd = NULL;
 
-	midc->chan.completed_cookie = txd->cookie;
+	dma_cookie_complete(txd);
 	callback_txd = txd->callback;
 	param_txd = txd->callback_param;
 
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index 5c06117..b0517c8 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -600,8 +600,7 @@ static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete)
 		 */
 		dump_desc_dbg(ioat, desc);
 		if (tx->cookie) {
-			chan->common.completed_cookie = tx->cookie;
-			tx->cookie = 0;
+			dma_cookie_complete(tx);
 			ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 			ioat->active -= desc->hw->tx_cnt;
 			if (tx->callback) {
diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c
index 17ecacb..e8e110f 100644
--- a/drivers/dma/ioat/dma_v2.c
+++ b/drivers/dma/ioat/dma_v2.c
@@ -149,8 +149,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
 		dump_desc_dbg(ioat, desc);
 		if (tx->cookie) {
 			ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
-			chan->common.completed_cookie = tx->cookie;
-			tx->cookie = 0;
+			dma_cookie_complete(tx);
 			if (tx->callback) {
 				tx->callback(tx->callback_param);
 				tx->callback = NULL;
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
index d4afac7..1bda46c 100644
--- a/drivers/dma/ioat/dma_v3.c
+++ b/drivers/dma/ioat/dma_v3.c
@@ -277,9 +277,8 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
 		dump_desc_dbg(ioat, desc);
 		tx = &desc->txd;
 		if (tx->cookie) {
-			chan->common.completed_cookie = tx->cookie;
+			dma_cookie_complete(tx);
 			ioat3_dma_unmap(ioat, desc, idx + i);
-			tx->cookie = 0;
 			if (tx->callback) {
 				tx->callback(tx->callback_param);
 				tx->callback = NULL;
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index d4620c5..bff9250 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -1289,7 +1289,7 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
 	/* Flip the active buffer - even if update above failed */
 	ichan->active_buffer = !ichan->active_buffer;
 	if (done)
-		ichan->dma_chan.completed_cookie = desc->txd.cookie;
+		dma_cookie_complete(&desc->txd);
 
 	callback = desc->txd.callback;
 	callback_param = desc->txd.callback_param;
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 4d3b6ff..5f3492e 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -262,7 +262,7 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
 		stat1 &= ~(1 << channel);
 
 		if (mxs_chan->status == DMA_SUCCESS)
-			mxs_chan->chan.completed_cookie = mxs_chan->desc.cookie;
+			dma_cookie_complete(&mxs_chan->desc);
 
 		/* schedule tasklet on this channel */
 		tasklet_schedule(&mxs_chan->tasklet);
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index ec9638b..76871b8 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -233,7 +233,7 @@ static void pl330_tasklet(unsigned long data)
 	/* Pick up ripe tomatoes */
 	list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
 		if (desc->status == DONE) {
-			pch->chan.completed_cookie = desc->txd.cookie;
+			dma_cookie_complete(&desc->txd);
 			list_move_tail(&desc->node, &list);
 		}
 
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 23e2edc..c246375 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1347,7 +1347,7 @@ static void dma_tasklet(unsigned long data)
 		goto err;
 
 	if (!d40d->cyclic)
-		d40c->chan.completed_cookie = d40d->txd.cookie;
+		dma_cookie_complete(&d40d->txd);
 
 	/*
 	 * If terminating a channel pending_tx is set to zero.
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index b6e83fc..1845ac9 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -285,7 +285,7 @@ static void __td_finish(struct timb_dma_chan *td_chan)
 	else
 		iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR);
 */
-	td_chan->chan.completed_cookie = txd->cookie;
+	dma_cookie_complete(txd);
 	td_chan->ongoing = false;
 
 	callback = txd->callback;
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index 66f8fca..8a5225b 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -411,7 +411,7 @@ txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
 	dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
 		 txd->cookie, desc);
 
-	dc->chan.completed_cookie = txd->cookie;
+	dma_cookie_complete(txd);
 	callback = txd->callback;
 	param = txd->callback_param;
 
-- 
1.7.4.4



From linux at arm.linux.org.uk  Tue Mar  6 17:35:27 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 06 Mar 2012 22:35:27 +0000
Subject: [PATCH 6/9] dmaengine: consolidate tx_status functions
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <E1S52yd-0002N1-76@rmk-PC.arm.linux.org.uk>

Now that we have the completed cookie in the dma_chan structure, we
can consolidate the tx_status functions by providing a function to set
the txstate structure and returning the DMA status.  We also provide
a separate helper to set the residue for cookies which are still in
progress.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/amba-pl08x.c    |   22 ++++------------------
 drivers/dma/at_hdmac.c      |   18 ++++++------------
 drivers/dma/coh901318.c     |   13 ++++---------
 drivers/dma/dmaengine.h     |   31 +++++++++++++++++++++++++++++++
 drivers/dma/dw_dmac.c       |   19 ++++---------------
 drivers/dma/ep93xx_dma.c    |    7 +------
 drivers/dma/fsldma.c        |   11 +++--------
 drivers/dma/imx-dma.c       |   11 +----------
 drivers/dma/intel_mid_dma.c |   19 +++----------------
 drivers/dma/ioat/dma.c      |    8 +++++---
 drivers/dma/ioat/dma.h      |   21 ---------------------
 drivers/dma/ioat/dma_v3.c   |    8 +++++---
 drivers/dma/iop-adma.c      |   16 +++-------------
 drivers/dma/mpc512x_dma.c   |    9 +++------
 drivers/dma/mv_xor.c        |   14 ++------------
 drivers/dma/pch_dma.c       |   11 ++---------
 drivers/dma/pl330.c         |   13 +------------
 drivers/dma/ppc4xx/adma.c   |   16 ++--------------
 drivers/dma/shdma.c         |   11 +----------
 drivers/dma/sirf-dma.c      |    9 +++------
 drivers/dma/ste_dma40.c     |   14 ++++----------
 drivers/dma/timb_dma.c      |   11 ++---------
 drivers/dma/txx9dmac.c      |   16 +++-------------
 23 files changed, 93 insertions(+), 235 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index f0888c1..2781a2b 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -964,31 +964,17 @@ static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
 		dma_cookie_t cookie, struct dma_tx_state *txstate)
 {
 	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
 	enum dma_status ret;
-	u32 bytesleft = 0;
 
-	last_used = plchan->chan.cookie;
-	last_complete = plchan->chan.completed_cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
-	if (ret == DMA_SUCCESS) {
-		dma_set_tx_state(txstate, last_complete, last_used, 0);
+	ret = dma_cookie_status(chan, cookie, txstate);
+	if (ret == DMA_SUCCESS)
 		return ret;
-	}
 
 	/*
 	 * This cookie not complete yet
+	 * Get number of bytes left in the active transactions and queue
 	 */
-	last_used = plchan->chan.cookie;
-	last_complete = plchan->chan.completed_cookie;
-
-	/* Get number of bytes left in the active transactions and queue */
-	bytesleft = pl08x_getbytes_chan(plchan);
-
-	dma_set_tx_state(txstate, last_complete, last_used,
-			 bytesleft);
+	dma_set_residue(txstate, pl08x_getbytes_chan(plchan));
 
 	if (plchan->state == PL08X_CHAN_PAUSED)
 		return DMA_PAUSED;
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index b282630..8a32974 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -996,26 +996,20 @@ atc_tx_status(struct dma_chan *chan,
 
 	spin_lock_irqsave(&atchan->lock, flags);
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret != DMA_SUCCESS) {
 		atc_cleanup_descriptors(atchan);
 
-		last_complete = chan->completed_cookie;
-		last_used = chan->cookie;
-
-		ret = dma_async_is_complete(cookie, last_complete, last_used);
+		ret = dma_cookie_status(chan, cookie, txstate);
 	}
 
+	last_complete = chan->completed_cookie;
+	last_used = chan->cookie;
+
 	spin_unlock_irqrestore(&atchan->lock, flags);
 
 	if (ret != DMA_SUCCESS)
-		dma_set_tx_state(txstate, last_complete, last_used,
-			atc_first_active(atchan)->len);
-	else
-		dma_set_tx_state(txstate, last_complete, last_used, 0);
+		dma_set_residue(txstate, atc_first_active(atchan)->len);
 
 	if (atc_chan_is_paused(atchan))
 		ret = DMA_PAUSED;
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 24837d7..f350517 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -1151,17 +1151,12 @@ coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 		 struct dma_tx_state *txstate)
 {
 	struct coh901318_chan *cohc = to_coh901318_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
-	int ret;
-
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
+	enum dma_status ret;
 
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
+	/* FIXME: should be conditional on ret != DMA_SUCCESS? */
+	dma_set_residue(txstate, coh901318_get_bytes_left(chan));
 
-	dma_set_tx_state(txstate, last_complete, last_used,
-			 coh901318_get_bytes_left(chan));
 	if (ret == DMA_IN_PROGRESS && cohc->stopped)
 		ret = DMA_PAUSED;
 
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
index 47e0997..1ca5e0e 100644
--- a/drivers/dma/dmaengine.h
+++ b/drivers/dma/dmaengine.h
@@ -45,4 +45,35 @@ static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
 	tx->cookie = 0;
 }
 
+/**
+ * dma_cookie_status - report cookie status
+ * @chan: dma channel
+ * @cookie: cookie we are interested in
+ * @state: dma_tx_state structure to return last/used cookies
+ *
+ * Report the status of the cookie, filling in the state structure if
+ * non-NULL.  No locking is required.
+ */
+static inline enum dma_status dma_cookie_status(struct dma_chan *chan,
+	dma_cookie_t cookie, struct dma_tx_state *state)
+{
+	dma_cookie_t used, complete;
+
+	used = chan->cookie;
+	complete = chan->completed_cookie;
+	barrier();
+	if (state) {
+		state->last = complete;
+		state->used = used;
+		state->residue = 0;
+	}
+	return dma_async_is_complete(cookie, complete, used);
+}
+
+static inline void dma_set_residue(struct dma_tx_state *state, u32 residue)
+{
+	if (state)
+		state->residue = residue;
+}
+
 #endif
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index a190c88..acc3bc0 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -937,28 +937,17 @@ dwc_tx_status(struct dma_chan *chan,
 	      struct dma_tx_state *txstate)
 {
 	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
-	dma_cookie_t		last_used;
-	dma_cookie_t		last_complete;
-	int			ret;
+	enum dma_status		ret;
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret != DMA_SUCCESS) {
 		dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 
-		last_complete = chan->completed_cookie;
-		last_used = chan->cookie;
-
-		ret = dma_async_is_complete(cookie, last_complete, last_used);
+		ret = dma_cookie_status(chan, cookie, txstate);
 	}
 
 	if (ret != DMA_SUCCESS)
-		dma_set_tx_state(txstate, last_complete, last_used,
-				dwc_first_active(dwc)->len);
-	else
-		dma_set_tx_state(txstate, last_complete, last_used, 0);
+		dma_set_residue(txstate, dwc_first_active(dwc)->len);
 
 	if (dwc->paused)
 		return DMA_PAUSED;
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index 1c56f75..142ebf0 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -1241,18 +1241,13 @@ static enum dma_status ep93xx_dma_tx_status(struct dma_chan *chan,
 					    struct dma_tx_state *state)
 {
 	struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
-	dma_cookie_t last_used, last_completed;
 	enum dma_status ret;
 	unsigned long flags;
 
 	spin_lock_irqsave(&edmac->lock, flags);
-	last_used = chan->cookie;
-	last_completed = chan->completed_cookie;
+	ret = dma_cookie_status(chan, cookie, state);
 	spin_unlock_irqrestore(&edmac->lock, flags);
 
-	ret = dma_async_is_complete(cookie, last_completed, last_used);
-	dma_set_tx_state(state, last_completed, last_used, 0);
-
 	return ret;
 }
 
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index f36e8b1..2f6c806 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -978,19 +978,14 @@ static enum dma_status fsl_tx_status(struct dma_chan *dchan,
 					struct dma_tx_state *txstate)
 {
 	struct fsldma_chan *chan = to_fsl_chan(dchan);
-	dma_cookie_t last_complete;
-	dma_cookie_t last_used;
+	enum dma_status ret;
 	unsigned long flags;
 
 	spin_lock_irqsave(&chan->desc_lock, flags);
-
-	last_complete = dchan->completed_cookie;
-	last_used = dchan->cookie;
-
+	ret = dma_cookie_status(dchan, cookie, txstate);
 	spin_unlock_irqrestore(&chan->desc_lock, flags);
 
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return ret;
 }
 
 /*----------------------------------------------------------------------------*/
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index f1226ad..ba317e6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -153,16 +153,7 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 					    dma_cookie_t cookie,
 					    struct dma_tx_state *txstate)
 {
-	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
-	dma_cookie_t last_used;
-	enum dma_status ret;
-
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, chan->completed_cookie, last_used);
-	dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
-
-	return ret;
+	return dma_cookie_status(chan, cookie, txstate);
 }
 
 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index 340509e..69ed1e6 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -477,30 +477,17 @@ static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
 						dma_cookie_t cookie,
 						struct dma_tx_state *txstate)
 {
-	dma_cookie_t		last_used;
-	dma_cookie_t		last_complete;
-	int				ret;
+	enum dma_status ret;
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret != DMA_SUCCESS) {
 		spin_lock_bh(&midc->lock);
 		midc_scan_descriptors(to_middma_device(chan->device), midc);
 		spin_unlock_bh(&midc->lock);
 
-		last_complete = chan->completed_cookie;
-		last_used = chan->cookie;
-
-		ret = dma_async_is_complete(cookie, last_complete, last_used);
+		ret = dma_cookie_status(chan, cookie, txstate);
 	}
 
-	if (txstate) {
-		txstate->last = last_complete;
-		txstate->used = last_used;
-		txstate->residue = 0;
-	}
 	return ret;
 }
 
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index b0517c8..97e100c 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -729,13 +729,15 @@ ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 {
 	struct ioat_chan_common *chan = to_chan_common(c);
 	struct ioatdma_device *device = chan->device;
+	enum dma_status ret;
 
-	if (ioat_tx_status(c, cookie, txstate) == DMA_SUCCESS)
-		return DMA_SUCCESS;
+	ret = dma_cookie_status(c, cookie, txstate);
+	if (ret == DMA_SUCCESS)
+		return ret;
 
 	device->cleanup_fn((unsigned long) c);
 
-	return ioat_tx_status(c, cookie, txstate);
+	return dma_cookie_status(c, cookie, txstate);
 }
 
 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h
index 9653b6b..c7888bc 100644
--- a/drivers/dma/ioat/dma.h
+++ b/drivers/dma/ioat/dma.h
@@ -142,27 +142,6 @@ static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
 	return container_of(chan, struct ioat_dma_chan, base);
 }
 
-/**
- * ioat_tx_status - poll the status of an ioat transaction
- * @c: channel handle
- * @cookie: transaction identifier
- * @txstate: if set, updated with the transaction state
- */
-static inline enum dma_status
-ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
-		 struct dma_tx_state *txstate)
-{
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
-
-	last_used = c->cookie;
-	last_complete = c->completed_cookie;
-
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
-	return dma_async_is_complete(cookie, last_complete, last_used);
-}
-
 /* wrapper around hardware descriptor format + additional software fields */
 
 /**
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
index 1bda46c..145eda2 100644
--- a/drivers/dma/ioat/dma_v3.c
+++ b/drivers/dma/ioat/dma_v3.c
@@ -410,13 +410,15 @@ ioat3_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 		struct dma_tx_state *txstate)
 {
 	struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
+	enum dma_status ret;
 
-	if (ioat_tx_status(c, cookie, txstate) == DMA_SUCCESS)
-		return DMA_SUCCESS;
+	ret = dma_cookie_status(c, cookie, txstate);
+	if (ret == DMA_SUCCESS)
+		return ret;
 
 	ioat3_cleanup(ioat);
 
-	return ioat_tx_status(c, cookie, txstate);
+	return dma_cookie_status(c, cookie, txstate);
 }
 
 static struct dma_async_tx_descriptor *
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index f2392d5..b1e3be08 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -894,24 +894,14 @@ static enum dma_status iop_adma_status(struct dma_chan *chan,
 					struct dma_tx_state *txstate)
 {
 	struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
-	enum dma_status ret;
-
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret == DMA_SUCCESS)
 		return ret;
 
 	iop_adma_slot_cleanup(iop_chan);
 
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return dma_cookie_status(chan, cookie, txstate);
 }
 
 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index 0253d5a..1382715 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -557,17 +557,14 @@ mpc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 	       struct dma_tx_state *txstate)
 {
 	struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
+	enum dma_status ret;
 	unsigned long flags;
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
 
 	spin_lock_irqsave(&mchan->lock, flags);
-	last_used = mchan->chan.cookie;
-	last_complete = mchan->chan.completed_cookie;
+	ret = dma_cookie_status(chan, cookie, txstate);
 	spin_unlock_irqrestore(&mchan->lock, flags);
 
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return ret;
 }
 
 /* Prepare descriptor for memory to memory copy */
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index d9810ce..486353e 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -810,26 +810,16 @@ static enum dma_status mv_xor_status(struct dma_chan *chan,
 					  struct dma_tx_state *txstate)
 {
 	struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
 	enum dma_status ret;
 
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret == DMA_SUCCESS) {
 		mv_xor_clean_completed_slots(mv_chan);
 		return ret;
 	}
 	mv_xor_slot_cleanup(mv_chan);
 
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return dma_cookie_status(chan, cookie, txstate);
 }
 
 static void mv_dump_xor_regs(struct mv_xor_chan *chan)
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index 5218e48..c30f63e 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -565,19 +565,12 @@ static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 				    struct dma_tx_state *txstate)
 {
 	struct pch_dma_chan *pd_chan = to_pd_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_completed;
-	int ret;
+	enum dma_status ret;
 
 	spin_lock_irq(&pd_chan->lock);
-	last_completed = chan->completed_cookie;
-	last_used = chan->cookie;
+	ret = dma_cookie_status(chan, cookie, txstate);
 	spin_unlock_irq(&pd_chan->lock);
 
-	ret = dma_async_is_complete(cookie, last_completed, last_used);
-
-	dma_set_tx_state(txstate, last_completed, last_used, 0);
-
 	return ret;
 }
 
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 76871b8..1993286 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -395,18 +395,7 @@ static enum dma_status
 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 		 struct dma_tx_state *txstate)
 {
-	struct dma_pl330_chan *pch = to_pchan(chan);
-	dma_cookie_t last_done, last_used;
-	int ret;
-
-	last_done = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_done, last_used);
-
-	dma_set_tx_state(txstate, last_done, last_used, 0);
-
-	return ret;
+	return dma_cookie_status(chan, cookie, txstate);
 }
 
 static void pl330_issue_pending(struct dma_chan *chan)
diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c
index 12e94dd..86239ea 100644
--- a/drivers/dma/ppc4xx/adma.c
+++ b/drivers/dma/ppc4xx/adma.c
@@ -3928,28 +3928,16 @@ static enum dma_status ppc440spe_adma_tx_status(struct dma_chan *chan,
 			dma_cookie_t cookie, struct dma_tx_state *txstate)
 {
 	struct ppc440spe_adma_chan *ppc440spe_chan;
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
 	enum dma_status ret;
 
 	ppc440spe_chan = to_ppc440spe_adma_chan(chan);
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret == DMA_SUCCESS)
 		return ret;
 
 	ppc440spe_adma_slot_cleanup(ppc440spe_chan);
 
-	last_used = chan->cookie;
-	last_complete = chan->completed_cookie;
-
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return dma_cookie_status(chan, cookie, txstate);
 }
 
 /**
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index 96d0a4f..50510ef 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -879,23 +879,14 @@ static enum dma_status sh_dmae_tx_status(struct dma_chan *chan,
 					struct dma_tx_state *txstate)
 {
 	struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
 	enum dma_status status;
 	unsigned long flags;
 
 	sh_dmae_chan_ld_cleanup(sh_chan, false);
 
-	/* First read completed cookie to avoid a skew */
-	last_complete = chan->completed_cookie;
-	rmb();
-	last_used = chan->cookie;
-	BUG_ON(last_complete < 0);
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
 	spin_lock_irqsave(&sh_chan->desc_lock, flags);
 
-	status = dma_async_is_complete(cookie, last_complete, last_used);
+	status = dma_cookie_status(chan, cookie, txstate);
 
 	/*
 	 * If we don't find cookie on the queue, it has been aborted and we have
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 7bb154a..a760d98 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -407,16 +407,13 @@ sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 {
 	struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
 	unsigned long flags;
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
+	enum dma_status ret;
 
 	spin_lock_irqsave(&schan->lock, flags);
-	last_used = schan->chan.cookie;
-	last_complete = schan->chan.completed_cookie;
+	ret = dma_cookie_status(chan, cookie, txstate);
 	spin_unlock_irqrestore(&schan->lock, flags);
 
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-	return dma_async_is_complete(cookie, last_complete, last_used);
+	return ret;
 }
 
 static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index c246375..07b82e3 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2332,25 +2332,19 @@ static enum dma_status d40_tx_status(struct dma_chan *chan,
 				     struct dma_tx_state *txstate)
 {
 	struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
-	int ret;
+	enum dma_status ret;
 
 	if (d40c->phy_chan == NULL) {
 		chan_err(d40c, "Cannot read status of unallocated channel\n");
 		return -EINVAL;
 	}
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
+	ret = dma_cookie_status(chan, cookie, txstate);
+	if (ret != DMA_SUCCESS)
+		dma_set_residue(txstate, stedma40_residue(chan));
 
 	if (d40_is_paused(d40c))
 		ret = DMA_PAUSED;
-	else
-		ret = dma_async_is_complete(cookie, last_complete, last_used);
-
-	dma_set_tx_state(txstate, last_complete, last_used,
-			 stedma40_residue(chan));
 
 	return ret;
 }
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index 1845ac9..6383abb 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -513,18 +513,11 @@ static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 {
 	struct timb_dma_chan *td_chan =
 		container_of(chan, struct timb_dma_chan, chan);
-	dma_cookie_t		last_used;
-	dma_cookie_t		last_complete;
-	int			ret;
+	enum dma_status ret;
 
 	dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
-
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
+	ret = dma_cookie_status(chan, cookie, txstate);
 
 	dev_dbg(chan2dev(chan),
 		"%s: exit, ret: %d, last_complete: %d, last_used: %d\n",
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index 8a5225b..bb7b3d9 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -959,27 +959,17 @@ txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 		   struct dma_tx_state *txstate)
 {
 	struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
-	dma_cookie_t last_used;
-	dma_cookie_t last_complete;
-	int ret;
+	enum dma_status ret;
 
-	last_complete = chan->completed_cookie;
-	last_used = chan->cookie;
-
-	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret != DMA_SUCCESS) {
 		spin_lock_bh(&dc->lock);
 		txx9dmac_scan_descriptors(dc);
 		spin_unlock_bh(&dc->lock);
 
-		last_complete = chan->completed_cookie;
-		last_used = chan->cookie;
-
-		ret = dma_async_is_complete(cookie, last_complete, last_used);
+		ret = dma_cookie_status(chan, cookie, txstate);
 	}
 
-	dma_set_tx_state(txstate, last_complete, last_used, 0);
-
 	return ret;
 }
 
-- 
1.7.4.4



From linux at arm.linux.org.uk  Tue Mar  6 17:35:47 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 06 Mar 2012 22:35:47 +0000
Subject: [PATCH 7/9] dmaengine: consolidate initialization of cookies
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <E1S52yx-0002N5-Bc@rmk-PC.arm.linux.org.uk>

Provide a common function to initialize a channels cookie values.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/amba-pl08x.c    |    3 +--
 drivers/dma/at_hdmac.c      |    4 ++--
 drivers/dma/coh901318.c     |    2 +-
 drivers/dma/dmaengine.h     |   10 ++++++++++
 drivers/dma/dw_dmac.c       |    4 ++--
 drivers/dma/ep93xx_dma.c    |    3 +--
 drivers/dma/intel_mid_dma.c |    4 ++--
 drivers/dma/ipu/ipu_idmac.c |    6 ++----
 drivers/dma/mpc512x_dma.c   |    3 +--
 drivers/dma/pch_dma.c       |    4 ++--
 drivers/dma/pl330.c         |    2 +-
 drivers/dma/sirf-dma.c      |    3 +--
 drivers/dma/ste_dma40.c     |    2 +-
 drivers/dma/timb_dma.c      |    5 ++---
 drivers/dma/txx9dmac.c      |    4 ++--
 15 files changed, 31 insertions(+), 28 deletions(-)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 2781a2b..13c4d08 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -1707,8 +1707,7 @@ static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
 			 chan->name);
 
 		chan->chan.device = dmadev;
-		chan->chan.cookie = 0;
-		chan->chan.completed_cookie = 0;
+		dma_cookie_init(&chan->chan);
 
 		spin_lock_init(&chan->lock);
 		INIT_LIST_HEAD(&chan->pend_list);
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 8a32974..5d225dd 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -1103,7 +1103,7 @@ static int atc_alloc_chan_resources(struct dma_chan *chan)
 	spin_lock_irqsave(&atchan->lock, flags);
 	atchan->descs_allocated = i;
 	list_splice(&tmp_list, &atchan->free_list);
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 	spin_unlock_irqrestore(&atchan->lock, flags);
 
 	/* channel parameters */
@@ -1303,7 +1303,7 @@ static int __init at_dma_probe(struct platform_device *pdev)
 		struct at_dma_chan	*atchan = &atdma->chan[i];
 
 		atchan->chan_common.device = &atdma->dma_common;
-		atchan->chan_common.cookie = atchan->chan_common.completed_cookie = 1;
+		dma_cookie_init(&atchan->chan_common);
 		list_add_tail(&atchan->chan_common.device_node,
 				&atdma->dma_common.channels);
 
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index f350517..187bb9e 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -915,7 +915,7 @@ static int coh901318_alloc_chan_resources(struct dma_chan *chan)
 	coh901318_config(cohc, NULL);
 
 	cohc->allocated = 1;
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 
 	spin_unlock_irqrestore(&cohc->lock, flags);
 
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
index 1ca5e0e..17f983a 100644
--- a/drivers/dma/dmaengine.h
+++ b/drivers/dma/dmaengine.h
@@ -9,6 +9,16 @@
 #include <linux/dmaengine.h>
 
 /**
+ * dma_cookie_init - initialize the cookies for a DMA channel
+ * @chan: dma channel to initialize
+ */
+static inline void dma_cookie_init(struct dma_chan *chan)
+{
+	chan->cookie = DMA_MIN_COOKIE;
+	chan->completed_cookie = DMA_MIN_COOKIE;
+}
+
+/**
  * dma_cookie_assign - assign a DMA engine cookie to the descriptor
  * @tx: descriptor needing cookie
  *
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index acc3bc0..8b4be42 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -979,7 +979,7 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
 		return -EIO;
 	}
 
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 
 	/*
 	 * NOTE: some controllers may have additional features that we
@@ -1398,7 +1398,7 @@ static int __init dw_probe(struct platform_device *pdev)
 		struct dw_dma_chan	*dwc = &dw->chan[i];
 
 		dwc->chan.device = &dw->dma;
-		dwc->chan.cookie = dwc->chan.completed_cookie = 1;
+		dma_cookie_init(&dwc->chan);
 		if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
 			list_add_tail(&dwc->chan.device_node,
 					&dw->dma.channels);
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index 142ebf0..f25e83b 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -854,8 +854,7 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
 		goto fail_clk_disable;
 
 	spin_lock_irq(&edmac->lock);
-	edmac->chan.completed_cookie = 1;
-	edmac->chan.cookie = 1;
+	dma_cookie_init(&edmac->chan);
 	ret = edmac->edma->hw_setup(edmac);
 	spin_unlock_irq(&edmac->lock);
 
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index 69ed1e6..9d82a84 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -867,7 +867,7 @@ static int intel_mid_dma_alloc_chan_resources(struct dma_chan *chan)
 		pm_runtime_put(&mid->pdev->dev);
 		return -EIO;
 	}
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 
 	spin_lock_bh(&midc->lock);
 	while (midc->descs_allocated < DESCS_PER_CHANNEL) {
@@ -1099,7 +1099,7 @@ static int mid_setup_dma(struct pci_dev *pdev)
 		struct intel_mid_dma_chan *midch = &dma->ch[i];
 
 		midch->chan.device = &dma->common;
-		midch->chan.cookie =  1;
+		dma_cookie_init(&midch->chan);
 		midch->ch_id = dma->chan_base + i;
 		pr_debug("MDMA:Init CH %d, ID %d\n", i, midch->ch_id);
 
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index bff9250..1880274 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -1504,8 +1504,7 @@ static int idmac_alloc_chan_resources(struct dma_chan *chan)
 	BUG_ON(chan->client_count > 1);
 	WARN_ON(ichan->status != IPU_CHANNEL_FREE);
 
-	chan->cookie		= 1;
-	chan->completed_cookie	= -ENXIO;
+	dma_cookie_init(chan);
 
 	ret = ipu_irq_map(chan->chan_id);
 	if (ret < 0)
@@ -1633,8 +1632,7 @@ static int __init ipu_idmac_init(struct ipu *ipu)
 		snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
 
 		dma_chan->device	= &idmac->dma;
-		dma_chan->cookie	= 1;
-		dma_chan->completed_cookie	= -ENXIO;
+		dma_cookie_init(dma_chan);
 		dma_chan->chan_id	= i;
 		list_add_tail(&dma_chan->device_node, &dma->channels);
 	}
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index 1382715..2ab0a3d 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -733,8 +733,7 @@ static int __devinit mpc_dma_probe(struct platform_device *op)
 		mchan = &mdma->channels[i];
 
 		mchan->chan.device = dma;
-		mchan->chan.cookie = 1;
-		mchan->chan.completed_cookie = mchan->chan.cookie;
+		dma_cookie_init(&mchan->chan);
 
 		INIT_LIST_HEAD(&mchan->free);
 		INIT_LIST_HEAD(&mchan->prepared);
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index c30f63e..c93bb045 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -531,7 +531,7 @@ static int pd_alloc_chan_resources(struct dma_chan *chan)
 	spin_lock_irq(&pd_chan->lock);
 	list_splice(&tmp_list, &pd_chan->free_list);
 	pd_chan->descs_allocated = i;
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 	spin_unlock_irq(&pd_chan->lock);
 
 	pdc_enable_irq(chan, 1);
@@ -912,7 +912,7 @@ static int __devinit pch_dma_probe(struct pci_dev *pdev,
 		struct pch_dma_chan *pd_chan = &pd->channels[i];
 
 		pd_chan->chan.device = &pd->dma;
-		pd_chan->chan.cookie = 1;
+		dma_cookie_init(&pd_chan->chan);
 
 		pd_chan->membase = &regs->desc[i];
 
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 1993286..49c123f 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -304,7 +304,7 @@ static int pl330_alloc_chan_resources(struct dma_chan *chan)
 
 	spin_lock_irqsave(&pch->lock, flags);
 
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 	pch->cyclic = false;
 
 	pch->pl330_chid = pl330_request_channel(&pdmac->pif);
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index a760d98..a2cde85 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -625,8 +625,7 @@ static int __devinit sirfsoc_dma_probe(struct platform_device *op)
 		schan = &sdma->channels[i];
 
 		schan->chan.device = dma;
-		schan->chan.cookie = 1;
-		schan->chan.completed_cookie = schan->chan.cookie;
+		dma_cookie_init(&schan->chan);
 
 		INIT_LIST_HEAD(&schan->free);
 		INIT_LIST_HEAD(&schan->prepared);
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 07b82e3..1ea6d02 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2172,7 +2172,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 	bool is_free_phy;
 	spin_lock_irqsave(&d40c->lock, flags);
 
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 
 	/* If no dma configuration is set use default configuration (memcpy) */
 	if (!d40c->configured) {
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index 6383abb..7805996 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -477,8 +477,7 @@ static int td_alloc_chan_resources(struct dma_chan *chan)
 	}
 
 	spin_lock_bh(&td_chan->lock);
-	chan->completed_cookie = 1;
-	chan->cookie = 1;
+	dma_cookie_init(chan);
 	spin_unlock_bh(&td_chan->lock);
 
 	return 0;
@@ -755,7 +754,7 @@ static int __devinit td_probe(struct platform_device *pdev)
 		}
 
 		td_chan->chan.device = &td->dma;
-		td_chan->chan.cookie = 1;
+		dma_cookie_init(&td_chan->chan);
 		spin_lock_init(&td_chan->lock);
 		INIT_LIST_HEAD(&td_chan->active_list);
 		INIT_LIST_HEAD(&td_chan->queue);
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index bb7b3d9..40440f9 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -1034,7 +1034,7 @@ static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
 		return -EIO;
 	}
 
-	chan->completed_cookie = chan->cookie = 1;
+	dma_cookie_init(chan);
 
 	dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
 	txx9dmac_chan_set_SMPCHN(dc);
@@ -1163,7 +1163,7 @@ static int __init txx9dmac_chan_probe(struct platform_device *pdev)
 	dc->ddev->chan[ch] = dc;
 	dc->chan.device = &dc->dma;
 	list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
-	dc->chan.cookie = dc->chan.completed_cookie = 1;
+	dma_cookie_init(&dc->chan);
 
 	if (is_dmac64(dc))
 		dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
-- 
1.7.4.4



From linux at arm.linux.org.uk  Tue Mar  6 17:36:27 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 06 Mar 2012 22:36:27 +0000
Subject: [PATCH 9/9] dmaengine: ensure all DMA engine drivers initialize
 their cookies
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <E1S52zb-0002NE-La@rmk-PC.arm.linux.org.uk>

Ensure all DMA engine drivers initialize their cookies in the same way,
so that they all behave in a similar fashion.  This means their first
issued cookie will be 2 rather than 1, and will increment to INT_MAX
before returning 1 and starting over.

In connection with this, Dan Williams said:
> Russell King wrote:
> > Secondly, some DMA engine drivers initialize the dma_chan cookie to 0,
> > others to 1. ?Is there a reason for this, or are these all buggy?
>
> I know that ioat and iop-adma expect 0 to mean "I have cleaned up this
> descriptor and it is idle", and would break if zero was an in-flight
> cookie value.  The reserved usage of zero is an driver internal
> concern, but I have no problem formalizing it as a reserved value.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/fsldma.c      |    1 +
 drivers/dma/imx-dma.c     |    1 +
 drivers/dma/imx-sdma.c    |    1 +
 drivers/dma/ioat/dma.c    |    1 +
 drivers/dma/iop-adma.c    |    1 +
 drivers/dma/mv_xor.c      |    1 +
 drivers/dma/mxs-dma.c     |    1 +
 drivers/dma/ppc4xx/adma.c |    1 +
 drivers/dma/shdma.c       |    1 +
 9 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 2f6c806..7d7384b 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -1292,6 +1292,7 @@ static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
 	chan->idle = true;
 
 	chan->common.device = &fdev->common;
+	dma_cookie_init(&chan->common);
 
 	/* find the IRQ line, if it exists in the device tree */
 	chan->irq = irq_of_parse_and_map(node, 0);
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index ba317e6..4e14f51 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -348,6 +348,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
 		spin_lock_init(&imxdmac->lock);
 
 		imxdmac->chan.device = &imxdma->dma_device;
+		dma_cookie_init(&imxdmac->chan);
 		imxdmac->channel = i;
 
 		/* Add the channel to the DMAC list */
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 4406be2..0be36a4 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1356,6 +1356,7 @@ static int __init sdma_probe(struct platform_device *pdev)
 		spin_lock_init(&sdmac->lock);
 
 		sdmac->chan.device = &sdma->dma_device;
+		dma_cookie_init(&sdmac->chan);
 		sdmac->channel = i;
 
 		/*
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index 97e100c..31493d8 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -109,6 +109,7 @@ void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *c
 	chan->reg_base = device->reg_base + (0x80 * (idx + 1));
 	spin_lock_init(&chan->cleanup_lock);
 	chan->common.device = dma;
+	dma_cookie_init(&chan->common);
 	list_add_tail(&chan->common.device_node, &dma->channels);
 	device->idx[idx] = chan;
 	init_timer(&chan->timer);
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index 4370b10..1f3a703 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -1545,6 +1545,7 @@ static int __devinit iop_adma_probe(struct platform_device *pdev)
 	INIT_LIST_HEAD(&iop_chan->chain);
 	INIT_LIST_HEAD(&iop_chan->all_slots);
 	iop_chan->common.device = dma_dev;
+	dma_cookie_init(&iop_chan->common);
 	list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
 
 	if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index 486353e..fa5d55f 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -1193,6 +1193,7 @@ static int __devinit mv_xor_probe(struct platform_device *pdev)
 	INIT_LIST_HEAD(&mv_chan->completed_slots);
 	INIT_LIST_HEAD(&mv_chan->all_slots);
 	mv_chan->common.device = dma_dev;
+	dma_cookie_init(&mv_chan->common);
 
 	list_add_tail(&mv_chan->common.device_node, &dma_dev->channels);
 
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 5f3492e..a2267f9 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -618,6 +618,7 @@ static int __init mxs_dma_probe(struct platform_device *pdev)
 
 		mxs_chan->mxs_dma = mxs_dma;
 		mxs_chan->chan.device = &mxs_dma->dma_device;
+		dma_cookie_init(&mxs_chan->chan);
 
 		tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
 			     (unsigned long) mxs_chan);
diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c
index 9752062..ced9882 100644
--- a/drivers/dma/ppc4xx/adma.c
+++ b/drivers/dma/ppc4xx/adma.c
@@ -4497,6 +4497,7 @@ static int __devinit ppc440spe_adma_probe(struct platform_device *ofdev)
 	INIT_LIST_HEAD(&chan->all_slots);
 	chan->device = adev;
 	chan->common.device = &adev->common;
+	dma_cookie_init(&chan->common);
 	list_add_tail(&chan->common.device_node, &adev->common.channels);
 	tasklet_init(&chan->irq_tasklet, ppc440spe_adma_tasklet,
 		     (unsigned long)chan);
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index 50510ef..5c40886 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -1089,6 +1089,7 @@ static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
 
 	/* reference struct dma_device */
 	new_sh_chan->common.device = &shdev->common;
+	dma_cookie_init(&new_sh_chan->common);
 
 	new_sh_chan->dev = shdev->common.dev;
 	new_sh_chan->id = id;
-- 
1.7.4.4



From linux at arm.linux.org.uk  Tue Mar  6 17:33:46 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 06 Mar 2012 22:33:46 +0000
Subject: [PATCH 1/9] dmaengine: mv_xor: remove write-only is_complete_cookie
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <E1S52x0-0002Mf-5s@rmk-PC.arm.linux.org.uk>

mv_xor's is_complete_cookie is only ever written to, but never read.
This is silly, remove the write-only structure member.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/mv_xor.c |    1 -
 drivers/dma/mv_xor.h |    1 -
 2 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index e779b43..ad7d03f 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -826,7 +826,6 @@ static enum dma_status mv_xor_status(struct dma_chan *chan,
 
 	last_used = chan->cookie;
 	last_complete = mv_chan->completed_cookie;
-	mv_chan->is_complete_cookie = cookie;
 	dma_set_tx_state(txstate, last_complete, last_used, 0);
 
 	ret = dma_async_is_complete(cookie, last_complete, last_used);
diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h
index 977b592..da04ac2 100644
--- a/drivers/dma/mv_xor.h
+++ b/drivers/dma/mv_xor.h
@@ -109,7 +109,6 @@ struct mv_xor_chan {
 #ifdef USE_TIMER
 	unsigned long		cleanup_time;
 	u32			current_on_last_cleanup;
-	dma_cookie_t		is_complete_cookie;
 #endif
 };
 
-- 
1.7.4.4



From linux at arm.linux.org.uk  Tue Mar  6 17:34:26 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 06 Mar 2012 22:34:26 +0000
Subject: [PATCH 3/9] dmaengine: add private header file
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <E1S52xe-0002Mn-Pn@rmk-PC.arm.linux.org.uk>

Add a local private header file to contain definitions and declarations
which should only be used by DMA engine drivers.

We also fix linux/dmaengine.h to use LINUX_DMAENGINE_H to guard against
multiple inclusion.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/amba-pl08x.c    |    2 ++
 drivers/dma/at_hdmac.c      |    1 +
 drivers/dma/coh901318.c     |    1 +
 drivers/dma/dmaengine.h     |   10 ++++++++++
 drivers/dma/dw_dmac.c       |    1 +
 drivers/dma/ep93xx_dma.c    |    2 ++
 drivers/dma/fsldma.c        |    1 +
 drivers/dma/imx-dma.c       |    2 ++
 drivers/dma/imx-sdma.c      |    2 ++
 drivers/dma/intel_mid_dma.c |    2 ++
 drivers/dma/ioat/dma.c      |    2 ++
 drivers/dma/ioat/dma_v2.c   |    2 ++
 drivers/dma/iop-adma.c      |    2 ++
 drivers/dma/ipu/ipu_idmac.c |    1 +
 drivers/dma/mpc512x_dma.c   |    2 ++
 drivers/dma/mv_xor.c        |    2 ++
 drivers/dma/mxs-dma.c       |    2 ++
 drivers/dma/pch_dma.c       |    2 ++
 drivers/dma/pl330.c         |    2 ++
 drivers/dma/ppc4xx/adma.c   |    1 +
 drivers/dma/shdma.c         |    2 ++
 drivers/dma/ste_dma40.c     |    1 +
 drivers/dma/timb_dma.c      |    2 ++
 drivers/dma/txx9dmac.c      |    2 ++
 include/linux/dmaengine.h   |    4 ++--
 25 files changed, 51 insertions(+), 2 deletions(-)
 create mode 100644 drivers/dma/dmaengine.h

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 2b5121f..87475cb 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -85,6 +85,8 @@
 #include <linux/slab.h>
 #include <asm/hardware/pl080.h>
 
+#include "dmaengine.h"
+
 #define DRIVER_NAME	"pl08xdmac"
 
 static struct amba_driver pl08x_amba_driver;
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 6baf5d7..ce26ba3 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -27,6 +27,7 @@
 #include <linux/of_device.h>
 
 #include "at_hdmac_regs.h"
+#include "dmaengine.h"
 
 /*
  * Glossary
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 521434b..fb0d124 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -24,6 +24,7 @@
 #include <mach/coh901318.h>
 
 #include "coh901318_lli.h"
+#include "dmaengine.h"
 
 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
 
diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
new file mode 100644
index 0000000..968570d
--- /dev/null
+++ b/drivers/dma/dmaengine.h
@@ -0,0 +1,10 @@
+/*
+ * The contents of this file are private to DMA engine drivers, and is not
+ * part of the API to be used by DMA engine users.
+ */
+#ifndef DMAENGINE_H
+#define DMAENGINE_H
+
+#include <linux/dmaengine.h>
+
+#endif
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index defe574..f10dbe1 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -22,6 +22,7 @@
 #include <linux/slab.h>
 
 #include "dw_dmac_regs.h"
+#include "dmaengine.h"
 
 /*
  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index bc45787..3260198 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -28,6 +28,8 @@
 
 #include <mach/dma.h>
 
+#include "dmaengine.h"
+
 /* M2P registers */
 #define M2P_CONTROL			0x0000
 #define M2P_CONTROL_STALLINT		BIT(0)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 9b5cb8a..2ebbe57 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -35,6 +35,7 @@
 #include <linux/dmapool.h>
 #include <linux/of_platform.h>
 
+#include "dmaengine.h"
 #include "fsldma.h"
 
 #define chan_dbg(chan, fmt, arg...)					\
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 321fc1f..51251a6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -30,6 +30,8 @@
 #include <mach/dma-v1.h>
 #include <mach/hardware.h>
 
+#include "dmaengine.h"
+
 struct imxdma_channel {
 	struct imxdma_engine		*imxdma;
 	unsigned int			channel;
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index e857904..9950ec3 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -42,6 +42,8 @@
 #include <mach/dma.h>
 #include <mach/hardware.h>
 
+#include "dmaengine.h"
+
 /* SDMA registers */
 #define SDMA_H_C0PTR		0x000
 #define SDMA_H_INTR		0x004
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index a27ae45..a907dd6 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -29,6 +29,8 @@
 #include <linux/intel_mid_dma.h>
 #include <linux/module.h>
 
+#include "dmaengine.h"
+
 #define MAX_CHAN	4 /*max ch across controllers*/
 #include "intel_mid_dma_regs.h"
 
diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c
index fab440a..dfe411b 100644
--- a/drivers/dma/ioat/dma.c
+++ b/drivers/dma/ioat/dma.c
@@ -40,6 +40,8 @@
 #include "registers.h"
 #include "hw.h"
 
+#include "../dmaengine.h"
+
 int ioat_pending_level = 4;
 module_param(ioat_pending_level, int, 0644);
 MODULE_PARM_DESC(ioat_pending_level,
diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c
index d3f0aff..6c1e675 100644
--- a/drivers/dma/ioat/dma_v2.c
+++ b/drivers/dma/ioat/dma_v2.c
@@ -41,6 +41,8 @@
 #include "registers.h"
 #include "hw.h"
 
+#include "../dmaengine.h"
+
 int ioat_ring_alloc_order = 8;
 module_param(ioat_ring_alloc_order, int, 0644);
 MODULE_PARM_DESC(ioat_ring_alloc_order,
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index d8027c2..650bf1e 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -36,6 +36,8 @@
 
 #include <mach/adma.h>
 
+#include "dmaengine.h"
+
 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
 #define to_iop_adma_device(dev) \
 	container_of(dev, struct iop_adma_device, common)
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index 9149ade..0fcff65 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -25,6 +25,7 @@
 
 #include <mach/ipu.h>
 
+#include "../dmaengine.h"
 #include "ipu_intern.h"
 
 #define FS_VF_IN_VALID	0x00000002
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index 39a5cde..c56b3fe 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -44,6 +44,8 @@
 
 #include <linux/random.h>
 
+#include "dmaengine.h"
+
 /* Number of DMA Transfer descriptors allocated per channel */
 #define MPC_DMA_DESCRIPTORS	64
 
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index c6a84da..ee61778 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -26,6 +26,8 @@
 #include <linux/platform_device.h>
 #include <linux/memory.h>
 #include <plat/mv_xor.h>
+
+#include "dmaengine.h"
 #include "mv_xor.h"
 
 static void mv_xor_issue_pending(struct dma_chan *chan);
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 3696e6e..daa84ee 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -28,6 +28,8 @@
 #include <mach/dma.h>
 #include <mach/common.h>
 
+#include "dmaengine.h"
+
 /*
  * NOTE: The term "PIO" throughout the mxs-dma implementation means
  * PIO mode of mxs apbh-dma and apbx-dma.  With this working mode,
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index 79a7185..2b3479d 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -25,6 +25,8 @@
 #include <linux/module.h>
 #include <linux/pch_dma.h>
 
+#include "dmaengine.h"
+
 #define DRV_NAME "pch-dma"
 
 #define DMA_CTL0_DISABLE		0x0
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index bdf04f1..d7b0af2 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -21,6 +21,8 @@
 #include <linux/scatterlist.h>
 #include <linux/of.h>
 
+#include "dmaengine.h"
+
 #define NR_DEFAULT_DESC	16
 
 enum desc_status {
diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c
index f878322..40082ec 100644
--- a/drivers/dma/ppc4xx/adma.c
+++ b/drivers/dma/ppc4xx/adma.c
@@ -46,6 +46,7 @@
 #include <asm/dcr.h>
 #include <asm/dcr-regs.h>
 #include "adma.h"
+#include "../dmaengine.h"
 
 enum ppc_adma_init_code {
 	PPC_ADMA_INIT_OK = 0,
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index ae84c12..c291433 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -30,6 +30,8 @@
 #include <linux/kdebug.h>
 #include <linux/spinlock.h>
 #include <linux/rculist.h>
+
+#include "dmaengine.h"
 #include "shdma.h"
 
 /* DMA descriptor control */
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index cfca2a0..156b98f 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -21,6 +21,7 @@
 
 #include <plat/ste_dma40.h>
 
+#include "dmaengine.h"
 #include "ste_dma40_ll.h"
 
 #define D40_NAME "dma40"
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index a1d1559..4b61879 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -31,6 +31,8 @@
 
 #include <linux/timb_dma.h>
 
+#include "dmaengine.h"
+
 #define DRIVER_NAME "timb-dma"
 
 /* Global DMA registers */
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index a917b67..db6d809 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -15,6 +15,8 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/scatterlist.h>
+
+#include "dmaengine.h"
 #include "txx9dmac.h"
 
 static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 41d0f92..4b17ca8 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -18,8 +18,8 @@
  * The full GNU General Public License is included in this distribution in the
  * file called COPYING.
  */
-#ifndef DMAENGINE_H
-#define DMAENGINE_H
+#ifndef LINUX_DMAENGINE_H
+#define LINUX_DMAENGINE_H
 
 #include <linux/device.h>
 #include <linux/uio.h>
-- 
1.7.4.4



From linux at arm.linux.org.uk  Tue Mar  6 17:36:07 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 06 Mar 2012 22:36:07 +0000
Subject: [PATCH 8/9] dmaengine: fix cookie handling in iop-adma.c and
 ppc4xx/adma.c
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <E1S52zH-0002N9-GU@rmk-PC.arm.linux.org.uk>

Dan Williams said:
> > Russell King wrote:
> > Firstly, we have DMA_MIN_COOKIE which has value 1 - so any cookies below
> > that aren't valid. ?That seems sane.
> >
> > We seem to have different behaviours:
> >
> > - ? ? ? cookie = c->cookie;
> > - ? ? ? cookie++;
> > - ? ? ? if (cookie < 0)
> > - ? ? ? ? ? ? ? cookie = 1;
> > - ? ? ? c->cookie = cookie;
> > - ? ? ? tx->cookie = cookie;
> >
> > c->cookie here is initialized to zero, so the first cookie given out will
> > be 1. ?This is how most DMA engine drivers implement this.
> >
> > Then we have this:
> >
> > ? ? ? ? ? ? ? ?cookie = chan->common.cookie;
> > ? ? ? ? ? ? ? ?cookie++;
> > ? ? ? ? ? ? ? ?if (cookie <= 1)
> > ? ? ? ? ? ? ? ? ? ? ? ?cookie = 2;
> >
> > ? ? ? ? ? ? ? ?/* initialize the completed cookie to be less than
> > ? ? ? ? ? ? ? ? * the most recently used cookie
> > ? ? ? ? ? ? ? ? */
> > ? ? ? ? ? ? ? ?chan->common.completed_cookie = cookie - 1;
> > ? ? ? ? ? ? ? ?chan->common.cookie = sw_desc->async_tx.cookie = cookie;
> >
> > Again, chan->common.cookie starts off at 0. ?The first cookie given out
> > will be 2, and 1 will never be used. ?There are three drivers which
> > implement it this way.
> >
> > Why is there this difference, and can these three be corrected to behave
> > the same way as the first (and therefore the assignment of cookies
> > consolidated?)
>
> Yes, they should be consolidated, and I believe they have drifted only
> because there were no good common helpers and murphy's law took over.

So lets fix this up to use the common dma_cookie_assign() helper.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 drivers/dma/iop-adma.c    |   12 ++----------
 drivers/dma/ppc4xx/adma.c |    6 +-----
 2 files changed, 3 insertions(+), 15 deletions(-)

diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index b1e3be08..4370b10 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -1622,16 +1622,12 @@ static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
 		iop_desc_set_dest_addr(grp_start, iop_chan, 0);
 		iop_desc_set_memcpy_src_addr(grp_start, 0);
 
-		cookie = iop_chan->common.cookie;
-		cookie++;
-		if (cookie <= 1)
-			cookie = 2;
+		cookie = dma_cookie_assign(&sw_desc->async_tx);
 
 		/* initialize the completed cookie to be less than
 		 * the most recently used cookie
 		 */
 		iop_chan->common.completed_cookie = cookie - 1;
-		iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
 		/* channel should not be busy */
 		BUG_ON(iop_chan_is_busy(iop_chan));
@@ -1679,16 +1675,12 @@ static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
 		iop_desc_set_xor_src_addr(grp_start, 0, 0);
 		iop_desc_set_xor_src_addr(grp_start, 1, 0);
 
-		cookie = iop_chan->common.cookie;
-		cookie++;
-		if (cookie <= 1)
-			cookie = 2;
+		cookie = dma_cookie_assign(&sw_desc->async_tx);
 
 		/* initialize the completed cookie to be less than
 		 * the most recently used cookie
 		 */
 		iop_chan->common.completed_cookie = cookie - 1;
-		iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
 		/* channel should not be busy */
 		BUG_ON(iop_chan_is_busy(iop_chan));
diff --git a/drivers/dma/ppc4xx/adma.c b/drivers/dma/ppc4xx/adma.c
index 86239ea..9752062 100644
--- a/drivers/dma/ppc4xx/adma.c
+++ b/drivers/dma/ppc4xx/adma.c
@@ -4022,16 +4022,12 @@ static void ppc440spe_chan_start_null_xor(struct ppc440spe_adma_chan *chan)
 		async_tx_ack(&sw_desc->async_tx);
 		ppc440spe_desc_init_null_xor(group_start);
 
-		cookie = chan->common.cookie;
-		cookie++;
-		if (cookie <= 1)
-			cookie = 2;
+		cookie = dma_cookie_assign(&sw_desc->async_tx);
 
 		/* initialize the completed cookie to be less than
 		 * the most recently used cookie
 		 */
 		chan->common.completed_cookie = cookie - 1;
-		chan->common.cookie = sw_desc->async_tx.cookie = cookie;
 
 		/* channel should not be busy */
 		BUG_ON(ppc440spe_chan_is_busy(chan));
-- 
1.7.4.4



From festevam at gmail.com  Tue Mar  6 17:42:12 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Tue,  6 Mar 2012 19:42:12 -0300
Subject: [PATCH] ARM: kernel/bios32: Remove unused variable
Message-ID: <1331073732-25236-1-git-send-email-festevam@gmail.com>

arch/arm/kernel/bios32.c: In function 'pcibios_fixup_bus':
arch/arm/kernel/bios32.c:302: warning: unused variable 'root'

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/kernel/bios32.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index be5d3b2..c0e71ea 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -299,7 +299,6 @@ static inline int pdev_bad_for_parity(struct pci_dev *dev)
  */
 void pcibios_fixup_bus(struct pci_bus *bus)
 {
-	struct pci_sys_data *root = bus->sysdata;
 	struct pci_dev *dev;
 	u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
 
-- 
1.7.1



From vdumpa at nvidia.com  Tue Mar  6 17:48:42 2012
From: vdumpa at nvidia.com (Krishna Reddy)
Date: Tue, 6 Mar 2012 14:48:42 -0800
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <000001ccfaea$00c16f70$02444e50$%szyprowski@samsung.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <20120305134721.0ab0d0e6de56fa30250059b1@nvidia.com>
 <000001ccfaea$00c16f70$02444e50$%szyprowski@samsung.com>
Message-ID: <401E54CE964CD94BAE1EB4A729C7087E37970113FE@HQMAIL04.nvidia.com>

> > +struct dma_iommu_mapping *
> > +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
> > +                        int order)
> > +{
> > +       unsigned int count = (size >> PAGE_SHIFT) - order;
> > +       unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);

The count calculation doesn't seem correct. "order" is log2 number and
 size >> PAGE_SHIFT is number of pages. 

If size is passed as 64*4096(256KB) and order is 6(allocation granularity is 2^6 pages=256KB),
 just 1 bit is enough to manage allocations.  So it should be 4 bytes or one long.

But the calculation gives count = 64 - 6 = 58 and 
Bitmap_size gets set to (58/(4*8)) * 4 = 8 bytes, which is incorrect.

It should be as follows.
unsigned int count = 1 << get_order(size) - order;
unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long) * BITS_PER_BYTE;

-KR

--nvpublic




From robherring2 at gmail.com  Tue Mar  6 17:49:24 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 06 Mar 2012 16:49:24 -0600
Subject: [PATCH v5 5/7] ARM: ixp4xx: use runtime ioremap hook
In-Reply-To: <20120306221152.GC15201@n2100.arm.linux.org.uk>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
 <1331070317-9598-5-git-send-email-robherring2@gmail.com>
 <20120306221152.GC15201@n2100.arm.linux.org.uk>
Message-ID: <4F569474.5090706@gmail.com>

On 03/06/2012 04:11 PM, Russell King - ARM Linux wrote:
> On Tue, Mar 06, 2012 at 03:45:15PM -0600, Rob Herring wrote:
>> diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
>> index a6329a0..c60e7b8 100644
>> --- a/arch/arm/mach-ixp4xx/common.c
>> +++ b/arch/arm/mach-ixp4xx/common.c
>> @@ -31,6 +31,7 @@
>>  
>>  #include <mach/udc.h>
>>  #include <mach/hardware.h>
>> +#include <mach/io.h>
> 
> I'll assume you have a good reason for this, inspite of there being
> no mention of it in the commit log...

To explicitly pick up is_pci_address(). Yes, it gets implicitly
included, but that could change (hopefully).

Rob


From robherring2 at gmail.com  Tue Mar  6 17:50:29 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 06 Mar 2012 16:50:29 -0600
Subject: [PATCH v5 5/7] ARM: ixp4xx: use runtime ioremap hook
In-Reply-To: <4F569474.5090706@gmail.com>
References: <alpine.LFD.2.02.1203051545200.31242@xanadu.home>
 <1331070317-9598-1-git-send-email-robherring2@gmail.com>
 <1331070317-9598-5-git-send-email-robherring2@gmail.com>
 <20120306221152.GC15201@n2100.arm.linux.org.uk> <4F569474.5090706@gmail.com>
Message-ID: <4F5694B5.30108@gmail.com>

On 03/06/2012 04:49 PM, Rob Herring wrote:
> On 03/06/2012 04:11 PM, Russell King - ARM Linux wrote:
>> On Tue, Mar 06, 2012 at 03:45:15PM -0600, Rob Herring wrote:
>>> diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
>>> index a6329a0..c60e7b8 100644
>>> --- a/arch/arm/mach-ixp4xx/common.c
>>> +++ b/arch/arm/mach-ixp4xx/common.c
>>> @@ -31,6 +31,7 @@
>>>  
>>>  #include <mach/udc.h>
>>>  #include <mach/hardware.h>
>>> +#include <mach/io.h>
>>
>> I'll assume you have a good reason for this, inspite of there being
>> no mention of it in the commit log...
> 
> To explicitly pick up is_pci_address(). Yes, it gets implicitly
> included, but that could change (hopefully).

s/is_pci_address/is_pci_memory/

Rob



From mgherzan at gmail.com  Tue Mar  6 17:55:04 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Tue,  6 Mar 2012 23:55:04 +0100
Subject: [PATCH v2] ARM: OMAP: WiLink platform data for the PandaBoard
Message-ID: <1331074504-22683-1-git-send-email-mgherzan@gmail.com>

The "uim" deamon requires sysfs entries that are filled in using
this platform data.

Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
---
 arch/arm/mach-omap2/board-omap4panda.c |   14 ++++++++++++--
 include/linux/ti_wilink_st.h           |    2 ++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index b1d74d6..339e781 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -27,6 +27,7 @@
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
+#include <linux/ti_wilink_st.h>
 #include <linux/wl12xx.h>
 
 #include <mach/hardware.h>
@@ -56,12 +57,21 @@
 #define HDMI_GPIO_HPD  63 /* Hotplug detect */
 
 /* wl127x BT, FM, GPS connectivity chip */
-static int wl1271_gpios[] = {46, -1, -1};
+static struct ti_st_plat_data wilink_platform_data = {
+	.nshutdown_gpio	= 46,
+	.dev_name	= "/dev/ttyO1",
+	.flow_cntrl	= 1,
+	.baud_rate	= 3000000,
+	.chip_enable	= NULL,
+	.suspend	= NULL,
+	.resume		= NULL,
+};
+
 static struct platform_device wl1271_device = {
 	.name	= "kim",
 	.id	= -1,
 	.dev	= {
-		.platform_data	= &wl1271_gpios,
+		.platform_data	= &wilink_platform_data,
 	},
 };
 
diff --git a/include/linux/ti_wilink_st.h b/include/linux/ti_wilink_st.h
index 2ef4385..3ca0269 100644
--- a/include/linux/ti_wilink_st.h
+++ b/include/linux/ti_wilink_st.h
@@ -25,6 +25,8 @@
 #ifndef TI_WILINK_ST_H
 #define TI_WILINK_ST_H
 
+#include <linux/skbuff.h>
+
 /**
  * enum proto-type - The protocol on WiLink chips which share a
  *	common physical interface like UART.
-- 
1.7.9.1



From linux at arm.linux.org.uk  Tue Mar  6 18:21:38 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 6 Mar 2012 23:21:38 +0000
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
Message-ID: <20120306232138.GF15201@n2100.arm.linux.org.uk>

On Wed, Feb 29, 2012 at 04:04:22PM +0100, Marek Szyprowski wrote:
> +static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
> +		    void *cpu_addr, dma_addr_t dma_addr, size_t size,
> +		    struct dma_attrs *attrs)
> +{
> +	struct arm_vmregion *c;
> +
> +	vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
> +	c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);

What protects this against other insertions/removals from the list?

> +
> +	if (c) {
> +		struct page **pages = c->priv;
> +
> +		unsigned long uaddr = vma->vm_start;
> +		unsigned long usize = vma->vm_end - vma->vm_start;
> +		int i = 0;
> +
> +		do {
> +			int ret;
> +
> +			ret = vm_insert_page(vma, uaddr, pages[i++]);
> +			if (ret) {
> +				pr_err("Remapping memory, error: %d\n", ret);
> +				return ret;
> +			}
> +
> +			uaddr += PAGE_SIZE;
> +			usize -= PAGE_SIZE;
> +		} while (usize > 0);
> +	}
> +	return 0;
> +}
> +
> +/*
> + * free a page as defined by the above mapping.
> + * Must not be called with IRQs disabled.
> + */
> +void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
> +			  dma_addr_t handle, struct dma_attrs *attrs)
> +{
> +	struct arm_vmregion *c;
> +	size = PAGE_ALIGN(size);
> +
> +	c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);

What protects this against other insertions/removals from the list?

> +	if (c) {
> +		struct page **pages = c->priv;
> +		__dma_free_remap(cpu_addr, size);
> +		__iommu_remove_mapping(dev, handle, size);
> +		__iommu_free_buffer(dev, pages, size);
> +	}
> +}
> +
> +/*
> + * Map a part of the scatter-gather list into contiguous io address space
> + */
> +static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
> +			  size_t size, dma_addr_t *handle,
> +			  enum dma_data_direction dir)
> +{
> +	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
> +	dma_addr_t iova, iova_base;
> +	int ret = 0;
> +	unsigned int count;
> +	struct scatterlist *s;
> +
> +	size = PAGE_ALIGN(size);
> +	*handle = ARM_DMA_ERROR;
> +
> +	iova_base = iova = __alloc_iova(mapping, size);
> +	if (iova == ARM_DMA_ERROR)
> +		return -ENOMEM;
> +
> +	for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s))
> +	{
> +		phys_addr_t phys = page_to_phys(sg_page(s));
> +		unsigned int len = PAGE_ALIGN(s->offset + s->length);
> +
> +		if (!arch_is_coherent())
> +			__dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
> +
> +		ret = iommu_map(mapping->domain, iova, phys, len, 0);

Dealing with phys addresses on one part and pages + offset + length
in a different part doesn't look like a good idea.  Why can't there
be some consistency?



From vdumpa at nvidia.com  Tue Mar  6 18:36:32 2012
From: vdumpa at nvidia.com (Krishna Reddy)
Date: Tue, 6 Mar 2012 15:36:32 -0800
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <20120306232138.GF15201@n2100.arm.linux.org.uk>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <20120306232138.GF15201@n2100.arm.linux.org.uk>
Message-ID: <401E54CE964CD94BAE1EB4A729C7087E3797011437@HQMAIL04.nvidia.com>

> On Wed, Feb 29, 2012 at 04:04:22PM +0100, Marek Szyprowski wrote:
> > +static int arm_iommu_mmap_attrs(struct device *dev, struct
> vm_area_struct *vma,
> > +		    void *cpu_addr, dma_addr_t dma_addr, size_t size,
> > +		    struct dma_attrs *attrs)
> > +{
> > +	struct arm_vmregion *c;
> > +
> > +	vma->vm_page_prot = __get_dma_pgprot(attrs, vma-
> >vm_page_prot);
> > +	c = arm_vmregion_find(&consistent_head, (unsigned
> long)cpu_addr);
> 
> What protects this against other insertions/removals from the list?

arm_vmregion_find uses a spin_lock internally before accessing consistent_head.
 So, it is protected.


-KR

--nvpublic




From rjw at sisk.pl  Tue Mar  6 18:53:37 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Wed, 7 Mar 2012 00:53:37 +0100
Subject: Pre-merge-window status of the arm-soc tree
In-Reply-To: <201203062054.55434.arnd@arndb.de>
References: <201203062054.55434.arnd@arndb.de>
Message-ID: <201203070053.37617.rjw@sisk.pl>

On Tuesday, March 06, 2012, Arnd Bergmann wrote:
> This is a summary of what we have today in the arm-soc tree, queued up for
> v3.4, as I expect the merge window to open soon. We currently have exactly
> 50 topic branches merged into the for-next tree, with a total of 331
> non-merge changesets. There are a few more pull requests outstanding for
> the pxa and exynos platforms.
> 
> About half the patches are cleanups and device tree conversion, which
> is a good indication that we're making progress there. There also seems
> to be an increased interest in ARMv5 and earlier platforms (pxa, at91,
> omap1, kirkwood, lpc32xx, sa1100), some of which are now moving over
> to device tree probing (at91 rapidly, in fact).
> 
> Top contributors so far are:
>      27 Nicolas Ferre
>      25 Stephen Warren
>      25 Jean-Christophe PLAGNIOL-VILLARD
>      20 Peter De Schrijver
>      19 Tony Lindgren
>      17 Ohad Ben-Cohen
>      15 Richard Zhao
>      14 Fabio Estevam
>      10 Benoit Cousson
>       9 Roland Stigge
> 
> A few things have changed since the last merge window:
> 
> * We now have staging branches, to let subarch maintainers get their
> patches into arm-soc early on, without having the actual commits
> being stable yet. Right now the only one there is the kirkwood/dt
> branch from Jason Cooper, but there can be more. These staging
> branches will not be sent to Linus during the merge window,
> the idea is that they get replaced with a final version that gets
> merged into one of the next/* topic branches.
> 
> * Russell now has a branch that contains patches from his tree that
> directly impact stuff in arm-soc. We had a lot of nasty conflicts
> the last time around, which resulted in some of the patches from
> arm-soc not making it in during the merge window. Pulling the
> rmk/for-armsoc branch into arm-soc hopefully lets us avoid this
> situation in the future because we will fix the conflicts much
> earlier.
> 
> * I have taken the rpmsg branch from Ohad Ben-Cohen into arm-soc.
> While this is not strictly what arm-soc is for, a lot of us are
> waiting for the branch to get in, and we hope that Linus will take
> it from us, while he was cautious the last time when Ohad was sending
> it as a new subsystem himself. Merging new subsystems through arm-soc
> should not become the norm, but we can do it when it's really needed.
> 
> * There is some renewed interest in fixing 'make randconfig'. I
> worked on this quite a bit last year but then didn't have the
> energy to get all the patches integrated besides doing the
> amr-soc maintainance. Russell has gotten more serious about it now,
> and a few other people are helping out getting my original patches
> integrated. If all goes well, we will soon get to the point where
> we can use randconfig builds for automated regression testing and
> just refuse to take pull requests into arm-soc if they break builds.
> 
> We are mostly converging on a set of topic branches that work for
> all platforms, right now we have:
> 
>   fixes				bug fixes for 3.3
>   next/fixes-non-critical       bug fixes for 3.4
>   next/maintainers              updates to MAINTAINERS file
>   next/cleanup                  any global cleanups
>   next/soc                      soc-wide changes
>   next/drivers                  driver related changes
>   next/cleanup2                 cleanups depending on the former
>   next/dt                       device-tree related changes
>   next/boards                   board-specific changes
>   next/soc2                     soc-wide changes with other dependencies
>   next/rpmsg                    remoteproc and rpmsg
>   staging/*			anything that is not quite ready
> 
> We can always add more if needed, just be careful not to introduce
> any circular dependencies. E.g. today the next/dt branch depends on
> patches in the next/drivers branch, so if you want to have other
> conflicting patches in both branches, make sure that we can resolve
> the branches in a way that lets the driver stuff come first. You will
> find a list of the dependencies in the linux-next tree or in
> arm-soc/for-next in the arch/arm/arm-soc-for-next-contents.txt file.
> 
> The overall changes today are
> $ git diff for-next --dirstat=1                                                                                                                                                            
>    1.4% Documentation/devicetree/bindings/arm/                                                                                                                                                                     
>    4.1% Documentation/                                                                                                                                                                                             
>    6.2% arch/arm/boot/dts/                                                                                                                                                                                         
>    7.6% arch/arm/mach-at91/include/mach/                                                                                                                                                                           
>   15.6% arch/arm/mach-at91/                                                                                                                                                                                        
>    1.9% arch/arm/mach-davinci/                                                                                                                                                                                     
>    5.6% arch/arm/mach-imx/                                                                                                                                                                                         
>    2.2% arch/arm/mach-mxs/                                                                                                                                                                                         
>    1.3% arch/arm/mach-omap1/                                                                                                                                                                                       
>    3.0% arch/arm/mach-omap2/                                                                                                                                                                                       
>    1.0% arch/arm/mach-tegra/include/mach/                                                                                                                                                                          
>   17.0% arch/arm/mach-tegra/                                                                                                                                                                                       
>    3.9% arch/arm/mach-ux500/                                                                                                                                                                                       
>    2.2% arch/arm/mach-vexpress/                                                                                                                                                                                    
>    1.9% arch/arm/plat-omap/include/plat/                                                                                                                                                                           
>    5.4% arch/arm/                                                                                                                                                                                                  
>    8.0% drivers/remoteproc/                                                                                                                                                                                        
>    3.6% drivers/rpmsg/                                                                                                                                                                                             
>    1.2% drivers/rtc/                                                                                                                                                                                               
>    2.8% drivers/
>    2.7% include/linux/
> 
> Notably absent here are still mach-msm and mach-shmobile and some
> platforms have more patches pending.

I'm going to have a pull request for mach-shmobile ready, hopefully on
Thursday.

Thanks,
Rafael


From khilman at ti.com  Tue Mar  6 18:55:47 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 06 Mar 2012 15:55:47 -0800
Subject: [PATCH] gpio/omap: Fix section warning for omap_mpuio_alloc_gc()
In-Reply-To: <20120306212605.GY12083@atomide.com> (Tony Lindgren's message of
 "Tue, 6 Mar 2012 13:26:06 -0800")
References: <20120306212605.GY12083@atomide.com>
Message-ID: <87pqcpb7y4.fsf@ti.com>

Tony Lindgren <tony at atomide.com> writes:

> From: Tony Lindgren <tony at atomide.com>
> Date: Mon, 5 Mar 2012 15:32:38 -0800
> Subject: [PATCH] gpio/omap: Fix section warning for omap_mpuio_alloc_gc()
>
> Make omap_mpuio_alloc_gc() __devinit as omap_gpio_chip_init()
> is __devinit. Otherwise we get:
>
> WARNING: vmlinux.o(.devinit.text+0xa10): Section mismatch in reference
> from the function omap_gpio_chip_init() to the function .init.text:omap_mpuio_alloc_gc()
> The function __devinit omap_gpio_chip_init() references
> a function __init omap_mpuio_alloc_gc().
> If omap_mpuio_alloc_gc is only used by omap_gpio_chip_init then
> annotate omap_mpuio_alloc_gc with a matching annotation.
>
> Signed-off-by: Tony Lindgren <tony at atomide.com>

Acked-by: Kevin Hilman <khilman at ti.com>



> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -1081,7 +1081,7 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
>  	}
>  }
>  
> -static __init void
> +static __devinit void
>  omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
>  		    unsigned int num)
>  {
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From khilman at ti.com  Tue Mar  6 19:05:27 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 06 Mar 2012 16:05:27 -0800
Subject: [PATCH V2] OMAP3+: PM: VP: fix integer truncation error
In-Reply-To: <1331059872-29011-1-git-send-email-nm@ti.com> (Nishanth Menon's
 message of "Tue, 6 Mar 2012 12:51:12 -0600")
References: <1331059872-29011-1-git-send-email-nm@ti.com>
Message-ID: <87hay1b7i0.fsf@ti.com>

Nishanth Menon <nm at ti.com> writes:

> From: Yuan Jiangli <jlyuan at motorola.com>
>
> commit 2f34ce81b8c05c900e45bd88595cc154f7bb5957
> (OMAP3: PM: Adding voltage driver support.)
> introduced runtime computation of waittime to handle all potential
> sys clocks available.
>
> In the voltage processor, the SPMSUpdateWait is calculated based on
> the slew rate and the voltage step (SMPSUpdateWait = slew rate *
> Voltage Step). After the voltage processor receives the SMPS_Ack
> signal, the Voltage Controller will wait for SMPSUpdateWait clock
> cycles for the voltage to settle to the new value. For all
> practical purposes, the waittime parameter is the OMAP hardware
> translation of what the slew rate on the PMIC is.
>
> As an example, with TPS62361 on OMAP4460,
> step_size = 10000
> slew_rate = 32000
> sys_clk_rate = 38400
>
> Our current computation results in the following:
>  = ((step_size / slew_rate) * sys_clk_rate) / 1000
>  = ((10000 / 32000) * 38400 / 1000
>  = 0
>
> Fix the same using DIV_ROUND_UP as an extra wait clock cycle
> is better than lesser clock cycle. For the above example, this
> translates to:
>  = (10000 * 38400) / (1000 * 32000)
>  = 12
>
> Acked-by: Jon Hunter <jon-hunter at ti.com>
> [nm at ti.com: slightly better implementation]
> Signed-off-by: Nishanth Menon <nm at ti.com>
> Signed-off-by: Yuan Jiangli <jlyuan at motorola.com>

Acked-by: Kevin Hilman <khilman at ti.com>

Tony, I don't have any more PM fixes for this cycle, so feel free to add
this to fixes-non-critical-part2.

This is an important fix, but since we're not doing active voltage
scaling in mainline today, I don't think it's 3.3 material.

Kevin

> ---
>  arch/arm/mach-omap2/vp.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
> index 0df8882..f95c1ba 100644
> --- a/arch/arm/mach-omap2/vp.c
> +++ b/arch/arm/mach-omap2/vp.c
> @@ -61,8 +61,8 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
>  	vddmin = voltdm->pmic->vp_vddmin;
>  	vddmax = voltdm->pmic->vp_vddmax;
>  
> -	waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
> -		    sys_clk_rate) / 1000;
> +	waittime = DIV_ROUND_UP(voltdm->pmic->step_size * sys_clk_rate,
> +				1000 * voltdm->pmic->slew_rate);
>  	vstepmin = voltdm->pmic->vp_vstepmin;
>  	vstepmax = voltdm->pmic->vp_vstepmax;


From paul.gortmaker at windriver.com  Tue Mar  6 19:10:23 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Tue, 6 Mar 2012 19:10:23 -0500
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <1330989122-6323-1-git-send-email-paul.gortmaker@windriver.com>
References: <1330989122-6323-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>

On Mon, Mar 5, 2012 at 6:12 PM, Paul Gortmaker
<paul.gortmaker at windriver.com> wrote:

[...]

> -REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps");
> -REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
> -REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
> -REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
> -REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
> -REGULATOR_CONSUMER(buck2, NULL, "vcc_core");
> +REGULATOR_CONSUMER(ldo3, "vcc gps");
> +REGULATOR_CONSUMER(ldo5, "vcc cam");
> +REGULATOR_CONSUMER(ldo10, "vcc sdio");
> +REGULATOR_CONSUMER(ldo12, "vcc usb");
> +REGULATOR_CONSUMER(ldo19, "vcc gprs");
> +REGULATOR_CONSUMER(buck2, "vcc_core");

Based on today's discussions, I'm no longer convinced the above
is right.  If I understand correctly, for the case of say the top one:

      em_x270_gps_userspace_consumer

I need to go find that struct, determine that it has a .name entry like:

        .name           = "reg-userspace-consumer",

and then use (for each case) something like:

      REGULATOR_SUPPLY("vcc gps", "reg-userspace-consumer")

The above wrapper for REGULATOR_CONSUMER would have
to be changed to either use or inline the REGULATOR_SUPPLY.

Let me know if I'm on the right track here.  This code is completely
foreign to me.   As such, the naming in the magician_defconfig
patch is also probably needing rework (i.e. it needs the corresponding
value for .name, and not the name of the parent struct itself.)

THanks,
Paul.
--

>
> ?#define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) ? ? ? ? ? ? ?\
> ? ? ? ?static struct regulator_init_data _ldo##_data = { ? ? ? ? ? ? ? \
> --
> 1.7.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-next" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html


From pullip.cho at samsung.com  Tue Mar  6 19:10:42 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Wed, 7 Mar 2012 09:10:42 +0900
Subject: [PATCH v10 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
In-Reply-To: <CAH9JG2Uvc27UMcsy_Apqo+Td_td_18C6i3vvC8aroBse2=+53w@mail.gmail.com>
References: <002101ccfb73$8684c240$938e46c0$%cho@samsung.com>
 <CAH9JG2Uvc27UMcsy_Apqo+Td_td_18C6i3vvC8aroBse2=+53w@mail.gmail.com>
Message-ID: <CAHQjnOP_mEck35PwhDd7v=MKc+ONFRFxa7i=ro0iMxWy-fuFNw@mail.gmail.com>

On Tue, Mar 6, 2012 at 7:03 PM, Kyungmin Park <kyungmin.park at samsung.com> wrote:
>>
>> -#define S5P_SYSMMU_TOTAL_IPNUM ? ? ? ? ? ? ? EXYNOS4_SYSMMU_TOTAL_IPNUM
>> +#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
>> +
>> +#define SYSMMU_CLOCK_NAME "sysmmu"
>> +#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
> What's the meaning of "mc"?
It stands for multi clock gating source.
ISP block has a lot of System MMUs and I merged them in a single
platform device to control them easier. However it is required to access
2 control registers to gating  their clocks. "sysmmu_mc" is prepared for the
case that requires 2 clock descriptors for clock gating.

>> +
>> +#ifdef CONFIG_EXYNOS_DEV_SYSMMU
>> +#include <linux/device.h>
>> +struct platform_device;
>> +
>> +#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
>> +
>> +extern struct platform_device SYSMMU_PLATDEV(mfc_l);
>> +extern struct platform_device SYSMMU_PLATDEV(mfc_r);
>> +extern struct platform_device SYSMMU_PLATDEV(tv);
>> +extern struct platform_device SYSMMU_PLATDEV(jpeg);
>> +extern struct platform_device SYSMMU_PLATDEV(rot);
> Where's the fimc platform_device?
>
> I think you only tested it with exynos5.

True. I am sorry that I have missed to define it externally.
Thank you.

Cho KyongHo.


From tony at atomide.com  Tue Mar  6 19:13:11 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 6 Mar 2012 16:13:11 -0800
Subject: [PATCH V2] OMAP3+: PM: VP: fix integer truncation error
In-Reply-To: <87hay1b7i0.fsf@ti.com>
References: <1331059872-29011-1-git-send-email-nm@ti.com>
 <87hay1b7i0.fsf@ti.com>
Message-ID: <20120307001311.GB12083@atomide.com>

* Kevin Hilman <khilman at ti.com> [120306 15:33]:
> Nishanth Menon <nm at ti.com> writes:
> 
> > From: Yuan Jiangli <jlyuan at motorola.com>
> >
> > commit 2f34ce81b8c05c900e45bd88595cc154f7bb5957
> > (OMAP3: PM: Adding voltage driver support.)
> > introduced runtime computation of waittime to handle all potential
> > sys clocks available.
> >
> > In the voltage processor, the SPMSUpdateWait is calculated based on
> > the slew rate and the voltage step (SMPSUpdateWait = slew rate *
> > Voltage Step). After the voltage processor receives the SMPS_Ack
> > signal, the Voltage Controller will wait for SMPSUpdateWait clock
> > cycles for the voltage to settle to the new value. For all
> > practical purposes, the waittime parameter is the OMAP hardware
> > translation of what the slew rate on the PMIC is.
> >
> > As an example, with TPS62361 on OMAP4460,
> > step_size = 10000
> > slew_rate = 32000
> > sys_clk_rate = 38400
> >
> > Our current computation results in the following:
> >  = ((step_size / slew_rate) * sys_clk_rate) / 1000
> >  = ((10000 / 32000) * 38400 / 1000
> >  = 0
> >
> > Fix the same using DIV_ROUND_UP as an extra wait clock cycle
> > is better than lesser clock cycle. For the above example, this
> > translates to:
> >  = (10000 * 38400) / (1000 * 32000)
> >  = 12
> >
> > Acked-by: Jon Hunter <jon-hunter at ti.com>
> > [nm at ti.com: slightly better implementation]
> > Signed-off-by: Nishanth Menon <nm at ti.com>
> > Signed-off-by: Yuan Jiangli <jlyuan at motorola.com>
> 
> Acked-by: Kevin Hilman <khilman at ti.com>
> 
> Tony, I don't have any more PM fixes for this cycle, so feel free to add
> this to fixes-non-critical-part2.
> 
> This is an important fix, but since we're not doing active voltage
> scaling in mainline today, I don't think it's 3.3 material.

OK, adding.

Thanks,

Tony


From khilman at ti.com  Tue Mar  6 19:15:47 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 06 Mar 2012 16:15:47 -0800
Subject: [GIT PULL] ARM: OMAP: UART: cleanups for v3.4
Message-ID: <877gyxb70s.fsf@ti.com>

Tony,

Here are a couple minor cleanups in the serial init code for v3.4.

Kevin


The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:

  Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/cleanup/uart

for you to fetch changes up to 7cb034f8179dfc2889c1f2341566ee68f648a324:

  ARM: OMAP2+: remove some orphan function declarations. (2012-02-21 11:13:11 -0800)

----------------------------------------------------------------
NeilBrown (2):
      ARM: OMAP2+: UART: remove unused fields in omap_uart_state.
      ARM: OMAP2+: remove some orphan function declarations.

 arch/arm/mach-omap2/pm.h                 |    1 -
 arch/arm/mach-omap2/serial.c             |    4 ----
 arch/arm/plat-omap/include/plat/serial.h |    1 -
 3 files changed, 6 deletions(-)


From swarren at wwwdotorg.org  Tue Mar  6 19:30:36 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue,  6 Mar 2012 17:30:36 -0700
Subject: [PATCH 1/3] Kbuild: centralize MKIMAGE and cmd_uimage definitions
Message-ID: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>

All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
to avoid duplication.

All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
parameterized version in Makefile.lib to avoid duplication.

The centralized cmd_uimage definition will allow the future introduction
of a centralized Kconfig option to make cmd_uimage use -T kernel_noload
rather than -T kernel.

Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
---
NOTE: I have not tested this patch in any way at all for architectures
other than ARM.

 arch/arm/boot/Makefile          |   23 +++++++++--------------
 arch/avr32/boot/images/Makefile |    9 +++------
 arch/blackfin/boot/Makefile     |   19 ++++++++-----------
 arch/microblaze/boot/Makefile   |   10 +++-------
 arch/sh/boot/Makefile           |    8 ++------
 arch/sparc/boot/Makefile        |    9 +++------
 arch/unicore32/boot/Makefile    |   12 ++----------
 scripts/Makefile.lib            |   24 ++++++++++++++++++++++++
 8 files changed, 54 insertions(+), 60 deletions(-)

diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index fc871e7..c877087 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -11,8 +11,6 @@
 # Copyright (C) 1995-2002 Russell King
 #
 
-MKIMAGE         := $(srctree)/scripts/mkuboot.sh
-
 ifneq ($(MACHINE),)
 include $(srctree)/$(MACHINE)/Makefile.boot
 endif
@@ -69,22 +67,19 @@ $(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
 
 clean-files := *.dtb
 
-quiet_cmd_uimage = UIMAGE  $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
-		   -C none -a $(LOADADDR) -e $(STARTADDR) \
-		   -n 'Linux-$(KERNELRELEASE)' -d $< $@
-
-ifeq ($(CONFIG_ZBOOT_ROM),y)
-$(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
+ifneq ($(LOADADDR),)
+  UIMAGE_LOADADDR=$(LOADADDR)
 else
-$(obj)/uImage: LOADADDR=$(ZRELADDR)
+  ifeq ($(CONFIG_ZBOOT_ROM),y)
+    UIMAGE_LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
+  else
+    UIMAGE_LOADADDR=$(ZRELADDR)
+  endif
 endif
 
-$(obj)/uImage: STARTADDR=$(LOADADDR)
-
 check_for_multiple_loadaddr = \
-if [ $(words $(LOADADDR)) -gt 1 ]; then \
-	echo 'multiple load addresses: $(LOADADDR)'; \
+if [ $(words $(UIMAGE_LOADADDR)) -gt 1 ]; then \
+	echo 'multiple load addresses: $(UIMAGE_LOADADDR)'; \
 	echo 'This is incompatible with uImages'; \
 	echo 'Specify LOADADDR on the commandline to build an uImage'; \
 	false; \
diff --git a/arch/avr32/boot/images/Makefile b/arch/avr32/boot/images/Makefile
index 1848bf0..c9d8ab5 100644
--- a/arch/avr32/boot/images/Makefile
+++ b/arch/avr32/boot/images/Makefile
@@ -6,8 +6,6 @@
 # for more details.
 #
 
-MKIMAGE		:= $(srctree)/scripts/mkuboot.sh
-
 extra-y		:= vmlinux.bin vmlinux.gz
 
 OBJCOPYFLAGS_vmlinux.bin := -O binary -R .note.gnu.build-id
@@ -17,10 +15,9 @@ $(obj)/vmlinux.bin: vmlinux FORCE
 $(obj)/vmlinux.gz: $(obj)/vmlinux.bin FORCE
 	$(call if_changed,gzip)
 
-quiet_cmd_uimage = UIMAGE $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A avr32 -O linux -T kernel	\
-		-C gzip -a $(CONFIG_LOAD_ADDRESS) -e $(CONFIG_ENTRY_ADDRESS)	\
-		-n 'Linux-$(KERNELRELEASE)' -d $< $@
+UIMAGE_LOADADDR = $(CONFIG_LOAD_ADDRESS
+UIMAGE_ENTRYADDR = $(CONFIG_ENTRY_ADDRESS)
+UIMAGE_COMPRESSION = gzip
 
 targets += uImage uImage.srec
 $(obj)/uImage: $(obj)/vmlinux.gz
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index 0a49279..6d2690a 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -6,20 +6,17 @@
 # for more details.
 #
 
-MKIMAGE := $(srctree)/scripts/mkuboot.sh
-
 targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip
 extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
 
-UIMAGE_OPTS-y :=
-UIMAGE_OPTS-$(CONFIG_RAMKERNEL) += -a $(CONFIG_BOOT_LOAD)
-UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -a $(CONFIG_ROM_BASE) -x
-
-quiet_cmd_uimage = UIMAGE  $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
-                   -C $(2) -n '$(CPU_REV)-$(KERNELRELEASE)' \
-                   -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
-                   $(UIMAGE_OPTS-y) -d $< $@
+ifeq ($(CONFIG_RAMKERNEL),y)
+UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
+else # CONFIG_ROMKERNEL must be set
+UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
+endif
+UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}')
+UIMAGE_NAME = '$(CPU_REV)-$(KERNELRELEASE)'
+UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -x
 
 $(obj)/vmlinux.bin: vmlinux FORCE
 	$(call if_changed,objcopy)
diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile
index 0c796cf..ca76ecd 100644
--- a/arch/microblaze/boot/Makefile
+++ b/arch/microblaze/boot/Makefile
@@ -2,8 +2,6 @@
 # arch/microblaze/boot/Makefile
 #
 
-MKIMAGE := $(srctree)/scripts/mkuboot.sh
-
 obj-y += linked_dtb.o
 
 targets := linux.bin linux.bin.gz simpleImage.%
@@ -35,11 +33,9 @@ quiet_cmd_strip = STRIP   $@
 	cmd_strip = $(STRIP) -K microblaze_start -K _end -K __log_buf \
 				-K _fdt_start vmlinux -o $@
 
-quiet_cmd_uimage = UIMAGE  $@.ub
-	cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A microblaze -O linux -T kernel \
-		-C none -n 'Linux-$(KERNELRELEASE)' \
-		-a $(CONFIG_KERNEL_BASE_ADDR) -e $(CONFIG_KERNEL_BASE_ADDR) \
-		-d $@ $@.ub
+UIMAGE_IN = $@
+UIMAGE_OUT = $@.ub
+UIMAGE_LOADADDR = $(CONFIG_KERNEL_BASE_ADDR)
 
 $(obj)/simpleImage.%: vmlinux FORCE
 	$(call if_changed,cp,.unstrip)
diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
index e4ea31a..58592df 100644
--- a/arch/sh/boot/Makefile
+++ b/arch/sh/boot/Makefile
@@ -8,8 +8,6 @@
 # Copyright (C) 1999 Stuart Menefy
 #
 
-MKIMAGE := $(srctree)/scripts/mkuboot.sh
-
 #
 # Assign safe dummy values if these variables are not defined,
 # in order to suppress error message.
@@ -61,10 +59,8 @@ KERNEL_ENTRY	:= $(shell /bin/bash -c 'printf "0x%08x" \
 			$(KERNEL_MEMORY) + \
 			$(CONFIG_ZERO_PAGE_OFFSET) + $(CONFIG_ENTRY_OFFSET)]')
 
-quiet_cmd_uimage = UIMAGE  $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sh -O linux -T kernel \
-		   -C $(2) -a $(KERNEL_LOAD) -e $(KERNEL_ENTRY) \
-		   -n 'Linux-$(KERNELRELEASE)' -d $< $@
+UIMAGE_LOADADDR = $(KERNEL_LOAD)
+UIMAGE_ENTRYADDR = $(KERNEL_ENTRY)
 
 $(obj)/vmlinux.bin: vmlinux FORCE
 	$(call if_changed,objcopy)
diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile
index 9205416..19e1bc7 100644
--- a/arch/sparc/boot/Makefile
+++ b/arch/sparc/boot/Makefile
@@ -5,7 +5,6 @@
 
 ROOT_IMG	:= /usr/src/root.img
 ELFTOAOUT	:= elftoaout
-MKIMAGE 	:= $(srctree)/scripts/mkuboot.sh
 
 hostprogs-y	:= piggyback btfixupprep
 targets		:= tftpboot.img btfix.o btfix.S image zImage vmlinux.aout
@@ -92,11 +91,9 @@ $(obj)/image.bin: $(obj)/image FORCE
 $(obj)/image.gz: $(obj)/image.bin
 	$(call if_changed,gzip)
 
-quiet_cmd_uimage = UIMAGE  $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sparc -O linux -T kernel \
-               -C gzip -a $(CONFIG_UBOOT_LOAD_ADDR) \
-	       -e $(CONFIG_UBOOT_ENTRY_ADDR) -n 'Linux-$(KERNELRELEASE)' \
-               -d $< $@
+UIMAGE_LOADADDR = $(CONFIG_UBOOT_LOAD_ADDR
+UIMAGE_ENTRYADDR = $(CONFIG_UBOOT_ENTRY_ADDR)
+UIMAGE_COMPRESSION = gzip
 
 quiet_cmd_uimage.o = UIMAGE.O $@
       cmd_uimage.o = $(LD) -Tdata $(CONFIG_UBOOT_FLASH_ADDR) \
diff --git a/arch/unicore32/boot/Makefile b/arch/unicore32/boot/Makefile
index 79e5f88..ec7fb70 100644
--- a/arch/unicore32/boot/Makefile
+++ b/arch/unicore32/boot/Makefile
@@ -11,8 +11,6 @@
 # Copyright (C) 2001~2010 GUAN Xue-tao
 #
 
-MKIMAGE := $(srctree)/scripts/mkuboot.sh
-
 targets := Image zImage uImage
 
 $(obj)/Image: vmlinux FORCE
@@ -26,14 +24,8 @@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE
 	$(call if_changed,objcopy)
 	@echo '  Kernel: $@ is ready'
 
-quiet_cmd_uimage = UIMAGE  $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A unicore -O linux -T kernel \
-		   -C none -a $(LOADADDR) -e $(STARTADDR) \
-		   -n 'Linux-$(KERNELRELEASE)' -d $< $@
-
-$(obj)/uImage: LOADADDR=0x0
-
-$(obj)/uImage: STARTADDR=$(LOADADDR)
+UIMAGE_ARCH = unicore
+UIMAGE_LOADADDR = 0x0
 
 $(obj)/uImage: $(obj)/zImage FORCE
 	$(call if_changed,uimage)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 00c368c..7b0be18 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -304,6 +304,30 @@ cmd_lzo = (cat $(filter-out FORCE,$^) | \
 	lzop -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
 	(rm -f $@ ; false)
 
+# U-Boot mkimage
+# ---------------------------------------------------------------------------
+
+MKIMAGE := $(srctree)/scripts/mkuboot.sh
+
+# SRCARCH just happens to match slightly more than ARCH (on sparc), so reduces
+# the number of overrides in arch makefiles
+UIMAGE_ARCH = $(SRCARCH)
+UIMAGE_COMPRESSION = $(if $(2),$(2),none)
+UIMAGE_OPTS-y =
+UIMAGE_TYPE = kernel
+UIMAGE_LOADADDR=arch_must_set_this
+UIMAGE_ENTRYADDR=$(UIMAGE_LOADADDR)
+UIMAGE_NAME = 'Linux-$(KERNELRELEASE)'
+UIMAGE_IN = $<
+UIMAGE_OUT = $@
+
+quiet_cmd_uimage = UIMAGE  $(UIMAGE_OUT)
+      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(UIMAGE_ARCH) -O linux \
+			-C $(UIMAGE_COMPRESSION) $(UIMAGE_OPTS-y) \
+			-T $(UIMAGE_TYPE) \
+			-a $(UIMAGE_LOADADDR) -e $(UIMAGE_ENTRYADDR) \
+			-n $(UIMAGE_NAME) -d $(UIMAGE_IN) $(UIMAGE_OUT)
+
 # XZ
 # ---------------------------------------------------------------------------
 # Use xzkern to compress the kernel image and xzmisc to compress other things.
-- 
1.7.0.4



From swarren at wwwdotorg.org  Tue Mar  6 19:30:37 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue,  6 Mar 2012 17:30:37 -0700
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>

This allows the user to use U-Boot's mkimage's -T kernel_noload option
if their arch Kconfig allows it, and they desire.

Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
---
The next patch enables this new CONFIG_ALLOW_ option for ARM. I assume
that some other architectures will also be able to enable it, but I'm
not familiar enough with any to know which.

 init/Kconfig         |   15 +++++++++++++++
 scripts/Makefile.lib |   15 ++++++++++++---
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/init/Kconfig b/init/Kconfig
index 6cfd71d..2035562 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -203,6 +203,21 @@ config KERNEL_LZO
 
 endchoice
 
+config ALLOW_UIMAGE_KERNEL_NOLOAD
+	bool
+
+config UIMAGE_KERNEL_NOLOAD
+	bool "Use mkimage's -T kernel_noload instead of -T kernel"
+	depends on ALLOW_UIMAGE_KERNEL_NOLOAD
+	help
+	  uImage files of type "kernel" embed an absolute load and entry point
+	  address. If the uImage is loaded to a different address, then the
+	  image must be copied the uImage file to the specified load address.
+	  This copy is a waste of time if the uImage is in fact completely
+	  relocatable. If your kernel and bootloader support it, you can build
+	  a "kernel_noload" uImage rather than a "kernel" uImage, which
+	  prevents any such copying. If unsure say N.
+
 config DEFAULT_HOSTNAME
 	string "Default hostname"
 	default "(none)"
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 7b0be18..d9c1c87 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -314,9 +314,18 @@ MKIMAGE := $(srctree)/scripts/mkuboot.sh
 UIMAGE_ARCH = $(SRCARCH)
 UIMAGE_COMPRESSION = $(if $(2),$(2),none)
 UIMAGE_OPTS-y =
-UIMAGE_TYPE = kernel
-UIMAGE_LOADADDR=arch_must_set_this
-UIMAGE_ENTRYADDR=$(UIMAGE_LOADADDR)
+ifeq ($(CONFIG_UIMAGE_KERNEL_NOLOAD),y)
+  UIMAGE_TYPE = kernel_noload
+  # Unused by bootloader:
+  UIMAGE_LOADADDR=0
+  # Entry point relative to actual load address:
+  UIMAGE_ENTRYADDR=0
+else
+  UIMAGE_TYPE = kernel
+  # Absolute addresses:
+  UIMAGE_LOADADDR=arch_must_set_this
+  UIMAGE_ENTRYADDR=$(UIMAGE_LOADADDR)
+endif
 UIMAGE_NAME = 'Linux-$(KERNELRELEASE)'
 UIMAGE_IN = $<
 UIMAGE_OUT = $@
-- 
1.7.0.4



From swarren at wwwdotorg.org  Tue Mar  6 19:30:38 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue,  6 Mar 2012 17:30:38 -0700
Subject: [PATCH 3/3] ARM: Allow the user to enable UIMAGE_KERNEL_NOLOAD
In-Reply-To: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1331080238-1524-3-git-send-email-swarren@wwwdotorg.org>

When AUTO_ZRELADDR is enabled, ARM zImages are relocatable, and hence
the user may use mkimage's -T kernel_noload option if their bootloader
supports it.

Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
---
 arch/arm/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4040796..5459b2e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2055,6 +2055,7 @@ config CRASH_DUMP
 
 config AUTO_ZRELADDR
 	bool "Auto calculation of the decompressed kernel image address"
+	select ALLOW_UIMAGE_KERNEL_NOLOAD
 	depends on !ZBOOT_ROM && !ARCH_U300
 	help
 	  ZRELADDR is the physical address where the decompressed kernel
-- 
1.7.0.4



From khilman at ti.com  Tue Mar  6 19:39:31 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue,  6 Mar 2012 16:39:31 -0800
Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulator for first
 instance
Message-ID: <1331080771-30687-1-git-send-email-khilman@ti.com>

commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
regulators) added regulators which are registered during
gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
than one instance of the SMSC911x and result in attempting to register
the same regulator more than once which causes a panic().

Fix this by only registering the regulator when the platform_data id
field is zero, indicating its the first instance.

Cc: Matt Porter <mporter at ti.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
Fix needed for v3.3.
Applies on top of Tony's fixes branch.

 arch/arm/mach-omap2/gpmc-smsc911x.c |   11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index bbb870c..4d6f1c6 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -101,10 +101,13 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
 
 	gpmc_cfg = board_data;
 
-	ret = platform_device_register(&gpmc_smsc911x_regulator);
-	if (ret < 0) {
-		pr_err("Unable to register smsc911x regulators: %d\n", ret);
-		return;
+	if (!gpmc_cfg) {
+		ret = platform_device_register(&gpmc_smsc911x_regulator);
+		if (ret < 0) {
+			pr_err("Unable to register smsc911x regulators: %d\n",
+			       ret);
+			return;
+		}
 	}
 
 	if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
-- 
1.7.9.2



From robertcnelson at gmail.com  Tue Mar  6 19:39:34 2012
From: robertcnelson at gmail.com (Robert Nelson)
Date: Tue, 6 Mar 2012 18:39:34 -0600
Subject: [PATCH] omap3_beagle: init uart2 for beagle rev AX/BX only
In-Reply-To: <20120306213859.GA12083@atomide.com>
References: <1331024711-23578-1-git-send-email-govindraj.raja@ti.com>
 <20120306213859.GA12083@atomide.com>
Message-ID: <CAOCHtYiERN2VySbBb7BoJAa97P4z6=a094vUMmgej3JP5Cy25g@mail.gmail.com>

On Tue, Mar 6, 2012 at 3:38 PM, Tony Lindgren <tony at atomide.com> wrote:
> * Govindraj.R <govindraj.raja at ti.com> [120306 00:34]:
>> From: "Govindraj.R" <govindraj.raja at ti.com>
>>
>> All beagle boards rev > AX/BX have external usb hubs connected to ehci
>> interface, external hub/peripheral uses a nreset sequence for which
>> uart2_rx.gpio_147 pin in mux mode4(USB2HS_nRST) is used on all beagle
>> boards expect rev Ax/BX.
>> (Reference to all beagle boards rev schematics:
>> http://beagleboard.org/hardware/design)
>>
>> Initialising uart2 will lead to serial init taking over uart2_rx pin
>> so init uart2_rx pin mux only for Beagle AX/BX rev boards.
>> Dont init uart2 for all other boards allowing usb_ehci functionality.
>>
>> To initialise individual uart port by id utilise and modify the existing
>> available func. omap_serial_board_init.
>>
>> Cc: Tony Lindgren <tony at atomide.com>
>> Cc: Kevin Hilman <khilman at ti.com>
>> Cc: Koen Kooi <koen at dominion.thruhere.net>
>> Tested-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
>> Tested-by: Robert Nelson <robertcnelson at gmail.com>
>> Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
>
> Can somebody please test this on non-xm beagle too and
> reply with a Tested-by?

Here's an update for my: Tested-by: Robert Nelson <robertcnelson at gmail.com>

Just tested with one of my Beagle C4's, (and re-verified the new patch
on a xM B) using usb flash drives on the ehci port...

beagle c4:
v3.2.9
Bus 001 Device 002: ID 0457:0151 Silicon Integrated Systems Corp.
Super Flash 1GB / GXT  64MB Flash Drive

v3.3-rc6:
ehci broken

v3.3-rc6 + this patch:
Bus 001 Device 002: ID 0457:0151 Silicon Integrated Systems Corp.
Super Flash 1GB / GXT  64MB Flash Driv

beagle xM B:
v3.2.9
Bus 001 Device 004: ID 1977:0824 T-Logic

v3.3-rc6:
ehci broken

v3.3-rc6 + this patch:
Bus 001 Device 004: ID 1977:0824 T-Logic

Regards,

-- 
Robert Nelson
http://www.rcn-ee.com/


From hartleys at visionengravers.com  Tue Mar  6 19:38:11 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 6 Mar 2012 18:38:11 -0600
Subject: [PATCH 2/9] dmaengine: move last completed cookie into generic
 dma_chan structure
In-Reply-To: <E1S52xK-0002Mj-Af@rmk-PC.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <E1S52xK-0002Mj-Af@rmk-PC.arm.linux.org.uk>
Message-ID: <ADE657CA350FB648AAC2C43247A983F001F41FF559A5@AUSP01VMBX24.collaborationhost.net>

On Tuesday, March 06, 2012 3:34 PM, Russell King wrote:
>
> Every DMA engine implementation declares a last completed dma cookie
> in their private dma channel structures.  This is pointless, and
> forces driver specific code.  Move this out into the common dma_chan
> structure.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---

<snip>

 drivers/dma/ep93xx_dma.c                 |    8 +++-----

<snip>

 include/linux/dmaengine.h                |    2 ++

<snip>

> diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
> index 59e7a96..bc45787 100644
> --- a/drivers/dma/ep93xx_dma.c
> +++ b/drivers/dma/ep93xx_dma.c
> @@ -122,7 +122,6 @@ struct ep93xx_dma_desc {
>   * @lock: lock protecting the fields following
>   * @flags: flags for the channel
>   * @buffer: which buffer to use next (0/1)
> - * @last_completed: last completed cookie value
>   * @active: flattened chain of descriptors currently being processed
>   * @queue: pending descriptors which are handled next
>   * @free_list: list of free descriptors which can be used
> @@ -157,7 +156,6 @@ struct ep93xx_dma_chan {
>  #define EP93XX_DMA_IS_CYCLIC		0
>  
>  	int				buffer;
> -	dma_cookie_t			last_completed;
>  	struct list_head		active;
>  	struct list_head		queue;
>  	struct list_head		free_list;
> @@ -703,7 +701,7 @@ static void ep93xx_dma_tasklet(unsigned long data)
>  	desc = ep93xx_dma_get_active(edmac);
>  	if (desc) {
>  		if (desc->complete) {
> -			edmac->last_completed = desc->txd.cookie;
> +			edmac->chan.completed_cookie = desc->txd.cookie;
>  			list_splice_init(&edmac->active, &list);
>  		}
>  		callback = desc->txd.callback;
> @@ -861,7 +859,7 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
>  		goto fail_clk_disable;
>  
>  	spin_lock_irq(&edmac->lock);
> -	edmac->last_completed = 1;
> +	edmac->chan.completed_cookie = 1;
>  	edmac->chan.cookie = 1;
>  	ret = edmac->edma->hw_setup(edmac);
>  	spin_unlock_irq(&edmac->lock);
> @@ -1254,7 +1252,7 @@ static enum dma_status ep93xx_dma_tx_status(struct dma_chan *chan,
>  
>  	spin_lock_irqsave(&edmac->lock, flags);
>  	last_used = chan->cookie;
> -	last_completed = edmac->last_completed;
> +	last_completed = chan->completed_cookie;
>  	spin_unlock_irqrestore(&edmac->lock, flags);
>  
>  	ret = dma_async_is_complete(cookie, last_completed, last_used);

<snip>

> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index 679b349..41d0f92 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -257,6 +257,7 @@ struct dma_chan_percpu {
>   * struct dma_chan - devices supply DMA channels, clients use them
>   * @device: ptr to the dma device who supplies this channel, always !%NULL
>   * @cookie: last cookie value returned to client
> + * @completed_cookie: last completed cookie for this channel
>   * @chan_id: channel ID for sysfs
>   * @dev: class device for sysfs
>   * @device_node: used to add this to the device chan list
> @@ -268,6 +269,7 @@ struct dma_chan_percpu {
>  struct dma_chan {
>  	struct dma_device *device;
>  	dma_cookie_t cookie;
> +	dma_cookie_t completed_cookie;
>  
>  	/* sysfs */
>  	int chan_id;

For ep93xx:

Tested-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>



From tony at atomide.com  Tue Mar  6 19:44:05 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 6 Mar 2012 16:44:05 -0800
Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulator
 for first instance
In-Reply-To: <1331080771-30687-1-git-send-email-khilman@ti.com>
References: <1331080771-30687-1-git-send-email-khilman@ti.com>
Message-ID: <20120307004405.GC12083@atomide.com>

* Kevin Hilman <khilman at ti.com> [120306 16:07]:
> commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
> regulators) added regulators which are registered during
> gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
> than one instance of the SMSC911x and result in attempting to register
> the same regulator more than once which causes a panic().
> 
> Fix this by only registering the regulator when the platform_data id
> field is zero, indicating its the first instance.
> 
> Cc: Matt Porter <mporter at ti.com>
> Signed-off-by: Kevin Hilman <khilman at ti.com>
> ---
> Fix needed for v3.3.
> Applies on top of Tony's fixes branch.
> 
>  arch/arm/mach-omap2/gpmc-smsc911x.c |   11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
> index bbb870c..4d6f1c6 100644
> --- a/arch/arm/mach-omap2/gpmc-smsc911x.c
> +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
> @@ -101,10 +101,13 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
>  
>  	gpmc_cfg = board_data;
>  
> -	ret = platform_device_register(&gpmc_smsc911x_regulator);
> -	if (ret < 0) {
> -		pr_err("Unable to register smsc911x regulators: %d\n", ret);
> -		return;
> +	if (!gpmc_cfg) {

Shouldn't this be !gpmc_cfg->id instead..

> +		ret = platform_device_register(&gpmc_smsc911x_regulator);
> +		if (ret < 0) {
> +			pr_err("Unable to register smsc911x regulators: %d\n",
> +			       ret);
> +			return;
> +		}
>  	}
>  
>  	if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {

..because we have gpmc_cfg always passed to gpmc_smsc911x_init().

Regards,

Tony


From hartleys at visionengravers.com  Tue Mar  6 19:47:54 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 6 Mar 2012 18:47:54 -0600
Subject: [PATCH 3/9] dmaengine: add private header file
In-Reply-To: <E1S52xe-0002Mn-Pn@rmk-PC.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <E1S52xe-0002Mn-Pn@rmk-PC.arm.linux.org.uk>
Message-ID: <ADE657CA350FB648AAC2C43247A983F001F41FF559AA@AUSP01VMBX24.collaborationhost.net>

On Tuesday, March 06, 2012 3:34 PM, Russell King wrote:
>
> Add a local private header file to contain definitions and declarations
> which should only be used by DMA engine drivers.
>
> We also fix linux/dmaengine.h to use LINUX_DMAENGINE_H to guard against
> multiple inclusion.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---

<snip>

>  drivers/dma/dmaengine.h     |   10 ++++++++++

<snip>

>  drivers/dma/ep93xx_dma.c    |    2 ++

<snip>

>  include/linux/dmaengine.h   |    4 ++--

<snip>

> diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
> new file mode 100644
> index 0000000..968570d
> --- /dev/null
> +++ b/drivers/dma/dmaengine.h
> @@ -0,0 +1,10 @@
> +/*
> + * The contents of this file are private to DMA engine drivers, and is not
> + * part of the API to be used by DMA engine users.
> + */
> +#ifndef DMAENGINE_H
> +#define DMAENGINE_H
> +
> +#include <linux/dmaengine.h>
> +
> +#endif

<snip>

> diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
> index bc45787..3260198 100644
> --- a/drivers/dma/ep93xx_dma.c
> +++ b/drivers/dma/ep93xx_dma.c
> @@ -28,6 +28,8 @@
>  
>  #include <mach/dma.h>
>  
> +#include "dmaengine.h"
> +
>  /* M2P registers */
>  #define M2P_CONTROL			0x0000
>  #define M2P_CONTROL_STALLINT		BIT(0)

<snip>

> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index 41d0f92..4b17ca8 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -18,8 +18,8 @@
>   * The full GNU General Public License is included in this distribution in the
>   * file called COPYING.
>   */
> -#ifndef DMAENGINE_H
> -#define DMAENGINE_H
> +#ifndef LINUX_DMAENGINE_H
> +#define LINUX_DMAENGINE_H
>  
>  #include <linux/device.h>
>  #include <linux/uio.h>

For ep93xx:

Tested-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>



From julian.calaby at gmail.com  Tue Mar  6 19:52:03 2012
From: julian.calaby at gmail.com (Julian Calaby)
Date: Wed, 7 Mar 2012 11:52:03 +1100
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
Message-ID: <CAGRGNgWHXrQgVobz+54sFBzj=bTHCKwg+H4_CY5JoGtmETw2yA@mail.gmail.com>

Hi Stephen,

On Wed, Mar 7, 2012 at 11:30, Stephen Warren <swarren at wwwdotorg.org> wrote:
> This allows the user to use U-Boot's mkimage's -T kernel_noload option
> if their arch Kconfig allows it, and they desire.
>
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> ---
> diff --git a/init/Kconfig b/init/Kconfig
> index 6cfd71d..2035562 100644
> --- a/init/Kconfig
> +++ b/init/Kconfig
> @@ -203,6 +203,21 @@ config KERNEL_LZO
>
> ?endchoice
>
> +config ALLOW_UIMAGE_KERNEL_NOLOAD
> + ? ? ? bool
> +
> +config UIMAGE_KERNEL_NOLOAD
> + ? ? ? bool "Use mkimage's -T kernel_noload instead of -T kernel"
> + ? ? ? depends on ALLOW_UIMAGE_KERNEL_NOLOAD
> + ? ? ? help
> + ? ? ? ? uImage files of type "kernel" embed an absolute load and entry point
> + ? ? ? ? address. If the uImage is loaded to a different address, then the
> + ? ? ? ? image must be copied the uImage file to the specified load address.

You seem to have an excess "the uImage file" in here.

> + ? ? ? ? This copy is a waste of time if the uImage is in fact completely
> + ? ? ? ? relocatable. If your kernel and bootloader support it, you can build
> + ? ? ? ? a "kernel_noload" uImage rather than a "kernel" uImage, which
> + ? ? ? ? prevents any such copying. If unsure say N.
> +
> ?config DEFAULT_HOSTNAME
> ? ? ? ?string "Default hostname"
> ? ? ? ?default "(none)"

Thanks,

-- 
Julian Calaby

Email: julian.calaby at gmail.com
Profile: http://www.google.com/profiles/julian.calaby/
.Plan: http://sites.google.com/site/juliancalaby/


From hartleys at visionengravers.com  Tue Mar  6 19:53:27 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 6 Mar 2012 18:53:27 -0600
Subject: [PATCH 4/9] dmaengine: consolidate assignment of DMA cookies
In-Reply-To: <E1S52xy-0002Ms-Ud@rmk-PC.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <E1S52xy-0002Ms-Ud@rmk-PC.arm.linux.org.uk>
Message-ID: <ADE657CA350FB648AAC2C43247A983F001F41FF559AB@AUSP01VMBX24.collaborationhost.net>

On Tuesday, March 06, 2012 3:35 PM, Russell King wrote:
>
> Everyone deals with assigning DMA cookies in the same way (it's part of
> the API so they should be), so lets consolidate the common code into a
> helper function to avoid this duplication.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---

<snip>

>  drivers/dma/dmaengine.h     |   20 ++++++++++++++++++++

<snip>

>  drivers/dma/ep93xx_dma.c    |    9 +--------

<snip>

> diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
> index 968570d..7692c86 100644
> --- a/drivers/dma/dmaengine.h
> +++ b/drivers/dma/dmaengine.h
> @@ -7,4 +7,24 @@
>  
>  #include <linux/dmaengine.h>
>  
> +/**
> + * dma_cookie_assign - assign a DMA engine cookie to the descriptor
> + * @tx: descriptor needing cookie
> + *
> + * Assign a unique non-zero per-channel cookie to the descriptor.
> + * Note: caller is expected to hold a lock to prevent concurrency.
> + */
> +static inline dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx)
> +{
> +	struct dma_chan *chan = tx->chan;
> +	dma_cookie_t cookie;
> +
> +	cookie = chan->cookie + 1;
> +	if (cookie < DMA_MIN_COOKIE)
> +		cookie = DMA_MIN_COOKIE;
> +	tx->cookie = chan->cookie = cookie;
> +
> +	return cookie;
> +}
> +
>  #endif

<snip>

> diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
> index 3260198..e5aaae8 100644
> --- a/drivers/dma/ep93xx_dma.c
> +++ b/drivers/dma/ep93xx_dma.c
> @@ -783,17 +783,10 @@ static dma_cookie_t ep93xx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
>  	unsigned long flags;
>  
>  	spin_lock_irqsave(&edmac->lock, flags);
> -
> -	cookie = edmac->chan.cookie;
> -
> -	if (++cookie < 0)
> -		cookie = 1;
> +	cookie = dma_cookie_assign(tx);
>  
>  	desc = container_of(tx, struct ep93xx_dma_desc, txd);
>  
> -	edmac->chan.cookie = cookie;
> -	desc->txd.cookie = cookie;
> -
>  	/*
>  	 * If nothing is currently prosessed, we push this descriptor
>  	 * directly to the hardware. Otherwise we put the descriptor

For ep93xx:

Tested-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>



From hartleys at visionengravers.com  Tue Mar  6 19:56:45 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 6 Mar 2012 18:56:45 -0600
Subject: [PATCH 5/9] dmaengine: provide a common function for completing
 a dma descriptor
In-Reply-To: <E1S52yJ-0002Mx-2e@rmk-PC.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <E1S52yJ-0002Mx-2e@rmk-PC.arm.linux.org.uk>
Message-ID: <ADE657CA350FB648AAC2C43247A983F001F41FF559AD@AUSP01VMBX24.collaborationhost.net>

On Tuesday, March 06, 2012 3:35 PM, Russell King wrote:
>
> Provide a common function to do the cookie mechanics for completing
> a DMA descriptor.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---

<snip>

>  drivers/dma/dmaengine.h     |   18 ++++++++++++++++++

<snip>

>  drivers/dma/ep93xx_dma.c    |    2 +-

<snip>

> diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
> index 7692c86..47e0997 100644
> --- a/drivers/dma/dmaengine.h
> +++ b/drivers/dma/dmaengine.h
> @@ -5,6 +5,7 @@
>  #ifndef DMAENGINE_H
>  #define DMAENGINE_H
>  
> +#include <linux/bug.h>
>  #include <linux/dmaengine.h>
>  
>  /**
> @@ -27,4 +28,21 @@ static inline dma_cookie_t dma_cookie_assign(struct dma_async_tx_descriptor *tx)
>  	return cookie;
>  }
>  
> +/**
> + * dma_cookie_complete - complete a descriptor
> + * @tx: descriptor to complete
> + *
> + * Mark this descriptor complete by updating the channels completed
> + * cookie marker.  Zero the descriptors cookie to prevent accidental
> + * repeated completions.
> + *
> + * Note: caller is expected to hold a lock to prevent concurrency.
> + */
> +static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
> +{
> +	BUG_ON(tx->cookie < DMA_MIN_COOKIE);
> +	tx->chan->completed_cookie = tx->cookie;
> +	tx->cookie = 0;
> +}
> +
>  #endif

<snip>

> diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
> index e5aaae8..1c56f75 100644
> --- a/drivers/dma/ep93xx_dma.c
> +++ b/drivers/dma/ep93xx_dma.c
> @@ -703,7 +703,7 @@ static void ep93xx_dma_tasklet(unsigned long data)
>  	desc = ep93xx_dma_get_active(edmac);
>  	if (desc) {
>  		if (desc->complete) {
> -			edmac->chan.completed_cookie = desc->txd.cookie;
> +			dma_cookie_complete(&desc->txd);
>  			list_splice_init(&edmac->active, &list);
>  		}
>  		callback = desc->txd.callback;

For ep93xx:

Tested-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>



From bhelgaas at google.com  Tue Mar  6 20:00:32 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Tue, 06 Mar 2012 18:00:32 -0700
Subject: [PATCH v1 5/9] arm/PCI: don't export pci_flags
In-Reply-To: <20120307005905.27465.71131.stgit@bhelgaas.mtv.corp.google.com>
References: <20120307005905.27465.71131.stgit@bhelgaas.mtv.corp.google.com>
Message-ID: <20120307010032.27465.35675.stgit@bhelgaas.mtv.corp.google.com>

There's no need to export pci_flags; it's not exported by any other
architecture, and no modules reference it.

CC: Rob Herring <rob.herring at calxeda.com>
CC: Russell King <linux at arm.linux.org.uk>
CC: linux-arm-kernel at lists.infradead.org
Signed-off-by: Bjorn Helgaas <bhelgaas at google.com>
---
 arch/arm/kernel/bios32.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index be5d3b2..632df9a 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -498,7 +498,6 @@ void __init pci_common_init(struct hw_pci *hw)
 		pci_bus_add_devices(bus);
 	}
 }
-EXPORT_SYMBOL(pci_flags);
 
 #ifndef CONFIG_PCI_HOST_ITE8152
 void pcibios_set_master(struct pci_dev *dev)



From hartleys at visionengravers.com  Tue Mar  6 20:04:54 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 6 Mar 2012 19:04:54 -0600
Subject: [PATCH 6/9] dmaengine: consolidate tx_status functions
In-Reply-To: <E1S52yd-0002N1-76@rmk-PC.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <E1S52yd-0002N1-76@rmk-PC.arm.linux.org.uk>
Message-ID: <ADE657CA350FB648AAC2C43247A983F001F41FF559AF@AUSP01VMBX24.collaborationhost.net>

On Tuesday, March 06, 2012 3:35 PM, Russell King wrote:
>
> Now that we have the completed cookie in the dma_chan structure, we
> can consolidate the tx_status functions by providing a function to set
> the txstate structure and returning the DMA status.  We also provide
> a separate helper to set the residue for cookies which are still in
> progress.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---

<snip>

>  drivers/dma/dmaengine.h     |   31 +++++++++++++++++++++++++++++++

<snip>

>  drivers/dma/ep93xx_dma.c    |    7 +------

<snip>

> diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
> index 47e0997..1ca5e0e 100644
> --- a/drivers/dma/dmaengine.h
> +++ b/drivers/dma/dmaengine.h
> @@ -45,4 +45,35 @@ static inline void dma_cookie_complete(struct dma_async_tx_descriptor *tx)
>  	tx->cookie = 0;
>  }
>  
> +/**
> + * dma_cookie_status - report cookie status
> + * @chan: dma channel
> + * @cookie: cookie we are interested in
> + * @state: dma_tx_state structure to return last/used cookies
> + *
> + * Report the status of the cookie, filling in the state structure if
> + * non-NULL.  No locking is required.
> + */
> +static inline enum dma_status dma_cookie_status(struct dma_chan *chan,
> +	dma_cookie_t cookie, struct dma_tx_state *state)
> +{
> +	dma_cookie_t used, complete;
> +
> +	used = chan->cookie;
> +	complete = chan->completed_cookie;
> +	barrier();
> +	if (state) {
> +		state->last = complete;
> +		state->used = used;
> +		state->residue = 0;
> +	}
> +	return dma_async_is_complete(cookie, complete, used);
> +}
> +
> +static inline void dma_set_residue(struct dma_tx_state *state, u32 residue)
> +{
> +	if (state)
> +		state->residue = residue;
> +}
> +
>  #endif

<snip>

> diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
> index 1c56f75..142ebf0 100644
> --- a/drivers/dma/ep93xx_dma.c
> +++ b/drivers/dma/ep93xx_dma.c
> @@ -1241,18 +1241,13 @@ static enum dma_status ep93xx_dma_tx_status(struct dma_chan *chan,
>  					    struct dma_tx_state *state)
>  {
>  	struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
> -	dma_cookie_t last_used, last_completed;
>  	enum dma_status ret;
>  	unsigned long flags;
>  
>  	spin_lock_irqsave(&edmac->lock, flags);
> -	last_used = chan->cookie;
> -	last_completed = chan->completed_cookie;
> +	ret = dma_cookie_status(chan, cookie, state);
>  	spin_unlock_irqrestore(&edmac->lock, flags);
>  
> -	ret = dma_async_is_complete(cookie, last_completed, last_used);
> -	dma_set_tx_state(state, last_completed, last_used, 0);
> -
>  	return ret;
>  }
>  

For ep93xx:

Tested-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>



From hartleys at visionengravers.com  Tue Mar  6 20:07:37 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 6 Mar 2012 19:07:37 -0600
Subject: [PATCH 7/9] dmaengine: consolidate initialization of cookies
In-Reply-To: <E1S52yx-0002N5-Bc@rmk-PC.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <E1S52yx-0002N5-Bc@rmk-PC.arm.linux.org.uk>
Message-ID: <ADE657CA350FB648AAC2C43247A983F001F41FF559B0@AUSP01VMBX24.collaborationhost.net>

On Tuesday, March 06, 2012 3:36 PM, Russell King wrote:
>
> Provide a common function to initialize a channels cookie values.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---

<snip>

>  drivers/dma/dmaengine.h     |   10 ++++++++++

<snip>

>  drivers/dma/ep93xx_dma.c    |    3 +--

<snip>

> diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h
> index 1ca5e0e..17f983a 100644
> --- a/drivers/dma/dmaengine.h
> +++ b/drivers/dma/dmaengine.h
> @@ -9,6 +9,16 @@
>  #include <linux/dmaengine.h>
>  
>  /**
> + * dma_cookie_init - initialize the cookies for a DMA channel
> + * @chan: dma channel to initialize
> + */
> +static inline void dma_cookie_init(struct dma_chan *chan)
> +{
> +	chan->cookie = DMA_MIN_COOKIE;
> +	chan->completed_cookie = DMA_MIN_COOKIE;
> +}
> +
> +/**
>   * dma_cookie_assign - assign a DMA engine cookie to the descriptor
>   * @tx: descriptor needing cookie
>   *

<snip>

> diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
> index 142ebf0..f25e83b 100644
> --- a/drivers/dma/ep93xx_dma.c
> +++ b/drivers/dma/ep93xx_dma.c
> @@ -854,8 +854,7 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
>  		goto fail_clk_disable;
>  
>  	spin_lock_irq(&edmac->lock);
> -	edmac->chan.completed_cookie = 1;
> -	edmac->chan.cookie = 1;
> +	dma_cookie_init(&edmac->chan);
>  	ret = edmac->edma->hw_setup(edmac);
>  	spin_unlock_irq(&edmac->lock);
>  

For ep93xx:

Tested-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>



From pullip.cho at samsung.com  Tue Mar  6 20:24:56 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Wed, 7 Mar 2012 10:24:56 +0900
Subject: [PATCH v10 3/3] iommu/exynos: Add iommu driver for Exynos
 Platforms
In-Reply-To: <CAH9JG2W=E7xmEO3o+up5a5Vm1PrPp60w0cfzN7=bYQO2BX1teA@mail.gmail.com>
References: <002201ccfb73$93311520$b9933f60$%cho@samsung.com>
 <CAH9JG2W=E7xmEO3o+up5a5Vm1PrPp60w0cfzN7=bYQO2BX1teA@mail.gmail.com>
Message-ID: <CAHQjnOOCFqSNtvvvvd54yFvrrnPJmZQhi3LXT8jZArcEhjePXQ@mail.gmail.com>

On Tue, Mar 6, 2012 at 10:13 PM, Kyungmin Park <kmpark at infradead.org> wrote:
> On Tue, Mar 6, 2012 at 5:31 PM, KyongHo Cho <pullip.cho at samsung.com> wrote:
>> HAALgBjAGgAbwBAAHMAYQBtAHMAdQBuAGcALgBjAG8AbQA=;Tue,
>> ?06 Mar 2012 08:31:29 GMT;WwBQAEEAVABDAEgAIAB2ADEAMAAgADMALwAzAF0AIABpAG8AbQBtAHUALwBlAHgAeQBuAG8AcwA6ACAAQQBkAGQAIABpAG8AbQBtAHUAIABkAHIAaQB2AGUAcgAgAGYAbwByACAARQB4AHkAbgBvAHMAIABQAGwAYQB0AGYAbwByAG0AcwA=
>> x-cr-puzzleid: {CF0AAF04-8639-4D69-B4E1-BF71EA1B0A70}
> What's this?
I think it is inserted by Outlook and it was not found in the email editor
before sending this patch. I am unable to use sendmail due to security
reason in my company.
I will find a way not to insert the above message. Thank you.

>>
>> This is the System MMU driver and IOMMU API implementation for
>> Exynos SOC platforms. Exynos platforms has more than 10 System
>> MMUs dedicated for each multimedia accellerators.
>>
>> The System MMU driver is already in arc/arm/plat-s5p but it is
>> moved to drivers/iommu due to Ohad Ben-Cohen gathered IOMMU drivers
>> there
>>
>> Any device driver in Exynos platforms that needs to control its
>> System MMU must call platform_set_sysmmu() to inform System MMU
>> driver who will control it.
>> platform_set_sysmmu() is defined in <mach/sysmmu.h>
> Does it really required? if we can remove it. it can be compiled
> without arch dependency.
The function must be called while board initialization and all source files for
the purpose is placed in 'mach' directory. Thus device driver is not dependent
on arch except the definition of data structure conveyed in
device.platform_data.

Since our System MMUs are attached to each peripheral devices, it is required
to define relationships between System MMUs and peripheral devices.
platform_set_sysmmu() defines the relationship.

>> +
>> +#ifdef CONFIG_EXYNOS_IOMMU_DEBUG
>> +#define DEBUG
>> +#endif
> If it's used only at here. you can add it at Makefile.
>
> ifeq ($(CONFIG_EXYNOS_IOMMU_DEBUG),y)
> ? ? ? ? CFLAGS-exynos-iommu ? ? ? ?+= -DDEBUG
> endif
>
> Of course you can select as your preference.

Thank you for advice.

>> +
>> +#define lv2ent_fault(pent) ((*(pent) & 3) == 0)
>> +#define lv2ent_small(pent) ((*(pent) & 2) == 2)
> #define lv2ent_small(pent) ((*(pent) & 3) == 2)?

The last bit is 'don't-care'.
It is intentionally ignored in the above comparison.

>> +
>> +#define REG_MMU_CTRL ? ? ? ? ? 0x000
>> +#define REG_MMU_CFG ? ? ? ? ? ?0x004
>> +#define REG_MMU_STATUS ? ? ? ? 0x008
>> +#define REG_MMU_FLUSH ? ? ? ? ?0x00C
>> +#define REG_MMU_FLUSH_ENTRY ? ?0x010
>> +#define REG_PT_BASE_ADDR ? ? ? 0x014
>> +#define REG_INT_STATUS ? ? ? ? 0x018
>> +#define REG_INT_CLEAR ? ? ? ? ?0x01C
>> +#define REG_MMU_VERSION ? ? ? ? ? ? ? ?0x034
> Please place it in order.

I found that a mistake while defining the offsets of control registers.
I will fix it.

>> +
>> +enum EXYNOS_SYSMMU_INTERRUPT_TYPE {
>> + ? ? ? SYSMMU_PAGEFAULT,
>> + ? ? ? SYSMMU_AR_MULTIHIT,
>> + ? ? ? SYSMMU_AW_MULTIHIT,
>> + ? ? ? SYSMMU_BUSERROR,
>> + ? ? ? SYSMMU_AR_SECURITY,
>> + ? ? ? SYSMMU_AR_ACCESS,
>> + ? ? ? SYSMMU_AW_SECURITY,
>> + ? ? ? SYSMMU_AW_PROTECTION, /* 7 */
>> + ? ? ? SYSMMU_FAULT_UNKNOWN,
>> + ? ? ? SYSMMU_FAULTS_NUM
> missing comma, "SYSMMU_FAULTS_NUM,"
Yes it is. I don't think that it is needed to appending comma after
the last element
unless it is predictable that adding elements after the last element
in the future.

>> +};
>> +
>> +typedef int (*sysmmu_fault_handler_t)(enum EXYNOS_SYSMMU_INTERRUPT_TYPE itype,
>> + ? ? ? ? ? ? ? ? ? ? ? unsigned long pgtable_base, unsigned long fault_addr);
>> +
>> +static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
>> + ? ? ? REG_PAGE_FAULT_ADDR,
>> + ? ? ? REG_AR_FAULT_ADDR,
>> + ? ? ? REG_AW_FAULT_ADDR,
>> + ? ? ? REG_DEFAULT_SLAVE_ADDR,
>> + ? ? ? REG_AR_FAULT_ADDR,
>> + ? ? ? REG_AR_FAULT_ADDR,
>> + ? ? ? REG_AW_FAULT_ADDR,
>> + ? ? ? REG_AW_FAULT_ADDR
> ditto.
Answered above.

>> +};
>> +
>> +static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
>> + ? ? ? "PAGE FAULT",
>> + ? ? ? "AR MULTI-HIT FAULT",
>> + ? ? ? "AW MULTI-HIT FAULT",
>> + ? ? ? "BUS ERROR",
>> + ? ? ? "AR SECURITY PROTECTION FAULT",
>> + ? ? ? "AR ACCESS PROTECTION FAULT",
>> + ? ? ? "AW SECURITY PROTECTION FAULT",
>> + ? ? ? "AW ACCESS PROTECTION FAULT",
>> + ? ? ? "UNKNOWN FAULT"
> ditto.
Answered above.

>> +void exynos_sysmmu_set_prefbuf(struct device *dev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long base0, unsigned long size0,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long base1, unsigned long size1)
>> +{
>> + ? ? ? struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
>> + ? ? ? unsigned long flags;
>> + ? ? ? int i;
>> +
>> + ? ? ? BUG_ON((base0 + size0) <= base0);
>> + ? ? ? BUG_ON((size1 > 0) && ((base1 + size1) <= base1));
> It's bogus check. it's impossible. Do you think overflow case?
Yes I do.
It is prepared to detect invalid parameters from device drivers.

>> +
>> + ? ? ? read_lock_irqsave(&data->lock, flags);
>> + ? ? ? if (!is_sysmmu_active(data))
>> + ? ? ? ? ? ? ? goto finish;
>> +
>> + ? ? ? for (i = 0; i < data->nsfrs; i++) {
>> + ? ? ? ? ? ? ? if ((readl(data->sfrbases[i] + S5P_MMU_VERSION) >> 28) == 3) {
>> + ? ? ? ? ? ? ? ? ? ? ? sysmmu_block(data->sfrbases[i]);
>> +
>> + ? ? ? ? ? ? ? ? ? ? ? if (size1 == 0) {
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? if (size0 <= SZ_128K) {
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? base1 = base0;
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size1 = size0;
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? } else {
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size1 = size0 -
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ALIGN(size0 / 2, SZ_64K);
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size0 = size0 - size1;
> Umm I mis-understand this codes at first. it think size1 has 0
> already. so it's meaning-less but now it re-use the size1 above.

Let me explain how this function works.
This function can accepts 2 memory regions to specify in the registers
of System MMU.
It is simple a device driver defines 2 memory regions but this function allows
it to define just one memory region and specify second regions as zero.
If the second regions is zero, this function divides the first region
into 2 regions
and specifies those regions into the registers of System MMU.

>> +void exynos_sysmmu_set_fault_handler(struct device *dev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sysmmu_fault_handler_t handler)
>> +{
>> + ? ? ? struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
>> +
>> + ? ? ? __set_fault_handler(data, handler);
>> +}
>> +
>> +static int default_fault_handler(enum EXYNOS_SYSMMU_INTERRUPT_TYPE itype,
> Can you use the small letter instead of large one? do you see codes like this?
Ok. I will make it lower case.

>> +static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long iova)
>> +{
>> + ? ? ? struct exynos_iommu_domain *priv = domain->priv;
>> + ? ? ? unsigned long *entry;
>> + ? ? ? unsigned long flags;
>> + ? ? ? phys_addr_t phys = -1;
>> +
>> + ? ? ? spin_lock_irqsave(&priv->pgtablelock, flags);
>> +
>> + ? ? ? entry = section_entry(priv->pgtable, iova);
>> +
>> + ? ? ? if (lv1ent_section(entry)) {
>> + ? ? ? ? ? ? ? phys = section_phys(entry) + section_offs(iova);
>> + ? ? ? } else if (lv1ent_page(entry)) {
>> + ? ? ? ? ? ? ? entry = page_entry(entry, iova);
>> +
>> + ? ? ? ? ? ? ? if (lv2ent_large(entry))
>> + ? ? ? ? ? ? ? ? ? ? ? phys = lpage_phys(entry) + lpage_offs(iova);
>> + ? ? ? ? ? ? ? else if (lv2ent_small(entry))
>> + ? ? ? ? ? ? ? ? ? ? ? phys = spage_phys(entry) + spage_offs(iova);
>> + ? ? ? }
>> +
>> + ? ? ? spin_unlock_irqrestore(&priv->pgtablelock, flags);
>> +
>> + ? ? ? return phys;
> What's happened if phys has -1? I mean it can't trigger any condition at above.
This function just follows page tables and finding corresponding
physical address
for the given IO virtual address.
-1 (0xFFFFFFFF in 32bit system) is just an error value
if no translation information is found.

But I found most IOMMU drivers return 0 for the case.
I will change it to 0.

Thank you for kind review.

Cho KyongHo.


From khilman at ti.com  Tue Mar  6 20:39:33 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 06 Mar 2012 17:39:33 -0800
Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulator for
 first instance
In-Reply-To: <20120307004405.GC12083@atomide.com> (Tony Lindgren's message of
 "Tue, 6 Mar 2012 16:44:05 -0800")
References: <1331080771-30687-1-git-send-email-khilman@ti.com>
 <20120307004405.GC12083@atomide.com>
Message-ID: <87sjhlnq96.fsf@ti.com>

Tony Lindgren <tony at atomide.com> writes:

> * Kevin Hilman <khilman at ti.com> [120306 16:07]:
>> commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
>> regulators) added regulators which are registered during
>> gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
>> than one instance of the SMSC911x and result in attempting to register
>> the same regulator more than once which causes a panic().
>> 
>> Fix this by only registering the regulator when the platform_data id
>> field is zero, indicating its the first instance.
>> 
>> Cc: Matt Porter <mporter at ti.com>
>> Signed-off-by: Kevin Hilman <khilman at ti.com>
>> ---
>> Fix needed for v3.3.
>> Applies on top of Tony's fixes branch.
>> 
>>  arch/arm/mach-omap2/gpmc-smsc911x.c |   11 +++++++----
>>  1 file changed, 7 insertions(+), 4 deletions(-)
>> 
>> diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
>> index bbb870c..4d6f1c6 100644
>> --- a/arch/arm/mach-omap2/gpmc-smsc911x.c
>> +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
>> @@ -101,10 +101,13 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
>>  
>>  	gpmc_cfg = board_data;
>>  
>> -	ret = platform_device_register(&gpmc_smsc911x_regulator);
>> -	if (ret < 0) {
>> -		pr_err("Unable to register smsc911x regulators: %d\n", ret);
>> -		return;
>> +	if (!gpmc_cfg) {
>
> Shouldn't this be !gpmc_cfg->id instead..

doh, of course.  Updated patch below.

Kevin

>From 3c17a6fe6fdcc5e4e33f174c2b0982d71e759cf1 Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman at ti.com>
Date: Thu, 1 Mar 2012 12:30:42 -0800
Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulator for
 first instance

commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
regulators) added regulators which are registered during
gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
than one instance of the SMSC911x and result in attempting to register
the same regulator more than once which causes a panic().

Fix this by only registering the regulator when the platform_data id
field is zero, indicating its the first instance.

Cc: Matt Porter <mporter at ti.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/gpmc-smsc911x.c |   11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index bbb870c..5e5880d 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -101,10 +101,13 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
 
 	gpmc_cfg = board_data;
 
-	ret = platform_device_register(&gpmc_smsc911x_regulator);
-	if (ret < 0) {
-		pr_err("Unable to register smsc911x regulators: %d\n", ret);
-		return;
+	if (!gpmc_cfg->id) {
+		ret = platform_device_register(&gpmc_smsc911x_regulator);
+		if (ret < 0) {
+			pr_err("Unable to register smsc911x regulators: %d\n",
+			       ret);
+			return;
+		}
 	}
 
 	if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
-- 
1.7.9.2



From haojian.zhuang at gmail.com  Tue Mar  6 20:42:05 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed,  7 Mar 2012 09:42:05 +0800
Subject: [PATCH v3 1/6] serial: pxa: add OF support
In-Reply-To: <201203061502.08097.arnd@arndb.de>
References: <201203061502.08097.arnd@arndb.de>
Message-ID: <1331084525-4638-1-git-send-email-haojian.zhuang@gmail.com>

From: Haojian Zhuang <haojian.zhuang at marvell.com>

Parse uart device id from alias in DTS file.

Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/tty/serial/pxa.c |   49 ++++++++++++++++++++++++++++++++++-----------
 1 files changed, 37 insertions(+), 12 deletions(-)

diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
index 5c8e3bb..cdf4b2b 100644
--- a/drivers/tty/serial/pxa.c
+++ b/drivers/tty/serial/pxa.c
@@ -36,6 +36,7 @@
 #include <linux/circ_buf.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
@@ -44,6 +45,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
+#define PXA_NAME_LEN		8
+
 struct uart_pxa_port {
 	struct uart_port        port;
 	unsigned char           ier;
@@ -51,7 +54,7 @@ struct uart_pxa_port {
 	unsigned char           mcr;
 	unsigned int            lsr_break_flag;
 	struct clk		*clk;
-	char			*name;
+	char			name[PXA_NAME_LEN];
 };
 
 static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
@@ -781,6 +784,31 @@ static const struct dev_pm_ops serial_pxa_pm_ops = {
 };
 #endif
 
+static struct of_device_id serial_pxa_dt_ids[] = {
+	{ .compatible = "mrvl,pxa-uart", },
+	{ .compatible = "mrvl,mmp-uart", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids);
+
+static int serial_pxa_probe_dt(struct platform_device *pdev,
+			       struct uart_pxa_port *sport)
+{
+	struct device_node *np = pdev->dev.of_node;
+	int ret;
+
+	if (!np)
+		return 1;
+
+	ret = of_alias_get_id(np, "serial");
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+		return ret;
+	}
+	sport->port.line = ret;
+	return 0;
+}
+
 static int serial_pxa_probe(struct platform_device *dev)
 {
 	struct uart_pxa_port *sport;
@@ -808,20 +836,16 @@ static int serial_pxa_probe(struct platform_device *dev)
 	sport->port.irq = irqres->start;
 	sport->port.fifosize = 64;
 	sport->port.ops = &serial_pxa_pops;
-	sport->port.line = dev->id;
 	sport->port.dev = &dev->dev;
 	sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
 	sport->port.uartclk = clk_get_rate(sport->clk);
 
-	switch (dev->id) {
-	case 0: sport->name = "FFUART"; break;
-	case 1: sport->name = "BTUART"; break;
-	case 2: sport->name = "STUART"; break;
-	case 3: sport->name = "HWUART"; break;
-	default:
-		sport->name = "???";
-		break;
-	}
+	ret = serial_pxa_probe_dt(dev, sport);
+	if (ret > 0)
+		sport->port.line = dev->id;
+	else if (ret < 0)
+		goto err_clk;
+	snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
 
 	sport->port.membase = ioremap(mmres->start, resource_size(mmres));
 	if (!sport->port.membase) {
@@ -829,7 +853,7 @@ static int serial_pxa_probe(struct platform_device *dev)
 		goto err_clk;
 	}
 
-	serial_pxa_ports[dev->id] = sport;
+	serial_pxa_ports[sport->port.line] = sport;
 
 	uart_add_one_port(&serial_pxa_reg, &sport->port);
 	platform_set_drvdata(dev, sport);
@@ -866,6 +890,7 @@ static struct platform_driver serial_pxa_driver = {
 #ifdef CONFIG_PM
 		.pm	= &serial_pxa_pm_ops,
 #endif
+		.of_match_table = serial_pxa_dt_ids,
 	},
 };
 
-- 
1.7.5.4



From haojian.zhuang at gmail.com  Tue Mar  6 20:45:29 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 7 Mar 2012 09:45:29 +0800
Subject: [GIT PULL][v3.4] pull request on pxa tree for DT branch
In-Reply-To: <CAN1soZyA8iYJjcWRQoPEP=ksCwVfP6JYqcAdVh_qYjg2oc5XqQ@mail.gmail.com>
References: <CAN1soZyA8iYJjcWRQoPEP=ksCwVfP6JYqcAdVh_qYjg2oc5XqQ@mail.gmail.com>
Message-ID: <CAN1soZzd_6BS=qXKzm8-a+Z=rqC1shJYcoHNwedcHUVhsMo4Ww@mail.gmail.com>

Hi Arnd,

I update the branch according the comments on serial-pxa driver.
Please help to merge these patches.

Thanks
Haojian

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

  Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:
  git://github.com/hzhuang1/linux.git dt

Haojian Zhuang (6):
      serial: pxa: add OF support
      i2c: pxa: add OF support
      ARM: mmp: enable rtc clk in pxa168
      ARM: mmp: append OF support on pxa168
      ARM: dts: append DTS file of pxa168
      Document: devicetree: add OF documents for arch-mmp

 Documentation/devicetree/bindings/arm/mrvl.txt     |    6 +
 .../devicetree/bindings/gpio/mrvl-gpio.txt         |   23 +++++
 Documentation/devicetree/bindings/i2c/mrvl-i2c.txt |   37 ++++++++
 .../devicetree/bindings/rtc/sa1100-rtc.txt         |   17 ++++
 .../devicetree/bindings/serial/mrvl-serial.txt     |    4 +
 arch/arm/boot/dts/pxa168-aspenite.dts              |   38 ++++++++
 arch/arm/boot/dts/pxa168.dtsi                      |   98 ++++++++++++++++++++
 arch/arm/mach-mmp/Kconfig                          |   10 ++
 arch/arm/mach-mmp/Makefile                         |    1 +
 arch/arm/mach-mmp/mmp-dt.c                         |   75 +++++++++++++++
 arch/arm/mach-mmp/pxa168.c                         |    2 +
 drivers/i2c/busses/i2c-pxa.c                       |   95 +++++++++++++++----
 drivers/tty/serial/pxa.c                           |   49 ++++++++---
 13 files changed, 422 insertions(+), 33 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mrvl.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
 create mode 100644 Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
 create mode 100644 Documentation/devicetree/bindings/serial/mrvl-serial.txt
 create mode 100644 arch/arm/boot/dts/pxa168-aspenite.dts
 create mode 100644 arch/arm/boot/dts/pxa168.dtsi
 create mode 100644 arch/arm/mach-mmp/mmp-dt.c


On Tue, Mar 6, 2012 at 1:51 PM, Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
> Hi Arnd,
>
> Please help to pull DT patches on pxa tree. I based it on v3.3-rc6.
>
> The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
>
> ?Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)
>
> are available in the git repository at:
> ?git://github.com/hzhuang1/linux.git dt
>
> Haojian Zhuang (6):
> ? ? ?serial: pxa: add OF support
> ? ? ?i2c: pxa: add OF support
> ? ? ?ARM: mmp: enable rtc clk in pxa168
> ? ? ?ARM: mmp: append OF support on pxa168
> ? ? ?ARM: dts: append DTS file of pxa168
> ? ? ?Document: devicetree: add OF documents for arch-mmp
>
> ?Documentation/devicetree/bindings/arm/mrvl.txt ? ? | ? ?6 +
> ?.../devicetree/bindings/gpio/mrvl-gpio.txt ? ? ? ? | ? 23 +++++
> ?Documentation/devicetree/bindings/i2c/mrvl-i2c.txt | ? 37 ++++++++
> ?.../devicetree/bindings/rtc/sa1100-rtc.txt ? ? ? ? | ? 17 ++++
> ?.../devicetree/bindings/serial/mrvl-serial.txt ? ? | ? ?4 +
> ?arch/arm/boot/dts/pxa168-aspenite.dts ? ? ? ? ? ? ?| ? 38 ++++++++
> ?arch/arm/boot/dts/pxa168.dtsi ? ? ? ? ? ? ? ? ? ? ?| ? 98 ++++++++++++++++++++
> ?arch/arm/mach-mmp/Kconfig ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 10 ++
> ?arch/arm/mach-mmp/Makefile ? ? ? ? ? ? ? ? ? ? ? ? | ? ?1 +
> ?arch/arm/mach-mmp/mmp-dt.c ? ? ? ? ? ? ? ? ? ? ? ? | ? 75 +++++++++++++++
> ?arch/arm/mach-mmp/pxa168.c ? ? ? ? ? ? ? ? ? ? ? ? | ? ?2 +
> ?drivers/i2c/busses/i2c-pxa.c ? ? ? ? ? ? ? ? ? ? ? | ? 95 +++++++++++++++----
> ?drivers/tty/serial/pxa.c ? ? ? ? ? ? ? ? ? ? ? ? ? | ? 52 ++++++++---
> ?13 files changed, 425 insertions(+), 33 deletions(-)
> ?create mode 100644 Documentation/devicetree/bindings/arm/mrvl.txt
> ?create mode 100644 Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
> ?create mode 100644 Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
> ?create mode 100644 Documentation/devicetree/bindings/rtc/sa1100-rtc.txt
> ?create mode 100644 Documentation/devicetree/bindings/serial/mrvl-serial.txt
> ?create mode 100644 arch/arm/boot/dts/pxa168-aspenite.dts
> ?create mode 100644 arch/arm/boot/dts/pxa168.dtsi
> ?create mode 100644 arch/arm/mach-mmp/mmp-dt.c


From lost.distance at yahoo.com  Tue Mar  6 20:46:54 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Wed, 7 Mar 2012 01:46:54 +0000 (GMT)
Subject: [PATCH v2] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <1331066978-24774-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>

--- On Tue, 6/3/12, Paul Gortmaker <paul.gortmaker at windriver.com> wrote:
> commit
> 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)
> 
> ? "regulator: Remove support for supplies specified by
> struct device"
> 
> deletes the field from the struct, but this platform was
> still trying
> to set those fields.? Convert them to use the
> REGULATOR_SUPPLY macro
> so as to fix this failure:
> 
> arch/arm/mach-pxa/magician.c:581: error: unknown field 'dev'
> specified in initializer
> arch/arm/mach-pxa/magician.c:581: warning: initialization
> from incompatible pointer type
> arch/arm/mach-pxa/magician.c:585: error: unknown field 'dev'
> specified in initializer
> arch/arm/mach-pxa/magician.c:585: warning: initialization
> from incompatible pointer type
> 
> arch/arm/mach-pxa/hx4700.c:683: error: unknown field 'dev'
> specified in initializer
> arch/arm/mach-pxa/hx4700.c:683: warning: initialization from
> incompatible pointer type
> arch/arm/mach-pxa/hx4700.c:687: error: unknown field 'dev'
> specified in initializer
> arch/arm/mach-pxa/hx4700.c:687: warning: initialization from
> incompatible pointer type
> 
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> ---
> 
> [v2: convert to using REGULATOR_SUPPLY instead of just
> deleting the
>  instances of setting the .dev field ]
> 
> diff --git a/arch/arm/mach-pxa/hx4700.c
> b/arch/arm/mach-pxa/hx4700.c
> index f2c23ea..53c3366 100644
> --- a/arch/arm/mach-pxa/hx4700.c
> +++ b/arch/arm/mach-pxa/hx4700.c
> @@ -679,14 +679,8 @@ static struct platform_device
> power_supply = {
> ? */
>  
>  static struct regulator_consumer_supply bq24022_consumers[]
> = {
> -??? {
> -??? ??? .dev =
> &gpio_vbus.dev,
> -??? ??? .supply =
> "vbus_draw",
> -??? },
> -??? {
> -??? ??? .dev =
> &power_supply.dev,
> -??? ??? .supply = "ac_draw",
> -??? },
> +??? REGULATOR_SUPPLY("vbus_draw",
> "gpio_vbus"),
> +??? REGULATOR_SUPPLY("ac_draw",
> "power_supply"),
>  };

The above hx4700 patch yields the following warnings:

_regulator_get: gpio-vbus supply vbus_draw not found, using dummy regulator
_regulator_get: pda-power supply ac_draw not found, using dummy regulator

I suggest the following lines instead:

	REGULATOR_SUPPLY("vbus_draw", "gpio-vbus"),
	REGULATOR_SUPPLY("ac_draw", "pda-power"),



From haojian.zhuang at gmail.com  Tue Mar  6 20:54:20 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 7 Mar 2012 09:54:20 +0800
Subject: [GIT PULL v2][for v3.4] request pull from arch-pxa on regulator branch
Message-ID: <CAN1soZzw+hAACoscyJ0q65t84ighZ1zPG92uKnwT-pDgcF2b6Q@mail.gmail.com>

Hi Arnd,

Please help to merge these patches from arch-pxa. They're used to
convert bq24022
to gpio-regulator. Now Mark acked these patches.

Best Regards
Haojian

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

  Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:
  git://github.com/hzhuang1/linux.git regulator

Heiko St?bner (2):
      pxa: magician/hx4700: Convert to gpio-regulator from bq24022
      regulator: Remove bq24022 regulator driver

 arch/arm/configs/magician_defconfig |    2 +-
 arch/arm/mach-pxa/hx4700.c          |   33 ++++++--
 arch/arm/mach-pxa/magician.c        |   33 ++++++--
 drivers/regulator/Kconfig           |    8 --
 drivers/regulator/Makefile          |    1 -
 drivers/regulator/bq24022.c         |  162 -----------------------------------
 include/linux/regulator/bq24022.h   |   24 -----
 7 files changed, 55 insertions(+), 208 deletions(-)
 delete mode 100644 drivers/regulator/bq24022.c
 delete mode 100644 include/linux/regulator/bq24022.h


From 21cnbao at gmail.com  Tue Mar  6 21:18:31 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 7 Mar 2012 10:18:31 +0800
Subject: [PATCH v2] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <op.waoyg7dp3l0zgt@mpn-glaptop>
References: <1330931626-30855-1-git-send-email-Barry.Song@csr.com>
 <op.waoyg7dp3l0zgt@mpn-glaptop>
Message-ID: <CAGsJ_4znJqc8+yJ9+8fcmuZEsfF-y9dfoy6By-dd=wJwPvoJWQ@mail.gmail.com>

hi Michal,

2012/3/5 Michal Nazarewicz <mina86 at mina86.com>:
> On Mon, 05 Mar 2012 08:13:46 +0100, Barry Song <Barry.Song at csr.com> wrote:
>>
>> Any write request to /dev/cma_test will let the module to allocate memory
>> from
>> CMA, for example:
>>
>> 1st time
>> $ echo 1024 > /dev/cma_test
>> will require cma_test to request 1MB(1024KB)
>> 2nd time
>> $ echo 2048 > /dev/cma_test
>> will require cma_test to request 2MB(2048KB)
>>
>> Any read request to /dev/cma_test will let the module to free the 1st
>> valid
>> memory from CMA, for example:
>>
>> 1st time
>> $ cat /dev/cma_test
>> will require cma_test to free the 1MB allocated in the first write request
>> 2nd time
>> $ cat /dev/cma_test
>> will require cma_test to free the 2MB allocated in the second write
>> request
>>
>> Signed-off-by: Barry Song <Baohua.Song at csr.com>
>
>
>> diff --git a/tools/cma/cma_test.c b/tools/cma/cma_test.c
>> new file mode 100644
>> index 0000000..46af250
>> --- /dev/null
>> +++ b/tools/cma/cma_test.c
>> @@ -0,0 +1,140 @@
>> +/*
>> + * kernel module helper for testing CMA
>> + *
>> + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group
>> company.
>
>
> It's 2012.
>
>
>> + *
>> + * Licensed under GPLv2 or later.
>> + */
>> +
>> +#include <linux/device.h>
>> +#include <linux/dma-mapping.h>
>> +#include <linux/fs.h>
>> +#include <linux/miscdevice.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/spinlock.h>
>> +
>> +struct cma_allocation {
>> + ? ? ? struct list_head list;
>> + ? ? ? unsigned long size;
>> + ? ? ? dma_addr_t dma;
>> + ? ? ? void *virt;
>> +};
>> +
>> +static struct device *cma_dev;
>> +static LIST_HEAD(cma_allocations);
>> +static DEFINE_SPINLOCK(cma_lock);
>> +
>> +/*
>> + * any read request will free the 1st allocated coherent memory, eg.
>> + * cat /dev/cma_test
>> + */
>> +static ssize_t
>> +cma_test_read(struct file *file, char __user *buf, size_t count, loff_t
>> *ppos)
>> +{
>> + ? ? ? struct cma_allocation *alloc = NULL;
>> +
>> + ? ? ? spin_lock(&cma_lock);
>> + ? ? ? if (!list_empty(&cma_allocations)) {
>> + ? ? ? ? ? ? ? alloc = list_first_entry(&cma_allocations,
>> + ? ? ? ? ? ? ? ? ? ? ? struct cma_allocation, list);
>> + ? ? ? ? ? ? ? list_del(&alloc->list);
>> + ? ? ? }
>> + ? ? ? spin_unlock(&cma_lock);
>> +
>
>
> Come to think of it, how about putting:
>
> ? ? ? ?if (!alloc)
> ? ? ? ? ? ? ? ?return -EIDRM;

ok. make sense. "Identifier removed"

>
> here and then removing one indention level later:
>

agree.

>
>> + ? ? ? if (alloc) {
>> + ? ? ? ? ? ? ? dma_free_coherent(cma_dev, alloc->size, alloc->virt,
>> + ? ? ? ? ? ? ? ? ? ? ? alloc->dma);
>> +
>> + ? ? ? ? ? ? ? _dev_info(cma_dev, "free CM at virtual address: 0x%p dma
>> address: 0x%p size:%luKiB\n",
>
>
> This message seem overly long and ?0x? seem redundant. ?How about something
> like:
>
> ? ? ? ? ? ? ? ?_dev_info(cma_dev, "free: virt:%p dma:%p size:%luK\n",
>
> which has all the same information but is shorter?
>

ok. anyway it is trivial.

>
>> + ? ? ? ? ? ? ? ? ? ? ? alloc->virt, (void *)alloc->dma, alloc->size /
>> SZ_1K);
>> + ? ? ? ? ? ? ? kfree(alloc);
>> + ? ? ? }
>> +
>> + ? ? ? return 0;
>> +}
>> +
>> +/*
>> + * any write request will alloc a new coherent memory, eg.
>> + * echo 1024 > /dev/cma_test
>> + * will request 1024KiB by CMA
>> + */
>> +static ssize_t
>> +cma_test_write(struct file *file, const char __user *buf, size_t count,
>> loff_t *ppos)
>> +{
>> + ? ? ? struct cma_allocation *alloc;
>> + ? ? ? int ret;
>> +
>> + ? ? ? alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
>> + ? ? ? if (!alloc)
>> + ? ? ? ? ? ? ? return -ENOMEM;
>> +
>> + ? ? ? ret = kstrtoul_from_user(buf, count, 0, &alloc->size);
>> + ? ? ? if (ret)
>> + ? ? ? ? ? ? ? return ret;
>> +
>> + ? ? ? if (!alloc->size)
>> + ? ? ? ? ? ? ? return -EINVAL;
>> +
>> + ? ? ? if (alloc->size > (ULONG_MAX << PAGE_SHIFT))
>
>
> You've changed units from pages to KiBs and, I've just realised that, since
> dma_alloc_coherent accepts ?size_t? as argument, this should read:
>
> ? ? ? ?if (alloc->size > ~(size_t)0 / SZ_1K)
>

ok.

> (?<<? was in fact a bug in my code from the beginning.)
>
>> + ? ? ? ? ? ? ? return -EOVERFLOW;
>
>
> Most importantly, there was a memory leak in my original suggestion, and
> it got carried over to this patch. ?The above code should look
> something like that:
>
>
> ? ? ? ?ret = kstrtoul_from_user(buf, count, 0, &alloc->size);
> ? ? ? ?if (ret)
> ? ? ? ? ? ? ? ?return ret;
>
> ? ? ? ?if (!alloc->size)
> ? ? ? ? ? ? ? ?return -EINVAL;
>
> ? ? ? ?if (alloc->size > ~(size_t)0 / SZ_1K)
> ? ? ? ? ? ? ? ?return -EOVERFLOW;
>
>
> ? ? ? ?alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
> ? ? ? ?if (!alloc)
> ? ? ? ? ? ? ? ?return -ENOMEM;
>

in original codes, "kmalloc(sizeof *alloc, GFP_KERNEL);" is not freed.
better we define a temp size_t size

        kstrtoul_from_user(buf, count, 0, &size);
        ...
        if (!size)
                return -EINVAL;

        if (size > ~(size_t)0 / SZ_1K)
                return -EOVERFLOW;

        alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
        if (!alloc)
                return -ENOMEM;

       alloc->size = size;

>
>> + ? ? ? alloc->size *= SZ_1K;
>> + ? ? ? alloc->virt = dma_alloc_coherent(cma_dev, alloc->size,
>> + ? ? ? ? ? ? ? &alloc->dma, GFP_KERNEL);
>> +
>> + ? ? ? if (alloc->virt) {
>> + ? ? ? ? ? ? ? _dev_info(cma_dev, "allocate CM at virtual address: 0x%p"
>> + ? ? ? ? ? ? ? ? ? ? ? "address: 0x%p size:%luKiB\n", alloc->virt,
>
>
> Similarly to message earlier, how about:
>
> ? ? ? ? ? ? ? ?_dev_info(cma_dev, "alloc: virt:%p dma:%p size:%luK\n",
>
>
>> + ? ? ? ? ? ? ? ? ? ? ? (void *)alloc->dma, alloc->size / SZ_1K);
>> +
>> + ? ? ? ? ? ? ? spin_lock(&cma_lock);
>> + ? ? ? ? ? ? ? list_add_tail(&alloc->list, &cma_allocations);
>> + ? ? ? ? ? ? ? spin_unlock(&cma_lock);
>> +
>> + ? ? ? ? ? ? ? return count;
>> + ? ? ? } else {
>> + ? ? ? ? ? ? ? dev_err(cma_dev, "no mem in CMA area\n");
>> + ? ? ? ? ? ? ? kfree(alloc);
>> + ? ? ? ? ? ? ? return -ENOSPC;
>> + ? ? ? }
>> +}
>> +
>> +static const struct file_operations cma_test_fops = {
>> + ? ? ? .owner = ? ?THIS_MODULE,
>> + ? ? ? .read ?= ? ?cma_test_read,
>> + ? ? ? .write = ? ?cma_test_write,
>> +};
>> +
>> +static struct miscdevice cma_test_misc = {
>> + ? ? ? .name = "cma_test",
>> + ? ? ? .fops = &cma_test_fops,
>> +};
>> +
>> +static int __init cma_test_init(void)
>> +{
>> + ? ? ? int ret = 0;
>
>
> Drop ?= 0?, or better yet, combain this declaration with the next line.
>
>
>> +
>> + ? ? ? ret = misc_register(&cma_test_misc);
>> + ? ? ? if (unlikely(ret)) {
>> + ? ? ? ? ? ? ? pr_err("failed to register cma test misc device!\n");
>> + ? ? ? ? ? ? ? return ret;
>> + ? ? ? }
>> + ? ? ? cma_dev = cma_test_misc.this_device;
>> + ? ? ? cma_dev->coherent_dma_mask = ~0;
>> + ? ? ? _dev_info(cma_dev, "registered.\n");
>> +
>> + ? ? ? return ret;
>
>
> ? ? ? ?return 0;
>
>
>> +}
>> +module_init(cma_test_init);
>> +
>> +static void __exit cma_test_exit(void)
>> +{
>> + ? ? ? misc_deregister(&cma_test_misc);
>> +}
>> +module_exit(cma_test_exit);
>> +
>> +MODULE_LICENSE("GPL");
>> +MODULE_AUTHOR("Barry Song <Baohua.Song at csr.com>");
>> +MODULE_DESCRIPTION("kernel module to help the test of CMA");
>> +MODULE_ALIAS("CMA test");
>
>
> Can module alias contain spaces? ?I don't think this declaration even
> adds anything useful. ?cma_test? as module name should be good enough.

ok.

>
> --
> Best regards, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _ ? ? _
> .o. | Liege of Serenely Enlightened Majesty of ? ? ?o' \,=./ `o
> ..o | Computer Science, ?Micha? ?mina86? Nazarewicz ? ?(o o)
> ooo +----<email/xmpp: mpn at google.com>--------------ooO--(_)--Ooo--
>
-barry


From tony at atomide.com  Tue Mar  6 21:28:09 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 6 Mar 2012 18:28:09 -0800
Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulator
 for first instance
In-Reply-To: <87sjhlnq96.fsf@ti.com>
References: <1331080771-30687-1-git-send-email-khilman@ti.com>
 <20120307004405.GC12083@atomide.com> <87sjhlnq96.fsf@ti.com>
Message-ID: <20120307022809.GD12083@atomide.com>

* Kevin Hilman <khilman at ti.com> [120306 17:07]:
> Tony Lindgren <tony at atomide.com> writes:
> 
> > * Kevin Hilman <khilman at ti.com> [120306 16:07]:
> >> commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
> >> regulators) added regulators which are registered during
> >> gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
> >> than one instance of the SMSC911x and result in attempting to register
> >> the same regulator more than once which causes a panic().
> >> 
> >> Fix this by only registering the regulator when the platform_data id
> >> field is zero, indicating its the first instance.
> >> 
> >> Cc: Matt Porter <mporter at ti.com>
> >> Signed-off-by: Kevin Hilman <khilman at ti.com>
> >> ---
> >> Fix needed for v3.3.
> >> Applies on top of Tony's fixes branch.
> >> 
> >>  arch/arm/mach-omap2/gpmc-smsc911x.c |   11 +++++++----
> >>  1 file changed, 7 insertions(+), 4 deletions(-)
> >> 
> >> diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
> >> index bbb870c..4d6f1c6 100644
> >> --- a/arch/arm/mach-omap2/gpmc-smsc911x.c
> >> +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
> >> @@ -101,10 +101,13 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
> >>  
> >>  	gpmc_cfg = board_data;
> >>  
> >> -	ret = platform_device_register(&gpmc_smsc911x_regulator);
> >> -	if (ret < 0) {
> >> -		pr_err("Unable to register smsc911x regulators: %d\n", ret);
> >> -		return;
> >> +	if (!gpmc_cfg) {
> >
> > Shouldn't this be !gpmc_cfg->id instead..
> 
> doh, of course.  Updated patch below.

Thanks, applying into fixes.

Regards,

Tony


From ming.lei at canonical.com  Tue Mar  6 21:49:46 2012
From: ming.lei at canonical.com (Ming Lei)
Date: Wed, 7 Mar 2012 10:49:46 +0800
Subject: oprofile and ARM A9 hardware counter
In-Reply-To: <20120127155454.GH2347@mudshark.cambridge.arm.com>
References: <CACVXFVPDdyKf5TffT4OMt+tKeB09TU2RcvcyBV45hAK0qw+GEg@mail.gmail.com>
 <CAMsRxfJK9kcFkV=itJHpzuOXoZQkmjj1wh8Y789D3iOVstPMyQ@mail.gmail.com>
 <CAMsRxfKPm0dEaKDeSZQ=6jkpo4MeS=0XF6TsCj+BV54WbW_LtA@mail.gmail.com>
 <CACVXFVMgk7ykSX3GjzCNvUU0zMzNvGGuZMBpxBf7NRVk9EM7ig@mail.gmail.com>
 <CAMsRxfJWjwznJYujSvr0DfhNxtnJDVdfjXXpx34HUDBRtMvjqw@mail.gmail.com>
 <20120127121311.GB2347@mudshark.cambridge.arm.com>
 <yw1x1uqlnw1o.fsf@unicorn.mansr.com>
 <20120127132826.GD2347@mudshark.cambridge.arm.com>
 <CACVXFVPHpmPX9OdeYzzWjQ-qqs=9oYbL_og-_xJA2ypYNu0nRA@mail.gmail.com>
 <CAMsRxfJOAh1V7sMWxqCXADDB_eSAuxop1iYAGqXvLC_74Pfz1A@mail.gmail.com>
 <20120127155454.GH2347@mudshark.cambridge.arm.com>
Message-ID: <CACVXFVNExXcU473=m5QLZXAhpNsC3WZHrFa-=HzGdjMEy3seDg@mail.gmail.com>

Hi Will,

On Fri, Jan 27, 2012 at 11:54 PM, Will Deacon <will.deacon at arm.com> wrote:
> Ok. Note that on ARM the PMU generates a standard IRQ (i.e. not an NMI) so
> you may miss samples if they occur during critical kernel sections (and if
> you look at a profile, spin_unlock_irqrestore will be quite high).

Also looks no any irq handler functions can be observed at a profile even
though they may be run at a very high frequency.

So could we configure ARM PMU interrupt as FIQ to address the above issues?

thanks
--
Ming Lei


From Barry.Song at csr.com  Tue Mar  6 22:14:58 2012
From: Barry.Song at csr.com (Barry Song)
Date: Wed, 7 Mar 2012 11:14:58 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper to test
 CMA
Message-ID: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

Any write request to /dev/cma_test will let the module to allocate memory from
CMA, for example:

1st time
$ echo 1024 > /dev/cma_test
will require cma_test to request 1MB(1024KB)
2nd time
$ echo 2048 > /dev/cma_test
will require cma_test to request 2MB(2048KB)

Any read request to /dev/cma_test will let the module to free the 1st valid
memory from CMA, for example:

1st time
$ cat /dev/cma_test
will require cma_test to free the 1MB allocated in the first write request
2nd time
$ cat /dev/cma_test
will require cma_test to free the 2MB allocated in the second write request

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 -v2:
 some minor cleanups by Michal Nazarewicz

 tools/cma/Makefile   |   13 +++++
 tools/cma/cma_test.c |  140 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 153 insertions(+), 0 deletions(-)
 create mode 100644 tools/cma/Makefile
 create mode 100644 tools/cma/cma_test.c

diff --git a/tools/cma/Makefile b/tools/cma/Makefile
new file mode 100644
index 0000000..d15c2c0
--- /dev/null
+++ b/tools/cma/Makefile
@@ -0,0 +1,13 @@
+# Kernel modules
+#
+# To compile for ARM:
+# make ARCH=arm CC=arm-none-linux-gnueabi-gcc
+#
+obj-m	+= cma_test.o
+
+build: kernel_modules
+
+kernel_modules:
+	${MAKE} -C $(CURDIR)/../.. M=$(CURDIR)
+clean:
+	${MAKE} -C $(CURDIR)/../.. M=$(CURDIR) clean
diff --git a/tools/cma/cma_test.c b/tools/cma/cma_test.c
new file mode 100644
index 0000000..40219ad
--- /dev/null
+++ b/tools/cma/cma_test.c
@@ -0,0 +1,140 @@
+/*
+ * kernel module helper for testing CMA
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+struct cma_allocation {
+	struct list_head list;
+	size_t size;
+	dma_addr_t dma;
+	void *virt;
+};
+
+static struct device *cma_dev;
+static LIST_HEAD(cma_allocations);
+static DEFINE_SPINLOCK(cma_lock);
+
+/*
+ * any read request will free the 1st allocated coherent memory, eg.
+ * cat /dev/cma_test
+ */
+static ssize_t
+cma_test_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
+{
+	struct cma_allocation *alloc = NULL;
+
+	spin_lock(&cma_lock);
+	if (!list_empty(&cma_allocations)) {
+		alloc = list_first_entry(&cma_allocations,
+			struct cma_allocation, list);
+		list_del(&alloc->list);
+	}
+	spin_unlock(&cma_lock);
+
+	if (!alloc)
+		return -EIDRM;
+
+	dma_free_coherent(cma_dev, alloc->size, alloc->virt,
+		alloc->dma);
+
+	_dev_info(cma_dev, "free: CM virt: %p dma: %p size:%uK\n",
+		alloc->virt, (void *)alloc->dma, alloc->size / SZ_1K);
+	kfree(alloc);
+
+	return 0;
+}
+
+/*
+ * any write request will alloc a new coherent memory, eg.
+ * echo 1024 > /dev/cma_test
+ * will request 1024KiB by CMA
+ */
+static ssize_t
+cma_test_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
+{
+	struct cma_allocation *alloc;
+	size_t size;
+	int ret;
+
+	ret = kstrtouint_from_user(buf, count, 0, &size);
+	if (ret)
+		return ret;
+
+	if (!size)
+		return -EINVAL;
+
+	if (size > ~(size_t)0 / SZ_1K)
+		return -EOVERFLOW;
+
+	alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
+	if (!alloc)
+		return -ENOMEM;
+
+	alloc->size = size * SZ_1K;
+	alloc->virt = dma_alloc_coherent(cma_dev, alloc->size,
+		&alloc->dma, GFP_KERNEL);
+
+	if (alloc->virt) {
+		_dev_info(cma_dev, "alloc: virt: %p dma: %p size: %uK\n",
+			alloc->virt, (void *)alloc->dma, size);
+
+		spin_lock(&cma_lock);
+		list_add_tail(&alloc->list, &cma_allocations);
+		spin_unlock(&cma_lock);
+
+		return count;
+	} else {
+		dev_err(cma_dev, "no mem in CMA area\n");
+		kfree(alloc);
+		return -ENOSPC;
+	}
+}
+
+static const struct file_operations cma_test_fops = {
+	.owner =    THIS_MODULE,
+	.read  =    cma_test_read,
+	.write =    cma_test_write,
+};
+
+static struct miscdevice cma_test_misc = {
+	.name = "cma_test",
+	.fops = &cma_test_fops,
+};
+
+static int __init cma_test_init(void)
+{
+	int ret = misc_register(&cma_test_misc);
+
+	if (unlikely(ret)) {
+		pr_err("failed to register cma test misc device!\n");
+		return ret;
+	}
+	cma_dev = cma_test_misc.this_device;
+	cma_dev->coherent_dma_mask = ~0;
+	_dev_info(cma_dev, "registered.\n");
+
+	return 0;
+}
+module_init(cma_test_init);
+
+static void __exit cma_test_exit(void)
+{
+	misc_deregister(&cma_test_misc);
+}
+module_exit(cma_test_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Barry Song <Baohua.Song at csr.com>");
+MODULE_DESCRIPTION("kernel module to help the test of CMA");
+MODULE_ALIAS("cma_test");
-- 
1.7.1



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From sjg at chromium.org  Tue Mar  6 22:16:43 2012
From: sjg at chromium.org (Simon Glass)
Date: Tue, 6 Mar 2012 19:16:43 -0800
Subject: [PATCH 0/3] arm: tegra: dts: USB Updates for Tegra legacy mode /
 OTG
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF178E5D2FF5@HQMAIL01.nvidia.com>
References: <1328288172-8059-1-git-send-email-sjg@chromium.org>
 <74CDBE0F657A3D45AFBB94109FB122FF178E5D2FF5@HQMAIL01.nvidia.com>
Message-ID: <CAPnjgZ1rXEGbi3m3HeWiUxG_TbmUug0C0QZgb7_9Eiz-xPMHwg@mail.gmail.com>

+Olof

Hi,

On Fri, Feb 3, 2012 at 11:59 AM, Stephen Warren <swarren at nvidia.com> wrote:
> Simon Glass wrote at riday, February 03, 2012 9:56 AM:
>> This little series brings in some bindings that seem useful for U-Boot.
>>
>> I am working mostly in U-Boot, but since there is no shared .dts repo
>> I was asked to commit these changes to the kernel. I do not propose to
>> update the Linux USB drivers to match.
>
> I think the series looks reasonable, so:
>
> Acked-by: Stephen Warren <swarren at nvidia.com<>
>
> (I note that the kernel's USB driver for USB1 doesn't attempt to clear
> legacy mode; I wonder how we're getting away with that. Perhaps it's
> only been tested with a bootloader that's already cleared legacy mode)
>

How does this series get picked up, please?

Regards,
Simon

> --
> nvpublic
>


From robherring2 at gmail.com  Tue Mar  6 22:36:22 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue,  6 Mar 2012 21:36:22 -0600
Subject: [PATCH] ARM: ebsa110: use runtime ioremap hook
In-Reply-To: <alpine.LFD.2.02.1203061704180.31242@xanadu.home>
References: <alpine.LFD.2.02.1203061704180.31242@xanadu.home>
Message-ID: <1331091382-21149-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Convert ebsa110 platforms to use run-time ioremap hook instead of the
compile time hook.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---

This fixes the missing caller ptr.

Rob

 arch/arm/mach-ebsa110/core.c            |   15 +++++++++++++++
 arch/arm/mach-ebsa110/include/mach/io.h |    9 ---------
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 804c912..b049edb 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -119,6 +119,20 @@ static void __init ebsa110_map_io(void)
 	iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
 }
 
+static void __iomem *ebsa110_ioremap_caller(unsigned long cookie, size_t size,
+					    unsigned int flags, void *caller)
+{
+	return (void __iomem *)cookie;
+}
+
+static void ebsa110_iounmap(volatile void __iomem *io_addr)
+{}
+
+static void __init ebsa110_init_early(void)
+{
+	arch_ioremap_caller = ebsa110_ioremap_caller;
+	arch_iounmap = ebsa110_iounmap;
+}
 
 #define PIT_CTRL		(PIT_BASE + 0x0d)
 #define PIT_T2			(PIT_BASE + 0x09)
@@ -315,6 +329,7 @@ MACHINE_START(EBSA110, "EBSA110")
 	.reserve_lp2	= 1,
 	.restart_mode	= 's',
 	.map_io		= ebsa110_map_io,
+	.init_early	= ebsa110_init_early,
 	.init_irq	= ebsa110_init_irq,
 	.timer		= &ebsa110_timer,
 	.restart	= ebsa110_restart,
diff --git a/arch/arm/mach-ebsa110/include/mach/io.h b/arch/arm/mach-ebsa110/include/mach/io.h
index 44679db..11bb079 100644
--- a/arch/arm/mach-ebsa110/include/mach/io.h
+++ b/arch/arm/mach-ebsa110/include/mach/io.h
@@ -62,15 +62,6 @@ void __writel(u32 val, void __iomem *addr);
 #define writew(v,b)		__writew(v,b)
 #define writel(v,b)		__writel(v,b)
 
-static inline void __iomem *__arch_ioremap(unsigned long cookie, size_t size,
-					   unsigned int flags)
-{
-	return (void __iomem *)cookie;
-}
-
-#define __arch_ioremap		__arch_ioremap
-#define __arch_iounmap(cookie)	do { } while (0)
-
 extern void insb(unsigned int port, void *buf, int sz);
 extern void insw(unsigned int port, void *buf, int sz);
 extern void insl(unsigned int port, void *buf, int sz);
-- 
1.7.5.4



From rob.lee at linaro.org  Tue Mar  6 22:42:18 2012
From: rob.lee at linaro.org (Robert Lee)
Date: Tue,  6 Mar 2012 21:42:18 -0600
Subject: [RFC PATCH] cpuidle: avoid unnecessary expensive governor processing
Message-ID: <1331091738-26322-1-git-send-email-rob.lee@linaro.org>

There a few cases when a platform's cpuidle_device will only have one
cpuidle state.  e.g., when a single idle state system uses cpuidle
to provide sysfs staticstics for profiling (powertop, etc).  This can
also be the case for coupled smp system implementations that keep
all but one cpuidle_device at a state_count of 1, but they still want
to export idle statistics for these states using cpuidle.

Signed-off-by: Robert Lee <rob.lee at linaro.org>
---
 drivers/cpuidle/governors/ladder.c |    7 +++++--
 drivers/cpuidle/governors/menu.c   |    7 +++++--
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/cpuidle/governors/ladder.c b/drivers/cpuidle/governors/ladder.c
index b6a09ea..13abdba 100644
--- a/drivers/cpuidle/governors/ladder.c
+++ b/drivers/cpuidle/governors/ladder.c
@@ -71,8 +71,11 @@ static int ladder_select_state(struct cpuidle_driver *drv,
 	int last_residency, last_idx = ldev->last_state_idx;
 	int latency_req = pm_qos_request(PM_QOS_CPU_DMA_LATENCY);
 
-	/* Special case when user has set very strict latency requirement */
-	if (unlikely(latency_req == 0)) {
+	/*
+	 * Special case when user has set very strict latency requirement or
+	 * there is currently only one state for this device.
+	 */
+	if ((latency_req == 0) || (dev->state_count == 1)) {
 		ladder_do_selection(ldev, last_idx, 0);
 		return 0;
 	}
diff --git a/drivers/cpuidle/governors/menu.c b/drivers/cpuidle/governors/menu.c
index ad09526..80eb606 100644
--- a/drivers/cpuidle/governors/menu.c
+++ b/drivers/cpuidle/governors/menu.c
@@ -249,8 +249,11 @@ static int menu_select(struct cpuidle_driver *drv, struct cpuidle_device *dev)
 	data->last_state_idx = 0;
 	data->exit_us = 0;
 
-	/* Special case when user has set very strict latency requirement */
-	if (unlikely(latency_req == 0))
+	/*
+	 * Special case when user has set very strict latency requirement or
+	 * there is currently only one state for this device.
+	 */
+	if ((latency_req == 0) || (dev->state_count == 1))
 		return 0;
 
 	/* determine the expected residency time, round up */
-- 
1.7.1



From jason at lakedaemon.net  Tue Mar  6 22:44:44 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:44 +0000
Subject: [PATCH 03/14] ARM: kirkwood: add dreamplug (fdt) support.
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <dc7b6bf6c75cfd73fa501480a3169e311d101e54.1331090356.git.jason@lakedaemon.net>

Initially, copied guruplug-setup.c and did s/guruplug/dreamplug/g.
Then, switched to SPI based NOR flash.

After talking to Arnd Bergman, chose an incremental approach to adding
devicetree support.  First, we use the dtb to tell us we are on the
dreamplug, then we gradually port over drivers.

Driver porting will start with the uart (see next patch), and progress
from there.  Possibly, spi/flash/partitions will be next.

When done, board-dt.c will no longer be dreamplug specific, and dt's can
be made for the other kirkwood boards.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Nicolas Pitre <nico at linaro.org>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---

Changes from previous version:

* s/marvell,/mrvl,/g for compatible properties

 arch/arm/boot/dts/kirkwood-dreamplug.dts |   18 +++
 arch/arm/boot/dts/kirkwood.dtsi          |    6 +
 arch/arm/mach-kirkwood/Kconfig           |   14 +++
 arch/arm/mach-kirkwood/Makefile          |    1 +
 arch/arm/mach-kirkwood/Makefile.boot     |    2 +
 arch/arm/mach-kirkwood/board-dt.c        |  182 ++++++++++++++++++++++++++++++
 6 files changed, 223 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-dreamplug.dts
 create mode 100644 arch/arm/boot/dts/kirkwood.dtsi
 create mode 100644 arch/arm/mach-kirkwood/board-dt.c

diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
new file mode 100644
index 0000000..578806d
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "Globalscale Technologies Dreamplug";
+	compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
new file mode 100644
index 0000000..702b955
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -0,0 +1,6 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "mrvl,kirkwood";
+};
+
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7fc603b..90ceab7 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -44,6 +44,20 @@ config MACH_GURUPLUG
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell GuruPlug Reference Board.
 
+config ARCH_KIRKWOOD_DT
+	bool "Marvell Kirkwood Flattened Device Tree"
+	select USE_OF
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell Kirkwood using flattened device tree.
+
+config MACH_DREAMPLUG_DT
+	bool "Marvell DreamPlug (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell DreamPlug (Flattened Device Tree).
+
 config MACH_TS219
 	bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
 	help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 5dcaa81..acbc5e1 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_MACH_NET5BIG_V2)		+= netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_T5325)		+= t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
+obj-$(CONFIG_ARCH_KIRKWOOD_DT)		+= board-dt.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 760a0ef..16f9385 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -1,3 +1,5 @@
    zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
new file mode 100644
index 0000000..76392af
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright 2012 (C), Jason Cooper <jason at lakedaemon.net>
+ *
+ * arch/arm/mach-kirkwood/board-dt.c
+ *
+ * Marvell DreamPlug Reference Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct of_device_id kirkwood_dt_match_table[] __initdata = {
+	{ .compatible = "simple-bus", },
+	{ }
+};
+
+struct mtd_partition dreamplug_partitions[] = {
+	{
+		.name	= "u-boot",
+		.size	= SZ_512K,
+		.offset = 0,
+	},
+	{
+		.name	= "u-boot env",
+		.size	= SZ_64K,
+		.offset = SZ_512K + SZ_512K,
+	},
+	{
+		.name	= "dtb",
+		.size	= SZ_64K,
+		.offset = SZ_512K + SZ_512K + SZ_512K,
+	},
+};
+
+static const struct flash_platform_data dreamplug_spi_slave_data = {
+	.type		= "mx25l1606e",
+	.name		= "spi_flash",
+	.parts		= dreamplug_partitions,
+	.nr_parts	= ARRAY_SIZE(dreamplug_partitions),
+};
+
+static struct spi_board_info __initdata dreamplug_spi_slave_info[] = {
+	{
+		.modalias	= "m25p80",
+		.platform_data	= &dreamplug_spi_slave_data,
+		.irq		= -1,
+		.max_speed_hz	= 50000000,
+		.bus_num	= 0,
+		.chip_select	= 0,
+	},
+};
+
+static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
+};
+
+static struct mv_sata_platform_data dreamplug_sata_data = {
+	.n_ports	= 1,
+};
+
+static struct mvsdio_platform_data dreamplug_mvsdio_data = {
+	/* unfortunately the CD signal has not been connected */
+};
+
+static struct gpio_led dreamplug_led_pins[] = {
+	{
+		.name			= "dreamplug:blue:bluetooth",
+		.gpio			= 47,
+		.active_low		= 1,
+	},
+	{
+		.name			= "dreamplug:green:wifi",
+		.gpio			= 48,
+		.active_low		= 1,
+	},
+	{
+		.name			= "dreamplug:green:wifi_ap",
+		.gpio			= 49,
+		.active_low		= 1,
+	},
+};
+
+static struct gpio_led_platform_data dreamplug_led_data = {
+	.leds		= dreamplug_led_pins,
+	.num_leds	= ARRAY_SIZE(dreamplug_led_pins),
+};
+
+static struct platform_device dreamplug_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &dreamplug_led_data,
+	}
+};
+
+static unsigned int dreamplug_mpp_config[] __initdata = {
+	MPP0_SPI_SCn,
+	MPP1_SPI_MOSI,
+	MPP2_SPI_SCK,
+	MPP3_SPI_MISO,
+	MPP47_GPIO,	/* Bluetooth LED */
+	MPP48_GPIO,	/* Wifi LED */
+	MPP49_GPIO,	/* Wifi AP LED */
+	0
+};
+
+static void __init dreamplug_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_mpp_conf(dreamplug_mpp_config);
+
+	kirkwood_uart0_init();
+
+	spi_register_board_info(dreamplug_spi_slave_info,
+				ARRAY_SIZE(dreamplug_spi_slave_info));
+	kirkwood_spi_init();
+
+	kirkwood_ehci_init();
+	kirkwood_ge00_init(&dreamplug_ge00_data);
+	kirkwood_ge01_init(&dreamplug_ge01_data);
+	kirkwood_sata_init(&dreamplug_sata_data);
+	kirkwood_sdio_init(&dreamplug_mvsdio_data);
+
+	platform_device_register(&dreamplug_leds);
+}
+
+static void __init kirkwood_dt_init(void)
+{
+	kirkwood_init();
+
+	if (of_machine_is_compatible("globalscale,dreamplug"))
+		dreamplug_init();
+
+	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
+}
+
+static const char *kirkwood_dt_board_compat[] = {
+	"globalscale,dreamplug",
+	NULL
+};
+
+DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
+	/* Maintainer: Jason Cooper <jason at lakedaemon.net> */
+	.map_io		= kirkwood_map_io,
+	.init_early	= kirkwood_init_early,
+	.init_irq	= kirkwood_init_irq,
+	.timer		= &kirkwood_timer,
+	.init_machine	= kirkwood_dt_init,
+	.restart	= kirkwood_restart,
+	.dt_compat	= kirkwood_dt_board_compat,
+MACHINE_END
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:41 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:41 +0000
Subject: [PATCH 0/14 v3] ARM: kirkwood: fdt: convert kirkwood to fdt
In-Reply-To: <cover.1330625877.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
Message-ID: <cover.1331090356.git.jason@lakedaemon.net>

This series begins the process of converting all of the drivers initialized
from kirkwood_init() to devicetree.

The first two patches are code cleanup from Andrew Lunn.

The rest of the series are devicetree bindings for drivers that don't use tclk.
These should be safe to merge as they won't interfere with the clk/clkdev work
Andrew Lunn is working on.

Several of these are patches created by Michael Walle several months ago and he
has agreed to let me usher them in.  I've changed them in minor ways to conform
with advice I've been given over the past several weeks.

Overall changes since v2:

	- added Andrew Lunn's cleanup patches
	- reshuffled to more logical order
	- wrapped all struct of_device_id[]'s in #ifdef CONFIG_OF
	- s/marvell,/mrvl,/g
	- added orion-ehci
	- added mv_sata
	- prevent clocks from gating when booting from devicetree

Drivers yet to be converted are:

	orion-spi: uses tclk
	orion-wdt: uses tclk
	mvsdio:    uses tclk
	i2c:       uses freq_m/freq_n, not sure if that should use clk/clkdev
	mv_xor:    haven't figured out howto do shared resources/dma in fdt
	ge0/ge1:   haven't looked at it yet
	nand:      not needed for dreamplug, haven't looked yet

Please be aware that this is a complete reshuffle of the whole series and is
based purely against v3.3-rc3.

Interested folks can pull from:

git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt


Andrew Lunn (2):
  ARM: orion: spi: remove enable_clock_fix which is not used
  ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data.

Jason Cooper (9):
  ARM: kirkwood: add dreamplug (fdt) support.
  ARM: kirkwood: fdt: absorb kirkwood_init()
  ARM: kirkwood: add interrupt controller to devicetree.
  ARM: kirkwood: convert uart0 to devicetree.
  ARM: kirkwood: rtc-mv devicetree bindings
  ARM: kirkwood: use devicetree for rtc-mv
  ARM: kirkwood: mv_cesa devicetree support.
  ARM: kirkwood: use devicetree for orion-ehci
  ARM: kirkwood: use devicetree to init sata_mv

Michael Walle (3):
  ARM: kirkwood: mv_cesa devicetree bindings
  ARM: kirkwood: ehci-orion: add device tree binding
  ARM: kirkwood: sata_mv: add device tree binding

 .../devicetree/bindings/crypto/mv_cesa.txt         |   18 ++
 .../devicetree/bindings/usb/ehci-orion.txt         |    5 +
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |   39 ++++
 arch/arm/boot/dts/kirkwood.dtsi                    |   26 +++
 arch/arm/mach-kirkwood/Kconfig                     |   14 ++
 arch/arm/mach-kirkwood/Makefile                    |    1 +
 arch/arm/mach-kirkwood/Makefile.boot               |    2 +
 arch/arm/mach-kirkwood/board-dt.c                  |  206 ++++++++++++++++++++
 arch/arm/mach-kirkwood/common.c                    |   41 ++++-
 arch/arm/mach-kirkwood/common.h                    |    6 +
 arch/arm/plat-orion/include/plat/audio.h           |    1 -
 drivers/ata/sata_mv.c                              |   18 ++-
 drivers/crypto/mv_cesa.c                           |   13 ++
 drivers/rtc/rtc-mv.c                               |    9 +
 drivers/spi/spi-orion.c                            |    5 -
 drivers/usb/host/ehci-orion.c                      |   50 +++++-
 include/linux/spi/orion_spi.h                      |    1 -
 17 files changed, 437 insertions(+), 18 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/mv_cesa.txt
 create mode 100644 Documentation/devicetree/bindings/usb/ehci-orion.txt
 create mode 100644 arch/arm/boot/dts/kirkwood-dreamplug.dts
 create mode 100644 arch/arm/boot/dts/kirkwood.dtsi
 create mode 100644 arch/arm/mach-kirkwood/board-dt.c

-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:46 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:46 +0000
Subject: [PATCH 05/14] ARM: kirkwood: add interrupt controller to devicetree.
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <c27a2b2c176940d153f2659e1a64f9349fbdb9c1.1331090356.git.jason@lakedaemon.net>

Based on work by Michael Walle (commit a952154).

Used just the intc portion of the patch, fixed the register address, and
used of_find_compatible_node() instead.

Signed-off-by: Michael Walle <michael at walle.cc>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/boot/dts/kirkwood.dtsi   |    9 ++++++++-
 arch/arm/mach-kirkwood/board-dt.c |    7 +++++++
 2 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 702b955..7896a1d 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -2,5 +2,12 @@
 
 / {
 	compatible = "mrvl,kirkwood";
-};
+	interrupt-parent = <&intc>;
 
+	intc: interrupt-controller at fed20200 {
+		compatible = "mrvl,orion-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0xfed20200 0x20>;
+	};
+};
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index f514b42..f9f446b 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/irqdomain.h>
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
@@ -159,6 +160,8 @@ static void __init dreamplug_init(void)
 
 static void __init kirkwood_dt_init(void)
 {
+	struct device_node *node;
+
 	pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
 
 	/*
@@ -175,6 +178,10 @@ static void __init kirkwood_dt_init(void)
 	kirkwood_l2_init();
 #endif
 
+	node = of_find_compatible_node(NULL, NULL, "mrvl,orion-intc");
+	if (node)
+		irq_domain_add_simple(node, 0);
+
 	/* internal devices that every board has */
 	kirkwood_rtc_init();
 	kirkwood_wdt_init();
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:47 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:47 +0000
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <80fb8cef577eee14364e95009f7a590fd9056ee3.1331090356.git.jason@lakedaemon.net>

This uart is the primary console for the dreamplug.  Removed
kirkwood_uart0_init() call from board-dt.c.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Nicolas Pitre <nico at linaro.org>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/boot/dts/kirkwood-dreamplug.dts |    7 +++++++
 arch/arm/mach-kirkwood/board-dt.c        |    2 --
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 578806d..ebb2c87 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -15,4 +15,11 @@
 		bootargs = "console=ttyS0,115200n8 earlyprintk";
 	};
 
+	serial at f1012000 {
+		compatible = "ns16550a";
+		reg = <0xf1012000 0xff>;
+		reg-shift = <2>;
+		interrupts = <33>;
+		clock-frequency = <200000000>;
+	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index f9f446b..b55d25b 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -143,8 +143,6 @@ static void __init dreamplug_init(void)
 	 */
 	kirkwood_mpp_conf(dreamplug_mpp_config);
 
-	kirkwood_uart0_init();
-
 	spi_register_board_info(dreamplug_spi_slave_info,
 				ARRAY_SIZE(dreamplug_spi_slave_info));
 	kirkwood_spi_init();
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:43 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:43 +0000
Subject: [PATCH 02/14] ARM: Kirkwood: Remove tclk from
 kirkwood_asoc_platform_data.
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <86ba431c57ae2f9172bdd92f69fd7a0938e4a374.1331090356.git.jason@lakedaemon.net>

From: Andrew Lunn <andrew at lunn.ch>

It is not used anywhere in the sound driver.

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/mach-kirkwood/common.c          |    1 -
 arch/arm/plat-orion/include/plat/audio.h |    1 -
 2 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index cc15426..eacf7f5 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -449,7 +449,6 @@ void __init kirkwood_init(void)
 {
 	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
 		kirkwood_id(), kirkwood_tclk);
-	kirkwood_i2s_data.tclk = kirkwood_tclk;
 
 	/*
 	 * Disable propagation of mbus errors to the CPU local bus,
diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h
index 885f8ab..d6a55bd 100644
--- a/arch/arm/plat-orion/include/plat/audio.h
+++ b/arch/arm/plat-orion/include/plat/audio.h
@@ -2,7 +2,6 @@
 #define __PLAT_AUDIO_H
 
 struct kirkwood_asoc_platform_data {
-	u32 tclk;
 	int burst;
 };
 #endif
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:48 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:48 +0000
Subject: [PATCH 07/14] ARM: kirkwood: rtc-mv devicetree bindings
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <bb4ab565bd8506f6ac126571f46fc3b26178821f.1331090356.git.jason@lakedaemon.net>

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes from previous version:

* s/marvell,/mrvl,/g for compatible properties
* split into binding patch and a use patch.

 drivers/rtc/rtc-mv.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c
index 768e2ed..0dd8421 100644
--- a/drivers/rtc/rtc-mv.c
+++ b/drivers/rtc/rtc-mv.c
@@ -12,6 +12,7 @@
 #include <linux/bcd.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/delay.h>
 #include <linux/gfp.h>
 #include <linux/module.h>
@@ -294,11 +295,19 @@ static int __exit mv_rtc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id rtc_mv_of_match_table[] = {
+	{ .compatible = "mrvl,orion-rtc", },
+	{}
+};
+#endif
+
 static struct platform_driver mv_rtc_driver = {
 	.remove		= __exit_p(mv_rtc_remove),
 	.driver		= {
 		.name	= "rtc-mv",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(rtc_mv_of_match_table),
 	},
 };
 
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:42 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:42 +0000
Subject: [PATCH 01/14] ARM: orion: spi: remove enable_clock_fix which is not
 used
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <b0fe0cfb7e76a869a8ba7f7344de75eb122e206c.1331090356.git.jason@lakedaemon.net>

From: Andrew Lunn <andrew at lunn.ch>

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 drivers/spi/spi-orion.c       |    5 -----
 include/linux/spi/orion_spi.h |    1 -
 2 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index 13448c8..e496f79 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -359,11 +359,6 @@ static int orion_spi_setup(struct spi_device *spi)
 
 	orion_spi = spi_master_get_devdata(spi->master);
 
-	/* Fix ac timing if required.   */
-	if (orion_spi->spi_info->enable_clock_fix)
-		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
-				  (1 << 14));
-
 	if ((spi->max_speed_hz == 0)
 			|| (spi->max_speed_hz > orion_spi->max_speed))
 		spi->max_speed_hz = orion_spi->max_speed;
diff --git a/include/linux/spi/orion_spi.h b/include/linux/spi/orion_spi.h
index decf6d8..b4d9fa6 100644
--- a/include/linux/spi/orion_spi.h
+++ b/include/linux/spi/orion_spi.h
@@ -11,7 +11,6 @@
 
 struct orion_spi_info {
 	u32	tclk;		/* no <linux/clk.h> support yet */
-	u32	enable_clock_fix;
 };
 
 
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:49 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:49 +0000
Subject: [PATCH 08/14] ARM: kirkwood: use devicetree for rtc-mv
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <146e96ef8a8649767b3beb49ff39a260e75f234a.1331090356.git.jason@lakedaemon.net>

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes from previous version:

* s/marvell,/mrvl,/g for compatible properties
* split into binding patch and a use patch.

 arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
 arch/arm/mach-kirkwood/board-dt.c |    1 -
 arch/arm/mach-kirkwood/common.c   |    2 +-
 arch/arm/mach-kirkwood/common.h   |    1 -
 4 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 7896a1d..5960a8e 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -10,4 +10,10 @@
 		#interrupt-cells = <1>;
 		reg = <0xfed20200 0x20>;
 	};
+
+	rtc at f1010300 {
+		compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc";
+		reg = <0xf1010300 0x1f>;
+		interrupts = <53>;
+	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index b55d25b..deea565 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -181,7 +181,6 @@ static void __init kirkwood_dt_init(void)
 		irq_domain_add_simple(node, 0);
 
 	/* internal devices that every board has */
-	kirkwood_rtc_init();
 	kirkwood_wdt_init();
 	kirkwood_xor0_init();
 	kirkwood_xor1_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index ae90f60..ef45244 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -162,7 +162,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-void __init kirkwood_rtc_init(void)
+static void __init kirkwood_rtc_init(void)
 {
 	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index c382447..ca08826 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -53,7 +53,6 @@ void kirkwood_restart(char, const char *);
 
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-void kirkwood_rtc_init(void);
 void kirkwood_wdt_init(void);
 void kirkwood_xor0_init(void);
 void kirkwood_xor1_init(void);
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:50 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:50 +0000
Subject: [PATCH 09/14] ARM: kirkwood: mv_cesa devicetree bindings
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <65fc66fea1c3d768f27eb8613518ae2c8ae74e40.1331090356.git.jason@lakedaemon.net>

From: Michael Walle <michael at walle.cc>

Written by Michael Walle, modified by Jason Cooper to use Marvell ticker
symbol in compatible property.  Also, changed patch subject to conform
to standard convention.

Signed-off-by: Michael Walle <michael at walle.cc>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes from previous version:

* s/marvell,/mrvl,/g for compatible properties
* split into binding patch and a use patch.

 .../devicetree/bindings/crypto/mv_cesa.txt         |   18 ++++++++++++++++++
 drivers/crypto/mv_cesa.c                           |   13 +++++++++++++
 2 files changed, 31 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/mv_cesa.txt

diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt
new file mode 100644
index 0000000..aa7135b
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/mv_cesa.txt
@@ -0,0 +1,18 @@
+Marvell Cryptographic Engines And Security Accelerator
+
+Required properties:
+- compatible : should be "mrvl,orion-crypto"
+- reg : base physical address of the engine and length of memory mapped
+        region, followed by base physical address of sram and its memory
+		length
+- interrupts : interrupt number
+
+Examples:
+
+crypto at f1030000 {
+	compatible = "mrvl,orion-crypto";
+	reg = <0xf1030000 0x10000
+	       0xf5000000 0x800>;    /* sram */
+	interrupts = <22>;
+};
+
diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c
index 597235a..457f69f 100644
--- a/drivers/crypto/mv_cesa.c
+++ b/drivers/crypto/mv_cesa.c
@@ -18,6 +18,7 @@
 #include <linux/module.h>
 #include <crypto/internal/hash.h>
 #include <crypto/sha.h>
+#include <linux/of_platform.h>
 
 #include "mv_cesa.h"
 
@@ -1000,6 +1001,8 @@ static int mv_probe(struct platform_device *pdev)
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 	if (!res)
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
 		return -ENXIO;
 
 	cp = kzalloc(sizeof(*cp), GFP_KERNEL);
@@ -1015,6 +1018,8 @@ static int mv_probe(struct platform_device *pdev)
 	}
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
+	if (!res)
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 	if (!res) {
 		ret = -ENXIO;
 		goto err_unmap_reg;
@@ -1118,12 +1123,20 @@ static int mv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id mv_cesa_dt_ids[] = {
+	{ .compatible = "mrvl,orion-crypto", },
+	{},
+};
+#endif
+
 static struct platform_driver marvell_crypto = {
 	.probe		= mv_probe,
 	.remove		= mv_remove,
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "mv_crypto",
+		.of_match_table = of_match_ptr(mv_cesa_dt_ids),
 	},
 };
 MODULE_ALIAS("platform:mv_crypto");
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:51 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:51 +0000
Subject: [PATCH 10/14] ARM: kirkwood: mv_cesa devicetree support.
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <4a6df8e03abfa36901103583376b3c33f703559b.1331090356.git.jason@lakedaemon.net>

Based on work by Michael Walle (commit a952154).

Used the crypto portion of the patch, integrated with board-dt.c

Signed-off-by: Michael Walle <michael at walle.cc>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes from previous version:

* s/marvell,/mrvl,/g for compatible properties
* split into binding patch and a use patch.
* make sure clock doesn't get disabled when booting fdt

 arch/arm/boot/dts/kirkwood.dtsi   |    7 +++++++
 arch/arm/mach-kirkwood/board-dt.c |    1 -
 arch/arm/mach-kirkwood/common.c   |   14 +++++++++++++-
 arch/arm/mach-kirkwood/common.h   |    1 -
 4 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 5960a8e..a1634ae 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -16,4 +16,11 @@
 		reg = <0xf1010300 0x1f>;
 		interrupts = <53>;
 	};
+
+	crypto at f1030000 {
+		compatible = "mrvl,kirkwood-crypto", "mrvl,orion-crypto";
+		reg = <0xf1030000 0x10000>,
+		      <0xf5000000 0x800>;
+		interrupts = <22>;
+	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index deea565..638f261 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -184,7 +184,6 @@ static void __init kirkwood_dt_init(void)
 	kirkwood_wdt_init();
 	kirkwood_xor0_init();
 	kirkwood_xor1_init();
-	kirkwood_crypto_init();
 
 #ifdef CONFIG_KEXEC
 	kexec_reinit = kirkwood_enable_pcie;
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index ef45244..154f1cf 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -15,6 +15,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mtd/nand.h>
 #include <linux/dma-mapping.h>
+#include <linux/of.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -267,7 +268,7 @@ void __init kirkwood_uart1_init(void)
 /*****************************************************************************
  * Cryptographic Engines and Security Accelerator (CESA)
  ****************************************************************************/
-void __init kirkwood_crypto_init(void)
+static void __init kirkwood_crypto_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_CRYPTO;
 	orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
@@ -480,6 +481,9 @@ static int __init kirkwood_clock_gate(void)
 {
 	unsigned int curr = readl(CLOCK_GATING_CTRL);
 	u32 dev, rev;
+#ifdef CONFIG_OF
+	struct device_node *np;
+#endif
 
 	kirkwood_pcie_id(&dev, &rev);
 	printk(KERN_DEBUG "Gating clock of unused units\n");
@@ -488,6 +492,14 @@ static int __init kirkwood_clock_gate(void)
 	/* Make sure those units are accessible */
 	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 
+#ifdef CONFIG_OF
+	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-crypto");
+	if (np && of_device_is_available(np)) {
+		kirkwood_clk_ctrl |= CGC_CRYPTO;
+		of_node_put(np);
+	}
+#endif
+
 	/* For SATA: first shutdown the phy */
 	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
 		/* Disable PLL and IVREF */
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index ca08826..76644e7 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -56,7 +56,6 @@ void kirkwood_l2_init(void);
 void kirkwood_wdt_init(void);
 void kirkwood_xor0_init(void);
 void kirkwood_xor1_init(void);
-void kirkwood_crypto_init(void);
 
 extern int kirkwood_tclk;
 extern struct sys_timer kirkwood_timer;
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:45 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:45 +0000
Subject: [PATCH 04/14] ARM: kirkwood: fdt: absorb kirkwood_init()
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <d26f8923d0e1446e834b0c6b996740264e6457f3.1331090356.git.jason@lakedaemon.net>

We need to absorb kirkwood_init() into kirkwood_dt_init() so that as we
convert drivers, we can remove the platform call, eg
kirkwood_rtc_init().  This maintains compatibility with non-fdt
configurations because they still call kirkwood_init() in common.c.

As drivers are converted, we will reinstate the 'static' qualifier in
common.c.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/mach-kirkwood/board-dt.c |   29 ++++++++++++++++++++++++++++-
 arch/arm/mach-kirkwood/common.c   |   12 ++++++------
 arch/arm/mach-kirkwood/common.h   |    8 ++++++++
 3 files changed, 42 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 76392af..f514b42 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -29,7 +29,9 @@
 #include <linux/spi/orion_spi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 #include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
 #include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
@@ -157,7 +159,32 @@ static void __init dreamplug_init(void)
 
 static void __init kirkwood_dt_init(void)
 {
-	kirkwood_init();
+	pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
+
+	/*
+	 * Disable propagation of mbus errors to the CPU local bus,
+	 * as this causes mbus errors (which can occur for example
+	 * for PCI aborts) to throw CPU aborts, which we're not set
+	 * up to deal with.
+	 */
+	writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
+
+	kirkwood_setup_cpu_mbus();
+
+#ifdef CONFIG_CACHE_FEROCEON_L2
+	kirkwood_l2_init();
+#endif
+
+	/* internal devices that every board has */
+	kirkwood_rtc_init();
+	kirkwood_wdt_init();
+	kirkwood_xor0_init();
+	kirkwood_xor1_init();
+	kirkwood_crypto_init();
+
+#ifdef CONFIG_KEXEC
+	kexec_reinit = kirkwood_enable_pcie;
+#endif
 
 	if (of_machine_is_compatible("globalscale,dreamplug"))
 		dreamplug_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index eacf7f5..ae90f60 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -162,7 +162,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-static void __init kirkwood_rtc_init(void)
+void __init kirkwood_rtc_init(void)
 {
 	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
@@ -278,7 +278,7 @@ void __init kirkwood_crypto_init(void)
 /*****************************************************************************
  * XOR0
  ****************************************************************************/
-static void __init kirkwood_xor0_init(void)
+void __init kirkwood_xor0_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_XOR0;
 
@@ -290,7 +290,7 @@ static void __init kirkwood_xor0_init(void)
 /*****************************************************************************
  * XOR1
  ****************************************************************************/
-static void __init kirkwood_xor1_init(void)
+void __init kirkwood_xor1_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_XOR1;
 
@@ -302,7 +302,7 @@ static void __init kirkwood_xor1_init(void)
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-static void __init kirkwood_wdt_init(void)
+void __init kirkwood_wdt_init(void)
 {
 	orion_wdt_init(kirkwood_tclk);
 }
@@ -391,7 +391,7 @@ void __init kirkwood_audio_init(void)
 /*
  * Identify device ID and revision.
  */
-static char * __init kirkwood_id(void)
+char * __init kirkwood_id(void)
 {
 	u32 dev, rev;
 
@@ -434,7 +434,7 @@ static char * __init kirkwood_id(void)
 	}
 }
 
-static void __init kirkwood_l2_init(void)
+void __init kirkwood_l2_init(void)
 {
 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
 	writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 9071a39..c382447 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -51,6 +51,14 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev
 void kirkwood_audio_init(void);
 void kirkwood_restart(char, const char *);
 
+char *kirkwood_id(void);
+void kirkwood_l2_init(void);
+void kirkwood_rtc_init(void);
+void kirkwood_wdt_init(void);
+void kirkwood_xor0_init(void);
+void kirkwood_xor1_init(void);
+void kirkwood_crypto_init(void);
+
 extern int kirkwood_tclk;
 extern struct sys_timer kirkwood_timer;
 
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:54 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:54 +0000
Subject: [PATCH 13/14] ARM: kirkwood: sata_mv: add device tree binding
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <9858608e73993c22b64e9f10cff6e597d20f73b1.1331090356.git.jason@lakedaemon.net>

From: Michael Walle <michael at walle.cc>

Based on devicetree work by Michael Walle.  Changed compatible property
to "mrvl,orion-sata", simplified retrieving nr_ports from fdt.

Signed-off-by: Michael Walle <michael at walle.cc>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 drivers/ata/sata_mv.c |   18 ++++++++++++++++--
 1 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 38950ea..ebd0d24 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -65,6 +65,7 @@
 #include <linux/mbus.h>
 #include <linux/bitops.h>
 #include <linux/gfp.h>
+#include <linux/of.h>
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_device.h>
@@ -4045,8 +4046,12 @@ static int mv_platform_probe(struct platform_device *pdev)
 		return -EINVAL;
 
 	/* allocate host */
-	mv_platform_data = pdev->dev.platform_data;
-	n_ports = mv_platform_data->n_ports;
+	if (pdev->dev.of_node)
+		of_property_read_u32(pdev->dev.of_node, "nr-ports", &n_ports);
+	else {
+		mv_platform_data = pdev->dev.platform_data;
+		n_ports = mv_platform_data->n_ports;
+	}
 
 	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
 	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
@@ -4172,6 +4177,14 @@ static int mv_platform_resume(struct platform_device *pdev)
 #define mv_platform_resume NULL
 #endif
 
+#ifdef CONFIG_OF
+static struct of_device_id mv_sata_dt_ids[] __devinitdata = {
+	{ .compatible = "mrvl,orion-sata", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, mvsdio_dt_ids);
+#endif
+
 static struct platform_driver mv_platform_driver = {
 	.probe			= mv_platform_probe,
 	.remove			= __devexit_p(mv_platform_remove),
@@ -4180,6 +4193,7 @@ static struct platform_driver mv_platform_driver = {
 	.driver			= {
 				   .name = DRV_NAME,
 				   .owner = THIS_MODULE,
+				   .of_match_table = of_match_ptr(mv_sata_dt_ids),
 				  },
 };
 
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:55 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:55 +0000
Subject: [PATCH 14/14] ARM: kirkwood: use devicetree to init sata_mv
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <8503a766f6f75c9acf49abd66d9cdce54807b2b2.1331090356.git.jason@lakedaemon.net>

Based on devicetree work by Michael Walle.  Changed compatible property
to "mrvl,orion-sata".

Signed-off-by: Michael Walle <michael at walle.cc>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/boot/dts/kirkwood-dreamplug.dts |    7 +++++++
 arch/arm/mach-kirkwood/board-dt.c        |    5 -----
 arch/arm/mach-kirkwood/common.c          |   10 ++++++++++
 3 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index f332380..8a28d5b 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -23,6 +23,13 @@
 		clock-frequency = <200000000>;
 	};
 
+	sata at f1080000 {
+		compatible = "mrvl,orion-sata";
+		reg = <0xf1080000 0x5000>;
+		interrupts = <21>;
+		nr-ports = <1>;
+	};
+
 	ehci at f1050000 {
 		compatible = "mrvl,orion-ehci";
 		reg = <0xf1050000 0x1000>;
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 1034ac7..12dec38 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -86,10 +86,6 @@ static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
 	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
 };
 
-static struct mv_sata_platform_data dreamplug_sata_data = {
-	.n_ports	= 1,
-};
-
 static struct mvsdio_platform_data dreamplug_mvsdio_data = {
 	/* unfortunately the CD signal has not been connected */
 };
@@ -149,7 +145,6 @@ static void __init dreamplug_init(void)
 
 	kirkwood_ge00_init(&dreamplug_ge00_data);
 	kirkwood_ge01_init(&dreamplug_ge01_data);
-	kirkwood_sata_init(&dreamplug_sata_data);
 	kirkwood_sdio_init(&dreamplug_mvsdio_data);
 
 	platform_device_register(&dreamplug_leds);
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index d0e8575..70ee7ac 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -504,6 +504,16 @@ static int __init kirkwood_clock_gate(void)
 		kirkwood_clk_ctrl |= CGC_USB0;
 		of_node_put(np);
 	}
+
+	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-sata");
+	if (np && of_device_is_available(np)) {
+		int nr_ports;
+		kirkwood_clk_ctrl |= CGC_SATA0;
+		of_property_read_u32(np, "nr-ports", &nr_ports);
+		if (nr_ports > 1)
+			kirkwood_clk_ctrl |= CGC_SATA1;
+		of_node_put(np);
+	}
 #endif
 
 	/* For SATA: first shutdown the phy */
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:52 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:52 +0000
Subject: [PATCH 11/14] ARM: kirkwood: ehci-orion: add device tree binding
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <8d2def2acb877d133bfbfb29a5afeb7aa6a7f954.1331090356.git.jason@lakedaemon.net>

From: Michael Walle <michael at walle.cc>

Signed-off-by: Michael Walle <michael at walle.cc>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 .../devicetree/bindings/usb/ehci-orion.txt         |    5 ++
 drivers/usb/host/ehci-orion.c                      |   50 +++++++++++++++++++-
 2 files changed, 53 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/ehci-orion.txt

diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt
new file mode 100644
index 0000000..b46d825
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ehci-orion.txt
@@ -0,0 +1,5 @@
+Marvell Orion SoC USB controller
+
+Required properties :
+ - compatible : should be "mrvl,orion-ehci".
+ - phy_version : should be "orion".
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
index 6c6a5a3..f1dec1d 100644
--- a/drivers/usb/host/ehci-orion.c
+++ b/drivers/usb/host/ehci-orion.c
@@ -12,6 +12,8 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/mbus.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 #include <plat/ehci-orion.h>
 
 #define rdl(off)	__raw_readl(hcd->regs + (off))
@@ -191,6 +193,29 @@ ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
 	}
 }
 
+static const char *phy_versions[] = {
+	[EHCI_PHY_NA]		= "",
+	[EHCI_PHY_ORION]	= "orion",
+	[EHCI_PHY_DD]		= "dd", /* XXX dd? */
+	[EHCI_PHY_KW]		= "kirkwood",
+};
+
+static const int get_phy_version(struct device_node *np)
+{
+	const char *pm;
+	int err, i;
+
+	err = of_property_read_string(np, "phy-version", &pm);
+	if (err < 0)
+		return err;
+
+	for (i = 0; i < ARRAY_SIZE(phy_versions); i++)
+		if (!strcasecmp(pm, phy_versions[i]))
+			return i;
+
+	return -ENODEV;
+}
+
 static int __devinit ehci_orion_drv_probe(struct platform_device *pdev)
 {
 	struct orion_ehci_data *pd = pdev->dev.platform_data;
@@ -200,6 +225,7 @@ static int __devinit ehci_orion_drv_probe(struct platform_device *pdev)
 	struct ehci_hcd *ehci;
 	void __iomem *regs;
 	int irq, err;
+	enum orion_ehci_phy_ver phy_version;
 
 	if (usb_disabled())
 		return -ENODEV;
@@ -267,7 +293,15 @@ static int __devinit ehci_orion_drv_probe(struct platform_device *pdev)
 	/*
 	 * setup Orion USB controller.
 	 */
-	switch (pd->phy_version) {
+	if (pdev->dev.of_node) {
+		phy_version = get_phy_version(pdev->dev.of_node);
+		if (phy_version < 0)
+			goto err3;
+	} else {
+		phy_version = pd->phy_version;
+	}
+
+	switch (phy_version) {
 	case EHCI_PHY_NA:	/* dont change USB phy settings */
 		break;
 	case EHCI_PHY_ORION:
@@ -312,9 +346,21 @@ static int __exit ehci_orion_drv_remove(struct platform_device *pdev)
 
 MODULE_ALIAS("platform:orion-ehci");
 
+#ifdef CONFIG_OF
+static const struct of_device_id ehci_orion_dt_ids[] __devinitdata = {
+	{ .compatible = "mrvl,orion-ehci", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, ehci_orion_dt_ids);
+#endif
+
 static struct platform_driver ehci_orion_driver = {
 	.probe		= ehci_orion_drv_probe,
 	.remove		= __exit_p(ehci_orion_drv_remove),
 	.shutdown	= usb_hcd_platform_shutdown,
-	.driver.name	= "orion-ehci",
+	.driver = {
+		.name	= "orion-ehci",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(ehci_orion_dt_ids),
+	},
 };
-- 
1.7.3.4



From jason at lakedaemon.net  Tue Mar  6 22:44:53 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed,  7 Mar 2012 03:44:53 +0000
Subject: [PATCH 12/14] ARM: kirkwood: use devicetree for orion-ehci
In-Reply-To: <cover.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
Message-ID: <45ba995e67914c0e04a8735fcc06b64b8dd687ec.1331090356.git.jason@lakedaemon.net>

Original devicetree node from Michael Walle, changed to use
'mrvl,orion-ehci' for compatible property.

Signed-off-by: Michael Walle <michael at walle.cc>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/boot/dts/kirkwood-dreamplug.dts |    7 +++++++
 arch/arm/mach-kirkwood/board-dt.c        |    1 -
 arch/arm/mach-kirkwood/common.c          |    6 ++++++
 3 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index ebb2c87..f332380 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -22,4 +22,11 @@
 		interrupts = <33>;
 		clock-frequency = <200000000>;
 	};
+
+	ehci at f1050000 {
+		compatible = "mrvl,orion-ehci";
+		reg = <0xf1050000 0x1000>;
+		interrupts = <19>;
+		phy-version = "orion";
+	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 638f261..1034ac7 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -147,7 +147,6 @@ static void __init dreamplug_init(void)
 				ARRAY_SIZE(dreamplug_spi_slave_info));
 	kirkwood_spi_init();
 
-	kirkwood_ehci_init();
 	kirkwood_ge00_init(&dreamplug_ge00_data);
 	kirkwood_ge01_init(&dreamplug_ge01_data);
 	kirkwood_sata_init(&dreamplug_sata_data);
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 154f1cf..d0e8575 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -498,6 +498,12 @@ static int __init kirkwood_clock_gate(void)
 		kirkwood_clk_ctrl |= CGC_CRYPTO;
 		of_node_put(np);
 	}
+
+	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-ehci");
+	if (np && of_device_is_available(np)) {
+		kirkwood_clk_ctrl |= CGC_USB0;
+		of_node_put(np);
+	}
 #endif
 
 	/* For SATA: first shutdown the phy */
-- 
1.7.3.4



From vapier at gentoo.org  Tue Mar  6 22:56:07 2012
From: vapier at gentoo.org (Mike Frysinger)
Date: Tue, 6 Mar 2012 22:56:07 -0500
Subject: [PATCH 1/3] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <201203062256.16105.vapier@gentoo.org>

On Tuesday 06 March 2012 19:30:36 Stephen Warren wrote:
> --- a/arch/blackfin/boot/Makefile
> +++ b/arch/blackfin/boot/Makefile
> 
> +ifeq ($(CONFIG_RAMKERNEL),y)
> +UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
> +else # CONFIG_ROMKERNEL must be set
> +UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
> +endif

this part is wrong :).  the else branch should be $(CONFIG_ROM_BASE).

> +UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "__start" {print
> $$1}')

i feel like if we tried harder, we could automate the -e arg for all arches.  
i understand if you don't want to undertake that though.
-mike
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From xiyou.wangcong at gmail.com  Tue Mar  6 23:14:36 2012
From: xiyou.wangcong at gmail.com (Cong Wang)
Date: Wed, 07 Mar 2012 12:14:36 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper
 to test CMA
In-Reply-To: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
Message-ID: <4F56E0AC.8070501@gmail.com>

On 03/07/2012 11:14 AM, Barry Song wrote:
> From: Barry Song<Baohua.Song at csr.com>
>
> Any write request to /dev/cma_test will let the module to allocate memory from
> CMA, for example:
>
> 1st time
> $ echo 1024>  /dev/cma_test
> will require cma_test to request 1MB(1024KB)
> 2nd time
> $ echo 2048>  /dev/cma_test
> will require cma_test to request 2MB(2048KB)
>
> Any read request to /dev/cma_test will let the module to free the 1st valid
> memory from CMA, for example:
>
> 1st time
> $ cat /dev/cma_test
> will require cma_test to free the 1MB allocated in the first write request
> 2nd time
> $ cat /dev/cma_test
> will require cma_test to free the 2MB allocated in the second write request

Any reason why using /dev not /proc or /sys?


From olof at lixom.net  Tue Mar  6 23:40:49 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 6 Mar 2012 20:40:49 -0800
Subject: [PATCH 0/3] arm: tegra: dts: USB Updates for Tegra legacy mode /
 OTG
In-Reply-To: <CAPnjgZ1rXEGbi3m3HeWiUxG_TbmUug0C0QZgb7_9Eiz-xPMHwg@mail.gmail.com>
References: <1328288172-8059-1-git-send-email-sjg@chromium.org>
 <74CDBE0F657A3D45AFBB94109FB122FF178E5D2FF5@HQMAIL01.nvidia.com>
 <CAPnjgZ1rXEGbi3m3HeWiUxG_TbmUug0C0QZgb7_9Eiz-xPMHwg@mail.gmail.com>
Message-ID: <CAOesGMjXkFOxfp9fnhwKFZSoUJmHObk7FaiaNNj2NSyyNMTjkw@mail.gmail.com>

On Tue, Mar 6, 2012 at 7:16 PM, Simon Glass <sjg at chromium.org> wrote:
> +Olof
>
> Hi,
>
> On Fri, Feb 3, 2012 at 11:59 AM, Stephen Warren <swarren at nvidia.com> wrote:
>> Simon Glass wrote at riday, February 03, 2012 9:56 AM:
>>> This little series brings in some bindings that seem useful for U-Boot.
>>>
>>> I am working mostly in U-Boot, but since there is no shared .dts repo
>>> I was asked to commit these changes to the kernel. I do not propose to
>>> update the Linux USB drivers to match.
>>
>> I think the series looks reasonable, so:
>>
>> Acked-by: Stephen Warren <swarren at nvidia.com<>
>>
>> (I note that the kernel's USB driver for USB1 doesn't attempt to clear
>> legacy mode; I wonder how we're getting away with that. Perhaps it's
>> only been tested with a bootloader that's already cleared legacy mode)
>>
>
> How does this series get picked up, please?

It drowned in the patch floods you've been sending, and it wasn't
addressed directly to me so I ignored it.

Please resend and I'll apply.


Thanks,

-Olof


From 21cnbao at gmail.com  Tue Mar  6 23:49:21 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 7 Mar 2012 12:49:21 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <4F56E0AC.8070501@gmail.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com>
Message-ID: <CAGsJ_4x4CwD+WAE9d+Xob_tfwqmE6SdBdBd5EbC64XBi4Uzvgg@mail.gmail.com>

2012/3/7 Cong Wang <xiyou.wangcong at gmail.com>:
> On 03/07/2012 11:14 AM, Barry Song wrote:
>>
>> From: Barry Song<Baohua.Song at csr.com>
>>
>> Any write request to /dev/cma_test will let the module to allocate memory
>> from
>> CMA, for example:
>>
>> 1st time
>> $ echo 1024> ?/dev/cma_test
>> will require cma_test to request 1MB(1024KB)
>> 2nd time
>> $ echo 2048> ?/dev/cma_test
>> will require cma_test to request 2MB(2048KB)
>>
>> Any read request to /dev/cma_test will let the module to free the 1st
>> valid
>> memory from CMA, for example:
>>
>> 1st time
>> $ cat /dev/cma_test
>> will require cma_test to free the 1MB allocated in the first write request
>> 2nd time
>> $ cat /dev/cma_test
>> will require cma_test to free the 2MB allocated in the second write
>> request
>
>
> Any reason why using /dev not /proc or /sys?

pls note it is just a test module to verify CMA at runtime. it is not
important either it is /dev, it is /proc or it is /sys.

any way to make things easier, we take that way.

-barry


From xiyou.wangcong at gmail.com  Tue Mar  6 23:55:37 2012
From: xiyou.wangcong at gmail.com (Cong Wang)
Date: Wed, 07 Mar 2012 12:55:37 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper
 to test CMA
In-Reply-To: <CAGsJ_4x4CwD+WAE9d+Xob_tfwqmE6SdBdBd5EbC64XBi4Uzvgg@mail.gmail.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com>
 <CAGsJ_4x4CwD+WAE9d+Xob_tfwqmE6SdBdBd5EbC64XBi4Uzvgg@mail.gmail.com>
Message-ID: <4F56EA49.8070808@gmail.com>

On 03/07/2012 12:49 PM, Barry Song wrote:
> 2012/3/7 Cong Wang<xiyou.wangcong at gmail.com>:
>> On 03/07/2012 11:14 AM, Barry Song wrote:
>>>
>>> From: Barry Song<Baohua.Song at csr.com>
>>>
>>> Any write request to /dev/cma_test will let the module to allocate memory
>>> from
>>> CMA, for example:
>>>
>>> 1st time
>>> $ echo 1024>    /dev/cma_test
>>> will require cma_test to request 1MB(1024KB)
>>> 2nd time
>>> $ echo 2048>    /dev/cma_test
>>> will require cma_test to request 2MB(2048KB)
>>>
>>> Any read request to /dev/cma_test will let the module to free the 1st
>>> valid
>>> memory from CMA, for example:
>>>
>>> 1st time
>>> $ cat /dev/cma_test
>>> will require cma_test to free the 1MB allocated in the first write request
>>> 2nd time
>>> $ cat /dev/cma_test
>>> will require cma_test to free the 2MB allocated in the second write
>>> request
>>
>>
>> Any reason why using /dev not /proc or /sys?
>
> pls note it is just a test module to verify CMA at runtime. it is not
> important either it is /dev, it is /proc or it is /sys.

Why not important? You want it to be merged, don't you?

>
> any way to make things easier, we take that way.
>

Why /dev interface is easier than /proc and /sys? Confused, actually I 
think /proc or /sys should be easier...


From 21cnbao at gmail.com  Tue Mar  6 23:57:31 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 7 Mar 2012 12:57:31 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <4F56EA49.8070808@gmail.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com>
 <CAGsJ_4x4CwD+WAE9d+Xob_tfwqmE6SdBdBd5EbC64XBi4Uzvgg@mail.gmail.com>
 <4F56EA49.8070808@gmail.com>
Message-ID: <CAGsJ_4xJoKGt3+b_3bteoMyeO615pCxFpMpsH4LtvufFNDv6bA@mail.gmail.com>

2012/3/7 Cong Wang <xiyou.wangcong at gmail.com>:
> On 03/07/2012 12:49 PM, Barry Song wrote:
>>
>> 2012/3/7 Cong Wang<xiyou.wangcong at gmail.com>:
>>>
>>> On 03/07/2012 11:14 AM, Barry Song wrote:
>>>>
>>>>
>>>> From: Barry Song<Baohua.Song at csr.com>
>>>>
>>>> Any write request to /dev/cma_test will let the module to allocate
>>>> memory
>>>> from
>>>> CMA, for example:
>>>>
>>>> 1st time
>>>> $ echo 1024> ? ?/dev/cma_test
>>>> will require cma_test to request 1MB(1024KB)
>>>> 2nd time
>>>> $ echo 2048> ? ?/dev/cma_test
>>>> will require cma_test to request 2MB(2048KB)
>>>>
>>>> Any read request to /dev/cma_test will let the module to free the 1st
>>>> valid
>>>> memory from CMA, for example:
>>>>
>>>> 1st time
>>>> $ cat /dev/cma_test
>>>> will require cma_test to free the 1MB allocated in the first write
>>>> request
>>>> 2nd time
>>>> $ cat /dev/cma_test
>>>> will require cma_test to free the 2MB allocated in the second write
>>>> request
>>>
>>>
>>>
>>> Any reason why using /dev not /proc or /sys?
>>
>>
>> pls note it is just a test module to verify CMA at runtime. it is not
>> important either it is /dev, it is /proc or it is /sys.
>
>
> Why not important? You want it to be merged, don't you?
>
>
>>
>> any way to make things easier, we take that way.
>>
>
> Why /dev interface is easier than /proc and /sys? Confused, actually I think
> /proc or /sys should be easier...

if you think so, pls do that and send v4 with your s-o-b.

-barry


From xiyou.wangcong at gmail.com  Wed Mar  7 00:01:26 2012
From: xiyou.wangcong at gmail.com (Cong Wang)
Date: Wed, 07 Mar 2012 13:01:26 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper
 to test CMA
In-Reply-To: <CAGsJ_4xJoKGt3+b_3bteoMyeO615pCxFpMpsH4LtvufFNDv6bA@mail.gmail.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com>
 <CAGsJ_4x4CwD+WAE9d+Xob_tfwqmE6SdBdBd5EbC64XBi4Uzvgg@mail.gmail.com>
 <4F56EA49.8070808@gmail.com>
 <CAGsJ_4xJoKGt3+b_3bteoMyeO615pCxFpMpsH4LtvufFNDv6bA@mail.gmail.com>
Message-ID: <4F56EBA6.6000704@gmail.com>

On 03/07/2012 12:57 PM, Barry Song wrote:
>
> if you think so, pls do that and send v4 with your s-o-b.
>

This is not a good attitude, nor helps your patch to be merged...

Be collaborative.


From sjg at chromium.org  Wed Mar  7 00:04:31 2012
From: sjg at chromium.org (Simon Glass)
Date: Tue,  6 Mar 2012 21:04:31 -0800
Subject: [RESEND PATCH 0/3] arm: tegra: dts: USB Updates for Tegra legacy mode
 / OTG
Message-ID: <1331096674-8324-1-git-send-email-sjg@chromium.org>

This little series brings in some bindings that seem useful for U-Boot.

I am working mostly in U-Boot, but since there is no shared .dts repo
I was asked to commit these changes to the kernel. I do not propose to
update the Linux USB drivers to match.


Simon Glass (3):
  arm: tegra: dts: Support host/device selection and legacy mode
  arm: tegra: dts: Add legacy mode support to Tegra2x USB1 port
  arm: tegra: dts: Mark USB1 as an OTG port on Seaboard

 .../devicetree/bindings/usb/tegra-usb.txt          |   13 +++++++++++++
 arch/arm/boot/dts/tegra-seaboard.dts               |    1 +
 arch/arm/boot/dts/tegra20.dtsi                     |    1 +
 3 files changed, 15 insertions(+), 0 deletions(-)

-- 
1.7.7.3



From sjg at chromium.org  Wed Mar  7 00:06:10 2012
From: sjg at chromium.org (Simon Glass)
Date: Tue, 6 Mar 2012 21:06:10 -0800
Subject: [PATCH 0/3] arm: tegra: dts: USB Updates for Tegra legacy mode /
 OTG
In-Reply-To: <CAOesGMjXkFOxfp9fnhwKFZSoUJmHObk7FaiaNNj2NSyyNMTjkw@mail.gmail.com>
References: <1328288172-8059-1-git-send-email-sjg@chromium.org>
 <74CDBE0F657A3D45AFBB94109FB122FF178E5D2FF5@HQMAIL01.nvidia.com>
 <CAPnjgZ1rXEGbi3m3HeWiUxG_TbmUug0C0QZgb7_9Eiz-xPMHwg@mail.gmail.com>
 <CAOesGMjXkFOxfp9fnhwKFZSoUJmHObk7FaiaNNj2NSyyNMTjkw@mail.gmail.com>
Message-ID: <CAPnjgZ3gBQyZ3BMesN+2_8ytYEz-0XtYGQwyDL3bUAp+pLoxdw@mail.gmail.com>

Hi Olof,

On Tue, Mar 6, 2012 at 8:40 PM, Olof Johansson <olof at lixom.net> wrote:
> On Tue, Mar 6, 2012 at 7:16 PM, Simon Glass <sjg at chromium.org> wrote:
>> +Olof
>>
>> Hi,
>>
>> On Fri, Feb 3, 2012 at 11:59 AM, Stephen Warren <swarren at nvidia.com> wrote:
>>> Simon Glass wrote at riday, February 03, 2012 9:56 AM:
>>>> This little series brings in some bindings that seem useful for U-Boot.
>>>>
>>>> I am working mostly in U-Boot, but since there is no shared .dts repo
>>>> I was asked to commit these changes to the kernel. I do not propose to
>>>> update the Linux USB drivers to match.
>>>
>>> I think the series looks reasonable, so:
>>>
>>> Acked-by: Stephen Warren <swarren at nvidia.com<>
>>>
>>> (I note that the kernel's USB driver for USB1 doesn't attempt to clear
>>> legacy mode; I wonder how we're getting away with that. Perhaps it's
>>> only been tested with a bootloader that's already cleared legacy mode)
>>>
>>
>> How does this series get picked up, please?
>
> It drowned in the patch floods you've been sending, and it wasn't
> addressed directly to me so I ignored it.
>
> Please resend and I'll apply.

You'll be happy to hear that the flood is mostly over now. I have
resent and copied you this time.

Regards,
Simon

>
>
> Thanks,
>
> -Olof


From 21cnbao at gmail.com  Wed Mar  7 00:05:56 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 7 Mar 2012 13:05:56 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <4F56EBA6.6000704@gmail.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com>
 <CAGsJ_4x4CwD+WAE9d+Xob_tfwqmE6SdBdBd5EbC64XBi4Uzvgg@mail.gmail.com>
 <4F56EA49.8070808@gmail.com>
 <CAGsJ_4xJoKGt3+b_3bteoMyeO615pCxFpMpsH4LtvufFNDv6bA@mail.gmail.com>
 <4F56EBA6.6000704@gmail.com>
Message-ID: <CAGsJ_4ypegMQVf0Xet1T5sLaaEDGh5s1Vi6w4t_UQSZp7nYQuQ@mail.gmail.com>

2012/3/7 Cong Wang <xiyou.wangcong at gmail.com>:
> On 03/07/2012 12:57 PM, Barry Song wrote:
>>
>>
>> if you think so, pls do that and send v4 with your s-o-b.
>>
>
> This is not a good attitude, nor helps your patch to be merged...
>
> Be collaborative.

some people like focusing on trivial things. i said i really didn't
care about the details whether it is /dev, /proc, /sys.
if you like a /proc, pls do it by yourself and i will agree. but i
will not waste my time on that.

-barry


From sjg at chromium.org  Wed Mar  7 00:04:32 2012
From: sjg at chromium.org (Simon Glass)
Date: Tue,  6 Mar 2012 21:04:32 -0800
Subject: [RESEND PATCH 1/3] arm: tegra: dts: Support host/device selection and
 legacy mode
In-Reply-To: <1331096674-8324-1-git-send-email-sjg@chromium.org>
References: <1331096674-8324-1-git-send-email-sjg@chromium.org>
Message-ID: <1331096674-8324-2-git-send-email-sjg@chromium.org>

Some USB ports can support host and device operation. We add the dr_mode
property (as found in Freescale) for this.

One USB port has a 'legacy mode', left over from the days of pre-Tegra
chips. I don't believe this is actually used, except that we must know
to turn this off in the driver.

Signed-off-by: Simon Glass <sjg at chromium.org>
---
 .../devicetree/bindings/usb/tegra-usb.txt          |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/tegra-usb.txt b/Documentation/devicetree/bindings/usb/tegra-usb.txt
index 035d63d..007005d 100644
--- a/Documentation/devicetree/bindings/usb/tegra-usb.txt
+++ b/Documentation/devicetree/bindings/usb/tegra-usb.txt
@@ -11,3 +11,16 @@ Required properties :
  - phy_type : Should be one of "ulpi" or "utmi".
  - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
    activated for the bus to be powered.
+
+Optional properties:
+  - dr_mode : dual role mode. Indicates the working mode for
+   nvidia,tegra20-ehci compatible controllers.  Can be "host", "peripheral",
+   or "otg".  Default to "host" if not defined for backward compatibility.
+      host means this is a host controller
+      peripheral means it is device controller
+      otg means it can operate as either ("on the go")
+  - nvidia,has-legacy-mode : boolean indicates whether this controller can
+    operate in legacy mode (as APX 2500 / 2600). In legacy mode some
+    registers are accessed through the APB_MISC base address instead of
+    the USB controller. Since this is a legacy issue it probably does not
+    warrant a compatible string of its own.
-- 
1.7.7.3



From sjg at chromium.org  Wed Mar  7 00:04:33 2012
From: sjg at chromium.org (Simon Glass)
Date: Tue,  6 Mar 2012 21:04:33 -0800
Subject: [RESEND PATCH 2/3] arm: tegra: dts: Add legacy mode support to
 Tegra2x USB1 port
In-Reply-To: <1331096674-8324-1-git-send-email-sjg@chromium.org>
References: <1331096674-8324-1-git-send-email-sjg@chromium.org>
Message-ID: <1331096674-8324-3-git-send-email-sjg@chromium.org>

Tegra's USB1 port supports legacy mode, so mark it as such. Even if we
don't use it, we must turn it off in the driver.

Signed-off-by: Simon Glass <sjg at chromium.org>
---
 arch/arm/boot/dts/tegra20.dtsi |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index ec1f010..a322c11 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -184,6 +184,7 @@
 		reg = <0xc5000000 0x4000>;
 		interrupts = < 0 20 0x04 >;
 		phy_type = "utmi";
+		nvidia,has-legacy-mode;
 	};
 
 	usb at c5004000 {
-- 
1.7.7.3



From sjg at chromium.org  Wed Mar  7 00:04:34 2012
From: sjg at chromium.org (Simon Glass)
Date: Tue,  6 Mar 2012 21:04:34 -0800
Subject: [RESEND PATCH 3/3] arm: tegra: dts: Mark USB1 as an OTG port on
 Seaboard
In-Reply-To: <1331096674-8324-1-git-send-email-sjg@chromium.org>
References: <1331096674-8324-1-git-send-email-sjg@chromium.org>
Message-ID: <1331096674-8324-4-git-send-email-sjg@chromium.org>

The USB1 port on Tegra2 supports operation in host or device modes. On
Seaboard this is possible, so mark the port as OTG.

Signed-off-by: Simon Glass <sjg at chromium.org>
---
 arch/arm/boot/dts/tegra-seaboard.dts |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index 876d5c9..dbf1c5a 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -112,6 +112,7 @@
 
 	usb at c5000000 {
 		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+		dr_mode = "otg";
 	};
 
 	gpio-keys {
-- 
1.7.7.3



From xiyou.wangcong at gmail.com  Wed Mar  7 00:09:49 2012
From: xiyou.wangcong at gmail.com (Cong Wang)
Date: Wed, 07 Mar 2012 13:09:49 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper
 to test CMA
In-Reply-To: <CAGsJ_4ypegMQVf0Xet1T5sLaaEDGh5s1Vi6w4t_UQSZp7nYQuQ@mail.gmail.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com>
 <CAGsJ_4x4CwD+WAE9d+Xob_tfwqmE6SdBdBd5EbC64XBi4Uzvgg@mail.gmail.com>
 <4F56EA49.8070808@gmail.com>
 <CAGsJ_4xJoKGt3+b_3bteoMyeO615pCxFpMpsH4LtvufFNDv6bA@mail.gmail.com>
 <4F56EBA6.6000704@gmail.com>
 <CAGsJ_4ypegMQVf0Xet1T5sLaaEDGh5s1Vi6w4t_UQSZp7nYQuQ@mail.gmail.com>
Message-ID: <4F56ED9D.3000504@gmail.com>

On 03/07/2012 01:05 PM, Barry Song wrote:
> 2012/3/7 Cong Wang<xiyou.wangcong at gmail.com>:
>> On 03/07/2012 12:57 PM, Barry Song wrote:
>>>
>>>
>>> if you think so, pls do that and send v4 with your s-o-b.
>>>
>>
>> This is not a good attitude, nor helps your patch to be merged...
>>
>> Be collaborative.
>
> some people like focusing on trivial things. i said i really didn't
> care about the details whether it is /dev, /proc, /sys.
> if you like a /proc, pls do it by yourself and i will agree. but i
> will not waste my time on that.

This is definitely not trivial... What's more, kernel developers *do* 
care about trivial things (trivial at kernel.org).

We are trying to make your patch perfect, you just refused, sigh...


From 21cnbao at gmail.com  Wed Mar  7 00:17:12 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 7 Mar 2012 13:17:12 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <4F56ED9D.3000504@gmail.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com>
 <CAGsJ_4x4CwD+WAE9d+Xob_tfwqmE6SdBdBd5EbC64XBi4Uzvgg@mail.gmail.com>
 <4F56EA49.8070808@gmail.com>
 <CAGsJ_4xJoKGt3+b_3bteoMyeO615pCxFpMpsH4LtvufFNDv6bA@mail.gmail.com>
 <4F56EBA6.6000704@gmail.com>
 <CAGsJ_4ypegMQVf0Xet1T5sLaaEDGh5s1Vi6w4t_UQSZp7nYQuQ@mail.gmail.com>
 <4F56ED9D.3000504@gmail.com>
Message-ID: <CAGsJ_4x9hGDh+PgrvtXqp-bdbPHABz1ErHGdvFQAr0m9RYM8Vw@mail.gmail.com>

2012/3/7 Cong Wang <xiyou.wangcong at gmail.com>:
> On 03/07/2012 01:05 PM, Barry Song wrote:
>>
>> 2012/3/7 Cong Wang<xiyou.wangcong at gmail.com>:
>>>
>>> On 03/07/2012 12:57 PM, Barry Song wrote:
>>>>
>>>>
>>>>
>>>> if you think so, pls do that and send v4 with your s-o-b.
>>>>
>>>
>>> This is not a good attitude, nor helps your patch to be merged...
>>>
>>> Be collaborative.
>>
>>
>> some people like focusing on trivial things. i said i really didn't
>> care about the details whether it is /dev, /proc, /sys.
>> if you like a /proc, pls do it by yourself and i will agree. but i
>> will not waste my time on that.
>
>
> This is definitely not trivial... What's more, kernel developers *do* care
> about trivial things (trivial at kernel.org).

that is definitely trivial as we are talking about things in a test
module. and we are not talking about any bug in the test module as
well.

>
> We are trying to make your patch perfect, you just refused, sigh...

pls note i just care about people have an easy way to test the newest
contiguous memory allocator. pls be focusing on valuable things.

i said if you like /proc, pls do and i agree.

-barry


From xiyou.wangcong at gmail.com  Wed Mar  7 00:22:48 2012
From: xiyou.wangcong at gmail.com (Cong Wang)
Date: Wed, 07 Mar 2012 13:22:48 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper
 to test CMA
In-Reply-To: <CAGsJ_4x9hGDh+PgrvtXqp-bdbPHABz1ErHGdvFQAr0m9RYM8Vw@mail.gmail.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com>
 <CAGsJ_4x4CwD+WAE9d+Xob_tfwqmE6SdBdBd5EbC64XBi4Uzvgg@mail.gmail.com>
 <4F56EA49.8070808@gmail.com>
 <CAGsJ_4xJoKGt3+b_3bteoMyeO615pCxFpMpsH4LtvufFNDv6bA@mail.gmail.com>
 <4F56EBA6.6000704@gmail.com>
 <CAGsJ_4ypegMQVf0Xet1T5sLaaEDGh5s1Vi6w4t_UQSZp7nYQuQ@mail.gmail.com>
 <4F56ED9D.3000504@gmail.com>
 <CAGsJ_4x9hGDh+PgrvtXqp-bdbPHABz1ErHGdvFQAr0m9RYM8Vw@mail.gmail.com>
Message-ID: <4F56F0A8.1000600@gmail.com>

On 03/07/2012 01:17 PM, Barry Song wrote:
> that is definitely trivial as we are talking about things in a test
> module. and we are not talking about any bug in the test module as
> well.

I am quite sure *any* patches have bugs will not be merged, IOW, you 
seem don't want your patch merged. :) Fine. That is all.


From daeinki at gmail.com  Wed Mar  7 00:28:13 2012
From: daeinki at gmail.com (InKi Dae)
Date: Wed, 7 Mar 2012 14:28:13 +0900
Subject: [PATCH v10 3/3] iommu/exynos: Add iommu driver for Exynos
 Platforms
In-Reply-To: <002201ccfb73$93311520$b9933f60$%cho@samsung.com>
References: <002201ccfb73$93311520$b9933f60$%cho@samsung.com>
Message-ID: <CAAQKjZNJHeApuiyh467w8wGaY8VFb_PqLrvHGUxmE8-+a4yRTA@mail.gmail.com>

> +static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
> +{
> + ? ? ? /* SYSMMU is in blocked when interrupt occurred. */
> + ? ? ? struct sysmmu_drvdata *data = dev_id;
> + ? ? ? struct resource *irqres;
> + ? ? ? struct platform_device *pdev;
> + ? ? ? enum EXYNOS_SYSMMU_INTERRUPT_TYPE itype;

how about to change EXYNOS_SYSMMU_INTERRUPT_TYPE to small letter? just
for code clean.

> + ? ? ? unsigned long addr = -1;
> +
> + ? ? ? int i, ret = -ENOSYS;
> +
> + ? ? ? read_lock(&data->lock);
> +
> + ? ? ? WARN_ON(!is_sysmmu_active(data));
> +
> + ? ? ? pdev = to_platform_device(data->sysmmu);
> + ? ? ? for (i = 0; i < pdev->num_resources; i++) {
> + ? ? ? ? ? ? ? irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
> + ? ? ? ? ? ? ? if (irqres && ((int)irqres->start == irq))
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? }

is there any reason that it should get irq resources in interrupt
handler? if not so then how about to move it into probe()?

> +
> + ? ? ? if (i == pdev->num_resources) {
> + ? ? ? ? ? ? ? itype = SYSMMU_FAULT_UNKNOWN;
> + ? ? ? } else {
> + ? ? ? ? ? ? ? i /= 2;
> +
> + ? ? ? ? ? ? ? itype = (enum EXYNOS_SYSMMU_INTERRUPT_TYPE)

ditto.

> + ? ? ? ? ? ? ? ? ? ? ? __ffs(__raw_readl(data->sfrbases[i] + REG_INT_STATUS));
> + ? ? ? ? ? ? ? if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
> + ? ? ? ? ? ? ? ? ? ? ? itype = SYSMMU_FAULT_UNKNOWN;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? addr = __raw_readl(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->sfrbases[i] + fault_reg_offset[itype]);
> + ? ? ? }
> +


From 21cnbao at gmail.com  Wed Mar  7 00:40:32 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 7 Mar 2012 13:40:32 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <4F56F0A8.1000600@gmail.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com>
 <CAGsJ_4x4CwD+WAE9d+Xob_tfwqmE6SdBdBd5EbC64XBi4Uzvgg@mail.gmail.com>
 <4F56EA49.8070808@gmail.com>
 <CAGsJ_4xJoKGt3+b_3bteoMyeO615pCxFpMpsH4LtvufFNDv6bA@mail.gmail.com>
 <4F56EBA6.6000704@gmail.com>
 <CAGsJ_4ypegMQVf0Xet1T5sLaaEDGh5s1Vi6w4t_UQSZp7nYQuQ@mail.gmail.com>
 <4F56ED9D.3000504@gmail.com>
 <CAGsJ_4x9hGDh+PgrvtXqp-bdbPHABz1ErHGdvFQAr0m9RYM8Vw@mail.gmail.com>
 <4F56F0A8.1000600@gmail.com>
Message-ID: <CAGsJ_4zPn=phmWw8qSed93QWnTdOF7peh71uom0i6idR1_jFSQ@mail.gmail.com>

2012/3/7 Cong Wang <xiyou.wangcong at gmail.com>:
> On 03/07/2012 01:17 PM, Barry Song wrote:
>>
>> that is definitely trivial as we are talking about things in a test
>> module. and we are not talking about any bug in the test module as
>> well.
>
>
> I am quite sure *any* patches have bugs will not be merged, IOW, you seem
> don't want your patch merged. :) Fine. That is all.

Cong, i was not againest what you said as a techinical issue.
definitely, it can be a /proc, it is also able to be /sys if you like.
/proc is probably better than /dev from the original design thinking in kernel.

here i focused on people have this module to test CMA at runtime. i
also thought Michal also wants this module to show people the usage of
CMA as well.

i'll much appreciate if you have time to move it to /proc.

-barry


From paul at pwsan.com  Wed Mar  7 00:57:22 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 6 Mar 2012 22:57:22 -0700 (MST)
Subject: [RFC PATCH] OMAP: UART: Enable tx wakeup bit in wer
In-Reply-To: <CAMrsUdJqmJ75=X_Qg3vQCr7zezs0jOK8L1ri8p5K=+6ZKsRFcg@mail.gmail.com>
References: <1327412249-31575-1-git-send-email-govindraj.raja@ti.com>
 <alpine.DEB.2.00.1201251217120.5324@utopia.booyaka.com>
 <alpine.DEB.2.00.1203051321580.1430@utopia.booyaka.com>
 <CAMrsUdJqmJ75=X_Qg3vQCr7zezs0jOK8L1ri8p5K=+6ZKsRFcg@mail.gmail.com>
Message-ID: <alpine.DEB.2.00.1203062251270.23214@utopia.booyaka.com>

Hi

On Tue, 6 Mar 2012, Raja, Govindraj wrote:

> I see two ways of adding this tx wake-up flag.
> 
> 1.) passing a feature flag from pdata and populating the feature value to wer.
> 
> 2.) Duplicating the uart1/2/3 hwmod for omap3430 without dev attrib
> and uart1/2/3/4
>      hwmod for omap3630 with dev attribs.
> 
> Approach-2 adds unnecessary code duplication in hwmod file with and without
> dev_attribs, So right now here is the patch to follow approach [1],
> 
> If its strongly recommended to use approach-2 will add it.
> (My concern is the diffstat it might produce with approach-2)

Both 1 and 2 are needed.

The current way that errata are handled in arch/arm/mach-omap2/serial.c 
needs to be changed.  Those should be flags that are passed from hwmod 
dev_attr data.  The presence of the TX wakeup bit should simply be another 
dev_attr flag.  These flags should be passed to the driver via the 
omap_up.errata field for the time being.

The exception to this is if the IP block's revision register was changed 
when TX wakeups became possible.  If that's the case, then that mechanism 
can be used in lieu of dev_attr and platform_data in this situation.


- Paul


From hdoyu at nvidia.com  Wed Mar  7 01:09:52 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 7 Mar 2012 07:09:52 +0100
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <401E54CE964CD94BAE1EB4A729C7087E37970113FE@HQMAIL04.nvidia.com>
References: <20120305134721.0ab0d0e6de56fa30250059b1@nvidia.com><000001ccfaea$00c16f70$02444e50$%szyprowski@samsung.com><401E54CE964CD94BAE1EB4A729C7087E37970113FE@HQMAIL04.nvidia.com>
Message-ID: <20120307.080952.2152478004740487196.hdoyu@nvidia.com>

From: Krishna Reddy <vdumpa at nvidia.com>
Subject: RE: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
Date: Tue, 6 Mar 2012 23:48:42 +0100
Message-ID: <401E54CE964CD94BAE1EB4A729C7087E37970113FE at HQMAIL04.nvidia.com>

> > > +struct dma_iommu_mapping *
> > > +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
> > > +                        int order)
> > > +{
> > > +       unsigned int count = (size >> PAGE_SHIFT) - order;
> > > +       unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
> 
> The count calculation doesn't seem correct. "order" is log2 number and
>  size >> PAGE_SHIFT is number of pages. 
> 
> If size is passed as 64*4096(256KB) and order is 6(allocation granularity is 2^6 pages=256KB),
>  just 1 bit is enough to manage allocations.  So it should be 4 bytes or one long.

Good catch!

> But the calculation gives count = 64 - 6 = 58 and 
> Bitmap_size gets set to (58/(4*8)) * 4 = 8 bytes, which is incorrect.

"order" isn't the order of size passed, which is minimal *page*
allocation order which client decides whatever, just in case.

> It should be as follows.
> unsigned int count = 1 << get_order(size) - order;
> unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long) * BITS_PER_BYTE;
> 
> -KR
> 
> --nvpublic
> 
> 


From pullip.cho at samsung.com  Wed Mar  7 01:22:33 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Wed, 7 Mar 2012 15:22:33 +0900
Subject: [PATCH v10 3/3] iommu/exynos: Add iommu driver for Exynos
 Platforms
In-Reply-To: <CAAQKjZNJHeApuiyh467w8wGaY8VFb_PqLrvHGUxmE8-+a4yRTA@mail.gmail.com>
References: <002201ccfb73$93311520$b9933f60$%cho@samsung.com>
 <CAAQKjZNJHeApuiyh467w8wGaY8VFb_PqLrvHGUxmE8-+a4yRTA@mail.gmail.com>
Message-ID: <CAHQjnOOQKS1EU-3zWDDq2sLxPucY9CRZyrnaT5cyyrSa9-k9Nw@mail.gmail.com>

On Wed, Mar 7, 2012 at 2:28 PM, InKi Dae <daeinki at gmail.com> wrote:
>> +static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
>> +{
>> + ? ? ? /* SYSMMU is in blocked when interrupt occurred. */
>> + ? ? ? struct sysmmu_drvdata *data = dev_id;
>> + ? ? ? struct resource *irqres;
>> + ? ? ? struct platform_device *pdev;
>> + ? ? ? enum EXYNOS_SYSMMU_INTERRUPT_TYPE itype;
>
> how about to change EXYNOS_SYSMMU_INTERRUPT_TYPE to small letter? just
> for code clean.
>
I will. please refer to the my reply to Kyungmin Park.

>> + ? ? ? unsigned long addr = -1;
>> +
>> + ? ? ? int i, ret = -ENOSYS;
>> +
>> + ? ? ? read_lock(&data->lock);
>> +
>> + ? ? ? WARN_ON(!is_sysmmu_active(data));
>> +
>> + ? ? ? pdev = to_platform_device(data->sysmmu);
>> + ? ? ? for (i = 0; i < pdev->num_resources; i++) {
>> + ? ? ? ? ? ? ? irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
>> + ? ? ? ? ? ? ? if (irqres && ((int)irqres->start == irq))
>> + ? ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? ? }
>
> is there any reason that it should get irq resources in interrupt
> handler? if not so then how about to move it into probe()?
>
The platform device of ISP has a lot of IRQ sources.
The above for clause determines which IRQ source (System MMU)
generated the interrupt.

>> +
>> + ? ? ? if (i == pdev->num_resources) {
>> + ? ? ? ? ? ? ? itype = SYSMMU_FAULT_UNKNOWN;
>> + ? ? ? } else {
>> + ? ? ? ? ? ? ? i /= 2;
>> +
>> + ? ? ? ? ? ? ? itype = (enum EXYNOS_SYSMMU_INTERRUPT_TYPE)
>
> ditto.
>

Thank you.

Cho KyongHo.


From hdoyu at nvidia.com  Wed Mar  7 01:37:06 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 7 Mar 2012 07:37:06 +0100
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <20120307.080952.2152478004740487196.hdoyu@nvidia.com>
References: <000001ccfaea$00c16f70$02444e50$%szyprowski@samsung.com><401E54CE964CD94BAE1EB4A729C7087E37970113FE@HQMAIL04.nvidia.com><20120307.080952.2152478004740487196.hdoyu@nvidia.com>
Message-ID: <20120307.083706.2087121294965856946.hdoyu@nvidia.com>

From: Hiroshi DOYU <hdoyu at nvidia.com>
Subject: Re: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
Date: Wed, 07 Mar 2012 08:09:52 +0200 (EET)
Message-ID: <20120307.080952.2152478004740487196.hdoyu at nvidia.com>

> From: Krishna Reddy <vdumpa at nvidia.com>
> Subject: RE: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
> Date: Tue, 6 Mar 2012 23:48:42 +0100
> Message-ID: <401E54CE964CD94BAE1EB4A729C7087E37970113FE at HQMAIL04.nvidia.com>
> 
> > > > +struct dma_iommu_mapping *
> > > > +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
> > > > +                        int order)
> > > > +{
> > > > +       unsigned int count = (size >> PAGE_SHIFT) - order;
> > > > +       unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
> > 
> > The count calculation doesn't seem correct. "order" is log2 number and
> >  size >> PAGE_SHIFT is number of pages. 
> > 
> > If size is passed as 64*4096(256KB) and order is 6(allocation granularity is 2^6 pages=256KB),
> >  just 1 bit is enough to manage allocations.  So it should be 4 bytes or one long.
> 
> Good catch!
> 
> > But the calculation gives count = 64 - 6 = 58 and 
> > Bitmap_size gets set to (58/(4*8)) * 4 = 8 bytes, which is incorrect.
> 
> "order" isn't the order of size passed, which is minimal *page*
> allocation order which client decides whatever, just in case.
> 
> > It should be as follows.
> > unsigned int count = 1 << get_order(size) - order;

To be precise, as below?

 unsigned int count = 1 << (get_order(size) - order);

> > unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long) * BITS_PER_BYTE;
> > 
> > -KR
> > 
> > --nvpublic
> > 
> > 


From vinod.koul at intel.com  Wed Mar  7 01:42:51 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Wed, 07 Mar 2012 12:12:51 +0530
Subject: [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with
 imx-dma.c
In-Reply-To: <1330964196-32623-2-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
 <1330964196-32623-2-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331102571.24656.324.camel@vkoul-udesk3>

On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
Sascha,
Are there any more users of dmac in mach-imx? If not then why not move
the code, rather than copy. If yes can we move them as well?

> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> ---
>  arch/arm/mach-imx/Kconfig  |    6 -
>  arch/arm/mach-imx/Makefile |    2 -
>  drivers/dma/Kconfig        |    1 -
>  drivers/dma/imx-dma.c      |  591 ++++++++++++++++++++++++++++++++++++++++----
>  4 files changed, 541 insertions(+), 59 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 0e6de36..3da1421 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -1,6 +1,3 @@
> -config IMX_HAVE_DMA_V1
> -	bool
> -
>  config HAVE_IMX_GPC
>  	bool
>  
> @@ -26,7 +23,6 @@ config SOC_IMX1
>  	bool
>  	select ARCH_MX1
>  	select CPU_ARM920T
> -	select IMX_HAVE_DMA_V1
>  	select IMX_HAVE_IOMUX_V1
>  	select MXC_AVIC
>  
> @@ -35,7 +31,6 @@ config SOC_IMX21
>  	select MACH_MX21
>  	select CPU_ARM926T
>  	select ARCH_MXC_AUDMUX_V1
> -	select IMX_HAVE_DMA_V1
>  	select IMX_HAVE_IOMUX_V1
>  	select MXC_AVIC
>  
> @@ -52,7 +47,6 @@ config SOC_IMX27
>  	select MACH_MX27
>  	select CPU_ARM926T
>  	select ARCH_MXC_AUDMUX_V1
> -	select IMX_HAVE_DMA_V1
>  	select IMX_HAVE_IOMUX_V1
>  	select MXC_AVIC
>  
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index f5920c2..a62dc3a 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -1,5 +1,3 @@
> -obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
> -
>  obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
>  obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
>  
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index f1a2749..eb58b91 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -231,7 +231,6 @@ config IMX_SDMA
>  
>  config IMX_DMA
>  	tristate "i.MX DMA support"
> -	depends on IMX_HAVE_DMA_V1
>  	select DMA_ENGINE
>  	help
>  	  Support the i.MX DMA engine. This engine is integrated into
> diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
> index c32103f..28d716c 100644
> --- a/drivers/dma/imx-dma.c
> +++ b/drivers/dma/imx-dma.c
> @@ -14,7 +14,6 @@
>   * http://www.opensource.org/licenses/gpl-license.html
>   * http://www.gnu.org/copyleft/gpl.html
>   */
> -
>  #include <linux/init.h>
>  #include <linux/module.h>
>  #include <linux/types.h>
> @@ -25,14 +24,88 @@
>  #include <linux/dma-mapping.h>
>  #include <linux/slab.h>
>  #include <linux/platform_device.h>
> +#include <linux/clk.h>
>  #include <linux/dmaengine.h>
>  #include <linux/module.h>
>  
>  #include <asm/irq.h>
> -#include <mach/dma-v1.h>
> +#include <mach/dma.h>
>  #include <mach/hardware.h>
>  
>  #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
> +#define IMX_DMA_CHANNELS  16
> +
> +#define DMA_MODE_READ		0
> +#define DMA_MODE_WRITE		1
> +#define DMA_MODE_MASK		1
> +
> +#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
> +#define IMX_DMA_MEMSIZE_32	(0 << 4)
> +#define IMX_DMA_MEMSIZE_8	(1 << 4)
> +#define IMX_DMA_MEMSIZE_16	(2 << 4)
> +#define IMX_DMA_TYPE_LINEAR	(0 << 10)
> +#define IMX_DMA_TYPE_2D		(1 << 10)
> +#define IMX_DMA_TYPE_FIFO	(2 << 10)
> +
> +#define IMX_DMA_ERR_BURST     (1 << 0)
> +#define IMX_DMA_ERR_REQUEST   (1 << 1)
> +#define IMX_DMA_ERR_TRANSFER  (1 << 2)
> +#define IMX_DMA_ERR_BUFFER    (1 << 3)
> +#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
> +
> +#define DMA_DCR     0x00		/* Control Register */
> +#define DMA_DISR    0x04		/* Interrupt status Register */
> +#define DMA_DIMR    0x08		/* Interrupt mask Register */
> +#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
> +#define DMA_DRTOSR  0x10		/* Request timeout Register */
> +#define DMA_DSESR   0x14		/* Transfer Error Status Register */
> +#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
> +#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
> +#define DMA_WSRA    0x40		/* W-Size Register A */
> +#define DMA_XSRA    0x44		/* X-Size Register A */
> +#define DMA_YSRA    0x48		/* Y-Size Register A */
> +#define DMA_WSRB    0x4c		/* W-Size Register B */
> +#define DMA_XSRB    0x50		/* X-Size Register B */
> +#define DMA_YSRB    0x54		/* Y-Size Register B */
> +#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
> +#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
> +#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
> +#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
> +#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
> +#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
> +#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
> +#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
> +#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */
> +
> +#define DCR_DRST           (1<<1)
> +#define DCR_DEN            (1<<0)
> +#define DBTOCR_EN          (1<<15)
> +#define DBTOCR_CNT(x)      ((x) & 0x7fff)
> +#define CNTR_CNT(x)        ((x) & 0xffffff)
> +#define CCR_ACRPT          (1<<14)
> +#define CCR_DMOD_LINEAR    (0x0 << 12)
> +#define CCR_DMOD_2D        (0x1 << 12)
> +#define CCR_DMOD_FIFO      (0x2 << 12)
> +#define CCR_DMOD_EOBFIFO   (0x3 << 12)
> +#define CCR_SMOD_LINEAR    (0x0 << 10)
> +#define CCR_SMOD_2D        (0x1 << 10)
> +#define CCR_SMOD_FIFO      (0x2 << 10)
> +#define CCR_SMOD_EOBFIFO   (0x3 << 10)
> +#define CCR_MDIR_DEC       (1<<9)
> +#define CCR_MSEL_B         (1<<8)
> +#define CCR_DSIZ_32        (0x0 << 6)
> +#define CCR_DSIZ_8         (0x1 << 6)
> +#define CCR_DSIZ_16        (0x2 << 6)
> +#define CCR_SSIZ_32        (0x0 << 4)
> +#define CCR_SSIZ_8         (0x1 << 4)
> +#define CCR_SSIZ_16        (0x2 << 4)
> +#define CCR_REN            (1<<3)
> +#define CCR_RPT            (1<<2)
> +#define CCR_FRC            (1<<1)
> +#define CCR_CEN            (1<<0)
> +#define RTOR_EN            (1<<15)
> +#define RTOR_CLK           (1<<14)
> +#define RTOR_PSC           (1<<13)
>  
>  enum  imxdma_prep_type {
>  	IMXDMA_DESC_MEMCPY,
> @@ -41,6 +114,39 @@ enum  imxdma_prep_type {
>  	IMXDMA_DESC_CYCLIC,
>  };
>  
> +/*
> + * struct imxdma_channel_internal - i.MX specific DMA extension
> + * @name: name specified by DMA client
> + * @irq_handler: client callback for end of transfer
> + * @err_handler: client callback for error condition
> + * @data: clients context data for callbacks
> + * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
> + * @sg: pointer to the actual read/written chunk for scatter-gather emulation
> + * @resbytes: total residual number of bytes to transfer
> + *            (it can be lower or same as sum of SG mapped chunk sizes)
> + * @sgcount: number of chunks to be read/written
> + *
> + * Structure is used for IMX DMA processing. It would be probably good
> + * @struct dma_struct in the future for external interfacing and use
> + * @struct imxdma_channel_internal only as extension to it.
> + */
> +
> +struct imxdma_channel_internal {
> +	void *data;
> +	unsigned int dma_mode;
> +	struct scatterlist *sg;
> +	unsigned int resbytes;
> +
> +	int in_use;
> +
> +	u32 ccr_from_device;
> +	u32 ccr_to_device;
> +
> +	struct timer_list watchdog;
> +
> +	int hw_chaining;
> +};
> +
>  struct imxdma_desc {
>  	struct list_head		node;
>  	struct dma_async_tx_descriptor	desc;
> @@ -63,9 +169,9 @@ struct imxdma_desc {
>  };
>  
>  struct imxdma_channel {
> +	struct imxdma_channel_internal	internal;
>  	struct imxdma_engine		*imxdma;
>  	unsigned int			channel;
> -	unsigned int			imxdma_channel;
>  
>  	struct tasklet_struct		dma_tasklet;
>  	struct list_head		ld_free;
> @@ -109,28 +215,381 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
>  	return false;
>  }
>  
> -static void imxdma_irq_handler(int channel, void *data)
> +/* TODO: put this inside any struct */
> +static void __iomem *imx_dmav1_baseaddr;
> +static struct clk *dma_clk;
> +
> +static void imx_dmav1_writel(unsigned val, unsigned offset)
>  {
> -	struct imxdma_channel *imxdmac = data;
> +	__raw_writel(val, imx_dmav1_baseaddr + offset);
> +}
>  
> -	tasklet_schedule(&imxdmac->dma_tasklet);
> +static unsigned imx_dmav1_readl(unsigned offset)
> +{
> +	return __raw_readl(imx_dmav1_baseaddr + offset);
>  }
>  
> -static void imxdma_err_handler(int channel, void *data, int error)
> +static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
>  {
> -	struct imxdma_channel *imxdmac = data;
> +	if (cpu_is_mx27())
> +		return imxdma->hw_chaining;
> +	else
> +		return 0;
> +}
> +
> +/*
> + * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
> + */
> +static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
> +{
> +	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
> +	unsigned long now;
> +
> +	now = min(imxdma->resbytes, sg->length);
> +	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
> +		imxdma->resbytes -= now;
> +
> +	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
> +		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
> +	else
> +		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
> +
> +	imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
> +
> +	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
> +		"size 0x%08x\n", imxdmac->channel,
> +		 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
> +		 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
> +		 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
> +
> +	return now;
> +}
> +
> +static int
> +imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
> +		     unsigned int dma_length, unsigned int dev_addr,
> +		     unsigned int dmamode)
> +{
> +	int channel = imxdmac->channel;
> +
> +	imxdmac->internal.sg = NULL;
> +	imxdmac->internal.dma_mode = dmamode;
> +
> +	if (!dma_address) {
> +		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
> +		       channel);
> +		return -EINVAL;
> +	}
> +
> +	if (!dma_length) {
> +		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
> +		       channel);
> +		return -EINVAL;
> +	}
> +
> +	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
> +		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
> +			"dev_addr=0x%08x for read\n",
> +			channel, __func__, (unsigned int)dma_address,
> +			dma_length, dev_addr);
> +
> +		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
> +		imx_dmav1_writel(dma_address, DMA_DAR(channel));
> +		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
> +	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
> +		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
> +			"dev_addr=0x%08x for write\n",
> +			channel, __func__, (unsigned int)dma_address,
> +			dma_length, dev_addr);
> +
> +		imx_dmav1_writel(dma_address, DMA_SAR(channel));
> +		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
> +		imx_dmav1_writel(imxdmac->internal.ccr_to_device,
> +				DMA_CCR(channel));
> +	} else {
> +		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
> +		       channel);
> +		return -EINVAL;
> +	}
>  
> +	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
> +
> +	return 0;
> +}
> +
> +static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
> +{
> +	int channel = imxdmac->channel;
> +	unsigned long flags;
> +
> +	pr_debug("imxdma%d: imx_dma_enable\n", channel);
> +
> +	if (imxdmac->internal.in_use)
> +		return;
> +
> +	local_irq_save(flags);
> +
> +	imx_dmav1_writel(1 << channel, DMA_DISR);
> +	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
> +	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
> +		CCR_ACRPT, DMA_CCR(channel));
> +
> +	if ((cpu_is_mx21() || cpu_is_mx27()) &&
> +			imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
> +		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
> +		if (imxdmac->internal.sg) {
> +			u32 tmp;
> +			imxdma_sg_next(imxdmac, imxdmac->internal.sg);
> +			tmp = imx_dmav1_readl(DMA_CCR(channel));
> +			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
> +				DMA_CCR(channel));
> +		}
> +	}
> +	imxdmac->internal.in_use = 1;
> +
> +	local_irq_restore(flags);
> +}
> +
> +static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
> +{
> +	int channel = imxdmac->channel;
> +	unsigned long flags;
> +
> +	pr_debug("imxdma%d: imx_dma_disable\n", channel);
> +
> +	if (imxdma_hw_chain(&imxdmac->internal))
> +		del_timer(&imxdmac->internal.watchdog);
> +
> +	local_irq_save(flags);
> +	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
> +	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
> +			DMA_CCR(channel));
> +	imx_dmav1_writel(1 << channel, DMA_DISR);
> +	imxdmac->internal.in_use = 0;
> +	local_irq_restore(flags);
> +}
> +
> +static int
> +imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
> +	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
> +{
> +	int channel = imxdmac->channel;
> +	u32 dreq = 0;
> +
> +	imxdmac->internal.hw_chaining = 0;
> +
> +	if (hw_chaining) {
> +		imxdmac->internal.hw_chaining = 1;
> +		if (!imxdma_hw_chain(&imxdmac->internal))
> +			return -EINVAL;
> +	}
> +
> +	if (dmareq)
> +		dreq = CCR_REN;
> +
> +	imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
> +	imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
> +
> +	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
> +
> +	return 0;
> +}
> +
> +static int
> +imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
> +		 struct scatterlist *sg, unsigned int sgcount,
> +		 unsigned int dma_length, unsigned int dev_addr,
> +		 unsigned int dmamode)
> +{
> +	int channel = imxdmac->channel;
> +
> +	if (imxdmac->internal.in_use)
> +		return -EBUSY;
> +
> +	imxdmac->internal.sg = sg;
> +	imxdmac->internal.dma_mode = dmamode;
> +	imxdmac->internal.resbytes = dma_length;
> +
> +	if (!sg || !sgcount) {
> +		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
> +		       channel);
> +		return -EINVAL;
> +	}
> +
> +	if (!sg->length) {
> +		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
> +		       channel);
> +		return -EINVAL;
> +	}
> +
> +	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
> +		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
> +			"dev_addr=0x%08x for read\n",
> +			channel, __func__, sg, sgcount, dma_length, dev_addr);
> +
> +		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
> +		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
> +	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
> +		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
> +			"dev_addr=0x%08x for write\n",
> +			channel, __func__, sg, sgcount, dma_length, dev_addr);
> +
> +		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
> +		imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
> +	} else {
> +		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
> +		       channel);
> +		return -EINVAL;
> +	}
> +
> +	imxdma_sg_next(imxdmac, sg);
> +
> +	return 0;
> +}
> +
> +static void imxdma_watchdog(unsigned long data)
> +{
> +	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
> +	int channel = imxdmac->channel;
> +
> +	imx_dmav1_writel(0, DMA_CCR(channel));
> +	imxdmac->internal.in_use = 0;
> +	imxdmac->internal.sg = NULL;
> +
> +	/* Tasklet watchdog error handler */
>  	tasklet_schedule(&imxdmac->dma_tasklet);
> +	pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
> +}
> +
> +static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
> +{
> +	struct imxdma_engine *imxdma = dev_id;
> +	struct imxdma_channel_internal *internal;
> +	unsigned int err_mask;
> +	int i, disr;
> +	int errcode;
> +
> +	disr = imx_dmav1_readl(DMA_DISR);
> +
> +	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
> +		   imx_dmav1_readl(DMA_DRTOSR) |
> +		   imx_dmav1_readl(DMA_DSESR)  |
> +		   imx_dmav1_readl(DMA_DBOSR);
> +
> +	if (!err_mask)
> +		return IRQ_HANDLED;
> +
> +	imx_dmav1_writel(disr & err_mask, DMA_DISR);
> +
> +	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
> +		if (!(err_mask & (1 << i)))
> +			continue;
> +		internal = &imxdma->channel[i].internal;
> +		errcode = 0;
> +
> +		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
> +			imx_dmav1_writel(1 << i, DMA_DBTOSR);
> +			errcode |= IMX_DMA_ERR_BURST;
> +		}
> +		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
> +			imx_dmav1_writel(1 << i, DMA_DRTOSR);
> +			errcode |= IMX_DMA_ERR_REQUEST;
> +		}
> +		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
> +			imx_dmav1_writel(1 << i, DMA_DSESR);
> +			errcode |= IMX_DMA_ERR_TRANSFER;
> +		}
> +		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
> +			imx_dmav1_writel(1 << i, DMA_DBOSR);
> +			errcode |= IMX_DMA_ERR_BUFFER;
> +		}
> +		/* Tasklet error handler */
> +		tasklet_schedule(&imxdma->channel[i].dma_tasklet);
> +
> +		printk(KERN_WARNING
> +		       "DMA timeout on channel %d -%s%s%s%s\n", i,
> +		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
> +		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
> +		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
> +		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
> +	}
> +	return IRQ_HANDLED;
>  }
>  
> -static void imxdma_progression(int channel, void *data,
> -		struct scatterlist *sg)
> +static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
>  {
> -	struct imxdma_channel *imxdmac = data;
> +	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
> +	int chno = imxdmac->channel;
> +
> +	if (imxdma->sg) {
> +		u32 tmp;
> +		imxdma->sg = sg_next(imxdma->sg);
> +
> +		if (imxdma->sg) {
> +			imxdma_sg_next(imxdmac, imxdma->sg);
> +
> +			tmp = imx_dmav1_readl(DMA_CCR(chno));
> +
> +			if (imxdma_hw_chain(imxdma)) {
> +				/* FIXME: The timeout should probably be
> +				 * configurable
> +				 */
> +				mod_timer(&imxdma->watchdog,
> +					jiffies + msecs_to_jiffies(500));
> +
> +				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
> +				imx_dmav1_writel(tmp, DMA_CCR(chno));
> +			} else {
> +				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
> +				tmp |= CCR_CEN;
> +			}
> +
> +			imx_dmav1_writel(tmp, DMA_CCR(chno));
> +
> +			if (imxdma_chan_is_doing_cyclic(imxdmac))
> +				/* Tasklet progression */
> +				tasklet_schedule(&imxdmac->dma_tasklet);
> +
> +			return;
> +		}
>  
> +		if (imxdma_hw_chain(imxdma)) {
> +			del_timer(&imxdma->watchdog);
> +			return;
> +		}
> +	}
> +
> +	imx_dmav1_writel(0, DMA_CCR(chno));
> +	imxdma->in_use = 0;
> +	/* Tasklet irq */
>  	tasklet_schedule(&imxdmac->dma_tasklet);
>  }
>  
> +static irqreturn_t dma_irq_handler(int irq, void *dev_id)
> +{
> +	struct imxdma_engine *imxdma = dev_id;
> +	struct imxdma_channel_internal *internal;
> +	int i, disr;
> +
> +	if (cpu_is_mx21() || cpu_is_mx27())
> +		imxdma_err_handler(irq, dev_id);
> +
> +	disr = imx_dmav1_readl(DMA_DISR);
> +
> +	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
> +		     disr);
> +
> +	imx_dmav1_writel(disr, DMA_DISR);
> +	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
> +		if (disr & (1 << i)) {
> +			internal = &imxdma->channel[i].internal;
> +			dma_irq_handle_channel(&imxdma->channel[i]);
> +		}
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
>  static int imxdma_xfer_desc(struct imxdma_desc *d)
>  {
>  	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
> @@ -139,31 +598,24 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
>  	/* Configure and enable */
>  	switch (d->type) {
>  	case IMXDMA_DESC_MEMCPY:
> -		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
> +		ret = imxdma_config_channel_hw(imxdmac,
>  					  d->config_port, d->config_mem, 0, 0);
>  		if (ret < 0)
>  			return ret;
> -		ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
> +		ret = imxdma_setup_single_hw(imxdmac, d->src,
>  					   d->len, d->dest, d->dmamode);
>  		if (ret < 0)
>  			return ret;
>  		break;
> +
> +	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
>  	case IMXDMA_DESC_CYCLIC:
> -		ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
> -							imxdma_progression);
> -		if (ret < 0)
> -			return ret;
> -		/*
> -		 * We fall through here since cyclic transfer is the same as
> -		 * slave_sg adding a progression handler and a specific sg
> -		 * configuration which is done in 'imxdma_prep_dma_cyclic'.
> -		 */
>  	case IMXDMA_DESC_SLAVE_SG:
>  		if (d->dmamode == DMA_MODE_READ)
> -			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
> +			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
>  				       d->sgcount, d->len, d->src, d->dmamode);
>  		else
> -			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
> +			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
>  				      d->sgcount, d->len, d->dest, d->dmamode);
>  		if (ret < 0)
>  			return ret;
> @@ -171,7 +623,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
>  	default:
>  		return -EINVAL;
>  	}
> -	imx_dma_enable(imxdmac->imxdma_channel);
> +	imxdma_enable_hw(imxdmac);
>  	return 0;
>  }
>  
> @@ -223,7 +675,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
>  
>  	switch (cmd) {
>  	case DMA_TERMINATE_ALL:
> -		imx_dma_disable(imxdmac->imxdma_channel);
> +		imxdma_disable_hw(imxdmac);
>  
>  		spin_lock_irqsave(&imxdmac->lock, flags);
>  		list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
> @@ -253,16 +705,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
>  			mode = IMX_DMA_MEMSIZE_32;
>  			break;
>  		}
> -		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
> +		ret = imxdma_config_channel_hw(imxdmac,
>  				mode | IMX_DMA_TYPE_FIFO,
>  				IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
>  				imxdmac->dma_request, 1);
>  
>  		if (ret)
>  			return ret;
> -
> -		imx_dma_config_burstlen(imxdmac->imxdma_channel,
> -				imxdmac->watermark_level * imxdmac->word_size);
> +		/* Set burst length */
> +		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
> +				 DMA_BLR(imxdmac->channel));
>  
>  		return 0;
>  	default:
> @@ -359,7 +811,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
>  
>  	spin_lock_irqsave(&imxdmac->lock, flags);
>  
> -	imx_dma_disable(imxdmac->imxdma_channel);
> +	imxdma_disable_hw(imxdmac);
>  	list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
>  	list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
>  
> @@ -545,10 +997,51 @@ static void imxdma_issue_pending(struct dma_chan *chan)
>  }
>  
>  static int __init imxdma_probe(struct platform_device *pdev)
> -{
> +	{
>  	struct imxdma_engine *imxdma;
>  	int ret, i;
>  
> +	if (cpu_is_mx1())
> +		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
> +	else if (cpu_is_mx21())
> +		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
> +	else if (cpu_is_mx27())
> +		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
> +	else
> +		return 0;
> +
> +	dma_clk = clk_get(NULL, "dma");
> +	if (IS_ERR(dma_clk))
> +		return PTR_ERR(dma_clk);
> +	clk_enable(dma_clk);
> +
> +	/* reset DMA module */
> +	imx_dmav1_writel(DCR_DRST, DMA_DCR);
> +
> +	if (cpu_is_mx1()) {
> +		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
> +		if (ret) {
> +			pr_crit("Can't register IRQ for DMA\n");
> +			return ret;
> +		}
> +
> +		ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
> +		if (ret) {
> +			pr_crit("Can't register ERRIRQ for DMA\n");
> +			free_irq(MX1_DMA_INT, NULL);
> +			return ret;
> +		}
> +	}
> +
> +	/* enable DMA module */
> +	imx_dmav1_writel(DCR_DEN, DMA_DCR);
> +
> +	/* clear all interrupts */
> +	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
> +
> +	/* disable interrupts */
> +	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
> +
>  	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
>  	if (!imxdma)
>  		return -ENOMEM;
> @@ -562,17 +1055,20 @@ static int __init imxdma_probe(struct platform_device *pdev)
>  	/* Initialize channel parameters */
>  	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
>  		struct imxdma_channel *imxdmac = &imxdma->channel[i];
> -
> -		imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
> -				DMA_PRIO_MEDIUM);
> -		if ((int)imxdmac->channel < 0) {
> -			ret = -ENODEV;
> -			goto err_init;
> +		memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
> +		if (cpu_is_mx21() || cpu_is_mx27()) {
> +			ret = request_irq(MX2x_INT_DMACH0 + i,
> +					dma_irq_handler, 0, "DMA", imxdma);
> +			if (ret) {
> +				pr_crit("Can't register IRQ %d for DMA channel %d\n",
> +						MX2x_INT_DMACH0 + i, i);
> +				goto err_init;
> +			}
> +			init_timer(&imxdmac->internal.watchdog);
> +			imxdmac->internal.watchdog.function = &imxdma_watchdog;
> +			imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
>  		}
>  
> -		imx_dma_setup_handlers(imxdmac->imxdma_channel,
> -		       imxdma_irq_handler, imxdma_err_handler, imxdmac);
> -
>  		imxdmac->imxdma = imxdma;
>  		spin_lock_init(&imxdmac->lock);
>  
> @@ -617,10 +1113,8 @@ static int __init imxdma_probe(struct platform_device *pdev)
>  	return 0;
>  
>  err_init:
> -	while (--i >= 0) {
> -		struct imxdma_channel *imxdmac = &imxdma->channel[i];
> -		imx_dma_free(imxdmac->imxdma_channel);
> -	}
> +	while (--i >= 0)
> +		free_irq(MX2x_INT_DMACH0 + i, NULL);
>  
>  	kfree(imxdma);
>  	return ret;
> @@ -633,11 +1127,8 @@ static int __exit imxdma_remove(struct platform_device *pdev)
>  
>          dma_async_device_unregister(&imxdma->dma_device);
>  
> -	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
> -		struct imxdma_channel *imxdmac = &imxdma->channel[i];
> -
> -		 imx_dma_free(imxdmac->imxdma_channel);
> -	}
> +	for (i = 0; i < MAX_DMA_CHANNELS; i++)
> +		free_irq(MX2x_INT_DMACH0 + i, NULL);
>  
>          kfree(imxdma);
>  


-- 
~Vinod



From thierry.reding at avionic-design.de  Wed Mar  7 01:38:29 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 7 Mar 2012 07:38:29 +0100
Subject: [PATCH/RFC 2/2] arm/tegra: add timeout to PCIe PLL lock
 detection loop
In-Reply-To: <1331023544-6439-3-git-send-email-mad_soft@inbox.ru>
References: <1331023544-6439-1-git-send-email-mad_soft@inbox.ru>
 <1331023544-6439-3-git-send-email-mad_soft@inbox.ru>
Message-ID: <20120307063829.GA16359@avionic-0098.mockup.avionic-design.de>

* Dmitry Artamonow wrote:
[...]
> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
[...]
> @@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
>  	pads_writel(0xfa5cfa5c, 0xc8);
>  
>  	/* Wait for the PLL to lock */
> +	timeout = 2000;

FWIW, the Vibrante kernel uses 300 for the timeout value.

Thierry
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From gxt at mprc.pku.edu.cn  Wed Mar  7 01:52:43 2012
From: gxt at mprc.pku.edu.cn (Guan Xuetao)
Date: Wed, 07 Mar 2012 14:52:43 +0800
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1331103163.2048.33.camel@epip-laptop>

On Tue, 2012-03-06 at 17:30 -0700, Stephen Warren wrote:
> This allows the user to use U-Boot's mkimage's -T kernel_noload option
> if their arch Kconfig allows it, and they desire.
> 
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> ---
> The next patch enables this new CONFIG_ALLOW_ option for ARM. I assume
> that some other architectures will also be able to enable it, but I'm
> not familiar enough with any to know which.
> 
>  init/Kconfig         |   15 +++++++++++++++
>  scripts/Makefile.lib |   15 ++++++++++++---
>  2 files changed, 27 insertions(+), 3 deletions(-)
> 
> diff --git a/init/Kconfig b/init/Kconfig
> index 6cfd71d..2035562 100644
> --- a/init/Kconfig
> +++ b/init/Kconfig
> @@ -203,6 +203,21 @@ config KERNEL_LZO
>  
>  endchoice
>  
> +config ALLOW_UIMAGE_KERNEL_NOLOAD
> +	bool
> +
> +config UIMAGE_KERNEL_NOLOAD
> +	bool "Use mkimage's -T kernel_noload instead of -T kernel"
> +	depends on ALLOW_UIMAGE_KERNEL_NOLOAD
> +	help
> +	  uImage files of type "kernel" embed an absolute load and entry point
> +	  address. If the uImage is loaded to a different address, then the
> +	  image must be copied the uImage file to the specified load address.
> +	  This copy is a waste of time if the uImage is in fact completely
> +	  relocatable. If your kernel and bootloader support it, you can build
> +	  a "kernel_noload" uImage rather than a "kernel" uImage, which
> +	  prevents any such copying. If unsure say N.
> +
>  config DEFAULT_HOSTNAME
>  	string "Default hostname"
>  	default "(none)"
> diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
> index 7b0be18..d9c1c87 100644
> --- a/scripts/Makefile.lib
> +++ b/scripts/Makefile.lib
> @@ -314,9 +314,18 @@ MKIMAGE := $(srctree)/scripts/mkuboot.sh
>  UIMAGE_ARCH = $(SRCARCH)
>  UIMAGE_COMPRESSION = $(if $(2),$(2),none)
>  UIMAGE_OPTS-y =
> -UIMAGE_TYPE = kernel
> -UIMAGE_LOADADDR=arch_must_set_this
> -UIMAGE_ENTRYADDR=$(UIMAGE_LOADADDR)
> +ifeq ($(CONFIG_UIMAGE_KERNEL_NOLOAD),y)
> +  UIMAGE_TYPE = kernel_noload
> +  # Unused by bootloader:
> +  UIMAGE_LOADADDR=0
> +  # Entry point relative to actual load address:
> +  UIMAGE_ENTRYADDR=0
> +else
> +  UIMAGE_TYPE = kernel
> +  # Absolute addresses:
> +  UIMAGE_LOADADDR=arch_must_set_this
> +  UIMAGE_ENTRYADDR=$(UIMAGE_LOADADDR)
> +endif
>  UIMAGE_NAME = 'Linux-$(KERNELRELEASE)'
>  UIMAGE_IN = $<
>  UIMAGE_OUT = $@
Hi, Stephen,
It seems that UIMAGE_ARCH and UIMAGE_LOADADDR can't be modified from
arch-Makefiles.

Regards,

Guan Xuetao



From vdumpa at nvidia.com  Wed Mar  7 02:06:13 2012
From: vdumpa at nvidia.com (Krishna Reddy)
Date: Tue, 6 Mar 2012 23:06:13 -0800
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <20120307.083706.2087121294965856946.hdoyu@nvidia.com>
References: <000001ccfaea$00c16f70$02444e50$%szyprowski@samsung.com><401E54CE964CD94BAE1EB4A729C7087E37970113FE@HQMAIL04.nvidia.com><20120307.080952.2152478004740487196.hdoyu@nvidia.com>
 <20120307.083706.2087121294965856946.hdoyu@nvidia.com>
Message-ID: <401E54CE964CD94BAE1EB4A729C7087E37973BEA74@HQMAIL04.nvidia.com>

> > > It should be as follows.
> > > unsigned int count = 1 << get_order(size) - order;
> 
> To be precise, as below?
> 
>  unsigned int count = 1 << (get_order(size) - order);

Minus has more precedence than left shift.
"1 << get_order(size) - order;" is equivalent to 1 << (get_order(size) - order);

-KR
--nvpublic


From hdoyu at nvidia.com  Wed Mar  7 02:16:01 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Wed, 7 Mar 2012 08:16:01 +0100
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <20120307.083706.2087121294965856946.hdoyu@nvidia.com>
References: <401E54CE964CD94BAE1EB4A729C7087E37970113FE@HQMAIL04.nvidia.com><20120307.080952.2152478004740487196.hdoyu@nvidia.com><20120307.083706.2087121294965856946.hdoyu@nvidia.com>
Message-ID: <20120307.091601.458605132780655792.hdoyu@nvidia.com>

From: Hiroshi DOYU <hdoyu at nvidia.com>
Subject: Re: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
Date: Wed, 07 Mar 2012 08:37:06 +0200 (EET)
Message-ID: <20120307.083706.2087121294965856946.hdoyu at nvidia.com>

> From: Hiroshi DOYU <hdoyu at nvidia.com>
> Subject: Re: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
> Date: Wed, 07 Mar 2012 08:09:52 +0200 (EET)
> Message-ID: <20120307.080952.2152478004740487196.hdoyu at nvidia.com>
> 
> > From: Krishna Reddy <vdumpa at nvidia.com>
> > Subject: RE: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
> > Date: Tue, 6 Mar 2012 23:48:42 +0100
> > Message-ID: <401E54CE964CD94BAE1EB4A729C7087E37970113FE at HQMAIL04.nvidia.com>
> > 
> > > > > +struct dma_iommu_mapping *
> > > > > +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
> > > > > +                        int order)
> > > > > +{
> > > > > +       unsigned int count = (size >> PAGE_SHIFT) - order;
> > > > > +       unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
> > > 
> > > The count calculation doesn't seem correct. "order" is log2 number and
> > >  size >> PAGE_SHIFT is number of pages. 
> > > 
> > > If size is passed as 64*4096(256KB) and order is 6(allocation granularity is 2^6 pages=256KB),
> > >  just 1 bit is enough to manage allocations.  So it should be 4 bytes or one long.
> > 
> > Good catch!
> > 
> > > But the calculation gives count = 64 - 6 = 58 and 
> > > Bitmap_size gets set to (58/(4*8)) * 4 = 8 bytes, which is incorrect.
> > 
> > "order" isn't the order of size passed, which is minimal *page*
> > allocation order which client decides whatever, just in case.
> > 
> > > It should be as follows.
> > > unsigned int count = 1 << get_order(size) - order;
> 
> To be precise, as below?
> 
>  unsigned int count = 1 << (get_order(size) - order);

This could be:

>From fd40740ef4bc4a3924fe1188ea6dd785be0fe859 Mon Sep 17 00:00:00 2001
From: Hiroshi DOYU <hdoyu at nvidia.com>
Date: Wed, 7 Mar 2012 08:14:38 +0200
Subject: [PATCH 1/1] dma-mapping: Fix count calculation of iova space

Fix count calculation of iova space.
Pointed by Krishna Reddy <vdumpa at nvidia.com>

Signed-off-by: Hiroshi DOYU <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 6c2f104..56f0af5 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1483,11 +1483,18 @@ struct dma_iommu_mapping *
 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
 			 int order)
 {
-	unsigned int count = (size >> PAGE_SHIFT) - order;
-	unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
+	unsigned int n, count;
+	unsigned int bitmap_size;
 	struct dma_iommu_mapping *mapping;
 	int err = -ENOMEM;
 
+	n = get_order(size);
+	if (n < order)
+		return ERR_PTR(-EINVAL);
+
+	count = 1 << (n - order);
+	bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
+
 	mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
 	if (!mapping)
 		goto err;
-- 
1.7.5.4


From javier.martin at vista-silicon.com  Wed Mar  7 02:52:40 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Wed, 7 Mar 2012 08:52:40 +0100
Subject: [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with
 imx-dma.c
In-Reply-To: <1331102571.24656.324.camel@vkoul-udesk3>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
 <1330964196-32623-2-git-send-email-javier.martin@vista-silicon.com>
 <1331102571.24656.324.camel@vkoul-udesk3>
Message-ID: <CACKLOr0iBSMd8hNdmeAiMWgyyUb_b1=5n47N97hu9EP2Zu9OsQ@mail.gmail.com>

Hi Vinod,

On 7 March 2012 07:42, Vinod Koul <vinod.koul at intel.com> wrote:
> On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
> Sascha,
> Are there any more users of dmac in mach-imx?

No, there are no other users of mach-imx. In fact, it was Sascha's
idea to make this merge [1].

> If not then why not move the code, rather than copy.
> If yes can we move them as well?

I do remove the code in mach-imx in PATCH 14/14. I considered it was
better doing this in the last patch to keep the old code available
during the whole development process.

[1] https://lkml.org/lkml/2012/2/9/171

-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From arnd at arndb.de  Wed Mar  7 02:58:48 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 7 Mar 2012 07:58:48 +0000
Subject: [PATCH v3 1/6] serial: pxa: add OF support
In-Reply-To: <1331084525-4638-1-git-send-email-haojian.zhuang@gmail.com>
References: <201203061502.08097.arnd@arndb.de>
 <1331084525-4638-1-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <201203070758.48948.arnd@arndb.de>

On Wednesday 07 March 2012, Haojian Zhuang wrote:
> From: Haojian Zhuang <haojian.zhuang at marvell.com>
> 
> Parse uart device id from alias in DTS file.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>

Looks good now,

Reviewed-by: Arnd Bergmann <arnd at arndb.de>


From vinod.koul at intel.com  Wed Mar  7 03:03:57 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Wed, 07 Mar 2012 13:33:57 +0530
Subject: [PATCH 04/14] dmaengine: imx-dma: remove
 'imxdma_setup_mem2mem_hw' function.
In-Reply-To: <1330964196-32623-5-git-send-email-javier.martin@vista-silicon.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
 <1330964196-32623-5-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331107437.24656.325.camel@vkoul-udesk3>

On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
will help to know in change log why you are doing this...

> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> ---
>  drivers/dma/imx-dma.c |   57 ++++++++++++-------------------------------------
>  1 files changed, 14 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
> index 2c524e1..8a0afb1 100644
> --- a/drivers/dma/imx-dma.c
> +++ b/drivers/dma/imx-dma.c
> @@ -260,41 +260,6 @@ static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
>  	return now;
>  }
>  
> -static int
> -imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
> -		     unsigned int dma_length, unsigned int dev_addr)
> -{
> -	int channel = imxdmac->channel;
> -
> -	imxdmac->internal.sg = NULL;
> -
> -	if (!dma_address) {
> -		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
> -		       channel);
> -		return -EINVAL;
> -	}
> -
> -	if (!dma_length) {
> -		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
> -		       channel);
> -		return -EINVAL;
> -	}
> -
> -	pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
> -		"dev_addr=0x%08x for write\n",
> -		channel, __func__, (unsigned int)dma_address,
> -		dma_length, dev_addr);
> -
> -	imx_dmav1_writel(dma_address, DMA_SAR(channel));
> -	imx_dmav1_writel(dev_addr, DMA_DAR(channel));
> -	imx_dmav1_writel(imxdmac->internal.ccr_to_device,
> -			 DMA_CCR(channel));
> -
> -	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
> -
> -	return 0;
> -}
> -
>  static void imxdma_enable_hw(struct imxdma_desc *d)
>  {
>  	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
> @@ -586,20 +551,26 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
>  static int imxdma_xfer_desc(struct imxdma_desc *d)
>  {
>  	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
> +	struct imxdma_engine *imxdma = imxdmac->imxdma;
>  	int ret;
>  
>  	/* Configure and enable */
>  	switch (d->type) {
>  	case IMXDMA_DESC_MEMCPY:
> -		ret = imxdma_config_channel_hw(imxdmac,
> -					  d->config_port, d->config_mem, 0, 0);
> -		if (ret < 0)
> -			return ret;
> -		ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
> -		if (ret < 0)
> -			return ret;
> -		break;
> +		imxdmac->internal.sg = NULL;
> +
> +		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
> +		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
> +		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
> +			 DMA_CCR(imxdmac->channel));
>  
> +		imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
> +
> +		dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
> +			"dma_length=%d\n", __func__, imxdmac->channel,
> +			d->dest, d->src, d->len);
> +
> +		break;
>  	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
>  	case IMXDMA_DESC_CYCLIC:
>  	case IMXDMA_DESC_SLAVE_SG:


-- 
~Vinod



From plagnioj at jcrosoft.com  Wed Mar  7 02:46:24 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 08:46:24 +0100
Subject: Pre-merge-window status of the arm-soc tree
In-Reply-To: <201203062054.55434.arnd@arndb.de>
References: <201203062054.55434.arnd@arndb.de>
Message-ID: <20120307074624.GH21255@game.jcrosoft.org>

> 
> Notably absent here are still mach-msm and mach-shmobile and some
> platforms have more patches pending. If you have anything that you
> want to get included in 3.4, then now would be a good time to send
> that. Anything that is not in arm-soc by the time the merge window
> opens is not going to make it into the release, and you should allow
> a little bit of time to sort out any conflicts between sending pull
> requests and having them in the branch.
I've much more to send to pull for AT91 DT but all depends on 2 patches
acked by not pulled so far for of

Grant can I apply it via AT91 (of boolean support and nand generic binding)
as I need them for
NAND
USB device
I2C
Shutdown Controller support
RAM Controller
Reset Controller
USB Host

Best Regards,
J.


From vinod.koul at intel.com  Wed Mar  7 03:15:58 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Wed, 07 Mar 2012 13:45:58 +0530
Subject: [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with
 imx-dma.c
In-Reply-To: <CACKLOr0iBSMd8hNdmeAiMWgyyUb_b1=5n47N97hu9EP2Zu9OsQ@mail.gmail.com>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
 <1330964196-32623-2-git-send-email-javier.martin@vista-silicon.com>
 <1331102571.24656.324.camel@vkoul-udesk3>
 <CACKLOr0iBSMd8hNdmeAiMWgyyUb_b1=5n47N97hu9EP2Zu9OsQ@mail.gmail.com>
Message-ID: <1331108158.24656.330.camel@vkoul-udesk3>

On Wed, 2012-03-07 at 08:52 +0100, javier Martin wrote:
> Hi Vinod,
> 
> On 7 March 2012 07:42, Vinod Koul <vinod.koul at intel.com> wrote:
> > On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
> > Sascha,
> > Are there any more users of dmac in mach-imx?
> 
> No, there are no other users of mach-imx. In fact, it was Sascha's
> idea to make this merge [1].
Then please move the file in 1st patch, also it would be easily clear
what parts are added, deleted and moved.

Otherwise the series looks fine except that it needs to have a better
changelog on why you are removing certain field/struct. It helps to
document the motivation of doing certain change, you will find that you
wont remember that six months down the line :)

Also I am looking for Tested-By from people who have use imx-dma.

> 
> > If not then why not move the code, rather than copy.
> > If yes can we move them as well?
> 
> I do remove the code in mach-imx in PATCH 14/14. I considered it was
> better doing this in the last patch to keep the old code available
> during the whole development process.
> 
> [1] https://lkml.org/lkml/2012/2/9/171
> 


-- 
~Vinod



From linus.walleij at linaro.org  Wed Mar  7 03:33:49 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 7 Mar 2012 09:33:49 +0100
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <CACRpkdYry6G4gi7LdVM4gYOQBKZCoQxdzLAGg1WcjB6rVD-PPQ@mail.gmail.com>

On Tue, Mar 6, 2012 at 11:33 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:

> This patch series cleans up the handling of cookies in DMA engine drivers.
> This is done by providing a set of inline library functions for common
> tasks:

I just applied the latest patches right off and tested with some stressy
MMC operations on the U300 and Ux500. (I had some minor hell
since patch 8/9 and 9/9 were uuencoded but managed to fix it...)

It works like a charm!

The patches look good too.

Tested-by: Linus Walleij <linus.walleij at linaro.org>
Reviewed-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From s.hauer at pengutronix.de  Wed Mar  7 03:37:36 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 7 Mar 2012 09:37:36 +0100
Subject: [PATCH v2 17/17] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <20120306155055.GA13802@S2101-09.ap.freescale.net>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-18-git-send-email-shawn.guo@linaro.org>
 <20120305174232.GA3852@pengutronix.de>
 <20120306155055.GA13802@S2101-09.ap.freescale.net>
Message-ID: <20120307083736.GK3852@pengutronix.de>

On Tue, Mar 06, 2012 at 11:50:57PM +0800, Shawn Guo wrote:
> On Mon, Mar 05, 2012 at 06:42:32PM +0100, Sascha Hauer wrote:
> > On Mon, Mar 05, 2012 at 10:31:05PM +0800, Shawn Guo wrote:
> > > This is the initial imx-sgtl5000 machine driver support with only
> > > playback dai link implemented.  More features can be added on top
> > > of it later.
> > 
> > Are there problems with capturing? It should be trivial to add and
> > it would be much more confident that this series as a whole works as
> > expected.
> > 
> I worked all day long to try to give that answer.  Here it is.
> 
> No, there is no problem with capturing on fsl_ssi + imx_pcm_dma +
> imx_sgtl5000 side.  But there is a problem with sgtl5000 codec driver.
> With that problem fixed in sgtl5000, this series works just fine with
> capturing.  (I'm not sure I want to fix it within this series though,
> as it's already big enough.)

Thanks a lot for testing this. In this case I'm fine with this series
and can likely Ack your next iteration. You can skip capture support
from this series as you said it's big enough. It's enough for me when
you say it works on your branch.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From plagnioj at jcrosoft.com  Wed Mar  7 03:28:40 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 09:28:40 +0100
Subject: [PATCH 1/5 v2] i2c/gpio: add DT support
In-Reply-To: <1330525221-25651-1-git-send-email-plagnioj@jcrosoft.com>
References: <1330525221-25651-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120307082840.GI21255@game.jcrosoft.org>

On 15:20 Wed 29 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-i2c at vger.kernel.org
> Cc: devicetree-discuss at lists.ozlabs.org
> ---
> v2:
> 
> 	use devm_kzalloc
> 	use i2c-gpio
> 	use time name in the properties
 is ok?

I need this for 3.4

Best Regars,
J.
>  .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 +++++++
>  drivers/i2c/busses/i2c-gpio.c                      |   95 +++++++++++++++----
>  2 files changed, 107 insertions(+), 20 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> new file mode 100644
> index 0000000..27e1b1a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> @@ -0,0 +1,32 @@
> +Device-Tree bindings for i2c gpio driver
> +
> +Required properties:
> +	- compatible = "i2c-gpio";
> +	- gpios: sda and scl gpio
> +
> +
> +Optional properties:
> +	- i2c-gpio,sda-open-drain: sda as open drain
> +	- i2c-gpio,scl-open-drain: scl as open drain
> +	- i2c-gpio,scl-output-only: scl as output only
> +	- udelay: delay between GPIO operations (may depend on each platform)
> +	- i2c-algo-bit,timeout-milliseconds: timeout to get data
> +
> +Example nodes:
> +
> +i2c-gpio at 0 {
> +	compatible = "i2c-gpio";
> +	gpios = <&pioA 23 0 /* sda */
> +		 &pioA 24 0 /* scl */
> +		>;
> +	i2c-gpio,sda-open-drain;
> +	i2c-gpio,scl-open-drain;
> +	udelay = <2>;		/* ~100 kHz */
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	rv3029c2 at 56 {
> +		compatible = "rv3029c2";
> +		reg = <0x56>;
> +	};
> +};
> diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
> index a651779..71adba5 100644
> --- a/drivers/i2c/busses/i2c-gpio.c
> +++ b/drivers/i2c/busses/i2c-gpio.c
> @@ -14,8 +14,15 @@
>  #include <linux/module.h>
>  #include <linux/slab.h>
>  #include <linux/platform_device.h>
> +#include <linux/gpio.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_i2c.h>
>  
> -#include <asm/gpio.h>
> +struct i2c_gpio_private_data {
> +	struct i2c_adapter adap;
> +	struct i2c_algo_bit_data bit_data;
> +	struct i2c_gpio_platform_data pdata;
> +};
>  
>  /* Toggle SDA by changing the direction of the pin */
>  static void i2c_gpio_setsda_dir(void *data, int state)
> @@ -78,24 +85,63 @@ static int i2c_gpio_getscl(void *data)
>  	return gpio_get_value(pdata->scl_pin);
>  }
>  
> +static int __devinit of_i2c_gpio_probe(struct device_node *np,
> +			     struct i2c_gpio_platform_data *pdata)
> +{
> +	u32 reg;
> +
> +	if (of_gpio_count(np) < 2)
> +		return -ENODEV;
> +
> +	pdata->sda_pin = of_get_gpio(np, 0);
> +	pdata->scl_pin = of_get_gpio(np, 1);
> +
> +	if (pdata->sda_pin < 0 || pdata->scl_pin < 0) {
> +		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
> +		       np->full_name, pdata->sda_pin, pdata->scl_pin);
> +		return -ENODEV;
> +	}
> +
> +	if (of_property_read_u32(np, "udelay", &reg))
> +		pdata->udelay = reg;
> +
> +	if (of_property_read_u32(np, "i2c-algo-bit,timeout-milliseconds", &reg))
> +		pdata->timeout = msecs_to_jiffies(reg);
> +
> +	pdata->sda_is_open_drain =
> +		!!of_property_read_bool(np, "i2c-gpio,sda-open-drain");
> +	pdata->scl_is_open_drain =
> +		!!of_property_read_bool(np, "i2c-gpio,scl-open-drain");
> +	pdata->scl_is_output_only =
> +		!!of_property_read_bool(np, "i2c-gpio,scl-output-only");
> +
> +	return 0;
> +}
> +
>  static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  {
> +	struct i2c_gpio_private_data *priv;
>  	struct i2c_gpio_platform_data *pdata;
>  	struct i2c_algo_bit_data *bit_data;
>  	struct i2c_adapter *adap;
>  	int ret;
>  
> -	pdata = pdev->dev.platform_data;
> -	if (!pdata)
> -		return -ENXIO;
> +	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +	adap = &priv->adap;
> +	bit_data = &priv->bit_data;
> +	pdata = &priv->pdata;
>  
> -	ret = -ENOMEM;
> -	adap = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
> -	if (!adap)
> -		goto err_alloc_adap;
> -	bit_data = kzalloc(sizeof(struct i2c_algo_bit_data), GFP_KERNEL);
> -	if (!bit_data)
> -		goto err_alloc_bit_data;
> +	if (pdev->dev.of_node) {
> +		ret = of_i2c_gpio_probe(pdev->dev.of_node, pdata);
> +		if (ret)
> +			return ret;
> +	} else {
> +		if (!pdev->dev.platform_data)
> +			return -ENXIO;
> +		memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
> +	}
>  
>  	ret = gpio_request(pdata->sda_pin, "sda");
>  	if (ret)
> @@ -143,6 +189,7 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  	adap->algo_data = bit_data;
>  	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
>  	adap->dev.parent = &pdev->dev;
> +	adap->dev.of_node = pdev->dev.of_node;
>  
>  	/*
>  	 * If "dev->id" is negative we consider it as zero.
> @@ -154,7 +201,9 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto err_add_bus;
>  
> -	platform_set_drvdata(pdev, adap);
> +	of_i2c_register_devices(adap);
> +
> +	platform_set_drvdata(pdev, priv);
>  
>  	dev_info(&pdev->dev, "using pins %u (SDA) and %u (SCL%s)\n",
>  		 pdata->sda_pin, pdata->scl_pin,
> @@ -168,34 +217,40 @@ err_add_bus:
>  err_request_scl:
>  	gpio_free(pdata->sda_pin);
>  err_request_sda:
> -	kfree(bit_data);
> -err_alloc_bit_data:
> -	kfree(adap);
> -err_alloc_adap:
>  	return ret;
>  }
>  
>  static int __devexit i2c_gpio_remove(struct platform_device *pdev)
>  {
> +	struct i2c_gpio_private_data *priv;
>  	struct i2c_gpio_platform_data *pdata;
>  	struct i2c_adapter *adap;
>  
> -	adap = platform_get_drvdata(pdev);
> -	pdata = pdev->dev.platform_data;
> +	priv = platform_get_drvdata(pdev);
> +	adap = &priv->adap;
> +	pdata = &priv->pdata;
>  
>  	i2c_del_adapter(adap);
>  	gpio_free(pdata->scl_pin);
>  	gpio_free(pdata->sda_pin);
> -	kfree(adap->algo_data);
> -	kfree(adap);
>  
>  	return 0;
>  }
>  
> +#if defined(CONFIG_OF)
> +static const struct of_device_id i2c_gpio_dt_ids[] = {
> +	{ .compatible = "i2c-gpio", },
> +	{ /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, i2c_gpio_dt_ids);
> +#endif
> +
>  static struct platform_driver i2c_gpio_driver = {
>  	.driver		= {
>  		.name	= "i2c-gpio",
>  		.owner	= THIS_MODULE,
> +		.of_match_table	= of_match_ptr(i2c_gpio_dt_ids),
>  	},
>  	.probe		= i2c_gpio_probe,
>  	.remove		= __devexit_p(i2c_gpio_remove),
> -- 
> 1.7.7
> 


From plagnioj at jcrosoft.com  Wed Mar  7 03:29:45 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 09:29:45 +0100
Subject: [PULL] of nand generic binding
In-Reply-To: <20120229152534.GH3318@game.jcrosoft.org>
References: <20120217155707.GR1214@game.jcrosoft.org>
 <20120229152534.GH3318@game.jcrosoft.org>
Message-ID: <20120307082945.GJ21255@game.jcrosoft.org>

On 16:25 Wed 29 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 16:57 Fri 17 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> > HI,
> > 
> > 	please find attached the generic binding for the MTD nand
> > 
> > 	This will add boolean and nand helpers
> is it ok?
I need this for 3.4

will you apply it or can I apply it via AT91

Best Regards,
J.


From linus.walleij at linaro.org  Wed Mar  7 03:40:31 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 7 Mar 2012 09:40:31 +0100
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <alpine.LFD.2.02.1203061146210.31242@xanadu.home>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201202281945.39419.arnd@arndb.de>
 <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
 <201203061412.00073.arnd@arndb.de>
 <alpine.LFD.2.02.1203061146210.31242@xanadu.home>
Message-ID: <CACRpkdYQpnSMVWUizEYHTjx_AK5Ai7dos0SBd208Wf5ZJLdrCw@mail.gmail.com>

On Tue, Mar 6, 2012 at 5:51 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Tue, 6 Mar 2012, Arnd Bergmann wrote:
>> Interestingly, that leaves ixp4xx as the only big-endian ARM platform.
>> I believe that ixp4xx is still being actively used quite a bit, but does
>> that include the big-endian ones? There is no immediate reason why we
>> would want to drop support for big-endian, but if it's not used at all,
>> that would be an interesting cleanup opportunity.
>
> The NSLU2 is (was) a quite popular NAS device and it is used in big
> endian by default.
>
> The BE support isn't getting in the way of anything, so there is no
> reason to remove it, even if it isn't being used much.

Network equipment seems to like using BE.

I have some vague idea that this is beacuse IP packets are big
endian, and thus you can process them quickly by just casting fields
to e.g. u32 pointers and read them.

I don't know if this is true, but seems to much of a correlation to
be pure coincidence. Thus a pretty interesting subject in
embedded ARM not used for tablets/mobile/generic computing
kind of stuff.

Yours,
Linus Walleij


From linus.walleij at linaro.org  Wed Mar  7 03:49:39 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 7 Mar 2012 09:49:39 +0100
Subject: AMBA devices behing a PCI bridge
In-Reply-To: <20120222191339.GA28388@mail.gnudd.com>
References: <20120222191339.GA28388@mail.gnudd.com>
Message-ID: <CACRpkdYv02sNAcTSPgW-aq8iL6mAhcY2XTDV1BztPS_NvYqYXA@mail.gmail.com>

On Wed, Feb 22, 2012 at 8:13 PM, Alessandro Rubini <ru at gnudd.com> wrote:

> Hello Russell.
> I'm working, with some mates, on a device which is basically a bridge
> from PCIe to AMBA.
>
> Some of the peripherals that live behind the bridge are actually
> normal primecell devices, with minor or no modifications from the
> original ARM cores. The list includes dma, uart, spi, i2c and mmc.

Just watching from the side this is very interesting, and of course it is
wise to reuse the existing PrimeCell drivers, given the effort that has
been put into maintaining and generalizing them over the last few
years.

Thanks for looking into this and I'll be happy to help out with the
review!

Yours,
Linus Walleij


From plagnioj at jcrosoft.com  Wed Mar  7 03:49:24 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 09:49:24 +0100
Subject: [PATCH 0/9 v2] at91 USB DT support
Message-ID: <20120307084924.GK21255@game.jcrosoft.org>

HI,

	this is a second version of the patch series to add DT suport for
	usb host and device on at91


The following changes since commit 3370718be26d86e7f8587390eee563c289542ee7:

  ARM: at91/dt: add Calao DAB-MMX daugther board support for USB-A9G20 (2012-03-02 00:46:21 +0800)

are available in the git repository at:
  git at github.com:at91linux/linux-at91.git ..BRANCH.NOT.VERIFIED..

Jean-Christophe PLAGNIOL-VILLARD (9):
      ARM: at91: usb ohci add dt support
      ARM: at91: dt: enable usb ohci for sam9g20, sam9g45 amd sam9x5
      ARM: at91: usb ehci add dt support
      ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5
      USB: at91: Device udc add dt support
      ARM: at91: sam9g20 udc add dt support
      usb: add Atmel USBA UDC DT support
      ARM: at91: sam9g45 add udc DT support
      ARM: at91: sam9x5 add udc DT support

 .../devicetree/bindings/usb/atmel-usb.txt          |  135 +++++++++++++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |   14 ++
 arch/arm/boot/dts/at91sam9g25ek.dts                |   17 ++
 arch/arm/boot/dts/at91sam9g45.dtsi                 |   80 ++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts             |   15 ++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |   81 ++++++++
 arch/arm/boot/dts/usb_a9g20.dts                    |   10 +
 arch/arm/mach-at91/at91sam9260.c                   |    1 +
 arch/arm/mach-at91/at91sam9g45.c                   |    4 +
 arch/arm/mach-at91/at91sam9x5.c                    |    7 +-
 drivers/usb/Kconfig                                |    2 +-
 drivers/usb/gadget/Kconfig                         |    4 +-
 drivers/usb/gadget/at91_udc.c                      |   40 ++++-
 drivers/usb/gadget/atmel_usba_udc.c                |  209 +++++++++++++++-----
 drivers/usb/gadget/atmel_usba_udc.h                |    1 +
 drivers/usb/host/ehci-atmel.c                      |   24 +++-
 drivers/usb/host/ohci-at91.c                       |  101 ++++++++++-
 17 files changed, 688 insertions(+), 57 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/atmel-usb.txt

Best Regards,
J.


From egtvedt at samfundet.no  Wed Mar  7 04:00:17 2012
From: egtvedt at samfundet.no (Hans-Christian Egtvedt)
Date: Wed, 7 Mar 2012 10:00:17 +0100
Subject: [PATCH 1/3] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <20120307090017.GB17076@samfundet.no>

Around Tue 06 Mar 2012 17:30:36 -0700 or thereabout, Stephen Warren wrote:
> All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
> to avoid duplication.
> 
> All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
> parameterized version in Makefile.lib to avoid duplication.
> 
> The centralized cmd_uimage definition will allow the future introduction
> of a centralized Kconfig option to make cmd_uimage use -T kernel_noload
> rather than -T kernel.
> 
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> ---
> NOTE: I have not tested this patch in any way at all for architectures
> other than ARM.
> 
>  arch/arm/boot/Makefile          |   23 +++++++++--------------
>  arch/avr32/boot/images/Makefile |    9 +++------

For the AVR32 related changes

Acked-by: Hans-Christian Egtvedt <egtvedt at samfundet.no>

-- 
Best regards, Hans-Christian Egtvedt


From linux at arm.linux.org.uk  Wed Mar  7 04:06:40 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 09:06:40 +0000
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <CACRpkdYry6G4gi7LdVM4gYOQBKZCoQxdzLAGg1WcjB6rVD-PPQ@mail.gmail.com>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <CACRpkdYry6G4gi7LdVM4gYOQBKZCoQxdzLAGg1WcjB6rVD-PPQ@mail.gmail.com>
Message-ID: <20120307090640.GK17370@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 09:33:49AM +0100, Linus Walleij wrote:
> On Tue, Mar 6, 2012 at 11:33 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> 
> > This patch series cleans up the handling of cookies in DMA engine drivers.
> > This is done by providing a set of inline library functions for common
> > tasks:
> 
> I just applied the latest patches right off and tested with some stressy
> MMC operations on the U300 and Ux500. (I had some minor hell
> since patch 8/9 and 9/9 were uuencoded but managed to fix it...)

That'll be some MTA deciding to change the encoding, probably because some
MTA spotted UTF-8 characters in the description and decided to convert to
base64.


From linux at arm.linux.org.uk  Wed Mar  7 04:14:09 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 09:14:09 +0000
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <CACRpkdYQpnSMVWUizEYHTjx_AK5Ai7dos0SBd208Wf5ZJLdrCw@mail.gmail.com>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201202281945.39419.arnd@arndb.de>
 <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
 <201203061412.00073.arnd@arndb.de>
 <alpine.LFD.2.02.1203061146210.31242@xanadu.home>
 <CACRpkdYQpnSMVWUizEYHTjx_AK5Ai7dos0SBd208Wf5ZJLdrCw@mail.gmail.com>
Message-ID: <20120307091409.GL17370@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 09:40:31AM +0100, Linus Walleij wrote:
> Network equipment seems to like using BE.
> 
> I have some vague idea that this is beacuse IP packets are big
> endian, and thus you can process them quickly by just casting fields
> to e.g. u32 pointers and read them.
> 
> I don't know if this is true, but seems to much of a correlation to
> be pure coincidence. Thus a pretty interesting subject in
> embedded ARM not used for tablets/mobile/generic computing
> kind of stuff.

ISTR Nicolas explained this to me as being an established thing in the
comms sector.  They expect BE and only understand BE.

I did point out that you end up with many more endian conversions by
going to BE, mainly because PCI is LE and all your PCI accesses have
to be endian-swapped.  So in terms of bandwidth, I'd expect an ARM
PCI platform running in BE mode to have worse throughput than a LE
PCI platform.

But... if BE allows the comms people to keep their warm fuzzy feeling
who are we to argue.


From javier.martin at vista-silicon.com  Wed Mar  7 04:25:19 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Wed, 7 Mar 2012 10:25:19 +0100
Subject: [PATCH 01/14] dmaengine: imx-dma: merge old dma-v1.c with
 imx-dma.c
In-Reply-To: <1331108158.24656.330.camel@vkoul-udesk3>
References: <1330964196-32623-1-git-send-email-javier.martin@vista-silicon.com>
 <1330964196-32623-2-git-send-email-javier.martin@vista-silicon.com>
 <1331102571.24656.324.camel@vkoul-udesk3>
 <CACKLOr0iBSMd8hNdmeAiMWgyyUb_b1=5n47N97hu9EP2Zu9OsQ@mail.gmail.com>
 <1331108158.24656.330.camel@vkoul-udesk3>
Message-ID: <CACKLOr1VHkLeCnUDcOEuBBjN5iY72ADvqXoNk0NR_N95fkd6Kg@mail.gmail.com>

On 7 March 2012 09:15, Vinod Koul <vinod.koul at intel.com> wrote:
> On Wed, 2012-03-07 at 08:52 +0100, javier Martin wrote:
>> Hi Vinod,
>>
>> On 7 March 2012 07:42, Vinod Koul <vinod.koul at intel.com> wrote:
>> > On Mon, 2012-03-05 at 17:16 +0100, Javier Martin wrote:
>> > Sascha,
>> > Are there any more users of dmac in mach-imx?
>>
>> No, there are no other users of mach-imx. In fact, it was Sascha's
>> idea to make this merge [1].
> Then please move the file in 1st patch, also it would be easily clear
> what parts are added, deleted and moved.

All right, I will, but I'll wait for Sascha and others to comment on
the series too.

> Otherwise the series looks fine except that it needs to have a better
> changelog on why you are removing certain field/struct. It helps to
> document the motivation of doing certain change, you will find that you
> wont remember that six months down the line :)

Thanks for the suggestion, I'll rewrite my changelogs.

> Also I am looking for Tested-By from people who have use imx-dma.

That would be awesome. I've tested this series with a test battery which covers:
- mxcmmc
- audio
- dmatest module


-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From plagnioj at jcrosoft.com  Wed Mar  7 04:15:38 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 10:15:38 +0100
Subject: [PATCH 1/9 v2] ARM: at91: usb ohci add dt support
In-Reply-To: <20120307084924.GK21255@game.jcrosoft.org>
References: <20120307084924.GK21255@game.jcrosoft.org>
Message-ID: <1331111746-21393-1-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Grant Likely <grant.likely at secretlab.ca>
Acked-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
---
 .../devicetree/bindings/usb/atmel-usb.txt          |   19 ++++
 drivers/usb/host/ohci-at91.c                       |  101 +++++++++++++++++++-
 2 files changed, 119 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/atmel-usb.txt

diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
new file mode 100644
index 0000000..6c7f728
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -0,0 +1,19 @@
+Atmel SOC USB controllers
+
+OHCI
+
+Required properties:
+ - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
+   used in host mode.
+ - num-ports: Number of ports.
+ - atmel,vbus-gpio: If present, specifies a gpio that needs to be
+   activated for the bus to be powered.
+ - atmel,oc-gpio: If present, specifies a gpio that needs to be
+   activated for the overcurrent detection.
+
+usb0: ohci at 00500000 {
+	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+	reg = <0x00500000 0x100000>;
+	interrupts = <20 4>;
+	num-ports = <2>;
+};
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 8e855eb..db8963f 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -14,6 +14,8 @@
 
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
 
 #include <mach/hardware.h>
 #include <asm/gpio.h>
@@ -477,13 +479,109 @@ static irqreturn_t ohci_hcd_at91_overcurrent_irq(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id at91_ohci_dt_ids[] = {
+	{ .compatible = "atmel,at91rm9200-ohci" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, at91_ohci_dt_ids);
+
+static u64 at91_ohci_dma_mask = DMA_BIT_MASK(32);
+
+static int __devinit ohci_at91_of_init(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	int i, ret, gpio;
+	enum of_gpio_flags flags;
+	struct at91_usbh_data	*pdata;
+	u32 ports;
+
+	if (!np)
+		return 0;
+
+	/* Right now device-tree probed devices don't get dma_mask set.
+	 * Since shared usb code relies on it, set it here for now.
+	 * Once we have dma capability bindings this can go away.
+	 */
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &at91_ohci_dma_mask;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	if (!of_property_read_u32(np, "num-ports", &ports))
+		pdata->ports = ports;
+
+	for (i = 0; i < 2; i++) {
+		gpio = of_get_named_gpio_flags(np, "atmel,vbus-gpio", i, &flags);
+		pdata->vbus_pin[i] = gpio;
+		if (!gpio_is_valid(gpio))
+			continue;
+		pdata->vbus_pin_active_low[i] = flags & OF_GPIO_ACTIVE_LOW;
+		ret = gpio_request(gpio, "ohci_vbus");
+		if (ret) {
+			dev_warn(&pdev->dev, "can't request vbus gpio %d", gpio);
+			continue;
+		}
+		ret = gpio_direction_output(gpio, !(flags & OF_GPIO_ACTIVE_LOW) ^ 1);
+		if (ret)
+			dev_warn(&pdev->dev, "can't put vbus gpio %d as output %d",
+				 !(flags & OF_GPIO_ACTIVE_LOW) ^ 1, gpio);
+	}
+
+	for (i = 0; i < 2; i++) {
+		gpio = of_get_named_gpio_flags(np, "atmel,oc-gpio", i, &flags);
+		pdata->overcurrent_pin[i] = gpio;
+		if (!gpio_is_valid(gpio))
+			continue;
+		ret = gpio_request(gpio, "ohci_overcurrent");
+		if (ret) {
+			dev_err(&pdev->dev, "can't request overcurrent gpio %d", gpio);
+			continue;
+		}
+
+		ret = gpio_direction_input(gpio);
+		if (ret) {
+			dev_err(&pdev->dev, "can't configure overcurrent gpio %d as input", gpio);
+			continue;
+		}
+
+		ret = request_irq(gpio_to_irq(gpio),
+				  ohci_hcd_at91_overcurrent_irq,
+				  IRQF_SHARED, "ohci_overcurrent", pdev);
+		if (ret) {
+			gpio_free(gpio);
+			dev_warn(& pdev->dev, "cannot get GPIO IRQ for overcurrent\n");
+		}
+	}
+
+	pdev->dev.platform_data = pdata;
+
+	return 0;
+}
+#else
+static int __devinit ohci_at91_of_init(struct platform_device *pdev)
+{
+	return 0;
+}
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 static int ohci_hcd_at91_drv_probe(struct platform_device *pdev)
 {
-	struct at91_usbh_data	*pdata = pdev->dev.platform_data;
+	struct at91_usbh_data	*pdata;
 	int			i;
 
+	i = ohci_at91_of_init(pdev);
+
+	if (i)
+		return i;
+
+	pdata = pdev->dev.platform_data;
+
 	if (pdata) {
 		for (i = 0; i < ARRAY_SIZE(pdata->vbus_pin); i++) {
 			if (!gpio_is_valid(pdata->vbus_pin[i]))
@@ -596,5 +694,6 @@ static struct platform_driver ohci_hcd_at91_driver = {
 	.driver		= {
 		.name	= "at91_ohci",
 		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(at91_ohci_dt_ids),
 	},
 };
-- 
1.7.7



From plagnioj at jcrosoft.com  Wed Mar  7 04:15:39 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 10:15:39 +0100
Subject: [PATCH 2/9 v2] ARM: at91: dt: enable usb ohci for sam9g20,
 sam9g45 amd sam9x5
In-Reply-To: <20120307084924.GK21255@game.jcrosoft.org>
References: <20120307084924.GK21255@game.jcrosoft.org>
Message-ID: <1331111746-21393-2-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9g20.dtsi     |    7 +++++++
 arch/arm/boot/dts/at91sam9g25ek.dts    |    8 ++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi     |    7 +++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts |    6 ++++++
 arch/arm/boot/dts/at91sam9x5.dtsi      |    7 +++++++
 arch/arm/boot/dts/usb_a9g20.dts        |    5 +++++
 arch/arm/mach-at91/at91sam9260.c       |    1 +
 arch/arm/mach-at91/at91sam9g45.c       |    1 +
 arch/arm/mach-at91/at91sam9x5.c        |    4 +++-
 9 files changed, 45 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index f803f31..8c5c175 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -188,6 +188,13 @@
 				>;
 			status = "disabled";
 		};
+
+		usb0: ohci at 00500000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00500000 0x100000>;
+			interrupts = <20 4>;
+			status = "disabled";
+		};
 	};
 
 	i2c-gpio at 0 {
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index c7596bf..93d5e36 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -33,5 +33,13 @@
 				status = "okay";
 			};
 		};
+
+		usb0: ohci at 00600000 {
+			status = "okay";
+			num-ports = <2>;
+			atmel,vbus-gpio = <&pioD 19 0
+					   &pioD 20 0
+					  >;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 93e095b..db9a51a 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -196,6 +196,13 @@
 				>;
 			status = "disabled";
 		};
+
+		usb0: ohci at 00700000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00700000 0x100000>;
+			interrupts = <22 4>;
+			status = "disabled";
+		};
 	};
 
 	i2c-gpio at 0 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 62ceffe..ce4640e 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -57,7 +57,13 @@
 				label = "data";
 				reg = <0x4000000 0xC000000>;
 			};
+		};
 
+		usb0: ohci at 00700000 {
+			status = "okay";
+			num-ports = <2>;
+			atmel,vbus-gpio = <&pioD 1 0
+					   &pioD 3 0>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index ad9570b..7b43014 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -187,6 +187,13 @@
 				>;
 			status = "disabled";
 		};
+
+		usb0: ohci at 00600000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x00600000 0x100000>;
+			interrupts = <22 4>;
+			status = "disabled";
+		};
 	};
 
 	i2c-gpio at 0 {
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 07012ca..55d0e54 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -73,6 +73,11 @@
 				reg = <0x7ca0000 0x8360000>;
 			};
 		};
+
+		usb0: ohci at 00500000 {
+			num-ports = <2>;
+			status = "okay";
+		};
 	};
 
 	leds {
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 14b5a9c..d1e5750 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -216,6 +216,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
 	CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
 	CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
+	CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 0014573..f58775e 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -232,6 +232,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	/* more tc lookup table for DT entries */
 	CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
+	CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 7bec5a4..40888ab 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -131,7 +131,7 @@ static struct clk dma1_clk = {
 	.type		= CLK_TYPE_PERIPHERAL,
 };
 static struct clk uhphs_clk = {
-	.name		= "uhphs_clk",
+	.name		= "uhphs",
 	.pmc_mask	= 1 << AT91SAM9X5_ID_UHPHS,
 	.type		= CLK_TYPE_PERIPHERAL,
 };
@@ -230,6 +230,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	/* additional fake clock for macb_hclk */
 	CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
 	CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
+	CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
+	CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
 };
 
 /*
-- 
1.7.7



From plagnioj at jcrosoft.com  Wed Mar  7 04:15:40 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 10:15:40 +0100
Subject: [PATCH 3/9 v2] ARM: at91: usb ehci add dt support
In-Reply-To: <20120307084924.GK21255@game.jcrosoft.org>
References: <20120307084924.GK21255@game.jcrosoft.org>
Message-ID: <1331111746-21393-3-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-usb at vger.kernel.org
Acked-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
---
 .../devicetree/bindings/usb/atmel-usb.txt          |   12 ++++++++++
 drivers/usb/host/ehci-atmel.c                      |   24 +++++++++++++++++++-
 2 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index 6c7f728..0143d7c 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -17,3 +17,15 @@ usb0: ohci at 00500000 {
 	interrupts = <20 4>;
 	num-ports = <2>;
 };
+
+EHCI
+
+Required properties:
+ - compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers
+   used in host mode.
+
+usb1: ehci at 00800000 {
+	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+	reg = <0x00800000 0x100000>;
+	interrupts = <22 4>;
+};
diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
index a5a3ef1..19f318a 100644
--- a/drivers/usb/host/ehci-atmel.c
+++ b/drivers/usb/host/ehci-atmel.c
@@ -13,6 +13,7 @@
 
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/of_platform.h>
 
 /* interface and function clocks */
 static struct clk *iclk, *fclk;
@@ -115,6 +116,8 @@ static const struct hc_driver ehci_atmel_hc_driver = {
 	.clear_tt_buffer_complete	= ehci_clear_tt_buffer_complete,
 };
 
+static u64 at91_ehci_dma_mask = DMA_BIT_MASK(32);
+
 static int __devinit ehci_atmel_drv_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd;
@@ -137,6 +140,13 @@ static int __devinit ehci_atmel_drv_probe(struct platform_device *pdev)
 		goto fail_create_hcd;
 	}
 
+	/* Right now device-tree probed devices don't get dma_mask set.
+	 * Since shared usb code relies on it, set it here for now.
+	 * Once we have dma capability bindings this can go away.
+	 */
+	if (!pdev->dev.dma_mask)
+		pdev->dev.dma_mask = &at91_ehci_dma_mask;
+
 	hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
 	if (!hcd) {
 		retval = -ENOMEM;
@@ -225,9 +235,21 @@ static int __devexit ehci_atmel_drv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id atmel_ehci_dt_ids[] = {
+	{ .compatible = "atmel,at91sam9g45-ehci" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, atmel_ehci_dt_ids);
+#endif
+
 static struct platform_driver ehci_atmel_driver = {
 	.probe		= ehci_atmel_drv_probe,
 	.remove		= __devexit_p(ehci_atmel_drv_remove),
 	.shutdown	= usb_hcd_platform_shutdown,
-	.driver.name	= "atmel-ehci",
+	.driver		= {
+		.name	= "atmel-ehci",
+		.of_match_table	= of_match_ptr(atmel_ehci_dt_ids),
+	},
 };
-- 
1.7.7



From plagnioj at jcrosoft.com  Wed Mar  7 04:15:41 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 10:15:41 +0100
Subject: [PATCH 4/9] ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5
In-Reply-To: <20120307084924.GK21255@game.jcrosoft.org>
References: <20120307084924.GK21255@game.jcrosoft.org>
Message-ID: <1331111746-21393-4-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9g25ek.dts    |    4 ++++
 arch/arm/boot/dts/at91sam9g45.dtsi     |    7 +++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts |    4 ++++
 arch/arm/boot/dts/at91sam9x5.dtsi      |    7 +++++++
 arch/arm/mach-at91/at91sam9g45.c       |    1 +
 arch/arm/mach-at91/at91sam9x5.c        |    1 +
 drivers/usb/Kconfig                    |    2 +-
 7 files changed, 25 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 93d5e36..ac0dc00 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -41,5 +41,9 @@
 					   &pioD 20 0
 					  >;
 		};
+
+		usb1: ehci at 00700000 {
+			status = "okay";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index db9a51a..4b54424 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -203,6 +203,13 @@
 			interrupts = <22 4>;
 			status = "disabled";
 		};
+
+		usb1: ehci at 00800000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00800000 0x100000>;
+			interrupts = <22 4>;
+			status = "disabled";
+		};
 	};
 
 	i2c-gpio at 0 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index ce4640e..4b1eb36 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -65,6 +65,10 @@
 			atmel,vbus-gpio = <&pioD 1 0
 					   &pioD 3 0>;
 		};
+
+		usb1: ehci at 00800000 {
+			status = "okay";
+		};
 	};
 
 	leds {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 7b43014..ac3c96c 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -194,6 +194,13 @@
 			interrupts = <22 4>;
 			status = "disabled";
 		};
+
+		usb1: ehci at 00700000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x00700000 0x100000>;
+			interrupts = <22 4>;
+			status = "disabled";
+		};
 	};
 
 	i2c-gpio at 0 {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index f58775e..df3bcea 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -233,6 +233,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
+	CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 40888ab..7333276 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -232,6 +232,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
 	CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
+	CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
 };
 
 /*
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 75823a1..afee052 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -65,7 +65,7 @@ config USB_ARCH_HAS_EHCI
 	default y if PPC_MPC512x
 	default y if ARCH_IXP4XX
 	default y if ARCH_W90X900
-	default y if ARCH_AT91SAM9G45
+	default y if ARCH_AT91SAM9G45 || ARCH_AT91SAM9X5
 	default y if ARCH_MXC
 	default y if ARCH_OMAP3
 	default y if ARCH_CNS3XXX
-- 
1.7.7



From plagnioj at jcrosoft.com  Wed Mar  7 04:15:43 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 10:15:43 +0100
Subject: [PATCH 6/9] ARM: at91: sam9g20 udc add dt support
In-Reply-To: <20120307084924.GK21255@game.jcrosoft.org>
References: <20120307084924.GK21255@game.jcrosoft.org>
Message-ID: <1331111746-21393-6-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9g20.dtsi |    7 +++++++
 arch/arm/boot/dts/usb_a9g20.dts    |    5 +++++
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 8c5c175..c030703 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -171,6 +171,13 @@
 				interrupts = <21 4>;
 				status = "disabled";
 			};
+
+			usb1: gadget at fffa4000 {
+				compatible = "atmel,at91rm9200-udc";
+				reg = <0xfffa4000 0x4000>;
+				interrupts = <10 4>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 55d0e54..e4a732f 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -30,6 +30,11 @@
 				phy-mode = "rmii";
 				status = "okay";
 			};
+
+			usb1: gadget at fffa4000 {
+				atmel,vbus-gpio = <&pioC 5 0>;
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {
-- 
1.7.7



From plagnioj at jcrosoft.com  Wed Mar  7 04:15:42 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 10:15:42 +0100
Subject: [PATCH 5/9] USB: at91: Device udc add dt support
In-Reply-To: <20120307084924.GK21255@game.jcrosoft.org>
References: <20120307084924.GK21255@game.jcrosoft.org>
Message-ID: <1331111746-21393-5-git-send-email-plagnioj@jcrosoft.com>

Allow to compile it if AT91 is enable.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-usb at vger.kernel.org
---
Hi Greg

	if it's ok with you I apply with the rest of the USB patch series via
	at91

Best Regards,
J.
 .../devicetree/bindings/usb/atmel-usb.txt          |   18 +++++++++
 drivers/usb/gadget/Kconfig                         |    2 +-
 drivers/usb/gadget/at91_udc.c                      |   40 +++++++++++++++++++-
 3 files changed, 57 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index 0143d7c..60bd215 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -29,3 +29,21 @@ usb1: ehci at 00800000 {
 	reg = <0x00800000 0x100000>;
 	interrupts = <22 4>;
 };
+
+AT91 USB device controller
+
+Required properties:
+ - compatible: Should be "atmel,at91rm9200-udc"
+ - reg: Address and length of the register set for the device
+ - interrupts: Should contain macb interrupt
+
+Optional properties:
+ - atmel,vbus-gpio: If present, specifies a gpio that needs to be
+   activated for the bus to be powered.
+
+usb1: gadget at fffa4000 {
+	compatible = "atmel,at91rm9200-udc";
+	reg = <0xfffa4000 0x4000>;
+	interrupts = <10 4>;
+	atmel,vbus-gpio = <&pioC 5 0>;
+};
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 85ae4b4..edf1144 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -137,7 +137,7 @@ choice
 
 config USB_AT91
 	tristate "Atmel AT91 USB Device Port"
-	depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91SAM9G45
+	depends on ARCH_AT91
 	help
 	   Many Atmel AT91 processors (such as the AT91RM2000) have a
 	   full speed USB Device Port with support for five configurable
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index f99b3dc..4063209 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -30,6 +30,8 @@
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/prefetch.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
 
 #include <asm/byteorder.h>
 #include <mach/hardware.h>
@@ -1707,7 +1709,27 @@ static void at91udc_shutdown(struct platform_device *dev)
 	spin_unlock_irqrestore(&udc->lock, flags);
 }
 
-static int __init at91udc_probe(struct platform_device *pdev)
+static void __devinit at91udc_of_init(struct at91_udc *udc,
+				     struct device_node *np)
+{
+	struct at91_udc_data *board = &udc->board;
+	u32 val;
+	enum of_gpio_flags flags;
+
+	if (of_property_read_u32(np, "atmel,vbus-polled", &val) == 0)
+		board->vbus_polled = 1;
+
+	board->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
+						  &flags);
+	board->vbus_active_low = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
+
+	board->pullup_pin = of_get_named_gpio_flags(np, "atmel,pullup-gpio", 0,
+						  &flags);
+
+	board->pullup_active_low = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
+}
+
+static int __devinit at91udc_probe(struct platform_device *pdev)
 {
 	struct device	*dev = &pdev->dev;
 	struct at91_udc	*udc;
@@ -1742,7 +1764,11 @@ static int __init at91udc_probe(struct platform_device *pdev)
 	/* init software state */
 	udc = &controller;
 	udc->gadget.dev.parent = dev;
-	udc->board = *(struct at91_udc_data *) dev->platform_data;
+	if (pdev->dev.of_node)
+		at91udc_of_init(udc, pdev->dev.of_node);
+	else
+		memcpy(&udc->board, dev->platform_data,
+		       sizeof(struct at91_udc_data));
 	udc->pdev = pdev;
 	udc->enabled = 0;
 	spin_lock_init(&udc->lock);
@@ -1971,6 +1997,15 @@ static int at91udc_resume(struct platform_device *pdev)
 #define	at91udc_resume	NULL
 #endif
 
+#if defined(CONFIG_OF)
+static const struct of_device_id at91_udc_dt_ids[] = {
+	{ .compatible = "atmel,at91rm9200-udc" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, at91_udc_dt_ids);
+#endif
+
 static struct platform_driver at91_udc_driver = {
 	.remove		= __exit_p(at91udc_remove),
 	.shutdown	= at91udc_shutdown,
@@ -1979,6 +2014,7 @@ static struct platform_driver at91_udc_driver = {
 	.driver		= {
 		.name	= (char *) driver_name,
 		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(at91_udc_dt_ids),
 	},
 };
 
-- 
1.7.7



From plagnioj at jcrosoft.com  Wed Mar  7 04:15:45 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 10:15:45 +0100
Subject: [PATCH 8/9] ARM: at91: sam9g45 add udc DT support
In-Reply-To: <20120307084924.GK21255@game.jcrosoft.org>
References: <20120307084924.GK21255@game.jcrosoft.org>
Message-ID: <1331111746-21393-8-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9g45.dtsi     |   66 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts |    5 ++
 arch/arm/mach-at91/at91sam9g45.c       |    2 +
 3 files changed, 73 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 4b54424..98407c7 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -179,6 +179,72 @@
 				interrupts = <25 4>;
 				status = "disabled";
 			};
+
+			usb2: gadget at fff78000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91sam9rl-udc";
+				reg = <0x00600000 0x80000
+				       0xfff78000 0x400>;
+				interrupts = <27 4>;
+				status = "disabled";
+
+				ep0 {
+					reg = <0>;
+					atmel,fifo-size = <64>;
+					atmel,nb-banks = <1>;
+					atmel,can-dma = <0>;
+					atmel,can-isoc = <0>;
+				};
+
+				ep1 {
+					reg = <1>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <1>;
+				};
+
+				ep2 {
+					reg = <2>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <1>;
+				};
+
+				ep3 {
+					reg = <3>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <0>;
+				};
+
+				ep4 {
+					reg = <4>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <0>;
+				};
+
+				ep5 {
+					reg = <5>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <1>;
+				};
+
+				ep6 {
+					reg = <6>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <1>;
+				};
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 4b1eb36..6dd2044 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -35,6 +35,11 @@
 				phy-mode = "rmii";
 				status = "okay";
 			};
+
+			usb2: gadget at fff78000 {
+				atmel,vbus-gpio = <&pioB 19 0>;
+				status = "okay";
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index df3bcea..da80f0c 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -234,6 +234,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
+	CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
+	CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
-- 
1.7.7



From plagnioj at jcrosoft.com  Wed Mar  7 04:15:46 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 10:15:46 +0100
Subject: [PATCH 9/9] ARM: at91: sam9x5 add udc DT support
In-Reply-To: <20120307084924.GK21255@game.jcrosoft.org>
References: <20120307084924.GK21255@game.jcrosoft.org>
Message-ID: <1331111746-21393-9-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9g25ek.dts |    5 +++
 arch/arm/boot/dts/at91sam9x5.dtsi   |   67 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-at91/at91sam9x5.c     |    2 +
 3 files changed, 74 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index ac0dc00..8e949d3 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -32,6 +32,11 @@
 				phy-mode = "rmii";
 				status = "okay";
 			};
+
+			usb2: gadget at f803c000 {
+				atmel,vbus-gpio = <&pioB 16 0>;
+				status = "okay";
+			};
 		};
 
 		usb0: ohci at 00600000 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index ac3c96c..0579698 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -171,6 +171,73 @@
 				interrupts = <27 4>;
 				status = "disabled";
 			};
+
+			usb2: gadget at f803c000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91sam9rl-udc";
+				reg = <0x00500000 0x80000
+				       0xf803c000 0x400>;
+				interrupts = <23 4>;
+				status = "disabled";
+
+				ep0 {
+					reg = <0>;
+					atmel,fifo-size = <64>;
+					atmel,nb-banks = <1>;
+					atmel,can-dma = <0>;
+					atmel,can-isoc = <0>;
+				};
+
+				ep1 {
+					reg = <1>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <1>;
+				};
+
+				ep2 {
+					reg = <2>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <2>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <1>;
+				};
+
+				ep3 {
+					reg = <3>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <0>;
+				};
+
+				ep4 {
+					reg = <4>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <0>;
+				};
+
+				ep5 {
+					reg = <5>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <1>;
+				};
+
+				ep6 {
+					reg = <6>;
+					atmel,fifo-size = <1024>;
+					atmel,nb-banks = <3>;
+					atmel,can-dma = <1>;
+					atmel,can-isoc = <1>;
+				};
+			};
+
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 7333276..66f2cb5 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -233,6 +233,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
+	CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
+	CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
 };
 
 /*
-- 
1.7.7



From plagnioj at jcrosoft.com  Wed Mar  7 04:15:44 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 10:15:44 +0100
Subject: [PATCH 7/9] usb: add Atmel USBA UDC DT support
In-Reply-To: <20120307084924.GK21255@game.jcrosoft.org>
References: <20120307084924.GK21255@game.jcrosoft.org>
Message-ID: <1331111746-21393-7-git-send-email-plagnioj@jcrosoft.com>

Allow to compile the driver all the time if AT91 enabled.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-usb at vger.kernel.org
---
Hi Greg

	if it's ok with you I apply with the rest of the USB patch series via
	at91

Best Regards,
J. .../devicetree/bindings/usb/atmel-usb.txt          |   86 ++++++++
 drivers/usb/gadget/Kconfig                         |    2 +-
 drivers/usb/gadget/atmel_usba_udc.c                |  209 +++++++++++++++-----
 drivers/usb/gadget/atmel_usba_udc.h                |    1 +
 4 files changed, 248 insertions(+), 50 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index 60bd215..b44f87e 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -47,3 +47,89 @@ usb1: gadget at fffa4000 {
 	interrupts = <10 4>;
 	atmel,vbus-gpio = <&pioC 5 0>;
 };
+
+Atmel High-Speed USB device controller
+
+Required properties:
+ - compatible: Should be "atmel,at91sam9rl-udc"
+ - reg: Address and length of the register set for the device
+ - interrupts: Should contain macb interrupt
+ - ep childnode: To specifiy the number of endpoints and their properties.
+
+Optional properties:
+ - atmel,vbus-gpio: If present, specifies a gpio that needs to be
+   activated for the bus to be powered.
+
+Required child node properties:
+ - name: Name of the endpoint.
+ - reg: Num of the endpoint.
+ - atmel,fifo-size: Size of the fifo.
+ - atmel,nb-banks: Number of banks.
+ - atmel,can-dma: Boolean to specify if the endpoint support DMA.
+ - atmel,can-isoc: Boolean to specify if the endpoint support ISOC.
+
+usb2: gadget at fff78000 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "atmel,at91sam9rl-udc";
+	reg = <0x00600000 0x80000
+	       0xfff78000 0x400>;
+	interrupts = <27 4>;
+	atmel,vbus-gpio = <&pioB 19 0>;
+
+	ep0 {
+		reg = <0>;
+		atmel,fifo-size = <64>;
+		atmel,nb-banks = <1>;
+		atmel,can-dma = <0>;
+		atmel,can-isoc = <0>;
+	};
+
+	ep1 {
+		reg = <1>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <2>;
+		atmel,can-dma = <1>;
+		atmel,can-isoc = <1>;
+	};
+
+	ep2 {
+		reg = <2>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <2>;
+		atmel,can-dma = <1>;
+		atmel,can-isoc = <1>;
+	};
+
+	ep3 {
+		reg = <3>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma = <1>;
+		atmel,can-isoc = <0>;
+	};
+
+	ep4 {
+		reg = <4>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma = <1>;
+		atmel,can-isoc = <0>;
+	};
+
+	ep5 {
+		reg = <5>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma = <1>;
+		atmel,can-isoc = <1>;
+	};
+
+	ep6 {
+		reg = <6>;
+		atmel,fifo-size = <1024>;
+		atmel,nb-banks = <3>;
+		atmel,can-dma = <1>;
+		atmel,can-isoc = <1>;
+	};
+};
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index edf1144..1dbba6c 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -150,7 +150,7 @@ config USB_AT91
 config USB_ATMEL_USBA
 	tristate "Atmel USBA"
 	select USB_GADGET_DUALSPEED
-	depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
+	depends on AVR32 || ARCH_AT91
 	help
 	  USBA is the integrated high-speed USB Device controller on
 	  the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index ce9dffb..234eabb 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -21,6 +21,8 @@
 #include <linux/usb/gadget.h>
 #include <linux/usb/atmel_usba_udc.h>
 #include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
 
 #include <asm/gpio.h>
 #include <mach/board.h>
@@ -1885,9 +1887,143 @@ static int atmel_usba_stop(struct usb_gadget_driver *driver)
 	return 0;
 }
 
-static int __init usba_udc_probe(struct platform_device *pdev)
+#ifdef CONFIG_OF
+static struct usba_ep * __devinit atmel_udc_of_init(struct platform_device *pdev,
+						    struct usba_udc *udc)
+{
+	u32 val;
+	const char *name;
+	enum of_gpio_flags flags;
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *pp;
+	int i, ret;
+	struct usba_ep *eps, *ep;
+
+	udc->num_ep = 0;
+
+	udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
+						&flags);
+	udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
+
+	pp = NULL;
+	while ((pp = of_get_next_child(np, pp)))
+		udc->num_ep++;
+
+	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
+			   GFP_KERNEL);
+	if (!eps)
+		return ERR_PTR(-ENOMEM);
+
+	udc->gadget.ep0 = &eps[0].ep;
+
+	INIT_LIST_HEAD(&eps[0].ep.ep_list);
+
+	pp = NULL;
+	i = 0;
+	while ((pp = of_get_next_child(np, pp))) {
+		ep = &eps[i];
+
+		ret = of_property_read_u32(pp, "reg", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: reg error(%d)\n", ret);
+			goto err;
+		}
+		ep->index = val;
+
+		ret = of_property_read_u32(pp, "atmel,fifo-size", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: fifo-size error(%d)\n", ret);
+			goto err;
+		}
+		ep->fifo_size = val;
+
+		ret = of_property_read_u32(pp, "atmel,nb-banks", &val);
+		if (ret) {
+			dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret);
+			goto err;
+		}
+		ep->nr_banks = val;
+
+		ep->can_dma = of_property_read_bool(pp, "atmel,can-dma");
+		ep->can_isoc = of_property_read_bool(pp, "atmel,can-isoc");
+
+		ret = of_property_read_string(pp, "name", &name);
+		ep->ep.name = name;
+
+		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
+		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
+		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
+		ep->ep.ops = &usba_ep_ops;
+		ep->ep.maxpacket = ep->fifo_size;
+		ep->udc = udc;
+		INIT_LIST_HEAD(&ep->queue);
+
+		if (i)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+
+		i++;
+	}
+
+	return eps;
+err:
+	return ERR_PTR(ret);
+}
+#else
+static struct usba_ep * __devinit atmel_udc_of_init(struct platform_device *pdev,
+						    struct usba_udc *udc)
+{
+	return ERR_PTR(-ENOSYS);
+}
+#endif
+
+static struct usba_ep * __devinit usba_udc_pdata(struct platform_device *pdev,
+						 struct usba_udc *udc)
 {
 	struct usba_platform_data *pdata = pdev->dev.platform_data;
+	struct usba_ep *eps;
+	int i;
+
+	if (!pdata)
+		return ERR_PTR(-ENXIO);
+
+	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * pdata->num_ep,
+			   GFP_KERNEL);
+	if (!eps)
+		return ERR_PTR(-ENOMEM);
+
+	udc->gadget.ep0 = &eps[0].ep;
+
+	udc->vbus_pin = pdata->vbus_pin;
+	udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
+	udc->num_ep = pdata->num_ep;
+
+	INIT_LIST_HEAD(&eps[0].ep.ep_list);
+
+	for (i = 0; i < pdata->num_ep; i++) {
+		struct usba_ep *ep = &eps[i];
+
+		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
+		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
+		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
+		ep->ep.ops = &usba_ep_ops;
+		ep->ep.name = pdata->ep[i].name;
+		ep->fifo_size = ep->ep.maxpacket = pdata->ep[i].fifo_size;
+		ep->udc = udc;
+		INIT_LIST_HEAD(&ep->queue);
+		ep->nr_banks = pdata->ep[i].nr_banks;
+		ep->index = pdata->ep[i].index;
+		ep->can_dma = pdata->ep[i].can_dma;
+		ep->can_isoc = pdata->ep[i].can_isoc;
+
+		if (i)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+	}
+
+	return eps;
+}
+
+static int __init usba_udc_probe(struct platform_device *pdev)
+{
 	struct resource *regs, *fifo;
 	struct clk *pclk, *hclk;
 	struct usba_udc *udc = &the_udc;
@@ -1895,7 +2031,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
 	fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
-	if (!regs || !fifo || !pdata)
+	if (!regs || !fifo)
 		return -ENXIO;
 
 	irq = platform_get_irq(pdev, 0);
@@ -1945,46 +2081,14 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 	usba_writel(udc, CTRL, USBA_DISABLE_MASK);
 	clk_disable(pclk);
 
-	usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
-			  GFP_KERNEL);
-	if (!usba_ep)
-		goto err_alloc_ep;
-
-	the_udc.gadget.ep0 = &usba_ep[0].ep;
-
-	INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
-	usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
-	usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
-	usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
-	usba_ep[0].ep.ops = &usba_ep_ops;
-	usba_ep[0].ep.name = pdata->ep[0].name;
-	usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
-	usba_ep[0].udc = &the_udc;
-	INIT_LIST_HEAD(&usba_ep[0].queue);
-	usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
-	usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
-	usba_ep[0].index = pdata->ep[0].index;
-	usba_ep[0].can_dma = pdata->ep[0].can_dma;
-	usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
-
-	for (i = 1; i < pdata->num_ep; i++) {
-		struct usba_ep *ep = &usba_ep[i];
-
-		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
-		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
-		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
-		ep->ep.ops = &usba_ep_ops;
-		ep->ep.name = pdata->ep[i].name;
-		ep->ep.maxpacket = pdata->ep[i].fifo_size;
-		ep->udc = &the_udc;
-		INIT_LIST_HEAD(&ep->queue);
-		ep->fifo_size = pdata->ep[i].fifo_size;
-		ep->nr_banks = pdata->ep[i].nr_banks;
-		ep->index = pdata->ep[i].index;
-		ep->can_dma = pdata->ep[i].can_dma;
-		ep->can_isoc = pdata->ep[i].can_isoc;
+	if (pdev->dev.of_node)
+		usba_ep = atmel_udc_of_init(pdev, udc);
+	else
+		usba_ep = usba_udc_pdata(pdev, udc);
 
-		list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+	if (IS_ERR(usba_ep)) {
+		ret = PTR_ERR(usba_ep);
+		goto err_alloc_ep;
 	}
 
 	ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
@@ -2001,10 +2105,8 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 		goto err_device_add;
 	}
 
-	if (gpio_is_valid(pdata->vbus_pin)) {
-		if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
-			udc->vbus_pin = pdata->vbus_pin;
-			udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
+	if (gpio_is_valid(udc->vbus_pin)) {
+		if (!gpio_request(udc->vbus_pin, "atmel_usba_udc")) {
 
 			ret = request_irq(gpio_to_irq(udc->vbus_pin),
 					usba_vbus_irq, 0,
@@ -2029,13 +2131,13 @@ static int __init usba_udc_probe(struct platform_device *pdev)
 		goto err_add_udc;
 
 	usba_init_debugfs(udc);
-	for (i = 1; i < pdata->num_ep; i++)
+	for (i = 1; i < udc->num_ep; i++)
 		usba_ep_init_debugfs(udc, &usba_ep[i]);
 
 	return 0;
 
 err_add_udc:
-	if (gpio_is_valid(pdata->vbus_pin)) {
+	if (gpio_is_valid(udc->vbus_pin)) {
 		free_irq(gpio_to_irq(udc->vbus_pin), udc);
 		gpio_free(udc->vbus_pin);
 	}
@@ -2064,13 +2166,12 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
 {
 	struct usba_udc *udc;
 	int i;
-	struct usba_platform_data *pdata = pdev->dev.platform_data;
 
 	udc = platform_get_drvdata(pdev);
 
 	usb_del_gadget_udc(&udc->gadget);
 
-	for (i = 1; i < pdata->num_ep; i++)
+	for (i = 1; i < udc->num_ep; i++)
 		usba_ep_cleanup_debugfs(&usba_ep[i]);
 	usba_cleanup_debugfs(udc);
 
@@ -2091,11 +2192,21 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id atmel_udc_dt_ids[] = {
+	{ .compatible = "atmel,at91sam9rl-udc" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
+#endif
+
 static struct platform_driver udc_driver = {
 	.remove		= __exit_p(usba_udc_remove),
 	.driver		= {
 		.name		= "atmel_usba_udc",
 		.owner		= THIS_MODULE,
+		.of_match_table	= of_match_ptr(atmel_udc_dt_ids),
 	},
 };
 
diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
index 88a2e07..2c068e7 100644
--- a/drivers/usb/gadget/atmel_usba_udc.h
+++ b/drivers/usb/gadget/atmel_usba_udc.h
@@ -324,6 +324,7 @@ struct usba_udc {
 	int irq;
 	int vbus_pin;
 	int vbus_pin_inverted;
+	int num_ep;
 	struct clk *pclk;
 	struct clk *hclk;
 
-- 
1.7.7



From linux at arm.linux.org.uk  Wed Mar  7 04:34:46 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 09:34:46 +0000
Subject: [PATCH 1/9 v2] ARM: at91: usb ohci add dt support
In-Reply-To: <1331111746-21393-1-git-send-email-plagnioj@jcrosoft.com>
References: <20120307084924.GK21255@game.jcrosoft.org>
 <1331111746-21393-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120307093446.GN17370@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 10:15:38AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> +static u64 at91_ohci_dma_mask = DMA_BIT_MASK(32);
> +
> +static int __devinit ohci_at91_of_init(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	int i, ret, gpio;
> +	enum of_gpio_flags flags;
> +	struct at91_usbh_data	*pdata;
> +	u32 ports;
> +
> +	if (!np)
> +		return 0;
> +
> +	/* Right now device-tree probed devices don't get dma_mask set.
> +	 * Since shared usb code relies on it, set it here for now.
> +	 * Once we have dma capability bindings this can go away.
> +	 */
> +	if (!pdev->dev.dma_mask)
> +		pdev->dev.dma_mask = &at91_ohci_dma_mask;

That sounds like a rather big omission from DT - what's happening to
address this (before we end up with lots of drivers with this).  Pretty
much any device which does DMA needs both this and the coherent DMA mask
set properly.

We really don't want this kind of workaround scattered in every driver
which has been converted to DT.


From linux at arm.linux.org.uk  Wed Mar  7 04:41:29 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 09:41:29 +0000
Subject: [PATCH 0/4] perf IRQ fixes
In-Reply-To: <1330012696-13472-1-git-send-email-will.deacon@arm.com>
References: <1330012696-13472-1-git-send-email-will.deacon@arm.com>
Message-ID: <20120307094129.GO17370@n2100.arm.linux.org.uk>

On Thu, Feb 23, 2012 at 03:58:12PM +0000, Will Deacon wrote:
> Hello,
> 
> This series is a set of fixes to the IRQ handling for perf-events on
> ARM. Thanks to Ming Lei for identifying a couple of the issues addressed
> here.
> 
> I tested the xscale2 changes on my Gumstix Verdex (PXA270 although the
> board isn't actually supported in mainline), the v6 changes on a PB1176
> and the v7 changes on a Cortex-A9 vexpress.
> 
> I think all of these are candidates for -stable, although it may be too
> late for the final cut of 3.3.

So do you want these (and the 5th patch) to have a stable tag on them?


From will.deacon at arm.com  Wed Mar  7 04:44:16 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 7 Mar 2012 09:44:16 +0000
Subject: [PATCH 0/4] perf IRQ fixes
In-Reply-To: <20120307094129.GO17370@n2100.arm.linux.org.uk>
References: <1330012696-13472-1-git-send-email-will.deacon@arm.com>
 <20120307094129.GO17370@n2100.arm.linux.org.uk>
Message-ID: <20120307094416.GA20673@mudshark.cambridge.arm.com>

Hi Russell,

On Wed, Mar 07, 2012 at 09:41:29AM +0000, Russell King - ARM Linux wrote:
> On Thu, Feb 23, 2012 at 03:58:12PM +0000, Will Deacon wrote:
> > Hello,
> > 
> > This series is a set of fixes to the IRQ handling for perf-events on
> > ARM. Thanks to Ming Lei for identifying a couple of the issues addressed
> > here.
> > 
> > I tested the xscale2 changes on my Gumstix Verdex (PXA270 although the
> > board isn't actually supported in mainline), the v6 changes on a PB1176
> > and the v7 changes on a Cortex-A9 vexpress.
> > 
> > I think all of these are candidates for -stable, although it may be too
> > late for the final cut of 3.3.
> 
> So do you want these (and the 5th patch) to have a stable tag on them?

I posted them to the patch system yesterday and included a CC stable tag
on the patches then. The only patch which doesn't need that is the hotplug
notifier.

Cheers,

Will


From hvaibhav at ti.com  Wed Mar  7 04:48:06 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 7 Mar 2012 09:48:06 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <20120305225530.GJ12083@atomide.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <20120305225530.GJ12083@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83180A006@DBDE01.ent.ti.com>

On Tue, Mar 06, 2012 at 04:25:30, Tony Lindgren wrote:
> Hi,
> 
> * Vaibhav Hiremath <hvaibhav at ti.com> [120119 06:01]:
> > OMAP device has 32k-sync timer which is currently used as a
> > clocksource in the kernel (omap2plus_defconfig).
> > The current implementation uses compile time selection between
> > gp-timer and 32k-sync timer, which breaks multi-omap build for
> > the devices like AM33xx, where 32k-sync timer is not available.
> > 
> > So use hwmod database lookup mechanism, through which at run-time
> > we can identify availability of 32k-sync timer on the device,
> > else fall back to gp-timer.
> ...
> 
> > --- a/arch/arm/plat-omap/counter_32k.c
> > +++ b/arch/arm/plat-omap/counter_32k.c
> > @@ -69,52 +69,55 @@ void read_persistent_clock(struct timespec *ts)
> >  
> >  int __init omap_init_clocksource_32k(void)
> >  {
> > -	static char err[] __initdata = KERN_ERR
> > -			"%s: can't register clocksource!\n";
> > -
> > -	if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
> > -		u32 pbase;
> > -		unsigned long size = SZ_4K;
> > -		void __iomem *base;
> > -		struct clk *sync_32k_ick;
> > -
> > -		if (cpu_is_omap16xx()) {
> > -			pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > -			size = SZ_1K;
> > -		} else if (cpu_is_omap2420())
> > -			pbase = OMAP2420_32KSYNCT_BASE + 0x10;
> > -		else if (cpu_is_omap2430())
> > -			pbase = OMAP2430_32KSYNCT_BASE + 0x10;
> > -		else if (cpu_is_omap34xx())
> > -			pbase = OMAP3430_32KSYNCT_BASE + 0x10;
> > -		else if (cpu_is_omap44xx())
> > -			pbase = OMAP4430_32KSYNCT_BASE + 0x10;
> > -		else
> > +	u32 pbase;
> > +	unsigned long size = SZ_4K;
> > +	void __iomem *base;
> > +	struct clk *sync_32k_ick;
> > +
> > +	if (cpu_is_omap16xx()) {
> > +		pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > +		size = SZ_1K;
> > +	} else if (cpu_class_is_omap2()) {
> > +		struct omap_hwmod *oh;
> > +		const char *oh_name = "counter_32k";
> > +
> > +		oh = omap_hwmod_lookup(oh_name);
> > +		if (!oh || oh->slaves_cnt == 0) {
> > +			pr_err("Could not lookup %s hwmod\n", oh_name);
> >  			return -ENODEV;
> > +		}
> > +		pbase = oh->slaves[0]->addr->pa_start + 0x10;
> > +	} else {
> > +		return -ENODEV;
> > +	}
> 
> How about have separate omap1 and omap2+ init functions that
> call a common function and passes the pbase as a parameter?
> 
> That way we can get rid of the cpu_is_omapxxxx tests here.
> 

Ok, let me clean this code accordingly  and submit the next version.

Thanks,
Vaibhav

> Regards,
> 
> Tony 
> 



From will.deacon at arm.com  Wed Mar  7 04:48:50 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 7 Mar 2012 09:48:50 +0000
Subject: oprofile and ARM A9 hardware counter
In-Reply-To: <CACVXFVNExXcU473=m5QLZXAhpNsC3WZHrFa-=HzGdjMEy3seDg@mail.gmail.com>
References: <CAMsRxfKPm0dEaKDeSZQ=6jkpo4MeS=0XF6TsCj+BV54WbW_LtA@mail.gmail.com>
 <CACVXFVMgk7ykSX3GjzCNvUU0zMzNvGGuZMBpxBf7NRVk9EM7ig@mail.gmail.com>
 <CAMsRxfJWjwznJYujSvr0DfhNxtnJDVdfjXXpx34HUDBRtMvjqw@mail.gmail.com>
 <20120127121311.GB2347@mudshark.cambridge.arm.com>
 <yw1x1uqlnw1o.fsf@unicorn.mansr.com>
 <20120127132826.GD2347@mudshark.cambridge.arm.com>
 <CACVXFVPHpmPX9OdeYzzWjQ-qqs=9oYbL_og-_xJA2ypYNu0nRA@mail.gmail.com>
 <CAMsRxfJOAh1V7sMWxqCXADDB_eSAuxop1iYAGqXvLC_74Pfz1A@mail.gmail.com>
 <20120127155454.GH2347@mudshark.cambridge.arm.com>
 <CACVXFVNExXcU473=m5QLZXAhpNsC3WZHrFa-=HzGdjMEy3seDg@mail.gmail.com>
Message-ID: <20120307094850.GB20673@mudshark.cambridge.arm.com>

On Wed, Mar 07, 2012 at 02:49:46AM +0000, Ming Lei wrote:
> Hi Will,

Hello,

> On Fri, Jan 27, 2012 at 11:54 PM, Will Deacon <will.deacon at arm.com> wrote:
> > Ok. Note that on ARM the PMU generates a standard IRQ (i.e. not an NMI) so
> > you may miss samples if they occur during critical kernel sections (and if
> > you look at a profile, spin_unlock_irqrestore will be quite high).
> 
> Also looks no any irq handler functions can be observed at a profile even
> though they may be run at a very high frequency.
> 
> So could we configure ARM PMU interrupt as FIQ to address the above issues?

I thought about that in the past but the problem is finding hardware which
allows this. It probably means that you need a second GIC which can route
interrupts onto the FIQ line into the CPU. Given that FIQ is usually claimed
for secure interrupts, there could also still be latency issues here.

A better (read: highly invasive) way to fix this is using interrupt
priorities at the distributor. You then have to hack the interrupt disabling
code so that it disables interrupts below a certain priority if they occur
during an IRQ-off section. The re-enabling code would then have to undo
those decisions and allow the interrupts to be serviced. Pretty nasty stuff.

Will


From hvaibhav at ti.com  Wed Mar  7 04:49:22 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 7 Mar 2012 09:49:22 +0000
Subject: [PATCH 2/3] ARM: OMAP2/3: Add idle_st bits for ST_32KSYNC timer
 to prcm-common header
In-Reply-To: <20120305225640.GK12083@atomide.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-3-git-send-email-hvaibhav@ti.com>
 <20120305225640.GK12083@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83180A024@DBDE01.ent.ti.com>

On Tue, Mar 06, 2012 at 04:26:40, Tony Lindgren wrote:
> * Vaibhav Hiremath <hvaibhav at ti.com> [120119 06:01]:
> > Add missing idle_st bit for 32k-sync timer into the prcm-common
> > header file, required for hwmod data.
> 
> These should be queued by Paul when the related hwmod changes
> are done.
> 

Paul,

Can you queue this up into your next-branch?

Thanks,
Vaibhav


> Regards,
> 
> Tony
>  
> > Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> > Cc: Felipe Balbi <balbi at ti.com>
> > Cc: Benoit Cousson <b-cousson at ti.com>
> > Cc: Tony Lindgren <tony at atomide.com>
> > Cc: Paul Walmsley <paul at pwsan.com>
> > ---
> >  arch/arm/mach-omap2/prcm-common.h |    4 ++++
> >  1 files changed, 4 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
> > index 5aa5435..29955d5 100644
> > --- a/arch/arm/mach-omap2/prcm-common.h
> > +++ b/arch/arm/mach-omap2/prcm-common.h
> > @@ -177,6 +177,8 @@
> >  /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
> >  #define OMAP24XX_ST_GPIOS_SHIFT				2
> >  #define OMAP24XX_ST_GPIOS_MASK				(1 << 2)
> > +#define OMAP24XX_ST_32KSYNC_SHIFT			1
> > +#define OMAP24XX_ST_32KSYNC_MASK			(1 << 1)
> >  #define OMAP24XX_ST_GPT1_SHIFT				0
> >  #define OMAP24XX_ST_GPT1_MASK				(1 << 0)
> >  
> > @@ -307,6 +309,8 @@
> >  #define OMAP3430_ST_SR1_MASK				(1 << 6)
> >  #define OMAP3430_ST_GPIO1_SHIFT				3
> >  #define OMAP3430_ST_GPIO1_MASK				(1 << 3)
> > +#define OMAP3430_ST_32KSYNC_SHIFT			2
> > +#define OMAP3430_ST_32KSYNC_MASK			(1 << 2)
> >  #define OMAP3430_ST_GPT12_SHIFT				1
> >  #define OMAP3430_ST_GPT12_MASK				(1 << 1)
> >  #define OMAP3430_ST_GPT1_SHIFT				0
> > -- 
> > 1.7.0.4
> > 
> 



From hvaibhav at ti.com  Wed Mar  7 04:50:34 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 7 Mar 2012 09:50:34 +0000
Subject: [PATCH 0/3] ARM: OMAP1/2+: 32k-timer: Add hwmod lookup for
 32k-timer
In-Reply-To: <20120305225751.GL12083@atomide.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <79CD15C6BA57404B839C016229A409A8317AF2D2@DBDE01.ent.ti.com>
 <20120305225751.GL12083@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83180A03F@DBDE01.ent.ti.com>

On Tue, Mar 06, 2012 at 04:27:52, Tony Lindgren wrote:
> * Hiremath, Vaibhav <hvaibhav at ti.com> [120123 00:16]:
> > On Thu, Jan 19, 2012 at 19:58:21, Hiremath, Vaibhav wrote:
> > > This patch series cleans up the existing 32k-sync timer implementation
> > > without any major code change and adds hwmod lookup for omap2+ devices,
> > > if lookup fails then fall back to gp-timer.
> ...
>  
> > Tony,
> > 
> > If there are no review comments, can this be merged?
> 
> Made a minor comment on the first patch, it would be nice to get
> that clean-up merged. The other two depend on some some hwmod
> data shrinkage by Paul..
> 

Working on it, will be submitting next version soon.

Thanks,
Vaibhav

> Regards,
> 
> Tony
> 



From srinidhi.kasagar at stericsson.com  Wed Mar  7 04:32:42 2012
From: srinidhi.kasagar at stericsson.com (Srinidhi Kasagar)
Date: Wed, 7 Mar 2012 15:02:42 +0530
Subject: [PATCH 1/2] mach-ux500: cache operations are atomic on PL310
In-Reply-To: <20120117133428.GB11581@mudshark.cambridge.arm.com>
References: <1326346663-6112-1-git-send-email-srinidhi.kasagar@stericsson.com>
 <20120113181422.GB24373@mudshark.cambridge.arm.com>
 <20120116110528.GA24824@bnru02>
 <20120116145008.GH9068@mudshark.cambridge.arm.com>
 <20120117062224.GA26832@bnru02>
 <20120117103023.GB9230@mudshark.cambridge.arm.com>
 <20120117112741.GA14426@bnru02>
 <20120117133428.GB11581@mudshark.cambridge.arm.com>
Message-ID: <20120307093240.GA21265@bnru02>

On Tue, Jan 17, 2012 at 14:34:28 +0100, Will Deacon wrote:
> On Tue, Jan 17, 2012 at 11:27:43AM +0000, Srinidhi KASAGAR wrote:
> > On Tue, Jan 17, 2012 at 11:30:23 +0100, Will Deacon wrote:
> > > On Tue, Jan 17, 2012 at 06:22:26AM +0000, Srinidhi KASAGAR wrote:
> > > > 
> > > > Yes, we boot with L2 enabled.
> > > 
> > > Interesting. I'm surprised you don't have problems with stale data on the
> > > D-side after the decompressor. Maybe you're lucky with the mappings being no
> > > write allocate.
> > 
> > Actually the pre bootloader makes sure that L2 is clean before relinquishing
> > the control to kernel decompressor.
> 
> I was thinking more of the decompressor populating the L2 and not flushing
> it.

Perhaps, we are lucky because we lock down l2 in bootloader?

srinidhi


From hvaibhav at ti.com  Wed Mar  7 04:56:02 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 7 Mar 2012 09:56:02 +0000
Subject: [PATCH v2 2/2] ARM: OMAP: sram: Add am33xx SRAM support (minimal)
In-Reply-To: <20120305231413.GP12083@atomide.com>
References: <1329113715-7634-1-git-send-email-afzal@ti.com>
 <87fweeyfp6.fsf@macbook.be.48ers.dk>
 <B5906170F1614E41A8A28DE3B8D121433179FC35@DBDE01.ent.ti.com>
 <20120305231413.GP12083@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83180A06D@DBDE01.ent.ti.com>

On Tue, Mar 06, 2012 at 04:44:13, Tony Lindgren wrote:
> * Bedia, Vaibhav <vaibhav.bedia at ti.com> [120213 07:36]:
> > On Mon, Feb 13, 2012 at 19:54:05, Peter Korsgaard wrote:
> > > >>>>> "Afzal" == Afzal Mohammed <afzal at ti.com> writes:
> > > 
> > >  Afzal> From: Vaibhav Bedia <vaibhav.bedia at ti.com>
> > >  Afzal> Update SRAM start & size for am33xx SoC's.
> > > 
> > 
> > This is a really awkward quoting style :|
> > 
> > > 
> > > I don't particular know the omap sram stuff, but doesn't the 33xx have
> > > 2x 64K blocks of SRAM?
> > > 
> > 
> > Yes, but since the lower 64KB will not be available on non-GP device and
> > only A8 can access it, for now we make use of the higher 64KB which is referred
> > to as the OCMC RAM in the TRM. This will also enable SRAM usage by other drivers
> > like PRU and McASP.
> > 
> > >  
> > >  Afzal> +static inline int am33xx_sram_init(void)
> > >  Afzal> +{
> > >  Afzal> +	return 0;
> > > 
> > > 
> > > I know you mentioned it in the commit message, but it might be good with
> > > a comment here as well that this dummy function is needed to not get the 34xx
> > > init function called for 33xx, so it doesn't get removed when somebody
> > > decides to cleanup.
> > 
> > You are right in saying that the dummy function is needed to avoid 34xx SRAM init.
> > We'll have some PM related code coming in soon and hopefully the SRAM code won't change
> > Without us noticing ;)
> 
> OK, applying into fixes-non-critical-part2. Our sram.c should get turned
> into a device driver, there's been already similar sram driver posted
> to LAKML. So that should allow us to remove the cpu_is_xxxx checks.
> 

I think I missed this, let me check the post.

Thanks,
Vaibhav

> Regards,
> 
> Tony
> 



From rnayak at ti.com  Wed Mar  7 04:58:06 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Wed, 07 Mar 2012 15:28:06 +0530
Subject: [PATCH v2 0/6] mmc: omap_hsmmc: Clean up use/abuse of pdev->id
In-Reply-To: <4F54714E.6080805@ti.com>
References: <1329996409-26861-1-git-send-email-rnayak@ti.com>
 <4F476228.7060607@ti.com> <4F54714E.6080805@ti.com>
Message-ID: <4F57312E.4080104@ti.com>

On Monday 05 March 2012 01:24 PM, Rajendra Nayak wrote:
> On Friday 24 February 2012 03:40 PM, Rajendra Nayak wrote:
>> Chris,
>>
>> On Thursday 23 February 2012 04:56 PM, Rajendra Nayak wrote:
>>> Re-sending as these patches did not make it to the lists due to
>>> issues with my 'git send-email'
>>>
>>> This series mainly cleans up all instances of hardcoding's in
>>> the driver based on pdev->id. This is cleanup leading to the
>>> DT adaptation of omap_hsmmc driver.
>>>
>>> v2 mainly has some minor changes to get rid of a debug print
>>> which was still using host->id and getting rid of 'id' field
>>> entirely from omap_hsmmc_host struct.
>>>
>>> The series is tested on OMAP4SDP, OMAP4panda, OMAP3beagle and
>>> OMAP2430SDP
>>> boards.
>>
>> This series is reviewed/tested and acked by Balaji and Venkat.
>> Care to pull this in for 3.4?
>>
>> I have one other cleanup patch on top of this series to make all
>> remaining pr_* prints in the driver to dev_* [1].
>> It would be great if you could pick that up as well.
>>
>> These patches are cleanups leading to the DT conversion of omap_hsmmc
>> driver.
>
> Chris, Ping. I am basing my DT support patches on top of these cleanups.
> Would be great if you can have a look and pull them in.

Chris, just realized the last two requests from me to get this merged
weren't addressed to you directly, but instead you were copied.
Resending with you in 'To', hope this lands in your inbox :)

regards,
Rajendra

>
>>
>> regards,
>> Rajendra
>>
>> [1] http://marc.info/?l=linux-mmc&m=132999677405098&w=3
>>
>>>
>>> regards,
>>> Rajendra
>>>
>>> Balaji T K (3):
>>> mmc: omap_hsmmc: use platform_get_resource_byname for tx/rx DMA
>>> channels
>>> mmc: omap_hsmmc: remove unused .set_sleep function
>>> mmc: omap_hsmmc: Use OMAP_HSMMC_SUPPORTS_DUAL_VOLT flag to remove
>>> host->id based hardcoding
>>>
>>> Rajendra Nayak (3):
>>> mmc: omap_hsmmc: Get rid of omap_hsmmc_1_set_power function
>>> mmc: omap_hsmmc: Get rid of omap_hsmmc_4_set_power function
>>> mmc: omap_hsmmc: Don't expect MMC1 to always have vmmc supply
>>>
>>> arch/arm/plat-omap/include/plat/mmc.h | 2 -
>>> drivers/mmc/host/omap_hsmmc.c | 175 +++------------------------------
>>> 2 files changed, 16 insertions(+), 161 deletions(-)
>>>
>>
>



From FlorianSchandinat at gmx.de  Wed Mar  7 05:09:18 2012
From: FlorianSchandinat at gmx.de (Florian Tobias Schandinat)
Date: Wed, 07 Mar 2012 10:09:18 +0000
Subject: [PATCH] pxafb: do console locking before calling fb_blank()
In-Reply-To: <1330264322-5938-1-git-send-email-anarsoul@gmail.com>
References: <1330264322-5938-1-git-send-email-anarsoul@gmail.com>
Message-ID: <4F5733CE.2060900@gmx.de>

On 02/26/2012 01:52 PM, Vasily Khoruzhick wrote:
> Otherwise we hit WARN_CONSOLE_UNLOCKED in do_unblank_screen
> 
> Signed-off-by: Vasily Khoruzhick <anarsoul at gmail.com>

Applied.


Thanks,

Florian Tobias Schandinat

> ---
>  drivers/video/pxafb.c |    6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
> index 1d1e4f1..c176561 100644
> --- a/drivers/video/pxafb.c
> +++ b/drivers/video/pxafb.c
> @@ -54,6 +54,7 @@
>  #include <linux/mutex.h>
>  #include <linux/kthread.h>
>  #include <linux/freezer.h>
> +#include <linux/console.h>
>  
>  #include <mach/hardware.h>
>  #include <asm/io.h>
> @@ -730,9 +731,12 @@ static int overlayfb_open(struct fb_info *info, int user)
>  	if (user == 0)
>  		return -ENODEV;
>  
> -	if (ofb->usage++ == 0)
> +	if (ofb->usage++ == 0) {
>  		/* unblank the base framebuffer */
> +		console_lock();
>  		fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
> +		console_unlock();
> +	}
>  
>  	return 0;
>  }



From FlorianSchandinat at gmx.de  Wed Mar  7 05:13:41 2012
From: FlorianSchandinat at gmx.de (Florian Tobias Schandinat)
Date: Wed, 07 Mar 2012 10:13:41 +0000
Subject: [PATCH] MAINTAINERS: add entry for exynos mipi display drivers
In-Reply-To: <4F557A2A.2080108@samsung.com>
References: <4F557A2A.2080108@samsung.com>
Message-ID: <4F5734D5.2030504@gmx.de>

On 03/06/2012 02:44 AM, Donghwa Lee wrote:
> Hi, I'd like to add Inki Dae, Donghwa Lee and Kyungmin Park as 
> maintainers who developers for exynos mipi display drivers for
> video/driver/exynos/exynos_mipi* and include/video/exynos_mipi*.
> 
> Signed-off-by: Donghwa Lee <dh09.lee at samsung.com>
> Signed-off-by: Inki Dae <inki.dae at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>

Applied after moving it to keep alphabetical order in MAINTAINERS and
amending the commit message like Andrew did with v1 of this patch
(deleting "Hi, I'd like to").


Thanks,

Florian Tobias Schandinat

> ---
>  MAINTAINERS |    9 +++++++++
>  1 files changed, 9 insertions(+), 0 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b087b3bc..eb5fbcb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2351,6 +2351,15 @@ S:	Supported
>  F:	drivers/gpu/drm/exynos
>  F:	include/drm/exynos*
>  
> +EXYNOS MIPI DISPLAY DRIVERS
> +M:	Inki Dae <inki.dae at samsung.com>
> +M:	Donghwa Lee <dh09.lee at samsung.com>
> +M:	Kyungmin Park <kyungmin.park at samsung.com>
> +L:	linux-fbdev at vger.kernel.org
> +S:	Maintained
> +F:	drivers/video/exynos/exynos_mipi*
> +F:	include/video/exynos_mipi*
> +
>  DSCC4 DRIVER
>  M:	Francois Romieu <romieu at fr.zoreil.com>
>  L:	netdev at vger.kernel.org



From viresh.kumar at st.com  Wed Mar  7 05:27:41 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:41 +0530
Subject: [PATCH 00/15] watchdog/mpcore: updates & fixes
Message-ID: <cover.1331115751.git.viresh.kumar@st.com>

Hello,

This patchset contains fixes and updates for ARM mpcore watchdog driver.
Changes are mentioned in following patch list:

Viresh Kumar (15):
  watchdog/mpcore_wdt: Fix multiline comments
  watchdog/mpcore_wdt: Add blank line after variable definitions in
    routines
  watchdog/mpcore_wdt: Arrange #includes in alphabetical order
  watchdog/mpcore_wdt: remove multiple 'ret = 0' statements from ioctl
    ops
  watchdog/mpcore_wdt: Rename dev to pdev for pointing to struct
    platform_device
  watchdog/mpcore_wdt: do request_irq before registering misc device
  watchdog/mpcore_wdt: Use devm routines
  watchdog/mpcore_wdt: handle module param mpcore_margin in probe
  watchdog/mpcore_wdt: convert to use module_platform_driver()
  watchdog/mpcore_wdt: Add support for dev_pm_ops interface
  watchdog/mpcore_wdt: disable wdt in suspend only if it is busy
  watchdog/mpcore_wdt: Add support for WDIOF_CARDRESET
  watchdog/mpcore_wdt: Allow platform_get_irq() to fail
  watchdog/mpcore_wdt: Add clock framework support
  watchdog/mpcore_wdt: use correct clk_rate to program timeout

 arch/arm/include/asm/smp_twd.h |   12 ++
 drivers/watchdog/mpcore_wdt.c  |  409 ++++++++++++++++++++++++----------------
 2 files changed, 255 insertions(+), 166 deletions(-)

-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:42 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:42 +0530
Subject: [PATCH 01/15] watchdog/mpcore_wdt: Fix multiline comments
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <5c73f2b1efa581d9faaf9ea2d25ba9e0fe9d98b3.1331115752.git.viresh.kumar@st.com>

Following kind of multiline comments are fixed in this patch:
 - Add single line comment instead of multiline one, wherever possible
 - In case of few multiline comment a 'tab' is present instead of 'space' after
   the '*' in the second column. Replace tab with space here.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   61 +++++++++++++++++------------------------
 1 files changed, 25 insertions(+), 36 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 82ccd36..64041ac 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -1,23 +1,21 @@
 /*
- *	Watchdog driver for the mpcore watchdog timer
+ * Watchdog driver for the mpcore watchdog timer
  *
- *	(c) Copyright 2004 ARM Limited
+ * (c) Copyright 2004 ARM Limited
  *
- *	Based on the SoftDog driver:
- *	(c) Copyright 1996 Alan Cox <alan at lxorguk.ukuu.org.uk>,
- *						All Rights Reserved.
+ * Based on the SoftDog driver:
+ * (c) Copyright 1996 Alan Cox <alan at lxorguk.ukuu.org.uk>, All Rights Reserved.
  *
- *	This program is free software; you can redistribute it and/or
- *	modify it under the terms of the GNU General Public License
- *	as published by the Free Software Foundation; either version
- *	2 of the License, or (at your option) any later version.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
  *
- *	Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
- *	warranty for any of this software. This material is provided
- *	"AS-IS" and at no charge.
- *
- *	(c) Copyright 1995    Alan Cox <alan at lxorguk.ukuu.org.uk>
+ * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
+ * warranty for any of this software. This material is provided
+ * "AS-IS" and at no charge.
  *
+ * (c) Copyright 1995    Alan Cox <alan at lxorguk.ukuu.org.uk>
  */
 #include <linux/module.h>
 #include <linux/moduleparam.h>
@@ -68,8 +66,8 @@ MODULE_PARM_DESC(mpcore_noboot, "MPcore watchdog action, "
 					__MODULE_STRING(ONLY_TESTING) ")");
 
 /*
- *	This is the interrupt handler.  Note that we only use this
- *	in testing mode, so don't actually do a reboot here.
+ * This is the interrupt handler.  Note that we only use this
+ * in testing mode, so don't actually do a reboot here.
  */
 static irqreturn_t mpcore_wdt_fire(int irq, void *arg)
 {
@@ -87,11 +85,11 @@ static irqreturn_t mpcore_wdt_fire(int irq, void *arg)
 }
 
 /*
- *	mpcore_wdt_keepalive - reload the timer
+ * mpcore_wdt_keepalive - reload the timer
  *
- *	Note that the spec says a DIFFERENT value must be written to the reload
- *	register each time.  The "perturb" variable deals with this by adding 1
- *	to the count every other time the function is called.
+ * Note that the spec says a DIFFERENT value must be written to the reload
+ * register each time.  The "perturb" variable deals with this by adding 1 to
+ * the count every other time the function is called.
  */
 static void mpcore_wdt_keepalive(struct mpcore_wdt *wdt)
 {
@@ -143,9 +141,7 @@ static int mpcore_wdt_set_heartbeat(int t)
 	return 0;
 }
 
-/*
- *	/dev/watchdog handling
- */
+/* /dev/watchdog handling */
 static int mpcore_wdt_open(struct inode *inode, struct file *file)
 {
 	struct mpcore_wdt *wdt = platform_get_drvdata(mpcore_wdt_dev);
@@ -158,9 +154,7 @@ static int mpcore_wdt_open(struct inode *inode, struct file *file)
 
 	file->private_data = wdt;
 
-	/*
-	 *	Activate timer
-	 */
+	/* Activate timer */
 	mpcore_wdt_start(wdt);
 
 	return nonseekable_open(inode, file);
@@ -171,8 +165,7 @@ static int mpcore_wdt_release(struct inode *inode, struct file *file)
 	struct mpcore_wdt *wdt = file->private_data;
 
 	/*
-	 *	Shut off the timer.
-	 *	Lock it in if it's a module and we set nowayout
+	 * Shut off the timer. Lock it in if it's a module and we set nowayout
 	 */
 	if (wdt->expect_close == 42)
 		mpcore_wdt_stop(wdt);
@@ -191,9 +184,7 @@ static ssize_t mpcore_wdt_write(struct file *file, const char *data,
 {
 	struct mpcore_wdt *wdt = file->private_data;
 
-	/*
-	 *	Refresh the timer.
-	 */
+	/* Refresh the timer. */
 	if (len) {
 		if (!nowayout) {
 			size_t i;
@@ -295,8 +286,8 @@ static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd,
 }
 
 /*
- *	System shutdown handler.  Turn off the watchdog if we're
- *	restarting or halting the system.
+ * System shutdown handler.  Turn off the watchdog if we're restarting or
+ * halting the system.
  */
 static void mpcore_wdt_shutdown(struct platform_device *dev)
 {
@@ -306,9 +297,7 @@ static void mpcore_wdt_shutdown(struct platform_device *dev)
 		mpcore_wdt_stop(wdt);
 }
 
-/*
- *	Kernel Interfaces
- */
+/* Kernel Interfaces */
 static const struct file_operations mpcore_wdt_fops = {
 	.owner		= THIS_MODULE,
 	.llseek		= no_llseek,
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:43 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:43 +0530
Subject: [PATCH 02/15] watchdog/mpcore_wdt: Add blank line after variable
 definitions in routines
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <0ba386ae73e8f716fbc2c9aae35ced5ab93a293a.1331115752.git.viresh.kumar@st.com>

This patch adds blank line between local variable definitions and normal code
inside routine to make code more clean.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 64041ac..25f6e4a 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -399,6 +399,7 @@ static int __devexit mpcore_wdt_remove(struct platform_device *dev)
 static int mpcore_wdt_suspend(struct platform_device *dev, pm_message_t msg)
 {
 	struct mpcore_wdt *wdt = platform_get_drvdata(dev);
+
 	mpcore_wdt_stop(wdt);		/* Turn the WDT off */
 	return 0;
 }
@@ -406,6 +407,7 @@ static int mpcore_wdt_suspend(struct platform_device *dev, pm_message_t msg)
 static int mpcore_wdt_resume(struct platform_device *dev)
 {
 	struct mpcore_wdt *wdt = platform_get_drvdata(dev);
+
 	/* re-activate timer */
 	if (test_bit(0, &wdt->timer_alive))
 		mpcore_wdt_start(wdt);
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:44 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:44 +0530
Subject: [PATCH 03/15] watchdog/mpcore_wdt: Arrange #includes in alphabetical
 order
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <8292539b7e0058cc69c945ee17d0f3347068b021.1331115752.git.viresh.kumar@st.com>

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 25f6e4a..daa6658 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -17,19 +17,19 @@
  *
  * (c) Copyright 1995    Alan Cox <alan at lxorguk.ukuu.org.uk>
  */
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/types.h>
-#include <linux/miscdevice.h>
-#include <linux/watchdog.h>
 #include <linux/fs.h>
-#include <linux/reboot.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
 #include <linux/platform_device.h>
-#include <linux/uaccess.h>
+#include <linux/reboot.h>
 #include <linux/slab.h>
-#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+#include <linux/watchdog.h>
 
 #include <asm/smp_twd.h>
 
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:45 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:45 +0530
Subject: [PATCH 04/15] watchdog/mpcore_wdt: remove multiple 'ret = 0'
 statements from ioctl ops
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <4803ddeb7dfe42ff1d46634bbd9724f8e1eedb67.1331115752.git.viresh.kumar@st.com>

mpcore_wdt_ioctl() has many lines where we do
	ret = 0;

Rewrite this routine to optimize these writes.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   17 +++++------------
 1 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index daa6658..89e8fae 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -217,7 +217,7 @@ static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd,
 							unsigned long arg)
 {
 	struct mpcore_wdt *wdt = file->private_data;
-	int ret;
+	int ret = 0;
 	union {
 		struct watchdog_info ident;
 		int i;
@@ -235,30 +235,24 @@ static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd,
 	switch (cmd) {
 	case WDIOC_GETSUPPORT:
 		uarg.ident = ident;
-		ret = 0;
 		break;
 
 	case WDIOC_GETSTATUS:
 	case WDIOC_GETBOOTSTATUS:
 		uarg.i = 0;
-		ret = 0;
 		break;
 
 	case WDIOC_SETOPTIONS:
-		ret = -EINVAL;
-		if (uarg.i & WDIOS_DISABLECARD) {
+		if (uarg.i & WDIOS_DISABLECARD)
 			mpcore_wdt_stop(wdt);
-			ret = 0;
-		}
-		if (uarg.i & WDIOS_ENABLECARD) {
+		else if (uarg.i & WDIOS_ENABLECARD)
 			mpcore_wdt_start(wdt);
-			ret = 0;
-		}
+		else
+			ret = -EINVAL;
 		break;
 
 	case WDIOC_KEEPALIVE:
 		mpcore_wdt_keepalive(wdt);
-		ret = 0;
 		break;
 
 	case WDIOC_SETTIMEOUT:
@@ -270,7 +264,6 @@ static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd,
 		/* Fall */
 	case WDIOC_GETTIMEOUT:
 		uarg.i = mpcore_margin;
-		ret = 0;
 		break;
 
 	default:
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:46 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:46 +0530
Subject: [PATCH 05/15] watchdog/mpcore_wdt: Rename dev to pdev for pointing to
 struct platform_device
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <fc64d42a383dc95cca64bddbac87c6e1fc578960.1331115752.git.viresh.kumar@st.com>

Pointer to struct platform_device is named as dev, which makes it confusing when
we write statements like dev->dev to access struct device within it.

This patch renames such names to pdev.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   40 ++++++++++++++++++++--------------------
 1 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 89e8fae..1e9c3d3 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -42,7 +42,7 @@ struct mpcore_wdt {
 	char		expect_close;
 };
 
-static struct platform_device *mpcore_wdt_dev;
+static struct platform_device *mpcore_wdt_pdev;
 static DEFINE_SPINLOCK(wdt_lock);
 
 #define TIMER_MARGIN	60
@@ -144,7 +144,7 @@ static int mpcore_wdt_set_heartbeat(int t)
 /* /dev/watchdog handling */
 static int mpcore_wdt_open(struct inode *inode, struct file *file)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(mpcore_wdt_dev);
+	struct mpcore_wdt *wdt = platform_get_drvdata(mpcore_wdt_pdev);
 
 	if (test_and_set_bit(0, &wdt->timer_alive))
 		return -EBUSY;
@@ -282,9 +282,9 @@ static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd,
  * System shutdown handler.  Turn off the watchdog if we're restarting or
  * halting the system.
  */
-static void mpcore_wdt_shutdown(struct platform_device *dev)
+static void mpcore_wdt_shutdown(struct platform_device *pdev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(dev);
+	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
 
 	if (system_state == SYSTEM_RESTART || system_state == SYSTEM_HALT)
 		mpcore_wdt_stop(wdt);
@@ -306,17 +306,17 @@ static struct miscdevice mpcore_wdt_miscdev = {
 	.fops		= &mpcore_wdt_fops,
 };
 
-static int __devinit mpcore_wdt_probe(struct platform_device *dev)
+static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 {
 	struct mpcore_wdt *wdt;
 	struct resource *res;
 	int ret;
 
 	/* We only accept one device, and it must have an id of -1 */
-	if (dev->id != -1)
+	if (pdev->id != -1)
 		return -ENODEV;
 
-	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		ret = -ENODEV;
 		goto err_out;
@@ -328,8 +328,8 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev)
 		goto err_out;
 	}
 
-	wdt->dev = &dev->dev;
-	wdt->irq = platform_get_irq(dev, 0);
+	wdt->dev = &pdev->dev;
+	wdt->irq = platform_get_irq(pdev, 0);
 	if (wdt->irq < 0) {
 		ret = -ENXIO;
 		goto err_free;
@@ -340,7 +340,7 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev)
 		goto err_free;
 	}
 
-	mpcore_wdt_miscdev.parent = &dev->dev;
+	mpcore_wdt_miscdev.parent = &pdev->dev;
 	ret = misc_register(&mpcore_wdt_miscdev);
 	if (ret) {
 		dev_printk(KERN_ERR, wdt->dev,
@@ -357,8 +357,8 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev)
 	}
 
 	mpcore_wdt_stop(wdt);
-	platform_set_drvdata(dev, wdt);
-	mpcore_wdt_dev = dev;
+	platform_set_drvdata(pdev, wdt);
+	mpcore_wdt_pdev = pdev;
 
 	return 0;
 
@@ -372,15 +372,15 @@ err_out:
 	return ret;
 }
 
-static int __devexit mpcore_wdt_remove(struct platform_device *dev)
+static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(dev);
+	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
 
-	platform_set_drvdata(dev, NULL);
+	platform_set_drvdata(pdev, NULL);
 
 	misc_deregister(&mpcore_wdt_miscdev);
 
-	mpcore_wdt_dev = NULL;
+	mpcore_wdt_pdev = NULL;
 
 	free_irq(wdt->irq, wdt);
 	iounmap(wdt->base);
@@ -389,17 +389,17 @@ static int __devexit mpcore_wdt_remove(struct platform_device *dev)
 }
 
 #ifdef CONFIG_PM
-static int mpcore_wdt_suspend(struct platform_device *dev, pm_message_t msg)
+static int mpcore_wdt_suspend(struct platform_device *pdev, pm_message_t msg)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(dev);
+	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
 
 	mpcore_wdt_stop(wdt);		/* Turn the WDT off */
 	return 0;
 }
 
-static int mpcore_wdt_resume(struct platform_device *dev)
+static int mpcore_wdt_resume(struct platform_device *pdev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(dev);
+	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
 
 	/* re-activate timer */
 	if (test_bit(0, &wdt->timer_alive))
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:47 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:47 +0530
Subject: [PATCH 06/15] watchdog/mpcore_wdt: do request_irq before registering
 misc device
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <a3f18ec8fa44163c7b0ba886f9e99583e17ece37.1331115752.git.viresh.kumar@st.com>

Ideally, device/driver must be completely ready while we register it with any
framework. This includes allocating resources, registering irqs, etc. Currently
for mpcore_wdt irq is requested after it is registered as a misc device.

So, this patch moves request_irq before registration of misc device.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 1e9c3d3..db379f7 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -340,6 +340,13 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		goto err_free;
 	}
 
+	ret = request_irq(wdt->irq, mpcore_wdt_fire, 0, "mpcore_wdt", wdt);
+	if (ret) {
+		dev_printk(KERN_ERR, wdt->dev,
+			"cannot register IRQ%d for watchdog\n", wdt->irq);
+		goto err_irq;
+	}
+
 	mpcore_wdt_miscdev.parent = &pdev->dev;
 	ret = misc_register(&mpcore_wdt_miscdev);
 	if (ret) {
@@ -349,22 +356,15 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		goto err_misc;
 	}
 
-	ret = request_irq(wdt->irq, mpcore_wdt_fire, 0, "mpcore_wdt", wdt);
-	if (ret) {
-		dev_printk(KERN_ERR, wdt->dev,
-			"cannot register IRQ%d for watchdog\n", wdt->irq);
-		goto err_irq;
-	}
-
 	mpcore_wdt_stop(wdt);
 	platform_set_drvdata(pdev, wdt);
 	mpcore_wdt_pdev = pdev;
 
 	return 0;
 
-err_irq:
-	misc_deregister(&mpcore_wdt_miscdev);
 err_misc:
+	free_irq(wdt->irq, wdt);
+err_irq:
 	iounmap(wdt->base);
 err_free:
 	kfree(wdt);
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:49 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:49 +0530
Subject: [PATCH 08/15] watchdog/mpcore_wdt: handle module param mpcore_margin
 in probe
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <1a4d3c2c9d58e5cc0d3770fd57d0d870cfd681c4.1331115752.git.viresh.kumar@st.com>

Currently mpcore_margin is handled in mpcore_wdt_init routine, which will be
called even if we don't have added any device for watchdog. Probably this is not
we want.

This patch moves this code into probe routine, so that it only gets hit once we
add device for this driver.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   30 +++++++++++++++---------------
 1 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 209c81d..9c58c63 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -306,6 +306,9 @@ static struct miscdevice mpcore_wdt_miscdev = {
 	.fops		= &mpcore_wdt_fops,
 };
 
+static char banner[] __initdata = KERN_INFO "MPcore Watchdog Timer: 0.1. "
+		"mpcore_noboot=%d mpcore_margin=%d sec (nowayout= %d)\n";
+
 static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 {
 	struct mpcore_wdt *wdt;
@@ -341,6 +344,18 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	/*
+	 * Check that the margin value is within it's range;
+	 * if not reset to the default
+	 */
+	if (mpcore_wdt_set_heartbeat(mpcore_margin)) {
+		mpcore_wdt_set_heartbeat(TIMER_MARGIN);
+		printk(KERN_INFO "mpcore_margin value must be 0 < mpcore_margin < 65536, using %d\n",
+			TIMER_MARGIN);
+	}
+
+	printk(banner, mpcore_noboot, mpcore_margin, nowayout);
+
 	mpcore_wdt_miscdev.parent = &pdev->dev;
 	ret = misc_register(&mpcore_wdt_miscdev);
 	if (ret) {
@@ -406,23 +421,8 @@ static struct platform_driver mpcore_wdt_driver = {
 	},
 };
 
-static char banner[] __initdata = KERN_INFO "MPcore Watchdog Timer: 0.1. "
-		"mpcore_noboot=%d mpcore_margin=%d sec (nowayout= %d)\n";
-
 static int __init mpcore_wdt_init(void)
 {
-	/*
-	 * Check that the margin value is within it's range;
-	 * if not reset to the default
-	 */
-	if (mpcore_wdt_set_heartbeat(mpcore_margin)) {
-		mpcore_wdt_set_heartbeat(TIMER_MARGIN);
-		printk(KERN_INFO "mpcore_margin value must be 0 < mpcore_margin < 65536, using %d\n",
-			TIMER_MARGIN);
-	}
-
-	printk(banner, mpcore_noboot, mpcore_margin, nowayout);
-
 	return platform_driver_register(&mpcore_wdt_driver);
 }
 
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:48 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:48 +0530
Subject: [PATCH 07/15] watchdog/mpcore_wdt: Use devm routines
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <8d5d4f4d36452bdf1005700c4376798e25f59adf.1331115752.git.viresh.kumar@st.com>

mpcore_wdt driver currently uses normal kzalloc, request_irq, ioremap, etc
routines. This patch replaces these routines with devm_kzalloc and
devm_request_mem_region etc, so that we don't need to handle freeing of
resources for error cases and module removal routine.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   50 ++++++++++++----------------------------
 1 files changed, 15 insertions(+), 35 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index db379f7..209c81d 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -317,34 +317,28 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		return -ENODEV;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		ret = -ENODEV;
-		goto err_out;
-	}
+	if (!res)
+		return -ENODEV;
 
-	wdt = kzalloc(sizeof(struct mpcore_wdt), GFP_KERNEL);
-	if (!wdt) {
-		ret = -ENOMEM;
-		goto err_out;
-	}
+	wdt = devm_kzalloc(&pdev->dev, sizeof(struct mpcore_wdt), GFP_KERNEL);
+	if (!wdt)
+		return -ENOMEM;
 
 	wdt->dev = &pdev->dev;
 	wdt->irq = platform_get_irq(pdev, 0);
-	if (wdt->irq < 0) {
-		ret = -ENXIO;
-		goto err_free;
-	}
-	wdt->base = ioremap(res->start, resource_size(res));
-	if (!wdt->base) {
-		ret = -ENOMEM;
-		goto err_free;
-	}
+	if (wdt->irq < 0)
+		return -ENXIO;
 
-	ret = request_irq(wdt->irq, mpcore_wdt_fire, 0, "mpcore_wdt", wdt);
+	wdt->base = devm_ioremap(wdt->dev, res->start, resource_size(res));
+	if (!wdt->base)
+		return -ENOMEM;
+
+	ret = devm_request_irq(wdt->dev, wdt->irq, mpcore_wdt_fire, 0,
+			"mpcore_wdt", wdt);
 	if (ret) {
 		dev_printk(KERN_ERR, wdt->dev,
 			"cannot register IRQ%d for watchdog\n", wdt->irq);
-		goto err_irq;
+		return ret;
 	}
 
 	mpcore_wdt_miscdev.parent = &pdev->dev;
@@ -353,7 +347,7 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		dev_printk(KERN_ERR, wdt->dev,
 			"cannot register miscdev on minor=%d (err=%d)\n",
 							WATCHDOG_MINOR, ret);
-		goto err_misc;
+		return ret;
 	}
 
 	mpcore_wdt_stop(wdt);
@@ -361,30 +355,16 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 	mpcore_wdt_pdev = pdev;
 
 	return 0;
-
-err_misc:
-	free_irq(wdt->irq, wdt);
-err_irq:
-	iounmap(wdt->base);
-err_free:
-	kfree(wdt);
-err_out:
-	return ret;
 }
 
 static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
-
 	platform_set_drvdata(pdev, NULL);
 
 	misc_deregister(&mpcore_wdt_miscdev);
 
 	mpcore_wdt_pdev = NULL;
 
-	free_irq(wdt->irq, wdt);
-	iounmap(wdt->base);
-	kfree(wdt);
 	return 0;
 }
 
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:50 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:50 +0530
Subject: [PATCH 09/15] watchdog/mpcore_wdt: convert to use
 module_platform_driver()
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <f286cb3454c3447f5551e6c24e27c9e478833e23.1331115752.git.viresh.kumar@st.com>

This patch converts the mpcore_wdt driver to use the module_platform_driver()
macro which makes the code smaller and a bit simpler.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   13 +------------
 1 files changed, 1 insertions(+), 12 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 9c58c63..e02c02b 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -421,18 +421,7 @@ static struct platform_driver mpcore_wdt_driver = {
 	},
 };
 
-static int __init mpcore_wdt_init(void)
-{
-	return platform_driver_register(&mpcore_wdt_driver);
-}
-
-static void __exit mpcore_wdt_exit(void)
-{
-	platform_driver_unregister(&mpcore_wdt_driver);
-}
-
-module_init(mpcore_wdt_init);
-module_exit(mpcore_wdt_exit);
+module_platform_driver(mpcore_wdt_driver);
 
 MODULE_AUTHOR("ARM Limited");
 MODULE_DESCRIPTION("MPcore Watchdog Device Driver");
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:51 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:51 +0530
Subject: [PATCH 10/15] watchdog/mpcore_wdt: Add support for dev_pm_ops
 interface
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <b50542be97df8b90d3e7c696a8d13be707f581f9.1331115752.git.viresh.kumar@st.com>

This patch adds dev_pm_ops support for standby/slepp/hibernate.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index e02c02b..a099418 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -25,6 +25,7 @@
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/platform_device.h>
+#include <linux/pm.h>
 #include <linux/reboot.h>
 #include <linux/slab.h>
 #include <linux/types.h>
@@ -384,40 +385,39 @@ static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM
-static int mpcore_wdt_suspend(struct platform_device *pdev, pm_message_t msg)
+static int mpcore_wdt_suspend(struct device *dev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
+	struct mpcore_wdt *wdt = dev_get_drvdata(dev);
 
 	mpcore_wdt_stop(wdt);		/* Turn the WDT off */
 	return 0;
 }
 
-static int mpcore_wdt_resume(struct platform_device *pdev)
+static int mpcore_wdt_resume(struct device *dev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
+	struct mpcore_wdt *wdt = dev_get_drvdata(dev);
 
 	/* re-activate timer */
 	if (test_bit(0, &wdt->timer_alive))
 		mpcore_wdt_start(wdt);
 	return 0;
 }
-#else
-#define mpcore_wdt_suspend	NULL
-#define mpcore_wdt_resume	NULL
 #endif
 
+static SIMPLE_DEV_PM_OPS(mpcore_wdt_dev_pm_ops, mpcore_wdt_suspend,
+		mpcore_wdt_resume);
+
 /* work with hotplug and coldplug */
 MODULE_ALIAS("platform:mpcore_wdt");
 
 static struct platform_driver mpcore_wdt_driver = {
 	.probe		= mpcore_wdt_probe,
 	.remove		= __devexit_p(mpcore_wdt_remove),
-	.suspend	= mpcore_wdt_suspend,
-	.resume		= mpcore_wdt_resume,
 	.shutdown	= mpcore_wdt_shutdown,
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "mpcore_wdt",
+		.pm = &mpcore_wdt_dev_pm_ops,
 	},
 };
 
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:52 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:52 +0530
Subject: [PATCH 11/15] watchdog/mpcore_wdt: disable wdt in suspend only if it
 is busy
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <f58a3c64f2768de81f910b75a5f1dfbb213aaac6.1331115752.git.viresh.kumar@st.com>

We don't need to call mpcore_wdt_stop() in suspend, if wdt is not BUSY. So, call
mpcore_wdt_stop() conditionally in suspend.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index a099418..27a5069 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -389,7 +389,8 @@ static int mpcore_wdt_suspend(struct device *dev)
 {
 	struct mpcore_wdt *wdt = dev_get_drvdata(dev);
 
-	mpcore_wdt_stop(wdt);		/* Turn the WDT off */
+	if (test_bit(0, &wdt->timer_alive))
+		mpcore_wdt_stop(wdt);		/* Turn the WDT off */
 	return 0;
 }
 
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:54 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:54 +0530
Subject: [PATCH 13/15] watchdog/mpcore_wdt: Allow platform_get_irq() to fail
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <df548cd74c18aaf00b42cb2976a6b274a4b95c56.1331115752.git.viresh.kumar@st.com>

irq is not necessary for mpcore wdt. Don't return error if it is not passed. But
if it is passed, then request_irq must pass.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 6a04e31..ebd964a 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -334,20 +334,20 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	wdt->dev = &pdev->dev;
-	wdt->irq = platform_get_irq(pdev, 0);
-	if (wdt->irq < 0)
-		return -ENXIO;
 
 	wdt->base = devm_ioremap(wdt->dev, res->start, resource_size(res));
 	if (!wdt->base)
 		return -ENOMEM;
 
-	ret = devm_request_irq(wdt->dev, wdt->irq, mpcore_wdt_fire, 0,
-			"mpcore_wdt", wdt);
-	if (ret) {
-		dev_printk(KERN_ERR, wdt->dev,
-			"cannot register IRQ%d for watchdog\n", wdt->irq);
-		return ret;
+	wdt->irq = platform_get_irq(pdev, 0);
+	if (wdt->irq >= 0) {
+		ret = devm_request_irq(wdt->dev, wdt->irq, mpcore_wdt_fire, 0,
+				"mpcore_wdt", wdt);
+		if (ret) {
+			dev_printk(KERN_ERR, wdt->dev,
+					"cannot register IRQ%d for watchdog\n", wdt->irq);
+			return ret;
+		}
 	}
 
 	/*
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:55 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:55 +0530
Subject: [PATCH 14/15] watchdog/mpcore_wdt: Add clock framework support
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <9ec7141baa4b1c1a0503893749e7ce0e19bb5029.1331115752.git.viresh.kumar@st.com>

This patch adds in clk framework support for wdt driver. If clk_get fails for
some platform, then we continue without clk_* API's.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   71 ++++++++++++++++++++++++++++++++++++-----
 1 files changed, 63 insertions(+), 8 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index ebd964a..9747193 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -17,6 +17,7 @@
  *
  * (c) Copyright 1995    Alan Cox <alan at lxorguk.ukuu.org.uk>
  */
+#include <linux/clk.h>
 #include <linux/fs.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
@@ -39,6 +40,7 @@ struct mpcore_wdt {
 	unsigned long	boot_status;
 	struct device	*dev;
 	void __iomem	*base;
+	struct clk	*clk;
 	int		irq;
 	unsigned int	perturb;
 	char		expect_close;
@@ -147,6 +149,7 @@ static int mpcore_wdt_set_heartbeat(int t)
 static int mpcore_wdt_open(struct inode *inode, struct file *file)
 {
 	struct mpcore_wdt *wdt = platform_get_drvdata(mpcore_wdt_pdev);
+	int ret;
 
 	if (test_and_set_bit(0, &wdt->timer_alive))
 		return -EBUSY;
@@ -156,10 +159,22 @@ static int mpcore_wdt_open(struct inode *inode, struct file *file)
 
 	file->private_data = wdt;
 
+	if (wdt->clk) {
+		ret = clk_enable(wdt->clk);
+		if (ret) {
+			dev_err(wdt->dev, "clock enable fail");
+			goto err;
+		}
+	}
+
 	/* Activate timer */
 	mpcore_wdt_start(wdt);
 
 	return nonseekable_open(inode, file);
+
+err:
+	clear_bit(0, &wdt->timer_alive);
+	return ret;
 }
 
 static int mpcore_wdt_release(struct inode *inode, struct file *file)
@@ -169,9 +184,12 @@ static int mpcore_wdt_release(struct inode *inode, struct file *file)
 	/*
 	 * Shut off the timer. Lock it in if it's a module and we set nowayout
 	 */
-	if (wdt->expect_close == 42)
+	if (wdt->expect_close == 42) {
 		mpcore_wdt_stop(wdt);
-	else {
+
+		if (wdt->clk)
+			clk_disable(wdt->clk);
+	} else {
 		dev_printk(KERN_CRIT, wdt->dev,
 				"unexpected close, not stopping watchdog!\n");
 		mpcore_wdt_keepalive(wdt);
@@ -350,6 +368,28 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		}
 	}
 
+	wdt->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(wdt->clk)) {
+		dev_warn(&pdev->dev, "Clock not found\n");
+		wdt->clk = NULL;
+	}
+
+	if (wdt->clk) {
+		ret = clk_enable(wdt->clk);
+		if (ret) {
+			dev_err(&pdev->dev, "Clock enable failed\n");
+			goto err_put_clk;
+		}
+	}
+
+	wdt->boot_status = (readl(wdt->base + TWD_WDOG_RESETSTAT) &
+			TWD_WDOG_RESETSTAT_MASK) ? WDIOF_CARDRESET : 0;
+
+	mpcore_wdt_stop(wdt);
+
+	if (wdt->clk)
+		clk_disable(wdt->clk);
+
 	/*
 	 * Check that the margin value is within it's range;
 	 * if not reset to the default
@@ -368,25 +408,32 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		dev_printk(KERN_ERR, wdt->dev,
 			"cannot register miscdev on minor=%d (err=%d)\n",
 							WATCHDOG_MINOR, ret);
-		return ret;
+		goto err_put_clk;
 	}
 
-	wdt->boot_status = (readl(wdt->base + TWD_WDOG_RESETSTAT) &
-			TWD_WDOG_RESETSTAT_MASK) ? WDIOF_CARDRESET : 0;
-
-	mpcore_wdt_stop(wdt);
 	platform_set_drvdata(pdev, wdt);
 	mpcore_wdt_pdev = pdev;
 
 	return 0;
+
+err_put_clk:
+	if (wdt->clk)
+		clk_put(wdt->clk);
+
+	return ret;
 }
 
 static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
 {
+	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
+
 	platform_set_drvdata(pdev, NULL);
 
 	misc_deregister(&mpcore_wdt_miscdev);
 
+	if (wdt->clk)
+		clk_put(wdt->clk);
+
 	mpcore_wdt_pdev = NULL;
 
 	return 0;
@@ -399,6 +446,9 @@ static int mpcore_wdt_suspend(struct device *dev)
 
 	if (test_bit(0, &wdt->timer_alive))
 		mpcore_wdt_stop(wdt);		/* Turn the WDT off */
+
+	if (wdt->clk)
+		clk_disable(wdt->clk);
 	return 0;
 }
 
@@ -407,8 +457,13 @@ static int mpcore_wdt_resume(struct device *dev)
 	struct mpcore_wdt *wdt = dev_get_drvdata(dev);
 
 	/* re-activate timer */
-	if (test_bit(0, &wdt->timer_alive))
+	if (test_bit(0, &wdt->timer_alive)) {
+		if (wdt->clk)
+			clk_enable(wdt->clk);
+
 		mpcore_wdt_start(wdt);
+	}
+
 	return 0;
 }
 #endif
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:56 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:56 +0530
Subject: [PATCH 15/15] watchdog/mpcore_wdt: use correct clk_rate to program
 timeout
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <df077de1c4561a5d3c42260d57cfc7732d292e22.1331115752.git.viresh.kumar@st.com>

Currently, mpcore wdt driver doesn't use exact clk_rate to program timeout in
hardware. This patch provides two ways of doing so:
	- either use clk_get_rate() if clk_get passes
	- use clk_rate passed via module param

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/include/asm/smp_twd.h |   10 ++++
 drivers/watchdog/mpcore_wdt.c  |  104 +++++++++++++++++++++++++++++++--------
 2 files changed, 92 insertions(+), 22 deletions(-)

diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index a13b536..389ca02 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -13,11 +13,21 @@
 #define TWD_WDOG_RESETSTAT		0x30
 #define TWD_WDOG_DISABLE		0x34
 
+#define TWD_WDOG_LOAD_MIN		0x00000000
+#define TWD_WDOG_LOAD_MAX		0xFFFFFFFF
+
 #define TWD_TIMER_CONTROL_ENABLE	(1 << 0)
 #define TWD_TIMER_CONTROL_ONESHOT	(0 << 1)
 #define TWD_TIMER_CONTROL_PERIODIC	(1 << 1)
 #define TWD_TIMER_CONTROL_IT_ENABLE	(1 << 2)
 
+#define TWD_WDOG_CONTROL_ENABLE		(1 << 0)
+#define TWD_WDOG_CONTROL_IRQ_ENABLE	(1 << 2)
+#define TWD_WDOG_CONTROL_WDT_MODE	(1 << 3)
+#define TWD_WDOG_CONTROL_WDT_PRESCALE(x)	((x) << 8)
+#define TWD_WDOG_CONTROL_PRESCALE_MIN	0x00
+#define TWD_WDOG_CONTROL_PRESCALE_MAX	0xFF
+
 #define TWD_WDOG_RESETSTAT_MASK		0x1
 
 struct clock_event_device;
diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 9747193..fc14709 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -41,7 +41,10 @@ struct mpcore_wdt {
 	struct device	*dev;
 	void __iomem	*base;
 	struct clk	*clk;
+	unsigned long	clk_rate;	/* In Hz */
 	int		irq;
+	unsigned int	prescale;
+	unsigned int	load_val;
 	unsigned int	perturb;
 	char		expect_close;
 };
@@ -62,6 +65,11 @@ MODULE_PARM_DESC(nowayout,
 	"Watchdog cannot be stopped once started (default="
 				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 
+static int clk_rate;
+module_param(clk_rate, int, 0);
+MODULE_PARM_DESC(clk_rate,
+	"Watchdog clock rate in Hz, required if clk_get() fails");
+
 #define ONLY_TESTING	0
 static int mpcore_noboot = ONLY_TESTING;
 module_param(mpcore_noboot, int, 0);
@@ -97,17 +105,9 @@ static irqreturn_t mpcore_wdt_fire(int irq, void *arg)
  */
 static void mpcore_wdt_keepalive(struct mpcore_wdt *wdt)
 {
-	unsigned long count;
-
 	spin_lock(&wdt_lock);
-	/* Assume prescale is set to 256 */
-	count =  __raw_readl(wdt->base + TWD_WDOG_COUNTER);
-	count = (0xFFFFFFFFU - count) * (HZ / 5);
-	count = (count / 256) * mpcore_margin;
-
-	/* Reload the counter */
-	writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD);
-	wdt->perturb = wdt->perturb ? 0 : 1;
+	writel(wdt->load_val + wdt->perturb, wdt->base + TWD_WDOG_LOAD);
+	wdt->perturb = !wdt->perturb;
 	spin_unlock(&wdt_lock);
 }
 
@@ -122,26 +122,76 @@ static void mpcore_wdt_stop(struct mpcore_wdt *wdt)
 
 static void mpcore_wdt_start(struct mpcore_wdt *wdt)
 {
+	u32 val, mode;
+
 	dev_printk(KERN_INFO, wdt->dev, "enabling watchdog.\n");
 
 	/* This loads the count register but does NOT start the count yet */
 	mpcore_wdt_keepalive(wdt);
 
-	if (mpcore_noboot) {
-		/* Enable watchdog - prescale=256, watchdog mode=0, enable=1 */
-		writel(0x0000FF01, wdt->base + TWD_WDOG_CONTROL);
-	} else {
-		/* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */
-		writel(0x0000FF09, wdt->base + TWD_WDOG_CONTROL);
+	if (mpcore_noboot)
+		mode = 0;
+	else
+		mode = TWD_WDOG_CONTROL_WDT_MODE;
+
+	spin_lock(&wdt_lock);
+
+	val = TWD_WDOG_CONTROL_WDT_PRESCALE(wdt->prescale) |
+		TWD_WDOG_CONTROL_ENABLE | mode;
+	writel(val, wdt->base + TWD_WDOG_CONTROL);
+
+	spin_unlock(&wdt_lock);
+}
+
+/* binary search */
+static inline void bsearch(u32 *var, u32 var_start, u32 var_end,
+		const u64 param, const u32 timeout, u32 rate)
+{
+	u64 tmp = 0;
+
+	/* get the lowest var value that can satisfy our requirement */
+	while (var_start < var_end) {
+		tmp = var_start;
+		tmp += var_end;
+		tmp = div_u64(tmp, 2);
+		if (timeout > div_u64((param + 1) * (tmp + 1), rate)) {
+			if (var_start == tmp)
+				break;
+			else
+				var_start = tmp;
+		} else {
+			if (var_end == tmp)
+				break;
+			else
+				var_end = tmp;
+		}
 	}
+	*var = tmp;
 }
 
-static int mpcore_wdt_set_heartbeat(int t)
+static int mpcore_wdt_set_heartbeat(struct mpcore_wdt *wdt, int timeout)
 {
-	if (t < 0x0001 || t > 0xFFFF)
+	unsigned int psc, rate = wdt->clk_rate;
+	u64 load = 0;
+
+	if (timeout < 0x0001 || timeout > 0xFFFF)
 		return -EINVAL;
 
-	mpcore_margin = t;
+	/* get appropriate value of psc and load */
+	bsearch(&psc, TWD_WDOG_CONTROL_PRESCALE_MIN,
+			TWD_WDOG_CONTROL_PRESCALE_MAX, TWD_WDOG_LOAD_MAX,
+			timeout, rate);
+	bsearch((u32 *)&load, TWD_WDOG_LOAD_MIN, TWD_WDOG_LOAD_MAX, psc,
+			timeout, rate);
+
+	spin_lock(&wdt_lock);
+	wdt->prescale = psc;
+	wdt->load_val = load;
+
+	/* roundup timeout to closest positive integer value */
+	mpcore_margin = div_u64((psc + 1) * (load + 1) + (rate / 2), rate);
+	spin_unlock(&wdt_lock);
+
 	return 0;
 }
 
@@ -280,7 +330,7 @@ static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd,
 		break;
 
 	case WDIOC_SETTIMEOUT:
-		ret = mpcore_wdt_set_heartbeat(uarg.i);
+		ret = mpcore_wdt_set_heartbeat(wdt, uarg.i);
 		if (ret)
 			break;
 
@@ -372,6 +422,16 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 	if (IS_ERR(wdt->clk)) {
 		dev_warn(&pdev->dev, "Clock not found\n");
 		wdt->clk = NULL;
+
+		wdt->clk_rate = clk_rate;
+	} else {
+		wdt->clk_rate = clk_get_rate(wdt->clk);
+	}
+
+	if (!wdt->clk_rate) {
+		dev_err(&pdev->dev, "Clock rate can't be zero\n");
+		ret = -EINVAL;
+		goto err_put_clk;
 	}
 
 	if (wdt->clk) {
@@ -394,8 +454,8 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 	 * Check that the margin value is within it's range;
 	 * if not reset to the default
 	 */
-	if (mpcore_wdt_set_heartbeat(mpcore_margin)) {
-		mpcore_wdt_set_heartbeat(TIMER_MARGIN);
+	if (mpcore_wdt_set_heartbeat(wdt, mpcore_margin)) {
+		mpcore_wdt_set_heartbeat(wdt, TIMER_MARGIN);
 		printk(KERN_INFO "mpcore_margin value must be 0 < mpcore_margin < 65536, using %d\n",
 			TIMER_MARGIN);
 	}
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Wed Mar  7 05:27:53 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 7 Mar 2012 15:57:53 +0530
Subject: [PATCH 12/15] watchdog/mpcore_wdt: Add support for WDIOF_CARDRESET
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <cb4bdf968a4d53eebf8005636fcef5fde8cbebf7.1331115752.git.viresh.kumar@st.com>

mpcore watchdog can give last boot status, whether we got a watchdog reset or
not, via bit 0 of TWD_WDOG_RESETSTAT register. This patch adds support to return
correct status if WDIOC_GETBOOTSTATUS cmd is called with ioctl.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/include/asm/smp_twd.h |    2 ++
 drivers/watchdog/mpcore_wdt.c  |   10 +++++++++-
 2 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index ef9ffba9..a13b536 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -18,6 +18,8 @@
 #define TWD_TIMER_CONTROL_PERIODIC	(1 << 1)
 #define TWD_TIMER_CONTROL_IT_ENABLE	(1 << 2)
 
+#define TWD_WDOG_RESETSTAT_MASK		0x1
+
 struct clock_event_device;
 
 extern void __iomem *twd_base;
diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 27a5069..6a04e31 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -36,6 +36,7 @@
 
 struct mpcore_wdt {
 	unsigned long	timer_alive;
+	unsigned long	boot_status;
 	struct device	*dev;
 	void __iomem	*base;
 	int		irq;
@@ -210,6 +211,7 @@ static ssize_t mpcore_wdt_write(struct file *file, const char *data,
 static const struct watchdog_info ident = {
 	.options		= WDIOF_SETTIMEOUT |
 				  WDIOF_KEEPALIVEPING |
+				  WDIOF_CARDRESET |
 				  WDIOF_MAGICCLOSE,
 	.identity		= "MPcore Watchdog",
 };
@@ -239,10 +241,13 @@ static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd,
 		break;
 
 	case WDIOC_GETSTATUS:
-	case WDIOC_GETBOOTSTATUS:
 		uarg.i = 0;
 		break;
 
+	case WDIOC_GETBOOTSTATUS:
+		uarg.i = wdt->boot_status;
+		break;
+
 	case WDIOC_SETOPTIONS:
 		if (uarg.i & WDIOS_DISABLECARD)
 			mpcore_wdt_stop(wdt);
@@ -366,6 +371,9 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	wdt->boot_status = (readl(wdt->base + TWD_WDOG_RESETSTAT) &
+			TWD_WDOG_RESETSTAT_MASK) ? WDIOF_CARDRESET : 0;
+
 	mpcore_wdt_stop(wdt);
 	platform_set_drvdata(pdev, wdt);
 	mpcore_wdt_pdev = pdev;
-- 
1.7.8.110.g4cb5d



From w.sang at pengutronix.de  Wed Mar  7 05:34:14 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed, 7 Mar 2012 11:34:14 +0100
Subject: [PATCH 00/15] watchdog/mpcore: updates & fixes
In-Reply-To: <cover.1331115751.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
Message-ID: <20120307103414.GA2568@pengutronix.de>


> This patchset contains fixes and updates for ARM mpcore watchdog driver.

It probably makes sense to convert this to use the watchdog-core. See
Documentation/watchdog/convert_drivers_to_kernel_api.txt for some
guidance.

Thanks,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From kgene.kim at samsung.com  Wed Mar  7 05:36:52 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed,  7 Mar 2012 02:36:52 -0800
Subject: [PATCH] ARM: S3C24XX: Fix Section mismatch
Message-ID: <1331116612-14491-1-git-send-email-kgene.kim@samsung.com>

Fixes following:

WARNING: arch/arm/mach-s3c24xx/built-in.o(.text+0x4464): Section mismatch in reference
from the function usb_simtec_init() to the (unknown reference) .init.data:(unknown)
The function usb_simtec_init() references
the (unknown reference) __initdata (unknown).
This is often because usb_simtec_init lacks a __initdata
annotation or the annotation of (unknown) is wrong.

WARNING: arch/arm/mach-s3c24xx/built-in.o(.data+0xf44): Section mismatch in reference
from the variable s3c2416_irq_interface to the function .init.text:s3c2416_irq_add()
The variable s3c2416_irq_interface references
the function __init s3c2416_irq_add()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

WARNING: arch/arm/mach-s3c24xx/built-in.o(.data+0x1b80): Section mismatch in reference
from the variable s3c2443_irq_interface to the function .init.text:s3c2443_irq_add()
The variable s3c2443_irq_interface references
the function __init s3c2443_irq_add()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s3c24xx/irq-s3c2416.c |    2 +-
 arch/arm/mach-s3c24xx/irq-s3c2443.c |    2 +-
 arch/arm/mach-s3c24xx/simtec-usb.c  |    2 +-
 arch/arm/mach-s3c24xx/simtec.h      |    2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
index b8a5836..59b7632 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2416.c
@@ -310,7 +310,7 @@ static int __init s3c2416_irq_add(struct device *dev)
 	return 0;
 }
 
-static struct subsys_interface s3c2416_irq_interface = {
+static struct subsys_interface s3c2416_irq_interface __initdata = {
 	.name		= "s3c2416_irq",
 	.subsys		= &s3c2416_subsys,
 	.add_dev	= s3c2416_irq_add,
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2443.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c
index 35e4ff2..439f186 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2443.c
@@ -265,7 +265,7 @@ static int __init s3c2443_irq_add(struct device *dev)
 	return 0;
 }
 
-static struct subsys_interface s3c2443_irq_interface = {
+static struct subsys_interface s3c2443_irq_interface __initdata = {
 	.name		= "s3c2443_irq",
 	.subsys		= &s3c2443_subsys,
 	.add_dev	= s3c2443_irq_add,
diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c
index d91c1a7..c303d1b 100644
--- a/arch/arm/mach-s3c24xx/simtec-usb.c
+++ b/arch/arm/mach-s3c24xx/simtec-usb.c
@@ -104,7 +104,7 @@ static struct s3c2410_hcd_info usb_simtec_info __initdata = {
 };
 
 
-int usb_simtec_init(void)
+int __init usb_simtec_init(void)
 {
 	int ret;
 
diff --git a/arch/arm/mach-s3c24xx/simtec.h b/arch/arm/mach-s3c24xx/simtec.h
index ae8f4f9..f514cd5 100644
--- a/arch/arm/mach-s3c24xx/simtec.h
+++ b/arch/arm/mach-s3c24xx/simtec.h
@@ -15,7 +15,7 @@ struct s3c24xx_audio_simtec_pdata;
 
 extern void nor_simtec_init(void);
 
-extern int usb_simtec_init(void);
+extern int __init usb_simtec_init(void);
 
 extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
 			    struct s3c24xx_audio_simtec_pdata *pdata);
-- 
1.7.4.4



From 21cnbao at gmail.com  Wed Mar  7 05:38:44 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 7 Mar 2012 18:38:44 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <4F56EBA6.6000704@gmail.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com>
 <CAGsJ_4x4CwD+WAE9d+Xob_tfwqmE6SdBdBd5EbC64XBi4Uzvgg@mail.gmail.com>
 <4F56EA49.8070808@gmail.com>
 <CAGsJ_4xJoKGt3+b_3bteoMyeO615pCxFpMpsH4LtvufFNDv6bA@mail.gmail.com>
 <4F56EBA6.6000704@gmail.com>
Message-ID: <CAGsJ_4wd14LNGf0xtbTzvGn5v0WUcRiN04OC+wtDqSrem0di4w@mail.gmail.com>

2012/3/7 Cong Wang <xiyou.wangcong at gmail.com>:
> On 03/07/2012 12:57 PM, Barry Song wrote:
>>
>>
>> if you think so, pls do that and send v4 with your s-o-b.
>>
>
> This is not a good attitude, nor helps your patch to be merged...
>
> Be collaborative.

pls just focus on techinical discussion and note you are not the man
to decide whether the patch should be merged. Many people know how to
make patches merged well.
you said that just like you are the one maintaining MM. Be modest, man!

-barry


From plagnioj at jcrosoft.com  Wed Mar  7 05:33:52 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 11:33:52 +0100
Subject: [PATCH 1/9 v2] ARM: at91: usb ohci add dt support
In-Reply-To: <20120307093446.GN17370@n2100.arm.linux.org.uk>
References: <20120307084924.GK21255@game.jcrosoft.org>
 <1331111746-21393-1-git-send-email-plagnioj@jcrosoft.com>
 <20120307093446.GN17370@n2100.arm.linux.org.uk>
Message-ID: <20120307103352.GA17745@game.jcrosoft.org>

On 09:34 Wed 07 Mar     , Russell King - ARM Linux wrote:
> On Wed, Mar 07, 2012 at 10:15:38AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > +static u64 at91_ohci_dma_mask = DMA_BIT_MASK(32);
> > +
> > +static int __devinit ohci_at91_of_init(struct platform_device *pdev)
> > +{
> > +	struct device_node *np = pdev->dev.of_node;
> > +	int i, ret, gpio;
> > +	enum of_gpio_flags flags;
> > +	struct at91_usbh_data	*pdata;
> > +	u32 ports;
> > +
> > +	if (!np)
> > +		return 0;
> > +
> > +	/* Right now device-tree probed devices don't get dma_mask set.
> > +	 * Since shared usb code relies on it, set it here for now.
> > +	 * Once we have dma capability bindings this can go away.
> > +	 */
> > +	if (!pdev->dev.dma_mask)
> > +		pdev->dev.dma_mask = &at91_ohci_dma_mask;
> 
> That sounds like a rather big omission from DT - what's happening to
> address this (before we end up with lots of drivers with this).  Pretty
> much any device which does DMA needs both this and the coherent DMA mask
> set properly.
> 
> We really don't want this kind of workaround scattered in every driver
> which has been converted to DT.
Tegra do it also
I do yet found a good generic way in DT

Today only usb need I do plan to drop it for 3.5 can we have for 3.4

Best Regards,
J.


From mina86 at mina86.com  Wed Mar  7 05:48:24 2012
From: mina86 at mina86.com (Michal Nazarewicz)
Date: Wed, 07 Mar 2012 11:48:24 +0100
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <4F56E0AC.8070501@gmail.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com>
Message-ID: <op.wasqyyok3l0zgt@mpn-glaptop>

> On 03/07/2012 11:14 AM, Barry Song wrote:
>> Any write request to /dev/cma_test will let the module to allocate memory from
>> CMA, for example:
>>
>> 1st time
>> $ echo 1024>  /dev/cma_test
>> will require cma_test to request 1MB(1024KB)
>> 2nd time
>> $ echo 2048>  /dev/cma_test
>> will require cma_test to request 2MB(2048KB)
>>
>> Any read request to /dev/cma_test will let the module to free the 1st valid
>> memory from CMA, for example:
>>
>> 1st time
>> $ cat /dev/cma_test
>> will require cma_test to free the 1MB allocated in the first write request
>> 2nd time
>> $ cat /dev/cma_test
>> will require cma_test to free the 2MB allocated in the second write request

On Wed, 07 Mar 2012 05:14:36 +0100, Cong Wang <xiyou.wangcong at gmail.com> wrote:
> Any reason why using /dev not /proc or /sys?

Because /proc is for processes and /sys is for stable, documented APIs.

If anything, debugfs might make some sense, but since the module needs struct
device anyway, it can just register a misc device, which is simpler and does
not require debugfs to be compiled.

-- 
Best regards,                                         _     _
.o. | Liege of Serenely Enlightened Majesty of      o' \,=./ `o
..o | Computer Science,  Micha? ?mina86? Nazarewicz    (o o)
ooo +----<email/xmpp: mpn at google.com>--------------ooO--(_)--Ooo--


From 21cnbao at gmail.com  Wed Mar  7 05:55:46 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 7 Mar 2012 18:55:46 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <op.wasqyyok3l0zgt@mpn-glaptop>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <4F56E0AC.8070501@gmail.com> <op.wasqyyok3l0zgt@mpn-glaptop>
Message-ID: <CAGsJ_4wb3yMwSVW8ppvMoFe-oJXvNYigttg9S_kAVnDkDhDGHg@mail.gmail.com>

2012/3/7 Michal Nazarewicz <mina86 at mina86.com>:
>> On 03/07/2012 11:14 AM, Barry Song wrote:
>>>
>>> Any write request to /dev/cma_test will let the module to allocate memory
>>> from
>>> CMA, for example:
>>>
>>> 1st time
>>> $ echo 1024> ?/dev/cma_test
>>> will require cma_test to request 1MB(1024KB)
>>> 2nd time
>>> $ echo 2048> ?/dev/cma_test
>>> will require cma_test to request 2MB(2048KB)
>>>
>>> Any read request to /dev/cma_test will let the module to free the 1st
>>> valid
>>> memory from CMA, for example:
>>>
>>> 1st time
>>> $ cat /dev/cma_test
>>> will require cma_test to free the 1MB allocated in the first write
>>> request
>>> 2nd time
>>> $ cat /dev/cma_test
>>> will require cma_test to free the 2MB allocated in the second write
>>> request
>
>
> On Wed, 07 Mar 2012 05:14:36 +0100, Cong Wang <xiyou.wangcong at gmail.com>
> wrote:
>>
>> Any reason why using /dev not /proc or /sys?
>
>
> Because /proc is for processes and /sys is for stable, documented APIs.
>
> If anything, debugfs might make some sense, but since the module needs
> struct
> device anyway, it can just register a misc device, which is simpler and does
> not require debugfs to be compiled.

Michal, thanks for clarification. actually after i sent my mail to
agree Cong's /proc might be ok, then i had more thinking, i came back
to think the original /dev is better since anyway we need to device to
alloc CM.
then we let the device's read/write to handle alloc/free. it is much
more direct for a test module.

>
> --
> Best regards, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _ ? ? _
> .o. | Liege of Serenely Enlightened Majesty of ? ? ?o' \,=./ `o
> ..o | Computer Science, ?Micha? ?mina86? Nazarewicz ? ?(o o)
> ooo +----<email/xmpp: mpn at google.com>--------------ooO--(_)--Ooo--
>

-barry


From mina86 at mina86.com  Wed Mar  7 05:59:03 2012
From: mina86 at mina86.com (Michal Nazarewicz)
Date: Wed, 07 Mar 2012 11:59:03 +0100
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
Message-ID: <op.wasrgptm3l0zgt@mpn-glaptop>

Thanks!  Some minor comments, hopefully last ones:

On Wed, 07 Mar 2012 04:14:58 +0100, Barry Song <Barry.Song at csr.com> wrote:
> +static ssize_t
> +cma_test_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
> +{

[...]

> +	_dev_info(cma_dev, "free: CM virt: %p dma: %p size:%uK\n",

This should read: ?size: %zuK?.  ?z? is the proper modifier to use for size_t type.

> +		alloc->virt, (void *)alloc->dma, alloc->size / SZ_1K);
> +	kfree(alloc);
> +
> +	return 0;
> +}

> +static ssize_t
> +cma_test_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
> +{
> +	struct cma_allocation *alloc;
> +	size_t size;
> +	int ret;
> +
> +	ret = kstrtouint_from_user(buf, count, 0, &size);

kstrtouint_from_user() expects pointer to unsigned int, size_t is not always
unsigned int.  It may be unsigned long.  As such, size should be of type
unsigned long and this line should use kstrtoulong_from_user().

[...]

> +	if (alloc->virt) {
> +		_dev_info(cma_dev, "alloc: virt: %p dma: %p size: %uK\n",
> +			alloc->virt, (void *)alloc->dma, size);

Like previously, this should be ?size: %zuK?.

[...]

> +}

-- 
Best regards,                                         _     _
.o. | Liege of Serenely Enlightened Majesty of      o' \,=./ `o
..o | Computer Science,  Micha? ?mina86? Nazarewicz    (o o)
ooo +----<email/xmpp: mpn at google.com>--------------ooO--(_)--Ooo--


From 21cnbao at gmail.com  Wed Mar  7 06:12:28 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Wed, 7 Mar 2012 19:12:28 +0800
Subject: [PATCH v3] MM: CMA: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <op.wasrgptm3l0zgt@mpn-glaptop>
References: <1331090098-25097-1-git-send-email-Barry.Song@csr.com>
 <op.wasrgptm3l0zgt@mpn-glaptop>
Message-ID: <CAGsJ_4ze8V0g0VKBKnfMeKoo_PBpEk86mB7-=L32A5jB65Qa0A@mail.gmail.com>

2012/3/7 Michal Nazarewicz <mina86 at mina86.com>:
> Thanks! ?Some minor comments, hopefully last ones:
>
>
> On Wed, 07 Mar 2012 04:14:58 +0100, Barry Song <Barry.Song at csr.com> wrote:
>>
>> +static ssize_t
>> +cma_test_read(struct file *file, char __user *buf, size_t count, loff_t
>> *ppos)
>> +{
>
>
> [...]
>
>
>> + ? ? ? _dev_info(cma_dev, "free: CM virt: %p dma: %p size:%uK\n",
>
>
> This should read: ?size: %zuK?. ??z? is the proper modifier to use for
> size_t type.

ok. thanks.

>
>
>> + ? ? ? ? ? ? ? alloc->virt, (void *)alloc->dma, alloc->size / SZ_1K);
>> + ? ? ? kfree(alloc);
>> +
>> + ? ? ? return 0;
>> +}
>
>
>> +static ssize_t
>> +cma_test_write(struct file *file, const char __user *buf, size_t count,
>> loff_t *ppos)
>> +{
>> + ? ? ? struct cma_allocation *alloc;
>> + ? ? ? size_t size;
>> + ? ? ? int ret;
>> +
>> + ? ? ? ret = kstrtouint_from_user(buf, count, 0, &size);
>
>
> kstrtouint_from_user() expects pointer to unsigned int, size_t is not always
> unsigned int. ?It may be unsigned long. ?As such, size should be of type
> unsigned long and this line should use kstrtoulong_from_user().

it comes to a compiling warning, so re-define "size" to unsigned long:

cma_test_write(struct file *file, const char __user *buf, size_t
count, loff_t *ppos)
 {
        struct cma_allocation *alloc;
-       size_t size;
+       unsigned long size;
        int ret;

-       ret = kstrtouint_from_user(buf, count, 0, &size);
+       ret = kstrtoul_from_user(buf, count, 0, &size);
        if (ret)
                return ret;

@@ -86,8 +86,8 @@ cma_test_write(struct file *file, const char __user
*buf, size_t count, loff_t *
                &alloc->dma, GFP_KERNEL);

        if (alloc->virt) {
-               _dev_info(cma_dev, "alloc: virt: %p dma: %p size: %uK\n",
-                       alloc->virt, (void *)alloc->dma, size);
+               _dev_info(cma_dev, "alloc: virt: %p dma: %p size: %zuK\n",
+                       alloc->virt, (void *)alloc->dma, alloc->size / SZ_1K);

                spin_lock(&cma_lock);
                list_add_tail(&alloc->list, &cma_allocations);

>
> [...]
>
>
>> + ? ? ? if (alloc->virt) {
>> + ? ? ? ? ? ? ? _dev_info(cma_dev, "alloc: virt: %p dma: %p size: %uK\n",
>> + ? ? ? ? ? ? ? ? ? ? ? alloc->virt, (void *)alloc->dma, size);
>
>
> Like previously, this should be ?size: %zuK?.
>
> [...]
>
>> +}
>
>
> --
> Best regards, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _ ? ? _
> .o. | Liege of Serenely Enlightened Majesty of ? ? ?o' \,=./ `o
> ..o | Computer Science, ?Micha? ?mina86? Nazarewicz ? ?(o o)
> ooo +----<email/xmpp: mpn at google.com>--------------ooO--(_)--Ooo--

-barry


From tarun.kanti at ti.com  Wed Mar  7 06:15:56 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:45:56 +0530
Subject: [PATCH v3 06/13] gpio/omap: fix trigger type to unsigned
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-7-git-send-email-tarun.kanti@ti.com>

The GPIO trigger parameter is of type unsigned.
enum {
        IRQ_TYPE_NONE           = 0x00000000,
        IRQ_TYPE_EDGE_RISING    = 0x00000001,
        IRQ_TYPE_EDGE_FALLING   = 0x00000002,
        IRQ_TYPE_EDGE_BOTH      = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
        IRQ_TYPE_LEVEL_HIGH     = 0x00000004,
        IRQ_TYPE_LEVEL_LOW      = 0x00000008,
        IRQ_TYPE_LEVEL_MASK     = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
        IRQ_TYPE_SENSE_MASK     = 0x0000000f,

        IRQ_TYPE_PROBE          = 0x00000010,
...
};
Even though gpio_irq_type(struct irq_data *d, unsigned type) has the right type
of parameter, the subsequent called functions set_gpio_triggering() and
set_gpio_trigger() wrongly makes it signed integer. Fix this.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index de5fe8f..bb994db 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -234,7 +234,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
 }
 
 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
-						int trigger)
+						unsigned trigger)
 {
 	void __iomem *base = bank->base;
 	u32 gpio_bit = 1 << gpio;
@@ -316,7 +316,8 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 #endif
 
-static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
+static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
+							unsigned trigger)
 {
 	void __iomem *reg = bank->base;
 	void __iomem *base = bank->base;
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:15:59 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:45:59 +0530
Subject: [PATCH v3 09/13] gpio/omap: remove suspend/resume callbacks
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-10-git-send-email-tarun.kanti@ti.com>

Both omap_gpio_suspend() and omap_gpio_resume() does programming
of wakeup_en register.
_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);

This is redundant in omap_gpio_suspend() because wakeup_en
register automatically gets initialized in _set_gpio_wakeup()
and set_gpio_trigger() while being called either from
chip.irq_set_wake() or chip.irq_set_type().

This is redundant in omap_gpio_resume() because wakeup_en
register is programmed in omap_gpio_restore_context() called
which is called from runtime resume callback.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 drivers/gpio/gpio-omap.c |   47 ----------------------------------------------
 1 files changed, 0 insertions(+), 47 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 186ce92..8b4a7ba 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1132,50 +1132,6 @@ err_exit:
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
 
-#if defined(CONFIG_PM_SLEEP)
-static int omap_gpio_suspend(struct device *dev)
-{
-	struct platform_device *pdev = to_platform_device(dev);
-	struct gpio_bank *bank = platform_get_drvdata(pdev);
-	void __iomem *base = bank->base;
-	unsigned long flags;
-
-	if (!bank->mod_usage || !bank->loses_context)
-		return 0;
-
-	if (!bank->regs->wkup_en || !bank->context.wake_en)
-		return 0;
-
-	spin_lock_irqsave(&bank->lock, flags);
-	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
-	_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
-	spin_unlock_irqrestore(&bank->lock, flags);
-
-	return 0;
-}
-
-static int omap_gpio_resume(struct device *dev)
-{
-	struct platform_device *pdev = to_platform_device(dev);
-	struct gpio_bank *bank = platform_get_drvdata(pdev);
-	void __iomem *base = bank->base;
-	unsigned long flags;
-
-	if (!bank->mod_usage || !bank->loses_context)
-		return 0;
-
-	if (!bank->regs->wkup_en || !bank->context.wake_en)
-		return 0;
-
-	spin_lock_irqsave(&bank->lock, flags);
-	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
-	_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
-	spin_unlock_irqrestore(&bank->lock, flags);
-
-	return 0;
-}
-#endif /* CONFIG_PM_SLEEP */
-
 #if defined(CONFIG_PM_RUNTIME)
 static void omap_gpio_restore_context(struct gpio_bank *bank);
 
@@ -1407,14 +1363,11 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)
 }
 #endif /* CONFIG_PM_RUNTIME */
 #else
-#define omap_gpio_suspend NULL
-#define omap_gpio_resume NULL
 #define omap_gpio_runtime_suspend NULL
 #define omap_gpio_runtime_resume NULL
 #endif
 
 static const struct dev_pm_ops gpio_pm_ops = {
-	SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
 	SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
 									NULL)
 };
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:15:53 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:45:53 +0530
Subject: [PATCH v3 03/13] gpio/omap: remove suspend_wakeup field from struct
 gpio_bank
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-4-git-send-email-tarun.kanti@ti.com>

Since we already have bank->context.wake_en to keep track
of gpios which are wakeup enabled, there is no need to have
this field any more.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |   13 ++++++-------
 1 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 895df7f..14c61e2 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -54,7 +54,6 @@ struct gpio_bank {
 	void __iomem *base;
 	u16 irq;
 	u16 virtual_irq_start;
-	u32 suspend_wakeup;
 	u32 saved_wakeup;
 	u32 non_wakeup_gpios;
 	u32 enabled_non_wakeup_gpios;
@@ -500,11 +499,11 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
 
 	spin_lock_irqsave(&bank->lock, flags);
 	if (enable)
-		bank->suspend_wakeup |= gpio_bit;
+		bank->context.wake_en |= gpio_bit;
 	else
-		bank->suspend_wakeup &= ~gpio_bit;
+		bank->context.wake_en &= ~gpio_bit;
 
-	__raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en);
+	__raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
@@ -776,7 +775,7 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
 
 	spin_lock_irqsave(&bank->lock, flags);
 	bank->saved_wakeup = __raw_readl(mask_reg);
-	__raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
+	__raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
@@ -1150,7 +1149,7 @@ static int omap_gpio_suspend(struct device *dev)
 	if (!bank->mod_usage || !bank->loses_context)
 		return 0;
 
-	if (!bank->regs->wkup_en || !bank->suspend_wakeup)
+	if (!bank->regs->wkup_en || !bank->context.wake_en)
 		return 0;
 
 	wakeup_enable = bank->base + bank->regs->wkup_en;
@@ -1158,7 +1157,7 @@ static int omap_gpio_suspend(struct device *dev)
 	spin_lock_irqsave(&bank->lock, flags);
 	bank->saved_wakeup = __raw_readl(wakeup_enable);
 	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
-	_gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
+	_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:16:02 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:46:02 +0530
Subject: [PATCH v3 12/13] gpio/omap: fix incorrect context restore logic in
 omap_gpio_runtime_resume
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-13-git-send-email-tarun.kanti@ti.com>

In omap_gpio_runtime_resume() the context restore should be independent
of bank->enabled_non_wakeup_gpios. This was preventing context restore
of GPIO lines which are not wakeup enabled.

Reported-by: Govindraj Raja <govindraj.raja at ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 drivers/gpio/gpio-omap.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 2e8e476..ccfbae0 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1227,7 +1227,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
 	__raw_writel(bank->context.risingdetect,
 		     bank->base + bank->regs->risingdetect);
 
-	if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
+	if (!bank->workaround_enabled) {
 		spin_unlock_irqrestore(&bank->lock, flags);
 		return 0;
 	}
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:16:03 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:46:03 +0530
Subject: [PATCH v3 13/13] gpio/omap: fix incorrect update to context.irqenable1
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-14-git-send-email-tarun.kanti@ti.com>

In _enable_gpio_irqbank() when bank->regs->set_irqenable is valid,
gpio_mask can be directly set by writing to set_irqenable register
without overwriting current value. In order to ensure the same is
stored in context.irqenable1, we must read from regs->irqenable
instead of overwriting it with gpio_mask.
The overwriting makes sense only in the second case where irqenable
is explicitly read and updated with new gpio_mask before writing it
back. However, for consistency reading regs->irqenable into the
bank->context.irqenable1 takes care of both the scenarios.

        if (bank->regs->set_irqenable) {
                reg += bank->regs->set_irqenable;
                l = gpio_mask;
        } else {
                reg += bank->regs->irqenable;
                l = __raw_readl(reg);
                if (bank->regs->irqenable_inv)
                        l &= ~gpio_mask;
                else
                        l |= gpio_mask;
        }

Make the same change for _disable_gpio_irqbank().

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 drivers/gpio/gpio-omap.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index ccfbae0..8b0d3ab 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -453,7 +453,8 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 	}
 
 	__raw_writel(l, reg);
-	bank->context.irqenable1 = l;
+	bank->context.irqenable1 =
+			__raw_readl(bank->base + bank->regs->irqenable);
 }
 
 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
@@ -474,7 +475,8 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 	}
 
 	__raw_writel(l, reg);
-	bank->context.irqenable1 = l;
+	bank->context.irqenable1 =
+			__raw_readl(bank->base + bank->regs->irqenable);
 }
 
 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:15:52 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:45:52 +0530
Subject: [PATCH v3 02/13] gpio/omap: fix wakeup_en register update in
 _set_gpio_wakeup()
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-3-git-send-email-tarun.kanti@ti.com>

There are two ways through which wakeup_en register can be programmed
using gpiolib APIs as shown below. It is seen that in the second case
in _set_gpio_wakeup(), even though bank->suspend_wakeup is updated
correctly, its value is not programmed in wakeup_en register. Fix this.

chip.irq_set_type()->gpio_irq_type()->_set_gpio_triggering()->set_gpio_trigger()
chip.irq_set_wake()->gpio_wake_enable()->_set_gpio_wakeup()

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 drivers/gpio/gpio-omap.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index c9369d2..895df7f 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -504,6 +504,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
 	else
 		bank->suspend_wakeup &= ~gpio_bit;
 
+	__raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:15:57 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:45:57 +0530
Subject: [PATCH v3 07/13] gpio/omap: fix _set_gpio_irqenable implementation
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-8-git-send-email-tarun.kanti@ti.com>

This function should be capable of both enabling and disabling interrupts
based upon the *enable* parameter. Right now the function only enables
the interrupt and *enable* is not used at all. So add the interrupt
disable capability also using the parameter.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index bb994db..19f8f44 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -475,7 +475,10 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 
 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
 {
-	_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
+	if (enable)
+		_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
+	else
+		_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
 }
 
 /*
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:16:00 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:46:00 +0530
Subject: [PATCH v3 10/13] gpio/omap: fix missing dataout context save in
 _set_gpio_dataout_reg
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-11-git-send-email-tarun.kanti@ti.com>

There are two functions, _set_gpio_dataout_reg() and _set_gpio_dataout_mask()
which writes to dataout register and the dataout context must be saved.
It is missing in the first function, _set_gpio_dataout_reg(). Fix this.

Reported-by: Govindraj Raja <govindraj.raja at ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 drivers/gpio/gpio-omap.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 8b4a7ba..04c2677 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -115,6 +115,7 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
 		reg += bank->regs->clr_dataout;
 
 	__raw_writel(l, reg);
+	bank->context.dataout = l;
 }
 
 /* set data out value using mask register */
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:16:01 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:46:01 +0530
Subject: [PATCH v3 11/13] gpio/omap: fix dataout register overwrite in
 _set_gpio_dataout_*
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-12-git-send-email-tarun.kanti@ti.com>

In the existing _set_gpio_dataout_*() implementation, the dataout
register is overwritten every time the function is called. This is
not intended behavior because that would end up one user of a GPIO
line overwriting what is written by another. Fix this so that previous
value is always preserved until explicitly changed by respective
user/driver of the GPIO line.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 drivers/gpio/gpio-omap.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 04c2677..2e8e476 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -114,6 +114,7 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
 	else
 		reg += bank->regs->clr_dataout;
 
+	l |= __raw_readl(bank->base + bank->regs->set_dataout);
 	__raw_writel(l, reg);
 	bank->context.dataout = l;
 }
@@ -130,6 +131,8 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
 		l |= gpio_bit;
 	else
 		l &= ~gpio_bit;
+
+	l |= __raw_readl(bank->base + bank->regs->set_dataout);
 	__raw_writel(l, reg);
 	bank->context.dataout = l;
 }
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:15:51 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:45:51 +0530
Subject: [PATCH v3 01/13] gpio/omap: remove saved_fallingdetect,
 saved_risingdetect fields
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-2-git-send-email-tarun.kanti@ti.com>

Since we already have context.fallingdetect and context.risingdetect
there is no more need to have these additional fields. Also, getting
rid of extra reads associated with them.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |   19 ++++++++-----------
 1 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 752ae9b..c9369d2 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -60,8 +60,6 @@ struct gpio_bank {
 	u32 enabled_non_wakeup_gpios;
 	struct gpio_regs context;
 	u32 saved_datain;
-	u32 saved_fallingdetect;
-	u32 saved_risingdetect;
 	u32 level_mask;
 	u32 toggle_mask;
 	spinlock_t lock;
@@ -1234,11 +1232,9 @@ static int omap_gpio_runtime_suspend(struct device *dev)
 
 	bank->saved_datain = __raw_readl(bank->base +
 						bank->regs->datain);
-	l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
-	l2 = __raw_readl(bank->base + bank->regs->risingdetect);
+	l1 = bank->context.fallingdetect;
+	l2 = bank->context.risingdetect;
 
-	bank->saved_fallingdetect = l1;
-	bank->saved_risingdetect = l2;
 	l1 &= ~bank->enabled_non_wakeup_gpios;
 	l2 &= ~bank->enabled_non_wakeup_gpios;
 
@@ -1297,9 +1293,9 @@ static int omap_gpio_runtime_resume(struct device *dev)
 		}
 	}
 
-	__raw_writel(bank->saved_fallingdetect,
+	__raw_writel(bank->context.fallingdetect,
 			bank->base + bank->regs->fallingdetect);
-	__raw_writel(bank->saved_risingdetect,
+	__raw_writel(bank->context.risingdetect,
 			bank->base + bank->regs->risingdetect);
 	l = __raw_readl(bank->base + bank->regs->datain);
 
@@ -1316,14 +1312,15 @@ static int omap_gpio_runtime_resume(struct device *dev)
 	 * No need to generate IRQs for the rising edge for gpio IRQs
 	 * configured with falling edge only; and vice versa.
 	 */
-	gen0 = l & bank->saved_fallingdetect;
+	gen0 = l & bank->context.fallingdetect;
 	gen0 &= bank->saved_datain;
 
-	gen1 = l & bank->saved_risingdetect;
+	gen1 = l & bank->context.risingdetect;
 	gen1 &= ~(bank->saved_datain);
 
 	/* FIXME: Consider GPIO IRQs with level detections properly! */
-	gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect));
+	gen = l & (~(bank->context.fallingdetect) &
+					 ~(bank->context.risingdetect));
 	/* Consider all GPIO IRQs needed to be updated */
 	gen |= gen0 | gen1;
 
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:15:50 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:45:50 +0530
Subject: [PATCH v3 00/13] gpio/omap: Some more driver cleanup and fixes 
Message-ID: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>

The cleanup is mostly getting rid of redundant fields in struct gpio_bank{}
as we already have them as part of bank->context now. Also, remove un-used
variable from gpio_irq_handler.

The fixes include correction of _set_gpio_irqenable() implementation,
missing wakeup_en register update in set_gpio_wakeup(), type mismatch
of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
register update in set_gpio_dataout_() and few corrections in context
save logic.

It is baselined on top of Kevin's following series:
gpio/omap: cleanup and runtime PM conversion for v3.4
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/gpio/runtime-pm-cleanup

Series is available here for reference:
git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_further_cleanup_fixes

Power Test: Off-mode and Retention on OMAP3430 (Suspend and Idle paths).
Functional Test: OMAP2430, OMAP3430SDP, ZOOM3, OMAP4430, OMAP4-BLAZE

v3:
- Added 4 more additional patches to the previous series
  which are all bug fixes.

v2:
- Added a new patch to update wakeup_en register in _set_gpio_wakeup()
 in addition to updating bank->context.wake_en.

- Added a new patch to remove redundant decoding of gpio offset in
 gpio_get(), _get_gpio_datain() and _get_gpio_dataout().

- Added a new patch to remove suspend/resume callbacks because the
 operations performed with the callbacks are redundant.

Tarun Kanti DebBarma (13):
  gpio/omap: remove saved_fallingdetect, saved_risingdetect fields
  gpio/omap: fix wakeup_en register update in _set_gpio_wakeup()
  gpio/omap: remove suspend_wakeup field from struct gpio_bank
  gpio/omap: remove saved_wakeup field from struct gpio_bank
  gpio/omap: get rid of retrigger variable in gpio_irq_handler
  gpio/omap: fix trigger type to unsigned
  gpio/omap: fix _set_gpio_irqenable implementation
  gpio/omap: remove redundant decoding of gpio offset
  gpio/omap: remove suspend/resume callbacks
  gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg
  gpio/omap: fix dataout register overwrite in _set_gpio_dataout_*
  gpio/omap: fix incorrect context restore logic in omap_gpio_runtime_resume
  gpio/omap: fix incorrect update to context.irqenable1

 drivers/gpio/gpio-omap.c |  125 +++++++++++++--------------------------------
 1 files changed, 36 insertions(+), 89 deletions(-)



From tarun.kanti at ti.com  Wed Mar  7 06:15:55 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:45:55 +0530
Subject: [PATCH v3 05/13] gpio/omap: get rid of retrigger variable in
 gpio_irq_handler
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-6-git-send-email-tarun.kanti@ti.com>

This local variable is just assigned zero and then OR'ed
with isr. It does not appear to serve any purpose and so
removing it.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 3765654..de5fe8f 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -626,7 +626,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 	u32 isr;
 	unsigned int gpio_irq, gpio_index;
 	struct gpio_bank *bank;
-	u32 retrigger = 0;
 	int unmasked = 0;
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 
@@ -663,8 +662,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 			chained_irq_exit(chip, desc);
 		}
 
-		isr |= retrigger;
-		retrigger = 0;
 		if (!isr)
 			break;
 
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:15:54 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:45:54 +0530
Subject: [PATCH v3 04/13] gpio/omap: remove saved_wakeup field from struct
 gpio_bank
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-5-git-send-email-tarun.kanti@ti.com>

There is no more need to have saved_wakeup because bank->context.wake_en
already holds that value. So getting rid of read/write operation associated
with this field.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |   12 +++---------
 1 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 14c61e2..3765654 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -54,7 +54,6 @@ struct gpio_bank {
 	void __iomem *base;
 	u16 irq;
 	u16 virtual_irq_start;
-	u32 saved_wakeup;
 	u32 non_wakeup_gpios;
 	u32 enabled_non_wakeup_gpios;
 	struct gpio_regs context;
@@ -774,7 +773,6 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
 	unsigned long		flags;
 
 	spin_lock_irqsave(&bank->lock, flags);
-	bank->saved_wakeup = __raw_readl(mask_reg);
 	__raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
@@ -790,7 +788,7 @@ static int omap_mpuio_resume_noirq(struct device *dev)
 	unsigned long		flags;
 
 	spin_lock_irqsave(&bank->lock, flags);
-	__raw_writel(bank->saved_wakeup, mask_reg);
+	__raw_writel(bank->context.wake_en, mask_reg);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
@@ -1143,7 +1141,6 @@ static int omap_gpio_suspend(struct device *dev)
 	struct platform_device *pdev = to_platform_device(dev);
 	struct gpio_bank *bank = platform_get_drvdata(pdev);
 	void __iomem *base = bank->base;
-	void __iomem *wakeup_enable;
 	unsigned long flags;
 
 	if (!bank->mod_usage || !bank->loses_context)
@@ -1152,10 +1149,7 @@ static int omap_gpio_suspend(struct device *dev)
 	if (!bank->regs->wkup_en || !bank->context.wake_en)
 		return 0;
 
-	wakeup_enable = bank->base + bank->regs->wkup_en;
-
 	spin_lock_irqsave(&bank->lock, flags);
-	bank->saved_wakeup = __raw_readl(wakeup_enable);
 	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
 	_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
 	spin_unlock_irqrestore(&bank->lock, flags);
@@ -1173,12 +1167,12 @@ static int omap_gpio_resume(struct device *dev)
 	if (!bank->mod_usage || !bank->loses_context)
 		return 0;
 
-	if (!bank->regs->wkup_en || !bank->saved_wakeup)
+	if (!bank->regs->wkup_en || !bank->context.wake_en)
 		return 0;
 
 	spin_lock_irqsave(&bank->lock, flags);
 	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
-	_gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
+	_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
-- 
1.7.0.4



From tarun.kanti at ti.com  Wed Mar  7 06:15:58 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Wed, 7 Mar 2012 16:45:58 +0530
Subject: [PATCH v3 08/13] gpio/omap: remove redundant decoding of gpio offset
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331118963-26364-9-git-send-email-tarun.kanti@ti.com>

In gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of
un-necessary operation to compute gpio mask. The gpio offset passed
to gpio_get() is sufficient to do that.

Here is Russell's original comment:
Can someone explain to me this:
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))

static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
       void __iomem *reg = bank->base + bank->regs->datain;

       return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
}

static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
       struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
       void __iomem *reg = bank->base;
       int gpio = chip->base + offset;
       u32 mask = GPIO_BIT(bank, gpio);

       if (gpio_is_input(bank, mask))
               return _get_gpio_datain(bank, gpio);
       else
               return _get_gpio_dataout(bank, gpio);
}

Given that bank->width on OMAP is either 32 or 16, and GPIO numbers for
any GPIO chip are always aligned to 32 or 16, why does this code bother
adding the chips base gpio number and then modulo the width?

Surely this means if - for argument sake - you registered a GPIO chip
with 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0
bit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be
chip 1 bit 0..7.

However, if you registered a GPIO chip with 16 lines first, it would
mean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be
chip 1 bit 0..15.

Surely this kind of behaviour is not intended?

Is there a reason why the bitmask can't just be (1 << offset) where
offset is passed into these functions as GPIO number - chip->base ?

Reported-by: Russell King - ARM Linux <linux at arm.linux.org.uk>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 drivers/gpio/gpio-omap.c |   18 +++++++-----------
 1 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 19f8f44..186ce92 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -133,18 +133,18 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
 	bank->context.dataout = l;
 }
 
-static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
+static int _get_gpio_datain(struct gpio_bank *bank, int offset)
 {
 	void __iomem *reg = bank->base + bank->regs->datain;
 
-	return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
+	return (__raw_readl(reg) & (1 << offset)) != 0;
 }
 
-static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
+static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
 {
 	void __iomem *reg = bank->base + bank->regs->dataout;
 
-	return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
+	return (__raw_readl(reg) & (1 << offset)) != 0;
 }
 
 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
@@ -849,19 +849,15 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
 static int gpio_get(struct gpio_chip *chip, unsigned offset)
 {
 	struct gpio_bank *bank;
-	void __iomem *reg;
-	int gpio;
 	u32 mask;
 
-	gpio = chip->base + offset;
 	bank = container_of(chip, struct gpio_bank, chip);
-	reg = bank->base;
-	mask = GPIO_BIT(bank, gpio);
+	mask = (1 << offset);
 
 	if (gpio_is_input(bank, mask))
-		return _get_gpio_datain(bank, gpio);
+		return _get_gpio_datain(bank, offset);
 	else
-		return _get_gpio_dataout(bank, gpio);
+		return _get_gpio_dataout(bank, offset);
 }
 
 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
-- 
1.7.0.4



From srinidhi.kasagar at stericsson.com  Wed Mar  7 06:17:12 2012
From: srinidhi.kasagar at stericsson.com (Srinidhi Kasagar)
Date: Wed, 7 Mar 2012 16:47:12 +0530
Subject: [PATCH 14/15] watchdog/mpcore_wdt: Add clock framework support
In-Reply-To: <9ec7141baa4b1c1a0503893749e7ce0e19bb5029.1331115752.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <9ec7141baa4b1c1a0503893749e7ce0e19bb5029.1331115752.git.viresh.kumar@st.com>
Message-ID: <20120307111711.GA31348@bnru02>

On Wed, Mar 07, 2012 at 11:27:55 +0100, Viresh KUMAR wrote:
> This patch adds in clk framework support for wdt driver. If clk_get fails for
> some platform, then we continue without clk_* API's.
> 
> Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
> ---
>  drivers/watchdog/mpcore_wdt.c |   71 ++++++++++++++++++++++++++++++++++++-----
>  1 files changed, 63 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
> index ebd964a..9747193 100644
> --- a/drivers/watchdog/mpcore_wdt.c
> +++ b/drivers/watchdog/mpcore_wdt.c
> @@ -17,6 +17,7 @@
>   *
>   * (c) Copyright 1995    Alan Cox <alan at lxorguk.ukuu.org.uk>
>   */

[..]

> @@ -350,6 +368,28 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
>  		}
>  	}
>  
> +	wdt->clk = clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(wdt->clk)) {
> +		dev_warn(&pdev->dev, "Clock not found\n");
> +		wdt->clk = NULL;
> +	}
> +
> +	if (wdt->clk) {
> +		ret = clk_enable(wdt->clk);
> +		if (ret) {
> +			dev_err(&pdev->dev, "Clock enable failed\n");
> +			goto err_put_clk;
> +		}
> +	}
> +
> +	wdt->boot_status = (readl(wdt->base + TWD_WDOG_RESETSTAT) &
> +			TWD_WDOG_RESETSTAT_MASK) ? WDIOF_CARDRESET : 0;
> +

I see that patch 12/15 does this, why are you doing it here again in clock patch?

> +	mpcore_wdt_stop(wdt);
> +
> +	if (wdt->clk)
> +		clk_disable(wdt->clk);
> +
>  	/*
>  	 * Check that the margin value is within it's range;
>  	 * if not reset to the default
> @@ -368,25 +408,32 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
>  		dev_printk(KERN_ERR, wdt->dev,
>  			"cannot register miscdev on minor=%d (err=%d)\n",
>  							WATCHDOG_MINOR, ret);
> -		return ret;
> +		goto err_put_clk;
>  	}
>  
> -	wdt->boot_status = (readl(wdt->base + TWD_WDOG_RESETSTAT) &
> -			TWD_WDOG_RESETSTAT_MASK) ? WDIOF_CARDRESET : 0;
> -

oh, you delete this stuff here again.

something messy in patch creation?

Srinidhi


From kgene.kim at samsung.com  Wed Mar  7 06:17:44 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 07 Mar 2012 03:17:44 -0800
Subject: [PATCH 0/4] Use clock functions also for clk_h and clk_p on
 S3C2443/2416
In-Reply-To: <201203032214.36820.heiko@sntech.de>
References: <201203032214.36820.heiko@sntech.de>
Message-ID: <4F5743D8.702@samsung.com>

On 03/03/12 13:14, Heiko St?bner wrote:
> This series modifies the clock init in common-s3c2443 to use the
> struct clk operations also for clk_p and clk_h whose values were until
> now set statically in s3c24xx_setup_clocks - a function more suited to
> the earlier S3C-SoCs.
>
> In the end it makes the code (hopefully) easier to read, as strange
> divisions through register values get replaced by simply clk_get_rate
> calls.
>
> To apply on top of the current s3c24xx consolidation.
>
OK, applied.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Wed Mar  7 06:18:07 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 07 Mar 2012 03:18:07 -0800
Subject: [PATCH 0/3] S3C24XX: Enable DMA on S3C2416 by sharing S3C2443-DMA
In-Reply-To: <201203041842.35420.heiko@sntech.de>
References: <201203041842.35420.heiko@sntech.de>
Message-ID: <4F5743EF.20603@samsung.com>

On 03/04/12 09:42, Heiko St?bner wrote:
> The S3C2416/2450 contains the same DMA register layout as the S3C2443.
> Therefore it can simply share this dma selection definition.
>
> As we use the S3C2443_DMA the S3C2416_DMA is no longer necessary. The
> third patch removes this remnant of the S3C24XX merge.
>
> The whole series was made on top of the recent S3C24XX merge.
>
Good, applied.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Wed Mar  7 06:18:16 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 07 Mar 2012 03:18:16 -0800
Subject: [PATCH 0/4] S3C24XX: Another move of code to the new mach
 directory
In-Reply-To: <201203061057.15815.heiko@sntech.de>
References: <201203061057.15815.heiko@sntech.de>
Message-ID: <4F5743F8.4040001@samsung.com>

On 03/06/12 01:57, Heiko St?bner wrote:
> This series contains the easy moves of common code for the SMDKs,
> Simtec boards and device setup from plat-s3c24xx to mach-s3c24xx.
>
> It also contains an extra patch to keep the Simtec code more together.
>
> Changes to the Kconfig and Makefile will probably conflict with the
> S3C2416-SPI series posted sunday, but this is ok, as the SPI series
> will probably have to wait for 3.5 anyway and can be redone then.
>
OK, I agree so applied this whole series.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From linux at arm.linux.org.uk  Wed Mar  7 06:18:33 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 11:18:33 +0000
Subject: [PATCH 14/15] watchdog/mpcore_wdt: Add clock framework support
In-Reply-To: <9ec7141baa4b1c1a0503893749e7ce0e19bb5029.1331115752.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <9ec7141baa4b1c1a0503893749e7ce0e19bb5029.1331115752.git.viresh.kumar@st.com>
Message-ID: <20120307111833.GQ17370@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 03:57:55PM +0530, Viresh Kumar wrote:
> @@ -156,10 +159,22 @@ static int mpcore_wdt_open(struct inode *inode, struct file *file)
>  
>  	file->private_data = wdt;
>  
> +	if (wdt->clk) {

	if (!IS_ERR(wdt->clk)) {

> +		ret = clk_enable(wdt->clk);

What about preparing the clock?

> +		if (ret) {
> +			dev_err(wdt->dev, "clock enable fail");
> +			goto err;
> +		}
> +	}
> +
>  	/* Activate timer */
>  	mpcore_wdt_start(wdt);
>  
>  	return nonseekable_open(inode, file);
> +
> +err:
> +	clear_bit(0, &wdt->timer_alive);
> +	return ret;
>  }
>  
>  static int mpcore_wdt_release(struct inode *inode, struct file *file)
> @@ -169,9 +184,12 @@ static int mpcore_wdt_release(struct inode *inode, struct file *file)
>  	/*
>  	 * Shut off the timer. Lock it in if it's a module and we set nowayout
>  	 */
> -	if (wdt->expect_close == 42)
> +	if (wdt->expect_close == 42) {
>  		mpcore_wdt_stop(wdt);
> -	else {
> +
> +		if (wdt->clk)

		if (!IS_ERR(wdt->clk))

> +			clk_disable(wdt->clk);

What about unpreparing the clock?

> +	} else {
>  		dev_printk(KERN_CRIT, wdt->dev,
>  				"unexpected close, not stopping watchdog!\n");
>  		mpcore_wdt_keepalive(wdt);
> @@ -350,6 +368,28 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
>  		}
>  	}
>  
> +	wdt->clk = clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(wdt->clk)) {
> +		dev_warn(&pdev->dev, "Clock not found\n");
> +		wdt->clk = NULL;

Remove this line.

> +	}
> +
> +	if (wdt->clk) {

	if (!IS_ERR(wdt->clk)) {

> +		ret = clk_enable(wdt->clk);

What about preparing the clock?

> +		if (ret) {
> +			dev_err(&pdev->dev, "Clock enable failed\n");
> +			goto err_put_clk;
> +		}
> +	}
> +
> +	wdt->boot_status = (readl(wdt->base + TWD_WDOG_RESETSTAT) &
> +			TWD_WDOG_RESETSTAT_MASK) ? WDIOF_CARDRESET : 0;
> +
> +	mpcore_wdt_stop(wdt);
> +
> +	if (wdt->clk)
> +		clk_disable(wdt->clk);

Same two comments...

> +
>  	/*
>  	 * Check that the margin value is within it's range;
>  	 * if not reset to the default
> @@ -368,25 +408,32 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
>  		dev_printk(KERN_ERR, wdt->dev,
>  			"cannot register miscdev on minor=%d (err=%d)\n",
>  							WATCHDOG_MINOR, ret);
> -		return ret;
> +		goto err_put_clk;
>  	}
>  
> -	wdt->boot_status = (readl(wdt->base + TWD_WDOG_RESETSTAT) &
> -			TWD_WDOG_RESETSTAT_MASK) ? WDIOF_CARDRESET : 0;
> -
> -	mpcore_wdt_stop(wdt);
>  	platform_set_drvdata(pdev, wdt);
>  	mpcore_wdt_pdev = pdev;
>  
>  	return 0;
> +
> +err_put_clk:
> +	if (wdt->clk)
> +		clk_put(wdt->clk);
> +
> +	return ret;
>  }
>  
>  static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
>  {
> +	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
> +
>  	platform_set_drvdata(pdev, NULL);
>  
>  	misc_deregister(&mpcore_wdt_miscdev);
>  
> +	if (wdt->clk)
> +		clk_put(wdt->clk);

Same comments.

> +
>  	mpcore_wdt_pdev = NULL;
>  
>  	return 0;
> @@ -399,6 +446,9 @@ static int mpcore_wdt_suspend(struct device *dev)
>  
>  	if (test_bit(0, &wdt->timer_alive))
>  		mpcore_wdt_stop(wdt);		/* Turn the WDT off */
> +
> +	if (wdt->clk)
> +		clk_disable(wdt->clk);

Same comments...  And what if the watchdog is not open?  Doesn't this
disable an already disabled clock?

>  	return 0;
>  }
>  
> @@ -407,8 +457,13 @@ static int mpcore_wdt_resume(struct device *dev)
>  	struct mpcore_wdt *wdt = dev_get_drvdata(dev);
>  
>  	/* re-activate timer */
> -	if (test_bit(0, &wdt->timer_alive))
> +	if (test_bit(0, &wdt->timer_alive)) {
> +		if (wdt->clk)
> +			clk_enable(wdt->clk);

Same two comments.

> +
>  		mpcore_wdt_start(wdt);
> +	}
> +
>  	return 0;
>  }
>  #endif
> -- 
> 1.7.8.110.g4cb5d
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From linux at arm.linux.org.uk  Wed Mar  7 06:22:19 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 11:22:19 +0000
Subject: [PATCH] ARM: S3C24XX: Fix Section mismatch
In-Reply-To: <1331116612-14491-1-git-send-email-kgene.kim@samsung.com>
References: <1331116612-14491-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <20120307112219.GR17370@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 02:36:52AM -0800, Kukjin Kim wrote:
> WARNING: arch/arm/mach-s3c24xx/built-in.o(.data+0xf44): Section mismatch in reference
> from the variable s3c2416_irq_interface to the function .init.text:s3c2416_irq_add()
> The variable s3c2416_irq_interface references
> the function __init s3c2416_irq_add()
> If the reference is valid then annotate the
> variable with __init* or __refdata (see linux/init.h) or name the variable:
> *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
> 
> WARNING: arch/arm/mach-s3c24xx/built-in.o(.data+0x1b80): Section mismatch in reference
> from the variable s3c2443_irq_interface to the function .init.text:s3c2443_irq_add()
> The variable s3c2443_irq_interface references
> the function __init s3c2443_irq_add()
> If the reference is valid then annotate the
> variable with __init* or __refdata (see linux/init.h) or name the variable:
> *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

> diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
> index b8a5836..59b7632 100644
> --- a/arch/arm/mach-s3c24xx/irq-s3c2416.c
> +++ b/arch/arm/mach-s3c24xx/irq-s3c2416.c
> @@ -310,7 +310,7 @@ static int __init s3c2416_irq_add(struct device *dev)
>  	return 0;
>  }
>  
> -static struct subsys_interface s3c2416_irq_interface = {
> +static struct subsys_interface s3c2416_irq_interface __initdata = {
>  	.name		= "s3c2416_irq",
>  	.subsys		= &s3c2416_subsys,
>  	.add_dev	= s3c2416_irq_add,
> diff --git a/arch/arm/mach-s3c24xx/irq-s3c2443.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c
> index 35e4ff2..439f186 100644
> --- a/arch/arm/mach-s3c24xx/irq-s3c2443.c
> +++ b/arch/arm/mach-s3c24xx/irq-s3c2443.c
> @@ -265,7 +265,7 @@ static int __init s3c2443_irq_add(struct device *dev)
>  	return 0;
>  }
>  
> -static struct subsys_interface s3c2443_irq_interface = {
> +static struct subsys_interface s3c2443_irq_interface __initdata = {
>  	.name		= "s3c2443_irq",
>  	.subsys		= &s3c2443_subsys,
>  	.add_dev	= s3c2443_irq_add,

You register these structures with some other bit of code.  That other
bit of code adds these structures to a list. You then mark them as
__initdata, which means they get freed and the memory reused.  That
corrupts the list beneath the other code.

So, clearly, both of these are wrong.


From plagnioj at jcrosoft.com  Wed Mar  7 06:26:15 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 12:26:15 +0100
Subject: [PATCH 1/1] of: add dma-mask binding
Message-ID: <1331119575-6638-1-git-send-email-plagnioj@jcrosoft.com>

This will allow each device to specify its dma-mask
The microblaze architecture hook is keep temporary if no dma-mask is specified
int the DT

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 drivers/of/platform.c |   26 +++++++++++++++++++++++++-
 1 files changed, 25 insertions(+), 1 deletions(-)

diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index cae9477..bb22194 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -121,6 +121,26 @@ void of_device_make_bus_id(struct device *dev)
 	dev_set_name(dev, "%s.%d", node->name, magic - 1);
 }
 
+static u64* of_get_dma_mask(struct device_node *np)
+{
+	const __be32 *prop;
+	int len;
+	u64 *dma_mask;
+
+	prop = of_get_property(np, "dma-mask", &len);
+
+	if (!prop)
+		return NULL;
+
+	dma_mask = kzalloc(sizeof(u64), GFP_KERNEL);
+	if (!dma_mask)
+		return NULL;
+
+	*dma_mask = of_read_number(prop, len / 4);
+
+	return dma_mask;
+}
+
 /**
  * of_device_alloc - Allocate and initialize an of_device
  * @np: device node to assign to device
@@ -161,10 +181,14 @@ struct platform_device *of_device_alloc(struct device_node *np,
 		WARN_ON(of_irq_to_resource_table(np, res, num_irq) != num_irq);
 	}
 
+	dev->dev.dma_mask = of_get_dma_mask(np);
 	dev->dev.of_node = of_node_get(np);
+
 #if defined(CONFIG_MICROBLAZE)
-	dev->dev.dma_mask = &dev->archdata.dma_mask;
+	if (!dev->dev.dma_mask)
+		dev->dev.dma_mask = &dev->archdata.dma_mask;
 #endif
+
 	dev->dev.parent = parent;
 
 	if (bus_id)
-- 
1.7.7



From Barry.Song at csr.com  Wed Mar  7 06:37:39 2012
From: Barry.Song at csr.com (Barry Song)
Date: Wed, 7 Mar 2012 19:37:39 +0800
Subject: [PATCH v4] mm: cma: add a simple kernel module as the helper to test
 CMA
Message-ID: <1331120259-30780-1-git-send-email-Barry.Song@csr.com>

From: Barry Song <Baohua.Song at csr.com>

Any write request to /dev/cma_test will let the module to allocate memory from
CMA, for example:

1st time
$ echo 1024 > /dev/cma_test
will require cma_test to request 1MB(1024KB)
2nd time
$ echo 2048 > /dev/cma_test
will require cma_test to request 2MB(2048KB)

Any read request to /dev/cma_test will let the module to free the 1st valid
memory from CMA, for example:

1st time
$ cat /dev/cma_test
will require cma_test to free the 1MB allocated in the first write request
2nd time
$ cat /dev/cma_test
will require cma_test to free the 2MB allocated in the second write request

Signed-off-by: Barry Song <Baohua.Song at csr.com>
---
 tools/cma/Makefile   |   13 +++++
 tools/cma/cma_test.c |  140 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 153 insertions(+), 0 deletions(-)
 create mode 100644 tools/cma/Makefile
 create mode 100644 tools/cma/cma_test.c

diff --git a/tools/cma/Makefile b/tools/cma/Makefile
new file mode 100644
index 0000000..d15c2c0
--- /dev/null
+++ b/tools/cma/Makefile
@@ -0,0 +1,13 @@
+# Kernel modules
+#
+# To compile for ARM:
+# make ARCH=arm CC=arm-none-linux-gnueabi-gcc
+#
+obj-m	+= cma_test.o
+
+build: kernel_modules
+
+kernel_modules:
+	${MAKE} -C $(CURDIR)/../.. M=$(CURDIR)
+clean:
+	${MAKE} -C $(CURDIR)/../.. M=$(CURDIR) clean
diff --git a/tools/cma/cma_test.c b/tools/cma/cma_test.c
new file mode 100644
index 0000000..7eb96db
--- /dev/null
+++ b/tools/cma/cma_test.c
@@ -0,0 +1,140 @@
+/*
+ * kernel module helper for testing CMA
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+struct cma_allocation {
+	struct list_head list;
+	size_t size;
+	dma_addr_t dma;
+	void *virt;
+};
+
+static struct device *cma_dev;
+static LIST_HEAD(cma_allocations);
+static DEFINE_SPINLOCK(cma_lock);
+
+/*
+ * any read request will free the 1st allocated coherent memory, eg.
+ * cat /dev/cma_test
+ */
+static ssize_t
+cma_test_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
+{
+	struct cma_allocation *alloc = NULL;
+
+	spin_lock(&cma_lock);
+	if (!list_empty(&cma_allocations)) {
+		alloc = list_first_entry(&cma_allocations,
+			struct cma_allocation, list);
+		list_del(&alloc->list);
+	}
+	spin_unlock(&cma_lock);
+
+	if (!alloc)
+		return -EIDRM;
+
+	dma_free_coherent(cma_dev, alloc->size, alloc->virt,
+		alloc->dma);
+
+	_dev_info(cma_dev, "free: CM virt: %p dma: %p size:%zuK\n",
+		alloc->virt, (void *)alloc->dma, alloc->size / SZ_1K);
+	kfree(alloc);
+
+	return 0;
+}
+
+/*
+ * any write request will alloc a new coherent memory, eg.
+ * echo 1024 > /dev/cma_test
+ * will request 1024KiB by CMA
+ */
+static ssize_t
+cma_test_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
+{
+	struct cma_allocation *alloc;
+	unsigned long size;
+	int ret;
+
+	ret = kstrtoul_from_user(buf, count, 0, &size);
+	if (ret)
+		return ret;
+
+	if (!size)
+		return -EINVAL;
+
+	if (size > ~(size_t)0 / SZ_1K)
+		return -EOVERFLOW;
+
+	alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
+	if (!alloc)
+		return -ENOMEM;
+
+	alloc->size = size * SZ_1K;
+	alloc->virt = dma_alloc_coherent(cma_dev, alloc->size,
+		&alloc->dma, GFP_KERNEL);
+
+	if (alloc->virt) {
+		_dev_info(cma_dev, "alloc: virt: %p dma: %p size: %zuK\n",
+			alloc->virt, (void *)alloc->dma, alloc->size / SZ_1K);
+
+		spin_lock(&cma_lock);
+		list_add_tail(&alloc->list, &cma_allocations);
+		spin_unlock(&cma_lock);
+
+		return count;
+	} else {
+		dev_err(cma_dev, "no mem in CMA area\n");
+		kfree(alloc);
+		return -ENOSPC;
+	}
+}
+
+static const struct file_operations cma_test_fops = {
+	.owner =    THIS_MODULE,
+	.read  =    cma_test_read,
+	.write =    cma_test_write,
+};
+
+static struct miscdevice cma_test_misc = {
+	.name = "cma_test",
+	.fops = &cma_test_fops,
+};
+
+static int __init cma_test_init(void)
+{
+	int ret = misc_register(&cma_test_misc);
+
+	if (unlikely(ret)) {
+		pr_err("failed to register cma test misc device!\n");
+		return ret;
+	}
+	cma_dev = cma_test_misc.this_device;
+	cma_dev->coherent_dma_mask = ~0;
+	_dev_info(cma_dev, "registered.\n");
+
+	return 0;
+}
+module_init(cma_test_init);
+
+static void __exit cma_test_exit(void)
+{
+	misc_deregister(&cma_test_misc);
+}
+module_exit(cma_test_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Barry Song <Baohua.Song at csr.com>");
+MODULE_DESCRIPTION("kernel module to help the test of CMA");
+MODULE_ALIAS("cma_test");
-- 
1.7.1



Member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom
More information can be found at www.csr.com. Follow CSR on Twitter at http://twitter.com/CSR_PLC and read our blog at www.csr.com/blog


From sshtylyov at mvista.com  Wed Mar  7 06:38:52 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 07 Mar 2012 15:38:52 +0400
Subject: [PATCH 10/15] watchdog/mpcore_wdt: Add support for dev_pm_ops
 interface
In-Reply-To: <b50542be97df8b90d3e7c696a8d13be707f581f9.1331115752.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <b50542be97df8b90d3e7c696a8d13be707f581f9.1331115752.git.viresh.kumar@st.com>
Message-ID: <4F5748CC.9020601@ru.mvista.com>

Hello.

On 07-03-2012 14:27, Viresh Kumar wrote:

> This patch adds dev_pm_ops support for standby/slepp/hibernate.

> Signed-off-by: Viresh Kumar<viresh.kumar at st.com>
> ---
>   drivers/watchdog/mpcore_wdt.c |   18 +++++++++---------
>   1 files changed, 9 insertions(+), 9 deletions(-)

> diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
> index e02c02b..a099418 100644
> --- a/drivers/watchdog/mpcore_wdt.c
> +++ b/drivers/watchdog/mpcore_wdt.c
[...]
> @@ -384,40 +385,39 @@ static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
[...]
>   /* work with hotplug and coldplug */
>   MODULE_ALIAS("platform:mpcore_wdt");
>
>   static struct platform_driver mpcore_wdt_driver = {
>   	.probe		= mpcore_wdt_probe,
>   	.remove		= __devexit_p(mpcore_wdt_remove),
> -	.suspend	= mpcore_wdt_suspend,
> -	.resume		= mpcore_wdt_resume,
>   	.shutdown	= mpcore_wdt_shutdown,
>   	.driver		= {
>   		.owner	= THIS_MODULE,
>   		.name	= "mpcore_wdt",
> +		.pm = &mpcore_wdt_dev_pm_ops,

    Please align the right part of initializer like all above.

WBR, Sergei


From kgene.kim at samsung.com  Wed Mar  7 06:41:22 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 07 Mar 2012 03:41:22 -0800
Subject: [PATCH] ARM: S3C24XX: Fix Section mismatch
In-Reply-To: <20120307112219.GR17370@n2100.arm.linux.org.uk>
References: <1331116612-14491-1-git-send-email-kgene.kim@samsung.com>
 <20120307112219.GR17370@n2100.arm.linux.org.uk>
Message-ID: <4F574962.9020801@samsung.com>

On 03/07/12 03:22, Russell King - ARM Linux wrote:
> On Wed, Mar 07, 2012 at 02:36:52AM -0800, Kukjin Kim wrote:
>> WARNING: arch/arm/mach-s3c24xx/built-in.o(.data+0xf44): Section mismatch in reference
>> from the variable s3c2416_irq_interface to the function .init.text:s3c2416_irq_add()
>> The variable s3c2416_irq_interface references
>> the function __init s3c2416_irq_add()
>> If the reference is valid then annotate the
>> variable with __init* or __refdata (see linux/init.h) or name the variable:
>> *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
>>
>> WARNING: arch/arm/mach-s3c24xx/built-in.o(.data+0x1b80): Section mismatch in reference
>> from the variable s3c2443_irq_interface to the function .init.text:s3c2443_irq_add()
>> The variable s3c2443_irq_interface references
>> the function __init s3c2443_irq_add()
>> If the reference is valid then annotate the
>> variable with __init* or __refdata (see linux/init.h) or name the variable:
>> *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
>
>> diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
>> index b8a5836..59b7632 100644
>> --- a/arch/arm/mach-s3c24xx/irq-s3c2416.c
>> +++ b/arch/arm/mach-s3c24xx/irq-s3c2416.c
>> @@ -310,7 +310,7 @@ static int __init s3c2416_irq_add(struct device *dev)
>>   	return 0;
>>   }
>>
>> -static struct subsys_interface s3c2416_irq_interface = {
>> +static struct subsys_interface s3c2416_irq_interface __initdata = {
>>   	.name		= "s3c2416_irq",
>>   	.subsys		=&s3c2416_subsys,
>>   	.add_dev	= s3c2416_irq_add,
>> diff --git a/arch/arm/mach-s3c24xx/irq-s3c2443.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c
>> index 35e4ff2..439f186 100644
>> --- a/arch/arm/mach-s3c24xx/irq-s3c2443.c
>> +++ b/arch/arm/mach-s3c24xx/irq-s3c2443.c
>> @@ -265,7 +265,7 @@ static int __init s3c2443_irq_add(struct device *dev)
>>   	return 0;
>>   }
>>
>> -static struct subsys_interface s3c2443_irq_interface = {
>> +static struct subsys_interface s3c2443_irq_interface __initdata = {
>>   	.name		= "s3c2443_irq",
>>   	.subsys		=&s3c2443_subsys,
>>   	.add_dev	= s3c2443_irq_add,
>
> You register these structures with some other bit of code.  That other
> bit of code adds these structures to a list. You then mark them as
> __initdata, which means they get freed and the memory reused.  That
> corrupts the list beneath the other code.
>
> So, clearly, both of these are wrong.

Oops, I see. Let me check it again.
Thanks for pointing out.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From sshtylyov at mvista.com  Wed Mar  7 06:40:38 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 07 Mar 2012 15:40:38 +0400
Subject: [PATCH 12/15] watchdog/mpcore_wdt: Add support for WDIOF_CARDRESET
In-Reply-To: <cb4bdf968a4d53eebf8005636fcef5fde8cbebf7.1331115752.git.viresh.kumar@st.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <cb4bdf968a4d53eebf8005636fcef5fde8cbebf7.1331115752.git.viresh.kumar@st.com>
Message-ID: <4F574936.3010909@ru.mvista.com>

Hello.

On 07-03-2012 14:27, Viresh Kumar wrote:

> mpcore watchdog can give last boot status, whether we got a watchdog reset or
> not, via bit 0 of TWD_WDOG_RESETSTAT register. This patch adds support to return
> correct status if WDIOC_GETBOOTSTATUS cmd is called with ioctl.

    In the subject you say about another ioclt.

> Signed-off-by: Viresh Kumar<viresh.kumar at st.com>
> ---
>   arch/arm/include/asm/smp_twd.h |    2 ++
>   drivers/watchdog/mpcore_wdt.c  |   10 +++++++++-
>   2 files changed, 11 insertions(+), 1 deletions(-)

WBR, Sergei



From stigge at antcom.de  Wed Mar  7 06:53:28 2012
From: stigge at antcom.de (Roland Stigge)
Date: Wed, 07 Mar 2012 12:53:28 +0100
Subject: [PATCH v5] lpc32xx: Added ethernet driver
In-Reply-To: <201203062134.38077.arnd@arndb.de>
References: <1331067664-9124-1-git-send-email-stigge@antcom.de>
 <201203062134.38077.arnd@arndb.de>
Message-ID: <4F574C38.4030006@antcom.de>

Hi Arnd,

On 03/06/2012 10:34 PM, Arnd Bergmann wrote:
> This should eventually both become run-time options based on the device tree.
> I don't know if you planned to do that anyway, but if you want the same kernel
> binary to be used for systems in different configurations, you cannot have
> compile-time decisions that are exclusive-or. Since you don't support device
> tree yet but plan to do that in the future, you could add a comment here
> about it, or you could even prepare it for that case already by passing the
> device into the functions that will be required for reading the properties.

Good point.

I prefer putting a comment for now, because upon the planned device tree
introduction in lpc32xx, an internal change in lpc_eth.c will be
necessary anyway, so there is no need to already introduce unused
parameters at this point.

Thanks,

Roland


From gerg at snapgear.com  Wed Mar  7 06:54:12 2012
From: gerg at snapgear.com (Greg Ungerer)
Date: Wed, 7 Mar 2012 21:54:12 +1000
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <20120307091409.GL17370@n2100.arm.linux.org.uk>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201202281945.39419.arnd@arndb.de>
 <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
 <201203061412.00073.arnd@arndb.de>
 <alpine.LFD.2.02.1203061146210.31242@xanadu.home>
 <CACRpkdYQpnSMVWUizEYHTjx_AK5Ai7dos0SBd208Wf5ZJLdrCw@mail.gmail.com>
 <20120307091409.GL17370@n2100.arm.linux.org.uk>
Message-ID: <4F574C64.7010905@snapgear.com>

On 03/07/2012 07:14 PM, Russell King - ARM Linux wrote:
> On Wed, Mar 07, 2012 at 09:40:31AM +0100, Linus Walleij wrote:
>> Network equipment seems to like using BE.
>>
>> I have some vague idea that this is beacuse IP packets are big
>> endian, and thus you can process them quickly by just casting fields
>> to e.g. u32 pointers and read them.
>>
>> I don't know if this is true, but seems to much of a correlation to
>> be pure coincidence. Thus a pretty interesting subject in
>> embedded ARM not used for tablets/mobile/generic computing
>> kind of stuff.
>
> ISTR Nicolas explained this to me as being an established thing in the
> comms sector.  They expect BE and only understand BE.
>
> I did point out that you end up with many more endian conversions by
> going to BE, mainly because PCI is LE and all your PCI accesses have
> to be endian-swapped.  So in terms of bandwidth, I'd expect an ARM
> PCI platform running in BE mode to have worse throughput than a LE
> PCI platform.

The built in ethernet interfaces on the ixp4xx family are not PCI
based. So they at least do not suffer from the BE/LE conversions
at the eth driver.

Regards
Greg


------------------------------------------------------------------------
Greg Ungerer  --  Principal Engineer        EMAIL:     gerg at snapgear.com
SnapGear Group, McAfee                      PHONE:       +61 7 3435 2888
8 Gardner Close,                            FAX:         +61 7 3891 3630
Milton, QLD, 4064, Australia                WEB: http://www.SnapGear.com


From kgene.kim at samsung.com  Wed Mar  7 06:55:26 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 07 Mar 2012 03:55:26 -0800
Subject: [GIT PULL] fix to use static declarations for samsung stuff
In-Reply-To: <013b01cce7f3$48c87e30$da597a90$%kim@samsung.com>
References: <013b01cce7f3$48c87e30$da597a90$%kim@samsung.com>
Message-ID: <4F574CAE.6030903@samsung.com>

On 02/10/12 04:55, Kukjin Kim wrote:
> Hi Russell, Arnd and Olof,
>
> Please pull following branch which is including fix to use static
> declarations for samsung stuff.
>   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/cleanup-use-static
>
> I'm not sure it can be sent to upstream for v3.3 but if so, would be better.
>
Hi Arnd, Olof,

I can't see this series in arm-soc yet. If missed, please pull from:
  http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/cleanup-use-static

As a note, I rebased it on top of arm-soc/depends/rmk/for-armsoc because 
this touches same points(dma declaration part).

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit a5f17d1f4c2831b9b9bf8b1a537cdbac995d6e13:

   Merge tag 'v3.3-rc2' into depends/rmk/for-armsoc (2012-02-07 15:05:20 
-0800)

are available in the git repository at:

 
http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/cleanup-use-static

Kukjin Kim (8):
       ARM: EXYNOS: use static declaration when it is not used in other 
files
       ARM: S3C24XX: use static declaration when it is not used in other 
files
       ARM: S3C64XX: use static declaration when it is not used in other 
files
       ARM: S5P64X0: use static declaration when it is not used in other 
files
       ARM: S5PC100: use static declaration when it is not used in other 
files
       ARM: S5PV210: use static declaration when it is not used in other 
files
       ARM: SAMSUNG: use static declaration when it is not used in other 
files
       Merge branch 'topic/cleanup-use-static' into next/cleanup-use-static

  arch/arm/mach-exynos/clock-exynos4210.c            |    2 +-
  arch/arm/mach-exynos/clock-exynos4212.c            |    2 +-
  arch/arm/mach-exynos/clock.c                       |    2 +-
  arch/arm/mach-exynos/common.c                      |    2 +-
  arch/arm/mach-exynos/dma.c                         |   16 +++++-----
  arch/arm/mach-exynos/mach-origen.c                 |    2 +-
  arch/arm/mach-exynos/mach-universal_c210.c         |    2 +-
  arch/arm/mach-s3c2410/mach-h1940.c                 |   12 ++++----
  arch/arm/mach-s3c2416/clock.c                      |    6 ----
  arch/arm/mach-s3c2416/mach-smdk2416.c              |    8 +++---
  arch/arm/mach-s3c2440/mach-gta02.c                 |    4 +-
  arch/arm/mach-s3c2440/mach-rx1950.c                |   12 ++++----
  arch/arm/mach-s3c64xx/common.c                     |    2 +-
  arch/arm/mach-s3c64xx/common.h                     |    2 -
  arch/arm/mach-s3c64xx/irq-pm.c                     |    2 +-
  arch/arm/mach-s5p64x0/clock.c                      |   11 ++++---
  arch/arm/mach-s5p64x0/dma.c                        |   12 ++++----
  arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h |    7 -----
  arch/arm/mach-s5pc100/clock.c                      |   28 
++++++++++----------
  arch/arm/mach-s5pc100/dma.c                        |   16 +++++-----
  arch/arm/mach-s5pv210/dma.c                        |   16 +++++-----
  arch/arm/mach-s5pv210/mach-goni.c                  |    2 +-
  arch/arm/mach-s5pv210/mach-smdkv210.c              |    2 +-
  arch/arm/plat-s3c24xx/s3c2443-clock.c              |    2 +-
  arch/arm/plat-s5p/irq-eint.c                       |    2 +-
  arch/arm/plat-s5p/irq-gpioint.c                    |    2 +-
  arch/arm/plat-samsung/devs.c                       |   13 +--------
  arch/arm/plat-samsung/dma-ops.c                    |    2 +-
  28 files changed, 83 insertions(+), 108 deletions(-)

> As a note, conflicts have been occurred when merge
> arm-soc/depends/rmk/for-armsoc.
> Following is my preferred resolution.
>
> If any problems, please kindly let me know.
>
> diff --cc arch/arm/mach-exynos/dma.c
> index 8dec3db,91370de..0000000
> --- a/arch/arm/mach-exynos/dma.c
> +++ b/arch/arm/mach-exynos/dma.c
> @@@ -74,23 -74,10 +74,10 @@@ static struct dma_pl330_platdata exynos
>    	.peri_id = pdma0_peri,
>    };
>
> - static struct amba_device exynos4_device_pdma0 = {
> - 	.dev = {
> - 		.init_name = "dma-pl330.0",
> - 		.dma_mask =&dma_dmamask,
> - 		.coherent_dma_mask = DMA_BIT_MASK(32),
> - 		.platform_data =&exynos4_pdma0_pdata,
> - 	},
> - 	.res = {
> - 		.start = EXYNOS4_PA_PDMA0,
> - 		.end = EXYNOS4_PA_PDMA0 + SZ_4K,
> - 		.flags = IORESOURCE_MEM,
> - 	},
> - 	.irq = {IRQ_PDMA0, NO_IRQ},
> - 	.periphid = 0x00041330,
> - };
>   -AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
> EXYNOS4_PA_PDMA0,
>   -	{IRQ_PDMA0},&exynos4_pdma0_pdata);
> ++static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
> ++	EXYNOS4_PA_PDMA0, {IRQ_PDMA0},&exynos4_pdma0_pdata);
>
>   -u8 pdma1_peri[] = {
>   +static u8 pdma1_peri[] = {
>    	DMACH_PCM0_RX,
>    	DMACH_PCM0_TX,
>    	DMACH_PCM1_RX,
> @@@ -123,21 -110,8 +110,8 @@@ static struct dma_pl330_platdata exynos
>    	.peri_id = pdma1_peri,
>    };
>
> - static struct amba_device exynos4_device_pdma1 = {
> - 	.dev = {
> - 		.init_name = "dma-pl330.1",
> - 		.dma_mask =&dma_dmamask,
> - 		.coherent_dma_mask = DMA_BIT_MASK(32),
> - 		.platform_data =&exynos4_pdma1_pdata,
> - 	},
> - 	.res = {
> - 		.start = EXYNOS4_PA_PDMA1,
> - 		.end = EXYNOS4_PA_PDMA1 + SZ_4K,
> - 		.flags = IORESOURCE_MEM,
> - 	},
> - 	.irq = {IRQ_PDMA1, NO_IRQ},
> - 	.periphid = 0x00041330,
> - };
>   -AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,
> EXYNOS4_PA_PDMA1,
>   -	{IRQ_PDMA1},&exynos4_pdma1_pdata);
> ++static AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,
> ++	EXYNOS4_PA_PDMA1, {IRQ_PDMA1},&exynos4_pdma1_pdata);
>
>    static int __init exynos4_dma_init(void)
>    {
> diff --cc arch/arm/mach-s5p64x0/dma.c
> index 8fce1161,f7f68ad..0000000
> --- a/arch/arm/mach-s5p64x0/dma.c
> +++ b/arch/arm/mach-s5p64x0/dma.c
> @@@ -108,20 -108,8 +108,8 @@@ static struct dma_pl330_platdata s5p645
>    	.peri_id = s5p6450_pdma_peri,
>    };
>
> - static struct amba_device s5p64x0_device_pdma = {
> - 	.dev = {
> - 		.init_name = "dma-pl330",
> - 		.dma_mask =&dma_dmamask,
> - 		.coherent_dma_mask = DMA_BIT_MASK(32),
> - 	},
> - 	.res = {
> - 		.start = S5P64X0_PA_PDMA,
> - 		.end = S5P64X0_PA_PDMA + SZ_4K,
> - 		.flags = IORESOURCE_MEM,
> - 	},
> - 	.irq = {IRQ_DMA0, NO_IRQ},
> - 	.periphid = 0x00041330,
> - };
>   -AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330, S5P64X0_PA_PDMA,
>   -	{IRQ_DMA0}, NULL);
> ++static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330,
> ++	S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL);
>
>    static int __init s5p64x0_dma_init(void)
>    {
> diff --cc arch/arm/mach-s5pc100/dma.c
> index 395e46b,96b1ab3..0000000
> --- a/arch/arm/mach-s5pc100/dma.c
> +++ b/arch/arm/mach-s5pc100/dma.c
> @@@ -73,23 -73,10 +73,10 @@@ static struct dma_pl330_platdata s5pc10
>    	.peri_id = pdma0_peri,
>    };
>
> - static struct amba_device s5pc100_device_pdma0 = {
> - 	.dev = {
> - 		.init_name = "dma-pl330.0",
> - 		.dma_mask =&dma_dmamask,
> - 		.coherent_dma_mask = DMA_BIT_MASK(32),
> - 		.platform_data =&s5pc100_pdma0_pdata,
> - 	},
> - 	.res = {
> - 		.start = S5PC100_PA_PDMA0,
> - 		.end = S5PC100_PA_PDMA0 + SZ_4K,
> - 		.flags = IORESOURCE_MEM,
> - 	},
> - 	.irq = {IRQ_PDMA0, NO_IRQ},
> - 	.periphid = 0x00041330,
> - };
>   -AMBA_AHB_DEVICE(s5pc100_pdma0,  "dma-pl330.0", 0x00041330,
> S5PC100_PA_PDMA0,
>   -	{IRQ_PDMA0},&s5pc100_pdma0_pdata);
> ++static AMBA_AHB_DEVICE(s5pc100_pdma0,  "dma-pl330.0", 0x00041330,
> ++	S5PC100_PA_PDMA0, {IRQ_PDMA0},&s5pc100_pdma0_pdata);
>
>   -u8 pdma1_peri[] = {
>   +static u8 pdma1_peri[] = {
>    	DMACH_UART0_RX,
>    	DMACH_UART0_TX,
>    	DMACH_UART1_RX,
> @@@ -127,21 -114,8 +114,8 @@@ static struct dma_pl330_platdata s5pc10
>    	.peri_id = pdma1_peri,
>    };
>
> - static struct amba_device s5pc100_device_pdma1 = {
> - 	.dev = {
> - 		.init_name = "dma-pl330.1",
> - 		.dma_mask =&dma_dmamask,
> - 		.coherent_dma_mask = DMA_BIT_MASK(32),
> - 		.platform_data =&s5pc100_pdma1_pdata,
> - 	},
> - 	.res = {
> - 		.start = S5PC100_PA_PDMA1,
> - 		.end = S5PC100_PA_PDMA1 + SZ_4K,
> - 		.flags = IORESOURCE_MEM,
> - 	},
> - 	.irq = {IRQ_PDMA1, NO_IRQ},
> - 	.periphid = 0x00041330,
> - };
>   -AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330,
> S5PC100_PA_PDMA1,
>   -	{IRQ_PDMA1},&s5pc100_pdma1_pdata);
> ++static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330,
> ++	S5PC100_PA_PDMA1, {IRQ_PDMA1},&s5pc100_pdma1_pdata);
>
>    static int __init s5pc100_dma_init(void)
>    {
> diff --cc arch/arm/mach-s5pv210/dma.c
> index fc1be6e,f6885d2..0000000
> --- a/arch/arm/mach-s5pv210/dma.c
> +++ b/arch/arm/mach-s5pv210/dma.c
> @@@ -71,23 -71,10 +71,10 @@@ static struct dma_pl330_platdata s5pv21
>    	.peri_id = pdma0_peri,
>    };
>
> - static struct amba_device s5pv210_device_pdma0 = {
> - 	.dev = {
> - 		.init_name = "dma-pl330.0",
> - 		.dma_mask =&dma_dmamask,
> - 		.coherent_dma_mask = DMA_BIT_MASK(32),
> - 		.platform_data =&s5pv210_pdma0_pdata,
> - 	},
> - 	.res = {
> - 		.start = S5PV210_PA_PDMA0,
> - 		.end = S5PV210_PA_PDMA0 + SZ_4K,
> - 		.flags = IORESOURCE_MEM,
> - 	},
> - 	.irq = {IRQ_PDMA0, NO_IRQ},
> - 	.periphid = 0x00041330,
> - };
>   -AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330,
> S5PV210_PA_PDMA0,
>   -	{IRQ_PDMA0},&s5pv210_pdma0_pdata);
> ++static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330,
> ++	S5PV210_PA_PDMA0, {IRQ_PDMA0},&s5pv210_pdma0_pdata);
>
>   -u8 pdma1_peri[] = {
>   +static u8 pdma1_peri[] = {
>    	DMACH_UART0_RX,
>    	DMACH_UART0_TX,
>    	DMACH_UART1_RX,
> @@@ -127,21 -114,8 +114,8 @@@ static struct dma_pl330_platdata s5pv21
>    	.peri_id = pdma1_peri,
>    };
>
> - static struct amba_device s5pv210_device_pdma1 = {
> - 	.dev = {
> - 		.init_name = "dma-pl330.1",
> - 		.dma_mask =&dma_dmamask,
> - 		.coherent_dma_mask = DMA_BIT_MASK(32),
> - 		.platform_data =&s5pv210_pdma1_pdata,
> - 	},
> - 	.res = {
> - 		.start = S5PV210_PA_PDMA1,
> - 		.end = S5PV210_PA_PDMA1 + SZ_4K,
> - 		.flags = IORESOURCE_MEM,
> - 	},
> - 	.irq = {IRQ_PDMA1, NO_IRQ},
> - 	.periphid = 0x00041330,
> - };
>   -AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330,
> S5PV210_PA_PDMA1,
>   -	{IRQ_PDMA1},&s5pv210_pdma1_pdata);
> ++static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330,
> ++	S5PV210_PA_PDMA1, {IRQ_PDMA1},&s5pv210_pdma1_pdata);
>
>    static int __init s5pv210_dma_init(void)
>    {
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim<kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> The following changes since commit 62aa2b537c6f5957afd98e29f96897419ed5ebab:
>
>    Linux 3.3-rc2 (2012-01-31 13:31:54 -0800)
>
> are available in the git repository at:
>    git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/cleanup-use-static
>
> Kukjin Kim (7):
>        ARM: EXYNOS: use static declaration when it is not used in other files
>        ARM: S3C24XX: use static declaration when it is not used in other
> files
>        ARM: S3C64XX: use static declaration when it is not used in other
> files
>        ARM: S5P64X0: use static declaration when it is not used in other
> files
>        ARM: S5PC100: use static declaration when it is not used in other
> files
>        ARM: S5PV210: use static declaration when it is not used in other
> files
>        ARM: SAMSUNG: use static declaration when it is not used in other
> files
>
>   arch/arm/mach-exynos/clock-exynos4210.c            |    2 +-
>   arch/arm/mach-exynos/clock-exynos4212.c            |    2 +-
>   arch/arm/mach-exynos/clock.c                       |    2 +-
>   arch/arm/mach-exynos/common.c                      |    2 +-
>   arch/arm/mach-exynos/dma.c                         |   12 ++++----
>   arch/arm/mach-exynos/mach-origen.c                 |    2 +-
>   arch/arm/mach-exynos/mach-universal_c210.c         |    2 +-
>   arch/arm/mach-s3c2410/mach-h1940.c                 |   12 ++++----
>   arch/arm/mach-s3c2416/clock.c                      |    6 ----
>   arch/arm/mach-s3c2416/mach-smdk2416.c              |    8 +++---
>   arch/arm/mach-s3c2440/mach-gta02.c                 |    4 +-
>   arch/arm/mach-s3c2440/mach-rx1950.c                |   12 ++++----
>   arch/arm/mach-s3c64xx/common.c                     |    2 +-
>   arch/arm/mach-s3c64xx/common.h                     |    2 -
>   arch/arm/mach-s3c64xx/irq-pm.c                     |    2 +-
>   arch/arm/mach-s5p64x0/clock.c                      |   11 ++++---
>   arch/arm/mach-s5p64x0/dma.c                        |   10 +++---
>   arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h |    7 -----
>   arch/arm/mach-s5pc100/clock.c                      |   28
> ++++++++++----------
>   arch/arm/mach-s5pc100/dma.c                        |   12 ++++----
>   arch/arm/mach-s5pv210/dma.c                        |   12 ++++----
>   arch/arm/mach-s5pv210/mach-goni.c                  |    2 +-
>   arch/arm/mach-s5pv210/mach-smdkv210.c              |    2 +-
>   arch/arm/plat-s3c24xx/s3c2443-clock.c              |    2 +-
>   arch/arm/plat-s5p/irq-eint.c                       |    2 +-
>   arch/arm/plat-s5p/irq-gpioint.c                    |    2 +-
>   arch/arm/plat-samsung/devs.c                       |   13 +--------
>   arch/arm/plat-samsung/dma-ops.c                    |    2 +-
>   28 files changed, 76 insertions(+), 101 deletions(-)


From santosh.shilimkar at ti.com  Wed Mar  7 06:59:18 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 07 Mar 2012 12:59:18 +0100
Subject: [PATCH v3 02/13] gpio/omap: fix wakeup_en register update in
 _set_gpio_wakeup()
In-Reply-To: <1331118963-26364-3-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-3-git-send-email-tarun.kanti@ti.com>
Message-ID: <4F574D96.5070306@ti.com>

On Wednesday 07 March 2012 12:15 PM, Tarun Kanti DebBarma wrote:
> There are two ways through which wakeup_en register can be programmed
> using gpiolib APIs as shown below. It is seen that in the second case
> in _set_gpio_wakeup(), even though bank->suspend_wakeup is updated
> correctly, its value is not programmed in wakeup_en register. Fix this.
> 
> chip.irq_set_type()->gpio_irq_type()->_set_gpio_triggering()->set_gpio_trigger()
> chip.irq_set_wake()->gpio_wake_enable()->_set_gpio_wakeup()
> 
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> ---
Looks good.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

Regards
Santosh


From santosh.shilimkar at ti.com  Wed Mar  7 07:00:13 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 07 Mar 2012 13:00:13 +0100
Subject: [PATCH v3 08/13] gpio/omap: remove redundant decoding of gpio
 offset
In-Reply-To: <1331118963-26364-9-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-9-git-send-email-tarun.kanti@ti.com>
Message-ID: <4F574DCD.4000507@ti.com>

On Wednesday 07 March 2012 12:15 PM, Tarun Kanti DebBarma wrote:
> In gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of
> un-necessary operation to compute gpio mask. The gpio offset passed
> to gpio_get() is sufficient to do that.
> 
> Here is Russell's original comment:
> Can someone explain to me this:
> #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
> #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
> 
> static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
> {
>        void __iomem *reg = bank->base + bank->regs->datain;
> 
>        return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
> }
> 
> static int gpio_get(struct gpio_chip *chip, unsigned offset)
> {
>        struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
>        void __iomem *reg = bank->base;
>        int gpio = chip->base + offset;
>        u32 mask = GPIO_BIT(bank, gpio);
> 
>        if (gpio_is_input(bank, mask))
>                return _get_gpio_datain(bank, gpio);
>        else
>                return _get_gpio_dataout(bank, gpio);
> }
> 
> Given that bank->width on OMAP is either 32 or 16, and GPIO numbers for
> any GPIO chip are always aligned to 32 or 16, why does this code bother
> adding the chips base gpio number and then modulo the width?
> 
> Surely this means if - for argument sake - you registered a GPIO chip
> with 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0
> bit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be
> chip 1 bit 0..7.
> 
> However, if you registered a GPIO chip with 16 lines first, it would
> mean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be
> chip 1 bit 0..15.
> 
> Surely this kind of behaviour is not intended?
> 
> Is there a reason why the bitmask can't just be (1 << offset) where
> offset is passed into these functions as GPIO number - chip->base ?
> 
> Reported-by: Russell King - ARM Linux <linux at arm.linux.org.uk>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Looks good.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

Regards
Santosh


From santosh.shilimkar at ti.com  Wed Mar  7 07:01:41 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 07 Mar 2012 13:01:41 +0100
Subject: [PATCH v3 09/13] gpio/omap: remove suspend/resume callbacks
In-Reply-To: <1331118963-26364-10-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-10-git-send-email-tarun.kanti@ti.com>
Message-ID: <4F574E25.6010702@ti.com>

On Wednesday 07 March 2012 12:15 PM, Tarun Kanti DebBarma wrote:
> Both omap_gpio_suspend() and omap_gpio_resume() does programming
> of wakeup_en register.
> _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
> _gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
> 
> This is redundant in omap_gpio_suspend() because wakeup_en
> register automatically gets initialized in _set_gpio_wakeup()
> and set_gpio_trigger() while being called either from
> chip.irq_set_wake() or chip.irq_set_type().
> 
> This is redundant in omap_gpio_resume() because wakeup_en
s/This is/This is also

> register is programmed in omap_gpio_restore_context() called
> which is called from runtime resume callback.
> 
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> ---
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

Regards
Santosh


From santosh.shilimkar at ti.com  Wed Mar  7 07:03:50 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 07 Mar 2012 13:03:50 +0100
Subject: [PATCH v3 10/13] gpio/omap: fix missing dataout context save
 in _set_gpio_dataout_reg
In-Reply-To: <1331118963-26364-11-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-11-git-send-email-tarun.kanti@ti.com>
Message-ID: <4F574EA6.4000807@ti.com>

On Wednesday 07 March 2012 12:16 PM, Tarun Kanti DebBarma wrote:
> There are two functions, _set_gpio_dataout_reg() and _set_gpio_dataout_mask()
> which writes to dataout register and the dataout context must be saved.
> It is missing in the first function, _set_gpio_dataout_reg(). Fix this.
> 
> Reported-by: Govindraj Raja <govindraj.raja at ti.com>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> ---
Good catch. Is the suspend/resume caught this issue?

This can go as a fix as well.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

Regards
Santosh


From santosh.shilimkar at ti.com  Wed Mar  7 07:04:34 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 07 Mar 2012 13:04:34 +0100
Subject: [PATCH v3 11/13] gpio/omap: fix dataout register overwrite in
 _set_gpio_dataout_*
In-Reply-To: <1331118963-26364-12-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-12-git-send-email-tarun.kanti@ti.com>
Message-ID: <4F574ED2.4020102@ti.com>

On Wednesday 07 March 2012 12:16 PM, Tarun Kanti DebBarma wrote:
> In the existing _set_gpio_dataout_*() implementation, the dataout
> register is overwritten every time the function is called. This is
> not intended behavior because that would end up one user of a GPIO
> line overwriting what is written by another. Fix this so that previous
> value is always preserved until explicitly changed by respective
> user/driver of the GPIO line.
> 
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> ---
This can also go as fix.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

Regards
Santosh


From kgene.kim at samsung.com  Wed Mar  7 07:06:37 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 07 Mar 2012 04:06:37 -0800
Subject: [PATCH v2 2/3] gpio/samsung: add support GPIOlib for EXYNOS5250
In-Reply-To: <1329341829-14403-3-git-send-email-kgene.kim@samsung.com>
References: <1329341829-14403-1-git-send-email-kgene.kim@samsung.com>
 <1329341829-14403-3-git-send-email-kgene.kim@samsung.com>
Message-ID: <4F574F4D.5000708@samsung.com>

On 02/15/12 13:37, Kukjin Kim wrote:
> From: Sangsu Park<sangsu4u.park at samsung.com>
>
> This patch adds gpio_chips for EXYNOS5250 and replaces
> exynos4_xxx() with exynos_xxx() and variables to support
> exynos4 and exynos5 together.
> In addition, use ioreamp() for base address of gpios.
>
> Signed-off-by: Sangsu Park<sangsu4u.park at samsung.com>
> Cc: Grant Likely<grant.likely at secretlab.ca>

Hi Grant,

How about upstreaming this via samsung tree when sending EXYNOS5 stuff, 
I think, gpio-samsung needs still cleanup though? If any comments, 
please kindly let me know.

> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
> ---
>   drivers/gpio/gpio-samsung.c             |  439 +++++++++++++++++++++++++++++--
>   1 files changed, 411 insertions(+), 28 deletions(-)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From santosh.shilimkar at ti.com  Wed Mar  7 07:07:49 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 07 Mar 2012 13:07:49 +0100
Subject: [PATCH v3 12/13] gpio/omap: fix incorrect context restore logic
 in omap_gpio_runtime_resume
In-Reply-To: <1331118963-26364-13-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-13-git-send-email-tarun.kanti@ti.com>
Message-ID: <4F574F95.7090801@ti.com>

On Wednesday 07 March 2012 12:16 PM, Tarun Kanti DebBarma wrote:
> In omap_gpio_runtime_resume() the context restore should be independent
> of bank->enabled_non_wakeup_gpios. This was preventing context restore
> of GPIO lines which are not wakeup enabled.
> 
> Reported-by: Govindraj Raja <govindraj.raja at ti.com>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> ---
>  drivers/gpio/gpio-omap.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 2e8e476..ccfbae0 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -1227,7 +1227,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
>  	__raw_writel(bank->context.risingdetect,
>  		     bank->base + bank->regs->risingdetect);
>  
> -	if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
> +	if (!bank->workaround_enabled) {
This doesn't seem to be right.
Don't you want to avoid GPIO restore for banks which are in
always on domain. Infact the purpose of "enabled_non_wakeup_gpios"
is exactly that ? Isn't it.

What am I missing ?

Regards
Santosh


From santosh.shilimkar at ti.com  Wed Mar  7 07:09:04 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 07 Mar 2012 13:09:04 +0100
Subject: [PATCH v3 13/13] gpio/omap: fix incorrect update to
 context.irqenable1
In-Reply-To: <1331118963-26364-14-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-14-git-send-email-tarun.kanti@ti.com>
Message-ID: <4F574FE0.7080706@ti.com>

On Wednesday 07 March 2012 12:16 PM, Tarun Kanti DebBarma wrote:
> In _enable_gpio_irqbank() when bank->regs->set_irqenable is valid,
> gpio_mask can be directly set by writing to set_irqenable register
> without overwriting current value. In order to ensure the same is
> stored in context.irqenable1, we must read from regs->irqenable
> instead of overwriting it with gpio_mask.
> The overwriting makes sense only in the second case where irqenable
> is explicitly read and updated with new gpio_mask before writing it
> back. However, for consistency reading regs->irqenable into the
> bank->context.irqenable1 takes care of both the scenarios.
> 
>         if (bank->regs->set_irqenable) {
>                 reg += bank->regs->set_irqenable;
>                 l = gpio_mask;
>         } else {
>                 reg += bank->regs->irqenable;
>                 l = __raw_readl(reg);
>                 if (bank->regs->irqenable_inv)
>                         l &= ~gpio_mask;
>                 else
>                         l |= gpio_mask;
>         }
> 
> Make the same change for _disable_gpio_irqbank().
> 
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> ---
OK.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

Regards
Santosh


From viresh.linux at gmail.com  Wed Mar  7 07:10:36 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Wed, 7 Mar 2012 04:10:36 -0800
Subject: [PATCH 12/15] watchdog/mpcore_wdt: Add support for WDIOF_CARDRESET
In-Reply-To: <4F574936.3010909@ru.mvista.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <cb4bdf968a4d53eebf8005636fcef5fde8cbebf7.1331115752.git.viresh.kumar@st.com>
 <4F574936.3010909@ru.mvista.com>
Message-ID: <CAOh2x==p26zb-vHcX5vnPZYD_P8DWkvTwj=J+4pLytusoMZSOA@mail.gmail.com>

On 3/7/12, Sergei Shtylyov <sshtylyov at mvista.com> wrote:
> On 07-03-2012 14:27, Viresh Kumar wrote:
>
>> mpcore watchdog can give last boot status, whether we got a watchdog reset
>> or
>> not, via bit 0 of TWD_WDOG_RESETSTAT register. This patch adds support to
>> return
>> correct status if WDIOC_GETBOOTSTATUS cmd is called with ioctl.
>
>     In the subject you say about another ioclt.
>

Actually i mentioned what we add in watchdog_info (WDIOF_CARDRESET) in subject,
and mentioned IOCTL in body. Both are right, but yes they must be
consistent. Will
fix subject in V2.

--
viresh


From mina86 at mina86.com  Wed Mar  7 07:11:13 2012
From: mina86 at mina86.com (Michal Nazarewicz)
Date: Wed, 07 Mar 2012 13:11:13 +0100
Subject: [PATCH v4] mm: cma: add a simple kernel module as the helper to
 test CMA
In-Reply-To: <1331120259-30780-1-git-send-email-Barry.Song@csr.com>
References: <1331120259-30780-1-git-send-email-Barry.Song@csr.com>
Message-ID: <op.wasuszai3l0zgt@mpn-glaptop>

On Wed, 07 Mar 2012 12:37:39 +0100, Barry Song <Barry.Song at csr.com> wrote:
> Any write request to /dev/cma_test will let the module to allocate memory from
> CMA, for example:
>
> 1st time
> $ echo 1024 > /dev/cma_test
> will require cma_test to request 1MB(1024KB)
> 2nd time
> $ echo 2048 > /dev/cma_test
> will require cma_test to request 2MB(2048KB)
>
> Any read request to /dev/cma_test will let the module to free the 1st valid
> memory from CMA, for example:
>
> 1st time
> $ cat /dev/cma_test
> will require cma_test to free the 1MB allocated in the first write request
> 2nd time
> $ cat /dev/cma_test
> will require cma_test to free the 2MB allocated in the second write request
>
> Signed-off-by: Barry Song <Baohua.Song at csr.com>

Reviewed-by: Michal Nazarewicz <mina86 at mina86.com>

-- 
Best regards,                                         _     _
.o. | Liege of Serenely Enlightened Majesty of      o' \,=./ `o
..o | Computer Science,  Micha? ?mina86? Nazarewicz    (o o)
ooo +----<email/xmpp: mpn at google.com>--------------ooO--(_)--Ooo--


From viresh.linux at gmail.com  Wed Mar  7 07:11:27 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Wed, 7 Mar 2012 04:11:27 -0800
Subject: [PATCH 10/15] watchdog/mpcore_wdt: Add support for dev_pm_ops
 interface
In-Reply-To: <4F5748CC.9020601@ru.mvista.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <b50542be97df8b90d3e7c696a8d13be707f581f9.1331115752.git.viresh.kumar@st.com>
 <4F5748CC.9020601@ru.mvista.com>
Message-ID: <CAOh2x=mvuFyG3Gg-rdU23hz2TyHNM=u2JWn2uiONuKUEUY3GnQ@mail.gmail.com>

On 3/7/12, Sergei Shtylyov <sshtylyov at mvista.com> wrote:
> On 07-03-2012 14:27, Viresh Kumar wrote:

>>   static struct platform_driver mpcore_wdt_driver = {

>>   	.driver		= {
>>   		.owner	= THIS_MODULE,
>>   		.name	= "mpcore_wdt",
>> +		.pm = &mpcore_wdt_dev_pm_ops,
>
>     Please align the right part of initializer like all above.
>
> WBR, Sergei
>

Sure.

--
viresh


From viresh.linux at gmail.com  Wed Mar  7 07:13:57 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Wed, 7 Mar 2012 04:13:57 -0800
Subject: [PATCH 14/15] watchdog/mpcore_wdt: Add clock framework support
In-Reply-To: <20120307111711.GA31348@bnru02>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <9ec7141baa4b1c1a0503893749e7ce0e19bb5029.1331115752.git.viresh.kumar@st.com>
 <20120307111711.GA31348@bnru02>
Message-ID: <CAOh2x=mcaiSqYW7+9dsNoEhOazrud7BHp5095iqmrgy6iZ4utw@mail.gmail.com>

On 3/7/12, Srinidhi Kasagar <srinidhi.kasagar at stericsson.com> wrote:
> On Wed, Mar 07, 2012 at 11:27:55 +0100, Viresh KUMAR wrote:
>> +	wdt->boot_status = (readl(wdt->base + TWD_WDOG_RESETSTAT) &
>> +			TWD_WDOG_RESETSTAT_MASK) ? WDIOF_CARDRESET : 0;
>> +
>
> I see that patch 12/15 does this, why are you doing it here again in clock
> patch?
>

>>
>> -	wdt->boot_status = (readl(wdt->base + TWD_WDOG_RESETSTAT) &
>> -			TWD_WDOG_RESETSTAT_MASK) ? WDIOF_CARDRESET : 0;
>> -
>
> oh, you delete this stuff here again.
>
> something messy in patch creation?

Yes. It does look messy. But it was intentional to move this code up
in the function.
Will move clk patch before IOCTL addition patch to make it clean.

--
viresh


From arnd at arndb.de  Wed Mar  7 07:15:57 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 7 Mar 2012 12:15:57 +0000
Subject: [GIT PULL] fix to use static declarations for samsung stuff
In-Reply-To: <4F574CAE.6030903@samsung.com>
References: <013b01cce7f3$48c87e30$da597a90$%kim@samsung.com>
 <4F574CAE.6030903@samsung.com>
Message-ID: <201203071215.57828.arnd@arndb.de>

On Wednesday 07 March 2012, Kukjin Kim wrote:
> im wrote:
> > Hi Russell, Arnd and Olof,
> >
> > Please pull following branch which is including fix to use static
> > declarations for samsung stuff.
> >   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> > next/cleanup-use-static
> >
> > I'm not sure it can be sent to upstream for v3.3 but if so, would be better.
> >
> Hi Arnd, Olof,
> 
> I can't see this series in arm-soc yet. If missed, please pull from:
>   http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
> next/cleanup-use-static
> 
> As a note, I rebased it on top of arm-soc/depends/rmk/for-armsoc because 
> this touches same points(dma declaration part).
> 
> If any problems, please kindly let me know.
> 

Sorry, I must have missed this request, I can't remember seeing it before.
The patches all look good, Olof will take care of getting them in.

	Arnd


From festevam at gmail.com  Wed Mar  7 07:18:55 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 7 Mar 2012 09:18:55 -0300
Subject: I.MX35 PDK
In-Reply-To: <4F562C90.6090103@freescale.com>
References: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A26@MEP-EXCH.meprolight.com>
 <4F562C90.6090103@freescale.com>
Message-ID: <CAOMZO5CyGazr1=kLF51W7S7ZpEy2Mg4k2n_ZHnGimSyu2oVcrA@mail.gmail.com>

On 3/6/12, Fabio Estevam <fabio.estevam at freescale.com> wrote:
> Alex Gershgorin wrote:
>> Hi Fabio,
>>
>>
>>
>> How I can get information about accesses to CMOS_RST_B and CSI_PWDN bits
>> of MC9S08DZ60 processor.
>>
>> I need address of this register and bits mapping in this register.

CMOS_RESET: Bit 6 of register 0x1a
CMOS_ENABLE: Bit 1 of register 0x20

After the mx35pdk lcd support patch gets applied I will submit a patch
to adding support to all of the registers/bits definitions for
mc9s08dz60 chip.

Regards,

Fabio Estevam


From govindraj.raja at ti.com  Wed Mar  7 07:19:35 2012
From: govindraj.raja at ti.com (Govindraj.R)
Date: Wed, 7 Mar 2012 17:49:35 +0530
Subject: [PATCH] omap_hwmod: Allow io_ring wakeup configuration for all
 modules.
Message-ID: <1331122775-761-1-git-send-email-govindraj.raja@ti.com>

From: "Govindraj.R" <govindraj.raja at ti.com>

Some modules doesn't have SYSC_HAS_ENAWAKEUP bit available
(ex: usb host uhh module) in absence of this flag
omap_hwmod_enable/disable_wakeup avoids configuring
pad mux wakeup capability.

Configure sysc if SYSC_HAS_ENAWAKEUP is available and for other cases
try enabling/disabling wakeup from mux_pad pins.

Cc: Paul Walmsley <paul at pwsan.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   30 ++++++++++++++++--------------
 1 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index eba6cd3..89582df 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2475,14 +2475,15 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
 	unsigned long flags;
 	u32 v;
 
-	if (!oh->class->sysc ||
-	    !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
-		return -EINVAL;
-
 	spin_lock_irqsave(&oh->_lock, flags);
-	v = oh->_sysc_cache;
-	_enable_wakeup(oh, &v);
-	_write_sysconfig(v, oh);
+
+	if (oh->class->sysc &&
+	    (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
+		v = oh->_sysc_cache;
+		_enable_wakeup(oh, &v);
+		_write_sysconfig(v, oh);
+	}
+
 	_set_idle_ioring_wakeup(oh, true);
 	spin_unlock_irqrestore(&oh->_lock, flags);
 
@@ -2506,14 +2507,15 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
 	unsigned long flags;
 	u32 v;
 
-	if (!oh->class->sysc ||
-	    !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
-		return -EINVAL;
-
 	spin_lock_irqsave(&oh->_lock, flags);
-	v = oh->_sysc_cache;
-	_disable_wakeup(oh, &v);
-	_write_sysconfig(v, oh);
+
+	if (oh->class->sysc ||
+	    (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
+		v = oh->_sysc_cache;
+		_disable_wakeup(oh, &v);
+		_write_sysconfig(v, oh);
+	}
+
 	_set_idle_ioring_wakeup(oh, false);
 	spin_unlock_irqrestore(&oh->_lock, flags);
 
-- 
1.7.5.4



From viresh.linux at gmail.com  Wed Mar  7 07:20:58 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Wed, 7 Mar 2012 04:20:58 -0800
Subject: [PATCH 14/15] watchdog/mpcore_wdt: Add clock framework support
In-Reply-To: <20120307111833.GQ17370@n2100.arm.linux.org.uk>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <9ec7141baa4b1c1a0503893749e7ce0e19bb5029.1331115752.git.viresh.kumar@st.com>
 <20120307111833.GQ17370@n2100.arm.linux.org.uk>
Message-ID: <CAOh2x==z1Mhc5k7qSJ++ix+TPaWcUfCKNdyfnzzZwiGO59Sudg@mail.gmail.com>

On 3/7/12, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> On Wed, Mar 07, 2012 at 03:57:55PM +0530, Viresh Kumar wrote:
>> @@ -156,10 +159,22 @@ static int mpcore_wdt_open(struct inode *inode,
>> struct file *file)

>> +		ret = clk_enable(wdt->clk);
>
> What about preparing the clock?
>

I missed that. Will update prepare/unprepare of clk across driver.

>> +	wdt->clk = clk_get(&pdev->dev, NULL);
>> +	if (IS_ERR(wdt->clk)) {
>> +		dev_warn(&pdev->dev, "Clock not found\n");
>> +		wdt->clk = NULL;
>
> Remove this line.

Actually this was very much intentional, so that i can do
    if (wdt->clk).

Also, this makes more sense as some platform doesn't support clk,
so it is not an error for them if clk_get() fails. And thus the check

    if (wdt->clk)                /* i.e. clock is supported or not */

make more sense than

    if (!IS_ERR(wdt->clk))             /* i.e. there is an error while
getting clock */

from readability point of view. So, i would like to keep it as it is.

>> @@ -399,6 +446,9 @@ static int mpcore_wdt_suspend(struct device *dev)
>>
>>  	if (test_bit(0, &wdt->timer_alive))
>>  		mpcore_wdt_stop(wdt);		/* Turn the WDT off */
>> +
>> +	if (wdt->clk)
>> +		clk_disable(wdt->clk);
>
> Same comments...  And what if the watchdog is not open?  Doesn't this
> disable an already disabled clock?
>

Yes, that'a a BUG. Will fix it.

--
viresh


From peter.ujfalusi at ti.com  Wed Mar  7 07:21:37 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Wed, 07 Mar 2012 14:21:37 +0200
Subject: [PATCH] plat-omap: mcbsp: Configure wakeup in later phase
In-Reply-To: <20120305195032.GO12083@atomide.com>
References: <1323941697-7902-1-git-send-email-peter.ujfalusi@ti.com>
 <20120305195032.GO12083@atomide.com>
Message-ID: <4F5752D1.7030601@ti.com>

On 03/05/2012 09:50 PM, Tony Lindgren wrote:
> Just checking.. I assume this one is already taken care of with your
> other McBSP changes?

Yes it is. I just resent it against the moved McBSP driver for ASoC.

-- 
P?ter


From viresh.linux at gmail.com  Wed Mar  7 07:26:58 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Wed, 7 Mar 2012 04:26:58 -0800
Subject: [PATCH 00/15] watchdog/mpcore: updates & fixes
In-Reply-To: <20120307103414.GA2568@pengutronix.de>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <20120307103414.GA2568@pengutronix.de>
Message-ID: <CAOh2x=n6Xx0r7OsTvYTY9d6V11WgGuruF9D3kGVb8DosqAtatw@mail.gmail.com>

On 3/7/12, Wolfram Sang <w.sang at pengutronix.de> wrote:
>
>> This patchset contains fixes and updates for ARM mpcore watchdog driver.
>
> It probably makes sense to convert this to use the watchdog-core. See
> Documentation/watchdog/convert_drivers_to_kernel_api.txt for some
> guidance.
>

Sorry for not checking that earlier.
Will align my patchset to that.

--
viresh


From linux at arm.linux.org.uk  Wed Mar  7 07:27:32 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 12:27:32 +0000
Subject: [PATCH 14/15] watchdog/mpcore_wdt: Add clock framework support
In-Reply-To: <CAOh2x==z1Mhc5k7qSJ++ix+TPaWcUfCKNdyfnzzZwiGO59Sudg@mail.gmail.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <9ec7141baa4b1c1a0503893749e7ce0e19bb5029.1331115752.git.viresh.kumar@st.com>
 <20120307111833.GQ17370@n2100.arm.linux.org.uk>
 <CAOh2x==z1Mhc5k7qSJ++ix+TPaWcUfCKNdyfnzzZwiGO59Sudg@mail.gmail.com>
Message-ID: <20120307122732.GS17370@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 04:20:58AM -0800, viresh kumar wrote:
> On 3/7/12, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> > On Wed, Mar 07, 2012 at 03:57:55PM +0530, Viresh Kumar wrote:
> >> @@ -156,10 +159,22 @@ static int mpcore_wdt_open(struct inode *inode,
> >> struct file *file)
> 
> >> +		ret = clk_enable(wdt->clk);
> >
> > What about preparing the clock?
> >
> 
> I missed that. Will update prepare/unprepare of clk across driver.
> 
> >> +	wdt->clk = clk_get(&pdev->dev, NULL);
> >> +	if (IS_ERR(wdt->clk)) {
> >> +		dev_warn(&pdev->dev, "Clock not found\n");
> >> +		wdt->clk = NULL;
> >
> > Remove this line.
> 
> Actually this was very much intentional, so that i can do
>     if (wdt->clk).

Drivers have no business interpreting anything but an IS_ERR() return from
clk_get() as invalid.  Everything else is the CLK APIs business, not the
driver's business.  So, to start using NULL as a special case is wrong.



From plagnioj at jcrosoft.com  Wed Mar  7 07:23:07 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 13:23:07 +0100
Subject: [PATCH 2/4 v4] spi/atmel: add DT support
In-Reply-To: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1331122989-14451-2-git-send-email-plagnioj@jcrosoft.com>

The atmel_spi use only gpio for chip select.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: spi-devel-general at lists.sourceforge.net
---
 .../devicetree/bindings/spi/spi_atmel.txt          |    6 +++++
 drivers/spi/spi-atmel.c                            |   21 ++++++++++++++++---
 2 files changed, 23 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/spi/spi_atmel.txt

diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
new file mode 100644
index 0000000..7ec3d8d
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -0,0 +1,6 @@
+Atmel SPI device
+
+Required properties:
+- compatible : should be "atmel,at91rm9200-spi".
+- reg: Address and length of the register set for the device
+- interrupts: Should contain macb interrupt
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 16d6a83..efbc5f8 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -19,6 +19,7 @@
 #include <linux/interrupt.h>
 #include <linux/spi/spi.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 #include <asm/io.h>
 #include <mach/board.h>
@@ -695,7 +696,7 @@ static int atmel_spi_setup(struct spi_device *spi)
 	u32			scbr, csr;
 	unsigned int		bits = spi->bits_per_word;
 	unsigned long		bus_hz;
-	unsigned int		npcs_pin;
+	int			npcs_pin;
 	int			ret;
 
 	as = spi_master_get_devdata(spi->master);
@@ -767,7 +768,9 @@ static int atmel_spi_setup(struct spi_device *spi)
 	csr |= SPI_BF(DLYBCT, 0);
 
 	/* chipselect must have been muxed as GPIO (e.g. in board setup) */
-	npcs_pin = (unsigned int)spi->controller_data;
+	if (!gpio_is_valid(spi->cs_gpio))
+		spi->cs_gpio = (int)spi->controller_data;
+	npcs_pin = spi->cs_gpio;
 	asd = spi->controller_state;
 	if (!asd) {
 		asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
@@ -887,7 +890,7 @@ static void atmel_spi_cleanup(struct spi_device *spi)
 {
 	struct atmel_spi	*as = spi_master_get_devdata(spi->master);
 	struct atmel_spi_device	*asd = spi->controller_state;
-	unsigned		gpio = (unsigned) spi->controller_data;
+	unsigned		gpio = spi->cs_gpio;
 	unsigned long		flags;
 
 	if (!asd)
@@ -938,7 +941,8 @@ static int __devinit atmel_spi_probe(struct platform_device *pdev)
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 
 	master->bus_num = pdev->id;
-	master->num_chipselect = 4;
+	master->dev.of_node = pdev->dev.of_node;
+	master->num_chipselect = master->dev.of_node ? 0 : 4;
 	master->setup = atmel_spi_setup;
 	master->transfer = atmel_spi_transfer;
 	master->cleanup = atmel_spi_cleanup;
@@ -1064,11 +1068,20 @@ static int atmel_spi_resume(struct platform_device *pdev)
 #define	atmel_spi_resume	NULL
 #endif
 
+#if defined(CONFIG_OF)
+static const struct of_device_id atmel_spi_dt_ids[] = {
+	{ .compatible = "atmel,at91rm9200-spi" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
+#endif
 
 static struct platform_driver atmel_spi_driver = {
 	.driver		= {
 		.name	= "atmel_spi",
 		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(atmel_spi_dt_ids),
 	},
 	.suspend	= atmel_spi_suspend,
 	.resume		= atmel_spi_resume,
-- 
1.7.7



From plagnioj at jcrosoft.com  Wed Mar  7 07:23:08 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 13:23:08 +0100
Subject: [PATCH 3/4 v4] ARM: at91: sam9g20 add spi DT support
In-Reply-To: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1331122989-14451-3-git-send-email-plagnioj@jcrosoft.com>

usb_a9g20:
	add mmc spi support

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9g20.dtsi |   18 ++++++++++++++++++
 arch/arm/boot/dts/usb_a9g20.dts    |   13 +++++++++++++
 arch/arm/mach-at91/at91sam9260.c   |    2 ++
 3 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 3cb4226..aef3d5be 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -203,6 +203,24 @@
 				interrupts = <10 4>;
 				status = "disabled";
 			};
+
+			spi0: spi at fffc8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffc8000 0x4000>;
+				interrupts = <12 4>;
+				status = "disabled";
+			};
+
+			spi1: spi at fffcc000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffcc000 0x4000>;
+				interrupts = <13 4>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 390c481..9efaff3 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -46,6 +46,19 @@
 				atmel,vbus-gpio = <&pioC 5 0>;
 				status = "okay";
 			};
+
+			spi1: spi at fffcc000 {
+				cs-gpios = <&pioB 3 0>;
+				status = "okay";
+				mmc-slot at 0 {
+					compatible = "mmc-spi-slot";
+					reg = <0>;
+					gpios = <&pioC 4 0   /* CD */
+						>;
+					voltage-ranges = <3200 3400>;
+					spi-max-frequency = <20000000>;
+				};
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index d1e5750..c6e5d0f 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -217,6 +217,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
 	CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
 	CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
-- 
1.7.7



From plagnioj at jcrosoft.com  Wed Mar  7 07:23:06 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 13:23:06 +0100
Subject: [PATCH 1/4 v4] of_spi: add generic binding support to specify cs gpio
Message-ID: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.com>

This will allow to use gpio for chip select with no modification in the
driver binding

When use the cs-gpios, the gpio number will be passed via the cs_gpio field
and the number of chip select will automatically increased.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: spi-devel-general at lists.sourceforge.net
---
v4:
	use cs_gpio to pass the gpio number

Best Regards,
J.
 Documentation/devicetree/bindings/spi/spi-bus.txt |    6 ++
 drivers/spi/spi.c                                 |   57 +++++++++++++++++++-
 include/linux/spi/spi.h                           |    6 ++
 3 files changed, 66 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
index e782add..c253379 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -12,6 +12,7 @@ The SPI master node requires the following properties:
 - #size-cells     - should be zero.
 - compatible      - name of SPI bus controller following generic names
     		recommended practice.
+- cs-gpios	  - (optional) gpios chip select.
 No other properties are required in the SPI bus node.  It is assumed
 that a driver for an SPI bus device will understand that it is an SPI bus.
 However, the binding does not attempt to define the specific method for
@@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
 chip selects.  Individual drivers can define additional properties to
 support describing the chip select layout.
 
+If cs-gpios is used the number of chip select will automatically increased.
+
 SPI slave nodes must be children of the SPI master node and can
 contain the following properties.
 - reg             - (required) chip select address of device.
@@ -34,6 +37,9 @@ contain the following properties.
 - spi-cs-high     - (optional) Empty property indicating device requires
     		chip select active high
 
+If a gpio chipselect is used for the SPI slave the gpio number will be passed
+via the controller_data
+
 SPI example for an MPC5200 SPI bus:
 	spi at f00 {
 		#address-cells = <1>;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index b2ccdea..c1d0955 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -28,6 +28,7 @@
 #include <linux/mod_devicetable.h>
 #include <linux/spi/spi.h>
 #include <linux/of_spi.h>
+#include <linux/of_gpio.h>
 #include <linux/pm_runtime.h>
 #include <linux/export.h>
 
@@ -322,6 +323,7 @@ struct spi_device *spi_alloc_device(struct spi_master *master)
 	spi->dev.parent = &master->dev;
 	spi->dev.bus = &spi_bus_type;
 	spi->dev.release = spidev_release;
+	spi->cs_gpio = -EINVAL;
 	device_initialize(&spi->dev);
 	return spi;
 }
@@ -339,15 +341,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
 int spi_add_device(struct spi_device *spi)
 {
 	static DEFINE_MUTEX(spi_add_lock);
-	struct device *dev = spi->master->dev.parent;
+	struct spi_master *master = spi->master;
+	struct device *dev = master->dev.parent;
 	struct device *d;
 	int status;
 
 	/* Chipselects are numbered 0..max; validate. */
-	if (spi->chip_select >= spi->master->num_chipselect) {
+	if (spi->chip_select >= master->num_chipselect) {
 		dev_err(dev, "cs%d >= max %d\n",
 			spi->chip_select,
-			spi->master->num_chipselect);
+			master->num_chipselect);
 		return -EINVAL;
 	}
 
@@ -371,6 +374,13 @@ int spi_add_device(struct spi_device *spi)
 		goto done;
 	}
 
+	if (master->num_gpio_cs &&
+	    spi->chip_select >= master->first_gpio_cs) {
+		int num = spi->chip_select - master->first_gpio_cs;
+
+		spi->cs_gpio = master->cs_gpios[num];
+	}
+
 	/* Drivers may modify this initial i/o setup, but will
 	 * normally rely on the device being setup.  Devices
 	 * using SPI_CS_HIGH can't coexist well otherwise...
@@ -561,6 +571,43 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
 }
 EXPORT_SYMBOL_GPL(spi_alloc_master);
 
+#ifdef CONFIG_OF
+static int of_spi_register_master(struct spi_master *master)
+{
+	int nb, i;
+	int *cs;
+	struct device_node *np = master->dev.of_node;
+
+	if (!np)
+		return 0;
+
+	nb = of_gpio_named_count(np, "cs-gpios");
+
+	if (nb < 1)
+		return 0;
+
+	cs = devm_kzalloc(&master->dev, sizeof(int) * nb, GFP_KERNEL);
+	master->cs_gpios = cs;
+
+	if (!master->cs_gpios)
+		return -ENOMEM;
+
+	master->first_gpio_cs = master->num_chipselect;
+	master->num_chipselect += nb;
+	master->num_gpio_cs = nb;
+
+	for (i = 0; i < nb; i++)
+		cs[i] = of_get_named_gpio(np, "cs-gpios", i);
+
+	return 0;
+}
+#else
+static int of_spi_register_master(struct spi_master *master)
+{
+	return 0;
+}
+#endif
+
 /**
  * spi_register_master - register SPI master controller
  * @master: initialized master, originally from spi_alloc_master()
@@ -592,6 +639,10 @@ int spi_register_master(struct spi_master *master)
 	if (!dev)
 		return -ENODEV;
 
+	status = of_spi_register_master(master);
+	if (status)
+		return status;
+
 	/* even if it's just one always-selected device, there must
 	 * be at least one chipselect
 	 */
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 176fce9..7dcf031 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -89,6 +89,7 @@ struct spi_device {
 	void			*controller_state;
 	void			*controller_data;
 	char			modalias[SPI_NAME_SIZE];
+	int			cs_gpio;	/* chip select gpio */
 
 	/*
 	 * likely need more hooks for more protocol options affecting how
@@ -318,6 +319,11 @@ struct spi_master {
 
 	/* called on release() to free memory provided by spi_master */
 	void			(*cleanup)(struct spi_device *spi);
+
+	/* gpio chip select */
+	int			*cs_gpios;
+	int			first_gpio_cs;
+	int			num_gpio_cs;
 };
 
 static inline void *spi_master_get_devdata(struct spi_master *master)
-- 
1.7.7



From plagnioj at jcrosoft.com  Wed Mar  7 07:23:09 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 13:23:09 +0100
Subject: [PATCH 4/4 v4] ARM: at91: sam9g45 add spi DT support
In-Reply-To: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1331122989-14451-4-git-send-email-plagnioj@jcrosoft.com>

at91sam9m10g45ek:
	add dataflash support

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9g45.dtsi     |   18 ++++++++++++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts |   23 +++++++++++++++++++++++
 arch/arm/mach-at91/at91sam9g45.c       |    2 ++
 3 files changed, 43 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 7a685f9..8a11530 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -271,6 +271,24 @@
 					atmel,can-isoc = <1>;
 				};
 			};
+
+			spi0: spi at fffa4000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffa4000 0x4000>;
+				interrupts = <14 4>;
+				status = "disabled";
+			};
+
+			spi1: spi at fffa8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffa8000 0x4000>;
+				interrupts = <15 4>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index b9382e3..2b96ab2 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -51,6 +51,29 @@
 				atmel,vbus-gpio = <&pioB 19 0>;
 				status = "okay";
 			};
+
+			spi0: spi at fffa4000 {
+				cs-gpios = <&pioB 3 0>;
+				status = "okay";
+				flash: at45db321d at 0 {
+					compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
+					reg = <0>;
+					spi-max-frequency = <15000000>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					partition at 0 {
+						label = "U-Boot";
+						reg = <0x0 0x40110>;
+						read-only;
+					};
+
+					partition at 40110 {
+						label = "Kernel";
+						reg = <0x40110 0x3dfef0>;
+					};
+				};
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index da80f0c..06547bf 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -236,6 +236,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
 	CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
-- 
1.7.7



From viresh.linux at gmail.com  Wed Mar  7 07:37:12 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Wed, 7 Mar 2012 04:37:12 -0800
Subject: [PATCH 14/15] watchdog/mpcore_wdt: Add clock framework support
In-Reply-To: <20120307122732.GS17370@n2100.arm.linux.org.uk>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <9ec7141baa4b1c1a0503893749e7ce0e19bb5029.1331115752.git.viresh.kumar@st.com>
 <20120307111833.GQ17370@n2100.arm.linux.org.uk>
 <CAOh2x==z1Mhc5k7qSJ++ix+TPaWcUfCKNdyfnzzZwiGO59Sudg@mail.gmail.com>
 <20120307122732.GS17370@n2100.arm.linux.org.uk>
Message-ID: <CAOh2x=mCMdSVAGXtEg3=P8aJxc5kmk-UqDYeKLGnQZpUYu0DrA@mail.gmail.com>

On 3/7/12, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> Drivers have no business interpreting anything but an IS_ERR() return from
> clk_get() as invalid.  Everything else is the CLK APIs business, not the
> driver's business.  So, to start using NULL as a special case is wrong.

But driver isn't comparing return value of clk_get with NULL (that would have
been wrong) or interpreting its return value in a wrong way.

Instead it is using the same pointer/variable to check if clk_* APIs are
supported or not by making it NULL. And that's a driver convention.
I still believe it is fine.

Thanks for your quick comments.

--
viresh


From linux at arm.linux.org.uk  Wed Mar  7 07:47:51 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 12:47:51 +0000
Subject: [PATCH 14/15] watchdog/mpcore_wdt: Add clock framework support
In-Reply-To: <CAOh2x=mCMdSVAGXtEg3=P8aJxc5kmk-UqDYeKLGnQZpUYu0DrA@mail.gmail.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <9ec7141baa4b1c1a0503893749e7ce0e19bb5029.1331115752.git.viresh.kumar@st.com>
 <20120307111833.GQ17370@n2100.arm.linux.org.uk>
 <CAOh2x==z1Mhc5k7qSJ++ix+TPaWcUfCKNdyfnzzZwiGO59Sudg@mail.gmail.com>
 <20120307122732.GS17370@n2100.arm.linux.org.uk>
 <CAOh2x=mCMdSVAGXtEg3=P8aJxc5kmk-UqDYeKLGnQZpUYu0DrA@mail.gmail.com>
Message-ID: <20120307124751.GU17370@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 04:37:12AM -0800, viresh kumar wrote:
> On 3/7/12, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> > Drivers have no business interpreting anything but an IS_ERR() return from
> > clk_get() as invalid.  Everything else is the CLK APIs business, not the
> > driver's business.  So, to start using NULL as a special case is wrong.
> 
> But driver isn't comparing return value of clk_get with NULL (that would have
> been wrong) or interpreting its return value in a wrong way.

What if clk_get() returned NULL?

Hint: as far as _you_ are concerned as a driver writer, a struct clk is
an opaque cookie.  IS_ERR(clk) means the cookie is invalid.  Everything
else is potentially valid.  You must not interpret anything which is
potentially valid as some kind of special case.

> Instead it is using the same pointer/variable to check if clk_* APIs are
> supported or not by making it NULL. And that's a driver convention.

Bollocks it is.

Plain and simple NAK to this patch until clue is forthcoming.


From w.sang at pengutronix.de  Wed Mar  7 07:48:24 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed, 7 Mar 2012 13:48:24 +0100
Subject: [PATCH 00/15] watchdog/mpcore: updates & fixes
In-Reply-To: <CAOh2x=n6Xx0r7OsTvYTY9d6V11WgGuruF9D3kGVb8DosqAtatw@mail.gmail.com>
References: <cover.1331115751.git.viresh.kumar@st.com>
 <20120307103414.GA2568@pengutronix.de>
 <CAOh2x=n6Xx0r7OsTvYTY9d6V11WgGuruF9D3kGVb8DosqAtatw@mail.gmail.com>
Message-ID: <20120307124824.GD2568@pengutronix.de>

> > It probably makes sense to convert this to use the watchdog-core. See
> > Documentation/watchdog/convert_drivers_to_kernel_api.txt for some
> > guidance.
> >
> 
> Sorry for not checking that earlier.
> Will align my patchset to that.

Cool, thanks!

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From b-cousson at ti.com  Wed Mar  7 07:57:05 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Wed, 7 Mar 2012 13:57:05 +0100
Subject: [PATCH 08/12] gpio/twl: Allocate irq_desc dynamically for
 SPARSE_IRQ support
In-Reply-To: <1330707024-23730-9-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-9-git-send-email-b-cousson@ti.com>
Message-ID: <4F575B21.30909@ti.com>

Hi Grant,

That fix is tightly coupled with the previous twl4030-irq change, so it 
will be good to pulled it with the twl series through MFD if you are OK 
with that?

Care to ack this one and the next one?

Thanks,
Benoit


On 3/2/2012 5:50 PM, Benoit Cousson wrote:
> Do not use the board pdata for irq_base, but allocate them dynamically
> to allow a proper support of SPARSE_IRQ.
>
> Fix an unneeded line wrap.
>
> Signed-off-by: Benoit Cousson<b-cousson at ti.com>
> Acked-by: Felipe Balbi<balbi at ti.com>
> ---
>   drivers/gpio/gpio-twl4030.c |   33 +++++++++++++++++----------------
>   1 files changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
> index 697396c..49e5c6e 100644
> --- a/drivers/gpio/gpio-twl4030.c
> +++ b/drivers/gpio/gpio-twl4030.c
> @@ -395,23 +395,26 @@ static int gpio_twl4030_remove(struct platform_device *pdev);
>   static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
>   {
>   	struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
> -	int ret;
> +	int ret, irq_base;
>
>   	/* maybe setup IRQs */
> -	if (pdata->irq_base) {
> -		if (is_module()) {
> -			dev_err(&pdev->dev,
> -				"can't dispatch IRQs from modules\n");
> -			goto no_irqs;
> -		}
> -		ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO,
> -					pdata->irq_base);
> -		if (ret<  0)
> -			return ret;
> -		WARN_ON(ret != pdata->irq_base);
> -		twl4030_gpio_irq_base = ret;
> +	if (is_module()) {
> +		dev_err(&pdev->dev, "can't dispatch IRQs from modules\n");
> +		goto no_irqs;
> +	}
> +
> +	irq_base = irq_alloc_descs(-1, 0, TWL4030_GPIO_MAX, 0);
> +	if (irq_base<  0) {
> +		dev_err(&pdev->dev, "Failed to alloc irq_descs\n");
> +		return irq_base;
>   	}
>
> +	ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO, irq_base);
> +	if (ret<  0)
> +		return ret;
> +
> +	twl4030_gpio_irq_base = irq_base;
> +
>   no_irqs:
>   	/*
>   	 * NOTE:  boards may waste power if they don't set pullups
> @@ -443,9 +446,7 @@ no_irqs:
>
>   	ret = gpiochip_add(&twl_gpiochip);
>   	if (ret<  0) {
> -		dev_err(&pdev->dev,
> -				"could not register gpiochip, %d\n",
> -				ret);
> +		dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
>   		twl_gpiochip.ngpio = 0;
>   		gpio_twl4030_remove(pdev);
>   	} else if (pdata->setup) {



From veli-pekka.peltola at bluegiga.com  Wed Mar  7 08:09:28 2012
From: veli-pekka.peltola at bluegiga.com (Veli-Pekka Peltola)
Date: Wed,  7 Mar 2012 15:09:28 +0200
Subject: [PATCH v2] mm: module_alloc: check if size is 0
In-Reply-To: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com>
References: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com>
Message-ID: <1331125768-25454-1-git-send-email-veli-pekka.peltola@bluegiga.com>

After commit de7d2b567d040e3b67fe7121945982f14343213d (mm/vmalloc.c: report
more vmalloc failures) users will get a warning if vmalloc_node_range() is
called with size 0. This happens if module's init size equals to 0. This
patch changes ARM, MIPS and x86 module_alloc() to return NULL before calling
vmalloc_node_range() that would also return NULL and print a warning.

Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola at bluegiga.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Ingo Molnar <mingo at redhat.com>
Cc: "H. Peter Anvin" <hpa at zytor.com>
Cc: x86 at kernel.org
---
I found this with ARM but after checking out various implementations of
module_alloc() I thought it would be better to fix all at once.

One way to replicate the warning:
compile kernel with CONFIG_KALLSYMS=n
insmod a module without init, I used usb-common.ko

Changes since v1:
 - changed style as hpa suggested

 arch/arm/kernel/module.c  |    2 ++
 arch/mips/kernel/module.c |    2 ++
 arch/x86/kernel/module.c  |    2 +-
 3 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 1e9be5d..17648e2 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -39,6 +39,8 @@
 #ifdef CONFIG_MMU
 void *module_alloc(unsigned long size)
 {
+	if (!size)
+		return NULL;
 	return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
 				GFP_KERNEL, PAGE_KERNEL_EXEC, -1,
 				__builtin_return_address(0));
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index a5066b1..1a51de1 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -47,6 +47,8 @@ static DEFINE_SPINLOCK(dbe_lock);
 #ifdef MODULE_START
 void *module_alloc(unsigned long size)
 {
+	if (!size)
+		return NULL;
 	return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END,
 				GFP_KERNEL, PAGE_KERNEL, -1,
 				__builtin_return_address(0));
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index 925179f..fd44d69 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -38,7 +38,7 @@
 
 void *module_alloc(unsigned long size)
 {
-	if (PAGE_ALIGN(size) > MODULES_LEN)
+	if (!size || PAGE_ALIGN(size) > MODULES_LEN)
 		return NULL;
 	return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
 				GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL_EXEC,
-- 
1.7.5.4



From jason at lakedaemon.net  Wed Mar  7 08:11:37 2012
From: jason at lakedaemon.net (Jason)
Date: Wed, 7 Mar 2012 08:11:37 -0500
Subject: [RFC 09/14] MV SATA: Add per channel clk/clkdev support.
In-Reply-To: <20120307063858.GA18792@lunn.ch>
References: <20120307063858.GA18792@lunn.ch>
Message-ID: <20120307131137.GY5050@titan.lakedaemon.net>

On Wed, Mar 07, 2012 at 07:38:58AM +0100, Andrew Lunn wrote:
> > Date: Tue, 6 Mar 2012 14:01:39 -0500
> > From: Jason <jason at lakedaemon.net>
> > To: Andrew Lunn <andrew at lunn.ch>
> > Cc: linux-arm-kernel at lists.infradead.org
> > Subject: Re: [RFC 09/14] MV SATA: Add per channel clk/clkdev support.
> > Message-ID: <20120306190139.GW5050 at titan.lakedaemon.net>
> > Content-Type: text/plain; charset=us-ascii
> > 
> > On Tue, Mar 06, 2012 at 07:31:05AM +0100, Andrew Lunn wrote:
> > > The Orion kirkwood chips have a gatable clock per SATA channel. Add
> > 
> > +mv_sata_platform_data *sata_data)
> > >       if (sata_data->n_ports > 1)
> > >               kirkwood_clk_ctrl |= CGC_SATA1;
> > >
> > > +     orion_clkdev_add("0", "sata_mv.0", &clk_sata0);
> > > +     orion_clkdev_add("1", "sata_mv.0", &clk_sata1);
> > > +
> > 
> > This is a problem for devicetree.  With devicetree, neither
> > kirkwood_sata_init(), nor orion_sata_init() are ever called.  The same
> > is true for all the other drivers as well.
> > 
> > Could this be moved into the driver's _probe() function?
> 
> No, this cannot be in the driver. This is setting up the mapping
> between the device name and the clk the device should use. dove,
> orion5x, mv78xx0 need a different clk to kirkwood and this is hidden
> by clkdev, so the driver does not have to care.

Thanks for the clarification.

> BTW: Not all drivers which orion uses are only used by orion. So we
> have to be careful not to add orion specific stuff into some of the
> drivers. This is particularly true for Ethernet and SATA.
> 
> There are two possible solutions to clkdev:
> 
> 1) Add DT bindings for clkdev. I don't know if this is currently
>    supported?

I came to the same conclusion late last night and started poking around.
I didn't see it in any of Mike's patches.

> 2) I can refactor the code. Currently i create the clkdev entries on
>    demand. However i could just create them all just after creating
>    the clocks.

Hmmm, I wouldn't worry about it too much, absent == disabled.  Which is
what I'm thinking for the dt bindings.

> Maybe you can take a look at 1) and see if its possible, while i look
> at refactoring the code.

drivers/clk/of_clk.c ?  I'll start looking at it.

thx,

Jason.


From kgene.kim at samsung.com  Wed Mar  7 08:12:40 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 07 Mar 2012 05:12:40 -0800
Subject: [PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for
 EXYNOS5250
In-Reply-To: <CAOesGMgedngJKRVCYwK=+xRnchXj4StGLTVqvv9BMqVhtM=5RA@mail.gmail.com>
References: <1328981685-8602-1-git-send-email-kgene.kim@samsung.com>	<1328981685-8602-5-git-send-email-kgene.kim@samsung.com>	<CAOesGMhmcnt6LPb9O+3420VgG=PiCnOjzZA3JqsA=4OdHN-R-g@mail.gmail.com>	<00a901ccf084$90460900$b0d21b00$%kim@samsung.com>
 <CAOesGMgedngJKRVCYwK=+xRnchXj4StGLTVqvv9BMqVhtM=5RA@mail.gmail.com>
Message-ID: <4F575EC8.2090205@samsung.com>

On 03/06/12 10:55, Olof Johansson wrote:
> Hi,
>
> On Tue, Feb 21, 2012 at 2:35 AM, Kukjin Kim<kgene.kim at samsung.com>  wrote:
>
>> Yes, as you said, it brakes single zImage for EXYNOS4 + EXYNOS5
>> (mach-exynos). So I'm working on regarding resource for EXYNOS SoCs and I
>> think, it can resolve the problem you said before v3.4 merge window.
>>
>> If any updates, let you know.
>
> Just a friendly reminder; the time is close to running out for staging
> new code for 3.4.
>
Hi Olof,

Thanks for your kindly reminder but I couldn't finish it yet because it 
is required to touch most of samsung stuff, and it's a big change. 
Frankly, I need more time...

So how about sending current exynos5 stuff for now and then sorting out 
single kernel for exynos4 and exynos5 next time? Actually, this exynos5 
arch part is _really_ needed for developing/contribution of drivers on 
exynos5.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Wed Mar  7 08:19:47 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 07 Mar 2012 05:19:47 -0800
Subject: [PATCH] ARM: SAMSUNG: change the name from s3c-sdhci to
 exynos4-sdhci
In-Reply-To: <4F55DE1F.9010405@samsung.com>
References: <4F45D343.6020409@samsung.com>
 <CAJuYYwTh8tVdA0X-TLEU-9O_M0_PmJR=i3WYAQXsaRcPF3MbJA@mail.gmail.com>
 <4F557692.8090102@samsung.com> <4F55DE1F.9010405@samsung.com>
Message-ID: <4F576073.6010001@samsung.com>

On 03/06/12 01:51, Kukjin Kim wrote:
> On 03/05/12 18:29, Jaehoon Chung wrote:
>> Hi Kukjin.
>>
>> Is it merged?
>>
>> Best Regards,
>> Jaehoon Chung
>>
>> On 02/24/2012 06:56 PM, Thomas Abraham wrote:
>>
>>> On 23 February 2012 11:18, Jaehoon Chung<jh80.chung at samsung.com> wrote:
>>>> Thomas Arbrahams's patchset have changed the device name in sdhci-s3c.c
>>>> (mmc: sdhci-s3c: Rework platform data and add device tree support)
>>>> But didn't change the regulator_consumer name.
>>>> So maybe didn't initialize the mmc/sd card for exynos4.
>>>>
>>>> This patch is fixed that (based-on linux-samsung for-next branch)
>>>>
>>>> Signed-off-by: Jaehoon Chung<jh80.chung at samsung.com>
>>>> Signed-off-by: kyungmin Park<kyungmin.park at samsung.com>
>>>> ---
>>>> arch/arm/mach-exynos/mach-nuri.c | 4 ++--
>>>> arch/arm/mach-exynos/mach-universal_c210.c | 2 +-
>>>> 2 files changed, 3 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-exynos/mach-nuri.c
>>>> b/arch/arm/mach-exynos/mach-nuri.c
>>>> index a6b9162..251dd7a 100644
>>>> --- a/arch/arm/mach-exynos/mach-nuri.c
>>>> +++ b/arch/arm/mach-exynos/mach-nuri.c
>>>> @@ -116,7 +116,7 @@ static struct s3c_sdhci_platdata
>>>> nuri_hsmmc0_data __initdata = {
>>>> };
>>>>
>>>> static struct regulator_consumer_supply emmc_supplies[] = {
>>>> - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
>>>> + REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
>>>> REGULATOR_SUPPLY("vmmc", "dw_mmc"),
>>>> };
>>>>
>>>> @@ -415,7 +415,7 @@ static struct regulator_consumer_supply
>>>> __initdata max8997_ldo12_[] = {
>>>> REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
>>>> };
>>>> static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
>>>> - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
>>>> + REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
>>>> };
>>>> static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
>>>> REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
>>>> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c
>>>> b/arch/arm/mach-exynos/mach-universal_c210.c
>>>> index 6017a21..320cb1d 100644
>>>> --- a/arch/arm/mach-exynos/mach-universal_c210.c
>>>> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
>>>> @@ -749,7 +749,7 @@ static struct s3c_sdhci_platdata
>>>> universal_hsmmc0_data __initdata = {
>>>> };
>>>>
>>>> static struct regulator_consumer_supply mmc0_supplies[] = {
>>>> - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
>>>> + REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
>>>> };
>>>>
>>>> static struct regulator_init_data mmc0_fixed_voltage_init_data = {
>>>
>>> Reviewed-by: Thomas Abraham<thomas.abraham at linaro.org>
>
> Looks OK, will apply.
>

(Cc'ed Marek)

Hi Kyungmin, Marek and Jaehoon,

As you know, same patches have been submitted duplicated and this should 
be fixed. Which one would be better to send upstream?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From andrew at lunn.ch  Wed Mar  7 08:21:06 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 7 Mar 2012 14:21:06 +0100
Subject: [RFC 09/14] MV SATA: Add per channel clk/clkdev support.
In-Reply-To: <20120307131137.GY5050@titan.lakedaemon.net>
References: <20120307063858.GA18792@lunn.ch>
 <20120307131137.GY5050@titan.lakedaemon.net>
Message-ID: <20120307132106.GA21349@lunn.ch>

On Wed, Mar 07, 2012 at 08:11:37AM -0500, Jason wrote:
> On Wed, Mar 07, 2012 at 07:38:58AM +0100, Andrew Lunn wrote:
> > > Date: Tue, 6 Mar 2012 14:01:39 -0500
> > > From: Jason <jason at lakedaemon.net>
> > > To: Andrew Lunn <andrew at lunn.ch>
> > > Cc: linux-arm-kernel at lists.infradead.org
> > > Subject: Re: [RFC 09/14] MV SATA: Add per channel clk/clkdev support.
> > > Message-ID: <20120306190139.GW5050 at titan.lakedaemon.net>
> > > Content-Type: text/plain; charset=us-ascii
> > > 
> > > On Tue, Mar 06, 2012 at 07:31:05AM +0100, Andrew Lunn wrote:
> > > > The Orion kirkwood chips have a gatable clock per SATA channel. Add
> > > 
> > > +mv_sata_platform_data *sata_data)
> > > >       if (sata_data->n_ports > 1)
> > > >               kirkwood_clk_ctrl |= CGC_SATA1;
> > > >
> > > > +     orion_clkdev_add("0", "sata_mv.0", &clk_sata0);
> > > > +     orion_clkdev_add("1", "sata_mv.0", &clk_sata1);
> > > > +
> > > 
> > > This is a problem for devicetree.  With devicetree, neither
> > > kirkwood_sata_init(), nor orion_sata_init() are ever called.  The same
> > > is true for all the other drivers as well.
> > > 
> > > Could this be moved into the driver's _probe() function?
> > 
> > No, this cannot be in the driver. This is setting up the mapping
> > between the device name and the clk the device should use. dove,
> > orion5x, mv78xx0 need a different clk to kirkwood and this is hidden
> > by clkdev, so the driver does not have to care.
> 
> Thanks for the clarification.
> 
> > BTW: Not all drivers which orion uses are only used by orion. So we
> > have to be careful not to add orion specific stuff into some of the
> > drivers. This is particularly true for Ethernet and SATA.
> > 
> > There are two possible solutions to clkdev:
> > 
> > 1) Add DT bindings for clkdev. I don't know if this is currently
> >    supported?
> 
> I came to the same conclusion late last night and started poking around.
> I didn't see it in any of Mike's patches.

You are missing up clk and clkdev. Mike's patches are for clk. You
need clkdev bindings.

> > 2) I can refactor the code. Currently i create the clkdev entries on
> >    demand. However i could just create them all just after creating
> >    the clocks.

> drivers/clk/of_clk.c ?  I'll start looking at it.

drivers/clk/of_clkdev.c, or maybe drivers/of/of_clkdev.c. You should
probably run this by Grant before investing too much effort. It might
be a stupid idea...

Also, most of the refactoring is done. Needs some testing and then i
can send RFCv2 patches.

    Andrew


From paul.liu at linaro.org  Wed Mar  7 08:24:18 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Wed,  7 Mar 2012 21:24:18 +0800
Subject: [PATCH v9] Regulator: Add Anatop regulator driver
Message-ID: <1331126658-26926-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.

Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Liam Girdwood <lrg at ti.com>
Cc: Samuel Ortiz <sameo at linux.intel.com>
---
 .../bindings/regulator/anatop-regulator.txt        |   28 +++
 drivers/regulator/Kconfig                          |    8 +
 drivers/regulator/Makefile                         |    1 +
 drivers/regulator/anatop-regulator.c               |  231 ++++++++++++++++++++
 4 files changed, 268 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.txt
 create mode 100644 drivers/regulator/anatop-regulator.c

diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
new file mode 100644
index 0000000..500463e
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -0,0 +1,28 @@
+Anatop Voltage regulators
+
+Required properties:
+- compatible: Must be "fsl,anatop-regulator"
+- vol-bit-shift: Bit shift for the register
+- vol-bit-width: Number of bits used in the register
+- min-bit-val: Minimum value of this register
+- min-voltage: Minimum voltage of this regulator
+- max-voltage: Maximum voltage of this regulator
+
+Any property defined as part of the core regulator
+binding, defined in regulator.txt, can also be used.
+
+Example:
+
+	reg_vddpu: regulator-vddpu at 140 {
+		compatible = "fsl,anatop-regulator";
+		regulator-name = "vddpu";
+		regulator-min-microvolt = <725000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-always-on;
+		reg = <0x140>;
+		vol-bit-shift = <9>;
+		vol-bit-width = <5>;
+		min-bit-val = <1>;
+		min-voltage = <725000>;
+		max-voltage = <1300000>;
+	};
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 7a61b17..5366991 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -335,5 +335,13 @@ config REGULATOR_AAT2870
 	  If you have a AnalogicTech AAT2870 say Y to enable the
 	  regulator driver.
 
+config REGULATOR_ANATOP
+	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
+	depends on MFD_ANATOP
+	help
+	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
+	  regulators. It is recommended that this option be
+	  enabled on i.MX6 platform.
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 503bac8..8440871 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -48,5 +48,6 @@ obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
 obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
 obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
 obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
+obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
new file mode 100644
index 0000000..1e20690
--- /dev/null
+++ b/drivers/regulator/anatop-regulator.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+
+struct anatop_regulator {
+	const char *name;
+	u32 control_reg;
+	struct anatop *mfd;
+	int vol_bit_shift;
+	int vol_bit_width;
+	int min_bit_val;
+	int min_voltage;
+	int max_voltage;
+	struct regulator_desc rdesc;
+	struct regulator_init_data *initdata;
+};
+
+static int anatop_set_voltage(struct regulator_dev *reg, int min_uV,
+				  int max_uV, unsigned *selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	u32 val, sel;
+	int uv;
+
+	uv = min_uV;
+	dev_dbg(&reg->dev, "%s: uv %d, min %d, max %d\n", __func__,
+		uv, anatop_reg->min_voltage,
+		anatop_reg->max_voltage);
+
+	if (uv < anatop_reg->min_voltage) {
+		if (max_uV > anatop_reg->min_voltage)
+			uv = anatop_reg->min_voltage;
+		else
+			return -EINVAL;
+	}
+
+	if (anatop_reg->control_reg) {
+		sel = (uv - anatop_reg->min_voltage) / 25000;
+		if (sel * 25000 + anatop_reg->min_voltage
+		    > anatop_reg->max_voltage)
+			return -EINVAL;
+		val = anatop_reg->min_bit_val + sel;
+		*selector = sel;
+		dev_dbg(&reg->dev, "%s: calculated val %d\n", __func__, val);
+		anatop_set_bits(anatop_reg->mfd,
+				anatop_reg->control_reg,
+				anatop_reg->vol_bit_shift,
+				anatop_reg->vol_bit_width,
+				val);
+		return 0;
+	} else {
+		return -ENOTSUPP;
+	}
+}
+
+static int anatop_get_voltage_sel(struct regulator_dev *reg)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int selector;
+
+	if (anatop_reg->control_reg) {
+		u32 val = anatop_get_bits(anatop_reg->mfd,
+					  anatop_reg->control_reg,
+					  anatop_reg->vol_bit_shift,
+					  anatop_reg->vol_bit_width);
+		selector = val - anatop_reg->min_bit_val;
+		return selector;
+	} else {
+		return -ENOTSUPP;
+	}
+}
+
+static int anatop_list_voltage(struct regulator_dev *reg, unsigned selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int uv;
+
+	uv = anatop_reg->min_voltage + selector * 25000;
+	dev_dbg(&reg->dev, "vddio = %d, selector = %u\n", uv, selector);
+
+	return uv;
+}
+
+static struct regulator_ops anatop_rops = {
+	.set_voltage     = anatop_set_voltage,
+	.get_voltage_sel = anatop_get_voltage_sel,
+	.list_voltage    = anatop_list_voltage,
+};
+
+static int __devinit anatop_regulator_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct regulator_desc *rdesc;
+	struct regulator_dev *rdev;
+	struct anatop_regulator *sreg;
+	struct regulator_init_data *initdata;
+	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
+	int ret = 0;
+
+	initdata = of_get_regulator_init_data(dev, np);
+	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
+	if (!sreg)
+		return -ENOMEM;
+	sreg->initdata = initdata;
+	sreg->name = kstrdup(of_get_property(np, "regulator-name", NULL),
+			     GFP_KERNEL);
+	rdesc = &sreg->rdesc;
+	memset(rdesc, 0, sizeof(*rdesc));
+	rdesc->name = sreg->name;
+	rdesc->ops = &anatop_rops;
+	rdesc->type = REGULATOR_VOLTAGE;
+	rdesc->owner = THIS_MODULE;
+	sreg->mfd = anatopmfd;
+	if (of_property_read_u32(np, "reg", &sreg->control_reg)) {
+		dev_err(&pdev->dev, "no reg property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "vol-bit-width", &sreg->vol_bit_width)) {
+		dev_err(&pdev->dev, "no vol-bit-width property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "vol-bit-shift", &sreg->vol_bit_shift)) {
+		dev_err(&pdev->dev, "no vol-bit-shift property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "min-bit-val", &sreg->min_bit_val)) {
+		dev_err(&pdev->dev, "no min-bit-val property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "min-voltage", &sreg->min_voltage)) {
+		dev_err(&pdev->dev, "no min-voltage property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "max-voltage", &sreg->max_voltage)) {
+		dev_err(&pdev->dev, "no max-voltage property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+
+	/* register regulator */
+	rdev = regulator_register(rdesc, &pdev->dev,
+				  initdata, sreg, pdev->dev.of_node);
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			rdesc->name);
+		ret = PTR_ERR(rdev);
+		goto anatop_probe_end;
+	}
+
+	platform_set_drvdata(pdev, rdev);
+
+anatop_probe_end:
+	if (ret != 0 && sreg->name)
+		kfree(sreg->name);
+	return ret;
+}
+
+static int __devexit anatop_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
+	kfree(sreg->name);
+	regulator_unregister(rdev);
+	return 0;
+}
+
+static struct of_device_id __devinitdata of_anatop_regulator_match_tbl[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ /* end */ }
+};
+
+static struct platform_driver anatop_regulator = {
+	.driver = {
+		.name	= "anatop_regulator",
+		.owner  = THIS_MODULE,
+		.of_match_table = of_anatop_regulator_match_tbl,
+	},
+	.probe	= anatop_regulator_probe,
+	.remove	= anatop_regulator_remove,
+};
+
+static int __init anatop_regulator_init(void)
+{
+	return platform_driver_register(&anatop_regulator);
+}
+postcore_initcall(anatop_regulator_init);
+
+static void __exit anatop_regulator_exit(void)
+{
+	platform_driver_unregister(&anatop_regulator);
+}
+module_exit(anatop_regulator_exit);
+
+MODULE_AUTHOR("Nancy Chen <Nancy.Chen at freescale.com>, "
+	      "Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP Regulator driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.1



From plagnioj at jcrosoft.com  Wed Mar  7 08:22:25 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 14:22:25 +0100
Subject: [PATCH v9] Regulator: Add Anatop regulator driver
In-Reply-To: <1331126658-26926-1-git-send-email-paul.liu@linaro.org>
References: <1331126658-26926-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120307132225.GB17745@game.jcrosoft.org>

On 21:24 Wed 07 Mar     , Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is an integrated regulator inside i.MX6 SoC.
> There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
> And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
> This patch adds the Anatop regulator driver.
> 
> Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Acked-by: Shawn Guo <shawn.guo at linaro.org>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Liam Girdwood <lrg at ti.com>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> ---
>  .../bindings/regulator/anatop-regulator.txt        |   28 +++
>  drivers/regulator/Kconfig                          |    8 +
>  drivers/regulator/Makefile                         |    1 +
>  drivers/regulator/anatop-regulator.c               |  231 ++++++++++++++++++++
>  4 files changed, 268 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.txt
>  create mode 100644 drivers/regulator/anatop-regulator.c
> 
> diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
> new file mode 100644
> index 0000000..500463e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
> @@ -0,0 +1,28 @@
> +Anatop Voltage regulators
> +
> +Required properties:
> +- compatible: Must be "fsl,anatop-regulator"
> +- vol-bit-shift: Bit shift for the register
> +- vol-bit-width: Number of bits used in the register
> +- min-bit-val: Minimum value of this register
> +- min-voltage: Minimum voltage of this regulator
> +- max-voltage: Maximum voltage of this regulator
specific properites need to be prefix by the vendor

Best Regards,
J.


From robherring2 at gmail.com  Wed Mar  7 08:43:30 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 07 Mar 2012 07:43:30 -0600
Subject: [PULL] of nand generic binding
In-Reply-To: <20120307082945.GJ21255@game.jcrosoft.org>
References: <20120217155707.GR1214@game.jcrosoft.org>
 <20120229152534.GH3318@game.jcrosoft.org>
 <20120307082945.GJ21255@game.jcrosoft.org>
Message-ID: <4F576602.8020808@gmail.com>

On 03/07/2012 02:29 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 16:25 Wed 29 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 16:57 Fri 17 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> HI,
>>>
>>> 	please find attached the generic binding for the MTD nand
>>>
>>> 	This will add boolean and nand helpers
>> is it ok?
> I need this for 3.4
> 
> will you apply it or can I apply it via AT91

Looks fine to me and Grant acked it, so go ahead and take with your at91
branch.

Rob

> 
> Best Regards,
> J.
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss



From broonie at opensource.wolfsonmicro.com  Wed Mar  7 08:45:52 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 7 Mar 2012 13:45:52 +0000
Subject: [PATCH v9] Regulator: Add Anatop regulator driver
In-Reply-To: <20120307132225.GB17745@game.jcrosoft.org>
References: <1331126658-26926-1-git-send-email-paul.liu@linaro.org>
 <20120307132225.GB17745@game.jcrosoft.org>
Message-ID: <20120307134551.GL3107@opensource.wolfsonmicro.com>

On Wed, Mar 07, 2012 at 02:22:25PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:

> > +- compatible: Must be "fsl,anatop-regulator"
> > +- vol-bit-shift: Bit shift for the register
> > +- vol-bit-width: Number of bits used in the register
> > +- min-bit-val: Minimum value of this register
> > +- min-voltage: Minimum voltage of this regulator
> > +- max-voltage: Maximum voltage of this regulator

> specific properites need to be prefix by the vendor

This really doesn't seem at all sane for a device which is already
vendor specific, it's just noise in the bindings.
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From vinod.koul at intel.com  Wed Mar  7 08:54:26 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Wed, 07 Mar 2012 19:24:26 +0530
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <1331128466.24656.421.camel@vkoul-udesk3>

On Tue, 2012-03-06 at 22:33 +0000, Russell King - ARM Linux wrote:
> [v2 - more or less same description.  Including lakml in cc for the full
> set]
> 
> This patch series cleans up the handling of cookies in DMA engine drivers.
> This is done by providing a set of inline library functions for common
> tasks:
> 
> - moving the 'last completed cookie' into struct dma_chan - everyone
>   has this in their driver private channel data structure
> 
> - consolidate allocation of cookies to DMA descriptors
> 
> - common way to update 'last completed cookie' value
> 
> - standard way to implement tx_status callback and update the residue
> 
> - consolidate initialization of cookies
> 
> - update implementations differing from the majority of DMA engine drivers
>   to behave the same as the majority implementation in respect of cookies
> 
> What this means is that we get to the point where all DMA engine drivers
> will hand out cookie value '2' as the first, and incrementing cookie
> values up to INT_MAX, returning to cookie '1' as the next cookie.
> 
> Think of this patch series as round 1...  I am hoping over time that more
> code can be consolidated between the DMA engine drivers and end up with a
> consistent way to handle various common themes in DMA engine hardware
> (like physical channel<->peripheral request signal selection.)
Thanks Russell,

I have tested this on atom today, and as expected works flawlessly :)
After all acks, I can merge or these can go thru your tree with my Ack.
Either way is okay.

I applied the v2 on a branch and also rebased on top of slave-dma.next.
There were few conflicts in imx-dma.c. Sacha, Javier, pls see that merge
is right.

This branch (rmk_cookie_fixes2_rebased) is not yet pushed, as I am not
able to connect to infradead.org, should be done when server is back.



-- 
~Vinod



From m.szyprowski at samsung.com  Wed Mar  7 09:01:41 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 07 Mar 2012 15:01:41 +0100
Subject: [PATCH] ARM: SAMSUNG: change the name from s3c-sdhci to
 exynos4-sdhci
In-Reply-To: <4F576073.6010001@samsung.com>
References: <4F45D343.6020409@samsung.com>
 <CAJuYYwTh8tVdA0X-TLEU-9O_M0_PmJR=i3WYAQXsaRcPF3MbJA@mail.gmail.com>
 <4F557692.8090102@samsung.com> <4F55DE1F.9010405@samsung.com>
 <4F576073.6010001@samsung.com>
Message-ID: <00db01ccfc6a$d34c2ee0$79e48ca0$%szyprowski@samsung.com>

Hello,

On Wednesday, March 07, 2012 2:20 PM Kukjin Kim wrote:

> On 03/06/12 01:51, Kukjin Kim wrote:
> > On 03/05/12 18:29, Jaehoon Chung wrote:
> >> Hi Kukjin.
> >>
> >> Is it merged?
> >>
> >> Best Regards,
> >> Jaehoon Chung
> >>
> >> On 02/24/2012 06:56 PM, Thomas Abraham wrote:
> >>
> >>> On 23 February 2012 11:18, Jaehoon Chung<jh80.chung at samsung.com> wrote:
> >>>> Thomas Arbrahams's patchset have changed the device name in sdhci-s3c.c
> >>>> (mmc: sdhci-s3c: Rework platform data and add device tree support)
> >>>> But didn't change the regulator_consumer name.
> >>>> So maybe didn't initialize the mmc/sd card for exynos4.
> >>>>
> >>>> This patch is fixed that (based-on linux-samsung for-next branch)
> >>>>
> >>>> Signed-off-by: Jaehoon Chung<jh80.chung at samsung.com>
> >>>> Signed-off-by: kyungmin Park<kyungmin.park at samsung.com>
> >>>> ---
> >>>> arch/arm/mach-exynos/mach-nuri.c | 4 ++--
> >>>> arch/arm/mach-exynos/mach-universal_c210.c | 2 +-
> >>>> 2 files changed, 3 insertions(+), 3 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm/mach-exynos/mach-nuri.c
> >>>> b/arch/arm/mach-exynos/mach-nuri.c
> >>>> index a6b9162..251dd7a 100644
> >>>> --- a/arch/arm/mach-exynos/mach-nuri.c
> >>>> +++ b/arch/arm/mach-exynos/mach-nuri.c
> >>>> @@ -116,7 +116,7 @@ static struct s3c_sdhci_platdata
> >>>> nuri_hsmmc0_data __initdata = {
> >>>> };
> >>>>
> >>>> static struct regulator_consumer_supply emmc_supplies[] = {
> >>>> - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
> >>>> + REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
> >>>> REGULATOR_SUPPLY("vmmc", "dw_mmc"),
> >>>> };
> >>>>
> >>>> @@ -415,7 +415,7 @@ static struct regulator_consumer_supply
> >>>> __initdata max8997_ldo12_[] = {
> >>>> REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
> >>>> };
> >>>> static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
> >>>> - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
> >>>> + REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
> >>>> };
> >>>> static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
> >>>> REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
> >>>> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c
> >>>> b/arch/arm/mach-exynos/mach-universal_c210.c
> >>>> index 6017a21..320cb1d 100644
> >>>> --- a/arch/arm/mach-exynos/mach-universal_c210.c
> >>>> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
> >>>> @@ -749,7 +749,7 @@ static struct s3c_sdhci_platdata
> >>>> universal_hsmmc0_data __initdata = {
> >>>> };
> >>>>
> >>>> static struct regulator_consumer_supply mmc0_supplies[] = {
> >>>> - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
> >>>> + REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
> >>>> };
> >>>>
> >>>> static struct regulator_init_data mmc0_fixed_voltage_init_data = {
> >>>
> >>> Reviewed-by: Thomas Abraham<thomas.abraham at linaro.org>
> >
> > Looks OK, will apply.
> >
> 
> (Cc'ed Marek)
> 
> Hi Kyungmin, Marek and Jaehoon,
> 
> As you know, same patches have been submitted duplicated and this should
> be fixed. Which one would be better to send upstream?

For me it doesn't matter, I just need this fix to get merged, because otherwise
the Universal C210 and Nuri boards are dysfunctional. 

You can select the one prepared by Jaehoon if You like.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From alexg at meprolight.com  Wed Mar  7 09:05:29 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Wed, 7 Mar 2012 16:05:29 +0200
Subject: I.MX35 PDK
In-Reply-To: <CAOMZO5CyGazr1=kLF51W7S7ZpEy2Mg4k2n_ZHnGimSyu2oVcrA@mail.gmail.com>
References: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A26@MEP-EXCH.meprolight.com>
 <4F562C90.6090103@freescale.com>,
 <CAOMZO5CyGazr1=kLF51W7S7ZpEy2Mg4k2n_ZHnGimSyu2oVcrA@mail.gmail.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D890F@MEP-EXCH.meprolight.com>

Thanks Fabio,

 
________________________________________
From: Fabio Estevam [festevam at gmail.com]
Sent: Wednesday, March 07, 2012 2:18 PM
To: Fabio Estevam
Cc: Alex Gershgorin; linux-arm-kernel at lists.infradead.org; kernel at pengutronix.de
Subject: Re: I.MX35 PDK

On 3/6/12, Fabio Estevam <fabio.estevam at freescale.com> wrote:
> Alex Gershgorin wrote:
>> Hi Fabio,
>>
>>
>>
>> How I can get information about accesses to CMOS_RST_B and CSI_PWDN bits
>> of MC9S08DZ60 processor.
>>
>> I need address of this register and bits mapping in this register.

CMOS_RESET: Bit 6 of register 0x1a
CMOS_ENABLE: Bit 1 of register 0x20

>>>After the mx35pdk lcd support patch gets applied I will submit a patch
>>>to adding support to all of the registers/bits definitions for
>>>>mc9s08dz60 chip.

I use a barebox boot loader which supported mc9s08dz60 driver :-)
Currently this is working, without  driver in the Linux kernel, but I have other problem:
In my I.MX35 pdk personality board on connector CN14 I measure signals CMOS_RST = 1, CSI_PWDN = 0 and all of the correct voltages,
in spite of this I get from ov2640 driver error 
Here Linux Kernel boot message:  

"Linux video capture interface: v2.00
soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
mx3-camera mx3-camera.0: MX3 Camera driver attached to camera 0
ov2640 0-0030: Product ID error fb:fb" 

I cannot understand what the problem is, if someone tested this?

Regards,
Alex Gershgorin





 


From govindraj.raja at ti.com  Wed Mar  7 09:10:07 2012
From: govindraj.raja at ti.com (Raja, Govindraj)
Date: Wed, 7 Mar 2012 19:40:07 +0530
Subject: [PATCH] omap_hwmod: Allow io_ring wakeup configuration for all
 modules.
In-Reply-To: <1331122775-761-1-git-send-email-govindraj.raja@ti.com>
References: <1331122775-761-1-git-send-email-govindraj.raja@ti.com>
Message-ID: <CAMrsUdJq8J8dTnKcZmXgMucDX=dNXgR+9xFhYOdHvNDuw_=4Mw@mail.gmail.com>

On Wed, Mar 7, 2012 at 5:49 PM, Govindraj.R <govindraj.raja at ti.com> wrote:
>
> From: "Govindraj.R" <govindraj.raja at ti.com>
>
> Some modules doesn't have SYSC_HAS_ENAWAKEUP bit available
> (ex: usb host uhh module) in absence of this flag
> omap_hwmod_enable/disable_wakeup avoids configuring
> pad mux wakeup capability.
>
> Configure sysc if SYSC_HAS_ENAWAKEUP is available and for other cases
> try enabling/disabling wakeup from mux_pad pins.
>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
> ---
> ?arch/arm/mach-omap2/omap_hwmod.c | ? 30 ++++++++++++++++--------------
> ?1 files changed, 16 insertions(+), 14 deletions(-)

[...]

>
> @@ -2506,14 +2507,15 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
> ? ? ? ?unsigned long flags;
> ? ? ? ?u32 v;
>
> - ? ? ? if (!oh->class->sysc ||
> - ? ? ? ? ? !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
> - ? ? ? ? ? ? ? return -EINVAL;
> -
> ? ? ? ?spin_lock_irqsave(&oh->_lock, flags);
> - ? ? ? v = oh->_sysc_cache;
> - ? ? ? _disable_wakeup(oh, &v);
> - ? ? ? _write_sysconfig(v, oh);
> +
> + ? ? ? if (oh->class->sysc ||
> + ? ? ? ? ? (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {


This condition check should have been _and_ (&&)
sorry for the typo,

Here [1] is the updated patch.

--
Thanks,
Govindraj.R

[1]:

>From b3aa1dac5909cad1b959f5b97bbf408b2f974060 Mon Sep 17 00:00:00 2001
From: "Govindraj.R" <govindraj.raja at ti.com>
Date: Wed, 7 Mar 2012 17:14:02 +0530
Subject: [PATCH] omap_hwmod: Allow io_ring wakeup configuration for all
 modules.

Some modules doesn't have SYSC_HAS_ENAWAKEUP bit available
(ex: usb host uhh module) in absence of this flag
omap_hwmod_enable/disable_wakeup avoids configuring
pad mux wakeup capability.

Configure sysc if SYSC_HAS_ENAWAKEUP is available and for other cases
try enabling/disabling wakeup from mux_pad pins.

Cc: Paul Walmsley <paul at pwsan.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   30 ++++++++++++++++--------------
 1 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index eba6cd3..9605fad 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2475,14 +2475,15 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
 	unsigned long flags;
 	u32 v;

-	if (!oh->class->sysc ||
-	    !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
-		return -EINVAL;
-
 	spin_lock_irqsave(&oh->_lock, flags);
-	v = oh->_sysc_cache;
-	_enable_wakeup(oh, &v);
-	_write_sysconfig(v, oh);
+
+	if (oh->class->sysc &&
+	    (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
+		v = oh->_sysc_cache;
+		_enable_wakeup(oh, &v);
+		_write_sysconfig(v, oh);
+	}
+
 	_set_idle_ioring_wakeup(oh, true);
 	spin_unlock_irqrestore(&oh->_lock, flags);

@@ -2506,14 +2507,15 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
 	unsigned long flags;
 	u32 v;

-	if (!oh->class->sysc ||
-	    !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
-		return -EINVAL;
-
 	spin_lock_irqsave(&oh->_lock, flags);
-	v = oh->_sysc_cache;
-	_disable_wakeup(oh, &v);
-	_write_sysconfig(v, oh);
+
+	if (oh->class->sysc &&
+	    (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
+		v = oh->_sysc_cache;
+		_disable_wakeup(oh, &v);
+		_write_sysconfig(v, oh);
+	}
+
 	_set_idle_ioring_wakeup(oh, false);
 	spin_unlock_irqrestore(&oh->_lock, flags);

-- 
1.7.5.4
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From jwboyer at gmail.com  Wed Mar  7 09:15:59 2012
From: jwboyer at gmail.com (Josh Boyer)
Date: Wed, 7 Mar 2012 09:15:59 -0500
Subject: [PATCH 1/3] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <CA+5PVA7PCow=Z7TpPtQYp3ye6uKFSp3XsdH75Pe9BRu9Vyy21g@mail.gmail.com>

On Tue, Mar 6, 2012 at 7:30 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
> to avoid duplication.
>
> All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
> parameterized version in Makefile.lib to avoid duplication.
>
> The centralized cmd_uimage definition will allow the future introduction
> of a centralized Kconfig option to make cmd_uimage use -T kernel_noload
> rather than -T kernel.
>
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> ---
> NOTE: I have not tested this patch in any way at all for architectures
> other than ARM.
>
> ?arch/arm/boot/Makefile ? ? ? ? ?| ? 23 +++++++++--------------
> ?arch/avr32/boot/images/Makefile | ? ?9 +++------
> ?arch/blackfin/boot/Makefile ? ? | ? 19 ++++++++-----------
> ?arch/microblaze/boot/Makefile ? | ? 10 +++-------
> ?arch/sh/boot/Makefile ? ? ? ? ? | ? ?8 ++------
> ?arch/sparc/boot/Makefile ? ? ? ?| ? ?9 +++------
> ?arch/unicore32/boot/Makefile ? ?| ? 12 ++----------
> ?scripts/Makefile.lib ? ? ? ? ? ?| ? 24 ++++++++++++++++++++++++
> ?8 files changed, 54 insertions(+), 60 deletions(-)

Is there a reason you skipped powerpc?

josh


From festevam at gmail.com  Wed Mar  7 09:17:55 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 7 Mar 2012 11:17:55 -0300
Subject: I.MX35 PDK
In-Reply-To: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D890F@MEP-EXCH.meprolight.com>
References: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A26@MEP-EXCH.meprolight.com>
 <4F562C90.6090103@freescale.com>
 <CAOMZO5CyGazr1=kLF51W7S7ZpEy2Mg4k2n_ZHnGimSyu2oVcrA@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D890F@MEP-EXCH.meprolight.com>
Message-ID: <CAOMZO5DnP7+zupy9vwBPS0+2XtKM1+nLbwCqBzuCqEG5OWbZRQ@mail.gmail.com>

On 3/7/12, Alex Gershgorin <alexg at meprolight.com> wrote:

> in spite of this I get from ov2640 driver error
> Here Linux Kernel boot message:
>
> "Linux video capture interface: v2.00
> soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
> mx3-camera mx3-camera.0: MX3 Camera driver attached to camera 0
> ov2640 0-0030: Product ID error fb:fb"
>
> I cannot understand what the problem is, if someone tested this?

Looks like a I2C issue.

Check the I2C1 pad settings in the mainline kernel.

On FSL kernel we have:

#define PAD_CONFIG (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain)

	switch (i2c_num) {
	case 0:
		mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
		mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);

		mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, PAD_CONFIG);
		mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, PAD_CONFIG);

Also check if you are getting the proper voltage levels at the I2C1 lines.

Good luck!


From kmpark at infradead.org  Wed Mar  7 09:20:34 2012
From: kmpark at infradead.org (Kyungmin Park)
Date: Wed, 7 Mar 2012 23:20:34 +0900
Subject: [PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for
 EXYNOS5250
In-Reply-To: <4F575EC8.2090205@samsung.com>
References: <1328981685-8602-1-git-send-email-kgene.kim@samsung.com>
 <1328981685-8602-5-git-send-email-kgene.kim@samsung.com>
 <CAOesGMhmcnt6LPb9O+3420VgG=PiCnOjzZA3JqsA=4OdHN-R-g@mail.gmail.com>
 <00a901ccf084$90460900$b0d21b00$%kim@samsung.com>
 <CAOesGMgedngJKRVCYwK=+xRnchXj4StGLTVqvv9BMqVhtM=5RA@mail.gmail.com>
 <4F575EC8.2090205@samsung.com>
Message-ID: <CAH9JG2VhCT6psHa3nhMCeA6dF12r1EuAaXMHxca44dOV1T5nbg@mail.gmail.com>

On Wed, Mar 7, 2012 at 10:12 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> On 03/06/12 10:55, Olof Johansson wrote:
>>
>> Hi,
>>
>> On Tue, Feb 21, 2012 at 2:35 AM, Kukjin Kim<kgene.kim at samsung.com> ?wrote:
>>
>>> Yes, as you said, it brakes single zImage for EXYNOS4 + EXYNOS5
>>> (mach-exynos). So I'm working on regarding resource for EXYNOS SoCs and I
>>> think, it can resolve the problem you said before v3.4 merge window.
>>>
>>> If any updates, let you know.
>>
>>
>> Just a friendly reminder; the time is close to running out for staging
>> new code for 3.4.
>>
> Hi Olof,
>
> Thanks for your kindly reminder but I couldn't finish it yet because it is
> required to touch most of samsung stuff, and it's a big change. Frankly, I
> need more time...
>
> So how about sending current exynos5 stuff for now and then sorting out
> single kernel for exynos4 and exynos5 next time? Actually, this exynos5 arch
> part is _really_ needed for developing/contribution of drivers on exynos5.
No,

I heard too many times. "we have plan to support ..." but I didn't see
any progress.
it's general rules. you should fix it correctly and merged correctly
instead of "not now"

Thank you,
Kyungmin Park
>
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html


From jm at lentin.co.uk  Wed Mar  7 09:25:10 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Wed, 7 Mar 2012 14:25:10 +0000 (GMT)
Subject: [PATCH] mach-kirkwood: Support for DLink DNS-320 & DNS-325 NAS
In-Reply-To: <20120301203917.GB11986@titan.lakedaemon.net>
References: <alpine.DEB.2.02.1202121424080.16803@bunsen.wrottesley.wormnet.eu>
 <201202291440.10418.arnd@arndb.de>
 <20120301203917.GB11986@titan.lakedaemon.net>
Message-ID: <alpine.DEB.2.00.1203071332030.23719@marmot.wormnet.eu>

On Thu, 1 Mar 2012, Jason wrote:

> On Wed, Feb 29, 2012 at 02:40:10PM +0000, Arnd Bergmann wrote:
>> On Sunday 12 February 2012, Jamie Lentin wrote:
>>> This patch adds support for the D-Link DNS-320 & DNS-325 NAS. Kirkwood-based
>>> successors to the DNS-323.
>>>
>>> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
>>> ---
>>> My previous patch supported just the DNS-325, the DNS-320 is a very similar
>>> device and so I've combined the support for both devices into one board support
>>> file. The main difference with the DNS-320 is that the temperature sensor
>>> is accessed via ttyS1 instead of I2C (I have a userland script to do this).
>>>
>>> I appreciate board support files like this are old hat and should be using
>>> device tree instead. If I should be focusing on that instead of getting this
>>> merged, some pointers would be very useful.
>>
>> Hi Jamie,
>>
>> I just saw this patch going through the mailing list and noticed that you
>> had sent it out another time before without getting any reply.
>>
>> I'm sorry that you did not get any feedback on this. Jason Cooper had a
>> similar patch and he ended up a bit more fortunate than you, since he
>> got support for the kirkwood based "dreamplug" into the arm-soc tree
>> and is working on converting that to device tree now.
>>
>> I would suggest that you two team up and put DNS-32x support into the new
>> common board-dt.c file as well.
>
> Jamie,
>
> Take a look at the dreamplug initial support patch series, latest here
> [1].  Make a kirkwood-dns-320.dts and a kirkwood-dns-325.dts file
> mimicing kirkwood-dreamplug.dts.  All you should need to start out is
> the compatible property and memory.
>
> [1] http://www.spinics.net/lists/arm-kernel/msg161696.html

Excellent, thank you both! This is definitely enough to get me going. 
All the patches seem to be in staging/kirkwood/dt, is submitting based on 
this tree reasonable too?

Will try to use CONFIG_ARM_APPENDED_DTB to get it booting, as D-Link's 
u-boot is probably not devicetree aware. Or is there a better approach 
(apart from a JTAG programmer and replacing u-boot)?

>> Some more comments:
>>
>>> diff --git a/arch/arm/mach-kirkwood/dnskw-setup.c b/arch/arm/mach-kirkwood/dnskw-setup.c
>>> new file mode 100644
>>> index 0000000..25ea0fa
>>> --- /dev/null
>>> +++ b/arch/arm/mach-kirkwood/dnskw-setup.c
>>> @@ -0,0 +1,431 @@
>>> +/*
>>> + * arch/arm/mach-kirkwood/dnskw-setup.c
>>
>> All future boards should ideally go through a single board file, and the plan
>> is to work on minimizing the non-generic contents of that over time.
>> Right now, it only contains support for the dreamplug, but there is no
>> reason why this one couldn't get merged into it as well.
>>

Definitely do-able, although I'm tempted to leave out anything 
non-essential to avoid board-dt.c becoming too unweildy. The MPP config 
and it's comments summarise my research, the rest is C+P code that could 
be reconstructed.

>>> +static struct mtd_partition dnskw_nand_parts[] = {
>>> +	{
>>> +		.name		= "u-boot",
>>> +		.offset		= 0,
>>> +		.size		= SZ_1M,
>>> +		.mask_flags	= MTD_WRITEABLE
>>> +	}, {
>>> +		.name		= "uImage",
>>> +		.offset		= MTDPART_OFS_NXTBLK,
>>> +		.size		= 5 * SZ_1M
>>> +	}, {
>>> +		.name		= "ramdisk",
>>> +		.offset		= MTDPART_OFS_NXTBLK,
>>> +		.size		= 5 * SZ_1M
>>> +	}, {
>>> +		.name		= "image",
>>> +		.offset		= MTDPART_OFS_NXTBLK,
>>> +		.size		= 102 * SZ_1M
>>> +	}, {
>>> +		.name		= "mini firmware",
>>> +		.offset		= MTDPART_OFS_NXTBLK,
>>> +		.size		= 10 * SZ_1M
>>> +	}, {
>>> +		.name		= "config",
>>> +		.offset		= MTDPART_OFS_NXTBLK,
>>> +		.size		= 5 * SZ_1M
>>> +	},
>>> +};
>>
>> Jason already has a patch for NAND partitions through the SPI attachment,
>> I would suggest that you do the same for the nand controller, the patch
>> should be fairly similar.
>>

Found this and can see what needs doing. Will attempt this after 
getting the basic devicetree support sorted.

>>> +/*****************************************************************************
>>> + * Power controls
>>> + ****************************************************************************/
>>> +
>>> +static void dnskw_power_off(void)
>>> +{
>>> +	gpio_set_value(DNSKW_GPIO_POWER, 1);
>>> +}
>>> ... <snip -- lots of gpio stuff>
>>
>> The entire gpio setup is rather complex, and I don't know how much of it
>> can be handled with the existing gpio device tree bindings. I hope someone
>> else can comment here.
>>

Turning on the HDDs is something a lot of NASes need to do. I wonder if 
the functionality to do so should be added to sata_mv. I don't know 
anywhere near enough to say if this makes sense, but could have a wild 
stab at a patch if it's not completely stupid.

The power-recovery pin is probably just random D-Link weirdness. The GPIO 
needs to be raised high on each boot to ensure the NAS turns back on after 
power failure. Just operating it from userland would work, although 
registering as a GPIO off/on-able switch would be neater. I'm not sure if 
anything similar exists?

>>> +/*****************************************************************************
>>> + * Main init
>>> + ****************************************************************************/
>>> +
>>> +static void __init dnskw_init(void)
>>> +{
>>> +	u32 dev, rev;
>>> +
>>> +	/*
>>> +	 * Basic setup. Needs to be called early.
>>> +	 */
>>> +	kirkwood_init();
>>> +	kirkwood_mpp_conf(dnskw_mpp_config);
>>
>> There is now a kirkwood_dt_init function that calls the board specific
>> functions based on an of_machine_is_compatible() check. Best add anything
>> from this function in there that cannot be handled using device tree
>> probing yet.
>>
>>> +	kirkwood_uart0_init();
>>> +	kirkwood_uart1_init();
>>
>> These can be done from the device tree already.
>>
>>> +	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
>>
>> This is the one I mentioned above that I think you should try to convert.
>>
>>> +	kirkwood_ehci_init();
>>> +	kirkwood_i2c_init();
>>> +	kirkwood_ge00_init(&dnskw_ge00_data);
>>> +	kirkwood_sata_init(&dnskw_sata_data);
>>
>> These should be handled next, but not necessarily before this board
>> supports makes it into the upstream kernel. Adding the bindings for
>> these should be fairly straightforward, and it will get easier
>> if kirkwood is first converted to use the generic clock framework.
>
> I've got a handle on these after I do xor and crypto.  If you get to it
> before I do, hit sata and ge00/01.  I'll start with ehci and i2c.
>

Okay---I'll let you know if I do get that far.

>>> +#ifdef CONFIG_MACH_DNS320
>>> +	if (machine_is_dns320())
>>> +		platform_device_register(&dns320_led_device);
>>> +#endif
>>> +#ifdef CONFIG_MACH_DNS325
>>> +	if (machine_is_dns325()) {
>>> +		platform_device_register(&dns325_led_device);
>>> +
>>> +		i2c_register_board_info(0, dns325_i2c_board_info,
>>> +					ARRAY_SIZE(dns325_i2c_board_info));
>>> +	}
>>> +#endif
>>> +
>>> +	/*
>>> +	 * Turn on power to harddrives, then enable SATA.
>>> +	 * NB: Bootloader should have turned sata0 on already, kernel needs
>>> +	 * to turn on sata1. The idea is to stagger spin-up of HDDs.
>>> +	 */
>>> +	dnskw_gpio_register(DNSKW_GPIO_POWER_SATA0, "dnskw:power:sata0", 1);
>>> +	dnskw_gpio_register(DNSKW_GPIO_POWER_SATA1, "dnskw:power:sata1", 1);
>>> +
>>> +	platform_device_register(&dnskw_button_device);
>>> +	platform_device_register(&dnskw_fan_device);
>>
>> It should be possible to handle all this by putting the right devices
>> into the device tree, but I don't know how to do that.
>>

arch/arm/boot/dts/imx53-qsb.dts amongst others have some examples, 
will steal them and see what happens.

>>> +	/* Register power off routine */
>>> +	kirkwood_pcie_id(&dev, &rev);
>>> +	if (dev == MV88F6281_DEV_ID) {
>>> +		pr_info("PCI-E Device ID: MV88F6281, configuring power-off");
>>> +		if (gpio_request(DNSKW_GPIO_POWER, "dnskw:power:off") == 0 &&
>>> +		    gpio_direction_output(DNSKW_GPIO_POWER, 0) == 0)
>>> +			pm_power_off = dnskw_power_off;
>>> +		else
>>> +			pr_err("dnskw: failed to configure power-off GPIO\n");
>>> +	} else {
>>> +		/*
>>> +		 * Dlink code also defines 0x6192, and sets LOW_BASE +
>>> +		 * 0x01000000 high. Either cargo-culted code or another model.
>>> +		 */
>>> +		pr_err("Unknown PCI-E Device ID %x, no power-off", dev);
>>> +	}
>>> +
>>> +	/* Set state of power_recover pin */
>>> +	if (gpio_request(DNSKW_GPIO_POWER_RECOVER, "dnskw:power:recover") == 0
>>> +	 && gpio_direction_output(DNSKW_GPIO_POWER_RECOVER, 0) == 0) {
>>> +		pr_info("dnskw: Setting power-recover %s\n",
>>> +			power_recover_value ? "on" : "off");
>>> +		gpio_set_value(DNSKW_GPIO_POWER_RECOVER, power_recover_value);
>>> +	} else
>>> +		pr_err("dnskw: Failed to register power-recover GPIO\n");
>>> +}
>>
>> This might have to stay board specific.
>>
>>> +#ifdef CONFIG_MACH_DNS320
>>> +MACHINE_START(DNS320, "D-Link DNS-320")
>>> +	/* Maintainer: Jamie Lentin <jm at lentin.co.uk> */
>>> +	.atag_offset	= 0x100,
>>> +	.init_machine	= dnskw_init,
>>> +	.map_io		= kirkwood_map_io,
>>> +	.init_early	= kirkwood_init_early,
>>> +	.init_irq	= kirkwood_init_irq,
>>> +	.timer		= &kirkwood_timer,
>>> +	.restart	= kirkwood_restart,
>>> +MACHINE_END
>>> +#endif
>>> +
>>> +#ifdef CONFIG_MACH_DNS325
>>> +MACHINE_START(DNS325, "D-Link DNS-325")
>>> +	/* Maintainer: Jamie Lentin <jm at lentin.co.uk> */
>>> +	.atag_offset	= 0x100,
>>> +	.init_machine	= dnskw_init,
>>> +	.map_io		= kirkwood_map_io,
>>> +	.init_early	= kirkwood_init_early,
>>> +	.init_irq	= kirkwood_init_irq,
>>> +	.timer		= &kirkwood_timer,
>>> +	.restart	= kirkwood_restart,
>>> +MACHINE_END
>>> +#endif
>>
>> Just use DT_MACHINE_START here and remove the machine ID and atag_offset. See
>> the board-dt.c file.
>
> See the link [1], above.
>
> thx,
>
> Jason.
>

-- 
Jamie Lentin


From nsekhar at ti.com  Wed Mar  7 09:30:30 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 7 Mar 2012 14:30:30 +0000
Subject: DaVinci unbanked GPIO IRQs broken
In-Reply-To: <DF0F476B391FA8409C78302C7BA518B6317A6E2B@DBDE01.ent.ti.com>
References: <70E876B0EA86DD4BAF101844BC814DFE0BF403DA89@Cloud.RL.local>
 <DF0F476B391FA8409C78302C7BA518B6317926BB@DBDE01.ent.ti.com>
 <DF0F476B391FA8409C78302C7BA518B6317A6E2B@DBDE01.ent.ti.com>
Message-ID: <DF0F476B391FA8409C78302C7BA518B6317EC8CA@DBDE01.ent.ti.com>

Hi Jon,

On Fri, Jan 27, 2012 at 18:49:42, Nori, Sekhar wrote:
> Hi Jon,
> 
> On Tue, Jan 17, 2012 at 15:32:23, Nori, Sekhar wrote:
> 
> > I was able to reproduce this on the EVM using v2.6.38 (works)
> > and v3.2 + my patch (doesn't work). I just started poking some
> > registers to see what is happening. Will keep you updated
> > on any progress.
> > 
> 
> Following patch fixes the issue of interrupt handler not getting
> called. I tested it using GPIO3 on DM365. On applying this, I
> see a constant rate of 4-5 interrupts per second on that line.
> Yet to figure out what is triggering those. Anyway I will wait for
> you to test this after you are back before sending this to Grant.

Are you back? Did you get a chance to test this?

Thanks,
Sekhar


From javier.martin at vista-silicon.com  Wed Mar  7 09:33:32 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:32 +0100
Subject: [PATCH v2 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
Message-ID: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>

The following series have to be applied on top of the following patches:
[PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
[PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.

As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
is deprecated and no new patches are accepted for it.

This series merges this code into the imx-dma.c dmaengine driver.

Changes since v1:
 - Merge patch 14 with 01.
 - Add a proper changelog to each patch of the series.

[PATCH v2 01/13] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
[PATCH v2 02/13] dmaengine: imx-dma: remove data member from internal structure.
[PATCH v2 03/13] dmaengine: imx-dma: remove dma_mode member of internal structure.
[PATCH v2 04/13] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
[PATCH v2 05/13] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
[PATCH v2 06/13] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
[PATCH v2 07/13] dmaengine: imx-dma: remove sg member from internal structure.
[PATCH v2 08/13] dmaengine: imx-dma: remove 'in_use' field of 'internal' structure.
[PATCH v2 09/13] dmaengine: imx-dma: remove 'resbytes' field of 'internal' structure.
[PATCH v2 10/13] dmaengine: imx-dma: remove internal structure.
[PATCH v2 11/13] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
[PATCH v2 12/13] dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and 'dma_clk'.
[PATCH v2 13/13] dmaengine: imx-dma: use 'dev_dbg' and 'dev_warn' for messages.


From javier.martin at vista-silicon.com  Wed Mar  7 09:33:34 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:34 +0100
Subject: [PATCH v2 02/13] dmaengine: imx-dma: remove data member from internal
 structure.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-3-git-send-email-javier.martin@vista-silicon.com>

Internal structure is just an auxiliary structure used for the initial
merge which is meant to be gone. As data member is not use anywhere
we can simply remove it.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 28d716c..1a9be6d 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -132,7 +132,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	void *data;
 	unsigned int dma_mode;
 	struct scatterlist *sg;
 	unsigned int resbytes;
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:33 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:33 +0100
Subject: [PATCH v2 01/13] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-2-git-send-email-javier.martin@vista-silicon.com>

It is mainly a simple merge changing the prefix of some
functions to fit the imx-dma namings.

As there are no users of the old dma-v1.c api we can safely
remove this file.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/mach-imx/Kconfig               |    6 -
 arch/arm/mach-imx/Makefile              |    2 -
 arch/arm/mach-imx/dma-v1.c              |  846 -------------------------------
 arch/arm/mach-imx/include/mach/dma-v1.h |  103 ----
 drivers/dma/Kconfig                     |    1 -
 drivers/dma/imx-dma.c                   |  591 ++++++++++++++++++++--
 6 files changed, 541 insertions(+), 1008 deletions(-)
 delete mode 100644 arch/arm/mach-imx/dma-v1.c
 delete mode 100644 arch/arm/mach-imx/include/mach/dma-v1.h

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0e6de36..3da1421 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,6 +1,3 @@
-config IMX_HAVE_DMA_V1
-	bool
-
 config HAVE_IMX_GPC
 	bool
 
@@ -26,7 +23,6 @@ config SOC_IMX1
 	bool
 	select ARCH_MX1
 	select CPU_ARM920T
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
@@ -35,7 +31,6 @@ config SOC_IMX21
 	select MACH_MX21
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
@@ -52,7 +47,6 @@ config SOC_IMX27
 	select MACH_MX27
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f5920c2..a62dc3a 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,5 +1,3 @@
-obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
-
 obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
 obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
 
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
deleted file mode 100644
index 42afc29..0000000
--- a/arch/arm/mach-imx/dma-v1.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/*
- *  linux/arch/arm/plat-mxc/dma-v1.c
- *
- *  i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/scatterlist.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/dma-v1.h>
-
-#define DMA_DCR     0x00		/* Control Register */
-#define DMA_DISR    0x04		/* Interrupt status Register */
-#define DMA_DIMR    0x08		/* Interrupt mask Register */
-#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
-#define DMA_DRTOSR  0x10		/* Request timeout Register */
-#define DMA_DSESR   0x14		/* Transfer Error Status Register */
-#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
-#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
-#define DMA_WSRA    0x40		/* W-Size Register A */
-#define DMA_XSRA    0x44		/* X-Size Register A */
-#define DMA_YSRA    0x48		/* Y-Size Register A */
-#define DMA_WSRB    0x4c		/* W-Size Register B */
-#define DMA_XSRB    0x50		/* X-Size Register B */
-#define DMA_YSRB    0x54		/* Y-Size Register B */
-#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
-#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
-#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
-#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
-#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
-#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
-#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
-#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
-#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */
-
-#define DCR_DRST           (1<<1)
-#define DCR_DEN            (1<<0)
-#define DBTOCR_EN          (1<<15)
-#define DBTOCR_CNT(x)      ((x) & 0x7fff)
-#define CNTR_CNT(x)        ((x) & 0xffffff)
-#define CCR_ACRPT          (1<<14)
-#define CCR_DMOD_LINEAR    (0x0 << 12)
-#define CCR_DMOD_2D        (0x1 << 12)
-#define CCR_DMOD_FIFO      (0x2 << 12)
-#define CCR_DMOD_EOBFIFO   (0x3 << 12)
-#define CCR_SMOD_LINEAR    (0x0 << 10)
-#define CCR_SMOD_2D        (0x1 << 10)
-#define CCR_SMOD_FIFO      (0x2 << 10)
-#define CCR_SMOD_EOBFIFO   (0x3 << 10)
-#define CCR_MDIR_DEC       (1<<9)
-#define CCR_MSEL_B         (1<<8)
-#define CCR_DSIZ_32        (0x0 << 6)
-#define CCR_DSIZ_8         (0x1 << 6)
-#define CCR_DSIZ_16        (0x2 << 6)
-#define CCR_SSIZ_32        (0x0 << 4)
-#define CCR_SSIZ_8         (0x1 << 4)
-#define CCR_SSIZ_16        (0x2 << 4)
-#define CCR_REN            (1<<3)
-#define CCR_RPT            (1<<2)
-#define CCR_FRC            (1<<1)
-#define CCR_CEN            (1<<0)
-#define RTOR_EN            (1<<15)
-#define RTOR_CLK           (1<<14)
-#define RTOR_PSC           (1<<13)
-
-/*
- * struct imx_dma_channel - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- *            (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imx_dma_channel only as extension to it.
- */
-
-struct imx_dma_channel {
-	const char *name;
-	void (*irq_handler) (int, void *);
-	void (*err_handler) (int, void *, int errcode);
-	void (*prog_handler) (int, void *, struct scatterlist *);
-	void *data;
-	unsigned int dma_mode;
-	struct scatterlist *sg;
-	unsigned int resbytes;
-	int dma_num;
-
-	int in_use;
-
-	u32 ccr_from_device;
-	u32 ccr_to_device;
-
-	struct timer_list watchdog;
-
-	int hw_chaining;
-};
-
-static void __iomem *imx_dmav1_baseaddr;
-
-static void imx_dmav1_writel(unsigned val, unsigned offset)
-{
-	__raw_writel(val, imx_dmav1_baseaddr + offset);
-}
-
-static unsigned imx_dmav1_readl(unsigned offset)
-{
-	return __raw_readl(imx_dmav1_baseaddr + offset);
-}
-
-static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
-
-static struct clk *dma_clk;
-
-static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
-{
-	if (cpu_is_mx27())
-		return imxdma->hw_chaining;
-	else
-		return 0;
-}
-
-/*
- * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
- */
-static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long now;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return 0;
-	}
-
-	now = min(imxdma->resbytes, sg->length);
-	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
-		imxdma->resbytes -= now;
-
-	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
-		imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
-	else
-		imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
-
-	imx_dmav1_writel(now, DMA_CNTR(channel));
-
-	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
-		"size 0x%08x\n", channel,
-		 imx_dmav1_readl(DMA_DAR(channel)),
-		 imx_dmav1_readl(DMA_SAR(channel)),
-		 imx_dmav1_readl(DMA_CNTR(channel)));
-
-	return now;
-}
-
-/**
- * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
- * device transfer
- *
- * @channel: i.MX DMA channel number
- * @dma_address: the DMA/physical memory address of the linear data block
- *		to transfer
- * @dma_length: length of the data block in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- *		Zero indicates success.
- */
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr,
-		     unsigned int dmamode)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	imxdma->sg = NULL;
-	imxdma->dma_mode = dmamode;
-
-	if (!dma_address) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!dma_length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(dma_address, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dma_address, DMA_SAR(channel));
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_to_device,
-				DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_single);
-
-/**
- * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
- * @channel: i.MX DMA channel number
- * @sg: pointer to the scatter-gather list/vector
- * @sgcount: scatter-gather list hungs count
- * @dma_length: total length of the transfer request in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * The function sets up DMA channel state and registers to be ready for
- * transfer specified by provided parameters. The scatter-gather emulation
- * is set up according to the parameters.
- *
- * The full preparation of the transfer requires setup of more register
- * by the caller before imx_dma_enable() can be called.
- *
- * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
- *
- * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
- *
- * %CCR(channel) has to specify transfer parameters, the next settings is
- * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
- * specified
- *
- * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
- *
- * The typical setup for %DMA_MODE_WRITE is specified by next options
- * combination
- *
- * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
- *
- * Be careful here and do not mistakenly mix source and target device
- * port sizes constants, they are really different:
- * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
- * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- * Zero indicates success.
- */
-int
-imx_dma_setup_sg(int channel,
-		 struct scatterlist *sg, unsigned int sgcount,
-		 unsigned int dma_length, unsigned int dev_addr,
-		 unsigned int dmamode)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	if (imxdma->in_use)
-		return -EBUSY;
-
-	imxdma->sg = sg;
-	imxdma->dma_mode = dmamode;
-	imxdma->resbytes = dma_length;
-
-	if (!sg || !sgcount) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!sg->length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imx_dma_sg_next(channel, sg);
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_sg);
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	u32 dreq = 0;
-
-	imxdma->hw_chaining = 0;
-
-	if (hw_chaining) {
-		imxdma->hw_chaining = 1;
-		if (!imx_dma_hw_chain(imxdma))
-			return -EINVAL;
-	}
-
-	if (dmareq)
-		dreq = CCR_REN;
-
-	imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
-	imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
-
-	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_config_channel);
-
-void imx_dma_config_burstlen(int channel, unsigned int burstlen)
-{
-	imx_dmav1_writel(burstlen, DMA_BLR(channel));
-}
-EXPORT_SYMBOL(imx_dma_config_burstlen);
-
-/**
- * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
- * handlers
- * @channel: i.MX DMA channel number
- * @irq_handler: the pointer to the function called if the transfer
- *		ends successfully
- * @err_handler: the pointer to the function called if the premature
- *		end caused by error occurs
- * @data: user specified value to be passed to the handlers
- */
-int
-imx_dma_setup_handlers(int channel,
-		       void (*irq_handler) (int, void *),
-		       void (*err_handler) (int, void *, int),
-		       void *data)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return -ENODEV;
-	}
-
-	local_irq_save(flags);
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdma->irq_handler = irq_handler;
-	imxdma->err_handler = err_handler;
-	imxdma->data = data;
-	local_irq_restore(flags);
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_handlers);
-
-/**
- * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
- * handlers
- * @channel: i.MX DMA channel number
- * @prog_handler: the pointer to the function called if the transfer progresses
- */
-int
-imx_dma_setup_progression_handler(int channel,
-			void (*prog_handler) (int, void*, struct scatterlist*))
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return -ENODEV;
-	}
-
-	local_irq_save(flags);
-	imxdma->prog_handler = prog_handler;
-	local_irq_restore(flags);
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_progression_handler);
-
-/**
- * imx_dma_enable - function to start i.MX DMA channel operation
- * @channel: i.MX DMA channel number
- *
- * The channel has to be allocated by driver through imx_dma_request()
- * or imx_dma_request_by_prio() function.
- * The transfer parameters has to be set to the channel registers through
- * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
- * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
- * be set prior this function call by the channel user.
- */
-void imx_dma_enable(int channel)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	pr_debug("imxdma%d: imx_dma_enable\n", channel);
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return;
-	}
-
-	if (imxdma->in_use)
-		return;
-
-	local_irq_save(flags);
-
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
-		CCR_ACRPT, DMA_CCR(channel));
-
-	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			imxdma->sg && imx_dma_hw_chain(imxdma)) {
-		imxdma->sg = sg_next(imxdma->sg);
-		if (imxdma->sg) {
-			u32 tmp;
-			imx_dma_sg_next(channel, imxdma->sg);
-			tmp = imx_dmav1_readl(DMA_CCR(channel));
-			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
-				DMA_CCR(channel));
-		}
-	}
-	imxdma->in_use = 1;
-
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_enable);
-
-/**
- * imx_dma_disable - stop, finish i.MX DMA channel operatin
- * @channel: i.MX DMA channel number
- */
-void imx_dma_disable(int channel)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	pr_debug("imxdma%d: imx_dma_disable\n", channel);
-
-	if (imx_dma_hw_chain(imxdma))
-		del_timer(&imxdma->watchdog);
-
-	local_irq_save(flags);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
-			DMA_CCR(channel));
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdma->in_use = 0;
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_disable);
-
-static void imx_dma_watchdog(unsigned long chno)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
-	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
-	imxdma->sg = NULL;
-
-	if (imxdma->err_handler)
-		imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
-}
-
-static irqreturn_t dma_err_handler(int irq, void *dev_id)
-{
-	int i, disr;
-	struct imx_dma_channel *imxdma;
-	unsigned int err_mask;
-	int errcode;
-
-	disr = imx_dmav1_readl(DMA_DISR);
-
-	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
-		   imx_dmav1_readl(DMA_DRTOSR) |
-		   imx_dmav1_readl(DMA_DSESR)  |
-		   imx_dmav1_readl(DMA_DBOSR);
-
-	if (!err_mask)
-		return IRQ_HANDLED;
-
-	imx_dmav1_writel(disr & err_mask, DMA_DISR);
-
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (!(err_mask & (1 << i)))
-			continue;
-		imxdma = &imx_dma_channels[i];
-		errcode = 0;
-
-		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBTOSR);
-			errcode |= IMX_DMA_ERR_BURST;
-		}
-		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DRTOSR);
-			errcode |= IMX_DMA_ERR_REQUEST;
-		}
-		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DSESR);
-			errcode |= IMX_DMA_ERR_TRANSFER;
-		}
-		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBOSR);
-			errcode |= IMX_DMA_ERR_BUFFER;
-		}
-		if (imxdma->name && imxdma->err_handler) {
-			imxdma->err_handler(i, imxdma->data, errcode);
-			continue;
-		}
-
-		imx_dma_channels[i].sg = NULL;
-
-		printk(KERN_WARNING
-		       "DMA timeout on channel %d (%s) -%s%s%s%s\n",
-		       i, imxdma->name,
-		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
-		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
-		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
-		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
-	}
-	return IRQ_HANDLED;
-}
-
-static void dma_irq_handle_channel(int chno)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
-	if (!imxdma->name) {
-		/*
-		 * IRQ for an unregistered DMA channel:
-		 * let's clear the interrupts and disable it.
-		 */
-		printk(KERN_WARNING
-		       "spurious IRQ for DMA channel %d\n", chno);
-		return;
-	}
-
-	if (imxdma->sg) {
-		u32 tmp;
-		struct scatterlist *current_sg = imxdma->sg;
-		imxdma->sg = sg_next(imxdma->sg);
-
-		if (imxdma->sg) {
-			imx_dma_sg_next(chno, imxdma->sg);
-
-			tmp = imx_dmav1_readl(DMA_CCR(chno));
-
-			if (imx_dma_hw_chain(imxdma)) {
-				/* FIXME: The timeout should probably be
-				 * configurable
-				 */
-				mod_timer(&imxdma->watchdog,
-					jiffies + msecs_to_jiffies(500));
-
-				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
-				imx_dmav1_writel(tmp, DMA_CCR(chno));
-			} else {
-				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
-				tmp |= CCR_CEN;
-			}
-
-			imx_dmav1_writel(tmp, DMA_CCR(chno));
-
-			if (imxdma->prog_handler)
-				imxdma->prog_handler(chno, imxdma->data,
-						current_sg);
-
-			return;
-		}
-
-		if (imx_dma_hw_chain(imxdma)) {
-			del_timer(&imxdma->watchdog);
-			return;
-		}
-	}
-
-	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
-	if (imxdma->irq_handler)
-		imxdma->irq_handler(chno, imxdma->data);
-}
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-	int i, disr;
-
-	if (cpu_is_mx21() || cpu_is_mx27())
-		dma_err_handler(irq, dev_id);
-
-	disr = imx_dmav1_readl(DMA_DISR);
-
-	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
-		     disr);
-
-	imx_dmav1_writel(disr, DMA_DISR);
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (disr & (1 << i))
-			dma_irq_handle_channel(i);
-	}
-
-	return IRQ_HANDLED;
-}
-
-/**
- * imx_dma_request - request/allocate specified channel number
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- */
-int imx_dma_request(int channel, const char *name)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-	int ret = 0;
-
-	/* basic sanity checks */
-	if (!name)
-		return -EINVAL;
-
-	if (channel >= IMX_DMA_CHANNELS) {
-		printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
-		       __func__, channel);
-		return -EINVAL;
-	}
-
-	local_irq_save(flags);
-	if (imxdma->name) {
-		local_irq_restore(flags);
-		return -EBUSY;
-	}
-	memset(imxdma, 0, sizeof(*imxdma));
-	imxdma->name = name;
-	local_irq_restore(flags); /* request_irq() can block */
-
-	if (cpu_is_mx21() || cpu_is_mx27()) {
-		ret = request_irq(MX2x_INT_DMACH0 + channel,
-				dma_irq_handler, 0, "DMA", NULL);
-		if (ret) {
-			imxdma->name = NULL;
-			pr_crit("Can't register IRQ %d for DMA channel %d\n",
-					MX2x_INT_DMACH0 + channel, channel);
-			return ret;
-		}
-		init_timer(&imxdma->watchdog);
-		imxdma->watchdog.function = &imx_dma_watchdog;
-		imxdma->watchdog.data = channel;
-	}
-
-	return ret;
-}
-EXPORT_SYMBOL(imx_dma_request);
-
-/**
- * imx_dma_free - release previously acquired channel
- * @channel: i.MX DMA channel number
- */
-void imx_dma_free(int channel)
-{
-	unsigned long flags;
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT
-		       "%s: trying to free free channel %d\n",
-		       __func__, channel);
-		return;
-	}
-
-	local_irq_save(flags);
-	/* Disable interrupts */
-	imx_dma_disable(channel);
-	imxdma->name = NULL;
-
-	if (cpu_is_mx21() || cpu_is_mx27())
-		free_irq(MX2x_INT_DMACH0 + channel, NULL);
-
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_free);
-
-/**
- * imx_dma_request_by_prio - find and request some of free channels best
- * suiting requested priority
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- *
- * This function tries to find a free channel in the specified priority group
- * if the priority cannot be achieved it tries to look for free channel
- * in the higher and then even lower priority groups.
- *
- * Return value: If there is no free channel to allocate, -%ENODEV is returned.
- *               On successful allocation channel is returned.
- */
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
-{
-	int i;
-	int best;
-
-	switch (prio) {
-	case (DMA_PRIO_HIGH):
-		best = 8;
-		break;
-	case (DMA_PRIO_MEDIUM):
-		best = 4;
-		break;
-	case (DMA_PRIO_LOW):
-	default:
-		best = 0;
-		break;
-	}
-
-	for (i = best; i < IMX_DMA_CHANNELS; i++)
-		if (!imx_dma_request(i, name))
-			return i;
-
-	for (i = best - 1; i >= 0; i--)
-		if (!imx_dma_request(i, name))
-			return i;
-
-	printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
-
-	return -ENODEV;
-}
-EXPORT_SYMBOL(imx_dma_request_by_prio);
-
-static int __init imx_dma_init(void)
-{
-	int ret = 0;
-	int i;
-
-	if (cpu_is_mx1())
-		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
-	else if (cpu_is_mx21())
-		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
-	else if (cpu_is_mx27())
-		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
-	else
-		return 0;
-
-	dma_clk = clk_get(NULL, "dma");
-	if (IS_ERR(dma_clk))
-		return PTR_ERR(dma_clk);
-	clk_enable(dma_clk);
-
-	/* reset DMA module */
-	imx_dmav1_writel(DCR_DRST, DMA_DCR);
-
-	if (cpu_is_mx1()) {
-		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
-		if (ret) {
-			pr_crit("Wow!  Can't register IRQ for DMA\n");
-			return ret;
-		}
-
-		ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
-		if (ret) {
-			pr_crit("Wow!  Can't register ERRIRQ for DMA\n");
-			free_irq(MX1_DMA_INT, NULL);
-			return ret;
-		}
-	}
-
-	/* enable DMA module */
-	imx_dmav1_writel(DCR_DEN, DMA_DCR);
-
-	/* clear all interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
-
-	/* disable interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		imx_dma_channels[i].sg = NULL;
-		imx_dma_channels[i].dma_num = i;
-	}
-
-	return ret;
-}
-
-arch_initcall(imx_dma_init);
diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h
deleted file mode 100644
index ac6fd71..0000000
--- a/arch/arm/mach-imx/include/mach/dma-v1.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- *  linux/arch/arm/mach-imx/include/mach/dma-v1.h
- *
- *  i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_DMA_V1_H__
-#define __MACH_DMA_V1_H__
-
-#define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
-
-#include <mach/dma.h>
-
-#define IMX_DMA_CHANNELS  16
-
-#define DMA_MODE_READ		0
-#define DMA_MODE_WRITE		1
-#define DMA_MODE_MASK		1
-
-#define MX1_DMA_REG(offset)	MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
-
-/* DMA Interrupt Mask Register */
-#define MX1_DMA_DIMR		MX1_DMA_REG(0x08)
-
-/* Channel Control Register */
-#define MX1_DMA_CCR(x)		MX1_DMA_REG(0x8c + ((x) << 6))
-
-#define IMX_DMA_MEMSIZE_32	(0 << 4)
-#define IMX_DMA_MEMSIZE_8	(1 << 4)
-#define IMX_DMA_MEMSIZE_16	(2 << 4)
-#define IMX_DMA_TYPE_LINEAR	(0 << 10)
-#define IMX_DMA_TYPE_2D		(1 << 10)
-#define IMX_DMA_TYPE_FIFO	(2 << 10)
-
-#define IMX_DMA_ERR_BURST     (1 << 0)
-#define IMX_DMA_ERR_REQUEST   (1 << 1)
-#define IMX_DMA_ERR_TRANSFER  (1 << 2)
-#define IMX_DMA_ERR_BUFFER    (1 << 3)
-#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining);
-
-void
-imx_dma_config_burstlen(int channel, unsigned int burstlen);
-
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
-		unsigned int dma_length, unsigned int dev_addr,
-		unsigned int dmamode);
-
-
-/*
- * Use this flag as the dma_length argument to imx_dma_setup_sg()
- * to create an endless running dma loop. The end of the scatterlist
- * must be linked to the beginning for this to work.
- */
-#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
-
-int
-imx_dma_setup_sg(int channel, struct scatterlist *sg,
-		unsigned int sgcount, unsigned int dma_length,
-		unsigned int dev_addr, unsigned int dmamode);
-
-int
-imx_dma_setup_handlers(int channel,
-		void (*irq_handler) (int, void *),
-		void (*err_handler) (int, void *, int), void *data);
-
-int
-imx_dma_setup_progression_handler(int channel,
-		void (*prog_handler) (int, void*, struct scatterlist*));
-
-void imx_dma_enable(int channel);
-
-void imx_dma_disable(int channel);
-
-int imx_dma_request(int channel, const char *name);
-
-void imx_dma_free(int channel);
-
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
-
-#endif	/* __MACH_DMA_V1_H__ */
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f1a2749..eb58b91 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -231,7 +231,6 @@ config IMX_SDMA
 
 config IMX_DMA
 	tristate "i.MX DMA support"
-	depends on IMX_HAVE_DMA_V1
 	select DMA_ENGINE
 	help
 	  Support the i.MX DMA engine. This engine is integrated into
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index c32103f..28d716c 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -14,7 +14,6 @@
  * http://www.opensource.org/licenses/gpl-license.html
  * http://www.gnu.org/copyleft/gpl.html
  */
-
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/types.h>
@@ -25,14 +24,88 @@
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 #include <linux/dmaengine.h>
 #include <linux/module.h>
 
 #include <asm/irq.h>
-#include <mach/dma-v1.h>
+#include <mach/dma.h>
 #include <mach/hardware.h>
 
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
+#define IMX_DMA_CHANNELS  16
+
+#define DMA_MODE_READ		0
+#define DMA_MODE_WRITE		1
+#define DMA_MODE_MASK		1
+
+#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
+#define IMX_DMA_MEMSIZE_32	(0 << 4)
+#define IMX_DMA_MEMSIZE_8	(1 << 4)
+#define IMX_DMA_MEMSIZE_16	(2 << 4)
+#define IMX_DMA_TYPE_LINEAR	(0 << 10)
+#define IMX_DMA_TYPE_2D		(1 << 10)
+#define IMX_DMA_TYPE_FIFO	(2 << 10)
+
+#define IMX_DMA_ERR_BURST     (1 << 0)
+#define IMX_DMA_ERR_REQUEST   (1 << 1)
+#define IMX_DMA_ERR_TRANSFER  (1 << 2)
+#define IMX_DMA_ERR_BUFFER    (1 << 3)
+#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
+
+#define DMA_DCR     0x00		/* Control Register */
+#define DMA_DISR    0x04		/* Interrupt status Register */
+#define DMA_DIMR    0x08		/* Interrupt mask Register */
+#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
+#define DMA_DRTOSR  0x10		/* Request timeout Register */
+#define DMA_DSESR   0x14		/* Transfer Error Status Register */
+#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
+#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
+#define DMA_WSRA    0x40		/* W-Size Register A */
+#define DMA_XSRA    0x44		/* X-Size Register A */
+#define DMA_YSRA    0x48		/* Y-Size Register A */
+#define DMA_WSRB    0x4c		/* W-Size Register B */
+#define DMA_XSRB    0x50		/* X-Size Register B */
+#define DMA_YSRB    0x54		/* Y-Size Register B */
+#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
+#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
+#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
+#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
+#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
+#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
+#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
+#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
+#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff)
+#define CNTR_CNT(x)        ((x) & 0xffffff)
+#define CCR_ACRPT          (1<<14)
+#define CCR_DMOD_LINEAR    (0x0 << 12)
+#define CCR_DMOD_2D        (0x1 << 12)
+#define CCR_DMOD_FIFO      (0x2 << 12)
+#define CCR_DMOD_EOBFIFO   (0x3 << 12)
+#define CCR_SMOD_LINEAR    (0x0 << 10)
+#define CCR_SMOD_2D        (0x1 << 10)
+#define CCR_SMOD_FIFO      (0x2 << 10)
+#define CCR_SMOD_EOBFIFO   (0x3 << 10)
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        (0x0 << 6)
+#define CCR_DSIZ_8         (0x1 << 6)
+#define CCR_DSIZ_16        (0x2 << 6)
+#define CCR_SSIZ_32        (0x0 << 4)
+#define CCR_SSIZ_8         (0x1 << 4)
+#define CCR_SSIZ_16        (0x2 << 4)
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
 
 enum  imxdma_prep_type {
 	IMXDMA_DESC_MEMCPY,
@@ -41,6 +114,39 @@ enum  imxdma_prep_type {
 	IMXDMA_DESC_CYCLIC,
 };
 
+/*
+ * struct imxdma_channel_internal - i.MX specific DMA extension
+ * @name: name specified by DMA client
+ * @irq_handler: client callback for end of transfer
+ * @err_handler: client callback for error condition
+ * @data: clients context data for callbacks
+ * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
+ * @sg: pointer to the actual read/written chunk for scatter-gather emulation
+ * @resbytes: total residual number of bytes to transfer
+ *            (it can be lower or same as sum of SG mapped chunk sizes)
+ * @sgcount: number of chunks to be read/written
+ *
+ * Structure is used for IMX DMA processing. It would be probably good
+ * @struct dma_struct in the future for external interfacing and use
+ * @struct imxdma_channel_internal only as extension to it.
+ */
+
+struct imxdma_channel_internal {
+	void *data;
+	unsigned int dma_mode;
+	struct scatterlist *sg;
+	unsigned int resbytes;
+
+	int in_use;
+
+	u32 ccr_from_device;
+	u32 ccr_to_device;
+
+	struct timer_list watchdog;
+
+	int hw_chaining;
+};
+
 struct imxdma_desc {
 	struct list_head		node;
 	struct dma_async_tx_descriptor	desc;
@@ -63,9 +169,9 @@ struct imxdma_desc {
 };
 
 struct imxdma_channel {
+	struct imxdma_channel_internal	internal;
 	struct imxdma_engine		*imxdma;
 	unsigned int			channel;
-	unsigned int			imxdma_channel;
 
 	struct tasklet_struct		dma_tasklet;
 	struct list_head		ld_free;
@@ -109,28 +215,381 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 	return false;
 }
 
-static void imxdma_irq_handler(int channel, void *data)
+/* TODO: put this inside any struct */
+static void __iomem *imx_dmav1_baseaddr;
+static struct clk *dma_clk;
+
+static void imx_dmav1_writel(unsigned val, unsigned offset)
 {
-	struct imxdma_channel *imxdmac = data;
+	__raw_writel(val, imx_dmav1_baseaddr + offset);
+}
 
-	tasklet_schedule(&imxdmac->dma_tasklet);
+static unsigned imx_dmav1_readl(unsigned offset)
+{
+	return __raw_readl(imx_dmav1_baseaddr + offset);
 }
 
-static void imxdma_err_handler(int channel, void *data, int error)
+static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
 {
-	struct imxdma_channel *imxdmac = data;
+	if (cpu_is_mx27())
+		return imxdma->hw_chaining;
+	else
+		return 0;
+}
+
+/*
+ * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
+ */
+static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+{
+	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+	unsigned long now;
+
+	now = min(imxdma->resbytes, sg->length);
+	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
+		imxdma->resbytes -= now;
+
+	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+	else
+		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+
+	imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+
+	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
+		"size 0x%08x\n", imxdmac->channel,
+		 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
+		 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
+		 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+
+	return now;
+}
+
+static int
+imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+		     unsigned int dma_length, unsigned int dev_addr,
+		     unsigned int dmamode)
+{
+	int channel = imxdmac->channel;
+
+	imxdmac->internal.sg = NULL;
+	imxdmac->internal.dma_mode = dmamode;
+
+	if (!dma_address) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if (!dma_length) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+			"dev_addr=0x%08x for read\n",
+			channel, __func__, (unsigned int)dma_address,
+			dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+		imx_dmav1_writel(dma_address, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+			"dev_addr=0x%08x for write\n",
+			channel, __func__, (unsigned int)dma_address,
+			dma_length, dev_addr);
+
+		imx_dmav1_writel(dma_address, DMA_SAR(channel));
+		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+				DMA_CCR(channel));
+	} else {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
+		       channel);
+		return -EINVAL;
+	}
 
+	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
+
+	return 0;
+}
+
+static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+{
+	int channel = imxdmac->channel;
+	unsigned long flags;
+
+	pr_debug("imxdma%d: imx_dma_enable\n", channel);
+
+	if (imxdmac->internal.in_use)
+		return;
+
+	local_irq_save(flags);
+
+	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
+		CCR_ACRPT, DMA_CCR(channel));
+
+	if ((cpu_is_mx21() || cpu_is_mx27()) &&
+			imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
+		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
+		if (imxdmac->internal.sg) {
+			u32 tmp;
+			imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+			tmp = imx_dmav1_readl(DMA_CCR(channel));
+			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
+				DMA_CCR(channel));
+		}
+	}
+	imxdmac->internal.in_use = 1;
+
+	local_irq_restore(flags);
+}
+
+static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
+{
+	int channel = imxdmac->channel;
+	unsigned long flags;
+
+	pr_debug("imxdma%d: imx_dma_disable\n", channel);
+
+	if (imxdma_hw_chain(&imxdmac->internal))
+		del_timer(&imxdmac->internal.watchdog);
+
+	local_irq_save(flags);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
+			DMA_CCR(channel));
+	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imxdmac->internal.in_use = 0;
+	local_irq_restore(flags);
+}
+
+static int
+imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
+	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
+{
+	int channel = imxdmac->channel;
+	u32 dreq = 0;
+
+	imxdmac->internal.hw_chaining = 0;
+
+	if (hw_chaining) {
+		imxdmac->internal.hw_chaining = 1;
+		if (!imxdma_hw_chain(&imxdmac->internal))
+			return -EINVAL;
+	}
+
+	if (dmareq)
+		dreq = CCR_REN;
+
+	imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
+	imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
+
+	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
+
+	return 0;
+}
+
+static int
+imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+		 struct scatterlist *sg, unsigned int sgcount,
+		 unsigned int dma_length, unsigned int dev_addr,
+		 unsigned int dmamode)
+{
+	int channel = imxdmac->channel;
+
+	if (imxdmac->internal.in_use)
+		return -EBUSY;
+
+	imxdmac->internal.sg = sg;
+	imxdmac->internal.dma_mode = dmamode;
+	imxdmac->internal.resbytes = dma_length;
+
+	if (!sg || !sgcount) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if (!sg->length) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+			"dev_addr=0x%08x for read\n",
+			channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+			"dev_addr=0x%08x for write\n",
+			channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
+	} else {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	imxdma_sg_next(imxdmac, sg);
+
+	return 0;
+}
+
+static void imxdma_watchdog(unsigned long data)
+{
+	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+	int channel = imxdmac->channel;
+
+	imx_dmav1_writel(0, DMA_CCR(channel));
+	imxdmac->internal.in_use = 0;
+	imxdmac->internal.sg = NULL;
+
+	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
+	pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+}
+
+static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
+{
+	struct imxdma_engine *imxdma = dev_id;
+	struct imxdma_channel_internal *internal;
+	unsigned int err_mask;
+	int i, disr;
+	int errcode;
+
+	disr = imx_dmav1_readl(DMA_DISR);
+
+	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
+		   imx_dmav1_readl(DMA_DRTOSR) |
+		   imx_dmav1_readl(DMA_DSESR)  |
+		   imx_dmav1_readl(DMA_DBOSR);
+
+	if (!err_mask)
+		return IRQ_HANDLED;
+
+	imx_dmav1_writel(disr & err_mask, DMA_DISR);
+
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+		if (!(err_mask & (1 << i)))
+			continue;
+		internal = &imxdma->channel[i].internal;
+		errcode = 0;
+
+		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DBTOSR);
+			errcode |= IMX_DMA_ERR_BURST;
+		}
+		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DRTOSR);
+			errcode |= IMX_DMA_ERR_REQUEST;
+		}
+		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DSESR);
+			errcode |= IMX_DMA_ERR_TRANSFER;
+		}
+		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DBOSR);
+			errcode |= IMX_DMA_ERR_BUFFER;
+		}
+		/* Tasklet error handler */
+		tasklet_schedule(&imxdma->channel[i].dma_tasklet);
+
+		printk(KERN_WARNING
+		       "DMA timeout on channel %d -%s%s%s%s\n", i,
+		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
+		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
+		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
+		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
+	}
+	return IRQ_HANDLED;
 }
 
-static void imxdma_progression(int channel, void *data,
-		struct scatterlist *sg)
+static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
-	struct imxdma_channel *imxdmac = data;
+	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+	int chno = imxdmac->channel;
+
+	if (imxdma->sg) {
+		u32 tmp;
+		imxdma->sg = sg_next(imxdma->sg);
+
+		if (imxdma->sg) {
+			imxdma_sg_next(imxdmac, imxdma->sg);
+
+			tmp = imx_dmav1_readl(DMA_CCR(chno));
+
+			if (imxdma_hw_chain(imxdma)) {
+				/* FIXME: The timeout should probably be
+				 * configurable
+				 */
+				mod_timer(&imxdma->watchdog,
+					jiffies + msecs_to_jiffies(500));
+
+				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
+				imx_dmav1_writel(tmp, DMA_CCR(chno));
+			} else {
+				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+				tmp |= CCR_CEN;
+			}
+
+			imx_dmav1_writel(tmp, DMA_CCR(chno));
+
+			if (imxdma_chan_is_doing_cyclic(imxdmac))
+				/* Tasklet progression */
+				tasklet_schedule(&imxdmac->dma_tasklet);
+
+			return;
+		}
 
+		if (imxdma_hw_chain(imxdma)) {
+			del_timer(&imxdma->watchdog);
+			return;
+		}
+	}
+
+	imx_dmav1_writel(0, DMA_CCR(chno));
+	imxdma->in_use = 0;
+	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
 
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+	struct imxdma_engine *imxdma = dev_id;
+	struct imxdma_channel_internal *internal;
+	int i, disr;
+
+	if (cpu_is_mx21() || cpu_is_mx27())
+		imxdma_err_handler(irq, dev_id);
+
+	disr = imx_dmav1_readl(DMA_DISR);
+
+	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
+		     disr);
+
+	imx_dmav1_writel(disr, DMA_DISR);
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+		if (disr & (1 << i)) {
+			internal = &imxdma->channel[i].internal;
+			dma_irq_handle_channel(&imxdma->channel[i]);
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
 static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -139,31 +598,24 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+		ret = imxdma_config_channel_hw(imxdmac,
 					  d->config_port, d->config_mem, 0, 0);
 		if (ret < 0)
 			return ret;
-		ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
+		ret = imxdma_setup_single_hw(imxdmac, d->src,
 					   d->len, d->dest, d->dmamode);
 		if (ret < 0)
 			return ret;
 		break;
+
+	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
-		ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
-							imxdma_progression);
-		if (ret < 0)
-			return ret;
-		/*
-		 * We fall through here since cyclic transfer is the same as
-		 * slave_sg adding a progression handler and a specific sg
-		 * configuration which is done in 'imxdma_prep_dma_cyclic'.
-		 */
 	case IMXDMA_DESC_SLAVE_SG:
 		if (d->dmamode == DMA_MODE_READ)
-			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
 				       d->sgcount, d->len, d->src, d->dmamode);
 		else
-			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
 				      d->sgcount, d->len, d->dest, d->dmamode);
 		if (ret < 0)
 			return ret;
@@ -171,7 +623,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	default:
 		return -EINVAL;
 	}
-	imx_dma_enable(imxdmac->imxdma_channel);
+	imxdma_enable_hw(imxdmac);
 	return 0;
 }
 
@@ -223,7 +675,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 
 	switch (cmd) {
 	case DMA_TERMINATE_ALL:
-		imx_dma_disable(imxdmac->imxdma_channel);
+		imxdma_disable_hw(imxdmac);
 
 		spin_lock_irqsave(&imxdmac->lock, flags);
 		list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
@@ -253,16 +705,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			mode = IMX_DMA_MEMSIZE_32;
 			break;
 		}
-		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+		ret = imxdma_config_channel_hw(imxdmac,
 				mode | IMX_DMA_TYPE_FIFO,
 				IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
 				imxdmac->dma_request, 1);
 
 		if (ret)
 			return ret;
-
-		imx_dma_config_burstlen(imxdmac->imxdma_channel,
-				imxdmac->watermark_level * imxdmac->word_size);
+		/* Set burst length */
+		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
+				 DMA_BLR(imxdmac->channel));
 
 		return 0;
 	default:
@@ -359,7 +811,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
 
 	spin_lock_irqsave(&imxdmac->lock, flags);
 
-	imx_dma_disable(imxdmac->imxdma_channel);
+	imxdma_disable_hw(imxdmac);
 	list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 	list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 
@@ -545,10 +997,51 @@ static void imxdma_issue_pending(struct dma_chan *chan)
 }
 
 static int __init imxdma_probe(struct platform_device *pdev)
-{
+	{
 	struct imxdma_engine *imxdma;
 	int ret, i;
 
+	if (cpu_is_mx1())
+		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+	else if (cpu_is_mx21())
+		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+	else if (cpu_is_mx27())
+		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+	else
+		return 0;
+
+	dma_clk = clk_get(NULL, "dma");
+	if (IS_ERR(dma_clk))
+		return PTR_ERR(dma_clk);
+	clk_enable(dma_clk);
+
+	/* reset DMA module */
+	imx_dmav1_writel(DCR_DRST, DMA_DCR);
+
+	if (cpu_is_mx1()) {
+		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
+		if (ret) {
+			pr_crit("Can't register IRQ for DMA\n");
+			return ret;
+		}
+
+		ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
+		if (ret) {
+			pr_crit("Can't register ERRIRQ for DMA\n");
+			free_irq(MX1_DMA_INT, NULL);
+			return ret;
+		}
+	}
+
+	/* enable DMA module */
+	imx_dmav1_writel(DCR_DEN, DMA_DCR);
+
+	/* clear all interrupts */
+	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+
+	/* disable interrupts */
+	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
+
 	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
 	if (!imxdma)
 		return -ENOMEM;
@@ -562,17 +1055,20 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	/* Initialize channel parameters */
 	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
 		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
-		imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
-				DMA_PRIO_MEDIUM);
-		if ((int)imxdmac->channel < 0) {
-			ret = -ENODEV;
-			goto err_init;
+		memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+		if (cpu_is_mx21() || cpu_is_mx27()) {
+			ret = request_irq(MX2x_INT_DMACH0 + i,
+					dma_irq_handler, 0, "DMA", imxdma);
+			if (ret) {
+				pr_crit("Can't register IRQ %d for DMA channel %d\n",
+						MX2x_INT_DMACH0 + i, i);
+				goto err_init;
+			}
+			init_timer(&imxdmac->internal.watchdog);
+			imxdmac->internal.watchdog.function = &imxdma_watchdog;
+			imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
 		}
 
-		imx_dma_setup_handlers(imxdmac->imxdma_channel,
-		       imxdma_irq_handler, imxdma_err_handler, imxdmac);
-
 		imxdmac->imxdma = imxdma;
 		spin_lock_init(&imxdmac->lock);
 
@@ -617,10 +1113,8 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	return 0;
 
 err_init:
-	while (--i >= 0) {
-		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-		imx_dma_free(imxdmac->imxdma_channel);
-	}
+	while (--i >= 0)
+		free_irq(MX2x_INT_DMACH0 + i, NULL);
 
 	kfree(imxdma);
 	return ret;
@@ -633,11 +1127,8 @@ static int __exit imxdma_remove(struct platform_device *pdev)
 
         dma_async_device_unregister(&imxdma->dma_device);
 
-	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
-		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
-		 imx_dma_free(imxdmac->imxdma_channel);
-	}
+	for (i = 0; i < MAX_DMA_CHANNELS; i++)
+		free_irq(MX2x_INT_DMACH0 + i, NULL);
 
         kfree(imxdma);
 
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:35 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:35 +0100
Subject: [PATCH v2 03/13] dmaengine: imx-dma: remove dma_mode member of
 internal structure.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-4-git-send-email-javier.martin@vista-silicon.com>

dmaengine now provides 'enum dma_transfer_direction' to properly
specify DMA transfer direction. For this reason, DMA_MODE_* defines
are replaced by this new type and therefore dma_mode member becomes
redundant.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |  103 +++++++++++++++++++++---------------------------
 1 files changed, 45 insertions(+), 58 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 1a9be6d..2c524e1 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -35,10 +35,6 @@
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
 #define IMX_DMA_CHANNELS  16
 
-#define DMA_MODE_READ		0
-#define DMA_MODE_WRITE		1
-#define DMA_MODE_MASK		1
-
 #define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
 #define IMX_DMA_MEMSIZE_32	(0 << 4)
 #define IMX_DMA_MEMSIZE_8	(1 << 4)
@@ -132,7 +128,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	unsigned int dma_mode;
 	struct scatterlist *sg;
 	unsigned int resbytes;
 
@@ -153,7 +148,7 @@ struct imxdma_desc {
 	dma_addr_t			src;
 	dma_addr_t			dest;
 	size_t				len;
-	unsigned int			dmamode;
+	enum dma_transfer_direction	direction;
 	enum imxdma_prep_type		type;
 	/* For memcpy and interleaved */
 	unsigned int			config_port;
@@ -239,8 +234,9 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
 /*
  * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
  */
-static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	unsigned long now;
 
@@ -248,7 +244,7 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
 	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
 		imxdma->resbytes -= now;
 
-	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+	if (d->direction == DMA_DEV_TO_MEM)
 		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
 	else
 		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
@@ -265,14 +261,12 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
 }
 
 static int
-imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr,
-		     unsigned int dmamode)
+imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+		     unsigned int dma_length, unsigned int dev_addr)
 {
 	int channel = imxdmac->channel;
 
 	imxdmac->internal.sg = NULL;
-	imxdmac->internal.dma_mode = dmamode;
 
 	if (!dma_address) {
 		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
@@ -286,38 +280,24 @@ imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
 		return -EINVAL;
 	}
 
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
+	pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+		"dev_addr=0x%08x for write\n",
+		channel, __func__, (unsigned int)dma_address,
+		dma_length, dev_addr);
 
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(dma_address, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dma_address, DMA_SAR(channel));
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_to_device,
-				DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
+	imx_dmav1_writel(dma_address, DMA_SAR(channel));
+	imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+	imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+			 DMA_CCR(channel));
 
 	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
 
 	return 0;
 }
 
-static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+static void imxdma_enable_hw(struct imxdma_desc *d)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -338,7 +318,7 @@ static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
 		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
 		if (imxdmac->internal.sg) {
 			u32 tmp;
-			imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+			imxdma_sg_next(d, imxdmac->internal.sg);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -395,18 +375,18 @@ imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_por
 }
 
 static int
-imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+imxdma_setup_sg_hw(struct imxdma_desc *d,
 		 struct scatterlist *sg, unsigned int sgcount,
 		 unsigned int dma_length, unsigned int dev_addr,
-		 unsigned int dmamode)
+		 enum dma_transfer_direction direction)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	int channel = imxdmac->channel;
 
 	if (imxdmac->internal.in_use)
 		return -EBUSY;
 
 	imxdmac->internal.sg = sg;
-	imxdmac->internal.dma_mode = dmamode;
 	imxdmac->internal.resbytes = dma_length;
 
 	if (!sg || !sgcount) {
@@ -421,14 +401,14 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
 		return -EINVAL;
 	}
 
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+	if (direction == DMA_DEV_TO_MEM) {
 		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
 			"dev_addr=0x%08x for read\n",
 			channel, __func__, sg, sgcount, dma_length, dev_addr);
 
 		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
 		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+	} else if (direction == DMA_MEM_TO_DEV) {
 		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
 			"dev_addr=0x%08x for write\n",
 			channel, __func__, sg, sgcount, dma_length, dev_addr);
@@ -441,7 +421,7 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
 		return -EINVAL;
 	}
 
-	imxdma_sg_next(imxdmac, sg);
+	imxdma_sg_next(d, sg);
 
 	return 0;
 }
@@ -519,13 +499,26 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
 	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	int chno = imxdmac->channel;
+	struct imxdma_desc *desc;
 
 	if (imxdma->sg) {
 		u32 tmp;
 		imxdma->sg = sg_next(imxdma->sg);
 
 		if (imxdma->sg) {
-			imxdma_sg_next(imxdmac, imxdma->sg);
+
+			spin_lock(&imxdmac->lock);
+			if (list_empty(&imxdmac->ld_active)) {
+				spin_unlock(&imxdmac->lock);
+				goto out;
+			}
+
+			desc = list_first_entry(&imxdmac->ld_active,
+						struct imxdma_desc,
+						node);
+			spin_unlock(&imxdmac->lock);
+
+			imxdma_sg_next(desc, imxdma->sg);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -558,6 +551,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		}
 	}
 
+out:
 	imx_dmav1_writel(0, DMA_CCR(chno));
 	imxdma->in_use = 0;
 	/* Tasklet irq */
@@ -601,8 +595,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 					  d->config_port, d->config_mem, 0, 0);
 		if (ret < 0)
 			return ret;
-		ret = imxdma_setup_single_hw(imxdmac, d->src,
-					   d->len, d->dest, d->dmamode);
+		ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
 		if (ret < 0)
 			return ret;
 		break;
@@ -610,19 +603,15 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		if (d->dmamode == DMA_MODE_READ)
-			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
-				       d->sgcount, d->len, d->src, d->dmamode);
-		else
-			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
-				      d->sgcount, d->len, d->dest, d->dmamode);
+		ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
+					 imxdmac->per_address, d->direction);
 		if (ret < 0)
 			return ret;
 		break;
 	default:
 		return -EINVAL;
 	}
-	imxdma_enable_hw(imxdmac);
+	imxdma_enable_hw(d);
 	return 0;
 }
 
@@ -867,11 +856,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
 	desc->sg = sgl;
 	desc->sgcount = sg_len;
 	desc->len = dma_length;
+	desc->direction = direction;
 	if (direction == DMA_DEV_TO_MEM) {
-		desc->dmamode = DMA_MODE_READ;
 		desc->src = imxdmac->per_address;
 	} else {
-		desc->dmamode = DMA_MODE_WRITE;
 		desc->dest = imxdmac->per_address;
 	}
 	desc->desc.callback = NULL;
@@ -927,11 +915,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
 	desc->sg = imxdmac->sg_list;
 	desc->sgcount = periods;
 	desc->len = IMX_DMA_LENGTH_LOOP;
+	desc->direction = direction;
 	if (direction == DMA_DEV_TO_MEM) {
-		desc->dmamode = DMA_MODE_READ;
 		desc->src = imxdmac->per_address;
 	} else {
-		desc->dmamode = DMA_MODE_WRITE;
 		desc->dest = imxdmac->per_address;
 	}
 	desc->desc.callback = NULL;
@@ -961,7 +948,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
 	desc->src = src;
 	desc->dest = dest;
 	desc->len = len;
-	desc->dmamode = DMA_MODE_WRITE;
+	desc->direction = DMA_MEM_TO_MEM;
 	desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 	desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 	desc->desc.callback = NULL;
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:36 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:36 +0100
Subject: [PATCH v2 04/13] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw'
 function.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-5-git-send-email-javier.martin@vista-silicon.com>

This function is only used once in the driver and has a lot of checks
that are not needed anymore. For this reason it's been merged
with 'imxdma_enable_hw'.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   57 ++++++++++++-------------------------------------
 1 files changed, 14 insertions(+), 43 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 2c524e1..8a0afb1 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -260,41 +260,6 @@ static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 	return now;
 }
 
-static int
-imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr)
-{
-	int channel = imxdmac->channel;
-
-	imxdmac->internal.sg = NULL;
-
-	if (!dma_address) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!dma_length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-		"dev_addr=0x%08x for write\n",
-		channel, __func__, (unsigned int)dma_address,
-		dma_length, dev_addr);
-
-	imx_dmav1_writel(dma_address, DMA_SAR(channel));
-	imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-	imx_dmav1_writel(imxdmac->internal.ccr_to_device,
-			 DMA_CCR(channel));
-
-	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
-	return 0;
-}
-
 static void imxdma_enable_hw(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -586,20 +551,26 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int ret;
 
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		ret = imxdma_config_channel_hw(imxdmac,
-					  d->config_port, d->config_mem, 0, 0);
-		if (ret < 0)
-			return ret;
-		ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
-		if (ret < 0)
-			return ret;
-		break;
+		imxdmac->internal.sg = NULL;
+
+		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+			 DMA_CCR(imxdmac->channel));
 
+		imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+
+		dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
+			"dma_length=%d\n", __func__, imxdmac->channel,
+			d->dest, d->src, d->len);
+
+		break;
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:37 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:37 +0100
Subject: [PATCH v2 05/13] dmaengine: imx-dma: remove
 'imxdma_config_channel_hw' function.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-6-git-send-email-javier.martin@vista-silicon.com>

This function is only used once in the driver and uses some
intermediary variables that are not needed anymore. For this
reason it's been merged with 'imxdma_control'.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   46 +++++++++++++---------------------------------
 1 files changed, 13 insertions(+), 33 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 8a0afb1..5432b04 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -314,32 +314,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 }
 
 static int
-imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
-	int channel = imxdmac->channel;
-	u32 dreq = 0;
-
-	imxdmac->internal.hw_chaining = 0;
-
-	if (hw_chaining) {
-		imxdmac->internal.hw_chaining = 1;
-		if (!imxdma_hw_chain(&imxdmac->internal))
-			return -EINVAL;
-	}
-
-	if (dmareq)
-		dreq = CCR_REN;
-
-	imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
-	imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
-
-	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
-	return 0;
-}
-
-static int
 imxdma_setup_sg_hw(struct imxdma_desc *d,
 		 struct scatterlist *sg, unsigned int sgcount,
 		 unsigned int dma_length, unsigned int dev_addr,
@@ -628,7 +602,6 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct dma_slave_config *dmaengine_cfg = (void *)arg;
-	int ret;
 	unsigned long flags;
 	unsigned int mode = 0;
 
@@ -664,13 +637,20 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			mode = IMX_DMA_MEMSIZE_32;
 			break;
 		}
-		ret = imxdma_config_channel_hw(imxdmac,
-				mode | IMX_DMA_TYPE_FIFO,
-				IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
-				imxdmac->dma_request, 1);
 
-		if (ret)
-			return ret;
+		imxdmac->internal.hw_chaining = 1;
+		if (!imxdma_hw_chain(&imxdmac->internal))
+			return -EINVAL;
+		imxdmac->internal.ccr_from_device =
+			(mode | IMX_DMA_TYPE_FIFO) |
+			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
+			CCR_REN;
+		imxdmac->internal.ccr_to_device =
+			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
+			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
+		imx_dmav1_writel(imxdmac->dma_request,
+				 DMA_RSSR(imxdmac->channel));
+
 		/* Set burst length */
 		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
 				 DMA_BLR(imxdmac->channel));
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:38 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:38 +0100
Subject: [PATCH v2 06/13] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw'
 function.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-7-git-send-email-javier.martin@vista-silicon.com>

Removing this function allows moving 'ccr_to_device' and
'ccr_from_device' from internal struct to channel struct.
This repesents a step forward towards removing auxiliary
'internal' structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   97 ++++++++++++++++++-------------------------------
 1 files changed, 35 insertions(+), 62 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 5432b04..cb45aff 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -133,9 +133,6 @@ struct imxdma_channel_internal {
 
 	int in_use;
 
-	u32 ccr_from_device;
-	u32 ccr_to_device;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -180,6 +177,8 @@ struct imxdma_channel {
 	dma_cookie_t			last_completed;
 	int				dma_request;
 	struct scatterlist		*sg_list;
+	u32				ccr_from_device;
+	u32				ccr_to_device;
 };
 
 #define MAX_DMA_CHANNELS 8
@@ -313,58 +312,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	local_irq_restore(flags);
 }
 
-static int
-imxdma_setup_sg_hw(struct imxdma_desc *d,
-		 struct scatterlist *sg, unsigned int sgcount,
-		 unsigned int dma_length, unsigned int dev_addr,
-		 enum dma_transfer_direction direction)
-{
-	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
-	int channel = imxdmac->channel;
-
-	if (imxdmac->internal.in_use)
-		return -EBUSY;
-
-	imxdmac->internal.sg = sg;
-	imxdmac->internal.resbytes = dma_length;
-
-	if (!sg || !sgcount) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!sg->length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (direction == DMA_DEV_TO_MEM) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if (direction == DMA_MEM_TO_DEV) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imxdma_sg_next(d, sg);
-
-	return 0;
-}
-
 static void imxdma_watchdog(unsigned long data)
 {
 	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
@@ -548,10 +495,37 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
-					 imxdmac->per_address, d->direction);
-		if (ret < 0)
-			return ret;
+		imxdmac->internal.sg = d->sg;
+		imxdmac->internal.resbytes = d->len;
+
+		if (d->direction == DMA_DEV_TO_MEM) {
+			imx_dmav1_writel(imxdmac->per_address,
+					 DMA_SAR(imxdmac->channel));
+			imx_dmav1_writel(imxdmac->ccr_from_device,
+					 DMA_CCR(imxdmac->channel));
+
+			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+				"total length=%d dev_addr=0x%08x (dev2mem)\n",
+				__func__, imxdmac->channel, d->sg, d->sgcount,
+				d->len, imxdmac->per_address);
+		} else if (d->direction == DMA_MEM_TO_DEV) {
+			imx_dmav1_writel(imxdmac->per_address,
+					 DMA_DAR(imxdmac->channel));
+			imx_dmav1_writel(imxdmac->ccr_to_device,
+					 DMA_CCR(imxdmac->channel));
+
+			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+				"total length=%d dev_addr=0x%08x (mem2dev)\n",
+				__func__, imxdmac->channel, d->sg, d->sgcount,
+				d->len, imxdmac->per_address);
+		} else {
+			dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
+				__func__, imxdmac->channel);
+			return -EINVAL;
+		}
+
+		imxdma_sg_next(d, d->sg);
+
 		break;
 	default:
 		return -EINVAL;
@@ -641,11 +615,10 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		imxdmac->internal.hw_chaining = 1;
 		if (!imxdma_hw_chain(&imxdmac->internal))
 			return -EINVAL;
-		imxdmac->internal.ccr_from_device =
-			(mode | IMX_DMA_TYPE_FIFO) |
+		imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
 			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
 			CCR_REN;
-		imxdmac->internal.ccr_to_device =
+		imxdmac->ccr_to_device =
 			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
 			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
 		imx_dmav1_writel(imxdmac->dma_request,
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:39 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:39 +0100
Subject: [PATCH v2 07/13] dmaengine: imx-dma: remove sg member from internal
 structure.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-8-git-send-email-javier.martin@vista-silicon.com>

This member is redundant, because it is already present in
descriptor structure. Removing it will make further removing
of 'internal' structure easier.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   42 ++++++++++++++++++------------------------
 1 files changed, 18 insertions(+), 24 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index cb45aff..ed94207 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -128,7 +128,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	struct scatterlist *sg;
 	unsigned int resbytes;
 
 	int in_use;
@@ -278,11 +277,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
-		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
-		if (imxdmac->internal.sg) {
+			d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+		d->sg = sg_next(d->sg);
+		if (d->sg) {
 			u32 tmp;
-			imxdma_sg_next(d, imxdmac->internal.sg);
+			imxdma_sg_next(d, d->sg);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -319,7 +318,6 @@ static void imxdma_watchdog(unsigned long data)
 
 	imx_dmav1_writel(0, DMA_CCR(channel));
 	imxdmac->internal.in_use = 0;
-	imxdmac->internal.sg = NULL;
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -387,24 +385,23 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
-	if (imxdma->sg) {
-		u32 tmp;
-		imxdma->sg = sg_next(imxdma->sg);
-
-		if (imxdma->sg) {
+	spin_lock(&imxdmac->lock);
+	if (list_empty(&imxdmac->ld_active)) {
+		spin_unlock(&imxdmac->lock);
+		goto out;
+	}
 
-			spin_lock(&imxdmac->lock);
-			if (list_empty(&imxdmac->ld_active)) {
-				spin_unlock(&imxdmac->lock);
-				goto out;
-			}
+	desc = list_first_entry(&imxdmac->ld_active,
+				struct imxdma_desc,
+				node);
+	spin_unlock(&imxdmac->lock);
 
-			desc = list_first_entry(&imxdmac->ld_active,
-						struct imxdma_desc,
-						node);
-			spin_unlock(&imxdmac->lock);
+	if (desc->sg) {
+		u32 tmp;
+		desc->sg = sg_next(desc->sg);
 
-			imxdma_sg_next(desc, imxdma->sg);
+		if (desc->sg) {
+			imxdma_sg_next(desc, desc->sg);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -478,8 +475,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		imxdmac->internal.sg = NULL;
-
 		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
 		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
 		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
@@ -495,7 +490,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		imxdmac->internal.sg = d->sg;
 		imxdmac->internal.resbytes = d->len;
 
 		if (d->direction == DMA_DEV_TO_MEM) {
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:40 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:40 +0100
Subject: [PATCH v2 08/13] dmaengine: imx-dma: remove 'in_use' field of
 'internal' structure.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-9-git-send-email-javier.martin@vista-silicon.com>

It makes no sense keeping an 'in_use' flag when the multiple descriptor
mechanism already prevents a new DMA transfer to be issued when another
one is in course.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   10 ----------
 1 files changed, 0 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index ed94207..1e66ee6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -130,8 +130,6 @@ enum  imxdma_prep_type {
 struct imxdma_channel_internal {
 	unsigned int resbytes;
 
-	int in_use;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -266,9 +264,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 	pr_debug("imxdma%d: imx_dma_enable\n", channel);
 
-	if (imxdmac->internal.in_use)
-		return;
-
 	local_irq_save(flags);
 
 	imx_dmav1_writel(1 << channel, DMA_DISR);
@@ -287,7 +282,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 				DMA_CCR(channel));
 		}
 	}
-	imxdmac->internal.in_use = 1;
 
 	local_irq_restore(flags);
 }
@@ -307,7 +301,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
 			DMA_CCR(channel));
 	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdmac->internal.in_use = 0;
 	local_irq_restore(flags);
 }
 
@@ -317,7 +310,6 @@ static void imxdma_watchdog(unsigned long data)
 	int channel = imxdmac->channel;
 
 	imx_dmav1_writel(0, DMA_CCR(channel));
-	imxdmac->internal.in_use = 0;
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -436,7 +428,6 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 
 out:
 	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
 	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
@@ -470,7 +461,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
-	int ret;
 
 	/* Configure and enable */
 	switch (d->type) {
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:41 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:41 +0100
Subject: [PATCH v2 09/13] dmaengine: imx-dma: remove 'resbytes' field of
 'internal' structure.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-10-git-send-email-javier.martin@vista-silicon.com>

Use per-descriptor 'len' field to keep track of the remaining bytes
instead. This goes on the direction of eventually removing the
'internal' structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   11 +++--------
 1 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 1e66ee6..d525f1e 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -128,8 +128,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	unsigned int resbytes;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -233,12 +231,11 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
 static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
-	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	unsigned long now;
 
-	now = min(imxdma->resbytes, sg->length);
-	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
-		imxdma->resbytes -= now;
+	now = min(d->len, sg->length);
+	if (d->len != IMX_DMA_LENGTH_LOOP)
+		d->len -= now;
 
 	if (d->direction == DMA_DEV_TO_MEM)
 		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
@@ -480,8 +477,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		imxdmac->internal.resbytes = d->len;
-
 		if (d->direction == DMA_DEV_TO_MEM) {
 			imx_dmav1_writel(imxdmac->per_address,
 					 DMA_SAR(imxdmac->channel));
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:42 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:42 +0100
Subject: [PATCH v2 10/13] dmaengine: imx-dma: remove internal structure.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-11-git-send-email-javier.martin@vista-silicon.com>

This structure was created to allow an smoothless
merge but was meant to be removed. Remaining members
'hw_chaining' and 'watchdog' are moved to the channel
structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   64 +++++++++++++-----------------------------------
 1 files changed, 18 insertions(+), 46 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index d525f1e..2f72447 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -110,29 +110,6 @@ enum  imxdma_prep_type {
 	IMXDMA_DESC_CYCLIC,
 };
 
-/*
- * struct imxdma_channel_internal - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- *            (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imxdma_channel_internal only as extension to it.
- */
-
-struct imxdma_channel_internal {
-	struct timer_list watchdog;
-
-	int hw_chaining;
-};
-
 struct imxdma_desc {
 	struct list_head		node;
 	struct dma_async_tx_descriptor	desc;
@@ -155,7 +132,8 @@ struct imxdma_desc {
 };
 
 struct imxdma_channel {
-	struct imxdma_channel_internal	internal;
+	int				hw_chaining;
+	struct timer_list		watchdog;
 	struct imxdma_engine		*imxdma;
 	unsigned int			channel;
 
@@ -217,10 +195,10 @@ static unsigned imx_dmav1_readl(unsigned offset)
 	return __raw_readl(imx_dmav1_baseaddr + offset);
 }
 
-static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
+static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 {
 	if (cpu_is_mx27())
-		return imxdma->hw_chaining;
+		return imxdmac->hw_chaining;
 	else
 		return 0;
 }
@@ -269,7 +247,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+			d->sg && imxdma_hw_chain(imxdmac)) {
 		d->sg = sg_next(d->sg);
 		if (d->sg) {
 			u32 tmp;
@@ -290,8 +268,8 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 
 	pr_debug("imxdma%d: imx_dma_disable\n", channel);
 
-	if (imxdma_hw_chain(&imxdmac->internal))
-		del_timer(&imxdmac->internal.watchdog);
+	if (imxdma_hw_chain(imxdmac))
+		del_timer(&imxdmac->watchdog);
 
 	local_irq_save(flags);
 	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
@@ -316,7 +294,6 @@ static void imxdma_watchdog(unsigned long data)
 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 {
 	struct imxdma_engine *imxdma = dev_id;
-	struct imxdma_channel_internal *internal;
 	unsigned int err_mask;
 	int i, disr;
 	int errcode;
@@ -336,7 +313,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (!(err_mask & (1 << i)))
 			continue;
-		internal = &imxdma->channel[i].internal;
 		errcode = 0;
 
 		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
@@ -370,7 +346,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 
 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
-	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
@@ -394,11 +369,11 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
-			if (imxdma_hw_chain(imxdma)) {
+			if (imxdma_hw_chain(imxdmac)) {
 				/* FIXME: The timeout should probably be
 				 * configurable
 				 */
-				mod_timer(&imxdma->watchdog,
+				mod_timer(&imxdmac->watchdog,
 					jiffies + msecs_to_jiffies(500));
 
 				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
@@ -417,8 +392,8 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 			return;
 		}
 
-		if (imxdma_hw_chain(imxdma)) {
-			del_timer(&imxdma->watchdog);
+		if (imxdma_hw_chain(imxdmac)) {
+			del_timer(&imxdmac->watchdog);
 			return;
 		}
 	}
@@ -432,7 +407,6 @@ out:
 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 {
 	struct imxdma_engine *imxdma = dev_id;
-	struct imxdma_channel_internal *internal;
 	int i, disr;
 
 	if (cpu_is_mx21() || cpu_is_mx27())
@@ -445,10 +419,8 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 
 	imx_dmav1_writel(disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (disr & (1 << i)) {
-			internal = &imxdma->channel[i].internal;
+		if (disr & (1 << i))
 			dma_irq_handle_channel(&imxdma->channel[i]);
-		}
 	}
 
 	return IRQ_HANDLED;
@@ -591,8 +563,8 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			break;
 		}
 
-		imxdmac->internal.hw_chaining = 1;
-		if (!imxdma_hw_chain(&imxdmac->internal))
+		imxdmac->hw_chaining = 1;
+		if (!imxdma_hw_chain(imxdmac))
 			return -EINVAL;
 		imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
 			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
@@ -944,7 +916,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	/* Initialize channel parameters */
 	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
 		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-		memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+
 		if (cpu_is_mx21() || cpu_is_mx27()) {
 			ret = request_irq(MX2x_INT_DMACH0 + i,
 					dma_irq_handler, 0, "DMA", imxdma);
@@ -953,9 +925,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
 						MX2x_INT_DMACH0 + i, i);
 				goto err_init;
 			}
-			init_timer(&imxdmac->internal.watchdog);
-			imxdmac->internal.watchdog.function = &imxdma_watchdog;
-			imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
+			init_timer(&imxdmac->watchdog);
+			imxdmac->watchdog.function = &imxdma_watchdog;
+			imxdmac->watchdog.data = (unsigned long)imxdmac;
 		}
 
 		imxdmac->imxdma = imxdma;
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:43 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:43 +0100
Subject: [PATCH v2 11/13] dmaengine: imx-dma: remove unused arg of
 imxdma_sg_next.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-12-git-send-email-javier.martin@vista-silicon.com>

Since this function is always used with 'desc' as first argument
and 'desc->sg' as second argument, the latter is clearly redundant
and can be removed.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 2f72447..d65eec6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -206,9 +206,10 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 /*
  * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
  */
-static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct scatterlist *sg = d->sg;
 	unsigned long now;
 
 	now = min(d->len, sg->length);
@@ -251,7 +252,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		d->sg = sg_next(d->sg);
 		if (d->sg) {
 			u32 tmp;
-			imxdma_sg_next(d, d->sg);
+			imxdma_sg_next(d);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -365,7 +366,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		desc->sg = sg_next(desc->sg);
 
 		if (desc->sg) {
-			imxdma_sg_next(desc, desc->sg);
+			imxdma_sg_next(desc);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -475,7 +476,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 			return -EINVAL;
 		}
 
-		imxdma_sg_next(d, d->sg);
+		imxdma_sg_next(d);
 
 		break;
 	default:
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:44 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:44 +0100
Subject: [PATCH v2 12/13] dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and
 'dma_clk'.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-13-git-send-email-javier.martin@vista-silicon.com>

These global variables are integrated into the dmaengine structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |  169 +++++++++++++++++++++++++++----------------------
 1 files changed, 93 insertions(+), 76 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index d65eec6..fe0f126 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -160,6 +160,8 @@ struct imxdma_engine {
 	struct device			*dev;
 	struct device_dma_parameters	dma_parms;
 	struct dma_device		dma_device;
+	void __iomem			*base;
+	struct clk			*dma_clk;
 	struct imxdma_channel		channel[MAX_DMA_CHANNELS];
 };
 
@@ -181,18 +183,17 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 	return false;
 }
 
-/* TODO: put this inside any struct */
-static void __iomem *imx_dmav1_baseaddr;
-static struct clk *dma_clk;
 
-static void imx_dmav1_writel(unsigned val, unsigned offset)
+
+static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
+			     unsigned offset)
 {
-	__raw_writel(val, imx_dmav1_baseaddr + offset);
+	__raw_writel(val, imxdma->base + offset);
 }
 
-static unsigned imx_dmav1_readl(unsigned offset)
+static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
 {
-	return __raw_readl(imx_dmav1_baseaddr + offset);
+	return __raw_readl(imxdma->base + offset);
 }
 
 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
@@ -209,6 +210,7 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 static inline int imxdma_sg_next(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	struct scatterlist *sg = d->sg;
 	unsigned long now;
 
@@ -217,17 +219,19 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 		d->len -= now;
 
 	if (d->direction == DMA_DEV_TO_MEM)
-		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, sg->dma_address,
+				 DMA_DAR(imxdmac->channel));
 	else
-		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, sg->dma_address,
+				 DMA_SAR(imxdmac->channel));
 
-	imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+	imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
 
 	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
 		"size 0x%08x\n", imxdmac->channel,
-		 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
-		 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
-		 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
+		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
+		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
 
 	return now;
 }
@@ -235,6 +239,7 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 static void imxdma_enable_hw(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -242,10 +247,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 	local_irq_save(flags);
 
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
-		CCR_ACRPT, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
+			 ~(1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
+			 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
 			d->sg && imxdma_hw_chain(imxdmac)) {
@@ -253,9 +259,9 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		if (d->sg) {
 			u32 tmp;
 			imxdma_sg_next(d);
-			tmp = imx_dmav1_readl(DMA_CCR(channel));
-			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
-				DMA_CCR(channel));
+			tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
+			imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
+					 DMA_CCR(channel));
 		}
 	}
 
@@ -264,6 +270,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 {
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -273,19 +280,21 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 		del_timer(&imxdmac->watchdog);
 
 	local_irq_save(flags);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
-			DMA_CCR(channel));
-	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
+			 (1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
+			 ~CCR_CEN, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
 	local_irq_restore(flags);
 }
 
 static void imxdma_watchdog(unsigned long data)
 {
 	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 
-	imx_dmav1_writel(0, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -299,37 +308,37 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 	int i, disr;
 	int errcode;
 
-	disr = imx_dmav1_readl(DMA_DISR);
+	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
-	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
-		   imx_dmav1_readl(DMA_DRTOSR) |
-		   imx_dmav1_readl(DMA_DSESR)  |
-		   imx_dmav1_readl(DMA_DBOSR);
+	err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
+		   imx_dmav1_readl(imxdma, DMA_DRTOSR) |
+		   imx_dmav1_readl(imxdma, DMA_DSESR)  |
+		   imx_dmav1_readl(imxdma, DMA_DBOSR);
 
 	if (!err_mask)
 		return IRQ_HANDLED;
 
-	imx_dmav1_writel(disr & err_mask, DMA_DISR);
+	imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
 
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (!(err_mask & (1 << i)))
 			continue;
 		errcode = 0;
 
-		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBTOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
 			errcode |= IMX_DMA_ERR_BURST;
 		}
-		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DRTOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
 			errcode |= IMX_DMA_ERR_REQUEST;
 		}
-		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DSESR);
+		if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
 			errcode |= IMX_DMA_ERR_TRANSFER;
 		}
-		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
 			errcode |= IMX_DMA_ERR_BUFFER;
 		}
 		/* Tasklet error handler */
@@ -347,6 +356,7 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 
 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
@@ -368,7 +378,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		if (desc->sg) {
 			imxdma_sg_next(desc);
 
-			tmp = imx_dmav1_readl(DMA_CCR(chno));
+			tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
 
 			if (imxdma_hw_chain(imxdmac)) {
 				/* FIXME: The timeout should probably be
@@ -378,13 +388,14 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 					jiffies + msecs_to_jiffies(500));
 
 				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
-				imx_dmav1_writel(tmp, DMA_CCR(chno));
+				imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 			} else {
-				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+				imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
+						 DMA_CCR(chno));
 				tmp |= CCR_CEN;
 			}
 
-			imx_dmav1_writel(tmp, DMA_CCR(chno));
+			imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 
 			if (imxdma_chan_is_doing_cyclic(imxdmac))
 				/* Tasklet progression */
@@ -400,7 +411,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 	}
 
 out:
-	imx_dmav1_writel(0, DMA_CCR(chno));
+	imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
 	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
@@ -413,12 +424,12 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 	if (cpu_is_mx21() || cpu_is_mx27())
 		imxdma_err_handler(irq, dev_id);
 
-	disr = imx_dmav1_readl(DMA_DISR);
+	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
 	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
 		     disr);
 
-	imx_dmav1_writel(disr, DMA_DISR);
+	imx_dmav1_writel(imxdma, disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (disr & (1 << i))
 			dma_irq_handle_channel(&imxdma->channel[i]);
@@ -435,12 +446,12 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
-		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
-		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+		imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
 			 DMA_CCR(imxdmac->channel));
 
-		imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
 
 		dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
 			"dma_length=%d\n", __func__, imxdmac->channel,
@@ -451,9 +462,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
 		if (d->direction == DMA_DEV_TO_MEM) {
-			imx_dmav1_writel(imxdmac->per_address,
+			imx_dmav1_writel(imxdma, imxdmac->per_address,
 					 DMA_SAR(imxdmac->channel));
-			imx_dmav1_writel(imxdmac->ccr_from_device,
+			imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
 					 DMA_CCR(imxdmac->channel));
 
 			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -461,9 +472,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 				__func__, imxdmac->channel, d->sg, d->sgcount,
 				d->len, imxdmac->per_address);
 		} else if (d->direction == DMA_MEM_TO_DEV) {
-			imx_dmav1_writel(imxdmac->per_address,
+			imx_dmav1_writel(imxdma, imxdmac->per_address,
 					 DMA_DAR(imxdmac->channel));
-			imx_dmav1_writel(imxdmac->ccr_to_device,
+			imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
 					 DMA_CCR(imxdmac->channel));
 
 			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -528,6 +539,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct dma_slave_config *dmaengine_cfg = (void *)arg;
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	unsigned long flags;
 	unsigned int mode = 0;
 
@@ -573,12 +585,12 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		imxdmac->ccr_to_device =
 			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
 			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
-		imx_dmav1_writel(imxdmac->dma_request,
+		imx_dmav1_writel(imxdma, imxdmac->dma_request,
 				 DMA_RSSR(imxdmac->channel));
 
 		/* Set burst length */
-		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
-				 DMA_BLR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, imxdmac->watermark_level *
+				imxdmac->word_size, DMA_BLR(imxdmac->channel));
 
 		return 0;
 	default:
@@ -863,27 +875,35 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	struct imxdma_engine *imxdma;
 	int ret, i;
 
-	if (cpu_is_mx1())
-		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
-	else if (cpu_is_mx21())
-		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
-	else if (cpu_is_mx27())
-		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
-	else
+
+	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
+	if (!imxdma)
+		return -ENOMEM;
+
+	if (cpu_is_mx1()) {
+		imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+	} else if (cpu_is_mx21()) {
+		imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+	} else if (cpu_is_mx27()) {
+		imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+	} else {
+		kfree(imxdma);
 		return 0;
+	}
 
-	dma_clk = clk_get(NULL, "dma");
-	if (IS_ERR(dma_clk))
-		return PTR_ERR(dma_clk);
-	clk_enable(dma_clk);
+	imxdma->dma_clk = clk_get(NULL, "dma");
+	if (IS_ERR(imxdma->dma_clk))
+		return PTR_ERR(imxdma->dma_clk);
+	clk_enable(imxdma->dma_clk);
 
 	/* reset DMA module */
-	imx_dmav1_writel(DCR_DRST, DMA_DCR);
+	imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
 
 	if (cpu_is_mx1()) {
 		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
 		if (ret) {
 			pr_crit("Can't register IRQ for DMA\n");
+			kfree(imxdma);
 			return ret;
 		}
 
@@ -891,22 +911,19 @@ static int __init imxdma_probe(struct platform_device *pdev)
 		if (ret) {
 			pr_crit("Can't register ERRIRQ for DMA\n");
 			free_irq(MX1_DMA_INT, NULL);
+			kfree(imxdma);
 			return ret;
 		}
 	}
 
 	/* enable DMA module */
-	imx_dmav1_writel(DCR_DEN, DMA_DCR);
+	imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
 
 	/* clear all interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
 
 	/* disable interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
-	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
-	if (!imxdma)
-		return -ENOMEM;
+	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
 
 	INIT_LIST_HEAD(&imxdma->dma_device.channels);
 
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Mar  7 09:33:45 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed,  7 Mar 2012 15:33:45 +0100
Subject: [PATCH v2 13/13] dmaengine: imx-dma: use 'dev_dbg' and 'dev_warn' for
 messages.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331130825-14947-14-git-send-email-javier.martin@vista-silicon.com>

There were some 'pr_crit' and 'pr_debug' messages due to the
initial merge. Replace them by 'dev_dbg' and 'dev_warn' to be
consistent.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   23 ++++++++++++-----------
 1 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index fe0f126..d1dee86 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -227,8 +227,8 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 
 	imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
 
-	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
-		"size 0x%08x\n", imxdmac->channel,
+	dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
+		"size 0x%08x\n", __func__, imxdmac->channel,
 		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
 		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
 		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
@@ -243,7 +243,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
-	pr_debug("imxdma%d: imx_dma_enable\n", channel);
+	dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
 
 	local_irq_save(flags);
 
@@ -274,7 +274,7 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
-	pr_debug("imxdma%d: imx_dma_disable\n", channel);
+	dev_dbg(imxdma->dev,"%s channel %d\n", __func__, channel);
 
 	if (imxdma_hw_chain(imxdmac))
 		del_timer(&imxdmac->watchdog);
@@ -298,7 +298,8 @@ static void imxdma_watchdog(unsigned long data)
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
-	pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+	dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
+		imxdmac->channel);
 }
 
 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
@@ -426,8 +427,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 
 	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
-	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
-		     disr);
+	dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
 
 	imx_dmav1_writel(imxdma, disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
@@ -902,14 +902,14 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	if (cpu_is_mx1()) {
 		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
 		if (ret) {
-			pr_crit("Can't register IRQ for DMA\n");
+			dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
 			kfree(imxdma);
 			return ret;
 		}
 
 		ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
 		if (ret) {
-			pr_crit("Can't register ERRIRQ for DMA\n");
+			dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
 			free_irq(MX1_DMA_INT, NULL);
 			kfree(imxdma);
 			return ret;
@@ -939,8 +939,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
 			ret = request_irq(MX2x_INT_DMACH0 + i,
 					dma_irq_handler, 0, "DMA", imxdma);
 			if (ret) {
-				pr_crit("Can't register IRQ %d for DMA channel %d\n",
-						MX2x_INT_DMACH0 + i, i);
+				dev_warn(imxdma->dev, "Can't register IRQ %d "
+					 "for DMA channel %d\n",
+					 MX2x_INT_DMACH0 + i, i);
 				goto err_init;
 			}
 			init_timer(&imxdmac->watchdog);
-- 
1.7.0.4



From jason at lakedaemon.net  Wed Mar  7 09:45:35 2012
From: jason at lakedaemon.net (Jason)
Date: Wed, 7 Mar 2012 09:45:35 -0500
Subject: [PATCH] mach-kirkwood: Support for DLink DNS-320 & DNS-325 NAS
In-Reply-To: <alpine.DEB.2.00.1203071332030.23719@marmot.wormnet.eu>
References: <alpine.DEB.2.02.1202121424080.16803@bunsen.wrottesley.wormnet.eu>
 <201202291440.10418.arnd@arndb.de>
 <20120301203917.GB11986@titan.lakedaemon.net>
 <alpine.DEB.2.00.1203071332030.23719@marmot.wormnet.eu>
Message-ID: <20120307144535.GZ5050@titan.lakedaemon.net>

On Wed, Mar 07, 2012 at 02:25:10PM +0000, Jamie Lentin wrote:
> On Thu, 1 Mar 2012, Jason wrote:
> 
> >On Wed, Feb 29, 2012 at 02:40:10PM +0000, Arnd Bergmann wrote:
> >>On Sunday 12 February 2012, Jamie Lentin wrote:
> >>>This patch adds support for the D-Link DNS-320 & DNS-325 NAS. Kirkwood-based
> >>>successors to the DNS-323.
> >>>
> >>>Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> >>>---
> >>>My previous patch supported just the DNS-325, the DNS-320 is a very similar
> >>>device and so I've combined the support for both devices into one board support
> >>>file. The main difference with the DNS-320 is that the temperature sensor
> >>>is accessed via ttyS1 instead of I2C (I have a userland script to do this).
> >>>
> >>>I appreciate board support files like this are old hat and should be using
> >>>device tree instead. If I should be focusing on that instead of getting this
> >>>merged, some pointers would be very useful.
> >>
> >>Hi Jamie,
> >>
> >>I just saw this patch going through the mailing list and noticed that you
> >>had sent it out another time before without getting any reply.
> >>
> >>I'm sorry that you did not get any feedback on this. Jason Cooper had a
> >>similar patch and he ended up a bit more fortunate than you, since he
> >>got support for the kirkwood based "dreamplug" into the arm-soc tree
> >>and is working on converting that to device tree now.
> >>
> >>I would suggest that you two team up and put DNS-32x support into the new
> >>common board-dt.c file as well.
> >
> >Jamie,
> >
> >Take a look at the dreamplug initial support patch series, latest here
> >[1].  Make a kirkwood-dns-320.dts and a kirkwood-dns-325.dts file
> >mimicing kirkwood-dreamplug.dts.  All you should need to start out is
> >the compatible property and memory.
> >
> >[1] http://www.spinics.net/lists/arm-kernel/msg161696.html
> 
> Excellent, thank you both! This is definitely enough to get me
> going. All the patches seem to be in staging/kirkwood/dt, is
> submitting based on this tree reasonable too?

newest version is here:

git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt

> Will try to use CONFIG_ARM_APPENDED_DTB to get it booting, as
> D-Link's u-boot is probably not devicetree aware. Or is there a
> better approach (apart from a JTAG programmer and replacing u-boot)?

That's fine for testing, but upgrading u-boot is definitely advised.  I
have yet to find a commercially distributed u-boot binary worth a d*mn.

> >>Some more comments:
> >>
> >>>diff --git a/arch/arm/mach-kirkwood/dnskw-setup.c b/arch/arm/mach-kirkwood/dnskw-setup.c
> >>>new file mode 100644
> >>>index 0000000..25ea0fa
> >>>--- /dev/null
> >>>+++ b/arch/arm/mach-kirkwood/dnskw-setup.c
> >>>@@ -0,0 +1,431 @@
> >>>+/*
> >>>+ * arch/arm/mach-kirkwood/dnskw-setup.c
> >>
> >>All future boards should ideally go through a single board file, and the plan
> >>is to work on minimizing the non-generic contents of that over time.
> >>Right now, it only contains support for the dreamplug, but there is no
> >>reason why this one couldn't get merged into it as well.
> >>
> 
> Definitely do-able, although I'm tempted to leave out anything
> non-essential to avoid board-dt.c becoming too unweildy. The MPP
> config and it's comments summarise my research, the rest is C+P code
> that could be reconstructed.

As more drivers are converted to DT, board-dt.c will shrink.  If pinmux
becomes too unwieldy, we can break it out into a separate file(s).

> >>>+static struct mtd_partition dnskw_nand_parts[] = {
> >>>+	{
> >>>+		.name		= "u-boot",
> >>>+		.offset		= 0,
> >>>+		.size		= SZ_1M,
> >>>+		.mask_flags	= MTD_WRITEABLE
> >>>+	}, {
> >>>+		.name		= "uImage",
> >>>+		.offset		= MTDPART_OFS_NXTBLK,
> >>>+		.size		= 5 * SZ_1M
> >>>+	}, {
> >>>+		.name		= "ramdisk",
> >>>+		.offset		= MTDPART_OFS_NXTBLK,
> >>>+		.size		= 5 * SZ_1M
> >>>+	}, {
> >>>+		.name		= "image",
> >>>+		.offset		= MTDPART_OFS_NXTBLK,
> >>>+		.size		= 102 * SZ_1M
> >>>+	}, {
> >>>+		.name		= "mini firmware",
> >>>+		.offset		= MTDPART_OFS_NXTBLK,
> >>>+		.size		= 10 * SZ_1M
> >>>+	}, {
> >>>+		.name		= "config",
> >>>+		.offset		= MTDPART_OFS_NXTBLK,
> >>>+		.size		= 5 * SZ_1M
> >>>+	},
> >>>+};
> >>
> >>Jason already has a patch for NAND partitions through the SPI attachment,
> >>I would suggest that you do the same for the nand controller, the patch
> >>should be fairly similar.
> >>
> 
> Found this and can see what needs doing. Will attempt this after
> getting the basic devicetree support sorted.
> 
> >>>+/*****************************************************************************
> >>>+ * Power controls
> >>>+ ****************************************************************************/
> >>>+
> >>>+static void dnskw_power_off(void)
> >>>+{
> >>>+	gpio_set_value(DNSKW_GPIO_POWER, 1);
> >>>+}
> >>>... <snip -- lots of gpio stuff>
> >>
> >>The entire gpio setup is rather complex, and I don't know how much of it
> >>can be handled with the existing gpio device tree bindings. I hope someone
> >>else can comment here.
> >>
> 
> Turning on the HDDs is something a lot of NASes need to do. I wonder
> if the functionality to do so should be added to sata_mv. I don't
> know anywhere near enough to say if this makes sense, but could have
> a wild stab at a patch if it's not completely stupid.

sata_mv is in the latest series.

> The power-recovery pin is probably just random D-Link weirdness. The
> GPIO needs to be raised high on each boot to ensure the NAS turns
> back on after power failure. Just operating it from userland would
> work, although registering as a GPIO off/on-able switch would be
> neater. I'm not sure if anything similar exists?
> 
> >>>+/*****************************************************************************
> >>>+ * Main init
> >>>+ ****************************************************************************/
> >>>+
> >>>+static void __init dnskw_init(void)
> >>>+{
> >>>+	u32 dev, rev;
> >>>+
> >>>+	/*
> >>>+	 * Basic setup. Needs to be called early.
> >>>+	 */
> >>>+	kirkwood_init();
> >>>+	kirkwood_mpp_conf(dnskw_mpp_config);
> >>
> >>There is now a kirkwood_dt_init function that calls the board specific
> >>functions based on an of_machine_is_compatible() check. Best add anything
> >>from this function in there that cannot be handled using device tree
> >>probing yet.
> >>
> >>>+	kirkwood_uart0_init();
> >>>+	kirkwood_uart1_init();
> >>
> >>These can be done from the device tree already.
> >>
> >>>+	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
> >>
> >>This is the one I mentioned above that I think you should try to convert.
> >>
> >>>+	kirkwood_ehci_init();

This is converted.

> >>>+	kirkwood_i2c_init();
> >>>+	kirkwood_ge00_init(&dnskw_ge00_data);

> >>>+	kirkwood_sata_init(&dnskw_sata_data);

And so is this one.

> >>
> >>These should be handled next, but not necessarily before this board
> >>supports makes it into the upstream kernel. Adding the bindings for
> >>these should be fairly straightforward, and it will get easier
> >>if kirkwood is first converted to use the generic clock framework.
> >
> >I've got a handle on these after I do xor and crypto.  If you get to it
> >before I do, hit sata and ge00/01.  I'll start with ehci and i2c.
> >
> 
> Okay---I'll let you know if I do get that far.

ge and i2c are going to take a little work and coordination with Andrew
Lunn, he's doing the common clock stuff for orion.

> >>>+#ifdef CONFIG_MACH_DNS320
> >>>+	if (machine_is_dns320())
> >>>+		platform_device_register(&dns320_led_device);
> >>>+#endif
> >>>+#ifdef CONFIG_MACH_DNS325
> >>>+	if (machine_is_dns325()) {
> >>>+		platform_device_register(&dns325_led_device);
> >>>+
> >>>+		i2c_register_board_info(0, dns325_i2c_board_info,
> >>>+					ARRAY_SIZE(dns325_i2c_board_info));
> >>>+	}
> >>>+#endif
> >>>+
> >>>+	/*
> >>>+	 * Turn on power to harddrives, then enable SATA.
> >>>+	 * NB: Bootloader should have turned sata0 on already, kernel needs
> >>>+	 * to turn on sata1. The idea is to stagger spin-up of HDDs.
> >>>+	 */
> >>>+	dnskw_gpio_register(DNSKW_GPIO_POWER_SATA0, "dnskw:power:sata0", 1);
> >>>+	dnskw_gpio_register(DNSKW_GPIO_POWER_SATA1, "dnskw:power:sata1", 1);
> >>>+
> >>>+	platform_device_register(&dnskw_button_device);
> >>>+	platform_device_register(&dnskw_fan_device);
> >>
> >>It should be possible to handle all this by putting the right devices
> >>into the device tree, but I don't know how to do that.
> >>
> 
> arch/arm/boot/dts/imx53-qsb.dts amongst others have some examples,
> will steal them and see what happens.
> 
> >>>+	/* Register power off routine */
> >>>+	kirkwood_pcie_id(&dev, &rev);
> >>>+	if (dev == MV88F6281_DEV_ID) {
> >>>+		pr_info("PCI-E Device ID: MV88F6281, configuring power-off");
> >>>+		if (gpio_request(DNSKW_GPIO_POWER, "dnskw:power:off") == 0 &&
> >>>+		    gpio_direction_output(DNSKW_GPIO_POWER, 0) == 0)
> >>>+			pm_power_off = dnskw_power_off;
> >>>+		else
> >>>+			pr_err("dnskw: failed to configure power-off GPIO\n");
> >>>+	} else {
> >>>+		/*
> >>>+		 * Dlink code also defines 0x6192, and sets LOW_BASE +
> >>>+		 * 0x01000000 high. Either cargo-culted code or another model.
> >>>+		 */
> >>>+		pr_err("Unknown PCI-E Device ID %x, no power-off", dev);
> >>>+	}
> >>>+
> >>>+	/* Set state of power_recover pin */
> >>>+	if (gpio_request(DNSKW_GPIO_POWER_RECOVER, "dnskw:power:recover") == 0
> >>>+	 && gpio_direction_output(DNSKW_GPIO_POWER_RECOVER, 0) == 0) {
> >>>+		pr_info("dnskw: Setting power-recover %s\n",
> >>>+			power_recover_value ? "on" : "off");
> >>>+		gpio_set_value(DNSKW_GPIO_POWER_RECOVER, power_recover_value);
> >>>+	} else
> >>>+		pr_err("dnskw: Failed to register power-recover GPIO\n");
> >>>+}
> >>
> >>This might have to stay board specific.
> >>
> >>>+#ifdef CONFIG_MACH_DNS320
> >>>+MACHINE_START(DNS320, "D-Link DNS-320")
> >>>+	/* Maintainer: Jamie Lentin <jm at lentin.co.uk> */
> >>>+	.atag_offset	= 0x100,
> >>>+	.init_machine	= dnskw_init,
> >>>+	.map_io		= kirkwood_map_io,
> >>>+	.init_early	= kirkwood_init_early,
> >>>+	.init_irq	= kirkwood_init_irq,
> >>>+	.timer		= &kirkwood_timer,
> >>>+	.restart	= kirkwood_restart,
> >>>+MACHINE_END
> >>>+#endif
> >>>+
> >>>+#ifdef CONFIG_MACH_DNS325
> >>>+MACHINE_START(DNS325, "D-Link DNS-325")
> >>>+	/* Maintainer: Jamie Lentin <jm at lentin.co.uk> */
> >>>+	.atag_offset	= 0x100,
> >>>+	.init_machine	= dnskw_init,
> >>>+	.map_io		= kirkwood_map_io,
> >>>+	.init_early	= kirkwood_init_early,
> >>>+	.init_irq	= kirkwood_init_irq,
> >>>+	.timer		= &kirkwood_timer,
> >>>+	.restart	= kirkwood_restart,
> >>>+MACHINE_END
> >>>+#endif
> >>
> >>Just use DT_MACHINE_START here and remove the machine ID and atag_offset. See
> >>the board-dt.c file.
> >
> >See the link [1], above.
> >
> >thx,
> >
> >Jason.
> >
> 
> -- 
> Jamie Lentin


From paul.gortmaker at windriver.com  Wed Mar  7 09:46:08 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Wed, 7 Mar 2012 09:46:08 -0500
Subject: [PATCH v2] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
References: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
Message-ID: <4F5774B0.1030209@windriver.com>

On 12-03-06 08:46 PM, Paul Parsons wrote:
> --- On Tue, 6/3/12, Paul Gortmaker <paul.gortmaker at windriver.com> wrote:
>> commit
>> 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)
>>
>>   "regulator: Remove support for supplies specified by
>> struct device"
>>
>> deletes the field from the struct, but this platform was
>> still trying
>> to set those fields.  Convert them to use the
>> REGULATOR_SUPPLY macro
>> so as to fix this failure:
>>
>> arch/arm/mach-pxa/magician.c:581: error: unknown field 'dev'
>> specified in initializer
>> arch/arm/mach-pxa/magician.c:581: warning: initialization
>> from incompatible pointer type
>> arch/arm/mach-pxa/magician.c:585: error: unknown field 'dev'
>> specified in initializer
>> arch/arm/mach-pxa/magician.c:585: warning: initialization
>> from incompatible pointer type
>>
>> arch/arm/mach-pxa/hx4700.c:683: error: unknown field 'dev'
>> specified in initializer
>> arch/arm/mach-pxa/hx4700.c:683: warning: initialization from
>> incompatible pointer type
>> arch/arm/mach-pxa/hx4700.c:687: error: unknown field 'dev'
>> specified in initializer
>> arch/arm/mach-pxa/hx4700.c:687: warning: initialization from
>> incompatible pointer type
>>
>> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
>> ---
>>
>> [v2: convert to using REGULATOR_SUPPLY instead of just
>> deleting the
>>  instances of setting the .dev field ]
>>
>> diff --git a/arch/arm/mach-pxa/hx4700.c
>> b/arch/arm/mach-pxa/hx4700.c
>> index f2c23ea..53c3366 100644
>> --- a/arch/arm/mach-pxa/hx4700.c
>> +++ b/arch/arm/mach-pxa/hx4700.c
>> @@ -679,14 +679,8 @@ static struct platform_device
>> power_supply = {
>>   */
>>  
>>  static struct regulator_consumer_supply bq24022_consumers[]
>> = {
>> -    {
>> -        .dev =
>> &gpio_vbus.dev,
>> -        .supply =
>> "vbus_draw",
>> -    },
>> -    {
>> -        .dev =
>> &power_supply.dev,
>> -        .supply = "ac_draw",
>> -    },
>> +    REGULATOR_SUPPLY("vbus_draw",
>> "gpio_vbus"),
>> +    REGULATOR_SUPPLY("ac_draw",
>> "power_supply"),
>>  };
> 
> The above hx4700 patch yields the following warnings:
> 
> _regulator_get: gpio-vbus supply vbus_draw not found, using dummy regulator
> _regulator_get: pda-power supply ac_draw not found, using dummy regulator
> 
> I suggest the following lines instead:
> 
> 	REGULATOR_SUPPLY("vbus_draw", "gpio-vbus"),
> 	REGULATOR_SUPPLY("ac_draw", "pda-power"),

Thanks for the report.  The regulator code is rather foreign
to me, but I think I figured out the expectations on the names
last night when looking at a similar patch here:

http://www.spinics.net/lists/arm-kernel/msg163418.html

I'll fix these two patches up, but next time I'll just report
the regulator regressions and let the sub-system maintainer
or the platform maintainer sort them out.

Paul.

> 


From linus.walleij at stericsson.com  Wed Mar  7 09:52:09 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 7 Mar 2012 15:52:09 +0100
Subject: [PATCH] watchdog/coh901327: convert to use watchdog core
Message-ID: <1331131929-22383-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This converts the COH901327 watchdog to use the watchdog core.
I followed Wolframs document, looked at some other drivers and
tested it on the U300.

Cc: Wolfram Sang <w.sang at pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/watchdog/Kconfig         |    1 +
 drivers/watchdog/coh901327_wdt.c |  148 ++++++++++----------------------------
 2 files changed, 40 insertions(+), 109 deletions(-)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 877b107..74c5f66 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -283,6 +283,7 @@ config COH901327_WATCHDOG
 	bool "ST-Ericsson COH 901 327 watchdog"
 	depends on ARCH_U300
 	default y if MACH_U300
+	select WATCHDOG_CORE
 	help
 	  Say Y here to include Watchdog timer support for the
 	  watchdog embedded into the ST-Ericsson U300 series platforms.
diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c
index 5b89f7d..3e6d899 100644
--- a/drivers/watchdog/coh901327_wdt.c
+++ b/drivers/watchdog/coh901327_wdt.c
@@ -9,7 +9,6 @@
 #include <linux/module.h>
 #include <linux/types.h>
 #include <linux/fs.h>
-#include <linux/miscdevice.h>
 #include <linux/watchdog.h>
 #include <linux/interrupt.h>
 #include <linux/pm.h>
@@ -74,8 +73,6 @@ static resource_size_t phybase;
 static resource_size_t physize;
 static int irq;
 static void __iomem *virtbase;
-static unsigned long coh901327_users;
-static unsigned long boot_status;
 static struct device *parent;
 
 /*
@@ -155,30 +152,31 @@ static void coh901327_disable(void)
 			__func__, val);
 }
 
-static void coh901327_start(void)
+static int coh901327_start(struct watchdog_device *wdt_dev)
 {
 	coh901327_enable(margin * 100);
+	return 0;
+}
+
+static int coh901327_stop(struct watchdog_device *wdt_dev)
+{
+	coh901327_disable();
+	return 0;
 }
 
-static void coh901327_keepalive(void)
+static int coh901327_ping(struct watchdog_device *wdd)
 {
 	clk_enable(clk);
 	/* Feed the watchdog */
 	writew(U300_WDOG_FR_FEED_RESTART_TIMER,
 	       virtbase + U300_WDOG_FR);
 	clk_disable(clk);
+	return 0;
 }
 
-static int coh901327_settimeout(int time)
+static int coh901327_settimeout(struct watchdog_device *wdt_dev,
+				unsigned int time)
 {
-	/*
-	 * Max margin is 327 since the 10ms
-	 * timeout register is max
-	 * 0x7FFF = 327670ms ~= 327s.
-	 */
-	if (time <= 0 || time > 327)
-		return -EINVAL;
-
 	margin = time;
 	clk_enable(clk);
 	/* Set new timeout value */
@@ -218,96 +216,18 @@ static irqreturn_t coh901327_interrupt(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
-/*
- * Allow only one user (daemon) to open the watchdog
- */
-static int coh901327_open(struct inode *inode, struct file *file)
-{
-	if (test_and_set_bit(1, &coh901327_users))
-		return -EBUSY;
-	coh901327_start();
-	return nonseekable_open(inode, file);
-}
-
-static int coh901327_release(struct inode *inode, struct file *file)
-{
-	clear_bit(1, &coh901327_users);
-	coh901327_disable();
-	return 0;
-}
-
-static ssize_t coh901327_write(struct file *file, const char __user *data,
-			       size_t len, loff_t *ppos)
-{
-	if (len)
-		coh901327_keepalive();
-	return len;
-}
-
-static long coh901327_ioctl(struct file *file, unsigned int cmd,
+static long coh901327_ioctl(struct watchdog_device *wdt_dev, unsigned int cmd,
 			    unsigned long arg)
 {
 	int ret = -ENOTTY;
 	u16 val;
-	int time;
-	int new_options;
 	union {
 		struct watchdog_info __user *ident;
 		int __user *i;
 	} uarg;
-	static const struct watchdog_info ident = {
-		.options		= WDIOF_CARDRESET |
-					  WDIOF_SETTIMEOUT |
-					  WDIOF_KEEPALIVEPING,
-		.identity		= "COH 901 327 Watchdog",
-		.firmware_version	= 1,
-	};
 	uarg.i = (int __user *)arg;
 
 	switch (cmd) {
-	case WDIOC_GETSUPPORT:
-		ret = copy_to_user(uarg.ident, &ident,
-				   sizeof(ident)) ? -EFAULT : 0;
-		break;
-
-	case WDIOC_GETSTATUS:
-		ret = put_user(0, uarg.i);
-		break;
-
-	case WDIOC_GETBOOTSTATUS:
-		ret = put_user(boot_status, uarg.i);
-		break;
-
-	case WDIOC_SETOPTIONS:
-		ret = get_user(new_options, uarg.i);
-		if (ret)
-			break;
-		if (new_options & WDIOS_DISABLECARD)
-			coh901327_disable();
-		if (new_options & WDIOS_ENABLECARD)
-			coh901327_start();
-		ret = 0;
-		break;
-
-	case WDIOC_KEEPALIVE:
-		coh901327_keepalive();
-		ret = 0;
-		break;
-
-	case WDIOC_SETTIMEOUT:
-		ret = get_user(time, uarg.i);
-		if (ret)
-			break;
-
-		ret = coh901327_settimeout(time);
-		if (ret)
-			break;
-		/* Then fall through to return set value */
-
-	case WDIOC_GETTIMEOUT:
-		ret = put_user(margin, uarg.i);
-		break;
-
 	case WDIOC_GETTIMELEFT:
 		clk_enable(clk);
 		/* Read repeatedly until the value is stable! */
@@ -324,24 +244,35 @@ static long coh901327_ioctl(struct file *file, unsigned int cmd,
 	return ret;
 }
 
-static const struct file_operations coh901327_fops = {
-	.owner		= THIS_MODULE,
-	.llseek		= no_llseek,
-	.write		= coh901327_write,
-	.unlocked_ioctl	= coh901327_ioctl,
-	.open		= coh901327_open,
-	.release	= coh901327_release,
+static const struct watchdog_info coh901327_ident = {
+	.options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
+	.identity = DRV_NAME,
+};
+
+static struct watchdog_ops coh901327_ops = {
+	.owner = THIS_MODULE,
+	.start = coh901327_start,
+	.stop = coh901327_stop,
+	.ping = coh901327_ping,
+	.set_timeout = coh901327_settimeout,
+	.ioctl = coh901327_ioctl,
 };
 
-static struct miscdevice coh901327_miscdev = {
-	.minor		= WATCHDOG_MINOR,
-	.name		= "watchdog",
-	.fops		= &coh901327_fops,
+static struct watchdog_device coh901327_wdt = {
+	.info = &coh901327_ident,
+	.ops = &coh901327_ops,
+	/*
+	 * Max margin is 327 since the 10ms
+	 * timeout register is max
+	 * 0x7FFF = 327670ms ~= 327s.
+	 */
+	.min_timeout = 0,
+	.max_timeout = 327,
 };
 
 static int __exit coh901327_remove(struct platform_device *pdev)
 {
-	misc_deregister(&coh901327_miscdev);
+	watchdog_unregister_device(&coh901327_wdt);
 	coh901327_disable();
 	free_irq(irq, pdev);
 	clk_put(clk);
@@ -350,7 +281,6 @@ static int __exit coh901327_remove(struct platform_device *pdev)
 	return 0;
 }
 
-
 static int __init coh901327_probe(struct platform_device *pdev)
 {
 	int ret;
@@ -393,7 +323,7 @@ static int __init coh901327_probe(struct platform_device *pdev)
 	case U300_WDOG_SR_STATUS_TIMED_OUT:
 		dev_info(&pdev->dev,
 			"watchdog timed out since last chip reset!\n");
-		boot_status = WDIOF_CARDRESET;
+		coh901327_wdt.bootstatus |= WDIOF_CARDRESET;
 		/* Status will be cleared below */
 		break;
 	case U300_WDOG_SR_STATUS_NORMAL:
@@ -435,7 +365,7 @@ static int __init coh901327_probe(struct platform_device *pdev)
 
 	clk_disable(clk);
 
-	ret = misc_register(&coh901327_miscdev);
+	ret = watchdog_register_device(&coh901327_wdt);
 	if (ret == 0)
 		dev_info(&pdev->dev,
 			 "initialized. timer margin=%d sec\n", margin);
@@ -547,4 +477,4 @@ module_param(margin, int, 0);
 MODULE_PARM_DESC(margin, "Watchdog margin in seconds (default 60s)");
 
 MODULE_LICENSE("GPL");
-MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
+MODULE_ALIAS("platform:coh901327-watchdog");
-- 
1.7.8



From broonie at opensource.wolfsonmicro.com  Wed Mar  7 09:57:17 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 7 Mar 2012 14:57:17 +0000
Subject: [PATCH v2] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <4F5774B0.1030209@windriver.com>
References: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
 <4F5774B0.1030209@windriver.com>
Message-ID: <20120307145717.GN3107@opensource.wolfsonmicro.com>

On Wed, Mar 07, 2012 at 09:46:08AM -0500, Paul Gortmaker wrote:

> Thanks for the report.  The regulator code is rather foreign
> to me, but I think I figured out the expectations on the names
> last night when looking at a similar patch here:

All it's looking for is the output of dev_name() for the device.
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From cjb at laptop.org  Wed Mar  7 09:59:57 2012
From: cjb at laptop.org (Chris Ball)
Date: Wed, 07 Mar 2012 09:59:57 -0500
Subject: [PATCH v2 0/6] mmc: omap_hsmmc: Clean up use/abuse of pdev->id
In-Reply-To: <4F57312E.4080104@ti.com> (Rajendra Nayak's message of "Wed, 07
 Mar 2012 15:28:06 +0530")
References: <1329996409-26861-1-git-send-email-rnayak@ti.com>
 <4F476228.7060607@ti.com> <4F54714E.6080805@ti.com>
 <4F57312E.4080104@ti.com>
Message-ID: <m2pqcoihhu.fsf@bob.laptop.org>

Hi Rajendra,

On Wed, Mar 07 2012, Rajendra Nayak wrote:
>> Chris, Ping. I am basing my DT support patches on top of these cleanups.
>> Would be great if you can have a look and pull them in.
>
> Chris, just realized the last two requests from me to get this merged
> weren't addressed to you directly, but instead you were copied.
> Resending with you in 'To', hope this lands in your inbox :)

Sorry for the delay, thanks for the ping; I've pushed these to mmc-next
for 3.4 now.

Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From balajitk at ti.com  Wed Mar  7 10:36:42 2012
From: balajitk at ti.com (T Krishnamoorthy, Balaji)
Date: Wed, 7 Mar 2012 21:06:42 +0530
Subject: [PATCH 4/4] mmc: omap_hsmmc: Simplify init for twl6030 MMC card
 detect
In-Reply-To: <CANrkHUZysOnHKKUuLm0Vbo1KsNp0yUd=udjGvQ43=gTTXbWeCw@mail.gmail.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185535.29210.71546.stgit@kaulin.local>
 <4F50643B.9050500@ti.com> <20120302172251.GJ18901@atomide.com>
 <4F548457.5050205@ti.com>
 <CANrkHUZysOnHKKUuLm0Vbo1KsNp0yUd=udjGvQ43=gTTXbWeCw@mail.gmail.com>
Message-ID: <CANrkHUaYDpv=p0p81oKWCoewyjheyZYkCqvZY7_ZQxWi_=8YFw@mail.gmail.com>

On Mon, Mar 5, 2012 at 3:55 PM, T Krishnamoorthy, Balaji
<balajitk at ti.com> wrote:
> On Mon, Mar 5, 2012 at 2:46 PM, Rajendra Nayak <rnayak at ti.com> wrote:
>> On Friday 02 March 2012 10:52 PM, Tony Lindgren wrote:
>>>
>>> BTW, with -rc5, looks like re-inserting omap_hsmmc on omap4 fails
>>> to detect any cards, and then fails to unload. This works on omap3
>>> just fine. Any ideas why that would be?
>>
>>
>> Yeah, looks like thats broken. I am not sure whats going wrong though.
>> I just enabled CONFIG_MMC_DEBUG and saw these logs below.
>>
>> Venkat/Balaji, care to look at this one?
>>
>
> Let me check this

OMAP4 and OMAP3 HSMMC IP registers differ by 0x100 offset.
Addng the offset to platform_device resource structure
increments the start address for every insmod operation.
MMC command fails on re-insertion as module due incorrect register base.
Fix this by updating the ioremap base address only.

Signed-off-by: Balaji T K <balajitk at ti.com>
---
Note:  eMMC detection is still failing on resertion due to card vcc
power off on rmmod

 drivers/mmc/host/omap_hsmmc.c |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index fd0c661..4e1f8f6 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1870,8 +1870,6 @@ static int __init omap_hsmmc_probe(struct
platform_device *pdev)
 	if (res == NULL || irq < 0)
 		return -ENXIO;

-	res->start += pdata->reg_offset;
-	res->end += pdata->reg_offset;
 	res = request_mem_region(res->start, resource_size(res), pdev->name);
 	if (res == NULL)
 		return -EBUSY;
@@ -1896,7 +1894,7 @@ static int __init omap_hsmmc_probe(struct
platform_device *pdev)
 	host->irq	= irq;
 	host->id	= pdev->id;
 	host->slot_id	= 0;
-	host->mapbase	= res->start;
+	host->mapbase	= res->start + pdata->reg_offset;
 	host->base	= ioremap(host->mapbase, SZ_4K);
 	host->power_mode = MMC_POWER_OFF;
 	host->next_data.cookie = 1;
-- 
1.7.0.4

>
>> # insmod omap_hsmmc.ko
>> [ ? 43.358398] omap_hsmmc omap_hsmmc.0: context was not lost
>> [ ? 43.364105] omap_hsmmc omap_hsmmc.0: enabled
>> [ ? 44.434661] mmc0: clock 0Hz busmode 1 powermode 0 cs 0 Vdd 0 width 0
>> timing 0
>> [ ? 44.442352] omap_hsmmc omap_hsmmc.0: Set clock to 0Hz
>> [ ? 44.474365] omap_hsmmc omap_hsmmc.0: disabled
>> [ ? 44.482208] omap_hsmmc omap_hsmmc.4: context was not lost
>> [ ? 44.482208] omap_hsmmc omap_hsmmc.4: enabled
>> [ ? 44.546600] omap_hsmmc omap_hsmmc.0: context was not lost
>> [ ? 44.552276] omap_hsmmc omap_hsmmc.0: enabled
>> [ ? 44.552276] mmc0: mmc_rescan_try_freq: trying to init card at 400000 Hz
>> [ ? 44.563720] mmc0: clock 0Hz busmode 2 powermode 1 cs 0 Vdd 18 width 0
>> timing 0
>> [ ? 44.572174] omap_hsmmc omap_hsmmc.0: Set clock to 0Hz
>> [ ? 44.613800] mmc0: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 18 width
>> 0 timing 0
>> [ ? 44.621887] omap_hsmmc omap_hsmmc.0: Set clock to 400000Hz
>> [ ? 44.735290] mmc0: starting CMD52 arg 00000c00 flags 00000195
>> [ ? 44.741271] omap_hsmmc omap_hsmmc.0: mmc0: CMD52, argument 0x00000c00
>> [ ? 45.560241] mmc1: clock 0Hz busmode 1 powermode 0 cs 0 Vdd 0 width 0
>> timing 0
>> [ ? 45.567871] omap_hsmmc omap_hsmmc.4: Set clock to 0Hz
>> [ ? 45.591491] omap_hsmmc omap_hsmmc.4: disabled
>> #
>> #
>> # rmmod omap_hsmmc
>> [ ?607.302307] omap_hsmmc omap_hsmmc.4: context was not lost
>> [ ?607.308044] omap_hsmmc omap_hsmmc.4: enabled
>> [ ?607.312591] omap_hsmmc omap_hsmmc.4: disabled
>> [ ?607.317199] omap_hsmmc omap_hsmmc.4: context was not lost
>> [ ?607.322875] omap_hsmmc omap_hsmmc.4: enabled
>>



-- 
Thanks and Regards,
Balaji T K


From cjb at laptop.org  Wed Mar  7 10:42:18 2012
From: cjb at laptop.org (Chris Ball)
Date: Wed, 07 Mar 2012 10:42:18 -0500
Subject: [PATCH 4/4] mmc: omap_hsmmc: Simplify init for twl6030 MMC card
 detect
In-Reply-To: <CANrkHUaYDpv=p0p81oKWCoewyjheyZYkCqvZY7_ZQxWi_=8YFw@mail.gmail.com>
 (T. Krishnamoorthy's message of "Wed, 7 Mar 2012 21:06:42 +0530")
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185535.29210.71546.stgit@kaulin.local>
 <4F50643B.9050500@ti.com> <20120302172251.GJ18901@atomide.com>
 <4F548457.5050205@ti.com>
 <CANrkHUZysOnHKKUuLm0Vbo1KsNp0yUd=udjGvQ43=gTTXbWeCw@mail.gmail.com>
 <CANrkHUaYDpv=p0p81oKWCoewyjheyZYkCqvZY7_ZQxWi_=8YFw@mail.gmail.com>
Message-ID: <m2lincifj9.fsf@bob.laptop.org>

Hi Balaji,

On Wed, Mar 07 2012, T Krishnamoorthy, Balaji wrote:
> OMAP4 and OMAP3 HSMMC IP registers differ by 0x100 offset.
> Addng the offset to platform_device resource structure
> increments the start address for every insmod operation.
> MMC command fails on re-insertion as module due incorrect register base.
> Fix this by updating the ioremap base address only.
>
> Signed-off-by: Balaji T K <balajitk at ti.com>

Is this a regression, or has it never worked in mainline?

> Note:  eMMC detection is still failing on resertion due to card vcc
> power off on rmmod

And this?

Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From plagnioj at jcrosoft.com  Wed Mar  7 10:36:22 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 16:36:22 +0100
Subject: [PATCH v9] Regulator: Add Anatop regulator driver
In-Reply-To: <20120307134551.GL3107@opensource.wolfsonmicro.com>
References: <1331126658-26926-1-git-send-email-paul.liu@linaro.org>
 <20120307132225.GB17745@game.jcrosoft.org>
 <20120307134551.GL3107@opensource.wolfsonmicro.com>
Message-ID: <20120307153622.GC17745@game.jcrosoft.org>

On 13:45 Wed 07 Mar     , Mark Brown wrote:
> On Wed, Mar 07, 2012 at 02:22:25PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> > > +- compatible: Must be "fsl,anatop-regulator"
> > > +- vol-bit-shift: Bit shift for the register
> > > +- vol-bit-width: Number of bits used in the register
> > > +- min-bit-val: Minimum value of this register
> > > +- min-voltage: Minimum voltage of this regulator
> > > +- max-voltage: Maximum voltage of this regulator
> 
> > specific properites need to be prefix by the vendor
> 
> This really doesn't seem at all sane for a device which is already
> vendor specific, it's just noise in the bindings.
No it's
Here is a good example as we have regulator generic binding & vendor
specific bindig

Best Regards,
J.


From kgene.kim at samsung.com  Wed Mar  7 10:54:09 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 07 Mar 2012 07:54:09 -0800
Subject: [PATCH] ARM: SAMSUNG: change the name from s3c-sdhci to
 exynos4-sdhci
In-Reply-To: <00db01ccfc6a$d34c2ee0$79e48ca0$%szyprowski@samsung.com>
References: <4F45D343.6020409@samsung.com>
 <CAJuYYwTh8tVdA0X-TLEU-9O_M0_PmJR=i3WYAQXsaRcPF3MbJA@mail.gmail.com>
 <4F557692.8090102@samsung.com> <4F55DE1F.9010405@samsung.com>
 <4F576073.6010001@samsung.com>
 <00db01ccfc6a$d34c2ee0$79e48ca0$%szyprowski@samsung.com>
Message-ID: <4F5784A1.1080903@samsung.com>

On 03/07/12 06:01, Marek Szyprowski wrote:
> Hello,
>
> On Wednesday, March 07, 2012 2:20 PM Kukjin Kim wrote:
>
>> On 03/06/12 01:51, Kukjin Kim wrote:
>>> On 03/05/12 18:29, Jaehoon Chung wrote:
>>>> Hi Kukjin.
>>>>
>>>> Is it merged?
>>>>
>>>> Best Regards,
>>>> Jaehoon Chung
>>>>
>>>> On 02/24/2012 06:56 PM, Thomas Abraham wrote:
>>>>
>>>>> On 23 February 2012 11:18, Jaehoon Chung<jh80.chung at samsung.com>  wrote:
>>>>>> Thomas Arbrahams's patchset have changed the device name in sdhci-s3c.c
>>>>>> (mmc: sdhci-s3c: Rework platform data and add device tree support)
>>>>>> But didn't change the regulator_consumer name.
>>>>>> So maybe didn't initialize the mmc/sd card for exynos4.
>>>>>>
>>>>>> This patch is fixed that (based-on linux-samsung for-next branch)
>>>>>>
>>>>>> Signed-off-by: Jaehoon Chung<jh80.chung at samsung.com>
>>>>>> Signed-off-by: kyungmin Park<kyungmin.park at samsung.com>
>>>>>> ---
>>>>>> arch/arm/mach-exynos/mach-nuri.c | 4 ++--
>>>>>> arch/arm/mach-exynos/mach-universal_c210.c | 2 +-
>>>>>> 2 files changed, 3 insertions(+), 3 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm/mach-exynos/mach-nuri.c
>>>>>> b/arch/arm/mach-exynos/mach-nuri.c
>>>>>> index a6b9162..251dd7a 100644
>>>>>> --- a/arch/arm/mach-exynos/mach-nuri.c
>>>>>> +++ b/arch/arm/mach-exynos/mach-nuri.c
>>>>>> @@ -116,7 +116,7 @@ static struct s3c_sdhci_platdata
>>>>>> nuri_hsmmc0_data __initdata = {
>>>>>> };
>>>>>>
>>>>>> static struct regulator_consumer_supply emmc_supplies[] = {
>>>>>> - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
>>>>>> + REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
>>>>>> REGULATOR_SUPPLY("vmmc", "dw_mmc"),
>>>>>> };
>>>>>>
>>>>>> @@ -415,7 +415,7 @@ static struct regulator_consumer_supply
>>>>>> __initdata max8997_ldo12_[] = {
>>>>>> REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
>>>>>> };
>>>>>> static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
>>>>>> - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
>>>>>> + REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
>>>>>> };
>>>>>> static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
>>>>>> REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
>>>>>> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c
>>>>>> b/arch/arm/mach-exynos/mach-universal_c210.c
>>>>>> index 6017a21..320cb1d 100644
>>>>>> --- a/arch/arm/mach-exynos/mach-universal_c210.c
>>>>>> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
>>>>>> @@ -749,7 +749,7 @@ static struct s3c_sdhci_platdata
>>>>>> universal_hsmmc0_data __initdata = {
>>>>>> };
>>>>>>
>>>>>> static struct regulator_consumer_supply mmc0_supplies[] = {
>>>>>> - REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
>>>>>> + REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
>>>>>> };
>>>>>>
>>>>>> static struct regulator_init_data mmc0_fixed_voltage_init_data = {
>>>>>
>>>>> Reviewed-by: Thomas Abraham<thomas.abraham at linaro.org>
>>>
>>> Looks OK, will apply.
>>>
>>
>> (Cc'ed Marek)
>>
>> Hi Kyungmin, Marek and Jaehoon,
>>
>> As you know, same patches have been submitted duplicated and this should
>> be fixed. Which one would be better to send upstream?
>
> For me it doesn't matter, I just need this fix to get merged, because otherwise
> the Universal C210 and Nuri boards are dysfunctional.
>
> You can select the one prepared by Jaehoon if You like.

OK, thanks :)

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From Russ.Dill at ti.com  Wed Mar  7 11:00:08 2012
From: Russ.Dill at ti.com (Russ Dill)
Date: Wed, 7 Mar 2012 10:00:08 -0600
Subject: [PATCH v3] ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
 regulators
In-Reply-To: <87pqcqnc7u.fsf@ti.com>
References: <1330006564-13290-1-git-send-email-mporter@ti.com>
 <87wr74gis6.fsf@ti.com>
 <20120301204553.GA21841@legolas.emea.dhcp.ti.com>
 <87pqcqnc7u.fsf@ti.com>
Message-ID: <CA+Bv8XaJqL1L8F-n6skY7dHn1XAdDLRKaRjw0deLeoQ5Ao0Fhg@mail.gmail.com>

On Mon, Mar 5, 2012 at 12:18 PM, Kevin Hilman <khilman at ti.com> wrote:
> Felipe Balbi <balbi at ti.com> writes:
>
>> Hi,
>>
>> On Thu, Mar 01, 2012 at 12:36:57PM -0800, Kevin Hilman wrote:
>>> Matt Porter <mporter at ti.com> writes:
>>>
>>> > This fixes smsc911x support on platforms using gpmc_smsc911x_init().
>>> >
>>> > Commit c7e963f6888816 (net/smsc911x: Add regulator support) added
>>> > the requirement that platforms provide vdd33a and vddvario supplies.
>>> >
>>> > Signed-off-by: Matt Porter <mporter at ti.com>
>>>
>>> [...]
>>>
>>> > ?/*
>>> > ? * Initialize smsc911x device connected to the GPMC. Note that we
>>> > ? * assume that pin multiplexing is done in the board-*.c file,
>>> > @@ -55,6 +101,12 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
>>> >
>>> > ? ?gpmc_cfg = board_data;
>>> >
>>> > + ?ret = platform_device_register(&gpmc_smsc911x_regulator);
>>> > + ?if (ret < 0) {
>>> > + ? ? ? ? ?pr_err("Unable to register smsc911x regulators: %d\n", ret);
>>> > + ? ? ? ? ?return;
>>> > + ?}
>>> > +
>>>
>>> Boards that have more than one instance of the smsc911x (OMAP3/Overo)
>>> barf here because of trying to register the same device twice.
>>>
>>> We need something like the patch below to make Overo boot again.
>>>
>>> Kevin
>>>
>>>
>>>
>>> From 4114dea2fb897ab75d05eaa943d29454034fc025 Mon Sep 17 00:00:00 2001
>>> From: Kevin Hilman <khilman at ti.com>
>>> Date: Thu, 1 Mar 2012 12:30:42 -0800
>>> Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulators once
>>>
>>> commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
>>> regulators) added regulators which are registered during
>>> gpmc_smsc911x_init(). ?However, some platforms (OMAP3/Overo) have more
>>> than one instance of the SMSC911x and result in attempting to register
>>> the same regulator more than once which causes a panic(). ?Fix this by
>>> tracking the regulator registration ensuring only a single device is
>>> registered.
>>>
>>> Cc: Matt Porter <mporter at ti.com>
>>> Signed-off-by: Kevin Hilman <khilman at ti.com>
>>> ---
>>> ?arch/arm/mach-omap2/gpmc-smsc911x.c | ? 14 ++++++++++----
>>> ?1 file changed, 10 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
>>> index bbb870c..95e6c7d 100644
>>> --- a/arch/arm/mach-omap2/gpmc-smsc911x.c
>>> +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
>>> @@ -88,6 +88,8 @@ static struct platform_device gpmc_smsc911x_regulator = {
>>> ? ? ?},
>>> ?};
>>>
>>> +static bool regulator_registered;
>>> +
>>> ?/*
>>> ? * Initialize smsc911x device connected to the GPMC. Note that we
>>> ? * assume that pin multiplexing is done in the board-*.c file,
>>> @@ -101,10 +103,14 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
>>>
>>> ? ? ?gpmc_cfg = board_data;
>>>
>>> - ? ?ret = platform_device_register(&gpmc_smsc911x_regulator);
>>> - ? ?if (ret < 0) {
>>> - ? ? ? ? ? ?pr_err("Unable to register smsc911x regulators: %d\n", ret);
>>> - ? ? ? ? ? ?return;
>>> + ? ?if (!regulator_registered) {
>>> + ? ? ? ? ? ?ret = platform_device_register(&gpmc_smsc911x_regulator);
>>> + ? ? ? ? ? ?if (ret < 0) {
>>> + ? ? ? ? ? ? ? ? ? ?pr_err("Unable to register smsc911x regulators: %d\n",
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ret);
>>> + ? ? ? ? ? ? ? ? ? ?return;
>>> + ? ? ? ? ? ?}
>>> + ? ? ? ? ? ?regulator_registered = true;
>>
>> Wow, this is quite a hack. Is the regulator part of the SMSC911x
>> device or is it outside ? If it's outside the SMSC91xx (which I
>> believe it is) there should be a regulator driver instead of this
>> hack. ?For boards which don't provide such a regulator (and tie the
>> supply pin to some constant voltage source) there should be a constant
>> regulator supplying the pin. But this patch is quite hacky.
>
> Are you referring to my patch or to the original $SUBJECT patch? ?It's
> not terribly clear.
>
> My patch doesn't add any regulators, it just fixes a bug when this init
> function is called more than once.
>
> The addition of the regulators was done in $SUBJECT patch, not my fix.
>
> In either case $SUBJECT patch is already in Tony's fixes queue, so if it
> is going be merged, then my fix above is needed also to not break
> Overo and any other platform that has more than one smsc911x instance.
>
> Kevin


Have you tested this fix? The only regulator consumer supply would be:

static struct regulator_consumer_supply gpmc_smsc911x_supply[] = {
        REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
        REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
};

I don't think the second smsc911x on the Overo, "smsc911x.1", would
find it due to the dev_id.


From jp.francois at cynove.com  Wed Mar  7 11:16:35 2012
From: jp.francois at cynove.com (jean-philippe francois)
Date: Wed, 7 Mar 2012 17:16:35 +0100
Subject: soft lockup on omap3 (dm3730)
Message-ID: <CAGGh5h3OQTniXbm8iUYGM+2oi+zzd1F6BxDKzN5epA89+i_7nQ@mail.gmail.com>

Hi,

I have a custom board using a dm3730 processor, on which I
am running a 3.2.0 kernel.

There is also a cmos sensor (aptina MT9J). When I use yavta
to capture video, it will always work on the first capture, but if
yavta is stopped, and then restarted, it will often get stuck in the
below function

spinlock, mutex and list manipulation debug options are on, but catch nothing.
The printk get printed, and the number of step in the loop is equal to
the number
of queued buffer.

According to the offset in the backtrace, the soft_lockup is either
in spin_unlock_irqrestore if spinlock debugging is activated, or
on the "msr CPSR_c"  instruction if spinlock debugging is not activated.

Is the backtrace pointing to this offset because soft_lockup can only
detect lockups at the output of critical sections ?

I don't know how to progress on this problem, any hint is welcome.

int omap3isp_video_queue_streamon(struct isp_video_queue *queue)
{
       struct isp_video_buffer *buf;
       unsigned long flags;

       mutex_lock(&queue->lock);

       if (queue->streaming)
               goto done;

       queue->streaming = 1;

       spin_lock_irqsave(&queue->irqlock, flags);
       list_for_each_entry(buf, &queue->queue, stream) {
               printk(KERN_INFO "inside list_for_each\n");
               queue->ops->buffer_queue(buf);
       }
       spin_unlock_irqrestore(&queue->irqlock, flags);  <---- soft lockup
says this is the culprit.

done:
       mutex_unlock(&queue->lock);
       return 0;
}


From m.szyprowski at samsung.com  Wed Mar  7 11:17:25 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 07 Mar 2012 17:17:25 +0100
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <20120306232138.GF15201@n2100.arm.linux.org.uk>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <20120306232138.GF15201@n2100.arm.linux.org.uk>
Message-ID: <00f801ccfc7d$c8da6810$5a8f3830$%szyprowski@samsung.com>

Hello,

On Wednesday, March 07, 2012 12:22 AM Russell King - ARM Linux wrote:

> On Wed, Feb 29, 2012 at 04:04:22PM +0100, Marek Szyprowski wrote:
> > +static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
> > +		    void *cpu_addr, dma_addr_t dma_addr, size_t size,
> > +		    struct dma_attrs *attrs)
> > +{
> > +	struct arm_vmregion *c;
> > +
> > +	vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
> > +	c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
> 
> What protects this against other insertions/removals from the list?

arm_vmregion_* functions have their own spinlock.

(snipped)

> > +	if (c) {
> > +		struct page **pages = c->priv;
> > +		__dma_free_remap(cpu_addr, size);
> > +		__iommu_remove_mapping(dev, handle, size);
> > +		__iommu_free_buffer(dev, pages, size);
> > +	}
> > +}
> > +
> > +/*
> > + * Map a part of the scatter-gather list into contiguous io address space
> > + */
> > +static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
> > +			  size_t size, dma_addr_t *handle,
> > +			  enum dma_data_direction dir)
> > +{
> > +	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
> > +	dma_addr_t iova, iova_base;
> > +	int ret = 0;
> > +	unsigned int count;
> > +	struct scatterlist *s;
> > +
> > +	size = PAGE_ALIGN(size);
> > +	*handle = ARM_DMA_ERROR;
> > +
> > +	iova_base = iova = __alloc_iova(mapping, size);
> > +	if (iova == ARM_DMA_ERROR)
> > +		return -ENOMEM;
> > +
> > +	for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s))
> > +	{
> > +		phys_addr_t phys = page_to_phys(sg_page(s));
> > +		unsigned int len = PAGE_ALIGN(s->offset + s->length);
> > +
> > +		if (!arch_is_coherent())
> > +			__dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
> > +
> > +		ret = iommu_map(mapping->domain, iova, phys, len, 0);
> 
> Dealing with phys addresses on one part and pages + offset + length
> in a different part doesn't look like a good idea.  Why can't there
> be some consistency?

Well, I have no idea how to be more consistent here. scatter-lists operates on 
pages + offsets + length parameters. iommu api operates on the whole pages, but
they are referred with physical address. Right now I cannot change any of it, 
at least not it the near future.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From broonie at opensource.wolfsonmicro.com  Wed Mar  7 11:28:22 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 7 Mar 2012 16:28:22 +0000
Subject: [PATCH v9] Regulator: Add Anatop regulator driver
In-Reply-To: <20120307153622.GC17745@game.jcrosoft.org>
References: <1331126658-26926-1-git-send-email-paul.liu@linaro.org>
 <20120307132225.GB17745@game.jcrosoft.org>
 <20120307134551.GL3107@opensource.wolfsonmicro.com>
 <20120307153622.GC17745@game.jcrosoft.org>
Message-ID: <20120307162821.GP3107@opensource.wolfsonmicro.com>

On Wed, Mar 07, 2012 at 04:36:22PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:

> > This really doesn't seem at all sane for a device which is already
> > vendor specific, it's just noise in the bindings.

> No it's

...?

> Here is a good example as we have regulator generic binding & vendor
> specific bindig

It's not vendor specific, it's device specific and people are doing it
even for devices with no generic bindings at all which is particularly
silly.

Device specific prefixes probably make sense, but vendor specific ones
are just noise.
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From linux at arm.linux.org.uk  Wed Mar  7 11:37:50 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 16:37:50 +0000
Subject: soft lockup on omap3 (dm3730)
In-Reply-To: <CAGGh5h3OQTniXbm8iUYGM+2oi+zzd1F6BxDKzN5epA89+i_7nQ@mail.gmail.com>
References: <CAGGh5h3OQTniXbm8iUYGM+2oi+zzd1F6BxDKzN5epA89+i_7nQ@mail.gmail.com>
Message-ID: <20120307163750.GC18787@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 05:16:35PM +0100, jean-philippe francois wrote:
> Is the backtrace pointing to this offset because soft_lockup can only
> detect lockups at the output of critical sections ?

Correct - soft lockups on ARM can only be detected when hardware
interrupts are enabled.  Any region which masks hard interrupts
effectively prevents the soft lockup detector firing should
execution get stuck inside such a region.

> I don't know how to progress on this problem, any hint is welcome.
> 
> int omap3isp_video_queue_streamon(struct isp_video_queue *queue)
> {
>        struct isp_video_buffer *buf;
>        unsigned long flags;
> 
>        mutex_lock(&queue->lock);
> 
>        if (queue->streaming)
>                goto done;
> 
>        queue->streaming = 1;
> 
>        spin_lock_irqsave(&queue->irqlock, flags);
>        list_for_each_entry(buf, &queue->queue, stream) {
>                printk(KERN_INFO "inside list_for_each\n");
>                queue->ops->buffer_queue(buf);
>        }
>        spin_unlock_irqrestore(&queue->irqlock, flags);  <---- soft lockup
> says this is the culprit.

My guess is something inside buffer_queue() is responsible.  If things
get stuck for quite a period of time, the only thing I can suggest is
using printk() based debugging to try and find where things get stuck.


From plagnioj at jcrosoft.com  Wed Mar  7 11:28:00 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 17:28:00 +0100
Subject: [PULL] of nand generic binding
In-Reply-To: <4F576602.8020808@gmail.com>
References: <20120217155707.GR1214@game.jcrosoft.org>
 <20120229152534.GH3318@game.jcrosoft.org>
 <20120307082945.GJ21255@game.jcrosoft.org>
 <4F576602.8020808@gmail.com>
Message-ID: <20120307162800.GD17745@game.jcrosoft.org>

On 07:43 Wed 07 Mar     , Rob Herring wrote:
> On 03/07/2012 02:29 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 16:25 Wed 29 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> >> On 16:57 Fri 17 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>> HI,
> >>>
> >>> 	please find attached the generic binding for the MTD nand
> >>>
> >>> 	This will add boolean and nand helpers
> >> is it ok?
> > I need this for 3.4
> > 
> > will you apply it or can I apply it via AT91
> 
> Looks fine to me and Grant acked it, so go ahead and take with your at91
> branch.
tks

can you take a look on i2c-gpio and usb and dma_mask patch I send

I wish them to go for 3.4

so I'll have 60 to 80% of the drivers depending on the soc.

for 3.5 we need to finish some cleanup to have finnaly multiple at91 SoC in
the same kernel and add more drivers to DT.

This will allow people to have DT-only kernel on at91 for they board.

Best Regards,
J.


From w.sang at pengutronix.de  Wed Mar  7 11:42:40 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed, 7 Mar 2012 17:42:40 +0100
Subject: [PATCH] watchdog/coh901327: convert to use watchdog core
In-Reply-To: <1331131929-22383-1-git-send-email-linus.walleij@stericsson.com>
References: <1331131929-22383-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20120307164240.GA1130@pengutronix.de>

Hi Linus,

> -static long coh901327_ioctl(struct file *file, unsigned int cmd,
> +static long coh901327_ioctl(struct watchdog_device *wdt_dev, unsigned int cmd,
>  			    unsigned long arg)
>  {
>  	int ret = -ENOTTY;
>  	u16 val;
> -	int time;
> -	int new_options;
>  	union {
>  		struct watchdog_info __user *ident;
>  		int __user *i;
>  	} uarg;

'uarg' is nice name for the union ;) You probably don't need that anymore.
If we keep the ioctl, that is, because...

...

>  	case WDIOC_GETTIMELEFT:
>  		clk_enable(clk);
>  		/* Read repeatedly until the value is stable! */

I was wondering if it pays to put this IOCTL to watchdog_dev and add another
callback to watchdog_ops? I'd think so. Wim, Linus, what do you think? We don't
save much (yet?), but since this is part of the kernel-API it might be nice to
have the common part centralized, even if it is mainly put_user (which might be
nice, too, since most users of GETTIMELEFT cast the result to various types).

> +static struct watchdog_device coh901327_wdt = {
> +	.info = &coh901327_ident,
> +	.ops = &coh901327_ops,
> +	/*
> +	 * Max margin is 327 since the 10ms
> +	 * timeout register is max
> +	 * 0x7FFF = 327670ms ~= 327s.
> +	 */

I'd drop that comment, but well...

> +	.min_timeout = 0,
> +	.max_timeout = 327,

Thanks!

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From plagnioj at jcrosoft.com  Wed Mar  7 11:45:13 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 17:45:13 +0100
Subject: [PATCH 1/9 v2] ARM: at91: usb ohci add dt support
In-Reply-To: <20120307103352.GA17745@game.jcrosoft.org>
References: <20120307084924.GK21255@game.jcrosoft.org>
 <1331111746-21393-1-git-send-email-plagnioj@jcrosoft.com>
 <20120307093446.GN17370@n2100.arm.linux.org.uk>
 <20120307103352.GA17745@game.jcrosoft.org>
Message-ID: <20120307164513.GA17087@game.jcrosoft.org>

On 11:33 Wed 07 Mar     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 09:34 Wed 07 Mar     , Russell King - ARM Linux wrote:
> > On Wed, Mar 07, 2012 at 10:15:38AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > +static u64 at91_ohci_dma_mask = DMA_BIT_MASK(32);
> > > +
> > > +static int __devinit ohci_at91_of_init(struct platform_device *pdev)
> > > +{
> > > +	struct device_node *np = pdev->dev.of_node;
> > > +	int i, ret, gpio;
> > > +	enum of_gpio_flags flags;
> > > +	struct at91_usbh_data	*pdata;
> > > +	u32 ports;
> > > +
> > > +	if (!np)
> > > +		return 0;
> > > +
> > > +	/* Right now device-tree probed devices don't get dma_mask set.
> > > +	 * Since shared usb code relies on it, set it here for now.
> > > +	 * Once we have dma capability bindings this can go away.
> > > +	 */
> > > +	if (!pdev->dev.dma_mask)
> > > +		pdev->dev.dma_mask = &at91_ohci_dma_mask;
> > 
> > That sounds like a rather big omission from DT - what's happening to
> > address this (before we end up with lots of drivers with this).  Pretty
> > much any device which does DMA needs both this and the coherent DMA mask
> > set properly.
> > 
> > We really don't want this kind of workaround scattered in every driver
> > which has been converted to DT.
> Tegra do it also
> I do yet found a good generic way in DT
> 
> Today only usb need I do plan to drop it for 3.5 can we have for 3.4
I send a patch to propose a binding for both dma-mask and coherent dma mask

If it does not got for 3.4 can this temporary fix up go?

Best Regards,
J.


From plagnioj at jcrosoft.com  Wed Mar  7 11:45:58 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed,  7 Mar 2012 17:45:58 +0100
Subject: [PATCH 1/1] of: add coherent dma-mask binding
In-Reply-To: <1331119575-6638-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331119575-6638-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1331138758-19480-1-git-send-email-plagnioj@jcrosoft.com>

This will allow each device to specify its coherent-dma-mask
The default behavior the set it to DMA_BIT_MASK(32) if none specified
is keeped.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 drivers/of/platform.c |   15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index bb22194..d2a2ea02 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -141,6 +141,19 @@ static u64* of_get_dma_mask(struct device_node *np)
 	return dma_mask;
 }
 
+static u64 of_get_coherent_dma_mask(struct device_node *np)
+{
+	const __be32 *prop;
+	int len;
+
+	prop = of_get_property(np, "coherent-dma-mask", &len);
+
+	if (!prop)
+		return DMA_BIT_MASK(32);
+
+	return of_read_number(prop, len / 4);
+}
+
 /**
  * of_device_alloc - Allocate and initialize an of_device
  * @np: device node to assign to device
@@ -228,7 +241,7 @@ struct platform_device *of_platform_device_create_pdata(
 #if defined(CONFIG_MICROBLAZE)
 	dev->archdata.dma_mask = 0xffffffffUL;
 #endif
-	dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+	dev->dev.coherent_dma_mask = of_get_coherent_dma_mask(np);
 	dev->dev.bus = &platform_bus_type;
 	dev->dev.platform_data = platform_data;
 
-- 
1.7.7



From m.szyprowski at samsung.com  Wed Mar  7 11:58:07 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 07 Mar 2012 17:58:07 +0100
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <20120307.091601.458605132780655792.hdoyu@nvidia.com>
References: <401E54CE964CD94BAE1EB4A729C7087E37970113FE@HQMAIL04.nvidia.com>
 <20120307.080952.2152478004740487196.hdoyu@nvidia.com>
 <20120307.083706.2087121294965856946.hdoyu@nvidia.com>
 <20120307.091601.458605132780655792.hdoyu@nvidia.com>
Message-ID: <011701ccfc83$78030180$68090480$%szyprowski@samsung.com>

Hello,

On Wednesday, March 07, 2012 8:16 AM Hiroshi Doyu wrote:

> From: Hiroshi DOYU <hdoyu at nvidia.com>
> Subject: Re: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
> Date: Wed, 07 Mar 2012 08:37:06 +0200 (EET)
> Message-ID: <20120307.083706.2087121294965856946.hdoyu at nvidia.com>
> 
> > From: Hiroshi DOYU <hdoyu at nvidia.com>
> > Subject: Re: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
> > Date: Wed, 07 Mar 2012 08:09:52 +0200 (EET)
> > Message-ID: <20120307.080952.2152478004740487196.hdoyu at nvidia.com>
> >
> > > From: Krishna Reddy <vdumpa at nvidia.com>
> > > Subject: RE: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
> > > Date: Tue, 6 Mar 2012 23:48:42 +0100
> > > Message-ID: <401E54CE964CD94BAE1EB4A729C7087E37970113FE at HQMAIL04.nvidia.com>
> > >
> > > > > > +struct dma_iommu_mapping *
> > > > > > +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
> > > > > > +                        int order)
> > > > > > +{
> > > > > > +       unsigned int count = (size >> PAGE_SHIFT) - order;
> > > > > > +       unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
> > > >
> > > > The count calculation doesn't seem correct. "order" is log2 number and
> > > >  size >> PAGE_SHIFT is number of pages.
> > > >
> > > > If size is passed as 64*4096(256KB) and order is 6(allocation granularity is 2^6
> pages=256KB),
> > > >  just 1 bit is enough to manage allocations.  So it should be 4 bytes or one long.
> > >
> > > Good catch!
> > >
> > > > But the calculation gives count = 64 - 6 = 58 and
> > > > Bitmap_size gets set to (58/(4*8)) * 4 = 8 bytes, which is incorrect.
> > >
> > > "order" isn't the order of size passed, which is minimal *page*
> > > allocation order which client decides whatever, just in case.
> > >
> > > > It should be as follows.
> > > > unsigned int count = 1 << get_order(size) - order;
> >
> > To be precise, as below?
> >
> >  unsigned int count = 1 << (get_order(size) - order);
> 
> This could be:
> 
> From fd40740ef4bc4a3924fe1188ea6dd785be0fe859 Mon Sep 17 00:00:00 2001
> From: Hiroshi DOYU <hdoyu at nvidia.com>
> Date: Wed, 7 Mar 2012 08:14:38 +0200
> Subject: [PATCH 1/1] dma-mapping: Fix count calculation of iova space
> 
> Fix count calculation of iova space.
> Pointed by Krishna Reddy <vdumpa at nvidia.com>
> 
> Signed-off-by: Hiroshi DOYU <hdoyu at nvidia.com>
> ---
>  arch/arm/mm/dma-mapping.c |   11 +++++++++--
>  1 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index 6c2f104..56f0af5 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -1483,11 +1483,18 @@ struct dma_iommu_mapping *
>  arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
>  			 int order)
>  {
> -	unsigned int count = (size >> PAGE_SHIFT) - order;
> -	unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
> +	unsigned int n, count;
> +	unsigned int bitmap_size;
>  	struct dma_iommu_mapping *mapping;
>  	int err = -ENOMEM;
> 
> +	n = get_order(size);
> +	if (n < order)
> +		return ERR_PTR(-EINVAL);
> +
> +	count = 1 << (n - order);
> +	bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
> +
>  	mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
>  	if (!mapping)
>  		goto err;

Thanks again for finding another bug. I thought that I've checked that code more
than twice, but it looks that I've missed something again.

IMHO the size of virtual memory area doesn't need to be aligned to the power of
two, so I will simplify it to the following code:

unsigned int count = size >> (PAGE_SHIFT + order);
unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);

if (!count)
	return ERR_PTR(-EINVAL);

...

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From xiachendong at hotmail.com  Wed Mar  7 11:59:13 2012
From: xiachendong at hotmail.com (Xiachen Dong)
Date: Wed, 7 Mar 2012 11:59:13 -0500
Subject: 2.6.36 and higher version kernel slower than 2.6.25.1 kernel?
Message-ID: <BAY167-W497E8A13D4F2938D985CF6BD560@phx.gbl>


Hi,

Recently we upgrade the OS for our AT91RM9200 platform from 2.6.25.1 to 2.6.36. We run the SQLITE3 database insertion tests for the new kernel. The test result shows that 2.6.36 kernel is around 10% slower than the 2.6.25.1.

The sqlite3 database insertion test originates from http://www.phoronix-test-suite.com/?k=home. It is very simple: it creates a new database under current directory and simply keeps on inserting 2500 records into the new DB created. Then it calculates the time it takes to finish the task.

Here's how we run the test:

1) Install or port sqlite3 to the platform;
2) mke2fs /dev/ram0;
3) mount -t ext2 /dev/ram0 /mnt/temp;
4) cp sqliteInsertionTest.sh /mnt/temp;
?? cp sqlite-insertions.txt /mnt/temp;
5) cd /mnt/temp;
6) ./sqliteInsertionTest.sh;
7) repeat the test 10 times and take the average;

To narrow down the problem. We also ran similar tests on a Pentium IV 1.7G laptop. Here is how the test was run:

a) install sqlite3 on the laptop
b) compile the 2.6.25.1 and 2.6.36 kernel on the laptop, try to make the kernel config as similar as possible;
c) boot into 2.6.25.1 and 2.6.36 kernel in single user mode ("single" in commandline argument);
d) run same tests in step 2) to step 7) above

The P4 CPU is single core, no hyper-threading. We can still see the performance hit in the 2.6.36 kernel on the Pentium laptop.

We may attach the kernel config files if needed. We choose CFQ for the scheduler for both kernels.


Here is the content of sqliteInsertionTest.sh:

============ sqliteInsertionTest.sh ===========
#!/bin/sh

TEST_PATH=`pwd`
rm -f $TEST_PATH/benchmark.db

echo "`date`, starting test ..."

sqlite3 $TEST_PATH/benchmark.db? "CREATE TABLE pts1 ('I' SMALLINT NOT NULL, 'DT' TIMESTAMP NOT NULL DEFAULT CURRENT_TIMESTAMP, 'F1' VARCHAR(4) NOT NULL, 'F2' VARCHAR(16) NOT NULL);"

cat $TEST_PATH/sqlite-insertions.txt | sqlite3 $TEST_PATH/benchmark.db
...
#cat $TEST_PATH/sqlite-insertions.txt | sqlite3 $TEST_PATH/benchmark.db
#cat $TEST_PATH/sqlite-insertions.txt | sqlite3 $TEST_PATH/behchmark.db

echo "`date`, test done."
============ end of sqliteInsertionTest.sh ===========

sqlite-insertions.txt is very simple:

INSERT INTO 'pts1' ('I', 'DT', 'F1', 'F2') VALUES ('1', CURRENT_TIMESTAMP, '6758', '9844343722998287');
INSERT INTO 'pts1' ('I', 'DT', 'F1', 'F2') VALUES ('2', CURRENT_TIMESTAMP, '3733', '8925952369645997');
...
INSERT INTO 'pts1' ('I', 'DT', 'F1', 'F2') VALUES ('2499', CURRENT_TIMESTAMP, '5955', '1088209297553915');
INSERT INTO 'pts1' ('I', 'DT', 'F1', 'F2') VALUES ('2500', CURRENT_TIMESTAMP, '6086', '6839549078383414');

The other thing we notice is that if the test is run under tempfs, the insertion can be done faster. However, there is still performance hit in 2.6.36 kernel.

We also run the same test on 3.0.23 kernel on the Pentium 4 laptop. The performance hit still exist.

Our questions are:
1. Is anyone else on the list notice such issue?
2. Did we did something silly in running such performance tests?
3. Are there any new features in 2.6.36 kernel that we didn't enable and those disabled features lead to our current test result?

Any suggestions and comments will be greatly appreciated.

Thank you.

Xiachen
 		 	   		  

From robherring2 at gmail.com  Wed Mar  7 11:59:21 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 07 Mar 2012 10:59:21 -0600
Subject: [PATCH 1/1] of: add dma-mask binding
In-Reply-To: <1331119575-6638-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331119575-6638-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <4F5793E9.9010100@gmail.com>

On 03/07/2012 05:26 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> This will allow each device to specify its dma-mask
> The microblaze architecture hook is keep temporary if no dma-mask is specified
> int the DT
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
>  drivers/of/platform.c |   26 +++++++++++++++++++++++++-
>  1 files changed, 25 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/of/platform.c b/drivers/of/platform.c
> index cae9477..bb22194 100644
> --- a/drivers/of/platform.c
> +++ b/drivers/of/platform.c
> @@ -121,6 +121,26 @@ void of_device_make_bus_id(struct device *dev)
>  	dev_set_name(dev, "%s.%d", node->name, magic - 1);
>  }
>  
> +static u64* of_get_dma_mask(struct device_node *np)
> +{
> +	const __be32 *prop;
> +	int len;
> +	u64 *dma_mask;
> +
> +	prop = of_get_property(np, "dma-mask", &len);

This would need some documentation. There is already "dma-ranges"
defined for OF which nay do what's needed.

> +
> +	if (!prop)
> +		return NULL;
> +
> +	dma_mask = kzalloc(sizeof(u64), GFP_KERNEL);

This seems kind of wasteful for 1 u64.

> +	if (!dma_mask)
> +		return NULL;
> +
> +	*dma_mask = of_read_number(prop, len / 4);
> +
> +	return dma_mask;
> +}
> +
>  /**
>   * of_device_alloc - Allocate and initialize an of_device
>   * @np: device node to assign to device
> @@ -161,10 +181,14 @@ struct platform_device *of_device_alloc(struct device_node *np,
>  		WARN_ON(of_irq_to_resource_table(np, res, num_irq) != num_irq);
>  	}
>  
> +	dev->dev.dma_mask = of_get_dma_mask(np);
>  	dev->dev.of_node = of_node_get(np);
> +
>  #if defined(CONFIG_MICROBLAZE)
> -	dev->dev.dma_mask = &dev->archdata.dma_mask;

And doing it this way for didn't get a warm reception either:

http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-April/005285.html

Do you really need this to be something other than ~0UL and if so does
it need to be per device or system wide?

You can solve this with bus notifiers in your at91 code. Here's an
example which I did (but no longer need):

static u64 highbank_dma_mask = DMA_BIT_MASK(32);

static int highbank_platform_notifier(struct notifier_block *nb,
				  unsigned long event, void *__dev)
{
	struct device *dev = __dev;

	if (event != BUS_NOTIFY_ADD_DEVICE)
		return NOTIFY_DONE;

	if (of_device_is_compatible(dev->of_node, "calxeda,hb-nfc"))
		dev->dma_mask = &highbank_dma_mask;
	else
		return NOTIFY_DONE;

	return NOTIFY_OK;
}

static struct notifier_block highbank_platform_nb = {
	.notifier_call = highbank_platform_notifier,
};

int highbank_devices_init(void)
{
	return bus_register_notifier(&platform_bus_type, &highbank_platform_nb);
}

Rob

> +	if (!dev->dev.dma_mask)
> +		dev->dev.dma_mask = &dev->archdata.dma_mask;
>  #endif
> +
>  	dev->dev.parent = parent;
>  
>  	if (bus_id)



From kaloz at openwrt.org  Wed Mar  7 12:09:07 2012
From: kaloz at openwrt.org (Imre Kaloz)
Date: Wed, 07 Mar 2012 18:09:07 +0100
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <201203061412.00073.arnd@arndb.de>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201202281945.39419.arnd@arndb.de>
 <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
 <201203061412.00073.arnd@arndb.de>
Message-ID: <op.was8lhu82s3iss@ecaz>

On Tue, 06 Mar 2012 15:11:59 +0100, Arnd Bergmann <arnd at arndb.de> wrote:

<snip>

>
> Interestingly, that leaves ixp4xx as the only big-endian ARM platform.
> I believe that ixp4xx is still being actively used quite a bit, but does
> that include the big-endian ones? There is no immediate reason why we
> would want to drop support for big-endian, but if it's not used at all,
> that would be an interesting cleanup opportunity.

IXP4xx is almost exclusively used in BE mode.


Imre


From tony at atomide.com  Wed Mar  7 12:10:45 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 09:10:45 -0800
Subject: Latest OMAP4 build errors
In-Reply-To: <20120307100615.GA17404@n2100.arm.linux.org.uk>
References: <20120228090209.GC18045@n2100.arm.linux.org.uk>
 <CAK=WgbZEDr_fYSonBQr3XNcTx5vefsH7LJfqycaxsqg-yechWQ@mail.gmail.com>
 <20120306165545.GB15392@n2100.arm.linux.org.uk>
 <201203061701.54141.arnd@arndb.de>
 <20120307100615.GA17404@n2100.arm.linux.org.uk>
Message-ID: <20120307171044.GE12083@atomide.com>

Hi,

Arnd & Olof, some urgent changes are needed, see below.

* Russell King - ARM Linux <linux at arm.linux.org.uk> [120307 01:34]:
> On Tue, Mar 06, 2012 at 05:01:53PM +0000, Arnd Bergmann wrote:
> > On Tuesday 06 March 2012, Russell King - ARM Linux wrote:
> > > On Tue, Feb 28, 2012 at 12:11:37PM +0200, Ohad Ben-Cohen wrote:
> > > > On Tue, Feb 28, 2012 at 12:01 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > > > > I think 'depends' would be better here, because selecting IOMMU_SUPPORT
> > > > > has other side-effects that a user might not want. It's just as likely
> > > > > that someone wants to disable IOMMU_SUPPORT and needs to find OMAP_REMOTEPROC
> > > > > as wanting to enable OMAP_REMOTEPROC and having to find IOMMU_SUPPORT.
> > > > >
> > > > > In most cases, the defconfig should just set both.
> > > > 
> > > > Ok, 'depends on' it is.
> > > 
> > > We're a week on, which means I now have a full set of 7 builds on the
> > > website for OMAP4430 all of which have failed in part due to this
> > > as yet unresolved problem.
> > > 
> > > What's happening to get it fixed and those fixes into whatever tree is
> > > necessary for them (presumably arm-soc)?
> > 
> > Ohad has sent a series of patches for review and there were no comments
> > on those. The fix was part of it as far as I remember. I'm still waiting
> > for a pull request from Ohad.
> 
> Given that we're coming to the end of what could be the _final_ week
> before the merge window opens, this is not good news.  Read: maybe
> three days before final.
> 
> The fact is that OMAP is - yet again - in a totally rotten state in terms
> of what's queued up in the armsoc tree.  It is - yet again - completely
> unbuildable for many configurations.  Just go and have a look at:
> 
> 	http://www.arm.linux.org.uk/developer/build/
> 
> to see what an utterly crappy state OMAP is in again.  Last nights build
> was my tree plus latest arm-soc.  Some of those issues have patches (I
> had been applying one patch manually to the build tree) but that's not
> the point - they're not in arm-soc, so the OMAP code in arm-soc is not
> yet ready for mainline.

Yes looks like there's an issue with getting urgent patches applied into
the arm-soc tree.. The patches to fix these issues are known and
other issues and warnings should be all sorted out now except for some
MMC changes that are still being discussed.
 
> So, as OMAP is soo broken, and as promised after the last merge window -
> I don't want any OMAP stuff going upstream from armsoc until we get error
> free builds from the allno and old configs on the builder.

What I got queued up in fixes-non-critical-part2 should fix all those
errors and warnings.

Arnd & Olof, I've posted one fix that should be applied to arm-soc tree
at [1]. I've also posted a request to revert one commit in arm-soc tree
at [2].

As it seems that you did not apply those to arm-soc, please apply them,
or repull the following two branches ASAP:

Re-pull fixes-non-critical containing one revert:

Revert "ARM: OMAP2+: Fix multiple randconfig errors with SOC_OMAP and SOC_OMAP_NOOP"

git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fixes-non-critical

Re-pull cleanup again containing one fix:

ARM: OMAP2+: Fix L4_EMU_34XX_BASE error after iomap changes

git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap cleanup

Note that the second one I just pushed, however the patch is known to
work for the build errors after merging arm-soc with Russell's changes.

Arnd & Olof, for future, how you want to handle urgent issues like this?

Regards,

Tony


[1] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg64149.html
[2] http://www.mail-archive.com/linux-omap at vger.kernel.org/msg64151.html


From robherring2 at gmail.com  Wed Mar  7 12:16:36 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 07 Mar 2012 11:16:36 -0600
Subject: [PATCH 1/5 v2] i2c/gpio: add DT support
In-Reply-To: <1330525221-25651-1-git-send-email-plagnioj@jcrosoft.com>
References: <1330525221-25651-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <4F5797F4.2040104@gmail.com>

On 02/29/2012 08:20 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-i2c at vger.kernel.org
> Cc: devicetree-discuss at lists.ozlabs.org
> ---
> v2:
> 
> 	use devm_kzalloc
> 	use i2c-gpio
> 	use time name in the properties
> 
> Best Regars,
> J.
>  .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 +++++++
>  drivers/i2c/busses/i2c-gpio.c                      |   95 +++++++++++++++----
>  2 files changed, 107 insertions(+), 20 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> new file mode 100644
> index 0000000..27e1b1a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> @@ -0,0 +1,32 @@
> +Device-Tree bindings for i2c gpio driver
> +
> +Required properties:
> +	- compatible = "i2c-gpio";
> +	- gpios: sda and scl gpio
> +
> +
> +Optional properties:
> +	- i2c-gpio,sda-open-drain: sda as open drain
> +	- i2c-gpio,scl-open-drain: scl as open drain
> +	- i2c-gpio,scl-output-only: scl as output only
> +	- udelay: delay between GPIO operations (may depend on each platform)

i2c-gpio,delay-us

> +	- i2c-algo-bit,timeout-milliseconds: timeout to get data

i2c-gpio,timeout-ms

> +
> +Example nodes:
> +
> +i2c-gpio at 0 {

Should be "i2c at 0"

> +	compatible = "i2c-gpio";
> +	gpios = <&pioA 23 0 /* sda */
> +		 &pioA 24 0 /* scl */
> +		>;
> +	i2c-gpio,sda-open-drain;
> +	i2c-gpio,scl-open-drain;
> +	udelay = <2>;		/* ~100 kHz */
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	rv3029c2 at 56 {
> +		compatible = "rv3029c2";
> +		reg = <0x56>;
> +	};
> +};
> diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
> index a651779..71adba5 100644
> --- a/drivers/i2c/busses/i2c-gpio.c
> +++ b/drivers/i2c/busses/i2c-gpio.c
> @@ -14,8 +14,15 @@
>  #include <linux/module.h>
>  #include <linux/slab.h>
>  #include <linux/platform_device.h>
> +#include <linux/gpio.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_i2c.h>
>  
> -#include <asm/gpio.h>
> +struct i2c_gpio_private_data {
> +	struct i2c_adapter adap;
> +	struct i2c_algo_bit_data bit_data;
> +	struct i2c_gpio_platform_data pdata;
> +};
>  
>  /* Toggle SDA by changing the direction of the pin */
>  static void i2c_gpio_setsda_dir(void *data, int state)
> @@ -78,24 +85,63 @@ static int i2c_gpio_getscl(void *data)
>  	return gpio_get_value(pdata->scl_pin);
>  }
>  
> +static int __devinit of_i2c_gpio_probe(struct device_node *np,
> +			     struct i2c_gpio_platform_data *pdata)
> +{
> +	u32 reg;
> +
> +	if (of_gpio_count(np) < 2)
> +		return -ENODEV;
> +
> +	pdata->sda_pin = of_get_gpio(np, 0);
> +	pdata->scl_pin = of_get_gpio(np, 1);
> +
> +	if (pdata->sda_pin < 0 || pdata->scl_pin < 0) {
> +		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
> +		       np->full_name, pdata->sda_pin, pdata->scl_pin);
> +		return -ENODEV;
> +	}
> +
> +	if (of_property_read_u32(np, "udelay", &reg))
> +		pdata->udelay = reg;

Why not of_property_read_u32(np, "udelay", &pdata->udelay)?

Also, reg may not be initialized here.

> +
> +	if (of_property_read_u32(np, "i2c-algo-bit,timeout-milliseconds", &reg))
> +		pdata->timeout = msecs_to_jiffies(reg);
> +
> +	pdata->sda_is_open_drain =
> +		!!of_property_read_bool(np, "i2c-gpio,sda-open-drain");
> +	pdata->scl_is_open_drain =
> +		!!of_property_read_bool(np, "i2c-gpio,scl-open-drain");
> +	pdata->scl_is_output_only =
> +		!!of_property_read_bool(np, "i2c-gpio,scl-output-only");
> +
> +	return 0;
> +}
> +
>  static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  {
> +	struct i2c_gpio_private_data *priv;
>  	struct i2c_gpio_platform_data *pdata;
>  	struct i2c_algo_bit_data *bit_data;
>  	struct i2c_adapter *adap;
>  	int ret;
>  
> -	pdata = pdev->dev.platform_data;
> -	if (!pdata)
> -		return -ENXIO;
> +	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +	adap = &priv->adap;
> +	bit_data = &priv->bit_data;
> +	pdata = &priv->pdata;
>  
> -	ret = -ENOMEM;
> -	adap = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
> -	if (!adap)
> -		goto err_alloc_adap;
> -	bit_data = kzalloc(sizeof(struct i2c_algo_bit_data), GFP_KERNEL);
> -	if (!bit_data)
> -		goto err_alloc_bit_data;
> +	if (pdev->dev.of_node) {
> +		ret = of_i2c_gpio_probe(pdev->dev.of_node, pdata);
> +		if (ret)
> +			return ret;
> +	} else {
> +		if (!pdev->dev.platform_data)
> +			return -ENXIO;
> +		memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
> +	}
>  
>  	ret = gpio_request(pdata->sda_pin, "sda");
>  	if (ret)
> @@ -143,6 +189,7 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  	adap->algo_data = bit_data;
>  	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
>  	adap->dev.parent = &pdev->dev;
> +	adap->dev.of_node = pdev->dev.of_node;
>  
>  	/*
>  	 * If "dev->id" is negative we consider it as zero.
> @@ -154,7 +201,9 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto err_add_bus;
>  
> -	platform_set_drvdata(pdev, adap);
> +	of_i2c_register_devices(adap);
> +
> +	platform_set_drvdata(pdev, priv);
>  
>  	dev_info(&pdev->dev, "using pins %u (SDA) and %u (SCL%s)\n",
>  		 pdata->sda_pin, pdata->scl_pin,
> @@ -168,34 +217,40 @@ err_add_bus:
>  err_request_scl:
>  	gpio_free(pdata->sda_pin);
>  err_request_sda:
> -	kfree(bit_data);
> -err_alloc_bit_data:
> -	kfree(adap);
> -err_alloc_adap:
>  	return ret;
>  }
>  
>  static int __devexit i2c_gpio_remove(struct platform_device *pdev)
>  {
> +	struct i2c_gpio_private_data *priv;
>  	struct i2c_gpio_platform_data *pdata;
>  	struct i2c_adapter *adap;
>  
> -	adap = platform_get_drvdata(pdev);
> -	pdata = pdev->dev.platform_data;
> +	priv = platform_get_drvdata(pdev);
> +	adap = &priv->adap;
> +	pdata = &priv->pdata;
>  
>  	i2c_del_adapter(adap);
>  	gpio_free(pdata->scl_pin);
>  	gpio_free(pdata->sda_pin);
> -	kfree(adap->algo_data);
> -	kfree(adap);
>  
>  	return 0;
>  }
>  
> +#if defined(CONFIG_OF)
> +static const struct of_device_id i2c_gpio_dt_ids[] = {
> +	{ .compatible = "i2c-gpio", },
> +	{ /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, i2c_gpio_dt_ids);
> +#endif
> +
>  static struct platform_driver i2c_gpio_driver = {
>  	.driver		= {
>  		.name	= "i2c-gpio",
>  		.owner	= THIS_MODULE,
> +		.of_match_table	= of_match_ptr(i2c_gpio_dt_ids),
>  	},
>  	.probe		= i2c_gpio_probe,
>  	.remove		= __devexit_p(i2c_gpio_remove),



From tony at atomide.com  Wed Mar  7 12:21:16 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 09:21:16 -0800
Subject: [PATCH v3] ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
 regulators
In-Reply-To: <CA+Bv8XaJqL1L8F-n6skY7dHn1XAdDLRKaRjw0deLeoQ5Ao0Fhg@mail.gmail.com>
References: <1330006564-13290-1-git-send-email-mporter@ti.com>
 <87wr74gis6.fsf@ti.com>
 <20120301204553.GA21841@legolas.emea.dhcp.ti.com>
 <87pqcqnc7u.fsf@ti.com>
 <CA+Bv8XaJqL1L8F-n6skY7dHn1XAdDLRKaRjw0deLeoQ5Ao0Fhg@mail.gmail.com>
Message-ID: <20120307172116.GF12083@atomide.com>

* Russ Dill <Russ.Dill at ti.com> [120307 07:28]:
> On Mon, Mar 5, 2012 at 12:18 PM, Kevin Hilman <khilman at ti.com> wrote:
> >
> > In either case $SUBJECT patch is already in Tony's fixes queue, so if it
> > is going be merged, then my fix above is needed also to not break
> > Overo and any other platform that has more than one smsc911x instance.
> >
> > Kevin
> 
> 
> Have you tested this fix? The only regulator consumer supply would be:
> 
> static struct regulator_consumer_supply gpmc_smsc911x_supply[] = {
>         REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
>         REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
> };
> 
> I don't think the second smsc911x on the Overo, "smsc911x.1", would
> find it due to the dev_id.

Hmm yeah sounds like there's some further changes needed. Dropping
the second version from fixes until we have somebody reply with
tested-by using two smsc911x instances.

Regards,

Tony


From tony at atomide.com  Wed Mar  7 12:31:52 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 09:31:52 -0800
Subject: [PATCH 4/4] mmc: omap_hsmmc: Simplify init for twl6030 MMC
 card detect
In-Reply-To: <m2lincifj9.fsf@bob.laptop.org>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185535.29210.71546.stgit@kaulin.local>
 <4F50643B.9050500@ti.com> <20120302172251.GJ18901@atomide.com>
 <4F548457.5050205@ti.com>
 <CANrkHUZysOnHKKUuLm0Vbo1KsNp0yUd=udjGvQ43=gTTXbWeCw@mail.gmail.com>
 <CANrkHUaYDpv=p0p81oKWCoewyjheyZYkCqvZY7_ZQxWi_=8YFw@mail.gmail.com>
 <m2lincifj9.fsf@bob.laptop.org>
Message-ID: <20120307173152.GG12083@atomide.com>

* Chris Ball <cjb at laptop.org> [120307 07:11]:
> Hi Balaji,
> 
> On Wed, Mar 07 2012, T Krishnamoorthy, Balaji wrote:
> > OMAP4 and OMAP3 HSMMC IP registers differ by 0x100 offset.
> > Addng the offset to platform_device resource structure
> > increments the start address for every insmod operation.
> > MMC command fails on re-insertion as module due incorrect register base.
> > Fix this by updating the ioremap base address only.
> >
> > Signed-off-by: Balaji T K <balajitk at ti.com>
> 
> Is this a regression, or has it never worked in mainline?

"Features that never worked originally" so this can wait for the
merge window. It happens on re-inserting of the card.
 
> > Note:  eMMC detection is still failing on resertion due to card vcc
> > power off on rmmod
> 
> And this?

That sounds like a separate issue that needs to be fixed.

Regards,

Tony


From plagnioj at jcrosoft.com  Wed Mar  7 12:22:23 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 18:22:23 +0100
Subject: [PATCH 1/5 v2] i2c/gpio: add DT support
In-Reply-To: <4F5797F4.2040104@gmail.com>
References: <1330525221-25651-1-git-send-email-plagnioj@jcrosoft.com>
 <4F5797F4.2040104@gmail.com>
Message-ID: <20120307172223.GB17087@game.jcrosoft.org>

On 11:16 Wed 07 Mar     , Rob Herring wrote:
> On 02/29/2012 08:20 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> > Cc: linux-i2c at vger.kernel.org
> > Cc: devicetree-discuss at lists.ozlabs.org
> > ---
> > v2:
> > 
> > 	use devm_kzalloc
> > 	use i2c-gpio
> > 	use time name in the properties
> > 
> > Best Regars,
> > J.
> >  .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 +++++++
> >  drivers/i2c/busses/i2c-gpio.c                      |   95 +++++++++++++++----
> >  2 files changed, 107 insertions(+), 20 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> > new file mode 100644
> > index 0000000..27e1b1a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> > @@ -0,0 +1,32 @@
> > +Device-Tree bindings for i2c gpio driver
> > +
> > +Required properties:
> > +	- compatible = "i2c-gpio";
> > +	- gpios: sda and scl gpio
> > +
> > +
> > +Optional properties:
> > +	- i2c-gpio,sda-open-drain: sda as open drain
> > +	- i2c-gpio,scl-open-drain: scl as open drain
> > +	- i2c-gpio,scl-output-only: scl as output only
> > +	- udelay: delay between GPIO operations (may depend on each platform)
> 
> i2c-gpio,delay-us
> 
> > +	- i2c-algo-bit,timeout-milliseconds: timeout to get data
> 
> i2c-gpio,timeout-ms
it's algo-bit speficic no i2c-gpio that's why I use i2c-algo-bit
> 
> > +
> > +Example nodes:
> > +
> > +i2c-gpio at 0 {
> 
> Should be "i2c at 0"
ok
> 
> > +	compatible = "i2c-gpio";
> > +	gpios = <&pioA 23 0 /* sda */
> > +		 &pioA 24 0 /* scl */
> > +		>;
> > +	i2c-gpio,sda-open-drain;
> > +	i2c-gpio,scl-open-drain;
> > +	udelay = <2>;		/* ~100 kHz */
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> > +
> > +	rv3029c2 at 56 {
> > +		compatible = "rv3029c2";
> > +		reg = <0x56>;
> > +	};
> > +};
> > diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
> > index a651779..71adba5 100644
> > --- a/drivers/i2c/busses/i2c-gpio.c
> > +++ b/drivers/i2c/busses/i2c-gpio.c
> > @@ -14,8 +14,15 @@
> >  #include <linux/module.h>
> >  #include <linux/slab.h>
> >  #include <linux/platform_device.h>
> > +#include <linux/gpio.h>
> > +#include <linux/of_gpio.h>
> > +#include <linux/of_i2c.h>
> >  
> > -#include <asm/gpio.h>
> > +struct i2c_gpio_private_data {
> > +	struct i2c_adapter adap;
> > +	struct i2c_algo_bit_data bit_data;
> > +	struct i2c_gpio_platform_data pdata;
> > +};
> >  
> >  /* Toggle SDA by changing the direction of the pin */
> >  static void i2c_gpio_setsda_dir(void *data, int state)
> > @@ -78,24 +85,63 @@ static int i2c_gpio_getscl(void *data)
> >  	return gpio_get_value(pdata->scl_pin);
> >  }
> >  
> > +static int __devinit of_i2c_gpio_probe(struct device_node *np,
> > +			     struct i2c_gpio_platform_data *pdata)
> > +{
> > +	u32 reg;
> > +
> > +	if (of_gpio_count(np) < 2)
> > +		return -ENODEV;
> > +
> > +	pdata->sda_pin = of_get_gpio(np, 0);
> > +	pdata->scl_pin = of_get_gpio(np, 1);
> > +
> > +	if (pdata->sda_pin < 0 || pdata->scl_pin < 0) {
> > +		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
> > +		       np->full_name, pdata->sda_pin, pdata->scl_pin);
> > +		return -ENODEV;
> > +	}
> > +
> > +	if (of_property_read_u32(np, "udelay", &reg))
> > +		pdata->udelay = reg;
> 
> Why not of_property_read_u32(np, "udelay", &pdata->udelay)?
> 
> Also, reg may not be initialized here.
if udelay have any error we keep udelay as 0

Best Regards,
J.


From swarren at wwwdotorg.org  Wed Mar  7 12:41:52 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 07 Mar 2012 10:41:52 -0700
Subject: [PATCH 1/3] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <201203062256.16105.vapier@gentoo.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <201203062256.16105.vapier@gentoo.org>
Message-ID: <4F579DE0.3050400@wwwdotorg.org>

On 03/06/2012 08:56 PM, Mike Frysinger wrote:
> On Tuesday 06 March 2012 19:30:36 Stephen Warren wrote:
>> --- a/arch/blackfin/boot/Makefile
>> +++ b/arch/blackfin/boot/Makefile
>>
>> +ifeq ($(CONFIG_RAMKERNEL),y)
>> +UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
>> +else # CONFIG_ROMKERNEL must be set
>> +UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
>> +endif
> 
> this part is wrong :).  the else branch should be $(CONFIG_ROM_BASE).

Thanks. I've fixed that locally.

>> +UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "__start" {print
>> $$1}')
> 
> i feel like if we tried harder, we could automate the -e arg for all arches.  
> i understand if you don't want to undertake that though.

Yes, this might be possible. I'd guess the symbol name varies between
archs, but that can probably be taken care of. This is probably best
left as a follow-on patch though, since it's a behavioral change,
whereas this patch is just consolidation.


From plagnioj at jcrosoft.com  Wed Mar  7 12:34:37 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 18:34:37 +0100
Subject: [PATCH 1/1] of: add dma-mask binding
In-Reply-To: <4F5793E9.9010100@gmail.com>
References: <1331119575-6638-1-git-send-email-plagnioj@jcrosoft.com>
 <4F5793E9.9010100@gmail.com>
Message-ID: <20120307173437.GC17087@game.jcrosoft.org>

On 10:59 Wed 07 Mar     , Rob Herring wrote:
> On 03/07/2012 05:26 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > This will allow each device to specify its dma-mask
> > The microblaze architecture hook is keep temporary if no dma-mask is specified
> > int the DT
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > ---
> >  drivers/of/platform.c |   26 +++++++++++++++++++++++++-
> >  1 files changed, 25 insertions(+), 1 deletions(-)
> > 
> > diff --git a/drivers/of/platform.c b/drivers/of/platform.c
> > index cae9477..bb22194 100644
> > --- a/drivers/of/platform.c
> > +++ b/drivers/of/platform.c
> > @@ -121,6 +121,26 @@ void of_device_make_bus_id(struct device *dev)
> >  	dev_set_name(dev, "%s.%d", node->name, magic - 1);
> >  }
> >  
> > +static u64* of_get_dma_mask(struct device_node *np)
> > +{
> > +	const __be32 *prop;
> > +	int len;
> > +	u64 *dma_mask;
> > +
> > +	prop = of_get_property(np, "dma-mask", &len);
> 
> This would need some documentation. There is already "dma-ranges"
> defined for OF which nay do what's needed.
what is dma-ranges I see no doc about it
but I don't think it could be used for the dma mask
> 
> > +
> > +	if (!prop)
> > +		return NULL;
> > +
> > +	dma_mask = kzalloc(sizeof(u64), GFP_KERNEL);
> 
> This seems kind of wasteful for 1 u64.
no choice dma_mask must be a pointer
> 
> > +	if (!dma_mask)
> > +		return NULL;
> > +
> > +	*dma_mask = of_read_number(prop, len / 4);
> > +
> > +	return dma_mask;
> > +}
> > +
> >  /**
> >   * of_device_alloc - Allocate and initialize an of_device
> >   * @np: device node to assign to device
> > @@ -161,10 +181,14 @@ struct platform_device *of_device_alloc(struct device_node *np,
> >  		WARN_ON(of_irq_to_resource_table(np, res, num_irq) != num_irq);
> >  	}
> >  
> > +	dev->dev.dma_mask = of_get_dma_mask(np);
> >  	dev->dev.of_node = of_node_get(np);
> > +
> >  #if defined(CONFIG_MICROBLAZE)
> > -	dev->dev.dma_mask = &dev->archdata.dma_mask;
> 
> And doing it this way for didn't get a warm reception either:
> 
> http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-April/005285.html
> 
> Do you really need this to be something other than ~0UL and if so does
> it need to be per device or system wide?
> 
> You can solve this with bus notifiers in your at91 code. Here's an
> example which I did (but no longer need):
> 
> static u64 highbank_dma_mask = DMA_BIT_MASK(32);
IIRC on at91 all of them that need it have a DMA_BIT_MASK(32)


> 
> static int highbank_platform_notifier(struct notifier_block *nb,
> 				  unsigned long event, void *__dev)
> {
> 	struct device *dev = __dev;
> 
> 	if (event != BUS_NOTIFY_ADD_DEVICE)
> 		return NOTIFY_DONE;
> 
> 	if (of_device_is_compatible(dev->of_node, "calxeda,hb-nfc"))
> 		dev->dma_mask = &highbank_dma_mask;
execpt as example today I need it on 2 node (OHCI & EHCI)

and if more device need I don't want to end up with more fixup

I really prefer to set it via DT

Best Regards,
J.


From plagnioj at jcrosoft.com  Wed Mar  7 12:38:28 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 18:38:28 +0100
Subject: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support
In-Reply-To: <201203022024.19488.arnd@arndb.de>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <1330718048-9314-6-git-send-email-plagnioj@jcrosoft.com>
 <201203022024.19488.arnd@arndb.de>
Message-ID: <20120307173828.GD17087@game.jcrosoft.org>

On 20:24 Fri 02 Mar     , Arnd Bergmann wrote:
> On Friday 02 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > +       }
> > +
> > +       if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
> > +               have_rtt = false;
> > +               have_rtc = true;
> > +       } else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
> > +               have_rtt = true;
> > +               have_rtc = true;
> > +       } else {
> > +               have_rtt = true;
> > +               have_rtc = false;
> > +       }
> > +
> > +       if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
> > +                       mode |= AT91_SHDW_RTCWKEN;
> > +
> > +       if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
> > +                       mode |= AT91_SHDW_RTTWKEN;
> > +
> > +       at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
> > +
> 
> Hi Jean-Christophe,
> 
> I don't understand why you check the specific part here. Isn't it enough to
> check the property when you already mandate that they can only be present
> on devices that support the specific wakeup?
> 
> If there is a good explanation for that, maybe add a code comment why it's
> required.
some wake update source exist on few soc and we are not supposed to set the
bit otherwise

Ill put a comment.

Best Regards,
J.


From plagnioj at jcrosoft.com  Wed Mar  7 12:39:07 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 18:39:07 +0100
Subject: [PATCH 0/6] AT91 more DT bindings
In-Reply-To: <20120302192844.GB21255@game.jcrosoft.org>
References: <20120302192844.GB21255@game.jcrosoft.org>
Message-ID: <20120307173907.GE17087@game.jcrosoft.org>

Hi,

	Rob is ok for you?

Best Regards,
J.
On 20:28 Fri 02 Mar     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> HI,
> 
> 	The following patch series add the bindings for:
> 	 - PMC
> 	 - SDRAM/DDR Controller
> 	 - Reset Controller
> 	 - Shutdown Controller
> 
> The following changes since commit c5ec01650adb1976f928177cd7e71afcb82026c5:
> 
>   ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5 (2012-03-02 00:46:37 +0800)
> 
> are available in the git repository at:
>   git://github.com/at91linux/linux-at91.git ..BRANCH.NOT.VERIFIED..
> 
> Jean-Christophe PLAGNIOL-VILLARD (6):
>       ARM: at91/dt: add specific DT soc init
>       ARM: at91: add pmc DT support
>       ARM: at91: always enable sam9 restart
>       ARM: at91: add RSTC (Reset Controller) dt support
>       ARM: at91: add ram controller DT support
>       ARM: at91: add Shutdown Controller (SHDWC) DT support
> 
>  .../devicetree/bindings/arm/atmel-at91.txt         |   60 ++++++++
>  .../devicetree/bindings/arm/atmel-pmc.txt          |   11 ++
>  arch/arm/boot/dts/at91sam9g20.dtsi                 |   20 +++
>  arch/arm/boot/dts/at91sam9g45.dtsi                 |   21 +++
>  arch/arm/boot/dts/at91sam9m10g45ek.dts             |   11 ++
>  arch/arm/boot/dts/at91sam9x5.dtsi                  |   20 +++
>  arch/arm/boot/dts/at91sam9x5cm.dtsi                |   11 ++
>  arch/arm/boot/dts/usb_a9g20.dts                    |   11 ++
>  arch/arm/mach-at91/Kconfig                         |   10 +-
>  arch/arm/mach-at91/at91sam9x5.c                    |    7 -
>  arch/arm/mach-at91/board-dt.c                      |    8 +-
>  arch/arm/mach-at91/clock.c                         |   54 ++++++-
>  arch/arm/mach-at91/generic.h                       |    2 +
>  arch/arm/mach-at91/include/mach/at91_shdwc.h       |    4 +-
>  arch/arm/mach-at91/include/mach/at91sam9x5.h       |    5 -
>  arch/arm/mach-at91/setup.c                         |  158 ++++++++++++++++++++
>  16 files changed, 380 insertions(+), 33 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/atmel-pmc.txt
> 
> Best Regards,
> J.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From tony at atomide.com  Wed Mar  7 12:51:01 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 09:51:01 -0800
Subject: Pre-merge-window status of the arm-soc tree
In-Reply-To: <201203062054.55434.arnd@arndb.de>
References: <201203062054.55434.arnd@arndb.de>
Message-ID: <20120307175100.GH12083@atomide.com>

Hi Arnd & Olof,

* Arnd Bergmann <arnd at arndb.de> [120306 12:26]:
> 
> * Russell now has a branch that contains patches from his tree that
> directly impact stuff in arm-soc. We had a lot of nasty conflicts
> the last time around, which resulted in some of the patches from
> arm-soc not making it in during the merge window. Pulling the
> rmk/for-armsoc branch into arm-soc hopefully lets us avoid this
> situation in the future because we will fix the conflicts much
> earlier.

There's also two urgent issues pending for omap in case you
are filtering mails on keywords to make them safe to read :)

See this:

http://www.spinics.net/lists/arm-kernel/msg163661.html

Also, after that is out of the way, I have two more pull request
ready for fixes for various build and warning issues Russell
has reported.

Regards,

Tony 


From jassisinghbrar at gmail.com  Wed Mar  7 13:09:25 2012
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Wed, 7 Mar 2012 23:39:25 +0530
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <CABb+yY0A9=XKuw=N1fFXCB507zR3U=wofqATVcO_wtnnVrgXzQ@mail.gmail.com>

On Wed, Mar 7, 2012 at 4:03 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> [v2 - more or less same description. ?Including lakml in cc for the full
> set]
>
> This patch series cleans up the handling of cookies in DMA engine drivers.
> This is done by providing a set of inline library functions for common
> tasks:
>
> - moving the 'last completed cookie' into struct dma_chan - everyone
> ?has this in their driver private channel data structure
>
> - consolidate allocation of cookies to DMA descriptors
>
> - common way to update 'last completed cookie' value
>
> - standard way to implement tx_status callback and update the residue
>
> - consolidate initialization of cookies
>
> - update implementations differing from the majority of DMA engine drivers
> ?to behave the same as the majority implementation in respect of cookies
>
> What this means is that we get to the point where all DMA engine drivers
> will hand out cookie value '2' as the first, and incrementing cookie
> values up to INT_MAX, returning to cookie '1' as the next cookie.
>
> Think of this patch series as round 1... ?I am hoping over time that more
> code can be consolidated between the DMA engine drivers and end up with a
> consistent way to handle various common themes in DMA engine hardware
> (like physical channel<->peripheral request signal selection.)
>
Compilation is broken without the following minor fix.
After that you may add
       Acked-by: Jassi Brar <jassisinghbrar at gmail.com>

diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 49c123f..abf35a3 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -339,7 +339,6 @@ static int pl330_control(struct dma_chan *chan,
enum dma_ctrl_cmd cmd, unsigned
 		/* Mark all desc done */
 		list_for_each_entry_safe(desc, _dt, &pch->work_list , node) {
 			desc->status = DONE;
-			pch->completed = desc->txd.cookie;
 			list_move_tail(&desc->node, &list);
 		}


Thanks.


From swarren at wwwdotorg.org  Wed Mar  7 13:10:19 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 07 Mar 2012 11:10:19 -0700
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <1331103163.2048.33.camel@epip-laptop>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>	
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <1331103163.2048.33.camel@epip-laptop>
Message-ID: <4F57A48B.1060100@wwwdotorg.org>

On 03/06/2012 11:52 PM, Guan Xuetao wrote:
> On Tue, 2012-03-06 at 17:30 -0700, Stephen Warren wrote:
>> This allows the user to use U-Boot's mkimage's -T kernel_noload option
>> if their arch Kconfig allows it, and they desire.
...
> Hi, Stephen,
> It seems that UIMAGE_ARCH and UIMAGE_LOADADDR can't be modified from
> arch-Makefiles.

Oh dear, you're right. I suck at testing:-( I've fixed this locally.

For reference, Makefile.lib is included after the Makefile in the
relevant source directory, whereas my patch assumed the other way
around. So, rather than setting defaults in Makefile.lib and having
foo/Makefile override them, I should set the non-defaults in
foo/Makefile, and have Makefile.lib provide default values for variables
that aren't already set. Testing indicates this solves the problem!


From plagnioj at jcrosoft.com  Wed Mar  7 13:08:15 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 19:08:15 +0100
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
Message-ID: <20120307180815.GA27213@game.jcrosoft.org>

On 17:30 Tue 06 Mar     , Stephen Warren wrote:
> This allows the user to use U-Boot's mkimage's -T kernel_noload option
> if their arch Kconfig allows it, and they desire.
> 
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> ---
> The next patch enables this new CONFIG_ALLOW_ option for ARM. I assume
> that some other architectures will also be able to enable it, but I'm
> not familiar enough with any to know which.
I'm going to repeat. I don't think any impromevent here.

with no specific kernel load address the uImage for is useless/

And this no the job of the kernel to build a boot loader specific boot image
format.

And the uImage format here is called the legacy format where now U-Boot
support a new format based on DT format.

Will you plan to add it too?

no sorry I don't think it's the right way to go.

On X86 we boot zImage simply. The new uImage option to do not specify the load
address add nothing more than just boot a zImage for kernel point of view.

Further more on server the vendor will use grub mostly (even on ARM) and will
expect to boot a zImage.

Best Regards,,
J.


From linux at arm.linux.org.uk  Wed Mar  7 13:21:55 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 18:21:55 +0000
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <CABb+yY0A9=XKuw=N1fFXCB507zR3U=wofqATVcO_wtnnVrgXzQ@mail.gmail.com>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <CABb+yY0A9=XKuw=N1fFXCB507zR3U=wofqATVcO_wtnnVrgXzQ@mail.gmail.com>
Message-ID: <20120307182155.GD18787@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 11:39:25PM +0530, Jassi Brar wrote:
> Compilation is broken without the following minor fix.
> After that you may add
>        Acked-by: Jassi Brar <jassisinghbrar at gmail.com>
> 
> diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
> index 49c123f..abf35a3 100644
> --- a/drivers/dma/pl330.c
> +++ b/drivers/dma/pl330.c
> @@ -339,7 +339,6 @@ static int pl330_control(struct dma_chan *chan,
> enum dma_ctrl_cmd cmd, unsigned
>  		/* Mark all desc done */
>  		list_for_each_entry_safe(desc, _dt, &pch->work_list , node) {
>  			desc->status = DONE;
> -			pch->completed = desc->txd.cookie;

I'm not sure just removing this is sufficient.  Presumably it's
there for some reason - maybe it needs replacing with a call to
dma_cookie_complete() to preserve existing behaviour?


From vapier at gentoo.org  Wed Mar  7 13:25:51 2012
From: vapier at gentoo.org (Mike Frysinger)
Date: Wed, 7 Mar 2012 13:25:51 -0500
Subject: [PATCH 1/3] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <4F579DE0.3050400@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <201203062256.16105.vapier@gentoo.org> <4F579DE0.3050400@wwwdotorg.org>
Message-ID: <201203071326.00264.vapier@gentoo.org>

On Wednesday 07 March 2012 12:41:52 Stephen Warren wrote:
> On 03/06/2012 08:56 PM, Mike Frysinger wrote:
> > On Tuesday 06 March 2012 19:30:36 Stephen Warren wrote:
> >> +UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "__start"
> >> {print $$1}')
> > 
> > i feel like if we tried harder, we could automate the -e arg for all
> > arches. i understand if you don't want to undertake that though.
> 
> Yes, this might be possible. I'd guess the symbol name varies between
> archs, but that can probably be taken care of.

i think we could avoid the symbol lookup.  if the entry point is set correctly 
in the ELF, we could do:
UIMAGE_ENTRYADDR = $(shell $(READELF) -h vmlinux | \
	awk '$$0 ~ /Entry point address:/ { print $$NF }'

99% sure this would work for Blackfin kernel images ...

> This is probably best
> left as a follow-on patch though, since it's a behavioral change,
> whereas this patch is just consolidation.

of course
-mike
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From swarren at wwwdotorg.org  Wed Mar  7 13:29:14 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 07 Mar 2012 11:29:14 -0700
Subject: [PATCH 1/3] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <CA+5PVA7PCow=Z7TpPtQYp3ye6uKFSp3XsdH75Pe9BRu9Vyy21g@mail.gmail.com>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <CA+5PVA7PCow=Z7TpPtQYp3ye6uKFSp3XsdH75Pe9BRu9Vyy21g@mail.gmail.com>
Message-ID: <4F57A8FA.8080208@wwwdotorg.org>

On 03/07/2012 07:15 AM, Josh Boyer wrote:
> On Tue, Mar 6, 2012 at 7:30 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
>> All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
>> to avoid duplication.
>>
>> All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
>> parameterized version in Makefile.lib to avoid duplication.
>>
>> The centralized cmd_uimage definition will allow the future introduction
>> of a centralized Kconfig option to make cmd_uimage use -T kernel_noload
>> rather than -T kernel.
...
> Is there a reason you skipped powerpc?

grepping the powerpc makefiles showed no hits on MKIMAGE, mkimage or
cmd_uimage.

Looking a little harder now, this is all inside the shell script
arch/powerpc/boot/wrapper. I'm not really sure quite how to unify that
shell script with the makefile use of mkimage. Do you have any ideas?


From arnd at arndb.de  Wed Mar  7 13:31:31 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 7 Mar 2012 18:31:31 +0000
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <80fb8cef577eee14364e95009f7a590fd9056ee3.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <80fb8cef577eee14364e95009f7a590fd9056ee3.1331090356.git.jason@lakedaemon.net>
Message-ID: <201203071831.31738.arnd@arndb.de>

On Wednesday 07 March 2012, Jason Cooper wrote:
> +       serial at f1012000 {
> +               compatible = "ns16550a";
> +               reg = <0xf1012000 0xff>;
> +               reg-shift = <2>;
> +               interrupts = <33>;
> +               clock-frequency = <200000000>;
> +       };

I just noticed that the length here should be inclusive, i.e. 0x100 not 0xff.
This is different from the way we define resources in Linux.

	Arnd


From arnd at arndb.de  Wed Mar  7 13:32:25 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 7 Mar 2012 18:32:25 +0000
Subject: [PATCH 08/14] ARM: kirkwood: use devicetree for rtc-mv
In-Reply-To: <146e96ef8a8649767b3beb49ff39a260e75f234a.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <146e96ef8a8649767b3beb49ff39a260e75f234a.1331090356.git.jason@lakedaemon.net>
Message-ID: <201203071832.25307.arnd@arndb.de>

On Wednesday 07 March 2012, Jason Cooper wrote:
> +
> +       rtc at f1010300 {
> +               compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc";
> +               reg = <0xf1010300 0x1f>;
> +               interrupts = <53>;
> +       };
>  };

Same as with the uart, this length should be 0x20 instead of 0x1f.

	Arnd


From jason at lakedaemon.net  Wed Mar  7 13:37:05 2012
From: jason at lakedaemon.net (Jason)
Date: Wed, 7 Mar 2012 13:37:05 -0500
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <201203071831.31738.arnd@arndb.de>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <80fb8cef577eee14364e95009f7a590fd9056ee3.1331090356.git.jason@lakedaemon.net>
 <201203071831.31738.arnd@arndb.de>
Message-ID: <20120307183705.GC5050@titan.lakedaemon.net>

On Wed, Mar 07, 2012 at 06:31:31PM +0000, Arnd Bergmann wrote:
> On Wednesday 07 March 2012, Jason Cooper wrote:
> > +       serial at f1012000 {
> > +               compatible = "ns16550a";
> > +               reg = <0xf1012000 0xff>;
> > +               reg-shift = <2>;
> > +               interrupts = <33>;
> > +               clock-frequency = <200000000>;
> > +       };
> 
> I just noticed that the length here should be inclusive, i.e. 0x100 not 0xff.
> This is different from the way we define resources in Linux.

I was maintaining form with plat-orion/common.c:66 (0xff)  I'll fix it
to inclusive.

thx,

Jason.


From swarren at wwwdotorg.org  Wed Mar  7 13:40:18 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 07 Mar 2012 11:40:18 -0700
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <20120307180815.GA27213@game.jcrosoft.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <20120307180815.GA27213@game.jcrosoft.org>
Message-ID: <4F57AB92.6060907@wwwdotorg.org>

On 03/07/2012 11:08 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 17:30 Tue 06 Mar     , Stephen Warren wrote:
>> This allows the user to use U-Boot's mkimage's -T kernel_noload option
>> if their arch Kconfig allows it, and they desire.
>>
>> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
>> ---
>> The next patch enables this new CONFIG_ALLOW_ option for ARM. I assume
>> that some other architectures will also be able to enable it, but I'm
>> not familiar enough with any to know which.
> I'm going to repeat. I don't think any impromevent here.
> 
> with no specific kernel load address the uImage for is useless/

No, the whole point of this type of kernel image is that it doesn't need
a specific load address; the kernel zImage can run from anywhere in RAM
(provided AUTO_ZRELADDR is enabled, subject to some slight
restrictions), and hence the uImage doesn't need to be loaded to or
moved to any particular location.

The scripts that U-Boot runs determine where the image gets loaded into
memory.

> And this no the job of the kernel to build a boot loader specific boot image
> format.

Not everyone agrees with this.

> And the uImage format here is called the legacy format where now U-Boot
> support a new format based on DT format.
> 
> Will you plan to add it too?

No. The last time I heard anyone talk about that, it sounded like the
adoption was basically zero, so it seems pointless. Personally, I find
creating that kind of image more complex, and don't see any benefits in
that format either.

> no sorry I don't think it's the right way to go.
> 
> On X86 we boot zImage simply. The new uImage option to do not specify the load
> address add nothing more than just boot a zImage for kernel point of view.

U-Boot does not currently have the ability to boot zImage on ARM.

> Further more on server the vendor will use grub mostly (even on ARM) and will
> expect to boot a zImage.

But that is irrelevant for the people who are using U-Boot not grub.


From arnd at arndb.de  Wed Mar  7 13:40:09 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 7 Mar 2012 18:40:09 +0000
Subject: [PATCH 14/14] ARM: kirkwood: use devicetree to init sata_mv
In-Reply-To: <8503a766f6f75c9acf49abd66d9cdce54807b2b2.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <8503a766f6f75c9acf49abd66d9cdce54807b2b2.1331090356.git.jason@lakedaemon.net>
Message-ID: <201203071840.09572.arnd@arndb.de>

On Wednesday 07 March 2012, Jason Cooper wrote:
> @@ -504,6 +504,16 @@ static int __init kirkwood_clock_gate(void)
>                 kirkwood_clk_ctrl |= CGC_USB0;
>                 of_node_put(np);
>         }
> +
> +       np = of_find_compatible_node(NULL, NULL, "mrvl,orion-sata");
> +       if (np && of_device_is_available(np)) {
> +               int nr_ports;
> +               kirkwood_clk_ctrl |= CGC_SATA0;
> +               of_property_read_u32(np, "nr-ports", &nr_ports);
> +               if (nr_ports > 1)
> +                       kirkwood_clk_ctrl |= CGC_SATA1;
> +               of_node_put(np);
> +       }
>  #endif
>  
>         /* For SATA: first shutdown the phy */

Is it guaranteed that it's always the first port that gets used if there
is only one? If not, this might turn on the wrong one.

	Arnd


From jassisinghbrar at gmail.com  Wed Mar  7 13:44:52 2012
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Thu, 8 Mar 2012 00:14:52 +0530
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <20120307182155.GD18787@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <CABb+yY0A9=XKuw=N1fFXCB507zR3U=wofqATVcO_wtnnVrgXzQ@mail.gmail.com>
 <20120307182155.GD18787@n2100.arm.linux.org.uk>
Message-ID: <CABb+yY0SpuOqFP396Q7me3Em=1OYD9Ndt47EXAs6Aem0q-goQA@mail.gmail.com>

On Wed, Mar 7, 2012 at 11:51 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Wed, Mar 07, 2012 at 11:39:25PM +0530, Jassi Brar wrote:
>> Compilation is broken without the following minor fix.
>> After that you may add
>> ? ? ? ?Acked-by: Jassi Brar <jassisinghbrar at gmail.com>
>>
>> diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
>> index 49c123f..abf35a3 100644
>> --- a/drivers/dma/pl330.c
>> +++ b/drivers/dma/pl330.c
>> @@ -339,7 +339,6 @@ static int pl330_control(struct dma_chan *chan,
>> enum dma_ctrl_cmd cmd, unsigned
>> ? ? ? ? ? ? ? /* Mark all desc done */
>> ? ? ? ? ? ? ? list_for_each_entry_safe(desc, _dt, &pch->work_list , node) {
>> ? ? ? ? ? ? ? ? ? ? ? desc->status = DONE;
>> - ? ? ? ? ? ? ? ? ? ? pch->completed = desc->txd.cookie;
>
> I'm not sure just removing this is sufficient. ?Presumably it's
> there for some reason - maybe it needs replacing with a call to
> dma_cookie_complete() to preserve existing behaviour?
>
That was anyway a redundant save in DMA_TERMINATE_ALL, so it should be ok.


From plagnioj at jcrosoft.com  Wed Mar  7 13:36:33 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 19:36:33 +0100
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <4F57AB92.6060907@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <20120307180815.GA27213@game.jcrosoft.org>
 <4F57AB92.6060907@wwwdotorg.org>
Message-ID: <20120307183633.GB27213@game.jcrosoft.org>

On 11:40 Wed 07 Mar     , Stephen Warren wrote:
> On 03/07/2012 11:08 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 17:30 Tue 06 Mar     , Stephen Warren wrote:
> >> This allows the user to use U-Boot's mkimage's -T kernel_noload option
> >> if their arch Kconfig allows it, and they desire.
> >>
> >> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> >> ---
> >> The next patch enables this new CONFIG_ALLOW_ option for ARM. I assume
> >> that some other architectures will also be able to enable it, but I'm
> >> not familiar enough with any to know which.
> > I'm going to repeat. I don't think any impromevent here.
> > 
> > with no specific kernel load address the uImage for is useless/
> 
> No, the whole point of this type of kernel image is that it doesn't need
> a specific load address; the kernel zImage can run from anywhere in RAM
> (provided AUTO_ZRELADDR is enabled, subject to some slight
> restrictions), and hence the uImage doesn't need to be loaded to or
> moved to any particular location.
> 
> The scripts that U-Boot runs determine where the image gets loaded into
> memory.
so instead of spending time on the uImage add simply the support the zImage to
U-Boot as this AUTO_ZRELADDR have 0 advantage compare to the zImage

> 
> > And this no the job of the kernel to build a boot loader specific boot image
> > format.
> 
> Not everyone agrees with this.
so if a new boot loader apear or a new format the kernel will have to support
it. No
> 
> > And the uImage format here is called the legacy format where now U-Boot
> > support a new format based on DT format.
> > 
> > Will you plan to add it too?
> 
> No. The last time I heard anyone talk about that, it sounded like the
> adoption was basically zero, so it seems pointless. Personally, I find
> creating that kind of image more complex, and don't see any benefits in
> that format either.
> 
> > no sorry I don't think it's the right way to go.
> > 
> > On X86 we boot zImage simply. The new uImage option to do not specify the load
> > address add nothing more than just boot a zImage for kernel point of view.
> 
> U-Boot does not currently have the ability to boot zImage on ARM.
so add it and drop the uImage format
> 
> > Further more on server the vendor will use grub mostly (even on ARM) and will
> > expect to boot a zImage.
> 
> But that is irrelevant for the people who are using U-Boot not grub.
execpt the zIamge is the common boot format for all the server and PC and
other boot loader

Best Regards,
J.


From arnd at arndb.de  Wed Mar  7 13:49:36 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 7 Mar 2012 18:49:36 +0000
Subject: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support
In-Reply-To: <20120307173828.GD17087@game.jcrosoft.org>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <201203022024.19488.arnd@arndb.de> <20120307173828.GD17087@game.jcrosoft.org>
Message-ID: <201203071849.36867.arnd@arndb.de>

On Wednesday 07 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 20:24 Fri 02 Mar     , Arnd Bergmann wrote:
> > On Friday 02 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > +       }
> > > +
> > > +       if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
> > > +               have_rtt = false;
> > > +               have_rtc = true;
> > > +       } else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
> > > +               have_rtt = true;
> > > +               have_rtc = true;
> > > +       } else {
> > > +               have_rtt = true;
> > > +               have_rtc = false;
> > > +       }
> > > +
> > > +       if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
> > > +                       mode |= AT91_SHDW_RTCWKEN;
> > > +
> > > +       if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
> > > +                       mode |= AT91_SHDW_RTTWKEN;
> > > +
> > > +       at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
> > > +
> > 
> > Hi Jean-Christophe,
> > 
> > I don't understand why you check the specific part here. Isn't it enough to
> > check the property when you already mandate that they can only be present
> > on devices that support the specific wakeup?
> > 
> > If there is a good explanation for that, maybe add a code comment why it's
> > required.
> some wake update source exist on few soc and we are not supposed to set the
> bit otherwise
> 

I still don't understand: Doesn't the property already give the information?
In general, you should try to encode these things in specific properties instead of
checking the compatible property.

	Arnd


From nico at fluxnic.net  Wed Mar  7 13:50:22 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 07 Mar 2012 13:50:22 -0500 (EST)
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <20120307180815.GA27213@game.jcrosoft.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <20120307180815.GA27213@game.jcrosoft.org>
Message-ID: <alpine.LFD.2.02.1203071336210.24151@xanadu.home>

On Wed, 7 Mar 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:

> On 17:30 Tue 06 Mar     , Stephen Warren wrote:
> > This allows the user to use U-Boot's mkimage's -T kernel_noload option
> > if their arch Kconfig allows it, and they desire.
> > 
> > Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> > ---
> > The next patch enables this new CONFIG_ALLOW_ option for ARM. I assume
> > that some other architectures will also be able to enable it, but I'm
> > not familiar enough with any to know which.
> I'm going to repeat. I don't think any impromevent here.

You know what?  I agree with you... on a conceptual level only though.

In reality, some people are are just too used to it, either for 
emotional reasons or simply because that's what was there before so they 
simply perpetuated it without thinking further, or whatever.  REmoving 
that support would just upset a lot of people.  And frankly we have 
better things to do than starting a flamewar over this.

So the next best thing is to make this u-Boot stuff well contained in a 
common place and make sure it doesn't spread incoherently over multiple 
architecture's directories and makefiles.  This way the u-Boot cruft 
won't be the ARM maintainer, or the PPC maintainer, or the SPARC 
maintainer, or any other architecture maintainer's business, but the 
responsibility of those who do care about it without affecting anyone 
else.

> And the uImage format here is called the legacy format where now U-Boot
> support a new format based on DT format.
> 
> Will you plan to add it too?

Why not if someone cares?  At least this will be done only 
once, centrally, without having to involve architecture maintainers.


Nicolas


From jason at lakedaemon.net  Wed Mar  7 13:52:04 2012
From: jason at lakedaemon.net (Jason)
Date: Wed, 7 Mar 2012 13:52:04 -0500
Subject: [PATCH 14/14] ARM: kirkwood: use devicetree to init sata_mv
In-Reply-To: <201203071840.09572.arnd@arndb.de>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <8503a766f6f75c9acf49abd66d9cdce54807b2b2.1331090356.git.jason@lakedaemon.net>
 <201203071840.09572.arnd@arndb.de>
Message-ID: <20120307185204.GD5050@titan.lakedaemon.net>

On Wed, Mar 07, 2012 at 06:40:09PM +0000, Arnd Bergmann wrote:
> On Wednesday 07 March 2012, Jason Cooper wrote:
> > @@ -504,6 +504,16 @@ static int __init kirkwood_clock_gate(void)
> >                 kirkwood_clk_ctrl |= CGC_USB0;
> >                 of_node_put(np);
> >         }
> > +
> > +       np = of_find_compatible_node(NULL, NULL, "mrvl,orion-sata");
> > +       if (np && of_device_is_available(np)) {
> > +               int nr_ports;
> > +               kirkwood_clk_ctrl |= CGC_SATA0;
> > +               of_property_read_u32(np, "nr-ports", &nr_ports);
> > +               if (nr_ports > 1)
> > +                       kirkwood_clk_ctrl |= CGC_SATA1;
> > +               of_node_put(np);
> > +       }
> >  #endif
> >  
> >         /* For SATA: first shutdown the phy */
> 
> Is it guaranteed that it's always the first port that gets used if there
> is only one? If not, this might turn on the wrong one.

This is the same logic as mach-kirkwood/common.c:176

void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
{
        kirkwood_clk_ctrl |= CGC_SATA0;
        if (sata_data->n_ports > 1)
                kirkwood_clk_ctrl |= CGC_SATA1;

        orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
}

So, I don't think I'm introducing a regression.

thx,

Jason.


From arnd at arndb.de  Wed Mar  7 14:00:47 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 7 Mar 2012 19:00:47 +0000
Subject: [PATCH 14/14] ARM: kirkwood: use devicetree to init sata_mv
In-Reply-To: <20120307185204.GD5050@titan.lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203071840.09572.arnd@arndb.de>
 <20120307185204.GD5050@titan.lakedaemon.net>
Message-ID: <201203071900.48096.arnd@arndb.de>

On Wednesday 07 March 2012, Jason wrote:
> > Is it guaranteed that it's always the first port that gets used if there
> > is only one? If not, this might turn on the wrong one.
> 
> This is the same logic as mach-kirkwood/common.c:176
> 
> void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
> {
>         kirkwood_clk_ctrl |= CGC_SATA0;
>         if (sata_data->n_ports > 1)
>                 kirkwood_clk_ctrl |= CGC_SATA1;
> 
>         orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
> }
> 
> So, I don't think I'm introducing a regression.

Ok, good point. I was wondering whether the individual ports should
be modeled in the device tree, but I guess it's not necessary if nobody
needed this so far.

	Arnd


From nsekhar at ti.com  Wed Mar  7 14:02:18 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 7 Mar 2012 19:02:18 +0000
Subject: [GIT PULL] maintainers file updates for DaVinci
Message-ID: <DF0F476B391FA8409C78302C7BA518B6317ECFD3@DBDE01.ent.ti.com>

Hi Arnd, Olof,

Can you please pull the following MAINTAINERS file
updates for DaVinci for v3.4?

Thanks,
Sekhar

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
  Linus Torvalds (1):
        Linux 3.3-rc6

are available in the git repository at:

  git://gitorious.org/linux-davinci/linux-davinci.git maintainers

Sekhar Nori (2):
      MAINTAINERS: mark TI DaVinci list as "moderated"
      MAINTAINERS: add TI DaVinci git tree information

 MAINTAINERS |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)


From nico at fluxnic.net  Wed Mar  7 14:02:32 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 07 Mar 2012 14:02:32 -0500 (EST)
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <20120307183633.GB27213@game.jcrosoft.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <20120307180815.GA27213@game.jcrosoft.org> <4F57AB92.6060907@wwwdotorg.org>
 <20120307183633.GB27213@game.jcrosoft.org>
Message-ID: <alpine.LFD.2.02.1203071354510.24151@xanadu.home>

On Wed, 7 Mar 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:

> On 11:40 Wed 07 Mar     , Stephen Warren wrote:
> > On 03/07/2012 11:08 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 17:30 Tue 06 Mar     , Stephen Warren wrote:
> > >> This allows the user to use U-Boot's mkimage's -T kernel_noload option
> > >> if their arch Kconfig allows it, and they desire.
> > >>
> > >> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> > >> ---
> > >> The next patch enables this new CONFIG_ALLOW_ option for ARM. I assume
> > >> that some other architectures will also be able to enable it, but I'm
> > >> not familiar enough with any to know which.
> > > I'm going to repeat. I don't think any impromevent here.
> > > 
> > > with no specific kernel load address the uImage for is useless/
> > 
> > No, the whole point of this type of kernel image is that it doesn't need
> > a specific load address; the kernel zImage can run from anywhere in RAM
> > (provided AUTO_ZRELADDR is enabled, subject to some slight
> > restrictions), and hence the uImage doesn't need to be loaded to or
> > moved to any particular location.
> > 
> > The scripts that U-Boot runs determine where the image gets loaded into
> > memory.
> so instead of spending time on the uImage add simply the support the zImage to
> U-Boot as this AUTO_ZRELADDR have 0 advantage compare to the zImage

This was attempted in the past with the result that you might guess.

> > > And this no the job of the kernel to build a boot loader specific boot image
> > > format.
> > 
> > Not everyone agrees with this.
> so if a new boot loader apear or a new format the kernel will have to support
> it. No

Well, apparently new bootloaders are being corrupted by the u-Boot image 
format themselves.

And in the end I don't mind that much, as long as this is once again 
made architecture independent and therefore implemented in an 
architecture independent way in the kernel build system.

> > U-Boot does not currently have the ability to boot zImage on ARM.
> so add it and drop the uImage format

Why don't you try yourself?  I bet you already did in the past.

> > > Further more on server the vendor will use grub mostly (even on ARM) and will
> > > expect to boot a zImage.
> > 
> > But that is irrelevant for the people who are using U-Boot not grub.
> execpt the zIamge is the common boot format for all the server and PC and
> other boot loader

Look Jean-Christophe, we do have a kernel maintenance problem here.  
The goal of this patch series is to solve that maintenance problem while 
preserving the same level of support as before, not to change the world.


Nicolas


From plagnioj at jcrosoft.com  Wed Mar  7 13:59:05 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 19:59:05 +0100
Subject: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support
In-Reply-To: <201203071849.36867.arnd@arndb.de>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <201203022024.19488.arnd@arndb.de>
 <20120307173828.GD17087@game.jcrosoft.org>
 <201203071849.36867.arnd@arndb.de>
Message-ID: <20120307185905.GC27213@game.jcrosoft.org>

On 18:49 Wed 07 Mar     , Arnd Bergmann wrote:
> On Wednesday 07 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 20:24 Fri 02 Mar     , Arnd Bergmann wrote:
> > > On Friday 02 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > > +       }
> > > > +
> > > > +       if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
> > > > +               have_rtt = false;
> > > > +               have_rtc = true;
> > > > +       } else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
> > > > +               have_rtt = true;
> > > > +               have_rtc = true;
> > > > +       } else {
> > > > +               have_rtt = true;
> > > > +               have_rtc = false;
> > > > +       }
> > > > +
> > > > +       if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
> > > > +                       mode |= AT91_SHDW_RTCWKEN;
> > > > +
> > > > +       if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
> > > > +                       mode |= AT91_SHDW_RTTWKEN;
> > > > +
> > > > +       at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
> > > > +
> > > 
> > > Hi Jean-Christophe,
> > > 
> > > I don't understand why you check the specific part here. Isn't it enough to
> > > check the property when you already mandate that they can only be present
> > > on devices that support the specific wakeup?
> > > 
> > > If there is a good explanation for that, maybe add a code comment why it's
> > > required.
> > some wake update source exist on few soc and we are not supposed to set the
> > bit otherwise
> > 
> 
> I still don't understand: Doesn't the property already give the information?
Yes
> In general, you should try to encode these things in specific properties instead of
> checking the compatible property.
But I check that no mistake is done in the DT as the source of wakeup is
availlable on different version of the IP

Just more cautious

Best Regards,
J.


From plagnioj at jcrosoft.com  Wed Mar  7 14:08:20 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 7 Mar 2012 20:08:20 +0100
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <alpine.LFD.2.02.1203071336210.24151@xanadu.home>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <20120307180815.GA27213@game.jcrosoft.org>
 <alpine.LFD.2.02.1203071336210.24151@xanadu.home>
Message-ID: <20120307190820.GD27213@game.jcrosoft.org>

On 13:50 Wed 07 Mar     , Nicolas Pitre wrote:
> On Wed, 7 Mar 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> > On 17:30 Tue 06 Mar     , Stephen Warren wrote:
> > > This allows the user to use U-Boot's mkimage's -T kernel_noload option
> > > if their arch Kconfig allows it, and they desire.
> > > 
> > > Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> > > ---
> > > The next patch enables this new CONFIG_ALLOW_ option for ARM. I assume
> > > that some other architectures will also be able to enable it, but I'm
> > > not familiar enough with any to know which.
> > I'm going to repeat. I don't think any impromevent here.
> 
> You know what?  I agree with you... on a conceptual level only though.
> 
> In reality, some people are are just too used to it, either for 
> emotional reasons or simply because that's what was there before so they 
> simply perpetuated it without thinking further, or whatever.  REmoving 
> that support would just upset a lot of people.  And frankly we have 
> better things to do than starting a flamewar over this.
My concern is this new feature is available on new version of U-Boot only
and people that does not have it and built the uImage are going to ask the
question. Why bla bla bla....

Where people are supposed to RTFM

I do do not want to have the answer this and manage this.
> 
> So the next best thing is to make this u-Boot stuff well contained in a 
> common place and make sure it doesn't spread incoherently over multiple 
> architecture's directories and makefiles.  This way the u-Boot cruft 
> won't be the ARM maintainer, or the PPC maintainer, or the SPARC 
> maintainer, or any other architecture maintainer's business, but the 
> responsibility of those who do care about it without affecting anyone 
> else.
Ditto here

People does not read the doc they as lazy and I do not want to manage this.

> 
> > And the uImage format here is called the legacy format where now U-Boot
> > support a new format based on DT format.
> > 
> > Will you plan to add it too?
> 
> Why not if someone cares?  At least this will be done only 
> once, centrally, without having to involve architecture maintainers.
So you manage this because I will not answer one e-mail that ask for help
Because for my point of view RTFM or boot the zImage

Best Regards,
J.


From jason at lakedaemon.net  Wed Mar  7 14:27:23 2012
From: jason at lakedaemon.net (Jason)
Date: Wed, 7 Mar 2012 14:27:23 -0500
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <201203071831.31738.arnd@arndb.de>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <80fb8cef577eee14364e95009f7a590fd9056ee3.1331090356.git.jason@lakedaemon.net>
 <201203071831.31738.arnd@arndb.de>
Message-ID: <20120307192723.GE5050@titan.lakedaemon.net>

On Wed, Mar 07, 2012 at 06:31:31PM +0000, Arnd Bergmann wrote:
> On Wednesday 07 March 2012, Jason Cooper wrote:
> > +       serial at f1012000 {
> > +               compatible = "ns16550a";
> > +               reg = <0xf1012000 0xff>;
> > +               reg-shift = <2>;
> > +               interrupts = <33>;
> > +               clock-frequency = <200000000>;
> > +       };
> 
> I just noticed that the length here should be inclusive, i.e. 0x100 not 0xff.
> This is different from the way we define resources in Linux.

Grrr.  Now I'm getting frustrated.  I'm trying to boot without
earlyprintk.  Evidently, something is wrong with the above, because the
device boots all the way up (blinky lights come on), but I get no
messages after the usual "Uncompressing Linux... done, booting the
kernel."

Here's my most recent attempt:

        serial at f1012000 {
                device_type = "serial";
                compatible = "ns16550a";
                reg = <0xf1012000 0x100>; /*phys addr*/
                virt-reg = <0xfed12000>;  /*virt addr*/
                reg-shift = <2>;
                reg-io-width = <1>;
                interrupts = <33>;
                current-speed = <115200>;
                interrupt-parent = <&intc>;
                clock-frequency = <200000000>;
        };

I've looked at what is done in the powerpc dt's, but, no luck.  When
earlyprintk is enabled, I see no error messages, just:

bootconsole [earlycon0] enabled
debug: skip boot console de-registration.
...
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled

Any pointers?

thx,

Jason.


From robherring2 at gmail.com  Wed Mar  7 14:30:46 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 07 Mar 2012 13:30:46 -0600
Subject: [PATCH 1/5 v2] i2c/gpio: add DT support
In-Reply-To: <20120307172223.GB17087@game.jcrosoft.org>
References: <1330525221-25651-1-git-send-email-plagnioj@jcrosoft.com>
 <4F5797F4.2040104@gmail.com> <20120307172223.GB17087@game.jcrosoft.org>
Message-ID: <4F57B766.3010701@gmail.com>

On 03/07/2012 11:22 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 11:16 Wed 07 Mar     , Rob Herring wrote:
>> On 02/29/2012 08:20 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>>> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
>>> Cc: linux-i2c at vger.kernel.org
>>> Cc: devicetree-discuss at lists.ozlabs.org
>>> ---
>>> v2:
>>>
>>> 	use devm_kzalloc
>>> 	use i2c-gpio
>>> 	use time name in the properties
>>>
>>> Best Regars,
>>> J.
>>>  .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 +++++++
>>>  drivers/i2c/busses/i2c-gpio.c                      |   95 +++++++++++++++----
>>>  2 files changed, 107 insertions(+), 20 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
>>> new file mode 100644
>>> index 0000000..27e1b1a
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
>>> @@ -0,0 +1,32 @@
>>> +Device-Tree bindings for i2c gpio driver
>>> +
>>> +Required properties:
>>> +	- compatible = "i2c-gpio";
>>> +	- gpios: sda and scl gpio
>>> +
>>> +
>>> +Optional properties:
>>> +	- i2c-gpio,sda-open-drain: sda as open drain
>>> +	- i2c-gpio,scl-open-drain: scl as open drain
>>> +	- i2c-gpio,scl-output-only: scl as output only
>>> +	- udelay: delay between GPIO operations (may depend on each platform)
>>
>> i2c-gpio,delay-us
>>
>>> +	- i2c-algo-bit,timeout-milliseconds: timeout to get data
>>
>> i2c-gpio,timeout-ms
> it's algo-bit speficic no i2c-gpio that's why I use i2c-algo-bit

Don't bring Linux into the binding. I would have to look at the Linux
driver to understand your reasoning.

>>
>>> +
>>> +Example nodes:
>>> +
>>> +i2c-gpio at 0 {
>>
>> Should be "i2c at 0"
> ok
>>
>>> +	compatible = "i2c-gpio";
>>> +	gpios = <&pioA 23 0 /* sda */
>>> +		 &pioA 24 0 /* scl */
>>> +		>;
>>> +	i2c-gpio,sda-open-drain;
>>> +	i2c-gpio,scl-open-drain;
>>> +	udelay = <2>;		/* ~100 kHz */
>>> +	#address-cells = <1>;
>>> +	#size-cells = <0>;
>>> +
>>> +	rv3029c2 at 56 {
>>> +		compatible = "rv3029c2";
>>> +		reg = <0x56>;
>>> +	};
>>> +};
>>> diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
>>> index a651779..71adba5 100644
>>> --- a/drivers/i2c/busses/i2c-gpio.c
>>> +++ b/drivers/i2c/busses/i2c-gpio.c
>>> @@ -14,8 +14,15 @@
>>>  #include <linux/module.h>
>>>  #include <linux/slab.h>
>>>  #include <linux/platform_device.h>
>>> +#include <linux/gpio.h>
>>> +#include <linux/of_gpio.h>
>>> +#include <linux/of_i2c.h>
>>>  
>>> -#include <asm/gpio.h>
>>> +struct i2c_gpio_private_data {
>>> +	struct i2c_adapter adap;
>>> +	struct i2c_algo_bit_data bit_data;
>>> +	struct i2c_gpio_platform_data pdata;
>>> +};
>>>  
>>>  /* Toggle SDA by changing the direction of the pin */
>>>  static void i2c_gpio_setsda_dir(void *data, int state)
>>> @@ -78,24 +85,63 @@ static int i2c_gpio_getscl(void *data)
>>>  	return gpio_get_value(pdata->scl_pin);
>>>  }
>>>  
>>> +static int __devinit of_i2c_gpio_probe(struct device_node *np,
>>> +			     struct i2c_gpio_platform_data *pdata)
>>> +{
>>> +	u32 reg;
>>> +
>>> +	if (of_gpio_count(np) < 2)
>>> +		return -ENODEV;
>>> +
>>> +	pdata->sda_pin = of_get_gpio(np, 0);
>>> +	pdata->scl_pin = of_get_gpio(np, 1);
>>> +
>>> +	if (pdata->sda_pin < 0 || pdata->scl_pin < 0) {
>>> +		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
>>> +		       np->full_name, pdata->sda_pin, pdata->scl_pin);
>>> +		return -ENODEV;
>>> +	}
>>> +
>>> +	if (of_property_read_u32(np, "udelay", &reg))
>>> +		pdata->udelay = reg;
>>
>> Why not of_property_read_u32(np, "udelay", &pdata->udelay)?
>>
>> Also, reg may not be initialized here.
> if udelay have any error we keep udelay as 0
> 

Right, so there is no init issue with reg, but still you can just right
this and get rid of the if:

of_property_read_u32(np, "udelay", &pdata->udelay);

If there's an error, the value will be unchanged.

Rob

> Best Regards,
> J.



From nico at fluxnic.net  Wed Mar  7 14:31:06 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 07 Mar 2012 14:31:06 -0500 (EST)
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <20120307190820.GD27213@game.jcrosoft.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <20120307180815.GA27213@game.jcrosoft.org>
 <alpine.LFD.2.02.1203071336210.24151@xanadu.home>
 <20120307190820.GD27213@game.jcrosoft.org>
Message-ID: <alpine.LFD.2.02.1203071429060.24151@xanadu.home>

On Wed, 7 Mar 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:

> On 13:50 Wed 07 Mar     , Nicolas Pitre wrote:
> > On Wed, 7 Mar 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > 
> > > On 17:30 Tue 06 Mar     , Stephen Warren wrote:
> > > > This allows the user to use U-Boot's mkimage's -T kernel_noload option
> > > > if their arch Kconfig allows it, and they desire.
> > > > 
> > > > Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> > > > ---
> > > > The next patch enables this new CONFIG_ALLOW_ option for ARM. I assume
> > > > that some other architectures will also be able to enable it, but I'm
> > > > not familiar enough with any to know which.
> > > I'm going to repeat. I don't think any impromevent here.
> > 
> > You know what?  I agree with you... on a conceptual level only though.
> > 
> > In reality, some people are are just too used to it, either for 
> > emotional reasons or simply because that's what was there before so they 
> > simply perpetuated it without thinking further, or whatever.  REmoving 
> > that support would just upset a lot of people.  And frankly we have 
> > better things to do than starting a flamewar over this.
> My concern is this new feature is available on new version of U-Boot only
> and people that does not have it and built the uImage are going to ask the
> question. Why bla bla bla....
> 
> Where people are supposed to RTFM
> 
> I do do not want to have the answer this and manage this.

Well, just don't then.


Nicolas


From khilman at ti.com  Wed Mar  7 14:36:57 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 07 Mar 2012 11:36:57 -0800
Subject: [PATCH v3] ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
 regulators
In-Reply-To: <CA+Bv8XaJqL1L8F-n6skY7dHn1XAdDLRKaRjw0deLeoQ5Ao0Fhg@mail.gmail.com>
 (Russ Dill's message of "Wed, 7 Mar 2012 10:00:08 -0600")
References: <1330006564-13290-1-git-send-email-mporter@ti.com>
 <87wr74gis6.fsf@ti.com>
 <20120301204553.GA21841@legolas.emea.dhcp.ti.com>
 <87pqcqnc7u.fsf@ti.com>
 <CA+Bv8XaJqL1L8F-n6skY7dHn1XAdDLRKaRjw0deLeoQ5Ao0Fhg@mail.gmail.com>
Message-ID: <87sjhkjj8m.fsf@ti.com>

Hi Russ,

Russ Dill <Russ.Dill at ti.com> writes:

> On Mon, Mar 5, 2012 at 12:18 PM, Kevin Hilman <khilman at ti.com> wrote:
>> Felipe Balbi <balbi at ti.com> writes:
>>
>>> Hi,
>>>
>>> On Thu, Mar 01, 2012 at 12:36:57PM -0800, Kevin Hilman wrote:
>>>> Matt Porter <mporter at ti.com> writes:
>>>>
>>>> > This fixes smsc911x support on platforms using gpmc_smsc911x_init().
>>>> >
>>>> > Commit c7e963f6888816 (net/smsc911x: Add regulator support) added
>>>> > the requirement that platforms provide vdd33a and vddvario supplies.
>>>> >
>>>> > Signed-off-by: Matt Porter <mporter at ti.com>
>>>>
>>>> [...]
>>>>
>>>> > ?/*
>>>> > ? * Initialize smsc911x device connected to the GPMC. Note that we
>>>> > ? * assume that pin multiplexing is done in the board-*.c file,
>>>> > @@ -55,6 +101,12 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
>>>> >
>>>> > ? ?gpmc_cfg = board_data;
>>>> >
>>>> > + ?ret = platform_device_register(&gpmc_smsc911x_regulator);
>>>> > + ?if (ret < 0) {
>>>> > + ? ? ? ? ?pr_err("Unable to register smsc911x regulators: %d\n", ret);
>>>> > + ? ? ? ? ?return;
>>>> > + ?}
>>>> > +
>>>>
>>>> Boards that have more than one instance of the smsc911x (OMAP3/Overo)
>>>> barf here because of trying to register the same device twice.
>>>>
>>>> We need something like the patch below to make Overo boot again.
>>>>
>>>> Kevin
>>>>
>>>>
>>>>
>>>> From 4114dea2fb897ab75d05eaa943d29454034fc025 Mon Sep 17 00:00:00 2001
>>>> From: Kevin Hilman <khilman at ti.com>
>>>> Date: Thu, 1 Mar 2012 12:30:42 -0800
>>>> Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulators once
>>>>
>>>> commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
>>>> regulators) added regulators which are registered during
>>>> gpmc_smsc911x_init(). ?However, some platforms (OMAP3/Overo) have more
>>>> than one instance of the SMSC911x and result in attempting to register
>>>> the same regulator more than once which causes a panic(). ?Fix this by
>>>> tracking the regulator registration ensuring only a single device is
>>>> registered.
>>>>
>>>> Cc: Matt Porter <mporter at ti.com>
>>>> Signed-off-by: Kevin Hilman <khilman at ti.com>
>>>> ---
>>>> ?arch/arm/mach-omap2/gpmc-smsc911x.c | ? 14 ++++++++++----
>>>> ?1 file changed, 10 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
>>>> index bbb870c..95e6c7d 100644
>>>> --- a/arch/arm/mach-omap2/gpmc-smsc911x.c
>>>> +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
>>>> @@ -88,6 +88,8 @@ static struct platform_device gpmc_smsc911x_regulator = {
>>>> ? ? ?},
>>>> ?};
>>>>
>>>> +static bool regulator_registered;
>>>> +
>>>> ?/*
>>>> ? * Initialize smsc911x device connected to the GPMC. Note that we
>>>> ? * assume that pin multiplexing is done in the board-*.c file,
>>>> @@ -101,10 +103,14 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
>>>>
>>>> ? ? ?gpmc_cfg = board_data;
>>>>
>>>> - ? ?ret = platform_device_register(&gpmc_smsc911x_regulator);
>>>> - ? ?if (ret < 0) {
>>>> - ? ? ? ? ? ?pr_err("Unable to register smsc911x regulators: %d\n", ret);
>>>> - ? ? ? ? ? ?return;
>>>> + ? ?if (!regulator_registered) {
>>>> + ? ? ? ? ? ?ret = platform_device_register(&gpmc_smsc911x_regulator);
>>>> + ? ? ? ? ? ?if (ret < 0) {
>>>> + ? ? ? ? ? ? ? ? ? ?pr_err("Unable to register smsc911x regulators: %d\n",
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ret);
>>>> + ? ? ? ? ? ? ? ? ? ?return;
>>>> + ? ? ? ? ? ?}
>>>> + ? ? ? ? ? ?regulator_registered = true;
>>>
>>> Wow, this is quite a hack. Is the regulator part of the SMSC911x
>>> device or is it outside ? If it's outside the SMSC91xx (which I
>>> believe it is) there should be a regulator driver instead of this
>>> hack. ?For boards which don't provide such a regulator (and tie the
>>> supply pin to some constant voltage source) there should be a constant
>>> regulator supplying the pin. But this patch is quite hacky.
>>
>> Are you referring to my patch or to the original $SUBJECT patch? ?It's
>> not terribly clear.
>>
>> My patch doesn't add any regulators, it just fixes a bug when this init
>> function is called more than once.
>>
>> The addition of the regulators was done in $SUBJECT patch, not my fix.
>>
>> In either case $SUBJECT patch is already in Tony's fixes queue, so if it
>> is going be merged, then my fix above is needed also to not break
>> Overo and any other platform that has more than one smsc911x instance.
>>
>> Kevin
>
>
> Have you tested this fix? 

Yes.  On 3530/Overo.

> The only regulator consumer supply would be:
>
> static struct regulator_consumer_supply gpmc_smsc911x_supply[] = {
>         REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
>         REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
> };
>
> I don't think the second smsc911x on the Overo, "smsc911x.1", would
> find it due to the dev_id.

It's not about finding the second regulator.  As stated in the
changelog, it's about the duplicate attempt to register the exact same
platform_device.

Duplicate attempts to register the exact same platform_device cause
kobject to panic and give up[1].  So, any platform that calls
gpmc_smsc911x_init() twice (Overo and T35 in mainline) will panic on
boot.

This patch fixes those platforms so they can boot.

Kevin



[1]
[    0.337036] kobject (c06b1730): tried to init an initialized object, something is seriously wrong.
[    0.346679] [<c001421c>] (unwind_backtrace+0x0/0xf0) from [<c022b944>] (kobject_init+0x74/0x94)
[    0.355804] [<c022b944>] (kobject_init+0x74/0x94) from [<c0284fa8>] (device_initialize+0x20/0x90)
[    0.365112] [<c0284fa8>] (device_initialize+0x20/0x90) from [<c02894fc>] (platform_device_register+0x10/0x24)
[    0.375488] [<c02894fc>] (platform_device_register+0x10/0x24) from [<c0619d7c>] (gpmc_smsc911x_init+0x1c/0x200)
[    0.386077] [<c0619d7c>] (gpmc_smsc911x_init+0x1c/0x200) from [<c06165e0>] (overo_init+0xdc/0x27c)
[    0.395446] [<c06165e0>] (overo_init+0xdc/0x27c) from [<c0609380>] (customize_machine+0x1c/0x28)
[    0.404663] [<c0609380>] (customize_machine+0x1c/0x28) from [<c0008800>] (do_one_initcall+0x34/0x178)
[    0.414306] [<c0008800>] (do_one_initcall+0x34/0x178) from [<c06068ac>] (kernel_init+0x8c/0x130)
[    0.423553] [<c06068ac>] (kernel_init+0x8c/0x130) from [<c000e850>] (kernel_thread_exit+0x0/0x8)
[    0.432800] ------------[ cut here ]------------
[    0.437652] WARNING: at /work/kernel/omap/pm/fs/sysfs/dir.c:481 sysfs_add_one+0x88/0xb0()
[    0.446228] sysfs: cannot create duplicate filename '/devices/platform/reg-fixed-voltage.42'
[    0.455047] Modules linked in:
[    0.458312] [<c001421c>] (unwind_backtrace+0x0/0xf0) from [<c00391e4>] (warn_slowpath_common+0x4c/0x64)
[    0.468170] [<c00391e4>] (warn_slowpath_common+0x4c/0x64) from [<c0039290>] (warn_slowpath_fmt+0x30/0x40)
[    0.478179] [<c0039290>] (warn_slowpath_fmt+0x30/0x40) from [<c014eed8>] (sysfs_add_one+0x88/0xb0)
[    0.487548] [<c014eed8>] (sysfs_add_one+0x88/0xb0) from [<c014ef60>] (create_dir+0x60/0xc4)
[    0.496307] [<c014ef60>] (create_dir+0x60/0xc4) from [<c014f048>] (sysfs_create_dir+0x58/0x8c)
[    0.505340] [<c014f048>] (sysfs_create_dir+0x58/0x8c) from [<c022bbec>] (kobject_add_internal+0x9c/0x1b8)
[    0.515350] [<c022bbec>] (kobject_add_internal+0x9c/0x1b8) from [<c022bfd8>] (kobject_add+0x50/0x98)
[    0.524932] [<c022bfd8>] (kobject_add+0x50/0x98) from [<c0285a14>] (device_add+0xb8/0x358)
[    0.533599] [<c0285a14>] (device_add+0xb8/0x358) from [<c0289234>] (platform_device_add+0xf8/0x1a4)
[    0.543090] [<c0289234>] (platform_device_add+0xf8/0x1a4) from [<c0619d7c>] (gpmc_smsc911x_init+0x1c/0x200)
[    0.553283] [<c0619d7c>] (gpmc_smsc911x_init+0x1c/0x200) from [<c06165e0>] (overo_init+0xdc/0x27c)
[    0.562652] [<c06165e0>] (overo_init+0xdc/0x27c) from [<c0609380>] (customize_machine+0x1c/0x28)
[    0.571868] [<c0609380>] (customize_machine+0x1c/0x28) from [<c0008800>] (do_one_initcall+0x34/0x178)
[    0.581512] [<c0008800>] (do_one_initcall+0x34/0x178) from [<c06068ac>] (kernel_init+0x8c/0x130)
[    0.590728] [<c06068ac>] (kernel_init+0x8c/0x130) from [<c000e850>] (kernel_thread_exit+0x0/0x8)
[    0.600372] ---[ end trace 1b75b31a2719ed1c ]---
[    0.605285] kobject_add_internal failed for reg-fixed-voltage.42 with -EEXIST, don't try to register things with the same name in the same directory.
[    0.619262] [<c001421c>] (unwind_backtrace+0x0/0xf0) from [<c022bcf0>] (kobject_add_internal+0x1a0/0x1b8)
[    0.629272] [<c022bcf0>] (kobject_add_internal+0x1a0/0x1b8) from [<c022bfd8>] (kobject_add+0x50/0x98)
[    0.638946] [<c022bfd8>] (kobject_add+0x50/0x98) from [<c0285a14>] (device_add+0xb8/0x358)
[    0.647613] [<c0285a14>] (device_add+0xb8/0x358) from [<c0289234>] (platform_device_add+0xf8/0x1a4)
[    0.657073] [<c0289234>] (platform_device_add+0xf8/0x1a4) from [<c0619d7c>] (gpmc_smsc911x_init+0x1c/0x200)
[    0.667266] [<c0619d7c>] (gpmc_smsc911x_init+0x1c/0x200) from [<c06165e0>] (overo_init+0xdc/0x27c)
[    0.676666] [<c06165e0>] (overo_init+0xdc/0x27c) from [<c0609380>] (customize_machine+0x1c/0x28)
[    0.685852] [<c0609380>] (customize_machine+0x1c/0x28) from [<c0008800>] (do_one_initcall+0x34/0x178)
[    0.695526] [<c0008800>] (do_one_initcall+0x34/0x178) from [<c06068ac>] (kernel_init+0x8c/0x130)
[    0.704711] [<c06068ac>] (kernel_init+0x8c/0x130) from [<c000e850>] (kernel_thread_exit+0x0/0x8)
[    0.713897] gpmc_smsc911x_init: Unable to register smsc911x regulators: -17



From robherring2 at gmail.com  Wed Mar  7 14:41:20 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 07 Mar 2012 13:41:20 -0600
Subject: [PATCH 1/1] of: add dma-mask binding
In-Reply-To: <20120307173437.GC17087@game.jcrosoft.org>
References: <1331119575-6638-1-git-send-email-plagnioj@jcrosoft.com>
 <4F5793E9.9010100@gmail.com> <20120307173437.GC17087@game.jcrosoft.org>
Message-ID: <4F57B9E0.3030109@gmail.com>

On 03/07/2012 11:34 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 10:59 Wed 07 Mar     , Rob Herring wrote:
>> On 03/07/2012 05:26 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> This will allow each device to specify its dma-mask
>>> The microblaze architecture hook is keep temporary if no dma-mask is specified
>>> int the DT
>>>
>>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>>> ---
>>>  drivers/of/platform.c |   26 +++++++++++++++++++++++++-
>>>  1 files changed, 25 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/drivers/of/platform.c b/drivers/of/platform.c
>>> index cae9477..bb22194 100644
>>> --- a/drivers/of/platform.c
>>> +++ b/drivers/of/platform.c
>>> @@ -121,6 +121,26 @@ void of_device_make_bus_id(struct device *dev)
>>>  	dev_set_name(dev, "%s.%d", node->name, magic - 1);
>>>  }
>>>  
>>> +static u64* of_get_dma_mask(struct device_node *np)
>>> +{
>>> +	const __be32 *prop;
>>> +	int len;
>>> +	u64 *dma_mask;
>>> +
>>> +	prop = of_get_property(np, "dma-mask", &len);
>>
>> This would need some documentation. There is already "dma-ranges"
>> defined for OF which nay do what's needed.
> what is dma-ranges I see no doc about it
> but I don't think it could be used for the dma mask

See the ePAPR spec. It's a PowerPC doc, but parts still apply.

https://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.1.pdf

There may also be something in OpenFirmware specs.

>>
>>> +
>>> +	if (!prop)
>>> +		return NULL;
>>> +
>>> +	dma_mask = kzalloc(sizeof(u64), GFP_KERNEL);
>>
>> This seems kind of wasteful for 1 u64.
> no choice dma_mask must be a pointer
>>
>>> +	if (!dma_mask)
>>> +		return NULL;
>>> +
>>> +	*dma_mask = of_read_number(prop, len / 4);
>>> +
>>> +	return dma_mask;
>>> +}
>>> +
>>>  /**
>>>   * of_device_alloc - Allocate and initialize an of_device
>>>   * @np: device node to assign to device
>>> @@ -161,10 +181,14 @@ struct platform_device *of_device_alloc(struct device_node *np,
>>>  		WARN_ON(of_irq_to_resource_table(np, res, num_irq) != num_irq);
>>>  	}
>>>  
>>> +	dev->dev.dma_mask = of_get_dma_mask(np);
>>>  	dev->dev.of_node = of_node_get(np);
>>> +
>>>  #if defined(CONFIG_MICROBLAZE)
>>> -	dev->dev.dma_mask = &dev->archdata.dma_mask;
>>
>> And doing it this way for didn't get a warm reception either:
>>
>> http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-April/005285.html
>>
>> Do you really need this to be something other than ~0UL and if so does
>> it need to be per device or system wide?
>>
>> You can solve this with bus notifiers in your at91 code. Here's an
>> example which I did (but no longer need):
>>
>> static u64 highbank_dma_mask = DMA_BIT_MASK(32);
> IIRC on at91 all of them that need it have a DMA_BIT_MASK(32)
> 
> 
>>
>> static int highbank_platform_notifier(struct notifier_block *nb,
>> 				  unsigned long event, void *__dev)
>> {
>> 	struct device *dev = __dev;
>>
>> 	if (event != BUS_NOTIFY_ADD_DEVICE)
>> 		return NOTIFY_DONE;
>>
>> 	if (of_device_is_compatible(dev->of_node, "calxeda,hb-nfc"))
>> 		dev->dma_mask = &highbank_dma_mask;
> execpt as example today I need it on 2 node (OHCI & EHCI)

I don't think there is any reason you can't point to a single value if a
system wide setting fits. If not, using a per device value here is
easily doable.

> 
> and if more device need I don't want to end up with more fixup
> 
> I really prefer to set it via DT

You don't have any h/w restrictions here and most ARM platforms don't,
so really this doesn't need to be solved with DT for the default case.

Rob


From robherring2 at gmail.com  Wed Mar  7 14:54:44 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 07 Mar 2012 13:54:44 -0600
Subject: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support
In-Reply-To: <201203071849.36867.arnd@arndb.de>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <201203022024.19488.arnd@arndb.de> <20120307173828.GD17087@game.jcrosoft.org>
 <201203071849.36867.arnd@arndb.de>
Message-ID: <4F57BD04.5090002@gmail.com>

On 03/07/2012 12:49 PM, Arnd Bergmann wrote:
> On Wednesday 07 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
>> On 20:24 Fri 02 Mar     , Arnd Bergmann wrote:
>>> On Friday 02 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>> +       }
>>>> +
>>>> +       if (of_device_is_compatible(np, "atmel,at91sam9x5-shdwc")) {
>>>> +               have_rtt = false;
>>>> +               have_rtc = true;
>>>> +       } else if (of_device_is_compatible(np, "atmel,at91sam9rl-shdwc")) {
>>>> +               have_rtt = true;
>>>> +               have_rtc = true;
>>>> +       } else {
>>>> +               have_rtt = true;
>>>> +               have_rtc = false;
>>>> +       }
>>>> +
>>>> +       if (have_rtc && of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
>>>> +                       mode |= AT91_SHDW_RTCWKEN;
>>>> +
>>>> +       if (have_rtt && of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
>>>> +                       mode |= AT91_SHDW_RTTWKEN;
>>>> +
>>>> +       at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
>>>> +
>>>
>>> Hi Jean-Christophe,
>>>
>>> I don't understand why you check the specific part here. Isn't it enough to
>>> check the property when you already mandate that they can only be present
>>> on devices that support the specific wakeup?
>>>
>>> If there is a good explanation for that, maybe add a code comment why it's
>>> required.
>> some wake update source exist on few soc and we are not supposed to set the
>> bit otherwise
>>
> 
> I still don't understand: Doesn't the property already give the information?
> In general, you should try to encode these things in specific properties instead of
> checking the compatible property.
> 

Or vice-versa, the compatible properties distinguish things enough that
the property is not needed. If it is fixed in the SOC design, then you
should distinguish things with the compatible property.

Rob

> 	Arnd
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From robherring2 at gmail.com  Wed Mar  7 14:58:06 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 07 Mar 2012 13:58:06 -0600
Subject: [PATCH 5/6] ARM: at91: add ram controller DT support
In-Reply-To: <1330718048-9314-5-git-send-email-plagnioj@jcrosoft.com>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <1330718048-9314-5-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <4F57BDCE.1050708@gmail.com>

On 03/02/2012 01:54 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> We can now drop the call to ioremap_registers() as we have the binding for the
> SDRAM/DDR Controller.
> 
> Drop ioremap_registers() for sam9x5 too.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> ---
>  .../devicetree/bindings/arm/atmel-at91.txt         |   19 ++++++++++++++
>  arch/arm/boot/dts/at91sam9g20.dtsi                 |    5 +++
>  arch/arm/boot/dts/at91sam9g45.dtsi                 |    6 ++++
>  arch/arm/boot/dts/at91sam9x5.dtsi                  |    5 +++
>  arch/arm/mach-at91/at91sam9x5.c                    |    6 ----
>  arch/arm/mach-at91/include/mach/at91sam9x5.h       |    5 ---
>  arch/arm/mach-at91/setup.c                         |   27 +++++++++++++++++--
>  7 files changed, 59 insertions(+), 14 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> index a64f867..1f87820 100644
> --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
> @@ -42,3 +42,22 @@ Example:
>  		compatible = "atmel,at91sam9260-rstc";
>  		reg = <0xfffffd00 0x10>;
>  	};
> +
> +RAMC SDRAM/DDR Controller required properties:
> +- compatible: Should be "atmel,at91sam9260-sdramc",
> +			"atmel,at91sam9g45-ddramc",
> +- reg: Should contain registers location and length
> +  For at91sam9263 and at91sam9g45 you must specify 2 entries.
> +
> +Examples:
> +
> +	ramc0: ramc at ffffe800 {
> +		compatible = "atmel,at91sam9g45-ddramc";
> +		reg = <0xffffe800 0x200>;
> +	};
> +
> +	ramc0: ramc at ffffe400 {
> +		compatible = "atmel,at91sam9g45-ddramc";
> +		reg = <0xffffe400 0x200
> +		       0xffffe600 0x200>;
> +	};
> diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
> index 5414347..573ac5a 100644
> --- a/arch/arm/boot/dts/at91sam9g20.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
> @@ -59,6 +59,11 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			ramc0: ramc at ffffea00 {
> +				compatible = "atmel,at91sam9260-sdramc";
> +				reg = <0xffffea00 0x200>;
> +			};
> +
>  			pmc: pmc at fffffc00 {
>  				compatible = "atmel,at91rm9200-pmc";
>  				reg = <0xfffffc00 0x100>;
> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> index e2ccba5..6da07a9 100644
> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> @@ -60,6 +60,12 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			ramc0: ramc at ffffe400 {
> +				compatible = "atmel,at91sam9g45-ddramc";
> +				reg = <0xffffe400 0x200
> +				       0xffffe600 0x200>;
> +			};
> +
>  			pmc: pmc at fffffc00 {
>  				compatible = "atmel,at91rm9200-pmc";
>  				reg = <0xfffffc00 0x100>;
> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> index 54e3030..09bc806 100644
> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> @@ -58,6 +58,11 @@
>  				reg = <0xfffff000 0x200>;
>  			};
>  
> +			ramc0: ramc at ffffe800 {
> +				compatible = "atmel,at91sam9g45-ddramc";
> +				reg = <0xffffe800 0x200>;
> +			};
> +
>  			pmc: pmc at fffffc00 {
>  				compatible = "atmel,at91rm9200-pmc";
>  				reg = <0xfffffc00 0x100>;
> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> index 0b82c34..b6831ee 100644
> --- a/arch/arm/mach-at91/at91sam9x5.c
> +++ b/arch/arm/mach-at91/at91sam9x5.c
> @@ -302,11 +302,6 @@ static void __init at91sam9x5_map_io(void)
>  	at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
>  }
>  
> -static void __init at91sam9x5_ioremap_registers(void)
> -{
> -	at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
> -}
> -
>  void __init at91sam9x5_initialize(void)
>  {
>  	at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
> @@ -359,7 +354,6 @@ static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
>  struct at91_init_soc __initdata at91sam9x5_soc = {
>  	.map_io = at91sam9x5_map_io,
>  	.default_irq_priority = at91sam9x5_default_irq_priority,
> -	.ioremap_registers = at91sam9x5_ioremap_registers,
>  	.register_clocks = at91sam9x5_register_clocks,
>  	.init = at91sam9x5_initialize,
>  };
> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> index a297a77..88e43d5 100644
> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> @@ -55,11 +55,6 @@
>  #define AT91SAM9X5_BASE_USART2	0xf8024000
>  
>  /*
> - * System Peripherals
> - */
> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
> -
> -/*
>   * Base addresses for early serial code (uncompress.h)
>   */
>  #define AT91_DBGU	AT91_BASE_DBGU0
> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> index 3e48b59..f86450d 100644
> --- a/arch/arm/mach-at91/setup.c
> +++ b/arch/arm/mach-at91/setup.c
> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
>  	of_node_put(np);
>  }
>  
> +static struct of_device_id ramc_ids[] = {
> +	{ .compatible = "atmel,at91sam9260-sdramc" },
> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
> +	{ /*sentinel*/ }
> +};
> +
> +static void at91_dt_ramc(void)
> +{
> +	struct device_node *np;
> +
> +	np = of_find_matching_node(NULL, ramc_ids);
> +	if (!np)
> +		panic("unable to find compatible ram conroller node in dtb\n");

You really can't boot if this fails? A WARN is better if it allows you
to boot until at least your console is actually up.

> +
> +	at91_ramc_base[0] = of_iomap(np, 0);
> +	if (!at91_ramc_base[0])
> +		panic("unable to map ramc[0] cpu registers\n");
> +	/* the controller may have 2 banks */
> +	at91_ramc_base[1] = of_iomap(np, 1);
> +
> +	of_node_put(np);
> +}
> +
>  void __init at91_dt_initialize(void)
>  {
>  	at91_dt_rstc();
> -
> -	/* temporary until have the ramc binding*/
> -	at91_boot_soc.ioremap_registers();
> +	at91_dt_ramc();
>  
>  	/* Init clock subsystem */
>  	at91_dt_clock_init();



From andrew at lunn.ch  Wed Mar  7 15:05:15 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 7 Mar 2012 21:05:15 +0100
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <20120307192723.GE5050@titan.lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <80fb8cef577eee14364e95009f7a590fd9056ee3.1331090356.git.jason@lakedaemon.net>
 <201203071831.31738.arnd@arndb.de>
 <20120307192723.GE5050@titan.lakedaemon.net>
Message-ID: <20120307200515.GC18513@lunn.ch>

On Wed, Mar 07, 2012 at 02:27:23PM -0500, Jason wrote:
> On Wed, Mar 07, 2012 at 06:31:31PM +0000, Arnd Bergmann wrote:
> > On Wednesday 07 March 2012, Jason Cooper wrote:
> > > +       serial at f1012000 {
> > > +               compatible = "ns16550a";
> > > +               reg = <0xf1012000 0xff>;
> > > +               reg-shift = <2>;
> > > +               interrupts = <33>;
> > > +               clock-frequency = <200000000>;
> > > +       };
> > 
> > I just noticed that the length here should be inclusive, i.e. 0x100 not 0xff.
> > This is different from the way we define resources in Linux.
> 
> Grrr.  Now I'm getting frustrated.  I'm trying to boot without
> earlyprintk.  Evidently, something is wrong with the above, because the
> device boots all the way up (blinky lights come on), but I get no
> messages after the usual "Uncompressing Linux... done, booting the
> kernel."

Hi Jason

What do you see in /proc/iomem?

You should expect:

f1012000-f10120ff : serial8250.0
  f1012000-f101201f : serial
f1012100-f10121ff : serial8250.1
  f1012100-f101211f : serial

or probably just the first, if your device only has one serial port.

How about /proc/interrupts?

 33:        195  orion_irq  serial


Anything like this in dmesg?

[   17.189397] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
[   17.210023] serial8250.0: ttyS0 at MMIO 0xf1012000 (irq = 33) is a 16550A
[   17.624748] console [ttyS0] enabled
[   17.648555] serial8250.1: ttyS1 at MMIO 0xf1012100 (irq = 34) is a 16550A

Comparing your system to the above might help you track down which
property is wrong.

	 Andrew


From khilman at ti.com  Wed Mar  7 15:14:38 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 07 Mar 2012 12:14:38 -0800
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators for v3.4
Message-ID: <877gywjhht.fsf@ti.com>

Tony,

Please pull the following support for using regulators to control the
on-chip VC/VP managed voltage domains.

The regulator driver support for this is already queued in the regulator
tree, and this is the supporting core work.

This combined with the CPUfreq changes to use the regulator framework
will finally result in MPU DVFS working in mainline.

Kevin


The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:

  Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/pm/smps-regulator

for you to fetch changes up to c15f1d84bb3ddd668593e9bca53221a2f82e9e99:

  ARM: OMAP2+: voltage: ensure voltage used is exact voltage from OPP table (2012-03-06 17:37:14 -0800)

----------------------------------------------------------------
Kevin Hilman (1):
      ARM: OMAP2+: voltage: ensure voltage used is exact voltage from OPP table

Tero Kristo (4):
      arm: omap3: voltage: fix channel configuration
      arm: omap3: add common twl configurations for vdd1 and vdd2
      arm: omap3: twl: add external controllers for core voltage regulators
      arm: omap4: add common twl configurations for vdd1, vdd2 and vdd3

 arch/arm/mach-omap2/twl-common.c  |  147 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/vc3xxx_data.c |    1 +
 arch/arm/mach-omap2/voltage.c     |   21 +++++-
 3 files changed, 166 insertions(+), 3 deletions(-)


From khilman at ti.com  Wed Mar  7 15:20:41 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 07 Mar 2012 12:20:41 -0800
Subject: [GIT PULL] cpufreq: OMAP updates for v3.4
Message-ID: <87y5rci2na.fsf@ti.com>

Dave,

Please pull the following OMAP CPUfreq driver changes for v3.4.

Thanks,

Kevin



The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:

  Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/cpufreq

for you to fetch changes up to 42daffd2d6c665716d442d518022ecaad17ddf64:

  cpufreq: OMAP: specify range for voltage scaling (2012-03-02 13:55:57 -0800)

----------------------------------------------------------------
Afzal Mohammed (1):
      cpufreq: OMAP: specify range for voltage scaling

Kevin Hilman (1):
      cpufreq: OMAP: scale voltage along with frequency

Russell King (1):
      cpufreq: OMAP driver depends CPUfreq tables

 drivers/cpufreq/Kconfig.arm    |    5 +++
 drivers/cpufreq/Makefile       |    2 +-
 drivers/cpufreq/omap-cpufreq.c |   72 +++++++++++++++++++++++++++++++++++++---
 3 files changed, 73 insertions(+), 6 deletions(-)


From timur at freescale.com  Wed Mar  7 15:20:29 2012
From: timur at freescale.com (Timur Tabi)
Date: Wed, 7 Mar 2012 14:20:29 -0600
Subject: [PATCH v2 09/17] ASoC: fsl: separate SSI and DMA Kconfig options
In-Reply-To: <1330957865-19085-10-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-10-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F57C30D.3000101@freescale.com>

Shawn Guo wrote:
> The fsl_ssi driver will possibly be shared between Freescale PowerPC
> and ARM/IMX families, so give it a separate Kconfig option.  Then
> fsl_ssi driver can possibly be selected independently from selecting
> PowerPC DMA based PCM driver.

This patch is going to require an update to the defconfigs, because by
default, it sets audio as disabled.

menuconfig SND_POWERPC_SOC
	tristate "SoC Audio for Freescale PowerPC CPUs"
	depends on FSL_SOC
	help
	  Say Y or M if you want to add support for codecs attached to
	  the PowerPC CPUs.

The P1022DS uses mpc85xx_smp_defconfig and mpc85xx_defconfig.  The
MPC8610HPCD uses mpc8610_hpcd_defconfig.

-- 
Timur Tabi
Linux kernel developer at Freescale



From stigge at antcom.de  Wed Mar  7 15:21:33 2012
From: stigge at antcom.de (Roland Stigge)
Date: Wed,  7 Mar 2012 21:21:33 +0100
Subject: [PATCH v6] lpc32xx: Added ethernet driver
Message-ID: <1331151693-21726-1-git-send-email-stigge@antcom.de>

This patch adds an ethernet driver for the LPC32xx ARM SoC.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Applies to v3.3-rc6

Changes since v5:
 * Indentation and whitespace fixes
 * Use __le32 for descriptors
 * Use bool for boolean function parameters
 * Removed unnecessary (u32) cast
 * Added comment regarding future device tree introduction

 Thanks to David Miller, Arnd Bergmann and Joe Perches for
 reviewing the last version!

 drivers/net/ethernet/Kconfig       |    1 
 drivers/net/ethernet/Makefile      |    1 
 drivers/net/ethernet/nxp/Kconfig   |    8 
 drivers/net/ethernet/nxp/Makefile  |    1 
 drivers/net/ethernet/nxp/lpc_eth.c | 1616 +++++++++++++++++++++++++++++++++++++
 5 files changed, 1627 insertions(+)

--- linux-2.6.orig/drivers/net/ethernet/Kconfig
+++ linux-2.6/drivers/net/ethernet/Kconfig
@@ -126,6 +126,7 @@ config NET_NETX
 
 source "drivers/net/ethernet/nuvoton/Kconfig"
 source "drivers/net/ethernet/nvidia/Kconfig"
+source "drivers/net/ethernet/nxp/Kconfig"
 source "drivers/net/ethernet/octeon/Kconfig"
 source "drivers/net/ethernet/oki-semi/Kconfig"
 
--- linux-2.6.orig/drivers/net/ethernet/Makefile
+++ linux-2.6/drivers/net/ethernet/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_NET_VENDOR_NATSEMI) += nats
 obj-$(CONFIG_NET_NETX) += netx-eth.o
 obj-$(CONFIG_NET_VENDOR_NUVOTON) += nuvoton/
 obj-$(CONFIG_NET_VENDOR_NVIDIA) += nvidia/
+obj-$(CONFIG_LPC_ENET) += nxp/
 obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon/
 obj-$(CONFIG_NET_VENDOR_OKI) += oki-semi/
 obj-$(CONFIG_ETHOC) += ethoc.o
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/Kconfig
@@ -0,0 +1,8 @@
+config LPC_ENET
+        tristate "NXP ethernet MAC on LPC devices"
+        depends on ARCH_LPC32XX
+        select PHYLIB
+        help
+	  Say Y or M here if you want to use the NXP ethernet MAC included on
+	  some NXP LPC devices. You can safely enable this option for LPC32xx
+	  SoC. Also available as a module.
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_LPC_ENET) += lpc_eth.o
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/lpc_eth.c
@@ -0,0 +1,1616 @@
+/*
+ * drivers/net/ethernet/nxp/lpc_eth.c
+ *
+ * Author: Kevin Wells <kevin.wells at nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ * Copyright (C) 2012 Roland Stigge <stigge at antcom.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/crc32.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/clk.h>
+#include <linux/workqueue.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/phy.h>
+#include <linux/dma-mapping.h>
+#include <linux/of_net.h>
+#include <linux/types.h>
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <mach/board.h>
+#include <mach/platform.h>
+#include <mach/hardware.h>
+
+#define MODNAME "lpc-eth"
+#define DRV_VERSION "1.00"
+#define PHYDEF_ADDR 0x00
+
+#define ENET_MAXF_SIZE 1536
+#define ENET_RX_DESC 48
+#define ENET_TX_DESC 16
+
+#define NAPI_WEIGHT 16
+
+/*
+ * Ethernet MAC controller Register offsets
+ */
+#define LPC_ENET_MAC1(x)			(x + 0x000)
+#define LPC_ENET_MAC2(x)			(x + 0x004)
+#define LPC_ENET_IPGT(x)			(x + 0x008)
+#define LPC_ENET_IPGR(x)			(x + 0x00C)
+#define LPC_ENET_CLRT(x)			(x + 0x010)
+#define LPC_ENET_MAXF(x)			(x + 0x014)
+#define LPC_ENET_SUPP(x)			(x + 0x018)
+#define LPC_ENET_TEST(x)			(x + 0x01C)
+#define LPC_ENET_MCFG(x)			(x + 0x020)
+#define LPC_ENET_MCMD(x)			(x + 0x024)
+#define LPC_ENET_MADR(x)			(x + 0x028)
+#define LPC_ENET_MWTD(x)			(x + 0x02C)
+#define LPC_ENET_MRDD(x)			(x + 0x030)
+#define LPC_ENET_MIND(x)			(x + 0x034)
+#define LPC_ENET_SA0(x)				(x + 0x040)
+#define LPC_ENET_SA1(x)				(x + 0x044)
+#define LPC_ENET_SA2(x)				(x + 0x048)
+#define LPC_ENET_COMMAND(x)			(x + 0x100)
+#define LPC_ENET_STATUS(x)			(x + 0x104)
+#define LPC_ENET_RXDESCRIPTOR(x)		(x + 0x108)
+#define LPC_ENET_RXSTATUS(x)			(x + 0x10C)
+#define LPC_ENET_RXDESCRIPTORNUMBER(x)		(x + 0x110)
+#define LPC_ENET_RXPRODUCEINDEX(x)		(x + 0x114)
+#define LPC_ENET_RXCONSUMEINDEX(x)		(x + 0x118)
+#define LPC_ENET_TXDESCRIPTOR(x)		(x + 0x11C)
+#define LPC_ENET_TXSTATUS(x)			(x + 0x120)
+#define LPC_ENET_TXDESCRIPTORNUMBER(x)		(x + 0x124)
+#define LPC_ENET_TXPRODUCEINDEX(x)		(x + 0x128)
+#define LPC_ENET_TXCONSUMEINDEX(x)		(x + 0x12C)
+#define LPC_ENET_TSV0(x)			(x + 0x158)
+#define LPC_ENET_TSV1(x)			(x + 0x15C)
+#define LPC_ENET_RSV(x)				(x + 0x160)
+#define LPC_ENET_FLOWCONTROLCOUNTER(x)		(x + 0x170)
+#define LPC_ENET_FLOWCONTROLSTATUS(x)		(x + 0x174)
+#define LPC_ENET_RXFILTER_CTRL(x)		(x + 0x200)
+#define LPC_ENET_RXFILTERWOLSTATUS(x)		(x + 0x204)
+#define LPC_ENET_RXFILTERWOLCLEAR(x)		(x + 0x208)
+#define LPC_ENET_HASHFILTERL(x)			(x + 0x210)
+#define LPC_ENET_HASHFILTERH(x)			(x + 0x214)
+#define LPC_ENET_INTSTATUS(x)			(x + 0xFE0)
+#define LPC_ENET_INTENABLE(x)			(x + 0xFE4)
+#define LPC_ENET_INTCLEAR(x)			(x + 0xFE8)
+#define LPC_ENET_INTSET(x)			(x + 0xFEC)
+#define LPC_ENET_POWERDOWN(x)			(x + 0xFF4)
+
+/*
+ * mac1 register definitions
+ */
+#define LPC_MAC1_RECV_ENABLE			(1 << 0)
+#define LPC_MAC1_PASS_ALL_RX_FRAMES		(1 << 1)
+#define LPC_MAC1_RX_FLOW_CONTROL		(1 << 2)
+#define LPC_MAC1_TX_FLOW_CONTROL		(1 << 3)
+#define LPC_MAC1_LOOPBACK			(1 << 4)
+#define LPC_MAC1_RESET_TX			(1 << 8)
+#define LPC_MAC1_RESET_MCS_TX			(1 << 9)
+#define LPC_MAC1_RESET_RX			(1 << 10)
+#define LPC_MAC1_RESET_MCS_RX			(1 << 11)
+#define LPC_MAC1_SIMULATION_RESET		(1 << 14)
+#define LPC_MAC1_SOFT_RESET			(1 << 15)
+
+/*
+ * mac2 register definitions
+ */
+#define LPC_MAC2_FULL_DUPLEX			(1 << 0)
+#define LPC_MAC2_FRAME_LENGTH_CHECKING		(1 << 1)
+#define LPC_MAC2_HUGH_LENGTH_CHECKING		(1 << 2)
+#define LPC_MAC2_DELAYED_CRC			(1 << 3)
+#define LPC_MAC2_CRC_ENABLE			(1 << 4)
+#define LPC_MAC2_PAD_CRC_ENABLE			(1 << 5)
+#define LPC_MAC2_VLAN_PAD_ENABLE		(1 << 6)
+#define LPC_MAC2_AUTO_DETECT_PAD_ENABLE		(1 << 7)
+#define LPC_MAC2_PURE_PREAMBLE_ENFORCEMENT	(1 << 8)
+#define LPC_MAC2_LONG_PREAMBLE_ENFORCEMENT	(1 << 9)
+#define LPC_MAC2_NO_BACKOFF			(1 << 12)
+#define LPC_MAC2_BACK_PRESSURE			(1 << 13)
+#define LPC_MAC2_EXCESS_DEFER			(1 << 14)
+
+/*
+ * ipgt register definitions
+ */
+#define LPC_IPGT_LOAD(n)			((n) & 0x7F)
+
+/*
+ * ipgr register definitions
+ */
+#define LPC_IPGR_LOAD_PART2(n)			((n) & 0x7F)
+#define LPC_IPGR_LOAD_PART1(n)			(((n) & 0x7F) << 8)
+
+/*
+ * clrt register definitions
+ */
+#define LPC_CLRT_LOAD_RETRY_MAX(n)		((n) & 0xF)
+#define LPC_CLRT_LOAD_COLLISION_WINDOW(n)	(((n) & 0x3F) << 8)
+
+/*
+ * maxf register definitions
+ */
+#define LPC_MAXF_LOAD_MAX_FRAME_LEN(n)		((n) & 0xFFFF)
+
+/*
+ * supp register definitions
+ */
+#define LPC_SUPP_SPEED				(1 << 8)
+#define LPC_SUPP_RESET_RMII			(1 << 11)
+
+/*
+ * test register definitions
+ */
+#define LPC_TEST_SHORTCUT_PAUSE_QUANTA		(1 << 0)
+#define LPC_TEST_PAUSE				(1 << 1)
+#define LPC_TEST_BACKPRESSURE			(1 << 2)
+
+/*
+ * mcfg register definitions
+ */
+#define LPC_MCFG_SCAN_INCREMENT			(1 << 0)
+#define LPC_MCFG_SUPPRESS_PREAMBLE		(1 << 1)
+#define LPC_MCFG_CLOCK_SELECT(n)		(((n) & 0x7) << 2)
+#define LPC_MCFG_CLOCK_HOST_DIV_4		0
+#define LPC_MCFG_CLOCK_HOST_DIV_6		2
+#define LPC_MCFG_CLOCK_HOST_DIV_8		3
+#define LPC_MCFG_CLOCK_HOST_DIV_10		4
+#define LPC_MCFG_CLOCK_HOST_DIV_14		5
+#define LPC_MCFG_CLOCK_HOST_DIV_20		6
+#define LPC_MCFG_CLOCK_HOST_DIV_28		7
+#define LPC_MCFG_RESET_MII_MGMT			(1 << 15)
+
+/*
+ * mcmd register definitions
+ */
+#define LPC_MCMD_READ				(1 << 0)
+#define LPC_MCMD_SCAN				(1 << 1)
+
+/*
+ * madr register definitions
+ */
+#define LPC_MADR_REGISTER_ADDRESS(n)		((n) & 0x1F)
+#define LPC_MADR_PHY_0ADDRESS(n)		(((n) & 0x1F) << 8)
+
+/*
+ * mwtd register definitions
+ */
+#define LPC_MWDT_WRITE(n)			((n) & 0xFFFF)
+
+/*
+ * mrdd register definitions
+ */
+#define LPC_MRDD_READ_MASK			0xFFFF
+
+/*
+ * mind register definitions
+ */
+#define LPC_MIND_BUSY				(1 << 0)
+#define LPC_MIND_SCANNING			(1 << 1)
+#define LPC_MIND_NOT_VALID			(1 << 2)
+#define LPC_MIND_MII_LINK_FAIL			(1 << 3)
+
+/*
+ * command register definitions
+ */
+#define LPC_COMMAND_RXENABLE			(1 << 0)
+#define LPC_COMMAND_TXENABLE			(1 << 1)
+#define LPC_COMMAND_REG_RESET			(1 << 3)
+#define LPC_COMMAND_TXRESET			(1 << 4)
+#define LPC_COMMAND_RXRESET			(1 << 5)
+#define LPC_COMMAND_PASSRUNTFRAME		(1 << 6)
+#define LPC_COMMAND_PASSRXFILTER		(1 << 7)
+#define LPC_COMMAND_TXFLOWCONTROL		(1 << 8)
+#define LPC_COMMAND_RMII			(1 << 9)
+#define LPC_COMMAND_FULLDUPLEX			(1 << 10)
+
+/*
+ * status register definitions
+ */
+#define LPC_STATUS_RXACTIVE			(1 << 0)
+#define LPC_STATUS_TXACTIVE			(1 << 1)
+
+/*
+ * tsv0 register definitions
+ */
+#define LPC_TSV0_CRC_ERROR			(1 << 0)
+#define LPC_TSV0_LENGTH_CHECK_ERROR		(1 << 1)
+#define LPC_TSV0_LENGTH_OUT_OF_RANGE		(1 << 2)
+#define LPC_TSV0_DONE				(1 << 3)
+#define LPC_TSV0_MULTICAST			(1 << 4)
+#define LPC_TSV0_BROADCAST			(1 << 5)
+#define LPC_TSV0_PACKET_DEFER			(1 << 6)
+#define LPC_TSV0_ESCESSIVE_DEFER		(1 << 7)
+#define LPC_TSV0_ESCESSIVE_COLLISION		(1 << 8)
+#define LPC_TSV0_LATE_COLLISION			(1 << 9)
+#define LPC_TSV0_GIANT				(1 << 10)
+#define LPC_TSV0_UNDERRUN			(1 << 11)
+#define LPC_TSV0_TOTAL_BYTES(n)			(((n) >> 12) & 0xFFFF)
+#define LPC_TSV0_CONTROL_FRAME			(1 << 28)
+#define LPC_TSV0_PAUSE				(1 << 29)
+#define LPC_TSV0_BACKPRESSURE			(1 << 30)
+#define LPC_TSV0_VLAN				(1 << 31)
+
+/*
+ * tsv1 register definitions
+ */
+#define LPC_TSV1_TRANSMIT_BYTE_COUNT(n)		((n) & 0xFFFF)
+#define LPC_TSV1_COLLISION_COUNT(n)		(((n) >> 16) & 0xF)
+
+/*
+ * rsv register definitions
+ */
+#define LPC_RSV_RECEIVED_BYTE_COUNT(n)		((n) & 0xFFFF)
+#define LPC_RSV_RXDV_EVENT_IGNORED		(1 << 16)
+#define LPC_RSV_RXDV_EVENT_PREVIOUSLY_SEEN	(1 << 17)
+#define LPC_RSV_CARRIER_EVNT_PREVIOUS_SEEN	(1 << 18)
+#define LPC_RSV_RECEIVE_CODE_VIOLATION		(1 << 19)
+#define LPC_RSV_CRC_ERROR			(1 << 20)
+#define LPC_RSV_LENGTH_CHECK_ERROR		(1 << 21)
+#define LPC_RSV_LENGTH_OUT_OF_RANGE		(1 << 22)
+#define LPC_RSV_RECEIVE_OK			(1 << 23)
+#define LPC_RSV_MULTICAST			(1 << 24)
+#define LPC_RSV_BROADCAST			(1 << 25)
+#define LPC_RSV_DRIBBLE_NIBBLE			(1 << 26)
+#define LPC_RSV_CONTROL_FRAME			(1 << 27)
+#define LPC_RSV_PAUSE				(1 << 28)
+#define LPC_RSV_UNSUPPORTED_OPCODE		(1 << 29)
+#define LPC_RSV_VLAN				(1 << 30)
+
+/*
+ * flowcontrolcounter register definitions
+ */
+#define LPC_FCCR_MIRRORCOUNTER(n)		((n) & 0xFFFF)
+#define LPC_FCCR_PAUSETIMER(n)			(((n) >> 16) & 0xFFFF)
+
+/*
+ * flowcontrolstatus register definitions
+ */
+#define LPC_FCCR_MIRRORCOUNTERCURRENT(n)	((n) & 0xFFFF)
+
+/*
+ * rxfliterctrl, rxfilterwolstatus, and rxfilterwolclear shared
+ * register definitions
+ */
+#define LPC_RXFLTRW_ACCEPTUNICAST		(1 << 0)
+#define LPC_RXFLTRW_ACCEPTUBROADCAST		(1 << 1)
+#define LPC_RXFLTRW_ACCEPTUMULTICAST		(1 << 2)
+#define LPC_RXFLTRW_ACCEPTUNICASTHASH		(1 << 3)
+#define LPC_RXFLTRW_ACCEPTUMULTICASTHASH	(1 << 4)
+#define LPC_RXFLTRW_ACCEPTPERFECT		(1 << 5)
+
+/*
+ * rxfliterctrl register definitions
+ */
+#define LPC_RXFLTRWSTS_MAGICPACKETENWOL		(1 << 12)
+#define LPC_RXFLTRWSTS_RXFILTERENWOL		(1 << 13)
+
+/*
+ * rxfilterwolstatus/rxfilterwolclear register definitions
+ */
+#define LPC_RXFLTRWSTS_RXFILTERWOL		(1 << 7)
+#define LPC_RXFLTRWSTS_MAGICPACKETWOL		(1 << 8)
+
+/*
+ * intstatus, intenable, intclear, and Intset shared register
+ * definitions
+ */
+#define LPC_MACINT_RXOVERRUNINTEN		(1 << 0)
+#define LPC_MACINT_RXERRORONINT			(1 << 1)
+#define LPC_MACINT_RXFINISHEDINTEN		(1 << 2)
+#define LPC_MACINT_RXDONEINTEN			(1 << 3)
+#define LPC_MACINT_TXUNDERRUNINTEN		(1 << 4)
+#define LPC_MACINT_TXERRORINTEN			(1 << 5)
+#define LPC_MACINT_TXFINISHEDINTEN		(1 << 6)
+#define LPC_MACINT_TXDONEINTEN			(1 << 7)
+#define LPC_MACINT_SOFTINTEN			(1 << 12)
+#define LPC_MACINT_WAKEUPINTEN			(1 << 13)
+
+/*
+ * powerdown register definitions
+ */
+#define LPC_POWERDOWN_MACAHB			(1 << 31)
+
+/* Upon the upcoming introduction of device tree usage in LPC32xx,
+ * lpc_phy_interface_mode() and use_iram_for_net() will be extended with a
+ * device parameter for access to device tree information at runtime, instead
+ * of defining the values at compile time
+ */
+static inline phy_interface_t lpc_phy_interface_mode(void)
+{
+#ifdef CONFIG_ARCH_LPC32XX_MII_SUPPORT
+	return PHY_INTERFACE_MODE_MII;
+#else
+	return PHY_INTERFACE_MODE_RMII;
+#endif
+}
+
+static inline int use_iram_for_net(void)
+{
+#ifdef CONFIG_ARCH_LPC32XX_IRAM_FOR_NET
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+/* Receive Status information word */
+#define RXSTATUS_SIZE			0x000007FF
+#define RXSTATUS_CONTROL		(1 << 18)
+#define RXSTATUS_VLAN			(1 << 19)
+#define RXSTATUS_FILTER			(1 << 20)
+#define RXSTATUS_MULTICAST		(1 << 21)
+#define RXSTATUS_BROADCAST		(1 << 22)
+#define RXSTATUS_CRC			(1 << 23)
+#define RXSTATUS_SYMBOL			(1 << 24)
+#define RXSTATUS_LENGTH			(1 << 25)
+#define RXSTATUS_RANGE			(1 << 26)
+#define RXSTATUS_ALIGN			(1 << 27)
+#define RXSTATUS_OVERRUN		(1 << 28)
+#define RXSTATUS_NODESC			(1 << 29)
+#define RXSTATUS_LAST			(1 << 30)
+#define RXSTATUS_ERROR			(1 << 31)
+
+#define RXSTATUS_STATUS_ERROR \
+	(RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | \
+	 RXSTATUS_RANGE | RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC)
+
+/* Receive Descriptor control word */
+#define RXDESC_CONTROL_SIZE		0x000007FF
+#define RXDESC_CONTROL_INT		(1 << 31)
+
+/* Transmit Status information word */
+#define TXSTATUS_COLLISIONS_GET(x)	(((x) >> 21) & 0xF)
+#define TXSTATUS_DEFER			(1 << 25)
+#define TXSTATUS_EXCESSDEFER		(1 << 26)
+#define TXSTATUS_EXCESSCOLL		(1 << 27)
+#define TXSTATUS_LATECOLL		(1 << 28)
+#define TXSTATUS_UNDERRUN		(1 << 29)
+#define TXSTATUS_NODESC			(1 << 30)
+#define TXSTATUS_ERROR			(1 << 31)
+
+/* Transmit Descriptor control word */
+#define TXDESC_CONTROL_SIZE		0x000007FF
+#define TXDESC_CONTROL_OVERRIDE		(1 << 26)
+#define TXDESC_CONTROL_HUGE		(1 << 27)
+#define TXDESC_CONTROL_PAD		(1 << 28)
+#define TXDESC_CONTROL_CRC		(1 << 29)
+#define TXDESC_CONTROL_LAST		(1 << 30)
+#define TXDESC_CONTROL_INT		(1 << 31)
+
+static int lpc_eth_hard_start_xmit(struct sk_buff *skb,
+				   struct net_device *ndev);
+
+/*
+ * Structure of a TX/RX descriptors and RX status
+ */
+struct txrx_desc_t {
+	__le32 packet;
+	__le32 control;
+};
+struct rx_status_t {
+	__le32 statusinfo;
+	__le32 statushashcrc;
+};
+
+/*
+ * Device driver data structure
+ */
+struct netdata_local {
+	struct platform_device	*pdev;
+	struct net_device	*ndev;
+	spinlock_t		lock;
+	void __iomem		*net_base;
+	u32			msg_enable;
+	struct sk_buff		*skb[ENET_TX_DESC];
+	unsigned int		last_tx_idx;
+	unsigned int		num_used_tx_buffs;
+	struct mii_bus		*mii_bus;
+	struct phy_device	*phy_dev;
+	struct clk		*clk;
+	dma_addr_t		dma_buff_base_p;
+	void			*dma_buff_base_v;
+	size_t			dma_buff_size;
+	struct txrx_desc_t	*tx_desc_v;
+	u32			*tx_stat_v;
+	void			*tx_buff_v;
+	struct txrx_desc_t	*rx_desc_v;
+	struct rx_status_t	*rx_stat_v;
+	void			*rx_buff_v;
+	int			link;
+	int			speed;
+	int			duplex;
+	struct napi_struct	napi;
+};
+
+/*
+ * MAC support functions
+ */
+static void __lpc_set_mac(struct netdata_local *pldat, u8 *mac)
+{
+	u32 tmp;
+
+	/* Set station address */
+	tmp = mac[0] | ((u32)mac[1] << 8);
+	writel(tmp, LPC_ENET_SA2(pldat->net_base));
+	tmp = mac[2] | ((u32)mac[3] << 8);
+	writel(tmp, LPC_ENET_SA1(pldat->net_base));
+	tmp = mac[4] | ((u32)mac[5] << 8);
+	writel(tmp, LPC_ENET_SA0(pldat->net_base));
+
+	netdev_dbg(pldat->ndev, "Ethernet MAC address %pM\n", mac);
+}
+
+static void __lpc_get_mac(struct netdata_local *pldat, u8 *mac)
+{
+	u32 tmp;
+
+	/* Get station address */
+	tmp = readl(LPC_ENET_SA2(pldat->net_base));
+	mac[0] = tmp & 0xFF;
+	mac[1] = tmp >> 8;
+	tmp = readl(LPC_ENET_SA1(pldat->net_base));
+	mac[2] = tmp & 0xFF;
+	mac[3] = tmp >> 8;
+	tmp = readl(LPC_ENET_SA0(pldat->net_base));
+	mac[4] = tmp & 0xFF;
+	mac[5] = tmp >> 8;
+}
+
+static void __lpc_eth_clock_enable(struct netdata_local *pldat,
+				   bool enable)
+{
+	if (enable)
+		clk_enable(pldat->clk);
+	else
+		clk_disable(pldat->clk);
+}
+
+static void __lpc_params_setup(struct netdata_local *pldat)
+{
+	u32 tmp;
+
+	if (pldat->duplex == DUPLEX_FULL) {
+		tmp = readl(LPC_ENET_MAC2(pldat->net_base));
+		tmp |= LPC_MAC2_FULL_DUPLEX;
+		writel(tmp, LPC_ENET_MAC2(pldat->net_base));
+		tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+		tmp |= LPC_COMMAND_FULLDUPLEX;
+		writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base));
+	} else {
+		tmp = readl(LPC_ENET_MAC2(pldat->net_base));
+		tmp &= ~LPC_MAC2_FULL_DUPLEX;
+		writel(tmp, LPC_ENET_MAC2(pldat->net_base));
+		tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+		tmp &= ~LPC_COMMAND_FULLDUPLEX;
+		writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base));
+	}
+
+	if (pldat->speed == SPEED_100)
+		writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base));
+	else
+		writel(0, LPC_ENET_SUPP(pldat->net_base));
+}
+
+static void __lpc_eth_reset(struct netdata_local *pldat)
+{
+	/* Reset all MAC logic */
+	writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX |
+		LPC_MAC1_RESET_MCS_RX | LPC_MAC1_SIMULATION_RESET |
+		LPC_MAC1_SOFT_RESET), LPC_ENET_MAC1(pldat->net_base));
+	writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET |
+		LPC_COMMAND_RXRESET), LPC_ENET_COMMAND(pldat->net_base));
+}
+
+static int __lpc_mii_mngt_reset(struct netdata_local *pldat)
+{
+	/* Reset MII management hardware */
+	writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base));
+
+	/* Setup MII clock to slowest rate with a /28 divider */
+	writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28),
+	       LPC_ENET_MCFG(pldat->net_base));
+
+	return 0;
+}
+
+static inline phys_addr_t __va_to_pa(void *addr, struct netdata_local *pldat)
+{
+	phys_addr_t phaddr;
+
+	phaddr = addr - pldat->dma_buff_base_v;
+	phaddr += pldat->dma_buff_base_p;
+
+	return phaddr;
+}
+
+static void lpc_eth_enable_int(void __iomem *regbase)
+{
+	writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN),
+	       LPC_ENET_INTENABLE(regbase));
+}
+
+static void lpc_eth_disable_int(void __iomem *regbase)
+{
+	writel(0, LPC_ENET_INTENABLE(regbase));
+}
+
+/* Setup TX/RX descriptors */
+static void __lpc_txrx_desc_setup(struct netdata_local *pldat)
+{
+	u32 *ptxstat;
+	void *tbuff;
+	int i;
+	struct txrx_desc_t *ptxrxdesc;
+	struct rx_status_t *prxstat;
+
+	tbuff = PTR_ALIGN(pldat->dma_buff_base_v, 16);
+
+	/* Setup TX descriptors, status, and buffers */
+	pldat->tx_desc_v = tbuff;
+	tbuff += sizeof(struct txrx_desc_t) * ENET_TX_DESC;
+
+	pldat->tx_stat_v = tbuff;
+	tbuff += sizeof(u32) * ENET_TX_DESC;
+
+	tbuff = PTR_ALIGN(tbuff, 16);
+	pldat->tx_buff_v = tbuff;
+	tbuff += ENET_MAXF_SIZE * ENET_TX_DESC;
+
+	/* Setup RX descriptors, status, and buffers */
+	pldat->rx_desc_v = tbuff;
+	tbuff += sizeof(struct txrx_desc_t) * ENET_RX_DESC;
+
+	tbuff = PTR_ALIGN(tbuff, 16);
+	pldat->rx_stat_v = tbuff;
+	tbuff += sizeof(struct rx_status_t) * ENET_RX_DESC;
+
+	tbuff = PTR_ALIGN(tbuff, 16);
+	pldat->rx_buff_v = tbuff;
+	tbuff += ENET_MAXF_SIZE * ENET_RX_DESC;
+
+	/* Map the TX descriptors to the TX buffers in hardware */
+	for (i = 0; i < ENET_TX_DESC; i++) {
+		ptxstat = &pldat->tx_stat_v[i];
+		ptxrxdesc = &pldat->tx_desc_v[i];
+
+		ptxrxdesc->packet = __va_to_pa(
+				pldat->tx_buff_v + i * ENET_MAXF_SIZE, pldat);
+		ptxrxdesc->control = 0;
+		*ptxstat = 0;
+	}
+
+	/* Map the RX descriptors to the RX buffers in hardware */
+	for (i = 0; i < ENET_RX_DESC; i++) {
+		prxstat = &pldat->rx_stat_v[i];
+		ptxrxdesc = &pldat->rx_desc_v[i];
+
+		ptxrxdesc->packet = __va_to_pa(
+				pldat->rx_buff_v + i * ENET_MAXF_SIZE, pldat);
+		ptxrxdesc->control = RXDESC_CONTROL_INT | (ENET_MAXF_SIZE - 1);
+		prxstat->statusinfo = 0;
+		prxstat->statushashcrc = 0;
+	}
+
+	/* Setup base addresses in hardware to point to buffers and
+	 * descriptors
+	 */
+	writel((ENET_TX_DESC - 1),
+	       LPC_ENET_TXDESCRIPTORNUMBER(pldat->net_base));
+	writel(__va_to_pa(pldat->tx_desc_v, pldat),
+	       LPC_ENET_TXDESCRIPTOR(pldat->net_base));
+	writel(__va_to_pa(pldat->tx_stat_v, pldat),
+	       LPC_ENET_TXSTATUS(pldat->net_base));
+	writel((ENET_RX_DESC - 1),
+	       LPC_ENET_RXDESCRIPTORNUMBER(pldat->net_base));
+	writel(__va_to_pa(pldat->rx_desc_v, pldat),
+	       LPC_ENET_RXDESCRIPTOR(pldat->net_base));
+	writel(__va_to_pa(pldat->rx_stat_v, pldat),
+	       LPC_ENET_RXSTATUS(pldat->net_base));
+}
+
+static void __lpc_eth_init(struct netdata_local *pldat)
+{
+	u32 tmp;
+
+	/* Disable controller and reset */
+	tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+	tmp &= ~LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
+	writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+	tmp = readl(LPC_ENET_MAC1(pldat->net_base));
+	tmp &= ~LPC_MAC1_RECV_ENABLE;
+	writel(tmp, LPC_ENET_MAC1(pldat->net_base));
+
+	/* Initial MAC setup */
+	writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base));
+	writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE),
+	       LPC_ENET_MAC2(pldat->net_base));
+	writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base));
+
+	/* Collision window, gap */
+	writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) |
+		LPC_CLRT_LOAD_COLLISION_WINDOW(0x37)),
+	       LPC_ENET_CLRT(pldat->net_base));
+	writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base));
+
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		writel(LPC_COMMAND_PASSRUNTFRAME,
+		       LPC_ENET_COMMAND(pldat->net_base));
+	else {
+		writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
+		       LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
+	}
+
+	__lpc_params_setup(pldat);
+
+	/* Setup TX and RX descriptors */
+	__lpc_txrx_desc_setup(pldat);
+
+	/* Setup packet filtering */
+	writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT),
+	       LPC_ENET_RXFILTER_CTRL(pldat->net_base));
+
+	/* Get the next TX buffer output index */
+	pldat->num_used_tx_buffs = 0;
+	pldat->last_tx_idx =
+		readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+
+	/* Clear and enable interrupts */
+	writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
+	smp_wmb();
+	lpc_eth_enable_int(pldat->net_base);
+
+	/* Enable controller */
+	tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+	tmp |= LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
+	writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+	tmp = readl(LPC_ENET_MAC1(pldat->net_base));
+	tmp |= LPC_MAC1_RECV_ENABLE;
+	writel(tmp, LPC_ENET_MAC1(pldat->net_base));
+}
+
+static void __lpc_eth_shutdown(struct netdata_local *pldat)
+{
+	/* Reset ethernet and power down PHY */
+	__lpc_eth_reset(pldat);
+	writel(0, LPC_ENET_MAC1(pldat->net_base));
+	writel(0, LPC_ENET_MAC2(pldat->net_base));
+}
+
+/*
+ * MAC<--->PHY support functions
+ */
+static int lpc_mdio_read(struct mii_bus *bus, int phy_id, int phyreg)
+{
+	struct netdata_local *pldat = bus->priv;
+	unsigned long timeout = jiffies + msecs_to_jiffies(100);
+	int lps;
+
+	writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
+	writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base));
+
+	/* Wait for unbusy status */
+	while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
+		if (time_after(jiffies, timeout))
+			return -EIO;
+		cpu_relax();
+	}
+
+	lps = readl(LPC_ENET_MRDD(pldat->net_base));
+	writel(0, LPC_ENET_MCMD(pldat->net_base));
+
+	return lps;
+}
+
+static int lpc_mdio_write(struct mii_bus *bus, int phy_id, int phyreg,
+			u16 phydata)
+{
+	struct netdata_local *pldat = bus->priv;
+	unsigned long timeout = jiffies + msecs_to_jiffies(100);
+
+	writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
+	writel(phydata, LPC_ENET_MWTD(pldat->net_base));
+
+	/* Wait for completion */
+	while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
+		if (time_after(jiffies, timeout))
+			return -EIO;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int lpc_mdio_reset(struct mii_bus *bus)
+{
+	return __lpc_mii_mngt_reset((struct netdata_local *)bus->priv);
+}
+
+static void lpc_handle_link_change(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+	unsigned long flags;
+
+	bool status_change = false;
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	if (phydev->link) {
+		if ((pldat->speed != phydev->speed) ||
+		    (pldat->duplex != phydev->duplex)) {
+			pldat->speed = phydev->speed;
+			pldat->duplex = phydev->duplex;
+			status_change = true;
+		}
+	}
+
+	if (phydev->link != pldat->link) {
+		if (!phydev->link) {
+			pldat->speed = 0;
+			pldat->duplex = -1;
+		}
+		pldat->link = phydev->link;
+
+		status_change = true;
+	}
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	if (status_change)
+		__lpc_params_setup(pldat);
+}
+
+static int lpc_mii_probe(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = NULL;
+	int phy_addr;
+
+	/* find the first phy */
+	for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
+		if (pldat->mii_bus->phy_map[phy_addr]) {
+			phydev = pldat->mii_bus->phy_map[phy_addr];
+			break;
+		}
+	}
+
+	if (!phydev) {
+		netdev_err(ndev, "no PHY found\n");
+		return -ENODEV;
+	}
+
+	/* Attach to the PHY */
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		netdev_info(ndev, "using MII interface\n");
+	else
+		netdev_info(ndev, "using RMII interface\n");
+	phydev = phy_connect(ndev, dev_name(&phydev->dev),
+		&lpc_handle_link_change, 0, lpc_phy_interface_mode());
+
+	if (IS_ERR(phydev)) {
+		netdev_err(ndev, "Could not attach to PHY\n");
+		return PTR_ERR(phydev);
+	}
+
+	/* mask with MAC supported features */
+	phydev->supported &= PHY_BASIC_FEATURES;
+
+	phydev->advertising = phydev->supported;
+
+	pldat->link = 0;
+	pldat->speed = 0;
+	pldat->duplex = -1;
+	pldat->phy_dev = phydev;
+
+	return 0;
+}
+
+static int lpc_mii_init(struct netdata_local *pldat)
+{
+	int err = -ENXIO, i;
+
+	pldat->mii_bus = mdiobus_alloc();
+	if (!pldat->mii_bus) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	/* Setup MII mode */
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		writel(LPC_COMMAND_PASSRUNTFRAME,
+		       LPC_ENET_COMMAND(pldat->net_base));
+	else {
+		writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
+		       LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
+	}
+
+	pldat->mii_bus->name = "lpc_mii_bus";
+	pldat->mii_bus->read = &lpc_mdio_read;
+	pldat->mii_bus->write = &lpc_mdio_write;
+	pldat->mii_bus->reset = &lpc_mdio_reset;
+	snprintf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%x", pldat->pdev->id);
+	pldat->mii_bus->priv = pldat;
+	pldat->mii_bus->parent = &pldat->pdev->dev;
+	pldat->mii_bus->phy_mask = 0xFFFFFFF0;
+
+	pldat->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!pldat->mii_bus->irq) {
+		err = -ENOMEM;
+		goto err_out_1;
+	}
+
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		pldat->mii_bus->irq[i] = PHY_POLL;
+
+	platform_set_drvdata(pldat->pdev, pldat->mii_bus);
+
+	if (mdiobus_register(pldat->mii_bus))
+		goto err_out_free_mdio_irq;
+
+	if (lpc_mii_probe(pldat->ndev) != 0)
+		goto err_out_unregister_bus;
+
+	return 0;
+
+err_out_unregister_bus:
+	mdiobus_unregister(pldat->mii_bus);
+err_out_free_mdio_irq:
+	kfree(pldat->mii_bus->irq);
+err_out_1:
+	mdiobus_free(pldat->mii_bus);
+err_out:
+	return err;
+}
+
+static void __lpc_handle_xmit(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct sk_buff *skb;
+	u32 txcidx, *ptxstat, txstat;
+
+	txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+	while (pldat->last_tx_idx != txcidx) {
+		skb = pldat->skb[pldat->last_tx_idx];
+
+		/* A buffer is available, get buffer status */
+		ptxstat = &pldat->tx_stat_v[pldat->last_tx_idx];
+		txstat = *ptxstat;
+
+		/* Next buffer and decrement used buffer counter */
+		pldat->num_used_tx_buffs--;
+		pldat->last_tx_idx++;
+		if (pldat->last_tx_idx >= ENET_TX_DESC)
+			pldat->last_tx_idx = 0;
+
+		/* Update collision counter */
+		ndev->stats.collisions += TXSTATUS_COLLISIONS_GET(txstat);
+
+		/* Any errors occurred? */
+		if (txstat & TXSTATUS_ERROR) {
+			if (txstat & TXSTATUS_UNDERRUN) {
+				/* FIFO underrun */
+				ndev->stats.tx_fifo_errors++;
+			}
+			if (txstat & TXSTATUS_LATECOLL) {
+				/* Late collision */
+				ndev->stats.tx_aborted_errors++;
+			}
+			if (txstat & TXSTATUS_EXCESSCOLL) {
+				/* Excessive collision */
+				ndev->stats.tx_aborted_errors++;
+			}
+			if (txstat & TXSTATUS_EXCESSDEFER) {
+				/* Defer limit */
+				ndev->stats.tx_aborted_errors++;
+			}
+			ndev->stats.tx_errors++;
+		} else {
+			/* Update stats */
+			ndev->stats.tx_packets++;
+			ndev->stats.tx_bytes += skb->len;
+
+			/* Free buffer */
+			dev_kfree_skb_irq(skb);
+		}
+
+		txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+	}
+
+	if (netif_queue_stopped(ndev))
+		netif_wake_queue(ndev);
+}
+
+static int __lpc_handle_recv(struct net_device *ndev, int budget)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct sk_buff *skb;
+	u32 rxconsidx, len, ethst;
+	struct rx_status_t *prxstat;
+	u8 *prdbuf;
+	int rx_done = 0;
+
+	/* Get the current RX buffer indexes */
+	rxconsidx = readl(LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
+	while (rx_done < budget && rxconsidx !=
+			readl(LPC_ENET_RXPRODUCEINDEX(pldat->net_base))) {
+		/* Get pointer to receive status */
+		prxstat = &pldat->rx_stat_v[rxconsidx];
+		len = (prxstat->statusinfo & RXSTATUS_SIZE) + 1;
+
+		/* Status error? */
+		ethst = prxstat->statusinfo;
+		if ((ethst & (RXSTATUS_ERROR | RXSTATUS_STATUS_ERROR)) ==
+		    (RXSTATUS_ERROR | RXSTATUS_RANGE))
+			ethst &= ~RXSTATUS_ERROR;
+
+		if (ethst & RXSTATUS_ERROR) {
+			int si = prxstat->statusinfo;
+			/* Check statuses */
+			if (si & RXSTATUS_OVERRUN) {
+				/* Overrun error */
+				ndev->stats.rx_fifo_errors++;
+			} else if (si & RXSTATUS_CRC) {
+				/* CRC error */
+				ndev->stats.rx_crc_errors++;
+			} else if (si & RXSTATUS_LENGTH) {
+				/* Length error */
+				ndev->stats.rx_length_errors++;
+			} else if (si & RXSTATUS_ERROR) {
+				/* Other error */
+				ndev->stats.rx_length_errors++;
+			}
+			ndev->stats.rx_errors++;
+		} else {
+			/* Packet is good */
+			skb = dev_alloc_skb(len + 8);
+			if (!skb)
+				ndev->stats.rx_dropped++;
+			else {
+				prdbuf = skb_put(skb, len);
+
+				/* Copy packet from buffer */
+				memcpy(prdbuf, pldat->rx_buff_v +
+					rxconsidx * ENET_MAXF_SIZE, len);
+
+				/* Pass to upper layer */
+				skb->protocol = eth_type_trans(skb, ndev);
+				netif_receive_skb(skb);
+				ndev->stats.rx_packets++;
+				ndev->stats.rx_bytes += len;
+			}
+		}
+
+		/* Increment consume index */
+		rxconsidx = rxconsidx + 1;
+		if (rxconsidx >= ENET_RX_DESC)
+			rxconsidx = 0;
+		writel(rxconsidx,
+		       LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
+		rx_done++;
+	}
+
+	return rx_done;
+}
+
+static int lpc_eth_poll(struct napi_struct *napi, int budget)
+{
+	struct netdata_local *pldat = container_of(napi,
+			struct netdata_local, napi);
+	struct net_device *ndev = pldat->ndev;
+	int rx_done = 0;
+	struct netdev_queue *txq = netdev_get_tx_queue(ndev, 0);
+
+	__netif_tx_lock(txq, smp_processor_id());
+	__lpc_handle_xmit(ndev);
+	__netif_tx_unlock(txq);
+	rx_done = __lpc_handle_recv(ndev, budget);
+
+	if (rx_done < budget) {
+		napi_complete(napi);
+		lpc_eth_enable_int(pldat->net_base);
+	}
+
+	return rx_done;
+}
+
+static irqreturn_t __lpc_eth_interrupt(int irq, void *dev_id)
+{
+	struct net_device *ndev = dev_id;
+	struct netdata_local *pldat = netdev_priv(ndev);
+	u32 tmp;
+
+	spin_lock(&pldat->lock);
+
+	tmp = readl(LPC_ENET_INTSTATUS(pldat->net_base));
+	/* Clear interrupts */
+	writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base));
+
+	lpc_eth_disable_int(pldat->net_base);
+	if (likely(napi_schedule_prep(&pldat->napi)))
+		__napi_schedule(&pldat->napi);
+
+	spin_unlock(&pldat->lock);
+
+	return IRQ_HANDLED;
+}
+
+static int lpc_eth_close(struct net_device *ndev)
+{
+	unsigned long flags;
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	if (netif_msg_ifdown(pldat))
+		dev_dbg(&pldat->pdev->dev, "shutting down %s\n", ndev->name);
+
+	napi_disable(&pldat->napi);
+	netif_stop_queue(ndev);
+
+	if (pldat->phy_dev)
+		phy_stop(pldat->phy_dev);
+
+	spin_lock_irqsave(&pldat->lock, flags);
+	__lpc_eth_reset(pldat);
+	netif_carrier_off(ndev);
+	writel(0, LPC_ENET_MAC1(pldat->net_base));
+	writel(0, LPC_ENET_MAC2(pldat->net_base));
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	__lpc_eth_clock_enable(pldat, false);
+
+	return 0;
+}
+
+static int lpc_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	u32 len, txidx;
+	u32 *ptxstat;
+	struct txrx_desc_t *ptxrxdesc;
+
+	len = skb->len;
+
+	spin_lock_irq(&pldat->lock);
+
+	if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) {
+		/* This function should never be called when there are no
+		   buffers */
+		netif_stop_queue(ndev);
+		spin_unlock_irq(&pldat->lock);
+		WARN(1, "BUG! TX request when no free TX buffers!\n");
+		return NETDEV_TX_BUSY;
+	}
+
+	/* Get the next TX descriptor index */
+	txidx = readl(LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
+
+	/* Setup control for the transfer */
+	ptxstat = &pldat->tx_stat_v[txidx];
+	*ptxstat = 0;
+	ptxrxdesc = &pldat->tx_desc_v[txidx];
+	ptxrxdesc->control =
+		(len - 1) | TXDESC_CONTROL_LAST | TXDESC_CONTROL_INT;
+
+	/* Copy data to the DMA buffer */
+	memcpy(pldat->tx_buff_v + txidx * ENET_MAXF_SIZE, skb->data, len);
+
+	/* Save the buffer and increment the buffer counter */
+	pldat->skb[txidx] = skb;
+	pldat->num_used_tx_buffs++;
+
+	/* Start transmit */
+	txidx++;
+	if (txidx >= ENET_TX_DESC)
+		txidx = 0;
+	writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
+
+	/* Stop queue if no more TX buffers */
+	if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1))
+		netif_stop_queue(ndev);
+
+	spin_unlock_irq(&pldat->lock);
+
+	return NETDEV_TX_OK;
+}
+
+static int lpc_set_mac_address(struct net_device *ndev, void *p)
+{
+	struct sockaddr *addr = p;
+	struct netdata_local *pldat = netdev_priv(ndev);
+	unsigned long flags;
+
+	if (!is_valid_ether_addr(addr->sa_data))
+		return -EADDRNOTAVAIL;
+	memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	/* Set station address */
+	__lpc_set_mac(pldat, ndev->dev_addr);
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	return 0;
+}
+
+static void lpc_eth_set_multicast_list(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct netdev_hw_addr_list *mcptr = &ndev->mc;
+	struct netdev_hw_addr *ha;
+	u32 tmp32, hash_val, hashlo, hashhi;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	/* Set station address */
+	__lpc_set_mac(pldat, ndev->dev_addr);
+
+	tmp32 =  LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT;
+
+	if (ndev->flags & IFF_PROMISC)
+		tmp32 |= LPC_RXFLTRW_ACCEPTUNICAST |
+			LPC_RXFLTRW_ACCEPTUMULTICAST;
+	if (ndev->flags & IFF_ALLMULTI)
+		tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICAST;
+
+	if (netdev_hw_addr_list_count(mcptr))
+		tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICASTHASH;
+
+	writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base));
+
+
+	/* Set initial hash table */
+	hashlo = 0x0;
+	hashhi = 0x0;
+
+	/* 64 bits : multicast address in hash table */
+	netdev_hw_addr_list_for_each(ha, mcptr) {
+		hash_val = (ether_crc(6, ha->addr) >> 23) & 0x3F;
+
+		if (hash_val >= 32)
+			hashhi |= 1 << (hash_val - 32);
+		else
+			hashlo |= 1 << hash_val;
+	}
+
+	writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base));
+	writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base));
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+}
+
+static int lpc_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!netif_running(ndev))
+		return -EINVAL;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_mii_ioctl(phydev, req, cmd);
+}
+
+static int lpc_eth_open(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	/* if the phy is not yet registered, retry later*/
+	if (!pldat->phy_dev)
+		return -EAGAIN;
+
+	if (netif_msg_ifup(pldat))
+		dev_dbg(&pldat->pdev->dev, "enabling %s\n", ndev->name);
+
+	if (!is_valid_ether_addr(ndev->dev_addr))
+		return -EADDRNOTAVAIL;
+
+	__lpc_eth_clock_enable(pldat, true);
+
+	/* Reset and initialize */
+	__lpc_eth_reset(pldat);
+	__lpc_eth_init(pldat);
+
+	/* schedule a link state check */
+	phy_start(pldat->phy_dev);
+	netif_start_queue(ndev);
+	napi_enable(&pldat->napi);
+
+	return 0;
+}
+
+/*
+ * Ethtool ops
+ */
+static void lpc_eth_ethtool_getdrvinfo(struct net_device *ndev,
+	struct ethtool_drvinfo *info)
+{
+	strcpy(info->driver, MODNAME);
+	strcpy(info->version, DRV_VERSION);
+	strcpy(info->bus_info, dev_name(ndev->dev.parent));
+}
+
+static u32 lpc_eth_ethtool_getmsglevel(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	return pldat->msg_enable;
+}
+
+static void lpc_eth_ethtool_setmsglevel(struct net_device *ndev, u32 level)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	pldat->msg_enable = level;
+}
+
+static int lpc_eth_ethtool_getsettings(struct net_device *ndev,
+	struct ethtool_cmd *cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!phydev)
+		return -EOPNOTSUPP;
+
+	return phy_ethtool_gset(phydev, cmd);
+}
+
+static int lpc_eth_ethtool_setsettings(struct net_device *ndev,
+	struct ethtool_cmd *cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!phydev)
+		return -EOPNOTSUPP;
+
+	return phy_ethtool_sset(phydev, cmd);
+}
+
+static const struct ethtool_ops lpc_eth_ethtool_ops = {
+	.get_drvinfo	= lpc_eth_ethtool_getdrvinfo,
+	.get_settings	= lpc_eth_ethtool_getsettings,
+	.set_settings	= lpc_eth_ethtool_setsettings,
+	.get_msglevel	= lpc_eth_ethtool_getmsglevel,
+	.set_msglevel	= lpc_eth_ethtool_setmsglevel,
+	.get_link	= ethtool_op_get_link,
+};
+
+static const struct net_device_ops lpc_netdev_ops = {
+	.ndo_open		= lpc_eth_open,
+	.ndo_stop		= lpc_eth_close,
+	.ndo_start_xmit		= lpc_eth_hard_start_xmit,
+	.ndo_set_rx_mode	= lpc_eth_set_multicast_list,
+	.ndo_do_ioctl		= lpc_eth_ioctl,
+	.ndo_set_mac_address	= lpc_set_mac_address,
+};
+
+static int lpc_eth_drv_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct resource *dma_res;
+	struct net_device *ndev;
+	struct netdata_local *pldat;
+	struct phy_device *phydev;
+	dma_addr_t dma_handle;
+	int irq, ret;
+
+	/* Get platform resources */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	irq = platform_get_irq(pdev, 0);
+	if ((!res) || (!dma_res) || (irq < 0) || (irq >= NR_IRQS)) {
+		dev_err(&pdev->dev, "error getting resources.\n");
+		ret = -ENXIO;
+		goto err_exit;
+	}
+
+	/* Allocate net driver data structure */
+	ndev = alloc_etherdev(sizeof(struct netdata_local));
+	if (!ndev) {
+		dev_err(&pdev->dev, "could not allocate device.\n");
+		ret = -ENOMEM;
+		goto err_exit;
+	}
+
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	pldat = netdev_priv(ndev);
+	pldat->pdev = pdev;
+	pldat->ndev = ndev;
+
+	spin_lock_init(&pldat->lock);
+
+	/* Save resources */
+	ndev->irq = irq;
+
+	/* Get clock for the device */
+	pldat->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(pldat->clk)) {
+		dev_err(&pdev->dev, "error getting clock.\n");
+		ret = PTR_ERR(pldat->clk);
+		goto err_out_free_dev;
+	}
+
+	/* Enable network clock */
+	__lpc_eth_clock_enable(pldat, true);
+
+	/* Map IO space */
+	pldat->net_base = ioremap(res->start, res->end - res->start + 1);
+	if (!pldat->net_base) {
+		dev_err(&pdev->dev, "failed to map registers\n");
+		ret = -ENOMEM;
+		goto err_out_disable_clocks;
+	}
+	ret = request_irq(ndev->irq, __lpc_eth_interrupt, 0,
+			  ndev->name, ndev);
+	if (ret) {
+		dev_err(&pdev->dev, "error requesting interrupt.\n");
+		goto err_out_iounmap;
+	}
+
+	/* Fill in the fields of the device structure with ethernet values. */
+	ether_setup(ndev);
+
+	/* Setup driver functions */
+	ndev->netdev_ops = &lpc_netdev_ops;
+	ndev->ethtool_ops = &lpc_eth_ethtool_ops;
+	ndev->watchdog_timeo = msecs_to_jiffies(2500);
+
+	/* Get size of DMA buffers/descriptors region */
+	pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE +
+		sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
+	pldat->dma_buff_base_v = 0;
+
+	if (use_iram_for_net()) {
+		dma_handle = dma_res->start;
+		if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
+			pldat->dma_buff_base_v =
+				io_p2v(dma_res->start);
+		else
+			netdev_err(ndev,
+				"IRAM not big enough for net buffers, using SDRAM instead.\n");
+	}
+
+	if (pldat->dma_buff_base_v == 0) {
+		pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size);
+
+		/* Allocate a chunk of memory for the DMA ethernet buffers
+		   and descriptors */
+		pldat->dma_buff_base_v =
+			dma_alloc_coherent(&pldat->pdev->dev,
+					   pldat->dma_buff_size, &dma_handle,
+					   GFP_KERNEL);
+
+		if (pldat->dma_buff_base_v == NULL) {
+			dev_err(&pdev->dev, "error getting DMA region.\n");
+			ret = -ENOMEM;
+			goto err_out_free_irq;
+		}
+	}
+	pldat->dma_buff_base_p = dma_handle;
+
+	netdev_dbg(ndev, "IO address start     :0x%08x\n",
+			res->start);
+	netdev_dbg(ndev, "IO address size      :%d\n",
+			res->end - res->start + 1);
+	netdev_err(ndev, "IO address (mapped)  :0x%p\n",
+			pldat->net_base);
+	netdev_dbg(ndev, "IRQ number           :%d\n", ndev->irq);
+	netdev_dbg(ndev, "DMA buffer size      :%d\n", pldat->dma_buff_size);
+	netdev_dbg(ndev, "DMA buffer P address :0x%08x\n",
+			pldat->dma_buff_base_p);
+	netdev_dbg(ndev, "DMA buffer V address :0x%p\n",
+			pldat->dma_buff_base_v);
+
+	/* Get MAC address from current HW setting (POR state is all zeros) */
+	__lpc_get_mac(pldat, ndev->dev_addr);
+
+#ifdef CONFIG_OF_NET
+	if (!is_valid_ether_addr(ndev->dev_addr)) {
+		const char *macaddr = of_get_mac_address(pdev->dev.of_node);
+		if (macaddr)
+			memcpy(ndev->dev_addr, macaddr, ETH_ALEN);
+	}
+#endif
+	if (!is_valid_ether_addr(ndev->dev_addr))
+		dev_hw_addr_random(ndev, ndev->dev_addr);
+
+	/* Reset the ethernet controller */
+	__lpc_eth_reset(pldat);
+
+	/* then shut everything down to save power */
+	__lpc_eth_shutdown(pldat);
+
+	/* Set default parameters */
+	pldat->msg_enable = NETIF_MSG_LINK;
+
+	/* Force an MII interface reset and clock setup */
+	__lpc_mii_mngt_reset(pldat);
+
+	/* Force default PHY interface setup in chip, this will probably be
+	   changed by the PHY driver */
+	pldat->link = 0;
+	pldat->speed = 100;
+	pldat->duplex = DUPLEX_FULL;
+	__lpc_params_setup(pldat);
+
+	netif_napi_add(ndev, &pldat->napi, lpc_eth_poll, NAPI_WEIGHT);
+
+	ret = register_netdev(ndev);
+	if (ret) {
+		dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
+		goto err_out_dma_unmap;
+	}
+	platform_set_drvdata(pdev, ndev);
+
+	if (lpc_mii_init(pldat) != 0)
+		goto err_out_unregister_netdev;
+
+	netdev_info(ndev, "LPC mac at 0x%08x irq %d\n",
+	       res->start, ndev->irq);
+
+	phydev = pldat->phy_dev;
+	netdev_info(ndev,
+		"attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
+		phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
+
+	device_init_wakeup(&pdev->dev, 1);
+	device_set_wakeup_enable(&pdev->dev, 0);
+
+	return 0;
+
+err_out_unregister_netdev:
+	platform_set_drvdata(pdev, NULL);
+	unregister_netdev(ndev);
+err_out_dma_unmap:
+	if (!use_iram_for_net() ||
+	    pldat->dma_buff_size > lpc32xx_return_iram_size())
+		dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
+				  pldat->dma_buff_base_v,
+				  pldat->dma_buff_base_p);
+err_out_free_irq:
+	free_irq(ndev->irq, ndev);
+err_out_iounmap:
+	iounmap(pldat->net_base);
+err_out_disable_clocks:
+	clk_disable(pldat->clk);
+	clk_put(pldat->clk);
+err_out_free_dev:
+	free_netdev(ndev);
+err_exit:
+	pr_err("%s: not found (%d).\n", MODNAME, ret);
+	return ret;
+}
+
+static int lpc_eth_drv_remove(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	unregister_netdev(ndev);
+	platform_set_drvdata(pdev, NULL);
+
+	if (!use_iram_for_net() ||
+	    pldat->dma_buff_size > lpc32xx_return_iram_size())
+		dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
+				  pldat->dma_buff_base_v,
+				  pldat->dma_buff_base_p);
+	free_irq(ndev->irq, ndev);
+	iounmap(pldat->net_base);
+	clk_disable(pldat->clk);
+	clk_put(pldat->clk);
+	free_netdev(ndev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int lpc_eth_drv_suspend(struct platform_device *pdev,
+	pm_message_t state)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	if (device_may_wakeup(&pdev->dev))
+		enable_irq_wake(ndev->irq);
+
+	if (ndev) {
+		if (netif_running(ndev)) {
+			netif_device_detach(ndev);
+			__lpc_eth_shutdown(pldat);
+			clk_disable(pldat->clk);
+
+			/*
+			 * Reset again now clock is disable to be sure
+			 * EMC_MDC is down
+			 */
+			__lpc_eth_reset(pldat);
+		}
+	}
+
+	return 0;
+}
+
+static int lpc_eth_drv_resume(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat;
+
+	if (device_may_wakeup(&pdev->dev))
+		disable_irq_wake(ndev->irq);
+
+	if (ndev) {
+		if (netif_running(ndev)) {
+			pldat = netdev_priv(ndev);
+
+			/* Enable interface clock */
+			clk_enable(pldat->clk);
+
+			/* Reset and initialize */
+			__lpc_eth_reset(pldat);
+			__lpc_eth_init(pldat);
+
+			netif_device_attach(ndev);
+		}
+	}
+
+	return 0;
+}
+#endif
+
+static struct platform_driver lpc_eth_driver = {
+	.probe		= lpc_eth_drv_probe,
+	.remove		= __devexit_p(lpc_eth_drv_remove),
+#ifdef CONFIG_PM
+	.suspend	= lpc_eth_drv_suspend,
+	.resume		= lpc_eth_drv_resume,
+#endif
+	.driver		= {
+		.name	= MODNAME,
+	},
+};
+
+module_platform_driver(lpc_eth_driver);
+
+MODULE_AUTHOR("Kevin Wells <kevin.wells at nxp.com>");
+MODULE_AUTHOR("Roland Stigge <stigge at antcom.de>");
+MODULE_DESCRIPTION("LPC Ethernet Driver");
+MODULE_LICENSE("GPL");


From stigge at antcom.de  Wed Mar  7 15:25:29 2012
From: stigge at antcom.de (Roland Stigge)
Date: Wed,  7 Mar 2012 21:25:29 +0100
Subject: [PATCH] ARM: LPX32xx: DMA support
Message-ID: <1331151929-23298-1-git-send-email-stigge@antcom.de>

This patch adds DMA support to the LPC32xx platform

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

 Applies to v3.3-rc6.  This patch is a precondition for the NAND and audio
 drivers (to be sent in one of my next mails).

 arch/arm/mach-lpc32xx/Makefile            |    2 
 arch/arm/mach-lpc32xx/dma.c               |  742 ++++++++++++++++++++++++++++++
 arch/arm/mach-lpc32xx/include/mach/dma.h  |  131 +++++
 arch/arm/mach-lpc32xx/include/mach/dmac.h |  285 +++++++++++
 4 files changed, 1159 insertions(+), 1 deletion(-)

--- linux-2.6.orig/arch/arm/mach-lpc32xx/Makefile
+++ linux-2.6/arch/arm/mach-lpc32xx/Makefile
@@ -3,6 +3,6 @@
 #
 
 obj-y	:= timer.o irq.o common.o serial.o clock.o
-obj-y	+= pm.o suspend.o
+obj-y	+= dma.o pm.o suspend.o
 obj-y	+= phy3250.o
 
--- /dev/null
+++ linux-2.6/arch/arm/mach-lpc32xx/dma.c
@@ -0,0 +1,742 @@
+/*
+ *  linux/arch/arm/mach-lpc32xx/dma.c
+ *
+ *  Copyright (C) 2008 NXP Semiconductors
+ *  (Based on parts of the PNX4008 DMA driver)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+
+#include <asm/system.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include <asm/dma-mapping.h>
+#include <asm/io.h>
+#include <mach/dma.h>
+#include <mach/dmac.h>
+
+#define DMAIOBASE io_p2v(LPC32XX_DMA_BASE)
+#define VALID_CHANNEL(c) (((c) >= 0) && ((c) < MAX_DMA_CHANNELS))
+
+static DEFINE_SPINLOCK(dma_lock);
+
+/* Each DMA channel has one of these structures */
+struct dma_channel {
+	char *name;
+	void (*irq_handler) (int, int, void *);
+	void *data;
+	struct dma_config *dmacfg;
+	u32 control;
+	u32 config;
+	u32 config_int_mask;
+
+	int list_entries; /* Number of list entries */
+	size_t list_size; /* Total size of allocated list in bytes */
+	struct dma_list_ctrl *list_vstart;
+	dma_addr_t list_pstart;
+	int free_entries; /* Number of free descriptors */
+	struct dma_list_ctrl *list_head, *list_tail, *list_curr;
+};
+
+struct dma_control {
+	struct clk *clk;
+	int num_clks;
+	struct dma_channel dma_channels[MAX_DMA_CHANNELS];
+};
+static struct dma_control dma_ctrl;
+
+static inline void __dma_regs_lock(void)
+{
+	spin_lock_irq(&dma_lock);
+}
+
+static inline void __dma_regs_unlock(void)
+{
+	spin_unlock_irq(&dma_lock);
+}
+
+static inline void __dma_enable(int ch)
+{
+	u32 ch_cfg = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
+	ch_cfg |= DMAC_CHAN_ENABLE;
+	__raw_writel(ch_cfg, DMACH_CONFIG_CH(DMAIOBASE, ch));
+}
+
+static inline void __dma_disable(int ch)
+{
+	u32 ch_cfg = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
+	ch_cfg &= ~DMAC_CHAN_ENABLE;
+	__raw_writel(ch_cfg, DMACH_CONFIG_CH(DMAIOBASE, ch));
+}
+
+static void dma_clocks_up(void)
+{
+	/* Enable DMA clock if needed */
+	if (dma_ctrl.num_clks == 0) {
+		clk_enable(dma_ctrl.clk);
+		__raw_writel(DMAC_CTRL_ENABLE, DMA_CONFIG(DMAIOBASE));
+	}
+
+	dma_ctrl.num_clks++;
+}
+
+static void dma_clocks_down(void)
+{
+	dma_ctrl.num_clks--;
+
+	/* Disable DMA clock if needed */
+	if (dma_ctrl.num_clks == 0) {
+		__raw_writel(0, DMA_CONFIG(DMAIOBASE));
+		clk_disable(dma_ctrl.clk);
+	}
+}
+
+static int lpc32xx_ch_setup(struct dma_config *dmachcfg)
+{
+	u32 tmpctrl, tmpcfg, tmp;
+	int ch = dmachcfg->ch;
+
+	/* Channel control setup */
+	tmpctrl = 0;
+	switch (dmachcfg->src_size) {
+	case 1:
+		tmpctrl |= DMAC_CHAN_SRC_WIDTH_8;
+		break;
+
+	case 2:
+		tmpctrl |= DMAC_CHAN_SRC_WIDTH_16;
+		break;
+
+	case 4:
+		tmpctrl |= DMAC_CHAN_SRC_WIDTH_32;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+	switch (dmachcfg->dst_size) {
+	case 1:
+		tmpctrl |= DMAC_CHAN_DEST_WIDTH_8;
+		break;
+
+	case 2:
+		tmpctrl |= DMAC_CHAN_DEST_WIDTH_16;
+		break;
+
+	case 4:
+		tmpctrl |= DMAC_CHAN_DEST_WIDTH_32;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+	if (dmachcfg->src_inc != 0)
+		tmpctrl |= DMAC_CHAN_SRC_AUTOINC;
+	if (dmachcfg->dst_inc != 0)
+		tmpctrl |= DMAC_CHAN_DEST_AUTOINC;
+	if (dmachcfg->src_ahb1 != 0)
+		tmpctrl |= DMAC_CHAN_SRC_AHB1;
+	if (dmachcfg->dst_ahb1 != 0)
+		tmpctrl |= DMAC_CHAN_DEST_AHB1;
+	if (dmachcfg->tc_inten != 0)
+		tmpctrl |= DMAC_CHAN_INT_TC_EN;
+	tmpctrl |= dmachcfg->src_bsize | dmachcfg->dst_bsize;
+	dma_ctrl.dma_channels[ch].control = tmpctrl;
+
+	/* Channel config setup */
+	tmpcfg = dmachcfg->src_prph | dmachcfg->dst_prph |
+		dmachcfg->flowctrl;
+	dma_ctrl.dma_channels[ch].config = tmpcfg;
+
+	dma_ctrl.dma_channels[ch].config_int_mask = 0;
+	if (dmachcfg->err_inten != 0)
+		dma_ctrl.dma_channels[ch].config_int_mask |=
+			DMAC_CHAN_IE;
+	if (dmachcfg->tc_inten != 0)
+		dma_ctrl.dma_channels[ch].config_int_mask |=
+			DMAC_CHAN_ITC;
+
+	tmp = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
+	tmp &= ~DMAC_CHAN_ENABLE;
+	__raw_writel(tmp, DMACH_CONFIG_CH(DMAIOBASE, ch));
+
+	/* Clear interrupts for channel */
+	__raw_writel((1 << ch), DMA_INT_TC_CLEAR(DMAIOBASE));
+	__raw_writel((1 << ch), DMA_INT_ERR_CLEAR(DMAIOBASE));
+
+	/* Write control and config words */
+	__raw_writel(tmpctrl, DMACH_CONTROL(DMAIOBASE, ch));
+	__raw_writel(tmpcfg, DMACH_CONFIG_CH(DMAIOBASE, ch));
+
+	return 0;
+}
+
+int lpc32xx_dma_ch_enable(int ch)
+{
+	if (!VALID_CHANNEL(ch) || !dma_ctrl.dma_channels[ch].name)
+		return -EINVAL;
+
+	__dma_regs_lock();
+	__dma_enable(ch);
+	__dma_regs_unlock();
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_ch_enable);
+
+int lpc32xx_dma_ch_disable(int ch)
+{
+	if (!VALID_CHANNEL(ch) || !dma_ctrl.dma_channels[ch].name)
+		return -EINVAL;
+
+	__dma_regs_lock();
+	__dma_disable(ch);
+	__dma_regs_unlock();
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_ch_disable);
+
+int lpc32xx_dma_ch_get(struct dma_config *dmachcfg, char *name,
+		       void *irq_handler, void *data)
+{
+	int ret;
+
+	if (!VALID_CHANNEL(dmachcfg->ch))
+		return -EINVAL;
+
+	/* If the channel is already enabled, return */
+	if (dma_ctrl.dma_channels[dmachcfg->ch].name != NULL)
+		return -ENODEV;
+
+	/* Save channel data */
+	dma_ctrl.dma_channels[dmachcfg->ch].dmacfg = dmachcfg;
+	dma_ctrl.dma_channels[dmachcfg->ch].name = name;
+	dma_ctrl.dma_channels[dmachcfg->ch].irq_handler = irq_handler;
+	dma_ctrl.dma_channels[dmachcfg->ch].data = data;
+
+	/* Setup channel */
+	__dma_regs_lock();
+	dma_clocks_up();
+	ret = lpc32xx_ch_setup(dmachcfg);
+	__dma_regs_unlock();
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_ch_get);
+
+int lpc32xx_dma_ch_put(int ch)
+{
+	u32 tmp;
+
+	if (!VALID_CHANNEL(ch))
+		return -EINVAL;
+
+	/* If the channel is already disabled, return */
+	if (dma_ctrl.dma_channels[ch].name == NULL)
+		return -EINVAL;
+
+	tmp = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
+	tmp &= ~DMAC_CHAN_ENABLE;
+	__raw_writel(tmp, DMACH_CONFIG_CH(DMAIOBASE, ch));
+
+	__dma_regs_lock();
+	lpc32xx_dma_ch_disable(ch);
+	dma_clocks_down();
+	__dma_regs_unlock();
+
+	dma_ctrl.dma_channels[ch].name = NULL;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_ch_put);
+
+int lpc32xx_dma_ch_pause_unpause(int ch, int pause)
+{
+	u32 tmp;
+
+	if (!VALID_CHANNEL(ch))
+		return -EINVAL;
+
+	/* If the channel is already disabled, return */
+	if (dma_ctrl.dma_channels[ch].name == NULL)
+		return -EINVAL;
+
+	tmp = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
+	if (pause)
+		tmp |= DMAC_CHAN_HALT;
+	else
+		tmp &= ~DMAC_CHAN_HALT;
+	__raw_writel(tmp, DMACH_CONFIG_CH(DMAIOBASE, ch));
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_ch_pause_unpause);
+
+int lpc32xx_dma_start_pflow_xfer(int ch,
+				dma_addr_t src,
+				dma_addr_t dst,
+				int enable)
+{
+	u32 tmp;
+
+	if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL))
+		return -EINVAL;
+
+	/* When starting a DMA transfer where the peripheral is the flow
+	   controller, DMA must be previously disabled */
+	tmp = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
+	if (tmp & DMAC_CHAN_ENABLE)
+		return -EBUSY;
+
+	__dma_regs_lock();
+	__raw_writel(src, DMACH_SRC_ADDR(DMAIOBASE, ch));
+	__raw_writel(dst, DMACH_DEST_ADDR(DMAIOBASE, ch));
+	__raw_writel(0, DMACH_LLI(DMAIOBASE, ch));
+	__raw_writel(dma_ctrl.dma_channels[ch].control,
+			DMACH_CONTROL(DMAIOBASE, ch));
+
+	tmp = dma_ctrl.dma_channels[ch].config |
+		dma_ctrl.dma_channels[ch].config_int_mask;
+	if (enable != 0)
+		tmp |= DMAC_CHAN_ENABLE;
+	__raw_writel(tmp, DMACH_CONFIG_CH(DMAIOBASE, ch));
+
+	__dma_regs_unlock();
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_start_pflow_xfer);
+
+int lpc32xx_dma_is_active(int ch)
+{
+	int active = 0;
+
+	if ((VALID_CHANNEL(ch)) && (dma_ctrl.dma_channels[ch].name != NULL)) {
+		if (__raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch)) &
+		    DMAC_CHAN_ENABLE)
+			active = 1;
+	}
+
+	return active;
+
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_is_active);
+
+extern dma_addr_t lpc32xx_dma_llist_v_to_p(int ch, struct dma_list_ctrl *vlist)
+{
+	dma_addr_t pptr;
+
+	if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
+	    (dma_ctrl.dma_channels[ch].list_vstart == NULL))
+		return 0;
+
+	pptr = dma_ctrl.dma_channels[ch].list_pstart;
+	pptr += (vlist - dma_ctrl.dma_channels[ch].list_vstart) *
+		sizeof(struct dma_list_ctrl) ;
+
+	return pptr;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_llist_v_to_p);
+
+struct dma_list_ctrl *lpc32xx_dma_llist_p_to_v(int ch, dma_addr_t plist)
+{
+	struct dma_list_ctrl *vptr;
+
+	if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
+		(dma_ctrl.dma_channels[ch].list_vstart == NULL))
+		return NULL;
+
+	vptr = dma_ctrl.dma_channels[ch].list_vstart;
+	vptr += plist - dma_ctrl.dma_channels[ch].list_pstart;
+
+	return vptr;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_llist_p_to_v);
+
+struct dma_list_ctrl *lpc32xx_dma_alloc_llist(int ch, int entries)
+{
+	int i;
+	dma_addr_t dma_handle;
+	struct dma_list_ctrl *pdmalist, *pdmalistst;
+
+	if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL))
+		return NULL;
+
+	/*
+	 * Limit number of list entries, but add 1 extra entry as a spot holder
+	 * for the end of the list
+	 */
+	if (entries < 2)
+		entries = 2;
+	if (entries > 64)
+		entries = 64;
+	entries++;
+
+	/* Save list information */
+	dma_ctrl.dma_channels[ch].list_entries = entries;
+	dma_ctrl.dma_channels[ch].list_size =
+		(entries * sizeof(struct dma_list_ctrl));
+	dma_ctrl.dma_channels[ch].list_vstart = dma_alloc_coherent(NULL,
+		dma_ctrl.dma_channels[ch].list_size, &dma_handle, GFP_KERNEL);
+	if (dma_ctrl.dma_channels[ch].list_vstart == NULL) {
+		/* No allocated DMA space */
+		return NULL;
+	}
+	dma_ctrl.dma_channels[ch].list_pstart = dma_handle;
+
+	/* Setup list tail and head pointers */
+	pdmalist = pdmalistst =
+		(struct dma_list_ctrl *)dma_ctrl.dma_channels[ch].list_vstart;
+	for (i = 0; i < entries; i++) {
+		pdmalistst->next_list_addr = pdmalistst + 1;
+		pdmalistst->prev_list_addr = pdmalistst - 1;
+		pdmalistst->next_list_phy =
+			lpc32xx_dma_llist_v_to_p(ch,
+						 pdmalistst->next_list_addr);
+		pdmalistst->prev_list_phy =
+			lpc32xx_dma_llist_v_to_p(ch,
+						 pdmalistst->prev_list_addr);
+		pdmalistst++;
+	}
+	pdmalist[entries - 1].next_list_addr = pdmalist;
+	pdmalist[entries - 1].next_list_phy =
+		lpc32xx_dma_llist_v_to_p(ch,
+					 pdmalist[entries - 1].next_list_addr);
+	pdmalist->prev_list_addr = &pdmalist[entries - 1];
+	pdmalist->prev_list_phy =
+		lpc32xx_dma_llist_v_to_p(ch, pdmalist->prev_list_addr);
+
+	/* Save current free descriptors and current head/tail */
+	dma_ctrl.dma_channels[ch].free_entries = entries - 1;
+	dma_ctrl.dma_channels[ch].list_head = pdmalist;
+	dma_ctrl.dma_channels[ch].list_tail = pdmalist;
+	dma_ctrl.dma_channels[ch].list_curr = pdmalist;
+
+	return dma_ctrl.dma_channels[ch].list_vstart;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_alloc_llist);
+
+void lpc32xx_dma_dealloc_llist(int ch)
+{
+	if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
+	    (dma_ctrl.dma_channels[ch].list_vstart == 0))
+		return;
+
+	dma_free_coherent(NULL, dma_ctrl.dma_channels[ch].list_size,
+			  dma_ctrl.dma_channels[ch].list_vstart,
+			  dma_ctrl.dma_channels[ch].list_pstart);
+	dma_ctrl.dma_channels[ch].list_head = NULL;
+	dma_ctrl.dma_channels[ch].list_tail = NULL;
+	dma_ctrl.dma_channels[ch].list_entries = 0;
+	dma_ctrl.dma_channels[ch].free_entries = 0;
+	dma_ctrl.dma_channels[ch].list_vstart = NULL;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_dealloc_llist);
+
+struct dma_list_ctrl *lpc32xx_dma_get_llist_head(int ch)
+{
+	if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
+	    (dma_ctrl.dma_channels[ch].list_vstart == NULL))
+		return NULL;
+
+	/* Return the current list pointer (virtual) for the
+	   DMA channel */
+	return lpc32xx_dma_llist_p_to_v(ch,
+					__raw_readl(DMACH_LLI(DMAIOBASE, ch)));
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_get_llist_head);
+
+void lpc32xx_dma_flush_llist(int ch)
+{
+	if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
+	    (dma_ctrl.dma_channels[ch].list_vstart == NULL))
+		return;
+
+	/* Disable channel and clear LLI */
+	__dma_regs_lock();
+	__dma_disable(ch);
+	__raw_writel(0, DMACH_LLI(DMAIOBASE, ch));
+	__dma_regs_unlock();
+
+	dma_ctrl.dma_channels[ch].list_head =
+		dma_ctrl.dma_channels[ch].list_vstart;
+	dma_ctrl.dma_channels[ch].list_tail =
+		dma_ctrl.dma_channels[ch].list_vstart;
+	dma_ctrl.dma_channels[ch].list_curr =
+		dma_ctrl.dma_channels[ch].list_vstart;
+	dma_ctrl.dma_channels[ch].free_entries =
+		dma_ctrl.dma_channels[ch].list_entries - 1;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_flush_llist);
+
+struct dma_list_ctrl *lpc32xx_dma_queue_llist_entry(int ch, dma_addr_t src,
+						    dma_addr_t dst, int size)
+{
+	struct dma_list_ctrl *plhead;
+	u32 ctrl, cfg;
+
+	if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
+	    (dma_ctrl.dma_channels[ch].list_vstart == NULL))
+		return NULL;
+
+	/* Exit if all the buffers are used */
+	if (dma_ctrl.dma_channels[ch].free_entries == 0)
+		return NULL;
+
+	/* Next available DMA link descriptor */
+	plhead = dma_ctrl.dma_channels[ch].list_head;
+
+	/* Adjust size to number of transfers (vs bytes) */
+	size = size / dma_ctrl.dma_channels[ch].dmacfg->dst_size;
+
+	/* Setup control and config words */
+	ctrl = dma_ctrl.dma_channels[ch].control | size;
+	cfg = dma_ctrl.dma_channels[ch].config | DMAC_CHAN_ENABLE |
+		dma_ctrl.dma_channels[ch].config_int_mask;
+
+	/* Populate DMA linked data structure */
+	plhead->dmall.src = src;
+	plhead->dmall.dest = dst;
+	plhead->dmall.next_lli = 0;
+	plhead->dmall.ctrl = ctrl;
+
+	__dma_regs_lock();
+
+	/* Append this link to the end of the previous link */
+	plhead->prev_list_addr->dmall.next_lli =
+		lpc32xx_dma_llist_v_to_p(ch, plhead);
+
+	/* Decrement available buffers */
+	dma_ctrl.dma_channels[ch].free_entries--;
+
+	/* If the DMA channel is idle, then the buffer needs to be placed
+	   directly into the DMA registers */
+	if ((__raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch)) & DMAC_CHAN_ENABLE)
+	    == 0) {
+		/* DMA is disabled, so move the current buffer into the
+		   channel registers and start transfer */
+		__raw_writel(src, DMACH_SRC_ADDR(DMAIOBASE, ch));
+		__raw_writel(dst, DMACH_DEST_ADDR(DMAIOBASE, ch));
+		__raw_writel(0, DMACH_LLI(DMAIOBASE, ch));
+		__raw_writel(ctrl, DMACH_CONTROL(DMAIOBASE, ch));
+		__raw_writel(cfg, DMACH_CONFIG_CH(DMAIOBASE, ch));
+	} else if (__raw_readl(DMACH_LLI(DMAIOBASE, ch)) == 0) {
+		/* Update current entry to next entry */
+		__raw_writel(dma_ctrl.dma_channels[ch].list_tail->next_list_phy,
+			     DMACH_LLI(DMAIOBASE, ch));
+
+		/*
+		 * If the channel was stopped before the next entry made it
+		 * into the hardware descriptor, the next entry didn't make
+		 * it there fast enough, so load the new descriptor here.
+		 */
+		if ((__raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch)) &
+		     DMAC_CHAN_ENABLE) == 0)	{
+			__raw_writel(src, DMACH_SRC_ADDR(DMAIOBASE, ch));
+			__raw_writel(dst, DMACH_DEST_ADDR(DMAIOBASE, ch));
+			__raw_writel(0, DMACH_LLI(DMAIOBASE, ch));
+			__raw_writel(ctrl, DMACH_CONTROL(DMAIOBASE, ch));
+			__raw_writel(cfg, DMACH_CONFIG_CH(DMAIOBASE, ch));
+		}
+	}
+
+	/* Process next link on next call */
+	dma_ctrl.dma_channels[ch].list_head = plhead->next_list_addr;
+
+	__dma_regs_unlock();
+
+	return plhead;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_queue_llist_entry);
+
+struct dma_list_ctrl *lpc32xx_get_free_llist_entry(int ch)
+{
+	struct dma_list_ctrl *pltail;
+
+	if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
+	    (dma_ctrl.dma_channels[ch].list_vstart == NULL))
+		return NULL;
+
+	/* Exit if no entries to free */
+	if (dma_ctrl.dma_channels[ch].free_entries ==
+	    dma_ctrl.dma_channels[ch].list_entries)
+		return NULL;
+
+	/* Get tail pointer */
+	pltail = dma_ctrl.dma_channels[ch].list_tail;
+
+	/* Next tail */
+	dma_ctrl.dma_channels[ch].list_tail = pltail->next_list_addr;
+
+	/* Increment available buffers */
+	dma_ctrl.dma_channels[ch].free_entries++;
+
+	return pltail;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_get_free_llist_entry);
+
+int lpc32xx_dma_start_xfer(int ch, u32 config)
+{
+	struct dma_list_ctrl *plhead;
+
+	if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
+	    (dma_ctrl.dma_channels[ch].list_vstart == NULL))
+		return -1;
+
+	plhead = dma_ctrl.dma_channels[ch].list_head;
+	__dma_regs_lock();
+	__raw_writel(plhead->dmall.src, DMACH_SRC_ADDR(DMAIOBASE, ch));
+	__raw_writel(plhead->dmall.dest, DMACH_DEST_ADDR(DMAIOBASE, ch));
+	__raw_writel(plhead->dmall.next_lli, DMACH_LLI(DMAIOBASE, ch));
+	__raw_writel(plhead->dmall.ctrl, DMACH_CONTROL(DMAIOBASE, ch));
+	__raw_writel(config, DMACH_CONFIG_CH(DMAIOBASE, ch));
+	__dma_regs_unlock();
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_start_xfer);
+
+struct dma_list_ctrl *lpc32xx_dma_queue_llist(int ch, dma_addr_t src,
+						     dma_addr_t dst, int size,
+						     u32 ctrl)
+{
+	struct dma_list_ctrl *plhead;
+
+	if ((!VALID_CHANNEL(ch)) || (dma_ctrl.dma_channels[ch].name == NULL) ||
+	    (dma_ctrl.dma_channels[ch].list_vstart == NULL))
+		return NULL;
+
+	/* Exit if all the buffers are used */
+	if (dma_ctrl.dma_channels[ch].free_entries == 0)
+		return NULL;
+
+	/* Next available DMA link descriptor */
+	plhead = dma_ctrl.dma_channels[ch].list_curr;
+
+	/* Populate DMA linked data structure */
+	plhead->dmall.src = src;
+	plhead->dmall.dest = dst;
+	plhead->dmall.next_lli = 0;
+	plhead->dmall.ctrl = ctrl;
+
+	/* Append this link to the end of the previous link */
+	plhead->prev_list_addr->dmall.next_lli =
+		lpc32xx_dma_llist_v_to_p(ch, plhead);
+
+	/* Decrement available buffers */
+	dma_ctrl.dma_channels[ch].free_entries--;
+
+	/* Process next link on next call */
+	dma_ctrl.dma_channels[ch].list_curr = plhead->next_list_addr;
+
+	return plhead;
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_queue_llist);
+
+extern void lpc32xx_dma_force_burst(int ch, int src)
+{
+	__raw_writel(1 << src, DMA_SW_BURST_REQ(DMAIOBASE));
+}
+EXPORT_SYMBOL_GPL(lpc32xx_dma_force_burst);
+
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+	int i;
+	unsigned long dint = __raw_readl(DMA_INT_STAT(DMAIOBASE));
+	unsigned long tcint = __raw_readl(DMA_INT_TC_STAT(DMAIOBASE));
+	unsigned long eint = __raw_readl(DMA_INT_ERR_STAT(DMAIOBASE));
+	unsigned long i_bit;
+
+	for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
+		i_bit = 1 << i;
+		if (dint & i_bit) {
+			struct dma_channel *channel = &dma_ctrl.dma_channels[i];
+
+			if (channel->name && channel->irq_handler) {
+				int cause = 0;
+
+				if (eint & i_bit) {
+					__raw_writel(i_bit,
+						DMA_INT_ERR_CLEAR(DMAIOBASE));
+					cause |= DMA_ERR_INT;
+				}
+				if (tcint & i_bit) {
+					__raw_writel(i_bit,
+						DMA_INT_TC_CLEAR(DMAIOBASE));
+					cause |= DMA_TC_INT;
+				}
+
+				channel->irq_handler(i, cause, channel->data);
+			} else {
+				/*
+				 * IRQ for an unregistered DMA channel
+				 */
+				__raw_writel(i_bit,
+					     DMA_INT_ERR_CLEAR(DMAIOBASE));
+				__raw_writel(i_bit,
+					     DMA_INT_TC_CLEAR(DMAIOBASE));
+				printk(KERN_WARNING
+				       "spurious IRQ for DMA channel %d\n", i);
+			}
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int __init lpc32xx_dma_init(void)
+{
+	int ret;
+
+	ret = request_irq(IRQ_LPC32XX_DMA, dma_irq_handler, 0, "DMA", NULL);
+	if (ret) {
+		printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
+		goto out;
+	}
+
+	/* Get DMA clock */
+	dma_ctrl.clk = clk_get(NULL, "clk_dmac");
+	if (IS_ERR(dma_ctrl.clk)) {
+		ret = -ENODEV;
+		goto errout;
+	}
+	clk_enable(dma_ctrl.clk);
+
+	/* Clear DMA controller */
+	__raw_writel(1, DMA_CONFIG(DMAIOBASE));
+	__raw_writel(0xFF, DMA_INT_TC_CLEAR(DMAIOBASE));
+	__raw_writel(0xFF, DMA_INT_ERR_CLEAR(DMAIOBASE));
+
+	/* Clock is only enabled when needed to save power */
+	clk_disable(dma_ctrl.clk);
+
+	return 0;
+
+errout:
+	free_irq(IRQ_LPC32XX_DMA, NULL);
+
+out:
+	return ret;
+}
+arch_initcall(lpc32xx_dma_init);
--- /dev/null
+++ linux-2.6/arch/arm/mach-lpc32xx/include/mach/dma.h
@@ -0,0 +1,131 @@
+/*
+ * asm-arm/arch-lpc32xx/dma.h
+ *
+ * Author: Kevin Wells <kevin.wells at nxp.com>
+ *
+ * Copyright (C) 2008 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#include <mach/platform.h>
+
+#define MAX_DMA_CHANNELS 8
+
+#define DMA_CH_SDCARD_TX	0
+#define DMA_CH_SDCARD_RX	1
+#define DMA_CH_I2S_TX		2
+#define DMA_CH_I2S_RX		3
+#define DMA_CH_NAND		4
+
+enum {
+	DMA_INT_UNKNOWN = 0,
+	DMA_ERR_INT = 1,
+	DMA_TC_INT = 2,
+};
+
+struct dma_linked_list {
+	__le32 src;
+	__le32 dest;
+	__le32 next_lli;
+	__le32 ctrl;
+};
+
+/* For DMA linked list operation, a linked list of DMA descriptors
+   is maintained along with some data to manage the list in software. */
+struct dma_list_ctrl {
+	struct dma_linked_list dmall; /* DMA list descriptor */
+	struct dma_list_ctrl *next_list_addr;
+	struct dma_list_ctrl *prev_list_addr;
+	dma_addr_t next_list_phy;
+	dma_addr_t prev_list_phy;
+};
+
+/*
+ * DMA channel control structure
+ */
+struct dma_config {
+	int ch;		/* Channel # to use */
+	int tc_inten;	/* !0 = Enable TC interrupts for this channel */
+	int err_inten;	/* !0 = Enable error interrupts for this channel */
+	int src_size;	/* Source xfer size - must be 1, 2, or 4 */
+	int src_inc;	/* !0 = Enable source address increment */
+	int src_ahb1;	/* !0 = Use AHB1 for source transfer */
+	int src_bsize;	/* Source burst size (ie, DMAC_CHAN_SRC_BURST_xxx) */
+	u32 src_prph;	/* Source peripheral (ie, DMA_PERID_xxxx) */
+	int dst_size;	/* Destination xfer size - must be 1, 2, or 4 */
+	int dst_inc;	/* !0 = Enable destination address increment */
+	int dst_ahb1;	/* !0 = Use AHB1 for destination transfer */
+	int dst_bsize;	/* Destination burst size */
+			/* (ie, DMAC_CHAN_DEST_BURST_xxx) */
+	u32 dst_prph;	/* Destination peripheral (ie, DMA_PERID_xxxx) */
+	u32 flowctrl;	/* Flow control (ie, DMAC_CHAN_FLOW_xxxxxx) */
+};
+
+/*
+ * Channel enable and disable functions
+ */
+extern int lpc32xx_dma_ch_enable(int ch);
+extern int lpc32xx_dma_ch_disable(int ch);
+
+/*
+ * Channel allocation and deallocation functions
+ */
+extern int lpc32xx_dma_ch_get(struct dma_config *dmachcfg,
+				char *name,
+				void *irq_handler,
+				void *data);
+extern int lpc32xx_dma_ch_put(int ch);
+extern int lpc32xx_dma_ch_pause_unpause(int ch, int pause);
+
+/*
+ * Setup or start an unbound DMA transfer
+ */
+extern int lpc32xx_dma_start_pflow_xfer(int ch,
+					dma_addr_t src,
+					dma_addr_t dst,
+					int enable);
+
+/*
+ * DMA channel status
+ */
+extern int lpc32xx_dma_is_active(int ch);
+
+/*
+ * DMA linked list support
+ */
+extern struct dma_list_ctrl *lpc32xx_dma_alloc_llist(int ch, int entries);
+extern void lpc32xx_dma_dealloc_llist(int ch);
+extern dma_addr_t lpc32xx_dma_llist_v_to_p(int ch, struct dma_list_ctrl *vlist);
+extern struct dma_list_ctrl *lpc32xx_dma_llist_p_to_v(int ch, dma_addr_t plist);
+extern struct dma_list_ctrl *lpc32xx_dma_get_llist_head(int ch);
+extern void lpc32xx_dma_flush_llist(int ch);
+extern struct dma_list_ctrl *lpc32xx_dma_queue_llist_entry(int ch,
+							   dma_addr_t src,
+							   dma_addr_t dst,
+							   int size);
+extern struct dma_list_ctrl *lpc32xx_get_free_llist_entry(int ch);
+extern struct dma_list_ctrl *lpc32xx_dma_queue_llist(int ch,
+						     dma_addr_t src,
+						     dma_addr_t dst,
+						     int size,
+						     u32 ctrl);
+extern int lpc32xx_dma_start_xfer(int chan, u32 config);
+extern void lpc32xx_dma_force_burst(int ch, int src);
+
+#endif /* _ASM_ARCH_DMA_H */
--- /dev/null
+++ linux-2.6/arch/arm/mach-lpc32xx/include/mach/dmac.h
@@ -0,0 +1,285 @@
+/*
+ * asm-arm/arch-lpc32xx/dmac.h
+ *
+ * Author: Kevin Wells <kevin.wells at nxp.com>
+ *
+ * Copyright (C) 2008 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_DMAC_H
+#define __ASM_ARCH_DMAC_H
+
+/**********************************************************************
+* DMA register offsets
+**********************************************************************/
+
+/* DMA controller register structures */
+#define DMA_INT_STAT(x)			(x + 0x00)
+#define DMA_INT_TC_STAT(x)		(x + 0x04)
+#define DMA_INT_TC_CLEAR(x)		(x + 0x08)
+#define DMA_INT_ERR_STAT(x)		(x + 0x0C)
+#define DMA_INT_ERR_CLEAR(x)		(x + 0x10)
+#define DMA_RAW_TC_STAT(x)		(x + 0x14)
+#define DMA_RAW_ERR_STAT(x)		(x + 0x18)
+#define DMA_CH_ENABLE(x)		(x + 0x1C)
+#define DMA_SW_BURST_REQ(x)		(x + 0x20)
+#define DMA_SW_SINGLE_REQ(x)		(x + 0x24)
+#define DMA_SW_LAST_BURST_REQ(x)	(x + 0x28)
+#define DMA_SW_LAST_SINGLE_REQ(x)	(x + 0x2C)
+#define DMA_CONFIG(x)			(x + 0x30)
+#define DMA_SYNC(x)			(x + 0x34)
+
+/* DMA controller channel register structure */
+#define DMA_CH_OFFS(c)			((c * 0x20) + 0x100)
+#define DMACH_SRC_ADDR(x, c)		(x + DMA_CH_OFFS(c) + 0x00)
+#define DMACH_DEST_ADDR(x, c)		(x + DMA_CH_OFFS(c) + 0x04)
+#define DMACH_LLI(x, c)			(x + DMA_CH_OFFS(c) + 0x08)
+#define DMACH_CONTROL(x, c)		(x + DMA_CH_OFFS(c) + 0x0C)
+#define DMACH_CONFIG_CH(x, c)		(x + DMA_CH_OFFS(c) + 0x10)
+
+/* DMA linked list structure */
+#define DMA_LL_SRC(x)			(x + 0x0)
+#define DMA_LL_DEST(x)			(x + 0x4)
+#define DMA_LL_NEXT_LLI(x)		(x + 0x8)
+#define DMA_LL_NEXT_CTRL(x)		(x + 0xC)
+
+#define DMA_LL_SIZE 16
+
+/**********************************************************************
+* int_stat, int_tc_stat, int_tc_clear, int_err_stat, raw_tc_stat,
+* raw_err_stat, and chan_enable register definitions
+**********************************************************************/
+/* Macro for determining a bit position for a channel */
+#define DMAC_GET_CHAN_POS(chan)     (0x1 << ((chan) & 0x7))
+
+/**********************************************************************
+* sw_burst_req, sw_single_req, sw_last_burst_req, sw_last_single_req,
+* and sync register definitions
+**********************************************************************/
+/* Peripheral DMA bit position for I2S0 DMA0 */
+#define DMA_PER_I2S0_DMA0           _BIT(0)
+
+/* Peripheral DMA bit position for NAND FLASH (same as 12) */
+#define DMA_PER_NAND1               _BIT(1)
+
+/* Peripheral DMA bit position for I2S1 DMA0 */
+#define DMA_PER_I2S1_DMA0           _BIT(2)
+
+/* Peripheral DMA bit position for SPI2 (RX and TX) */
+#define DMA_PER_SPI2_TXRX           _BIT(3)
+
+/* Peripheral DMA bit position for SSP1 (RX) */
+#define DMA_PER_SSP1_RX             _BIT(3)
+
+/* Peripheral DMA bit position for SD card */
+#define DMA_PER_SDCARD              _BIT(4)
+
+/* Peripheral DMA bit position for HSUART1 TX */
+#define DMA_PER_HSUART1_TX          _BIT(5)
+
+/* Peripheral DMA bit position for HSUART1 RX */
+#define DMA_PER_HSUART1_RX          _BIT(6)
+
+/* Peripheral DMA bit position for HSUART2 TX */
+#define DMA_PER_HSUART2_TX          _BIT(7)
+
+/* Peripheral DMA bit position for HSUART2 RX */
+#define DMA_PER_HSUART2_RX          _BIT(8)
+
+/* Peripheral DMA bit position for HSUART7 TX */
+#define DMA_PER_HSUART7_TX          _BIT(9)
+
+/* Peripheral DMA bit position for HSUART7 RX */
+#define DMA_PER_HSUART7_RX          _BIT(10)
+
+/* Peripheral DMA bit position for I2S1 DMA1 */
+#define DMA_PER_I2S1_DMA1           _BIT(10)
+
+/* Peripheral DMA bit position for SPI1 (RX and TX) */
+#define DMA_PER_SPI1_TXRX           _BIT(11)
+
+/* Peripheral DMA bit position for SSP1 (TX) */
+#define DMA_PER_SSP1_TX             _BIT(11)
+
+/* Peripheral DMA bit position for NAND FLASH (same as 1) */
+#define DMA_PER_NAND2               _BIT(12)
+
+/* Peripheral DMA bit position for I2S0 DMA1 */
+#define DMA_PER_I2S0_DMA1           _BIT(13)
+
+/* Peripheral DMA bit position for SSP0 (RX) */
+#define DMA_PER_SSP0_RX             _BIT(14)
+
+/* Peripheral DMA bit position for SSP0 (TX) */
+#define DMA_PER_SSP0_TX             _BIT(15)
+
+/**********************************************************************
+* config register definitions
+**********************************************************************/
+/* Bit for enabling big endian mode on AHB 1 */
+#define DMAC_BIG_ENDIAN_AHB1        _BIT(2)
+
+/* Bit for enabling big endian mode on AHB 0 */
+#define DMAC_BIG_ENDIAN_AHB0        _BIT(1)
+
+/* Bit for enabling the DMA controller */
+#define DMAC_CTRL_ENABLE            _BIT(0)
+
+/**********************************************************************
+* lli register definitions
+**********************************************************************/
+/* Bit for selecting AHB0 (0) or AHB1 (1) */
+#define DMAC_CHAN_LLI_SEL_AHB1      _BIT(0)
+
+/**********************************************************************
+* control register definitions
+**********************************************************************/
+/* Bit for enabling a channel terminal count interrupt */
+#define DMAC_CHAN_INT_TC_EN         _BIT(31)
+
+/* Bit for indicating address is cacheable */
+#define DMAC_CHAN_PROT3             _BIT(30)
+
+/* Bit for indicating address is bufferable */
+#define DMAC_CHAN_PROT2             _BIT(29)
+
+/* Bit for indicating address is privelaged mode (1) or user
+   mode (0) */
+#define DMAC_CHAN_PROT1             _BIT(28)
+
+/* Bit for enabling automatic destination increment */
+#define DMAC_CHAN_DEST_AUTOINC      _BIT(27)
+
+/* Bit for enabling automatic source increment */
+#define DMAC_CHAN_SRC_AUTOINC       _BIT(26)
+
+/* Bit for using AHB1 master for destination transfer */
+#define DMAC_CHAN_DEST_AHB1         _BIT(25)
+
+/* Bit for using AHB1 master for source transfer */
+#define DMAC_CHAN_SRC_AHB1          _BIT(24)
+
+/* Destination data width selection defines */
+#define DMAC_CHAN_DEST_WIDTH_8      0x0
+#define DMAC_CHAN_DEST_WIDTH_16     _BIT(21)
+#define DMAC_CHAN_DEST_WIDTH_32     _BIT(22)
+
+/* Source data width selection defines */
+#define DMAC_CHAN_SRC_WIDTH_8       0x0
+#define DMAC_CHAN_SRC_WIDTH_16      _BIT(18)
+#define DMAC_CHAN_SRC_WIDTH_32      _BIT(19)
+
+/* Destination data burst size defines (in transfer width) */
+#define DMAC_CHAN_DEST_BURST_1      0
+#define DMAC_CHAN_DEST_BURST_4      _BIT(15)
+#define DMAC_CHAN_DEST_BURST_8      _BIT(16)
+#define DMAC_CHAN_DEST_BURST_16     (_BIT(16) | _BIT(15))
+#define DMAC_CHAN_DEST_BURST_32     _BIT(17)
+#define DMAC_CHAN_DEST_BURST_64     (_BIT(17) | _BIT(15))
+#define DMAC_CHAN_DEST_BURST_128    (_BIT(17) | _BIT(16))
+#define DMAC_CHAN_DEST_BURST_256    (_BIT(17) | _BIT(16) | _BIT(15))
+
+/* Macro for direct loading of destination burst size field */
+#define DMAC_CHAN_DEST_BURST_LOAD(n) (((n) & 0x7) << 15)
+
+/* Source data burst size defines (in transfer width) */
+#define DMAC_CHAN_SRC_BURST_1       0
+#define DMAC_CHAN_SRC_BURST_4       _BIT(12)
+#define DMAC_CHAN_SRC_BURST_8       _BIT(13)
+#define DMAC_CHAN_SRC_BURST_16      (_BIT(13) | _BIT(12))
+#define DMAC_CHAN_SRC_BURST_32      _BIT(14)
+#define DMAC_CHAN_SRC_BURST_64      (_BIT(14) | _BIT(12))
+#define DMAC_CHAN_SRC_BURST_128     (_BIT(14) | _BIT(13))
+#define DMAC_CHAN_SRC_BURST_256     (_BIT(14) | _BIT(13) | _BIT(12))
+
+/* Macro for direct loading of source burst size field */
+#define DMAC_CHAN_SRC_BURST_LOAD(n) (((n) & 0x7) << 12)
+
+/* Macro for loading transfer size */
+#define DMAC_CHAN_TRANSFER_SIZE(n)  ((n) & 0xFFF)
+
+/**********************************************************************
+* config_ch register definitions
+**********************************************************************/
+/* Bit for halting a DMA transfer */
+#define DMAC_CHAN_HALT              _BIT(18)
+
+/* Bit for checking active status of the DMA channel */
+#define DMAC_CHAN_ACTIVE            _BIT(17)
+
+/* Bit for enabling locked transfers */
+#define DMAC_CHAN_LOCK              _BIT(16)
+
+/* Terminal count interrupt mask bit */
+#define DMAC_CHAN_ITC               _BIT(15)
+
+/* Interrupt error mask bit */
+#define DMAC_CHAN_IE                _BIT(14)
+
+/* Defines for flow control with DMA as the controller */
+#define DMAC_CHAN_FLOW_D_M2M        (0x0 << 11)
+#define DMAC_CHAN_FLOW_D_M2P        (0x1 << 11)
+#define DMAC_CHAN_FLOW_D_P2M        (0x2 << 11)
+#define DMAC_CHAN_FLOW_D_SP2DP      (0x3 << 11)
+
+/* Defines for flow control with destination peripheral as the
+   controller */
+#define DMAC_CHAN_FLOW_DP_SP2DP     (0x4 << 11)
+
+/* Defines for flow control with peripheral as the controller */
+#define DMAC_CHAN_FLOW_P_M2P        (0x5 << 11)
+#define DMAC_CHAN_FLOW_P_P2M        (0x6 << 11)
+
+/* Defines for flow control with source peripheral as the
+   controller */
+#define DMAC_CHAN_FLOW_SP_SP2DP     (0x7 << 11)
+
+/* Macro for loading destination peripheral */
+#define DMAC_DEST_PERIP(n)          (((n) & 0x1F) << 6)
+
+/* Macro for loading source peripheral */
+#define DMAC_SRC_PERIP(n)           (((n) & 0x1F) << 1)
+
+/* Channel enable bit */
+#define DMAC_CHAN_ENABLE            _BIT(0)
+
+/**********************************************************************
+* config_ch register definitions (source and destination
+* peripheral ID numbers). These can be used with the DMAC_DEST_PERIP
+* and DMAC_SRC_PERIP macros.
+**********************************************************************/
+#define DMA_PERID_I2S0_DMA0         0
+#define DMA_PERID_NAND1             1
+#define DMA_PERID_I2S1_DMA0         2
+#define DMA_PERID_SPI2_TXRX         3
+#define DMA_PERID_SSP1_RX           3
+#define DMA_PERID_SDCARD            4
+#define DMA_PERID_HSUART1_TX        5
+#define DMA_PERID_HSUART1_RX        6
+#define DMA_PERID_HSUART2_TX        7
+#define DMA_PERID_HSUART2_RX        8
+#define DMA_PERID_HSUART7_TX        9
+#define DMA_PERID_HSUART7_RX        10
+#define DMA_PERID_I2S1_DMA1         10
+#define DMA_PERID_SPI1_TXRX         11
+#define DMA_PERID_SSP1_TX           11
+#define DMA_PERID_NAND2             12
+#define DMA_PERID_I2S0_DMA1         13
+#define DMA_PERID_SSP0_RX           14
+#define DMA_PERID_SSP0_TX           15
+
+#endif /* __ASM_ARCH_DMAC_H */


From swarren at wwwdotorg.org  Wed Mar  7 15:27:50 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 07 Mar 2012 13:27:50 -0700
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <20120307183633.GB27213@game.jcrosoft.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <20120307180815.GA27213@game.jcrosoft.org> <4F57AB92.6060907@wwwdotorg.org>
 <20120307183633.GB27213@game.jcrosoft.org>
Message-ID: <4F57C4C6.2070602@wwwdotorg.org>

On 03/07/2012 11:36 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 11:40 Wed 07 Mar     , Stephen Warren wrote:
>> On 03/07/2012 11:08 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> On 17:30 Tue 06 Mar     , Stephen Warren wrote:
>>>> This allows the user to use U-Boot's mkimage's -T kernel_noload option
>>>> if their arch Kconfig allows it, and they desire.
>>>>
>>>> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
>>>> ---
>>>> The next patch enables this new CONFIG_ALLOW_ option for ARM. I assume
>>>> that some other architectures will also be able to enable it, but I'm
>>>> not familiar enough with any to know which.
>>> I'm going to repeat. I don't think any impromevent here.
>>>
>>> with no specific kernel load address the uImage for is useless/
>>
>> No, the whole point of this type of kernel image is that it doesn't need
>> a specific load address; the kernel zImage can run from anywhere in RAM
>> (provided AUTO_ZRELADDR is enabled, subject to some slight
>> restrictions), and hence the uImage doesn't need to be loaded to or
>> moved to any particular location.
>>
>> The scripts that U-Boot runs determine where the image gets loaded into
>> memory.
>
> so instead of spending time on the uImage add simply the support the zImage to
> U-Boot as this AUTO_ZRELADDR have 0 advantage compare to the zImage

Thinking more about this, I guess the reliance on AUTO_ZRELADDR is wrong
here; Russell, Nico, is the ARM decompressor fully position-independent
irrespective of the AUTO_ZRELADDR setting. That setting just determines
where the decompressor writes its output, not what address the
decompressor can run at, right? So, this KERNEL_NOLOAD feature could be
enabled in all cases on ARM, not only when AUTO_ZRELADDR is enabled.

As such to address Jean-Christophe's most recent comment above, this
patch isn't about adding support for AUTO_ZRELADDR, but for U-Boot's
kernel_noload feature, so comparisons should be drawn between
kernel_noload uImages and zImage, not between AUTO_ZRELADDR and zImage.

In other words:

We already have and need ZRELADDR no matter what, for reasons unrelated
to U-Boot/uImage.

Patch 1 in this series is just consolidating duplicate definitions, and
doesn't introduce any new features, so I think hope you think it's a
good thing no matter what anyone thinks about U-Boot/uImage.

I assume you're only arguing about patches 2 and 3?


From davej at redhat.com  Wed Mar  7 15:30:31 2012
From: davej at redhat.com (Dave Jones)
Date: Wed, 7 Mar 2012 15:30:31 -0500
Subject: [GIT PULL] cpufreq: OMAP updates for v3.4
In-Reply-To: <87y5rci2na.fsf@ti.com>
References: <87y5rci2na.fsf@ti.com>
Message-ID: <20120307203031.GA7672@redhat.com>

On Wed, Mar 07, 2012 at 12:20:41PM -0800, Kevin Hilman wrote:
 > Dave,
 > 
 > Please pull the following OMAP CPUfreq driver changes for v3.4.

pulled, thanks.

	Dave 


From swarren at wwwdotorg.org  Wed Mar  7 15:51:01 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 07 Mar 2012 13:51:01 -0700
Subject: [RESEND PATCH 0/3] arm: tegra: dts: USB Updates for Tegra legacy
 mode / OTG
In-Reply-To: <1331096674-8324-1-git-send-email-sjg@chromium.org>
References: <1331096674-8324-1-git-send-email-sjg@chromium.org>
Message-ID: <4F57CA35.50406@wwwdotorg.org>

On 03/06/2012 10:04 PM, Simon Glass wrote:
> This little series brings in some bindings that seem useful for U-Boot.
> 
> I am working mostly in U-Boot, but since there is no shared .dts repo
> I was asked to commit these changes to the kernel. I do not propose to
> update the Linux USB drivers to match.
> 
> 
> Simon Glass (3):
>   arm: tegra: dts: Support host/device selection and legacy mode
>   arm: tegra: dts: Add legacy mode support to Tegra2x USB1 port
>   arm: tegra: dts: Mark USB1 as an OTG port on Seaboard

I ack'd this before, but just in case it got lost: The series,

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From s.hauer at pengutronix.de  Wed Mar  7 15:54:29 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 7 Mar 2012 21:54:29 +0100
Subject: [GIT PULL] i.MX 35/5 AIPS Setup
Message-ID: <20120307205429.GO3852@pengutronix.de>


Hi Arnd,

Please pull the following for -next. It contains Fabios Aips setup
patches. They depend on your imx/soc branch.

Sascha

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

  Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:

  git://git.pengutronix.de/git/imx/linux-2.6.git tags/imx35-imx5-aips-setup

for you to fetch changes up to 38bb3630bcba25f16106166a4aaf211c1d195863:

  ARM: mx35: Setup the AIPS registers (2012-03-07 21:29:57 +0100)

----------------------------------------------------------------
i.MX35/5 AIPS setup

----------------------------------------------------------------
Fabio Estevam (2):
      ARM: mx5: Use common function for configuring AIPS
      ARM: mx35: Setup the AIPS registers

 arch/arm/mach-imx/cpu-imx5.c |   36 ------------------------------------
 arch/arm/mach-imx/mm-imx3.c  |    4 ++++
 arch/arm/mach-imx/mm-imx5.c  |    8 ++++++++
 3 files changed, 12 insertions(+), 36 deletions(-)
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From nico at fluxnic.net  Wed Mar  7 16:03:04 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 07 Mar 2012 16:03:04 -0500 (EST)
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <4F57C4C6.2070602@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <20120307180815.GA27213@game.jcrosoft.org> <4F57AB92.6060907@wwwdotorg.org>
 <20120307183633.GB27213@game.jcrosoft.org> <4F57C4C6.2070602@wwwdotorg.org>
Message-ID: <alpine.LFD.2.02.1203071537130.24151@xanadu.home>

On Wed, 7 Mar 2012, Stephen Warren wrote:

> On 03/07/2012 11:36 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 11:40 Wed 07 Mar     , Stephen Warren wrote:
> >> On 03/07/2012 11:08 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>> On 17:30 Tue 06 Mar     , Stephen Warren wrote:
> >>>> This allows the user to use U-Boot's mkimage's -T kernel_noload option
> >>>> if their arch Kconfig allows it, and they desire.
> >>>>
> >>>> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> >>>> ---
> >>>> The next patch enables this new CONFIG_ALLOW_ option for ARM. I assume
> >>>> that some other architectures will also be able to enable it, but I'm
> >>>> not familiar enough with any to know which.
> >>> I'm going to repeat. I don't think any impromevent here.
> >>>
> >>> with no specific kernel load address the uImage for is useless/
> >>
> >> No, the whole point of this type of kernel image is that it doesn't need
> >> a specific load address; the kernel zImage can run from anywhere in RAM
> >> (provided AUTO_ZRELADDR is enabled, subject to some slight
> >> restrictions), and hence the uImage doesn't need to be loaded to or
> >> moved to any particular location.
> >>
> >> The scripts that U-Boot runs determine where the image gets loaded into
> >> memory.
> >
> > so instead of spending time on the uImage add simply the support the zImage to
> > U-Boot as this AUTO_ZRELADDR have 0 advantage compare to the zImage
> 
> Thinking more about this, I guess the reliance on AUTO_ZRELADDR is wrong
> here; Russell, Nico, is the ARM decompressor fully position-independent
> irrespective of the AUTO_ZRELADDR setting.

Absolutely.

> That setting just determines where the decompressor writes its output, 
> not what address the decompressor can run at, right?

Right.

> So, this KERNEL_NOLOAD feature could be
> enabled in all cases on ARM, not only when AUTO_ZRELADDR is enabled.

Except when CONFIG_ZBOOT_ROM is selected (if the uImage format 
allows it), or when the u-Boot environment doesn't know where to load 
the uImage.

FWIW, I really hate this confusing usage of "noload" imposed on us by
we know who.  I thought better than contesting his definition though.

But yes, AUTO_ZRELADDR has no effect on the location where the zImage 
should be _loaded_, except for the 128MB restriction.

> As such to address Jean-Christophe's most recent comment above, this
> patch isn't about adding support for AUTO_ZRELADDR, but for U-Boot's
> kernel_noload feature, so comparisons should be drawn between
> kernel_noload uImages and zImage, not between AUTO_ZRELADDR and zImage.
> 
> In other words:
> 
> We already have and need ZRELADDR no matter what, for reasons unrelated
> to U-Boot/uImage.

Well, I do have a patch series getting rid of ZRELADDR entirely, and 
AUTO_ZRELADDR would then become implicit, unless CONFIG_PHYS_OFFSET is 
defined.


Nicolas


From timur at freescale.com  Wed Mar  7 16:05:48 2012
From: timur at freescale.com (Timur Tabi)
Date: Wed, 7 Mar 2012 15:05:48 -0600
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F57CDAC.9030604@freescale.com>

Shawn Guo wrote:
> Changes since v1:
>  * Address comments from Mark, Timur, and Sascha (Thanks for review).
>  * Drop patches that have been applied by Mark.

So I'm testing them now, and I get this on boot:

ALSA device list:
  No soundcards found.

This happens frequently to my drivers whenever something in ASoC changes.
 And it's a pain to debug because ASoC never tells me what's wrong.

I'm debugging it now.  I'll let you know when I find something.

-- 
Timur Tabi
Linux kernel developer at Freescale



From broonie at opensource.wolfsonmicro.com  Wed Mar  7 16:08:33 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 7 Mar 2012 21:08:33 +0000
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <4F57CDAC.9030604@freescale.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <4F57CDAC.9030604@freescale.com>
Message-ID: <20120307210833.GO3107@opensource.wolfsonmicro.com>

On Wed, Mar 07, 2012 at 03:05:48PM -0600, Timur Tabi wrote:

> This happens frequently to my drivers whenever something in ASoC changes.
>  And it's a pain to debug because ASoC never tells me what's wrong.

Turn on the debug logging in soc-core.c and it'll chatter away about
what's up; not finding cards is a perfectly normal thing s we're not too
verbose.
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From arnd at arndb.de  Wed Mar  7 16:13:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 7 Mar 2012 21:13:04 +0000
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <20120307192723.GE5050@titan.lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203071831.31738.arnd@arndb.de>
 <20120307192723.GE5050@titan.lakedaemon.net>
Message-ID: <201203072113.04369.arnd@arndb.de>

On Wednesday 07 March 2012, Jason wrote:
> Grrr.  Now I'm getting frustrated.  I'm trying to boot without
> earlyprintk.  Evidently, something is wrong with the above, because the
> device boots all the way up (blinky lights come on), but I get no
> messages after the usual "Uncompressing Linux... done, booting the
> kernel."
> 
> Here's my most recent attempt:
> 
>         serial at f1012000 {
>                 device_type = "serial";
>                 compatible = "ns16550a";
>                 reg = <0xf1012000 0x100>; /*phys addr*/
>                 virt-reg = <0xfed12000>;  /*virt addr*/
>                 reg-shift = <2>;
>                 reg-io-width = <1>;
>                 interrupts = <33>;
>                 current-speed = <115200>;
>                 interrupt-parent = <&intc>;
>                 clock-frequency = <200000000>;
>         };
> 
> I've looked at what is done in the powerpc dt's, but, no luck.  When
> earlyprintk is enabled, I see no error messages, just:
> 
> bootconsole [earlycon0] enabled
> debug: skip boot console de-registration.
> ...
> Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
> 
> Any pointers?

My first guess was that clock-frequency is wrong, but it seems that
this one actually is correct, at least it's the same thing that
the platform code sets.

You should never need to pass the virtual address to a device,
most of all because it cannot be known to the device tree at all.
The of_serial driver (you did enable that one in Kconfig, right?)
sets UPF_IOREMAP for this reason, which means membase gets 
overwritten anyway.

You should also not need to set interrupt-parent in the device itself,
as long as it's set in the root node. This one should not hurt though.

Regarting the compatible value, you should check what 
/proc/tty/driver/serial contains when the system is up and running.
If you can log into the system through the network after booting it
up, you can also compare the contents of that file and the 'setserial'
output with what you got before the device tree conversion.

Finally, something could be wrong with the interrupt controller.
AFAICT, you register it through the device tree now, but it's also
getting initialized through kirkwood_init_irq, so the numbers
would all be wrong.

	Arnd


From arnd at arndb.de  Wed Mar  7 16:16:06 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 7 Mar 2012 21:16:06 +0000
Subject: [PATCH 6/6] ARM: at91: add Shutdown Controller (SHDWC) DT support
In-Reply-To: <4F57BD04.5090002@gmail.com>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <201203071849.36867.arnd@arndb.de> <4F57BD04.5090002@gmail.com>
Message-ID: <201203072116.07109.arnd@arndb.de>

On Wednesday 07 March 2012, Rob Herring wrote:
> > 
> > I still don't understand: Doesn't the property already give the information?
> > In general, you should try to encode these things in specific properties instead of
> > checking the compatible property.
> > 
> 
> Or vice-versa, the compatible properties distinguish things enough that
> the property is not needed. If it is fixed in the SOC design, then you
> should distinguish things with the compatible property.

Well, one of the two, basically. I would suggest using special properties
in order to be prepared when other SOCs have the same requirement. If you
know for certain that each one will only ever be needed in one specific
SOC, then the compatible property is enough, but if it's likely that others
will have the same requirement in the future, I think it's much better
to have just a single check rather than a list of SOCs.

	Arnd


From mturquette at ti.com  Wed Mar  7 16:20:07 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 7 Mar 2012 13:20:07 -0800
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120306190039.GJ3852@pengutronix.de>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
Message-ID: <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>

On Tue, Mar 6, 2012 at 11:00 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Mon, Mar 05, 2012 at 12:03:15PM -0800, Turquette, Mike wrote:
>> On Sun, Mar 4, 2012 at 11:38 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>> > On Sun, Mar 04, 2012 at 04:12:21PM -0800, Turquette, Mike wrote:
>> >> >>
>> >> >> I believe this patch already does what you suggest, but I might be
>> >> >> missing your point.
>> >> >
>> >> > In include/linux/clk-private.h you expose struct clk outside the core.
>> >> > This has to be done to make static initializers possible. There is a big
>> >> > warning in this file that it must not be included from files implementing
>> >> > struct clk_ops. You can simply avoid this warning by declaring struct clk
>> >> > with only a single member:
>> >> >
>> >> > include/linux/clk.h:
>> >> >
>> >> > struct clk {
>> >> > ? ? ? ?struct clk_internal *internal;
>> >> > };
>> >> >
>> >> > This way everybody knows struct clk (thus can embed it in their static
>> >> > initializers), but doesn't know anything about the internal members. Now
>> >> > in drivers/clk/clk.c you declare struct clk_internal exactly like struct
>> >> > clk was declared before:
>> >> >
>> >> > struct clk_internal {
>> >> > ? ? ? ?const char ? ? ? ? ? ? ?*name;
>> >> > ? ? ? ?const struct clk_ops ? ?*ops;
>> >> > ? ? ? ?struct clk_hw ? ? ? ? ? *hw;
>> >> > ? ? ? ?struct clk ? ? ? ? ? ? ?*parent;
>> >> > ? ? ? ?char ? ? ? ? ? ? ? ? ? ?**parent_names;
>> >> > ? ? ? ?struct clk ? ? ? ? ? ? ?**parents;
>> >> > ? ? ? ?u8 ? ? ? ? ? ? ? ? ? ? ?num_parents;
>> >> > ? ? ? ?unsigned long ? ? ? ? ? rate;
>> >> > ? ? ? ?unsigned long ? ? ? ? ? flags;
>> >> > ? ? ? ?unsigned int ? ? ? ? ? ?enable_count;
>> >> > ? ? ? ?unsigned int ? ? ? ? ? ?prepare_count;
>> >> > ? ? ? ?struct hlist_head ? ? ? children;
>> >> > ? ? ? ?struct hlist_node ? ? ? child_node;
>> >> > ? ? ? ?unsigned int ? ? ? ? ? ?notifier_count;
>> >> > #ifdef CONFIG_COMMON_CLK_DEBUG
>> >> > ? ? ? ?struct dentry ? ? ? ? ? *dentry;
>> >> > #endif
>> >> > };
>> >> >
>> >> > An instance of struct clk_internal will be allocated in
>> >> > __clk_init/clk_register. Now the private data stays completely inside
>> >> > the core and noone can abuse it.
>> >>
>> >> Hi Sascha,
>> >>
>> >> I see the disconnect here. ?For OMAP (and possibly other platforms) at
>> >> least some clock data is necessary during early boot, before the
>> >> regular allocation methods are available (timers for instance).
>> >
>> > We had this problem on i.MX aswell. It turned out that the timer clock
>> > is the only clock that is needed so early. We solved this by moving the
>> > clock init to the system timer init function.
>>
>> When you say "mov[ed] the clock init to the system timer init
>> function" do you mean that you statically allocated struct clk and
>> used the clk framework api, or instead you just did some direct
>> register writes to initialize things properly?
>
> I meant that on i.MX we do the clock tree initialization when kmalloc is
> available, see the attached patch for omap4 based on your branch which
> does the same for Omap. The first clock you need is the one for the
> timer, so you can initialize the clocktree at the beginning of
> time_init() and don't need statically initialized clocks anymore.
>
>> >
>> > Well, the file is work in progress, you probably fix this before sending
>> > it out, but I bet people will include clk-private.h and nobody else
>> > notices it.
>>
>> clock44xx_data.c does not violate that rule. ?None of the logic that
>> implements ops for those clocks is present clock44xx_data.c.
>
> Indeed, I missed that. It only has the ops but not the individual
> functions.
>
>> All of
>> the code in that file is simply initialization and registration of
>> OMAP4 clocks. ?Many of the clocks are basic clock types (divider,
>> multiplexer and fixed-rate are used in that file) with protected code
>> drivers/clk/clk-*.c and the remaining clocks are of the struct
>> clk_hw_omap variety, which has code spread across several files:
>>
>> arch/arm/mach-omap2/clock.c
>> arch/arm/mach-omap2/clock.h
>> arch/arm/mach-omap2/clkt_dpll.c
>> arch/arm/mach-omap2/clkt_clksel.c
>> arch/arm/mach-omap2/dpll3xxx.c
>> arch/arm/mach-omap2/dpll4xxx.c
>>
>> All of the above files include linux/clk-provider.h, not
>> linux/clk-private.h. ?That code makes heavy use of the
>> __clk_get_whatever helpers and shows how a platform might honor the
>> layer of separation between struct clk and stuct clk_ops/struct
>> clk_foo. ?You are correct that the code is a work-in-progress, but
>> there are no layering violations that I can see.
>>
>> I also think we are talking past each other to some degree. ?One point
>> I would like to make (and maybe you already know this from code
>> review) is that it is unnecessary to have pointers to your parent
>> struct clk*'s when either initializing or registering your clocks. ?In
>> fact the existing clk_register_foo functions don't even allow you to
>> pass in parent pointers and rely wholly on string name matching. ?I
>> just wanted to point that out in case it went unnoticed, as it is a
>> new way of doing things from the previous series and was born out of
>> Thomas' review of V4 and multi-parent handling. ?This also keeps
>> device-tree in mind where we might not know the struct clk *pointer at
>> compile time for "connecting" discrete devices.
>
> Yes, I've seen this and I really like it. Also the change that
> multiplexers return an index to an array instead of the parent
> clock is very nice.
>
> Sascha
>
>
> 8<-----------------------------------------------------
>
> ARM omap4: move clocktree init to timer init time so we don't need static clocks
>
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>

Hi Sascha,

Thanks for the example code.  This is in fact something I had
considered doing before, but it is a bit complicated for my platform.

We set up all of the OMAP clocks with __clk_init because this is a
dependency of OMAP's hwmod code which models and interacts with
specific resources for hardware modules, such as clocks.  There are
other dependencies such as our clockdomain code, which needs the
clocks to be fully initialized.  Some aspects of these layers get
init'd before we can allocate memory.

Admittedly I think that the OMAP code could migrate some of these bits
to a lazy-registration model, specifically the hwmod object instances,
but that requires an awful lot of refactoring for a fairly large stack
of platform code.  This might be something to achieve in the future
but for now we *need* initialisation to be fully static.

Assuming that some day OMAP code can be refactored to allow for lazy
(or at least initcall-based) registration of clocks then perhaps your
suggestion can take root.  Which leads me to this question: are there
any other platforms out there that require the level of expose to
struct clk present in this patchset?  OMAP does, for now, but if that
changes then I need to know if others require this as well.

Regards,
Mike

> ---
> ?arch/arm/mach-omap2/clock44xx_data.c | ? ?4 +++-
> ?arch/arm/mach-omap2/io.c ? ? ? ? ? ? | ? ?1 -
> ?arch/arm/mach-omap2/timer.c ? ? ? ? ?| ? ?3 +++
> ?3 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
> index 7f833a7..5aa8dd2 100644
> --- a/arch/arm/mach-omap2/clock44xx_data.c
> +++ b/arch/arm/mach-omap2/clock44xx_data.c
> @@ -6032,7 +6032,9 @@ int __init omap4xxx_clk_init(void)
> ? ? ? ? ? ? ? ?}
> ?# else
> ? ? ? ? ? ? ? ?clkdev_add(c);
> - ? ? ? ? ? ? ? __clk_init(NULL, c->clk);
> +
> + ? ? ? ? ? ? ? clk_register(NULL, c->clk->name, c->clk->ops, c->clk->hw,
> + ? ? ? ? ? ? ? ? ? ? ? c->clk->parent_names, c->clk->num_parents, c->clk->flags);
> ?#endif
> ? ? ? ?}
>
> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
> index eb50c29..8db4380 100644
> --- a/arch/arm/mach-omap2/io.c
> +++ b/arch/arm/mach-omap2/io.c
> @@ -476,7 +476,6 @@ void __init omap4430_init_early(void)
> ? ? ? ?omap44xx_clockdomains_init();
> ? ? ? ?omap44xx_hwmod_init();
> ? ? ? ?omap_hwmod_init_postsetup();
> - ? ? ? omap4xxx_clk_init();
> ?}
> ?#endif
>
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 5c9acea..2cca796 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -323,9 +323,12 @@ OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
> ?OMAP_SYS_TIMER(3_secure)
> ?#endif
>
> +int __init omap4xxx_clk_init(void);
> +
> ?#ifdef CONFIG_ARCH_OMAP4
> ?static void __init omap4_timer_init(void)
> ?{
> + ? ? ? omap4xxx_clk_init();
> ?#ifdef CONFIG_LOCAL_TIMERS
> ? ? ? ?twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
> ? ? ? ?BUG_ON(!twd_base);
> --
> 1.7.9.1
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Mar  7 16:20:25 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 7 Mar 2012 22:20:25 +0100
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <1330763341-3437-5-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
Message-ID: <20120307212025.GC26882@pengutronix.de>

On Sat, Mar 03, 2012 at 12:29:01AM -0800, Mike Turquette wrote:
> +struct clk *clk_register_divider(struct device *dev, const char *name,
> +		const char *parent_name, unsigned long flags,
> +		void __iomem *reg, u8 shift, u8 width,
> +		u8 clk_divider_flags, spinlock_t *lock)
> +{
> +	struct clk_divider *div;
> +	char **parent_names = NULL;
> +	u8 len;
> +
> +	div = kmalloc(sizeof(struct clk_divider), GFP_KERNEL);
> +
> +	if (!div) {
> +		pr_err("%s: could not allocate divider clk\n", __func__);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	/* struct clk_divider assignments */
> +	div->reg = reg;
> +	div->shift = shift;
> +	div->width = width;
> +	div->flags = clk_divider_flags;
> +	div->lock = lock;
> +
> +	if (parent_name) {
> +		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
> +
> +		if (! parent_names)
> +			goto out;
> +
> +		len = sizeof(char) * strlen(parent_name);
> +
> +		parent_names[0] = kmalloc(len, GFP_KERNEL);
> +
> +		if (!parent_names[0])
> +			goto out;
> +
> +		strncpy(parent_names[0], parent_name, len);
> +	}
> +
> +out:
> +	return clk_register(dev, name,
> +			&clk_divider_ops, &div->hw,
> +			parent_names,
> +			(parent_name ? 1 : 0),
> +			flags);
> +}

clk_register_divider and also clk_register_gate have some problems.
First you allocate memory with exactly the string length without
the terminating 0. Then the functions leak memory when clk_register
fails. Could you fold in the following patch to fix this?

Sascha

8<--------------------------------------------------

fix divider/gate registration

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/clk-divider.c    |   34 +++++++++++++++-------------------
 drivers/clk/clk-gate.c       |   33 ++++++++++++++-------------------
 include/linux/clk-provider.h |    2 ++
 3 files changed, 31 insertions(+), 38 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8f02930..99b6b55 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -156,14 +156,13 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
 		u8 clk_divider_flags, spinlock_t *lock)
 {
 	struct clk_divider *div;
-	char **parent_names = NULL;
-	u8 len;
+	struct clk *clk;
 
-	div = kmalloc(sizeof(struct clk_divider), GFP_KERNEL);
+	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
 
 	if (!div) {
 		pr_err("%s: could not allocate divider clk\n", __func__);
-		return ERR_PTR(-ENOMEM);
+		return NULL;
 	}
 
 	/* struct clk_divider assignments */
@@ -174,25 +173,22 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
 	div->lock = lock;
 
 	if (parent_name) {
-		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
-
-		if (! parent_names)
-			goto out;
-
-		len = sizeof(char) * strlen(parent_name);
-
-		parent_names[0] = kmalloc(len, GFP_KERNEL);
-
-		if (!parent_names[0])
+		div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
+		if (!div->parent[0])
 			goto out;
-
-		strncpy(parent_names[0], parent_name, len);
 	}
 
-out:
-	return clk_register(dev, name,
+	clk = clk_register(dev, name,
 			&clk_divider_ops, &div->hw,
-			parent_names,
+			div->parent,
 			(parent_name ? 1 : 0),
 			flags);
+	if (clk)
+		return clk;
+
+out:
+	kfree(div->parent[0]);
+	kfree(div);
+
+	return NULL;
 }
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index e831f7b..92c0489 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -80,14 +80,13 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 		u8 clk_gate_flags, spinlock_t *lock)
 {
 	struct clk_gate *gate;
-	char **parent_names = NULL;
-	u8 len;
+	struct clk *clk;
 
-	gate = kmalloc(sizeof(struct clk_gate), GFP_KERNEL);
+	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
 
 	if (!gate) {
 		pr_err("%s: could not allocate gated clk\n", __func__);
-		return ERR_PTR(-ENOMEM);
+		return NULL;
 	}
 
 	/* struct clk_gate assignments */
@@ -97,25 +96,21 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 	gate->lock = lock;
 
 	if (parent_name) {
-		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
-
-		if (! parent_names)
-			goto out;
-
-		len = sizeof(char) * strlen(parent_name);
-
-		parent_names[0] = kmalloc(len, GFP_KERNEL);
-
-		if (!parent_names[0])
+		gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
+		if (!gate->parent[0])
 			goto out;
-
-		strncpy(parent_names[0], parent_name, len);
 	}
 
-out:
-	return clk_register(dev, name,
+	clk = clk_register(dev, name,
 			&clk_gate_ops, &gate->hw,
-			parent_names,
+			gate->parent,
 			(parent_name ? 1 : 0),
 			flags);
+	if (clk)
+		return clk;
+out:
+	kfree(gate->parent[0]);
+	kfree(gate);
+
+	return NULL;
 }
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 9b7dd5e..ed1f918 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -174,6 +174,7 @@ struct clk_gate {
 	u8		bit_idx;
 	u8		flags;
 	spinlock_t	*lock;
+	char		*parent[1];
 };
 
 #define CLK_GATE_SET_TO_DISABLE		BIT(0)
@@ -210,6 +211,7 @@ struct clk_divider {
 	u8		width;
 	u8		flags;
 	spinlock_t	*lock;
+	char		*parent[1];
 };
 
 #define CLK_DIVIDER_ONE_BASED		BIT(0)
-- 
1.7.9.1

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From tony at atomide.com  Wed Mar  7 16:32:09 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 13:32:09 -0800
Subject: [PATCH] ARM: OMAP2+: Fix build issues with missing include of
 linux/bug.h
Message-ID: <20120307213209.GI12083@atomide.com>

Otherwise we can get the following for some .config files:

arch/arm/mach-omap2/powerdomain-common.c:
In function 'omap2_pwrdm_get_mem_bank_onstate_mask':
arch/arm/mach-omap2/powerdomain-common.c:64:3: error:
implicit declaration of function 'WARN_ON' [-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors

Signed-off-by: Tony Lindgren <tony at atomide.com>

---

Looks like this is needed for some .config files with
current for-next

--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -43,6 +43,7 @@
 #include <linux/errno.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/bug.h>
 
 #include <plat/clock.h>
 
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -13,6 +13,7 @@
 
 #include <linux/errno.h>
 #include <linux/kernel.h>
+#include <linux/bug.h>
 #include "pm.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/bug.h>
 
 #include <plat/prcm.h>
 
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -13,6 +13,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/bug.h>
 
 #include <plat/cpu.h>
 


From sboyd at codeaurora.org  Wed Mar  7 16:32:23 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 07 Mar 2012 13:32:23 -0800
Subject: [GIT PULL] One more sched_clock() patch
In-Reply-To: <322c288d3ad6aecc8014e0a3582c8527@localhost>
References: <322c288d3ad6aecc8014e0a3582c8527@localhost>
Message-ID: <4F57D3E7.6020605@codeaurora.org>

On 02/27/12 00:44, Marc Zyngier wrote:
> Russell,
>
> Could you please pull from my sched_clock-for-rmk branch again?
> It contains a single additional patch. courtesy of Stephen Boyd, that
> contains support for sched_clock() on msm. The rest of the branch is
> unchanged.

Has this been pulled? I don't see this showing up in linux-next as of
20120307.

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From linux at arm.linux.org.uk  Wed Mar  7 16:28:05 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 21:28:05 +0000
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <4F57C4C6.2070602@wwwdotorg.org>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <20120307180815.GA27213@game.jcrosoft.org> <4F57AB92.6060907@wwwdotorg.org>
 <20120307183633.GB27213@game.jcrosoft.org> <4F57C4C6.2070602@wwwdotorg.org>
Message-ID: <20120307212805.GE18787@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 01:27:50PM -0700, Stephen Warren wrote:
> Thinking more about this, I guess the reliance on AUTO_ZRELADDR is wrong
> here; Russell, Nico, is the ARM decompressor fully position-independent
> irrespective of the AUTO_ZRELADDR setting.

The standard decompressor is fully relocatable into any part of the system
which contains sufficient _RAM_ to contain the size of the zImage plus 64k
malloc space (that's including the BSS for the zImage.)

AUTO_ZRELADDR controls how the _decompressed_ kernel is placed, whether
it is placed at a fixed address controlled by the zreladdr-y symbol
in arch/arm/mach-*/Makefile.boot, or whether it is controlled by where
the zImage is placed - iow, (phys address & 0xf8000000) + TEXT_OFFSET.

> That setting just determines
> where the decompressor writes its output, not what address the
> decompressor can run at, right? So, this KERNEL_NOLOAD feature could be
> enabled in all cases on ARM, not only when AUTO_ZRELADDR is enabled.

I'm not entirely sure about that - there's at least the uboot on some
of the ARM devel platforms which relocates things like the ATAG list if
it's loading a uImage at 0x60008000 vs 0x00008000 (and we want it to be
at the 0x60008000 address so it can see 1GB of memory rather than just
256MB via the low mapping.)

So in some cases we do need control over where the uImage (or zImage)
is loaded by the boot loader.

> In other words:
> 
> We already have and need ZRELADDR no matter what, for reasons unrelated
> to U-Boot/uImage.

That's a tad icky... because a !AUTO_ZRELADDR kernel has no need for a
load address provided it ends up in RAM.  So, uboot enforcing a specific
load address more of an inconvenience rather than a problem.

However, for AUTO_ZRELADDR, the zImage does have to be placed in the
same 128M aligned block of RAM which you want the start of it to be
called PHYS_OFFSET.  So in that sense, an AUTO_ZRELADDR kernel is
more critical with its placement than a !AUTO_ZRELADDR kernel.


From linux at arm.linux.org.uk  Wed Mar  7 16:30:09 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 21:30:09 +0000
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <alpine.LFD.2.02.1203071537130.24151@xanadu.home>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <20120307180815.GA27213@game.jcrosoft.org> <4F57AB92.6060907@wwwdotorg.org>
 <20120307183633.GB27213@game.jcrosoft.org> <4F57C4C6.2070602@wwwdotorg.org>
 <alpine.LFD.2.02.1203071537130.24151@xanadu.home>
Message-ID: <20120307213009.GF18787@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 04:03:04PM -0500, Nicolas Pitre wrote:
> Well, I do have a patch series getting rid of ZRELADDR entirely, and 
> AUTO_ZRELADDR would then become implicit, unless CONFIG_PHYS_OFFSET is 
> defined.

Not possible, unless you're goign to also rip out uImage support.

Otherwise, how do we deal with platforms like Versatile Express where
uboot does a funky relocation of data depending on whether the uImage
it's loading is for the low 256MB RAM mapping or the high 1GB RAM
mapping.


From linux at arm.linux.org.uk  Wed Mar  7 16:38:04 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 21:38:04 +0000
Subject: [GIT PULL] One more sched_clock() patch
In-Reply-To: <4F57D3E7.6020605@codeaurora.org>
References: <322c288d3ad6aecc8014e0a3582c8527@localhost>
 <4F57D3E7.6020605@codeaurora.org>
Message-ID: <20120307213804.GG18787@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 01:32:23PM -0800, Stephen Boyd wrote:
> On 02/27/12 00:44, Marc Zyngier wrote:
> > Russell,
> >
> > Could you please pull from my sched_clock-for-rmk branch again?
> > It contains a single additional patch. courtesy of Stephen Boyd, that
> > contains support for sched_clock() on msm. The rest of the branch is
> > unchanged.
> 
> Has this been pulled? I don't see this showing up in linux-next as of
> 20120307.

Probably not yet, because I really don't like seeing a trickle of "some
more to fix" pull request followed by "oh another one to fix" pull
request, especially when they get pulled into devel-stable.

I'm waiting a bit to see if there's any more on their way. ;)


From michael at walle.cc  Wed Mar  7 16:47:09 2012
From: michael at walle.cc (Michael Walle)
Date: Wed, 7 Mar 2012 22:47:09 +0100
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <20120307192723.GE5050@titan.lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203071831.31738.arnd@arndb.de>
 <20120307192723.GE5050@titan.lakedaemon.net>
Message-ID: <201203072247.10065.michael@walle.cc>

Am Mittwoch 07 M?rz 2012, 20:27:23 schrieb Jason:
> On Wed, Mar 07, 2012 at 06:31:31PM +0000, Arnd Bergmann wrote:
> > On Wednesday 07 March 2012, Jason Cooper wrote:
> > > +       serial at f1012000 {
> > > +               compatible = "ns16550a";
> > > +               reg = <0xf1012000 0xff>;
> > > +               reg-shift = <2>;
> > > +               interrupts = <33>;
> > > +               clock-frequency = <200000000>;
> > > +       };
> > 
> > I just noticed that the length here should be inclusive, i.e. 0x100 not
> > 0xff. This is different from the way we define resources in Linux.
> 
> Grrr.  Now I'm getting frustrated.  I'm trying to boot without
> earlyprintk.  Evidently, something is wrong with the above, because the
> device boots all the way up (blinky lights come on), but I get no
> messages after the usual "Uncompressing Linux... done, booting the
> kernel."
> 
> Here's my most recent attempt:
> 
>         serial at f1012000 {
>                 device_type = "serial";
>                 compatible = "ns16550a";
>                 reg = <0xf1012000 0x100>; /*phys addr*/
>                 virt-reg = <0xfed12000>;  /*virt addr*/
>                 reg-shift = <2>;
>                 reg-io-width = <1>;
>                 interrupts = <33>;
>                 current-speed = <115200>;
>                 interrupt-parent = <&intc>;
>                 clock-frequency = <200000000>;
>         };
> 
> I've looked at what is done in the powerpc dt's, but, no luck.  When
> earlyprintk is enabled, I see no error messages, just:
> 
> bootconsole [earlycon0] enabled
> debug: skip boot console de-registration.
> ...
> Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
> 
> Any pointers?

dunno if that helps a lot but the following was working for me with my 
linkstation:

        serial0: serial at f1012000 {
                cell-index = <0>;
                device_type = "serial";
                compatible = "ns16550a";
                reg = <0xf1012000 0x20>;
                reg-shift = <2>;
                clock-frequency = <200000000>;
                interrupts = <33>;
        };

-- 
michael


From linux at arm.linux.org.uk  Wed Mar  7 16:52:49 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 21:52:49 +0000
Subject: [PATCH] ARM: LPX32xx: DMA support
In-Reply-To: <1331151929-23298-1-git-send-email-stigge@antcom.de>
References: <1331151929-23298-1-git-send-email-stigge@antcom.de>
Message-ID: <20120307215249.GH18787@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 09:25:29PM +0100, Roland Stigge wrote:
> This patch adds DMA support to the LPC32xx platform
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>
> 
> ---
> 
>  Applies to v3.3-rc6.  This patch is a precondition for the NAND and audio
>  drivers (to be sent in one of my next mails).

Is there a reason this can't be converted to a dmaengine driver?

> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/interrupt.h>
> +#include <linux/errno.h>
> +#include <linux/err.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/clk.h>
> +
> +#include <asm/system.h>
> +#include <mach/hardware.h>
> +#include <mach/platform.h>
> +#include <asm/dma-mapping.h>

Not required.

> +#include <asm/io.h>

linux/io.h?

> +static int __init lpc32xx_dma_init(void)
> +{
> +	int ret;
> +
> +	ret = request_irq(IRQ_LPC32XX_DMA, dma_irq_handler, 0, "DMA", NULL);
> +	if (ret) {
> +		printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");

Why KERN_CRIT?

Also consider printing the reason why it failed (errno stored in ret.)

> +		goto out;
> +	}
> +
> +	/* Get DMA clock */
> +	dma_ctrl.clk = clk_get(NULL, "clk_dmac");
> +	if (IS_ERR(dma_ctrl.clk)) {
> +		ret = -ENODEV;

		ret = PTR_ERR(dma_ctrl.clk);

> +struct dma_linked_list {
> +	__le32 src;
> +	__le32 dest;
> +	__le32 next_lli;
> +	__le32 ctrl;
> +};

This looks familiar.

> +struct dma_config {
> +	int ch;		/* Channel # to use */
> +	int tc_inten;	/* !0 = Enable TC interrupts for this channel */
> +	int err_inten;	/* !0 = Enable error interrupts for this channel */
> +	int src_size;	/* Source xfer size - must be 1, 2, or 4 */
> +	int src_inc;	/* !0 = Enable source address increment */
> +	int src_ahb1;	/* !0 = Use AHB1 for source transfer */

Oh, two AHBs.

> +/* DMA controller register structures */
> +#define DMA_INT_STAT(x)			(x + 0x00)
> +#define DMA_INT_TC_STAT(x)		(x + 0x04)
> +#define DMA_INT_TC_CLEAR(x)		(x + 0x08)
> +#define DMA_INT_ERR_STAT(x)		(x + 0x0C)
> +#define DMA_INT_ERR_CLEAR(x)		(x + 0x10)
> +#define DMA_RAW_TC_STAT(x)		(x + 0x14)
> +#define DMA_RAW_ERR_STAT(x)		(x + 0x18)
> +#define DMA_CH_ENABLE(x)		(x + 0x1C)
> +#define DMA_SW_BURST_REQ(x)		(x + 0x20)
> +#define DMA_SW_SINGLE_REQ(x)		(x + 0x24)
> +#define DMA_SW_LAST_BURST_REQ(x)	(x + 0x28)
> +#define DMA_SW_LAST_SINGLE_REQ(x)	(x + 0x2C)
> +#define DMA_CONFIG(x)			(x + 0x30)
> +#define DMA_SYNC(x)			(x + 0x34)
> +
> +/* DMA controller channel register structure */
> +#define DMA_CH_OFFS(c)			((c * 0x20) + 0x100)
> +#define DMACH_SRC_ADDR(x, c)		(x + DMA_CH_OFFS(c) + 0x00)
> +#define DMACH_DEST_ADDR(x, c)		(x + DMA_CH_OFFS(c) + 0x04)
> +#define DMACH_LLI(x, c)			(x + DMA_CH_OFFS(c) + 0x08)
> +#define DMACH_CONTROL(x, c)		(x + DMA_CH_OFFS(c) + 0x0C)
> +#define DMACH_CONFIG_CH(x, c)		(x + DMA_CH_OFFS(c) + 0x10)

Oh, the register layout is identical to the AMBA PL08x primecell.
> +
> +/* DMA linked list structure */
> +#define DMA_LL_SRC(x)			(x + 0x0)
> +#define DMA_LL_DEST(x)			(x + 0x4)
> +#define DMA_LL_NEXT_LLI(x)		(x + 0x8)
> +#define DMA_LL_NEXT_CTRL(x)		(x + 0xC)
> +
> +#define DMA_LL_SIZE 16
> +
> +/**********************************************************************
> +* int_stat, int_tc_stat, int_tc_clear, int_err_stat, raw_tc_stat,
> +* raw_err_stat, and chan_enable register definitions
> +**********************************************************************/
> +/* Macro for determining a bit position for a channel */
> +#define DMAC_GET_CHAN_POS(chan)     (0x1 << ((chan) & 0x7))
> +
> +/**********************************************************************
> +* sw_burst_req, sw_single_req, sw_last_burst_req, sw_last_single_req,
> +* and sync register definitions
> +**********************************************************************/
> +/* Peripheral DMA bit position for I2S0 DMA0 */
> +#define DMA_PER_I2S0_DMA0           _BIT(0)
> +
> +/* Peripheral DMA bit position for NAND FLASH (same as 12) */
> +#define DMA_PER_NAND1               _BIT(1)
> +
> +/* Peripheral DMA bit position for I2S1 DMA0 */
> +#define DMA_PER_I2S1_DMA0           _BIT(2)
> +
> +/* Peripheral DMA bit position for SPI2 (RX and TX) */
> +#define DMA_PER_SPI2_TXRX           _BIT(3)
> +
> +/* Peripheral DMA bit position for SSP1 (RX) */
> +#define DMA_PER_SSP1_RX             _BIT(3)
> +
> +/* Peripheral DMA bit position for SD card */
> +#define DMA_PER_SDCARD              _BIT(4)
> +
> +/* Peripheral DMA bit position for HSUART1 TX */
> +#define DMA_PER_HSUART1_TX          _BIT(5)
> +
> +/* Peripheral DMA bit position for HSUART1 RX */
> +#define DMA_PER_HSUART1_RX          _BIT(6)
> +
> +/* Peripheral DMA bit position for HSUART2 TX */
> +#define DMA_PER_HSUART2_TX          _BIT(7)
> +
> +/* Peripheral DMA bit position for HSUART2 RX */
> +#define DMA_PER_HSUART2_RX          _BIT(8)
> +
> +/* Peripheral DMA bit position for HSUART7 TX */
> +#define DMA_PER_HSUART7_TX          _BIT(9)
> +
> +/* Peripheral DMA bit position for HSUART7 RX */
> +#define DMA_PER_HSUART7_RX          _BIT(10)
> +
> +/* Peripheral DMA bit position for I2S1 DMA1 */
> +#define DMA_PER_I2S1_DMA1           _BIT(10)
> +
> +/* Peripheral DMA bit position for SPI1 (RX and TX) */
> +#define DMA_PER_SPI1_TXRX           _BIT(11)
> +
> +/* Peripheral DMA bit position for SSP1 (TX) */
> +#define DMA_PER_SSP1_TX             _BIT(11)
> +
> +/* Peripheral DMA bit position for NAND FLASH (same as 1) */
> +#define DMA_PER_NAND2               _BIT(12)
> +
> +/* Peripheral DMA bit position for I2S0 DMA1 */
> +#define DMA_PER_I2S0_DMA1           _BIT(13)
> +
> +/* Peripheral DMA bit position for SSP0 (RX) */
> +#define DMA_PER_SSP0_RX             _BIT(14)
> +
> +/* Peripheral DMA bit position for SSP0 (TX) */
> +#define DMA_PER_SSP0_TX             _BIT(15)
> +
> +/**********************************************************************
> +* config register definitions
> +**********************************************************************/
> +/* Bit for enabling big endian mode on AHB 1 */
> +#define DMAC_BIG_ENDIAN_AHB1        _BIT(2)
> +
> +/* Bit for enabling big endian mode on AHB 0 */
> +#define DMAC_BIG_ENDIAN_AHB0        _BIT(1)
> +
> +/* Bit for enabling the DMA controller */
> +#define DMAC_CTRL_ENABLE            _BIT(0)
> +
> +/**********************************************************************
> +* lli register definitions
> +**********************************************************************/
> +/* Bit for selecting AHB0 (0) or AHB1 (1) */
> +#define DMAC_CHAN_LLI_SEL_AHB1      _BIT(0)
> +
> +/**********************************************************************
> +* control register definitions
> +**********************************************************************/
> +/* Bit for enabling a channel terminal count interrupt */
> +#define DMAC_CHAN_INT_TC_EN         _BIT(31)
> +
> +/* Bit for indicating address is cacheable */
> +#define DMAC_CHAN_PROT3             _BIT(30)
> +
> +/* Bit for indicating address is bufferable */
> +#define DMAC_CHAN_PROT2             _BIT(29)
> +
> +/* Bit for indicating address is privelaged mode (1) or user
> +   mode (0) */
> +#define DMAC_CHAN_PROT1             _BIT(28)
> +
> +/* Bit for enabling automatic destination increment */
> +#define DMAC_CHAN_DEST_AUTOINC      _BIT(27)
> +
> +/* Bit for enabling automatic source increment */
> +#define DMAC_CHAN_SRC_AUTOINC       _BIT(26)
> +
> +/* Bit for using AHB1 master for destination transfer */
> +#define DMAC_CHAN_DEST_AHB1         _BIT(25)
> +
> +/* Bit for using AHB1 master for source transfer */
> +#define DMAC_CHAN_SRC_AHB1          _BIT(24)
> +
> +/* Destination data width selection defines */
> +#define DMAC_CHAN_DEST_WIDTH_8      0x0
> +#define DMAC_CHAN_DEST_WIDTH_16     _BIT(21)
> +#define DMAC_CHAN_DEST_WIDTH_32     _BIT(22)
> +
> +/* Source data width selection defines */
> +#define DMAC_CHAN_SRC_WIDTH_8       0x0
> +#define DMAC_CHAN_SRC_WIDTH_16      _BIT(18)
> +#define DMAC_CHAN_SRC_WIDTH_32      _BIT(19)
> +
> +/* Destination data burst size defines (in transfer width) */
> +#define DMAC_CHAN_DEST_BURST_1      0
> +#define DMAC_CHAN_DEST_BURST_4      _BIT(15)
> +#define DMAC_CHAN_DEST_BURST_8      _BIT(16)
> +#define DMAC_CHAN_DEST_BURST_16     (_BIT(16) | _BIT(15))
> +#define DMAC_CHAN_DEST_BURST_32     _BIT(17)
> +#define DMAC_CHAN_DEST_BURST_64     (_BIT(17) | _BIT(15))
> +#define DMAC_CHAN_DEST_BURST_128    (_BIT(17) | _BIT(16))
> +#define DMAC_CHAN_DEST_BURST_256    (_BIT(17) | _BIT(16) | _BIT(15))
> +
> +/* Macro for direct loading of destination burst size field */
> +#define DMAC_CHAN_DEST_BURST_LOAD(n) (((n) & 0x7) << 15)
> +
> +/* Source data burst size defines (in transfer width) */
> +#define DMAC_CHAN_SRC_BURST_1       0
> +#define DMAC_CHAN_SRC_BURST_4       _BIT(12)
> +#define DMAC_CHAN_SRC_BURST_8       _BIT(13)
> +#define DMAC_CHAN_SRC_BURST_16      (_BIT(13) | _BIT(12))
> +#define DMAC_CHAN_SRC_BURST_32      _BIT(14)
> +#define DMAC_CHAN_SRC_BURST_64      (_BIT(14) | _BIT(12))
> +#define DMAC_CHAN_SRC_BURST_128     (_BIT(14) | _BIT(13))
> +#define DMAC_CHAN_SRC_BURST_256     (_BIT(14) | _BIT(13) | _BIT(12))
> +
> +/* Macro for direct loading of source burst size field */
> +#define DMAC_CHAN_SRC_BURST_LOAD(n) (((n) & 0x7) << 12)
> +
> +/* Macro for loading transfer size */
> +#define DMAC_CHAN_TRANSFER_SIZE(n)  ((n) & 0xFFF)

Same bit definitions for the control register....

> +
> +/**********************************************************************
> +* config_ch register definitions
> +**********************************************************************/
> +/* Bit for halting a DMA transfer */
> +#define DMAC_CHAN_HALT              _BIT(18)
> +
> +/* Bit for checking active status of the DMA channel */
> +#define DMAC_CHAN_ACTIVE            _BIT(17)
> +
> +/* Bit for enabling locked transfers */
> +#define DMAC_CHAN_LOCK              _BIT(16)
> +
> +/* Terminal count interrupt mask bit */
> +#define DMAC_CHAN_ITC               _BIT(15)
> +
> +/* Interrupt error mask bit */
> +#define DMAC_CHAN_IE                _BIT(14)
> +
> +/* Defines for flow control with DMA as the controller */
> +#define DMAC_CHAN_FLOW_D_M2M        (0x0 << 11)
> +#define DMAC_CHAN_FLOW_D_M2P        (0x1 << 11)
> +#define DMAC_CHAN_FLOW_D_P2M        (0x2 << 11)
> +#define DMAC_CHAN_FLOW_D_SP2DP      (0x3 << 11)
> +
> +/* Defines for flow control with destination peripheral as the
> +   controller */
> +#define DMAC_CHAN_FLOW_DP_SP2DP     (0x4 << 11)
> +
> +/* Defines for flow control with peripheral as the controller */
> +#define DMAC_CHAN_FLOW_P_M2P        (0x5 << 11)
> +#define DMAC_CHAN_FLOW_P_P2M        (0x6 << 11)
> +
> +/* Defines for flow control with source peripheral as the
> +   controller */
> +#define DMAC_CHAN_FLOW_SP_SP2DP     (0x7 << 11)
> +
> +/* Macro for loading destination peripheral */
> +#define DMAC_DEST_PERIP(n)          (((n) & 0x1F) << 6)
> +
> +/* Macro for loading source peripheral */
> +#define DMAC_SRC_PERIP(n)           (((n) & 0x1F) << 1)
> +
> +/* Channel enable bit */
> +#define DMAC_CHAN_ENABLE            _BIT(0)

And the channel configuration register...

So, no need to convert this to a DMA engine driver, because there's
already one provided in the mainline kernel source.  Please make use
of it rather than reinventing the square wheel.

Thanks.


From u.kleine-koenig at pengutronix.de  Wed Mar  7 17:03:56 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Wed,  7 Mar 2012 23:03:56 +0100
Subject: [PATCH] ARM: davinci: DA850: move da850_register_pm to .init.text
Message-ID: <1331157836-30527-1-git-send-email-u.kleine-koenig@pengutronix.de>

All callers (board-mityomapl138.c and board-da850-evm.c) use it in
__init functions only.

This fixes:

	WARNING: vmlinux.o(.text+0xd664): Section mismatch in reference from the function da850_register_pm() to the function .init.text:da8xx_get_mem_ctlr()
	The function da850_register_pm() references
	the function __init da8xx_get_mem_ctlr().
	This is often because da850_register_pm lacks a __init
	annotation or the annotation of da8xx_get_mem_ctlr is wrong.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-davinci/da850.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 992c4c4..b44dc84 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1026,7 +1026,7 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
 }
 #endif
 
-int da850_register_pm(struct platform_device *pdev)
+int __init da850_register_pm(struct platform_device *pdev)
 {
 	int ret;
 	struct davinci_pm_config *pdata = pdev->dev.platform_data;
-- 
1.7.9.1



From olof at lixom.net  Wed Mar  7 17:18:19 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 7 Mar 2012 14:18:19 -0800
Subject: Latest OMAP4 build errors
In-Reply-To: <20120307171044.GE12083@atomide.com>
References: <20120228090209.GC18045@n2100.arm.linux.org.uk>
 <CAK=WgbZEDr_fYSonBQr3XNcTx5vefsH7LJfqycaxsqg-yechWQ@mail.gmail.com>
 <20120306165545.GB15392@n2100.arm.linux.org.uk>
 <201203061701.54141.arnd@arndb.de>
 <20120307100615.GA17404@n2100.arm.linux.org.uk>
 <20120307171044.GE12083@atomide.com>
Message-ID: <CAOesGMiNSyc9F+Wf5pXPG=hRAfnG6aMHtccLBwvekuB3HpyevQ@mail.gmail.com>

Hi,

On Wed, Mar 7, 2012 at 9:10 AM, Tony Lindgren <tony at atomide.com> wrote:
> Hi,
>
> Arnd & Olof, some urgent changes are needed, see below.
>
> * Russell King - ARM Linux <linux at arm.linux.org.uk> [120307 01:34]:
>> On Tue, Mar 06, 2012 at 05:01:53PM +0000, Arnd Bergmann wrote:
>> > On Tuesday 06 March 2012, Russell King - ARM Linux wrote:
>> > > On Tue, Feb 28, 2012 at 12:11:37PM +0200, Ohad Ben-Cohen wrote:
>> > > > On Tue, Feb 28, 2012 at 12:01 PM, Arnd Bergmann <arnd at arndb.de> wrote:
>> > > > > I think 'depends' would be better here, because selecting IOMMU_SUPPORT
>> > > > > has other side-effects that a user might not want. It's just as likely
>> > > > > that someone wants to disable IOMMU_SUPPORT and needs to find OMAP_REMOTEPROC
>> > > > > as wanting to enable OMAP_REMOTEPROC and having to find IOMMU_SUPPORT.
>> > > > >
>> > > > > In most cases, the defconfig should just set both.
>> > > >
>> > > > Ok, 'depends on' it is.
>> > >
>> > > We're a week on, which means I now have a full set of 7 builds on the
>> > > website for OMAP4430 all of which have failed in part due to this
>> > > as yet unresolved problem.
>> > >
>> > > What's happening to get it fixed and those fixes into whatever tree is
>> > > necessary for them (presumably arm-soc)?
>> >
>> > Ohad has sent a series of patches for review and there were no comments
>> > on those. The fix was part of it as far as I remember. I'm still waiting
>> > for a pull request from Ohad.
>>
>> Given that we're coming to the end of what could be the _final_ week
>> before the merge window opens, this is not good news. ?Read: maybe
>> three days before final.
>>
>> The fact is that OMAP is - yet again - in a totally rotten state in terms
>> of what's queued up in the armsoc tree. ?It is - yet again - completely
>> unbuildable for many configurations. ?Just go and have a look at:
>>
>> ? ? ? http://www.arm.linux.org.uk/developer/build/
>>
>> to see what an utterly crappy state OMAP is in again. ?Last nights build
>> was my tree plus latest arm-soc. ?Some of those issues have patches (I
>> had been applying one patch manually to the build tree) but that's not
>> the point - they're not in arm-soc, so the OMAP code in arm-soc is not
>> yet ready for mainline.
>
> Yes looks like there's an issue with getting urgent patches applied into
> the arm-soc tree.. The patches to fix these issues are known and
> other issues and warnings should be all sorted out now except for some
> MMC changes that are still being discussed.
>
>> So, as OMAP is soo broken, and as promised after the last merge window -
>> I don't want any OMAP stuff going upstream from armsoc until we get error
>> free builds from the allno and old configs on the builder.
>
> What I got queued up in fixes-non-critical-part2 should fix all those
> errors and warnings.
>
> Arnd & Olof, I've posted one fix that should be applied to arm-soc tree
> at [1]. I've also posted a request to revert one commit in arm-soc tree
> at [2].
>
> As it seems that you did not apply those to arm-soc, please apply them,
> or repull the following two branches ASAP:

Done (repulled the branches). Stephen Rothwell has not surfaced on irc
yet, so hopefully this means it'll make it into today's linux-next.

>
> Re-pull fixes-non-critical containing one revert:
>
> Revert "ARM: OMAP2+: Fix multiple randconfig errors with SOC_OMAP and SOC_OMAP_NOOP"
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fixes-non-critical
>
> Re-pull cleanup again containing one fix:
>
> ARM: OMAP2+: Fix L4_EMU_34XX_BASE error after iomap changes
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap cleanup
>
> Note that the second one I just pushed, however the patch is known to
> work for the build errors after merging arm-soc with Russell's changes.

Looks like you pasted the wrong subject above -- the mail below
contains the patch that you added though so it looked OK to me (the
subject above was the previous top-of-branch before you added the last
one).

> Arnd & Olof, for future, how you want to handle urgent issues like this?

Personally I missed the requests since they ended up in the chain of
replies and I didn't notice them, my mistake. A separate email
requesting pulls or patch application it to arm at kernel.org would
reduce the risk of that happening (Flagging the subject with [URGENT]
wouldn't hurt).


-Olof


From w.sang at pengutronix.de  Wed Mar  7 17:28:31 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed,  7 Mar 2012 23:28:31 +0100
Subject: [PATCH 0/3] introduce stmp-style devices
Message-ID: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>

This series makes support for a certain type of devices mach independant. We
want that because such devices (having a special register layout) have been
found in mach-mxs and mach-mx6 meanwhile. Please refer to patch 1/3 for a more
detailed description.

Patch 1/3 adds the basic support and is of main interest to get upstream.
Patches 2/3 and 3/3 are usage examples and will be send to the relevant
subsystems once the basic support is accepted.

Main changes since the RFC:

* renamed the macros to STMP_OFFSET_*
* rebased to 3.3-rc6

Tested with a TX28 board.

Thanks,

   Wolfram

Wolfram Sang (3):
  drivers: base: add support for stmp-style devices
  i2c: mxs: use global reset function
  rtc: stmp3xxx: use global stmp_device functionality

 drivers/base/Kconfig         |    3 ++
 drivers/base/Makefile        |    1 +
 drivers/base/stmp_device.c   |   80 ++++++++++++++++++++++++++++++++++++++++++
 drivers/i2c/busses/Kconfig   |    1 +
 drivers/i2c/busses/i2c-mxs.c |    9 +----
 drivers/rtc/Kconfig          |    1 +
 drivers/rtc/rtc-stmp3xxx.c   |   29 +++++----------
 include/linux/stmp_device.h  |   19 ++++++++++
 8 files changed, 117 insertions(+), 26 deletions(-)
 create mode 100644 drivers/base/stmp_device.c
 create mode 100644 include/linux/stmp_device.h

-- 
1.7.9.1



From w.sang at pengutronix.de  Wed Mar  7 17:28:33 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed,  7 Mar 2012 23:28:33 +0100
Subject: [PATCH 2/3] i2c: mxs: use global reset function
In-Reply-To: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
References: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
Message-ID: <1331159314-12022-3-git-send-email-w.sang@pengutronix.de>

The former mach specific reset_block function has been converted to a global
one. Use the new one to remove mach dependency from the driver.

Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
---
 drivers/i2c/busses/Kconfig   |    1 +
 drivers/i2c/busses/i2c-mxs.c |    9 ++-------
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 3101dd5..d4378cf 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -467,6 +467,7 @@ config I2C_MV64XXX
 config I2C_MXS
 	tristate "Freescale i.MX28 I2C interface"
 	depends on SOC_IMX28
+	select STMP_DEVICE
 	help
 	  Say Y here if you want to use the I2C bus controller on
 	  the Freescale i.MX28 processors.
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 3d471d5..0834802 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -26,8 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/jiffies.h>
 #include <linux/io.h>
-
-#include <mach/common.h>
+#include <linux/stmp_device.h>
 
 #define DRIVER_NAME "mxs-i2c"
 
@@ -111,13 +110,9 @@ struct mxs_i2c_dev {
 	struct i2c_adapter adapter;
 };
 
-/*
- * TODO: check if calls to here are really needed. If not, we could get rid of
- * mxs_reset_block and the mach-dependency. Needs an I2C analyzer, probably.
- */
 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
 {
-	mxs_reset_block(i2c->regs);
+	stmp_reset_block(i2c->regs);
 	writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 	writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
 			i2c->regs + MXS_I2C_QUEUECTRL_SET);
-- 
1.7.9.1



From w.sang at pengutronix.de  Wed Mar  7 17:28:32 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed,  7 Mar 2012 23:28:32 +0100
Subject: [PATCH 1/3] drivers: base: add support for stmp-style devices
In-Reply-To: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
References: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
Message-ID: <1331159314-12022-2-git-send-email-w.sang@pengutronix.de>

MX23/28 use IP cores which follow a register layout I have first seen on
STMP3xxx SoCs. In this layout, every register actually has four u32:

 1.) to store a value directly
 2.) a SET register where every 1-bit sets the corresponding bit,
     others are unaffected
 3.) same with a CLR register
 4.) same with a TOG (toggle) register

Also, the 2 MSBs in register 0 are always the same and can be used to reset
the IP core.

All this is strictly speaking not mach-specific (but IP core specific) and,
thus, doesn't need to be in mach-mxs/include. At least mx6 also uses IP cores
following this stmp-style. So:

Introduce a stmp-style device, put the code and defines for that in a public
place (drivers/base/), and let drivers for stmp-style devices select that code.
To avoid regressions and ease reviewing, the actual code is simply copied from
mach-mxs. It definately wants updates, but those need a seperate patch series.

Voila, mach dependency gone, reusable code introduced. Note that I didn't
remove the duplicated code from mach-mxs yet, first the drivers have to be
converted.

Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
---
 drivers/base/Kconfig        |    3 ++
 drivers/base/Makefile       |    1 +
 drivers/base/stmp_device.c  |   80 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/stmp_device.h |   19 ++++++++++
 4 files changed, 103 insertions(+), 0 deletions(-)
 create mode 100644 drivers/base/stmp_device.c
 create mode 100644 include/linux/stmp_device.h

diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index 7be9f79..bcd3356 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
@@ -176,6 +176,9 @@ config GENERIC_CPU_DEVICES
 	bool
 	default n
 
+config STMP_DEVICE
+	bool
+
 source "drivers/base/regmap/Kconfig"
 
 config DMA_SHARED_BUFFER
diff --git a/drivers/base/Makefile b/drivers/base/Makefile
index 610f999..86e4134 100644
--- a/drivers/base/Makefile
+++ b/drivers/base/Makefile
@@ -18,6 +18,7 @@ ifeq ($(CONFIG_SYSFS),y)
 obj-$(CONFIG_MODULES)	+= module.o
 endif
 obj-$(CONFIG_SYS_HYPERVISOR) += hypervisor.o
+obj-$(CONFIG_STMP_DEVICE) += stmp_device.o
 obj-$(CONFIG_REGMAP)	+= regmap/
 
 ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG
diff --git a/drivers/base/stmp_device.c b/drivers/base/stmp_device.c
new file mode 100644
index 0000000..8ac9bcc
--- /dev/null
+++ b/drivers/base/stmp_device.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel at pengutronix.de
+ * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok at emcraft.com
+ * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/stmp_device.h>
+
+#define STMP_MODULE_CLKGATE	(1 << 30)
+#define STMP_MODULE_SFTRST	(1 << 31)
+
+/*
+ * Clear the bit and poll it cleared.  This is usually called with
+ * a reset address and mask being either SFTRST(bit 31) or CLKGATE
+ * (bit 30).
+ */
+static int stmp_clear_poll_bit(void __iomem *addr, u32 mask)
+{
+	int timeout = 0x400;
+
+	writel(mask, addr + STMP_OFFSET_REG_CLR);
+	udelay(1);
+	while ((readl(addr) & mask) && --timeout)
+		/* nothing */;
+
+	return !timeout;
+}
+
+int stmp_reset_block(void __iomem *reset_addr)
+{
+	int ret;
+	int timeout = 0x400;
+
+	/* clear and poll SFTRST */
+	ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
+	if (unlikely(ret))
+		goto error;
+
+	/* clear CLKGATE */
+	writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR);
+
+	/* set SFTRST to reset the block */
+	writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET);
+	udelay(1);
+
+	/* poll CLKGATE becoming set */
+	while ((!(readl(reset_addr) & STMP_MODULE_CLKGATE)) && --timeout)
+		/* nothing */;
+	if (unlikely(!timeout))
+		goto error;
+
+	/* clear and poll SFTRST */
+	ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
+	if (unlikely(ret))
+		goto error;
+
+	/* clear and poll CLKGATE */
+	ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_CLKGATE);
+	if (unlikely(ret))
+		goto error;
+
+	return 0;
+
+error:
+	pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
+	return -ETIMEDOUT;
+}
+EXPORT_SYMBOL(stmp_reset_block);
diff --git a/include/linux/stmp_device.h b/include/linux/stmp_device.h
new file mode 100644
index 0000000..d088de2
--- /dev/null
+++ b/include/linux/stmp_device.h
@@ -0,0 +1,19 @@
+/*
+ * basic functions for devices following the "stmp" style register layout
+ *
+ * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#ifndef __STMP_DEVICE_H__
+#define __STMP_DEVICE_H__
+
+#define STMP_OFFSET_REG_SET	0x4
+#define STMP_OFFSET_REG_CLR	0x8
+#define STMP_OFFSET_REG_TOG	0xc
+
+extern int stmp_reset_block(void __iomem *);
+#endif /* __STMP_DEVICE_H__ */
-- 
1.7.9.1



From w.sang at pengutronix.de  Wed Mar  7 17:28:34 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed,  7 Mar 2012 23:28:34 +0100
Subject: [PATCH 3/3] rtc: stmp3xxx: use global stmp_device functionality
In-Reply-To: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
References: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
Message-ID: <1331159314-12022-4-git-send-email-w.sang@pengutronix.de>

The former mach specific reset_block function has been converted to a global
one. Use the new one to remove mach dependency from the driver. Also simplify
code using the new STMP_OFFSET_REG_* macros.

Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
---
 drivers/rtc/Kconfig        |    1 +
 drivers/rtc/rtc-stmp3xxx.c |   29 ++++++++++-------------------
 2 files changed, 11 insertions(+), 19 deletions(-)

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 3a125b8..e124f93 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -983,6 +983,7 @@ config RTC_DRV_COH901331
 config RTC_DRV_STMP
 	tristate "Freescale STMP3xxx/i.MX23/i.MX28 RTC"
 	depends on ARCH_MXS
+	select STMP_DEVICE
 	help
 	  If you say yes here you will get support for the onboard
 	  STMP3xxx/i.MX23/i.MX28 RTC.
diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c
index 1028786..e755d3e 100644
--- a/drivers/rtc/rtc-stmp3xxx.c
+++ b/drivers/rtc/rtc-stmp3xxx.c
@@ -25,11 +25,9 @@
 #include <linux/interrupt.h>
 #include <linux/rtc.h>
 #include <linux/slab.h>
-
-#include <mach/common.h>
+#include <linux/stmp_device.h>
 
 #define STMP3XXX_RTC_CTRL			0x0
-#define STMP3XXX_RTC_CTRL_SET			0x4
 #define STMP3XXX_RTC_CTRL_CLR			0x8
 #define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN		0x00000001
 #define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN	0x00000002
@@ -44,7 +42,6 @@
 #define STMP3XXX_RTC_ALARM			0x40
 
 #define STMP3XXX_RTC_PERSISTENT0		0x60
-#define STMP3XXX_RTC_PERSISTENT0_SET		0x64
 #define STMP3XXX_RTC_PERSISTENT0_CLR		0x68
 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN	0x00000002
 #define STMP3XXX_RTC_PERSISTENT0_ALARM_EN	0x00000004
@@ -106,20 +103,14 @@ static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
 static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
 {
 	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
+	u32 set_clr_offset = enabled ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
+
+	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
+		STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
+		rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + set_clr_offset);
+	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
+		rtc_data->io + STMP3XXX_RTC_CTRL + set_clr_offset);
 
-	if (enabled) {
-		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
-				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
-				rtc_data->io + STMP3XXX_RTC_PERSISTENT0_SET);
-		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
-				rtc_data->io + STMP3XXX_RTC_CTRL_SET);
-	} else {
-		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
-				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
-				rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR);
-		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
-				rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
-	}
 	return 0;
 }
 
@@ -206,7 +197,7 @@ static int stmp3xxx_rtc_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, rtc_data);
 
-	mxs_reset_block(rtc_data->io);
+	stmp_reset_block(rtc_data->io);
 	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
 			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
@@ -253,7 +244,7 @@ static int stmp3xxx_rtc_resume(struct platform_device *dev)
 {
 	struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(dev);
 
-	mxs_reset_block(rtc_data->io);
+	stmp_reset_block(rtc_data->io);
 	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
 			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
-- 
1.7.9.1



From swarren at wwwdotorg.org  Wed Mar  7 17:31:55 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 07 Mar 2012 15:31:55 -0700
Subject: [PATCH 1/4] pinctrl: introduce generic pin config
In-Reply-To: <1331071509-24661-1-git-send-email-linus.walleij@stericsson.com>
References: <1331071509-24661-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <4F57E1DB.3020605@wwwdotorg.org>

On 03/06/2012 03:05 PM, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This is a split-off from the earlier patch set which adds generic
> pin configuration for the pin controllers that want it. Since
> we may have a system with mixed generic and custom pin controllers,
> we pass a boolean in the pin controller ops vtable to indicate
> if it is generic.
> 
> ChangeLog v1->v5:
> - Follow parent patch versioning number system.
> - Document the semantic meaning of return values from pin config
>   get functions, so we can iterate over pins and check their
>   properties from debugfs as part of the generic config code.
> - Use proper cast functions in the generic debugfs pin config
>   file.
> - Expand generic config to optionally cover groups too.
> ChangeLog v5->v6:
> - Update to match underlying changes.
> 
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

> diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
...
> +/**
> + * enum pin_config_param - possible pin configuration parameters
> + * @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a
> + *     transition from say pull-up to pull-down implies that you disable
> + *     pull-up in the process, this setting disables all biasing.

What's the use-case for that? It seems like if one state's mapping table
entry says:

PIN_CONFIG_BIAS_PULL_UP, value

and another state wants to switch to pull-down, it'd be best to just be
explicit, and say:

PIN_CONFIG_BIAS_PULL_UP, disabled
PIN_CONFIG_BIAS_PULL_DOWN, value

This is somewhat related to my comments on PULL_UP/DOWN below...

> + * @PIN_CONFIG_BIAS_HIGH_IMPEDANCE: the pin will be set to a high impedance
> + *     mode, also know as "third-state" (tristate) or "high-Z" or "floating".
> + *     On output pins this effectively disconnects the pin, which is useful
> + *     if for example some other pin is going to drive the signal connected
> + *     to it for a while. Pins used for input are usually always high
> + *     impedance.

Isn't this the same as DRIVE_OFF?

> + * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
> + *     impedance to VDD), if the controller supports specifying a certain
> + *     pull-up resistance, this is given as an argument (in Ohms) when
> + *     setting this parameter.
> + * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
> + *     impedance to GROUND), if the controller supports specifying a certain
> + *     pull-down resistance, this is given as an argument (in Ohms) when
> + *     setting this parameter.

I don't think its a good idea to combine enabling/disabling features
with configuring values for those features. If an SoC only has on/off
control for pull-up, and the resistance isn't documented, what value
does the driver author guess and require as the value here?

Even when multiple pull-up/down strengths are available, it's quite
plausible they're just documented as "weak" and "strong", and requiring
someone to go find out what the exact values are rather than just using
an enum disabled/enabled,weak=0/enabled,strong=1/ is going to be annoying.

In other words, I think we'd be better off with:

PIN_CONFIG_BIAS_PULL_UP = enabled/disabled 0/1
PIN_CONFIG_BIAS_PULL_DOWN = enabled/disabled 0/1
PIN_CONFIG_PULL_UP_STRENGTH = enumerated value 0..n-1
PIN_CONFIG_PULL_DOWN_STRENGTH = enumerated value 0..n-1

> + * @PIN_CONFIG_BIAS_HIGH: the pin will be wired high, connected to VDD
> + * @PIN_CONFIG_BIAS_GROUND: the pin will be grounded, connected to GROUND

Aren't these special cases of pull-up/down, with nominally zero
resistance? I suppose I could see these having separate control bits
though, so I suppose having explicit PIN_CONFIG_* values is reasonable.

> + * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
> + *     low, this is the most typical case and is typically achieved with two
> + *     active transistors on the output. If the pin can support different
> + *     drive strengths for push/pull, the strength is given in the argument
> + *     as the number of driving stages vs nominal load impedance, so say
> + *     quadruple driving stages (usually 8 transistors rather than two) will
> + *     be configured with the 8 passed as argument.
> + * @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open
> + *     collector) which means it is usually wired with other output ports
> + *     which are then pulled up with an external resistor. If the pin can
> + *     support different drive strengths for the open drain pin, the format
> + *     is the same as for PIN_CONFIG_DRIVE_PUSH_PULL.
> + * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open drain
> + *     (open emitter) which is the same as open drain but pulled to ground.
> + *     If the pin can support different drive strengths for the open drain
> + *     pin, the format is the same as for PIN_CONFIG_DRIVE_PUSH_PULL.
> + * @PIN_CONFIG_DRIVE_OFF: the pin is set to inactive drive mode, off.

Again, I don't think that explicitly documenting the units (# of
transistors) here is helpful. Datasheets may just be written in terms of
weak/normal/strong...

Again, this mixes selection of drive type with configuring that drive
type. For example, on some SoCs, PUSH_PULL might have a different set of
available drive strengths for PUSH and PULL hence need two parameters.
Equally, the parameter for OPEN_DRAIN is the same as for PUSH_PULL, so
why not separate selecting the drive type and setting the drive strength
so that the setting of the drive strength can be shared between the
drive types?

So, I think this should be:

PIN_CONFIG_DRIVE = push_pull/open_drain/open_source/tristate
PIN_CONFIG_DRIVE_STRENGTH_UP = enumerated value 0..n-1
PIN_CONFIG_DRIVE_STRENGTH_DOWN = enumerated value 0..n-1

Note that PIN_CONFIG_SLEW_RATE_* are essentially parameterizations of
the drive type just like drive strength is, and they're already separate
config parameters.

> + * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in
> + *     schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis,
> + *     the threshold value is given on a custom format as argument when
> + *     setting pins to this mode. The argument zero turns the schmitt trigger
> + *     off.
> + * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
> + *     which means it will wait for signals to settle when reading inputs. The
> + *     argument gives the debounce time on a custom format. Setting the
> + *     argument to zero turns debouncing off.

> + * @PIN_CONFIG_SLEW_RATE_RISING: this will configure the slew rate for rising
> + *     signals on the pin. The argument gives the rise time in fractions
> + *     compared to maximum rise time, 0 means nominal rise time. If you can
> + *     control slew rate in 4 steps these will likely be equidistant like
> + *     1/4, 1/2, 3/4 or full nominal slew rate, which means argument 4 gives
> + *     you 1/4 of nominal slew rate and the argument 4 has the same meaning
> + *     as 0 - nominal slew rate (fastest possible, steep edges). You may want
> + *     to adjust slew rates so that signal edges don't get too steep, causing
> + *     disturbances in surrounding electronics known as electromagnetic
> + *     interference (EMI) for example.
> + * @PIN_CONFIG_SLEW_RATE_FALLING: this will configure the slew rate for falling
> + *     signals on the pin. The argument gives the fall time in fractions
> + *     compared to nominal fall time.

The same comment here; I think the value of those two should just be an
enumeration 0..n-1 to avoid documenting specific units.

> + * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
> + *     supplies, the argument to this parameter (on a custom format) tells
> + *     the driver which alternative power source to use.
> + * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
> + *     operation, if several modes of operation are supported these can be
> + *     passed in the argument on a custom form, else just use argument 1
> + *     to indicate low power mode, argument 0 turns low power mode off.

> + * @PIN_CONFIG_WAKEUP: this will configure an input pin such that if a
> + *     signal transition arrives at the pin when the pin controller/system
> + *     is sleeping, it will wake up the system if argument 1 is passed along.
> + *     Pass argument 0 to turn wakeup enablement off.

Is this something that's controlled at the pinmux level? I would have
expected it to be controlled by whatever HW input signals were routed to
- i.e. a GPIO controller could control which GPIO inputs provided
wakeup, or a USB controller would wake if some bus condition was seen
etc. I suppose it's possible that a pin controller itself could wake the
system, but how would the wake reason be mapped to something that could
interpret that? If co-ordination between e.g. the GPIO driver an pinctrl
driver is needed to achieve this, shouldn't the GPIO driver call into
some private API in the pinctrl driver to set this up, similar to how
pinctrl_gpio_direction_input() works?

Still, if there's a specific reason for this I don't see any need to
oppose it; it just seems surprising it'd be needed.

> + * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
> + *     you need to pass in custom configurations to the pin controller, use
> + *     PIN_CONFIG_END+1 as the base offset.
> + */
> +enum pin_config_param {
> +       PIN_CONFIG_BIAS_DISABLE,
> +       PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
> +       PIN_CONFIG_BIAS_PULL_UP,
> +       PIN_CONFIG_BIAS_PULL_DOWN,
> +       PIN_CONFIG_BIAS_HIGH,
> +       PIN_CONFIG_BIAS_GROUND,
> +       PIN_CONFIG_DRIVE_PUSH_PULL,
> +       PIN_CONFIG_DRIVE_OPEN_DRAIN,
> +       PIN_CONFIG_DRIVE_OPEN_SOURCE,
> +       PIN_CONFIG_DRIVE_OFF,
> +       PIN_CONFIG_INPUT_SCHMITT,
> +       PIN_CONFIG_INPUT_DEBOUNCE,
> +       PIN_CONFIG_SLEW_RATE_RISING,
> +       PIN_CONFIG_SLEW_RATE_FALLING,
> +       PIN_CONFIG_POWER_SOURCE,
> +       PIN_CONFIG_LOW_POWER_MODE,
> +       PIN_CONFIG_WAKEUP,
> +       PIN_CONFIG_END,
> +};

I think this should be given a large static value, e.g. 0x8000. That way
the value will never change, and hence the values of custom enumerations
will never change.

That isn't important for mapping tables/... provided by data in the
kernel since a recompile would trivially adapt to changes, but it might
be for device tree; someone might want to represent the raw custom
pin_config_param enumeration values directly in device tree (so they
could read an int from device tree and cast it directly to an enum
pin_config_param without using a lookup table to do the conversion), and
the meanings of values in device tree need to stay static.

Of course, you could argue that drivers parsing DT and creating mapping
tables from it must always do an explicit mapping, in which case having
PIN_CONFIG_END floating is fine.

> +static inline enum pin_config_param to_config_param(unsigned long config)
> +{
> +       return (enum pin_config_param) (config & 0xffffUL);
> +}
> +
> +static inline u16 to_config_argument(unsigned long config)
> +{
> +       return (enum pin_config_param) ((config >> 16) & 0xffffUL);
> +}
> +
> +static inline unsigned long to_config_packed(enum pin_config_param param,
> +                                            u16 argument)
> +{
> +       return (argument << 16) | ((unsigned long) param & 0xffffUL);
> +}

Those function names all have very generic names; shouldn't they be
name-spaced e.g. pinconfig_to_param()/pinconfig_to_argument()?

Shouldn't to_config_packed() either be removed, or rewritten to use
PIN_CONF_PACKED() to remove the duplication?

> +/*
> + * Helpful configuration macro to be used in tables etc.
> + */
> +#define PIN_CONF_PACKED(p, a) ((a << 16) | ((unsigned long) p & 0xffffUL))

> diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c

> +void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
> +                             struct seq_file *s, unsigned pin)
...
> +               /* We want to check out this parameter */
> +               config = to_config_packed(conf_items[i].param, 0);
> +               ret = pin_config_get_for_pin(pctldev, pin, &config);
> +               /* These are legal errors */
> +               if (ret == -EINVAL || ret == -ENOTSUPP)
> +                       continue;

What's the meaning of -EINVAL and -ENOTSUPP in this context? I don't
understand why you'd need two "legal errors" rather than just -ENOTSUPP.

...
> +               seq_puts(s, conf_items[i].display);
> +               /* Print unit if available */
> +               if (conf_items[i].format && to_config_argument(config) != 0)
> +                       seq_printf(s, " (%u %s)", to_config_argument(config),
> +                                  conf_items[i].format);

Wouldn't you always want to dump the value, or if not, wouldn't you only
want to print conf_items[i].display if you're going to print the value too?


From bhelgaas at google.com  Wed Mar  7 17:32:24 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Wed, 07 Mar 2012 15:32:24 -0700
Subject: [PATCH v3 04/34] arm/PCI: remove arch pci_flags definition
In-Reply-To: <20120307222436.25669.52282.stgit@bhelgaas.mtv.corp.google.com>
References: <20120307222436.25669.52282.stgit@bhelgaas.mtv.corp.google.com>
Message-ID: <20120307223224.25669.89103.stgit@bhelgaas.mtv.corp.google.com>

The PCI core provides a pci_flags definition (currently __weak), so drop
the arm definition in favor of that.

arm previously had EXPORT_SYMBOL(pci_flags), but no other architecture does
this, and no modules reference it, so I removed the export.

CC: Rob Herring <rob.herring at calxeda.com>
CC: Russell King <linux at arm.linux.org.uk>
CC: linux-arm-kernel at lists.infradead.org
Signed-off-by: Bjorn Helgaas <bhelgaas at google.com>
---
 arch/arm/kernel/bios32.c |    1 +
 arch/arm/mm/iomap.c      |    3 ---
 2 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index f58ba35..d13b6c2 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -525,6 +525,7 @@ void __init pci_common_init(struct hw_pci *hw)
 
 	INIT_LIST_HEAD(&hw->buses);
 
+	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
 	if (hw->preinit)
 		hw->preinit();
 	pcibios_init_hw(hw);
diff --git a/arch/arm/mm/iomap.c b/arch/arm/mm/iomap.c
index e62956e..4614208 100644
--- a/arch/arm/mm/iomap.c
+++ b/arch/arm/mm/iomap.c
@@ -32,9 +32,6 @@ EXPORT_SYMBOL(pcibios_min_io);
 unsigned long pcibios_min_mem = 0x01000000;
 EXPORT_SYMBOL(pcibios_min_mem);
 
-unsigned int pci_flags = PCI_REASSIGN_ALL_RSRC;
-EXPORT_SYMBOL(pci_flags);
-
 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 {
 	if ((unsigned long)addr >= VMALLOC_START &&



From bhelgaas at google.com  Wed Mar  7 17:32:29 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Wed, 07 Mar 2012 15:32:29 -0700
Subject: [PATCH v3 05/34] arm/PCI: use pci_flags PCI_PROBE_ONLY instead of
 arm-specific flag
In-Reply-To: <20120307222436.25669.52282.stgit@bhelgaas.mtv.corp.google.com>
References: <20120307222436.25669.52282.stgit@bhelgaas.mtv.corp.google.com>
Message-ID: <20120307223229.25669.55000.stgit@bhelgaas.mtv.corp.google.com>

CC: Russell King <linux at arm.linux.org.uk>
CC: linux-arm-kernel at lists.infradead.org
Signed-off-by: Bjorn Helgaas <bhelgaas at google.com>
---
 arch/arm/kernel/bios32.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index d13b6c2..a28c78e 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -16,7 +16,6 @@
 #include <asm/mach/pci.h>
 
 static int debug_pci;
-static int use_firmware;
 
 /*
  * We can't use pci_find_device() here since we are
@@ -537,7 +536,7 @@ void __init pci_common_init(struct hw_pci *hw)
 	list_for_each_entry(sys, &hw->buses, node) {
 		struct pci_bus *bus = sys->bus;
 
-		if (!use_firmware) {
+		if (!pci_has_flag(PCI_PROBE_ONLY)) {
 			/*
 			 * Size the bridge windows.
 			 */
@@ -574,7 +573,7 @@ char * __init pcibios_setup(char *str)
 		debug_pci = 1;
 		return NULL;
 	} else if (!strcmp(str, "firmware")) {
-		use_firmware = 1;
+		pci_add_flags(PCI_PROBE_ONLY);
 		return NULL;
 	}
 	return str;



From swarren at wwwdotorg.org  Wed Mar  7 17:40:18 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 07 Mar 2012 15:40:18 -0700
Subject: [PATCH 3/4] pinctrl: support pinconfig on the U300
In-Reply-To: <1331071533-24789-1-git-send-email-linus.walleij@stericsson.com>
References: <1331071533-24789-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <4F57E3D2.40405@wwwdotorg.org>

On 03/06/2012 03:05 PM, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This adds pin configuration support for the U300 driver pair,
> we can now read out the biasing and drive mode in debugfs and
> configure it using the new configuration API.

> +int u300_pin_config_set(struct pinctrl_dev *pctldev,
> +			unsigned pin,
> +			unsigned long config)
> +{
> +	struct pinctrl_gpio_range *range = u300_match_gpio_range(pin);
> +	int ret;
> +
> +	if (!range)
> +		return -EINVAL;
> +
> +	/* Note: none of these configurations take any argument */
> +	ret = u300_gpio_config_set(range->gc,
> +				   (pin - range->pin_base + range->base),
> +				   to_config_param(config));

I'm a little confused here; the documentation for most of the
PIN_CONFIG_* parameters that this function is passed does explicitly
document that there is an associated argument value. For example,
IN_CONFIG_BIAS_PULL_UP is coupled with the pull up resistance in Ohms.
Shouldn't this code extract the argument and validate that it's a
supported value for the HW?


From festevam at gmail.com  Wed Mar  7 17:40:22 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 7 Mar 2012 19:40:22 -0300
Subject: [PATCH 1/3] drivers: base: add support for stmp-style devices
In-Reply-To: <1331159314-12022-2-git-send-email-w.sang@pengutronix.de>
References: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
 <1331159314-12022-2-git-send-email-w.sang@pengutronix.de>
Message-ID: <CAOMZO5C9EDi_Hy-8=iphr+154gyPgBLnjSVV0seLgi+HoK4zRw@mail.gmail.com>

On Wed, Mar 7, 2012 at 7:28 PM, Wolfram Sang <w.sang at pengutronix.de> wrote:
...
> +static int stmp_clear_poll_bit(void __iomem *addr, u32 mask)
> +{
> + ? ? ? int timeout = 0x400;

Could you please add a proper timeout mechanism here?

Something like: http://patchwork.ozlabs.org/patch/137365/

,as you suggested in the first place ;-)

> +
> + ? ? ? writel(mask, addr + STMP_OFFSET_REG_CLR);
> + ? ? ? udelay(1);
> + ? ? ? while ((readl(addr) & mask) && --timeout)
> + ? ? ? ? ? ? ? /* nothing */;
> +
> + ? ? ? return !timeout;
> +}
> +
> +int stmp_reset_block(void __iomem *reset_addr)
> +{
> + ? ? ? int ret;
> + ? ? ? int timeout = 0x400;

Same here.

Regards,

Fabio Estevam


From swarren at wwwdotorg.org  Wed Mar  7 17:42:55 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 07 Mar 2012 15:42:55 -0700
Subject: [PATCH 4/4] ARM: u300: configure some pins as an example
In-Reply-To: <1331071547-25109-1-git-send-email-linus.walleij@stericsson.com>
References: <1331071547-25109-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <4F57E46F.6050505@wwwdotorg.org>

On 03/06/2012 03:05 PM, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> To show how the pin configuration is used on the U300, let's
> include some configs for two GPIO pins.

> -/* Pinmux settings */
> +static unsigned long g0d_conf[] = {
> +	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
> +};
> +
> +static unsigned long g1d_conf[] = {
> +	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
> +};
> +
> +static unsigned long g0i_conf[] = {
> +	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
> +};
> +
> +static unsigned long g1i_conf[] = {
> +	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
> +};

Those are all the same, so you could just point all the mapping tables
at the same config param array.

> +
> +/* Pin control settings */
>  static struct pinctrl_map __initdata u300_pinmux_map[] = {
>  	/* anonymous maps for chip power and EMIFs */
>  	PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
> @@ -1615,6 +1632,11 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
>  	PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
>  	PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
>  	PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
> +	/* some pin configurations */
> +	PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "GPIO0", g0d_conf),
> +	PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "GPIO1", g1d_conf),
> +	PIN_MAP_CONFIGS_PIN("mmci", "idle", "pinctrl-u300", "GPIO0", g0i_conf),
> +	PIN_MAP_CONFIGS_PIN("mmci", "idle", "pinctrl-u300", "GPIO1", g1i_conf),
>  };

I'd assume though that the default and idle state should have different
pin configurations?

(and if this was stacked on top of your other patch, you could use
PINCTRL_STATE_IDLE instead of "idle" for the last two entries)


From nico at fluxnic.net  Wed Mar  7 17:43:43 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 07 Mar 2012 17:43:43 -0500 (EST)
Subject: [PATCH 2/3] Kbuild: Implement CONFIG_UIMAGE_KERNEL_NOLOAD
In-Reply-To: <20120307213009.GF18787@n2100.arm.linux.org.uk>
References: <1331080238-1524-1-git-send-email-swarren@wwwdotorg.org>
 <1331080238-1524-2-git-send-email-swarren@wwwdotorg.org>
 <20120307180815.GA27213@game.jcrosoft.org> <4F57AB92.6060907@wwwdotorg.org>
 <20120307183633.GB27213@game.jcrosoft.org> <4F57C4C6.2070602@wwwdotorg.org>
 <alpine.LFD.2.02.1203071537130.24151@xanadu.home>
 <20120307213009.GF18787@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.02.1203071644180.24151@xanadu.home>

On Wed, 7 Mar 2012, Russell King - ARM Linux wrote:

> On Wed, Mar 07, 2012 at 04:03:04PM -0500, Nicolas Pitre wrote:
> > Well, I do have a patch series getting rid of ZRELADDR entirely, and 
> > AUTO_ZRELADDR would then become implicit, unless CONFIG_PHYS_OFFSET is 
> > defined.
> 
> Not possible, unless you're goign to also rip out uImage support.

I wish I could.  At least this new "noload" option would make uImage 
compatible with this.  That won't help existing u-Boot installations 
though, which is why I didn't post that patch series yet as I still 
haven't found a good fallback.

> Otherwise, how do we deal with platforms like Versatile Express where
> uboot does a funky relocation of data depending on whether the uImage
> it's loading is for the low 256MB RAM mapping or the high 1GB RAM
> mapping.

Doesn't it use AUTO_ZRELADDR?  With the newer u-Boot, you'd just load 
uImage to whatever address and u-Boot won't mess with it.


Nicolas


From tony at atomide.com  Wed Mar  7 17:44:59 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 14:44:59 -0800
Subject: Latest OMAP4 build errors
In-Reply-To: <CAOesGMiNSyc9F+Wf5pXPG=hRAfnG6aMHtccLBwvekuB3HpyevQ@mail.gmail.com>
References: <20120228090209.GC18045@n2100.arm.linux.org.uk>
 <CAK=WgbZEDr_fYSonBQr3XNcTx5vefsH7LJfqycaxsqg-yechWQ@mail.gmail.com>
 <20120306165545.GB15392@n2100.arm.linux.org.uk>
 <201203061701.54141.arnd@arndb.de>
 <20120307100615.GA17404@n2100.arm.linux.org.uk>
 <20120307171044.GE12083@atomide.com>
 <CAOesGMiNSyc9F+Wf5pXPG=hRAfnG6aMHtccLBwvekuB3HpyevQ@mail.gmail.com>
Message-ID: <20120307224459.GJ12083@atomide.com>

* Olof Johansson <olof at lixom.net> [120307 13:46]:
> On Wed, Mar 7, 2012 at 9:10 AM, Tony Lindgren <tony at atomide.com> wrote:
> >
> > What I got queued up in fixes-non-critical-part2 should fix all those
> > errors and warnings.
> >
> > Arnd & Olof, I've posted one fix that should be applied to arm-soc tree
> > at [1]. I've also posted a request to revert one commit in arm-soc tree
> > at [2].
> >
> > As it seems that you did not apply those to arm-soc, please apply them,
> > or repull the following two branches ASAP:
> 
> Done (repulled the branches). Stephen Rothwell has not surfaced on irc
> yet, so hopefully this means it'll make it into today's linux-next.

Thanks!
 
> > Re-pull fixes-non-critical containing one revert:
> >
> > Revert "ARM: OMAP2+: Fix multiple randconfig errors with SOC_OMAP and SOC_OMAP_NOOP"
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fixes-non-critical
> >
> > Re-pull cleanup again containing one fix:
> >
> > ARM: OMAP2+: Fix L4_EMU_34XX_BASE error after iomap changes
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap cleanup
> >
> > Note that the second one I just pushed, however the patch is known to
> > work for the build errors after merging arm-soc with Russell's changes.
> 
> Looks like you pasted the wrong subject above -- the mail below
> contains the patch that you added though so it looked OK to me (the
> subject above was the previous top-of-branch before you added the last
> one).

Oops, sorry about that. The end result looks right.
 
> > Arnd & Olof, for future, how you want to handle urgent issues like this?
> 
> Personally I missed the requests since they ended up in the chain of
> replies and I didn't notice them, my mistake. A separate email
> requesting pulls or patch application it to arm at kernel.org would
> reduce the risk of that happening (Flagging the subject with [URGENT]
> wouldn't hurt).

OK thanks, will do that next time if there's something urgent.

I'll send a pull request shortly for fixes-non-critical-part2 that
should sort out the remaining issues.

Regards,

Tony


From olof at lixom.net  Wed Mar  7 17:49:19 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 7 Mar 2012 14:49:19 -0800
Subject: [GIT PULL] fix to use static declarations for samsung stuff
In-Reply-To: <201203071215.57828.arnd@arndb.de>
References: <013b01cce7f3$48c87e30$da597a90$%kim@samsung.com>
 <4F574CAE.6030903@samsung.com> <201203071215.57828.arnd@arndb.de>
Message-ID: <CAOesGMgDkWmwVxBRnoOzX-u8FhmXgS_MuLwAigDmGpnXEPwciw@mail.gmail.com>

On Wed, Mar 7, 2012 at 4:15 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 07 March 2012, Kukjin Kim wrote:
>> im wrote:
>> > Hi Russell, Arnd and Olof,
>> >
>> > Please pull following branch which is including fix to use static
>> > declarations for samsung stuff.
>> > ? git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> > next/cleanup-use-static
>> >
>> > I'm not sure it can be sent to upstream for v3.3 but if so, would be better.
>> >
>> Hi Arnd, Olof,
>>
>> I can't see this series in arm-soc yet. If missed, please pull from:
>> ? http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> next/cleanup-use-static
>>
>> As a note, I rebased it on top of arm-soc/depends/rmk/for-armsoc because
>> this touches same points(dma declaration part).
>>
>> If any problems, please kindly let me know.
>>
>
> Sorry, I must have missed this request, I can't remember seeing it before.
> The patches all look good, Olof will take care of getting them in.

Yep, pulled now. Apologies for missing it earlier.


-Olof


From olof at lixom.net  Wed Mar  7 17:56:29 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 7 Mar 2012 14:56:29 -0800
Subject: [PATCH] MAINTAINERS: update my email address
In-Reply-To: <1330995516-22160-1-git-send-email-swarren@nvidia.com>
References: <1330995516-22160-1-git-send-email-swarren@nvidia.com>
Message-ID: <20120307225629.GA24934@quad.lixom.net>

On Mon, Mar 05, 2012 at 05:58:36PM -0700, Stephen Warren wrote:
> From: Stephen Warren <swarren at wwwdotorg.org>
> 
> My nvidia.com address is hosted by MS Exchange Server and isn't suitable
> for receiving patches. Update my MAINTAINERS entry to something that is.
> Note: The old address continues to work, I just want to ensure that I
> receive patches at the new one where possible.
> 
> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>

Thanks, I reworded the subject line and applied directly to the arm-soc
next/maintainers branch.


-Olof


From olof at lixom.net  Wed Mar  7 17:59:05 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 7 Mar 2012 14:59:05 -0800
Subject: [GIT PULL] maintainers file updates for DaVinci
In-Reply-To: <DF0F476B391FA8409C78302C7BA518B6317ECFD3@DBDE01.ent.ti.com>
References: <DF0F476B391FA8409C78302C7BA518B6317ECFD3@DBDE01.ent.ti.com>
Message-ID: <CAOesGMiUt9xUVf-F6B58Sn6EBWegb3Lb8tb76KeCiLk+_PUowA@mail.gmail.com>

Hi,

On Wed, Mar 7, 2012 at 11:02 AM, Nori, Sekhar <nsekhar at ti.com> wrote:
> Hi Arnd, Olof,
>
> Can you please pull the following MAINTAINERS file
> updates for DaVinci for v3.4?

Pulled, thanks.


-Olof


From tony at atomide.com  Wed Mar  7 17:59:46 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 14:59:46 -0800
Subject: [GIT PULL] Urgent pre-emptive fixes for next merge window
Message-ID: <20120307225946.GK12083@atomide.com>

Hi Arnd & Olof,

The following contains fixes for the next merge window.
Included are the issues noted by Russell.

I've tested it against the current next tree with
omap1_defconfig, omap2plus_defconfig, and Russell's
omap3430-ldp and omap4430-sdp seed configs, and the
related allnoconfigs.

One more patch seems to be needed for some .config
files that I've just posted as "[PATCH] ARM: OMAP2+:
Fix build issues with missing include of linux/bug.h".
I'd like to figure out what exactly causes that, so
as soon as that's done, I'll send a pull request for
that.

Please note that arm-soc/for-next and ASoC changes
in next can have minor merge with these fixes.  

I saw the following with today's next tree:

1. These fixes can conflict with some ASoC changes
   using cpu_is_omap4430 that should be replaced with
   cpu_is_omap443x (or cpu_is_omap44xx) to avoid
   breaking build. This series removes cpu_is_omap4430
   as it is broken as noted in the changelog. As an
   earlier patch already fixed an issue in dma.c,
   this series is based on commit d82ba995.

2. For arch/arm/mach-omap2/io.c this series can cause
   a minor conflict with clean-up with the includes.
   This can break build if include "common.h" is
   not kept.

For reference, here's what I resolved with when doing
a test merge against current next tree:

--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@@ -528,20 -485,6 +528,20 @@@ void __init omap4_panda_display_init(vo
  	omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
  }
  
 +static void omap4_panda_init_rev(void)
 +{
- 	if (cpu_is_omap4430()) {
++	if (cpu_is_omap443x()) {
 +		/* PandaBoard 4430 */
 +		/* ASoC audio configuration */
 +		panda_abe_audio_data.card_name = "PandaBoard";
 +		panda_abe_audio_data.has_hsmic = 1;
 +	} else {
 +		/* PandaBoard ES */
 +		/* ASoC audio configuration */
 +		panda_abe_audio_data.card_name = "PandaBoardES";
 +	}
 +}
 +
  static void __init omap4_panda_init(void)
  {
  	int package = OMAP_PACKAGE_CBS;
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@@ -29,18 -30,19 +29,18 @@@
  #include <plat/sram.h>
  #include <plat/sdrc.h>
  #include <plat/serial.h>
 +#include <plat/omap-pm.h>
 +#include <plat/omap_hwmod.h>
 +#include <plat/multi.h>
  
 -#include "clock2xxx.h"
 -#include "clock3xxx.h"
 -#include "clock44xx.h"
 -
 +#include "iomap.h"
+ #include "common.h"
 -#include <plat/omap-pm.h>
  #include "voltage.h"
  #include "powerdomain.h"
 -
  #include "clockdomain.h"
- #include "common.h"
 -#include <plat/omap_hwmod.h>
 -#include <plat/multi.h>
 +#include "clock2xxx.h"
 +#include "clock3xxx.h"
 +#include "clock44xx.h"
  
  /*
   * The machine specific code may provide the extra mapping besides the

And the pull request is below.

Regards,

Tony


The following changes since commit d82ba9954b6b2c4ac91ec6f6f42be8c5215d0619:
  Peter Ujfalusi (1):
        OMAP4: dma: Correct CPU version check for dma_common_ch_end

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fixes-non-critical-part2

Afzal Mohammed (1):
      ARM: OMAP2+: id: Add am33xx SoC type detection

Bernhard Walle (1):
      ARM: OMAP2+: GPMC: Export gpmc_enable_hwecc and gpmc_calculate_ecc

Danny Kukawka (2):
      ARM: OMAP: clock.c: included linux/debugfs.h twice
      ARM: OMAP2+: included some headers twice

Felipe Contreras (1):
      ARM: OMAP: mailbox: trivial whitespace fix

Grazvydas Ignotas (1):
      ARM: omap: pandora: fix usbhs platform data

Ilya Yanok (1):
      ARM: OMAP2+: ads7846_init: put gpio_pendown into pdata if it's provided

Jon Hunter (1):
      ARM: OMAP: Remove definition cpu_is_omap4430()

Kevin Hilman (2):
      ARM: OMAP2+: PM: fix section mismatch with omap2_init_processor_devices()
      ARM: OMAP2+: PM: fix wakeupgen warning when hotplug disabled

Masanari Iida (1):
      ARM: OMAP1: Fix typo in lcd_dma.c

Ohad Ben-Cohen (1):
      ARM: OMAP: don't build hwspinlock in vain

Tarun Kanti DebBarma (1):
      ARM: OMAP: dmtimer: fix missing content/correction in low-power mode support

Tony Lindgren (3):
      ARM: OMAP1: Fix section mismatch for omap1_init_early()
      ARM: OMAP2+: Fix omap24xx_io_desc warning if SoC subtypes are not selected
      ARM: OMAP2: Fix section warning for n8x0 when CONFIG_MMC_OMAP is not set

Vaibhav Bedia (1):
      ARM: OMAP: sram: Add am33xx SRAM support (minimal)

Yuan Jiangli (1):
      ARM: OMAP3+: PM: VP: fix integer truncation error

 arch/arm/mach-omap1/io.c                   |    2 +-
 arch/arm/mach-omap1/lcd_dma.c              |    2 +-
 arch/arm/mach-omap2/Makefile               |    4 ++-
 arch/arm/mach-omap2/board-ldp.c            |    1 -
 arch/arm/mach-omap2/board-n8x0.c           |    8 ++--
 arch/arm/mach-omap2/board-omap3pandora.c   |   10 +++---
 arch/arm/mach-omap2/common-board-devices.c |    8 +++--
 arch/arm/mach-omap2/control.h              |    5 +++
 arch/arm/mach-omap2/gpmc.c                 |    2 +
 arch/arm/mach-omap2/id.c                   |    2 +
 arch/arm/mach-omap2/io.c                   |    3 +-
 arch/arm/mach-omap2/omap-wakeupgen.c       |   53 +++++++++++++++-------------
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    1 -
 arch/arm/mach-omap2/pm.c                   |    2 +-
 arch/arm/mach-omap2/vp.c                   |    4 +-
 arch/arm/plat-omap/clock.c                 |    1 -
 arch/arm/plat-omap/dmtimer.c               |   19 ++++++++--
 arch/arm/plat-omap/include/plat/cpu.h      |    2 -
 arch/arm/plat-omap/include/plat/sram.h     |    1 +
 arch/arm/plat-omap/mailbox.c               |    2 +-
 arch/arm/plat-omap/sram.c                  |   14 ++++++-
 21 files changed, 90 insertions(+), 56 deletions(-)


From timur at freescale.com  Wed Mar  7 18:03:00 2012
From: timur at freescale.com (Timur Tabi)
Date: Wed, 7 Mar 2012 17:03:00 -0600
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <20120307210833.GO3107@opensource.wolfsonmicro.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <4F57CDAC.9030604@freescale.com>
 <20120307210833.GO3107@opensource.wolfsonmicro.com>
Message-ID: <4F57E924.4050208@freescale.com>

Mark Brown wrote:
> Turn on the debug logging in soc-core.c and it'll chatter away about
> what's up; not finding cards is a perfectly normal thing s we're not too
> verbose.

So it turns out there are a couple problems.

1) This patch is missing:

http://patchwork.ozlabs.org/patch/128533/

Our exalted maintainer apparently forgot to apply this patch in a timely
manner for 3.3, so it probably won't make it.  But that's something I'll
just have to deal with.

2) The p1022_ds.c needs the equivalent of this patch:

http://mailman.alsa-project.org/pipermail/alsa-devel/2011-November/046253.html

I have no idea how the P1022DS ever worked, because the WM8776 driver has
always needed the SND_SOC_DAIFMT_Cxx_xxx macro defined.

Apparently, p1022_ds.c needs to set a value for SND_SOC_DAIFMT_INV_MASK.
I tried SND_SOC_DAIFMT_NB_NF, and that seems to work.

Shawn, I'd make the change myself, but I don't want to step on your toes
while doing it.  Do you want to make it yourself?

-- 
Timur Tabi
Linux kernel developer at Freescale



From olof at lixom.net  Wed Mar  7 18:10:23 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 7 Mar 2012 15:10:23 -0800
Subject: [GIT PULL] Urgent pre-emptive fixes for next merge window
In-Reply-To: <20120307225946.GK12083@atomide.com>
References: <20120307225946.GK12083@atomide.com>
Message-ID: <CAOesGMiHU81Y8yiD5rZT5v2SRR419LggUYBB8C_j1Vq2Ge_z6w@mail.gmail.com>

On Wed, Mar 7, 2012 at 2:59 PM, Tony Lindgren <tony at atomide.com> wrote:

> The following changes since commit d82ba9954b6b2c4ac91ec6f6f42be8c5215d0619:
> ?Peter Ujfalusi (1):
> ? ? ? ?OMAP4: dma: Correct CPU version check for dma_common_ch_end
>
> are available in the git repository at:
>
> ?git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fixes-non-critical-part2

Pulled, thanks.

-Olof


From rob.lee at linaro.org  Wed Mar  7 18:12:59 2012
From: rob.lee at linaro.org (Rob Lee)
Date: Wed, 7 Mar 2012 17:12:59 -0600
Subject: [PATCH V6 1/5] ARM: exynos: Add support AFTR mode on EXYNOS4210
In-Reply-To: <CAK44p22LOnJx=bZRfdzAHt7X_snhJGrNoBuXOfsgwBHLLuUziA@mail.gmail.com>
References: <1329805190-8874-1-git-send-email-amit.kachhap@linaro.org>
 <1329805190-8874-2-git-send-email-amit.kachhap@linaro.org>
 <CAMXH7KHTgzY7XZ=4rOxsu-Ra8SRTOsCg=YWOLBD1QDTskRbygw@mail.gmail.com>
 <CAK44p22LOnJx=bZRfdzAHt7X_snhJGrNoBuXOfsgwBHLLuUziA@mail.gmail.com>
Message-ID: <CAMXH7KHtEcg5VSCNFarX9-GuKzWsh3k8Kz+bCu3ZtiqJpvWZZw@mail.gmail.com>

Hello Kukjim and Amit,

Can you tell me the status of this patch?  I based my core cpuidle
consolidation patchset on these changes.  My patchset seems to be
acceptable now and I would like to do a git pull-request for
linux-next, but I see these Exynos cpuidle changes have not yet made
it to linux-next.

Thanks,
Rob


From timur at freescale.com  Wed Mar  7 18:18:31 2012
From: timur at freescale.com (Timur Tabi)
Date: Wed, 7 Mar 2012 17:18:31 -0600
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F57ECC7.1040100@freescale.com>

Shawn Guo wrote:
> Changes since v1:
>  * Address comments from Mark, Timur, and Sascha (Thanks for review).
>  * Drop patches that have been applied by Mark.

I've tested this patchset, and after adding the changes that I pointed out
in my previous email, audio still works on the P1022DS and MPC8610HPCD.

Therefore:

Acked-by: Timur Tabi <timur at freescale.com>

-- 
Timur Tabi
Linux kernel developer at Freescale



From olof at lixom.net  Wed Mar  7 18:24:02 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 7 Mar 2012 15:24:02 -0800
Subject: [GIT PULL] fixing and cleaning up rpmsg/remoteproc for 3.4
In-Reply-To: <CAK=WgbYsZUzTos_sXd+ZayKfPc=sxL7v0Q_==bTMh-_4XiMWiw@mail.gmail.com>
References: <CAK=WgbYsZUzTos_sXd+ZayKfPc=sxL7v0Q_==bTMh-_4XiMWiw@mail.gmail.com>
Message-ID: <CAOesGMgtK76q0KYM0SVMd1GSayUZ6WMOedrh3HM-x+WsXYj6PQ@mail.gmail.com>

On Tue, Mar 6, 2012 at 10:09 AM, Ohad Ben-Cohen <ohad at wizery.com> wrote:
> Hi Arnd,
>
> Please pull:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/ohad/remoteproc.git
> rpmsg-fixes-and-more-for-3.4
>
> To get a few rpmsg/remoteproc fixes, cleanups and some generalization
> work for 3.4.
>
> Again, I should have sent the Kconfig patch earlier in a separate pull
> request. Sorry about that.

Pulled, thanks.


-Olof


From tony at atomide.com  Wed Mar  7 18:26:16 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 15:26:16 -0800
Subject: [GIT PULL] Urgent pre-emptive fixes for next merge window
In-Reply-To: <CAOesGMiHU81Y8yiD5rZT5v2SRR419LggUYBB8C_j1Vq2Ge_z6w@mail.gmail.com>
References: <20120307225946.GK12083@atomide.com>
 <CAOesGMiHU81Y8yiD5rZT5v2SRR419LggUYBB8C_j1Vq2Ge_z6w@mail.gmail.com>
Message-ID: <20120307232615.GL12083@atomide.com>

* Olof Johansson <olof at lixom.net> [120307 14:41]:
> On Wed, Mar 7, 2012 at 2:59 PM, Tony Lindgren <tony at atomide.com> wrote:
> 
> > The following changes since commit d82ba9954b6b2c4ac91ec6f6f42be8c5215d0619:
> > ?Peter Ujfalusi (1):
> > ? ? ? ?OMAP4: dma: Correct CPU version check for dma_common_ch_end
> >
> > are available in the git repository at:
> >
> > ?git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fixes-non-critical-part2
> 
> Pulled, thanks.

Thanks. Once the remoteproc updates are there, things build
even without IOMMU_SUPPORT selected.

So that leaves the include "linux/bug.h" issue and the
ASoC cpu_is_omap4430 issue. I'll let Peter know about the
ASoC issue.

Regards,

Tony


From linux at arm.linux.org.uk  Wed Mar  7 18:43:08 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 7 Mar 2012 23:43:08 +0000
Subject: Latest OMAP4 build errors
In-Reply-To: <20120307224459.GJ12083@atomide.com>
References: <20120228090209.GC18045@n2100.arm.linux.org.uk>
 <CAK=WgbZEDr_fYSonBQr3XNcTx5vefsH7LJfqycaxsqg-yechWQ@mail.gmail.com>
 <20120306165545.GB15392@n2100.arm.linux.org.uk>
 <201203061701.54141.arnd@arndb.de>
 <20120307100615.GA17404@n2100.arm.linux.org.uk>
 <20120307171044.GE12083@atomide.com>
 <CAOesGMiNSyc9F+Wf5pXPG=hRAfnG6aMHtccLBwvekuB3HpyevQ@mail.gmail.com>
 <20120307224459.GJ12083@atomide.com>
Message-ID: <20120307234308.GA20364@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 02:44:59PM -0800, Tony Lindgren wrote:
> OK thanks, will do that next time if there's something urgent.
> 
> I'll send a pull request shortly for fixes-non-critical-part2 that
> should sort out the remaining issues.

FYI, I've just updated the build tree with what's in arm-soc (as of
a couple of minutes ago), which contained a bunch of OMAP updates, so
I'm hopeful that tomorrows results should show an improvement.

It'll start its run in about 2h20.


From bill4carson at gmail.com  Wed Mar  7 19:35:36 2012
From: bill4carson at gmail.com (bill4carson)
Date: Thu, 08 Mar 2012 08:35:36 +0800
Subject: [PATCH 1/7] Add various hugetlb arm high level hooks
In-Reply-To: <20120229153814.GK17745@arm.com>
References: <1329126268-11032-1-git-send-email-bill4carson@gmail.com>
 <1329126268-11032-2-git-send-email-bill4carson@gmail.com>
 <20120229103207.GB17745@arm.com> <4F4E0BDE.6040708@gmail.com>
 <20120229153814.GK17745@arm.com>
Message-ID: <4F57FED8.7050708@gmail.com>



On 2012?02?29? 23:38, Catalin Marinas wrote:
> On Wed, Feb 29, 2012 at 11:28:30AM +0000, bill4carson wrote:
>> On 2012?02?29? 18:32, Catalin Marinas wrote:
>>> On Mon, Feb 13, 2012 at 09:44:22AM +0000, Bill Carson wrote:
>>>> +static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
>>>> +					   unsigned long addr, pte_t *ptep)
>>>> +{
>>>> +	pte_t old_pte = *ptep;
>>>> +	set_huge_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
>>>> +}
>>>
>>> You could use the generic ptep_set_wrprotect()
>>
>> I'm a bit of confused about this.
>>
>> generic ptep_set_wrprotect() can not set huge pte, that's why
>> set_huge_pte_at is used instead here.
>
> Ah, the generic one can only work with with LPAE where set_huge_pte_at()
> is just a set_pte_at(). So this part looks good.
>
Hi, Catalin

Thanks for your time to review PATCH1/7 :)

I'm wondering if reset of this patch set is ok,
I would like to start working on V3 as per your comments.



-- 
I am a slow learner
but I will keep trying to fight for my dreams!

--bill


From jason at lakedaemon.net  Wed Mar  7 15:55:31 2012
From: jason at lakedaemon.net (Jason)
Date: Wed, 7 Mar 2012 15:55:31 -0500
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <20120307200515.GC18513@lunn.ch>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <80fb8cef577eee14364e95009f7a590fd9056ee3.1331090356.git.jason@lakedaemon.net>
 <201203071831.31738.arnd@arndb.de>
 <20120307192723.GE5050@titan.lakedaemon.net>
 <20120307200515.GC18513@lunn.ch>
Message-ID: <20120307205531.GF5050@titan.lakedaemon.net>

On Wed, Mar 07, 2012 at 09:05:15PM +0100, Andrew Lunn wrote:
> On Wed, Mar 07, 2012 at 02:27:23PM -0500, Jason wrote:
> > On Wed, Mar 07, 2012 at 06:31:31PM +0000, Arnd Bergmann wrote:
> > > On Wednesday 07 March 2012, Jason Cooper wrote:
> > > > +       serial at f1012000 {
> > > > +               compatible = "ns16550a";
> > > > +               reg = <0xf1012000 0xff>;
> > > > +               reg-shift = <2>;
> > > > +               interrupts = <33>;
> > > > +               clock-frequency = <200000000>;
> > > > +       };
> > > 
> > > I just noticed that the length here should be inclusive, i.e. 0x100 not 0xff.
> > > This is different from the way we define resources in Linux.
> > 
> > Grrr.  Now I'm getting frustrated.  I'm trying to boot without
> > earlyprintk.  Evidently, something is wrong with the above, because the
> > device boots all the way up (blinky lights come on), but I get no
> > messages after the usual "Uncompressing Linux... done, booting the
> > kernel."
> 
> Hi Jason
> 
> What do you see in /proc/iomem?
> 
> You should expect:
> 
> f1012000-f10120ff : serial8250.0
>   f1012000-f101201f : serial
> f1012100-f10121ff : serial8250.1
>   f1012100-f101211f : serial
> 
> or probably just the first, if your device only has one serial port.
> 
> How about /proc/interrupts?
> 
>  33:        195  orion_irq  serial
> 
> 
> Anything like this in dmesg?
> 
> [   17.189397] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled

> [   17.210023] serial8250.0: ttyS0 at MMIO 0xf1012000 (irq = 33) is a 16550A
> [   17.624748] console [ttyS0] enabled

These two lines ^^^^ are what I'm missing.  Some probe by printk shows
it's getting all the way through tty/serial/8250/8250.c:3263
serial8250_init() okay... then nothing.

> [   17.648555] serial8250.1: ttyS1 at MMIO 0xf1012100 (irq = 34) is a 16550A
> 
> Comparing your system to the above might help you track down which
> property is wrong.
> 
> 	 Andrew


From jason at lakedaemon.net  Wed Mar  7 17:10:12 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 7 Mar 2012 17:10:12 -0500
Subject: [GIT PULL v4] ARM: kirkwood: fdt conversion progress
Message-ID: <20120307221012.GH5050@titan.lakedaemon.net>

The following changes since commit d65b4e98d7ea3038b767b70fe8be959b2913f16d:

  Linux 3.3-rc3 (2012-02-08 19:21:53 -0800)

are available in the git repository at:
  git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt

---
Arnd,

My first two should match up with what you have already, the only
outlier is that Jean-Christophe's patch is needed, but I don't think
everyone agrees on it yet.

thx,

Jason.

Andrew Lunn (2):
      ARM: orion: spi: remove enable_clock_fix which is not used
      ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data.

Jason Cooper (10):
      ARM: kirkwood: add dreamplug (fdt) support.
      ARM: kirkwood: convert uart0 to devicetree.
      ARM: kirkwood: fdt: use mrvl ticker symbol
      ARM: kirkwood: fdt: absorb kirkwood_init()
      ARM: kirkwood: add interrupt controller to devicetree.
      ARM: kirkwood: rtc-mv devicetree bindings
      ARM: kirkwood: use devicetree for rtc-mv
      ARM: kirkwood: mv_cesa devicetree support.
      ARM: kirkwood: use devicetree for orion-ehci
      ARM: kirkwood: use devicetree to init sata_mv

Jean-Christophe PLAGNIOL-VILLARD (1):
      of: add dma-mask binding

Michael Walle (3):
      ARM: kirkwood: mv_cesa devicetree bindings
      ARM: kirkwood: ehci-orion: add device tree binding
      ARM: kirkwood: sata_mv: add device tree binding

 .../devicetree/bindings/crypto/mv_cesa.txt         |   18 ++
 .../devicetree/bindings/usb/ehci-orion.txt         |    5 +
 arch/arm/boot/dts/kirkwood-dreamplug.dts           |   41 ++++
 arch/arm/boot/dts/kirkwood.dtsi                    |   26 +++
 arch/arm/mach-kirkwood/Kconfig                     |   14 ++
 arch/arm/mach-kirkwood/Makefile                    |    1 +
 arch/arm/mach-kirkwood/Makefile.boot               |    2 +
 arch/arm/mach-kirkwood/board-dt.c                  |  206 ++++++++++++++++++++
 arch/arm/mach-kirkwood/common.c                    |   41 ++++-
 arch/arm/mach-kirkwood/common.h                    |    6 +
 arch/arm/plat-orion/include/plat/audio.h           |    1 -
 drivers/ata/sata_mv.c                              |   18 ++-
 drivers/crypto/mv_cesa.c                           |   13 ++
 drivers/of/platform.c                              |   26 +++-
 drivers/rtc/rtc-mv.c                               |    9 +
 drivers/spi/spi-orion.c                            |    5 -
 drivers/usb/host/ehci-orion.c                      |   50 +++++-
 include/linux/spi/orion_spi.h                      |    1 -
 18 files changed, 464 insertions(+), 19 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/crypto/mv_cesa.txt
 create mode 100644 Documentation/devicetree/bindings/usb/ehci-orion.txt
 create mode 100644 arch/arm/boot/dts/kirkwood-dreamplug.dts
 create mode 100644 arch/arm/boot/dts/kirkwood.dtsi
 create mode 100644 arch/arm/mach-kirkwood/board-dt.c



From tony at atomide.com  Wed Mar  7 19:45:59 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 16:45:59 -0800
Subject: [PATCH] ARM: OMAP2+: Fix build issues with missing include of
 linux/bug.h
In-Reply-To: <20120307213209.GI12083@atomide.com>
References: <20120307213209.GI12083@atomide.com>
Message-ID: <20120308004559.GN12083@atomide.com>

* Tony Lindgren <tony at atomide.com> [120307 13:04]:
> 
> Looks like this is needed for some .config files with
> current for-next

This is because of next/master commit 6c03438ed (kernel.h: doesn't
explicitly use bug.h, so don't include it). Will update the commit
message to say:

Otherwise we can get the following if bug.h is not included from kernel.h:

> arch/arm/mach-omap2/powerdomain-common.c:
> In function 'omap2_pwrdm_get_mem_bank_onstate_mask':
> arch/arm/mach-omap2/powerdomain-common.c:64:3: error:
> implicit declaration of function 'WARN_ON' [-Werror=implicit-function-declaration]
> cc1: some warnings being treated as errors
>
> Signed-off-by: Tony Lindgren <tony at atomide.com>

 
> --- a/arch/arm/mach-omap2/clkt_clksel.c
> +++ b/arch/arm/mach-omap2/clkt_clksel.c
> @@ -43,6 +43,7 @@
>  #include <linux/errno.h>
>  #include <linux/clk.h>
>  #include <linux/io.h>
> +#include <linux/bug.h>
>  
>  #include <plat/clock.h>
>  
> --- a/arch/arm/mach-omap2/powerdomain-common.c
> +++ b/arch/arm/mach-omap2/powerdomain-common.c
> @@ -13,6 +13,7 @@
>  
>  #include <linux/errno.h>
>  #include <linux/kernel.h>
> +#include <linux/bug.h>
>  #include "pm.h"
>  #include "cm.h"
>  #include "cm-regbits-34xx.h"
> --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
> +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
> @@ -15,6 +15,7 @@
>  #include <linux/io.h>
>  #include <linux/errno.h>
>  #include <linux/delay.h>
> +#include <linux/bug.h>
>  
>  #include <plat/prcm.h>
>  
> --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
> +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
> @@ -13,6 +13,7 @@
>  
>  #include <linux/kernel.h>
>  #include <linux/init.h>
> +#include <linux/bug.h>
>  
>  #include <plat/cpu.h>
>  
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From jason at lakedaemon.net  Wed Mar  7 16:29:24 2012
From: jason at lakedaemon.net (Jason)
Date: Wed, 7 Mar 2012 16:29:24 -0500
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <201203072113.04369.arnd@arndb.de>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203071831.31738.arnd@arndb.de>
 <20120307192723.GE5050@titan.lakedaemon.net>
 <201203072113.04369.arnd@arndb.de>
Message-ID: <20120307212924.GG5050@titan.lakedaemon.net>

On Wed, Mar 07, 2012 at 09:13:04PM +0000, Arnd Bergmann wrote:
> On Wednesday 07 March 2012, Jason wrote:
> > Grrr.  Now I'm getting frustrated.  I'm trying to boot without
> > earlyprintk.  Evidently, something is wrong with the above, because the
> > device boots all the way up (blinky lights come on), but I get no
> > messages after the usual "Uncompressing Linux... done, booting the
> > kernel."
> > 
> > Here's my most recent attempt:
> > 
> >         serial at f1012000 {
> >                 device_type = "serial";
> >                 compatible = "ns16550a";
> >                 reg = <0xf1012000 0x100>; /*phys addr*/
> >                 virt-reg = <0xfed12000>;  /*virt addr*/
> >                 reg-shift = <2>;
> >                 reg-io-width = <1>;
> >                 interrupts = <33>;
> >                 current-speed = <115200>;
> >                 interrupt-parent = <&intc>;
> >                 clock-frequency = <200000000>;
> >         };
> > 
> > I've looked at what is done in the powerpc dt's, but, no luck.  When
> > earlyprintk is enabled, I see no error messages, just:
> > 
> > bootconsole [earlycon0] enabled
> > debug: skip boot console de-registration.
> > ...
> > Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
> > 
> > Any pointers?

> The of_serial driver (you did enable that one in Kconfig, right?)

Wow.  I can't believe I missed that.  I now get:

Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
f1012000.serial: ttyS0 at MMIO 0xf1012000 (irq = 33) is a 16550A
console [ttyS0] enabled

without earlyprintk.

Thanks, Arnd.

Jason.

PS - the only change from your code is the 0x100.  I'm going to do some
more testing...


From tony at atomide.com  Wed Mar  7 20:28:01 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 17:28:01 -0800
Subject: [PATCH v2] ARM: OMAP2+: Fix build issues with missing include of
 linux/bug.h
Message-ID: <20120308012801.GO12083@atomide.com>

Otherwise we can get the following if bug.h is not included from kernel.h:

arch/arm/mach-omap2/powerdomain-common.c:
In function 'omap2_pwrdm_get_mem_bank_onstate_mask':
arch/arm/mach-omap2/powerdomain-common.c:64:3: error:
implicit declaration of function 'WARN_ON' [-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors

Signed-off-by: Tony Lindgren <tony at atomide.com>

diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index e25364d..04d551b 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -43,6 +43,7 @@
 #include <linux/errno.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/bug.h>
 
 #include <plat/clock.h>
 
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index f97afff..c0aeabf 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -13,6 +13,7 @@
 
 #include <linux/errno.h>
 #include <linux/kernel.h>
+#include <linux/bug.h>
 #include "pm.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
index 6a17e4c..0f0a9f1 100644
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/bug.h>
 
 #include <plat/prcm.h>
 
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 8ef26da..b7ea468 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -13,6 +13,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/bug.h>
 
 #include <plat/cpu.h>
 


From olof at lixom.net  Wed Mar  7 20:31:19 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 7 Mar 2012 17:31:19 -0800
Subject: [PATCH v2] ARM: OMAP2+: Fix build issues with missing include of
 linux/bug.h
In-Reply-To: <20120308012801.GO12083@atomide.com>
References: <20120308012801.GO12083@atomide.com>
Message-ID: <CAOesGMi3tf7_q1hwOXMGQBLW2EugDcUfH0yL=sgOtwBpYM7xjQ@mail.gmail.com>

On Wed, Mar 7, 2012 at 5:28 PM, Tony Lindgren <tony at atomide.com> wrote:
> Otherwise we can get the following if bug.h is not included from kernel.h:
>
> arch/arm/mach-omap2/powerdomain-common.c:
> In function 'omap2_pwrdm_get_mem_bank_onstate_mask':
> arch/arm/mach-omap2/powerdomain-common.c:64:3: error:
> implicit declaration of function 'WARN_ON' [-Werror=implicit-function-declaration]
> cc1: some warnings being treated as errors
>
> Signed-off-by: Tony Lindgren <tony at atomide.com>

Applied to next/fixes-non-critical. Thanks!


-Olof


From tony at atomide.com  Wed Mar  7 20:32:16 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 17:32:16 -0800
Subject: [PATCH v2] ARM: OMAP2+: Fix build issues with missing include
 of linux/bug.h
In-Reply-To: <CAOesGMi3tf7_q1hwOXMGQBLW2EugDcUfH0yL=sgOtwBpYM7xjQ@mail.gmail.com>
References: <20120308012801.GO12083@atomide.com>
 <CAOesGMi3tf7_q1hwOXMGQBLW2EugDcUfH0yL=sgOtwBpYM7xjQ@mail.gmail.com>
Message-ID: <20120308013216.GP12083@atomide.com>

* Olof Johansson <olof at lixom.net> [120307 16:59]:
> On Wed, Mar 7, 2012 at 5:28 PM, Tony Lindgren <tony at atomide.com> wrote:
> > Otherwise we can get the following if bug.h is not included from kernel.h:
> >
> > arch/arm/mach-omap2/powerdomain-common.c:
> > In function 'omap2_pwrdm_get_mem_bank_onstate_mask':
> > arch/arm/mach-omap2/powerdomain-common.c:64:3: error:
> > implicit declaration of function 'WARN_ON' [-Werror=implicit-function-declaration]
> > cc1: some warnings being treated as errors
> >
> > Signed-off-by: Tony Lindgren <tony at atomide.com>
> 
> Applied to next/fixes-non-critical. Thanks!

Thanks a lot!

Tony


From b32955 at freescale.com  Wed Mar  7 21:09:10 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 8 Mar 2012 10:09:10 +0800
Subject: [PATCH 1/3] drivers: base: add support for stmp-style devices
In-Reply-To: <1331159314-12022-2-git-send-email-w.sang@pengutronix.de>
References: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
 <1331159314-12022-2-git-send-email-w.sang@pengutronix.de>
Message-ID: <4F5814C6.1080801@freescale.com>

? 2012?03?08? 06:28, Wolfram Sang ??:
> All this is strictly speaking not mach-specific (but IP core specific) and,
> thus, doesn't need to be in mach-mxs/include. At least mx6 also uses IP cores
> following this stmp-style. So:
>
mx50 also uses the same IP core.

BR
Huang Shijie



From tony at atomide.com  Wed Mar  7 21:18:43 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 18:18:43 -0800
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators
 for v3.4
In-Reply-To: <877gywjhht.fsf@ti.com>
References: <877gywjhht.fsf@ti.com>
Message-ID: <20120308021843.GQ12083@atomide.com>

* Kevin Hilman <khilman at ti.com> [120307 11:42]:
> Tony,
> 
> Please pull the following support for using regulators to control the
> on-chip VC/VP managed voltage domains.
> 
> The regulator driver support for this is already queued in the regulator
> tree, and this is the supporting core work.
> 
> This combined with the CPUfreq changes to use the regulator framework
> will finally result in MPU DVFS working in mainline.

Nice.. However this one might be missing some header changes?

I'm getting the following:

arch/arm/mach-omap2/twl-common.c:174:15: error: variable 'omap3_vdd1_drvdata' has initializer but incomplete type
arch/arm/mach-omap2/twl-common.c:175:2: error: unknown field 'get_voltage' specified in initializer
arch/arm/mach-omap2/twl-common.c:175:2: warning: excess elements in struct initializer [enabled by default]
arch/arm/mach-omap2/twl-common.c:175:2: warning: (near initialization for 'omap3_vdd1_drvdata') [enabled by default]
arch/arm/mach-omap2/twl-common.c:176:2: error: unknown field 'set_voltage' specified in initializer
arch/arm/mach-omap2/twl-common.c:176:2: warning: excess elements in struct initializer [enabled by default]
arch/arm/mach-omap2/twl-common.c:176:2: warning: (near initialization for 'omap3_vdd1_drvdata') [enabled by default]
arch/arm/mach-omap2/twl-common.c:179:15: error: variable 'omap3_vdd2_drvdata' has initializer but incomplete type
arch/arm/mach-omap2/twl-common.c:180:2: error: unknown field 'get_voltage' specified in initializer
arch/arm/mach-omap2/twl-common.c:180:2: warning: excess elements in struct initializer [enabled by default]
arch/arm/mach-omap2/twl-common.c:180:2: warning: (near initialization for 'omap3_vdd2_drvdata') [enabled by default]
arch/arm/mach-omap2/twl-common.c:181:2: error: unknown field 'set_voltage' specified in initializer
arch/arm/mach-omap2/twl-common.c:181:2: warning: excess elements in struct initializer [enabled by default]
arch/arm/mach-omap2/twl-common.c:181:2: warning: (near initialization for 'omap3_vdd2_drvdata') [enabled by default]
arch/arm/mach-omap2/twl-common.c: In function 'omap3_pmic_get_config':
arch/arm/mach-omap2/twl-common.c:193:3: error: invalid use of undefined type 'struct twl_regulator_driver_data'
arch/arm/mach-omap2/twl-common.c:198:3: error: invalid use of undefined type 'struct twl_regulator_driver_data'
arch/arm/mach-omap2/twl-common.c: At top level:
arch/arm/mach-omap2/twl-common.c:400:15: error: variable 'omap4_vdd1_drvdata' has initializer but incomplete type
arch/arm/mach-omap2/twl-common.c:401:2: error: unknown field 'get_voltage' specified in initializer
arch/arm/mach-omap2/twl-common.c:401:2: warning: excess elements in struct initializer [enabled by default]
arch/arm/mach-omap2/twl-common.c:401:2: warning: (near initialization for 'omap4_vdd1_drvdata') [enabled by default]
arch/arm/mach-omap2/twl-common.c:402:2: error: unknown field 'set_voltage' specified in initializer
arch/arm/mach-omap2/twl-common.c:402:2: warning: excess elements in struct initializer [enabled by default]
arch/arm/mach-omap2/twl-common.c:402:2: warning: (near initialization for 'omap4_vdd1_drvdata') [enabled by default]
arch/arm/mach-omap2/twl-common.c:405:15: error: variable 'omap4_vdd2_drvdata' has initializer but incomplete type
arch/arm/mach-omap2/twl-common.c:406:2: error: unknown field 'get_voltage' specified in initializer
arch/arm/mach-omap2/twl-common.c:406:2: warning: excess elements in struct initializer [enabled by default]
arch/arm/mach-omap2/twl-common.c:406:2: warning: (near initialization for 'omap4_vdd2_drvdata') [enabled by default]
arch/arm/mach-omap2/twl-common.c:407:2: error: unknown field 'set_voltage' specified in initializer
arch/arm/mach-omap2/twl-common.c:407:2: warning: excess elements in struct initializer [enabled by default]
arch/arm/mach-omap2/twl-common.c:407:2: warning: (near initialization for 'omap4_vdd2_drvdata') [enabled by default]
arch/arm/mach-omap2/twl-common.c:410:15: error: variable 'omap4_vdd3_drvdata' has initializer but incomplete type
arch/arm/mach-omap2/twl-common.c:411:2: error: unknown field 'get_voltage' specified in initializer
arch/arm/mach-omap2/twl-common.c:411:2: warning: excess elements in struct initializer [enabled by default]
arch/arm/mach-omap2/twl-common.c:411:2: warning: (near initialization for 'omap4_vdd3_drvdata') [enabled by default]
arch/arm/mach-omap2/twl-common.c:412:2: error: unknown field 'set_voltage' specified in initializer
arch/arm/mach-omap2/twl-common.c:412:2: warning: excess elements in struct initializer [enabled by default]
arch/arm/mach-omap2/twl-common.c:412:2: warning: (near initialization for 'omap4_vdd3_drvdata') [enabled by default]
arch/arm/mach-omap2/twl-common.c: In function 'omap4_pmic_get_config':
arch/arm/mach-omap2/twl-common.c:425:3: error: invalid use of undefined type 'struct twl_regulator_driver_data'
arch/arm/mach-omap2/twl-common.c:431:3: error: invalid use of undefined type 'struct twl_regulator_driver_data'
arch/arm/mach-omap2/twl-common.c:435:16: error: 'struct twl4030_platform_data' has no member named 'vdd3'
arch/arm/mach-omap2/twl-common.c:437:3: error: invalid use of undefined type 'struct twl_regulator_driver_data'
arch/arm/mach-omap2/twl-common.c:438:12: error: 'struct twl4030_platform_data' has no member named 'vdd3'

Regards,

Tony


From paul at pwsan.com  Wed Mar  7 21:38:36 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 07 Mar 2012 19:38:36 -0700
Subject: [PATCH 06/12] ARM: OMAP: hwmod: remove code support for direct hwmod
 registration
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <20120308023834.8205.55023.stgit@dusk>

Now that the data has been converted to use interface registration, we
can remove the (now unused) direct hwmod registration code.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c             |  124 +++++++-------------------
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    7 -
 2 files changed, 33 insertions(+), 98 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index edbeefa..f3d264a 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -173,12 +173,6 @@ static LIST_HEAD(omap_hwmod_list);
 static struct omap_hwmod *mpu_oh;
 
 /*
- * link_registration: set to true if hwmod interfaces are being registered
- * directly; set to false if hwmods are being registered directly
- */
-static bool link_registration;
-
-/*
  * linkspace: ptr to a buffer that struct omap_hwmod_link records are
  * allocated from - used to reduce the number of small memory
  * allocations, which has a significant impact on performance
@@ -195,32 +189,22 @@ static unsigned short free_ls, max_ls, ls_supp;
 /* Private functions */
 
 /**
- * _fetch_next_ocp_if - return next OCP interface in an array or list
+ * _fetch_next_ocp_if - return the next OCP interface in a list
  * @p: ptr to a ptr to the list_head inside the ocp_if to return
- * @old: ptr to an array of struct omap_hwmod_ocp_if records
- * @i: pointer to the index into the @old array
- *
- * Return a pointer to the next struct omap_hwmod_ocp_if record in a
- * sequence.  If hwmods are being registered directly, then return a
- * struct omap_hwmod_ocp_if record corresponding to the element index
- * pointed to by @i in the
- * @old array.  Otherwise, return a pointer to the struct
- * omap_hwmod_ocp_if record containing the struct list_head record pointed
- * to by @p, and set the pointer pointed to by @p to point to the next
- * struct list_head record in the list.
+ * @i: pointer to the index of the element pointed to by @p in the list
+ *
+ * Return a pointer to the struct omap_hwmod_ocp_if record
+ * containing the struct list_head pointed to by @p, and increment
+ * @p such that a future call to this routine will return the next
+ * record.
  */
 static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p,
-						    struct omap_hwmod_ocp_if **old,
 						    int *i)
 {
 	struct omap_hwmod_ocp_if *oi;
 
-	if (!link_registration) {
-		oi = old[*i];
-	} else {
-		oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if;
-		*p = (*p)->next;
-	}
+	oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if;
+	*p = (*p)->next;
 
 	*i = *i + 1;
 
@@ -642,16 +626,15 @@ static int _init_main_clk(struct omap_hwmod *oh)
 static int _init_interface_clks(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os;
-	struct list_head *p = NULL;
+	struct list_head *p;
 	struct clk *c;
 	int i = 0;
 	int ret = 0;
 
-	if (link_registration)
-		p = oh->slave_ports.next;
+	p = oh->slave_ports.next;
 
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, &i);
 		if (!os->clk)
 			continue;
 
@@ -704,7 +687,7 @@ static int _init_opt_clks(struct omap_hwmod *oh)
 static int _enable_clocks(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os;
-	struct list_head *p = NULL;
+	struct list_head *p;
 	int i = 0;
 
 	pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
@@ -712,11 +695,10 @@ static int _enable_clocks(struct omap_hwmod *oh)
 	if (oh->_clk)
 		clk_enable(oh->_clk);
 
-	if (link_registration)
-		p = oh->slave_ports.next;
+	p = oh->slave_ports.next;
 
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, &i);
 
 		if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
 			clk_enable(os->_clk);
@@ -736,7 +718,7 @@ static int _enable_clocks(struct omap_hwmod *oh)
 static int _disable_clocks(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os;
-	struct list_head *p = NULL;
+	struct list_head *p;
 	int i = 0;
 
 	pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
@@ -744,11 +726,10 @@ static int _disable_clocks(struct omap_hwmod *oh)
 	if (oh->_clk)
 		clk_disable(oh->_clk);
 
-	if (link_registration)
-		p = oh->slave_ports.next;
+	p = oh->slave_ports.next;
 
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, &i);
 
 		if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
 			clk_disable(os->_clk);
@@ -1062,12 +1043,11 @@ static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
 	struct list_head *p = NULL;
 	bool found = false;
 
-	if (link_registration)
-		p = oh->slave_ports.next;
+	p = oh->slave_ports.next;
 
 	i = 0;
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, &i);
 
 		if (!os->addr)
 			return -ENOENT;
@@ -1107,7 +1087,7 @@ static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
 static void __init _save_mpu_port_index(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os = NULL;
-	struct list_head *p = NULL;
+	struct list_head *p;
 	int i = 0;
 
 	if (!oh)
@@ -1115,14 +1095,12 @@ static void __init _save_mpu_port_index(struct omap_hwmod *oh)
 
 	oh->_int_flags |= _HWMOD_NO_MPU_PORT;
 
-	if (link_registration)
-		p = oh->slave_ports.next;
+	p = oh->slave_ports.next;
 
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, &i);
 		if (os->user & OCP_USER_MPU) {
 			oh->_mpu_port = os;
-			oh->_mpu_port_index = i - 1;
 			oh->_int_flags &= ~_HWMOD_NO_MPU_PORT;
 			break;
 		}
@@ -1149,10 +1127,7 @@ static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
 	if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
 		return NULL;
 
-	if (!link_registration)
-		return oh->slaves[oh->_mpu_port_index];
-	else
-		return oh->_mpu_port;
+	return oh->_mpu_port;
 };
 
 /**
@@ -2033,16 +2008,15 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
 static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os;
-	struct list_head *p = NULL;
+	struct list_head *p;
 	int i = 0;
 	if (oh->_state != _HWMOD_STATE_INITIALIZED)
 		return;
 
-	if (link_registration)
-		p = oh->slave_ports.next;
+	p = oh->slave_ports.next;
 
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, &i);
 		if (!os->_clk)
 			continue;
 
@@ -2546,34 +2520,6 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
 }
 
 /**
- * omap_hwmod_register - register an array of hwmods
- * @ohs: pointer to an array of omap_hwmods to register
- *
- * Intended to be called early in boot before the clock framework is
- * initialized.  If @ohs is not null, will register all omap_hwmods
- * listed in @ohs that are valid for this chip.  Returns 0.
- */
-int __init omap_hwmod_register(struct omap_hwmod **ohs)
-{
-	int r, i;
-
-	if (link_registration)
-		return -EINVAL;
-
-	if (!ohs)
-		return 0;
-
-	i = 0;
-	do {
-		r = _register(ohs[i]);
-		WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
-		     r);
-	} while (ohs[++i]);
-
-	return 0;
-}
-
-/**
  * omap_hwmod_register_links - register an array of hwmod links
  * @ois: pointer to an array of omap_hwmod_ocp_if to register
  *
@@ -2588,8 +2534,6 @@ int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
 	if (!ois)
 		return 0;
 
-	link_registration = true;
-
 	if (!linkspace) {
 		if (_alloc_linkspace(ois)) {
 			pr_err("omap_hwmod: could not allocate link space\n");
@@ -2850,17 +2794,16 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
 int omap_hwmod_count_resources(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os;
-	struct list_head *p = NULL;
+	struct list_head *p;
 	int ret;
 	int i = 0;
 
 	ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
 
-	if (link_registration)
-		p = oh->slave_ports.next;
+	p = oh->slave_ports.next;
 
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, &i);
 		ret += _count_ocp_if_addr_spaces(os);
 	}
 
@@ -2880,7 +2823,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 {
 	struct omap_hwmod_ocp_if *os;
-	struct list_head *p = NULL;
+	struct list_head *p;
 	int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt;
 	int r = 0;
 
@@ -2904,12 +2847,11 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 		r++;
 	}
 
-	if (link_registration)
-		p = oh->slave_ports.next;
+	p = oh->slave_ports.next;
 
 	i = 0;
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, &i);
 		addr_cnt = _count_ocp_if_addr_spaces(os);
 
 		for (j = 0; j < addr_cnt; j++) {
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 66c4a30..8c39f70 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -505,12 +505,9 @@ struct omap_hwmod_link {
  * @opt_clks: other device clocks that drivers can request (0..*)
  * @vdd_name: voltage domain name
  * @voltdm: pointer to voltage domain (filled in at runtime)
- * @masters: ptr to array of OCP ifs that this hwmod can initiate on
- * @slaves: ptr to array of OCP ifs that this hwmod can respond on
  * @dev_attr: arbitrary device attributes that can be passed to the driver
  * @_sysc_cache: internal-use hwmod flags
  * @_mpu_rt_va: cached register target start address (internal use)
- * @_mpu_port_index: cached MPU register target slave ID (internal use)
  * @_mpu_port: cached MPU register target slave (internal use)
  * @opt_clks_cnt: number of @opt_clks
  * @master_cnt: number of @master entries
@@ -551,8 +548,6 @@ struct omap_hwmod {
 	char				*clkdm_name;
 	struct clockdomain		*clkdm;
 	char				*vdd_name;
-	struct omap_hwmod_ocp_if	**masters; /* connect to *_IA */
-	struct omap_hwmod_ocp_if	**slaves;  /* connect to *_TA */
 	struct list_head		master_ports; /* connect to *_IA */
 	struct list_head		slave_ports; /* connect to *_TA */
 	void				*dev_attr;
@@ -562,7 +557,6 @@ struct omap_hwmod {
 	struct list_head		node;
 	struct omap_hwmod_ocp_if	*_mpu_port;
 	u16				flags;
-	u8				_mpu_port_index;
 	u8				response_lat;
 	u8				rst_lines_cnt;
 	u8				opt_clks_cnt;
@@ -574,7 +568,6 @@ struct omap_hwmod {
 	u8				_postsetup_state;
 };
 
-int omap_hwmod_register(struct omap_hwmod **ohs);
 struct omap_hwmod *omap_hwmod_lookup(const char *name);
 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
 			void *data);




From paul at pwsan.com  Wed Mar  7 21:38:23 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 07 Mar 2012 19:38:23 -0700
Subject: [PATCH 01/12] ARM: OMAP2+: hwmod: add _find_mpu_rt_port()
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <20120308023821.8205.21191.stgit@dusk>

Most IP blocks on the OMAP SoC have an interconnect link that is
intended to be used by the MPU to communicate with the IP block.
Several parts of the hwmod code need to be able to identify this link.
Currently, this is open-coded.  However, future patches will change
the way that interconnect links are represented and will make
identifying the link more complex.  So to avoid code duplication, this
patch centralizes the MPU port link identification code into a new
function, _find_mpu_rt_port().

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   39 ++++++++++++++++++++++++++++----------
 1 files changed, 29 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 3462dc5..503047a 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1061,6 +1061,27 @@ static int __init _find_mpu_port_index(struct omap_hwmod *oh)
 }
 
 /**
+ * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU
+ * @oh: struct omap_hwmod *
+ *
+ * Given a pointer to a struct omap_hwmod record @oh, return a pointer
+ * to the struct omap_hwmod_ocp_if record that is used by the MPU to
+ * communicate with the IP block.  This interface need not be directly
+ * connected to the MPU (and almost certainly is not), but is directly
+ * connected to the IP block represented by @oh.  Returns a pointer
+ * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon
+ * error or if there does not appear to be a path from the MPU to this
+ * IP block.
+ */
+static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
+{
+	if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
+		return NULL;
+
+	return oh->slaves[oh->_mpu_port_index];
+};
+
+/**
  * _find_mpu_rt_addr_space - return MPU register target address space for @oh
  * @oh: struct omap_hwmod *
  *
@@ -1073,10 +1094,7 @@ static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap
 	struct omap_hwmod_addr_space *mem;
 	int found = 0, i = 0;
 
-	if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
-		return NULL;
-
-	os = oh->slaves[oh->_mpu_port_index];
+	os = _find_mpu_rt_port(oh);
 	if (!os->addr)
 		return NULL;
 
@@ -1334,12 +1352,11 @@ static int _wait_target_ready(struct omap_hwmod *oh)
 	if (!oh)
 		return -EINVAL;
 
-	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+	if (oh->flags & HWMOD_NO_IDLEST)
 		return 0;
 
-	os = oh->slaves[oh->_mpu_port_index];
-
-	if (oh->flags & HWMOD_NO_IDLEST)
+	os = _find_mpu_rt_port(oh);
+	if (!os)
 		return 0;
 
 	/* XXX check module SIDLEMODE */
@@ -2709,6 +2726,7 @@ int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
 struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
 {
 	struct clk *c;
+	struct omap_hwmod_ocp_if *oi;
 
 	if (!oh)
 		return NULL;
@@ -2716,9 +2734,10 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
 	if (oh->_clk) {
 		c = oh->_clk;
 	} else {
-		if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+		oi = _find_mpu_rt_port(oh);
+		if (!oi)
 			return NULL;
-		c = oh->slaves[oh->_mpu_port_index]->_clk;
+		c = oi->_clk;
 	}
 
 	if (!c->clkdm)




From paul at pwsan.com  Wed Mar  7 21:38:25 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 07 Mar 2012 19:38:25 -0700
Subject: [PATCH 03/12] ARM: OMAP2+: hwmod: consolidate finding the MPU port
 index and storing it
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <20120308023824.8205.11522.stgit@dusk>

An IP block's MPU interface port only needs to be found once.  The result
can be cached to speed further lookups.  This patch consolidates these
two steps into a single function.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   39 +++++++++++++++-----------------------
 1 files changed, 15 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 96a03d7..3c733a8 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1044,37 +1044,34 @@ static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
 }
 
 /**
- * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
+ * _save_mpu_port_index - find and save the index to @oh's MPU port
  * @oh: struct omap_hwmod *
  *
- * Returns the array index of the OCP slave port that the MPU
- * addresses the device on, or -EINVAL upon error or not found.
+ * Determines the array index of the OCP slave port that the MPU uses
+ * to address the device, and saves it into the struct omap_hwmod.
+ * Intended to be called during hwmod registration only. No return
+ * value.
  */
-static int __init _find_mpu_port_index(struct omap_hwmod *oh)
+static void __init _save_mpu_port_index(struct omap_hwmod *oh)
 {
-	struct omap_hwmod_ocp_if *os;
+	struct omap_hwmod_ocp_if *os = NULL;
 	int i = 0;
-	int found = 0;
 
 	if (!oh)
-		return -EINVAL;
+		return;
+
+	oh->_int_flags |= _HWMOD_NO_MPU_PORT;
 
 	while (i < oh->slaves_cnt) {
 		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
 		if (os->user & OCP_USER_MPU) {
-			found = 1;
+			oh->_mpu_port_index = i - 1;
+			oh->_int_flags &= ~_HWMOD_NO_MPU_PORT;
 			break;
 		}
 	}
 
-	if (found)
-		pr_debug("omap_hwmod: %s: MPU OCP slave port ID  %d\n",
-			 oh->name, i - 1);
-	else
-		pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
-			 oh->name);
-
-	return (found) ? (i - 1) : -EINVAL;
+	return;
 }
 
 /**
@@ -1112,7 +1109,7 @@ static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap
 	int found = 0, i = 0;
 
 	os = _find_mpu_rt_port(oh);
-	if (!os->addr)
+	if (!os || !os->addr)
 		return NULL;
 
 	do {
@@ -2175,8 +2172,6 @@ static int __init _setup(struct omap_hwmod *oh, void *n)
  */
 static int __init _register(struct omap_hwmod *oh)
 {
-	int ms_id;
-
 	if (!oh || !oh->name || !oh->class || !oh->class->name ||
 	    (oh->_state != _HWMOD_STATE_UNKNOWN))
 		return -EINVAL;
@@ -2186,11 +2181,7 @@ static int __init _register(struct omap_hwmod *oh)
 	if (_lookup(oh->name))
 		return -EEXIST;
 
-	ms_id = _find_mpu_port_index(oh);
-	if (!IS_ERR_VALUE(ms_id))
-		oh->_mpu_port_index = ms_id;
-	else
-		oh->_int_flags |= _HWMOD_NO_MPU_PORT;
+	_save_mpu_port_index(oh);
 
 	list_add_tail(&oh->node, &omap_hwmod_list);
 




From paul at pwsan.com  Wed Mar  7 21:38:40 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 07 Mar 2012 19:38:40 -0700
Subject: [PATCH 11/12] ARM: OMAP3: hwmod data: add IVA hard reset lines,
 main clock, clockdomain
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <20120308023839.8205.19425.stgit@dusk>

The IVA hwmod data is missing some fields that cause the following
warning on boot:

[    0.118011] omap_hwmod: iva: cannot be enabled for reset (3)

Fix by encoding the IP block's main functional clock, reset lines, and
clockdomain.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index c05a445..1bf1888 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -98,9 +98,19 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
 };
 
 /* IVA2 (IVA2) */
+static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
+	{ .name = "logic", .rst_shift = 0 },
+	{ .name = "seq0", .rst_shift = 1 },
+	{ .name = "seq1", .rst_shift = 2 },
+};
+
 static struct omap_hwmod omap3xxx_iva_hwmod = {
 	.name		= "iva",
 	.class		= &iva_hwmod_class,
+	.clkdm_name	= "iva2_clkdm",
+	.rst_lines	= omap3xxx_iva_resets,
+	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_iva_resets),
+	.main_clk	= "iva2_ck",
 };
 
 /* timer class */




From paul at pwsan.com  Wed Mar  7 21:38:24 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 07 Mar 2012 19:38:24 -0700
Subject: [PATCH 02/12] ARM: OMAP2+: hwmod: add function to iterate over struct
 omap_hwmod_ocp_if
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <20120308023823.8205.84120.stgit@dusk>

To reduce the number of lines of data in the OMAP portion of the Linux
code base, subsequent patches will remove the lists of hwmod
interconnect links from the static hwmod data.  These lists will be
built dynamically during boot.  To ease this transition, this patch
centralizes the way that interconnect links are iterated into a single
function, _fetch_next_ocp_if().

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |  115 ++++++++++++++++++++++----------------
 1 files changed, 67 insertions(+), 48 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 503047a..96a03d7 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -169,6 +169,29 @@ static struct omap_hwmod *mpu_oh;
 /* Private functions */
 
 /**
+ * _fetch_next_ocp_if - return @i'th OCP interface in an array
+ * @p: ptr to a ptr to the list_head inside the ocp_if to return (not yet used)
+ * @old: ptr to an array of struct omap_hwmod_ocp_if records
+ * @i: pointer to the index into the @old array
+ *
+ * Return a pointer to the next struct omap_hwmod_ocp_if record in a
+ * sequence.  Currently returns a struct omap_hwmod_ocp_if record
+ * corresponding to the element index pointed to by @i in the @old
+ * array, and increments the index pointed to by @i.
+ */
+static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p,
+						    struct omap_hwmod_ocp_if **old,
+						    int *i)
+{
+	struct omap_hwmod_ocp_if *oi;
+
+	oi = old[*i];
+	*i = *i + 1;
+
+	return oi;
+}
+
+/**
  * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
  * @oh: struct omap_hwmod *
  *
@@ -582,16 +605,13 @@ static int _init_main_clk(struct omap_hwmod *oh)
  */
 static int _init_interface_clks(struct omap_hwmod *oh)
 {
+	struct omap_hwmod_ocp_if *os;
 	struct clk *c;
-	int i;
+	int i = 0;
 	int ret = 0;
 
-	if (oh->slaves_cnt == 0)
-		return 0;
-
-	for (i = 0; i < oh->slaves_cnt; i++) {
-		struct omap_hwmod_ocp_if *os = oh->slaves[i];
-
+	while (i < oh->slaves_cnt) {
+		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
 		if (!os->clk)
 			continue;
 
@@ -643,21 +663,19 @@ static int _init_opt_clks(struct omap_hwmod *oh)
  */
 static int _enable_clocks(struct omap_hwmod *oh)
 {
-	int i;
+	struct omap_hwmod_ocp_if *os;
+	int i = 0;
 
 	pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
 
 	if (oh->_clk)
 		clk_enable(oh->_clk);
 
-	if (oh->slaves_cnt > 0) {
-		for (i = 0; i < oh->slaves_cnt; i++) {
-			struct omap_hwmod_ocp_if *os = oh->slaves[i];
-			struct clk *c = os->_clk;
+	while (i < oh->slaves_cnt) {
+		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
 
-			if (c && (os->flags & OCPIF_SWSUP_IDLE))
-				clk_enable(c);
-		}
+		if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
+			clk_enable(os->_clk);
 	}
 
 	/* The opt clocks are controlled by the device driver. */
@@ -673,21 +691,19 @@ static int _enable_clocks(struct omap_hwmod *oh)
  */
 static int _disable_clocks(struct omap_hwmod *oh)
 {
-	int i;
+	struct omap_hwmod_ocp_if *os;
+	int i = 0;
 
 	pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
 
 	if (oh->_clk)
 		clk_disable(oh->_clk);
 
-	if (oh->slaves_cnt > 0) {
-		for (i = 0; i < oh->slaves_cnt; i++) {
-			struct omap_hwmod_ocp_if *os = oh->slaves[i];
-			struct clk *c = os->_clk;
+	while (i < oh->slaves_cnt) {
+		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
 
-			if (c && (os->flags & OCPIF_SWSUP_IDLE))
-				clk_disable(c);
-		}
+		if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
+			clk_disable(os->_clk);
 	}
 
 	/* The opt clocks are controlled by the device driver. */
@@ -997,8 +1013,9 @@ static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
 	struct omap_hwmod_ocp_if *os;
 	bool found = false;
 
-	for (i = 0; i < oh->slaves_cnt; i++) {
-		os = oh->slaves[i];
+	i = 0;
+	while (i < oh->slaves_cnt) {
+		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
 
 		if (!os->addr)
 			return -ENOENT;
@@ -1035,15 +1052,15 @@ static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
  */
 static int __init _find_mpu_port_index(struct omap_hwmod *oh)
 {
-	int i;
+	struct omap_hwmod_ocp_if *os;
+	int i = 0;
 	int found = 0;
 
-	if (!oh || oh->slaves_cnt == 0)
+	if (!oh)
 		return -EINVAL;
 
-	for (i = 0; i < oh->slaves_cnt; i++) {
-		struct omap_hwmod_ocp_if *os = oh->slaves[i];
-
+	while (i < oh->slaves_cnt) {
+		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
 		if (os->user & OCP_USER_MPU) {
 			found = 1;
 			break;
@@ -1052,12 +1069,12 @@ static int __init _find_mpu_port_index(struct omap_hwmod *oh)
 
 	if (found)
 		pr_debug("omap_hwmod: %s: MPU OCP slave port ID  %d\n",
-			 oh->name, i);
+			 oh->name, i - 1);
 	else
 		pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
 			 oh->name);
 
-	return (found) ? i : -EINVAL;
+	return (found) ? (i - 1) : -EINVAL;
 }
 
 /**
@@ -1956,23 +1973,22 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
  */
 static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
 {
-	int i;
-
+	struct omap_hwmod_ocp_if *os;
+	int i = 0;
 	if (oh->_state != _HWMOD_STATE_INITIALIZED)
 		return;
 
-	for (i = 0; i < oh->slaves_cnt; i++) {
-		struct omap_hwmod_ocp_if *os = oh->slaves[i];
-		struct clk *c = os->_clk;
 
-		if (!c)
+	while (i < oh->slaves_cnt) {
+		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
+		if (!os->_clk)
 			continue;
 
 		if (os->flags & OCPIF_SWSUP_IDLE) {
 			/* XXX omap_iclk_deny_idle(c); */
 		} else {
 			/* XXX omap_iclk_allow_idle(c); */
-			clk_enable(c);
+			clk_enable(os->_clk);
 		}
 	}
 
@@ -2585,12 +2601,16 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
  */
 int omap_hwmod_count_resources(struct omap_hwmod *oh)
 {
-	int ret, i;
+	struct omap_hwmod_ocp_if *os;
+	int ret;
+	int i = 0;
 
 	ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
 
-	for (i = 0; i < oh->slaves_cnt; i++)
-		ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
+	while (i < oh->slaves_cnt) {
+		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
+		ret += _count_ocp_if_addr_spaces(os);
+	}
 
 	return ret;
 }
@@ -2607,7 +2627,8 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
  */
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 {
-	int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
+	struct omap_hwmod_ocp_if *os;
+	int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt;
 	int r = 0;
 
 	/* For each IRQ, DMA, memory area, fill in array.*/
@@ -2630,11 +2651,9 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 		r++;
 	}
 
-	for (i = 0; i < oh->slaves_cnt; i++) {
-		struct omap_hwmod_ocp_if *os;
-		int addr_cnt;
-
-		os = oh->slaves[i];
+	i = 0;
+	while (i < oh->slaves_cnt) {
+		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
 		addr_cnt = _count_ocp_if_addr_spaces(os);
 
 		for (j = 0; j < addr_cnt; j++) {




From paul at pwsan.com  Wed Mar  7 21:38:41 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 07 Mar 2012 19:38:41 -0700
Subject: [PATCH 12/12] ARM: OMAP2xxx: hwmod data: start to fix the IVA1,
 IVA2 and DSP
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <20120308023840.8205.51532.stgit@dusk>

N800 logs this message on boot:

[    0.182281] omap_hwmod: iva: cannot be enabled for reset (3)

Fix by creating basic IVA1 and DSP hwmods for OMAP2420, and a basic IVA2
hwmod for OMAP2430.  There is still more information to be added, but
this should resolve the immediate issue.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |   46 ++++++++++++++++++++++++++--
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |   11 ++++++-
 2 files changed, 53 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b01b66a..2c087ff 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -43,10 +43,41 @@
  * IP blocks
  */
 
-/* IVA2 (IVA2) */
+/* IVA1 (IVA1) */
+static struct omap_hwmod_class iva1_hwmod_class = {
+	.name		= "iva1",
+};
+
+static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
+	{ .name = "iva", .rst_shift = 8 },
+};
+
 static struct omap_hwmod omap2420_iva_hwmod = {
 	.name		= "iva",
-	.class		= &iva_hwmod_class,
+	.class		= &iva1_hwmod_class,
+	.clkdm_name	= "iva1_clkdm",
+	.rst_lines	= omap2420_iva_resets,
+	.rst_lines_cnt	= ARRAY_SIZE(omap2420_iva_resets),
+	.main_clk	= "iva1_ifck",
+};
+
+/* DSP */
+static struct omap_hwmod_class dsp_hwmod_class = {
+	.name		= "dsp",
+};
+
+static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
+	{ .name = "logic", .rst_shift = 0 },
+	{ .name = "mmu", .rst_shift = 1 },
+};
+
+static struct omap_hwmod omap2420_dsp_hwmod = {
+	.name		= "dsp",
+	.class		= &dsp_hwmod_class,
+	.clkdm_name	= "dsp_clkdm",
+	.rst_lines	= omap2420_dsp_resets,
+	.rst_lines_cnt	= ARRAY_SIZE(omap2420_dsp_resets),
+	.main_clk	= "dsp_fck",
 };
 
 /* I2C common */
@@ -234,7 +265,15 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 	.master		= &omap2xxx_l3_main_hwmod,
 	.slave		= &omap2420_iva_hwmod,
-	.clk		= "iva1_ifck",
+	.clk		= "core_l3_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* DSP <- L3 interface */
+static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
+	.master		= &omap2xxx_l3_main_hwmod,
+	.slave		= &omap2420_dsp_hwmod,
+	.clk		= "dsp_ick",
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -402,6 +441,7 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 	&omap2420_l4_core__i2c1,
 	&omap2420_l4_core__i2c2,
 	&omap2420_l3__iva,
+	&omap2420_l3__dsp,
 	&omap2420_l4_wkup__timer1,
 	&omap2xxx_l4_core__timer2,
 	&omap2xxx_l4_core__timer3,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 23ca551..b359bfb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -45,9 +45,18 @@
  */
 
 /* IVA2 (IVA2) */
+static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
+	{ .name = "logic", .rst_shift = 0 },
+	{ .name = "mmu", .rst_shift = 1 },
+};
+
 static struct omap_hwmod omap2430_iva_hwmod = {
 	.name		= "iva",
 	.class		= &iva_hwmod_class,
+	.clkdm_name	= "dsp_clkdm",
+	.rst_lines	= omap2430_iva_resets,
+	.rst_lines_cnt	= ARRAY_SIZE(omap2430_iva_resets),
+	.main_clk	= "dsp_fck",
 };
 
 /* I2C common */
@@ -599,7 +608,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 	.master		= &omap2xxx_l3_main_hwmod,
 	.slave		= &omap2430_iva_hwmod,
-	.clk		= "dsp_fck",
+	.clk		= "core_l3_ick",
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 




From paul at pwsan.com  Wed Mar  7 21:38:21 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 07 Mar 2012 19:38:21 -0700
Subject: [PATCH 00/12] ARM: OMAP2+: hwmod: remove link arrays
Message-ID: <20120308023614.8205.78768.stgit@dusk>

The hwmod code and data format was originally designed to minimize
boot time and for autogenerated data files.  Compactness was traded
for precomputation.  Now that the emphasis is on reducing the number
of lines in the OMAP source tree, this trade can be reversed.

This series removes the precomputed "link arrays" from the hwmod data,
and converts the code to register IP blocks by their interconnects,
rather than directly.  This results in a significant reduction in
lines of source, at the cost of some additional boot time.  The change
also makes it easier to share more IP block data across SoCs.

This series has a dependency on the 'hwmod_data_cleanup_3.4' branch
posted earlier.

This series is also available via git://git.pwsan.com/linux-2.6 in the
"hwmod_remove_link_arrays_cleanup_3.4" branch.  

Boot-tested on N800.  Boot and suspend-tested on OMAP35xx Beagleboard
and OMAP44xx Pandaboard.


- Paul

---

hwmod_remove_link_arrays_cleanup_3.4
   text	   data	    bss	    dec	    hex	filename
3831449	 297100	5382832	9511381	 9121d5	vmlinux.omap2plus_defconfig.orig
3832257	 297708	5382864	9512829	 91277d	vmlinux.omap2plus_defconfig


Paul Walmsley (12):
      ARM: OMAP2+: hwmod: add _find_mpu_rt_port()
      ARM: OMAP2+: hwmod: add function to iterate over struct omap_hwmod_ocp_if
      ARM: OMAP2+: hwmod: consolidate finding the MPU port index and storing it
      ARM: OMAP2+: hwmod: add support for link registration
      ARM: OMAP2+: hwmod data: convert to link registration
      ARM: OMAP: hwmod: remove code support for direct hwmod registration
      ARM: OMAP2+: hwmod data: remove forward declarations, reorganize
      ARM: OMAP2xxx: hwmod data: share common hwmods between OMAP2420 and OMAP2430
      ARM: OMAP2xxx: hwmod data: share common interface data
      ARM: OMAP3: hwmod data: fix IVA interface clock
      ARM: OMAP3: hwmod data: add IVA hard reset lines, main clock, clockdomain
      ARM: OMAP2xxx: hwmod data: start to fix the IVA1, IVA2 and DSP


 arch/arm/mach-omap2/omap_hwmod.c                   |  410 +-
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         | 1563 +-----
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         | 2316 ++-------
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c |  266 +
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |  562 ++
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         | 5047 +++++++++-----------
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         | 4882 ++++++++-----------
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |   71 
 arch/arm/plat-omap/include/plat/omap_hwmod.h       |   31 
 9 files changed, 6324 insertions(+), 8824 deletions(-)



From paul at pwsan.com  Wed Mar  7 21:38:33 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 07 Mar 2012 19:38:33 -0700
Subject: [PATCH 04/12] ARM: OMAP2+: hwmod: add support for link registration
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <20120308023825.8205.87940.stgit@dusk>

Add support for direct IP block interconnect ("link") registration to
the hwmod code via a new function, omap_hwmod_register_links().  This
will replace direct registration of hwmods, and a subsequent patch
will remove omap_hwmod_register().

This change will allow a subsequent patch to remove the hwmod data
link arrays.  This will reduce the size of the hwmod static data and
also make it easier to generate the data files.  It will also make it
possible to share some of the struct omap_hwmod records across
multiple SoCs, since the link array pointers will be removed from the
struct omap_hwmod.

The downside is that boot time will increase.  Minimizing boot time
was the reason why the link arrays were originally introduced.
Removing them will require extra computation during boot to allocate
memory and associate IP blocks with their interconnects.  However,
since the current kernel development focus is on reducing the number
of lines in arch/arm/mach-omap2/, boot time impact is now seemingly
considered a lower priority.

This patch contains additional complexity to reduce the number of
memory allocations required for this change.  This reduces the boot
time impact: total hwmod link registration time was ~ 2655
microseconds with a simple allocation strategy, but is now ~ 549
microseconds[1] with the approach taken by this patch.

1. Measured on a BeagleBoard 35xx @ 500MHz MPU/333 MHz CORE, average
   of 7 samples.  Total uncertainty is +/- 61 microseconds.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c             |  297 +++++++++++++++++++++++++-
 arch/arm/plat-omap/include/plat/omap_hwmod.h |   24 ++
 2 files changed, 305 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 3c733a8..edbeefa 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -137,6 +137,7 @@
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
 #include <linux/slab.h>
+#include <linux/bootmem.h>
 
 #include "common.h"
 #include <plat/cpu.h>
@@ -159,25 +160,54 @@
 /* Name of the OMAP hwmod for the MPU */
 #define MPU_INITIATOR_NAME		"mpu"
 
+/*
+ * Number of struct omap_hwmod_link records per struct
+ * omap_hwmod_ocp_if record (master->slave and slave->master)
+ */
+#define LINKS_PER_OCP_IF		2
+
 /* omap_hwmod_list contains all registered struct omap_hwmods */
 static LIST_HEAD(omap_hwmod_list);
 
 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
 static struct omap_hwmod *mpu_oh;
 
+/*
+ * link_registration: set to true if hwmod interfaces are being registered
+ * directly; set to false if hwmods are being registered directly
+ */
+static bool link_registration;
+
+/*
+ * linkspace: ptr to a buffer that struct omap_hwmod_link records are
+ * allocated from - used to reduce the number of small memory
+ * allocations, which has a significant impact on performance
+ */
+static struct omap_hwmod_link *linkspace;
+
+/*
+ * free_ls, max_ls: array indexes into linkspace; representing the
+ * next free struct omap_hwmod_link index, and the maximum number of
+ * struct omap_hwmod_link records allocated (respectively)
+ */
+static unsigned short free_ls, max_ls, ls_supp;
 
 /* Private functions */
 
 /**
- * _fetch_next_ocp_if - return @i'th OCP interface in an array
- * @p: ptr to a ptr to the list_head inside the ocp_if to return (not yet used)
+ * _fetch_next_ocp_if - return next OCP interface in an array or list
+ * @p: ptr to a ptr to the list_head inside the ocp_if to return
  * @old: ptr to an array of struct omap_hwmod_ocp_if records
  * @i: pointer to the index into the @old array
  *
  * Return a pointer to the next struct omap_hwmod_ocp_if record in a
- * sequence.  Currently returns a struct omap_hwmod_ocp_if record
- * corresponding to the element index pointed to by @i in the @old
- * array, and increments the index pointed to by @i.
+ * sequence.  If hwmods are being registered directly, then return a
+ * struct omap_hwmod_ocp_if record corresponding to the element index
+ * pointed to by @i in the
+ * @old array.  Otherwise, return a pointer to the struct
+ * omap_hwmod_ocp_if record containing the struct list_head record pointed
+ * to by @p, and set the pointer pointed to by @p to point to the next
+ * struct list_head record in the list.
  */
 static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p,
 						    struct omap_hwmod_ocp_if **old,
@@ -185,7 +215,13 @@ static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p,
 {
 	struct omap_hwmod_ocp_if *oi;
 
-	oi = old[*i];
+	if (!link_registration) {
+		oi = old[*i];
+	} else {
+		oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if;
+		*p = (*p)->next;
+	}
+
 	*i = *i + 1;
 
 	return oi;
@@ -606,12 +642,16 @@ static int _init_main_clk(struct omap_hwmod *oh)
 static int _init_interface_clks(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os;
+	struct list_head *p = NULL;
 	struct clk *c;
 	int i = 0;
 	int ret = 0;
 
+	if (link_registration)
+		p = oh->slave_ports.next;
+
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
 		if (!os->clk)
 			continue;
 
@@ -664,6 +704,7 @@ static int _init_opt_clks(struct omap_hwmod *oh)
 static int _enable_clocks(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os;
+	struct list_head *p = NULL;
 	int i = 0;
 
 	pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
@@ -671,8 +712,11 @@ static int _enable_clocks(struct omap_hwmod *oh)
 	if (oh->_clk)
 		clk_enable(oh->_clk);
 
+	if (link_registration)
+		p = oh->slave_ports.next;
+
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
 
 		if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
 			clk_enable(os->_clk);
@@ -692,6 +736,7 @@ static int _enable_clocks(struct omap_hwmod *oh)
 static int _disable_clocks(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os;
+	struct list_head *p = NULL;
 	int i = 0;
 
 	pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
@@ -699,8 +744,11 @@ static int _disable_clocks(struct omap_hwmod *oh)
 	if (oh->_clk)
 		clk_disable(oh->_clk);
 
+	if (link_registration)
+		p = oh->slave_ports.next;
+
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
 
 		if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
 			clk_disable(os->_clk);
@@ -1011,8 +1059,12 @@ static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
 {
 	int i, j;
 	struct omap_hwmod_ocp_if *os;
+	struct list_head *p = NULL;
 	bool found = false;
 
+	if (link_registration)
+		p = oh->slave_ports.next;
+
 	i = 0;
 	while (i < oh->slaves_cnt) {
 		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
@@ -1055,6 +1107,7 @@ static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
 static void __init _save_mpu_port_index(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os = NULL;
+	struct list_head *p = NULL;
 	int i = 0;
 
 	if (!oh)
@@ -1062,9 +1115,13 @@ static void __init _save_mpu_port_index(struct omap_hwmod *oh)
 
 	oh->_int_flags |= _HWMOD_NO_MPU_PORT;
 
+	if (link_registration)
+		p = oh->slave_ports.next;
+
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
 		if (os->user & OCP_USER_MPU) {
+			oh->_mpu_port = os;
 			oh->_mpu_port_index = i - 1;
 			oh->_int_flags &= ~_HWMOD_NO_MPU_PORT;
 			break;
@@ -1092,7 +1149,10 @@ static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
 	if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
 		return NULL;
 
-	return oh->slaves[oh->_mpu_port_index];
+	if (!link_registration)
+		return oh->slaves[oh->_mpu_port_index];
+	else
+		return oh->_mpu_port;
 };
 
 /**
@@ -1938,6 +1998,8 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
 	if (!oh)
 		return;
 
+	_save_mpu_port_index(oh);
+
 	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
 		return;
 
@@ -1971,13 +2033,16 @@ static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
 static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os;
+	struct list_head *p = NULL;
 	int i = 0;
 	if (oh->_state != _HWMOD_STATE_INITIALIZED)
 		return;
 
+	if (link_registration)
+		p = oh->slave_ports.next;
 
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
 		if (!os->_clk)
 			continue;
 
@@ -2181,10 +2246,10 @@ static int __init _register(struct omap_hwmod *oh)
 	if (_lookup(oh->name))
 		return -EEXIST;
 
-	_save_mpu_port_index(oh);
-
 	list_add_tail(&oh->node, &omap_hwmod_list);
 
+	INIT_LIST_HEAD(&oh->master_ports);
+	INIT_LIST_HEAD(&oh->slave_ports);
 	spin_lock_init(&oh->_lock);
 
 	oh->_state = _HWMOD_STATE_REGISTERED;
@@ -2199,6 +2264,160 @@ static int __init _register(struct omap_hwmod *oh)
 	return 0;
 }
 
+/**
+ * _alloc_links - return allocated memory for hwmod links
+ * @ml: pointer to a struct omap_hwmod_link * for the master link
+ * @sl: pointer to a struct omap_hwmod_link * for the slave link
+ *
+ * Return pointers to two struct omap_hwmod_link records, via the
+ * addresses pointed to by @ml and @sl.  Will first attempt to return
+ * memory allocated as part of a large initial block, but if that has
+ * been exhausted, will allocate memory itself.  Since ideally this
+ * second allocation path will never occur, the number of these
+ * 'supplemental' allocations will be logged when debugging is
+ * enabled.  Returns 0.
+ */
+static int __init _alloc_links(struct omap_hwmod_link **ml,
+			       struct omap_hwmod_link **sl)
+{
+	unsigned int sz;
+
+	if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) {
+		*ml = &linkspace[free_ls++];
+		*sl = &linkspace[free_ls++];
+		return 0;
+	}
+
+	sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF;
+
+	*sl = NULL;
+	*ml = alloc_bootmem(sz);
+
+	memset(*ml, 0, sz);
+
+	*sl = (void *)(*ml) + sizeof(struct omap_hwmod_link);
+
+	ls_supp++;
+	pr_debug("omap_hwmod: supplemental link allocations needed: %d\n",
+		 ls_supp * LINKS_PER_OCP_IF);
+
+	return 0;
+};
+
+/**
+ * _add_link - add an interconnect between two IP blocks
+ * @oi: pointer to a struct omap_hwmod_ocp_if record
+ *
+ * Add struct omap_hwmod_link records connecting the master IP block
+ * specified in @oi->master to @oi, and connecting the slave IP block
+ * specified in @oi->slave to @oi.  This code is assumed to run before
+ * preemption or SMP has been enabled, thus avoiding the need for
+ * locking in this code.  Changes to this assumption will require
+ * additional locking.  Returns 0.
+ */
+static int __init _add_link(struct omap_hwmod_ocp_if *oi)
+{
+	struct omap_hwmod_link *ml, *sl;
+
+	pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name,
+		 oi->slave->name);
+
+	_alloc_links(&ml, &sl);
+
+	ml->ocp_if = oi;
+	INIT_LIST_HEAD(&ml->node);
+	list_add(&ml->node, &oi->master->master_ports);
+	oi->master->masters_cnt++;
+
+	sl->ocp_if = oi;
+	INIT_LIST_HEAD(&sl->node);
+	list_add(&sl->node, &oi->slave->slave_ports);
+	oi->slave->slaves_cnt++;
+
+	return 0;
+}
+
+/**
+ * _register_link - register a struct omap_hwmod_ocp_if
+ * @oi: struct omap_hwmod_ocp_if *
+ *
+ * Registers the omap_hwmod_ocp_if record @oi.  Returns -EEXIST if it
+ * has already been registered; -EINVAL if @oi is NULL or if the
+ * record pointed to by @oi is missing required fields; or 0 upon
+ * success.
+ *
+ * XXX The data should be copied into bootmem, so the original data
+ * should be marked __initdata and freed after init.  This would allow
+ * unneeded omap_hwmods to be freed on multi-OMAP configurations.
+ */
+static int __init _register_link(struct omap_hwmod_ocp_if *oi)
+{
+	if (!oi || !oi->master || !oi->slave || !oi->user)
+		return -EINVAL;
+
+	if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED)
+		return -EEXIST;
+
+	pr_debug("omap_hwmod: registering link from %s to %s\n",
+		 oi->master->name, oi->slave->name);
+
+	/*
+	 * Register the connected hwmods, if they haven't been
+	 * registered already
+	 */
+	if (oi->master->_state != _HWMOD_STATE_REGISTERED)
+		_register(oi->master);
+
+	if (oi->slave->_state != _HWMOD_STATE_REGISTERED)
+		_register(oi->slave);
+
+	_add_link(oi);
+
+	oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED;
+
+	return 0;
+}
+
+/**
+ * _alloc_linkspace - allocate large block of hwmod links
+ * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count
+ *
+ * Allocate a large block of struct omap_hwmod_link records.  This
+ * improves boot time significantly by avoiding the need to allocate
+ * individual records one by one.  If the number of records to
+ * allocate in the block hasn't been manually specified, this function
+ * will count the number of struct omap_hwmod_ocp_if records in @ois
+ * and use that to determine the allocation size.  For SoC families
+ * that require multiple list registrations, such as OMAP3xxx, this
+ * estimation process isn't optimal, so manual estimation is advised
+ * in those cases.  Returns -EEXIST if the allocation has already occurred
+ * or 0 upon success.
+ */
+static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
+{
+	unsigned int i = 0;
+	unsigned int sz;
+
+	if (linkspace) {
+		WARN(1, "linkspace already allocated\n");
+		return -EEXIST;
+	}
+
+	if (max_ls == 0)
+		while (ois[i++])
+			max_ls += LINKS_PER_OCP_IF;
+
+	sz = sizeof(struct omap_hwmod_link) * max_ls;
+
+	pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n",
+		 __func__, sz, max_ls);
+
+	linkspace = alloc_bootmem(sz);
+
+	memset(linkspace, 0, sz);
+
+	return 0;
+}
 
 /* Public functions */
 
@@ -2338,6 +2557,9 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs)
 {
 	int r, i;
 
+	if (link_registration)
+		return -EINVAL;
+
 	if (!ohs)
 		return 0;
 
@@ -2352,6 +2574,41 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs)
 }
 
 /**
+ * omap_hwmod_register_links - register an array of hwmod links
+ * @ois: pointer to an array of omap_hwmod_ocp_if to register
+ *
+ * Intended to be called early in boot before the clock framework is
+ * initialized.  If @ois is not null, will register all omap_hwmods
+ * listed in @ois that are valid for this chip.  Returns 0.
+ */
+int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
+{
+	int r, i;
+
+	if (!ois)
+		return 0;
+
+	link_registration = true;
+
+	if (!linkspace) {
+		if (_alloc_linkspace(ois)) {
+			pr_err("omap_hwmod: could not allocate link space\n");
+			return -ENOMEM;
+		}
+	}
+
+	i = 0;
+	do {
+		r = _register_link(ois[i]);
+		WARN(r && r != -EEXIST,
+		     "omap_hwmod: _register_link(%s -> %s) returned %d\n",
+		     ois[i]->master->name, ois[i]->slave->name, r);
+	} while (ois[++i]);
+
+	return 0;
+}
+
+/**
  * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
  * @oh: pointer to the hwmod currently being set up (usually not the MPU)
  *
@@ -2593,13 +2850,17 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
 int omap_hwmod_count_resources(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os;
+	struct list_head *p = NULL;
 	int ret;
 	int i = 0;
 
 	ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
 
+	if (link_registration)
+		p = oh->slave_ports.next;
+
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
 		ret += _count_ocp_if_addr_spaces(os);
 	}
 
@@ -2619,6 +2880,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 {
 	struct omap_hwmod_ocp_if *os;
+	struct list_head *p = NULL;
 	int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt;
 	int r = 0;
 
@@ -2642,9 +2904,12 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 		r++;
 	}
 
+	if (link_registration)
+		p = oh->slave_ports.next;
+
 	i = 0;
 	while (i < oh->slaves_cnt) {
-		os = _fetch_next_ocp_if(NULL, oh->slaves, &i);
+		os = _fetch_next_ocp_if(&p, oh->slaves, &i);
 		addr_cnt = _count_ocp_if_addr_spaces(os);
 
 		for (j = 0; j < addr_cnt; j++) {
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 083b6da..66c4a30 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -219,6 +219,10 @@ struct omap_hwmod_addr_space {
 #define OCPIF_SWSUP_IDLE		(1 << 0)
 #define OCPIF_CAN_BURST			(1 << 1)
 
+/* omap_hwmod_ocp_if._int_flags possibilities */
+#define _OCPIF_INT_FLAGS_REGISTERED	(1 << 0)
+
+
 /**
  * struct omap_hwmod_ocp_if - OCP interface data
  * @master: struct omap_hwmod that initiates OCP transactions on this link
@@ -230,6 +234,7 @@ struct omap_hwmod_addr_space {
  * @width: OCP data width
  * @user: initiators using this interface (see OCP_USER_* macros above)
  * @flags: OCP interface flags (see OCPIF_* macros above)
+ * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above)
  *
  * It may also be useful to add a tag_cnt field for OCP2.x devices.
  *
@@ -248,6 +253,7 @@ struct omap_hwmod_ocp_if {
 	u8				width;
 	u8				user;
 	u8				flags;
+	u8				_int_flags;
 };
 
 
@@ -477,6 +483,16 @@ struct omap_hwmod_class {
 };
 
 /**
+ * struct omap_hwmod_link - internal structure linking hwmods with ocp_ifs
+ * @ocp_if: OCP interface structure record pointer
+ * @node: list_head pointing to next struct omap_hwmod_link in a list
+ */
+struct omap_hwmod_link {
+	struct omap_hwmod_ocp_if	*ocp_if;
+	struct list_head		node;
+};
+
+/**
  * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
  * @name: name of the hwmod
  * @class: struct omap_hwmod_class * to the class of this hwmod
@@ -495,6 +511,7 @@ struct omap_hwmod_class {
  * @_sysc_cache: internal-use hwmod flags
  * @_mpu_rt_va: cached register target start address (internal use)
  * @_mpu_port_index: cached MPU register target slave ID (internal use)
+ * @_mpu_port: cached MPU register target slave (internal use)
  * @opt_clks_cnt: number of @opt_clks
  * @master_cnt: number of @master entries
  * @slaves_cnt: number of @slave entries
@@ -513,6 +530,8 @@ struct omap_hwmod_class {
  *
  * Parameter names beginning with an underscore are managed internally by
  * the omap_hwmod code and should not be set during initialization.
+ *
+ * @masters and @slaves are now deprecated.
  */
 struct omap_hwmod {
 	const char			*name;
@@ -534,11 +553,14 @@ struct omap_hwmod {
 	char				*vdd_name;
 	struct omap_hwmod_ocp_if	**masters; /* connect to *_IA */
 	struct omap_hwmod_ocp_if	**slaves;  /* connect to *_TA */
+	struct list_head		master_ports; /* connect to *_IA */
+	struct list_head		slave_ports; /* connect to *_TA */
 	void				*dev_attr;
 	u32				_sysc_cache;
 	void __iomem			*_mpu_rt_va;
 	spinlock_t			_lock;
 	struct list_head		node;
+	struct omap_hwmod_ocp_if	*_mpu_port;
 	u16				flags;
 	u8				_mpu_port_index;
 	u8				response_lat;
@@ -624,4 +646,6 @@ extern int omap2430_hwmod_init(void);
 extern int omap3xxx_hwmod_init(void);
 extern int omap44xx_hwmod_init(void);
 
+extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
+
 #endif




From paul at pwsan.com  Wed Mar  7 21:38:39 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 07 Mar 2012 19:38:39 -0700
Subject: [PATCH 10/12] ARM: OMAP3: hwmod data: fix IVA interface clock
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <20120308023839.8205.66682.stgit@dusk>

The OMAP3 hwmod data listed iva2_ck as an interface clock between the
IVA and L3.  This is incorrect.  iva2_ck is not an interface clock.
Since it cannot auto-idle, specifying it here prevents the IVA and at
least one of the CORE clockdomains from going idle, which causes PM
problems such as these upon system suspend:

[   70.626129] Powerdomain (iva2_pwrdm) didn't enter target state 1
[   70.626190] Powerdomain (core_pwrdm) didn't enter target state 1

Fix by specifying the actual interface clock in the hwmod data.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3b245e9..c05a445 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2325,7 +2325,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 	.master		= &omap3xxx_l3_main_hwmod,
 	.slave		= &omap3xxx_iva_hwmod,
-	.clk		= "iva2_ck",
+	.clk		= "core_l3_ick",
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 




From paul at pwsan.com  Wed Mar  7 21:38:39 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 07 Mar 2012 19:38:39 -0700
Subject: [PATCH 09/12] ARM: OMAP2xxx: hwmod data: share common interface data
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <20120308023838.8205.31672.stgit@dusk>

Several struct omap_hwmod_ocp_if records can be shared between OMAP2420
and OMAP2430.  Move these shared records out of the chip-specific files
into mach-omap2/omap_hwmod_2xxx_interconnect_data.c.  This should save some
memory and source lines, at the cost of readability.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |  281 +-------------------
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |  256 +-----------------
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c |  266 ++++++++++++++++++-
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |   39 ++-
 4 files changed, 324 insertions(+), 518 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 75c57d3..b01b66a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -212,85 +212,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
  * interfaces
  */
 
-/* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
-	.master	= &omap2xxx_l3_main_hwmod,
-	.slave	= &omap2xxx_l4_core_hwmod,
-	.user	= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
-	.master = &omap2xxx_mpu_hwmod,
-	.slave	= &omap2xxx_l3_main_hwmod,
-	.user	= OCP_USER_MPU,
-};
-
-/* DSS -> l3 */
-static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
-	.master		= &omap2xxx_dss_core_hwmod,
-	.slave		= &omap2xxx_l3_main_hwmod,
-	.fw = {
-		.omap2 = {
-			.l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
-			.flags	= OMAP_FIREWALL_L3,
-		}
-	},
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_mcspi1_hwmod,
-	.clk		= "mcspi1_ick",
-	.addr		= omap2_mcspi1_addr_space,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_mcspi2_hwmod,
-	.clk		= "mcspi2_ick",
-	.addr		= omap2_mcspi2_addr_space,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
-	.master	= &omap2xxx_l4_core_hwmod,
-	.slave	= &omap2xxx_l4_wkup_hwmod,
-	.user	= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_uart1_hwmod,
-	.clk		= "uart1_ick",
-	.addr		= omap2xxx_uart1_addr_space,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_uart2_hwmod,
-	.clk		= "uart2_ick",
-	.addr		= omap2xxx_uart2_addr_space,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 PER -> UART3 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_uart3_hwmod,
-	.clk		= "uart3_ick",
-	.addr		= omap2xxx_uart3_addr_space,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* L4 CORE -> I2C1 interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 	.master		= &omap2xxx_l4_core_hwmod,
@@ -335,105 +256,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_core -> timer2 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer2_hwmod,
-	.clk		= "gpt2_ick",
-	.addr		= omap2xxx_timer2_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer3 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer3_hwmod,
-	.clk		= "gpt3_ick",
-	.addr		= omap2xxx_timer3_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer4 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer4_hwmod,
-	.clk		= "gpt4_ick",
-	.addr		= omap2xxx_timer4_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer5 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer5_hwmod,
-	.clk		= "gpt5_ick",
-	.addr		= omap2xxx_timer5_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer6 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer6_hwmod,
-	.clk		= "gpt6_ick",
-	.addr		= omap2xxx_timer6_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer7 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer7_hwmod,
-	.clk		= "gpt7_ick",
-	.addr		= omap2xxx_timer7_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer8 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer8_hwmod,
-	.clk		= "gpt8_ick",
-	.addr		= omap2xxx_timer8_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer9 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer9_hwmod,
-	.clk		= "gpt9_ick",
-	.addr		= omap2xxx_timer9_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer10 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer10_hwmod,
-	.clk		= "gpt10_ick",
-	.addr		= omap2_timer10_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer11 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer11_hwmod,
-	.clk		= "gpt11_ick",
-	.addr		= omap2_timer11_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer12_hwmod,
-	.clk		= "gpt12_ick",
-	.addr		= omap2xxx_timer12_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 	{
@@ -452,67 +274,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_core -> dss */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_dss_core_hwmod,
-	.clk		= "dss_ick",
-	.addr		= omap2_dss_addrs,
-	.fw = {
-		.omap2 = {
-			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
-			.flags	= OMAP_FIREWALL_L4,
-		}
-	},
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_dispc */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_dss_dispc_hwmod,
-	.clk		= "dss_ick",
-	.addr		= omap2_dss_dispc_addrs,
-	.fw = {
-		.omap2 = {
-			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
-			.flags	= OMAP_FIREWALL_L4,
-		}
-	},
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_dss_rfbi_hwmod,
-	.clk		= "dss_ick",
-	.addr		= omap2_dss_rfbi_addrs,
-	.fw = {
-		.omap2 = {
-			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
-			.flags	= OMAP_FIREWALL_L4,
-		}
-	},
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_venc */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_dss_venc_hwmod,
-	.clk		= "dss_ick",
-	.addr		= omap2_dss_venc_addrs,
-	.fw = {
-		.omap2 = {
-			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
-			.flags	= OMAP_FIREWALL_L4,
-		}
-	},
-	.flags		= OCPIF_SWSUP_IDLE,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_wkup -> gpio1 */
 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
 	{
@@ -629,12 +390,12 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
 };
 
 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
-	&omap2420_l3_main__l4_core,
-	&omap2420_mpu__l3_main,
-	&omap2420_dss__l3,
-	&omap2420_l4_core__mcspi1,
-	&omap2420_l4_core__mcspi2,
-	&omap2420_l4_core__l4_wkup,
+	&omap2xxx_l3_main__l4_core,
+	&omap2xxx_mpu__l3_main,
+	&omap2xxx_dss__l3,
+	&omap2xxx_l4_core__mcspi1,
+	&omap2xxx_l4_core__mcspi2,
+	&omap2xxx_l4_core__l4_wkup,
 	&omap2_l4_core__uart1,
 	&omap2_l4_core__uart2,
 	&omap2_l4_core__uart3,
@@ -642,22 +403,22 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 	&omap2420_l4_core__i2c2,
 	&omap2420_l3__iva,
 	&omap2420_l4_wkup__timer1,
-	&omap2420_l4_core__timer2,
-	&omap2420_l4_core__timer3,
-	&omap2420_l4_core__timer4,
-	&omap2420_l4_core__timer5,
-	&omap2420_l4_core__timer6,
-	&omap2420_l4_core__timer7,
-	&omap2420_l4_core__timer8,
-	&omap2420_l4_core__timer9,
-	&omap2420_l4_core__timer10,
-	&omap2420_l4_core__timer11,
-	&omap2420_l4_core__timer12,
+	&omap2xxx_l4_core__timer2,
+	&omap2xxx_l4_core__timer3,
+	&omap2xxx_l4_core__timer4,
+	&omap2xxx_l4_core__timer5,
+	&omap2xxx_l4_core__timer6,
+	&omap2xxx_l4_core__timer7,
+	&omap2xxx_l4_core__timer8,
+	&omap2xxx_l4_core__timer9,
+	&omap2xxx_l4_core__timer10,
+	&omap2xxx_l4_core__timer11,
+	&omap2xxx_l4_core__timer12,
 	&omap2420_l4_wkup__wd_timer2,
-	&omap2420_l4_core__dss,
-	&omap2420_l4_core__dss_dispc,
-	&omap2420_l4_core__dss_rfbi,
-	&omap2420_l4_core__dss_venc,
+	&omap2xxx_l4_core__dss,
+	&omap2xxx_l4_core__dss_dispc,
+	&omap2xxx_l4_core__dss_rfbi,
+	&omap2xxx_l4_core__dss_venc,
 	&omap2420_l4_wkup__gpio1,
 	&omap2420_l4_wkup__gpio2,
 	&omap2420_l4_wkup__gpio3,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 8b04938..23ca551 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -524,32 +524,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
  */
 
 /* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
-	.master	= &omap2xxx_l3_main_hwmod,
-	.slave	= &omap2xxx_l4_core_hwmod,
-	.user	= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
-	.master = &omap2xxx_mpu_hwmod,
-	.slave	= &omap2xxx_l3_main_hwmod,
-	.user	= OCP_USER_MPU,
-};
-
-/* DSS -> l3 */
-static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
-	.master		= &omap2xxx_dss_core_hwmod,
-	.slave		= &omap2xxx_l3_main_hwmod,
-	.fw = {
-		.omap2 = {
-			.l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
-			.flags	= OMAP_FIREWALL_L3,
-		}
-	},
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l3_core -> usbhsotg  interface */
 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 	.master		= &omap2430_usbhsotg_hwmod,
@@ -576,40 +550,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
-	.master	= &omap2xxx_l4_core_hwmod,
-	.slave	= &omap2xxx_l4_wkup_hwmod,
-	.user	= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_uart1_hwmod,
-	.clk		= "uart1_ick",
-	.addr		= omap2xxx_uart1_addr_space,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_uart2_hwmod,
-	.clk		= "uart2_ick",
-	.addr		= omap2xxx_uart2_addr_space,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 PER -> UART3 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_uart3_hwmod,
-	.clk		= "uart3_ick",
-	.addr		= omap2xxx_uart3_addr_space,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 	{
 		.pa_start	= OMAP243X_HS_BASE,
@@ -646,24 +586,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_mcspi1_hwmod,
-	.clk		= "mcspi1_ick",
-	.addr		= omap2_mcspi1_addr_space,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_mcspi2_hwmod,
-	.clk		= "mcspi2_ick",
-	.addr		= omap2_mcspi2_addr_space,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4 core -> mcspi3 interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 	.master		= &omap2xxx_l4_core_hwmod,
@@ -699,105 +621,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_core -> timer2 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer2_hwmod,
-	.clk		= "gpt2_ick",
-	.addr		= omap2xxx_timer2_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer3 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer3_hwmod,
-	.clk		= "gpt3_ick",
-	.addr		= omap2xxx_timer3_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer4 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer4_hwmod,
-	.clk		= "gpt4_ick",
-	.addr		= omap2xxx_timer4_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer5 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer5_hwmod,
-	.clk		= "gpt5_ick",
-	.addr		= omap2xxx_timer5_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer6 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer6_hwmod,
-	.clk		= "gpt6_ick",
-	.addr		= omap2xxx_timer6_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer7 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer7_hwmod,
-	.clk		= "gpt7_ick",
-	.addr		= omap2xxx_timer7_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer8 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer8_hwmod,
-	.clk		= "gpt8_ick",
-	.addr		= omap2xxx_timer8_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer9 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer9_hwmod,
-	.clk		= "gpt9_ick",
-	.addr		= omap2xxx_timer9_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer10 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer10_hwmod,
-	.clk		= "gpt10_ick",
-	.addr		= omap2_timer10_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer11 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer11_hwmod,
-	.clk		= "gpt11_ick",
-	.addr		= omap2_timer11_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_timer12_hwmod,
-	.clk		= "gpt12_ick",
-	.addr		= omap2xxx_timer12_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
 	{
@@ -816,43 +639,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_core -> dss */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_dss_core_hwmod,
-	.clk		= "dss_ick",
-	.addr		= omap2_dss_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_dispc */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_dss_dispc_hwmod,
-	.clk		= "dss_ick",
-	.addr		= omap2_dss_dispc_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_dss_rfbi_hwmod,
-	.clk		= "dss_ick",
-	.addr		= omap2_dss_rfbi_addrs,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dss_venc */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
-	.master		= &omap2xxx_l4_core_hwmod,
-	.slave		= &omap2xxx_dss_venc_hwmod,
-	.clk		= "dss_ick",
-	.addr		= omap2_dss_venc_addrs,
-	.flags		= OCPIF_SWSUP_IDLE,
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_wkup -> gpio1 */
 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
 	{
@@ -1044,40 +830,40 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
 };
 
 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
-	&omap2430_l3_main__l4_core,
-	&omap2430_mpu__l3_main,
-	&omap2430_dss__l3,
+	&omap2xxx_l3_main__l4_core,
+	&omap2xxx_mpu__l3_main,
+	&omap2xxx_dss__l3,
 	&omap2430_usbhsotg__l3,
 	&omap2430_l4_core__i2c1,
 	&omap2430_l4_core__i2c2,
-	&omap2430_l4_core__l4_wkup,
+	&omap2xxx_l4_core__l4_wkup,
 	&omap2_l4_core__uart1,
 	&omap2_l4_core__uart2,
 	&omap2_l4_core__uart3,
 	&omap2430_l4_core__usbhsotg,
 	&omap2430_l4_core__mmc1,
 	&omap2430_l4_core__mmc2,
-	&omap2430_l4_core__mcspi1,
-	&omap2430_l4_core__mcspi2,
+	&omap2xxx_l4_core__mcspi1,
+	&omap2xxx_l4_core__mcspi2,
 	&omap2430_l4_core__mcspi3,
 	&omap2430_l3__iva,
 	&omap2430_l4_wkup__timer1,
-	&omap2430_l4_core__timer2,
-	&omap2430_l4_core__timer3,
-	&omap2430_l4_core__timer4,
-	&omap2430_l4_core__timer5,
-	&omap2430_l4_core__timer6,
-	&omap2430_l4_core__timer7,
-	&omap2430_l4_core__timer8,
-	&omap2430_l4_core__timer9,
-	&omap2430_l4_core__timer10,
-	&omap2430_l4_core__timer11,
-	&omap2430_l4_core__timer12,
+	&omap2xxx_l4_core__timer2,
+	&omap2xxx_l4_core__timer3,
+	&omap2xxx_l4_core__timer4,
+	&omap2xxx_l4_core__timer5,
+	&omap2xxx_l4_core__timer6,
+	&omap2xxx_l4_core__timer7,
+	&omap2xxx_l4_core__timer8,
+	&omap2xxx_l4_core__timer9,
+	&omap2xxx_l4_core__timer10,
+	&omap2xxx_l4_core__timer11,
+	&omap2xxx_l4_core__timer12,
 	&omap2430_l4_wkup__wd_timer2,
-	&omap2430_l4_core__dss,
-	&omap2430_l4_core__dss_dispc,
-	&omap2430_l4_core__dss_rfbi,
-	&omap2430_l4_core__dss_venc,
+	&omap2xxx_l4_core__dss,
+	&omap2xxx_l4_core__dss_dispc,
+	&omap2xxx_l4_core__dss_rfbi,
+	&omap2xxx_l4_core__dss_venc,
 	&omap2430_l4_wkup__gpio1,
 	&omap2430_l4_wkup__gpio2,
 	&omap2430_l4_wkup__gpio3,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 4f3547c..5178e40 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -15,10 +15,12 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
+#include <plat/l3_2xxx.h>
+#include <plat/l4_2xxx.h>
 
 #include "omap_hwmod_common_data.h"
 
-struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
 	{
 		.pa_start	= OMAP2_UART1_BASE,
 		.pa_end		= OMAP2_UART1_BASE + SZ_8K - 1,
@@ -27,7 +29,7 @@ struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
 	{ }
 };
 
-struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
 	{
 		.pa_start	= OMAP2_UART2_BASE,
 		.pa_end		= OMAP2_UART2_BASE + SZ_1K - 1,
@@ -36,7 +38,7 @@ struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
 	{ }
 };
 
-struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
 	{
 		.pa_start	= OMAP2_UART3_BASE,
 		.pa_end		= OMAP2_UART3_BASE + SZ_1K - 1,
@@ -45,7 +47,7 @@ struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
 	{ }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
 	{
 		.pa_start	= 0x4802a000,
 		.pa_end		= 0x4802a000 + SZ_1K - 1,
@@ -54,7 +56,7 @@ struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
 	{ }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
 	{
 		.pa_start	= 0x48078000,
 		.pa_end		= 0x48078000 + SZ_1K - 1,
@@ -63,7 +65,7 @@ struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
 	{ }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
 	{
 		.pa_start	= 0x4807a000,
 		.pa_end		= 0x4807a000 + SZ_1K - 1,
@@ -72,7 +74,7 @@ struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
 	{ }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
 	{
 		.pa_start	= 0x4807c000,
 		.pa_end		= 0x4807c000 + SZ_1K - 1,
@@ -81,7 +83,7 @@ struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
 	{ }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
 	{
 		.pa_start	= 0x4807e000,
 		.pa_end		= 0x4807e000 + SZ_1K - 1,
@@ -90,7 +92,7 @@ struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
 	{ }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
 	{
 		.pa_start	= 0x48080000,
 		.pa_end		= 0x48080000 + SZ_1K - 1,
@@ -99,7 +101,7 @@ struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
 	{ }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
 	{
 		.pa_start	= 0x48082000,
 		.pa_end		= 0x48082000 + SZ_1K - 1,
@@ -108,7 +110,7 @@ struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
 	{ }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
 	{
 		.pa_start	= 0x48084000,
 		.pa_end		= 0x48084000 + SZ_1K - 1,
@@ -127,4 +129,246 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
 	{ }
 };
 
+/*
+ * Common interconnect data
+ */
+
+/* L3 -> L4_CORE interface */
+struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
+	.master	= &omap2xxx_l3_main_hwmod,
+	.slave	= &omap2xxx_l4_core_hwmod,
+	.user	= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* MPU -> L3 interface */
+struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
+	.master = &omap2xxx_mpu_hwmod,
+	.slave	= &omap2xxx_l3_main_hwmod,
+	.user	= OCP_USER_MPU,
+};
+
+/* DSS -> l3 */
+struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
+	.master		= &omap2xxx_dss_core_hwmod,
+	.slave		= &omap2xxx_l3_main_hwmod,
+	.fw = {
+		.omap2 = {
+			.l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
+			.flags	= OMAP_FIREWALL_L3,
+		}
+	},
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4_CORE -> L4_WKUP interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
+	.master	= &omap2xxx_l4_core_hwmod,
+	.slave	= &omap2xxx_l4_wkup_hwmod,
+	.user	= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART1 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_uart1_hwmod,
+	.clk		= "uart1_ick",
+	.addr		= omap2xxx_uart1_addr_space,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_uart2_hwmod,
+	.clk		= "uart2_ick",
+	.addr		= omap2xxx_uart2_addr_space,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_uart3_hwmod,
+	.clk		= "uart3_ick",
+	.addr		= omap2xxx_uart3_addr_space,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi1 interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_mcspi1_hwmod,
+	.clk		= "mcspi1_ick",
+	.addr		= omap2_mcspi1_addr_space,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi2 interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_mcspi2_hwmod,
+	.clk		= "mcspi2_ick",
+	.addr		= omap2_mcspi2_addr_space,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer2 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer2_hwmod,
+	.clk		= "gpt2_ick",
+	.addr		= omap2xxx_timer2_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer3 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer3_hwmod,
+	.clk		= "gpt3_ick",
+	.addr		= omap2xxx_timer3_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer4 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer4_hwmod,
+	.clk		= "gpt4_ick",
+	.addr		= omap2xxx_timer4_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer5 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer5_hwmod,
+	.clk		= "gpt5_ick",
+	.addr		= omap2xxx_timer5_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer6 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer6_hwmod,
+	.clk		= "gpt6_ick",
+	.addr		= omap2xxx_timer6_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer7 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer7_hwmod,
+	.clk		= "gpt7_ick",
+	.addr		= omap2xxx_timer7_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer8 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer8_hwmod,
+	.clk		= "gpt8_ick",
+	.addr		= omap2xxx_timer8_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer9 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer9_hwmod,
+	.clk		= "gpt9_ick",
+	.addr		= omap2xxx_timer9_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer10 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer10_hwmod,
+	.clk		= "gpt10_ick",
+	.addr		= omap2_timer10_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer11 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer11_hwmod,
+	.clk		= "gpt11_ick",
+	.addr		= omap2_timer11_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer12 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer12_hwmod,
+	.clk		= "gpt12_ick",
+	.addr		= omap2xxx_timer12_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_core_hwmod,
+	.clk		= "dss_ick",
+	.addr		= omap2_dss_addrs,
+	.fw = {
+		.omap2 = {
+			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+			.flags	= OMAP_FIREWALL_L4,
+		}
+	},
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_dispc */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_dispc_hwmod,
+	.clk		= "dss_ick",
+	.addr		= omap2_dss_dispc_addrs,
+	.fw = {
+		.omap2 = {
+			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
+			.flags	= OMAP_FIREWALL_L4,
+		}
+	},
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_rfbi */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_rfbi_hwmod,
+	.clk		= "dss_ick",
+	.addr		= omap2_dss_rfbi_addrs,
+	.fw = {
+		.omap2 = {
+			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+			.flags	= OMAP_FIREWALL_L4,
+		}
+	},
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_venc */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_venc_hwmod,
+	.clk		= "dss_ick",
+	.addr		= omap2_dss_venc_addrs,
+	.fw = {
+		.omap2 = {
+			.l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
+			.flags	= OMAP_FIREWALL_L4,
+		}
+	},
+	.flags		= OCPIF_SWSUP_IDLE,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 65757f3..7aa9156 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -19,18 +19,6 @@
 #include "display.h"
 
 /* Common address space across OMAP2xxx */
-extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
 extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
 
 /* Common address space across OMAP2xxx/3xxx */
@@ -87,6 +75,32 @@ extern struct omap_hwmod omap2xxx_gpio4_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
 
+/* Common interface data across OMAP2xxx */
+extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
+extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main;
+extern struct omap_hwmod_ocp_if omap2xxx_dss__l3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart1;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
+
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
 extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[];
@@ -126,6 +140,7 @@ extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
 extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
 extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
 extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
 
 /* OMAP hwmod classes - forward declarations */
 extern struct omap_hwmod_class l3_hwmod_class;




From paul at pwsan.com  Wed Mar  7 21:38:38 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 07 Mar 2012 19:38:38 -0700
Subject: [PATCH 08/12] ARM: OMAP2xxx: hwmod data: share common hwmods between
 OMAP2420 and OMAP2430
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <20120308023837.8205.66638.stgit@dusk>

After the link registration conversion, it's much easier to share some
hwmod data between OMAP2420 and 2430.  Move the shareable data into a
common file.  This should save some memory and lines of source, at the
cost of readability.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |  669 ++-----------------
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |  688 ++------------------
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |  562 ++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |   32 +
 4 files changed, 740 insertions(+), 1211 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index f74335f..75c57d3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -43,417 +43,12 @@
  * IP blocks
  */
 
-/* L3 */
-static struct omap_hwmod omap2420_l3_main_hwmod = {
-	.name		= "l3_main",
-	.class		= &l3_hwmod_class,
-	.flags		= HWMOD_NO_IDLEST,
-};
-
-/* L4 CORE */
-static struct omap_hwmod omap2420_l4_core_hwmod = {
-	.name		= "l4_core",
-	.class		= &l4_hwmod_class,
-	.flags		= HWMOD_NO_IDLEST,
-};
-
-/* L4 WKUP */
-static struct omap_hwmod omap2420_l4_wkup_hwmod = {
-	.name		= "l4_wkup",
-	.class		= &l4_hwmod_class,
-	.flags		= HWMOD_NO_IDLEST,
-};
-
-/* MPU */
-static struct omap_hwmod omap2420_mpu_hwmod = {
-	.name		= "mpu",
-	.class		= &mpu_hwmod_class,
-	.main_clk	= "mpu_ck",
-};
-
 /* IVA2 (IVA2) */
 static struct omap_hwmod omap2420_iva_hwmod = {
 	.name		= "iva",
 	.class		= &iva_hwmod_class,
 };
 
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
-	.timer_capability	= OMAP_TIMER_ALWON,
-};
-
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
-	.timer_capability	= OMAP_TIMER_HAS_PWM,
-};
-
-/* timer1 */
-static struct omap_hwmod omap2420_timer1_hwmod = {
-	.name		= "timer1",
-	.mpu_irqs	= omap2_timer1_mpu_irqs,
-	.main_clk	= "gpt1_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT1_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer2 */
-static struct omap_hwmod omap2420_timer2_hwmod = {
-	.name		= "timer2",
-	.mpu_irqs	= omap2_timer2_mpu_irqs,
-	.main_clk	= "gpt2_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT2_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer3 */
-static struct omap_hwmod omap2420_timer3_hwmod = {
-	.name		= "timer3",
-	.mpu_irqs	= omap2_timer3_mpu_irqs,
-	.main_clk	= "gpt3_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT3_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer4 */
-static struct omap_hwmod omap2420_timer4_hwmod = {
-	.name		= "timer4",
-	.mpu_irqs	= omap2_timer4_mpu_irqs,
-	.main_clk	= "gpt4_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT4_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer5 */
-static struct omap_hwmod omap2420_timer5_hwmod = {
-	.name		= "timer5",
-	.mpu_irqs	= omap2_timer5_mpu_irqs,
-	.main_clk	= "gpt5_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT5_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer6 */
-static struct omap_hwmod omap2420_timer6_hwmod = {
-	.name		= "timer6",
-	.mpu_irqs	= omap2_timer6_mpu_irqs,
-	.main_clk	= "gpt6_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT6_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer7 */
-static struct omap_hwmod omap2420_timer7_hwmod = {
-	.name		= "timer7",
-	.mpu_irqs	= omap2_timer7_mpu_irqs,
-	.main_clk	= "gpt7_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT7_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer8 */
-static struct omap_hwmod omap2420_timer8_hwmod = {
-	.name		= "timer8",
-	.mpu_irqs	= omap2_timer8_mpu_irqs,
-	.main_clk	= "gpt8_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT8_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer9 */
-static struct omap_hwmod omap2420_timer9_hwmod = {
-	.name		= "timer9",
-	.mpu_irqs	= omap2_timer9_mpu_irqs,
-	.main_clk	= "gpt9_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT9_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_pwm_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer10 */
-static struct omap_hwmod omap2420_timer10_hwmod = {
-	.name		= "timer10",
-	.mpu_irqs	= omap2_timer10_mpu_irqs,
-	.main_clk	= "gpt10_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT10_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_pwm_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer11 */
-static struct omap_hwmod omap2420_timer11_hwmod = {
-	.name		= "timer11",
-	.mpu_irqs	= omap2_timer11_mpu_irqs,
-	.main_clk	= "gpt11_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT11_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_pwm_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer12 */
-static struct omap_hwmod omap2420_timer12_hwmod = {
-	.name		= "timer12",
-	.mpu_irqs	= omap2xxx_timer12_mpu_irqs,
-	.main_clk	= "gpt12_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT12_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_pwm_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-static struct omap_hwmod omap2420_wd_timer2_hwmod = {
-	.name		= "wd_timer2",
-	.class		= &omap2xxx_wd_timer_hwmod_class,
-	.main_clk	= "mpu_wdt_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
-		},
-	},
-};
-
-/* UART1 */
-static struct omap_hwmod omap2420_uart1_hwmod = {
-	.name		= "uart1",
-	.mpu_irqs	= omap2_uart1_mpu_irqs,
-	.sdma_reqs	= omap2_uart1_sdma_reqs,
-	.main_clk	= "uart1_fck",
-	.prcm		= {
-		.omap2 = {
-			.module_offs = CORE_MOD,
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_UART1_SHIFT,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
-		},
-	},
-	.class		= &omap2_uart_class,
-};
-
-/* UART2 */
-static struct omap_hwmod omap2420_uart2_hwmod = {
-	.name		= "uart2",
-	.mpu_irqs	= omap2_uart2_mpu_irqs,
-	.sdma_reqs	= omap2_uart2_sdma_reqs,
-	.main_clk	= "uart2_fck",
-	.prcm		= {
-		.omap2 = {
-			.module_offs = CORE_MOD,
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_UART2_SHIFT,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
-		},
-	},
-	.class		= &omap2_uart_class,
-};
-
-/* UART3 */
-static struct omap_hwmod omap2420_uart3_hwmod = {
-	.name		= "uart3",
-	.mpu_irqs	= omap2_uart3_mpu_irqs,
-	.sdma_reqs	= omap2_uart3_sdma_reqs,
-	.main_clk	= "uart3_fck",
-	.prcm		= {
-		.omap2 = {
-			.module_offs = CORE_MOD,
-			.prcm_reg_id = 2,
-			.module_bit = OMAP24XX_EN_UART3_SHIFT,
-			.idlest_reg_id = 2,
-			.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
-		},
-	},
-	.class		= &omap2_uart_class,
-};
-
-/* dss */
-
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
-	/*
-	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
-	 * driver does not use these clocks.
-	 */
-	{ .role = "tv_clk", .clk = "dss_54m_fck" },
-	{ .role = "sys_clk", .clk = "dss2_fck" },
-};
-
-static struct omap_hwmod omap2420_dss_core_hwmod = {
-	.name		= "dss_core",
-	.class		= &omap2_dss_hwmod_class,
-	.main_clk	= "dss1_fck", /* instead of dss_fck */
-	.sdma_reqs	= omap2xxx_dss_sdma_chs,
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-		},
-	},
-	.opt_clks	= dss_opt_clks,
-	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-	.flags		= HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-};
-
-static struct omap_hwmod omap2420_dss_dispc_hwmod = {
-	.name		= "dss_dispc",
-	.class		= &omap2_dispc_hwmod_class,
-	.mpu_irqs	= omap2_dispc_irqs,
-	.main_clk	= "dss1_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-		},
-	},
-	.flags		= HWMOD_NO_IDLEST,
-	.dev_attr	= &omap2_3_dss_dispc_dev_attr
-};
-
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
-	{ .role = "ick", .clk = "dss_ick" },
-};
-
-static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
-	.name		= "dss_rfbi",
-	.class		= &omap2_rfbi_hwmod_class,
-	.main_clk	= "dss1_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
-			.module_offs = CORE_MOD,
-		},
-	},
-	.opt_clks	= dss_rfbi_opt_clks,
-	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
-	.flags		= HWMOD_NO_IDLEST,
-};
-
-static struct omap_hwmod omap2420_dss_venc_hwmod = {
-	.name		= "dss_venc",
-	.class		= &omap2_venc_hwmod_class,
-	.main_clk	= "dss_54m_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
-			.module_offs = CORE_MOD,
-		},
-	},
-	.flags		= HWMOD_NO_IDLEST,
-};
-
 /* I2C common */
 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 	.rev_offs	= 0x00,
@@ -517,88 +112,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
 	.flags		= HWMOD_16BIT_REG,
 };
 
-/* gpio dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
-	.bank_width = 32,
-	.dbck_flag = false,
-};
-
-/* gpio1 */
-static struct omap_hwmod omap2420_gpio1_hwmod = {
-	.name		= "gpio1",
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap2_gpio1_irqs,
-	.main_clk	= "gpios_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_gpio_hwmod_class,
-	.dev_attr	= &gpio_dev_attr,
-};
-
-/* gpio2 */
-static struct omap_hwmod omap2420_gpio2_hwmod = {
-	.name		= "gpio2",
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap2_gpio2_irqs,
-	.main_clk	= "gpios_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_gpio_hwmod_class,
-	.dev_attr	= &gpio_dev_attr,
-};
-
-/* gpio3 */
-static struct omap_hwmod omap2420_gpio3_hwmod = {
-	.name		= "gpio3",
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap2_gpio3_irqs,
-	.main_clk	= "gpios_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_gpio_hwmod_class,
-	.dev_attr	= &gpio_dev_attr,
-};
-
-/* gpio4 */
-static struct omap_hwmod omap2420_gpio4_hwmod = {
-	.name		= "gpio4",
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap2_gpio4_irqs,
-	.main_clk	= "gpios_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_gpio_hwmod_class,
-	.dev_attr	= &gpio_dev_attr,
-};
-
 /* dma attributes */
 static struct omap_dma_dev_attr dma_dev_attr = {
 	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -638,52 +151,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
 	},
 };
 
-/* mcspi1 */
-static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
-	.num_chipselect = 4,
-};
-
-static struct omap_hwmod omap2420_mcspi1_hwmod = {
-	.name		= "mcspi1",
-	.mpu_irqs	= omap2_mcspi1_mpu_irqs,
-	.sdma_reqs	= omap2_mcspi1_sdma_reqs,
-	.main_clk	= "mcspi1_fck",
-	.prcm		= {
-		.omap2 = {
-			.module_offs = CORE_MOD,
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_mcspi_class,
-	.dev_attr	= &omap_mcspi1_dev_attr,
-};
-
-/* mcspi2 */
-static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
-	.num_chipselect = 2,
-};
-
-static struct omap_hwmod omap2420_mcspi2_hwmod = {
-	.name		= "mcspi2",
-	.mpu_irqs	= omap2_mcspi2_mpu_irqs,
-	.sdma_reqs	= omap2_mcspi2_sdma_reqs,
-	.main_clk	= "mcspi2_fck",
-	.prcm		= {
-		.omap2 = {
-			.module_offs = CORE_MOD,
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_mcspi_class,
-	.dev_attr	= &omap_mcspi2_dev_attr,
-};
-
 /*
  * 'mcbsp' class
  * multi channel buffered serial port controller
@@ -747,22 +214,22 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
-	.master	= &omap2420_l3_main_hwmod,
-	.slave	= &omap2420_l4_core_hwmod,
+	.master	= &omap2xxx_l3_main_hwmod,
+	.slave	= &omap2xxx_l4_core_hwmod,
 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* MPU -> L3 interface */
 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
-	.master = &omap2420_mpu_hwmod,
-	.slave	= &omap2420_l3_main_hwmod,
+	.master = &omap2xxx_mpu_hwmod,
+	.slave	= &omap2xxx_l3_main_hwmod,
 	.user	= OCP_USER_MPU,
 };
 
 /* DSS -> l3 */
 static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
-	.master		= &omap2420_dss_core_hwmod,
-	.slave		= &omap2420_l3_main_hwmod,
+	.master		= &omap2xxx_dss_core_hwmod,
+	.slave		= &omap2xxx_l3_main_hwmod,
 	.fw = {
 		.omap2 = {
 			.l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
@@ -774,8 +241,8 @@ static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
 
 /* l4 core -> mcspi1 interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_mcspi1_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_mcspi1_hwmod,
 	.clk		= "mcspi1_ick",
 	.addr		= omap2_mcspi1_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -783,8 +250,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
 
 /* l4 core -> mcspi2 interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_mcspi2_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_mcspi2_hwmod,
 	.clk		= "mcspi2_ick",
 	.addr		= omap2_mcspi2_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -792,15 +259,15 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
-	.master	= &omap2420_l4_core_hwmod,
-	.slave	= &omap2420_l4_wkup_hwmod,
+	.master	= &omap2xxx_l4_core_hwmod,
+	.slave	= &omap2xxx_l4_wkup_hwmod,
 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L4 CORE -> UART1 interface */
 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_uart1_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_uart1_hwmod,
 	.clk		= "uart1_ick",
 	.addr		= omap2xxx_uart1_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -808,8 +275,8 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 
 /* L4 CORE -> UART2 interface */
 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_uart2_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_uart2_hwmod,
 	.clk		= "uart2_ick",
 	.addr		= omap2xxx_uart2_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -817,8 +284,8 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 
 /* L4 PER -> UART3 interface */
 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_uart3_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_uart3_hwmod,
 	.clk		= "uart3_ick",
 	.addr		= omap2xxx_uart3_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -826,7 +293,7 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 
 /* L4 CORE -> I2C1 interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
-	.master		= &omap2420_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2420_i2c1_hwmod,
 	.clk		= "i2c1_ick",
 	.addr		= omap2_i2c1_addr_space,
@@ -835,7 +302,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 
 /* L4 CORE -> I2C2 interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
-	.master		= &omap2420_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2420_i2c2_hwmod,
 	.clk		= "i2c2_ick",
 	.addr		= omap2_i2c2_addr_space,
@@ -844,7 +311,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 
 /* IVA <- L3 interface */
 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
-	.master		= &omap2420_l3_main_hwmod,
+	.master		= &omap2xxx_l3_main_hwmod,
 	.slave		= &omap2420_iva_hwmod,
 	.clk		= "iva1_ifck",
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -861,8 +328,8 @@ static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
 
 /* l4_wkup -> timer1 */
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
-	.master		= &omap2420_l4_wkup_hwmod,
-	.slave		= &omap2420_timer1_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_timer1_hwmod,
 	.clk		= "gpt1_ick",
 	.addr		= omap2420_timer1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -870,8 +337,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 
 /* l4_core -> timer2 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_timer2_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer2_hwmod,
 	.clk		= "gpt2_ick",
 	.addr		= omap2xxx_timer2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -879,8 +346,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
 
 /* l4_core -> timer3 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_timer3_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer3_hwmod,
 	.clk		= "gpt3_ick",
 	.addr		= omap2xxx_timer3_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -888,8 +355,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
 
 /* l4_core -> timer4 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_timer4_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer4_hwmod,
 	.clk		= "gpt4_ick",
 	.addr		= omap2xxx_timer4_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -897,8 +364,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
 
 /* l4_core -> timer5 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_timer5_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer5_hwmod,
 	.clk		= "gpt5_ick",
 	.addr		= omap2xxx_timer5_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -906,8 +373,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
 
 /* l4_core -> timer6 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_timer6_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer6_hwmod,
 	.clk		= "gpt6_ick",
 	.addr		= omap2xxx_timer6_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -915,8 +382,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
 
 /* l4_core -> timer7 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_timer7_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer7_hwmod,
 	.clk		= "gpt7_ick",
 	.addr		= omap2xxx_timer7_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -924,8 +391,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
 
 /* l4_core -> timer8 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_timer8_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer8_hwmod,
 	.clk		= "gpt8_ick",
 	.addr		= omap2xxx_timer8_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -933,8 +400,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
 
 /* l4_core -> timer9 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_timer9_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer9_hwmod,
 	.clk		= "gpt9_ick",
 	.addr		= omap2xxx_timer9_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -942,8 +409,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
 
 /* l4_core -> timer10 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_timer10_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer10_hwmod,
 	.clk		= "gpt10_ick",
 	.addr		= omap2_timer10_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -951,8 +418,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
 
 /* l4_core -> timer11 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_timer11_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer11_hwmod,
 	.clk		= "gpt11_ick",
 	.addr		= omap2_timer11_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -960,8 +427,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
 
 /* l4_core -> timer12 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_timer12_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer12_hwmod,
 	.clk		= "gpt12_ick",
 	.addr		= omap2xxx_timer12_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -978,8 +445,8 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
-	.master		= &omap2420_l4_wkup_hwmod,
-	.slave		= &omap2420_wd_timer2_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_wd_timer2_hwmod,
 	.clk		= "mpu_wdt_ick",
 	.addr		= omap2420_wd_timer2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -987,8 +454,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 
 /* l4_core -> dss */
 static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_dss_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_core_hwmod,
 	.clk		= "dss_ick",
 	.addr		= omap2_dss_addrs,
 	.fw = {
@@ -1002,8 +469,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
 
 /* l4_core -> dss_dispc */
 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_dss_dispc_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_dispc_hwmod,
 	.clk		= "dss_ick",
 	.addr		= omap2_dss_dispc_addrs,
 	.fw = {
@@ -1017,8 +484,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
 
 /* l4_core -> dss_rfbi */
 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_dss_rfbi_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_rfbi_hwmod,
 	.clk		= "dss_ick",
 	.addr		= omap2_dss_rfbi_addrs,
 	.fw = {
@@ -1032,8 +499,8 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
 
 /* l4_core -> dss_venc */
 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
-	.master		= &omap2420_l4_core_hwmod,
-	.slave		= &omap2420_dss_venc_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_venc_hwmod,
 	.clk		= "dss_ick",
 	.addr		= omap2_dss_venc_addrs,
 	.fw = {
@@ -1057,8 +524,8 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
-	.master		= &omap2420_l4_wkup_hwmod,
-	.slave		= &omap2420_gpio1_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_gpio1_hwmod,
 	.clk		= "gpios_ick",
 	.addr		= omap2420_gpio1_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1075,8 +542,8 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
-	.master		= &omap2420_l4_wkup_hwmod,
-	.slave		= &omap2420_gpio2_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_gpio2_hwmod,
 	.clk		= "gpios_ick",
 	.addr		= omap2420_gpio2_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1093,8 +560,8 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
-	.master		= &omap2420_l4_wkup_hwmod,
-	.slave		= &omap2420_gpio3_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_gpio3_hwmod,
 	.clk		= "gpios_ick",
 	.addr		= omap2420_gpio3_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1111,8 +578,8 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
-	.master		= &omap2420_l4_wkup_hwmod,
-	.slave		= &omap2420_gpio4_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_gpio4_hwmod,
 	.clk		= "gpios_ick",
 	.addr		= omap2420_gpio4_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1121,14 +588,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
 /* dma_system -> L3 */
 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
 	.master		= &omap2420_dma_system_hwmod,
-	.slave		= &omap2420_l3_main_hwmod,
+	.slave		= &omap2xxx_l3_main_hwmod,
 	.clk		= "core_l3_ck",
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_core -> dma_system */
 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
-	.master		= &omap2420_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2420_dma_system_hwmod,
 	.clk		= "sdma_ick",
 	.addr		= omap2_dma_system_addrs,
@@ -1137,7 +604,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
 
 /* l4_core -> mailbox */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
-	.master		= &omap2420_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2420_mailbox_hwmod,
 	.addr		= omap2_mailbox_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1145,7 +612,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
 
 /* l4_core -> mcbsp1 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
-	.master		= &omap2420_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2420_mcbsp1_hwmod,
 	.clk		= "mcbsp1_ick",
 	.addr		= omap2_mcbsp1_addrs,
@@ -1154,7 +621,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
 
 /* l4_core -> mcbsp2 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
-	.master		= &omap2420_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2420_mcbsp2_hwmod,
 	.clk		= "mcbsp2_ick",
 	.addr		= omap2xxx_mcbsp2_addrs,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index da8fef0..8b04938 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -44,416 +44,12 @@
  * IP blocks
  */
 
-/* L3 */
-static struct omap_hwmod omap2430_l3_main_hwmod = {
-	.name		= "l3_main",
-	.class		= &l3_hwmod_class,
-	.flags		= HWMOD_NO_IDLEST,
-};
-
-/* L4 CORE */
-static struct omap_hwmod omap2430_l4_core_hwmod = {
-	.name		= "l4_core",
-	.class		= &l4_hwmod_class,
-	.flags		= HWMOD_NO_IDLEST,
-};
-
-/* L4 WKUP */
-static struct omap_hwmod omap2430_l4_wkup_hwmod = {
-	.name		= "l4_wkup",
-	.class		= &l4_hwmod_class,
-	.flags		= HWMOD_NO_IDLEST,
-};
-
-/* MPU */
-static struct omap_hwmod omap2430_mpu_hwmod = {
-	.name		= "mpu",
-	.class		= &mpu_hwmod_class,
-	.main_clk	= "mpu_ck",
-};
-
 /* IVA2 (IVA2) */
 static struct omap_hwmod omap2430_iva_hwmod = {
 	.name		= "iva",
 	.class		= &iva_hwmod_class,
 };
 
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
-	.timer_capability	= OMAP_TIMER_ALWON,
-};
-
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
-	.timer_capability	= OMAP_TIMER_HAS_PWM,
-};
-
-/* timer1 */
-static struct omap_hwmod omap2430_timer1_hwmod = {
-	.name		= "timer1",
-	.mpu_irqs	= omap2_timer1_mpu_irqs,
-	.main_clk	= "gpt1_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT1_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer2 */
-static struct omap_hwmod omap2430_timer2_hwmod = {
-	.name		= "timer2",
-	.mpu_irqs	= omap2_timer2_mpu_irqs,
-	.main_clk	= "gpt2_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT2_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer3 */
-static struct omap_hwmod omap2430_timer3_hwmod = {
-	.name		= "timer3",
-	.mpu_irqs	= omap2_timer3_mpu_irqs,
-	.main_clk	= "gpt3_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT3_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer4 */
-static struct omap_hwmod omap2430_timer4_hwmod = {
-	.name		= "timer4",
-	.mpu_irqs	= omap2_timer4_mpu_irqs,
-	.main_clk	= "gpt4_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT4_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer5 */
-static struct omap_hwmod omap2430_timer5_hwmod = {
-	.name		= "timer5",
-	.mpu_irqs	= omap2_timer5_mpu_irqs,
-	.main_clk	= "gpt5_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT5_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer6 */
-static struct omap_hwmod omap2430_timer6_hwmod = {
-	.name		= "timer6",
-	.mpu_irqs	= omap2_timer6_mpu_irqs,
-	.main_clk	= "gpt6_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT6_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer7 */
-static struct omap_hwmod omap2430_timer7_hwmod = {
-	.name		= "timer7",
-	.mpu_irqs	= omap2_timer7_mpu_irqs,
-	.main_clk	= "gpt7_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT7_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer8 */
-static struct omap_hwmod omap2430_timer8_hwmod = {
-	.name		= "timer8",
-	.mpu_irqs	= omap2_timer8_mpu_irqs,
-	.main_clk	= "gpt8_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT8_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_alwon_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer9 */
-static struct omap_hwmod omap2430_timer9_hwmod = {
-	.name		= "timer9",
-	.mpu_irqs	= omap2_timer9_mpu_irqs,
-	.main_clk	= "gpt9_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT9_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_pwm_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer10 */
-static struct omap_hwmod omap2430_timer10_hwmod = {
-	.name		= "timer10",
-	.mpu_irqs	= omap2_timer10_mpu_irqs,
-	.main_clk	= "gpt10_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT10_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_pwm_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer11 */
-static struct omap_hwmod omap2430_timer11_hwmod = {
-	.name		= "timer11",
-	.mpu_irqs	= omap2_timer11_mpu_irqs,
-	.main_clk	= "gpt11_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT11_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_pwm_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-/* timer12 */
-static struct omap_hwmod omap2430_timer12_hwmod = {
-	.name		= "timer12",
-	.mpu_irqs	= omap2xxx_timer12_mpu_irqs,
-	.main_clk	= "gpt12_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPT12_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
-		},
-	},
-	.dev_attr	= &capability_pwm_dev_attr,
-	.class		= &omap2xxx_timer_hwmod_class,
-};
-
-static struct omap_hwmod omap2430_wd_timer2_hwmod = {
-	.name		= "wd_timer2",
-	.class		= &omap2xxx_wd_timer_hwmod_class,
-	.main_clk	= "mpu_wdt_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
-		},
-	},
-};
-
-/* UART1 */
-static struct omap_hwmod omap2430_uart1_hwmod = {
-	.name		= "uart1",
-	.mpu_irqs	= omap2_uart1_mpu_irqs,
-	.sdma_reqs	= omap2_uart1_sdma_reqs,
-	.main_clk	= "uart1_fck",
-	.prcm		= {
-		.omap2 = {
-			.module_offs = CORE_MOD,
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_UART1_SHIFT,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
-		},
-	},
-	.class		= &omap2_uart_class,
-};
-
-/* UART2 */
-static struct omap_hwmod omap2430_uart2_hwmod = {
-	.name		= "uart2",
-	.mpu_irqs	= omap2_uart2_mpu_irqs,
-	.sdma_reqs	= omap2_uart2_sdma_reqs,
-	.main_clk	= "uart2_fck",
-	.prcm		= {
-		.omap2 = {
-			.module_offs = CORE_MOD,
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_UART2_SHIFT,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
-		},
-	},
-	.class		= &omap2_uart_class,
-};
-
-/* UART3 */
-static struct omap_hwmod omap2430_uart3_hwmod = {
-	.name		= "uart3",
-	.mpu_irqs	= omap2_uart3_mpu_irqs,
-	.sdma_reqs	= omap2_uart3_sdma_reqs,
-	.main_clk	= "uart3_fck",
-	.prcm		= {
-		.omap2 = {
-			.module_offs = CORE_MOD,
-			.prcm_reg_id = 2,
-			.module_bit = OMAP24XX_EN_UART3_SHIFT,
-			.idlest_reg_id = 2,
-			.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
-		},
-	},
-	.class		= &omap2_uart_class,
-};
-
-/* dss */
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
-	/*
-	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
-	 * driver does not use these clocks.
-	 */
-	{ .role = "tv_clk", .clk = "dss_54m_fck" },
-	{ .role = "sys_clk", .clk = "dss2_fck" },
-};
-
-static struct omap_hwmod omap2430_dss_core_hwmod = {
-	.name		= "dss_core",
-	.class		= &omap2_dss_hwmod_class,
-	.main_clk	= "dss1_fck", /* instead of dss_fck */
-	.sdma_reqs	= omap2xxx_dss_sdma_chs,
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-		},
-	},
-	.opt_clks	= dss_opt_clks,
-	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-	.flags		= HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-};
-
-static struct omap_hwmod omap2430_dss_dispc_hwmod = {
-	.name		= "dss_dispc",
-	.class		= &omap2_dispc_hwmod_class,
-	.mpu_irqs	= omap2_dispc_irqs,
-	.main_clk	= "dss1_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
-			.module_offs = CORE_MOD,
-			.idlest_reg_id = 1,
-			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-		},
-	},
-	.flags		= HWMOD_NO_IDLEST,
-	.dev_attr	= &omap2_3_dss_dispc_dev_attr
-};
-
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
-	{ .role = "ick", .clk = "dss_ick" },
-};
-
-static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
-	.name		= "dss_rfbi",
-	.class		= &omap2_rfbi_hwmod_class,
-	.main_clk	= "dss1_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
-			.module_offs = CORE_MOD,
-		},
-	},
-	.opt_clks	= dss_rfbi_opt_clks,
-	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
-	.flags		= HWMOD_NO_IDLEST,
-};
-
-static struct omap_hwmod omap2430_dss_venc_hwmod = {
-	.name		= "dss_venc",
-	.class		= &omap2_venc_hwmod_class,
-	.main_clk	= "dss_54m_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
-			.module_offs = CORE_MOD,
-		},
-	},
-	.flags		= HWMOD_NO_IDLEST,
-};
-
 /* I2C common */
 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 	.rev_offs	= 0x00,
@@ -526,88 +122,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
 	.dev_attr	= &i2c_dev_attr,
 };
 
-/* gpio dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
-	.bank_width = 32,
-	.dbck_flag = false,
-};
-
-/* gpio1 */
-static struct omap_hwmod omap2430_gpio1_hwmod = {
-	.name		= "gpio1",
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap2_gpio1_irqs,
-	.main_clk	= "gpios_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_gpio_hwmod_class,
-	.dev_attr	= &gpio_dev_attr,
-};
-
-/* gpio2 */
-static struct omap_hwmod omap2430_gpio2_hwmod = {
-	.name		= "gpio2",
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap2_gpio2_irqs,
-	.main_clk	= "gpios_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_gpio_hwmod_class,
-	.dev_attr	= &gpio_dev_attr,
-};
-
-/* gpio3 */
-static struct omap_hwmod omap2430_gpio3_hwmod = {
-	.name		= "gpio3",
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap2_gpio3_irqs,
-	.main_clk	= "gpios_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_gpio_hwmod_class,
-	.dev_attr	= &gpio_dev_attr,
-};
-
-/* gpio4 */
-static struct omap_hwmod omap2430_gpio4_hwmod = {
-	.name		= "gpio4",
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-	.mpu_irqs	= omap2_gpio4_irqs,
-	.main_clk	= "gpios_fck",
-	.prcm		= {
-		.omap2 = {
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-			.module_offs = WKUP_MOD,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_gpio_hwmod_class,
-	.dev_attr	= &gpio_dev_attr,
-};
-
 /* gpio5 */
 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
 	{ .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
@@ -629,7 +143,7 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
 		},
 	},
 	.class		= &omap2xxx_gpio_hwmod_class,
-	.dev_attr	= &gpio_dev_attr,
+	.dev_attr	= &omap2xxx_gpio_dev_attr,
 };
 
 /* dma attributes */
@@ -670,52 +184,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
 	},
 };
 
-/* mcspi1 */
-static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
-	.num_chipselect = 4,
-};
-
-static struct omap_hwmod omap2430_mcspi1_hwmod = {
-	.name		= "mcspi1",
-	.mpu_irqs	= omap2_mcspi1_mpu_irqs,
-	.sdma_reqs	= omap2_mcspi1_sdma_reqs,
-	.main_clk	= "mcspi1_fck",
-	.prcm		= {
-		.omap2 = {
-			.module_offs = CORE_MOD,
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_mcspi_class,
-	.dev_attr	= &omap_mcspi1_dev_attr,
-};
-
-/* mcspi2 */
-static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
-	.num_chipselect = 2,
-};
-
-static struct omap_hwmod omap2430_mcspi2_hwmod = {
-	.name		= "mcspi2",
-	.mpu_irqs	= omap2_mcspi2_mpu_irqs,
-	.sdma_reqs	= omap2_mcspi2_sdma_reqs,
-	.main_clk	= "mcspi2_fck",
-	.prcm		= {
-		.omap2 = {
-			.module_offs = CORE_MOD,
-			.prcm_reg_id = 1,
-			.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
-			.idlest_reg_id = 1,
-			.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
-		},
-	},
-	.class		= &omap2xxx_mcspi_class,
-	.dev_attr	= &omap_mcspi2_dev_attr,
-};
-
 /* mcspi3 */
 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
 	{ .irq = 91 },
@@ -1057,22 +525,22 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
-	.master	= &omap2430_l3_main_hwmod,
-	.slave	= &omap2430_l4_core_hwmod,
+	.master	= &omap2xxx_l3_main_hwmod,
+	.slave	= &omap2xxx_l4_core_hwmod,
 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* MPU -> L3 interface */
 static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
-	.master = &omap2430_mpu_hwmod,
-	.slave	= &omap2430_l3_main_hwmod,
+	.master = &omap2xxx_mpu_hwmod,
+	.slave	= &omap2xxx_l3_main_hwmod,
 	.user	= OCP_USER_MPU,
 };
 
 /* DSS -> l3 */
 static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
-	.master		= &omap2430_dss_core_hwmod,
-	.slave		= &omap2430_l3_main_hwmod,
+	.master		= &omap2xxx_dss_core_hwmod,
+	.slave		= &omap2xxx_l3_main_hwmod,
 	.fw = {
 		.omap2 = {
 			.l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
@@ -1085,14 +553,14 @@ static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
 /* l3_core -> usbhsotg  interface */
 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 	.master		= &omap2430_usbhsotg_hwmod,
-	.slave		= &omap2430_l3_main_hwmod,
+	.slave		= &omap2xxx_l3_main_hwmod,
 	.clk		= "core_l3_ck",
 	.user		= OCP_USER_MPU,
 };
 
 /* L4 CORE -> I2C1 interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_i2c1_hwmod,
 	.clk		= "i2c1_ick",
 	.addr		= omap2_i2c1_addr_space,
@@ -1101,7 +569,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 
 /* L4 CORE -> I2C2 interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_i2c2_hwmod,
 	.clk		= "i2c2_ick",
 	.addr		= omap2_i2c2_addr_space,
@@ -1110,15 +578,15 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
-	.master	= &omap2430_l4_core_hwmod,
-	.slave	= &omap2430_l4_wkup_hwmod,
+	.master	= &omap2xxx_l4_core_hwmod,
+	.slave	= &omap2xxx_l4_wkup_hwmod,
 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L4 CORE -> UART1 interface */
 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_uart1_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_uart1_hwmod,
 	.clk		= "uart1_ick",
 	.addr		= omap2xxx_uart1_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1126,8 +594,8 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 
 /* L4 CORE -> UART2 interface */
 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_uart2_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_uart2_hwmod,
 	.clk		= "uart2_ick",
 	.addr		= omap2xxx_uart2_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1135,8 +603,8 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 
 /* L4 PER -> UART3 interface */
 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_uart3_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_uart3_hwmod,
 	.clk		= "uart3_ick",
 	.addr		= omap2xxx_uart3_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1153,7 +621,7 @@ static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 
 /*  l4_core ->usbhsotg  interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_usbhsotg_hwmod,
 	.clk		= "usb_l4_ick",
 	.addr		= omap2430_usbhsotg_addrs,
@@ -1162,7 +630,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
 
 /* L4 CORE -> MMC1 interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_mmc1_hwmod,
 	.clk		= "mmchs1_ick",
 	.addr		= omap2430_mmc1_addr_space,
@@ -1171,7 +639,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
 
 /* L4 CORE -> MMC2 interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_mmc2_hwmod,
 	.clk		= "mmchs2_ick",
 	.addr		= omap2430_mmc2_addr_space,
@@ -1180,8 +648,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
 
 /* l4 core -> mcspi1 interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_mcspi1_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_mcspi1_hwmod,
 	.clk		= "mcspi1_ick",
 	.addr		= omap2_mcspi1_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1189,8 +657,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
 
 /* l4 core -> mcspi2 interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_mcspi2_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_mcspi2_hwmod,
 	.clk		= "mcspi2_ick",
 	.addr		= omap2_mcspi2_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1198,7 +666,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
 
 /* l4 core -> mcspi3 interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_mcspi3_hwmod,
 	.clk		= "mcspi3_ick",
 	.addr		= omap2430_mcspi3_addr_space,
@@ -1207,7 +675,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 
 /* IVA2 <- L3 interface */
 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
-	.master		= &omap2430_l3_main_hwmod,
+	.master		= &omap2xxx_l3_main_hwmod,
 	.slave		= &omap2430_iva_hwmod,
 	.clk		= "dsp_fck",
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1224,8 +692,8 @@ static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
 
 /* l4_wkup -> timer1 */
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
-	.master		= &omap2430_l4_wkup_hwmod,
-	.slave		= &omap2430_timer1_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_timer1_hwmod,
 	.clk		= "gpt1_ick",
 	.addr		= omap2430_timer1_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1233,8 +701,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 
 /* l4_core -> timer2 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_timer2_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer2_hwmod,
 	.clk		= "gpt2_ick",
 	.addr		= omap2xxx_timer2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1242,8 +710,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
 
 /* l4_core -> timer3 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_timer3_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer3_hwmod,
 	.clk		= "gpt3_ick",
 	.addr		= omap2xxx_timer3_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1251,8 +719,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
 
 /* l4_core -> timer4 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_timer4_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer4_hwmod,
 	.clk		= "gpt4_ick",
 	.addr		= omap2xxx_timer4_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1260,8 +728,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
 
 /* l4_core -> timer5 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_timer5_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer5_hwmod,
 	.clk		= "gpt5_ick",
 	.addr		= omap2xxx_timer5_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1269,8 +737,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
 
 /* l4_core -> timer6 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_timer6_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer6_hwmod,
 	.clk		= "gpt6_ick",
 	.addr		= omap2xxx_timer6_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1278,8 +746,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
 
 /* l4_core -> timer7 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_timer7_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer7_hwmod,
 	.clk		= "gpt7_ick",
 	.addr		= omap2xxx_timer7_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1287,8 +755,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
 
 /* l4_core -> timer8 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_timer8_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer8_hwmod,
 	.clk		= "gpt8_ick",
 	.addr		= omap2xxx_timer8_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1296,8 +764,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
 
 /* l4_core -> timer9 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_timer9_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer9_hwmod,
 	.clk		= "gpt9_ick",
 	.addr		= omap2xxx_timer9_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1305,8 +773,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
 
 /* l4_core -> timer10 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_timer10_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer10_hwmod,
 	.clk		= "gpt10_ick",
 	.addr		= omap2_timer10_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1314,8 +782,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
 
 /* l4_core -> timer11 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_timer11_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer11_hwmod,
 	.clk		= "gpt11_ick",
 	.addr		= omap2_timer11_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1323,8 +791,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
 
 /* l4_core -> timer12 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_timer12_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_timer12_hwmod,
 	.clk		= "gpt12_ick",
 	.addr		= omap2xxx_timer12_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1341,8 +809,8 @@ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
-	.master		= &omap2430_l4_wkup_hwmod,
-	.slave		= &omap2430_wd_timer2_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_wd_timer2_hwmod,
 	.clk		= "mpu_wdt_ick",
 	.addr		= omap2430_wd_timer2_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1350,8 +818,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
 
 /* l4_core -> dss */
 static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_dss_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_core_hwmod,
 	.clk		= "dss_ick",
 	.addr		= omap2_dss_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1359,8 +827,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
 
 /* l4_core -> dss_dispc */
 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_dss_dispc_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_dispc_hwmod,
 	.clk		= "dss_ick",
 	.addr		= omap2_dss_dispc_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1368,8 +836,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
 
 /* l4_core -> dss_rfbi */
 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_dss_rfbi_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_rfbi_hwmod,
 	.clk		= "dss_ick",
 	.addr		= omap2_dss_rfbi_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1377,8 +845,8 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
 
 /* l4_core -> dss_venc */
 static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
-	.master		= &omap2430_l4_core_hwmod,
-	.slave		= &omap2430_dss_venc_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
+	.slave		= &omap2xxx_dss_venc_hwmod,
 	.clk		= "dss_ick",
 	.addr		= omap2_dss_venc_addrs,
 	.flags		= OCPIF_SWSUP_IDLE,
@@ -1396,8 +864,8 @@ static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
-	.master		= &omap2430_l4_wkup_hwmod,
-	.slave		= &omap2430_gpio1_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_gpio1_hwmod,
 	.clk		= "gpios_ick",
 	.addr		= omap2430_gpio1_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1414,8 +882,8 @@ static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
-	.master		= &omap2430_l4_wkup_hwmod,
-	.slave		= &omap2430_gpio2_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_gpio2_hwmod,
 	.clk		= "gpios_ick",
 	.addr		= omap2430_gpio2_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1432,8 +900,8 @@ static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
-	.master		= &omap2430_l4_wkup_hwmod,
-	.slave		= &omap2430_gpio3_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_gpio3_hwmod,
 	.clk		= "gpios_ick",
 	.addr		= omap2430_gpio3_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1450,8 +918,8 @@ static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
-	.master		= &omap2430_l4_wkup_hwmod,
-	.slave		= &omap2430_gpio4_hwmod,
+	.master		= &omap2xxx_l4_wkup_hwmod,
+	.slave		= &omap2xxx_gpio4_hwmod,
 	.clk		= "gpios_ick",
 	.addr		= omap2430_gpio4_addr_space,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1468,7 +936,7 @@ static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_gpio5_hwmod,
 	.clk		= "gpio5_ick",
 	.addr		= omap2430_gpio5_addr_space,
@@ -1478,14 +946,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
 /* dma_system -> L3 */
 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
 	.master		= &omap2430_dma_system_hwmod,
-	.slave		= &omap2430_l3_main_hwmod,
+	.slave		= &omap2xxx_l3_main_hwmod,
 	.clk		= "core_l3_ck",
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4_core -> dma_system */
 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_dma_system_hwmod,
 	.clk		= "sdma_ick",
 	.addr		= omap2_dma_system_addrs,
@@ -1494,7 +962,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
 
 /* l4_core -> mailbox */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_mailbox_hwmod,
 	.addr		= omap2_mailbox_addrs,
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
@@ -1502,7 +970,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
 
 /* l4_core -> mcbsp1 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_mcbsp1_hwmod,
 	.clk		= "mcbsp1_ick",
 	.addr		= omap2_mcbsp1_addrs,
@@ -1511,7 +979,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
 
 /* l4_core -> mcbsp2 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_mcbsp2_hwmod,
 	.clk		= "mcbsp2_ick",
 	.addr		= omap2xxx_mcbsp2_addrs,
@@ -1530,7 +998,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
 
 /* l4_core -> mcbsp3 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_mcbsp3_hwmod,
 	.clk		= "mcbsp3_ick",
 	.addr		= omap2430_mcbsp3_addrs,
@@ -1549,7 +1017,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
 
 /* l4_core -> mcbsp4 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_mcbsp4_hwmod,
 	.clk		= "mcbsp4_ick",
 	.addr		= omap2430_mcbsp4_addrs,
@@ -1568,7 +1036,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
 
 /* l4_core -> mcbsp5 */
 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
-	.master		= &omap2430_l4_core_hwmod,
+	.master		= &omap2xxx_l4_core_hwmod,
 	.slave		= &omap2430_mcbsp5_hwmod,
 	.clk		= "mcbsp5_ick",
 	.addr		= omap2430_mcbsp5_addrs,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 2a67297..45aaa07 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -10,6 +10,7 @@
  */
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
+#include <plat/gpio.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
 #include <plat/mcspi.h>
@@ -17,6 +18,8 @@
 #include <mach/irqs.h>
 
 #include "omap_hwmod_common_data.h"
+#include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
 #include "wd_timer.h"
 
 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
@@ -170,3 +173,562 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
 	.sysc	= &omap2xxx_mcspi_sysc,
 	.rev	= OMAP2_MCSPI_REV,
 };
+
+/*
+ * IP blocks
+ */
+
+/* L3 */
+struct omap_hwmod omap2xxx_l3_main_hwmod = {
+	.name		= "l3_main",
+	.class		= &l3_hwmod_class,
+	.flags		= HWMOD_NO_IDLEST,
+};
+
+/* L4 CORE */
+struct omap_hwmod omap2xxx_l4_core_hwmod = {
+	.name		= "l4_core",
+	.class		= &l4_hwmod_class,
+	.flags		= HWMOD_NO_IDLEST,
+};
+
+/* L4 WKUP */
+struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
+	.name		= "l4_wkup",
+	.class		= &l4_hwmod_class,
+	.flags		= HWMOD_NO_IDLEST,
+};
+
+/* MPU */
+struct omap_hwmod omap2xxx_mpu_hwmod = {
+	.name		= "mpu",
+	.class		= &mpu_hwmod_class,
+	.main_clk	= "mpu_ck",
+};
+
+/* IVA2 */
+struct omap_hwmod omap2xxx_iva_hwmod = {
+	.name		= "iva",
+	.class		= &iva_hwmod_class,
+};
+
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+	.timer_capability       = OMAP_TIMER_ALWON,
+};
+
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+	.timer_capability       = OMAP_TIMER_HAS_PWM,
+};
+
+/* timer1 */
+
+struct omap_hwmod omap2xxx_timer1_hwmod = {
+	.name		= "timer1",
+	.mpu_irqs	= omap2_timer1_mpu_irqs,
+	.main_clk	= "gpt1_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT1_SHIFT,
+			.module_offs = WKUP_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_alwon_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* timer2 */
+
+struct omap_hwmod omap2xxx_timer2_hwmod = {
+	.name		= "timer2",
+	.mpu_irqs	= omap2_timer2_mpu_irqs,
+	.main_clk	= "gpt2_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT2_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_alwon_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* timer3 */
+
+struct omap_hwmod omap2xxx_timer3_hwmod = {
+	.name		= "timer3",
+	.mpu_irqs	= omap2_timer3_mpu_irqs,
+	.main_clk	= "gpt3_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT3_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_alwon_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* timer4 */
+
+struct omap_hwmod omap2xxx_timer4_hwmod = {
+	.name		= "timer4",
+	.mpu_irqs	= omap2_timer4_mpu_irqs,
+	.main_clk	= "gpt4_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT4_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_alwon_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* timer5 */
+
+struct omap_hwmod omap2xxx_timer5_hwmod = {
+	.name		= "timer5",
+	.mpu_irqs	= omap2_timer5_mpu_irqs,
+	.main_clk	= "gpt5_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT5_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_alwon_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* timer6 */
+
+struct omap_hwmod omap2xxx_timer6_hwmod = {
+	.name		= "timer6",
+	.mpu_irqs	= omap2_timer6_mpu_irqs,
+	.main_clk	= "gpt6_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT6_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_alwon_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* timer7 */
+
+struct omap_hwmod omap2xxx_timer7_hwmod = {
+	.name		= "timer7",
+	.mpu_irqs	= omap2_timer7_mpu_irqs,
+	.main_clk	= "gpt7_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT7_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_alwon_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* timer8 */
+
+struct omap_hwmod omap2xxx_timer8_hwmod = {
+	.name		= "timer8",
+	.mpu_irqs	= omap2_timer8_mpu_irqs,
+	.main_clk	= "gpt8_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT8_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_alwon_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* timer9 */
+
+struct omap_hwmod omap2xxx_timer9_hwmod = {
+	.name		= "timer9",
+	.mpu_irqs	= omap2_timer9_mpu_irqs,
+	.main_clk	= "gpt9_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT9_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_pwm_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* timer10 */
+
+struct omap_hwmod omap2xxx_timer10_hwmod = {
+	.name		= "timer10",
+	.mpu_irqs	= omap2_timer10_mpu_irqs,
+	.main_clk	= "gpt10_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT10_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_pwm_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* timer11 */
+
+struct omap_hwmod omap2xxx_timer11_hwmod = {
+	.name		= "timer11",
+	.mpu_irqs	= omap2_timer11_mpu_irqs,
+	.main_clk	= "gpt11_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT11_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_pwm_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* timer12 */
+
+struct omap_hwmod omap2xxx_timer12_hwmod = {
+	.name		= "timer12",
+	.mpu_irqs	= omap2xxx_timer12_mpu_irqs,
+	.main_clk	= "gpt12_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPT12_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
+		},
+	},
+	.dev_attr	= &capability_pwm_dev_attr,
+	.class		= &omap2xxx_timer_hwmod_class,
+};
+
+/* wd_timer2 */
+struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
+	.name		= "wd_timer2",
+	.class		= &omap2xxx_wd_timer_hwmod_class,
+	.main_clk	= "mpu_wdt_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+			.module_offs = WKUP_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
+		},
+	},
+};
+
+/* UART1 */
+
+struct omap_hwmod omap2xxx_uart1_hwmod = {
+	.name		= "uart1",
+	.mpu_irqs	= omap2_uart1_mpu_irqs,
+	.sdma_reqs	= omap2_uart1_sdma_reqs,
+	.main_clk	= "uart1_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_UART1_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+		},
+	},
+	.class		= &omap2_uart_class,
+};
+
+/* UART2 */
+
+struct omap_hwmod omap2xxx_uart2_hwmod = {
+	.name		= "uart2",
+	.mpu_irqs	= omap2_uart2_mpu_irqs,
+	.sdma_reqs	= omap2_uart2_sdma_reqs,
+	.main_clk	= "uart2_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_UART2_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+		},
+	},
+	.class		= &omap2_uart_class,
+};
+
+/* UART3 */
+
+struct omap_hwmod omap2xxx_uart3_hwmod = {
+	.name		= "uart3",
+	.mpu_irqs	= omap2_uart3_mpu_irqs,
+	.sdma_reqs	= omap2_uart3_sdma_reqs,
+	.main_clk	= "uart3_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 2,
+			.module_bit = OMAP24XX_EN_UART3_SHIFT,
+			.idlest_reg_id = 2,
+			.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+		},
+	},
+	.class		= &omap2_uart_class,
+};
+
+/* dss */
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+	/*
+	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+	 * driver does not use these clocks.
+	 */
+	{ .role = "tv_clk", .clk = "dss_54m_fck" },
+	{ .role = "sys_clk", .clk = "dss2_fck" },
+};
+
+struct omap_hwmod omap2xxx_dss_core_hwmod = {
+	.name		= "dss_core",
+	.class		= &omap2_dss_hwmod_class,
+	.main_clk	= "dss1_fck", /* instead of dss_fck */
+	.sdma_reqs	= omap2xxx_dss_sdma_chs,
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+		},
+	},
+	.opt_clks	= dss_opt_clks,
+	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+	.flags		= HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+};
+
+struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
+	.name		= "dss_dispc",
+	.class		= &omap2_dispc_hwmod_class,
+	.mpu_irqs	= omap2_dispc_irqs,
+	.main_clk	= "dss1_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
+			.module_offs = CORE_MOD,
+			.idlest_reg_id = 1,
+			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+		},
+	},
+	.flags		= HWMOD_NO_IDLEST,
+	.dev_attr	= &omap2_3_dss_dispc_dev_attr
+};
+
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+	{ .role = "ick", .clk = "dss_ick" },
+};
+
+struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
+	.name		= "dss_rfbi",
+	.class		= &omap2_rfbi_hwmod_class,
+	.main_clk	= "dss1_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
+			.module_offs = CORE_MOD,
+		},
+	},
+	.opt_clks	= dss_rfbi_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
+	.flags		= HWMOD_NO_IDLEST,
+};
+
+struct omap_hwmod omap2xxx_dss_venc_hwmod = {
+	.name		= "dss_venc",
+	.class		= &omap2_venc_hwmod_class,
+	.main_clk	= "dss_54m_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
+			.module_offs = CORE_MOD,
+		},
+	},
+	.flags		= HWMOD_NO_IDLEST,
+};
+
+/* gpio dev_attr */
+struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
+	.bank_width = 32,
+	.dbck_flag = false,
+};
+
+/* gpio1 */
+struct omap_hwmod omap2xxx_gpio1_hwmod = {
+	.name		= "gpio1",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.mpu_irqs	= omap2_gpio1_irqs,
+	.main_clk	= "gpios_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+			.module_offs = WKUP_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+		},
+	},
+	.class		= &omap2xxx_gpio_hwmod_class,
+	.dev_attr	= &omap2xxx_gpio_dev_attr,
+};
+
+/* gpio2 */
+struct omap_hwmod omap2xxx_gpio2_hwmod = {
+	.name		= "gpio2",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.mpu_irqs	= omap2_gpio2_irqs,
+	.main_clk	= "gpios_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+			.module_offs = WKUP_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+		},
+	},
+	.class		= &omap2xxx_gpio_hwmod_class,
+	.dev_attr	= &omap2xxx_gpio_dev_attr,
+};
+
+/* gpio3 */
+struct omap_hwmod omap2xxx_gpio3_hwmod = {
+	.name		= "gpio3",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.mpu_irqs	= omap2_gpio3_irqs,
+	.main_clk	= "gpios_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+			.module_offs = WKUP_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+		},
+	},
+	.class		= &omap2xxx_gpio_hwmod_class,
+	.dev_attr	= &omap2xxx_gpio_dev_attr,
+};
+
+/* gpio4 */
+struct omap_hwmod omap2xxx_gpio4_hwmod = {
+	.name		= "gpio4",
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+	.mpu_irqs	= omap2_gpio4_irqs,
+	.main_clk	= "gpios_fck",
+	.prcm		= {
+		.omap2 = {
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+			.module_offs = WKUP_MOD,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+		},
+	},
+	.class		= &omap2xxx_gpio_hwmod_class,
+	.dev_attr	= &omap2xxx_gpio_dev_attr,
+};
+
+/* mcspi1 */
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+	.num_chipselect = 4,
+};
+
+struct omap_hwmod omap2xxx_mcspi1_hwmod = {
+	.name		= "mcspi1",
+	.mpu_irqs	= omap2_mcspi1_mpu_irqs,
+	.sdma_reqs	= omap2_mcspi1_sdma_reqs,
+	.main_clk	= "mcspi1_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
+		},
+	},
+	.class		= &omap2xxx_mcspi_class,
+	.dev_attr	= &omap_mcspi1_dev_attr,
+};
+
+/* mcspi2 */
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+	.num_chipselect = 2,
+};
+
+struct omap_hwmod omap2xxx_mcspi2_hwmod = {
+	.name		= "mcspi2",
+	.mpu_irqs	= omap2_mcspi2_mpu_irqs,
+	.sdma_reqs	= omap2_mcspi2_sdma_reqs,
+	.main_clk	= "mcspi2_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
+		},
+	},
+	.class		= &omap2xxx_mcspi_class,
+	.dev_attr	= &omap_mcspi2_dev_attr,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index ad5d8f0..65757f3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -54,6 +54,38 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
 /* Common IP block data across OMAP2xxx */
 extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
 extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
+extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
+extern struct omap_hwmod omap2xxx_l3_main_hwmod;
+extern struct omap_hwmod omap2xxx_l4_core_hwmod;
+extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
+extern struct omap_hwmod omap2xxx_mpu_hwmod;
+extern struct omap_hwmod omap2xxx_iva_hwmod;
+extern struct omap_hwmod omap2xxx_timer1_hwmod;
+extern struct omap_hwmod omap2xxx_timer2_hwmod;
+extern struct omap_hwmod omap2xxx_timer3_hwmod;
+extern struct omap_hwmod omap2xxx_timer4_hwmod;
+extern struct omap_hwmod omap2xxx_timer5_hwmod;
+extern struct omap_hwmod omap2xxx_timer6_hwmod;
+extern struct omap_hwmod omap2xxx_timer7_hwmod;
+extern struct omap_hwmod omap2xxx_timer8_hwmod;
+extern struct omap_hwmod omap2xxx_timer9_hwmod;
+extern struct omap_hwmod omap2xxx_timer10_hwmod;
+extern struct omap_hwmod omap2xxx_timer11_hwmod;
+extern struct omap_hwmod omap2xxx_timer12_hwmod;
+extern struct omap_hwmod omap2xxx_wd_timer2_hwmod;
+extern struct omap_hwmod omap2xxx_uart1_hwmod;
+extern struct omap_hwmod omap2xxx_uart2_hwmod;
+extern struct omap_hwmod omap2xxx_uart3_hwmod;
+extern struct omap_hwmod omap2xxx_dss_core_hwmod;
+extern struct omap_hwmod omap2xxx_dss_dispc_hwmod;
+extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod;
+extern struct omap_hwmod omap2xxx_dss_venc_hwmod;
+extern struct omap_hwmod omap2xxx_gpio1_hwmod;
+extern struct omap_hwmod omap2xxx_gpio2_hwmod;
+extern struct omap_hwmod omap2xxx_gpio3_hwmod;
+extern struct omap_hwmod omap2xxx_gpio4_hwmod;
+extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
+extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
 
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];




From paul at pwsan.com  Wed Mar  7 21:55:27 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 7 Mar 2012 19:55:27 -0700 (MST)
Subject: [PATCH 00/12] ARM: OMAP2+: hwmod: remove link arrays
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <alpine.DEB.2.00.1203071954100.12760@utopia.booyaka.com>


Hi

a couple of these patches are too big to make it through the lists, so the 
entire series has been posted here:

http://www.pwsan.com/omap/patches-hwmod_remove_link_arrays_cleanup_3.4/


- Paul


From rnayak at ti.com  Wed Mar  7 22:11:13 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 08 Mar 2012 08:41:13 +0530
Subject: [PATCH v2 0/6] mmc: omap_hsmmc: Clean up use/abuse of pdev->id
In-Reply-To: <m2pqcoihhu.fsf@bob.laptop.org>
References: <1329996409-26861-1-git-send-email-rnayak@ti.com>	<4F476228.7060607@ti.com>
 <4F54714E.6080805@ti.com>	<4F57312E.4080104@ti.com>
 <m2pqcoihhu.fsf@bob.laptop.org>
Message-ID: <4F582351.3080805@ti.com>

On Wednesday 07 March 2012 08:29 PM, Chris Ball wrote:
> Hi Rajendra,
>
> On Wed, Mar 07 2012, Rajendra Nayak wrote:
>>> Chris, Ping. I am basing my DT support patches on top of these cleanups.
>>> Would be great if you can have a look and pull them in.
>>
>> Chris, just realized the last two requests from me to get this merged
>> weren't addressed to you directly, but instead you were copied.
>> Resending with you in 'To', hope this lands in your inbox :)
>
> Sorry for the delay, thanks for the ping; I've pushed these to mmc-next
> for 3.4 now.

Great, thanks Chris.

>
> Thanks,
>
> - Chris.



From tarun.kanti at ti.com  Wed Mar  7 22:34:27 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Thu, 8 Mar 2012 09:04:27 +0530
Subject: [PATCH v3 10/13] gpio/omap: fix missing dataout context save in
 _set_gpio_dataout_reg
In-Reply-To: <4F574EA6.4000807@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-11-git-send-email-tarun.kanti@ti.com>
 <4F574EA6.4000807@ti.com>
Message-ID: <CAC83ZvKuOfd3kxJSdsU2W_si92zzAOn+gpvLAcVOfPdsEH8+gA@mail.gmail.com>

On Wed, Mar 7, 2012 at 5:33 PM, Santosh Shilimkar
<santosh.shilimkar at ti.com> wrote:
> On Wednesday 07 March 2012 12:16 PM, Tarun Kanti DebBarma wrote:
>> There are two functions, _set_gpio_dataout_reg() and _set_gpio_dataout_mask()
>> which writes to dataout register and the dataout context must be saved.
>> It is missing in the first function, _set_gpio_dataout_reg(). Fix this.
>>
>> Reported-by: Govindraj Raja <govindraj.raja at ti.com>
>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>> ---
> Good catch. Is the suspend/resume caught this issue?
That's right.
--
Tarun
>
> This can go as a fix as well.
>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>
> Regards
> Santosh


From tony at atomide.com  Wed Mar  7 22:34:40 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 19:34:40 -0800
Subject: Latest OMAP4 build errors
In-Reply-To: <20120307234308.GA20364@n2100.arm.linux.org.uk>
References: <20120228090209.GC18045@n2100.arm.linux.org.uk>
 <CAK=WgbZEDr_fYSonBQr3XNcTx5vefsH7LJfqycaxsqg-yechWQ@mail.gmail.com>
 <20120306165545.GB15392@n2100.arm.linux.org.uk>
 <201203061701.54141.arnd@arndb.de>
 <20120307100615.GA17404@n2100.arm.linux.org.uk>
 <20120307171044.GE12083@atomide.com>
 <CAOesGMiNSyc9F+Wf5pXPG=hRAfnG6aMHtccLBwvekuB3HpyevQ@mail.gmail.com>
 <20120307224459.GJ12083@atomide.com>
 <20120307234308.GA20364@n2100.arm.linux.org.uk>
Message-ID: <20120308033439.GR12083@atomide.com>

* Russell King - ARM Linux <linux at arm.linux.org.uk> [120307 15:11]:
> On Wed, Mar 07, 2012 at 02:44:59PM -0800, Tony Lindgren wrote:
> > OK thanks, will do that next time if there's something urgent.
> > 
> > I'll send a pull request shortly for fixes-non-critical-part2 that
> > should sort out the remaining issues.
> 
> FYI, I've just updated the build tree with what's in arm-soc (as of
> a couple of minutes ago), which contained a bunch of OMAP updates, so
> I'm hopeful that tomorrows results should show an improvement.
> 
> It'll start its run in about 2h20.

Looks like there one new section warning with omap_hsmmc_init_one
depending on the compiler. I'll post a fix for that.

Not seeing that with codesourcery/linaro compilers, but seeing
with the emdebian gcc 4.3.5.

Regards,

Tony


From tony at atomide.com  Wed Mar  7 22:37:04 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 7 Mar 2012 19:37:04 -0800
Subject: [PATCH] ARM: OMAP2+: Fix section warnings for hsmmc_init_one
Message-ID: <20120308033703.GS12083@atomide.com>

From: Tony Lindgren <tony at atomide.com>
Date: Wed, 7 Mar 2012 18:54:24 -0800
Subject: [PATCH] ARM: OMAP2+: Fix section warnings for hsmmc_init_one

Otherwise we can get the following error depending on
the compiler:

WARNING: arch/arm/mach-omap2/built-in.o(.text+0xafe0):
Section mismatch in reference from the function omap_hsmmc_init_one()
to the function .init.text:omap_hsmmc_pdata_init()
The function omap_hsmmc_init_one() references
the function __init omap_hsmmc_pdata_init().
This is often because omap_hsmmc_init_one lacks a __init
annotation or the annotation of omap_hsmmc_pdata_init is wrong.

Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -466,7 +466,7 @@ void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
 
 #define MAX_OMAP_MMC_HWMOD_NAME_LEN		16
 
-static void omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
+static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
 					int ctrl_nr)
 {
 	struct omap_hwmod *oh;


From rnayak at ti.com  Wed Mar  7 22:46:01 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 08 Mar 2012 09:16:01 +0530
Subject: [PATCH v2 1/4] mmc: omap_hsmmc: Convert hsmmc driver to use device
 tree
In-Reply-To: <1329998490-27555-2-git-send-email-rnayak@ti.com>
References: <1329998490-27555-1-git-send-email-rnayak@ti.com>
 <1329998490-27555-2-git-send-email-rnayak@ti.com>
Message-ID: <4F582B79.60001@ti.com>

Hi Rob/Grant,

On Thursday 23 February 2012 05:31 PM, Rajendra Nayak wrote:
> Define dt bindings for the ti-omap-hsmmc, and adapt
> the driver to extract data (which was earlier passed as
> platform_data) from device tree.

Any comments on these bindings for omap hsmmc? All the dependent
patches/series on which this series was based have now made it to
the respective -next of Mark and Chris.

regards,
Rajendra

>
> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
> ---
>   .../devicetree/bindings/mmc/ti-omap-hsmmc.txt      |   31 +++++++++
>   drivers/mmc/host/omap_hsmmc.c                      |   68 ++++++++++++++++++++
>   2 files changed, 99 insertions(+), 0 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>
> diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> new file mode 100644
> index 0000000..e4fa8f0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> @@ -0,0 +1,31 @@
> +* TI Highspeed MMC host controller for OMAP
> +
> +The Highspeed MMC Host Controller on TI OMAP family
> +provides an interface for MMC, SD, and SDIO types of memory cards.
> +
> +Required properties:
> +- compatible:
> + Should be "ti,omap2-hsmmc", for OMAP2/3 controllers
> + Should be "ti,omap4-hsmmc", for OMAP4 controllers
> +- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
> +- reg : should contain hsmmc registers location and length
> +
> +Optional properties:
> +ti,dual-volt: boolean, supports dual voltage cards
> +<supply-name>-supply: phandle to the regulator device tree node
> +"supply-name" examples are "vmmc", "vmmc_aux" etc
> +ti,bus-width: Number of data lines, default assumed is 1 if the property is missing.
> +cd-gpios: GPIOs for card detection
> +wp-gpios: GPIOs for write protection
> +ti,non-removable: non-removable slot (like eMMC)
> +
> +Example:
> +	mmc1: mmc at 0x4809c000 {
> +		compatible = "ti,omap4-hsmmc";
> +		reg =<0x4809c000 0x400>;
> +		ti,hwmods = "mmc1";
> +		ti,dual-volt;
> +		ti,bus-width =<4>;
> +		vmmc-supply =<&vmmc>; /* phandle to regulator node */
> +		ti,non-removable;
> +	};
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index 35f6dc1..0c93d58 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -26,6 +26,9 @@
>   #include<linux/platform_device.h>
>   #include<linux/timer.h>
>   #include<linux/clk.h>
> +#include<linux/of.h>
> +#include<linux/of_gpio.h>
> +#include<linux/of_device.h>
>   #include<linux/mmc/host.h>
>   #include<linux/mmc/core.h>
>   #include<linux/mmc/mmc.h>
> @@ -1718,6 +1721,46 @@ static void omap_hsmmc_debugfs(struct mmc_host *mmc)
>
>   #endif
>
> +#ifdef CONFIG_OF
> +static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
> +{
> +	struct omap_mmc_platform_data *pdata;
> +	struct device_node *np = dev->of_node;
> +	u32 bus_width;
> +
> +	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata)
> +		return NULL; /* out of memory */
> +
> +	if (of_find_property(np, "ti,dual-volt", NULL))
> +		pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
> +
> +	/* This driver only supports 1 slot */
> +	pdata->nr_slots = 1;
> +	pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
> +	pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
> +
> +	if (of_find_property(np, "ti,non-removable", NULL)) {
> +		pdata->slots[0].nonremovable = true;
> +		pdata->slots[0].no_regulator_off_init = true;
> +	}
> +	of_property_read_u32(np, "ti,bus-width",&bus_width);
> +	if (bus_width == 4)
> +		pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
> +	else if (bus_width == 8)
> +		pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
> +	return pdata;
> +}
> +#else
> +static inline struct omap_mmc_platform_data
> +			*of_get_hsmmc_pdata(struct device *dev)
> +{
> +	return NULL;
> +}
> +#endif
> +
> +static const struct of_device_id omap_mmc_of_match[];
> +
>   static int __init omap_hsmmc_probe(struct platform_device *pdev)
>   {
>   	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
> @@ -1725,6 +1768,14 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>   	struct omap_hsmmc_host *host = NULL;
>   	struct resource *res;
>   	int ret, irq;
> +	const struct of_device_id *match;
> +
> +	match = of_match_device(omap_mmc_of_match,&pdev->dev);
> +	if (match) {
> +		pdata = of_get_hsmmc_pdata(&pdev->dev);
> +		if (match->data)
> +			pdata->reg_offset = *(u16 *)match->data;
> +	}
>
>   	if (pdata == NULL) {
>   		dev_err(&pdev->dev, "Platform Data is missing\n");
> @@ -2120,12 +2171,29 @@ static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
>   	.runtime_resume = omap_hsmmc_runtime_resume,
>   };
>
> +#if defined(CONFIG_OF)
> +static u16 omap4_reg_offset = 0x100;
> +
> +static const struct of_device_id omap_mmc_of_match[] = {
> +	{
> +		.compatible = "ti,omap2-hsmmc",
> +	},
> +	{
> +		.compatible = "ti,omap4-hsmmc",
> +		.data =&omap4_reg_offset,
> +	},
> +	{},
> +}
> +MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
> +#endif
> +
>   static struct platform_driver omap_hsmmc_driver = {
>   	.remove		= omap_hsmmc_remove,
>   	.driver		= {
>   		.name = DRIVER_NAME,
>   		.owner = THIS_MODULE,
>   		.pm =&omap_hsmmc_dev_pm_ops,
> +		.of_match_table = of_match_ptr(omap_mmc_of_match),
>   	},
>   };
>



From tarun.kanti at ti.com  Wed Mar  7 22:58:53 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Thu, 8 Mar 2012 09:28:53 +0530
Subject: [PATCH v3 12/13] gpio/omap: fix incorrect context restore logic
 in omap_gpio_runtime_resume
In-Reply-To: <4F574F95.7090801@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-13-git-send-email-tarun.kanti@ti.com>
 <4F574F95.7090801@ti.com>
Message-ID: <CAC83ZvLFoSppTiPw-_a=z_Mnpmk6nHeaadTShdJP8RpDWh9TLg@mail.gmail.com>

On Wed, Mar 7, 2012 at 5:37 PM, Santosh Shilimkar
<santosh.shilimkar at ti.com> wrote:
> On Wednesday 07 March 2012 12:16 PM, Tarun Kanti DebBarma wrote:
>> In omap_gpio_runtime_resume() the context restore should be independent
>> of bank->enabled_non_wakeup_gpios. This was preventing context restore
>> of GPIO lines which are not wakeup enabled.
>>
>> Reported-by: Govindraj Raja <govindraj.raja at ti.com>
>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>> ---
>> ?drivers/gpio/gpio-omap.c | ? ?2 +-
>> ?1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
>> index 2e8e476..ccfbae0 100644
>> --- a/drivers/gpio/gpio-omap.c
>> +++ b/drivers/gpio/gpio-omap.c
>> @@ -1227,7 +1227,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
>> ? ? ? __raw_writel(bank->context.risingdetect,
>> ? ? ? ? ? ? ? ? ? ?bank->base + bank->regs->risingdetect);
>>
>> - ? ? if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
>> + ? ? if (!bank->workaround_enabled) {
> This doesn't seem to be right.
> Don't you want to avoid GPIO restore for banks which are in
> always on domain. Infact the purpose of "enabled_non_wakeup_gpios"
> is exactly that ? Isn't it.
>
> What am I missing ?
The bank->enabled_non_wakeup_gpios is set whenever a gpio line is programmed
as edge trigger as shown below.
(This is not meant to distinguish between gpios in WKUP domain vs
those in PER domain).
The context restore should happen irrespective of whether the trigger
type is edge or level.
In fact context restore was not happening for a gpio line because of
this condition while
testing suspend/resume.

[...]
                if (trigger & IRQ_TYPE_EDGE_BOTH)
                        bank->enabled_non_wakeup_gpios |= gpio_bit;
                else
                        bank->enabled_non_wakeup_gpios &= ~gpio_bit;
[...]
--
Tarun

>
> Regards
> Santosh


From paul at pwsan.com  Wed Mar  7 23:02:13 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 7 Mar 2012 21:02:13 -0700 (MST)
Subject: [GIT PULL] ARM: OMAP2+: hwmod/timer: first set of cleanups for 3.4
Message-ID: <alpine.DEB.2.00.1203072054470.12760@utopia.booyaka.com>

Hi Tony 

The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:

  Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)

are available in the git repository at:

  git://git.pwsan.com/linux-2.6 hwmod_code_cleanup_3.4

for you to fetch changes up to b8a633451951d149494076393698880453bf6bfe:

  ARM: OMAP: hwmod: add softreset delay field and OMAP4 data (2012-02-28 03:46:31 -0700)


- Paul

----------------------------------------------------------------
Fernando Guzman Lugo (1):
      ARM: OMAP: hwmod: add softreset delay field and OMAP4 data

Paul Walmsley (8):
      ARM: OMAP2+: hwmod: control all hardreset lines attached to a hwmod
      ARM: OMAP4: hwmod data: remove pseudo-hwmods associated with hardreset lines
      ARM: OMAP2+: hwmod: reorganize and document the setup process
      ARM: OMAP2+: hwmod: revise hardreset behavior
      ARM: OMAP2+: hwmod: ensure that SYSCONFIG bits are reprogrammed after a reset
      ARM: OMAP2+: hwmod: provide a function to return the address space of the MPU RT
      ARM: OMAP2+: hwmod: add omap_hwmod_get_resource_byname()
      ARM: OMAP2+: timer: use a proper interface to get hwmod data

 arch/arm/mach-omap2/omap_hwmod.c             |  674 +++++++++++++++++++-------
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c   |  119 +----
 arch/arm/mach-omap2/timer.c                  |   15 +-
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    6 +-
 4 files changed, 544 insertions(+), 270 deletions(-)


From paul at pwsan.com  Wed Mar  7 23:06:15 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 7 Mar 2012 21:06:15 -0700 (MST)
Subject: [GIT PULL] ARM: OMAP2+: hwmod data: cleanup in preparation for link
 array removal
Message-ID: <alpine.DEB.2.00.1203072102150.21662@utopia.booyaka.com>

Hi Tony

The following changes since commit b8a633451951d149494076393698880453bf6bfe:

  ARM: OMAP: hwmod: add softreset delay field and OMAP4 data (2012-02-28 03:46:31 -0700)

are available in the git repository at:

  git://git.pwsan.com/linux-2.6 hwmod_data_cleanup_3.4

for you to fetch changes up to a2d4b88dd32b02e8b5088e0d64b3c102c0852210:

  ARM: OMAP2+: hwmod: extend OCP_* register offsets from 16 to 32 bits (2012-02-28 03:49:34 -0700)

(This branch is based on the 'hwmod_code_cleanup_3.4' branch, pull req 
sent previously)


- Paul

----------------------------------------------------------------
Paul Walmsley (9):
      ARM: OMAP2/3: hwmod data: update old names
      ARM: OMAP3: hwmod data: fix interfaces for the MMC hwmods
      ARM: OMAP3: hwmod data: add DSS->L3 interconnect for 3430ES1
      ARM: OMAP3: hwmod data: GPTIMER12 is attached to a separate interconnect
      ARM: OMAP36xx: hwmod data: fix SmartReflex interface data
      ARM: OMAP4: hwmod data: remove bandgap hwmod
      ARM: OMAP4: hwmod data: add OCP_USER_DSP; mark omap44xx_dsp__iva appropriately
      ARM: OMAP4: hwmod data: uncomment some "excluded" hwmods
      ARM: OMAP2+: hwmod: extend OCP_* register offsets from 16 to 32 bits

 arch/arm/mach-omap2/omap_hwmod_2420_data.c   |    4 +-
 arch/arm/mach-omap2/omap_hwmod_2430_data.c   |    6 +-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c   |  137 ++++++++++++++++++++------
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c   |   39 +-------
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    7 +-
 5 files changed, 121 insertions(+), 72 deletions(-)


From sfr at canb.auug.org.au  Thu Mar  8 00:51:16 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 8 Mar 2012 16:51:16 +1100
Subject: linux-next: manual merge of the arm-soc tree with the omap_dss2 tree
Message-ID: <20120308165116.d400947f35e40a923e9c6ad0@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-omap1/board-ams-delta.c between commit ddba6c7f7ec6
("OMAP1: pass LCD config with omapfb_set_lcd_config()") from the
omap_dss2 tree and commits 5ca6180fa6d7 ("ARM: OMAP1: ams-delta:
supersede custom led device by leds-gpio") and 2e3ee9f45b3c ("ARM: OMAP1:
Move most of plat/io.h into local iomap.h") from the arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-omap1/board-ams-delta.c
index e0e8245,c847597..0000000
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@@ -20,7 -21,7 +21,8 @@@
  #include <linux/platform_device.h>
  #include <linux/serial_8250.h>
  #include <linux/export.h>
 +#include <linux/omapfb.h>
+ #include <linux/io.h>
  
  #include <media/soc_camera.h>
  
@@@ -170,6 -162,117 +163,113 @@@ static struct omap_usb_config ams_delta
  	.pins[0]	= 2,
  };
  
 -static struct omap_board_config_kernel ams_delta_config[] __initdata = {
 -	{ OMAP_TAG_LCD,		&ams_delta_lcd_config },
 -};
 -
+ #define LATCH1_GPIO_BASE	232
+ #define LATCH1_NGPIO		8
+ 
+ static struct resource latch1_resources[] __initconst = {
+ 	[0] = {
+ 		.name	= "dat",
+ 		.start	= LATCH1_PHYS,
+ 		.end	= LATCH1_PHYS + (LATCH1_NGPIO - 1) / 8,
+ 		.flags	= IORESOURCE_MEM,
+ 	},
+ };
+ 
+ static struct bgpio_pdata latch1_pdata __initconst = {
+ 	.base	= LATCH1_GPIO_BASE,
+ 	.ngpio	= LATCH1_NGPIO,
+ };
+ 
+ static struct platform_device latch1_gpio_device = {
+ 	.name		= "basic-mmio-gpio",
+ 	.id		= 0,
+ 	.resource	= latch1_resources,
+ 	.num_resources	= ARRAY_SIZE(latch1_resources),
+ 	.dev		= {
+ 		.platform_data	= &latch1_pdata,
+ 	},
+ };
+ 
+ static struct resource latch2_resources[] __initconst = {
+ 	[0] = {
+ 		.name	= "dat",
+ 		.start	= LATCH2_PHYS,
+ 		.end	= LATCH2_PHYS + (AMS_DELTA_LATCH2_NGPIO - 1) / 8,
+ 		.flags	= IORESOURCE_MEM,
+ 	},
+ };
+ 
+ static struct bgpio_pdata latch2_pdata __initconst = {
+ 	.base	= AMS_DELTA_LATCH2_GPIO_BASE,
+ 	.ngpio	= AMS_DELTA_LATCH2_NGPIO,
+ };
+ 
+ static struct platform_device latch2_gpio_device = {
+ 	.name		= "basic-mmio-gpio",
+ 	.id		= 1,
+ 	.resource	= latch2_resources,
+ 	.num_resources	= ARRAY_SIZE(latch2_resources),
+ 	.dev		= {
+ 		.platform_data	= &latch2_pdata,
+ 	},
+ };
+ 
+ static struct gpio latch_gpios[] __initconst = {
+ 	{
+ 		.gpio	= LATCH1_GPIO_BASE + 6,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "dockit1",
+ 	},
+ 	{
+ 		.gpio	= LATCH1_GPIO_BASE + 7,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "dockit2",
+ 	},
+ 	{
+ 		.gpio	= AMS_DELTA_GPIO_PIN_SCARD_RSTIN,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "scard_rstin",
+ 	},
+ 	{
+ 		.gpio	= AMS_DELTA_GPIO_PIN_SCARD_CMDVCC,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "scard_cmdvcc",
+ 	},
+ 	{
+ 		.gpio	= AMS_DELTA_GPIO_PIN_MODEM_NRESET,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "modem_nreset",
+ 	},
+ 	{
+ 		.gpio	= AMS_DELTA_GPIO_PIN_MODEM_CODEC,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "modem_codec",
+ 	},
+ 	{
+ 		.gpio	= AMS_DELTA_LATCH2_GPIO_BASE + 14,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "hookflash1",
+ 	},
+ 	{
+ 		.gpio	= AMS_DELTA_LATCH2_GPIO_BASE + 15,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "hookflash2",
+ 	},
+ };
+ 
+ void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value)
+ {
+ 	int bit = 0;
+ 	u16 bitpos = 1 << bit;
+ 
+ 	for (; bit < ngpio; bit++, bitpos = bitpos << 1) {
+ 		if (!(mask & bitpos))
+ 			continue;
+ 		gpio_set_value(base + bit, (value & bitpos) != 0);
+ 	}
+ }
+ EXPORT_SYMBOL(ams_delta_latch_write);
+ 
  static struct resource ams_delta_nand_resources[] = {
  	[0] = {
  		.start	= OMAP1_MPUIO_BASE,
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From olof at lixom.net  Thu Mar  8 00:53:38 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 7 Mar 2012 21:53:38 -0800
Subject: [PATCH v2 04/11] ARM: EXYNOS: add interrupt definitions for
 EXYNOS5250
In-Reply-To: <4F575EC8.2090205@samsung.com>
References: <1328981685-8602-1-git-send-email-kgene.kim@samsung.com>
 <1328981685-8602-5-git-send-email-kgene.kim@samsung.com>
 <CAOesGMhmcnt6LPb9O+3420VgG=PiCnOjzZA3JqsA=4OdHN-R-g@mail.gmail.com>
 <00a901ccf084$90460900$b0d21b00$%kim@samsung.com>
 <CAOesGMgedngJKRVCYwK=+xRnchXj4StGLTVqvv9BMqVhtM=5RA@mail.gmail.com>
 <4F575EC8.2090205@samsung.com>
Message-ID: <CAOesGMgbm0+3nSnw=MTM--5kzUNMEofNQRudRUNzF_LCLCKX5A@mail.gmail.com>

Hi,

On Wed, Mar 7, 2012 at 5:12 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:

> Thanks for your kindly reminder but I couldn't finish it yet because it is
> required to touch most of samsung stuff, and it's a big change. Frankly, I
> need more time...
>
> So how about sending current exynos5 stuff for now and then sorting out
> single kernel for exynos4 and exynos5 next time? Actually, this exynos5 arch
> part is _really_ needed for developing/contribution of drivers on exynos5.

I suggest that you work on the code until it's in shape to go in. If
we pick it up half-finished it just causes extra churn.

We have been pushing back on v6/v7 additions that are not multi-board
and multi-soc within the same machine type. Not being able to build a
combined binary with exynos 4 and 5 support in one would be a step
backwards on that effort.

I'm not sure I understand the argument about drivers -- they should
mostly be possible to submit and get included without the core SoC
patches such that when those land, you'll have a fully functional
system.


-Olof


From sfr at canb.auug.org.au  Thu Mar  8 00:55:39 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 8 Mar 2012 16:55:39 +1100
Subject: linux-next: manual merge of the arm-soc tree with the omap_dss2 tree
Message-ID: <20120308165539.8a3b718be677de97a8767cd5@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-omap1/board-nokia770.c between commit 58e0d6ab02eb ("OMAP:
N770: remove HWA742 platform data") from the omap_dss2 tree and commit
2e3ee9f45b3c ("ARM: OMAP1: Move most of plat/io.h into local iomap.h")
from the arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-omap1/board-nokia770.c
index 9b6332a,abdbdb0..0000000
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@@ -30,7 -29,7 +29,6 @@@
  #include <plat/usb.h>
  #include <plat/board.h>
  #include <plat/keypad.h>
- #include "common.h"
 -#include <plat/hwa742.h>
  #include <plat/lcd_mipid.h>
  #include <plat/mmc.h>
  #include <plat/clock.h>
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From sfr at canb.auug.org.au  Thu Mar  8 00:58:38 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 8 Mar 2012 16:58:38 +1100
Subject: linux-next: manual merge of the arm-soc tree with the omap_dss2 tree
Message-ID: <20120308165838.c22b95e78c0ae3dd0ab1fea3@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-omap1/board-osk.c between commit ddba6c7f7ec6 ("OMAP1: pass
LCD config with omapfb_set_lcd_config()") from the omap_dss2 tree and
commit 2e3ee9f45b3c ("ARM: OMAP1: Move most of plat/io.h into local
iomap.h") from the arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-omap1/board-osk.c
index ef87465,e2d7ae4..0000000
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@@ -34,8 -34,6 +34,7 @@@
  #include <linux/i2c.h>
  #include <linux/leds.h>
  #include <linux/smc91x.h>
 +#include <linux/omapfb.h>
- 
  #include <linux/mtd/mtd.h>
  #include <linux/mtd/partitions.h>
  #include <linux/mtd/physmap.h>
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From sfr at canb.auug.org.au  Thu Mar  8 01:00:48 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 8 Mar 2012 17:00:48 +1100
Subject: linux-next: manual merge of the arm-soc tree with the omap_dss2 tree
Message-ID: <20120308170048.f1a992bca2ca2d93fa9747bf@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-omap1/board-palmtt.c between commit ddba6c7f7ec6 ("OMAP1:
pass LCD config with omapfb_set_lcd_config()") from the omap_dss2 tree
and commit 2e3ee9f45b3c ("ARM: OMAP1: Move most of plat/io.h into local
iomap.h") from the arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-omap1/board-palmtt.c
index b63350b,acd1f36..0000000
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@@ -24,9 -24,9 +24,10 @@@
  #include <linux/mtd/partitions.h>
  #include <linux/mtd/physmap.h>
  #include <linux/leds.h>
 +#include <linux/omapfb.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/ads7846.h>
  
- #include <mach/hardware.h>
  #include <asm/mach-types.h>
  #include <asm/mach/arch.h>
  #include <asm/mach/map.h>
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From sfr at canb.auug.org.au  Thu Mar  8 01:03:03 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 8 Mar 2012 17:03:03 +1100
Subject: linux-next: manual merge of the arm-soc tree with the  tree
Message-ID: <20120308170303.c113c6c34b8a7ae95caeb592@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in arch/arm/mach-omap1/board-palmz71.c between commit  ("") from the  tree and commit  ("") from the arm-soc tree.
Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-omap1/board-palmz71.c between commit ddba6c7f7ec6 ("OMAP1:
pass LCD config with omapfb_set_lcd_config()") from the omap_dss2 tree
and commit 2e3ee9f45b3c ("ARM: OMAP1: Move most of plat/io.h into local
iomap.h") from the arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary.

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-omap1/board-palmz71.c
index 9924c70,c1cd0f2..0000000
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@@ -27,9 -27,9 +27,10 @@@
  #include <linux/mtd/mtd.h>
  #include <linux/mtd/partitions.h>
  #include <linux/mtd/physmap.h>
 +#include <linux/omapfb.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/ads7846.h>
  
- #include <mach/hardware.h>
  #include <asm/mach-types.h>
  #include <asm/mach/arch.h>
  #include <asm/mach/map.h>
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From sfr at canb.auug.org.au  Thu Mar  8 01:07:51 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 8 Mar 2012 17:07:51 +1100
Subject: linux-next: manual merge of the arm-soc tree with Linus' tree
Message-ID: <20120308170751.8197b85ec3ab0a95e99ce945@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-vexpress/Kconfig between commit 43a6955fa8c3 ("ARM: 7346/1:
errata: fix PL310 erratum #753970 workaround selection") from Linus' tree
and commit 8deed1786a64 ("ARM: vexpress: Add Device Tree support") from
the arm-soc tree.

The latter took the former into account, so I dropped the former for this
file.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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From linus.walleij at linaro.org  Thu Mar  8 01:16:11 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 8 Mar 2012 07:16:11 +0100
Subject: [PATCH] watchdog/coh901327: convert to use watchdog core
In-Reply-To: <20120307164240.GA1130@pengutronix.de>
References: <1331131929-22383-1-git-send-email-linus.walleij@stericsson.com>
 <20120307164240.GA1130@pengutronix.de>
Message-ID: <CACRpkdaE5HASdF27db7EfnSoaUF8mA5bWoKUhaAzSegdBKsKFQ@mail.gmail.com>

On Wed, Mar 7, 2012 at 5:42 PM, Wolfram Sang <w.sang at pengutronix.de> wrote:

>> ? ? ? case WDIOC_GETTIMELEFT:
>> ? ? ? ? ? ? ? clk_enable(clk);
>> ? ? ? ? ? ? ? /* Read repeatedly until the value is stable! */
>
> I was wondering if it pays to put this IOCTL to watchdog_dev and add another
> callback to watchdog_ops? I'd think so. Wim, Linus, what do you think?

OK with me, shall I hack a patch?

Yours,
Linus Walleij


From sfr at canb.auug.org.au  Thu Mar  8 01:17:16 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 8 Mar 2012 17:17:16 +1100
Subject: linux-next: manual merge of the arm-soc tree with the  tree
In-Reply-To: <20120308170303.c113c6c34b8a7ae95caeb592@canb.auug.org.au>
References: <20120308170303.c113c6c34b8a7ae95caeb592@canb.auug.org.au>
Message-ID: <20120308171716.67ef72a3b195ef25f1d781d6@canb.auug.org.au>

Hi guys,

Sorry for the cut and paste mess ... :-(

On Thu, 8 Mar 2012 17:03:03 +1100 Stephen Rothwell <sfr at canb.auug.org.au> wrote:
>
> Hi all,
> 
> Today's linux-next merge of the arm-soc tree got a conflict in arch/arm/mach-omap1/board-palmz71.c between commit  ("") from the  tree and commit  ("") from the arm-soc tree.
> Today's linux-next merge of the arm-soc tree got a conflict in
> arch/arm/mach-omap1/board-palmz71.c between commit ddba6c7f7ec6 ("OMAP1:
> pass LCD config with omapfb_set_lcd_config()") from the omap_dss2 tree
> and commit 2e3ee9f45b3c ("ARM: OMAP1: Move most of plat/io.h into local
> iomap.h") from the arm-soc tree.
> 
> I fixed it up (see below) and can carry the fix as necessary.
> 
> -- 
> Cheers,
> Stephen Rothwell                    sfr at canb.auug.org.au
> 
> diff --cc arch/arm/mach-omap1/board-palmz71.c
> index 9924c70,c1cd0f2..0000000
> --- a/arch/arm/mach-omap1/board-palmz71.c
> +++ b/arch/arm/mach-omap1/board-palmz71.c
> @@@ -27,9 -27,9 +27,10 @@@
>   #include <linux/mtd/mtd.h>
>   #include <linux/mtd/partitions.h>
>   #include <linux/mtd/physmap.h>
>  +#include <linux/omapfb.h>
> + #include <linux/spi/spi.h>
> + #include <linux/spi/ads7846.h>
>   
> - #include <mach/hardware.h>
>   #include <asm/mach-types.h>
>   #include <asm/mach/arch.h>
>   #include <asm/mach/map.h>


-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From plagnioj at jcrosoft.com  Thu Mar  8 01:13:24 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 8 Mar 2012 07:13:24 +0100
Subject: [PATCH 5/6] ARM: at91: add ram controller DT support
In-Reply-To: <4F57BDCE.1050708@gmail.com>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <1330718048-9314-5-git-send-email-plagnioj@jcrosoft.com>
 <4F57BDCE.1050708@gmail.com>
Message-ID: <20120308061324.GE27213@game.jcrosoft.org>

> > diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> > index a297a77..88e43d5 100644
> > --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> > +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> > @@ -55,11 +55,6 @@
> >  #define AT91SAM9X5_BASE_USART2	0xf8024000
> >  
> >  /*
> > - * System Peripherals
> > - */
> > -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
> > -
> > -/*
> >   * Base addresses for early serial code (uncompress.h)
> >   */
> >  #define AT91_DBGU	AT91_BASE_DBGU0
> > diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> > index 3e48b59..f86450d 100644
> > --- a/arch/arm/mach-at91/setup.c
> > +++ b/arch/arm/mach-at91/setup.c
> > @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
> >  	of_node_put(np);
> >  }
> >  
> > +static struct of_device_id ramc_ids[] = {
> > +	{ .compatible = "atmel,at91sam9260-sdramc" },
> > +	{ .compatible = "atmel,at91sam9g45-ddramc" },
> > +	{ /*sentinel*/ }
> > +};
> > +
> > +static void at91_dt_ramc(void)
> > +{
> > +	struct device_node *np;
> > +
> > +	np = of_find_matching_node(NULL, ramc_ids);
> > +	if (!np)
> > +		panic("unable to find compatible ram conroller node in dtb\n");
> 
> You really can't boot if this fails? A WARN is better if it allows you
> to boot until at least your console is actually up.
if the restart is called you will have a oops so no it's a basic mandatory
device on at91

Best Regards,
J.


From andrew at lunn.ch  Thu Mar  8 01:27:39 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Thu, 8 Mar 2012 07:27:39 +0100
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
 <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
Message-ID: <20120308062739.GE18513@lunn.ch>

> Assuming that some day OMAP code can be refactored to allow for lazy
> (or at least initcall-based) registration of clocks then perhaps your
> suggestion can take root.  Which leads me to this question: are there
> any other platforms out there that require the level of expose to
> struct clk present in this patchset?  OMAP does, for now, but if that
> changes then I need to know if others require this as well.

Hi Mike

For kirkwood, i use static clk's for all but my root clock. I cannot
statically know the rate of the root clock, so i have to determine it
at boot time using heuristics, PCI ID, etc.

I used statics thinking it would be less code. No idea if it actually
is, and there is nothing stopping me moving to creating the clocks
after creating the root clock.

One comment i have about the current static clks. I completely missing
you need to call __clk_init() on them and so ended up with lots of
division by zero errors, since they did not have a parent, and so the
code seemed not be to able to determine the rate.

So 

1) Please add __clk_init() to the documentation in the section about
   static clocks.

2) Should maybe the name change? It seems strange having to call a
   __X() function. If this is a function which is supposed to be used,
   drop the __. Maybe clk_static_register()?

3) Maybe, if the parent is missing, clk_get_rate() should return an
   error?

Andrew


From dh09.lee at samsung.com  Thu Mar  8 01:52:44 2012
From: dh09.lee at samsung.com (Donghwa Lee)
Date: Thu, 08 Mar 2012 15:52:44 +0900
Subject: [RFC PATCH] video:backlight: add dimming sysfs node
Message-ID: <4F58573C.3020407@samsung.com>

In backlight class, update_status() callback function is mostly used to change
backlight brightness. When platform enter the dimming state, it is usually used.
But, I think dimming state can be defined variety of method including brightness.
So, it is need to differentiated node from brightness node.

In set_dimming() callback function, developers can define variety dimming functions.

Signed-off-by: Donghwa Lee <dh09.lee at samsung.com>
Signed-off-by: Inki Dae <inki.dae at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/video/backlight/backlight.c |   37 +++++++++++++++++++++++++++++++++++
 include/linux/backlight.h           |    9 ++++++++
 2 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c
index bf5b1ec..44a77e4 100644
--- a/drivers/video/backlight/backlight.c
+++ b/drivers/video/backlight/backlight.c
@@ -101,6 +101,43 @@ static void backlight_generate_event(struct backlight_device *bd,
 	sysfs_notify(&bd->dev.kobj, NULL, "actual_brightness");
 }
 
+static ssize_t backlight_store_dimming(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	int rc;
+	struct backlight_device *bd = to_backlight_device(dev);
+	unsigned long dimming;
+
+	rc = strict_strtoul(buf, 0, &dimming);
+	if (rc)
+		return rc;
+
+	if (dimming < 0)
+		rc = -EINVAL;
+	else {
+		pr_debug("set dimming mode\n");
+
+		if (dimming)
+			bd->props.dimming = true;
+		else
+			bd->props.dimming = false;
+
+		backlight_set_dimming(bd);
+
+		rc = count;
+	}
+
+	return rc;
+}
+
+static ssize_t backlight_show_dimming(struct device *dev,
+		struct device_attribute *attr,char *buf)
+{
+	struct backlight_device *bd = to_backlight_device(dev);
+
+	return sprintf(buf, "%d\n", bd->props.dimming);
+}
+
 static ssize_t backlight_show_power(struct device *dev,
 		struct device_attribute *attr, char *buf)
 {
diff --git a/include/linux/backlight.h b/include/linux/backlight.h
index 5ffc6dd..823717e 100644
--- a/include/linux/backlight.h
+++ b/include/linux/backlight.h
@@ -55,10 +55,13 @@ struct backlight_ops {
 	/* Check if given framebuffer device is the one bound to this backlight;
 	   return 0 if not, !=0 if it is. If NULL, backlight always matches the fb. */
 	int (*check_fb)(struct backlight_device *, struct fb_info *);
+	/* Notify the backlight driver to enter the dimming state */
+	int (*set_dimming)(struct backlight_device *);
 };
 
 /* This structure defines all the properties of a backlight */
 struct backlight_properties {
+	bool dimming;
 	/* Current User requested brightness (0 - max_brightness) */
 	int brightness;
 	/* Maximal value for brightness (read-only) */
@@ -111,6 +114,12 @@ static inline void backlight_update_status(struct backlight_device *bd)
 	mutex_unlock(&bd->update_lock);
 }
 
+static inline void backlight_set_dimming(struct backlight_device *bd)
+{
+	if (bd->ops && bd->ops->set_dimming)
+		bd->ops->set_dimming(bd);
+}
+
 extern struct backlight_device *backlight_device_register(const char *name,
 	struct device *dev, void *devdata, const struct backlight_ops *ops,
 	const struct backlight_properties *props);
-- 
1.7.4.1


From santosh.shilimkar at ti.com  Thu Mar  8 02:19:15 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Thu, 8 Mar 2012 08:19:15 +0100
Subject: [PATCH v3 12/13] gpio/omap: fix incorrect context restore logic
 in omap_gpio_runtime_resume
In-Reply-To: <CAC83ZvLFoSppTiPw-_a=z_Mnpmk6nHeaadTShdJP8RpDWh9TLg@mail.gmail.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-13-git-send-email-tarun.kanti@ti.com>
 <4F574F95.7090801@ti.com>
 <CAC83ZvLFoSppTiPw-_a=z_Mnpmk6nHeaadTShdJP8RpDWh9TLg@mail.gmail.com>
Message-ID: <CAMQu2gzgM=Hc4fis5AsgL50e2KLttTR79iroOtExGecU7F50yw@mail.gmail.com>

On Thu, Mar 8, 2012 at 4:58 AM, DebBarma, Tarun Kanti
<tarun.kanti at ti.com> wrote:
> On Wed, Mar 7, 2012 at 5:37 PM, Santosh Shilimkar
> <santosh.shilimkar at ti.com> wrote:
>> On Wednesday 07 March 2012 12:16 PM, Tarun Kanti DebBarma wrote:
>>> In omap_gpio_runtime_resume() the context restore should be independent
>>> of bank->enabled_non_wakeup_gpios. This was preventing context restore
>>> of GPIO lines which are not wakeup enabled.
>>>
>>> Reported-by: Govindraj Raja <govindraj.raja at ti.com>
>>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>>> ---
>>> ?drivers/gpio/gpio-omap.c | ? ?2 +-
>>> ?1 files changed, 1 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
>>> index 2e8e476..ccfbae0 100644
>>> --- a/drivers/gpio/gpio-omap.c
>>> +++ b/drivers/gpio/gpio-omap.c
>>> @@ -1227,7 +1227,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
>>> ? ? ? __raw_writel(bank->context.risingdetect,
>>> ? ? ? ? ? ? ? ? ? ?bank->base + bank->regs->risingdetect);
>>>
>>> - ? ? if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
>>> + ? ? if (!bank->workaround_enabled) {
>> This doesn't seem to be right.
>> Don't you want to avoid GPIO restore for banks which are in
>> always on domain. Infact the purpose of "enabled_non_wakeup_gpios"
>> is exactly that ? Isn't it.
>>
>> What am I missing ?
> The bank->enabled_non_wakeup_gpios is set whenever a gpio line is programmed
> as edge trigger as shown below.
> (This is not meant to distinguish between gpios in WKUP domain vs
> those in PER domain).
> The context restore should happen irrespective of whether the trigger
> type is edge or level.
> In fact context restore was not happening for a gpio line because of
> this condition while
> testing suspend/resume.
>
> [...]
> ? ? ? ? ? ? ? ?if (trigger & IRQ_TYPE_EDGE_BOTH)
> ? ? ? ? ? ? ? ? ? ? ? ?bank->enabled_non_wakeup_gpios |= gpio_bit;
> ? ? ? ? ? ? ? ?else
> ? ? ? ? ? ? ? ? ? ? ? ?bank->enabled_non_wakeup_gpios &= ~gpio_bit;
> [...]

Make sense now. Thanks for clarification Tarun.
You can add mine..
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

Regards
Santosh


From w.sang at pengutronix.de  Thu Mar  8 02:45:10 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 8 Mar 2012 08:45:10 +0100
Subject: [PATCH 1/3] drivers: base: add support for stmp-style devices
In-Reply-To: <CAOMZO5C9EDi_Hy-8=iphr+154gyPgBLnjSVV0seLgi+HoK4zRw@mail.gmail.com>
References: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
 <1331159314-12022-2-git-send-email-w.sang@pengutronix.de>
 <CAOMZO5C9EDi_Hy-8=iphr+154gyPgBLnjSVV0seLgi+HoK4zRw@mail.gmail.com>
Message-ID: <20120308074510.GB18510@pengutronix.de>

On Wed, Mar 07, 2012 at 07:40:22PM -0300, Fabio Estevam wrote:
> On Wed, Mar 7, 2012 at 7:28 PM, Wolfram Sang <w.sang at pengutronix.de> wrote:
> ...
> > +static int stmp_clear_poll_bit(void __iomem *addr, u32 mask)
> > +{
> > + ? ? ? int timeout = 0x400;
> 
> Could you please add a proper timeout mechanism here?
> 
> Something like: http://patchwork.ozlabs.org/patch/137365/

From the patch description:

===

To avoid regressions and ease reviewing, the actual code is simply copied from
mach-mxs. It definately wants updates, but those need a seperate patch series.

===

Or is that considered a wrong path?

Thanks,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From jp.francois at cynove.com  Thu Mar  8 03:26:19 2012
From: jp.francois at cynove.com (jean-philippe francois)
Date: Thu, 8 Mar 2012 09:26:19 +0100
Subject: soft lockup on omap3 (dm3730)
In-Reply-To: <20120307163750.GC18787@n2100.arm.linux.org.uk>
References: <CAGGh5h3OQTniXbm8iUYGM+2oi+zzd1F6BxDKzN5epA89+i_7nQ@mail.gmail.com>
 <20120307163750.GC18787@n2100.arm.linux.org.uk>
Message-ID: <CAGGh5h3AtiuFuU0OY1FpPre6hyGKTSTEc=S6hkf2hAr=6LAehg@mail.gmail.com>

Le 7 mars 2012 17:37, Russell King - ARM Linux
<linux at arm.linux.org.uk> a ?crit :
> On Wed, Mar 07, 2012 at 05:16:35PM +0100, jean-philippe francois wrote:
>> Is the backtrace pointing to this offset because soft_lockup can only
>> detect lockups at the output of critical sections ?
>
> Correct - soft lockups on ARM can only be detected when hardware
> interrupts are enabled. ?Any region which masks hard interrupts
> effectively prevents the soft lockup detector firing should
> execution get stuck inside such a region.

But then, how is the soft lockup detector able to break this hard lockup ?
 Without soft / hard lockup detection configured, the loop
runs forever. Anyway, Thanks for the suggestion, I will try to printk  my way
out of this problem.

>
>> I don't know how to progress on this problem, any hint is welcome.
>>
>> int omap3isp_video_queue_streamon(struct isp_video_queue *queue)
>> {
>> ? ? ? ?struct isp_video_buffer *buf;
>> ? ? ? ?unsigned long flags;
>>
>> ? ? ? ?mutex_lock(&queue->lock);
>>
>> ? ? ? ?if (queue->streaming)
>> ? ? ? ? ? ? ? ?goto done;
>>
>> ? ? ? ?queue->streaming = 1;
>>
>> ? ? ? ?spin_lock_irqsave(&queue->irqlock, flags);
>> ? ? ? ?list_for_each_entry(buf, &queue->queue, stream) {
>> ? ? ? ? ? ? ? ?printk(KERN_INFO "inside list_for_each\n");
>> ? ? ? ? ? ? ? ?queue->ops->buffer_queue(buf);
>> ? ? ? ?}
>> ? ? ? ?spin_unlock_irqrestore(&queue->irqlock, flags); ?<---- soft lockup
>> says this is the culprit.
>
> My guess is something inside buffer_queue() is responsible. ?If things
> get stuck for quite a period of time, the only thing I can suggest is
> using printk() based debugging to try and find where things get stuck.
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From plagnioj at jcrosoft.com  Thu Mar  8 03:50:33 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu,  8 Mar 2012 09:50:33 +0100
Subject: [PATCH 3/5 v3] ARM: at91: usb_a9g20 add DT i2c support
In-Reply-To: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1331196635-27203-3-git-send-email-plagnioj@jcrosoft.com>

Use i2c-gpio and enable rv3029 RTC.

Enable the rtc in the sam9g20 defconfig.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: devicetree-discuss at lists.ozlabs.org
---
 arch/arm/boot/dts/usb_a9g20.dts        |    9 +++++++++
 arch/arm/configs/at91sam9g20_defconfig |    3 +++
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 6ab7e7a..07012ca 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -97,4 +97,13 @@
 			gpio-key,wakeup;
 		};
 	};
+
+	i2c-gpio at 0 {
+		status = "okay";
+
+		rv3029c2 at 56 {
+			compatible = "rv3029c2";
+			reg = <0x56>;
+		};
+	};
 };
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index 9123568..994d331 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -74,6 +74,8 @@ CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_SPI_SPIDEV=y
@@ -105,6 +107,7 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_EXT2_FS=y
 CONFIG_MSDOS_FS=y
-- 
1.7.7



From plagnioj at jcrosoft.com  Thu Mar  8 03:50:32 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu,  8 Mar 2012 09:50:32 +0100
Subject: [PATCH 2/5 v3] ARM: at91: sam9g20 add i2c DT support
In-Reply-To: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1331196635-27203-2-git-send-email-plagnioj@jcrosoft.com>

For now on use i2c-gpio driver on the same pin as the hardware IP.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: devicetree-discuss at lists.ozlabs.org
---
v3:

	update i2c binding (Rob comments)

Best Regards,
J.
 arch/arm/boot/dts/at91sam9g20.dtsi |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 4b0dc99..072b2da 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -189,4 +189,17 @@
 			status = "disabled";
 		};
 	};
+
+	i2c-gpio at 0 {
+		compatible = "i2c-gpio";
+		gpios = <&pioA 23 0 /* sda */
+			 &pioA 24 0 /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
-- 
1.7.7



From plagnioj at jcrosoft.com  Thu Mar  8 03:50:34 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu,  8 Mar 2012 09:50:34 +0100
Subject: [PATCH 4/5 v3] ARM: at91: sam9g45 add i2c DT support
In-Reply-To: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1331196635-27203-4-git-send-email-plagnioj@jcrosoft.com>

For now on use i2c-gpio driver on the same pin as the hardware IP.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: devicetree-discuss at lists.ozlabs.org
---
v3:

	update i2c binding (Rob comments)

Best Regards,
J.
 arch/arm/boot/dts/at91sam9g45.dtsi |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index d79021b..4a8a36d 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -197,4 +197,17 @@
 			status = "disabled";
 		};
 	};
+
+	i2c-gpio at 0 {
+		compatible = "i2c-gpio";
+		gpios = <&pioA 20 0 /* sda */
+			 &pioA 21 0 /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <5>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
-- 
1.7.7



From plagnioj at jcrosoft.com  Thu Mar  8 03:50:35 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu,  8 Mar 2012 09:50:35 +0100
Subject: [PATCH 5/5 v3] ARM: at91: sam9x5 add i2c DT support
In-Reply-To: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1331196635-27203-5-git-send-email-plagnioj@jcrosoft.com>

For now on use i2c-gpio driver on the same pin as the hardware IP.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: devicetree-discuss at lists.ozlabs.org
---
v3:

	update i2c binding (Rob comments)

Best Regards,
J.
 arch/arm/boot/dts/at91sam9x5.dtsi |   39 +++++++++++++++++++++++++++++++++++++
 1 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index c294657..fdd1ac6 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -188,4 +188,43 @@
 			status = "disabled";
 		};
 	};
+
+	i2c-gpio at 0 {
+		compatible = "i2c-gpio";
+		gpios = <&pioA 30 0 /* sda */
+			 &pioA 31 0 /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c-gpio at 1 {
+		compatible = "i2c-gpio";
+		gpios = <&pioC 0 0 /* sda */
+			 &pioC 1 0 /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c-gpio at 2 {
+		compatible = "i2c-gpio";
+		gpios = <&pioB 4 0 /* sda */
+			 &pioB 5 0 /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
-- 
1.7.7



From plagnioj at jcrosoft.com  Thu Mar  8 03:50:31 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu,  8 Mar 2012 09:50:31 +0100
Subject: [PATCH 1/5 v3] i2c/gpio: add DT support
Message-ID: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-i2c at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
---
v3:

	update i2c binding (Rob comments)

	Jean can I have a ack to apply it?

Best Regards,
J.
 .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 +++++++
 drivers/i2c/busses/i2c-gpio.c                      |   94 +++++++++++++++----
 2 files changed, 106 insertions(+), 20 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
new file mode 100644
index 0000000..4f8ec94
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
@@ -0,0 +1,32 @@
+Device-Tree bindings for i2c gpio driver
+
+Required properties:
+	- compatible = "i2c-gpio";
+	- gpios: sda and scl gpio
+
+
+Optional properties:
+	- i2c-gpio,sda-open-drain: sda as open drain
+	- i2c-gpio,scl-open-drain: scl as open drain
+	- i2c-gpio,scl-output-only: scl as output only
+	- i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform)
+	- i2c-gpio,timeout-ms: timeout to get data
+
+Example nodes:
+
+i2c at 0 {
+	compatible = "i2c-gpio";
+	gpios = <&pioA 23 0 /* sda */
+		 &pioA 24 0 /* scl */
+		>;
+	i2c-gpio,sda-open-drain;
+	i2c-gpio,scl-open-drain;
+	i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	rv3029c2 at 56 {
+		compatible = "rv3029c2";
+		reg = <0x56>;
+	};
+};
diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
index a651779..98ae85b 100644
--- a/drivers/i2c/busses/i2c-gpio.c
+++ b/drivers/i2c/busses/i2c-gpio.c
@@ -14,8 +14,15 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/of_i2c.h>
 
-#include <asm/gpio.h>
+struct i2c_gpio_private_data {
+	struct i2c_adapter adap;
+	struct i2c_algo_bit_data bit_data;
+	struct i2c_gpio_platform_data pdata;
+};
 
 /* Toggle SDA by changing the direction of the pin */
 static void i2c_gpio_setsda_dir(void *data, int state)
@@ -78,24 +85,62 @@ static int i2c_gpio_getscl(void *data)
 	return gpio_get_value(pdata->scl_pin);
 }
 
+static int __devinit of_i2c_gpio_probe(struct device_node *np,
+			     struct i2c_gpio_platform_data *pdata)
+{
+	u32 reg;
+
+	if (of_gpio_count(np) < 2)
+		return -ENODEV;
+
+	pdata->sda_pin = of_get_gpio(np, 0);
+	pdata->scl_pin = of_get_gpio(np, 1);
+
+	if (pdata->sda_pin < 0 || pdata->scl_pin < 0) {
+		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
+		       np->full_name, pdata->sda_pin, pdata->scl_pin);
+		return -ENODEV;
+	}
+
+	of_property_read_u32(np, "i2c-gpio,delay-us", &pdata->udelay);
+
+	if (of_property_read_u32(np, "i2c-gpio,timeout-ms", &reg))
+		pdata->timeout = msecs_to_jiffies(reg);
+
+	pdata->sda_is_open_drain =
+		!!of_property_read_bool(np, "i2c-gpio,sda-open-drain");
+	pdata->scl_is_open_drain =
+		!!of_property_read_bool(np, "i2c-gpio,scl-open-drain");
+	pdata->scl_is_output_only =
+		!!of_property_read_bool(np, "i2c-gpio,scl-output-only");
+
+	return 0;
+}
+
 static int __devinit i2c_gpio_probe(struct platform_device *pdev)
 {
+	struct i2c_gpio_private_data *priv;
 	struct i2c_gpio_platform_data *pdata;
 	struct i2c_algo_bit_data *bit_data;
 	struct i2c_adapter *adap;
 	int ret;
 
-	pdata = pdev->dev.platform_data;
-	if (!pdata)
-		return -ENXIO;
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	adap = &priv->adap;
+	bit_data = &priv->bit_data;
+	pdata = &priv->pdata;
 
-	ret = -ENOMEM;
-	adap = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
-	if (!adap)
-		goto err_alloc_adap;
-	bit_data = kzalloc(sizeof(struct i2c_algo_bit_data), GFP_KERNEL);
-	if (!bit_data)
-		goto err_alloc_bit_data;
+	if (pdev->dev.of_node) {
+		ret = of_i2c_gpio_probe(pdev->dev.of_node, pdata);
+		if (ret)
+			return ret;
+	} else {
+		if (!pdev->dev.platform_data)
+			return -ENXIO;
+		memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
+	}
 
 	ret = gpio_request(pdata->sda_pin, "sda");
 	if (ret)
@@ -143,6 +188,7 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
 	adap->algo_data = bit_data;
 	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 	adap->dev.parent = &pdev->dev;
+	adap->dev.of_node = pdev->dev.of_node;
 
 	/*
 	 * If "dev->id" is negative we consider it as zero.
@@ -154,7 +200,9 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_add_bus;
 
-	platform_set_drvdata(pdev, adap);
+	of_i2c_register_devices(adap);
+
+	platform_set_drvdata(pdev, priv);
 
 	dev_info(&pdev->dev, "using pins %u (SDA) and %u (SCL%s)\n",
 		 pdata->sda_pin, pdata->scl_pin,
@@ -168,34 +216,40 @@ err_add_bus:
 err_request_scl:
 	gpio_free(pdata->sda_pin);
 err_request_sda:
-	kfree(bit_data);
-err_alloc_bit_data:
-	kfree(adap);
-err_alloc_adap:
 	return ret;
 }
 
 static int __devexit i2c_gpio_remove(struct platform_device *pdev)
 {
+	struct i2c_gpio_private_data *priv;
 	struct i2c_gpio_platform_data *pdata;
 	struct i2c_adapter *adap;
 
-	adap = platform_get_drvdata(pdev);
-	pdata = pdev->dev.platform_data;
+	priv = platform_get_drvdata(pdev);
+	adap = &priv->adap;
+	pdata = &priv->pdata;
 
 	i2c_del_adapter(adap);
 	gpio_free(pdata->scl_pin);
 	gpio_free(pdata->sda_pin);
-	kfree(adap->algo_data);
-	kfree(adap);
 
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id i2c_gpio_dt_ids[] = {
+	{ .compatible = "i2c-gpio", },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, i2c_gpio_dt_ids);
+#endif
+
 static struct platform_driver i2c_gpio_driver = {
 	.driver		= {
 		.name	= "i2c-gpio",
 		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(i2c_gpio_dt_ids),
 	},
 	.probe		= i2c_gpio_probe,
 	.remove		= __devexit_p(i2c_gpio_remove),
-- 
1.7.7



From bryan.wu at canonical.com  Thu Mar  8 04:11:02 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Thu,  8 Mar 2012 17:11:02 +0800
Subject: [PATCH 2/3] led-triggers: use atomic kzalloc during led trigger
 registering
In-Reply-To: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1331197863-25564-2-git-send-email-bryan.wu@canonical.com>

kzalloc might cause sleep and will generate some warning detected by lockdep,
when call led_trigger_register_simple on each cpu cores in SMP. This patch fix
this.

[    1.999938] ------------[ cut here ]------------
[    2.004791] WARNING: at kernel/lockdep.c:2664 lockdep_trace_alloc+0xd8/0xf0()
[    2.012298] Modules linked in:
[    2.015563] [<c001b0cc>] (unwind_backtrace+0x0/0xf0) from [<c0052408>] (warn_slowpath_common+0x4c/0x64)
[    2.025451] [<c0052408>] (warn_slowpath_common+0x4c/0x64) from [<c005243c>] (warn_slowpath_null+0x1c/0x24)
[    2.035583] [<c005243c>] (warn_slowpath_null+0x1c/0x24) from [<c008be28>] (lockdep_trace_alloc+0xd8/0xf0)
[    2.045684] [<c008be28>] (lockdep_trace_alloc+0xd8/0xf0) from [<c00feeb4>] (kmem_cache_alloc_trace+0x2c/0x148)
[    2.056213] [<c00feeb4>] (kmem_cache_alloc_trace+0x2c/0x148) from [<c03770a0>] (led_trigger_register_simple+0x20/0x74)
[    2.067474] [<c03770a0>] (led_trigger_register_simple+0x20/0x74) from [<c0627a30>] (ledtrig_cpu_register+0x4c/0x8c)
[    2.078460] [<c0627a30>] (ledtrig_cpu_register+0x4c/0x8c) from [<c0094ca4>] (generic_smp_call_function_single_interrupt+0xcc/0x138)
[    2.090911] [<c0094ca4>] (generic_smp_call_function_single_interrupt+0xcc/0x138) from [<c0008408>] (do_IPI+0xb0/0x128)
[    2.102172] [<c0008408>] (do_IPI+0xb0/0x128) from [<c045921c>] (__irq_svc+0x3c/0x100)
[    2.110412] Exception stack(0xc07adf70 to 0xc07adfb8)
[    2.115722] df60:                                     c07c80f8 0000fb45 00000000 c07c80f8
[    2.124328] df80: c07ac000 c0837be4 c0464b64 c07c9d8c 00000000 411fc092 00000000 00000000
[    2.132934] dfa0: c0649760 c07adfb8 c07c5c58 c0014d50 20000013 ffffffff
[    2.139892] [<c045921c>] (__irq_svc+0x3c/0x100) from [<c0014d50>] (default_idle+0x30/0x38)
[    2.148590] [<c0014d50>] (default_idle+0x30/0x38) from [<c0014f74>] (cpu_idle+0xb4/0xf4)
[    2.157135] [<c0014f74>] (cpu_idle+0xb4/0xf4) from [<c0602778>] (start_kernel+0x2a8/0x2fc)
[    2.165832] [<c0602778>] (start_kernel+0x2a8/0x2fc) from [<80008040>] (0x80008040)
[    2.173797] ---[ end trace 97549d21d8dad3f5 ]---

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 drivers/leds/led-triggers.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/leds/led-triggers.c b/drivers/leds/led-triggers.c
index 46b4c76..74d0ba7 100644
--- a/drivers/leds/led-triggers.c
+++ b/drivers/leds/led-triggers.c
@@ -255,7 +255,7 @@ void led_trigger_register_simple(const char *name, struct led_trigger **tp)
 	struct led_trigger *trigger;
 	int err;
 
-	trigger = kzalloc(sizeof(struct led_trigger), GFP_KERNEL);
+	trigger = kzalloc(sizeof(struct led_trigger), GFP_ATOMIC);
 
 	if (trigger) {
 		trigger->name = name;
-- 
1.7.9



From bryan.wu at canonical.com  Thu Mar  8 04:11:01 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Thu,  8 Mar 2012 17:11:01 +0800
Subject: [PATCH 1/3] led-class: change back LEDS_CLASS to tristate instead of
 bool
Message-ID: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>

After moving some core functions to led-core.c, led-class.c can be built as
module again.

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 drivers/leds/Kconfig     |    2 +-
 drivers/leds/led-class.c |   70 ----------------------------------------------
 drivers/leds/led-core.c  |   70 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+), 71 deletions(-)

diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 9ca28fc..3f17f0d 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -17,7 +17,7 @@ menuconfig NEW_LEDS
 if NEW_LEDS
 
 config LEDS_CLASS
-	bool "LED Class Support"
+	tristate "LED Class Support"
 	help
 	  This option enables the led sysfs class in /sys/class/leds.  You'll
 	  need this to do anything useful with LEDs.  If unsure, say N.
diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
index 0c8739c..5bff843 100644
--- a/drivers/leds/led-class.c
+++ b/drivers/leds/led-class.c
@@ -110,50 +110,6 @@ static void led_timer_function(unsigned long data)
 	mod_timer(&led_cdev->blink_timer, jiffies + msecs_to_jiffies(delay));
 }
 
-static void led_stop_software_blink(struct led_classdev *led_cdev)
-{
-	/* deactivate previous settings */
-	del_timer_sync(&led_cdev->blink_timer);
-	led_cdev->blink_delay_on = 0;
-	led_cdev->blink_delay_off = 0;
-}
-
-static void led_set_software_blink(struct led_classdev *led_cdev,
-				   unsigned long delay_on,
-				   unsigned long delay_off)
-{
-	int current_brightness;
-
-	current_brightness = led_get_brightness(led_cdev);
-	if (current_brightness)
-		led_cdev->blink_brightness = current_brightness;
-	if (!led_cdev->blink_brightness)
-		led_cdev->blink_brightness = led_cdev->max_brightness;
-
-	if (led_get_trigger_data(led_cdev) &&
-	    delay_on == led_cdev->blink_delay_on &&
-	    delay_off == led_cdev->blink_delay_off)
-		return;
-
-	led_stop_software_blink(led_cdev);
-
-	led_cdev->blink_delay_on = delay_on;
-	led_cdev->blink_delay_off = delay_off;
-
-	/* never on - don't blink */
-	if (!delay_on)
-		return;
-
-	/* never off - just set to brightness */
-	if (!delay_off) {
-		led_set_brightness(led_cdev, led_cdev->blink_brightness);
-		return;
-	}
-
-	mod_timer(&led_cdev->blink_timer, jiffies + 1);
-}
-
-
 /**
  * led_classdev_suspend - suspend an led_classdev.
  * @led_cdev: the led_classdev to suspend.
@@ -262,32 +218,6 @@ void led_classdev_unregister(struct led_classdev *led_cdev)
 }
 EXPORT_SYMBOL_GPL(led_classdev_unregister);
 
-void led_blink_set(struct led_classdev *led_cdev,
-		   unsigned long *delay_on,
-		   unsigned long *delay_off)
-{
-	del_timer_sync(&led_cdev->blink_timer);
-
-	if (led_cdev->blink_set &&
-	    !led_cdev->blink_set(led_cdev, delay_on, delay_off))
-		return;
-
-	/* blink with 1 Hz as default if nothing specified */
-	if (!*delay_on && !*delay_off)
-		*delay_on = *delay_off = 500;
-
-	led_set_software_blink(led_cdev, *delay_on, *delay_off);
-}
-EXPORT_SYMBOL(led_blink_set);
-
-void led_brightness_set(struct led_classdev *led_cdev,
-			enum led_brightness brightness)
-{
-	led_stop_software_blink(led_cdev);
-	led_cdev->brightness_set(led_cdev, brightness);
-}
-EXPORT_SYMBOL(led_brightness_set);
-
 static int __init leds_init(void)
 {
 	leds_class = class_create(THIS_MODULE, "leds");
diff --git a/drivers/leds/led-core.c b/drivers/leds/led-core.c
index 016d19f..d686004 100644
--- a/drivers/leds/led-core.c
+++ b/drivers/leds/led-core.c
@@ -23,3 +23,73 @@ EXPORT_SYMBOL_GPL(leds_list_lock);
 
 LIST_HEAD(leds_list);
 EXPORT_SYMBOL_GPL(leds_list);
+
+static void led_stop_software_blink(struct led_classdev *led_cdev)
+{
+	/* deactivate previous settings */
+	del_timer_sync(&led_cdev->blink_timer);
+	led_cdev->blink_delay_on = 0;
+	led_cdev->blink_delay_off = 0;
+}
+
+static void led_set_software_blink(struct led_classdev *led_cdev,
+				   unsigned long delay_on,
+				   unsigned long delay_off)
+{
+	int current_brightness;
+
+	current_brightness = led_get_brightness(led_cdev);
+	if (current_brightness)
+		led_cdev->blink_brightness = current_brightness;
+	if (!led_cdev->blink_brightness)
+		led_cdev->blink_brightness = led_cdev->max_brightness;
+
+	if (led_get_trigger_data(led_cdev) &&
+	    delay_on == led_cdev->blink_delay_on &&
+	    delay_off == led_cdev->blink_delay_off)
+		return;
+
+	led_stop_software_blink(led_cdev);
+
+	led_cdev->blink_delay_on = delay_on;
+	led_cdev->blink_delay_off = delay_off;
+
+	/* never on - don't blink */
+	if (!delay_on)
+		return;
+
+	/* never off - just set to brightness */
+	if (!delay_off) {
+		led_set_brightness(led_cdev, led_cdev->blink_brightness);
+		return;
+	}
+
+	mod_timer(&led_cdev->blink_timer, jiffies + 1);
+}
+
+
+void led_blink_set(struct led_classdev *led_cdev,
+		   unsigned long *delay_on,
+		   unsigned long *delay_off)
+{
+	del_timer_sync(&led_cdev->blink_timer);
+
+	if (led_cdev->blink_set &&
+	    !led_cdev->blink_set(led_cdev, delay_on, delay_off))
+		return;
+
+	/* blink with 1 Hz as default if nothing specified */
+	if (!*delay_on && !*delay_off)
+		*delay_on = *delay_off = 500;
+
+	led_set_software_blink(led_cdev, *delay_on, *delay_off);
+}
+EXPORT_SYMBOL(led_blink_set);
+
+void led_brightness_set(struct led_classdev *led_cdev,
+			enum led_brightness brightness)
+{
+	led_stop_software_blink(led_cdev);
+	led_cdev->brightness_set(led_cdev, brightness);
+}
+EXPORT_SYMBOL(led_brightness_set);
-- 
1.7.9



From bryan.wu at canonical.com  Thu Mar  8 04:11:03 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Thu,  8 Mar 2012 17:11:03 +0800
Subject: [PATCH 3/3] led-triggers: create a trigger for CPU activity
In-Reply-To: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1331197863-25564-3-git-send-email-bryan.wu@canonical.com>

Attempting to consolidate the ARM LED code, this removes the
custom RealView LED trigger code to turn LEDs on and off in
response to CPU activity and replace it with a standard trigger.

(bryan.wu at canonical.com:
It moves arch/arm/kernel/leds.c syscore stubs into this trigger.
It also provides ledtrig_cpu trigger event stub in <linux/leds.h>.
Although it was inspired by ARM work, it can be used in other arch.)

Cc: Richard Purdie <rpurdie at rpsys.net>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Bryan Wu <bryan.wu at canonical.com>

Reviewed-by: Jamie Iles <jamie at jamieiles.com>
Tested-by: Jochen Friedrich <jochen at scram.de>
---
 drivers/leds/Kconfig       |   10 ++++
 drivers/leds/Makefile      |    1 +
 drivers/leds/ledtrig-cpu.c |  119 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/leds.h       |   15 ++++++
 4 files changed, 145 insertions(+), 0 deletions(-)
 create mode 100644 drivers/leds/ledtrig-cpu.c

diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 3f17f0d..f7f4761 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -457,6 +457,16 @@ config LEDS_TRIGGER_BACKLIGHT
 
 	  If unsure, say N.
 
+config LEDS_TRIGGER_CPU
+	tristate "LED CPU Trigger"
+	depends on LEDS_TRIGGERS
+	help
+	  This allows LEDs to be controlled by active CPUs. This shows
+	  the active CPUs across an array of LEDs so you can see what
+	  CPUs are active on the system at any given moment.
+
+	  If unsure, say N.
+
 config LEDS_TRIGGER_GPIO
 	tristate "LED GPIO Trigger"
 	depends on LEDS_TRIGGERS
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 1fc6875..6629916 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -56,4 +56,5 @@ obj-$(CONFIG_LEDS_TRIGGER_IDE_DISK)	+= ledtrig-ide-disk.o
 obj-$(CONFIG_LEDS_TRIGGER_HEARTBEAT)	+= ledtrig-heartbeat.o
 obj-$(CONFIG_LEDS_TRIGGER_BACKLIGHT)	+= ledtrig-backlight.o
 obj-$(CONFIG_LEDS_TRIGGER_GPIO)		+= ledtrig-gpio.o
+obj-$(CONFIG_LEDS_TRIGGER_CPU)		+= ledtrig-cpu.o
 obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON)	+= ledtrig-default-on.o
diff --git a/drivers/leds/ledtrig-cpu.c b/drivers/leds/ledtrig-cpu.c
new file mode 100644
index 0000000..49f7879
--- /dev/null
+++ b/drivers/leds/ledtrig-cpu.c
@@ -0,0 +1,119 @@
+/*
+ * ledtrig-cpu.c - LED trigger based on CPU activity
+ *
+ * Copyright 2011 Linus Walleij <linus.walleij at linaro.org>
+ * Copyright 2011 Bryan Wu <bryan.wu at canonical.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/percpu.h>
+#include <linux/syscore_ops.h>
+#include "leds.h"
+
+static DEFINE_PER_CPU(struct led_trigger *, cpu_trig);
+static DEFINE_PER_CPU(char [8], trig_name);
+
+void ledtrig_cpu(enum cpu_led_event ledevt)
+{
+	struct led_trigger *trig = __get_cpu_var(cpu_trig);
+
+	if (!trig)
+		return;
+
+	/* Locate the correct CPU LED */
+	switch (ledevt) {
+	case CPU_LED_IDLE_END:
+	case CPU_LED_START:
+		/* Will turn the LED on, max brightness */
+		led_trigger_event(trig, LED_FULL);
+		break;
+
+	case CPU_LED_IDLE_START:
+	case CPU_LED_STOP:
+	case CPU_LED_HALTED:
+		/* Will turn the LED off */
+		led_trigger_event(trig, LED_OFF);
+		break;
+
+	default:
+		/* Will leave the LED as it is */
+		break;
+	}
+}
+EXPORT_SYMBOL(ledtrig_cpu);
+
+static int ledtrig_cpu_syscore_suspend(void)
+{
+	ledtrig_cpu(CPU_LED_STOP);
+	return 0;
+}
+
+static void ledtrig_cpu_syscore_resume(void)
+{
+	ledtrig_cpu(CPU_LED_START);
+}
+
+static void ledtrig_cpu_syscore_shutdown(void)
+{
+	ledtrig_cpu(CPU_LED_HALTED);
+}
+
+static struct syscore_ops ledtrig_cpu_syscore_ops = {
+	.shutdown	= ledtrig_cpu_syscore_shutdown,
+	.suspend	= ledtrig_cpu_syscore_suspend,
+	.resume		= ledtrig_cpu_syscore_resume,
+};
+
+static void __init ledtrig_cpu_register(void *info)
+{
+	int cpuid = smp_processor_id();
+	struct led_trigger *trig;
+	char *name = __get_cpu_var(trig_name);
+
+	snprintf(name, 8, "cpu%d", cpuid);
+	led_trigger_register_simple(name, &trig);
+
+	pr_info("LED trigger %s indicate activity on CPU %d\n",
+		trig->name, cpuid);
+
+	__get_cpu_var(cpu_trig) = trig;
+}
+
+static void __exit ledtrig_cpu_unregister(void *info)
+{
+	struct led_trigger *trig = __get_cpu_var(cpu_trig);
+	char *name = __get_cpu_var(trig_name);
+
+	led_trigger_unregister_simple(trig);
+	__get_cpu_var(cpu_trig) = NULL;
+	memset(name, 0, 8);
+}
+
+static int __init ledtrig_cpu_init(void)
+{
+	on_each_cpu(ledtrig_cpu_register, NULL, 1);
+	register_syscore_ops(&ledtrig_cpu_syscore_ops);
+
+	return 0;
+}
+module_init(ledtrig_cpu_init);
+
+static void __exit ledtrig_cpu_exit(void)
+{
+	on_each_cpu(ledtrig_cpu_unregister, NULL, 1);
+	unregister_syscore_ops(&ledtrig_cpu_syscore_ops);
+}
+module_exit(ledtrig_cpu_exit);
+
+MODULE_AUTHOR("Linus Walleij <linus.walleij at linaro.org>");
+MODULE_AUTHOR("Bryan Wu <bryan.wu at canonical.com>");
+MODULE_DESCRIPTION("CPU LED trigger");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/leds.h b/include/linux/leds.h
index 5884def..2afecb7 100644
--- a/include/linux/leds.h
+++ b/include/linux/leds.h
@@ -210,4 +210,19 @@ struct gpio_led_platform_data {
 struct platform_device *gpio_led_register_device(
 		int id, const struct gpio_led_platform_data *pdata);
 
+#if defined(CONFIG_LEDS_TRIGGER_CPU) || defined(CONFIG_LEDS_TRIGGER_CPU_MODULE)
+enum cpu_led_event {
+	CPU_LED_IDLE_START,	/* CPU enters idle */
+	CPU_LED_IDLE_END,	/* CPU idle ends */
+	CPU_LED_START,		/* Machine starts, especially resume */
+	CPU_LED_STOP,		/* Machine stops, especially suspend */
+	CPU_LED_HALTED,		/* Machine shutdown */
+};
+
+/* Use this routine to handle LEDs */
+extern void ledtrig_cpu(enum cpu_led_event evt);
+#else
+#define ledtrig_cpu(evt) do {} while (0)
+#endif
+
 #endif		/* __LINUX_LEDS_H_INCLUDED */
-- 
1.7.9



From catalin.marinas at arm.com  Thu Mar  8 04:21:22 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 8 Mar 2012 09:21:22 +0000
Subject: [PATCH 1/7] Add various hugetlb arm high level hooks
In-Reply-To: <4F57FED8.7050708@gmail.com>
References: <1329126268-11032-1-git-send-email-bill4carson@gmail.com>
 <1329126268-11032-2-git-send-email-bill4carson@gmail.com>
 <20120229103207.GB17745@arm.com> <4F4E0BDE.6040708@gmail.com>
 <20120229153814.GK17745@arm.com> <4F57FED8.7050708@gmail.com>
Message-ID: <20120308092121.GA26727@arm.com>

On Thu, Mar 08, 2012 at 12:35:36AM +0000, bill4carson wrote:
> On 2012?02?29? 23:38, Catalin Marinas wrote:
> > On Wed, Feb 29, 2012 at 11:28:30AM +0000, bill4carson wrote:
> >> On 2012?02?29? 18:32, Catalin Marinas wrote:
> >>> On Mon, Feb 13, 2012 at 09:44:22AM +0000, Bill Carson wrote:
> >>>> +static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
> >>>> +					   unsigned long addr, pte_t *ptep)
> >>>> +{
> >>>> +	pte_t old_pte = *ptep;
> >>>> +	set_huge_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
> >>>> +}
> >>>
> >>> You could use the generic ptep_set_wrprotect()
> >>
> >> I'm a bit of confused about this.
> >>
> >> generic ptep_set_wrprotect() can not set huge pte, that's why
> >> set_huge_pte_at is used instead here.
> >
> > Ah, the generic one can only work with with LPAE where set_huge_pte_at()
> > is just a set_pte_at(). So this part looks good.
> 
> Thanks for your time to review PATCH1/7 :)
> 
> I'm wondering if reset of this patch set is ok,
> I would like to start working on V3 as per your comments.

I haven't finished looking through the patches. Probably I will by the
end of this week.

-- 
Catalin


From peter.ujfalusi at ti.com  Thu Mar  8 04:22:14 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu,  8 Mar 2012 11:22:14 +0200
Subject: [PATCH v2 0/3] ARM/ASoC: OMAP McBSP: Correct CLKR/FSR source selection
Message-ID: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>

Hello,

Changes since v1:
- Adapted to the moved mcbsp code which helped to reduce the number of patches
  from 5 to 3.
- Clock selection related defines moved from arch to ASoC header.

No change in functionality otherwise.

This series fixes the CLKR/FSR mux selection (on McBSP ports with 6 pin setup).
OMAP2/3 has 6 pin setup on McBSP1 port while OMAP4 has the 6 pin setup on McBSP4
port.
Add support for OMAP4 CLKR/FSR source selection, and simplify the ASoC part of
CLK mux configuration.

This series should go via ASoC with the rest of McBSP changes.

Regards,
Peter
---
Peter Ujfalusi (3):
  ARM: OMAP2+: McBSP: Correct CLKR/FSR clock source mux configuration
  ARM/ASoC: OMAP McBSP: Move remainig defines from arch to ASoC header
  ASoC: omap-mcbsp: Single function CLKR/FSR source mux configuration

 arch/arm/mach-omap2/mcbsp.c             |   46 ++++++++++++++++++++++++++++-
 arch/arm/plat-omap/include/plat/mcbsp.h |   12 --------
 sound/soc/omap/mcbsp.c                  |   48 ++++++++++++++----------------
 sound/soc/omap/mcbsp.h                  |   13 +++++++-
 sound/soc/omap/omap-mcbsp.c             |    8 ++--
 5 files changed, 81 insertions(+), 46 deletions(-)

-- 
1.7.8.5



From peter.ujfalusi at ti.com  Thu Mar  8 04:22:15 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu,  8 Mar 2012 11:22:15 +0200
Subject: [PATCH v2 1/3] ARM: OMAP2+: McBSP: Correct CLKR/FSR clock source mux
 configuration
In-Reply-To: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1331198537-13469-2-git-send-email-peter.ujfalusi@ti.com>

On OMAP2/3 McBSP1 port has 6 pin setup, while on OMAP4 the port is McBSP4.
Implement the CLKR/FSR clock mux selection for OMAP4, and make sure that
we add the correct callback for the correct port across supported OMAP
versions.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 arch/arm/mach-omap2/mcbsp.c |   46 +++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 49ff5b8..ecc039e 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -34,7 +34,7 @@
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
-/* McBSP internal signal muxing function */
+/* McBSP1 internal signal muxing function for OMAP2/3 */
 static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
 				   const char *src)
 {
@@ -65,6 +65,42 @@ static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
 	return 0;
 }
 
+/* McBSP4 internal signal muxing function for OMAP4 */
+#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX	(1 << 31)
+#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX	(1 << 30)
+static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
+				   const char *src)
+{
+	u32 v;
+
+	/*
+	 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
+	 * mux) is used */
+	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
+
+	if (!strcmp(signal, "clkr")) {
+		if (!strcmp(src, "clkr"))
+			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
+		else if (!strcmp(src, "clkx"))
+			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
+		else
+			return -EINVAL;
+	} else if (!strcmp(signal, "fsr")) {
+		if (!strcmp(src, "fsr"))
+			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
+		else if (!strcmp(src, "fsx"))
+			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
+		else
+			return -EINVAL;
+	} else {
+		return -EINVAL;
+	}
+
+	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
+
+	return 0;
+}
+
 /* McBSP CLKS source switching function */
 static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
 				   const char *src)
@@ -146,9 +182,15 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 		pdata->has_ccr = true;
 	}
 	pdata->set_clk_src = omap2_mcbsp_set_clk_src;
-	if (id == 1)
+
+	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
+	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
 		pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
 
+	/* On OMAP4 the McBSP4 port has 6 pin configuration */
+	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
+		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
+
 	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
 		if (id == 2)
 			/* The FIFO has 1024 + 256 locations */
-- 
1.7.8.5



From peter.ujfalusi at ti.com  Thu Mar  8 04:22:16 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu,  8 Mar 2012 11:22:16 +0200
Subject: [PATCH v2 2/3] ARM/ASoC: OMAP McBSP: Move remainig defines from arch
 to ASoC header
In-Reply-To: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1331198537-13469-3-git-send-email-peter.ujfalusi@ti.com>

Clock signal muxing, and functional clock related defines are only needed
in ASoC drivers.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 arch/arm/plat-omap/include/plat/mcbsp.h |   12 ------------
 sound/soc/omap/mcbsp.h                  |   12 ++++++++++++
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 8eb9b0e..1881412 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -31,18 +31,6 @@
 #define MCBSP_CONFIG_TYPE3	0x3
 #define MCBSP_CONFIG_TYPE4	0x4
 
-/* CLKR signal muxing options */
-#define CLKR_SRC_CLKR		0
-#define CLKR_SRC_CLKX		1
-
-/* FSR signal muxing options */
-#define FSR_SRC_FSR		0
-#define FSR_SRC_FSX		1
-
-/* McBSP functional clock sources */
-#define MCBSP_CLKS_PRCM_SRC	0
-#define MCBSP_CLKS_PAD_SRC	1
-
 /* Platform specific configuration */
 struct omap_mcbsp_ops {
 	void (*request)(unsigned int);
diff --git a/sound/soc/omap/mcbsp.h b/sound/soc/omap/mcbsp.h
index a5518d7..acc9470 100644
--- a/sound/soc/omap/mcbsp.h
+++ b/sound/soc/omap/mcbsp.h
@@ -230,6 +230,18 @@ enum {
 #define XRDYEN			BIT(10)
 #define XEMPTYEOFEN		BIT(14)
 
+/* CLKR signal muxing options */
+#define CLKR_SRC_CLKR		0
+#define CLKR_SRC_CLKX		1
+
+/* FSR signal muxing options */
+#define FSR_SRC_FSR		0
+#define FSR_SRC_FSX		1
+
+/* McBSP functional clock sources */
+#define MCBSP_CLKS_PRCM_SRC	0
+#define MCBSP_CLKS_PAD_SRC	1
+
 /* we don't do multichannel for now */
 struct omap_mcbsp_reg_cfg {
 	u16 spcr2;
-- 
1.7.8.5



From peter.ujfalusi at ti.com  Thu Mar  8 04:22:17 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu,  8 Mar 2012 11:22:17 +0200
Subject: [PATCH v2 3/3] ASoC: omap-mcbsp: Single function CLKR/FSR source mux
 configuration
In-Reply-To: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1331198537-13469-4-git-send-email-peter.ujfalusi@ti.com>

Use single function for the CLKR/FSR mux configuration.
OMAP2/3 has 6 pin configuration on McBSP1 instance, while on OMAP4
McBSP4 instance have the 6 pin configuration so the omap2_mcbsp1_mux_* is
not correct name for all support OMAP versions

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
---
 sound/soc/omap/mcbsp.c      |   48 +++++++++++++++++++-----------------------
 sound/soc/omap/mcbsp.h      |   15 +++++--------
 sound/soc/omap/omap-mcbsp.c |    8 +++---
 3 files changed, 32 insertions(+), 39 deletions(-)

diff --git a/sound/soc/omap/mcbsp.c b/sound/soc/omap/mcbsp.c
index c3e31de..95413a1 100644
--- a/sound/soc/omap/mcbsp.c
+++ b/sound/soc/omap/mcbsp.c
@@ -687,40 +687,36 @@ int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
 		return -EINVAL;
 }
 
-void omap2_mcbsp1_mux_clkr_src(struct omap_mcbsp *mcbsp, u8 mux)
+int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
 {
-	const char *src;
-
-	if (mcbsp->id != 1)
-		return;
+	const char *signal, *src;
+	int ret = 0;
 
-	if (mux == CLKR_SRC_CLKR)
+	switch (mux) {
+	case CLKR_SRC_CLKR:
+		signal = "clkr";
 		src = "clkr";
-	else if (mux == CLKR_SRC_CLKX)
+		break;
+	case CLKR_SRC_CLKX:
+		signal = "clkr";
 		src = "clkx";
-	else
-		return;
-
-	if (mcbsp->pdata->mux_signal)
-		mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src);
-}
-
-void omap2_mcbsp1_mux_fsr_src(struct omap_mcbsp *mcbsp, u8 mux)
-{
-	const char *src;
-
-	if (mcbsp->id != 1)
-		return;
-
-	if (mux == FSR_SRC_FSR)
+		break;
+	case FSR_SRC_FSR:
+		signal = "fsr";
 		src = "fsr";
-	else if (mux == FSR_SRC_FSX)
+		break;
+	case FSR_SRC_FSX:
+		signal = "fsr";
 		src = "fsx";
-	else
-		return;
+		break;
+	default:
+		return -EINVAL;
+	}
 
 	if (mcbsp->pdata->mux_signal)
-		mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src);
+		ret = mcbsp->pdata->mux_signal(mcbsp->dev, signal, src);
+
+	return ret;
 }
 
 #define max_thres(m)			(mcbsp->pdata->buffer_size)
diff --git a/sound/soc/omap/mcbsp.h b/sound/soc/omap/mcbsp.h
index acc9470..a944fcc 100644
--- a/sound/soc/omap/mcbsp.h
+++ b/sound/soc/omap/mcbsp.h
@@ -230,13 +230,11 @@ enum {
 #define XRDYEN			BIT(10)
 #define XEMPTYEOFEN		BIT(14)
 
-/* CLKR signal muxing options */
-#define CLKR_SRC_CLKR		0
-#define CLKR_SRC_CLKX		1
-
-/* FSR signal muxing options */
-#define FSR_SRC_FSR		0
-#define FSR_SRC_FSX		1
+/* Clock signal muxing options */
+#define CLKR_SRC_CLKR		0 /* CLKR signal is from the CLKR pin */
+#define CLKR_SRC_CLKX		1 /* CLKR signal is from the CLKX pin */
+#define FSR_SRC_FSR		2 /* FSR signal is from the FSR pin */
+#define FSR_SRC_FSX		3 /* FSR signal is from the FSX pin */
 
 /* McBSP functional clock sources */
 #define MCBSP_CLKS_PRCM_SRC	0
@@ -333,8 +331,7 @@ void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx);
 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id);
 
 /* McBSP signal muxing API */
-void omap2_mcbsp1_mux_clkr_src(struct omap_mcbsp *mcbsp, u8 mux);
-void omap2_mcbsp1_mux_fsr_src(struct omap_mcbsp *mcbsp, u8 mux);
+int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux);
 
 /* Sidetone specific API */
 int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain);
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 10eb645..d8409b0 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -554,22 +554,22 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 	case OMAP_MCBSP_CLKR_SRC_CLKR:
 		if (cpu_class_is_omap1())
 			break;
-		omap2_mcbsp1_mux_clkr_src(mcbsp, CLKR_SRC_CLKR);
+		err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKR);
 		break;
 	case OMAP_MCBSP_CLKR_SRC_CLKX:
 		if (cpu_class_is_omap1())
 			break;
-		omap2_mcbsp1_mux_clkr_src(mcbsp, CLKR_SRC_CLKX);
+		err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKX);
 		break;
 	case OMAP_MCBSP_FSR_SRC_FSR:
 		if (cpu_class_is_omap1())
 			break;
-		omap2_mcbsp1_mux_fsr_src(mcbsp, FSR_SRC_FSR);
+		err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSR);
 		break;
 	case OMAP_MCBSP_FSR_SRC_FSX:
 		if (cpu_class_is_omap1())
 			break;
-		omap2_mcbsp1_mux_fsr_src(mcbsp, FSR_SRC_FSX);
+		err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSX);
 		break;
 	default:
 		err = -ENODEV;
-- 
1.7.8.5



From bryan.wu at canonical.com  Thu Mar  8 04:23:49 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Thu, 8 Mar 2012 17:23:49 +0800
Subject: [PATCH] leds: kill CONFIG_LEDS_CLASS option
In-Reply-To: <1323356570.5309.25.camel@ted>
References: <1314647628-21707-1-git-send-email-bryan.wu@canonical.com>
 <alpine.LFD.2.00.1108291630020.20358@xanadu.home>
 <1314653699.5939.299.camel@rex>
 <CAK5ve-+J3hzVB=_b0AOJ-Q1LYewahVraMti=y=6AaQy3+iy+rg@mail.gmail.com>
 <1314791341.5939.464.camel@rex>
 <CAK5ve-LcUabPS2EGAPD7q3-_thS4XhmGyhafmRkOCUAAriaXSw@mail.gmail.com>
 <1323356570.5309.25.camel@ted>
Message-ID: <CAK5ve-LikCFcWGgcmLYgOG_TNnLZ=LPj9XdWXVgCWXgLP6G+jQ@mail.gmail.com>

On Thu, Dec 8, 2011 at 11:02 PM, Richard Purdie <rpurdie at rpsys.net> wrote:
> On Thu, 2011-12-08 at 19:53 +0800, Bryan Wu wrote:
>> On Wed, Aug 31, 2011 at 7:49 PM, Richard Purdie <rpurdie at rpsys.net> wrote:
>> > On Wed, 2011-08-31 at 10:45 +0800, Bryan Wu wrote:
>> >> On Tue, Aug 30, 2011 at 5:34 AM, Richard Purdie <rpurdie at rpsys.net> wrote:
>> >> > On Mon, 2011-08-29 at 16:34 -0400, Nicolas Pitre wrote:
>> >> >> On Tue, 30 Aug 2011, Bryan Wu wrote:
>> >> >>
>> >> >> > Almost all the new leds driver and trigger driver are depends on
>> >> >> > CONFIG_LED_CLASS, so there is no such user with CONFIG_NEW_LEDS=y
>> >> >> > and CONFIG_LED_CLASS=n. Moreover, lots of API functions in led-class.c
>> >> >> > are very common and should be built-in when CONFIG_NEW_LEDS=y.
>> >> >> >
>> >> >> > Obviously, CONFIG_LEDS_CLASS is pointless. This patch kills it and
>> >> >> > also updates defconfigs which contains CONFIG_LEDS_CLASS.
>> >> >> >
>> >> >> > Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
>> >> >> > ---
>> >> >
>> >> > Looking at the code I'm a little concerned to see the direction this is
>> >> > going. There was originally a reason that there were two options, it was
>> >> > related to being able to compile as much of the LED code as a module as
>> >> > possible.
>> >> >
>> >>
>> >> I quite understand the original reason for 2 options, but I failed to
>> >> see any user of CONFIG_NEW_LEDS=y and CONFIG_LEDS_CLASS=n.
>> >
>> > Right, the intent was to support CONFIG_NEW_LEDS=y and
>> > CONFIG_LEDS_CLASS=m and I believe that still should be possible.
>> >
>> >> > It looks like commit 5ada28bf76752e33dce3d807bf0dfbe6d1b943ad changed
>> >> > the tristate to a bool at which point the separate option obviously
>> >> > becomes pointless.
>> >>
>> >> Exactly, this patch added some function API which are used very widely
>> >> as default LEDS driver behavior in some drivers.
>> >
>> > Looking at that commit, its adds the code to leds-class.c and shouldn't
>> > have needed to change the tristate to a bool. I know we discussed that
>> > at the time and I think that part might have been unnecessary and just
>> > accidentally committed. It could well be we can just revert that piece
>> > of the patch.
>> >
>>
>> Richard,
>>
>> Sorry for bringing up this topic so late. I was occupied by other
>> stuff for a while.
>>
>> I'm trying to make leds-class.c as a module, but found APIs exported
>> from led-class.c are widely used in kernel.
>>
>> For example: led_classdev_register()
>> --
>> linux-2.6$ grep -r led_classdev_register .
>> ./include/linux/leds.h:extern int led_classdev_register(struct device *parent,
>> ./drivers/mmc/host/au1xmmc.c: ? ? ? ? ret = led_classdev_register(mmc_dev(mmc), led);
>
> If there are users of the LED API compiled in, then the config code
> should be handling this so the led class code is compiled in too.
>
> That shouldn't make it impossible to have the class code as a module, if
> the users are also modules.
>
>> When CONFIG_NEW_LEDS=y, CONFIG_LEDS_CLASS=m and CONFIG_LEDS_TRIGGER=y,
>> I got following error for building omap2plus_defconfig
>> --
>> arch/arm/plat-omap/built-in.o: In function `newled_init':
>> /opt/git/linux-2.6/arch/arm/plat-omap/debug-leds.c:248: undefined
>> reference to `led_classdev_register'
>
> So this is a dependency issues as far as I can see,
>
>> drivers/built-in.o: In function `led_trigger_blink':
>> /opt/git/linux-2.6/drivers/leds/led-triggers.c:248: undefined
>> reference to `led_blink_set'
>> drivers/built-in.o: In function `led_trigger_set':
>> /opt/git/linux-2.6/drivers/leds/led-triggers.c:116: undefined
>> reference to `led_brightness_set'
>
> but I agree these are more problematic.
>
>> The commit 5ada28bf76752e33dce3d807bf0dfbe6d1b943ad "led-class: always
>> implement blinking" added 2 API (led_blink_set and
>> `led_brightness_set'), which are used by led-trigger.c
>>
>> For this kind of errors, I think it's quite hard to set led-class.c as
>> a module now and suggest we merge NEW_LEDS and LEDS_CLASS together.
>
> I still don't believe this is necessary.
>
> How about moving led_timer_function(), led_set_software_blink()
> led_blink_set() and to led-triggers.c, putting #ifdef
> CONFIG_LEDS_TRIGGERS around the appropriate pieces of leds-class.c. We'd
> then move led_brightness_set() and led_stop_software_blink() to
> led-core.c since those are the real problem.
>
> It means there is a slightly higher always loaded footprint but its
> better than giving up and making it all always loaded.
>

Richard,

So sorry for the delay, I was occupied by other stuff for a long time.

As you pointed out, I moved some code to led-core.c to solve the
issue, please find my patch about that.

Thanks,
-- 
Bryan Wu <bryan.wu at canonical.com>
Kernel Developer ? ?+86.138-1617-6545 Mobile
Canonical Ltd. ? ? ?www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com


From florian at openwrt.org  Thu Mar  8 04:27:58 2012
From: florian at openwrt.org (Florian Fainelli)
Date: Thu, 08 Mar 2012 10:27:58 +0100
Subject: [PATCH v6] lpc32xx: Added ethernet driver
In-Reply-To: <1331151693-21726-1-git-send-email-stigge@antcom.de>
References: <1331151693-21726-1-git-send-email-stigge@antcom.de>
Message-ID: <4F587B9E.4000708@openwrt.org>

Hi Roland,

Le 03/07/12 21:21, Roland Stigge a ?crit :
> This patch adds an ethernet driver for the LPC32xx ARM SoC.
>
> Signed-off-by: Roland Stigge<stigge at antcom.de>

I have a couple of phylib-related comments addressed inline.

>
> ---
>
> Applies to v3.3-rc6
>
> Changes since v5:
>   * Indentation and whitespace fixes
>   * Use __le32 for descriptors
>   * Use bool for boolean function parameters
>   * Removed unnecessary (u32) cast
>   * Added comment regarding future device tree introduction
>
>   Thanks to David Miller, Arnd Bergmann and Joe Perches for
>   reviewing the last version!
>
>   drivers/net/ethernet/Kconfig       |    1
>   drivers/net/ethernet/Makefile      |    1
>   drivers/net/ethernet/nxp/Kconfig   |    8
>   drivers/net/ethernet/nxp/Makefile  |    1
>   drivers/net/ethernet/nxp/lpc_eth.c | 1616 +++++++++++++++++++++++++++++++++++++
>   5 files changed, 1627 insertions(+)
>
> --- linux-2.6.orig/drivers/net/ethernet/Kconfig
> +++ linux-2.6/drivers/net/ethernet/Kconfig

> +
> +static int lpc_mii_probe(struct net_device *ndev)
> +{
> +	struct netdata_local *pldat = netdev_priv(ndev);
> +	struct phy_device *phydev = NULL;
> +	int phy_addr;
> +
> +	/* find the first phy */
> +	for (phy_addr = 0; phy_addr<  PHY_MAX_ADDR; phy_addr++) {
> +		if (pldat->mii_bus->phy_map[phy_addr]) {
> +			phydev = pldat->mii_bus->phy_map[phy_addr];
> +			break;
> +		}
> +	}

Please use phy_find_first() instead of open-coding this.

> +
> +	if (!phydev) {
> +		netdev_err(ndev, "no PHY found\n");
> +		return -ENODEV;
> +	}
> +
> +	/* Attach to the PHY */
> +	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
> +		netdev_info(ndev, "using MII interface\n");
> +	else
> +		netdev_info(ndev, "using RMII interface\n");
> +	phydev = phy_connect(ndev, dev_name(&phydev->dev),
> +		&lpc_handle_link_change, 0, lpc_phy_interface_mode());
> +
> +	if (IS_ERR(phydev)) {
> +		netdev_err(ndev, "Could not attach to PHY\n");
> +		return PTR_ERR(phydev);
> +	}
> +
> +	/* mask with MAC supported features */
> +	phydev->supported&= PHY_BASIC_FEATURES;
> +
> +	phydev->advertising = phydev->supported;
> +
> +	pldat->link = 0;
> +	pldat->speed = 0;
> +	pldat->duplex = -1;
> +	pldat->phy_dev = phydev;
> +
> +	return 0;
> +}
> +
> +static int lpc_mii_init(struct netdata_local *pldat)
> +{
> +	int err = -ENXIO, i;
> +
> +	pldat->mii_bus = mdiobus_alloc();
> +	if (!pldat->mii_bus) {
> +		err = -ENOMEM;
> +		goto err_out;
> +	}
> +
> +	/* Setup MII mode */
> +	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
> +		writel(LPC_COMMAND_PASSRUNTFRAME,
> +		       LPC_ENET_COMMAND(pldat->net_base));
> +	else {
> +		writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
> +		       LPC_ENET_COMMAND(pldat->net_base));
> +		writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
> +	}
> +
> +	pldat->mii_bus->name = "lpc_mii_bus";
> +	pldat->mii_bus->read =&lpc_mdio_read;
> +	pldat->mii_bus->write =&lpc_mdio_write;
> +	pldat->mii_bus->reset =&lpc_mdio_reset;
> +	snprintf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%x", pldat->pdev->id);

No, makes this bus name unique in the system:
snprnitf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
	pldat->pdev->name, pldat->pdev->id);

> +	pldat->mii_bus->priv = pldat;
> +	pldat->mii_bus->parent =&pldat->pdev->dev;
> +	pldat->mii_bus->phy_mask = 0xFFFFFFF0;

I would rather not hardcode the phy_mask here, just leave it to 0, and 
let phy_find_first() find the PHY devices for you, or make this platform 
configurable.

> +
> +	pldat->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
> +	if (!pldat->mii_bus->irq) {
> +		err = -ENOMEM;
> +		goto err_out_1;
> +	}
> +
> +	for (i = 0; i<  PHY_MAX_ADDR; i++)
> +		pldat->mii_bus->irq[i] = PHY_POLL;
> +
> +	platform_set_drvdata(pldat->pdev, pldat->mii_bus);
> +
> +	if (mdiobus_register(pldat->mii_bus))
> +		goto err_out_free_mdio_irq;
> +
> +	if (lpc_mii_probe(pldat->ndev) != 0)
> +		goto err_out_unregister_bus;
> +
> +	return 0;
> +
> +err_out_unregister_bus:
> +	mdiobus_unregister(pldat->mii_bus);
> +err_out_free_mdio_irq:
> +	kfree(pldat->mii_bus->irq);
> +err_out_1:
> +	mdiobus_free(pldat->mii_bus);
> +err_out:
> +	return err;
> +}
> +

[snip]

> +
> +static int lpc_eth_open(struct net_device *ndev)
> +{
> +	struct netdata_local *pldat = netdev_priv(ndev);
> +
> +	/* if the phy is not yet registered, retry later*/
> +	if (!pldat->phy_dev)
> +		return -EAGAIN;

You have already probed the mii bus in the driver's probe function, how 
can you end up here without a phy being attached here?

[snip]

> +	if (lpc_mii_init(pldat) != 0)
> +		goto err_out_unregister_netdev;
> +
> +	netdev_info(ndev, "LPC mac at 0x%08x irq %d\n",
> +	       res->start, ndev->irq);
> +
> +	phydev = pldat->phy_dev;
> +	netdev_info(ndev,
> +		"attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
> +		phydev->drv->name, dev_name(&phydev->dev), phydev->irq);

Most drivers put this informational message in their mii probing 
function, please move it here as well.

> +
> +	device_init_wakeup(&pdev->dev, 1);
> +	device_set_wakeup_enable(&pdev->dev, 0);
> +
> +	return 0;
> +
> +err_out_unregister_netdev:
> +	platform_set_drvdata(pdev, NULL);
> +	unregister_netdev(ndev);
> +err_out_dma_unmap:
> +	if (!use_iram_for_net() ||
> +	    pldat->dma_buff_size>  lpc32xx_return_iram_size())
> +		dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
> +				  pldat->dma_buff_base_v,
> +				  pldat->dma_buff_base_p);
> +err_out_free_irq:
> +	free_irq(ndev->irq, ndev);
> +err_out_iounmap:
> +	iounmap(pldat->net_base);
> +err_out_disable_clocks:
> +	clk_disable(pldat->clk);
> +	clk_put(pldat->clk);
> +err_out_free_dev:
> +	free_netdev(ndev);
> +err_exit:
> +	pr_err("%s: not found (%d).\n", MODNAME, ret);
> +	return ret;
> +}
> +
> +static int lpc_eth_drv_remove(struct platform_device *pdev)
> +{
> +	struct net_device *ndev = platform_get_drvdata(pdev);
> +	struct netdata_local *pldat = netdev_priv(ndev);
> +
> +	unregister_netdev(ndev);
> +	platform_set_drvdata(pdev, NULL);
> +
> +	if (!use_iram_for_net() ||
> +	    pldat->dma_buff_size>  lpc32xx_return_iram_size())
> +		dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
> +				  pldat->dma_buff_base_v,
> +				  pldat->dma_buff_base_p);
> +	free_irq(ndev->irq, ndev);
> +	iounmap(pldat->net_base);
> +	clk_disable(pldat->clk);
> +	clk_put(pldat->clk);
> +	free_netdev(ndev);

You are not freeing the mii bus in the driver's remove path.
--
Florian


From u.kleine-koenig at pengutronix.de  Thu Mar  8 04:29:13 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 8 Mar 2012 10:29:13 +0100
Subject: [PATCH 2/3] led-triggers: use atomic kzalloc during led trigger
 registering
In-Reply-To: <1331197863-25564-2-git-send-email-bryan.wu@canonical.com>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
 <1331197863-25564-2-git-send-email-bryan.wu@canonical.com>
Message-ID: <20120308092913.GF14173@pengutronix.de>

On Thu, Mar 08, 2012 at 05:11:02PM +0800, Bryan Wu wrote:
> kzalloc might cause sleep and will generate some warning detected by lockdep,
> when call led_trigger_register_simple on each cpu cores in SMP. This patch fix
> this.
The obvious (and IMHO better) alternative is to call
led_trigger_register_simple from non-atomic context.

For registering this should be OK, shouldn't it?

Best regards
Uwe

> 
> [    1.999938] ------------[ cut here ]------------
> [    2.004791] WARNING: at kernel/lockdep.c:2664 lockdep_trace_alloc+0xd8/0xf0()
> [    2.012298] Modules linked in:
> [    2.015563] [<c001b0cc>] (unwind_backtrace+0x0/0xf0) from [<c0052408>] (warn_slowpath_common+0x4c/0x64)
> [    2.025451] [<c0052408>] (warn_slowpath_common+0x4c/0x64) from [<c005243c>] (warn_slowpath_null+0x1c/0x24)
> [    2.035583] [<c005243c>] (warn_slowpath_null+0x1c/0x24) from [<c008be28>] (lockdep_trace_alloc+0xd8/0xf0)
> [    2.045684] [<c008be28>] (lockdep_trace_alloc+0xd8/0xf0) from [<c00feeb4>] (kmem_cache_alloc_trace+0x2c/0x148)
> [    2.056213] [<c00feeb4>] (kmem_cache_alloc_trace+0x2c/0x148) from [<c03770a0>] (led_trigger_register_simple+0x20/0x74)
> [    2.067474] [<c03770a0>] (led_trigger_register_simple+0x20/0x74) from [<c0627a30>] (ledtrig_cpu_register+0x4c/0x8c)
> [    2.078460] [<c0627a30>] (ledtrig_cpu_register+0x4c/0x8c) from [<c0094ca4>] (generic_smp_call_function_single_interrupt+0xcc/0x138)
> [    2.090911] [<c0094ca4>] (generic_smp_call_function_single_interrupt+0xcc/0x138) from [<c0008408>] (do_IPI+0xb0/0x128)
> [    2.102172] [<c0008408>] (do_IPI+0xb0/0x128) from [<c045921c>] (__irq_svc+0x3c/0x100)
> [    2.110412] Exception stack(0xc07adf70 to 0xc07adfb8)
> [    2.115722] df60:                                     c07c80f8 0000fb45 00000000 c07c80f8
> [    2.124328] df80: c07ac000 c0837be4 c0464b64 c07c9d8c 00000000 411fc092 00000000 00000000
> [    2.132934] dfa0: c0649760 c07adfb8 c07c5c58 c0014d50 20000013 ffffffff
> [    2.139892] [<c045921c>] (__irq_svc+0x3c/0x100) from [<c0014d50>] (default_idle+0x30/0x38)
> [    2.148590] [<c0014d50>] (default_idle+0x30/0x38) from [<c0014f74>] (cpu_idle+0xb4/0xf4)
> [    2.157135] [<c0014f74>] (cpu_idle+0xb4/0xf4) from [<c0602778>] (start_kernel+0x2a8/0x2fc)
> [    2.165832] [<c0602778>] (start_kernel+0x2a8/0x2fc) from [<80008040>] (0x80008040)
> [    2.173797] ---[ end trace 97549d21d8dad3f5 ]---
> 
> Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
> ---
>  drivers/leds/led-triggers.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/leds/led-triggers.c b/drivers/leds/led-triggers.c
> index 46b4c76..74d0ba7 100644
> --- a/drivers/leds/led-triggers.c
> +++ b/drivers/leds/led-triggers.c
> @@ -255,7 +255,7 @@ void led_trigger_register_simple(const char *name, struct led_trigger **tp)
>  	struct led_trigger *trigger;
>  	int err;
>  
> -	trigger = kzalloc(sizeof(struct led_trigger), GFP_KERNEL);
> +	trigger = kzalloc(sizeof(struct led_trigger), GFP_ATOMIC);
>  
>  	if (trigger) {
>  		trigger->name = name;
> -- 
> 1.7.9
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From peter.ujfalusi at ti.com  Thu Mar  8 04:29:36 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Thu, 08 Mar 2012 11:29:36 +0200
Subject: [PATCH v2 2/3] ARM/ASoC: OMAP McBSP: Move remainig defines from
 arch to ASoC header
In-Reply-To: <1331198537-13469-3-git-send-email-peter.ujfalusi@ti.com>
References: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>
 <1331198537-13469-3-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <4F587C00.1090307@ti.com>

Hi Jarkko,

On 03/08/2012 11:22 AM, Peter Ujfalusi wrote:
> Clock signal muxing, and functional clock related defines are only needed
> in ASoC drivers.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>

I have added your ack to this patch by accident when I updated the
series. Sorry about that.
Please confirm if you are OK with this change.

Sorry again,
P?ter

> ---
>  arch/arm/plat-omap/include/plat/mcbsp.h |   12 ------------
>  sound/soc/omap/mcbsp.h                  |   12 ++++++++++++
>  2 files changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
> index 8eb9b0e..1881412 100644
> --- a/arch/arm/plat-omap/include/plat/mcbsp.h
> +++ b/arch/arm/plat-omap/include/plat/mcbsp.h
> @@ -31,18 +31,6 @@
>  #define MCBSP_CONFIG_TYPE3	0x3
>  #define MCBSP_CONFIG_TYPE4	0x4
>  
> -/* CLKR signal muxing options */
> -#define CLKR_SRC_CLKR		0
> -#define CLKR_SRC_CLKX		1
> -
> -/* FSR signal muxing options */
> -#define FSR_SRC_FSR		0
> -#define FSR_SRC_FSX		1
> -
> -/* McBSP functional clock sources */
> -#define MCBSP_CLKS_PRCM_SRC	0
> -#define MCBSP_CLKS_PAD_SRC	1
> -
>  /* Platform specific configuration */
>  struct omap_mcbsp_ops {
>  	void (*request)(unsigned int);
> diff --git a/sound/soc/omap/mcbsp.h b/sound/soc/omap/mcbsp.h
> index a5518d7..acc9470 100644
> --- a/sound/soc/omap/mcbsp.h
> +++ b/sound/soc/omap/mcbsp.h
> @@ -230,6 +230,18 @@ enum {
>  #define XRDYEN			BIT(10)
>  #define XEMPTYEOFEN		BIT(14)
>  
> +/* CLKR signal muxing options */
> +#define CLKR_SRC_CLKR		0
> +#define CLKR_SRC_CLKX		1
> +
> +/* FSR signal muxing options */
> +#define FSR_SRC_FSR		0
> +#define FSR_SRC_FSX		1
> +
> +/* McBSP functional clock sources */
> +#define MCBSP_CLKS_PRCM_SRC	0
> +#define MCBSP_CLKS_PAD_SRC	1
> +
>  /* we don't do multichannel for now */
>  struct omap_mcbsp_reg_cfg {
>  	u16 spcr2;


From jarkko.nikula at bitmer.com  Thu Mar  8 04:37:31 2012
From: jarkko.nikula at bitmer.com (Jarkko Nikula)
Date: Thu, 08 Mar 2012 11:37:31 +0200
Subject: [PATCH v2 2/3] ARM/ASoC: OMAP McBSP: Move remainig defines from
 arch to ASoC header
In-Reply-To: <4F587C00.1090307@ti.com>
References: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>
 <1331198537-13469-3-git-send-email-peter.ujfalusi@ti.com>
 <4F587C00.1090307@ti.com>
Message-ID: <4F587DDB.5080202@bitmer.com>

On 03/08/2012 11:29 AM, Peter Ujfalusi wrote:
> Hi Jarkko,
> 
> On 03/08/2012 11:22 AM, Peter Ujfalusi wrote:
>> Clock signal muxing, and functional clock related defines are only needed
>> in ASoC drivers.
>>
>> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
>> Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>
> 
> I have added your ack to this patch by accident when I updated the
> series. Sorry about that.
> Please confirm if you are OK with this change.
> 
Go ahead :-)

-- 
Jarkko


From lars at metafoo.de  Thu Mar  8 04:25:49 2012
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Thu, 08 Mar 2012 10:25:49 +0100
Subject: [RFC PATCH] video:backlight: add dimming sysfs node
In-Reply-To: <4F58573C.3020407@samsung.com>
References: <4F58573C.3020407@samsung.com>
Message-ID: <4F587B1D.5080206@metafoo.de>

On 03/08/2012 07:52 AM, Donghwa Lee wrote:
> In backlight class, update_status() callback function is mostly used to change
> backlight brightness. When platform enter the dimming state, it is usually used.
> But, I think dimming state can be defined variety of method including brightness.
> So, it is need to differentiated node from brightness node.

What do you mean by dimming? Completely blank the display or just lower the
brightness to a certain level > 0? In the former case the bl_power sysfs
node already exposes such functionality. In the later case can you give an
example how this will be used and how a typical driver would implement this
functionality?

> 
> In set_dimming() callback function, developers can define variety dimming functions.
> 
> Signed-off-by: Donghwa Lee <dh09.lee at samsung.com>
> Signed-off-by: Inki Dae <inki.dae at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  drivers/video/backlight/backlight.c |   37 +++++++++++++++++++++++++++++++++++
>  include/linux/backlight.h           |    9 ++++++++
>  2 files changed, 46 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c
> index bf5b1ec..44a77e4 100644
> --- a/drivers/video/backlight/backlight.c
> +++ b/drivers/video/backlight/backlight.c
> @@ -101,6 +101,43 @@ static void backlight_generate_event(struct backlight_device *bd,
>  	sysfs_notify(&bd->dev.kobj, NULL, "actual_brightness");
>  }
>  
> +static ssize_t backlight_store_dimming(struct device *dev,
> +		struct device_attribute *attr, const char *buf, size_t count)
> +{
> +	int rc;
> +	struct backlight_device *bd = to_backlight_device(dev);
> +	unsigned long dimming;
> +
> +	rc = strict_strtoul(buf, 0, &dimming);
> +	if (rc)
> +		return rc;
> +
> +	if (dimming < 0)
> +		rc = -EINVAL;
> +	else {
> +		pr_debug("set dimming mode\n");
> +
> +		if (dimming)
> +			bd->props.dimming = true;
> +		else
> +			bd->props.dimming = false;
> +
> +		backlight_set_dimming(bd);
> +
> +		rc = count;
> +	}
> +
> +	return rc;
> +}
> +
> +static ssize_t backlight_show_dimming(struct device *dev,
> +		struct device_attribute *attr,char *buf)
> +{
> +	struct backlight_device *bd = to_backlight_device(dev);
> +
> +	return sprintf(buf, "%d\n", bd->props.dimming);
> +}
> +
>  static ssize_t backlight_show_power(struct device *dev,
>  		struct device_attribute *attr, char *buf)
>  {
> diff --git a/include/linux/backlight.h b/include/linux/backlight.h
> index 5ffc6dd..823717e 100644
> --- a/include/linux/backlight.h
> +++ b/include/linux/backlight.h
> @@ -55,10 +55,13 @@ struct backlight_ops {
>  	/* Check if given framebuffer device is the one bound to this backlight;
>  	   return 0 if not, !=0 if it is. If NULL, backlight always matches the fb. */
>  	int (*check_fb)(struct backlight_device *, struct fb_info *);
> +	/* Notify the backlight driver to enter the dimming state */
> +	int (*set_dimming)(struct backlight_device *);
>  };
>  
>  /* This structure defines all the properties of a backlight */
>  struct backlight_properties {
> +	bool dimming;
>  	/* Current User requested brightness (0 - max_brightness) */
>  	int brightness;
>  	/* Maximal value for brightness (read-only) */
> @@ -111,6 +114,12 @@ static inline void backlight_update_status(struct backlight_device *bd)
>  	mutex_unlock(&bd->update_lock);
>  }
>  
> +static inline void backlight_set_dimming(struct backlight_device *bd)
> +{
> +	if (bd->ops && bd->ops->set_dimming)
> +		bd->ops->set_dimming(bd);
> +}
> +
>  extern struct backlight_device *backlight_device_register(const char *name,
>  	struct device *dev, void *devdata, const struct backlight_ops *ops,
>  	const struct backlight_properties *props);



From kgene.kim at samsung.com  Thu Mar  8 04:48:36 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu,  8 Mar 2012 01:48:36 -0800
Subject: [PATCH] ARM: S3C2440: Fixed build error for s3c244x
Message-ID: <1331200116-2424-1-git-send-email-kgene.kim@samsung.com>

Fixed following:
arch/arm/mach-s3c2440/s3c244x.c: In function 's3c244x_restart':
arch/arm/mach-s3c2440/s3c244x.c:209: error: expected declaration or statement at end of input
make[1]: *** [arch/arm/mach-s3c24xx/s3c244x.o] Error 1
make: *** [arch/arm/mach-s3c24xx] Error 2

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
Hi Arnd, Olof,

This happened when I applied Heiko's 'Fix restart on S3C2442'.
It was my fault :( and this should be sent before release v3.3.

Please pick this up.

Thanks.
Kgene.

 arch/arm/mach-s3c2440/s3c244x.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c
index 744930a..d15852f 100644
--- a/arch/arm/mach-s3c2440/s3c244x.c
+++ b/arch/arm/mach-s3c2440/s3c244x.c
@@ -207,3 +207,4 @@ void s3c244x_restart(char mode, const char *cmd)
 
 	/* we'll take a jump through zero as a poor second */
 	soft_restart(0);
+}
-- 
1.7.4.4



From kgene.kim at samsung.com  Thu Mar  8 04:57:42 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 08 Mar 2012 01:57:42 -0800
Subject: [PATCH V6 1/5] ARM: exynos: Add support AFTR mode on EXYNOS4210
In-Reply-To: <CAMXH7KHtEcg5VSCNFarX9-GuKzWsh3k8Kz+bCu3ZtiqJpvWZZw@mail.gmail.com>
References: <1329805190-8874-1-git-send-email-amit.kachhap@linaro.org>	<1329805190-8874-2-git-send-email-amit.kachhap@linaro.org>	<CAMXH7KHTgzY7XZ=4rOxsu-Ra8SRTOsCg=YWOLBD1QDTskRbygw@mail.gmail.com>	<CAK44p22LOnJx=bZRfdzAHt7X_snhJGrNoBuXOfsgwBHLLuUziA@mail.gmail.com>
 <CAMXH7KHtEcg5VSCNFarX9-GuKzWsh3k8Kz+bCu3ZtiqJpvWZZw@mail.gmail.com>
Message-ID: <4F588296.8020601@samsung.com>

On 03/07/12 15:12, Rob Lee wrote:
> Hello Kukjim and Amit,
>
> Can you tell me the status of this patch?  I based my core cpuidle
> consolidation patchset on these changes.  My patchset seems to be
> acceptable now and I would like to do a git pull-request for
> linux-next, but I see these Exynos cpuidle changes have not yet made
> it to linux-next.
>
Hi Rob,

Probably, I missed merging its topic branch and I will do right now.
I think you can see it in a couple of hours.

Then, if any problems, please let me know.

Thanks for your reminder.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From Jon.Povey at racelogic.co.uk  Thu Mar  8 04:58:39 2012
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Thu, 8 Mar 2012 09:58:39 +0000
Subject: DaVinci unbanked GPIO IRQs broken
In-Reply-To: <DF0F476B391FA8409C78302C7BA518B6317EC8CA@DBDE01.ent.ti.com>
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE0BF41C8E81@Cloud.RL.local>

> On Fri, Jan 27, 2012 at 18:49:42, Nori, Sekhar wrote:
>> Hi Jon,
>>
>> On Tue, Jan 17, 2012 at 15:32:23, Nori, Sekhar wrote:
>>
>>> I was able to reproduce this on the EVM using v2.6.38 (works)
>>> and v3.2 + my patch (doesn't work). I just started poking some
>>> registers to see what is happening. Will keep you updated
>>> on any progress.
>>>
>>
>> Following patch fixes the issue of interrupt handler not getting
>> called. I tested it using GPIO3 on DM365. On applying this, I
>> see a constant rate of 4-5 interrupts per second on that line.
>> Yet to figure out what is triggering those. Anyway I will wait for
>> you to test this after you are back before sending this to Grant.
>
> Are you back? Did you get a chance to test this?

Hi, sorry about that. I was away for a month, and forgot about this.

Tested just now. It seems good, GPIO interrupts work under 3.2
with this patch same as they do if I revert the genirq change.

I noticed that something else is broken for me under 3.2 (my FPGA driver
fails to load bitstream) compared with 3.0, but that is also broken with
genirq reverted so I think it's a separate issue and your patch is good.

So,

Tested-By: Jon Povey <jon.povey at racelogic.co.uk>

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

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From paul.liu at linaro.org  Thu Mar  8 04:59:03 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Thu,  8 Mar 2012 17:59:03 +0800
Subject: [PATCH v10] Regulator: Add Anatop regulator driver
Message-ID: <1331200744-5986-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.

Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Liam Girdwood <lrg at ti.com>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Axel Lin <axel.lin at gmail.com>
---
 .../bindings/regulator/anatop-regulator.txt        |   28 +++
 drivers/regulator/Kconfig                          |    8 +
 drivers/regulator/Makefile                         |    1 +
 drivers/regulator/anatop-regulator.c               |  236 ++++++++++++++++++++
 4 files changed, 273 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.txt
 create mode 100644 drivers/regulator/anatop-regulator.c

diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
new file mode 100644
index 0000000..73363e76
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -0,0 +1,28 @@
+Anatop Voltage regulators
+
+Required properties:
+- compatible: Must be "fsl,anatop-regulator"
+- anatop-vol-bit-shift: Bit shift for the register
+- anatop-vol-bit-width: Number of bits used in the register
+- anatop-min-bit-val: Minimum value of this register
+- anatop-min-voltage: Minimum voltage of this regulator
+- anatop-max-voltage: Maximum voltage of this regulator
+
+Any property defined as part of the core regulator
+binding, defined in regulator.txt, can also be used.
+
+Example:
+
+	reg_vddpu: regulator-vddpu at 140 {
+		compatible = "fsl,anatop-regulator";
+		regulator-name = "vddpu";
+		regulator-min-microvolt = <725000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-always-on;
+		reg = <0x140>;
+		anatop-vol-bit-shift = <9>;
+		anatop-vol-bit-width = <5>;
+		anatop-min-bit-val = <1>;
+		anatop-min-voltage = <725000>;
+		anatop-max-voltage = <1300000>;
+	};
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 7a61b17..3857209 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -213,6 +213,14 @@ config REGULATOR_PCAP
 	 This driver provides support for the voltage regulators of the
 	 PCAP2 PMIC.
 
+config REGULATOR_ANATOP
+	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
+	depends on MFD_ANATOP
+	help
+	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
+	  regulators. It is recommended that this option be
+	  enabled on i.MX6 platform.
+
 config REGULATOR_MC13XXX_CORE
 	tristate
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 503bac8..8440871 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -48,5 +48,6 @@ obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
 obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
 obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
 obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
+obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
new file mode 100644
index 0000000..133a17b
--- /dev/null
+++ b/drivers/regulator/anatop-regulator.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+
+struct anatop_regulator {
+	const char *name;
+	u32 control_reg;
+	struct anatop *mfd;
+	int vol_bit_shift;
+	int vol_bit_width;
+	int min_bit_val;
+	int min_voltage;
+	int max_voltage;
+	struct regulator_desc rdesc;
+	struct regulator_init_data *initdata;
+};
+
+static int anatop_set_voltage(struct regulator_dev *reg, int min_uV,
+				  int max_uV, unsigned *selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	u32 val, sel;
+	int uv;
+
+	uv = min_uV;
+	dev_dbg(&reg->dev, "%s: uv %d, min %d, max %d\n", __func__,
+		uv, anatop_reg->min_voltage,
+		anatop_reg->max_voltage);
+
+	if (uv < anatop_reg->min_voltage) {
+		if (max_uV > anatop_reg->min_voltage)
+			uv = anatop_reg->min_voltage;
+		else
+			return -EINVAL;
+	}
+
+	if (anatop_reg->control_reg) {
+		sel = (uv - anatop_reg->min_voltage) / 25000;
+		if (sel * 25000 + anatop_reg->min_voltage
+		    > anatop_reg->max_voltage)
+			return -EINVAL;
+		val = anatop_reg->min_bit_val + sel;
+		*selector = sel;
+		dev_dbg(&reg->dev, "%s: calculated val %d\n", __func__, val);
+		anatop_set_bits(anatop_reg->mfd,
+				anatop_reg->control_reg,
+				anatop_reg->vol_bit_shift,
+				anatop_reg->vol_bit_width,
+				val);
+		return 0;
+	} else {
+		return -ENOTSUPP;
+	}
+}
+
+static int anatop_get_voltage_sel(struct regulator_dev *reg)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int selector;
+
+	if (anatop_reg->control_reg) {
+		u32 val = anatop_get_bits(anatop_reg->mfd,
+					  anatop_reg->control_reg,
+					  anatop_reg->vol_bit_shift,
+					  anatop_reg->vol_bit_width);
+		selector = val - anatop_reg->min_bit_val;
+		return selector;
+	} else {
+		return -ENOTSUPP;
+	}
+}
+
+static int anatop_list_voltage(struct regulator_dev *reg, unsigned selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int uv;
+
+	uv = anatop_reg->min_voltage + selector * 25000;
+	dev_dbg(&reg->dev, "vddio = %d, selector = %u\n", uv, selector);
+
+	return uv;
+}
+
+static struct regulator_ops anatop_rops = {
+	.set_voltage     = anatop_set_voltage,
+	.get_voltage_sel = anatop_get_voltage_sel,
+	.list_voltage    = anatop_list_voltage,
+};
+
+static int __devinit anatop_regulator_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct regulator_desc *rdesc;
+	struct regulator_dev *rdev;
+	struct anatop_regulator *sreg;
+	struct regulator_init_data *initdata;
+	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
+	int ret = 0;
+
+	initdata = of_get_regulator_init_data(dev, np);
+	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
+	if (!sreg)
+		return -ENOMEM;
+	sreg->initdata = initdata;
+	sreg->name = kstrdup(of_get_property(np, "regulator-name", NULL),
+			     GFP_KERNEL);
+	rdesc = &sreg->rdesc;
+	memset(rdesc, 0, sizeof(*rdesc));
+	rdesc->name = sreg->name;
+	rdesc->ops = &anatop_rops;
+	rdesc->type = REGULATOR_VOLTAGE;
+	rdesc->owner = THIS_MODULE;
+	sreg->mfd = anatopmfd;
+	if (of_property_read_u32(np, "reg", &sreg->control_reg)) {
+		dev_err(&pdev->dev, "no reg property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "anatop-vol-bit-width",
+				 &sreg->vol_bit_width)) {
+		dev_err(&pdev->dev, "no anatop-vol-bit-width property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "anatop-vol-bit-shift",
+				 &sreg->vol_bit_shift)) {
+		dev_err(&pdev->dev, "no anatop-vol-bit-shift property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "anatop-min-bit-val",
+				 &sreg->min_bit_val)) {
+		dev_err(&pdev->dev, "no anatop-min-bit-val property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "anatop-min-voltage",
+				 &sreg->min_voltage)) {
+		dev_err(&pdev->dev, "no anatop-min-voltage property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+	if (of_property_read_u32(np, "anatop-max-voltage",
+				 &sreg->max_voltage)) {
+		dev_err(&pdev->dev, "no anatop-max-voltage property set\n");
+		ret = -ENODEV;
+		goto anatop_probe_end;
+	}
+
+	/* register regulator */
+	rdev = regulator_register(rdesc, &pdev->dev,
+				  initdata, sreg, pdev->dev.of_node);
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "failed to register %s\n",
+			rdesc->name);
+		ret = PTR_ERR(rdev);
+		goto anatop_probe_end;
+	}
+
+	platform_set_drvdata(pdev, rdev);
+
+anatop_probe_end:
+	if (ret != 0 && sreg->name)
+		kfree(sreg->name);
+	return ret;
+}
+
+static int __devexit anatop_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
+	kfree(sreg->name);
+	regulator_unregister(rdev);
+	return 0;
+}
+
+static struct of_device_id __devinitdata of_anatop_regulator_match_tbl[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ /* end */ }
+};
+
+static struct platform_driver anatop_regulator = {
+	.driver = {
+		.name	= "anatop_regulator",
+		.owner  = THIS_MODULE,
+		.of_match_table = of_anatop_regulator_match_tbl,
+	},
+	.probe	= anatop_regulator_probe,
+	.remove	= anatop_regulator_remove,
+};
+
+static int __init anatop_regulator_init(void)
+{
+	return platform_driver_register(&anatop_regulator);
+}
+postcore_initcall(anatop_regulator_init);
+
+static void __exit anatop_regulator_exit(void)
+{
+	platform_driver_unregister(&anatop_regulator);
+}
+module_exit(anatop_regulator_exit);
+
+MODULE_AUTHOR("Nancy Chen <Nancy.Chen at freescale.com>, "
+	      "Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP Regulator driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.1



From Richard.Earnshaw at arm.com  Thu Mar  8 04:58:23 2012
From: Richard.Earnshaw at arm.com (Richard Earnshaw)
Date: Thu, 8 Mar 2012 09:58:23 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <alpine.LFD.2.02.1203021528150.31242@xanadu.home>
References: <alpine.DEB.2.00.1202231714590.23091@kaball-desktop>
 <1330019314-20865-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <alpine.LFD.2.02.1203021528150.31242@xanadu.home>
Message-ID: <4F5882BF.1030104@arm.com>

On 02/03/12 21:15, Nicolas Pitre wrote:
> [ coming back from vacation and trying to catch up ]
>
> On Wed, 29 Feb 2012, Dave Martin wrote:
>
>> Just had a chat with some tools guys -- apparently, when passing register
>> arguments to gcc inline asms there really isn't a guarantee that those
>> variables will be in the expected registers on entry to the inline asm.
>>
>> If gcc reorders other function calls or other code around the inline asm
>> (which it can do, except under certain controlled situations), then
>> intervening code can clobber any registers in general.
>
> I'm hearing this argument about once every year or so for the last 8
> years.  I think that the tools people are getting confused between
> themselves as you may get a different interpretation of what gcc should
> do depending to whom you happen to talk to.
>
> I did submit a bug to gcc in 2004 about this:
>
>       http://gcc.gnu.org/bugzilla/show_bug.cgi?id=15089
>
> You can see the confusion among gcc developers lurking there.
>
> So let's quote the relevant gcc documentation:
>
> -> * C Extensions::    GNU extensions to the C language family.
>    -> * Explicit Reg Vars::   Defining variables residing in specified registers.
>
> |GNU C allows you to put a few global variables into specified hardware
> |registers.  You can also specify the register in which an ordinary
> |register variable should be allocated.
> |
> |   * Global register variables reserve registers throughout the program.
> |     This may be useful in programs such as programming language
> |     interpreters which have a couple of global variables that are
> |     accessed very often.
> |
> |   * Local register variables in specific registers do not reserve the
> |     registers, except at the point where they are used as input or
> |     output operands in an `asm' statement and the `asm' statement
> |     itself is not deleted.  The compiler's data flow analysis is
> |     capable of determining where the specified registers contain live
> |     values, and where they are available for other uses.  Stores into
> |     local register variables may be deleted when they appear to be
> |     dead according to dataflow analysis.  References to local register
> |     variables may be deleted or moved or simplified.
> |
> |     These local variables are sometimes convenient for use with the
> |     extended `asm' feature (*note Extended Asm::), if you want to
> |     write one output of the assembler instruction directly into a
> |     particular register.  (This will work provided the register you
> |     specify fits the constraints specified for that operand in the
> |     `asm'.)
>
>       -> * Local Reg Vars::
>
> [...]
>
> | Defining such a register variable does not reserve the register; it
> |remains available for other uses in places where flow control
> |determines the variable's value is not live.
> |
> | This option does not guarantee that GCC will generate code that has
> |this variable in the register you specify at all times.  You may not
> |code an explicit reference to this register in the _assembler
> |instruction template_ part of an `asm' statement and assume it will
> |always refer to this variable.  However, using the variable as an `asm'
> |_operand_ guarantees that the specified register is used for the
> |operand.
>
> So, to me, the gcc documentation is perfectly clear on this topic.
> there really _is_ a guarantee that those asm marked variables will be in
> the expected registers on entry to the inline asm, given that the
> variable is _also_ listed as an operand to the asm statement.  But only
> in that case.
>
> It is true that gcc may reorder other function calls or other code
> around the inline asm and then intervening code can clobber any
> registers.  Then it is up to gcc to preserve the variable's content
> elsewhere when its register is used for other purposes, and restore it
> when some inline asm statement is referring to it.
>
> And if gcc does not do this then it is buggy.  Version 3.4.0 of gcc was
> buggy.  No other gcc versions in the last 7 years had such a problem or
> the __asmeq macro in the kernel would have told us.
>
>> Or, to summarise another way, there is no way to control which register
>> is used to pass something to an inline asm in general (often we get away
>> with this, and there are a lot of inline asms in the kernel that assume
>> it works, but the more you inline the more likely you are to get nasty
>> surprises).
>
> This statement is therefore unfounded and wrong.  Please direct the
> tools guy who mislead you to the above gcc documentation.
>

The problem is not really about re-ordering functions but about implicit
functions that come from the source code; for example

int foo (int a, int b)
{
  register int x __asm__("r0") = 33;

  register int c __asm__("r1") = a / b; /* Ooops, clobbers r0 with
division function call.  */

  asm ("svc 0" : : "r" (x));
}

There's nothing in the specification to say what happens if there's a
statement in the code that causes an implicit clobber of your assembly
register.

The best you can do here is to never initialize asm regs until you are
about to use them, but even that won't help if your register
initialization code needs the help of a function call.

Other common ways of exposing this weakness in the spec are TLS
variables and structure copies...

R.

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.



From k.lewandowsk at samsung.com  Thu Mar  8 05:52:00 2012
From: k.lewandowsk at samsung.com (Karol Lewandowski)
Date: Thu, 08 Mar 2012 11:52:00 +0100
Subject: [PATCH 1/5 v3] i2c/gpio: add DT support
In-Reply-To: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <4F588F50.7060906@samsung.com>

On 08.03.2012 09:50, Jean-Christophe PLAGNIOL-VILLARD wrote:

> +static int __devinit of_i2c_gpio_probe(struct device_node *np,
> +			     struct i2c_gpio_platform_data *pdata)
> +{
> +	u32 reg;
> +
> +	if (of_gpio_count(np) < 2)
> +		return -ENODEV;
> +
> +	pdata->sda_pin = of_get_gpio(np, 0);
> +	pdata->scl_pin = of_get_gpio(np, 1);
> +
> +	if (pdata->sda_pin < 0 || pdata->scl_pin < 0) {
> +		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
> +		       np->full_name, pdata->sda_pin, pdata->scl_pin);
> +		return -ENODEV;
> +	}
> +
> +	of_property_read_u32(np, "i2c-gpio,delay-us", &pdata->udelay);
> +



> +	if (of_property_read_u32(np, "i2c-gpio,timeout-ms", &reg))
> +		pdata->timeout = msecs_to_jiffies(reg);


I've already said (two times!) that of_property_read_u32() returns
nonzero (negative) error code on _error_.

Don't you see obvious error in above code fragment?

You assign to pdata->timeout on _error_.



From catalin.marinas at arm.com  Thu Mar  8 05:52:46 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 8 Mar 2012 10:52:46 +0000
Subject: [PATCH v2 4/5] Cortex-M3: Add base support for Cortex-M3
In-Reply-To: <1330967042-25612-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <CAHkRjk70x+Fn+Z4iUxSMc7Zq2cKBo_ka0tNhV0i5JWmEixpRrA@mail.gmail.com>
 <1330967042-25612-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120308105246.GC26727@arm.com>

Hi Uwe,

On Mon, Mar 05, 2012 at 05:04:01PM +0000, Uwe Kleine-K?nig wrote:
> --- a/arch/arm/include/asm/processor.h
> +++ b/arch/arm/include/asm/processor.h
> @@ -49,7 +49,15 @@ struct thread_struct {
>  #ifdef CONFIG_MMU
>  #define nommu_start_thread(regs) do { } while (0)
>  #else
> +#ifndef CONFIG_CPU_V7M
>  #define nommu_start_thread(regs) regs->ARM_r10 = current->mm->start_data
> +#else
> +#define nommu_start_thread(regs) do {                                  \
> +       regs->ARM_r10 = current->mm->start_data;                        \
> +       regs->ARM_sp -= 32;             /* exception return state */    \
> +       regs->ARM_EXCRET = 0xfffffffdL;                                 \
> +} while (0)
...
> --- a/arch/arm/include/asm/ptrace.h
> +++ b/arch/arm/include/asm/ptrace.h
> @@ -39,16 +39,25 @@
> @@ -127,7 +136,11 @@ struct pt_regs {
>  #define ARM_r2         uregs[2]
>  #define ARM_r1         uregs[1]
>  #define ARM_r0         uregs[0]
> +#if defined CONFIG_CPU_V7M
> +#define ARM_EXCRET     uregs[17]
> +#else
>  #define ARM_ORIG_r0    uregs[17]
> +#endif

Could we save the exception return somewhere in thread_info and preserve
ORIG_r0?

Alternatively, with some care, we could extend the kernel pt_regs
definition with two more registers and use one of them for exception
return. The user variant would remain the same as it's used by ptrace.

-- 
Catalin


From paul at pwsan.com  Thu Mar  8 05:51:23 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:23 -0700
Subject: [PATCH 00/15] ARM: OMAP4: hwmod data: add almost all remaining IP
 blocks
Message-ID: <20120308104918.14753.69281.stgit@dusk>

Hi

This series adds basic hwmods for all but one of the remaining
OMAP4 IP blocks that can be meaningfully controlled by the
kernel.  (The remaining IP block is the USIM - there's a clocking
problem that requires further investigation to resolve.)

There are a few new boot-time warnings added by this series:

[    0.280548] omap_hwmod: trace_clk_div_ck: missing clockdomain for trace_clk_div_ck.
[    0.302429] omap_hwmod: ddrphy_ck: missing clockdomain for ddrphy_ck.
[    0.319519] omap_hwmod: sl2if: cannot be enabled for reset (3)

These messages will be resolved by subsequent patches, and, while annoying,
should not affect the operation of the system.

These patches have been boot-tested and suspend-tested on a
OMAP44xx PandaBoard.

The series is intended to apply on the
'hwmod_remove_link_arrays_cleanup_3.4' branch, posted previously.

These patches are also available via git from git://git.pwsan.com/linux-2.6
in the branch "hwmod_enable_remaining_hwmods_devel_3.4".


- Paul

---

hwmod_enable_remaining_hwmods_devel_3.4
   text	   data	    bss	    dec	    hex	filename
6590067	 677452	5593500	12861019	 c43e5b	vmlinux.omap2plus_defconfig.orig
6594227	 684620	5593500	12872347	 c46a9b	vmlinux.omap2plus_defconfig

Beno?t Cousson (6):
      ARM: OMAP4: hwmod data: add GPMC
      ARM: OMAP4: hwmod data: add the Slimbus IP blocks
      ARM: OMAP4: hwmod data: add McASP
      ARM: OMAP4: hwmod data: add remaining USB-related IP blocks
      ARM: OMAP4: hwmod data: add the OCP-WP IP block
      ARM: OMAP4: hwmod data: add DEBUGSS skeleton

Ming Lei (1):
      ARM: OMAP4: hwmod data: introduce fdif(face detect module) hwmod

Paul Walmsley (8):
      ARM: OMAP2+: clockdomains: make {prm,cm}_clkdm common
      ARM: OMAP4: hwmod data: add HDQ/1-wire
      ARM: OMAP4: hwmod data: add EMIF1 and 2
      ARM: OMAP4: hwmod data: add GPU
      ARM: OMAP4: hwmod data: add some interconnect-related IP blocks
      ARM: OMAP4: hwmod data: add OCM RAM IP block
      ARM: OMAP4: hwmod data: add System Control Module
      ARM: OMAP4: hwmod data: add PRCM and related IP blocks


 arch/arm/mach-omap2/Makefile                     |    8 
 arch/arm/mach-omap2/clockdomain44xx.c            |    6 
 arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |   10 
 arch/arm/mach-omap2/clockdomains44xx_data.c      |    2 
 arch/arm/mach-omap2/clockdomains_common_data.c   |   24 
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c       | 1473 +++++++++++++++++++++-
 arch/arm/plat-omap/include/plat/omap_hwmod.h     |    1 
 7 files changed, 1443 insertions(+), 81 deletions(-)
 create mode 100644 arch/arm/mach-omap2/clockdomains_common_data.c




From paul at pwsan.com  Thu Mar  8 05:51:29 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:29 -0700
Subject: [PATCH 03/15] ARM: OMAP4: hwmod data: add HDQ/1-wire
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105127.14753.19376.stgit@dusk>

Add the HDQ/1-wire hwmod and associated interconnect data.  The
HDQ/1-wire IP block is a low-speed serial interconnect.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   61 ++++++++++++++++++++++++++++
 1 files changed, 60 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7f42431..ae87401 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -264,7 +264,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  emif2
  *  gpmc
  *  gpu
- *  hdq1w
  *  mcasp
  *  mpu_c0
  *  mpu_c1
@@ -1057,6 +1056,47 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
 };
 
 /*
+ * 'hdq1w' class
+ * hdq / 1-wire serial interface controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0014,
+	.syss_offs	= 0x0018,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
+			   SYSS_HAS_RESET_STATUS),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
+	.name	= "hdq1w",
+	.sysc	= &omap44xx_hdq1w_sysc,
+};
+
+/* hdq1w */
+static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
+	{ .irq = 58 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_hdq1w_hwmod = {
+	.name		= "hdq1w",
+	.class		= &omap44xx_hdq1w_hwmod_class,
+	.clkdm_name	= "l4_per_clkdm",
+	.flags		= HWMOD_INIT_NO_RESET, /* XXX temporary */
+	.mpu_irqs	= omap44xx_hdq1w_irqs,
+	.main_clk	= "hdq1w_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
  * 'hsi' class
  * mipi high-speed synchronous serial interface (multichannel and full-duplex
  * serial if)
@@ -3672,6 +3712,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
+	{
+		.pa_start	= 0x480b2000,
+		.pa_end		= 0x480b201f,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_per -> hdq1w */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_hdq1w_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_hdq1w_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
 	{
 		.pa_start	= 0x4a058000,
@@ -4770,6 +4828,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__gpio4,
 	&omap44xx_l4_per__gpio5,
 	&omap44xx_l4_per__gpio6,
+	&omap44xx_l4_per__hdq1w,
 	&omap44xx_l4_cfg__hsi,
 	&omap44xx_l4_per__i2c1,
 	&omap44xx_l4_per__i2c2,




From paul at pwsan.com  Thu Mar  8 05:51:29 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:29 -0700
Subject: [PATCH 04/15] ARM: OMAP4: hwmod data: add GPMC
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105129.14753.577.stgit@dusk>

From: Beno?t Cousson <b-cousson at ti.com>

Add the GPMC hwmod and associated interconnect data.   The GPMC is a
programmable parallel-bus memory controller.

Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   67 ++++++++++++++++++++++++++++
 1 files changed, 66 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ae87401..6a7e26e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -262,7 +262,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  elm
  *  emif1
  *  emif2
- *  gpmc
  *  gpu
  *  mcasp
  *  mpu_c0
@@ -1056,6 +1055,53 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
 };
 
 /*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0014,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
+	.name	= "gpmc",
+	.sysc	= &omap44xx_gpmc_sysc,
+};
+
+/* gpmc */
+static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
+	{ .irq = 20 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
+	{ .dma_req = 3 + OMAP44XX_DMA_REQ_START },
+	{ .dma_req = -1 }
+};
+
+static struct omap_hwmod omap44xx_gpmc_hwmod = {
+	.name		= "gpmc",
+	.class		= &omap44xx_gpmc_hwmod_class,
+	.clkdm_name	= "l3_2_clkdm",
+	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+	.mpu_irqs	= omap44xx_gpmc_irqs,
+	.sdma_reqs	= omap44xx_gpmc_sdma_reqs,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/*
  * 'hdq1w' class
  * hdq / 1-wire serial interface controller
  */
@@ -3712,6 +3758,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
+	{
+		.pa_start	= 0x50000000,
+		.pa_end		= 0x500003ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l3_main_2 -> gpmc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
+	.master		= &omap44xx_l3_main_2_hwmod,
+	.slave		= &omap44xx_gpmc_hwmod,
+	.clk		= "l3_div_ck",
+	.addr		= omap44xx_gpmc_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
 	{
 		.pa_start	= 0x480b2000,
@@ -4828,6 +4892,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__gpio4,
 	&omap44xx_l4_per__gpio5,
 	&omap44xx_l4_per__gpio6,
+	&omap44xx_l3_main_2__gpmc,
 	&omap44xx_l4_per__hdq1w,
 	&omap44xx_l4_cfg__hsi,
 	&omap44xx_l4_per__i2c1,




From paul at pwsan.com  Thu Mar  8 05:51:25 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:25 -0700
Subject: [PATCH 01/15] ARM: OMAP2+: clockdomains: make {prm,cm}_clkdm common
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105123.14753.65790.stgit@dusk>

The PRM and CM implicit clockdomains will soon be used by OMAP44xx.
So, make them common to OMAP2+ and modify the OMAP4 clockdomains code
so use of these clockdomains doesn't crash the system.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/Makefile                     |    8 +++++--
 arch/arm/mach-omap2/clockdomain44xx.c            |    6 ++++++
 arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |   10 ---------
 arch/arm/mach-omap2/clockdomains44xx_data.c      |    2 ++
 arch/arm/mach-omap2/clockdomains_common_data.c   |   24 ++++++++++++++++++++++
 5 files changed, 37 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mach-omap2/clockdomains_common_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index bd76394..9b2f406 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -117,16 +117,18 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common) \
 					   powerdomains44xx_data.o
 
 # PRCM clockdomain control
-obj-$(CONFIG_ARCH_OMAP2)		+= clockdomain.o \
+clockdomain-common			+= clockdomain.o \
+					   clockdomains_common_data.o
+obj-$(CONFIG_ARCH_OMAP2)		+= $(clockdomain-common) \
 					   clockdomain2xxx_3xxx.o \
 					   clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_SOC_OMAP2420)		+= clockdomains2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)		+= clockdomains2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)		+= clockdomain.o \
+obj-$(CONFIG_ARCH_OMAP3)		+= $(clockdomain-common) \
 					   clockdomain2xxx_3xxx.o \
 					   clockdomains2xxx_3xxx_data.o \
 					   clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)		+= clockdomain.o \
+obj-$(CONFIG_ARCH_OMAP4)		+= $(clockdomain-common) \
 					   clockdomain44xx.o \
 					   clockdomains44xx_data.o
 
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 935c7f0..4f04dd1 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -51,6 +51,9 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
 	struct clkdm_dep *cd;
 	u32 mask = 0;
 
+	if (!clkdm->prcm_partition)
+		return 0;
+
 	for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
 		if (!cd->clkdm)
 			continue; /* only happens if data is erroneous */
@@ -103,6 +106,9 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
 {
 	bool hwsup = false;
 
+	if (!clkdm->prcm_partition)
+		return 0;
+
 	hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
 					clkdm->cm_inst, clkdm->clkdm_offs);
 
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 0a6a048..839145e 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -89,13 +89,3 @@ struct clockdomain wkup_common_clkdm = {
 	.pwrdm		= { .name = "wkup_pwrdm" },
 	.dep_bit	= OMAP_EN_WKUP_SHIFT,
 };
-
-struct clockdomain prm_common_clkdm = {
-	.name		= "prm_clkdm",
-	.pwrdm		= { .name = "wkup_pwrdm" },
-};
-
-struct clockdomain cm_common_clkdm = {
-	.name		= "cm_clkdm",
-	.pwrdm		= { .name = "core_pwrdm" },
-};
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 9299ac2..dc42cd6 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -430,6 +430,8 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
 	&l4_wkup_44xx_clkdm,
 	&emu_sys_44xx_clkdm,
 	&l3_dma_44xx_clkdm,
+	&prm_common_clkdm,
+	&cm_common_clkdm,
 	NULL
 };
 
diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c
new file mode 100644
index 0000000..615b1f0
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains_common_data.c
@@ -0,0 +1,24 @@
+/*
+ * OMAP2+-common clockdomain data
+ *
+ * Copyright (C) 2008-2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni H?gander
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+
+/* These are implicit clockdomains - they are never defined as such in TRM */
+struct clockdomain prm_common_clkdm = {
+	.name		= "prm_clkdm",
+	.pwrdm		= { .name = "wkup_pwrdm" },
+};
+
+struct clockdomain cm_common_clkdm = {
+	.name		= "cm_clkdm",
+	.pwrdm		= { .name = "core_pwrdm" },
+};




From paul at pwsan.com  Thu Mar  8 05:51:31 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:31 -0700
Subject: [PATCH 06/15] ARM: OMAP4: hwmod data: add GPU
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105130.14753.7993.stgit@dusk>

Add the GPU hwmod and associated interconnect data.  The GPU is a
graphics accelerator.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   70 ++++++++++++++++++++++++++++
 1 files changed, 69 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 812c990..adacc09 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -260,7 +260,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  efuse_ctrl_cust
  *  efuse_ctrl_std
  *  elm
- *  gpu
  *  mcasp
  *  mpu_c0
  *  mpu_c1
@@ -1158,6 +1157,47 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
 };
 
 /*
+ * 'gpu' class
+ * 2d/3d graphics accelerator
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
+	.rev_offs	= 0x1fc00,
+	.sysc_offs	= 0x1fc10,
+	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
+	.name	= "gpu",
+	.sysc	= &omap44xx_gpu_sysc,
+};
+
+/* gpu */
+static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
+	{ .irq = 21 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_gpu_hwmod = {
+	.name		= "gpu",
+	.class		= &omap44xx_gpu_hwmod_class,
+	.clkdm_name	= "l3_gfx_clkdm",
+	.mpu_irqs	= omap44xx_gpu_irqs,
+	.main_clk	= "gpu_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
  * 'hdq1w' class
  * hdq / 1-wire serial interface controller
  */
@@ -3138,6 +3178,14 @@ static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* gpu -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
+	.master		= &omap44xx_gpu_hwmod,
+	.slave		= &omap44xx_l3_main_2_hwmod,
+	.clk		= "l3_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* hsi -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 	.master		= &omap44xx_hsi_hwmod,
@@ -3868,6 +3916,24 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
+	{
+		.pa_start	= 0x56000000,
+		.pa_end		= 0x5600ffff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l3_main_2 -> gpu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
+	.master		= &omap44xx_l3_main_2_hwmod,
+	.slave		= &omap44xx_gpu_hwmod,
+	.clk		= "l3_div_ck",
+	.addr		= omap44xx_gpu_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
 	{
 		.pa_start	= 0x480b2000,
@@ -4936,6 +5002,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_mpu__l3_main_1,
 	&omap44xx_dma_system__l3_main_2,
 	&omap44xx_fdif__l3_main_2,
+	&omap44xx_gpu__l3_main_2,
 	&omap44xx_hsi__l3_main_2,
 	&omap44xx_ipu__l3_main_2,
 	&omap44xx_iss__l3_main_2,
@@ -4987,6 +5054,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__gpio5,
 	&omap44xx_l4_per__gpio6,
 	&omap44xx_l3_main_2__gpmc,
+	&omap44xx_l3_main_2__gpu,
 	&omap44xx_l4_per__hdq1w,
 	&omap44xx_l4_cfg__hsi,
 	&omap44xx_l4_per__i2c1,




From paul at pwsan.com  Thu Mar  8 05:51:30 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:30 -0700
Subject: [PATCH 05/15] ARM: OMAP4: hwmod data: add EMIF1 and 2
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105129.14753.7319.stgit@dusk>

Add the EMIF1 and 2 hwmods and associated interconnect data.  The EMIFs
are SDRAM interface IP blocks.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   98 +++++++++++++++++++++++++++-
 1 files changed, 96 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 6a7e26e..812c990 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -260,8 +260,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  efuse_ctrl_cust
  *  efuse_ctrl_std
  *  elm
- *  emif1
- *  emif2
  *  gpu
  *  mcasp
  *  mpu_c0
@@ -812,6 +810,64 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 };
 
 /*
+ * 'emif' class
+ * external memory interface no1
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
+	.rev_offs	= 0x0000,
+};
+
+static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
+	.name	= "emif",
+	.sysc	= &omap44xx_emif_sysc,
+};
+
+/* emif1 */
+static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
+	{ .irq = 110 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_emif1_hwmod = {
+	.name		= "emif1",
+	.class		= &omap44xx_emif_hwmod_class,
+	.clkdm_name	= "l3_emif_clkdm",
+	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+	.mpu_irqs	= omap44xx_emif1_irqs,
+	.main_clk	= "ddrphy_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/* emif2 */
+static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
+	{ .irq = 111 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_emif2_hwmod = {
+	.name		= "emif2",
+	.class		= &omap44xx_emif_hwmod_class,
+	.clkdm_name	= "l3_emif_clkdm",
+	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+	.mpu_irqs	= omap44xx_emif2_irqs,
+	.main_clk	= "ddrphy_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/*
  * 'fdif' class
  * face detection hw accelerator module
  */
@@ -3632,6 +3688,42 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
 	.user		= OCP_USER_MPU,
 };
 
+static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
+	{
+		.pa_start	= 0x4c000000,
+		.pa_end		= 0x4c0000ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* emif_fw -> emif1 */
+static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
+	.master		= &omap44xx_emif_fw_hwmod,
+	.slave		= &omap44xx_emif1_hwmod,
+	.clk		= "l3_div_ck",
+	.addr		= omap44xx_emif1_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
+	{
+		.pa_start	= 0x4d000000,
+		.pa_end		= 0x4d0000ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* emif_fw -> emif2 */
+static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
+	.master		= &omap44xx_emif_fw_hwmod,
+	.slave		= &omap44xx_emif2_hwmod,
+	.clk		= "l3_div_ck",
+	.addr		= omap44xx_emif2_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
 	{
 		.pa_start	= 0x4a10a000,
@@ -4885,6 +4977,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__dss_rfbi,
 	&omap44xx_l3_main_2__dss_venc,
 	&omap44xx_l4_per__dss_venc,
+	&omap44xx_emif_fw__emif1,
+	&omap44xx_emif_fw__emif2,
 	&omap44xx_l4_cfg__fdif,
 	&omap44xx_l4_wkup__gpio1,
 	&omap44xx_l4_per__gpio2,




From paul at pwsan.com  Thu Mar  8 05:51:27 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:27 -0700
Subject: [PATCH 02/15] ARM: OMAP4: hwmod data: introduce fdif(face detect
 module) hwmod
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105125.14753.82086.stgit@dusk>

From: Ming Lei <ming.lei at canonical.com>

Add hwmod data for the OMAP4 FDIF IP block.

Signed-off-by: Ming Lei <ming.lei at canonical.com>
Acked-by: Beno?t Cousson <b-cousson at ti.com>
[paul at pwsan.com: rearranged to match script output; fixed FDIF end address to
 match script data; wrote trivial changelog]
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   70 ++++++++++++++++++++++++++++
 1 files changed, 69 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 9180714..7f42431 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -262,7 +262,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  elm
  *  emif1
  *  emif2
- *  fdif
  *  gpmc
  *  gpu
  *  hdq1w
@@ -815,6 +814,47 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 };
 
 /*
+ * 'fdif' class
+ * face detection hw accelerator module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
+	.name	= "fdif",
+	.sysc	= &omap44xx_fdif_sysc,
+};
+
+/* fdif */
+static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
+	{ .irq = 69 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_fdif_hwmod = {
+	.name		= "fdif",
+	.class		= &omap44xx_fdif_hwmod_class,
+	.clkdm_name	= "iss_clkdm",
+	.mpu_irqs	= omap44xx_fdif_irqs,
+	.main_clk	= "fdif_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
  * 'gpio' class
  * general purpose io module
  */
@@ -2948,6 +2988,14 @@ static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* fdif -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
+	.master		= &omap44xx_fdif_hwmod,
+	.slave		= &omap44xx_l3_main_2_hwmod,
+	.clk		= "l3_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* hsi -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 	.master		= &omap44xx_hsi_hwmod,
@@ -3498,6 +3546,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
 	.user		= OCP_USER_MPU,
 };
 
+static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
+	{
+		.pa_start	= 0x4a10a000,
+		.pa_end		= 0x4a10a1ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_cfg -> fdif */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_fdif_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_fdif_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
 	{
 		.pa_start	= 0x4a310000,
@@ -4655,6 +4721,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_mmc2__l3_main_1,
 	&omap44xx_mpu__l3_main_1,
 	&omap44xx_dma_system__l3_main_2,
+	&omap44xx_fdif__l3_main_2,
 	&omap44xx_hsi__l3_main_2,
 	&omap44xx_ipu__l3_main_2,
 	&omap44xx_iss__l3_main_2,
@@ -4696,6 +4763,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__dss_rfbi,
 	&omap44xx_l3_main_2__dss_venc,
 	&omap44xx_l4_per__dss_venc,
+	&omap44xx_l4_cfg__fdif,
 	&omap44xx_l4_wkup__gpio1,
 	&omap44xx_l4_per__gpio2,
 	&omap44xx_l4_per__gpio3,




From paul at pwsan.com  Thu Mar  8 05:51:33 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:33 -0700
Subject: [PATCH 08/15] ARM: OMAP4: hwmod data: add McASP
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105132.14753.91529.stgit@dusk>

From: Beno?t Cousson <b-cousson at ti.com>

Add the McASP hwmod and associated interconnect data.  The McASP is a
general-purpose audio serial port.

Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   91 ++++++++++++++++++++++++++++
 1 files changed, 90 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 283c5b2..3be64f5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -260,7 +260,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  efuse_ctrl_cust
  *  efuse_ctrl_std
  *  elm
- *  mcasp
  *  mpu_c0
  *  mpu_c1
  *  ocmc_ram
@@ -1669,6 +1668,58 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
 };
 
 /*
+ * 'mcasp' class
+ * multi-channel audio serial port controller
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
+	.sidle_shift	= 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
+	.sysc_offs	= 0x0004,
+	.sysc_flags	= SYSC_HAS_SIDLEMODE,
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type_mcasp,
+};
+
+static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
+	.name	= "mcasp",
+	.sysc	= &omap44xx_mcasp_sysc,
+};
+
+/* mcasp */
+static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
+	{ .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
+	{ .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
+	{ .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
+	{ .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
+	{ .dma_req = -1 }
+};
+
+static struct omap_hwmod omap44xx_mcasp_hwmod = {
+	.name		= "mcasp",
+	.class		= &omap44xx_mcasp_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	.mpu_irqs	= omap44xx_mcasp_irqs,
+	.sdma_reqs	= omap44xx_mcasp_sdma_reqs,
+	.main_clk	= "mcasp_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
  * 'mcbsp' class
  * multi channel buffered serial port controller
  */
@@ -4224,6 +4275,42 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
+	{
+		.pa_start	= 0x40128000,
+		.pa_end		= 0x401283ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_abe -> mcasp */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
+	.master		= &omap44xx_l4_abe_hwmod,
+	.slave		= &omap44xx_mcasp_hwmod,
+	.clk		= "ocp_abe_iclk",
+	.addr		= omap44xx_mcasp_addrs,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
+	{
+		.pa_start	= 0x49028000,
+		.pa_end		= 0x490283ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_abe -> mcasp (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
+	.master		= &omap44xx_l4_abe_hwmod,
+	.slave		= &omap44xx_mcasp_hwmod,
+	.clk		= "ocp_abe_iclk",
+	.addr		= omap44xx_mcasp_dma_addrs,
+	.user		= OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
 	{
 		.name		= "mpu",
@@ -5222,6 +5309,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l3_main_2__iva,
 	&omap44xx_l4_wkup__kbd,
 	&omap44xx_l4_cfg__mailbox,
+	&omap44xx_l4_abe__mcasp,
+	&omap44xx_l4_abe__mcasp_dma,
 	&omap44xx_l4_abe__mcbsp1,
 	&omap44xx_l4_abe__mcbsp1_dma,
 	&omap44xx_l4_abe__mcbsp2,




From paul at pwsan.com  Thu Mar  8 05:51:35 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:35 -0700
Subject: [PATCH 11/15] ARM: OMAP4: hwmod data: add OCM RAM IP block
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105134.14753.63101.stgit@dusk>

Add the OCM RAM IP block and interconnect data.  This is an oh-chip
block of SRAM connected directly to the L3 bus.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   32 +++++++++++++++++++++++++++-
 1 files changed, 31 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 968feb0..f48fe77 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -280,7 +280,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  efuse_ctrl_std
  *  mpu_c0
  *  mpu_c1
- *  ocmc_ram
  *  ocp_wp_noc
  *  prcm_mpu
  *  prm
@@ -2356,6 +2355,28 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
 };
 
 /*
+ * 'ocmc_ram' class
+ * top-level core on-chip ram
+ */
+
+static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
+	.name	= "ocmc_ram",
+};
+
+/* ocmc_ram */
+static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
+	.name		= "ocmc_ram",
+	.class		= &omap44xx_ocmc_ram_hwmod_class,
+	.clkdm_name	= "l3_2_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
  * 'ocp2scp' class
  * bridge to transform ocp interface protocol to scp (serial control port)
  * protocol
@@ -4923,6 +4944,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3_main_2 -> ocmc_ram */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
+	.master		= &omap44xx_l3_main_2_hwmod,
+	.slave		= &omap44xx_ocmc_ram_hwmod,
+	.clk		= "l3_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_cfg -> ocp2scp_usb_phy */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
 	.master		= &omap44xx_l4_cfg_hwmod,
@@ -5654,6 +5683,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__mmc3,
 	&omap44xx_l4_per__mmc4,
 	&omap44xx_l4_per__mmc5,
+	&omap44xx_l3_main_2__ocmc_ram,
 	&omap44xx_l4_cfg__ocp2scp_usb_phy,
 	&omap44xx_l3_main_2__sl2if,
 	&omap44xx_l4_abe__slimbus1,




From paul at pwsan.com  Thu Mar  8 05:51:32 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:32 -0700
Subject: [PATCH 07/15] ARM: OMAP4: hwmod data: add the Slimbus IP blocks
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105131.14753.60810.stgit@dusk>

From: Beno?t Cousson <b-cousson at ti.com>

Add the Slimbus hwmods and associated interconnect data.  The Slimbus
IP blocks implement a two-wire serial interface.

Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  163 ++++++++++++++++++++++++++++
 1 files changed, 161 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index adacc09..283c5b2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -270,8 +270,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  prm
  *  scrm
  *  sl2if
- *  slimbus1
- *  slimbus2
  *  usb_host_fs
  *  usb_host_hs
  *  usb_phy_cm
@@ -2219,6 +2217,110 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
 };
 
 /*
+ * 'slimbus' class
+ * bidirectional, multi-drop, multi-channel two-line serial interface between
+ * the device and external components
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
+	.name	= "slimbus",
+	.sysc	= &omap44xx_slimbus_sysc,
+};
+
+/* slimbus1 */
+static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
+	{ .irq = 97 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
+	{ .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
+	{ .role = "fclk_1", .clk = "slimbus1_fclk_1" },
+	{ .role = "fclk_0", .clk = "slimbus1_fclk_0" },
+	{ .role = "fclk_2", .clk = "slimbus1_fclk_2" },
+	{ .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
+};
+
+static struct omap_hwmod omap44xx_slimbus1_hwmod = {
+	.name		= "slimbus1",
+	.class		= &omap44xx_slimbus_hwmod_class,
+	.clkdm_name	= "abe_clkdm",
+	.mpu_irqs	= omap44xx_slimbus1_irqs,
+	.sdma_reqs	= omap44xx_slimbus1_sdma_reqs,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= slimbus1_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(slimbus1_opt_clks),
+};
+
+/* slimbus2 */
+static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
+	{ .irq = 98 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
+	{ .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
+	{ .role = "fclk_1", .clk = "slimbus2_fclk_1" },
+	{ .role = "fclk_0", .clk = "slimbus2_fclk_0" },
+	{ .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
+};
+
+static struct omap_hwmod omap44xx_slimbus2_hwmod = {
+	.name		= "slimbus2",
+	.class		= &omap44xx_slimbus_hwmod_class,
+	.clkdm_name	= "l4_per_clkdm",
+	.mpu_irqs	= omap44xx_slimbus2_irqs,
+	.sdma_reqs	= omap44xx_slimbus2_sdma_reqs,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.opt_clks	= slimbus2_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(slimbus2_opt_clks),
+};
+
+/*
  * 'smartreflex' class
  * smartreflex module (monitor silicon performance and outputs a measure of
  * performance error)
@@ -4452,6 +4554,60 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
+	{
+		.pa_start	= 0x4012c000,
+		.pa_end		= 0x4012c3ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_abe -> slimbus1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
+	.master		= &omap44xx_l4_abe_hwmod,
+	.slave		= &omap44xx_slimbus1_hwmod,
+	.clk		= "ocp_abe_iclk",
+	.addr		= omap44xx_slimbus1_addrs,
+	.user		= OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
+	{
+		.pa_start	= 0x4902c000,
+		.pa_end		= 0x4902c3ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_abe -> slimbus1 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
+	.master		= &omap44xx_l4_abe_hwmod,
+	.slave		= &omap44xx_slimbus1_hwmod,
+	.clk		= "ocp_abe_iclk",
+	.addr		= omap44xx_slimbus1_dma_addrs,
+	.user		= OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
+	{
+		.pa_start	= 0x48076000,
+		.pa_end		= 0x480763ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_per -> slimbus2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_slimbus2_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_slimbus2_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
 	{
 		.pa_start	= 0x4a0dd000,
@@ -5084,6 +5240,9 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__mmc3,
 	&omap44xx_l4_per__mmc4,
 	&omap44xx_l4_per__mmc5,
+	&omap44xx_l4_abe__slimbus1,
+	&omap44xx_l4_abe__slimbus1_dma,
+	&omap44xx_l4_per__slimbus2,
 	&omap44xx_l4_cfg__smartreflex_core,
 	&omap44xx_l4_cfg__smartreflex_iva,
 	&omap44xx_l4_cfg__smartreflex_mpu,




From paul at pwsan.com  Thu Mar  8 05:51:34 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:34 -0700
Subject: [PATCH 10/15] ARM: OMAP4: hwmod data: add remaining USB-related IP
 blocks
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105133.14753.73322.stgit@dusk>

From: Beno?t Cousson <b-cousson at ti.com>

Add the OCP2SCP IP block and interconnect data.  The OCP2SCP can be
used in conjunction with the on-chip embedded USB PHY, associated with
the OTG controller.

Add the on-chip full-speed USB host controller IP block and
interconnect data.

Cc: Felipe Balbi <balbi at ti.com>
Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  120 +++++++++++++++++++++++++++-
 1 files changed, 116 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 8d3a7c1..968feb0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -281,15 +281,11 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  mpu_c0
  *  mpu_c1
  *  ocmc_ram
- *  ocp2scp_usb_phy
  *  ocp_wp_noc
  *  prcm_mpu
  *  prm
  *  scrm
- *  usb_host_fs
- *  usb_host_hs
  *  usb_phy_cm
- *  usb_tll_hs
  *  usim
  */
 
@@ -2360,6 +2356,36 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
 };
 
 /*
+ * 'ocp2scp' class
+ * bridge to transform ocp interface protocol to scp (serial control port)
+ * protocol
+ */
+
+static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
+	.name	= "ocp2scp",
+};
+
+/* ocp2scp_usb_phy */
+static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
+	{ .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
+};
+
+static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
+	.name		= "ocp2scp_usb_phy",
+	.class		= &omap44xx_ocp2scp_hwmod_class,
+	.clkdm_name	= "l3_init_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+	.opt_clks	= ocp2scp_usb_phy_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
+};
+
+/*
  * 'sl2if' class
  * shared level 2 memory interface
  */
@@ -3042,6 +3068,55 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
 };
 
 /*
+ * 'usb_host_fs' class
+ * full-speed usb host controller
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
+	.midle_shift	= 4,
+	.sidle_shift	= 2,
+	.srst_shift	= 1,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0210,
+	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+			   SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type_usb_host_fs,
+};
+
+static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
+	.name	= "usb_host_fs",
+	.sysc	= &omap44xx_usb_host_fs_sysc,
+};
+
+/* usb_host_fs */
+static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
+	{ .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
+	{ .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
+	.name		= "usb_host_fs",
+	.class		= &omap44xx_usb_host_fs_hwmod_class,
+	.clkdm_name	= "l3_init_clkdm",
+	.mpu_irqs	= omap44xx_usb_host_fs_irqs,
+	.main_clk	= "usb_host_fs_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/*
  * 'usb_host_hs' class
  * high-speed multi-port usb host controller
  */
@@ -3554,6 +3629,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* usb_host_fs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
+	.master		= &omap44xx_usb_host_fs_hwmod,
+	.slave		= &omap44xx_l3_main_2_hwmod,
+	.clk		= "l3_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* usb_host_hs -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
 	.master		= &omap44xx_usb_host_hs_hwmod,
@@ -4840,6 +4923,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg -> ocp2scp_usb_phy */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_ocp2scp_usb_phy_hwmod,
+	.clk		= "l4_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l3_main_2 -> sl2if */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
 	.master		= &omap44xx_l3_main_2_hwmod,
@@ -5316,6 +5407,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
+	{
+		.pa_start	= 0x4a0a9000,
+		.pa_end		= 0x4a0a93ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_cfg -> usb_host_fs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_usb_host_fs_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_usb_host_fs_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
 	{
 		.name		= "uhh",
@@ -5463,6 +5572,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_iva__l3_main_2,
 	&omap44xx_l3_main_1__l3_main_2,
 	&omap44xx_l4_cfg__l3_main_2,
+	&omap44xx_usb_host_fs__l3_main_2,
 	&omap44xx_usb_host_hs__l3_main_2,
 	&omap44xx_usb_otg_hs__l3_main_2,
 	&omap44xx_l3_main_1__l3_main_3,
@@ -5544,6 +5654,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__mmc3,
 	&omap44xx_l4_per__mmc4,
 	&omap44xx_l4_per__mmc5,
+	&omap44xx_l4_cfg__ocp2scp_usb_phy,
 	&omap44xx_l3_main_2__sl2if,
 	&omap44xx_l4_abe__slimbus1,
 	&omap44xx_l4_abe__slimbus1_dma,
@@ -5571,6 +5682,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__uart2,
 	&omap44xx_l4_per__uart3,
 	&omap44xx_l4_per__uart4,
+	&omap44xx_l4_cfg__usb_host_fs,
 	&omap44xx_l4_cfg__usb_host_hs,
 	&omap44xx_l4_cfg__usb_otg_hs,
 	&omap44xx_l4_cfg__usb_tll_hs,




From paul at pwsan.com  Thu Mar  8 05:51:35 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:35 -0700
Subject: [PATCH 12/15] ARM: OMAP4: hwmod data: add the OCP-WP IP block
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105135.14753.5020.stgit@dusk>

From: Beno?t Cousson <b-cousson at ti.com>

Add the OCP-WP hwmod and associated interconnect data.  The OCP-WP,
or OCP watchpoint, can be used to collect interconnect data and
transmit it via the STM port.

Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   51 +++++++++++++++++++++++++++-
 1 files changed, 50 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index f48fe77..5c89307 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -262,6 +262,28 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 };
 
 /*
+ * 'ocp_wp_noc' class
+ * instance(s): ocp_wp_noc
+ */
+static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
+	.name	= "ocp_wp_noc",
+};
+
+/* ocp_wp_noc */
+static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
+	.name		= "ocp_wp_noc",
+	.class		= &omap44xx_ocp_wp_noc_hwmod_class,
+	.clkdm_name	= "l3_instr_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/*
  * Modules omap_hwmod structures
  *
  * The following IPs are excluded for the moment because:
@@ -280,7 +302,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  efuse_ctrl_std
  *  mpu_c0
  *  mpu_c1
- *  ocp_wp_noc
  *  prcm_mpu
  *  prm
  *  scrm
@@ -3494,6 +3515,14 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* ocp_wp_noc -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
+	.master		= &omap44xx_ocp_wp_noc_hwmod,
+	.slave		= &omap44xx_l3_instr_hwmod,
+	.clk		= "l3_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* dsp -> l3_main_1 */
 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 	.master		= &omap44xx_dsp_hwmod,
@@ -3772,6 +3801,24 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
+	{
+		.pa_start	= 0x4a102000,
+		.pa_end		= 0x4a10207f,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_cfg -> ocp_wp_noc */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_ocp_wp_noc_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_ocp_wp_noc_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 	{
 		.pa_start	= 0x401f1000,
@@ -5584,6 +5631,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_cfg__emif_fw,
 	&omap44xx_iva__l3_instr,
 	&omap44xx_l3_main_3__l3_instr,
+	&omap44xx_ocp_wp_noc__l3_instr,
 	&omap44xx_dsp__l3_main_1,
 	&omap44xx_dss__l3_main_1,
 	&omap44xx_l3_main_2__l3_main_1,
@@ -5615,6 +5663,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l3_main_2__l4_per,
 	&omap44xx_l4_cfg__l4_wkup,
 	&omap44xx_mpu__mpu_private,
+	&omap44xx_l4_cfg__ocp_wp_noc,
 	&omap44xx_l4_abe__aess,
 	&omap44xx_l4_abe__aess_dma,
 	&omap44xx_l3_main_2__c2c,




From paul at pwsan.com  Thu Mar  8 05:51:33 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:33 -0700
Subject: [PATCH 09/15] ARM: OMAP4: hwmod data: add some interconnect-related
 IP blocks
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105133.14753.52890.stgit@dusk>

Add the SL2 interface IP block and interconnect data.  The SL2 is related
to the IVA-HD subsystem.

Add IP block and interconnect data for the C2C ("Chip-to-chip")
interconnect.  This can provide a direct system interconnect link to
other devices stacked on the OMAP package.

Add the ELM IP block and interconnect data.  The ELM can be used
to locate errors in NAND flash connected to the GPMC.


Signed-off-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c   |  224 ++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    1 
 2 files changed, 221 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 3be64f5..8d3a7c1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -50,6 +50,27 @@
  */
 
 /*
+ * 'c2c_target_fw' class
+ * instance(s): c2c_target_fw
+ */
+static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
+	.name	= "c2c_target_fw",
+};
+
+/* c2c_target_fw */
+static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
+	.name		= "c2c_target_fw",
+	.class		= &omap44xx_c2c_target_fw_hwmod_class,
+	.clkdm_name	= "d2d_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
  * 'dmm' class
  * instance(s): dmm
  */
@@ -248,8 +269,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  * - They still need to be validated with the driver
  *   properly adapted to omap_hwmod / omap_device
  *
- *  c2c
- *  c2c_target_fw
  *  cm_core
  *  cm_core_aon
  *  ctrl_module_core
@@ -259,7 +278,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  debugss
  *  efuse_ctrl_cust
  *  efuse_ctrl_std
- *  elm
  *  mpu_c0
  *  mpu_c1
  *  ocmc_ram
@@ -268,7 +286,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  *  prcm_mpu
  *  prm
  *  scrm
- *  sl2if
  *  usb_host_fs
  *  usb_host_hs
  *  usb_phy_cm
@@ -331,6 +348,41 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
 };
 
 /*
+ * 'c2c' class
+ * chip 2 chip interface used to plug the ape soc (omap) with an external modem
+ * soc
+ */
+
+static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
+	.name	= "c2c",
+};
+
+/* c2c */
+static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
+	{ .irq = 88 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
+	{ .dma_req = 68 + OMAP44XX_DMA_REQ_START },
+	{ .dma_req = -1 }
+};
+
+static struct omap_hwmod omap44xx_c2c_hwmod = {
+	.name		= "c2c",
+	.class		= &omap44xx_c2c_hwmod_class,
+	.clkdm_name	= "d2d_clkdm",
+	.mpu_irqs	= omap44xx_c2c_irqs,
+	.sdma_reqs	= omap44xx_c2c_sdma_reqs,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
  * 'counter' class
  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
  */
@@ -806,6 +858,46 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 };
 
 /*
+ * 'elm' class
+ * bch error location module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0014,
+	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+			   SYSS_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
+	.name	= "elm",
+	.sysc	= &omap44xx_elm_sysc,
+};
+
+/* elm */
+static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
+	{ .irq = 4 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_elm_hwmod = {
+	.name		= "elm",
+	.class		= &omap44xx_elm_hwmod_class,
+	.clkdm_name	= "l4_per_clkdm",
+	.mpu_irqs	= omap44xx_elm_irqs,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
  * 'emif' class
  * external memory interface no1
  */
@@ -2268,6 +2360,29 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
 };
 
 /*
+ * 'sl2if' class
+ * shared level 2 memory interface
+ */
+
+static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
+	.name	= "sl2if",
+};
+
+/* sl2if */
+static struct omap_hwmod omap44xx_sl2if_hwmod = {
+	.name		= "sl2if",
+	.class		= &omap44xx_sl2if_hwmod_class,
+	.clkdm_name	= "ivahd_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/*
  * 'slimbus' class
  * bidirectional, multi-drop, multi-channel two-line serial interface between
  * the device and external components
@@ -3181,6 +3296,32 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
  * interfaces
  */
 
+static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
+	{
+		.pa_start	= 0x4a204000,
+		.pa_end		= 0x4a2040ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* c2c -> c2c_target_fw */
+static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
+	.master		= &omap44xx_c2c_hwmod,
+	.slave		= &omap44xx_c2c_target_fw_hwmod,
+	.clk		= "div_core_ck",
+	.addr		= omap44xx_c2c_target_fw_addrs,
+	.user		= OCP_USER_MPU,
+};
+
+/* l4_cfg -> c2c_target_fw */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_c2c_target_fw_hwmod,
+	.clk		= "l4_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l3_main_1 -> dmm */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
 	.master		= &omap44xx_l3_main_1_hwmod,
@@ -3207,6 +3348,14 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 	.user		= OCP_USER_MPU,
 };
 
+/* c2c -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
+	.master		= &omap44xx_c2c_hwmod,
+	.slave		= &omap44xx_emif_fw_hwmod,
+	.clk		= "div_core_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* dmm -> emif_fw */
 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 	.master		= &omap44xx_dmm_hwmod,
@@ -3315,6 +3464,14 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 	.user		= OCP_USER_MPU,
 };
 
+/* c2c_target_fw -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
+	.master		= &omap44xx_c2c_target_fw_hwmod,
+	.slave		= &omap44xx_l3_main_2_hwmod,
+	.clk		= "l3_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* dma_system -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 	.master		= &omap44xx_dma_system_hwmod,
@@ -3547,6 +3704,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 	.user		= OCP_USER_SDMA,
 };
 
+/* l3_main_2 -> c2c */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
+	.master		= &omap44xx_l3_main_2_hwmod,
+	.slave		= &omap44xx_c2c_hwmod,
+	.clk		= "l3_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 	{
 		.pa_start	= 0x4a304000,
@@ -3629,6 +3794,14 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
 	.user		= OCP_USER_DSP,
 };
 
+/* dsp -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
+	.master		= &omap44xx_dsp_hwmod,
+	.slave		= &omap44xx_sl2if_hwmod,
+	.clk		= "dpll_iva_m5x2_ck",
+	.user		= OCP_USER_DSP,
+};
+
 /* l4_cfg -> dsp */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
 	.master		= &omap44xx_l4_cfg_hwmod,
@@ -3889,6 +4062,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
 	.user		= OCP_USER_MPU,
 };
 
+static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
+	{
+		.pa_start	= 0x48078000,
+		.pa_end		= 0x48078fff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_per -> elm */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_elm_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_elm_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
 	{
 		.pa_start	= 0x4c000000,
@@ -4221,6 +4412,14 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* iva -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
+	.master		= &omap44xx_iva_hwmod,
+	.slave		= &omap44xx_sl2if_hwmod,
+	.clk		= "dpll_iva_m5x2_ck",
+	.user		= OCP_USER_IVA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
 	{
 		.pa_start	= 0x5a000000,
@@ -4641,6 +4840,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3_main_2 -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
+	.master		= &omap44xx_l3_main_2_hwmod,
+	.slave		= &omap44xx_sl2if_hwmod,
+	.clk		= "l3_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
 	{
 		.pa_start	= 0x4012c000,
@@ -5230,8 +5437,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
 };
 
 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
+	&omap44xx_c2c__c2c_target_fw,
+	&omap44xx_l4_cfg__c2c_target_fw,
 	&omap44xx_l3_main_1__dmm,
 	&omap44xx_mpu__dmm,
+	&omap44xx_c2c__emif_fw,
 	&omap44xx_dmm__emif_fw,
 	&omap44xx_l4_cfg__emif_fw,
 	&omap44xx_iva__l3_instr,
@@ -5243,6 +5453,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_mmc1__l3_main_1,
 	&omap44xx_mmc2__l3_main_1,
 	&omap44xx_mpu__l3_main_1,
+	&omap44xx_c2c_target_fw__l3_main_2,
 	&omap44xx_dma_system__l3_main_2,
 	&omap44xx_fdif__l3_main_2,
 	&omap44xx_gpu__l3_main_2,
@@ -5267,11 +5478,13 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_mpu__mpu_private,
 	&omap44xx_l4_abe__aess,
 	&omap44xx_l4_abe__aess_dma,
+	&omap44xx_l3_main_2__c2c,
 	&omap44xx_l4_wkup__counter_32k,
 	&omap44xx_l4_cfg__dma_system,
 	&omap44xx_l4_abe__dmic,
 	&omap44xx_l4_abe__dmic_dma,
 	&omap44xx_dsp__iva,
+	&omap44xx_dsp__sl2if,
 	&omap44xx_l4_cfg__dsp,
 	&omap44xx_l3_main_2__dss,
 	&omap44xx_l4_per__dss,
@@ -5287,6 +5500,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__dss_rfbi,
 	&omap44xx_l3_main_2__dss_venc,
 	&omap44xx_l4_per__dss_venc,
+	&omap44xx_l4_per__elm,
 	&omap44xx_emif_fw__emif1,
 	&omap44xx_emif_fw__emif2,
 	&omap44xx_l4_cfg__fdif,
@@ -5306,6 +5520,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__i2c4,
 	&omap44xx_l3_main_2__ipu,
 	&omap44xx_l3_main_2__iss,
+	&omap44xx_iva__sl2if,
 	&omap44xx_l3_main_2__iva,
 	&omap44xx_l4_wkup__kbd,
 	&omap44xx_l4_cfg__mailbox,
@@ -5329,6 +5544,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__mmc3,
 	&omap44xx_l4_per__mmc4,
 	&omap44xx_l4_per__mmc5,
+	&omap44xx_l3_main_2__sl2if,
 	&omap44xx_l4_abe__slimbus1,
 	&omap44xx_l4_abe__slimbus1_dma,
 	&omap44xx_l4_per__slimbus2,
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 8c39f70..965d8ab 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -214,6 +214,7 @@ struct omap_hwmod_addr_space {
 #define OCP_USER_MPU			(1 << 0)
 #define OCP_USER_SDMA			(1 << 1)
 #define OCP_USER_DSP			(1 << 2)
+#define OCP_USER_IVA			(1 << 3)
 
 /* omap_hwmod_ocp_if.flags bits */
 #define OCPIF_SWSUP_IDLE		(1 << 0)




From paul at pwsan.com  Thu Mar  8 05:51:36 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:36 -0700
Subject: [PATCH 13/15] ARM: OMAP4: hwmod data: add System Control Module
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105135.14753.35011.stgit@dusk>

Add the System Control Module hwmod and associated interconnect data.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  134 +++++++++++++++++++++++++++-
 1 files changed, 130 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 5c89307..ccc1249 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -293,10 +293,6 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
  *
  *  cm_core
  *  cm_core_aon
- *  ctrl_module_core
- *  ctrl_module_pad_core
- *  ctrl_module_pad_wkup
- *  ctrl_module_wkup
  *  debugss
  *  efuse_ctrl_cust
  *  efuse_ctrl_std
@@ -433,6 +429,60 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 };
 
 /*
+ * 'ctrl_module' class
+ * attila core control module + core pad control module + wkup pad control
+ * module + attila wkup control module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= SYSC_HAS_SIDLEMODE,
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
+	.name	= "ctrl_module",
+	.sysc	= &omap44xx_ctrl_module_sysc,
+};
+
+/* ctrl_module_core */
+static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
+	{ .irq = 8 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
+	.name		= "ctrl_module_core",
+	.class		= &omap44xx_ctrl_module_hwmod_class,
+	.clkdm_name	= "l4_cfg_clkdm",
+	.mpu_irqs	= omap44xx_ctrl_module_core_irqs,
+};
+
+/* ctrl_module_pad_core */
+static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
+	.name		= "ctrl_module_pad_core",
+	.class		= &omap44xx_ctrl_module_hwmod_class,
+	.clkdm_name	= "l4_cfg_clkdm",
+};
+
+/* ctrl_module_wkup */
+static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
+	.name		= "ctrl_module_wkup",
+	.class		= &omap44xx_ctrl_module_hwmod_class,
+	.clkdm_name	= "l4_wkup_clkdm",
+};
+
+/* ctrl_module_pad_wkup */
+static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
+	.name		= "ctrl_module_pad_wkup",
+	.class		= &omap44xx_ctrl_module_hwmod_class,
+	.clkdm_name	= "l4_wkup_clkdm",
+};
+
+/*
  * 'dma' class
  * dma controller for data exchange between memory to memory (i.e. internal or
  * external memory) and gp peripherals to memory or memory to gp peripherals
@@ -3881,6 +3931,78 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
+	{
+		.pa_start	= 0x4a002000,
+		.pa_end		= 0x4a0027ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_cfg -> ctrl_module_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_ctrl_module_core_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_ctrl_module_core_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
+	{
+		.pa_start	= 0x4a100000,
+		.pa_end		= 0x4a1007ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_cfg -> ctrl_module_pad_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_ctrl_module_pad_core_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_ctrl_module_pad_core_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
+	{
+		.pa_start	= 0x4a30c000,
+		.pa_end		= 0x4a30c7ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_wkup -> ctrl_module_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
+	.master		= &omap44xx_l4_wkup_hwmod,
+	.slave		= &omap44xx_ctrl_module_wkup_hwmod,
+	.clk		= "l4_wkup_clk_mux_ck",
+	.addr		= omap44xx_ctrl_module_wkup_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
+	{
+		.pa_start	= 0x4a31e000,
+		.pa_end		= 0x4a31e7ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_wkup -> ctrl_module_pad_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
+	.master		= &omap44xx_l4_wkup_hwmod,
+	.slave		= &omap44xx_ctrl_module_pad_wkup_hwmod,
+	.clk		= "l4_wkup_clk_mux_ck",
+	.addr		= omap44xx_ctrl_module_pad_wkup_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 	{
 		.pa_start	= 0x4a056000,
@@ -5668,6 +5790,10 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_abe__aess_dma,
 	&omap44xx_l3_main_2__c2c,
 	&omap44xx_l4_wkup__counter_32k,
+	&omap44xx_l4_cfg__ctrl_module_core,
+	&omap44xx_l4_cfg__ctrl_module_pad_core,
+	&omap44xx_l4_wkup__ctrl_module_wkup,
+	&omap44xx_l4_wkup__ctrl_module_pad_wkup,
 	&omap44xx_l4_cfg__dma_system,
 	&omap44xx_l4_abe__dmic,
 	&omap44xx_l4_abe__dmic_dma,




From paul at pwsan.com  Thu Mar  8 05:51:37 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:37 -0700
Subject: [PATCH 14/15] ARM: OMAP4: hwmod data: add PRCM and related IP blocks
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105136.14753.4296.stgit@dusk>

Add the PRCM, CM, PRM, and related hwmod and associated interconnect
data.  These IP blocks handle most of the on-chip power, reset, and clock
control.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  167 +++++++++++++++++++++++++++-
 1 files changed, 162 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ccc1249..a01d91f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -291,16 +291,11 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
  * - They still need to be validated with the driver
  *   properly adapted to omap_hwmod / omap_device
  *
- *  cm_core
- *  cm_core_aon
  *  debugss
  *  efuse_ctrl_cust
  *  efuse_ctrl_std
  *  mpu_c0
  *  mpu_c1
- *  prcm_mpu
- *  prm
- *  scrm
  *  usb_phy_cm
  *  usim
  */
@@ -2478,6 +2473,73 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
 };
 
 /*
+ * 'prcm' class
+ * power and reset manager (part of the prcm infrastructure) + clock manager 2
+ * + clock manager 1 (in always on power domain) + local prm in mpu
+ */
+
+static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
+	.name	= "prcm",
+};
+
+/* prcm_mpu */
+static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
+	.name		= "prcm_mpu",
+	.class		= &omap44xx_prcm_hwmod_class,
+	.clkdm_name	= "l4_wkup_clkdm",
+};
+
+/* cm_core_aon */
+static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
+	.name		= "cm_core_aon",
+	.class		= &omap44xx_prcm_hwmod_class,
+	.clkdm_name	= "cm_clkdm",
+};
+
+/* cm_core */
+static struct omap_hwmod omap44xx_cm_core_hwmod = {
+	.name		= "cm_core",
+	.class		= &omap44xx_prcm_hwmod_class,
+	.clkdm_name	= "cm_clkdm",
+};
+
+/* prm */
+static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
+	{ .irq = 11 + OMAP44XX_IRQ_GIC_START },
+	{ .irq = -1 }
+};
+
+static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
+	{ .name = "rst_global_warm_sw", .rst_shift = 0 },
+	{ .name = "rst_global_cold_sw", .rst_shift = 1 },
+};
+
+static struct omap_hwmod omap44xx_prm_hwmod = {
+	.name		= "prm",
+	.class		= &omap44xx_prcm_hwmod_class,
+	.clkdm_name	= "prm_clkdm",
+	.mpu_irqs	= omap44xx_prm_irqs,
+	.rst_lines	= omap44xx_prm_resets,
+	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_prm_resets),
+};
+
+/*
+ * 'scrm' class
+ * system clock and reset manager
+ */
+
+static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
+	.name	= "scrm",
+};
+
+/* scrm */
+static struct omap_hwmod omap44xx_scrm_hwmod = {
+	.name		= "scrm",
+	.class		= &omap44xx_scrm_hwmod_class,
+	.clkdm_name	= "l4_wkup_clkdm",
+};
+
+/*
  * 'sl2if' class
  * shared level 2 memory interface
  */
@@ -5129,6 +5191,96 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
+	{
+		.pa_start	= 0x48243000,
+		.pa_end		= 0x48243fff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* mpu_private -> prcm_mpu */
+static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
+	.master		= &omap44xx_mpu_private_hwmod,
+	.slave		= &omap44xx_prcm_mpu_hwmod,
+	.clk		= "l3_div_ck",
+	.addr		= omap44xx_prcm_mpu_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
+	{
+		.pa_start	= 0x4a004000,
+		.pa_end		= 0x4a004fff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_wkup -> cm_core_aon */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
+	.master		= &omap44xx_l4_wkup_hwmod,
+	.slave		= &omap44xx_cm_core_aon_hwmod,
+	.clk		= "l4_wkup_clk_mux_ck",
+	.addr		= omap44xx_cm_core_aon_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
+	{
+		.pa_start	= 0x4a008000,
+		.pa_end		= 0x4a009fff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_cfg -> cm_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
+	.master		= &omap44xx_l4_cfg_hwmod,
+	.slave		= &omap44xx_cm_core_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_cm_core_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
+	{
+		.pa_start	= 0x4a306000,
+		.pa_end		= 0x4a307fff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_wkup -> prm */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
+	.master		= &omap44xx_l4_wkup_hwmod,
+	.slave		= &omap44xx_prm_hwmod,
+	.clk		= "l4_wkup_clk_mux_ck",
+	.addr		= omap44xx_prm_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
+	{
+		.pa_start	= 0x4a30a000,
+		.pa_end		= 0x4a30a7ff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_wkup -> scrm */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
+	.master		= &omap44xx_l4_wkup_hwmod,
+	.slave		= &omap44xx_scrm_hwmod,
+	.clk		= "l4_wkup_clk_mux_ck",
+	.addr		= omap44xx_scrm_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l3_main_2 -> sl2if */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
 	.master		= &omap44xx_l3_main_2_hwmod,
@@ -5860,6 +6012,11 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_per__mmc5,
 	&omap44xx_l3_main_2__ocmc_ram,
 	&omap44xx_l4_cfg__ocp2scp_usb_phy,
+	&omap44xx_mpu_private__prcm_mpu,
+	&omap44xx_l4_wkup__cm_core_aon,
+	&omap44xx_l4_cfg__cm_core,
+	&omap44xx_l4_wkup__prm,
+	&omap44xx_l4_wkup__scrm,
 	&omap44xx_l3_main_2__sl2if,
 	&omap44xx_l4_abe__slimbus1,
 	&omap44xx_l4_abe__slimbus1_dma,




From paul at pwsan.com  Thu Mar  8 05:51:37 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 08 Mar 2012 03:51:37 -0700
Subject: [PATCH 15/15] ARM: OMAP4: hwmod data: add DEBUGSS skeleton
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <20120308105137.14753.19864.stgit@dusk>

From: Beno?t Cousson <b-cousson at ti.com>

Add a skeleton hwmod for the DEBUGSS and associated interconnect data.
This is a basic set of data that will need further additions as
further DEBUGSS information becomes available.

Signed-off-by: Beno?t Cousson <b-cousson at ti.com>
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   59 +++++++++++++++++++++++++---
 1 files changed, 52 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index a01d91f..2044c80 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -291,13 +291,7 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
  * - They still need to be validated with the driver
  *   properly adapted to omap_hwmod / omap_device
  *
- *  debugss
- *  efuse_ctrl_cust
- *  efuse_ctrl_std
- *  mpu_c0
- *  mpu_c1
- *  usb_phy_cm
- *  usim
+ * usim
  */
 
 /*
@@ -478,6 +472,29 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 };
 
 /*
+ * 'debugss' class
+ * debug and emulation sub system
+ */
+
+static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
+	.name	= "debugss",
+};
+
+/* debugss */
+static struct omap_hwmod omap44xx_debugss_hwmod = {
+	.name		= "debugss",
+	.class		= &omap44xx_debugss_hwmod_class,
+	.clkdm_name	= "emu_sys_clkdm",
+	.main_clk	= "trace_clk_div_ck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
+			.context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
+		},
+	},
+};
+
+/*
  * 'dma' class
  * dma controller for data exchange between memory to memory (i.e. internal or
  * external memory) and gp peripherals to memory or memory to gp peripherals
@@ -3709,6 +3726,14 @@ static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* debugss -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
+	.master		= &omap44xx_debugss_hwmod,
+	.slave		= &omap44xx_l3_main_2_hwmod,
+	.clk		= "dbgclk_mux_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* dma_system -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 	.master		= &omap44xx_dma_system_hwmod,
@@ -4065,6 +4090,24 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
+	{
+		.pa_start	= 0x54160000,
+		.pa_end		= 0x54167fff,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l3_instr -> debugss */
+static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
+	.master		= &omap44xx_l3_instr_hwmod,
+	.slave		= &omap44xx_debugss_hwmod,
+	.clk		= "l3_div_ck",
+	.addr		= omap44xx_debugss_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 	{
 		.pa_start	= 0x4a056000,
@@ -5914,6 +5957,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_mmc2__l3_main_1,
 	&omap44xx_mpu__l3_main_1,
 	&omap44xx_c2c_target_fw__l3_main_2,
+	&omap44xx_debugss__l3_main_2,
 	&omap44xx_dma_system__l3_main_2,
 	&omap44xx_fdif__l3_main_2,
 	&omap44xx_gpu__l3_main_2,
@@ -5946,6 +5990,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_cfg__ctrl_module_pad_core,
 	&omap44xx_l4_wkup__ctrl_module_wkup,
 	&omap44xx_l4_wkup__ctrl_module_pad_wkup,
+	&omap44xx_l3_instr__debugss,
 	&omap44xx_l4_cfg__dma_system,
 	&omap44xx_l4_abe__dmic,
 	&omap44xx_l4_abe__dmic_dma,




From enrico.scholz at sigma-chemnitz.de  Thu Mar  8 05:55:13 2012
From: enrico.scholz at sigma-chemnitz.de (Enrico Scholz)
Date: Thu, 08 Mar 2012 11:55:13 +0100
Subject: Regression in 3.2.9 for omap-serial (at least)
Message-ID: <lyk42vxsz2.fsf@ensc-virt.intern.sigma-chemnitz.de>

Hi,

the commit "genirq: Unmask oneshot irqs when thread was not woken"[1]
breaks at least the omap-serial driver which requests a shared interrupt
as

 --- arch/arm/mach-omap2/serial.c ---
	ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
				   IRQF_SHARED, "serial idle", (void *)uart);

 --- drivers/tty/serial/omap-serial.c
	retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
				up->name, up);


(note the missing IRQF_ONESHOT in the first piece of code)


Where previously 

  if (!irqd_irq_disabled(&desc->irq_data) && !(desc->istate & IRQS_ONESHOT))
          unmask_irq(desc);

was checked in kernel/irq/chip.c, now

  if (!irqd_irq_disabled(&desc->irq_data) &&
  	    irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
  		unmask_irq(desc);

will be done.

Because the threaded irq was requested without IRQF_ONESHOT, IRQS_ONESHOT
is not set but 'desc->threads_oneshot' is 1 due to the threaded irq. So,
irq was unmasked with old code but stays masked with the new one.  The new
behavior renders systems unusable because console becomes disfunctional.




Enrico

Footnotes: 
[1]  aa0eb3474beae8f6d9dcc2311dc02bea50cfd7b7


From broonie at opensource.wolfsonmicro.com  Thu Mar  8 05:58:22 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 8 Mar 2012 10:58:22 +0000
Subject: [PATCH v2 2/3] ARM/ASoC: OMAP McBSP: Move remainig defines from
 arch to ASoC header
In-Reply-To: <1331198537-13469-3-git-send-email-peter.ujfalusi@ti.com>
References: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>
 <1331198537-13469-3-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120308105821.GA3638@opensource.wolfsonmicro.com>

On Thu, Mar 08, 2012 at 11:22:16AM +0200, Peter Ujfalusi wrote:
> Clock signal muxing, and functional clock related defines are only needed
> in ASoC drivers.

Acked-by: Mark Brown <broonoie at opensource.wolfsonmicro.com>
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From broonie at opensource.wolfsonmicro.com  Thu Mar  8 05:59:21 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 8 Mar 2012 10:59:21 +0000
Subject: [PATCH v2 3/3] ASoC: omap-mcbsp: Single function CLKR/FSR source
 mux configuration
In-Reply-To: <1331198537-13469-4-git-send-email-peter.ujfalusi@ti.com>
References: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>
 <1331198537-13469-4-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120308105921.GB3638@opensource.wolfsonmicro.com>

On Thu, Mar 08, 2012 at 11:22:17AM +0200, Peter Ujfalusi wrote:
> Use single function for the CLKR/FSR mux configuration.
> OMAP2/3 has 6 pin configuration on McBSP1 instance, while on OMAP4
> McBSP4 instance have the 6 pin configuration so the omap2_mcbsp1_mux_* is
> not correct name for all support OMAP versions

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
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From jp.francois at cynove.com  Thu Mar  8 06:06:32 2012
From: jp.francois at cynove.com (jean-philippe francois)
Date: Thu, 8 Mar 2012 12:06:32 +0100
Subject: soft lockup on omap3 (dm3730)
In-Reply-To: <CAGGh5h3AtiuFuU0OY1FpPre6hyGKTSTEc=S6hkf2hAr=6LAehg@mail.gmail.com>
References: <CAGGh5h3OQTniXbm8iUYGM+2oi+zzd1F6BxDKzN5epA89+i_7nQ@mail.gmail.com>
 <20120307163750.GC18787@n2100.arm.linux.org.uk>
 <CAGGh5h3AtiuFuU0OY1FpPre6hyGKTSTEc=S6hkf2hAr=6LAehg@mail.gmail.com>
Message-ID: <CAGGh5h0CtnndXtHVU_tdRDja5OcABKe9yZfEDK7xi_VcRN8G_Q@mail.gmail.com>

Le 8 mars 2012 09:26, jean-philippe francois <jp.francois at cynove.com> a ?crit :
> Le 7 mars 2012 17:37, Russell King - ARM Linux
> <linux at arm.linux.org.uk> a ?crit :
>> On Wed, Mar 07, 2012 at 05:16:35PM +0100, jean-philippe francois wrote:
>>> Is the backtrace pointing to this offset because soft_lockup can only
>>> detect lockups at the output of critical sections ?
>>
>> Correct - soft lockups on ARM can only be detected when hardware
>> interrupts are enabled. ?Any region which masks hard interrupts
>> effectively prevents the soft lockup detector firing should
>> execution get stuck inside such a region.
>
> But then, how is the soft lockup detector able to break this hard lockup ?

I think I may be looking at the wrong place. May be the proc is stuck
in an IRQ that is
handled at the output of the critical sections ? Below is the soft
lockup backtrace :
what belongs to the soft lockup detector, and is not the real culprit
__do_softirq ?


BUG: soft lockup - CPU#0 stuck for 22s! [yavta:496]
Modules linked in: omap3_isp fpgacam(O) ks8851_mll

Pid: 496, comm:                yavta
CPU: 0    Tainted: G           O  (3.2.0 #55)
PC is at __do_softirq+0x50/0x110
LR is at __do_softirq+0x38/0x110
pc : [<c0036be4>]    lr : [<c0036bcc>]    psr: 20000113
sp : ceff3c70  ip : cf493800  fp : 00000000
r10: cefeb2ac  r9 : 0000000a  r8 : ceff2000
r7 : 00000002  r6 : 00000000  r5 : 00000000  r4 : 00000025
r3 : c0475c80  r2 : 00000000  r1 : 00000102  r0 : 00000000
Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 10c5387d  Table: 8e808019  DAC: 00000015
[<c00123b0>] (unwind_backtrace+0x0/0xec) from [<c0066310>]
(watchdog_timer_fn+0xd8/0x128)
[<c0066310>] (watchdog_timer_fn+0xd8/0x128) from [<c004d7a4>]
(__run_hrtimer+0x50/0xcc)
[<c004d7a4>] (__run_hrtimer+0x50/0xcc) from [<c004d9f0>]
(hrtimer_interrupt+0x114/0x290)
[<c004d9f0>] (hrtimer_interrupt+0x114/0x290) from [<c0018e30>]
(omap2_gp_timer_interrupt+0x24/0x34)
[<c0018e30>] (omap2_gp_timer_interrupt+0x24/0x34) from [<c0066a04>]
(handle_irq_event_percpu+0x28/0x110)
[<c0066a04>] (handle_irq_event_percpu+0x28/0x110) from [<c0066b28>]
(handle_irq_event+0x3c/0x5c)
[<c0066b28>] (handle_irq_event+0x3c/0x5c) from [<c0069128>]
(handle_level_irq+0xb8/0xe8)
[<c0069128>] (handle_level_irq+0xb8/0xe8) from [<c0066674>]
(generic_handle_irq+0x28/0x30)
[<c0066674>] (generic_handle_irq+0x28/0x30) from [<c000e570>]
(handle_IRQ+0x60/0x84)
[<c000e570>] (handle_IRQ+0x60/0x84) from [<c000d874>]
(__irq_svc+0x34/0x98)     <--- soft lockup backtrace
[<c000d874>] (__irq_svc+0x34/0x98) from [<c0036be4>]
(__do_softirq+0x50/0x110)  <--- real soft lockup position ??
[<c0036be4>] (__do_softirq+0x50/0x110) from [<c0036e7c>] (irq_exit+0x48/0x9c)
[<c0036e7c>] (irq_exit+0x48/0x9c) from [<c000e574>] (handle_IRQ+0x64/0x84)
[<c000e574>] (handle_IRQ+0x64/0x84) from [<c000d874>] (__irq_svc+0x34/0x98)
[<c000d874>] (__irq_svc+0x34/0x98) from [<c02d436c>]
(_raw_spin_unlock_irqrestore+0x28/0x50)
[<c02d436c>] (_raw_spin_unlock_irqrestore+0x28/0x50) from [<bf00e890>]
(omap3isp_video_queue_streamon+0x8c/0xa8 [omap3_isp])
[<bf00e890>] (omap3isp_video_queue_streamon+0x8c/0xa8 [omap3_isp])
from [<bf0105b4>] (isp_video_streamon+0x15c/0x224 [omap3_isp])
[<bf0105b4>] (isp_video_streamon+0x15c/0x224 [omap3_isp]) from
[<c0228450>] (__video_do_ioctl+0x1b9c/0x4894)
[<c0228450>] (__video_do_ioctl+0x1b9c/0x4894) from [<c0226774>]
(video_usercopy+0x1b8/0x298)
[<c0226774>] (video_usercopy+0x1b8/0x298) from [<c0225678>]
(v4l2_ioctl+0x6c/0x11c)
[<c0225678>] (v4l2_ioctl+0x6c/0x11c) from [<c00a3034>] (vfs_ioctl+0x20/0x3c)
[<c00a3034>] (vfs_ioctl+0x20/0x3c) from [<c00a38a4>] (do_vfs_ioctl+0x1ac/0x1c4)
[<c00a38a4>] (do_vfs_ioctl+0x1ac/0x1c4) from [<c00a38f0>] (sys_ioctl+0x34/0x54)
[<c00a38f0>] (sys_ioctl+0x34/0x54) from [<c000dcc0>] (ret_fast_syscall+0x0/0x30)

Thank you for your help


From kgene.kim at samsung.com  Thu Mar  8 06:08:03 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 08 Mar 2012 03:08:03 -0800
Subject: [GIT PULL] Samsung Cleanup S3C24XX for v3.4
Message-ID: <4F589313.1050706@samsung.com>

Hi Arnd, Olof,

Please pull cleanup s3c24xx from following:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/cleanup-s3c24xx

As I said before, this is including merge of mach-s3c24.. directories 
into just one mach-s3c24xx directory.

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit a5f17d1f4c2831b9b9bf8b1a537cdbac995d6e13:

   Merge tag 'v3.3-rc2' into depends/rmk/for-armsoc (2012-02-07 15:05:20 
-0800)

are available in the git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/cleanup-s3c24xx

Heiko Stuebner (17):
       ARM: S3C24XX: remove unused spi gpio setup functions
       ARM: S3C24XX: move spi-s3c24xx platdata out of mach
       ARM: S3C24XX: Remove extern declaration of clk_msysclk
       ARM: S3C24XX: move common S3C2443 clock definitions to clock.h
       ARM: S3C2410: move s3c2410_baseclk_add to clock.h
       ARM: S3C24XX: Move s3c2443-clock.c to mach-s3c24xx
       ARM: S3C24XX: Move common-smdk code to mach directory
       ARM: S3C24XX: move simtec-specific code to mach directory
       ARM: S3C24XX: Consolidate Simtec extensions
       ARM: S3C24XX: Move device setup files to mach directory
       ARM: S3C24XX: Fix indentation of dma-s3c2443
       ARM: S3C24XX: Reuse S3C2443 dma for S3C2416
       ARM: S3C24XX: remove obsolete S3C2416_DMA option
       ARM: S3C24XX: remove XXX_setup_clocks method from S3C2443
       ARM: S3C24XX: add get_rate for clk_h on S3C2416/2443
       ARM: S3C24XX: add get_rate for clk_p on S3C2416/2443
       ARM: S3C24XX: remove call to s3c24xx_setup_clocks

Kukjin Kim (8):
       ARM: S3C24XX: change the ARCH_S3C2410 to ARCH_S3C24XX
       ARM: S3C2410: move mach-s3c2410/* into mach-s3c24xx/
       ARM: S3C2412: move mach-s3c2412/* into mach-s3c24xx/
       ARM: S3C2416: move mach-s3c2416/* into mach-s3c24xx/
       ARM: S3C2440: move mach-s3c2440/* into mach-s3c24xx/
       ARM: S3C2443: move mach-s3c2443/* into mach-s3c24xx/
       ARM: s3c2410_defconfig: update s3c2410_defconfig
       Merge branch 'topic/cleanup-s3c24xx' into next/cleanup-s3c24xx

  arch/arm/Kconfig                                   |   27 +-
  arch/arm/Makefile                                  |    2 +-
  arch/arm/boot/compressed/head.S                    |    2 +-
  arch/arm/configs/mini2440_defconfig                |    2 +-
  arch/arm/configs/s3c2410_defconfig                 |   57 +--
  arch/arm/configs/tct_hammer_defconfig              |    2 +-
  arch/arm/mach-s3c2410/Kconfig                      |  154 ------
  arch/arm/mach-s3c2410/Makefile                     |   26 -
  arch/arm/mach-s3c2410/usb-simtec.h                 |   16 -
  arch/arm/mach-s3c2412/Kconfig                      |   85 ---
  arch/arm/mach-s3c2412/Makefile                     |   12 -
  arch/arm/mach-s3c2416/Kconfig                      |   60 ---
  arch/arm/mach-s3c2416/Makefile                     |   22 -
  arch/arm/mach-s3c2440/Kconfig                      |  165 ------
  arch/arm/mach-s3c2440/Makefile                     |   26 +-
  arch/arm/mach-s3c2440/common.h                     |   17 -
  arch/arm/mach-s3c2443/Kconfig                      |   32 --
  arch/arm/mach-s3c2443/Makefile                     |   20 -
  arch/arm/mach-s3c24xx/Kconfig                      |  538 
++++++++++++++++++++
  arch/arm/mach-s3c24xx/Makefile                     |   95 ++++
  .../{mach-s3c2410 => mach-s3c24xx}/Makefile.boot   |    0
  arch/arm/{mach-s3c2410 => mach-s3c24xx}/bast-ide.c |    0
  arch/arm/{mach-s3c2410 => mach-s3c24xx}/bast-irq.c |    0
  .../clock.c => mach-s3c24xx/clock-s3c2412.c}       |    0
  .../clock.c => mach-s3c24xx/clock-s3c2416.c}       |    1 -
  .../clock.c => mach-s3c24xx/clock-s3c2440.c}       |    0
  .../clock.c => mach-s3c24xx/clock-s3c2443.c}       |    7 -
  .../clock-s3c244x.c}                               |    0
  .../common-s3c2443.c}                              |   88 +++-
  .../{plat-s3c24xx => mach-s3c24xx}/common-smdk.c   |    0
  arch/arm/{mach-s3c2410 => mach-s3c24xx}/common.h   |    6 +
  .../dma.c => mach-s3c24xx/dma-s3c2410.c}           |    0
  .../dma.c => mach-s3c24xx/dma-s3c2412.c}           |    0
  .../dma.c => mach-s3c24xx/dma-s3c2440.c}           |    0
  .../dma.c => mach-s3c24xx/dma-s3c2443.c}           |   30 +-
  .../h1940-bluetooth.c                              |    0
  .../include/mach/anubis-cpld.h                     |    0
  .../include/mach/anubis-irq.h                      |    0
  .../include/mach/anubis-map.h                      |    0
  .../include/mach/bast-cpld.h                       |    0
  .../include/mach/bast-irq.h                        |    0
  .../include/mach/bast-map.h                        |    0
  .../include/mach/bast-pmu.h                        |    0
  .../include/mach/debug-macro.S                     |    0
  .../include/mach/dma.h                             |    0
  .../include/mach/entry-macro.S                     |    0
  .../include/mach/fb.h                              |    0
  .../include/mach/gpio-fns.h                        |    0
  .../include/mach/gpio-nrs.h                        |    0
  .../include/mach/gpio-track.h                      |    0
  .../include/mach/gpio.h                            |    0
  .../include/mach/gta02.h                           |    0
  .../include/mach/h1940-latch.h                     |    0
  .../include/mach/h1940.h                           |    0
  .../include/mach/hardware.h                        |    0
  .../include/mach/idle.h                            |    0
  .../include/mach/io.h                              |    0
  .../include/mach/irqs.h                            |    0
  .../include/mach/leds-gpio.h                       |    0
  .../include/mach/map.h                             |    0
  .../include/mach/osiris-cpld.h                     |    0
  .../include/mach/osiris-map.h                      |    0
  .../include/mach/otom-map.h                        |    0
  .../include/mach/pm-core.h                         |    0
  .../include/mach/regs-clock.h                      |    0
  .../include/mach/regs-dsc.h                        |    0
  .../include/mach/regs-gpio.h                       |    0
  .../include/mach/regs-gpioj.h                      |    0
  .../include/mach/regs-irq.h                        |    0
  .../include/mach/regs-lcd.h                        |    0
  .../include/mach/regs-mem.h                        |    0
  .../include/mach/regs-power.h                      |    0
  .../include/mach/regs-s3c2412-mem.h                |    0
  .../include/mach/regs-s3c2412.h                    |    0
  .../include/mach/regs-s3c2416-mem.h                |    0
  .../include/mach/regs-s3c2416.h                    |    0
  .../include/mach/regs-s3c2443-clock.h              |    0
  .../include/mach/regs-sdi.h                        |    0
  .../include/mach/tick.h                            |    0
  .../include/mach/timex.h                           |    0
  .../include/mach/uncompress.h                      |    0
  .../include/mach/vr1000-cpld.h                     |    0
  .../include/mach/vr1000-irq.h                      |    0
  .../include/mach/vr1000-map.h                      |    0
  .../irq.c => mach-s3c24xx/irq-s3c2412.c}           |    0
  .../irq.c => mach-s3c24xx/irq-s3c2416.c}           |    0
  .../irq.c => mach-s3c24xx/irq-s3c2440.c}           |    0
  .../irq.c => mach-s3c24xx/irq-s3c2443.c}           |    0
  .../s3c244x-irq.c => mach-s3c24xx/irq-s3c244x.c}   |    0
  .../{mach-s3c2410 => mach-s3c24xx}/mach-amlm5900.c |    0
  .../{mach-s3c2440 => mach-s3c24xx}/mach-anubis.c   |    1 +
  .../mach-at2440evb.c                               |    0
  .../arm/{mach-s3c2410 => mach-s3c24xx}/mach-bast.c |    3 +-
  .../{mach-s3c2440 => mach-s3c24xx}/mach-gta02.c    |    2 +-
  .../{mach-s3c2410 => mach-s3c24xx}/mach-h1940.c    |    0
  .../arm/{mach-s3c2412 => mach-s3c24xx}/mach-jive.c |    0
  .../{mach-s3c2440 => mach-s3c24xx}/mach-mini2440.c |    0
  arch/arm/{mach-s3c2410 => mach-s3c24xx}/mach-n30.c |    0
  .../{mach-s3c2440 => mach-s3c24xx}/mach-nexcoder.c |    0
  .../mach-osiris-dvs.c                              |    0
  .../{mach-s3c2440 => mach-s3c24xx}/mach-osiris.c   |    0
  .../arm/{mach-s3c2410 => mach-s3c24xx}/mach-otom.c |    0
  .../{mach-s3c2410 => mach-s3c24xx}/mach-qt2410.c   |    0
  .../{mach-s3c2440 => mach-s3c24xx}/mach-rx1950.c   |    0
  .../{mach-s3c2440 => mach-s3c24xx}/mach-rx3715.c   |    0
  .../{mach-s3c2410 => mach-s3c24xx}/mach-smdk2410.c |    0
  .../{mach-s3c2412 => mach-s3c24xx}/mach-smdk2413.c |    0
  .../{mach-s3c2416 => mach-s3c24xx}/mach-smdk2416.c |    0
  .../{mach-s3c2440 => mach-s3c24xx}/mach-smdk2440.c |    0
  .../{mach-s3c2443 => mach-s3c24xx}/mach-smdk2443.c |    0
  .../mach-tct_hammer.c                              |    0
  .../{mach-s3c2410 => mach-s3c24xx}/mach-vr1000.c   |    3 +-
  .../{mach-s3c2412 => mach-s3c24xx}/mach-vstms.c    |    0
  arch/arm/{mach-s3c2410 => mach-s3c24xx}/pm-h1940.S |    0
  .../pm.c => mach-s3c24xx/pm-s3c2410.c}             |    0
  .../pm.c => mach-s3c24xx/pm-s3c2412.c}             |    0
  .../pm.c => mach-s3c24xx/pm-s3c2416.c}             |    0
  arch/arm/{mach-s3c2410 => mach-s3c24xx}/s3c2410.c  |    0
  arch/arm/{mach-s3c2412 => mach-s3c24xx}/s3c2412.c  |    0
  arch/arm/{mach-s3c2416 => mach-s3c24xx}/s3c2416.c  |    0
  arch/arm/{mach-s3c2440 => mach-s3c24xx}/s3c2440.c  |    0
  arch/arm/{mach-s3c2440 => mach-s3c24xx}/s3c2442.c  |    0
  arch/arm/{mach-s3c2443 => mach-s3c24xx}/s3c2443.c  |    0
  arch/arm/{mach-s3c2440 => mach-s3c24xx}/s3c244x.c  |    0
  .../arm/{plat-s3c24xx => mach-s3c24xx}/setup-i2c.c |    0
  .../setup-sdhci-gpio.c                             |    0
  arch/arm/{plat-s3c24xx => mach-s3c24xx}/setup-ts.c |    0
  .../{plat-s3c24xx => mach-s3c24xx}/simtec-audio.c  |    2 +
  .../nor-simtec.c => mach-s3c24xx/simtec-nor.c}     |    2 +-
  .../pm-simtec.c => mach-s3c24xx/simtec-pm.c}       |    0
  .../usb-simtec.c => mach-s3c24xx/simtec-usb.c}     |    2 +-
  .../nor-simtec.h => mach-s3c24xx/simtec.h}         |    9 +-
  .../sleep.S => mach-s3c24xx/sleep-s3c2410.S}       |    0
  .../sleep.S => mach-s3c24xx/sleep-s3c2412.S}       |    0
  arch/arm/plat-s3c24xx/Kconfig                      |   57 +--
  arch/arm/plat-s3c24xx/Makefile                     |   19 +-
  arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c       |   36 --
  arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c         |   38 --
  arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c          |   36 --
  arch/arm/plat-samsung/Kconfig                      |    4 +-
  arch/arm/plat-samsung/include/plat/audio-simtec.h  |    3 -
  arch/arm/plat-samsung/include/plat/clock.h         |   22 +-
  arch/arm/plat-samsung/include/plat/regs-dma.h      |    2 +-
  arch/arm/plat-samsung/include/plat/s3c2410.h       |    2 -
  arch/arm/plat-samsung/include/plat/s3c2443.h       |   20 -
  drivers/input/touchscreen/Kconfig                  |    2 +-
  drivers/leds/Kconfig                               |    2 +-
  drivers/mmc/host/Kconfig                           |    2 +-
  drivers/mtd/nand/Kconfig                           |    2 +-
  drivers/rtc/Kconfig                                |    2 +-
  drivers/spi/Kconfig                                |    2 +-
  drivers/spi/spi-s3c24xx.c                          |    2 +-
  drivers/usb/Kconfig                                |    2 +-
  drivers/usb/gadget/Kconfig                         |    4 +-
  drivers/usb/host/ohci-hcd.c                        |    2 +-
  drivers/video/Kconfig                              |    2 +-
  drivers/watchdog/Kconfig                           |    2 +-
  .../mach/spi.h => include/linux/spi/s3c24xx.h      |   20 +-
  sound/soc/samsung/Kconfig                          |   12 +-
  159 files changed, 827 insertions(+), 986 deletions(-)
  delete mode 100644 arch/arm/mach-s3c2410/usb-simtec.h
  delete mode 100644 arch/arm/mach-s3c2416/Kconfig
  delete mode 100644 arch/arm/mach-s3c2416/Makefile
  delete mode 100644 arch/arm/mach-s3c2440/common.h
  delete mode 100644 arch/arm/mach-s3c2443/Kconfig
  delete mode 100644 arch/arm/mach-s3c2443/Makefile
  create mode 100644 arch/arm/mach-s3c24xx/Kconfig
  create mode 100644 arch/arm/mach-s3c24xx/Makefile
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/Makefile.boot (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/bast-ide.c (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/bast-irq.c (100%)
  rename arch/arm/{mach-s3c2412/clock.c => mach-s3c24xx/clock-s3c2412.c} 
(100%)
  rename arch/arm/{mach-s3c2416/clock.c => mach-s3c24xx/clock-s3c2416.c} 
(99%)
  rename arch/arm/{mach-s3c2440/clock.c => mach-s3c24xx/clock-s3c2440.c} 
(100%)
  rename arch/arm/{mach-s3c2443/clock.c => mach-s3c24xx/clock-s3c2443.c} 
(97%)
  rename arch/arm/{mach-s3c2440/s3c244x-clock.c => 
mach-s3c24xx/clock-s3c244x.c} (100%)
  rename arch/arm/{plat-s3c24xx/s3c2443-clock.c => 
mach-s3c24xx/common-s3c2443.c} (89%)
  rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/common-smdk.c (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/common.h (80%)
  rename arch/arm/{mach-s3c2410/dma.c => mach-s3c24xx/dma-s3c2410.c} (100%)
  rename arch/arm/{mach-s3c2412/dma.c => mach-s3c24xx/dma-s3c2412.c} (100%)
  rename arch/arm/{mach-s3c2440/dma.c => mach-s3c24xx/dma-s3c2440.c} (100%)
  rename arch/arm/{mach-s3c2443/dma.c => mach-s3c24xx/dma-s3c2443.c} (85%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/h1940-bluetooth.c (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/anubis-cpld.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/anubis-irq.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/anubis-map.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/bast-cpld.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/bast-irq.h 
(100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/bast-map.h 
(100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/bast-pmu.h 
(100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/debug-macro.S (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/dma.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/entry-macro.S (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/fb.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/gpio-fns.h 
(100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/gpio-nrs.h 
(100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/gpio-track.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/gpio.h (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/include/mach/gta02.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/h1940-latch.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/h1940.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/hardware.h 
(100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/idle.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/io.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/irqs.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/leds-gpio.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/map.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/osiris-cpld.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/osiris-map.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/otom-map.h 
(100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/pm-core.h 
(100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/regs-clock.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/regs-dsc.h 
(100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/regs-gpio.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/regs-gpioj.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/regs-irq.h 
(100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/regs-lcd.h 
(100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/regs-mem.h 
(100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/regs-power.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/regs-s3c2412-mem.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/regs-s3c2412.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/regs-s3c2416-mem.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/regs-s3c2416.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/regs-s3c2443-clock.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/regs-sdi.h 
(100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/tick.h (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/include/mach/timex.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/uncompress.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/vr1000-cpld.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/vr1000-irq.h (100%)
  rename arch/arm/{mach-s3c2410 => 
mach-s3c24xx}/include/mach/vr1000-map.h (100%)
  rename arch/arm/{mach-s3c2412/irq.c => mach-s3c24xx/irq-s3c2412.c} (100%)
  rename arch/arm/{mach-s3c2416/irq.c => mach-s3c24xx/irq-s3c2416.c} (100%)
  rename arch/arm/{mach-s3c2440/irq.c => mach-s3c24xx/irq-s3c2440.c} (100%)
  rename arch/arm/{mach-s3c2443/irq.c => mach-s3c24xx/irq-s3c2443.c} (100%)
  rename arch/arm/{mach-s3c2440/s3c244x-irq.c => 
mach-s3c24xx/irq-s3c244x.c} (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/mach-amlm5900.c (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/mach-anubis.c (99%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/mach-at2440evb.c (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/mach-bast.c (99%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/mach-gta02.c (99%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/mach-h1940.c (100%)
  rename arch/arm/{mach-s3c2412 => mach-s3c24xx}/mach-jive.c (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/mach-mini2440.c (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/mach-n30.c (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/mach-nexcoder.c (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/mach-osiris-dvs.c (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/mach-osiris.c (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/mach-otom.c (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/mach-qt2410.c (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/mach-rx1950.c (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/mach-rx3715.c (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/mach-smdk2410.c (100%)
  rename arch/arm/{mach-s3c2412 => mach-s3c24xx}/mach-smdk2413.c (100%)
  rename arch/arm/{mach-s3c2416 => mach-s3c24xx}/mach-smdk2416.c (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/mach-smdk2440.c (100%)
  rename arch/arm/{mach-s3c2443 => mach-s3c24xx}/mach-smdk2443.c (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/mach-tct_hammer.c (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/mach-vr1000.c (99%)
  rename arch/arm/{mach-s3c2412 => mach-s3c24xx}/mach-vstms.c (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/pm-h1940.S (100%)
  rename arch/arm/{mach-s3c2410/pm.c => mach-s3c24xx/pm-s3c2410.c} (100%)
  rename arch/arm/{mach-s3c2412/pm.c => mach-s3c24xx/pm-s3c2412.c} (100%)
  rename arch/arm/{mach-s3c2416/pm.c => mach-s3c24xx/pm-s3c2416.c} (100%)
  rename arch/arm/{mach-s3c2410 => mach-s3c24xx}/s3c2410.c (100%)
  rename arch/arm/{mach-s3c2412 => mach-s3c24xx}/s3c2412.c (100%)
  rename arch/arm/{mach-s3c2416 => mach-s3c24xx}/s3c2416.c (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/s3c2440.c (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/s3c2442.c (100%)
  rename arch/arm/{mach-s3c2443 => mach-s3c24xx}/s3c2443.c (100%)
  rename arch/arm/{mach-s3c2440 => mach-s3c24xx}/s3c244x.c (100%)
  rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/setup-i2c.c (100%)
  rename arch/arm/{mach-s3c2416 => mach-s3c24xx}/setup-sdhci-gpio.c (100%)
  rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/setup-ts.c (100%)
  rename arch/arm/{plat-s3c24xx => mach-s3c24xx}/simtec-audio.c (98%)
  rename arch/arm/{mach-s3c2410/nor-simtec.c => 
mach-s3c24xx/simtec-nor.c} (98%)
  rename arch/arm/{plat-s3c24xx/pm-simtec.c => mach-s3c24xx/simtec-pm.c} 
(100%)
  rename arch/arm/{mach-s3c2410/usb-simtec.c => 
mach-s3c24xx/simtec-usb.c} (99%)
  rename arch/arm/{mach-s3c2410/nor-simtec.h => mach-s3c24xx/simtec.h} (63%)
  rename arch/arm/{mach-s3c2410/sleep.S => mach-s3c24xx/sleep-s3c2410.S} 
(100%)
  rename arch/arm/{mach-s3c2412/sleep.S => mach-s3c24xx/sleep-s3c2412.S} 
(100%)
  delete mode 100644 arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
  delete mode 100644 arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
  delete mode 100644 arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
  rename arch/arm/mach-s3c2410/include/mach/spi.h => 
include/linux/spi/s3c24xx.h (56%)


From yegorslists at googlemail.com  Thu Mar  8 06:07:26 2012
From: yegorslists at googlemail.com (yegorslists at googlemail.com)
Date: Thu,  8 Mar 2012 12:07:26 +0100
Subject: [PATCH v2] GPMC: add ECC control definitions
Message-ID: <1331204846-19573-1-git-send-email-yegorslists@googlemail.com>

From: Yegor Yefremov <yegorslists at googlemail.com>

Signed-off-by: Yegor Yefremov <yegorslists at googlemail.com>
---
v2: READ and WRITE will be configured in the same way, so change the cases accordingly
 arch/arm/mach-omap2/gpmc.c |   30 +++++++++++++++++++++++-------
 1 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 00d5108..212018d 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -50,6 +50,19 @@
 #define GPMC_ECC_SIZE_CONFIG	0x1fc
 #define GPMC_ECC1_RESULT        0x200
 
+/* GPMC ECC control settings */
+#define GPMC_ECC_CTRL_ECCCLEAR		0x100
+#define GPMC_ECC_CTRL_ECCDISABLE	0x000
+#define GPMC_ECC_CTRL_ECCREG1		0x001
+#define GPMC_ECC_CTRL_ECCREG2		0x002
+#define GPMC_ECC_CTRL_ECCREG3		0x003
+#define GPMC_ECC_CTRL_ECCREG4		0x004
+#define GPMC_ECC_CTRL_ECCREG5		0x005
+#define GPMC_ECC_CTRL_ECCREG6		0x006
+#define GPMC_ECC_CTRL_ECCREG7		0x007
+#define GPMC_ECC_CTRL_ECCREG8		0x008
+#define GPMC_ECC_CTRL_ECCREG9		0x009
+
 #define GPMC_CS0_OFFSET		0x60
 #define GPMC_CS_SIZE		0x30
 
@@ -861,8 +874,9 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
 	gpmc_ecc_used = cs;
 
 	/* clear ecc and enable bits */
-	val = ((0x00000001<<8) | 0x00000001);
-	gpmc_write_reg(GPMC_ECC_CONTROL, val);
+	gpmc_write_reg(GPMC_ECC_CONTROL,
+			GPMC_ECC_CTRL_ECCCLEAR |
+			GPMC_ECC_CTRL_ECCREG1);
 
 	/* program ecc and result sizes */
 	val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
@@ -870,13 +884,15 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
 
 	switch (mode) {
 	case GPMC_ECC_READ:
-		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
+	case GPMC_ECC_WRITE:
+		gpmc_write_reg(GPMC_ECC_CONTROL,
+				GPMC_ECC_CTRL_ECCCLEAR |
+				GPMC_ECC_CTRL_ECCREG1);
 		break;
 	case GPMC_ECC_READSYN:
-		 gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
-		break;
-	case GPMC_ECC_WRITE:
-		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
+		gpmc_write_reg(GPMC_ECC_CONTROL,
+				GPMC_ECC_CTRL_ECCCLEAR |
+				GPMC_ECC_CTRL_ECCDISABLE);
 		break;
 	default:
 		printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
-- 
1.7.7



From yegor_sub1 at visionsystems.de  Thu Mar  8 06:10:31 2012
From: yegor_sub1 at visionsystems.de (Yegor Yefremov)
Date: Thu, 08 Mar 2012 12:10:31 +0100
Subject: [PATCH] GPMC: add ECC control definitions
In-Reply-To: <20120305230334.GM12083@atomide.com>
References: <4F1D4CB3.5080803@visionsystems.de>
 <20120305230334.GM12083@atomide.com>
Message-ID: <4F5893A7.2070909@visionsystems.de>

Am 06.03.2012 00:03, schrieb Tony Lindgren:
> * Yegor Yefremov <yegor_sub1 at visionsystems.de> [120123 03:33]:
>> Signed-off-by: Yegor Yefremov <yegorslists at googlemail.com>
>> ---
>>  arch/arm/mach-omap2/gpmc.c |   30 +++++++++++++++++++++++++-----
>>  1 file changed, 25 insertions(+), 5 deletions(-)
>>
>> Index: b/arch/arm/mach-omap2/gpmc.c
>> ===================================================================
>> --- a/arch/arm/mach-omap2/gpmc.c
>> +++ b/arch/arm/mach-omap2/gpmc.c
>> @@ -50,6 +50,19 @@
>>  #define GPMC_ECC_SIZE_CONFIG	0x1fc
>>  #define GPMC_ECC1_RESULT        0x200
>>  
>> +/* GPMC ECC control settings */
>> +#define GPMC_ECC_CTRL_ECCCLEAR		0x100
>> +#define GPMC_ECC_CTRL_ECCDISABLE	0x000
>> +#define GPMC_ECC_CTRL_ECCREG1		0x001
>> +#define GPMC_ECC_CTRL_ECCREG2		0x002
>> +#define GPMC_ECC_CTRL_ECCREG3		0x003
>> +#define GPMC_ECC_CTRL_ECCREG4		0x004
>> +#define GPMC_ECC_CTRL_ECCREG5		0x005
>> +#define GPMC_ECC_CTRL_ECCREG6		0x006
>> +#define GPMC_ECC_CTRL_ECCREG7		0x007
>> +#define GPMC_ECC_CTRL_ECCREG8		0x008
>> +#define GPMC_ECC_CTRL_ECCREG9		0x009
>> +
>>  #define GPMC_CS0_OFFSET		0x60
>>  #define GPMC_CS_SIZE		0x30
>>  
>> @@ -855,8 +868,9 @@
>>  	gpmc_ecc_used = cs;
>>  
>>  	/* clear ecc and enable bits */
>> -	val = ((0x00000001<<8) | 0x00000001);
>> -	gpmc_write_reg(GPMC_ECC_CONTROL, val);
>> +	gpmc_write_reg(GPMC_ECC_CONTROL,
>> +			GPMC_ECC_CTRL_ECCCLEAR |
>> +			GPMC_ECC_CTRL_ECCREG1);
>>  
>>  	/* program ecc and result sizes */
>>  	val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
>> @@ -864,13 +878,19 @@
>>  
>>  	switch (mode) {
>>  	case GPMC_ECC_READ:
>> -		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
>> +		gpmc_write_reg(GPMC_ECC_CONTROL,
>> +				GPMC_ECC_CTRL_ECCCLEAR |
>> +				GPMC_ECC_CTRL_ECCREG1);
>>  		break;
>>  	case GPMC_ECC_READSYN:
>> -		 gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
>> +		gpmc_write_reg(GPMC_ECC_CONTROL,
>> +				GPMC_ECC_CTRL_ECCCLEAR |
>> +				GPMC_ECC_CTRL_ECCDISABLE);
>>  		break;
>>  	case GPMC_ECC_WRITE:
>> -		gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
>> +		gpmc_write_reg(GPMC_ECC_CONTROL,
>> +				GPMC_ECC_CTRL_ECCCLEAR |
>> +				GPMC_ECC_CTRL_ECCREG1);
>>  		break;
>>  	default:
>>  		printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
>>
> No functional changes here, right?
>
> Can GPMC_ECC_READ and GPMC_ECC_WRITE case be combined:
>
> 	switch (mode) {
> 	case GPMC_ECC_READ:
> 	case GPMC_ECC_WRITE:
> 		gpmc_write_reg(GPMC_ECC_CONTROL,
> 			GPMC_ECC_CTRL_ECCCLEAR |
> 			GPMC_ECC_CTRL_ECCREG1);
> 	break;
> 	...

You are right. path v2 already sent.

Thanks for review.

Best regards,
Yegor



From kgene.kim at samsung.com  Thu Mar  8 06:13:56 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 08 Mar 2012 03:13:56 -0800
Subject: [GIT PULL] Samsung Cleanup EXYNOS clock for v3.4
Message-ID: <4F589474.8050609@samsung.com>

Hi Arnd, Olof,

Here is cleanup clock part for EXYNOS SoCs from:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/cleanup-exynos-clock

Please pull and if any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:

   Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)

are available in the git repository at:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/cleanup-exynos-clock

Kukjin Kim (2):
       ARM: EXYNOS: cleanup clock part for new EXYNOS SoCs
       PM / devfreq: update the name of EXYNOS clock register

  arch/arm/mach-exynos/Makefile                     |    3 +-
  arch/arm/mach-exynos/clock-exynos4.c              | 1564 
+++++++++++++++++++++
  arch/arm/mach-exynos/clock-exynos4.h              |   32 +
  arch/arm/mach-exynos/clock-exynos4210.c           |   46 +-
  arch/arm/mach-exynos/clock-exynos4212.c           |   30 +-
  arch/arm/mach-exynos/clock.c                      | 1564 
---------------------
  arch/arm/mach-exynos/common.h                     |    9 +
  arch/arm/mach-exynos/include/mach/exynos4-clock.h |   43 -
  arch/arm/mach-exynos/include/mach/regs-clock.h    |  364 +++---
  arch/arm/mach-exynos/pm.c                         |   40 +-
  drivers/devfreq/exynos4_bus.c                     |  224 ++--
  11 files changed, 1959 insertions(+), 1960 deletions(-)
  create mode 100644 arch/arm/mach-exynos/clock-exynos4.c
  create mode 100644 arch/arm/mach-exynos/clock-exynos4.h
  delete mode 100644 arch/arm/mach-exynos/clock.c
  delete mode 100644 arch/arm/mach-exynos/include/mach/exynos4-clock.h



From alexg at meprolight.com  Thu Mar  8 06:16:50 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Thu, 8 Mar 2012 13:16:50 +0200
Subject: I.MX35 PDK
In-Reply-To: <CAOMZO5DnP7+zupy9vwBPS0+2XtKM1+nLbwCqBzuCqEG5OWbZRQ@mail.gmail.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A28@MEP-EXCH.meprolight.com>

Hi Fabio,

Thanks for you response...

> in spite of this I get from ov2640 driver error
> Here Linux Kernel boot message:
>
> "Linux video capture interface: v2.00
> soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
> mx3-camera mx3-camera.0: MX3 Camera driver attached to camera 0
> ov2640 0-0030: Product ID error fb:fb"
>
> I cannot understand what the problem is, if someone tested this?

>>Looks like a I2C issue.

>>Check the I2C1 pad settings in the mainline kernel.

>>On FSL kernel we have:

#<<define PAD_CONFIG (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
>>PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain)

	<<switch (i2c_num) {
	<<case 0:
		<<mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
		<<mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);

		<<mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, PAD_CONFIG);
		<<mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, PAD_CONFIG);

>>Also check if you are getting the proper voltage levels at the I2C1 lines.

Yes this I2C problem, all I2C slave device need response to Host CPU by pulls I2C data bus to low, in other words generate ACK, the clock pulse for the acknowledge bit is always created by the bus master.

In this case, the camera tries to reset the data bus and generate an ACK, but the voltage drops to the area of two volts, although it should be reset to zero.
I replaced R172 with 10K on CPU board and got a good result, but there are other surprises 

Linux video capture interface: v2.00
soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
mx3-camera mx3-camera.0: MX3 Camera driver attached to camera 0
ov2640 0-0030: ov2640 Product ID 26:42 Manufacturer ID 7f:a2
i2c i2c-0: OV2640 Probed
mx3-camera mx3-camera.0: MX3 Camera driver detached from camera 0
dmaengine: failed to get dma1chan0: (-22)
dmaengine: failed to get dma1chan1: (-22)
dmaengine: failed to get dma1chan2: (-22)
dmaengine: failed to get dma1chan3: (-22)
dmaengine: failed to get dma1chan4: (-22)
dmaengine: failed to get dma1chan5: (-22)
dmaengine: failed to get dma1chan6: (-22)
dmaengine: failed to get dma1chan7: (-22)
dmaengine: failed to get dma1chan8: (-22)
dmaengine: failed to get dma1chan9: (-22)
dmaengine: failed to get dma1chan10: (-22)
dmaengine: failed to get dma1chan11: (-22)
dmaengine: failed to get dma1chan12: (-22)
dmaengine: failed to get dma1chan13: (-22)
dmaengine: failed to get dma1chan14: (-22)
dmaengine: failed to get dma1chan15: (-22)
dmaengine: failed to get dma1chan16: (-22)
dmaengine: failed to get dma1chan17: (-22)
dmaengine: failed to get dma1chan18: (-22)
dmaengine: failed to get dma1chan19: (-22)
dmaengine: failed to get dma1chan20: (-22)
dmaengine: failed to get dma1chan21: (-22)
dmaengine: failed to get dma1chan22: (-22)
dmaengine: failed to get dma1chan23: (-22)
dmaengine: failed to get dma1chan24: (-22)
dmaengine: failed to get dma1chan25: (-22)
dmaengine: failed to get dma1chan26: (-22)
dmaengine: failed to get dma1chan27: (-22)
dmaengine: failed to get dma1chan28: (-22)
dmaengine: failed to get dma1chan29: (-22)
dmaengine: failed to get dma1chan30: (-22):


What is the problem? 
Guennadi please help me understand 

Thanks,
 
Alex Gershgorin


From festevam at gmail.com  Thu Mar  8 06:26:24 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 8 Mar 2012 08:26:24 -0300
Subject: I.MX35 PDK
In-Reply-To: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A28@MEP-EXCH.meprolight.com>
References: <CAOMZO5DnP7+zupy9vwBPS0+2XtKM1+nLbwCqBzuCqEG5OWbZRQ@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A28@MEP-EXCH.meprolight.com>
Message-ID: <CAOMZO5Amo0XFf+TV7PprCL079C5Y0qKmo+k-FfShU7k4SG7W6Q@mail.gmail.com>

On 3/8/12, Alex Gershgorin <alexg at meprolight.com> wrote:
...
> Yes this I2C problem, all I2C slave device need response to Host CPU by
> pulls I2C data bus to low, in other words generate ACK, the clock pulse for
> the acknowledge bit is always created by the bus master.
>
> In this case, the camera tries to reset the data bus and generate an ACK,
> but the voltage drops to the area of two volts, although it should be reset
> to zero.
> I replaced R172 with 10K on CPU board and got a good result, but there are
> other surprises

Ok, good.

Can you try to change the I2C1 pad settings in software, so that the
board can work with the original resistor?

>
> Linux video capture interface: v2.00
> soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
> mx3-camera mx3-camera.0: MX3 Camera driver attached to camera 0
> ov2640 0-0030: ov2640 Product ID 26:42 Manufacturer ID 7f:a2
> i2c i2c-0: OV2640 Probed
> mx3-camera mx3-camera.0: MX3 Camera driver detached from camera 0
> dmaengine: failed to get dma1chan0: (-22)
> dmaengine: failed to get dma1chan1: (-22)
> dmaengine: failed to get dma1chan2: (-22)
> dmaengine: failed to get dma1chan3: (-22)
> dmaengine: failed to get dma1chan4: (-22)
> dmaengine: failed to get dma1chan5: (-22)
> dmaengine: failed to get dma1chan6: (-22)
> dmaengine: failed to get dma1chan7: (-22)
> dmaengine: failed to get dma1chan8: (-22)
> dmaengine: failed to get dma1chan9: (-22)
> dmaengine: failed to get dma1chan10: (-22)
> dmaengine: failed to get dma1chan11: (-22)
> dmaengine: failed to get dma1chan12: (-22)
> dmaengine: failed to get dma1chan13: (-22)
> dmaengine: failed to get dma1chan14: (-22)
> dmaengine: failed to get dma1chan15: (-22)
> dmaengine: failed to get dma1chan16: (-22)
> dmaengine: failed to get dma1chan17: (-22)
> dmaengine: failed to get dma1chan18: (-22)
> dmaengine: failed to get dma1chan19: (-22)
> dmaengine: failed to get dma1chan20: (-22)
> dmaengine: failed to get dma1chan21: (-22)
> dmaengine: failed to get dma1chan22: (-22)
> dmaengine: failed to get dma1chan23: (-22)
> dmaengine: failed to get dma1chan24: (-22)
> dmaengine: failed to get dma1chan25: (-22)
> dmaengine: failed to get dma1chan26: (-22)
> dmaengine: failed to get dma1chan27: (-22)
> dmaengine: failed to get dma1chan28: (-22)
> dmaengine: failed to get dma1chan29: (-22)
> dmaengine: failed to get dma1chan30: (-22):

This is something that needs to be solved, but it does not prevent the
camera to work though.

On my mx31pdk I get the same dmaengine errors and the ov2640 does work fine.

I think you can go ahead and try to use the camera on the mx35pdk now.

You can try:

gst-launch -v v4l2src device=/dev/video0 !
video/x-raw-yuv,width=320,height=240,framerate=25/1 ! ffmpegcolorspace
! fbdevsink

Regards,

Fabio Estevam


From rnayak at ti.com  Thu Mar  8 06:31:51 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 08 Mar 2012 17:01:51 +0530
Subject: [PATCH 00/15] ARM: OMAP4: hwmod data: add almost all remaining
 IP blocks
In-Reply-To: <20120308104918.14753.69281.stgit@dusk>
References: <20120308104918.14753.69281.stgit@dusk>
Message-ID: <4F5898A7.5040005@ti.com>

Hi Paul,

On Thursday 08 March 2012 04:21 PM, Paul Walmsley wrote:
> Hi
>
> This series adds basic hwmods for all but one of the remaining
> OMAP4 IP blocks that can be meaningfully controlled by the
> kernel.  (The remaining IP block is the USIM - there's a clocking
> problem that requires further investigation to resolve.)
>
> There are a few new boot-time warnings added by this series:
>
> [    0.280548] omap_hwmod: trace_clk_div_ck: missing clockdomain for trace_clk_div_ck.
> [    0.302429] omap_hwmod: ddrphy_ck: missing clockdomain for ddrphy_ck.
> [    0.319519] omap_hwmod: sl2if: cannot be enabled for reset (3)
>
> These messages will be resolved by subsequent patches, and, while annoying,
> should not affect the operation of the system.
>
> These patches have been boot-tested and suspend-tested on a
> OMAP44xx PandaBoard.
>
> The series is intended to apply on the
> 'hwmod_remove_link_arrays_cleanup_3.4' branch, posted previously.
>
> These patches are also available via git from git://git.pwsan.com/linux-2.6
> in the branch "hwmod_enable_remaining_hwmods_devel_3.4".

Could not find this branch on your tree. Found a
'enable_remaining_omap4_hwmods' instead, but that seems to
be an old branch.

regards,
Rajendra
>
>
> - Paul
>
> ---
>
> hwmod_enable_remaining_hwmods_devel_3.4
>     text	   data	    bss	    dec	    hex	filename
> 6590067	 677452	5593500	12861019	 c43e5b	vmlinux.omap2plus_defconfig.orig
> 6594227	 684620	5593500	12872347	 c46a9b	vmlinux.omap2plus_defconfig
>
> Beno?t Cousson (6):
>        ARM: OMAP4: hwmod data: add GPMC
>        ARM: OMAP4: hwmod data: add the Slimbus IP blocks
>        ARM: OMAP4: hwmod data: add McASP
>        ARM: OMAP4: hwmod data: add remaining USB-related IP blocks
>        ARM: OMAP4: hwmod data: add the OCP-WP IP block
>        ARM: OMAP4: hwmod data: add DEBUGSS skeleton
>
> Ming Lei (1):
>        ARM: OMAP4: hwmod data: introduce fdif(face detect module) hwmod
>
> Paul Walmsley (8):
>        ARM: OMAP2+: clockdomains: make {prm,cm}_clkdm common
>        ARM: OMAP4: hwmod data: add HDQ/1-wire
>        ARM: OMAP4: hwmod data: add EMIF1 and 2
>        ARM: OMAP4: hwmod data: add GPU
>        ARM: OMAP4: hwmod data: add some interconnect-related IP blocks
>        ARM: OMAP4: hwmod data: add OCM RAM IP block
>        ARM: OMAP4: hwmod data: add System Control Module
>        ARM: OMAP4: hwmod data: add PRCM and related IP blocks
>
>
>   arch/arm/mach-omap2/Makefile                     |    8
>   arch/arm/mach-omap2/clockdomain44xx.c            |    6
>   arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |   10
>   arch/arm/mach-omap2/clockdomains44xx_data.c      |    2
>   arch/arm/mach-omap2/clockdomains_common_data.c   |   24
>   arch/arm/mach-omap2/omap_hwmod_44xx_data.c       | 1473 +++++++++++++++++++++-
>   arch/arm/plat-omap/include/plat/omap_hwmod.h     |    1
>   7 files changed, 1443 insertions(+), 81 deletions(-)
>   create mode 100644 arch/arm/mach-omap2/clockdomains_common_data.c
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From g.liakhovetski at gmx.de  Thu Mar  8 06:34:41 2012
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Thu, 8 Mar 2012 12:34:41 +0100 (CET)
Subject: I.MX35 PDK
In-Reply-To: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A28@MEP-EXCH.meprolight.com>
References: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A28@MEP-EXCH.meprolight.com>
Message-ID: <Pine.LNX.4.64.1203081225290.29847@axis700.grange>

Hi Alex

Why is the cc-list mangled again? Why is the V4L list dropped again? 
What's so difficult about hitting the "reply-to-all" button?

On Thu, 8 Mar 2012, Alex Gershgorin wrote:

> Hi Fabio,
> 
> Thanks for you response...
> 
> > in spite of this I get from ov2640 driver error
> > Here Linux Kernel boot message:
> >
> > "Linux video capture interface: v2.00
> > soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
> > mx3-camera mx3-camera.0: MX3 Camera driver attached to camera 0
> > ov2640 0-0030: Product ID error fb:fb"
> >
> > I cannot understand what the problem is, if someone tested this?
> 
> >>Looks like a I2C issue.
> 
> >>Check the I2C1 pad settings in the mainline kernel.
> 
> >>On FSL kernel we have:
> 
> #<<define PAD_CONFIG (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
> >>PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain)
> 
> 	<<switch (i2c_num) {
> 	<<case 0:
> 		<<mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
> 		<<mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
> 
> 		<<mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, PAD_CONFIG);
> 		<<mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, PAD_CONFIG);
> 
> >>Also check if you are getting the proper voltage levels at the I2C1 lines.
> 
> Yes this I2C problem, all I2C slave device need response to Host CPU by pulls I2C data bus to low, in other words generate ACK, the clock pulse for the acknowledge bit is always created by the bus master.
> 
> In this case, the camera tries to reset the data bus and generate an ACK, but the voltage drops to the area of two volts, although it should be reset to zero.
> I replaced R172 with 10K on CPU board and got a good result, but there are other surprises 
> 
> Linux video capture interface: v2.00
> soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
> mx3-camera mx3-camera.0: MX3 Camera driver attached to camera 0
> ov2640 0-0030: ov2640 Product ID 26:42 Manufacturer ID 7f:a2
> i2c i2c-0: OV2640 Probed
> mx3-camera mx3-camera.0: MX3 Camera driver detached from camera 0
> dmaengine: failed to get dma1chan0: (-22)
> dmaengine: failed to get dma1chan1: (-22)
> dmaengine: failed to get dma1chan2: (-22)
> dmaengine: failed to get dma1chan3: (-22)

First of all it shows, that you're not using the newest kernel:

http://thread.gmane.org/gmane.linux.ports.sh.devel/11508

Secondly, as Fabio just pointed out, these messages are not fatal, which 
is also the reason, why I changed their priority to "debug"

Please, describe the actual problem, that you're getting (if any) and do 
add the v4l list back to the list of recipients!

Thanks
Guennadi

> dmaengine: failed to get dma1chan4: (-22)
> dmaengine: failed to get dma1chan5: (-22)
> dmaengine: failed to get dma1chan6: (-22)
> dmaengine: failed to get dma1chan7: (-22)
> dmaengine: failed to get dma1chan8: (-22)
> dmaengine: failed to get dma1chan9: (-22)
> dmaengine: failed to get dma1chan10: (-22)
> dmaengine: failed to get dma1chan11: (-22)
> dmaengine: failed to get dma1chan12: (-22)
> dmaengine: failed to get dma1chan13: (-22)
> dmaengine: failed to get dma1chan14: (-22)
> dmaengine: failed to get dma1chan15: (-22)
> dmaengine: failed to get dma1chan16: (-22)
> dmaengine: failed to get dma1chan17: (-22)
> dmaengine: failed to get dma1chan18: (-22)
> dmaengine: failed to get dma1chan19: (-22)
> dmaengine: failed to get dma1chan20: (-22)
> dmaengine: failed to get dma1chan21: (-22)
> dmaengine: failed to get dma1chan22: (-22)
> dmaengine: failed to get dma1chan23: (-22)
> dmaengine: failed to get dma1chan24: (-22)
> dmaengine: failed to get dma1chan25: (-22)
> dmaengine: failed to get dma1chan26: (-22)
> dmaengine: failed to get dma1chan27: (-22)
> dmaengine: failed to get dma1chan28: (-22)
> dmaengine: failed to get dma1chan29: (-22)
> dmaengine: failed to get dma1chan30: (-22):
> 
> 
> What is the problem? 
> Guennadi please help me understand 
> 
> Thanks,
>  
> Alex Gershgorin
> 

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From tglx at linutronix.de  Thu Mar  8 06:46:59 2012
From: tglx at linutronix.de (Thomas Gleixner)
Date: Thu, 8 Mar 2012 12:46:59 +0100 (CET)
Subject: Regression in 3.2.9 for omap-serial (at least)
In-Reply-To: <lyk42vxsz2.fsf@ensc-virt.intern.sigma-chemnitz.de>
References: <lyk42vxsz2.fsf@ensc-virt.intern.sigma-chemnitz.de>
Message-ID: <alpine.LFD.2.02.1203081246130.2742@ionos>

On Thu, 8 Mar 2012, Enrico Scholz wrote:
> Hi,
> 
> the commit "genirq: Unmask oneshot irqs when thread was not woken"[1]
> breaks at least the omap-serial driver which requests a shared interrupt

Fixed with 52abb700e16a9a

Thanks,

	tglx


From rnayak at ti.com  Thu Mar  8 06:48:36 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 08 Mar 2012 17:18:36 +0530
Subject: [PATCH v2 0/6] mmc: omap_hsmmc: Clean up use/abuse of pdev->id
In-Reply-To: <m2pqcoihhu.fsf@bob.laptop.org>
References: <1329996409-26861-1-git-send-email-rnayak@ti.com>	<4F476228.7060607@ti.com>
 <4F54714E.6080805@ti.com>	<4F57312E.4080104@ti.com>
 <m2pqcoihhu.fsf@bob.laptop.org>
Message-ID: <4F589C94.9010601@ti.com>

Hi Chris,

On Wednesday 07 March 2012 08:29 PM, Chris Ball wrote:
> Hi Rajendra,
>
> On Wed, Mar 07 2012, Rajendra Nayak wrote:
>>> Chris, Ping. I am basing my DT support patches on top of these cleanups.
>>> Would be great if you can have a look and pull them in.
>>
>> Chris, just realized the last two requests from me to get this merged
>> weren't addressed to you directly, but instead you were copied.
>> Resending with you in 'To', hope this lands in your inbox :)
>
> Sorry for the delay, thanks for the ping; I've pushed these to mmc-next
> for 3.4 now.

There's just one other cleanup patch here [1] to convert all pr_* prints
in the driver to dev_*. Would be great if you can pick that as well.

Thanks,
Rajendra

[1] http://marc.info/?l=linux-mmc&m=132999677405098&w=3

>
> Thanks,
>
> - Chris.



From broonie at opensource.wolfsonmicro.com  Thu Mar  8 06:51:27 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 8 Mar 2012 11:51:27 +0000
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <4F57E924.4050208@freescale.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <4F57CDAC.9030604@freescale.com>
 <20120307210833.GO3107@opensource.wolfsonmicro.com>
 <4F57E924.4050208@freescale.com>
Message-ID: <20120308115127.GI3638@opensource.wolfsonmicro.com>

On Wed, Mar 07, 2012 at 05:03:00PM -0600, Timur Tabi wrote:

> Our exalted maintainer apparently forgot to apply this patch in a timely
> manner for 3.3, so it probably won't make it.  But that's something I'll
> just have to deal with.

Probably work asking for it to have a CC to stable added (or ask Greg
directly if it gets applied without one) - people are getting better at
deploying stable updates so it'll save you some pain if it's in there.
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From broonie at opensource.wolfsonmicro.com  Thu Mar  8 07:02:07 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 8 Mar 2012 12:02:07 +0000
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <4F57ECC7.1040100@freescale.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <4F57ECC7.1040100@freescale.com>
Message-ID: <20120308120207.GJ3638@opensource.wolfsonmicro.com>

On Wed, Mar 07, 2012 at 05:18:31PM -0600, Timur Tabi wrote:

> I've tested this patchset, and after adding the changes that I pointed out
> in my previous email, audio still works on the P1022DS and MPC8610HPCD.

> Therefore:

> Acked-by: Timur Tabi <timur at freescale.com>

Excellent, it's great to see the SSI drivers merged!  Shawn, could you
please resend the unapplied patches with all the relevant acks collected
and tweaks that people requested just to make sure I've got everything.

I know Sascha wanted some slightly larger changes to the new card driver
so if you want to hold off on that until you've done the updates that's
fine but it'd be good to get all the other stuff merging the drivers
together for 3.4 if we can.
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From alexg at meprolight.com  Thu Mar  8 07:10:52 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Thu, 8 Mar 2012 14:10:52 +0200
Subject: I.MX35 PDK
In-Reply-To: <CAOMZO5Amo0XFf+TV7PprCL079C5Y0qKmo+k-FfShU7k4SG7W6Q@mail.gmail.com>
References: <CAOMZO5DnP7+zupy9vwBPS0+2XtKM1+nLbwCqBzuCqEG5OWbZRQ@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A28@MEP-EXCH.meprolight.com>,
 <CAOMZO5Amo0XFf+TV7PprCL079C5Y0qKmo+k-FfShU7k4SG7W6Q@mail.gmail.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8913@MEP-EXCH.meprolight.com>

 
> Yes this I2C problem, all I2C slave device need response to Host CPU by
> pulls I2C data bus to low, in other words generate ACK, the clock pulse for
> the acknowledge bit is always created by the bus master.
>
> In this case, the camera tries to reset the data bus and generate an ACK,
> but the voltage drops to the area of two volts, although it should be reset
> to zero.
> I replaced R172 with 10K on CPU board and got a good result, but there are
> other surprises

>Ok, good.

>Can you try to change the I2C1 pad settings in software, so that the
>board can work with the original resistor?

In the near future I will check this option:-) 

>
> Linux video capture interface: v2.00
> soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
> mx3-camera mx3-camera.0: MX3 Camera driver attached to camera 0
> ov2640 0-0030: ov2640 Product ID 26:42 Manufacturer ID 7f:a2
> i2c i2c-0: OV2640 Probed1
> mx3-camera mx3-camera.0: MX3 Camera driver detached from camera 0
> dmaengine: failed to get dma1chan0: (-22)
> dmaengine: failed to get dma1chan1: (-22)
> dmaengine: failed to get dma1chan2: (-22)
> dmaengine: failed to get dma1chan3: (-22)
> dmaengine: failed to get dma1chan4: (-22)
> dmaengine: failed to get dma1chan5: (-22)
> dmaengine: failed to get dma1chan6: (-22)
> dmaengine: failed to get dma1chan7: (-22)
> dmaengine: failed to get dma1chan8: (-22)
> dmaengine: failed to get dma1chan9: (-22)
> dmaengine: failed to get dma1chan10: (-22)
> dmaengine: failed to get dma1chan11: (-22)
> dmaengine: failed to get dma1chan12: (-22)
> dmaengine: failed to get dma1chan13: (-22)
> dmaengine: failed to get dma1chan14: (-22)
> dmaengine: failed to get dma1chan15: (-22)
> dmaengine: failed to get dma1chan16: (-22)
> dmaengine: failed to get dma1chan17: (-22)
> dmaengine: failed to get dma1chan18: (-22)
> dmaengine: failed to get dma1chan19: (-22)
> dmaengine: failed to get dma1chan20: (-22)
> dmaengine: failed to get dma1chan21: (-22)
> dmaengine: failed to get dma1chan22: (-22)
> dmaengine: failed to get dma1chan23: (-22)
> dmaengine: failed to get dma1chan24: (-22)
> dmaengine: failed to get dma1chan25: (-22)
> dmaengine: failed to get dma1chan26: (-22)
> dmaengine: failed to get dma1chan27: (-22)
> dmaengine: failed to get dma1chan28: (-22)
> dmaengine: failed to get dma1chan29: (-22)
> dmaengine: failed to get dma1chan30: (-22):

>This is something that needs to be solved, but it does not prevent the
>camera to work though.

>On my mx31pdk I get the same dmaengine errors and the ov2640 does work fine.
>I think you can go ahead and try to use the camera on the mx35pdk now.
>You can try:

>gst-launch -v v4l2src device=/dev/video0 !
>video/x-raw-yuv,width=320,height=240,framerate=25/1 ! ffmpegcolorspace
>! fbdevsink

 Thank Fabio I'll try to check it.

Regards
Alex Gershgorin 


From shawn.guo at linaro.org  Thu Mar  8 07:14:55 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 8 Mar 2012 20:14:55 +0800
Subject: [PATCH 1/3] drivers: base: add support for stmp-style devices
In-Reply-To: <1331159314-12022-2-git-send-email-w.sang@pengutronix.de>
References: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
 <1331159314-12022-2-git-send-email-w.sang@pengutronix.de>
Message-ID: <20120308121452.GA2499@S2101-09.ap.freescale.net>

On Wed, Mar 07, 2012 at 11:28:32PM +0100, Wolfram Sang wrote:
> MX23/28 use IP cores which follow a register layout I have first seen on
> STMP3xxx SoCs. In this layout, every register actually has four u32:
> 
>  1.) to store a value directly
>  2.) a SET register where every 1-bit sets the corresponding bit,
>      others are unaffected
>  3.) same with a CLR register
>  4.) same with a TOG (toggle) register
> 
> Also, the 2 MSBs in register 0 are always the same and can be used to reset
> the IP core.
> 
> All this is strictly speaking not mach-specific (but IP core specific) and,
> thus, doesn't need to be in mach-mxs/include. At least mx6 also uses IP cores
> following this stmp-style. So:
> 
> Introduce a stmp-style device, put the code and defines for that in a public
> place (drivers/base/), and let drivers for stmp-style devices select that code.
> To avoid regressions and ease reviewing, the actual code is simply copied from
> mach-mxs. It definately wants updates, but those need a seperate patch series.
> 
> Voila, mach dependency gone, reusable code introduced. Note that I didn't
> remove the duplicated code from mach-mxs yet, first the drivers have to be
> converted.
> 
> Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>

Acked-by: Shawn Guo <shawn.guo at linaro.org>


From dave.martin at linaro.org  Thu Mar  8 07:17:55 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 8 Mar 2012 12:17:55 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <4F5882BF.1030104@arm.com>
References: <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <alpine.LFD.2.02.1203021528150.31242@xanadu.home>
 <4F5882BF.1030104@arm.com>
Message-ID: <20120308121755.GA2703@linaro.org>

On Thu, Mar 08, 2012 at 09:58:23AM +0000, Richard Earnshaw wrote:
> On 02/03/12 21:15, Nicolas Pitre wrote:
> > [ coming back from vacation and trying to catch up ]
> >
> > On Wed, 29 Feb 2012, Dave Martin wrote:
> >
> >> Just had a chat with some tools guys -- apparently, when passing register
> >> arguments to gcc inline asms there really isn't a guarantee that those
> >> variables will be in the expected registers on entry to the inline asm.
> >>
> >> If gcc reorders other function calls or other code around the inline asm
> >> (which it can do, except under certain controlled situations), then
> >> intervening code can clobber any registers in general.
> >
> > I'm hearing this argument about once every year or so for the last 8
> > years.  I think that the tools people are getting confused between
> > themselves as you may get a different interpretation of what gcc should
> > do depending to whom you happen to talk to.
> >
> > I did submit a bug to gcc in 2004 about this:
> >
> >       http://gcc.gnu.org/bugzilla/show_bug.cgi?id=15089
> >
> > You can see the confusion among gcc developers lurking there.
> >
> > So let's quote the relevant gcc documentation:
> >
> > -> * C Extensions::    GNU extensions to the C language family.
> >    -> * Explicit Reg Vars::   Defining variables residing in specified registers.
> >
> > |GNU C allows you to put a few global variables into specified hardware
> > |registers.  You can also specify the register in which an ordinary
> > |register variable should be allocated.
> > |
> > |   * Global register variables reserve registers throughout the program.
> > |     This may be useful in programs such as programming language
> > |     interpreters which have a couple of global variables that are
> > |     accessed very often.
> > |
> > |   * Local register variables in specific registers do not reserve the
> > |     registers, except at the point where they are used as input or
> > |     output operands in an `asm' statement and the `asm' statement
> > |     itself is not deleted.  The compiler's data flow analysis is
> > |     capable of determining where the specified registers contain live
> > |     values, and where they are available for other uses.  Stores into
> > |     local register variables may be deleted when they appear to be
> > |     dead according to dataflow analysis.  References to local register
> > |     variables may be deleted or moved or simplified.
> > |
> > |     These local variables are sometimes convenient for use with the
> > |     extended `asm' feature (*note Extended Asm::), if you want to
> > |     write one output of the assembler instruction directly into a
> > |     particular register.  (This will work provided the register you
> > |     specify fits the constraints specified for that operand in the
> > |     `asm'.)
> >
> >       -> * Local Reg Vars::
> >
> > [...]
> >
> > | Defining such a register variable does not reserve the register; it
> > |remains available for other uses in places where flow control
> > |determines the variable's value is not live.
> > |
> > | This option does not guarantee that GCC will generate code that has
> > |this variable in the register you specify at all times.  You may not
> > |code an explicit reference to this register in the _assembler
> > |instruction template_ part of an `asm' statement and assume it will
> > |always refer to this variable.  However, using the variable as an `asm'
> > |_operand_ guarantees that the specified register is used for the
> > |operand.

Hmmm, it's a while since I saw that documentation, and it had clearly
fallen out of my head when I made my previous statements...

> >
> > So, to me, the gcc documentation is perfectly clear on this topic.
> > there really _is_ a guarantee that those asm marked variables will be in
> > the expected registers on entry to the inline asm, given that the
> > variable is _also_ listed as an operand to the asm statement.  But only
> > in that case.
> >
> > It is true that gcc may reorder other function calls or other code
> > around the inline asm and then intervening code can clobber any
> > registers.  Then it is up to gcc to preserve the variable's content
> > elsewhere when its register is used for other purposes, and restore it
> > when some inline asm statement is referring to it.
> >
> > And if gcc does not do this then it is buggy.  Version 3.4.0 of gcc was
> > buggy.  No other gcc versions in the last 7 years had such a problem or
> > the __asmeq macro in the kernel would have told us.
> >
> >> Or, to summarise another way, there is no way to control which register
> >> is used to pass something to an inline asm in general (often we get away
> >> with this, and there are a lot of inline asms in the kernel that assume
> >> it works, but the more you inline the more likely you are to get nasty
> >> surprises).
> >
> > This statement is therefore unfounded and wrong.  Please direct the
> > tools guy who mislead you to the above gcc documentation.
> >
> 
> The problem is not really about re-ordering functions but about implicit
> functions that come from the source code; for example
> 
> int foo (int a, int b)
> {
>   register int x __asm__("r0") = 33;
> 
>   register int c __asm__("r1") = a / b; /* Ooops, clobbers r0 with
> division function call.  */
> 
>   asm ("svc 0" : : "r" (x));
> }

|   * Local register variables in specific registers do not reserve the
|     registers, except at the point where they are used as input or
|     output operands in an `asm' statement and the `asm' statement
|     itself is not deleted.  The compiler's data flow analysis is

So, I guess the issue is how to interpret this statement in the context
of the above code:  i.e., what does it mean for a register to be reserved
for a local register variable?

"The above paragraph says that Local register variables [do] reserve the
registers _[at] the point_ where they are used as input or output
operands in an `asm' statement and the `asm' statement itself is not
deleted." (my emphasis)

Under that reading, r0 must be reserved for x on entry to the asm, but
not necessarily at points preceding that.  If the asm sees anything in
r0 except for x, that would be noncompliant with the above paragraph.

Nevertheless, a slightly modified version of the above which does not
allow gcc to optimise the asm away does trigger just the kind of
behaviour you describe:

int foo(int a, int b)
{
	register int x asm("r0") = 33;
	register int c asm("r1") = a / b;

	asm("svc 0" : "+r" (x) : "r" (c));

	return x;
}

 -->

00000000 <foo>:
   0:   e92d4008        push    {r3, lr}
   4:   ebfffffe        bl      0 <__aeabi_idiv>
   8:   e1a01000        mov     r1, r0
   c:   ef000000        svc     0x00000000
  10:   e8bd8008        pop     {r3, pc}


This is doubly weird: x is an I/O to the asm with a "+r" constraint,
so even if the asm("rX") assignments are not guaranteed, then x should
be _somewhere_ on entry to the asm (even if not in r0).  But it is
completely gone.

Is this allowed, or wrong?  I don't see how this can be rationalised
with the gcc documentation that Nico quoted.

Have I missed something?

Cheers
---Dave


From coelho at ti.com  Thu Mar  8 07:21:43 2012
From: coelho at ti.com (Coelho, Luciano)
Date: Thu, 8 Mar 2012 14:21:43 +0200
Subject: [PATCH 0/2] ARM: OMAP2+: PM: code consolidation for 3.4
In-Reply-To: <alpine.DEB.2.00.1202021328450.586@utopia.booyaka.com>
References: <20120202093600.12509.35052.stgit@dusk> <87ty39cc7s.fsf@ti.com>
 <alpine.DEB.2.00.1202021140060.586@utopia.booyaka.com>
 <alpine.DEB.2.00.1202021328450.586@utopia.booyaka.com>
Message-ID: <CAKd1q9rq67gUyXn+rOL348YwaYQiqHR8UQCSd68fpxhZHHsYGA@mail.gmail.com>

Hi,

On Thu, Feb 2, 2012 at 10:29 PM, Paul Walmsley <paul at pwsan.com> wrote:
> On Thu, 2 Feb 2012, Paul Walmsley wrote:
>
>> Great. ?Do you know what the deal is with suspend on 34xx? ?I enabled
>> ttyO2 wakeup and entered suspend, but serial traffic doesn't bring it out?
>
> Just a quick followup; Kevin tracked this down. ?v3.3-rc needs the MTD
> suspend patch that Artem posted recently to suspend correctly on OMAP35xx
> BeagleBoard with omap2plus_defconfig. ?Thanks Kevin.

I can't get ttyO2 wakeup to work on my Blaze with 3.3-rc5.  It works
fine with 3.2.  I've been trying to bisect and everything, but it's
difficult.  To start with, during my bisect, many patches seem to be
in a state where the compilation fails (one example is
'OMAP44XX_IRQ_PRCM' undeclared).

Anyway, what I found out is that after fcf6efa3 (ARM: OMAP4: PM: Add
WakeupGen module as OMAP gic_arch_extn) wakeup from the console
doesn't work anymore for me.  Then I tried to comment out the
omap_wakeupgen_init() call in  gic_init_irq() and that seems to
work... for a while.  At least until ff819da4 (ARM: OMAP3: CPUidle:
Make use of CPU PM notifiers) commenting out that line seems to work.
But it doesn't work if I comment out the line with v3.3-rc5.

And that's when I reckoned I've been using too much time trying to
figure this one out. :)

Does anyone know how to solve this?

-- 
Cheers,
Luca.


From shawn.guo at linaro.org  Thu Mar  8 07:33:10 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 8 Mar 2012 20:33:10 +0800
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <4F57E924.4050208@freescale.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <4F57CDAC.9030604@freescale.com>
 <20120307210833.GO3107@opensource.wolfsonmicro.com>
 <4F57E924.4050208@freescale.com>
Message-ID: <20120308123307.GB2499@S2101-09.ap.freescale.net>

On Wed, Mar 07, 2012 at 05:03:00PM -0600, Timur Tabi wrote:
...
> Shawn, I'd make the change myself, but I don't want to step on your toes
> while doing it.  Do you want to make it yourself?

I'd prefer you do it too.

-- 
Regards,
Shawn


From B04825 at freescale.com  Thu Mar  8 07:36:18 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Thu, 8 Mar 2012 12:36:18 +0000
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <20120308123307.GB2499@S2101-09.ap.freescale.net>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <4F57CDAC.9030604@freescale.com>
 <20120307210833.GO3107@opensource.wolfsonmicro.com>
 <4F57E924.4050208@freescale.com>
 <20120308123307.GB2499@S2101-09.ap.freescale.net>
Message-ID: <4F58A7C0.4070603@freescale.com>

Shawn Guo wrote:
>> >  Shawn, I'd make the change myself, but I don't want to step on your toes
>> >  while doing it.  Do you want to make it yourself?

> I'd prefer you do it too.

Ok.

-- 
Timur Tabi
Linux kernel developer at Freescale


From shawn.guo at linaro.org  Thu Mar  8 07:37:41 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 8 Mar 2012 20:37:41 +0800
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <20120308120207.GJ3638@opensource.wolfsonmicro.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <4F57ECC7.1040100@freescale.com>
 <20120308120207.GJ3638@opensource.wolfsonmicro.com>
Message-ID: <20120308123739.GC2499@S2101-09.ap.freescale.net>

On Thu, Mar 08, 2012 at 12:02:07PM +0000, Mark Brown wrote:
> On Wed, Mar 07, 2012 at 05:18:31PM -0600, Timur Tabi wrote:
> 
> > I've tested this patchset, and after adding the changes that I pointed out
> > in my previous email, audio still works on the P1022DS and MPC8610HPCD.
> 
> > Therefore:
> 
> > Acked-by: Timur Tabi <timur at freescale.com>
> 
> Excellent, it's great to see the SSI drivers merged!  Shawn, could you
> please resend the unapplied patches with all the relevant acks collected
> and tweaks that people requested just to make sure I've got everything.
> 
Sure.  I got interrupted from the work during the past 2 days, but I'm
resuming it now.

> I know Sascha wanted some slightly larger changes to the new card driver
> so if you want to hold off on that until you've done the updates that's
> fine but it'd be good to get all the other stuff merging the drivers
> together for 3.4 if we can.

That's my goal too.

-- 
Regards,
Shawn


From vinod.koul at intel.com  Thu Mar  8 07:49:48 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Thu, 08 Mar 2012 18:19:48 +0530
Subject: [GIT PULL] merge PL330 DMAC driver
In-Reply-To: <077301ccf769$f6ac3750$e404a5f0$%kim@samsung.com>
References: <077301ccf769$f6ac3750$e404a5f0$%kim@samsung.com>
Message-ID: <1331210988.4657.60.camel@vkoul-udesk3>

On Thu, 2012-03-01 at 14:12 +0900, Kukjin Kim wrote:
> Hi Russell and Vinod,
> 
> Please pull merging dma pl330 driver into drivers/dma/.
> It's time to send this to you, and I think that should be sent to upstream
> via rmk and dma tree together.
> 
> If any problems, please kindly let me know.
> 
> As a note, since there is no regarding samsung stuff here, I don't merge
> this into samsung tree.
Thanks, I have manually merged these tree patches with Jassi Ack.
They should be showing up in my next now.
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> 
> The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:
> 
>   Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)
> 
> are available in the git repository at:
>   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> v3.4-for-vkoul-v3
> 
> Boojin Kim (3):
>       DMA: PL330: Merge PL330 driver into drivers/dma/
>       DMA: PL330: Removes useless function
>       DMA: PL330: Support MEMTOMEM transmit w/o RMB, WMB
> 
>  arch/arm/common/Kconfig               |    3 -
>  arch/arm/common/Makefile              |    1 -
>  arch/arm/common/pl330.c               | 1959
> -------------------------------
>  arch/arm/include/asm/hardware/pl330.h |  217 ----
>  drivers/dma/Kconfig                   |    1 -
>  drivers/dma/pl330.c                   | 2089
> ++++++++++++++++++++++++++++++++-
>  include/linux/amba/pl330.h            |    1 -
>  7 files changed, 2088 insertions(+), 2183 deletions(-)
>  delete mode 100644 arch/arm/common/pl330.c
>  delete mode 100644 arch/arm/include/asm/hardware/pl330.h
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


-- 
~Vinod



From shawn.guo at linaro.org  Thu Mar  8 08:08:35 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 8 Mar 2012 21:08:35 +0800
Subject: [PATCH v2 09/17] ASoC: fsl: separate SSI and DMA Kconfig options
In-Reply-To: <4F57C30D.3000101@freescale.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <1330957865-19085-10-git-send-email-shawn.guo@linaro.org>
 <4F57C30D.3000101@freescale.com>
Message-ID: <20120308130832.GD2499@S2101-09.ap.freescale.net>

On Wed, Mar 07, 2012 at 02:20:29PM -0600, Timur Tabi wrote:
> Shawn Guo wrote:
> > The fsl_ssi driver will possibly be shared between Freescale PowerPC
> > and ARM/IMX families, so give it a separate Kconfig option.  Then
> > fsl_ssi driver can possibly be selected independently from selecting
> > PowerPC DMA based PCM driver.
> 
> This patch is going to require an update to the defconfigs, because by
> default, it sets audio as disabled.
> 
I guess you meant the next patch (#10) require an update, since
SND_POWERPC_SOC is introduced in that patch.

Regards,
Shawn

> menuconfig SND_POWERPC_SOC
> 	tristate "SoC Audio for Freescale PowerPC CPUs"
> 	depends on FSL_SOC
> 	help
> 	  Say Y or M if you want to add support for codecs attached to
> 	  the PowerPC CPUs.
> 
> The P1022DS uses mpc85xx_smp_defconfig and mpc85xx_defconfig.  The
> MPC8610HPCD uses mpc8610_hpcd_defconfig.


From shawn.guo at linaro.org  Thu Mar  8 08:11:19 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 8 Mar 2012 21:11:19 +0800
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <4F57ECC7.1040100@freescale.com>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <4F57ECC7.1040100@freescale.com>
Message-ID: <20120308131117.GE2499@S2101-09.ap.freescale.net>

On Wed, Mar 07, 2012 at 05:18:31PM -0600, Timur Tabi wrote:
> Shawn Guo wrote:
> > Changes since v1:
> >  * Address comments from Mark, Timur, and Sascha (Thanks for review).
> >  * Drop patches that have been applied by Mark.
> 
> I've tested this patchset, and after adding the changes that I pointed out
> in my previous email, audio still works on the P1022DS and MPC8610HPCD.
> 
Thanks a lot, Timur.

> Therefore:
> 
> Acked-by: Timur Tabi <timur at freescale.com>
> 
What are the patches I can apply your ack?  Or every one in this series?

-- 
Regards,
Shawn


From shubhrajyoti at ti.com  Thu Mar  8 08:17:55 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:47:55 +0530
Subject: [PATCHv2 03/13] I2C: OMAP: Recover from Bus Busy condition
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-4-git-send-email-shubhrajyoti@ti.com>

From: Vikram Pandita <vikram.pandita at ti.com>

In case a peripheral is driving SDA bus low (ie. a start condition), provide
a constant clock output using the test mode of the OMAP I2C controller to
try and clear the bus. Soft reset I2C controller after attempting the bus clear
to ensure that controller is in a good state.

Based upon Vikram Pandita's patch from TI Android 3.0.
I acknowledge the contributions and suggestions of Jon and Hemant.

A couple differences from the original patch ...
1. Add a new function for bus clear
2. Ensure that the CON.I2C_EN bit is set when using the SYSTEST feature to
   output a permanent clock. This bit needs to be set and typically it would
   be set by the unidle function but this is not the case for all OMAP
   generations.
3. Program the SYSTEST setting only the bits we care about. However, restore
   SYSTEST registers to there original state as some OMAP generations do not
   implement perform a soft-reset.
4. Clear the CON register after performing the bus clear, so when we call the
   init function the controller is disabled and the init function will
   re-enable later.


Signed-off-by: Vikram Pandita <vikram.pandita at ti.com>
Signed-off-by: Jon Hunter <jon-hunter at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
Original patch can be found here:
http://git.omapzoom.org/?p=kernel/omap.git;a=commit;h=a2ab04192ba25e60f95ba1ff3af5601a2d7b5bd1

 drivers/i2c/busses/i2c-omap.c |   33 ++++++++++++++++++++++++++++++---
 1 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index a115d2c..f19bb7e 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -147,16 +147,15 @@ enum {
 #define OMAP_I2C_SCLH_HSSCLH	8
 
 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
-#ifdef DEBUG
 #define OMAP_I2C_SYSTEST_ST_EN		(1 << 15)	/* System test enable */
 #define OMAP_I2C_SYSTEST_FREE		(1 << 14)	/* Free running mode */
 #define OMAP_I2C_SYSTEST_TMODE_MASK	(3 << 12)	/* Test mode select */
-#define OMAP_I2C_SYSTEST_TMODE_SHIFT	(12)		/* Test mode select */
+#define OMAP_I2C_SYSTEST_TMODE_TEST	(2 << 12)	/* Test mode select */
+#define OMAP_I2C_SYSTEST_TMODE_LOOP	(3 << 12)	/* Test mode select */
 #define OMAP_I2C_SYSTEST_SCL_I		(1 << 3)	/* SCL line sense in */
 #define OMAP_I2C_SYSTEST_SCL_O		(1 << 2)	/* SCL line drive out */
 #define OMAP_I2C_SYSTEST_SDA_I		(1 << 1)	/* SDA line sense in */
 #define OMAP_I2C_SYSTEST_SDA_O		(1 << 0)	/* SDA line drive out */
-#endif
 
 /* OCP_SYSSTATUS bit definitions */
 #define SYSS_RESETDONE_MASK		(1 << 0)
@@ -319,6 +318,7 @@ static int omap_i2c_reset(struct omap_i2c_dev *dev)
 							dev->westate);
 		}
 	}
+	return 0;
 }
 
 static int omap_i2c_init(struct omap_i2c_dev *dev)
@@ -471,6 +471,31 @@ static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 }
 
 /*
+ * Bus Clear
+ */
+static int omap_i2c_bus_clear(struct omap_i2c_dev *dev)
+{
+	u16 w;
+
+	/*
+	 * Per the I2C specification, if we are stuck in a bus busy state
+	 * we can attempt a bus clear to try and recover the bus by sending
+	 * at least 9 clock pulses on SCL. Put the I2C in a test mode so it
+	 * will output a continuous clock on SCL.
+	 */
+	w = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
+	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
+	omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG,
+		(OMAP_I2C_SYSTEST_ST_EN | OMAP_I2C_SYSTEST_TMODE_TEST));
+	msleep(1);
+	omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, w);
+	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
+	omap_i2c_reset(dev);
+	omap_i2c_init(dev);
+	return omap_i2c_wait_for_bb(dev);
+}
+
+/*
  * Low level master read/write transaction.
  */
 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
@@ -597,6 +622,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 
 	r = omap_i2c_wait_for_bb(dev);
 	if (r < 0)
+		r = omap_i2c_bus_clear(dev);
+	if (r < 0)
 		goto out;
 
 	if (dev->set_mpu_wkup_lat != NULL)
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:17:53 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:47:53 +0530
Subject: [PATCHv2 01/13] I2C : OMAP : make omap_i2c_unidle/idle functions
 depend on CONFIG_PM_RUNTIME
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-2-git-send-email-shubhrajyoti@ti.com>

The functions omap_i2c_unidle/idle are called from omap_i2c_runtime_resume
and omap_i2c_runtime_suspend which is compiled for CONFIG_PM_RUNTIME.
This patch removes the omap_i2c_unidle/idle functions and folds them
into the runtime callbacks.

This fixes the below warn when CONFIG_PM_RUNTIME is not defined

 CC      arch/arm/mach-omap2/board-ti8168evm.o
drivers/i2c/busses/i2c-omap.c:272: warning: 'omap_i2c_unidle' defined but not used
drivers/i2c/busses/i2c-omap.c:293: warning: 'omap_i2c_idle' defined but not used
  CC      net/ipv4/ip_forward.o

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   75 +++++++++++++++++-----------------------
 1 files changed, 32 insertions(+), 43 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 801df60..4f4188d 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -269,47 +269,6 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 				(i2c_dev->regs[reg] << i2c_dev->reg_shift));
 }
 
-static void omap_i2c_unidle(struct omap_i2c_dev *dev)
-{
-	if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
-		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
-		omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
-		omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
-		omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
-		omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
-		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
-		omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
-		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
-	}
-
-	/*
-	 * Don't write to this register if the IE state is 0 as it can
-	 * cause deadlock.
-	 */
-	if (dev->iestate)
-		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
-}
-
-static void omap_i2c_idle(struct omap_i2c_dev *dev)
-{
-	u16 iv;
-
-	dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
-	if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
-		omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1);
-	else
-		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
-
-	if (dev->rev < OMAP_I2C_OMAP1_REV_2) {
-		iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
-	} else {
-		omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
-
-		/* Flush posted write */
-		omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
-	}
-}
-
 static int omap_i2c_init(struct omap_i2c_dev *dev)
 {
 	u16 psc = 0, scll = 0, sclh = 0, buf = 0;
@@ -1163,8 +1122,22 @@ static int omap_i2c_runtime_suspend(struct device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
+	u16 iv;
+
+	_dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
+	if (_dev->dtrev == OMAP_I2C_IP_VERSION_2)
+		omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1);
+	else
+		omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
+
+	if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
+		iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
+	} else {
+		omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
 
-	omap_i2c_idle(_dev);
+		/* Flush posted write */
+		omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
+	}
 
 	return 0;
 }
@@ -1174,7 +1147,23 @@ static int omap_i2c_runtime_resume(struct device *dev)
 	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
 
-	omap_i2c_unidle(_dev);
+	if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
+		omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
+		omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
+		omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
+		omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
+		omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
+		omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
+		omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
+		omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
+	}
+
+	/*
+	 * Don't write to this register if the IE state is 0 as it can
+	 * cause deadlock.
+	 */
+	if (_dev->iestate)
+		omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
 
 	return 0;
 }
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:17:54 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:47:54 +0530
Subject: [PATCHv2 02/13] OMAP : I2C : Remove reset at init
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-3-git-send-email-shubhrajyoti@ti.com>

The reset in the driver at init is not needed anymore as the
following patch has removed the HWMOD_INIT_NO_RESET flag.
6d3c55f [OMAP: hwmod: fix the i2c-reset timeout during bootup]

This patch does the following
-removes the reset from the probe and implements a omap_i2c_reset
 function to reset.
- Reset is removed from omap_i2c_init, which was called
 not only during probe, but also after time out and error handling.
 omap_i2c_reset is added in those places to effect the reset.

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   20 +++++++++++++-------
 1 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 4f4188d..a115d2c 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -269,15 +269,9 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 				(i2c_dev->regs[reg] << i2c_dev->reg_shift));
 }
 
-static int omap_i2c_init(struct omap_i2c_dev *dev)
+static int omap_i2c_reset(struct omap_i2c_dev *dev)
 {
-	u16 psc = 0, scll = 0, sclh = 0, buf = 0;
-	u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
-	unsigned long fclk_rate = 12000000;
 	unsigned long timeout;
-	unsigned long internal_clk = 0;
-	struct clk *fclk;
-
 	if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
 		/* Disable I2C controller before soft reset */
 		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
@@ -325,6 +319,16 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
 							dev->westate);
 		}
 	}
+}
+
+static int omap_i2c_init(struct omap_i2c_dev *dev)
+{
+	u16 psc = 0, scll = 0, sclh = 0, buf = 0;
+	u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
+	unsigned long fclk_rate = 12000000;
+	unsigned long internal_clk = 0;
+	struct clk *fclk;
+
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 
 	if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
@@ -549,6 +553,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 	if (r == 0) {
 		dev_err(dev->dev, "controller timed out\n");
 		omap_i2c_init(dev);
+		omap_i2c_reset(dev);
 		return -ETIMEDOUT;
 	}
 
@@ -559,6 +564,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 	if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 			    OMAP_I2C_STAT_XUDF)) {
 		omap_i2c_init(dev);
+		omap_i2c_reset(dev);
 		return -EIO;
 	}
 
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:17:56 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:47:56 +0530
Subject: [PATCHv2 04/13] OMAP: I2C: I2C register restore only if context is
 lost
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-5-git-send-email-shubhrajyoti@ti.com>

 Currently i2c register restore is done always.
 Adding conditional restore.
 The i2c register restore is done only if the context is lost.
 Also remove the definition of SYSS_RESETDONE_MASK and use the
 one in omap_hwmod.h.

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 arch/arm/plat-omap/i2c.c      |    3 +++
 drivers/i2c/busses/i2c-omap.c |   40 ++++++++++++++++++++++++++++------------
 include/linux/i2c-omap.h      |    1 +
 3 files changed, 32 insertions(+), 12 deletions(-)

diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index db071bc..4ccab07 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -179,6 +179,9 @@ static inline int omap2_i2c_add_bus(int bus_id)
 	 */
 	if (cpu_is_omap34xx())
 		pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
+
+	pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
+
 	pdev = omap_device_build(name, bus_id, oh, pdata,
 			sizeof(struct omap_i2c_bus_platform_data),
 			NULL, 0, 0);
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index f19bb7e..ceb09c7 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -43,6 +43,7 @@
 #include <linux/slab.h>
 #include <linux/i2c-omap.h>
 #include <linux/pm_runtime.h>
+#include <plat/omap_device.h>
 
 /* I2C controller revisions */
 #define OMAP_I2C_OMAP1_REV_2		0x20
@@ -157,9 +158,6 @@ enum {
 #define OMAP_I2C_SYSTEST_SDA_I		(1 << 1)	/* SDA line sense in */
 #define OMAP_I2C_SYSTEST_SDA_O		(1 << 0)	/* SDA line drive out */
 
-/* OCP_SYSSTATUS bit definitions */
-#define SYSS_RESETDONE_MASK		(1 << 0)
-
 /* OCP_SYSCONFIG bit definitions */
 #define SYSC_CLOCKACTIVITY_MASK		(0x3 << 8)
 #define SYSC_SIDLEMODE_MASK		(0x3 << 3)
@@ -184,6 +182,7 @@ struct omap_i2c_dev {
 	u32			latency;	/* maximum mpu wkup latency */
 	void			(*set_mpu_wkup_lat)(struct device *dev,
 						    long latency);
+	int			(*get_context_loss_count)(struct device *dev);
 	u32			speed;		/* Speed of bus in kHz */
 	u32			dtrev;		/* extra revision from DT */
 	u32			flags;
@@ -206,6 +205,7 @@ struct omap_i2c_dev {
 	u16			syscstate;
 	u16			westate;
 	u16			errata;
+	int			dev_lost_count;
 };
 
 static const u8 reg_map_ip_v1[] = {
@@ -1025,6 +1025,7 @@ omap_i2c_probe(struct platform_device *pdev)
 		dev->speed = pdata->clkrate;
 		dev->flags = pdata->flags;
 		dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
+		dev->get_context_loss_count = pdata->get_context_loss_count;
 		dev->dtrev = pdata->rev;
 	}
 
@@ -1151,12 +1152,25 @@ omap_i2c_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM_RUNTIME
+static void omap_i2c_restore(struct omap_i2c_dev *dev)
+{
+	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
+	omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
+	omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
+	omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
+	omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
+	omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
+	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
+}
 static int omap_i2c_runtime_suspend(struct device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
 	u16 iv;
 
+	if (_dev->get_context_loss_count)
+		_dev->dev_lost_count = _dev->get_context_loss_count(dev);
+
 	_dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
 	if (_dev->dtrev == OMAP_I2C_IP_VERSION_2)
 		omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1);
@@ -1179,18 +1193,20 @@ static int omap_i2c_runtime_resume(struct device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
+	int loss_cnt;
+
+	if (_dev->get_context_loss_count) {
+		loss_cnt = _dev->get_context_loss_count(dev);
+		if (loss_cnt < 0)
+			return loss_cnt;
 
-	if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
-		omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
-		omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
-		omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
-		omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
-		omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
-		omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
-		omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
-		omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
+		if (_dev->dev_lost_count == loss_cnt && _dev->dev_lost_count)
+			return 0;
 	}
 
+	if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE)
+		omap_i2c_restore(_dev);
+
 	/*
 	 * Don't write to this register if the IE state is 0 as it can
 	 * cause deadlock.
diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
index 92a0dc7..c76cbc0 100644
--- a/include/linux/i2c-omap.h
+++ b/include/linux/i2c-omap.h
@@ -35,6 +35,7 @@ struct omap_i2c_bus_platform_data {
 	u32		rev;
 	u32		flags;
 	void		(*set_mpu_wkup_lat)(struct device *dev, long set);
+	int		(*get_context_loss_count)(struct device *dev);
 };
 
 #endif
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:17:57 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:47:57 +0530
Subject: [PATCHv2 05/13] OMAP: I2C: Fix the interrupt clearing in OMAP4
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-6-git-send-email-shubhrajyoti@ti.com>

On OMAP4 we were writing 1 to IRQENABLE_CLR which cleared only
the arbitration lost interrupt. The patch intends to fix the same by writing 0
to the IE register clearing all interrupts.

This is based on the work done by Vikram Pandita <vikram.pandita at ti.com>.

The  changes from the original patch ...
-  Does not use the IRQENABLE_CLR register to clear as it is not mentioned
  to be legacy register IRQENABLE_CLR helps in  atomically
  setting/clearing specific interrupts, instead use the OMAP_I2C_IE_REG as we are
  clearing all interrupts.

Cc: Vikram Pandita <vikram.pandita at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
Original patch can be found here:
http://git.omapzoom.org/?p=kernel/omap.git;a=commit;h=41049d62e146e0fafe2fac0a31be566b3bbc9149

 drivers/i2c/busses/i2c-omap.c |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index ceb09c7..98720c9 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1172,10 +1172,8 @@ static int omap_i2c_runtime_suspend(struct device *dev)
 		_dev->dev_lost_count = _dev->get_context_loss_count(dev);
 
 	_dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
-	if (_dev->dtrev == OMAP_I2C_IP_VERSION_2)
-		omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1);
-	else
-		omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
+
+	omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
 
 	if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
 		iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:17:52 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:47:52 +0530
Subject: [PATCHv2 00/13] I2C updates
Message-ID: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>

The patch series does the following 

- Warn fixes if CONFIG_PM_RUNTIME is not selected.
- I2C register restore only if context if the context is lost
- Bus busy recovery mechanism.
- the reset is not done in init.

v2 changes
-Adds a patch to use devm_* functions
-Also checks the return type of the get_sync and in case
 of errors prevents register access. 
- In case of i2c remove register access was done without any
 get_sync fix the same.
- Adds a pdata function pointer to do context save restore
 
Tested on omap4sdp and omap3sdp. 

Also available through 

git://gitorious.org/linus-tree/linus-tree.git for_3.4_i2c_fixes


Jon Hunter (1):
  I2C: OMAP: Correct I2C revision for OMAP3

Shubhrajyoti D (11):
  I2C : OMAP : make omap_i2c_unidle/idle functions depend on
    CONFIG_PM_RUNTIME
  OMAP : I2C : Remove reset at init
  OMAP: I2C: I2C register restore only if context is lost
  OMAP: I2C: Fix the interrupt clearing in OMAP4
  OMAP: I2C: Fix the mismatch of pm_runtime enable and disable
  OMAP: I2C: Optimise the remove code
  OMAP: I2C: Fix the error handling
  I2C: OMAP: Don't check if wait_for_completion_timeout() returns less
    than zero
  OMAP : I2C : use devm_* functions
  I2C : OMAP : Fix the crash in i2c remove
  OMAP: I2C: Handle error check for pm runtime

Vikram Pandita (1):
  I2C: OMAP: Recover from Bus Busy condition



From shubhrajyoti at ti.com  Thu Mar  8 08:18:00 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:48:00 +0530
Subject: [PATCHv2 08/13] OMAP: I2C: Fix the error handling
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-9-git-send-email-shubhrajyoti@ti.com>

Currently in probe
      pm_runtime_put(dev->dev);

...
        /* i2c device drivers may be active on return from add_adapter() */
        adap->nr = pdev->id;
        r = i2c_add_numbered_adapter(adap);
        if (r) {
                dev_err(dev->dev, "failure adding adapter\n");
                goto err_free_irq;
        }
...

        return 0;

err_free_irq:
        free_irq(dev->irq, dev);
err_unuse_clocks:
        omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
        pm_runtime_put(dev->dev);

This may access the i2c registers without the clocks.
Attempting to fix the same by moving the pm_rintime_put after the error check.

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index dd4e296..e12144e 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1095,8 +1095,6 @@ omap_i2c_probe(struct platform_device *pdev)
 	dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
 		 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
 
-	pm_runtime_put(dev->dev);
-
 	adap = &dev->adapter;
 	i2c_set_adapdata(adap, dev);
 	adap->owner = THIS_MODULE;
@@ -1116,6 +1114,8 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	of_i2c_register_devices(adap);
 
+	pm_runtime_put(dev->dev);
+
 	return 0;
 
 err_free_irq:
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:17:58 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:47:58 +0530
Subject: [PATCHv2 06/13] OMAP: I2C: Fix the mismatch of pm_runtime enable and
 disable
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-7-git-send-email-shubhrajyoti@ti.com>

Currently the i2c driver calls the pm_runtime_enable and never
the disable. This may cause a warning when pm_runtime_enable
checks for the count match.Attempting to fix the same by calling
pm_runtime_disable in the error and the remove path.

Cc: Kevin Hilman <khilman at ti.com>
Cc: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 98720c9..99b14d3 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1124,6 +1124,7 @@ err_unuse_clocks:
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 	pm_runtime_put(dev->dev);
 	iounmap(dev->base);
+	pm_runtime_disable(&pdev->dev);
 err_free_mem:
 	platform_set_drvdata(pdev, NULL);
 	kfree(dev);
@@ -1144,6 +1145,7 @@ omap_i2c_remove(struct platform_device *pdev)
 	free_irq(dev->irq, dev);
 	i2c_del_adapter(&dev->adapter);
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
+	pm_runtime_disable(&pdev->dev);
 	iounmap(dev->base);
 	kfree(dev);
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:17:59 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:47:59 +0530
Subject: [PATCHv2 07/13] OMAP: I2C: Optimise the remove code
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-8-git-send-email-shubhrajyoti@ti.com>

The omap_i2c_remove function may not be needed after
device exit so the memory could be freed.

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 99b14d3..dd4e296 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1134,8 +1134,7 @@ err_release_region:
 	return r;
 }
 
-static int
-omap_i2c_remove(struct platform_device *pdev)
+static int __devexit omap_i2c_remove(struct platform_device *pdev)
 {
 	struct omap_i2c_dev	*dev = platform_get_drvdata(pdev);
 	struct resource		*mem;
@@ -1228,7 +1227,7 @@ static struct dev_pm_ops omap_i2c_pm_ops = {
 
 static struct platform_driver omap_i2c_driver = {
 	.probe		= omap_i2c_probe,
-	.remove		= omap_i2c_remove,
+	.remove		= __devexit_p(omap_i2c_remove),
 	.driver		= {
 		.name	= "omap_i2c",
 		.owner	= THIS_MODULE,
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:18:04 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:48:04 +0530
Subject: [PATCHv2 12/13] I2C : OMAP : Fix the crash in i2c remove
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-13-git-send-email-shubhrajyoti@ti.com>

    In omap_i2c_remove we are accessing the I2C_CON register without
    enabling the clocks. Fix the same by enabling the clocks and disabling
    it.
    This fixes the following crash.
    [  154.723022] ------------[ cut here ]------------
    [  154.725677] WARNING: at arch/arm/mach-omap2/omap_l3_noc.c:112 l3_interrupt_handler+0x1b4/0x1c4()
    [  154.725677] L3 custom error: MASTER:MPU TARGET:L4 PER2
    [  154.742614] Modules linked in: i2c_omap(-)
    [  154.746948] Backtrace:
    [  154.746948] [<c0013078>] (dump_backtrace+0x0/0x110) from [<c026c158>] (dump_stack+0x18/0x1c)
    [  154.752716]  r6:00000070 r5:c002c43c r4:df9b9e98 r3:df9b8000
    [  154.764465] [<c026c140>] (dump_stack+0x0/0x1c) from [<c0041a2c>] (warn_slowpath_common+0x5c/0x6c)
    [  154.768341] [<c00419d0>] (warn_slowpath_common+0x0/0x6c) from [<c0041ae0>] (warn_slowpath_fmt+0x38/0x40)
    [  154.776153]  r8:00000180 r7:c0361594 r6:c0379b48 r5:00080003 r4:e0838b00
    [  154.790771] r3:00000009
    [  154.791778] [<c0041aa8>] (warn_slowpath_fmt+0x0/0x40) from [<c002c43c>] (l3_interrupt_handler+0x1b4/0x1c4)
    [  154.803710]  r3:c0361598 r2:c02ef74c
    [  154.807403] [<c002c288>] (l3_interrupt_handler+0x0/0x1c4) from [<c0085f44>] (handle_irq_event_percpu+0x58/0
    [  154.818237]  r8:0000002a r7:00000000 r6:00000000 r5:df808054 r4:df8893c0
    [  154.825378] [<c0085eec>] (handle_irq_event_percpu+0x0/0x188) from [<c00860b8>] (handle_irq_event+0x44/0x64)
    [  154.835662] [<c0086074>] (handle_irq_event+0x0/0x64) from [<c0088ec0>] (handle_fasteoi_irq+0xa4/0x10c)
    [  154.845458]  r6:0000002a r5:df808054 r4:df808000 r3:c034a150
    [  154.846466] [<c0088e1c>] (handle_fasteoi_irq+0x0/0x10c) from [<c0085ed0>] (generic_handle_irq+0x30/0x38)
    [  154.854278]  r5:c034aa48 r4:0000002a
    [  154.862091] [<c0085ea0>] (generic_handle_irq+0x0/0x38) from [<c000fd38>] (handle_IRQ+0x60/0xc0)
    [  154.874450]  r4:c034ea70 r3:000001f8
    [  154.878234] [<c000fcd8>] (handle_IRQ+0x0/0xc0) from [<c0008478>] (gic_handle_irq+0x20/0x5c)
    [  154.887023]  r7:ffffff40 r6:df9b9fb0 r5:c034e2b4 r4:0000001a
    [  154.887054] [<c0008458>] (gic_handle_irq+0x0/0x5c) from [<c000ea80>] (__irq_usr+0x40/0x60)
    [  154.901153] Exception stack(0xdf9b9fb0 to 0xdf9b9ff8)
    [  154.907104] 9fa0:                                     beaf1f04 4006be00 0000000f 0000000c
    [  154.915710] 9fc0: 4006c000 00000000 00008034 ffffff40 00000007 00000000 00000000 0007b8d7
    [  154.916778] 9fe0: 00000000 beaf1b68 0000d23c 4005baf0 80000010 ffffffff
    [  154.931335]  r6:ffffffff r5:80000010 r4:4005baf0 r3:beaf1f04
    [  154.937316] ---[ end trace 1b75b31a2719ed21 ]--

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index f454041..47a94cf 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -1134,7 +1134,9 @@ static int __devexit omap_i2c_remove(struct platform_device *pdev)
 
 	free_irq(dev->irq, dev);
 	i2c_del_adapter(&dev->adapter);
+	pm_runtime_get_sync(&pdev->dev);
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
+	pm_runtime_put(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
 	return 0;
 }
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:18:03 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:48:03 +0530
Subject: [PATCHv2 11/13] OMAP : I2C : use devm_* functions
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-12-git-send-email-shubhrajyoti@ti.com>

The various devm_ functions allocate memory that is released when a driver
detaches. This patch uses devm_kzalloc, devm_request_mem_region and
devm_ioremap for data that is allocated in the probe function of a platform
device and is only freed in the remove function.

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   29 +++++++++--------------------
 1 files changed, 9 insertions(+), 20 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 43c22a7..f454041 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -995,17 +995,17 @@ omap_i2c_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	ioarea = request_mem_region(mem->start, resource_size(mem),
-			pdev->name);
+	ioarea = devm_request_mem_region(&pdev->dev, mem->start,
+			resource_size(mem), pdev->name);
 	if (!ioarea) {
 		dev_err(&pdev->dev, "I2C region already claimed\n");
 		return -EBUSY;
 	}
 
-	dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
+	dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
 	if (!dev) {
-		r = -ENOMEM;
-		goto err_release_region;
+		dev_err(&pdev->dev, "Menory allocation failed\n");
+		return -ENOMEM;
 	}
 
 	match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
@@ -1029,11 +1029,10 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	dev->dev = &pdev->dev;
 	dev->irq = irq->start;
-	dev->base = ioremap(mem->start, resource_size(mem));
-	if (!dev->base) {
-		r = -ENOMEM;
-		goto err_free_mem;
-	}
+	dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
+	if (!dev->base)
+		return -ENOMEM;
+
 
 	platform_set_drvdata(pdev, dev);
 
@@ -1121,13 +1120,8 @@ err_free_irq:
 err_unuse_clocks:
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 	pm_runtime_put(dev->dev);
-	iounmap(dev->base);
 	pm_runtime_disable(&pdev->dev);
-err_free_mem:
 	platform_set_drvdata(pdev, NULL);
-	kfree(dev);
-err_release_region:
-	release_mem_region(mem->start, resource_size(mem));
 
 	return r;
 }
@@ -1135,7 +1129,6 @@ err_release_region:
 static int __devexit omap_i2c_remove(struct platform_device *pdev)
 {
 	struct omap_i2c_dev	*dev = platform_get_drvdata(pdev);
-	struct resource		*mem;
 
 	platform_set_drvdata(pdev, NULL);
 
@@ -1143,10 +1136,6 @@ static int __devexit omap_i2c_remove(struct platform_device *pdev)
 	i2c_del_adapter(&dev->adapter);
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 	pm_runtime_disable(&pdev->dev);
-	iounmap(dev->base);
-	kfree(dev);
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	release_mem_region(mem->start, resource_size(mem));
 	return 0;
 }
 
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:18:02 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:48:02 +0530
Subject: [PATCHv2 10/13] I2C: OMAP: Don't check if
 wait_for_completion_timeout() returns less than zero
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-11-git-send-email-shubhrajyoti@ti.com>

By definition, wait_for_completion_timeout() returns an unsigned value and
therefore, it is not necessary to check if the return value is less than zero
as this is not possible.

This is based on a patch from Jon Hunter <jon-hunter at ti.com>
Changes from his patch
- Declare a long as the wait_for_completion_timeout returns long.

Cc : Jon Hunter <jon-hunter at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
Original patch is
http://git.omapzoom.org/?p=kernel/omap.git;a=commitdiff;h=ea02cece7b0000bc736e60c4188a11aaa74bc6e6

 drivers/i2c/busses/i2c-omap.c |   10 ++++------
 1 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index ed22e67..43c22a7 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -502,7 +502,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 			     struct i2c_msg *msg, int stop)
 {
 	struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
-	int r;
+	unsigned long timeout;
 	u16 w;
 
 	dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
@@ -570,12 +570,10 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 	 * REVISIT: We should abort the transfer on signals, but the bus goes
 	 * into arbitration and we're currently unable to recover from it.
 	 */
-	r = wait_for_completion_timeout(&dev->cmd_complete,
-					OMAP_I2C_TIMEOUT);
+	timeout = wait_for_completion_timeout(&dev->cmd_complete,
+						OMAP_I2C_TIMEOUT);
 	dev->buf_len = 0;
-	if (r < 0)
-		return r;
-	if (r == 0) {
+	if (timeout == 0) {
 		dev_err(dev->dev, "controller timed out\n");
 		omap_i2c_init(dev);
 		omap_i2c_reset(dev);
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:18:05 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:48:05 +0530
Subject: [PATCHv2 13/13] OMAP: I2C: Handle error check for pm runtime
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-14-git-send-email-shubhrajyoti@ti.com>

If PM runtime get_sync fails return with the error
so that no further reads/writes goes through the interface.
This will avoid possible abort.

Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   13 ++++++++++---
 1 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 47a94cf..293e056 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -616,7 +616,9 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 	int i;
 	int r;
 
-	pm_runtime_get_sync(dev->dev);
+	r = pm_runtime_get_sync(dev->dev);
+	if (r < 0)
+		return r;
 
 	r = omap_i2c_wait_for_bb(dev);
 	if (r < 0)
@@ -1044,7 +1046,9 @@ omap_i2c_probe(struct platform_device *pdev)
 		dev->regs = (u8 *)reg_map_ip_v1;
 
 	pm_runtime_enable(dev->dev);
-	pm_runtime_get_sync(dev->dev);
+	r = pm_runtime_get_sync(dev->dev);
+	if (r < 0)
+		return r;
 
 	dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 
@@ -1129,12 +1133,15 @@ err_unuse_clocks:
 static int __devexit omap_i2c_remove(struct platform_device *pdev)
 {
 	struct omap_i2c_dev	*dev = platform_get_drvdata(pdev);
+	int ret;
 
 	platform_set_drvdata(pdev, NULL);
 
 	free_irq(dev->irq, dev);
 	i2c_del_adapter(&dev->adapter);
-	pm_runtime_get_sync(&pdev->dev);
+	ret = pm_runtime_get_sync(&pdev->dev);
+	if (ret < 0)
+		return ret;
 	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 	pm_runtime_put(&pdev->dev);
 	pm_runtime_disable(&pdev->dev);
-- 
1.7.1



From shubhrajyoti at ti.com  Thu Mar  8 08:18:01 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Thu, 8 Mar 2012 18:48:01 +0530
Subject: [PATCHv2 09/13] I2C: OMAP: Correct I2C revision for OMAP3
In-Reply-To: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
References: <1331212685-6524-1-git-send-email-shubhrajyoti@ti.com>
Message-ID: <1331212685-6524-10-git-send-email-shubhrajyoti@ti.com>

From: Jon Hunter <jon-hunter at ti.com>

The OMAP3530 is based upon the same silicon as the OMAP3430 and so the I2C
revision is the same for 3430 and 3530. However, the OMAP3630 device has the
same I2C revision as OMAP4. Correct the revision definition to reflect this.

This patch is based on work done by Jon Hunter <jon-hunter at ti.com>
Changes from his patch
- Update OMAP_I2C_REV_ON_3430 also to reflect that it is same as 3530

Signed-off-by: Jon Hunter <jon-hunter at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 drivers/i2c/busses/i2c-omap.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e12144e..ed22e67 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -50,8 +50,8 @@
 
 /* I2C controller revisions present on specific hardware */
 #define OMAP_I2C_REV_ON_2430		0x36
-#define OMAP_I2C_REV_ON_3430		0x3C
-#define OMAP_I2C_REV_ON_3530_4430	0x40
+#define OMAP_I2C_REV_ON_3430_3530	0x3C
+#define OMAP_I2C_REV_ON_3630_4430	0x40
 
 /* timeout waiting for the controller to respond */
 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
@@ -298,7 +298,7 @@ static int omap_i2c_reset(struct omap_i2c_dev *dev)
 			omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
 					   SYSC_AUTOIDLE_MASK);
 
-		} else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
+		} else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
 			dev->syscstate = SYSC_AUTOIDLE_MASK;
 			dev->syscstate |= SYSC_ENAWAKEUP_MASK;
 			dev->syscstate |= (SYSC_IDLEMODE_SMART <<
@@ -1051,7 +1051,7 @@ omap_i2c_probe(struct platform_device *pdev)
 
 	dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 
-	if (dev->rev <= OMAP_I2C_REV_ON_3430)
+	if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
 		dev->errata |= I2C_OMAP3_1P153;
 
 	if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
@@ -1069,7 +1069,7 @@ omap_i2c_probe(struct platform_device *pdev)
 
 		dev->fifo_size = (dev->fifo_size / 2);
 
-		if (dev->rev >= OMAP_I2C_REV_ON_3530_4430)
+		if (dev->rev >= OMAP_I2C_REV_ON_3630_4430)
 			dev->b_hw = 0; /* Disable hardware fixes */
 		else
 			dev->b_hw = 1; /* Enable hardware fixes */
-- 
1.7.1



From alexg at meprolight.com  Thu Mar  8 08:43:03 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Thu, 8 Mar 2012 15:43:03 +0200
Subject: I.MX35 PDK
In-Reply-To: <Pine.LNX.4.64.1203081225290.29847@axis700.grange>
References: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A28@MEP-EXCH.meprolight.com>,
 <Pine.LNX.4.64.1203081225290.29847@axis700.grange>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8914@MEP-EXCH.meprolight.com>

Hi Guennadi,

Thanks for you comments...

>>>Hi Alex

>>>Why is the cc-list mangled again? Why is the V4L list dropped again?
>>>What's so difficult about hitting the "reply-to-all" button?

 You are absolutely right, I hope that now the cc-list valid.

> Hi Fabio,
>
> Thanks for you response...
>
> > in spite of this I get from ov2640 driver error
> > Here Linux Kernel boot message:
> >
> > "Linux video capture interface: v2.00
> > soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
> > mx3-camera mx3-camera.0: MX3 Camera driver attached to camera 0
> > ov2640 0-0030: Product ID error fb:fb"
> >
> > I cannot understand what the problem is, if someone tested this?
>
> >>Looks like a I2C issue.
>
> >>Check the I2C1 pad settings in the mainline kernel.
>
> >>On FSL kernel we have:
>
> #<<define PAD_CONFIG (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
> >>PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain)
>
>       <<switch (i2c_num) {
>       <<case 0:
>               <<mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
>               <<mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
>
>               <<mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, PAD_CONFIG);
>               <<mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, PAD_CONFIG);
>
> >>Also check if you are getting the proper voltage levels at the I2C1 lines.
>
> Yes this I2C problem, all I2C slave device need response to Host CPU by pulls I2C data bus to low, in other words generate ACK, the clock pulse for the acknowledge bit is always created by the bus master.
>
> In this case, the camera tries to reset the data bus and generate an ACK, but the voltage drops to the area of two volts, although it should be reset to zero.
> I replaced R172 with 10K on CPU board and got a good result, but there are other surprises
>
> Linux video capture interface: v2.00
> soc-camera-pdrv soc-camera-pdrv.0: Probing soc-camera-pdrv.0
> mx3-camera mx3-camera.0: MX3 Camera driver attached to camera 0
> ov2640 0-0030: ov2640 Product ID 26:42 Manufacturer ID 7f:a2
> i2c i2c-0: OV2640 Probed
> mx3-camera mx3-camera.0: MX3 Camera driver detached from camera 0
> dmaengine: failed to get dma1chan0: (-22)
> dmaengine: failed to get dma1chan1: (-22)
> dmaengine: failed to get dma1chan2: (-22)
> dmaengine: failed to get dma1chan3: (-22)

>>>First of all it shows, that you're not using the newest kernel:

>>>http://thread.gmane.org/gmane.linux.ports.sh.devel/11508

I use Linux version 3.3.0-rc6 it contains the changes.

>>>Secondly, as Fabio just pointed out, these messages are not fatal, which
>>>is also the reason, why I changed their priority to "debug"

Ok

>>>Please, describe the actual problem, that you're getting (if any) and do
>>>add the v4l list back to the list of recipients!

At this stage, for me the problem of this type are actual, for the simple reason that I see it the first time.
Thanks for support and patience :-) 

> What is the problem?
> Guennadi please help me understand
>

Regards, 
Alex Gershgorin
 


From robherring2 at gmail.com  Thu Mar  8 09:12:31 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 08 Mar 2012 08:12:31 -0600
Subject: [PATCH 5/6] ARM: at91: add ram controller DT support
In-Reply-To: <20120308061324.GE27213@game.jcrosoft.org>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <1330718048-9314-5-git-send-email-plagnioj@jcrosoft.com>
 <4F57BDCE.1050708@gmail.com> <20120308061324.GE27213@game.jcrosoft.org>
Message-ID: <4F58BE4F.5080009@gmail.com>

On 03/08/2012 12:13 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>> index a297a77..88e43d5 100644
>>> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>> @@ -55,11 +55,6 @@
>>>  #define AT91SAM9X5_BASE_USART2	0xf8024000
>>>  
>>>  /*
>>> - * System Peripherals
>>> - */
>>> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
>>> -
>>> -/*
>>>   * Base addresses for early serial code (uncompress.h)
>>>   */
>>>  #define AT91_DBGU	AT91_BASE_DBGU0
>>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
>>> index 3e48b59..f86450d 100644
>>> --- a/arch/arm/mach-at91/setup.c
>>> +++ b/arch/arm/mach-at91/setup.c
>>> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
>>>  	of_node_put(np);
>>>  }
>>>  
>>> +static struct of_device_id ramc_ids[] = {
>>> +	{ .compatible = "atmel,at91sam9260-sdramc" },
>>> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
>>> +	{ /*sentinel*/ }
>>> +};
>>> +
>>> +static void at91_dt_ramc(void)
>>> +{
>>> +	struct device_node *np;
>>> +
>>> +	np = of_find_matching_node(NULL, ramc_ids);
>>> +	if (!np)
>>> +		panic("unable to find compatible ram conroller node in dtb\n");
>>
>> You really can't boot if this fails? A WARN is better if it allows you
>> to boot until at least your console is actually up.
> if the restart is called you will have a oops so no it's a basic mandatory
> device on at91
> 

But you may never see the panic message because your console is not up.
If you WARN and can continue to boot, then the user can see the problem
and fix it. Otherwise you get nothing and have to go rebuild and turn on
earlyprintk.

Rob



From plagnioj at jcrosoft.com  Thu Mar  8 09:10:00 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 8 Mar 2012 15:10:00 +0100
Subject: [PATCH 5/6] ARM: at91: add ram controller DT support
In-Reply-To: <4F58BE4F.5080009@gmail.com>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <1330718048-9314-5-git-send-email-plagnioj@jcrosoft.com>
 <4F57BDCE.1050708@gmail.com>
 <20120308061324.GE27213@game.jcrosoft.org>
 <4F58BE4F.5080009@gmail.com>
Message-ID: <20120308141000.GF27213@game.jcrosoft.org>

On 08:12 Thu 08 Mar     , Rob Herring wrote:
> On 03/08/2012 12:13 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>> index a297a77..88e43d5 100644
> >>> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>> @@ -55,11 +55,6 @@
> >>>  #define AT91SAM9X5_BASE_USART2	0xf8024000
> >>>  
> >>>  /*
> >>> - * System Peripherals
> >>> - */
> >>> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
> >>> -
> >>> -/*
> >>>   * Base addresses for early serial code (uncompress.h)
> >>>   */
> >>>  #define AT91_DBGU	AT91_BASE_DBGU0
> >>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> >>> index 3e48b59..f86450d 100644
> >>> --- a/arch/arm/mach-at91/setup.c
> >>> +++ b/arch/arm/mach-at91/setup.c
> >>> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
> >>>  	of_node_put(np);
> >>>  }
> >>>  
> >>> +static struct of_device_id ramc_ids[] = {
> >>> +	{ .compatible = "atmel,at91sam9260-sdramc" },
> >>> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
> >>> +	{ /*sentinel*/ }
> >>> +};
> >>> +
> >>> +static void at91_dt_ramc(void)
> >>> +{
> >>> +	struct device_node *np;
> >>> +
> >>> +	np = of_find_matching_node(NULL, ramc_ids);
> >>> +	if (!np)
> >>> +		panic("unable to find compatible ram conroller node in dtb\n");
> >>
> >> You really can't boot if this fails? A WARN is better if it allows you
> >> to boot until at least your console is actually up.
> > if the restart is called you will have a oops so no it's a basic mandatory
> > device on at91
> > 
> 
> But you may never see the panic message because your console is not up.
> If you WARN and can continue to boot, then the user can see the problem
> and fix it. Otherwise you get nothing and have to go rebuild and turn on
> earlyprintk.
yeah agreed but if the restart id use before the console is enable you will
have the same issue. the ramc controller are basic device so people usally
don't touch it except you add a SoC support.

so I prefer to panic

Best Regards,
J.


From plagnioj at jcrosoft.com  Thu Mar  8 09:18:47 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 8 Mar 2012 15:18:47 +0100
Subject: [PATCH v10] Regulator: Add Anatop regulator driver
In-Reply-To: <1331200744-5986-1-git-send-email-paul.liu@linaro.org>
References: <1331200744-5986-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120308141847.GG27213@game.jcrosoft.org>

On 17:59 Thu 08 Mar     , Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is an integrated regulator inside i.MX6 SoC.
> There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
> And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
> This patch adds the Anatop regulator driver.
> 
> Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Acked-by: Shawn Guo <shawn.guo at linaro.org>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Liam Girdwood <lrg at ti.com>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Axel Lin <axel.lin at gmail.com>
> ---
>  .../bindings/regulator/anatop-regulator.txt        |   28 +++
>  drivers/regulator/Kconfig                          |    8 +
>  drivers/regulator/Makefile                         |    1 +
>  drivers/regulator/anatop-regulator.c               |  236 ++++++++++++++++++++
>  4 files changed, 273 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.txt
>  create mode 100644 drivers/regulator/anatop-regulator.c
> 
> diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
> new file mode 100644
> index 0000000..73363e76
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
> @@ -0,0 +1,28 @@
> +Anatop Voltage regulators
> +
> +Required properties:
> +- compatible: Must be "fsl,anatop-regulator"
> +- anatop-vol-bit-shift: Bit shift for the register
> +- anatop-vol-bit-width: Number of bits used in the register
> +- anatop-min-bit-val: Minimum value of this register
> +- anatop-min-voltage: Minimum voltage of this regulator
> +- anatop-max-voltage: Maximum voltage of this regulator
> +
> +Any property defined as part of the core regulator
> +binding, defined in regulator.txt, can also be used.
> +
> +Example:
> +
> +	reg_vddpu: regulator-vddpu at 140 {
> +		compatible = "fsl,anatop-regulator";
> +		regulator-name = "vddpu";
> +		regulator-min-microvolt = <725000>;
> +		regulator-max-microvolt = <1300000>;
> +		regulator-always-on;
> +		reg = <0x140>;
> +		anatop-vol-bit-shift = <9>;
> +		anatop-vol-bit-width = <5>;
> +		anatop-min-bit-val = <1>;
> +		anatop-min-voltage = <725000>;
> +		anatop-max-voltage = <1300000>;
> +	};
> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> index 7a61b17..3857209 100644
> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -213,6 +213,14 @@ config REGULATOR_PCAP
>  	 This driver provides support for the voltage regulators of the
>  	 PCAP2 PMIC.
>  
> +config REGULATOR_ANATOP
> +	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
> +	depends on MFD_ANATOP
> +	help
> +	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
> +	  regulators. It is recommended that this option be
> +	  enabled on i.MX6 platform.
> +
>  config REGULATOR_MC13XXX_CORE
>  	tristate
>  
> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
> index 503bac8..8440871 100644
> --- a/drivers/regulator/Makefile
> +++ b/drivers/regulator/Makefile
> @@ -48,5 +48,6 @@ obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
>  obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
>  obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
>  obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
> +obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
>  
>  ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
> diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
> new file mode 100644
> index 0000000..133a17b
> --- /dev/null
> +++ b/drivers/regulator/anatop-regulator.c
> @@ -0,0 +1,236 @@
> +/*
> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> +
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> +
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + */
> +
> +#include <linux/slab.h>
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/mfd/anatop.h>
> +#include <linux/regulator/driver.h>
> +#include <linux/regulator/of_regulator.h>
> +
> +struct anatop_regulator {
> +	const char *name;
> +	u32 control_reg;
> +	struct anatop *mfd;
> +	int vol_bit_shift;
> +	int vol_bit_width;
> +	int min_bit_val;
> +	int min_voltage;
> +	int max_voltage;
> +	struct regulator_desc rdesc;
> +	struct regulator_init_data *initdata;
> +};
> +
> +static int anatop_set_voltage(struct regulator_dev *reg, int min_uV,
> +				  int max_uV, unsigned *selector)
> +{
> +	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
> +	u32 val, sel;
> +	int uv;
> +
> +	uv = min_uV;
> +	dev_dbg(&reg->dev, "%s: uv %d, min %d, max %d\n", __func__,
> +		uv, anatop_reg->min_voltage,
> +		anatop_reg->max_voltage);
> +
> +	if (uv < anatop_reg->min_voltage) {
> +		if (max_uV > anatop_reg->min_voltage)
> +			uv = anatop_reg->min_voltage;
> +		else
> +			return -EINVAL;
> +	}
> +
> +	if (anatop_reg->control_reg) {
> +		sel = (uv - anatop_reg->min_voltage) / 25000;
> +		if (sel * 25000 + anatop_reg->min_voltage
> +		    > anatop_reg->max_voltage)
> +			return -EINVAL;
> +		val = anatop_reg->min_bit_val + sel;
> +		*selector = sel;
> +		dev_dbg(&reg->dev, "%s: calculated val %d\n", __func__, val);
> +		anatop_set_bits(anatop_reg->mfd,
> +				anatop_reg->control_reg,
> +				anatop_reg->vol_bit_shift,
> +				anatop_reg->vol_bit_width,
> +				val);
> +		return 0;
> +	} else {
> +		return -ENOTSUPP;
> +	}
invert the test to make the code more readable
> +}
> +
> +static int anatop_get_voltage_sel(struct regulator_dev *reg)
> +{
> +	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
> +	int selector;
> +
> +	if (anatop_reg->control_reg) {
> +		u32 val = anatop_get_bits(anatop_reg->mfd,
> +					  anatop_reg->control_reg,
> +					  anatop_reg->vol_bit_shift,
> +					  anatop_reg->vol_bit_width);
> +		selector = val - anatop_reg->min_bit_val;
> +		return selector;
why do you need selector
> +	} else {
> +		return -ENOTSUPP;
> +	}
invert the test to make the code more readable
> +}
> +
> +static int anatop_list_voltage(struct regulator_dev *reg, unsigned selector)
> +{
> +	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
> +	int uv;
> +
> +	uv = anatop_reg->min_voltage + selector * 25000;
> +	dev_dbg(&reg->dev, "vddio = %d, selector = %u\n", uv, selector);
> +
> +	return uv;
> +}
> +
> +static struct regulator_ops anatop_rops = {
> +	.set_voltage     = anatop_set_voltage,
> +	.get_voltage_sel = anatop_get_voltage_sel,
> +	.list_voltage    = anatop_list_voltage,
> +};
> +
> +static int __devinit anatop_regulator_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
you set a dev var but use &pdev->dev most of the time
> +	struct device_node *np = dev->of_node;
> +	struct regulator_desc *rdesc;
> +	struct regulator_dev *rdev;
> +	struct anatop_regulator *sreg;
> +	struct regulator_init_data *initdata;
> +	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
> +	int ret = 0;
> +
> +	initdata = of_get_regulator_init_data(dev, np);
> +	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
> +	if (!sreg)
> +		return -ENOMEM;
> +	sreg->initdata = initdata;
> +	sreg->name = kstrdup(of_get_property(np, "regulator-name", NULL),
> +			     GFP_KERNEL);
> +	rdesc = &sreg->rdesc;
> +	memset(rdesc, 0, sizeof(*rdesc));
> +	rdesc->name = sreg->name;
> +	rdesc->ops = &anatop_rops;
> +	rdesc->type = REGULATOR_VOLTAGE;
> +	rdesc->owner = THIS_MODULE;
> +	sreg->mfd = anatopmfd;
> +	if (of_property_read_u32(np, "reg", &sreg->control_reg)) {
> +		dev_err(&pdev->dev, "no reg property set\n");
> +		ret = -ENODEV;
why not return the err return by the read_u32 or atleast print it
> +		goto anatop_probe_end;
> +	}
> +	if (of_property_read_u32(np, "anatop-vol-bit-width",
> +				 &sreg->vol_bit_width)) {
> +		dev_err(&pdev->dev, "no anatop-vol-bit-width property set\n");
> +		ret = -ENODEV;
> +		goto anatop_probe_end;
> +	}
> +	if (of_property_read_u32(np, "anatop-vol-bit-shift",
> +				 &sreg->vol_bit_shift)) {
> +		dev_err(&pdev->dev, "no anatop-vol-bit-shift property set\n");
> +		ret = -ENODEV;
> +		goto anatop_probe_end;
> +	}
> +	if (of_property_read_u32(np, "anatop-min-bit-val",
> +				 &sreg->min_bit_val)) {
> +		dev_err(&pdev->dev, "no anatop-min-bit-val property set\n");
> +		ret = -ENODEV;
> +		goto anatop_probe_end;
> +	}
> +	if (of_property_read_u32(np, "anatop-min-voltage",
> +				 &sreg->min_voltage)) {
> +		dev_err(&pdev->dev, "no anatop-min-voltage property set\n");
> +		ret = -ENODEV;
> +		goto anatop_probe_end;
> +	}
> +	if (of_property_read_u32(np, "anatop-max-voltage",
> +				 &sreg->max_voltage)) {
> +		dev_err(&pdev->dev, "no anatop-max-voltage property set\n");
> +		ret = -ENODEV;
> +		goto anatop_probe_end;
> +	}
> +
> +	/* register regulator */
> +	rdev = regulator_register(rdesc, &pdev->dev,
> +				  initdata, sreg, pdev->dev.of_node);
> +	if (IS_ERR(rdev)) {
> +		dev_err(&pdev->dev, "failed to register %s\n",
> +			rdesc->name);
> +		ret = PTR_ERR(rdev);
> +		goto anatop_probe_end;
> +	}
> +
> +	platform_set_drvdata(pdev, rdev);
> +
> +anatop_probe_end:
> +	if (ret != 0 && sreg->name)
> +		kfree(sreg->name);
kfree can be called with a NULL pointer
> +	return ret;
> +}
> +
> +static int __devexit anatop_regulator_remove(struct platform_device *pdev)
> +{
> +	struct regulator_dev *rdev = platform_get_drvdata(pdev);
> +	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
> +	kfree(sreg->name);
> +	regulator_unregister(rdev);
return from the unregister
> +	return 0;
> +}
Best Regards,
J.


From B04825 at freescale.com  Thu Mar  8 09:45:12 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Thu, 8 Mar 2012 14:45:12 +0000
Subject: [PATCH v2 00/17] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <20120308131117.GE2499@S2101-09.ap.freescale.net>
References: <1330957865-19085-1-git-send-email-shawn.guo@linaro.org>
 <4F57ECC7.1040100@freescale.com>,
 <20120308131117.GE2499@S2101-09.ap.freescale.net>
Message-ID: <23552818-7136-47DD-A817-CB0EF5C805EF@freescale.com>

On Mar 8, 2012, at 7:11 AM, "Shawn Guo" <shawn.guo at linaro.org> wrote:

> What are the patches I can apply your ack?  Or every one in this series?

The whole series. I didn't test individual patches, so I don't know if any one of them is bad by itself.



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:20 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:20 +0100
Subject: [PATCH 00/11] ARM: tegra: Add PCIe device tree support
Message-ID: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>

This patch series adds support for device tree based probing of the PCIe
controller found on Tegra SoCs.

Patches 1 and 2 have already been posted by Grant and Mark respectively
but I've included them here for reference. Both patches are dependencies
for the subsequent patches.

Patches 3, 4 and 5 add support for obtaining the regulators required to
power the PCIe controller from the device tree. Patches 6 and 7 are
required to make some common PCI functions available after the init
phase because the deferred probing will postpone the probing of the PCIe
controller driver until that point.

Patches 8 and 9 make the PCIe controller code available as a driver and
add the corresponding platform devices to the boards that enable PCIe
(Harmony and TrimSlice). Patch 10 adds MSI support and patch 11 finally
adds a device tree binding with documentation.

The code in patch 10 (MSI support) is based on the Vibrante kernel and I
wasn't able to get a proper Signed-off-by or even copyright information.
Perhaps somebody at NVIDIA can find out?

Thierry

Grant Likely (1):
  drivercore: Add driver probe deferral mechanism

Mark Brown (1):
  regulator: Support driver probe deferral

Thierry Reding (9):
  regulator: fixed: Support driver probe deferral
  regulator: tps6586x: fix typo in debug message
  tps6586x: Add device-tree support
  PCI: Keep pci_fixup_irqs() around after init
  ARM: pci: Keep pci_common_init() around after init
  ARM: tegra: Move tegra_pcie_xclk_clamp() to PMC
  ARM: tegra: Rewrite PCIe support as a driver
  ARM: tegra: pcie: Add MSI support
  ARM: tegra: pcie: Add device tree support

 .../devicetree/bindings/pci/tegra-pcie.txt         |   23 +
 .../devicetree/bindings/regulator/tps6586x.txt     |   98 +++
 arch/arm/boot/dts/tegra20.dtsi                     |    8 +
 arch/arm/kernel/bios32.c                           |    4 +-
 arch/arm/mach-tegra/Kconfig                        |    1 +
 arch/arm/mach-tegra/board-harmony-pcie.c           |   38 +-
 arch/arm/mach-tegra/board-harmony.c                |    1 +
 arch/arm/mach-tegra/board-harmony.h                |    1 +
 arch/arm/mach-tegra/board-trimslice.c              |   16 +-
 arch/arm/mach-tegra/board.h                        |   11 +-
 arch/arm/mach-tegra/devices.c                      |   32 +
 arch/arm/mach-tegra/devices.h                      |    1 +
 arch/arm/mach-tegra/include/mach/iomap.h           |    6 +
 arch/arm/mach-tegra/include/mach/irqs.h            |    5 +-
 arch/arm/mach-tegra/pcie.c                         |  895 +++++++++++++++-----
 arch/arm/mach-tegra/pmc.c                          |   16 +
 arch/arm/mach-tegra/pmc.h                          |    1 +
 drivers/base/base.h                                |    1 +
 drivers/base/core.c                                |    2 +
 drivers/base/dd.c                                  |  138 ++-
 drivers/mfd/tps6586x.c                             |   66 ++
 drivers/pci/setup-irq.c                            |    4 +-
 drivers/regulator/core.c                           |    4 +-
 drivers/regulator/fixed.c                          |   14 +-
 drivers/regulator/tps6586x-regulator.c             |    4 +-
 include/linux/device.h                             |    5 +
 include/linux/errno.h                              |    1 +
 include/linux/mfd/tps6586x.h                       |    1 +
 28 files changed, 1136 insertions(+), 261 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/tegra-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/regulator/tps6586x.txt

-- 
1.7.9.3



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:25 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:25 +0100
Subject: [PATCH 05/11] tps6586x: Add device-tree support
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331218291-16119-6-git-send-email-thierry.reding@avionic-design.de>

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 .../devicetree/bindings/regulator/tps6586x.txt     |   98 ++++++++++++++++++++
 drivers/mfd/tps6586x.c                             |   66 +++++++++++++
 drivers/regulator/tps6586x-regulator.c             |    2 +-
 include/linux/mfd/tps6586x.h                       |    1 +
 4 files changed, 166 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/tps6586x.txt

diff --git a/Documentation/devicetree/bindings/regulator/tps6586x.txt b/Documentation/devicetree/bindings/regulator/tps6586x.txt
new file mode 100644
index 0000000..e8d2888
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/tps6586x.txt
@@ -0,0 +1,98 @@
+TPS6586x family of regulators
+
+Required properties:
+- compatible: "ti,tps6586x"
+- reg: I2C slave address
+- interrupts: the interrupt outputs of the controller
+- #gpio-cells: number of cells to describe a GPIO
+- gpio-controller: mark the device as a GPIO controller
+- regulators: list of regulators provided by this controller, must be in the
+  following order:
+    SM0, SM1, SM2, LDO0, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9
+
+Each regulator is defined using the standard binding for regulators.
+
+Example:
+
+	pmu: tps6586x at 34 {
+		compatible = "ti,tps6586x";
+		reg = <0x34>;
+		interrupts = <0 88 0x4>;
+
+		#gpio-cells = <2>;
+		gpio-controller;
+
+		regulators {
+			sm0_reg: sm0 {
+				regulator-min-microvolt = < 725000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sm1_reg: sm1 {
+				regulator-min-microvolt = < 725000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sm2_reg: sm2 {
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <4550000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo0_reg: ldo0 {
+				regulator-name = "PCIE CLK";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo1_reg: ldo1 {
+				regulator-min-microvolt = < 725000>;
+				regulator-max-microvolt = <1500000>;
+			};
+
+			ldo2_reg: ldo2 {
+				regulator-min-microvolt = < 725000>;
+				regulator-max-microvolt = <1500000>;
+			};
+
+			ldo3_reg: ldo3 {
+				regulator-min-microvolt = <1250000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo4_reg: ldo4 {
+				regulator-min-microvolt = <1700000>;
+				regulator-max-microvolt = <2475000>;
+			};
+
+			ldo5_reg: ldo5 {
+				regulator-min-microvolt = <1250000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo6_reg: ldo6 {
+				regulator-min-microvolt = <1250000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo7_reg: ldo7 {
+				regulator-min-microvolt = <1250000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo8_reg: ldo8 {
+				regulator-min-microvolt = <1250000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo9_reg: ldo9 {
+				regulator-min-microvolt = <1250000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index a5ddf31..71997d2 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -23,6 +23,7 @@
 #include <linux/slab.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
+#include <linux/regulator/of_regulator.h>
 
 #include <linux/mfd/core.h>
 #include <linux/mfd/tps6586x.h>
@@ -460,6 +461,7 @@ static int __devinit tps6586x_add_subdevs(struct tps6586x *tps6586x,
 
 		pdev->dev.parent = tps6586x->dev;
 		pdev->dev.platform_data = subdev->platform_data;
+		pdev->dev.of_node = subdev->of_node;
 
 		ret = platform_device_add(pdev);
 		if (ret) {
@@ -474,6 +476,66 @@ failed:
 	return ret;
 }
 
+#ifdef CONFIG_OF
+static struct tps6586x_platform_data *tps6586x_parse_dt(struct i2c_client *client)
+{
+	struct device_node *np = client->dev.of_node;
+	struct tps6586x_platform_data *pdata;
+	struct tps6586x_subdev_info *devs;
+	struct device_node *regulators;
+	struct device_node *child;
+	unsigned int num = 0;
+
+	regulators = of_find_node_by_name(np, "regulators");
+
+	for_each_child_of_node(regulators, child)
+		num++;
+
+	devs = devm_kzalloc(&client->dev, num * sizeof(*devs), GFP_KERNEL);
+	if (!devs)
+		return NULL;
+
+	num = 0;
+
+	for_each_child_of_node(regulators, child) {
+		struct regulator_init_data *init_data;
+
+		init_data = of_get_regulator_init_data(&client->dev, child);
+		if (!init_data)
+			dev_err(&client->dev,
+				"failed to parse DT for regulator %s\n",
+				child->name);
+
+		devs[num].name = "tps6586x-regulator";
+		devs[num].platform_data = init_data;
+		devs[num].of_node = child;
+		devs[num].id = num;
+		num++;
+	}
+
+	pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return NULL;
+
+	pdata->num_subdevs = num;
+	pdata->subdevs = devs;
+	pdata->gpio_base = -1;
+	pdata->irq_base = -1;
+
+	return pdata;
+}
+
+static struct of_device_id tps6586x_of_match[] = {
+	{ .compatible = "ti,tps6586x", },
+	{ },
+};
+#else
+static struct tps6586x_platform_data *tps6586x_parse_dt(struct i2c_client *client)
+{
+	return NULL;
+}
+#endif
+
 static int __devinit tps6586x_i2c_probe(struct i2c_client *client,
 					const struct i2c_device_id *id)
 {
@@ -481,6 +543,9 @@ static int __devinit tps6586x_i2c_probe(struct i2c_client *client,
 	struct tps6586x *tps6586x;
 	int ret;
 
+	if (!pdata && client->dev.of_node)
+		pdata = tps6586x_parse_dt(client);
+
 	if (!pdata) {
 		dev_err(&client->dev, "tps6586x requires platform data\n");
 		return -ENOTSUPP;
@@ -573,6 +638,7 @@ static struct i2c_driver tps6586x_driver = {
 	.driver	= {
 		.name	= "tps6586x",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(tps6586x_of_match),
 	},
 	.probe		= tps6586x_i2c_probe,
 	.remove		= __devexit_p(tps6586x_i2c_remove),
diff --git a/drivers/regulator/tps6586x-regulator.c b/drivers/regulator/tps6586x-regulator.c
index 29b615c..f10a735 100644
--- a/drivers/regulator/tps6586x-regulator.c
+++ b/drivers/regulator/tps6586x-regulator.c
@@ -396,7 +396,7 @@ static int __devinit tps6586x_regulator_probe(struct platform_device *pdev)
 		return err;
 
 	rdev = regulator_register(&ri->desc, &pdev->dev,
-				  pdev->dev.platform_data, ri, NULL);
+				  pdev->dev.platform_data, ri, pdev->dev.of_node);
 	if (IS_ERR(rdev)) {
 		dev_err(&pdev->dev, "failed to register regulator %s\n",
 				ri->desc.name);
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
index b19176e..f350fd0 100644
--- a/include/linux/mfd/tps6586x.h
+++ b/include/linux/mfd/tps6586x.h
@@ -68,6 +68,7 @@ struct tps6586x_subdev_info {
 	int		id;
 	const char	*name;
 	void		*platform_data;
+	struct device_node *of_node;
 };
 
 struct tps6586x_platform_data {
-- 
1.7.9.3



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:21 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:21 +0100
Subject: [PATCH 01/11] drivercore: Add driver probe deferral mechanism
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331218291-16119-2-git-send-email-thierry.reding@avionic-design.de>

From: Grant Likely <grant.likely at secretlab.ca>

Allow drivers to report at probe time that they cannot get all the resources
required by the device, and should be retried at a later time.

This should completely solve the problem of getting devices
initialized in the right order.  Right now this is mostly handled by
mucking about with initcall ordering which is a complete hack, and
doesn't even remotely handle the case where device drivers are in
modules.  This approach completely sidesteps the issues by allowing
driver registration to occur in any order, and any driver can request
to be retried after a few more other drivers get probed.

v4: - Integrate Manjunath's addition of a separate workqueue
    - Change -EAGAIN to -EPROBE_DEFER for drivers to trigger deferral
    - Update comment blocks to reflect how the code really works
v3: - Hold off workqueue scheduling until late_initcall so that the bulk
      of driver probes are complete before we start retrying deferred devices.
    - Tested with simple use cases.  Still needs more testing though.
      Using it to get rid of the gpio early_initcall madness, or to replace
      the ASoC internal probe deferral code would be ideal.
v2: - added locking so it should no longer be utterly broken in that regard
    - remove device from deferred list at device_del time.
    - Still completely untested with any real use case, but has been
      boot tested.

Signed-off-by: Grant Likely <grant.likely at secretlab.ca>
[Cc list stripped in order not to get on people's nerves]
---
 drivers/base/base.h    |    1 +
 drivers/base/core.c    |    2 +
 drivers/base/dd.c      |  138 +++++++++++++++++++++++++++++++++++++++++++++++-
 include/linux/device.h |    5 ++
 include/linux/errno.h  |    1 +
 5 files changed, 146 insertions(+), 1 deletion(-)

diff --git a/drivers/base/base.h b/drivers/base/base.h
index b858dfd..2c13dea 100644
--- a/drivers/base/base.h
+++ b/drivers/base/base.h
@@ -105,6 +105,7 @@ extern void bus_remove_driver(struct device_driver *drv);
 
 extern void driver_detach(struct device_driver *drv);
 extern int driver_probe_device(struct device_driver *drv, struct device *dev);
+extern void driver_deferred_probe_del(struct device *dev);
 static inline int driver_match_device(struct device_driver *drv,
 				      struct device *dev)
 {
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 0841a36..946094f 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -649,6 +649,7 @@ void device_initialize(struct device *dev)
 {
 	dev->kobj.kset = devices_kset;
 	kobject_init(&dev->kobj, &device_ktype);
+	INIT_LIST_HEAD(&dev->deferred_probe);
 	INIT_LIST_HEAD(&dev->dma_pools);
 	mutex_init(&dev->mutex);
 	lockdep_set_novalidate_class(&dev->mutex);
@@ -1193,6 +1194,7 @@ void device_del(struct device *dev)
 	device_remove_file(dev, &uevent_attr);
 	device_remove_attrs(dev);
 	bus_remove_device(dev);
+	driver_deferred_probe_del(dev);
 
 	/*
 	 * Some platform devices are driven without driver attached
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index 142e3d600..442b764 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -28,6 +28,133 @@
 #include "base.h"
 #include "power/power.h"
 
+/*
+ * Deferred Probe infrastructure.
+ *
+ * Sometimes driver probe order matters, but the kernel doesn't always have
+ * dependency information which means some drivers will get probed before a
+ * resource it depends on is available.  For example, an SDHCI driver may
+ * first need a GPIO line from an i2c GPIO controller before it can be
+ * initialized.  If a required resource is not available yet, a driver can
+ * request probing to be deferred by returning -EPROBE_DEFER from its probe hook
+ *
+ * Deferred probe maintains two lists of devices, a pending list and an active
+ * list.  A driver returning -EPROBE_DEFER causes the device to be added to the
+ * pending list.  A successful driver probe will trigger moving all devices
+ * from the pending to the active list so that the workqueue will eventually
+ * retry them.
+ *
+ * The deferred_probe_mutex must be held any time the deferred_probe_*_list
+ * of the (struct device*)->deferred_probe pointers are manipulated
+ */
+static DEFINE_MUTEX(deferred_probe_mutex);
+static LIST_HEAD(deferred_probe_pending_list);
+static LIST_HEAD(deferred_probe_active_list);
+static struct workqueue_struct *deferred_wq;
+
+/**
+ * deferred_probe_work_func() - Retry probing devices in the active list.
+ */
+static void deferred_probe_work_func(struct work_struct *work)
+{
+	struct device *dev;
+	/*
+	 * This block processes every device in the deferred 'active' list.
+	 * Each device is removed from the active list and passed to
+	 * bus_probe_device() to re-attempt the probe.  The loop continues
+	 * until every device in the active list is removed and retried.
+	 *
+	 * Note: Once the device is removed from the list and the mutex is
+	 * released, it is possible for the device get freed by another thread
+	 * and cause a illegal pointer dereference.  This code uses
+	 * get/put_device() to ensure the device structure cannot disappear
+	 * from under our feet.
+	 */
+	mutex_lock(&deferred_probe_mutex);
+	while (!list_empty(&deferred_probe_active_list)) {
+		dev = list_first_entry(&deferred_probe_active_list,
+					typeof(*dev), deferred_probe);
+		list_del_init(&dev->deferred_probe);
+
+		get_device(dev);
+
+		/* Drop the mutex while probing each device; the probe path
+		 * may manipulate the deferred list */
+		mutex_unlock(&deferred_probe_mutex);
+		dev_dbg(dev, "Retrying from deferred list\n");
+		bus_probe_device(dev);
+		mutex_lock(&deferred_probe_mutex);
+
+		put_device(dev);
+	}
+	mutex_unlock(&deferred_probe_mutex);
+}
+static DECLARE_WORK(deferred_probe_work, deferred_probe_work_func);
+
+static void driver_deferred_probe_add(struct device *dev)
+{
+	mutex_lock(&deferred_probe_mutex);
+	if (list_empty(&dev->deferred_probe)) {
+		dev_dbg(dev, "Added to deferred list\n");
+		list_add(&dev->deferred_probe, &deferred_probe_pending_list);
+	}
+	mutex_unlock(&deferred_probe_mutex);
+}
+
+void driver_deferred_probe_del(struct device *dev)
+{
+	mutex_lock(&deferred_probe_mutex);
+	if (!list_empty(&dev->deferred_probe)) {
+		dev_dbg(dev, "Removed from deferred list\n");
+		list_del_init(&dev->deferred_probe);
+	}
+	mutex_unlock(&deferred_probe_mutex);
+}
+
+static bool driver_deferred_probe_enable = false;
+/**
+ * driver_deferred_probe_trigger() - Kick off re-probing deferred devices
+ *
+ * This functions moves all devices from the pending list to the active
+ * list and schedules the deferred probe workqueue to process them.  It
+ * should be called anytime a driver is successfully bound to a device.
+ */
+static void driver_deferred_probe_trigger(void)
+{
+	if (!driver_deferred_probe_enable)
+		return;
+
+	/* A successful probe means that all the devices in the pending list
+	 * should be triggered to be reprobed.  Move all the deferred devices
+	 * into the active list so they can be retried by the workqueue */
+	mutex_lock(&deferred_probe_mutex);
+	list_splice_tail_init(&deferred_probe_pending_list,
+			      &deferred_probe_active_list);
+	mutex_unlock(&deferred_probe_mutex);
+
+	/* Kick the re-probe thread.  It may already be scheduled, but
+	 * it is safe to kick it again. */
+	queue_work(deferred_wq, &deferred_probe_work);
+}
+
+/**
+ * deferred_probe_initcall() - Enable probing of deferred devices
+ *
+ * We don't want to get in the way when the bulk of drivers are getting probed.
+ * Instead, this initcall makes sure that deferred probing is delayed until
+ * late_initcall time.
+ */
+static int deferred_probe_initcall(void)
+{
+	deferred_wq = create_singlethread_workqueue("deferwq");
+	if (WARN_ON(!deferred_wq))
+		return -ENOMEM;
+
+	driver_deferred_probe_enable = true;
+	driver_deferred_probe_trigger();
+	return 0;
+}
+late_initcall(deferred_probe_initcall);
 
 static void driver_bound(struct device *dev)
 {
@@ -42,6 +169,11 @@ static void driver_bound(struct device *dev)
 
 	klist_add_tail(&dev->p->knode_driver, &dev->driver->p->klist_devices);
 
+	/* Make sure the device is no longer in one of the deferred lists
+	 * and kick off retrying all pending devices */
+	driver_deferred_probe_del(dev);
+	driver_deferred_probe_trigger();
+
 	if (dev->bus)
 		blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
 					     BUS_NOTIFY_BOUND_DRIVER, dev);
@@ -142,7 +274,11 @@ probe_failed:
 	driver_sysfs_remove(dev);
 	dev->driver = NULL;
 
-	if (ret != -ENODEV && ret != -ENXIO) {
+	if (ret == -EPROBE_DEFER) {
+		/* Driver requested deferred probing */
+		dev_info(dev, "Driver %s requests probe deferral\n", drv->name);
+		driver_deferred_probe_add(dev);
+	} else if (ret != -ENODEV && ret != -ENXIO) {
 		/* driver matched but the probe failed */
 		printk(KERN_WARNING
 		       "%s: probe of %s failed with error %d\n",
diff --git a/include/linux/device.h b/include/linux/device.h
index f62e216..22d6938 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -585,6 +585,10 @@ struct device_dma_parameters {
  * @mutex:	Mutex to synchronize calls to its driver.
  * @bus:	Type of bus device is on.
  * @driver:	Which driver has allocated this
+ * @deferred_probe: entry in deferred_probe_list which is used to retry the
+ * 		binding of drivers which were unable to get all the resources
+ * 		needed by the device; typically because it depends on another
+ * 		driver getting probed first.
  * @platform_data: Platform data specific to the device.
  * 		Example: For devices on custom boards, as typical of embedded
  * 		and SOC based hardware, Linux often uses platform_data to point
@@ -644,6 +648,7 @@ struct device {
 	struct bus_type	*bus;		/* type of bus device is on */
 	struct device_driver *driver;	/* which driver has allocated this
 					   device */
+	struct list_head	deferred_probe;
 	void		*platform_data;	/* Platform specific data, device
 					   core doesn't touch it */
 	struct dev_pm_info	power;
diff --git a/include/linux/errno.h b/include/linux/errno.h
index 4668583..2d09bfa 100644
--- a/include/linux/errno.h
+++ b/include/linux/errno.h
@@ -16,6 +16,7 @@
 #define ERESTARTNOHAND	514	/* restart if no handler.. */
 #define ENOIOCTLCMD	515	/* No ioctl command */
 #define ERESTART_RESTARTBLOCK 516 /* restart by calling sys_restart_syscall */
+#define EPROBE_DEFER	517	/* Driver requests probe retry */
 
 /* Defined for the NFSv3 protocol */
 #define EBADHANDLE	521	/* Illegal NFS file handle */
-- 
1.7.9.3



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:28 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:28 +0100
Subject: [PATCH 08/11] ARM: tegra: Move tegra_pcie_xclk_clamp() to PMC
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331218291-16119-9-git-send-email-thierry.reding@avionic-design.de>

The PMC code already accesses the PMC registers so it makes sense to
move this function there as well. While at it, rename the function to
tegra_pmc_pcie_xclk_clamp() for consistency.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 arch/arm/mach-tegra/pcie.c |   30 ++++--------------------------
 arch/arm/mach-tegra/pmc.c  |   16 ++++++++++++++++
 arch/arm/mach-tegra/pmc.h  |    1 +
 3 files changed, 21 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 7313059..7704af7a 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -42,6 +42,7 @@
 #include <mach/powergate.h>
 
 #include "board.h"
+#include "pmc.h"
 
 /* register definitions */
 #define AFI_OFFSET	0x3800
@@ -145,17 +146,6 @@
 #define  PADS_PLL_CTL_TXCLKREF_DIV10		(0 << 20)
 #define  PADS_PLL_CTL_TXCLKREF_DIV5		(1 << 20)
 
-/* PMC access is required for PCIE xclk (un)clamping */
-#define PMC_SCRATCH42		0x144
-#define PMC_SCRATCH42_PCX_CLAMP	(1 << 0)
-
-static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-
-#define pmc_writel(value, reg) \
-	__raw_writel(value, reg_pmc_base + (reg))
-#define pmc_readl(reg) \
-	__raw_readl(reg_pmc_base + (reg))
-
 /*
  * Tegra2 defines 1GB in the AXI address map for PCIe.
  *
@@ -680,18 +670,6 @@ static int tegra_pcie_enable_controller(void)
 	return;
 }
 
-static void tegra_pcie_xclk_clamp(bool clamp)
-{
-	u32 reg;
-
-	reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
-
-	if (clamp)
-		reg |= PMC_SCRATCH42_PCX_CLAMP;
-
-	pmc_writel(reg, PMC_SCRATCH42);
-}
-
 static void tegra_pcie_power_off(void)
 {
 	tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
@@ -699,7 +677,7 @@ static void tegra_pcie_power_off(void)
 	tegra_periph_reset_assert(tegra_pcie.pex_clk);
 
 	tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
-	tegra_pcie_xclk_clamp(true);
+	tegra_pmc_pcie_xclk_clamp(true);
 }
 
 static int tegra_pcie_power_regate(void)
@@ -708,7 +686,7 @@ static int tegra_pcie_power_regate(void)
 
 	tegra_pcie_power_off();
 
-	tegra_pcie_xclk_clamp(true);
+	tegra_pmc_pcie_xclk_clamp(true);
 
 	tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
 	tegra_periph_reset_assert(tegra_pcie.afi_clk);
@@ -722,7 +700,7 @@ static int tegra_pcie_power_regate(void)
 
 	tegra_periph_reset_deassert(tegra_pcie.afi_clk);
 
-	tegra_pcie_xclk_clamp(false);
+	tegra_pmc_pcie_xclk_clamp(false);
 
 	clk_enable(tegra_pcie.afi_clk);
 	clk_enable(tegra_pcie.pex_clk);
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 7af6a54..399dc3a 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -24,6 +24,10 @@
 #define PMC_CTRL		0x0
 #define PMC_CTRL_INTR_LOW	(1 << 17)
 
+/* PMC access is required for PCIE xclk (un)clamping */
+#define PMC_SCRATCH42		0x144
+#define PMC_SCRATCH42_PCX_CLAMP	(1 << 0)
+
 static inline u32 tegra_pmc_readl(u32 reg)
 {
 	return readl(IO_ADDRESS(TEGRA_PMC_BASE + reg));
@@ -74,3 +78,15 @@ void __init tegra_pmc_init(void)
 		val &= ~PMC_CTRL_INTR_LOW;
 	tegra_pmc_writel(val, PMC_CTRL);
 }
+
+void tegra_pmc_pcie_xclk_clamp(bool clamp)
+{
+	u32 reg;
+
+	reg = tegra_pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
+
+	if (clamp)
+		reg |= PMC_SCRATCH42_PCX_CLAMP;
+
+	tegra_pmc_writel(reg, PMC_SCRATCH42);
+}
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 8995ee4..2631c9a 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -19,5 +19,6 @@
 #define __MACH_TEGRA_PMC_H
 
 void tegra_pmc_init(void);
+void tegra_pmc_pcie_xclk_clamp(bool clamp);
 
 #endif
-- 
1.7.9.3



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:22 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:22 +0100
Subject: [PATCH 02/11] regulator: Support driver probe deferral
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331218291-16119-3-git-send-email-thierry.reding@avionic-design.de>

From: Mark Brown <broonie at opensource.wolfsonmicro.com>

If we fail to locate a requested regulator return -EPROBE_DEFER. If drivers
pass this error code through to their caller (which they really should)
then this will ensure that the probe is retried later when further devices
become available.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
[G,Manjunath Kondaiah removed in order not to bother him]
Acked-by: Grant Likely <grant.likely at secretlab.ca>
Acked-by: Liam Girdwood <lrg at ti.com>
---
 drivers/regulator/core.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 5a6b8ba..8a4b0a8 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -1198,7 +1198,7 @@ static struct regulator *_regulator_get(struct device *dev, const char *id,
 {
 	struct regulator_dev *rdev;
 	struct regulator_map *map;
-	struct regulator *regulator = ERR_PTR(-ENODEV);
+	struct regulator *regulator = ERR_PTR(-EPROBE_DEFER);
 	const char *devname = NULL;
 	int ret;
 
@@ -2926,7 +2926,7 @@ struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc,
 
 		if (!r) {
 			dev_err(dev, "Failed to find supply %s\n", supply);
-			ret = -ENODEV;
+			ret = -EPROBE_DEFER;
 			goto scrub;
 		}
 
-- 
1.7.9.3



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:23 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:23 +0100
Subject: [PATCH 03/11] regulator: fixed: Support driver probe deferral
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331218291-16119-4-git-send-email-thierry.reding@avionic-design.de>

If the specified GPIO is not found, return -EPROBE_DEFER. This will
cause the driver to be probed again later when the required GPIO may
have become available.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 drivers/regulator/fixed.c |   14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c
index 40f3803..35cec44 100644
--- a/drivers/regulator/fixed.c
+++ b/drivers/regulator/fixed.c
@@ -58,12 +58,19 @@ of_get_fixed_voltage_config(struct device *dev)
 	struct device_node *np = dev->of_node;
 	const __be32 *delay;
 	struct regulator_init_data *init_data;
+	int gpio;
+
+	gpio = of_get_named_gpio(np, "gpio", 0);
+	if (gpio < 0)
+		return ERR_PTR(-EPROBE_DEFER);
 
 	config = devm_kzalloc(dev, sizeof(struct fixed_voltage_config),
 								 GFP_KERNEL);
 	if (!config)
 		return NULL;
 
+	config->gpio = gpio;
+
 	config->init_data = of_get_regulator_init_data(dev, dev->of_node);
 	if (!config->init_data)
 		return NULL;
@@ -83,7 +90,6 @@ of_get_fixed_voltage_config(struct device *dev)
 	if (init_data->constraints.boot_on)
 		config->enabled_at_boot = true;
 
-	config->gpio = of_get_named_gpio(np, "gpio", 0);
 	delay = of_get_property(np, "startup-delay-us", NULL);
 	if (delay)
 		config->startup_delay = be32_to_cpu(*delay);
@@ -168,9 +174,11 @@ static int __devinit reg_fixed_voltage_probe(struct platform_device *pdev)
 	struct fixed_voltage_data *drvdata;
 	int ret;
 
-	if (pdev->dev.of_node)
+	if (pdev->dev.of_node) {
 		config = of_get_fixed_voltage_config(&pdev->dev);
-	else
+		if (IS_ERR(config))
+			return PTR_ERR(config);
+	} else
 		config = pdev->dev.platform_data;
 
 	if (!config)
-- 
1.7.9.3



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:26 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:26 +0100
Subject: [PATCH 06/11] PCI: Keep pci_fixup_irqs() around after init
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331218291-16119-7-git-send-email-thierry.reding@avionic-design.de>

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 drivers/pci/setup-irq.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c
index eb219a1..270ae7b 100644
--- a/drivers/pci/setup-irq.c
+++ b/drivers/pci/setup-irq.c
@@ -18,7 +18,7 @@
 #include <linux/cache.h>
 
 
-static void __init
+static void
 pdev_fixup_irq(struct pci_dev *dev,
 	       u8 (*swizzle)(struct pci_dev *, u8 *),
 	       int (*map_irq)(const struct pci_dev *, u8, u8))
@@ -54,7 +54,7 @@ pdev_fixup_irq(struct pci_dev *dev,
 	pcibios_update_irq(dev, irq);
 }
 
-void __init
+void
 pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
 	       int (*map_irq)(const struct pci_dev *, u8, u8))
 {
-- 
1.7.9.3



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:27 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:27 +0100
Subject: [PATCH 07/11] ARM: pci: Keep pci_common_init() around after init
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331218291-16119-8-git-send-email-thierry.reding@avionic-design.de>

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 arch/arm/kernel/bios32.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index be5d3b2..c88dcf5 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -411,7 +411,7 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 	return irq;
 }
 
-static void __init pcibios_init_hw(struct hw_pci *hw)
+static void pcibios_init_hw(struct hw_pci *hw)
 {
 	struct pci_sys_data *sys = NULL;
 	int ret;
@@ -457,7 +457,7 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
 	}
 }
 
-void __init pci_common_init(struct hw_pci *hw)
+void pci_common_init(struct hw_pci *hw)
 {
 	struct pci_sys_data *sys;
 
-- 
1.7.9.3



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:30 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:30 +0100
Subject: [PATCH 10/11] ARM: tegra: pcie: Add MSI support
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331218291-16119-11-git-send-email-thierry.reding@avionic-design.de>

This commit adds support for message signaled interrupts to the Tegra
PCIe controller.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
This code is taken from the NVIDIA Vibrante kernel and therefore has no
appropriate Signed-off-by from the original author. Maybe someone at
NVIDIA can find out who wrote this code and maybe provide a proper
Signed-off-by that I can add?

 arch/arm/mach-tegra/Kconfig             |    1 +
 arch/arm/mach-tegra/devices.c           |    7 +
 arch/arm/mach-tegra/include/mach/irqs.h |    5 +-
 arch/arm/mach-tegra/pcie.c              |  239 +++++++++++++++++++++++++++++++
 4 files changed, 251 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 1651119..7c596e6 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -48,6 +48,7 @@ config ARCH_TEGRA_3x_SOC
 config TEGRA_PCI
 	bool "PCI Express support"
 	depends on ARCH_TEGRA_2x_SOC
+	select ARCH_SUPPORTS_MSI
 	select PCI
 
 comment "Tegra board type"
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 09e24e1..195f165 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -721,6 +721,13 @@ static struct resource tegra_pcie_resources[] = {
 		.end = INT_PCIE_INTR,
 		.flags = IORESOURCE_IRQ,
 	},
+#ifdef CONFIG_PCI_MSI
+	[3] = {
+		.start = INT_PCIE_MSI,
+		.end = INT_PCIE_MSI,
+		.flags = IORESOURCE_IRQ,
+	},
+#endif
 };
 
 struct platform_device tegra_pcie_device = {
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index aad1a2c..02e84bc 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -172,7 +172,10 @@
 /* Tegra30 has 8 banks of 32 GPIOs */
 #define INT_GPIO_NR			(32 * 8)
 
-#define TEGRA_NR_IRQS			(INT_GPIO_BASE + INT_GPIO_NR)
+#define INT_PCI_MSI_BASE		(INT_GPIO_BASE + INT_GPIO_NR)
+#define INT_PCI_MSI_NR			(32 * 8)
+
+#define TEGRA_NR_IRQS			(INT_PCI_MSI_BASE + INT_PCI_MSI_NR)
 
 #define INT_BOARD_BASE			TEGRA_NR_IRQS
 #define NR_BOARD_IRQS			32
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 8b20bc5..85db9fb 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -31,11 +31,14 @@
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/export.h>
+#include <linux/msi.h>
 
 #include <asm/sizes.h>
+#include <asm/mach/irq.h>
 #include <asm/mach/pci.h>
 
 #include <mach/iomap.h>
@@ -81,6 +84,24 @@
 #define AFI_MSI_FPCI_BAR_ST	0x64
 #define AFI_MSI_AXI_BAR_ST	0x68
 
+#define AFI_MSI_VEC0		0x6c
+#define AFI_MSI_VEC1		0x70
+#define AFI_MSI_VEC2		0x74
+#define AFI_MSI_VEC3		0x78
+#define AFI_MSI_VEC4		0x7c
+#define AFI_MSI_VEC5		0x80
+#define AFI_MSI_VEC6		0x84
+#define AFI_MSI_VEC7		0x88
+
+#define AFI_MSI_EN_VEC0		0x8c
+#define AFI_MSI_EN_VEC1		0x90
+#define AFI_MSI_EN_VEC2		0x94
+#define AFI_MSI_EN_VEC3		0x98
+#define AFI_MSI_EN_VEC4		0x9c
+#define AFI_MSI_EN_VEC5		0xa0
+#define AFI_MSI_EN_VEC6		0xa4
+#define AFI_MSI_EN_VEC7		0xa8
+
 #define AFI_CONFIGURATION		0xac
 #define  AFI_CONFIGURATION_EN_FPCI	(1 << 0)
 
@@ -211,6 +232,14 @@ struct tegra_pcie_info {
 	struct clk		*afi_clk;
 	struct clk		*pcie_xclk;
 	struct clk		*pll_e;
+
+#ifdef CONFIG_PCI_MSI
+	int msi_irq;
+	struct irq_chip msi_chip;
+	DECLARE_BITMAP(msi_in_use, INT_PCI_MSI_NR);
+	struct irq_domain *msi_domain;
+	struct mutex msi_lock;
+#endif
 };
 
 static inline struct tegra_pcie_info *sys_to_pcie(struct pci_sys_data *sys)
@@ -939,6 +968,208 @@ static void __devinit tegra_pcie_add_port(struct tegra_pcie_info *pcie,
 	memset(pp->res, 0, sizeof(pp->res));
 }
 
+#ifdef CONFIG_PCI_MSI
+static int tegra_pcie_msi_alloc(struct tegra_pcie_info *pcie)
+{
+	int msi;
+
+	mutex_lock(&pcie->msi_lock);
+
+	msi = find_first_zero_bit(pcie->msi_in_use, INT_PCI_MSI_NR);
+	if (msi < INT_PCI_MSI_NR)
+		set_bit(msi, pcie->msi_in_use);
+	else
+		msi = -ENOSPC;
+
+	mutex_unlock(&pcie->msi_lock);
+
+	return msi;
+}
+
+static void tegra_pcie_msi_free(struct tegra_pcie_info *pcie, unsigned long irq)
+{
+	mutex_lock(&pcie->msi_lock);
+
+	if (!test_bit(irq, pcie->msi_in_use))
+		dev_err(pcie->dev, "trying to free unused MSI#%lu\n", irq);
+	else
+		clear_bit(irq, pcie->msi_in_use);
+
+	mutex_unlock(&pcie->msi_lock);
+}
+
+static void tegra_pcie_msi_isr(unsigned int irq, struct irq_desc *desc)
+{
+	struct tegra_pcie_info *pcie = irq_get_handler_data(irq);
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	unsigned int i;
+
+	chained_irq_enter(chip, desc);
+
+	for (i = 0; i < 8; i++) {
+		unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
+
+		while (reg) {
+			unsigned int offset = find_first_bit(&reg, 32);
+			unsigned int index = i * 32 + offset;
+			unsigned int irq;
+
+			irq = irq_find_mapping(pcie->msi_domain, index);
+			if (irq) {
+				if (test_bit(index, pcie->msi_in_use))
+					generic_handle_irq(irq);
+				else
+					dev_info(pcie->dev, "unhandled MSI\n");
+			} else {
+				/*
+				 * that's weird who triggered this?
+				 * just clear it
+				 */
+				dev_info(pcie->dev, "unexpected MSI\n");
+			}
+
+			/* clear the interrupt */
+			afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
+			/* see if there's any more pending in this vector */
+			reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+/* called by arch_setup_msi_irqs in drivers/pci/msi.c */
+int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
+{
+	struct tegra_pcie_info *pcie = sys_to_pcie(pdev->bus->sysdata);
+	struct msi_msg msg;
+	unsigned int irq;
+	int hwirq;
+
+	hwirq = tegra_pcie_msi_alloc(pcie);
+	if (hwirq < 0)
+		return hwirq;
+
+	irq = irq_find_mapping(pcie->msi_domain, hwirq);
+	if (!irq)
+		return -EINVAL;
+
+	irq_set_msi_desc(irq, desc);
+
+	msg.address_lo = afi_readl(pcie, AFI_MSI_AXI_BAR_ST);
+	/* 32 bit address only */
+	msg.address_hi = 0;
+	msg.data = hwirq;
+
+	write_msi_msg(irq, &msg);
+
+	return 0;
+}
+
+void arch_teardown_msi_irq(unsigned int irq)
+{
+	struct tegra_pcie_info *pcie = irq_get_chip_data(irq);
+	struct irq_data *d = irq_get_irq_data(irq);
+
+	tegra_pcie_msi_free(pcie, d->hwirq);
+}
+
+static int tegra_pcie_enable_msi(struct platform_device *pdev)
+{
+	struct tegra_pcie_info *pcie = platform_get_drvdata(pdev);
+	volatile void *pages;
+	unsigned long base;
+	unsigned int msi;
+	int msi_base;
+	int err;
+	u32 reg;
+
+	mutex_init(&pcie->msi_lock);
+
+	msi_base = irq_alloc_descs(-1, 0, INT_PCI_MSI_NR, 0);
+	if (msi_base < 0) {
+		dev_err(&pdev->dev, "failed to allocate IRQs\n");
+		return msi_base;
+	}
+
+	pcie->msi_domain = irq_domain_add_legacy(pcie->dev->of_node,
+						 INT_PCI_MSI_NR, msi_base,
+						 0, &irq_domain_simple_ops,
+						 NULL);
+	if (!pcie->msi_domain) {
+		dev_err(&pdev->dev, "failed to create IRQ domain\n");
+		return -ENOMEM;
+	}
+
+	pcie->msi_chip.name = "PCIe-MSI";
+	pcie->msi_chip.irq_enable = unmask_msi_irq;
+	pcie->msi_chip.irq_disable = mask_msi_irq;
+	pcie->msi_chip.irq_mask = mask_msi_irq;
+	pcie->msi_chip.irq_unmask = unmask_msi_irq;
+
+	for (msi = 0; msi < INT_PCI_MSI_NR; msi++) {
+		unsigned int irq = irq_find_mapping(pcie->msi_domain, msi);
+
+		irq_set_chip_data(irq, pcie);
+		irq_set_chip_and_handler(irq, &pcie->msi_chip,
+					 handle_simple_irq);
+		set_irq_flags(irq, IRQF_VALID);
+	}
+
+	err = platform_get_irq(pdev, 1);
+	if (err < 0) {
+		dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
+		return err;
+	}
+
+	pcie->msi_irq = err;
+
+	irq_set_chained_handler(pcie->msi_irq, tegra_pcie_msi_isr);
+	irq_set_handler_data(pcie->msi_irq, pcie);
+
+	/* setup AFI/FPCI range */
+	pages = (volatile void *)__get_free_pages(GFP_KERNEL, 3);
+	base = virt_to_phys(pages);
+
+	afi_writel(pcie, base, AFI_MSI_FPCI_BAR_ST);
+	afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST);
+	/* this register is in 4K increments */
+	afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
+
+	/* enable all MSI vectors */
+	afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
+	afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
+	afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
+	afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
+	afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
+	afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
+	afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
+	afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
+
+	/* and unmask the MSI interrupt */
+	reg = afi_readl(pcie, AFI_INTR_MASK);
+	reg |= AFI_INTR_MASK_MSI_MASK;
+	afi_writel(pcie, reg, AFI_INTR_MASK);
+
+	return 0;
+}
+
+static int tegra_pcie_disable_msi(struct platform_device *pdev)
+{
+	return 0;
+}
+#else
+static int tegra_pcie_enable_msi(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static int tegra_pcie_disable_msi(struct platform_device *pdev)
+{
+	return 0;
+}
+#endif
+
 static int __devinit tegra_pcie_probe(struct platform_device *pdev)
 {
 	struct tegra_pcie_pdata *pdata = pdev->dev.platform_data;
@@ -978,6 +1209,10 @@ static int __devinit tegra_pcie_probe(struct platform_device *pdev)
 	/* setup the AFI address translations */
 	tegra_pcie_setup_translations(pcie);
 
+	err = tegra_pcie_enable_msi(pdev);
+	if (err < 0)
+		dev_err(&pdev->dev, "failed to enable MSI support: %d\n", err);
+
 	if (pdata->enable_ports[0])
 		tegra_pcie_add_port(pcie, 0, RP0_OFFSET, AFI_PEX0_CTRL);
 
@@ -1000,6 +1235,10 @@ static int __devexit tegra_pcie_remove(struct platform_device *pdev)
 	struct tegra_pcie_pdata *pdata = pdev->dev.platform_data;
 	int err;
 
+	err = tegra_pcie_disable_msi(pdev);
+	if (err < 0)
+		return err;
+
 	err = tegra_pcie_put_resources(pdev);
 	if (err < 0)
 		return err;
-- 
1.7.9.3



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:24 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:24 +0100
Subject: [PATCH 04/11] regulator: tps6586x: fix typo in debug message
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331218291-16119-5-git-send-email-thierry.reding@avionic-design.de>

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 drivers/regulator/tps6586x-regulator.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/regulator/tps6586x-regulator.c b/drivers/regulator/tps6586x-regulator.c
index c75fb20..29b615c 100644
--- a/drivers/regulator/tps6586x-regulator.c
+++ b/drivers/regulator/tps6586x-regulator.c
@@ -383,7 +383,7 @@ static int __devinit tps6586x_regulator_probe(struct platform_device *pdev)
 	int id = pdev->id;
 	int err;
 
-	dev_dbg(&pdev->dev, "Probing reulator %d\n", id);
+	dev_dbg(&pdev->dev, "Probing regulator %d\n", id);
 
 	ri = find_regulator_info(id);
 	if (ri == NULL) {
-- 
1.7.9.3



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:29 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:29 +0100
Subject: [PATCH 09/11] ARM: tegra: Rewrite PCIe support as a driver
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331218291-16119-10-git-send-email-thierry.reding@avionic-design.de>

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 arch/arm/mach-tegra/board-harmony-pcie.c |   38 ++-
 arch/arm/mach-tegra/board-harmony.c      |    1 +
 arch/arm/mach-tegra/board-harmony.h      |    1 +
 arch/arm/mach-tegra/board-trimslice.c    |   16 +-
 arch/arm/mach-tegra/board.h              |   11 +-
 arch/arm/mach-tegra/devices.c            |   25 ++
 arch/arm/mach-tegra/devices.h            |    1 +
 arch/arm/mach-tegra/include/mach/iomap.h |    6 +
 arch/arm/mach-tegra/pcie.c               |  509 ++++++++++++++++++------------
 9 files changed, 386 insertions(+), 222 deletions(-)

diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index 33c4fed..e624a9c 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -23,18 +23,15 @@
 #include <asm/mach-types.h>
 
 #include "board.h"
+#include "devices.h"
 #include "board-harmony.h"
 
 #ifdef CONFIG_TEGRA_PCI
-
-static int __init harmony_pcie_init(void)
+static int tegra_pcie_init(struct platform_device *pdev)
 {
 	struct regulator *regulator = NULL;
 	int err;
 
-	if (!machine_is_harmony())
-		return 0;
-
 	err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05");
 	if (err)
 		return err;
@@ -47,22 +44,35 @@ static int __init harmony_pcie_init(void)
 
 	regulator_enable(regulator);
 
-	err = tegra_pcie_init(true, true);
-	if (err)
-		goto err_pcie;
-
 	return 0;
 
-err_pcie:
-	regulator_disable(regulator);
-	regulator_put(regulator);
 err_reg:
 	gpio_free(TEGRA_GPIO_EN_VDD_1V05_GPIO);
 
 	return err;
 }
 
-/* PCI should be initialized after I2C, mfd and regulators */
-subsys_initcall_sync(harmony_pcie_init);
+static struct tegra_pcie_pdata tegra_pcie_pdata = {
+	.init = tegra_pcie_init,
+	.enable_ports = {
+		[0] = true,
+		[1] = true,
+	},
+};
+
+int __init harmony_pcie_init(void)
+{
+	if (!machine_is_harmony())
+		return 0;
+
+	tegra_pcie_device.dev.platform_data = &tegra_pcie_pdata;
+	platform_device_register(&tegra_pcie_device);
 
+	return 0;
+}
+#else
+int __init harmony_pcie_init(void)
+{
+	return 0;
+}
 #endif
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index c00aadb..ca20680 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -180,6 +180,7 @@ static void __init tegra_harmony_init(void)
 	platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
 	harmony_i2c_init();
 	harmony_regulator_init();
+	harmony_pcie_init();
 }
 
 MACHINE_START(HARMONY, "harmony")
diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h
index 139d96c..afa68e2 100644
--- a/arch/arm/mach-tegra/board-harmony.h
+++ b/arch/arm/mach-tegra/board-harmony.h
@@ -37,5 +37,6 @@
 
 void harmony_pinmux_init(void);
 int harmony_regulator_init(void);
+int harmony_pcie_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index cd52820..9bc414a 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -147,14 +147,23 @@ static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
 	{ NULL,		NULL,		0,		0},
 };
 
-static int __init tegra_trimslice_pci_init(void)
+static struct tegra_pcie_pdata tegra_pcie_pdata = {
+	.enable_ports = {
+		[0] = true,
+		[1] = true,
+	},
+};
+
+static int __init trimslice_pci_init(void)
 {
 	if (!machine_is_trimslice())
 		return 0;
 
-	return tegra_pcie_init(true, true);
+	tegra_pcie_device.dev.platform_data = &tegra_pcie_pdata;
+	platform_device_register(&tegra_pcie_device);
+
+	return 0;
 }
-subsys_initcall(tegra_trimslice_pci_init);
 
 static void __init tegra_trimslice_init(void)
 {
@@ -169,6 +178,7 @@ static void __init tegra_trimslice_init(void)
 
 	trimslice_i2c_init();
 	trimslice_usb_init();
+	trimslice_pci_init();
 }
 
 MACHINE_START(TRIMSLICE, "trimslice")
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 75d1543..40f7e6b 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -21,6 +21,7 @@
 #ifndef __MACH_TEGRA_BOARD_H
 #define __MACH_TEGRA_BOARD_H
 
+#include <linux/platform_device.h>
 #include <linux/types.h>
 
 void tegra_assert_system_reset(char mode, const char *cmd);
@@ -30,7 +31,15 @@ void __init tegra30_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 void __init tegra_dt_init_irq(void);
-int __init tegra_pcie_init(bool init_port0, bool init_port1);
 
 extern struct sys_timer tegra_timer;
+
+#define TEGRA_PCIE_MAX_PORTS 2
+
+struct tegra_pcie_pdata {
+	int (*init)(struct platform_device *pdev);
+	int (*exit)(struct platform_device *pdev);
+	bool enable_ports[TEGRA_PCIE_MAX_PORTS];
+};
+
 #endif
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 7a2a02d..09e24e1 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -704,3 +704,28 @@ struct platform_device tegra_pcm_device = {
 	.name = "tegra-pcm-audio",
 	.id = -1,
 };
+
+static struct resource tegra_pcie_resources[] = {
+	[0] = {
+		.start = TEGRA_PCIE_BASE,
+		.end = TEGRA_PCIE_BASE + TEGRA_PCIE_SIZE - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = TEGRA_PCIE_MMIO_BASE,
+		.end = TEGRA_PCIE_MMIO_BASE + TEGRA_PCIE_MMIO_SIZE - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[2] = {
+		.start = INT_PCIE_INTR,
+		.end = INT_PCIE_INTR,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device tegra_pcie_device = {
+	.name = "tegra-pcie",
+	.id = -1,
+	.resource = tegra_pcie_resources,
+	.num_resources = ARRAY_SIZE(tegra_pcie_resources),
+};
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
index 873ecb2..95f0a97 100644
--- a/arch/arm/mach-tegra/devices.h
+++ b/arch/arm/mach-tegra/devices.h
@@ -48,5 +48,6 @@ extern struct platform_device tegra_i2s_device1;
 extern struct platform_device tegra_i2s_device2;
 extern struct platform_device tegra_das_device;
 extern struct platform_device tegra_pcm_device;
+extern struct platform_device tegra_pcie_device;
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index cff672a..53b0dbe 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -242,6 +242,12 @@
 #define TEGRA_CSITE_BASE		0x70040000
 #define TEGRA_CSITE_SIZE		SZ_256K
 
+#define TEGRA_PCIE_BASE			0x80000000
+#define TEGRA_PCIE_SIZE			SZ_4M
+
+#define TEGRA_PCIE_MMIO_BASE		0x80400000
+#define TEGRA_PCIE_MMIO_SIZE		SZ_64K
+
 #define TEGRA_USB_BASE			0xC5000000
 #define TEGRA_USB_SIZE			SZ_16K
 
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 7704af7a..8b20bc5 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -28,6 +28,7 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/clk.h>
@@ -161,17 +162,12 @@
  * 0x90000000 - 0x9fffffff - non-prefetchable memory
  * 0xa0000000 - 0xbfffffff - prefetchable memory
  */
-#define TEGRA_PCIE_BASE		0x80000000
-
 #define PCIE_REGS_SZ		SZ_16K
 #define PCIE_CFG_OFF		PCIE_REGS_SZ
 #define PCIE_CFG_SZ		SZ_1M
 #define PCIE_EXT_CFG_OFF	(PCIE_CFG_SZ + PCIE_CFG_OFF)
 #define PCIE_EXT_CFG_SZ		SZ_1M
-#define PCIE_IOMAP_SZ		(PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
 
-#define MMIO_BASE		(TEGRA_PCIE_BASE + SZ_4M)
-#define MMIO_SIZE		SZ_64K
 #define MEM_BASE_0		(TEGRA_PCIE_BASE + SZ_256M)
 #define MEM_SIZE_0		SZ_128M
 #define MEM_BASE_1		(MEM_BASE_0 + MEM_SIZE_0)
@@ -201,11 +197,15 @@ struct tegra_pcie_port {
 };
 
 struct tegra_pcie_info {
-	struct tegra_pcie_port	port[2];
+	struct device		*dev;
+	struct hw_pci		hw;
+
+	struct tegra_pcie_port	port[TEGRA_PCIE_MAX_PORTS];
 	int			num_ports;
 
 	void __iomem		*regs;
-	struct resource		res_mmio;
+	void __iomem		*mmio;
+	int			irq;
 
 	struct clk		*pex_clk;
 	struct clk		*afi_clk;
@@ -213,55 +213,53 @@ struct tegra_pcie_info {
 	struct clk		*pll_e;
 };
 
-static struct tegra_pcie_info tegra_pcie = {
-	.res_mmio = {
-		.name = "PCI IO",
-		.start = MMIO_BASE,
-		.end = MMIO_BASE + MMIO_SIZE - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
+static inline struct tegra_pcie_info *sys_to_pcie(struct pci_sys_data *sys)
+{
+	return container_of(sys->hw, struct tegra_pcie_info, hw);
+}
 
 void __iomem *tegra_pcie_io_base;
 EXPORT_SYMBOL(tegra_pcie_io_base);
 
-static inline void afi_writel(u32 value, unsigned long offset)
+static inline void afi_writel(struct tegra_pcie_info *pcie, u32 value, unsigned long offset)
 {
-	writel(value, offset + AFI_OFFSET + tegra_pcie.regs);
+	writel(value, offset + AFI_OFFSET + pcie->regs);
 }
 
-static inline u32 afi_readl(unsigned long offset)
+static inline u32 afi_readl(struct tegra_pcie_info *pcie, unsigned long offset)
 {
-	return readl(offset + AFI_OFFSET + tegra_pcie.regs);
+	return readl(offset + AFI_OFFSET + pcie->regs);
 }
 
-static inline void pads_writel(u32 value, unsigned long offset)
+static inline void pads_writel(struct tegra_pcie_info *pcie, u32 value, unsigned long offset)
 {
-	writel(value, offset + PADS_OFFSET + tegra_pcie.regs);
+	writel(value, offset + PADS_OFFSET + pcie->regs);
 }
 
-static inline u32 pads_readl(unsigned long offset)
+static inline u32 pads_readl(struct tegra_pcie_info *pcie, unsigned long offset)
 {
-	return readl(offset + PADS_OFFSET + tegra_pcie.regs);
+	return readl(offset + PADS_OFFSET + pcie->regs);
 }
 
-static struct tegra_pcie_port *bus_to_port(int bus)
+static struct tegra_pcie_port *bus_to_port(struct pci_bus *bus)
 {
+	struct tegra_pcie_info *pcie = sys_to_pcie(bus->sysdata);
 	int i;
 
-	for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
-		int rbus = tegra_pcie.port[i].root_bus_nr;
-		if (rbus != -1 && rbus == bus)
+	for (i = pcie->num_ports - 1; i >= 0; i--) {
+		int rbus = pcie->port[i].root_bus_nr;
+		if (rbus != -1 && rbus == bus->number)
 			break;
 	}
 
-	return i >= 0 ? tegra_pcie.port + i : NULL;
+	return i >= 0 ? pcie->port + i : NULL;
 }
 
 static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
 				int where, int size, u32 *val)
 {
-	struct tegra_pcie_port *pp = bus_to_port(bus->number);
+	struct tegra_pcie_info *pcie = sys_to_pcie(bus->sysdata);
+	struct tegra_pcie_port *pp = bus_to_port(bus);
 	void __iomem *addr;
 
 	if (pp) {
@@ -272,10 +270,10 @@ static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
 
 		addr = pp->base + (where & ~0x3);
 	} else {
-		addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
-					  PCIE_CONF_DEV(PCI_SLOT(devfn)) +
-					  PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
-					  PCIE_CONF_REG(where));
+		addr = pcie->regs + (PCIE_CONF_BUS(bus->number) +
+				     PCIE_CONF_DEV(PCI_SLOT(devfn)) +
+				     PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
+				     PCIE_CONF_REG(where));
 	}
 
 	*val = readl(addr);
@@ -291,7 +289,8 @@ static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
 static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
 				 int where, int size, u32 val)
 {
-	struct tegra_pcie_port *pp = bus_to_port(bus->number);
+	struct tegra_pcie_info *pcie = sys_to_pcie(bus->sysdata);
+	struct tegra_pcie_port *pp = bus_to_port(bus);
 	void __iomem *addr;
 
 	u32 mask;
@@ -303,10 +302,10 @@ static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
 
 		addr = pp->base + (where & ~0x3);
 	} else {
-		addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
-					  PCIE_CONF_DEV(PCI_SLOT(devfn)) +
-					  PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
-					  PCIE_CONF_REG(where));
+		addr = pcie->regs + (PCIE_CONF_BUS(bus->number) +
+				     PCIE_CONF_DEV(PCI_SLOT(devfn)) +
+				     PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
+				     PCIE_CONF_REG(where));
 	}
 
 	if (size == 4) {
@@ -373,12 +372,13 @@ DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
 
 static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
 {
+	struct tegra_pcie_info *pcie = sys_to_pcie(sys);
 	struct tegra_pcie_port *pp;
 
-	if (nr >= tegra_pcie.num_ports)
+	if (nr >= pcie->num_ports)
 		return 0;
 
-	pp = tegra_pcie.port + nr;
+	pp = pcie->port + nr;
 	pp->root_bus_nr = sys->busnr;
 
 	/*
@@ -441,35 +441,29 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
 	return 1;
 }
 
-static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
 {
-	return INT_PCIE_INTR;
+	struct tegra_pcie_info *pcie = sys_to_pcie(pdev->bus->sysdata);
+
+	return pcie->irq;
 }
 
-static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
-						  struct pci_sys_data *sys)
+static struct pci_bus __devinit *tegra_pcie_scan_bus(int nr,
+						     struct pci_sys_data *sys)
 {
+	struct tegra_pcie_info *pcie = sys_to_pcie(sys);
 	struct tegra_pcie_port *pp;
 
-	if (nr >= tegra_pcie.num_ports)
+	if (nr >= pcie->num_ports)
 		return NULL;
 
-	pp = tegra_pcie.port + nr;
+	pp = pcie->port + nr;
 	pp->root_bus_nr = sys->busnr;
 
 	return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys,
 				 &sys->resources);
 }
 
-static struct hw_pci tegra_pcie_hw __initdata = {
-	.nr_controllers	= 2,
-	.setup		= tegra_pcie_setup,
-	.scan		= tegra_pcie_scan_bus,
-	.swizzle	= pci_std_swizzle,
-	.map_irq	= tegra_pcie_map_irq,
-};
-
-
 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
 {
 	const char *err_msg[] = {
@@ -483,12 +477,12 @@ static irqreturn_t tegra_pcie_isr(int irq, void *arg)
 		"AXI response decoding error",
 		"Transcation timeout",
 	};
-
+	struct tegra_pcie_info *pcie = arg;
 	u32 code, signature;
 
-	code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
-	signature = afi_readl(AFI_INTR_SIGNATURE);
-	afi_writel(0, AFI_INTR_CODE);
+	code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
+	signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
+	afi_writel(pcie, 0, AFI_INTR_CODE);
 
 	if (code == AFI_INTR_LEGACY)
 		return IRQ_NONE;
@@ -501,14 +495,16 @@ static irqreturn_t tegra_pcie_isr(int irq, void *arg)
 	 * happen a lot during enumeration
 	 */
 	if (code == AFI_INTR_MASTER_ABORT)
-		pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature);
+		dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code],
+			signature);
 	else
-		pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature);
+		dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code],
+			signature);
 
 	return IRQ_HANDLED;
 }
 
-static void tegra_pcie_setup_translations(void)
+static void tegra_pcie_setup_translations(struct tegra_pcie_info *pcie)
 {
 	u32 fpci_bar;
 	u32 size;
@@ -518,120 +514,120 @@ static void tegra_pcie_setup_translations(void)
 	fpci_bar = ((u32)0xfdff << 16);
 	size = PCIE_CFG_SZ;
 	axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
-	afi_writel(axi_address, AFI_AXI_BAR0_START);
-	afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
-	afi_writel(fpci_bar, AFI_FPCI_BAR0);
+	afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
+	afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
+	afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0);
 
 	/* Bar 1: extended config Bar */
 	fpci_bar = ((u32)0xfe1 << 20);
 	size = PCIE_EXT_CFG_SZ;
 	axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
-	afi_writel(axi_address, AFI_AXI_BAR1_START);
-	afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
-	afi_writel(fpci_bar, AFI_FPCI_BAR1);
+	afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
+	afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
+	afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
 
 	/* Bar 2: downstream IO bar */
 	fpci_bar = ((__u32)0xfdfc << 16);
-	size = MMIO_SIZE;
-	axi_address = MMIO_BASE;
-	afi_writel(axi_address, AFI_AXI_BAR2_START);
-	afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
-	afi_writel(fpci_bar, AFI_FPCI_BAR2);
+	size = TEGRA_PCIE_MMIO_SIZE;
+	axi_address = TEGRA_PCIE_MMIO_BASE;
+	afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
+	afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
+	afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
 
 	/* Bar 3: prefetchable memory BAR */
 	fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
 	size =  PREFETCH_MEM_SIZE_0 +  PREFETCH_MEM_SIZE_1;
 	axi_address = PREFETCH_MEM_BASE_0;
-	afi_writel(axi_address, AFI_AXI_BAR3_START);
-	afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
-	afi_writel(fpci_bar, AFI_FPCI_BAR3);
+	afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
+	afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
+	afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
 
 	/* Bar 4: non prefetchable memory BAR */
 	fpci_bar = (((MEM_BASE_0 >> 12)	& 0x0FFFFFFF) << 4) | 0x1;
 	size = MEM_SIZE_0 + MEM_SIZE_1;
 	axi_address = MEM_BASE_0;
-	afi_writel(axi_address, AFI_AXI_BAR4_START);
-	afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
-	afi_writel(fpci_bar, AFI_FPCI_BAR4);
+	afi_writel(pcie, axi_address, AFI_AXI_BAR4_START);
+	afi_writel(pcie, size >> 12, AFI_AXI_BAR4_SZ);
+	afi_writel(pcie, fpci_bar, AFI_FPCI_BAR4);
 
 	/* Bar 5: NULL out the remaining BAR as it is not used */
 	fpci_bar = 0;
 	size = 0;
 	axi_address = 0;
-	afi_writel(axi_address, AFI_AXI_BAR5_START);
-	afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
-	afi_writel(fpci_bar, AFI_FPCI_BAR5);
+	afi_writel(pcie, axi_address, AFI_AXI_BAR5_START);
+	afi_writel(pcie, size >> 12, AFI_AXI_BAR5_SZ);
+	afi_writel(pcie, fpci_bar, AFI_FPCI_BAR5);
 
 	/* map all upstream transactions as uncached */
-	afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
-	afi_writel(0, AFI_CACHE_BAR0_SZ);
-	afi_writel(0, AFI_CACHE_BAR1_ST);
-	afi_writel(0, AFI_CACHE_BAR1_SZ);
+	afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST);
+	afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
+	afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
+	afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
 
 	/* No MSI */
-	afi_writel(0, AFI_MSI_FPCI_BAR_ST);
-	afi_writel(0, AFI_MSI_BAR_SZ);
-	afi_writel(0, AFI_MSI_AXI_BAR_ST);
-	afi_writel(0, AFI_MSI_BAR_SZ);
+	afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
+	afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
+	afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
+	afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
 }
 
-static int tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(struct tegra_pcie_info *pcie)
 {
 	u32 val, reg;
 	int i, timeout;
 
 	/* Enable slot clock and pulse the reset signals */
 	for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
-		val = afi_readl(reg) |  AFI_PEX_CTRL_REFCLK_EN;
-		afi_writel(val, reg);
+		val = afi_readl(pcie, reg) |  AFI_PEX_CTRL_REFCLK_EN;
+		afi_writel(pcie, val, reg);
 		val &= ~AFI_PEX_CTRL_RST;
-		afi_writel(val, reg);
+		afi_writel(pcie, val, reg);
 
-		val = afi_readl(reg) | AFI_PEX_CTRL_RST;
-		afi_writel(val, reg);
+		val = afi_readl(pcie, reg) | AFI_PEX_CTRL_RST;
+		afi_writel(pcie, val, reg);
 	}
 
 	/* Enable dual controller and both ports */
-	val = afi_readl(AFI_PCIE_CONFIG);
+	val = afi_readl(pcie, AFI_PCIE_CONFIG);
 	val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
 		 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
 		 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
 	val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
-	afi_writel(val, AFI_PCIE_CONFIG);
+	afi_writel(pcie, val, AFI_PCIE_CONFIG);
 
-	val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
-	afi_writel(val, AFI_FUSE);
+	val = afi_readl(pcie, AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
+	afi_writel(pcie, val, AFI_FUSE);
 
 	/* Initialze internal PHY, enable up to 16 PCIE lanes */
-	pads_writel(0x0, PADS_CTL_SEL);
+	pads_writel(pcie, 0x0, PADS_CTL_SEL);
 
 	/* override IDDQ to 1 on all 4 lanes */
-	val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
-	pads_writel(val, PADS_CTL);
+	val = pads_readl(pcie, PADS_CTL) | PADS_CTL_IDDQ_1L;
+	pads_writel(pcie, val, PADS_CTL);
 
 	/*
 	 * set up PHY PLL inputs select PLLE output as refclock,
 	 * set TX ref sel to div10 (not div5)
 	 */
-	val = pads_readl(PADS_PLL_CTL);
+	val = pads_readl(pcie, PADS_PLL_CTL);
 	val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
 	val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
-	pads_writel(val, PADS_PLL_CTL);
+	pads_writel(pcie, val, PADS_PLL_CTL);
 
 	/* take PLL out of reset  */
-	val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
-	pads_writel(val, PADS_PLL_CTL);
+	val = pads_readl(pcie, PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
+	pads_writel(pcie, val, PADS_PLL_CTL);
 
 	/*
 	 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
 	 * This doesn't exist in the documentation
 	 */
-	pads_writel(0xfa5cfa5c, 0xc8);
+	pads_writel(pcie, 0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
 	timeout = 2000;
 	do {
-		val = pads_readl(PADS_PLL_CTL);
+		val = pads_readl(pcie, PADS_PLL_CTL);
 		mdelay(1);
 		if (--timeout == 0) {
 			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
@@ -640,188 +636,237 @@ static int tegra_pcie_enable_controller(void)
 	} while (!(val & PADS_PLL_CTL_LOCKDET));
 
 	/* turn off IDDQ override */
-	val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
-	pads_writel(val, PADS_CTL);
+	val = pads_readl(pcie, PADS_CTL) & ~PADS_CTL_IDDQ_1L;
+	pads_writel(pcie, val, PADS_CTL);
 
 	/* enable TX/RX data */
-	val = pads_readl(PADS_CTL);
+	val = pads_readl(pcie, PADS_CTL);
 	val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
-	pads_writel(val, PADS_CTL);
+	pads_writel(pcie, val, PADS_CTL);
 
 	/* Take the PCIe interface module out of reset */
-	tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
+	tegra_periph_reset_deassert(pcie->pcie_xclk);
 
 	/* Finally enable PCIe */
-	val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
-	afi_writel(val, AFI_CONFIGURATION);
+	val = afi_readl(pcie, AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
+	afi_writel(pcie, val, AFI_CONFIGURATION);
 
 	val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
 	       AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
 	       AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
-	afi_writel(val, AFI_AFI_INTR_ENABLE);
-	afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
+	afi_writel(pcie, val, AFI_AFI_INTR_ENABLE);
+	afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
 
 	/* FIXME: No MSI for now, only INT */
-	afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
+	afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
 
 	/* Disable all execptions */
-	afi_writel(0, AFI_FPCI_ERROR_MASKS);
+	afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
 
-	return;
+	return 0;
 }
 
-static void tegra_pcie_power_off(void)
+static void tegra_pcie_power_off(struct tegra_pcie_info *pcie)
 {
-	tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
-	tegra_periph_reset_assert(tegra_pcie.afi_clk);
-	tegra_periph_reset_assert(tegra_pcie.pex_clk);
+	tegra_periph_reset_assert(pcie->pcie_xclk);
+	tegra_periph_reset_assert(pcie->afi_clk);
+	tegra_periph_reset_assert(pcie->pex_clk);
 
 	tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
 	tegra_pmc_pcie_xclk_clamp(true);
 }
 
-static int tegra_pcie_power_regate(void)
+static int tegra_pcie_power_regate(struct tegra_pcie_info *pcie)
 {
 	int err;
 
-	tegra_pcie_power_off();
+	tegra_pcie_power_off(pcie);
 
 	tegra_pmc_pcie_xclk_clamp(true);
 
-	tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
-	tegra_periph_reset_assert(tegra_pcie.afi_clk);
+	tegra_periph_reset_assert(pcie->pcie_xclk);
+	tegra_periph_reset_assert(pcie->afi_clk);
 
 	err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
-						tegra_pcie.pex_clk);
+						pcie->pex_clk);
 	if (err) {
-		pr_err("PCIE: powerup sequence failed: %d\n", err);
+		dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
 		return err;
 	}
 
-	tegra_periph_reset_deassert(tegra_pcie.afi_clk);
+	tegra_periph_reset_deassert(pcie->afi_clk);
 
 	tegra_pmc_pcie_xclk_clamp(false);
 
-	clk_enable(tegra_pcie.afi_clk);
-	clk_enable(tegra_pcie.pex_clk);
-	return clk_enable(tegra_pcie.pll_e);
+	clk_enable(pcie->afi_clk);
+	clk_enable(pcie->pex_clk);
+	return clk_enable(pcie->pll_e);
 }
 
-static int tegra_pcie_clocks_get(void)
+static int tegra_pcie_clocks_get(struct tegra_pcie_info *pcie)
 {
 	int err;
 
-	tegra_pcie.pex_clk = clk_get(NULL, "pex");
-	if (IS_ERR(tegra_pcie.pex_clk))
-		return PTR_ERR(tegra_pcie.pex_clk);
+	pcie->pex_clk = clk_get(NULL, "pex");
+	if (IS_ERR(pcie->pex_clk))
+		return PTR_ERR(pcie->pex_clk);
 
-	tegra_pcie.afi_clk = clk_get(NULL, "afi");
-	if (IS_ERR(tegra_pcie.afi_clk)) {
-		err = PTR_ERR(tegra_pcie.afi_clk);
+	pcie->afi_clk = clk_get(NULL, "afi");
+	if (IS_ERR(pcie->afi_clk)) {
+		err = PTR_ERR(pcie->afi_clk);
 		goto err_afi_clk;
 	}
 
-	tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk");
-	if (IS_ERR(tegra_pcie.pcie_xclk)) {
-		err =  PTR_ERR(tegra_pcie.pcie_xclk);
+	pcie->pcie_xclk = clk_get(NULL, "pcie_xclk");
+	if (IS_ERR(pcie->pcie_xclk)) {
+		err = PTR_ERR(pcie->pcie_xclk);
 		goto err_pcie_xclk;
 	}
 
-	tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
-	if (IS_ERR(tegra_pcie.pll_e)) {
-		err = PTR_ERR(tegra_pcie.pll_e);
+	pcie->pll_e = clk_get_sys(NULL, "pll_e");
+	if (IS_ERR(pcie->pll_e)) {
+		err = PTR_ERR(pcie->pll_e);
 		goto err_pll_e;
 	}
 
 	return 0;
 
 err_pll_e:
-	clk_put(tegra_pcie.pcie_xclk);
+	clk_put(pcie->pcie_xclk);
 err_pcie_xclk:
-	clk_put(tegra_pcie.afi_clk);
+	clk_put(pcie->afi_clk);
 err_afi_clk:
-	clk_put(tegra_pcie.pex_clk);
+	clk_put(pcie->pex_clk);
 
 	return err;
 }
 
-static void tegra_pcie_clocks_put(void)
+static void tegra_pcie_clocks_put(struct tegra_pcie_info *pcie)
 {
-	clk_put(tegra_pcie.pll_e);
-	clk_put(tegra_pcie.pcie_xclk);
-	clk_put(tegra_pcie.afi_clk);
-	clk_put(tegra_pcie.pex_clk);
+	clk_put(pcie->pll_e);
+	clk_put(pcie->pcie_xclk);
+	clk_put(pcie->afi_clk);
+	clk_put(pcie->pex_clk);
 }
 
-static int __init tegra_pcie_get_resources(void)
+static int __devinit tegra_pcie_get_resources(struct platform_device *pdev)
 {
-	struct resource *res_mmio = &tegra_pcie.res_mmio;
+	struct tegra_pcie_info *pcie = platform_get_drvdata(pdev);
+	struct resource *regs;
+	struct resource *mmio;
 	int err;
 
-	err = tegra_pcie_clocks_get();
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mmio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+
+	if (!regs || !mmio) {
+		dev_err(&pdev->dev, "failed to get I/O resources\n");
+		return -ENXIO;
+	}
+
+	err = tegra_pcie_clocks_get(pcie);
 	if (err) {
-		pr_err("PCIE: failed to get clocks: %d\n", err);
+		dev_err(&pdev->dev, "failed to get clocks: %d\n", err);
 		return err;
 	}
 
-	err = tegra_pcie_power_regate();
+	err = tegra_pcie_power_regate(pcie);
 	if (err) {
-		pr_err("PCIE: failed to power up: %d\n", err);
+		dev_err(&pdev->dev, "failed to power up: %d\n", err);
 		goto err_pwr_on;
 	}
 
-	tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
-	if (tegra_pcie.regs == NULL) {
-		pr_err("PCIE: Failed to map PCI/AFI registers\n");
+	regs = request_mem_region(regs->start, resource_size(regs), "PCI/AFI");
+	if (regs == NULL) {
+		dev_err(&pdev->dev, "failed to request PCI/AFI region: %d\n", err);
+		goto err_req_reg;
+	}
+
+	pcie->regs = ioremap_nocache(regs->start, resource_size(regs));
+	if (pcie->regs == NULL) {
+		dev_err(&pdev->dev, "failed to map PCI/AFI registers\n");
 		err = -ENOMEM;
 		goto err_map_reg;
 	}
 
-	err = request_resource(&iomem_resource, res_mmio);
-	if (err) {
-		pr_err("PCIE: Failed to request resources: %d\n", err);
+	mmio = request_mem_region(mmio->start, resource_size(mmio), "PCI I/O");
+	if (mmio == NULL) {
+		dev_err(&pdev->dev, "failed to request PCI I/O region: %d\n", err);
 		goto err_req_io;
 	}
 
-	tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
-					     resource_size(res_mmio));
-	if (tegra_pcie_io_base == NULL) {
-		pr_err("PCIE: Failed to map IO\n");
+	pcie->mmio = ioremap_nocache(mmio->start, resource_size(mmio));
+	if (pcie->mmio == NULL) {
+		dev_err(&pdev->dev, "failed to map PCI I/O region\n");
 		err = -ENOMEM;
 		goto err_map_io;
 	}
 
-	err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
-			  IRQF_SHARED, "PCIE", &tegra_pcie);
+	tegra_pcie_io_base = pcie->mmio;
+
+	err = platform_get_irq(pdev, 0);
+	if (err < 0) {
+		dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
+		goto err_irq;
+	}
+
+	pcie->irq = err;
+
+	err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE",
+			  pcie);
 	if (err) {
-		pr_err("PCIE: Failed to register IRQ: %d\n", err);
+		dev_err(&pdev->dev, "failed to register IRQ: %d\n", err);
 		goto err_irq;
 	}
-	set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
 
 	return 0;
 
 err_irq:
-	iounmap(tegra_pcie_io_base);
+	iounmap(pcie->mmio);
 err_map_io:
-	release_resource(&tegra_pcie.res_mmio);
+	release_resource(mmio);
 err_req_io:
-	iounmap(tegra_pcie.regs);
+	iounmap(pcie->regs);
 err_map_reg:
-	tegra_pcie_power_off();
+	release_resource(regs);
+err_req_reg:
+	tegra_pcie_power_off(pcie);
 err_pwr_on:
-	tegra_pcie_clocks_put();
+	tegra_pcie_clocks_put(pcie);
 
 	return err;
 }
 
+static int tegra_pcie_put_resources(struct platform_device *pdev)
+{
+	struct tegra_pcie_info *pcie = platform_get_drvdata(pdev);
+	struct resource *regs;
+	struct resource *mmio;
+
+	free_irq(pcie->irq, pcie);
+
+	iounmap(pcie->mmio);
+	mmio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	release_resource(mmio);
+
+	iounmap(pcie->regs);
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_resource(regs);
+
+	tegra_pcie_power_off(pcie);
+	tegra_pcie_clocks_put(pcie);
+
+	return 0;
+}
+
 /*
  * FIXME: If there are no PCIe cards attached, then calling this function
  * can result in the increase of the bootup time as there are big timeout
  * loops.
  */
 #define TEGRA_PCIE_LINKUP_TIMEOUT	200	/* up to 1.2 seconds */
-static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
+static bool tegra_pcie_check_link(struct tegra_pcie_info *pcie,
+				  struct tegra_pcie_port *pp, int idx,
 				  u32 reset_reg)
 {
 	u32 reg;
@@ -841,7 +886,7 @@ static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
 		}
 
 		if (!timeout)  {
-			pr_err("PCIE: port %d: link down, retrying\n", idx);
+			dev_err(pcie->dev, "port %d: link down, retrying\n", idx);
 			goto retry;
 		}
 
@@ -858,11 +903,11 @@ static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
 
 retry:
 		/* Pulse the PEX reset */
-		reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
-		afi_writel(reg, reset_reg);
+		reg = afi_readl(pcie, reset_reg) | AFI_PEX_CTRL_RST;
+		afi_writel(pcie, reg, reset_reg);
 		mdelay(1);
-		reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
-		afi_writel(reg, reset_reg);
+		reg = afi_readl(pcie, reset_reg) & ~AFI_PEX_CTRL_RST;
+		afi_writel(pcie, reg, reset_reg);
 
 		retries--;
 	} while (retries);
@@ -870,55 +915,111 @@ retry:
 	return false;
 }
 
-static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
+static void __devinit tegra_pcie_add_port(struct tegra_pcie_info *pcie,
+					  int index, u32 offset,
+					  u32 reset_reg)
 {
 	struct tegra_pcie_port *pp;
 
-	pp = tegra_pcie.port + tegra_pcie.num_ports;
+	pp = pcie->port + pcie->num_ports;
 
 	pp->index = -1;
-	pp->base = tegra_pcie.regs + offset;
-	pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
+	pp->base = pcie->regs + offset;
+	pp->link_up = tegra_pcie_check_link(pcie, pp, index, reset_reg);
 
 	if (!pp->link_up) {
 		pp->base = NULL;
-		printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
+		dev_info(pcie->dev, "port %d: link down, ignoring\n", index);
 		return;
 	}
 
-	tegra_pcie.num_ports++;
+	pcie->num_ports++;
 	pp->index = index;
 	pp->root_bus_nr = -1;
 	memset(pp->res, 0, sizeof(pp->res));
 }
 
-int __init tegra_pcie_init(bool init_port0, bool init_port1)
+static int __devinit tegra_pcie_probe(struct platform_device *pdev)
 {
+	struct tegra_pcie_pdata *pdata = pdev->dev.platform_data;
+	struct tegra_pcie_info *pcie;
 	int err;
 
-	if (!(init_port0 || init_port1))
+	if (!pdata->enable_ports[0] && !pdata->enable_ports[1])
 		return -ENODEV;
 
+	pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
+	if (!pcie)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, pcie);
+	pcie->dev = &pdev->dev;
+
 	pcibios_min_mem = 0;
 
-	err = tegra_pcie_get_resources();
-	if (err)
+	err = tegra_pcie_get_resources(pdev);
+	if (err < 0) {
+		dev_err(&pdev->dev, "failed to request resources: %d\n", err);
 		return err;
+	}
 
-	err = tegra_pcie_enable_controller();
+	if (pdata->init) {
+		err = pdata->init(pdev);
+		if (err < 0) {
+			tegra_pcie_put_resources(pdev);
+			return err;
+		}
+	}
+
+	err = tegra_pcie_enable_controller(pcie);
 	if (err)
 		return err;
 
 	/* setup the AFI address translations */
-	tegra_pcie_setup_translations();
+	tegra_pcie_setup_translations(pcie);
+
+	if (pdata->enable_ports[0])
+		tegra_pcie_add_port(pcie, 0, RP0_OFFSET, AFI_PEX0_CTRL);
 
-	if (init_port0)
-		tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
+	if (pdata->enable_ports[1])
+		tegra_pcie_add_port(pcie, 1, RP1_OFFSET, AFI_PEX1_CTRL);
 
-	if (init_port1)
-		tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
+	pcie->hw.nr_controllers = 2;
+	pcie->hw.setup = tegra_pcie_setup;
+	pcie->hw.scan = tegra_pcie_scan_bus;
+	pcie->hw.swizzle = pci_std_swizzle;
+	pcie->hw.map_irq = tegra_pcie_map_irq;
 
-	pci_common_init(&tegra_pcie_hw);
+	pci_common_init(&pcie->hw);
 
 	return 0;
 }
+
+static int __devexit tegra_pcie_remove(struct platform_device *pdev)
+{
+	struct tegra_pcie_pdata *pdata = pdev->dev.platform_data;
+	int err;
+
+	err = tegra_pcie_put_resources(pdev);
+	if (err < 0)
+		return err;
+
+	if (pdata->exit) {
+		err = pdata->exit(pdev);
+		if (err < 0)
+			return err;
+	}
+
+	return 0;
+}
+
+static struct platform_driver tegra_pcie_driver = {
+	.driver = {
+		.name = "tegra-pcie",
+		.owner = THIS_MODULE,
+	},
+	.probe = tegra_pcie_probe,
+	.remove = __devexit_p(tegra_pcie_remove),
+};
+
+module_platform_driver(tegra_pcie_driver);
-- 
1.7.9.3



From thierry.reding at avionic-design.de  Thu Mar  8 09:51:31 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu,  8 Mar 2012 15:51:31 +0100
Subject: [PATCH 11/11] ARM: tegra: pcie: Add device tree support
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331218291-16119-12-git-send-email-thierry.reding@avionic-design.de>

This commit adds support for instantiating the Tegra PCIe controller
from a device tree.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 .../devicetree/bindings/pci/tegra-pcie.txt         |   23 ++++
 arch/arm/boot/dts/tegra20.dtsi                     |    8 ++
 arch/arm/mach-tegra/pcie.c                         |  123 +++++++++++++++++++-
 3 files changed, 151 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/tegra-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/tegra-pcie.txt b/Documentation/devicetree/bindings/pci/tegra-pcie.txt
new file mode 100644
index 0000000..10bbc40
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/tegra-pcie.txt
@@ -0,0 +1,23 @@
+NVIDIA Tegra PCIe controller
+
+Required properties:
+- compatible: "nvidia,tegra20-pcie"
+- reg: physical base address and length of the controller's registers
+- interrupts: the interrupt outputs of the controller
+
+Optional properties:
+- pex-clk-supply: supply voltage for internal reference clock
+- vdd-supply: power supply for controller (1.05V)
+
+Example:
+
+	pci at 80000000 {
+		compatible = "nvidia,tegra20-pcie",
+		reg = <0x80000000 0x400000   /* PCIe AFI registers */
+		       0x80400000 0x010000>; /* PCI I/O space */
+		interrupts = < 0 98 0x04    /* controller interrupt */
+		               0 99 0x04 >; /* MSI interrupt */
+
+		pex-clk-supply = <&ldo0_reg>;
+		vdd-supply = <&pcie_reg>;
+	};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 108e894..9b4692e 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -161,6 +161,14 @@
 		reg = <0x7000f400 0x200>;
 	};
 
+	pci at 80000000 {
+		compatible = "nvidia,tegra20-pcie";
+		reg = <0x80000000 0x400000   /* PCIe AFI registers */
+		       0x80400000 0x010000>; /* PCI I/O space */
+		interrupts = < 0 98 0x04    /* controller interrupt */
+		               0 99 0x04 >; /* MSI interrupt */
+	};
+
 	sdhci at c8000000 {
 		compatible = "nvidia,tegra20-sdhci";
 		reg = <0xc8000000 0x200>;
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 85db9fb..829af6e 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -36,6 +36,8 @@
 #include <linux/delay.h>
 #include <linux/export.h>
 #include <linux/msi.h>
+#include <linux/of.h>
+#include <linux/regulator/consumer.h>
 
 #include <asm/sizes.h>
 #include <asm/mach/irq.h>
@@ -240,6 +242,9 @@ struct tegra_pcie_info {
 	struct irq_domain *msi_domain;
 	struct mutex msi_lock;
 #endif
+
+	struct regulator *pex_clk_supply;
+	struct regulator *vdd_supply;
 };
 
 static inline struct tegra_pcie_info *sys_to_pcie(struct pci_sys_data *sys)
@@ -1170,15 +1175,110 @@ static int tegra_pcie_disable_msi(struct platform_device *pdev)
 }
 #endif
 
+#ifdef CONFIG_OF
+static int tegra_pcie_dt_init(struct platform_device *pdev)
+{
+	struct tegra_pcie_info *pcie = platform_get_drvdata(pdev);
+	int err;
+
+	if (!IS_ERR_OR_NULL(pcie->vdd_supply)) {
+		err = regulator_enable(pcie->vdd_supply);
+		if (err < 0) {
+			dev_err(&pdev->dev,
+				"failed to enable VDD regulator: %d\n", err);
+			return err;
+		}
+	}
+
+	if (!IS_ERR_OR_NULL(pcie->pex_clk_supply)) {
+		err = regulator_enable(pcie->pex_clk_supply);
+		if (err < 0) {
+			dev_err(&pdev->dev,
+				"failed to enable pex-clk regulator: %d\n",
+				err);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+static int tegra_pcie_dt_exit(struct platform_device *pdev)
+{
+	struct tegra_pcie_info *pcie = platform_get_drvdata(pdev);
+	int err;
+
+	if (!IS_ERR_OR_NULL(pcie->pex_clk_supply)) {
+		err = regulator_disable(pcie->pex_clk_supply);
+		if (err < 0) {
+			dev_err(&pdev->dev,
+				"failed to disable pex-clk regulator: %d\n",
+				err);
+			return err;
+		}
+	}
+
+	if (!IS_ERR_OR_NULL(pcie->vdd_supply)) {
+		err = regulator_disable(pcie->vdd_supply);
+		if (err < 0) {
+			dev_err(&pdev->dev,
+				"failed to disable VDD regulator: %d\n", err);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+static struct tegra_pcie_pdata *tegra_pcie_parse_dt(struct platform_device *pdev)
+{
+	struct tegra_pcie_info *pcie = platform_get_drvdata(pdev);
+	struct device_node *node = pdev->dev.of_node;
+	struct tegra_pcie_pdata *pdata;
+	unsigned int i;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return NULL;
+
+	pdata->init = tegra_pcie_dt_init;
+	pdata->exit = tegra_pcie_dt_exit;
+
+	if (of_find_property(node, "vdd-supply", NULL)) {
+		pcie->vdd_supply = regulator_get(&pdev->dev, "vdd");
+		if (IS_ERR_OR_NULL(pcie->vdd_supply))
+			return ERR_PTR(-EPROBE_DEFER);
+	}
+
+	if (of_find_property(node, "pex-clk-supply", NULL)) {
+		pcie->pex_clk_supply = regulator_get(&pdev->dev, "pex-clk");
+		if (IS_ERR_OR_NULL(pcie->pex_clk_supply))
+			return ERR_PTR(-EPROBE_DEFER);
+	}
+
+	for (i = 0; i < TEGRA_PCIE_MAX_PORTS; i++)
+		pdata->enable_ports[i] = true;
+
+	return pdata;
+}
+
+static struct of_device_id tegra_pcie_of_match[] = {
+	{ .compatible = "nvidia,tegra20-pcie", },
+	{ },
+};
+#else
+static struct tegra_pcie_pdata *tegra_pcie_parse_dt(struct platform_device *pdev)
+{
+	return NULL;
+}
+#endif
+
 static int __devinit tegra_pcie_probe(struct platform_device *pdev)
 {
 	struct tegra_pcie_pdata *pdata = pdev->dev.platform_data;
 	struct tegra_pcie_info *pcie;
 	int err;
 
-	if (!pdata->enable_ports[0] && !pdata->enable_ports[1])
-		return -ENODEV;
-
 	pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
 	if (!pcie)
 		return -ENOMEM;
@@ -1186,6 +1286,18 @@ static int __devinit tegra_pcie_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, pcie);
 	pcie->dev = &pdev->dev;
 
+	if (!pdata && pdev->dev.of_node) {
+		pdata = tegra_pcie_parse_dt(pdev);
+		if (IS_ERR(pdata))
+			return PTR_ERR(pdata);
+	}
+
+	if (!pdata)
+		return -ENODEV;
+
+	if (!pdata->enable_ports[0] && !pdata->enable_ports[1])
+		return -ENODEV;
+
 	pcibios_min_mem = 0;
 
 	err = tegra_pcie_get_resources(pdev);
@@ -1232,6 +1344,7 @@ static int __devinit tegra_pcie_probe(struct platform_device *pdev)
 
 static int __devexit tegra_pcie_remove(struct platform_device *pdev)
 {
+	struct tegra_pcie_info *pcie = platform_get_drvdata(pdev);
 	struct tegra_pcie_pdata *pdata = pdev->dev.platform_data;
 	int err;
 
@@ -1249,6 +1362,9 @@ static int __devexit tegra_pcie_remove(struct platform_device *pdev)
 			return err;
 	}
 
+	regulator_put(pcie->pex_clk_supply);
+	regulator_put(pcie->vdd_supply);
+
 	return 0;
 }
 
@@ -1256,6 +1372,7 @@ static struct platform_driver tegra_pcie_driver = {
 	.driver = {
 		.name = "tegra-pcie",
 		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(tegra_pcie_of_match),
 	},
 	.probe = tegra_pcie_probe,
 	.remove = __devexit_p(tegra_pcie_remove),
-- 
1.7.9.3



From broonie at opensource.wolfsonmicro.com  Thu Mar  8 10:06:07 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 8 Mar 2012 15:06:07 +0000
Subject: [PATCH 05/11] tps6586x: Add device-tree support
In-Reply-To: <1331218291-16119-6-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-6-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120308150607.GP3638@opensource.wolfsonmicro.com>

On Thu, Mar 08, 2012 at 03:51:25PM +0100, Thierry Reding wrote:

> +- gpio-controller: mark the device as a GPIO controller
> +- regulators: list of regulators provided by this controller, must be in the
> +  following order:
> +    SM0, SM1, SM2, LDO0, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9

This ordering requirement is fairly sad, if there are unused regulators
they still need to be listed even though...

> +			sm0_reg: sm0 {
> +				regulator-min-microvolt = < 725000>;
> +				regulator-max-microvolt = <1500000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			sm1_reg: sm1 {

...they all seem to be explicitly named in the device tree so presumably
there's enough information in there for the driver to pick any set of
regulators in any order.  This would be much nicer to use.

Otherwise this looks good.
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From thierry.reding at avionic-design.de  Thu Mar  8 10:15:46 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 8 Mar 2012 16:15:46 +0100
Subject: [PATCH 05/11] tps6586x: Add device-tree support
In-Reply-To: <20120308150607.GP3638@opensource.wolfsonmicro.com>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-6-git-send-email-thierry.reding@avionic-design.de>
 <20120308150607.GP3638@opensource.wolfsonmicro.com>
Message-ID: <20120308151545.GA23934@avionic-0098.mockup.avionic-design.de>

* Mark Brown wrote:
> On Thu, Mar 08, 2012 at 03:51:25PM +0100, Thierry Reding wrote:
> 
> > +- gpio-controller: mark the device as a GPIO controller
> > +- regulators: list of regulators provided by this controller, must be in the
> > +  following order:
> > +    SM0, SM1, SM2, LDO0, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9
> 
> This ordering requirement is fairly sad, if there are unused regulators
> they still need to be listed even though...
> 
> > +			sm0_reg: sm0 {
> > +				regulator-min-microvolt = < 725000>;
> > +				regulator-max-microvolt = <1500000>;
> > +				regulator-boot-on;
> > +				regulator-always-on;
> > +			};
> > +
> > +			sm1_reg: sm1 {
> 
> ...they all seem to be explicitly named in the device tree so presumably
> there's enough information in there for the driver to pick any set of
> regulators in any order.  This would be much nicer to use.

I don't like it much either. The only reason that requirement exists is
because it makes the assignment of the regulator ID (as defined in the
include/linux/mfd/tps6586x.h header) very trivial. Would it be better to
look up the ID based on the node name (sm0 --> TPS6586X_ID_SM_0, ...)?

Then the only requirement would be that the names match.

Thierry
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From olof at lixom.net  Thu Mar  8 10:16:59 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 8 Mar 2012 07:16:59 -0800
Subject: [GIT PULL] Samsung Cleanup EXYNOS clock for v3.4
In-Reply-To: <4F589474.8050609@samsung.com>
References: <4F589474.8050609@samsung.com>
Message-ID: <CAOesGMiWOChuMjLQTK1pGys+oXCc4A=HO-2_=37rh3M6pgUP_g@mail.gmail.com>

Hi,

On Thu, Mar 8, 2012 at 3:13 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:

> Kukjin Kim (2):
> ? ? ?ARM: EXYNOS: cleanup clock part for new EXYNOS SoCs

This is one large commit that does many things in one change. As the
patch message says:

ARM: EXYNOS: cleanup clock part for new EXYNOS SoCs

- the prefix of clk register replace S5P_ with EXYNOS4_
- move mach-exynos/clock.c to mach-exynos/clock-exynos4.c
- according to moving clock-exynos4.c,
  move <mach/exynos4-clock.h> to "clock-exynos4.h"
- add prefix exynos4_ on clk declaration

It makes it hard to review, especially when you combine a move with
other changes. It's better to do the move in a separate commit that
doesn't change code (or only changes very very little) and then do the
other changes in separate commits later.


-Olof


From broonie at opensource.wolfsonmicro.com  Thu Mar  8 10:17:56 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 8 Mar 2012 15:17:56 +0000
Subject: [PATCH 05/11] tps6586x: Add device-tree support
In-Reply-To: <20120308151545.GA23934@avionic-0098.mockup.avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-6-git-send-email-thierry.reding@avionic-design.de>
 <20120308150607.GP3638@opensource.wolfsonmicro.com>
 <20120308151545.GA23934@avionic-0098.mockup.avionic-design.de>
Message-ID: <20120308151756.GQ3638@opensource.wolfsonmicro.com>

On Thu, Mar 08, 2012 at 04:15:46PM +0100, Thierry Reding wrote:
> * Mark Brown wrote:

> > ...they all seem to be explicitly named in the device tree so presumably
> > there's enough information in there for the driver to pick any set of
> > regulators in any order.  This would be much nicer to use.

> I don't like it much either. The only reason that requirement exists is
> because it makes the assignment of the regulator ID (as defined in the
> include/linux/mfd/tps6586x.h header) very trivial. Would it be better to
> look up the ID based on the node name (sm0 --> TPS6586X_ID_SM_0, ...)?

> Then the only requirement would be that the names match.

Yes, that's going to be more code but much nicer for users.
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From robherring2 at gmail.com  Thu Mar  8 10:22:05 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 08 Mar 2012 09:22:05 -0600
Subject: [PATCH 00/11] ARM: tegra: Add PCIe device tree support
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F58CE9D.3070605@gmail.com>

On 03/08/2012 08:51 AM, Thierry Reding wrote:
> This patch series adds support for device tree based probing of the PCIe
> controller found on Tegra SoCs.
> 
> Patches 1 and 2 have already been posted by Grant and Mark respectively
> but I've included them here for reference. Both patches are dependencies
> for the subsequent patches.
> 
> Patches 3, 4 and 5 add support for obtaining the regulators required to
> power the PCIe controller from the device tree. Patches 6 and 7 are
> required to make some common PCI functions available after the init
> phase because the deferred probing will postpone the probing of the PCIe
> controller driver until that point.
> 
> Patches 8 and 9 make the PCIe controller code available as a driver and
> add the corresponding platform devices to the boards that enable PCIe
> (Harmony and TrimSlice). Patch 10 adds MSI support and patch 11 finally
> adds a device tree binding with documentation.
> 
> The code in patch 10 (MSI support) is based on the Vibrante kernel and I
> wasn't able to get a proper Signed-off-by or even copyright information.
> Perhaps somebody at NVIDIA can find out?
> 
> Thierry
> 
> Grant Likely (1):
>   drivercore: Add driver probe deferral mechanism
> 
> Mark Brown (1):
>   regulator: Support driver probe deferral
> 
> Thierry Reding (9):
>   regulator: fixed: Support driver probe deferral
>   regulator: tps6586x: fix typo in debug message
>   tps6586x: Add device-tree support
>   PCI: Keep pci_fixup_irqs() around after init
>   ARM: pci: Keep pci_common_init() around after init
>   ARM: tegra: Move tegra_pcie_xclk_clamp() to PMC
>   ARM: tegra: Rewrite PCIe support as a driver
>   ARM: tegra: pcie: Add MSI support
>   ARM: tegra: pcie: Add device tree support
> 
>  .../devicetree/bindings/pci/tegra-pcie.txt         |   23 +
>  .../devicetree/bindings/regulator/tps6586x.txt     |   98 +++
>  arch/arm/boot/dts/tegra20.dtsi                     |    8 +
>  arch/arm/kernel/bios32.c                           |    4 +-
>  arch/arm/mach-tegra/Kconfig                        |    1 +
>  arch/arm/mach-tegra/board-harmony-pcie.c           |   38 +-
>  arch/arm/mach-tegra/board-harmony.c                |    1 +
>  arch/arm/mach-tegra/board-harmony.h                |    1 +
>  arch/arm/mach-tegra/board-trimslice.c              |   16 +-
>  arch/arm/mach-tegra/board.h                        |   11 +-
>  arch/arm/mach-tegra/devices.c                      |   32 +
>  arch/arm/mach-tegra/devices.h                      |    1 +
>  arch/arm/mach-tegra/include/mach/iomap.h           |    6 +
>  arch/arm/mach-tegra/include/mach/irqs.h            |    5 +-
>  arch/arm/mach-tegra/pcie.c                         |  895 +++++++++++++++-----
>  arch/arm/mach-tegra/pmc.c                          |   16 +
>  arch/arm/mach-tegra/pmc.h                          |    1 +
>  drivers/base/base.h                                |    1 +
>  drivers/base/core.c                                |    2 +
>  drivers/base/dd.c                                  |  138 ++-
>  drivers/mfd/tps6586x.c                             |   66 ++
>  drivers/pci/setup-irq.c                            |    4 +-
>  drivers/regulator/core.c                           |    4 +-
>  drivers/regulator/fixed.c                          |   14 +-
>  drivers/regulator/tps6586x-regulator.c             |    4 +-
>  include/linux/device.h                             |    5 +
>  include/linux/errno.h                              |    1 +
>  include/linux/mfd/tps6586x.h                       |    1 +
>  28 files changed, 1136 insertions(+), 261 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/pci/tegra-pcie.txt
>  create mode 100644 Documentation/devicetree/bindings/regulator/tps6586x.txt

There is a whole bunch of PCI DT code sitting in the powerpc tree that
probably needs to be moved to common location and used here.

This looks way too simple to be what's needed if I compare to PCI
bindings in powerpc dts files.

Rob


From robherring2 at gmail.com  Thu Mar  8 10:24:25 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 08 Mar 2012 09:24:25 -0600
Subject: [PATCH 5/6] ARM: at91: add ram controller DT support
In-Reply-To: <20120308141000.GF27213@game.jcrosoft.org>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <1330718048-9314-5-git-send-email-plagnioj@jcrosoft.com>
 <4F57BDCE.1050708@gmail.com> <20120308061324.GE27213@game.jcrosoft.org>
 <4F58BE4F.5080009@gmail.com> <20120308141000.GF27213@game.jcrosoft.org>
Message-ID: <4F58CF29.6020906@gmail.com>

On 03/08/2012 08:10 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 08:12 Thu 08 Mar     , Rob Herring wrote:
>> On 03/08/2012 12:13 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>>> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>> index a297a77..88e43d5 100644
>>>>> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>> @@ -55,11 +55,6 @@
>>>>>  #define AT91SAM9X5_BASE_USART2	0xf8024000
>>>>>  
>>>>>  /*
>>>>> - * System Peripherals
>>>>> - */
>>>>> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
>>>>> -
>>>>> -/*
>>>>>   * Base addresses for early serial code (uncompress.h)
>>>>>   */
>>>>>  #define AT91_DBGU	AT91_BASE_DBGU0
>>>>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
>>>>> index 3e48b59..f86450d 100644
>>>>> --- a/arch/arm/mach-at91/setup.c
>>>>> +++ b/arch/arm/mach-at91/setup.c
>>>>> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
>>>>>  	of_node_put(np);
>>>>>  }
>>>>>  
>>>>> +static struct of_device_id ramc_ids[] = {
>>>>> +	{ .compatible = "atmel,at91sam9260-sdramc" },
>>>>> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
>>>>> +	{ /*sentinel*/ }
>>>>> +};
>>>>> +
>>>>> +static void at91_dt_ramc(void)
>>>>> +{
>>>>> +	struct device_node *np;
>>>>> +
>>>>> +	np = of_find_matching_node(NULL, ramc_ids);
>>>>> +	if (!np)
>>>>> +		panic("unable to find compatible ram conroller node in dtb\n");
>>>>
>>>> You really can't boot if this fails? A WARN is better if it allows you
>>>> to boot until at least your console is actually up.
>>> if the restart is called you will have a oops so no it's a basic mandatory
>>> device on at91
>>>
>>
>> But you may never see the panic message because your console is not up.
>> If you WARN and can continue to boot, then the user can see the problem
>> and fix it. Otherwise you get nothing and have to go rebuild and turn on
>> earlyprintk.
> yeah agreed but if the restart id use before the console is enable you will
> have the same issue. the ramc controller are basic device so people usally
> don't touch it except you add a SoC support.
> 
> so I prefer to panic
> 

Then panic in the restart code if it doesn't have something it needs.

Rob



From jp.francois at cynove.com  Thu Mar  8 10:26:56 2012
From: jp.francois at cynove.com (jean-philippe francois)
Date: Thu, 8 Mar 2012 16:26:56 +0100
Subject: Regression in 3.2.9 for omap-serial (at least)
In-Reply-To: <alpine.LFD.2.02.1203081246130.2742@ionos>
References: <lyk42vxsz2.fsf@ensc-virt.intern.sigma-chemnitz.de>
 <alpine.LFD.2.02.1203081246130.2742@ionos>
Message-ID: <CAGGh5h3-1XhMO1-jiBdUJYgh4unRcPonvp=zcXLKMJBfS+qpuQ@mail.gmail.com>

Le 8 mars 2012 12:46, Thomas Gleixner <tglx at linutronix.de> a ?crit :
> On Thu, 8 Mar 2012, Enrico Scholz wrote:
>> Hi,
>>
>> the commit "genirq: Unmask oneshot irqs when thread was not woken"[1]
>> breaks at least the omap-serial driver which requests a shared interrupt
>
> Fixed with 52abb700e16a9a

How can I find it ?
I tried searching in various tree on git.kernel.org,
but could not find the fix.
>
> Thanks,
>
> ? ? ? ?tglx
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From alexg at meprolight.com  Thu Mar  8 10:36:05 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Thu, 8 Mar 2012 17:36:05 +0200
Subject: I.MX35 PDK
In-Reply-To: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8913@MEP-EXCH.meprolight.com>
References: <CAOMZO5DnP7+zupy9vwBPS0+2XtKM1+nLbwCqBzuCqEG5OWbZRQ@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A28@MEP-EXCH.meprolight.com>,
 <CAOMZO5Amo0XFf+TV7PprCL079C5Y0qKmo+k-FfShU7k4SG7W6Q@mail.gmail.com>,
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8913@MEP-EXCH.meprolight.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8918@MEP-EXCH.meprolight.com>


>On my mx31pdk I get the same dmaengine errors and the ov2640 does work fine.
>I think you can go ahead and try to use the camera on the mx35pdk now.
>You can try:

>gst-launch -v v4l2src device=/dev/video0 !
>video/x-raw-yuv,width=320,height=240,framerate=25/1 ! ffmpegcolorspace
>! fbdevsink

<<Thank Fabio I'll try to check it.

I tried to test it, everything is fine,  just do not see the video on display.
Here can see messages:

Setting pipeline to PAUSED ...mx3-camera mx3-camera.0: MX3 Camera driver attached to camera 0
/GstPipeline:pipeline0/GstV4l2Src:v4l2src0.GstPad:src: caps = video/x-raw-yuv, format=(fourcc)UYVY, framerate=(fraction)25/1, width=(int)320, height=(int)240, interlaced=(boolean)false
Pipeline is live and does not need PREROLL ...
WARNING: from element /GstPipeline:pipeline0/GstV4l2Src:v4l2src0: Could not get parameters on device '/dev/video0'
Additional debug info:
v4l2src_calls.c(240): gst_v4l2src_set_capture (): /GstPipeline:pipeline0/GstV4l2Src:v4l2src0:
system error: Invalid argument
Setting pipeline to PLAYING ...
New clock: GstSystemClock

It works well :-) 
gst-launch videotestsrc ! fbdevsink

Regards
Alex Gershgorin


From thierry.reding at avionic-design.de  Thu Mar  8 10:43:59 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 8 Mar 2012 16:43:59 +0100
Subject: [PATCH 00/11] ARM: tegra: Add PCIe device tree support
In-Reply-To: <4F58CE9D.3070605@gmail.com>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <4F58CE9D.3070605@gmail.com>
Message-ID: <20120308154359.GA544@avionic-0098.mockup.avionic-design.de>

* Rob Herring wrote:
> There is a whole bunch of PCI DT code sitting in the powerpc tree that
> probably needs to be moved to common location and used here.
> 
> This looks way too simple to be what's needed if I compare to PCI
> bindings in powerpc dts files.

My particular setup may be much simpler than the average PowerPC machine. The
patchset is only what I need to get PCIe running on the platform, which has
an FPGA connected to the Tegra via PCIe. For instance there is no legacy
interrupt support (only MSI), so interrupt remapping is not required. I also
know that OF nodes are not properly hooked up with the PCI devices yet, which
I will need, among other things, to provide platform data for an SPI flash
connected to an SPI master implemented within the FPGA. I also haven't looked
at specifying the memory ranges via the device tree.

So quite a lot may still be missing, but does that prevent any of this from
being added to mainline? Things can be added on an as-needed basis, can't
they?

Thierry
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From thierry.reding at avionic-design.de  Thu Mar  8 10:45:03 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 8 Mar 2012 16:45:03 +0100
Subject: [PATCH 05/11] tps6586x: Add device-tree support
In-Reply-To: <20120308151756.GQ3638@opensource.wolfsonmicro.com>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-6-git-send-email-thierry.reding@avionic-design.de>
 <20120308150607.GP3638@opensource.wolfsonmicro.com>
 <20120308151545.GA23934@avionic-0098.mockup.avionic-design.de>
 <20120308151756.GQ3638@opensource.wolfsonmicro.com>
Message-ID: <20120308154502.GA4617@avionic-0098.mockup.avionic-design.de>

* Mark Brown wrote:
> On Thu, Mar 08, 2012 at 04:15:46PM +0100, Thierry Reding wrote:
> > * Mark Brown wrote:
> 
> > > ...they all seem to be explicitly named in the device tree so presumably
> > > there's enough information in there for the driver to pick any set of
> > > regulators in any order.  This would be much nicer to use.
> 
> > I don't like it much either. The only reason that requirement exists is
> > because it makes the assignment of the regulator ID (as defined in the
> > include/linux/mfd/tps6586x.h header) very trivial. Would it be better to
> > look up the ID based on the node name (sm0 --> TPS6586X_ID_SM_0, ...)?
> 
> > Then the only requirement would be that the names match.
> 
> Yes, that's going to be more code but much nicer for users.

Okay, I'll add that for the next round.

Thierry
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From festevam at gmail.com  Thu Mar  8 10:46:38 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 8 Mar 2012 12:46:38 -0300
Subject: I.MX35 PDK
In-Reply-To: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8918@MEP-EXCH.meprolight.com>
References: <CAOMZO5DnP7+zupy9vwBPS0+2XtKM1+nLbwCqBzuCqEG5OWbZRQ@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A28@MEP-EXCH.meprolight.com>
 <CAOMZO5Amo0XFf+TV7PprCL079C5Y0qKmo+k-FfShU7k4SG7W6Q@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8913@MEP-EXCH.meprolight.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8918@MEP-EXCH.meprolight.com>
Message-ID: <CAOMZO5A6T+WdOE41Wx6Nctwz9wk8FKaxzjbAt_woZkCnuodNYg@mail.gmail.com>

On 3/8/12, Alex Gershgorin <alexg at meprolight.com> wrote:

> Setting pipeline to PAUSED ...mx3-camera mx3-camera.0: MX3 Camera driver
> attached to camera 0
> /GstPipeline:pipeline0/GstV4l2Src:v4l2src0.GstPad:src: caps =
> video/x-raw-yuv, format=(fourcc)UYVY, framerate=(fraction)25/1,
> width=(int)320, height=(int)240, interlaced=(boolean)false
> Pipeline is live and does not need PREROLL ...
> WARNING: from element /GstPipeline:pipeline0/GstV4l2Src:v4l2src0: Could not
> get parameters on device '/dev/video0'
> Additional debug info:
> v4l2src_calls.c(240): gst_v4l2src_set_capture ():
> /GstPipeline:pipeline0/GstV4l2Src:v4l2src0:
> system error: Invalid argument

Looks like some kind of Gstreamer issue.

You could also try:
gst-launch -v v4l2src ! fbdevsink

or gst-launch -v v4l2src ! filesink location= raw.data

If you still get Gstreamer issues you can try v4l2grab utility:
http://git.linuxtv.org/v4l-utils.git/blob/de42be924c5154732bc8dfd1c8bc7812985ab2d6?f=contrib/test/v4l2grab.c

Good luck!


From balajitk at ti.com  Thu Mar  8 10:53:10 2012
From: balajitk at ti.com (T Krishnamoorthy, Balaji)
Date: Thu, 8 Mar 2012 21:23:10 +0530
Subject: [PATCH 4/4] mmc: omap_hsmmc: Simplify init for twl6030 MMC card
 detect
In-Reply-To: <m2lincifj9.fsf@bob.laptop.org>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185535.29210.71546.stgit@kaulin.local>
 <4F50643B.9050500@ti.com> <20120302172251.GJ18901@atomide.com>
 <4F548457.5050205@ti.com>
 <CANrkHUZysOnHKKUuLm0Vbo1KsNp0yUd=udjGvQ43=gTTXbWeCw@mail.gmail.com>
 <CANrkHUaYDpv=p0p81oKWCoewyjheyZYkCqvZY7_ZQxWi_=8YFw@mail.gmail.com>
 <m2lincifj9.fsf@bob.laptop.org>
Message-ID: <CANrkHUbsiTz9+cRM83845=nYp82BSyje+ikV_sg3BT+64uD2XA@mail.gmail.com>

On Wed, Mar 7, 2012 at 9:12 PM, Chris Ball <cjb at laptop.org> wrote:
> Hi Balaji,
>
> On Wed, Mar 07 2012, T Krishnamoorthy, Balaji wrote:
>> OMAP4 and OMAP3 HSMMC IP registers differ by 0x100 offset.
>> Addng the offset to platform_device resource structure
>> increments the start address for every insmod operation.
>> MMC command fails on re-insertion as module due incorrect register base.
>> Fix this by updating the ioremap base address only.
>>
>> Signed-off-by: Balaji T K <balajitk at ti.com>
>
> Is this a regression, or has it never worked in mainline?

Not a regression introduced in current merge window.
It happens on re-insertion of module.
will post a patch with $SUBJECT

>
>> Note: ?eMMC detection is still failing on resertion due to card vcc
>> power off on rmmod
>
> And this?

This issue was hidden and uncovered after this fix.
This problem is Vcc being powered off without sleep command.

>
> Thanks,
>
> - Chris.
> --
> Chris Ball ? <cjb at laptop.org> ? <http://printf.net/>
> One Laptop Per Child


From robherring2 at gmail.com  Thu Mar  8 10:58:13 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 08 Mar 2012 09:58:13 -0600
Subject: [PATCH v2 1/4] mmc: omap_hsmmc: Convert hsmmc driver to use device
 tree
In-Reply-To: <4F582B79.60001@ti.com>
References: <1329998490-27555-1-git-send-email-rnayak@ti.com>
 <1329998490-27555-2-git-send-email-rnayak@ti.com> <4F582B79.60001@ti.com>
Message-ID: <4F58D715.5080708@gmail.com>

On 03/07/2012 09:46 PM, Rajendra Nayak wrote:
> Hi Rob/Grant,
> 
> On Thursday 23 February 2012 05:31 PM, Rajendra Nayak wrote:
>> Define dt bindings for the ti-omap-hsmmc, and adapt
>> the driver to extract data (which was earlier passed as
>> platform_data) from device tree.
> 
> Any comments on these bindings for omap hsmmc? All the dependent
> patches/series on which this series was based have now made it to
> the respective -next of Mark and Chris.
> 

Acked-by: Rob Herring <rob.herring at calxeda.com>

> 
>>
>> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
>> ---
>>   .../devicetree/bindings/mmc/ti-omap-hsmmc.txt      |   31 +++++++++
>>   drivers/mmc/host/omap_hsmmc.c                      |   68
>> ++++++++++++++++++++
>>   2 files changed, 99 insertions(+), 0 deletions(-)
>>   create mode 100644
>> Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>> b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>> new file mode 100644
>> index 0000000..e4fa8f0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>> @@ -0,0 +1,31 @@
>> +* TI Highspeed MMC host controller for OMAP
>> +
>> +The Highspeed MMC Host Controller on TI OMAP family
>> +provides an interface for MMC, SD, and SDIO types of memory cards.
>> +
>> +Required properties:
>> +- compatible:
>> + Should be "ti,omap2-hsmmc", for OMAP2/3 controllers
>> + Should be "ti,omap4-hsmmc", for OMAP4 controllers
>> +- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
>> +- reg : should contain hsmmc registers location and length
>> +
>> +Optional properties:
>> +ti,dual-volt: boolean, supports dual voltage cards
>> +<supply-name>-supply: phandle to the regulator device tree node
>> +"supply-name" examples are "vmmc", "vmmc_aux" etc
>> +ti,bus-width: Number of data lines, default assumed is 1 if the
>> property is missing.
>> +cd-gpios: GPIOs for card detection
>> +wp-gpios: GPIOs for write protection
>> +ti,non-removable: non-removable slot (like eMMC)
>> +
>> +Example:
>> +    mmc1: mmc at 0x4809c000 {
>> +        compatible = "ti,omap4-hsmmc";
>> +        reg =<0x4809c000 0x400>;
>> +        ti,hwmods = "mmc1";
>> +        ti,dual-volt;
>> +        ti,bus-width =<4>;
>> +        vmmc-supply =<&vmmc>; /* phandle to regulator node */
>> +        ti,non-removable;
>> +    };
>> diff --git a/drivers/mmc/host/omap_hsmmc.c
>> b/drivers/mmc/host/omap_hsmmc.c
>> index 35f6dc1..0c93d58 100644
>> --- a/drivers/mmc/host/omap_hsmmc.c
>> +++ b/drivers/mmc/host/omap_hsmmc.c
>> @@ -26,6 +26,9 @@
>>   #include<linux/platform_device.h>
>>   #include<linux/timer.h>
>>   #include<linux/clk.h>
>> +#include<linux/of.h>
>> +#include<linux/of_gpio.h>
>> +#include<linux/of_device.h>
>>   #include<linux/mmc/host.h>
>>   #include<linux/mmc/core.h>
>>   #include<linux/mmc/mmc.h>
>> @@ -1718,6 +1721,46 @@ static void omap_hsmmc_debugfs(struct mmc_host
>> *mmc)
>>
>>   #endif
>>
>> +#ifdef CONFIG_OF
>> +static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct
>> device *dev)
>> +{
>> +    struct omap_mmc_platform_data *pdata;
>> +    struct device_node *np = dev->of_node;
>> +    u32 bus_width;
>> +
>> +    pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
>> +    if (!pdata)
>> +        return NULL; /* out of memory */
>> +
>> +    if (of_find_property(np, "ti,dual-volt", NULL))
>> +        pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
>> +
>> +    /* This driver only supports 1 slot */
>> +    pdata->nr_slots = 1;
>> +    pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
>> +    pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
>> +
>> +    if (of_find_property(np, "ti,non-removable", NULL)) {
>> +        pdata->slots[0].nonremovable = true;
>> +        pdata->slots[0].no_regulator_off_init = true;
>> +    }
>> +    of_property_read_u32(np, "ti,bus-width",&bus_width);
>> +    if (bus_width == 4)
>> +        pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
>> +    else if (bus_width == 8)
>> +        pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
>> +    return pdata;
>> +}
>> +#else
>> +static inline struct omap_mmc_platform_data
>> +            *of_get_hsmmc_pdata(struct device *dev)
>> +{
>> +    return NULL;
>> +}
>> +#endif
>> +
>> +static const struct of_device_id omap_mmc_of_match[];
>> +
>>   static int __init omap_hsmmc_probe(struct platform_device *pdev)
>>   {
>>       struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
>> @@ -1725,6 +1768,14 @@ static int __init omap_hsmmc_probe(struct
>> platform_device *pdev)
>>       struct omap_hsmmc_host *host = NULL;
>>       struct resource *res;
>>       int ret, irq;
>> +    const struct of_device_id *match;
>> +
>> +    match = of_match_device(omap_mmc_of_match,&pdev->dev);
>> +    if (match) {
>> +        pdata = of_get_hsmmc_pdata(&pdev->dev);
>> +        if (match->data)
>> +            pdata->reg_offset = *(u16 *)match->data;
>> +    }
>>
>>       if (pdata == NULL) {
>>           dev_err(&pdev->dev, "Platform Data is missing\n");
>> @@ -2120,12 +2171,29 @@ static struct dev_pm_ops omap_hsmmc_dev_pm_ops
>> = {
>>       .runtime_resume = omap_hsmmc_runtime_resume,
>>   };
>>
>> +#if defined(CONFIG_OF)
>> +static u16 omap4_reg_offset = 0x100;
>> +
>> +static const struct of_device_id omap_mmc_of_match[] = {
>> +    {
>> +        .compatible = "ti,omap2-hsmmc",
>> +    },
>> +    {
>> +        .compatible = "ti,omap4-hsmmc",
>> +        .data =&omap4_reg_offset,
>> +    },
>> +    {},
>> +}
>> +MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
>> +#endif
>> +
>>   static struct platform_driver omap_hsmmc_driver = {
>>       .remove        = omap_hsmmc_remove,
>>       .driver        = {
>>           .name = DRIVER_NAME,
>>           .owner = THIS_MODULE,
>>           .pm =&omap_hsmmc_dev_pm_ops,
>> +        .of_match_table = of_match_ptr(omap_mmc_of_match),
>>       },
>>   };
>>
> 



From arnd at arndb.de  Thu Mar  8 11:03:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 8 Mar 2012 16:03:12 +0000
Subject: [PATCH 0/3] introduce stmp-style devices
In-Reply-To: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
References: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
Message-ID: <201203081603.12817.arnd@arndb.de>

On Wednesday 07 March 2012, Wolfram Sang wrote:
> 
> This series makes support for a certain type of devices mach independant. We
> want that because such devices (having a special register layout) have been
> found in mach-mxs and mach-mx6 meanwhile. Please refer to patch 1/3 for a more
> detailed description.
> 
> Patch 1/3 adds the basic support and is of main interest to get upstream.
> Patches 2/3 and 3/3 are usage examples and will be send to the relevant
> subsystems once the basic support is accepted.
> 
> Main changes since the RFC:
> 
> * renamed the macros to STMP_OFFSET_*
> * rebased to 3.3-rc6
> 
> Tested with a TX28 board.

I think having the stmp_device code is good, but I'm not sure about the
location in drivers/base, which is otherwise reserved for anything related
to 'struct device'. How about putting the same file into lib/stmpregs.c?

	Arnd


From arnd at arndb.de  Thu Mar  8 11:10:21 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 8 Mar 2012 16:10:21 +0000
Subject: [GIT PULL v4] ARM: kirkwood: fdt conversion progress
In-Reply-To: <20120307221012.GH5050@titan.lakedaemon.net>
References: <20120307221012.GH5050@titan.lakedaemon.net>
Message-ID: <201203081610.21493.arnd@arndb.de>

On Wednesday 07 March 2012, Jason Cooper wrote:
> The following changes since commit d65b4e98d7ea3038b767b70fe8be959b2913f16d:
> 
>   Linux 3.3-rc3 (2012-02-08 19:21:53 -0800)
> 
> are available in the git repository at:
>   git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt
> 
> ---
> Arnd,
> 
> My first two should match up with what you have already, the only
> outlier is that Jean-Christophe's patch is needed, but I don't think
> everyone agrees on it yet.
> 

Right now, Olof is handling the pull requests. I would suggest that he
can use your branch to replace the current staging branch but still keep
it in staging until everyone agrees or you replace it with a better version.

	Arnd


From arnd at arndb.de  Thu Mar  8 11:16:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 8 Mar 2012 16:16:12 +0000
Subject: linux-next: manual merge of the arm-soc tree with the omap_dss2
 tree
In-Reply-To: <20120308170048.f1a992bca2ca2d93fa9747bf@canb.auug.org.au>
References: <20120308170048.f1a992bca2ca2d93fa9747bf@canb.auug.org.au>
Message-ID: <201203081616.12510.arnd@arndb.de>

On Thursday 08 March 2012, Stephen Rothwell wrote:
> Hi all,
> 
> Today's linux-next merge of the arm-soc tree got a conflict in
> arch/arm/mach-omap1/board-palmtt.c between commit ddba6c7f7ec6 ("OMAP1:
> pass LCD config with omapfb_set_lcd_config()") from the omap_dss2 tree
> and commit 2e3ee9f45b3c ("ARM: OMAP1: Move most of plat/io.h into local
> iomap.h") from the arm-soc tree.
> 
> I fixed it up (see below) and can carry the fix as necessary.

Hi Stephen,

Thanks for fixing up all the conflicts between arm-soc and omap_dss2.
I think we should make sure they are resolved in one of the trees before
the merge window.

Tomi, what are your plans for the omap_dss2 branch to get merged?
Do you think you should send it to Linus first and we merge it into
arm-soc to resolve the conflicts?
Or do you want to merge it through the arm-soc tree?
Or should we go first and you fix up the conflicts by pulling in the
necessary topic branches from arm-soc into your tree?

	Arnd



From robherring2 at gmail.com  Thu Mar  8 11:24:16 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 08 Mar 2012 10:24:16 -0600
Subject: [GIT PULL] mach/io.h clean-up and removal
Message-ID: <4F58DD30.4060704@gmail.com>

Arnd, Olof,

Please pull the mach/io.h cleanup series for 3.4. This does not include
the PCI i/o mapping changes. In hopes of testing, I'll wait until 3.5
for that. Although, it seems no one has devices with i/o.

I'm sending this to you rather than Russell as it is based on at91 and
omap cleanup branches in arm-soc tree.

Rob

The following changes since commit d50673ed97a7ce609cf62bcd40c57517ada31806:

  Merge remote-tracking branch 'arm-soc/at91/base2+cleanup' into
cleanup-base (2012-03-04 22:00:46 -0600)

are available in the git repository at:

  git://sources.calxeda.com/kernel/linux.git io-cleanup-for-3.4

Rob Herring (21):
      usb: ohci-pxa27x: add explicit include of hardware.h
      ARM: provide runtime hook for ioremap/iounmap
      ARM: imx: convert to common runtime ioremap hook
      ARM: msm: use runtime ioremap hook
      ARM: iop13xx: use runtime ioremap hook
      ARM: ixp4xx: use runtime ioremap hook
      ARM: ebsa110: use runtime ioremap hook
      ARM: remove compile time __arch_ioremap/__arch_iounmap
      ARM: iop13xx: move io.h externs to pci.h
      ARM: msm: clean-up mach/io.h
      [media] davinci: remove includes of mach/io.h
      ARM: davinci: remove unneeded mach/io.h include
      ARM: orion5x: clean-up mach/io.h
      ARM: tegra: clean-up mach/io.h
      ARM: ep93xx: clean-up mach/io.h
      ARM: at91: add explicit include of hardware.h to uncompressor
      ARM: dove: add explicit include of dove.h to addr-map.c
      ARM: clps711x: remove unneeded include of mach/io.h
      ARM: make mach/io.h include optional
      ARM: remove bunch of now unused mach/io.h files
      ARM: kill off __mem_pci

Tony Lindgren (1):
      ARM: OMAP: Remove remaining includes for mach/io.h

 arch/arm/Kconfig                                 |   23 +++++++
 arch/arm/include/asm/io.h                        |   69
++++++++++------------
 arch/arm/mach-at91/include/mach/io.h             |   31 ----------
 arch/arm/mach-at91/include/mach/uncompress.h     |    1 +
 arch/arm/mach-bcmring/include/mach/io.h          |   33 ----------
 arch/arm/mach-clps711x/include/mach/io.h         |   36 -----------
 arch/arm/mach-clps711x/include/mach/uncompress.h |    1 -
 arch/arm/mach-cns3xxx/include/mach/io.h          |   17 -----
 arch/arm/mach-davinci/include/mach/entry-macro.S |    1 -
 arch/arm/mach-davinci/include/mach/io.h          |   24 --------
 arch/arm/mach-dove/addr-map.c                    |    1 +
 arch/arm/mach-dove/include/mach/io.h             |    1 -
 arch/arm/mach-ebsa110/core.c                     |   15 +++++
 arch/arm/mach-ebsa110/include/mach/io.h          |    9 ---
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h  |    9 +++
 arch/arm/mach-ep93xx/include/mach/io.h           |   22 -------
 arch/arm/mach-exynos/include/mach/io.h           |   26 --------
 arch/arm/mach-footbridge/include/mach/io.h       |   13 ----
 arch/arm/mach-gemini/include/mach/io.h           |   18 ------
 arch/arm/mach-h720x/include/mach/io.h            |   22 -------
 arch/arm/mach-highbank/include/mach/io.h         |    7 --
 arch/arm/mach-imx/mm-imx3.c                      |   10 ++--
 arch/arm/mach-integrator/include/mach/io.h       |    1 -
 arch/arm/mach-iop13xx/include/mach/io.h          |   13 ----
 arch/arm/mach-iop13xx/io.c                       |   20 ++++---
 arch/arm/mach-iop13xx/iq81340mc.c                |    1 +
 arch/arm/mach-iop13xx/iq81340sc.c                |    1 +
 arch/arm/mach-iop13xx/pci.h                      |    6 ++
 arch/arm/mach-iop32x/include/mach/io.h           |    1 -
 arch/arm/mach-iop33x/include/mach/io.h           |    1 -
 arch/arm/mach-ixp2000/include/mach/io.h          |    1 -
 arch/arm/mach-ixp23xx/include/mach/io.h          |    1 -
 arch/arm/mach-ixp4xx/avila-setup.c               |    2 +
 arch/arm/mach-ixp4xx/common.c                    |   33 ++++++++++
 arch/arm/mach-ixp4xx/coyote-setup.c              |    2 +
 arch/arm/mach-ixp4xx/dsmg600-setup.c             |    1 +
 arch/arm/mach-ixp4xx/fsg-setup.c                 |    1 +
 arch/arm/mach-ixp4xx/gateway7001-setup.c         |    1 +
 arch/arm/mach-ixp4xx/goramo_mlr.c                |    1 +
 arch/arm/mach-ixp4xx/gtwx5715-setup.c            |    1 +
 arch/arm/mach-ixp4xx/include/mach/io.h           |   24 +-------
 arch/arm/mach-ixp4xx/include/mach/platform.h     |    1 +
 arch/arm/mach-ixp4xx/ixdp425-setup.c             |    4 +
 arch/arm/mach-ixp4xx/nas100d-setup.c             |    1 +
 arch/arm/mach-ixp4xx/nslu2-setup.c               |    1 +
 arch/arm/mach-ixp4xx/omixp-setup.c               |    3 +
 arch/arm/mach-ixp4xx/vulcan-setup.c              |    1 +
 arch/arm/mach-ixp4xx/wg302v2-setup.c             |    1 +
 arch/arm/mach-kirkwood/include/mach/io.h         |    2 -
 arch/arm/mach-ks8695/include/mach/io.h           |   19 ------
 arch/arm/mach-lpc32xx/include/mach/io.h          |   27 ---------
 arch/arm/mach-mmp/include/mach/io.h              |   21 -------
 arch/arm/mach-msm/board-halibut.c                |    6 ++
 arch/arm/mach-msm/board-trout.c                  |    6 ++
 arch/arm/mach-msm/include/mach/io.h              |   36 -----------
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h  |    6 ++
 arch/arm/mach-msm/include/mach/msm_iomap-7x30.h  |    4 +
 arch/arm/mach-msm/include/mach/msm_iomap-8960.h  |    4 +
 arch/arm/mach-msm/include/mach/msm_iomap-8x50.h  |    4 +
 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h  |    4 +
 arch/arm/mach-msm/io.c                           |    8 +--
 arch/arm/mach-mv78xx0/include/mach/io.h          |    2 -
 arch/arm/mach-mxs/include/mach/io.h              |   22 -------
 arch/arm/mach-netx/include/mach/io.h             |   28 ---------
 arch/arm/mach-nomadik/include/mach/io.h          |   22 -------
 arch/arm/mach-omap1/include/mach/entry-macro.S   |    1 -
 arch/arm/mach-omap1/include/mach/io.h            |   46 --------------
 arch/arm/mach-omap1/sleep.S                      |    2 -
 arch/arm/mach-omap1/sram.S                       |    1 -
 arch/arm/mach-omap2/include/mach/io.h            |   49 ---------------
 arch/arm/mach-orion5x/common.h                   |    9 +++
 arch/arm/mach-orion5x/include/mach/io.h          |   33 ----------
 arch/arm/mach-orion5x/pci.c                      |    1 +
 arch/arm/mach-orion5x/tsx09-common.c             |    1 +
 arch/arm/mach-picoxcell/include/mach/io.h        |   22 -------
 arch/arm/mach-pnx4008/include/mach/io.h          |   21 -------
 arch/arm/mach-prima2/include/mach/io.h           |   16 -----
 arch/arm/mach-pxa/include/mach/io.h              |   20 ------
 arch/arm/mach-realview/include/mach/io.h         |   28 ---------
 arch/arm/mach-rpc/include/mach/io.h              |    5 --
 arch/arm/mach-s3c2410/include/mach/io.h          |    5 --
 arch/arm/mach-s3c64xx/include/mach/io.h          |   18 ------
 arch/arm/mach-s5p64x0/include/mach/io.h          |   25 --------
 arch/arm/mach-s5pc100/include/mach/io.h          |   18 ------
 arch/arm/mach-s5pv210/include/mach/io.h          |   26 --------
 arch/arm/mach-sa1100/include/mach/io.h           |   20 ------
 arch/arm/mach-shark/include/mach/io.h            |    2 -
 arch/arm/mach-shmobile/include/mach/io.h         |    9 ---
 arch/arm/mach-spear3xx/include/mach/io.h         |   19 ------
 arch/arm/mach-spear6xx/include/mach/io.h         |   20 ------
 arch/arm/mach-tegra/include/mach/debug-macro.S   |    1 -
 arch/arm/mach-tegra/include/mach/io.h            |   49 ---------------
 arch/arm/mach-tegra/include/mach/iomap.h         |   48 +++++++++++++++
 arch/arm/mach-tegra/io.c                         |    1 +
 arch/arm/mach-u300/include/mach/io.h             |   20 ------
 arch/arm/mach-ux500/include/mach/io.h            |   22 -------
 arch/arm/mach-versatile/include/mach/io.h        |   28 ---------
 arch/arm/mach-vexpress/include/mach/io.h         |   26 --------
 arch/arm/mach-vt8500/include/mach/io.h           |   26 --------
 arch/arm/mach-w90x900/include/mach/io.h          |   30 ---------
 arch/arm/mach-zynq/include/mach/io.h             |   33 ----------
 arch/arm/mm/ioremap.c                            |   17 +++++-
 arch/arm/plat-mxc/include/mach/hardware.h        |    3 +
 arch/arm/plat-mxc/include/mach/io.h              |   39 ------------
 arch/arm/plat-omap/include/plat/sdrc.h           |    1 -
 arch/arm/plat-spear/include/plat/io.h            |   22 -------
 drivers/media/video/davinci/vpbe_osd.c           |    1 -
 drivers/media/video/davinci/vpbe_venc.c          |    1 -
 drivers/usb/host/ohci-pxa27x.c                   |    1 +
 drivers/video/omap2/vrfb.c                       |    1 -
 110 files changed, 275 insertions(+), 1246 deletions(-)
 delete mode 100644 arch/arm/mach-at91/include/mach/io.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/io.h
 delete mode 100644 arch/arm/mach-clps711x/include/mach/io.h
 delete mode 100644 arch/arm/mach-cns3xxx/include/mach/io.h
 delete mode 100644 arch/arm/mach-davinci/include/mach/io.h
 delete mode 100644 arch/arm/mach-ep93xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-exynos/include/mach/io.h
 delete mode 100644 arch/arm/mach-gemini/include/mach/io.h
 delete mode 100644 arch/arm/mach-h720x/include/mach/io.h
 delete mode 100644 arch/arm/mach-highbank/include/mach/io.h
 create mode 100644 arch/arm/mach-iop13xx/pci.h
 delete mode 100644 arch/arm/mach-ks8695/include/mach/io.h
 delete mode 100644 arch/arm/mach-lpc32xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-mmp/include/mach/io.h
 delete mode 100644 arch/arm/mach-msm/include/mach/io.h
 delete mode 100644 arch/arm/mach-mxs/include/mach/io.h
 delete mode 100644 arch/arm/mach-netx/include/mach/io.h
 delete mode 100644 arch/arm/mach-nomadik/include/mach/io.h
 delete mode 100644 arch/arm/mach-omap1/include/mach/io.h
 delete mode 100644 arch/arm/mach-omap2/include/mach/io.h
 delete mode 100644 arch/arm/mach-orion5x/include/mach/io.h
 delete mode 100644 arch/arm/mach-picoxcell/include/mach/io.h
 delete mode 100644 arch/arm/mach-pnx4008/include/mach/io.h
 delete mode 100644 arch/arm/mach-prima2/include/mach/io.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/io.h
 delete mode 100644 arch/arm/mach-realview/include/mach/io.h
 delete mode 100644 arch/arm/mach-s3c64xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-s5p64x0/include/mach/io.h
 delete mode 100644 arch/arm/mach-s5pc100/include/mach/io.h
 delete mode 100644 arch/arm/mach-s5pv210/include/mach/io.h
 delete mode 100644 arch/arm/mach-sa1100/include/mach/io.h
 delete mode 100644 arch/arm/mach-shmobile/include/mach/io.h
 delete mode 100644 arch/arm/mach-spear3xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-spear6xx/include/mach/io.h
 delete mode 100644 arch/arm/mach-u300/include/mach/io.h
 delete mode 100644 arch/arm/mach-ux500/include/mach/io.h
 delete mode 100644 arch/arm/mach-versatile/include/mach/io.h
 delete mode 100644 arch/arm/mach-vexpress/include/mach/io.h
 delete mode 100644 arch/arm/mach-vt8500/include/mach/io.h
 delete mode 100644 arch/arm/mach-w90x900/include/mach/io.h
 delete mode 100644 arch/arm/mach-zynq/include/mach/io.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/io.h
 delete mode 100644 arch/arm/plat-spear/include/plat/io.h


From jason at lakedaemon.net  Thu Mar  8 11:27:29 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 8 Mar 2012 11:27:29 -0500
Subject: [GIT PULL v4] ARM: kirkwood: fdt conversion progress
In-Reply-To: <201203081610.21493.arnd@arndb.de>
References: <20120307221012.GH5050@titan.lakedaemon.net>
 <201203081610.21493.arnd@arndb.de>
Message-ID: <20120308162729.GJ5050@titan.lakedaemon.net>

On Thu, Mar 08, 2012 at 04:10:21PM +0000, Arnd Bergmann wrote:
> On Wednesday 07 March 2012, Jason Cooper wrote:
> > The following changes since commit d65b4e98d7ea3038b767b70fe8be959b2913f16d:
> > 
> >   Linux 3.3-rc3 (2012-02-08 19:21:53 -0800)
> > 
> > are available in the git repository at:
> >   git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt
> > 
> > ---
> > Arnd,
> > 
> > My first two should match up with what you have already, the only
> > outlier is that Jean-Christophe's patch is needed, but I don't think
> > everyone agrees on it yet.
> > 
> 
> Right now, Olof is handling the pull requests. I would suggest that he
> can use your branch to replace the current staging branch but still keep
> it in staging until everyone agrees or you replace it with a better version.

Ok, I'll make sure he's added to future emails.

thx,

Jason.


From jason at lakedaemon.net  Thu Mar  8 11:25:30 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 8 Mar 2012 11:25:30 -0500
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <201203072113.04369.arnd@arndb.de>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203071831.31738.arnd@arndb.de>
 <20120307192723.GE5050@titan.lakedaemon.net>
 <201203072113.04369.arnd@arndb.de>
Message-ID: <20120308162530.GI5050@titan.lakedaemon.net>

On Wed, Mar 07, 2012 at 09:13:04PM +0000, Arnd Bergmann wrote:
> Finally, something could be wrong with the interrupt controller.
> AFAICT, you register it through the device tree now, but it's also
> getting initialized through kirkwood_init_irq, so the numbers
> would all be wrong.

Yes, I'm working through this now.  mv_cesa silently fails to come up
if it can't find the interrupt controller via fdt.  So, it needs to get
done.

Right now, I'm looking at how mach-versatile does it (vic_init()) since
it's also an ARM926ej-s...

thx,

Jason.


From aneesh at ti.com  Thu Mar  8 11:33:53 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu,  8 Mar 2012 22:03:53 +0530
Subject: [PATCH 0/4] dt: device tree support for TI EMIF driver
Message-ID: <1331224437-4808-1-git-send-email-aneesh@ti.com>

This series adds device tree support for TI EMIF SDRAM controller
driver. For this, a binding has been added for representing AC timing
parameters and other details of LPDDR2 memories.

This series depends my series for adding EMIF driver [1]

[1] http://marc.info/?l=linux-omap&m=133122243430942&w=2

Aneesh V (4):
  dt: device tree bindings for LPDDR2 memories
  dt: emif: device tree bindings for TI's EMIF sdram controller
  arm: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
  misc: emif: add device tree support to emif driver

 .../devicetree/bindings/lpddr2/lpddr2-timings.txt  |   52 ++++
 .../devicetree/bindings/lpddr2/lpddr2.txt          |  102 +++++++
 .../bindings/memory-controllers/ti/emif.txt        |   55 ++++
 arch/arm/boot/dts/elpida_ecb240abacn.dtsi          |   67 +++++
 arch/arm/boot/dts/omap4-panda.dts                  |   13 +
 arch/arm/boot/dts/omap4-sdp.dts                    |   13 +
 arch/arm/boot/dts/omap4.dtsi                       |   18 ++
 drivers/misc/emif.c                                |  289 +++++++++++++++++++-
 8 files changed, 608 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
 create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
 create mode 100644 arch/arm/boot/dts/elpida_ecb240abacn.dtsi



From aneesh at ti.com  Thu Mar  8 11:33:54 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu,  8 Mar 2012 22:03:54 +0530
Subject: [PATCH 1/4] dt: device tree bindings for LPDDR2 memories
In-Reply-To: <1331224437-4808-1-git-send-email-aneesh@ti.com>
References: <1331224437-4808-1-git-send-email-aneesh@ti.com>
Message-ID: <1331224437-4808-2-git-send-email-aneesh@ti.com>

device tree bindings for LPDDR2 SDRAM memories compliant
to JESD209-2 standard.

The 'lpddr2' binding in-turn uses another binding 'lpddr2-timings'
for specifying the AC timing parameters of the memory device at
different speed-bins.

Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
Changes since RFC v4:
- Removed two DDR3 only timing parameters that were
  inadvertently added in the binding
---
 .../devicetree/bindings/lpddr2/lpddr2-timings.txt  |   52 ++++++++++
 .../devicetree/bindings/lpddr2/lpddr2.txt          |  102 ++++++++++++++++++++
 2 files changed, 154 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
 create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2.txt

diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
new file mode 100644
index 0000000..a48f698
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
@@ -0,0 +1,52 @@
+* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
+
+Required properties:
+- compatible : Should be "jedec,lpddr2-timings"
+- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
+- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
+
+Optional properties:
+
+The following properties represent AC timing parameters from the memory
+data-sheet of the device for a given speed-bin. All these properties are
+of type <u32> and the default unit is ps (pico seconds). Parameters with
+a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
+- tRCD
+- tWR
+- tRAS-min
+- tRRD
+- tWTR
+- tXP
+- tRTP
+- tDQSCK-max
+- tFAW
+- tZQCS
+- tZQinit
+- tRPab
+- tZQCL
+- tCKESR
+- tRAS-max-ns
+- tDQSCK-max-derated
+
+Example:
+
+timings_elpida_ECB240ABACN_400mhz: lpddr2-timings at 0 {
+	compatible 	= "jedec,lpddr2-timings";
+	min-freq	= <10000000>;
+	max-freq	= <400000000>;
+	tRPab		= <21000>;
+	tRCD		= <18000>;
+	tWR		= <15000>;
+	tRAS-min	= <42000>;
+	tRRD		= <10000>;
+	tWTR		= <7500>;
+	tXP		= <7500>;
+	tRTP		= <7500>;
+	tCKESR		= <15000>;
+	tDQSCK-max 	= <5500>;
+	tFAW		= <50000>;
+	tZQCS		= <90000>;
+	tZQCL		= <360000>;
+	tZQinit		= <1000000>;
+	tRAS-max-ns	= <70000>;
+};
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
new file mode 100644
index 0000000..a2ab203
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
@@ -0,0 +1,102 @@
+* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
+
+Required properties:
+- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
+  "jedec,lpddr2-s4"
+
+  "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
+
+  "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
+
+  "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
+
+- density  : <u32> representing density in Mb (Mega bits)
+
+- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
+
+Optional properties:
+
+The following optional properties represent the minimum value of some AC
+timing parameters of the DDR device in terms of number of clock cycles.
+These values shall be obtained from the device data-sheet.
+- tRRD-min-tck
+- tWTR-min-tck
+- tXP-min-tck
+- tRTP-min-tck
+- tCKE-min-tck
+- tRPab-min-tck
+- tRCD-min-tck
+- tWR-min-tck
+- tRASmin-min-tck
+- tCKESR-min-tck
+- tFAW-min-tck
+
+Child nodes:
+- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
+  "lpddr2-timings" provides AC timing parameters of the device for
+  a given speed-bin. The user may provide the timings for as many
+  speed-bins as is required. Please see Documentation/devicetree/
+  bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
+
+Example:
+
+elpida_ECB240ABACN : lpddr2 {
+	compatible 	= "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+	density		= <2048>;
+	io-width	= <32>;
+
+	tRPab-min-tck	= <3>;
+	tRCD-min-tck	= <3>;
+	tWR-min-tck	= <3>;
+	tRASmin-min-tck	= <3>;
+	tRRD-min-tck	= <2>;
+	tWTR-min-tck	= <2>;
+	tXP-min-tck	= <2>;
+	tRTP-min-tck	= <2>;
+	tCKE-min-tck	= <3>;
+	tCKESR-min-tck	= <3>;
+	tFAW-min-tck	= <8>;
+
+	timings_elpida_ECB240ABACN_400mhz: lpddr2-timings at 0 {
+		compatible 	= "jedec,lpddr2-timings";
+		min-freq	= <10000000>;
+		max-freq	= <400000000>;
+		tRPab		= <21000>;
+		tRCD		= <18000>;
+		tWR		= <15000>;
+		tRAS-min	= <42000>;
+		tRRD		= <10000>;
+		tWTR		= <7500>;
+		tXP		= <7500>;
+		tRTP		= <7500>;
+		tCKESR		= <15000>;
+		tDQSCK-max 	= <5500>;
+		tFAW		= <50000>;
+		tZQCS		= <90000>;
+		tZQCL		= <360000>;
+		tZQinit		= <1000000>;
+		tRAS-max-ns	= <70000>;
+	};
+
+	timings_elpida_ECB240ABACN_200mhz: lpddr2-timings at 1 {
+		compatible 	= "jedec,lpddr2-timings";
+		min-freq	= <10000000>;
+		max-freq	= <200000000>;
+		tRPab		= <21000>;
+		tRCD		= <18000>;
+		tWR		= <15000>;
+		tRAS-min	= <42000>;
+		tRRD		= <10000>;
+		tWTR		= <10000>;
+		tXP		= <7500>;
+		tRTP		= <7500>;
+		tCKESR		= <15000>;
+		tDQSCK-max 	= <5500>;
+		tFAW		= <50000>;
+		tZQCS		= <90000>;
+		tZQCL		= <360000>;
+		tZQinit		= <1000000>;
+		tRAS-max-ns	= <70000>;
+	};
+
+}
-- 
1.7.1



From aneesh at ti.com  Thu Mar  8 11:33:56 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu,  8 Mar 2012 22:03:56 +0530
Subject: [PATCH 3/4] arm: dts: EMIF and LPDDR2 device tree data for OMAP4
 boards
In-Reply-To: <1331224437-4808-1-git-send-email-aneesh@ti.com>
References: <1331224437-4808-1-git-send-email-aneesh@ti.com>
Message-ID: <1331224437-4808-4-git-send-email-aneesh@ti.com>

Device tree data for the EMIF sdram controllers in OMAP4
and LPDDR2 memory devices attached to OMAP4 boards.

Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
Changes since RFC v4:
- Removed DDR3 only parameters from
  elpida_ecb240abacn.dtsi
---
 arch/arm/boot/dts/elpida_ecb240abacn.dtsi |   67 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap4-panda.dts         |   13 ++++++
 arch/arm/boot/dts/omap4-sdp.dts           |   13 ++++++
 arch/arm/boot/dts/omap4.dtsi              |   18 ++++++++
 4 files changed, 111 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/elpida_ecb240abacn.dtsi

diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
new file mode 100644
index 0000000..34b9f72
--- /dev/null
+++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Common devices used in different OMAP boards
+ */
+
+/ {
+	elpida_ECB240ABACN: lpddr2 {
+		compatible 	= "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+		density		= <2048>;
+		io-width	= <32>;
+
+		tRPab-min-tck	= <3>;
+		tRCD-min-tck	= <3>;
+		tWR-min-tck	= <3>;
+		tRASmin-min-tck	= <3>;
+		tRRD-min-tck	= <2>;
+		tWTR-min-tck	= <2>;
+		tXP-min-tck	= <2>;
+		tRTP-min-tck	= <2>;
+		tCKE-min-tck	= <3>;
+		tCKESR-min-tck	= <3>;
+		tFAW-min-tck	= <8>;
+
+		timings_elpida_ECB240ABACN_400mhz: lpddr2-timings at 0 {
+			compatible	= "jedec,lpddr2-timings";
+			min-freq	= <10000000>;
+			max-freq	= <400000000>;
+			tRPab		= <21000>;
+			tRCD		= <18000>;
+			tWR		= <15000>;
+			tRAS-min	= <42000>;
+			tRRD		= <10000>;
+			tWTR		= <7500>;
+			tXP		= <7500>;
+			tRTP		= <7500>;
+			tCKESR		= <15000>;
+			tDQSCK-max 	= <5500>;
+			tFAW		= <50000>;
+			tZQCS		= <90000>;
+			tZQCL		= <360000>;
+			tZQinit		= <1000000>;
+			tRAS-max-ns	= <70000>;
+			tDQSCK-max-derated = <6000>;
+		};
+
+		timings_elpida_ECB240ABACN_200mhz: lpddr2-timings at 1 {
+			compatible	= "jedec,lpddr2-timings";
+			min-freq	= <10000000>;
+			max-freq	= <200000000>;
+			tRPab		= <21000>;
+			tRCD		= <18000>;
+			tWR		= <15000>;
+			tRAS-min	= <42000>;
+			tRRD		= <10000>;
+			tWTR		= <10000>;
+			tXP		= <7500>;
+			tRTP		= <7500>;
+			tCKESR		= <15000>;
+			tDQSCK-max 	= <5500>;
+			tFAW		= <50000>;
+			tZQCS		= <90000>;
+			tZQCL		= <360000>;
+			tZQinit		= <1000000>;
+			tRAS-max-ns	= <70000>;
+			tDQSCK-max-derated = <6000>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9755ad5..f548523 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 /include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 PandaBoard";
@@ -17,4 +18,16 @@
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
+
+	ocp {
+		emif1: emif at 0x4c000000 {
+			cs1-used;
+			device-handle = <&elpida_ECB240ABACN>;
+		};
+
+		emif2: emif at 0x4d000000 {
+			cs1-used;
+			device-handle = <&elpida_ECB240ABACN>;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 63c6b2b..6dc08bc 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 /include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 SDP board";
@@ -17,4 +18,16 @@
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
+
+	ocp {
+		emif1: emif at 0x4c000000 {
+			cs1-used;
+			device-handle = <&elpida_ECB240ABACN>;
+		};
+
+		emif2: emif at 0x4d000000 {
+			cs1-used;
+			device-handle = <&elpida_ECB240ABACN>;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 70a44f6..fe3664a 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -127,5 +127,23 @@
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
+
+		emif1: emif at 0x4c000000 {
+			compatible	= "ti,emif-4d";
+			ti,hwmods	= "emif1";
+			phy-type	= <1>;
+			hw-caps-read-idle-ctrl;
+			hw-caps-ll-interface;
+			hw-caps-temp-alert;
+		};
+
+		emif2: emif at 0x4d000000 {
+			compatible	= "ti,emif-4d";
+			ti,hwmods	= "emif2";
+			phy-type	= <1>;
+			hw-caps-read-idle-ctrl;
+			hw-caps-ll-interface;
+			hw-caps-temp-alert;
+		};
 	};
 };
-- 
1.7.1



From aneesh at ti.com  Thu Mar  8 11:33:57 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu,  8 Mar 2012 22:03:57 +0530
Subject: [PATCH 4/4] misc: emif: add device tree support to emif driver
In-Reply-To: <1331224437-4808-1-git-send-email-aneesh@ti.com>
References: <1331224437-4808-1-git-send-email-aneesh@ti.com>
Message-ID: <1331224437-4808-5-git-send-email-aneesh@ti.com>

Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
Changes since RFC v4:
- Rebased to the latest version of EMIF series
- Replace kzalloc()/kfree() with devm_* variants
---
 drivers/misc/emif.c |  289 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 288 insertions(+), 1 deletions(-)

diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index 79fb161..0aaa61e 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/module.h>
@@ -49,6 +50,7 @@
  *				frequency in effect at the moment)
  * @plat_data:			Pointer to saved platform data.
  * @debugfs_root:		dentry to the root folder for EMIF in debugfs
+ * @np_ddr:			Pointer to ddr device tree node
  */
 struct emif_data {
 	u8				duplicate;
@@ -63,6 +65,9 @@ struct emif_data {
 	struct emif_regs		*curr_regs;
 	struct emif_platform_data	*plat_data;
 	struct dentry			*debugfs_root;
+#if defined(CONFIG_OF)
+	struct device_node		*np_ddr;
+#endif
 };
 
 static struct emif_data *emif1;
@@ -1147,6 +1152,270 @@ static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
 	return valid;
 }
 
+#if defined(CONFIG_OF)
+static void __init of_get_custom_configs(struct device_node *np_emif,
+		struct emif_data *emif)
+{
+	struct emif_custom_configs	*cust_cfgs = NULL;
+	int				len;
+	const int			*lpmode, *poll_intvl;
+
+	lpmode = of_get_property(np_emif, "low-power-mode", &len);
+	poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
+
+	if (lpmode || poll_intvl)
+		cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
+			GFP_KERNEL);
+
+	if (!cust_cfgs)
+		return;
+
+	if (lpmode) {
+		cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
+		cust_cfgs->lpmode = *lpmode;
+		of_property_read_u32(np_emif,
+				"low-power-mode-timeout-performance",
+				&cust_cfgs->lpmode_timeout_performance);
+		of_property_read_u32(np_emif,
+				"low-power-mode-timeout-power",
+				&cust_cfgs->lpmode_timeout_power);
+		of_property_read_u32(np_emif,
+				"low-power-mode-freq-threshold",
+				&cust_cfgs->lpmode_freq_threshold);
+	}
+
+	if (poll_intvl) {
+		cust_cfgs->mask |=
+				EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
+		cust_cfgs->temp_alert_poll_interval_ms = *poll_intvl;
+	}
+
+	if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
+		devm_kfree(emif->dev, cust_cfgs);
+		return;
+	}
+
+	emif->plat_data->custom_configs = cust_cfgs;
+}
+
+static void __init of_get_min_tck(struct device_node *np,
+		struct emif_data *emif)
+{
+	int			ret = 0;
+	struct lpddr2_min_tck	*min;
+
+	min = devm_kzalloc(emif->dev, sizeof(*min), GFP_KERNEL);
+	if (!min)
+		goto default_min_tck;
+
+	ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab);
+	ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD);
+	ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR);
+	ret |= of_property_read_u32(np, "tRASmin-min-tck", &min->tRASmin);
+	ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD);
+	ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR);
+	ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP);
+	ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP);
+	ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE);
+	ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR);
+	ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW);
+
+	if (ret) {
+		devm_kfree(emif->dev, min);
+		goto default_min_tck;
+	}
+
+	emif->plat_data->min_tck = min;
+	return;
+
+default_min_tck:
+	dev_warn(emif->dev, "%s: using default min-tck values\n", __func__);
+	emif->plat_data->min_tck = &lpddr2_min_tck;
+}
+
+static int __init of_do_get_timings(struct device_node *np,
+		struct lpddr2_timings *tim)
+{
+	int ret;
+
+	ret = of_property_read_u32(np, "max-freq", &tim->max_freq);
+	ret |= of_property_read_u32(np, "min-freq", &tim->min_freq);
+	ret |= of_property_read_u32(np, "tRPab", &tim->tRPab);
+	ret |= of_property_read_u32(np, "tRCD", &tim->tRCD);
+	ret |= of_property_read_u32(np, "tWR", &tim->tWR);
+	ret |= of_property_read_u32(np, "tRAS-min", &tim->tRAS_min);
+	ret |= of_property_read_u32(np, "tRRD", &tim->tRRD);
+	ret |= of_property_read_u32(np, "tWTR", &tim->tWTR);
+	ret |= of_property_read_u32(np, "tXP", &tim->tXP);
+	ret |= of_property_read_u32(np, "tRTP", &tim->tRTP);
+	ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR);
+	ret |= of_property_read_u32(np, "tDQSCK-max", &tim->tDQSCK_max);
+	ret |= of_property_read_u32(np, "tFAW", &tim->tFAW);
+	ret |= of_property_read_u32(np, "tZQCS", &tim->tZQCS);
+	ret |= of_property_read_u32(np, "tZQCL", &tim->tZQCL);
+	ret |= of_property_read_u32(np, "tZQinit", &tim->tZQinit);
+	ret |= of_property_read_u32(np, "tRAS-max-ns", &tim->tRAS_max_ns);
+	ret |= of_property_read_u32(np, "tDQSCK-max-derated",
+		&tim->tDQSCK_max_derated);
+
+	return ret;
+}
+
+static void __init of_get_ddr_timings(struct device_node *np_ddr,
+		struct emif_data *emif)
+{
+	struct lpddr2_timings	*timings = NULL;
+	u32			arr_sz = 0, i = 0;
+	struct device_node	*np_tim;
+	char			*tim_compat;
+
+	switch (emif->plat_data->device_info->type) {
+	case DDR_TYPE_LPDDR2_S2:
+	case DDR_TYPE_LPDDR2_S4:
+		tim_compat = "jedec,lpddr2-timings";
+		break;
+	default:
+		dev_warn(emif->dev, "%s: un-supported memory type\n", __func__);
+	}
+
+	for_each_child_of_node(np_ddr, np_tim)
+		if (of_device_is_compatible(np_tim, tim_compat))
+			arr_sz++;
+
+	if (arr_sz)
+		timings = devm_kzalloc(emif->dev, sizeof(*timings) * arr_sz,
+			GFP_KERNEL);
+
+	if (!timings)
+		goto default_timings;
+
+	for_each_child_of_node(np_ddr, np_tim) {
+		if (of_device_is_compatible(np_tim, tim_compat)) {
+			if (of_do_get_timings(np_tim, &timings[i])) {
+				devm_kfree(emif->dev, timings);
+				goto default_timings;
+			}
+			i++;
+		}
+	}
+
+	emif->plat_data->timings = timings;
+	emif->plat_data->timings_arr_size = arr_sz;
+
+	return;
+
+default_timings:
+	get_default_timings(emif);
+
+	return;
+}
+
+static void __init of_get_ddr_info(struct device_node *np_emif,
+		struct device_node *np_ddr,
+		struct ddr_device_info *dev_info)
+{
+	u32 density = 0, io_width = 0;
+	int len;
+
+	if (of_find_property(np_emif, "cs1-used", &len))
+		dev_info->cs1_used = true;
+
+	if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
+		dev_info->cal_resistors_per_cs = true;
+
+	if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s4"))
+		dev_info->type = DDR_TYPE_LPDDR2_S4;
+	else if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s2"))
+		dev_info->type = DDR_TYPE_LPDDR2_S2;
+
+	of_property_read_u32(np_ddr, "density", &density);
+	of_property_read_u32(np_ddr, "io-width", &io_width);
+
+	/* Convert from density in Mb to the density encoding in jedc_ddr.h */
+	if (density & (density - 1))
+		dev_info->density = 0;
+	else
+		dev_info->density = __fls(density) - 5;
+
+	/* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
+	if (io_width & (io_width - 1))
+		dev_info->io_width = 0;
+	else
+		dev_info->io_width = __fls(io_width) - 1;
+}
+
+static struct emif_data * __init of_get_device_details(
+		struct device_node *np_emif, struct device *dev)
+{
+	struct emif_data		*emif = NULL;
+	struct ddr_device_info		*dev_info = NULL;
+	struct emif_platform_data	*pd = NULL;
+	struct device_node		*np_ddr;
+	int				len;
+
+	np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
+	if (!np_ddr)
+		goto error;
+	emif	= devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
+	pd	= devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+	dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
+
+	if (!emif || !pd || !dev_info) {
+		dev_err(dev, "%s: of_get_device_details() failure!!\n",
+			__func__);
+		goto error;
+	}
+
+	emif->plat_data		= pd;
+	pd->device_info		= dev_info;
+	emif->dev		= dev;
+	emif->np_ddr		= np_ddr;
+	emif->temperature_level	= SDRAM_TEMP_NOMINAL;
+
+	if (of_device_is_compatible(np_emif, "ti,emif-4d"))
+		emif->plat_data->ip_rev = EMIF_4D;
+	else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
+		emif->plat_data->ip_rev = EMIF_4D5;
+
+	of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
+
+	if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
+		pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
+
+	of_get_ddr_info(np_emif, np_ddr, dev_info);
+	if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
+			pd->device_info->io_width, pd->phy_type, pd->ip_rev,
+			emif->dev)) {
+		dev_err(dev, "%s: invalid device data!!\n", __func__);
+		goto error;
+	}
+	/*
+	 * For EMIF instances other than EMIF1 see if the devices connected
+	 * are exactly same as on EMIF1(which is typically the case). If so,
+	 * mark it as a duplicate of EMIF1. This will save some memory and
+	 * computation.
+	 */
+	if (emif1 && emif1->np_ddr == np_ddr) {
+		emif->duplicate = true;
+		goto out;
+	} else if (emif1) {
+		dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
+			__func__);
+	}
+
+
+	of_get_custom_configs(np_emif, emif);
+	of_get_ddr_timings(np_ddr, emif);
+	of_get_min_tck(np_ddr, emif);
+	goto out;
+
+error:
+	return NULL;
+out:
+	return emif;
+}
+#endif
+
 static struct emif_data * __init get_device_details(
 		struct platform_device *pdev)
 {
@@ -1266,7 +1535,13 @@ static int __init emif_probe(struct platform_device *pdev)
 	struct resource		*res;
 	int			irq;
 
-	emif = get_device_details(pdev);
+#if defined(CONFIG_OF)
+	if (pdev->dev.of_node)
+		emif = of_get_device_details(pdev->dev.of_node, &pdev->dev);
+	else
+#endif
+		emif = get_device_details(pdev);
+
 	if (!emif) {
 		pr_err("%s: error getting device data\n", __func__);
 		goto error;
@@ -1643,11 +1918,23 @@ static void __attribute__((unused)) freq_post_notify_handling(void)
 	spin_unlock_irqrestore(&emif_lock, irq_state);
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id emif_of_match[] = {
+		{ .compatible = "ti,emif-4d" },
+		{ .compatible = "ti,emif-4d5" },
+		{},
+};
+MODULE_DEVICE_TABLE(of, emif_of_match);
+#endif
+
 static struct platform_driver emif_driver = {
 	.remove		= __exit_p(emif_remove),
 	.shutdown	= emif_shutdown,
 	.driver = {
 		.name = "emif",
+#if defined(CONFIG_OF)
+		.of_match_table = of_match_ptr(emif_of_match),
+#endif
 	},
 };
 
-- 
1.7.1



From aneesh at ti.com  Thu Mar  8 11:33:55 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu,  8 Mar 2012 22:03:55 +0530
Subject: [PATCH 2/4] dt: emif: device tree bindings for TI's EMIF sdram
 controller
In-Reply-To: <1331224437-4808-1-git-send-email-aneesh@ti.com>
References: <1331224437-4808-1-git-send-email-aneesh@ti.com>
Message-ID: <1331224437-4808-3-git-send-email-aneesh@ti.com>

EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
of the EMIF IP and memory parts attached to it.

Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
Changes sice RFC v4:
- None
---
 .../bindings/memory-controllers/ti/emif.txt        |   55 ++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/emif.txt

diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
new file mode 100644
index 0000000..938f8e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -0,0 +1,55 @@
+* EMIF family of TI SDRAM controllers
+
+EMIF - External Memory Interface - is an SDRAM controller used in
+TI SoCs. EMIF supports, based on the IP revision, one or more of
+DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
+of the EMIF IP and memory parts attached to it.
+
+Required properties:
+- compatible	: Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
+  is the IP revision of the specific EMIF instance.
+
+- phy-type	: <u32> indicating the DDR phy type. Following are the
+  allowed values
+  <1>	: Attila PHY
+  <2>	: Intelli PHY
+
+- device-handle	: phandle to a "lpddr2" node representing the memory part
+
+- ti,hwmods	: For TI hwmods processing and omap device creation
+  the value shall be "emif<n>" where <n> is the number of the EMIF
+  instance with base 1.
+
+Optional properties:
+- cs1-used		: Have this property if CS1 of this EMIF
+  instance has a memory part attached to it. If there is a memory
+  part attached to CS1, it should be the same type as the one on CS0,
+  so there is no need to give the details of this memory part.
+
+- cal-resistor-per-cs	: Have this property if the board has one
+  calibration resistor per chip-select.
+
+- hw-caps-read-idle-ctrl: Have this property if the controller
+  supports read idle window programming
+
+- hw-caps-dll-calib-ctrl: Have this property if the controller
+  supports dll calibration control
+
+- hw-caps-ll-interface	: Have this property if the controller
+  has a low latency interface and corresponding interrupt events
+
+- hw-caps-temp-alert	: Have this property if the controller
+  has capability for generating SDRAM temperature alerts
+
+Example:
+
+emif1: emif at 0x4c000000 {
+	compatible	= "ti,emif-4d";
+	ti,hwmods	= "emif2";
+	phy-type	= <1>;
+	device-handle	= <&elpida_ECB240ABACN>;
+	cs1-used;
+	hw-caps-read-idle-ctrl;
+	hw-caps-ll-interface;
+	hw-caps-temp-alert;
+};
-- 
1.7.1



From hvaibhav at ti.com  Thu Mar  8 11:39:57 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Thu, 8 Mar 2012 16:39:57 +0000
Subject: [PATCH-V2 2/2] arm:omap:am33xx: Add power domain data
In-Reply-To: <alpine.DEB.2.00.1203020337330.15424@utopia.booyaka.com>
References: <1324803628-16790-1-git-send-email-hvaibhav@ti.com>
 <1324803628-16790-3-git-send-email-hvaibhav@ti.com>
 <alpine.DEB.2.00.1202291839130.12752@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A8317E515D@DBDE01.ent.ti.com>
 <alpine.DEB.2.00.1203012330490.22980@utopia.booyaka.com>
 <79CD15C6BA57404B839C016229A409A8317E6763@DBDE01.ent.ti.com>
 <alpine.DEB.2.00.1203020337330.15424@utopia.booyaka.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83180D786@DBDE01.ent.ti.com>

On Fri, Mar 02, 2012 at 16:16:47, Paul Walmsley wrote:
> Hi
> 
> On Fri, 2 Mar 2012, Hiremath, Vaibhav wrote:
> 
> > Paul,
> > Thanks for your review comments, can we also align on the approach, 
> > Whether to merge am33xx powerdomain with omap4 (same direction we are now)
> > OR
> > Have separate implementation (my original approach).
> 
> Could you please take a look at the "am335x_prcm_devel_3.4" branch on 
> git://git.pwsan.com/linux-2.6 and let me know what you think?
> 
> It is still rough, incomplete, and compile-tested only; and the patch 
> commit messages have to be updated and revised; but I think it is a 
> slightly better approach.
> 

Paul,

Sorry for delayed response, was bit stuck with some baseport thing.


I have reviewed the changes from your above branch. And as I mentioned 
before, it looks closer to my earlier approach + some good and important 
changes/cleanups.

> A significant change is that the prminst code changes have been removed.  
> That is only needed when PRM registers are spread across multiple PRCM IP 
> blocks.  

Make sense actually...I don't know, why didn't thought about this before...

> This does not appear to be the case with AM33xx?  So the 
> implementation has been modified to create a prm33xx.c file instead.  
> This avoids an extra, unnecessary layer of indirection for PRM accesses.
> 
> This, along with the other differences between OMAP4 and this chip, means 
> that a separate powerdomain33xx.c file had to be created.
> 
> The powerdomains33xx_data.c file is still missing the bitmask position 
> data, but the structure members are there.
> 

Yeah, I understand, I think without this it won't be usefule. I will also get this done in next (aligned) changes.

> Feel free to combine, rework, or merge this series with what you are 
> working on if you feel that it is a good approach.  Otherwise, let's 
> discuss.
> 

Thanks, Thanks a lot for your time/support/review, as always its helpful.


Thanks,
Vaibhav

> 
> - Paul
> 



From olof at lixom.net  Thu Mar  8 11:56:14 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 8 Mar 2012 08:56:14 -0800
Subject: [GIT PULL] Samsung Cleanup S3C24XX for v3.4
In-Reply-To: <4F589313.1050706@samsung.com>
References: <4F589313.1050706@samsung.com>
Message-ID: <CAOesGMhbmnWSrfEQC5tVrskhjQPMSj1aki1CQ-UM_=mv0-re+A@mail.gmail.com>

On Thu, Mar 8, 2012 at 3:08 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Hi Arnd, Olof,
>
> Please pull cleanup s3c24xx from following:
> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/cleanup-s3c24xx
>
> As I said before, this is including merge of mach-s3c24.. directories into
> just one mach-s3c24xx directory.
>
> If any problems, please kindly let me know.

Thanks, pulled. Nice first step on making all of this common!


-Olof


From olof at lixom.net  Thu Mar  8 11:59:33 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 8 Mar 2012 08:59:33 -0800
Subject: [PATCH] ARM: S3C2440: Fixed build error for s3c244x
In-Reply-To: <1331200116-2424-1-git-send-email-kgene.kim@samsung.com>
References: <1331200116-2424-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <CAOesGMhkZLGRYi3QTko0gcbj3MJ4vZE6mddEFLFsMhdx9fkx9Q@mail.gmail.com>

On Thu, Mar 8, 2012 at 1:48 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Fixed following:
> arch/arm/mach-s3c2440/s3c244x.c: In function 's3c244x_restart':
> arch/arm/mach-s3c2440/s3c244x.c:209: error: expected declaration or statement at end of input
> make[1]: *** [arch/arm/mach-s3c24xx/s3c244x.o] Error 1
> make: *** [arch/arm/mach-s3c24xx] Error 2
>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>

Thanks, applied to fixes and I'll send out a pull request for the branch today.


-Olof


From shawn.guo at linaro.org  Thu Mar  8 11:59:39 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:39 +0800
Subject: [PATCH v3 00/11] ASoC: add imx-sgtl5000 machine driver working with
 fsl_ssi
Message-ID: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>

I believe I have addressed all the outstanding comments and requests
reviewers put on previous versions.  So, hopefully this will be the
last iteration of the series.

The current sound/for-next branch seems broken for me, and I have not
tracking the problem down.  But the series works good on SHA below.

  3030763 (Merge tag 'asoc-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into topic/asoc)

Timur,

I did not pick up you Ack-by tag, because there are some changes since
v2 you will need to take another look and have the testing, I guess.

Regards,
Shawn

Shawn Guo (11):
      ASoC: core: missing set_fmt should not be complaint
      ASoC: fsl: separate SSI and DMA Kconfig options
      ASoC: imx: merge sound/soc/imx into sound/soc/fsl
      ASoC: fsl: rename imx-pcm Kconfig options and filename
      ASoC: fsl: create fsl_utils to accommodate the common functions
      ASoC: fsl: remove helper fsl_asoc_get_codec_dev_name
      ASoC: fsl: check property 'compatible' for the machine name
      ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
      ASoC: fsl: remove the fatal error checking on codec-handle
      ASoC: fsl: let fsl_ssi work with imx pcm and machine drivers
      ASoC: fsl: add imx-sgtl5000 machine driver

 .../bindings/sound/imx-audio-sgtl5000.txt          |   24 +++
 arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig   |    1 +
 arch/powerpc/configs/mpc85xx_defconfig             |    1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig         |    1 +
 sound/soc/Kconfig                                  |    1 -
 sound/soc/Makefile                                 |    1 -
 sound/soc/fsl/Kconfig                              |  124 ++++++++++++-
 sound/soc/fsl/Makefile                             |   29 +++-
 sound/soc/{imx => fsl}/eukrea-tlv320.c             |    2 +-
 sound/soc/fsl/fsl_ssi.c                            |  146 ++++++++++++----
 sound/soc/fsl/fsl_utils.c                          |   91 ++++++++++
 sound/soc/fsl/fsl_utils.h                          |   26 +++
 sound/soc/{imx => fsl}/imx-audmux.c                |    0
 sound/soc/{imx => fsl}/imx-audmux.h                |    0
 .../{imx/imx-pcm-dma-mx2.c => fsl/imx-pcm-dma.c}   |    0
 sound/soc/{imx => fsl}/imx-pcm-fiq.c               |    0
 sound/soc/{imx => fsl}/imx-pcm.c                   |    0
 sound/soc/{imx => fsl}/imx-pcm.h                   |    0
 sound/soc/fsl/imx-sgtl5000.c                       |  177 ++++++++++++++++++
 sound/soc/{imx => fsl}/imx-ssi.c                   |    2 +-
 sound/soc/{imx => fsl}/imx-ssi.h                   |    0
 sound/soc/fsl/mpc8610_hpcd.c                       |  168 ++----------------
 sound/soc/{imx => fsl}/mx27vis-aic32x4.c           |    0
 sound/soc/fsl/p1022_ds.c                           |  190 ++------------------
 sound/soc/{imx => fsl}/phycore-ac97.c              |    0
 sound/soc/{imx => fsl}/wm1133-ev1.c                |    0
 sound/soc/imx/Kconfig                              |   79 --------
 sound/soc/imx/Makefile                             |   22 ---
 sound/soc/soc-core.c                               |   11 +-
 29 files changed, 616 insertions(+), 480 deletions(-)


From shawn.guo at linaro.org  Thu Mar  8 11:59:40 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:40 +0800
Subject: [PATCH v3 01/11] ASoC: core: missing set_fmt should not be complaint
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331225990-27308-2-git-send-email-shawn.guo@linaro.org>

Not having a DAI link set_fmt operation is perfectly normal and
should not be complaint.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/soc-core.c |   11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index 7978f6c..98b2635 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -1531,14 +1531,14 @@ static void snd_soc_instantiate_card(struct snd_soc_card *card)
 		if (dai_link->dai_fmt) {
 			ret = snd_soc_dai_set_fmt(card->rtd[i].codec_dai,
 						  dai_link->dai_fmt);
-			if (ret != 0)
+			if (ret != 0 && ret != -ENOTSUPP)
 				dev_warn(card->rtd[i].codec_dai->dev,
 					 "Failed to set DAI format: %d\n",
 					 ret);
 
 			ret = snd_soc_dai_set_fmt(card->rtd[i].cpu_dai,
 						  dai_link->dai_fmt);
-			if (ret != 0)
+			if (ret != 0 && ret != -ENOTSUPP)
 				dev_warn(card->rtd[i].cpu_dai->dev,
 					 "Failed to set DAI format: %d\n",
 					 ret);
@@ -2971,10 +2971,11 @@ EXPORT_SYMBOL_GPL(snd_soc_codec_set_pll);
  */
 int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 {
-	if (dai->driver && dai->driver->ops->set_fmt)
-		return dai->driver->ops->set_fmt(dai, fmt);
-	else
+	if (dai->driver == NULL)
 		return -EINVAL;
+	if (dai->driver->ops->set_fmt == NULL)
+		return -ENOTSUPP;
+	return dai->driver->ops->set_fmt(dai, fmt);
 }
 EXPORT_SYMBOL_GPL(snd_soc_dai_set_fmt);
 
-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Mar  8 11:59:41 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:41 +0800
Subject: [PATCH v3 02/11] ASoC: fsl: separate SSI and DMA Kconfig options
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331225990-27308-3-git-send-email-shawn.guo@linaro.org>

The fsl_ssi driver will possibly be shared between Freescale PowerPC
and ARM/IMX families, so give it a separate Kconfig option.  Then
fsl_ssi driver can possibly be selected independently from selecting
PowerPC DMA based PCM driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/Kconfig  |   15 +++++++++------
 sound/soc/fsl/Makefile |    3 ++-
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index d754d34..ca693b2 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,10 +1,11 @@
 config SND_MPC52xx_DMA
 	tristate
 
-# ASoC platform support for the Freescale PowerPC SOCs that have an SSI and
-# an Elo DMA controller, such as the MPC8610 and P1022.  You will still need to
-# select a platform driver and a codec driver.
-config SND_SOC_POWERPC_SSI
+config SND_SOC_FSL_SSI
+	tristate
+	depends on FSL_SOC
+
+config SND_SOC_POWERPC_DMA
 	tristate
 	depends on FSL_SOC
 
@@ -12,7 +13,8 @@ config SND_SOC_MPC8610_HPCD
 	tristate "ALSA SoC support for the Freescale MPC8610 HPCD board"
 	# I2C is necessary for the CS4270 driver
 	depends on MPC8610_HPCD && I2C
-	select SND_SOC_POWERPC_SSI
+	select SND_SOC_FSL_SSI
+	select SND_SOC_POWERPC_DMA
 	select SND_SOC_CS4270
 	select SND_SOC_CS4270_VD33_ERRATA
 	default y if MPC8610_HPCD
@@ -23,7 +25,8 @@ config SND_SOC_P1022_DS
 	tristate "ALSA SoC support for the Freescale P1022 DS board"
 	# I2C is necessary for the WM8776 driver
 	depends on P1022_DS && I2C
-	select SND_SOC_POWERPC_SSI
+	select SND_SOC_FSL_SSI
+	select SND_SOC_POWERPC_DMA
 	select SND_SOC_WM8776
 	default y if P1022_DS
 	help
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index b4a38c0..95d483f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -9,7 +9,8 @@ obj-$(CONFIG_SND_SOC_P1022_DS) += snd-soc-p1022-ds.o
 # Freescale PowerPC SSI/DMA Platform Support
 snd-soc-fsl-ssi-objs := fsl_ssi.o
 snd-soc-fsl-dma-objs := fsl_dma.o
-obj-$(CONFIG_SND_SOC_POWERPC_SSI) += snd-soc-fsl-ssi.o snd-soc-fsl-dma.o
+obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 
 # MPC5200 Platform Support
 obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Mar  8 11:59:42 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:42 +0800
Subject: [PATCH v3 03/11] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331225990-27308-4-git-send-email-shawn.guo@linaro.org>

Freescale PowerPC and ARM/IMX families share the same SSI IP block.
The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
code sharing and consolidation can happen.

This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
IMX platform.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig |    1 +
 arch/powerpc/configs/mpc85xx_defconfig           |    1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig       |    1 +
 sound/soc/Kconfig                                |    1 -
 sound/soc/Makefile                               |    1 -
 sound/soc/fsl/Kconfig                            |   92 ++++++++++++++++++++++
 sound/soc/fsl/Makefile                           |   22 +++++
 sound/soc/{imx => fsl}/eukrea-tlv320.c           |    2 +-
 sound/soc/{imx => fsl}/imx-audmux.c              |    0
 sound/soc/{imx => fsl}/imx-audmux.h              |    0
 sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c         |    0
 sound/soc/{imx => fsl}/imx-pcm-fiq.c             |    0
 sound/soc/{imx => fsl}/imx-pcm.c                 |    0
 sound/soc/{imx => fsl}/imx-pcm.h                 |    0
 sound/soc/{imx => fsl}/imx-ssi.c                 |    2 +-
 sound/soc/{imx => fsl}/imx-ssi.h                 |    0
 sound/soc/{imx => fsl}/mx27vis-aic32x4.c         |    0
 sound/soc/{imx => fsl}/phycore-ac97.c            |    0
 sound/soc/{imx => fsl}/wm1133-ev1.c              |    0
 sound/soc/imx/Kconfig                            |   79 -------------------
 sound/soc/imx/Makefile                           |   22 -----
 21 files changed, 119 insertions(+), 105 deletions(-)
 rename sound/soc/{imx => fsl}/eukrea-tlv320.c (99%)
 rename sound/soc/{imx => fsl}/imx-audmux.c (100%)
 rename sound/soc/{imx => fsl}/imx-audmux.h (100%)
 rename sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm-fiq.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm.h (100%)
 rename sound/soc/{imx => fsl}/imx-ssi.c (99%)
 rename sound/soc/{imx => fsl}/imx-ssi.h (100%)
 rename sound/soc/{imx => fsl}/mx27vis-aic32x4.c (100%)
 rename sound/soc/{imx => fsl}/phycore-ac97.c (100%)
 rename sound/soc/{imx => fsl}/wm1133-ev1.c (100%)
 delete mode 100644 sound/soc/imx/Kconfig
 delete mode 100644 sound/soc/imx/Makefile

diff --git a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
index 0db9ba0..c09598b 100644
--- a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
+++ b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
@@ -100,6 +100,7 @@ CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
 CONFIG_SND_SOC=y
+CONFIG_SND_POWERPC_SOC=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_EXT2_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index f37a2ab..44605f8 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -139,6 +139,7 @@ CONFIG_SND_INTEL8X0=y
 # CONFIG_SND_PPC is not set
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=y
+CONFIG_SND_POWERPC_SOC=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index abdcd31..98e227e 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -141,6 +141,7 @@ CONFIG_SND_INTEL8X0=y
 # CONFIG_SND_PPC is not set
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=y
+CONFIG_SND_POWERPC_SOC=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 91c9855..0f85f6d 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -35,7 +35,6 @@ source "sound/soc/blackfin/Kconfig"
 source "sound/soc/davinci/Kconfig"
 source "sound/soc/ep93xx/Kconfig"
 source "sound/soc/fsl/Kconfig"
-source "sound/soc/imx/Kconfig"
 source "sound/soc/jz4740/Kconfig"
 source "sound/soc/nuc900/Kconfig"
 source "sound/soc/omap/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 2feaf37..363dfd6 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_SND_SOC)	+= blackfin/
 obj-$(CONFIG_SND_SOC)	+= davinci/
 obj-$(CONFIG_SND_SOC)	+= ep93xx/
 obj-$(CONFIG_SND_SOC)	+= fsl/
-obj-$(CONFIG_SND_SOC)   += imx/
 obj-$(CONFIG_SND_SOC)	+= jz4740/
 obj-$(CONFIG_SND_SOC)	+= mid-x86/
 obj-$(CONFIG_SND_SOC)	+= mxs/
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index ca693b2..19856a0 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,3 +1,15 @@
+config SND_SOC_FSL_SSI
+	tristate
+
+menuconfig SND_POWERPC_SOC
+	tristate "SoC Audio for Freescale PowerPC CPUs"
+	depends on FSL_SOC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the PowerPC CPUs.
+
+if SND_POWERPC_SOC
+
 config SND_MPC52xx_DMA
 	tristate
 
@@ -68,3 +80,83 @@ config SND_MPC52xx_SOC_EFIKA
 	help
 	  Say Y if you want to add support for sound on the Efika.
 
+endif # SND_POWERPC_SOC
+
+menuconfig SND_IMX_SOC
+	tristate "SoC Audio for Freescale i.MX CPUs"
+	depends on ARCH_MXC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the i.MX CPUs.
+
+if SND_IMX_SOC
+
+config SND_SOC_IMX_SSI
+	tristate
+
+config SND_SOC_IMX_PCM
+	tristate
+
+config SND_MXC_SOC_FIQ
+	tristate
+	select FIQ
+	select SND_SOC_IMX_PCM
+
+config SND_MXC_SOC_MX2
+	tristate
+	select SND_SOC_DMAENGINE_PCM
+	select SND_SOC_IMX_PCM
+
+config SND_SOC_IMX_AUDMUX
+	tristate
+
+config SND_MXC_SOC_WM1133_EV1
+	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
+	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
+	select SND_SOC_WM8350
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
+	  PMIC board with WM8835x fitted.
+
+config SND_SOC_MX27VIS_AIC32X4
+	tristate "SoC audio support for Visstrim M10 boards"
+	depends on MACH_IMX27_VISSTRIM_M10 && I2C
+	select SND_SOC_TLV320AIC32X4
+	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Say Y if you want to add support for SoC audio on Visstrim SM10
+	  board with TLV320AIC32X4 codec.
+
+config SND_SOC_PHYCORE_AC97
+	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
+	depends on MACH_PCM043 || MACH_PCA100
+	select SND_SOC_AC97_BUS
+	select SND_SOC_WM9712
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Say Y if you want to add support for SoC audio on Phytec phyCORE
+	  and phyCARD boards in AC97 mode
+
+config SND_SOC_EUKREA_TLV320
+	tristate "Eukrea TLV320"
+	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
+	depends on I2C
+	select SND_SOC_TLV320AIC23
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Enable I2S based access to the TLV320AIC23B codec attached
+	  to the SSI interface
+
+endif # SND_IMX_SOC
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 95d483f..36c257f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -21,3 +21,25 @@ obj-$(CONFIG_SND_SOC_MPC5200_AC97) += mpc5200_psc_ac97.o
 obj-$(CONFIG_SND_MPC52xx_SOC_PCM030) += pcm030-audio-fabric.o
 obj-$(CONFIG_SND_MPC52xx_SOC_EFIKA) += efika-audio-fabric.o
 
+# i.MX Platform Support
+snd-soc-imx-ssi-objs := imx-ssi.o
+snd-soc-imx-audmux-objs := imx-audmux.o
+
+obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
+obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
+
+obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
+snd-soc-imx-pcm-y := imx-pcm.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
+
+# i.MX Machine Support
+snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
+snd-soc-phycore-ac97-objs := phycore-ac97.o
+snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
+snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+
+obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
+obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
+obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
+obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/fsl/eukrea-tlv320.c
similarity index 99%
rename from sound/soc/imx/eukrea-tlv320.c
rename to sound/soc/fsl/eukrea-tlv320.c
index 7d4475c..efb9ede 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/fsl/eukrea-tlv320.c
@@ -7,7 +7,7 @@
  * which is Copyright 2009 Simtec Electronics
  * and on sound/soc/imx/phycore-ac97.c which is
  * Copyright 2009 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
- * 
+ *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
  *  Free Software Foundation;  either version 2 of the  License, or (at your
diff --git a/sound/soc/imx/imx-audmux.c b/sound/soc/fsl/imx-audmux.c
similarity index 100%
rename from sound/soc/imx/imx-audmux.c
rename to sound/soc/fsl/imx-audmux.c
diff --git a/sound/soc/imx/imx-audmux.h b/sound/soc/fsl/imx-audmux.h
similarity index 100%
rename from sound/soc/imx/imx-audmux.h
rename to sound/soc/fsl/imx-audmux.h
diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/fsl/imx-pcm-dma-mx2.c
similarity index 100%
rename from sound/soc/imx/imx-pcm-dma-mx2.c
rename to sound/soc/fsl/imx-pcm-dma-mx2.c
diff --git a/sound/soc/imx/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
similarity index 100%
rename from sound/soc/imx/imx-pcm-fiq.c
rename to sound/soc/fsl/imx-pcm-fiq.c
diff --git a/sound/soc/imx/imx-pcm.c b/sound/soc/fsl/imx-pcm.c
similarity index 100%
rename from sound/soc/imx/imx-pcm.c
rename to sound/soc/fsl/imx-pcm.c
diff --git a/sound/soc/imx/imx-pcm.h b/sound/soc/fsl/imx-pcm.h
similarity index 100%
rename from sound/soc/imx/imx-pcm.h
rename to sound/soc/fsl/imx-pcm.h
diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
similarity index 99%
rename from sound/soc/imx/imx-ssi.c
rename to sound/soc/fsl/imx-ssi.c
index 9203cdd..3e0dac5a 100644
--- a/sound/soc/imx/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -28,7 +28,7 @@
  * value. When we read the same register two times (and the register still
  * contains the same value) these status bits are not set. We work
  * around this by not polling these bits but only wait a fixed delay.
- * 
+ *
  */
 
 #include <linux/clk.h>
diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/fsl/imx-ssi.h
similarity index 100%
rename from sound/soc/imx/imx-ssi.h
rename to sound/soc/fsl/imx-ssi.h
diff --git a/sound/soc/imx/mx27vis-aic32x4.c b/sound/soc/fsl/mx27vis-aic32x4.c
similarity index 100%
rename from sound/soc/imx/mx27vis-aic32x4.c
rename to sound/soc/fsl/mx27vis-aic32x4.c
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/fsl/phycore-ac97.c
similarity index 100%
rename from sound/soc/imx/phycore-ac97.c
rename to sound/soc/fsl/phycore-ac97.c
diff --git a/sound/soc/imx/wm1133-ev1.c b/sound/soc/fsl/wm1133-ev1.c
similarity index 100%
rename from sound/soc/imx/wm1133-ev1.c
rename to sound/soc/fsl/wm1133-ev1.c
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
deleted file mode 100644
index 810acaa..0000000
--- a/sound/soc/imx/Kconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-menuconfig SND_IMX_SOC
-	tristate "SoC Audio for Freescale i.MX CPUs"
-	depends on ARCH_MXC
-	help
-	  Say Y or M if you want to add support for codecs attached to
-	  the i.MX SSI interface.
-
-
-if SND_IMX_SOC
-
-config SND_SOC_IMX_SSI
-	tristate
-
-config SND_SOC_IMX_PCM
-	tristate
-
-config SND_MXC_SOC_FIQ
-	tristate
-	select FIQ
-	select SND_SOC_IMX_PCM
-
-config SND_MXC_SOC_MX2
-	select SND_SOC_DMAENGINE_PCM
-	tristate
-	select SND_SOC_IMX_PCM
-
-config SND_SOC_IMX_AUDMUX
-	tristate
-
-config SND_MXC_SOC_WM1133_EV1
-	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
-	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
-	select SND_SOC_WM8350
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
-	  PMIC board with WM8835x fitted.
-
-config SND_SOC_MX27VIS_AIC32X4
-	tristate "SoC audio support for Visstrim M10 boards"
-	depends on MACH_IMX27_VISSTRIM_M10 && I2C
-	select SND_SOC_TLV320AIC32X4
-	select SND_MXC_SOC_MX2
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Say Y if you want to add support for SoC audio on Visstrim SM10
-	  board with TLV320AIC32X4 codec.
-
-config SND_SOC_PHYCORE_AC97
-	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
-	depends on MACH_PCM043 || MACH_PCA100
-	select SND_SOC_AC97_BUS
-	select SND_SOC_WM9712
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Say Y if you want to add support for SoC audio on Phytec phyCORE
-	  and phyCARD boards in AC97 mode
-
-config SND_SOC_EUKREA_TLV320
-	tristate "Eukrea TLV320"
-	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
-	depends on I2C
-	select SND_SOC_TLV320AIC23
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Enable I2S based access to the TLV320AIC23B codec attached
-	  to the SSI interface
-
-endif	# SND_IMX_SOC
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
deleted file mode 100644
index f5db3e9..0000000
--- a/sound/soc/imx/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-# i.MX Platform Support
-snd-soc-imx-ssi-objs := imx-ssi.o
-snd-soc-imx-audmux-objs := imx-audmux.o
-
-obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
-obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
-
-obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
-snd-soc-imx-pcm-y := imx-pcm.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
-
-# i.MX Machine Support
-snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
-snd-soc-phycore-ac97-objs := phycore-ac97.o
-snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
-snd-soc-wm1133-ev1-objs := wm1133-ev1.o
-
-obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
-obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
-obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
-obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Mar  8 11:59:43 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:43 +0800
Subject: [PATCH v3 04/11] ASoC: fsl: rename imx-pcm Kconfig options and
 filename
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331225990-27308-5-git-send-email-shawn.guo@linaro.org>

Rename a couple of imx-pcm Kconfig options and filename to get them
well named and less confusing.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/Kconfig                              |   12 ++++++------
 sound/soc/fsl/Makefile                             |    4 ++--
 sound/soc/fsl/{imx-pcm-dma-mx2.c => imx-pcm-dma.c} |    0
 3 files changed, 8 insertions(+), 8 deletions(-)
 rename sound/soc/fsl/{imx-pcm-dma-mx2.c => imx-pcm-dma.c} (100%)

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 19856a0..e3f7509 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -97,12 +97,12 @@ config SND_SOC_IMX_SSI
 config SND_SOC_IMX_PCM
 	tristate
 
-config SND_MXC_SOC_FIQ
+config SND_SOC_IMX_PCM_FIQ
 	tristate
 	select FIQ
 	select SND_SOC_IMX_PCM
 
-config SND_MXC_SOC_MX2
+config SND_SOC_IMX_PCM_DMA
 	tristate
 	select SND_SOC_DMAENGINE_PCM
 	select SND_SOC_IMX_PCM
@@ -114,7 +114,7 @@ config SND_MXC_SOC_WM1133_EV1
 	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
 	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
 	select SND_SOC_WM8350
-	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_PCM_FIQ
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
@@ -125,7 +125,7 @@ config SND_SOC_MX27VIS_AIC32X4
 	tristate "SoC audio support for Visstrim M10 boards"
 	depends on MACH_IMX27_VISSTRIM_M10 && I2C
 	select SND_SOC_TLV320AIC32X4
-	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_PCM_DMA
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
@@ -137,7 +137,7 @@ config SND_SOC_PHYCORE_AC97
 	depends on MACH_PCM043 || MACH_PCA100
 	select SND_SOC_AC97_BUS
 	select SND_SOC_WM9712
-	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_PCM_FIQ
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
@@ -152,7 +152,7 @@ config SND_SOC_EUKREA_TLV320
 		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
 	depends on I2C
 	select SND_SOC_TLV320AIC23
-	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_PCM_FIQ
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 36c257f..f031409 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -30,8 +30,8 @@ obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
 
 obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
 snd-soc-imx-pcm-y := imx-pcm.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
+snd-soc-imx-pcm-$(CONFIG_SND_SOC_IMX_PCM_FIQ) += imx-pcm-fiq.o
+snd-soc-imx-pcm-$(CONFIG_SND_SOC_IMX_PCM_DMA) += imx-pcm-dma.o
 
 # i.MX Machine Support
 snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
diff --git a/sound/soc/fsl/imx-pcm-dma-mx2.c b/sound/soc/fsl/imx-pcm-dma.c
similarity index 100%
rename from sound/soc/fsl/imx-pcm-dma-mx2.c
rename to sound/soc/fsl/imx-pcm-dma.c
-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Mar  8 11:59:44 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:44 +0800
Subject: [PATCH v3 05/11] ASoC: fsl: create fsl_utils to accommodate the
 common functions
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331225990-27308-6-git-send-email-shawn.guo@linaro.org>

There is some amount of code duplication between mpc8610_hpcd and
p1022_ds machine drivers, and the same code will be duplicated again
when another new machine driver is added.  The patch creates fsl_utils
to accommodate the common functions to stop the code duplication.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/Kconfig        |    5 ++
 sound/soc/fsl/Makefile       |    2 +
 sound/soc/fsl/fsl_utils.c    |  135 ++++++++++++++++++++++++++++++++++++
 sound/soc/fsl/fsl_utils.h    |   27 +++++++
 sound/soc/fsl/mpc8610_hpcd.c |  157 +++---------------------------------------
 sound/soc/fsl/p1022_ds.c     |  149 +++-------------------------------------
 6 files changed, 189 insertions(+), 286 deletions(-)
 create mode 100644 sound/soc/fsl/fsl_utils.c
 create mode 100644 sound/soc/fsl/fsl_utils.h

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index e3f7509..535ee73 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,6 +1,9 @@
 config SND_SOC_FSL_SSI
 	tristate
 
+config SND_SOC_FSL_UTILS
+	tristate
+
 menuconfig SND_POWERPC_SOC
 	tristate "SoC Audio for Freescale PowerPC CPUs"
 	depends on FSL_SOC
@@ -26,6 +29,7 @@ config SND_SOC_MPC8610_HPCD
 	# I2C is necessary for the CS4270 driver
 	depends on MPC8610_HPCD && I2C
 	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
 	select SND_SOC_POWERPC_DMA
 	select SND_SOC_CS4270
 	select SND_SOC_CS4270_VD33_ERRATA
@@ -38,6 +42,7 @@ config SND_SOC_P1022_DS
 	# I2C is necessary for the WM8776 driver
 	depends on P1022_DS && I2C
 	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
 	select SND_SOC_POWERPC_DMA
 	select SND_SOC_WM8776
 	default y if P1022_DS
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index f031409..fbdbed0 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -8,8 +8,10 @@ obj-$(CONFIG_SND_SOC_P1022_DS) += snd-soc-p1022-ds.o
 
 # Freescale PowerPC SSI/DMA Platform Support
 snd-soc-fsl-ssi-objs := fsl_ssi.o
+snd-soc-fsl-utils-objs := fsl_utils.o
 snd-soc-fsl-dma-objs := fsl_dma.o
 obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
 obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 
 # MPC5200 Platform Support
diff --git a/sound/soc/fsl/fsl_utils.c b/sound/soc/fsl/fsl_utils.c
new file mode 100644
index 0000000..4370c28
--- /dev/null
+++ b/sound/soc/fsl/fsl_utils.c
@@ -0,0 +1,135 @@
+/**
+ * Freescale ALSA SoC Machine driver utility
+ *
+ * Author: Timur Tabi <timur at freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_i2c.h>
+#include <sound/soc.h>
+
+#include "fsl_utils.h"
+
+/**
+ * fsl_asoc_get_codec_dev_name - determine the dev_name for a codec node
+ *
+ * @np: pointer to the I2C device tree node
+ * @buf: buffer to be filled with the dev_name of the I2C device
+ * @len: the length of the buffer
+ *
+ * This function determines the dev_name for an I2C node.  This is the name
+ * that would be returned by dev_name() if this device_node were part of a
+ * 'struct device'  It's ugly and hackish, but it works.
+ *
+ * The dev_name for such devices include the bus number and I2C address. For
+ * example, "cs4270.0-004f".
+ */
+int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len)
+{
+	const u32 *iprop;
+	u32 addr;
+	char temp[DAI_NAME_SIZE];
+	struct i2c_client *i2c;
+
+	of_modalias_node(np, temp, DAI_NAME_SIZE);
+
+	iprop = of_get_property(np, "reg", NULL);
+	if (!iprop)
+		return -EINVAL;
+
+	addr = be32_to_cpup(iprop);
+
+	/* We need the adapter number */
+	i2c = of_find_i2c_device_by_node(np);
+	if (!i2c) {
+		put_device(&i2c->dev);
+		return -ENODEV;
+	}
+
+	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
+	put_device(&i2c->dev);
+
+	return 0;
+}
+EXPORT_SYMBOL(fsl_asoc_get_codec_dev_name);
+
+/**
+ * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
+ *
+ * @ssi_np: pointer to the SSI device tree node
+ * @name: name of the phandle pointing to the dma channel
+ * @dai: ASoC DAI link pointer to be filled with platform_name
+ * @dma_channel_id: dma channel id to be returned
+ * @dma_id: dma id to be returned
+ *
+ * This function determines the dma and channel id for given SSI node.  It
+ * also discovers the platform_name for the ASoC DAI link.
+ */
+int fsl_asoc_get_dma_channel(struct device_node *ssi_np,
+			     const char *name,
+			     struct snd_soc_dai_link *dai,
+			     unsigned int *dma_channel_id,
+			     unsigned int *dma_id)
+{
+	struct resource res;
+	struct device_node *dma_channel_np, *dma_np;
+	const u32 *iprop;
+	int ret;
+
+	dma_channel_np = of_parse_phandle(ssi_np, name, 0);
+	if (!dma_channel_np)
+		return -EINVAL;
+
+	if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) {
+		of_node_put(dma_channel_np);
+		return -EINVAL;
+	}
+
+	/* Determine the dev_name for the device_node.  This code mimics the
+	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
+	 * the dev_name() of the device to match the platform (DMA) device with
+	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
+	 * now).
+	 *
+	 * dai->platform name should already point to an allocated buffer.
+	 */
+	ret = of_address_to_resource(dma_channel_np, 0, &res);
+	if (ret) {
+		of_node_put(dma_channel_np);
+		return ret;
+	}
+	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
+		 (unsigned long long) res.start, dma_channel_np->name);
+
+	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
+	if (!iprop) {
+		of_node_put(dma_channel_np);
+		return -EINVAL;
+	}
+	*dma_channel_id = be32_to_cpup(iprop);
+
+	dma_np = of_get_parent(dma_channel_np);
+	iprop = of_get_property(dma_np, "cell-index", NULL);
+	if (!iprop) {
+		of_node_put(dma_np);
+		return -EINVAL;
+	}
+	*dma_id = be32_to_cpup(iprop);
+
+	of_node_put(dma_np);
+	of_node_put(dma_channel_np);
+
+	return 0;
+}
+EXPORT_SYMBOL(fsl_asoc_get_dma_channel);
+
+MODULE_AUTHOR("Timur Tabi <timur at freescale.com>");
+MODULE_DESCRIPTION("Freescale ASoC utility code");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/fsl/fsl_utils.h b/sound/soc/fsl/fsl_utils.h
new file mode 100644
index 0000000..44d1436
--- /dev/null
+++ b/sound/soc/fsl/fsl_utils.h
@@ -0,0 +1,27 @@
+/**
+ * Freescale ALSA SoC Machine driver utility
+ *
+ * Author: Timur Tabi <timur at freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef _FSL_UTILS_H
+#define _FSL_UTILS_H
+
+#define DAI_NAME_SIZE	32
+
+struct snd_soc_dai_link;
+struct device_node;
+
+int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len);
+int fsl_asoc_get_dma_channel(struct device_node *ssi_np, const char *name,
+			     struct snd_soc_dai_link *dai,
+			     unsigned int *dma_channel_id,
+			     unsigned int *dma_id);
+
+#endif /* _FSL_UTILS_H */
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index fcf9302..7ead1e5 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -14,18 +14,16 @@
 #include <linux/interrupt.h>
 #include <linux/of_device.h>
 #include <linux/slab.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 #include <asm/fsl_guts.h>
 
 #include "fsl_dma.h"
 #include "fsl_ssi.h"
+#include "fsl_utils.h"
 
 /* There's only one global utilities register */
 static phys_addr_t guts_phys;
 
-#define DAI_NAME_SIZE	32
-
 /**
  * mpc8610_hpcd_data: machine-specific ASoC device data
  *
@@ -181,141 +179,6 @@ static struct snd_soc_ops mpc8610_hpcd_ops = {
 };
 
 /**
- * get_node_by_phandle_name - get a node by its phandle name
- *
- * This function takes a node, the name of a property in that node, and a
- * compatible string.  Assuming the property is a phandle to another node,
- * it returns that node, (optionally) if that node is compatible.
- *
- * If the property is not a phandle, or the node it points to is not compatible
- * with the specific string, then NULL is returned.
- */
-static struct device_node *get_node_by_phandle_name(struct device_node *np,
-					       const char *name,
-					       const char *compatible)
-{
-	const phandle *ph;
-	int len;
-
-	ph = of_get_property(np, name, &len);
-	if (!ph || (len != sizeof(phandle)))
-		return NULL;
-
-	np = of_find_node_by_phandle(*ph);
-	if (!np)
-		return NULL;
-
-	if (compatible && !of_device_is_compatible(np, compatible)) {
-		of_node_put(np);
-		return NULL;
-	}
-
-	return np;
-}
-
-/**
- * get_parent_cell_index -- return the cell-index of the parent of a node
- *
- * Return the value of the cell-index property of the parent of the given
- * node.  This is used for DMA channel nodes that need to know the DMA ID
- * of the controller they are on.
- */
-static int get_parent_cell_index(struct device_node *np)
-{
-	struct device_node *parent = of_get_parent(np);
-	const u32 *iprop;
-
-	if (!parent)
-		return -1;
-
-	iprop = of_get_property(parent, "cell-index", NULL);
-	of_node_put(parent);
-
-	if (!iprop)
-		return -1;
-
-	return be32_to_cpup(iprop);
-}
-
-/**
- * codec_node_dev_name - determine the dev_name for a codec node
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270.0-004f".
- */
-static int codec_node_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	int addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c)
-		return -ENODEV;
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-
-	return 0;
-}
-
-static int get_dma_channel(struct device_node *ssi_np,
-			   const char *name,
-			   struct snd_soc_dai_link *dai,
-			   unsigned int *dma_channel_id,
-			   unsigned int *dma_id)
-{
-	struct resource res;
-	struct device_node *dma_channel_np;
-	const u32 *iprop;
-	int ret;
-
-	dma_channel_np = get_node_by_phandle_name(ssi_np, name,
-						  "fsl,ssi-dma-channel");
-	if (!dma_channel_np)
-		return -EINVAL;
-
-	/* Determine the dev_name for the device_node.  This code mimics the
-	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
-	 * the dev_name() of the device to match the platform (DMA) device with
-	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
-	 * now).
-	 *
-	 * dai->platform name should already point to an allocated buffer.
-	 */
-	ret = of_address_to_resource(dma_channel_np, 0, &res);
-	if (ret)
-		return ret;
-	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
-		 (unsigned long long) res.start, dma_channel_np->name);
-
-	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
-	if (!iprop) {
-		of_node_put(dma_channel_np);
-		return -EINVAL;
-	}
-
-	*dma_channel_id = be32_to_cpup(iprop);
-	*dma_id = get_parent_cell_index(dma_channel_np);
-	of_node_put(dma_channel_np);
-
-	return 0;
-}
-
-/**
  * mpc8610_hpcd_probe: platform probe function for the machine driver
  *
  * Although this is a machine driver, the SSI node is the "master" node with
@@ -353,8 +216,8 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 	machine_data->dai[0].ops = &mpc8610_hpcd_ops;
 
 	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = codec_node_dev_name(codec_np, machine_data->codec_name,
-				  DAI_NAME_SIZE);
+	ret = fsl_asoc_get_codec_dev_name(codec_np, machine_data->codec_name,
+					  DAI_NAME_SIZE);
 	if (ret) {
 		dev_err(&pdev->dev, "invalid codec node %s\n",
 			codec_np->full_name);
@@ -458,9 +321,10 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 
 	/* Find the playback DMA channel to use. */
 	machine_data->dai[0].platform_name = machine_data->platform_name[0];
-	ret = get_dma_channel(np, "fsl,playback-dma", &machine_data->dai[0],
-			      &machine_data->dma_channel_id[0],
-			      &machine_data->dma_id[0]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma",
+				       &machine_data->dai[0],
+				       &machine_data->dma_channel_id[0],
+				       &machine_data->dma_id[0]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
 		goto error;
@@ -468,9 +332,10 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 
 	/* Find the capture DMA channel to use. */
 	machine_data->dai[1].platform_name = machine_data->platform_name[1];
-	ret = get_dma_channel(np, "fsl,capture-dma", &machine_data->dai[1],
-			      &machine_data->dma_channel_id[1],
-			      &machine_data->dma_id[1]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma",
+				       &machine_data->dai[1],
+				       &machine_data->dma_channel_id[1],
+				       &machine_data->dma_id[1]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
 		goto error;
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index d32ec46..60f7bb8 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -14,12 +14,12 @@
 #include <linux/interrupt.h>
 #include <linux/of_device.h>
 #include <linux/slab.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 #include <asm/fsl_guts.h>
 
 #include "fsl_dma.h"
 #include "fsl_ssi.h"
+#include "fsl_utils.h"
 
 /* P1022-specific PMUXCR and DMUXCR bit definitions */
 
@@ -57,8 +57,6 @@ static inline void guts_set_dmuxcr(struct ccsr_guts_85xx __iomem *guts,
 /* There's only one global utilities register */
 static phys_addr_t guts_phys;
 
-#define DAI_NAME_SIZE	32
-
 /**
  * machine_data: machine-specific ASoC device data
  *
@@ -191,136 +189,6 @@ static struct snd_soc_ops p1022_ds_ops = {
 };
 
 /**
- * get_node_by_phandle_name - get a node by its phandle name
- *
- * This function takes a node, the name of a property in that node, and a
- * compatible string.  Assuming the property is a phandle to another node,
- * it returns that node, (optionally) if that node is compatible.
- *
- * If the property is not a phandle, or the node it points to is not compatible
- * with the specific string, then NULL is returned.
- */
-static struct device_node *get_node_by_phandle_name(struct device_node *np,
-	const char *name, const char *compatible)
-{
-	np = of_parse_phandle(np, name, 0);
-	if (!np)
-		return NULL;
-
-	if (!of_device_is_compatible(np, compatible)) {
-		of_node_put(np);
-		return NULL;
-	}
-
-	return np;
-}
-
-/**
- * get_parent_cell_index -- return the cell-index of the parent of a node
- *
- * Return the value of the cell-index property of the parent of the given
- * node.  This is used for DMA channel nodes that need to know the DMA ID
- * of the controller they are on.
- */
-static int get_parent_cell_index(struct device_node *np)
-{
-	struct device_node *parent = of_get_parent(np);
-	const u32 *iprop;
-	int ret = -1;
-
-	if (!parent)
-		return -1;
-
-	iprop = of_get_property(parent, "cell-index", NULL);
-	if (iprop)
-		ret = be32_to_cpup(iprop);
-
-	of_node_put(parent);
-
-	return ret;
-}
-
-/**
- * codec_node_dev_name - determine the dev_name for a codec node
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270-codec.0-004f".
- */
-static int codec_node_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	int addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c)
-		return -ENODEV;
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-
-	return 0;
-}
-
-static int get_dma_channel(struct device_node *ssi_np,
-			   const char *name,
-			   struct snd_soc_dai_link *dai,
-			   unsigned int *dma_channel_id,
-			   unsigned int *dma_id)
-{
-	struct resource res;
-	struct device_node *dma_channel_np;
-	const u32 *iprop;
-	int ret;
-
-	dma_channel_np = get_node_by_phandle_name(ssi_np, name,
-						  "fsl,ssi-dma-channel");
-	if (!dma_channel_np)
-		return -EINVAL;
-
-	/* Determine the dev_name for the device_node.  This code mimics the
-	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
-	 * the dev_name() of the device to match the platform (DMA) device with
-	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
-	 * now).
-	 *
-	 * dai->platform name should already point to an allocated buffer.
-	 */
-	ret = of_address_to_resource(dma_channel_np, 0, &res);
-	if (ret) {
-		of_node_put(dma_channel_np);
-		return ret;
-	}
-	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
-		 (unsigned long long) res.start, dma_channel_np->name);
-
-	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
-	if (!iprop) {
-		of_node_put(dma_channel_np);
-		return -EINVAL;
-	}
-
-	*dma_channel_id = be32_to_cpup(iprop);
-	*dma_id = get_parent_cell_index(dma_channel_np);
-	of_node_put(dma_channel_np);
-
-	return 0;
-}
-
-/**
  * p1022_ds_probe: platform probe function for the machine driver
  *
  * Although this is a machine driver, the SSI node is the "master" node with
@@ -358,7 +226,8 @@ static int p1022_ds_probe(struct platform_device *pdev)
 	mdata->dai[0].ops = &p1022_ds_ops;
 
 	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = codec_node_dev_name(codec_np, mdata->codec_name, DAI_NAME_SIZE);
+	ret = fsl_asoc_get_codec_dev_name(codec_np, mdata->codec_name,
+					  DAI_NAME_SIZE);
 	if (ret) {
 		dev_err(&pdev->dev, "invalid codec node %s\n",
 			codec_np->full_name);
@@ -454,9 +323,9 @@ static int p1022_ds_probe(struct platform_device *pdev)
 
 	/* Find the playback DMA channel to use. */
 	mdata->dai[0].platform_name = mdata->platform_name[0];
-	ret = get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
-			      &mdata->dma_channel_id[0],
-			      &mdata->dma_id[0]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
+				       &mdata->dma_channel_id[0],
+				       &mdata->dma_id[0]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
 		goto error;
@@ -464,9 +333,9 @@ static int p1022_ds_probe(struct platform_device *pdev)
 
 	/* Find the capture DMA channel to use. */
 	mdata->dai[1].platform_name = mdata->platform_name[1];
-	ret = get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
-			      &mdata->dma_channel_id[1],
-			      &mdata->dma_id[1]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
+				       &mdata->dma_channel_id[1],
+				       &mdata->dma_id[1]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
 		goto error;
-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Mar  8 11:59:45 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:45 +0800
Subject: [PATCH v3 06/11] ASoC: fsl: remove helper fsl_asoc_get_codec_dev_name
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331225990-27308-7-git-send-email-shawn.guo@linaro.org>

The ASoC core now can support matching codec with device node besides
name, so we can save helper function fsl_asoc_get_codec_dev_name.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_utils.c    |   44 ------------------------------------------
 sound/soc/fsl/fsl_utils.h    |    1 -
 sound/soc/fsl/mpc8610_hpcd.c |   13 +----------
 sound/soc/fsl/p1022_ds.c     |   13 +----------
 4 files changed, 4 insertions(+), 67 deletions(-)

diff --git a/sound/soc/fsl/fsl_utils.c b/sound/soc/fsl/fsl_utils.c
index 4370c28..b9e42b5 100644
--- a/sound/soc/fsl/fsl_utils.c
+++ b/sound/soc/fsl/fsl_utils.c
@@ -12,55 +12,11 @@
 
 #include <linux/module.h>
 #include <linux/of_address.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 
 #include "fsl_utils.h"
 
 /**
- * fsl_asoc_get_codec_dev_name - determine the dev_name for a codec node
- *
- * @np: pointer to the I2C device tree node
- * @buf: buffer to be filled with the dev_name of the I2C device
- * @len: the length of the buffer
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270.0-004f".
- */
-int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	u32 addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c) {
-		put_device(&i2c->dev);
-		return -ENODEV;
-	}
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-	put_device(&i2c->dev);
-
-	return 0;
-}
-EXPORT_SYMBOL(fsl_asoc_get_codec_dev_name);
-
-/**
  * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
  *
  * @ssi_np: pointer to the SSI device tree node
diff --git a/sound/soc/fsl/fsl_utils.h b/sound/soc/fsl/fsl_utils.h
index 44d1436..b295112 100644
--- a/sound/soc/fsl/fsl_utils.h
+++ b/sound/soc/fsl/fsl_utils.h
@@ -18,7 +18,6 @@
 struct snd_soc_dai_link;
 struct device_node;
 
-int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len);
 int fsl_asoc_get_dma_channel(struct device_node *ssi_np, const char *name,
 			     struct snd_soc_dai_link *dai,
 			     unsigned int *dma_channel_id,
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index 7ead1e5..354b753 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -41,7 +41,6 @@ struct mpc8610_hpcd_data {
 	unsigned int dma_id[2];		/* 0 = DMA1, 1 = DMA2, etc */
 	unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
 	char codec_dai_name[DAI_NAME_SIZE];
-	char codec_name[DAI_NAME_SIZE];
 	char platform_name[2][DAI_NAME_SIZE]; /* One for each DMA channel */
 };
 
@@ -215,16 +214,8 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 	machine_data->dai[0].cpu_dai_name = dev_name(&ssi_pdev->dev);
 	machine_data->dai[0].ops = &mpc8610_hpcd_ops;
 
-	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = fsl_asoc_get_codec_dev_name(codec_np, machine_data->codec_name,
-					  DAI_NAME_SIZE);
-	if (ret) {
-		dev_err(&pdev->dev, "invalid codec node %s\n",
-			codec_np->full_name);
-		ret = -EINVAL;
-		goto error;
-	}
-	machine_data->dai[0].codec_name = machine_data->codec_name;
+	/* ASoC core can match codec with device node */
+	machine_data->dai[0].codec_of_node = codec_np;
 
 	/* The DAI name from the codec (snd_soc_dai_driver.name) */
 	machine_data->dai[0].codec_dai_name = "cs4270-hifi";
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index 60f7bb8..e87cb41 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -73,7 +73,6 @@ struct machine_data {
 	unsigned int ssi_id;		/* 0 = SSI1, 1 = SSI2, etc */
 	unsigned int dma_id[2];		/* 0 = DMA1, 1 = DMA2, etc */
 	unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
-	char codec_name[DAI_NAME_SIZE];
 	char platform_name[2][DAI_NAME_SIZE]; /* One for each DMA channel */
 };
 
@@ -225,16 +224,8 @@ static int p1022_ds_probe(struct platform_device *pdev)
 	mdata->dai[0].cpu_dai_name = dev_name(&ssi_pdev->dev);
 	mdata->dai[0].ops = &p1022_ds_ops;
 
-	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = fsl_asoc_get_codec_dev_name(codec_np, mdata->codec_name,
-					  DAI_NAME_SIZE);
-	if (ret) {
-		dev_err(&pdev->dev, "invalid codec node %s\n",
-			codec_np->full_name);
-		ret = -EINVAL;
-		goto error;
-	}
-	mdata->dai[0].codec_name = mdata->codec_name;
+	/* ASoC core can match codec with device node */
+	mdata->dai[0].codec_of_node = codec_np;
 
 	/* We register two DAIs per SSI, one for playback and the other for
 	 * capture.  We support codecs that have separate DAIs for both playback
-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Mar  8 11:59:46 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:46 +0800
Subject: [PATCH v3 07/11] ASoC: fsl: check property 'compatible' for the
 machine name
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331225990-27308-8-git-send-email-shawn.guo@linaro.org>

Check /compatible rather than /model to determine the machine name.
The p1022ds older device trees get a different /model from the new
ones, while /compatible is consistent there, so checking /compatible
will save the bother of detecting older p1022ds device trees.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c      |    6 +++---
 sound/soc/fsl/mpc8610_hpcd.c |    2 +-
 sound/soc/fsl/p1022_ds.c     |   32 +++++---------------------------
 3 files changed, 9 insertions(+), 31 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 3e06696..2eb407f 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -716,12 +716,12 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 	}
 
 	/* Trigger the machine driver's probe function.  The platform driver
-	 * name of the machine driver is taken from the /model property of the
+	 * name of the machine driver is taken from /compatible property of the
 	 * device tree.  We also pass the address of the CPU DAI driver
 	 * structure.
 	 */
-	sprop = of_get_property(of_find_node_by_path("/"), "model", NULL);
-	/* Sometimes the model name has a "fsl," prefix, so we strip that. */
+	sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
+	/* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
 	p = strrchr(sprop, ',');
 	if (p)
 		sprop = p + 1;
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index 354b753..8fdc430 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -402,7 +402,7 @@ static struct platform_driver mpc8610_hpcd_driver = {
 	.probe = mpc8610_hpcd_probe,
 	.remove = __devexit_p(mpc8610_hpcd_remove),
 	.driver = {
-		/* The name must match the 'model' property in the device tree,
+		/* The name must match 'compatible' property in the device tree,
 		 * in lowercase letters.
 		 */
 		.name = "snd-soc-mpc8610hpcd",
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index e87cb41..0f42f31 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -403,6 +403,11 @@ static struct platform_driver p1022_ds_driver = {
 	.probe = p1022_ds_probe,
 	.remove = __devexit_p(p1022_ds_remove),
 	.driver = {
+		/*
+		 * The name must match 'compatible' property in the device tree,
+		 * in lowercase letters.
+		 */
+		.name = "snd-soc-p1022ds",
 		.owner = THIS_MODULE,
 	},
 };
@@ -416,33 +421,6 @@ static int __init p1022_ds_init(void)
 {
 	struct device_node *guts_np;
 	struct resource res;
-	const char *sprop;
-
-	/*
-	 * Check if we're actually running on a P1022DS.  Older device trees
-	 * have a model of "fsl,P1022" and newer ones use "fsl,P1022DS", so we
-	 * need to support both.  The SSI driver uses that property to link to
-	 * the machine driver, so have to match it.
-	 */
-	sprop = of_get_property(of_find_node_by_path("/"), "model", NULL);
-	if (!sprop) {
-		pr_err("snd-soc-p1022ds: missing /model node");
-		return -ENODEV;
-	}
-
-	pr_debug("snd-soc-p1022ds: board model name is %s\n", sprop);
-
-	/*
-	 * The name of this board, taken from the device tree.  Normally, this is a*
-	 * fixed string, but some P1022DS device trees have a /model property of
-	 * "fsl,P1022", and others have "fsl,P1022DS".
-	 */
-	if (strcasecmp(sprop, "fsl,p1022ds") == 0)
-		p1022_ds_driver.driver.name = "snd-soc-p1022ds";
-	else if (strcasecmp(sprop, "fsl,p1022") == 0)
-		p1022_ds_driver.driver.name = "snd-soc-p1022";
-	else
-		return -ENODEV;
 
 	/* Get the physical address of the global utilities registers */
 	guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Mar  8 11:59:47 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:47 +0800
Subject: [PATCH v3 08/11] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331225990-27308-9-git-send-email-shawn.guo@linaro.org>

Provide different pair of accessors for accessing SSI registers on
PowerPC and ARM/IMX, so that fsl_ssi driver can be built on both
architectures.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |   67 +++++++++++++++++++++++++++++++---------------
 1 files changed, 45 insertions(+), 22 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 2eb407f..aee2066 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -11,12 +11,16 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/spinlock.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -26,6 +30,27 @@
 
 #include "fsl_ssi.h"
 
+#ifdef PPC
+#define read_ssi(addr)			 in_be32(addr)
+#define write_ssi(val, addr)		 out_be32(addr, val)
+#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
+#elif defined ARM
+#define read_ssi(addr)			 readl(addr)
+#define write_ssi(val, addr)		 writel(val, addr)
+static DEFINE_SPINLOCK(ssi_reg_lock);
+static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
+{
+	u32 val;
+	unsigned long flags;
+
+	spin_lock_irqsave(&ssi_reg_lock, flags);
+	val = readl(addr);
+	val = (val & ~clear) | set;
+	writel(val, addr);
+	spin_unlock_irqrestore(&ssi_reg_lock, flags);
+}
+#endif
+
 /**
  * FSLSSI_I2S_RATES: sample rates supported by the I2S
  *
@@ -145,7 +170,7 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 	   were interrupted for.  We mask it with the Interrupt Enable register
 	   so that we only check for events that we're interested in.
 	 */
-	sisr = in_be32(&ssi->sisr) & SIER_FLAGS;
+	sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
 
 	if (sisr & CCSR_SSI_SISR_RFRC) {
 		ssi_private->stats.rfrc++;
@@ -260,7 +285,7 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 
 	/* Clear the bits that we set */
 	if (sisr2)
-		out_be32(&ssi->sisr, sisr2);
+		write_ssi(sisr2, &ssi->sisr);
 
 	return ret;
 }
@@ -295,7 +320,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 * SSI needs to be disabled before updating the registers we set
 		 * here.
 		 */
-		clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
+		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
 
 		/*
 		 * Program the SSI into I2S Slave Non-Network Synchronous mode.
@@ -303,20 +328,18 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 *
 		 * FIXME: Little-endian samples require a different shift dir
 		 */
-		clrsetbits_be32(&ssi->scr,
+		write_ssi_mask(&ssi->scr,
 			CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
 			CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE
 			| (synchronous ? CCSR_SSI_SCR_SYN : 0));
 
-		out_be32(&ssi->stcr,
-			 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
+		write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
 			 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
-			 CCSR_SSI_STCR_TSCKP);
+			 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
 
-		out_be32(&ssi->srcr,
-			 CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
+		write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
 			 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
-			 CCSR_SSI_SRCR_RSCKP);
+			 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
 
 		/*
 		 * The DC and PM bits are only used if the SSI is the clock
@@ -324,7 +347,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 */
 
 		/* Enable the interrupts and DMA requests */
-		out_be32(&ssi->sier, SIER_FLAGS);
+		write_ssi(SIER_FLAGS, &ssi->sier);
 
 		/*
 		 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
@@ -339,9 +362,9 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 * make this value larger (and maybe we should), but this way
 		 * data will be written to memory as soon as it's available.
 		 */
-		out_be32(&ssi->sfcsr,
-			CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
-			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2));
+		write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
+			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2),
+			&ssi->sfcsr);
 
 		/*
 		 * We keep the SSI disabled because if we enable it, then the
@@ -417,7 +440,7 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 	unsigned int sample_size =
 		snd_pcm_format_width(params_format(hw_params));
 	u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
-	int enabled = in_be32(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
+	int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
 
 	/*
 	 * If we're in synchronous mode, and the SSI is already enabled,
@@ -439,9 +462,9 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 	/* In synchronous mode, the SSI uses STCCR for capture */
 	if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
 	    ssi_private->cpu_dai_drv.symmetric_rates)
-		clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+		write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
 	else
-		clrsetbits_be32(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+		write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
 
 	return 0;
 }
@@ -466,19 +489,19 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-			setbits32(&ssi->scr,
+			write_ssi_mask(&ssi->scr, 0,
 				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
 		else
-			setbits32(&ssi->scr,
+			write_ssi_mask(&ssi->scr, 0,
 				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
 		break;
 
 	case SNDRV_PCM_TRIGGER_STOP:
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-			clrbits32(&ssi->scr, CCSR_SSI_SCR_TE);
+			write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
 		else
-			clrbits32(&ssi->scr, CCSR_SSI_SCR_RE);
+			write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
 		break;
 
 	default:
@@ -510,7 +533,7 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
 	if (!ssi_private->first_stream) {
 		struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 
-		clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
+		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
 	}
 }
 
-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Mar  8 11:59:48 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:48 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>

As Documentation/devicetree/bindings/powerpc/fsl/ssi.txt documented,
codec-handle is an optional property, so missing it should not be a
fatal error.

More importantly, the imx machine drivers to be added working with
fsl_ssi will not have this property, as they use new ASoC machine
driver binding mechanism.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index aee2066..e5903cb 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -645,12 +645,6 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 	if (!of_device_is_available(np))
 		return -ENODEV;
 
-	/* Check for a codec-handle property. */
-	if (!of_get_property(np, "codec-handle", NULL)) {
-		dev_err(&pdev->dev, "missing codec-handle property\n");
-		return -ENODEV;
-	}
-
 	/* We only support the SSI in "I2S Slave" mode */
 	sprop = of_get_property(np, "fsl,mode", NULL);
 	if (!sprop || strcmp(sprop, "i2s-slave")) {
-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Mar  8 11:59:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:49 +0800
Subject: [PATCH v3 10/11] ASoC: fsl: let fsl_ssi work with imx pcm and machine
 drivers
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331225990-27308-11-git-send-email-shawn.guo@linaro.org>

Makes necessary changes on fsl_ssi to let it work with imx pcm and
machine drivers.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |   67 +++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 67 insertions(+), 0 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index e5903cb..c251ee9 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -29,6 +29,7 @@
 #include <sound/soc.h>
 
 #include "fsl_ssi.h"
+#include "imx-pcm.h"
 
 #ifdef PPC
 #define read_ssi(addr)			 in_be32(addr)
@@ -119,6 +120,11 @@ struct fsl_ssi_private {
 	struct device_attribute dev_attr;
 	struct platform_device *pdev;
 
+	int ssi_on_imx;
+	struct platform_device *imx_pcm_pdev;
+	struct imx_pcm_dma_params dma_params_tx;
+	struct imx_pcm_dma_params dma_params_rx;
+
 	struct {
 		unsigned int rfrc;
 		unsigned int tfrc;
@@ -416,6 +422,12 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		ssi_private->second_stream = substream;
 	}
 
+	if (ssi_private->ssi_on_imx)
+		snd_soc_dai_set_dma_data(dai, substream,
+			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+				&ssi_private->dma_params_tx :
+				&ssi_private->dma_params_rx);
+
 	return 0;
 }
 
@@ -709,6 +721,38 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
                 /* Older 8610 DTs didn't have the fifo-depth property */
 		ssi_private->fifo_depth = 8;
 
+	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx1-ssi")) {
+		u32 dma_events[2];
+		ssi_private->ssi_on_imx = 1;
+		/*
+		 * FIXME: The dma burst size must equal to ssi watermark
+		 * setting on imx.  We have burstsize be "fifo_depth - 2"
+		 * here because "fifo_depth - 2" rather than fifo_depth is
+		 * being written into watermark register in fsl_ssi_startup().
+		 * Is this something needs to be fixed for PowerPC?
+		 */
+		ssi_private->dma_params_tx.burstsize =
+			ssi_private->fifo_depth - 2;
+		ssi_private->dma_params_rx.burstsize =
+			ssi_private->fifo_depth - 2;
+		ssi_private->dma_params_tx.dma_addr =
+			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
+		ssi_private->dma_params_rx.dma_addr =
+			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
+		/*
+		 * TODO: This is a temporary solution and should be changed
+		 * to use generic DMA binding later when the helplers get in.
+		 */
+		ret = of_property_read_u32_array(pdev->dev.of_node,
+					"fsl,ssi-dma-events", dma_events, 2);
+		if (ret) {
+			dev_err(&pdev->dev, "could not get dma events\n");
+			goto error_irq;
+		}
+		ssi_private->dma_params_tx.dma = dma_events[0];
+		ssi_private->dma_params_rx.dma = dma_events[1];
+	}
+
 	/* Initialize the the device_attribute structure */
 	dev_attr = &ssi_private->dev_attr;
 	sysfs_attr_init(&dev_attr->attr);
@@ -732,6 +776,24 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 		goto error_dev;
 	}
 
+	/*
+	 * In case of imx, the machine driver uses new binding which does
+	 * not require SSI driver to trigger machine driver's probe, but
+	 * the pcm device needs to be registered here.
+	 */
+	if (ssi_private->ssi_on_imx) {
+		ssi_private->imx_pcm_pdev =
+			platform_device_register_simple("imx-pcm-audio",
+							-1, NULL, 0);
+		if (IS_ERR(ssi_private->imx_pcm_pdev)) {
+			ret = PTR_ERR(ssi_private->imx_pcm_pdev);
+			goto error_dev;
+		} else {
+			/* success for imx */
+			return 0;
+		}
+	}
+
 	/* Trigger the machine driver's probe function.  The platform driver
 	 * name of the machine driver is taken from /compatible property of the
 	 * device tree.  We also pass the address of the CPU DAI driver
@@ -757,6 +819,8 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 
 error_dai:
 	snd_soc_unregister_dai(&pdev->dev);
+	if (ssi_private->ssi_on_imx)
+		platform_device_unregister(ssi_private->imx_pcm_pdev);
 
 error_dev:
 	dev_set_drvdata(&pdev->dev, NULL);
@@ -783,6 +847,8 @@ static int fsl_ssi_remove(struct platform_device *pdev)
 
 	platform_device_unregister(ssi_private->pdev);
 	snd_soc_unregister_dai(&pdev->dev);
+	if (ssi_private->ssi_on_imx)
+		platform_device_unregister(ssi_private->imx_pcm_pdev);
 	device_remove_file(&pdev->dev, &ssi_private->dev_attr);
 
 	free_irq(ssi_private->irq, ssi_private);
@@ -796,6 +862,7 @@ static int fsl_ssi_remove(struct platform_device *pdev)
 
 static const struct of_device_id fsl_ssi_ids[] = {
 	{ .compatible = "fsl,mpc8610-ssi", },
+	{ .compatible = "fsl,imx1-ssi", },
 	{}
 };
 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
-- 
1.7.5.4



From shawn.guo at linaro.org  Thu Mar  8 11:59:50 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri,  9 Mar 2012 00:59:50 +0800
Subject: [PATCH v3 11/11] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331225990-27308-12-git-send-email-shawn.guo@linaro.org>

This is the initial imx-sgtl5000 machine driver support.  It's a device
tree only machine driver working with fsl_ssi driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../bindings/sound/imx-audio-sgtl5000.txt          |   24 +++
 sound/soc/fsl/Kconfig                              |   12 ++
 sound/soc/fsl/Makefile                             |    2 +
 sound/soc/fsl/imx-sgtl5000.c                       |  177 ++++++++++++++++++++
 4 files changed, 215 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
 create mode 100644 sound/soc/fsl/imx-sgtl5000.c

diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
new file mode 100644
index 0000000..421a374
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
@@ -0,0 +1,24 @@
+Freescale i.MX audio complex with SGTL5000 codec
+
+Required properties:
+- compatible : "fsl,imx-audio-sgtl5000"
+- model : The user-visible name of this sound complex
+- ssi-controller : The phandle of the i.MX SSI controller
+- audio-codec : The phandle of the SGTL5000 audio codec
+- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
+- mux-ext-port : The external port of the i.MX audio muxer
+
+Note: The AUDMUX port numbering should start at 1, which is consistent with
+hardware manual.
+
+Example:
+
+sound {
+	compatible = "fsl,imx51-babbage-sgtl5000",
+		     "fsl,imx-audio-sgtl5000";
+	model = "imx51-babbage-sgtl5000";
+	ssi-controller = <&ssi1>;
+	audio-codec = <&sgtl5000>;
+	mux-int-port = <1>;
+	mux-ext-port = <3>;
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 535ee73..aa14fc9 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -164,4 +164,16 @@ config SND_SOC_EUKREA_TLV320
 	  Enable I2S based access to the TLV320AIC23B codec attached
 	  to the SSI interface
 
+config SND_SOC_IMX_SGTL5000
+	tristate "SoC Audio support for i.MX boards with sgtl5000"
+	depends on OF && I2C
+	select SND_SOC_SGTL5000
+	select SND_SOC_IMX_PCM_DMA
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
+	help
+	  Say Y if you want to add support for SoC audio on an i.MX board with
+	  a sgtl5000 codec.
+
 endif # SND_IMX_SOC
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index fbdbed0..638d385 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -40,8 +40,10 @@ snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
 snd-soc-phycore-ac97-objs := phycore-ac97.o
 snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
 snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
 
 obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
 obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
 obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
 obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
+obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
diff --git a/sound/soc/fsl/imx-sgtl5000.c b/sound/soc/fsl/imx-sgtl5000.c
new file mode 100644
index 0000000..3786b61
--- /dev/null
+++ b/sound/soc/fsl/imx-sgtl5000.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <sound/soc.h>
+
+#include "../codecs/sgtl5000.h"
+#include "imx-audmux.h"
+
+#define DAI_NAME_SIZE	32
+
+struct imx_sgtl5000_data {
+	struct snd_soc_dai_link dai;
+	struct snd_soc_card card;
+	char codec_dai_name[DAI_NAME_SIZE];
+	char platform_name[DAI_NAME_SIZE];
+	unsigned int clk_frequency;
+};
+
+static int imx_sgtl5000_dai_init(struct snd_soc_pcm_runtime *rtd)
+{
+	struct imx_sgtl5000_data *data = container_of(rtd->card,
+					struct imx_sgtl5000_data, card);
+	struct device *dev = rtd->card->dev;
+	int ret;
+
+	ret = snd_soc_dai_set_sysclk(rtd->codec_dai, SGTL5000_SYSCLK,
+				     data->clk_frequency, SND_SOC_CLOCK_IN);
+	if (ret) {
+		dev_err(dev, "could not set codec driver clock params\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __devinit imx_sgtl5000_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *ssi_np, *codec_np;
+	struct platform_device *ssi_pdev;
+	struct imx_sgtl5000_data *data;
+	int int_port, ext_port;
+	int ret;
+
+	ret = of_property_read_u32(np, "mux-int-port", &int_port);
+	if (ret) {
+		dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
+		return ret;
+	}
+	ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
+	if (ret) {
+		dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
+		return ret;
+	}
+
+	/*
+	 * The port numbering in the hardware manual starts at 1, while
+	 * the audmux API expects it starts at 0.
+	 */
+	int_port--;
+	ext_port--;
+	ret = imx_audmux_v2_configure_port(int_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TFSDIR |
+			IMX_AUDMUX_V2_PTCR_TCLKDIR,
+			IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
+	if (ret) {
+		dev_err(&pdev->dev, "audmux internal port setup failed\n");
+		return ret;
+	}
+	imx_audmux_v2_configure_port(ext_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TCSEL(int_port),
+			IMX_AUDMUX_V2_PDCR_RXDSEL(int_port));
+	if (ret) {
+		dev_err(&pdev->dev, "audmux external port setup failed\n");
+		return ret;
+	}
+
+	ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
+	codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
+	if (!ssi_np || !codec_np) {
+		dev_err(&pdev->dev, "phandle missing or invalid\n");
+		return -EINVAL;
+	}
+
+	ssi_pdev = of_find_device_by_node(ssi_np);
+	if (!ssi_pdev) {
+		dev_err(&pdev->dev, "failed to find SSI platform device\n");
+		return -EINVAL;
+	}
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	ret = of_property_read_u32(codec_np, "clock-frequency",
+				   &data->clk_frequency);
+	if (ret) {
+		dev_err(&pdev->dev, "clock-frequency missing or invalid\n");
+		return ret;
+	}
+
+	data->dai.name = "HiFi";
+	data->dai.stream_name = "HiFi";
+	data->dai.codec_dai_name = "sgtl5000";
+	data->dai.codec_of_node = codec_np;
+	data->dai.cpu_dai_name = dev_name(&ssi_pdev->dev);
+	data->dai.platform_name = "imx-pcm-audio";
+	data->dai.init = &imx_sgtl5000_dai_init;
+	data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+			    SND_SOC_DAIFMT_CBM_CFM;
+
+	data->card.dev = &pdev->dev;
+	ret = snd_soc_of_parse_card_name(&data->card, "model");
+	if (ret)
+		return ret;
+	data->card.num_links = 1;
+	data->card.dai_link = &data->dai;
+
+	ret = snd_soc_register_card(&data->card);
+	if (ret) {
+		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, data);
+	of_node_put(ssi_np);
+	of_node_put(codec_np);
+
+	return 0;
+}
+
+static int __devexit imx_sgtl5000_remove(struct platform_device *pdev)
+{
+	struct imx_sgtl5000_data *data = platform_get_drvdata(pdev);
+
+	snd_soc_unregister_card(&data->card);
+
+	return 0;
+}
+
+static const struct of_device_id imx_sgtl5000_dt_ids[] = {
+	{ .compatible = "fsl,imx-audio-sgtl5000", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_sgtl5000_dt_ids);
+
+static struct platform_driver imx_sgtl5000_driver = {
+	.driver = {
+		.name = "imx-sgtl5000",
+		.owner = THIS_MODULE,
+		.of_match_table = imx_sgtl5000_dt_ids,
+	},
+	.probe = imx_sgtl5000_probe,
+	.remove = __devexit_p(imx_sgtl5000_remove),
+};
+module_platform_driver(imx_sgtl5000_driver);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo at linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX SGTL5000 ASoC machine driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx-sgtl5000");
-- 
1.7.5.4



From arnd at arndb.de  Thu Mar  8 12:01:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 8 Mar 2012 17:01:01 +0000
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <20120308162530.GI5050@titan.lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203072113.04369.arnd@arndb.de>
 <20120308162530.GI5050@titan.lakedaemon.net>
Message-ID: <201203081701.01663.arnd@arndb.de>

On Thursday 08 March 2012, Jason wrote:
> 
> On Wed, Mar 07, 2012 at 09:13:04PM +0000, Arnd Bergmann wrote:
> > Finally, something could be wrong with the interrupt controller.
> > AFAICT, you register it through the device tree now, but it's also
> > getting initialized through kirkwood_init_irq, so the numbers
> > would all be wrong.
> 
> Yes, I'm working through this now.  mv_cesa silently fails to come up
> if it can't find the interrupt controller via fdt.  So, it needs to get
> done.
> 
> Right now, I'm looking at how mach-versatile does it (vic_init()) since
> it's also an ARM926ej-s...
> 

Ok, sounds good. It's not important whether it's an ARM9 or not btw.
You should look at both anything that defines an "interrupt-controller"
property as an example including Documentation/devicetree/bindings/arm/vic.txt
and Documentation/devicetree/bindings/arm/gic.txt.

(taking Thomas Gleixner on Cc)

Since the orion irq chip is based on irqchip_generic, it would be
perfect to have a generic irqchip binding to go along with
kernel/irq/generic-chip.c. Not sure if anyone has thought about this
before, but it looks like we can completely avoid using
arch/arm/plat-orion/irq.c and arch/arm/mach-kirkwood/irq.c if we
do that.

	Arnd


From plagnioj at jcrosoft.com  Thu Mar  8 11:51:53 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 8 Mar 2012 17:51:53 +0100
Subject: [PATCH 5/6] ARM: at91: add ram controller DT support
In-Reply-To: <4F58CF29.6020906@gmail.com>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <1330718048-9314-5-git-send-email-plagnioj@jcrosoft.com>
 <4F57BDCE.1050708@gmail.com>
 <20120308061324.GE27213@game.jcrosoft.org>
 <4F58BE4F.5080009@gmail.com>
 <20120308141000.GF27213@game.jcrosoft.org>
 <4F58CF29.6020906@gmail.com>
Message-ID: <20120308165153.GH27213@game.jcrosoft.org>

On 09:24 Thu 08 Mar     , Rob Herring wrote:
> On 03/08/2012 08:10 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 08:12 Thu 08 Mar     , Rob Herring wrote:
> >> On 03/08/2012 12:13 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>>>> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>>>> index a297a77..88e43d5 100644
> >>>>> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>>>> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
> >>>>> @@ -55,11 +55,6 @@
> >>>>>  #define AT91SAM9X5_BASE_USART2	0xf8024000
> >>>>>  
> >>>>>  /*
> >>>>> - * System Peripherals
> >>>>> - */
> >>>>> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
> >>>>> -
> >>>>> -/*
> >>>>>   * Base addresses for early serial code (uncompress.h)
> >>>>>   */
> >>>>>  #define AT91_DBGU	AT91_BASE_DBGU0
> >>>>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> >>>>> index 3e48b59..f86450d 100644
> >>>>> --- a/arch/arm/mach-at91/setup.c
> >>>>> +++ b/arch/arm/mach-at91/setup.c
> >>>>> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
> >>>>>  	of_node_put(np);
> >>>>>  }
> >>>>>  
> >>>>> +static struct of_device_id ramc_ids[] = {
> >>>>> +	{ .compatible = "atmel,at91sam9260-sdramc" },
> >>>>> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
> >>>>> +	{ /*sentinel*/ }
> >>>>> +};
> >>>>> +
> >>>>> +static void at91_dt_ramc(void)
> >>>>> +{
> >>>>> +	struct device_node *np;
> >>>>> +
> >>>>> +	np = of_find_matching_node(NULL, ramc_ids);
> >>>>> +	if (!np)
> >>>>> +		panic("unable to find compatible ram conroller node in dtb\n");
> >>>>
> >>>> You really can't boot if this fails? A WARN is better if it allows you
> >>>> to boot until at least your console is actually up.
> >>> if the restart is called you will have a oops so no it's a basic mandatory
> >>> device on at91
> >>>
> >>
> >> But you may never see the panic message because your console is not up.
> >> If you WARN and can continue to boot, then the user can see the problem
> >> and fix it. Otherwise you get nothing and have to go rebuild and turn on
> >> earlyprintk.
> > yeah agreed but if the restart id use before the console is enable you will
> > have the same issue. the ramc controller are basic device so people usally
> > don't touch it except you add a SoC support.
> > 
> > so I prefer to panic
> > 
> 
> Then panic in the restart code if it doesn't have something it needs.
The code is in assembly (mandatory) so difficult

The warn on other missing binding agreed but here please let go
It's basic device that except the maintainer will never touch

People will just include the dtsi and if you really need to debug soc init
enable earlyprintk is fine

Best Regards,
J.


From plagnioj at jcrosoft.com  Thu Mar  8 11:53:38 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 8 Mar 2012 17:53:38 +0100
Subject: [PATCH 1/5 v3] i2c/gpio: add DT support
In-Reply-To: <4F588F50.7060906@samsung.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <4F588F50.7060906@samsung.com>
Message-ID: <20120308165338.GI27213@game.jcrosoft.org>

On 11:52 Thu 08 Mar     , Karol Lewandowski wrote:
> On 08.03.2012 09:50, Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> > +static int __devinit of_i2c_gpio_probe(struct device_node *np,
> > +			     struct i2c_gpio_platform_data *pdata)
> > +{
> > +	u32 reg;
> > +
> > +	if (of_gpio_count(np) < 2)
> > +		return -ENODEV;
> > +
> > +	pdata->sda_pin = of_get_gpio(np, 0);
> > +	pdata->scl_pin = of_get_gpio(np, 1);
> > +
> > +	if (pdata->sda_pin < 0 || pdata->scl_pin < 0) {
> > +		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
> > +		       np->full_name, pdata->sda_pin, pdata->scl_pin);
> > +		return -ENODEV;
> > +	}
> > +
> > +	of_property_read_u32(np, "i2c-gpio,delay-us", &pdata->udelay);
> > +
> 
> 
> 
> > +	if (of_property_read_u32(np, "i2c-gpio,timeout-ms", &reg))
> > +		pdata->timeout = msecs_to_jiffies(reg);
> 
> 
> I've already said (two times!) that of_property_read_u32() returns
> nonzero (negative) error code on _error_.
> 
> Don't you see obvious error in above code fragment?
> 
> You assign to pdata->timeout on _error_.
yeah forget this one

Jean can I have you are ack so I send the v4 and the pull today

Best Regards,
J.


From paul at pwsan.com  Thu Mar  8 12:05:58 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 8 Mar 2012 10:05:58 -0700 (MST)
Subject: [PATCH 00/15] ARM: OMAP4: hwmod data: add almost all remaining
 IP blocks
In-Reply-To: <4F5898A7.5040005@ti.com>
References: <20120308104918.14753.69281.stgit@dusk> <4F5898A7.5040005@ti.com>
Message-ID: <alpine.DEB.2.00.1203081003100.27901@utopia.booyaka.com>

Hi Rajendra,

On Thu, 8 Mar 2012, Rajendra Nayak wrote:

> On Thursday 08 March 2012 04:21 PM, Paul Walmsley wrote:
>
> > These patches are also available via git from git://git.pwsan.com/linux-2.6
> > in the branch "hwmod_enable_remaining_hwmods_devel_3.4".
> 
> Could not find this branch on your tree. Found a
> 'enable_remaining_omap4_hwmods' instead, but that seems to
> be an old branch.

Sorry about that.  It should be pushed now.


- Paul


From robherring2 at gmail.com  Thu Mar  8 12:08:11 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 08 Mar 2012 11:08:11 -0600
Subject: [PATCH 2/5 v3] ARM: at91: sam9g20 add i2c DT support
In-Reply-To: <1331196635-27203-2-git-send-email-plagnioj@jcrosoft.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <1331196635-27203-2-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <4F58E77B.4010500@gmail.com>

On 03/08/2012 02:50 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> For now on use i2c-gpio driver on the same pin as the hardware IP.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: devicetree-discuss at lists.ozlabs.org
> ---
> v3:
> 
> 	update i2c binding (Rob comments)
> 
> Best Regards,
> J.
>  arch/arm/boot/dts/at91sam9g20.dtsi |   13 +++++++++++++
>  1 files changed, 13 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
> index 4b0dc99..072b2da 100644
> --- a/arch/arm/boot/dts/at91sam9g20.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
> @@ -189,4 +189,17 @@
>  			status = "disabled";
>  		};
>  	};
> +
> +	i2c-gpio at 0 {

You updated the example, but not all the actual uses to i2c at 0.

Rob

> +		compatible = "i2c-gpio";
> +		gpios = <&pioA 23 0 /* sda */
> +			 &pioA 24 0 /* scl */
> +			>;
> +		i2c-gpio,sda-open-drain;
> +		i2c-gpio,scl-open-drain;
> +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
>  };



From robherring2 at gmail.com  Thu Mar  8 12:12:29 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 08 Mar 2012 11:12:29 -0600
Subject: [PATCH 5/5 v3] ARM: at91: sam9x5 add i2c DT support
In-Reply-To: <1331196635-27203-5-git-send-email-plagnioj@jcrosoft.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <1331196635-27203-5-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <4F58E87D.9040701@gmail.com>

On 03/08/2012 02:50 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> For now on use i2c-gpio driver on the same pin as the hardware IP.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: devicetree-discuss at lists.ozlabs.org
> ---
> v3:
> 
> 	update i2c binding (Rob comments)
> 
> Best Regards,
> J.
>  arch/arm/boot/dts/at91sam9x5.dtsi |   39 +++++++++++++++++++++++++++++++++++++
>  1 files changed, 39 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> index c294657..fdd1ac6 100644
> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> @@ -188,4 +188,43 @@
>  			status = "disabled";
>  		};
>  	};
> +
> +	i2c-gpio at 0 {
> +		compatible = "i2c-gpio";
> +		gpios = <&pioA 30 0 /* sda */
> +			 &pioA 31 0 /* scl */
> +			>;
> +		i2c-gpio,sda-open-drain;
> +		i2c-gpio,scl-open-drain;
> +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	i2c-gpio at 1 {
> +		compatible = "i2c-gpio";
> +		gpios = <&pioC 0 0 /* sda */
> +			 &pioC 1 0 /* scl */
> +			>;
> +		i2c-gpio,sda-open-drain;
> +		i2c-gpio,scl-open-drain;
> +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	i2c-gpio at 2 {
> +		compatible = "i2c-gpio";
> +		gpios = <&pioB 4 0 /* sda */
> +			 &pioB 5 0 /* scl */
> +			>;
> +		i2c-gpio,sda-open-drain;
> +		i2c-gpio,scl-open-drain;
> +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};

If these are just any random gpio lines, it seems strange to define
these in a SOC dtsi and then disable them.

Rob


>  };



From robherring2 at gmail.com  Thu Mar  8 12:13:45 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 08 Mar 2012 11:13:45 -0600
Subject: [PATCH 5/6] ARM: at91: add ram controller DT support
In-Reply-To: <20120308165153.GH27213@game.jcrosoft.org>
References: <20120302192844.GB21255@game.jcrosoft.org>
 <1330718048-9314-5-git-send-email-plagnioj@jcrosoft.com>
 <4F57BDCE.1050708@gmail.com> <20120308061324.GE27213@game.jcrosoft.org>
 <4F58BE4F.5080009@gmail.com> <20120308141000.GF27213@game.jcrosoft.org>
 <4F58CF29.6020906@gmail.com> <20120308165153.GH27213@game.jcrosoft.org>
Message-ID: <4F58E8C9.6010608@gmail.com>

On 03/08/2012 10:51 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 09:24 Thu 08 Mar     , Rob Herring wrote:
>> On 03/08/2012 08:10 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> On 08:12 Thu 08 Mar     , Rob Herring wrote:
>>>> On 03/08/2012 12:13 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>>>>> diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>>>> index a297a77..88e43d5 100644
>>>>>>> --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>>>> +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
>>>>>>> @@ -55,11 +55,6 @@
>>>>>>>  #define AT91SAM9X5_BASE_USART2	0xf8024000
>>>>>>>  
>>>>>>>  /*
>>>>>>> - * System Peripherals
>>>>>>> - */
>>>>>>> -#define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
>>>>>>> -
>>>>>>> -/*
>>>>>>>   * Base addresses for early serial code (uncompress.h)
>>>>>>>   */
>>>>>>>  #define AT91_DBGU	AT91_BASE_DBGU0
>>>>>>> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
>>>>>>> index 3e48b59..f86450d 100644
>>>>>>> --- a/arch/arm/mach-at91/setup.c
>>>>>>> +++ b/arch/arm/mach-at91/setup.c
>>>>>>> @@ -315,12 +315,33 @@ static void at91_dt_rstc(void)
>>>>>>>  	of_node_put(np);
>>>>>>>  }
>>>>>>>  
>>>>>>> +static struct of_device_id ramc_ids[] = {
>>>>>>> +	{ .compatible = "atmel,at91sam9260-sdramc" },
>>>>>>> +	{ .compatible = "atmel,at91sam9g45-ddramc" },
>>>>>>> +	{ /*sentinel*/ }
>>>>>>> +};
>>>>>>> +
>>>>>>> +static void at91_dt_ramc(void)
>>>>>>> +{
>>>>>>> +	struct device_node *np;
>>>>>>> +
>>>>>>> +	np = of_find_matching_node(NULL, ramc_ids);
>>>>>>> +	if (!np)
>>>>>>> +		panic("unable to find compatible ram conroller node in dtb\n");
>>>>>>
>>>>>> You really can't boot if this fails? A WARN is better if it allows you
>>>>>> to boot until at least your console is actually up.
>>>>> if the restart is called you will have a oops so no it's a basic mandatory
>>>>> device on at91
>>>>>
>>>>
>>>> But you may never see the panic message because your console is not up.
>>>> If you WARN and can continue to boot, then the user can see the problem
>>>> and fix it. Otherwise you get nothing and have to go rebuild and turn on
>>>> earlyprintk.
>>> yeah agreed but if the restart id use before the console is enable you will
>>> have the same issue. the ramc controller are basic device so people usally
>>> don't touch it except you add a SoC support.
>>>
>>> so I prefer to panic
>>>
>>
>> Then panic in the restart code if it doesn't have something it needs.
> The code is in assembly (mandatory) so difficult
> 
> The warn on other missing binding agreed but here please let go
> It's basic device that except the maintainer will never touch
> 
> People will just include the dtsi and if you really need to debug soc init
> enable earlyprintk is fine

Okay.

Acked-by: Rob Herring <rob.herring at calxeda.com>


From olof at lixom.net  Thu Mar  8 12:15:08 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 8 Mar 2012 09:15:08 -0800
Subject: [GIT PULL v4] ARM: kirkwood: fdt conversion progress
In-Reply-To: <201203081610.21493.arnd@arndb.de>
References: <20120307221012.GH5050@titan.lakedaemon.net>
 <201203081610.21493.arnd@arndb.de>
Message-ID: <CAOesGMh2etdQSOjktDGcWGfnsMhyFnVuebWRQeYuR6fvm1_DSA@mail.gmail.com>

Hi,

On Thu, Mar 8, 2012 at 8:10 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 07 March 2012, Jason Cooper wrote:
>> The following changes since commit d65b4e98d7ea3038b767b70fe8be959b2913f16d:
>>
>> ? Linux 3.3-rc3 (2012-02-08 19:21:53 -0800)
>>
>> are available in the git repository at:
>> ? git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt
>>
>> ---
>> Arnd,
>>
>> My first two should match up with what you have already, the only
>> outlier is that Jean-Christophe's patch is needed, but I don't think
>> everyone agrees on it yet.
>>
>
> Right now, Olof is handling the pull requests. I would suggest that he
> can use your branch to replace the current staging branch but still keep
> it in staging until everyone agrees or you replace it with a better version.

Jason,

Looking at the new pull request I see some differences in device
support. For example, the DT conversion of orion-spi and wdt is not in
the new branch.

Is that intentional? If not I'll hold off replacing your branch.


-Olof


From robherring2 at gmail.com  Thu Mar  8 12:16:04 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 08 Mar 2012 11:16:04 -0600
Subject: [PATCH 1/5 v3] i2c/gpio: add DT support
In-Reply-To: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <4F58E954.4010205@gmail.com>

On 03/08/2012 02:50 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-i2c at vger.kernel.org
> Cc: devicetree-discuss at lists.ozlabs.org
> ---
> v3:
> 
> 	update i2c binding (Rob comments)
> 
> 	Jean can I have a ack to apply it?
> 
> Best Regards,
> J.

For this patch:

Acked-by: Rob Herring <rob.herring at calxeda.com>


>  .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 +++++++
>  drivers/i2c/busses/i2c-gpio.c                      |   94 +++++++++++++++----
>  2 files changed, 106 insertions(+), 20 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> new file mode 100644
> index 0000000..4f8ec94
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> @@ -0,0 +1,32 @@
> +Device-Tree bindings for i2c gpio driver
> +
> +Required properties:
> +	- compatible = "i2c-gpio";
> +	- gpios: sda and scl gpio
> +
> +
> +Optional properties:
> +	- i2c-gpio,sda-open-drain: sda as open drain
> +	- i2c-gpio,scl-open-drain: scl as open drain
> +	- i2c-gpio,scl-output-only: scl as output only
> +	- i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform)
> +	- i2c-gpio,timeout-ms: timeout to get data
> +
> +Example nodes:
> +
> +i2c at 0 {
> +	compatible = "i2c-gpio";
> +	gpios = <&pioA 23 0 /* sda */
> +		 &pioA 24 0 /* scl */
> +		>;
> +	i2c-gpio,sda-open-drain;
> +	i2c-gpio,scl-open-drain;
> +	i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	rv3029c2 at 56 {
> +		compatible = "rv3029c2";
> +		reg = <0x56>;
> +	};
> +};
> diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
> index a651779..98ae85b 100644
> --- a/drivers/i2c/busses/i2c-gpio.c
> +++ b/drivers/i2c/busses/i2c-gpio.c
> @@ -14,8 +14,15 @@
>  #include <linux/module.h>
>  #include <linux/slab.h>
>  #include <linux/platform_device.h>
> +#include <linux/gpio.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_i2c.h>
>  
> -#include <asm/gpio.h>
> +struct i2c_gpio_private_data {
> +	struct i2c_adapter adap;
> +	struct i2c_algo_bit_data bit_data;
> +	struct i2c_gpio_platform_data pdata;
> +};
>  
>  /* Toggle SDA by changing the direction of the pin */
>  static void i2c_gpio_setsda_dir(void *data, int state)
> @@ -78,24 +85,62 @@ static int i2c_gpio_getscl(void *data)
>  	return gpio_get_value(pdata->scl_pin);
>  }
>  
> +static int __devinit of_i2c_gpio_probe(struct device_node *np,
> +			     struct i2c_gpio_platform_data *pdata)
> +{
> +	u32 reg;
> +
> +	if (of_gpio_count(np) < 2)
> +		return -ENODEV;
> +
> +	pdata->sda_pin = of_get_gpio(np, 0);
> +	pdata->scl_pin = of_get_gpio(np, 1);
> +
> +	if (pdata->sda_pin < 0 || pdata->scl_pin < 0) {
> +		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
> +		       np->full_name, pdata->sda_pin, pdata->scl_pin);
> +		return -ENODEV;
> +	}
> +
> +	of_property_read_u32(np, "i2c-gpio,delay-us", &pdata->udelay);
> +
> +	if (of_property_read_u32(np, "i2c-gpio,timeout-ms", &reg))
> +		pdata->timeout = msecs_to_jiffies(reg);
> +
> +	pdata->sda_is_open_drain =
> +		!!of_property_read_bool(np, "i2c-gpio,sda-open-drain");
> +	pdata->scl_is_open_drain =
> +		!!of_property_read_bool(np, "i2c-gpio,scl-open-drain");
> +	pdata->scl_is_output_only =
> +		!!of_property_read_bool(np, "i2c-gpio,scl-output-only");
> +
> +	return 0;
> +}
> +
>  static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  {
> +	struct i2c_gpio_private_data *priv;
>  	struct i2c_gpio_platform_data *pdata;
>  	struct i2c_algo_bit_data *bit_data;
>  	struct i2c_adapter *adap;
>  	int ret;
>  
> -	pdata = pdev->dev.platform_data;
> -	if (!pdata)
> -		return -ENXIO;
> +	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +	adap = &priv->adap;
> +	bit_data = &priv->bit_data;
> +	pdata = &priv->pdata;
>  
> -	ret = -ENOMEM;
> -	adap = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
> -	if (!adap)
> -		goto err_alloc_adap;
> -	bit_data = kzalloc(sizeof(struct i2c_algo_bit_data), GFP_KERNEL);
> -	if (!bit_data)
> -		goto err_alloc_bit_data;
> +	if (pdev->dev.of_node) {
> +		ret = of_i2c_gpio_probe(pdev->dev.of_node, pdata);
> +		if (ret)
> +			return ret;
> +	} else {
> +		if (!pdev->dev.platform_data)
> +			return -ENXIO;
> +		memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
> +	}
>  
>  	ret = gpio_request(pdata->sda_pin, "sda");
>  	if (ret)
> @@ -143,6 +188,7 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  	adap->algo_data = bit_data;
>  	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
>  	adap->dev.parent = &pdev->dev;
> +	adap->dev.of_node = pdev->dev.of_node;
>  
>  	/*
>  	 * If "dev->id" is negative we consider it as zero.
> @@ -154,7 +200,9 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto err_add_bus;
>  
> -	platform_set_drvdata(pdev, adap);
> +	of_i2c_register_devices(adap);
> +
> +	platform_set_drvdata(pdev, priv);
>  
>  	dev_info(&pdev->dev, "using pins %u (SDA) and %u (SCL%s)\n",
>  		 pdata->sda_pin, pdata->scl_pin,
> @@ -168,34 +216,40 @@ err_add_bus:
>  err_request_scl:
>  	gpio_free(pdata->sda_pin);
>  err_request_sda:
> -	kfree(bit_data);
> -err_alloc_bit_data:
> -	kfree(adap);
> -err_alloc_adap:
>  	return ret;
>  }
>  
>  static int __devexit i2c_gpio_remove(struct platform_device *pdev)
>  {
> +	struct i2c_gpio_private_data *priv;
>  	struct i2c_gpio_platform_data *pdata;
>  	struct i2c_adapter *adap;
>  
> -	adap = platform_get_drvdata(pdev);
> -	pdata = pdev->dev.platform_data;
> +	priv = platform_get_drvdata(pdev);
> +	adap = &priv->adap;
> +	pdata = &priv->pdata;
>  
>  	i2c_del_adapter(adap);
>  	gpio_free(pdata->scl_pin);
>  	gpio_free(pdata->sda_pin);
> -	kfree(adap->algo_data);
> -	kfree(adap);
>  
>  	return 0;
>  }
>  
> +#if defined(CONFIG_OF)
> +static const struct of_device_id i2c_gpio_dt_ids[] = {
> +	{ .compatible = "i2c-gpio", },
> +	{ /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, i2c_gpio_dt_ids);
> +#endif
> +
>  static struct platform_driver i2c_gpio_driver = {
>  	.driver		= {
>  		.name	= "i2c-gpio",
>  		.owner	= THIS_MODULE,
> +		.of_match_table	= of_match_ptr(i2c_gpio_dt_ids),
>  	},
>  	.probe		= i2c_gpio_probe,
>  	.remove		= __devexit_p(i2c_gpio_remove),



From nicolas.pitre at linaro.org  Thu Mar  8 12:21:17 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 8 Mar 2012 12:21:17 -0500 (EST)
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <4F5882BF.1030104@arm.com>
References: <alpine.DEB.2.00.1202231714590.23091@kaball-desktop>
 <1330019314-20865-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <alpine.LFD.2.02.1203021528150.31242@xanadu.home> <4F5882BF.1030104@arm.com>
Message-ID: <alpine.LFD.2.02.1203081041340.24151@xanadu.home>

On Thu, 8 Mar 2012, Richard Earnshaw wrote:

> On 02/03/12 21:15, Nicolas Pitre wrote:
> > So, to me, the gcc documentation is perfectly clear on this topic.
> > there really _is_ a guarantee that those asm marked variables will be in
> > the expected registers on entry to the inline asm, given that the
> > variable is _also_ listed as an operand to the asm statement.  But only
> > in that case.
> >
> > It is true that gcc may reorder other function calls or other code
> > around the inline asm and then intervening code can clobber any
> > registers.  Then it is up to gcc to preserve the variable's content
> > elsewhere when its register is used for other purposes, and restore it
> > when some inline asm statement is referring to it.
> >
> > And if gcc does not do this then it is buggy.  Version 3.4.0 of gcc was
> > buggy.  No other gcc versions in the last 7 years had such a problem or
> > the __asmeq macro in the kernel would have told us.
> >
> >> Or, to summarise another way, there is no way to control which register
> >> is used to pass something to an inline asm in general (often we get away
> >> with this, and there are a lot of inline asms in the kernel that assume
> >> it works, but the more you inline the more likely you are to get nasty
> >> surprises).
> >
> > This statement is therefore unfounded and wrong.  Please direct the
> > tools guy who mislead you to the above gcc documentation.
> >
> 
> The problem is not really about re-ordering functions but about implicit
> functions that come from the source code; for example
> 
> int foo (int a, int b)
> {
>   register int x __asm__("r0") = 33;
> 
>   register int c __asm__("r1") = a / b; /* Ooops, clobbers r0 with
> division function call.  */
> 
>   asm ("svc 0" : : "r" (x));
> }
> 
> There's nothing in the specification to say what happens if there's a
> statement in the code that causes an implicit clobber of your assembly
> register.

I'm sure gcc is full of implicit behaviors that are not mentioned in 
the specification.  But as long as the specification is respected, then 
there is no need to mention any unobservable side effects from a program 
flow point of view, right?

Why wouldn't gcc be able to respect the documented feature by 
preventing live variable from being clobbered and reloading them in 
the specified register at the inline asm entry point, just like it does 
for function calls?

Here's an example code that shows that, unfortunately, gcc is still 
broken with regards to the documented behavior:

extern int bar(int);
int foo(int y)
{
        register int x __asm__("r1") = 33;
        y += bar(x);
        asm ("@ x should be live in %0 here" : "+r" (x) : "r" (y));
        y += bar(x);
        asm ("@ x should be live in %0 here" : "+r" (x) : "r" (y));
        return x;
}

Result is:

foo:
        stmfd   sp!, {r4, lr}
        mov     r4, r0
        mov     r0, #33
        bl      bar
        add     r4, r0, r4
        @ x should be live in r1 here
        mov     r0, r1
        bl      bar
        add     r0, r0, r4
        @ x should be live in r1 here
        mov     r0, r1
        ldmfd   sp!, {r4, lr}
        bx      lr

To me this is clearly a bug if gcc is not able to meet the documented 
expectation.  And the documented expectation is not at all unreasonable.


Nicolas


From olof at lixom.net  Thu Mar  8 12:22:48 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 8 Mar 2012 09:22:48 -0800
Subject: [GIT PULL] i.MX 35/5 AIPS Setup
In-Reply-To: <20120307205429.GO3852@pengutronix.de>
References: <20120307205429.GO3852@pengutronix.de>
Message-ID: <CAOesGMjfGuof2Ss9x98PjH9Hgu0w9eNCZNRYjjNPT___r-tOQw@mail.gmail.com>

Hi,

On Wed, Mar 7, 2012 at 12:54 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>
> Hi Arnd,
>
> Please pull the following for -next. It contains Fabios Aips setup
> patches. They depend on your imx/soc branch.
>
> Sascha
>
> The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
>
> ?Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)
>
> are available in the git repository at:
>
> ?git://git.pengutronix.de/git/imx/linux-2.6.git tags/imx35-imx5-aips-setup

Thanks, pulled into next/soc.

-Olof


From bhelgaas at google.com  Thu Mar  8 12:27:07 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Thu, 8 Mar 2012 10:27:07 -0700
Subject: [PATCH 06/11] PCI: Keep pci_fixup_irqs() around after init
In-Reply-To: <1331218291-16119-7-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-7-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <CAErSpo6hbWjteESST1+O2WzbtmZq6hC-pnUB4o3MAXWG-EgU+g@mail.gmail.com>

On Thu, Mar 8, 2012 at 7:51 AM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> ---
> ?drivers/pci/setup-irq.c | ? ?4 ++--
> ?1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c
> index eb219a1..270ae7b 100644
> --- a/drivers/pci/setup-irq.c
> +++ b/drivers/pci/setup-irq.c
> @@ -18,7 +18,7 @@
> ?#include <linux/cache.h>
>
>
> -static void __init
> +static void
> ?pdev_fixup_irq(struct pci_dev *dev,
> ? ? ? ? ? ? ? u8 (*swizzle)(struct pci_dev *, u8 *),
> ? ? ? ? ? ? ? int (*map_irq)(const struct pci_dev *, u8, u8))
> @@ -54,7 +54,7 @@ pdev_fixup_irq(struct pci_dev *dev,
> ? ? ? ?pcibios_update_irq(dev, irq);
> ?}
>
> -void __init
> +void
> ?pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
> ? ? ? ? ? ? ? int (*map_irq)(const struct pci_dev *, u8, u8))
> ?{


        struct pci_dev *dev = NULL;
        for_each_pci_dev(dev)
                pdev_fixup_irq(dev, swizzle, map_irq);
}

Hmm, your patch looks OK as far as it goes, but the implementation of
pci_fixup_irqs() as a call-once-at-boot-time thing with a loop through
all the PCI devices we've found so far looks completely broken with
regard to hotplug.

Who does the swizzle for devices hot-added after boot?

Bjorn


From jason at lakedaemon.net  Thu Mar  8 12:30:29 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 8 Mar 2012 12:30:29 -0500
Subject: [GIT PULL v4] ARM: kirkwood: fdt conversion progress
In-Reply-To: <CAOesGMh2etdQSOjktDGcWGfnsMhyFnVuebWRQeYuR6fvm1_DSA@mail.gmail.com>
References: <20120307221012.GH5050@titan.lakedaemon.net>
 <201203081610.21493.arnd@arndb.de>
 <CAOesGMh2etdQSOjktDGcWGfnsMhyFnVuebWRQeYuR6fvm1_DSA@mail.gmail.com>
Message-ID: <20120308173029.GK5050@titan.lakedaemon.net>

On Thu, Mar 08, 2012 at 09:15:08AM -0800, Olof Johansson wrote:
> Hi,
> 
> On Thu, Mar 8, 2012 at 8:10 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Wednesday 07 March 2012, Jason Cooper wrote:
> >> The following changes since commit d65b4e98d7ea3038b767b70fe8be959b2913f16d:
> >>
> >> ? Linux 3.3-rc3 (2012-02-08 19:21:53 -0800)
> >>
> >> are available in the git repository at:
> >> ? git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt
> >>
> >> ---
> >> Arnd,
> >>
> >> My first two should match up with what you have already, the only
> >> outlier is that Jean-Christophe's patch is needed, but I don't think
> >> everyone agrees on it yet.
> >>
> >
> > Right now, Olof is handling the pull requests. I would suggest that he
> > can use your branch to replace the current staging branch but still keep
> > it in staging until everyone agrees or you replace it with a better version.
> 
> Jason,
> 
> Looking at the new pull request I see some differences in device
> support. For example, the DT conversion of orion-spi and wdt is not in
> the new branch.
> 
> Is that intentional? If not I'll hold off replacing your branch.

Yes, Andrew Lunn is working on adding common clock support to
plat-orion, which mach-kirkwood depends on.  So, I'm holding off on
changes to drivers which get passed tclk.  Once Andrew's clock code is
up, then I'll add fdt support to it and re-introduce those driver
changes.

clock gating is a separate issue that is further down the road.

Basically, we're trying to avoid merge conflicts.  :-)

The following patches should be fine to merge into stable (for 3.4):

af42511 ARM: orion: spi: remove enable_clock_fix which is not used
d93b2ca ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data.
2bb9207 ARM: kirkwood: fdt: use mrvl ticker symbol
ec0ec68 ARM: kirkwood: fdt: absorb kirkwood_init()
...
b5c25c3 ARM: kirkwood: rtc-mv devicetree bindings
5e40593 ARM: kirkwood: use devicetree for rtc-mv
...

I'm still working on the interrupt controller and dma.  orion-ehci,
mv_cesa and sata_mv depend on one or both of those to work.

thx,

Jason.


From olof at lixom.net  Thu Mar  8 12:38:12 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 8 Mar 2012 09:38:12 -0800
Subject: [GIT PULL][for v3.4]pull request from arch-pxa tree with rtc
 branch
In-Reply-To: <CAN1soZxSpnDJCiz-5_PiHcb+zoR+X0b2VLyANLY0om0MDo+YYg@mail.gmail.com>
References: <CAN1soZxSpnDJCiz-5_PiHcb+zoR+X0b2VLyANLY0om0MDo+YYg@mail.gmail.com>
Message-ID: <CAOesGMhuK5k-wshFGeu2jn83+Ck8q0OCZPKSndQ4-FKzmhEv7Q@mail.gmail.com>

On Mon, Mar 5, 2012 at 11:06 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> Hi Arnd,
>
> Please help to pull this patch from arch-pxa git with rtc branch. I
> have to put it into rtc branch since I met patch conflict on v3.3-rc6.
> It seems that putting it into rtc branch with previous rtc patches is
> a better choice.
>
> Best Regards
> Haojian
>
> The following changes since commit 4128e27584f58bce9f56a9a0346650c94a651332:
>
> ?ARM: mmp: enable rtc in pxa910 (2012-02-28 11:23:09 +0800)
>
> are available in the git repository at:
> ?git://github.com/hzhuang1/linux.git rtc

Pulled, thanks.


-Olof


From olof at lixom.net  Thu Mar  8 12:38:17 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 8 Mar 2012 09:38:17 -0800
Subject: [GIT PULL][v3.4] pull request on pxa tree for DT branch
In-Reply-To: <CAN1soZzd_6BS=qXKzm8-a+Z=rqC1shJYcoHNwedcHUVhsMo4Ww@mail.gmail.com>
References: <CAN1soZyA8iYJjcWRQoPEP=ksCwVfP6JYqcAdVh_qYjg2oc5XqQ@mail.gmail.com>
 <CAN1soZzd_6BS=qXKzm8-a+Z=rqC1shJYcoHNwedcHUVhsMo4Ww@mail.gmail.com>
Message-ID: <CAOesGMhVpw0uhL5oejf=2XpAmp5+pBSYeaenZvhS0U9vxinOkQ@mail.gmail.com>

Hi,

On Tue, Mar 6, 2012 at 5:45 PM, Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
> Hi Arnd,
>
> I update the branch according the comments on serial-pxa driver.
> Please help to merge these patches.
>
> Thanks
> Haojian
>
> The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
>
> ?Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)
>
> are available in the git repository at:
> ?git://github.com/hzhuang1/linux.git dt

Pulled, thanks.

-Olof


From olof at lixom.net  Thu Mar  8 12:38:22 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 8 Mar 2012 09:38:22 -0800
Subject: [GIT PULL v2][for v3.4] request pull from arch-pxa on regulator
 branch
In-Reply-To: <CAN1soZzw+hAACoscyJ0q65t84ighZ1zPG92uKnwT-pDgcF2b6Q@mail.gmail.com>
References: <CAN1soZzw+hAACoscyJ0q65t84ighZ1zPG92uKnwT-pDgcF2b6Q@mail.gmail.com>
Message-ID: <CAOesGMgSR8xJN=OGCdMcyvkaZ8yOzQW+hgAGh_Esf2+DhOMCjw@mail.gmail.com>

Hi,

On Tue, Mar 6, 2012 at 5:54 PM, Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
> Hi Arnd,
>
> Please help to merge these patches from arch-pxa. They're used to
> convert bq24022
> to gpio-regulator. Now Mark acked these patches.
>
> Best Regards
> Haojian
>
> The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
>
> ?Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)
>
> are available in the git repository at:
> ?git://github.com/hzhuang1/linux.git regulator

Pulled, thanks.


-Olof


From olof at lixom.net  Thu Mar  8 12:53:06 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 8 Mar 2012 09:53:06 -0800
Subject: [GIT PULL v4] ARM: kirkwood: fdt conversion progress
In-Reply-To: <20120308173029.GK5050@titan.lakedaemon.net>
References: <20120307221012.GH5050@titan.lakedaemon.net>
 <201203081610.21493.arnd@arndb.de>
 <CAOesGMh2etdQSOjktDGcWGfnsMhyFnVuebWRQeYuR6fvm1_DSA@mail.gmail.com>
 <20120308173029.GK5050@titan.lakedaemon.net>
Message-ID: <CAOesGMikpxMd+MtnjKix7D0KiHD+e8s2YFjB3j9a=7i7S9J+0g@mail.gmail.com>

Hi,

On Thu, Mar 8, 2012 at 9:30 AM, Jason <jason at lakedaemon.net> wrote:
> On Thu, Mar 08, 2012 at 09:15:08AM -0800, Olof Johansson wrote:
>> Hi,
>>
>> On Thu, Mar 8, 2012 at 8:10 AM, Arnd Bergmann <arnd at arndb.de> wrote:
>> > On Wednesday 07 March 2012, Jason Cooper wrote:
>> >> The following changes since commit d65b4e98d7ea3038b767b70fe8be959b2913f16d:
>> >>
>> >> ? Linux 3.3-rc3 (2012-02-08 19:21:53 -0800)
>> >>
>> >> are available in the git repository at:
>> >> ? git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt
>> >>
>> >> ---
>> >> Arnd,
>> >>
>> >> My first two should match up with what you have already, the only
>> >> outlier is that Jean-Christophe's patch is needed, but I don't think
>> >> everyone agrees on it yet.
>> >>
>> >
>> > Right now, Olof is handling the pull requests. I would suggest that he
>> > can use your branch to replace the current staging branch but still keep
>> > it in staging until everyone agrees or you replace it with a better version.
>>
>> Jason,
>>
>> Looking at the new pull request I see some differences in device
>> support. For example, the DT conversion of orion-spi and wdt is not in
>> the new branch.
>>
>> Is that intentional? If not I'll hold off replacing your branch.
>
> Yes, Andrew Lunn is working on adding common clock support to
> plat-orion, which mach-kirkwood depends on. ?So, I'm holding off on
> changes to drivers which get passed tclk. ?Once Andrew's clock code is
> up, then I'll add fdt support to it and re-introduce those driver
> changes.
>
> clock gating is a separate issue that is further down the road.
>
> Basically, we're trying to avoid merge conflicts. ?:-)

Ok, great. I'll replace the branch then.

> The following patches should be fine to merge into stable (for 3.4):
>
> af42511 ARM: orion: spi: remove enable_clock_fix which is not used
> d93b2ca ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data.
> 2bb9207 ARM: kirkwood: fdt: use mrvl ticker symbol
> ec0ec68 ARM: kirkwood: fdt: absorb kirkwood_init()
> ...
> b5c25c3 ARM: kirkwood: rtc-mv devicetree bindings
> 5e40593 ARM: kirkwood: use devicetree for rtc-mv
> ...

Excellent. Can you build up one or more stable branches that I can
pull those from?

> I'm still working on the interrupt controller and dma. ?orion-ehci,
> mv_cesa and sata_mv depend on one or both of those to work.

Cool.


-Olof


From plagnioj at jcrosoft.com  Thu Mar  8 12:52:04 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 8 Mar 2012 18:52:04 +0100
Subject: [PATCH 5/5 v3] ARM: at91: sam9x5 add i2c DT support
In-Reply-To: <4F58E87D.9040701@gmail.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <1331196635-27203-5-git-send-email-plagnioj@jcrosoft.com>
 <4F58E87D.9040701@gmail.com>
Message-ID: <20120308175204.GJ27213@game.jcrosoft.org>

On 11:12 Thu 08 Mar     , Rob Herring wrote:
> On 03/08/2012 02:50 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > For now on use i2c-gpio driver on the same pin as the hardware IP.
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> > Cc: devicetree-discuss at lists.ozlabs.org
> > ---
> > v3:
> > 
> > 	update i2c binding (Rob comments)
> > 
> > Best Regards,
> > J.
> >  arch/arm/boot/dts/at91sam9x5.dtsi |   39 +++++++++++++++++++++++++++++++++++++
> >  1 files changed, 39 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> > index c294657..fdd1ac6 100644
> > --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> > +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> > @@ -188,4 +188,43 @@
> >  			status = "disabled";
> >  		};
> >  	};
> > +
> > +	i2c-gpio at 0 {
> > +		compatible = "i2c-gpio";
> > +		gpios = <&pioA 30 0 /* sda */
> > +			 &pioA 31 0 /* scl */
> > +			>;
> > +		i2c-gpio,sda-open-drain;
> > +		i2c-gpio,scl-open-drain;
> > +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		status = "disabled";
> > +	};
> > +
> > +	i2c-gpio at 1 {
> > +		compatible = "i2c-gpio";
> > +		gpios = <&pioC 0 0 /* sda */
> > +			 &pioC 1 0 /* scl */
> > +			>;
> > +		i2c-gpio,sda-open-drain;
> > +		i2c-gpio,scl-open-drain;
> > +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		status = "disabled";
> > +	};
> > +
> > +	i2c-gpio at 2 {
> > +		compatible = "i2c-gpio";
> > +		gpios = <&pioB 4 0 /* sda */
> > +			 &pioB 5 0 /* scl */
> > +			>;
> > +		i2c-gpio,sda-open-drain;
> > +		i2c-gpio,scl-open-drain;
> > +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		status = "disabled";
> > +	};
> 
> If these are just any random gpio lines, it seems strange to define
> these in a SOC dtsi and then disable them.
they are not, they are the same pin as the i2c hardware IP.

Today the hw driver is not ready or will not work correctly (IP issue)

On hardware design we use the I2C pin but can not use the hw driver

Best Regards,
J.


From tony at atomide.com  Thu Mar  8 13:04:41 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 10:04:41 -0800
Subject: [GIT PULL] few more fixes for v3.3-rc6
Message-ID: <20120308180441.GT12083@atomide.com>

Hi Arnd & Olof,

Here are few more fixes for the current -rc cycle if there's
still enough time to get them in.

Regards,

Tony


The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
  Linus Torvalds (1):
        Linux 3.3-rc6

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fixes

Cousson, Benoit (1):
      ARM: OMAP: irqs: Fix NR_IRQS value to handle PRCM interrupts

R Sricharan (1):
      ARM: OMAP2+: Fix module build errors with CONFIG_OMAP4_ERRATA_I688

Rajendra Nayak (1):
      ARM: OMAP2+: Remove apply_uV constraints for fixed regulator

Vaibhav Hiremath (1):
      ARM: OMAP: id: Add missing break statement in omap3xxx_check_revision

 arch/arm/mach-omap2/id.c               |    1 +
 arch/arm/mach-omap2/omap4-common.c     |    2 ++
 arch/arm/mach-omap2/twl-common.c       |    1 -
 arch/arm/plat-omap/include/plat/irqs.h |   10 +++++++++-
 4 files changed, 12 insertions(+), 2 deletions(-)


From jason at lakedaemon.net  Thu Mar  8 13:07:12 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 8 Mar 2012 13:07:12 -0500
Subject: [GIT PULL v4] ARM: kirkwood: fdt conversion progress
In-Reply-To: <CAOesGMikpxMd+MtnjKix7D0KiHD+e8s2YFjB3j9a=7i7S9J+0g@mail.gmail.com>
References: <20120307221012.GH5050@titan.lakedaemon.net>
 <201203081610.21493.arnd@arndb.de>
 <CAOesGMh2etdQSOjktDGcWGfnsMhyFnVuebWRQeYuR6fvm1_DSA@mail.gmail.com>
 <20120308173029.GK5050@titan.lakedaemon.net>
 <CAOesGMikpxMd+MtnjKix7D0KiHD+e8s2YFjB3j9a=7i7S9J+0g@mail.gmail.com>
Message-ID: <20120308180712.GL5050@titan.lakedaemon.net>

On Thu, Mar 08, 2012 at 09:53:06AM -0800, Olof Johansson wrote:
> On Thu, Mar 8, 2012 at 9:30 AM, Jason <jason at lakedaemon.net> wrote:
> > The following patches should be fine to merge into stable (for 3.4):
> >
> > af42511 ARM: orion: spi: remove enable_clock_fix which is not used
> > d93b2ca ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data.
> > 2bb9207 ARM: kirkwood: fdt: use mrvl ticker symbol
> > ec0ec68 ARM: kirkwood: fdt: absorb kirkwood_init()
> > ...
> > b5c25c3 ARM: kirkwood: rtc-mv devicetree bindings
> > 5e40593 ARM: kirkwood: use devicetree for rtc-mv
> > ...
> 
> Excellent. Can you build up one or more stable branches that I can
> pull those from?

Here's the pull request for stable:

The following changes since commit d65b4e98d7ea3038b767b70fe8be959b2913f16d:

  Linux 3.3-rc3 (2012-02-08 19:21:53 -0800)

are available in the git repository at:
  git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_stable

Andrew Lunn (2):
      ARM: orion: spi: remove enable_clock_fix which is not used
      ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data.

Jason Cooper (6):
      ARM: kirkwood: add dreamplug (fdt) support.
      ARM: kirkwood: convert uart0 to devicetree.
      ARM: kirkwood: fdt: use mrvl ticker symbol
      ARM: kirkwood: fdt: absorb kirkwood_init()
      ARM: kirkwood: rtc-mv devicetree bindings
      ARM: kirkwood: use devicetree for rtc-mv

 arch/arm/boot/dts/kirkwood-dreamplug.dts |   25 ++++
 arch/arm/boot/dts/kirkwood.dtsi          |   12 ++
 arch/arm/mach-kirkwood/Kconfig           |   14 ++
 arch/arm/mach-kirkwood/Makefile          |    1 +
 arch/arm/mach-kirkwood/Makefile.boot     |    2 +
 arch/arm/mach-kirkwood/board-dt.c        |  206 ++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/common.c          |   11 +-
 arch/arm/mach-kirkwood/common.h          |    7 +
 arch/arm/plat-orion/include/plat/audio.h |    1 -
 drivers/rtc/rtc-mv.c                     |    9 ++
 drivers/spi/spi-orion.c                  |    5 -
 include/linux/spi/orion_spi.h            |    1 -
 12 files changed, 281 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-dreamplug.dts
 create mode 100644 arch/arm/boot/dts/kirkwood.dtsi
 create mode 100644 arch/arm/mach-kirkwood/board-dt.c

thx,

Jason.


From khilman at ti.com  Thu Mar  8 13:09:32 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 08 Mar 2012 10:09:32 -0800
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators for
 v3.4
In-Reply-To: <20120308021843.GQ12083@atomide.com> (Tony Lindgren's message of
 "Wed, 7 Mar 2012 18:18:43 -0800")
References: <877gywjhht.fsf@ti.com> <20120308021843.GQ12083@atomide.com>
Message-ID: <87399jc6cj.fsf@ti.com>

Tony Lindgren <tony at atomide.com> writes:

> * Kevin Hilman <khilman at ti.com> [120307 11:42]:
>> Tony,
>> 
>> Please pull the following support for using regulators to control the
>> on-chip VC/VP managed voltage domains.
>> 
>> The regulator driver support for this is already queued in the regulator
>> tree, and this is the supporting core work.
>> 
>> This combined with the CPUfreq changes to use the regulator framework
>> will finally result in MPU DVFS working in mainline.
>
> Nice.. However this one might be missing some header changes?

Oh, that's because it depends on the regulator core changes that are in
Mark's regulator tree.  You need the for-next branch of :

git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git 

For this to compile correctly.

Sorry, I should've been more clear above about the build dependency.

Kevin


From tony at atomide.com  Thu Mar  8 13:13:46 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 10:13:46 -0800
Subject: [GIT PULL] few more fixes for v3.3-rc6
In-Reply-To: <20120308180441.GT12083@atomide.com>
References: <20120308180441.GT12083@atomide.com>
Message-ID: <20120308181345.GU12083@atomide.com>

Olof,

* Tony Lindgren <tony at atomide.com> [120308 09:34]:
> 
> Vaibhav Hiremath (1):
>       ARM: OMAP: id: Add missing break statement in omap3xxx_check_revision

FYI, this one will cause a minor merge conflict with what's in
arm-soc/for-next, here's how to resolve for reference:

--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@@ -397,7 -342,8 +397,8 @@@ void __init omap3xxx_check_revision(voi
  		break;
  	case 0xb944:
  		omap_revision = AM335X_REV_ES1_0;
 -		*cpu_rev = "1.0";
 +		cpu_rev = "1.0";
+ 		break;
  	case 0xb8f2:
  		switch (rev) {
  		case 0:

Regards,

Tony


From paul at pwsan.com  Thu Mar  8 13:18:38 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 8 Mar 2012 11:18:38 -0700 (MST)
Subject: [PATCH 0/2] ARM: OMAP2+: PM: code consolidation for 3.4
In-Reply-To: <CAKd1q9rq67gUyXn+rOL348YwaYQiqHR8UQCSd68fpxhZHHsYGA@mail.gmail.com>
References: <20120202093600.12509.35052.stgit@dusk> <87ty39cc7s.fsf@ti.com>
 <alpine.DEB.2.00.1202021140060.586@utopia.booyaka.com>
 <alpine.DEB.2.00.1202021328450.586@utopia.booyaka.com>
 <CAKd1q9rq67gUyXn+rOL348YwaYQiqHR8UQCSd68fpxhZHHsYGA@mail.gmail.com>
Message-ID: <alpine.DEB.2.00.1203081115010.9551@utopia.booyaka.com>

Hi Luciano,

On Thu, 8 Mar 2012, Coelho, Luciano wrote:

> I can't get ttyO2 wakeup to work on my Blaze with 3.3-rc5.  It works
> fine with 3.2.  I've been trying to bisect and everything, but it's
> difficult.  To start with, during my bisect, many patches seem to be
> in a state where the compilation fails (one example is
> 'OMAP44XX_IRQ_PRCM' undeclared).
> 
> Anyway, what I found out is that after fcf6efa3 (ARM: OMAP4: PM: Add
> WakeupGen module as OMAP gic_arch_extn) wakeup from the console
> doesn't work anymore for me.  Then I tried to comment out the
> omap_wakeupgen_init() call in  gic_init_irq() and that seems to
> work... for a while.  At least until ff819da4 (ARM: OMAP3: CPUidle:
> Make use of CPU PM notifiers) commenting out that line seems to work.
> But it doesn't work if I comment out the line with v3.3-rc5.

Maybe try this patch:

http://www.spinics.net/lists/linux-omap/msg65786.html

If that doesn't work, could you try to reproduce with omap2plus_defconfig 
and a boring kernel command line?


- Paul


From broonie at opensource.wolfsonmicro.com  Thu Mar  8 13:24:28 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 8 Mar 2012 18:24:28 +0000
Subject: [PATCH v3 01/11] ASoC: core: missing set_fmt should not be
 complaint
In-Reply-To: <1331225990-27308-2-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120308182427.GA3638@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 12:59:40AM +0800, Shawn Guo wrote:
> Not having a DAI link set_fmt operation is perfectly normal and
> should not be complaint.

Applied, thanks.  I'll wait for Timur's review on the rest before
applying.
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From khilman at ti.com  Thu Mar  8 13:27:17 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 08 Mar 2012 10:27:17 -0800
Subject: [PATCH 0/2] ARM: OMAP2+: PM: code consolidation for 3.4
In-Reply-To: <CAKd1q9rq67gUyXn+rOL348YwaYQiqHR8UQCSd68fpxhZHHsYGA@mail.gmail.com>
 (Luciano Coelho's message of "Thu, 8 Mar 2012 14:21:43 +0200")
References: <20120202093600.12509.35052.stgit@dusk> <87ty39cc7s.fsf@ti.com>
 <alpine.DEB.2.00.1202021140060.586@utopia.booyaka.com>
 <alpine.DEB.2.00.1202021328450.586@utopia.booyaka.com>
 <CAKd1q9rq67gUyXn+rOL348YwaYQiqHR8UQCSd68fpxhZHHsYGA@mail.gmail.com>
Message-ID: <87sjhjaqyi.fsf@ti.com>

Hi Luca,

"Coelho, Luciano" <coelho at ti.com> writes:

[...]

> I can't get ttyO2 wakeup to work on my Blaze with 3.3-rc5.  It works
> fine with 3.2.  

I assume you mean wakeup from system-wide suspend (echo mem > /sys/power/state)?

Are you enabling UART wakeups?

They are disabled by default, so you need to:

echo enabled > /sys/devices/platform/omap/omap_uart.2/tty/ttyO2/power/wakeup

It may work in v3.2 due to the fact that the UART runtime PM had the
unintended side-effect of essentially disabling MPU and CORE PM.  With
that bug fixed and MPU & CORE actually hitting low power states, you'll
need to ensure UART wakeups are enabled.

If you're already enabling wakeups and this still isn't working, try
adding 'no_console_suspend' to the kernel cmdline, try a suspend/resume
and post the console output.

Thanks,

Kevin


From khilman at ti.com  Thu Mar  8 13:32:05 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 08 Mar 2012 10:32:05 -0800
Subject: [PATCH] mmc: omap_hsmmc: Fix Unbalanced pm_runtime_enable warning
In-Reply-To: <87obsaio93.fsf@ti.com>
References: <20120305234240.GQ12083@atomide.com> <87obsaio93.fsf@ti.com>
Message-ID: <4F58FB25.8020602@ti.com>

Chris,

On 03/05/2012 04:09 PM, Kevin Hilman wrote:
> Tony Lindgren<tony at atomide.com>  writes:
>
>> mmc: omap_hsmmc: Fix Unbalanced pm_runtime_enable warning
>>
>> Otherwise we can get following warning when re-loading the
>> omap_hsmmc driver module when gpio_twl4030 module is not
>> loaded:
>>
>> omap_hsmmc omap_hsmmc.0: Unbalanced pm_runtime_enable!
>> omap_hsmmc omap_hsmmc.0: Unable to grab MMC CD IRQ
>> omap_hsmmc: probe of omap_hsmmc.0 failed with error -22
>>
>> Signed-off-by: Tony Lindgren<tony at atomide.com>
>> ---
>>
>> Kevin, maybe take a look and see if this is correct and
>> fits into your PM branches?
>
> Looks right to me:
>
> Acked-by: Kevin Hilman<khilman at ti.com>
>
> But this is a fix to the driver itself, so Chris should queue this in
> mmc-next.
>
> Chris, can you take this one?
>

just checking on this to be sure it can make it for v3.4.

Kevin


From thierry.reding at avionic-design.de  Thu Mar  8 13:37:31 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 8 Mar 2012 19:37:31 +0100
Subject: [PATCH 06/11] PCI: Keep pci_fixup_irqs() around after init
In-Reply-To: <CAErSpo6hbWjteESST1+O2WzbtmZq6hC-pnUB4o3MAXWG-EgU+g@mail.gmail.com>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-7-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo6hbWjteESST1+O2WzbtmZq6hC-pnUB4o3MAXWG-EgU+g@mail.gmail.com>
Message-ID: <20120308183731.GA25254@avionic-0098.mockup.avionic-design.de>

* Bjorn Helgaas wrote:
> Hmm, your patch looks OK as far as it goes, but the implementation of
> pci_fixup_irqs() as a call-once-at-boot-time thing with a loop through
> all the PCI devices we've found so far looks completely broken with
> regard to hotplug.
> 
> Who does the swizzle for devices hot-added after boot?

Perhaps I should have mentioned this in the commit message, but the patch
isn't actually used in a hotplug scenario. In fact, the code is still run
once at boot time, only very late. Grant's deferred probing allows the
PCIe controller driver to postpone initialization until all the devices
that it depends on (regulators) have been probed. This has the side-effect
that the probing actually takes place *after* code and data annotated with
__init have already been freed.

Thierry
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From bhelgaas at google.com  Thu Mar  8 13:41:13 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Thu, 8 Mar 2012 11:41:13 -0700
Subject: [PATCH 06/11] PCI: Keep pci_fixup_irqs() around after init
In-Reply-To: <20120308183731.GA25254@avionic-0098.mockup.avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-7-git-send-email-thierry.reding@avionic-design.de>
 <CAErSpo6hbWjteESST1+O2WzbtmZq6hC-pnUB4o3MAXWG-EgU+g@mail.gmail.com>
 <20120308183731.GA25254@avionic-0098.mockup.avionic-design.de>
Message-ID: <CAErSpo5rsepKu5yP=f83CadfX3acpV+WP9NuC4nf3FqhPW5Enw@mail.gmail.com>

On Thu, Mar 8, 2012 at 11:37 AM, Thierry Reding
<thierry.reding at avionic-design.de> wrote:
> * Bjorn Helgaas wrote:
>> Hmm, your patch looks OK as far as it goes, but the implementation of
>> pci_fixup_irqs() as a call-once-at-boot-time thing with a loop through
>> all the PCI devices we've found so far looks completely broken with
>> regard to hotplug.
>>
>> Who does the swizzle for devices hot-added after boot?
>
> Perhaps I should have mentioned this in the commit message, but the patch
> isn't actually used in a hotplug scenario. In fact, the code is still run
> once at boot time, only very late. Grant's deferred probing allows the
> PCIe controller driver to postpone initialization until all the devices
> that it depends on (regulators) have been probed. This has the side-effect
> that the probing actually takes place *after* code and data annotated with
> __init have already been freed.

Oh, I know *you're* not using the hotplug scenario.  I'm just thinking
that the PCi core looks a little broken in that scenario.

I think your patch is fine; it's just that I think the PCI core needs
a little more attention in this area.

Bjorn


From coelho at ti.com  Thu Mar  8 13:47:13 2012
From: coelho at ti.com (Luciano Coelho)
Date: Thu, 08 Mar 2012 20:47:13 +0200
Subject: [PATCH 0/2] ARM: OMAP2+: PM: code consolidation for 3.4
In-Reply-To: <87sjhjaqyi.fsf@ti.com>
References: <20120202093600.12509.35052.stgit@dusk> <87ty39cc7s.fsf@ti.com>
 <alpine.DEB.2.00.1202021140060.586@utopia.booyaka.com>
 <alpine.DEB.2.00.1202021328450.586@utopia.booyaka.com>
 <CAKd1q9rq67gUyXn+rOL348YwaYQiqHR8UQCSd68fpxhZHHsYGA@mail.gmail.com>
 <87sjhjaqyi.fsf@ti.com>
Message-ID: <1331232433.18015.69.camel@cumari>

On Thu, 2012-03-08 at 10:27 -0800, Kevin Hilman wrote: 
> Hi Luca,

Hey Kevin,

Thanks for your reply! :)


> "Coelho, Luciano" <coelho at ti.com> writes:
> 
> [...]
> 
> > I can't get ttyO2 wakeup to work on my Blaze with 3.3-rc5.  It works
> > fine with 3.2.  
> 
> I assume you mean wakeup from system-wide suspend (echo mem > /sys/power/state)?

Yes, that's what I meant.

> Are you enabling UART wakeups?
> 
> They are disabled by default, so you need to:
> 
> echo enabled > /sys/devices/platform/omap/omap_uart.2/tty/ttyO2/power/wakeup

No, I was actually not enabling the UART wakeups.  But I tried it now
but it still doesn't work. :(


> It may work in v3.2 due to the fact that the UART runtime PM had the
> unintended side-effect of essentially disabling MPU and CORE PM.  With
> that bug fixed and MPU & CORE actually hitting low power states, you'll
> need to ensure UART wakeups are enabled.
> 
> If you're already enabling wakeups and this still isn't working, try
> adding 'no_console_suspend' to the kernel cmdline, try a suspend/resume
> and post the console output.

I have no_console_suspend in bootargs.  Without it, it didn't work with
3.2 either.

This is what I get when I suspend with "echo mem > /sys/power/state": 

[  128.534271] PM: Syncing filesystems ... done.                                                                        
[  129.948364] PM: Preparing system for mem sleep                                                                       
[  129.957061] Freezing user space processes ...                                                                        
[  129.961761] BUG: sleeping function called from invalid context at include/linux/freezer.h:46                         
[  129.969177] in_atomic(): 0, irqs_disabled(): 128, pid: 770, name: udevd                                              
[  129.977813] INFO: lockdep is turned off.                                                                             
[  129.977813] irq event stamp: 0                                                                                       
[  129.985168] hardirqs last  enabled at (0): [<  (null)>]   (null)                                                     
[  129.991485] hardirqs last disabled at (0): [<c004233c>] copy_process+0x3ec/0x1050                                    
[  129.996520] softirqs last  enabled at (0): [<c004233c>] copy_process+0x3ec/0x1050                                    
[  130.005218] softirqs last disabled at (0): [<  (null)>]   (null)                                                     
[  130.011291] [<c001e204>] (unwind_backtrace+0x0/0x148) from [<c0502fdc>] (dump_stack+0x20/0x24)                       
[  130.018829] [<c0502fdc>] (dump_stack+0x20/0x24) from [<c00779d0>] (__might_sleep+0x130/0x134)                        
[  130.030670] [<c00779d0>] (__might_sleep+0x130/0x134) from [<c0018998>] (do_signal+0x54/0x600)                        
[  130.031738] [<c0018998>] (do_signal+0x54/0x600) from [<c0018fa4>] (do_notify_resume+0x60/0x6c)                       
[  130.049804] [<c0018fa4>] (do_notify_resume+0x60/0x6c) from [<c00154e4>] (work_pending+0x24/0x28)                     
[  130.067138] (elapsed 0.10 seconds) done.                                                                             
[  130.070648] Freezing remaining freezable tasks ... (elapsed 0.02 seconds) done.                                      
[  130.101165] PM: Entering mem sleep                                                                                   
[  130.120056] PM: suspend of devices complete after 9.646 msecs                                                        
[  130.127716] PM: late suspend of devices complete after 7.662 msecs                                                   
[  130.134246] Disabling non-boot CPUs ...                                                                              
[  130.139953] CPU1: shutdown  

The "sleeping function" BUG is that known bug I already complained about
some time ago.  I get it all the time and, in general, it doesn't really
hurt (I guess I'm lucky most of the times not to hit a race-condition).

-- 
Cheers,
Luca.



From Richard.Earnshaw at arm.com  Thu Mar  8 13:47:28 2012
From: Richard.Earnshaw at arm.com (Richard Earnshaw)
Date: Thu, 8 Mar 2012 18:47:28 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <alpine.LFD.2.02.1203081041340.24151@xanadu.home>
References: <alpine.DEB.2.00.1202231714590.23091@kaball-desktop>
 <1330019314-20865-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <alpine.LFD.2.02.1203021528150.31242@xanadu.home> <4F5882BF.1030104@arm.com>
 <alpine.LFD.2.02.1203081041340.24151@xanadu.home>
Message-ID: <4F58FEC0.8080706@arm.com>

On 08/03/12 17:21, Nicolas Pitre wrote:
> On Thu, 8 Mar 2012, Richard Earnshaw wrote:
>
>> On 02/03/12 21:15, Nicolas Pitre wrote:
>>> So, to me, the gcc documentation is perfectly clear on this topic.
>>> there really _is_ a guarantee that those asm marked variables will be in
>>> the expected registers on entry to the inline asm, given that the
>>> variable is _also_ listed as an operand to the asm statement.  But only
>>> in that case.
>>>
>>> It is true that gcc may reorder other function calls or other code
>>> around the inline asm and then intervening code can clobber any
>>> registers.  Then it is up to gcc to preserve the variable's content
>>> elsewhere when its register is used for other purposes, and restore it
>>> when some inline asm statement is referring to it.
>>>
>>> And if gcc does not do this then it is buggy.  Version 3.4.0 of gcc was
>>> buggy.  No other gcc versions in the last 7 years had such a problem or
>>> the __asmeq macro in the kernel would have told us.
>>>
>>>> Or, to summarise another way, there is no way to control which register
>>>> is used to pass something to an inline asm in general (often we get away
>>>> with this, and there are a lot of inline asms in the kernel that assume
>>>> it works, but the more you inline the more likely you are to get nasty
>>>> surprises).
>>>
>>> This statement is therefore unfounded and wrong.  Please direct the
>>> tools guy who mislead you to the above gcc documentation.
>>>
>>
>> The problem is not really about re-ordering functions but about implicit
>> functions that come from the source code; for example
>>
>> int foo (int a, int b)
>> {
>>   register int x __asm__("r0") = 33;
>>
>>   register int c __asm__("r1") = a / b; /* Ooops, clobbers r0 with
>> division function call.  */
>>
>>   asm ("svc 0" : : "r" (x));
>> }
>>
>> There's nothing in the specification to say what happens if there's a
>> statement in the code that causes an implicit clobber of your assembly
>> register.
>
> I'm sure gcc is full of implicit behaviors that are not mentioned in
> the specification.  But as long as the specification is respected, then
> there is no need to mention any unobservable side effects from a program
> flow point of view, right?
>
> Why wouldn't gcc be able to respect the documented feature by
> preventing live variable from being clobbered and reloading them in
> the specified register at the inline asm entry point, just like it does
> for function calls?
>
> Here's an example code that shows that, unfortunately, gcc is still
> broken with regards to the documented behavior:
>
> extern int bar(int);
> int foo(int y)
> {
>         register int x __asm__("r1") = 33;
>         y += bar(x);
>         asm ("@ x should be live in %0 here" : "+r" (x) : "r" (y));
>         y += bar(x);
>         asm ("@ x should be live in %0 here" : "+r" (x) : "r" (y));
>         return x;
> }
>
> Result is:
>
> foo:
>         stmfd   sp!, {r4, lr}
>         mov     r4, r0
>         mov     r0, #33
>         bl      bar
>         add     r4, r0, r4
>         @ x should be live in r1 here
>         mov     r0, r1
>         bl      bar
>         add     r0, r0, r4
>         @ x should be live in r1 here
>         mov     r0, r1
>         ldmfd   sp!, {r4, lr}
>         bx      lr
>
> To me this is clearly a bug if gcc is not able to meet the documented
> expectation.  And the documented expectation is not at all unreasonable.
>
No, in this case it is presumed that /you/ know that calling bar() will
modify x.  Thus the code is either well defined (if you know what is in
r1 after each call to bar), or undefined (if you can't say anything
about r1 after each call).

As I said, the problem really comes from compiler generated calls which
are not mentioned explicitly in the source code.

R.


--
Richard Earnshaw             Email: Richard.Earnshaw at arm.com
Engineering Manager          Phone: +44 1223 400569 (Direct + VoiceMail)
OpenSource Tools             Switchboard: +44 1223 400400
ARM Ltd                      Fax: +44 1223 400410
110 Fulbourn Rd              Web: http://www.arm.com/
Cambridge, UK. CB1 9NJ

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.



From tony at atomide.com  Thu Mar  8 13:49:23 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 10:49:23 -0800
Subject: [PATCH] ARM: OMAP2+: Fix build for omap4 only builds with missing
 include of linux/bug.h
Message-ID: <20120308184923.GV12083@atomide.com>

Found few more with randconfig generated .configs:

In file included from arch/arm/mach-omap2/prm-regbits-34xx.h:17,
                 from arch/arm/mach-omap2/vc.c:18:
arch/arm/mach-omap2/prm2xxx_3xxx.h: In function ?omap2_prm_read_mod_reg?:
arch/arm/mach-omap2/prm2xxx_3xxx.h:239: error: implicit declaration of function ?WARN?

In file included from arch/arm/mach-omap2/powerdomain44xx.c:22:
arch/arm/mach-omap2/prm2xxx_3xxx.h: In function ?omap2_prm_read_mod_reg?:
arch/arm/mach-omap2/prm2xxx_3xxx.h:239: error: implicit declaration of function ?WARN?

This is because omap2_prm functions are currently just stubs for
omap4 only builds.

Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/bug.h>
 
 #include "powerdomain.h"
 #include <plat/prcm.h>
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -10,6 +10,7 @@
 #include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/bug.h>
 
 #include <plat/cpu.h>
 


From paul at pwsan.com  Thu Mar  8 13:55:26 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 8 Mar 2012 11:55:26 -0700 (MST)
Subject: [PATCH 0/2] ARM: OMAP2+: PM: code consolidation for 3.4
In-Reply-To: <1331232433.18015.69.camel@cumari>
References: <20120202093600.12509.35052.stgit@dusk> <87ty39cc7s.fsf@ti.com>
 <alpine.DEB.2.00.1202021140060.586@utopia.booyaka.com>
 <alpine.DEB.2.00.1202021328450.586@utopia.booyaka.com>
 <CAKd1q9rq67gUyXn+rOL348YwaYQiqHR8UQCSd68fpxhZHHsYGA@mail.gmail.com>
 <87sjhjaqyi.fsf@ti.com> <1331232433.18015.69.camel@cumari>
Message-ID: <alpine.DEB.2.00.1203081153540.9551@utopia.booyaka.com>

On Thu, 8 Mar 2012, Luciano Coelho wrote:

> On Thu, 2012-03-08 at 10:27 -0800, Kevin Hilman wrote: 
> 
> > Are you enabling UART wakeups?
> > 
> > They are disabled by default, so you need to:
> > 
> > echo enabled > /sys/devices/platform/omap/omap_uart.2/tty/ttyO2/power/wakeup
> 
> No, I was actually not enabling the UART wakeups.  But I tried it now
> but it still doesn't work. :(

You definitely need that.

> I have no_console_suspend in bootargs.  Without it, it didn't work with
> 3.2 either.

If you want to use no_console_suspend -- which is not recommended -- then 
you'll need 

http://www.spinics.net/lists/linux-omap/msg65786.html

but best simply not to use no_console_suspend.


- Paul


From olof at lixom.net  Thu Mar  8 13:57:28 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 8 Mar 2012 10:57:28 -0800
Subject: [GIT PULL] few more fixes for v3.3-rc6
In-Reply-To: <20120308180441.GT12083@atomide.com>
References: <20120308180441.GT12083@atomide.com>
Message-ID: <CAOesGMjP140q3MP3he=FCa_Rw9xq50V=EpKisMKBZH=HtW98nw@mail.gmail.com>

On Thu, Mar 8, 2012 at 10:04 AM, Tony Lindgren <tony at atomide.com> wrote:
> Hi Arnd & Olof,
>
> Here are few more fixes for the current -rc cycle if there's
> still enough time to get them in.
>
> Regards,
>
> Tony
>
>
> The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
> ?Linus Torvalds (1):
> ? ? ? ?Linux 3.3-rc6
>
> are available in the git repository at:
>
> ?git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fixes

Pulled, thanks.


-Olof


From coelho at ti.com  Thu Mar  8 14:05:47 2012
From: coelho at ti.com (Luciano Coelho)
Date: Thu, 08 Mar 2012 21:05:47 +0200
Subject: [PATCH 0/2] ARM: OMAP2+: PM: code consolidation for 3.4
In-Reply-To: <alpine.DEB.2.00.1203081153540.9551@utopia.booyaka.com>
References: <20120202093600.12509.35052.stgit@dusk> <87ty39cc7s.fsf@ti.com>
 <alpine.DEB.2.00.1202021140060.586@utopia.booyaka.com>
 <alpine.DEB.2.00.1202021328450.586@utopia.booyaka.com>
 <CAKd1q9rq67gUyXn+rOL348YwaYQiqHR8UQCSd68fpxhZHHsYGA@mail.gmail.com>
 <87sjhjaqyi.fsf@ti.com> <1331232433.18015.69.camel@cumari>
 <alpine.DEB.2.00.1203081153540.9551@utopia.booyaka.com>
Message-ID: <1331233547.18015.74.camel@cumari>

On Thu, 2012-03-08 at 11:55 -0700, Paul Walmsley wrote: 
> On Thu, 8 Mar 2012, Luciano Coelho wrote:
> 
> > On Thu, 2012-03-08 at 10:27 -0800, Kevin Hilman wrote: 
> > 
> > > Are you enabling UART wakeups?
> > > 
> > > They are disabled by default, so you need to:
> > > 
> > > echo enabled > /sys/devices/platform/omap/omap_uart.2/tty/ttyO2/power/wakeup
> > 
> > No, I was actually not enabling the UART wakeups.  But I tried it now
> > but it still doesn't work. :(
> 
> You definitely need that.
> 
> > I have no_console_suspend in bootargs.  Without it, it didn't work with
> > 3.2 either.
> 
> If you want to use no_console_suspend -- which is not recommended -- then 
> you'll need 
> 
> http://www.spinics.net/lists/linux-omap/msg65786.html
> 
> but best simply not to use no_console_suspend.

Thanks, Paul! I was just chatting with Kevin about this on IRC.  With
your patch and no_console_suspend, it works. :)

I needed no_console_suspend because it wouldn't work otherwise on
<3.3-rc1.

Now I tried a vanilla 3.3-rc5 without no_console_suspend and enabling
the UART wakeup and it works fine!

Thanks for your help, guys!

-- 
Cheers,
Luca.



From broonie at opensource.wolfsonmicro.com  Thu Mar  8 14:08:27 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 8 Mar 2012 19:08:27 +0000
Subject: [PATCH 04/11] regulator: tps6586x: fix typo in debug message
In-Reply-To: <1331218291-16119-5-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-5-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120308190827.GB3638@opensource.wolfsonmicro.com>

On Thu, Mar 08, 2012 at 03:51:24PM +0100, Thierry Reding wrote:
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>

Applied, thanks.
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From s.hauer at pengutronix.de  Thu Mar  8 14:15:26 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 8 Mar 2012 20:15:26 +0100
Subject: [PATCH v3 10/11] ASoC: fsl: let fsl_ssi work with imx pcm and
 machine drivers
In-Reply-To: <1331225990-27308-11-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-11-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120308191526.GQ3852@pengutronix.de>

On Fri, Mar 09, 2012 at 12:59:49AM +0800, Shawn Guo wrote:
> Makes necessary changes on fsl_ssi to let it work with imx pcm and
> machine drivers.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  sound/soc/fsl/fsl_ssi.c |   67 +++++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 67 insertions(+), 0 deletions(-)
> 
> diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
> index e5903cb..c251ee9 100644
> --- a/sound/soc/fsl/fsl_ssi.c
> +++ b/sound/soc/fsl/fsl_ssi.c
> @@ -29,6 +29,7 @@
>  #include <sound/soc.h>
>  
>  #include "fsl_ssi.h"
> +#include "imx-pcm.h"
>  
>  #ifdef PPC
>  #define read_ssi(addr)			 in_be32(addr)
> @@ -119,6 +120,11 @@ struct fsl_ssi_private {
>  	struct device_attribute dev_attr;
>  	struct platform_device *pdev;
>  
> +	int ssi_on_imx;
> +	struct platform_device *imx_pcm_pdev;
> +	struct imx_pcm_dma_params dma_params_tx;
> +	struct imx_pcm_dma_params dma_params_rx;
> +
>  	struct {
>  		unsigned int rfrc;
>  		unsigned int tfrc;
> @@ -416,6 +422,12 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
>  		ssi_private->second_stream = substream;
>  	}
>  
> +	if (ssi_private->ssi_on_imx)
> +		snd_soc_dai_set_dma_data(dai, substream,
> +			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
> +				&ssi_private->dma_params_tx :
> +				&ssi_private->dma_params_rx);
> +
>  	return 0;
>  }
>  
> @@ -709,6 +721,38 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
>                  /* Older 8610 DTs didn't have the fifo-depth property */
>  		ssi_private->fifo_depth = 8;
>  
> +	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx1-ssi")) {
> +		u32 dma_events[2];
> +		ssi_private->ssi_on_imx = 1;
> +		/*
> +		 * FIXME: The dma burst size must equal to ssi watermark
> +		 * setting on imx.  We have burstsize be "fifo_depth - 2"
> +		 * here because "fifo_depth - 2" rather than fifo_depth is
> +		 * being written into watermark register in fsl_ssi_startup().
> +		 * Is this something needs to be fixed for PowerPC?
> +		 */
> +		ssi_private->dma_params_tx.burstsize =
> +			ssi_private->fifo_depth - 2;
> +		ssi_private->dma_params_rx.burstsize =
> +			ssi_private->fifo_depth - 2;
> +		ssi_private->dma_params_tx.dma_addr =
> +			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
> +		ssi_private->dma_params_rx.dma_addr =
> +			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
> +		/*
> +		 * TODO: This is a temporary solution and should be changed
> +		 * to use generic DMA binding later when the helplers get in.
> +		 */
> +		ret = of_property_read_u32_array(pdev->dev.of_node,
> +					"fsl,ssi-dma-events", dma_events, 2);
> +		if (ret) {
> +			dev_err(&pdev->dev, "could not get dma events\n");
> +			goto error_irq;
> +		}
> +		ssi_private->dma_params_tx.dma = dma_events[0];
> +		ssi_private->dma_params_rx.dma = dma_events[1];
> +	}
> +
>  	/* Initialize the the device_attribute structure */
>  	dev_attr = &ssi_private->dev_attr;
>  	sysfs_attr_init(&dev_attr->attr);
> @@ -732,6 +776,24 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
>  		goto error_dev;
>  	}
>  
> +	/*
> +	 * In case of imx, the machine driver uses new binding which does
> +	 * not require SSI driver to trigger machine driver's probe, but
> +	 * the pcm device needs to be registered here.
> +	 */
> +	if (ssi_private->ssi_on_imx) {
> +		ssi_private->imx_pcm_pdev =
> +			platform_device_register_simple("imx-pcm-audio",
> +							-1, NULL, 0);
> +		if (IS_ERR(ssi_private->imx_pcm_pdev)) {
> +			ret = PTR_ERR(ssi_private->imx_pcm_pdev);
> +			goto error_dev;
> +		} else {
> +			/* success for imx */
> +			return 0;
> +		}
> +	}
> +
>  	/* Trigger the machine driver's probe function.  The platform driver
>  	 * name of the machine driver is taken from /compatible property of the
>  	 * device tree.  We also pass the address of the CPU DAI driver
> @@ -757,6 +819,8 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
>  
>  error_dai:
>  	snd_soc_unregister_dai(&pdev->dev);
> +	if (ssi_private->ssi_on_imx)
> +		platform_device_unregister(ssi_private->imx_pcm_pdev);
>  
>  error_dev:
>  	dev_set_drvdata(&pdev->dev, NULL);
> @@ -783,6 +847,8 @@ static int fsl_ssi_remove(struct platform_device *pdev)
>  
>  	platform_device_unregister(ssi_private->pdev);
>  	snd_soc_unregister_dai(&pdev->dev);
> +	if (ssi_private->ssi_on_imx)
> +		platform_device_unregister(ssi_private->imx_pcm_pdev);
>  	device_remove_file(&pdev->dev, &ssi_private->dev_attr);
>  
>  	free_irq(ssi_private->irq, ssi_private);
> @@ -796,6 +862,7 @@ static int fsl_ssi_remove(struct platform_device *pdev)
>  
>  static const struct of_device_id fsl_ssi_ids[] = {
>  	{ .compatible = "fsl,mpc8610-ssi", },
> +	{ .compatible = "fsl,imx1-ssi", },

imx1 seems wrong here. The register layout has changed significantly between
i.MX1 and i.MX21.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From nsekhar at ti.com  Thu Mar  8 14:23:00 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Thu, 8 Mar 2012 19:23:00 +0000
Subject: [GIT PULL] DaVinci DM644x video display support
Message-ID: <DF0F476B391FA8409C78302C7BA518B6317EEB34@DBDE01.ent.ti.com>

Hi Arnd, Olof,

Can you please pull these two patches adding support
for DaVinci DM644x V4L2 display support for v3.4.

These patches heavily depend on the clean-up series sent earlier.
Since the clean-up series is already included in for-next branch
of arm-soc, I have generated a request using that as baseline.

Let me know if that's not desirable, and I can do it any
other way you want.

Thanks,
Sekhar

The following changes since commit 3a034af7c1a3c55014eeb15a9c9430e9f72810e4:
  Arnd Bergmann (1):
        Merge branch 'next/fixes-non-critical' into for-next

are available in the git repository at:

  git://gitorious.org/linux-davinci/linux-davinci.git v3.4/features

Manjunath Hadli (2):
      ARM: davinci: dm644x: add support for v4l2 video display
      ARM: davinci: dm644x evm: add support for VPBE display

 arch/arm/mach-davinci/board-dm644x-evm.c |  109 +++++++++++++++++++-
 arch/arm/mach-davinci/davinci.h          |    8 ++-
 arch/arm/mach-davinci/dm644x.c           |  166 +++++++++++++++++++++++++++---
 3 files changed, 268 insertions(+), 15 deletions(-)


From tglx at linutronix.de  Thu Mar  8 14:26:11 2012
From: tglx at linutronix.de (Thomas Gleixner)
Date: Thu, 8 Mar 2012 20:26:11 +0100 (CET)
Subject: Regression in 3.2.9 for omap-serial (at least)
In-Reply-To: <CAGGh5h3-1XhMO1-jiBdUJYgh4unRcPonvp=zcXLKMJBfS+qpuQ@mail.gmail.com>
References: <lyk42vxsz2.fsf@ensc-virt.intern.sigma-chemnitz.de>
 <alpine.LFD.2.02.1203081246130.2742@ionos>
 <CAGGh5h3-1XhMO1-jiBdUJYgh4unRcPonvp=zcXLKMJBfS+qpuQ@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1203082024450.2742@ionos>

On Thu, 8 Mar 2012, jean-philippe francois wrote:

> Le 8 mars 2012 12:46, Thomas Gleixner <tglx at linutronix.de> a ?crit :
> > On Thu, 8 Mar 2012, Enrico Scholz wrote:
> >> Hi,
> >>
> >> the commit "genirq: Unmask oneshot irqs when thread was not woken"[1]
> >> breaks at least the omap-serial driver which requests a shared interrupt
> >
> > Fixed with 52abb700e16a9a
> 
> How can I find it ?
> I tried searching in various tree on git.kernel.org,
> but could not find the fix.

It's in Linus tree.

http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=52abb700e16a9aa4cbc03f3d7f80206cbbc80680

From tglx at linutronix.de  Thu Mar  8 14:27:11 2012
From: tglx at linutronix.de (Thomas Gleixner)
Date: Thu, 8 Mar 2012 20:27:11 +0100 (CET)
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <201203081701.01663.arnd@arndb.de>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203072113.04369.arnd@arndb.de>
 <20120308162530.GI5050@titan.lakedaemon.net>
 <201203081701.01663.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1203082026470.2742@ionos>

On Thu, 8 Mar 2012, Arnd Bergmann wrote:

> On Thursday 08 March 2012, Jason wrote:
> > 
> > On Wed, Mar 07, 2012 at 09:13:04PM +0000, Arnd Bergmann wrote:
> > > Finally, something could be wrong with the interrupt controller.
> > > AFAICT, you register it through the device tree now, but it's also
> > > getting initialized through kirkwood_init_irq, so the numbers
> > > would all be wrong.
> > 
> > Yes, I'm working through this now.  mv_cesa silently fails to come up
> > if it can't find the interrupt controller via fdt.  So, it needs to get
> > done.
> > 
> > Right now, I'm looking at how mach-versatile does it (vic_init()) since
> > it's also an ARM926ej-s...
> > 
> 
> Ok, sounds good. It's not important whether it's an ARM9 or not btw.
> You should look at both anything that defines an "interrupt-controller"
> property as an example including Documentation/devicetree/bindings/arm/vic.txt
> and Documentation/devicetree/bindings/arm/gic.txt.
> 
> (taking Thomas Gleixner on Cc)
> 
> Since the orion irq chip is based on irqchip_generic, it would be
> perfect to have a generic irqchip binding to go along with
> kernel/irq/generic-chip.c. Not sure if anyone has thought about this
> before, but it looks like we can completely avoid using
> arch/arm/plat-orion/irq.c and arch/arm/mach-kirkwood/irq.c if we
> do that.

Right. That should be trivial to implement.


From u.kleine-koenig at pengutronix.de  Thu Mar  8 14:36:44 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu,  8 Mar 2012 20:36:44 +0100
Subject: [PATCH] ARM: davinci: cpufreq: fix compiler warning
Message-ID: <1331235404-15565-1-git-send-email-u.kleine-koenig@pengutronix.de>

This fixes:
	arch/arm/mach-davinci/cpufreq.c: In function davinci_target:
	arch/arm/mach-davinci/cpufreq.c:98: warning: passing argument 2 of dev_printk from incompatible pointer type

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-davinci/cpufreq.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
index 5bba707..031048f 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -95,7 +95,7 @@ static int davinci_target(struct cpufreq_policy *policy,
 	if (freqs.old == freqs.new)
 		return ret;
 
-	dev_dbg(&cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new);
+	dev_dbg(cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new);
 
 	ret = cpufreq_frequency_table_target(policy, pdata->freq_table,
 						freqs.new, relation, &idx);
-- 
1.7.9.1



From s.hauer at pengutronix.de  Thu Mar  8 14:37:11 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 8 Mar 2012 20:37:11 +0100
Subject: [PATCH v3] ARM : mx35: 3ds-board: add framebuffer device
In-Reply-To: <1320401632-21444-1-git-send-email-b39297@freescale.com>
References: <1320401632-21444-1-git-send-email-b39297@freescale.com>
Message-ID: <20120308193711.GA32550@pengutronix.de>

On Fri, Nov 04, 2011 at 06:13:52PM +0800, wu guoxing wrote:
> This patch adds framebuffer support for freescale mx35 3ds board
> 
> Signed-off-by: Wu Guoxing <b39297 at freescale.com>
> ---
> Changes since v2:
> 	1. use gpio_set_value_cansleep instead of gpio_set_value
> Changes since v1:
> 	1. use gpio driver for mc9s08dz60
> 
>  arch/arm/mach-imx/mach-mx35_3ds.c |  113 +++++++++++++++++++++++++++++++++++++
>  1 files changed, 113 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
> index 5a5eb3e..fa19c0d 100644
> --- a/arch/arm/mach-imx/mach-mx35_3ds.c
> +++ b/arch/arm/mach-imx/mach-mx35_3ds.c
> @@ -40,9 +40,86 @@
>  #include <mach/iomux-mx35.h>
>  #include <mach/irqs.h>
>  #include <mach/3ds_debugboard.h>
> +#include <video/platform_lcd.h>
>  
>  #include "devices-imx35.h"
>  
> +static const struct fb_videomode fb_modedb[] = {
> +	{
> +	 /* 800x480 @ 55 Hz */
> +	 .name = "Ceramate-CLAA070VC01",
> +	 .refresh = 55,
> +	 .xres = 800,
> +	 .yres = 480,
> +	 .pixclock = 40000,
> +	 .left_margin = 40,
> +	 .right_margin = 40,
> +	 .upper_margin = 5,
> +	 .lower_margin = 5,
> +	 .hsync_len = 20,
> +	 .vsync_len = 10,
> +	 .sync = FB_SYNC_OE_ACT_HIGH,
> +	 .vmode = FB_VMODE_NONINTERLACED,
> +	 .flag = 0,

Two tabs here please

> +	 },
> +};
> +
> +static const struct ipu_platform_data mx3_ipu_data __initconst = {
> +	.irq_base = MXC_IPU_IRQ_START,
> +};
> +
> +static struct mx3fb_platform_data mx3fb_pdata __initdata = {
> +	.name = "Ceramate-CLAA070VC01",
> +	.mode = fb_modedb,
> +	.num_modes = ARRAY_SIZE(fb_modedb),
> +};
> +
> +static struct i2c_board_info __initdata i2c_devices_3ds[] = {
> +	{
> +		I2C_BOARD_INFO("mc9s08dz60", 0x69),
> +	},
> +};
> +
> +static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
> +						     void *data)
> +{
> +	return !strcmp(chip->label, data);
> +}
> +
> +static int mc9s08dz60_lcd_gpio_get(void)
> +{
> +	int ret;
> +	struct gpio_chip *chip;
> +	chip = gpiochip_find(
> +			"mc9s08dz60", mc9s08dz60_gpiochip_match);

The way you search for the gpio looks awkward, though there seems to be
no better way. At least you should call this only once and store the
value. Also you should request the gpio.

> +	if (chip)
> +		ret = chip->base + 6;
> +	else {
> +		pr_err("didn't find mc9s08dz60 gpio\n");
> +		ret = -1;
> +	}

If you have braces in one path the other path should have them aswell.
Please don't return -1 as error value, choose a better one from
incude/asm-generic/errno*

> +	int gpio;
> +
> +	gpio = mc9s08dz60_lcd_gpio_get();
> +	if (gpio >= 0)
> +		gpio_set_value_cansleep(gpio, power);
> +}
> +
> +static struct plat_lcd_data mx35_3ds_lcd_data = {
> +	.set_power = mx35_3ds_lcd_set_power,
> +};
> +
> +static struct platform_device mx35_3ds_lcd = {
> +	.name = "platform-lcd",
> +	.dev.platform_data = &mx35_3ds_lcd_data,
> +};
> +
>  #define EXPIO_PARENT_INT	gpio_to_irq(IMX_GPIO_NR(1, 1))
>  
>  static const struct imxuart_platform_data uart_pdata __initconst = {
> @@ -120,6 +197,32 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
>  	/* I2C1 */
>  	MX35_PAD_I2C1_CLK__I2C1_SCL,
>  	MX35_PAD_I2C1_DAT__I2C1_SDA,
> +	/* Display */
> +	MX35_PAD_LD0__IPU_DISPB_DAT_0,
> +	MX35_PAD_LD1__IPU_DISPB_DAT_1,
> +	MX35_PAD_LD2__IPU_DISPB_DAT_2,
> +	MX35_PAD_LD3__IPU_DISPB_DAT_3,
> +	MX35_PAD_LD4__IPU_DISPB_DAT_4,
> +	MX35_PAD_LD5__IPU_DISPB_DAT_5,
> +	MX35_PAD_LD6__IPU_DISPB_DAT_6,
> +	MX35_PAD_LD7__IPU_DISPB_DAT_7,
> +	MX35_PAD_LD8__IPU_DISPB_DAT_8,
> +	MX35_PAD_LD9__IPU_DISPB_DAT_9,
> +	MX35_PAD_LD10__IPU_DISPB_DAT_10,
> +	MX35_PAD_LD11__IPU_DISPB_DAT_11,
> +	MX35_PAD_LD12__IPU_DISPB_DAT_12,
> +	MX35_PAD_LD13__IPU_DISPB_DAT_13,
> +	MX35_PAD_LD14__IPU_DISPB_DAT_14,
> +	MX35_PAD_LD15__IPU_DISPB_DAT_15,
> +	MX35_PAD_LD16__IPU_DISPB_DAT_16,
> +	MX35_PAD_LD17__IPU_DISPB_DAT_17,
> +	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
> +	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
> +	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
> +	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
> +	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
> +	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
> +	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
>  };
>  
>  static int mx35_3ds_otg_init(struct platform_device *pdev)
> @@ -179,6 +282,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
>   */
>  static void __init mx35_3ds_init(void)
>  {
> +	struct platform_device *imx35_fb_pdev;
> +
>  	imx35_soc_init();
>  
>  	mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
> @@ -204,6 +309,14 @@ static void __init mx35_3ds_init(void)
>  		pr_warn("Init of the debugboard failed, all "
>  				"devices on the debugboard are unusable.\n");
>  	imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
> +
> +	i2c_register_board_info(
> +		0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
> +
> +	imx35_add_ipu_core(&mx3_ipu_data);
> +	imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
> +	mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
> +	platform_device_register(&mx35_3ds_lcd);
>  }
>  
>  static void __init mx35pdk_timer_init(void)
> -- 
> 1.7.1
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From jason at lakedaemon.net  Thu Mar  8 14:47:25 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 8 Mar 2012 14:47:25 -0500
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <alpine.LFD.2.02.1203082026470.2742@ionos>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203072113.04369.arnd@arndb.de>
 <20120308162530.GI5050@titan.lakedaemon.net>
 <201203081701.01663.arnd@arndb.de>
 <alpine.LFD.2.02.1203082026470.2742@ionos>
Message-ID: <20120308194725.GM5050@titan.lakedaemon.net>

On Thu, Mar 08, 2012 at 08:27:11PM +0100, Thomas Gleixner wrote:
> On Thu, 8 Mar 2012, Arnd Bergmann wrote:
> 
> > On Thursday 08 March 2012, Jason wrote:
> > > 
> > > On Wed, Mar 07, 2012 at 09:13:04PM +0000, Arnd Bergmann wrote:
> > > > Finally, something could be wrong with the interrupt controller.
> > > > AFAICT, you register it through the device tree now, but it's also
> > > > getting initialized through kirkwood_init_irq, so the numbers
> > > > would all be wrong.
> > > 
> > > Yes, I'm working through this now.  mv_cesa silently fails to come up
> > > if it can't find the interrupt controller via fdt.  So, it needs to get
> > > done.
> > > 
> > > Right now, I'm looking at how mach-versatile does it (vic_init()) since
> > > it's also an ARM926ej-s...
> > > 
> > 
> > Ok, sounds good. It's not important whether it's an ARM9 or not btw.
> > You should look at both anything that defines an "interrupt-controller"
> > property as an example including Documentation/devicetree/bindings/arm/vic.txt
> > and Documentation/devicetree/bindings/arm/gic.txt.
> > 
> > (taking Thomas Gleixner on Cc)
> > 
> > Since the orion irq chip is based on irqchip_generic, it would be
> > perfect to have a generic irqchip binding to go along with
> > kernel/irq/generic-chip.c. Not sure if anyone has thought about this
> > before, but it looks like we can completely avoid using
> > arch/arm/plat-orion/irq.c and arch/arm/mach-kirkwood/irq.c if we
> > do that.
> 
> Right. That should be trivial to implement.

ok, I'm on it.  kernel/irq/of_generic_irq.c sound good?

thx,

Jason.


From swarren at wwwdotorg.org  Thu Mar  8 14:50:21 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 08 Mar 2012 12:50:21 -0700
Subject: [PATCH 08/11] ARM: tegra: Move tegra_pcie_xclk_clamp() to PMC
In-Reply-To: <1331218291-16119-9-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-9-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F590D7D.70308@wwwdotorg.org>

On 03/08/2012 07:51 AM, Thierry Reding wrote:
> The PMC code already accesses the PMC registers so it makes sense to
> move this function there as well. While at it, rename the function to
> tegra_pmc_pcie_xclk_clamp() for consistency.
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From s.hauer at pengutronix.de  Thu Mar  8 15:04:48 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 8 Mar 2012 21:04:48 +0100
Subject: [PATCH v2 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120308200448.GR3852@pengutronix.de>

On Wed, Mar 07, 2012 at 03:33:32PM +0100, Javier Martin wrote:
> The following series have to be applied on top of the following patches:
> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
> 
> As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
> is deprecated and no new patches are accepted for it.
> 
> This series merges this code into the imx-dma.c dmaengine driver.
> 

I can't find a branch to apply this on. Could you provide a git tree?

If you have to repost this series please consider using -M with git
format-patch.

Sascha

> Changes since v1:
>  - Merge patch 14 with 01.
>  - Add a proper changelog to each patch of the series.
> 
> [PATCH v2 01/13] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
> [PATCH v2 02/13] dmaengine: imx-dma: remove data member from internal structure.
> [PATCH v2 03/13] dmaengine: imx-dma: remove dma_mode member of internal structure.
> [PATCH v2 04/13] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
> [PATCH v2 05/13] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
> [PATCH v2 06/13] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
> [PATCH v2 07/13] dmaengine: imx-dma: remove sg member from internal structure.
> [PATCH v2 08/13] dmaengine: imx-dma: remove 'in_use' field of 'internal' structure.
> [PATCH v2 09/13] dmaengine: imx-dma: remove 'resbytes' field of 'internal' structure.
> [PATCH v2 10/13] dmaengine: imx-dma: remove internal structure.
> [PATCH v2 11/13] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
> [PATCH v2 12/13] dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and 'dma_clk'.
> [PATCH v2 13/13] dmaengine: imx-dma: use 'dev_dbg' and 'dev_warn' for messages.
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From timur at freescale.com  Thu Mar  8 15:05:02 2012
From: timur at freescale.com (Timur Tabi)
Date: Thu, 8 Mar 2012 14:05:02 -0600
Subject: [PATCH v3 00/11] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F5910EE.8090408@freescale.com>

Shawn Guo wrote:
> I did not pick up you Ack-by tag, because there are some changes since
> v2 you will need to take another look and have the testing, I guess.

Unfortunately, although it works on the MPC8610, it's broken on the P1022:

# speaker-test -t sine -c 2 -r 44100


speaker-test 1.0.11rc2


Playback device is default
Stream parameters are 44100Hz, S16_BE, 2 channels
Sine wave rate is 440.0000Hz
Rate set to 44100Hz (requested 44100Hz)
Buffer size range from 256 to 32768
Period size range from 128 to 16384
Periods = 4
Buffer time size 575
To choose buffer_size = 32768
To choose period_size = 8192
was set period_size = 8192
was set buffer_size = 32768

At this point, nothing else happens, there's no audio, and even Ctrl-C
doesn't work.

-- 
Timur Tabi
Linux kernel developer at Freescale



From swarren at wwwdotorg.org  Thu Mar  8 15:09:04 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 08 Mar 2012 13:09:04 -0700
Subject: [PATCH 09/11] ARM: tegra: Rewrite PCIe support as a driver
In-Reply-To: <1331218291-16119-10-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-10-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F5911E0.6060802@wwwdotorg.org>

On 03/08/2012 07:51 AM, Thierry Reding wrote:
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>

Patch description?

> diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
...
> -static int __init harmony_pcie_init(void)
> +static int tegra_pcie_init(struct platform_device *pdev)

That name should probably still be called harmony_something() since it's
still board-specific.

I wonder how having a per-board callback will integrate with device
tree. I guess I'll find out when I review patch 11:-)

> diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c

> +static int __init trimslice_pci_init(void)
>  {
>  	if (!machine_is_trimslice())
>  		return 0;

You can remove that test now.

> diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h

> +#define TEGRA_PCIE_MAX_PORTS 2
> +
> +struct tegra_pcie_pdata {
> +	int (*init)(struct platform_device *pdev);
> +	int (*exit)(struct platform_device *pdev);
> +	bool enable_ports[TEGRA_PCIE_MAX_PORTS];
> +};

That's a somewhat odd place to put the header; a dedicated
mach-tegra/include/mach/tegra_pcie_pdata.h or
include/linux/platform_data/tegra_pcie.h might make more sense.

Aside from those pretty minor issues, this all looks great. Thanks for
fixing our driver!


From timur at freescale.com  Thu Mar  8 15:13:04 2012
From: timur at freescale.com (Timur Tabi)
Date: Thu, 8 Mar 2012 14:13:04 -0600
Subject: [PATCH v3 08/11] ASoC: fsl: make fsl_ssi driver compilable on
 ARM/IMX
In-Reply-To: <1331225990-27308-9-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-9-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F5912D0.2090800@freescale.com>

Shawn Guo wrote:
> +static DEFINE_SPINLOCK(ssi_reg_lock);
> +static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
> +{
> +	u32 val;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&ssi_reg_lock, flags);
> +	val = readl(addr);
> +	val = (val & ~clear) | set;
> +	writel(val, addr);
> +	spin_unlock_irqrestore(&ssi_reg_lock, flags);
> +}
> +#endif

I think this spinlock is the wrong approach.  The problem with
read-modify-write is on the function level, not the register level.

-- 
Timur Tabi
Linux kernel developer at Freescale



From olof at lixom.net  Thu Mar  8 15:23:01 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 8 Mar 2012 12:23:01 -0800
Subject: [GIT PULL] arm-soc: last minute fixes for 3.3
Message-ID: <CAOesGMg0RD1KtejF0LpqO4GUdzMtPxvpbkgONOvhGQVDSH0xsQ@mail.gmail.com>

Hi Linus,

Here are a few last-minute arm-soc fixes for 3.3.


Thanks!

-Olof

The following changes since commit 4f262acfde22b63498b5e4f165e53d3bb4e96400:

  Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
(2012-03-07 08:33:03 -0800)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
tags/fixes-urgent

for you to fetch changes up to c66fcfa938d84d4661c77e9fe85312dece0133e8:

  Merge branch 'fixes' of
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into
fixes (2012-03-08 10:56:12 -0800)

----------------------------------------------------------------

Last minute fixes for 3.3

One samsung build fix due to a mis-applied patch, and a small set of OMAP fixes.
This should be the last from arm-soc for 3.3, hopefully.

----------------------------------------------------------------
Cousson, Benoit (1):
      ARM: OMAP: irqs: Fix NR_IRQS value to handle PRCM interrupts

Kukjin Kim (1):
      ARM: S3C2440: Fixed build error for s3c244x

Olof Johansson (1):
      Merge branch 'fixes' of
git://git.kernel.org/.../tmlind/linux-omap into fixes

R Sricharan (1):
      ARM: OMAP2+: Fix module build errors with CONFIG_OMAP4_ERRATA_I688

Rajendra Nayak (1):
      ARM: OMAP2+: Remove apply_uV constraints for fixed regulator

Vaibhav Hiremath (1):
      ARM: OMAP: id: Add missing break statement in omap3xxx_check_revision

 arch/arm/mach-omap2/id.c               |    1 +
 arch/arm/mach-omap2/omap4-common.c     |    2 ++
 arch/arm/mach-omap2/twl-common.c       |    1 -
 arch/arm/mach-s3c2440/s3c244x.c        |    1 +
 arch/arm/plat-omap/include/plat/irqs.h |   10 +++++++++-
 5 files changed, 13 insertions(+), 2 deletions(-)


From robherring2 at gmail.com  Thu Mar  8 15:36:05 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 08 Mar 2012 14:36:05 -0600
Subject: [PATCH 5/5 v3] ARM: at91: sam9x5 add i2c DT support
In-Reply-To: <20120308175204.GJ27213@game.jcrosoft.org>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <1331196635-27203-5-git-send-email-plagnioj@jcrosoft.com>
 <4F58E87D.9040701@gmail.com> <20120308175204.GJ27213@game.jcrosoft.org>
Message-ID: <4F591835.5040702@gmail.com>

On 03/08/2012 11:52 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 11:12 Thu 08 Mar     , Rob Herring wrote:
>> On 03/08/2012 02:50 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> For now on use i2c-gpio driver on the same pin as the hardware IP.
>>>
>>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>>> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
>>> Cc: devicetree-discuss at lists.ozlabs.org
>>> ---
>>> v3:
>>>
>>> 	update i2c binding (Rob comments)
>>>
>>> Best Regards,
>>> J.
>>>  arch/arm/boot/dts/at91sam9x5.dtsi |   39 +++++++++++++++++++++++++++++++++++++
>>>  1 files changed, 39 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
>>> index c294657..fdd1ac6 100644
>>> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
>>> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
>>> @@ -188,4 +188,43 @@
>>>  			status = "disabled";
>>>  		};
>>>  	};
>>> +
>>> +	i2c-gpio at 0 {
>>> +		compatible = "i2c-gpio";
>>> +		gpios = <&pioA 30 0 /* sda */
>>> +			 &pioA 31 0 /* scl */
>>> +			>;
>>> +		i2c-gpio,sda-open-drain;
>>> +		i2c-gpio,scl-open-drain;
>>> +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +		status = "disabled";
>>> +	};
>>> +
>>> +	i2c-gpio at 1 {
>>> +		compatible = "i2c-gpio";
>>> +		gpios = <&pioC 0 0 /* sda */
>>> +			 &pioC 1 0 /* scl */
>>> +			>;
>>> +		i2c-gpio,sda-open-drain;
>>> +		i2c-gpio,scl-open-drain;
>>> +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +		status = "disabled";
>>> +	};
>>> +
>>> +	i2c-gpio at 2 {
>>> +		compatible = "i2c-gpio";
>>> +		gpios = <&pioB 4 0 /* sda */
>>> +			 &pioB 5 0 /* scl */
>>> +			>;
>>> +		i2c-gpio,sda-open-drain;
>>> +		i2c-gpio,scl-open-drain;
>>> +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +		status = "disabled";
>>> +	};
>>
>> If these are just any random gpio lines, it seems strange to define
>> these in a SOC dtsi and then disable them.
> they are not, they are the same pin as the i2c hardware IP.
> 
> Today the hw driver is not ready or will not work correctly (IP issue)
> 
> On hardware design we use the I2C pin but can not use the hw driver
> 

Okay. Then other than the i2c-gpio node name, ack for all of these.

Rob



From tony at atomide.com  Thu Mar  8 15:43:28 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 12:43:28 -0800
Subject: [PATCH] ARM: OMAP2+: Fix compile error when FB_OMAP2 is not set
Message-ID: <20120308204328.GW12083@atomide.com>

Otherwise we will get:

arch/arm/plat-omap/fb.c:101: error: expected ?)? before ?*? token

Signed-off-by: Tony Lindgren <tony at atomide.com>

---

Tomi, you need something like this for what you have in for-next.

--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -98,6 +98,8 @@ arch_initcall(omap_init_fb);
 
 #else
 
-void __init omapfb_set_lcd_config(omap_lcd_config *config) { }
+void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
+{
+}
 
 #endif


From timur at freescale.com  Thu Mar  8 15:45:29 2012
From: timur at freescale.com (Timur Tabi)
Date: Thu, 8 Mar 2012 14:45:29 -0600
Subject: [PATCH v3 10/11] ASoC: fsl: let fsl_ssi work with imx pcm and
 machine drivers
In-Reply-To: <1331225990-27308-11-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-11-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F591A69.9060401@freescale.com>

Shawn Guo wrote:

> +	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx1-ssi")) {

I wonder if the i.MX code should be protected by an #ifdef.  There's no
point in compiling this code on PowerPC.

> +		/*
> +		 * FIXME: The dma burst size must equal to ssi watermark
> +		 * setting on imx.  We have burstsize be "fifo_depth - 2"
> +		 * here because "fifo_depth - 2" rather than fifo_depth is
> +		 * being written into watermark register in fsl_ssi_startup().
> +		 * Is this something needs to be fixed for PowerPC?

Setting the watermark to fifo_depth-2 allows the SSI to continue storing
data into the FIFO (during capture) in the case the DMA engine isn't fast
enough.  I don't want the FIFO to be completely full before we start the DMA.

For playback, it's the same thing.  I can't be sure the FIFO is completely
empty when it's time to DMA more data.

> +		 */
> +		ssi_private->dma_params_tx.burstsize =
> +			ssi_private->fifo_depth - 2;
> +		ssi_private->dma_params_rx.burstsize =
> +			ssi_private->fifo_depth - 2;
> +		ssi_private->dma_params_tx.dma_addr =
> +			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
> +		ssi_private->dma_params_rx.dma_addr =
> +			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);

So I'm a little confused by this new binding.  I went through a lot of
work to remove DMA-specific data from the SSI driver, and here you are
adding a bunch of it back.  What you're doing here -- I'm doing it in the
DMA driver where it belongs.

> +		/*
> +		 * TODO: This is a temporary solution and should be changed
> +		 * to use generic DMA binding later when the helplers get in.
> +		 */
> +		ret = of_property_read_u32_array(pdev->dev.of_node,
> +					"fsl,ssi-dma-events", dma_events, 2);
> +		if (ret) {
> +			dev_err(&pdev->dev, "could not get dma events\n");
> +			goto error_irq;
> +		}
> +		ssi_private->dma_params_tx.dma = dma_events[0];
> +		ssi_private->dma_params_rx.dma = dma_events[1];

of_property_read_u32_array seems overkill for just two integers.

ssi_private->dma_params_tx.dma = be32_to_cpu(prop[0]);
ssi_private->dma_params_rx.dma = be32_to_cpu(prop[1]);

-- 
Timur Tabi
Linux kernel developer at Freescale



From tony at atomide.com  Thu Mar  8 15:46:07 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 12:46:07 -0800
Subject: [PATCH] ARM: OMAP2+: Fix compile error when FB_OMAP2 is not set
In-Reply-To: <20120308204328.GW12083@atomide.com>
References: <20120308204328.GW12083@atomide.com>
Message-ID: <20120308204607.GX12083@atomide.com>

* Tony Lindgren <tony at atomide.com> [120308 12:11]:
> Otherwise we will get:
> 
> arch/arm/plat-omap/fb.c:101: error: expected ?)? before ?*? token
> 
> Signed-off-by: Tony Lindgren <tony at atomide.com>
> 
> ---
> 
> Tomi, you need something like this for what you have in for-next.
> 
> --- a/arch/arm/plat-omap/fb.c
> +++ b/arch/arm/plat-omap/fb.c
> @@ -98,6 +98,8 @@ arch_initcall(omap_init_fb);
>  
>  #else
>  
> -void __init omapfb_set_lcd_config(omap_lcd_config *config) { }
> +void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
> +{
> +}
>  
>  #endif

Also now seeing the following with what you have in for-next:

drivers/video/omap2/displays/panel-taal.c: In function ?taal_num_errors_show?:
drivers/video/omap2/displays/panel-taal.c:605: warning: ?errors? may be used uninitialized in this function

Tony


From timur at freescale.com  Thu Mar  8 15:50:21 2012
From: timur at freescale.com (Timur Tabi)
Date: Thu, 8 Mar 2012 14:50:21 -0600
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F591B8D.8090705@freescale.com>

Shawn Guo wrote:
> As Documentation/devicetree/bindings/powerpc/fsl/ssi.txt documented,
> codec-handle is an optional property, so missing it should not be a
> fatal error.]

It's optional in the sense that if your SSI is not connected to anything,
then you don't need to specify the codec handle.  If the SSI is connected
to a codec, then the SSI node needs to point to it.

> More importantly, the imx machine drivers to be added working with
> fsl_ssi will not have this property, as they use new ASoC machine
> driver binding mechanism.

I want to see that binding documented in Documentation/devicetree/bindings
first.

-- 
Timur Tabi
Linux kernel developer at Freescale



From timur at freescale.com  Thu Mar  8 15:50:47 2012
From: timur at freescale.com (Timur Tabi)
Date: Thu, 8 Mar 2012 14:50:47 -0600
Subject: [PATCH v3 07/11] ASoC: fsl: check property 'compatible' for the
 machine name
In-Reply-To: <1331225990-27308-8-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-8-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F591BA7.2050602@freescale.com>

Shawn Guo wrote:
> Check /compatible rather than /model to determine the machine name.
> The p1022ds older device trees get a different /model from the new
> ones, while /compatible is consistent there, so checking /compatible
> will save the bother of detecting older p1022ds device trees.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---

Acked-by: Timur Tabi <timur at freescale.com>

-- 
Timur Tabi
Linux kernel developer at Freescale



From tony at atomide.com  Thu Mar  8 15:53:29 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 12:53:29 -0800
Subject: [GIT PULL 1/7] non-critical fixes part3 for upcoming merge window
Message-ID: <pull-1331240009-558004>

Hi Olof,

Here are two more pre-emptive fixes for upcoming merge
window to pull into arm-soc/next/fixes-non-critical.

Now with the fixes finallny out of the way after all
the cleanup related changes, as a reply to this pull
request I'm posting some more pull requests for cleanup
and some minor board changes.

Regards,

Tony


The following changes since commit 9cf793f9b8b1ba9414e2a7591b2e911885f85a27:
  Kevin Hilman (1):
        ARM: OMAP: convert omap_device_build() and callers to __init

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fixes-non-critical-part3

Tony Lindgren (2):
      ARM: OMAP2+: Fix section warnings for hsmmc_init_one
      ARM: OMAP2+: Fix build for omap4 only builds with missing include of linux/bug.h

 arch/arm/mach-omap2/hsmmc.c           |    2 +-
 arch/arm/mach-omap2/powerdomain44xx.c |    1 +
 arch/arm/mach-omap2/vc.c              |    1 +
 3 files changed, 3 insertions(+), 1 deletions(-)


From tony at atomide.com  Thu Mar  8 15:53:29 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 12:53:29 -0800
Subject: [GIT PULL 2/7] omap1 ams-delta clean-up
In-Reply-To: <pull-1331240009-558004>
Message-ID: <mailman.4.1331240024.14256.linux-arm-kernel@lists.infradead.org>

This one contains the recently discussed omap1 ams-delta
clean-up to pull into the board branch. This removes the
last remaining section warnings for omap1, at least when
using omap1_defconfig.

As this depends on already merged omap1 branch 967809b
in arm-soc boards branch, and for a later than -rc1 to
compile on omap1, this one is based on a merge of omap1
and -rc5. So the suggested pull location is boards branch.


The following changes since commit 42392762149cba0a74c1c5b1b1bb868d86e62383:
  Tony Lindgren (1):
        Merge branch 'omap1' into ams-delta

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap ams-delta

Janusz Krzysztofik (5):
      ARM: OMAP1: ams-delta: fix incorrect section tags
      ARM: OMAP1: ams-delta: clean up init data section assignments
      ARM: OMAP1: ams-delta: set up regulator over modem reset GPIO pin
      ARM: OMAP1: ams-delta: update the modem to use regulator API
      ASoC: OMAP: ams-delta: drop .set_bias_level callback

 arch/arm/mach-omap1/Kconfig                       |    2 +
 arch/arm/mach-omap1/board-ams-delta.c             |  116 +++++++++++++++++----
 arch/arm/plat-omap/include/plat/board-ams-delta.h |    1 -
 drivers/input/serio/ams_delta_serio.c             |    2 +-
 drivers/mtd/nand/ams-delta.c                      |    2 +-
 drivers/video/omap/lcd_ams_delta.c                |    2 +-
 sound/soc/omap/ams-delta.c                        |   32 ------
 7 files changed, 101 insertions(+), 56 deletions(-)


From tony at atomide.com  Thu Mar  8 15:53:29 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 12:53:29 -0800
Subject: [GIT PULL 3/7] PM clean-up for the upcoming merge window
In-Reply-To: <pull-1331240009-558004>
Message-ID: <mailman.5.1331240029.14256.linux-arm-kernel@lists.infradead.org>

This contains PM clean-up for the upcoming merge window.

As this was conflicting with both already queued cleanup
and hsmmc in fixes-non-critical branches, Kevin based the
series on a merge of the two. Suggest pulling this into
cleanup, this makes cleanup depend on fixes-non-critical,
which I believe already the case.


The following changes since commit 015f1e4297ad32f83251f3f4cee2389ce5516e9e:
  Kevin Hilman (1):
        Merge remote-tracking branch 'omap/hsmmc' into for_3.4/cleanup/pm-base

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap cleanup-pm

Jean Pihet (1):
      ARM: OMAP2+: PM debug: fix the use of debugfs_create_* API

Kevin Hilman (1):
      ARM: OMAP: omap_device: remove omap_device_parent

Paul Walmsley (5):
      ARM: OMAP3: PM: remove superfluous calls to pwrdm_clear_all_prev_pwrst()
      ARM: OMAP2+: PM: clean up omap_set_pwrdm_state()
      ARM: OMAP2+: PM: share clkdms_setup() across OMAP2, 3, 4
      ARM: OMAP2+: omap_device: call all suspend, resume callbacks when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set
      ARM: OMAP2+: PM: share some suspend-related functions across OMAP2, 3, 4

Tony Lindgren (1):
      Merge branch 'for_3.4/cleanup/pm' of git://git.kernel.org/.../khilman/linux-omap-pm into cleanup-pm

 arch/arm/mach-omap2/omap-mpuss-lowpower.c     |    2 -
 arch/arm/mach-omap2/pm-debug.c                |    6 +-
 arch/arm/mach-omap2/pm.c                      |  113 ++++++++++++++++++++-----
 arch/arm/mach-omap2/pm.h                      |    2 +
 arch/arm/mach-omap2/pm24xx.c                  |   75 ++---------------
 arch/arm/mach-omap2/pm34xx.c                  |   74 +----------------
 arch/arm/mach-omap2/pm44xx.c                  |   57 +------------
 arch/arm/plat-omap/include/plat/omap_device.h |    2 +-
 arch/arm/plat-omap/omap-pm-noop.c             |    2 +-
 arch/arm/plat-omap/omap_device.c              |   24 ++----
 10 files changed, 118 insertions(+), 239 deletions(-)


From tony at atomide.com  Thu Mar  8 15:53:29 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 12:53:29 -0800
Subject: [GIT PULL 4/7] tiny uart clean-up for upcoming merge window
In-Reply-To: <pull-1331240009-558004>
Message-ID: <mailman.6.1331240034.14256.linux-arm-kernel@lists.infradead.org>

This one contains removal of some now unneded code.
Also suggested to pull into cleanup branch.


The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:
  Linus Torvalds (1):
        Linux 3.3-rc4

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap uart

NeilBrown (2):
      ARM: OMAP2+: UART: remove unused fields in omap_uart_state.
      ARM: OMAP2+: remove some orphan function declarations.

Tony Lindgren (1):
      Merge branch 'for_3.4/cleanup/uart' of git://git.kernel.org/.../khilman/linux-omap-pm into uart

 arch/arm/mach-omap2/pm.h                 |    1 -
 arch/arm/mach-omap2/serial.c             |    4 ----
 arch/arm/plat-omap/include/plat/serial.h |    1 -
 3 files changed, 0 insertions(+), 6 deletions(-)


From tony at atomide.com  Thu Mar  8 15:53:29 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 12:53:29 -0800
Subject: [GIT PULL 5/7] more DT changes for upcoming merge window
In-Reply-To: <pull-1331240009-558004>
Message-ID: <mailman.7.1331240039.14256.linux-arm-kernel@lists.infradead.org>

Here are some more changes to the DT branch.

As these depend both on the earlier omap dt patches pulled in, and
irqdomain patches queued by Grant, Benoit based on a merge
of the two. Looks like arm-soc/next/dt already has Grant's
commit 280ad7fd, so this should not add any new dependencies.



The following changes since commit 1f52299ec000e2161635b263d81ab92ea7f1f0a7:
  Benoit Cousson (1):
        Merge branch 'irqdomain/next' of git://git.secretlab.ca/git/linux-2.6 into for_3.4/dt_irq_domain2

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap dt-part2

Benoit Cousson (3):
      ARM: OMAP2/3: intc: Add DT support for TI interrupt controller
      arm/dts: OMAP3: Add interrupt-controller bindings for INTC
      ARM: OMAP2+: board-generic: Use of_irq_init API

Ilya Yanok (1):
      arm/dts: mt_ventoux: very basic support for TeeJet Mt.Ventoux board

Tony Lindgren (3):
      Merge branch 'for_3.4/dt_irq_domain' of git://git.kernel.org/.../bcousson/linux-omap-dt into dt-part2
      ARM: OMAP2+: Fix build error when only ARCH_OMAP2/3 or 4 is selected
      ARM: OMAP2+: Remove extra ifdefs for board-generic

 .../devicetree/bindings/arm/omap/intc.txt          |   27 ++++++
 arch/arm/boot/dts/am3517_mt_ventoux.dts            |   27 ++++++
 arch/arm/boot/dts/omap3.dtsi                       |    6 +-
 arch/arm/mach-omap2/board-generic.c                |   99 ++++++++++----------
 arch/arm/mach-omap2/common.h                       |   12 +++
 arch/arm/mach-omap2/irq.c                          |   60 ++++++++++--
 6 files changed, 168 insertions(+), 63 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt
 create mode 100644 arch/arm/boot/dts/am3517_mt_ventoux.dts


From tony at atomide.com  Thu Mar  8 15:53:29 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 12:53:29 -0800
Subject: [GIT PULL 6/7] smartreflex fixes and clean-up for upcoming merge
 window
In-Reply-To: <pull-1331240009-558004>
Message-ID: <mailman.8.1331240042.14256.linux-arm-kernel@lists.infradead.org>

This one contains clean-up and fixes for the smartreflex
so it can be eventually moved to live under drivers.
After this series, the next series will move this to
drivers.

As this depends on earlier fixes-non-critical merged
into arm-soc, this one is based on commit 149f1d5c
there. This would be probably best merged into driver
branch that would then depend on fixes-non-critical.


The following changes since commit 149f1d5c8d2fd6879cdf93ca70f1cb745e698a1e:
  Tony Lindgren (1):
        ARM: OMAP2+: Fix devexit for smartreflex when CONFIG_HOTPLUG is not set

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap sr

Felipe Balbi (4):
      ARM: OMAP3+: SmartReflex: add missing platform_set_drvdata()
      ARM: OMAP3+: SmartReflex: move late_initcall() closer to its argument
      ARM: OMAP3+: SmartReflex: misc cleanups
      ARM: OMAP3+: SmartReflex: micro-optimization for sanity check

Jean Pihet (2):
      ARM: OMAP3+: SmartReflex: fix the use of debugfs_create_* API
      ARM: OMAP3+: SmartReflex: fix error handling

Nishanth Menon (6):
      ARM: OMAP3+: SmartReflex: fix err interrupt disable sequence
      ARM: OMAP3+: SmartReflex Class3: disable errorgen before disable VP
      ARM: OMAP3+: SmartReflex: Add a shutdown hook
      ARM: OMAP3+: SmartReflex: Fix status masking in ERRCONFIG register
      ARM: OMAP3+: SmartReflex: clear ERRCONFIG_VPBOUNDINTST only on a need
      ARM: OMAP3+: hwmod: add SmartReflex IRQs

Shweta Gulati (1):
      ARM: OMAP3+: SmartReflex: use voltage domain name in device attributes

Tony Lindgren (1):
      Merge branch 'for_3.4/cleanup/sr' of git://git.kernel.org/.../khilman/linux-omap-pm into sr

 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c   |   31 +++-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c   |   19 ++-
 arch/arm/mach-omap2/smartreflex-class3.c     |    1 +
 arch/arm/mach-omap2/smartreflex.c            |  227 +++++++++++++++++++-------
 arch/arm/mach-omap2/smartreflex.h            |   10 +
 arch/arm/mach-omap2/sr_device.c              |   11 +-
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    2 -
 7 files changed, 229 insertions(+), 72 deletions(-)


From tony at atomide.com  Thu Mar  8 15:53:29 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 12:53:29 -0800
Subject: [GIT PULL 7/7] minimal omap board updates for upcoming merge window
In-Reply-To: <pull-1331240009-558004>
Message-ID: <mailman.9.1331240046.14256.linux-arm-kernel@lists.infradead.org>

This one contains minimal updates to existing board
files so people can use the mainline kernel easier.

Note that the board-omap4panda.c changes have a minor merge
conflict in the ASoC tree in next/master.


The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
  Linus Torvalds (1):
        Linux 3.3-rc6

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap board

Aaro Koskinen (1):
      ARM: OMAP: add minimal support for Nokia RM-696

Alex (1):
      ARM: OMAP: Add omap_reserve functionality

Grazvydas Ignotas (1):
      ARM: OMAP: pandora: add support for backlight and poweroff

Igor Grinberg (1):
      ARM: OMAP3: cm-t3517: add EMAC support

Ilya Yanok (1):
      ARM: OMAP: move generic EMAC init to separate file

Mircea Gherzan (1):
      ARM: OMAP: enable Bluetooth on the PandaBoard

Uwe Kleine-Knig (1):
      ARM: OMAP4: board-4430sdp: don't initialize value that is never used

Vladimir Zapolskiy (1):
      ARM: OMAP3: RX-51: add explicit mux configuration of tsc2005 control gpios

 arch/arm/mach-omap2/Kconfig                  |    3 +-
 arch/arm/mach-omap2/Makefile                 |    3 +
 arch/arm/mach-omap2/am35xx-emac.c            |  117 ++++++++++++++++++++++++++
 arch/arm/mach-omap2/am35xx-emac.h            |   15 ++++
 arch/arm/mach-omap2/board-4430sdp.c          |    5 +-
 arch/arm/mach-omap2/board-am3517evm.c        |  117 +-------------------------
 arch/arm/mach-omap2/board-cm-t3517.c         |    2 +
 arch/arm/mach-omap2/board-omap3logic.c       |    2 +
 arch/arm/mach-omap2/board-omap3pandora.c     |   11 +++
 arch/arm/mach-omap2/board-omap4panda.c       |    6 ++
 arch/arm/mach-omap2/board-rm680.c            |   14 +++-
 arch/arm/mach-omap2/board-rx51-peripherals.c |   25 +++---
 arch/arm/plat-omap/include/plat/uncompress.h |    1 +
 13 files changed, 192 insertions(+), 129 deletions(-)
 create mode 100644 arch/arm/mach-omap2/am35xx-emac.c
 create mode 100644 arch/arm/mach-omap2/am35xx-emac.h


From gregkh at linuxfoundation.org  Thu Mar  8 15:53:38 2012
From: gregkh at linuxfoundation.org (Greg KH)
Date: Thu, 8 Mar 2012 12:53:38 -0800
Subject: [PATCH 5/9] USB: at91: Device udc add dt support
In-Reply-To: <1331111746-21393-5-git-send-email-plagnioj@jcrosoft.com>
References: <20120307084924.GK21255@game.jcrosoft.org>
 <1331111746-21393-5-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120308205338.GA16644@kroah.com>

On Wed, Mar 07, 2012 at 10:15:42AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Allow to compile it if AT91 is enable.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-usb at vger.kernel.org
> ---
> Hi Greg
> 
> 	if it's ok with you I apply with the rest of the USB patch series via
> 	at91

Ok with me.

greg k-h


From tony at atomide.com  Thu Mar  8 16:08:26 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 13:08:26 -0800
Subject: [PATCH v3] ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
 regulators
In-Reply-To: <87sjhkjj8m.fsf@ti.com>
References: <1330006564-13290-1-git-send-email-mporter@ti.com>
 <87wr74gis6.fsf@ti.com>
 <20120301204553.GA21841@legolas.emea.dhcp.ti.com>
 <87pqcqnc7u.fsf@ti.com>
 <CA+Bv8XaJqL1L8F-n6skY7dHn1XAdDLRKaRjw0deLeoQ5Ao0Fhg@mail.gmail.com>
 <87sjhkjj8m.fsf@ti.com>
Message-ID: <20120308210825.GY12083@atomide.com>

* Kevin Hilman <khilman at ti.com> [120307 11:05]:
> >
> > I don't think the second smsc911x on the Overo, "smsc911x.1", would
> > find it due to the dev_id.
> 
> It's not about finding the second regulator.  As stated in the
> changelog, it's about the duplicate attempt to register the exact same
> platform_device.
> 
> Duplicate attempts to register the exact same platform_device cause
> kobject to panic and give up[1].  So, any platform that calls
> gpmc_smsc911x_init() twice (Overo and T35 in mainline) will panic on
> boot.
> 
> This patch fixes those platforms so they can boot.

Yeah but I guess the second smsc911x instance still would not work,
or am I missing something?

Regards,

Tony


From gregkh at linuxfoundation.org  Thu Mar  8 16:11:20 2012
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Thu, 8 Mar 2012 13:11:20 -0800
Subject: [PATCH RESEND v3] USB: Support for LPC32xx SoC
In-Reply-To: <1331068913-9321-1-git-send-email-stigge@antcom.de>
References: <1331068913-9321-1-git-send-email-stigge@antcom.de>
Message-ID: <20120308211120.GB21058@kroah.com>

On Tue, Mar 06, 2012 at 10:21:53PM +0100, Roland Stigge wrote:
> This patch adds OHCI support to the LPC32xx ARM platform
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>
> 
> ---
>  drivers/usb/host/ohci-hcd.c     |    5 +++
>  drivers/usb/host/ohci-pnx4008.c |   66 +++++++++++++++++++++++++++++++++++++---
>  2 files changed, 67 insertions(+), 4 deletions(-)
> 
> --- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
> +++ linux-2.6/drivers/usb/host/ohci-hcd.c
> @@ -1055,6 +1055,11 @@ MODULE_LICENSE ("GPL");
>  #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
>  #endif
>  
> +#ifdef CONFIG_ARCH_LPC32XX
> +#include "ohci-pnx4008.c"
> +#define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
> +#endif
> +
>  #ifdef CONFIG_ARCH_DAVINCI_DA8XX
>  #include "ohci-da8xx.c"
>  #define PLATFORM_DRIVER		ohci_hcd_da8xx_driver
> --- linux-2.6.orig/drivers/usb/host/ohci-pnx4008.c
> +++ linux-2.6/drivers/usb/host/ohci-pnx4008.c
> @@ -22,6 +22,7 @@
>  #include <linux/i2c.h>
>  
>  #include <mach/hardware.h>
> +#include <asm/mach-types.h>
>  #include <asm/io.h>
>  
>  #include <mach/platform.h>
> @@ -143,7 +144,17 @@ static void i2c_write(u8 buf, u8 subaddr
>  	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
>  }
>  
> -static void isp1301_configure(void)
> +static u16 i2c_read16(u8 subaddr)
> +{
> +	u16 data;
> +
> +	i2c_master_send(isp1301_i2c_client, &subaddr, 1);
> +	i2c_master_recv(isp1301_i2c_client, (u8 *) &data, 2);
> +
> +	return data;
> +}
> +
> +static void isp1301_configure_pnx4008(void)
>  {
>  	/* PNX4008 only supports DAT_SE0 USB mode */
>  	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
> @@ -166,7 +177,51 @@ static void isp1301_configure(void)
>  		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
>  	i2c_write(0xFF,
>  		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
> +}
>  
> +static void isp1301_configure_lpc32xx(void)
> +{
> +	/* LPC32XX only supports DAT_SE0 USB mode */
> +	/* This sequence is important */
> +
> +	/* Disable transparent UART mode first */
> +	i2c_write(MC1_UART_EN, (ISP1301_I2C_MODE_CONTROL_1 |
> +		ISP1301_I2C_REG_CLEAR_ADDR));
> +
> +	i2c_write(~MC1_SPEED_REG, (ISP1301_I2C_MODE_CONTROL_1 |
> +		ISP1301_I2C_REG_CLEAR_ADDR));
> +	i2c_write(MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
> +	i2c_write(~0,
> +		(ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR));
> +	i2c_write((MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
> +		ISP1301_I2C_MODE_CONTROL_2);
> +	i2c_write(~0, (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
> +	i2c_write(MC1_DAT_SE0, ISP1301_I2C_MODE_CONTROL_1);
> +	i2c_write((OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
> +		ISP1301_I2C_OTG_CONTROL_1);
> +	i2c_write((OTG1_DM_PULLUP | OTG1_DP_PULLUP),
> +		(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
> +	i2c_write(~0,
> +		 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
> +	i2c_write(~0,
> +		ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
> +	i2c_write(~0,
> +		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
> +
> +	/* Enable usb_need_clk clock after transceiver is initialized */
> +	__raw_writel((__raw_readl(USB_CTRL) | (1 << 22)), USB_CTRL);
> +
> +	printk(KERN_INFO "ISP1301 Vendor ID  : 0x%04x\n", i2c_read16(0x00));
> +	printk(KERN_INFO "ISP1301 Product ID : 0x%04x\n", i2c_read16(0x02));
> +	printk(KERN_INFO "ISP1301 Version ID : 0x%04x\n", i2c_read16(0x14));
> +}
> +
> +static void isp1301_configure(void)
> +{
> +	if (machine_is_pnx4008())
> +		isp1301_configure_pnx4008();
> +	else
> +		isp1301_configure_lpc32xx();
>  }
>  
>  static inline void isp1301_vbus_on(void)
> @@ -375,7 +430,8 @@ static int __devinit usb_hcd_pnx4008_pro
>  	}
>  
>  	/* Set all USB bits in the Start Enable register */
> -	pnx4008_set_usb_bits();
> +	if (machine_is_pnx4008())
> +		pnx4008_set_usb_bits();
>  
>  	hcd->rsrc_start = pdev->resource[0].start;
>  	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
> @@ -404,7 +460,8 @@ static int __devinit usb_hcd_pnx4008_pro
>  
>  	pnx4008_stop_hc();
>  out4:
> -	pnx4008_unset_usb_bits();
> +	if (machine_is_pnx4008())
> +		pnx4008_unset_usb_bits();

How come some of these pnx4008_* functions you have wrapped in
machine_is_pnx4008(), but not all of them?

Actually, why don't those functions do that kind of checking themselves,
without having to do this before you call them each time?

Consistancy is key.

thanks,

greg k-h


From tony at atomide.com  Thu Mar  8 16:12:48 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 13:12:48 -0800
Subject: [PATCH v2 1/3] ARM: OMAP2+: McBSP: Correct CLKR/FSR clock
 source mux configuration
In-Reply-To: <1331198537-13469-2-git-send-email-peter.ujfalusi@ti.com>
References: <1331198537-13469-1-git-send-email-peter.ujfalusi@ti.com>
 <1331198537-13469-2-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120308211247.GZ12083@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120308 00:50]:
> On OMAP2/3 McBSP1 port has 6 pin setup, while on OMAP4 the port is McBSP4.
> Implement the CLKR/FSR clock mux selection for OMAP4, and make sure that
> we add the correct callback for the correct port across supported OMAP
> versions.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Acked-by: Jarkko Nikula <jarkko.nikula at bitmer.com>

Acked-by: Tony Lindgren <tony at atomide.com>


From swarren at wwwdotorg.org  Thu Mar  8 16:14:39 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 08 Mar 2012 14:14:39 -0700
Subject: [PATCH 10/11] ARM: tegra: pcie: Add MSI support
In-Reply-To: <1331218291-16119-11-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-11-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F59213F.6070107@wwwdotorg.org>

On 03/08/2012 07:51 AM, Thierry Reding wrote:
> This commit adds support for message signaled interrupts to the Tegra
> PCIe controller.
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> ---
> This code is taken from the NVIDIA Vibrante kernel and therefore has no
> appropriate Signed-off-by from the original author. Maybe someone at
> NVIDIA can find out who wrote this code and maybe provide a proper
> Signed-off-by that I can add?

I think if you look in:
git://nv-tegra.nvidia.com/linux-2.6.git android-tegra-2.6.36

the following commits are what you're after:

de7fd8768b32da66eaf4eaf58473c65f7a76808d
arm: tegra: pcie: enabling MSI support for pcie

ac1f8310811c64a084511d2afc27f66334b31a81
ARM: tegra: pcie: fix return value from MSI irq routine

Although the patch below only partially resembles those patches, I guess
because you've rewritten the code a lot to conform to the current kernel
APIs, clean stuff up, etc. Perhaps just saying "based on code by Krishna
Kishore <kthota at nvidia.com>" is enough...

> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c

> +static int tegra_pcie_enable_msi(struct platform_device *pdev)
> +{
> +	struct tegra_pcie_info *pcie = platform_get_drvdata(pdev);
> +	volatile void *pages;
> +	unsigned long base;
> +	unsigned int msi;
> +	int msi_base;
> +	int err;
> +	u32 reg;
> +
> +	mutex_init(&pcie->msi_lock);
> +
> +	msi_base = irq_alloc_descs(-1, 0, INT_PCI_MSI_NR, 0);
> +	if (msi_base < 0) {
> +		dev_err(&pdev->dev, "failed to allocate IRQs\n");
> +		return msi_base;
> +	}
> +
> +	pcie->msi_domain = irq_domain_add_legacy(pcie->dev->of_node,
> +						 INT_PCI_MSI_NR, msi_base,
> +						 0, &irq_domain_simple_ops,
> +						 NULL);
> +	if (!pcie->msi_domain) {
> +		dev_err(&pdev->dev, "failed to create IRQ domain\n");

Free the IRQ descriptors in the error paths?

> +		return -ENOMEM;
> +	}
> +
> +	pcie->msi_chip.name = "PCIe-MSI";
> +	pcie->msi_chip.irq_enable = unmask_msi_irq;
> +	pcie->msi_chip.irq_disable = mask_msi_irq;
> +	pcie->msi_chip.irq_mask = mask_msi_irq;
> +	pcie->msi_chip.irq_unmask = unmask_msi_irq;
> +
> +	for (msi = 0; msi < INT_PCI_MSI_NR; msi++) {
> +		unsigned int irq = irq_find_mapping(pcie->msi_domain, msi);
> +
> +		irq_set_chip_data(irq, pcie);
> +		irq_set_chip_and_handler(irq, &pcie->msi_chip,
> +					 handle_simple_irq);
> +		set_irq_flags(irq, IRQF_VALID);
> +	}
> +
> +	err = platform_get_irq(pdev, 1);
> +	if (err < 0) {
> +		dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);

Same here, and undo setting IRQF_VALID?

> +		return err;
> +	}
...

> +static int tegra_pcie_disable_msi(struct platform_device *pdev)
> +{
> +	return 0;
> +}

This is empty in both the ifdef(CONFIG_PCI_MSI) case and otherwise. It
should probably clean everything up here right?


From khilman at ti.com  Thu Mar  8 16:21:57 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 08 Mar 2012 13:21:57 -0800
Subject: [PATCH 0/2] ARM: OMAP2+: PM: code consolidation for 3.4
In-Reply-To: <1331233547.18015.74.camel@cumari> (Luciano Coelho's message of
 "Thu, 08 Mar 2012 21:05:47 +0200")
References: <20120202093600.12509.35052.stgit@dusk> <87ty39cc7s.fsf@ti.com>
 <alpine.DEB.2.00.1202021140060.586@utopia.booyaka.com>
 <alpine.DEB.2.00.1202021328450.586@utopia.booyaka.com>
 <CAKd1q9rq67gUyXn+rOL348YwaYQiqHR8UQCSd68fpxhZHHsYGA@mail.gmail.com>
 <87sjhjaqyi.fsf@ti.com> <1331232433.18015.69.camel@cumari>
 <alpine.DEB.2.00.1203081153540.9551@utopia.booyaka.com>
 <1331233547.18015.74.camel@cumari>
Message-ID: <87d38mbxfu.fsf@ti.com>

Luciano Coelho <coelho at ti.com> writes:

[...]

> Thanks, Paul! I was just chatting with Kevin about this on IRC.  With
> your patch and no_console_suspend, it works. :)

Just FYI... I've queued this patch from Paul and it's now queued by Tony
for v3.4 in his cleanup-pm branch.

Kevin


From psandeep.s at gmail.com  Thu Mar  8 16:25:13 2012
From: psandeep.s at gmail.com (Sandeep Patil)
Date: Thu, 8 Mar 2012 13:25:13 -0800
Subject: [Linaro-mm-sig] [PATCHv23 12/16] mm: trigger page reclaim in
 alloc_contig_range() to stabilise watermarks
In-Reply-To: <1329929337-16648-13-git-send-email-m.szyprowski@samsung.com>
References: <1329929337-16648-1-git-send-email-m.szyprowski@samsung.com>
 <1329929337-16648-13-git-send-email-m.szyprowski@samsung.com>
Message-ID: <CA+K6fF5aN7Z3roKOzZe+a87ey4YcLd5Fr1U794wvb+8H3qP2+w@mail.gmail.com>

> +static int __reclaim_pages(struct zone *zone, gfp_t gfp_mask, int count)
> +{
> + ? ? ? /*
> + ? ? ? ?* Increase level of watermarks to force kswapd do his job
> + ? ? ? ?* to stabilise at new watermark level.
> + ? ? ? ?*/
> + ? ? ? __update_cma_watermarks(zone, count);
> +
> + ? ? ? /* Obey watermarks as if the page was being allocated */
> + ? ? ? watermark = low_wmark_pages(zone) + count;
> + ? ? ? while (!zone_watermark_ok(zone, 0, watermark, 0, 0)) {

Wouldn't this reclaim (2 * count pages) above low wmark?

You are updating the low wmark first and then adding "count"
for the zone_watermark_ok() check as well ..

Sandeep


From khilman at ti.com  Thu Mar  8 16:26:12 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 08 Mar 2012 13:26:12 -0800
Subject: [PATCH v3] ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
 regulators
In-Reply-To: <20120308210825.GY12083@atomide.com> (Tony Lindgren's message of
 "Thu, 8 Mar 2012 13:08:26 -0800")
References: <1330006564-13290-1-git-send-email-mporter@ti.com>
 <87wr74gis6.fsf@ti.com>
 <20120301204553.GA21841@legolas.emea.dhcp.ti.com>
 <87pqcqnc7u.fsf@ti.com>
 <CA+Bv8XaJqL1L8F-n6skY7dHn1XAdDLRKaRjw0deLeoQ5Ao0Fhg@mail.gmail.com>
 <87sjhkjj8m.fsf@ti.com> <20120308210825.GY12083@atomide.com>
Message-ID: <87y5raaiob.fsf@ti.com>

Tony Lindgren <tony at atomide.com> writes:

> * Kevin Hilman <khilman at ti.com> [120307 11:05]:
>> >
>> > I don't think the second smsc911x on the Overo, "smsc911x.1", would
>> > find it due to the dev_id.
>> 
>> It's not about finding the second regulator.  As stated in the
>> changelog, it's about the duplicate attempt to register the exact same
>> platform_device.
>> 
>> Duplicate attempts to register the exact same platform_device cause
>> kobject to panic and give up[1].  So, any platform that calls
>> gpmc_smsc911x_init() twice (Overo and T35 in mainline) will panic on
>> boot.
>> 
>> This patch fixes those platforms so they can boot.
>
> Yeah but I guess the second smsc911x instance still would not work,
> or am I missing something?

I don't know since my Overo expansion boards don't have a 2nd NIC, but I
suspect you're right.

However, my fix isn't addressing that.  I am fixing a problem where
mainline today will panic on some boards due to duplicate registration.

If the 2nd interface doesn't work, then the original patch that added
the regulators needs a rethink.  My patch to prevent the panic() is
needed for mainline.

Kevin


From grant.likely at secretlab.ca  Thu Mar  8 16:27:01 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 8 Mar 2012 14:27:01 -0700
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <201203072113.04369.arnd@arndb.de>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203071831.31738.arnd@arndb.de>
 <20120307192723.GE5050@titan.lakedaemon.net>
 <201203072113.04369.arnd@arndb.de>
Message-ID: <20120308212701.GB16533@ponder.secretlab.ca>

On Wed, Mar 07, 2012 at 09:13:04PM +0000, Arnd Bergmann wrote:
> On Wednesday 07 March 2012, Jason wrote:
> > Grrr.  Now I'm getting frustrated.  I'm trying to boot without
> > earlyprintk.  Evidently, something is wrong with the above, because the
> > device boots all the way up (blinky lights come on), but I get no
> > messages after the usual "Uncompressing Linux... done, booting the
> > kernel."
> > 
> > Here's my most recent attempt:
> > 
> >         serial at f1012000 {
> >                 device_type = "serial";
> >                 compatible = "ns16550a";
> >                 reg = <0xf1012000 0x100>; /*phys addr*/
> >                 virt-reg = <0xfed12000>;  /*virt addr*/
> >                 reg-shift = <2>;
> >                 reg-io-width = <1>;
> >                 interrupts = <33>;
> >                 current-speed = <115200>;
> >                 interrupt-parent = <&intc>;
> >                 clock-frequency = <200000000>;
> >         };
> > 
> > I've looked at what is done in the powerpc dt's, but, no luck.  When
> > earlyprintk is enabled, I see no error messages, just:
> > 
> > bootconsole [earlycon0] enabled
> > debug: skip boot console de-registration.
> > ...
> > Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
> > 
> > Any pointers?
> 
> My first guess was that clock-frequency is wrong, but it seems that
> this one actually is correct, at least it's the same thing that
> the platform code sets.
> 
> You should never need to pass the virtual address to a device,
> most of all because it cannot be known to the device tree at all.
> The of_serial driver (you did enable that one in Kconfig, right?)

Ugh.  Someone really needs to step up and kill the of_serial driver.  All that
stuff belongs in the core 16550 driver.

g.


From grant.likely at secretlab.ca  Thu Mar  8 16:31:39 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 8 Mar 2012 14:31:39 -0700
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <20120307192723.GE5050@titan.lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <80fb8cef577eee14364e95009f7a590fd9056ee3.1331090356.git.jason@lakedaemon.net>
 <201203071831.31738.arnd@arndb.de>
 <20120307192723.GE5050@titan.lakedaemon.net>
Message-ID: <20120308213139.GC16533@ponder.secretlab.ca>

On Wed, Mar 07, 2012 at 02:27:23PM -0500, Jason wrote:
> On Wed, Mar 07, 2012 at 06:31:31PM +0000, Arnd Bergmann wrote:
> > On Wednesday 07 March 2012, Jason Cooper wrote:
> > > +       serial at f1012000 {
> > > +               compatible = "ns16550a";
> > > +               reg = <0xf1012000 0xff>;
> > > +               reg-shift = <2>;
> > > +               interrupts = <33>;
> > > +               clock-frequency = <200000000>;
> > > +       };
> > 
> > I just noticed that the length here should be inclusive, i.e. 0x100 not 0xff.
> > This is different from the way we define resources in Linux.
> 
> Grrr.  Now I'm getting frustrated.  I'm trying to boot without
> earlyprintk.  Evidently, something is wrong with the above, because the
> device boots all the way up (blinky lights come on), but I get no
> messages after the usual "Uncompressing Linux... done, booting the
> kernel."
> 
> Here's my most recent attempt:
> 

I see that you've resolved your problem, but some comments below on the
device node:

>         serial at f1012000 {
>                 device_type = "serial";

Never use device_type.  It should only ever appear in the memory node, and
I plan to remove it from there too.

>                 compatible = "ns16550a";
>                 reg = <0xf1012000 0x100>; /*phys addr*/
>                 virt-reg = <0xfed12000>;  /*virt addr*/

Don't use virt-reg.  Nothing in the kernel uses it and the kernel will
make it's own decision about virtual address mapping.

>                 reg-shift = <2>;
>                 reg-io-width = <1>;

1 is the default for reg-io-width.  No need to have this property.  It
should only be used if the device requires 32 bit accesses.

>                 interrupts = <33>;
>                 current-speed = <115200>;
>                 interrupt-parent = <&intc>;
>                 clock-frequency = <200000000>;
>         };
> 

g.


From swarren at wwwdotorg.org  Thu Mar  8 16:31:41 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 08 Mar 2012 14:31:41 -0700
Subject: [PATCH 11/11] ARM: tegra: pcie: Add device tree support
In-Reply-To: <1331218291-16119-12-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-12-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F59253D.7070100@wwwdotorg.org>

On 03/08/2012 07:51 AM, Thierry Reding wrote:
> This commit adds support for instantiating the Tegra PCIe controller
> from a device tree.
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>

> diff --git a/Documentation/devicetree/bindings/pci/tegra-pcie.txt b/Documentation/devicetree/bindings/pci/tegra-pcie.txt

> +NVIDIA Tegra PCIe controller
> +
> +Required properties:
> +- compatible: "nvidia,tegra20-pcie"
> +- reg: physical base address and length of the controller's registers
> +- interrupts: the interrupt outputs of the controller
> +
> +Optional properties:
> +- pex-clk-supply: supply voltage for internal reference clock
> +- vdd-supply: power supply for controller (1.05V)

Mark, Liam,

Should those *-supply properties really be optional? I got the
impression talking to Mark in a different thread that all regulators
should exist, although their implementation may be via a fixed
regulator, with no GPIO, as determined by the board design.


From grant.likely at secretlab.ca  Thu Mar  8 16:32:44 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 8 Mar 2012 14:32:44 -0700
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <20120308194725.GM5050@titan.lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203072113.04369.arnd@arndb.de>
 <20120308162530.GI5050@titan.lakedaemon.net>
 <201203081701.01663.arnd@arndb.de>
 <alpine.LFD.2.02.1203082026470.2742@ionos>
 <20120308194725.GM5050@titan.lakedaemon.net>
Message-ID: <20120308213244.GD16533@ponder.secretlab.ca>

On Thu, Mar 08, 2012 at 02:47:25PM -0500, Jason wrote:
> On Thu, Mar 08, 2012 at 08:27:11PM +0100, Thomas Gleixner wrote:
> > On Thu, 8 Mar 2012, Arnd Bergmann wrote:
> > 
> > > On Thursday 08 March 2012, Jason wrote:
> > > > 
> > > > On Wed, Mar 07, 2012 at 09:13:04PM +0000, Arnd Bergmann wrote:
> > > > > Finally, something could be wrong with the interrupt controller.
> > > > > AFAICT, you register it through the device tree now, but it's also
> > > > > getting initialized through kirkwood_init_irq, so the numbers
> > > > > would all be wrong.
> > > > 
> > > > Yes, I'm working through this now.  mv_cesa silently fails to come up
> > > > if it can't find the interrupt controller via fdt.  So, it needs to get
> > > > done.
> > > > 
> > > > Right now, I'm looking at how mach-versatile does it (vic_init()) since
> > > > it's also an ARM926ej-s...
> > > > 
> > > 
> > > Ok, sounds good. It's not important whether it's an ARM9 or not btw.
> > > You should look at both anything that defines an "interrupt-controller"
> > > property as an example including Documentation/devicetree/bindings/arm/vic.txt
> > > and Documentation/devicetree/bindings/arm/gic.txt.
> > > 
> > > (taking Thomas Gleixner on Cc)
> > > 
> > > Since the orion irq chip is based on irqchip_generic, it would be
> > > perfect to have a generic irqchip binding to go along with
> > > kernel/irq/generic-chip.c. Not sure if anyone has thought about this
> > > before, but it looks like we can completely avoid using
> > > arch/arm/plat-orion/irq.c and arch/arm/mach-kirkwood/irq.c if we
> > > do that.
> > 
> > Right. That should be trivial to implement.
> 
> ok, I'm on it.  kernel/irq/of_generic_irq.c sound good?

Rob Herring has done some work in this area.  Please coordinate with him.

g.



From paul.gortmaker at windriver.com  Thu Mar  8 16:34:54 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Thu,  8 Mar 2012 16:34:54 -0500
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
References: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
Message-ID: <1331242494-3157-1-git-send-email-paul.gortmaker@windriver.com>

commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)

  "regulator: Remove support for supplies specified by struct device"

deletes the field from the struct, but this platform was still trying
to set those fields.  Convert them to use the REGULATOR_SUPPLY macro.

arch/arm/mach-pxa/magician.c:581: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/magician.c:581: warning: initialization from incompatible pointer type
arch/arm/mach-pxa/magician.c:585: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/magician.c:585: warning: initialization from incompatible pointer type

arch/arm/mach-pxa/hx4700.c:683: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/hx4700.c:683: warning: initialization from incompatible pointer type
arch/arm/mach-pxa/hx4700.c:687: error: unknown field 'dev' specified in initializer
arch/arm/mach-pxa/hx4700.c:687: warning: initialization from incompatible pointer type

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
---

[v3: fix arg2 in REGULATOR_SUPPLY to have correct names ]

diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index f2c23ea..b6a338b 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -679,14 +679,8 @@ static struct platform_device power_supply = {
  */
 
 static struct regulator_consumer_supply bq24022_consumers[] = {
-	{
-		.dev = &gpio_vbus.dev,
-		.supply = "vbus_draw",
-	},
-	{
-		.dev = &power_supply.dev,
-		.supply = "ac_draw",
-	},
+	REGULATOR_SUPPLY("vbus_draw", "gpio-vbus"),
+	REGULATOR_SUPPLY("ac_draw", "pda-power"),
 };
 
 static struct regulator_init_data bq24022_init_data = {
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 3d6baf9..1a18e63 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -577,14 +577,8 @@ static struct platform_device power_supply = {
  */
 
 static struct regulator_consumer_supply bq24022_consumers[] = {
-	{
-		.dev = &gpio_vbus.dev,
-		.supply = "vbus_draw",
-	},
-	{
-		.dev = &power_supply.dev,
-		.supply = "ac_draw",
-	},
+	REGULATOR_SUPPLY("vbus_draw", "gpio-vbus"),
+	REGULATOR_SUPPLY("ac_draw", "pda-power"),
 };
 
 static struct regulator_init_data bq24022_init_data = {
-- 
1.7.9.1



From s.hauer at pengutronix.de  Thu Mar  8 16:42:27 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu,  8 Mar 2012 22:42:27 +0100
Subject: [RFC] i.MX: drop secondary clocks
Message-ID: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>

Hi All,

On i.MX we currently have grouped clocks, also known as secondary clocks.
These are clocks that get enabled when the primary clock gets enabled.  This
doesn't integrate well into the generic clock framework. Also we often return
the rate of one clock and really enable/disable another clock. I plan to get
rid of these clocks by exposing the individual clocks to the drivers. The
following is meant as an example how this can be done. I have a more complete
series internally but this conflicts with Richards clk_prepare series.

Thanks to the nature of clk_get we can simply clk_get the individual clocks in
the drivers and the current clock implementation will always return the one
with con_id = NULL. Then with the generic clk implementation the drivers will
finally get the individual clocks.

So unless there are objections I will follow up on this after the next merge
window.

Sascha

----------------------------------------------------------------
Sascha Hauer (2):
      clk: Add helper to get/put arrays of clocks
      spi i.MX: do not depend on grouped clocks

 drivers/clk/clkdev.c  |   36 ++++++++++++++++++++++++++++++++++++
 drivers/spi/spi-imx.c |   30 ++++++++++++++++++++----------
 include/linux/clk.h   |    3 +++
 3 files changed, 59 insertions(+), 10 deletions(-)


From s.hauer at pengutronix.de  Thu Mar  8 16:42:28 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu,  8 Mar 2012 22:42:28 +0100
Subject: [PATCH 1/2] clk: Add helper to get/put arrays of clocks
In-Reply-To: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
References: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1331242949-22780-2-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/clkdev.c |   36 ++++++++++++++++++++++++++++++++++++
 include/linux/clk.h  |    3 +++
 2 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 6db161f..c661395 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -89,6 +89,42 @@ void clk_put(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_put);
 
+int clk_get_array(struct device *dev, struct clk **clks, const char **names,
+		int numclks, bool msg)
+{
+	int i, ret;
+
+	for (i = 0; i < numclks; i++) {
+		clks[i] = clk_get(dev, names[i]);
+		if (IS_ERR(clks[i])) {
+			if (msg)
+				dev_err(dev, "getting clock \"%s\" failed with %d\n",
+						names[i] ? names[i] : "",
+						PTR_ERR(clks[i]));
+			ret = PTR_ERR(clks[i]);
+			goto err;
+		}
+	}
+
+	return 0;
+err:
+	while (i > 0) {
+		i--;
+		clk_put(clks[i]);
+	}
+	return ret;
+}
+EXPORT_SYMBOL(clk_get_array);
+
+void clk_put_array(struct clk **clks, int numclks)
+{
+	int i;
+
+	for (i = 0; i < numclks; i++)
+		clk_put(clks[i]);
+}
+EXPORT_SYMBOL(clk_put_array);
+
 void clkdev_add(struct clk_lookup *cl)
 {
 	mutex_lock(&clocks_mutex);
diff --git a/include/linux/clk.h b/include/linux/clk.h
index b9d46fa..1584cbd 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -148,6 +148,9 @@ unsigned long clk_get_rate(struct clk *clk);
  */
 void clk_put(struct clk *clk);
 
+int clk_get_array(struct device *dev, struct clk **clks, const char **names,
+		int numclks, bool msg);
+void clk_put_array(struct clk **clks, int numclks);
 
 /*
  * The remaining APIs are optional for machine class support.
-- 
1.7.9.1



From s.hauer at pengutronix.de  Thu Mar  8 16:42:29 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu,  8 Mar 2012 22:42:29 +0100
Subject: [PATCH 2/2] spi i.MX: do not depend on grouped clocks
In-Reply-To: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
References: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1331242949-22780-3-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/spi/spi-imx.c |   30 ++++++++++++++++++++----------
 1 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index c6e697f..dc32976 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -79,13 +79,20 @@ struct spi_imx_devtype_data {
 	enum spi_imx_devtype devtype;
 };
 
+enum {
+	CLK_PER,
+	CLK_IPG,
+};
+static const char *clknames[] = {"per", "ipg"};
+#define NUM_CLOCKS ARRAY_SIZE(clknames)
+
 struct spi_imx_data {
 	struct spi_bitbang bitbang;
 
 	struct completion xfer_done;
 	void *base;
 	int irq;
-	struct clk *clk;
+	struct clk *clk[NUM_CLOCKS];
 	unsigned long spi_clk;
 
 	unsigned int count;
@@ -846,15 +853,16 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 		goto out_iounmap;
 	}
 
-	spi_imx->clk = clk_get(&pdev->dev, NULL);
-	if (IS_ERR(spi_imx->clk)) {
+	ret = clk_get_array(&pdev->dev, spi_imx->clk, clknames, NUM_CLOCKS, 1);
+	if (ret) {
 		dev_err(&pdev->dev, "unable to get clock\n");
-		ret = PTR_ERR(spi_imx->clk);
 		goto out_free_irq;
 	}
 
-	clk_enable(spi_imx->clk);
-	spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
+	clk_prepare_enable(spi_imx->clk[CLK_IPG]);
+	clk_prepare_enable(spi_imx->clk[CLK_PER]);
+
+	spi_imx->spi_clk = clk_get_rate(spi_imx->clk[CLK_PER]);
 
 	spi_imx->devtype_data->reset(spi_imx);
 
@@ -872,8 +880,9 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 	return ret;
 
 out_clk_put:
-	clk_disable(spi_imx->clk);
-	clk_put(spi_imx->clk);
+	clk_disable_unprepare(spi_imx->clk[CLK_PER]);
+	clk_disable_unprepare(spi_imx->clk[CLK_IPG]);
+	clk_put_array(spi_imx->clk, NUM_CLOCKS);
 out_free_irq:
 	free_irq(spi_imx->irq, spi_imx);
 out_iounmap:
@@ -901,8 +910,9 @@ static int __devexit spi_imx_remove(struct platform_device *pdev)
 	spi_bitbang_stop(&spi_imx->bitbang);
 
 	writel(0, spi_imx->base + MXC_CSPICTRL);
-	clk_disable(spi_imx->clk);
-	clk_put(spi_imx->clk);
+	clk_disable_unprepare(spi_imx->clk[CLK_PER]);
+	clk_disable_unprepare(spi_imx->clk[CLK_IPG]);
+	clk_put_array(spi_imx->clk, NUM_CLOCKS);
 	free_irq(spi_imx->irq, spi_imx);
 	iounmap(spi_imx->base);
 
-- 
1.7.9.1



From stigge at antcom.de  Thu Mar  8 16:49:17 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu,  8 Mar 2012 22:49:17 +0100
Subject: [PATCH v7] lpc32xx: Added ethernet driver
Message-ID: <1331243357-27497-1-git-send-email-stigge@antcom.de>

This patch adds an ethernet driver for the LPC32xx ARM SoC.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Applies to v3.3-rc6

Changes since v6:
 * Use phy_find_first()
 * Fix uniqueness of mii bus name
 * Removed setting of phy_mask (let phy_find_first() do)
 * Removed redundant guard against unset phy_dev in lpc_eth_open()
 * Move PHY attach message to lpc_mii_probe()
 * Added mdiobus_free() to driver remove function

 Thanks to Florian Fainelli for reviewing the last version!

 drivers/net/ethernet/Kconfig       |    1 
 drivers/net/ethernet/Makefile      |    1 
 drivers/net/ethernet/nxp/Kconfig   |    8 
 drivers/net/ethernet/nxp/Makefile  |    1 
 drivers/net/ethernet/nxp/lpc_eth.c | 1604 +++++++++++++++++++++++++++++++++++++
 5 files changed, 1615 insertions(+)

--- linux-2.6.orig/drivers/net/ethernet/Kconfig
+++ linux-2.6/drivers/net/ethernet/Kconfig
@@ -126,6 +126,7 @@ config NET_NETX
 
 source "drivers/net/ethernet/nuvoton/Kconfig"
 source "drivers/net/ethernet/nvidia/Kconfig"
+source "drivers/net/ethernet/nxp/Kconfig"
 source "drivers/net/ethernet/octeon/Kconfig"
 source "drivers/net/ethernet/oki-semi/Kconfig"
 
--- linux-2.6.orig/drivers/net/ethernet/Makefile
+++ linux-2.6/drivers/net/ethernet/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_NET_VENDOR_NATSEMI) += nats
 obj-$(CONFIG_NET_NETX) += netx-eth.o
 obj-$(CONFIG_NET_VENDOR_NUVOTON) += nuvoton/
 obj-$(CONFIG_NET_VENDOR_NVIDIA) += nvidia/
+obj-$(CONFIG_LPC_ENET) += nxp/
 obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon/
 obj-$(CONFIG_NET_VENDOR_OKI) += oki-semi/
 obj-$(CONFIG_ETHOC) += ethoc.o
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/Kconfig
@@ -0,0 +1,8 @@
+config LPC_ENET
+        tristate "NXP ethernet MAC on LPC devices"
+        depends on ARCH_LPC32XX
+        select PHYLIB
+        help
+	  Say Y or M here if you want to use the NXP ethernet MAC included on
+	  some NXP LPC devices. You can safely enable this option for LPC32xx
+	  SoC. Also available as a module.
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_LPC_ENET) += lpc_eth.o
--- /dev/null
+++ linux-2.6/drivers/net/ethernet/nxp/lpc_eth.c
@@ -0,0 +1,1604 @@
+/*
+ * drivers/net/ethernet/nxp/lpc_eth.c
+ *
+ * Author: Kevin Wells <kevin.wells at nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ * Copyright (C) 2012 Roland Stigge <stigge at antcom.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/crc32.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/clk.h>
+#include <linux/workqueue.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/phy.h>
+#include <linux/dma-mapping.h>
+#include <linux/of_net.h>
+#include <linux/types.h>
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <mach/board.h>
+#include <mach/platform.h>
+#include <mach/hardware.h>
+
+#define MODNAME "lpc-eth"
+#define DRV_VERSION "1.00"
+#define PHYDEF_ADDR 0x00
+
+#define ENET_MAXF_SIZE 1536
+#define ENET_RX_DESC 48
+#define ENET_TX_DESC 16
+
+#define NAPI_WEIGHT 16
+
+/*
+ * Ethernet MAC controller Register offsets
+ */
+#define LPC_ENET_MAC1(x)			(x + 0x000)
+#define LPC_ENET_MAC2(x)			(x + 0x004)
+#define LPC_ENET_IPGT(x)			(x + 0x008)
+#define LPC_ENET_IPGR(x)			(x + 0x00C)
+#define LPC_ENET_CLRT(x)			(x + 0x010)
+#define LPC_ENET_MAXF(x)			(x + 0x014)
+#define LPC_ENET_SUPP(x)			(x + 0x018)
+#define LPC_ENET_TEST(x)			(x + 0x01C)
+#define LPC_ENET_MCFG(x)			(x + 0x020)
+#define LPC_ENET_MCMD(x)			(x + 0x024)
+#define LPC_ENET_MADR(x)			(x + 0x028)
+#define LPC_ENET_MWTD(x)			(x + 0x02C)
+#define LPC_ENET_MRDD(x)			(x + 0x030)
+#define LPC_ENET_MIND(x)			(x + 0x034)
+#define LPC_ENET_SA0(x)				(x + 0x040)
+#define LPC_ENET_SA1(x)				(x + 0x044)
+#define LPC_ENET_SA2(x)				(x + 0x048)
+#define LPC_ENET_COMMAND(x)			(x + 0x100)
+#define LPC_ENET_STATUS(x)			(x + 0x104)
+#define LPC_ENET_RXDESCRIPTOR(x)		(x + 0x108)
+#define LPC_ENET_RXSTATUS(x)			(x + 0x10C)
+#define LPC_ENET_RXDESCRIPTORNUMBER(x)		(x + 0x110)
+#define LPC_ENET_RXPRODUCEINDEX(x)		(x + 0x114)
+#define LPC_ENET_RXCONSUMEINDEX(x)		(x + 0x118)
+#define LPC_ENET_TXDESCRIPTOR(x)		(x + 0x11C)
+#define LPC_ENET_TXSTATUS(x)			(x + 0x120)
+#define LPC_ENET_TXDESCRIPTORNUMBER(x)		(x + 0x124)
+#define LPC_ENET_TXPRODUCEINDEX(x)		(x + 0x128)
+#define LPC_ENET_TXCONSUMEINDEX(x)		(x + 0x12C)
+#define LPC_ENET_TSV0(x)			(x + 0x158)
+#define LPC_ENET_TSV1(x)			(x + 0x15C)
+#define LPC_ENET_RSV(x)				(x + 0x160)
+#define LPC_ENET_FLOWCONTROLCOUNTER(x)		(x + 0x170)
+#define LPC_ENET_FLOWCONTROLSTATUS(x)		(x + 0x174)
+#define LPC_ENET_RXFILTER_CTRL(x)		(x + 0x200)
+#define LPC_ENET_RXFILTERWOLSTATUS(x)		(x + 0x204)
+#define LPC_ENET_RXFILTERWOLCLEAR(x)		(x + 0x208)
+#define LPC_ENET_HASHFILTERL(x)			(x + 0x210)
+#define LPC_ENET_HASHFILTERH(x)			(x + 0x214)
+#define LPC_ENET_INTSTATUS(x)			(x + 0xFE0)
+#define LPC_ENET_INTENABLE(x)			(x + 0xFE4)
+#define LPC_ENET_INTCLEAR(x)			(x + 0xFE8)
+#define LPC_ENET_INTSET(x)			(x + 0xFEC)
+#define LPC_ENET_POWERDOWN(x)			(x + 0xFF4)
+
+/*
+ * mac1 register definitions
+ */
+#define LPC_MAC1_RECV_ENABLE			(1 << 0)
+#define LPC_MAC1_PASS_ALL_RX_FRAMES		(1 << 1)
+#define LPC_MAC1_RX_FLOW_CONTROL		(1 << 2)
+#define LPC_MAC1_TX_FLOW_CONTROL		(1 << 3)
+#define LPC_MAC1_LOOPBACK			(1 << 4)
+#define LPC_MAC1_RESET_TX			(1 << 8)
+#define LPC_MAC1_RESET_MCS_TX			(1 << 9)
+#define LPC_MAC1_RESET_RX			(1 << 10)
+#define LPC_MAC1_RESET_MCS_RX			(1 << 11)
+#define LPC_MAC1_SIMULATION_RESET		(1 << 14)
+#define LPC_MAC1_SOFT_RESET			(1 << 15)
+
+/*
+ * mac2 register definitions
+ */
+#define LPC_MAC2_FULL_DUPLEX			(1 << 0)
+#define LPC_MAC2_FRAME_LENGTH_CHECKING		(1 << 1)
+#define LPC_MAC2_HUGH_LENGTH_CHECKING		(1 << 2)
+#define LPC_MAC2_DELAYED_CRC			(1 << 3)
+#define LPC_MAC2_CRC_ENABLE			(1 << 4)
+#define LPC_MAC2_PAD_CRC_ENABLE			(1 << 5)
+#define LPC_MAC2_VLAN_PAD_ENABLE		(1 << 6)
+#define LPC_MAC2_AUTO_DETECT_PAD_ENABLE		(1 << 7)
+#define LPC_MAC2_PURE_PREAMBLE_ENFORCEMENT	(1 << 8)
+#define LPC_MAC2_LONG_PREAMBLE_ENFORCEMENT	(1 << 9)
+#define LPC_MAC2_NO_BACKOFF			(1 << 12)
+#define LPC_MAC2_BACK_PRESSURE			(1 << 13)
+#define LPC_MAC2_EXCESS_DEFER			(1 << 14)
+
+/*
+ * ipgt register definitions
+ */
+#define LPC_IPGT_LOAD(n)			((n) & 0x7F)
+
+/*
+ * ipgr register definitions
+ */
+#define LPC_IPGR_LOAD_PART2(n)			((n) & 0x7F)
+#define LPC_IPGR_LOAD_PART1(n)			(((n) & 0x7F) << 8)
+
+/*
+ * clrt register definitions
+ */
+#define LPC_CLRT_LOAD_RETRY_MAX(n)		((n) & 0xF)
+#define LPC_CLRT_LOAD_COLLISION_WINDOW(n)	(((n) & 0x3F) << 8)
+
+/*
+ * maxf register definitions
+ */
+#define LPC_MAXF_LOAD_MAX_FRAME_LEN(n)		((n) & 0xFFFF)
+
+/*
+ * supp register definitions
+ */
+#define LPC_SUPP_SPEED				(1 << 8)
+#define LPC_SUPP_RESET_RMII			(1 << 11)
+
+/*
+ * test register definitions
+ */
+#define LPC_TEST_SHORTCUT_PAUSE_QUANTA		(1 << 0)
+#define LPC_TEST_PAUSE				(1 << 1)
+#define LPC_TEST_BACKPRESSURE			(1 << 2)
+
+/*
+ * mcfg register definitions
+ */
+#define LPC_MCFG_SCAN_INCREMENT			(1 << 0)
+#define LPC_MCFG_SUPPRESS_PREAMBLE		(1 << 1)
+#define LPC_MCFG_CLOCK_SELECT(n)		(((n) & 0x7) << 2)
+#define LPC_MCFG_CLOCK_HOST_DIV_4		0
+#define LPC_MCFG_CLOCK_HOST_DIV_6		2
+#define LPC_MCFG_CLOCK_HOST_DIV_8		3
+#define LPC_MCFG_CLOCK_HOST_DIV_10		4
+#define LPC_MCFG_CLOCK_HOST_DIV_14		5
+#define LPC_MCFG_CLOCK_HOST_DIV_20		6
+#define LPC_MCFG_CLOCK_HOST_DIV_28		7
+#define LPC_MCFG_RESET_MII_MGMT			(1 << 15)
+
+/*
+ * mcmd register definitions
+ */
+#define LPC_MCMD_READ				(1 << 0)
+#define LPC_MCMD_SCAN				(1 << 1)
+
+/*
+ * madr register definitions
+ */
+#define LPC_MADR_REGISTER_ADDRESS(n)		((n) & 0x1F)
+#define LPC_MADR_PHY_0ADDRESS(n)		(((n) & 0x1F) << 8)
+
+/*
+ * mwtd register definitions
+ */
+#define LPC_MWDT_WRITE(n)			((n) & 0xFFFF)
+
+/*
+ * mrdd register definitions
+ */
+#define LPC_MRDD_READ_MASK			0xFFFF
+
+/*
+ * mind register definitions
+ */
+#define LPC_MIND_BUSY				(1 << 0)
+#define LPC_MIND_SCANNING			(1 << 1)
+#define LPC_MIND_NOT_VALID			(1 << 2)
+#define LPC_MIND_MII_LINK_FAIL			(1 << 3)
+
+/*
+ * command register definitions
+ */
+#define LPC_COMMAND_RXENABLE			(1 << 0)
+#define LPC_COMMAND_TXENABLE			(1 << 1)
+#define LPC_COMMAND_REG_RESET			(1 << 3)
+#define LPC_COMMAND_TXRESET			(1 << 4)
+#define LPC_COMMAND_RXRESET			(1 << 5)
+#define LPC_COMMAND_PASSRUNTFRAME		(1 << 6)
+#define LPC_COMMAND_PASSRXFILTER		(1 << 7)
+#define LPC_COMMAND_TXFLOWCONTROL		(1 << 8)
+#define LPC_COMMAND_RMII			(1 << 9)
+#define LPC_COMMAND_FULLDUPLEX			(1 << 10)
+
+/*
+ * status register definitions
+ */
+#define LPC_STATUS_RXACTIVE			(1 << 0)
+#define LPC_STATUS_TXACTIVE			(1 << 1)
+
+/*
+ * tsv0 register definitions
+ */
+#define LPC_TSV0_CRC_ERROR			(1 << 0)
+#define LPC_TSV0_LENGTH_CHECK_ERROR		(1 << 1)
+#define LPC_TSV0_LENGTH_OUT_OF_RANGE		(1 << 2)
+#define LPC_TSV0_DONE				(1 << 3)
+#define LPC_TSV0_MULTICAST			(1 << 4)
+#define LPC_TSV0_BROADCAST			(1 << 5)
+#define LPC_TSV0_PACKET_DEFER			(1 << 6)
+#define LPC_TSV0_ESCESSIVE_DEFER		(1 << 7)
+#define LPC_TSV0_ESCESSIVE_COLLISION		(1 << 8)
+#define LPC_TSV0_LATE_COLLISION			(1 << 9)
+#define LPC_TSV0_GIANT				(1 << 10)
+#define LPC_TSV0_UNDERRUN			(1 << 11)
+#define LPC_TSV0_TOTAL_BYTES(n)			(((n) >> 12) & 0xFFFF)
+#define LPC_TSV0_CONTROL_FRAME			(1 << 28)
+#define LPC_TSV0_PAUSE				(1 << 29)
+#define LPC_TSV0_BACKPRESSURE			(1 << 30)
+#define LPC_TSV0_VLAN				(1 << 31)
+
+/*
+ * tsv1 register definitions
+ */
+#define LPC_TSV1_TRANSMIT_BYTE_COUNT(n)		((n) & 0xFFFF)
+#define LPC_TSV1_COLLISION_COUNT(n)		(((n) >> 16) & 0xF)
+
+/*
+ * rsv register definitions
+ */
+#define LPC_RSV_RECEIVED_BYTE_COUNT(n)		((n) & 0xFFFF)
+#define LPC_RSV_RXDV_EVENT_IGNORED		(1 << 16)
+#define LPC_RSV_RXDV_EVENT_PREVIOUSLY_SEEN	(1 << 17)
+#define LPC_RSV_CARRIER_EVNT_PREVIOUS_SEEN	(1 << 18)
+#define LPC_RSV_RECEIVE_CODE_VIOLATION		(1 << 19)
+#define LPC_RSV_CRC_ERROR			(1 << 20)
+#define LPC_RSV_LENGTH_CHECK_ERROR		(1 << 21)
+#define LPC_RSV_LENGTH_OUT_OF_RANGE		(1 << 22)
+#define LPC_RSV_RECEIVE_OK			(1 << 23)
+#define LPC_RSV_MULTICAST			(1 << 24)
+#define LPC_RSV_BROADCAST			(1 << 25)
+#define LPC_RSV_DRIBBLE_NIBBLE			(1 << 26)
+#define LPC_RSV_CONTROL_FRAME			(1 << 27)
+#define LPC_RSV_PAUSE				(1 << 28)
+#define LPC_RSV_UNSUPPORTED_OPCODE		(1 << 29)
+#define LPC_RSV_VLAN				(1 << 30)
+
+/*
+ * flowcontrolcounter register definitions
+ */
+#define LPC_FCCR_MIRRORCOUNTER(n)		((n) & 0xFFFF)
+#define LPC_FCCR_PAUSETIMER(n)			(((n) >> 16) & 0xFFFF)
+
+/*
+ * flowcontrolstatus register definitions
+ */
+#define LPC_FCCR_MIRRORCOUNTERCURRENT(n)	((n) & 0xFFFF)
+
+/*
+ * rxfliterctrl, rxfilterwolstatus, and rxfilterwolclear shared
+ * register definitions
+ */
+#define LPC_RXFLTRW_ACCEPTUNICAST		(1 << 0)
+#define LPC_RXFLTRW_ACCEPTUBROADCAST		(1 << 1)
+#define LPC_RXFLTRW_ACCEPTUMULTICAST		(1 << 2)
+#define LPC_RXFLTRW_ACCEPTUNICASTHASH		(1 << 3)
+#define LPC_RXFLTRW_ACCEPTUMULTICASTHASH	(1 << 4)
+#define LPC_RXFLTRW_ACCEPTPERFECT		(1 << 5)
+
+/*
+ * rxfliterctrl register definitions
+ */
+#define LPC_RXFLTRWSTS_MAGICPACKETENWOL		(1 << 12)
+#define LPC_RXFLTRWSTS_RXFILTERENWOL		(1 << 13)
+
+/*
+ * rxfilterwolstatus/rxfilterwolclear register definitions
+ */
+#define LPC_RXFLTRWSTS_RXFILTERWOL		(1 << 7)
+#define LPC_RXFLTRWSTS_MAGICPACKETWOL		(1 << 8)
+
+/*
+ * intstatus, intenable, intclear, and Intset shared register
+ * definitions
+ */
+#define LPC_MACINT_RXOVERRUNINTEN		(1 << 0)
+#define LPC_MACINT_RXERRORONINT			(1 << 1)
+#define LPC_MACINT_RXFINISHEDINTEN		(1 << 2)
+#define LPC_MACINT_RXDONEINTEN			(1 << 3)
+#define LPC_MACINT_TXUNDERRUNINTEN		(1 << 4)
+#define LPC_MACINT_TXERRORINTEN			(1 << 5)
+#define LPC_MACINT_TXFINISHEDINTEN		(1 << 6)
+#define LPC_MACINT_TXDONEINTEN			(1 << 7)
+#define LPC_MACINT_SOFTINTEN			(1 << 12)
+#define LPC_MACINT_WAKEUPINTEN			(1 << 13)
+
+/*
+ * powerdown register definitions
+ */
+#define LPC_POWERDOWN_MACAHB			(1 << 31)
+
+/* Upon the upcoming introduction of device tree usage in LPC32xx,
+ * lpc_phy_interface_mode() and use_iram_for_net() will be extended with a
+ * device parameter for access to device tree information at runtime, instead
+ * of defining the values at compile time
+ */
+static inline phy_interface_t lpc_phy_interface_mode(void)
+{
+#ifdef CONFIG_ARCH_LPC32XX_MII_SUPPORT
+	return PHY_INTERFACE_MODE_MII;
+#else
+	return PHY_INTERFACE_MODE_RMII;
+#endif
+}
+
+static inline int use_iram_for_net(void)
+{
+#ifdef CONFIG_ARCH_LPC32XX_IRAM_FOR_NET
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+/* Receive Status information word */
+#define RXSTATUS_SIZE			0x000007FF
+#define RXSTATUS_CONTROL		(1 << 18)
+#define RXSTATUS_VLAN			(1 << 19)
+#define RXSTATUS_FILTER			(1 << 20)
+#define RXSTATUS_MULTICAST		(1 << 21)
+#define RXSTATUS_BROADCAST		(1 << 22)
+#define RXSTATUS_CRC			(1 << 23)
+#define RXSTATUS_SYMBOL			(1 << 24)
+#define RXSTATUS_LENGTH			(1 << 25)
+#define RXSTATUS_RANGE			(1 << 26)
+#define RXSTATUS_ALIGN			(1 << 27)
+#define RXSTATUS_OVERRUN		(1 << 28)
+#define RXSTATUS_NODESC			(1 << 29)
+#define RXSTATUS_LAST			(1 << 30)
+#define RXSTATUS_ERROR			(1 << 31)
+
+#define RXSTATUS_STATUS_ERROR \
+	(RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | \
+	 RXSTATUS_RANGE | RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC)
+
+/* Receive Descriptor control word */
+#define RXDESC_CONTROL_SIZE		0x000007FF
+#define RXDESC_CONTROL_INT		(1 << 31)
+
+/* Transmit Status information word */
+#define TXSTATUS_COLLISIONS_GET(x)	(((x) >> 21) & 0xF)
+#define TXSTATUS_DEFER			(1 << 25)
+#define TXSTATUS_EXCESSDEFER		(1 << 26)
+#define TXSTATUS_EXCESSCOLL		(1 << 27)
+#define TXSTATUS_LATECOLL		(1 << 28)
+#define TXSTATUS_UNDERRUN		(1 << 29)
+#define TXSTATUS_NODESC			(1 << 30)
+#define TXSTATUS_ERROR			(1 << 31)
+
+/* Transmit Descriptor control word */
+#define TXDESC_CONTROL_SIZE		0x000007FF
+#define TXDESC_CONTROL_OVERRIDE		(1 << 26)
+#define TXDESC_CONTROL_HUGE		(1 << 27)
+#define TXDESC_CONTROL_PAD		(1 << 28)
+#define TXDESC_CONTROL_CRC		(1 << 29)
+#define TXDESC_CONTROL_LAST		(1 << 30)
+#define TXDESC_CONTROL_INT		(1 << 31)
+
+static int lpc_eth_hard_start_xmit(struct sk_buff *skb,
+				   struct net_device *ndev);
+
+/*
+ * Structure of a TX/RX descriptors and RX status
+ */
+struct txrx_desc_t {
+	__le32 packet;
+	__le32 control;
+};
+struct rx_status_t {
+	__le32 statusinfo;
+	__le32 statushashcrc;
+};
+
+/*
+ * Device driver data structure
+ */
+struct netdata_local {
+	struct platform_device	*pdev;
+	struct net_device	*ndev;
+	spinlock_t		lock;
+	void __iomem		*net_base;
+	u32			msg_enable;
+	struct sk_buff		*skb[ENET_TX_DESC];
+	unsigned int		last_tx_idx;
+	unsigned int		num_used_tx_buffs;
+	struct mii_bus		*mii_bus;
+	struct phy_device	*phy_dev;
+	struct clk		*clk;
+	dma_addr_t		dma_buff_base_p;
+	void			*dma_buff_base_v;
+	size_t			dma_buff_size;
+	struct txrx_desc_t	*tx_desc_v;
+	u32			*tx_stat_v;
+	void			*tx_buff_v;
+	struct txrx_desc_t	*rx_desc_v;
+	struct rx_status_t	*rx_stat_v;
+	void			*rx_buff_v;
+	int			link;
+	int			speed;
+	int			duplex;
+	struct napi_struct	napi;
+};
+
+/*
+ * MAC support functions
+ */
+static void __lpc_set_mac(struct netdata_local *pldat, u8 *mac)
+{
+	u32 tmp;
+
+	/* Set station address */
+	tmp = mac[0] | ((u32)mac[1] << 8);
+	writel(tmp, LPC_ENET_SA2(pldat->net_base));
+	tmp = mac[2] | ((u32)mac[3] << 8);
+	writel(tmp, LPC_ENET_SA1(pldat->net_base));
+	tmp = mac[4] | ((u32)mac[5] << 8);
+	writel(tmp, LPC_ENET_SA0(pldat->net_base));
+
+	netdev_dbg(pldat->ndev, "Ethernet MAC address %pM\n", mac);
+}
+
+static void __lpc_get_mac(struct netdata_local *pldat, u8 *mac)
+{
+	u32 tmp;
+
+	/* Get station address */
+	tmp = readl(LPC_ENET_SA2(pldat->net_base));
+	mac[0] = tmp & 0xFF;
+	mac[1] = tmp >> 8;
+	tmp = readl(LPC_ENET_SA1(pldat->net_base));
+	mac[2] = tmp & 0xFF;
+	mac[3] = tmp >> 8;
+	tmp = readl(LPC_ENET_SA0(pldat->net_base));
+	mac[4] = tmp & 0xFF;
+	mac[5] = tmp >> 8;
+}
+
+static void __lpc_eth_clock_enable(struct netdata_local *pldat,
+				   bool enable)
+{
+	if (enable)
+		clk_enable(pldat->clk);
+	else
+		clk_disable(pldat->clk);
+}
+
+static void __lpc_params_setup(struct netdata_local *pldat)
+{
+	u32 tmp;
+
+	if (pldat->duplex == DUPLEX_FULL) {
+		tmp = readl(LPC_ENET_MAC2(pldat->net_base));
+		tmp |= LPC_MAC2_FULL_DUPLEX;
+		writel(tmp, LPC_ENET_MAC2(pldat->net_base));
+		tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+		tmp |= LPC_COMMAND_FULLDUPLEX;
+		writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base));
+	} else {
+		tmp = readl(LPC_ENET_MAC2(pldat->net_base));
+		tmp &= ~LPC_MAC2_FULL_DUPLEX;
+		writel(tmp, LPC_ENET_MAC2(pldat->net_base));
+		tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+		tmp &= ~LPC_COMMAND_FULLDUPLEX;
+		writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base));
+	}
+
+	if (pldat->speed == SPEED_100)
+		writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base));
+	else
+		writel(0, LPC_ENET_SUPP(pldat->net_base));
+}
+
+static void __lpc_eth_reset(struct netdata_local *pldat)
+{
+	/* Reset all MAC logic */
+	writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX |
+		LPC_MAC1_RESET_MCS_RX | LPC_MAC1_SIMULATION_RESET |
+		LPC_MAC1_SOFT_RESET), LPC_ENET_MAC1(pldat->net_base));
+	writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET |
+		LPC_COMMAND_RXRESET), LPC_ENET_COMMAND(pldat->net_base));
+}
+
+static int __lpc_mii_mngt_reset(struct netdata_local *pldat)
+{
+	/* Reset MII management hardware */
+	writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base));
+
+	/* Setup MII clock to slowest rate with a /28 divider */
+	writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28),
+	       LPC_ENET_MCFG(pldat->net_base));
+
+	return 0;
+}
+
+static inline phys_addr_t __va_to_pa(void *addr, struct netdata_local *pldat)
+{
+	phys_addr_t phaddr;
+
+	phaddr = addr - pldat->dma_buff_base_v;
+	phaddr += pldat->dma_buff_base_p;
+
+	return phaddr;
+}
+
+static void lpc_eth_enable_int(void __iomem *regbase)
+{
+	writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN),
+	       LPC_ENET_INTENABLE(regbase));
+}
+
+static void lpc_eth_disable_int(void __iomem *regbase)
+{
+	writel(0, LPC_ENET_INTENABLE(regbase));
+}
+
+/* Setup TX/RX descriptors */
+static void __lpc_txrx_desc_setup(struct netdata_local *pldat)
+{
+	u32 *ptxstat;
+	void *tbuff;
+	int i;
+	struct txrx_desc_t *ptxrxdesc;
+	struct rx_status_t *prxstat;
+
+	tbuff = PTR_ALIGN(pldat->dma_buff_base_v, 16);
+
+	/* Setup TX descriptors, status, and buffers */
+	pldat->tx_desc_v = tbuff;
+	tbuff += sizeof(struct txrx_desc_t) * ENET_TX_DESC;
+
+	pldat->tx_stat_v = tbuff;
+	tbuff += sizeof(u32) * ENET_TX_DESC;
+
+	tbuff = PTR_ALIGN(tbuff, 16);
+	pldat->tx_buff_v = tbuff;
+	tbuff += ENET_MAXF_SIZE * ENET_TX_DESC;
+
+	/* Setup RX descriptors, status, and buffers */
+	pldat->rx_desc_v = tbuff;
+	tbuff += sizeof(struct txrx_desc_t) * ENET_RX_DESC;
+
+	tbuff = PTR_ALIGN(tbuff, 16);
+	pldat->rx_stat_v = tbuff;
+	tbuff += sizeof(struct rx_status_t) * ENET_RX_DESC;
+
+	tbuff = PTR_ALIGN(tbuff, 16);
+	pldat->rx_buff_v = tbuff;
+	tbuff += ENET_MAXF_SIZE * ENET_RX_DESC;
+
+	/* Map the TX descriptors to the TX buffers in hardware */
+	for (i = 0; i < ENET_TX_DESC; i++) {
+		ptxstat = &pldat->tx_stat_v[i];
+		ptxrxdesc = &pldat->tx_desc_v[i];
+
+		ptxrxdesc->packet = __va_to_pa(
+				pldat->tx_buff_v + i * ENET_MAXF_SIZE, pldat);
+		ptxrxdesc->control = 0;
+		*ptxstat = 0;
+	}
+
+	/* Map the RX descriptors to the RX buffers in hardware */
+	for (i = 0; i < ENET_RX_DESC; i++) {
+		prxstat = &pldat->rx_stat_v[i];
+		ptxrxdesc = &pldat->rx_desc_v[i];
+
+		ptxrxdesc->packet = __va_to_pa(
+				pldat->rx_buff_v + i * ENET_MAXF_SIZE, pldat);
+		ptxrxdesc->control = RXDESC_CONTROL_INT | (ENET_MAXF_SIZE - 1);
+		prxstat->statusinfo = 0;
+		prxstat->statushashcrc = 0;
+	}
+
+	/* Setup base addresses in hardware to point to buffers and
+	 * descriptors
+	 */
+	writel((ENET_TX_DESC - 1),
+	       LPC_ENET_TXDESCRIPTORNUMBER(pldat->net_base));
+	writel(__va_to_pa(pldat->tx_desc_v, pldat),
+	       LPC_ENET_TXDESCRIPTOR(pldat->net_base));
+	writel(__va_to_pa(pldat->tx_stat_v, pldat),
+	       LPC_ENET_TXSTATUS(pldat->net_base));
+	writel((ENET_RX_DESC - 1),
+	       LPC_ENET_RXDESCRIPTORNUMBER(pldat->net_base));
+	writel(__va_to_pa(pldat->rx_desc_v, pldat),
+	       LPC_ENET_RXDESCRIPTOR(pldat->net_base));
+	writel(__va_to_pa(pldat->rx_stat_v, pldat),
+	       LPC_ENET_RXSTATUS(pldat->net_base));
+}
+
+static void __lpc_eth_init(struct netdata_local *pldat)
+{
+	u32 tmp;
+
+	/* Disable controller and reset */
+	tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+	tmp &= ~LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
+	writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+	tmp = readl(LPC_ENET_MAC1(pldat->net_base));
+	tmp &= ~LPC_MAC1_RECV_ENABLE;
+	writel(tmp, LPC_ENET_MAC1(pldat->net_base));
+
+	/* Initial MAC setup */
+	writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base));
+	writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE),
+	       LPC_ENET_MAC2(pldat->net_base));
+	writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base));
+
+	/* Collision window, gap */
+	writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) |
+		LPC_CLRT_LOAD_COLLISION_WINDOW(0x37)),
+	       LPC_ENET_CLRT(pldat->net_base));
+	writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base));
+
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		writel(LPC_COMMAND_PASSRUNTFRAME,
+		       LPC_ENET_COMMAND(pldat->net_base));
+	else {
+		writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
+		       LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
+	}
+
+	__lpc_params_setup(pldat);
+
+	/* Setup TX and RX descriptors */
+	__lpc_txrx_desc_setup(pldat);
+
+	/* Setup packet filtering */
+	writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT),
+	       LPC_ENET_RXFILTER_CTRL(pldat->net_base));
+
+	/* Get the next TX buffer output index */
+	pldat->num_used_tx_buffs = 0;
+	pldat->last_tx_idx =
+		readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+
+	/* Clear and enable interrupts */
+	writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
+	smp_wmb();
+	lpc_eth_enable_int(pldat->net_base);
+
+	/* Enable controller */
+	tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
+	tmp |= LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
+	writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
+	tmp = readl(LPC_ENET_MAC1(pldat->net_base));
+	tmp |= LPC_MAC1_RECV_ENABLE;
+	writel(tmp, LPC_ENET_MAC1(pldat->net_base));
+}
+
+static void __lpc_eth_shutdown(struct netdata_local *pldat)
+{
+	/* Reset ethernet and power down PHY */
+	__lpc_eth_reset(pldat);
+	writel(0, LPC_ENET_MAC1(pldat->net_base));
+	writel(0, LPC_ENET_MAC2(pldat->net_base));
+}
+
+/*
+ * MAC<--->PHY support functions
+ */
+static int lpc_mdio_read(struct mii_bus *bus, int phy_id, int phyreg)
+{
+	struct netdata_local *pldat = bus->priv;
+	unsigned long timeout = jiffies + msecs_to_jiffies(100);
+	int lps;
+
+	writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
+	writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base));
+
+	/* Wait for unbusy status */
+	while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
+		if (time_after(jiffies, timeout))
+			return -EIO;
+		cpu_relax();
+	}
+
+	lps = readl(LPC_ENET_MRDD(pldat->net_base));
+	writel(0, LPC_ENET_MCMD(pldat->net_base));
+
+	return lps;
+}
+
+static int lpc_mdio_write(struct mii_bus *bus, int phy_id, int phyreg,
+			u16 phydata)
+{
+	struct netdata_local *pldat = bus->priv;
+	unsigned long timeout = jiffies + msecs_to_jiffies(100);
+
+	writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
+	writel(phydata, LPC_ENET_MWTD(pldat->net_base));
+
+	/* Wait for completion */
+	while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
+		if (time_after(jiffies, timeout))
+			return -EIO;
+		cpu_relax();
+	}
+
+	return 0;
+}
+
+static int lpc_mdio_reset(struct mii_bus *bus)
+{
+	return __lpc_mii_mngt_reset((struct netdata_local *)bus->priv);
+}
+
+static void lpc_handle_link_change(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+	unsigned long flags;
+
+	bool status_change = false;
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	if (phydev->link) {
+		if ((pldat->speed != phydev->speed) ||
+		    (pldat->duplex != phydev->duplex)) {
+			pldat->speed = phydev->speed;
+			pldat->duplex = phydev->duplex;
+			status_change = true;
+		}
+	}
+
+	if (phydev->link != pldat->link) {
+		if (!phydev->link) {
+			pldat->speed = 0;
+			pldat->duplex = -1;
+		}
+		pldat->link = phydev->link;
+
+		status_change = true;
+	}
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	if (status_change)
+		__lpc_params_setup(pldat);
+}
+
+static int lpc_mii_probe(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = phy_find_first(pldat->mii_bus);
+
+	if (!phydev) {
+		netdev_err(ndev, "no PHY found\n");
+		return -ENODEV;
+	}
+
+	/* Attach to the PHY */
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		netdev_info(ndev, "using MII interface\n");
+	else
+		netdev_info(ndev, "using RMII interface\n");
+	phydev = phy_connect(ndev, dev_name(&phydev->dev),
+		&lpc_handle_link_change, 0, lpc_phy_interface_mode());
+
+	if (IS_ERR(phydev)) {
+		netdev_err(ndev, "Could not attach to PHY\n");
+		return PTR_ERR(phydev);
+	}
+
+	/* mask with MAC supported features */
+	phydev->supported &= PHY_BASIC_FEATURES;
+
+	phydev->advertising = phydev->supported;
+
+	pldat->link = 0;
+	pldat->speed = 0;
+	pldat->duplex = -1;
+	pldat->phy_dev = phydev;
+
+	netdev_info(ndev,
+		"attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
+		phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
+	return 0;
+}
+
+static int lpc_mii_init(struct netdata_local *pldat)
+{
+	int err = -ENXIO, i;
+
+	pldat->mii_bus = mdiobus_alloc();
+	if (!pldat->mii_bus) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	/* Setup MII mode */
+	if (lpc_phy_interface_mode() == PHY_INTERFACE_MODE_MII)
+		writel(LPC_COMMAND_PASSRUNTFRAME,
+		       LPC_ENET_COMMAND(pldat->net_base));
+	else {
+		writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
+		       LPC_ENET_COMMAND(pldat->net_base));
+		writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
+	}
+
+	pldat->mii_bus->name = "lpc_mii_bus";
+	pldat->mii_bus->read = &lpc_mdio_read;
+	pldat->mii_bus->write = &lpc_mdio_write;
+	pldat->mii_bus->reset = &lpc_mdio_reset;
+	snprintf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+		 pldat->pdev->name, pldat->pdev->id);
+	pldat->mii_bus->priv = pldat;
+	pldat->mii_bus->parent = &pldat->pdev->dev;
+
+	pldat->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+	if (!pldat->mii_bus->irq) {
+		err = -ENOMEM;
+		goto err_out_1;
+	}
+
+	for (i = 0; i < PHY_MAX_ADDR; i++)
+		pldat->mii_bus->irq[i] = PHY_POLL;
+
+	platform_set_drvdata(pldat->pdev, pldat->mii_bus);
+
+	if (mdiobus_register(pldat->mii_bus))
+		goto err_out_free_mdio_irq;
+
+	if (lpc_mii_probe(pldat->ndev) != 0)
+		goto err_out_unregister_bus;
+
+	return 0;
+
+err_out_unregister_bus:
+	mdiobus_unregister(pldat->mii_bus);
+err_out_free_mdio_irq:
+	kfree(pldat->mii_bus->irq);
+err_out_1:
+	mdiobus_free(pldat->mii_bus);
+err_out:
+	return err;
+}
+
+static void __lpc_handle_xmit(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct sk_buff *skb;
+	u32 txcidx, *ptxstat, txstat;
+
+	txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+	while (pldat->last_tx_idx != txcidx) {
+		skb = pldat->skb[pldat->last_tx_idx];
+
+		/* A buffer is available, get buffer status */
+		ptxstat = &pldat->tx_stat_v[pldat->last_tx_idx];
+		txstat = *ptxstat;
+
+		/* Next buffer and decrement used buffer counter */
+		pldat->num_used_tx_buffs--;
+		pldat->last_tx_idx++;
+		if (pldat->last_tx_idx >= ENET_TX_DESC)
+			pldat->last_tx_idx = 0;
+
+		/* Update collision counter */
+		ndev->stats.collisions += TXSTATUS_COLLISIONS_GET(txstat);
+
+		/* Any errors occurred? */
+		if (txstat & TXSTATUS_ERROR) {
+			if (txstat & TXSTATUS_UNDERRUN) {
+				/* FIFO underrun */
+				ndev->stats.tx_fifo_errors++;
+			}
+			if (txstat & TXSTATUS_LATECOLL) {
+				/* Late collision */
+				ndev->stats.tx_aborted_errors++;
+			}
+			if (txstat & TXSTATUS_EXCESSCOLL) {
+				/* Excessive collision */
+				ndev->stats.tx_aborted_errors++;
+			}
+			if (txstat & TXSTATUS_EXCESSDEFER) {
+				/* Defer limit */
+				ndev->stats.tx_aborted_errors++;
+			}
+			ndev->stats.tx_errors++;
+		} else {
+			/* Update stats */
+			ndev->stats.tx_packets++;
+			ndev->stats.tx_bytes += skb->len;
+
+			/* Free buffer */
+			dev_kfree_skb_irq(skb);
+		}
+
+		txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
+	}
+
+	if (netif_queue_stopped(ndev))
+		netif_wake_queue(ndev);
+}
+
+static int __lpc_handle_recv(struct net_device *ndev, int budget)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct sk_buff *skb;
+	u32 rxconsidx, len, ethst;
+	struct rx_status_t *prxstat;
+	u8 *prdbuf;
+	int rx_done = 0;
+
+	/* Get the current RX buffer indexes */
+	rxconsidx = readl(LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
+	while (rx_done < budget && rxconsidx !=
+			readl(LPC_ENET_RXPRODUCEINDEX(pldat->net_base))) {
+		/* Get pointer to receive status */
+		prxstat = &pldat->rx_stat_v[rxconsidx];
+		len = (prxstat->statusinfo & RXSTATUS_SIZE) + 1;
+
+		/* Status error? */
+		ethst = prxstat->statusinfo;
+		if ((ethst & (RXSTATUS_ERROR | RXSTATUS_STATUS_ERROR)) ==
+		    (RXSTATUS_ERROR | RXSTATUS_RANGE))
+			ethst &= ~RXSTATUS_ERROR;
+
+		if (ethst & RXSTATUS_ERROR) {
+			int si = prxstat->statusinfo;
+			/* Check statuses */
+			if (si & RXSTATUS_OVERRUN) {
+				/* Overrun error */
+				ndev->stats.rx_fifo_errors++;
+			} else if (si & RXSTATUS_CRC) {
+				/* CRC error */
+				ndev->stats.rx_crc_errors++;
+			} else if (si & RXSTATUS_LENGTH) {
+				/* Length error */
+				ndev->stats.rx_length_errors++;
+			} else if (si & RXSTATUS_ERROR) {
+				/* Other error */
+				ndev->stats.rx_length_errors++;
+			}
+			ndev->stats.rx_errors++;
+		} else {
+			/* Packet is good */
+			skb = dev_alloc_skb(len + 8);
+			if (!skb)
+				ndev->stats.rx_dropped++;
+			else {
+				prdbuf = skb_put(skb, len);
+
+				/* Copy packet from buffer */
+				memcpy(prdbuf, pldat->rx_buff_v +
+					rxconsidx * ENET_MAXF_SIZE, len);
+
+				/* Pass to upper layer */
+				skb->protocol = eth_type_trans(skb, ndev);
+				netif_receive_skb(skb);
+				ndev->stats.rx_packets++;
+				ndev->stats.rx_bytes += len;
+			}
+		}
+
+		/* Increment consume index */
+		rxconsidx = rxconsidx + 1;
+		if (rxconsidx >= ENET_RX_DESC)
+			rxconsidx = 0;
+		writel(rxconsidx,
+		       LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
+		rx_done++;
+	}
+
+	return rx_done;
+}
+
+static int lpc_eth_poll(struct napi_struct *napi, int budget)
+{
+	struct netdata_local *pldat = container_of(napi,
+			struct netdata_local, napi);
+	struct net_device *ndev = pldat->ndev;
+	int rx_done = 0;
+	struct netdev_queue *txq = netdev_get_tx_queue(ndev, 0);
+
+	__netif_tx_lock(txq, smp_processor_id());
+	__lpc_handle_xmit(ndev);
+	__netif_tx_unlock(txq);
+	rx_done = __lpc_handle_recv(ndev, budget);
+
+	if (rx_done < budget) {
+		napi_complete(napi);
+		lpc_eth_enable_int(pldat->net_base);
+	}
+
+	return rx_done;
+}
+
+static irqreturn_t __lpc_eth_interrupt(int irq, void *dev_id)
+{
+	struct net_device *ndev = dev_id;
+	struct netdata_local *pldat = netdev_priv(ndev);
+	u32 tmp;
+
+	spin_lock(&pldat->lock);
+
+	tmp = readl(LPC_ENET_INTSTATUS(pldat->net_base));
+	/* Clear interrupts */
+	writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base));
+
+	lpc_eth_disable_int(pldat->net_base);
+	if (likely(napi_schedule_prep(&pldat->napi)))
+		__napi_schedule(&pldat->napi);
+
+	spin_unlock(&pldat->lock);
+
+	return IRQ_HANDLED;
+}
+
+static int lpc_eth_close(struct net_device *ndev)
+{
+	unsigned long flags;
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	if (netif_msg_ifdown(pldat))
+		dev_dbg(&pldat->pdev->dev, "shutting down %s\n", ndev->name);
+
+	napi_disable(&pldat->napi);
+	netif_stop_queue(ndev);
+
+	if (pldat->phy_dev)
+		phy_stop(pldat->phy_dev);
+
+	spin_lock_irqsave(&pldat->lock, flags);
+	__lpc_eth_reset(pldat);
+	netif_carrier_off(ndev);
+	writel(0, LPC_ENET_MAC1(pldat->net_base));
+	writel(0, LPC_ENET_MAC2(pldat->net_base));
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	__lpc_eth_clock_enable(pldat, false);
+
+	return 0;
+}
+
+static int lpc_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	u32 len, txidx;
+	u32 *ptxstat;
+	struct txrx_desc_t *ptxrxdesc;
+
+	len = skb->len;
+
+	spin_lock_irq(&pldat->lock);
+
+	if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) {
+		/* This function should never be called when there are no
+		   buffers */
+		netif_stop_queue(ndev);
+		spin_unlock_irq(&pldat->lock);
+		WARN(1, "BUG! TX request when no free TX buffers!\n");
+		return NETDEV_TX_BUSY;
+	}
+
+	/* Get the next TX descriptor index */
+	txidx = readl(LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
+
+	/* Setup control for the transfer */
+	ptxstat = &pldat->tx_stat_v[txidx];
+	*ptxstat = 0;
+	ptxrxdesc = &pldat->tx_desc_v[txidx];
+	ptxrxdesc->control =
+		(len - 1) | TXDESC_CONTROL_LAST | TXDESC_CONTROL_INT;
+
+	/* Copy data to the DMA buffer */
+	memcpy(pldat->tx_buff_v + txidx * ENET_MAXF_SIZE, skb->data, len);
+
+	/* Save the buffer and increment the buffer counter */
+	pldat->skb[txidx] = skb;
+	pldat->num_used_tx_buffs++;
+
+	/* Start transmit */
+	txidx++;
+	if (txidx >= ENET_TX_DESC)
+		txidx = 0;
+	writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
+
+	/* Stop queue if no more TX buffers */
+	if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1))
+		netif_stop_queue(ndev);
+
+	spin_unlock_irq(&pldat->lock);
+
+	return NETDEV_TX_OK;
+}
+
+static int lpc_set_mac_address(struct net_device *ndev, void *p)
+{
+	struct sockaddr *addr = p;
+	struct netdata_local *pldat = netdev_priv(ndev);
+	unsigned long flags;
+
+	if (!is_valid_ether_addr(addr->sa_data))
+		return -EADDRNOTAVAIL;
+	memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	/* Set station address */
+	__lpc_set_mac(pldat, ndev->dev_addr);
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+
+	return 0;
+}
+
+static void lpc_eth_set_multicast_list(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct netdev_hw_addr_list *mcptr = &ndev->mc;
+	struct netdev_hw_addr *ha;
+	u32 tmp32, hash_val, hashlo, hashhi;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pldat->lock, flags);
+
+	/* Set station address */
+	__lpc_set_mac(pldat, ndev->dev_addr);
+
+	tmp32 =  LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT;
+
+	if (ndev->flags & IFF_PROMISC)
+		tmp32 |= LPC_RXFLTRW_ACCEPTUNICAST |
+			LPC_RXFLTRW_ACCEPTUMULTICAST;
+	if (ndev->flags & IFF_ALLMULTI)
+		tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICAST;
+
+	if (netdev_hw_addr_list_count(mcptr))
+		tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICASTHASH;
+
+	writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base));
+
+
+	/* Set initial hash table */
+	hashlo = 0x0;
+	hashhi = 0x0;
+
+	/* 64 bits : multicast address in hash table */
+	netdev_hw_addr_list_for_each(ha, mcptr) {
+		hash_val = (ether_crc(6, ha->addr) >> 23) & 0x3F;
+
+		if (hash_val >= 32)
+			hashhi |= 1 << (hash_val - 32);
+		else
+			hashlo |= 1 << hash_val;
+	}
+
+	writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base));
+	writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base));
+
+	spin_unlock_irqrestore(&pldat->lock, flags);
+}
+
+static int lpc_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!netif_running(ndev))
+		return -EINVAL;
+
+	if (!phydev)
+		return -ENODEV;
+
+	return phy_mii_ioctl(phydev, req, cmd);
+}
+
+static int lpc_eth_open(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	if (netif_msg_ifup(pldat))
+		dev_dbg(&pldat->pdev->dev, "enabling %s\n", ndev->name);
+
+	if (!is_valid_ether_addr(ndev->dev_addr))
+		return -EADDRNOTAVAIL;
+
+	__lpc_eth_clock_enable(pldat, true);
+
+	/* Reset and initialize */
+	__lpc_eth_reset(pldat);
+	__lpc_eth_init(pldat);
+
+	/* schedule a link state check */
+	phy_start(pldat->phy_dev);
+	netif_start_queue(ndev);
+	napi_enable(&pldat->napi);
+
+	return 0;
+}
+
+/*
+ * Ethtool ops
+ */
+static void lpc_eth_ethtool_getdrvinfo(struct net_device *ndev,
+	struct ethtool_drvinfo *info)
+{
+	strcpy(info->driver, MODNAME);
+	strcpy(info->version, DRV_VERSION);
+	strcpy(info->bus_info, dev_name(ndev->dev.parent));
+}
+
+static u32 lpc_eth_ethtool_getmsglevel(struct net_device *ndev)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	return pldat->msg_enable;
+}
+
+static void lpc_eth_ethtool_setmsglevel(struct net_device *ndev, u32 level)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	pldat->msg_enable = level;
+}
+
+static int lpc_eth_ethtool_getsettings(struct net_device *ndev,
+	struct ethtool_cmd *cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!phydev)
+		return -EOPNOTSUPP;
+
+	return phy_ethtool_gset(phydev, cmd);
+}
+
+static int lpc_eth_ethtool_setsettings(struct net_device *ndev,
+	struct ethtool_cmd *cmd)
+{
+	struct netdata_local *pldat = netdev_priv(ndev);
+	struct phy_device *phydev = pldat->phy_dev;
+
+	if (!phydev)
+		return -EOPNOTSUPP;
+
+	return phy_ethtool_sset(phydev, cmd);
+}
+
+static const struct ethtool_ops lpc_eth_ethtool_ops = {
+	.get_drvinfo	= lpc_eth_ethtool_getdrvinfo,
+	.get_settings	= lpc_eth_ethtool_getsettings,
+	.set_settings	= lpc_eth_ethtool_setsettings,
+	.get_msglevel	= lpc_eth_ethtool_getmsglevel,
+	.set_msglevel	= lpc_eth_ethtool_setmsglevel,
+	.get_link	= ethtool_op_get_link,
+};
+
+static const struct net_device_ops lpc_netdev_ops = {
+	.ndo_open		= lpc_eth_open,
+	.ndo_stop		= lpc_eth_close,
+	.ndo_start_xmit		= lpc_eth_hard_start_xmit,
+	.ndo_set_rx_mode	= lpc_eth_set_multicast_list,
+	.ndo_do_ioctl		= lpc_eth_ioctl,
+	.ndo_set_mac_address	= lpc_set_mac_address,
+};
+
+static int lpc_eth_drv_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct resource *dma_res;
+	struct net_device *ndev;
+	struct netdata_local *pldat;
+	struct phy_device *phydev;
+	dma_addr_t dma_handle;
+	int irq, ret;
+
+	/* Get platform resources */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	irq = platform_get_irq(pdev, 0);
+	if ((!res) || (!dma_res) || (irq < 0) || (irq >= NR_IRQS)) {
+		dev_err(&pdev->dev, "error getting resources.\n");
+		ret = -ENXIO;
+		goto err_exit;
+	}
+
+	/* Allocate net driver data structure */
+	ndev = alloc_etherdev(sizeof(struct netdata_local));
+	if (!ndev) {
+		dev_err(&pdev->dev, "could not allocate device.\n");
+		ret = -ENOMEM;
+		goto err_exit;
+	}
+
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	pldat = netdev_priv(ndev);
+	pldat->pdev = pdev;
+	pldat->ndev = ndev;
+
+	spin_lock_init(&pldat->lock);
+
+	/* Save resources */
+	ndev->irq = irq;
+
+	/* Get clock for the device */
+	pldat->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(pldat->clk)) {
+		dev_err(&pdev->dev, "error getting clock.\n");
+		ret = PTR_ERR(pldat->clk);
+		goto err_out_free_dev;
+	}
+
+	/* Enable network clock */
+	__lpc_eth_clock_enable(pldat, true);
+
+	/* Map IO space */
+	pldat->net_base = ioremap(res->start, res->end - res->start + 1);
+	if (!pldat->net_base) {
+		dev_err(&pdev->dev, "failed to map registers\n");
+		ret = -ENOMEM;
+		goto err_out_disable_clocks;
+	}
+	ret = request_irq(ndev->irq, __lpc_eth_interrupt, 0,
+			  ndev->name, ndev);
+	if (ret) {
+		dev_err(&pdev->dev, "error requesting interrupt.\n");
+		goto err_out_iounmap;
+	}
+
+	/* Fill in the fields of the device structure with ethernet values. */
+	ether_setup(ndev);
+
+	/* Setup driver functions */
+	ndev->netdev_ops = &lpc_netdev_ops;
+	ndev->ethtool_ops = &lpc_eth_ethtool_ops;
+	ndev->watchdog_timeo = msecs_to_jiffies(2500);
+
+	/* Get size of DMA buffers/descriptors region */
+	pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE +
+		sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
+	pldat->dma_buff_base_v = 0;
+
+	if (use_iram_for_net()) {
+		dma_handle = dma_res->start;
+		if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
+			pldat->dma_buff_base_v =
+				io_p2v(dma_res->start);
+		else
+			netdev_err(ndev,
+				"IRAM not big enough for net buffers, using SDRAM instead.\n");
+	}
+
+	if (pldat->dma_buff_base_v == 0) {
+		pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size);
+
+		/* Allocate a chunk of memory for the DMA ethernet buffers
+		   and descriptors */
+		pldat->dma_buff_base_v =
+			dma_alloc_coherent(&pldat->pdev->dev,
+					   pldat->dma_buff_size, &dma_handle,
+					   GFP_KERNEL);
+
+		if (pldat->dma_buff_base_v == NULL) {
+			dev_err(&pdev->dev, "error getting DMA region.\n");
+			ret = -ENOMEM;
+			goto err_out_free_irq;
+		}
+	}
+	pldat->dma_buff_base_p = dma_handle;
+
+	netdev_dbg(ndev, "IO address start     :0x%08x\n",
+			res->start);
+	netdev_dbg(ndev, "IO address size      :%d\n",
+			res->end - res->start + 1);
+	netdev_err(ndev, "IO address (mapped)  :0x%p\n",
+			pldat->net_base);
+	netdev_dbg(ndev, "IRQ number           :%d\n", ndev->irq);
+	netdev_dbg(ndev, "DMA buffer size      :%d\n", pldat->dma_buff_size);
+	netdev_dbg(ndev, "DMA buffer P address :0x%08x\n",
+			pldat->dma_buff_base_p);
+	netdev_dbg(ndev, "DMA buffer V address :0x%p\n",
+			pldat->dma_buff_base_v);
+
+	/* Get MAC address from current HW setting (POR state is all zeros) */
+	__lpc_get_mac(pldat, ndev->dev_addr);
+
+#ifdef CONFIG_OF_NET
+	if (!is_valid_ether_addr(ndev->dev_addr)) {
+		const char *macaddr = of_get_mac_address(pdev->dev.of_node);
+		if (macaddr)
+			memcpy(ndev->dev_addr, macaddr, ETH_ALEN);
+	}
+#endif
+	if (!is_valid_ether_addr(ndev->dev_addr))
+		dev_hw_addr_random(ndev, ndev->dev_addr);
+
+	/* Reset the ethernet controller */
+	__lpc_eth_reset(pldat);
+
+	/* then shut everything down to save power */
+	__lpc_eth_shutdown(pldat);
+
+	/* Set default parameters */
+	pldat->msg_enable = NETIF_MSG_LINK;
+
+	/* Force an MII interface reset and clock setup */
+	__lpc_mii_mngt_reset(pldat);
+
+	/* Force default PHY interface setup in chip, this will probably be
+	   changed by the PHY driver */
+	pldat->link = 0;
+	pldat->speed = 100;
+	pldat->duplex = DUPLEX_FULL;
+	__lpc_params_setup(pldat);
+
+	netif_napi_add(ndev, &pldat->napi, lpc_eth_poll, NAPI_WEIGHT);
+
+	ret = register_netdev(ndev);
+	if (ret) {
+		dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
+		goto err_out_dma_unmap;
+	}
+	platform_set_drvdata(pdev, ndev);
+
+	if (lpc_mii_init(pldat) != 0)
+		goto err_out_unregister_netdev;
+
+	netdev_info(ndev, "LPC mac at 0x%08x irq %d\n",
+	       res->start, ndev->irq);
+
+	phydev = pldat->phy_dev;
+
+	device_init_wakeup(&pdev->dev, 1);
+	device_set_wakeup_enable(&pdev->dev, 0);
+
+	return 0;
+
+err_out_unregister_netdev:
+	platform_set_drvdata(pdev, NULL);
+	unregister_netdev(ndev);
+err_out_dma_unmap:
+	if (!use_iram_for_net() ||
+	    pldat->dma_buff_size > lpc32xx_return_iram_size())
+		dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
+				  pldat->dma_buff_base_v,
+				  pldat->dma_buff_base_p);
+err_out_free_irq:
+	free_irq(ndev->irq, ndev);
+err_out_iounmap:
+	iounmap(pldat->net_base);
+err_out_disable_clocks:
+	clk_disable(pldat->clk);
+	clk_put(pldat->clk);
+err_out_free_dev:
+	free_netdev(ndev);
+err_exit:
+	pr_err("%s: not found (%d).\n", MODNAME, ret);
+	return ret;
+}
+
+static int lpc_eth_drv_remove(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	unregister_netdev(ndev);
+	platform_set_drvdata(pdev, NULL);
+
+	if (!use_iram_for_net() ||
+	    pldat->dma_buff_size > lpc32xx_return_iram_size())
+		dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
+				  pldat->dma_buff_base_v,
+				  pldat->dma_buff_base_p);
+	free_irq(ndev->irq, ndev);
+	iounmap(pldat->net_base);
+	mdiobus_free(pldat->mii_bus);
+	clk_disable(pldat->clk);
+	clk_put(pldat->clk);
+	free_netdev(ndev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int lpc_eth_drv_suspend(struct platform_device *pdev,
+	pm_message_t state)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat = netdev_priv(ndev);
+
+	if (device_may_wakeup(&pdev->dev))
+		enable_irq_wake(ndev->irq);
+
+	if (ndev) {
+		if (netif_running(ndev)) {
+			netif_device_detach(ndev);
+			__lpc_eth_shutdown(pldat);
+			clk_disable(pldat->clk);
+
+			/*
+			 * Reset again now clock is disable to be sure
+			 * EMC_MDC is down
+			 */
+			__lpc_eth_reset(pldat);
+		}
+	}
+
+	return 0;
+}
+
+static int lpc_eth_drv_resume(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct netdata_local *pldat;
+
+	if (device_may_wakeup(&pdev->dev))
+		disable_irq_wake(ndev->irq);
+
+	if (ndev) {
+		if (netif_running(ndev)) {
+			pldat = netdev_priv(ndev);
+
+			/* Enable interface clock */
+			clk_enable(pldat->clk);
+
+			/* Reset and initialize */
+			__lpc_eth_reset(pldat);
+			__lpc_eth_init(pldat);
+
+			netif_device_attach(ndev);
+		}
+	}
+
+	return 0;
+}
+#endif
+
+static struct platform_driver lpc_eth_driver = {
+	.probe		= lpc_eth_drv_probe,
+	.remove		= __devexit_p(lpc_eth_drv_remove),
+#ifdef CONFIG_PM
+	.suspend	= lpc_eth_drv_suspend,
+	.resume		= lpc_eth_drv_resume,
+#endif
+	.driver		= {
+		.name	= MODNAME,
+	},
+};
+
+module_platform_driver(lpc_eth_driver);
+
+MODULE_AUTHOR("Kevin Wells <kevin.wells at nxp.com>");
+MODULE_AUTHOR("Roland Stigge <stigge at antcom.de>");
+MODULE_DESCRIPTION("LPC Ethernet Driver");
+MODULE_LICENSE("GPL");


From jason at lakedaemon.net  Thu Mar  8 16:50:48 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 8 Mar 2012 16:50:48 -0500
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <20120308213244.GD16533@ponder.secretlab.ca>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203072113.04369.arnd@arndb.de>
 <20120308162530.GI5050@titan.lakedaemon.net>
 <201203081701.01663.arnd@arndb.de>
 <alpine.LFD.2.02.1203082026470.2742@ionos>
 <20120308194725.GM5050@titan.lakedaemon.net>
 <20120308213244.GD16533@ponder.secretlab.ca>
Message-ID: <20120308215048.GN5050@titan.lakedaemon.net>

On Thu, Mar 08, 2012 at 02:32:44PM -0700, Grant Likely wrote:
> On Thu, Mar 08, 2012 at 02:47:25PM -0500, Jason wrote:
> > On Thu, Mar 08, 2012 at 08:27:11PM +0100, Thomas Gleixner wrote:
> > > On Thu, 8 Mar 2012, Arnd Bergmann wrote:
> > > 
> > > > On Thursday 08 March 2012, Jason wrote:
> > > > > 
> > > > > On Wed, Mar 07, 2012 at 09:13:04PM +0000, Arnd Bergmann wrote:
> > > > > > Finally, something could be wrong with the interrupt controller.
> > > > > > AFAICT, you register it through the device tree now, but it's also
> > > > > > getting initialized through kirkwood_init_irq, so the numbers
> > > > > > would all be wrong.
> > > > > 
> > > > > Yes, I'm working through this now.  mv_cesa silently fails to come up
> > > > > if it can't find the interrupt controller via fdt.  So, it needs to get
> > > > > done.
> > > > > 
> > > > > Right now, I'm looking at how mach-versatile does it (vic_init()) since
> > > > > it's also an ARM926ej-s...
> > > > > 
> > > > 
> > > > Ok, sounds good. It's not important whether it's an ARM9 or not btw.
> > > > You should look at both anything that defines an "interrupt-controller"
> > > > property as an example including Documentation/devicetree/bindings/arm/vic.txt
> > > > and Documentation/devicetree/bindings/arm/gic.txt.
> > > > 
> > > > (taking Thomas Gleixner on Cc)
> > > > 
> > > > Since the orion irq chip is based on irqchip_generic, it would be
> > > > perfect to have a generic irqchip binding to go along with
> > > > kernel/irq/generic-chip.c. Not sure if anyone has thought about this
> > > > before, but it looks like we can completely avoid using
> > > > arch/arm/plat-orion/irq.c and arch/arm/mach-kirkwood/irq.c if we
> > > > do that.
> > > 
> > > Right. That should be trivial to implement.
> > 
> > ok, I'm on it.  kernel/irq/of_generic_irq.c sound good?
> 
> Rob Herring has done some work in this area.  Please coordinate with him.

Rob,

I'm attempting to convert mach-kirkwood boards over to devicetree,
starting with the dreamplug.

You can find my stable patches here:

git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_stable

and the stuff I'm still trying to figure out:

git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_staging

My next task looks like converting the irq code, since mv_cesa fails
silently without the interrupt-controller specified in the dtb.

The code I'm replacing can be found here:

arch/arm/mach-kirkwood/irq.c
arch/arm/plat-orion/irq.c

This is the first time I've attempted something like this, so any
pointers would be much appreciated.  Also, if there is anything I would
need to deconflict with, please let me know.

thx,

Jason.


From jason at lakedaemon.net  Thu Mar  8 16:55:50 2012
From: jason at lakedaemon.net (Jason)
Date: Thu, 8 Mar 2012 16:55:50 -0500
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <20120308213139.GC16533@ponder.secretlab.ca>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <80fb8cef577eee14364e95009f7a590fd9056ee3.1331090356.git.jason@lakedaemon.net>
 <201203071831.31738.arnd@arndb.de>
 <20120307192723.GE5050@titan.lakedaemon.net>
 <20120308213139.GC16533@ponder.secretlab.ca>
Message-ID: <20120308215550.GO5050@titan.lakedaemon.net>

On Thu, Mar 08, 2012 at 02:31:39PM -0700, Grant Likely wrote:
> On Wed, Mar 07, 2012 at 02:27:23PM -0500, Jason wrote:
> > On Wed, Mar 07, 2012 at 06:31:31PM +0000, Arnd Bergmann wrote:
> > > On Wednesday 07 March 2012, Jason Cooper wrote:
> > > > +       serial at f1012000 {
> > > > +               compatible = "ns16550a";
> > > > +               reg = <0xf1012000 0xff>;
> > > > +               reg-shift = <2>;
> > > > +               interrupts = <33>;
> > > > +               clock-frequency = <200000000>;
> > > > +       };
> > > 
> > > I just noticed that the length here should be inclusive, i.e. 0x100 not 0xff.
> > > This is different from the way we define resources in Linux.
> > 
> > Grrr.  Now I'm getting frustrated.  I'm trying to boot without
> > earlyprintk.  Evidently, something is wrong with the above, because the
> > device boots all the way up (blinky lights come on), but I get no
> > messages after the usual "Uncompressing Linux... done, booting the
> > kernel."
> > 
> > Here's my most recent attempt:
> > 
> 
> I see that you've resolved your problem, but some comments below on the
> device node:
> 
> >         serial at f1012000 {
> >                 device_type = "serial";
> 
> Never use device_type.  It should only ever appear in the memory node, and
> I plan to remove it from there too.
> 
> >                 compatible = "ns16550a";
> >                 reg = <0xf1012000 0x100>; /*phys addr*/
> >                 virt-reg = <0xfed12000>;  /*virt addr*/
> 
> Don't use virt-reg.  Nothing in the kernel uses it and the kernel will
> make it's own decision about virtual address mapping.
> 
> >                 reg-shift = <2>;
> >                 reg-io-width = <1>;
> 
> 1 is the default for reg-io-width.  No need to have this property.  It
> should only be used if the device requires 32 bit accesses.
> 
> >                 interrupts = <33>;
> >                 current-speed = <115200>;
> >                 interrupt-parent = <&intc>;
> >                 clock-frequency = <200000000>;
> >         };

Thanks, Grant.  I reverted all of those changes once I found the root of
my problem.

thx,

Jason.


From stigge at antcom.de  Thu Mar  8 17:01:00 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 08 Mar 2012 23:01:00 +0100
Subject: [PATCH RESEND v3] USB: Support for LPC32xx SoC
In-Reply-To: <20120308211120.GB21058@kroah.com>
References: <1331068913-9321-1-git-send-email-stigge@antcom.de>
 <20120308211120.GB21058@kroah.com>
Message-ID: <4F592C1C.1050909@antcom.de>

On 08/03/12 22:11, Greg Kroah-Hartman wrote:
>> -	pnx4008_unset_usb_bits();
>> +	if (machine_is_pnx4008())
>> +		pnx4008_unset_usb_bits();
> 
> How come some of these pnx4008_* functions you have wrapped in
> machine_is_pnx4008(), but not all of them?
> 
> Actually, why don't those functions do that kind of checking themselves,
> without having to do this before you call them each time?

Good idea, I moved the machine dependent execution of the bits()
functions into the functions.

The dependency is only in the bits functions because those are done via
interfaces not available on LPC. The other pnx4008 functions seem to be
mostly compatible.

Thanks for your notes!

Roland


From paul.gortmaker at windriver.com  Thu Mar  8 17:06:06 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Thu,  8 Mar 2012 17:06:06 -0500
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
Message-ID: <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>

Commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)

  "regulator: Remove support for supplies specified by struct device"

caused this file to break, since it was still relying on the
device field to be present.  Update them to use the new dev_name
entries instead.

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
CC: Mark Brown <broonie at opensource.wolfsonmicro.com>
---

[v2: replace dev with dev_name instead of just deleting dev.
 Note however there is dev_name overlap; not sure if that matters? ]

diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index c1b65da..0ffc100 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1083,19 +1083,19 @@ static void __init em_x270_userspace_consumers_init(void)
 }
 
 /* DA9030 related initializations */
-#define REGULATOR_CONSUMER(_name, _dev, _supply)			       \
+#define REGULATOR_CONSUMER(_name, _dev_name, _supply)		        \
 	static struct regulator_consumer_supply _name##_consumers[] = {	\
 		{							\
-			.dev = _dev,					\
+			.dev_name = _dev_name,				\
 			.supply = _supply,				\
 		},							\
 	}
 
-REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps");
+REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer", "vcc gps");
 REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
-REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
+REGULATOR_CONSUMER(ldo10, "pxa2xx-mci", "vcc sdio");
 REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
-REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
+REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer", "vcc gprs");
 REGULATOR_CONSUMER(buck2, NULL, "vcc_core");
 
 #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask)		\
-- 
1.7.9.1



From stigge at antcom.de  Thu Mar  8 17:09:34 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu,  8 Mar 2012 23:09:34 +0100
Subject: [PATCH v4] USB: Support for LPC32xx SoC
Message-ID: <1331244574-32570-1-git-send-email-stigge@antcom.de>

This patch adds OHCI support to the LPC32xx ARM platform

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 Applies to v3.3-rc6

 Since v3, only the machine_is_*() dependencies have been pulled into
 the machine dependent functions.

 Thanks to Greg Kroah-Hartman for reviewing!

 drivers/usb/host/ohci-hcd.c     |    5 +
 drivers/usb/host/ohci-pnx4008.c |  119 +++++++++++++++++++++++++++++-----------
 2 files changed, 94 insertions(+), 30 deletions(-)

--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1055,6 +1055,11 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
 #endif
 
+#ifdef CONFIG_ARCH_LPC32XX
+#include "ohci-pnx4008.c"
+#define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
+#endif
+
 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
 #include "ohci-da8xx.c"
 #define PLATFORM_DRIVER		ohci_hcd_da8xx_driver
--- linux-2.6.orig/drivers/usb/host/ohci-pnx4008.c
+++ linux-2.6/drivers/usb/host/ohci-pnx4008.c
@@ -22,6 +22,7 @@
 #include <linux/i2c.h>
 
 #include <mach/hardware.h>
+#include <asm/mach-types.h>
 #include <asm/io.h>
 
 #include <mach/platform.h>
@@ -143,7 +144,17 @@ static void i2c_write(u8 buf, u8 subaddr
 	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
 }
 
-static void isp1301_configure(void)
+static u16 i2c_read16(u8 subaddr)
+{
+	u16 data;
+
+	i2c_master_send(isp1301_i2c_client, &subaddr, 1);
+	i2c_master_recv(isp1301_i2c_client, (u8 *) &data, 2);
+
+	return data;
+}
+
+static void isp1301_configure_pnx4008(void)
 {
 	/* PNX4008 only supports DAT_SE0 USB mode */
 	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
@@ -166,7 +177,51 @@ static void isp1301_configure(void)
 		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
 	i2c_write(0xFF,
 		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+}
 
+static void isp1301_configure_lpc32xx(void)
+{
+	/* LPC32XX only supports DAT_SE0 USB mode */
+	/* This sequence is important */
+
+	/* Disable transparent UART mode first */
+	i2c_write(MC1_UART_EN, (ISP1301_I2C_MODE_CONTROL_1 |
+		ISP1301_I2C_REG_CLEAR_ADDR));
+
+	i2c_write(~MC1_SPEED_REG, (ISP1301_I2C_MODE_CONTROL_1 |
+		ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
+	i2c_write(~0,
+		(ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write((MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
+		ISP1301_I2C_MODE_CONTROL_2);
+	i2c_write(~0, (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(MC1_DAT_SE0, ISP1301_I2C_MODE_CONTROL_1);
+	i2c_write((OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
+		ISP1301_I2C_OTG_CONTROL_1);
+	i2c_write((OTG1_DM_PULLUP | OTG1_DP_PULLUP),
+		(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(~0,
+		 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(~0,
+		ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(~0,
+		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+
+	/* Enable usb_need_clk clock after transceiver is initialized */
+	__raw_writel((__raw_readl(USB_CTRL) | (1 << 22)), USB_CTRL);
+
+	printk(KERN_INFO "ISP1301 Vendor ID  : 0x%04x\n", i2c_read16(0x00));
+	printk(KERN_INFO "ISP1301 Product ID : 0x%04x\n", i2c_read16(0x02));
+	printk(KERN_INFO "ISP1301 Version ID : 0x%04x\n", i2c_read16(0x14));
+}
+
+static void isp1301_configure(void)
+{
+	if (machine_is_pnx4008())
+		isp1301_configure_pnx4008();
+	else
+		isp1301_configure_lpc32xx();
 }
 
 static inline void isp1301_vbus_on(void)
@@ -257,39 +312,43 @@ static const struct hc_driver ohci_pnx40
 
 static void pnx4008_set_usb_bits(void)
 {
-	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-	start_int_ack(SE_USB_OTG_ATX_INT_N);
-	start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-	start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-	start_int_ack(SE_USB_OTG_TIMER_INT);
-	start_int_umask(SE_USB_OTG_TIMER_INT);
-
-	start_int_set_rising_edge(SE_USB_I2C_INT);
-	start_int_ack(SE_USB_I2C_INT);
-	start_int_umask(SE_USB_I2C_INT);
-
-	start_int_set_rising_edge(SE_USB_INT);
-	start_int_ack(SE_USB_INT);
-	start_int_umask(SE_USB_INT);
-
-	start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-	start_int_ack(SE_USB_NEED_CLK_INT);
-	start_int_umask(SE_USB_NEED_CLK_INT);
-
-	start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-	start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+	if (machine_is_pnx4008()) {
+		start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
+		start_int_ack(SE_USB_OTG_ATX_INT_N);
+		start_int_umask(SE_USB_OTG_ATX_INT_N);
+
+		start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
+		start_int_ack(SE_USB_OTG_TIMER_INT);
+		start_int_umask(SE_USB_OTG_TIMER_INT);
+
+		start_int_set_rising_edge(SE_USB_I2C_INT);
+		start_int_ack(SE_USB_I2C_INT);
+		start_int_umask(SE_USB_I2C_INT);
+
+		start_int_set_rising_edge(SE_USB_INT);
+		start_int_ack(SE_USB_INT);
+		start_int_umask(SE_USB_INT);
+
+		start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
+		start_int_ack(SE_USB_NEED_CLK_INT);
+		start_int_umask(SE_USB_NEED_CLK_INT);
+
+		start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
+		start_int_ack(SE_USB_AHB_NEED_CLK_INT);
+		start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+	}
 }
 
 static void pnx4008_unset_usb_bits(void)
 {
-	start_int_mask(SE_USB_OTG_ATX_INT_N);
-	start_int_mask(SE_USB_OTG_TIMER_INT);
-	start_int_mask(SE_USB_I2C_INT);
-	start_int_mask(SE_USB_INT);
-	start_int_mask(SE_USB_NEED_CLK_INT);
-	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+	if (machine_is_pnx4008()) {
+		start_int_mask(SE_USB_OTG_ATX_INT_N);
+		start_int_mask(SE_USB_OTG_TIMER_INT);
+		start_int_mask(SE_USB_I2C_INT);
+		start_int_mask(SE_USB_INT);
+		start_int_mask(SE_USB_NEED_CLK_INT);
+		start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+	}
 }
 
 static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)


From gregkh at linuxfoundation.org  Thu Mar  8 17:22:34 2012
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Thu, 8 Mar 2012 14:22:34 -0800
Subject: [PATCH v4] USB: Support for LPC32xx SoC
In-Reply-To: <1331244574-32570-1-git-send-email-stigge@antcom.de>
References: <1331244574-32570-1-git-send-email-stigge@antcom.de>
Message-ID: <20120308222234.GA25576@kroah.com>

On Thu, Mar 08, 2012 at 11:09:34PM +0100, Roland Stigge wrote:
> This patch adds OHCI support to the LPC32xx ARM platform
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>
> 
> ---
>  Applies to v3.3-rc6
> 
>  Since v3, only the machine_is_*() dependencies have been pulled into
>  the machine dependent functions.

Better, but:

>  static void pnx4008_unset_usb_bits(void)
>  {
> -	start_int_mask(SE_USB_OTG_ATX_INT_N);
> -	start_int_mask(SE_USB_OTG_TIMER_INT);
> -	start_int_mask(SE_USB_I2C_INT);
> -	start_int_mask(SE_USB_INT);
> -	start_int_mask(SE_USB_NEED_CLK_INT);
> -	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
> +	if (machine_is_pnx4008()) {

The function is called "pnx4008...", so why would any code path that is
not this hardware call this?

I think there's a disconnect between what you think a pnx4008 machine
is, and what I think it is, or what this code is running on and thinks
it is.

So, should this function just be called something else, for the type of
hardware (lpc32xx?), and then do this check within the function?

Again, consistancy is key.  Note how not all of the pnc4008_*()
functions make this check, which implies that something is not
consistant here...

thanks,

greg k-h


From robherring2 at gmail.com  Thu Mar  8 17:22:44 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 08 Mar 2012 16:22:44 -0600
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <20120308215048.GN5050@titan.lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203072113.04369.arnd@arndb.de>
 <20120308162530.GI5050@titan.lakedaemon.net>
 <201203081701.01663.arnd@arndb.de> <alpine.LFD.2.02.1203082026470.2742@ionos>
 <20120308194725.GM5050@titan.lakedaemon.net>
 <20120308213244.GD16533@ponder.secretlab.ca>
 <20120308215048.GN5050@titan.lakedaemon.net>
Message-ID: <4F593134.5000603@gmail.com>

On 03/08/2012 03:50 PM, Jason wrote:
> On Thu, Mar 08, 2012 at 02:32:44PM -0700, Grant Likely wrote:
>> On Thu, Mar 08, 2012 at 02:47:25PM -0500, Jason wrote:
>>> On Thu, Mar 08, 2012 at 08:27:11PM +0100, Thomas Gleixner wrote:
>>>> On Thu, 8 Mar 2012, Arnd Bergmann wrote:
>>>>
>>>>> On Thursday 08 March 2012, Jason wrote:
>>>>>>
>>>>>> On Wed, Mar 07, 2012 at 09:13:04PM +0000, Arnd Bergmann wrote:
>>>>>>> Finally, something could be wrong with the interrupt controller.
>>>>>>> AFAICT, you register it through the device tree now, but it's also
>>>>>>> getting initialized through kirkwood_init_irq, so the numbers
>>>>>>> would all be wrong.
>>>>>>
>>>>>> Yes, I'm working through this now.  mv_cesa silently fails to come up
>>>>>> if it can't find the interrupt controller via fdt.  So, it needs to get
>>>>>> done.
>>>>>>
>>>>>> Right now, I'm looking at how mach-versatile does it (vic_init()) since
>>>>>> it's also an ARM926ej-s...
>>>>>>
>>>>>
>>>>> Ok, sounds good. It's not important whether it's an ARM9 or not btw.
>>>>> You should look at both anything that defines an "interrupt-controller"
>>>>> property as an example including Documentation/devicetree/bindings/arm/vic.txt
>>>>> and Documentation/devicetree/bindings/arm/gic.txt.
>>>>>
>>>>> (taking Thomas Gleixner on Cc)
>>>>>
>>>>> Since the orion irq chip is based on irqchip_generic, it would be
>>>>> perfect to have a generic irqchip binding to go along with
>>>>> kernel/irq/generic-chip.c. Not sure if anyone has thought about this
>>>>> before, but it looks like we can completely avoid using
>>>>> arch/arm/plat-orion/irq.c and arch/arm/mach-kirkwood/irq.c if we
>>>>> do that.

A generic irqchip binding is not the right approach. The binding should
still be specific to the controller as the generic irqchip code doesn't
handle everything like dispatching interrupts or know how many blocks of
32 interrupts your controller has.

>>>> Right. That should be trivial to implement.

Yes, since someone else already has (me).

>>>
>>> ok, I'm on it.  kernel/irq/of_generic_irq.c sound good?
>>
>> Rob Herring has done some work in this area.  Please coordinate with him.
> 
> Rob,
> 
> I'm attempting to convert mach-kirkwood boards over to devicetree,
> starting with the dreamplug.
> 
> You can find my stable patches here:
> 
> git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_stable
> 
> and the stuff I'm still trying to figure out:
> 
> git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_staging
> 
> My next task looks like converting the irq code, since mv_cesa fails
> silently without the interrupt-controller specified in the dtb.
> 
> The code I'm replacing can be found here:
> 
> arch/arm/mach-kirkwood/irq.c
> arch/arm/plat-orion/irq.c
> 
> This is the first time I've attempted something like this, so any
> pointers would be much appreciated.  Also, if there is anything I would
> need to deconflict with, please let me know.
> 

Look at my branch here:

git://sources.calxeda.com/kernel/linux.git irqdomain-for-grant

Your .init_irq function should call of_irq_init which will then call an
init function for each controller. Then you need to call
irq_setup_generic_chip_domain to setup the generic irqchip instances.

You also should convert to enabling CONFIG_MULTI_IRQ_HANDLER or I think
a linear domain won't work for you and that's what the generic irqchip
code will use. Also you should enable SPARSE_IRQ, but that is somewhat
independent.

In the DT case, you want to not have any compile time dependencies on
Linux irq numbers. If you're keeping non-DT compatibility, that will
complicate your conversion.

Rob


From w.sang at pengutronix.de  Thu Mar  8 17:31:56 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 8 Mar 2012 23:31:56 +0100
Subject: [PATCH v4] USB: Support for LPC32xx SoC
In-Reply-To: <1331244574-32570-1-git-send-email-stigge@antcom.de>
References: <1331244574-32570-1-git-send-email-stigge@antcom.de>
Message-ID: <20120308223155.GA19176@pengutronix.de>


> --- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
> +++ linux-2.6/drivers/usb/host/ohci-hcd.c
> @@ -1055,6 +1055,11 @@ MODULE_LICENSE ("GPL");
>  #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
>  #endif
>  
> +#ifdef CONFIG_ARCH_LPC32XX
> +#include "ohci-pnx4008.c"
> +#define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
> +#endif

Can't we just do

#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX)

to save the duplicate entry?

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From stigge at antcom.de  Thu Mar  8 17:44:34 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 08 Mar 2012 23:44:34 +0100
Subject: [PATCH v4] USB: Support for LPC32xx SoC
In-Reply-To: <20120308222234.GA25576@kroah.com>
References: <1331244574-32570-1-git-send-email-stigge@antcom.de>
 <20120308222234.GA25576@kroah.com>
Message-ID: <4F593652.90809@antcom.de>

Hi,

On 08/03/12 23:22, Greg Kroah-Hartman wrote:
> So, should this function just be called something else, for the type of
> hardware (lpc32xx?), and then do this check within the function?

Right. LPC32xx and PNX4008 seem to share much of the functionality but
they don't share the bits() part. How about renaming (the static)

pnx4008_set_usb_bits()
pnx4008_unset_usb_bits()

to

set_usb_bits()
unset_usb_bits()

and internally doing machine_is_pnx4008() dependent stuff?

Regarding the other pnx4008_*() functions that are shared with lpc32xx,
they only inherit the name for historical reasons. Which naming scheme
should apply here if change is due? One common name between those two
would be "nxp". We could replace everything common between pnx4008 and
lpc32xx with nxp (including ths driver name) and handle the small
pnx4008-specific stuff via machine_is_pnx4008().

Thanks in advance,

Roland


From gregkh at linuxfoundation.org  Thu Mar  8 17:48:49 2012
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Thu, 8 Mar 2012 14:48:49 -0800
Subject: [PATCH v4] USB: Support for LPC32xx SoC
In-Reply-To: <4F593652.90809@antcom.de>
References: <1331244574-32570-1-git-send-email-stigge@antcom.de>
 <20120308222234.GA25576@kroah.com> <4F593652.90809@antcom.de>
Message-ID: <20120308224849.GA32667@kroah.com>

On Thu, Mar 08, 2012 at 11:44:34PM +0100, Roland Stigge wrote:
> Hi,
> 
> On 08/03/12 23:22, Greg Kroah-Hartman wrote:
> > So, should this function just be called something else, for the type of
> > hardware (lpc32xx?), and then do this check within the function?
> 
> Right. LPC32xx and PNX4008 seem to share much of the functionality but
> they don't share the bits() part. How about renaming (the static)
> 
> pnx4008_set_usb_bits()
> pnx4008_unset_usb_bits()
> 
> to
> 
> set_usb_bits()
> unset_usb_bits()
> 
> and internally doing machine_is_pnx4008() dependent stuff?
> 
> Regarding the other pnx4008_*() functions that are shared with lpc32xx,
> they only inherit the name for historical reasons. Which naming scheme
> should apply here if change is due? One common name between those two
> would be "nxp". We could replace everything common between pnx4008 and
> lpc32xx with nxp (including ths driver name) and handle the small
> pnx4008-specific stuff via machine_is_pnx4008().

That sounds more reasonable, right?  But do it in at least two patches
to make things obvious as to what is happening.

thanks,

greg k-h


From arnd at arndb.de  Thu Mar  8 18:14:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 8 Mar 2012 23:14:04 +0000
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <20120308212701.GB16533@ponder.secretlab.ca>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <201203072113.04369.arnd@arndb.de>
 <20120308212701.GB16533@ponder.secretlab.ca>
Message-ID: <201203082314.05385.arnd@arndb.de>

On Thursday 08 March 2012, Grant Likely wrote:
> > 
> > My first guess was that clock-frequency is wrong, but it seems that
> > this one actually is correct, at least it's the same thing that
> > the platform code sets.
> > 
> > You should never need to pass the virtual address to a device,
> > most of all because it cannot be known to the device tree at all.
> > The of_serial driver (you did enable that one in Kconfig, right?)
> 
> Ugh.  Someone really needs to step up and kill the of_serial driver.  All that
> stuff belongs in the core 16550 driver.

Well, actually I would argue that nothing belongs into the core 8250 driver.
What we should do though is split the of_serial.c file into the main 8250
portion and put that into drivers/tty/serial/8250/ along with the other
14 bus glue drivers, and put the nwpserial portion into
drivers/tty/serial/nwpserial.c.

I have started a major rework of 8250 some time ago that I need to finish up,
to make the different ways for registering an 8250 device more regular,
and get rid of the more obscure ways we have in the kernel, replacing them
with platform devices or other bus specific 'struct device' versions.

The main intention of that patch series is to confine the ISA/PCI specific
inb/outb accessors in the files that need them so we can actually build
the platform drivers without defining those, but I can take care of
of_serial.c as well -- after all I wrote that file originally.

	Arnd


From arnd at arndb.de  Thu Mar  8 12:41:16 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 8 Mar 2012 17:41:16 +0000
Subject: [PATCH 06/14] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <201203081701.01663.arnd@arndb.de>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <20120308162530.GI5050@titan.lakedaemon.net>
 <201203081701.01663.arnd@arndb.de>
Message-ID: <201203081741.16412.arnd@arndb.de>

On Thursday 08 March 2012, Arnd Bergmann wrote:

> Since the orion irq chip is based on irqchip_generic, it would be
> perfect to have a generic irqchip binding to go along with
> kernel/irq/generic-chip.c. Not sure if anyone has thought about this
> before, but it looks like we can completely avoid using
> arch/arm/plat-orion/irq.c and arch/arm/mach-kirkwood/irq.c if we
> do that.
> 

One more thing about the interrupt controller changes: The arm-soc
tree includes Grants "irqchip" branch, and the tegra/soc-drivers
and at91/dt branches are building on top of that. Please have a look
at what they do so you can do the same.

	Arnd



From s.hauer at pengutronix.de  Thu Mar  8 18:25:49 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 9 Mar 2012 00:25:49 +0100
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120308062739.GE18513@lunn.ch>
References: <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
 <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
 <20120308062739.GE18513@lunn.ch>
Message-ID: <20120308232549.GU3852@pengutronix.de>

On Thu, Mar 08, 2012 at 07:27:39AM +0100, Andrew Lunn wrote:
> > Assuming that some day OMAP code can be refactored to allow for lazy
> > (or at least initcall-based) registration of clocks then perhaps your
> > suggestion can take root.  Which leads me to this question: are there
> > any other platforms out there that require the level of expose to
> > struct clk present in this patchset?  OMAP does, for now, but if that
> > changes then I need to know if others require this as well.
> 
> Hi Mike
> 
> For kirkwood, i use static clk's for all but my root clock. I cannot
> statically know the rate of the root clock, so i have to determine it
> at boot time using heuristics, PCI ID, etc.
> 
> I used statics thinking it would be less code. No idea if it actually
> is, and there is nothing stopping me moving to creating the clocks
> after creating the root clock.

I'd say use the nonstatic ones. I think using the static initializers
will cause us much pain in the future. I've been through several rebases
on the i.MX clock rework and everytime I wish my sed foo would be
better. Now imagine what happens when it turns out that the internal
struct clk layout or the structs for the muxes/dividers/gates have to
be changed. This task is next to impossible when we have thousands of
clocks scattered around the tree.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From tony at atomide.com  Thu Mar  8 19:06:22 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 16:06:22 -0800
Subject: [PATCH v3] ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
 regulators
In-Reply-To: <87y5raaiob.fsf@ti.com>
References: <1330006564-13290-1-git-send-email-mporter@ti.com>
 <87wr74gis6.fsf@ti.com>
 <20120301204553.GA21841@legolas.emea.dhcp.ti.com>
 <87pqcqnc7u.fsf@ti.com>
 <CA+Bv8XaJqL1L8F-n6skY7dHn1XAdDLRKaRjw0deLeoQ5Ao0Fhg@mail.gmail.com>
 <87sjhkjj8m.fsf@ti.com> <20120308210825.GY12083@atomide.com>
 <87y5raaiob.fsf@ti.com>
Message-ID: <20120309000621.GA12083@atomide.com>

* Kevin Hilman <khilman at ti.com> [120308 12:54]:
> Tony Lindgren <tony at atomide.com> writes:
> 
> > * Kevin Hilman <khilman at ti.com> [120307 11:05]:
> >> >
> >> > I don't think the second smsc911x on the Overo, "smsc911x.1", would
> >> > find it due to the dev_id.
> >> 
> >> It's not about finding the second regulator.  As stated in the
> >> changelog, it's about the duplicate attempt to register the exact same
> >> platform_device.
> >> 
> >> Duplicate attempts to register the exact same platform_device cause
> >> kobject to panic and give up[1].  So, any platform that calls
> >> gpmc_smsc911x_init() twice (Overo and T35 in mainline) will panic on
> >> boot.
> >> 
> >> This patch fixes those platforms so they can boot.
> >
> > Yeah but I guess the second smsc911x instance still would not work,
> > or am I missing something?
> 
> I don't know since my Overo expansion boards don't have a 2nd NIC, but I
> suspect you're right.
> 
> However, my fix isn't addressing that.  I am fixing a problem where
> mainline today will panic on some boards due to duplicate registration.
> 
> If the 2nd interface doesn't work, then the original patch that added
> the regulators needs a rethink.  My patch to prevent the panic() is
> needed for mainline.

With Kevin's second version of this patch applied we avoid the panic
on boards with more than one smsc911x.

After this patch, board-*.c files can add custom regulators for their
other smsc911x instances.

We should also add a regulator to the struct omap_smsc911x_platform_data,
and then only initialize the fixed regulator automatically
if (!board_data->regulator && !board_data->id).

So I've pushed Kevin's second version of the fix to fix-smsc911x-regulator
branch.

Regards,

Tony


From marc at plastictigers.com  Thu Mar  8 19:21:06 2012
From: marc at plastictigers.com (Marc Butler)
Date: Thu, 8 Mar 2012 19:21:06 -0500
Subject: [RFC PATCH] slimbus message encoding/decoding
Message-ID: <20120309002106.GA605@plastictigers.com>

All,

This patch provides generic functions for encoding/decoding SLIMbus
messages (Section 8 of the specification).

This message API is built around the conjecture that the vast majority
of transactions will be using short arbitration, and a logical address
destination type. So there are separate functions for handling
short/long arbitration fields, logical/enumerated/broadcast header
fields.

This work has been done in separate files slimbus-msg.[ch] to avoid
collision with work in the main (slimbus.*) patch. The API is internal
to slimbus, and I do not anticipate slimbus device drivers needing
these functions.

No CRC generator is included for the PI and MI fields. The OMAP4430
chip this is being tested on generates and populates these fields in
h/w. However, I have include a general (and untested) callback
mechanism.

-m

Signed-off-by: Marc Butler <marc at plastictigers.com>
---
drivers/slimbus/slimbus-msg.c |  242 +++++++++++++++++++++++++++++++++++++++++
 drivers/slimbus/slimbus-msg.h |   70 ++++++++++++
 2 files changed, 312 insertions(+), 0 deletions(-)

diff --git a/drivers/slimbus/slimbus-msg.c b/drivers/slimbus/slimbus-msg.c
new file mode 100644
index 0000000..c88974e
--- /dev/null
+++ b/drivers/slimbus/slimbus-msg.c
@@ -0,0 +1,242 @@
+/* Copyright (c) 2012, Audience Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "slimbus-msg.h"
+
+/**
+ * slim_msg_scout() - quickly extract important information.
+ * @msg:	Valid binary message.
+ * @mt:		Message type.
+ * @mc:		Message code.
+ * @atype:	Address type.
+ * @paddr:	Pointer to destination address in message. Will be
+ *		Null if atype == broadcast.
+ * @plen:	Payload length in bytes.
+ * @pdat:	Pointer to first byte of payload. Null if plen == 0.
+ *
+ * This function is intended to aid parsing and handling incoming
+ * messages, by quickly extracting commonly referenced fields.
+ */
+int slim_msg_scout(struct slim_msg *msg, u8 *mt, u8 *mc, int *atype, u8 **paddr,
+		   u8 *plen, u8 **pdat)
+{
+	u8 i = 0;
+	u8 tmp;
+	u8 rlen;
+	u8 alen;
+
+	if (msg->len < SLIM_MSG_MINLEN) {
+		pr_err("slimbus: message with invalid length = %u\n", msg->len);
+		return -1;
+	}
+
+	/* Skip arbitration header. */
+	tmp = msg->b[0] >> 4;
+	switch (tmp) {
+	case 0xf:
+		i += 2; /* Short = logical address. */
+		break;
+	case 0x5:
+		i += 7; /* Long = enumerated address. */
+		break;
+	default:
+		pr_err("slimbus: unknown arbitration type = 0x%x\n", tmp);
+		return -1;
+	}
+
+	/* Cache the length of the arbitration portion. */
+	alen = i;
+	rlen = msg->b[i] & 0x1f;
+	*mt = msg->b[i++] >> 5;
+	*mc = msg->b[i++];
+
+	/* Extract the destination address. */
+	tmp = msg->b[i++] >> 4;
+	*atype = tmp;
+	switch (tmp) {
+	case SLIM_MSG_DEST_LOGICALADDR:
+		*paddr = &msg->b[i++];
+		break;
+	case SLIM_MSG_DEST_ENUMADDR:
+		*paddr = &msg->b[i];
+		i += 6;
+		break;
+	case SLIM_MSG_DEST_BROADCAST:
+		*paddr = NULL;
+		break;
+	default:
+		pr_warn("Slimbus invalid dt=0x%x\n", tmp);
+		return -1;
+	}
+
+	/*
+	 * Payload length = remaining length - header - 1 (MR+MI byte).
+	 *
+	 * We do not need to account for the MR+MI byte as i includes
+	 * the byte that contains remaining length (rlen), which is
+	 * not included by the specification. However, this means we
+	 * can simply ignore the -1 adjustment for the MR+MI byte.
+	 */
+	*plen = rlen - (i - alen);
+	*pdat = (*plen > 0) ? &msg->b[i] : NULL;
+	return 0;
+}
+
+/**
+ * slim_ins_arb_short() - insert a short arbitration field.
+ * @msg:	Empty message.
+ * @pri:	Arbitration priority.
+ * @la:		Logical address.
+ *
+ * The Arbitation Extension field (Spec: 8.2.1.2) is assumed to be
+ * Normal, as it is unclear to me if Reserved is valid.
+ */
+void slim_ins_arb_short(struct slim_msg *msg, u8 pri, u8 la)
+{
+	BUG_ON(msg->len > 0);
+	msg->b[msg->len++] = (SLIM_AT_SHORT << 4) | (pri & 0x7);
+	msg->b[msg->len++] = la;
+}
+
+/**
+ * slim_ins_arb_long() - insert a long arbitration field.
+ * @msg:	Empty message.
+ * @pri:	Arbitration priority.
+ * @la:		Enumerated address.
+ *
+ * The Arbitation Extension field (Spec: 8.2.1.2) is assumed to be
+ * Normal, as it is unclear to me if Reserved is valid.
+ */
+void slim_ins_arb_long(struct slim_msg *msg, u8 pri, u8 *ea)
+{
+	BUG_ON(msg->len > 0);
+	msg->b[msg->len++] = (SLIM_AT_LONG << 4) | (pri & 0x7);
+	msg->b[msg->len++] = *ea++;
+	msg->b[msg->len++] = *ea++;
+	msg->b[msg->len++] = *ea++;
+	msg->b[msg->len++] = *ea++;
+	msg->b[msg->len++] = *ea++;
+	msg->b[msg->len++] = *ea++;
+}
+
+/**
+ * slim_ins_hdr_la() -	insert a logical address header field.
+ * @msg:	Message already containing arbitration field.
+ * @mt:		Message type.
+ * @mc:		Message code.
+ * @plen:	Payload length.
+ * @la:		Logical address.
+ * @crcgen:	Optional 4-bit CRC generator.
+ *
+ * The remaining length field will be calculated based on the payload
+ * length @plen.
+ */
+void slim_ins_hdr_la(struct slim_msg *msg, u8 mt, u8 mc, u8 plen, u8 la,
+		     slim_crc_gen crcgen)
+{
+	/* Account for the 3 bytes following this field, the payload,
+	 * and +1 for the MR+MI field.
+	 */
+	msg->b[msg->len++] = (mt << 5) | (plen + 3 + 1);
+	msg->b[msg->len++] = mc & 0x7f;
+	if (crcgen)
+		msg->b[msg->len] |= crcgen(msg);
+	msg->b[msg->len++] |= SLIM_MSG_DEST_LOGICALADDR << 4;
+	msg->b[msg->len++] = la;
+}
+
+/**
+ * slim_ins_hdr_ea() -	insert an enumerated address header field.
+ * @msg:	Message already containing arbitration field.
+ * @mt:		Message type.
+ * @mc:		Message code.
+ * @plen:	Payload length.
+ * @ea:		Pointer to first byte of the enumerated address.
+ * @crcgen:	Optional 4-bit CRC generator.
+ *
+ * The remaining length field will be calculated based on the payload
+ * length @plen.
+ */
+void slim_ins_hdr_ea(struct slim_msg *msg, u8 mc, u8 mt, u8 plen, u8 *ea,
+		     slim_crc_gen crcgen)
+{
+	/* Account for the 7 bytes following this field, the
+	 * payload, and +1 for the MR+MI field.
+	 */
+	msg->b[msg->len++] = (mt << 5) | (plen + 7 + 1);
+	msg->b[msg->len++] = mc & 0x7f;
+	if (crcgen)
+		msg->b[msg->len] = crcgen(msg);
+	msg->b[msg->len++] |= SLIM_MSG_DEST_ENUMADDR << 4;
+	msg->b[msg->len++] = *ea++;
+	msg->b[msg->len++] = *ea++;
+	msg->b[msg->len++] = *ea++;
+	msg->b[msg->len++] = *ea++;
+	msg->b[msg->len++] = *ea++;
+	msg->b[msg->len++] = *ea++;
+}
+
+/**
+ * slim_ins_hdr_bcast() -	insert a broadcast header field.
+ * @msg:	Message already containing arbitration field.
+ * @mt:		Message type.
+ * @mc:		Message code.
+ * @plen:	Payload length.
+ * @ea:		Pointer to first byte of the enumerated address.
+ * @crcgen:	Optional 4-bit CRC generator.
+ *
+ * The remaining length field will be calculated based on the payload
+ * length @plen.
+ */
+void slim_ins_hdr_bcast(struct slim_msg *msg, u8 mc, u8 mt, u8 plen,
+			slim_crc_gen crcgen)
+{
+	/* Account for the 2 bytes following this field, the
+	 * payload, and +1 for the MR+MI field.
+	 */
+	msg->b[msg->len++] = (mt << 5) | (plen + 2 + 1);
+	msg->b[msg->len++] = mc & 0x7f;
+	if (crcgen)
+		msg->b[msg->len] = crcgen(msg);
+	msg->b[msg->len++] |= SLIM_MSG_DEST_BROADCAST << 4;
+}
+
+/**
+ * slim_ins_payload() -	insert a payload.
+ * @msg:	Message containing arbitration and header fields.
+ * @plen:	Payload length in bytes. This *must* match the value
+ *		given to slim_ins_hdr_*().
+ * @pdat:	Pointer to the first byte of the payload.
+ */
+void slim_ins_payload(struct slim_msg *msg, u8 plen, u8 *pdat)
+{
+	while (plen--)
+		msg->b[msg->len++] = *pdat++;
+}
+
+/**
+ * @slim_ins_mi() -	insert message response and
+ *			message integrity fields.
+ * @msg:	Message containing arbitration, header, and
+ *		payload.
+ * @crcgen:	Optional 4-bit CRC generator.
+ */
+void slim_ins_mi(struct slim_msg *msg, slim_crc_gen crcgen)
+{
+	if (!crcgen)
+		msg->b[msg->len] = 0;
+	else
+		msg->b[msg->len] = crcgen(msg);
+	msg->len++;
+}
+
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/slimbus/slimbus-msg.h b/drivers/slimbus/slimbus-msg.h
new file mode 100644
index 0000000..311ccb6
--- /dev/null
+++ b/drivers/slimbus/slimbus-msg.h
@@ -0,0 +1,70 @@
+/* Copyright (c) 2012, Audience Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _SLIMBUS_MSG_H
+#define _SLIMBUS_MSG_H
+
+#include <linux/slimbus/slimbus.h>
+
+/* Spec: 8.2 */
+#define SLIM_MSG_MAXLEN	39
+/* Inferred from Spec: 8.2, tbl 24. */
+#define SLIM_MSG_MINLEN	6
+/**
+ * slim_msg -	Slimbus message in binary form.
+ * @len:	Length of the message in bytes.
+ * @b:		Message in binary form.
+ */
+struct slim_msg {
+	u8 len;
+	u8 b[SLIM_MSG_MAXLEN];
+};
+
+#define SLIM_MSG_INIT_EMPTY { .len = 0 }
+
+/* Message arbitration types. Spec: 8.2.1.1. */
+#define SLIM_AT_NONE	0x0
+#define SLIM_AT_LONG	0x5
+#define SLIM_AT_SHORT	0xf
+
+/* Arbitration priority codes. Spec: 8.2.1.3. */
+#define SLIM_AP_LOW	0x01
+#define SLIM_AP_DEFAULT	0x02
+#define SLIM_AP_HIGH	0x03
+#define SLIM_AP_MAX	0x07
+
+/* Callback for 4-bit CRC generator. Spec: 8.2.4.1
+ *
+ * A callback is used so that h/w that the same functions can be used
+ * for drivers that control h/w that will automatically generate and
+ * fill in the integrity fields, such as the TI OMAP4430.
+ */
+typedef u8 (*slim_crc_gen)(struct slim_msg *msg);
+
+int slim_msg_scout(struct slim_msg *msg, u8 *mt, u8 *mc, int *atype, u8 **paddr,
+		   u8 *plen, u8 **pdat);
+
+void slim_ins_arb_short(struct slim_msg *msg, u8 pri, u8 la);
+
+void slim_ins_arb_long(struct slim_msg *msg, u8 pri, u8 *ea);
+
+void slim_ins_hdr_la(struct slim_msg *msg, u8 mt, u8 mc, u8 plen, u8 la,
+		     slim_crc_gen crcgen);
+void slim_ins_hdr_ea(struct slim_msg *msg, u8 mt, u8 mc, u8 plen, u8 *ea,
+		     slim_crc_gen crcgen);
+void slim_ins_hdr_bcast(struct slim_msg *msg, u8 mc, u8 mt, u8 plen,
+			slim_crc_gen crcgen);
+
+void slim_ins_payload(struct slim_msg *msg, u8 plen, u8 *pdat);
+
+void slim_ins_mi(struct slim_msg *msg, slim_crc_gen crcgen);
+
+#endif


From dh09.lee at samsung.com  Thu Mar  8 19:30:27 2012
From: dh09.lee at samsung.com (Donghwa Lee)
Date: Fri, 09 Mar 2012 09:30:27 +0900
Subject: [RFC PATCH] video:backlight: add dimming sysfs node
In-Reply-To: <4F587B1D.5080206@metafoo.de>
References: <4F58573C.3020407@samsung.com> <4F587B1D.5080206@metafoo.de>
Message-ID: <4F594F23.9030308@samsung.com>

Hi,
On Thu, Mar 8, 2012? 18:25, Lars-Peter Clausen wrote:

> On 03/08/2012 07:52 AM, Donghwa Lee wrote:
>> In backlight class, update_status() callback function is mostly used to change
>> backlight brightness. When platform enter the dimming state, it is usually used.
>> But, I think dimming state can be defined variety of method including brightness.
>> So, it is need to differentiated node from brightness node.
> 
> What do you mean by dimming? Completely blank the display or just lower the
> brightness to a certain level > 0? In the former case the bl_power sysfs
> node already exposes such functionality. In the later case can you give an
> example how this will be used and how a typical driver would implement this
> functionality?
> 


The dimming usually means minimum backlight brightness status which is not 
completely blank. Most backlight driver uses minimum brightness by using 
update_status() callback function so far as I know. 

But, I think sysfs node have to use only one goals. update_status() is normally
used to change brightness. 

I think dimming is different from changing brightness function. Others 
functionality can be added to dimming, for example, functionality to reduce 
power consumption. In each drivers, some functionalities can be implemented 
how to reduce power consumption in driver not only setting minimum brightness
to enter dimming state.

That is to say, dimming status can be defined many ways and be implemented by 
developers. Just that time, I think dimming node is used to interface between
driver and platform.

Thank you, 
Donghwa Lee

>>
>> In set_dimming() callback function, developers can define variety dimming functions.
>>
>> Signed-off-by: Donghwa Lee <dh09.lee at samsung.com>
>> Signed-off-by: Inki Dae <inki.dae at samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> ---
>>  drivers/video/backlight/backlight.c |   37 +++++++++++++++++++++++++++++++++++
>>  include/linux/backlight.h           |    9 ++++++++
>>  2 files changed, 46 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c
>> index bf5b1ec..44a77e4 100644
>> --- a/drivers/video/backlight/backlight.c
>> +++ b/drivers/video/backlight/backlight.c
>> @@ -101,6 +101,43 @@ static void backlight_generate_event(struct backlight_device *bd,
>>  	sysfs_notify(&bd->dev.kobj, NULL, "actual_brightness");
>>  }
>>  
>> +static ssize_t backlight_store_dimming(struct device *dev,
>> +		struct device_attribute *attr, const char *buf, size_t count)
>> +{
>> +	int rc;
>> +	struct backlight_device *bd = to_backlight_device(dev);
>> +	unsigned long dimming;
>> +
>> +	rc = strict_strtoul(buf, 0, &dimming);
>> +	if (rc)
>> +		return rc;
>> +
>> +	if (dimming < 0)
>> +		rc = -EINVAL;
>> +	else {
>> +		pr_debug("set dimming mode\n");
>> +
>> +		if (dimming)
>> +			bd->props.dimming = true;
>> +		else
>> +			bd->props.dimming = false;
>> +
>> +		backlight_set_dimming(bd);
>> +
>> +		rc = count;
>> +	}
>> +
>> +	return rc;
>> +}
>> +
>> +static ssize_t backlight_show_dimming(struct device *dev,
>> +		struct device_attribute *attr,char *buf)
>> +{
>> +	struct backlight_device *bd = to_backlight_device(dev);
>> +
>> +	return sprintf(buf, "%d\n", bd->props.dimming);
>> +}
>> +
>>  static ssize_t backlight_show_power(struct device *dev,
>>  		struct device_attribute *attr, char *buf)
>>  {
>> diff --git a/include/linux/backlight.h b/include/linux/backlight.h
>> index 5ffc6dd..823717e 100644
>> --- a/include/linux/backlight.h
>> +++ b/include/linux/backlight.h
>> @@ -55,10 +55,13 @@ struct backlight_ops {
>>  	/* Check if given framebuffer device is the one bound to this backlight;
>>  	   return 0 if not, !=0 if it is. If NULL, backlight always matches the fb. */
>>  	int (*check_fb)(struct backlight_device *, struct fb_info *);
>> +	/* Notify the backlight driver to enter the dimming state */
>> +	int (*set_dimming)(struct backlight_device *);
>>  };
>>  
>>  /* This structure defines all the properties of a backlight */
>>  struct backlight_properties {
>> +	bool dimming;
>>  	/* Current User requested brightness (0 - max_brightness) */
>>  	int brightness;
>>  	/* Maximal value for brightness (read-only) */
>> @@ -111,6 +114,12 @@ static inline void backlight_update_status(struct backlight_device *bd)
>>  	mutex_unlock(&bd->update_lock);
>>  }
>>  
>> +static inline void backlight_set_dimming(struct backlight_device *bd)
>> +{
>> +	if (bd->ops && bd->ops->set_dimming)
>> +		bd->ops->set_dimming(bd);
>> +}
>> +
>>  extern struct backlight_device *backlight_device_register(const char *name,
>>  	struct device *dev, void *devdata, const struct backlight_ops *ops,
>>  	const struct backlight_properties *props);
> 
> 






From tony at atomide.com  Thu Mar  8 19:32:18 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 16:32:18 -0800
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators
 for v3.4
In-Reply-To: <87399jc6cj.fsf@ti.com>
References: <877gywjhht.fsf@ti.com> <20120308021843.GQ12083@atomide.com>
 <87399jc6cj.fsf@ti.com>
Message-ID: <20120309003217.GB12083@atomide.com>

* Kevin Hilman <khilman at ti.com> [120308 09:37]:
> Tony Lindgren <tony at atomide.com> writes:
> 
> > * Kevin Hilman <khilman at ti.com> [120307 11:42]:
> >> Tony,
> >> 
> >> Please pull the following support for using regulators to control the
> >> on-chip VC/VP managed voltage domains.
> >> 
> >> The regulator driver support for this is already queued in the regulator
> >> tree, and this is the supporting core work.
> >> 
> >> This combined with the CPUfreq changes to use the regulator framework
> >> will finally result in MPU DVFS working in mainline.
> >
> > Nice.. However this one might be missing some header changes?
> 
> Oh, that's because it depends on the regulator core changes that are in
> Mark's regulator tree.  You need the for-next branch of :
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git 
> 
> For this to compile correctly.
> 
> Sorry, I should've been more clear above about the build dependency.

Hmm just checking.. Recently Mark replied to Peter:

* Mark Brown <broonie at opensource.wolfsonmicro.com> [120228 02:17]:
> On Tue, Feb 28, 2012 at 09:40:10AM +0200, Peter Ujfalusi wrote:
>
> > NOTE: this series has been generated agains Takashi's topic/asoc branch merged
> > with Mark's for-next branch since this series depends on changes in Marks'
> > branch, but not yet pulled by Takashi (snd_soc_add_dai_controls implementation
> > from Liam).
>
> Never base *anything* off my for-next branch, it gets rebuilt regularly.

So can you guys please confirm that if is indeed an immutable
commit to use as a base to merge in something?

Regards,

Tony


From tglx at linutronix.de  Thu Mar  8 19:51:36 2012
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 9 Mar 2012 01:51:36 +0100 (CET)
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
 <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1203090148270.2742@ionos>

On Wed, 7 Mar 2012, Turquette, Mike wrote:
> Assuming that some day OMAP code can be refactored to allow for lazy
> (or at least initcall-based) registration of clocks then perhaps your
> suggestion can take root.  Which leads me to this question: are there
> any other platforms out there that require the level of expose to
> struct clk present in this patchset?  OMAP does, for now, but if that
> changes then I need to know if others require this as well.

I can't see the problem, really. Other than existing code doing stuff
before the memory allocator is up and running.

We allocate interrupt data structures in the early boot process today
and I don't see a reason why you want clocks, which have not been
configured by the boot loader, accesible before that point.

Thanks,

	tglx


From grant.likely at secretlab.ca  Thu Mar  8 19:59:23 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 08 Mar 2012 17:59:23 -0700
Subject: [PATCH 1/1] of: add dma-mask binding
In-Reply-To: <20120307173437.GC17087@game.jcrosoft.org>
References: <1331119575-6638-1-git-send-email-plagnioj@jcrosoft.com>
 <4F5793E9.9010100@gmail.com> <20120307173437.GC17087@game.jcrosoft.org>
Message-ID: <20120309005923.2E04F3E0901@localhost>

[cc'ing Russell and Ben because my dma-mask-foo is weak]

On Wed, 7 Mar 2012 18:34:37 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> On 10:59 Wed 07 Mar     , Rob Herring wrote:
> > On 03/07/2012 05:26 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > This will allow each device to specify its dma-mask
> > > The microblaze architecture hook is keep temporary if no dma-mask is specified
> > > int the DT
> > > 
> > > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > > ---
> > >  drivers/of/platform.c |   26 +++++++++++++++++++++++++-
> > >  1 files changed, 25 insertions(+), 1 deletions(-)
> > > 
> > > diff --git a/drivers/of/platform.c b/drivers/of/platform.c
> > > index cae9477..bb22194 100644
> > > --- a/drivers/of/platform.c
> > > +++ b/drivers/of/platform.c
> > > @@ -121,6 +121,26 @@ void of_device_make_bus_id(struct device *dev)
> > >  	dev_set_name(dev, "%s.%d", node->name, magic - 1);
> > >  }
> > >  
> > > +static u64* of_get_dma_mask(struct device_node *np)
> > > +{
> > > +	const __be32 *prop;
> > > +	int len;
> > > +	u64 *dma_mask;
> > > +
> > > +	prop = of_get_property(np, "dma-mask", &len);
> > 
> > This would need some documentation. There is already "dma-ranges"
> > defined for OF which nay do what's needed.
> what is dma-ranges I see no doc about it
> but I don't think it could be used for the dma mask

As Rob says, it's documented in ePAPR.

> > 
> > > +
> > > +	if (!prop)
> > > +		return NULL;
> > > +
> > > +	dma_mask = kzalloc(sizeof(u64), GFP_KERNEL);
> > 
> > This seems kind of wasteful for 1 u64.
> no choice dma_mask must be a pointer

We could merely add an empty dma_mask u64 to the containing struct
platform_device and then assign the pointer to dev.dma_mask if it is
needed.  That would eliminate the malloc.  Or we could by default
use dev->dev.dma_mask = &dev->dev.coherent_dma_mask;  Drivers or
notifier code could override whatever we setup here as the default.

dma-ranges really is the property that should be used for this, but
dma-ranges can describe a different set of permutations than dma_mask.
The former can have any number of valid DMA windows, but dma_mask
is based on per-address-line values.  (The whole dma_mask approach
appears insufficient to me, but I don't understand all the background
details as to why it is implemented that way).

I'd like to avoid defining a new mechanism for describing the valid
dma layout if at all possible.  This could be done with a new function
to fetch and parse each of the dma-ranges tuples and extract the
intersect of the ranges.  It will never be a perfect translation,
particularly because RAM doesn't start at 0 on a lot of platforms.

So, let's call the base of ram X, and the top of ram X+S.  Then let's
assume that dma_mask is intended to filter out high address (instead
of broken DMA low addresses) and that the DMA limitations are based
on attached address lines, not arbitrary start-end addresses, so if
we let number of address lines be 'A', then dma_mask = 2^A-1
(ideally).  Individual bits could also be blanked out, but what that
really means in a practical sense is that those address lines must be
0.  There isn't a way to constrain address bits that must be set to 1.

Okay, so if we assume that linux will never choose a dma address below
X (because there is no RAM there; except in the iommu case which can
put dma addresses where it needs to regardless), then we only need to
worry about the upper range for a device.  We could derive a dma_mask
by calling of_translate_address on the base address of each dma-ranges
tuple and finding the one that starts at or below the base of memory.
Then the default dma_mask can perhaps be calculated thusly (using 'Y'
for top of the chosen dma-range tuple):

	dma_mask = (2 ^ fls64(Y)) - 1;

Alternately, we could simply decide to do as you suggest and define a
dma-mask property because that approach is sufficient for a lot of
hardware and is therefore is a reasonable binding.

Thoughts?

> > 
> > > +	if (!dma_mask)
> > > +		return NULL;
> > > +
> > > +	*dma_mask = of_read_number(prop, len / 4);
> > > +
> > > +	return dma_mask;
> > > +}
> > > +
> > >  /**
> > >   * of_device_alloc - Allocate and initialize an of_device
> > >   * @np: device node to assign to device
> > > @@ -161,10 +181,14 @@ struct platform_device *of_device_alloc(struct device_node *np,
> > >  		WARN_ON(of_irq_to_resource_table(np, res, num_irq) != num_irq);
> > >  	}
> > >  
> > > +	dev->dev.dma_mask = of_get_dma_mask(np);
> > >  	dev->dev.of_node = of_node_get(np);
> > > +
> > >  #if defined(CONFIG_MICROBLAZE)
> > > -	dev->dev.dma_mask = &dev->archdata.dma_mask;
> > 
> > And doing it this way for didn't get a warm reception either:
> > 
> > http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-April/005285.html
> > 
> > Do you really need this to be something other than ~0UL and if so does
> > it need to be per device or system wide?
> > 
> > You can solve this with bus notifiers in your at91 code. Here's an
> > example which I did (but no longer need):
> > 
> > static u64 highbank_dma_mask = DMA_BIT_MASK(32);
> IIRC on at91 all of them that need it have a DMA_BIT_MASK(32)
> 
> 
> > 
> > static int highbank_platform_notifier(struct notifier_block *nb,
> > 				  unsigned long event, void *__dev)
> > {
> > 	struct device *dev = __dev;
> > 
> > 	if (event != BUS_NOTIFY_ADD_DEVICE)
> > 		return NOTIFY_DONE;
> > 
> > 	if (of_device_is_compatible(dev->of_node, "calxeda,hb-nfc"))
> > 		dev->dma_mask = &highbank_dma_mask;
> execpt as example today I need it on 2 node (OHCI & EHCI)
> 
> and if more device need I don't want to end up with more fixup
> 
> I really prefer to set it via DT
> 
> Best Regards,
> J.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
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From grant.likely at secretlab.ca  Thu Mar  8 20:05:55 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 08 Mar 2012 18:05:55 -0700
Subject: [PATCH 1/4] gpiolib: Add gpiochip_find_by_name() and
 gpio_find_by_chip_name()
In-Reply-To: <20120302190614.GO18901@atomide.com>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185524.29210.60381.stgit@kaulin.local>
 <20120302075804.F28DB3E2DB4@localhost> <20120302170327.GF18901@atomide.com>
 <20120302180848.GM18901@atomide.com> <20120302184833.C296A3E1C63@localhost>
 <20120302190614.GO18901@atomide.com>
Message-ID: <20120309010555.8DE213E0901@localhost>

On Fri, 2 Mar 2012 11:06:15 -0800, Tony Lindgren <tony at atomide.com> wrote:
> * Grant Likely <grant.likely at secretlab.ca> [120302 10:16]:
> > On Fri, 2 Mar 2012 10:08:48 -0800, Tony Lindgren <tony at atomide.com> wrote:
> > > * Tony Lindgren <tony at atomide.com> [120302 08:31]:
> > > > * Grant Likely <grant.likely at secretlab.ca> [120302 01:00]:
> > > > > On Thu, 01 Mar 2012 10:55:24 -0800, Tony Lindgren <tony at atomide.com> wrote:
> > > > > > +
> > > > > > +/**
> > > > > > + * gpiochip_find_by_name() - iterator for locating a gpio_chip by name
> > > > > > + * @name: name of the gpio_chip
> > > > > > + *
> > > > > > + * Similar to bus_find_device_by_name. It returns a reference to the
> > > > > > + * first gpio_chip with matching name. It ignores NULL and empty names.
> > > > > > + * If you need to do something more complex, then use gpiochip_find.
> > > > > > + */
> > > > > > +struct gpio_chip *gpiochip_find_by_name(const char *name)
> > > > > > +{
> > > > > > +	if (!name || !strcmp(name, ""))
> > > > > > +		return NULL;
> > > > > > +
> > > > > > +	return gpiochip_find((void *)name, match_name);
> > > > > 
> > > > > Nasty cast.  Can the signature for gpiochip_find be changed to accept
> > > > > a (const void *)?
> > > > 
> > > > I think so, this too comes from the bus code.
> > > 
> > > Looks like it can't be const as of_node_to_gpiochip uses it with
> > > a struct device_node * that for of_get_named_gpio_flags comes from
> > > of_parse_phandle_with_args.
> > 
> > Really? It sees to work fine here:
> 
> Hmm right you are. I must have missed adding the const to
> of_gpiochip_is_match, that's good news :)
> 
> Want to do that as a separate patch or want me to fold it in?

I've got it as a separate commit in my gpio/next branch.

g.

> > ---
> > 
> > diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
> > index d773540..e633a2a 100644
> > --- a/drivers/gpio/gpiolib.c
> > +++ b/drivers/gpio/gpiolib.c
> > @@ -1152,8 +1152,9 @@ EXPORT_SYMBOL_GPL(gpiochip_remove);
> >   * non-zero, this function will return to the caller and not iterate over any
> >   * more gpio_chips.
> >   */
> > -struct gpio_chip *gpiochip_find(void *data,
> > -				int (*match)(struct gpio_chip *chip, void *data))
> > +struct gpio_chip *gpiochip_find(const void *data,
> > +				int (*match)(struct gpio_chip *chip,
> > +					     const void *data))
> >  {
> >  	struct gpio_chip *chip = NULL;
> >  	unsigned long flags;
> > diff --git a/drivers/of/gpio.c b/drivers/of/gpio.c
> > index e034b38..bba8121 100644
> > --- a/drivers/of/gpio.c
> > +++ b/drivers/of/gpio.c
> > @@ -229,7 +229,7 @@ void of_gpiochip_remove(struct gpio_chip *chip)
> >  }
> >  
> >  /* Private function for resolving node pointer to gpio_chip */
> > -static int of_gpiochip_is_match(struct gpio_chip *chip, void *data)
> > +static int of_gpiochip_is_match(struct gpio_chip *chip, const void *data)
> >  {
> >  	return chip->of_node == data;
> >  }
> > diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
> > index 1ff4e22..5f52690 100644
> > --- a/include/asm-generic/gpio.h
> > +++ b/include/asm-generic/gpio.h
> > @@ -142,9 +142,9 @@ extern int __must_check gpiochip_reserve(int start, int ngpio);
> >  /* add/remove chips */
> >  extern int gpiochip_add(struct gpio_chip *chip);
> >  extern int __must_check gpiochip_remove(struct gpio_chip *chip);
> > -extern struct gpio_chip *gpiochip_find(void *data,
> > +extern struct gpio_chip *gpiochip_find(const void *data,
> >  					int (*match)(struct gpio_chip *chip,
> > -						     void *data));
> > +						     const void *data));
> >  
> >  
> >  /* Always use the library code for GPIO management calls,
> > 

-- 
email sent from notmuch.vim plugin


From shawn.guo at linaro.org  Thu Mar  8 20:19:16 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 9 Mar 2012 09:19:16 +0800
Subject: [PATCH v3 00/11] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <4F5910EE.8090408@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <4F5910EE.8090408@freescale.com>
Message-ID: <20120309011914.GF2499@S2101-09.ap.freescale.net>

On Thu, Mar 08, 2012 at 02:05:02PM -0600, Timur Tabi wrote:
> Shawn Guo wrote:
> > I did not pick up you Ack-by tag, because there are some changes since
> > v2 you will need to take another look and have the testing, I guess.
> 
> Unfortunately, although it works on the MPC8610, it's broken on the P1022:
> 
> # speaker-test -t sine -c 2 -r 44100
> 
> 
> speaker-test 1.0.11rc2
> 
> 
> Playback device is default
> Stream parameters are 44100Hz, S16_BE, 2 channels
> Sine wave rate is 440.0000Hz
> Rate set to 44100Hz (requested 44100Hz)
> Buffer size range from 256 to 32768
> Period size range from 128 to 16384
> Periods = 4
> Buffer time size 575
> To choose buffer_size = 32768
> To choose period_size = 8192
> was set period_size = 8192
> was set buffer_size = 32768
> 
> At this point, nothing else happens, there's no audio, and even Ctrl-C
> doesn't work.
> 
Are you testing the patch set on top of the SHA below, which I
mentioned in the cover letter?

  3030763 (Merge tag 'asoc-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into topic/asoc)

I see the similar problem on the following SHA with my testing on
imx-sgtl5000.

  1a8feca (Merge branch 'for-3.4' into asoc-next)

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Thu Mar  8 20:26:55 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 9 Mar 2012 09:26:55 +0800
Subject: [PATCH v3 08/11] ASoC: fsl: make fsl_ssi driver compilable on
 ARM/IMX
In-Reply-To: <4F5912D0.2090800@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-9-git-send-email-shawn.guo@linaro.org>
 <4F5912D0.2090800@freescale.com>
Message-ID: <20120309012653.GG2499@S2101-09.ap.freescale.net>

On Thu, Mar 08, 2012 at 02:13:04PM -0600, Timur Tabi wrote:
> Shawn Guo wrote:
> > +static DEFINE_SPINLOCK(ssi_reg_lock);
> > +static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
> > +{
> > +	u32 val;
> > +	unsigned long flags;
> > +
> > +	spin_lock_irqsave(&ssi_reg_lock, flags);
> > +	val = readl(addr);
> > +	val = (val & ~clear) | set;
> > +	writel(val, addr);
> > +	spin_unlock_irqrestore(&ssi_reg_lock, flags);
> > +}
> > +#endif
> 
> I think this spinlock is the wrong approach.  The problem with
> read-modify-write is on the function level, not the register level.
> 
Something like this:

@@ -496,6 +494,10 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
        struct snd_soc_pcm_runtime *rtd = substream->private_data;
        struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
        struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+       unsigned long flags;
+       int ret = 0;
+
+       spin_lock_irqsave(&ssi_lock, flags);

        switch (cmd) {
        case SNDRV_PCM_TRIGGER_START:
@@ -517,10 +519,12 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
                break;

        default:
-               return -EINVAL;
+               ret = -EINVAL;
        }

-       return 0;
+       spin_unlock_irqrestore(&ssi_lock, flags);
+
+       return ret;
 }

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Thu Mar  8 20:32:17 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 9 Mar 2012 09:32:17 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F591B8D.8090705@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
Message-ID: <20120309013216.GH2499@S2101-09.ap.freescale.net>

On Thu, Mar 08, 2012 at 02:50:21PM -0600, Timur Tabi wrote:
> Shawn Guo wrote:
> > As Documentation/devicetree/bindings/powerpc/fsl/ssi.txt documented,
> > codec-handle is an optional property, so missing it should not be a
> > fatal error.]
> 
> It's optional in the sense that if your SSI is not connected to anything,
> then you don't need to specify the codec handle.  If the SSI is connected
> to a codec, then the SSI node needs to point to it.
> 
It's true for the binding that mpc8610_hpcd and p1022_ds use.  But per
request from Mark, we need to use the new binding for imx machine
drivers, which will have the codec phandle in "audio complex" node.

> > More importantly, the imx machine drivers to be added working with
> > fsl_ssi will not have this property, as they use new ASoC machine
> > driver binding mechanism.
> 
> I want to see that binding documented in Documentation/devicetree/bindings
> first.

Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt, which
takes Documentation/devicetree/bindings/sound/tegra-audio-wm8903.txt
as the example.

-- 
Regards,
Shawn


From tony at atomide.com  Thu Mar  8 20:40:16 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 17:40:16 -0800
Subject: [GIT PULL] ARM: OMAP2+: hwmod data: cleanup in preparation for
 link array removal
In-Reply-To: <alpine.DEB.2.00.1203072102150.21662@utopia.booyaka.com>
References: <alpine.DEB.2.00.1203072102150.21662@utopia.booyaka.com>
Message-ID: <20120309014016.GC12083@atomide.com>

Hi Paul,

* Paul Walmsley <paul at pwsan.com> [120307 19:34]:
> Hi Tony
> 
> The following changes since commit b8a633451951d149494076393698880453bf6bfe:
> 
>   ARM: OMAP: hwmod: add softreset delay field and OMAP4 data (2012-02-28 03:46:31 -0700)
> 
> are available in the git repository at:
> 
>   git://git.pwsan.com/linux-2.6 hwmod_data_cleanup_3.4
> 
> for you to fetch changes up to a2d4b88dd32b02e8b5088e0d64b3c102c0852210:
> 
>   ARM: OMAP2+: hwmod: extend OCP_* register offsets from 16 to 32 bits (2012-02-28 03:49:34 -0700)
> 
> (This branch is based on the 'hwmod_code_cleanup_3.4' branch, pull req 
> sent previously)

Got these now merged into l-o master, but ran into a merge
conflict with already queued sr branch. Resolved it by using
your version except left out vdd_name. As the namings have
changed for smartreflex, now I suspect it's broken for the
interrupts..

Care to take a look and see how we should deal with this?
My merge resolution below for reference.

Regards,

Tony


--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@@ -2684,9 -2736,10 +2736,9 @@@ static struct omap_hwmod_ocp_if *omap34
  };
  
  static struct omap_hwmod omap34xx_sr1_hwmod = {
- 	.name		= "sr1_hwmod",
+ 	.name		= "sr1",
  	.class		= &omap34xx_smartreflex_hwmod_class,
  	.main_clk	= "sr1_fck",
 -	.vdd_name	= "mpu_iva",
  	.prcm		= {
  		.omap2 = {
  			.prcm_reg_id = 1,
@@@ -2703,10 -2754,15 +2753,14 @@@
  	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
  };
  
+ static struct omap_hwmod_ocp_if *omap36xx_sr1_slaves[] = {
+ 	&omap36xx_l4_core__sr1,
+ };
+ 
  static struct omap_hwmod omap36xx_sr1_hwmod = {
- 	.name		= "sr1_hwmod",
+ 	.name		= "sr1",
  	.class		= &omap36xx_smartreflex_hwmod_class,
  	.main_clk	= "sr1_fck",
 -	.vdd_name	= "mpu_iva",
  	.prcm		= {
  		.omap2 = {
  			.prcm_reg_id = 1,
@@@ -2732,9 -2782,10 +2780,9 @@@ static struct omap_hwmod_ocp_if *omap34
  };
  
  static struct omap_hwmod omap34xx_sr2_hwmod = {
- 	.name		= "sr2_hwmod",
+ 	.name		= "sr2",
  	.class		= &omap34xx_smartreflex_hwmod_class,
  	.main_clk	= "sr2_fck",
 -	.vdd_name	= "core",
  	.prcm		= {
  		.omap2 = {
  			.prcm_reg_id = 1,
@@@ -2751,10 -2800,15 +2797,14 @@@
  	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
  };
  
+ static struct omap_hwmod_ocp_if *omap36xx_sr2_slaves[] = {
+ 	&omap36xx_l4_core__sr2,
+ };
+ 
  static struct omap_hwmod omap36xx_sr2_hwmod = {
- 	.name		= "sr2_hwmod",
+ 	.name		= "sr2",
  	.class		= &omap36xx_smartreflex_hwmod_class,
  	.main_clk	= "sr2_fck",
 -	.vdd_name	= "core",
  	.prcm		= {
  		.omap2 = {
  			.prcm_reg_id = 1,


From grant.likely at secretlab.ca  Thu Mar  8 20:44:39 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 08 Mar 2012 18:44:39 -0700
Subject: [PULL] of nand generic binding
In-Reply-To: <4F576602.8020808@gmail.com>
References: <20120217155707.GR1214@game.jcrosoft.org>
 <20120229152534.GH3318@game.jcrosoft.org>
 <20120307082945.GJ21255@game.jcrosoft.org> <4F576602.8020808@gmail.com>
Message-ID: <20120309014439.235C23E0901@localhost>

On Wed, 07 Mar 2012 07:43:30 -0600, Rob Herring <robherring2 at gmail.com> wrote:
> On 03/07/2012 02:29 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 16:25 Wed 29 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> >> On 16:57 Fri 17 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>> HI,
> >>>
> >>> 	please find attached the generic binding for the MTD nand
> >>>
> >>> 	This will add boolean and nand helpers
> >> is it ok?
> > I need this for 3.4
> > 
> > will you apply it or can I apply it via AT91
> 
> Looks fine to me and Grant acked it, so go ahead and take with your at91
> branch.

Actually, taking another look at the of_mtd patch, that stuff really
belongs in the drivers/mtd directory.  I'm not nacking the patch, but
you should send a follow up to move it into the correct place.

I don't like the of_property_read_bool patch.  I don't want the
of_property_read_ functions to mix data return and error codes.
Either return a bool with an error code in the parameter list, or the
other way around.  Otherwise we'll end up with the same problem as
APIs that use the ERR_PTR() pattern where callers will use it without
understanding that the return value isn't necessarily a bool.

g.

> 
> Rob
> 
> > 
> > Best Regards,
> > J.
> > _______________________________________________
> > devicetree-discuss mailing list
> > devicetree-discuss at lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/devicetree-discuss
> 

-- 
email sent from notmuch.vim plugin


From grant.likely at secretlab.ca  Thu Mar  8 20:44:41 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 08 Mar 2012 18:44:41 -0700
Subject: [PATCH 1/1] of: introduce helper to manage boolean
In-Reply-To: <1328588028-24766-1-git-send-email-plagnioj@jcrosoft.com>
References: <1328588028-24766-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120309014441.8236B3E0903@localhost>

On Tue,  7 Feb 2012 05:13:48 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> of_property_read_bool
> 
> Search for a property in a device node and read a 32-bit value from
> it. Returns 0 if <0> or if the property does not exist, 1 if <1> or none.
> 
> this will allow to disable a boolean
> 
> is-ok;          => true
> is-ok = <1>;    => true
> is-ok = <0>;    => false
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: devicetree-discuss at lists.ozlabs.org
> ---
> Hi,
> 
> 	if this is ok I'll rebase my mtd and i2c patch to use it
> 
> Best Regards,
> J.
>  drivers/of/base.c  |   30 ++++++++++++++++++++++++++++++
>  include/linux/of.h |    8 ++++++++
>  2 files changed, 38 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/of/base.c b/drivers/of/base.c
> index 133908a..a0eaf08 100644
> --- a/drivers/of/base.c
> +++ b/drivers/of/base.c
> @@ -686,6 +686,36 @@ int of_property_read_u64(const struct device_node *np, const char *propname,
>  EXPORT_SYMBOL_GPL(of_property_read_u64);
>  
>  /**
> + * of_property_read_bool - Find and read a boolean from a property
> + * @np:		device node from which the property value is to be read.
> + * @propname:	name of the property to be searched.
> + *
> + * Search for a property in a device node and read a 32-bit value from
> + * it. Returns 0 if <0> or if the property does not exist, 1 if <1> or none.
> + *
> + * is-ok;	=> true
> + * is-ok = <1>;	=> true
> + * is-ok = <0>;	=> false
> + */
> +int of_property_read_bool(const struct device_node *np, const char *propname)
> +{
> +	u32 reg;
> +	int ret = of_property_read_u32(np, propname, &reg);
> +
> +	switch (ret) {
> +	case -EINVAL:
> +		return false;
> +	case -ENODATA:
> +		return true;
> +	case 0:
> +		return reg == 1;

Ugh.  so any value other than 1 returns false?  I think that will surprise
most people.

I don't like this api or binding.  If it is a bool property, then why isn't
simply testing for the property existance sufficient?

g.


From shawn.guo at linaro.org  Thu Mar  8 20:51:30 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 9 Mar 2012 09:51:30 +0800
Subject: [PATCH v3 10/11] ASoC: fsl: let fsl_ssi work with imx pcm and
 machine drivers
In-Reply-To: <20120308191526.GQ3852@pengutronix.de>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-11-git-send-email-shawn.guo@linaro.org>
 <20120308191526.GQ3852@pengutronix.de>
Message-ID: <20120309015128.GI2499@S2101-09.ap.freescale.net>

On Thu, Mar 08, 2012 at 08:15:26PM +0100, Sascha Hauer wrote:
...
> > @@ -796,6 +862,7 @@ static int fsl_ssi_remove(struct platform_device *pdev)
> >  
> >  static const struct of_device_id fsl_ssi_ids[] = {
> >  	{ .compatible = "fsl,mpc8610-ssi", },
> > +	{ .compatible = "fsl,imx1-ssi", },
> 
> imx1 seems wrong here. The register layout has changed significantly between
> i.MX1 and i.MX21.
> 
Yeah, that's right.  You indeed know i.MX1 much better than me.  Will
change to:

  .compatible = "fsl,imx21-ssi"

-- 
Regards,
Shawn


From paul at pwsan.com  Thu Mar  8 20:57:04 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 8 Mar 2012 18:57:04 -0700 (MST)
Subject: [GIT PULL] ARM: OMAP2+: hwmod data: cleanup in preparation for
 link array removal
In-Reply-To: <20120309014016.GC12083@atomide.com>
References: <alpine.DEB.2.00.1203072102150.21662@utopia.booyaka.com>
 <20120309014016.GC12083@atomide.com>
Message-ID: <alpine.DEB.2.00.1203081851570.9551@utopia.booyaka.com>

Hi

On Thu, 8 Mar 2012, Tony Lindgren wrote:

> Got these now merged into l-o master, but ran into a merge
> conflict with already queued sr branch. Resolved it by using
> your version except left out vdd_name.

Definitely we want the vdd_name fields.  Other than that it looks okay.  

> As the namings have changed for smartreflex, now I suspect it's broken 
> for the interrupts..

Hmm, not sure I understand that part?  AFAIK the SmartReflex code doesn't 
rely on hwmod names.  Or are you talking about the vdd_name?


- Paul


From paul at pwsan.com  Thu Mar  8 21:04:31 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 8 Mar 2012 19:04:31 -0700 (MST)
Subject: [GIT PULL] ARM: OMAP2+: hwmod data: cleanup in preparation for
 link array removal
In-Reply-To: <alpine.DEB.2.00.1203081851570.9551@utopia.booyaka.com>
References: <alpine.DEB.2.00.1203072102150.21662@utopia.booyaka.com>
 <20120309014016.GC12083@atomide.com>
 <alpine.DEB.2.00.1203081851570.9551@utopia.booyaka.com>
Message-ID: <alpine.DEB.2.00.1203081900500.26543@utopia.booyaka.com>

Hi

on second thought...

On Thu, 8 Mar 2012, Paul Walmsley wrote:

> On Thu, 8 Mar 2012, Tony Lindgren wrote:
> 
> > Got these now merged into l-o master, but ran into a merge
> > conflict with already queued sr branch. Resolved it by using
> > your version except left out vdd_name.
> 
> Definitely we want the vdd_name fields.  Other than that it looks okay.  

I guess that other SR series that you merged removed the vdd_name fields?

If so then yeah, we'd better leave those out.

This means that I'm going to have to rebase those big hwmod data changes 
:-(

Can you send me a stable commit for that?


- Paul


From tony at atomide.com  Thu Mar  8 21:09:36 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 18:09:36 -0800
Subject: [PATCH 1/4] gpiolib: Add gpiochip_find_by_name() and
 gpio_find_by_chip_name()
In-Reply-To: <20120309010555.8DE213E0901@localhost>
References: <20120301185044.29210.44521.stgit@kaulin.local>
 <20120301185524.29210.60381.stgit@kaulin.local>
 <20120302075804.F28DB3E2DB4@localhost>
 <20120302170327.GF18901@atomide.com>
 <20120302180848.GM18901@atomide.com>
 <20120302184833.C296A3E1C63@localhost>
 <20120302190614.GO18901@atomide.com>
 <20120309010555.8DE213E0901@localhost>
Message-ID: <20120309020935.GD12083@atomide.com>

* Grant Likely <grant.likely at secretlab.ca> [120308 17:08]:
> On Fri, 2 Mar 2012 11:06:15 -0800, Tony Lindgren <tony at atomide.com> wrote:
> > 
> > Want to do that as a separate patch or want me to fold it in?
> 
> I've got it as a separate commit in my gpio/next branch.

OK great, below is my patch updated against gpio/next if you
want to pick it up.

Regards,

Tony


From: Tony Lindgren <tony at atomide.com>
Date: Fri, 2 Mar 2012 11:30:23 -0800
Subject: [PATCH] gpiolib: Add gpiochip_find_by_name() and gpio_find_by_chip_name()

Currently there is no way for drivers to request a GPIO on a particular
gpio chip using platform data. This makes it hard to support multiple
GPIO controllers with platform driver with dynamic GPIO and interrupt
numbering, such as with CONFIG_SPARSE_IRQ.

Let's make it easier for platform device drivers to find GPIOs on a
specific gpio_chip by adding two functions: gpiochip_find_by_name()
and gpio_find_by_chip_name().

Note that these functions should not be used with device tree as
pointed out by Grant Likely <grant.likely at secretlab.ca> as the names
are instantiated from device tree.

As gpiochip_find() is already exported, we may as well export
gpiochip_find_by_name() too.

Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1178,6 +1178,51 @@ struct gpio_chip *gpiochip_find(const void *data,
 }
 EXPORT_SYMBOL_GPL(gpiochip_find);
 
+static int gpiochip_match_name(struct gpio_chip *chip, const void *name)
+{
+	return !strcmp(name, chip->label);
+}
+
+/**
+ * gpiochip_find_by_name() - iterator for locating a gpio_chip by name
+ * @name: name of the gpio_chip
+ *
+ * Similar to bus_find_device_by_name. It returns a reference to the
+ * first gpio_chip with matching name. It ignores NULL and empty names.
+ * If you need to do something more complex, then use gpiochip_find.
+ */
+struct gpio_chip *gpiochip_find_by_name(const char *name)
+{
+	if (!name || !strcmp(name, ""))
+		return NULL;
+
+	return gpiochip_find(name, gpiochip_match_name);
+}
+EXPORT_SYMBOL_GPL(gpiochip_find_by_name);
+
+/**
+ * gpio_find_by_chip_name() - find a gpio on a specific gpio_chip
+ * @chip_name: name of the gpio_chip
+ * @gpio_offset: offset of the gpio on the gpio_chip
+ *
+ * Note that gpiochip_find_by_name returns the first matching
+ * gpio_chip name. For more complex matching, see gpio_find.
+ */
+int gpio_find_by_chip_name(const char *chip_name, unsigned gpio_offset)
+{
+	struct gpio_chip *chip;
+	int gpio;
+
+	chip = gpiochip_find_by_name(chip_name);
+	if (!chip)
+		return -ENODEV;
+
+	gpio = chip->base + gpio_offset;
+
+	return gpio;
+}
+EXPORT_SYMBOL_GPL(gpio_find_by_chip_name);
+
 /* These "optional" allocation calls help prevent drivers from stomping
  * on each other, and help provide better diagnostics in debugfs.
  * They're called even less than the "set direction" calls.
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -145,7 +145,8 @@ extern int __must_check gpiochip_remove(struct gpio_chip *chip);
 extern struct gpio_chip *gpiochip_find(const void *data,
 					int (*match)(struct gpio_chip *chip,
 						     const void *data));
-
+extern struct gpio_chip *gpiochip_find_by_name(const char *name);
+extern int gpio_find_by_chip_name(const char *chip_name, unsigned gpio_offset);
 
 /* Always use the library code for GPIO management calls,
  * or when sleeping may be involved.


From B04825 at freescale.com  Thu Mar  8 21:09:57 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Fri, 9 Mar 2012 02:09:57 +0000
Subject: [PATCH v3 08/11] ASoC: fsl: make fsl_ssi driver compilable on
 ARM/IMX
In-Reply-To: <20120309012653.GG2499@S2101-09.ap.freescale.net>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-9-git-send-email-shawn.guo@linaro.org>
 <4F5912D0.2090800@freescale.com>
 <20120309012653.GG2499@S2101-09.ap.freescale.net>
Message-ID: <4F596674.5030405@freescale.com>

Shawn Guo wrote:

> Something like this:
>
> @@ -496,6 +494,10 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
>          struct snd_soc_pcm_runtime *rtd = substream->private_data;
>          struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
>          struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
> +       unsigned long flags;
> +       int ret = 0;
> +
> +       spin_lock_irqsave(&ssi_lock, flags);
>
>          switch (cmd) {
>          case SNDRV_PCM_TRIGGER_START:
> @@ -517,10 +519,12 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
>                  break;
>
>          default:
> -               return -EINVAL;
> +               ret = -EINVAL;
>          }
>
> -       return 0;
> +       spin_unlock_irqrestore(&ssi_lock, flags);
> +
> +       return ret;
>   }

That's the general idea, but I think it needs more study.  I don't 
consider this to be a bug that needs to be fixed ASAP, since it's never 
been an actual problem so far.  For instance, do we need to protect 
between hw_params and _trigger?

-- 
Timur Tabi
Linux kernel developer at Freescale


From B04825 at freescale.com  Thu Mar  8 21:11:41 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Fri, 9 Mar 2012 02:11:41 +0000
Subject: [PATCH v3 00/11] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <20120309011914.GF2499@S2101-09.ap.freescale.net>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <4F5910EE.8090408@freescale.com>
 <20120309011914.GF2499@S2101-09.ap.freescale.net>
Message-ID: <4F5966DC.6090201@freescale.com>

Shawn Guo wrote:
> Are you testing the patch set on top of the SHA below, which I
> mentioned in the cover letter?
>
>    3030763 (Merge tag 'asoc-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into topic/asoc)
>
> I see the similar problem on the following SHA with my testing on
> imx-sgtl5000.
>
>    1a8feca (Merge branch 'for-3.4' into asoc-next)

It appears the problem is with for-3.4 itself.  I'm running git-bisect now 
to narrow it down.

-- 
Timur Tabi
Linux kernel developer at Freescale


From tony at atomide.com  Thu Mar  8 21:16:33 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 8 Mar 2012 18:16:33 -0800
Subject: [GIT PULL] ARM: OMAP2+: hwmod data: cleanup in preparation for
 link array removal
In-Reply-To: <alpine.DEB.2.00.1203081900500.26543@utopia.booyaka.com>
References: <alpine.DEB.2.00.1203072102150.21662@utopia.booyaka.com>
 <20120309014016.GC12083@atomide.com>
 <alpine.DEB.2.00.1203081851570.9551@utopia.booyaka.com>
 <alpine.DEB.2.00.1203081900500.26543@utopia.booyaka.com>
Message-ID: <20120309021633.GE12083@atomide.com>

* Paul Walmsley <paul at pwsan.com> [120308 18:07]:
> Hi
> 
> on second thought...
> 
> On Thu, 8 Mar 2012, Paul Walmsley wrote:
> 
> > On Thu, 8 Mar 2012, Tony Lindgren wrote:
> > 
> > > Got these now merged into l-o master, but ran into a merge
> > > conflict with already queued sr branch. Resolved it by using
> > > your version except left out vdd_name.
> > 
> > Definitely we want the vdd_name fields.  Other than that it looks okay.  
> 
> I guess that other SR series that you merged removed the vdd_name fields?

So it seems, commit cea6b942124683305280962969599fed36f0ea7e. Then
the interrupts we added there for smartreflex it seems.
 
> If so then yeah, we'd better leave those out.
> 
> This means that I'm going to have to rebase those big hwmod data changes 
> :-(
> 
> Can you send me a stable commit for that?

Bummer :( What we already have queued is the sr branch at commit
bb887688bccb48d94fa873f0f6cc7e7e3e4dc05e.

Regards,

Tony


From benh at kernel.crashing.org  Thu Mar  8 21:32:45 2012
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Fri, 09 Mar 2012 13:32:45 +1100
Subject: [PATCH 1/1] of: add dma-mask binding
In-Reply-To: <20120309005923.2E04F3E0901@localhost>
References: <1331119575-6638-1-git-send-email-plagnioj@jcrosoft.com>
 <4F5793E9.9010100@gmail.com> <20120307173437.GC17087@game.jcrosoft.org>
 <20120309005923.2E04F3E0901@localhost>
Message-ID: <1331260365.3105.46.camel@pasglop>

On Thu, 2012-03-08 at 17:59 -0700, Grant Likely wrote:

> > > This would need some documentation. There is already "dma-ranges"
> > > defined for OF which nay do what's needed.
> > what is dma-ranges I see no doc about it
> > but I don't think it could be used for the dma mask
> 
> As Rob says, it's documented in ePAPR.

dma-ranges is generally defined for bridges to indicate the dma window
to system memory, it's not been by actual devices so far. It provides
the opposite of "ranges", ie a translation from children to parent
address space.

So it's not quite the same thing.

Now the fact that we are limited to power-of-2 masks is a Linux
implementation detail. We might want to make the device-tree a bit more
flexible and use something like dma-limit instead. However hardware
limits tend to be in term of number of bits anyways so it's not a big
issue.

I don't see a need to keep a "ranges" type of semantic. If we ever do
that we can do a new binding for it or add a dma-base...

> We could merely add an empty dma_mask u64 to the containing struct
> platform_device and then assign the pointer to dev.dma_mask if it is
> needed.  That would eliminate the malloc.

Agreed.

>   Or we could by default
> use dev->dev.dma_mask = &dev->dev.coherent_dma_mask;  Drivers or
> notifier code could override whatever we setup here as the default.
> 
> dma-ranges really is the property that should be used for this, but
> dma-ranges can describe a different set of permutations than dma_mask.

I don't think so. As I said, dma-ranges is about a bridge/bus exposing
DMA windows & translations. It has nothing to do with the device
intrinsic DMA'ing capabilities.
 
Cheers,
Ben.




From richard.zhao at freescale.com  Thu Mar  8 21:34:19 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Fri, 9 Mar 2012 10:34:19 +0800
Subject: [PATCH v5 0/4] common clk framework
In-Reply-To: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
Message-ID: <20120309023418.GF3261@b20223-02.ap.freescale.net>

Hello Mike,

The main interface for clk implementer is to register clocks dynamically.
I think it highly depends on clk DT bindings. From the patch Grant sent
out, it looks like he doesn't like one node per clk. So how do we
register clocks dynamically? You have any sample code?

Thanks
Richard



From lost.distance at yahoo.com  Thu Mar  8 21:47:24 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 9 Mar 2012 02:47:24 +0000 (GMT)
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <1331242494-3157-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <1331261244.65321.YahooMailClassic@web29007.mail.ird.yahoo.com>

Thanks Paul.

The hx4700 patch works for me on linux-3.3.0-rc6.
I'm not able to test the magician patch.

Tested-by: Paul Parsons <lost.distance at yahoo.com>

--- On Thu, 8/3/12, Paul Gortmaker <paul.gortmaker at windriver.com> wrote:
> commit
> 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)
> 
> ? "regulator: Remove support for supplies specified by
> struct device"
> 
> deletes the field from the struct, but this platform was
> still trying
> to set those fields.? Convert them to use the
> REGULATOR_SUPPLY macro.
> 
> arch/arm/mach-pxa/magician.c:581: error: unknown field 'dev'
> specified in initializer
> arch/arm/mach-pxa/magician.c:581: warning: initialization
> from incompatible pointer type
> arch/arm/mach-pxa/magician.c:585: error: unknown field 'dev'
> specified in initializer
> arch/arm/mach-pxa/magician.c:585: warning: initialization
> from incompatible pointer type
> 
> arch/arm/mach-pxa/hx4700.c:683: error: unknown field 'dev'
> specified in initializer
> arch/arm/mach-pxa/hx4700.c:683: warning: initialization from
> incompatible pointer type
> arch/arm/mach-pxa/hx4700.c:687: error: unknown field 'dev'
> specified in initializer
> arch/arm/mach-pxa/hx4700.c:687: warning: initialization from
> incompatible pointer type
> 
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> ---
> 
> [v3: fix arg2 in REGULATOR_SUPPLY to have correct names ]
> 
> diff --git a/arch/arm/mach-pxa/hx4700.c
> b/arch/arm/mach-pxa/hx4700.c
> index f2c23ea..b6a338b 100644
> --- a/arch/arm/mach-pxa/hx4700.c
> +++ b/arch/arm/mach-pxa/hx4700.c
> @@ -679,14 +679,8 @@ static struct platform_device
> power_supply = {
> ? */
>  
>  static struct regulator_consumer_supply bq24022_consumers[]
> = {
> -??? {
> -??? ??? .dev =
> &gpio_vbus.dev,
> -??? ??? .supply =
> "vbus_draw",
> -??? },
> -??? {
> -??? ??? .dev =
> &power_supply.dev,
> -??? ??? .supply = "ac_draw",
> -??? },
> +??? REGULATOR_SUPPLY("vbus_draw",
> "gpio-vbus"),
> +??? REGULATOR_SUPPLY("ac_draw",
> "pda-power"),
>  };
>  
>  static struct regulator_init_data bq24022_init_data = {
> diff --git a/arch/arm/mach-pxa/magician.c
> b/arch/arm/mach-pxa/magician.c
> index 3d6baf9..1a18e63 100644
> --- a/arch/arm/mach-pxa/magician.c
> +++ b/arch/arm/mach-pxa/magician.c
> @@ -577,14 +577,8 @@ static struct platform_device
> power_supply = {
> ? */
>  
>  static struct regulator_consumer_supply bq24022_consumers[]
> = {
> -??? {
> -??? ??? .dev =
> &gpio_vbus.dev,
> -??? ??? .supply =
> "vbus_draw",
> -??? },
> -??? {
> -??? ??? .dev =
> &power_supply.dev,
> -??? ??? .supply = "ac_draw",
> -??? },
> +??? REGULATOR_SUPPLY("vbus_draw",
> "gpio-vbus"),
> +??? REGULATOR_SUPPLY("ac_draw",
> "pda-power"),
>  };
>  
>  static struct regulator_init_data bq24022_init_data = {
> -- 
> 1.7.9.1
> 
> 


From axel.lin at gmail.com  Thu Mar  8 21:59:56 2012
From: axel.lin at gmail.com (Axel Lin)
Date: Fri, 9 Mar 2012 10:59:56 +0800
Subject: [PATCH v10] Regulator: Add Anatop regulator driver
In-Reply-To: <1331200744-5986-1-git-send-email-paul.liu@linaro.org>
References: <1331200744-5986-1-git-send-email-paul.liu@linaro.org>
Message-ID: <CAF+7xWmDUhzuaPXuGRsr2b4ZjCjxgwpv0hpvMrGqNz3gjUeW0A@mail.gmail.com>

> + ? ? ? if (anatop_reg->control_reg) {
> + ? ? ? ? ? ? ? sel = (uv - anatop_reg->min_voltage) / 25000;

sel = DIV_ROUND_UP(uv - anatop_reg->min_voltage, 25000);

Use DIV_ROUND_UP to avoid the possible truncate of integer division.
This ensures the selected volatge falls within the specified range.


> +static int __devexit anatop_regulator_remove(struct platform_device *pdev)
> +{
> + ? ? ? struct regulator_dev *rdev = platform_get_drvdata(pdev);
> + ? ? ? struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
> + ? ? ? kfree(sreg->name);
> + ? ? ? regulator_unregister(rdev);
Do regulator_unregister before kfree sreg->name.


From shawn.guo at linaro.org  Thu Mar  8 22:19:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 9 Mar 2012 11:19:11 +0800
Subject: [PATCH v3 10/11] ASoC: fsl: let fsl_ssi work with imx pcm and
 machine drivers
In-Reply-To: <4F591A69.9060401@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-11-git-send-email-shawn.guo@linaro.org>
 <4F591A69.9060401@freescale.com>
Message-ID: <20120309031909.GJ2499@S2101-09.ap.freescale.net>

On Thu, Mar 08, 2012 at 02:45:29PM -0600, Timur Tabi wrote:
> Shawn Guo wrote:
> 
> > +	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx1-ssi")) {
> 
> I wonder if the i.MX code should be protected by an #ifdef.  There's no
> point in compiling this code on PowerPC.
> 
I'm not really fond of #ifdef.  The i.MX code is not that much after
all.

> > +		/*
> > +		 * FIXME: The dma burst size must equal to ssi watermark
> > +		 * setting on imx.  We have burstsize be "fifo_depth - 2"
> > +		 * here because "fifo_depth - 2" rather than fifo_depth is
> > +		 * being written into watermark register in fsl_ssi_startup().
> > +		 * Is this something needs to be fixed for PowerPC?
> 
> Setting the watermark to fifo_depth-2 allows the SSI to continue storing
> data into the FIFO (during capture) in the case the DMA engine isn't fast
> enough.  I don't want the FIFO to be completely full before we start the DMA.
> 
> For playback, it's the same thing.  I can't be sure the FIFO is completely
> empty when it's time to DMA more data.
> 
Ok, got you.  We used to set fifo_depth on imx-ssi not the value given
by hardware manual, but the one already tuned.

So all we need is to encode the hardware value in device tree property
"fsl,fifo-depth", and it just works.  I will remove this "FIXME". 

> > +		 */
> > +		ssi_private->dma_params_tx.burstsize =
> > +			ssi_private->fifo_depth - 2;
> > +		ssi_private->dma_params_rx.burstsize =
> > +			ssi_private->fifo_depth - 2;
> > +		ssi_private->dma_params_tx.dma_addr =
> > +			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
> > +		ssi_private->dma_params_rx.dma_addr =
> > +			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
> 
> So I'm a little confused by this new binding.  I went through a lot of
> work to remove DMA-specific data from the SSI driver, and here you are
> adding a bunch of it back.  What you're doing here -- I'm doing it in the
> DMA driver where it belongs.

I'm not sure these all belong to DMA driver.  These are all
configurations/parameters of SSI, which are related to DMA though.
I see fsl_dma are handling these, but I do not fully agree with that,
because we end up with fsl_dma driver accessing SSI node and
"struct ccsr_ssi" which should be SSI private data.

Secondly, this is the way that how imx-ssi and imx-pcm-dma works and
interacts.  If we want to move these stuff into imx-pcm-dma, we need
a good story to convince imx-ssi users that why it's better than what
they currently do.

> 
> > +		/*
> > +		 * TODO: This is a temporary solution and should be changed
> > +		 * to use generic DMA binding later when the helplers get in.
> > +		 */
> > +		ret = of_property_read_u32_array(pdev->dev.of_node,
> > +					"fsl,ssi-dma-events", dma_events, 2);
> > +		if (ret) {
> > +			dev_err(&pdev->dev, "could not get dma events\n");
> > +			goto error_irq;
> > +		}
> > +		ssi_private->dma_params_tx.dma = dma_events[0];
> > +		ssi_private->dma_params_rx.dma = dma_events[1];
> 
> of_property_read_u32_array seems overkill for just two integers.
> 
Hmm, I do not think so.

Device tree maintainers created helpers of_property_read_u32 and
of_property_read_u32_array to ease the user and make the operation
less error prone.  Looking at the of_property_read_u32 implementation,
it's even calling into of_property_read_u32_array.  So I do not think
it's overkill for reading two integers in any way.

static inline int of_property_read_u32(const struct device_node *np,
                                       const char *propname,
                                       u32 *out_value)
{
        return of_property_read_u32_array(np, propname, out_value, 1);
}

> ssi_private->dma_params_tx.dma = be32_to_cpu(prop[0]);
> ssi_private->dma_params_rx.dma = be32_to_cpu(prop[1]);
> 

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Thu Mar  8 22:21:31 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 9 Mar 2012 11:21:31 +0800
Subject: [PATCH v3 08/11] ASoC: fsl: make fsl_ssi driver compilable on
 ARM/IMX
In-Reply-To: <4F596674.5030405@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-9-git-send-email-shawn.guo@linaro.org>
 <4F5912D0.2090800@freescale.com>
 <20120309012653.GG2499@S2101-09.ap.freescale.net>
 <4F596674.5030405@freescale.com>
Message-ID: <20120309032128.GK2499@S2101-09.ap.freescale.net>

On Fri, Mar 09, 2012 at 02:09:57AM +0000, Tabi Timur-B04825 wrote:
> That's the general idea, but I think it needs more study.  I don't 
> consider this to be a bug that needs to be fixed ASAP, since it's never 
> been an actual problem so far.  For instance, do we need to protect 
> between hw_params and _trigger?
> 
Ok, I will leave it to you with a big "FIXME" comment then.

-- 
Regards,
Shawn


From axel.lin at gmail.com  Thu Mar  8 22:45:15 2012
From: axel.lin at gmail.com (Axel Lin)
Date: Fri, 9 Mar 2012 11:45:15 +0800
Subject: [PATCH v10] Regulator: Add Anatop regulator driver
In-Reply-To: <1331200744-5986-1-git-send-email-paul.liu@linaro.org>
References: <1331200744-5986-1-git-send-email-paul.liu@linaro.org>
Message-ID: <CAF+7xWm4R02eK0a-q-yTF16fm4tGQUf7XUQK8+KtPNhjnzff5A@mail.gmail.com>

> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -213,6 +213,14 @@ config REGULATOR_PCAP
> ? ? ? ? This driver provides support for the voltage regulators of the
> ? ? ? ? PCAP2 PMIC.
>
> +config REGULATOR_ANATOP
> + ? ? ? tristate "Freescale i.MX on-chip ANATOP LDO regulators"
> + ? ? ? depends on MFD_ANATOP
> + ? ? ? help
> + ? ? ? ? Say y here to support Freescale i.MX on-chip ANATOP LDOs
> + ? ? ? ? regulators. It is recommended that this option be
> + ? ? ? ? enabled on i.MX6 platform.
> +
> ?config REGULATOR_MC13XXX_CORE
> ? ? ? ?tristate
>
> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
> index 503bac8..8440871 100644
> --- a/drivers/regulator/Makefile
> +++ b/drivers/regulator/Makefile
> @@ -48,5 +48,6 @@ obj-$(CONFIG_REGULATOR_AB8500) ? ? ? ?+= ab8500.o
> ?obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
> ?obj-$(CONFIG_REGULATOR_TPS65910) += tps65910-regulator.o
> ?obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
> +obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
>
> ?ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG

Looks like your patch is against Linus' tree.
Currently, we have sorted the Kconfig entries and Makefile entries in
Mark's tree.
The Kconfig entries are sorted by vender name first, then driver name.
The Makefile entries are sorted by by alphabetical order.

Regards,
Axel


From paul at pwsan.com  Thu Mar  8 22:51:56 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 8 Mar 2012 20:51:56 -0700 (MST)
Subject: [PATCH 5/9] ARM: OMAP36xx: hwmod data: fix SmartReflex interface
 data
In-Reply-To: <20120228111054.808.16941.stgit@dusk>
References: <20120228110943.808.73639.stgit@dusk>
 <20120228111054.808.16941.stgit@dusk>
Message-ID: <alpine.DEB.2.00.1203082051150.26656@utopia.booyaka.com>


Dropping this patch from this series due to conflicts with the SmartReflex 
branch.  It will be moved to a subsequent series.


- Paul


From paul at pwsan.com  Thu Mar  8 22:57:41 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 8 Mar 2012 20:57:41 -0700 (MST)
Subject: [GIT PULL] ARM: OMAP2+: hwmod: miscellaneous changes for 3.4
Message-ID: <alpine.DEB.2.00.1203082056230.26656@utopia.booyaka.com>

Hi Tony

The following changes since commit bb887688bccb48d94fa873f0f6cc7e7e3e4dc05e:

  Merge branch 'for_3.4/cleanup/sr' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into sr (2012-03-05 14:25:35 -0800)

are available in the git repository at:

  git://git.pwsan.com/linux-2.6 hwmod_misc_devel_3.4

for you to fetch changes up to 7ef827505cbc58660ee18e5c4080ed8072022162:

  ARM: OMAP2+: hwmod: manage the wake-up latency constraints (2012-03-08 20:04:45 -0700)


- Paul


----------------------------------------------------------------
Jean Pihet (1):
      ARM: OMAP2+: hwmod: manage the wake-up latency constraints

Paul Walmsley (1):
      ARM: OMAP36xx: hwmod data: fix SmartReflex interface data

 arch/arm/mach-omap2/omap_hwmod.c             |   54 +++++++++++++++++++++++++-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c   |   54 +++++++++++++++++++-------
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    5 ++
 3 files changed, 98 insertions(+), 15 deletions(-)


From B04825 at freescale.com  Thu Mar  8 23:02:40 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Fri, 9 Mar 2012 04:02:40 +0000
Subject: [PATCH v3 10/11] ASoC: fsl: let fsl_ssi work with imx pcm and
 machine drivers
In-Reply-To: <20120309031909.GJ2499@S2101-09.ap.freescale.net>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-11-git-send-email-shawn.guo@linaro.org>
 <4F591A69.9060401@freescale.com>
 <20120309031909.GJ2499@S2101-09.ap.freescale.net>
Message-ID: <4F5980DE.9050002@freescale.com>

Shawn Guo wrote:

> Ok, got you.  We used to set fifo_depth on imx-ssi not the value given
> by hardware manual, but the one already tuned.

What do you mean by "already tuned".  Tuned by whom?

>>> +		 */
>>> +		ssi_private->dma_params_tx.burstsize =
>>> +			ssi_private->fifo_depth - 2;
>>> +		ssi_private->dma_params_rx.burstsize =
>>> +			ssi_private->fifo_depth - 2;
>>> +		ssi_private->dma_params_tx.dma_addr =
>>> +			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
>>> +		ssi_private->dma_params_rx.dma_addr =
>>> +			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
>>
>> So I'm a little confused by this new binding.  I went through a lot of
>> work to remove DMA-specific data from the SSI driver, and here you are
>> aFrom arnd at arndb.de  Mon Mar 12 12:43:25 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 12 Mar 2012 16:43:25 +0000
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <20120312161004.GB5050@titan.lakedaemon.net>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <201203120811.23137.arnd@arndb.de>
 <20120312161004.GB5050@titan.lakedaemon.net>
Message-ID: <201203121643.26133.arnd@arndb.de>

On Monday 12 March 2012, Jason Cooper wrote:
> Okay, that's what smelled funny.  wdt and intc both only have registers
> in virtual address space defined.  Can I assume they map like everything
> else to corresponding physical addresses?
> 
> eg wdt at fed20300 -> wdt at f1020300 ?

Yes, correct. Or just uses 20300 as the address if you remap everything
using the ranges property.

	Arnd


From grant.likely at secretlab.ca  Mon Mar 12 12:32:12 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 10:32:12 -0600
Subject: [PATCH 1/2] Documentation/gpio.txt: Explain expected pinctrl
 interaction
In-Reply-To: <CACRpkdbPeVBv5VWefDvib5HmGF0K2gT79Mx7g-yviyQj33+Z-w@mail.gmail.com>
References: <1329719263-18971-1-git-send-email-swarren@nvidia.com>
 <CACRpkdbPeVBv5VWefDvib5HmGF0K2gT79Mx7g-yviyQj33+Z-w@mail.gmail.com>
Message-ID: <20120312163212.70E283E07B0@localhost>

On Tue, 21 Feb 2012 11:46:03 +0100, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Mon, Feb 20, 2012 at 7:27 AM, Stephen Warren <swarren at nvidia.com> wrote:
> 
> > Update gpio.txt based on recent discussions regarding interaction with the
> > pinctrl subsystem.
> >
> > Previously, gpio_request() was described as explicitly not performing any
> > required mux setup operations etc.
> >
> > Now, gpio_request() is explicitly as explicitly performing any required mux
> > setup operations where possible. In the case it isn't, platform code is
> > required to have set up any required muxing or other configuration prior to
> > gpio_request() being called, in order to maintain the same semantics.
> >
> > This is achieved by gpiolib drivers calling e.g. pinctrl_request_gpio() in
> > their .request() operation.
> >
> > Signed-off-by: Stephen Warren <swarren at nvidia.com>
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> 
> Grant can you take this one? I'd prefer for you to have a look at
> it as well.

I've taken this one, but left the 2nd for Olof.

g.



From grant.likely at secretlab.ca  Mon Mar 12 12:38:38 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 10:38:38 -0600
Subject: [PATCH RESEND v3 1/2] GPIO: LPC32xx: Fix missing bit selection
 mask
In-Reply-To: <1330984871-411-1-git-send-email-stigge@antcom.de>
References: <1330984871-411-1-git-send-email-stigge@antcom.de>
Message-ID: <20120312163838.AABCC3E07B0@localhost>

On Mon,  5 Mar 2012 23:01:10 +0100, Roland Stigge <stigge at antcom.de> wrote:
> Add missing mask to pin bit selection in gpio-lpc32xx.c
> (#define GPIO3_PIN_IN_SEL)
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>
> Acked-by: Arnd Bergmann <arnd at arndb.de>

Applied, thx.

g.

> 
> ---
>  drivers/gpio/gpio-lpc32xx.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> --- linux-2.6.orig/drivers/gpio/gpio-lpc32xx.c
> +++ linux-2.6/drivers/gpio/gpio-lpc32xx.c
> @@ -59,7 +59,7 @@
>  #define GPO3_PIN_TO_BIT(x)			(1 << (x))
>  #define GPIO012_PIN_IN_SEL(x, y)		(((x) >> (y)) & 1)
>  #define GPIO3_PIN_IN_SHIFT(x)			((x) == 5 ? 24 : 10 + (x))
> -#define GPIO3_PIN_IN_SEL(x, y)			((x) >> GPIO3_PIN_IN_SHIFT(y))
> +#define GPIO3_PIN_IN_SEL(x, y)			(((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
>  #define GPIO3_PIN5_IN_SEL(x)			(((x) >> 24) & 1)
>  #define GPI3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)
>  
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From robherring2 at gmail.com  Mon Mar 12 14:33:28 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 12 Mar 2012 13:33:28 -0500
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <201203112134.45302.arnd@arndb.de>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-4-git-send-email-robherring2@gmail.com>
 <201203112134.45302.arnd@arndb.de>
Message-ID: <4F5E4178.50801@gmail.com>

On 03/11/2012 04:34 PM, Arnd Bergmann wrote:
> On Sunday 11 March 2012, Rob Herring wrote:
>> From: Rob Herring <rob.herring at calxeda.com>
>>
>> Several platforms create IOMEM defines for casting to 'void __iomem *',
>> and other platforms are incorrectly using __io() macro for the same
>> purpose. This creates a common definition and removes all the platform
>> specific versions. Rather than try to make linux/io.h and asm/io.h
>> assembly safe, the assembly version of IOMEM is moved into
>> asm/assembler.h.
> 
> Looks good to me, in order to fix the problem at hand. I'm not sure
> about spreading the IOMEM() macro further, that is largely a separate
> problem and only a question of style, not of correctness as with __io().

Got a better suggestion? I didn't think adding IOMEM to 5 more platforms
or inventing something different was the right path. Hopefully this is a
shrinking problem as things move to DT.

Rob

> Acked-by: Arnd Bergmann <arnd at arndb.de>



From grant.likely at secretlab.ca  Mon Mar 12 12:38:24 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 10:38:24 -0600
Subject: [PATCH RESEND v3 2/2] GPIO: LPC32xx: Add output reading to GPO P3
In-Reply-To: <1330984871-411-2-git-send-email-stigge@antcom.de>
References: <1330984871-411-1-git-send-email-stigge@antcom.de>
 <1330984871-411-2-git-send-email-stigge@antcom.de>
Message-ID: <20120312163824.96F933E07B0@localhost>

On Mon,  5 Mar 2012 23:01:11 +0100, Roland Stigge <stigge at antcom.de> wrote:
> The chip offers the function to detect the current state of output of the GPO
> P3 pins. Useful for reading GPIO output state in Linux' GPIO API, e.g. via
> sysfs.
> 
> Please note that this only reads back the currently programmed output state,
> not the actual electrical level in terms of a GPI function. Finally, GPO3 is
> still just an output.
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>
> Acked-by: Arnd Bergmann <arnd at arndb.de>

Applied, thanks

g.

> 
> ---
>  drivers/gpio/gpio-lpc32xx.c |   17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> --- linux-2.6.orig/drivers/gpio/gpio-lpc32xx.c
> +++ linux-2.6/drivers/gpio/gpio-lpc32xx.c
> @@ -62,9 +62,11 @@
>  #define GPIO3_PIN_IN_SEL(x, y)			(((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
>  #define GPIO3_PIN5_IN_SEL(x)			(((x) >> 24) & 1)
>  #define GPI3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)
> +#define GPO3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)
>  
>  struct gpio_regs {
>  	void __iomem *inp_state;
> +	void __iomem *outp_state;
>  	void __iomem *outp_set;
>  	void __iomem *outp_clr;
>  	void __iomem *dir_set;
> @@ -145,6 +147,7 @@ static struct gpio_regs gpio_grp_regs_p2
>  
>  static struct gpio_regs gpio_grp_regs_p3 = {
>  	.inp_state	= LPC32XX_GPIO_P3_INP_STATE,
> +	.outp_state	= LPC32XX_GPIO_P3_OUTP_STATE,
>  	.outp_set	= LPC32XX_GPIO_P3_OUTP_SET,
>  	.outp_clr	= LPC32XX_GPIO_P3_OUTP_CLR,
>  	.dir_set	= LPC32XX_GPIO_P2_DIR_SET,
> @@ -240,6 +243,12 @@ static int __get_gpi_state_p3(struct lpc
>  	return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
>  }
>  
> +static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
> +	unsigned pin)
> +{
> +	return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
> +}
> +
>  /*
>   * GENERIC_GPIO primitives.
>   */
> @@ -340,6 +349,13 @@ static void lpc32xx_gpo_set_value(struct
>  	__set_gpo_level_p3(group, pin, value);
>  }
>  
> +static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
> +{
> +	struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
> +
> +	return __get_gpo_state_p3(group, pin);
> +}
> +
>  static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
>  {
>  	if (pin < chip->ngpio)
> @@ -427,6 +443,7 @@ static struct lpc32xx_gpio_chip lpc32xx_
>  			.label			= "gpo_p3",
>  			.direction_output	= lpc32xx_gpio_dir_out_always,
>  			.set			= lpc32xx_gpo_set_value,
> +			.get			= lpc32xx_gpo_get_value,
>  			.request		= lpc32xx_gpio_request,
>  			.base			= LPC32XX_GPO_P3_GRP,
>  			.ngpio			= LPC32XX_GPO_P3_MAX,
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From khilman at ti.com  Mon Mar 12 14:42:34 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 12 Mar 2012 11:42:34 -0700
Subject: [PATCH 0/6] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <20120312173425.A6B893E07B0@localhost> (Grant Likely's message of
 "Mon, 12 Mar 2012 11:34:25 -0600")
References: <1329999031-6914-1-git-send-email-tarun.kanti@ti.com>
 <CAMQu2gzdfxJms8cc3VhsVzhGq4f8x1QeY6LU6X+2eFZ4_Yv_bw@mail.gmail.com>
 <20120312173425.A6B893E07B0@localhost>
Message-ID: <87wr6py82t.fsf@ti.com>

Grant Likely <grant.likely at secretlab.ca> writes:

> On Thu, 23 Feb 2012 17:56:33 +0530, "Shilimkar, Santosh" <santosh.shilimkar at ti.com> wrote:
>> On Thu, Feb 23, 2012 at 5:40 PM, Tarun Kanti DebBarma
>> <tarun.kanti at ti.com> wrote:
>> > The cleanup is mostly getting rid of redundant fields in struct gpio_bank{}
>> > as we already have them as part of bank->context now. Also, remove un-used
>> > variable from gpio_irq_handler.
>> >
>> > The fix include correction of _set_gpio_irqenable() implementation and fix
>> > type mismatch of gpio trigger parameter.
>> >
>> > It is baselined on top of Kevin's following series:
>> > gpio/omap: cleanup and runtime PM conversion for v3.4
>> > git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/gpio/runtime-pm-cleanup
>> >
>> > I have applied Benoit's GPIO patches in following series on top of Kevin's
>> > before applying my changes.
>> > gpio/omap: Cleanup and adaptation to Device Tree
>> > git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/dt_gpio
>> >
>> > Series is available here for reference:
>> > git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_further_cleanup_fixes
>> >
>> > Power Test: Off-mode and Retention on OMAP3430 (Suspend and Idle paths).
>> > Functional Test: OMAP2430, OMAP3430SDP, ZOOM3, OMAP4430, OMAP4-BLAZE
>> >
>> > Tarun Kanti DebBarma (6):
>> > ?gpio/omap: remove saved_fallingdetect, saved_risingdetect fields
>> > ?gpio/omap: remove saved_wakeup field from struct gpio_bank
>> > ?gpio/omap: remove suspend_wakeup field from struct gpio_bank
>> > ?gpio/omap: get rid of retrigger variable in gpio_irq_handler
>> > ?gpio/omap: fix trigger type to unsigned
>> > ?gpio/omap: fix _set_gpio_irqenable implementation
>> >
>> > ?drivers/gpio/gpio-omap.c | ? 56 +++++++++++++++++++--------------------------
>> > ?1 files changed, 24 insertions(+), 32 deletions(-)
>> >
>> Nice clean-up series. I have gone through this series one more time
>> Thanks for updating change-logs. I noticed you dropped the edge triggered
>> irq wakeup fix....I see on the list now.... Kevin has fixed that already.
>> 
>> Series looks good to me. You can add:
>> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>
> What's the status of this series?  Should I be expecting a v2?  Or am I supposed
> to pick up this one? (a pull req would make things easier for me)

I haven't been through this one yet.

You can expect a pull req from me when ready.

Kevin


From linus.walleij at linaro.org  Mon Mar 12 15:35:42 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 12 Mar 2012 20:35:42 +0100
Subject: [PATCH 1/3] led-class: change back LEDS_CLASS to tristate instead
 of bool
In-Reply-To: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <CACRpkdYA3kjhnaeC2whfTEynJDB+MO=GQXd6TZfSSRGWzTUZEw@mail.gmail.com>

On Thu, Mar 8, 2012 at 10:11 AM, Bryan Wu <bryan.wu at canonical.com> wrote:

> After moving some core functions to led-core.c, led-class.c can be built as
> module again.
>
> Signed-off-by: Bryan Wu <bryan.wu at canonical.com>

Thanks for driving this Bryan,
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From sr at denx.de  Mon Mar 12 10:05:57 2012
From: sr at denx.de (Stefan Roese)
Date: Mon, 12 Mar 2012 15:05:57 +0100
Subject: [PATCH] stmmac: Add device-tree support
Message-ID: <1331561157-3820-1-git-send-email-sr@denx.de>

This patch adds support to configure the STMMAC ethernet driver via
device-tree instead of platform_data.

Currently, only the properties needed on SPEAr600 are provided. All
other properties should be added once needed on other platforms.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
Cc: Viresh Kumar <viresh.kumar at st.com>
---
 Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66 +++++++++++++++++++-
 2 files changed, 103 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt

diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
new file mode 100644
index 0000000..386a47f
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -0,0 +1,38 @@
+* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
+
+Required properties:
+- compatible: Should be "stm,gmac"
+- reg: Address and length of the register set for the device
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- interrupts: Should contain the STMMAC interrupts
+- interrupt-names: Should contain the interrupt names "macirq"
+  "eth_wake_irq" if this interrupt is supported in the "interrupts"
+  property
+- phy-mode: String, operation mode of the PHY interface.
+  Supported values are: "mii", "rmii", "gmii", "rgmii".
+- phy-addr: MDIO address of the PHY
+
+Optional properties:
+- stm,prog-burst-len: Specify the burst length
+- stm,has-gmac: Indicates that the controller supports 1000Mbps
+- stm,has-pmt: Indicates that the controller supports power management
+- mac-address: 6 bytes, mac address
+
+Examples:
+
+	gmac0: stmmac at e0800000 {
+		compatible = "stm,gmac";
+		reg = <0xe0800000 0x8000>;
+		interrupt-parent = <&vic1>;
+		interrupts = <24 23>;
+		interrupt-names = "macirq", "eth_wake_irq";
+		mac-address = [000000000000]; /* Filled in by U-Boot */
+
+		stm,prog-burst-len = <8>;
+		stm,has-gmac;
+		stm,has-pmt;
+
+		phy-mode = "gmii";
+		phy-addr = <0>;
+	};
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 3aad981..fcf46c7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -24,8 +24,43 @@
 
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
 #include "stmmac.h"
 
+#ifdef CONFIG_OF
+static int __devinit stmmac_probe_config_dt(struct platform_device *pdev,
+					    struct plat_stmmacenet_data *plat,
+					    const char **mac)
+{
+	struct device_node *np = pdev->dev.of_node;
+
+	if (!np)
+		return -ENODEV;
+
+	*mac = of_get_mac_address(np);
+
+	plat->interface = of_get_phy_mode(np);
+	of_property_read_u32(np, "phy-addr", &plat->phy_addr);
+	plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
+					   sizeof(struct stmmac_mdio_bus_data),
+					   GFP_KERNEL);
+
+	/*
+	 * Currently only the properties needed on SPEAr600
+	 * are provided. All other properties should be added
+	 * once needed on other platforms.
+	 */
+	of_property_read_u32(np, "stm,prog-burst-len", &plat->pbl);
+	if (of_get_property(np, "stm,has-gmac", NULL))
+		plat->has_gmac = 1;
+	if (of_get_property(np, "stm,has-pmt", NULL))
+		plat->pmt = 1;
+
+	return 0;
+}
+#endif /* CONFIG_OF */
+
 /**
  * stmmac_pltfr_probe
  * @pdev: platform device pointer
@@ -39,7 +74,8 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
 	struct resource *res;
 	void __iomem *addr = NULL;
 	struct stmmac_priv *priv = NULL;
-	struct plat_stmmacenet_data *plat_dat;
+	struct plat_stmmacenet_data *plat_dat = NULL;
+	const char *mac = NULL;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res)
@@ -58,6 +94,22 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
 		ret = -ENOMEM;
 		goto out_release_region;
 	}
+
+#ifdef CONFIG_OF
+	plat_dat = devm_kzalloc(&pdev->dev, sizeof(struct plat_stmmacenet_data),
+				GFP_KERNEL);
+	if (!plat_dat) {
+		pr_err("%s: ERROR: no memory", __func__);
+		ret = -ENOMEM;
+		goto out_unmap;
+	}
+
+	ret = stmmac_probe_config_dt(pdev, plat_dat, &mac);
+	if (ret) {
+		pr_err("%s: main dt probe failed", __func__);
+		goto out_unmap;
+	}
+#else
 	plat_dat = pdev->dev.platform_data;
 
 	/* Custom initialisation (if needed)*/
@@ -66,6 +118,7 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
 		if (unlikely(ret))
 			goto out_unmap;
 	}
+#endif
 
 	priv = stmmac_dvr_probe(&(pdev->dev), plat_dat, addr);
 	if (!priv) {
@@ -73,6 +126,10 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
 		goto out_unmap;
 	}
 
+	/* Get MAC address if available (DT) */
+	if (mac)
+		memcpy(priv->dev->dev_addr, mac, ETH_ALEN);
+
 	/* Get the MAC information */
 	priv->dev->irq = platform_get_irq_byname(pdev, "macirq");
 	if (priv->dev->irq == -ENXIO) {
@@ -178,6 +235,12 @@ static const struct dev_pm_ops stmmac_pltfr_pm_ops = {
 static const struct dev_pm_ops stmmac_pltfr_pm_ops;
 #endif /* CONFIG_PM */
 
+static const struct of_device_id stmmac_dt_ids[] = {
+	{ .compatible = "stm,gmac", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, stmmac_dt_ids);
+
 static struct platform_driver stmmac_driver = {
 	.probe = stmmac_pltfr_probe,
 	.remove = stmmac_pltfr_remove,
@@ -185,6 +248,7 @@ static struct platform_driver stmmac_driver = {
 		   .name = STMMAC_RESOURCE_NAME,
 		   .owner = THIS_MODULE,
 		   .pm = &stmmac_pltfr_pm_ops,
+		   .of_match_table = of_match_ptr(stmmac_dt_ids),
 		   },
 };
 
-- 
1.7.9.2



From thomas.abraham at linaro.org  Mon Mar 12 10:31:34 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 12 Mar 2012 20:01:34 +0530
Subject: [PATCH 5/5] mmc: sdhci-s3c: setup pins using pinctrl interface
In-Reply-To: <20120312142143.GC14020@sirena.org.uk>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
 <20120312142143.GC14020@sirena.org.uk>
Message-ID: <CAJuYYwQ=vhcrbH3gsMBuLG1D_p=mx_RFbN86+ETPT4bLYrRgEA@mail.gmail.com>

On 12 March 2012 19:51, Mark Brown <broonie at opensource.wolfsonmicro.com> wrote:
> On Sun, Mar 11, 2012 at 06:16:05PM +0530, Thomas Abraham wrote:
>> The platform specific callback to setup the sdhci pin mux and pin config
>> is removed and the pinctrl subsystem interface is used to setup the
>> mux and config.
>
> You've only added pinctrl support for Exynos but this driver is also
> used by SoCs going back to s3c24xx era. ?Either all those SoCs need to
> be converted to use pinctrl or the driver needs to understand both
> methods (eg, using pinctrl if no callback is supplied).

Yes, I agree with your comment. I did refer to manuals of s3c24xx to
Exynos to ensure that the samsung pinctrl driver is generic and
reusable on all samsung soc's. I hope I have not missed out something
important that would require additional tweaks in the samsung pinctrl
driver. The missing bits now are gpio interrupt and wakeup interrupt
support in the samsung pinctrl driver. Once that is complete, I
believe it should be easy to add support for other SoC and convert the
drivers to use pinctrl (other option being to let pinctrl driver hog
all the mappings at boot and remove the cfg_gpio platform callbacks
from the driver).

Thank you Mark for your comments.

Regards,
Thomas.


From grant.likely at secretlab.ca  Mon Mar 12 13:45:03 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 11:45:03 -0600
Subject: [PATCH] gpio/omap: Fix section warning for omap_mpuio_alloc_gc()
In-Reply-To: <87pqcpb7y4.fsf@ti.com>
References: <20120306212605.GY12083@atomide.com> <87pqcpb7y4.fsf@ti.com>
Message-ID: <20120312174503.E06123E07B0@localhost>

On Tue, 06 Mar 2012 15:55:47 -0800, Kevin Hilman <khilman at ti.com> wrote:
> Tony Lindgren <tony at atomide.com> writes:
> 
> > From: Tony Lindgren <tony at atomide.com>
> > Date: Mon, 5 Mar 2012 15:32:38 -0800
> > Subject: [PATCH] gpio/omap: Fix section warning for omap_mpuio_alloc_gc()
> >
> > Make omap_mpuio_alloc_gc() __devinit as omap_gpio_chip_init()
> > is __devinit. Otherwise we get:
> >
> > WARNING: vmlinux.o(.devinit.text+0xa10): Section mismatch in reference
> > from the function omap_gpio_chip_init() to the function .init.text:omap_mpuio_alloc_gc()
> > The function __devinit omap_gpio_chip_init() references
> > a function __init omap_mpuio_alloc_gc().
> > If omap_mpuio_alloc_gc is only used by omap_gpio_chip_init then
> > annotate omap_mpuio_alloc_gc with a matching annotation.
> >
> > Signed-off-by: Tony Lindgren <tony at atomide.com>
> 
> Acked-by: Kevin Hilman <khilman at ti.com>

applied, thx.

g.


From sr at denx.de  Mon Mar 12 11:06:26 2012
From: sr at denx.de (Stefan Roese)
Date: Mon, 12 Mar 2012 16:06:26 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <4F5E0993.9020000@gmail.com>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <4F5E0993.9020000@gmail.com>
Message-ID: <201203121606.26926.sr@denx.de>

Hi Rob,

On Monday 12 March 2012 15:34:59 Rob Herring wrote:
> On 03/12/2012 09:05 AM, Stefan Roese wrote:
> > This patch adds support to configure the STMMAC ethernet driver via
> > device-tree instead of platform_data.
> > 
> > Currently, only the properties needed on SPEAr600 are provided. All
> > other properties should be added once needed on other platforms.
> > 
> > Signed-off-by: Stefan Roese <sr at denx.de>
> > Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
> > Cc: Viresh Kumar <viresh.kumar at st.com>
> > ---
> > 
> >  Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
> >  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66
> >  +++++++++++++++++++- 2 files changed, 103 insertions(+), 1 deletion(-)
> >  create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/net/stmmac.txt
> > b/Documentation/devicetree/bindings/net/stmmac.txt new file mode 100644
> > index 0000000..386a47f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/stmmac.txt
> > @@ -0,0 +1,38 @@
> > +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
> > +
> > +Required properties:
> > +- compatible: Should be "stm,gmac"
> 
> This is too generic. This should be 1 string per version of h/w.

Viresh, Giuseppe, can you please suggest a proper string for the SPEAr600 
STMMAC core, including version?
 
> 'stm' should be 'st' according to vendor-prefixes.txt.

Okay.
 
> > +- reg: Address and length of the register set for the device
> > +- interrupt-parent: Should be the phandle for the interrupt controller
> > +  that services interrupts for this device
> > +- interrupts: Should contain the STMMAC interrupts
> > +- interrupt-names: Should contain the interrupt names "macirq"
> > +  "eth_wake_irq" if this interrupt is supported in the "interrupts"
> > +  property
> 
> You should be able to tell this from the compatible string and number of
> interrupts.

Yes. Currently the driver uses platform_get_irq_byname() to register the 
irq's. That's why I added these properties. Is there something wrong with 
using it this way?
 
> > +- phy-mode: String, operation mode of the PHY interface.
> > +  Supported values are: "mii", "rmii", "gmii", "rgmii".
> > +- phy-addr: MDIO address of the PHY
> 
> This is normally probed or the mdio bus is a sub-node of the MAC node.
> See arch/powerpc/boot/dts/mpc8377_mds.dts for an example.

Okay, I'll rework this.

> > +
> > +Optional properties:
> > +- stm,prog-burst-len: Specify the burst length
> > +- stm,has-gmac: Indicates that the controller supports 1000Mbps
> > +- stm,has-pmt: Indicates that the controller supports power management
> 
> I think these should all be encoded by the compatible string.

You mean that by defining a specific compatible string (e.g.
"st,gmac-spear600"), these settings are implicitly set? And should therefore 
be omitted from the dts?

Thanks,
Stefan


From linus.walleij at linaro.org  Mon Mar 12 15:37:44 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 12 Mar 2012 20:37:44 +0100
Subject: [PATCH 2/3] led-triggers: use atomic kzalloc during led trigger
 registering
In-Reply-To: <CAK5ve-+L9gVBOp4RVe2pTUbBnrb-PEn7ERbWWkb=7A=4qOrdTQ@mail.gmail.com>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
 <1331197863-25564-2-git-send-email-bryan.wu@canonical.com>
 <20120308092913.GF14173@pengutronix.de>
 <CAK5ve-+L9gVBOp4RVe2pTUbBnrb-PEn7ERbWWkb=7A=4qOrdTQ@mail.gmail.com>
Message-ID: <CACRpkdYvfzrdAC1vjT5WD4rk0ozpbXkPtkQpBVMv_WYhdkg7ag@mail.gmail.com>

2012/3/10 Bryan Wu <bryan.wu at canonical.com>:
> 2012/3/8 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
>> On Thu, Mar 08, 2012 at 05:11:02PM +0800, Bryan Wu wrote:
>>> kzalloc might cause sleep and will generate some warning detected by lockdep,
>>> when call led_trigger_register_simple on each cpu cores in SMP. This patch fix
>>> this.
>> The obvious (and IMHO better) alternative is to call
>> led_trigger_register_simple from non-atomic context.
>>
>> For registering this should be OK, shouldn't it?
>>
> Thanks Uwe, it's my bad. I think I should not use on_each_cpu() API to
> run led_trigger_register_simple. on_each_cpu() will disable interrupt.

It might have been my mistake even so not your fault ... :-)

Thanks,
Linus Walleij


From grant.likely at secretlab.ca  Mon Mar 12 13:48:12 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 11:48:12 -0600
Subject: [PATCH 09/12] gpio/twl: Add DT support to gpio-twl4030 driver
In-Reply-To: <1330707024-23730-10-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-10-git-send-email-b-cousson@ti.com>
Message-ID: <20120312174812.6A6BD3E07B0@localhost>

On Fri, 2 Mar 2012 17:50:21 +0100, Benoit Cousson <b-cousson at ti.com> wrote:
> Add the DT support for the I2C GPIO expander inside the twl4030.
> 
> Signed-off-by: Benoit Cousson <b-cousson at ti.com>
> Acked-by: Felipe Balbi <balbi at ti.com>

Acked-by: Grant Likely <grant.likely at secretlab.ca>

> ---
>  .../devicetree/bindings/gpio/gpio-twl4030.txt      |   23 ++++++
>  drivers/gpio/gpio-twl4030.c                        |   79 ++++++++++++-------
>  2 files changed, 73 insertions(+), 29 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
> new file mode 100644
> index 0000000..16695d9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
> @@ -0,0 +1,23 @@
> +twl4030 GPIO controller bindings
> +
> +Required properties:
> +- compatible:
> +  - "ti,twl4030-gpio" for twl4030 GPIO controller
> +- #gpio-cells : Should be two.
> +  - first cell is the pin number
> +  - second cell is used to specify optional parameters (unused)
> +- gpio-controller : Marks the device node as a GPIO controller.
> +- #interrupt-cells : Should be 2.
> +- interrupt-controller: Mark the device node as an interrupt controller
> +  The first cell is the GPIO number.
> +  The second cell is not used.
> +
> +Example:
> +
> +twl_gpio: gpio {
> +    compatible = "ti,twl4030-gpio";
> +    #gpio-cells = <2>;
> +    gpio-controller;
> +    #interrupt-cells = <2>;
> +    interrupt-controller;
> +};
> diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
> index 49e5c6e..94256fe 100644
> --- a/drivers/gpio/gpio-twl4030.c
> +++ b/drivers/gpio/gpio-twl4030.c
> @@ -32,6 +32,8 @@
>  #include <linux/irq.h>
>  #include <linux/gpio.h>
>  #include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/irqdomain.h>
>  
>  #include <linux/i2c/twl.h>
>  
> @@ -256,7 +258,8 @@ static int twl_request(struct gpio_chip *chip, unsigned offset)
>  		 * and vMMC2 power supplies based on card presence.
>  		 */
>  		pdata = chip->dev->platform_data;
> -		value |= pdata->mmc_cd & 0x03;
> +		if (pdata)
> +			value |= pdata->mmc_cd & 0x03;
>  
>  		status = gpio_twl4030_write(REG_GPIO_CTRL, value);
>  	}
> @@ -395,6 +398,7 @@ static int gpio_twl4030_remove(struct platform_device *pdev);
>  static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
>  {
>  	struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
> +	struct device_node *node = pdev->dev.of_node;
>  	int ret, irq_base;
>  
>  	/* maybe setup IRQs */
> @@ -409,6 +413,9 @@ static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
>  		return irq_base;
>  	}
>  
> +	irq_domain_add_legacy(node, TWL4030_GPIO_MAX, irq_base, 0,
> +			      &irq_domain_simple_ops, NULL);
> +
>  	ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO, irq_base);
>  	if (ret < 0)
>  		return ret;
> @@ -416,40 +423,45 @@ static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
>  	twl4030_gpio_irq_base = irq_base;
>  
>  no_irqs:
> -	/*
> -	 * NOTE:  boards may waste power if they don't set pullups
> -	 * and pulldowns correctly ... default for non-ULPI pins is
> -	 * pulldown, and some other pins may have external pullups
> -	 * or pulldowns.  Careful!
> -	 */
> -	ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
> -	if (ret)
> -		dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
> -				pdata->pullups, pdata->pulldowns,
> -				ret);
> -
> -	ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
> -	if (ret)
> -		dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
> -				pdata->debounce, pdata->mmc_cd,
> -				ret);
> -
> -	twl_gpiochip.base = pdata->gpio_base;
> +	twl_gpiochip.base = -1;
>  	twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
>  	twl_gpiochip.dev = &pdev->dev;
>  
> -	/* NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
> -	 * is (still) clear if use_leds is set.
> -	 */
> -	if (pdata->use_leds)
> -		twl_gpiochip.ngpio += 2;
> +	if (pdata) {
> +		twl_gpiochip.base = pdata->gpio_base;
> +
> +		/*
> +		 * NOTE:  boards may waste power if they don't set pullups
> +		 * and pulldowns correctly ... default for non-ULPI pins is
> +		 * pulldown, and some other pins may have external pullups
> +		 * or pulldowns.  Careful!
> +		 */
> +		ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
> +		if (ret)
> +			dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
> +					pdata->pullups, pdata->pulldowns,
> +					ret);
> +
> +		ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
> +		if (ret)
> +			dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
> +					pdata->debounce, pdata->mmc_cd,
> +					ret);
> +
> +		/*
> +		 * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
> +		 * is (still) clear if use_leds is set.
> +		 */
> +		if (pdata->use_leds)
> +			twl_gpiochip.ngpio += 2;
> +	}
>  
>  	ret = gpiochip_add(&twl_gpiochip);
>  	if (ret < 0) {
>  		dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
>  		twl_gpiochip.ngpio = 0;
>  		gpio_twl4030_remove(pdev);
> -	} else if (pdata->setup) {
> +	} else if (pdata && pdata->setup) {
>  		int status;
>  
>  		status = pdata->setup(&pdev->dev,
> @@ -467,7 +479,7 @@ static int gpio_twl4030_remove(struct platform_device *pdev)
>  	struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
>  	int status;
>  
> -	if (pdata->teardown) {
> +	if (pdata && pdata->teardown) {
>  		status = pdata->teardown(&pdev->dev,
>  				pdata->gpio_base, TWL4030_GPIO_MAX);
>  		if (status) {
> @@ -488,12 +500,21 @@ static int gpio_twl4030_remove(struct platform_device *pdev)
>  	return -EIO;
>  }
>  
> +static const struct of_device_id twl_gpio_match[] = {
> +	{ .compatible = "ti,twl4030-gpio", },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, twl_gpio_match);
> +
>  /* Note:  this hardware lives inside an I2C-based multi-function device. */
>  MODULE_ALIAS("platform:twl4030_gpio");
>  
>  static struct platform_driver gpio_twl4030_driver = {
> -	.driver.name	= "twl4030_gpio",
> -	.driver.owner	= THIS_MODULE,
> +	.driver = {
> +		.name	= "twl4030_gpio",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(twl_gpio_match),
> +	},
>  	.probe		= gpio_twl4030_probe,
>  	.remove		= gpio_twl4030_remove,
>  };
> -- 
> 1.7.0.4
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From scottwood at freescale.com  Mon Mar 12 15:39:06 2012
From: scottwood at freescale.com (Scott Wood)
Date: Mon, 12 Mar 2012 14:39:06 -0500
Subject: [PATCH 1/1] of: introduce helper to manage boolean
In-Reply-To: <20120309163608.GQ27213@game.jcrosoft.org>
References: <1328588028-24766-1-git-send-email-plagnioj@jcrosoft.com>
 <20120309014441.8236B3E0903@localhost>
 <20120309100435.GN27213@game.jcrosoft.org>
 <20120309162638.92E813E0880@localhost>
 <20120309163608.GQ27213@game.jcrosoft.org>
Message-ID: <4F5E50DA.6080000@freescale.com>

On 03/09/2012 10:36 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>>> Ugh.  so any value other than 1 returns false?  I think that will surprise
>>>> most people.
>>>>
>>>> I don't like this api or binding.  If it is a bool property, then why isn't
>>>> simply testing for the property existance sufficient?
>>> no if you want to disable it
>>>
>>> if a bool is define in the dtsi and want to disable it int the dts
>>>
>>> if you we can do the the invert
>>>
>>> if !0 => true
>>>
>>> is-ok;			=> true
>>> is-ok = <val != 0>;	=> true
>>> is-ok = <0>;		=> false
>>
>> This is a failure of the dtc tool, not the binding.  Accepting this binding
>> means we have to live with it for a very long time.  It needs to be fixed
>> in dtc instead so that properties can be deleted instead of only modified.
> I understand your idea but today if you put and value in the property it's true.
> 
> So is-ok = <0>; is true also which is illogical as in any language a boolean is
> true (1) or false (0). When I read the property I will understand false not true

You could say similar things about is-ok = "no" or is-ok = "" or is-ok =
"I'd rather you didn't"... it's expected that violating the binding may
produce illogical results.

> And I see no good way to add the "delete" in dtc.

It shouldn't be that hard, just needs a new keyword and/or bit of syntax
to express what you want it to do.

-Scott



From grant.likely at secretlab.ca  Mon Mar 12 13:46:58 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 11:46:58 -0600
Subject: [PATCH 08/12] gpio/twl: Allocate irq_desc dynamically for
 SPARSE_IRQ support
In-Reply-To: <4F575B21.30909@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-9-git-send-email-b-cousson@ti.com> <4F575B21.30909@ti.com>
Message-ID: <20120312174658.132053E07B0@localhost>

On Wed, 7 Mar 2012 13:57:05 +0100, "Cousson, Benoit" <b-cousson at ti.com> wrote:
> Hi Grant,
> 
> That fix is tightly coupled with the previous twl4030-irq change, so it 
> will be good to pulled it with the twl series through MFD if you are OK 
> with that?
> 
> Care to ack this one and the next one?
> 
> Thanks,
> Benoit
> 
> 
> On 3/2/2012 5:50 PM, Benoit Cousson wrote:
> > Do not use the board pdata for irq_base, but allocate them dynamically
> > to allow a proper support of SPARSE_IRQ.
> >
> > Fix an unneeded line wrap.
> >
> > Signed-off-by: Benoit Cousson<b-cousson at ti.com>
> > Acked-by: Felipe Balbi<balbi at ti.com>

Acked-by: Grant Likely <grant.likely at secretlab.ca>

> > ---
> >   drivers/gpio/gpio-twl4030.c |   33 +++++++++++++++++----------------
> >   1 files changed, 17 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
> > index 697396c..49e5c6e 100644
> > --- a/drivers/gpio/gpio-twl4030.c
> > +++ b/drivers/gpio/gpio-twl4030.c
> > @@ -395,23 +395,26 @@ static int gpio_twl4030_remove(struct platform_device *pdev);
> >   static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
> >   {
> >   	struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
> > -	int ret;
> > +	int ret, irq_base;
> >
> >   	/* maybe setup IRQs */
> > -	if (pdata->irq_base) {
> > -		if (is_module()) {
> > -			dev_err(&pdev->dev,
> > -				"can't dispatch IRQs from modules\n");
> > -			goto no_irqs;
> > -		}
> > -		ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO,
> > -					pdata->irq_base);
> > -		if (ret<  0)
> > -			return ret;
> > -		WARN_ON(ret != pdata->irq_base);
> > -		twl4030_gpio_irq_base = ret;
> > +	if (is_module()) {
> > +		dev_err(&pdev->dev, "can't dispatch IRQs from modules\n");
> > +		goto no_irqs;
> > +	}
> > +
> > +	irq_base = irq_alloc_descs(-1, 0, TWL4030_GPIO_MAX, 0);
> > +	if (irq_base<  0) {
> > +		dev_err(&pdev->dev, "Failed to alloc irq_descs\n");
> > +		return irq_base;
> >   	}
> >
> > +	ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO, irq_base);
> > +	if (ret<  0)
> > +		return ret;
> > +
> > +	twl4030_gpio_irq_base = irq_base;
> > +
> >   no_irqs:
> >   	/*
> >   	 * NOTE:  boards may waste power if they don't set pullups
> > @@ -443,9 +446,7 @@ no_irqs:
> >
> >   	ret = gpiochip_add(&twl_gpiochip);
> >   	if (ret<  0) {
> > -		dev_err(&pdev->dev,
> > -				"could not register gpiochip, %d\n",
> > -				ret);
> > +		dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
> >   		twl_gpiochip.ngpio = 0;
> >   		gpio_twl4030_remove(pdev);
> >   	} else if (pdata->setup) {
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From swarren at wwwdotorg.org  Mon Mar 12 14:24:35 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 12 Mar 2012 12:24:35 -0600
Subject: [PATCH V2 2/3] pinctrl: allow concurrent gpio and mux function
 ownership of pins
In-Reply-To: <CACRpkdYdSaNsrr34o2Cc4vS12ee9oY7FG0pxB92mefHZKwdEpA@mail.gmail.com>
References: <1330993336-9538-1-git-send-email-swarren@nvidia.com>	<1330993336-9538-2-git-send-email-swarren@nvidia.com>
 <CACRpkdYdSaNsrr34o2Cc4vS12ee9oY7FG0pxB92mefHZKwdEpA@mail.gmail.com>
Message-ID: <4F5E3F63.5080506@wwwdotorg.org>

On 03/06/2012 03:03 AM, Linus Walleij wrote:
> On Tue, Mar 6, 2012 at 1:22 AM, Stephen Warren <swarren at nvidia.com> wrote:
> 
>> Per recent updates to Documentation/gpio.txt, gpiolib drivers should
>> inform pinctrl when a GPIO is requested. pinctrl then marks that pin as
>> in-use for that GPIO function.
>>
>> When an SoC muxes pins in a group, it's quite possible for the group to
>> contain e.g. 6 pins, but only 4 of them actually be needed by the HW
>> module that's mux'd to them. In this case, the other 2 pins could be
>> used as GPIOs. However, pinctrl marks all the pins within the group as
>> in-use by the selected mux function. To allow the expected gpiolib
>> interaction, separate the concepts of pin ownership into two parts: One
>> for the mux function and one for GPIO usage. Finally, allow those two
>> ownerships to exist in parallel.
>>
>> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> 
> Good, and 100% in accordance with earlier discussions.
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

Linus, now that Grant has ack'd and applied the documentation change
behind this, could you take this one patch into the pinctrl tree. I
assume it's 3.5 material. After the 3.4 merge window closes, I'll
probably come back and ask for a stable pinctrl branch that I can use as
the basis for a Tegra branch that'll contain patch 3 in this series.

(Olof, I assume that's the right way to approach this; having Linus
apply both patches 2/3 in this series to pinctrl is going to make life
difficult in the Tegra tree, since my outstanding patches to convert
Tegra to use pinctrl will touch many of the same files as patch 3 in
this series, in conflicting or dependent ways.)

Thanks.


From rob.lee at linaro.org  Mon Mar 12 14:45:15 2012
From: rob.lee at linaro.org (Rob Lee)
Date: Mon, 12 Mar 2012 13:45:15 -0500
Subject: [git pull] Consolidate cpuidle functionality
In-Reply-To: <20120309174017.081154936f57039b37c50435@canb.auug.org.au>
References: <1330562578-3410-1-git-send-email-rob.lee@linaro.org>
 <87y5reivhb.fsf@ti.com>
 <CAMXH7KEwQM37R++8moXB8Q41_fBXOnVY2hXJGFQmTQ20oeFPEQ@mail.gmail.com>
 <20120309174017.081154936f57039b37c50435@canb.auug.org.au>
Message-ID: <CAMXH7KFrMVzn1tVxWzm1yOVuiaVJoo7x_NHm6XPo3rPDtuM=tQ@mail.gmail.com>

Len and Andrew,

Please consider this an official merge request of this cpuidle
patchset for v3.4.

There were two small conflicts Stephen Rothwell found when merging to
linux-next.  The first conflict is with patch 1/9 in the
drivers/cpuidle/cpuidle.c file which is trivially to resolve.  I'm
told this fixup is trivially enough to not require anyone to carry it.

The second is with patch 2/9 in mach-at91/cpuidle.c due to some minor
cleanup changes.  The fix is also pretty simple but I'm waiting to
hear back about who will carry it.

Please let me know if you need any other action or information on my part.

Thanks,
Rob


On Fri, Mar 9, 2012 at 12:40 AM, Stephen Rothwell <sfr at canb.auug.org.au> wrote:
> Hi Rob,
>
> On Thu, 8 Mar 2012 19:58:23 -0600 Rob Lee <rob.lee at linaro.org> wrote:
>>
>> ? git://git.linaro.org/people/rob_lee/linux.git cpuidle_consol_pull
>>
>> These changes move various functionality duplicated in platform
>> cpuidle drivers to the core cpuidle driver and common arch arm code. Also,
>> the irq disabling in the platform code was removed as all calls into
>> cpuidle_call_idle() will have already called local_irq_disable().
>>
>> This patchset is bisect safe. ?Also, the core cpuidle and arch changes of the
>> first commit do not require any changes to the arch and platform cpuidle
>> drivers, though those arch and platform change should be made to take
>> advantage of the new consolidation function.
>>
>> Stephen, this patch has been reviewed, tested, and ACK'd per the list above but
>> cpuidle maintainer Len Brown has been out on vacation for a couple of weeks so
>> I am sending you this pull request as time is running out to get this into
>> v3.4. ?I've had a brief communication with Andrew Morton about
>> this as well so he is aware of this situation. ?I am fairly new to the
>> community so please let me know if you see anything that needs my attention or
>> anything I should be doing differently.
>
> I will add this tree from today. ?Lets see if anyone screams.
>
> Thanks for adding your subsystem tree as a participant of linux-next. ?As
> you may know, this is not a judgment of your code. ?The purpose of
> linux-next is for integration testing and to lower the impact of
> conflicts between subsystems in the next merge window.
>
> You will need to ensure that the patches/commits in your tree/series have
> been:
> ? ? * submitted under GPL v2 (or later) and include the Contributor's
> ? ? ? ?Signed-off-by,
> ? ? * posted to the relevant mailing list,
> ? ? * reviewed by you (or another maintainer of your subsystem tree),
> ? ? * successfully unit tested, and
> ? ? * destined for the current or next Linux merge window.
>
> Basically, this should be just what you would send to Linus (or ask him
> to fetch). ?It is allowed to be rebased if you deem it necessary.
>
> --
> Cheers,
> Stephen Rothwell
> sfr at canb.auug.org.au
>
> Legal Stuff:
> By participating in linux-next, your subsystem tree contributions are
> public and will be included in the linux-next trees. ?You may be sent
> e-mail messages indicating errors or other issues when the
> patches/commits from your subsystem tree are merged and tested in
> linux-next. ?These messages may also be cross-posted to the linux-next
> mailing list, the linux-kernel mailing list, etc. ?The linux-next tree
> project and IBM (my employer) make no warranties regarding the linux-next
> project, the testing procedures, the results, the e-mails, etc. ?If you
> don't agree to these ground rules, let me know and I'll remove your tree
> from participation in linux-next.


From cbouatmailru at gmail.com  Mon Mar 12 15:42:24 2012
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Mon, 12 Mar 2012 23:42:24 +0400
Subject: [PATCH 4/4] ARM: __io abuse cleanup
In-Reply-To: <1331500100-31351-5-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-5-git-send-email-robherring2@gmail.com>
Message-ID: <20120312194224.GB26116@oksana.dev.rtsoft.ru>

On Sun, Mar 11, 2012 at 04:08:20PM -0500, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> Several platforms incorrectly use __io() for casting to 'void __iomem *'.
> This converts all of those uses to use the common IOMEM macro.
> 
> Reported-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Anton Vorontsov <avorontsov at mvista.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Paul Mundt <lethal at linux-sh.org>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: linux-sh at vger.kernel.org
> ---

For cns3xxx:

Acked-by: Anton Vorontsov <cbouatmailru at gmail.com>

Thanks!

-- 
Anton Vorontsov
Email: cbouatmailru at gmail.com


From paul at pwsan.com  Mon Mar 12 14:42:38 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 12:42:38 -0600 (MDT)
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <1331500100-31351-4-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-4-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.DEB.2.00.1203121242160.11332@utopia.booyaka.com>


For the OMAP3/4 clock data changes:

Acked-by: Paul Walmsley <paul at pwsan.com>



- Paul


From grant.likely at secretlab.ca  Mon Mar 12 11:40:19 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 09:40:19 -0600
Subject: [PATCH 1/4 v5] of_spi: add generic binding support to specify cs
 gpio
In-Reply-To: <20120311182537.GS27213@game.jcrosoft.org>
References: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.co>
 <1331317544-21735-1-git-send-email-plagnioj@jcrosoft.com>
 <20120311140731.2D4F93E0979@localhost>
 <20120311182537.GS27213@game.jcrosoft.org>
Message-ID: <20120312154019.1DB653E0950@localhost>

On Sun, 11 Mar 2012 19:25:37 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> On 08:07 Sun 11 Mar     , Grant Likely wrote:
> > On Fri,  9 Mar 2012 19:25:44 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > > This will allow to use gpio for chip select with no modification in the
> > > driver binding
> > > 
> > > When use the cs-gpios, the gpio number will be passed via the cs_gpio field
> > > and the number of chip select will automatically increased.
> > > 
> > > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > > Cc: devicetree-discuss at lists.ozlabs.org
> > > Cc: spi-devel-general at lists.sourceforge.net
> > > ---
> > > v5:
> > > 	update grant comment to simplify the cs_gpio management
> > > 
> > > Best Regards,
> > > J.
> > >  Documentation/devicetree/bindings/spi/spi-bus.txt |    6 ++
> > >  drivers/spi/spi.c                                 |   55 +++++++++++++++++++-
> > >  include/linux/spi/spi.h                           |    4 ++
> > >  3 files changed, 62 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
> > > index e782add..c253379 100644
> > > --- a/Documentation/devicetree/bindings/spi/spi-bus.txt
> > > +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
> > > @@ -12,6 +12,7 @@ The SPI master node requires the following properties:
> > >  - #size-cells     - should be zero.
> > >  - compatible      - name of SPI bus controller following generic names
> > >      		recommended practice.
> > > +- cs-gpios	  - (optional) gpios chip select.
> > >  No other properties are required in the SPI bus node.  It is assumed
> > >  that a driver for an SPI bus device will understand that it is an SPI bus.
> > >  However, the binding does not attempt to define the specific method for
> > > @@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
> > >  chip selects.  Individual drivers can define additional properties to
> > >  support describing the chip select layout.
> > >  
> > > +If cs-gpios is used the number of chip select will automatically increased.
> > > +
> > >  SPI slave nodes must be children of the SPI master node and can
> > >  contain the following properties.
> > >  - reg             - (required) chip select address of device.
> > > @@ -34,6 +37,9 @@ contain the following properties.
> > >  - spi-cs-high     - (optional) Empty property indicating device requires
> > >      		chip select active high
> > >  
> > > +If a gpio chipselect is used for the SPI slave the gpio number will be passed
> > > +via the cs_gpio
> > > +
> > >  SPI example for an MPC5200 SPI bus:
> > >  	spi at f00 {
> > >  		#address-cells = <1>;
> > > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> > > index b2ccdea..446eee5 100644
> > > --- a/drivers/spi/spi.c
> > > +++ b/drivers/spi/spi.c
> > > @@ -28,6 +28,7 @@
> > >  #include <linux/mod_devicetable.h>
> > >  #include <linux/spi/spi.h>
> > >  #include <linux/of_spi.h>
> > > +#include <linux/of_gpio.h>
> > >  #include <linux/pm_runtime.h>
> > >  #include <linux/export.h>
> > >  
> > > @@ -322,6 +323,7 @@ struct spi_device *spi_alloc_device(struct spi_master *master)
> > >  	spi->dev.parent = &master->dev;
> > >  	spi->dev.bus = &spi_bus_type;
> > >  	spi->dev.release = spidev_release;
> > > +	spi->cs_gpio = -EINVAL;
> > >  	device_initialize(&spi->dev);
> > >  	return spi;
> > >  }
> > > @@ -339,15 +341,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
> > >  int spi_add_device(struct spi_device *spi)
> > >  {
> > >  	static DEFINE_MUTEX(spi_add_lock);
> > > -	struct device *dev = spi->master->dev.parent;
> > > +	struct spi_master *master = spi->master;
> > > +	struct device *dev = master->dev.parent;
> > >  	struct device *d;
> > >  	int status;
> > >  
> > >  	/* Chipselects are numbered 0..max; validate. */
> > > -	if (spi->chip_select >= spi->master->num_chipselect) {
> > > +	if (spi->chip_select >= master->num_chipselect) {
> > >  		dev_err(dev, "cs%d >= max %d\n",
> > >  			spi->chip_select,
> > > -			spi->master->num_chipselect);
> > > +			master->num_chipselect);
> > >  		return -EINVAL;
> > >  	}
> > >  
> > > @@ -371,6 +374,9 @@ int spi_add_device(struct spi_device *spi)
> > >  		goto done;
> > >  	}
> > >  
> > > +	if (master->cs_gpios)
> > > +		spi->cs_gpio = master->cs_gpios[spi->chip_select];
> > > +
> > 
> > I still don't understand the need for this.  Only the master driver will need
> > this data, and it is already stored in the master->cs_gpios array.  Why
> > does it need to get duplicated into the spi_device?
> yeah can drop it
> > 
> > >  	/* Drivers may modify this initial i/o setup, but will
> > >  	 * normally rely on the device being setup.  Devices
> > >  	 * using SPI_CS_HIGH can't coexist well otherwise...
> > > @@ -561,6 +567,45 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
> > >  }
> > >  EXPORT_SYMBOL_GPL(spi_alloc_master);
> > >  
> > > +#ifdef CONFIG_OF
> > > +static int of_spi_register_master(struct spi_master *master)
> > > +{
> > > +	int nb, i;
> > > +	int *cs;
> > > +	struct device_node *np = master->dev.of_node;
> > > +
> > > +	if (!np)
> > > +		return 0;
> > > +
> > > +	nb = of_gpio_named_count(np, "cs-gpios");
> > > +
> > > +	if (nb < 1)
> > > +		return 0;
> > > +
> > > +	cs = devm_kzalloc(&master->dev,
> > > +			  sizeof(int) * (master->num_chipselect + nb),
> > > +			  GFP_KERNEL);
> > 
> > sizeof(*cs)
> > 
> > > +	master->cs_gpios = cs;
> > > +
> > > +	if (!master->cs_gpios)
> > > +		return -ENOMEM;
> > > +
> > > +	memset(cs, -EINVAL, master->num_chipselect);
> > > +	master->num_chipselect += nb;
> > 
> > Looks buggy.  Should be:
> > 	if (nb > master->num_chipselect)
> > 		master->num_chipselect = nb;
> > 
> > However, this is actually quite risky.  Changing the size of
> > num_chipselect without the driver knowing about it will most likely
> > cause breakage in drivers.  Drivers may use it as an array index, and
> > if it gets increased then there will be problems.  In fact, drivers
> > are probably using spi->chip_select as an array or register index so I
> > don't think it can be transparently extended to include gpios.
> > 
> > So, this function must change.  It cannot be called automatically
> > from spi_register_master().  It needs to be a library function that spi bus
> > drivers must call explicitly so they are prepared for a change in the
> > num_chipselect value.
> I'll prefer to let the spi framework manage it

I understand your preference, but it must not carry the risk of breakage.

spi devices cannot be added if the cs number is larger than num_chipselect;
even if those devices are backed by gpios.  The controller driver still
needs to understand they are there and modify it's own num_chipselects
value.  Otherwise transfer requests will pass a CS number larger than
the bus drivers know what to do with.

> > Also, if we're doing this, then the gpio cs manipulation hook should be
> > moved out of spi_bitbang and into the core spi_master.  There should
> > also be a stock function for manipulating gpio chip selects. I don't want
> > spi driver authors under the impression that they should open code the
> > chip select manipulation.
> yeah I was thinking about it too
> 
> how about we split it in two
> 
> num_hw_cs manage by the drivers
> 
> and
> 
> num_gpio_cs for cs gpio
> 
> and num_chipselect (hw + cs) will for internal use
> 
> the gpio cs will be after the hw cs.

As already discussed, don't split the number space.  Keep gpio cs numbers
based at zero and let them overlap the hw cs numbers.

> 
> and we move the gpio cs from spi_bitbang to spi_master

Yes, please move the gpio cs handling.

g.


From grant.likely at secretlab.ca  Mon Mar 12 14:43:36 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 12:43:36 -0600
Subject: [PATCH 0/6] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <87wr6py82t.fsf@ti.com>
References: <1329999031-6914-1-git-send-email-tarun.kanti@ti.com>
 <CAMQu2gzdfxJms8cc3VhsVzhGq4f8x1QeY6LU6X+2eFZ4_Yv_bw@mail.gmail.com>
 <20120312173425.A6B893E07B0@localhost> <87wr6py82t.fsf@ti.com>
Message-ID: <CACxGe6tH5_GsJ1Wa9zSF711qwFgXR9=yp5AsUMKDn5+egwmavg@mail.gmail.com>

On Mon, Mar 12, 2012 at 12:42 PM, Kevin Hilman <khilman at ti.com> wrote:
> Grant Likely <grant.likely at secretlab.ca> writes:
>
>> On Thu, 23 Feb 2012 17:56:33 +0530, "Shilimkar, Santosh" <santosh.shilimkar at ti.com> wrote:
>>> On Thu, Feb 23, 2012 at 5:40 PM, Tarun Kanti DebBarma
>>> <tarun.kanti at ti.com> wrote:
>>> > The cleanup is mostly getting rid of redundant fields in struct gpio_bank{}
>>> > as we already have them as part of bank->context now. Also, remove un-used
>>> > variable from gpio_irq_handler.
>>> >
>>> > The fix include correction of _set_gpio_irqenable() implementation and fix
>>> > type mismatch of gpio trigger parameter.
>>> >
>>> > It is baselined on top of Kevin's following series:
>>> > gpio/omap: cleanup and runtime PM conversion for v3.4
>>> > git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/gpio/runtime-pm-cleanup
>>> >
>>> > I have applied Benoit's GPIO patches in following series on top of Kevin's
>>> > before applying my changes.
>>> > gpio/omap: Cleanup and adaptation to Device Tree
>>> > git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/dt_gpio
>>> >
>>> > Series is available here for reference:
>>> > git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_further_cleanup_fixes
>>> >
>>> > Power Test: Off-mode and Retention on OMAP3430 (Suspend and Idle paths).
>>> > Functional Test: OMAP2430, OMAP3430SDP, ZOOM3, OMAP4430, OMAP4-BLAZE
>>> >
>>> > Tarun Kanti DebBarma (6):
>>> > ?gpio/omap: remove saved_fallingdetect, saved_risingdetect fields
>>> > ?gpio/omap: remove saved_wakeup field from struct gpio_bank
>>> > ?gpio/omap: remove suspend_wakeup field from struct gpio_bank
>>> > ?gpio/omap: get rid of retrigger variable in gpio_irq_handler
>>> > ?gpio/omap: fix trigger type to unsigned
>>> > ?gpio/omap: fix _set_gpio_irqenable implementation
>>> >
>>> > ?drivers/gpio/gpio-omap.c | ? 56 +++++++++++++++++++--------------------------
>>> > ?1 files changed, 24 insertions(+), 32 deletions(-)
>>> >
>>> Nice clean-up series. I have gone through this series one more time
>>> Thanks for updating change-logs. I noticed you dropped the edge triggered
>>> irq wakeup fix....I see on the list now.... Kevin has fixed that already.
>>>
>>> Series looks good to me. You can add:
>>> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>>
>> What's the status of this series? ?Should I be expecting a v2? ?Or am I supposed
>> to pick up this one? (a pull req would make things easier for me)
>
> I haven't been through this one yet.
>
> You can expect a pull req from me when ready.

Perfect, thx.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From swarren at wwwdotorg.org  Mon Mar 12 13:19:25 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 12 Mar 2012 11:19:25 -0600
Subject: [PATCH 1/2] Documentation/gpio.txt: Explain expected pinctrl
 interaction
In-Reply-To: <20120312163212.70E283E07B0@localhost>
References: <1329719263-18971-1-git-send-email-swarren@nvidia.com>
 <CACRpkdbPeVBv5VWefDvib5HmGF0K2gT79Mx7g-yviyQj33+Z-w@mail.gmail.com>
 <20120312163212.70E283E07B0@localhost>
Message-ID: <4F5E301D.9030700@wwwdotorg.org>

On 03/12/2012 10:32 AM, Grant Likely wrote:
> On Tue, 21 Feb 2012 11:46:03 +0100, Linus Walleij <linus.walleij at linaro.org> wrote:
>> On Mon, Feb 20, 2012 at 7:27 AM, Stephen Warren <swarren at nvidia.com> wrote:
>>
>>> Update gpio.txt based on recent discussions regarding interaction with the
>>> pinctrl subsystem.
>>>
>>> Previously, gpio_request() was described as explicitly not performing any
>>> required mux setup operations etc.
>>>
>>> Now, gpio_request() is explicitly as explicitly performing any required mux
>>> setup operations where possible. In the case it isn't, platform code is
>>> required to have set up any required muxing or other configuration prior to
>>> gpio_request() being called, in order to maintain the same semantics.
>>>
>>> This is achieved by gpiolib drivers calling e.g. pinctrl_request_gpio() in
>>> their .request() operation.
>>>
>>> Signed-off-by: Stephen Warren <swarren at nvidia.com>
>>
>> Acked-by: Linus Walleij <linus.walleij at linaro.org>
>>
>> Grant can you take this one? I'd prefer for you to have a look at
>> it as well.
> 
> I've taken this one, but left the 2nd for Olof.

Grant, did you take V2 of this patch? I assume not since you replied to V1.

For reference, that's:
http://lkml.org/lkml/2012/3/5/533

Thanks.


From khilman at ti.com  Mon Mar 12 14:52:41 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 12 Mar 2012 11:52:41 -0700
Subject: [PATCH v3 05/13] gpio/omap: get rid of retrigger variable in
 gpio_irq_handler
In-Reply-To: <1331118963-26364-6-git-send-email-tarun.kanti@ti.com> (Tarun
 Kanti DebBarma's message of "Wed, 7 Mar 2012 16:45:55 +0530")
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-6-git-send-email-tarun.kanti@ti.com>
Message-ID: <87k42py7ly.fsf@ti.com>

Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:

> This local variable is just assigned zero and then OR'ed
> with isr. It does not appear to serve any purpose and so
> removing it.

Still missing the changelog changes I requested in v1.

Kevin

> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Acked-by: Felipe Balbi <balbi at ti.com>
> ---
>  drivers/gpio/gpio-omap.c |    3 ---
>  1 files changed, 0 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 3765654..de5fe8f 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -626,7 +626,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
>  	u32 isr;
>  	unsigned int gpio_irq, gpio_index;
>  	struct gpio_bank *bank;
> -	u32 retrigger = 0;
>  	int unmasked = 0;
>  	struct irq_chip *chip = irq_desc_get_chip(desc);
>  
> @@ -663,8 +662,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
>  			chained_irq_exit(chip, desc);
>  		}
>  
> -		isr |= retrigger;
> -		retrigger = 0;
>  		if (!isr)
>  			break;


From rob.lee at linaro.org  Mon Mar 12 13:03:48 2012
From: rob.lee at linaro.org (Rob Lee)
Date: Mon, 12 Mar 2012 12:03:48 -0500
Subject: linux-next: manual merge of the cpuidle-cons tree with the
 arm-soc tree
In-Reply-To: <4F5E1ECC.1040605@atmel.com>
References: <20120309183732.512d3676599da324f4747219@canb.auug.org.au>
 <4F5E1ECC.1040605@atmel.com>
Message-ID: <CAMXH7KH_vgri3EPRvkXR+LddRUc=0ve=4u7yr51utBfgV5bF3w@mail.gmail.com>

Arnd, Stephen, Nicolas, Daniel,

On Mon, Mar 12, 2012 at 11:05 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> On 03/09/2012 08:37 AM, Stephen Rothwell :
>> Hi Rob,
>>
>> Today's linux-next merge of the cpuidle-cons tree got a conflict
>> in arch/arm/mach-at91/cpuidle.c between commit 00482a4078f4 ("ARM:
>> at91: implement the standby function for pm/cpuidle") from the
>> arm-soc tree and commit 7a1f6e72dce1 ("ARM: at91: Consolidate time
>> keeping and irq enable") from the cpuidle-cons tree.
>>
>> I fixed it up (I think - see below) and can carry the fix as
>> necessary.
>
> Yes: resolution correct. Please carry it.
>

Who should carry this fixup and related necessary at91 changes?  Me?
FYI, my at91 changes are dependent on my core cpuidle change, but my
core cpuidle changes do not require any at91 changes as the at91 and
other platform changes were only made to consolidate duplicate code.

Best Regards,
Rob

> Thanks to Rob and Daniel for their answers.
>

Thank you as well Nicolas.

> Best regards,
> - --
> Nicolas Ferre
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> Version: GnuPG v1.4.11 (GNU/Linux)
> Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/
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> MkXiO7pQAOdGtojqSrZI8Sp0kxtfdR6QlNu5o518yvlKIkxbWJoXdVty9+MuciOv
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> =rZpG
> -----END PGP SIGNATURE-----


From vinod.koul at intel.com  Mon Mar 12 12:29:56 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Mon, 12 Mar 2012 21:59:56 +0530
Subject: [PATCH v3 1/2] dmaengine: Add support for per xfer specific
 privatedata
In-Reply-To: <1331548336-27802-1-git-send-email-kumarrav@codeaurora.org>
References: <1331548336-27802-1-git-send-email-kumarrav@codeaurora.org>
Message-ID: <1331569796.1727.9.camel@vkoul-udesk3>

On Mon, 2012-03-12 at 16:02 +0530, Ravi Kumar V wrote:
> Add new argument to DMA SG and Interleave mode for passing
> per transfer specific private data, using this it enables the
> dma devices which needs to pass the parameters which changes per
> each transfer.
> 
> Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
> ---
>  include/linux/dmaengine.h |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index 679b349..b8f0495 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -570,7 +570,7 @@ struct dma_device {
>  		struct dma_chan *chan,
>  		struct scatterlist *dst_sg, unsigned int dst_nents,
>  		struct scatterlist *src_sg, unsigned int src_nents,
> -		unsigned long flags);
> +		unsigned long flags, void *context);
Please follow the related discussion we had. Alexandre had already
posted updated and this needs to follow.
Also this way you break the existing drivers which use this API, not
sure why you posted without fixing them?

>  	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
>  		struct dma_chan *chan, struct scatterlist *sgl,
> @@ -581,7 +581,7 @@ struct dma_device {
>  		size_t period_len, enum dma_transfer_direction direction);
>  	struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
>  		struct dma_chan *chan, struct dma_interleaved_template *xt,
> -		unsigned long flags);
> +		unsigned long flags, void *context);
>  	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
>  		unsigned long arg);
>  


-- 
~Vinod



From khilman at ti.com  Mon Mar 12 14:54:32 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 12 Mar 2012 11:54:32 -0700
Subject: [PATCH v3 00/13] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com> (Tarun
 Kanti DebBarma's message of "Wed, 7 Mar 2012 16:45:50 +0530")
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <878vj5y7iv.fsf@ti.com>

Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:

> The cleanup is mostly getting rid of redundant fields in struct gpio_bank{}
> as we already have them as part of bank->context now. Also, remove un-used
> variable from gpio_irq_handler.
>
> The fixes include correction of _set_gpio_irqenable() implementation,
> missing wakeup_en register update in set_gpio_wakeup(), type mismatch
> of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
> register update in set_gpio_dataout_() and few corrections in context
> save logic.
>
> It is baselined on top of Kevin's following series:
> gpio/omap: cleanup and runtime PM conversion for v3.4
> git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/gpio/runtime-pm-cleanup
>
> Series is available here for reference:
> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_further_cleanup_fixes

This branch doesn't exist.

Kevin



From khilman at ti.com  Mon Mar 12 14:53:14 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 12 Mar 2012 11:53:14 -0700
Subject: [PATCH v3 05/13] gpio/omap: get rid of retrigger variable in
 gpio_irq_handler
In-Reply-To: <CAC83ZvJXK-FsiqyQT6BQxggRewkiHZkRBi44CVH15gb4dUbsjw@mail.gmail.com>
 (Tarun Kanti DebBarma's message of "Fri, 9 Mar 2012 14:16:52 +0530")
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-6-git-send-email-tarun.kanti@ti.com>
 <CAC83ZvJXK-FsiqyQT6BQxggRewkiHZkRBi44CVH15gb4dUbsjw@mail.gmail.com>
Message-ID: <87ehsxy7l1.fsf@ti.com>

"DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:

> On Wed, Mar 7, 2012 at 4:45 PM, Tarun Kanti DebBarma <tarun.kanti at ti.com> wrote:
>> This local variable is just assigned zero and then OR'ed
>> with isr. It does not appear to serve any purpose and so
>> removing it.
> Missed following comments from Kevin given in v2. Sorry about that.
> I have updated the change in:
> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev
> for_3.4/gpio_further_cleanup_fixes
>
> "commit 672e302e3c (ARM: OMAP: use edge/level handlers from generic IRQ
> framework) removed retrigger support in favor of using generic IRQ
> framework.  This patch cleans up some unused remnants of that removal.

Ah, thanks.

Kevin


From tarun.kanti at ti.com  Mon Mar 12 15:53:45 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Tue, 13 Mar 2012 01:23:45 +0530
Subject: [PATCH v3 00/13] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <878vj5y7iv.fsf@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <878vj5y7iv.fsf@ti.com>
Message-ID: <CAC83Zv+8AjCHBOJbtvSQS-URvCE5Xm9oPk9_X7h4Kz7FZ_7Otw@mail.gmail.com>

On Tue, Mar 13, 2012 at 12:24 AM, Kevin Hilman <khilman at ti.com> wrote:
> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>
>> The cleanup is mostly getting rid of redundant fields in struct gpio_bank{}
>> as we already have them as part of bank->context now. Also, remove un-used
>> variable from gpio_irq_handler.
>>
>> The fixes include correction of _set_gpio_irqenable() implementation,
>> missing wakeup_en register update in set_gpio_wakeup(), type mismatch
>> of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
>> register update in set_gpio_dataout_() and few corrections in context
>> save logic.
>>
>> It is baselined on top of Kevin's following series:
>> gpio/omap: cleanup and runtime PM conversion for v3.4
>> git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/gpio/runtime-pm-cleanup
>>
>> Series is available here for reference:
>> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_further_cleanup_fixes
>
> This branch doesn't exist.
Oops... I am sorry.
I was in the process of updating the branch with latest comments after
base-lining on Grant's:
git://git.secretlab.ca/git/linux-2.6.git
Branch: gpio/next
Because this has all the gpio changes including Benoit's latest gpio
devicetree changes.
Should I go ahead?
--
Tarun
>
> Kevin
>


From sr at denx.de  Mon Mar 12 12:23:38 2012
From: sr at denx.de (Stefan Roese)
Date: Mon, 12 Mar 2012 17:23:38 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <4F5E169D.3070508@st.com>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <201203121606.26926.sr@denx.de> <4F5E169D.3070508@st.com>
Message-ID: <201203121723.38411.sr@denx.de>

On Monday 12 March 2012 16:30:37 Giuseppe CAVALLARO wrote:
> >>> +Required properties:
> >>> +- compatible: Should be "stm,gmac"
> >> 
> >> This is too generic. This should be 1 string per version of h/w.
> > 
> > Viresh, Giuseppe, can you please suggest a proper string for the SPEAr600
> > STMMAC core, including version?
> > 
> >> 'stm' should be 'st' according to vendor-prefixes.txt.
> 
> I'm not familiar with devicetree; maybe we should have:
> 
> "stmicro,mac100"
> "stmicro,gmac"
> 
> or: st instead of stmicro if you prefer.
> 
> in fact, stmmac is for mac100 and gmac devices.

How about "st,spear600-gmac" for SPEAr600 then?
 
> > Okay.
> > 
> >>> +- reg: Address and length of the register set for the device
> >>> +- interrupt-parent: Should be the phandle for the interrupt controller
> >>> +  that services interrupts for this device
> >>> +- interrupts: Should contain the STMMAC interrupts
> >>> +- interrupt-names: Should contain the interrupt names "macirq"
> >>> +  "eth_wake_irq" if this interrupt is supported in the "interrupts"
> >>> +  property
> >> 
> >> You should be able to tell this from the compatible string and number of
> >> interrupts.
> > 
> > Yes. Currently the driver uses platform_get_irq_byname() to register the
> > irq's. That's why I added these properties. Is there something wrong with
> > using it this way?
> > 
> >>> +- phy-mode: String, operation mode of the PHY interface.
> >>> +  Supported values are: "mii", "rmii", "gmii", "rgmii".
> >>> +- phy-addr: MDIO address of the PHY
> >> 
> >> This is normally probed or the mdio bus is a sub-node of the MAC node.
> >> See arch/powerpc/boot/dts/mpc8377_mds.dts for an example.
> > 
> > Okay, I'll rework this.
> > 
> >>> +
> >>> +Optional properties:
> >>> +- stm,prog-burst-len: Specify the burst length
> >>> +- stm,has-gmac: Indicates that the controller supports 1000Mbps
> >>> +- stm,has-pmt: Indicates that the controller supports power management
> >> 
> >> I think these should all be encoded by the compatible string.
> 
> and should we have all the other flags e.g. tx_coe etc?
> (see stmmac.txt)

As Rob suggested, some of these flags/parameters are implicitly defined by the 
compatible string. If this is not the case, then sure, those flags/parameters 
need to be provided via the device-tree as well. I just don't need "tx_coe" 
etc. for my platform (SPEAr600) as far as I know. I suggest to add support for 
them once they are really needed/used by other platforms.

Thanks,
Stefan


From kgene.kim at samsung.com  Mon Mar 12 14:52:16 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 12 Mar 2012 11:52:16 -0700
Subject: [PATCH v2 3/3] gpio/samsung: use ioremap() for EXYNOS4 GPIOlib
In-Reply-To: <20120312161904.E57193E07B0@localhost>
References: <1329341829-14403-1-git-send-email-kgene.kim@samsung.com>
 <1329341829-14403-4-git-send-email-kgene.kim@samsung.com>
 <20120312161904.E57193E07B0@localhost>
Message-ID: <4F5E45E0.9020108@samsung.com>

Grant Likely wrote:
> On Thu, 16 Feb 2012 06:37:09 +0900, Kukjin Kim<kgene.kim at samsung.com>  wrote:
>> From: Sangsu Park<sangsu4u.park at samsung.com>
>>
>> This patch changes to use ioremap() for EXYNOS4210
>> so that we can drop the static mapping for EXYNOS
>> SoCs.
>>
>> Note: Will be updated for all of Samsung GPIOlibs
>> to use ioremap() next time.
>>
>> Signed-off-by: Sangsu Park<sangsu4u.park at samsung.com>
>> Cc: Grant Likely<grant.likely at secretlab.ca>
>> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
> 
> Acked-by: Grant Likely<grant.likely at secretlab.ca>
> 
> Kukjin, I think you wanted to take this via your tree?  I'm fine with that.
> Let me know if you'd rather it go via the gpio tree.
> 
Hi Grant,

I think, since this series has no depenency with current samsung tree
for upcoming merge window, this can be sent to upstream via the gpio tree.

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From grant.likely at secretlab.ca  Mon Mar 12 13:17:27 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 11:17:27 -0600
Subject: [PATCH] gpio/mxs: support irqs triggered by both edges
In-Reply-To: <lyhaxt4usz.fsf@ensc-virt.intern.sigma-chemnitz.de>
References: <1329745925-7868-1-git-send-email-enrico.scholz@sigma-chemnitz.de>
 <20120312163503.AEBC73E07B0@localhost>
 <lyhaxt4usz.fsf@ensc-virt.intern.sigma-chemnitz.de>
Message-ID: <CACxGe6uOtgqb1GcBUCDY3L7B5THg1_set0pNcxkzZihr2y9==Q@mail.gmail.com>

On Mon, Mar 12, 2012 at 11:02 AM, Enrico Scholz
<enrico.scholz at sigma-chemnitz.de> wrote:
> Grant Likely <grant.likely at secretlab.ca> writes:
>
>>> iMX28 silicon does not support irqs triggered by both gpio edges. Patch
>>> emulates this behavior by configuring such irqs as level triggered and
>>> by switching polarity in the interrupt handler.
>>
>> That looks dodgy and hacky. ?This will definitely miss interrupts if
>> they come in too fast.
>
> Because patch calculates the trigger from the actual level, there should
> not be missed more interrupts than with native edge-both support.

Edge interrupt controllers latch interrupt requests. so that nothing
gets missed.  Level interrupt controllers do not.  So, if the irq line
toggles 3 times before the handling code gets executed, then the
kernel will still only recognize 1 irq, not 3.

>> I don't like this approach. ?What do you need it for?
>
> some drivers (e.g. gpio-keys, otg gpio-vbus, gpio-charger) are requesting
> gpio based interrupts with IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
> flags. ?It is not possible to use such drivers without having EDGE_BOTH
> support.
>
>
> Enrico



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From olof at lixom.net  Mon Mar 12 15:56:10 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 12 Mar 2012 12:56:10 -0700
Subject: [PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection
 loop
In-Reply-To: <20120312193020.GA1584@rainbow>
References: <20120306201538.GA14350@rainbow>
 <1331287760-10546-1-git-send-email-mad_soft@inbox.ru>
 <4F5E3BE7.4080207@wwwdotorg.org> <20120312193020.GA1584@rainbow>
Message-ID: <CAOesGMi0aqCjLsJ5wWXwFVQL2T8wtUuE14rFZ9h7NKHXcWAoqQ@mail.gmail.com>

On Mon, Mar 12, 2012 at 12:30 PM, Dmitry Artamonow <mad_soft at inbox.ru> wrote:
> On 12:09 Mon 12 Mar ? ? , Stephen Warren wrote:
>> Thierry pointed out that one of NVIDIA's downstream kernels uses a
>> timeout of 300 here, rather than 2000 above. Do you see a specific need
>> for this timeout for be 2000 rather than 300? It might be nice to be
>> consistent.
> No, there's no specific need for it to be 2000 - it may as well be 300.
> I just wanted to stay on the safe side, but I think 300 should be still
> more than enough time for PLL to lock.
>
>>
>> Olof, I notice you've already applied V1 of this, which has the return
>> statement issue. Can you replace it with this, or should Dmitry send an
>> incremental patch?
>
> Yes, V1 breaks more things than it fixes, so it would be nice if
> it can be replaced with fixed version (I hope it's not too late yet).
> BTW, regarding timeout discussion above - should I resend patch with
> adjusted timeout, or can you change it while applying? (of course,
> if we settle on incremental patch, I'll roll this change in)

Please send an incremental patch which also solves the above question. :)


-Olof


From sr at denx.de  Mon Mar 12 11:25:50 2012
From: sr at denx.de (Stefan Roese)
Date: Mon, 12 Mar 2012 16:25:50 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <20120312143825.GB13869@game.jcrosoft.org>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <20120312143825.GB13869@game.jcrosoft.org>
Message-ID: <201203121625.50283.sr@denx.de>

On Monday 12 March 2012 15:38:25 Jean-Christophe PLAGNIOL-VILLARD wrote:
> > @@ -58,6 +94,22 @@ static int stmmac_pltfr_probe(struct platform_device
> > *pdev)
> > 
> >  		ret = -ENOMEM;
> >  		goto out_release_region;
> >  	
> >  	}
> > 
> > +
> > +#ifdef CONFIG_OF
> > +	plat_dat = devm_kzalloc(&pdev->dev, sizeof(struct
> > plat_stmmacenet_data), +				GFP_KERNEL);
> > +	if (!plat_dat) {
> > +		pr_err("%s: ERROR: no memory", __func__);
> > +		ret = -ENOMEM;
> > +		goto out_unmap;
> > +	}
> > +
> > +	ret = stmmac_probe_config_dt(pdev, plat_dat, &mac);
> > +	if (ret) {
> > +		pr_err("%s: main dt probe failed", __func__);
> > +		goto out_unmap;
> > +	}
> > +#else
> 
> This must be check at runtime, we can boot a kernel with or without DT.

Are you referring to using "if (pdev->dev.of_node)" to distinguish between DT 
and non-DT version instead of this #ifdef?

Thanks,
Stefan


From santosh.shilimkar at ti.com  Mon Mar 12 10:39:02 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Mon, 12 Mar 2012 20:09:02 +0530
Subject: [PATCH 0/2] ARM: OMAP4: powerdomain: Misc powerdomain fix and
 associated cleanup
In-Reply-To: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
References: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <CAMQu2gxGMbq9o3v7tQSbebBHpS7o7SsXhraLUoYFUP2yECkpUg@mail.gmail.com>

On Mon, Mar 12, 2012 at 8:04 PM, Santosh Shilimkar
<santosh.shilimkar at ti.com> wrote:
> Paul,
> Can you please have at this series ?
> First patch is the bug fix and second one is the cleanup which you proposed some
> time back.
>
In $subject
s/OMAP4/OMAP

Regards
Santosh


From vinod.koul at intel.com  Mon Mar 12 12:23:58 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Mon, 12 Mar 2012 21:53:58 +0530
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <20120312161143.GA10830@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <1331128466.24656.421.camel@vkoul-udesk3>
 <20120312161143.GA10830@n2100.arm.linux.org.uk>
Message-ID: <1331569438.1727.3.camel@vkoul-udesk3>

On Mon, 2012-03-12 at 16:11 +0000, Russell King - ARM Linux wrote:
> On Wed, Mar 07, 2012 at 07:24:26PM +0530, Vinod Koul wrote:
> > On Tue, 2012-03-06 at 22:33 +0000, Russell King - ARM Linux wrote:
> > > [v2 - more or less same description.  Including lakml in cc for the full
> > > set]
> > > 
> > > This patch series cleans up the handling of cookies in DMA engine drivers.
> > > This is done by providing a set of inline library functions for common
> > > tasks:
> > > 
> > > - moving the 'last completed cookie' into struct dma_chan - everyone
> > >   has this in their driver private channel data structure
> > > 
> > > - consolidate allocation of cookies to DMA descriptors
> > > 
> > > - common way to update 'last completed cookie' value
> > > 
> > > - standard way to implement tx_status callback and update the residue
> > > 
> > > - consolidate initialization of cookies
> > > 
> > > - update implementations differing from the majority of DMA engine drivers
> > >   to behave the same as the majority implementation in respect of cookies
> > > 
> > > What this means is that we get to the point where all DMA engine drivers
> > > will hand out cookie value '2' as the first, and incrementing cookie
> > > values up to INT_MAX, returning to cookie '1' as the next cookie.
> > > 
> > > Think of this patch series as round 1...  I am hoping over time that more
> > > code can be consolidated between the DMA engine drivers and end up with a
> > > consistent way to handle various common themes in DMA engine hardware
> > > (like physical channel<->peripheral request signal selection.)
> > Thanks Russell,
> > 
> > I have tested this on atom today, and as expected works flawlessly :)
> > After all acks, I can merge or these can go thru your tree with my Ack.
> > Either way is okay.
> > 
> > I applied the v2 on a branch and also rebased on top of slave-dma.next.
> > There were few conflicts in imx-dma.c. Sacha, Javier, pls see that merge
> > is right.
> > 
> > This branch (rmk_cookie_fixes2_rebased) is not yet pushed, as I am not
> > able to connect to infradead.org, should be done when server is back.
> 
> Are you going to pick up Shawn Guo's tested-by for these patches, or are
> we saying its too late for that now?
Sure, his and others we have received on this series.
Also, IIRC there was one fixup from Jassi on pl330?

I should be able to merge this tomorrow, if thats fine with you.



-- 
~Vinod



From coelho at ti.com  Sat Mar 10 00:07:17 2012
From: coelho at ti.com (Luciano Coelho)
Date: Sat, 10 Mar 2012 07:07:17 +0200
Subject: [PATCH v2] ARM: OMAP: WiLink platform data for the PandaBoard
In-Reply-To: <20120309183150.GH12083@atomide.com>
References: <1331074504-22683-1-git-send-email-mgherzan@gmail.com>
 <20120309183150.GH12083@atomide.com>
Message-ID: <1331356037.3164.31.camel@cumari>

On Fri, 2012-03-09 at 10:31 -0800, Tony Lindgren wrote: 
> Hi Luca,

Hi Tony,


> * Mircea Gherzan <mgherzan at gmail.com> [120306 14:23]:
> > The "uim" deamon requires sysfs entries that are filled in using
> > this platform data.
> > 
> > Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
> > ---
> >  arch/arm/mach-omap2/board-omap4panda.c |   14 ++++++++++++--
> >  include/linux/ti_wilink_st.h           |    2 ++
> >  2 files changed, 14 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
> > index b1d74d6..339e781 100644
> > --- a/arch/arm/mach-omap2/board-omap4panda.c
> > +++ b/arch/arm/mach-omap2/board-omap4panda.c
> > @@ -27,6 +27,7 @@
> >  #include <linux/i2c/twl.h>
> >  #include <linux/regulator/machine.h>
> >  #include <linux/regulator/fixed.h>
> > +#include <linux/ti_wilink_st.h>
> >  #include <linux/wl12xx.h>
> >  
> >  #include <mach/hardware.h>
> > @@ -56,12 +57,21 @@
> >  #define HDMI_GPIO_HPD  63 /* Hotplug detect */
> >  
> >  /* wl127x BT, FM, GPS connectivity chip */
> > -static int wl1271_gpios[] = {46, -1, -1};
> > +static struct ti_st_plat_data wilink_platform_data = {
> > +	.nshutdown_gpio	= 46,
> > +	.dev_name	= "/dev/ttyO1",
> > +	.flow_cntrl	= 1,
> > +	.baud_rate	= 3000000,
> > +	.chip_enable	= NULL,
> > +	.suspend	= NULL,
> > +	.resume		= NULL,
> > +};
> > +
> >  static struct platform_device wl1271_device = {
> >  	.name	= "kim",
> >  	.id	= -1,
> >  	.dev	= {
> > -		.platform_data	= &wl1271_gpios,
> > +		.platform_data	= &wilink_platform_data,
> >  	},
> >  };
> >  
> > diff --git a/include/linux/ti_wilink_st.h b/include/linux/ti_wilink_st.h
> > index 2ef4385..3ca0269 100644
> > --- a/include/linux/ti_wilink_st.h
> > +++ b/include/linux/ti_wilink_st.h
> > @@ -25,6 +25,8 @@
> >  #ifndef TI_WILINK_ST_H
> >  #define TI_WILINK_ST_H
> >  
> > +#include <linux/skbuff.h>
> > +
> >  /**
> >   * enum proto-type - The protocol on WiLink chips which share a
> >   *	common physical interface like UART.
> > -- 
> 
> Just checking.. Can you please take a look at this patch
> and confirm that this is how things are supposed to be done?
> 
> To me passing some third driver's dev_name in pdata seems
> pretty weird.. But then again maybe I just don't know how
> this is supposed to work.

This looks pretty weird to me too.  The "/dev/ttyO1" thing doesn't look
right.  But I don't really know how this works either, because this is
the BT/FM/GPS part of the wl12xx chip.  And, to be honest, I don't know
anything about it.  I only know about the wifi part of it. :\

-- 
Cheers,
Luca.



From thierry.reding at avionic-design.de  Fri Mar  9 01:37:40 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 9 Mar 2012 07:37:40 +0100
Subject: [PATCH 09/11] ARM: tegra: Rewrite PCIe support as a driver
In-Reply-To: <4F5911E0.6060802@wwwdotorg.org>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-10-git-send-email-thierry.reding@avionic-design.de>
 <4F5911E0.6060802@wwwdotorg.org>
Message-ID: <20120309063739.GC25208@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> On 03/08/2012 07:51 AM, Thierry Reding wrote:
> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> 
> Patch description?

I actually sat in front of the editor for a couple of minutes and I just
couldn't think of anything. I'll try harder for the next version.

> > diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
> ...
> > -static int __init harmony_pcie_init(void)
> > +static int tegra_pcie_init(struct platform_device *pdev)
> 
> That name should probably still be called harmony_something() since it's
> still board-specific.

Okay, I'll rename it to harmony_pcie_init().

> I wonder how having a per-board callback will integrate with device
> tree. I guess I'll find out when I review patch 11:-)
> 
> > diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
> 
> > +static int __init trimslice_pci_init(void)
> >  {
> >  	if (!machine_is_trimslice())
> >  		return 0;
> 
> You can remove that test now.

Okay.

> > diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
> 
> > +#define TEGRA_PCIE_MAX_PORTS 2
> > +
> > +struct tegra_pcie_pdata {
> > +	int (*init)(struct platform_device *pdev);
> > +	int (*exit)(struct platform_device *pdev);
> > +	bool enable_ports[TEGRA_PCIE_MAX_PORTS];
> > +};
> 
> That's a somewhat odd place to put the header; a dedicated
> mach-tegra/include/mach/tegra_pcie_pdata.h or
> include/linux/platform_data/tegra_pcie.h might make more sense.

mach-tegra/include/mach/pcie.h perhaps? That would be less redundant.

Thierry
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From jdzheng at broadcom.com  Fri Mar  9 16:59:14 2012
From: jdzheng at broadcom.com (JD (Jiandong) Zheng)
Date: Fri, 9 Mar 2012 13:59:14 -0800
Subject: [PATCH] ARM: BCMRING: Fix static IO mapping
Message-ID: <8628FE4E7912BF47A96AE7DD7BAC0AAD0109D775AF28@SJEXCHCCR02.corp.ad.broadcom.com>

Fix bcmring static IO mapping which causes booting issue since v3.2.0

Signed-off-by: Jiandong Zheng jdzheng at broadcom.com 
---
 arch/arm/mach-bcmring/mm.c |   27 +++++++++++----------------
 1 files changed, 11 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
index 1adec78..b46ea07 100644
--- a/arch/arm/mach-bcmring/mm.c
+++ b/arch/arm/mach-bcmring/mm.c
@@ -31,24 +31,19 @@
  .type = MT_MEMORY }
 
 static struct map_desc bcmring_io_desc[] __initdata = {
- IO_DESC(MM_IO_BASE_NAND, SZ_64K), /* phys:0x28000000-0x28000FFF  virt:0xE8000000-0xE8000FFF  size:0x00010000 */
- IO_DESC(MM_IO_BASE_UMI, SZ_64K), /* phys:0x2C000000-0x2C000FFF  virt:0xEC000000-0xEC000FFF  size:0x00010000 */
-
  IO_DESC(MM_IO_BASE_BROM, SZ_64K), /* phys:0x30000000-0x3000FFFF  virt:0xF3000000-0xF300FFFF  size:0x00010000 */
- MEM_DESC(MM_IO_BASE_ARAM, SZ_1M), /* phys:0x31000000-0x31FFFFFF  virt:0xF3100000-0xF31FFFFF  size:0x01000000 */
- IO_DESC(MM_IO_BASE_DMA0, SZ_1M), /* phys:0x32000000-0x32FFFFFF  virt:0xF3200000-0xF32FFFFF  size:0x01000000 */
- IO_DESC(MM_IO_BASE_DMA1, SZ_1M), /* phys:0x33000000-0x33FFFFFF  virt:0xF3300000-0xF33FFFFF  size:0x01000000 */
- IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF  virt:0xF3400000-0xF34FFFFF  size:0x01000000 */
- IO_DESC(MM_IO_BASE_CLCD, SZ_1M), /* phys:0x35000000-0x35FFFFFF  virt:0xF3500000-0xF35FFFFF  size:0x01000000 */
- IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF  virt:0xF3600000-0xF36FFFFF  size:0x01000000 */
- IO_DESC(MM_IO_BASE_SPUM, SZ_1M), /* phys:0x37000000-0x37FFFFFF  virt:0xF3700000-0xF37FFFFF  size:0x01000000 */
- IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M), /* phys:0x38000000-0x38FFFFFF  virt:0xF3800000-0xF38FFFFF  size:0x01000000 */
- IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M), /* phys:0x3A000000-0x3AFFFFFF  virt:0xF3A00000-0xF3AFFFFF  size:0x01000000 */
-
+ MEM_DESC(MM_IO_BASE_ARAM, SZ_1M), /* phys:0x31000000-0x31FFFFFF  virt:0xF3100000-0xF31FFFFF  size:0x00100000 */
+ IO_DESC(MM_IO_BASE_DMA0, SZ_1M), /* phys:0x32000000-0x32FFFFFF  virt:0xF3200000-0xF32FFFFF  size:0x00100000 */
+ IO_DESC(MM_IO_BASE_DMA1, SZ_1M), /* phys:0x33000000-0x33FFFFFF  virt:0xF3300000-0xF33FFFFF  size:0x00100000 */
+ IO_DESC(MM_IO_BASE_ESW, SZ_1M),         /* phys:0x34000000-0x34FFFFFF  virt:0xF3400000-0xF34FFFFF  size:0x00100000 */
+ IO_DESC(MM_IO_BASE_CLCD, SZ_1M), /* phys:0x35000000-0x35FFFFFF  virt:0xF3500000-0xF35FFFFF  size:0x00100000 */
+ IO_DESC(MM_IO_BASE_APM, SZ_1M),         /* phys:0x36000000-0x36FFFFFF  virt:0xF3600000-0xF36FFFFF  size:0x00100000 */
+ IO_DESC(MM_IO_BASE_SPUM, SZ_1M), /* phys:0x37000000-0x37FFFFFF  virt:0xF3700000-0xF37FFFFF  size:0x00100000 */
+ IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M), /* phys:0x38000000-0x38FFFFFF  virt:0xF3800000-0xF38FFFFF  size:0x00100000 */
+ IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M), /* phys:0x3A000000-0x3AFFFFFF  virt:0xF3A00000-0xF3AFFFFF  size:0x00100000 */
  IO_DESC(MM_IO_BASE_VRAM, SZ_64K), /* phys:0x40000000-0x4000FFFF  virt:0xF4000000-0xF400FFFF  size:0x00010000 */
- IO_DESC(MM_IO_BASE_CHIPC, SZ_16M), /* phys:0x80000000-0x80FFFFFF  virt:0xF8000000-0xF8FFFFFF  size:0x01000000 */
- IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
-  SZ_16M), /* phys:0x0F000000-0x0FFFFFFF  virt:0xF0000000-0xF0FFFFFF  size:0x01000000 */
+ IO_DESC(MM_IO_BASE_CHIPC, SZ_8M), /* phys:0x80000000-0x807FFFFF  virt:0xF8000000-0xF87FFFFF  size:0x00800000 */
+ IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD, SZ_16M), /* phys:0x0F000000-0x0FFFFFFF virt:0xF0000000-0xF0FFFFFF  size:0x01000000 */
 };
 
 void __init bcmring_map_io(void)
-- 
1.7.9.1


From lost.distance at yahoo.com  Sat Mar 10 09:54:25 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Sat, 10 Mar 2012 14:54:25 +0000 (GMT)
Subject: [PATCH v3] pxa/hx4700: Fix basic suspend/resume
Message-ID: <1331391265.88838.YahooMailClassic@web29002.mail.ird.yahoo.com>

Basic suspend/resume is fixed by ensuring that the PGSR registers are set
correctly before sleep mode is entered. In particular four of the active low
resets need to be driven high while in sleep mode, otherwise the unit resets
itself instead of suspending. Another problem was that the PCFR_GPROD bit is set
by the HTC bootloader; this caused GPIO reset (i.e. the reset button) to fail
immediately after returning from sleep mode.

Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
---

V3:
Changed GPIO72, GPIO96 back to KEEP_OUTPUT.

diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c
--- clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-04 01:08:09.000000000 +0000
+++ linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-10 14:42:41.328255002 +0000
@@ -121,7 +121,11 @@ static unsigned long hx4700_pin_config[]
 	GPIO19_SSP2_SCLK,
 	GPIO86_SSP2_RXD,
 	GPIO87_SSP2_TXD,
-	GPIO88_GPIO,
+	GPIO88_GPIO | MFP_LPM_DRIVE_HIGH,	/* TSC2046_CS */
+
+	/* BQ24022 Regulator */
+	GPIO72_GPIO | MFP_LPM_KEEP_OUTPUT,	/* BQ24022_nCHARGE_EN */
+	GPIO96_GPIO | MFP_LPM_KEEP_OUTPUT,	/* BQ24022_ISET2 */
 
 	/* HX4700 specific input GPIOs */
 	GPIO12_GPIO,	/* ASIC3_IRQ */
@@ -134,6 +138,11 @@ static unsigned long hx4700_pin_config[]
 	GPIO108_GPIO,	/* GSM_READY */
 	GPIO58_GPIO,	/* TSC2046_nPENIRQ */
 	GPIO66_GPIO,	/* nSDIO_IRQ */
+
+	GPIO61_GPIO | MFP_LPM_DRIVE_HIGH,	/* W3220_nRESET */
+	GPIO71_GPIO | MFP_LPM_DRIVE_HIGH,	/* ASIC3_nRESET */
+	GPIO81_GPIO | MFP_LPM_DRIVE_HIGH,	/* CPU_GP_nRESET */
+	GPIO116_GPIO | MFP_LPM_DRIVE_HIGH,	/* CPU_HW_nRESET */
 };
 
 /*
@@ -828,15 +837,20 @@ static struct gpio global_gpios[] = {
 	{ GPIO110_HX4700_LCD_LVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_LVDD" },
 	{ GPIO111_HX4700_LCD_AVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_AVDD" },
 	{ GPIO32_HX4700_RS232_ON,         GPIOF_OUT_INIT_HIGH, "RS232_ON" },
+	{ GPIO61_HX4700_W3220_nRESET,     GPIOF_OUT_INIT_HIGH, "W3220_nRESET" },
 	{ GPIO71_HX4700_ASIC3_nRESET,     GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
+	{ GPIO81_HX4700_CPU_GP_nRESET,    GPIOF_OUT_INIT_HIGH, "CPU_GP_nRESET" },
 	{ GPIO82_HX4700_EUART_RESET,      GPIOF_OUT_INIT_HIGH, "EUART_RESET" },
 	{ GPIO105_HX4700_nIR_ON,          GPIOF_OUT_INIT_HIGH, "nIR_EN" },
+	{ GPIO116_HX4700_CPU_HW_nRESET,   GPIOF_OUT_INIT_HIGH, "CPU_HW_nRESET" },
 };
 
 static void __init hx4700_init(void)
 {
 	int ret;
 
+	PCFR = PCFR_GPR_EN | PCFR_OPDE;
+
 	pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
 	ret = gpio_request_array(ARRAY_AND_SIZE(global_gpios));
 	if (ret)



From uri.y at variscite.com  Mon Mar 12 06:20:29 2012
From: uri.y at variscite.com (Uri Yosef)
Date: Mon, 12 Mar 2012 12:20:29 +0200
Subject: [PATCH]: arm/dts: OMAP4: Add Variscite OMAP4 System-On-Modeule support
Message-ID: <1331547629-17556-1-git-send-email-uri.y@variscite.com>

From: Uri yosef <uri.y at variscite.com>

 Hi Tony,

 This patch add device tree support for Variscite OMAP4 System-On-Modeule.

 Regards,
 Uri Yosef

---
 arch/arm/boot/dts/omap4-var_som.dts |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/omap4-var_som.dts

diff --git a/arch/arm/boot/dts/omap4-var_som.dts b/arch/arm/boot/dts/omap4-var_som.dts
new file mode 100644
index 0000000..e352f38
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-var_som.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap4.dtsi"
+
+/ {
+	model = "Variscite OMAP4 SOM";
+	compatible = "var,omap4-var_som", "ti,omap4430", "ti,omap4";
+
+	/*
+	 * Since the initial device tree board file does not create any
+	 * devices (MMC, network...), the only way to boot is to provide a
+	 * ramdisk.
+	 */
+	chosen {
+		bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>; /* 1 GB */
+	};
+};
-- 
1.7.5.4



From jm at lentin.co.uk  Sun Mar 11 10:33:24 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sun, 11 Mar 2012 14:33:24 +0000
Subject: [PATCH 0/2] Add support for DNS-320 and DNS-325 using devicetree
Message-ID: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>

As agreed with Arnd Bergmann and Jason Cooper, include any board setup that
cannot be done in devicetree in board-dt.c, then replace with devicetree
entries.

The NAND driver is converted to devicetree as part of this patch series, 
although I don't feel qualified to explain the parameters actually mean so 
have left documentation fields blank.

The patches should apply cleanly to staging/kirkwood/dt, although 
kirkwood-dns320.dts attempts to override the orion-wdt definition with a
lower TCLK, even though the orion-wdt work isn't merged yet. If this would
be better to remove I shall.

Cheers,

Jamie Lentin (2):
  ARM: kirkwood: Basic support for DNS-320 and DNS-325
  ARM: kirkwood: Convert orion-nand to fdt

 .../devicetree/bindings/mtd/orion-nand.txt         |   41 +++
 arch/arm/boot/dts/kirkwood-dns320.dts              |   96 +++++++
 arch/arm/boot/dts/kirkwood-dns325.dts              |   82 ++++++
 arch/arm/mach-kirkwood/Kconfig                     |   18 ++
 arch/arm/mach-kirkwood/Makefile.boot               |    2 +
 arch/arm/mach-kirkwood/board-dt.c                  |  264 ++++++++++++++++++++
 arch/arm/mach-kirkwood/common.c                    |    6 +
 drivers/mtd/nand/orion_nand.c                      |   39 +++-
 8 files changed, 546 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt
 create mode 100644 arch/arm/boot/dts/kirkwood-dns320.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-dns325.dts

-- 
1.7.9.1



From enrico.scholz at sigma-chemnitz.de  Mon Mar 12 13:38:53 2012
From: enrico.scholz at sigma-chemnitz.de (Enrico Scholz)
Date: Mon, 12 Mar 2012 18:38:53 +0100
Subject: [PATCH] gpio/mxs: support irqs triggered by both edges
In-Reply-To: <CACxGe6uOtgqb1GcBUCDY3L7B5THg1_set0pNcxkzZihr2y9==Q@mail.gmail.com>
 (Grant Likely's message of "Mon, 12 Mar 2012 11:17:27 -0600")
References: <1329745925-7868-1-git-send-email-enrico.scholz@sigma-chemnitz.de>
 <20120312163503.AEBC73E07B0@localhost>
 <lyhaxt4usz.fsf@ensc-virt.intern.sigma-chemnitz.de>
 <CACxGe6uOtgqb1GcBUCDY3L7B5THg1_set0pNcxkzZihr2y9==Q@mail.gmail.com>
Message-ID: <lyd38h4t3m.fsf@ensc-virt.intern.sigma-chemnitz.de>

Grant Likely <grant.likely at secretlab.ca> writes:

>>>> iMX28 silicon does not support irqs triggered by both gpio edges. Patch
>>>> emulates this behavior by configuring such irqs as level triggered and
>>>> by switching polarity in the interrupt handler.
>>>
>>> That looks dodgy and hacky. ?This will definitely miss interrupts if
>>> they come in too fast.
>>
>> Because patch calculates the trigger from the actual level, there should
>> not be missed more interrupts than with native edge-both support.
>
> Edge interrupt controllers latch interrupt requests. so that nothing
> gets missed.  Level interrupt controllers do not.

iMX28 hardware sets interrupt status only but never clears it[1]. E.g. when
the requested level has been seen, the interrupt is pending until software
clears it.  It does not matter whether level changes back or stays asserted.


> So, if the irq line toggles 3 times before the handling code gets
> executed, then the kernel will still only recognize 1 irq, not 3.

There is no difference to edge triggered interrupts. When the trigger
events happen too fast, not all of them can be handled. But both for
edge and for level triggered interrupts, the interrupt handler will be
executed at least once.



Enrico

Footnotes: 
[1]  see figure "Figure 9-5. GPIO Interrupt Generation", page 688 in
     "i.MX28 Applications Processor Reference Manual, Rev. 1, 2010"


From grant.likely at secretlab.ca  Sun Mar 11 10:07:31 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 11 Mar 2012 08:07:31 -0600
Subject: [PATCH 1/4 v5] of_spi: add generic binding support to specify cs
 gpio
In-Reply-To: <1331317544-21735-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.co>
 <1331317544-21735-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120311140731.2D4F93E0979@localhost>

On Fri,  9 Mar 2012 19:25:44 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> This will allow to use gpio for chip select with no modification in the
> driver binding
> 
> When use the cs-gpios, the gpio number will be passed via the cs_gpio field
> and the number of chip select will automatically increased.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: spi-devel-general at lists.sourceforge.net
> ---
> v5:
> 	update grant comment to simplify the cs_gpio management
> 
> Best Regards,
> J.
>  Documentation/devicetree/bindings/spi/spi-bus.txt |    6 ++
>  drivers/spi/spi.c                                 |   55 +++++++++++++++++++-
>  include/linux/spi/spi.h                           |    4 ++
>  3 files changed, 62 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
> index e782add..c253379 100644
> --- a/Documentation/devicetree/bindings/spi/spi-bus.txt
> +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
> @@ -12,6 +12,7 @@ The SPI master node requires the following properties:
>  - #size-cells     - should be zero.
>  - compatible      - name of SPI bus controller following generic names
>      		recommended practice.
> +- cs-gpios	  - (optional) gpios chip select.
>  No other properties are required in the SPI bus node.  It is assumed
>  that a driver for an SPI bus device will understand that it is an SPI bus.
>  However, the binding does not attempt to define the specific method for
> @@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
>  chip selects.  Individual drivers can define additional properties to
>  support describing the chip select layout.
>  
> +If cs-gpios is used the number of chip select will automatically increased.
> +
>  SPI slave nodes must be children of the SPI master node and can
>  contain the following properties.
>  - reg             - (required) chip select address of device.
> @@ -34,6 +37,9 @@ contain the following properties.
>  - spi-cs-high     - (optional) Empty property indicating device requires
>      		chip select active high
>  
> +If a gpio chipselect is used for the SPI slave the gpio number will be passed
> +via the cs_gpio
> +
>  SPI example for an MPC5200 SPI bus:
>  	spi at f00 {
>  		#address-cells = <1>;
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index b2ccdea..446eee5 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -28,6 +28,7 @@
>  #include <linux/mod_devicetable.h>
>  #include <linux/spi/spi.h>
>  #include <linux/of_spi.h>
> +#include <linux/of_gpio.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/export.h>
>  
> @@ -322,6 +323,7 @@ struct spi_device *spi_alloc_device(struct spi_master *master)
>  	spi->dev.parent = &master->dev;
>  	spi->dev.bus = &spi_bus_type;
>  	spi->dev.release = spidev_release;
> +	spi->cs_gpio = -EINVAL;
>  	device_initialize(&spi->dev);
>  	return spi;
>  }
> @@ -339,15 +341,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
>  int spi_add_device(struct spi_device *spi)
>  {
>  	static DEFINE_MUTEX(spi_add_lock);
> -	struct device *dev = spi->master->dev.parent;
> +	struct spi_master *master = spi->master;
> +	struct device *dev = master->dev.parent;
>  	struct device *d;
>  	int status;
>  
>  	/* Chipselects are numbered 0..max; validate. */
> -	if (spi->chip_select >= spi->master->num_chipselect) {
> +	if (spi->chip_select >= master->num_chipselect) {
>  		dev_err(dev, "cs%d >= max %d\n",
>  			spi->chip_select,
> -			spi->master->num_chipselect);
> +			master->num_chipselect);
>  		return -EINVAL;
>  	}
>  
> @@ -371,6 +374,9 @@ int spi_add_device(struct spi_device *spi)
>  		goto done;
>  	}
>  
> +	if (master->cs_gpios)
> +		spi->cs_gpio = master->cs_gpios[spi->chip_select];
> +

I still don't understand the need for this.  Only the master driver will need
this data, and it is already stored in the master->cs_gpios array.  Why
does it need to get duplicated into the spi_device?

>  	/* Drivers may modify this initial i/o setup, but will
>  	 * normally rely on the device being setup.  Devices
>  	 * using SPI_CS_HIGH can't coexist well otherwise...
> @@ -561,6 +567,45 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
>  }
>  EXPORT_SYMBOL_GPL(spi_alloc_master);
>  
> +#ifdef CONFIG_OF
> +static int of_spi_register_master(struct spi_master *master)
> +{
> +	int nb, i;
> +	int *cs;
> +	struct device_node *np = master->dev.of_node;
> +
> +	if (!np)
> +		return 0;
> +
> +	nb = of_gpio_named_count(np, "cs-gpios");
> +
> +	if (nb < 1)
> +		return 0;
> +
> +	cs = devm_kzalloc(&master->dev,
> +			  sizeof(int) * (master->num_chipselect + nb),
> +			  GFP_KERNEL);

sizeof(*cs)

> +	master->cs_gpios = cs;
> +
> +	if (!master->cs_gpios)
> +		return -ENOMEM;
> +
> +	memset(cs, -EINVAL, master->num_chipselect);
> +	master->num_chipselect += nb;

Looks buggy.  Should be:
	if (nb > master->num_chipselect)
		master->num_chipselect = nb;

However, this is actually quite risky.  Changing the size of
num_chipselect without the driver knowing about it will most likely
cause breakage in drivers.  Drivers may use it as an array index, and
if it gets increased then there will be problems.  In fact, drivers
are probably using spi->chip_select as an array or register index so I
don't think it can be transparently extended to include gpios.

So, this function must change.  It cannot be called automatically
from spi_register_master().  It needs to be a library function that spi bus
drivers must call explicitly so they are prepared for a change in the
num_chipselect value.

Also, if we're doing this, then the gpio cs manipulation hook should be
moved out of spi_bitbang and into the core spi_master.  There should
also be a stock function for manipulating gpio chip selects. I don't want
spi driver authors under the impression that they should open code the
chip select manipulation.

> +	cs += master->num_chipselect;
> +
> +	for (i = 0; i < nb; i++)
> +		cs[i] = of_get_named_gpio(np, "cs-gpios", i);
> +
> +	return 0;
> +}
> +#else
> +static int of_spi_register_master(struct spi_master *master)
> +{
> +	return 0;
> +}
> +#endif
> +
>  /**
>   * spi_register_master - register SPI master controller
>   * @master: initialized master, originally from spi_alloc_master()
> @@ -592,6 +637,10 @@ int spi_register_master(struct spi_master *master)
>  	if (!dev)
>  		return -ENODEV;
>  
> +	status = of_spi_register_master(master);
> +	if (status)
> +		return status;
> +
>  	/* even if it's just one always-selected device, there must
>  	 * be at least one chipselect
>  	 */
> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> index 176fce9..328d492 100644
> --- a/include/linux/spi/spi.h
> +++ b/include/linux/spi/spi.h
> @@ -89,6 +89,7 @@ struct spi_device {
>  	void			*controller_state;
>  	void			*controller_data;
>  	char			modalias[SPI_NAME_SIZE];
> +	int			cs_gpio;	/* chip select gpio */
>  
>  	/*
>  	 * likely need more hooks for more protocol options affecting how
> @@ -318,6 +319,9 @@ struct spi_master {
>  
>  	/* called on release() to free memory provided by spi_master */
>  	void			(*cleanup)(struct spi_device *spi);
> +
> +	/* gpio chip select */
> +	int			*cs_gpios;
>  };
>  
>  static inline void *spi_master_get_devdata(struct spi_master *master)
> -- 
> 1.7.7
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From w.sang at pengutronix.de  Mon Mar 12 06:10:37 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Mon, 12 Mar 2012 11:10:37 +0100
Subject: iMX53 and MMC_CAP_SDIO_IRQ
In-Reply-To: <4F5DB793.3080904@linuxtv.org>
References: <4F5DB793.3080904@linuxtv.org>
Message-ID: <20120312101037.GA2459@pengutronix.de>

Hi,

> The main problem is that the ancient Freescale 2.6.35 kernel is using
> the "mx_sdhci" driver, while in 3.3.0-rc6+ the generic "sdhci" driver is
> used, so it's not possible to simply compare the changes between the two
> versions. :-(

Not via diff, but the structure of both drivers should still be somewhat
similar.

> Probably this is a question for the Freescale people: why was the
> "mx_sdhci" necessary at all

It probably was never necessary, it was just easier to hack on a forked
driver, because you can't break other sdhci-users, I guess. Since large
portions of the code are duplicated but issues have been fixed in a
very, ahem, custom manner, this was never suitable for mainline. Back
then, most vendors thought this is good enough. Luckily, times have
changed a bit.

> and why is it not necessary any more?

Because I wanted SD support in mainline, so I had to take a different
path.

> Any help, hints and historical informations are highly appreciated,
> before I start to look deeper into this problem.

They don't have a common ancestor. Just dig into both, you will
recognize patterns, I guess.

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From festevam at gmail.com  Fri Mar  9 09:16:49 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 9 Mar 2012 11:16:49 -0300
Subject: implementing "suspend to ram" on cortex A8 based on linux 3.0.8
In-Reply-To: <CAFawwkXQhyj+c8LEDnD7q4mXDJV2jYCAHV0tBrqxrEaNGk+_0w@mail.gmail.com>
References: <CAFawwkXQhyj+c8LEDnD7q4mXDJV2jYCAHV0tBrqxrEaNGk+_0w@mail.gmail.com>
Message-ID: <CAOMZO5AMfdFciOtgn+8jU07ciL_TCd_Fo-DgfA09vR8tAAoh2w@mail.gmail.com>

On Wed, Mar 7, 2012 at 12:05 PM, yang gqyang <hustgqyang at gmail.com> wrote:
> dear all:
> I am working on arm cortex a8 now, trying to implement "suspend to ram"
> based on linux 3.0.8.

Which CPU exactly are you using?


From grant.likely at secretlab.ca  Mon Mar 12 13:27:50 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 11:27:50 -0600
Subject: [PATCH V2 1/3] Documentation/gpio.txt: Explain expected pinctrl
 interaction
In-Reply-To: <CACRpkdaQCwOPG8OKHxN3N8m_A71Pf9VurB40DZUA9sJnCsxSjw@mail.gmail.com>
References: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
 <CACRpkdaQCwOPG8OKHxN3N8m_A71Pf9VurB40DZUA9sJnCsxSjw@mail.gmail.com>
Message-ID: <20120312172750.2608B3E07B0@localhost>

On Tue, 6 Mar 2012 11:01:06 +0100, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Tue, Mar 6, 2012 at 1:22 AM, Stephen Warren <swarren at nvidia.com> wrote:
> 
> > Update gpio.txt based on recent discussions regarding interaction with the
> > pinctrl subsystem.
> 
> Looks good to me:
> Reviewed-by: Linus Walleij <linus.walleij at linaro.org>

Oops, missed this updated version.  I've dropped the v1 and picked up this
one.

g.



From james.dutton at gmail.com  Mon Mar 12 05:27:28 2012
From: james.dutton at gmail.com (James Courtier-Dutton)
Date: Mon, 12 Mar 2012 09:27:28 +0000
Subject: [PATCH] serial: PL011: clear pending interrupts
In-Reply-To: <1331540750-25697-1-git-send-email-linus.walleij@stericsson.com>
References: <1331540750-25697-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CAAMvbhF7-5FyzjgtK7EjFZSJg4KBxdMdd1jnTRTLA-LnsVhKyw@mail.gmail.com>

On 12 March 2012 08:25, Linus Walleij <linus.walleij at stericsson.com> wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
>
> Chanho Min reported that when the boot loader transfers
> control to the kernel, there may be pending interrupts
> causing the UART to lock up in an eternal loop trying to
> pick tokens from the FIFO (since the RX interrupt flag
> indicates there are tokens) while in practice there are
> no tokens - in fact there is only a pending IRQ flag.
>

I might be off base here, because I don't know this particular UART,
but if an IRQ routine is called because the RX interrupt flag is set,
shouldn't the IRQ routine be written in such a way that it can never
lock up.
If the IRQ routing has a loop that is used to read each byte from the
port, the loop should have a counter limit in it, so in case of some
unexpected situation, it can always make an exit, and not lock up.
So, in your case, if the loop counter limit is hit, it would mean that
although we had an RX interrupt flag set, there are no tokens, so act
according with a suitable error path.

I had to implement this in one Linux kernel driver due to an error
condition that happened on PCMCIA card insertion.
On the first insertion, there were unwanted IRQ calls, but after the
second false IRQ call, it calmed down. I used a counter limit in the
IRQ driver in order to handle the false IRQ calls situation.

Kind Regards

James


From mad_soft at inbox.ru  Fri Mar  9 05:09:20 2012
From: mad_soft at inbox.ru (Dmitry Artamonow)
Date: Fri,  9 Mar 2012 14:09:20 +0400
Subject: [PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection loop
In-Reply-To: <20120306201538.GA14350@rainbow>
References: <20120306201538.GA14350@rainbow>
Message-ID: <1331287760-10546-1-git-send-email-mad_soft@inbox.ru>

Tegra PCIe driver waits for PLL to lock using busy loop.
If PLL fails to lock for some reason, this leads to silent lockup
while booting (PCIe code is not modular).

Fix by adding timeout, so if PLL doesn't lock in a couple
of seconds, just PCIe driver fails and machine continues to boot.

Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>
---
Changes v1 -> v2:
* msleep is changed to usleep_range
* function now returns 0 on success instead of undefined value

 arch/arm/mach-tegra/pcie.c |   16 ++++++++++++----
 1 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 14b29ab..90f85eb 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
 	afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
 	u32 val, reg;
-	int i;
+	int i, timeout;
 
 	/* Enable slot clock and pulse the reset signals */
 	for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
+	timeout = 2000;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
+		usleep_range(1000, 1000);
+		if (--timeout == 0) {
+			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+			return -EBUSY;
+		}
 	} while (!(val & PADS_PLL_CTL_LOCKDET));
 
 	/* turn off IDDQ override */
@@ -671,7 +677,7 @@ static void tegra_pcie_enable_controller(void)
 	/* Disable all execptions */
 	afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-	return;
+	return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
 	if (err)
 		return err;
 
-	tegra_pcie_enable_controller();
+	err = tegra_pcie_enable_controller();
+	if (err)
+		return err;
 
 	/* setup the AFI address translations */
 	tegra_pcie_setup_translations();
-- 
1.7.5.1.300.gc565c



From bryan.wu at canonical.com  Sat Mar 10 06:15:18 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Sat, 10 Mar 2012 19:15:18 +0800
Subject: [PATCH 2/3] led-triggers: use atomic kzalloc during led trigger
 registering
In-Reply-To: <20120308092913.GF14173@pengutronix.de>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
 <1331197863-25564-2-git-send-email-bryan.wu@canonical.com>
 <20120308092913.GF14173@pengutronix.de>
Message-ID: <CAK5ve-+L9gVBOp4RVe2pTUbBnrb-PEn7ERbWWkb=7A=4qOrdTQ@mail.gmail.com>

2012/3/8 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> On Thu, Mar 08, 2012 at 05:11:02PM +0800, Bryan Wu wrote:
>> kzalloc might cause sleep and will generate some warning detected by lockdep,
>> when call led_trigger_register_simple on each cpu cores in SMP. This patch fix
>> this.
> The obvious (and IMHO better) alternative is to call
> led_trigger_register_simple from non-atomic context.
>
> For registering this should be OK, shouldn't it?
>
Thanks Uwe, it's my bad. I think I should not use on_each_cpu() API to
run led_trigger_register_simple. on_each_cpu() will disable interrupt.

Let's ignore this patch and I will update my ledtrig-cpu patch to use
for_each_cpu().

And thanks Ming for your advice.

Best Regards,
-Bryan

>
>>
>> [ ? ?1.999938] ------------[ cut here ]------------
>> [ ? ?2.004791] WARNING: at kernel/lockdep.c:2664 lockdep_trace_alloc+0xd8/0xf0()
>> [ ? ?2.012298] Modules linked in:
>> [ ? ?2.015563] [<c001b0cc>] (unwind_backtrace+0x0/0xf0) from [<c0052408>] (warn_slowpath_common+0x4c/0x64)
>> [ ? ?2.025451] [<c0052408>] (warn_slowpath_common+0x4c/0x64) from [<c005243c>] (warn_slowpath_null+0x1c/0x24)
>> [ ? ?2.035583] [<c005243c>] (warn_slowpath_null+0x1c/0x24) from [<c008be28>] (lockdep_trace_alloc+0xd8/0xf0)
>> [ ? ?2.045684] [<c008be28>] (lockdep_trace_alloc+0xd8/0xf0) from [<c00feeb4>] (kmem_cache_alloc_trace+0x2c/0x148)
>> [ ? ?2.056213] [<c00feeb4>] (kmem_cache_alloc_trace+0x2c/0x148) from [<c03770a0>] (led_trigger_register_simple+0x20/0x74)
>> [ ? ?2.067474] [<c03770a0>] (led_trigger_register_simple+0x20/0x74) from [<c0627a30>] (ledtrig_cpu_register+0x4c/0x8c)
>> [ ? ?2.078460] [<c0627a30>] (ledtrig_cpu_register+0x4c/0x8c) from [<c0094ca4>] (generic_smp_call_function_single_interrupt+0xcc/0x138)
>> [ ? ?2.090911] [<c0094ca4>] (generic_smp_call_function_single_interrupt+0xcc/0x138) from [<c0008408>] (do_IPI+0xb0/0x128)
>> [ ? ?2.102172] [<c0008408>] (do_IPI+0xb0/0x128) from [<c045921c>] (__irq_svc+0x3c/0x100)
>> [ ? ?2.110412] Exception stack(0xc07adf70 to 0xc07adfb8)
>> [ ? ?2.115722] df60: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? c07c80f8 0000fb45 00000000 c07c80f8
>> [ ? ?2.124328] df80: c07ac000 c0837be4 c0464b64 c07c9d8c 00000000 411fc092 00000000 00000000
>> [ ? ?2.132934] dfa0: c0649760 c07adfb8 c07c5c58 c0014d50 20000013 ffffffff
>> [ ? ?2.139892] [<c045921c>] (__irq_svc+0x3c/0x100) from [<c0014d50>] (default_idle+0x30/0x38)
>> [ ? ?2.148590] [<c0014d50>] (default_idle+0x30/0x38) from [<c0014f74>] (cpu_idle+0xb4/0xf4)
>> [ ? ?2.157135] [<c0014f74>] (cpu_idle+0xb4/0xf4) from [<c0602778>] (start_kernel+0x2a8/0x2fc)
>> [ ? ?2.165832] [<c0602778>] (start_kernel+0x2a8/0x2fc) from [<80008040>] (0x80008040)
>> [ ? ?2.173797] ---[ end trace 97549d21d8dad3f5 ]---
>>
>> Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
>> ---
>> ?drivers/leds/led-triggers.c | ? ?2 +-
>> ?1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/leds/led-triggers.c b/drivers/leds/led-triggers.c
>> index 46b4c76..74d0ba7 100644
>> --- a/drivers/leds/led-triggers.c
>> +++ b/drivers/leds/led-triggers.c
>> @@ -255,7 +255,7 @@ void led_trigger_register_simple(const char *name, struct led_trigger **tp)
>> ? ? ? struct led_trigger *trigger;
>> ? ? ? int err;
>>
>> - ? ? trigger = kzalloc(sizeof(struct led_trigger), GFP_KERNEL);
>> + ? ? trigger = kzalloc(sizeof(struct led_trigger), GFP_ATOMIC);
>>
>> ? ? ? if (trigger) {
>> ? ? ? ? ? ? ? trigger->name = name;
>> --
>> 1.7.9
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | Uwe Kleine-K?nig ? ? ? ? ? ?|
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|



-- 
Bryan Wu <bryan.wu at canonical.com>
Kernel Developer ? ?+86.138-1617-6545 Mobile
Ubuntu ARM Team
Canonical Ltd. ? ? ?www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com


From philippe.retornaz at epfl.ch  Mon Mar 12 04:11:50 2012
From: philippe.retornaz at epfl.ch (Philippe =?ISO-8859-1?Q?R=E9tornaz?=)
Date: Mon, 12 Mar 2012 09:11:50 +0100
Subject: [PATCH 2/4] Add imx3sound sound support.
In-Reply-To: <CAOMZO5DP4P9Lq-gH_NNtDxwf8DxVAVg9MWHKr1E3RoexOgNYnQ@mail.gmail.com>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-3-git-send-email-philippe.retornaz@epfl.ch>
 <CAOMZO5DP4P9Lq-gH_NNtDxwf8DxVAVg9MWHKr1E3RoexOgNYnQ@mail.gmail.com>
Message-ID: <4989193.ghnyrmjmJD@laptop>

Le dimanche 11 mars 2012 11:59:40 Fabio Estevam a ?crit :
> On Fri, Mar 9, 2012 at 11:55 AM, Philippe R?tornaz
> 
> <philippe.retornaz at epfl.ch> wrote:
> > --- /dev/null
> > +++ b/sound/soc/imx/imx3sound-mc13783.c
> > @@ -0,0 +1,141 @@
> > +/*
> > + * imx3sound-mc13783.c  --  SoC audio for imx31_3ds based boards
> 
> Please rename this file to  "imx-mc13783.c".
> 
> mx27pdk board also has a mc13783 and will use this file.
> 
> It is not restricted to mx3 boards.

Ok, will do.

Thanks,

Philippe



From philippe.retornaz at epfl.ch  Mon Mar 12 04:11:08 2012
From: philippe.retornaz at epfl.ch (Philippe =?ISO-8859-1?Q?R=E9tornaz?=)
Date: Mon, 12 Mar 2012 09:11:08 +0100
Subject: [PATCH 1/4] add a mc13783 codec driver
In-Reply-To: <20120311113848.GA3233@opensource.wolfsonmicro.com>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
 <20120311113848.GA3233@opensource.wolfsonmicro.com>
Message-ID: <1496586.ebXd01ibP4@laptop>

Le dimanche 11 mars 2012 11:38:48 Mark Brown a ?crit :
> On Fri, Mar 09, 2012 at 03:55:13PM +0100, Philippe R?tornaz wrote:
> > From: Sascha Hauer <s.hauer at pengutronix.de>
> > 
> > sha 20111307:
> > - rebased to 3.0-rc2
> > - implement tdm slot settings
> > - made it work with single ssi port
> > - more register names instead of hardcoded numbers
> > 
> > philippe 20120803:
> > - Add headset detection
> > - add mic2 bias
> > - enable headset output by default
> 
> If including stuff like this please include it after the ---.  Things
> like notes about the odd arrangements with the SSI ports which will have
> ongoing meaning are much more useful in the changelog.
> 
> Overall this looks fairly clean but very out of date, for example
> there's a custom register cache impelementation and no DAPM.

Thank you for this detailed review. I will redo the patch based on your 
comments. I had a quick look at DAPM (dapm.txt in asoc documentation), but is 
there any good "reference" implementation which is in the kernel where I could 
have a look ? 

Thanks,

Philippe




From sfr at canb.auug.org.au  Fri Mar  9 02:15:17 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 9 Mar 2012 18:15:17 +1100
Subject: linux-next: manual merge of the arm-soc tree with the regulator tree
Message-ID: <20120309181517.dce3405dc696afdf1a29be39@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
drivers/regulator/Kconfig between commit 8aa1ab9219e7 ("regulator: Sort
Kconfig and Makefile entries") from the regulator tree and commit
8a16a701ad78 ("regulator: Remove bq24022 regulator driver") from the
arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc drivers/regulator/Kconfig
index c733df5,740f468..0000000
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@@ -232,32 -233,6 +232,24 @@@ config REGULATOR_AB310
  	 AB3100 analog baseband dealing with power regulators
  	 for the system.
  
 +config REGULATOR_AB8500
 +	bool "ST-Ericsson AB8500 Power Regulators"
 +	depends on AB8500_CORE
 +	help
 +	  This driver supports the regulators found on the ST-Ericsson mixed
 +	  signal AB8500 PMIC
 +
 +config REGULATOR_DBX500_PRCMU
 +	bool
 +
 +config REGULATOR_DB8500_PRCMU
 +	bool "ST-Ericsson DB8500 Voltage Domain Regulators"
 +	depends on MFD_DB8500_PRCMU
 +	select REGULATOR_DBX500_PRCMU
 +	help
 +	  This driver supports the voltage domain regulators controlled by the
 +	  DB8500 PRCMU
 +
- config REGULATOR_BQ24022
- 	tristate "TI bq24022 Dual Input 1-Cell Li-Ion Charger IC"
- 	help
- 	  This driver controls a TI bq24022 Charger attached via
- 	  GPIOs. The provided current regulator can enable/disable
- 	  charging select between 100 mA and 500 mA charging current
- 	  limit.
- 
  config REGULATOR_TPS6105X
  	tristate "TI TPS6105X Power regulators"
  	depends on TPS6105X
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From b39297 at freescale.com  Fri Mar  9 00:05:21 2012
From: b39297 at freescale.com (Wu Guoxing)
Date: Fri, 9 Mar 2012 13:05:21 +0800
Subject: [PATCH v6] ARM : mx35: 3ds-board: add framebuffer device
Message-ID: <1331269521-20784-1-git-send-email-b39297@freescale.com>

From: wu guoxing <b39297 at freescale.com>

This patch adds framebuffer support for freescale mx35 3ds board

Signed-off-by: Wu Guoxing <b39297 at freescale.com>
---
Changes since v5:
	1. fixed a typo error in fb_modedb[].
Changes since v4:
	1. fixed a typo error in mx35_3ds_lcd_set_power.
Changes since v3:
	1. use a static variable to save the gpio value instead of find
	the gpiochip every time.
	2. add gpio_request after found the gpio.
Changes since v2:
	1. use gpio_set_value_cansleep instead of gpio_set_value
Changes since v1:
	1. use gpio driver for mc9s08dz60

 arch/arm/mach-imx/mach-mx35_3ds.c |  121 +++++++++++++++++++++++++++++++++++++
 1 files changed, 121 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c..01856b1 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -40,9 +40,94 @@
 #include <mach/iomux-mx35.h>
 #include <mach/irqs.h>
 #include <mach/3ds_debugboard.h>
+#include <video/platform_lcd.h>
 
 #include "devices-imx35.h"
 
+static const struct fb_videomode fb_modedb[] = {
+	{
+		 /* 800x480 @ 55 Hz */
+		.name = "Ceramate-CLAA070VC01",
+		.refresh = 55,
+		.xres = 800,
+		.yres = 480,
+		.pixclock = 40000,
+		.left_margin = 40,
+		.right_margin = 40,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 20,
+		.vsync_len = 10,
+		.sync = FB_SYNC_OE_ACT_HIGH,
+		.vmode = FB_VMODE_NONINTERLACED,
+		.flag = 0,
+	 },
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+	.irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+	.name = "Ceramate-CLAA070VC01",
+	.mode = fb_modedb,
+	.num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static struct i2c_board_info __initdata i2c_devices_3ds[] = {
+	{
+		I2C_BOARD_INFO("mc9s08dz60", 0x69),
+	},
+};
+
+static int lcd_power_gpio = -ENXIO;
+
+static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
+						     void *data)
+{
+	return !strcmp(chip->label, data);
+}
+
+static int mc9s08dz60_lcd_gpio_get(void)
+{
+	struct gpio_chip *chip;
+
+	if (!gpio_is_valid(lcd_power_gpio)) {
+		chip = gpiochip_find(
+				"mc9s08dz60", mc9s08dz60_gpiochip_match);
+		if (chip) {
+			lcd_power_gpio = chip->base + 6;
+			if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
+				pr_err("error: gpio already requested by other!\n");
+				lcd_power_gpio = -ENXIO;
+			}
+		} else {
+			pr_err("error: didn't find mc9s08dz60 gpio chip\n");
+			lcd_power_gpio = -ENXIO;
+		}
+	}
+
+	return lcd_power_gpio;
+}
+
+static void mx35_3ds_lcd_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+	int gpio;
+
+	gpio = mc9s08dz60_lcd_gpio_get();
+	if (gpio_is_valid(gpio))
+		gpio_set_value_cansleep(gpio, power);
+}
+
+static struct plat_lcd_data mx35_3ds_lcd_data = {
+	.set_power = mx35_3ds_lcd_set_power,
+};
+
+static struct platform_device mx35_3ds_lcd = {
+	.name = "platform-lcd",
+	.dev.platform_data = &mx35_3ds_lcd_data,
+};
+
 #define EXPIO_PARENT_INT	gpio_to_irq(IMX_GPIO_NR(1, 1))
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -120,6 +205,32 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
 	/* I2C1 */
 	MX35_PAD_I2C1_CLK__I2C1_SCL,
 	MX35_PAD_I2C1_DAT__I2C1_SDA,
+	/* Display */
+	MX35_PAD_LD0__IPU_DISPB_DAT_0,
+	MX35_PAD_LD1__IPU_DISPB_DAT_1,
+	MX35_PAD_LD2__IPU_DISPB_DAT_2,
+	MX35_PAD_LD3__IPU_DISPB_DAT_3,
+	MX35_PAD_LD4__IPU_DISPB_DAT_4,
+	MX35_PAD_LD5__IPU_DISPB_DAT_5,
+	MX35_PAD_LD6__IPU_DISPB_DAT_6,
+	MX35_PAD_LD7__IPU_DISPB_DAT_7,
+	MX35_PAD_LD8__IPU_DISPB_DAT_8,
+	MX35_PAD_LD9__IPU_DISPB_DAT_9,
+	MX35_PAD_LD10__IPU_DISPB_DAT_10,
+	MX35_PAD_LD11__IPU_DISPB_DAT_11,
+	MX35_PAD_LD12__IPU_DISPB_DAT_12,
+	MX35_PAD_LD13__IPU_DISPB_DAT_13,
+	MX35_PAD_LD14__IPU_DISPB_DAT_14,
+	MX35_PAD_LD15__IPU_DISPB_DAT_15,
+	MX35_PAD_LD16__IPU_DISPB_DAT_16,
+	MX35_PAD_LD17__IPU_DISPB_DAT_17,
+	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
+	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
 };
 
 static int mx35_3ds_otg_init(struct platform_device *pdev)
@@ -179,6 +290,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
  */
 static void __init mx35_3ds_init(void)
 {
+	struct platform_device *imx35_fb_pdev;
+
 	imx35_soc_init();
 
 	mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
@@ -204,6 +317,14 @@ static void __init mx35_3ds_init(void)
 		pr_warn("Init of the debugboard failed, all "
 				"devices on the debugboard are unusable.\n");
 	imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+
+	i2c_register_board_info(
+		0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
+
+	imx35_add_ipu_core(&mx3_ipu_data);
+	imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
+	mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
+	platform_device_register(&mx35_3ds_lcd);
 }
 
 static void __init mx35pdk_timer_init(void)
-- 
1.7.1




From govindraj.raja at ti.com  Fri Mar  9 01:19:51 2012
From: govindraj.raja at ti.com (Raja, Govindraj)
Date: Fri, 9 Mar 2012 11:49:51 +0530
Subject: [RFC PATCH] OMAP: UART: Enable tx wakeup bit in wer
In-Reply-To: <alpine.DEB.2.00.1203062251270.23214@utopia.booyaka.com>
References: <1327412249-31575-1-git-send-email-govindraj.raja@ti.com>
 <alpine.DEB.2.00.1201251217120.5324@utopia.booyaka.com>
 <alpine.DEB.2.00.1203051321580.1430@utopia.booyaka.com>
 <CAMrsUdJqmJ75=X_Qg3vQCr7zezs0jOK8L1ri8p5K=+6ZKsRFcg@mail.gmail.com>
 <alpine.DEB.2.00.1203062251270.23214@utopia.booyaka.com>
Message-ID: <CAMrsUdL6jPguVLDnEkg-T9fyvv+XY5tkNiooZOXszUYrdrUwPw@mail.gmail.com>

On Wed, Mar 7, 2012 at 11:27 AM, Paul Walmsley <paul at pwsan.com> wrote:
> Hi
>
> On Tue, 6 Mar 2012, Raja, Govindraj wrote:
>
>> I see two ways of adding this tx wake-up flag.
>>
>> 1.) passing a feature flag from pdata and populating the feature value to wer.
>>
>> 2.) Duplicating the uart1/2/3 hwmod for omap3430 without dev attrib
>> and uart1/2/3/4
>> ? ? ?hwmod for omap3630 with dev attribs.
>>
>> Approach-2 adds unnecessary code duplication in hwmod file with and without
>> dev_attribs, So right now here is the patch to follow approach [1],
>>
>> If its strongly recommended to use approach-2 will add it.
>> (My concern is the diffstat it might produce with approach-2)
>
> Both 1 and 2 are needed.
>
> The current way that errata are handled in arch/arm/mach-omap2/serial.c
> needs to be changed. ?Those should be flags that are passed from hwmod
> dev_attr data. ?The presence of the TX wakeup bit should simply be another
> dev_attr flag. ?These flags should be passed to the driver via the
> omap_up.errata field for the time being.

okay.

>
> The exception to this is if the IP block's revision register was changed
> when TX wakeups became possible. ?If that's the case, then that mechanism
> can be used in lieu of dev_attr and platform_data in this situation.

I will check on the MVR reg available for uart-rev on different omap socs,
and will get back by end on next of week with a possible patch.

--
Thanks,
Govindraj.R


From alexg at meprolight.com  Mon Mar 12 12:06:55 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Mon, 12 Mar 2012 18:06:55 +0200
Subject: I.MX35 PDK
In-Reply-To: <CAOMZO5B_mZ16zvXdNbKP_PWM5axNPzMeHQttxe8PYHET7UMufg@mail.gmail.com>
References: <CAOMZO5DnP7+zupy9vwBPS0+2XtKM1+nLbwCqBzuCqEG5OWbZRQ@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A28@MEP-EXCH.meprolight.com>
 <CAOMZO5Amo0XFf+TV7PprCL079C5Y0qKmo+k-FfShU7k4SG7W6Q@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8913@MEP-EXCH.meprolight.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8918@MEP-EXCH.meprolight.com>
 <CAOMZO5A6T+WdOE41Wx6Nctwz9wk8FKaxzjbAt_woZkCnuodNYg@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A29@MEP-EXCH.meprolight.com>,
 <CAOMZO5B_mZ16zvXdNbKP_PWM5axNPzMeHQttxe8PYHET7UMufg@mail.gmail.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D891C@MEP-EXCH.meprolight.com>

Thanks for your response,

> 1. Back resistor 172 to the default value.
>
> 2. Removed the resistor 146, through which a voltage was applied from a PMIC
> (EXT_3V) on "CMOS_VIO".
>
> 3. Connecting a resistor 147 which supplies power from the LDO_3V3 on
> "CMOS_VIO".

> >The camera on the FSL BSP works fine with no hardware modification on
> >the mx35pdk.

> >As I suggested previously you should control the power rails, i2c pad
> >settings, etc from software so that the camera can also work in
> >mainline without the need of changing the hardware.

You're right, currently mainline Linux kernel  i.MX35 PDK platform does not support power management 
devices, probably for this reason was the need for small changes in equipment.

> On my display I see snow flickering and unfortunately not a live video from
> camera.

> >Do you have this patch applied?

Yes I need to prepare it.


 > >http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=f910fb8fcd1c97788f2291c8646597bcd87ee061

> >Also, try to isolate the display from this issue. Capture the image to
> >a file and try to play it on a PC.

Thanks for the tip, I'll think about how I can check it.

Regards

Alex Gershgorin 

 


From philipp.zabel at gmail.com  Sat Mar 10 10:09:43 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Sat, 10 Mar 2012 16:09:43 +0100
Subject: [PATCH v3] pxa/hx4700: Fix basic suspend/resume
In-Reply-To: <1331391265.88838.YahooMailClassic@web29002.mail.ird.yahoo.com>
References: <1331391265.88838.YahooMailClassic@web29002.mail.ird.yahoo.com>
Message-ID: <CA+gwMcfa4Bqcj-86cW8tuFLtXVFWayeXzACJHb0xdkxY4r8Q4w@mail.gmail.com>

On Sat, Mar 10, 2012 at 3:54 PM, Paul Parsons <lost.distance at yahoo.com> wrote:
> Basic suspend/resume is fixed by ensuring that the PGSR registers are set
> correctly before sleep mode is entered. In particular four of the active low
> resets need to be driven high while in sleep mode, otherwise the unit resets
> itself instead of suspending. Another problem was that the PCFR_GPROD bit is set
> by the HTC bootloader; this caused GPIO reset (i.e. the reset button) to fail
> immediately after returning from sleep mode.
>
> Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
> ---
>
> V3:
> Changed GPIO72, GPIO96 back to KEEP_OUTPUT.

Thanks!

Acked-by: Philipp Zabel <philipp.zabel at gmail.com>

> diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c
> --- clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c ? ?2012-03-04 01:08:09.000000000 +0000
> +++ linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c ? ?2012-03-10 14:42:41.328255002 +0000
> @@ -121,7 +121,11 @@ static unsigned long hx4700_pin_config[]
> ? ? ? ?GPIO19_SSP2_SCLK,
> ? ? ? ?GPIO86_SSP2_RXD,
> ? ? ? ?GPIO87_SSP2_TXD,
> - ? ? ? GPIO88_GPIO,
> + ? ? ? GPIO88_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ? /* TSC2046_CS */
> +
> + ? ? ? /* BQ24022 Regulator */
> + ? ? ? GPIO72_GPIO | MFP_LPM_KEEP_OUTPUT, ? ? ?/* BQ24022_nCHARGE_EN */
> + ? ? ? GPIO96_GPIO | MFP_LPM_KEEP_OUTPUT, ? ? ?/* BQ24022_ISET2 */
>
> ? ? ? ?/* HX4700 specific input GPIOs */
> ? ? ? ?GPIO12_GPIO, ? ?/* ASIC3_IRQ */
> @@ -134,6 +138,11 @@ static unsigned long hx4700_pin_config[]
> ? ? ? ?GPIO108_GPIO, ? /* GSM_READY */
> ? ? ? ?GPIO58_GPIO, ? ?/* TSC2046_nPENIRQ */
> ? ? ? ?GPIO66_GPIO, ? ?/* nSDIO_IRQ */
> +
> + ? ? ? GPIO61_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ? /* W3220_nRESET */
> + ? ? ? GPIO71_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ? /* ASIC3_nRESET */
> + ? ? ? GPIO81_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ? /* CPU_GP_nRESET */
> + ? ? ? GPIO116_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ?/* CPU_HW_nRESET */
> ?};
>
> ?/*
> @@ -828,15 +837,20 @@ static struct gpio global_gpios[] = {
> ? ? ? ?{ GPIO110_HX4700_LCD_LVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_LVDD" },
> ? ? ? ?{ GPIO111_HX4700_LCD_AVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_AVDD" },
> ? ? ? ?{ GPIO32_HX4700_RS232_ON, ? ? ? ? GPIOF_OUT_INIT_HIGH, "RS232_ON" },
> + ? ? ? { GPIO61_HX4700_W3220_nRESET, ? ? GPIOF_OUT_INIT_HIGH, "W3220_nRESET" },
> ? ? ? ?{ GPIO71_HX4700_ASIC3_nRESET, ? ? GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
> + ? ? ? { GPIO81_HX4700_CPU_GP_nRESET, ? ?GPIOF_OUT_INIT_HIGH, "CPU_GP_nRESET" },
> ? ? ? ?{ GPIO82_HX4700_EUART_RESET, ? ? ?GPIOF_OUT_INIT_HIGH, "EUART_RESET" },
> ? ? ? ?{ GPIO105_HX4700_nIR_ON, ? ? ? ? ?GPIOF_OUT_INIT_HIGH, "nIR_EN" },
> + ? ? ? { GPIO116_HX4700_CPU_HW_nRESET, ? GPIOF_OUT_INIT_HIGH, "CPU_HW_nRESET" },
> ?};
>
> ?static void __init hx4700_init(void)
> ?{
> ? ? ? ?int ret;
>
> + ? ? ? PCFR = PCFR_GPR_EN | PCFR_OPDE;
> +
> ? ? ? ?pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
> ? ? ? ?ret = gpio_request_array(ARRAY_AND_SIZE(global_gpios));
> ? ? ? ?if (ret)
>


From viresh.kumar at st.com  Mon Mar 12 00:22:16 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:16 +0530
Subject: [PATCH V2 21/22] watchdog/sp805: convert to watchdog core
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <5995d6811770943879be2ab5bcc0810aa38dd72f.1331524811.git.viresh.kumar@st.com>

This patch converts existing sp805 watchdog driver to use already in place
common infrastructure present in watchdog core. With this lot of code goes away.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/Kconfig     |    1 +
 drivers/watchdog/sp805_wdt.c |  241 ++++++++++++++---------------------------
 2 files changed, 83 insertions(+), 159 deletions(-)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index f66617a..438c393 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -85,6 +85,7 @@ config WM8350_WATCHDOG
 config ARM_SP805_WATCHDOG
 	tristate "ARM SP805 Watchdog"
 	depends on ARM_AMBA
+	select WATCHDOG_CORE
 	help
 	  ARM Primecell SP805 Watchdog timer. This will reboot your system when
 	  the timeout is reached.
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 859d8b0..5c34eda 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -16,20 +16,17 @@
 #include <linux/amba/bus.h>
 #include <linux/bitops.h>
 #include <linux/clk.h>
-#include <linux/fs.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/kernel.h>
 #include <linux/math64.h>
-#include <linux/miscdevice.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/pm.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/types.h>
-#include <linux/uaccess.h>
 #include <linux/watchdog.h>
 
 /* default timeout in seconds */
@@ -56,6 +53,7 @@
 
 /**
  * struct sp805_wdt: sp805 wdt device structure
+ * @wdd: instance of struct watchdog_device
  * @lock: spin lock protecting dev structure and io access
  * @base: base address of wdt
  * @clk: clock structure of wdt
@@ -65,24 +63,24 @@
  * @timeout: current programmed timeout
  */
 struct sp805_wdt {
+	struct watchdog_device		wdd;
 	spinlock_t			lock;
 	void __iomem			*base;
 	struct clk			*clk;
 	struct amba_device		*adev;
-	unsigned long			status;
-	#define WDT_BUSY		0
-	#define WDT_CAN_BE_CLOSED	1
 	unsigned int			load_val;
 	unsigned int			timeout;
 };
 
-/* local variables */
-static struct sp805_wdt *wdt;
 static int nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout,
+		"Set to 1 to keep watchdog running after device release");
 
 /* This routine finds load value that will reset system in required timout */
-static void wdt_setload(unsigned int timeout)
+static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
 {
+	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
 	u64 load, rate;
 
 	rate = clk_get_rate(wdt->clk);
@@ -103,11 +101,14 @@ static void wdt_setload(unsigned int timeout)
 	/* roundup timeout to closest positive integer value */
 	wdt->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
 	spin_unlock(&wdt->lock);
+
+	return 0;
 }
 
 /* returns number of seconds left for reset to occur */
-static u32 wdt_timeleft(void)
+static unsigned int wdt_timeleft(struct watchdog_device *wdd)
 {
+	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
 	u64 load, rate;
 
 	rate = clk_get_rate(wdt->clk);
@@ -123,166 +124,88 @@ static u32 wdt_timeleft(void)
 	return div_u64(load, rate);
 }
 
-/* enables watchdog timers reset */
-static void wdt_enable(void)
+static int wdt_config(struct watchdog_device *wdd, bool ping)
 {
+	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
+	int ret;
+
+	if (!ping) {
+		ret = clk_enable(wdt->clk);
+		if (ret) {
+			dev_err(&wdt->adev->dev, "clock enable fail");
+			return ret;
+		}
+	}
+
 	spin_lock(&wdt->lock);
 
 	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
 	writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
-	writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
-	writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
-	writel_relaxed(LOCK, wdt->base + WDTLOCK);
-
-	/* Flush posted writes. */
-	readl_relaxed(wdt->base + WDTLOCK);
-	spin_unlock(&wdt->lock);
-}
 
-/* disables watchdog timers reset */
-static void wdt_disable(void)
-{
-	spin_lock(&wdt->lock);
+	if (!ping) {
+		writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
+		writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
+				WDTCONTROL);
+	}
 
-	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
-	writel_relaxed(0, wdt->base + WDTCONTROL);
 	writel_relaxed(LOCK, wdt->base + WDTLOCK);
 
 	/* Flush posted writes. */
 	readl_relaxed(wdt->base + WDTLOCK);
 	spin_unlock(&wdt->lock);
+
+	return 0;
 }
 
-static ssize_t sp805_wdt_write(struct file *file, const char *data,
-		size_t len, loff_t *ppos)
+static int wdt_ping(struct watchdog_device *wdd)
 {
-	if (len) {
-		if (!nowayout) {
-			size_t i;
-
-			clear_bit(WDT_CAN_BE_CLOSED, &wdt->status);
-
-			for (i = 0; i != len; i++) {
-				char c;
-
-				if (get_user(c, data + i))
-					return -EFAULT;
-				/* Check for Magic Close character */
-				if (c == 'V') {
-					set_bit(WDT_CAN_BE_CLOSED,
-							&wdt->status);
-					break;
-				}
-			}
-		}
-		wdt_enable();
-	}
-	return len;
+	return wdt_config(wdd, true);
 }
 
-static const struct watchdog_info ident = {
-	.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
-	.identity = MODULE_NAME,
-};
-
-static long sp805_wdt_ioctl(struct file *file, unsigned int cmd,
-		unsigned long arg)
+/* enables watchdog timers reset */
+static int wdt_enable(struct watchdog_device *wdd)
 {
-	int ret = -ENOTTY;
-	unsigned int timeout;
-
-	switch (cmd) {
-	case WDIOC_GETSUPPORT:
-		ret = copy_to_user((struct watchdog_info *)arg, &ident,
-				sizeof(ident)) ? -EFAULT : 0;
-		break;
-
-	case WDIOC_GETSTATUS:
-		ret = put_user(0, (int *)arg);
-		break;
-
-	case WDIOC_KEEPALIVE:
-		wdt_enable();
-		ret = 0;
-		break;
-
-	case WDIOC_SETTIMEOUT:
-		ret = get_user(timeout, (unsigned int *)arg);
-		if (ret)
-			break;
-
-		wdt_setload(timeout);
-
-		wdt_enable();
-		/* Fall through */
-
-	case WDIOC_GETTIMEOUT:
-		ret = put_user(wdt->timeout, (unsigned int *)arg);
-		break;
-	case WDIOC_GETTIMELEFT:
-		ret = put_user(wdt_timeleft(), (unsigned int *)arg);
-		break;
-	}
-	return ret;
+	return wdt_config(wdd, false);
 }
 
-static int sp805_wdt_open(struct inode *inode, struct file *file)
+/* disables watchdog timers reset */
+static int wdt_disable(struct watchdog_device *wdd)
 {
-	int ret = 0;
+	struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
 
-	if (test_and_set_bit(WDT_BUSY, &wdt->status))
-		return -EBUSY;
-
-	ret = clk_enable(wdt->clk);
-	if (ret) {
-		dev_err(&wdt->adev->dev, "clock enable fail");
-		goto err;
-	}
-
-	wdt_enable();
-
-	/* can not be closed, once enabled */
-	clear_bit(WDT_CAN_BE_CLOSED, &wdt->status);
-	return nonseekable_open(inode, file);
+	spin_lock(&wdt->lock);
 
-err:
-	clear_bit(WDT_BUSY, &wdt->status);
-	return ret;
-}
+	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
+	writel_relaxed(0, wdt->base + WDTCONTROL);
+	writel_relaxed(LOCK, wdt->base + WDTLOCK);
 
-static int sp805_wdt_release(struct inode *inode, struct file *file)
-{
-	if (!test_bit(WDT_CAN_BE_CLOSED, &wdt->status)) {
-		clear_bit(WDT_BUSY, &wdt->status);
-		dev_warn(&wdt->adev->dev, "Device closed unexpectedly\n");
-		return 0;
-	}
+	/* Flush posted writes. */
+	readl_relaxed(wdt->base + WDTLOCK);
+	spin_unlock(&wdt->lock);
 
-	wdt_disable();
 	clk_disable(wdt->clk);
-	clear_bit(WDT_BUSY, &wdt->status);
 
 	return 0;
 }
 
-static const struct file_operations sp805_wdt_fops = {
-	.owner = THIS_MODULE,
-	.llseek = no_llseek,
-	.write = sp805_wdt_write,
-	.unlocked_ioctl = sp805_wdt_ioctl,
-	.open = sp805_wdt_open,
-	.release = sp805_wdt_release,
+static const struct watchdog_info wdt_info = {
+	.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
+	.identity = MODULE_NAME,
 };
 
-static struct miscdevice sp805_wdt_miscdev = {
-	.minor = WATCHDOG_MINOR,
-	.name = "watchdog",
-	.fops = &sp805_wdt_fops,
+static const struct watchdog_ops wdt_ops = {
+	.owner		= THIS_MODULE,
+	.start		= wdt_enable,
+	.stop		= wdt_disable,
+	.ping		= wdt_ping,
+	.set_timeout	= wdt_setload,
+	.get_timeleft	= wdt_timeleft,
 };
 
 static int __devinit
 sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
 {
+	struct sp805_wdt *wdt;
 	int ret = 0;
 
 	if (!devm_request_mem_region(&adev->dev, adev->res.start,
@@ -315,19 +238,26 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
 	}
 
 	wdt->adev = adev;
+	wdt->wdd.info = &wdt_info;
+	wdt->wdd.ops = &wdt_ops;
+
 	spin_lock_init(&wdt->lock);
-	wdt_setload(DEFAULT_TIMEOUT);
+	watchdog_set_nowayout(&wdt->wdd, nowayout);
+	wdt_setload(&wdt->wdd, DEFAULT_TIMEOUT);
 
-	ret = misc_register(&sp805_wdt_miscdev);
-	if (ret < 0) {
-		dev_warn(&adev->dev, "cannot register misc device\n");
-		goto err_misc_register;
+	ret = watchdog_register_device(&wdt->wdd);
+	if (ret) {
+		dev_err(&adev->dev, "watchdog_register_device() failed: %d\n",
+				ret);
+		goto err_register;
 	}
+	amba_set_drvdata(adev, wdt);
+	watchdog_set_drvdata(&wdt->wdd, wdt);
 
 	dev_info(&adev->dev, "registration successful\n");
 	return 0;
 
-err_misc_register:
+err_register:
 	clk_put(wdt->clk);
 err:
 	dev_err(&adev->dev, "Probe Failed!!!\n");
@@ -336,7 +266,11 @@ err:
 
 static int __devexit sp805_wdt_remove(struct amba_device *adev)
 {
-	misc_deregister(&sp805_wdt_miscdev);
+	struct sp805_wdt *wdt = amba_get_drvdata(adev);
+
+	watchdog_unregister_device(&wdt->wdd);
+	amba_set_drvdata(adev, NULL);
+	watchdog_set_drvdata(&wdt->wdd, NULL);
 	clk_put(wdt->clk);
 
 	return 0;
@@ -345,28 +279,22 @@ static int __devexit sp805_wdt_remove(struct amba_device *adev)
 #ifdef CONFIG_PM
 static int sp805_wdt_suspend(struct device *dev)
 {
-	if (test_bit(WDT_BUSY, &wdt->status)) {
-		wdt_disable();
-		clk_disable(wdt->clk);
-	}
+	struct sp805_wdt *wdt = dev_get_drvdata(dev);
+
+	if (is_wdd_active(&wdt->wdd))
+		return wdt_disable(&wdt->wdd);
 
 	return 0;
 }
 
 static int sp805_wdt_resume(struct device *dev)
 {
-	int ret = 0;
+	struct sp805_wdt *wdt = dev_get_drvdata(dev);
 
-	if (test_bit(WDT_BUSY, &wdt->status)) {
-		ret = clk_enable(wdt->clk);
-		if (ret) {
-			dev_err(dev, "clock enable fail");
-			return ret;
-		}
-		wdt_enable();
-	}
+	if (is_wdd_active(&wdt->wdd))
+		return wdt_enable(&wdt->wdd);
 
-	return ret;
+	return 0;
 }
 #endif /* CONFIG_PM */
 
@@ -405,11 +333,6 @@ static void __exit sp805_wdt_exit(void)
 }
 module_exit(sp805_wdt_exit);
 
-module_param(nowayout, int, 0);
-MODULE_PARM_DESC(nowayout,
-		"Set to 1 to keep watchdog running after device release");
-
 MODULE_AUTHOR("Viresh Kumar <viresh.kumar at st.com>");
 MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
 MODULE_LICENSE("GPL");
-MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:22:15 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:15 +0530
Subject: [PATCH V2 20/22] watchdog/sp805: Use devm routines
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <5b951b210d14db05858e7fccb4d184df9a56a719.1331524811.git.viresh.kumar@st.com>

sp805 driver currently uses normal kzalloc, ioremap, etc routines. This patch
replaces these routines with devm_kzalloc and devm_request_mem_region etc, so
that we don't need to handle freeing of resources for error cases and module
removal routine.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/sp805_wdt.c |   35 +++++++++++++----------------------
 1 files changed, 13 insertions(+), 22 deletions(-)

diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 1291960..859d8b0 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -285,32 +285,33 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
 {
 	int ret = 0;
 
-	if (!request_mem_region(adev->res.start, resource_size(&adev->res),
-				"sp805_wdt")) {
+	if (!devm_request_mem_region(&adev->dev, adev->res.start,
+				resource_size(&adev->res), "sp805_wdt")) {
 		dev_warn(&adev->dev, "Failed to get memory region resource\n");
 		ret = -ENOENT;
 		goto err;
 	}
 
-	wdt = kzalloc(sizeof(*wdt), GFP_KERNEL);
+	wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
 	if (!wdt) {
 		dev_warn(&adev->dev, "Kzalloc failed\n");
 		ret = -ENOMEM;
-		goto err_kzalloc;
+		goto err;
+	}
+
+	wdt->base = devm_ioremap(&adev->dev, adev->res.start,
+			resource_size(&adev->res));
+	if (!wdt->base) {
+		ret = -ENOMEM;
+		dev_warn(&adev->dev, "ioremap fail\n");
+		goto err;
 	}
 
 	wdt->clk = clk_get(&adev->dev, NULL);
 	if (IS_ERR(wdt->clk)) {
 		dev_warn(&adev->dev, "Clock not found\n");
 		ret = PTR_ERR(wdt->clk);
-		goto err_clk_get;
-	}
-
-	wdt->base = ioremap(adev->res.start, resource_size(&adev->res));
-	if (!wdt->base) {
-		ret = -ENOMEM;
-		dev_warn(&adev->dev, "ioremap fail\n");
-		goto err_ioremap;
+		goto err;
 	}
 
 	wdt->adev = adev;
@@ -327,14 +328,7 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
 	return 0;
 
 err_misc_register:
-	iounmap(wdt->base);
-err_ioremap:
 	clk_put(wdt->clk);
-err_clk_get:
-	kfree(wdt);
-	wdt = NULL;
-err_kzalloc:
-	release_mem_region(adev->res.start, resource_size(&adev->res));
 err:
 	dev_err(&adev->dev, "Probe Failed!!!\n");
 	return ret;
@@ -343,10 +337,7 @@ err:
 static int __devexit sp805_wdt_remove(struct amba_device *adev)
 {
 	misc_deregister(&sp805_wdt_miscdev);
-	iounmap(wdt->base);
 	clk_put(wdt->clk);
-	kfree(wdt);
-	release_mem_region(adev->res.start, resource_size(&adev->res));
 
 	return 0;
 }
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:22:14 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:14 +0530
Subject: [PATCH V2 19/22] watchdog/sp805: replace readl/writel with lighter
 _relaxed variants
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <5a279730768f9532101283ccea2990cb691824ff.1331524811.git.viresh.kumar@st.com>

readl/writel versions for ARM contain memory barrier instruction for
synchronizing DMA buffers.  These are not required at least on this
module.  So use lighter _relaxed variants.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/sp805_wdt.c |   24 ++++++++++++------------
 1 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 7af1386..1291960 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -113,10 +113,10 @@ static u32 wdt_timeleft(void)
 	rate = clk_get_rate(wdt->clk);
 
 	spin_lock(&wdt->lock);
-	load = readl(wdt->base + WDTVALUE);
+	load = readl_relaxed(wdt->base + WDTVALUE);
 
 	/*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
-	if (!(readl(wdt->base + WDTRIS) & INT_MASK))
+	if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
 		load += wdt->load_val + 1;
 	spin_unlock(&wdt->lock);
 
@@ -128,14 +128,14 @@ static void wdt_enable(void)
 {
 	spin_lock(&wdt->lock);
 
-	writel(UNLOCK, wdt->base + WDTLOCK);
-	writel(wdt->load_val, wdt->base + WDTLOAD);
-	writel(INT_MASK, wdt->base + WDTINTCLR);
-	writel(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
-	writel(LOCK, wdt->base + WDTLOCK);
+	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
+	writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
+	writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
+	writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
+	writel_relaxed(LOCK, wdt->base + WDTLOCK);
 
 	/* Flush posted writes. */
-	readl(wdt->base + WDTLOCK);
+	readl_relaxed(wdt->base + WDTLOCK);
 	spin_unlock(&wdt->lock);
 }
 
@@ -144,12 +144,12 @@ static void wdt_disable(void)
 {
 	spin_lock(&wdt->lock);
 
-	writel(UNLOCK, wdt->base + WDTLOCK);
-	writel(0, wdt->base + WDTCONTROL);
-	writel(LOCK, wdt->base + WDTLOCK);
+	writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
+	writel_relaxed(0, wdt->base + WDTCONTROL);
+	writel_relaxed(LOCK, wdt->base + WDTLOCK);
 
 	/* Flush posted writes. */
-	readl(wdt->base + WDTLOCK);
+	readl_relaxed(wdt->base + WDTLOCK);
 	spin_unlock(&wdt->lock);
 }
 
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:22:07 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:07 +0530
Subject: [PATCH V2 12/22] watchdog/mpcore_wdt: Add support for dev_pm_ops
 interface
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <70350419aeda6aa96081b6d81407efeb17b2d87c.1331524811.git.viresh.kumar@st.com>

This patch adds dev_pm_ops support for standby/slepp/hibernate.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 6902580..3f47b7e 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -23,6 +23,7 @@
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/platform_device.h>
+#include <linux/pm.h>
 #include <linux/reboot.h>
 #include <linux/slab.h>
 #include <linux/types.h>
@@ -256,40 +257,39 @@ static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM
-static int mpcore_wdt_suspend(struct platform_device *pdev, pm_message_t msg)
+static int mpcore_wdt_suspend(struct device *dev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
+	struct mpcore_wdt *wdt = dev_get_drvdata(dev);
 	mpcore_wdt_stop(&wdt->wdd);	/* Turn the WDT off */
 
 	return 0;
 }
 
-static int mpcore_wdt_resume(struct platform_device *pdev)
+static int mpcore_wdt_resume(struct device *dev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
+	struct mpcore_wdt *wdt = dev_get_drvdata(dev);
 
 	if (is_wdd_active(&wdt->wdd))
 		mpcore_wdt_start(&wdt->wdd);
 
 	return 0;
 }
-#else
-#define mpcore_wdt_suspend	NULL
-#define mpcore_wdt_resume	NULL
 #endif
 
+static SIMPLE_DEV_PM_OPS(mpcore_wdt_dev_pm_ops, mpcore_wdt_suspend,
+		mpcore_wdt_resume);
+
 /* work with hotplug and coldplug */
 MODULE_ALIAS("platform:mpcore_wdt");
 
 static struct platform_driver mpcore_wdt_driver = {
 	.probe		= mpcore_wdt_probe,
 	.remove		= __devexit_p(mpcore_wdt_remove),
-	.suspend	= mpcore_wdt_suspend,
-	.resume		= mpcore_wdt_resume,
 	.shutdown	= mpcore_wdt_shutdown,
 	.driver		= {
 		.owner	= THIS_MODULE,
 		.name	= "mpcore_wdt",
+		.pm	= &mpcore_wdt_dev_pm_ops,
 	},
 };
 
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:22:02 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:02 +0530
Subject: [PATCH V2 07/22] watchdog/mpcore_wdt: Fix multiline comments
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <c6c6a42167a5938b869c43045fadcdfe0b069555.1331524811.git.viresh.kumar@st.com>

In case of few multiline comment a 'tab' is present instead of 'space' after the
'*' in the second column. Replace tab with space here.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   42 +++++++++++++++++++---------------------
 1 files changed, 20 insertions(+), 22 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 953044a..7c9f78c 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -1,23 +1,21 @@
 /*
- *	Watchdog driver for the mpcore watchdog timer
+ * Watchdog driver for the mpcore watchdog timer
  *
- *	(c) Copyright 2004 ARM Limited
+ * (c) Copyright 2004 ARM Limited
  *
- *	Based on the SoftDog driver:
- *	(c) Copyright 1996 Alan Cox <alan at lxorguk.ukuu.org.uk>,
- *						All Rights Reserved.
+ * Based on the SoftDog driver:
+ * (c) Copyright 1996 Alan Cox <alan at lxorguk.ukuu.org.uk>, All Rights Reserved.
  *
- *	This program is free software; you can redistribute it and/or
- *	modify it under the terms of the GNU General Public License
- *	as published by the Free Software Foundation; either version
- *	2 of the License, or (at your option) any later version.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
  *
- *	Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
- *	warranty for any of this software. This material is provided
- *	"AS-IS" and at no charge.
- *
- *	(c) Copyright 1995    Alan Cox <alan at lxorguk.ukuu.org.uk>
+ * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
+ * warranty for any of this software. This material is provided
+ * "AS-IS" and at no charge.
  *
+ * (c) Copyright 1995    Alan Cox <alan at lxorguk.ukuu.org.uk>
  */
 #include <linux/module.h>
 #include <linux/moduleparam.h>
@@ -64,8 +62,8 @@ MODULE_PARM_DESC(mpcore_noboot, "MPcore watchdog action, "
 					__MODULE_STRING(ONLY_TESTING) ")");
 
 /*
- *	This is the interrupt handler.  Note that we only use this
- *	in testing mode, so don't actually do a reboot here.
+ * This is the interrupt handler.  Note that we only use this
+ * in testing mode, so don't actually do a reboot here.
  */
 static irqreturn_t mpcore_wdt_fire(int irq, void *arg)
 {
@@ -83,11 +81,11 @@ static irqreturn_t mpcore_wdt_fire(int irq, void *arg)
 }
 
 /*
- *	mpcore_wdt_ping - reload the timer
+ * mpcore_wdt_ping - reload the timer
  *
- *	Note that the spec says a DIFFERENT value must be written to the reload
- *	register each time.  The "perturb" variable deals with this by adding 1
- *	to the count every other time the function is called.
+ * Note that the spec says a DIFFERENT value must be written to the reload
+ * register each time.  The "perturb" variable deals with this by adding 1 to
+ * the count every other time the function is called.
  */
 static int mpcore_wdt_ping(struct watchdog_device *wdd)
 {
@@ -163,8 +161,8 @@ static const struct watchdog_ops mpcore_wdt_ops = {
 };
 
 /*
- *	System shutdown handler.  Turn off the watchdog if we're
- *	restarting or halting the system.
+ * System shutdown handler.  Turn off the watchdog if we're restarting or
+ * halting the system.
  */
 static void mpcore_wdt_shutdown(struct platform_device *pdev)
 {
-- 
1.7.8.110.g4cb5d



From robherring2 at gmail.com  Mon Mar 12 16:07:26 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 12 Mar 2012 15:07:26 -0500
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <4F5E2858.4000708@st.com>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <201203121606.26926.sr@denx.de> <4F5E169D.3070508@st.com>
 <201203121723.38411.sr@denx.de> <4F5E2858.4000708@st.com>
Message-ID: <4F5E577E.7090808@gmail.com>

On 03/12/2012 11:46 AM, Giuseppe CAVALLARO wrote:
> On 3/12/2012 5:23 PM, Stefan Roese wrote:
>> On Monday 12 March 2012 16:30:37 Giuseppe CAVALLARO wrote:
>>>>>> +Required properties:
>>>>>> +- compatible: Should be "stm,gmac"
>>>>>
>>>>> This is too generic. This should be 1 string per version of h/w.
>>>>
>>>> Viresh, Giuseppe, can you please suggest a proper string for the SPEAr600
>>>> STMMAC core, including version?
>>>>
>>>>> 'stm' should be 'st' according to vendor-prefixes.txt.
>>>
>>> I'm not familiar with devicetree; maybe we should have:
>>>
>>> "stmicro,mac100"
>>> "stmicro,gmac"
>>>
>>> or: st instead of stmicro if you prefer.
>>>
>>> in fact, stmmac is for mac100 and gmac devices.
>>
>> How about "st,spear600-gmac" for SPEAr600 then?
> 
> IIUC, as final result we should have something like this... that sounds
> quite good to me.
> 
> ST/ARM SPEAr
> "st,spear600-gmac"
> "st,spear1310-gmac"
>   ...
> 
> ST/SH
> 
> "st,stx7108-gmac"
> "st,stx7106-gmac"
> "st,stx7109-mac"    ->>> mac10/100
> ...
> 
> MIPS
> "st,Loongson1B"
> 

This seems fine to me.

Rob

>>  
>>>> Okay.
>>>>
>>>>>> +- reg: Address and length of the register set for the device
>>>>>> +- interrupt-parent: Should be the phandle for the interrupt controller
>>>>>> +  that services interrupts for this device
>>>>>> +- interrupts: Should contain the STMMAC interrupts
>>>>>> +- interrupt-names: Should contain the interrupt names "macirq"
>>>>>> +  "eth_wake_irq" if this interrupt is supported in the "interrupts"
>>>>>> +  property
>>>>>
>>>>> You should be able to tell this from the compatible string and number of
>>>>> interrupts.
>>>>
>>>> Yes. Currently the driver uses platform_get_irq_byname() to register the
>>>> irq's. That's why I added these properties. Is there something wrong with
>>>> using it this way?
>>>>
>>>>>> +- phy-mode: String, operation mode of the PHY interface.
>>>>>> +  Supported values are: "mii", "rmii", "gmii", "rgmii".
>>>>>> +- phy-addr: MDIO address of the PHY
>>>>>
>>>>> This is normally probed or the mdio bus is a sub-node of the MAC node.
>>>>> See arch/powerpc/boot/dts/mpc8377_mds.dts for an example.
>>>>
>>>> Okay, I'll rework this.
>>>>
>>>>>> +
>>>>>> +Optional properties:
>>>>>> +- stm,prog-burst-len: Specify the burst length
>>>>>> +- stm,has-gmac: Indicates that the controller supports 1000Mbps
>>>>>> +- stm,has-pmt: Indicates that the controller supports power management
>>>>>
>>>>> I think these should all be encoded by the compatible string.
>>>
>>> and should we have all the other flags e.g. tx_coe etc?
>>> (see stmmac.txt)
>>
>> As Rob suggested, some of these flags/parameters are implicitly defined by the 
>> compatible string. If this is not the case, then sure, those flags/parameters 
>> need to be provided via the device-tree as well. I just don't need "tx_coe" 
>> etc. for my platform (SPEAr600) as far as I know. I suggest to add support for 
>> them once they are really needed/used by other platforms.
> 
> Ok, but on SPEAr indeed some of these are not used at all.
> If you agree, we can go head with these and then we will add new ones
> next time. In the meantime, I will try to be more familiar with
> devicetree and provide further patches
> 
> peppe
> 
>>
>> Thanks,
>> Stefan
>> --
>> To unsubscribe from this list: send the line "unsubscribe netdev" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
> 



From viresh.kumar at st.com  Mon Mar 12 00:22:00 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:00 +0530
Subject: [PATCH V2 05/22] watchdog/mpcore_wdt: Allow platform_get_irq() to fail
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <d086dbc044d530c9db101898d7e7e8d25d91c984.1331524811.git.viresh.kumar@st.com>

irq is not necessary for mpcore wdt. Don't return error if it is not passed. But
if it is passed, then request_irq must pass.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 63bd161..1d2f1a1 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -344,15 +344,15 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 
 	wdt->dev = &pdev->dev;
 	wdt->irq = platform_get_irq(pdev, 0);
-	if (wdt->irq < 0)
-		return -ENXIO;
-
-	ret = devm_request_irq(wdt->dev, wdt->irq, mpcore_wdt_fire, 0,
-			"mpcore_wdt", wdt);
-	if (ret) {
-		dev_printk(KERN_ERR, wdt->dev,
-			"cannot register IRQ%d for watchdog\n", wdt->irq);
-		return ret;
+	if (wdt->irq >= 0) {
+		ret = devm_request_irq(wdt->dev, wdt->irq, mpcore_wdt_fire, 0,
+				"mpcore_wdt", wdt);
+		if (ret) {
+			dev_printk(KERN_ERR, wdt->dev,
+					"cannot register IRQ%d for watchdog\n",
+					wdt->irq);
+			return ret;
+		}
 	}
 
 	wdt->base = devm_ioremap(wdt->dev, res->start, resource_size(res));
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:21:58 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:51:58 +0530
Subject: [PATCH V2 03/22] watchdog/mpcore_wdt: Rename dev to pdev for pointing
 to struct platform_device
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <d9bc91707225b317a0700b50e70227aae91e9d78.1331524811.git.viresh.kumar@st.com>

Pointer to struct platform_device is named as dev, which makes it confusing when
we write statements like dev->dev to access struct device within it.

This patch renames such names to pdev.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   40 ++++++++++++++++++++--------------------
 1 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 82ccd36..fd9f91b 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -44,7 +44,7 @@ struct mpcore_wdt {
 	char		expect_close;
 };
 
-static struct platform_device *mpcore_wdt_dev;
+static struct platform_device *mpcore_wdt_pdev;
 static DEFINE_SPINLOCK(wdt_lock);
 
 #define TIMER_MARGIN	60
@@ -148,7 +148,7 @@ static int mpcore_wdt_set_heartbeat(int t)
  */
 static int mpcore_wdt_open(struct inode *inode, struct file *file)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(mpcore_wdt_dev);
+	struct mpcore_wdt *wdt = platform_get_drvdata(mpcore_wdt_pdev);
 
 	if (test_and_set_bit(0, &wdt->timer_alive))
 		return -EBUSY;
@@ -298,9 +298,9 @@ static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd,
  *	System shutdown handler.  Turn off the watchdog if we're
  *	restarting or halting the system.
  */
-static void mpcore_wdt_shutdown(struct platform_device *dev)
+static void mpcore_wdt_shutdown(struct platform_device *pdev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(dev);
+	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
 
 	if (system_state == SYSTEM_RESTART || system_state == SYSTEM_HALT)
 		mpcore_wdt_stop(wdt);
@@ -324,17 +324,17 @@ static struct miscdevice mpcore_wdt_miscdev = {
 	.fops		= &mpcore_wdt_fops,
 };
 
-static int __devinit mpcore_wdt_probe(struct platform_device *dev)
+static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 {
 	struct mpcore_wdt *wdt;
 	struct resource *res;
 	int ret;
 
 	/* We only accept one device, and it must have an id of -1 */
-	if (dev->id != -1)
+	if (pdev->id != -1)
 		return -ENODEV;
 
-	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		ret = -ENODEV;
 		goto err_out;
@@ -346,8 +346,8 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev)
 		goto err_out;
 	}
 
-	wdt->dev = &dev->dev;
-	wdt->irq = platform_get_irq(dev, 0);
+	wdt->dev = &pdev->dev;
+	wdt->irq = platform_get_irq(pdev, 0);
 	if (wdt->irq < 0) {
 		ret = -ENXIO;
 		goto err_free;
@@ -358,7 +358,7 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev)
 		goto err_free;
 	}
 
-	mpcore_wdt_miscdev.parent = &dev->dev;
+	mpcore_wdt_miscdev.parent = &pdev->dev;
 	ret = misc_register(&mpcore_wdt_miscdev);
 	if (ret) {
 		dev_printk(KERN_ERR, wdt->dev,
@@ -375,8 +375,8 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev)
 	}
 
 	mpcore_wdt_stop(wdt);
-	platform_set_drvdata(dev, wdt);
-	mpcore_wdt_dev = dev;
+	platform_set_drvdata(pdev, wdt);
+	mpcore_wdt_pdev = pdev;
 
 	return 0;
 
@@ -390,15 +390,15 @@ err_out:
 	return ret;
 }
 
-static int __devexit mpcore_wdt_remove(struct platform_device *dev)
+static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(dev);
+	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
 
-	platform_set_drvdata(dev, NULL);
+	platform_set_drvdata(pdev, NULL);
 
 	misc_deregister(&mpcore_wdt_miscdev);
 
-	mpcore_wdt_dev = NULL;
+	mpcore_wdt_pdev = NULL;
 
 	free_irq(wdt->irq, wdt);
 	iounmap(wdt->base);
@@ -407,16 +407,16 @@ static int __devexit mpcore_wdt_remove(struct platform_device *dev)
 }
 
 #ifdef CONFIG_PM
-static int mpcore_wdt_suspend(struct platform_device *dev, pm_message_t msg)
+static int mpcore_wdt_suspend(struct platform_device *pdev, pm_message_t msg)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(dev);
+	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
 	mpcore_wdt_stop(wdt);		/* Turn the WDT off */
 	return 0;
 }
 
-static int mpcore_wdt_resume(struct platform_device *dev)
+static int mpcore_wdt_resume(struct platform_device *pdev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(dev);
+	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
 	/* re-activate timer */
 	if (test_bit(0, &wdt->timer_alive))
 		mpcore_wdt_start(wdt);
-- 
1.7.8.110.g4cb5d



From linus.walleij at stericsson.com  Mon Mar 12 04:25:50 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 12 Mar 2012 09:25:50 +0100
Subject: [PATCH] serial: PL011: clear pending interrupts
Message-ID: <1331540750-25697-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Chanho Min reported that when the boot loader transfers
control to the kernel, there may be pending interrupts
causing the UART to lock up in an eternal loop trying to
pick tokens from the FIFO (since the RX interrupt flag
indicates there are tokens) while in practice there are
no tokens - in fact there is only a pending IRQ flag.

This patch address the issue with a combination of a patch
from Russell King that clears and mask all interrupts at
probe() and clears any pending error and RX interrupts at
port startup time, and a patch from Jong-Sung Kim that
clears any RX interrupts (including timeouts) even if if
there are zero tokens in the FIFO.

This way these pending interrupts should be addressed in
two ways and solidify the driver in both probe() and
IRQ paths.

Cc: stable at kernel.org
Cc: Shreshtha Kumar Sahu <shreshthakumar.sahu at stericsson.com>
Reported-by: Chanho Min <chanho0207 at gmail.com>
Suggested-by: Russell King <linux at arm.linux.org.uk>
Suggested-by: Jong-Sung Kim <neidhard.kim at lge.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
OK Greg requested that we send out this combined approach, can
addressees (Chanho especially) please confirm that the patch
solves the problem? Tested on U300 and U8500.
---
 drivers/tty/serial/amba-pl011.c |   17 +++++++++++++----
 1 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 6800f5f..ff3fed0 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -224,6 +224,11 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap)
 		uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
 	}
 
+	/* RXIS but RXFE? Just clear the interrupt */
+	if(unlikely(fifotaken == 0))
+		writew(UART011_RTIS | UART011_RXIS,
+		       uap->port.membase + UART011_ICR);
+
 	return fifotaken;
 }
 
@@ -1381,6 +1386,10 @@ static int pl011_startup(struct uart_port *port)
 
 	uap->port.uartclk = clk_get_rate(uap->clk);
 
+	/* Clear pending error and receive interrupts */
+	writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
+	       UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
+
 	/*
 	 * Allocate the IRQ
 	 */
@@ -1417,10 +1426,6 @@ static int pl011_startup(struct uart_port *port)
 	cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
 	writew(cr, uap->port.membase + UART011_CR);
 
-	/* Clear pending error interrupts */
-	writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
-	       uap->port.membase + UART011_ICR);
-
 	/*
 	 * initialise the old status of the modem signals
 	 */
@@ -1927,6 +1932,10 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 		goto unmap;
 	}
 
+	/* Ensure interrupts from this UART are masked and cleared */
+	writew(0, uap->port.membase + UART011_IMSC);
+	writew(0xffff, uap->port.membase + UART011_ICR);
+
 	uap->vendor = vendor;
 	uap->lcrh_rx = vendor->lcrh_rx;
 	uap->lcrh_tx = vendor->lcrh_tx;
-- 
1.7.8



From nicolas.ferre at atmel.com  Mon Mar 12 12:05:32 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 12 Mar 2012 17:05:32 +0100
Subject: linux-next: manual merge of the cpuidle-cons tree with the arm-soc
 tree
In-Reply-To: <20120309183732.512d3676599da324f4747219@canb.auug.org.au>
References: <20120309183732.512d3676599da324f4747219@canb.auug.org.au>
Message-ID: <4F5E1ECC.1040605@atmel.com>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 03/09/2012 08:37 AM, Stephen Rothwell :
> Hi Rob,
> 
> Today's linux-next merge of the cpuidle-cons tree got a conflict
> in arch/arm/mach-at91/cpuidle.c between commit 00482a4078f4 ("ARM:
> at91: implement the standby function for pm/cpuidle") from the
> arm-soc tree and commit 7a1f6e72dce1 ("ARM: at91: Consolidate time
> keeping and irq enable") from the cpuidle-cons tree.
> 
> I fixed it up (I think - see below) and can carry the fix as
> necessary.

Yes: resolution correct. Please carry it.

Thanks to Rob and Daniel for their answers.

Best regards,
- -- 
Nicolas Ferre
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Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/

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From b39297 at freescale.com  Mon Mar 12 00:57:58 2012
From: b39297 at freescale.com (Wu Guoxing)
Date: Mon, 12 Mar 2012 12:57:58 +0800
Subject: [PATCH 1/2] ARM: mx35: 3ds: add mc9s08dz60 gpio definitions
Message-ID: <1331528279-2263-1-git-send-email-b39297@freescale.com>

add a new header file for mx35 3ds board
add the mc9s08dz60 gpio definitions

Signed-off-by: Wu Guoxing <b39297 at freescale.com>
---
 arch/arm/plat-mxc/include/mach/board_mx35_3ds.h |   26 +++++++++++++++++++++++
 1 files changed, 26 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/include/mach/board_mx35_3ds.h

diff --git a/arch/arm/plat-mxc/include/mach/board_mx35_3ds.h b/arch/arm/plat-mxc/include/mach/board_mx35_3ds.h
new file mode 100644
index 0000000..df0d5f7
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board_mx35_3ds.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Author: Wu Guoxing <b39297 at freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX35_3DS_H__
+#define __ASM_ARCH_MXC_BOARD_MX35_3DS_H__
+
+#define GPIO_MC9S08DZ60_GPS_ENABLE 0
+#define GPIO_MC9S08DZ60_HDD_ENABLE 4
+#define GPIO_MC9S08DZ60_WIFI_ENABLE 5
+#define GPIO_MC9S08DZ60_LCD_ENABLE 6
+#define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8
+
+#endif
-- 
1.7.1




From viresh.kumar at st.com  Mon Mar 12 00:22:12 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:12 +0530
Subject: [PATCH V2 17/22] watchdog/mpcore_wdt: use correct clk_rate to program
 timeout
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <4d69b903be5a62ee88aa1017d5dcbf94bbe0dc8e.1331524811.git.viresh.kumar@st.com>

Currently, mpcore wdt driver doesn't use exact clk_rate to program timeout in
hardware. This patch provides two ways of doing so:
	- either use clk_get_rate() if clk_get passes
	- use clk_rate passed via module param

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/include/asm/smp_twd.h |   10 ++++
 drivers/watchdog/mpcore_wdt.c  |   97 ++++++++++++++++++++++++++++++++-------
 2 files changed, 89 insertions(+), 18 deletions(-)

diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index a13b536..389ca02 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -13,11 +13,21 @@
 #define TWD_WDOG_RESETSTAT		0x30
 #define TWD_WDOG_DISABLE		0x34
 
+#define TWD_WDOG_LOAD_MIN		0x00000000
+#define TWD_WDOG_LOAD_MAX		0xFFFFFFFF
+
 #define TWD_TIMER_CONTROL_ENABLE	(1 << 0)
 #define TWD_TIMER_CONTROL_ONESHOT	(0 << 1)
 #define TWD_TIMER_CONTROL_PERIODIC	(1 << 1)
 #define TWD_TIMER_CONTROL_IT_ENABLE	(1 << 2)
 
+#define TWD_WDOG_CONTROL_ENABLE		(1 << 0)
+#define TWD_WDOG_CONTROL_IRQ_ENABLE	(1 << 2)
+#define TWD_WDOG_CONTROL_WDT_MODE	(1 << 3)
+#define TWD_WDOG_CONTROL_WDT_PRESCALE(x)	((x) << 8)
+#define TWD_WDOG_CONTROL_PRESCALE_MIN	0x00
+#define TWD_WDOG_CONTROL_PRESCALE_MAX	0xFF
+
 #define TWD_WDOG_RESETSTAT_MASK		0x1
 
 struct clock_event_device;
diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 23c324c..de46b5d 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -39,7 +39,10 @@ struct mpcore_wdt {
 	void __iomem	*base;
 	spinlock_t	lock;
 	struct clk	*clk;
+	unsigned long	clk_rate;	/* In Hz */
 	int		irq;
+	unsigned int	prescale;
+	unsigned int	load_val;
 	unsigned int	perturb;
 };
 
@@ -58,6 +61,11 @@ MODULE_PARM_DESC(nowayout,
 	"Watchdog cannot be stopped once started (default="
 				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 
+static int clk_rate;
+module_param(clk_rate, int, 0);
+MODULE_PARM_DESC(clk_rate,
+	"Watchdog clock rate in Hz, required if clk_get() fails");
+
 #define ONLY_TESTING	0
 static int mpcore_noboot = ONLY_TESTING;
 module_param(mpcore_noboot, int, 0);
@@ -93,17 +101,10 @@ static irqreturn_t mpcore_wdt_fire(int irq, void *arg)
 static int mpcore_wdt_ping(struct watchdog_device *wdd)
 {
 	struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd);
-	unsigned long count;
 
 	spin_lock(&wdt->lock);
-	/* Assume prescale is set to 256 */
-	count = readl_relaxed(wdt->base + TWD_WDOG_COUNTER);
-	count = (0xFFFFFFFFU - count) * (HZ / 5);
-	count = (count / 256) * mpcore_margin;
-
-	/* Reload the counter */
-	writel_relaxed(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD);
-	wdt->perturb = wdt->perturb ? 0 : 1;
+	writel_relaxed(wdt->load_val + wdt->perturb, wdt->base + TWD_WDOG_LOAD);
+	wdt->perturb = !wdt->perturb;
 	spin_unlock(&wdt->lock);
 
 	return 0;
@@ -135,6 +136,7 @@ static int mpcore_wdt_stop(struct watchdog_device *wdd)
 static int mpcore_wdt_start(struct watchdog_device *wdd)
 {
 	struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd);
+	u32 val, mode;
 	int ret;
 
 	dev_info(wdt->dev, "enabling watchdog.\n");
@@ -157,20 +159,70 @@ static int mpcore_wdt_start(struct watchdog_device *wdd)
 	/* This loads the count register but does NOT start the count yet */
 	mpcore_wdt_ping(wdd);
 
-	if (mpcore_noboot) {
-		/* Enable watchdog - prescale=256, watchdog mode=0, enable=1 */
-		writel_relaxed(0x0000FF01, wdt->base + TWD_WDOG_CONTROL);
-	} else {
-		/* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */
-		writel_relaxed(0x0000FF09, wdt->base + TWD_WDOG_CONTROL);
-	}
+	if (mpcore_noboot)
+		mode = 0;
+	else
+		mode = TWD_WDOG_CONTROL_WDT_MODE;
+
+	spin_lock(&wdt->lock);
+
+	val = TWD_WDOG_CONTROL_WDT_PRESCALE(wdt->prescale) |
+		TWD_WDOG_CONTROL_ENABLE | mode;
+	writel_relaxed(val, wdt->base + TWD_WDOG_CONTROL);
+
+	spin_unlock(&wdt->lock);
 
 	return 0;
 }
 
-static int mpcore_wdt_set_heartbeat(struct watchdog_device *wdd, unsigned int t)
+/* binary search */
+static inline void bsearch(u32 *var, u32 var_start, u32 var_end,
+		const u64 param, const u32 timeout, u32 rate)
+{
+	u64 tmp = 0;
+
+	/* get the lowest var value that can satisfy our requirement */
+	while (var_start < var_end) {
+		tmp = var_start;
+		tmp += var_end;
+		tmp = div_u64(tmp, 2);
+		if (timeout > div_u64((param + 1) * (tmp + 1), rate)) {
+			if (var_start == tmp)
+				break;
+			else
+				var_start = tmp;
+		} else {
+			if (var_end == tmp)
+				break;
+			else
+				var_end = tmp;
+		}
+	}
+	*var = tmp;
+}
+
+static int
+mpcore_wdt_set_heartbeat(struct watchdog_device *wdd, unsigned int timeout)
 {
-	mpcore_margin = t;
+	struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd);
+	unsigned int psc, rate = wdt->clk_rate;
+	u64 load = 0;
+
+	/* get appropriate value of psc and load */
+	bsearch(&psc, TWD_WDOG_CONTROL_PRESCALE_MIN,
+			TWD_WDOG_CONTROL_PRESCALE_MAX, TWD_WDOG_LOAD_MAX,
+			timeout, rate);
+	bsearch((u32 *)&load, TWD_WDOG_LOAD_MIN, TWD_WDOG_LOAD_MAX, psc,
+			timeout, rate);
+
+	spin_lock(&wdt->lock);
+	wdt->prescale = psc;
+	wdt->load_val = load;
+
+	/* roundup timeout to closest positive integer value */
+	mpcore_margin = div_u64((psc + 1) * (load + 1) + (rate / 2), rate);
+	spin_unlock(&wdt->lock);
+
 	return 0;
 }
 
@@ -246,7 +298,10 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 	wdt->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(wdt->clk)) {
 		dev_warn(&pdev->dev, "Clock not found\n");
+		wdt->clk_rate = clk_rate;
 	} else {
+		wdt->clk_rate = clk_get_rate(wdt->clk);
+
 		ret = clk_prepare(wdt->clk);
 		if (ret) {
 			dev_err(wdt->dev, "clock prepare fail");
@@ -266,6 +321,12 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 
 	mpcore_wdt_stop(&wdt->wdd);
 
+	if (!wdt->clk_rate) {
+		dev_err(&pdev->dev, "Clock rate can't be zero\n");
+		ret = -EINVAL;
+		goto err_put_clk;
+	}
+
 	ret = watchdog_register_device(&wdt->wdd);
 	if (ret) {
 		dev_err(wdt->dev, "watchdog_register_device() failed: %d\n",
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:22:06 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:06 +0530
Subject: [PATCH V2 11/22] watchdog/mpcore_wdt: convert to use
 module_platform_driver()
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <32e80a12b24d0e4ecff0d32396e85c782abbe9e7.1331524811.git.viresh.kumar@st.com>

This patch converts the mpcore_wdt driver to use the module_platform_driver()
macro which makes the code smaller and a bit simpler.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   13 +------------
 1 files changed, 1 insertions(+), 12 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index c820e4f..6902580 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -293,18 +293,7 @@ static struct platform_driver mpcore_wdt_driver = {
 	},
 };
 
-static int __init mpcore_wdt_init(void)
-{
-	return platform_driver_register(&mpcore_wdt_driver);
-}
-
-static void __exit mpcore_wdt_exit(void)
-{
-	platform_driver_unregister(&mpcore_wdt_driver);
-}
-
-module_init(mpcore_wdt_init);
-module_exit(mpcore_wdt_exit);
+module_platform_driver(mpcore_wdt_driver);
 
 MODULE_AUTHOR("ARM Limited");
 MODULE_DESCRIPTION("MPcore Watchdog Device Driver");
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:22:03 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:03 +0530
Subject: [PATCH V2 08/22] watchdog/mpcore_wdt: Arrange #includes in
 alphabetical order
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <352721112bf538b960d5b642570d64c286760c49.1331524811.git.viresh.kumar@st.com>

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 7c9f78c..1c37109 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -17,16 +17,16 @@
  *
  * (c) Copyright 1995    Alan Cox <alan at lxorguk.ukuu.org.uk>
  */
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/types.h>
-#include <linux/watchdog.h>
-#include <linux/reboot.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
 #include <linux/platform_device.h>
+#include <linux/reboot.h>
 #include <linux/slab.h>
-#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/watchdog.h>
 
 #include <asm/smp_twd.h>
 
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:22:01 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:01 +0530
Subject: [PATCH V2 06/22] watchdog/mpcore_wdt: convert to watchdog core
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <45602d964bcc47908f5c02cf09511847a4663e12.1331524811.git.viresh.kumar@st.com>

This patch converts existing mpcore watchdog driver to use already in place
common infrastructure present in watchdog core. With this lot of code goes away.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/Kconfig      |    1 +
 drivers/watchdog/mpcore_wdt.c |  281 ++++++++++-------------------------------
 2 files changed, 71 insertions(+), 211 deletions(-)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index ee27f57..f66617a 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -208,6 +208,7 @@ config DW_WATCHDOG
 config MPCORE_WATCHDOG
 	tristate "MPcore watchdog"
 	depends on HAVE_ARM_TWD
+	select WATCHDOG_CORE
 	help
 	  Watchdog timer embedded into the MPcore system.
 
diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 1d2f1a1..953044a 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -22,31 +22,27 @@
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/types.h>
-#include <linux/miscdevice.h>
 #include <linux/watchdog.h>
-#include <linux/fs.h>
 #include <linux/reboot.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <linux/uaccess.h>
 #include <linux/slab.h>
 #include <linux/io.h>
 
 #include <asm/smp_twd.h>
 
 struct mpcore_wdt {
-	unsigned long	timer_alive;
+	struct watchdog_device wdd;
 	struct device	*dev;
 	void __iomem	*base;
+	spinlock_t	lock;
 	int		irq;
 	unsigned int	perturb;
-	char		expect_close;
 };
 
-static struct platform_device *mpcore_wdt_pdev;
-static DEFINE_SPINLOCK(wdt_lock);
-
+#define MIN_TIME	0x0001
+#define MAX_TIME	0xFFFF
 #define TIMER_MARGIN	60
 static int mpcore_margin = TIMER_MARGIN;
 module_param(mpcore_margin, int, 0);
@@ -87,17 +83,18 @@ static irqreturn_t mpcore_wdt_fire(int irq, void *arg)
 }
 
 /*
- *	mpcore_wdt_keepalive - reload the timer
+ *	mpcore_wdt_ping - reload the timer
  *
  *	Note that the spec says a DIFFERENT value must be written to the reload
  *	register each time.  The "perturb" variable deals with this by adding 1
  *	to the count every other time the function is called.
  */
-static void mpcore_wdt_keepalive(struct mpcore_wdt *wdt)
+static int mpcore_wdt_ping(struct watchdog_device *wdd)
 {
+	struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd);
 	unsigned long count;
 
-	spin_lock(&wdt_lock);
+	spin_lock(&wdt->lock);
 	/* Assume prescale is set to 256 */
 	count =  __raw_readl(wdt->base + TWD_WDOG_COUNTER);
 	count = (0xFFFFFFFFU - count) * (HZ / 5);
@@ -106,24 +103,32 @@ static void mpcore_wdt_keepalive(struct mpcore_wdt *wdt)
 	/* Reload the counter */
 	writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD);
 	wdt->perturb = wdt->perturb ? 0 : 1;
-	spin_unlock(&wdt_lock);
+	spin_unlock(&wdt->lock);
+
+	return 0;
 }
 
-static void mpcore_wdt_stop(struct mpcore_wdt *wdt)
+static int mpcore_wdt_stop(struct watchdog_device *wdd)
 {
-	spin_lock(&wdt_lock);
+	struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd);
+
+	spin_lock(&wdt->lock);
 	writel(0x12345678, wdt->base + TWD_WDOG_DISABLE);
 	writel(0x87654321, wdt->base + TWD_WDOG_DISABLE);
 	writel(0x0, wdt->base + TWD_WDOG_CONTROL);
-	spin_unlock(&wdt_lock);
+	spin_unlock(&wdt->lock);
+
+	return 0;
 }
 
-static void mpcore_wdt_start(struct mpcore_wdt *wdt)
+static int mpcore_wdt_start(struct watchdog_device *wdd)
 {
+	struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd);
+
 	dev_printk(KERN_INFO, wdt->dev, "enabling watchdog.\n");
 
 	/* This loads the count register but does NOT start the count yet */
-	mpcore_wdt_keepalive(wdt);
+	mpcore_wdt_ping(wdd);
 
 	if (mpcore_noboot) {
 		/* Enable watchdog - prescale=256, watchdog mode=0, enable=1 */
@@ -132,167 +137,30 @@ static void mpcore_wdt_start(struct mpcore_wdt *wdt)
 		/* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */
 		writel(0x0000FF09, wdt->base + TWD_WDOG_CONTROL);
 	}
-}
-
-static int mpcore_wdt_set_heartbeat(int t)
-{
-	if (t < 0x0001 || t > 0xFFFF)
-		return -EINVAL;
 
-	mpcore_margin = t;
 	return 0;
 }
 
-/*
- *	/dev/watchdog handling
- */
-static int mpcore_wdt_open(struct inode *inode, struct file *file)
-{
-	struct mpcore_wdt *wdt = platform_get_drvdata(mpcore_wdt_pdev);
-
-	if (test_and_set_bit(0, &wdt->timer_alive))
-		return -EBUSY;
-
-	if (nowayout)
-		__module_get(THIS_MODULE);
-
-	file->private_data = wdt;
-
-	/*
-	 *	Activate timer
-	 */
-	mpcore_wdt_start(wdt);
-
-	return nonseekable_open(inode, file);
-}
-
-static int mpcore_wdt_release(struct inode *inode, struct file *file)
+static int mpcore_wdt_set_heartbeat(struct watchdog_device *wdd, unsigned int t)
 {
-	struct mpcore_wdt *wdt = file->private_data;
-
-	/*
-	 *	Shut off the timer.
-	 *	Lock it in if it's a module and we set nowayout
-	 */
-	if (wdt->expect_close == 42)
-		mpcore_wdt_stop(wdt);
-	else {
-		dev_printk(KERN_CRIT, wdt->dev,
-				"unexpected close, not stopping watchdog!\n");
-		mpcore_wdt_keepalive(wdt);
-	}
-	clear_bit(0, &wdt->timer_alive);
-	wdt->expect_close = 0;
+	mpcore_margin = t;
 	return 0;
 }
 
-static ssize_t mpcore_wdt_write(struct file *file, const char *data,
-						size_t len, loff_t *ppos)
-{
-	struct mpcore_wdt *wdt = file->private_data;
-
-	/*
-	 *	Refresh the timer.
-	 */
-	if (len) {
-		if (!nowayout) {
-			size_t i;
-
-			/* In case it was set long ago */
-			wdt->expect_close = 0;
-
-			for (i = 0; i != len; i++) {
-				char c;
-
-				if (get_user(c, data + i))
-					return -EFAULT;
-				if (c == 'V')
-					wdt->expect_close = 42;
-			}
-		}
-		mpcore_wdt_keepalive(wdt);
-	}
-	return len;
-}
-
-static const struct watchdog_info ident = {
+static const struct watchdog_info mpcore_wdt_info = {
 	.options		= WDIOF_SETTIMEOUT |
 				  WDIOF_KEEPALIVEPING |
 				  WDIOF_MAGICCLOSE,
 	.identity		= "MPcore Watchdog",
 };
 
-static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd,
-							unsigned long arg)
-{
-	struct mpcore_wdt *wdt = file->private_data;
-	int ret;
-	union {
-		struct watchdog_info ident;
-		int i;
-	} uarg;
-
-	if (_IOC_DIR(cmd) && _IOC_SIZE(cmd) > sizeof(uarg))
-		return -ENOTTY;
-
-	if (_IOC_DIR(cmd) & _IOC_WRITE) {
-		ret = copy_from_user(&uarg, (void __user *)arg, _IOC_SIZE(cmd));
-		if (ret)
-			return -EFAULT;
-	}
-
-	switch (cmd) {
-	case WDIOC_GETSUPPORT:
-		uarg.ident = ident;
-		ret = 0;
-		break;
-
-	case WDIOC_GETSTATUS:
-	case WDIOC_GETBOOTSTATUS:
-		uarg.i = 0;
-		ret = 0;
-		break;
-
-	case WDIOC_SETOPTIONS:
-		ret = -EINVAL;
-		if (uarg.i & WDIOS_DISABLECARD) {
-			mpcore_wdt_stop(wdt);
-			ret = 0;
-		}
-		if (uarg.i & WDIOS_ENABLECARD) {
-			mpcore_wdt_start(wdt);
-			ret = 0;
-		}
-		break;
-
-	case WDIOC_KEEPALIVE:
-		mpcore_wdt_keepalive(wdt);
-		ret = 0;
-		break;
-
-	case WDIOC_SETTIMEOUT:
-		ret = mpcore_wdt_set_heartbeat(uarg.i);
-		if (ret)
-			break;
-
-		mpcore_wdt_keepalive(wdt);
-		/* Fall */
-	case WDIOC_GETTIMEOUT:
-		uarg.i = mpcore_margin;
-		ret = 0;
-		break;
-
-	default:
-		return -ENOTTY;
-	}
-
-	if (ret == 0 && _IOC_DIR(cmd) & _IOC_READ) {
-		ret = copy_to_user((void __user *)arg, &uarg, _IOC_SIZE(cmd));
-		if (ret)
-			ret = -EFAULT;
-	}
-	return ret;
-}
+static const struct watchdog_ops mpcore_wdt_ops = {
+	.owner		= THIS_MODULE,
+	.start		= mpcore_wdt_start,
+	.stop		= mpcore_wdt_stop,
+	.ping		= mpcore_wdt_ping,
+	.set_timeout	= mpcore_wdt_set_heartbeat,
+};
 
 /*
  *	System shutdown handler.  Turn off the watchdog if we're
@@ -303,37 +171,15 @@ static void mpcore_wdt_shutdown(struct platform_device *pdev)
 	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
 
 	if (system_state == SYSTEM_RESTART || system_state == SYSTEM_HALT)
-		mpcore_wdt_stop(wdt);
+		mpcore_wdt_stop(&wdt->wdd);
 }
 
-/*
- *	Kernel Interfaces
- */
-static const struct file_operations mpcore_wdt_fops = {
-	.owner		= THIS_MODULE,
-	.llseek		= no_llseek,
-	.write		= mpcore_wdt_write,
-	.unlocked_ioctl	= mpcore_wdt_ioctl,
-	.open		= mpcore_wdt_open,
-	.release	= mpcore_wdt_release,
-};
-
-static struct miscdevice mpcore_wdt_miscdev = {
-	.minor		= WATCHDOG_MINOR,
-	.name		= "watchdog",
-	.fops		= &mpcore_wdt_fops,
-};
-
 static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 {
 	struct mpcore_wdt *wdt;
 	struct resource *res;
 	int ret;
 
-	/* We only accept one device, and it must have an id of -1 */
-	if (pdev->id != -1)
-		return -ENODEV;
-
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res)
 		return -ENODEV;
@@ -359,30 +205,41 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 	if (!wdt->base)
 		return -ENOMEM;
 
-	mpcore_wdt_miscdev.parent = &pdev->dev;
-	ret = misc_register(&mpcore_wdt_miscdev);
-	if (ret) {
-		dev_printk(KERN_ERR, wdt->dev,
-			"cannot register miscdev on minor=%d (err=%d)\n",
-							WATCHDOG_MINOR, ret);
-		return ret;
-	}
+	wdt->wdd.info = &mpcore_wdt_info;
+	wdt->wdd.ops = &mpcore_wdt_ops;
+	wdt->wdd.min_timeout = MIN_TIME;
+	wdt->wdd.max_timeout = MAX_TIME;
+	spin_lock_init(&wdt->lock);
 
-	mpcore_wdt_stop(wdt);
+	watchdog_set_nowayout(&wdt->wdd, nowayout);
 	platform_set_drvdata(pdev, wdt);
-	mpcore_wdt_pdev = pdev;
+	watchdog_set_drvdata(&wdt->wdd, wdt);
+
+	mpcore_wdt_stop(&wdt->wdd);
+
+	ret = watchdog_register_device(&wdt->wdd);
+	if (ret) {
+		dev_err(wdt->dev, "watchdog_register_device() failed: %d\n",
+				ret);
+		goto err_register;
+	}
 
 	return 0;
-}
 
-static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
-{
+err_register:
 	platform_set_drvdata(pdev, NULL);
+	watchdog_set_drvdata(&wdt->wdd, NULL);
 
-	misc_deregister(&mpcore_wdt_miscdev);
+	return ret;
+}
 
-	mpcore_wdt_pdev = NULL;
+static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
+{
+	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
 
+	watchdog_unregister_device(&wdt->wdd);
+	platform_set_drvdata(pdev, NULL);
+	watchdog_set_drvdata(&wdt->wdd, NULL);
 	return 0;
 }
 
@@ -390,16 +247,18 @@ static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
 static int mpcore_wdt_suspend(struct platform_device *pdev, pm_message_t msg)
 {
 	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
-	mpcore_wdt_stop(wdt);		/* Turn the WDT off */
+	mpcore_wdt_stop(&wdt->wdd);	/* Turn the WDT off */
+
 	return 0;
 }
 
 static int mpcore_wdt_resume(struct platform_device *pdev)
 {
 	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
-	/* re-activate timer */
-	if (test_bit(0, &wdt->timer_alive))
-		mpcore_wdt_start(wdt);
+
+	if (is_wdd_active(&wdt->wdd))
+		mpcore_wdt_start(&wdt->wdd);
+
 	return 0;
 }
 #else
@@ -428,15 +287,16 @@ static char banner[] __initdata = KERN_INFO "MPcore Watchdog Timer: 0.1. "
 static int __init mpcore_wdt_init(void)
 {
 	/*
-	 * Check that the margin value is within it's range;
+	 * Check that the mpcore_margin value is within it's range;
 	 * if not reset to the default
 	 */
-	if (mpcore_wdt_set_heartbeat(mpcore_margin)) {
-		mpcore_wdt_set_heartbeat(TIMER_MARGIN);
+	if (mpcore_margin < MIN_TIME || mpcore_margin > MAX_TIME) {
+		mpcore_margin = TIMER_MARGIN;
 		printk(KERN_INFO "mpcore_margin value must be 0 < mpcore_margin < 65536, using %d\n",
-			TIMER_MARGIN);
+				TIMER_MARGIN);
 	}
 
+	mpcore_wdt_set_heartbeat(NULL, mpcore_margin);
 	printk(banner, mpcore_noboot, mpcore_margin, nowayout);
 
 	return platform_driver_register(&mpcore_wdt_driver);
@@ -453,4 +313,3 @@ module_exit(mpcore_wdt_exit);
 MODULE_AUTHOR("ARM Limited");
 MODULE_DESCRIPTION("MPcore Watchdog Device Driver");
 MODULE_LICENSE("GPL");
-MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:21:57 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:51:57 +0530
Subject: [PATCH V2 02/22] watchdog: Add support for WDIOC_GETTIMELEFT IOCTL in
 watchdog core
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <3743d1bdbd827e09add04206c0413c5d7f1c7b1d.1331524811.git.viresh.kumar@st.com>

This patch adds support for WDIOC_GETTIMELEFT IOCTL in watchdog core. So, there
is another function pointer added to struct watchdog_ops, which can be passed by
drivers to support this IOCTL.

Related documentation is updated too.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 .../watchdog/convert_drivers_to_kernel_api.txt     |    4 ++++
 Documentation/watchdog/watchdog-kernel-api.txt     |    2 ++
 drivers/watchdog/watchdog_dev.c                    |    5 +++++
 include/linux/watchdog.h                           |    2 ++
 4 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/Documentation/watchdog/convert_drivers_to_kernel_api.txt b/Documentation/watchdog/convert_drivers_to_kernel_api.txt
index be8119b..271b885 100644
--- a/Documentation/watchdog/convert_drivers_to_kernel_api.txt
+++ b/Documentation/watchdog/convert_drivers_to_kernel_api.txt
@@ -59,6 +59,10 @@ Here is a overview of the functions and probably needed actions:
 	WDIOC_GETTIMEOUT:
 		No preparations needed
 
+	WDIOC_GETTIMELEFT:
+		It needs get_timeleft() callback to be defined. Otherwise it
+		will return EOPNOTSUPP
+
   Other IOCTLs can be served using the ioctl-callback. Note that this is mainly
   intended for porting old drivers; new drivers should not invent private IOCTLs.
   Private IOCTLs are processed first. When the callback returns with
diff --git a/Documentation/watchdog/watchdog-kernel-api.txt b/Documentation/watchdog/watchdog-kernel-api.txt
index 9e16246..24d9a35 100644
--- a/Documentation/watchdog/watchdog-kernel-api.txt
+++ b/Documentation/watchdog/watchdog-kernel-api.txt
@@ -77,6 +77,7 @@ struct watchdog_ops {
 	int (*ping)(struct watchdog_device *);
 	unsigned int (*status)(struct watchdog_device *);
 	int (*set_timeout)(struct watchdog_device *, unsigned int);
+	unsigned int (*get_timeleft)(struct watchdog_device *);
 	long (*ioctl)(struct watchdog_device *, unsigned int, unsigned long);
 };
 
@@ -122,6 +123,7 @@ they are supported. These optional routines/operations are:
   to re-program the watchdog timer device.
   (Note: the WDIOF_SETTIMEOUT needs to be set in the options field of the
   watchdog's info structure).
+* get_timeleft: this routines returns the time left for reset.
 * ioctl: if this routine is present then it will be called first before we do
   our own internal ioctl call handling. This routine should return -ENOIOCTLCMD
   if a command is not supported. The parameters that are passed to the ioctl
diff --git a/drivers/watchdog/watchdog_dev.c b/drivers/watchdog/watchdog_dev.c
index 9668253..6206e1b 100644
--- a/drivers/watchdog/watchdog_dev.c
+++ b/drivers/watchdog/watchdog_dev.c
@@ -237,6 +237,11 @@ static long watchdog_ioctl(struct file *file, unsigned int cmd,
 		if (wdd->timeout == 0)
 			return -EOPNOTSUPP;
 		return put_user(wdd->timeout, p);
+	case WDIOC_GETTIMELEFT:
+		if (!wdd->ops->get_timeleft)
+			return -EOPNOTSUPP;
+
+		return put_user(wdd->ops->get_timeleft(wdd), p);
 	default:
 		return -ENOTTY;
 	}
diff --git a/include/linux/watchdog.h b/include/linux/watchdog.h
index 4fc57b2..6b4e918 100644
--- a/include/linux/watchdog.h
+++ b/include/linux/watchdog.h
@@ -66,6 +66,7 @@ struct watchdog_device;
  * @ping:	The routine that sends a keepalive ping to the watchdog device.
  * @status:	The routine that shows the status of the watchdog device.
  * @set_timeout:The routine for setting the watchdog devices timeout value.
+ * @get_timeleft:The routine for getting the watchdog device's timeleft value.
  * @ioctl:	The routines that handles extra ioctl calls.
  *
  * The watchdog_ops structure contains a list of low-level operations
@@ -82,6 +83,7 @@ struct watchdog_ops {
 	int (*ping)(struct watchdog_device *);
 	unsigned int (*status)(struct watchdog_device *);
 	int (*set_timeout)(struct watchdog_device *, unsigned int);
+	unsigned int (*get_timeleft)(struct watchdog_device *);
 	long (*ioctl)(struct watchdog_device *, unsigned int, unsigned long);
 };
 
-- 
1.7.8.110.g4cb5d



From andrew at lunn.ch  Sat Mar 10 12:50:16 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sat, 10 Mar 2012 18:50:16 +0100
Subject: [PATCH v6 1/3] Documentation: common clk API
In-Reply-To: <1331366064-1273-2-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-2-git-send-email-mturquette@linaro.org>
Message-ID: <20120310175016.GJ16608@lunn.ch>

On Fri, Mar 09, 2012 at 11:54:22PM -0800, Mike Turquette wrote:
> Provide documentation for the common clk structures and APIs.  This code
> can be found in drivers/clk/ and include/linux/clk*.h.

Hi Mike

Please feel free to add:

Reviewed-by: Andrew Lunn <andrew at lunn.ch>

     Andrew


From jason at lakedaemon.net  Sun Mar 11 23:17:51 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 11 Mar 2012 23:17:51 -0400
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <201203111746.09757.arnd@arndb.de>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <1331476406-9844-2-git-send-email-jm@lentin.co.uk>
 <201203111746.09757.arnd@arndb.de>
Message-ID: <20120312031751.GY5050@titan.lakedaemon.net>

On Sun, Mar 11, 2012 at 05:46:09PM +0000, Arnd Bergmann wrote:
> On Sunday 11 March 2012, Jamie Lentin wrote:
> > Add support for the DNS-320 and DNS-325. Describe as much as currently possible
> > in the devicetree files, leave everything else in board-dt.c to be patched
> > later.
> > 
> > Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> 
> Great work!
> 
> > +
> > +/ {
> > +	model = "D-Link DNS-320 NAS (Rev A1)";
> > +	compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
> > +
> > +	memory {
> > +		device_type = "memory";
> > +		reg = <0x00000000 0x8000000>;
> > +	};
> > +
> > +	chosen {
> > +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> > +	};
> > +
> > +	wdt at fed20300 {
> > +		compatible = "mrvl,orion-wdt";
> > +		reg = <0xfed20300 0x28>;
> > +		clock-frequency = <166666667>;
> > +	};
> > +
> > +	serial at f1012000 {
> > +		compatible = "ns16550a";
> > +		reg = <0xf1012000 0xff>;
> > +		reg-shift = <2>;
> > +		interrupts = <33>;
> > +		clock-frequency = <166666667>;
> > +	};
> > +
> > +	serial at f1012100 {
> > +		compatible = "ns16550a";
> > +		reg = <0xf1012100 0xff>;

oops, I missed this earlier (and, I just corrected in my own code).
Arnd says Linux uses inclusive sizes, so the above should be 0x100.
Please correct for all register sizes.

> > +		reg-shift = <2>;
> > +		interrupts = <34>;
> > +		clock-frequency = <166666667>;
> > +	};
> 
> I think the generic kirkwood device nodes should all be part of
> the kirkwood.dtsi file, except for any properties you want to
> override.
> 
> You can add a status="disabled" property in device nodes
> that may not be connected in individual boards, and then
> just override it by listing status="enabled" in the board.dts
> file, without having to duplicate all the other properties.

The clock-frequency property complicates that, since it is different
from board to board.  of_serial appears to print an error message if
clock-frequency isn't set, so would this work:

### blah.dtsi ###
...
	serial at f1012100 {
		compatible = "ns16550a";
		reg = <0xf1012100 0xff>;
		reg-shift = <2>;
		interrupts = <34>;
		/* no clock set */
		status = "disabled";
	}
#################

then,

### blah-foo.dts ###
...
	serial at f1012100 {
		status = "ok";
		clock-frequency = <166666667>;
	}
####################

> I would also suggest to change the kirkwood.dtsi layout to
> put all the on-chip peripherals from the 0xf1 section into
> one bus in the device tree, like
> 
> 	ocp at f1000000 {
> 		compatible = "simple-bus";
> 		ranges = <0xf1000000 0xf1000000 0x1000000>;
> 		#address-cells = 1;
> 		#size-cells = 1;
> 
> 		serial at f1012000 {
> 			...
> 		};
> 
> 		...
> 	};
> 
> Or even use the ranges property to remap everything into
> a simpler address range:
> 
> 	ocp at f1000000 {
> 		compatible = "simple-bus";
> 		ranges = <0 0xf1000000 0x1000000>;
> 		#address-cells = 1;
> 		#size-cells = 1;
> 
> 		serial at 12000 {
> 			reg = <0x12000 0x100>;
> 			...
> 		};
> 
> 		...
> 	};

Okay, that's pretty slick.  The wdt and intc are at 0xfed00000, is that
another ocp bus?  Or, am I missing something?

thx,

Jason.


From jason at lakedaemon.net  Sun Mar 11 23:02:32 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 11 Mar 2012 23:02:32 -0400
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <1331476406-9844-2-git-send-email-jm@lentin.co.uk>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <1331476406-9844-2-git-send-email-jm@lentin.co.uk>
Message-ID: <20120312030232.GX5050@titan.lakedaemon.net>

On Sun, Mar 11, 2012 at 02:33:25PM +0000, Jamie Lentin wrote:
> Add support for the DNS-320 and DNS-325. Describe as much as currently possible
> in the devicetree files, leave everything else in board-dt.c to be patched
> later.
> 
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>

Great work!  comments, below.
> ---
>  arch/arm/boot/dts/kirkwood-dns320.dts |   54 ++++++
>  arch/arm/boot/dts/kirkwood-dns325.dts |   40 +++++
>  arch/arm/mach-kirkwood/Kconfig        |   18 ++
>  arch/arm/mach-kirkwood/Makefile.boot  |    2 +
>  arch/arm/mach-kirkwood/board-dt.c     |  294 +++++++++++++++++++++++++++++++++
>  5 files changed, 408 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/kirkwood-dns320.dts
>  create mode 100644 arch/arm/boot/dts/kirkwood-dns325.dts
> 
> diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
> new file mode 100644
> index 0000000..c039041
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-dns320.dts
> @@ -0,0 +1,54 @@
> +/dts-v1/;
> +
> +/include/ "kirkwood.dtsi"
> +
> +/ {
> +	model = "D-Link DNS-320 NAS (Rev A1)";
> +	compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";

s/marvell/mrvl/g for compatible properties.

> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x8000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +	};
> +
> +	wdt at fed20300 {
> +		compatible = "mrvl,orion-wdt";
> +		reg = <0xfed20300 0x28>;
> +		clock-frequency = <166666667>;
> +	};

This hasn't made it into my stable branch yet, waiting on common clock
to land (may be 3.5).  Please use kirkwood_wdt_init() in the mean time.

> +	serial at f1012000 {
> +		compatible = "ns16550a";
> +		reg = <0xf1012000 0xff>;
> +		reg-shift = <2>;
> +		interrupts = <33>;
> +		clock-frequency = <166666667>;
> +	};
> +
> +	serial at f1012100 {
> +		compatible = "ns16550a";
> +		reg = <0xf1012100 0xff>;
> +		reg-shift = <2>;
> +		interrupts = <34>;
> +		clock-frequency = <166666667>;
> +	};
> +
> +	sata at f1080000 {
> +		compatible = "mrvl,orion-sata";
> +		reg = <0xf1080000 0x5000>;
> +		interrupts = <21>;
> +		nr-ports = <2>;
> +	};
> +
> +	ehci at f1050000 {
> +		compatible = "mrvl,orion-ehci";
> +		reg = <0xf1050000 0x1000>;
> +		interrupts = <19>;
> +		dma-mask = <0xffffffff>;
> +		phy-version = "";
> +	};

sata and ehci both require working dma and interrupt controller.  I
should have the interrupt controller done soon.  mv_cesa will then work.
dma will be after that.

Basically, anything in mach-kirkwood/common.c that passes kirkwood_tclk
is on hold for devicetree.

> +};
> diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
> new file mode 100644
> index 0000000..a7c2c26
> --- /dev/null
> +++ b/arch/arm/boot/dts/kirkwood-dns325.dts
> @@ -0,0 +1,40 @@
> +/dts-v1/;
> +
> +/include/ "kirkwood.dtsi"
> +
> +/ {
> +	model = "D-Link DNS-325 NAS (Rev A1)";
> +	compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";

same as above, mrvl.

> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x10000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +	};

make sure to test serial with earlyprintk disabled.  That bit me once.

> +
> +	serial at f1012000 {
> +		compatible = "ns16550a";
> +		reg = <0xf1012000 0xff>;
> +		reg-shift = <2>;
> +		interrupts = <33>;
> +		clock-frequency = <200000000>;
> +	};
> +
> +	sata at f1080000 {
> +		compatible = "mrvl,orion-sata";
> +		reg = <0xf1080000 0x5000>;
> +		interrupts = <21>;
> +		nr-ports = <2>;
> +	};
> +
> +	ehci at f1050000 {
> +		compatible = "mrvl,orion-ehci";
> +		reg = <0xf1050000 0x1000>;
> +		interrupts = <19>;
> +		dma-mask = <0xffffffff>;
> +		phy-version = "";
> +	};
> +};
> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
> index 90ceab7..6c76e18 100644
> --- a/arch/arm/mach-kirkwood/Kconfig
> +++ b/arch/arm/mach-kirkwood/Kconfig
> @@ -58,6 +58,24 @@ config MACH_DREAMPLUG_DT
>  	  Say 'Y' here if you want your kernel to support the
>  	  Marvell DreamPlug (Flattened Device Tree).
>  
> +config MACH_DNS320_DT
> +	bool "D-Link DNS-320 (Flattened Device Tree)"
> +	select ARCH_KIRKWOOD_DT
> +	select CONFIG_MTD_OF_PARTS
> +	select CONFIG_SERIAL_OF_PLATFORM
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  D-Link DNS-320 (Flattened Device Tree).
> +
> +config MACH_DNS325_DT
> +	bool "D-Link DNS-325 (Flattened Device Tree)"
> +	select ARCH_KIRKWOOD_DT
> +	select CONFIG_MTD_OF_PARTS
> +	select CONFIG_SERIAL_OF_PLATFORM
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  D-Link DNS-325 (Flattened Device Tree).
> +
>  config MACH_TS219
>  	bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
>  	help
> diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
> index 16f9385..9c5e45f 100644
> --- a/arch/arm/mach-kirkwood/Makefile.boot
> +++ b/arch/arm/mach-kirkwood/Makefile.boot
> @@ -3,3 +3,5 @@ params_phys-y	:= 0x00000100
>  initrd_phys-y	:= 0x00800000
>  
>  dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
> +dtb-$(CONFIG_MACH_DNS320_DT) += kirkwood-dns320.dtb
> +dtb-$(CONFIG_MACH_DNS325_DT) += kirkwood-dns325.dtb
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index 12dec38..0885713 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -15,6 +15,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/irqdomain.h>
>  #include <linux/mtd/partitions.h>
> +#include <linux/i2c.h>
>  #include <linux/ata_platform.h>
>  #include <linux/mv643xx_eth.h>
>  #include <linux/of.h>
> @@ -23,6 +24,9 @@
>  #include <linux/of_irq.h>
>  #include <linux/of_platform.h>
>  #include <linux/gpio.h>
> +#include <linux/input.h>
> +#include <linux/gpio_keys.h>
> +#include <linux/gpio-fan.h>
>  #include <linux/leds.h>
>  #include <linux/mtd/physmap.h>
>  #include <linux/spi/flash.h>
> @@ -150,6 +154,291 @@ static void __init dreamplug_init(void)
>  	platform_device_register(&dreamplug_leds);
>  }
>  
> +/*****************************************************************************
> + * DNS-320 & DNS-325 specifics
> + ****************************************************************************/
> +
> +static struct mtd_partition dnskw_nand_parts[] = {
> +	{
> +		.name		= "u-boot",
> +		.offset		= 0,
> +		.size		= SZ_1M,
> +		.mask_flags	= MTD_WRITEABLE
> +	}, {
> +		.name		= "uImage",
> +		.offset		= MTDPART_OFS_NXTBLK,
> +		.size		= 5 * SZ_1M
> +	}, {
> +		.name		= "ramdisk",
> +		.offset		= MTDPART_OFS_NXTBLK,
> +		.size		= 5 * SZ_1M
> +	}, {
> +		.name		= "image",
> +		.offset		= MTDPART_OFS_NXTBLK,
> +		.size		= 102 * SZ_1M
> +	}, {
> +		.name		= "mini firmware",
> +		.offset		= MTDPART_OFS_NXTBLK,
> +		.size		= 10 * SZ_1M
> +	}, {
> +		.name		= "config",
> +		.offset		= MTDPART_OFS_NXTBLK,
> +		.size		= 5 * SZ_1M
> +	},
> +};

You should probably squeeze in a partition for the dtb.  ;-)

Is the config partition the u-boot environment?  That usually is much
smaller than what you have alotted.  So, you might be able to split that
to make room for the dtb.

> +
> +static struct mv643xx_eth_platform_data dnskw_ge00_data = {
> +	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
> +};
> +
> +static unsigned int dnskw_mpp_config[] __initdata = {
> +	MPP13_UART1_TXD,	/* Custom ... */
> +	MPP14_UART1_RXD,	/* ... Controller (DNS-320 only) */
> +	MPP20_SATA1_ACTn,	/* LED: White Right HDD */
> +	MPP21_SATA0_ACTn,	/* LED: White Left HDD */
> +	MPP24_GPIO,
> +	MPP25_GPIO,
> +	MPP26_GPIO,	/* LED: Power */
> +	MPP27_GPIO,	/* LED: Red Right HDD */
> +	MPP28_GPIO,	/* LED: Red Left HDD */
> +	MPP29_GPIO,	/* LED: Red USB (DNS-325 only) */
> +	MPP30_GPIO,
> +	MPP31_GPIO,
> +	MPP32_GPIO,
> +	MPP33_GPO,
> +	MPP34_GPIO,	/* Button: Front power */
> +	MPP35_GPIO,	/* LED: Red USB (DNS-320 only) */
> +	MPP36_GPIO,	/* Power: MV88F6281_DEV_ID Board */
> +	MPP37_GPIO,	/* Power: Boot when power applied */
> +	MPP38_GPIO,
> +	MPP39_GPIO,	/* Power: SATA0 */
> +	MPP40_GPIO,	/* Power: SATA1 */
> +	MPP41_GPIO,
> +	MPP42_GPIO,
> +	MPP43_GPIO,	/* LED: White USB */
> +	MPP44_GPIO,	/* Fan: Tachometer Pin */
> +	MPP45_GPIO,	/* Fan: high speed */
> +	MPP46_GPIO,	/* Fan: low speed */
> +	MPP47_GPIO,	/* Button: Back unmount */
> +	MPP48_GPIO,	/* Button: Back reset */
> +	MPP49_GPIO,	/* Pin of unused U5 (DNS-320 only) */
> +	0
> +};
> +
> +static struct gpio_led dns325_led_pins[] = {
> +	{
> +		.name	= "dns325:white:power",
> +		.gpio	= 26,
> +		.active_low = 1,
> +		.default_trigger = "default-on",
> +	},
> +	{
> +		.name	= "dns325:white:usb",
> +		.gpio	= 43,
> +		.active_low = 1,
> +	},
> +	{
> +		.name	= "dns325:red:l_hdd",
> +		.gpio	= 28,
> +		.active_low = 1,
> +	},
> +	{
> +		.name	= "dns325:red:r_hdd",
> +		.gpio	= 27,
> +		.active_low = 1,
> +	},
> +	{
> +		.name	= "dns325:red:usb",
> +		.gpio	= 29,
> +		.active_low = 1,
> +	},
> +};
> +
> +static struct gpio_led_platform_data dns325_led_data = {
> +	.num_leds	= ARRAY_SIZE(dns325_led_pins),
> +	.leds		= dns325_led_pins,
> +};
> +
> +static struct platform_device dns325_led_device = {
> +	.name		= "leds-gpio",
> +	.id		= -1,
> +	.dev		= {
> +		.platform_data	= &dns325_led_data,
> +	},
> +};
> +
> +static struct gpio_led dns320_led_pins[] = {
> +	{
> +		.name	= "dns320:blue:power",
> +		.gpio	= 26,
> +		.active_low = 1,
> +		.default_trigger = "default-on",
> +	},
> +	{
> +		.name	= "dns320:blue:usb",
> +		.gpio	= 43,
> +		.active_low = 1,
> +	},
> +	{
> +		.name	= "dns320:orange:l_hdd",
> +		.gpio	= 28,
> +		.active_low = 1,
> +	},
> +	{
> +		.name	= "dns320:orange:r_hdd",
> +		.gpio	= 27,
> +		.active_low = 1,
> +	},
> +	{
> +		.name	= "dns320:orange:usb",
> +		.gpio	= 35,
> +		.active_low = 1,
> +	},
> +};
> +
> +static struct gpio_led_platform_data dns320_led_data = {
> +	.num_leds	= ARRAY_SIZE(dns320_led_pins),
> +	.leds		= dns320_led_pins,
> +};
> +
> +static struct platform_device dns320_led_device = {
> +	.name		= "leds-gpio",
> +	.id		= -1,
> +	.dev		= {
> +		.platform_data	= &dns320_led_data,
> +	},
> +};
> +
> +static struct i2c_board_info dns325_i2c_board_info[] __initdata = {
> +	{
> +		I2C_BOARD_INFO("lm75", 0x48),
> +	},
> +	/* Something at 0x0c also */
> +};
> +
> +static struct gpio_keys_button dnskw_button_pins[] = {
> +	{
> +		.code		= KEY_POWER,
> +		.gpio		= 34,
> +		.desc		= "Power button",
> +		.active_low	= 1,
> +	},
> +	{
> +		.code		= KEY_EJECTCD,
> +		.gpio		= 47,
> +		.desc		= "USB unmount button",
> +		.active_low	= 1,
> +	},
> +	{
> +		.code		= KEY_RESTART,
> +		.gpio		= 48,
> +		.desc		= "Reset button",
> +		.active_low	= 1,
> +	},
> +};
> +
> +static struct gpio_keys_platform_data dnskw_button_data = {
> +	.buttons	= dnskw_button_pins,
> +	.nbuttons	= ARRAY_SIZE(dnskw_button_pins),
> +};
> +
> +static struct platform_device dnskw_button_device = {
> +	.name		= "gpio-keys",
> +	.id		= -1,
> +	.num_resources	= 0,
> +	.dev		= {
> +		.platform_data	= &dnskw_button_data,
> +	}
> +};
> +
> +/* Fan: ADDA AD045HB-G73 40mm 6000rpm at 5v */
> +static struct gpio_fan_speed dnskw_fan_speed[] = {
> +	{    0,  0 },
> +	{ 3000,	 1 },
> +	{ 6000,	 2 },
> +};
> +static unsigned dnskw_fan_pins[] = {46, 45};
> +
> +static struct gpio_fan_platform_data dnskw_fan_data = {
> +	.num_ctrl	= ARRAY_SIZE(dnskw_fan_pins),
> +	.ctrl		= dnskw_fan_pins,
> +	.num_speed	= ARRAY_SIZE(dnskw_fan_speed),
> +	.speed		= dnskw_fan_speed,
> +};
> +
> +static struct platform_device dnskw_fan_device = {
> +	.name	= "gpio-fan",
> +	.id	= -1,
> +	.dev	= {
> +		.platform_data	= &dnskw_fan_data,
> +	},
> +};
> +
> +static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
> +{
> +	if (gpio_request(gpio, name) == 0 &&
> +	    gpio_direction_output(gpio, 0) == 0) {
> +		gpio_set_value(gpio, def);
> +		if (gpio_export(gpio, 0) != 0)
> +			pr_err("dnskw: Failed to export GPIO %s\n", name);
> +	} else
> +		pr_err("dnskw: Failed to register %s\n", name);
> +}
> +
> +static void dnskw_power_off(void)
> +{
> +	gpio_set_value(36, 1);
> +}
> +
> +static void __init dnskw_init(void)
> +{
> +	u32 dev, rev;
> +
> +	kirkwood_mpp_conf(dnskw_mpp_config);
> +	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
> +
> +	kirkwood_ge00_init(&dnskw_ge00_data);
> +	kirkwood_i2c_init();
> +
> +	platform_device_register(&dnskw_button_device);
> +	platform_device_register(&dnskw_fan_device);
> +
> +	if (of_machine_is_compatible("dlink,dns-325")) {
> +		i2c_register_board_info(0, dns325_i2c_board_info,
> +					ARRAY_SIZE(dns325_i2c_board_info));
> +		platform_device_register(&dns325_led_device);
> +
> +	} else if (of_machine_is_compatible("dlink,dns-320")) {
> +		platform_device_register(&dns320_led_device);
> +	}

braces not needed.

> +
> +	/* Register power off routine */
> +	kirkwood_pcie_id(&dev, &rev);
> +	if (dev == MV88F6281_DEV_ID) {
> +		pr_info("PCI-E Device ID: MV88F6281, configuring power-off");
> +		if (gpio_request(36, "dnskw:power:off") == 0 &&
> +		    gpio_direction_output(36, 0) == 0)
> +			pm_power_off = dnskw_power_off;
> +		else
> +			pr_err("dnskw: failed to configure power-off GPIO\n");
> +	} else {
> +		/*
> +		 * Dlink code also defines 0x6192, and sets LOW_BASE +
> +		 * 0x01000000 high. Either cargo-culted code or another model.
> +		 */

I'm just curious, what is cargo-culted?

> +		pr_err("Unknown PCI-E Device ID %x, no power-off", dev);
> +	}
> +
> +	/*
> +	 * Supply power to HDDs. Bootloader should have turned on sata0 already
> +	 */

Don't assume the bootloader does or doesn't do anything.  Put the
peripheral into a known state and work from there.

> +	dnskw_gpio_register(39, "dnskw:power:sata0", 1);
> +	dnskw_gpio_register(40, "dnskw:power:sata1", 1);
> +
> +	/* Set NAS to turn back on after a power failure */
> +	dnskw_gpio_register(37, "dnskw:power:recover", 1);
> +}
> +

I doubt this board is the only one that wants to be added while the
conversion to devicetree is progressing.  It makes more sense to me to
break the above out to a separate file, eg board-dnskw.c.  I'll follow
and break out the dreamplug code to board-dreamplug.c.  Otherwise, I see
board-dt.c becoming a long mess.

Arnd, sound okay to you?

>  static void __init kirkwood_dt_init(void)
>  {
>  	struct device_node *node;
> @@ -186,11 +475,16 @@ static void __init kirkwood_dt_init(void)
>  	if (of_machine_is_compatible("globalscale,dreamplug"))
>  		dreamplug_init();
>  
> +	if (of_machine_is_compatible("dlink,dns-kirkwood"))
> +		dnskw_init();
> +
>  	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
>  }
>  
>  static const char *kirkwood_dt_board_compat[] = {
>  	"globalscale,dreamplug",
> +	"dlink,dns-320",
> +	"dlink,dns-325",
>  	NULL
>  };
>  
> -- 
> 1.7.9.1
> 


From jason at lakedaemon.net  Sun Mar 11 22:36:32 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 11 Mar 2012 22:36:32 -0400
Subject: [PATCH 0/2] Add support for DNS-320 and DNS-325 using devicetree
In-Reply-To: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
Message-ID: <20120312023632.GW5050@titan.lakedaemon.net>

On Sun, Mar 11, 2012 at 02:33:24PM +0000, Jamie Lentin wrote:
> As agreed with Arnd Bergmann and Jason Cooper, include any board setup that
> cannot be done in devicetree in board-dt.c, then replace with devicetree
> entries.
> 
> The NAND driver is converted to devicetree as part of this patch series, 
> although I don't feel qualified to explain the parameters actually mean so 
> have left documentation fields blank.

Thanks!

> The patches should apply cleanly to staging/kirkwood/dt, although 
> kirkwood-dns320.dts attempts to override the orion-wdt definition with a
> lower TCLK, even though the orion-wdt work isn't merged yet. If this would
> be better to remove I shall.

It would be better if you base off of my stable branch.  You won't have
the clock issues (wdt isn't merged there yet).  Also, my staging branch
has been in flux and will soon be renamed/removed.

> Cheers,
> 
> Jamie Lentin (2):
>   ARM: kirkwood: Basic support for DNS-320 and DNS-325
>   ARM: kirkwood: Convert orion-nand to fdt
> 
>  .../devicetree/bindings/mtd/orion-nand.txt         |   41 +++
>  arch/arm/boot/dts/kirkwood-dns320.dts              |   96 +++++++
>  arch/arm/boot/dts/kirkwood-dns325.dts              |   82 ++++++
>  arch/arm/mach-kirkwood/Kconfig                     |   18 ++
>  arch/arm/mach-kirkwood/Makefile.boot               |    2 +
>  arch/arm/mach-kirkwood/board-dt.c                  |  264 ++++++++++++++++++++
>  arch/arm/mach-kirkwood/common.c                    |    6 +
>  drivers/mtd/nand/orion_nand.c                      |   39 +++-
>  8 files changed, 546 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt
>  create mode 100644 arch/arm/boot/dts/kirkwood-dns320.dts
>  create mode 100644 arch/arm/boot/dts/kirkwood-dns325.dts
> 
> -- 
> 1.7.9.1
> 


From bryan.wu at canonical.com  Sun Mar 11 22:32:19 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Mon, 12 Mar 2012 10:32:19 +0800
Subject: [PATCH 1/3] led-class: change back LEDS_CLASS to tristate instead
 of bool
In-Reply-To: <1331471632.14746.3.camel@ted>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
 <1331471632.14746.3.camel@ted>
Message-ID: <CAK5ve-JFotWoeDCfBLpBbTnpvp2hpkY-tK8nJvdN1WfV7o0cdw@mail.gmail.com>

On Sun, Mar 11, 2012 at 9:13 PM, Richard Purdie
<richard.purdie at linuxfoundation.org> wrote:
> On Thu, 2012-03-08 at 17:11 +0800, Bryan Wu wrote:
>> After moving some core functions to led-core.c, led-class.c can be built as
>> module again.
>>
>> Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
>
> I'd prefer to have less code being required in led-core.c but this is
> better than many of the alternatives. I'm happy to see it becoming
> modular again, thanks!
>
> Acked-by: Richard Purdie <richard.purdie at linuxfoundation.org>
>

Great, Thank you very much.

-Bryan

>> ---
>> ?drivers/leds/Kconfig ? ? | ? ?2 +-
>> ?drivers/leds/led-class.c | ? 70 ----------------------------------------------
>> ?drivers/leds/led-core.c ?| ? 70 ++++++++++++++++++++++++++++++++++++++++++++++
>> ?3 files changed, 71 insertions(+), 71 deletions(-)
>>
>> diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
>> index 9ca28fc..3f17f0d 100644
>> --- a/drivers/leds/Kconfig
>> +++ b/drivers/leds/Kconfig
>> @@ -17,7 +17,7 @@ menuconfig NEW_LEDS
>> ?if NEW_LEDS
>>
>> ?config LEDS_CLASS
>> - ? ? bool "LED Class Support"
>> + ? ? tristate "LED Class Support"
>> ? ? ? help
>> ? ? ? ? This option enables the led sysfs class in /sys/class/leds. ?You'll
>> ? ? ? ? need this to do anything useful with LEDs. ?If unsure, say N.
>> diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
>> index 0c8739c..5bff843 100644
>> --- a/drivers/leds/led-class.c
>> +++ b/drivers/leds/led-class.c
>> @@ -110,50 +110,6 @@ static void led_timer_function(unsigned long data)
>> ? ? ? mod_timer(&led_cdev->blink_timer, jiffies + msecs_to_jiffies(delay));
>> ?}
>>
>> -static void led_stop_software_blink(struct led_classdev *led_cdev)
>> -{
>> - ? ? /* deactivate previous settings */
>> - ? ? del_timer_sync(&led_cdev->blink_timer);
>> - ? ? led_cdev->blink_delay_on = 0;
>> - ? ? led_cdev->blink_delay_off = 0;
>> -}
>> -
>> -static void led_set_software_blink(struct led_classdev *led_cdev,
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long delay_on,
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long delay_off)
>> -{
>> - ? ? int current_brightness;
>> -
>> - ? ? current_brightness = led_get_brightness(led_cdev);
>> - ? ? if (current_brightness)
>> - ? ? ? ? ? ? led_cdev->blink_brightness = current_brightness;
>> - ? ? if (!led_cdev->blink_brightness)
>> - ? ? ? ? ? ? led_cdev->blink_brightness = led_cdev->max_brightness;
>> -
>> - ? ? if (led_get_trigger_data(led_cdev) &&
>> - ? ? ? ? delay_on == led_cdev->blink_delay_on &&
>> - ? ? ? ? delay_off == led_cdev->blink_delay_off)
>> - ? ? ? ? ? ? return;
>> -
>> - ? ? led_stop_software_blink(led_cdev);
>> -
>> - ? ? led_cdev->blink_delay_on = delay_on;
>> - ? ? led_cdev->blink_delay_off = delay_off;
>> -
>> - ? ? /* never on - don't blink */
>> - ? ? if (!delay_on)
>> - ? ? ? ? ? ? return;
>> -
>> - ? ? /* never off - just set to brightness */
>> - ? ? if (!delay_off) {
>> - ? ? ? ? ? ? led_set_brightness(led_cdev, led_cdev->blink_brightness);
>> - ? ? ? ? ? ? return;
>> - ? ? }
>> -
>> - ? ? mod_timer(&led_cdev->blink_timer, jiffies + 1);
>> -}
>> -
>> -
>> ?/**
>> ? * led_classdev_suspend - suspend an led_classdev.
>> ? * @led_cdev: the led_classdev to suspend.
>> @@ -262,32 +218,6 @@ void led_classdev_unregister(struct led_classdev *led_cdev)
>> ?}
>> ?EXPORT_SYMBOL_GPL(led_classdev_unregister);
>>
>> -void led_blink_set(struct led_classdev *led_cdev,
>> - ? ? ? ? ? ? ? ?unsigned long *delay_on,
>> - ? ? ? ? ? ? ? ?unsigned long *delay_off)
>> -{
>> - ? ? del_timer_sync(&led_cdev->blink_timer);
>> -
>> - ? ? if (led_cdev->blink_set &&
>> - ? ? ? ? !led_cdev->blink_set(led_cdev, delay_on, delay_off))
>> - ? ? ? ? ? ? return;
>> -
>> - ? ? /* blink with 1 Hz as default if nothing specified */
>> - ? ? if (!*delay_on && !*delay_off)
>> - ? ? ? ? ? ? *delay_on = *delay_off = 500;
>> -
>> - ? ? led_set_software_blink(led_cdev, *delay_on, *delay_off);
>> -}
>> -EXPORT_SYMBOL(led_blink_set);
>> -
>> -void led_brightness_set(struct led_classdev *led_cdev,
>> - ? ? ? ? ? ? ? ? ? ? enum led_brightness brightness)
>> -{
>> - ? ? led_stop_software_blink(led_cdev);
>> - ? ? led_cdev->brightness_set(led_cdev, brightness);
>> -}
>> -EXPORT_SYMBOL(led_brightness_set);
>> -
>> ?static int __init leds_init(void)
>> ?{
>> ? ? ? leds_class = class_create(THIS_MODULE, "leds");
>> diff --git a/drivers/leds/led-core.c b/drivers/leds/led-core.c
>> index 016d19f..d686004 100644
>> --- a/drivers/leds/led-core.c
>> +++ b/drivers/leds/led-core.c
>> @@ -23,3 +23,73 @@ EXPORT_SYMBOL_GPL(leds_list_lock);
>>
>> ?LIST_HEAD(leds_list);
>> ?EXPORT_SYMBOL_GPL(leds_list);
>> +
>> +static void led_stop_software_blink(struct led_classdev *led_cdev)
>> +{
>> + ? ? /* deactivate previous settings */
>> + ? ? del_timer_sync(&led_cdev->blink_timer);
>> + ? ? led_cdev->blink_delay_on = 0;
>> + ? ? led_cdev->blink_delay_off = 0;
>> +}
>> +
>> +static void led_set_software_blink(struct led_classdev *led_cdev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long delay_on,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long delay_off)
>> +{
>> + ? ? int current_brightness;
>> +
>> + ? ? current_brightness = led_get_brightness(led_cdev);
>> + ? ? if (current_brightness)
>> + ? ? ? ? ? ? led_cdev->blink_brightness = current_brightness;
>> + ? ? if (!led_cdev->blink_brightness)
>> + ? ? ? ? ? ? led_cdev->blink_brightness = led_cdev->max_brightness;
>> +
>> + ? ? if (led_get_trigger_data(led_cdev) &&
>> + ? ? ? ? delay_on == led_cdev->blink_delay_on &&
>> + ? ? ? ? delay_off == led_cdev->blink_delay_off)
>> + ? ? ? ? ? ? return;
>> +
>> + ? ? led_stop_software_blink(led_cdev);
>> +
>> + ? ? led_cdev->blink_delay_on = delay_on;
>> + ? ? led_cdev->blink_delay_off = delay_off;
>> +
>> + ? ? /* never on - don't blink */
>> + ? ? if (!delay_on)
>> + ? ? ? ? ? ? return;
>> +
>> + ? ? /* never off - just set to brightness */
>> + ? ? if (!delay_off) {
>> + ? ? ? ? ? ? led_set_brightness(led_cdev, led_cdev->blink_brightness);
>> + ? ? ? ? ? ? return;
>> + ? ? }
>> +
>> + ? ? mod_timer(&led_cdev->blink_timer, jiffies + 1);
>> +}
>> +
>> +
>> +void led_blink_set(struct led_classdev *led_cdev,
>> + ? ? ? ? ? ? ? ?unsigned long *delay_on,
>> + ? ? ? ? ? ? ? ?unsigned long *delay_off)
>> +{
>> + ? ? del_timer_sync(&led_cdev->blink_timer);
>> +
>> + ? ? if (led_cdev->blink_set &&
>> + ? ? ? ? !led_cdev->blink_set(led_cdev, delay_on, delay_off))
>> + ? ? ? ? ? ? return;
>> +
>> + ? ? /* blink with 1 Hz as default if nothing specified */
>> + ? ? if (!*delay_on && !*delay_off)
>> + ? ? ? ? ? ? *delay_on = *delay_off = 500;
>> +
>> + ? ? led_set_software_blink(led_cdev, *delay_on, *delay_off);
>> +}
>> +EXPORT_SYMBOL(led_blink_set);
>> +
>> +void led_brightness_set(struct led_classdev *led_cdev,
>> + ? ? ? ? ? ? ? ? ? ? enum led_brightness brightness)
>> +{
>> + ? ? led_stop_software_blink(led_cdev);
>> + ? ? led_cdev->brightness_set(led_cdev, brightness);
>> +}
>> +EXPORT_SYMBOL(led_brightness_set);
>
>



-- 
Bryan Wu <bryan.wu at canonical.com>
Kernel Developer ? ?+86.138-1617-6545 Mobile
Canonical Ltd. ? ? ?www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com


From pavan.savoy at gmail.com  Sun Mar 11 16:13:43 2012
From: pavan.savoy at gmail.com (Pavan Savoy)
Date: Sun, 11 Mar 2012 14:13:43 -0600
Subject: [PATCH v2] ARM: OMAP: WiLink platform data for the PandaBoard
In-Reply-To: <4F5D057A.3080601@gmail.com>
References: <1331074504-22683-1-git-send-email-mgherzan@gmail.com>
 <20120309183150.GH12083@atomide.com> <4F5D057A.3080601@gmail.com>
Message-ID: <CAHd==dp1GNov4gqMzPLkJzX1A205HUMhTPtg28399FcPQFZH0A@mail.gmail.com>

On Sun, Mar 11, 2012 at 2:05 PM, Mircea Gherzan <mgherzan at gmail.com> wrote:
> Am 09.03.2012 19:31, schrieb Tony Lindgren:
>> Hi Luca,
>>
>> * Mircea Gherzan <mgherzan at gmail.com> [120306 14:23]:
>>> The "uim" deamon requires sysfs entries that are filled in using
>>> this platform data.
>>>
>>> Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
>>> ---
>>> ?arch/arm/mach-omap2/board-omap4panda.c | ? 14 ++++++++++++--
>>> ?include/linux/ti_wilink_st.h ? ? ? ? ? | ? ?2 ++
>>> ?2 files changed, 14 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
>>> index b1d74d6..339e781 100644
>>> --- a/arch/arm/mach-omap2/board-omap4panda.c
>>> +++ b/arch/arm/mach-omap2/board-omap4panda.c
>>> @@ -27,6 +27,7 @@
>>> ?#include <linux/i2c/twl.h>
>>> ?#include <linux/regulator/machine.h>
>>> ?#include <linux/regulator/fixed.h>
>>> +#include <linux/ti_wilink_st.h>
>>> ?#include <linux/wl12xx.h>
>>>
>>> ?#include <mach/hardware.h>
>>> @@ -56,12 +57,21 @@
>>> ?#define HDMI_GPIO_HPD ?63 /* Hotplug detect */
>>>
>>> ?/* wl127x BT, FM, GPS connectivity chip */
>>> -static int wl1271_gpios[] = {46, -1, -1};
>>> +static struct ti_st_plat_data wilink_platform_data = {
>>> + ? ?.nshutdown_gpio = 46,
>>> + ? ?.dev_name ? ? ? = "/dev/ttyO1",
>>> + ? ?.flow_cntrl ? ? = 1,
>>> + ? ?.baud_rate ? ? ?= 3000000,
>>> + ? ?.chip_enable ? ?= NULL,
>>> + ? ?.suspend ? ? ? ?= NULL,
>>> + ? ?.resume ? ? ? ? = NULL,
>>> +};
>>> +
>>> ?static struct platform_device wl1271_device = {
>>> ? ? ?.name ? = "kim",
>>> ? ? ?.id ? ? = -1,
>>> ? ? ?.dev ? ?= {
>>> - ? ? ? ? ? ?.platform_data ?= &wl1271_gpios,
>>> + ? ? ? ? ? ?.platform_data ?= &wilink_platform_data,
>>> ? ? ?},
>>> ?};
>>>
>>> diff --git a/include/linux/ti_wilink_st.h b/include/linux/ti_wilink_st.h
>>> index 2ef4385..3ca0269 100644
>>> --- a/include/linux/ti_wilink_st.h
>>> +++ b/include/linux/ti_wilink_st.h
>>> @@ -25,6 +25,8 @@
>>> ?#ifndef TI_WILINK_ST_H
>>> ?#define TI_WILINK_ST_H
>>>
>>> +#include <linux/skbuff.h>
>>> +
>>> ?/**
>>> ? * enum proto-type - The protocol on WiLink chips which share a
>>> ? * ?common physical interface like UART.
>>> --
>>
>> Just checking.. Can you please take a look at this patch
>> and confirm that this is how things are supposed to be done?
>>
>> To me passing some third driver's dev_name in pdata seems
>> pretty weird.. But then again maybe I just don't know how
>> this is supposed to work.
>
> This is what the ti_st driver expects in the platform data structure.
> More precisely, in kim_probe():
>
> ? ? ? ?/* copying platform data */
> ? ? ? ?strncpy(kim_gdata->dev_name, pdata->dev_name,UART_DEV_NAME_LEN);
> ? ? ? ?kim_gdata->flow_cntrl = pdata->flow_cntrl;
> ? ? ? ?kim_gdata->baud_rate = pdata->baud_rate;
> ? ? ? ?pr_info("sysfs entries created\n");
>
> So IMHO the patch is a valid fix. However, one more patch [1] is still
> required to get BT and WLAN working on the PandaBoard.

The patch looks alright to me.
Yes, the UART to which BT chip is connected (along with other
technologies for which shared transport is required), the baud rate
which the UART supports & also a flag so as to check whether it
supports flow control - ideally is supposed to come from boot-loader,
device tree sort of configuration - if not can be hard-coded in the
relevant platform specific files like in this case.

This is picked up from ST as platform data as is read from the
user-space daemon, because unfortunately none of these configurations
can be done in kernel (the right way for TTY).

1 more patch or an addition to this patch to add the wl1271_device &
the btwilink device is also required to get ST probe & BT probe.
The btwilink driver is a platform device because UART devices don't
have a probe mechanism unlike say usb, i2c..

> Thanks,
> Mircea
>
> [1] http://elinux.org/images/8/8d/0001a-omap4-pandaboard-wlan-fix.patch
>



-- 
--Pavan Savoy


From grant.likely at secretlab.ca  Fri Mar  9 10:14:45 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 09 Mar 2012 08:14:45 -0700
Subject: [PATCH 1/4 v4] of_spi: add generic binding support to specify cs
 gpio
In-Reply-To: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120309151445.97E2B3E0901@localhost>

On Wed,  7 Mar 2012 13:23:06 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> This will allow to use gpio for chip select with no modification in the
> driver binding
> 
> When use the cs-gpios, the gpio number will be passed via the cs_gpio field
> and the number of chip select will automatically increased.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: devicetree-discuss at lists.ozlabs.org
> Cc: spi-devel-general at lists.sourceforge.net
> ---
> v4:
> 	use cs_gpio to pass the gpio number
> 
> Best Regards,
> J.
>  Documentation/devicetree/bindings/spi/spi-bus.txt |    6 ++
>  drivers/spi/spi.c                                 |   57 +++++++++++++++++++-
>  include/linux/spi/spi.h                           |    6 ++
>  3 files changed, 66 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
> index e782add..c253379 100644
> --- a/Documentation/devicetree/bindings/spi/spi-bus.txt
> +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
> @@ -12,6 +12,7 @@ The SPI master node requires the following properties:
>  - #size-cells     - should be zero.
>  - compatible      - name of SPI bus controller following generic names
>      		recommended practice.
> +- cs-gpios	  - (optional) gpios chip select.
>  No other properties are required in the SPI bus node.  It is assumed
>  that a driver for an SPI bus device will understand that it is an SPI bus.
>  However, the binding does not attempt to define the specific method for
> @@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
>  chip selects.  Individual drivers can define additional properties to
>  support describing the chip select layout.
>  
> +If cs-gpios is used the number of chip select will automatically increased.
> +
>  SPI slave nodes must be children of the SPI master node and can
>  contain the following properties.
>  - reg             - (required) chip select address of device.
> @@ -34,6 +37,9 @@ contain the following properties.
>  - spi-cs-high     - (optional) Empty property indicating device requires
>      		chip select active high
>  
> +If a gpio chipselect is used for the SPI slave the gpio number will be passed
> +via the controller_data
> +
>  SPI example for an MPC5200 SPI bus:
>  	spi at f00 {
>  		#address-cells = <1>;
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index b2ccdea..c1d0955 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -28,6 +28,7 @@
>  #include <linux/mod_devicetable.h>
>  #include <linux/spi/spi.h>
>  #include <linux/of_spi.h>
> +#include <linux/of_gpio.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/export.h>
>  
> @@ -322,6 +323,7 @@ struct spi_device *spi_alloc_device(struct spi_master *master)
>  	spi->dev.parent = &master->dev;
>  	spi->dev.bus = &spi_bus_type;
>  	spi->dev.release = spidev_release;
> +	spi->cs_gpio = -EINVAL;
>  	device_initialize(&spi->dev);
>  	return spi;
>  }
> @@ -339,15 +341,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
>  int spi_add_device(struct spi_device *spi)
>  {
>  	static DEFINE_MUTEX(spi_add_lock);
> -	struct device *dev = spi->master->dev.parent;
> +	struct spi_master *master = spi->master;
> +	struct device *dev = master->dev.parent;
>  	struct device *d;
>  	int status;
>  
>  	/* Chipselects are numbered 0..max; validate. */
> -	if (spi->chip_select >= spi->master->num_chipselect) {
> +	if (spi->chip_select >= master->num_chipselect) {
>  		dev_err(dev, "cs%d >= max %d\n",
>  			spi->chip_select,
> -			spi->master->num_chipselect);
> +			master->num_chipselect);
>  		return -EINVAL;
>  	}
>  
> @@ -371,6 +374,13 @@ int spi_add_device(struct spi_device *spi)
>  		goto done;
>  	}
>  
> +	if (master->num_gpio_cs &&
> +	    spi->chip_select >= master->first_gpio_cs) {
> +		int num = spi->chip_select - master->first_gpio_cs;
> +
> +		spi->cs_gpio = master->cs_gpios[num];

spi->cs_gpio isn't used anywhere.

> +	}
> +
>  	/* Drivers may modify this initial i/o setup, but will
>  	 * normally rely on the device being setup.  Devices
>  	 * using SPI_CS_HIGH can't coexist well otherwise...
> @@ -561,6 +571,43 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
>  }
>  EXPORT_SYMBOL_GPL(spi_alloc_master);
>  
> +#ifdef CONFIG_OF
> +static int of_spi_register_master(struct spi_master *master)
> +{
> +	int nb, i;
> +	int *cs;
> +	struct device_node *np = master->dev.of_node;
> +
> +	if (!np)
> +		return 0;
> +
> +	nb = of_gpio_named_count(np, "cs-gpios");
> +
> +	if (nb < 1)
> +		return 0;
> +
> +	cs = devm_kzalloc(&master->dev, sizeof(int) * nb, GFP_KERNEL);
> +	master->cs_gpios = cs;
> +
> +	if (!master->cs_gpios)
> +		return -ENOMEM;
> +
> +	master->first_gpio_cs = master->num_chipselect;
> +	master->num_chipselect += nb;
> +	master->num_gpio_cs = nb;

I think this can be simplified.  Rather than trying to optimize by having
a set of integrated cs lines followed by a gpio set, I think it would be
better to have a single cs_gpios table that covers the whole range of
num_chipselect; even if they overlap natural cs lines.  That will make for
an easier to use binding since users won't need to remember how many natural
cs lines are on the device when filling the cs-gpios property.  It will
also make the code simpler because first_gpio_cs and num_gpio_cs can both
be eliminated.  It also means the core can have exact knowledge about which
gpio is associated with which cs number.

> +
> +	for (i = 0; i < nb; i++)
> +		cs[i] = of_get_named_gpio(np, "cs-gpios", i);
> +
> +	return 0;
> +}
> +#else
> +static int of_spi_register_master(struct spi_master *master)
> +{
> +	return 0;
> +}
> +#endif
> +
>  /**
>   * spi_register_master - register SPI master controller
>   * @master: initialized master, originally from spi_alloc_master()
> @@ -592,6 +639,10 @@ int spi_register_master(struct spi_master *master)
>  	if (!dev)
>  		return -ENODEV;
>  
> +	status = of_spi_register_master(master);
> +	if (status)
> +		return status;
> +
>  	/* even if it's just one always-selected device, there must
>  	 * be at least one chipselect
>  	 */
> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> index 176fce9..7dcf031 100644
> --- a/include/linux/spi/spi.h
> +++ b/include/linux/spi/spi.h
> @@ -89,6 +89,7 @@ struct spi_device {
>  	void			*controller_state;
>  	void			*controller_data;
>  	char			modalias[SPI_NAME_SIZE];
> +	int			cs_gpio;	/* chip select gpio */
>  
>  	/*
>  	 * likely need more hooks for more protocol options affecting how
> @@ -318,6 +319,11 @@ struct spi_master {
>  
>  	/* called on release() to free memory provided by spi_master */
>  	void			(*cleanup)(struct spi_device *spi);
> +
> +	/* gpio chip select */
> +	int			*cs_gpios;
> +	int			first_gpio_cs;
> +	int			num_gpio_cs;
>  };
>  
>  static inline void *spi_master_get_devdata(struct spi_master *master)
> -- 
> 1.7.7
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From marc at plastictigers.com  Fri Mar  9 17:39:52 2012
From: marc at plastictigers.com (Marc Butler)
Date: Fri, 9 Mar 2012 17:39:52 -0500
Subject: [RFC PATCH] slimbus message encoding/decoding
In-Reply-To: <4F5A5F00.70508@codeaurora.org>
References: <20120309002106.GA605@plastictigers.com>
 <4F5A5F00.70508@codeaurora.org>
Message-ID: <20120309223952.GA5669@plastictigers.com>

On Fri, Mar 09, 2012 at 12:50:24PM -0700, Sagar Dharia wrote:
> On 03/08/2012 05:21 PM, Marc Butler wrote:
> 
> Thanks for providing this patch. My understanding is that this patch
> provides helper functions for h/w controllers which rely on s/w to
> provide the exact message to be sent out on the bus.

Yes. The ti omap4430 expects the messages, to be complete except for
the PI, MR, and MI fields which are encoded by the h/w.

> Just like CRC, some other fields may be populated by HW. e.g.
> Qualcomm chip also populates Arbitration priority, Arbitration
> Extension fields. So it expects SW to only program a few fields,
> a.k.a logical/elemental address, MT,MC, DT etc.(that too, SW
> programs this based on software interface manual). The hardware will
> convert this information to actual slimbus-compliant message and
> send it on the bus.

Understood. The functions are not incompatible with construction
partial messages, but as it will not likely work when inserting the
header field, as it goes about trying to compute the remaining length,
based on the current (icomplete) message including the arbitration
header.

> Being said that, I am not aware of how majority of h/w controllers
> work and will be open to have this patch if other hardwares rely on
> s/w to provide the exact message as well.

The ti omap4430 requires this support.

Regards,
-m


From jean.pihet at newoldbits.com  Fri Mar  9 03:20:07 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Fri, 9 Mar 2012 09:20:07 +0100
Subject: [PATCH 5/9] ARM: OMAP36xx: hwmod data: fix SmartReflex interface
 data
In-Reply-To: <alpine.DEB.2.00.1203082051150.26656@utopia.booyaka.com>
References: <20120228110943.808.73639.stgit@dusk>
 <20120228111054.808.16941.stgit@dusk>
 <alpine.DEB.2.00.1203082051150.26656@utopia.booyaka.com>
Message-ID: <CAORVsuV8YXNRF=UjBOd8hoYbJ+ksg6RT1dZYC=TuUTmLiuD+ow@mail.gmail.com>

Hi Paul,

On Fri, Mar 9, 2012 at 4:51 AM, Paul Walmsley <paul at pwsan.com> wrote:
>
> Dropping this patch from this series due to conflicts with the SmartReflex
> branch. ?It will be moved to a subsequent series.
I can take this change as part of the series I am preparing for the SR
conversion to drivers/.
What do you thin?

> - Paul

Jean

> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html


From s.hauer at pengutronix.de  Fri Mar  9 12:44:11 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 9 Mar 2012 18:44:11 +0100
Subject: [PATCH v3 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120309174411.GI3852@pengutronix.de>

On Fri, Mar 09, 2012 at 04:20:36PM +0100, Javier Martin wrote:
> The following series have to be applied on top of the following patches:
> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
> 
> As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
> is deprecated and no new patches are accepted for it.
> 
> This series merges this code into the imx-dma.c dmaengine driver.

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From jp.francois at cynove.com  Fri Mar  9 02:34:44 2012
From: jp.francois at cynove.com (jean-philippe francois)
Date: Fri, 9 Mar 2012 08:34:44 +0100
Subject: Regression in 3.2.9 for omap-serial (at least)
In-Reply-To: <alpine.LFD.2.02.1203082024450.2742@ionos>
References: <lyk42vxsz2.fsf@ensc-virt.intern.sigma-chemnitz.de>
 <alpine.LFD.2.02.1203081246130.2742@ionos>
 <CAGGh5h3-1XhMO1-jiBdUJYgh4unRcPonvp=zcXLKMJBfS+qpuQ@mail.gmail.com>
 <alpine.LFD.2.02.1203082024450.2742@ionos>
Message-ID: <CAGGh5h0sC1mYFpDj973Xgbh7CQ3eGZEYVTy8qZwbsPBA_z4MRQ@mail.gmail.com>

Le 8 mars 2012 20:26, Thomas Gleixner <tglx at linutronix.de> a ?crit :
> On Thu, 8 Mar 2012, jean-philippe francois wrote:
>
>> Le 8 mars 2012 12:46, Thomas Gleixner <tglx at linutronix.de> a ?crit :
>> > On Thu, 8 Mar 2012, Enrico Scholz wrote:
>> >> Hi,
>> >>
>> >> the commit "genirq: Unmask oneshot irqs when thread was not woken"[1]
>> >> breaks at least the omap-serial driver which requests a shared interrupt
>> >
>> > Fixed with 52abb700e16a9a
>>
>> How can I find it ?
>> I tried searching in various tree on git.kernel.org,
>> but could not find the fix.
>
> It's in Linus tree.
>
> http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=52abb700e16a9aa4cbc03f3d7f80206cbbc80680

Thank you !
In fact I don't know how to use this interface to search by commit number.
Do you know if it is possible ?


From Richard.Earnshaw at arm.com  Fri Mar  9 12:38:38 2012
From: Richard.Earnshaw at arm.com (Richard Earnshaw)
Date: Fri, 9 Mar 2012 17:38:38 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <alpine.LFD.2.02.1203091112050.24151@xanadu.home>
References: <alpine.DEB.2.00.1202231714590.23091@kaball-desktop>
 <1330019314-20865-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <alpine.LFD.2.02.1203021528150.31242@xanadu.home> <4F5882BF.1030104@arm.com>
 <alpine.LFD.2.02.1203081041340.24151@xanadu.home> <4F58FEC0.8080706@arm.com>
 <CA+wbFdfF5c+Bw6RrxCm3YThqCRDuDYzanq+HV8a6LyXaBqWrQA@mail.gmail.com>
 <alpine.LFD.2.02.1203091112050.24151@xanadu.home>
Message-ID: <4F5A401E.3070008@arm.com>

On 09/03/12 16:20, Nicolas Pitre wrote:
> On Fri, 9 Mar 2012, Dave Martin wrote:
>
>> Register variables feel like a red herring though.  We're only using
>> those because we can't do the needful thing and actually desscribe
>> these constraints in the asm constraints (which would seem to be the
>> right place).  We specifically don't care where those values are
>> except at the boundaries of the asm block itself.
>
> Absolutely.
>
>> Is there a reason why ARM gcc doesn't provide the ability to specify
>> such exact-register constraints, or is this more for historical
>> reasons?  It is possible?
>
> I don't know how much things have changed since I last looked at the gcc
> code, but implementing this seemed to be pretty trivial at the time.
> The problem would be to determine a good letter scheme to map to actual
> registers.
>
>
> Nicolas
>

While it is technically possible, it is likely to end up hurting overall
compiler performance as we'll then have to define the machine as having
small register classes.

--
Richard Earnshaw             Email: Richard.Earnshaw at arm.com
Engineering Manager          Phone: +44 1223 400569 (Direct + VoiceMail)
OpenSource Tools             Switchboard: +44 1223 400400
ARM Ltd                      Fax: +44 1223 400410
110 Fulbourn Rd              Web: http://www.arm.com/
Cambridge, UK. CB1 9NJ

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.



From heiko at sntech.de  Mon Mar 12 15:03:36 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Mon, 12 Mar 2012 20:03:36 +0100
Subject: [PATCH 6/6] spi/s3c64xx: Allow usage for ARCH_S3C24XX
In-Reply-To: <201203121959.32966.heiko@sntech.de>
References: <201203121959.32966.heiko@sntech.de>
Message-ID: <201203122003.36553.heiko@sntech.de>

Newer SoCs from the S3C24XX line, namely S3C2416/2443/2450 contain
hsspi-controllers compatible with the s3c64xx type.

The previous patches enabled platform support for it, so make the
driver also usable for the S3C24xx architecture.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
---
 drivers/spi/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 004e6d1..e981fe6 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -305,7 +305,7 @@ config SPI_S3C24XX_FIQ
 
 config SPI_S3C64XX
 	tristate "Samsung S3C64XX series type SPI"
-	depends on (ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
+	depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
 	select S3C64XX_DMA if ARCH_S3C64XX
 	help
 	  SPI driver for Samsung S3C64XX and newer SoCs.
-- 
1.7.2.3



From mturquette at ti.com  Sun Mar 11 17:02:53 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Sun, 11 Mar 2012 14:02:53 -0700
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <20120311075250.GB3138@richard-laptop>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
 <20120311075250.GB3138@richard-laptop>
Message-ID: <CAJOA=zPzCSBHEynvm1hf-5VqdevAg26KQ2PZ5yykZqmxFywZpw@mail.gmail.com>

On Sat, Mar 10, 2012 at 11:52 PM, Richard Zhao <richard.zhao at linaro.org> wrote:
> Looks like you didn't take my comments for v5.
> http://www.spinics.net/lists/arm-kernel/msg162903.html

Sorry Richard, that one slipped through the cracks.  I'll publish a
new version tomorrow with some of those fixes.  Some of the others
(such as multiple pre-rate change notifiers) I won't take in, but we
can discuss more.

Regards,
Mike

>
> Regards
> Richard


From olof at lixom.net  Sat Mar 10 13:08:57 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 10:08:57 -0800
Subject: [GIT PULL 3/4] Samsung devel-mmc for v3.4
In-Reply-To: <4F5B7C8D.5000805@samsung.com>
References: <4F5B7C8D.5000805@samsung.com>
Message-ID: <CAOesGMgx-86rUuOfjTN8BeYZD+S=04oj+N9u-m9dr8JQA1Oxiw@mail.gmail.com>

Hi,

On Sat, Mar 10, 2012 at 8:08 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Hi Arnd, Olof
>
> This is regarding Samsung mmc for v3.4.
>
> As a note, v3.4-for-cjb branch is merged into mmc/mmc-next like following:
> http://git.kernel.org/?p=linux/kernel/git/cjb/mmc.git;a=commit;h=fcd9bdae386753531a9cb6b2577359a83f4e121c

Looking at this series, there's really only one patch that is not in
the mmc tree:

ARM: SAMSUNG: change the name from s3c-sdhci to exynos4-sdhci

And all it does is change the platform device string contents.

Since there are no build-time dependencies between this and the MMC
change, I suggest you send only this patch so that we avoid having
merge dependencies where not strictly needed.

Would that be OK with you? If so, please send a fresh pull request
with only the above change in it.



Thanks,

-Olof


From rusty at rustcorp.com.au  Thu Mar  8 23:26:52 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 09 Mar 2012 14:56:52 +1030
Subject: [PATCH 4/8] ARM: KVM: split cp15 mrc/mcr and mrrc/mcrr handling.
Message-ID: <1331267212.23398.rusty@rustcorp.com.au>


From: Rusty Russell <rusty at rustcorp.com.au>

The hardware has separate traps for the two cases, so don't prematurely
unify them.

Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
---
 arch/arm/include/asm/kvm_emulate.h |    3 +
 arch/arm/kvm/arm.c                 |    4 +
 arch/arm/kvm/emulate.c             |  102 ++++++++++++++++++++----------------
 3 files changed, 62 insertions(+), 47 deletions(-)

diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index 029f45f..fa54247 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -44,7 +44,8 @@ int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_handle_cp15_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_emulate_mmio_ls(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
 			unsigned long instr);
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index f27a96b..a6cf02b 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -377,8 +377,8 @@ static int handle_dabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
 
 static int (*arm_exit_handlers[])(struct kvm_vcpu *vcpu, struct kvm_run *r) = {
 	[HSR_EC_WFI]		= kvm_handle_wfi,
-	[HSR_EC_CP15_32]	= kvm_handle_cp15_access,
-	[HSR_EC_CP15_64]	= kvm_handle_cp15_access,
+	[HSR_EC_CP15_32]	= kvm_handle_cp15_32,
+	[HSR_EC_CP15_64]	= kvm_handle_cp15_64,
 	[HSR_EC_CP14_MR]	= kvm_handle_cp14_access,
 	[HSR_EC_CP14_LS]	= kvm_handle_cp14_load_store,
 	[HSR_EC_CP14_64]	= kvm_handle_cp14_access,
diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
index 87a1141..88c6493 100644
--- a/arch/arm/kvm/emulate.c
+++ b/arch/arm/kvm/emulate.c
@@ -304,62 +304,31 @@ static int emulate_cp15_c15_access(struct kvm_vcpu *vcpu,
 	return 0;
 }
 
-/**
- * kvm_handle_cp15_access -- handles a trap on a guest CP15 access
- * @vcpu: The VCPU pointer
- * @run:  The kvm_run struct
- *
- * Investigates the CRn/CRm and wether this was mcr/mrc or mcrr/mrrc and either
- * simply errors out if the operation was not supported (should maybe raise
- * undefined to guest instead?) and otherwise emulated access.
- */
-int kvm_handle_cp15_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
+static int emulate_cp15(struct kvm_vcpu *vcpu,
+			const struct coproc_params *params)
 {
-	unsigned long hsr_ec, instr_len;
-	struct coproc_params params;
-	int ret = 0;
-
-	hsr_ec = vcpu->arch.hsr >> HSR_EC_SHIFT;
-	params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
-	params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
-	BUG_ON(params.Rt1 >= 15);
-	params.is_write = ((vcpu->arch.hsr & 1) == 0);
-	params.is_64bit = (hsr_ec == HSR_EC_CP15_64);
-
-	if (params.is_64bit) {
-		/* mrrc, mccr operation */
-		params.Op1 = (vcpu->arch.hsr >> 16) & 0xf;
-		params.Op2 = 0;
-		params.Rt2 = (vcpu->arch.hsr >> 10) & 0xf;
-		BUG_ON(params.Rt2 >= 15);
-		params.CRn = 0;
-	} else {
-		params.CRn = (vcpu->arch.hsr >> 10) & 0xf;
-		params.Op1 = (vcpu->arch.hsr >> 14) & 0x7;
-		params.Op2 = (vcpu->arch.hsr >> 17) & 0x7;
-		params.Rt2 = 0;
-	}
+	unsigned long instr_len;
+	int ret;
 
 	/* So far no mrrc/mcrr accesses are emulated */
-	if (params.is_64bit)
+	if (params->is_64bit)
 		goto unsupp_err_out;
 
-	switch (params.CRn) {
+	switch (params->CRn) {
 	case 9:
-		ret = emulate_cp15_c9_access(vcpu, &params);
+		ret = emulate_cp15_c9_access(vcpu, params);
 		break;
 	case 10:
-		ret = emulate_cp15_c10_access(vcpu, &params);
+		ret = emulate_cp15_c10_access(vcpu, params);
 		break;
 	case 15:
-		ret = emulate_cp15_c15_access(vcpu, &params);
+		ret = emulate_cp15_c15_access(vcpu, params);
 		break;
 	default:
 		ret = -EINVAL;
-		break;
 	}
 
-	if (ret)
+	if (ret != 0)
 		goto unsupp_err_out;
 
 	/* Skip instruction, since it was emulated */
@@ -367,10 +336,55 @@ int kvm_handle_cp15_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
 	*vcpu_reg(vcpu, 15) += instr_len;
 
 	return ret;
-unsupp_err_out:
+
+unsupp_err_out:	
 	kvm_err("Unsupported guest CP15 access at: %08x\n", vcpu->arch.regs.pc);
-	print_cp_instr(&params);
-	return -EINVAL;
+	print_cp_instr(params);
+	return ret;
+}
+
+/**
+ * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	struct coproc_params params;
+
+	params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
+	params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
+	params.is_write = ((vcpu->arch.hsr & 1) == 0);
+	params.is_64bit = true;
+
+	params.Op1 = (vcpu->arch.hsr >> 16) & 0xf;
+	params.Op2 = 0;
+	params.Rt2 = (vcpu->arch.hsr >> 10) & 0xf;
+	params.CRn = 0;
+
+	return emulate_cp15(vcpu, &params);
+}
+
+/**
+ * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	struct coproc_params params;
+
+	params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
+	params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
+	params.is_write = ((vcpu->arch.hsr & 1) == 0);
+	params.is_64bit = false;
+
+	params.CRn = (vcpu->arch.hsr >> 10) & 0xf;
+	params.Op1 = (vcpu->arch.hsr >> 14) & 0x7;
+	params.Op2 = (vcpu->arch.hsr >> 17) & 0x7;
+	params.Rt2 = 0;
+
+	return emulate_cp15(vcpu, &params);
 }
 
 /**



From tarun.kanti at ti.com  Mon Mar 12 16:08:41 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Tue, 13 Mar 2012 01:38:41 +0530
Subject: [PATCH v3 00/13] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <CAC83Zv+8AjCHBOJbtvSQS-URvCE5Xm9oPk9_X7h4Kz7FZ_7Otw@mail.gmail.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <878vj5y7iv.fsf@ti.com>
 <CAC83Zv+8AjCHBOJbtvSQS-URvCE5Xm9oPk9_X7h4Kz7FZ_7Otw@mail.gmail.com>
Message-ID: <CAC83ZvJKS34Py6vVtk_Si9q3A-9CVN6v4ixNM+HJ37AATcGNPA@mail.gmail.com>

On Tue, Mar 13, 2012 at 1:23 AM, DebBarma, Tarun Kanti
<tarun.kanti at ti.com> wrote:
> On Tue, Mar 13, 2012 at 12:24 AM, Kevin Hilman <khilman at ti.com> wrote:
>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>>
>>> The cleanup is mostly getting rid of redundant fields in struct gpio_bank{}
>>> as we already have them as part of bank->context now. Also, remove un-used
>>> variable from gpio_irq_handler.
>>>
>>> The fixes include correction of _set_gpio_irqenable() implementation,
>>> missing wakeup_en register update in set_gpio_wakeup(), type mismatch
>>> of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
>>> register update in set_gpio_dataout_() and few corrections in context
>>> save logic.
>>>
>>> It is baselined on top of Kevin's following series:
>>> gpio/omap: cleanup and runtime PM conversion for v3.4
>>> git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/gpio/runtime-pm-cleanup
>>>
>>> Series is available here for reference:
>>> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_further_cleanup_fixes
>>
>> This branch doesn't exist.
> Oops... I am sorry.
> I was in the process of updating the branch with latest comments after
> base-lining on Grant's:
> git://git.secretlab.ca/git/linux-2.6.git
> Branch: gpio/next
> Because this has all the gpio changes including Benoit's latest gpio
> devicetree changes.
> Should I go ahead?
Anyways, for the time being I am updating on top of your changes as before.
You should be able to see the branch shortly.
--
Tarun
>>
>> Kevin
>>


From richard.purdie at linuxfoundation.org  Sun Mar 11 09:13:52 2012
From: richard.purdie at linuxfoundation.org (Richard Purdie)
Date: Sun, 11 Mar 2012 13:13:52 +0000
Subject: [PATCH 1/3] led-class: change back LEDS_CLASS to tristate
 instead of bool
In-Reply-To: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1331471632.14746.3.camel@ted>

On Thu, 2012-03-08 at 17:11 +0800, Bryan Wu wrote:
> After moving some core functions to led-core.c, led-class.c can be built as
> module again.
> 
> Signed-off-by: Bryan Wu <bryan.wu at canonical.com>

I'd prefer to have less code being required in led-core.c but this is
better than many of the alternatives. I'm happy to see it becoming
modular again, thanks!

Acked-by: Richard Purdie <richard.purdie at linuxfoundation.org>

> ---
>  drivers/leds/Kconfig     |    2 +-
>  drivers/leds/led-class.c |   70 ----------------------------------------------
>  drivers/leds/led-core.c  |   70 ++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 71 insertions(+), 71 deletions(-)
> 
> diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
> index 9ca28fc..3f17f0d 100644
> --- a/drivers/leds/Kconfig
> +++ b/drivers/leds/Kconfig
> @@ -17,7 +17,7 @@ menuconfig NEW_LEDS
>  if NEW_LEDS
>  
>  config LEDS_CLASS
> -	bool "LED Class Support"
> +	tristate "LED Class Support"
>  	help
>  	  This option enables the led sysfs class in /sys/class/leds.  You'll
>  	  need this to do anything useful with LEDs.  If unsure, say N.
> diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
> index 0c8739c..5bff843 100644
> --- a/drivers/leds/led-class.c
> +++ b/drivers/leds/led-class.c
> @@ -110,50 +110,6 @@ static void led_timer_function(unsigned long data)
>  	mod_timer(&led_cdev->blink_timer, jiffies + msecs_to_jiffies(delay));
>  }
>  
> -static void led_stop_software_blink(struct led_classdev *led_cdev)
> -{
> -	/* deactivate previous settings */
> -	del_timer_sync(&led_cdev->blink_timer);
> -	led_cdev->blink_delay_on = 0;
> -	led_cdev->blink_delay_off = 0;
> -}
> -
> -static void led_set_software_blink(struct led_classdev *led_cdev,
> -				   unsigned long delay_on,
> -				   unsigned long delay_off)
> -{
> -	int current_brightness;
> -
> -	current_brightness = led_get_brightness(led_cdev);
> -	if (current_brightness)
> -		led_cdev->blink_brightness = current_brightness;
> -	if (!led_cdev->blink_brightness)
> -		led_cdev->blink_brightness = led_cdev->max_brightness;
> -
> -	if (led_get_trigger_data(led_cdev) &&
> -	    delay_on == led_cdev->blink_delay_on &&
> -	    delay_off == led_cdev->blink_delay_off)
> -		return;
> -
> -	led_stop_software_blink(led_cdev);
> -
> -	led_cdev->blink_delay_on = delay_on;
> -	led_cdev->blink_delay_off = delay_off;
> -
> -	/* never on - don't blink */
> -	if (!delay_on)
> -		return;
> -
> -	/* never off - just set to brightness */
> -	if (!delay_off) {
> -		led_set_brightness(led_cdev, led_cdev->blink_brightness);
> -		return;
> -	}
> -
> -	mod_timer(&led_cdev->blink_timer, jiffies + 1);
> -}
> -
> -
>  /**
>   * led_classdev_suspend - suspend an led_classdev.
>   * @led_cdev: the led_classdev to suspend.
> @@ -262,32 +218,6 @@ void led_classdev_unregister(struct led_classdev *led_cdev)
>  }
>  EXPORT_SYMBOL_GPL(led_classdev_unregister);
>  
> -void led_blink_set(struct led_classdev *led_cdev,
> -		   unsigned long *delay_on,
> -		   unsigned long *delay_off)
> -{
> -	del_timer_sync(&led_cdev->blink_timer);
> -
> -	if (led_cdev->blink_set &&
> -	    !led_cdev->blink_set(led_cdev, delay_on, delay_off))
> -		return;
> -
> -	/* blink with 1 Hz as default if nothing specified */
> -	if (!*delay_on && !*delay_off)
> -		*delay_on = *delay_off = 500;
> -
> -	led_set_software_blink(led_cdev, *delay_on, *delay_off);
> -}
> -EXPORT_SYMBOL(led_blink_set);
> -
> -void led_brightness_set(struct led_classdev *led_cdev,
> -			enum led_brightness brightness)
> -{
> -	led_stop_software_blink(led_cdev);
> -	led_cdev->brightness_set(led_cdev, brightness);
> -}
> -EXPORT_SYMBOL(led_brightness_set);
> -
>  static int __init leds_init(void)
>  {
>  	leds_class = class_create(THIS_MODULE, "leds");
> diff --git a/drivers/leds/led-core.c b/drivers/leds/led-core.c
> index 016d19f..d686004 100644
> --- a/drivers/leds/led-core.c
> +++ b/drivers/leds/led-core.c
> @@ -23,3 +23,73 @@ EXPORT_SYMBOL_GPL(leds_list_lock);
>  
>  LIST_HEAD(leds_list);
>  EXPORT_SYMBOL_GPL(leds_list);
> +
> +static void led_stop_software_blink(struct led_classdev *led_cdev)
> +{
> +	/* deactivate previous settings */
> +	del_timer_sync(&led_cdev->blink_timer);
> +	led_cdev->blink_delay_on = 0;
> +	led_cdev->blink_delay_off = 0;
> +}
> +
> +static void led_set_software_blink(struct led_classdev *led_cdev,
> +				   unsigned long delay_on,
> +				   unsigned long delay_off)
> +{
> +	int current_brightness;
> +
> +	current_brightness = led_get_brightness(led_cdev);
> +	if (current_brightness)
> +		led_cdev->blink_brightness = current_brightness;
> +	if (!led_cdev->blink_brightness)
> +		led_cdev->blink_brightness = led_cdev->max_brightness;
> +
> +	if (led_get_trigger_data(led_cdev) &&
> +	    delay_on == led_cdev->blink_delay_on &&
> +	    delay_off == led_cdev->blink_delay_off)
> +		return;
> +
> +	led_stop_software_blink(led_cdev);
> +
> +	led_cdev->blink_delay_on = delay_on;
> +	led_cdev->blink_delay_off = delay_off;
> +
> +	/* never on - don't blink */
> +	if (!delay_on)
> +		return;
> +
> +	/* never off - just set to brightness */
> +	if (!delay_off) {
> +		led_set_brightness(led_cdev, led_cdev->blink_brightness);
> +		return;
> +	}
> +
> +	mod_timer(&led_cdev->blink_timer, jiffies + 1);
> +}
> +
> +
> +void led_blink_set(struct led_classdev *led_cdev,
> +		   unsigned long *delay_on,
> +		   unsigned long *delay_off)
> +{
> +	del_timer_sync(&led_cdev->blink_timer);
> +
> +	if (led_cdev->blink_set &&
> +	    !led_cdev->blink_set(led_cdev, delay_on, delay_off))
> +		return;
> +
> +	/* blink with 1 Hz as default if nothing specified */
> +	if (!*delay_on && !*delay_off)
> +		*delay_on = *delay_off = 500;
> +
> +	led_set_software_blink(led_cdev, *delay_on, *delay_off);
> +}
> +EXPORT_SYMBOL(led_blink_set);
> +
> +void led_brightness_set(struct led_classdev *led_cdev,
> +			enum led_brightness brightness)
> +{
> +	led_stop_software_blink(led_cdev);
> +	led_cdev->brightness_set(led_cdev, brightness);
> +}
> +EXPORT_SYMBOL(led_brightness_set);




From rusty at rustcorp.com.au  Thu Mar  8 23:26:52 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 09 Mar 2012 14:56:52 +1030
Subject: [PATCH 5/8] ARM: KVM: make emulation functions return bool.
Message-ID: <1331267212.5775.rusty@rustcorp.com.au>


From: Rusty Russell <rusty at rustcorp.com.au>

Simplifies error handling into the parent: all errors mean
"can't emulate".

Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
---
 arch/arm/kvm/emulate.c |   44 ++++++++++++++++++++++----------------------
 1 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
index 88c6493..d386874 100644
--- a/arch/arm/kvm/emulate.c
+++ b/arch/arm/kvm/emulate.c
@@ -212,8 +212,8 @@ int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
  * @vcpu: The VCPU pointer
  * @p:    The coprocessor parameters struct pointer holding trap inst. details
  */
-static int emulate_cp15_c9_access(struct kvm_vcpu *vcpu,
-				  const struct coproc_params *p)
+static bool emulate_cp15_c9_access(struct kvm_vcpu *vcpu,
+				   const struct coproc_params *p)
 {
 	BUG_ON(p->CRn != 9);
 	BUG_ON(p->is_64bit);
@@ -223,7 +223,7 @@ static int emulate_cp15_c9_access(struct kvm_vcpu *vcpu,
 		u32 l2ctlr, ncores;
 
 		if (p->is_write)
-			return 0;
+			return true;
 
 		asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
 		l2ctlr &= ~(3 << 24);
@@ -231,13 +231,13 @@ static int emulate_cp15_c9_access(struct kvm_vcpu *vcpu,
 		l2ctlr |= (ncores & 3) << 24;
 		*vcpu_reg(vcpu, p->Rt1) = l2ctlr;
 
-		return 0;
+		return true;
 	}
 
 	/* hack alert!!! */
 	if (!p->is_write)
 		*vcpu_reg(vcpu, p->Rt1) = 0;
-	return 0;
+	return true;
 }
 
 /**
@@ -250,8 +250,8 @@ static int emulate_cp15_c9_access(struct kvm_vcpu *vcpu,
  * host/guest PRRR and NMRR memory remap registers and allow guest direct access
  * to these registers.
  */
-static int emulate_cp15_c10_access(struct kvm_vcpu *vcpu,
-				   const struct coproc_params *p)
+static bool emulate_cp15_c10_access(struct kvm_vcpu *vcpu,
+				    const struct coproc_params *p)
 {
 	BUG_ON(p->CRn != 10);
 	BUG_ON(p->is_64bit);
@@ -259,7 +259,7 @@ static int emulate_cp15_c10_access(struct kvm_vcpu *vcpu,
 	if ((p->CRm == 0 || p->CRm == 1 || p->CRm == 4 || p->CRm == 8) &&
 	    (p->Op2 <= 7)) {
 		/* TLB Lockdown operations - ignored */
-		return 0;
+		return true;
 	}
 
 	/*
@@ -270,15 +270,15 @@ static int emulate_cp15_c10_access(struct kvm_vcpu *vcpu,
 
 	if (p->CRm == 2 && p->Op1 == 0 && p->Op2 == 0) {
 		cp15_op(vcpu, p, c10_PRRR);
-		return 0;
+		return true;
 	}
 
 	if (p->CRm == 2 && p->Op1 == 0 && p->Op2 == 1) {
 		cp15_op(vcpu, p, c10_NMRR);
-		return 0;
+		return true;
 	}
 
-	return -EINVAL;
+	return false;
 }
 
 /**
@@ -292,8 +292,8 @@ static int emulate_cp15_c10_access(struct kvm_vcpu *vcpu,
  *
  * This may need to be refined.
  */
-static int emulate_cp15_c15_access(struct kvm_vcpu *vcpu,
-				   const struct coproc_params *p)
+static bool emulate_cp15_c15_access(struct kvm_vcpu *vcpu,
+				    const struct coproc_params *p)
 {
 	trace_kvm_emulate_cp15_imp(p->Op1, p->Rt1, p->CRn, p->CRm,
 				   p->Op2, p->is_write);
@@ -301,14 +301,14 @@ static int emulate_cp15_c15_access(struct kvm_vcpu *vcpu,
 	if (!p->is_write)
 		*vcpu_reg(vcpu, p->Rt1) = 0;
 
-	return 0;
+	return true;
 }
 
 static int emulate_cp15(struct kvm_vcpu *vcpu,
 			const struct coproc_params *params)
 {
 	unsigned long instr_len;
-	int ret;
+	bool ok;
 
 	/* So far no mrrc/mcrr accesses are emulated */
 	if (params->is_64bit)
@@ -316,31 +316,31 @@ static int emulate_cp15(struct kvm_vcpu *vcpu,
 
 	switch (params->CRn) {
 	case 9:
-		ret = emulate_cp15_c9_access(vcpu, params);
+		ok = emulate_cp15_c9_access(vcpu, params);
 		break;
 	case 10:
-		ret = emulate_cp15_c10_access(vcpu, params);
+		ok = emulate_cp15_c10_access(vcpu, params);
 		break;
 	case 15:
-		ret = emulate_cp15_c15_access(vcpu, params);
+		ok = emulate_cp15_c15_access(vcpu, params);
 		break;
 	default:
-		ret = -EINVAL;
+		ok = false;
 	}
 
-	if (ret != 0)
+	if (!ok)
 		goto unsupp_err_out;
 
 	/* Skip instruction, since it was emulated */
 	instr_len = ((vcpu->arch.hsr >> 25) & 1) ? 4 : 2;
 	*vcpu_reg(vcpu, 15) += instr_len;
 
-	return ret;
+	return 0;
 
 unsupp_err_out:	
 	kvm_err("Unsupported guest CP15 access at: %08x\n", vcpu->arch.regs.pc);
 	print_cp_instr(params);
-	return ret;
+	return -EINVAL;
 }
 
 /**



From rusty at rustcorp.com.au  Thu Mar  8 23:26:52 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 09 Mar 2012 14:56:52 +1030
Subject: [PATCH 3/8] ARM: KVM: make struct coproc_params arg const.
Message-ID: <1331267212.32474.rusty@rustcorp.com.au>


From: Rusty Russell <rusty at rustcorp.com.au>

Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
---
 arch/arm/kvm/emulate.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
index 108db38..87a1141 100644
--- a/arch/arm/kvm/emulate.c
+++ b/arch/arm/kvm/emulate.c
@@ -165,7 +165,7 @@ struct coproc_params {
 	bool is_write;
 };
 
-static void cp15_op(struct kvm_vcpu *vcpu, struct coproc_params *p,
+static void cp15_op(struct kvm_vcpu *vcpu, const struct coproc_params *p,
 			   enum cp15_regs cp15_reg)
 {
 	if (p->is_write)
@@ -174,7 +174,7 @@ static void cp15_op(struct kvm_vcpu *vcpu, struct coproc_params *p,
 		*vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[cp15_reg];
 }
 
-static void print_cp_instr(struct coproc_params *p)
+static void print_cp_instr(const struct coproc_params *p)
 {
 	if (p->is_64bit) {
 		kvm_debug("%s\tp15, %lu, r%lu, r%lu, c%lu",
@@ -213,7 +213,7 @@ int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
  * @p:    The coprocessor parameters struct pointer holding trap inst. details
  */
 static int emulate_cp15_c9_access(struct kvm_vcpu *vcpu,
-				  struct coproc_params *p)
+				  const struct coproc_params *p)
 {
 	BUG_ON(p->CRn != 9);
 	BUG_ON(p->is_64bit);
@@ -251,7 +251,7 @@ static int emulate_cp15_c9_access(struct kvm_vcpu *vcpu,
  * to these registers.
  */
 static int emulate_cp15_c10_access(struct kvm_vcpu *vcpu,
-				   struct coproc_params *p)
+				   const struct coproc_params *p)
 {
 	BUG_ON(p->CRn != 10);
 	BUG_ON(p->is_64bit);
@@ -293,7 +293,7 @@ static int emulate_cp15_c10_access(struct kvm_vcpu *vcpu,
  * This may need to be refined.
  */
 static int emulate_cp15_c15_access(struct kvm_vcpu *vcpu,
-				   struct coproc_params *p)
+				   const struct coproc_params *p)
 {
 	trace_kvm_emulate_cp15_imp(p->Op1, p->Rt1, p->CRn, p->CRm,
 				   p->Op2, p->is_write);



From olof at lixom.net  Sat Mar 10 16:18:47 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 13:18:47 -0800
Subject: [GIT PULL] mach/io.h clean-up and removal
In-Reply-To: <4F5BA82C.1040400@gmail.com>
References: <4F58DD30.4060704@gmail.com>
 <CAOesGMi1pD+1BEkXSGDA8k6UC2DD65QYt3Z_59McFkgWrdqehQ@mail.gmail.com>
 <4F5BA82C.1040400@gmail.com>
Message-ID: <CAOesGMjdErqMaMjH9DUirWn9CXbooHab-CJ-0k+qnZ6Zcy1XQw@mail.gmail.com>

On Sat, Mar 10, 2012 at 11:14 AM, Rob Herring <robherring2 at gmail.com> wrote:
> On 03/10/2012 12:20 PM, Olof Johansson wrote:
>> Hi,
>>
>> On Thu, Mar 8, 2012 at 8:24 AM, Rob Herring <robherring2 at gmail.com> wrote:
>>> Arnd, Olof,
>>>
>>> Please pull the mach/io.h cleanup series for 3.4. This does not include
>>> the PCI i/o mapping changes. In hopes of testing, I'll wait until 3.5
>>> for that. Although, it seems no one has devices with i/o.
>>>
>>> I'm sending this to you rather than Russell as it is based on at91 and
>>> omap cleanup branches in arm-soc tree.
>>>
>>> Rob
>>>
>>> The following changes since commit d50673ed97a7ce609cf62bcd40c57517ada31806:
>>>
>>> ?Merge remote-tracking branch 'arm-soc/at91/base2+cleanup' into
>>> cleanup-base (2012-03-04 22:00:46 -0600)
>>>
>>> are available in the git repository at:
>>>
>>> ?git://sources.calxeda.com/kernel/linux.git io-cleanup-for-3.4
>>
>> I've pulled this into next/cleanup2. Nice diffstat!
>>
>
> Actually, Arnd just found some abusers of __io() that I need to fix
> first. They are using __io() to cast defines to a void __iomem * ptr. I
> should have something out for review soon. So please drop this and I'll
> send a new pull request.


Rats. I saw the discussion but didn't think of it when I was doing
pulls this morning.

I'll revert it in for-next but keep it in next/cleanup2, so please
just do an incremental pull request for additional patches.


Thanks,

-Olof


From rjw at sisk.pl  Sat Mar 10 16:09:22 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Sat, 10 Mar 2012 22:09:22 +0100
Subject: [GIT PULL 2/4] Samsung devel-pd for v3.4
In-Reply-To: <CAOesGMjff3gVNJQ5FpJuSf+uvVDW8k22b+Xcikot-isM-4-6iw@mail.gmail.com>
References: <4F5B7C81.6080301@samsung.com>
 <CAOesGMjff3gVNJQ5FpJuSf+uvVDW8k22b+Xcikot-isM-4-6iw@mail.gmail.com>
Message-ID: <201203102209.22451.rjw@sisk.pl>

Hi,

On Saturday, March 10, 2012, Olof Johansson wrote:
> Hi Rafael,
> 
> The below series contains two patches that have been sent to you, and
> that are sitting in the pm-domains branch.
> 
> Two questions before I pull this into arm-soc:
> 
> 1) Are you 100% sure this will be submitted to 3.4? And if so, will
> you send it early during the merge window?

Yes and yes.

> 2) Are you 100% sure you will not rebase the branch into which you
> pulled the v3.4-for-rafael branch?

Yes, I am.

> I am asking because if we pull this in, and you rebase between now and
> when it's sent in, we're risking merge conflicts that will be painful
> to resolve. We've been bitten by that from other dependencies in the
> past so we're being careful.

Sure, I understand that.

As a general rule, topic braches in my tree whose names start with pm- are
never rebased (exactly for this reason).

Thanks,
Rafael


> On Sat, Mar 10, 2012 at 8:08 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > Hi Arnd, Olof,
> >
> > This is Generic Power Domain patches for EXYNOS. Basically, Thomas' patches,
> > adding support Generic Power Domain patches are in Rafael's tree,
> > linux-pm/linux-next and see below merge commit.
> > http://git.kernel.org/?p=linux/kernel/git/rafael/linux-pm.git;a=commit;h=dcaad77a8074b6de58e745546bc543d5538404f2
> > And this adds hooking up G2D and JPEG to Generic PD.
> >
> > Please pull and here is my preferred resolution when merge this after
> > next/board-samsung.
> >
> > diff --cc arch/arm/mach-exynos/mach-universal_c210.c
> > index 3663aee,0262417..0b944eb
> > --- a/arch/arm/mach-exynos/mach-universal_c210.c
> > +++ b/arch/arm/mach-exynos/mach-universal_c210.c
> > @@@ -1053,10 -981,6 +1052,7 @@@ static struct platform_device *universa
> >        &s5p_device_mfc,
> >        &s5p_device_mfc_l,
> >        &s5p_device_mfc_r,
> > -       &exynos4_device_pd[PD_MFC],
> > -       &exynos4_device_pd[PD_LCD0],
> > -       &exynos4_device_pd[PD_CAM],
> >  +      &cam_vt_dio_fixed_reg_dev,
> >        &cam_i_core_fixed_reg_dev,
> >        &cam_s_if_fixed_reg_dev,
> >        &s5p_device_fimc_md,
> >
> > If any problems, please kindly let me know.
> >
> > Thanks.
> >
> > Best regards,
> > Kgene.
> > --
> > Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> > SW Solution Development Team, Samsung Electronics Co., Ltd.
> >
> > The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
> >
> >  Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)
> >
> > are available in the git repository at:
> >  git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> > next/devel-samsung-pd
> >
> > Sachin Kamat (2):
> >      ARM: EXYNOS: Hook up G2D PD to generic PD infrastructure
> >      ARM: EXYNOS: Hook up JPEG PD to generic PD infrastructure
> >
> > Thomas Abraham (2):
> >      PM / Domains: Add OF support
> >      ARM: EXYNOS: Hook up power domains to generic power domain
> > infrastructure
> >
> >  .../bindings/arm/exynos/power_domain.txt           |   21 ++
> >  arch/arm/mach-exynos/Kconfig                       |   10 +-
> >  arch/arm/mach-exynos/Makefile                      |    2 +-
> >  arch/arm/mach-exynos/dev-pd.c                      |  139 --------------
> >  arch/arm/mach-exynos/mach-nuri.c                   |   11 -
> >  arch/arm/mach-exynos/mach-origen.c                 |   14 --
> >  arch/arm/mach-exynos/mach-smdkv310.c               |   12 --
> >  arch/arm/mach-exynos/mach-universal_c210.c         |   17 --
> >  arch/arm/mach-exynos/pm_domains.c                  |  201
> > ++++++++++++++++++++
> >  drivers/base/power/domain.c                        |   32 +++
> >  include/linux/pm_domain.h                          |   12 ++
> >  11 files changed, 268 insertions(+), 203 deletions(-)
> >  create mode 100644
> > Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> >  delete mode 100644 arch/arm/mach-exynos/dev-pd.c
> >  create mode 100644 arch/arm/mach-exynos/pm_domains.c
> 
> 



From shawn.guo at linaro.org  Fri Mar  9 03:03:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 9 Mar 2012 16:03:26 +0800
Subject: [RFC] i.MX: drop secondary clocks
In-Reply-To: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
References: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120309080324.GN2499@S2101-09.ap.freescale.net>

On Thu, Mar 08, 2012 at 10:42:27PM +0100, Sascha Hauer wrote:
> Hi All,
> 
> On i.MX we currently have grouped clocks, also known as secondary clocks.
> These are clocks that get enabled when the primary clock gets enabled.  This
> doesn't integrate well into the generic clock framework. Also we often return
> the rate of one clock and really enable/disable another clock. I plan to get
> rid of these clocks by exposing the individual clocks to the drivers. The
> following is meant as an example how this can be done. I have a more complete
> series internally but this conflicts with Richards clk_prepare series.
> 
> Thanks to the nature of clk_get we can simply clk_get the individual clocks in
> the drivers and the current clock implementation will always return the one
> with con_id = NULL. Then with the generic clk implementation the drivers will
> finally get the individual clocks.
> 
> So unless there are objections I will follow up on this after the next merge
> window.
> 
So glad to see you are getting rid of this nasty imx secondary clock.
I agree this is the way to go.

-- 
Regards,
Shawn


From hector.oron at gmail.com  Sun Mar 11 08:33:47 2012
From: hector.oron at gmail.com (Hector Oron)
Date: Sun, 11 Mar 2012 13:33:47 +0100
Subject: [PATCH] efikamx: match machine descriptions with legacy
In-Reply-To: <1329779368-27878-1-git-send-email-hector.oron@gmail.com>
References: <1329779368-27878-1-git-send-email-hector.oron@gmail.com>
Message-ID: <CAODfWeE86mUf17CAZ+aa1bKxX4Toq9ogm01tDEMVYcnqu96LAg@mail.gmail.com>

Hello,

2012/2/21 Hector Oron <hector.oron at gmail.com>:
> ?Rename machine descriptions to match legacy descriptions distributed by
> ?manufacturer BSP. This way distributions can do clean upgrades from
> ?userspace scripts which check for these values to differentiate platforms
> ?with single kernel binaries.
>
> Signed-off-by: Hector Oron <hector.oron at gmail.com>
> Acked-by: Matt Sealey <matt at genesi-usa.com>
> ---
> ?arch/arm/mach-mx5/board-mx51_efikamx.c | ? ?3 +--
> ?arch/arm/mach-mx5/board-mx51_efikasb.c | ? ?2 +-
> ?2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
> index 3a5ed2d..fbfccc7 100644
> --- a/arch/arm/mach-mx5/board-mx51_efikamx.c
> +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
> @@ -283,8 +283,7 @@ static struct sys_timer mx51_efikamx_timer = {
> ? ? ? ?.init = mx51_efikamx_timer_init,
> ?};
>
> -MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
> - ? ? ? /* Maintainer: Amit Kucheria <amit.kucheria at linaro.org> */
> +MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)")
> ? ? ? ?.atag_offset = 0x100,
> ? ? ? ?.map_io = mx51_map_io,
> ? ? ? ?.init_early = imx51_init_early,
> diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
> index 4baf05c..dedbca5 100644
> --- a/arch/arm/mach-mx5/board-mx51_efikasb.c
> +++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
> @@ -483,7 +483,7 @@ static struct sys_timer mx51_efikasb_timer = {
> ? ? ? ?.init ? = mx51_efikasb_timer_init,
> ?};
>
> -MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
> +MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)")
> ? ? ? ?.atag_offset = 0x100,
> ? ? ? ?.map_io = mx51_map_io,
> ? ? ? ?.init_early = imx51_init_early,
> --
> 1.7.9
>

Ping!
I dont see the patch being applied. Is there any problem with it?

Cheers,
-- 
?H?ctor Or?n ?-.. . -... .. .- -. ? -.. . ...- . .-.. --- .--. . .-.


From lost.distance at yahoo.com  Sun Mar 11 09:23:42 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Sun, 11 Mar 2012 13:23:42 +0000 (GMT)
Subject: [PATCH v2] pxa/hx4700: Reduce sleep mode battery discharge by 35%
Message-ID: <1331472222.71907.YahooMailClassic@web29003.mail.ird.yahoo.com>

Drive the two Bluetooth UART output GPIOs (GPIO43_BTUART_TXD, GPIO45_BTUART_RTS)
LOW during sleep mode instead of HIGH. This reduces sleep mode battery discharge
from approximately 46 mA to approximately 30 mA.

Signed-off-by: Oliver Winker <oliver at oli1170.net>
Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
---

V2:
Corrected nomenclature.
Added GPIO43_BTUART_TXD_LPM_LOW and GPIO45_BTUART_RTS_LPM_LOW to mfp-pxa27x.h

diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c
--- clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-04 01:08:09.000000000 +0000
+++ linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-11 12:30:29.799567611 +0000
@@ -97,9 +97,9 @@ static unsigned long hx4700_pin_config[]
 
 	/* BTUART */
 	GPIO42_BTUART_RXD,
-	GPIO43_BTUART_TXD,
+	GPIO43_BTUART_TXD_LPM_LOW,
 	GPIO44_BTUART_CTS,
-	GPIO45_BTUART_RTS,
+	GPIO45_BTUART_RTS_LPM_LOW,
 
 	/* PWM 1 (Backlight) */
 	GPIO17_PWM1_OUT,
diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h linux-3.3-rc6/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
--- clean-3.3-rc6/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h	2012-03-04 01:08:09.000000000 +0000
+++ linux-3.3-rc6/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h	2012-03-11 12:32:23.728285708 +0000
@@ -158,7 +158,9 @@
 #define GPIO44_BTUART_CTS	MFP_CFG_IN(GPIO44, AF1)
 #define GPIO42_BTUART_RXD	MFP_CFG_IN(GPIO42, AF1)
 #define GPIO45_BTUART_RTS	MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
+#define GPIO45_BTUART_RTS_LPM_LOW	MFP_CFG_OUT(GPIO45, AF2, DRIVE_LOW)
 #define GPIO43_BTUART_TXD	MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
+#define GPIO43_BTUART_TXD_LPM_LOW	MFP_CFG_OUT(GPIO43, AF2, DRIVE_LOW)
 
 /* STUART */
 #define GPIO46_STUART_RXD	MFP_CFG_IN(GPIO46, AF2)



From lost.distance at yahoo.com  Fri Mar  9 09:56:49 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 9 Mar 2012 14:56:49 +0000 (GMT)
Subject: [PATCH 2/2 v5] pxa/hx4700: Add PCMCIA/CF support
Message-ID: <1331305009.57620.YahooMailClassic@web29018.mail.ird.yahoo.com>

Add PCMCIA/CF support for the HP iPAQ hx4700. Underlying support is provided by
the pcmcia/pxa2xx_hx4700 platform_device implementation which hooks into the
existing pxa2xx-pcmcia driver.

Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
---

V5:
Separated removal of old pcmcia platform_device structure (which is unrelated,
and whose patch hunks fail to apply against linux-3.3-rc6) into a new patch.
Rebased to linux-3.3-rc6.

diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c
--- clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-04 01:08:09.000000000 +0000
+++ linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-09 13:58:39.421923593 +0000
@@ -226,7 +226,6 @@ static u16 asic3_gpio_config[] = {
 	ASIC3_GPIOC0_LED0,		/* red */
 	ASIC3_GPIOC1_LED1,		/* green */
 	ASIC3_GPIOC2_LED2,		/* blue */
-	ASIC3_GPIOC4_CF_nCD,
 	ASIC3_GPIOC5_nCIOW,
 	ASIC3_GPIOC6_nCIOR,
 	ASIC3_GPIOC7_nPCE_1,
@@ -240,6 +239,7 @@ static u16 asic3_gpio_config[] = {
 	ASIC3_GPIOC15_nPIOR,
 
 	/* GPIOD: input GPIOs, CF */
+	ASIC3_GPIOD4_CF_nCD,
 	ASIC3_GPIOD11_nCIOIS16,
 	ASIC3_GPIOD12_nCWAIT,
 	ASIC3_GPIOD15_nPIOW,
diff -uprN clean-3.3-rc6/include/linux/mfd/asic3.h linux-3.3-rc6/include/linux/mfd/asic3.h
--- clean-3.3-rc6/include/linux/mfd/asic3.h	2012-03-04 01:08:09.000000000 +0000
+++ linux-3.3-rc6/include/linux/mfd/asic3.h	2012-03-09 13:58:39.421923593 +0000
@@ -138,6 +138,7 @@ struct asic3_platform_data {
 #define ASIC3_GPIOC13_nPWAIT		ASIC3_CONFIG_GPIO(45, 1, 1, 0)
 #define ASIC3_GPIOC14_nPIOIS16		ASIC3_CONFIG_GPIO(46, 1, 1, 0)
 #define ASIC3_GPIOC15_nPIOR		ASIC3_CONFIG_GPIO(47, 1, 0, 0)
+#define ASIC3_GPIOD4_CF_nCD		ASIC3_CONFIG_GPIO(52, 1, 0, 0)
 #define ASIC3_GPIOD11_nCIOIS16		ASIC3_CONFIG_GPIO(59, 1, 0, 0)
 #define ASIC3_GPIOD12_nCWAIT		ASIC3_CONFIG_GPIO(60, 1, 0, 0)
 #define ASIC3_GPIOD15_nPIOW		ASIC3_CONFIG_GPIO(63, 1, 0, 0)



From pullip.cho at samsung.com  Fri Mar  9 07:15:01 2012
From: pullip.cho at samsung.com (Cho KyongHo)
Date: Fri, 09 Mar 2012 21:15:01 +0900
Subject: [PATCH v11 1/3] S5P: SYSMMU: Remove System MMU device driver
Message-ID: <017801ccfdee$40b18000$c2148000$%cho@samsung.com>

This patch removes System MMU device driver from arm/plat-s5p tree
for transition to implement IOMMU driver.
Although controlling System MMU in this removing driver
is similar to the new IOMMU driver in the following patch,
the new one is almost rewrite of this driver and there is no
benefit to moving the driver file from arch/arm/ to drivers/iommu.

Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
---
 arch/arm/plat-s5p/Kconfig                   |    8 -
 arch/arm/plat-s5p/Makefile                  |    1 -
 arch/arm/plat-s5p/sysmmu.c                  |  313 ---------------------------
 arch/arm/plat-samsung/include/plat/devs.h   |    1 -
 arch/arm/plat-samsung/include/plat/sysmmu.h |   95 --------
 5 files changed, 0 insertions(+), 418 deletions(-)
 delete mode 100644 arch/arm/plat-s5p/sysmmu.c
 delete mode 100644 arch/arm/plat-samsung/include/plat/sysmmu.h

diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 8490695..9451ed4 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -50,14 +50,6 @@ config S5P_PM
 	  Common code for power management support on S5P and newer SoCs
 	  Note: Do not select this for S5P6440 and S5P6450.
 
-comment "System MMU"
-
-config S5P_SYSTEM_MMU
-	bool "S5P SYSTEM MMU"
-	depends on ARCH_EXYNOS4
-	help
-	  Say Y here if you want to enable System MMU
-
 config S5P_SLEEP
 	bool
 	help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 4bd8241..4953d50 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -16,7 +16,6 @@ obj-y				+= clock.o
 obj-y				+= irq.o
 obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
 obj-$(CONFIG_S5P_GPIO_INT)	+= irq-gpioint.o
-obj-$(CONFIG_S5P_SYSTEM_MMU)	+= sysmmu.o
 obj-$(CONFIG_S5P_PM)		+= pm.o irq-pm.o
 obj-$(CONFIG_S5P_SLEEP)		+= sleep.o
 obj-$(CONFIG_S5P_HRT) 		+= s5p-time.o
diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c
deleted file mode 100644
index c8bec9c..0000000
--- a/arch/arm/plat-s5p/sysmmu.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/* linux/arch/arm/plat-s5p/sysmmu.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/export.h>
-
-#include <asm/pgtable.h>
-
-#include <mach/map.h>
-#include <mach/regs-sysmmu.h>
-#include <plat/sysmmu.h>
-
-#define CTRL_ENABLE	0x5
-#define CTRL_BLOCK	0x7
-#define CTRL_DISABLE	0x0
-
-static struct device *dev;
-
-static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
-	S5P_PAGE_FAULT_ADDR,
-	S5P_AR_FAULT_ADDR,
-	S5P_AW_FAULT_ADDR,
-	S5P_DEFAULT_SLAVE_ADDR,
-	S5P_AR_FAULT_ADDR,
-	S5P_AR_FAULT_ADDR,
-	S5P_AW_FAULT_ADDR,
-	S5P_AW_FAULT_ADDR
-};
-
-static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
-	"PAGE FAULT",
-	"AR MULTI-HIT FAULT",
-	"AW MULTI-HIT FAULT",
-	"BUS ERROR",
-	"AR SECURITY PROTECTION FAULT",
-	"AR ACCESS PROTECTION FAULT",
-	"AW SECURITY PROTECTION FAULT",
-	"AW ACCESS PROTECTION FAULT"
-};
-
-static int (*fault_handlers[S5P_SYSMMU_TOTAL_IPNUM])(
-		enum S5P_SYSMMU_INTERRUPT_TYPE itype,
-		unsigned long pgtable_base,
-		unsigned long fault_addr);
-
-/*
- * If adjacent 2 bits are true, the system MMU is enabled.
- * The system MMU is disabled, otherwise.
- */
-static unsigned long sysmmu_states;
-
-static inline void set_sysmmu_active(sysmmu_ips ips)
-{
-	sysmmu_states |= 3 << (ips * 2);
-}
-
-static inline void set_sysmmu_inactive(sysmmu_ips ips)
-{
-	sysmmu_states &= ~(3 << (ips * 2));
-}
-
-static inline int is_sysmmu_active(sysmmu_ips ips)
-{
-	return sysmmu_states & (3 << (ips * 2));
-}
-
-static void __iomem *sysmmusfrs[S5P_SYSMMU_TOTAL_IPNUM];
-
-static inline void sysmmu_block(sysmmu_ips ips)
-{
-	__raw_writel(CTRL_BLOCK, sysmmusfrs[ips] + S5P_MMU_CTRL);
-	dev_dbg(dev, "%s is blocked.\n", sysmmu_ips_name[ips]);
-}
-
-static inline void sysmmu_unblock(sysmmu_ips ips)
-{
-	__raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
-	dev_dbg(dev, "%s is unblocked.\n", sysmmu_ips_name[ips]);
-}
-
-static inline void __sysmmu_tlb_invalidate(sysmmu_ips ips)
-{
-	__raw_writel(0x1, sysmmusfrs[ips] + S5P_MMU_FLUSH);
-	dev_dbg(dev, "TLB of %s is invalidated.\n", sysmmu_ips_name[ips]);
-}
-
-static inline void __sysmmu_set_ptbase(sysmmu_ips ips, unsigned long pgd)
-{
-	if (unlikely(pgd == 0)) {
-		pgd = (unsigned long)ZERO_PAGE(0);
-		__raw_writel(0x20, sysmmusfrs[ips] + S5P_MMU_CFG); /* 4KB LV1 */
-	} else {
-		__raw_writel(0x0, sysmmusfrs[ips] + S5P_MMU_CFG); /* 16KB LV1 */
-	}
-
-	__raw_writel(pgd, sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
-
-	dev_dbg(dev, "Page table base of %s is initialized with 0x%08lX.\n",
-						sysmmu_ips_name[ips], pgd);
-	__sysmmu_tlb_invalidate(ips);
-}
-
-void sysmmu_set_fault_handler(sysmmu_ips ips,
-			int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
-					unsigned long pgtable_base,
-					unsigned long fault_addr))
-{
-	BUG_ON(!((ips >= SYSMMU_MDMA) && (ips < S5P_SYSMMU_TOTAL_IPNUM)));
-	fault_handlers[ips] = handler;
-}
-
-static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id)
-{
-	/* SYSMMU is in blocked when interrupt occurred. */
-	unsigned long base = 0;
-	sysmmu_ips ips = (sysmmu_ips)dev_id;
-	enum S5P_SYSMMU_INTERRUPT_TYPE itype;
-
-	itype = (enum S5P_SYSMMU_INTERRUPT_TYPE)
-		__ffs(__raw_readl(sysmmusfrs[ips] + S5P_INT_STATUS));
-
-	BUG_ON(!((itype >= 0) && (itype < 8)));
-
-	dev_alert(dev, "%s occurred by %s.\n", sysmmu_fault_name[itype],
-							sysmmu_ips_name[ips]);
-
-	if (fault_handlers[ips]) {
-		unsigned long addr;
-
-		base = __raw_readl(sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
-		addr = __raw_readl(sysmmusfrs[ips] + fault_reg_offset[itype]);
-
-		if (fault_handlers[ips](itype, base, addr)) {
-			__raw_writel(1 << itype,
-					sysmmusfrs[ips] + S5P_INT_CLEAR);
-			dev_notice(dev, "%s from %s is resolved."
-					" Retrying translation.\n",
-				sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
-		} else {
-			base = 0;
-		}
-	}
-
-	sysmmu_unblock(ips);
-
-	if (!base)
-		dev_notice(dev, "%s from %s is not handled.\n",
-			sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
-
-	return IRQ_HANDLED;
-}
-
-void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd)
-{
-	if (is_sysmmu_active(ips)) {
-		sysmmu_block(ips);
-		__sysmmu_set_ptbase(ips, pgd);
-		sysmmu_unblock(ips);
-	} else {
-		dev_dbg(dev, "%s is disabled. "
-			"Skipping initializing page table base.\n",
-						sysmmu_ips_name[ips]);
-	}
-}
-
-void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd)
-{
-	if (!is_sysmmu_active(ips)) {
-		sysmmu_clk_enable(ips);
-
-		__sysmmu_set_ptbase(ips, pgd);
-
-		__raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
-
-		set_sysmmu_active(ips);
-		dev_dbg(dev, "%s is enabled.\n", sysmmu_ips_name[ips]);
-	} else {
-		dev_dbg(dev, "%s is already enabled.\n", sysmmu_ips_name[ips]);
-	}
-}
-
-void s5p_sysmmu_disable(sysmmu_ips ips)
-{
-	if (is_sysmmu_active(ips)) {
-		__raw_writel(CTRL_DISABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
-		set_sysmmu_inactive(ips);
-		sysmmu_clk_disable(ips);
-		dev_dbg(dev, "%s is disabled.\n", sysmmu_ips_name[ips]);
-	} else {
-		dev_dbg(dev, "%s is already disabled.\n", sysmmu_ips_name[ips]);
-	}
-}
-
-void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips)
-{
-	if (is_sysmmu_active(ips)) {
-		sysmmu_block(ips);
-		__sysmmu_tlb_invalidate(ips);
-		sysmmu_unblock(ips);
-	} else {
-		dev_dbg(dev, "%s is disabled. "
-			"Skipping invalidating TLB.\n", sysmmu_ips_name[ips]);
-	}
-}
-
-static int s5p_sysmmu_probe(struct platform_device *pdev)
-{
-	int i, ret;
-	struct resource *res, *mem;
-
-	dev = &pdev->dev;
-
-	for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
-		int irq;
-
-		sysmmu_clk_init(dev, i);
-		sysmmu_clk_disable(i);
-
-		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-		if (!res) {
-			dev_err(dev, "Failed to get the resource of %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENODEV;
-			goto err_res;
-		}
-
-		mem = request_mem_region(res->start, resource_size(res),
-					 pdev->name);
-		if (!mem) {
-			dev_err(dev, "Failed to request the memory region of %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -EBUSY;
-			goto err_res;
-		}
-
-		sysmmusfrs[i] = ioremap(res->start, resource_size(res));
-		if (!sysmmusfrs[i]) {
-			dev_err(dev, "Failed to ioremap() for %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENXIO;
-			goto err_reg;
-		}
-
-		irq = platform_get_irq(pdev, i);
-		if (irq <= 0) {
-			dev_err(dev, "Failed to get the IRQ resource of %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENOENT;
-			goto err_map;
-		}
-
-		if (request_irq(irq, s5p_sysmmu_irq, IRQF_DISABLED,
-						pdev->name, (void *)i)) {
-			dev_err(dev, "Failed to request IRQ for %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENOENT;
-			goto err_map;
-		}
-	}
-
-	return 0;
-
-err_map:
-	iounmap(sysmmusfrs[i]);
-err_reg:
-	release_mem_region(mem->start, resource_size(mem));
-err_res:
-	return ret;
-}
-
-static int s5p_sysmmu_remove(struct platform_device *pdev)
-{
-	return 0;
-}
-int s5p_sysmmu_runtime_suspend(struct device *dev)
-{
-	return 0;
-}
-
-int s5p_sysmmu_runtime_resume(struct device *dev)
-{
-	return 0;
-}
-
-const struct dev_pm_ops s5p_sysmmu_pm_ops = {
-	.runtime_suspend	= s5p_sysmmu_runtime_suspend,
-	.runtime_resume		= s5p_sysmmu_runtime_resume,
-};
-
-static struct platform_driver s5p_sysmmu_driver = {
-	.probe		= s5p_sysmmu_probe,
-	.remove		= s5p_sysmmu_remove,
-	.driver		= {
-		.owner		= THIS_MODULE,
-		.name		= "s5p-sysmmu",
-		.pm		= &s5p_sysmmu_pm_ops,
-	}
-};
-
-static int __init s5p_sysmmu_init(void)
-{
-	return platform_driver_register(&s5p_sysmmu_driver);
-}
-arch_initcall(s5p_sysmmu_init);
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 2dd5267..a604cb8 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -132,7 +132,6 @@ extern struct platform_device exynos4_device_pcm1;
 extern struct platform_device exynos4_device_pcm2;
 extern struct platform_device exynos4_device_pd[];
 extern struct platform_device exynos4_device_spdif;
-extern struct platform_device exynos4_device_sysmmu;
 
 extern struct platform_device samsung_asoc_dma;
 extern struct platform_device samsung_asoc_idma;
diff --git a/arch/arm/plat-samsung/include/plat/sysmmu.h b/arch/arm/plat-samsung/include/plat/sysmmu.h
deleted file mode 100644
index 5fe8ee0..0000000
--- a/arch/arm/plat-samsung/include/plat/sysmmu.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * Samsung System MMU driver for S5P platform
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __PLAT_SAMSUNG_SYSMMU_H
-#define __PLAT_SAMSUNG_SYSMMU_H __FILE__
-
-enum S5P_SYSMMU_INTERRUPT_TYPE {
-	SYSMMU_PAGEFAULT,
-	SYSMMU_AR_MULTIHIT,
-	SYSMMU_AW_MULTIHIT,
-	SYSMMU_BUSERROR,
-	SYSMMU_AR_SECURITY,
-	SYSMMU_AR_ACCESS,
-	SYSMMU_AW_SECURITY,
-	SYSMMU_AW_PROTECTION, /* 7 */
-	SYSMMU_FAULTS_NUM
-};
-
-#ifdef CONFIG_S5P_SYSTEM_MMU
-
-#include <mach/sysmmu.h>
-
-/**
- * s5p_sysmmu_enable() - enable system mmu of ip
- * @ips: The ip connected system mmu.
- * #pgd: Base physical address of the 1st level page table
- *
- * This function enable system mmu to transfer address
- * from virtual address to physical address
- */
-void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd);
-
-/**
- * s5p_sysmmu_disable() - disable sysmmu mmu of ip
- * @ips: The ip connected system mmu.
- *
- * This function disable system mmu to transfer address
- * from virtual address to physical address
- */
-void s5p_sysmmu_disable(sysmmu_ips ips);
-
-/**
- * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
- * @ips: The ip connected system mmu.
- * @pgd: The page table base address.
- *
- * This function set page table base address
- * When system mmu transfer address from virtaul address to physical address,
- * system mmu refer address information from page table
- */
-void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
-
-/**
- * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
- * @ips: The ip connected system mmu.
- *
- * This function flush all TLB entry in system mmu
- */
-void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
-
-/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs
- * @itype: type of fault.
- * @pgtable_base: the physical address of page table base. This is 0 if @ips is
- *               SYSMMU_BUSERROR.
- * @fault_addr: the device (virtual) address that the System MMU tried to
- *             translated. This is 0 if @ips is SYSMMU_BUSERROR.
- * Called when interrupt occurred by the System MMUs
- * The device drivers of peripheral devices that has a System MMU can implement
- * a fault handler to resolve address translation fault by System MMU.
- * The meanings of return value and parameters are described below.
-
- * return value: non-zero if the fault is correctly resolved.
- *         zero if the fault is not handled.
- */
-void s5p_sysmmu_set_fault_handler(sysmmu_ips ips,
-			int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
-					unsigned long pgtable_base,
-					unsigned long fault_addr));
-#else
-#define s5p_sysmmu_enable(ips, pgd) do { } while (0)
-#define s5p_sysmmu_disable(ips) do { } while (0)
-#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0)
-#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0)
-#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0)
-#endif
-#endif /* __ASM_PLAT_SYSMMU_H */
-- 
1.7.1



From bryan.wu at canonical.com  Sun Mar 11 03:45:23 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Sun, 11 Mar 2012 15:45:23 +0800
Subject: [PATCH 1/3] led-class: change back LEDS_CLASS to tristate instead
 of bool
In-Reply-To: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <CAK5ve-+KxyQ4RgftyHZ5PLYSvbxWG263f1d6WXty0RO6khYTrA@mail.gmail.com>

Richard,

How about this patch we discussed before? Thanks,

-Bryan

On Thu, Mar 8, 2012 at 5:11 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
> After moving some core functions to led-core.c, led-class.c can be built as
> module again.
>
> Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
> ---
> ?drivers/leds/Kconfig ? ? | ? ?2 +-
> ?drivers/leds/led-class.c | ? 70 ----------------------------------------------
> ?drivers/leds/led-core.c ?| ? 70 ++++++++++++++++++++++++++++++++++++++++++++++
> ?3 files changed, 71 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
> index 9ca28fc..3f17f0d 100644
> --- a/drivers/leds/Kconfig
> +++ b/drivers/leds/Kconfig
> @@ -17,7 +17,7 @@ menuconfig NEW_LEDS
> ?if NEW_LEDS
>
> ?config LEDS_CLASS
> - ? ? ? bool "LED Class Support"
> + ? ? ? tristate "LED Class Support"
> ? ? ? ?help
> ? ? ? ? ?This option enables the led sysfs class in /sys/class/leds. ?You'll
> ? ? ? ? ?need this to do anything useful with LEDs. ?If unsure, say N.
> diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
> index 0c8739c..5bff843 100644
> --- a/drivers/leds/led-class.c
> +++ b/drivers/leds/led-class.c
> @@ -110,50 +110,6 @@ static void led_timer_function(unsigned long data)
> ? ? ? ?mod_timer(&led_cdev->blink_timer, jiffies + msecs_to_jiffies(delay));
> ?}
>
> -static void led_stop_software_blink(struct led_classdev *led_cdev)
> -{
> - ? ? ? /* deactivate previous settings */
> - ? ? ? del_timer_sync(&led_cdev->blink_timer);
> - ? ? ? led_cdev->blink_delay_on = 0;
> - ? ? ? led_cdev->blink_delay_off = 0;
> -}
> -
> -static void led_set_software_blink(struct led_classdev *led_cdev,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long delay_on,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long delay_off)
> -{
> - ? ? ? int current_brightness;
> -
> - ? ? ? current_brightness = led_get_brightness(led_cdev);
> - ? ? ? if (current_brightness)
> - ? ? ? ? ? ? ? led_cdev->blink_brightness = current_brightness;
> - ? ? ? if (!led_cdev->blink_brightness)
> - ? ? ? ? ? ? ? led_cdev->blink_brightness = led_cdev->max_brightness;
> -
> - ? ? ? if (led_get_trigger_data(led_cdev) &&
> - ? ? ? ? ? delay_on == led_cdev->blink_delay_on &&
> - ? ? ? ? ? delay_off == led_cdev->blink_delay_off)
> - ? ? ? ? ? ? ? return;
> -
> - ? ? ? led_stop_software_blink(led_cdev);
> -
> - ? ? ? led_cdev->blink_delay_on = delay_on;
> - ? ? ? led_cdev->blink_delay_off = delay_off;
> -
> - ? ? ? /* never on - don't blink */
> - ? ? ? if (!delay_on)
> - ? ? ? ? ? ? ? return;
> -
> - ? ? ? /* never off - just set to brightness */
> - ? ? ? if (!delay_off) {
> - ? ? ? ? ? ? ? led_set_brightness(led_cdev, led_cdev->blink_brightness);
> - ? ? ? ? ? ? ? return;
> - ? ? ? }
> -
> - ? ? ? mod_timer(&led_cdev->blink_timer, jiffies + 1);
> -}
> -
> -
> ?/**
> ?* led_classdev_suspend - suspend an led_classdev.
> ?* @led_cdev: the led_classdev to suspend.
> @@ -262,32 +218,6 @@ void led_classdev_unregister(struct led_classdev *led_cdev)
> ?}
> ?EXPORT_SYMBOL_GPL(led_classdev_unregister);
>
> -void led_blink_set(struct led_classdev *led_cdev,
> - ? ? ? ? ? ? ? ? ?unsigned long *delay_on,
> - ? ? ? ? ? ? ? ? ?unsigned long *delay_off)
> -{
> - ? ? ? del_timer_sync(&led_cdev->blink_timer);
> -
> - ? ? ? if (led_cdev->blink_set &&
> - ? ? ? ? ? !led_cdev->blink_set(led_cdev, delay_on, delay_off))
> - ? ? ? ? ? ? ? return;
> -
> - ? ? ? /* blink with 1 Hz as default if nothing specified */
> - ? ? ? if (!*delay_on && !*delay_off)
> - ? ? ? ? ? ? ? *delay_on = *delay_off = 500;
> -
> - ? ? ? led_set_software_blink(led_cdev, *delay_on, *delay_off);
> -}
> -EXPORT_SYMBOL(led_blink_set);
> -
> -void led_brightness_set(struct led_classdev *led_cdev,
> - ? ? ? ? ? ? ? ? ? ? ? enum led_brightness brightness)
> -{
> - ? ? ? led_stop_software_blink(led_cdev);
> - ? ? ? led_cdev->brightness_set(led_cdev, brightness);
> -}
> -EXPORT_SYMBOL(led_brightness_set);
> -
> ?static int __init leds_init(void)
> ?{
> ? ? ? ?leds_class = class_create(THIS_MODULE, "leds");
> diff --git a/drivers/leds/led-core.c b/drivers/leds/led-core.c
> index 016d19f..d686004 100644
> --- a/drivers/leds/led-core.c
> +++ b/drivers/leds/led-core.c
> @@ -23,3 +23,73 @@ EXPORT_SYMBOL_GPL(leds_list_lock);
>
> ?LIST_HEAD(leds_list);
> ?EXPORT_SYMBOL_GPL(leds_list);
> +
> +static void led_stop_software_blink(struct led_classdev *led_cdev)
> +{
> + ? ? ? /* deactivate previous settings */
> + ? ? ? del_timer_sync(&led_cdev->blink_timer);
> + ? ? ? led_cdev->blink_delay_on = 0;
> + ? ? ? led_cdev->blink_delay_off = 0;
> +}
> +
> +static void led_set_software_blink(struct led_classdev *led_cdev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long delay_on,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long delay_off)
> +{
> + ? ? ? int current_brightness;
> +
> + ? ? ? current_brightness = led_get_brightness(led_cdev);
> + ? ? ? if (current_brightness)
> + ? ? ? ? ? ? ? led_cdev->blink_brightness = current_brightness;
> + ? ? ? if (!led_cdev->blink_brightness)
> + ? ? ? ? ? ? ? led_cdev->blink_brightness = led_cdev->max_brightness;
> +
> + ? ? ? if (led_get_trigger_data(led_cdev) &&
> + ? ? ? ? ? delay_on == led_cdev->blink_delay_on &&
> + ? ? ? ? ? delay_off == led_cdev->blink_delay_off)
> + ? ? ? ? ? ? ? return;
> +
> + ? ? ? led_stop_software_blink(led_cdev);
> +
> + ? ? ? led_cdev->blink_delay_on = delay_on;
> + ? ? ? led_cdev->blink_delay_off = delay_off;
> +
> + ? ? ? /* never on - don't blink */
> + ? ? ? if (!delay_on)
> + ? ? ? ? ? ? ? return;
> +
> + ? ? ? /* never off - just set to brightness */
> + ? ? ? if (!delay_off) {
> + ? ? ? ? ? ? ? led_set_brightness(led_cdev, led_cdev->blink_brightness);
> + ? ? ? ? ? ? ? return;
> + ? ? ? }
> +
> + ? ? ? mod_timer(&led_cdev->blink_timer, jiffies + 1);
> +}
> +
> +
> +void led_blink_set(struct led_classdev *led_cdev,
> + ? ? ? ? ? ? ? ? ?unsigned long *delay_on,
> + ? ? ? ? ? ? ? ? ?unsigned long *delay_off)
> +{
> + ? ? ? del_timer_sync(&led_cdev->blink_timer);
> +
> + ? ? ? if (led_cdev->blink_set &&
> + ? ? ? ? ? !led_cdev->blink_set(led_cdev, delay_on, delay_off))
> + ? ? ? ? ? ? ? return;
> +
> + ? ? ? /* blink with 1 Hz as default if nothing specified */
> + ? ? ? if (!*delay_on && !*delay_off)
> + ? ? ? ? ? ? ? *delay_on = *delay_off = 500;
> +
> + ? ? ? led_set_software_blink(led_cdev, *delay_on, *delay_off);
> +}
> +EXPORT_SYMBOL(led_blink_set);
> +
> +void led_brightness_set(struct led_classdev *led_cdev,
> + ? ? ? ? ? ? ? ? ? ? ? enum led_brightness brightness)
> +{
> + ? ? ? led_stop_software_blink(led_cdev);
> + ? ? ? led_cdev->brightness_set(led_cdev, brightness);
> +}
> +EXPORT_SYMBOL(led_brightness_set);
> --
> 1.7.9
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



-- 
Bryan Wu <bryan.wu at canonical.com>
Kernel Developer ? ?+86.138-1617-6545 Mobile
Ubuntu ARM Team
Canonical Ltd. ? ? ?www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com


From cjb at laptop.org  Thu Mar  8 23:56:10 2012
From: cjb at laptop.org (Chris Ball)
Date: Thu, 08 Mar 2012 23:56:10 -0500
Subject: [PATCH 1/2] mmc: sdhci-s3c: Use CONFIG_PM_SLEEP to ifdef system
 suspend
In-Reply-To: <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 (Mark Brown's message of "Sat, 3 Mar 2012 00:46:41 +0000")
References: <4F51697C.40408@samsung.com>
 <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <m27gyupe39.fsf@bob.laptop.org>

Hi Mark,

On Fri, Mar 02 2012, Mark Brown wrote:
> This matches current best practice as one can have runtime PM enabled
> without system sleep and CONFIG_PM is defined for both.
>
> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---
>  drivers/mmc/host/sdhci-s3c.c |    9 +++++----
>  1 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index ea0767e..46152d6 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -22,6 +22,7 @@
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/of_gpio.h>
> +#include <linux/pm.h>
>  
>  #include <linux/mmc/host.h>
>  
> @@ -807,8 +808,7 @@ static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -#ifdef CONFIG_PM
> -
> +#ifdef CONFIG_PM_SLEEP
>  static int sdhci_s3c_suspend(struct device *dev)
>  {
>  	struct sdhci_host *host = dev_get_drvdata(dev);
> @@ -822,10 +822,11 @@ static int sdhci_s3c_resume(struct device *dev)
>  
>  	return sdhci_resume_host(host);
>  }
> +#endif
>  
> +#ifdef CONFIG_PM
>  static const struct dev_pm_ops sdhci_s3c_pmops = {
> -	.suspend	= sdhci_s3c_suspend,
> -	.resume		= sdhci_s3c_resume,
> +	SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
>  };
>  
>  #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)

Thanks, pushed to mmc-next for 3.4 with Jaehoon's ACK.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From olof at lixom.net  Sat Mar 10 13:21:49 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 10:21:49 -0800
Subject: [GIT PULL 4/4] Samsung devel-dma for v3.4
In-Reply-To: <4F5B7CA7.2010604@samsung.com>
References: <4F5B7CA7.2010604@samsung.com>
Message-ID: <20120310182149.GA656@quad.lixom.net>

On Sat, Mar 10, 2012 at 08:09:11AM -0800, Kukjin Kim wrote:
> Hi Arnd, Olof,
> 
> This is for Samsung dma stuff for v3.4 and depends on following:
>   next/cleanup-use-static
>   next/cleanup-exynos-clock
> 
> Please pull from:

> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/devel-samsung-dma
> 
> And conflicts will be happened in clock part. Here is my preferred
> resolution. The mach-exynos/clock.c can be removed with following:
> 
> arch/arm/mach-exynos/exynos-clock4.c

Hi,

given my feedback on the cleanup-exynos-clock pull request, I'm holding off on
this one waiting on you to do the resolution of the conflicts. :-)


Thanks,

-Olof


From peter.ujfalusi at ti.com  Fri Mar  9 03:51:16 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Fri,  9 Mar 2012 10:51:16 +0200
Subject: [PATCH 0/2] ARM/ASoC: OMAP: McBSP config cleanup
Message-ID: <1331283078-14846-1-git-send-email-peter.ujfalusi@ti.com>

Hi,

Since the McBSP driver has been moved out from arch/arm/plat-omap/ and it is
combined as a single driver with the sound/soc/omap/omap-mcbsp.c there is no
longer need to have CONFIG_OMAP_MCBSP.
This series cleans up the Kconfigs, and Makefiles.
Also it is fixes the issue that the OMAP audio drivers were not buildable as
modules (the ones using McBSP) reported by Grazvydas Ignotas <notasas at gmail.com>

I have generated this series on top of Liam's for-3.4 branch. The
arch/arm/mach-omap* patch applies cleanly on top of todays linux-next, so if
this series goes via ASoC we are not going to have conflicts with stuff coming
via l-o.

Tested on BeagleBoard, and SDP4430, compile tested for OMAP1.

This series should go via ASoC along with the rest of the McBSP changes.

Regards,
Peter
---
Peter Ujfalusi (2):
  ARM: OMAP: Remove CONFIG_OMAP_MCBSP references
  ASoC: OMAP: Build config cleanup for McBSP

 arch/arm/mach-omap1/Kconfig  |    3 ---
 arch/arm/mach-omap1/Makefile |    4 +++-
 arch/arm/mach-omap2/Makefile |    4 +++-
 sound/soc/omap/Kconfig       |    6 ------
 sound/soc/omap/Makefile      |    3 +--
 5 files changed, 7 insertions(+), 13 deletions(-)

-- 
1.7.8.5



From daniel.lezcano at linaro.org  Fri Mar  9 17:45:19 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 09 Mar 2012 23:45:19 +0100
Subject: linux-next: manual merge of the cpuidle-cons tree with the arm-soc
 tree
In-Reply-To: <CAMXH7KE5En7U-2zydT3MfJ7C7B164-zsQuBoHMUqzD-Kb_nh1w@mail.gmail.com>
References: <20120309183732.512d3676599da324f4747219@canb.auug.org.au>
 <CAMXH7KE5En7U-2zydT3MfJ7C7B164-zsQuBoHMUqzD-Kb_nh1w@mail.gmail.com>
Message-ID: <4F5A87FF.8060606@linaro.org>

On 03/09/2012 11:26 PM, Rob Lee wrote:
> Hello Stephen,
>
> Yes, your resolution looks correct to me.

For me too.

Thanks
   -- Daniel


> On Fri, Mar 9, 2012 at 1:37 AM, Stephen Rothwell<sfr at canb.auug.org.au>  wrote:
>> Hi Rob,
>>
>> Today's linux-next merge of the cpuidle-cons tree got a conflict in
>> arch/arm/mach-at91/cpuidle.c between commit 00482a4078f4 ("ARM: at91:
>> implement the standby function for pm/cpuidle") from the arm-soc tree and
>> commit 7a1f6e72dce1 ("ARM: at91: Consolidate time keeping and irq
>> enable") from the cpuidle-cons tree.
>>
>> I fixed it up (I think - see below) and can carry the fix as necessary.
>> --
>> Cheers,
>> Stephen Rothwell                    sfr at canb.auug.org.au
>>
>> diff --cc arch/arm/mach-at91/cpuidle.c
>> index 555d956,d40b3f3..0000000
>> --- a/arch/arm/mach-at91/cpuidle.c
>> +++ b/arch/arm/mach-at91/cpuidle.c
>> @@@ -37,23 -33,15 +33,8 @@@ static int at91_enter_idle(struct cpuid
>>                         struct cpuidle_driver *drv,
>>                                int index)
>>   {
>> -       struct timeval before, after;
>> -       int idle_time;
>> -
>> -       local_irq_disable();
>> -       do_gettimeofday(&before);
>> -       if (index == 0)
>> -               /* Wait for interrupt state */
>> -               cpu_do_idle();
>> -       else if (index == 1)
>> -               at91_standby();
>>   -      u32 saved_lpr;
>>   -
>>   -      __asm__("b 1f; .align 5; 1:\n"
>>   -      "       mcr p15, 0, r0, c7, c10, 4");   /* drain write buffer */
>>   -
>>   -      saved_lpr = sdram_selfrefresh_enable();
>>   -      cpu_do_idle();
>>   -      sdram_selfrefresh_disable(saved_lpr);
>> ++      at91_standby();
>>
>> -       do_gettimeofday(&after);
>> -       local_irq_enable();
>> -       idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
>> -                       (after.tv_usec - before.tv_usec);
>> -
>> -       dev->last_residency = idle_time;
>>         return index;
>>   }
>>


-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From grant.likely at secretlab.ca  Fri Mar  9 00:26:00 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 08 Mar 2012 22:26:00 -0700
Subject: [PATCH 2/5 v3] ARM: at91: sam9g20 add i2c DT support
In-Reply-To: <1331196635-27203-2-git-send-email-plagnioj@jcrosoft.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <1331196635-27203-2-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120309052600.B13BA3E0649@localhost>

On Thu,  8 Mar 2012 09:50:32 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> For now on use i2c-gpio driver on the same pin as the hardware IP.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: devicetree-discuss at lists.ozlabs.org
> ---
> v3:
> 
> 	update i2c binding (Rob comments)
> 
> Best Regards,
> J.
>  arch/arm/boot/dts/at91sam9g20.dtsi |   13 +++++++++++++
>  1 files changed, 13 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
> index 4b0dc99..072b2da 100644
> --- a/arch/arm/boot/dts/at91sam9g20.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
> @@ -189,4 +189,17 @@
>  			status = "disabled";
>  		};
>  	};
> +
> +	i2c-gpio at 0 {

i2c at 0

> +		compatible = "i2c-gpio";
> +		gpios = <&pioA 23 0 /* sda */
> +			 &pioA 24 0 /* scl */
> +			>;
> +		i2c-gpio,sda-open-drain;
> +		i2c-gpio,scl-open-drain;
> +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};

gpio-driven i2c busses are inherently board-specific.  Why is this
in the SoC include file?

Otherwise I think this patch series looks okay.

g.

>  };
> -- 
> 1.7.7
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From olof at lixom.net  Sat Mar 10 13:20:29 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 10:20:29 -0800
Subject: [GIT PULL] mach/io.h clean-up and removal
In-Reply-To: <4F58DD30.4060704@gmail.com>
References: <4F58DD30.4060704@gmail.com>
Message-ID: <CAOesGMi1pD+1BEkXSGDA8k6UC2DD65QYt3Z_59McFkgWrdqehQ@mail.gmail.com>

Hi,

On Thu, Mar 8, 2012 at 8:24 AM, Rob Herring <robherring2 at gmail.com> wrote:
> Arnd, Olof,
>
> Please pull the mach/io.h cleanup series for 3.4. This does not include
> the PCI i/o mapping changes. In hopes of testing, I'll wait until 3.5
> for that. Although, it seems no one has devices with i/o.
>
> I'm sending this to you rather than Russell as it is based on at91 and
> omap cleanup branches in arm-soc tree.
>
> Rob
>
> The following changes since commit d50673ed97a7ce609cf62bcd40c57517ada31806:
>
> ?Merge remote-tracking branch 'arm-soc/at91/base2+cleanup' into
> cleanup-base (2012-03-04 22:00:46 -0600)
>
> are available in the git repository at:
>
> ?git://sources.calxeda.com/kernel/linux.git io-cleanup-for-3.4

I've pulled this into next/cleanup2. Nice diffstat!


Thanks,

-Olof


From rusty at rustcorp.com.au  Thu Mar  8 23:26:52 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 09 Mar 2012 14:56:52 +1030
Subject: [PATCH 6/8] ARM: KVM: table-driven coprocessor emulation.
Message-ID: <1331267212.16020.rusty@rustcorp.com.au>


From: Rusty Russell <rusty at rustcorp.com.au>

To try to avoid encroaching ad-hoc emulation, drive it from
a single table, so it's clear exactly what we do and do not
emulate.

Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
---
 arch/arm/kvm/emulate.c |  255 ++++++++++++++++++++++++------------------------
 1 files changed, 130 insertions(+), 125 deletions(-)

diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
index d386874..bd2c3dc 100644
--- a/arch/arm/kvm/emulate.c
+++ b/arch/arm/kvm/emulate.c
@@ -165,25 +165,19 @@ struct coproc_params {
 	bool is_write;
 };
 
-static void cp15_op(struct kvm_vcpu *vcpu, const struct coproc_params *p,
-			   enum cp15_regs cp15_reg)
-{
-	if (p->is_write)
-		vcpu->arch.cp15[cp15_reg] = *vcpu_reg(vcpu, p->Rt1);
-	else
-		*vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[cp15_reg];
-}
-
 static void print_cp_instr(const struct coproc_params *p)
 {
+	/* Look, we even formatted it for you to paste into the table! */
 	if (p->is_64bit) {
-		kvm_debug("%s\tp15, %lu, r%lu, r%lu, c%lu",
-			  (p->is_write) ? "mcrr" : "mrrc",
-			  p->Op1, p->Rt1, p->Rt2, p->CRm);
+		kvm_debug("{ .is_64bit = true, .is_write = %s, .param ="
+			  " { .CRm = %lu, .Op1 = %lu } }",
+			  p->is_write ? "true" : "false", p->CRm, p->Op1);
 	} else {
-		kvm_debug("%s\tp15, %lu, r%lu, c%lu, c%lu, %lu",
-			  (p->is_write) ? "mcr" : "mrc",
-			  p->Op1, p->Rt1, p->CRn, p->CRm, p->Op2);
+		kvm_debug("{ .is_64bit = false, .is_write = %s, .param ="
+			  " { .CRn = %lu, .CRm = %lu,"
+			  " .Op1 = %lu, .Op2 = %lu } }",
+			  p->is_write ? "true" : "false",
+			  p->CRn, p->CRm, p->Op1, p->Op2);
 	}
 }
 
@@ -207,139 +201,150 @@ int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
 	return -EINVAL;
 }
 
-/**
- * emulate_cp15_c9_access -- emulates cp15 accesses for CRn == 9
- * @vcpu: The VCPU pointer
- * @p:    The coprocessor parameters struct pointer holding trap inst. details
- */
-static bool emulate_cp15_c9_access(struct kvm_vcpu *vcpu,
-				   const struct coproc_params *p)
+static bool ignore_write(struct kvm_vcpu *vcpu,
+			 const struct coproc_params *p,
+			 unsigned long arg)
 {
-	BUG_ON(p->CRn != 9);
-	BUG_ON(p->is_64bit);
-
-	if (p->CRm == 0 && p->Op1 == 1 && p->Op2 == 2) {
-		/* Emulate L2CTLR access */
-		u32 l2ctlr, ncores;
+	if (arg)
+		trace_kvm_emulate_cp15_imp(p->Op1, p->Rt1, p->CRn, p->CRm,
+					   p->Op2, p->is_write);
+	return true;
+}
 
-		if (p->is_write)
-			return true;
+static bool read_zero(struct kvm_vcpu *vcpu,
+		      const struct coproc_params *p,
+		      unsigned long arg)
+{
+	if (arg)
+		trace_kvm_emulate_cp15_imp(p->Op1, p->Rt1, p->CRn, p->CRm,
+					   p->Op2, p->is_write);
+	*vcpu_reg(vcpu, p->Rt1) = 0;
+	return true;
+}
 
-		asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
-		l2ctlr &= ~(3 << 24);
-		ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1;
-		l2ctlr |= (ncores & 3) << 24;
-		*vcpu_reg(vcpu, p->Rt1) = l2ctlr;
+static bool read_l2ctlr(struct kvm_vcpu *vcpu,
+			const struct coproc_params *p,
+			unsigned long arg)
+{
+	u32 l2ctlr, ncores;
 
-		return true;
-	}
+	asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
+	l2ctlr &= ~(3 << 24);
+	ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1;
+	l2ctlr |= (ncores & 3) << 24;
+	*vcpu_reg(vcpu, p->Rt1) = l2ctlr;
 
-	/* hack alert!!! */
-	if (!p->is_write)
-		*vcpu_reg(vcpu, p->Rt1) = 0;
 	return true;
 }
 
-/**
- * emulate_cp15_c10_access -- emulates cp15 accesses for CRn == 10
- * @vcpu: The VCPU pointer
- * @p:    The coprocessor parameters struct pointer holding trap inst. details
- *
- * This function may not need to exist - if we can ignore guest attempts to
- * tamper with TLB lockdowns then it should be enough to store/restore the
- * host/guest PRRR and NMRR memory remap registers and allow guest direct access
- * to these registers.
- */
-static bool emulate_cp15_c10_access(struct kvm_vcpu *vcpu,
-				    const struct coproc_params *p)
+static bool access_cp15_reg(struct kvm_vcpu *vcpu,
+			    const struct coproc_params *p,
+			    unsigned long cp15_reg)
 {
-	BUG_ON(p->CRn != 10);
-	BUG_ON(p->is_64bit);
-
-	if ((p->CRm == 0 || p->CRm == 1 || p->CRm == 4 || p->CRm == 8) &&
-	    (p->Op2 <= 7)) {
-		/* TLB Lockdown operations - ignored */
-		return true;
-	}
+	if (p->is_write)
+		vcpu->arch.cp15[cp15_reg] = *vcpu_reg(vcpu, p->Rt1);
+	else
+		*vcpu_reg(vcpu, p->Rt1) = vcpu->arch.cp15[cp15_reg];
+	return true;
+}
 
-	/*
-	 * The role of these registers depends on whether LPAE is defined or
-	 * not, but there shouldn't be any breakage in any case - we may
-	 * simply not respect the nomenclature here.
-	 */
 
-	if (p->CRm == 2 && p->Op1 == 0 && p->Op2 == 0) {
-		cp15_op(vcpu, p, c10_PRRR);
-		return true;
-	}
+/* Any field which is 0xFFFFFFFF == any. */
+#define ANY (-1UL)
+struct coproc_emulate {
+	unsigned long is_64;
+	unsigned long is_w;
+	struct {
+		unsigned long CRm;
+		unsigned long CRn;
+		unsigned long Op1;
+		unsigned long Op2;
+	} param;
+
+	bool (*f)(struct kvm_vcpu *,
+		  const struct coproc_params *,
+		  unsigned long);
+	unsigned long arg;
+};
 
-	if (p->CRm == 2 && p->Op1 == 0 && p->Op2 == 1) {
-		cp15_op(vcpu, p, c10_NMRR);
-		return true;
-	}
 
-	return false;
-}
+static const struct coproc_emulate coproc_emulate[] = {
+	/* Ignore writes to L2CTLR access */
+	{ .is_64 = false, .is_w = true, .f = ignore_write,
+	  .param = { .CRn = 9, .CRm = 0, .Op1 = 1, .Op2 = 2 } },
+	{ .is_64 = false, .is_w = false, .f = read_l2ctlr,
+	  .param = { .CRn = 9, .CRm = 0, .Op1 = 1, .Op2 = 2 } },
+	/* Hack alert!!! */
+	{ .is_64 = false, .is_w = true, .f = ignore_write,
+	  .param = { .CRn = 9, .CRm = ANY, .Op1 = ANY, .Op2 = ANY } },
+	{ .is_64 = false, .is_w = false, .f = read_zero,
+	  .param = { .CRn = 9, .CRm = ANY, .Op1 = ANY, .Op2 = ANY } },
+
+	/* These CRn == 10 entries may not need to exist - if we can
+	 * ignore guest attempts to tamper with TLB lockdowns then it
+	 * should be enough to store/restore the host/guest PRRR and
+	 * NMRR memory remap registers and allow guest direct access
+	 * to these registers. */
+	/* TLB Lockdown operations - ignored */
+	{ .is_64 = false, .is_w = true, .f = ignore_write,
+	  .param = { .CRn = 10, .CRm = 0, .Op1 = ANY, .Op2 = ANY } },
+	{ .is_64 = false, .is_w = ANY, .f = access_cp15_reg,
+	  .arg = c10_PRRR,
+	  .param = { .CRn = 10, .CRm = 2, .Op1 = 0, .Op2 = 0 } },
+	{ .is_64 = false, .is_w = ANY, .f = access_cp15_reg,
+	  .arg = c10_NMRR,
+	  .param = { .CRn = 10, .CRm = 2, .Op1 = 0, .Op2 = 1 } },
+
+	/* The CP15 c15 register is architecturally implementation
+	 * defined, but some guest kernels attempt to read/write a
+	 * diagnostics register here. We always return 0 and ignore
+	 * writes and hope for the best. */
+	{ .is_64 = false, .is_w = true, .f = ignore_write, .arg = 1,
+	  .param = { .CRn = 15, .CRm = ANY, .Op1 = ANY, .Op2 = ANY } },
+	{ .is_64 = false, .is_w = false, .f = read_zero, .arg = 1,
+	  .param = { .CRn = 15, .CRm = ANY, .Op1 = ANY, .Op2 = ANY } },
+};
 
-/**
- * emulate_cp15_c15_access -- emulates cp15 accesses for CRn == 15
- * @vcpu: The VCPU pointer
- * @p:    The coprocessor parameters struct pointer holding trap inst. details
- *
- * The CP15 c15 register is architecturally implementation defined, but some
- * guest kernels attempt to read/write a diagnostics register here. We always
- * return 0 and ignore writes and hope for the best.
- *
- * This may need to be refined.
- */
-static bool emulate_cp15_c15_access(struct kvm_vcpu *vcpu,
-				    const struct coproc_params *p)
+static inline bool match(unsigned long val, unsigned long param)
 {
-	trace_kvm_emulate_cp15_imp(p->Op1, p->Rt1, p->CRn, p->CRm,
-				   p->Op2, p->is_write);
-
-	if (!p->is_write)
-		*vcpu_reg(vcpu, p->Rt1) = 0;
-
-	return true;
+	return param == ANY || val == param;
 }
 
 static int emulate_cp15(struct kvm_vcpu *vcpu,
 			const struct coproc_params *params)
 {
-	unsigned long instr_len;
-	bool ok;
-
-	/* So far no mrrc/mcrr accesses are emulated */
-	if (params->is_64bit)
-		goto unsupp_err_out;
-
-	switch (params->CRn) {
-	case 9:
-		ok = emulate_cp15_c9_access(vcpu, params);
-		break;
-	case 10:
-		ok = emulate_cp15_c10_access(vcpu, params);
-		break;
-	case 15:
-		ok = emulate_cp15_c15_access(vcpu, params);
-		break;
-	default:
-		ok = false;
+	unsigned long instr_len, i;
+
+	for (i = 0; i < ARRAY_SIZE(coproc_emulate); i++) {
+		const struct coproc_emulate *e = &coproc_emulate[i];
+
+		if (!match(params->is_64bit, e->is_64))
+			continue;
+		if (!match(params->is_write, e->is_w))
+			continue;
+		if (!match(params->CRn, e->param.CRn))
+			continue;
+		if (!match(params->CRm, e->param.CRm))
+			continue;
+		if (!match(params->Op1, e->param.Op1))
+			continue;
+		if (!match(params->Op2, e->param.Op2))
+			continue;
+
+		/* If function fails, it should complain. */
+		if (!e->f(vcpu, params, e->arg))
+			goto fail;
+
+		/* Skip instruction, since it was emulated */
+		instr_len = ((vcpu->arch.hsr >> 25) & 1) ? 4 : 2;
+		*vcpu_reg(vcpu, 15) += instr_len;
+		return 0;
 	}
 
-	if (!ok)
-		goto unsupp_err_out;
-
-	/* Skip instruction, since it was emulated */
-	instr_len = ((vcpu->arch.hsr >> 25) & 1) ? 4 : 2;
-	*vcpu_reg(vcpu, 15) += instr_len;
-
-	return 0;
-
-unsupp_err_out:	
-	kvm_err("Unsupported guest CP15 access at: %08x\n", vcpu->arch.regs.pc);
+	kvm_err("Unsupported guest CP15 access at: %08x\n",
+		vcpu->arch.regs.pc);
 	print_cp_instr(params);
+fail:
 	return -EINVAL;
 }
 



From pullip.cho at samsung.com  Fri Mar  9 07:15:04 2012
From: pullip.cho at samsung.com (Cho KyongHo)
Date: Fri, 09 Mar 2012 21:15:04 +0900
Subject: [PATCH v11 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
Message-ID: <017901ccfdee$42420b10$c6c62130$%cho@samsung.com>

Handling System MMUs with an identifier is not flexible to manage
System MMU platform devices because of the following reasons:
1. A device driver which needs to handle System MMU must know the ID.
2. A System MMU may not present in some implementations of Exynos family.
3. Handling System MMU with IOMMU API does not require an ID.

This patch is the result of removing ID of System MMUs.
Instead, a device driver that needs to handle its System MMU must
use IOMMU API while its descriptor of platform device is given.

This patch also includes the following enhancements:
- A System MMU device becomes a child if its power domain device.
- clkdev

Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
---
 arch/arm/mach-exynos/Kconfig                    |   11 +-
 arch/arm/mach-exynos/Makefile                   |    2 +-
 arch/arm/mach-exynos/clock-exynos4.c            |   79 ++--
 arch/arm/mach-exynos/clock-exynos4.h            |    2 +
 arch/arm/mach-exynos/clock-exynos4210.c         |   11 +
 arch/arm/mach-exynos/clock-exynos4212.c         |   28 ++-
 arch/arm/mach-exynos/clock-exynos5.c            |   90 +++++
 arch/arm/mach-exynos/dev-sysmmu.c               |  457 ++++++++++++----------
 arch/arm/mach-exynos/include/mach/irqs.h        |  179 +++++-----
 arch/arm/mach-exynos/include/mach/map.h         |   38 ++
 arch/arm/mach-exynos/include/mach/regs-clock.h  |    5 +
 arch/arm/mach-exynos/include/mach/regs-sysmmu.h |   28 --
 arch/arm/mach-exynos/include/mach/sysmmu.h      |   88 +++--
 arch/arm/mach-exynos/mach-armlex4210.c          |    1 -
 arch/arm/mach-exynos/mach-smdkv310.c            |    1 -
 15 files changed, 616 insertions(+), 404 deletions(-)
 delete mode 100644 arch/arm/mach-exynos/include/mach/regs-sysmmu.h

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 9b8ccef..b08923f 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -90,10 +90,10 @@ config EXYNOS4_SETUP_FIMD0
 	help
 	  Common setup code for FIMD0.
 
-config EXYNOS4_DEV_SYSMMU
+config EXYNOS_DEV_SYSMMU
 	bool
 	help
-	  Common setup code for SYSTEM MMU in EXYNOS4
+	  Common setup code for SYSTEM MMU in EXYNOS platforms
 
 config EXYNOS4_DEV_DWMCI
 	bool
@@ -203,12 +203,12 @@ config MACH_SMDKV310
 	select S3C_DEV_HSMMC2
 	select S3C_DEV_HSMMC3
 	select SAMSUNG_DEV_BACKLIGHT
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_DEV_AHCI
 	select SAMSUNG_DEV_KEYPAD
 	select EXYNOS4_DEV_DMA
 	select SAMSUNG_DEV_PWM
 	select EXYNOS4_DEV_USB_OHCI
-	select EXYNOS4_DEV_SYSMMU
 	select EXYNOS4_SETUP_FIMD0
 	select EXYNOS4_SETUP_I2C1
 	select EXYNOS4_SETUP_KEYPAD
@@ -227,7 +227,6 @@ config MACH_ARMLEX4210
 	select S3C_DEV_HSMMC3
 	select EXYNOS4_DEV_AHCI
 	select EXYNOS4_DEV_DMA
-	select EXYNOS4_DEV_SYSMMU
 	select EXYNOS4_SETUP_SDHCI
 	help
 	  Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@@ -253,6 +252,7 @@ config MACH_UNIVERSAL_C210
 	select S5P_DEV_MFC
 	select S5P_DEV_ONENAND
 	select S5P_DEV_TV
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_DEV_DMA
 	select EXYNOS4_SETUP_FIMD0
 	select EXYNOS4_SETUP_I2C1
@@ -322,6 +322,7 @@ config MACH_ORIGEN
 	select S5P_DEV_USB_EHCI
 	select SAMSUNG_DEV_BACKLIGHT
 	select SAMSUNG_DEV_PWM
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_DEV_DMA
 	select EXYNOS4_DEV_USB_OHCI
 	select EXYNOS4_SETUP_FIMD0
@@ -357,6 +358,7 @@ config MACH_SMDK4212
 	select SAMSUNG_DEV_KEYPAD
 	select SAMSUNG_DEV_PWM
 	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_SETUP_I2C1
 	select EXYNOS4_SETUP_I2C3
 	select EXYNOS4_SETUP_I2C7
@@ -382,6 +384,7 @@ comment "EXYNOS5250 Boards"
 config MACH_SMDK5250
 	bool "SMDK5250"
 	select SOC_EXYNOS5250
+	select EXYNOS_DEV_SYSMMU
 	help
 	  Machine support for Samsung SMDK5250
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 04feed2..7d33283 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -51,7 +51,7 @@ obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
 obj-y					+= dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
-obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)	+= dev-sysmmu.o
+obj-$(CONFIG_EXYNOS_DEV_SYSMMU)		+= dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
 obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index af48ad1..7d4784d 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -169,7 +169,7 @@ static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
 }
 
-static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
 }
@@ -199,6 +199,11 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
 }
 
+int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
+}
+
 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
@@ -679,61 +684,55 @@ static struct clk exynos4_init_clocks_off[] = {
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 14),
 	}, {
-		.name		= "SYSMMU_MDMA",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+		.enable		= exynos4_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+		.enable		= exynos4_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(tv, 2),
+		.enable		= exynos4_clk_ip_tv_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(rot, 4),
 		.enable		= exynos4_clk_ip_image_ctrl,
-		.ctrlbit	= (1 << 5),
+		.ctrlbit	= (1 << 4),
 	}, {
-		.name		= "SYSMMU_FIMC0",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc0, 5),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 7),
 	}, {
-		.name		= "SYSMMU_FIMC1",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc1, 6),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 8),
 	}, {
-		.name		= "SYSMMU_FIMC2",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc2, 7),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 9),
 	}, {
-		.name		= "SYSMMU_FIMC3",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc3, 8),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 10),
 	}, {
-		.name		= "SYSMMU_JPEG",
-		.enable		= exynos4_clk_ip_cam_ctrl,
-		.ctrlbit	= (1 << 11),
-	}, {
-		.name		= "SYSMMU_FIMD0",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimd0, 10),
 		.enable		= exynos4_clk_ip_lcd0_ctrl,
 		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_FIMD1",
-		.enable		= exynos4_clk_ip_lcd1_ctrl,
-		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_PCIe",
-		.enable		= exynos4_clk_ip_fsys_ctrl,
-		.ctrlbit	= (1 << 18),
-	}, {
-		.name		= "SYSMMU_G2D",
-		.enable		= exynos4_clk_ip_image_ctrl,
-		.ctrlbit	= (1 << 3),
-	}, {
-		.name		= "SYSMMU_ROTATOR",
-		.enable		= exynos4_clk_ip_image_ctrl,
-		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_TV",
-		.enable		= exynos4_clk_ip_tv_ctrl,
-		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_MFC_L",
-		.enable		= exynos4_clk_ip_mfc_ctrl,
-		.ctrlbit	= (1 << 1),
-	}, {
-		.name		= "SYSMMU_MFC_R",
-		.enable		= exynos4_clk_ip_mfc_ctrl,
-		.ctrlbit	= (1 << 2),
 	}
 };
 
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
index 9d27a56..309cc71 100644
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -28,5 +28,7 @@ extern struct clk *exynos4_clkset_group_list[];
 extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
 
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 68763b3..c1fcd2f 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -28,6 +28,7 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
 
 #include "clock-exynos4.h"
 #include "common.h"
@@ -96,6 +97,16 @@ static struct clk init_clocks_off[] = {
 		.devname	= "exynos4-fb.1",
 		.enable		= exynos4_clk_ip_lcd1_ctrl,
 		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimd1, 11),
+		.enable		= exynos4_clk_ip_lcd1_ctrl,
+		.ctrlbit	= (1 << 4),
 	},
 };
 
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index f22a0a2..e1059a2 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -28,6 +28,7 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
 
 #include "clock-exynos4.h"
 #include "common.h"
@@ -41,6 +42,16 @@ static struct sleep_save exynos4212_clock_save[] = {
 };
 #endif
 
+static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
+}
+
+static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
+}
+
 static struct clk *clk_src_mpll_user_list[] = {
 	[0] = &clk_fin_mpll,
 	[1] = &exynos4_clk_mout_mpll.clk,
@@ -68,7 +79,22 @@ static struct clksrc_clk clksrcs[] = {
 };
 
 static struct clk init_clocks_off[] = {
-	/* nothing here yet */
+	{
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (7 << 8),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME2,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 4),
+	}
 };
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index d013982..3320ad1 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
 }
 
+static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
+}
+
 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
@@ -127,6 +132,21 @@ static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
 }
 
+static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
+}
+
+static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
+}
+
+static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
+}
+
 /* Core list of CMU_CPU side */
 
 static struct clksrc_clk exynos5_clk_mout_apll = {
@@ -630,6 +650,76 @@ static struct clk exynos5_init_clocks_off[] = {
 		.parent		= &exynos5_clk_aclk_66.clk,
 		.enable		= exynos5_clk_ip_peric_ctrl,
 		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+		.enable		= &exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+		.enable		= &exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(tv, 2),
+		.enable		= &exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 9)
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+		.enable		= &exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(rot, 4),
+		.enable		= &exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 6)
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc0, 5),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc1, 6),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc2, 7),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc3, 8),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= &exynos5_clk_ip_isp0_ctrl,
+		.ctrlbit	= (0x3F << 8),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME2,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= &exynos5_clk_ip_isp1_ctrl,
+		.ctrlbit	= (0xF << 4),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(camif0, 12),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(camif1, 13),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
+		.enable		= &exynos5_clk_ip_acp_ctrl,
+		.ctrlbit	= (1 << 7)
 	}
 };
 
diff --git a/arch/arm/mach-exynos/dev-sysmmu.c b/arch/arm/mach-exynos/dev-sysmmu.c
index 781563f..c5b1ea3 100644
--- a/arch/arm/mach-exynos/dev-sysmmu.c
+++ b/arch/arm/mach-exynos/dev-sysmmu.c
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
+/* linux/arch/arm/mach-exynos/dev-sysmmu.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * EXYNOS4 - System MMU support
+ * EXYNOS - System MMU support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,222 +12,263 @@
 
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
-#include <linux/export.h>
+
+#include <plat/cpu.h>
 
 #include <mach/map.h>
 #include <mach/irqs.h>
 #include <mach/sysmmu.h>
-#include <plat/s5p-clock.h>
-
-/* These names must be equal to the clock names in mach-exynos4/clock.c */
-const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
-	"SYSMMU_MDMA"	,
-	"SYSMMU_SSS"	,
-	"SYSMMU_FIMC0"	,
-	"SYSMMU_FIMC1"	,
-	"SYSMMU_FIMC2"	,
-	"SYSMMU_FIMC3"	,
-	"SYSMMU_JPEG"	,
-	"SYSMMU_FIMD0"	,
-	"SYSMMU_FIMD1"	,
-	"SYSMMU_PCIe"	,
-	"SYSMMU_G2D"	,
-	"SYSMMU_ROTATOR",
-	"SYSMMU_MDMA2"	,
-	"SYSMMU_TV"	,
-	"SYSMMU_MFC_L"	,
-	"SYSMMU_MFC_R"	,
-};
 
-static struct resource exynos4_sysmmu_resource[] = {
-	[0] = {
-		.start	= EXYNOS4_PA_SYSMMU_MDMA,
-		.end	= EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_SYSMMU_MDMA0_0,
-		.end	= IRQ_SYSMMU_MDMA0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start	= EXYNOS4_PA_SYSMMU_SSS,
-		.end	= EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[3] = {
-		.start	= IRQ_SYSMMU_SSS_0,
-		.end	= IRQ_SYSMMU_SSS_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[4] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC0,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[5] = {
-		.start	= IRQ_SYSMMU_FIMC0_0,
-		.end	= IRQ_SYSMMU_FIMC0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[6] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC1,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[7] = {
-		.start	= IRQ_SYSMMU_FIMC1_0,
-		.end	= IRQ_SYSMMU_FIMC1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[8] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC2,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[9] = {
-		.start	= IRQ_SYSMMU_FIMC2_0,
-		.end	= IRQ_SYSMMU_FIMC2_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[10] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC3,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[11] = {
-		.start	= IRQ_SYSMMU_FIMC3_0,
-		.end	= IRQ_SYSMMU_FIMC3_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[12] = {
-		.start	= EXYNOS4_PA_SYSMMU_JPEG,
-		.end	= EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[13] = {
-		.start	= IRQ_SYSMMU_JPEG_0,
-		.end	= IRQ_SYSMMU_JPEG_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[14] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMD0,
-		.end	= EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[15] = {
-		.start	= IRQ_SYSMMU_LCD0_M0_0,
-		.end	= IRQ_SYSMMU_LCD0_M0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[16] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMD1,
-		.end	= EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[17] = {
-		.start	= IRQ_SYSMMU_LCD1_M1_0,
-		.end	= IRQ_SYSMMU_LCD1_M1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[18] = {
-		.start	= EXYNOS4_PA_SYSMMU_PCIe,
-		.end	= EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[19] = {
-		.start	= IRQ_SYSMMU_PCIE_0,
-		.end	= IRQ_SYSMMU_PCIE_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[20] = {
-		.start	= EXYNOS4_PA_SYSMMU_G2D,
-		.end	= EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[21] = {
-		.start	= IRQ_SYSMMU_2D_0,
-		.end	= IRQ_SYSMMU_2D_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[22] = {
-		.start	= EXYNOS4_PA_SYSMMU_ROTATOR,
-		.end	= EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[23] = {
-		.start	= IRQ_SYSMMU_ROTATOR_0,
-		.end	= IRQ_SYSMMU_ROTATOR_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[24] = {
-		.start	= EXYNOS4_PA_SYSMMU_MDMA2,
-		.end	= EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[25] = {
-		.start	= IRQ_SYSMMU_MDMA1_0,
-		.end	= IRQ_SYSMMU_MDMA1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[26] = {
-		.start	= EXYNOS4_PA_SYSMMU_TV,
-		.end	= EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[27] = {
-		.start	= IRQ_SYSMMU_TV_M0_0,
-		.end	= IRQ_SYSMMU_TV_M0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[28] = {
-		.start	= EXYNOS4_PA_SYSMMU_MFC_L,
-		.end	= EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[29] = {
-		.start	= IRQ_SYSMMU_MFC_M0_0,
-		.end	= IRQ_SYSMMU_MFC_M0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[30] = {
-		.start	= EXYNOS4_PA_SYSMMU_MFC_R,
-		.end	= EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[31] = {
-		.start	= IRQ_SYSMMU_MFC_M1_0,
-		.end	= IRQ_SYSMMU_MFC_M1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
+static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
+
+#define SYSMMU_PLATFORM_DEVICE(ipname, devid)				\
+static struct sysmmu_platform_data platdata_##ipname = {		\
+	.dbgname = #ipname,						\
+};									\
+struct platform_device SYSMMU_PLATDEV(ipname) =				\
+{									\
+	.name		= SYSMMU_DEVNAME_BASE,				\
+	.id		= devid,					\
+	.dev		= {						\
+		.dma_mask		= &exynos_sysmmu_dma_mask,	\
+		.coherent_dma_mask	= DMA_BIT_MASK(32),		\
+		.platform_data		= &platdata_##ipname,		\
+	},								\
+}
+
+SYSMMU_PLATFORM_DEVICE(mfc_l,	0);
+SYSMMU_PLATFORM_DEVICE(mfc_r,	1);
+SYSMMU_PLATFORM_DEVICE(tv,	2);
+SYSMMU_PLATFORM_DEVICE(jpeg,	3);
+SYSMMU_PLATFORM_DEVICE(rot,	4);
+SYSMMU_PLATFORM_DEVICE(fimc0,	5); /* fimc* and gsc* exist exclusively */
+SYSMMU_PLATFORM_DEVICE(fimc1,	6);
+SYSMMU_PLATFORM_DEVICE(fimc2,	7);
+SYSMMU_PLATFORM_DEVICE(fimc3,	8);
+SYSMMU_PLATFORM_DEVICE(gsc0,	5);
+SYSMMU_PLATFORM_DEVICE(gsc1,	6);
+SYSMMU_PLATFORM_DEVICE(gsc2,	7);
+SYSMMU_PLATFORM_DEVICE(gsc3,	8);
+SYSMMU_PLATFORM_DEVICE(isp,	9);
+SYSMMU_PLATFORM_DEVICE(fimd0,	10);
+SYSMMU_PLATFORM_DEVICE(fimd1,	11);
+SYSMMU_PLATFORM_DEVICE(camif0,	12);
+SYSMMU_PLATFORM_DEVICE(camif1,	13);
+SYSMMU_PLATFORM_DEVICE(2d,	14);
+
+#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
+
+#define SYSMMU_RESOURCE(core, ipname)					\
+	static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
+
+#define DEFINE_SYSMMU_RESOURCE(core, mem, irq)				\
+	DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem),	\
+	DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
+
+#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq)			\
+	SYSMMU_RESOURCE(core, ipname) {					\
+		DEFINE_SYSMMU_RESOURCE(core, mem, irq)			\
+	}
 
-struct platform_device exynos4_device_sysmmu = {
-	.name		= "s5p-sysmmu",
-	.id		= 32,
-	.num_resources	= ARRAY_SIZE(exynos4_sysmmu_resource),
-	.resource	= exynos4_sysmmu_resource,
+struct sysmmu_resource_map {
+	struct platform_device *pdev;
+	struct resource *res;
+	u32 rnum;
+	struct device *pdd;
+	char *clocknames;
 };
-EXPORT_SYMBOL(exynos4_device_sysmmu);
 
-static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
-void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
-{
-	sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
-	if (IS_ERR(sysmmu_clk[ips]))
-		sysmmu_clk[ips] = NULL;
-	else
-		clk_put(sysmmu_clk[ips]);
+#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) {		\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME,				\
 }
 
-void sysmmu_clk_enable(sysmmu_ips ips)
-{
-	if (sysmmu_clk[ips])
-		clk_enable(sysmmu_clk[ips]);
+#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) {	\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,		\
+}
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) {		\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME,				\
+	.pdd = &exynos##core##_device_pd[pd].dev,			\
+}
+
+#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,		\
+	.pdd = &exynos##core##_device_pd[pd].dev,			\
 }
+#else
+#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd)		\
+		SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
+#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata)	\
+		SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
+
+#endif /* CONFIG_EXYNOS_DEV_PD */
+
+#ifdef CONFIG_ARCH_EXYNOS4
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0,	FIMC0,	FIMC0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1,	FIMC1,	FIMC1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2,	FIMC2,	FIMC2);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3,	FIMC3,	FIMC3);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg,	JPEG,	JPEG);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d,	G2D,	2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv,	TV,	TV_M0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp,	2D_ACP,	2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot,	ROTATOR, ROTATOR);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0,	FIMD0,	LCD0_M0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1,	FIMD1,	LCD1_M1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0,	FIMC_LITE0, FIMC_LITE0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1,	FIMC_LITE1, FIMC_LITE1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r,	MFC_R,	MFC_M0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l,	MFC_L,	MFC_M1);
+SYSMMU_RESOURCE(EXYNOS4, isp) {
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc0,	fimc0,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc1,	fimc1,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc2,	fimc2,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc3,	fimc3,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, tv,	tv,	PD_TV),
+	SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r,	mfc_r,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l,	mfc_l,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_PD(4, rot,	rot,	PD_LCD0),
+	SYSMMU_RESOURCE_MAPPING_PD(4, jpeg,	jpeg,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimd0,	fimd0,	PD_LCD0),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING_PD(4, 2d,	2d,	PD_LCD0),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimd1,	fimd1,	PD_LCD1),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING(4,	2d,	2d_acp),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	camif0, flite0,	PD_ISP),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	camif1, flite1,	PD_ISP),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	isp,	isp,	PD_ISP),
+};
+#endif /* CONFIG_ARCH_EXYNOS4 */
 
-void sysmmu_clk_disable(sysmmu_ips ips)
+#ifdef CONFIG_ARCH_EXYNOS5
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg,	JPEG,	JPEG);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1,	FIMD1,	FIMD1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d,	2D,	2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot,	ROTATOR, ROTATOR);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv,	TV,	TV);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0,	LITE0,	LITE0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1,	LITE1,	LITE1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0,	GSC0,	GSC0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1,	GSC1,	GSC1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2,	GSC2,	GSC2);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3,	GSC3,	GSC3);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r,	MFC_R,	MFC_R);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l,	MFC_L,	MFC_L);
+SYSMMU_RESOURCE(EXYNOS5, isp) {
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5,	ODC, ODC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING(5,	jpeg,	jpeg),
+	SYSMMU_RESOURCE_MAPPING(5,	fimd1,	fimd1),
+	SYSMMU_RESOURCE_MAPPING(5,	2d,	2d),
+	SYSMMU_RESOURCE_MAPPING(5,	rot,	rot),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	tv,	tv,	PD_DISP1),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	camif0,	flite0,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	camif1,	flite1,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc0,	gsc0,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc1,	gsc1,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc2,	gsc2,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc3,	gsc3,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	mfc_r,	mfc_r,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	mfc_l,	mfc_l,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_MCPD(5,	isp,	isp,	PD_ISP, mc_platdata),
+};
+#endif /* CONFIG_ARCH_EXYNOS5 */
+
+static int __init init_sysmmu_platform_device(void)
 {
-	if (sysmmu_clk[ips])
-		clk_disable(sysmmu_clk[ips]);
+	int i, j;
+	struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
+	int nmap[2] = {0, 0};
+
+#ifdef CONFIG_ARCH_EXYNOS5
+	if (soc_is_exynos5250()) {
+		resmap[0] = sysmmu_resmap5;
+		nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
+		nmap[1] = 0;
+	}
+#endif
+
+#ifdef CONFIG_ARCH_EXYNOS4
+	if (resmap[0] == NULL) {
+		resmap[0] = sysmmu_resmap4;
+		nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
+	}
+
+	if (soc_is_exynos4210()) {
+		resmap[1] = sysmmu_resmap4210;
+		nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
+	}
+
+	if (soc_is_exynos4412() || soc_is_exynos4212()) {
+		resmap[1] = sysmmu_resmap4212;
+		nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
+	}
+#endif
+
+	for (j = 0; j < 2; j++) {
+		for (i = 0; i < nmap[j]; i++) {
+			struct sysmmu_resource_map *map;
+			struct sysmmu_platform_data *platdata;
+
+			map = &resmap[j][i];
+
+			map->pdev->dev.parent = map->pdd;
+
+			platdata = map->pdev->dev.platform_data;
+			platdata->clockname = map->clocknames;
+
+			if (platform_device_add_resources(map->pdev, map->res,
+								map->rnum)) {
+				pr_err("%s: Failed to add device resources for "
+						"%s.%d\n", __func__,
+						map->pdev->name, map->pdev->id);
+				continue;
+			}
+
+			if (platform_device_register(map->pdev)) {
+				pr_err("%s: Failed to register %s.%d\n",
+					__func__, map->pdev->name,
+						map->pdev->id);
+			}
+		}
+	}
+
+	return 0;
 }
+arch_initcall(init_sysmmu_platform_device);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 2fd2c25..60c5c81 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -131,23 +131,30 @@
 #define COMBINER_GROUP(x)	((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
 #define COMBINER_IRQ(x, y)	(COMBINER_GROUP(x) + y)
 
-#define IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
-#define IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
-#define IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
-#define IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
-#define IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
-#define IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
-#define IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
-#define IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
-
-#define IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
-#define IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
-#define IRQ_SYSMMU_LCD0_M0_0	COMBINER_IRQ(5, 2)
-#define IRQ_SYSMMU_LCD1_M1_0	COMBINER_IRQ(5, 3)
-#define IRQ_SYSMMU_TV_M0_0	COMBINER_IRQ(5, 4)
-#define IRQ_SYSMMU_MFC_M0_0	COMBINER_IRQ(5, 5)
-#define IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
-#define IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
+#define EXYNOS4_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
+#define EXYNOS4_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
+#define EXYNOS4_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
+#define EXYNOS4_IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
+
+#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
+#define EXYNOS4_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
+#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0	COMBINER_IRQ(5, 2)
+#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0	COMBINER_IRQ(5, 3)
+#define EXYNOS4_IRQ_SYSMMU_TV_M0_0	COMBINER_IRQ(5, 4)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0	COMBINER_IRQ(5, 5)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
+#define EXYNOS4_IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
+
+#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0	COMBINER_IRQ(16, 0)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0	COMBINER_IRQ(16, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0	COMBINER_IRQ(16, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0	COMBINER_IRQ(16, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0	COMBINER_IRQ(16, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0	COMBINER_IRQ(16, 5)
 
 #define IRQ_FIMD0_FIFO		COMBINER_IRQ(11, 0)
 #define IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
@@ -277,70 +284,70 @@
 #define IRQ_PMU			COMBINER_IRQ(1, 2)
 #define IRQ_PMU_CPU1		COMBINER_IRQ(1, 6)
 
-#define IRQ_SYSMMU_GSC0_0	COMBINER_IRQ(2, 0)
-#define IRQ_SYSMMU_GSC0_1	COMBINER_IRQ(2, 1)
-#define IRQ_SYSMMU_GSC1_0	COMBINER_IRQ(2, 2)
-#define IRQ_SYSMMU_GSC1_1	COMBINER_IRQ(2, 3)
-#define IRQ_SYSMMU_GSC2_0	COMBINER_IRQ(2, 4)
-#define IRQ_SYSMMU_GSC2_1	COMBINER_IRQ(2, 5)
-#define IRQ_SYSMMU_GSC3_0	COMBINER_IRQ(2, 6)
-#define IRQ_SYSMMU_GSC3_1	COMBINER_IRQ(2, 7)
-
-#define IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(3, 2)
-#define IRQ_SYSMMU_FIMD1_1	COMBINER_IRQ(3, 3)
-#define IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(3, 4)
-#define IRQ_SYSMMU_LITE0_1	COMBINER_IRQ(3, 5)
-#define IRQ_SYSMMU_SCALERPISP_0	COMBINER_IRQ(3, 6)
-#define IRQ_SYSMMU_SCALERPISP_1	COMBINER_IRQ(3, 7)
-
-#define IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(4, 0)
-#define IRQ_SYSMMU_ROTATOR_1	COMBINER_IRQ(4, 1)
-#define IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 2)
-#define IRQ_SYSMMU_JPEG_1	COMBINER_IRQ(4, 3)
-
-#define IRQ_SYSMMU_FD_0		COMBINER_IRQ(5, 0)
-#define IRQ_SYSMMU_FD_1		COMBINER_IRQ(5, 1)
-#define IRQ_SYSMMU_SCALERCISP_0	COMBINER_IRQ(5, 2)
-#define IRQ_SYSMMU_SCALERCISP_1	COMBINER_IRQ(5, 3)
-#define IRQ_SYSMMU_MCUISP_0	COMBINER_IRQ(5, 4)
-#define IRQ_SYSMMU_MCUISP_1	COMBINER_IRQ(5, 5)
-#define IRQ_SYSMMU_3DNR_0	COMBINER_IRQ(5, 6)
-#define IRQ_SYSMMU_3DNR_1	COMBINER_IRQ(5, 7)
-
-#define IRQ_SYSMMU_ARM_0	COMBINER_IRQ(6, 0)
-#define IRQ_SYSMMU_ARM_1	COMBINER_IRQ(6, 1)
-#define IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(6, 2)
-#define IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(6, 3)
-#define IRQ_SYSMMU_RTIC_0	COMBINER_IRQ(6, 4)
-#define IRQ_SYSMMU_RTIC_1	COMBINER_IRQ(6, 5)
-#define IRQ_SYSMMU_SSS_0	COMBINER_IRQ(6, 6)
-#define IRQ_SYSMMU_SSS_1	COMBINER_IRQ(6, 7)
-
-#define IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(7, 0)
-#define IRQ_SYSMMU_MDMA0_1	COMBINER_IRQ(7, 1)
-#define IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(7, 2)
-#define IRQ_SYSMMU_MDMA1_1	COMBINER_IRQ(7, 3)
-#define IRQ_SYSMMU_TV_0		COMBINER_IRQ(7, 4)
-#define IRQ_SYSMMU_TV_1		COMBINER_IRQ(7, 5)
-#define IRQ_SYSMMU_GPSX_0	COMBINER_IRQ(7, 6)
-#define IRQ_SYSMMU_GPSX_1	COMBINER_IRQ(7, 7)
-
-#define IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(8, 5)
-#define IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(8, 6)
-
-#define IRQ_SYSMMU_DIS1_0	COMBINER_IRQ(9, 4)
-#define IRQ_SYSMMU_DIS1_1	COMBINER_IRQ(9, 5)
-
-#define IRQ_DP			COMBINER_IRQ(10, 3)
-#define IRQ_SYSMMU_DIS0_0	COMBINER_IRQ(10, 4)
-#define IRQ_SYSMMU_DIS0_1	COMBINER_IRQ(10, 5)
-#define IRQ_SYSMMU_ISP_0	COMBINER_IRQ(10, 6)
-#define IRQ_SYSMMU_ISP_1	COMBINER_IRQ(10, 7)
-
-#define IRQ_SYSMMU_ODC_0	COMBINER_IRQ(11, 0)
-#define IRQ_SYSMMU_ODC_1	COMBINER_IRQ(11, 1)
-#define IRQ_SYSMMU_DRC_0	COMBINER_IRQ(11, 6)
-#define IRQ_SYSMMU_DRC_1	COMBINER_IRQ(11, 7)
+#define EXYNOS5_IRQ_SYSMMU_GSC0_0	COMBINER_IRQ(2, 0)
+#define EXYNOS5_IRQ_SYSMMU_GSC0_1	COMBINER_IRQ(2, 1)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_0	COMBINER_IRQ(2, 2)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_1	COMBINER_IRQ(2, 3)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_0	COMBINER_IRQ(2, 4)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_1	COMBINER_IRQ(2, 5)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_0	COMBINER_IRQ(2, 6)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_1	COMBINER_IRQ(2, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(3, 2)
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_1	COMBINER_IRQ(3, 3)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(3, 4)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_1	COMBINER_IRQ(3, 5)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0	COMBINER_IRQ(3, 6)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1	COMBINER_IRQ(3, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(4, 0)
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1	COMBINER_IRQ(4, 1)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 2)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_1	COMBINER_IRQ(4, 3)
+
+#define EXYNOS5_IRQ_SYSMMU_FD_0		COMBINER_IRQ(5, 0)
+#define EXYNOS5_IRQ_SYSMMU_FD_1		COMBINER_IRQ(5, 1)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0	COMBINER_IRQ(5, 2)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1	COMBINER_IRQ(5, 3)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_0	COMBINER_IRQ(5, 4)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_1	COMBINER_IRQ(5, 5)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_0	COMBINER_IRQ(5, 6)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_1	COMBINER_IRQ(5, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ARM_0	COMBINER_IRQ(6, 0)
+#define EXYNOS5_IRQ_SYSMMU_ARM_1	COMBINER_IRQ(6, 1)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_0	COMBINER_IRQ(6, 4)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_1	COMBINER_IRQ(6, 5)
+#define EXYNOS5_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(6, 6)
+#define EXYNOS5_IRQ_SYSMMU_SSS_1	COMBINER_IRQ(6, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(7, 0)
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_1	COMBINER_IRQ(7, 1)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(7, 2)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_1	COMBINER_IRQ(7, 3)
+#define EXYNOS5_IRQ_SYSMMU_TV_0		COMBINER_IRQ(7, 4)
+#define EXYNOS5_IRQ_SYSMMU_TV_1		COMBINER_IRQ(7, 5)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_0	COMBINER_IRQ(7, 6)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_1	COMBINER_IRQ(7, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(8, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_DIS1_0	COMBINER_IRQ(9, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS1_1	COMBINER_IRQ(9, 5)
+
+#define IRQ_DP				COMBINER_IRQ(10, 3)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_0	COMBINER_IRQ(10, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_1	COMBINER_IRQ(10, 5)
+#define EXYNOS5_IRQ_SYSMMU_ISP_0	COMBINER_IRQ(10, 6)
+#define EXYNOS5_IRQ_SYSMMU_ISP_1	COMBINER_IRQ(10, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ODC_0	COMBINER_IRQ(11, 0)
+#define EXYNOS5_IRQ_SYSMMU_ODC_1	COMBINER_IRQ(11, 1)
+#define EXYNOS5_IRQ_SYSMMU_DRC_0	COMBINER_IRQ(11, 6)
+#define EXYNOS5_IRQ_SYSMMU_DRC_1	COMBINER_IRQ(11, 7)
 
 #define IRQ_FIMD1_FIFO		COMBINER_IRQ(18, 4)
 #define IRQ_FIMD1_VSYNC		COMBINER_IRQ(18, 5)
@@ -354,11 +361,11 @@
 #define IRQ_MCT_G2		COMBINER_IRQ(23, 5)
 #define IRQ_MCT_G3		COMBINER_IRQ(23, 6)
 
-#define IRQ_EINT1		COMBINER_IRQ(24, 0)
-#define IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(24, 1)
-#define IRQ_SYSMMU_LITE1_1	COMBINER_IRQ(24, 2)
-#define IRQ_SYSMMU_2D_0		COMBINER_IRQ(24, 5)
-#define IRQ_SYSMMU_2D_1		COMBINER_IRQ(24, 6)
+#define IRQ_EINT1			COMBINER_IRQ(24, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(24, 1)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_1	COMBINER_IRQ(24, 2)
+#define EXYNOS5_IRQ_SYSMMU_2D_0		COMBINER_IRQ(24, 5)
+#define EXYNOS5_IRQ_SYSMMU_2D_1		COMBINER_IRQ(24, 6)
 
 #define IRQ_EINT2		COMBINER_IRQ(25, 0)
 #define IRQ_EINT3		COMBINER_IRQ(25, 1)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index f28f5de..a687642 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -88,6 +88,7 @@
 #define EXYNOS4_PA_PDMA1		0x12690000
 
 #define EXYNOS4_PA_SYSMMU_MDMA		0x10A40000
+#define EXYNOS4_PA_SYSMMU_2D_ACP	0x10A40000
 #define EXYNOS4_PA_SYSMMU_SSS		0x10A50000
 #define EXYNOS4_PA_SYSMMU_FIMC0		0x11A20000
 #define EXYNOS4_PA_SYSMMU_FIMC1		0x11A30000
@@ -96,6 +97,12 @@
 #define EXYNOS4_PA_SYSMMU_JPEG		0x11A60000
 #define EXYNOS4_PA_SYSMMU_FIMD0		0x11E20000
 #define EXYNOS4_PA_SYSMMU_FIMD1		0x12220000
+#define EXYNOS4_PA_SYSMMU_FIMC_ISP	0x12260000
+#define EXYNOS4_PA_SYSMMU_FIMC_DRC	0x12270000
+#define EXYNOS4_PA_SYSMMU_FIMC_FD	0x122A0000
+#define EXYNOS4_PA_SYSMMU_ISPCPU	0x122B0000
+#define EXYNOS4_PA_SYSMMU_FIMC_LITE0	0x123B0000
+#define EXYNOS4_PA_SYSMMU_FIMC_LITE1	0x123C0000
 #define EXYNOS4_PA_SYSMMU_PCIe		0x12620000
 #define EXYNOS4_PA_SYSMMU_G2D		0x12A20000
 #define EXYNOS4_PA_SYSMMU_ROTATOR	0x12A30000
@@ -103,6 +110,37 @@
 #define EXYNOS4_PA_SYSMMU_TV		0x12E20000
 #define EXYNOS4_PA_SYSMMU_MFC_L		0x13620000
 #define EXYNOS4_PA_SYSMMU_MFC_R		0x13630000
+
+#define EXYNOS5_PA_SYSMMU_MDMA1		0x10A40000
+#define EXYNOS5_PA_SYSMMU_SSS		0x10A50000
+#define EXYNOS5_PA_SYSMMU_2D		0x10A60000
+#define EXYNOS5_PA_SYSMMU_MFC_L		0x11200000
+#define EXYNOS5_PA_SYSMMU_MFC_R		0x11210000
+#define EXYNOS5_PA_SYSMMU_ROTATOR	0x11D40000
+#define EXYNOS5_PA_SYSMMU_MDMA2		0x11D50000
+#define EXYNOS5_PA_SYSMMU_JPEG		0x11F20000
+#define EXYNOS5_PA_SYSMMU_IOP		0x12360000
+#define EXYNOS5_PA_SYSMMU_RTIC		0x12370000
+#define EXYNOS5_PA_SYSMMU_GPS		0x12630000
+#define EXYNOS5_PA_SYSMMU_ISP		0x13260000
+#define EXYNOS5_PA_SYSMMU_DRC		0x12370000
+#define EXYNOS5_PA_SYSMMU_SCALERC	0x13280000
+#define EXYNOS5_PA_SYSMMU_SCALERP	0x13290000
+#define EXYNOS5_PA_SYSMMU_FD		0x132A0000
+#define EXYNOS5_PA_SYSMMU_ISPCPU	0x132B0000
+#define EXYNOS5_PA_SYSMMU_ODC		0x132C0000
+#define EXYNOS5_PA_SYSMMU_DIS0		0x132D0000
+#define EXYNOS5_PA_SYSMMU_DIS1		0x132E0000
+#define EXYNOS5_PA_SYSMMU_3DNR		0x132F0000
+#define EXYNOS5_PA_SYSMMU_LITE0		0x13C40000
+#define EXYNOS5_PA_SYSMMU_LITE1		0x13C50000
+#define EXYNOS5_PA_SYSMMU_GSC0		0x13E80000
+#define EXYNOS5_PA_SYSMMU_GSC1		0x13E90000
+#define EXYNOS5_PA_SYSMMU_GSC2		0x13EA0000
+#define EXYNOS5_PA_SYSMMU_GSC3		0x13EB0000
+#define EXYNOS5_PA_SYSMMU_FIMD1		0x14640000
+#define EXYNOS5_PA_SYSMMU_TV		0x14650000
+
 #define EXYNOS4_PA_SPI0			0x13920000
 #define EXYNOS4_PA_SPI1			0x13930000
 #define EXYNOS4_PA_SPI2			0x13940000
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 113836b..de42145 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -130,6 +130,9 @@
 #define EXYNOS4_CLKGATE_SCLKCPU			EXYNOS_CLKREG(0x14800)
 #define EXYNOS4_CLKGATE_IP_CPU			EXYNOS_CLKREG(0x14900)
 
+#define EXYNOS4_CLKGATE_IP_ISP0			EXYNOS_CLKREG(0x18800)
+#define EXYNOS4_CLKGATE_IP_ISP1			EXYNOS_CLKREG(0x18804)
+
 #define EXYNOS4_APLL_LOCKTIME			(0x1C20)	/* 300us */
 
 #define EXYNOS4_APLLCON0_ENABLE_SHIFT		(31)
@@ -245,6 +248,8 @@
 #define EXYNOS5_CLKDIV_PERIC0			EXYNOS_CLKREG(0x10558)
 
 #define EXYNOS5_CLKGATE_IP_ACP			EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_ISP0			EXYNOS_CLKREG(0x0C800)
+#define EXYNOS5_CLKGATE_IP_ISP1			EXYNOS_CLKREG(0x0C804)
 #define EXYNOS5_CLKGATE_IP_GSCL			EXYNOS_CLKREG(0x10920)
 #define EXYNOS5_CLKGATE_IP_DISP1		EXYNOS_CLKREG(0x10928)
 #define EXYNOS5_CLKGATE_IP_MFC			EXYNOS_CLKREG(0x1092C)
diff --git a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
deleted file mode 100644
index 68ff6ad..0000000
--- a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * EXYNOS4 - System MMU register
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_SYSMMU_H
-#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
-
-#define S5P_MMU_CTRL			0x000
-#define S5P_MMU_CFG			0x004
-#define S5P_MMU_STATUS			0x008
-#define S5P_MMU_FLUSH			0x00C
-#define S5P_PT_BASE_ADDR		0x014
-#define S5P_INT_STATUS			0x018
-#define S5P_INT_CLEAR			0x01C
-#define S5P_PAGE_FAULT_ADDR		0x024
-#define S5P_AW_FAULT_ADDR		0x028
-#define S5P_AR_FAULT_ADDR		0x02C
-#define S5P_DEFAULT_SLAVE_ADDR		0x030
-
-#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
index 6a5fbb5..998daf2 100644
--- a/arch/arm/mach-exynos/include/mach/sysmmu.h
+++ b/arch/arm/mach-exynos/include/mach/sysmmu.h
@@ -1,46 +1,66 @@
-/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * Samsung sysmmu driver for EXYNOS4
+ * EXYNOS - System MMU support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_ARCH_SYSMMU_H
-#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
-
-enum exynos4_sysmmu_ips {
-	SYSMMU_MDMA,
-	SYSMMU_SSS,
-	SYSMMU_FIMC0,
-	SYSMMU_FIMC1,
-	SYSMMU_FIMC2,
-	SYSMMU_FIMC3,
-	SYSMMU_JPEG,
-	SYSMMU_FIMD0,
-	SYSMMU_FIMD1,
-	SYSMMU_PCIe,
-	SYSMMU_G2D,
-	SYSMMU_ROTATOR,
-	SYSMMU_MDMA2,
-	SYSMMU_TV,
-	SYSMMU_MFC_L,
-	SYSMMU_MFC_R,
-	EXYNOS4_SYSMMU_TOTAL_IPNUM,
+ */
+
+#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
+#define _ARM_MACH_EXYNOS_SYSMMU_H_
+
+struct sysmmu_platform_data {
+	char *dbgname;
+	/* comma(,) separated list of clock names for clock gating */
+	char *clockname;
 };
 
-#define S5P_SYSMMU_TOTAL_IPNUM		EXYNOS4_SYSMMU_TOTAL_IPNUM
+#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
+
+#define SYSMMU_CLOCK_NAME "sysmmu"
+#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
+
+#ifdef CONFIG_EXYNOS_DEV_SYSMMU
+#include <linux/device.h>
+struct platform_device;
+
+#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
+
+extern struct platform_device SYSMMU_PLATDEV(mfc_l);
+extern struct platform_device SYSMMU_PLATDEV(mfc_r);
+extern struct platform_device SYSMMU_PLATDEV(tv);
+extern struct platform_device SYSMMU_PLATDEV(jpeg);
+extern struct platform_device SYSMMU_PLATDEV(rot);
+extern struct platform_device SYSMMU_PLATDEV(fimc0);
+extern struct platform_device SYSMMU_PLATDEV(fimc1);
+extern struct platform_device SYSMMU_PLATDEV(fimc2);
+extern struct platform_device SYSMMU_PLATDEV(fimc3);
+extern struct platform_device SYSMMU_PLATDEV(gsc0);
+extern struct platform_device SYSMMU_PLATDEV(gsc1);
+extern struct platform_device SYSMMU_PLATDEV(gsc2);
+extern struct platform_device SYSMMU_PLATDEV(gsc3);
+extern struct platform_device SYSMMU_PLATDEV(isp);
+extern struct platform_device SYSMMU_PLATDEV(fimd0);
+extern struct platform_device SYSMMU_PLATDEV(fimd1);
+extern struct platform_device SYSMMU_PLATDEV(camif0);
+extern struct platform_device SYSMMU_PLATDEV(camif1);
+extern struct platform_device SYSMMU_PLATDEV(2d);
 
-extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
+#ifdef CONFIG_IOMMU_API
+static inline void platform_set_sysmmu(
+				struct device *sysmmu, struct device *dev)
+{
+	dev->archdata.iommu = sysmmu;
+}
+#endif
 
-typedef enum exynos4_sysmmu_ips sysmmu_ips;
+#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
+#define platform_set_sysmmu(dev, sysmmu) do { } while (0)
+#endif
 
-void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
-void sysmmu_clk_enable(sysmmu_ips ips);
-void sysmmu_clk_disable(sysmmu_ips ips);
+#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
 
-#endif /* __ASM_ARM_ARCH_SYSMMU_H */
+#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index a1e7007..6ab171c 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -154,7 +154,6 @@ static struct platform_device *armlex4210_devices[] __initdata = {
 	&s3c_device_hsmmc3,
 	&s3c_device_rtc,
 	&s3c_device_wdt,
-	&exynos4_device_sysmmu,
 	&samsung_asoc_dma,
 	&armlex4210_smsc911x,
 	&exynos4_device_ahci,
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 2b71f18..49975ad 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -275,7 +275,6 @@ static struct platform_device *smdkv310_devices[] __initdata = {
 	&s5p_device_mfc_l,
 	&s5p_device_mfc_r,
 	&exynos4_device_spdif,
-	&exynos4_device_sysmmu,
 	&samsung_asoc_dma,
 	&samsung_asoc_idma,
 	&s5p_device_fimd0,
-- 
1.7.1



From olof at lixom.net  Sat Mar 10 13:24:25 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 10:24:25 -0800
Subject: [GIT PULL 1/7] non-critical fixes part3 for upcoming merge window
In-Reply-To: <4f591c4d.e471340a.1f3f.3a69SMTPIN_ADDED@mx.google.com>
References: <4f591c4d.e471340a.1f3f.3a69SMTPIN_ADDED@mx.google.com>
Message-ID: <20120310182425.GA698@quad.lixom.net>

On Thu, Mar 08, 2012 at 12:53:29PM -0800, Tony Lindgren wrote:
> Hi Olof,
> 
> Here are two more pre-emptive fixes for upcoming merge
> window to pull into arm-soc/next/fixes-non-critical.
> 
> Now with the fixes finallny out of the way after all
> the cleanup related changes, as a reply to this pull
> request I'm posting some more pull requests for cleanup
> and some minor board changes.

Pulled request 1-7.


Thanks,

-Olof


From rusty at rustcorp.com.au  Thu Mar  8 23:26:52 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 09 Mar 2012 14:56:52 +1030
Subject: [PATCH 7/8] ARM: KVM: guest_didnt_mean_it()
Message-ID: <1331267212.26948.rusty@rustcorp.com.au>


From: Rusty Russell <rusty at rustcorp.com.au>

Conditional instructions may trap even if the condition isn't true, so a good
hypervisor will check this.  The same can happen with undefined instructions,
so the kernel should be doing this dance already (it isn't).

(See p1206 of ARMv7-A ARM)

Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
---
 arch/arm/include/asm/kvm_arm.h     |    4 +++
 arch/arm/include/asm/kvm_emulate.h |    2 +
 arch/arm/kvm/Makefile              |    2 +
 arch/arm/kvm/arm.c                 |    3 ++
 arch/arm/kvm/emulate.c             |   41 +++++++++++++++++++++++++++
 arch/arm/kvm/kvm_cond_match.S      |   54 ++++++++++++++++++++++++++++++++++++
 6 files changed, 105 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/kvm/kvm_cond_match.S

diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index 1769187..156284a 100644
--- a/arch/arm/include/asm/kvm_arm.h
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -107,6 +107,10 @@
 #define HSR_ISS		(HSR_IL - 1)
 #define HSR_ISV_SHIFT	(24)
 #define HSR_ISV		(1U << HSR_ISV_SHIFT)
+#define HSR_CV_SHIFT	(24)
+#define HSR_CV		(1U << HSR_CV_SHIFT)
+#define HSR_COND_SHIFT	(20)
+#define HSR_COND	(0xfU << HSR_COND_SHIFT)
 
 #define HSR_EC_UNKNOWN	(0x00)
 #define HSR_EC_WFI	(0x01)
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index fa54247..fe21e86 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -49,6 +49,8 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_emulate_mmio_ls(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
 			unsigned long instr);
+bool kvm_should_not_have_trapped(struct kvm_vcpu *vcpu);
+bool kvm_cond_match(u32 flags, u32 cond);
 
 /*
  * Return the SPSR for the specified mode of the virtual CPU.
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index e69a8e1..68f05b9 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -12,6 +12,6 @@ obj-$(CONFIG_KVM_ARM_HOST) += init.o interrupts.o exports.o
 
 kvm-arm-y += $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
 
-kvm-arm-y += arm.o guest.o mmu.o emulate.o
+kvm-arm-y += arm.o guest.o mmu.o emulate.o kvm_cond_match.o
 
 obj-$(CONFIG_KVM) += kvm-arm.o
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index a6cf02b..1724657 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -414,6 +414,9 @@ static inline int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
 		BUG();
 	}
 
+	if (kvm_should_not_have_trapped(vcpu))
+		return 0;
+
 	return arm_exit_handlers[hsr_ec](vcpu, run);
 }
 
diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
index bd2c3dc..11e2dab 100644
--- a/arch/arm/kvm/emulate.c
+++ b/arch/arm/kvm/emulate.c
@@ -659,3 +659,44 @@ int kvm_emulate_mmio_ls(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
 	*vcpu_reg(vcpu, 15) += 4;
 	return 0;
 }
+
+/* Some implementations may not check condition codes before trapping! */
+bool kvm_should_not_have_trapped(struct kvm_vcpu *vcpu)
+{
+	unsigned long spsr, cond, flags;
+
+	/*
+	 * Exception Code 0 can only happen if we set HCR.TGE to 1, to
+	 * catch undefined instructions, and then we won't get past
+	 * the arm_exit_handlers test anyway.
+	 */
+	BUG_ON(((vcpu->arch.hsr & HSR_EC) >> HSR_EC_SHIFT) == 0);
+
+	/* Top two bits non-zero?  Unconditional. */
+	if (vcpu->arch.hsr >> 30)
+		return false;
+
+	spsr = *vcpu_spsr(vcpu);
+
+	/* Is condition field valid? */
+	if ((vcpu->arch.hsr & HSR_CV) >> HSR_CV_SHIFT)
+		cond = (vcpu->arch.hsr & HSR_COND) >> HSR_COND_SHIFT;
+	else {
+		/* This can happen in Thumb mode: examine IT state. */
+		unsigned long it;
+		
+		it = ((spsr >> 8) & 0xFC)
+			| ((spsr >> 25) & 0x3);
+
+		/* it == 0 => unconditional. */
+		if (it == 0)
+			return false;
+
+		/* The cond for this insn works out as the top 4 bits. */
+		cond = (it >> 4);
+	}
+
+	flags = spsr & ~0x07FFFFFF;
+
+	return !kvm_cond_match(flags, cond);
+}
diff --git a/arch/arm/kvm/kvm_cond_match.S b/arch/arm/kvm/kvm_cond_match.S
new file mode 100644
index 0000000..cf48786
--- /dev/null
+++ b/arch/arm/kvm/kvm_cond_match.S
@@ -0,0 +1,54 @@
+#include <linux/linkage.h>
+
+/* extern bool kvm_cond_match(u32 flags, u32 cond); */
+ENTRY(kvm_cond_match)
+.arm
+	/* First, set our condition flags to the arg. */
+	mrs	r2, cpsr
+	and	r2, r2, #0x07FFFFFF
+	orr	r2, r2, r0
+	msr	cpsr, r2
+
+	/* Now, jump to table depending on cond, return via there. */
+	mov	r0, #0
+	add	r2, r0, r1, LSL #3
+	sub	r2, #4
+	add	pc, r2
+
+/* This is "mov<cond>	r0, #1" */
+#define COND_MOVEQ_R0_1(cond) .word	((cond << 28) | 0x03a00001)
+
+cond_table:
+	COND_MOVEQ_R0_1(0)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(1)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(2)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(3)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(4)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(5)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(6)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(7)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(8)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(9)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(10)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(11)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(12)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(13)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(14)
+	mov	pc, lr
+	COND_MOVEQ_R0_1(15)
+	mov	pc, lr
+ENDPROC(kvm_cond_match)



From olof at lixom.net  Sat Mar 10 13:05:15 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 10:05:15 -0800
Subject: [GIT PULL 2/4] Samsung devel-pd for v3.4
In-Reply-To: <4F5B7C81.6080301@samsung.com>
References: <4F5B7C81.6080301@samsung.com>
Message-ID: <CAOesGMjff3gVNJQ5FpJuSf+uvVDW8k22b+Xcikot-isM-4-6iw@mail.gmail.com>

Hi Rafael,

The below series contains two patches that have been sent to you, and
that are sitting in the pm-domains branch.

Two questions before I pull this into arm-soc:

1) Are you 100% sure this will be submitted to 3.4? And if so, will
you send it early during the merge window?
2) Are you 100% sure you will not rebase the branch into which you
pulled the v3.4-for-rafael branch?

I am asking because if we pull this in, and you rebase between now and
when it's sent in, we're risking merge conflicts that will be painful
to resolve. We've been bitten by that from other dependencies in the
past so we're being careful.


Thanks,

-Olof

On Sat, Mar 10, 2012 at 8:08 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Hi Arnd, Olof,
>
> This is Generic Power Domain patches for EXYNOS. Basically, Thomas' patches,
> adding support Generic Power Domain patches are in Rafael's tree,
> linux-pm/linux-next and see below merge commit.
> http://git.kernel.org/?p=linux/kernel/git/rafael/linux-pm.git;a=commit;h=dcaad77a8074b6de58e745546bc543d5538404f2
> And this adds hooking up G2D and JPEG to Generic PD.
>
> Please pull and here is my preferred resolution when merge this after
> next/board-samsung.
>
> diff --cc arch/arm/mach-exynos/mach-universal_c210.c
> index 3663aee,0262417..0b944eb
> --- a/arch/arm/mach-exynos/mach-universal_c210.c
> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
> @@@ -1053,10 -981,6 +1052,7 @@@ static struct platform_device *universa
> ? ? ? ?&s5p_device_mfc,
> ? ? ? ?&s5p_device_mfc_l,
> ? ? ? ?&s5p_device_mfc_r,
> - ? ? ? &exynos4_device_pd[PD_MFC],
> - ? ? ? &exynos4_device_pd[PD_LCD0],
> - ? ? ? &exynos4_device_pd[PD_CAM],
> ?+ ? ? ?&cam_vt_dio_fixed_reg_dev,
> ? ? ? ?&cam_i_core_fixed_reg_dev,
> ? ? ? ?&cam_s_if_fixed_reg_dev,
> ? ? ? ?&s5p_device_fimc_md,
>
> If any problems, please kindly let me know.
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
>
> ?Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)
>
> are available in the git repository at:
> ?git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/devel-samsung-pd
>
> Sachin Kamat (2):
> ? ? ?ARM: EXYNOS: Hook up G2D PD to generic PD infrastructure
> ? ? ?ARM: EXYNOS: Hook up JPEG PD to generic PD infrastructure
>
> Thomas Abraham (2):
> ? ? ?PM / Domains: Add OF support
> ? ? ?ARM: EXYNOS: Hook up power domains to generic power domain
> infrastructure
>
> ?.../bindings/arm/exynos/power_domain.txt ? ? ? ? ? | ? 21 ++
> ?arch/arm/mach-exynos/Kconfig ? ? ? ? ? ? ? ? ? ? ? | ? 10 +-
> ?arch/arm/mach-exynos/Makefile ? ? ? ? ? ? ? ? ? ? ?| ? ?2 +-
> ?arch/arm/mach-exynos/dev-pd.c ? ? ? ? ? ? ? ? ? ? ?| ?139 --------------
> ?arch/arm/mach-exynos/mach-nuri.c ? ? ? ? ? ? ? ? ? | ? 11 -
> ?arch/arm/mach-exynos/mach-origen.c ? ? ? ? ? ? ? ? | ? 14 --
> ?arch/arm/mach-exynos/mach-smdkv310.c ? ? ? ? ? ? ? | ? 12 --
> ?arch/arm/mach-exynos/mach-universal_c210.c ? ? ? ? | ? 17 --
> ?arch/arm/mach-exynos/pm_domains.c ? ? ? ? ? ? ? ? ?| ?201
> ++++++++++++++++++++
> ?drivers/base/power/domain.c ? ? ? ? ? ? ? ? ? ? ? ?| ? 32 +++
> ?include/linux/pm_domain.h ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 12 ++
> ?11 files changed, 268 insertions(+), 203 deletions(-)
> ?create mode 100644
> Documentation/devicetree/bindings/arm/exynos/power_domain.txt
> ?delete mode 100644 arch/arm/mach-exynos/dev-pd.c
> ?create mode 100644 arch/arm/mach-exynos/pm_domains.c


From olof at lixom.net  Sat Mar 10 12:35:26 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 09:35:26 -0800
Subject: [GIT PULL] Samsung Cleanup EXYNOS clock for v3.4
In-Reply-To: <4F5B74C1.3080200@samsung.com>
References: <4F589474.8050609@samsung.com>
 <CAOesGMiWOChuMjLQTK1pGys+oXCc4A=HO-2_=37rh3M6pgUP_g@mail.gmail.com>
 <4F5A22AD.1070907@samsung.com> <4F5B74C1.3080200@samsung.com>
Message-ID: <20120310173526.GB5972@quad.lixom.net>

On Sat, Mar 10, 2012 at 07:35:29AM -0800, Kukjin Kim wrote:
> On 03/09/12 07:33, Kukjin Kim wrote:
> >On 03/08/12 07:16, Olof Johansson wrote:
> >>Hi,
> >>
> >>On Thu, Mar 8, 2012 at 3:13 AM, Kukjin Kim<kgene.kim at samsung.com> wrote:
> >>
> >>>Kukjin Kim (2):
> >>>ARM: EXYNOS: cleanup clock part for new EXYNOS SoCs
> >>
> >>This is one large commit that does many things in one change. As the
> >>patch message says:
> >>
> >>ARM: EXYNOS: cleanup clock part for new EXYNOS SoCs
> >>
> >>- the prefix of clk register replace S5P_ with EXYNOS4_
> >>- move mach-exynos/clock.c to mach-exynos/clock-exynos4.c
> >>- according to moving clock-exynos4.c,
> >>move<mach/exynos4-clock.h> to "clock-exynos4.h"
> >>- add prefix exynos4_ on clk declaration
> >>
> >>It makes it hard to review, especially when you combine a move with
> >>other changes. It's better to do the move in a separate commit that
> >>doesn't change code (or only changes very very little) and then do the
> >>other changes in separate commits later.
> >>
> >Hmm...OK, let me do as per your suggestion and will re-send this soon.
> >
> Hi Olof,
> 
> I addressed comments from you and I think it should be ok to you.

Yes, much easier to review.


> Please pull from:

> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/cleanup-exynos-clock
> 
> If any problems, please kindly let me know.
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> 
> 
> The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
> 
>   Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)
> 
> are available in the git repository at:

> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/cleanup-exynos-clock


The contents of the branch itself looks good, but now you have introduced
a modified/delete conflict with yourself.

You modify arch/arm/mach-exynos/clock.c in your cleanup-use-static branch, and
then you move it here. That means that when I merge in this branch, git throws
a conflict and I have to do manual edits to make the contents match.

It's better if you base this branch on your cleanup-use-static branch, so that
the move includes those edits. That way there is no conflict resolution to do
at our end either.

Can you please do that rebase and send a fresh pull request? I'll continue
looking at your other requests meanwhile.


Thanks!

-Olof


From olof at lixom.net  Sat Mar 10 12:22:27 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 09:22:27 -0800
Subject: [PATCH 1/5] ARM: EXYNOS: replace clock.c for other new EXYNOS SoCs
In-Reply-To: <1331374749-23256-2-git-send-email-kgene.kim@samsung.com>
References: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>
 <1331374749-23256-2-git-send-email-kgene.kim@samsung.com>
Message-ID: <20120310172227.GA5972@quad.lixom.net>

On Sat, Mar 10, 2012 at 02:19:05AM -0800, Kukjin Kim wrote:
> This patch changes the name of clock.c to clock-exynos4.c for other
> EXYNOS series such as EXYNOS5. And since the header file of clock
> is used only in arch/arm/mach-exynos, moves it in the local directory.
> 
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>

Thanks, much easier to review this way!

Ideally the whitespace cleanup could also be split up to a separate
patch that has _no_ contents changes besides whitespace, but this is OK
too since it's easy to see what's a change and not anyway.


-Olof


From hvaibhav at ti.com  Mon Mar 12 06:15:05 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 12 Mar 2012 10:15:05 +0000
Subject: [PATCH] ARM: OMAP2+: hwmod: Fix wrong SYSC_TYPE1_XXX_MASK bit
 definitions
In-Reply-To: <4F3E581E.1050009@ti.com>
References: <1329477961-1307-1-git-send-email-hvaibhav@ti.com>
 <4F3E581E.1050009@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831810F23@DBDE01.ent.ti.com>

On Fri, Feb 17, 2012 at 19:07:34, Cousson, Benoit wrote:
> On 2/17/2012 12:26 PM, Vaibhav Hiremath wrote:
> > In the SYSC_TYPE1_XXX_MASK configuration, SYSC_XXX_SHIFT macro
> > is used which is not defined anywhere in the kernel.
> > Until now the build was going through successfully, since it
> > is not being used anywhere in kernel.
> 
> Good catch.
> 
> > This bug got introduced by the commit
> > 358f0e630d5409ab3837b86db3595560eae773b6 ("OMAP3: hwmod: support
> > to specify the offset position of various SYSCONFIG register bits.")
> >
> > Signed-off-by: Vaibhav Hiremath<hvaibhav at ti.com>
> 
> Acked-by: Benoit Cousson <b-cousson at ti.com>
> 

Tony/Paul,

Can you accept/merge this patch? 

Thanks,
Vaibhav

> Regards,
> Benoit
> 
> 
> > ---
> >   arch/arm/plat-omap/include/plat/omap_hwmod.h |   12 ++++++------
> >   1 files changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
> > index dbc18ad..55bef2b 100644
> > --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
> > +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
> > @@ -49,17 +49,17 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4;
> >    * with the original PRCM protocol defined for OMAP2420
> >    */
> >   #define SYSC_TYPE1_MIDLEMODE_SHIFT	12
> > -#define SYSC_TYPE1_MIDLEMODE_MASK	(0x3<<  SYSC_MIDLEMODE_SHIFT)
> > +#define SYSC_TYPE1_MIDLEMODE_MASK	(0x3<<  SYSC_TYPE1_MIDLEMODE_SHIFT)
> >   #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT	8
> > -#define SYSC_TYPE1_CLOCKACTIVITY_MASK	(0x3<<  SYSC_CLOCKACTIVITY_SHIFT)
> > +#define SYSC_TYPE1_CLOCKACTIVITY_MASK	(0x3<<  SYSC_TYPE1_CLOCKACTIVITY_SHIFT)
> >   #define SYSC_TYPE1_SIDLEMODE_SHIFT	3
> > -#define SYSC_TYPE1_SIDLEMODE_MASK	(0x3<<  SYSC_SIDLEMODE_SHIFT)
> > +#define SYSC_TYPE1_SIDLEMODE_MASK	(0x3<<  SYSC_TYPE1_SIDLEMODE_SHIFT)
> >   #define SYSC_TYPE1_ENAWAKEUP_SHIFT	2
> > -#define SYSC_TYPE1_ENAWAKEUP_MASK	(1<<  SYSC_ENAWAKEUP_SHIFT)
> > +#define SYSC_TYPE1_ENAWAKEUP_MASK	(1<<  SYSC_TYPE1_ENAWAKEUP_SHIFT)
> >   #define SYSC_TYPE1_SOFTRESET_SHIFT	1
> > -#define SYSC_TYPE1_SOFTRESET_MASK	(1<<  SYSC_SOFTRESET_SHIFT)
> > +#define SYSC_TYPE1_SOFTRESET_MASK	(1<<  SYSC_TYPE1_SOFTRESET_SHIFT)
> >   #define SYSC_TYPE1_AUTOIDLE_SHIFT	0
> > -#define SYSC_TYPE1_AUTOIDLE_MASK	(1<<  SYSC_AUTOIDLE_SHIFT)
> > +#define SYSC_TYPE1_AUTOIDLE_MASK	(1<<  SYSC_TYPE1_AUTOIDLE_SHIFT)
> >
> >   /*
> >    * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
> > --
> > 1.7.0.4
> >
> 
> 



From rnayak at ti.com  Fri Mar  9 04:26:07 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 09 Mar 2012 14:56:07 +0530
Subject: [PATCH v2 4/4] arm/dts: OMAP3: Add mmc controller nodes and board
 data
In-Reply-To: <20120309054608.647473E0901@localhost>
References: <1329998490-27555-1-git-send-email-rnayak@ti.com>
 <1329998490-27555-5-git-send-email-rnayak@ti.com>
 <20120223185718.GZ18185@atomide.com> <4F470B71.1020308@ti.com>
 <20120224184859.GN18185@atomide.com> <20120309054608.647473E0901@localhost>
Message-ID: <4F59CCAF.1090806@ti.com>

On Friday 09 March 2012 11:16 AM, Grant Likely wrote:
> On Fri, 24 Feb 2012 10:49:00 -0800, Tony Lindgren<tony at atomide.com>  wrote:
>> * Rajendra Nayak<rnayak at ti.com>  [120223 19:29]:
>>> On Friday 24 February 2012 12:27 AM, Tony Lindgren wrote:
>>>>> --- a/arch/arm/boot/dts/omap3.dtsi
>>>>> +++ b/arch/arm/boot/dts/omap3.dtsi
>>>>> @@ -113,5 +113,31 @@
>>>>>   			#size-cells =<0>;
>>>>>   			ti,hwmods = "i2c3";
>>>>>   		};
>>>>> +
>>>>> +		mmc1: mmc at 1 {
>>>>> +			compatible = "ti,omap2-hsmmc";
>>>>> +			ti,hwmods = "mmc1";
>>>>> +			ti,dual-volt;
>>>>> +		};
>>>>> +
>>>>> +		mmc2: mmc at 2 {
>>>>> +			compatible = "ti,omap2-hsmmc";
>>>>> +			ti,hwmods = "mmc2";
>>>>> +		};
>>>>> +
>>>>> +		mmc3: mmc at 3 {
>>>>> +			compatible = "ti,omap2-hsmmc";
>>>>> +			ti,hwmods = "mmc3";
>>>>> +		};
>>>>> +
>>>>> +		mmc4: mmc at 4 {
>>>>> +			compatible = "ti,omap2-hsmmc";
>>>>> +			ti,hwmods = "mmc4";
>>>>> +		};
>>>>> +
>>>>> +		mmc5: mmc at 5 {
>>>>> +			compatible = "ti,omap2-hsmmc";
>>>>> +			ti,hwmods = "mmc5";
>>>>> +		};
>>>>>   	};
>>>>>   };
>>>>
>>>> These all should all be "ti,omap3-hsmmc" I guess?
>>>
>>> Well, I defined the binding such that both omap2 and omap3
>>> can use the same compatible "ti,omap2-hsmmc" since there is
>>> no difference in the way they are defined or handled. If thats
>>> confusing, I can have separate compatibles.
>>> Btw, I guess we do the same with a few other re-used IPs as well,
>>> I just checked and mcpsi does the same.
>>
>> Yeah let's use separate compatibles to avoid confusion.
>> For omap2 we also have the ti,omap2-mmc in addition to
>> ti,omap2-hsmmc..
>
> Yes, absolutely use separate compatible values.  It is always important
> to be specific as to the silicon implementing the IP.  The omap3 instance
> can also carry the omap2 string in its compatible list:
>
> 	compatible = "ti,omap3-hsmmc", "ti,omap2-hsmmc";

Sure, will repost with seperate compatible strings. Also missed adding
the 'status = "disable";' for unused mmc blocks in the board .dts file
causing unused mmc modules to get probed too. Will fix that as well.

thanks,
Rajendra

>
> g.



From s.hauer at pengutronix.de  Fri Mar  9 06:06:14 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 9 Mar 2012 12:06:14 +0100
Subject: [PATCH v6] ARM : mx35: 3ds-board: add framebuffer device
In-Reply-To: <1331269521-20784-1-git-send-email-b39297@freescale.com>
References: <1331269521-20784-1-git-send-email-b39297@freescale.com>
Message-ID: <20120309110614.GC3852@pengutronix.de>

On Fri, Mar 09, 2012 at 01:05:21PM +0800, Wu Guoxing wrote:
> From: wu guoxing <b39297 at freescale.com>
> 
> This patch adds framebuffer support for freescale mx35 3ds board
> 
> Signed-off-by: Wu Guoxing <b39297 at freescale.com>
> 
>  arch/arm/mach-imx/mach-mx35_3ds.c |  121 +++++++++++++++++++++++++++++++++++++
>  1 files changed, 121 insertions(+), 0 deletions(-)
> 
> +static int lcd_power_gpio = -ENXIO;
> +
> +static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
> +						     void *data)
> +{
> +	return !strcmp(chip->label, data);
> +}
> +
> +static int mc9s08dz60_lcd_gpio_get(void)
> +{
> +	struct gpio_chip *chip;
> +
> +	if (!gpio_is_valid(lcd_power_gpio)) {
> +		chip = gpiochip_find(
> +				"mc9s08dz60", mc9s08dz60_gpiochip_match);
> +		if (chip) {
> +			lcd_power_gpio = chip->base + 6;
> +			if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
> +				pr_err("error: gpio already requested by other!\n");
> +				lcd_power_gpio = -ENXIO;
> +			}
> +		} else {
> +			pr_err("error: didn't find mc9s08dz60 gpio chip\n");
> +			lcd_power_gpio = -ENXIO;
> +		}
> +	}
> +
> +	return lcd_power_gpio;
> +}
> +
> +static void mx35_3ds_lcd_set_power(struct plat_lcd_data *pd, unsigned int power)
> +{
> +	int gpio;
> +
> +	gpio = mc9s08dz60_lcd_gpio_get();
> +	if (gpio_is_valid(gpio))
> +		gpio_set_value_cansleep(gpio, power);
> +}

This looks unnecessary complicated. Please fold mc9s08dz60_lcd_gpio_get
into mx35_3ds_lcd_set_power:

	if (!gpio_is_valid()) {
		request()
	}

	if (gpio_is_valid()) {
		set_value()
	}

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From tomi.valkeinen at ti.com  Fri Mar  9 02:55:00 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 09 Mar 2012 09:55:00 +0200
Subject: [PATCH] ARM: OMAP2+: Fix compile error when FB_OMAP2 is not set
In-Reply-To: <20120308204328.GW12083@atomide.com>
References: <20120308204328.GW12083@atomide.com>
Message-ID: <1331279700.1927.1.camel@deskari>

On Thu, 2012-03-08 at 12:43 -0800, Tony Lindgren wrote:
> Otherwise we will get:
> 
> arch/arm/plat-omap/fb.c:101: error: expected ?)? before ?*? token
> 
> Signed-off-by: Tony Lindgren <tony at atomide.com>

Thanks. It seems I need to improve my testing practices to include
non-FB builds also...

 Tomi

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From s.hauer at pengutronix.de  Fri Mar  9 08:08:03 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 9 Mar 2012 14:08:03 +0100
Subject: [PATCH v2 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <CACKLOr3Y9BW_pMUnr6q4eH2c+2=jQ2WHEjWprb=O5wFrS9=T=A@mail.gmail.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
 <20120309105645.GA3852@pengutronix.de>
 <CACKLOr3Y9BW_pMUnr6q4eH2c+2=jQ2WHEjWprb=O5wFrS9=T=A@mail.gmail.com>
Message-ID: <20120309130803.GD3852@pengutronix.de>

On Fri, Mar 09, 2012 at 01:04:36PM +0100, javier Martin wrote:
> Hi Sascha,
> thank you for your time.
> 
> On 9 March 2012 11:56, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > On Wed, Mar 07, 2012 at 03:33:32PM +0100, Javier Martin wrote:
> >> The following series have to be applied on top of the following patches:
> >> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
> >> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
> >>
> >> As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
> >> is deprecated and no new patches are accepted for it.
> >>
> >> This series merges this code into the imx-dma.c dmaengine driver.
> >>
> >> Changes since v1:
> >> ?- Merge patch 14 with 01.
> >> ?- Add a proper changelog to each patch of the series.
> >>
> >> [PATCH v2 01/13] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
> >> [PATCH v2 02/13] dmaengine: imx-dma: remove data member from internal structure.
> >> [PATCH v2 03/13] dmaengine: imx-dma: remove dma_mode member of internal structure.
> >> [PATCH v2 04/13] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
> >> [PATCH v2 05/13] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
> >> [PATCH v2 06/13] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
> >> [PATCH v2 07/13] dmaengine: imx-dma: remove sg member from internal structure.
> >> [PATCH v2 08/13] dmaengine: imx-dma: remove 'in_use' field of 'internal' structure.
> >> [PATCH v2 09/13] dmaengine: imx-dma: remove 'resbytes' field of 'internal' structure.
> >> [PATCH v2 10/13] dmaengine: imx-dma: remove internal structure.
> >> [PATCH v2 11/13] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
> >> [PATCH v2 12/13] dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and 'dma_clk'.
> >> [PATCH v2 13/13] dmaengine: imx-dma: use 'dev_dbg' and 'dev_warn' for messages.
> >
> > I didn't look at the individual patches but only on the end result and
> > overall it looks good. There are several things left for further cleanup:
> >
> > - use resources for irq and base address
> > - use platform device id rather than cpu_is_* to distinguish
> > ?between the different device types.
> > - request_irq for i.MX21/27 in alloc_chan_resources instead in probe
> > - Use all available channels. In the time we had dmaengine users and
> > ?legacy API users 8 channels were reserved for the old API and 8
> > ?channels for the dmaengine API.
> >
> > I think the first three points can be done in a later series, the last
> > one should be trivial to fix now.
> 
> I agree. Let me fix the last issue you mention in a v3 of the involved patch.
> 
> > Some comments follow to the individual patches.
> >
> > And, oh:
> >
> > Tested-by: Sascha Hauer <s.hauer at pengutronix.de
> 
> Cool. Did you test it for any other platform than i.MX27?

Nope, only i.MX27

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From rusty at rustcorp.com.au  Thu Mar  8 23:44:31 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 09 Mar 2012 15:14:31 +1030
Subject: [PATCH 1/8] ARM: KVM: Fix missing clobber (causes host oops on UP)
In-Reply-To: <1331267212.8104.rusty@rustcorp.com.au>
References: <1331267212.8104.rusty@rustcorp.com.au>
Message-ID: <878vja1iz4.fsf@rustcorp.com.au>

On Fri, 09 Mar 2012 14:56:52 +1030, Rusty Russell <rusty at rustcorp.com.au> wrote:
> 
> From: Rusty Russell <rusty at rustcorp.com.au>

Oops, premature script misfire.

These were meant to go to Christoffer, and the android-virt list.

Will resend...

Cheers,
Rusty.
-- 
  How could I marry someone with more hair than me?  http://baldalex.org


From bppdimd at dlzhept.com  Sat Mar 10 08:28:22 2012
From: bppdimd at dlzhept.com (ncocbax)
Date: Sat, 10 Mar 2012 21:28:22 +0800
Subject: =?utf-8?B?77yIM+aciDE15pel5rex5Zyz5Lya6K6u77yJ56eR5oqA6aG555uu5LiT6aG56LWE6YeR55Sz?=
 =?utf-8?B?5oql5pqo5LyB5Lia55+l6K+G5Lqn5p2D566h55CG5oiY55Wl5Y+K5LiT5Yip6L+Q55So?=
Message-ID: <DDA18F4C4578D775AC7ECA7C653613B2@fpwd>







21:28:31
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From tglx at linutronix.de  Sat Mar 10 05:51:36 2012
From: tglx at linutronix.de (Thomas Gleixner)
Date: Sat, 10 Mar 2012 11:51:36 +0100 (CET)
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <1331366064-1273-3-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
Message-ID: <alpine.LFD.2.02.1203101128100.2742@ionos>

On Fri, 9 Mar 2012, Mike Turquette wrote:
> +inline unsigned long __clk_get_enable_count(struct clk *clk)
> +{
> +	return !clk ? -EINVAL : clk->enable_count;

Returning negative error codes in a function with a return value
unsigned long is a bit strange at least. Shouldn't that be long ?

> +#ifndef __LINUX_CLK_PRIVATE_H
> +#define __LINUX_CLK_PRIVATE_H
> +
> +#include <linux/clk-provider.h>
> +#include <linux/list.h>
> +
> +/*
> + * WARNING: Do not include clk-private.h from any file that implements struct
> + * clk_ops.  Doing so is a layering violation!
> + *
> + * This header exists only to allow for statically initialized clock data.  Any
> + * static clock data must be defined in a separate file from the logic that
> + * implements the clock operations for that same data.

Now the question is whether you should provide a data structure which
is explicitely used for static initialization and instead of having
struct clk static you register the static initializer structure, which
would be initdata. I don't think that anything needs clocks before the
memory allocators are up and running. The clocks which are necessary
to get that far have to be enabled in the boot loader anyway.

The static initialization question should not hold off this set from
being merged, though settling it before growing users would be nice.

Otherwise this is a very well done infrastructure implementation!
Thanks a lot Mike!

Reviewed-by: Thomas Gleixner <tglx at linutronix.de>


From sdharia at codeaurora.org  Fri Mar  9 14:50:24 2012
From: sdharia at codeaurora.org (Sagar Dharia)
Date: Fri, 09 Mar 2012 12:50:24 -0700
Subject: [RFC PATCH] slimbus message encoding/decoding
In-Reply-To: <20120309002106.GA605@plastictigers.com>
References: <20120309002106.GA605@plastictigers.com>
Message-ID: <4F5A5F00.70508@codeaurora.org>

On 03/08/2012 05:21 PM, Marc Butler wrote:
> All,
>
> This patch provides generic functions for encoding/decoding SLIMbus
> messages (Section 8 of the specification).

Thanks for providing this patch. My understanding is that this patch 
provides helper functions for h/w controllers which rely on s/w to 
provide the exact message to be sent out on the bus.

> No CRC generator is included for the PI and MI fields. The OMAP4430
> chip this is being tested on generates and populates these fields in
> h/w. However, I have include a general (and untested) callback
> mechanism.

Just like CRC, some other fields may be populated by HW. e.g. Qualcomm 
chip also populates Arbitration priority, Arbitration Extension fields. 
So it expects SW to only program a few fields, a.k.a logical/elemental 
address, MT,MC, DT etc.(that too, SW programs this based on software 
interface manual). The hardware will convert this information to actual 
slimbus-compliant message and send it on the bus.

Being said that, I am not aware of how majority of h/w controllers work 
and will be open to have this patch if other hardwares rely on s/w to 
provide the exact message as well.

-Sagar
> -m

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From mturquette at linaro.org  Sat Mar 10 02:54:21 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Fri,  9 Mar 2012 23:54:21 -0800
Subject: [PATCH v6 0/3] common clk framework
Message-ID: <1331366064-1273-1-git-send-email-mturquette@linaro.org>

The common clock framework defines a common struct clk as well as an
implementation of the clk api that unifies clock operations on various
platforms and devices.

The net result is consolidation of many different struct clk definitions
and platform-specific clock framework implementations.

Thanks to Sascha Hauer and Andrew Lunn for their great review and
feedback on the previous v5 series.

Major changes since v5:
 * removed redundant HAVE_CLK_PREPARE in Kconfig
 * new CONFIG_COMMON_CLK_DISABLE_UNUSED feature
  * results in a new clk_op callback, .is_enabled
 * standardized the hw-specific locking in the basic clock types
 * export the individual ops for each basic clock type
 * improve registration for single-parent basic clocks (thanks Sascha)
 * fixed bugs in gate clock's static initializers (thanks Andrew)
 * overall improvements to Documentation/clk.txt
 * rebased onto Linus' v3.3-rc6 tag

Major changes since v4:
 * rolled in TGLX's comments on overall design.  We now have,
   * proper handling of root clocks and orphan clocks
   * multi-parent clocks are handled in the core
   * struct clk is shielded from struct clk_foo and vice versa
     * this is a return to the previous struct clk_hw design
 * split basic clock types out into separate files
 * split headers up by purpose
   * clk.h remains the driver-level interface
     * declarations for rate change notifiers are the only additions
   * clk-provider.h is primary header for implementing clock operations
   * clk-private.h allows for static initialization of clock data
 * validation and bug fixes
 * rebased onto Linus' v3.3-rc5 tag

Patches can be pulled from:
git://git.linaro.org/people/mturquette/linux.git v3.3-rc6-clkv6

v5 can be found at,
http://article.gmane.org/gmane.linux.kernel/1261472

v4 can be found at,
http://article.gmane.org/gmane.linux.linaro.devel/8896/

v3 can be found at,
http://article.gmane.org/gmane.linux.kernel/1218622

Mike Turquette (3):
  Documentation: common clk API
  clk: introduce the common clock framework
  clk: basic clock hardware types

 Documentation/clk.txt        |  233 +++++++
 drivers/clk/Kconfig          |   39 ++
 drivers/clk/Makefile         |    2 +
 drivers/clk/clk-divider.c    |  204 ++++++
 drivers/clk/clk-fixed-rate.c |   82 +++
 drivers/clk/clk-gate.c       |  157 +++++
 drivers/clk/clk-mux.c        |  123 ++++
 drivers/clk/clk.c            | 1424 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-private.h  |  192 ++++++
 include/linux/clk-provider.h |  298 +++++++++
 include/linux/clk.h          |   68 ++-
 11 files changed, 2817 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/clk.txt
 create mode 100644 drivers/clk/clk-divider.c
 create mode 100644 drivers/clk/clk-fixed-rate.c
 create mode 100644 drivers/clk/clk-gate.c
 create mode 100644 drivers/clk/clk-mux.c
 create mode 100644 drivers/clk/clk.c
 create mode 100644 include/linux/clk-private.h
 create mode 100644 include/linux/clk-provider.h

-- 
1.7.5.4



From mgherzan at gmail.com  Sun Mar 11 16:05:14 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Sun, 11 Mar 2012 21:05:14 +0100
Subject: [PATCH v2] ARM: OMAP: WiLink platform data for the PandaBoard
In-Reply-To: <20120309183150.GH12083@atomide.com>
References: <1331074504-22683-1-git-send-email-mgherzan@gmail.com>
 <20120309183150.GH12083@atomide.com>
Message-ID: <4F5D057A.3080601@gmail.com>

Am 09.03.2012 19:31, schrieb Tony Lindgren:
> Hi Luca,
> 
> * Mircea Gherzan <mgherzan at gmail.com> [120306 14:23]:
>> The "uim" deamon requires sysfs entries that are filled in using
>> this platform data.
>>
>> Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
>> ---
>>  arch/arm/mach-omap2/board-omap4panda.c |   14 ++++++++++++--
>>  include/linux/ti_wilink_st.h           |    2 ++
>>  2 files changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
>> index b1d74d6..339e781 100644
>> --- a/arch/arm/mach-omap2/board-omap4panda.c
>> +++ b/arch/arm/mach-omap2/board-omap4panda.c
>> @@ -27,6 +27,7 @@
>>  #include <linux/i2c/twl.h>
>>  #include <linux/regulator/machine.h>
>>  #include <linux/regulator/fixed.h>
>> +#include <linux/ti_wilink_st.h>
>>  #include <linux/wl12xx.h>
>>  
>>  #include <mach/hardware.h>
>> @@ -56,12 +57,21 @@
>>  #define HDMI_GPIO_HPD  63 /* Hotplug detect */
>>  
>>  /* wl127x BT, FM, GPS connectivity chip */
>> -static int wl1271_gpios[] = {46, -1, -1};
>> +static struct ti_st_plat_data wilink_platform_data = {
>> +	.nshutdown_gpio	= 46,
>> +	.dev_name	= "/dev/ttyO1",
>> +	.flow_cntrl	= 1,
>> +	.baud_rate	= 3000000,
>> +	.chip_enable	= NULL,
>> +	.suspend	= NULL,
>> +	.resume		= NULL,
>> +};
>> +
>>  static struct platform_device wl1271_device = {
>>  	.name	= "kim",
>>  	.id	= -1,
>>  	.dev	= {
>> -		.platform_data	= &wl1271_gpios,
>> +		.platform_data	= &wilink_platform_data,
>>  	},
>>  };
>>  
>> diff --git a/include/linux/ti_wilink_st.h b/include/linux/ti_wilink_st.h
>> index 2ef4385..3ca0269 100644
>> --- a/include/linux/ti_wilink_st.h
>> +++ b/include/linux/ti_wilink_st.h
>> @@ -25,6 +25,8 @@
>>  #ifndef TI_WILINK_ST_H
>>  #define TI_WILINK_ST_H
>>  
>> +#include <linux/skbuff.h>
>> +
>>  /**
>>   * enum proto-type - The protocol on WiLink chips which share a
>>   *	common physical interface like UART.
>> -- 
> 
> Just checking.. Can you please take a look at this patch
> and confirm that this is how things are supposed to be done?
> 
> To me passing some third driver's dev_name in pdata seems
> pretty weird.. But then again maybe I just don't know how
> this is supposed to work.

This is what the ti_st driver expects in the platform data structure.
More precisely, in kim_probe():

	/* copying platform data */
	strncpy(kim_gdata->dev_name, pdata->dev_name,UART_DEV_NAME_LEN);
	kim_gdata->flow_cntrl = pdata->flow_cntrl;
	kim_gdata->baud_rate = pdata->baud_rate;
	pr_info("sysfs entries created\n");

So IMHO the patch is a valid fix. However, one more patch [1] is still
required to get BT and WLAN working on the PandaBoard.

Thanks,
Mircea

[1] http://elinux.org/images/8/8d/0001a-omap4-pandaboard-wlan-fix.patch



From heiko at sntech.de  Mon Mar 12 15:00:30 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Mon, 12 Mar 2012 20:00:30 +0100
Subject: [PATCH 1/6] ARM: S3C24XX: Add forgotten clock lookup table to S3C2443
In-Reply-To: <201203121959.32966.heiko@sntech.de>
References: <201203121959.32966.heiko@sntech.de>
Message-ID: <201203122000.31216.heiko@sntech.de>

When the hsmmc clock lookup was changed to be lookup tables based,
it seems the S3C2443 was forgotten.

As subsequent patches will want to add more lookups to it, this
patch adds the base table with the missing hsmmc lookup.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/clock-s3c2443.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index efb3ac3..bce1cd3 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -179,6 +179,10 @@ static struct clk *clks[] __initdata = {
 	&clk_hsmmc,
 };
 
+static struct clk_lookup s3c2443_clk_lookup[] = {
+	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
+};
+
 void __init s3c2443_init_clocks(int xtal)
 {
 	unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
@@ -210,6 +214,7 @@ void __init s3c2443_init_clocks(int xtal)
 
 	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+	clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
 
 	s3c_pwmclk_init();
 }
-- 
1.7.2.3



From heiko at sntech.de  Mon Mar 12 15:03:03 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Mon, 12 Mar 2012 20:03:03 +0100
Subject: [PATCH v2 5/6] ARM: S3C24XX: Add HSSPI setup callback for s3c64xx-spi
 driver
In-Reply-To: <201203121959.32966.heiko@sntech.de>
References: <201203121959.32966.heiko@sntech.de>
Message-ID: <201203122003.03303.heiko@sntech.de>

This lets the s3c64xx-spi driver know the specifics of the controller-
variant and also setups the gpios and the misccr bit.

This setup is valid for all S3C24XX SoCs containing a HSSPI controller
(i.e. S3C2416/2450 and S3C2443)

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
changes since v1: adapt to changes in Makefile

 arch/arm/mach-s3c24xx/Kconfig     |    5 ++++
 arch/arm/mach-s3c24xx/Makefile    |    1 +
 arch/arm/mach-s3c24xx/setup-spi.c |   39 +++++++++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s3c24xx/setup-spi.c

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 0f3a327..38e6b30 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -518,6 +518,11 @@ config S3C2443_DMA
 	help
 	  Internal config node for S3C2443 DMA support
 
+config S3C2443_SETUP_SPI
+	bool
+	help
+	  Common setup code for SPI GPIO configurations
+
 endif	# CPU_S3C2443 || CPU_S3C2416
 
 if CPU_S3C2443
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 3518fe8..d0f3a92 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -91,5 +91,6 @@ obj-$(CONFIG_MACH_OSIRIS_DVS)		+= mach-osiris-dvs.o
 # device setup
 
 obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
+obj-$(CONFIG_S3C2443_SETUP_SPI)		+= setup-spi.o
 obj-$(CONFIG_ARCH_S3C24XX)		+= setup-i2c.o
 obj-$(CONFIG_S3C24XX_SETUP_TS)		+= setup-ts.o
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
new file mode 100644
index 0000000..5712c85
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -0,0 +1,39 @@
+/*
+ * HS-SPI device setup for S3C2443/S3C2416
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+	.fifo_lvl_mask	= 0x7f,
+	.rx_lvl_offset	= 13,
+	.tx_st_done	= 21,
+	.high_speed	= 1,
+};
+
+int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
+{
+	/* enable hsspi bit in misccr */
+	s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
+
+	s3c_gpio_cfgall_range(S3C2410_GPE(11), 3,
+			      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+
+	return 0;
+}
+#endif
-- 
1.7.2.3



From paul.liu at linaro.org  Fri Mar  9 22:13:08 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Sat, 10 Mar 2012 11:13:08 +0800
Subject: [PATCH v12] Regulator: Add Anatop regulator driver
Message-ID: <1331349188-14765-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.

Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
Reviewed-by: Axel Lin <axel.lin at gmail.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Liam Girdwood <lrg at ti.com>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 drivers/regulator/Kconfig            |    8 +
 drivers/regulator/Makefile           |    1 +
 drivers/regulator/anatop-regulator.c |  241 ++++++++++++++++++++++++++++++++++
 3 files changed, 250 insertions(+), 0 deletions(-)
 create mode 100644 drivers/regulator/anatop-regulator.c

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index c733df5..a229de9 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -102,6 +102,14 @@ config REGULATOR_DA9052
 	  This driver supports the voltage regulators of DA9052-BC and
 	  DA9053-AA/Bx PMIC.
 
+config REGULATOR_ANATOP
+	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
+	depends on MFD_ANATOP
+	help
+	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
+	  regulators. It is recommended that this option be
+	  enabled on i.MX6 platform.
+
 config REGULATOR_MC13XXX_CORE
 	tristate
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 2b09c81..b5042c8 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
 obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
 obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
 obj-$(CONFIG_REGULATOR_AD5398) += ad5398.o
+obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
 obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o
 obj-$(CONFIG_REGULATOR_DA903X)	+= da903x.o
 obj-$(CONFIG_REGULATOR_DA9052)	+= da9052-regulator.o
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
new file mode 100644
index 0000000..17499a5
--- /dev/null
+++ b/drivers/regulator/anatop-regulator.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+
+struct anatop_regulator {
+	const char *name;
+	u32 control_reg;
+	struct anatop *mfd;
+	int vol_bit_shift;
+	int vol_bit_width;
+	int min_bit_val;
+	int min_voltage;
+	int max_voltage;
+	struct regulator_desc rdesc;
+	struct regulator_init_data *initdata;
+};
+
+static int anatop_set_voltage(struct regulator_dev *reg, int min_uV,
+				  int max_uV, unsigned *selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	u32 val, sel;
+	int uv;
+
+	uv = min_uV;
+	dev_dbg(&reg->dev, "%s: uv %d, min %d, max %d\n", __func__,
+		uv, anatop_reg->min_voltage,
+		anatop_reg->max_voltage);
+
+	if (uv < anatop_reg->min_voltage) {
+		if (max_uV > anatop_reg->min_voltage)
+			uv = anatop_reg->min_voltage;
+		else
+			return -EINVAL;
+	}
+
+	if (!anatop_reg->control_reg)
+		return -ENOTSUPP;
+
+	sel = DIV_ROUND_UP(uv - anatop_reg->min_voltage, 25000);
+	if (sel * 25000 + anatop_reg->min_voltage > anatop_reg->max_voltage)
+		return -EINVAL;
+	val = anatop_reg->min_bit_val + sel;
+	*selector = sel;
+	dev_dbg(&reg->dev, "%s: calculated val %d\n", __func__, val);
+	anatop_set_bits(anatop_reg->mfd,
+			anatop_reg->control_reg,
+			anatop_reg->vol_bit_shift,
+			anatop_reg->vol_bit_width,
+			val);
+
+	return 0;
+}
+
+static int anatop_get_voltage_sel(struct regulator_dev *reg)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	u32 val;
+
+	if (!anatop_reg->control_reg)
+		return -ENOTSUPP;
+
+	val = anatop_get_bits(anatop_reg->mfd,
+			      anatop_reg->control_reg,
+			      anatop_reg->vol_bit_shift,
+			      anatop_reg->vol_bit_width);
+
+	return val - anatop_reg->min_bit_val;
+}
+
+static int anatop_list_voltage(struct regulator_dev *reg, unsigned selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int uv;
+
+	uv = anatop_reg->min_voltage + selector * 25000;
+	dev_dbg(&reg->dev, "vddio = %d, selector = %u\n", uv, selector);
+
+	return uv;
+}
+
+static struct regulator_ops anatop_rops = {
+	.set_voltage     = anatop_set_voltage,
+	.get_voltage_sel = anatop_get_voltage_sel,
+	.list_voltage    = anatop_list_voltage,
+};
+
+static int __devinit anatop_regulator_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct regulator_desc *rdesc;
+	struct regulator_dev *rdev;
+	struct anatop_regulator *sreg;
+	struct regulator_init_data *initdata;
+	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
+	int ret = 0;
+
+	initdata = of_get_regulator_init_data(dev, np);
+	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
+	if (!sreg)
+		return -ENOMEM;
+	sreg->initdata = initdata;
+	sreg->name = kstrdup(of_get_property(np, "regulator-name", NULL),
+			     GFP_KERNEL);
+	rdesc = &sreg->rdesc;
+	memset(rdesc, 0, sizeof(*rdesc));
+	rdesc->name = sreg->name;
+	rdesc->ops = &anatop_rops;
+	rdesc->type = REGULATOR_VOLTAGE;
+	rdesc->owner = THIS_MODULE;
+	sreg->mfd = anatopmfd;
+	ret = of_property_read_u32(np, "reg", &sreg->control_reg);
+	if (ret) {
+		dev_err(dev, "no reg property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-vol-bit-width",
+				   &sreg->vol_bit_width);
+	if (ret) {
+		dev_err(dev, "no anatop-vol-bit-width property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
+				   &sreg->vol_bit_shift);
+	if (ret) {
+		dev_err(dev, "no anatop-vol-bit-shift property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-min-bit-val",
+				   &sreg->min_bit_val);
+	if (ret) {
+		dev_err(dev, "no anatop-min-bit-val property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-min-voltage",
+				   &sreg->min_voltage);
+	if (ret) {
+		dev_err(dev, "no anatop-min-voltage property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-max-voltage",
+				   &sreg->max_voltage);
+	if (ret) {
+		dev_err(dev, "no anatop-max-voltage property set\n");
+		goto anatop_probe_end;
+	}
+
+	rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage)
+		/ 25000 + 1;
+
+	/* register regulator */
+	rdev = regulator_register(rdesc, dev,
+				  initdata, sreg, pdev->dev.of_node);
+	if (IS_ERR(rdev)) {
+		dev_err(dev, "failed to register %s\n",
+			rdesc->name);
+		ret = PTR_ERR(rdev);
+		goto anatop_probe_end;
+	}
+
+	platform_set_drvdata(pdev, rdev);
+
+anatop_probe_end:
+	if (ret)
+		kfree(sreg->name);
+
+	return ret;
+}
+
+static int __devexit anatop_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
+	const char *name = sreg->name;
+
+	regulator_unregister(rdev);
+	kfree(name);
+
+	return 0;
+}
+
+static struct of_device_id __devinitdata of_anatop_regulator_match_tbl[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ /* end */ }
+};
+
+static struct platform_driver anatop_regulator = {
+	.driver = {
+		.name	= "anatop_regulator",
+		.owner  = THIS_MODULE,
+		.of_match_table = of_anatop_regulator_match_tbl,
+	},
+	.probe	= anatop_regulator_probe,
+	.remove	= anatop_regulator_remove,
+};
+
+static int __init anatop_regulator_init(void)
+{
+	return platform_driver_register(&anatop_regulator);
+}
+postcore_initcall(anatop_regulator_init);
+
+static void __exit anatop_regulator_exit(void)
+{
+	platform_driver_unregister(&anatop_regulator);
+}
+module_exit(anatop_regulator_exit);
+
+MODULE_AUTHOR("Nancy Chen <Nancy.Chen at freescale.com>, "
+	      "Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP Regulator driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.1



From lauraa at codeaurora.org  Mon Mar 12 13:40:27 2012
From: lauraa at codeaurora.org (Laura Abbott)
Date: Mon, 12 Mar 2012 10:40:27 -0700
Subject: [PATCH] arm: Add unwinding support for memset and memzero.
Message-ID: <1331574027-28542-1-git-send-email-lauraa@codeaurora.org>

Both memset and memzero lack unwinding annoations. If
an abort occurs trying to access the pointer, the backtrace
is incomplete. Add unwinding annotations to both functions
so we can actually get a useful backtrace.

Signed-off-by: Laura Abbott <lauraa at codeaurora.org>
---
 arch/arm/lib/memset.S  |    7 +++++--
 arch/arm/lib/memzero.S |    7 +++++--
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
index 650d592..4379912 100644
--- a/arch/arm/lib/memset.S
+++ b/arch/arm/lib/memset.S
@@ -11,6 +11,7 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <asm/unwind.h>
 
 	.text
 	.align	5
@@ -29,6 +30,7 @@
  */
 
 ENTRY(memset)
+UNWIND(.fnstart)
 	ands	r3, r0, #3		@ 1 unaligned?
 	bne	1b			@ 1
 /*
@@ -41,7 +43,7 @@ ENTRY(memset)
 	blt	4f
 
 #if ! CALGN(1)+0
-
+UNWIND(.save {lr})
 /*
  * We need an extra register for this loop - save the return address and
  * use the LR
@@ -68,7 +70,7 @@ ENTRY(memset)
 	ldr	lr, [sp], #4
 
 #else
-
+UNWIND(.save {r4, r5, r6, r7, lr})
 /*
  * This version aligns the destination pointer in order to write
  * whole cache lines at once.
@@ -124,4 +126,5 @@ ENTRY(memset)
 	tst	r2, #1
 	strneb	r1, [r0], #1
 	mov	pc, lr
+UNWIND(.fnend)
 ENDPROC(memset)
diff --git a/arch/arm/lib/memzero.S b/arch/arm/lib/memzero.S
index 3fbdef5..26f9ce8 100644
--- a/arch/arm/lib/memzero.S
+++ b/arch/arm/lib/memzero.S
@@ -9,6 +9,7 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <asm/unwind.h>
 
 	.text
 	.align	5
@@ -31,6 +32,7 @@
  */
 
 ENTRY(__memzero)
+UNWIND(.fnstart)
 	mov	r2, #0			@ 1
 	ands	r3, r0, #3		@ 1 unaligned?
 	bne	1b			@ 1
@@ -41,7 +43,7 @@ ENTRY(__memzero)
 	blt	4f			@ 1 have < 16 bytes
 
 #if ! CALGN(1)+0
-
+UNWIND(.save {lr})
 /*
  * We need an extra register for this loop - save the return address and
  * use the LR
@@ -68,7 +70,7 @@ ENTRY(__memzero)
 	ldr	lr, [sp], #4		@ 1
 
 #else
-
+UNWIND(.save{r4, r5, r6, r7})
 /*
  * This version aligns the destination pointer in order to write
  * whole cache lines at once.
@@ -122,4 +124,5 @@ ENTRY(__memzero)
 	tst	r1, #1			@ 1 a byte left over
 	strneb	r2, [r0], #1		@ 1
 	mov	pc, lr			@ 1
+UNWIND(.fnend)
 ENDPROC(__memzero)
-- 
1.7.8.3



From jm at lentin.co.uk  Mon Mar 12 13:59:50 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Mon, 12 Mar 2012 17:59:50 -0000
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <20120312030232.GX5050@titan.lakedaemon.net>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <1331476406-9844-2-git-send-email-jm@lentin.co.uk>
 <20120312030232.GX5050@titan.lakedaemon.net>
Message-ID: <op.wa2j90zu4cuzmg@gonzo.lentin.co.uk>

On Mon, 12 Mar 2012 03:02:32 -0000, Jason Cooper <jason at lakedaemon.net>  
wrote:

> On Sun, Mar 11, 2012 at 02:33:25PM +0000, Jamie Lentin wrote:
>> Add support for the DNS-320 and DNS-325. Describe as much as currently  
>> possible
>> in the devicetree files, leave everything else in board-dt.c to be  
>> patched
>> later.
>>
>> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
>
> Great work!  comments, below.
>> ---
>>  arch/arm/boot/dts/kirkwood-dns320.dts |   54 ++++++
>>  arch/arm/boot/dts/kirkwood-dns325.dts |   40 +++++
>>  arch/arm/mach-kirkwood/Kconfig        |   18 ++
>>  arch/arm/mach-kirkwood/Makefile.boot  |    2 +
>>  arch/arm/mach-kirkwood/board-dt.c     |  294  
>> +++++++++++++++++++++++++++++++++
>>  5 files changed, 408 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/boot/dts/kirkwood-dns320.dts
>>  create mode 100644 arch/arm/boot/dts/kirkwood-dns325.dts
>>
>> diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts  
>> b/arch/arm/boot/dts/kirkwood-dns320.dts
>> new file mode 100644
>> index 0000000..c039041
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/kirkwood-dns320.dts
>> @@ -0,0 +1,54 @@
>> +/dts-v1/;
>> +
>> +/include/ "kirkwood.dtsi"
>> +
>> +/ {
>> +	model = "D-Link DNS-320 NAS (Rev A1)";
>> +	compatible = "dlink,dns-320-a1", "dlink,dns-320",  
>> "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
>
> s/marvell/mrvl/g for compatible properties.
>

Okay.

>> +	memory {
>> +		device_type = "memory";
>> +		reg = <0x00000000 0x8000000>;
>> +	};
>> +
>> +	chosen {
>> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
>> +	};
>> +
>> +	wdt at fed20300 {
>> +		compatible = "mrvl,orion-wdt";
>> +		reg = <0xfed20300 0x28>;
>> +		clock-frequency = <166666667>;
>> +	};
>
> This hasn't made it into my stable branch yet, waiting on common clock
> to land (may be 3.5).  Please use kirkwood_wdt_init() in the mean time.
>

So just to be clear kirkwood_dt_stable on git.infradead.org, as opposed to  
any branches on arm-soc?

>> +	serial at f1012000 {
>> +		compatible = "ns16550a";
>> +		reg = <0xf1012000 0xff>;
>> +		reg-shift = <2>;
>> +		interrupts = <33>;
>> +		clock-frequency = <166666667>;
>> +	};
>> +
>> +	serial at f1012100 {
>> +		compatible = "ns16550a";
>> +		reg = <0xf1012100 0xff>;
>> +		reg-shift = <2>;
>> +		interrupts = <34>;
>> +		clock-frequency = <166666667>;
>> +	};
>> +
>> +	sata at f1080000 {
>> +		compatible = "mrvl,orion-sata";
>> +		reg = <0xf1080000 0x5000>;
>> +		interrupts = <21>;
>> +		nr-ports = <2>;
>> +	};
>> +
>> +	ehci at f1050000 {
>> +		compatible = "mrvl,orion-ehci";
>> +		reg = <0xf1050000 0x1000>;
>> +		interrupts = <19>;
>> +		dma-mask = <0xffffffff>;
>> +		phy-version = "";
>> +	};
>
> sata and ehci both require working dma and interrupt controller.  I
> should have the interrupt controller done soon.  mv_cesa will then work.
> dma will be after that.

I found this out the hard way, but saw that dma-mask was supported in  
staging/kirkwood/dt on arm-soc and managed to get working USB using it.  
I'll switch back for now.

> Basically, anything in mach-kirkwood/common.c that passes kirkwood_tclk
> is on hold for devicetree.

Including serial ports?

>> +};
>> diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts  
>> b/arch/arm/boot/dts/kirkwood-dns325.dts
>> new file mode 100644
>> index 0000000..a7c2c26
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/kirkwood-dns325.dts
>> @@ -0,0 +1,40 @@
>> +/dts-v1/;
>> +
>> +/include/ "kirkwood.dtsi"
>> +
>> +/ {
>> +	model = "D-Link DNS-325 NAS (Rev A1)";
>> +	compatible = "dlink,dns-325-a1", "dlink,dns-325",  
>> "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
>
> same as above, mrvl.
>
>> +
>> +	memory {
>> +		device_type = "memory";
>> +		reg = <0x00000000 0x10000000>;
>> +	};
>> +
>> +	chosen {
>> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
>> +	};
>
> make sure to test serial with earlyprintk disabled.  That bit me once.
>

Thanks. I didn't think to try that!

>> +
>> +	serial at f1012000 {
>> +		compatible = "ns16550a";
>> +		reg = <0xf1012000 0xff>;
>> +		reg-shift = <2>;
>> +		interrupts = <33>;
>> +		clock-frequency = <200000000>;
>> +	};
>> +
>> +	sata at f1080000 {
>> +		compatible = "mrvl,orion-sata";
>> +		reg = <0xf1080000 0x5000>;
>> +		interrupts = <21>;
>> +		nr-ports = <2>;
>> +	};
>> +
>> +	ehci at f1050000 {
>> +		compatible = "mrvl,orion-ehci";
>> +		reg = <0xf1050000 0x1000>;
>> +		interrupts = <19>;
>> +		dma-mask = <0xffffffff>;
>> +		phy-version = "";
>> +	};
>> +};
>> diff --git a/arch/arm/mach-kirkwood/Kconfig  
>> b/arch/arm/mach-kirkwood/Kconfig
>> index 90ceab7..6c76e18 100644
>> --- a/arch/arm/mach-kirkwood/Kconfig
>> +++ b/arch/arm/mach-kirkwood/Kconfig
>> @@ -58,6 +58,24 @@ config MACH_DREAMPLUG_DT
>>  	  Say 'Y' here if you want your kernel to support the
>>  	  Marvell DreamPlug (Flattened Device Tree).
>>
>> +config MACH_DNS320_DT
>> +	bool "D-Link DNS-320 (Flattened Device Tree)"
>> +	select ARCH_KIRKWOOD_DT
>> +	select CONFIG_MTD_OF_PARTS
>> +	select CONFIG_SERIAL_OF_PLATFORM
>> +	help
>> +	  Say 'Y' here if you want your kernel to support the
>> +	  D-Link DNS-320 (Flattened Device Tree).
>> +
>> +config MACH_DNS325_DT
>> +	bool "D-Link DNS-325 (Flattened Device Tree)"
>> +	select ARCH_KIRKWOOD_DT
>> +	select CONFIG_MTD_OF_PARTS
>> +	select CONFIG_SERIAL_OF_PLATFORM
>> +	help
>> +	  Say 'Y' here if you want your kernel to support the
>> +	  D-Link DNS-325 (Flattened Device Tree).
>> +
>>  config MACH_TS219
>>  	bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and  
>> TS-219P+ Turbo NAS"
>>  	help
>> diff --git a/arch/arm/mach-kirkwood/Makefile.boot  
>> b/arch/arm/mach-kirkwood/Makefile.boot
>> index 16f9385..9c5e45f 100644
>> --- a/arch/arm/mach-kirkwood/Makefile.boot
>> +++ b/arch/arm/mach-kirkwood/Makefile.boot
>> @@ -3,3 +3,5 @@ params_phys-y	:= 0x00000100
>>  initrd_phys-y	:= 0x00800000
>>
>>  dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
>> +dtb-$(CONFIG_MACH_DNS320_DT) += kirkwood-dns320.dtb
>> +dtb-$(CONFIG_MACH_DNS325_DT) += kirkwood-dns325.dtb
>> diff --git a/arch/arm/mach-kirkwood/board-dt.c  
>> b/arch/arm/mach-kirkwood/board-dt.c
>> index 12dec38..0885713 100644
>> --- a/arch/arm/mach-kirkwood/board-dt.c
>> +++ b/arch/arm/mach-kirkwood/board-dt.c
>> @@ -15,6 +15,7 @@
>>  #include <linux/platform_device.h>
>>  #include <linux/irqdomain.h>
>>  #include <linux/mtd/partitions.h>
>> +#include <linux/i2c.h>
>>  #include <linux/ata_platform.h>
>>  #include <linux/mv643xx_eth.h>
>>  #include <linux/of.h>
>> @@ -23,6 +24,9 @@
>>  #include <linux/of_irq.h>
>>  #include <linux/of_platform.h>
>>  #include <linux/gpio.h>
>> +#include <linux/input.h>
>> +#include <linux/gpio_keys.h>
>> +#include <linux/gpio-fan.h>
>>  #include <linux/leds.h>
>>  #include <linux/mtd/physmap.h>
>>  #include <linux/spi/flash.h>
>> @@ -150,6 +154,291 @@ static void __init dreamplug_init(void)
>>  	platform_device_register(&dreamplug_leds);
>>  }
>>
>> +/*****************************************************************************
>> + * DNS-320 & DNS-325 specifics
>> +  
>> ****************************************************************************/
>> +
>> +static struct mtd_partition dnskw_nand_parts[] = {
>> +	{
>> +		.name		= "u-boot",
>> +		.offset		= 0,
>> +		.size		= SZ_1M,
>> +		.mask_flags	= MTD_WRITEABLE
>> +	}, {
>> +		.name		= "uImage",
>> +		.offset		= MTDPART_OFS_NXTBLK,
>> +		.size		= 5 * SZ_1M
>> +	}, {
>> +		.name		= "ramdisk",
>> +		.offset		= MTDPART_OFS_NXTBLK,
>> +		.size		= 5 * SZ_1M
>> +	}, {
>> +		.name		= "image",
>> +		.offset		= MTDPART_OFS_NXTBLK,
>> +		.size		= 102 * SZ_1M
>> +	}, {
>> +		.name		= "mini firmware",
>> +		.offset		= MTDPART_OFS_NXTBLK,
>> +		.size		= 10 * SZ_1M
>> +	}, {
>> +		.name		= "config",
>> +		.offset		= MTDPART_OFS_NXTBLK,
>> +		.size		= 5 * SZ_1M
>> +	},
>> +};
>
> You should probably squeeze in a partition for the dtb.  ;-)
>
> Is the config partition the u-boot environment?  That usually is much
> smaller than what you have alotted.  So, you might be able to split that
> to make room for the dtb.
>

The partition scheme is the same as D-Link's kernel. The config area is a  
jffs2 filesystem that contains their config files. It seemed to me that  
copying the partition table was the right thing to do to allow the NAND to  
be read, even though in practice it's not that useful---I'm not sure even  
D-Link pay much attention to it, there's all sorts of odd offsets in their  
code.

The other option would be to ignore the nonsense and replace it with  
something useful. This would be more convenient for me because it'd mean I  
don't have to replace it with my partition scheme :). Any opinions?

>> +
>> +static struct mv643xx_eth_platform_data dnskw_ge00_data = {
>> +	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
>> +};
>> +
>> +static unsigned int dnskw_mpp_config[] __initdata = {
>> +	MPP13_UART1_TXD,	/* Custom ... */
>> +	MPP14_UART1_RXD,	/* ... Controller (DNS-320 only) */
>> +	MPP20_SATA1_ACTn,	/* LED: White Right HDD */
>> +	MPP21_SATA0_ACTn,	/* LED: White Left HDD */
>> +	MPP24_GPIO,
>> +	MPP25_GPIO,
>> +	MPP26_GPIO,	/* LED: Power */
>> +	MPP27_GPIO,	/* LED: Red Right HDD */
>> +	MPP28_GPIO,	/* LED: Red Left HDD */
>> +	MPP29_GPIO,	/* LED: Red USB (DNS-325 only) */
>> +	MPP30_GPIO,
>> +	MPP31_GPIO,
>> +	MPP32_GPIO,
>> +	MPP33_GPO,
>> +	MPP34_GPIO,	/* Button: Front power */
>> +	MPP35_GPIO,	/* LED: Red USB (DNS-320 only) */
>> +	MPP36_GPIO,	/* Power: MV88F6281_DEV_ID Board */
>> +	MPP37_GPIO,	/* Power: Boot when power applied */
>> +	MPP38_GPIO,
>> +	MPP39_GPIO,	/* Power: SATA0 */
>> +	MPP40_GPIO,	/* Power: SATA1 */
>> +	MPP41_GPIO,
>> +	MPP42_GPIO,
>> +	MPP43_GPIO,	/* LED: White USB */
>> +	MPP44_GPIO,	/* Fan: Tachometer Pin */
>> +	MPP45_GPIO,	/* Fan: high speed */
>> +	MPP46_GPIO,	/* Fan: low speed */
>> +	MPP47_GPIO,	/* Button: Back unmount */
>> +	MPP48_GPIO,	/* Button: Back reset */
>> +	MPP49_GPIO,	/* Pin of unused U5 (DNS-320 only) */
>> +	0
>> +};
>> +
>> +static struct gpio_led dns325_led_pins[] = {
>> +	{
>> +		.name	= "dns325:white:power",
>> +		.gpio	= 26,
>> +		.active_low = 1,
>> +		.default_trigger = "default-on",
>> +	},
>> +	{
>> +		.name	= "dns325:white:usb",
>> +		.gpio	= 43,
>> +		.active_low = 1,
>> +	},
>> +	{
>> +		.name	= "dns325:red:l_hdd",
>> +		.gpio	= 28,
>> +		.active_low = 1,
>> +	},
>> +	{
>> +		.name	= "dns325:red:r_hdd",
>> +		.gpio	= 27,
>> +		.active_low = 1,
>> +	},
>> +	{
>> +		.name	= "dns325:red:usb",
>> +		.gpio	= 29,
>> +		.active_low = 1,
>> +	},
>> +};
>> +
>> +static struct gpio_led_platform_data dns325_led_data = {
>> +	.num_leds	= ARRAY_SIZE(dns325_led_pins),
>> +	.leds		= dns325_led_pins,
>> +};
>> +
>> +static struct platform_device dns325_led_device = {
>> +	.name		= "leds-gpio",
>> +	.id		= -1,
>> +	.dev		= {
>> +		.platform_data	= &dns325_led_data,
>> +	},
>> +};
>> +
>> +static struct gpio_led dns320_led_pins[] = {
>> +	{
>> +		.name	= "dns320:blue:power",
>> +		.gpio	= 26,
>> +		.active_low = 1,
>> +		.default_trigger = "default-on",
>> +	},
>> +	{
>> +		.name	= "dns320:blue:usb",
>> +		.gpio	= 43,
>> +		.active_low = 1,
>> +	},
>> +	{
>> +		.name	= "dns320:orange:l_hdd",
>> +		.gpio	= 28,
>> +		.active_low = 1,
>> +	},
>> +	{
>> +		.name	= "dns320:orange:r_hdd",
>> +		.gpio	= 27,
>> +		.active_low = 1,
>> +	},
>> +	{
>> +		.name	= "dns320:orange:usb",
>> +		.gpio	= 35,
>> +		.active_low = 1,
>> +	},
>> +};
>> +
>> +static struct gpio_led_platform_data dns320_led_data = {
>> +	.num_leds	= ARRAY_SIZE(dns320_led_pins),
>> +	.leds		= dns320_led_pins,
>> +};
>> +
>> +static struct platform_device dns320_led_device = {
>> +	.name		= "leds-gpio",
>> +	.id		= -1,
>> +	.dev		= {
>> +		.platform_data	= &dns320_led_data,
>> +	},
>> +};
>> +
>> +static struct i2c_board_info dns325_i2c_board_info[] __initdata = {
>> +	{
>> +		I2C_BOARD_INFO("lm75", 0x48),
>> +	},
>> +	/* Something at 0x0c also */
>> +};
>> +
>> +static struct gpio_keys_button dnskw_button_pins[] = {
>> +	{
>> +		.code		= KEY_POWER,
>> +		.gpio		= 34,
>> +		.desc		= "Power button",
>> +		.active_low	= 1,
>> +	},
>> +	{
>> +		.code		= KEY_EJECTCD,
>> +		.gpio		= 47,
>> +		.desc		= "USB unmount button",
>> +		.active_low	= 1,
>> +	},
>> +	{
>> +		.code		= KEY_RESTART,
>> +		.gpio		= 48,
>> +		.desc		= "Reset button",
>> +		.active_low	= 1,
>> +	},
>> +};
>> +
>> +static struct gpio_keys_platform_data dnskw_button_data = {
>> +	.buttons	= dnskw_button_pins,
>> +	.nbuttons	= ARRAY_SIZE(dnskw_button_pins),
>> +};
>> +
>> +static struct platform_device dnskw_button_device = {
>> +	.name		= "gpio-keys",
>> +	.id		= -1,
>> +	.num_resources	= 0,
>> +	.dev		= {
>> +		.platform_data	= &dnskw_button_data,
>> +	}
>> +};
>> +
>> +/* Fan: ADDA AD045HB-G73 40mm 6000rpm at 5v */
>> +static struct gpio_fan_speed dnskw_fan_speed[] = {
>> +	{    0,  0 },
>> +	{ 3000,	 1 },
>> +	{ 6000,	 2 },
>> +};
>> +static unsigned dnskw_fan_pins[] = {46, 45};
>> +
>> +static struct gpio_fan_platform_data dnskw_fan_data = {
>> +	.num_ctrl	= ARRAY_SIZE(dnskw_fan_pins),
>> +	.ctrl		= dnskw_fan_pins,
>> +	.num_speed	= ARRAY_SIZE(dnskw_fan_speed),
>> +	.speed		= dnskw_fan_speed,
>> +};
>> +
>> +static struct platform_device dnskw_fan_device = {
>> +	.name	= "gpio-fan",
>> +	.id	= -1,
>> +	.dev	= {
>> +		.platform_data	= &dnskw_fan_data,
>> +	},
>> +};
>> +
>> +static void __init dnskw_gpio_register(unsigned gpio, char *name, int  
>> def)
>> +{
>> +	if (gpio_request(gpio, name) == 0 &&
>> +	    gpio_direction_output(gpio, 0) == 0) {
>> +		gpio_set_value(gpio, def);
>> +		if (gpio_export(gpio, 0) != 0)
>> +			pr_err("dnskw: Failed to export GPIO %s\n", name);
>> +	} else
>> +		pr_err("dnskw: Failed to register %s\n", name);
>> +}
>> +
>> +static void dnskw_power_off(void)
>> +{
>> +	gpio_set_value(36, 1);
>> +}
>> +
>> +static void __init dnskw_init(void)
>> +{
>> +	u32 dev, rev;
>> +
>> +	kirkwood_mpp_conf(dnskw_mpp_config);
>> +	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
>> +
>> +	kirkwood_ge00_init(&dnskw_ge00_data);
>> +	kirkwood_i2c_init();
>> +
>> +	platform_device_register(&dnskw_button_device);
>> +	platform_device_register(&dnskw_fan_device);
>> +
>> +	if (of_machine_is_compatible("dlink,dns-325")) {
>> +		i2c_register_board_info(0, dns325_i2c_board_info,
>> +					ARRAY_SIZE(dns325_i2c_board_info));
>> +		platform_device_register(&dns325_led_device);
>> +
>> +	} else if (of_machine_is_compatible("dlink,dns-320")) {
>> +		platform_device_register(&dns320_led_device);
>> +	}
>
> braces not needed.
>
>> +
>> +	/* Register power off routine */
>> +	kirkwood_pcie_id(&dev, &rev);
>> +	if (dev == MV88F6281_DEV_ID) {
>> +		pr_info("PCI-E Device ID: MV88F6281, configuring power-off");
>> +		if (gpio_request(36, "dnskw:power:off") == 0 &&
>> +		    gpio_direction_output(36, 0) == 0)
>> +			pm_power_off = dnskw_power_off;
>> +		else
>> +			pr_err("dnskw: failed to configure power-off GPIO\n");
>> +	} else {
>> +		/*
>> +		 * Dlink code also defines 0x6192, and sets LOW_BASE +
>> +		 * 0x01000000 high. Either cargo-culted code or another model.
>> +		 */
>
> I'm just curious, what is cargo-culted?
>

http://en.wikipedia.org/wiki/Cargo_cult_programming

In this case, I originally thought that the line was relevant to  
supporting the DNS-320 (I assumed it had a MV88F6192 based on it's lower  
TCLK), but it seems it uses the MV88F6281 too. So either D-link have been  
blindly including this logic or there is a model somewhere that uses the  
different SoC.

On reflection, it's probably best to remove this entirely. Testing the  
pcie_id isn't achieving anything and is likely to confuse when it comes to  
porting the power-off to devicetree.

>> +		pr_err("Unknown PCI-E Device ID %x, no power-off", dev);
>> +	}
>> +
>> +	/*
>> +	 * Supply power to HDDs. Bootloader should have turned on sata0  
>> already
>> +	 */
>
> Don't assume the bootloader does or doesn't do anything.  Put the
> peripheral into a known state and work from there.
>

It doesn't, it turns both HDDs on. I'll clarify the comment though.

>> +	dnskw_gpio_register(39, "dnskw:power:sata0", 1);
>> +	dnskw_gpio_register(40, "dnskw:power:sata1", 1);
>> +
>> +	/* Set NAS to turn back on after a power failure */
>> +	dnskw_gpio_register(37, "dnskw:power:recover", 1);
>> +}
>> +
>
> I doubt this board is the only one that wants to be added while the
> conversion to devicetree is progressing.  It makes more sense to me to
> break the above out to a separate file, eg board-dnskw.c.  I'll follow
> and break out the dreamplug code to board-dreamplug.c.  Otherwise, I see
> board-dt.c becoming a long mess.
>
> Arnd, sound okay to you?
>
>>  static void __init kirkwood_dt_init(void)
>>  {
>>  	struct device_node *node;
>> @@ -186,11 +475,16 @@ static void __init kirkwood_dt_init(void)
>>  	if (of_machine_is_compatible("globalscale,dreamplug"))
>>  		dreamplug_init();
>>
>> +	if (of_machine_is_compatible("dlink,dns-kirkwood"))
>> +		dnskw_init();
>> +
>>  	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
>>  }
>>
>>  static const char *kirkwood_dt_board_compat[] = {
>>  	"globalscale,dreamplug",
>> +	"dlink,dns-320",
>> +	"dlink,dns-325",
>>  	NULL
>>  };
>>
>> --
>> 1.7.9.1
>>


-- 
Jamie Lentin


From LW at KARO-electronics.de  Fri Mar  9 09:44:31 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Fri, 9 Mar 2012 15:44:31 +0100
Subject: [RFC] i.MX: drop secondary clocks
In-Reply-To: <20120309142205.GF3852@pengutronix.de>
References: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
 <20313.52782.832292.580932@ipc1.ka-ro>
 <20120309102931.GY3852@pengutronix.de>
 <20313.60910.420339.905973@ipc1.ka-ro>
 <20120309142205.GF3852@pengutronix.de>
Message-ID: <20314.5967.278184.187691@ipc1.ka-ro>

Hi,

Sascha Hauer writes:
> On Fri, Mar 09, 2012 at 12:47:58PM +0100, Lothar Wa?mann wrote:
> > Hi,
> > 
> > Sascha Hauer writes:
> > > On Fri, Mar 09, 2012 at 10:32:30AM +0100, Lothar Wa?mann wrote:
> > > > Hi,
> > > > 
> > > > Sascha Hauer writes:
> > > > > Hi All,
> > > > > 
> > [...]
> > > > I think that's a bad idea! Drivers should not have to know intimate
> > > > details about the clock logic of the CPU core they are running on!
> > > 
> > > They don't have to. There really are different clocks connected to the
> > > devices. If for example you have a look eSDHC Block diagram in the
> > > reference Manual  you'll see that this has three clock inputs. All
> > > we do is to tell the driver about these three clocks which are device
> > > specific and not SoC specific. Which of these clocks are actually
> > > gatetable varies from SoC to SoC. Also on some SoCs two of the three
> > > clocks may be actually the same.
> > > 
> > At least this should be done in a way that is independent from the
> > name of the clock on a specific SoC, but is related to the function of
> > the clock for the driver. Thus instead of e.g. CLK_IPG and CLK_PER use
> > CLK_REG and CLK_BITRATE.
> 
> 'per', 'ipg' and 'ahb' seems to be a common pattern with all i.MXs. Only
> ahb is sometimes refered to as hclk. Do you also have a name for
> ahb/hclk? I don't insist on specific names, in the end they are just
> names and the pattern I used at least seems mostly consistent.
> 
CLK_BUS?

> I assume that any given device has a set of clocks as inputs which
> should get device specific names. It's the job of the clock tree
> to know which SoC clocks map to which device clocks. If now a newer
> UART block has an additional clock, then we would depending on the
> device id (fsl,imx7-uart) know that it requires the additional clock
> and request it.
> 
It's also not the business of a device driver to know any details
about clock dependencies on a specific SoC.
We probably really need a bus layer that can hide the details of the
bus architecture and their corresponding clocks from the device
drivers.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From grant.likely at secretlab.ca  Fri Mar  9 12:52:10 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 09 Mar 2012 10:52:10 -0700
Subject: [PATCH 6/6] spi/s3c64xx: Allow usage for ARCH_S3C24XX
In-Reply-To: <201203041909.10400.heiko@sntech.de>
References: <201203041902.38318.heiko@sntech.de>
 <201203041909.10400.heiko@sntech.de>
Message-ID: <20120309175210.21B2C3E0880@localhost>

On Sun, 4 Mar 2012 19:09:10 +0100, Heiko St??bner <heiko at sntech.de> wrote:
> Newer SoCs from the S3C24XX line, namely S3C2416/2443/2450 contain
> hsspi-controllers compatible with the s3c64xx type.
> 
> The previous patches enabled platform support for it, so make the
> driver also usable for the S3C24xx architecture.
> 
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>

Acked-by: Grant Likely <grant.likely at secretlab.ca>

> ---
> As it is part of a series this probably needs an ack from Grant Likely
> and should be merged via the samsung tree.
> 
>  drivers/spi/Kconfig |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index ac92194..e411364 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -299,7 +299,7 @@ config SPI_S3C24XX_FIQ
>  
>  config SPI_S3C64XX
>  	tristate "Samsung S3C64XX series type SPI"
> -	depends on (ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
> +	depends on (ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || ARCH_EXYNOS)
>  	select S3C64XX_DMA if ARCH_S3C64XX
>  	help
>  	  SPI driver for Samsung S3C64XX and newer SoCs.
> -- 
> 1.7.2.3
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From rnayak at ti.com  Mon Mar 12 11:02:37 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 12 Mar 2012 20:32:37 +0530
Subject: [PATCH v2 1/4] mmc: omap_hsmmc: Convert hsmmc driver to use device
 tree
In-Reply-To: <1331564560-23276-1-git-send-email-rnayak@ti.com>
References: <1331564560-23276-1-git-send-email-rnayak@ti.com>
Message-ID: <1331564560-23276-2-git-send-email-rnayak@ti.com>

Define dt bindings for the ti-omap-hsmmc, and adapt
the driver to extract data (which was earlier passed as
platform_data) from device tree.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Acked-by: Rob Herring <rob.herring at calxeda.com>
---
 .../devicetree/bindings/mmc/ti-omap-hsmmc.txt      |   33 +++++++++
 drivers/mmc/host/omap_hsmmc.c                      |   73 ++++++++++++++++++++
 2 files changed, 106 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt

diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
new file mode 100644
index 0000000..dbd4368
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -0,0 +1,33 @@
+* TI Highspeed MMC host controller for OMAP
+
+The Highspeed MMC Host Controller on TI OMAP family
+provides an interface for MMC, SD, and SDIO types of memory cards.
+
+Required properties:
+- compatible:
+ Should be "ti,omap2-hsmmc", for OMAP2 controllers
+ Should be "ti,omap3-hsmmc", for OMAP3 controllers
+ Should be "ti,omap4-hsmmc", for OMAP4 controllers
+- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
+- reg : should contain hsmmc registers location and length
+
+Optional properties:
+ti,dual-volt: boolean, supports dual voltage cards
+<supply-name>-supply: phandle to the regulator device tree node
+"supply-name" examples are "vmmc", "vmmc_aux" etc
+ti,bus-width: Number of data lines, default assumed is 1 if the property is missing.
+cd-gpios: GPIOs for card detection
+wp-gpios: GPIOs for write protection
+ti,non-removable: non-removable slot (like eMMC)
+ti,needs-special-reset: Requires a special softreset sequence
+
+Example:
+	mmc1: mmc at 0x4809c000 {
+		compatible = "ti,omap4-hsmmc";
+		reg = <0x4809c000 0x400>;
+		ti,hwmods = "mmc1";
+		ti,dual-volt;
+		ti,bus-width = <4>;
+		vmmc-supply = <&vmmc>; /* phandle to regulator node */
+		ti,non-removable;
+	};
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 82583bf..38ae8c0 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -26,6 +26,9 @@
 #include <linux/platform_device.h>
 #include <linux/timer.h>
 #include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/of_device.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/core.h>
 #include <linux/mmc/mmc.h>
@@ -1690,6 +1693,65 @@ static void omap_hsmmc_debugfs(struct mmc_host *mmc)
 
 #endif
 
+#ifdef CONFIG_OF
+static u16 omap4_reg_offset = 0x100;
+
+static const struct of_device_id omap_mmc_of_match[] = {
+	{
+		.compatible = "ti,omap2-hsmmc",
+	},
+	{
+		.compatible = "ti,omap3-hsmmc",
+	},
+	{
+		.compatible = "ti,omap4-hsmmc",
+		.data = &omap4_reg_offset,
+	},
+	{},
+}
+MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
+
+static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
+{
+	struct omap_mmc_platform_data *pdata;
+	struct device_node *np = dev->of_node;
+	u32 bus_width;
+
+	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return NULL; /* out of memory */
+
+	if (of_find_property(np, "ti,dual-volt", NULL))
+		pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
+
+	/* This driver only supports 1 slot */
+	pdata->nr_slots = 1;
+	pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
+	pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
+
+	if (of_find_property(np, "ti,non-removable", NULL)) {
+		pdata->slots[0].nonremovable = true;
+		pdata->slots[0].no_regulator_off_init = true;
+	}
+	of_property_read_u32(np, "ti,bus-width", &bus_width);
+	if (bus_width == 4)
+		pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
+	else if (bus_width == 8)
+		pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
+
+	if (of_find_property(np, "ti,needs-special-reset", NULL))
+		pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
+
+	return pdata;
+}
+#else
+static inline struct omap_mmc_platform_data
+			*of_get_hsmmc_pdata(struct device *dev)
+{
+	return NULL;
+}
+#endif
+
 static int __init omap_hsmmc_probe(struct platform_device *pdev)
 {
 	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
@@ -1697,6 +1759,16 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
 	struct omap_hsmmc_host *host = NULL;
 	struct resource *res;
 	int ret, irq;
+	const struct of_device_id *match;
+
+	match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
+	if (match) {
+		pdata = of_get_hsmmc_pdata(&pdev->dev);
+		if (match->data) {
+			u16 *offsetp = match->data;
+			pdata->reg_offset = *offsetp;
+		}
+	}
 
 	if (pdata == NULL) {
 		dev_err(&pdev->dev, "Platform Data is missing\n");
@@ -2102,6 +2174,7 @@ static struct platform_driver omap_hsmmc_driver = {
 		.name = DRIVER_NAME,
 		.owner = THIS_MODULE,
 		.pm = &omap_hsmmc_dev_pm_ops,
+		.of_match_table = of_match_ptr(omap_mmc_of_match),
 	},
 };
 
-- 
1.7.1



From peter.ujfalusi at ti.com  Fri Mar  9 10:45:19 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Fri, 09 Mar 2012 17:45:19 +0200
Subject: [PATCH] ARM: OMAP4: clock: Add aliases for McBSP fclk clocks
In-Reply-To: <1331024133-18201-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331024133-18201-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <4F5A258F.8050704@ti.com>

Hi Paul, Tony,

On 03/06/2012 10:55 AM, Peter Ujfalusi wrote:
> CLKS signal for McBSP ports can be selected from internal (PRCM) or external
> (ABE_CLKS pin) source.
> To be able to use existing code we need to create clock aliases consistent
> among OMAP2/3/4.

Would you be able to take a look at this patch?

Thanks,
P?ter


From khilman at ti.com  Fri Mar  9 10:29:28 2012
From: khilman at ti.com (Kevin Hilman)
Date: Fri, 09 Mar 2012 07:29:28 -0800
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators for
 v3.4
In-Reply-To: <20120309114731.GA3273@opensource.wolfsonmicro.com> (Mark Brown's
 message of "Fri, 9 Mar 2012 11:47:36 +0000")
References: <877gywjhht.fsf@ti.com> <20120308021843.GQ12083@atomide.com>
 <87399jc6cj.fsf@ti.com> <20120309003217.GB12083@atomide.com>
 <20120309114731.GA3273@opensource.wolfsonmicro.com>
Message-ID: <87zkbp4wtj.fsf@ti.com>

Mark Brown <broonie at opensource.wolfsonmicro.com> writes:

> On Thu, Mar 08, 2012 at 04:32:18PM -0800, Tony Lindgren wrote:
>> * Kevin Hilman <khilman at ti.com> [120308 09:37]:
>> > Tony Lindgren <tony at atomide.com> writes:
>
>> > Oh, that's because it depends on the regulator core changes that are in
>> > Mark's regulator tree.  You need the for-next branch of :
>
>> > git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git 
>
>> > For this to compile correctly.
>
>> > Sorry, I should've been more clear above about the build dependency.
>
>> Hmm just checking.. Recently Mark replied to Peter:
>
> ...
>
>> So can you guys please confirm that if is indeed an immutable
>> commit to use as a base to merge in something?
>
> Absolutely not, the for-next branch is rebuilt frequently especially
> since it includes stuff sent to Linus and he complained about bugfixes
> merged up into development code.  What is the actual dependency here?

The stuff is in your topic/drivers branch.  Specifically:

ed5da2a mfd: twl-core: regulator configuration for twl6030 V1V8, V2V1 SMPS
77a3915 regulator: twl-regulator: Add fixed LDO for V1V8, V2V1 supply
d64214b regulator: twl: adapt twl-regulator driver to dt
3e1ff1f regulator: twl6030: add support for vdd1, vdd2 and vdd3 regulators
1a4a805 regulator: twl4030: add support for external voltage get/set

> The topic branches are more or less static, though some more than
> others.

Is topic/drivers something stable?  If not, these are a ways back in
that branch, maybe you make a topic/drivers-stable for us?

> In general you should warn people if you've got a dependency on their
> tree, it makes life easier.

Yeah, I should've raised this when the original series were posted.  The
arch stuff and drivers/regulator stuff were posted all together, but you
picked out the regulator stuff and I picked up the rest.  

Kevin


From tomi.valkeinen at ti.com  Fri Mar  9 04:35:51 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 09 Mar 2012 11:35:51 +0200
Subject: linux-next: manual merge of the arm-soc tree with the
 omap_dss2 tree
In-Reply-To: <201203081616.12510.arnd@arndb.de>
References: <20120308170048.f1a992bca2ca2d93fa9747bf@canb.auug.org.au>
 <201203081616.12510.arnd@arndb.de>
Message-ID: <1331285751.1927.20.camel@deskari>

Hi,

On Thu, 2012-03-08 at 16:16 +0000, Arnd Bergmann wrote:
> On Thursday 08 March 2012, Stephen Rothwell wrote:
> > Hi all,
> > 
> > Today's linux-next merge of the arm-soc tree got a conflict in
> > arch/arm/mach-omap1/board-palmtt.c between commit ddba6c7f7ec6 ("OMAP1:
> > pass LCD config with omapfb_set_lcd_config()") from the omap_dss2 tree
> > and commit 2e3ee9f45b3c ("ARM: OMAP1: Move most of plat/io.h into local
> > iomap.h") from the arm-soc tree.
> > 
> > I fixed it up (see below) and can carry the fix as necessary.
> 
> Hi Stephen,
> 
> Thanks for fixing up all the conflicts between arm-soc and omap_dss2.
> I think we should make sure they are resolved in one of the trees before
> the merge window.

Do we need to? The conflicts seemed to be trivial ones, like arm-soc
adds/removes something that just happens to be next to something else
that I add/remove.

My understanding is that it's better to leave those conflicts than to do
"trickery" to avoid them.

> Tomi, what are your plans for the omap_dss2 branch to get merged?

Normally my tree goes via fbdev-tree (Florian's tree) to mainline.

> Do you think you should send it to Linus first and we merge it into
> arm-soc to resolve the conflicts?
> Or do you want to merge it through the arm-soc tree?
> Or should we go first and you fix up the conflicts by pulling in the
> necessary topic branches from arm-soc into your tree?

If we want to resolve the conflicts, perhaps it's simplest if the dss
tree is merged to arm-soc.

 Tomi

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From peter.ujfalusi at ti.com  Fri Mar  9 03:51:17 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Fri,  9 Mar 2012 10:51:17 +0200
Subject: [PATCH 1/2] ARM: OMAP: Remove CONFIG_OMAP_MCBSP references
In-Reply-To: <1331283078-14846-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331283078-14846-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1331283078-14846-2-git-send-email-peter.ujfalusi@ti.com>

The McBSP driver stack has been moved to ASoC. The CONFIG_OMAP_MCBSP will
be removed since the CONFIG_SND_OMAP_SOC_MCBSP will trigger to build the
McBSP (audio) drivers.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap1/Kconfig  |    3 ---
 arch/arm/mach-omap1/Makefile |    4 +++-
 arch/arm/mach-omap2/Makefile |    4 +++-
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 4f8d66f..922ab0d 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -37,7 +37,6 @@ comment "OMAP Board Type"
 config MACH_OMAP_INNOVATOR
 	bool "TI Innovator"
 	depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
-	select OMAP_MCBSP
 	help
           TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
           have such a board.
@@ -45,7 +44,6 @@ config MACH_OMAP_INNOVATOR
 config MACH_OMAP_H2
 	bool "TI H2 Support"
 	depends on ARCH_OMAP1 && ARCH_OMAP16XX
-	select OMAP_MCBSP
     	help
 	  TI OMAP 1610/1611B H2 board support. Say Y here if you have such
 	  a board.
@@ -72,7 +70,6 @@ config MACH_HERALD
 config MACH_OMAP_OSK
 	bool "TI OSK Support"
 	depends on ARCH_OMAP1 && ARCH_OMAP16XX
-	select OMAP_MCBSP
     	help
 	  TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here
           if you have such a board.
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 11c85cd..9923f92 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -6,7 +6,9 @@
 obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
 obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
 
-obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
+ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
+obj-y += mcbsp.o
+endif
 
 obj-$(CONFIG_OMAP_32K_TIMER)	+= timer32k.o
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index bd76394..06326a6 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -17,7 +17,9 @@ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
 
-obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
+ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
+obj-y += mcbsp.o
+endif
 
 obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
 
-- 
1.7.8.5



From grant.likely at secretlab.ca  Fri Mar  9 11:30:30 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 09 Mar 2012 09:30:30 -0700
Subject: Subject: [PATCH] MAINTAINERS: add maintainer entry for SAMSUNG
 EXYNOS DeviceTree
In-Reply-To: <CAJuYYwSqGDmuXrtBscCSFoQEOpWCQ-1H+2dHxeUYny7KwUPLOg@mail.gmail.com>
References: <00f301ccf0f7$39f222a0$add667e0$%kim@samsung.com>
 <CAJuYYwSqGDmuXrtBscCSFoQEOpWCQ-1H+2dHxeUYny7KwUPLOg@mail.gmail.com>
Message-ID: <20120309163030.661F93E0880@localhost>

On Wed, 22 Feb 2012 07:49:18 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> On 22 February 2012 05:46, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > Add Samsung EXYNOS DT maintainer
> >
> > Cc: Thomas Abraham <thomas.abraham at linaro.org>
> > Cc: Grant Likely <grant.likely at secretlab.ca>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> > ---
> > ??MAINTAINERS | ?? 10 ++++++++++
> > ??1 files changed, 10 insertions(+), 0 deletions(-)
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 9a648eb..5ac5aaf 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1065,6 +1065,16 @@ S: ?? ?? ?? Maintained
> > ??F: ?? ?? arch/arm/mach-s5p*/
> > ??F: ?? ?? arch/arm/mach-exynos*/
> >
> > +ARM/SAMSUNG EXYNOS DEVICE TREE
> > +M: ?? ?? Thomas Abraham <thomas.abraham at linaro.org>
> > +M: ?? ?? Kukjin Kim <kgene.kim at samsung.com>
> > +L: ?? ?? devicetree-discuss at lists.ozlabs.org (moderated for non-subscribers)
> > +L: ?? ?? linux-samsung-soc at vger.kernel.org (moderated for non-subscribers)
> > +S: ?? ?? Maintained
> > +F: ?? ?? arch/arm/boot/dts/exynos*
> > +F: ?? ?? arch/arm/mach-exynos/*dt.c
> > +F: ?? ?? Documentation/devicetree/*/*/*samsung*
> > +
> 
> Acked-by: Thomas Abraham <thomas.abraham at linaro.org>

Acked-by: Grant Likely <grant.likely at secretlab.ca>



From rnayak at ti.com  Mon Mar 12 11:02:39 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 12 Mar 2012 20:32:39 +0530
Subject: [PATCH v2 3/4] arm/dts: OMAP4: Add mmc controller nodes and board data
In-Reply-To: <1331564560-23276-1-git-send-email-rnayak@ti.com>
References: <1331564560-23276-1-git-send-email-rnayak@ti.com>
Message-ID: <1331564560-23276-4-git-send-email-rnayak@ti.com>

Add omap mmc related device tree data for OMAP4.
Currenly limited to only omap4-panda and omap4-sdp
boards.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/boot/dts/omap4-panda.dts |   22 ++++++++++++++++++++++
 arch/arm/boot/dts/omap4-sdp.dts   |   24 ++++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi      |   31 +++++++++++++++++++++++++++++++
 3 files changed, 77 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 29646dc..ea6f5bb 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -52,3 +52,25 @@
 &i2c4 {
 	clock-frequency = <400000>;
 };
+
+&mmc1 {
+	vmmc-supply = <&vmmc>;
+	ti,bus-width = <8>;
+};
+
+&mmc2 {
+	status = "disable";
+};
+
+&mmc3 {
+	status = "disable";
+};
+
+&mmc4 {
+	status = "disable";
+};
+
+&mmc5 {
+	ti,non-removable;
+	ti,bus-width = <4>;
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 01db8b7..852657a 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -70,3 +70,27 @@
 		reg = <0x1e>;
 	};
 };
+
+&mmc1 {
+	vmmc-supply = <&vmmc>;
+	ti,bus-width = <8>;
+};
+
+&mmc2 {
+	vmmc-supply = <&vaux1>;
+	ti,bus-width = <8>;
+	ti,non-removable;
+};
+
+&mmc3 {
+	status = "disable";
+};
+
+&mmc4 {
+	status = "disable";
+};
+
+&mmc5 {
+	ti,bus-width = <4>;
+	ti,non-removable;
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 29f4589..9226543 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -155,5 +155,36 @@
 			#size-cells = <0>;
 			ti,hwmods = "i2c4";
 		};
+
+		mmc1: mmc at 1 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc1";
+			ti,dual-volt;
+			ti,needs-special-reset;
+		};
+
+		mmc2: mmc at 2 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc2";
+			ti,needs-special-reset;
+		};
+
+		mmc3: mmc at 3 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc3";
+			ti,needs-special-reset;
+		};
+
+		mmc4: mmc at 4 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc4";
+			ti,needs-special-reset;
+		};
+
+		mmc5: mmc at 5 {
+			compatible = "ti,omap4-hsmmc";
+			ti,hwmods = "mmc5";
+			ti,needs-special-reset;
+		};
 	};
 };
-- 
1.7.1



From axel.lin at gmail.com  Fri Mar  9 03:25:28 2012
From: axel.lin at gmail.com (Axel Lin)
Date: Fri, 9 Mar 2012 16:25:28 +0800
Subject: [PATCH v11] Regulator: Add Anatop regulator driver
In-Reply-To: <1331279829-4584-1-git-send-email-paul.liu@linaro.org>
References: <1331279829-4584-1-git-send-email-paul.liu@linaro.org>
Message-ID: <CAF+7xWkA-rDML03U=7d30ipXV9buhbqnZYWS54nGVKZbkYxXJw@mail.gmail.com>

2012/3/9 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
>
> Anatop is an integrated regulator inside i.MX6 SoC.
> There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
> And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
> This patch adds the Anatop regulator driver.
>
> Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Acked-by: Shawn Guo <shawn.guo at linaro.org>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Liam Girdwood <lrg at ti.com>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Axel Lin <axel.lin at gmail.com>

The rdesc->n_voltage setting is missing.
Otherwise, Reviewed-by: Axel Lin <axel.lin at gmail.com>


From grant.likely at secretlab.ca  Mon Mar 12 13:30:05 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 11:30:05 -0600
Subject: [PATCH 4/8] ARM: OMAP1: Move 16xx GPIO system clock to platform
 init code
In-Reply-To: <20120221234042.18709.57610.stgit@kaulin.local>
References: <20120221233619.18709.87982.stgit@kaulin.local>
 <20120221234042.18709.57610.stgit@kaulin.local>
Message-ID: <20120312173005.A11093E07B0@localhost>

On Tue, 21 Feb 2012 15:40:42 -0800, Tony Lindgren <tony at atomide.com> wrote:
> This way we can remove omap_read/write call from the GPIO driver
> and remove include to linux/io.h.
> 
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Signed-off-by: Tony Lindgren <tony at atomide.com>

Acked-by: Grant Likely <grant.likely at secretlab.ca>

Who will be picking up this series?  How intertwined is it with your tree Tony?

g.

> ---
>  arch/arm/mach-omap1/gpio16xx.c |    7 +++++++
>  drivers/gpio/gpio-omap.c       |    8 --------
>  2 files changed, 7 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
> index 0f399bd..99cabc4 100644
> --- a/arch/arm/mach-omap1/gpio16xx.c
> +++ b/arch/arm/mach-omap1/gpio16xx.c
> @@ -218,6 +218,13 @@ static int __init omap16xx_gpio_init(void)
>  	if (!cpu_is_omap16xx())
>  		return -EINVAL;
>  
> +	/*
> +	 * Enable system clock for GPIO module.
> +	 * The CAM_CLK_CTRL *is* really the right place.
> +	 */
> +	omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
> +					ULPD_CAM_CLK_CTRL);
> +
>  	for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
>  		platform_device_register(omap16xx_gpio_dev[i]);
>  
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 0b05629..1078a14 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -18,7 +18,6 @@
>  #include <linux/syscore_ops.h>
>  #include <linux/err.h>
>  #include <linux/clk.h>
> -#include <linux/io.h>
>  #include <linux/slab.h>
>  #include <linux/pm_runtime.h>
>  
> @@ -1064,13 +1063,6 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
>  						+ OMAP1610_GPIO_IRQSTATUS1);
>  			__raw_writew(0x0014, bank->base
>  						+ OMAP1610_GPIO_SYSCONFIG);
> -
> -			/*
> -			 * Enable system clock for GPIO module.
> -			 * The CAM_CLK_CTRL *is* really the right place.
> -			 */
> -			omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
> -						ULPD_CAM_CLK_CTRL);
>  		}
>  		if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
>  			__raw_writel(0xffffffff, bank->base
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From hvaibhav at ti.com  Mon Mar 12 06:39:28 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 12 Mar 2012 10:39:28 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <20120312101757.GH5375@legolas.emea.dhcp.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <20120305225530.GJ12083@atomide.com>
 <79CD15C6BA57404B839C016229A409A83180F73D@DBDE01.ent.ti.com>
 <20120312093921.GA5375@legolas.emea.dhcp.ti.com>
 <79CD15C6BA57404B839C016229A409A831810E32@DBDE01.ent.ti.com>
 <20120312101757.GH5375@legolas.emea.dhcp.ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831810FE1@DBDE01.ent.ti.com>

On Mon, Mar 12, 2012 at 15:47:58, Balbi, Felipe wrote:
> Hi,
> 
> On Mon, Mar 12, 2012 at 09:48:20AM +0000, Hiremath, Vaibhav wrote:
> > On Mon, Mar 12, 2012 at 15:09:24, Balbi, Felipe wrote:
> > > On Fri, Mar 09, 2012 at 05:58:00PM +0000, Hiremath, Vaibhav wrote:
> > > > On Tue, Mar 06, 2012 at 04:25:30, Tony Lindgren wrote:
> > > > > Hi,
> > > > > 
> > > > > * Vaibhav Hiremath <hvaibhav at ti.com> [120119 06:01]:
> > > > > > OMAP device has 32k-sync timer which is currently used as a
> > > > > > clocksource in the kernel (omap2plus_defconfig).
> > > > > > The current implementation uses compile time selection between
> > > > > > gp-timer and 32k-sync timer, which breaks multi-omap build for
> > > > > > the devices like AM33xx, where 32k-sync timer is not available.
> > > > > > 
> > > > > > So use hwmod database lookup mechanism, through which at run-time
> > > > > > we can identify availability of 32k-sync timer on the device,
> > > > > > else fall back to gp-timer.
> > > > > ...
> > > > > 
> > > > > > --- a/arch/arm/plat-omap/counter_32k.c
> > > > > > +++ b/arch/arm/plat-omap/counter_32k.c
> > > > > > @@ -69,52 +69,55 @@ void read_persistent_clock(struct timespec *ts)
> > > > > >  
> > > > > >  int __init omap_init_clocksource_32k(void)
> > > > > >  {
> > > > > > -	static char err[] __initdata = KERN_ERR
> > > > > > -			"%s: can't register clocksource!\n";
> > > > > > -
> > > > > > -	if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
> > > > > > -		u32 pbase;
> > > > > > -		unsigned long size = SZ_4K;
> > > > > > -		void __iomem *base;
> > > > > > -		struct clk *sync_32k_ick;
> > > > > > -
> > > > > > -		if (cpu_is_omap16xx()) {
> > > > > > -			pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > > > > > -			size = SZ_1K;
> > > > > > -		} else if (cpu_is_omap2420())
> > > > > > -			pbase = OMAP2420_32KSYNCT_BASE + 0x10;
> > > > > > -		else if (cpu_is_omap2430())
> > > > > > -			pbase = OMAP2430_32KSYNCT_BASE + 0x10;
> > > > > > -		else if (cpu_is_omap34xx())
> > > > > > -			pbase = OMAP3430_32KSYNCT_BASE + 0x10;
> > > > > > -		else if (cpu_is_omap44xx())
> > > > > > -			pbase = OMAP4430_32KSYNCT_BASE + 0x10;
> > > > > > -		else
> > > > > > +	u32 pbase;
> > > > > > +	unsigned long size = SZ_4K;
> > > > > > +	void __iomem *base;
> > > > > > +	struct clk *sync_32k_ick;
> > > > > > +
> > > > > > +	if (cpu_is_omap16xx()) {
> > > > > > +		pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > > > > > +		size = SZ_1K;
> > > > > > +	} else if (cpu_class_is_omap2()) {
> > > > > > +		struct omap_hwmod *oh;
> > > > > > +		const char *oh_name = "counter_32k";
> > > > > > +
> > > > > > +		oh = omap_hwmod_lookup(oh_name);
> > > > > > +		if (!oh || oh->slaves_cnt == 0) {
> > > > > > +			pr_err("Could not lookup %s hwmod\n", oh_name);
> > > > > >  			return -ENODEV;
> > > > > > +		}
> > > > > > +		pbase = oh->slaves[0]->addr->pa_start + 0x10;
> > > > > > +	} else {
> > > > > > +		return -ENODEV;
> > > > > > +	}
> > > > > 
> > > > > How about have separate omap1 and omap2+ init functions that
> > > > > call a common function and passes the pbase as a parameter?
> > > > > 
> > > > > That way we can get rid of the cpu_is_omapxxxx tests here.
> > > > > 
> > > > 
> > > > Tony,
> > > > 
> > > > In the morning, I replied very soon, without much thinking...
> > > > 
> > > > Just now I started working on the patch, I was just reviewing the code, 
> > > > and I felt that, it is unnecessary to split the code between omap1 and 
> > > > omap2+.
> > > > 
> > > > The reason is,
> > > > 
> > > > Currently Only OMAP16xx base-address is hardcoded with
> > > > cpu_is_omap16xx() macro, For all other omap family of devices the
> > > > complete information is fetched from HWDMO api's/data.
> > > 
> > > In that case, why don't you create the platform_device by hand on
> > > arch/arm/mach-omap1/devices.c and move the omap2+ (which is based on
> > > hwmod) to arch/arm/mach-omap2/devices.c ?
> > > 
> > 
> > Balbi,
> > 
> > 32k_counter code is not a platform_device/driver, we don't build the 
> > any device here. We only need hwmod data to fetch the basic information like, 
> > base-address, size, etc...
> > 
> > And I am note sure whether we really intend to make it 
> > platform_device/driver thing.
> 
> that's kinda weird... 

Balbi,

Its not that weird, I think its because, this code is used as system 
clocksource.

> anyway, you can also pass base as argument to
> omap_init_clocksource_32k()... dunno.
> 

That's the whole point, just for one platform (omap16xx), we are changing the code. Rest all other platforms are using hwmod data, which is I believe 
is clean interface as of now.

To be more specific, we have to choose between something like -

"arch/arm/mach-omap1/timer32k.c"
bool __init omap_32k_timer_init(void) {
	omap_init_clocksource_32k(OMAP16XX_TIMER_32K_SYNCHRONIZED, SZ_1K);
	...
}
"arch/arm/mach-omap2/timer.c"

static void __init omap2_gp_clocksource_init(int gptimer_id,
                                                 const char *fck_source)
{
	/* Parse the hwmod data here*/
	Base = oh->slaves[0]->addr->pa_start + 0x10;
	Size = oh->slaves[0]->addr->pa_end - oh->slaves[0]->addr->pa_start;
	res = omap_init_clocksource_32k(base, size);
	if (!res)
		return;

	/* Fall back to gptimer */
}


OR

My current patch, which actually add cpu_is_16xx() check at one place and
does everything.


Thanks,
Vaibhav
> -- 
> balbi
> 



From LW at KARO-electronics.de  Fri Mar  9 06:47:58 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Fri, 9 Mar 2012 12:47:58 +0100
Subject: [RFC] i.MX: drop secondary clocks
In-Reply-To: <20120309102931.GY3852@pengutronix.de>
References: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
 <20313.52782.832292.580932@ipc1.ka-ro>
 <20120309102931.GY3852@pengutronix.de>
Message-ID: <20313.60910.420339.905973@ipc1.ka-ro>

Hi,

Sascha Hauer writes:
> On Fri, Mar 09, 2012 at 10:32:30AM +0100, Lothar Wa?mann wrote:
> > Hi,
> > 
> > Sascha Hauer writes:
> > > Hi All,
> > > 
[...]
> > I think that's a bad idea! Drivers should not have to know intimate
> > details about the clock logic of the CPU core they are running on!
> 
> They don't have to. There really are different clocks connected to the
> devices. If for example you have a look eSDHC Block diagram in the
> reference Manual  you'll see that this has three clock inputs. All
> we do is to tell the driver about these three clocks which are device
> specific and not SoC specific. Which of these clocks are actually
> gatetable varies from SoC to SoC. Also on some SoCs two of the three
> clocks may be actually the same.
> 
At least this should be done in a way that is independent from the
name of the clock on a specific SoC, but is related to the function of
the clock for the driver. Thus instead of e.g. CLK_IPG and CLK_PER use
CLK_REG and CLK_BITRATE.

> > They should simply request a clock for the unit they operate on and
> > the clock core code should figure out which other clocks need to be
> > enabled on a specific machine to get the unit working.
> 
> Yes, that's what we want to do, except that devices do not need 'a'
> clock but several. And the clock core figures out which other clocks
> have to be activated, these are the parent clocks.
> 
What about devices which have multiple 'parent' clocks that are
completely unrelated wrt. each other? In the current clock system you
can model this by having secondary clocks.
How would you represent the current structure on i.MX53:
uart_ipg_clk <- aips_tz1_clk <-+- ahb_clk
                               +-> ahb_max_clk
in the new model?
Should every driver have to request the ahb_max_clk in addition to the
uart_ipg_clk?

What, if you have a device on a number of SoCs with a certain set of
clocks, but on a later SoC another clock is required for the device?
You would not only have to change the driver to add the new clock but
also would have to add that clock as a dummy clock in the core clock
code for all previous SoCs that did not provide that clock.

> I also don't really like exposing this to the drivers, but it's a clean
> way to do so. A framebuffer driver needs a pixel clock which must be
> enabled when the display is turned on. It may also have a register clock
> which has to be turned on when we want to access registers. These are
> two different clocks and the driver can make use of this (not that we
> currently do though...)
> 
But we could do so without any problem.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From grant.likely at secretlab.ca  Thu Mar  8 23:33:19 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 08 Mar 2012 21:33:19 -0700
Subject: [PATCH 01/14] ARM: orion: spi: remove enable_clock_fix which is
 not used
In-Reply-To: <b0fe0cfb7e76a869a8ba7f7344de75eb122e206c.1331090356.git.jason@lakedaemon.net>
References: <cover.1331090356.git.jason@lakedaemon.net>
 <b0fe0cfb7e76a869a8ba7f7344de75eb122e206c.1331090356.git.jason@lakedaemon.net>
Message-ID: <20120309043319.316C93E0903@localhost>

On Wed,  7 Mar 2012 03:44:42 +0000, Jason Cooper <jason at lakedaemon.net> wrote:
> From: Andrew Lunn <andrew at lunn.ch>
> 
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>

Acked-by: Grant Likely <grant.likely at secretlab.ca>

> ---
>  drivers/spi/spi-orion.c       |    5 -----
>  include/linux/spi/orion_spi.h |    1 -
>  2 files changed, 0 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
> index 13448c8..e496f79 100644
> --- a/drivers/spi/spi-orion.c
> +++ b/drivers/spi/spi-orion.c
> @@ -359,11 +359,6 @@ static int orion_spi_setup(struct spi_device *spi)
>  
>  	orion_spi = spi_master_get_devdata(spi->master);
>  
> -	/* Fix ac timing if required.   */
> -	if (orion_spi->spi_info->enable_clock_fix)
> -		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
> -				  (1 << 14));
> -
>  	if ((spi->max_speed_hz == 0)
>  			|| (spi->max_speed_hz > orion_spi->max_speed))
>  		spi->max_speed_hz = orion_spi->max_speed;
> diff --git a/include/linux/spi/orion_spi.h b/include/linux/spi/orion_spi.h
> index decf6d8..b4d9fa6 100644
> --- a/include/linux/spi/orion_spi.h
> +++ b/include/linux/spi/orion_spi.h
> @@ -11,7 +11,6 @@
>  
>  struct orion_spi_info {
>  	u32	tclk;		/* no <linux/clk.h> support yet */
> -	u32	enable_clock_fix;
>  };
>  
>  
> -- 
> 1.7.3.4
> 

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies,Ltd.


From heiko at sntech.de  Mon Mar 12 15:01:02 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Mon, 12 Mar 2012 20:01:02 +0100
Subject: [PATCH 2/6] ARM: S3C24XX: claim spi channels for hsspi in dma-s3c2443
In-Reply-To: <201203121959.32966.heiko@sntech.de>
References: <201203121959.32966.heiko@sntech.de>
Message-ID: <201203122001.03099.heiko@sntech.de>

SoCs starting with the S3C2443 contain SPI controllers compatible with the
spi-s3c64xx driver and therefore need separate dma channels for rx and tx.

This patch introduces dma channel declarations for these and changes the
dma-s3c2443.c accordingly.

None of the older SoCs use the spi-dma at all. Most boards bitbang their
spi use and the spi-s3c24xx driver also does not use the dma system.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/dma-s3c2443.c      |   16 ++++++++++++----
 arch/arm/mach-s3c24xx/include/mach/dma.h |    4 ++++
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index e227c47..2d94228 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -55,12 +55,20 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
 		.name		= "sdi",
 		.channels	= MAP(S3C2443_DMAREQSEL_SDI),
 	},
-	[DMACH_SPI0] = {
-		.name		= "spi0",
+	[DMACH_SPI0_RX] = {
+		.name		= "spi0-rx",
+		.channels	= MAP(S3C2443_DMAREQSEL_SPI0RX),
+	},
+	[DMACH_SPI0_TX] = {
+		.name		= "spi0-tx",
 		.channels	= MAP(S3C2443_DMAREQSEL_SPI0TX),
 	},
-	[DMACH_SPI1] = { /* only on S3C2443/S3C2450 */
-		.name		= "spi1",
+	[DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
+		.name		= "spi1-rx",
+		.channels	= MAP(S3C2443_DMAREQSEL_SPI1RX),
+	},
+	[DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
+		.name		= "spi1-tx",
 		.channels	= MAP(S3C2443_DMAREQSEL_SPI1TX),
 	},
 	[DMACH_UART0] = {
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index acbdfec..454831b 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -47,6 +47,10 @@ enum dma_ch {
 	DMACH_UART2_SRC2,
 	DMACH_UART3,		/* s3c2443 has extra uart */
 	DMACH_UART3_SRC2,
+	DMACH_SPI0_TX,		/* s3c2443/2416/2450 hsspi0 */
+	DMACH_SPI0_RX,		/* s3c2443/2416/2450 hsspi0 */
+	DMACH_SPI1_TX,		/* s3c2443/2450 hsspi1 */
+	DMACH_SPI1_RX,		/* s3c2443/2450 hsspi1 */
 	DMACH_MAX,		/* the end entry */
 };
 
-- 
1.7.2.3



From paul.liu at linaro.org  Fri Mar  9 03:00:25 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Fri, 09 Mar 2012 16:00:25 +0800
Subject: [PATCH v10] Regulator: Add Anatop regulator driver
In-Reply-To: <20120308141847.GG27213@game.jcrosoft.org>
References: <1331200744-5986-1-git-send-email-paul.liu@linaro.org>
 <20120308141847.GG27213@game.jcrosoft.org>
Message-ID: <4F59B899.2080704@linaro.org>

(2012?03?08? 22:18), Jean-Christophe PLAGNIOL-VILLARD wrote:
>> +static int __devexit anatop_regulator_remove(struct platform_device *pdev)
>> +{
>> +	struct regulator_dev *rdev = platform_get_drvdata(pdev);
>> +	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
>> +	kfree(sreg->name);
>> +	regulator_unregister(rdev);
> return from the unregister
>> +	return 0;
>> +}
> Best Regards,
> J.

Hi Jean-Christophe,

I've modify the patch based on your review. However, the last one cannot
be made because regulator_unregister is void return.

Yours Sincerely,
Paul


From sfr at canb.auug.org.au  Fri Mar  9 02:06:47 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 9 Mar 2012 18:06:47 +1100
Subject: linux-next: manual merge of the arm-soc tree with the sound tree
Message-ID: <20120309180647.a27cc03a8997f9b38eb8ad0e@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got conflicts in
arch/arm/mach-imx/mm-imx3.c and arch/arm/mach-imx/mm-imx5.c between
commit 3bc34a614335 ("ARM: imx: convert audmux to a platform driver")
from the sound tree and commits 38bb3630bcba ("ARM: mx35: Setup the AIPS
registers") and aa6a9fa1f274 ("ARM: mx5: Use common function for
configuring AIPS") from the arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-imx/mm-imx3.c
index 9c9b7f9,1646991..0000000
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@@ -177,8 -175,9 +179,12 @@@ void __init imx31_soc_init(void
  	}
  
  	imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
+ 
+ 	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
+ 	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
++
 +	platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
 +					ARRAY_SIZE(imx31_audmux_res));
  }
  #endif /* ifdef CONFIG_SOC_IMX31 */
  
@@@ -267,8 -262,9 +273,13 @@@ void __init imx35_soc_init(void
  	}
  
  	imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
+ 
+ 	/* Setup AIPS registers */
+ 	imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
+ 	imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
++
 +	/* i.mx35 has the i.mx31 type audmux */
 +	platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
 +					ARRAY_SIZE(imx35_audmux_res));
  }
  #endif /* ifdef CONFIG_SOC_IMX35 */
diff --cc arch/arm/mach-imx/mm-imx5.c
index dc7c4ed,92efece..0000000
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@@ -201,9 -185,10 +201,14 @@@ void __init imx51_soc_init(void
  
  	/* i.mx51 has the i.mx35 type sdma */
  	imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
+ 
+ 	/* Setup AIPS registers */
+ 	imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
+ 	imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
++
 +	/* i.mx51 has the i.mx31 type audmux */
 +	platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
 +					ARRAY_SIZE(imx51_audmux_res));
  }
  
  void __init imx53_soc_init(void)
@@@ -219,7 -204,8 +224,12 @@@
  
  	/* i.mx53 has the i.mx35 type sdma */
  	imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
+ 
+ 	/* Setup AIPS registers */
+ 	imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
+ 	imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
++
 +	/* i.mx53 has the i.mx31 type audmux */
 +	platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
 +					ARRAY_SIZE(imx53_audmux_res));
  }
-------------- next part --------------
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From shawn.guo at linaro.org  Fri Mar  9 03:59:46 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 9 Mar 2012 16:59:46 +0800
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <20120309085943.GO2499@S2101-09.ap.freescale.net>

On Tue, Mar 06, 2012 at 10:33:21PM +0000, Russell King - ARM Linux wrote:
...
>  drivers/dma/imx-sdma.c                   |   23 ++------
...
>  drivers/dma/mxs-dma.c                    |   23 ++------

Tested-by: Shawn Guo <shawn.guo at linaro.org>


From shawn.guo at linaro.org  Fri Mar  9 00:00:59 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 9 Mar 2012 13:00:59 +0800
Subject: [PATCH v3 10/11] ASoC: fsl: let fsl_ssi work with imx pcm and
 machine drivers
In-Reply-To: <4F5980DE.9050002@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-11-git-send-email-shawn.guo@linaro.org>
 <4F591A69.9060401@freescale.com>
 <20120309031909.GJ2499@S2101-09.ap.freescale.net>
 <4F5980DE.9050002@freescale.com>
Message-ID: <20120309050057.GL2499@S2101-09.ap.freescale.net>

On Fri, Mar 09, 2012 at 04:02:40AM +0000, Tabi Timur-B04825 wrote:
> Shawn Guo wrote:
> 
> > Ok, got you.  We used to set fifo_depth on imx-ssi not the value given
> > by hardware manual, but the one already tuned.
> 
> What do you mean by "already tuned".  Tuned by whom?
> 
For example, we have SSI fifo depth 15 on i.MX51 design.  Instead of
having fifo_depth as 15 and then writing 15 - 2 into burstsize and
watermark, we used to have fifo_depth as 13, and then burstsize and
watermark can just be fifo_depth.

I agree that fsl_ssi does the right thing, having fifo_depth be the
hardware value.

> >>> +		 */
> >>> +		ssi_private->dma_params_tx.burstsize =
> >>> +			ssi_private->fifo_depth - 2;
> >>> +		ssi_private->dma_params_rx.burstsize =
> >>> +			ssi_private->fifo_depth - 2;
> >>> +		ssi_private->dma_params_tx.dma_addr =
> >>> +			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
> >>> +		ssi_private->dma_params_rx.dma_addr =
> >>> +			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
> >>
> >> So I'm a little confused by this new binding.  I went through a lot of
> >> work to remove DMA-specific data from the SSI driver, and here you are
> >> adding a bunch of it back.  What you're doing here -- I'm doing it in the
> >> DMA driver where it belongs.
> >
> > I'm not sure these all belong to DMA driver.  These are all
> > configurations/parameters of SSI, which are related to DMA though.
> > I see fsl_dma are handling these, but I do not fully agree with that,
> > because we end up with fsl_dma driver accessing SSI node and
> > "struct ccsr_ssi" which should be SSI private data.
> 
> Well, the SSI needs to tell the DMA driver how to program itself.  On 
> PowerPC, the DMA's burst size is based on the SSI's FIFO depth.  You're 
> effectively doing what I already do, except you do more work in the SSI 
> driver.
> 
> I understand that we need to support old and new bindings, but I already 
> created an infrastructure that supports passing SSI information to the DMA 
> driver.

I do not see an infrastructure, but that fsl_dma driver accesses SSI
private data structure.  Instead, snd_soc_dai_set[get]_dma_data looks
more like an infrastructure to me.

> It seems that the above code is different only for the sake of 
> being different, not because it's better.
> 
> This is not really an i.MX vs. PowerPC issue, which is why I'm not sure 
> this change belong in this patchset.
> 
Without this change, fsl_ssi can not work with imx-pcm-dma.  I do not
understand how it can possibly not belong in this patchset?

> > Secondly, this is the way that how imx-ssi and imx-pcm-dma works and
> > interacts.  If we want to move these stuff into imx-pcm-dma, we need
> > a good story to convince imx-ssi users that why it's better than what
> > they currently do.
> 
> I don't understand that.  You're already rewriting these drivers.  Who 
> else needs to be convinced?
> 
As I told before, even now we have fsl_ssi working for DT based IMX
platforms, imx5 and imx6, imx-ssi will still exist for those non-DT
IMX, like imx21, imx25, imx27, imx31, imx35.  That said, imx-pcm-dma
will need to work with both fsl_ssi and imx-ssi.  Moving those stuff
into imx-pcm-dma will require significant changes on imx-ssi too.

-- 
Regards,
Shawn


From myungjoo.ham at samsung.com  Fri Mar  9 02:06:15 2012
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Fri, 9 Mar 2012 16:06:15 +0900
Subject: [GIT PULL] Samsung Cleanup EXYNOS clock for v3.4
In-Reply-To: <22926872.16671331267895327.JavaMail.weblogic@epml04>
References: <22926872.16671331267895327.JavaMail.weblogic@epml04>
Message-ID: <CAJ0PZbQebwvFrmXWn=-m7YH3Ri7t2fvm+E_EKZ45rD7cAyo2UA@mail.gmail.com>

2012/3/9 ??? <myungjoo.ham at samsung.com>:
>> Hi Arnd, Olof,
>>
>> Here is cleanup clock part for EXYNOS SoCs from:
>>    git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> next/cleanup-exynos-clock
>>
>> Please pull and if any problems, please kindly let me know.
>
> Hello,
>
> It appears that some patches are missing in this branch; i.e., you seemed not to have pulled one required by this patchset: http://permalink.gmane.org/gmane.linux.kernel.samsung-soc/8474
>
> If the missing patches are included in another branch of yours and being pulled at somewhere else, please never mind. However, it doesn't appear so.
>
> Anyway, I'm rebasing the pull-requested branch upon most recent RC, so it'll be available soon (in an hour?) at http://git.infradead.org/users/kmpark/linux-samsung/shortlog/refs/heads/devfreq-for-samsung
>
>
> Cheers!
> MyungJoo.
>

Hello, Kgene

I've rebased the branch that was pull-requested to Kgene based on this branch.

http://git.infradead.org/users/kmpark/linux-samsung/shortlog/refs/heads/devfreq-for-samsung


The following changes since commit e01127814c640f6cd06a5c06731c6d1ee8c45101:

  PM / devfreq: update the name of EXYNOS clock register (2012-03-07
03:25:31 -0800)

are available in the git repository at:
  git://git.infradead.org / users/kmpark/linux-samsung devfreq-for-samsung

MyungJoo Ham (4):
      ARM: EXYNOS4: Add DMC1, allow PPMU access for DMC.
      ARM: EXYNOS4: Add clock register addresses for Exynos4x12 bus
devfreq driver
      ARM Exynos4210-Nuri: support Exynos4210-bus Devfreq driver.
      PM / devfreq: update the name of EXYNOS clock registers that were omitted.

 arch/arm/mach-exynos/common.c                  |    7 +++-
 arch/arm/mach-exynos/include/mach/map.h        |    1 +
 arch/arm/mach-exynos/include/mach/regs-clock.h |   42 ++++++++++++++++++++++++
 arch/arm/mach-exynos/mach-nuri.c               |   11 ++++--
 drivers/devfreq/exynos4_bus.c                  |    6 ++--
 5 files changed, 60 insertions(+), 7 deletions(-)



>>
>> The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:
>>
>>    Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)
>>
>> are available in the git repository at:
>>    git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> next/cleanup-exynos-clock
>>
>> Kukjin Kim (2):
>>        ARM: EXYNOS: cleanup clock part for new EXYNOS SoCs
>>        PM / devfreq: update the name of EXYNOS clock register
>>
>>   arch/arm/mach-exynos/Makefile                     |    3 +-
>>   arch/arm/mach-exynos/clock-exynos4.c              | 1564
>> +++++++++++++++++++++
>>   arch/arm/mach-exynos/clock-exynos4.h              |   32 +
>>   arch/arm/mach-exynos/clock-exynos4210.c           |   46 +-
>>   arch/arm/mach-exynos/clock-exynos4212.c           |   30 +-
>>   arch/arm/mach-exynos/clock.c                      | 1564
>> ---------------------
>>   arch/arm/mach-exynos/common.h                     |    9 +
>>   arch/arm/mach-exynos/include/mach/exynos4-clock.h |   43 -
>>   arch/arm/mach-exynos/include/mach/regs-clock.h    |  364 +++---
>>   arch/arm/mach-exynos/pm.c                         |   40 +-
>>   drivers/devfreq/exynos4_bus.c                     |  224 ++--
>>   11 files changed, 1959 insertions(+), 1960 deletions(-)
>>   create mode 100644 arch/arm/mach-exynos/clock-exynos4.c
>>   create mode 100644 arch/arm/mach-exynos/clock-exynos4.h
>>   delete mode 100644 arch/arm/mach-exynos/clock.c
>>   delete mode 100644 arch/arm/mach-exynos/include/mach/exynos4-clock.h
>>



-- 
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab, DMC Business, Samsung Electronics


From rnayak at ti.com  Mon Mar 12 02:10:06 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 12 Mar 2012 11:40:06 +0530
Subject: [PATCHv5 3/6] ARM: OMAP4 PM: Add IO Daisychain support
In-Reply-To: <4F5D8F2A.1070602@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-4-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203092051140.30879@utopia.booyaka.com>
 <4F5D8F2A.1070602@ti.com>
Message-ID: <4F5D933E.2070200@ti.com>

On Monday 12 March 2012 11:22 AM, Rajendra Nayak wrote:
>>
>> From: Rajendra Nayak<rnayak at ti.com>
>> Date: Fri, 2 Mar 2012 17:17:52 +0200
>> Subject: [PATCH 3/6] ARM: OMAP4: PRM: Add IO Daisychain support
>>
>> IO daisychain is a mechanism that allows individual IO pads to generate
>> wakeup events on their own based on a switch of an input signal level.
>> This allows the hardware module behind the pad to be powered down, but
>> still have device level capability to detect IO events, and once this
>> happens the module can be powered back up to resume IO. See section
>> 3.9.4 in OMAP4430 Public TRM for details.
>>
>> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
>> Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com> is just bad
> documentation.
>
>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
>> [paul at pwsan.com: removed MAX_IOPAD_LATCH_TIME declaration; renamed
>
> But the code below still seems to use it. Is it now defined in some
> common header so the same value is used in omap3 and omap4?

never mind, just saw the other updates from you. The patches look good
to me, except for the comment I add to add the second timeout back in
omap3.

Tero, was there a specific reason you got rid of it for omap3 in your
latest patch-set?


From shawn.guo at linaro.org  Fri Mar  9 02:28:22 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 9 Mar 2012 15:28:22 +0800
Subject: [PATCH v3 00/11] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <20120309071347.GM2499@S2101-09.ap.freescale.net>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <4F5910EE.8090408@freescale.com>
 <20120309011914.GF2499@S2101-09.ap.freescale.net>
 <4F5966DC.6090201@freescale.com>
 <20120309071347.GM2499@S2101-09.ap.freescale.net>
Message-ID: <CAAQ0ZWQHm+SZgDA6x93=Q9CxAqz6uVu1F2UPBc=zafrhT71D1Q@mail.gmail.com>

On 9 March 2012 15:13, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Fri, Mar 09, 2012 at 02:11:41AM +0000, Tabi Timur-B04825 wrote:
>> Shawn Guo wrote:
>> > Are you testing the patch set on top of the SHA below, which I
>> > mentioned in the cover letter?
>> >
>> > ? ?3030763 (Merge tag 'asoc-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into topic/asoc)
>> >
>> > I see the similar problem on the following SHA with my testing on
>> > imx-sgtl5000.
>> >
>> > ? ?1a8feca (Merge branch 'for-3.4' into asoc-next)
>>
>> It appears the problem is with for-3.4 itself. ?I'm running git-bisect now
>> to narrow it down.
>>
> My bisect tells that the offending commit is:
>
> ?96acc35 (ASoC: DAPM: Make sure DAPM widget IO ops hold the component mutex)
>
> But I do not understand why yet.

=============================================
[ INFO: possible recursive locking detected ]
3.3.0-rc4+ #159 Not tainted
---------------------------------------------
aplay/395 is trying to acquire lock:
 (&codec->mutex){+.+...}, at: [<802f7414>] soc_widget_update_bits_locked+0x88/0x
1a0

but task is already holding lock:
 (&codec->mutex){+.+...}, at: [<802f9df4>] snd_soc_dapm_stream_event+0x38/0xc0


From dwalker at fifo99.com  Mon Mar 12 16:14:21 2012
From: dwalker at fifo99.com (Daniel Walker)
Date: Mon, 12 Mar 2012 13:14:21 -0700
Subject: [PATCH v3 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 DMA APIs
In-Reply-To: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>
References: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>
Message-ID: <20120312201421.GA3459@fifo99.com>

On Mon, Mar 12, 2012 at 04:02:44PM +0530, Ravi Kumar V wrote:
> Add DMAEngine based driver using the old MSM DMA APIs internally.

What do you mean by this?

> The benefit of this approach is that not all the drivers
> have to get converted to DMAEngine APIs simultaneosly while
> both the drivers can stay enabled in the kernel. The client
> drivers using the old MSM APIs directly can now convert to
> DMAEngine one by one.

Which drivers?

Daniel


From robherring2 at gmail.com  Mon Mar 12 10:34:59 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 12 Mar 2012 09:34:59 -0500
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <1331561157-3820-1-git-send-email-sr@denx.de>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
Message-ID: <4F5E0993.9020000@gmail.com>

On 03/12/2012 09:05 AM, Stefan Roese wrote:
> This patch adds support to configure the STMMAC ethernet driver via
> device-tree instead of platform_data.
> 
> Currently, only the properties needed on SPEAr600 are provided. All
> other properties should be added once needed on other platforms.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> ---
>  Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
>  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66 +++++++++++++++++++-
>  2 files changed, 103 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt
> 
> diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
> new file mode 100644
> index 0000000..386a47f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/stmmac.txt
> @@ -0,0 +1,38 @@
> +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
> +
> +Required properties:
> +- compatible: Should be "stm,gmac"

This is too generic. This should be 1 string per version of h/w.

'stm' should be 'st' according to vendor-prefixes.txt.

> +- reg: Address and length of the register set for the device
> +- interrupt-parent: Should be the phandle for the interrupt controller
> +  that services interrupts for this device
> +- interrupts: Should contain the STMMAC interrupts
> +- interrupt-names: Should contain the interrupt names "macirq"
> +  "eth_wake_irq" if this interrupt is supported in the "interrupts"
> +  property

You should be able to tell this from the compatible string and number of
interrupts.

> +- phy-mode: String, operation mode of the PHY interface.
> +  Supported values are: "mii", "rmii", "gmii", "rgmii".
> +- phy-addr: MDIO address of the PHY

This is normally probed or the mdio bus is a sub-node of the MAC node.
See arch/powerpc/boot/dts/mpc8377_mds.dts for an example.

> +
> +Optional properties:
> +- stm,prog-burst-len: Specify the burst length
> +- stm,has-gmac: Indicates that the controller supports 1000Mbps
> +- stm,has-pmt: Indicates that the controller supports power management

I think these should all be encoded by the compatible string.

Rob

> +- mac-address: 6 bytes, mac address
> +
> +Examples:
> +
> +	gmac0: stmmac at e0800000 {
> +		compatible = "stm,gmac";
> +		reg = <0xe0800000 0x8000>;
> +		interrupt-parent = <&vic1>;
> +		interrupts = <24 23>;
> +		interrupt-names = "macirq", "eth_wake_irq";
> +		mac-address = [000000000000]; /* Filled in by U-Boot */
> +
> +		stm,prog-burst-len = <8>;
> +		stm,has-gmac;
> +		stm,has-pmt;
> +
> +		phy-mode = "gmii";
> +		phy-addr = <0>;
> +	};
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> index 3aad981..fcf46c7 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> @@ -24,8 +24,43 @@
>  
>  #include <linux/platform_device.h>
>  #include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_net.h>
>  #include "stmmac.h"
>  
> +#ifdef CONFIG_OF
> +static int __devinit stmmac_probe_config_dt(struct platform_device *pdev,
> +					    struct plat_stmmacenet_data *plat,
> +					    const char **mac)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +
> +	if (!np)
> +		return -ENODEV;
> +
> +	*mac = of_get_mac_address(np);
> +
> +	plat->interface = of_get_phy_mode(np);
> +	of_property_read_u32(np, "phy-addr", &plat->phy_addr);
> +	plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
> +					   sizeof(struct stmmac_mdio_bus_data),
> +					   GFP_KERNEL);
> +
> +	/*
> +	 * Currently only the properties needed on SPEAr600
> +	 * are provided. All other properties should be added
> +	 * once needed on other platforms.
> +	 */
> +	of_property_read_u32(np, "stm,prog-burst-len", &plat->pbl);
> +	if (of_get_property(np, "stm,has-gmac", NULL))
> +		plat->has_gmac = 1;
> +	if (of_get_property(np, "stm,has-pmt", NULL))
> +		plat->pmt = 1;
> +
> +	return 0;
> +}
> +#endif /* CONFIG_OF */
> +
>  /**
>   * stmmac_pltfr_probe
>   * @pdev: platform device pointer
> @@ -39,7 +74,8 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>  	struct resource *res;
>  	void __iomem *addr = NULL;
>  	struct stmmac_priv *priv = NULL;
> -	struct plat_stmmacenet_data *plat_dat;
> +	struct plat_stmmacenet_data *plat_dat = NULL;
> +	const char *mac = NULL;
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	if (!res)
> @@ -58,6 +94,22 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>  		ret = -ENOMEM;
>  		goto out_release_region;
>  	}
> +
> +#ifdef CONFIG_OF
> +	plat_dat = devm_kzalloc(&pdev->dev, sizeof(struct plat_stmmacenet_data),
> +				GFP_KERNEL);
> +	if (!plat_dat) {
> +		pr_err("%s: ERROR: no memory", __func__);
> +		ret = -ENOMEM;
> +		goto out_unmap;
> +	}
> +
> +	ret = stmmac_probe_config_dt(pdev, plat_dat, &mac);
> +	if (ret) {
> +		pr_err("%s: main dt probe failed", __func__);
> +		goto out_unmap;
> +	}
> +#else
>  	plat_dat = pdev->dev.platform_data;
>  
>  	/* Custom initialisation (if needed)*/
> @@ -66,6 +118,7 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>  		if (unlikely(ret))
>  			goto out_unmap;
>  	}
> +#endif
>  
>  	priv = stmmac_dvr_probe(&(pdev->dev), plat_dat, addr);
>  	if (!priv) {
> @@ -73,6 +126,10 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>  		goto out_unmap;
>  	}
>  
> +	/* Get MAC address if available (DT) */
> +	if (mac)
> +		memcpy(priv->dev->dev_addr, mac, ETH_ALEN);
> +
>  	/* Get the MAC information */
>  	priv->dev->irq = platform_get_irq_byname(pdev, "macirq");
>  	if (priv->dev->irq == -ENXIO) {
> @@ -178,6 +235,12 @@ static const struct dev_pm_ops stmmac_pltfr_pm_ops = {
>  static const struct dev_pm_ops stmmac_pltfr_pm_ops;
>  #endif /* CONFIG_PM */
>  
> +static const struct of_device_id stmmac_dt_ids[] = {
> +	{ .compatible = "stm,gmac", },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, stmmac_dt_ids);
> +
>  static struct platform_driver stmmac_driver = {
>  	.probe = stmmac_pltfr_probe,
>  	.remove = stmmac_pltfr_remove,
> @@ -185,6 +248,7 @@ static struct platform_driver stmmac_driver = {
>  		   .name = STMMAC_RESOURCE_NAME,
>  		   .owner = THIS_MODULE,
>  		   .pm = &stmmac_pltfr_pm_ops,
> +		   .of_match_table = of_match_ptr(stmmac_dt_ids),
>  		   },
>  };
>  



From robherring2 at gmail.com  Mon Mar 12 16:14:57 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 12 Mar 2012 15:14:57 -0500
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <1331366064-1273-3-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
Message-ID: <4F5E5941.3090305@gmail.com>

On 03/10/2012 01:54 AM, Mike Turquette wrote:
> The common clock framework defines a common struct clk useful across
> most platforms as well as an implementation of the clk api that drivers
> can use safely for managing clocks.
> 
> The net result is consolidation of many different struct clk definitions
> and platform-specific clock framework implementations.
> 
> This patch introduces the common struct clk, struct clk_ops and an
> implementation of the well-known clock api in include/clk/clk.h.
> Platforms may define their own hardware-specific clock structure and
> their own clock operation callbacks, so long as it wraps an instance of
> struct clk_hw.
> 
> See Documentation/clk.txt for more details.
> 
> This patch is based on the work of Jeremy Kerr, which in turn was based
> on the work of Ben Herrenschmidt.
> 
> Signed-off-by: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Mike Turquette <mturquette at ti.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Shawn Guo <shawn.guo at freescale.com>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Richard Zhao <richard.zhao at linaro.org>
> Cc: Saravana Kannan <skannan at codeaurora.org>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Stephen Boyd <sboyd at codeaurora.org>
> Cc: Amit Kucheria <amit.kucheria at linaro.org>
> Cc: Deepak Saxena <dsaxena at linaro.org>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Andrew Lunn <andrew at lunn.ch>
> ---

I've gotten this at least booting on highbank with DT clock bindings.

One comment below, but otherwise:

Reviewed-by: Rob Herring <rob.herring at calxeda.com>

> Changes since v5:
>  * new CONFIG_COMMON_CLK_DISABLE_UNUSED feature
>   * results in a new clk_op callback, .is_enabled
>  * new helpers
>   * __clk_get_prepare_count
>   * __clk_get_enable_count
>   * __clk_is_enabled
>  * fix bug in __clk_get_rate for orphan clocks
> 
>  drivers/clk/Kconfig          |   39 ++
>  drivers/clk/Makefile         |    1 +
>  drivers/clk/clk.c            | 1424 ++++++++++++++++++++++++++++++++++++++++++
>  include/linux/clk-private.h  |   68 ++
>  include/linux/clk-provider.h |  171 +++++
>  include/linux/clk.h          |   68 ++-
>  6 files changed, 1766 insertions(+), 5 deletions(-)
>  create mode 100644 drivers/clk/clk.c
>  create mode 100644 include/linux/clk-private.h
>  create mode 100644 include/linux/clk-provider.h
> 
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 9b3cd08..31ceb27 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -8,3 +8,42 @@ config HAVE_CLK_PREPARE
>  
>  config HAVE_MACH_CLKDEV
>  	bool
> +
> +menuconfig COMMON_CLK
> +	bool "Common Clock Framework"
> +	select HAVE_CLK_PREPARE
> +	---help---
> +	  The common clock framework is a single definition of struct
> +	  clk, useful across many platforms, as well as an
> +	  implementation of the clock API in include/linux/clk.h.
> +	  Architectures utilizing the common struct clk should select
> +	  this automatically, but it may be necessary to manually select
> +	  this option for loadable modules requiring the common clock
> +	  framework.
> +
> +	  If in doubt, say "N".
> +
> +if COMMON_CLK
> +
> +config COMMON_CLK_DISABLE_UNUSED
> +	bool "Disabled unused clocks at boot"
> +	depends on COMMON_CLK
> +	---help---
> +	  Traverses the entire clock tree and disables any clocks that are
> +	  enabled in hardware but have not been enabled by any device drivers.
> +	  This saves power and keeps the software model of the clock in line
> +	  with reality.
> +
> +	  If in doubt, say "N".
> +
> +config COMMON_CLK_DEBUG
> +	bool "DebugFS representation of clock tree"
> +	depends on COMMON_CLK

depends on or select DEBUG_FS


> +	---help---
> +	  Creates a directory hierchy in debugfs for visualizing the clk
> +	  tree structure.  Each directory contains read-only members
> +	  that export information specific to that clk node: clk_rate,
> +	  clk_flags, clk_prepare_count, clk_enable_count &
> +	  clk_notifier_count.
> +
> +endif
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 07613fa..ff362c4 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -1,2 +1,3 @@
>  
>  obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
> +obj-$(CONFIG_COMMON_CLK)	+= clk.o
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> new file mode 100644
> index 0000000..c7c3bc5
> --- /dev/null
> +++ b/drivers/clk/clk.c
> @@ -0,0 +1,1424 @@
> +/*
> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
> + * Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Standard functionality for the common clock API.  See Documentation/clk.txt
> + */
> +
> +#include <linux/clk-private.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/spinlock.h>
> +#include <linux/err.h>
> +#include <linux/list.h>
> +#include <linux/slab.h>
> +
> +static DEFINE_SPINLOCK(enable_lock);
> +static DEFINE_MUTEX(prepare_lock);
> +
> +static HLIST_HEAD(clk_root_list);
> +static HLIST_HEAD(clk_orphan_list);
> +static LIST_HEAD(clk_notifier_list);
> +
> +/***        debugfs support        ***/
> +
> +#ifdef CONFIG_COMMON_CLK_DEBUG
> +#include <linux/debugfs.h>
> +
> +static struct dentry *rootdir;
> +static struct dentry *orphandir;
> +static int inited = 0;
> +
> +/* caller must hold prepare_lock */
> +static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
> +{
> +	struct dentry *d;
> +	int ret = -ENOMEM;
> +
> +	if (!clk || !pdentry) {
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	d = debugfs_create_dir(clk->name, pdentry);
> +	if (!d)
> +		goto out;
> +
> +	clk->dentry = d;
> +
> +	d = debugfs_create_u32("clk_rate", S_IRUGO, clk->dentry,
> +			(u32 *)&clk->rate);
> +	if (!d)
> +		goto err_out;
> +
> +	d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
> +			(u32 *)&clk->flags);
> +	if (!d)
> +		goto err_out;
> +
> +	d = debugfs_create_u32("clk_prepare_count", S_IRUGO, clk->dentry,
> +			(u32 *)&clk->prepare_count);
> +	if (!d)
> +		goto err_out;
> +
> +	d = debugfs_create_u32("clk_enable_count", S_IRUGO, clk->dentry,
> +			(u32 *)&clk->enable_count);
> +	if (!d)
> +		goto err_out;
> +
> +	d = debugfs_create_u32("clk_notifier_count", S_IRUGO, clk->dentry,
> +			(u32 *)&clk->notifier_count);
> +	if (!d)
> +		goto err_out;
> +
> +	ret = 0;
> +	goto out;
> +
> +err_out:
> +	debugfs_remove(clk->dentry);
> +out:
> +	return ret;
> +}
> +
> +/* caller must hold prepare_lock */
> +static int clk_debug_create_subtree(struct clk *clk, struct dentry *pdentry)
> +{
> +	struct clk *child;
> +	struct hlist_node *tmp;
> +	int ret = -EINVAL;;
> +
> +	if (!clk || !pdentry)
> +		goto out;
> +
> +	ret = clk_debug_create_one(clk, pdentry);
> +
> +	if (ret)
> +		goto out;
> +
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node)
> +		clk_debug_create_subtree(child, clk->dentry);
> +
> +	ret = 0;
> +out:
> +	return ret;
> +}
> +
> +/**
> + * clk_debug_register - add a clk node to the debugfs clk tree
> + * @clk: the clk being added to the debugfs clk tree
> + *
> + * Dynamically adds a clk to the debugfs clk tree if debugfs has been
> + * initialized.  Otherwise it bails out early since the debugfs clk tree
> + * will be created lazily by clk_debug_init as part of a late_initcall.
> + *
> + * Caller must hold prepare_lock.  Only clk_init calls this function (so
> + * far) so this is taken care.
> + */
> +static int clk_debug_register(struct clk *clk)
> +{
> +	struct clk *parent;
> +	struct dentry *pdentry;
> +	int ret = 0;
> +
> +	if (!inited)
> +		goto out;
> +
> +	parent = clk->parent;
> +
> +	/*
> +	 * Check to see if a clk is a root clk.  Also check that it is
> +	 * safe to add this clk to debugfs
> +	 */
> +	if (!parent)
> +		if (clk->flags & CLK_IS_ROOT)
> +			pdentry = rootdir;
> +		else
> +			pdentry = orphandir;
> +	else
> +		if (parent->dentry)
> +			pdentry = parent->dentry;
> +		else
> +			goto out;
> +
> +	ret = clk_debug_create_subtree(clk, pdentry);
> +
> +out:
> +	return ret;
> +}
> +
> +/**
> + * clk_debug_init - lazily create the debugfs clk tree visualization
> + *
> + * clks are often initialized very early during boot before memory can
> + * be dynamically allocated and well before debugfs is setup.
> + * clk_debug_init walks the clk tree hierarchy while holding
> + * prepare_lock and creates the topology as part of a late_initcall,
> + * thus insuring that clks initialized very early will still be
> + * represented in the debugfs clk tree.  This function should only be
> + * called once at boot-time, and all other clks added dynamically will
> + * be done so with clk_debug_register.
> + */
> +static int __init clk_debug_init(void)
> +{
> +	struct clk *clk;
> +	struct hlist_node *tmp;
> +
> +	rootdir = debugfs_create_dir("clk", NULL);
> +
> +	if (!rootdir)
> +		return -ENOMEM;
> +
> +	orphandir = debugfs_create_dir("orphans", rootdir);
> +
> +	if (!orphandir)
> +		return -ENOMEM;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
> +		clk_debug_create_subtree(clk, rootdir);
> +
> +	hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
> +		clk_debug_create_subtree(clk, orphandir);
> +
> +	inited = 1;
> +
> +	mutex_unlock(&prepare_lock);
> +
> +	return 0;
> +}
> +late_initcall(clk_debug_init);
> +#else
> +static inline int clk_debug_register(struct clk *clk) { return 0; }
> +#endif /* CONFIG_COMMON_CLK_DEBUG */
> +
> +#ifdef CONFIG_COMMON_CLK_DISABLE_UNUSED
> +/* caller must hold prepare_lock */
> +static void clk_disable_unused_subtree(struct clk *clk)
> +{
> +	struct clk *child;
> +	struct hlist_node *tmp;
> +	unsigned long flags;
> +
> +	if (!clk)
> +		goto out;
> +
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node)
> +		clk_disable_unused_subtree(child);
> +
> +	spin_lock_irqsave(&enable_lock, flags);
> +
> +	if (clk->enable_count)
> +		goto unlock_out;
> +
> +	if (clk->flags & CLK_IGNORE_UNUSED)
> +		goto unlock_out;
> +
> +	if (__clk_is_enabled(clk) && clk->ops->disable)
> +		clk->ops->disable(clk->hw);
> +
> +unlock_out:
> +	spin_unlock_irqrestore(&enable_lock, flags);
> +
> +out:
> +	return;
> +}
> +
> +static int clk_disable_unused(void)
> +{
> +	struct clk *clk;
> +	struct hlist_node *tmp;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
> +		clk_disable_unused_subtree(clk);
> +
> +	hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
> +		clk_disable_unused_subtree(clk);
> +
> +	mutex_unlock(&prepare_lock);
> +
> +	return 0;
> +}
> +late_initcall(clk_disable_unused);
> +#else
> +static inline int clk_disable_unused(struct clk *clk) { return 0; }
> +#endif /* CONFIG_COMMON_CLK_DISABLE_UNUSED */
> +
> +/***    helper functions   ***/
> +
> +inline const char *__clk_get_name(struct clk *clk)
> +{
> +	return !clk ? NULL : clk->name;
> +}
> +
> +inline struct clk_hw *__clk_get_hw(struct clk *clk)
> +{
> +	return !clk ? NULL : clk->hw;
> +}
> +
> +inline u8 __clk_get_num_parents(struct clk *clk)
> +{
> +	return !clk ? -EINVAL : clk->num_parents;
> +}
> +
> +inline struct clk *__clk_get_parent(struct clk *clk)
> +{
> +	return !clk ? NULL : clk->parent;
> +}
> +
> +inline unsigned long __clk_get_enable_count(struct clk *clk)
> +{
> +	return !clk ? -EINVAL : clk->enable_count;
> +}
> +
> +inline unsigned long __clk_get_prepare_count(struct clk *clk)
> +{
> +	return !clk ? -EINVAL : clk->prepare_count;
> +}
> +
> +unsigned long __clk_get_rate(struct clk *clk)
> +{
> +	unsigned long ret;
> +
> +	if (!clk) {
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	ret = clk->rate;
> +
> +	if (clk->flags & CLK_IS_ROOT)
> +		goto out;
> +
> +	if (!clk->parent)
> +		ret = -ENODEV;
> +
> +out:
> +	return ret;
> +}
> +
> +inline unsigned long __clk_get_flags(struct clk *clk)
> +{
> +	return !clk ? -EINVAL : clk->flags;
> +}
> +
> +int __clk_is_enabled(struct clk *clk)
> +{
> +	int ret;
> +
> +	if (!clk)
> +		return -EINVAL;
> +
> +	/*
> +	 * .is_enabled is only mandatory for clocks that gate
> +	 * fall back to software usage counter if .is_enabled is missing
> +	 */
> +	if (!clk->ops->is_enabled) {
> +		ret = clk->enable_count ? 1 : 0;
> +		goto out;
> +	}
> +
> +	ret = clk->ops->is_enabled(clk->hw);
> +out:
> +	return ret;
> +}
> +
> +static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
> +{
> +	struct clk *child;
> +	struct clk *ret;
> +	struct hlist_node *tmp;
> +
> +	if (!strcmp(clk->name, name))
> +		return clk;
> +
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
> +		ret = __clk_lookup_subtree(name, child);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return NULL;
> +}
> +
> +struct clk *__clk_lookup(const char *name)
> +{
> +	struct clk *root_clk;
> +	struct clk *ret;
> +	struct hlist_node *tmp;
> +
> +	/* search the 'proper' clk tree first */
> +	hlist_for_each_entry(root_clk, tmp, &clk_root_list, child_node) {
> +		ret = __clk_lookup_subtree(name, root_clk);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	/* if not found, then search the orphan tree */
> +	hlist_for_each_entry(root_clk, tmp, &clk_orphan_list, child_node) {
> +		ret = __clk_lookup_subtree(name, root_clk);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return NULL;
> +}
> +
> +/***        clk api        ***/
> +
> +void __clk_unprepare(struct clk *clk)
> +{
> +	if (!clk)
> +		return;
> +
> +	if (WARN_ON(clk->prepare_count == 0))
> +		return;
> +
> +	if (--clk->prepare_count > 0)
> +		return;
> +
> +	WARN_ON(clk->enable_count > 0);
> +
> +	if (clk->ops->unprepare)
> +		clk->ops->unprepare(clk->hw);
> +
> +	__clk_unprepare(clk->parent);
> +}
> +
> +/**
> + * clk_unprepare - undo preparation of a clock source
> + * @clk: the clk being unprepare
> + *
> + * clk_unprepare may sleep, which differentiates it from clk_disable.  In a
> + * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
> + * if the operation may sleep.  One example is a clk which is accessed over
> + * I2c.  In the complex case a clk gate operation may require a fast and a slow
> + * part.  It is this reason that clk_unprepare and clk_disable are not mutually
> + * exclusive.  In fact clk_disable must be called before clk_unprepare.
> + */
> +void clk_unprepare(struct clk *clk)
> +{
> +	mutex_lock(&prepare_lock);
> +	__clk_unprepare(clk);
> +	mutex_unlock(&prepare_lock);
> +}
> +EXPORT_SYMBOL_GPL(clk_unprepare);
> +
> +int __clk_prepare(struct clk *clk)
> +{
> +	int ret = 0;
> +
> +	if (!clk)
> +		return 0;
> +
> +	if (clk->prepare_count == 0) {
> +		ret = __clk_prepare(clk->parent);
> +		if (ret)
> +			return ret;
> +
> +		if (clk->ops->prepare) {
> +			ret = clk->ops->prepare(clk->hw);
> +			if (ret) {
> +				__clk_unprepare(clk->parent);
> +				return ret;
> +			}
> +		}
> +	}
> +
> +	clk->prepare_count++;
> +
> +	return 0;
> +}
> +
> +/**
> + * clk_prepare - prepare a clock source
> + * @clk: the clk being prepared
> + *
> + * clk_prepare may sleep, which differentiates it from clk_enable.  In a simple
> + * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
> + * operation may sleep.  One example is a clk which is accessed over I2c.  In
> + * the complex case a clk ungate operation may require a fast and a slow part.
> + * It is this reason that clk_prepare and clk_enable are not mutually
> + * exclusive.  In fact clk_prepare must be called before clk_enable.
> + * Returns 0 on success, -EERROR otherwise.
> + */
> +int clk_prepare(struct clk *clk)
> +{
> +	int ret;
> +
> +	mutex_lock(&prepare_lock);
> +	ret = __clk_prepare(clk);
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_prepare);
> +
> +static void __clk_disable(struct clk *clk)
> +{
> +	if (!clk)
> +		return;
> +
> +	if (WARN_ON(clk->enable_count == 0))
> +		return;
> +
> +	if (--clk->enable_count > 0)
> +		return;
> +
> +	if (clk->ops->disable)
> +		clk->ops->disable(clk->hw);
> +
> +	if (clk->parent)
> +		__clk_disable(clk->parent);
> +}
> +
> +/**
> + * clk_disable - gate a clock
> + * @clk: the clk being gated
> + *
> + * clk_disable must not sleep, which differentiates it from clk_unprepare.  In
> + * a simple case, clk_disable can be used instead of clk_unprepare to gate a
> + * clk if the operation is fast and will never sleep.  One example is a
> + * SoC-internal clk which is controlled via simple register writes.  In the
> + * complex case a clk gate operation may require a fast and a slow part.  It is
> + * this reason that clk_unprepare and clk_disable are not mutually exclusive.
> + * In fact clk_disable must be called before clk_unprepare.
> + */
> +void clk_disable(struct clk *clk)
> +{
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&enable_lock, flags);
> +	__clk_disable(clk);
> +	spin_unlock_irqrestore(&enable_lock, flags);
> +}
> +EXPORT_SYMBOL_GPL(clk_disable);
> +
> +static int __clk_enable(struct clk *clk)
> +{
> +	int ret = 0;
> +
> +	if (!clk)
> +		return 0;
> +
> +	if (WARN_ON(clk->prepare_count == 0))
> +		return -ESHUTDOWN;
> +
> +	if (clk->enable_count == 0) {
> +		if (clk->parent)
> +			ret = __clk_enable(clk->parent);
> +
> +		if (ret)
> +			return ret;
> +
> +		if (clk->ops->enable) {
> +			ret = clk->ops->enable(clk->hw);
> +			if (ret) {
> +				__clk_disable(clk->parent);
> +				return ret;
> +			}
> +		}
> +	}
> +
> +	clk->enable_count++;
> +	return 0;
> +}
> +
> +/**
> + * clk_enable - ungate a clock
> + * @clk: the clk being ungated
> + *
> + * clk_enable must not sleep, which differentiates it from clk_prepare.  In a
> + * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
> + * if the operation will never sleep.  One example is a SoC-internal clk which
> + * is controlled via simple register writes.  In the complex case a clk ungate
> + * operation may require a fast and a slow part.  It is this reason that
> + * clk_enable and clk_prepare are not mutually exclusive.  In fact clk_prepare
> + * must be called before clk_enable.  Returns 0 on success, -EERROR
> + * otherwise.
> + */
> +int clk_enable(struct clk *clk)
> +{
> +	unsigned long flags;
> +	int ret;
> +
> +	spin_lock_irqsave(&enable_lock, flags);
> +	ret = __clk_enable(clk);
> +	spin_unlock_irqrestore(&enable_lock, flags);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_enable);
> +
> +/**
> + * clk_get_rate - return the rate of clk
> + * @clk: the clk whose rate is being returned
> + *
> + * Simply returns the cached rate of the clk.  Does not query the hardware.  If
> + * clk is NULL then returns -EINVAL.
> + */
> +unsigned long clk_get_rate(struct clk *clk)
> +{
> +	unsigned long rate;
> +
> +	mutex_lock(&prepare_lock);
> +	rate = __clk_get_rate(clk);
> +	mutex_unlock(&prepare_lock);
> +
> +	return rate;
> +}
> +EXPORT_SYMBOL_GPL(clk_get_rate);
> +
> +/**
> + * __clk_round_rate - round the given rate for a clk
> + * @clk: round the rate of this clock
> + *
> + * Caller must hold prepare_lock.  Useful for clk_ops such as .set_rate
> + */
> +unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	if (!clk && !clk->ops->round_rate)
> +		return -EINVAL;
> +
> +	return clk->ops->round_rate(clk->hw, rate, NULL);
> +}
> +
> +/**
> + * clk_round_rate - round the given rate for a clk
> + * @clk: the clk for which we are rounding a rate
> + * @rate: the rate which is to be rounded
> + *
> + * Takes in a rate as input and rounds it to a rate that the clk can actually
> + * use which is then returned.  If clk doesn't support round_rate operation
> + * then the rate passed in is returned.
> + */
> +long clk_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	unsigned long ret = rate;
> +
> +	mutex_lock(&prepare_lock);
> +	if (clk && clk->ops->round_rate)
> +		ret = __clk_round_rate(clk, rate);
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_round_rate);
> +
> +/**
> + * __clk_notify - call clk notifier chain
> + * @clk: struct clk * that is changing rate
> + * @msg: clk notifier type (see include/linux/clk.h)
> + * @old_rate: old clk rate
> + * @new_rate: new clk rate
> + *
> + * Triggers a notifier call chain on the clk rate-change notification
> + * for 'clk'.  Passes a pointer to the struct clk and the previous
> + * and current rates to the notifier callback.  Intended to be called by
> + * internal clock code only.  Returns NOTIFY_DONE from the last driver
> + * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
> + * a driver returns that.
> + */
> +static int __clk_notify(struct clk *clk, unsigned long msg,
> +		unsigned long old_rate, unsigned long new_rate)
> +{
> +	struct clk_notifier *cn;
> +	struct clk_notifier_data cnd;
> +	int ret = NOTIFY_DONE;
> +
> +	cnd.clk = clk;
> +	cnd.old_rate = old_rate;
> +	cnd.new_rate = new_rate;
> +
> +	list_for_each_entry(cn, &clk_notifier_list, node) {
> +		if (cn->clk == clk) {
> +			ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
> +					&cnd);
> +			break;
> +		}
> +	}
> +
> +	return ret;
> +}
> +
> +/**
> + * __clk_recalc_rates
> + * @clk: first clk in the subtree
> + * @msg: notification type (see include/linux/clk.h)
> + *
> + * Walks the subtree of clks starting with clk and recalculates rates as it
> + * goes.  Note that if a clk does not implement the recalc_rate operation then
> + * propagation of that subtree stops and all of that clks children will not
> + * have their rates updated.
> + *
> + * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
> + * if necessary.
> + *
> + * Caller must hold prepare_lock.
> + */
> +static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
> +{
> +	unsigned long old_rate;
> +	unsigned long parent_rate = 0;
> +	struct hlist_node *tmp;
> +	struct clk *child;
> +
> +	old_rate = clk->rate;
> +
> +	if (clk->parent)
> +		parent_rate = clk->parent->rate;
> +
> +	if (clk->ops->recalc_rate)
> +		clk->rate = clk->ops->recalc_rate(clk->hw, parent_rate);
> +	else
> +		clk->rate = parent_rate;
> +
> +	/*
> +	 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
> +	 * & ABORT_RATE_CHANGE notifiers
> +	 */
> +	if (clk->notifier_count && msg)
> +		__clk_notify(clk, msg, old_rate, clk->rate);
> +
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node)
> +		__clk_recalc_rates(child, msg);
> +}
> +
> +/**
> + * __clk_speculate_rates
> + * @clk: first clk in the subtree
> + * @parent_rate: the "future" rate of clk's parent
> + *
> + * Walks the subtree of clks starting with clk, speculating rates as it
> + * goes and firing off PRE_RATE_CHANGE notifications as necessary.
> + *
> + * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
> + * pre-rate change notifications and returns early if no clks in the
> + * subtree have subscribed to the notifications.
> + *
> + * Caller must hold prepare_lock.
> + */
> +static int __clk_speculate_rates(struct clk *clk, unsigned long parent_rate)
> +{
> +	struct hlist_node *tmp;
> +	struct clk *child;
> +	unsigned long new_rate;
> +	int ret = NOTIFY_DONE;
> +
> +	if (!clk->ops->recalc_rate)
> +		goto out;
> +
> +	new_rate = clk->ops->recalc_rate(clk->hw, parent_rate);
> +
> +	/* abort the rate change if a driver returns NOTIFY_BAD */
> +	if (clk->notifier_count)
> +		ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
> +
> +	if (ret == NOTIFY_BAD)
> +		goto out;
> +
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
> +		ret = __clk_speculate_rates(child, new_rate);
> +		if (ret == NOTIFY_BAD)
> +			break;
> +	}
> +
> +out:
> +	return ret;
> +}
> +
> +/**
> + * DOC: Using the CLK_SET_RATE_PARENT flag
> + *
> + * __clk_set_rate changes the child's rate before the parent's to more
> + * easily handle failure conditions.
> + *
> + * This means clk might run out of spec for a short time if its rate is
> + * increased before the parent's rate is updated.
> + *
> + * To prevent this consider setting the CLK_SET_RATE_GATE flag on any
> + * clk where you also set the CLK_SET_RATE_PARENT flag
> + *
> + * PRE_RATE_CHANGE notifications are supposed to stack as a rate change
> + * request propagates up the clk tree.  This reflects the different
> + * rates that a downstream clk might experience if left enabled while
> + * upstream parents change their rates.
> + */
> +static struct clk *__clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	struct clk *fail_clk = NULL;
> +	int ret = NOTIFY_DONE;
> +	unsigned long old_rate = clk->rate;
> +	unsigned long new_rate;
> +	unsigned long parent_old_rate;
> +	unsigned long parent_new_rate = 0;
> +	struct clk *child;
> +	struct hlist_node *tmp;
> +
> +	/* bail early if we can't change rate while clk is enabled */
> +	if ((clk->flags & CLK_SET_RATE_GATE) && clk->enable_count)
> +		return clk;
> +
> +	/* find the new rate and see if parent rate should change too */
> +	WARN_ON(!clk->ops->round_rate);
> +
> +	new_rate = clk->ops->round_rate(clk->hw, rate, &parent_new_rate);
> +
> +	/* NOTE: pre-rate change notifications will stack */
> +	if (clk->notifier_count)
> +		ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
> +
> +	if (ret == NOTIFY_BAD)
> +		return clk;
> +
> +	/* speculate rate changes down the tree */
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
> +		ret = __clk_speculate_rates(child, new_rate);
> +		if (ret == NOTIFY_BAD)
> +			return clk;
> +	}
> +
> +	/* change the rate of this clk */
> +	if (clk->ops->set_rate)
> +		ret = clk->ops->set_rate(clk->hw, new_rate);
> +
> +	if (ret == NOTIFY_BAD)
> +		return clk;
> +
> +	/*
> +	 * change the rate of the parent clk if necessary
> +	 *
> +	 * hitting the nested 'if' path implies we have hit a .set_rate
> +	 * failure somewhere upstream while propagating __clk_set_rate
> +	 * up the clk tree.  roll back the clk rates one by one and
> +	 * return the pointer to the clk that failed.  clk_set_rate will
> +	 * use the pointer to propagate a rate-change abort notifier
> +	 * from the "highest" point.
> +	 */
> +	if ((clk->flags & CLK_SET_RATE_PARENT) && parent_new_rate) {
> +		parent_old_rate = clk->parent->rate;
> +		fail_clk = __clk_set_rate(clk->parent, parent_new_rate);
> +
> +		/* roll back changes if parent rate change failed */
> +		if (fail_clk) {
> +			pr_warn("%s: failed to set parent %s rate to %lu\n",
> +					__func__, fail_clk->name,
> +					parent_new_rate);
> +
> +			/*
> +			 * Send PRE_RATE_CHANGE notifiers down the tree
> +			 * again, since we're rolling back the rate
> +			 * changes due to the abort.
> +			 *
> +			 * Ignore any NOTIFY_BAD's since this *is* the
> +			 * exception handler.
> +			 *
> +			 * NOTE: pre-rate change notifications will stack
> +			 */
> +			__clk_speculate_rates(clk, clk->parent->rate);
> +
> +			clk->ops->set_rate(clk->hw, old_rate);
> +		}
> +		return fail_clk;
> +	}
> +
> +	/*
> +	 * set clk's rate & recalculate the rates of clk's children
> +	 *
> +	 * hitting this path implies we have successfully finished
> +	 * propagating recursive calls to __clk_set_rate up the clk tree
> +	 * (if necessary) and it is safe to propagate __clk_recalc_rates
> +	 * and post-rate change notifiers down the clk tree from this
> +	 * point.
> +	 */
> +	__clk_recalc_rates(clk, POST_RATE_CHANGE);
> +
> +	return NULL;
> +}
> +
> +/**
> + * clk_set_rate - specify a new rate for clk
> + * @clk: the clk whose rate is being changed
> + * @rate: the new rate for clk
> + *
> + * In the simplest case clk_set_rate will only change the rate of clk.
> + *
> + * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call
> + * will fail; only when the clk is disabled will it be able to change
> + * its rate.
> + *
> + * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to
> + * recursively propagate up to clk's parent; whether or not this happens
> + * depends on the outcome of clk's .round_rate implementation.  If
> + * *parent_rate is 0 after calling .round_rate then upstream parent
> + * propagation is ignored.  If *parent_rate comes back with a new rate
> + * for clk's parent then we propagate up to clk's parent and set it's
> + * rate.  Upward propagation will continue until either a clk does not
> + * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting
> + * changes to clk's parent_rate.  If there is a failure during upstream
> + * propagation then clk_set_rate will unwind and restore each clk's rate
> + * that had been successfully changed.  Afterwards a rate change abort
> + * notification will be propagated downstream, starting from the clk
> + * that failed.
> + *
> + * At the end of all of the rate setting, clk_set_rate internally calls
> + * __clk_recalc_rates and propagates the rate changes downstream,
> + * starting from the highest clk whose rate was changed.  This has the
> + * added benefit of propagating post-rate change notifiers.
> + *
> + * Note that while post-rate change and rate change abort notifications
> + * are guaranteed to be sent to a clk only once per call to
> + * clk_set_rate, pre-change notifications will be sent for every clk
> + * whose rate is changed.  Stacking pre-change notifications is noisy
> + * for the drivers subscribed to them, but this allows drivers to react
> + * to intermediate clk rate changes up until the point where the final
> + * rate is achieved at the end of upstream propagation.
> + *
> + * Returns 0 on success, -EERROR otherwise.
> + */
> +int clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	struct clk *fail_clk;
> +	int ret = 0;
> +
> +	/* prevent racing with updates to the clock topology */
> +	mutex_lock(&prepare_lock);
> +
> +	/* bail early if nothing to do */
> +	if (rate == clk->rate)
> +		goto out;
> +
> +	fail_clk = __clk_set_rate(clk, rate);
> +	if (fail_clk) {
> +		pr_warn("%s: failed to set %s rate\n", __func__,
> +				fail_clk->name);
> +		__clk_recalc_rates(clk, ABORT_RATE_CHANGE);
> +		ret = -EIO;
> +	}
> +
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_set_rate);
> +
> +/**
> + * clk_get_parent - return the parent of a clk
> + * @clk: the clk whose parent gets returned
> + *
> + * Simply returns clk->parent.  Returns NULL if clk is NULL.
> + */
> +struct clk *clk_get_parent(struct clk *clk)
> +{
> +	struct clk *parent;
> +
> +	mutex_lock(&prepare_lock);
> +	parent = __clk_get_parent(clk);
> +	mutex_unlock(&prepare_lock);
> +
> +	return parent;
> +}
> +EXPORT_SYMBOL_GPL(clk_get_parent);
> +
> +/*
> + * .get_parent is mandatory for clocks with multiple possible parents.  It is
> + * optional for single-parent clocks.  Always call .get_parent if it is
> + * available and WARN if it is missing for multi-parent clocks.
> + *
> + * For single-parent clocks without .get_parent, first check to see if the
> + * .parents array exists, and if so use it to avoid an expensive tree
> + * traversal.  If .parents does not exist then walk the tree with __clk_lookup.
> + */
> +static struct clk *__clk_init_parent(struct clk *clk)
> +{
> +	struct clk *ret = NULL;
> +	u8 index;
> +
> +	/* handle the trivial cases */
> +
> +	if (!clk->num_parents)
> +		goto out;
> +
> +	if (clk->num_parents == 1) {
> +		if (IS_ERR_OR_NULL(clk->parent))
> +			ret = clk->parent = __clk_lookup(clk->parent_names[0]);
> +		ret = clk->parent;
> +		goto out;
> +	}
> +
> +	if (!clk->ops->get_parent) {
> +		WARN(!clk->ops->get_parent,
> +			"%s: multi-parent clocks must implement .get_parent\n",
> +			__func__);
> +		goto out;
> +	};
> +
> +	/*
> +	 * Do our best to cache parent clocks in clk->parents.  This prevents
> +	 * unnecessary and expensive calls to __clk_lookup.  We don't set
> +	 * clk->parent here; that is done by the calling function
> +	 */
> +
> +	index = clk->ops->get_parent(clk->hw);
> +
> +	if (!clk->parents)
> +		clk->parents =
> +			kmalloc((sizeof(struct clk*) * clk->num_parents),
> +					GFP_KERNEL);
> +
> +	if (!clk->parents)
> +		ret = __clk_lookup(clk->parent_names[index]);
> +	else if (!clk->parents[index])
> +		ret = clk->parents[index] =
> +			__clk_lookup(clk->parent_names[index]);
> +	else
> +		ret = clk->parents[index];
> +
> +out:
> +	return ret;
> +}
> +
> +void __clk_reparent(struct clk *clk, struct clk *new_parent)
> +{
> +#ifdef CONFIG_COMMON_CLK_DEBUG
> +	struct dentry *d;
> +	struct dentry *new_parent_d;
> +#endif
> +
> +	if (!clk || !new_parent)
> +		return;
> +
> +	hlist_del(&clk->child_node);
> +
> +	if (new_parent)
> +		hlist_add_head(&clk->child_node, &new_parent->children);
> +	else
> +		hlist_add_head(&clk->child_node, &clk_orphan_list);
> +
> +#ifdef CONFIG_COMMON_CLK_DEBUG
> +	if (!inited)
> +		goto out;
> +
> +	if (new_parent)
> +		new_parent_d = new_parent->dentry;
> +	else
> +		new_parent_d = orphandir;
> +
> +	d = debugfs_rename(clk->dentry->d_parent, clk->dentry,
> +			new_parent_d, clk->name);
> +	if (d)
> +		clk->dentry = d;
> +	else
> +		pr_debug("%s: failed to rename debugfs entry for %s\n",
> +				__func__, clk->name);
> +out:
> +#endif
> +
> +	clk->parent = new_parent;
> +
> +	__clk_recalc_rates(clk, POST_RATE_CHANGE);
> +}
> +
> +static int __clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> +	struct clk *old_parent;
> +	unsigned long flags;
> +	int ret = -EINVAL;
> +	u8 i;
> +
> +	old_parent = clk->parent;
> +
> +	/* find index of new parent clock using cached parent ptrs */
> +	for (i = 0; i < clk->num_parents; i++)
> +		if (clk->parents[i] == parent)
> +			break;
> +
> +	/*
> +	 * find index of new parent clock using string name comparison
> +	 * also try to cache the parent to avoid future calls to __clk_lookup
> +	 */
> +	if (i == clk->num_parents)
> +		for (i = 0; i < clk->num_parents; i++)
> +			if (!strcmp(clk->parent_names[i], parent->name)) {
> +				clk->parents[i] = __clk_lookup(parent->name);
> +				break;
> +			}
> +
> +	if (i == clk->num_parents) {
> +		pr_debug("%s: clock %s is not a possible parent of clock %s\n",
> +				__func__, parent->name, clk->name);
> +		goto out;
> +	}
> +
> +	/* migrate prepare and enable */
> +	if (clk->prepare_count)
> +		__clk_prepare(parent);
> +
> +	/* FIXME replace with clk_is_enabled(clk) someday */
> +	spin_lock_irqsave(&enable_lock, flags);
> +	if (clk->enable_count)
> +		__clk_enable(parent);
> +	spin_unlock_irqrestore(&enable_lock, flags);
> +
> +	/* change clock input source */
> +	ret = clk->ops->set_parent(clk->hw, i);
> +
> +	/* clean up old prepare and enable */
> +	spin_lock_irqsave(&enable_lock, flags);
> +	if (clk->enable_count)
> +		__clk_disable(old_parent);
> +	spin_unlock_irqrestore(&enable_lock, flags);
> +
> +	if (clk->prepare_count)
> +		__clk_unprepare(old_parent);
> +
> +out:
> +	return ret;
> +}
> +
> +/**
> + * clk_set_parent - switch the parent of a mux clk
> + * @clk: the mux clk whose input we are switching
> + * @parent: the new input to clk
> + *
> + * Re-parent clk to use parent as it's new input source.  If clk has the
> + * CLK_SET_PARENT_GATE flag set then clk must be gated for this
> + * operation to succeed.  After successfully changing clk's parent
> + * clk_set_parent will update the clk topology, sysfs topology and
> + * propagate rate recalculation via __clk_recalc_rates.  Returns 0 on
> + * success, -EERROR otherwise.
> + */
> +int clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> +	int ret = 0;
> +
> +	if (!clk || !clk->ops)
> +		return -EINVAL;
> +
> +	if (!clk->ops->set_parent)
> +		return -ENOSYS;
> +
> +	/* prevent racing with updates to the clock topology */
> +	mutex_lock(&prepare_lock);
> +
> +	if (clk->parent == parent)
> +		goto out;
> +
> +	/* propagate PRE_RATE_CHANGE notifications */
> +	if (clk->notifier_count)
> +		ret = __clk_speculate_rates(clk, parent->rate);
> +
> +	/* abort if a driver objects */
> +	if (ret == NOTIFY_STOP)
> +		goto out;
> +
> +	/* only re-parent if the clock is not in use */
> +	if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count)
> +		ret = -EBUSY;
> +	else
> +		ret = __clk_set_parent(clk, parent);
> +
> +	/* propagate ABORT_RATE_CHANGE if .set_parent failed */
> +	if (ret) {
> +		__clk_recalc_rates(clk, ABORT_RATE_CHANGE);
> +		goto out;
> +	}
> +
> +	/* propagate rate recalculation downstream */
> +	__clk_reparent(clk, parent);
> +
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_set_parent);
> +
> +/**
> + * __clk_init - initialize the data structures in a struct clk
> + * @dev:	device initializing this clk, placeholder for now
> + * @clk:	clk being initialized
> + *
> + * Initializes the lists in struct clk, queries the hardware for the
> + * parent and rate and sets them both.
> + *
> + * Any struct clk passed into __clk_init must have the following members
> + * populated:
> + * 	.name
> + * 	.ops
> + * 	.hw
> + * 	.parent_names
> + * 	.num_parents
> + * 	.flags
> + *
> + * Essentially, everything that would normally be passed into clk_register is
> + * assumed to be initialized already in __clk_init.  The other members may be
> + * populated, but are optional.
> + *
> + * __clk_init is only exposed via clk-private.h and is intended for use with
> + * very large numbers of clocks that need to be statically initialized.  It is
> + * a layering violation to include clk-private.h from any code which implements
> + * a clock's .ops; as such any statically initialized clock data MUST be in a
> + * separate C file from the logic that implements it's operations.
> + */
> +void __clk_init(struct device *dev, struct clk *clk)
> +{
> +	int i;
> +	struct clk *orphan;
> +	struct hlist_node *tmp;
> +
> +	if (!clk)
> +		return;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	/* check to see if a clock with this name is already registered */
> +	if (__clk_lookup(clk->name))
> +		goto out;
> +
> +	/*
> +	 * Allocate an array of struct clk *'s to avoid unnecessary string
> +	 * look-ups of clk's possible parents.  This can fail for clocks passed
> +	 * in to clk_init during early boot; thus any access to clk->parents[]
> +	 * must always check for a NULL pointer and try to populate it if
> +	 * necessary.
> +	 *
> +	 * If clk->parents is not NULL we skip this entire block.  This allows
> +	 * for clock drivers to statically initialize clk->parents.
> +	 */
> +	if (clk->num_parents && !clk->parents) {
> +		clk->parents = kmalloc((sizeof(struct clk*) * clk->num_parents),
> +				GFP_KERNEL);
> +		/*
> +		 * __clk_lookup returns NULL for parents that have not been
> +		 * clk_init'd; thus any access to clk->parents[] must check
> +		 * for a NULL pointer.  We can always perform lazy lookups for
> +		 * missing parents later on.
> +		 */
> +		if (clk->parents)
> +			for (i = 0; i < clk->num_parents; i++)
> +				clk->parents[i] =
> +					__clk_lookup(clk->parent_names[i]);
> +	}
> +
> +	clk->parent = __clk_init_parent(clk);
> +
> +	/*
> +	 * Populate clk->parent if parent has already been __clk_init'd.  If
> +	 * parent has not yet been __clk_init'd then place clk in the orphan
> +	 * list.  If clk has set the CLK_IS_ROOT flag then place it in the root
> +	 * clk list.
> +	 *
> +	 * Every time a new clk is clk_init'd then we walk the list of orphan
> +	 * clocks and re-parent any that are children of the clock currently
> +	 * being clk_init'd.
> +	 */
> +	if (clk->parent)
> +		hlist_add_head(&clk->child_node,
> +				&clk->parent->children);
> +	else if (clk->flags & CLK_IS_ROOT)
> +		hlist_add_head(&clk->child_node, &clk_root_list);
> +	else
> +		hlist_add_head(&clk->child_node, &clk_orphan_list);
> +
> +	/*
> +	 * Set clk's rate.  The preferred method is to use .recalc_rate.  For
> +	 * simple clocks and lazy developers the default fallback is to use the
> +	 * parent's rate.  If a clock doesn't have a parent (or is orphaned)
> +	 * then rate is set to zero.
> +	 */
> +	if (clk->ops->recalc_rate)
> +		clk->rate = clk->ops->recalc_rate(clk->hw,
> +				__clk_get_rate(clk->parent));
> +	else if (clk->parent)
> +		clk->rate = clk->parent->rate;
> +	else
> +		clk->rate = 0;
> +
> +	/*
> +	 * walk the list of orphan clocks and reparent any that are children of
> +	 * this clock
> +	 */
> +	hlist_for_each_entry(orphan, tmp, &clk_orphan_list, child_node)
> +		__clk_reparent(orphan, __clk_init_parent(orphan));
> +
> +	/*
> +	 * optional platform-specific magic
> +	 *
> +	 * The .init callback is not used by any of the basic clock types, but
> +	 * exists for weird hardware that must perform initialization magic.
> +	 * Please consider other ways of solving initialization problems before
> +	 * using this callback, as it's use is discouraged.
> +	 */
> +	if (clk->ops->init)
> +		clk->ops->init(clk->hw);
> +
> +	clk_debug_register(clk);
> +
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return;
> +}
> +
> +/**
> + * clk_register - allocate a new clock, register it and return an opaque cookie
> + * @dev: device that is registering this clock
> + * @name: clock name
> + * @ops: operations this clock supports
> + * @hw: link to hardware-specific clock data
> + * @parent_names: array of string names for all possible parents
> + * @num_parents: number of possible parents
> + * @flags: framework-level hints and quirks
> + *
> + * clk_register is the primary interface for populating the clock tree with new
> + * clock nodes.  It returns a pointer to the newly allocated struct clk which
> + * cannot be dereferenced by driver code but may be used in conjuction with the
> + * rest of the clock API.
> + */
> +struct clk *clk_register(struct device *dev, const char *name,
> +		const struct clk_ops *ops, struct clk_hw *hw,
> +		char **parent_names, u8 num_parents, unsigned long flags)
> +{
> +	struct clk *clk;
> +
> +	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
> +	if (!clk)
> +		return NULL;
> +
> +	clk->name = name;
> +	clk->ops = ops;
> +	clk->hw = hw;
> +	clk->flags = flags;
> +	clk->parent_names = parent_names;
> +	clk->num_parents = num_parents;
> +	hw->clk = clk;
> +
> +	__clk_init(dev, clk);
> +
> +	return clk;
> +}
> +EXPORT_SYMBOL_GPL(clk_register);
> +
> +/***        clk rate change notifiers        ***/
> +
> +/**
> + * clk_notifier_register - add a clk rate change notifier
> + * @clk: struct clk * to watch
> + * @nb: struct notifier_block * with callback info
> + *
> + * Request notification when clk's rate changes.  This uses an SRCU
> + * notifier because we want it to block and notifier unregistrations are
> + * uncommon.  The callbacks associated with the notifier must not
> + * re-enter into the clk framework by calling any top-level clk APIs;
> + * this will cause a nested prepare_lock mutex.
> + *
> + * Pre-change notifier callbacks will be passed the current, pre-change
> + * rate of the clk via struct clk_notifier_data.old_rate.  The new,
> + * post-change rate of the clk is passed via struct
> + * clk_notifier.new_rate.
> + *
> + * Post-change notifiers will pass the now-current, post-change rate of
> + * the clk in both struct clk_notifier_data.old_rate and struct
> + * clk_notifier_data.new_rate.
> + *
> + * Abort-change notifiers are effectively the opposite of pre-change
> + * notifiers: the original pre-change clk rate is passed in via struct
> + * clk_notifier_data.new_rate and the failed post-change rate is passed
> + * in via struct clk_notifier_data.old_rate.
> + *
> + * clk_notifier_register() must be called from non-atomic context.
> + * Returns -EINVAL if called with null arguments, -ENOMEM upon
> + * allocation failure; otherwise, passes along the return value of
> + * srcu_notifier_chain_register().
> + */
> +int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
> +{
> +	struct clk_notifier *cn;
> +	int ret = -ENOMEM;
> +
> +	if (!clk || !nb)
> +		return -EINVAL;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	/* search the list of notifiers for this clk */
> +	list_for_each_entry(cn, &clk_notifier_list, node)
> +		if (cn->clk == clk)
> +			break;
> +
> +	/* if clk wasn't in the notifier list, allocate new clk_notifier */
> +	if (cn->clk != clk) {
> +		cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
> +		if (!cn)
> +			goto out;
> +
> +		cn->clk = clk;
> +		srcu_init_notifier_head(&cn->notifier_head);
> +
> +		list_add(&cn->node, &clk_notifier_list);
> +	}
> +
> +	ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
> +
> +	clk->notifier_count++;
> +
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_notifier_register);
> +
> +/**
> + * clk_notifier_unregister - remove a clk rate change notifier
> + * @clk: struct clk *
> + * @nb: struct notifier_block * with callback info
> + *
> + * Request no further notification for changes to 'clk' and frees memory
> + * allocated in clk_notifier_register.
> + *
> + * Returns -EINVAL if called with null arguments; otherwise, passes
> + * along the return value of srcu_notifier_chain_unregister().
> + */
> +int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
> +{
> +	struct clk_notifier *cn = NULL;
> +	int ret = -EINVAL;
> +
> +	if (!clk || !nb)
> +		return -EINVAL;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	list_for_each_entry(cn, &clk_notifier_list, node)
> +		if (cn->clk == clk)
> +			break;
> +
> +	if (cn->clk == clk) {
> +		ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
> +
> +		clk->notifier_count--;
> +
> +		/* XXX the notifier code should handle this better */
> +		if (!cn->notifier_head.head) {
> +			srcu_cleanup_notifier_head(&cn->notifier_head);
> +			kfree(cn);
> +		}
> +
> +	} else {
> +		ret = -ENOENT;
> +	}
> +
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_notifier_unregister);
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> new file mode 100644
> index 0000000..33bf6a7
> --- /dev/null
> +++ b/include/linux/clk-private.h
> @@ -0,0 +1,68 @@
> +/*
> + *  linux/include/linux/clk-private.h
> + *
> + *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr at canonical.com>
> + *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef __LINUX_CLK_PRIVATE_H
> +#define __LINUX_CLK_PRIVATE_H
> +
> +#include <linux/clk-provider.h>
> +#include <linux/list.h>
> +
> +/*
> + * WARNING: Do not include clk-private.h from any file that implements struct
> + * clk_ops.  Doing so is a layering violation!
> + *
> + * This header exists only to allow for statically initialized clock data.  Any
> + * static clock data must be defined in a separate file from the logic that
> + * implements the clock operations for that same data.
> + */
> +
> +#ifdef CONFIG_COMMON_CLK
> +
> +struct clk {
> +	const char		*name;
> +	const struct clk_ops	*ops;
> +	struct clk_hw		*hw;
> +	struct clk		*parent;
> +	char			**parent_names;
> +	struct clk		**parents;
> +	u8			num_parents;
> +	unsigned long		rate;
> +	unsigned long		flags;
> +	unsigned int		enable_count;
> +	unsigned int		prepare_count;
> +	struct hlist_head	children;
> +	struct hlist_node	child_node;
> +	unsigned int		notifier_count;
> +#ifdef CONFIG_COMMON_CLK_DEBUG
> +	struct dentry		*dentry;
> +#endif
> +};
> +
> +/**
> + * __clk_init - initialize the data structures in a struct clk
> + * @dev:	device initializing this clk, placeholder for now
> + * @clk:	clk being initialized
> + *
> + * Initializes the lists in struct clk, queries the hardware for the
> + * parent and rate and sets them both.
> + *
> + * Any struct clk passed into __clk_init must have the following members
> + * populated:
> + * 	.name
> + * 	.ops
> + * 	.hw
> + * 	.parent_names
> + * 	.num_parents
> + * 	.flags
> + */
> +void __clk_init(struct device *dev, struct clk *clk);
> +
> +#endif /* CONFIG_COMMON_CLK */
> +#endif /* CLK_PRIVATE_H */
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> new file mode 100644
> index 0000000..09dea1f
> --- /dev/null
> +++ b/include/linux/clk-provider.h
> @@ -0,0 +1,171 @@
> +/*
> + *  linux/include/linux/clk-provider.h
> + *
> + *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr at canonical.com>
> + *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef __LINUX_CLK_PROVIDER_H
> +#define __LINUX_CLK_PROVIDER_H
> +
> +#include <linux/clk.h>
> +
> +#ifdef CONFIG_COMMON_CLK
> +
> +/**
> + * struct clk_hw - handle for traversing from a struct clk to its corresponding
> + * hardware-specific structure.  struct clk_hw should be declared within struct
> + * clk_foo and then referenced by the struct clk instance that uses struct
> + * clk_foo's clk_ops
> + *
> + * clk: pointer to the struct clk instance that points back to this struct
> + * clk_hw instance
> + */
> +struct clk_hw {
> +	struct clk *clk;
> +};
> +
> +/*
> + * flags used across common struct clk.  these flags should only affect the
> + * top-level framework.  custom flags for dealing with hardware specifics
> + * belong in struct clk_foo
> + */
> +#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
> +#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
> +#define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
> +#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
> +#define CLK_IS_ROOT		BIT(4) /* root clk, has no parent */
> +
> +/**
> + * struct clk_ops -  Callback operations for hardware clocks; these are to
> + * be provided by the clock implementation, and will be called by drivers
> + * through the clk_* api.
> + *
> + * @prepare:	Prepare the clock for enabling. This must not return until
> + * 		the clock is fully prepared, and it's safe to call clk_enable.
> + * 		This callback is intended to allow clock implementations to
> + * 		do any initialisation that may sleep. Called with
> + * 		prepare_lock held.
> + *
> + * @unprepare:	Release the clock from its prepared state. This will typically
> + * 		undo any work done in the @prepare callback. Called with
> + * 		prepare_lock held.
> + *
> + * @enable:	Enable the clock atomically. This must not return until the
> + * 		clock is generating a valid clock signal, usable by consumer
> + * 		devices. Called with enable_lock held. This function must not
> + * 		sleep.
> + *
> + * @disable:	Disable the clock atomically. Called with enable_lock held.
> + * 		This function must not sleep.
> + *
> + * @recalc_rate	Recalculate the rate of this clock, by quering hardware.  The
> + * 		parent rate is an input parameter.  It is up to the caller to
> + * 		insure that the prepare_mutex is held across this call.
> + * 		Returns the calculated rate.  Optional, but recommended - if
> + * 		this op is not set then clock rate will be initialized to 0.
> + *
> + * @round_rate:	Given a target rate as input, returns the closest rate actually
> + * 		supported by the clock.
> + *
> + * @get_parent:	Queries the hardware to determine the parent of a clock.  The
> + * 		return value is a u8 which specifies the index corresponding to
> + * 		the parent clock.  This index can be applied to either the
> + * 		.parent_names or .parents arrays.  In short, this function
> + * 		translates the parent value read from hardware into an array
> + * 		index.  Currently only called when the clock is initialized by
> + * 		__clk_init.  This callback is mandatory for clocks with
> + * 		multiple parents.  It is optional (and unnecessary) for clocks
> + * 		with 0 or 1 parents.
> + *
> + * @set_parent:	Change the input source of this clock; for clocks with multiple
> + * 		possible parents specify a new parent by passing in the index
> + * 		as a u8 corresponding to the parent in either the .parent_names
> + * 		or .parents arrays.  This function in affect translates an
> + * 		array index into the value programmed into the hardware.
> + * 		Returns 0 on success, -EERROR otherwise.
> + *
> + * @set_rate:	Change the rate of this clock. If this callback returns
> + * 		CLK_SET_RATE_PARENT, the rate change will be propagated to the
> + * 		parent clock (which may propagate again if the parent clock
> + * 		also sets this flag). The requested rate of the parent is
> + * 		passed back from the callback in the second 'unsigned long *'
> + * 		argument.  Note that it is up to the hardware clock's set_rate
> + * 		implementation to insure that clocks do not run out of spec
> + * 		when propgating the call to set_rate up to the parent.  One way
> + * 		to do this is to gate the clock (via clk_disable and/or
> + * 		clk_unprepare) before calling clk_set_rate, then ungating it
> + * 		afterward.  If your clock also has the CLK_GATE_SET_RATE flag
> + * 		set then this will insure safety.  Returns 0 on success,
> + * 		-EERROR otherwise.
> + *
> + * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
> + * implementations to split any work between atomic (enable) and sleepable
> + * (prepare) contexts.  If enabling a clock requires code that might sleep,
> + * this must be done in clk_prepare.  Clock enable code that will never be
> + * called in a sleepable context may be implement in clk_enable.
> + *
> + * Typically, drivers will call clk_prepare when a clock may be needed later
> + * (eg. when a device is opened), and clk_enable when the clock is actually
> + * required (eg. from an interrupt). Note that clk_prepare MUST have been
> + * called before clk_enable.
> + */
> +struct clk_ops {
> +	int		(*prepare)(struct clk_hw *hw);
> +	void		(*unprepare)(struct clk_hw *hw);
> +	int		(*enable)(struct clk_hw *hw);
> +	void		(*disable)(struct clk_hw *hw);
> +	int		(*is_enabled)(struct clk_hw *hw);
> +	unsigned long	(*recalc_rate)(struct clk_hw *hw,
> +					unsigned long parent_rate);
> +	long		(*round_rate)(struct clk_hw *hw, unsigned long,
> +					unsigned long *);
> +	int		(*set_parent)(struct clk_hw *hw, u8 index);
> +	u8		(*get_parent)(struct clk_hw *hw);
> +	int		(*set_rate)(struct clk_hw *hw, unsigned long);
> +	void		(*init)(struct clk_hw *hw);
> +};
> +
> +
> +/**
> + * clk_register - allocate a new clock, register it and return an opaque cookie
> + * @dev: device that is registering this clock
> + * @name: clock name
> + * @ops: operations this clock supports
> + * @hw: link to hardware-specific clock data
> + * @parent_names: array of string names for all possible parents
> + * @num_parents: number of possible parents
> + * @flags: framework-level hints and quirks
> + *
> + * clk_register is the primary interface for populating the clock tree with new
> + * clock nodes.  It returns a pointer to the newly allocated struct clk which
> + * cannot be dereferenced by driver code but may be used in conjuction with the
> + * rest of the clock API.
> + */
> +struct clk *clk_register(struct device *dev, const char *name,
> +		const struct clk_ops *ops, struct clk_hw *hw,
> +		char **parent_names, u8 num_parents, unsigned long flags);
> +
> +/* helper functions */
> +const char *__clk_get_name(struct clk *clk);
> +struct clk_hw *__clk_get_hw(struct clk *clk);
> +u8 __clk_get_num_parents(struct clk *clk);
> +struct clk *__clk_get_parent(struct clk *clk);
> +unsigned long __clk_get_rate(struct clk *clk);
> +unsigned long __clk_get_flags(struct clk *clk);
> +int __clk_is_enabled(struct clk *clk);
> +struct clk *__clk_lookup(const char *name);
> +
> +/*
> + * FIXME clock api without lock protection
> + */
> +int __clk_prepare(struct clk *clk);
> +void __clk_unprepare(struct clk *clk);
> +void __clk_reparent(struct clk *clk, struct clk *new_parent);
> +unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
> +
> +#endif /* CONFIG_COMMON_CLK */
> +#endif /* CLK_PROVIDER_H */
> diff --git a/include/linux/clk.h b/include/linux/clk.h
> index b9d46fa..b025272 100644
> --- a/include/linux/clk.h
> +++ b/include/linux/clk.h
> @@ -3,6 +3,7 @@
>   *
>   *  Copyright (C) 2004 ARM Limited.
>   *  Written by Deep Blue Solutions Limited.
> + *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
> @@ -12,18 +13,75 @@
>  #define __LINUX_CLK_H
>  
>  #include <linux/kernel.h>
> +#include <linux/notifier.h>
>  
>  struct device;
>  
> -/*
> - * The base API.
> +struct clk;
> +
> +#ifdef CONFIG_COMMON_CLK
> +
> +/**
> + * DOC: clk notifier callback types
> + *
> + * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
> + *     to indicate that the rate change will proceed.  Drivers must
> + *     immediately terminate any operations that will be affected by the
> + *     rate change.  Callbacks may either return NOTIFY_DONE or
> + *     NOTIFY_STOP.
> + *
> + * ABORT_RATE_CHANGE: called if the rate change failed for some reason
> + *     after PRE_RATE_CHANGE.  In this case, all registered notifiers on
> + *     the clk will be called with ABORT_RATE_CHANGE. Callbacks must
> + *     always return NOTIFY_DONE.
> + *
> + * POST_RATE_CHANGE - called after the clk rate change has successfully
> + *     completed.  Callbacks must always return NOTIFY_DONE.
> + *
>   */
> +#define PRE_RATE_CHANGE			BIT(0)
> +#define POST_RATE_CHANGE		BIT(1)
> +#define ABORT_RATE_CHANGE		BIT(2)
>  
> +/**
> + * struct clk_notifier - associate a clk with a notifier
> + * @clk: struct clk * to associate the notifier with
> + * @notifier_head: a blocking_notifier_head for this clk
> + * @node: linked list pointers
> + *
> + * A list of struct clk_notifier is maintained by the notifier code.
> + * An entry is created whenever code registers the first notifier on a
> + * particular @clk.  Future notifiers on that @clk are added to the
> + * @notifier_head.
> + */
> +struct clk_notifier {
> +	struct clk			*clk;
> +	struct srcu_notifier_head	notifier_head;
> +	struct list_head		node;
> +};
>  
> -/*
> - * struct clk - an machine class defined object / cookie.
> +/**
> + * struct clk_notifier_data - rate data to pass to the notifier callback
> + * @clk: struct clk * being changed
> + * @old_rate: previous rate of this clk
> + * @new_rate: new rate of this clk
> + *
> + * For a pre-notifier, old_rate is the clk's rate before this rate
> + * change, and new_rate is what the rate will be in the future.  For a
> + * post-notifier, old_rate and new_rate are both set to the clk's
> + * current rate (this was done to optimize the implementation).
>   */
> -struct clk;
> +struct clk_notifier_data {
> +	struct clk		*clk;
> +	unsigned long		old_rate;
> +	unsigned long		new_rate;
> +};
> +
> +int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
> +
> +int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
> +
> +#endif /* !CONFIG_COMMON_CLK */
>  
>  /**
>   * clk_get - lookup and obtain a reference to a clock producer.



From marek.vasut at gmail.com  Mon Mar 12 13:40:49 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 12 Mar 2012 18:40:49 +0100
Subject: [PATCH 1/2] ARM: Add Kconfig option to use mkimage -T
 kernel_noload
In-Reply-To: <20120229185013.GJ3318@game.jcrosoft.org>
References: <1330473804-23348-1-git-send-email-swarren@nvidia.com>
 <4F4E6F96.8080907@am.sony.com> <20120229185013.GJ3318@game.jcrosoft.org>
Message-ID: <201203121840.49776.marek.vasut@gmail.com>

Dear Jean-Christophe PLAGNIOL-VILLARD,

> On 10:33 Wed 29 Feb     , Tim Bird wrote:
> > On 02/29/2012 10:14 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 08:58 Wed 29 Feb     , Stephen Warren wrote:
> > >> Jean-Christophe PLAGNIOL-VILLARD wrote at Wednesday, February 29, 2012 
5:30 AM:
> > >>> On 17:03 Tue 28 Feb     , Stephen Warren wrote:
> > >>>> uImage files typically encode a single absolute load and entry
> > >>>> address. This is inconvenient when attempting to share that uImage
> > >>>> across multiple SoCs with different physical RAM addresses. Recent
> > >>>> versions of mkimage implement a "kernel_noload" image type which
> > >>>> encodes no absolute load address, and a relative entry address.
> > >>>> This works well for uImage-wrapped ARM zImages, since they are
> > >>>> relocatable.
> > >>>> 
> > >>>> This is enabled by commit b9b50e89d317c58becd0e2d7fac2e21e3a81dd0a
> > >>>> "image: Implement IH_TYPE_KERNEL_NOLOAD" in U-Boot.
> > >>>> 
> > >>>> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> > >>>> ---
> > >>>> I assume I should put this into the ARM patch tracker if it's OK?
> > >>> 
> > >>> Again a new option for uImage no why not just boot the zImage
> > >>> 
> > >>> in this case the uImage is useless
> > >> 
> > >> U-Boot doesn't support zImage at present.
> > >> 
> > >> A patch was posted to support it at least for ARM, but needed a little
> > >> work before it could be committed.
> > > 
> > > Sorry I see no advantage to have the uImage build by the kernel anymore
> > > as we have a relocatable zImage
> > > 
> > > I'll even drop its support
> > 
> > This seems at least premature, and possibly ill-advised in general.
> > There are lots of U-Boot images out in the field, many of which that
> > are rarely updated. A lot of workflow will be disrupted unnecessarily
> > by a change like this.
> > 
> > Could you wait to drop uImage build support in the kernel until
> > U-Boot supports zImage, and has worked it's way into the field
> > for a few years?
> 
> I'm fine to keep for now on but not to add new feature
> 
> Barebox (former U-Boot v2) support zImage for quite a while and
> relocable one for too.

On the other hand, noone uses barebox and you should stop with this obvious 
malice towards uboot please. I believe for most people it's easier to spend time 
only on implementing their hardware support into U-Boot, not waste time 
implementing basic components that are still missing in barebox.

Last but not least, the uImage contains additional checksum on the whole image, 
which is useful on flash media.

That said, I'm all for having uImage support in kernel and for adding this 
NOLOAD option.

Best regards,
Marek Vasut


From robherring2 at gmail.com  Mon Mar 12 16:18:20 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 12 Mar 2012 15:18:20 -0500
Subject: [PATCH v6 3/3] clk: basic clock hardware types
In-Reply-To: <1331366064-1273-4-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-4-git-send-email-mturquette@linaro.org>
Message-ID: <4F5E5A0C.6080604@gmail.com>

On 03/10/2012 01:54 AM, Mike Turquette wrote:
> Many platforms support simple gateable clocks, fixed-rate clocks,
> adjustable divider clocks and multi-parent multiplexer clocks.
> 
> This patch introduces basic clock types for the above-mentioned hardware
> which share some common characteristics.
> 
> Based on original work by Jeremy Kerr and contribution by Jamie Iles.
> Dividers and multiplexor clocks originally contributed by Richard Zhao &
> Sascha Hauer.
> 
> Signed-off-by: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Mike Turquette <mturquette at ti.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Shawn Guo <shawn.guo at freescale.com>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Jamie Iles <jamie at jamieiles.com>
> Cc: Richard Zhao <richard.zhao at linaro.org>
> Cc: Saravana Kannan <skannan at codeaurora.org>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Stephen Boyd <sboyd at codeaurora.org>
> Cc: Amit Kucheria <amit.kucheria at linaro.org>
> Cc: Deepak Saxena <dsaxena at linaro.org>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Andrew Lunn <andrew at lunn.ch>

One issue with spinlocks below, but otherwise:

Reviewed-by: Rob Herring <rob.herring at calxeda.com>

> ---
> Changes since v5:
>  * standardized the hw-specific locking in the basic clock types
>  * export the individual ops for each basic clock type
>  * improve registration for single-parent basic clocks (thanks Sascha)
>  * fixed bugs in gate clock's static initializers (thanks Andrew)
> 
>  drivers/clk/Makefile         |    3 +-
>  drivers/clk/clk-divider.c    |  204 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/clk-fixed-rate.c |   82 +++++++++++++++++
>  drivers/clk/clk-gate.c       |  157 ++++++++++++++++++++++++++++++++
>  drivers/clk/clk-mux.c        |  123 +++++++++++++++++++++++++
>  include/linux/clk-private.h  |  124 +++++++++++++++++++++++++
>  include/linux/clk-provider.h |  127 ++++++++++++++++++++++++++
>  7 files changed, 819 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/clk/clk-divider.c
>  create mode 100644 drivers/clk/clk-fixed-rate.c
>  create mode 100644 drivers/clk/clk-gate.c
>  create mode 100644 drivers/clk/clk-mux.c
> 
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index ff362c4..1f736bc 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -1,3 +1,4 @@
>  
>  obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
> -obj-$(CONFIG_COMMON_CLK)	+= clk.o
> +obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
> +				   clk-mux.o clk-divider.o
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> new file mode 100644
> index 0000000..c0c4e0b
> --- /dev/null
> +++ b/drivers/clk/clk-divider.c
> @@ -0,0 +1,204 @@
> +/*
> + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
> + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Adjustable divider clock implementation
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +
> +/*
> + * DOC: basic adjustable divider clock that cannot gate
> + *
> + * Traits of this clock:
> + * prepare - clk_prepare only ensures that parents are prepared
> + * enable - clk_enable only ensures that parents are enabled
> + * rate - rate is adjustable.  clk->rate = parent->rate / divisor
> + * parent - fixed parent.  No clk_set_parent support
> + */
> +
> +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
> +
> +static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> +		unsigned long parent_rate)
> +{
> +	struct clk_divider *divider = to_clk_divider(hw);
> +	unsigned int div;
> +	unsigned long flags = 0;
> +
> +	if (divider->lock)
> +		spin_lock_irqsave(divider->lock, flags);
> +
> +	div = readl(divider->reg) >> divider->shift;
> +	div &= (1 << divider->width) - 1;
> +
> +	if (divider->lock)
> +		spin_unlock_irqrestore(divider->lock, flags);

What are you locking against? You are only reading the register.

> +
> +	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
> +		div++;
> +
> +	return parent_rate / div;
> +}
> +EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
> +
> +static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
> +		unsigned long *best_parent_rate)
> +{
> +	struct clk_divider *divider = to_clk_divider(hw);
> +	int i, bestdiv = 0;
> +	unsigned long parent_rate, best = 0, now, maxdiv;
> +
> +	maxdiv = (1 << divider->width);
> +
> +	if (divider->flags & CLK_DIVIDER_ONE_BASED)
> +		maxdiv--;
> +
> +	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
> +		parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
> +		bestdiv = parent_rate / rate;
> +		bestdiv = bestdiv == 0 ? 1 : bestdiv;
> +		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
> +		goto out;
> +	}
> +
> +	/*
> +	 * The maximum divider we can use without overflowing
> +	 * unsigned long in rate * i below
> +	 */
> +	maxdiv = min(ULONG_MAX / rate, maxdiv);
> +
> +	for (i = 1; i <= maxdiv; i++) {
> +		int div;
> +		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
> +				rate * i);
> +		div = parent_rate / rate;
> +		div = div > maxdiv ? maxdiv : div;
> +		div = div < 1 ? 1 : div;
> +		now = parent_rate / div;
> +
> +		if (now <= rate && now >= best) {
> +			bestdiv = div;
> +			best = now;
> +			*best_parent_rate = parent_rate;
> +		}
> +	}
> +
> +	if (!bestdiv) {
> +		bestdiv = (1 << divider->width);
> +		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
> +	} else {
> +		parent_rate = best * bestdiv;
> +	}
> +
> +out:
> +	if (best_parent_rate)
> +		*best_parent_rate = parent_rate;
> +
> +	return bestdiv;
> +}
> +
> +static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
> +				unsigned long *prate)
> +{
> +	unsigned long best_parent_rate;
> +	int div = clk_divider_bestdiv(hw, rate, &best_parent_rate);
> +	if (prate) {
> +		if (best_parent_rate == __clk_get_rate(
> +					__clk_get_parent(hw->clk)))
> +			*prate = 0;
> +		else
> +			*prate = best_parent_rate;
> +	}
> +
> +	return best_parent_rate / div;
> +}
> +EXPORT_SYMBOL_GPL(clk_divider_round_rate);
> +
> +static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
> +{
> +	unsigned long best_parent_rate;
> +	struct clk_divider *divider = to_clk_divider(hw);
> +	unsigned int div;
> +	unsigned long flags = 0;
> +	u32 val;
> +
> +	div = clk_divider_bestdiv(hw, rate, &best_parent_rate);
> +
> +	if (divider->lock)
> +		spin_lock_irqsave(divider->lock, flags);
> +
> +	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
> +		div--;
> +
> +	val = readl(divider->reg);
> +	val &= ~(((1 << divider->width) - 1) << divider->shift);
> +	val |= div << divider->shift;
> +	writel(val, divider->reg);
> +
> +	if (divider->lock)
> +		spin_unlock_irqrestore(divider->lock, flags);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(clk_divider_set_rate);
> +
> +struct clk_ops clk_divider_ops = {
> +	.recalc_rate = clk_divider_recalc_rate,
> +	.round_rate = clk_divider_round_rate,
> +	.set_rate = clk_divider_set_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_divider_ops);
> +
> +struct clk *clk_register_divider(struct device *dev, const char *name,
> +		const char *parent_name, unsigned long flags,
> +		void __iomem *reg, u8 shift, u8 width,
> +		u8 clk_divider_flags, spinlock_t *lock)
> +{
> +	struct clk_divider *div;
> +	struct clk *clk;
> +
> +	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
> +
> +	if (!div) {
> +		pr_err("%s: could not allocate divider clk\n", __func__);
> +		return NULL;
> +	}
> +
> +	/* struct clk_divider assignments */
> +	div->reg = reg;
> +	div->shift = shift;
> +	div->width = width;
> +	div->flags = clk_divider_flags;
> +	div->lock = lock;
> +
> +	if (parent_name) {
> +		div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
> +		if (!div->parent[0])
> +			goto out;
> +	}
> +
> +	clk = clk_register(dev, name,
> +			&clk_divider_ops, &div->hw,
> +			div->parent,
> +			(parent_name ? 1 : 0),
> +			flags);
> +	if (clk)
> +		return clk;
> +
> +out:
> +	kfree(div->parent[0]);
> +	kfree(div);
> +
> +	return NULL;
> +}
> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
> new file mode 100644
> index 0000000..90c79fb
> --- /dev/null
> +++ b/drivers/clk/clk-fixed-rate.c
> @@ -0,0 +1,82 @@
> +/*
> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Fixed rate clock implementation
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +
> +/*
> + * DOC: basic fixed-rate clock that cannot gate
> + *
> + * Traits of this clock:
> + * prepare - clk_(un)prepare only ensures parents are prepared
> + * enable - clk_enable only ensures parents are enabled
> + * rate - rate is always a fixed value.  No clk_set_rate support
> + * parent - fixed parent.  No clk_set_parent support
> + */
> +
> +#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
> +
> +static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
> +		unsigned long parent_rate)
> +{
> +	return to_clk_fixed_rate(hw)->fixed_rate;
> +}
> +EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate);
> +
> +struct clk_ops clk_fixed_rate_ops = {
> +	.recalc_rate = clk_fixed_rate_recalc_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
> +
> +struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> +		const char *parent_name, unsigned long flags,
> +		unsigned long fixed_rate)
> +{
> +	struct clk_fixed_rate *fixed;
> +	char **parent_names = NULL;
> +	u8 len;
> +
> +	fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
> +
> +	if (!fixed) {
> +		pr_err("%s: could not allocate fixed clk\n", __func__);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	/* struct clk_fixed_rate assignments */
> +	fixed->fixed_rate = fixed_rate;
> +
> +	if (parent_name) {
> +		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
> +
> +		if (! parent_names)
> +			goto out;
> +
> +		len = sizeof(char) * strlen(parent_name);
> +
> +		parent_names[0] = kmalloc(len, GFP_KERNEL);
> +
> +		if (!parent_names[0])
> +			goto out;
> +
> +		strncpy(parent_names[0], parent_name, len);
> +	}
> +
> +out:
> +	return clk_register(dev, name,
> +			&clk_fixed_rate_ops, &fixed->hw,
> +			parent_names,
> +			(parent_name ? 1 : 0),
> +			flags);
> +}
> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> new file mode 100644
> index 0000000..5d50efa
> --- /dev/null
> +++ b/drivers/clk/clk-gate.c
> @@ -0,0 +1,157 @@
> +/*
> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Gated clock implementation
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +
> +/**
> + * DOC: basic gatable clock which can gate and ungate it's ouput
> + *
> + * Traits of this clock:
> + * prepare - clk_(un)prepare only ensures parent is (un)prepared
> + * enable - clk_enable and clk_disable are functional & control gating
> + * rate - inherits rate from parent.  No clk_set_rate support
> + * parent - fixed parent.  No clk_set_parent support
> + */
> +
> +#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
> +
> +static void clk_gate_set_bit(struct clk_gate *gate)
> +{
> +	u32 reg;
> +	unsigned long flags = 0;
> +
> +	if (gate->lock)
> +		spin_lock_irqsave(gate->lock, flags);
> +
> +	reg = readl(gate->reg);
> +	reg |= BIT(gate->bit_idx);
> +	writel(reg, gate->reg);
> +
> +	if (gate->lock)
> +		spin_unlock_irqrestore(gate->lock, flags);
> +}
> +
> +static void clk_gate_clear_bit(struct clk_gate *gate)
> +{
> +	u32 reg;
> +	unsigned long flags = 0;
> +
> +	if (gate->lock)
> +		spin_lock_irqsave(gate->lock, flags);
> +
> +	reg = readl(gate->reg);
> +	reg &= ~BIT(gate->bit_idx);
> +	writel(reg, gate->reg);
> +
> +	if (gate->lock)
> +		spin_unlock_irqrestore(gate->lock, flags);
> +}
> +
> +static int clk_gate_enable(struct clk_hw *hw)
> +{
> +	struct clk_gate *gate = to_clk_gate(hw);
> +
> +	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> +		clk_gate_clear_bit(gate);
> +	else
> +		clk_gate_set_bit(gate);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(clk_gate_enable);
> +
> +static void clk_gate_disable(struct clk_hw *hw)
> +{
> +	struct clk_gate *gate = to_clk_gate(hw);
> +
> +	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> +		clk_gate_set_bit(gate);
> +	else
> +		clk_gate_clear_bit(gate);
> +}
> +EXPORT_SYMBOL_GPL(clk_gate_disable);
> +
> +static int clk_gate_is_enabled(struct clk_hw *hw)
> +{
> +	u32 reg;
> +	unsigned long flags = 0;
> +	struct clk_gate *gate = to_clk_gate(hw);
> +
> +	if (gate->lock)
> +		spin_lock_irqsave(gate->lock, flags);
> +
> +	reg = readl(gate->reg);
> +
> +	if (gate->lock)
> +		spin_unlock_irqrestore(gate->lock, flags);
> +

ditto.

> +	/* if a set bit disables this clk, flip it before masking */
> +	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> +		reg ^= BIT(gate->bit_idx);
> +
> +	reg &= BIT(gate->bit_idx);
> +
> +	return reg ? 1 : 0;
> +}
> +EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
> +
> +struct clk_ops clk_gate_ops = {
> +	.enable = clk_gate_enable,
> +	.disable = clk_gate_disable,
> +	.is_enabled = clk_gate_is_enabled,
> +};
> +EXPORT_SYMBOL_GPL(clk_gate_ops);
> +
> +struct clk *clk_register_gate(struct device *dev, const char *name,
> +		const char *parent_name, unsigned long flags,
> +		void __iomem *reg, u8 bit_idx,
> +		u8 clk_gate_flags, spinlock_t *lock)
> +{
> +	struct clk_gate *gate;
> +	struct clk *clk;
> +
> +	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
> +
> +	if (!gate) {
> +		pr_err("%s: could not allocate gated clk\n", __func__);
> +		return NULL;
> +	}
> +
> +	/* struct clk_gate assignments */
> +	gate->reg = reg;
> +	gate->bit_idx = bit_idx;
> +	gate->flags = clk_gate_flags;
> +	gate->lock = lock;
> +
> +	if (parent_name) {
> +		gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
> +		if (!gate->parent[0])
> +			goto out;
> +	}
> +
> +	clk = clk_register(dev, name,
> +			&clk_gate_ops, &gate->hw,
> +			gate->parent,
> +			(parent_name ? 1 : 0),
> +			flags);
> +	if (clk)
> +		return clk;
> +out:
> +	kfree(gate->parent[0]);
> +	kfree(gate);
> +
> +	return NULL;
> +}
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> new file mode 100644
> index 0000000..6fc0878
> --- /dev/null
> +++ b/drivers/clk/clk-mux.c
> @@ -0,0 +1,123 @@
> +/*
> + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
> + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Simple multiplexer clock implementation
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +
> +/*
> + * DOC: basic adjustable multiplexer clock that cannot gate
> + *
> + * Traits of this clock:
> + * prepare - clk_prepare only ensures that parents are prepared
> + * enable - clk_enable only ensures that parents are enabled
> + * rate - rate is only affected by parent switching.  No clk_set_rate support
> + * parent - parent is adjustable through clk_set_parent
> + */
> +
> +#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
> +
> +static u8 clk_mux_get_parent(struct clk_hw *hw)
> +{
> +	struct clk_mux *mux = to_clk_mux(hw);
> +	u32 val;
> +	unsigned long flags = 0;
> +
> +	if (mux->lock)
> +		spin_lock_irqsave(mux->lock, flags);
> +
> +	/*
> +	 * FIXME need a mux-specific flag to determine if val is bitwise or numeric
> +	 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
> +	 * to 0x7 (index starts at one)
> +	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
> +	 * val = 0x4 really means "bit 2, index starts at bit 0"
> +	 */
> +	val = readl(mux->reg) >> mux->shift;
> +	val &= (1 << mux->width) - 1;
> +
> +	if (mux->lock)
> +		spin_unlock_irqrestore(mux->lock, flags);

ditto

> +
> +	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
> +		val = ffs(val) - 1;
> +
> +	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
> +		val--;
> +
> +	if (val >= __clk_get_num_parents(hw->clk))
> +		return -EINVAL;
> +
> +	return val;
> +}
> +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
> +
> +static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct clk_mux *mux = to_clk_mux(hw);
> +	u32 val;
> +	unsigned long flags = 0;
> +
> +	if (mux->flags & CLK_MUX_INDEX_BIT)
> +		index = (1 << ffs(index));
> +
> +	if (mux->flags & CLK_MUX_INDEX_ONE)
> +		index++;
> +
> +	if (mux->lock)
> +		spin_lock_irqsave(mux->lock, flags);
> +
> +	val = readl(mux->reg);
> +	val &= ~(((1 << mux->width) - 1) << mux->shift);
> +	val |= index << mux->shift;
> +	writel(val, mux->reg);
> +
> +	if (mux->lock)
> +		spin_unlock_irqrestore(mux->lock, flags);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(clk_mux_set_parent);
> +
> +struct clk_ops clk_mux_ops = {
> +	.get_parent = clk_mux_get_parent,
> +	.set_parent = clk_mux_set_parent,
> +};
> +EXPORT_SYMBOL_GPL(clk_mux_ops);
> +
> +struct clk *clk_register_mux(struct device *dev, const char *name,
> +		char **parent_names, u8 num_parents, unsigned long flags,
> +		void __iomem *reg, u8 shift, u8 width,
> +		u8 clk_mux_flags, spinlock_t *lock)
> +{
> +	struct clk_mux *mux;
> +
> +	mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL);
> +
> +	if (!mux) {
> +		pr_err("%s: could not allocate mux clk\n", __func__);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	/* struct clk_mux assignments */
> +	mux->reg = reg;
> +	mux->shift = shift;
> +	mux->width = width;
> +	mux->flags = clk_mux_flags;
> +	mux->lock = lock;
> +
> +	return clk_register(dev, name, &clk_mux_ops, &mux->hw,
> +			parent_names, num_parents, flags);
> +}
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> index 33bf6a7..9d5c4b1 100644
> --- a/include/linux/clk-private.h
> +++ b/include/linux/clk-private.h
> @@ -45,6 +45,130 @@ struct clk {
>  #endif
>  };
>  
> +/*
> + * DOC: Basic clock implementations common to many platforms
> + *
> + * Each basic clock hardware type is comprised of a structure describing the
> + * clock hardware, implementations of the relevant callbacks in struct clk_ops,
> + * unique flags for that hardware type, a registration function and an
> + * alternative macro for static initialization
> + */
> +
> +extern struct clk_ops clk_fixed_rate_ops;
> +
> +#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate,		\
> +				_fixed_rate_flags)		\
> +	static struct clk _name;				\
> +	static char *_name##_parent_names[] = {};		\
> +	static struct clk_fixed_rate _name##_hw = {		\
> +		.hw = {						\
> +			.clk = &_name,				\
> +		},						\
> +		.fixed_rate = _rate,				\
> +		.flags = _fixed_rate_flags,			\
> +	};							\
> +	static struct clk _name = {				\
> +		.name = #_name,					\
> +		.ops = &clk_fixed_rate_ops,			\
> +		.hw = &_name##_hw.hw,				\
> +		.parent_names = _name##_parent_names,		\
> +		.num_parents =					\
> +			ARRAY_SIZE(_name##_parent_names),	\
> +		.flags = _flags,				\
> +	};
> +
> +extern struct clk_ops clk_gate_ops;
> +
> +#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,	\
> +				_flags, _reg, _bit_idx,		\
> +				_gate_flags, _lock)		\
> +	static struct clk _name;				\
> +	static char *_name##_parent_names[] = {			\
> +		_parent_name,					\
> +	};							\
> +	static struct clk *_name##_parents[] = {		\
> +		_parent_ptr,					\
> +	};							\
> +	static struct clk_gate _name##_hw = {			\
> +		.hw = {						\
> +			.clk = &_name,				\
> +		},						\
> +		.reg = _reg,					\
> +		.bit_idx = _bit_idx,				\
> +		.flags = _gate_flags,				\
> +		.lock = _lock,					\
> +	};							\
> +	static struct clk _name = {				\
> +		.name = #_name,					\
> +		.ops = &clk_gate_ops,				\
> +		.hw = &_name##_hw.hw,				\
> +		.parent_names = _name##_parent_names,		\
> +		.num_parents =					\
> +			ARRAY_SIZE(_name##_parent_names),	\
> +		.parents = _name##_parents,			\
> +		.flags = _flags,				\
> +	};
> +
> +extern struct clk_ops clk_divider_ops;
> +
> +#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
> +				_flags, _reg, _shift, _width,	\
> +				_divider_flags, _lock)		\
> +	static struct clk _name;				\
> +	static char *_name##_parent_names[] = {			\
> +		_parent_name,					\
> +	};							\
> +	static struct clk *_name##_parents[] = {		\
> +		_parent_ptr,					\
> +	};							\
> +	static struct clk_divider _name##_hw = {		\
> +		.hw = {						\
> +			.clk = &_name,				\
> +		},						\
> +		.reg = _reg,					\
> +		.shift = _shift,				\
> +		.width = _width,				\
> +		.flags = _divider_flags,			\
> +		.lock = _lock,					\
> +	};							\
> +	static struct clk _name = {				\
> +		.name = #_name,					\
> +		.ops = &clk_divider_ops,			\
> +		.hw = &_name##_hw.hw,				\
> +		.parent_names = _name##_parent_names,		\
> +		.num_parents =					\
> +			ARRAY_SIZE(_name##_parent_names),	\
> +		.parents = _name##_parents,			\
> +		.flags = _flags,				\
> +	};
> +
> +extern struct clk_ops clk_mux_ops;
> +
> +#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags,	\
> +				_reg, _shift, _width,		\
> +				_mux_flags, _lock)		\
> +	static struct clk _name;				\
> +	static struct clk_mux _name##_hw = {			\
> +		.hw = {						\
> +			.clk = &_name,				\
> +		},						\
> +		.reg = _reg,					\
> +		.shift = _shift,				\
> +		.width = _width,				\
> +		.flags = _mux_flags,				\
> +		.lock = _lock,					\
> +	};							\
> +	static struct clk _name = {				\
> +		.name = #_name,					\
> +		.ops = &clk_mux_ops,				\
> +		.hw = &_name##_hw.hw,				\
> +		.parent_names = _parent_names,			\
> +		.num_parents =					\
> +			ARRAY_SIZE(_parent_names),		\
> +		.parents = _parents,				\
> +		.flags = _flags,				\
> +	};
> +
>  /**
>   * __clk_init - initialize the data structures in a struct clk
>   * @dev:	device initializing this clk, placeholder for now
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 09dea1f..853d526 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -129,6 +129,133 @@ struct clk_ops {
>  	void		(*init)(struct clk_hw *hw);
>  };
>  
> +/*
> + * DOC: Basic clock implementations common to many platforms
> + *
> + * Each basic clock hardware type is comprised of a structure describing the
> + * clock hardware, implementations of the relevant callbacks in struct clk_ops,
> + * unique flags for that hardware type, a registration function and an
> + * alternative macro for static initialization
> + */
> +
> +/**
> + * struct clk_fixed_rate - fixed-rate clock
> + * @hw:		handle between common and hardware-specific interfaces
> + * @fixed_rate:	constant frequency of clock
> + */
> +struct clk_fixed_rate {
> +	struct		clk_hw hw;
> +	unsigned long	fixed_rate;
> +	u8		flags;
> +};
> +
> +struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> +		const char *parent_name, unsigned long flags,
> +		unsigned long fixed_rate);
> +
> +/**
> + * struct clk_gate - gating clock
> + *
> + * @hw:		handle between common and hardware-specific interfaces
> + * @reg:	register controlling gate
> + * @bit_idx:	single bit controlling gate
> + * @flags:	hardware-specific flags
> + * @lock:	register lock
> + *
> + * Clock which can gate its output.  Implements .enable & .disable
> + *
> + * Flags:
> + * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
> + * 	enable the clock.  Setting this flag does the opposite: setting the bit
> + * 	disable the clock and clearing it enables the clock
> + */
> +struct clk_gate {
> +	struct clk_hw hw;
> +	void __iomem	*reg;
> +	u8		bit_idx;
> +	u8		flags;
> +	spinlock_t	*lock;
> +	char		*parent[1];
> +};
> +
> +#define CLK_GATE_SET_TO_DISABLE		BIT(0)
> +
> +struct clk *clk_register_gate(struct device *dev, const char *name,
> +		const char *parent_name, unsigned long flags,
> +		void __iomem *reg, u8 bit_idx,
> +		u8 clk_gate_flags, spinlock_t *lock);
> +
> +/**
> + * struct clk_divider - adjustable divider clock
> + *
> + * @hw:		handle between common and hardware-specific interfaces
> + * @reg:	register containing the divider
> + * @shift:	shift to the divider bit field
> + * @width:	width of the divider bit field
> + * @lock:	register lock
> + *
> + * Clock with an adjustable divider affecting its output frequency.  Implements
> + * .recalc_rate, .set_rate and .round_rate
> + *
> + * Flags:
> + * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
> + * 	register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
> + * 	the raw value read from the register, with the value of zero considered
> + * 	invalid
> + * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
> + * 	the hardware register
> + */
> +struct clk_divider {
> +	struct clk_hw	hw;
> +	void __iomem	*reg;
> +	u8		shift;
> +	u8		width;
> +	u8		flags;
> +	spinlock_t	*lock;
> +	char		*parent[1];
> +};
> +
> +#define CLK_DIVIDER_ONE_BASED		BIT(0)
> +#define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
> +
> +struct clk *clk_register_divider(struct device *dev, const char *name,
> +		const char *parent_name, unsigned long flags,
> +		void __iomem *reg, u8 shift, u8 width,
> +		u8 clk_divider_flags, spinlock_t *lock);
> +
> +/**
> + * struct clk_mux - multiplexer clock
> + *
> + * @hw:		handle between common and hardware-specific interfaces
> + * @reg:	register controlling multiplexer
> + * @shift:	shift to multiplexer bit field
> + * @width:	width of mutliplexer bit field
> + * @num_clks:	number of parent clocks
> + * @lock:	register lock
> + *
> + * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
> + * and .recalc_rate
> + *
> + * Flags:
> + * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
> + * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two)
> + */
> +struct clk_mux {
> +	struct clk_hw	hw;
> +	void __iomem	*reg;
> +	u8		shift;
> +	u8		width;
> +	u8		flags;
> +	spinlock_t	*lock;
> +};
> +
> +#define CLK_MUX_INDEX_ONE		BIT(0)
> +#define CLK_MUX_INDEX_BIT		BIT(1)
> +
> +struct clk *clk_register_mux(struct device *dev, const char *name,
> +		char **parent_names, u8 num_parents, unsigned long flags,
> +		void __iomem *reg, u8 shift, u8 width,
> +		u8 clk_mux_flags, spinlock_t *lock);
>  
>  /**
>   * clk_register - allocate a new clock, register it and return an opaque cookie



From grant.likely at secretlab.ca  Mon Mar 12 13:34:25 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 11:34:25 -0600
Subject: [PATCH 0/6] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <CAMQu2gzdfxJms8cc3VhsVzhGq4f8x1QeY6LU6X+2eFZ4_Yv_bw@mail.gmail.com>
References: <1329999031-6914-1-git-send-email-tarun.kanti@ti.com>
 <CAMQu2gzdfxJms8cc3VhsVzhGq4f8x1QeY6LU6X+2eFZ4_Yv_bw@mail.gmail.com>
Message-ID: <20120312173425.A6B893E07B0@localhost>

On Thu, 23 Feb 2012 17:56:33 +0530, "Shilimkar, Santosh" <santosh.shilimkar at ti.com> wrote:
> On Thu, Feb 23, 2012 at 5:40 PM, Tarun Kanti DebBarma
> <tarun.kanti at ti.com> wrote:
> > The cleanup is mostly getting rid of redundant fields in struct gpio_bank{}
> > as we already have them as part of bank->context now. Also, remove un-used
> > variable from gpio_irq_handler.
> >
> > The fix include correction of _set_gpio_irqenable() implementation and fix
> > type mismatch of gpio trigger parameter.
> >
> > It is baselined on top of Kevin's following series:
> > gpio/omap: cleanup and runtime PM conversion for v3.4
> > git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/gpio/runtime-pm-cleanup
> >
> > I have applied Benoit's GPIO patches in following series on top of Kevin's
> > before applying my changes.
> > gpio/omap: Cleanup and adaptation to Device Tree
> > git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/dt_gpio
> >
> > Series is available here for reference:
> > git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_further_cleanup_fixes
> >
> > Power Test: Off-mode and Retention on OMAP3430 (Suspend and Idle paths).
> > Functional Test: OMAP2430, OMAP3430SDP, ZOOM3, OMAP4430, OMAP4-BLAZE
> >
> > Tarun Kanti DebBarma (6):
> > ??gpio/omap: remove saved_fallingdetect, saved_risingdetect fields
> > ??gpio/omap: remove saved_wakeup field from struct gpio_bank
> > ??gpio/omap: remove suspend_wakeup field from struct gpio_bank
> > ??gpio/omap: get rid of retrigger variable in gpio_irq_handler
> > ??gpio/omap: fix trigger type to unsigned
> > ??gpio/omap: fix _set_gpio_irqenable implementation
> >
> > ??drivers/gpio/gpio-omap.c | ?? 56 +++++++++++++++++++--------------------------
> > ??1 files changed, 24 insertions(+), 32 deletions(-)
> >
> Nice clean-up series. I have gone through this series one more time
> Thanks for updating change-logs. I noticed you dropped the edge triggered
> irq wakeup fix....I see on the list now.... Kevin has fixed that already.
> 
> Series looks good to me. You can add:
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>

What's the status of this series?  Should I be expecting a v2?  Or am I supposed
to pick up this one? (a pull req would make things easier for me)

g.



From marek.vasut at gmail.com  Mon Mar 12 13:42:59 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 12 Mar 2012 18:42:59 +0100
Subject: [PATCH 1/2] ARM: Add Kconfig option to use mkimage -T
 kernel_noload
In-Reply-To: <20120229205901.GR14173@pengutronix.de>
References: <4F4E6F96.8080907@am.sony.com>
 <20120229204527.GD16999@n2100.arm.linux.org.uk>
 <20120229205901.GR14173@pengutronix.de>
Message-ID: <201203121843.00025.marek.vasut@gmail.com>

Dear Uwe Kleine-K?nig,

> On Wed, Feb 29, 2012 at 08:45:27PM +0000, Russell King - ARM Linux wrote:
> > On Wed, Feb 29, 2012 at 09:39:58PM +0100, Uwe Kleine-K?nig wrote:
> > > I'd bet your platform has cache support in the decompressor without
> > > knowing which platform you use. I suggest commenting out
> > > 
> > > 	bl	cache_on
> > > 
> > > in arch/arm/boot/compressed/head.S to see the difference.
> > > 
> > > How do you build the uImage containing the zImage? If you use the
> > > 
> > > in-kernel uImage target booting that usually means:
> > > 	- move the zImage to ZRELADDR
> > > 	- jump into zImage
> > > 	- decompress zImage to somewhere else
> > > 	- move decompressed image to ZRELADDR
> > > 	- jump to ZRELADDR
> > > 
> > > That is you have two relocations because the first location for sure
> > > conflicts with the decompressed image.
> > 
> > Actually, we do this slightly differently nowadays.  Inside zImage:
> > 	- if zImage location conflicts, move the decompressed data
> 
> s/de//
> 
> > 	  and decompressor to another location
> > 	
> > 	- decompress zImage to ZRELADDR
> > 	- jump to ZRELADDR
> > 
> > That reduces the size required for copying.  Of course, that copy can
> > (as it's always been the case) be totally eliminated by ensuring that
> > you load the zImage out of the way of the decompressed image.
> > 
> > So, really, comparing a standard uImage produced by the standard kernel
> > with gzipped Image is far from a fair comparison.  And that's actually
> > another argument for getting rid of the uImage target... it may make
> > people think a bit about what they're doing rather than accepting
> > whatever default location someone else chose for their kernel.
> 
> I'm all in favour to remove the uImage target because back in 2007 we
> already had a similar discussion[1]. (Back then I still thought that
> improving the uImage support would be a good idea.)
> 
> That said I think *in general* having support for U-Boot in the kernel
> is fine because I think U-Boot is the bootloader used most. But if you
> need some Kconfig settings or more than one Makefile target I think just
> building an Image or zImage and doing the U-Boot wrapping without the
> help of Linux' build system is preferable.

I believe eventually everyone will converge to having this option enabled. 
Therefore this config option will just be always on and can be squashed away.

> 
> Best regards
> Uwe
> 
> [1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/36547/focus=36588

Best regards,
Marek Vasut


From khilman at ti.com  Mon Mar 12 13:26:53 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 12 Mar 2012 10:26:53 -0700
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators for
 v3.4
In-Reply-To: <20120311204232.GC3171@opensource.wolfsonmicro.com> (Mark Brown's
 message of "Sun, 11 Mar 2012 20:42:33 +0000")
References: <877gywjhht.fsf@ti.com> <20120308021843.GQ12083@atomide.com>
 <87399jc6cj.fsf@ti.com> <20120309003217.GB12083@atomide.com>
 <20120309114731.GA3273@opensource.wolfsonmicro.com>
 <87zkbp4wtj.fsf@ti.com>
 <20120311204232.GC3171@opensource.wolfsonmicro.com>
Message-ID: <87399dzq5e.fsf@ti.com>

Mark Brown <broonie at opensource.wolfsonmicro.com> writes:

> The branch itself is essentially stable but I'm not enthused about the
> idea of merging the whole thing via the OMAP tree.  

Right, I wasn't suggesting we merge it via OMAP tree.   I was just
looking for a stable point we could use as s dependency when merging
everything together for the arm-soc tree.

> However, as Linus has released an -rc7 I should pull some stuff out of
> there and send fixes to him so I've created a topic/twl so let's just
> rebase.

OK.

>> > In general you should warn people if you've got a dependency on their
>> > tree, it makes life easier.
>
>> Yeah, I should've raised this when the original series were posted.  The
>> arch stuff and drivers/regulator stuff were posted all together, but you
>> picked out the regulator stuff and I picked up the rest.  
>
> Actually IIRC by the time I applied this the ARM changes had been
> totally deteched from the regulator stuff - Tero was sending just the
> regulator patch by itself and I actually applied the patch it was part
> of a twl regulator series Rajendra put together after I got fed up with
> the number of people sending me incompatible changes without talking to
> each other.  I'd completely forgotten about any arch/arm stuff.
>
> This sort of issue is becoming far too common with the OMAP stuff, there
> needs to be a much greater awareness of the need to coordinate both
> between trees and with multiple people working on the same code.

Completely agree, hence this email trying to work this out before the
merge window.

Thanks for this topic branch.  We'll ask for it to be included as a
branch in arm-soc/depends/* so that OMAP voltage core changes will build
there as well as in linux-next.

Thanks,

Kevin


> The following changes since commit dcd6c92267155e70a94b3927bce681ce74b80d1f:
>
>   Linux 3.3-rc1 (2012-01-19 15:04:48 -0800)
>
> are available in the git repository at:
>
>   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git tags/topic/twl
>
> for you to fetch changes up to 46eda3e96a65b378041c79c51ff2e02009f7e2d0:
>
>   mfd: twl-core: regulator configuration for twl6030 V1V8, V2V1 SMPS (2012-03-11 20:09:26 +0000)
>
> ----------------------------------------------------------------
> TWL specific changes, cross-merged with OMAP due to arch/arm wanting to
> use the new ability to override the voltage set and get operations to
> support the in-CPU voltage management.  The other changes are minor
> fixes, the addition of a few new regulators and device tree support.
>
> ----------------------------------------------------------------
> Laxman Dewangan (1):
>       regulator: twl6030: Fix voltage selection logic
>
> Peter Ujfalusi (2):
>       regulator: twl-regulator: Add fixed LDO for V1V8, V2V1 supply
>       mfd: twl-core: regulator configuration for twl6030 V1V8, V2V1 SMPS
>
> Rajendra Nayak (1):
>       regulator: twl: adapt twl-regulator driver to dt
>
> Tero Kristo (2):
>       regulator: twl4030: add support for external voltage get/set
>       regulator: twl6030: add support for vdd1, vdd2 and vdd3 regulators
>
>  .../bindings/regulator/twl-regulator.txt           |   68 ++++
>  drivers/mfd/twl-core.c                             |   41 +++-
>  drivers/regulator/twl-regulator.c                  |  327 +++++++++++++++-----
>  include/linux/i2c/twl.h                            |   14 +-
>  4 files changed, 366 insertions(+), 84 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/regulator/twl-regulator.txt


From viresh.kumar at st.com  Mon Mar 12 00:23:18 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:53:18 +0530
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <1331500100-31351-4-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-4-git-send-email-robherring2@gmail.com>
Message-ID: <4F5D7A36.8030601@st.com>

On 3/12/2012 2:38 AM, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> Several platforms create IOMEM defines for casting to 'void __iomem *',
> and other platforms are incorrectly using __io() macro for the same
> purpose. This creates a common definition and removes all the platform
> specific versions. Rather than try to make linux/io.h and asm/io.h
> assembly safe, the assembly version of IOMEM is moved into
> asm/assembler.h.
> 
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Sekhar Nori <nsekhar at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <rmallon at gmail.com>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
> Cc: David Brown <davidb at codeaurora.org>
> Cc: Daniel Walker <dwalker at fifo99.com>
> Cc: Bryan Huntsman <bryanh at codeaurora.org>
> Cc: Sascha Hauer <kernel at pengutronix.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> Cc: Rajeev Kumar <rajeev-dlh.kumar at st.com>
> Cc: Colin Cross <ccross at android.com>
> Cc: Olof Johansson <olof at lixom.net>
> Cc: Stephen Warren <swarren at nvidia.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> ---
>  arch/arm/include/asm/assembler.h                |    2 ++
>  arch/arm/include/asm/io.h                       |    2 ++
>  arch/arm/kernel/debug.S                         |    1 +
>  arch/arm/kernel/entry-armv.S                    |    1 +
>  arch/arm/mach-davinci/include/mach/hardware.h   |    6 ------
>  arch/arm/mach-davinci/include/mach/uncompress.h |    2 ++
>  arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |    9 ---------
>  arch/arm/mach-mmp/include/mach/addr-map.h       |    6 ------
>  arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |    6 ------
>  arch/arm/mach-msm/include/mach/msm_iomap.h      |    6 ------
>  arch/arm/mach-mxs/include/mach/hardware.h       |    6 ------
>  arch/arm/mach-omap1/ams-delta-fiq-handler.S     |    1 +
>  arch/arm/mach-omap1/iomap.h                     |    6 ------
>  arch/arm/mach-omap2/clock3xxx_data.c            |    1 +
>  arch/arm/mach-omap2/clock44xx_data.c            |    1 +
>  arch/arm/mach-omap2/iomap.h                     |    6 ------
>  arch/arm/mach-rpc/include/mach/hardware.h       |    6 ------
>  arch/arm/mach-spear3xx/clock.c                  |    1 +
>  arch/arm/mach-spear6xx/clock.c                  |    1 +
>  arch/arm/mach-tegra/include/mach/iomap.h        |    6 ------
>  arch/arm/mach-u300/include/mach/u300-regs.h     |    6 ------
>  arch/arm/plat-mxc/include/mach/hardware.h       |    6 ------
>  arch/arm/plat-omap/include/plat/hardware.h      |    6 ------
>  arch/arm/plat-omap/include/plat/usb.h           |    1 -
>  arch/arm/plat-spear/include/plat/hardware.h     |    6 ------
>  25 files changed, 13 insertions(+), 88 deletions(-)
> 

[For SPEAr]
Acked-by: Viresh Kumar <viresh.kumar at st.com>

--
viresh


From viresh.kumar at st.com  Mon Mar 12 00:22:11 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:11 +0530
Subject: [PATCH V2 16/22] watchdog/mpcore_wdt: Add clock framework support
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <418b92e874f89c0163536aa4c79d0230f73b0c42.1331524811.git.viresh.kumar@st.com>

This patch adds in clk framework support for wdt driver. If clk_get fails for
some platform, then we continue without clk_* API's.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   66 ++++++++++++++++++++++++++++++++++++-----
 1 files changed, 58 insertions(+), 8 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 73d50c3..23c324c 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -17,6 +17,8 @@
  *
  * (c) Copyright 1995    Alan Cox <alan at lxorguk.ukuu.org.uk>
  */
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
@@ -36,6 +38,7 @@ struct mpcore_wdt {
 	struct device	*dev;
 	void __iomem	*base;
 	spinlock_t	lock;
+	struct clk	*clk;
 	int		irq;
 	unsigned int	perturb;
 };
@@ -106,15 +109,25 @@ static int mpcore_wdt_ping(struct watchdog_device *wdd)
 	return 0;
 }
 
-static int mpcore_wdt_stop(struct watchdog_device *wdd)
+static void __mpcore_wdt_stop(struct mpcore_wdt *wdt)
 {
-	struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd);
-
 	spin_lock(&wdt->lock);
 	writel_relaxed(0x12345678, wdt->base + TWD_WDOG_DISABLE);
 	writel_relaxed(0x87654321, wdt->base + TWD_WDOG_DISABLE);
 	writel_relaxed(0x0, wdt->base + TWD_WDOG_CONTROL);
 	spin_unlock(&wdt->lock);
+}
+
+static int mpcore_wdt_stop(struct watchdog_device *wdd)
+{
+	struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd);
+
+	__mpcore_wdt_stop(wdt);
+
+	if (!IS_ERR(wdt->clk)) {
+		clk_disable(wdt->clk);
+		clk_unprepare(wdt->clk);
+	}
 
 	return 0;
 }
@@ -122,9 +135,25 @@ static int mpcore_wdt_stop(struct watchdog_device *wdd)
 static int mpcore_wdt_start(struct watchdog_device *wdd)
 {
 	struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd);
+	int ret;
 
 	dev_info(wdt->dev, "enabling watchdog.\n");
 
+	if (!IS_ERR(wdt->clk)) {
+		ret = clk_prepare(wdt->clk);
+		if (ret) {
+			dev_err(wdt->dev, "clock prepare fail");
+			return ret;
+		}
+
+		ret = clk_enable(wdt->clk);
+		if (ret) {
+			dev_err(wdt->dev, "Clock enable failed\n");
+			clk_unprepare(wdt->clk);
+			return ret;
+		}
+	}
+
 	/* This loads the count register but does NOT start the count yet */
 	mpcore_wdt_ping(wdd);
 
@@ -170,7 +199,7 @@ static void mpcore_wdt_shutdown(struct platform_device *pdev)
 	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
 
 	if (system_state == SYSTEM_RESTART || system_state == SYSTEM_HALT)
-		mpcore_wdt_stop(&wdt->wdd);
+		__mpcore_wdt_stop(wdt);
 }
 
 static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
@@ -214,6 +243,24 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, wdt);
 	watchdog_set_drvdata(&wdt->wdd, wdt);
 
+	wdt->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(wdt->clk)) {
+		dev_warn(&pdev->dev, "Clock not found\n");
+	} else {
+		ret = clk_prepare(wdt->clk);
+		if (ret) {
+			dev_err(wdt->dev, "clock prepare fail");
+			goto err_put_clk;
+		}
+
+		ret = clk_enable(wdt->clk);
+		if (ret) {
+			dev_err(&pdev->dev, "Clock enable failed\n");
+			clk_unprepare(wdt->clk);
+			goto err_put_clk;
+		}
+	}
+
 	wdt->wdd.bootstatus = (readl_relaxed(wdt->base + TWD_WDOG_RESETSTAT) &
 			TWD_WDOG_RESETSTAT_MASK) ? WDIOF_CARDRESET : 0;
 
@@ -223,7 +270,7 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 	if (ret) {
 		dev_err(wdt->dev, "watchdog_register_device() failed: %d\n",
 				ret);
-		goto err_register;
+		goto err_put_clk;
 	}
 
 	/*
@@ -243,7 +290,10 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 
 	return 0;
 
-err_register:
+err_put_clk:
+	if (!IS_ERR(wdt->clk))
+		clk_put(wdt->clk);
+
 	platform_set_drvdata(pdev, NULL);
 	watchdog_set_drvdata(&wdt->wdd, NULL);
 
@@ -266,7 +316,7 @@ static int mpcore_wdt_suspend(struct device *dev)
 	struct mpcore_wdt *wdt = dev_get_drvdata(dev);
 
 	if (is_wdd_active(&wdt->wdd))
-		mpcore_wdt_stop(&wdt->wdd);	/* Turn the WDT off */
+		return mpcore_wdt_stop(&wdt->wdd);	/* Turn the WDT off */
 
 	return 0;
 }
@@ -276,7 +326,7 @@ static int mpcore_wdt_resume(struct device *dev)
 	struct mpcore_wdt *wdt = dev_get_drvdata(dev);
 
 	if (is_wdd_active(&wdt->wdd))
-		mpcore_wdt_start(&wdt->wdd);
+		return mpcore_wdt_start(&wdt->wdd);
 
 	return 0;
 }
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:22:09 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:09 +0530
Subject: [PATCH V2 14/22] watchdog/mpcore_wdt: replace (__raw_)readl/writel
 with lighter *_relaxed variants
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <8ff8571bad9de24858b525e01c51a22d7837e201.1331524811.git.viresh.kumar@st.com>

readl/writel versions for ARMV6+ contain memory barrier instruction for
synchronizing DMA buffers. These are not required at least on this module.  So
use lighter _relaxed variants.

Also, __raw_* variants don't have take care about endianess, so replace them too
with _relaxed variants.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 7ded2a0..0d2ea32 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -71,10 +71,10 @@ static irqreturn_t mpcore_wdt_fire(int irq, void *arg)
 	struct mpcore_wdt *wdt = arg;
 
 	/* Check it really was our interrupt */
-	if (readl(wdt->base + TWD_WDOG_INTSTAT)) {
+	if (readl_relaxed(wdt->base + TWD_WDOG_INTSTAT)) {
 		dev_crit(wdt->dev, "Triggered - Reboot ignored.\n");
 		/* Clear the interrupt on the watchdog */
-		writel(1, wdt->base + TWD_WDOG_INTSTAT);
+		writel_relaxed(1, wdt->base + TWD_WDOG_INTSTAT);
 		return IRQ_HANDLED;
 	}
 	return IRQ_NONE;
@@ -94,12 +94,12 @@ static int mpcore_wdt_ping(struct watchdog_device *wdd)
 
 	spin_lock(&wdt->lock);
 	/* Assume prescale is set to 256 */
-	count =  __raw_readl(wdt->base + TWD_WDOG_COUNTER);
+	count = readl_relaxed(wdt->base + TWD_WDOG_COUNTER);
 	count = (0xFFFFFFFFU - count) * (HZ / 5);
 	count = (count / 256) * mpcore_margin;
 
 	/* Reload the counter */
-	writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD);
+	writel_relaxed(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD);
 	wdt->perturb = wdt->perturb ? 0 : 1;
 	spin_unlock(&wdt->lock);
 
@@ -111,9 +111,9 @@ static int mpcore_wdt_stop(struct watchdog_device *wdd)
 	struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd);
 
 	spin_lock(&wdt->lock);
-	writel(0x12345678, wdt->base + TWD_WDOG_DISABLE);
-	writel(0x87654321, wdt->base + TWD_WDOG_DISABLE);
-	writel(0x0, wdt->base + TWD_WDOG_CONTROL);
+	writel_relaxed(0x12345678, wdt->base + TWD_WDOG_DISABLE);
+	writel_relaxed(0x87654321, wdt->base + TWD_WDOG_DISABLE);
+	writel_relaxed(0x0, wdt->base + TWD_WDOG_CONTROL);
 	spin_unlock(&wdt->lock);
 
 	return 0;
@@ -130,10 +130,10 @@ static int mpcore_wdt_start(struct watchdog_device *wdd)
 
 	if (mpcore_noboot) {
 		/* Enable watchdog - prescale=256, watchdog mode=0, enable=1 */
-		writel(0x0000FF01, wdt->base + TWD_WDOG_CONTROL);
+		writel_relaxed(0x0000FF01, wdt->base + TWD_WDOG_CONTROL);
 	} else {
 		/* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */
-		writel(0x0000FF09, wdt->base + TWD_WDOG_CONTROL);
+		writel_relaxed(0x0000FF09, wdt->base + TWD_WDOG_CONTROL);
 	}
 
 	return 0;
-- 
1.7.8.110.g4cb5d



From shawn.guo at linaro.org  Fri Mar  9 02:13:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 9 Mar 2012 15:13:49 +0800
Subject: [PATCH v3 00/11] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <4F5966DC.6090201@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <4F5910EE.8090408@freescale.com>
 <20120309011914.GF2499@S2101-09.ap.freescale.net>
 <4F5966DC.6090201@freescale.com>
Message-ID: <20120309071347.GM2499@S2101-09.ap.freescale.net>

On Fri, Mar 09, 2012 at 02:11:41AM +0000, Tabi Timur-B04825 wrote:
> Shawn Guo wrote:
> > Are you testing the patch set on top of the SHA below, which I
> > mentioned in the cover letter?
> >
> >    3030763 (Merge tag 'asoc-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into topic/asoc)
> >
> > I see the similar problem on the following SHA with my testing on
> > imx-sgtl5000.
> >
> >    1a8feca (Merge branch 'for-3.4' into asoc-next)
> 
> It appears the problem is with for-3.4 itself.  I'm running git-bisect now 
> to narrow it down.
> 
My bisect tells that the offending commit is:

  96acc35 (ASoC: DAPM: Make sure DAPM widget IO ops hold the component mutex)

But I do not understand why yet.

-- 
Regards,
Shawn


From broonie at opensource.wolfsonmicro.com  Mon Mar 12 10:23:40 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 12 Mar 2012 14:23:40 +0000
Subject: [PATCH 11/11] ARM: tegra: pcie: Add device tree support
In-Reply-To: <20120312141705.GA16395@avionic-0098.mockup.avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-12-git-send-email-thierry.reding@avionic-design.de>
 <4F59253D.7070100@wwwdotorg.org>
 <20120312120610.GA14020@sirena.org.uk>
 <20120312141705.GA16395@avionic-0098.mockup.avionic-design.de>
Message-ID: <20120312142340.GI3110@opensource.wolfsonmicro.com>

On Mon, Mar 12, 2012 at 03:17:05PM +0100, Thierry Reding wrote:

> My understanding of the fixed regulator was that it was meant to be used for
> fixed voltage supplies that can still be enabled or disabled (for example as
> supplied by a GPIO) but not regulators that are fix in the sense that they
> cannot be enabled or disabled at all but are always on.

No, not at all.  It's for any random supply that doesn't have much
meaningful control - as you'll see from the code the GPIO is totally
optional if you look at the git history you'll see that the GPIO was
added some time after the driver was originally merged.

> Is that how it is supposed to work?

Yes.
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From broonie at opensource.wolfsonmicro.com  Mon Mar 12 10:21:43 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 12 Mar 2012 14:21:43 +0000
Subject: [PATCH 5/5] mmc: sdhci-s3c: setup pins using pinctrl interface
In-Reply-To: <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
Message-ID: <20120312142143.GC14020@sirena.org.uk>

On Sun, Mar 11, 2012 at 06:16:05PM +0530, Thomas Abraham wrote:
> The platform specific callback to setup the sdhci pin mux and pin config
> is removed and the pinctrl subsystem interface is used to setup the
> mux and config.

You've only added pinctrl support for Exynos but this driver is also
used by SoCs going back to s3c24xx era.  Either all those SoCs need to
be converted to use pinctrl or the driver needs to understand both
methods (eg, using pinctrl if no callback is supplied).


From broonie at opensource.wolfsonmicro.com  Mon Mar 12 10:06:20 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 12 Mar 2012 14:06:20 +0000
Subject: mfd: mc13xxx: add I2C support, V2
In-Reply-To: <20120311115018.GA16825@pengutronix.de>
References: <1331429402-9639-1-git-send-email-marc@cpdesign.com.au>
 <20120311115018.GA16825@pengutronix.de>
Message-ID: <20120312140620.GB14020@sirena.org.uk>

On Sun, Mar 11, 2012 at 12:50:18PM +0100, Wolfram Sang wrote:

> free, if this is desired. I think the regmap approach should have been tried
> before we go custom. sound/soc/codecs/ad193x.c might give an impression how
> regmap spi/i2c in one driver could look like.

There's a bunch of other examples in sound/soc and also the wm831x PMIC
driver in drivers/mfd.  For an initial conversion I'd not worry about
the cache, especially with some of the older PMICs hardware designers
were known to come up with some "innovative usability solutions" which
can cause hassle.


From viresh.kumar at st.com  Mon Mar 12 00:21:56 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:51:56 +0530
Subject: [PATCH V2 01/22] watchdog: Add is_wdt_active() routine
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <a80728acba22a17994a2ae795a10a8796d4b6d72.1331524811.git.viresh.kumar@st.com>

Some watchdog may need to check if watchdog is ACTIVE or not, for example in
their suspend/resume hooks.

This patch adds this routine and changes the core drivers to use it.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/via_wdt.c      |    2 +-
 drivers/watchdog/watchdog_dev.c |    6 +++---
 include/linux/watchdog.h        |    5 +++++
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/watchdog/via_wdt.c b/drivers/watchdog/via_wdt.c
index 8f07dd4..62fed64 100644
--- a/drivers/watchdog/via_wdt.c
+++ b/drivers/watchdog/via_wdt.c
@@ -88,7 +88,7 @@ static inline void wdt_reset(void)
 static void wdt_timer_tick(unsigned long data)
 {
 	if (time_before(jiffies, next_heartbeat) ||
-	   (!test_bit(WDOG_ACTIVE, &wdt_dev.status))) {
+	   (!is_wdd_active(&wdt_dev))) {
 		wdt_reset();
 		mod_timer(&timer, jiffies + WDT_HEARTBEAT);
 	} else
diff --git a/drivers/watchdog/watchdog_dev.c b/drivers/watchdog/watchdog_dev.c
index 1199da0f..9668253 100644
--- a/drivers/watchdog/watchdog_dev.c
+++ b/drivers/watchdog/watchdog_dev.c
@@ -59,7 +59,7 @@ static struct watchdog_device *wdd;
 
 static int watchdog_ping(struct watchdog_device *wddev)
 {
-	if (test_bit(WDOG_ACTIVE, &wddev->status)) {
+	if (is_wdd_active(wddev)) {
 		if (wddev->ops->ping)
 			return wddev->ops->ping(wddev);  /* ping the watchdog */
 		else
@@ -81,7 +81,7 @@ static int watchdog_start(struct watchdog_device *wddev)
 {
 	int err;
 
-	if (!test_bit(WDOG_ACTIVE, &wddev->status)) {
+	if (!is_wdd_active(wddev)) {
 		err = wddev->ops->start(wddev);
 		if (err < 0)
 			return err;
@@ -111,7 +111,7 @@ static int watchdog_stop(struct watchdog_device *wddev)
 		return err;
 	}
 
-	if (test_bit(WDOG_ACTIVE, &wddev->status)) {
+	if (is_wdd_active(wddev)) {
 		err = wddev->ops->stop(wddev);
 		if (err < 0)
 			return err;
diff --git a/include/linux/watchdog.h b/include/linux/watchdog.h
index 43ba5b3..4fc57b2 100644
--- a/include/linux/watchdog.h
+++ b/include/linux/watchdog.h
@@ -118,6 +118,11 @@ struct watchdog_device {
 #define WDOG_NO_WAY_OUT		3	/* Is 'nowayout' feature set ? */
 };
 
+static inline bool is_wdd_active(struct watchdog_device *wdd)
+{
+	return test_bit(WDOG_ACTIVE, &wdd->status);
+}
+
 #ifdef CONFIG_WATCHDOG_NOWAYOUT
 #define WATCHDOG_NOWAYOUT		1
 #define WATCHDOG_NOWAYOUT_INIT_STATUS	(1 << WDOG_NO_WAY_OUT)
-- 
1.7.8.110.g4cb5d



From broonie at opensource.wolfsonmicro.com  Sun Mar 11 07:40:15 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 11 Mar 2012 11:40:15 +0000
Subject: [PATCH 2/4] Add imx3sound sound support.
In-Reply-To: <1331304916-4724-3-git-send-email-philippe.retornaz@epfl.ch>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-3-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <20120311114014.GB3233@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 03:55:14PM +0100, Philippe R?tornaz wrote:

> +static int imx3sound_hifi_hw_free(struct snd_pcm_substream *substream)
> +{
> +	return 0;
> +}

Remove all empty functions.

> +	imx3sound_snd_device = platform_device_alloc("soc-audio", -1);
> +	if (!imx3sound_snd_device)
> +		return -ENOMEM;

No soc-audio usage, use snd_soc_register_card() from a platform device.
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From broonie at opensource.wolfsonmicro.com  Fri Mar  9 07:37:04 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 12:37:04 +0000
Subject: [PATCH v11] Regulator: Add Anatop regulator driver
In-Reply-To: <1331279829-4584-1-git-send-email-paul.liu@linaro.org>
References: <1331279829-4584-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120309123704.GU3273@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 03:57:09PM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is an integrated regulator inside i.MX6 SoC.
> There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
> And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
> This patch adds the Anatop regulator driver.

This looks good apart from the issue Axel noted.
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From heiko at sntech.de  Mon Mar 12 14:59:32 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Mon, 12 Mar 2012 19:59:32 +0100
Subject: [PATCH 0/6] S3C24XX: Add support for HSSPI on S3C2416/S3C2443
Message-ID: <201203121959.32966.heiko@sntech.de>

The S3C2416/S3C2443/S3C2450 SoCs contain HSSPI controllers compatible
with the ones in the S3C64xx and later.

The second patch modifying the dma selection depends on the series
enabling the dma support on the S3C2416, but as the whole s3c64xx-spi
driver needs dma support this should be ok.

Tested on an Asus DR-900 ebook reader with a Marvell MR8686 using the
libertas driver.


This is a repost of the series adapted to changes resulting from the
other cleanup series.


Heiko Stuebner (6):
  ARM: S3C24XX: Add forgotten clock lookup table to S3C2443
  ARM: S3C24XX: claim spi channels for hsspi in dma-s3c2443
  ARM: S3C24XX: Add map entries needed by the s3c64xx-spi devices
  ARM: S3C24XX: Add clock-lookup entries required by s3c64xx-spi
  ARM: S3C24XX: Add HSSPI setup callback for s3c64xx-spi driver
  spi/s3c64xx: Allow usage for ARCH_S3C24XX

 arch/arm/mach-s3c24xx/Kconfig            |    5 ++++
 arch/arm/mach-s3c24xx/Makefile           |    1 +
 arch/arm/mach-s3c24xx/clock-s3c2416.c    |    1 +
 arch/arm/mach-s3c24xx/clock-s3c2443.c    |    6 ++++
 arch/arm/mach-s3c24xx/common-s3c2443.c   |   15 +++++++----
 arch/arm/mach-s3c24xx/dma-s3c2443.c      |   16 +++++++++---
 arch/arm/mach-s3c24xx/include/mach/dma.h |    4 +++
 arch/arm/mach-s3c24xx/include/mach/map.h |    5 ++++
 arch/arm/mach-s3c24xx/setup-spi.c        |   39 ++++++++++++++++++++++++++++++
 drivers/spi/Kconfig                      |    2 +-
 10 files changed, 84 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/mach-s3c24xx/setup-spi.c

-- 
1.7.2.3



From broonie at opensource.wolfsonmicro.com  Mon Mar 12 08:06:11 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 12 Mar 2012 12:06:11 +0000
Subject: [PATCH 11/11] ARM: tegra: pcie: Add device tree support
In-Reply-To: <4F59253D.7070100@wwwdotorg.org>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-12-git-send-email-thierry.reding@avionic-design.de>
 <4F59253D.7070100@wwwdotorg.org>
Message-ID: <20120312120610.GA14020@sirena.org.uk>

On Thu, Mar 08, 2012 at 02:31:41PM -0700, Stephen Warren wrote:
> On 03/08/2012 07:51 AM, Thierry Reding wrote:

> > +- vdd-supply: power supply for controller (1.05V)

> Should those *-supply properties really be optional? I got the
> impression talking to Mark in a different thread that all regulators
> should exist, although their implementation may be via a fixed
> regulator, with no GPIO, as determined by the board design.

Depends on the electronics, if the device can function without a supply
then it is OK for it to be optional.  This is moderately unusual but not
unknown.  It's obviously also OK to omit the supply if the system
doesn't use software regulators at all, though a kernel with regulator
support enabled would need to use dummy regulators to stub things out.


From broonie at opensource.wolfsonmicro.com  Fri Mar  9 07:50:03 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 12:50:03 +0000
Subject: [PATCH 2/2] ASoC: OMAP: Build config cleanup for McBSP
In-Reply-To: <1331283078-14846-3-git-send-email-peter.ujfalusi@ti.com>
References: <1331283078-14846-1-git-send-email-peter.ujfalusi@ti.com>
 <1331283078-14846-3-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120309125003.GY3273@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 10:51:18AM +0200, Peter Ujfalusi wrote:
> The McBSP driver stack has been moved, and rewritten resulting a single
> driver - selected by CONFIG_SND_OMAP_SOC_MCBSP. There is no longer need to
> have CONFIG_OMAP_MCBSP anymore.

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
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From hunold at linuxtv.org  Mon Mar 12 04:45:07 2012
From: hunold at linuxtv.org (Michael Hunold)
Date: Mon, 12 Mar 2012 09:45:07 +0100
Subject: iMX53 and MMC_CAP_SDIO_IRQ
Message-ID: <4F5DB793.3080904@linuxtv.org>

Hi,

I am using a Freescale iMX53 Quick Start Board. The uSD card that comes
with the device contains a Linux kernel labeled "Linux version
2.6.35.3-01129-g691c08a-dirty".

After some digging I found out that this corresponds to the
"imx_2.6.35_11.09.01" tag in the Freescale Linux kernel that can be
found at http://opensource.freescale.com/pub/scm/imx/linux-2.6-imx.git

I am experimenting with an SDIO card and that one works fine using that
kernel. So far, so good.

Now I have tried to use a vanilla Git Linux kernel (3.3.0-rc6+) with
mixed results.

The card is recognised correctly and mostly initialised, up to the point
where an apparently an interrupt from the card is expected to happen.
Because the SDHCI driver supports "real" interrupts (via
MMC_CAP_SDIO_IRQ) the SDIO IRQ thread goes to sleep, but is never woken
up in my case.

After about 2.5 seconds, I receive an error -110 (timeout) and the
initialisation is aborted.

So my question is: is anybody using an iMX53 (or any other hardware
using the SDHCI driver) together with "real" interrupts (via
MMC_CAP_SDIO_IRQ), not polled interrupts?

The main problem is that the ancient Freescale 2.6.35 kernel is using
the "mx_sdhci" driver, while in 3.3.0-rc6+ the generic "sdhci" driver is
used, so it's not possible to simply compare the changes between the two
versions. :-(

Does anybody know the difference between the "mx_sdhci" from Freescale
2.6.35 kernel and the the "sdhci" driver in 3.3.0-rc6+?

Probably this is a question for the Freescale people: why was the
"mx_sdhci" necessary at all and why is it not necessary any more?

Any help, hints and historical informations are highly appreciated,
before I start to look deeper into this problem.

CU
Michael.


From pullip.cho at samsung.com  Fri Mar  9 07:15:24 2012
From: pullip.cho at samsung.com (Cho KyongHo)
Date: Fri, 09 Mar 2012 21:15:24 +0900
Subject: [PATCH v11 3/3] iommu/exynos: Add iommu driver for Exynos Platforms
Message-ID: <017a01ccfdee$4e5e7a00$eb1b6e00$%cho@samsung.com>

This is the System MMU driver and IOMMU API implementation for
Exynos SOC platforms. Exynos platforms has more than 10 System
MMUs dedicated for each multimedia accelerators.

The System MMU driver is already in arc/arm/plat-s5p but it is
moved to drivers/iommu due to Ohad Ben-Cohen gathered IOMMU drivers
there

Any device driver in Exynos platforms that needs to control its
System MMU must call platform_set_sysmmu() to inform System MMU
driver who will control it.
platform_set_sysmmu() is defined in <mach/sysmmu.h>

Cc: Joerg Roedel <joerg.roedel at amd.com>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
---
 drivers/iommu/Kconfig        |   21 +
 drivers/iommu/Makefile       |    1 +
 drivers/iommu/exynos-iommu.c | 1081 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1103 insertions(+), 0 deletions(-)
 create mode 100644 drivers/iommu/exynos-iommu.c

diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 6bea696..25d3eed 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -142,4 +142,25 @@ config OMAP_IOMMU_DEBUG
 
          Say N unless you know you need this.
 
+config EXYNOS_IOMMU
+	bool "Exynos IOMMU Support"
+	depends on EXYNOS_DEV_SYSMMU
+	select IOMMU_API
+	help
+	  Support for the IOMMU(System MMU) of Samsung Exynos application
+	  processor family. This enables H/W multimedia accellerators to see
+	  non-linear physical memory chunks as a linear memory in their
+	  address spaces
+
+	  If unsure, say N here.
+
+config EXYNOS_IOMMU_DEBUG
+	bool "Debugging log for Exynos IOMMU"
+	depends on EXYNOS_IOMMU
+	help
+	  Select this to see the detailed log message that shows what
+	  happens in the IOMMU driver
+
+	  Say N unless you need kernel log message for IOMMU debugging
+
 endif # IOMMU_SUPPORT
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 0e36b49..5a8fd97 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_IRQ_REMAP) += intr_remapping.o
 obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
 obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o
 obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
+obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
new file mode 100644
index 0000000..8156c41
--- /dev/null
+++ b/drivers/iommu/exynos-iommu.c
@@ -0,0 +1,1081 @@
+/* linux/drivers/iommu/exynos_iommu.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifdef CONFIG_EXYNOS_IOMMU_DEBUG
+#define DEBUG
+#endif
+
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mm.h>
+#include <linux/iommu.h>
+#include <linux/errno.h>
+#include <linux/list.h>
+#include <linux/memblock.h>
+#include <linux/export.h>
+
+#include <asm/cacheflush.h>
+#include <asm/pgtable.h>
+
+#include <mach/sysmmu.h>
+
+#define SECT_ORDER 20
+#define LPAGE_ORDER 16
+#define SPAGE_ORDER 12
+
+#define SECT_SIZE (1 << SECT_ORDER)
+#define LPAGE_SIZE (1 << LPAGE_ORDER)
+#define SPAGE_SIZE (1 << SPAGE_ORDER)
+
+#define SECT_MASK (~(SECT_SIZE - 1))
+#define LPAGE_MASK (~(LPAGE_SIZE - 1))
+#define SPAGE_MASK (~(SPAGE_SIZE - 1))
+
+#define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
+#define lv1ent_page(sent) ((*(sent) & 3) == 1)
+#define lv1ent_section(sent) ((*(sent) & 3) == 2)
+
+#define lv2ent_fault(pent) ((*(pent) & 3) == 0)
+#define lv2ent_small(pent) ((*(pent) & 2) == 2)
+#define lv2ent_large(pent) ((*(pent) & 3) == 1)
+
+#define section_phys(sent) (*(sent) & SECT_MASK)
+#define section_offs(iova) ((iova) & 0xFFFFF)
+#define lpage_phys(pent) (*(pent) & LPAGE_MASK)
+#define lpage_offs(iova) ((iova) & 0xFFFF)
+#define spage_phys(pent) (*(pent) & SPAGE_MASK)
+#define spage_offs(iova) ((iova) & 0xFFF)
+
+#define lv1ent_offset(iova) ((iova) >> SECT_ORDER)
+#define lv2ent_offset(iova) (((iova) & 0xFF000) >> SPAGE_ORDER)
+
+#define NUM_LV1ENTRIES 4096
+#define NUM_LV2ENTRIES 256
+
+#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
+
+#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
+
+#define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
+
+#define mk_lv1ent_sect(pa) ((pa) | 2)
+#define mk_lv1ent_page(pa) ((pa) | 1)
+#define mk_lv2ent_lpage(pa) ((pa) | 1)
+#define mk_lv2ent_spage(pa) ((pa) | 2)
+
+#define CTRL_ENABLE	0x5
+#define CTRL_BLOCK	0x7
+#define CTRL_DISABLE	0x0
+
+#define REG_MMU_CTRL		0x000
+#define REG_MMU_CFG		0x004
+#define REG_MMU_STATUS		0x008
+#define REG_MMU_FLUSH		0x00C
+#define REG_MMU_FLUSH_ENTRY	0x010
+#define REG_PT_BASE_ADDR	0x014
+#define REG_INT_STATUS		0x018
+#define REG_INT_CLEAR		0x01C
+
+#define REG_PAGE_FAULT_ADDR	0x024
+#define REG_AW_FAULT_ADDR	0x028
+#define REG_AR_FAULT_ADDR	0x02C
+#define REG_DEFAULT_SLAVE_ADDR	0x030
+
+#define REG_MMU_VERSION		0x034
+
+#define REG_PB0_SADDR		0x04C
+#define REG_PB0_EADDR		0x050
+#define REG_PB1_SADDR		0x054
+#define REG_PB1_EADDR		0x058
+
+static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
+{
+	return pgtable + lv1ent_offset(iova);
+}
+
+static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
+{
+	return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
+}
+
+enum exynos_sysmmu_inttype {
+	SYSMMU_PAGEFAULT,
+	SYSMMU_AR_MULTIHIT,
+	SYSMMU_AW_MULTIHIT,
+	SYSMMU_BUSERROR,
+	SYSMMU_AR_SECURITY,
+	SYSMMU_AR_ACCESS,
+	SYSMMU_AW_SECURITY,
+	SYSMMU_AW_PROTECTION, /* 7 */
+	SYSMMU_FAULT_UNKNOWN,
+	SYSMMU_FAULTS_NUM
+};
+
+typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype,
+			unsigned long pgtable_base, unsigned long fault_addr);
+
+static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
+	REG_PAGE_FAULT_ADDR,
+	REG_AR_FAULT_ADDR,
+	REG_AW_FAULT_ADDR,
+	REG_DEFAULT_SLAVE_ADDR,
+	REG_AR_FAULT_ADDR,
+	REG_AR_FAULT_ADDR,
+	REG_AW_FAULT_ADDR,
+	REG_AW_FAULT_ADDR
+};
+
+static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
+	"PAGE FAULT",
+	"AR MULTI-HIT FAULT",
+	"AW MULTI-HIT FAULT",
+	"BUS ERROR",
+	"AR SECURITY PROTECTION FAULT",
+	"AR ACCESS PROTECTION FAULT",
+	"AW SECURITY PROTECTION FAULT",
+	"AW ACCESS PROTECTION FAULT",
+	"UNKNOWN FAULT"
+};
+
+/* We does not consider super section mapping (16MB) */
+struct iommu_client {
+	struct list_head node;
+	struct device *dev;
+};
+
+struct exynos_iommu_domain {
+	struct list_head clients; /* list of iommu_client */
+	unsigned long *pgtable; /* lv1 page table, 16KB */
+	short *lv2entcnt; /* free lv2 entry counter for each section */
+	spinlock_t lock; /* lock for this structure and attached iommu_client */
+	spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
+};
+
+struct sysmmu_drvdata {
+	struct device *sysmmu;
+	char *dbgname;
+	int nsfrs;
+	void __iomem **sfrbases;
+	struct clk *clk[2];
+	int activations;
+	rwlock_t lock;
+	struct iommu_domain *domain;
+	sysmmu_fault_handler_t fault_handler;
+	unsigned long pgtable;
+	struct iommu_client client;
+};
+
+static bool set_sysmmu_active(struct sysmmu_drvdata *data)
+{
+	/* return true if the System MMU was not active previously
+	   and it needs to be initialized */
+	return ++data->activations == 1;
+}
+
+static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
+{
+	/* return true if the System MMU is needed to be disabled */
+	BUG_ON(data->activations < 1);
+	return --data->activations == 0;
+}
+
+static bool is_sysmmu_active(struct sysmmu_drvdata *data)
+{
+	return data->activations > 0;
+}
+
+static void sysmmu_block(void __iomem *sfrbase)
+{
+	__raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
+}
+
+static void sysmmu_unblock(void __iomem *sfrbase)
+{
+	__raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
+}
+
+static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
+{
+	__raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
+}
+
+static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
+						unsigned long iova)
+{
+	__raw_writel((iova & SPAGE_MASK) | 1, sfrbase + REG_MMU_FLUSH_ENTRY);
+}
+
+static void __sysmmu_set_ptbase(void __iomem *sfrbase,
+				       unsigned long pgd)
+{
+	__raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */
+	__raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
+
+	__sysmmu_tlb_invalidate(sfrbase);
+}
+
+static void __sysmmu_set_prefbuf(void __iomem *sfrbase, unsigned long base,
+						unsigned long size, int idx)
+{
+	__raw_writel(base, sfrbase + REG_PB0_SADDR + idx * 8);
+	__raw_writel(size - 1 + base,  sfrbase + REG_PB0_EADDR + idx * 8);
+}
+
+void exynos_sysmmu_set_prefbuf(struct device *dev,
+				unsigned long base0, unsigned long size0,
+				unsigned long base1, unsigned long size1)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	unsigned long flags;
+	int i;
+
+	BUG_ON((base0 + size0) <= base0);
+	BUG_ON((size1 > 0) && ((base1 + size1) <= base1));
+
+	read_lock_irqsave(&data->lock, flags);
+	if (!is_sysmmu_active(data))
+		goto finish;
+
+	for (i = 0; i < data->nsfrs; i++) {
+		if ((readl(data->sfrbases[i] + REG_MMU_VERSION) >> 28) == 3) {
+			sysmmu_block(data->sfrbases[i]);
+
+			if (size1 == 0) {
+				if (size0 <= SZ_128K) {
+					base1 = base0;
+					size1 = size0;
+				} else {
+					size1 = size0 -
+						ALIGN(size0 / 2, SZ_64K);
+					size0 = size0 - size1;
+					base1 = base0 + size0;
+				}
+			}
+
+			__sysmmu_set_prefbuf(
+					data->sfrbases[i], base0, size0, 0);
+			__sysmmu_set_prefbuf(
+					data->sfrbases[i], base1, size1, 1);
+
+			sysmmu_unblock(data->sfrbases[i]);
+		}
+	}
+finish:
+	read_unlock_irqrestore(&data->lock, flags);
+}
+
+static void __set_fault_handler(struct sysmmu_drvdata *data,
+					sysmmu_fault_handler_t handler)
+{
+	unsigned long flags;
+
+	write_lock_irqsave(&data->lock, flags);
+	data->fault_handler = handler;
+	write_unlock_irqrestore(&data->lock, flags);
+}
+
+void exynos_sysmmu_set_fault_handler(struct device *dev,
+					sysmmu_fault_handler_t handler)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+
+	__set_fault_handler(data, handler);
+}
+
+static int default_fault_handler(enum exynos_sysmmu_inttype itype,
+		     unsigned long pgtable_base, unsigned long fault_addr)
+{
+	unsigned long *ent;
+
+	if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
+		itype = SYSMMU_FAULT_UNKNOWN;
+
+	pr_err("%s occured at 0x%lx(Page table base: 0x%lx)\n",
+			sysmmu_fault_name[itype], fault_addr, pgtable_base);
+
+	ent = section_entry(__va(pgtable_base), fault_addr);
+	pr_err("\tLv1 entry: 0x%lx\n", *ent);
+
+	if (lv1ent_page(ent)) {
+		ent = page_entry(ent, fault_addr);
+		pr_err("\t Lv2 entry: 0x%lx\n", *ent);
+	}
+
+	pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
+
+	BUG();
+
+	return 0;
+}
+
+static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
+{
+	/* SYSMMU is in blocked when interrupt occurred. */
+	struct sysmmu_drvdata *data = dev_id;
+	struct resource *irqres;
+	struct platform_device *pdev;
+	enum exynos_sysmmu_inttype itype;
+	unsigned long addr = -1;
+
+	int i, ret = -ENOSYS;
+
+	read_lock(&data->lock);
+
+	WARN_ON(!is_sysmmu_active(data));
+
+	pdev = to_platform_device(data->sysmmu);
+	for (i = 0; i < pdev->num_resources; i++) {
+		irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+		if (irqres && ((int)irqres->start == irq))
+			break;
+	}
+
+	if (i == pdev->num_resources) {
+		itype = SYSMMU_FAULT_UNKNOWN;
+	} else {
+		i /= 2;
+
+		itype = (enum exynos_sysmmu_inttype)
+			__ffs(__raw_readl(data->sfrbases[i] + REG_INT_STATUS));
+		if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
+			itype = SYSMMU_FAULT_UNKNOWN;
+		else
+			addr = __raw_readl(
+				data->sfrbases[i] + fault_reg_offset[itype]);
+	}
+
+	if (data->domain)
+		ret = report_iommu_fault(data->domain, data->client.dev,
+				addr, itype);
+
+	if ((ret == -ENOSYS) && data->fault_handler) {
+		unsigned long base = data->pgtable;
+		if (itype != SYSMMU_FAULT_UNKNOWN)
+			base = __raw_readl(
+					data->sfrbases[i] + REG_PT_BASE_ADDR);
+		ret = data->fault_handler(itype, base, addr);
+	}
+
+	if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
+		__raw_writel(1 << itype, data->sfrbases[i] + REG_INT_CLEAR);
+	else
+		dev_dbg(data->sysmmu, "(%s) %s is not handled.\n",
+				data->dbgname, sysmmu_fault_name[itype]);
+
+	if (itype != SYSMMU_FAULT_UNKNOWN)
+		sysmmu_unblock(data->sfrbases[i]);
+
+	read_unlock(&data->lock);
+
+	return IRQ_HANDLED;
+}
+
+static bool __sysmmu_disable(struct sysmmu_drvdata *data)
+{
+	unsigned long flags;
+	bool disabled = false;
+	int i;
+
+	write_lock_irqsave(&data->lock, flags);
+
+	if (!set_sysmmu_inactive(data))
+		goto finish;
+
+	for (i = 0; i < data->nsfrs; i++)
+		__raw_writel(CTRL_DISABLE, data->sfrbases[i] + REG_MMU_CTRL);
+
+	if (data->clk[1])
+		clk_disable(data->clk[1]);
+	if (data->clk[0])
+		clk_disable(data->clk[0]);
+
+	disabled = true;
+	data->pgtable = 0;
+	data->domain = NULL;
+finish:
+	write_unlock_irqrestore(&data->lock, flags);
+
+	if (disabled)
+		dev_dbg(data->sysmmu, "(%s) Disabled\n", data->dbgname);
+	else
+		dev_dbg(data->sysmmu, "(%s) %d times left to be disabled\n",
+					data->dbgname, data->activations);
+
+	return disabled;
+}
+
+/* __exynos_sysmmu_enable: Enables System MMU
+ *
+ * returns -error if an error occurred and System MMU is not enabled,
+ * 0 if the System MMU has been just enabled and 1 if System MMU was already
+ * enabled before.
+ */
+static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data,
+			unsigned long pgtable, struct iommu_domain *domain)
+{
+	int i, ret;
+	unsigned long flags;
+
+	write_lock_irqsave(&data->lock, flags);
+
+	if (!set_sysmmu_active(data)) {
+		if (WARN_ON(pgtable != data->pgtable)) {
+			ret = -EBUSY;
+			set_sysmmu_inactive(data);
+		} else {
+			ret = 1;
+		}
+
+		dev_dbg(data->sysmmu, "(%s) Already enabled\n", data->dbgname);
+		goto finish;
+	}
+
+	ret = 0;
+
+	if (data->clk[0])
+		clk_enable(data->clk[0]);
+	if (data->clk[1])
+		clk_enable(data->clk[1]);
+
+	data->pgtable = pgtable;
+
+	for (i = 0; i < data->nsfrs; i++) {
+		__sysmmu_set_ptbase(data->sfrbases[i], pgtable);
+
+		if ((readl(data->sfrbases[i] + REG_MMU_VERSION) >> 28) == 3) {
+			/* System MMU version is 3.x */
+			__raw_writel((1 << 12) | (2 << 28),
+					data->sfrbases[i] + REG_MMU_CFG);
+			__sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 0);
+			__sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 1);
+		}
+
+		__raw_writel(CTRL_ENABLE, data->sfrbases[i] + REG_MMU_CTRL);
+	}
+
+	data->domain = domain;
+
+	dev_dbg(data->sysmmu, "(%s) Enabled\n", data->dbgname);
+finish:
+	write_unlock_irqrestore(&data->lock, flags);
+
+	if ((ret < 0) && (ret != -EBUSY)) {
+		__sysmmu_disable(data);
+		dev_dbg(data->sysmmu, "(%s) Failed to enable\n", data->dbgname);
+	}
+
+	return ret;
+}
+
+int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	int ret;
+
+	BUG_ON(!memblock_is_memory(pgtable));
+
+	ret = pm_runtime_get_sync(data->sysmmu);
+	if (ret < 0)
+		return ret;
+
+	ret = __exynos_sysmmu_enable(data, pgtable, NULL);
+	if (ret < 0)
+		pm_runtime_put(data->sysmmu);
+
+	return ret;
+}
+
+bool exynos_sysmmu_disable(struct device *dev)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	bool disabled;
+
+	disabled = __sysmmu_disable(data);
+	dev_dbg(dev, disabled ? "System MMU Disabled.\n" :
+			"Deactivation request for System MMU ignorred.\n");
+
+	pm_runtime_put(data->sysmmu);
+
+	return disabled;
+}
+
+static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova)
+{
+	unsigned long flags;
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+
+	read_lock_irqsave(&data->lock, flags);
+
+	if (is_sysmmu_active(data)) {
+		int i;
+		for (i = 0; i < data->nsfrs; i++) {
+			sysmmu_block(data->sfrbases[i]);
+			__sysmmu_tlb_invalidate_entry(data->sfrbases[i], iova);
+			sysmmu_unblock(data->sfrbases[i]);
+		}
+	} else {
+		dev_dbg(data->sysmmu,
+			"(%s) Disabled. Skipping invalidating TLB.\n",
+			data->dbgname);
+	}
+
+	read_unlock_irqrestore(&data->lock, flags);
+}
+
+void exynos_sysmmu_tlb_invalidate(struct device *dev)
+{
+	unsigned long flags;
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+
+	read_lock_irqsave(&data->lock, flags);
+
+	if (is_sysmmu_active(data)) {
+		int i;
+		for (i = 0; i < data->nsfrs; i++) {
+			sysmmu_block(data->sfrbases[i]);
+			__sysmmu_tlb_invalidate(data->sfrbases[i]);
+			sysmmu_unblock(data->sfrbases[i]);
+		}
+	} else {
+		dev_dbg(data->sysmmu,
+			"(%s) Disabled. Skipping invalidating TLB.\n",
+			data->dbgname);
+	}
+
+	read_unlock_irqrestore(&data->lock, flags);
+}
+
+static int exynos_sysmmu_probe(struct platform_device *pdev)
+{
+	int i, ret;
+	struct device *dev;
+	struct sysmmu_drvdata *data;
+
+	dev = &pdev->dev;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data) {
+		dev_dbg(dev, "Not enough memory\n");
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+
+	ret = dev_set_drvdata(dev, data);
+	if (ret) {
+		dev_dbg(dev, "Unabled to initialize driver data\n");
+		goto err_init;
+	}
+
+	data->nsfrs = pdev->num_resources / 2;
+	data->sfrbases = kmalloc(sizeof(*data->sfrbases) * data->nsfrs,
+								GFP_KERNEL);
+	if (data->sfrbases == NULL) {
+		dev_dbg(dev, "Not enough memory\n");
+		ret = -ENOMEM;
+		goto err_init;
+	}
+
+	for (i = 0; i < data->nsfrs; i++) {
+		struct resource *res;
+		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+		if (!res) {
+			dev_dbg(dev, "Unable to find IOMEM region\n");
+			ret = -ENOENT;
+			goto err_res;
+		}
+
+		data->sfrbases[i] = ioremap(res->start, resource_size(res));
+		if (!data->sfrbases[i]) {
+			dev_dbg(dev, "Unable to map IOMEM @ PA:%#x\n",
+							res->start);
+			ret = -ENOENT;
+			goto err_res;
+		}
+	}
+
+	for (i = 0; i < data->nsfrs; i++) {
+		ret = platform_get_irq(pdev, i);
+		if (ret <= 0) {
+			dev_dbg(dev, "Unable to find IRQ resource\n");
+			goto err_irq;
+		}
+
+		ret = request_irq(ret, exynos_sysmmu_irq, 0,
+					dev_name(dev), data);
+		if (ret) {
+			dev_dbg(dev, "Unabled to register interrupt handler\n");
+			goto err_irq;
+		}
+	}
+
+	if (dev_get_platdata(dev)) {
+		char *deli, *beg;
+		struct sysmmu_platform_data *platdata = dev_get_platdata(dev);
+
+		beg = platdata->clockname;
+
+		for (deli = beg; (*deli != '\0') && (*deli != ','); deli++)
+			/* NOTHING */;
+
+		if (*deli == '\0')
+			deli = NULL;
+		else
+			*deli = '\0';
+
+		data->clk[0] = clk_get(dev, beg);
+		if (IS_ERR(data->clk[0])) {
+			data->clk[0] = NULL;
+			dev_dbg(dev, "No clock descriptor registered\n");
+		}
+
+		if (data->clk[0] && deli) {
+			*deli = ',';
+			data->clk[1] = clk_get(dev, deli + 1);
+			if (IS_ERR(data->clk[1]))
+				data->clk[1] = NULL;
+		}
+
+		data->dbgname = platdata->dbgname;
+	}
+
+	data->sysmmu = dev;
+	rwlock_init(&data->lock);
+	INIT_LIST_HEAD(&data->client.node);
+
+	__set_fault_handler(data, &default_fault_handler);
+
+	if (dev->parent)
+		pm_runtime_enable(dev);
+
+	dev_dbg(dev, "(%s) Initialized\n", data->dbgname);
+	return 0;
+err_irq:
+	while (i-- > 0) {
+		int irq;
+
+		irq = platform_get_irq(pdev, i);
+		free_irq(irq, data);
+	}
+err_res:
+	while (data->nsfrs-- > 0)
+		iounmap(data->sfrbases[data->nsfrs]);
+	kfree(data->sfrbases);
+err_init:
+	kfree(data);
+err_alloc:
+	dev_err(dev, "Failed to initialize\n");
+	return ret;
+}
+
+static struct platform_driver exynos_sysmmu_driver = {
+	.probe		= exynos_sysmmu_probe,
+	.driver		= {
+		.owner		= THIS_MODULE,
+		.name		= "exynos-sysmmu",
+	}
+};
+
+static inline void pgtable_flush(void *vastart, void *vaend)
+{
+	dmac_flush_range(vastart, vaend);
+	outer_flush_range(virt_to_phys(vastart),
+				virt_to_phys(vaend));
+}
+
+static int exynos_iommu_domain_init(struct iommu_domain *domain)
+{
+	struct exynos_iommu_domain *priv;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->pgtable = (unsigned long *)__get_free_pages(
+						GFP_KERNEL | __GFP_ZERO, 2);
+	if (!priv->pgtable)
+		goto err_pgtable;
+
+	priv->lv2entcnt = (short *)__get_free_pages(
+						GFP_KERNEL | __GFP_ZERO, 1);
+	if (!priv->lv2entcnt)
+		goto err_counter;
+
+	pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
+
+	spin_lock_init(&priv->lock);
+	spin_lock_init(&priv->pgtablelock);
+	INIT_LIST_HEAD(&priv->clients);
+
+	domain->priv = priv;
+	return 0;
+
+err_counter:
+	free_pages((unsigned long)priv->pgtable, 2);
+err_pgtable:
+	kfree(priv);
+	return -ENOMEM;
+}
+
+static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	struct list_head *pos, *n;
+	unsigned long flags;
+	int i;
+
+	WARN_ON(!list_empty(&priv->clients));
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	list_for_each_safe(pos, n, &priv->clients) {
+		struct iommu_client *client;
+
+		client = list_entry(pos, struct iommu_client, node);
+		exynos_sysmmu_disable(client->dev);
+		kfree(client);
+	}
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	for (i = 0; i < NUM_LV1ENTRIES; i++)
+		if (lv1ent_page(priv->pgtable + i))
+			kfree(__va(lv2table_base(priv->pgtable + i)));
+
+	free_pages((unsigned long)priv->pgtable, 2);
+	free_pages((unsigned long)priv->lv2entcnt, 1);
+	kfree(domain->priv);
+	domain->priv = NULL;
+}
+
+static int exynos_iommu_attach_device(struct iommu_domain *domain,
+				   struct device *dev)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	struct exynos_iommu_domain *priv = domain->priv;
+	struct iommu_client *client = NULL;
+	struct list_head *pos;
+	unsigned long flags;
+	int ret;
+
+	ret = pm_runtime_get_sync(data->sysmmu);
+	if (ret < 0)
+		return ret;
+
+	ret = 0;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	list_for_each(pos, &priv->clients) {
+		struct iommu_client *cur;
+
+		cur = list_entry(pos, struct iommu_client, node);
+		if (cur->dev == dev) {
+			client = cur;
+			break;
+		}
+	}
+
+	ret = __exynos_sysmmu_enable(data, __pa(priv->pgtable), domain);
+
+	BUG_ON((ret > 0) && (client == NULL));
+
+	if (ret == 0) {
+		BUG_ON(client);
+
+		data->client.dev = dev;
+		list_add_tail(&data->client.node, &priv->clients);
+	}
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	if (ret < 0) {
+		dev_err(dev, "%s: Failed to IOMMU with pgtable %#lx\n",
+				__func__, __pa(priv->pgtable));
+		pm_runtime_put(data->sysmmu);
+	} else if (ret > 0) {
+		dev_dbg(dev, "%s: IOMMU with pgtable 0x%lx already attached\n",
+					__func__, __pa(priv->pgtable));
+	} else {
+		dev_dbg(dev, "%s: Attached new IOMMU with pgtable 0x%lx\n",
+					__func__, __pa(priv->pgtable));
+	}
+
+	return ret;
+}
+
+static void exynos_iommu_detach_device(struct iommu_domain *domain,
+				    struct device *dev)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	struct exynos_iommu_domain *priv = domain->priv;
+	struct iommu_client *client = NULL;
+	struct list_head *pos;
+	unsigned long flags;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	list_for_each(pos, &priv->clients) {
+		struct iommu_client *cur;
+
+		cur = list_entry(pos, struct iommu_client, node);
+		if (cur->dev == dev) {
+			client = cur;
+			break;
+		}
+	}
+
+	if (client) {
+		if (exynos_sysmmu_disable(client->dev)) {
+			dev_dbg(dev, "%s: Detached IOMMU with pgtable %#lx\n",
+					__func__, __pa(priv->pgtable));
+			list_del(&client->node);
+			INIT_LIST_HEAD(&client->node);
+
+		} else {
+			dev_dbg(dev,
+				"%s: Detaching IOMMU with pgtable %#lx delayed",
+					__func__, __pa(priv->pgtable));
+		}
+	}
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	if (client)
+		pm_runtime_put(data->sysmmu);
+}
+
+static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,
+					short *pgcounter)
+{
+	if (lv1ent_fault(sent)) {
+		unsigned long *pent;
+
+		pent = kzalloc(LV2TABLE_SIZE, GFP_ATOMIC);
+		BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
+		if (!pent)
+			return NULL;
+
+		*sent = mk_lv1ent_page(__pa(pent));
+		*pgcounter = NUM_LV2ENTRIES;
+		pgtable_flush(pent, pent + NUM_LV2ENTRIES);
+		pgtable_flush(sent, sent + 1);
+	}
+
+	return page_entry(sent, iova);
+}
+
+static int lv1set_section(unsigned long *sent, phys_addr_t paddr, short *pgcnt)
+{
+	if (lv1ent_section(sent))
+		return -EADDRINUSE;
+
+	if (lv1ent_page(sent)) {
+		if (*pgcnt != NUM_LV2ENTRIES)
+			return -EADDRINUSE;
+
+		kfree(page_entry(sent, 0));
+
+		*pgcnt = 0;
+	}
+
+	*sent = mk_lv1ent_sect(paddr);
+
+	pgtable_flush(sent, sent + 1);
+
+	return 0;
+}
+
+static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
+								short *pgcnt)
+{
+	if (size == SPAGE_SIZE) {
+		if (!lv2ent_fault(pent))
+			return -EADDRINUSE;
+
+		*pent = mk_lv2ent_spage(paddr);
+		pgtable_flush(pent, pent + 1);
+		*pgcnt -= 1;
+	} else { /* size == LPAGE_SIZE */
+		int i;
+		for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
+			if (!lv2ent_fault(pent)) {
+				memset(pent, 0, sizeof(*pent) * i);
+				return -EADDRINUSE;
+			}
+
+			*pent = mk_lv2ent_lpage(paddr);
+		}
+		pgtable_flush(pent - SPAGES_PER_LPAGE, pent);
+		*pgcnt -= SPAGES_PER_LPAGE;
+	}
+
+	return 0;
+}
+
+static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova,
+			 phys_addr_t paddr, size_t size, int prot)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	unsigned long *entry;
+	unsigned long flags;
+	int ret = -ENOMEM;
+
+	BUG_ON(priv->pgtable == NULL);
+
+	spin_lock_irqsave(&priv->pgtablelock, flags);
+
+	entry = section_entry(priv->pgtable, iova);
+
+	if (size == SECT_SIZE) {
+		ret = lv1set_section(entry, paddr,
+					&priv->lv2entcnt[lv1ent_offset(iova)]);
+	} else {
+		unsigned long *pent;
+
+		pent = alloc_lv2entry(entry, iova,
+					&priv->lv2entcnt[lv1ent_offset(iova)]);
+
+		if (!pent)
+			ret = -ENOMEM;
+		else
+			ret = lv2set_page(pent, paddr, size,
+					&priv->lv2entcnt[lv1ent_offset(iova)]);
+	}
+
+	if (ret) {
+		pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n",
+							__func__, iova, size);
+	}
+
+	spin_unlock_irqrestore(&priv->pgtablelock, flags);
+
+	return ret;
+}
+
+static size_t exynos_iommu_unmap(struct iommu_domain *domain,
+					       unsigned long iova, size_t size)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	struct iommu_client *client;
+	unsigned long flags;
+	unsigned long *ent;
+
+	BUG_ON(priv->pgtable == NULL);
+
+	spin_lock_irqsave(&priv->pgtablelock, flags);
+
+	ent = section_entry(priv->pgtable, iova);
+
+	if (lv1ent_section(ent)) {
+		BUG_ON(size < SECT_SIZE);
+
+		*ent = 0;
+		pgtable_flush(ent, ent + 1);
+		size = SECT_SIZE;
+		goto done;
+	}
+
+	if (unlikely(lv1ent_fault(ent))) {
+		if (size > SECT_SIZE)
+			size = SECT_SIZE;
+		goto done;
+	}
+
+	/* lv1ent_page(sent) == true here */
+
+	ent = page_entry(ent, iova);
+
+	if (unlikely(lv2ent_fault(ent))) {
+		size = SPAGE_SIZE;
+		goto done;
+	}
+
+	if (lv2ent_small(ent)) {
+		*ent = 0;
+		size = SPAGE_SIZE;
+		priv->lv2entcnt[lv1ent_offset(iova)] += 1;
+		goto done;
+	}
+
+	/* lv1ent_large(ent) == true here */
+	BUG_ON(size < LPAGE_SIZE);
+
+	memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
+
+	size = LPAGE_SIZE;
+	priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
+done:
+	spin_unlock_irqrestore(&priv->pgtablelock, flags);
+
+	spin_lock_irqsave(&priv->lock, flags);
+	list_for_each_entry(client, &priv->clients, node)
+		sysmmu_tlb_invalidate_entry(client->dev, iova);
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+
+	return size;
+}
+
+static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
+					  unsigned long iova)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	unsigned long *entry;
+	unsigned long flags;
+	phys_addr_t phys = 0;
+
+	spin_lock_irqsave(&priv->pgtablelock, flags);
+
+	entry = section_entry(priv->pgtable, iova);
+
+	if (lv1ent_section(entry)) {
+		phys = section_phys(entry) + section_offs(iova);
+	} else if (lv1ent_page(entry)) {
+		entry = page_entry(entry, iova);
+
+		if (lv2ent_large(entry))
+			phys = lpage_phys(entry) + lpage_offs(iova);
+		else if (lv2ent_small(entry))
+			phys = spage_phys(entry) + spage_offs(iova);
+	}
+
+	spin_unlock_irqrestore(&priv->pgtablelock, flags);
+
+	return phys;
+}
+
+static struct iommu_ops exynos_iommu_ops = {
+	.domain_init = &exynos_iommu_domain_init,
+	.domain_destroy = &exynos_iommu_domain_destroy,
+	.attach_dev = &exynos_iommu_attach_device,
+	.detach_dev = &exynos_iommu_detach_device,
+	.map = &exynos_iommu_map,
+	.unmap = &exynos_iommu_unmap,
+	.iova_to_phys = &exynos_iommu_iova_to_phys,
+	.pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
+};
+
+static int __init exynos_iommu_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&exynos_sysmmu_driver);
+
+	if (ret == 0)
+		bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
+
+	return ret;
+}
+arch_initcall(exynos_iommu_init);
-- 
1.7.1



From pullip.cho at samsung.com  Fri Mar  9 07:14:59 2012
From: pullip.cho at samsung.com (Cho KyongHo)
Date: Fri, 09 Mar 2012 21:14:59 +0900
Subject: [PATCH v11 0/3] iommu/exynos: Add IOMMU/System MMU driver for Samsung
 Exynos
Message-ID: <017701ccfdee$3f7c8270$be758750$%cho@samsung.com>

These patches are successfully compiled
with little modification in
linux-samsung.git/for-next branch
You can find the git repo in
http://git.kernel.org/?p=linux/kernel/git/kgene/linux-samsung.git

Changes since v10:
- Prevent race condition between iommu_attach_device() and
   iommu_detach_device().
- Added declaration of platform device for System MMU-FIMCs
   in mach/sysmmu.h.
- Some changes on macros and type names:
   * enum EXYNOS_SYSMMU_INTERRUPT_TYPE
      -> enum exynos_sysmmu_inttype
   * Changed macro definitions for register offsets
      to look uniform.

Changes since v9:
- Split the first patch into 2 patches.
   One removes System MMU driver from arch/arm/plat- tree and
   the other modifies and adds platform device definitions in
   arch/arm/mach tree
- Some bug fixes
- Change "gsc" for Exynos4 to "fimc"

Changes since v8:
- exynos_iommu_map/unmap() just works for the page sizes
   that System MMU supports. (Joerg's comment)
- 1 platform device for 1 H/W though a multimedia accelerator
   with several System MMUs attached.
   This make controlling System MMU simpler.
- Information between System MMU and the accelerators:
   Shifted to accelerator's device structure from System MMU's

Changes since v7:
- Rebased with the recent commits of the following git branches
  * git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git/next
  * git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git/for-next
- Changed magic numbers into macros
- Setting owner of a System MMU in 'iommu' field of dev_archdata
- Verbose message in the default fault handler
- Some bug fixes.

Changes since v6:
- Totally rewrite exynos_iommu_map() and exynos_iommu_unmap() according
  to the change in iommu_map() and iommu_unmap().
- Change special slab for Lv2 page table to kmalloc().

Changes since v5:
- Relation between device and a domain become n:1 (Joerg's comment)
- Implements iommu_commit(). --> Removed

Changes since v4:
- exynos_iommu_unmap()returns unmapped size in page order
  (Ohad Ben-Cohen's comment)
- Fixed typo error of resource names
- Fixed missing #include<mach/sysmmu.h>
  in arch/arm/mach-exynos4/mach-armlex4210.c

Changes since v3:
- Used DEFINE_RES_MEM and DEFINE_RES_IRQ macros
  to define resources of System MMU (Russell King's comment)
- Fixed removal of CONFIG_S5P_SLEEP definition  (Sylwester Nawrocki's comment)

Changes since v2:
- Add lock for System MMU private data.
  And fixes the following problems pointed by Joerg Rodel:
- Fix wrong argument to kmalloc() and get_free_pages()
- Merged patches into 2 due to bisectability

Changes since v1:
Fixes of the following problems pointed by Russell King.:
 - Missing unlocking a spinlock in exynos_iommu_attach_dev().
 - atomic_t -> int in sysmmu_drvdata.activations
 - sysmmu_platdata -> sysmmu_drvdata
 - Change in error messages in irq handler
 - Removed casting in format of error message
 - omap_iommu_ops -> exynos_iommu_ops in the last patch

Patch Summary:
[PATCH v11 1/3] S5P: SYSMMU: Remove System MMU device driver
[PATCH v11 2/3] ARM: EXYNOS: Change System MMU platform device definitions
[PATCH v11 3/3] iommu/exynos: Add iommu driver for Exynos Platforms

The first patch removes the existing System MMU device driver which does not conform to IOMMU API set prepared in the kernel.
 
The second patch enhances System MMU platform device definition:
 - Removed System MMU for MDMA0 in TOP block because it is not
   used. Use MDMA2 in LCD block.
 - Removed System MMU ID. Instead, a System MMU is bound to a device
   that the System MMU is dedicated during machine initialization.
   If a device driver wants to handle System MMU, it must bind its
   device with System MMU with sysmmu_set_owner().
 - clkdev
 - Added support for Exynos5

The last patch implements IOMMU API:
- New System MMU device driver that fully implements IOMMU API.

Thanks to Kyungmin Park and Marek Szyprowski for kind review.

Diffstats:
 arch/arm/mach-exynos/Kconfig                    |   11 +-
 arch/arm/mach-exynos/Makefile                   |    2 +-
 arch/arm/mach-exynos/clock-exynos4.c            |   79 +-
 arch/arm/mach-exynos/clock-exynos4.h            |    2 +
 arch/arm/mach-exynos/clock-exynos4210.c         |   11 +
 arch/arm/mach-exynos/clock-exynos4212.c         |   28 +-
 arch/arm/mach-exynos/clock-exynos5.c            |   90 ++
 arch/arm/mach-exynos/dev-sysmmu.c               |  457 ++++++-----
 arch/arm/mach-exynos/include/mach/irqs.h        |  179 ++--
 arch/arm/mach-exynos/include/mach/map.h         |   38 +
 arch/arm/mach-exynos/include/mach/regs-clock.h  |    5 +
 arch/arm/mach-exynos/include/mach/regs-sysmmu.h |   28 -
 arch/arm/mach-exynos/include/mach/sysmmu.h      |   88 ++-
 arch/arm/mach-exynos/mach-armlex4210.c          |    1 -
 arch/arm/mach-exynos/mach-smdkv310.c            |    1 -
 arch/arm/plat-s5p/Kconfig                       |    8 -
 arch/arm/plat-s5p/Makefile                      |    1 -
 arch/arm/plat-s5p/sysmmu.c                      |  313 -------
 arch/arm/plat-samsung/include/plat/devs.h       |    1 -
 arch/arm/plat-samsung/include/plat/sysmmu.h     |   95 --
 drivers/iommu/Kconfig                           |   21 +
 drivers/iommu/Makefile                          |    1 +
 drivers/iommu/exynos-iommu.c                    | 1081 +++++++++++++++++++++++
 23 files changed, 1719 insertions(+), 822 deletions(-)



From broonie at opensource.wolfsonmicro.com  Mon Mar 12 06:57:20 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 12 Mar 2012 10:57:20 +0000
Subject: [PATCH v12] Regulator: Add Anatop regulator driver
In-Reply-To: <1331349188-14765-1-git-send-email-paul.liu@linaro.org>
References: <1331349188-14765-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120312105719.GD3110@opensource.wolfsonmicro.com>

On Sat, Mar 10, 2012 at 11:13:08AM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is an integrated regulator inside i.MX6 SoC.
> There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
> And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
> This patch adds the Anatop regulator driver.

This looks OK but doesn't apply against current regulator code due to
sorting in Kconfig and Makefile, you should always submit against
current development versions of the subsystem.  Please rebase and
resend, this will also give you an opportunity to build test against the
current subsystem :)
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From balbi at ti.com  Mon Mar 12 05:39:24 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon, 12 Mar 2012 11:39:24 +0200
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A83180F73D@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <20120305225530.GJ12083@atomide.com>
 <79CD15C6BA57404B839C016229A409A83180F73D@DBDE01.ent.ti.com>
Message-ID: <20120312093921.GA5375@legolas.emea.dhcp.ti.com>

On Fri, Mar 09, 2012 at 05:58:00PM +0000, Hiremath, Vaibhav wrote:
> On Tue, Mar 06, 2012 at 04:25:30, Tony Lindgren wrote:
> > Hi,
> > 
> > * Vaibhav Hiremath <hvaibhav at ti.com> [120119 06:01]:
> > > OMAP device has 32k-sync timer which is currently used as a
> > > clocksource in the kernel (omap2plus_defconfig).
> > > The current implementation uses compile time selection between
> > > gp-timer and 32k-sync timer, which breaks multi-omap build for
> > > the devices like AM33xx, where 32k-sync timer is not available.
> > > 
> > > So use hwmod database lookup mechanism, through which at run-time
> > > we can identify availability of 32k-sync timer on the device,
> > > else fall back to gp-timer.
> > ...
> > 
> > > --- a/arch/arm/plat-omap/counter_32k.c
> > > +++ b/arch/arm/plat-omap/counter_32k.c
> > > @@ -69,52 +69,55 @@ void read_persistent_clock(struct timespec *ts)
> > >  
> > >  int __init omap_init_clocksource_32k(void)
> > >  {
> > > -	static char err[] __initdata = KERN_ERR
> > > -			"%s: can't register clocksource!\n";
> > > -
> > > -	if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
> > > -		u32 pbase;
> > > -		unsigned long size = SZ_4K;
> > > -		void __iomem *base;
> > > -		struct clk *sync_32k_ick;
> > > -
> > > -		if (cpu_is_omap16xx()) {
> > > -			pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > > -			size = SZ_1K;
> > > -		} else if (cpu_is_omap2420())
> > > -			pbase = OMAP2420_32KSYNCT_BASE + 0x10;
> > > -		else if (cpu_is_omap2430())
> > > -			pbase = OMAP2430_32KSYNCT_BASE + 0x10;
> > > -		else if (cpu_is_omap34xx())
> > > -			pbase = OMAP3430_32KSYNCT_BASE + 0x10;
> > > -		else if (cpu_is_omap44xx())
> > > -			pbase = OMAP4430_32KSYNCT_BASE + 0x10;
> > > -		else
> > > +	u32 pbase;
> > > +	unsigned long size = SZ_4K;
> > > +	void __iomem *base;
> > > +	struct clk *sync_32k_ick;
> > > +
> > > +	if (cpu_is_omap16xx()) {
> > > +		pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > > +		size = SZ_1K;
> > > +	} else if (cpu_class_is_omap2()) {
> > > +		struct omap_hwmod *oh;
> > > +		const char *oh_name = "counter_32k";
> > > +
> > > +		oh = omap_hwmod_lookup(oh_name);
> > > +		if (!oh || oh->slaves_cnt == 0) {
> > > +			pr_err("Could not lookup %s hwmod\n", oh_name);
> > >  			return -ENODEV;
> > > +		}
> > > +		pbase = oh->slaves[0]->addr->pa_start + 0x10;
> > > +	} else {
> > > +		return -ENODEV;
> > > +	}
> > 
> > How about have separate omap1 and omap2+ init functions that
> > call a common function and passes the pbase as a parameter?
> > 
> > That way we can get rid of the cpu_is_omapxxxx tests here.
> > 
> 
> Tony,
> 
> In the morning, I replied very soon, without much thinking...
> 
> Just now I started working on the patch, I was just reviewing the code, 
> and I felt that, it is unnecessary to split the code between omap1 and 
> omap2+.
> 
> The reason is,
> 
> Currently Only OMAP16xx base-address is hardcoded with
> cpu_is_omap16xx() macro, For all other omap family of devices the
> complete information is fetched from HWDMO api's/data.

In that case, why don't you create the platform_device by hand on
arch/arm/mach-omap1/devices.c and move the omap2+ (which is based on
hwmod) to arch/arm/mach-omap2/devices.c ?

-- 
balbi
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From hunold at linuxtv.org  Mon Mar 12 06:40:15 2012
From: hunold at linuxtv.org (Michael Hunold)
Date: Mon, 12 Mar 2012 11:40:15 +0100
Subject: iMX53 and MMC_CAP_SDIO_IRQ
In-Reply-To: <20120312101037.GA2459@pengutronix.de>
References: <4F5DB793.3080904@linuxtv.org>
 <20120312101037.GA2459@pengutronix.de>
Message-ID: <4F5DD28F.50600@linuxtv.org>

Hello Wolfram,

thank you for your answer.

on 12.03.2012 11:10 Wolfram Sang said the following:
>> Probably this is a question for the Freescale people: why was the
>> "mx_sdhci" necessary at all
> 
> It probably was never necessary, it was just easier to hack on a forked
> driver, because you can't break other sdhci-users, I guess. Since large
> portions of the code are duplicated but issues have been fixed in a
> very, ahem, custom manner, this was never suitable for mainline. Back
> then, most vendors thought this is good enough. Luckily, times have
> changed a bit.

Yes, I know that thinking.

>> and why is it not necessary any more?
> 
> Because I wanted SD support in mainline, so I had to take a different
> path.

I understand.

>> Any help, hints and historical informations are highly appreciated,
>> before I start to look deeper into this problem.
> 
> They don't have a common ancestor. Just dig into both, you will
> recognize patterns, I guess.

Ok, to sum this up:

SDIO IRQs are working in mx_sdhci in the Freescale tree because it was
properly implemented and tested, obviously.

SDIO IRQs are working for sdhci in mainline probably for other
non-freescale platforms.

You fixed the generic sdhci driver in mainline to work with iMX53 to get
rid of the need for mx_sdhci, but probably never got the chance to test
if SDIO IRQs are really working.

That means, the subtle difference between mx_sdhci and sdhci to get SDIO
IRQS to work on sdhci with iMX53 has yet to be found.

> Regards,
>    Wolfram

CU
Michael.


From kumarrav at codeaurora.org  Mon Mar 12 06:32:44 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Mon, 12 Mar 2012 16:02:44 +0530
Subject: [PATCH v3 2/2] DMAEngine: Add DMAEngine driver based on old MSM DMA
 APIs
Message-ID: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>

Add DMAEngine based driver using the old MSM DMA APIs internally.
The benefit of this approach is that not all the drivers
have to get converted to DMAEngine APIs simultaneosly while
both the drivers can stay enabled in the kernel. The client
drivers using the old MSM APIs directly can now convert to
DMAEngine one by one.

Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
---
 arch/arm/mach-msm/include/mach/dma.h |   30 ++
 drivers/dma/Kconfig                  |   12 +
 drivers/dma/Makefile                 |    1 +
 drivers/dma/msm-dma.c                |  724 ++++++++++++++++++++++++++++++++++
 4 files changed, 767 insertions(+), 0 deletions(-)
 create mode 100644 drivers/dma/msm-dma.c

diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 05583f5..5a432c5 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -18,6 +18,36 @@
 #include <linux/list.h>
 #include <mach/msm_iomap.h>
 
+#define sg_dma_offset(sg)               ((sg)->offset)
+#define box_dma_row_address(box)        ((box)->dma_row_address)
+#define box_dma_row_len(box)            ((box)->dma_row_len)
+#define box_dma_row_num(box)            ((box)->dma_row_num)
+#define box_dma_row_offset(box)         ((box)->dma_row_offset)
+
+#define MSM_DMA_CMD_MASK		0x9FFF8
+#define MSM_DMA_CMD_SHIFT		0
+#define MSM_BOX_SRC_RLEN_MASK		0xFFFF
+#define MSM_BOX_SRC_RLEN_SHIFT		16
+#define MSM_BOX_SRC_RNUM_MASK		0xFFFF
+#define MSM_BOX_SRC_RNUM_SHIFT		16
+#define MSM_BOX_SRC_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_SRC_ROFFSET_SHIFT	16
+#define MSM_BOX_DST_RLEN_MASK		0xFFFF
+#define MSM_BOX_DST_RNUM_MASK		0xFFFF
+#define MSM_BOX_DST_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_MODE_CMD		0x3
+
+enum adm_flush_type {
+	ADM_FORCED_FLUSH,
+	ADM_GRACEFUL_FLUSH,
+};
+
+enum adm_dma_type {
+	ADM_SINGLE_MODE,
+	ADM_SG_MODE,
+	ADM_BOX_MODE,
+};
+
 struct msm_dmov_errdata {
 	uint32_t flush[6];
 };
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f1a2749..85d16a8 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -252,6 +252,18 @@ config EP93XX_DMA
 	help
 	  Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
 
+config MSM_DMA
+	tristate "Qualcomm MSM DMA support"
+	depends on ARCH_MSM
+	select DMA_ENGINE
+	help
+	  Support the Qualcomm DMA engine. This engine is integrated into
+	  Qualcomm chips.
+
+	  Say Y here if you have such a chipset.
+
+	  If unsure, say N.
+
 config DMA_ENGINE
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 009a222..55026d1 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
 obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
 obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
 obj-$(CONFIG_IMX_DMA) += imx-dma.o
+obj-$(CONFIG_MSM_DMA) += msm-dma.o
 obj-$(CONFIG_MXS_DMA) += mxs-dma.o
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
diff --git a/drivers/dma/msm-dma.c b/drivers/dma/msm-dma.c
new file mode 100644
index 0000000..0b47c0f
--- /dev/null
+++ b/drivers/dma/msm-dma.c
@@ -0,0 +1,724 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/dmapool.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/dma.h>
+
+#define SD3_CHAN_START			0
+#define MSM_DMOV_CRCI_COUNT		16
+#define MSM_DMA_MAX_CHANS_PER_DEVICE	16
+#define MAX_TRANSFER_LENGTH		65535
+#define NO_ERR_CHAN_STATUS		0x80000002
+#define to_msm_chan(chan) container_of(chan, struct msm_dma_chan, channel)
+
+struct msm_dma_chan {
+	int chan_id;
+	dma_cookie_t completed_cookie;
+	dma_cookie_t error_cookie;
+	spinlock_t lock;
+	struct list_head active_list;
+	struct list_head pending_list;
+	struct dma_chan channel;
+	struct dma_pool *desc_pool;
+	struct device *dev;
+	int max_len;
+	int err;
+	struct tasklet_struct tasklet;
+};
+
+struct msm_dma_device {
+	void __iomem *base;
+	struct device *dev;
+	struct dma_device common;
+	struct msm_dma_chan *chan[MSM_DMA_MAX_CHANS_PER_DEVICE];
+};
+
+struct msm_dma_desc_hw {
+	unsigned int cmd_list_ptr;
+} __aligned(8);
+
+/* Single Item Mode */
+struct adm_cmd_t {
+	unsigned int cmd_cntrl;
+	unsigned int src;
+	unsigned int dst;
+	unsigned int len;
+};
+
+struct adm_box_cmd_t {
+	uint32_t cmd_cntrl;
+	uint32_t src_row_addr;
+	uint32_t dst_row_addr;
+	uint32_t src_dst_len;
+	uint32_t num_rows;
+	uint32_t row_offset;
+};
+
+struct msm_dma_desc_sw {
+	struct msm_dma_desc_hw hw;
+	struct adm_cmd_t *vaddr_cmd;
+	struct adm_box_cmd_t *vaddr_box_cmd;
+	size_t coherent_size;
+	dma_addr_t paddr_cmd_list;
+	struct list_head node;
+	struct msm_dmov_cmd dmov_cmd;
+	struct dma_async_tx_descriptor async_tx;
+} __aligned(8);
+
+static int msm_dma_alloc_chan_resources(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+
+	/* Has this channel already been allocated? */
+	if (chan->desc_pool)
+		return 1;
+
+	/*
+	 * We need the descriptor to be aligned to 8bytes
+	 * for meeting ADM specification requirement.
+	 */
+	chan->desc_pool = dma_pool_create("msm_dma_desc_pool",
+					chan->dev,
+					sizeof(struct msm_dma_desc_sw),
+				__alignof__(struct msm_dma_desc_sw), 0);
+	if (!chan->desc_pool) {
+		dev_err(chan->dev, "unable to allocate channel %d "
+				"descriptor pool\n", chan->chan_id);
+		return -ENOMEM;
+	}
+
+	chan->completed_cookie = 1;
+	dchan->cookie = 1;
+
+	/* there is at least one descriptor free to be allocated */
+	return 1;
+}
+
+static void msm_dma_free_desc_list(struct msm_dma_chan *chan,
+						struct list_head *list)
+{
+	struct msm_dma_desc_sw *desc, *_desc;
+
+	list_for_each_entry_safe(desc, _desc, list, node) {
+		list_del(&desc->node);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	}
+}
+
+static void msm_dma_free_chan_resources(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	unsigned long flags;
+
+	dev_dbg(chan->dev, "Free all channel resources.\n");
+	spin_lock_irqsave(&chan->lock, flags);
+	msm_dma_free_desc_list(chan, &chan->active_list);
+	msm_dma_free_desc_list(chan, &chan->pending_list);
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	dma_pool_destroy(chan->desc_pool);
+	chan->desc_pool = NULL;
+}
+
+static enum dma_status msm_dma_desc_status(struct msm_dma_chan *chan,
+					struct msm_dma_desc_sw *desc)
+{
+	return dma_async_is_complete(desc->async_tx.cookie,
+					chan->completed_cookie,
+					chan->channel.cookie);
+}
+
+static void msm_chan_desc_cleanup(struct msm_dma_chan *chan)
+{
+	struct msm_dma_desc_sw *desc, *_desc;
+	unsigned long flags;
+
+	dev_dbg(chan->dev, "Cleaning completed descriptor of channel %d\n",
+							chan->chan_id);
+	spin_lock_irqsave(&chan->lock, flags);
+
+	list_for_each_entry_safe(desc, _desc, &chan->active_list, node) {
+		dma_async_tx_callback callback;
+		void *callback_param;
+
+		if (msm_dma_desc_status(chan, desc) == DMA_IN_PROGRESS)
+			break;
+
+		/* Remove from the list of running transactions */
+		list_del(&desc->node);
+
+		/* Run the link descriptor callback function */
+		callback = desc->async_tx.callback;
+		callback_param = desc->async_tx.callback_param;
+		if (callback) {
+			spin_unlock_irqrestore(&chan->lock, flags);
+			callback(callback_param);
+			spin_lock_irqsave(&chan->lock, flags);
+		}
+
+		/* Run any dependencies, then free the descriptor */
+		dma_run_dependencies(&desc->async_tx);
+		spin_unlock_irqrestore(&chan->lock, flags);
+
+		if (desc->vaddr_cmd) {
+			dma_free_coherent(chan->dev, desc->coherent_size,
+						(void *)desc->vaddr_cmd,
+							desc->paddr_cmd_list);
+		} else {
+			dma_free_coherent(chan->dev, desc->coherent_size,
+						(void *)desc->vaddr_box_cmd,
+							desc->paddr_cmd_list);
+		}
+		spin_lock_irqsave(&chan->lock, flags);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	}
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+static void dma_do_tasklet(unsigned long data)
+{
+	struct msm_dma_chan *chan = (struct msm_dma_chan *)data;
+	msm_chan_desc_cleanup(chan);
+}
+
+static void
+msm_dma_complete_func(struct msm_dmov_cmd *cmd,
+				unsigned int result,
+				struct msm_dmov_errdata *err)
+{
+	unsigned long flags;
+	struct msm_dma_desc_sw *desch = container_of(cmd,
+				struct msm_dma_desc_sw, dmov_cmd);
+	struct msm_dma_chan *chan = to_msm_chan(desch->async_tx.chan);
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if ((result != NO_ERR_CHAN_STATUS) && err)
+		chan->error_cookie = desch->async_tx.cookie;
+	chan->completed_cookie = desch->async_tx.cookie;
+
+	tasklet_schedule(&chan->tasklet);
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+/*
+ *  Passes transfer descriptors to DMA hardware.
+ */
+static void msm_dma_issue_pending(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	struct msm_dma_desc_sw *desch;
+	unsigned long flags;
+
+	if (chan->err)
+		return;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if (list_empty(&chan->pending_list))
+		goto out_unlock;
+
+	desch = list_first_entry(&chan->pending_list, struct msm_dma_desc_sw,
+									node);
+	list_del(&desch->node);
+	desch->dmov_cmd.complete_func = msm_dma_complete_func;
+	desch->dmov_cmd.execute_func = NULL;
+	desch->dmov_cmd.cmdptr = DMOV_CMD_ADDR(desch->async_tx.phys);
+	list_add_tail(&desch->node, &chan->active_list);
+	mb();
+	msm_dmov_enqueue_cmd(chan->chan_id, &desch->dmov_cmd);
+out_unlock:
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+/*
+ *  Assignes cookie for each transfer descriptor passed.
+ *  Returns
+ *	Assigend cookie for success.
+ *	Error value for failure.
+ */
+static dma_cookie_t msm_dma_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	struct msm_dma_chan *chan = to_msm_chan(tx->chan);
+	struct msm_dma_desc_sw *desc = container_of(tx,
+	struct msm_dma_desc_sw, async_tx);
+	unsigned long flags;
+	dma_cookie_t cookie = -EBUSY;
+
+	if (chan->err)
+		return cookie;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	/*
+	 * assign cookies to all of the software descriptors
+	 * that make up this transaction
+	 */
+	cookie = chan->channel.cookie;
+	cookie++;
+	if (cookie < 0)
+		cookie = DMA_MIN_COOKIE;
+
+	desc->async_tx.cookie = cookie;
+	chan->channel.cookie = cookie;
+
+	/* put this transaction onto the tail of the pending queue */
+	list_add_tail(&desc->node, &chan->pending_list);
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	return cookie;
+}
+
+/*
+ *  Returns the DMA transfer status of a particular cookie
+ */
+static enum dma_status msm_tx_status(struct dma_chan *dchan,
+					dma_cookie_t cookie,
+				struct dma_tx_state *txstate)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	dma_cookie_t last_used;
+	dma_cookie_t last_complete;
+	enum dma_status status;
+
+	last_used = dchan->cookie;
+	last_complete = chan->completed_cookie;
+
+	dma_set_tx_state(txstate, last_complete, last_used, 0);
+
+	status = dma_async_is_complete(cookie, last_complete, last_used);
+
+	if (status != DMA_IN_PROGRESS)
+		if (chan->error_cookie == cookie)
+			status = DMA_ERROR;
+
+	return status;
+}
+
+static struct msm_dma_desc_sw *msm_dma_alloc_descriptor(
+				struct msm_dma_chan *chan,
+				int cmd_cnt,
+				enum adm_dma_type mask)
+{
+	struct msm_dma_desc_sw *desc;
+	dma_addr_t pdesc_addr;
+	dma_addr_t paddr_cmd_list;
+	void *err = NULL;
+
+	desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc_addr);
+	if (!desc) {
+		dev_dbg(chan->dev, "out of memory for desc\n");
+		return ERR_CAST(desc);
+	}
+
+	memset(desc, 0, sizeof(*desc));
+	desc->async_tx.phys = pdesc_addr;
+
+	if (mask == ADM_BOX_MODE) {
+		desc->coherent_size = sizeof(struct adm_box_cmd_t);
+		desc->vaddr_box_cmd = dma_alloc_coherent(chan->dev,
+				sizeof(struct adm_box_cmd_t),
+				&paddr_cmd_list, GFP_ATOMIC);
+		if (!desc->vaddr_box_cmd) {
+			dev_dbg(chan->dev, "out of memory for desc\n");
+			err = desc->vaddr_box_cmd;
+			goto fail;
+		}
+	} else {
+		desc->coherent_size = sizeof(struct adm_cmd_t)*cmd_cnt;
+
+		desc->vaddr_cmd = dma_alloc_coherent(chan->dev,
+				sizeof(struct adm_cmd_t)*cmd_cnt,
+				&paddr_cmd_list, GFP_ATOMIC);
+
+		if (!desc->vaddr_cmd) {
+			dev_dbg(chan->dev, "out of memory for desc\n");
+			err = desc->vaddr_cmd;
+			goto fail;
+		}
+	}
+
+	dma_async_tx_descriptor_init(&desc->async_tx, &chan->channel);
+	desc->async_tx.tx_submit = msm_dma_tx_submit;
+	desc->paddr_cmd_list = paddr_cmd_list;
+	desc->hw.cmd_list_ptr = (paddr_cmd_list >> 3) | CMD_PTR_LP;
+	return desc;
+fail:
+	dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	return ERR_CAST(err);
+}
+
+/*
+ *  Prepares the transfer descriptors for SG transaction.
+ *  Returns
+ *	address of dma_async_tx_descriptor for success.
+ *	Pointer of error value for failure.
+ */
+static struct dma_async_tx_descriptor *msm_dma_prep_sg(
+		struct dma_chan *dchan,
+		struct scatterlist *dst_sg, unsigned int dst_nents,
+		struct scatterlist *src_sg, unsigned int src_nents,
+		unsigned long flags, void *context)
+{
+
+	struct msm_dma_chan *chan;
+	struct msm_dma_desc_sw *new;
+	size_t copy, len;
+	int cmd_cnt = 0;
+	int first = 0;
+	int i;
+	dma_addr_t src;
+	dma_addr_t dst;
+	struct adm_cmd_t *cmdlist_vaddr;
+	struct scatterlist *sg;
+	u32 *cmd_cntrl = context;
+
+	if (!dchan)
+		return ERR_PTR(-EINVAL);
+
+	if (dst_nents == 0 || src_nents == 0)
+		return ERR_PTR(-EINVAL);
+	if (!dst_sg || !src_sg)
+		return ERR_PTR(-EINVAL);
+
+	if (dst_nents != src_nents)
+		return ERR_PTR(-EINVAL);
+
+	chan = to_msm_chan(dchan);
+
+	cmd_cnt = src_nents;
+	for (i = 0; i < src_nents; i++) {
+		len = sg_dma_len(src_sg + i);
+		if (len != MAX_TRANSFER_LENGTH)
+			cmd_cnt += len/MAX_TRANSFER_LENGTH;
+	}
+
+	new = msm_dma_alloc_descriptor(chan, cmd_cnt, ADM_SG_MODE);
+
+	if (!new) {
+		dev_err(chan->dev,
+			"No free memory for link descriptor\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	cmdlist_vaddr = new->vaddr_cmd;
+
+	for_each_sg(src_sg, sg, src_nents, i) {
+		len = sg_dma_len(sg);
+		src = sg_dma_address(sg);
+		do {
+			copy = (len >= MAX_TRANSFER_LENGTH) ?
+						MAX_TRANSFER_LENGTH : len;
+			cmdlist_vaddr->src = src;
+			cmdlist_vaddr->len = copy;
+			cmdlist_vaddr->cmd_cntrl = *(cmd_cntrl + i) &
+							MSM_DMA_CMD_MASK;
+			if (first == 0) {
+				if (cmd_cnt == 1)
+					cmdlist_vaddr->cmd_cntrl |= CMD_LC;
+				else
+					cmdlist_vaddr->cmd_cntrl |= CMD_OCB;
+				first = 1;
+			}
+			cmdlist_vaddr++;
+			len -= copy;
+			src += copy;
+		} while (len);
+	}
+	if (cmd_cnt > 1) {
+		cmdlist_vaddr--;
+		cmdlist_vaddr->cmd_cntrl |= CMD_LC | CMD_OCU;
+	}
+
+	cmdlist_vaddr = new->vaddr_cmd;
+
+	for_each_sg(dst_sg, sg, src_nents, i) {
+		len = sg_dma_len(sg);
+		dst = sg_dma_address(sg);
+		do {
+			copy = (len >= MAX_TRANSFER_LENGTH) ?
+					MAX_TRANSFER_LENGTH : len;
+			cmdlist_vaddr->dst = dst;
+			cmdlist_vaddr++;
+			len -= copy;
+			dst += copy;
+		} while (len);
+
+	}
+
+#ifdef DEBUG
+	cmdlist_vaddr = new->vaddr_cmd;
+	i = 0;
+	do {
+		dev_dbg(chan->dev, "cmd %d src 0x%x dst 0x%x len 0x%x "
+						"cntrl 0x%x\n",
+				i, cmdlist_vaddr->src, cmdlist_vaddr->dst,
+				cmdlist_vaddr->len, cmdlist_vaddr->cmd_cntrl);
+			cmdlist_vaddr++;
+	} while (!((cmdlist_vaddr-1)->cmd_cntrl & CMD_LC));
+#endif
+	new->async_tx.flags = flags;
+	new->async_tx.cookie = -EBUSY;
+
+	return &new->async_tx;
+}
+
+struct dma_async_tx_descriptor *msm_dma_prep_interleaved(struct dma_chan *dchan,
+					struct dma_interleaved_template *xt,
+					unsigned long flags, void *context)
+{
+
+	struct msm_dma_chan *chan;
+	struct msm_dma_desc_sw *new;
+	struct adm_box_cmd_t *box_cmd_vaddr;
+	u32 *cmd_cntrl = context;
+
+	if (!dchan)
+		return ERR_PTR(-EINVAL);
+
+	if (!xt)
+		return ERR_PTR(-EINVAL);
+
+	chan = to_msm_chan(dchan);
+
+	new = msm_dma_alloc_descriptor(chan, 1, ADM_BOX_MODE);
+
+	if (!new) {
+		dev_err(chan->dev,
+			"No free memory for link descriptor\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	box_cmd_vaddr = new->vaddr_box_cmd;
+
+
+	box_cmd_vaddr->src_row_addr = xt->src_start;
+	box_cmd_vaddr->dst_row_addr = xt->dst_start;
+	box_cmd_vaddr->src_dst_len =
+			((xt->sgl[0].size & MSM_BOX_SRC_RLEN_MASK) <<
+					MSM_BOX_SRC_RLEN_SHIFT) |
+				(xt->sgl[0].size & MSM_BOX_DST_RLEN_MASK);
+
+	box_cmd_vaddr->cmd_cntrl = (cmd_cntrl[0] & MSM_DMA_CMD_MASK) |
+						MSM_BOX_MODE_CMD | CMD_LC;
+
+	box_cmd_vaddr->num_rows =
+			((xt->numf & MSM_BOX_SRC_RNUM_MASK) <<
+			MSM_BOX_SRC_RNUM_SHIFT) |
+			(xt->numf & MSM_BOX_DST_RNUM_MASK);
+
+	if ((xt->src_sgl) && (xt->src_inc))
+		box_cmd_vaddr->row_offset =
+				((xt->sgl[0].size + xt->sgl[0].icg) &
+				MSM_BOX_SRC_ROFFSET_MASK) <<
+				MSM_BOX_SRC_ROFFSET_SHIFT;
+	else if ((!xt->src_sgl) && (xt->src_inc))
+		box_cmd_vaddr->row_offset = ((xt->sgl[0].size) &
+				MSM_BOX_SRC_ROFFSET_MASK) <<
+				MSM_BOX_SRC_ROFFSET_SHIFT;
+	else
+		box_cmd_vaddr->row_offset =
+			(0 & MSM_BOX_SRC_ROFFSET_MASK) <<
+			MSM_BOX_SRC_ROFFSET_SHIFT;
+
+
+	if ((xt->dst_sgl) && (xt->dst_inc))
+		box_cmd_vaddr->row_offset |=
+			((xt->sgl[0].size + xt->sgl[0].icg) &
+			MSM_BOX_DST_ROFFSET_MASK);
+	else if ((!xt->dst_sgl) && (xt->dst_inc))
+		box_cmd_vaddr->row_offset |= ((xt->sgl[0].size) &
+					MSM_BOX_DST_ROFFSET_MASK);
+	else
+		box_cmd_vaddr->row_offset |= (0 & MSM_BOX_DST_ROFFSET_MASK);
+
+	new->async_tx.flags = flags;
+	new->async_tx.cookie = -EBUSY;
+
+	return &new->async_tx;
+}
+
+/*
+ *  Controlling the hardware channel like stopping, flushing.
+ */
+static int msm_dma_chan_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+							unsigned long arg)
+{
+	enum adm_flush_type cmd_type = arg;
+
+	if (cmd == DMA_TERMINATE_ALL) {
+		switch (cmd_type) {
+		case ADM_GRACEFUL_FLUSH:
+				msm_dmov_stop_cmd(chan->chan_id, NULL, 1);
+			break;
+		case ADM_FORCED_FLUSH:
+			/*
+			 * We treate default as forced flush
+			 * so we fall through
+			 */
+		default:
+				msm_dmov_stop_cmd(chan->chan_id, NULL, 0);
+			break;
+		}
+	}
+	return 0;
+}
+
+static void msm_dma_chan_remove(struct msm_dma_chan *chan)
+{
+	tasklet_kill(&chan->tasklet);
+	list_del(&chan->channel.device_node);
+	kfree(chan);
+}
+
+static __devinit int msm_dma_chan_probe(struct msm_dma_device *qdev,
+					int channel)
+{
+	struct msm_dma_chan *chan;
+
+	chan = kzalloc(sizeof(*chan), GFP_KERNEL);
+	if (!chan) {
+		dev_err(qdev->dev, "no free memory for DMA channels!\n");
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&chan->lock);
+	INIT_LIST_HEAD(&chan->pending_list);
+	INIT_LIST_HEAD(&chan->active_list);
+
+	chan->chan_id = channel;
+	chan->completed_cookie = 0;
+	chan->channel.cookie = 0;
+	chan->max_len = MAX_TRANSFER_LENGTH;
+	chan->err = 0;
+	qdev->chan[channel] = chan;
+	chan->channel.device = &qdev->common;
+	chan->dev = qdev->dev;
+
+	tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
+
+	list_add_tail(&chan->channel.device_node, &qdev->common.channels);
+	qdev->common.chancnt++;
+
+	return 0;
+}
+
+static int __devinit msm_dma_probe(struct platform_device *pdev)
+{
+	struct msm_dma_device *qdev;
+	int i;
+	int ret = 0;
+
+	qdev = kzalloc(sizeof(*qdev), GFP_KERNEL);
+	if (!qdev) {
+		dev_err(&pdev->dev, "Not enough memory for device\n");
+		return -ENOMEM;
+	}
+
+	qdev->dev = &pdev->dev;
+	INIT_LIST_HEAD(&qdev->common.channels);
+	qdev->common.device_alloc_chan_resources =
+				msm_dma_alloc_chan_resources;
+	qdev->common.device_free_chan_resources =
+				msm_dma_free_chan_resources;
+	dma_cap_set(DMA_SG, qdev->common.cap_mask);
+	dma_cap_set(DMA_INTERLEAVE, qdev->common.cap_mask);
+
+	qdev->common.device_prep_dma_sg = msm_dma_prep_sg;
+	qdev->common.device_prep_interleaved_dma = msm_dma_prep_interleaved;
+	qdev->common.device_issue_pending = msm_dma_issue_pending;
+	qdev->common.dev = &pdev->dev;
+	qdev->common.device_tx_status = msm_tx_status;
+	qdev->common.device_control = msm_dma_chan_control;
+
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		ret = msm_dma_chan_probe(qdev, i);
+		if (ret) {
+			dev_err(&pdev->dev, "channel %d probe failed\n", i);
+			goto chan_free;
+		}
+	}
+
+	dev_info(&pdev->dev, "registering dma device\n");
+
+	ret = dma_async_device_register(&qdev->common);
+
+	if (ret) {
+		dev_err(&pdev->dev, "Registering Dma device failed\n");
+		goto chan_free;
+	}
+
+	dev_set_drvdata(&pdev->dev, qdev);
+	return 0;
+chan_free:
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		if (qdev->chan[i])
+			msm_dma_chan_remove(qdev->chan[i]);
+	}
+	kfree(qdev);
+	return ret;
+}
+
+static int  __devexit msm_dma_remove(struct platform_device *pdev)
+{
+	struct msm_dma_device *qdev = platform_get_drvdata(pdev);
+	int i;
+
+	dma_async_device_unregister(&qdev->common);
+
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		if (qdev->chan[i])
+			msm_dma_chan_remove(qdev->chan[i]);
+	}
+
+	dev_set_drvdata(&pdev->dev, NULL);
+	kfree(qdev);
+
+	return 0;
+}
+
+static struct platform_driver msm_dma_driver = {
+	.remove = __devexit_p(msm_dma_remove),
+	.driver = {
+		.name = "msm_dma",
+		.owner = THIS_MODULE,
+	},
+};
+
+static __init int msm_dma_init(void)
+{
+	return platform_driver_probe(&msm_dma_driver, msm_dma_probe);
+}
+subsys_initcall(msm_dma_init);
+
+static void __exit msm_dma_exit(void)
+{
+	platform_driver_unregister(&msm_dma_driver);
+}
+module_exit(msm_dma_exit);
+
+MODULE_DESCRIPTION("Qualcomm DMA driver");
+MODULE_LICENSE("GPL v2");
-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From balbi at ti.com  Mon Mar 12 06:17:58 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon, 12 Mar 2012 12:17:58 +0200
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A831810E32@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <20120305225530.GJ12083@atomide.com>
 <79CD15C6BA57404B839C016229A409A83180F73D@DBDE01.ent.ti.com>
 <20120312093921.GA5375@legolas.emea.dhcp.ti.com>
 <79CD15C6BA57404B839C016229A409A831810E32@DBDE01.ent.ti.com>
Message-ID: <20120312101757.GH5375@legolas.emea.dhcp.ti.com>

Hi,

On Mon, Mar 12, 2012 at 09:48:20AM +0000, Hiremath, Vaibhav wrote:
> On Mon, Mar 12, 2012 at 15:09:24, Balbi, Felipe wrote:
> > On Fri, Mar 09, 2012 at 05:58:00PM +0000, Hiremath, Vaibhav wrote:
> > > On Tue, Mar 06, 2012 at 04:25:30, Tony Lindgren wrote:
> > > > Hi,
> > > > 
> > > > * Vaibhav Hiremath <hvaibhav at ti.com> [120119 06:01]:
> > > > > OMAP device has 32k-sync timer which is currently used as a
> > > > > clocksource in the kernel (omap2plus_defconfig).
> > > > > The current implementation uses compile time selection between
> > > > > gp-timer and 32k-sync timer, which breaks multi-omap build for
> > > > > the devices like AM33xx, where 32k-sync timer is not available.
> > > > > 
> > > > > So use hwmod database lookup mechanism, through which at run-time
> > > > > we can identify availability of 32k-sync timer on the device,
> > > > > else fall back to gp-timer.
> > > > ...
> > > > 
> > > > > --- a/arch/arm/plat-omap/counter_32k.c
> > > > > +++ b/arch/arm/plat-omap/counter_32k.c
> > > > > @@ -69,52 +69,55 @@ void read_persistent_clock(struct timespec *ts)
> > > > >  
> > > > >  int __init omap_init_clocksource_32k(void)
> > > > >  {
> > > > > -	static char err[] __initdata = KERN_ERR
> > > > > -			"%s: can't register clocksource!\n";
> > > > > -
> > > > > -	if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
> > > > > -		u32 pbase;
> > > > > -		unsigned long size = SZ_4K;
> > > > > -		void __iomem *base;
> > > > > -		struct clk *sync_32k_ick;
> > > > > -
> > > > > -		if (cpu_is_omap16xx()) {
> > > > > -			pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > > > > -			size = SZ_1K;
> > > > > -		} else if (cpu_is_omap2420())
> > > > > -			pbase = OMAP2420_32KSYNCT_BASE + 0x10;
> > > > > -		else if (cpu_is_omap2430())
> > > > > -			pbase = OMAP2430_32KSYNCT_BASE + 0x10;
> > > > > -		else if (cpu_is_omap34xx())
> > > > > -			pbase = OMAP3430_32KSYNCT_BASE + 0x10;
> > > > > -		else if (cpu_is_omap44xx())
> > > > > -			pbase = OMAP4430_32KSYNCT_BASE + 0x10;
> > > > > -		else
> > > > > +	u32 pbase;
> > > > > +	unsigned long size = SZ_4K;
> > > > > +	void __iomem *base;
> > > > > +	struct clk *sync_32k_ick;
> > > > > +
> > > > > +	if (cpu_is_omap16xx()) {
> > > > > +		pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > > > > +		size = SZ_1K;
> > > > > +	} else if (cpu_class_is_omap2()) {
> > > > > +		struct omap_hwmod *oh;
> > > > > +		const char *oh_name = "counter_32k";
> > > > > +
> > > > > +		oh = omap_hwmod_lookup(oh_name);
> > > > > +		if (!oh || oh->slaves_cnt == 0) {
> > > > > +			pr_err("Could not lookup %s hwmod\n", oh_name);
> > > > >  			return -ENODEV;
> > > > > +		}
> > > > > +		pbase = oh->slaves[0]->addr->pa_start + 0x10;
> > > > > +	} else {
> > > > > +		return -ENODEV;
> > > > > +	}
> > > > 
> > > > How about have separate omap1 and omap2+ init functions that
> > > > call a common function and passes the pbase as a parameter?
> > > > 
> > > > That way we can get rid of the cpu_is_omapxxxx tests here.
> > > > 
> > > 
> > > Tony,
> > > 
> > > In the morning, I replied very soon, without much thinking...
> > > 
> > > Just now I started working on the patch, I was just reviewing the code, 
> > > and I felt that, it is unnecessary to split the code between omap1 and 
> > > omap2+.
> > > 
> > > The reason is,
> > > 
> > > Currently Only OMAP16xx base-address is hardcoded with
> > > cpu_is_omap16xx() macro, For all other omap family of devices the
> > > complete information is fetched from HWDMO api's/data.
> > 
> > In that case, why don't you create the platform_device by hand on
> > arch/arm/mach-omap1/devices.c and move the omap2+ (which is based on
> > hwmod) to arch/arm/mach-omap2/devices.c ?
> > 
> 
> Balbi,
> 
> 32k_counter code is not a platform_device/driver, we don't build the 
> any device here. We only need hwmod data to fetch the basic information like, 
> base-address, size, etc...
> 
> And I am note sure whether we really intend to make it 
> platform_device/driver thing.

that's kinda weird... anyway, you can also pass base as argument to
omap_init_clocksource_32k()... dunno.

-- 
balbi
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From thierry.reding at avionic-design.de  Mon Mar 12 04:00:23 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Mon, 12 Mar 2012 09:00:23 +0100
Subject: [PATCH 10/11] ARM: tegra: pcie: Add MSI support
In-Reply-To: <4F59213F.6070107@wwwdotorg.org>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-11-git-send-email-thierry.reding@avionic-design.de>
 <4F59213F.6070107@wwwdotorg.org>
Message-ID: <20120312080023.GA13788@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> On 03/08/2012 07:51 AM, Thierry Reding wrote:
> > diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
> 
> > +static int tegra_pcie_enable_msi(struct platform_device *pdev)
> > +{
> > +	struct tegra_pcie_info *pcie = platform_get_drvdata(pdev);
> > +	volatile void *pages;
> > +	unsigned long base;
> > +	unsigned int msi;
> > +	int msi_base;
> > +	int err;
> > +	u32 reg;
> > +
> > +	mutex_init(&pcie->msi_lock);
> > +
> > +	msi_base = irq_alloc_descs(-1, 0, INT_PCI_MSI_NR, 0);
> > +	if (msi_base < 0) {
> > +		dev_err(&pdev->dev, "failed to allocate IRQs\n");
> > +		return msi_base;
> > +	}
> > +
> > +	pcie->msi_domain = irq_domain_add_legacy(pcie->dev->of_node,
> > +						 INT_PCI_MSI_NR, msi_base,
> > +						 0, &irq_domain_simple_ops,
> > +						 NULL);
> > +	if (!pcie->msi_domain) {
> > +		dev_err(&pdev->dev, "failed to create IRQ domain\n");
> 
> Free the IRQ descriptors in the error paths?
> 
> > +		return -ENOMEM;
> > +	}
> > +
> > +	pcie->msi_chip.name = "PCIe-MSI";
> > +	pcie->msi_chip.irq_enable = unmask_msi_irq;
> > +	pcie->msi_chip.irq_disable = mask_msi_irq;
> > +	pcie->msi_chip.irq_mask = mask_msi_irq;
> > +	pcie->msi_chip.irq_unmask = unmask_msi_irq;
> > +
> > +	for (msi = 0; msi < INT_PCI_MSI_NR; msi++) {
> > +		unsigned int irq = irq_find_mapping(pcie->msi_domain, msi);
> > +
> > +		irq_set_chip_data(irq, pcie);
> > +		irq_set_chip_and_handler(irq, &pcie->msi_chip,
> > +					 handle_simple_irq);
> > +		set_irq_flags(irq, IRQF_VALID);
> > +	}
> > +
> > +	err = platform_get_irq(pdev, 1);
> > +	if (err < 0) {
> > +		dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
> 
> Same here, and undo setting IRQF_VALID?

Does it make sense to explicitly unset the IRQF_VALID flag when the IRQ
descriptors are free'd afterwards anyway? I also think it would be necessary
to free the struct irq_domain, but I wasn't able to find any function that
does this other than just calling kfree(), which obviously wouldn't be
enough. Maybe Grant can shed some light onto this. I'm also Cc'ing Thomas
Gleixner as maintainer of the IRQ subsystem, he probably knows best how
dynamically allocated interrupts should be cleaned up.

Thierry
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From peter.ujfalusi at ti.com  Mon Mar 12 05:53:15 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 12 Mar 2012 11:53:15 +0200
Subject: [PATCH] ARM: OMAP4: clock: Add aliases for McBSP fclk clocks
In-Reply-To: <alpine.DEB.2.00.1203092355280.27395@utopia.booyaka.com>
References: <1331024133-18201-1-git-send-email-peter.ujfalusi@ti.com>
 <4F5A258F.8050704@ti.com> <20120309180027.GF12083@atomide.com>
 <alpine.DEB.2.00.1203091101400.7039@utopia.booyaka.com>
 <alpine.DEB.2.00.1203091103450.7039@utopia.booyaka.com>
 <alpine.DEB.2.00.1203092355280.27395@utopia.booyaka.com>
Message-ID: <4F5DC78B.2060203@ti.com>

Hello Paul,

On 03/10/2012 09:08 AM, Paul Walmsley wrote:
> 
> Hello P?ter
> 
> could you please try this patch instead of the clkdev change?
> 
> It is based on my 'hwmod_enable_remaining_hwmods_devel_3.4' branch, but 
> the basic idea should work on v3.3-rc6 as well.
> 
> If it works for you, please let us know and we can queue this up along 
> with the hwmod data changes.  Probably we should replace the changelog 
> also with the one from your patch, it might be a little more useful?  
> Suggestions welcome.

Unfortunately I can not test the McBSP on OMAP4 at the moment. The patch
looks good, and as far as I can see it will be perfect for OMAP4.
Thank you.
In case you need:

> From: Paul Walmsley <paul at pwsan.com>
> Date: Fri, 9 Mar 2012 23:28:28 -0700
> Subject: [PATCH] ARM: OMAP4: hwmod data: add McBSP parent clock aliases
> 
> Add optional parent clocks for the OMAP4 McBSP modules so the driver
> can switch between parent clocks.

Acked-by: Peter Ujfalusi <peter.ujfalusi at ti.com>



From broonie at opensource.wolfsonmicro.com  Sun Mar 11 16:42:33 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 11 Mar 2012 20:42:33 +0000
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators for
 v3.4
In-Reply-To: <87zkbp4wtj.fsf@ti.com>
References: <877gywjhht.fsf@ti.com> <20120308021843.GQ12083@atomide.com>
 <87399jc6cj.fsf@ti.com> <20120309003217.GB12083@atomide.com>
 <20120309114731.GA3273@opensource.wolfsonmicro.com>
 <87zkbp4wtj.fsf@ti.com>
Message-ID: <20120311204232.GC3171@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 07:29:28AM -0800, Kevin Hilman wrote:
> Mark Brown <broonie at opensource.wolfsonmicro.com> writes:

> > Absolutely not, the for-next branch is rebuilt frequently especially
> > since it includes stuff sent to Linus and he complained about bugfixes
> > merged up into development code.  What is the actual dependency here?

> The stuff is in your topic/drivers branch.  Specifically:

> ed5da2a mfd: twl-core: regulator configuration for twl6030 V1V8, V2V1 SMPS
> 77a3915 regulator: twl-regulator: Add fixed LDO for V1V8, V2V1 supply
> d64214b regulator: twl: adapt twl-regulator driver to dt
> 3e1ff1f regulator: twl6030: add support for vdd1, vdd2 and vdd3 regulators
> 1a4a805 regulator: twl4030: add support for external voltage get/set

Oh, ick.  That really is quite buried and probably depends on some of
the earlier changes too.

> > The topic branches are more or less static, though some more than
> > others.

> Is topic/drivers something stable?  If not, these are a ways back in
> that branch, maybe you make a topic/drivers-stable for us?

The branch itself is essentially stable but I'm not enthused about the
idea of merging the whole thing via the OMAP tree.  However, as Linus
has released an -rc7 I should pull some stuff out of there and send
fixes to him so I've created a topic/twl so let's just rebase.

> > In general you should warn people if you've got a dependency on their
> > tree, it makes life easier.

> Yeah, I should've raised this when the original series were posted.  The
> arch stuff and drivers/regulator stuff were posted all together, but you
> picked out the regulator stuff and I picked up the rest.  

Actually IIRC by the time I applied this the ARM changes had been
totally deteched from the regulator stuff - Tero was sending just the
regulator patch by itself and I actually applied the patch it was part
of a twl regulator series Rajendra put together after I got fed up with
the number of people sending me incompatible changes without talking to
each other.  I'd completely forgotten about any arch/arm stuff.

This sort of issue is becoming far too common with the OMAP stuff, there
needs to be a much greater awareness of the need to coordinate both
between trees and with multiple people working on the same code.

The following changes since commit dcd6c92267155e70a94b3927bce681ce74b80d1f:

  Linux 3.3-rc1 (2012-01-19 15:04:48 -0800)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git tags/topic/twl

for you to fetch changes up to 46eda3e96a65b378041c79c51ff2e02009f7e2d0:

  mfd: twl-core: regulator configuration for twl6030 V1V8, V2V1 SMPS (2012-03-11 20:09:26 +0000)

----------------------------------------------------------------
TWL specific changes, cross-merged with OMAP due to arch/arm wanting to
use the new ability to override the voltage set and get operations to
support the in-CPU voltage management.  The other changes are minor
fixes, the addition of a few new regulators and device tree support.

----------------------------------------------------------------
Laxman Dewangan (1):
      regulator: twl6030: Fix voltage selection logic

Peter Ujfalusi (2):
      regulator: twl-regulator: Add fixed LDO for V1V8, V2V1 supply
      mfd: twl-core: regulator configuration for twl6030 V1V8, V2V1 SMPS

Rajendra Nayak (1):
      regulator: twl: adapt twl-regulator driver to dt

Tero Kristo (2):
      regulator: twl4030: add support for external voltage get/set
      regulator: twl6030: add support for vdd1, vdd2 and vdd3 regulators

 .../bindings/regulator/twl-regulator.txt           |   68 ++++
 drivers/mfd/twl-core.c                             |   41 +++-
 drivers/regulator/twl-regulator.c                  |  327 +++++++++++++++-----
 include/linux/i2c/twl.h                            |   14 +-
 4 files changed, 366 insertions(+), 84 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/twl-regulator.txt
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From shawn.guo at linaro.org  Mon Mar 12 07:58:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 12 Mar 2012 19:58:56 +0800
Subject: [PATCH v4 09/10] ASoC: fsl: let fsl_ssi work with imx pcm and machine
 drivers
In-Reply-To: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331553537-19789-10-git-send-email-shawn.guo@linaro.org>

Makes necessary changes on fsl_ssi to let it work with imx pcm and
machine drivers.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |   64 +++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 64 insertions(+), 0 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 0192c02..3cf23e5 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -28,6 +28,7 @@
 #include <sound/soc.h>
 
 #include "fsl_ssi.h"
+#include "imx-pcm.h"
 
 #ifdef PPC
 #define read_ssi(addr)			 in_be32(addr)
@@ -116,6 +117,11 @@ struct fsl_ssi_private {
 	struct device_attribute dev_attr;
 	struct platform_device *pdev;
 
+	int ssi_on_imx;
+	struct platform_device *imx_pcm_pdev;
+	struct imx_pcm_dma_params dma_params_tx;
+	struct imx_pcm_dma_params dma_params_rx;
+
 	struct {
 		unsigned int rfrc;
 		unsigned int tfrc;
@@ -413,6 +419,12 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		ssi_private->second_stream = substream;
 	}
 
+	if (ssi_private->ssi_on_imx)
+		snd_soc_dai_set_dma_data(dai, substream,
+			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+				&ssi_private->dma_params_tx :
+				&ssi_private->dma_params_rx);
+
 	return 0;
 }
 
@@ -706,6 +718,35 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
                 /* Older 8610 DTs didn't have the fifo-depth property */
 		ssi_private->fifo_depth = 8;
 
+	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
+		u32 dma_events[2];
+		ssi_private->ssi_on_imx = 1;
+		/*
+		 * We have burstsize be "fifo_depth - 2" to match the SSI
+		 * watermark setting in fsl_ssi_startup().
+		 */
+		ssi_private->dma_params_tx.burstsize =
+			ssi_private->fifo_depth - 2;
+		ssi_private->dma_params_rx.burstsize =
+			ssi_private->fifo_depth - 2;
+		ssi_private->dma_params_tx.dma_addr =
+			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
+		ssi_private->dma_params_rx.dma_addr =
+			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
+		/*
+		 * TODO: This is a temporary solution and should be changed
+		 * to use generic DMA binding later when the helplers get in.
+		 */
+		ret = of_property_read_u32_array(pdev->dev.of_node,
+					"fsl,ssi-dma-events", dma_events, 2);
+		if (ret) {
+			dev_err(&pdev->dev, "could not get dma events\n");
+			goto error_irq;
+		}
+		ssi_private->dma_params_tx.dma = dma_events[0];
+		ssi_private->dma_params_rx.dma = dma_events[1];
+	}
+
 	/* Initialize the the device_attribute structure */
 	dev_attr = &ssi_private->dev_attr;
 	sysfs_attr_init(&dev_attr->attr);
@@ -729,6 +770,24 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 		goto error_dev;
 	}
 
+	/*
+	 * In case of imx, the machine driver uses new binding which does
+	 * not require SSI driver to trigger machine driver's probe, but
+	 * the pcm device needs to be registered here.
+	 */
+	if (ssi_private->ssi_on_imx) {
+		ssi_private->imx_pcm_pdev =
+			platform_device_register_simple("imx-pcm-audio",
+							-1, NULL, 0);
+		if (IS_ERR(ssi_private->imx_pcm_pdev)) {
+			ret = PTR_ERR(ssi_private->imx_pcm_pdev);
+			goto error_dev;
+		} else {
+			/* success for imx */
+			return 0;
+		}
+	}
+
 	/* Trigger the machine driver's probe function.  The platform driver
 	 * name of the machine driver is taken from /compatible property of the
 	 * device tree.  We also pass the address of the CPU DAI driver
@@ -754,6 +813,8 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 
 error_dai:
 	snd_soc_unregister_dai(&pdev->dev);
+	if (ssi_private->ssi_on_imx)
+		platform_device_unregister(ssi_private->imx_pcm_pdev);
 
 error_dev:
 	dev_set_drvdata(&pdev->dev, NULL);
@@ -780,6 +841,8 @@ static int fsl_ssi_remove(struct platform_device *pdev)
 
 	platform_device_unregister(ssi_private->pdev);
 	snd_soc_unregister_dai(&pdev->dev);
+	if (ssi_private->ssi_on_imx)
+		platform_device_unregister(ssi_private->imx_pcm_pdev);
 	device_remove_file(&pdev->dev, &ssi_private->dev_attr);
 
 	free_irq(ssi_private->irq, ssi_private);
@@ -793,6 +856,7 @@ static int fsl_ssi_remove(struct platform_device *pdev)
 
 static const struct of_device_id fsl_ssi_ids[] = {
 	{ .compatible = "fsl,mpc8610-ssi", },
+	{ .compatible = "fsl,imx21-ssi", },
 	{}
 };
 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
-- 
1.7.5.4



From viresh.kumar at st.com  Mon Mar 12 00:22:08 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:08 +0530
Subject: [PATCH V2 13/22] watchdog/mpcore_wdt: disable wdt in suspend only if
 it is busy
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <6e7bfa62de432452eb6b814e92a9045ea9e6d0c9.1331524811.git.viresh.kumar@st.com>

We don't need to call mpcore_wdt_stop() in suspend, if wdt is not BUSY. So, call
mpcore_wdt_stop() conditionally in suspend.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 3f47b7e..7ded2a0 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -260,7 +260,9 @@ static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
 static int mpcore_wdt_suspend(struct device *dev)
 {
 	struct mpcore_wdt *wdt = dev_get_drvdata(dev);
-	mpcore_wdt_stop(&wdt->wdd);	/* Turn the WDT off */
+
+	if (is_wdd_active(&wdt->wdd))
+		mpcore_wdt_stop(&wdt->wdd);	/* Turn the WDT off */
 
 	return 0;
 }
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:21:55 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:51:55 +0530
Subject: [PATCH V2 00/22] watchdog: ARM watchdogs: sp805 & mpcore updates &
 fixes
Message-ID: <cover.1331524811.git.viresh.kumar@st.com>

Hello,

This patchset contains fixes and updates for ARM watchdog drivers sp805 and
mpcore.

Changes since V1:
- Included patches for sp805 driver.
- Removed: wdt->clk = NULL from mpcore driver, and use IS_ERR() to check if
  clock is supported or not.
- Adapted to watchdog core for both the drivers.
- two patches for watchdog core added
- add patch to use __raw_readl{writel} instead of readl{writel}
- taken care of few more review comments.

Changes are mentioned in following patch list:

watchdog/mpcore: updates & fixes
Viresh Kumar (22):
  watchdog: Add is_wdt_active() routine
  watchdog: Add support for WDIOC_GETTIMELEFT IOCTL in watchdog core
  watchdog/mpcore_wdt: Rename dev to pdev for pointing to struct
    platform_device
  watchdog/mpcore_wdt: Use devm routines
  watchdog/mpcore_wdt: Allow platform_get_irq() to fail
  watchdog/mpcore_wdt: convert to watchdog core
  watchdog/mpcore_wdt: Fix multiline comments
  watchdog/mpcore_wdt: Arrange #includes in alphabetical order
  watchdog/mpcore_wdt: Set default heartbeat in probe instead of init
  watchdog/mpcore_wdt: Use dev_(crit, err, info) instead of dev_printk
  watchdog/mpcore_wdt: convert to use module_platform_driver()
  watchdog/mpcore_wdt: Add support for dev_pm_ops interface
  watchdog/mpcore_wdt: disable wdt in suspend only if it is busy
  watchdog/mpcore_wdt: replace (__raw_)readl/writel with lighter
    *_relaxed variants
  watchdog/mpcore_wdt: Add support for WDIOC_GETBOOTSTATUS IOCTL
  watchdog/mpcore_wdt: Add clock framework support
  watchdog/mpcore_wdt: use correct clk_rate to program timeout
  watchdog/sp805: Fix documentation style comment
  watchdog/sp805: replace readl/writel with lighter _relaxed variants
  watchdog/sp805: Use devm routines
  watchdog/sp805: convert to watchdog core
  watchdog/sp805: Add clk_{un}prepare support

 .../watchdog/convert_drivers_to_kernel_api.txt     |    4 +
 Documentation/watchdog/watchdog-kernel-api.txt     |    2 +
 arch/arm/include/asm/smp_twd.h                     |   12 +
 drivers/watchdog/Kconfig                           |    2 +
 drivers/watchdog/mpcore_wdt.c                      |  573 +++++++++-----------
 drivers/watchdog/sp805_wdt.c                       |  309 ++++-------
 drivers/watchdog/via_wdt.c                         |    2 +-
 drivers/watchdog/watchdog_dev.c                    |   11 +-
 include/linux/watchdog.h                           |    7 +
 9 files changed, 408 insertions(+), 514 deletions(-)

-- 
1.7.8.110.g4cb5d



From tarun.kanti at ti.com  Mon Mar 12 16:27:03 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Tue, 13 Mar 2012 01:57:03 +0530
Subject: [PATCH v3 00/13] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <CAC83ZvJKS34Py6vVtk_Si9q3A-9CVN6v4ixNM+HJ37AATcGNPA@mail.gmail.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <878vj5y7iv.fsf@ti.com>
 <CAC83Zv+8AjCHBOJbtvSQS-URvCE5Xm9oPk9_X7h4Kz7FZ_7Otw@mail.gmail.com>
 <CAC83ZvJKS34Py6vVtk_Si9q3A-9CVN6v4ixNM+HJ37AATcGNPA@mail.gmail.com>
Message-ID: <CAC83ZvJDfDBcRU1isYaxRe-fWN8F2+QW6W5EeWWuTRcFBGpYNg@mail.gmail.com>

On Tue, Mar 13, 2012 at 1:38 AM, DebBarma, Tarun Kanti
<tarun.kanti at ti.com> wrote:
> On Tue, Mar 13, 2012 at 1:23 AM, DebBarma, Tarun Kanti
> <tarun.kanti at ti.com> wrote:
>> On Tue, Mar 13, 2012 at 12:24 AM, Kevin Hilman <khilman at ti.com> wrote:
>>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>>>
>>>> The cleanup is mostly getting rid of redundant fields in struct gpio_bank{}
>>>> as we already have them as part of bank->context now. Also, remove un-used
>>>> variable from gpio_irq_handler.
>>>>
>>>> The fixes include correction of _set_gpio_irqenable() implementation,
>>>> missing wakeup_en register update in set_gpio_wakeup(), type mismatch
>>>> of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
>>>> register update in set_gpio_dataout_() and few corrections in context
>>>> save logic.
>>>>
>>>> It is baselined on top of Kevin's following series:
>>>> gpio/omap: cleanup and runtime PM conversion for v3.4
>>>> git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/gpio/runtime-pm-cleanup
>>>>
>>>> Series is available here for reference:
>>>> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_further_cleanup_fixes
>>>
>>> This branch doesn't exist.
>> Oops... I am sorry.
>> I was in the process of updating the branch with latest comments after
>> base-lining on Grant's:
>> git://git.secretlab.ca/git/linux-2.6.git
>> Branch: gpio/next
>> Because this has all the gpio changes including Benoit's latest gpio
>> devicetree changes.
>> Should I go ahead?
> Anyways, for the time being I am updating on top of your changes as before.
> You should be able to see the branch shortly.
Please note that the branch has your following patch:
gpio/omap: fix wakeups on level-triggered GPIOs
--
Tarun

>>> Kevin
>>>


From kmpark at infradead.org  Sun Mar 11 22:38:35 2012
From: kmpark at infradead.org (Kyungmin Park)
Date: Mon, 12 Mar 2012 11:38:35 +0900
Subject: [PATCH 5/5] mmc: sdhci-s3c: setup pins using pinctrl interface
In-Reply-To: <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CAH9JG2XJ3HrQROc-_6Lq6zccgF-QZupVozXCQnXYGN7+DBnq+A@mail.gmail.com>

On 3/11/12, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> The platform specific callback to setup the sdhci pin mux and pin config
> is removed and the pinctrl subsystem interface is used to setup the
> mux and config.
>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> ---
>  drivers/mmc/host/sdhci-s3c.c |   15 +++++++++++++--
>  1 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index ea0767e..76c1c36 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -22,6 +22,7 @@
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/of_gpio.h>
> +#include <linux/pinctrl/consumer.h>
>
>  #include <linux/mmc/host.h>
>
> @@ -50,6 +51,7 @@ struct sdhci_s3c {
>  	struct platform_device	*pdev;
>  	struct resource		*ioarea;
>  	struct s3c_sdhci_platdata *pdata;
> +	struct pinctrl 		*pinctrl;
>  	unsigned int		cur_clk;
>  	int			ext_cd_irq;
>  	int			ext_cd_gpio;
> @@ -529,6 +531,9 @@ static inline struct sdhci_s3c_drv_data
> *sdhci_s3c_get_driver_data(
>  			platform_get_device_id(pdev)->driver_data;
>  }
>
> +#include <plat/map-s5p.h>
> +#include <plat/map-base.h>

Why this header files are required?
> +
>  static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>  {
>  	struct s3c_sdhci_platdata *pdata;
> @@ -538,6 +543,7 @@ static int __devinit sdhci_s3c_probe(struct
> platform_device *pdev)
>  	struct sdhci_s3c *sc;
>  	struct resource *res;
>  	int ret, irq, ptr, clks;
> +	char *pstate;
>
>  	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
>  		dev_err(dev, "no device data specified\n");
> @@ -643,8 +649,13 @@ static int __devinit sdhci_s3c_probe(struct
> platform_device *pdev)
>  	}
>
>  	/* Ensure we have minimal gpio selected CMD/CLK/Detect */
> -	if (pdata->cfg_gpio)
> -		pdata->cfg_gpio(pdev, pdata->max_width);
> +	pstate = pdata->max_width ? "sdhci-pcfg8" : "sdhci-pcfg4";
You should check pdata->max_width == 8 instead of max_width itself.
BTW if platform set the amx_width as 1. How do you handle this?

Thank you,
Kyungmin Park
> +	sc->pinctrl = pinctrl_get_select(&pdev->dev, pstate);
> +	if (IS_ERR(sc->pinctrl)) {
> +		dev_err(dev, "failed to setup pin configuration\n");
> +		ret = -ENXIO;
> +		goto err_req_regs;
> +	}
>
>  	host->hw_name = "samsung-hsmmc";
>  	host->ops = &sdhci_s3c_ops;
> --
> 1.6.6.rc2
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


From broonie at opensource.wolfsonmicro.com  Fri Mar  9 07:31:30 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 12:31:30 +0000
Subject: [PATCH v10] Regulator: Add Anatop regulator driver
In-Reply-To: <20120309095834.GM27213@game.jcrosoft.org>
References: <1331200744-5986-1-git-send-email-paul.liu@linaro.org>
 <20120308141847.GG27213@game.jcrosoft.org>
 <4F59B899.2080704@linaro.org>
 <20120309095834.GM27213@game.jcrosoft.org>
Message-ID: <20120309123130.GO3273@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 10:58:34AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:

> > I've modify the patch based on your review. However, the last one cannot
> > be made because regulator_unregister is void return.

> so we have a issue here regulator_unregister MUST return an error conde

The error handling on remove is totally irrelevant to merging this
driver.  If you want to work on changing this in the core you're more
than welcome to spend your time on it, I'm really not sure it's really
worth the time or effort for the systems we currently have, if someone
actually has a system where it becomes relevant then they can work on
it.
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From santosh.shilimkar at ti.com  Mon Mar 12 10:34:33 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Mon, 12 Mar 2012 20:04:33 +0530
Subject: [PATCH 2/2] ARM: OMAP: powerdomain: Get rid off duplicate
 pwrdm_clkdm_state_switch() API
In-Reply-To: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
References: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1331562873-29535-3-git-send-email-santosh.shilimkar@ti.com>

With patch 'ARM: OMAP: powerdomain: Wait for powerdomain transition
in pwrdm_state_switch()', the pwrdm_clkdm_state_switch() API becomes
duplicate of pwrdm_state_switch().

Get rid off duplicate pwrdm_clkdm_state_switch() and update the
users of it with pwrdm_state_switch()

Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
CC: Rajendra Nayak <rnayak at ti.com>
CC: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/clock.c       |    2 +-
 arch/arm/mach-omap2/clockdomain.c |    7 +++----
 arch/arm/mach-omap2/powerdomain.c |   10 ----------
 arch/arm/mach-omap2/powerdomain.h |    1 -
 4 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index f57ed5b..77db067 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -439,7 +439,7 @@ void omap2_clk_disable_unused(struct clk *clk)
 		clk->ops->disable(clk);
 	}
 	if (clk->clkdm != NULL)
-		pwrdm_clkdm_state_switch(clk->clkdm);
+		pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index ad07689..8664f5a 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -840,7 +840,7 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
 	spin_lock_irqsave(&clkdm->lock, flags);
 	clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
 	arch_clkdm->clkdm_allow_idle(clkdm);
-	pwrdm_clkdm_state_switch(clkdm);
+	pwrdm_state_switch(clkdm->pwrdm.ptr);
 	spin_unlock_irqrestore(&clkdm->lock, flags);
 }
 
@@ -924,8 +924,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
 
 	spin_lock_irqsave(&clkdm->lock, flags);
 	arch_clkdm->clkdm_clk_enable(clkdm);
-	pwrdm_wait_transition(clkdm->pwrdm.ptr);
-	pwrdm_clkdm_state_switch(clkdm);
+	pwrdm_state_switch(clkdm->pwrdm.ptr);
 	spin_unlock_irqrestore(&clkdm->lock, flags);
 
 	pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
@@ -950,7 +949,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
 
 	spin_lock_irqsave(&clkdm->lock, flags);
 	arch_clkdm->clkdm_clk_disable(clkdm);
-	pwrdm_clkdm_state_switch(clkdm);
+	pwrdm_state_switch(clkdm->pwrdm.ptr);
 	spin_unlock_irqrestore(&clkdm->lock, flags);
 
 	pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 96ad3dbe..9611490 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -981,16 +981,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm)
 	return ret;
 }
 
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
-{
-	if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
-		pwrdm_wait_transition(clkdm->pwrdm.ptr);
-		return pwrdm_state_switch(clkdm->pwrdm.ptr);
-	}
-
-	return -EINVAL;
-}
-
 int pwrdm_pre_transition(void)
 {
 	pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 0d72a8a..8f88d65 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -213,7 +213,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
 int pwrdm_wait_transition(struct powerdomain *pwrdm);
 
 int pwrdm_state_switch(struct powerdomain *pwrdm);
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
 int pwrdm_pre_transition(void);
 int pwrdm_post_transition(void);
 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
-- 
1.7.4.1



From cjb at laptop.org  Thu Mar  8 23:53:35 2012
From: cjb at laptop.org (Chris Ball)
Date: Thu, 08 Mar 2012 23:53:35 -0500
Subject: [PATCH v2 0/6] mmc: omap_hsmmc: Clean up use/abuse of pdev->id
In-Reply-To: <4F589C94.9010601@ti.com> (Rajendra Nayak's message of "Thu, 08
 Mar 2012 17:18:36 +0530")
References: <1329996409-26861-1-git-send-email-rnayak@ti.com>
 <4F476228.7060607@ti.com> <4F54714E.6080805@ti.com>
 <4F57312E.4080104@ti.com> <m2pqcoihhu.fsf@bob.laptop.org>
 <4F589C94.9010601@ti.com>
Message-ID: <m2boo6pe7k.fsf@bob.laptop.org>

Hi,

On Thu, Mar 08 2012, Rajendra Nayak wrote:
> There's just one other cleanup patch here [1] to convert all pr_* prints
> in the driver to dev_*. Would be great if you can pick that as well.
>
> Thanks,
> Rajendra
>
> [1] http://marc.info/?l=linux-mmc&m=132999677405098&w=3

Thanks, I've pushed this to mmc-next for 3.4 now too.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From mturquette at ti.com  Sun Mar 11 17:24:46 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Sun, 11 Mar 2012 14:24:46 -0700
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <20120311113414.GM3852@pengutronix.de>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
 <20120311113414.GM3852@pengutronix.de>
Message-ID: <CAJOA=zMdkLB-DCPOk=kz5mn6BK6A_swocyCHJHeGE6H7FxBbmQ@mail.gmail.com>

On Sun, Mar 11, 2012 at 4:34 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> Hi Mike,
>
> I was about to give my tested-by when I decided to test the set_rate
> function. Unfortunately this is broken for several reasons. I'll try
> to come up with a fixup series later the day.

I haven't tested clk_set_rate since V4, but I also haven't changed the
code appreciably.  I'll retest on my end also.

> On Fri, Mar 09, 2012 at 11:54:23PM -0800, Mike Turquette wrote:
>> + ? ? /* find the new rate and see if parent rate should change too */
>> + ? ? WARN_ON(!clk->ops->round_rate);
>> +
>> + ? ? new_rate = clk->ops->round_rate(clk->hw, rate, &parent_new_rate);
>
> You don't need a WARN_ON when you derefence clk->ops->round_rate anyway.

Agreed that the WARN_ON should not be there.

The v6 Documentation/clk.txt states that .round_rate is mandatory for
clocks that can adjust their rate, but I need to clarify this a bit
more.  Ideally we want to be able to call clk_set_rate on any clock
and get a changed rate (if possible) by either adjusting that clocks
rate direction (e.g. a PLL or an adjustable divider) or by propagating
__clk_set_rate up the parents (assuming of course that
CLK_SET_RATE_PARENT flag is set appropriately).

> Also, even when the current clock does not have a set_rate function it
> can still change its rate when the CLK_SET_RATE_PARENT is set.

Correct.  I'll clean this up and make the documentation a bit more
verbose on when .set_rate/.round_rate/.recalc_rate are mandatory.

>
>> +
>> + ? ? /* NOTE: pre-rate change notifications will stack */
>> + ? ? if (clk->notifier_count)
>> + ? ? ? ? ? ? ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
>> +
>> + ? ? if (ret == NOTIFY_BAD)
>> + ? ? ? ? ? ? return clk;
>> +
>> + ? ? /* speculate rate changes down the tree */
>> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node) {
>> + ? ? ? ? ? ? ret = __clk_speculate_rates(child, new_rate);
>> + ? ? ? ? ? ? if (ret == NOTIFY_BAD)
>> + ? ? ? ? ? ? ? ? ? ? return clk;
>> + ? ? }
>> +
>> + ? ? /* change the rate of this clk */
>> + ? ? if (clk->ops->set_rate)
>> + ? ? ? ? ? ? ret = clk->ops->set_rate(clk->hw, new_rate);
>
> I don't know the reason why you change the child clock before the parent
> clock, but it cannot work since this clock will change its rate based on
> the old parent rate and not the new one.

This depends on the .round_rate implementation, which I admit to
having lost some sleep over.  A clever .round_rate will request the
"intermediate" rate for a clock when propagating a request to change
the parent rate later on.  Take for instance the following:

pll @ 200MHz (locked)
    |
parent @ 100MHz (can divide by 1 or 2; currently divider is 2)
    |
child @ 25MHz (can divide by 2 or 4; currently divider is 4)

If we want child to run at 100MHz then the desirable configuration
would be to have parent divide-by-1 and child divide-by-2.  When we
call,

clk_set_rate(child, 100MHz);

Its .round_rate should return 50MHz, and &parent_new_rate should be
200MHz.  So 50MHz is an "intermediate" rate, but it gets us the
divider we want.  And in fact 50MHz reflects reality because that will
be the rate of child until the parent propagation completes and we can
adjust parent's dividers.  (this is one reason why I prefer for
pre-rate change notifiers to stack on top of each other).

So now that &parent_new_rate is > 0, __clk_set_rate will propagate the
request up and parent's .round_rate will simply return 200MHz and
leave it's own &parent_new_rate at 0.  This will change from
divide-by-2 to divide-by-1 and from this highest point in the tree we
will propagate post-rate change notifiers downstream, as part of the
recalc_rate tree walk.

I have tested this with OMAP4's CPUfreq driver and I think, while
complicated, it is a sound way to approach the problem.  Maybe the API
can be cleaned up, if you have any suggestions.

Regards,
Mike

>
> There are more things, as said I'll try to come up with a fixup series.
>
> Sascha
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |


From myungjoo.ham at samsung.com  Mon Mar 12 04:06:23 2012
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Mon, 12 Mar 2012 17:06:23 +0900
Subject: [PATCH v6 1/5] Extcon (external connector): import Android's
 switch class and modify.
In-Reply-To: <20120309124119.GV3273@opensource.wolfsonmicro.com>
References: <1328856038-21912-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-2-git-send-email-myungjoo.ham@samsung.com>
 <20120309124119.GV3273@opensource.wolfsonmicro.com>
Message-ID: <CAJ0PZbTnKf2VA-OCyVjEC7kf7mnqt04UDjDw-zqi8f7J6yJUiA@mail.gmail.com>

On Fri, Mar 9, 2012 at 9:41 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Mon, Feb 27, 2012 at 09:15:35PM +0900, MyungJoo Ham wrote:
>
>> +#ifdef CONFIG_ANDROID
>> + ? ? ? ? ? ? extcon_class = class_create(THIS_MODULE, "switch");
>> +#else /* !CONFIG_ANDROID */
>> + ? ? ? ? ? ? extcon_class = class_create(THIS_MODULE, "extcon");
>> +#endif /* CONFIG_ANDROID */
>
> This seems somewhat sad - if ANDROID is turned on the standard ABI
> vanishes. ?It'd be much nicer to do this with a symlink (or with
> symlinks within the android directory if the driver core doesn't support
> that). ?That way userspace code can be written to the new ABI and will
> work on Android systems without ifdefery.

Yes, this was the itching part.

I'll first look into creating symlinks (either /sys/class/switch -->
/sys/class/extcon or /sys/class/switch/* --> /sys/class/extcon/*).
However, I think this symbolic links are better created selectively w/
CONFIG_ANDROID.

Thanks.


Cheers!
MyungJoo.

-- 
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab, DMC Business, Samsung Electronics


From festevam at gmail.com  Sun Mar 11 10:59:40 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sun, 11 Mar 2012 11:59:40 -0300
Subject: [PATCH 2/4] Add imx3sound sound support.
In-Reply-To: <1331304916-4724-3-git-send-email-philippe.retornaz@epfl.ch>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-3-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <CAOMZO5DP4P9Lq-gH_NNtDxwf8DxVAVg9MWHKr1E3RoexOgNYnQ@mail.gmail.com>

On Fri, Mar 9, 2012 at 11:55 AM, Philippe R?tornaz
<philippe.retornaz at epfl.ch> wrote:

> --- /dev/null
> +++ b/sound/soc/imx/imx3sound-mc13783.c
> @@ -0,0 +1,141 @@
> +/*
> + * imx3sound-mc13783.c ?-- ?SoC audio for imx31_3ds based boards

Please rename this file to  "imx-mc13783.c".

mx27pdk board also has a mc13783 and will use this file.

It is not restricted to mx3 boards.

Thanks,

Fabio Estevam


From olof at lixom.net  Sat Mar 10 12:45:08 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 09:45:08 -0800
Subject: [GIT PULL] Samsung board stuff for v3.4
In-Reply-To: <4F5B748B.6050404@samsung.com>
References: <4F5B748B.6050404@samsung.com>
Message-ID: <CAOesGMjiYDFhkjS=2e+3YdPJHExupt3Wm_NS3x1XW-17eEZM=A@mail.gmail.com>

Hi,

On Sat, Mar 10, 2012 at 7:34 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Hi Arnd, Olof,
>
> Please pull regarding Samsung board patches for v3.4.
>
> Most are enabling some features(IPs) on each board and
> one is adding new board file, Samsung Mobile's TRATS board.

Given that exynos has started conversion to device tree, there should
not be any  additions of non-devicetree-probed board files being
added.

At the very least, you should move over to using DT_MACHINE instead of
MACHINE for the new board, and probe using device tree. Even better
would be if you added support for this board through mach-exynos4-dt.c
instead of adding a brand new board file.

I also see a large number of the same additions of devices, done to a
number of board files. I don't think you need to rework those patches
now, but please consider how you can make it less "churny" to add a
device on the SoC in the future without touching all board files.


If you rebase without the board file addition I can take the rest of
the branch while that part is being reworked. Please send a new pull
request with the rebased tree.


Thanks,

-Olof


From heiko at sntech.de  Mon Mar 12 15:02:33 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Mon, 12 Mar 2012 20:02:33 +0100
Subject: [PATCH 4/6] ARM: S3C24XX: Add clock-lookup entries required by
 s3c64xx-spi
In-Reply-To: <201203121959.32966.heiko@sntech.de>
References: <201203121959.32966.heiko@sntech.de>
Message-ID: <201203122002.33629.heiko@sntech.de>

Currently usable are busclk0 and busclk2.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/clock-s3c2416.c  |    1 +
 arch/arm/mach-s3c24xx/clock-s3c2443.c  |    1 +
 arch/arm/mach-s3c24xx/common-s3c2443.c |   15 ++++++++++-----
 3 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index dbc9ab4..8702ecf 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -144,6 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
+	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
 };
 
 void __init s3c2416_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index bce1cd3..bb3231d 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -181,6 +181,7 @@ static struct clk *clks[] __initdata = {
 
 static struct clk_lookup s3c2443_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
+	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
 };
 
 void __init s3c2443_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index 4604315..aeeb2be 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -424,11 +424,6 @@ static struct clk init_clocks_off[] = {
 		.enable		= s3c2443_clkcon_enable_p,
 		.ctrlbit	= S3C2443_PCLKCON_IIS,
 	}, {
-		.name		= "hsspi",
-		.parent		= &clk_p,
-		.enable		= s3c2443_clkcon_enable_p,
-		.ctrlbit	= S3C2443_PCLKCON_HSSPI,
-	}, {
 		.name		= "adc",
 		.parent		= &clk_p,
 		.enable		= s3c2443_clkcon_enable_p,
@@ -562,6 +557,14 @@ static struct clk hsmmc1_clk = {
 	.ctrlbit	= S3C2443_HCLKCON_HSMMC,
 };
 
+static struct clk hsspi_clk = {
+	.name		= "spi",
+	.devname	= "s3c64xx-spi.0",
+	.parent		= &clk_p,
+	.enable		= s3c2443_clkcon_enable_p,
+	.ctrlbit	= S3C2443_PCLKCON_HSSPI,
+};
+
 /* EPLLCON compatible enough to get on/off information */
 
 void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
@@ -612,6 +615,7 @@ static struct clk *clks[] __initdata = {
 	&clk_usb_bus,
 	&clk_armdiv,
 	&hsmmc1_clk,
+	&hsspi_clk,
 };
 
 static struct clksrc_clk *clksrcs[] __initdata = {
@@ -629,6 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
 	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
 	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
+	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
 };
 
 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
-- 
1.7.2.3



From m.szyprowski at samsung.com  Fri Mar  9 06:05:02 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 09 Mar 2012 12:05:02 +0100
Subject: [PATCH 0/3] Add support for DRM display subsystem
Message-ID: <1331291105-18152-1-git-send-email-m.szyprowski@samsung.com>

Hello,

This patch set adds support for Exysno DRM display subsystem for
Universal C210 and NURI boards. Exynos DRM driver has been merged to 3.3
kernel tree and provides unified and more powerful alternative for
s3c-fb and s5p-tv drivers.

Best regards

Marek Szyprowski
Samsung Poland R&D Center

Patch summary:

Marek Szyprowski (3):
  ARM: Exynos4: add platform device for core DRM subsystem
  ARM: Exynos4: Add DRM core device support for Universal C210 board
  ARM: Exynos4: Add DRM core support for NURI board

 arch/arm/mach-exynos/Kconfig               |    7 ++++++
 arch/arm/mach-exynos/Makefile              |    1 +
 arch/arm/mach-exynos/dev-drm.c             |   29 ++++++++++++++++++++++++++
 arch/arm/mach-exynos/mach-nuri.c           |   31 ++++++++++++++++++++++++++++
 arch/arm/mach-exynos/mach-universal_c210.c |   31 ++++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h  |    2 +
 6 files changed, 101 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/dev-drm.c

-- 
1.7.1.569.g6f426



From cjb at laptop.org  Thu Mar  8 23:43:25 2012
From: cjb at laptop.org (Chris Ball)
Date: Thu, 08 Mar 2012 23:43:25 -0500
Subject: [PATCH] mmc: omap_hsmmc: Fix Unbalanced pm_runtime_enable warning
In-Reply-To: <4F58FB25.8020602@ti.com> (Kevin Hilman's message of "Thu, 08 Mar
 2012 10:32:05 -0800")
References: <20120305234240.GQ12083@atomide.com> <87obsaio93.fsf@ti.com>
 <4F58FB25.8020602@ti.com>
Message-ID: <m2ty1ypeoi.fsf@bob.laptop.org>

Hi,

On Thu, Mar 08 2012, Kevin Hilman wrote:
>> Tony Lindgren<tony at atomide.com>  writes:
>>
>>> mmc: omap_hsmmc: Fix Unbalanced pm_runtime_enable warning
>>>
>>> Otherwise we can get following warning when re-loading the
>>> omap_hsmmc driver module when gpio_twl4030 module is not
>>> loaded:
>>>
>>> omap_hsmmc omap_hsmmc.0: Unbalanced pm_runtime_enable!
>>> omap_hsmmc omap_hsmmc.0: Unable to grab MMC CD IRQ
>>> omap_hsmmc: probe of omap_hsmmc.0 failed with error -22
>>>
>>> Signed-off-by: Tony Lindgren<tony at atomide.com>
>>> ---
>>>
>>> Kevin, maybe take a look and see if this is correct and
>>> fits into your PM branches?
>>
>> Looks right to me:
>>
>> Acked-by: Kevin Hilman<khilman at ti.com>
>>
>> But this is a fix to the driver itself, so Chris should queue this in
>> mmc-next.
>>
>> Chris, can you take this one?
>
> just checking on this to be sure it can make it for v3.4.

Thanks, I've pushed this to mmc-next for 3.4 now.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From olof at lixom.net  Sat Mar 10 13:20:41 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 10:20:41 -0800
Subject: [GIT PULL 1/4] Samsung devel for v3.4
In-Reply-To: <4F5B7C71.2090303@samsung.com>
References: <4F5B7C71.2090303@samsung.com>
Message-ID: <CAOesGMgec=KVBQJjVs3p3B2GGj9q9mwC2XCdxLNvvJL61u+f8g@mail.gmail.com>

On Sat, Mar 10, 2012 at 8:08 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Hi Arnd, Olof,
>
> This is various develop regarding Samsung stuff for v3.4.
> Please pull following:
> ?git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/devel-samsung
>
> I think, you can pull this cleanly without any conflicts.
> If any problems, please kindly let me know.


Thanks, pulled into next/soc.


-Olof


From stigge at antcom.de  Sun Mar 11 06:53:35 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 11 Mar 2012 11:53:35 +0100
Subject: [PATCH v7 0/4] USB: OHCI-HCD: Support for LPC32xx
Message-ID: <1331463219-23293-1-git-send-email-stigge@antcom.de>

These patches add support for the LPC32xx to the ohci-pnx4008 driver and make
the driver use smbus functions.

As discussed with Greg-KH on the USB mailing list, the ohci-pnx4008 driver is
first renamed to reflect its multi-platform support. The second patch also
renames the respective pnx4008_* symbols accordingly.

The third patch adds the actual lpc32xx support.

The fourth patch removes the re-coded i2c_write() by using an existing smbus
function. You can leave out this very single patch to still have the desired
LPC32xx support. It just fixes existing kernel code to only use smbus calls in
this driver.

Applies to v3.3-rc6

Since v6, i2c_write() has been removed in favour of i2c_smbus_write_byte_data()

Thanks to Wolfram Sang for reviewing!

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Roland Stigge (4):
 USB: OHCI-HCD: Rename ohci-pnx4008 to ohci-nxp
 USB: ohci-nxp: Rename symbols from pnx4008 to nxp
 USB: ohci-nxp: Support for LPC32xx
 USB: ohci-nxp: Remove i2c_write(), use smbus

 Documentation/i2c/instantiating-devices |    6 
 drivers/usb/host/ohci-hcd.c             |    6 
 drivers/usb/host/ohci-nxp.c             |  652 ++++++++++++++++++++++++++++----
 drivers/usb/host/ohci-pnx4008.c         |  453 ----------------------
 4 files changed, 596 insertions(+), 521 deletions(-)


From stigge at antcom.de  Sun Mar 11 06:16:43 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 11 Mar 2012 11:16:43 +0100
Subject: [PATCH v5 3/3] USB: ohci-nxp: Support for LPC32xx
In-Reply-To: <20120311074323.GA30894@pengutronix.de>
References: <1331408166-11607-1-git-send-email-stigge@antcom.de>
 <1331408166-11607-4-git-send-email-stigge@antcom.de>
 <20120310204955.GA14564@pengutronix.de> <4F5BD5BE.3000808@antcom.de>
 <20120311074323.GA30894@pengutronix.de>
Message-ID: <4F5C7B8B.7050508@antcom.de>

Hi,

On 11/03/12 08:43, Wolfram Sang wrote:
>>> And while we are at it: Could you also try replacing
>>> i2c_write() with i2c_smbus_write_byte_data(isp1301_i2c_client,
>>> reg, val)?
>> 
>> Interestingly now, replacing i2c_write() calls with 
>> i2c_smbus_write_byte_data() did _not_ work (hardware
>> initialization failure). I guess this is due to the differences
>> between i2c and smbus, and the hardware only handles the former
>> correctly?
> 
> Did you take into consideration that the smbus-call has (client,
> reg, val) as arguments while i2c_write has (val, reg), that is you
> have to swap the arguments?

Yes, that's it! :-)

I'll update my patch to not use i2c_write() anymore.

For the remaining i2c_write() in the current kernel driver, I will
include an additional patch to remove it completely in favour of
i2c_smbus_write_byte_data().

Thanks,

Roland


From peppe.cavallaro at st.com  Mon Mar 12 11:30:37 2012
From: peppe.cavallaro at st.com (Giuseppe CAVALLARO)
Date: Mon, 12 Mar 2012 16:30:37 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <201203121606.26926.sr@denx.de>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <4F5E0993.9020000@gmail.com> <201203121606.26926.sr@denx.de>
Message-ID: <4F5E169D.3070508@st.com>

On 3/12/2012 4:06 PM, Stefan Roese wrote:
> Hi Rob,
> 
> On Monday 12 March 2012 15:34:59 Rob Herring wrote:
>> On 03/12/2012 09:05 AM, Stefan Roese wrote:
>>> This patch adds support to configure the STMMAC ethernet driver via
>>> device-tree instead of platform_data.
>>>
>>> Currently, only the properties needed on SPEAr600 are provided. All
>>> other properties should be added once needed on other platforms.
>>>
>>> Signed-off-by: Stefan Roese <sr at denx.de>
>>> Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
>>> Cc: Viresh Kumar <viresh.kumar at st.com>
>>> ---
>>>
>>>  Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
>>>  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66
>>>  +++++++++++++++++++- 2 files changed, 103 insertions(+), 1 deletion(-)
>>>  create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/net/stmmac.txt
>>> b/Documentation/devicetree/bindings/net/stmmac.txt new file mode 100644
>>> index 0000000..386a47f
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/net/stmmac.txt
>>> @@ -0,0 +1,38 @@
>>> +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
>>> +
>>> +Required properties:
>>> +- compatible: Should be "stm,gmac"
>>
>> This is too generic. This should be 1 string per version of h/w.
> 
> Viresh, Giuseppe, can you please suggest a proper string for the SPEAr600 
> STMMAC core, including version?
>  
>> 'stm' should be 'st' according to vendor-prefixes.txt.

I'm not familiar with devicetree; maybe we should have:

"stmicro,mac100"
"stmicro,gmac"

or: st instead of stmicro if you prefer.

in fact, stmmac is for mac100 and gmac devices.

> 
> Okay.
>  
>>> +- reg: Address and length of the register set for the device
>>> +- interrupt-parent: Should be the phandle for the interrupt controller
>>> +  that services interrupts for this device
>>> +- interrupts: Should contain the STMMAC interrupts
>>> +- interrupt-names: Should contain the interrupt names "macirq"
>>> +  "eth_wake_irq" if this interrupt is supported in the "interrupts"
>>> +  property
>>
>> You should be able to tell this from the compatible string and number of
>> interrupts.
> 
> Yes. Currently the driver uses platform_get_irq_byname() to register the 
> irq's. That's why I added these properties. Is there something wrong with 
> using it this way?
>  
>>> +- phy-mode: String, operation mode of the PHY interface.
>>> +  Supported values are: "mii", "rmii", "gmii", "rgmii".
>>> +- phy-addr: MDIO address of the PHY
>>
>> This is normally probed or the mdio bus is a sub-node of the MAC node.
>> See arch/powerpc/boot/dts/mpc8377_mds.dts for an example.
> 
> Okay, I'll rework this.
> 
>>> +
>>> +Optional properties:
>>> +- stm,prog-burst-len: Specify the burst length
>>> +- stm,has-gmac: Indicates that the controller supports 1000Mbps
>>> +- stm,has-pmt: Indicates that the controller supports power management
>>
>> I think these should all be encoded by the compatible string.

and should we have all the other flags e.g. tx_coe etc?
(see stmmac.txt)

Peppe

> 
> You mean that by defining a specific compatible string (e.g.
> "st,gmac-spear600"), these settings are implicitly set? And should therefore 
> be omitted from the dts?
> 
> Thanks,
> Stefan
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 



From festevam at gmail.com  Sun Mar 11 10:13:54 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sun, 11 Mar 2012 11:13:54 -0300
Subject: [PATCH 3/4] mx31moboard: Add ssi configuration
In-Reply-To: <20120311114104.GC3233@opensource.wolfsonmicro.com>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-3-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-4-git-send-email-philippe.retornaz@epfl.ch>
 <20120311114104.GC3233@opensource.wolfsonmicro.com>
Message-ID: <CAOMZO5Ao2u71AixumSUgG8BbqL_BPYw-yKjkmZOj0ygkqLRdtw@mail.gmail.com>

Philippe,

2012/3/11 Mark Brown <broonie at opensource.wolfsonmicro.com>:
> On Fri, Mar 09, 2012 at 03:55:15PM +0100, Philippe R?tornaz wrote:
>
>> + ? ? mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT1_SSI0,
>> + ? ? ? ? ? ? MXC_AUDMUX_V2_PTCR_SYN |
>> + ? ? ? ? ? ? MXC_AUDMUX_V2_PTCR_TFSDIR |
>
> This will need to be rebased off current code, the audmux has been moved
> into sound/soc.

You can use linux-next tree as it already contains the recent audmux changes.

Thanks,

Fabio Estevam


From linux at arm.linux.org.uk  Mon Mar 12 04:32:22 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 12 Mar 2012 08:32:22 +0000
Subject: [PATCH] serial: PL011: clear pending interrupts
In-Reply-To: <1331540750-25697-1-git-send-email-linus.walleij@stericsson.com>
References: <1331540750-25697-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20120312083221.GW17370@n2100.arm.linux.org.uk>

On Mon, Mar 12, 2012 at 09:25:50AM +0100, Linus Walleij wrote:
> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
> index 6800f5f..ff3fed0 100644
> --- a/drivers/tty/serial/amba-pl011.c
> +++ b/drivers/tty/serial/amba-pl011.c
> @@ -224,6 +224,11 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap)
>  		uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
>  	}
>  

What if we really do end up receiving some characters here?

> +	/* RXIS but RXFE? Just clear the interrupt */
> +	if(unlikely(fifotaken == 0))
> +		writew(UART011_RTIS | UART011_RXIS,
> +		       uap->port.membase + UART011_ICR);


From marc at cpdesign.com.au  Sat Mar 10 20:30:01 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Sun, 11 Mar 2012 12:30:01 +1100
Subject: [PATCH v2 2/3] mfd: mc13xxx-core: Move spi specific code into
 separate module.
In-Reply-To: <1331429402-9639-1-git-send-email-marc@cpdesign.com.au>
References: <1331429402-9639-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1331429402-9639-3-git-send-email-marc@cpdesign.com.au>

All spi specific code is moved into a new module. The mc13xxx
struct moves to a new local include file by necessity.

A new config choice selects the SPI bus type support and by default is
value of SPI_MASTER to remain compatible with existing configs.

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/mfd/Kconfig        |   15 +++-
 drivers/mfd/Makefile       |    1 +
 drivers/mfd/mc13xxx-core.c |  189 +-------------------------------------------
 drivers/mfd/mc13xxx-spi.c  |  187 +++++++++++++++++++++++++++++++++++++++++++
 drivers/mfd/mc13xxx.h      |   42 ++++++++++
 5 files changed, 245 insertions(+), 189 deletions(-)
 create mode 100644 drivers/mfd/mc13xxx-spi.c
 create mode 100644 drivers/mfd/mc13xxx.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index cd13e9f..501fee5 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -577,12 +577,21 @@ config MFD_MC13XXX
 	select MFD_CORE
 	select MFD_MC13783
 	help
-	  Support for the Freescale (Atlas) PMIC and audio CODECs
-	  MC13783 and MC13892.
-	  This driver provides common support for accessing  the device,
+	  Enable support for the Freescale MC13783 and MC13892 PMICs.
+	  This driver provides common support for accessing the device,
 	  additional drivers must be enabled in order to use the
 	  functionality of the device.
 
+if MFD_MC13XXX
+
+config MFD_MC13XXX_SPI
+	tristate "MC13xxx SPI interface" if SPI_MASTER
+	default SPI_MASTER
+	help
+	  Select this if your MC13xxx is connected via an SPI bus.
+
+endif
+
 config ABX500_CORE
 	bool "ST-Ericsson ABX500 Mixed Signal Circuit register functions"
 	default y if ARCH_U300 || ARCH_U8500
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b953bab..2dc66ed 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_TWL6030_PWM)	+= twl6030-pwm.o
 obj-$(CONFIG_TWL6040_CORE)	+= twl6040-core.o twl6040-irq.o
 
 obj-$(CONFIG_MFD_MC13XXX)	+= mc13xxx-core.o
+obj-$(CONFIG_MFD_MC13XXX_SPI)	+= mc13xxx-spi.o
 
 obj-$(CONFIG_MFD_CORE)		+= mfd-core.o
 
diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index 19d94a1..4dca8bb 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -15,36 +15,13 @@
 #include <linux/platform_device.h>
 #include <linux/mutex.h>
 #include <linux/interrupt.h>
-#include <linux/spi/spi.h>
 #include <linux/mfd/core.h>
 #include <linux/mfd/mc13xxx.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
 
-enum mc13xxx_id {
-	MC13XXX_ID_MC13783,
-	MC13XXX_ID_MC13892,
-	MC13XXX_ID_INVALID,
-};
-
-struct mc13xxx {
-	struct spi_device *spidev;
-
-	struct device *dev;
-	enum mc13xxx_id ictype;
-
-	struct mutex lock;
-	int flags;
-
-	int (*read_dev)(struct mc13xxx *, unsigned int, u32 *);
-	int (*write_dev)(struct mc13xxx *, unsigned int, u32);
-
-	irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
-	void *irqdata[MC13XXX_NUM_IRQ];
-
-	int adcflags;
-};
+#include "mc13xxx.h"
 
 #define MC13XXX_IRQSTAT0	0
 #define MC13XXX_IRQSTAT0_ADCDONEI	(1 << 0)
@@ -174,67 +151,6 @@ void mc13xxx_unlock(struct mc13xxx *mc13xxx)
 }
 EXPORT_SYMBOL(mc13xxx_unlock);
 
-#define MC13XXX_REGOFFSET_SHIFT 25
-static int mc13xxx_spi_reg_read(struct mc13xxx *mc13xxx,
-				unsigned int offset, u32 *val)
-{
-	struct spi_transfer t;
-	struct spi_message m;
-	int ret;
-
-	*val = offset << MC13XXX_REGOFFSET_SHIFT;
-
-	memset(&t, 0, sizeof(t));
-
-	t.tx_buf = val;
-	t.rx_buf = val;
-	t.len = sizeof(u32);
-
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	ret = spi_sync(mc13xxx->spidev, &m);
-
-	/* error in message.status implies error return from spi_sync */
-	BUG_ON(!ret && m.status);
-
-	if (ret)
-		return ret;
-
-	*val &= 0xffffff;
-
-	return 0;
-}
-
-static int mc13xxx_spi_reg_write(struct mc13xxx *mc13xxx, unsigned int offset,
-		u32 val)
-{
-	u32 buf;
-	struct spi_transfer t;
-	struct spi_message m;
-	int ret;
-
-	buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
-
-	memset(&t, 0, sizeof(t));
-
-	t.tx_buf = &buf;
-	t.rx_buf = &buf;
-	t.len = sizeof(u32);
-
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	ret = spi_sync(mc13xxx->spidev, &m);
-
-	BUG_ON(!ret && m.status);
-
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
 int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 {
 	int ret;
@@ -734,71 +650,7 @@ static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 }
 #endif
 
-static const struct spi_device_id mc13xxx_device_id[] = {
-	{
-		.name = "mc13783",
-		.driver_data = MC13XXX_ID_MC13783,
-	}, {
-		.name = "mc13892",
-		.driver_data = MC13XXX_ID_MC13892,
-	}, {
-		/* sentinel */
-	}
-};
-MODULE_DEVICE_TABLE(spi, mc13xxx_device_id);
-
-static const struct of_device_id mc13xxx_dt_ids[] = {
-	{ .compatible = "fsl,mc13783", .data = (void *) MC13XXX_ID_MC13783, },
-	{ .compatible = "fsl,mc13892", .data = (void *) MC13XXX_ID_MC13892, },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
-
-static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
-		struct mc13xxx_platform_data *pdata, int irq);
-
-static int mc13xxx_probe(struct spi_device *spi)
-{
-	const struct of_device_id *of_id;
-	struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
-	struct mc13xxx *mc13xxx;
-	struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
-	int ret;
-
-	of_id = of_match_device(mc13xxx_dt_ids, &spi->dev);
-	if (of_id)
-		sdrv->id_table = &mc13xxx_device_id[(enum mc13xxx_id) of_id->data];
-
-	mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
-	if (!mc13xxx)
-		return -ENOMEM;
-
-	dev_set_drvdata(&spi->dev, mc13xxx);
-	spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
-	spi->bits_per_word = 32;
-	spi_setup(spi);
-
-	mc13xxx->dev = &spi->dev;
-	mc13xxx->spidev = spi;
-	mc13xxx->read_dev = mc13xxx_spi_reg_read;
-	mc13xxx->write_dev = mc13xxx_spi_reg_write;
-
-	ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
-
-	if (ret) {
-		dev_set_drvdata(&spi->dev, NULL);
-	} else {
-		const struct spi_device_id *devid =
-			spi_get_device_id(mc13xxx->spidev);
-		if (!devid || devid->driver_data != mc13xxx->ictype)
-			dev_warn(mc13xxx->dev,
-				"device id doesn't match auto detection!\n");
-	}
-
-	return ret;
-}
-
-static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+int mc13xxx_common_init(struct mc13xxx *mc13xxx,
 		struct mc13xxx_platform_data *pdata, int irq)
 {
 	int ret;
@@ -862,42 +714,7 @@ err_revision:
 
 	return 0;
 }
-
-static int __devexit mc13xxx_remove(struct spi_device *spi)
-{
-	struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
-
-	free_irq(mc13xxx->spidev->irq, mc13xxx);
-
-	mfd_remove_devices(&spi->dev);
-
-	kfree(mc13xxx);
-
-	return 0;
-}
-
-static struct spi_driver mc13xxx_driver = {
-	.id_table = mc13xxx_device_id,
-	.driver = {
-		.name = "mc13xxx",
-		.owner = THIS_MODULE,
-		.of_match_table = mc13xxx_dt_ids,
-	},
-	.probe = mc13xxx_probe,
-	.remove = __devexit_p(mc13xxx_remove),
-};
-
-static int __init mc13xxx_init(void)
-{
-	return spi_register_driver(&mc13xxx_driver);
-}
-subsys_initcall(mc13xxx_init);
-
-static void __exit mc13xxx_exit(void)
-{
-	spi_unregister_driver(&mc13xxx_driver);
-}
-module_exit(mc13xxx_exit);
+EXPORT_SYMBOL_GPL(mc13xxx_common_init);
 
 MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>");
diff --git a/drivers/mfd/mc13xxx-spi.c b/drivers/mfd/mc13xxx-spi.c
new file mode 100644
index 0000000..70d352b
--- /dev/null
+++ b/drivers/mfd/mc13xxx-spi.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * loosely based on an earlier driver that has
+ * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/interrupt.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/mc13xxx.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+
+#include "mc13xxx.h"
+
+#define MC13XXX_REGOFFSET_SHIFT 25
+static int mc13xxx_spi_reg_read(struct mc13xxx *mc13xxx,
+				unsigned int offset, u32 *val)
+{
+	struct spi_transfer t;
+	struct spi_message m;
+	int ret;
+
+	*val = offset << MC13XXX_REGOFFSET_SHIFT;
+
+	memset(&t, 0, sizeof(t));
+
+	t.tx_buf = val;
+	t.rx_buf = val;
+	t.len = sizeof(u32);
+
+	spi_message_init(&m);
+	spi_message_add_tail(&t, &m);
+
+	ret = spi_sync(mc13xxx->spidev, &m);
+
+	/* error in message.status implies error return from spi_sync */
+	BUG_ON(!ret && m.status);
+
+	if (ret)
+		return ret;
+
+	*val &= 0xffffff;
+
+	return 0;
+}
+
+static int mc13xxx_spi_reg_write(struct mc13xxx *mc13xxx, unsigned int offset,
+		u32 val)
+{
+	u32 buf;
+	struct spi_transfer t;
+	struct spi_message m;
+	int ret;
+
+	buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
+
+	memset(&t, 0, sizeof(t));
+
+	t.tx_buf = &buf;
+	t.rx_buf = &buf;
+	t.len = sizeof(u32);
+
+	spi_message_init(&m);
+	spi_message_add_tail(&t, &m);
+
+	ret = spi_sync(mc13xxx->spidev, &m);
+
+	BUG_ON(!ret && m.status);
+
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct spi_device_id mc13xxx_device_id[] = {
+	{
+		.name = "mc13783",
+		.driver_data = MC13XXX_ID_MC13783,
+	}, {
+		.name = "mc13892",
+		.driver_data = MC13XXX_ID_MC13892,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(spi, mc13xxx_device_id);
+
+static const struct of_device_id mc13xxx_dt_ids[] = {
+	{ .compatible = "fsl,mc13783", .data = (void *) MC13XXX_ID_MC13783, },
+	{ .compatible = "fsl,mc13892", .data = (void *) MC13XXX_ID_MC13892, },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
+
+static int mc13xxx_spi_probe(struct spi_device *spi)
+{
+	const struct of_device_id *of_id;
+	struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
+	struct mc13xxx *mc13xxx;
+	struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
+	int ret;
+
+	of_id = of_match_device(mc13xxx_dt_ids, &spi->dev);
+	if (of_id)
+		sdrv->id_table = &mc13xxx_device_id[(enum mc13xxx_id) of_id->data];
+
+	mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
+	if (!mc13xxx)
+		return -ENOMEM;
+
+	dev_set_drvdata(&spi->dev, mc13xxx);
+	spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
+	spi->bits_per_word = 32;
+	spi_setup(spi);
+
+	mc13xxx->dev = &spi->dev;
+	mc13xxx->spidev = spi;
+	mc13xxx->read_dev = mc13xxx_spi_reg_read;
+	mc13xxx->write_dev = mc13xxx_spi_reg_write;
+
+	ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
+
+	if (ret) {
+		dev_set_drvdata(&spi->dev, NULL);
+	} else {
+		const struct spi_device_id *devid =
+			spi_get_device_id(mc13xxx->spidev);
+		if (!devid || devid->driver_data != mc13xxx->ictype)
+			dev_warn(mc13xxx->dev,
+				"device id doesn't match auto detection!\n");
+	}
+
+	return ret;
+}
+
+static int __devexit mc13xxx_spi_remove(struct spi_device *spi)
+{
+	struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
+
+	free_irq(mc13xxx->spidev->irq, mc13xxx);
+
+	mfd_remove_devices(&spi->dev);
+
+	kfree(mc13xxx);
+
+	return 0;
+}
+
+static struct spi_driver mc13xxx_spi_driver = {
+	.id_table = mc13xxx_device_id,
+	.driver = {
+		.name = "mc13xxx",
+		.bus = &spi_bus_type,
+		.owner = THIS_MODULE,
+	},
+	.probe = mc13xxx_spi_probe,
+	.remove = __devexit_p(mc13xxx_spi_remove),
+};
+
+static int __init mc13xxx_spi_init(void)
+{
+	return spi_register_driver(&mc13xxx_spi_driver);
+}
+subsys_initcall(mc13xxx_spi_init);
+
+static void __exit mc13xxx_spi_exit(void)
+{
+	spi_unregister_driver(&mc13xxx_spi_driver);
+}
+module_exit(mc13xxx_spi_exit);
+
+MODULE_DESCRIPTION("SPI driver for Freescale MC13XXX PMIC");
+MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/mc13xxx.h b/drivers/mfd/mc13xxx.h
new file mode 100644
index 0000000..fbec2d1
--- /dev/null
+++ b/drivers/mfd/mc13xxx.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2012 Creative Product Design
+ * Marc Reilly <marc at cpdesign.com.au>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#ifndef __DRIVERS_MFD_MC13XXX_H
+#define __DRIVERS_MFD_MC13XXX_H
+
+#include <linux/mutex.h>
+#include <linux/mfd/mc13xxx.h>
+
+enum mc13xxx_id {
+	MC13XXX_ID_MC13783,
+	MC13XXX_ID_MC13892,
+	MC13XXX_ID_INVALID,
+};
+
+struct mc13xxx {
+	struct spi_device *spidev;
+
+	struct device *dev;
+	enum mc13xxx_id ictype;
+
+	struct mutex lock;
+	int flags;
+
+	int (*read_dev)(struct mc13xxx *, unsigned int, u32 *);
+	int (*write_dev)(struct mc13xxx *, unsigned int, u32);
+
+	irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
+	void *irqdata[MC13XXX_NUM_IRQ];
+
+	int adcflags;
+};
+
+int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+		struct mc13xxx_platform_data *pdata, int irq);
+
+#endif /* __DRIVERS_MFD_MC13XXX_H */
-- 
1.7.3.4



From cjb at laptop.org  Thu Mar  8 23:57:16 2012
From: cjb at laptop.org (Chris Ball)
Date: Thu, 08 Mar 2012 23:57:16 -0500
Subject: [PATCH 2/2] mmc: sdhci-s3c: Enable runtime power management
In-Reply-To: <1330735602-22409-2-git-send-email-broonie@opensource.wolfsonmicro.com>
 (Mark Brown's message of "Sat, 3 Mar 2012 00:46:42 +0000")
References: <4F51697C.40408@samsung.com>
 <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1330735602-22409-2-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <m2399ipe1f.fsf@bob.laptop.org>

Hi Mark,

On Fri, Mar 02 2012, Mark Brown wrote:
> Since most of the work is already done by the core we just need to add
> runtime suspend methods and tell the PM core that runtime PM is enabled
> for this device.
>
> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---
>  drivers/mmc/host/sdhci-s3c.c |   28 ++++++++++++++++++++++++++++
>  1 files changed, 28 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index 46152d6..6926ac9 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -23,6 +23,7 @@
>  #include <linux/of.h>
>  #include <linux/of_gpio.h>
>  #include <linux/pm.h>
> +#include <linux/pm_runtime.h>
>  
>  #include <linux/mmc/host.h>
>  
> @@ -721,6 +722,11 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>  	if (pdata->host_caps2)
>  		host->mmc->caps2 |= pdata->host_caps2;
>  
> +	pm_runtime_enable(&pdev->dev);
> +	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
> +	pm_runtime_use_autosuspend(&pdev->dev);
> +	pm_suspend_ignore_children(&pdev->dev, 1);
> +
>  	ret = sdhci_add_host(host);
>  	if (ret) {
>  		dev_err(dev, "sdhci_add_host() failed\n");
> @@ -740,6 +746,8 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>  
>   err_add_host:
>  	release_resource(sc->ioarea);
> +	pm_runtime_forbid(&pdev->dev);
> +	pm_runtime_get_noresume(&pdev->dev);
>  	kfree(sc->ioarea);
>  
>   err_req_regs:
> @@ -784,6 +792,8 @@ static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
>  
>  	sdhci_remove_host(host, 1);
>  
> +	pm_runtime_disable(&pdev->dev);
> +
>  	for (ptr = 0; ptr < 3; ptr++) {
>  		if (sc->clk_bus[ptr]) {
>  			clk_disable(sc->clk_bus[ptr]);
> @@ -824,9 +834,27 @@ static int sdhci_s3c_resume(struct device *dev)
>  }
>  #endif
>  
> +#ifdef CONFIG_PM_RUNTIME
> +static int sdhci_s3c_runtime_suspend(struct device *dev)
> +{
> +	struct sdhci_host *host = dev_get_drvdata(dev);
> +
> +	return sdhci_runtime_suspend_host(host);
> +}
> +
> +static int sdhci_s3c_runtime_resume(struct device *dev)
> +{
> +	struct sdhci_host *host = dev_get_drvdata(dev);
> +
> +	return sdhci_runtime_resume_host(host);
> +}
> +#endif
> +
>  #ifdef CONFIG_PM
>  static const struct dev_pm_ops sdhci_s3c_pmops = {
>  	SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
> +	SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
> +			   NULL)
>  };
>  
>  #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)

Thanks, pushed to mmc-next for 3.4 with Jaehoon's ACK.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From philipp.zabel at gmail.com  Fri Mar  9 12:34:47 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Fri, 9 Mar 2012 18:34:47 +0100
Subject: [PATCH v2] pxa/hx4700: Fix basic suspend/resume
In-Reply-To: <1331310973.21920.YahooMailClassic@web29018.mail.ird.yahoo.com>
References: <1331310973.21920.YahooMailClassic@web29018.mail.ird.yahoo.com>
Message-ID: <CA+gwMccn+rLo2Q+z+gxboE82pmGT0ud2c1Q65PzhrGhFXLrvgw@mail.gmail.com>

Hi Paul,

On Fri, Mar 9, 2012 at 5:36 PM, Paul Parsons <lost.distance at yahoo.com> wrote:
> Basic suspend/resume is fixed by ensuring that the PGSR registers are set
> correctly before sleep mode is entered. In particular four of the active low
> resets need to be driven high while in sleep mode, otherwise the unit resets
> itself instead of suspending. Another problem was that the PCFR_GPROD bit is set
> by the HTC bootloader; this caused GPIO reset (i.e. the reset button) to fail
> immediately after returning from sleep mode.
>
> Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
> ---
>
> V2:
> Removed comment about mmc driver not resuming properly: 10 months later it does.
> Stopped using the verboten MFP_CFG_OUT().

thanks for the update.

> Changed GPIO88, GPIO72, GPIO96 from KEEP_OUTPUT to DRIVE_HIGH.

The bq24022 GPIOs (72 and 96) should stay KEEP_OUTPUT to allow
charging from the AC adapter while suspended.

> Added GPIO61, GPIO81, GPIO116 to global_gpios[].
> Assign to PCFR instead of masking it, per manual: "Write 0b0 to reserved bits".
> Rebased to linux-3.2-rc6.
>
> diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c
> --- clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c ? ?2012-03-04 01:08:09.000000000 +0000
> +++ linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c ? ?2012-03-09 16:06:31.121359005 +0000
> @@ -121,7 +121,11 @@ static unsigned long hx4700_pin_config[]
> ? ? ? ?GPIO19_SSP2_SCLK,
> ? ? ? ?GPIO86_SSP2_RXD,
> ? ? ? ?GPIO87_SSP2_TXD,
> - ? ? ? GPIO88_GPIO,
> + ? ? ? GPIO88_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ? /* TSC2046_CS */
> +
> + ? ? ? /* BQ24022 Regulator */
> + ? ? ? GPIO72_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ? /* BQ24022_nCHARGE_EN */
> + ? ? ? GPIO96_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ? /* BQ24022_ISET2 */

GPIO72_GPIO | MFP_LPM_KEEP_OUTPUT,
GPIO96_GPIO | MFP_LPM_KEEP_OUTPUT,

> ? ? ? ?/* HX4700 specific input GPIOs */
> ? ? ? ?GPIO12_GPIO, ? ?/* ASIC3_IRQ */
> @@ -134,6 +138,11 @@ static unsigned long hx4700_pin_config[]
> ? ? ? ?GPIO108_GPIO, ? /* GSM_READY */
> ? ? ? ?GPIO58_GPIO, ? ?/* TSC2046_nPENIRQ */
> ? ? ? ?GPIO66_GPIO, ? ?/* nSDIO_IRQ */
> +
> + ? ? ? GPIO61_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ? /* W3220_nRESET */
> + ? ? ? GPIO71_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ? /* ASIC3_nRESET */
> + ? ? ? GPIO81_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ? /* CPU_GP_nRESET */
> + ? ? ? GPIO116_GPIO | MFP_LPM_DRIVE_HIGH, ? ? ?/* CPU_HW_nRESET */
> ?};
>
> ?/*
> @@ -828,15 +837,20 @@ static struct gpio global_gpios[] = {
> ? ? ? ?{ GPIO110_HX4700_LCD_LVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_LVDD" },
> ? ? ? ?{ GPIO111_HX4700_LCD_AVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_AVDD" },
> ? ? ? ?{ GPIO32_HX4700_RS232_ON, ? ? ? ? GPIOF_OUT_INIT_HIGH, "RS232_ON" },
> + ? ? ? { GPIO61_HX4700_W3220_nRESET, ? ? GPIOF_OUT_INIT_HIGH, "W3220_nRESET" },
> ? ? ? ?{ GPIO71_HX4700_ASIC3_nRESET, ? ? GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
> + ? ? ? { GPIO81_HX4700_CPU_GP_nRESET, ? ?GPIOF_OUT_INIT_HIGH, "CPU_GP_nRESET" },
> ? ? ? ?{ GPIO82_HX4700_EUART_RESET, ? ? ?GPIOF_OUT_INIT_HIGH, "EUART_RESET" },
> ? ? ? ?{ GPIO105_HX4700_nIR_ON, ? ? ? ? ?GPIOF_OUT_INIT_HIGH, "nIR_EN" },
> + ? ? ? { GPIO116_HX4700_CPU_HW_nRESET, ? GPIOF_OUT_INIT_HIGH, "CPU_HW_nRESET" },
> ?};
>
> ?static void __init hx4700_init(void)
> ?{
> ? ? ? ?int ret;
>
> + ? ? ? PCFR = PCFR_GPR_EN | PCFR_OPDE;
> +
> ? ? ? ?pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
> ? ? ? ?ret = gpio_request_array(ARRAY_AND_SIZE(global_gpios));
> ? ? ? ?if (ret)

regards
Philipp


From cjb at laptop.org  Thu Mar  8 23:35:21 2012
From: cjb at laptop.org (Chris Ball)
Date: Thu, 08 Mar 2012 23:35:21 -0500
Subject: [PATCH V2 1/1] mmc: start removing enable / disable API
In-Reply-To: <1330499841-6879-2-git-send-email-adrian.hunter@intel.com>
 (Adrian Hunter's message of "Wed, 29 Feb 2012 09:17:21 +0200")
References: <1330499841-6879-1-git-send-email-adrian.hunter@intel.com>
 <1330499841-6879-2-git-send-email-adrian.hunter@intel.com>
Message-ID: <m27gyuqtme.fsf@bob.laptop.org>

Hi Adrian,

On Wed, Feb 29 2012, Adrian Hunter wrote:
> Most parts of the enable / disable API are no longer used and
> can be removed.
>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Cc: Venkatraman S <svenkatr at ti.com>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Cc: Thomas Abraham <thomas.abraham at linaro.org>
> Cc: Kyungmin Park <kyungmin.park at samsung.com>
> Cc: Sekhar Nori <nsekhar at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Signed-off-by: Adrian Hunter <adrian.hunter at intel.com>

Thanks very much, pushed to mmc-next for 3.4 (with Tested-by from
Venkatraman and Jaehoon).

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From marc at cpdesign.com.au  Sat Mar 10 20:30:02 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Sun, 11 Mar 2012 12:30:02 +1100
Subject: [PATCH v2 3/3] mfd: mc13xxx-core: Add i2c driver
In-Reply-To: <1331429402-9639-1-git-send-email-marc@cpdesign.com.au>
References: <1331429402-9639-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1331429402-9639-4-git-send-email-marc@cpdesign.com.au>

Adds support for mc13xxx family ICs connected via i2c.

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
Signed-off-by: Oskar Schirmer <oskar at scara.com>
---
 drivers/mfd/Kconfig       |    8 ++-
 drivers/mfd/Makefile      |    1 +
 drivers/mfd/mc13xxx-i2c.c |  143 +++++++++++++++++++++++++++++++++++++++++++++
 drivers/mfd/mc13xxx.h     |    5 +-
 4 files changed, 155 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mfd/mc13xxx-i2c.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 501fee5..3a039ff 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -573,7 +573,7 @@ config MFD_MC13783
 
 config MFD_MC13XXX
 	tristate "Support Freescale MC13783 and MC13892"
-	depends on SPI_MASTER
+	depends on SPI_MASTER || I2C
 	select MFD_CORE
 	select MFD_MC13783
 	help
@@ -590,6 +590,12 @@ config MFD_MC13XXX_SPI
 	help
 	  Select this if your MC13xxx is connected via an SPI bus.
 
+config MFD_MC13XXX_I2C
+	tristate "MC13xxx I2C interface" if I2C
+	default I2C
+	help
+	  Select this if your MC13xxx is connected via an I2C bus.
+
 endif
 
 config ABX500_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 2dc66ed..6d4566f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_TWL6040_CORE)	+= twl6040-core.o twl6040-irq.o
 
 obj-$(CONFIG_MFD_MC13XXX)	+= mc13xxx-core.o
 obj-$(CONFIG_MFD_MC13XXX_SPI)	+= mc13xxx-spi.o
+obj-$(CONFIG_MFD_MC13XXX_I2C)	+= mc13xxx-i2c.o
 
 obj-$(CONFIG_MFD_CORE)		+= mfd-core.o
 
diff --git a/drivers/mfd/mc13xxx-i2c.c b/drivers/mfd/mc13xxx-i2c.c
new file mode 100644
index 0000000..100c9e6
--- /dev/null
+++ b/drivers/mfd/mc13xxx-i2c.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2009-2010 Creative Product Design
+ * Marc Reilly marc at cpdesign.com.au
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/i2c.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/mc13xxx.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+
+#include "mc13xxx.h"
+
+static int mc13xxx_i2c_reg_read(struct mc13xxx *mc13xxx, unsigned int offset,
+		u32 *val)
+{
+	int ret;
+	unsigned char buf[3] = {0, 0, 0};
+
+	ret = i2c_smbus_read_i2c_block_data(mc13xxx->i2cclient,
+			offset, 3, buf);
+	*val = buf[0] << 16 | buf[1] << 8 | buf[2];
+
+	return ret == 3 ? 0 : ret;
+}
+
+static int mc13xxx_i2c_reg_write(struct mc13xxx *mc13xxx, unsigned int offset,
+		u32 val)
+{
+	int ret;
+	unsigned char buf[3];
+
+	buf[0] = (val >> 16) & 0xff;
+	buf[1] = (val >> 8) & 0xff;
+	buf[2] = val & 0xff;
+
+	ret = i2c_smbus_write_i2c_block_data(mc13xxx->i2cclient,
+			offset, 3, buf);
+
+	return ret;
+}
+
+static const struct i2c_device_id mc13xxx_i2c_device_id[] = {
+	{
+		.name = "mc13783",
+		.driver_data = MC13XXX_ID_MC13783
+	}, {
+		.name = "mc13892",
+		.driver_data = MC13XXX_ID_MC13892,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(i2c, mc13xxx_i2c_device_id);
+
+static const struct of_device_id mc13xxx_dt_ids[] = {
+	{ .compatible = "fsl,mc13783", .data = (void *) MC13XXX_ID_MC13783, },
+	{ .compatible = "fsl,mc13892", .data = (void *) MC13XXX_ID_MC13892, },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
+
+static int mc13xxx_i2c_probe(struct i2c_client *client,
+		const struct i2c_device_id *id)
+{
+	const struct of_device_id *of_id;
+	struct i2c_driver *idrv = to_i2c_driver(client->dev.driver);
+	struct mc13xxx *mc13xxx;
+	struct mc13xxx_platform_data *pdata = dev_get_platdata(&client->dev);
+	int ret;
+
+	of_id = of_match_device(mc13xxx_dt_ids, &client->dev);
+	if (of_id)
+		idrv->id_table =
+			&mc13xxx_i2c_device_id[(enum mc13xxx_id) of_id->data];
+
+	mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
+	if (!mc13xxx)
+		return -ENOMEM;
+
+	dev_set_drvdata(&client->dev, mc13xxx);
+	mc13xxx->dev = &client->dev;
+	mc13xxx->i2cclient = client;
+	mc13xxx->read_dev = mc13xxx_i2c_reg_read;
+	mc13xxx->write_dev = mc13xxx_i2c_reg_write;
+
+	ret = mc13xxx_common_init(mc13xxx, pdata, client->irq);
+
+	if (ret == 0 && (id->driver_data != mc13xxx->ictype))
+		dev_warn(mc13xxx->dev,
+				"device id doesn't match auto detection!\n");
+
+	return ret;
+}
+
+static int __devexit mc13xxx_i2c_remove(struct i2c_client *client)
+{
+	struct mc13xxx *mc13xxx = dev_get_drvdata(&client->dev);
+
+	free_irq(client->irq, mc13xxx);
+
+	mfd_remove_devices(&client->dev);
+
+	kfree(mc13xxx);
+
+	return 0;
+}
+
+static struct i2c_driver mc13xxx_i2c_driver = {
+	.id_table = mc13xxx_i2c_device_id,
+	.driver = {
+		.owner = THIS_MODULE,
+		.name = "mc13xxx",
+		.of_match_table = mc13xxx_dt_ids,
+	},
+	.probe = mc13xxx_i2c_probe,
+	.remove = __devexit_p(mc13xxx_i2c_remove),
+};
+
+static int __init mc13xxx_i2c_init(void)
+{
+	return i2c_add_driver(&mc13xxx_i2c_driver);
+}
+subsys_initcall(mc13xxx_i2c_init);
+
+static void __exit mc13xxx_i2c_exit(void)
+{
+	i2c_del_driver(&mc13xxx_i2c_driver);
+}
+module_exit(mc13xxx_i2c_exit);
+
+MODULE_DESCRIPTION("i2c driver for Freescale MC13XXX PMIC");
+MODULE_AUTHOR("Marc Reilly <marc at cpdesign.com.au");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/mc13xxx.h b/drivers/mfd/mc13xxx.h
index fbec2d1..13f83ed 100644
--- a/drivers/mfd/mc13xxx.h
+++ b/drivers/mfd/mc13xxx.h
@@ -19,7 +19,10 @@ enum mc13xxx_id {
 };
 
 struct mc13xxx {
-	struct spi_device *spidev;
+	union {
+		struct spi_device *spidev;
+		struct i2c_client *i2cclient;
+	};
 
 	struct device *dev;
 	enum mc13xxx_id ictype;
-- 
1.7.3.4



From marc at cpdesign.com.au  Sat Mar 10 20:30:00 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Sun, 11 Mar 2012 12:30:00 +1100
Subject: [PATCH v2 1/3] mfd: mc13xxx-core: Prepare for separate spi and i2c
 backends.
In-Reply-To: <1331429402-9639-1-git-send-email-marc@cpdesign.com.au>
References: <1331429402-9639-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1331429402-9639-2-git-send-email-marc@cpdesign.com.au>

This patch abstracts the bus specific operations from the driver core.
Read and write handlers are introduced and generic initialization is
consolidated into mc13xxx_comon_init. The irq member is removed because
it is unused.

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/mfd/mc13xxx-core.c |  162 ++++++++++++++++++++++++++------------------
 1 files changed, 97 insertions(+), 65 deletions(-)

diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index 7122386..19d94a1 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -22,12 +22,24 @@
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
 
+enum mc13xxx_id {
+	MC13XXX_ID_MC13783,
+	MC13XXX_ID_MC13892,
+	MC13XXX_ID_INVALID,
+};
+
 struct mc13xxx {
 	struct spi_device *spidev;
+
+	struct device *dev;
+	enum mc13xxx_id ictype;
+
 	struct mutex lock;
-	int irq;
 	int flags;
 
+	int (*read_dev)(struct mc13xxx *, unsigned int, u32 *);
+	int (*write_dev)(struct mc13xxx *, unsigned int, u32);
+
 	irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
 	void *irqdata[MC13XXX_NUM_IRQ];
 
@@ -144,36 +156,32 @@ struct mc13xxx {
 void mc13xxx_lock(struct mc13xxx *mc13xxx)
 {
 	if (!mutex_trylock(&mc13xxx->lock)) {
-		dev_dbg(&mc13xxx->spidev->dev, "wait for %s from %pf\n",
+		dev_dbg(mc13xxx->dev, "wait for %s from %pf\n",
 				__func__, __builtin_return_address(0));
 
 		mutex_lock(&mc13xxx->lock);
 	}
-	dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
+	dev_dbg(mc13xxx->dev, "%s from %pf\n",
 			__func__, __builtin_return_address(0));
 }
 EXPORT_SYMBOL(mc13xxx_lock);
 
 void mc13xxx_unlock(struct mc13xxx *mc13xxx)
 {
-	dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
+	dev_dbg(mc13xxx->dev, "%s from %pf\n",
 			__func__, __builtin_return_address(0));
 	mutex_unlock(&mc13xxx->lock);
 }
 EXPORT_SYMBOL(mc13xxx_unlock);
 
 #define MC13XXX_REGOFFSET_SHIFT 25
-int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
+static int mc13xxx_spi_reg_read(struct mc13xxx *mc13xxx,
+				unsigned int offset, u32 *val)
 {
 	struct spi_transfer t;
 	struct spi_message m;
 	int ret;
 
-	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
-
-	if (offset > MC13XXX_NUMREGS)
-		return -EINVAL;
-
 	*val = offset << MC13XXX_REGOFFSET_SHIFT;
 
 	memset(&t, 0, sizeof(t));
@@ -195,26 +203,17 @@ int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 
 	*val &= 0xffffff;
 
-	dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
-
 	return 0;
 }
-EXPORT_SYMBOL(mc13xxx_reg_read);
 
-int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
+static int mc13xxx_spi_reg_write(struct mc13xxx *mc13xxx, unsigned int offset,
+		u32 val)
 {
 	u32 buf;
 	struct spi_transfer t;
 	struct spi_message m;
 	int ret;
 
-	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
-
-	dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
-
-	if (offset > MC13XXX_NUMREGS || val > 0xffffff)
-		return -EINVAL;
-
 	buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
 
 	memset(&t, 0, sizeof(t));
@@ -235,6 +234,34 @@ int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
 
 	return 0;
 }
+
+int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
+{
+	int ret;
+
+	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
+
+	if (offset > MC13XXX_NUMREGS)
+		return -EINVAL;
+
+	ret = mc13xxx->read_dev(mc13xxx, offset, val);
+	dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
+
+	return ret;
+}
+EXPORT_SYMBOL(mc13xxx_reg_read);
+
+int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
+{
+	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
+
+	dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
+
+	if (offset > MC13XXX_NUMREGS || val > 0xffffff)
+		return -EINVAL;
+
+	return mc13xxx->write_dev(mc13xxx, offset, val);
+}
 EXPORT_SYMBOL(mc13xxx_reg_write);
 
 int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
@@ -439,7 +466,7 @@ static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
 			if (handled == IRQ_HANDLED)
 				num_handled++;
 		} else {
-			dev_err(&mc13xxx->spidev->dev,
+			dev_err(mc13xxx->dev,
 					"BUG: irq %u but no handler\n",
 					baseirq + irq);
 
@@ -475,25 +502,23 @@ static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
 	return IRQ_RETVAL(handled);
 }
 
-enum mc13xxx_id {
-	MC13XXX_ID_MC13783,
-	MC13XXX_ID_MC13892,
-	MC13XXX_ID_INVALID,
-};
-
 static const char *mc13xxx_chipname[] = {
 	[MC13XXX_ID_MC13783] = "mc13783",
 	[MC13XXX_ID_MC13892] = "mc13892",
 };
 
 #define maskval(reg, mask)	(((reg) & (mask)) >> __ffs(mask))
-static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
+static int mc13xxx_identify(struct mc13xxx *mc13xxx)
 {
 	u32 icid;
 	u32 revision;
-	const char *name;
 	int ret;
 
+	/*
+	 * Get the generation ID from register 46, as apparently some older
+	 * IC revisions only have this info at this location. Newer ICs seem to
+	 * have both.
+	 */
 	ret = mc13xxx_reg_read(mc13xxx, 46, &icid);
 	if (ret)
 		return ret;
@@ -502,26 +527,23 @@ static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
 
 	switch (icid) {
 	case 2:
-		*id = MC13XXX_ID_MC13783;
-		name = "mc13783";
+		mc13xxx->ictype = MC13XXX_ID_MC13783;
 		break;
 	case 7:
-		*id = MC13XXX_ID_MC13892;
-		name = "mc13892";
+		mc13xxx->ictype = MC13XXX_ID_MC13892;
 		break;
 	default:
-		*id = MC13XXX_ID_INVALID;
+		mc13xxx->ictype = MC13XXX_ID_INVALID;
 		break;
 	}
 
-	if (*id == MC13XXX_ID_MC13783 || *id == MC13XXX_ID_MC13892) {
+	if (mc13xxx->ictype == MC13XXX_ID_MC13783 ||
+			mc13xxx->ictype == MC13XXX_ID_MC13892) {
 		ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
-		if (ret)
-			return ret;
 
-		dev_info(&mc13xxx->spidev->dev, "%s: rev: %d.%d, "
+		dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
 				"fin: %d, fab: %d, icid: %d/%d\n",
-				mc13xxx_chipname[*id],
+				mc13xxx_chipname[mc13xxx->ictype],
 				maskval(revision, MC13XXX_REVISION_REVFULL),
 				maskval(revision, MC13XXX_REVISION_REVMETAL),
 				maskval(revision, MC13XXX_REVISION_FIN),
@@ -530,26 +552,12 @@ static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
 				maskval(revision, MC13XXX_REVISION_ICIDCODE));
 	}
 
-	if (*id != MC13XXX_ID_INVALID) {
-		const struct spi_device_id *devid =
-			spi_get_device_id(mc13xxx->spidev);
-		if (!devid || devid->driver_data != *id)
-			dev_warn(&mc13xxx->spidev->dev, "device id doesn't "
-					"match auto detection!\n");
-	}
-
-	return 0;
+	return (mc13xxx->ictype == MC13XXX_ID_INVALID) ? -ENODEV : 0;
 }
 
 static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
 {
-	const struct spi_device_id *devid =
-		spi_get_device_id(mc13xxx->spidev);
-
-	if (!devid)
-		return NULL;
-
-	return mc13xxx_chipname[devid->driver_data];
+	return mc13xxx_chipname[mc13xxx->ictype];
 }
 
 int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
@@ -589,7 +597,7 @@ int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
 	};
 	init_completion(&adcdone_data.done);
 
-	dev_dbg(&mc13xxx->spidev->dev, "%s\n", __func__);
+	dev_dbg(mc13xxx->dev, "%s\n", __func__);
 
 	mc13xxx_lock(mc13xxx);
 
@@ -631,7 +639,7 @@ int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
 		return -EINVAL;
 	}
 
-	dev_dbg(&mc13xxx->spidev->dev, "%s: request irq\n", __func__);
+	dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
 	mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
 			mc13xxx_handler_adcdone, __func__, &adcdone_data);
 	mc13xxx_irq_ack(mc13xxx, MC13XXX_IRQ_ADCDONE);
@@ -689,7 +697,7 @@ static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
 	if (!cell.name)
 		return -ENOMEM;
 
-	return mfd_add_devices(&mc13xxx->spidev->dev, -1, &cell, 1, NULL, 0);
+	return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0);
 }
 
 static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
@@ -700,7 +708,7 @@ static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
 #ifdef CONFIG_OF
 static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 {
-	struct device_node *np = mc13xxx->spidev->dev.of_node;
+	struct device_node *np = mc13xxx->dev.of_node;
 
 	if (!np)
 		return -ENODEV;
@@ -746,13 +754,15 @@ static const struct of_device_id mc13xxx_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
 
+static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+		struct mc13xxx_platform_data *pdata, int irq);
+
 static int mc13xxx_probe(struct spi_device *spi)
 {
 	const struct of_device_id *of_id;
 	struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
 	struct mc13xxx *mc13xxx;
 	struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
-	enum mc13xxx_id id;
 	int ret;
 
 	of_id = of_match_device(mc13xxx_dt_ids, &spi->dev);
@@ -768,13 +778,36 @@ static int mc13xxx_probe(struct spi_device *spi)
 	spi->bits_per_word = 32;
 	spi_setup(spi);
 
+	mc13xxx->dev = &spi->dev;
 	mc13xxx->spidev = spi;
+	mc13xxx->read_dev = mc13xxx_spi_reg_read;
+	mc13xxx->write_dev = mc13xxx_spi_reg_write;
+
+	ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
+
+	if (ret) {
+		dev_set_drvdata(&spi->dev, NULL);
+	} else {
+		const struct spi_device_id *devid =
+			spi_get_device_id(mc13xxx->spidev);
+		if (!devid || devid->driver_data != mc13xxx->ictype)
+			dev_warn(mc13xxx->dev,
+				"device id doesn't match auto detection!\n");
+	}
+
+	return ret;
+}
+
+static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+		struct mc13xxx_platform_data *pdata, int irq)
+{
+	int ret;
 
 	mutex_init(&mc13xxx->lock);
 	mc13xxx_lock(mc13xxx);
 
-	ret = mc13xxx_identify(mc13xxx, &id);
-	if (ret || id == MC13XXX_ID_INVALID)
+	ret = mc13xxx_identify(mc13xxx);
+	if (ret)
 		goto err_revision;
 
 	/* mask all irqs */
@@ -786,14 +819,13 @@ static int mc13xxx_probe(struct spi_device *spi)
 	if (ret)
 		goto err_mask;
 
-	ret = request_threaded_irq(spi->irq, NULL, mc13xxx_irq_thread,
+	ret = request_threaded_irq(irq, NULL, mc13xxx_irq_thread,
 			IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
 
 	if (ret) {
 err_mask:
 err_revision:
 		mc13xxx_unlock(mc13xxx);
-		dev_set_drvdata(&spi->dev, NULL);
 		kfree(mc13xxx);
 		return ret;
 	}
-- 
1.7.3.4



From stigge at antcom.de  Sat Mar 10 20:46:13 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 11 Mar 2012 02:46:13 +0100
Subject: [PATCH v6 1/3] USB: OHCI-HCD: Rename ohci-pnx4008 to ohci-nxp
In-Reply-To: <1331430375-31227-1-git-send-email-stigge@antcom.de>
References: <1331430375-31227-1-git-send-email-stigge@antcom.de>
Message-ID: <1331430375-31227-2-git-send-email-stigge@antcom.de>

Since this driver is compatible with several NXP devices, the driver is renamed
accordingly. Please combine with the following patch which also changes the
respective symbol names.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 drivers/usb/host/ohci-hcd.c     |    2 
 drivers/usb/host/ohci-nxp.c     |  453 ++++++++++++++++++++++++++++++++++++++++
 drivers/usb/host/ohci-pnx4008.c |  453 ----------------------------------------
 3 files changed, 454 insertions(+), 454 deletions(-)

--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1051,7 +1051,7 @@ MODULE_LICENSE ("GPL");
 #endif
 
 #ifdef CONFIG_ARCH_PNX4008
-#include "ohci-pnx4008.c"
+#include "ohci-nxp.c"
 #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
 #endif
 
--- /dev/null
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -0,0 +1,453 @@
+/*
+ * drivers/usb/host/ohci-pnx4008.c
+ *
+ * driver for Philips PNX4008 USB Host
+ *
+ * Authors: Dmitry Chigirev <source at mvista.com>
+ *	    Vitaly Wool <vitalywool at gmail.com>
+ *
+ * register initialization is based on code examples provided by Philips
+ * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
+ *
+ * NOTE: This driver does not have suspend/resume functionality
+ * This driver is intended for engineering development purposes only
+ *
+ * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+
+#include <mach/platform.h>
+#include <mach/irqs.h>
+#include <asm/gpio.h>
+
+#define USB_CTRL	IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64)
+
+/* USB_CTRL bit defines */
+#define USB_SLAVE_HCLK_EN	(1 << 24)
+#define USB_HOST_NEED_CLK_EN	(1 << 21)
+
+#define USB_OTG_CLK_CTRL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF4)
+#define USB_OTG_CLK_STAT	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF8)
+
+/* USB_OTG_CLK_CTRL bit defines */
+#define AHB_M_CLOCK_ON		(1 << 4)
+#define OTG_CLOCK_ON		(1 << 3)
+#define I2C_CLOCK_ON		(1 << 2)
+#define DEV_CLOCK_ON		(1 << 1)
+#define HOST_CLOCK_ON		(1 << 0)
+
+#define USB_OTG_STAT_CONTROL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x110)
+
+/* USB_OTG_STAT_CONTROL bit defines */
+#define TRANSPARENT_I2C_EN	(1 << 7)
+#define HOST_EN			(1 << 0)
+
+/* ISP1301 USB transceiver I2C registers */
+#define	ISP1301_MODE_CONTROL_1		0x04	/* u8 read, set, +1 clear */
+
+#define	MC1_SPEED_REG		(1 << 0)
+#define	MC1_SUSPEND_REG		(1 << 1)
+#define	MC1_DAT_SE0		(1 << 2)
+#define	MC1_TRANSPARENT		(1 << 3)
+#define	MC1_BDIS_ACON_EN	(1 << 4)
+#define	MC1_OE_INT_EN		(1 << 5)
+#define	MC1_UART_EN		(1 << 6)
+#define	MC1_MASK		0x7f
+
+#define	ISP1301_MODE_CONTROL_2		0x12	/* u8 read, set, +1 clear */
+
+#define	MC2_GLOBAL_PWR_DN	(1 << 0)
+#define	MC2_SPD_SUSP_CTRL	(1 << 1)
+#define	MC2_BI_DI		(1 << 2)
+#define	MC2_TRANSP_BDIR0	(1 << 3)
+#define	MC2_TRANSP_BDIR1	(1 << 4)
+#define	MC2_AUDIO_EN		(1 << 5)
+#define	MC2_PSW_EN		(1 << 6)
+#define	MC2_EN2V7		(1 << 7)
+
+#define	ISP1301_OTG_CONTROL_1		0x06	/* u8 read, set, +1 clear */
+#	define	OTG1_DP_PULLUP		(1 << 0)
+#	define	OTG1_DM_PULLUP		(1 << 1)
+#	define	OTG1_DP_PULLDOWN	(1 << 2)
+#	define	OTG1_DM_PULLDOWN	(1 << 3)
+#	define	OTG1_ID_PULLDOWN	(1 << 4)
+#	define	OTG1_VBUS_DRV		(1 << 5)
+#	define	OTG1_VBUS_DISCHRG	(1 << 6)
+#	define	OTG1_VBUS_CHRG		(1 << 7)
+#define	ISP1301_OTG_STATUS		0x10	/* u8 readonly */
+#	define	OTG_B_SESS_END		(1 << 6)
+#	define	OTG_B_SESS_VLD		(1 << 7)
+
+#define ISP1301_I2C_ADDR 0x2C
+
+#define ISP1301_I2C_MODE_CONTROL_1 0x4
+#define ISP1301_I2C_MODE_CONTROL_2 0x12
+#define ISP1301_I2C_OTG_CONTROL_1 0x6
+#define ISP1301_I2C_OTG_CONTROL_2 0x10
+#define ISP1301_I2C_INTERRUPT_SOURCE 0x8
+#define ISP1301_I2C_INTERRUPT_LATCH 0xA
+#define ISP1301_I2C_INTERRUPT_FALLING 0xC
+#define ISP1301_I2C_INTERRUPT_RISING 0xE
+#define ISP1301_I2C_REG_CLEAR_ADDR 1
+
+static struct i2c_driver isp1301_driver;
+static struct i2c_client *isp1301_i2c_client;
+
+extern int usb_disabled(void);
+extern int ocpi_enable(void);
+
+static struct clk *usb_clk;
+
+static const unsigned short normal_i2c[] =
+    { ISP1301_I2C_ADDR, ISP1301_I2C_ADDR + 1, I2C_CLIENT_END };
+
+static int isp1301_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	return 0;
+}
+
+static int isp1301_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+static const struct i2c_device_id isp1301_id[] = {
+	{ "isp1301_pnx", 0 },
+	{ }
+};
+
+static struct i2c_driver isp1301_driver = {
+	.driver = {
+		.name = "isp1301_pnx",
+	},
+	.probe = isp1301_probe,
+	.remove = isp1301_remove,
+	.id_table = isp1301_id,
+};
+
+static void i2c_write(u8 buf, u8 subaddr)
+{
+	char tmpbuf[2];
+
+	tmpbuf[0] = subaddr;	/*register number */
+	tmpbuf[1] = buf;	/*register data */
+	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
+}
+
+static void isp1301_configure(void)
+{
+	/* PNX4008 only supports DAT_SE0 USB mode */
+	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
+	/* Power up externel charge-pump */
+
+	i2c_write(MC1_DAT_SE0 | MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
+	i2c_write(~(MC1_DAT_SE0 | MC1_SPEED_REG),
+		  ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL,
+		  ISP1301_I2C_MODE_CONTROL_2);
+	i2c_write(~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
+		  ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN,
+		  ISP1301_I2C_OTG_CONTROL_1);
+	i2c_write(~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
+		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(0xFF,
+		  ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(0xFF,
+		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(0xFF,
+		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+
+}
+
+static inline void isp1301_vbus_on(void)
+{
+	i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1);
+}
+
+static inline void isp1301_vbus_off(void)
+{
+	i2c_write(OTG1_VBUS_DRV,
+		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
+}
+
+static void pnx4008_start_hc(void)
+{
+	unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
+	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
+	isp1301_vbus_on();
+}
+
+static void pnx4008_stop_hc(void)
+{
+	unsigned long tmp;
+	isp1301_vbus_off();
+	tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN;
+	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
+}
+
+static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd)
+{
+	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+	int ret;
+
+	if ((ret = ohci_init(ohci)) < 0)
+		return ret;
+
+	if ((ret = ohci_run(ohci)) < 0) {
+		dev_err(hcd->self.controller, "can't start\n");
+		ohci_stop(hcd);
+		return ret;
+	}
+	return 0;
+}
+
+static const struct hc_driver ohci_pnx4008_hc_driver = {
+	.description = hcd_name,
+	.product_desc =		"pnx4008 OHCI",
+
+	/*
+	 * generic hardware linkage
+	 */
+	.irq = ohci_irq,
+	.flags = HCD_USB11 | HCD_MEMORY,
+
+	.hcd_priv_size =	sizeof(struct ohci_hcd),
+	/*
+	 * basic lifecycle operations
+	 */
+	.start = ohci_pnx4008_start,
+	.stop = ohci_stop,
+	.shutdown = ohci_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	 */
+	.urb_enqueue = ohci_urb_enqueue,
+	.urb_dequeue = ohci_urb_dequeue,
+	.endpoint_disable = ohci_endpoint_disable,
+
+	/*
+	 * scheduling support
+	 */
+	.get_frame_number = ohci_get_frame,
+
+	/*
+	 * root hub support
+	 */
+	.hub_status_data = ohci_hub_status_data,
+	.hub_control = ohci_hub_control,
+#ifdef	CONFIG_PM
+	.bus_suspend = ohci_bus_suspend,
+	.bus_resume = ohci_bus_resume,
+#endif
+	.start_port_reset = ohci_start_port_reset,
+};
+
+#define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON)
+
+static void pnx4008_set_usb_bits(void)
+{
+	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
+	start_int_ack(SE_USB_OTG_ATX_INT_N);
+	start_int_umask(SE_USB_OTG_ATX_INT_N);
+
+	start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
+	start_int_ack(SE_USB_OTG_TIMER_INT);
+	start_int_umask(SE_USB_OTG_TIMER_INT);
+
+	start_int_set_rising_edge(SE_USB_I2C_INT);
+	start_int_ack(SE_USB_I2C_INT);
+	start_int_umask(SE_USB_I2C_INT);
+
+	start_int_set_rising_edge(SE_USB_INT);
+	start_int_ack(SE_USB_INT);
+	start_int_umask(SE_USB_INT);
+
+	start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
+	start_int_ack(SE_USB_NEED_CLK_INT);
+	start_int_umask(SE_USB_NEED_CLK_INT);
+
+	start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
+	start_int_ack(SE_USB_AHB_NEED_CLK_INT);
+	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+}
+
+static void pnx4008_unset_usb_bits(void)
+{
+	start_int_mask(SE_USB_OTG_ATX_INT_N);
+	start_int_mask(SE_USB_OTG_TIMER_INT);
+	start_int_mask(SE_USB_I2C_INT);
+	start_int_mask(SE_USB_INT);
+	start_int_mask(SE_USB_NEED_CLK_INT);
+	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+}
+
+static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = 0;
+	struct ohci_hcd *ohci;
+	const struct hc_driver *driver = &ohci_pnx4008_hc_driver;
+	struct i2c_adapter *i2c_adap;
+	struct i2c_board_info i2c_info;
+
+	int ret = 0, irq;
+
+	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (pnx4008)\n", hcd_name);
+	if (usb_disabled()) {
+		err("USB is disabled");
+		ret = -ENODEV;
+		goto out;
+	}
+
+	if (pdev->num_resources != 2
+	    || pdev->resource[0].flags != IORESOURCE_MEM
+	    || pdev->resource[1].flags != IORESOURCE_IRQ) {
+		err("Invalid resource configuration");
+		ret = -ENODEV;
+		goto out;
+	}
+
+	/* Enable AHB slave USB clock, needed for further USB clock control */
+	__raw_writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
+
+	ret = i2c_add_driver(&isp1301_driver);
+	if (ret < 0) {
+		err("failed to add ISP1301 driver");
+		goto out;
+	}
+	i2c_adap = i2c_get_adapter(2);
+	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
+	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
+	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
+						   normal_i2c, NULL);
+	i2c_put_adapter(i2c_adap);
+	if (!isp1301_i2c_client) {
+		err("failed to connect I2C to ISP1301 USB Transceiver");
+		ret = -ENODEV;
+		goto out_i2c_driver;
+	}
+
+	isp1301_configure();
+
+	/* Enable USB PLL */
+	usb_clk = clk_get(&pdev->dev, "ck_pll5");
+	if (IS_ERR(usb_clk)) {
+		err("failed to acquire USB PLL");
+		ret = PTR_ERR(usb_clk);
+		goto out1;
+	}
+
+	ret = clk_enable(usb_clk);
+	if (ret < 0) {
+		err("failed to start USB PLL");
+		goto out2;
+	}
+
+	ret = clk_set_rate(usb_clk, 48000);
+	if (ret < 0) {
+		err("failed to set USB clock rate");
+		goto out3;
+	}
+
+	__raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL);
+
+	/* Set to enable all needed USB clocks */
+	__raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL);
+
+	while ((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) !=
+	       USB_CLOCK_MASK) ;
+
+	hcd = usb_create_hcd (driver, &pdev->dev, dev_name(&pdev->dev));
+	if (!hcd) {
+		err("Failed to allocate HC buffer");
+		ret = -ENOMEM;
+		goto out3;
+	}
+
+	/* Set all USB bits in the Start Enable register */
+	pnx4008_set_usb_bits();
+
+	hcd->rsrc_start = pdev->resource[0].start;
+	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
+	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+		dev_dbg(&pdev->dev, "request_mem_region failed\n");
+		ret =  -ENOMEM;
+		goto out4;
+	}
+	hcd->regs = (void __iomem *)pdev->resource[0].start;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		ret = -ENXIO;
+		goto out4;
+	}
+
+	pnx4008_start_hc();
+	platform_set_drvdata(pdev, hcd);
+	ohci = hcd_to_ohci(hcd);
+	ohci_hcd_init(ohci);
+
+	dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq);
+	ret = usb_add_hcd(hcd, irq, 0);
+	if (ret == 0)
+		return ret;
+
+	pnx4008_stop_hc();
+out4:
+	pnx4008_unset_usb_bits();
+	usb_put_hcd(hcd);
+out3:
+	clk_disable(usb_clk);
+out2:
+	clk_put(usb_clk);
+out1:
+	i2c_unregister_device(isp1301_i2c_client);
+	isp1301_i2c_client = NULL;
+out_i2c_driver:
+	i2c_del_driver(&isp1301_driver);
+out:
+	return ret;
+}
+
+static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+	usb_remove_hcd(hcd);
+	pnx4008_stop_hc();
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	usb_put_hcd(hcd);
+	pnx4008_unset_usb_bits();
+	clk_disable(usb_clk);
+	clk_put(usb_clk);
+	i2c_unregister_device(isp1301_i2c_client);
+	isp1301_i2c_client = NULL;
+	i2c_del_driver(&isp1301_driver);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+/* work with hotplug and coldplug */
+MODULE_ALIAS("platform:usb-ohci");
+
+static struct platform_driver usb_hcd_pnx4008_driver = {
+	.driver = {
+		.name = "usb-ohci",
+		.owner	= THIS_MODULE,
+	},
+	.probe = usb_hcd_pnx4008_probe,
+	.remove = usb_hcd_pnx4008_remove,
+};
+
--- linux-2.6.orig/drivers/usb/host/ohci-pnx4008.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * drivers/usb/host/ohci-pnx4008.c
- *
- * driver for Philips PNX4008 USB Host
- *
- * Authors: Dmitry Chigirev <source at mvista.com>
- *	    Vitaly Wool <vitalywool at gmail.com>
- *
- * register initialization is based on code examples provided by Philips
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * NOTE: This driver does not have suspend/resume functionality
- * This driver is intended for engineering development purposes only
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-
-#include <mach/hardware.h>
-#include <asm/io.h>
-
-#include <mach/platform.h>
-#include <mach/irqs.h>
-#include <asm/gpio.h>
-
-#define USB_CTRL	IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64)
-
-/* USB_CTRL bit defines */
-#define USB_SLAVE_HCLK_EN	(1 << 24)
-#define USB_HOST_NEED_CLK_EN	(1 << 21)
-
-#define USB_OTG_CLK_CTRL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF4)
-#define USB_OTG_CLK_STAT	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF8)
-
-/* USB_OTG_CLK_CTRL bit defines */
-#define AHB_M_CLOCK_ON		(1 << 4)
-#define OTG_CLOCK_ON		(1 << 3)
-#define I2C_CLOCK_ON		(1 << 2)
-#define DEV_CLOCK_ON		(1 << 1)
-#define HOST_CLOCK_ON		(1 << 0)
-
-#define USB_OTG_STAT_CONTROL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x110)
-
-/* USB_OTG_STAT_CONTROL bit defines */
-#define TRANSPARENT_I2C_EN	(1 << 7)
-#define HOST_EN			(1 << 0)
-
-/* ISP1301 USB transceiver I2C registers */
-#define	ISP1301_MODE_CONTROL_1		0x04	/* u8 read, set, +1 clear */
-
-#define	MC1_SPEED_REG		(1 << 0)
-#define	MC1_SUSPEND_REG		(1 << 1)
-#define	MC1_DAT_SE0		(1 << 2)
-#define	MC1_TRANSPARENT		(1 << 3)
-#define	MC1_BDIS_ACON_EN	(1 << 4)
-#define	MC1_OE_INT_EN		(1 << 5)
-#define	MC1_UART_EN		(1 << 6)
-#define	MC1_MASK		0x7f
-
-#define	ISP1301_MODE_CONTROL_2		0x12	/* u8 read, set, +1 clear */
-
-#define	MC2_GLOBAL_PWR_DN	(1 << 0)
-#define	MC2_SPD_SUSP_CTRL	(1 << 1)
-#define	MC2_BI_DI		(1 << 2)
-#define	MC2_TRANSP_BDIR0	(1 << 3)
-#define	MC2_TRANSP_BDIR1	(1 << 4)
-#define	MC2_AUDIO_EN		(1 << 5)
-#define	MC2_PSW_EN		(1 << 6)
-#define	MC2_EN2V7		(1 << 7)
-
-#define	ISP1301_OTG_CONTROL_1		0x06	/* u8 read, set, +1 clear */
-#	define	OTG1_DP_PULLUP		(1 << 0)
-#	define	OTG1_DM_PULLUP		(1 << 1)
-#	define	OTG1_DP_PULLDOWN	(1 << 2)
-#	define	OTG1_DM_PULLDOWN	(1 << 3)
-#	define	OTG1_ID_PULLDOWN	(1 << 4)
-#	define	OTG1_VBUS_DRV		(1 << 5)
-#	define	OTG1_VBUS_DISCHRG	(1 << 6)
-#	define	OTG1_VBUS_CHRG		(1 << 7)
-#define	ISP1301_OTG_STATUS		0x10	/* u8 readonly */
-#	define	OTG_B_SESS_END		(1 << 6)
-#	define	OTG_B_SESS_VLD		(1 << 7)
-
-#define ISP1301_I2C_ADDR 0x2C
-
-#define ISP1301_I2C_MODE_CONTROL_1 0x4
-#define ISP1301_I2C_MODE_CONTROL_2 0x12
-#define ISP1301_I2C_OTG_CONTROL_1 0x6
-#define ISP1301_I2C_OTG_CONTROL_2 0x10
-#define ISP1301_I2C_INTERRUPT_SOURCE 0x8
-#define ISP1301_I2C_INTERRUPT_LATCH 0xA
-#define ISP1301_I2C_INTERRUPT_FALLING 0xC
-#define ISP1301_I2C_INTERRUPT_RISING 0xE
-#define ISP1301_I2C_REG_CLEAR_ADDR 1
-
-static struct i2c_driver isp1301_driver;
-static struct i2c_client *isp1301_i2c_client;
-
-extern int usb_disabled(void);
-extern int ocpi_enable(void);
-
-static struct clk *usb_clk;
-
-static const unsigned short normal_i2c[] =
-    { ISP1301_I2C_ADDR, ISP1301_I2C_ADDR + 1, I2C_CLIENT_END };
-
-static int isp1301_probe(struct i2c_client *client,
-			 const struct i2c_device_id *id)
-{
-	return 0;
-}
-
-static int isp1301_remove(struct i2c_client *client)
-{
-	return 0;
-}
-
-static const struct i2c_device_id isp1301_id[] = {
-	{ "isp1301_pnx", 0 },
-	{ }
-};
-
-static struct i2c_driver isp1301_driver = {
-	.driver = {
-		.name = "isp1301_pnx",
-	},
-	.probe = isp1301_probe,
-	.remove = isp1301_remove,
-	.id_table = isp1301_id,
-};
-
-static void i2c_write(u8 buf, u8 subaddr)
-{
-	char tmpbuf[2];
-
-	tmpbuf[0] = subaddr;	/*register number */
-	tmpbuf[1] = buf;	/*register data */
-	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
-}
-
-static void isp1301_configure(void)
-{
-	/* PNX4008 only supports DAT_SE0 USB mode */
-	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
-	/* Power up externel charge-pump */
-
-	i2c_write(MC1_DAT_SE0 | MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
-	i2c_write(~(MC1_DAT_SE0 | MC1_SPEED_REG),
-		  ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL,
-		  ISP1301_I2C_MODE_CONTROL_2);
-	i2c_write(~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
-		  ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN,
-		  ISP1301_I2C_OTG_CONTROL_1);
-	i2c_write(~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
-		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
-
-}
-
-static inline void isp1301_vbus_on(void)
-{
-	i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1);
-}
-
-static inline void isp1301_vbus_off(void)
-{
-	i2c_write(OTG1_VBUS_DRV,
-		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-}
-
-static void pnx4008_start_hc(void)
-{
-	unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
-	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
-	isp1301_vbus_on();
-}
-
-static void pnx4008_stop_hc(void)
-{
-	unsigned long tmp;
-	isp1301_vbus_off();
-	tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN;
-	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
-}
-
-static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd)
-{
-	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
-	int ret;
-
-	if ((ret = ohci_init(ohci)) < 0)
-		return ret;
-
-	if ((ret = ohci_run(ohci)) < 0) {
-		dev_err(hcd->self.controller, "can't start\n");
-		ohci_stop(hcd);
-		return ret;
-	}
-	return 0;
-}
-
-static const struct hc_driver ohci_pnx4008_hc_driver = {
-	.description = hcd_name,
-	.product_desc =		"pnx4008 OHCI",
-
-	/*
-	 * generic hardware linkage
-	 */
-	.irq = ohci_irq,
-	.flags = HCD_USB11 | HCD_MEMORY,
-
-	.hcd_priv_size =	sizeof(struct ohci_hcd),
-	/*
-	 * basic lifecycle operations
-	 */
-	.start = ohci_pnx4008_start,
-	.stop = ohci_stop,
-	.shutdown = ohci_shutdown,
-
-	/*
-	 * managing i/o requests and associated device resources
-	 */
-	.urb_enqueue = ohci_urb_enqueue,
-	.urb_dequeue = ohci_urb_dequeue,
-	.endpoint_disable = ohci_endpoint_disable,
-
-	/*
-	 * scheduling support
-	 */
-	.get_frame_number = ohci_get_frame,
-
-	/*
-	 * root hub support
-	 */
-	.hub_status_data = ohci_hub_status_data,
-	.hub_control = ohci_hub_control,
-#ifdef	CONFIG_PM
-	.bus_suspend = ohci_bus_suspend,
-	.bus_resume = ohci_bus_resume,
-#endif
-	.start_port_reset = ohci_start_port_reset,
-};
-
-#define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON)
-
-static void pnx4008_set_usb_bits(void)
-{
-	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-	start_int_ack(SE_USB_OTG_ATX_INT_N);
-	start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-	start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-	start_int_ack(SE_USB_OTG_TIMER_INT);
-	start_int_umask(SE_USB_OTG_TIMER_INT);
-
-	start_int_set_rising_edge(SE_USB_I2C_INT);
-	start_int_ack(SE_USB_I2C_INT);
-	start_int_umask(SE_USB_I2C_INT);
-
-	start_int_set_rising_edge(SE_USB_INT);
-	start_int_ack(SE_USB_INT);
-	start_int_umask(SE_USB_INT);
-
-	start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-	start_int_ack(SE_USB_NEED_CLK_INT);
-	start_int_umask(SE_USB_NEED_CLK_INT);
-
-	start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-	start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
-}
-
-static void pnx4008_unset_usb_bits(void)
-{
-	start_int_mask(SE_USB_OTG_ATX_INT_N);
-	start_int_mask(SE_USB_OTG_TIMER_INT);
-	start_int_mask(SE_USB_I2C_INT);
-	start_int_mask(SE_USB_INT);
-	start_int_mask(SE_USB_NEED_CLK_INT);
-	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
-}
-
-static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
-{
-	struct usb_hcd *hcd = 0;
-	struct ohci_hcd *ohci;
-	const struct hc_driver *driver = &ohci_pnx4008_hc_driver;
-	struct i2c_adapter *i2c_adap;
-	struct i2c_board_info i2c_info;
-
-	int ret = 0, irq;
-
-	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (pnx4008)\n", hcd_name);
-	if (usb_disabled()) {
-		err("USB is disabled");
-		ret = -ENODEV;
-		goto out;
-	}
-
-	if (pdev->num_resources != 2
-	    || pdev->resource[0].flags != IORESOURCE_MEM
-	    || pdev->resource[1].flags != IORESOURCE_IRQ) {
-		err("Invalid resource configuration");
-		ret = -ENODEV;
-		goto out;
-	}
-
-	/* Enable AHB slave USB clock, needed for further USB clock control */
-	__raw_writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
-
-	ret = i2c_add_driver(&isp1301_driver);
-	if (ret < 0) {
-		err("failed to add ISP1301 driver");
-		goto out;
-	}
-	i2c_adap = i2c_get_adapter(2);
-	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
-	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
-	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
-						   normal_i2c, NULL);
-	i2c_put_adapter(i2c_adap);
-	if (!isp1301_i2c_client) {
-		err("failed to connect I2C to ISP1301 USB Transceiver");
-		ret = -ENODEV;
-		goto out_i2c_driver;
-	}
-
-	isp1301_configure();
-
-	/* Enable USB PLL */
-	usb_clk = clk_get(&pdev->dev, "ck_pll5");
-	if (IS_ERR(usb_clk)) {
-		err("failed to acquire USB PLL");
-		ret = PTR_ERR(usb_clk);
-		goto out1;
-	}
-
-	ret = clk_enable(usb_clk);
-	if (ret < 0) {
-		err("failed to start USB PLL");
-		goto out2;
-	}
-
-	ret = clk_set_rate(usb_clk, 48000);
-	if (ret < 0) {
-		err("failed to set USB clock rate");
-		goto out3;
-	}
-
-	__raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL);
-
-	/* Set to enable all needed USB clocks */
-	__raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL);
-
-	while ((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) !=
-	       USB_CLOCK_MASK) ;
-
-	hcd = usb_create_hcd (driver, &pdev->dev, dev_name(&pdev->dev));
-	if (!hcd) {
-		err("Failed to allocate HC buffer");
-		ret = -ENOMEM;
-		goto out3;
-	}
-
-	/* Set all USB bits in the Start Enable register */
-	pnx4008_set_usb_bits();
-
-	hcd->rsrc_start = pdev->resource[0].start;
-	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
-	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
-		dev_dbg(&pdev->dev, "request_mem_region failed\n");
-		ret =  -ENOMEM;
-		goto out4;
-	}
-	hcd->regs = (void __iomem *)pdev->resource[0].start;
-
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
-		ret = -ENXIO;
-		goto out4;
-	}
-
-	pnx4008_start_hc();
-	platform_set_drvdata(pdev, hcd);
-	ohci = hcd_to_ohci(hcd);
-	ohci_hcd_init(ohci);
-
-	dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq);
-	ret = usb_add_hcd(hcd, irq, 0);
-	if (ret == 0)
-		return ret;
-
-	pnx4008_stop_hc();
-out4:
-	pnx4008_unset_usb_bits();
-	usb_put_hcd(hcd);
-out3:
-	clk_disable(usb_clk);
-out2:
-	clk_put(usb_clk);
-out1:
-	i2c_unregister_device(isp1301_i2c_client);
-	isp1301_i2c_client = NULL;
-out_i2c_driver:
-	i2c_del_driver(&isp1301_driver);
-out:
-	return ret;
-}
-
-static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
-{
-	struct usb_hcd *hcd = platform_get_drvdata(pdev);
-
-	usb_remove_hcd(hcd);
-	pnx4008_stop_hc();
-	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-	usb_put_hcd(hcd);
-	pnx4008_unset_usb_bits();
-	clk_disable(usb_clk);
-	clk_put(usb_clk);
-	i2c_unregister_device(isp1301_i2c_client);
-	isp1301_i2c_client = NULL;
-	i2c_del_driver(&isp1301_driver);
-
-	platform_set_drvdata(pdev, NULL);
-
-	return 0;
-}
-
-/* work with hotplug and coldplug */
-MODULE_ALIAS("platform:usb-ohci");
-
-static struct platform_driver usb_hcd_pnx4008_driver = {
-	.driver = {
-		.name = "usb-ohci",
-		.owner	= THIS_MODULE,
-	},
-	.probe = usb_hcd_pnx4008_probe,
-	.remove = usb_hcd_pnx4008_remove,
-};
-


From alan at signal11.us  Sat Mar 10 16:36:20 2012
From: alan at signal11.us (Alan Ott)
Date: Sat, 10 Mar 2012 16:36:20 -0500
Subject: [PATCH v2 0/2] ata: AT91 ata driver requires specific platforms
In-Reply-To: <1331405617-4053-1-git-send-email-alan@signal11.us>
References: <1331405617-4053-1-git-send-email-alan@signal11.us>
Message-ID: <1331415380-10928-1-git-send-email-alan@signal11.us>

Based on suggestions from Ben Dooks, This patch now adds an AT91_HAS_PATA
kconfig item and the AT91 CPUs which have PATA now select it. The
AT91 PATA driver how depends on this kconfig item.

Ben, let me know if this is what you had in mind.


Alan Ott (2):
  ARM: AT91: Add parameter for AT91_HAS_PATA
  ata: AT91 ata driver requires AT91_HAS_PATA

 arch/arm/mach-at91/Kconfig |   11 +++++++++++
 drivers/ata/Kconfig        |    1 +
 2 files changed, 12 insertions(+), 0 deletions(-)



From enrico.scholz at sigma-chemnitz.de  Mon Mar 12 13:02:04 2012
From: enrico.scholz at sigma-chemnitz.de (Enrico Scholz)
Date: Mon, 12 Mar 2012 18:02:04 +0100
Subject: [PATCH] gpio/mxs: support irqs triggered by both edges
In-Reply-To: <20120312163503.AEBC73E07B0@localhost> (Grant Likely's message of
 "Mon, 12 Mar 2012 10:35:03 -0600")
References: <1329745925-7868-1-git-send-email-enrico.scholz@sigma-chemnitz.de>
 <20120312163503.AEBC73E07B0@localhost>
Message-ID: <lyhaxt4usz.fsf@ensc-virt.intern.sigma-chemnitz.de>

Grant Likely <grant.likely at secretlab.ca> writes:

>> iMX28 silicon does not support irqs triggered by both gpio edges. Patch
>> emulates this behavior by configuring such irqs as level triggered and
>> by switching polarity in the interrupt handler.
>
> That looks dodgy and hacky.  This will definitely miss interrupts if
> they come in too fast. 

Because patch calculates the trigger from the actual level, there should
not be missed more interrupts than with native edge-both support.

> I don't like this approach.  What do you need it for?

some drivers (e.g. gpio-keys, otg gpio-vbus, gpio-charger) are requesting
gpio based interrupts with IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
flags.  It is not possible to use such drivers without having EDGE_BOTH
support.


Enrico


From stigge at antcom.de  Sat Mar 10 14:36:04 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sat, 10 Mar 2012 20:36:04 +0100
Subject: [PATCH v5 1/3] USB: OHCI-HCD: Rename ohci-pnx4008 to ohci-nxp
In-Reply-To: <1331408166-11607-1-git-send-email-stigge@antcom.de>
References: <1331408166-11607-1-git-send-email-stigge@antcom.de>
Message-ID: <1331408166-11607-2-git-send-email-stigge@antcom.de>

Since this driver is compatible with several NXP devices, the driver is renamed
accordingly. Please combine with the following patch which also changes the
respective symbol names.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 drivers/usb/host/ohci-hcd.c     |    2 
 drivers/usb/host/ohci-nxp.c     |  453 ++++++++++++++++++++++++++++++++++++++++
 drivers/usb/host/ohci-pnx4008.c |  453 ----------------------------------------
 3 files changed, 454 insertions(+), 454 deletions(-)

--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1051,7 +1051,7 @@ MODULE_LICENSE ("GPL");
 #endif
 
 #ifdef CONFIG_ARCH_PNX4008
-#include "ohci-pnx4008.c"
+#include "ohci-nxp.c"
 #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
 #endif
 
--- /dev/null
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -0,0 +1,453 @@
+/*
+ * drivers/usb/host/ohci-pnx4008.c
+ *
+ * driver for Philips PNX4008 USB Host
+ *
+ * Authors: Dmitry Chigirev <source at mvista.com>
+ *	    Vitaly Wool <vitalywool at gmail.com>
+ *
+ * register initialization is based on code examples provided by Philips
+ * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
+ *
+ * NOTE: This driver does not have suspend/resume functionality
+ * This driver is intended for engineering development purposes only
+ *
+ * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+
+#include <mach/platform.h>
+#include <mach/irqs.h>
+#include <asm/gpio.h>
+
+#define USB_CTRL	IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64)
+
+/* USB_CTRL bit defines */
+#define USB_SLAVE_HCLK_EN	(1 << 24)
+#define USB_HOST_NEED_CLK_EN	(1 << 21)
+
+#define USB_OTG_CLK_CTRL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF4)
+#define USB_OTG_CLK_STAT	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF8)
+
+/* USB_OTG_CLK_CTRL bit defines */
+#define AHB_M_CLOCK_ON		(1 << 4)
+#define OTG_CLOCK_ON		(1 << 3)
+#define I2C_CLOCK_ON		(1 << 2)
+#define DEV_CLOCK_ON		(1 << 1)
+#define HOST_CLOCK_ON		(1 << 0)
+
+#define USB_OTG_STAT_CONTROL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x110)
+
+/* USB_OTG_STAT_CONTROL bit defines */
+#define TRANSPARENT_I2C_EN	(1 << 7)
+#define HOST_EN			(1 << 0)
+
+/* ISP1301 USB transceiver I2C registers */
+#define	ISP1301_MODE_CONTROL_1		0x04	/* u8 read, set, +1 clear */
+
+#define	MC1_SPEED_REG		(1 << 0)
+#define	MC1_SUSPEND_REG		(1 << 1)
+#define	MC1_DAT_SE0		(1 << 2)
+#define	MC1_TRANSPARENT		(1 << 3)
+#define	MC1_BDIS_ACON_EN	(1 << 4)
+#define	MC1_OE_INT_EN		(1 << 5)
+#define	MC1_UART_EN		(1 << 6)
+#define	MC1_MASK		0x7f
+
+#define	ISP1301_MODE_CONTROL_2		0x12	/* u8 read, set, +1 clear */
+
+#define	MC2_GLOBAL_PWR_DN	(1 << 0)
+#define	MC2_SPD_SUSP_CTRL	(1 << 1)
+#define	MC2_BI_DI		(1 << 2)
+#define	MC2_TRANSP_BDIR0	(1 << 3)
+#define	MC2_TRANSP_BDIR1	(1 << 4)
+#define	MC2_AUDIO_EN		(1 << 5)
+#define	MC2_PSW_EN		(1 << 6)
+#define	MC2_EN2V7		(1 << 7)
+
+#define	ISP1301_OTG_CONTROL_1		0x06	/* u8 read, set, +1 clear */
+#	define	OTG1_DP_PULLUP		(1 << 0)
+#	define	OTG1_DM_PULLUP		(1 << 1)
+#	define	OTG1_DP_PULLDOWN	(1 << 2)
+#	define	OTG1_DM_PULLDOWN	(1 << 3)
+#	define	OTG1_ID_PULLDOWN	(1 << 4)
+#	define	OTG1_VBUS_DRV		(1 << 5)
+#	define	OTG1_VBUS_DISCHRG	(1 << 6)
+#	define	OTG1_VBUS_CHRG		(1 << 7)
+#define	ISP1301_OTG_STATUS		0x10	/* u8 readonly */
+#	define	OTG_B_SESS_END		(1 << 6)
+#	define	OTG_B_SESS_VLD		(1 << 7)
+
+#define ISP1301_I2C_ADDR 0x2C
+
+#define ISP1301_I2C_MODE_CONTROL_1 0x4
+#define ISP1301_I2C_MODE_CONTROL_2 0x12
+#define ISP1301_I2C_OTG_CONTROL_1 0x6
+#define ISP1301_I2C_OTG_CONTROL_2 0x10
+#define ISP1301_I2C_INTERRUPT_SOURCE 0x8
+#define ISP1301_I2C_INTERRUPT_LATCH 0xA
+#define ISP1301_I2C_INTERRUPT_FALLING 0xC
+#define ISP1301_I2C_INTERRUPT_RISING 0xE
+#define ISP1301_I2C_REG_CLEAR_ADDR 1
+
+static struct i2c_driver isp1301_driver;
+static struct i2c_client *isp1301_i2c_client;
+
+extern int usb_disabled(void);
+extern int ocpi_enable(void);
+
+static struct clk *usb_clk;
+
+static const unsigned short normal_i2c[] =
+    { ISP1301_I2C_ADDR, ISP1301_I2C_ADDR + 1, I2C_CLIENT_END };
+
+static int isp1301_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	return 0;
+}
+
+static int isp1301_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+static const struct i2c_device_id isp1301_id[] = {
+	{ "isp1301_pnx", 0 },
+	{ }
+};
+
+static struct i2c_driver isp1301_driver = {
+	.driver = {
+		.name = "isp1301_pnx",
+	},
+	.probe = isp1301_probe,
+	.remove = isp1301_remove,
+	.id_table = isp1301_id,
+};
+
+static void i2c_write(u8 buf, u8 subaddr)
+{
+	char tmpbuf[2];
+
+	tmpbuf[0] = subaddr;	/*register number */
+	tmpbuf[1] = buf;	/*register data */
+	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
+}
+
+static void isp1301_configure(void)
+{
+	/* PNX4008 only supports DAT_SE0 USB mode */
+	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
+	/* Power up externel charge-pump */
+
+	i2c_write(MC1_DAT_SE0 | MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
+	i2c_write(~(MC1_DAT_SE0 | MC1_SPEED_REG),
+		  ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL,
+		  ISP1301_I2C_MODE_CONTROL_2);
+	i2c_write(~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
+		  ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN,
+		  ISP1301_I2C_OTG_CONTROL_1);
+	i2c_write(~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
+		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(0xFF,
+		  ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(0xFF,
+		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(0xFF,
+		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+
+}
+
+static inline void isp1301_vbus_on(void)
+{
+	i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1);
+}
+
+static inline void isp1301_vbus_off(void)
+{
+	i2c_write(OTG1_VBUS_DRV,
+		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
+}
+
+static void pnx4008_start_hc(void)
+{
+	unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
+	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
+	isp1301_vbus_on();
+}
+
+static void pnx4008_stop_hc(void)
+{
+	unsigned long tmp;
+	isp1301_vbus_off();
+	tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN;
+	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
+}
+
+static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd)
+{
+	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+	int ret;
+
+	if ((ret = ohci_init(ohci)) < 0)
+		return ret;
+
+	if ((ret = ohci_run(ohci)) < 0) {
+		dev_err(hcd->self.controller, "can't start\n");
+		ohci_stop(hcd);
+		return ret;
+	}
+	return 0;
+}
+
+static const struct hc_driver ohci_pnx4008_hc_driver = {
+	.description = hcd_name,
+	.product_desc =		"pnx4008 OHCI",
+
+	/*
+	 * generic hardware linkage
+	 */
+	.irq = ohci_irq,
+	.flags = HCD_USB11 | HCD_MEMORY,
+
+	.hcd_priv_size =	sizeof(struct ohci_hcd),
+	/*
+	 * basic lifecycle operations
+	 */
+	.start = ohci_pnx4008_start,
+	.stop = ohci_stop,
+	.shutdown = ohci_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	 */
+	.urb_enqueue = ohci_urb_enqueue,
+	.urb_dequeue = ohci_urb_dequeue,
+	.endpoint_disable = ohci_endpoint_disable,
+
+	/*
+	 * scheduling support
+	 */
+	.get_frame_number = ohci_get_frame,
+
+	/*
+	 * root hub support
+	 */
+	.hub_status_data = ohci_hub_status_data,
+	.hub_control = ohci_hub_control,
+#ifdef	CONFIG_PM
+	.bus_suspend = ohci_bus_suspend,
+	.bus_resume = ohci_bus_resume,
+#endif
+	.start_port_reset = ohci_start_port_reset,
+};
+
+#define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON)
+
+static void pnx4008_set_usb_bits(void)
+{
+	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
+	start_int_ack(SE_USB_OTG_ATX_INT_N);
+	start_int_umask(SE_USB_OTG_ATX_INT_N);
+
+	start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
+	start_int_ack(SE_USB_OTG_TIMER_INT);
+	start_int_umask(SE_USB_OTG_TIMER_INT);
+
+	start_int_set_rising_edge(SE_USB_I2C_INT);
+	start_int_ack(SE_USB_I2C_INT);
+	start_int_umask(SE_USB_I2C_INT);
+
+	start_int_set_rising_edge(SE_USB_INT);
+	start_int_ack(SE_USB_INT);
+	start_int_umask(SE_USB_INT);
+
+	start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
+	start_int_ack(SE_USB_NEED_CLK_INT);
+	start_int_umask(SE_USB_NEED_CLK_INT);
+
+	start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
+	start_int_ack(SE_USB_AHB_NEED_CLK_INT);
+	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+}
+
+static void pnx4008_unset_usb_bits(void)
+{
+	start_int_mask(SE_USB_OTG_ATX_INT_N);
+	start_int_mask(SE_USB_OTG_TIMER_INT);
+	start_int_mask(SE_USB_I2C_INT);
+	start_int_mask(SE_USB_INT);
+	start_int_mask(SE_USB_NEED_CLK_INT);
+	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+}
+
+static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = 0;
+	struct ohci_hcd *ohci;
+	const struct hc_driver *driver = &ohci_pnx4008_hc_driver;
+	struct i2c_adapter *i2c_adap;
+	struct i2c_board_info i2c_info;
+
+	int ret = 0, irq;
+
+	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (pnx4008)\n", hcd_name);
+	if (usb_disabled()) {
+		err("USB is disabled");
+		ret = -ENODEV;
+		goto out;
+	}
+
+	if (pdev->num_resources != 2
+	    || pdev->resource[0].flags != IORESOURCE_MEM
+	    || pdev->resource[1].flags != IORESOURCE_IRQ) {
+		err("Invalid resource configuration");
+		ret = -ENODEV;
+		goto out;
+	}
+
+	/* Enable AHB slave USB clock, needed for further USB clock control */
+	__raw_writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
+
+	ret = i2c_add_driver(&isp1301_driver);
+	if (ret < 0) {
+		err("failed to add ISP1301 driver");
+		goto out;
+	}
+	i2c_adap = i2c_get_adapter(2);
+	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
+	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
+	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
+						   normal_i2c, NULL);
+	i2c_put_adapter(i2c_adap);
+	if (!isp1301_i2c_client) {
+		err("failed to connect I2C to ISP1301 USB Transceiver");
+		ret = -ENODEV;
+		goto out_i2c_driver;
+	}
+
+	isp1301_configure();
+
+	/* Enable USB PLL */
+	usb_clk = clk_get(&pdev->dev, "ck_pll5");
+	if (IS_ERR(usb_clk)) {
+		err("failed to acquire USB PLL");
+		ret = PTR_ERR(usb_clk);
+		goto out1;
+	}
+
+	ret = clk_enable(usb_clk);
+	if (ret < 0) {
+		err("failed to start USB PLL");
+		goto out2;
+	}
+
+	ret = clk_set_rate(usb_clk, 48000);
+	if (ret < 0) {
+		err("failed to set USB clock rate");
+		goto out3;
+	}
+
+	__raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL);
+
+	/* Set to enable all needed USB clocks */
+	__raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL);
+
+	while ((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) !=
+	       USB_CLOCK_MASK) ;
+
+	hcd = usb_create_hcd (driver, &pdev->dev, dev_name(&pdev->dev));
+	if (!hcd) {
+		err("Failed to allocate HC buffer");
+		ret = -ENOMEM;
+		goto out3;
+	}
+
+	/* Set all USB bits in the Start Enable register */
+	pnx4008_set_usb_bits();
+
+	hcd->rsrc_start = pdev->resource[0].start;
+	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
+	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+		dev_dbg(&pdev->dev, "request_mem_region failed\n");
+		ret =  -ENOMEM;
+		goto out4;
+	}
+	hcd->regs = (void __iomem *)pdev->resource[0].start;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		ret = -ENXIO;
+		goto out4;
+	}
+
+	pnx4008_start_hc();
+	platform_set_drvdata(pdev, hcd);
+	ohci = hcd_to_ohci(hcd);
+	ohci_hcd_init(ohci);
+
+	dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq);
+	ret = usb_add_hcd(hcd, irq, 0);
+	if (ret == 0)
+		return ret;
+
+	pnx4008_stop_hc();
+out4:
+	pnx4008_unset_usb_bits();
+	usb_put_hcd(hcd);
+out3:
+	clk_disable(usb_clk);
+out2:
+	clk_put(usb_clk);
+out1:
+	i2c_unregister_device(isp1301_i2c_client);
+	isp1301_i2c_client = NULL;
+out_i2c_driver:
+	i2c_del_driver(&isp1301_driver);
+out:
+	return ret;
+}
+
+static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+	usb_remove_hcd(hcd);
+	pnx4008_stop_hc();
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	usb_put_hcd(hcd);
+	pnx4008_unset_usb_bits();
+	clk_disable(usb_clk);
+	clk_put(usb_clk);
+	i2c_unregister_device(isp1301_i2c_client);
+	isp1301_i2c_client = NULL;
+	i2c_del_driver(&isp1301_driver);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+/* work with hotplug and coldplug */
+MODULE_ALIAS("platform:usb-ohci");
+
+static struct platform_driver usb_hcd_pnx4008_driver = {
+	.driver = {
+		.name = "usb-ohci",
+		.owner	= THIS_MODULE,
+	},
+	.probe = usb_hcd_pnx4008_probe,
+	.remove = usb_hcd_pnx4008_remove,
+};
+
--- linux-2.6.orig/drivers/usb/host/ohci-pnx4008.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * drivers/usb/host/ohci-pnx4008.c
- *
- * driver for Philips PNX4008 USB Host
- *
- * Authors: Dmitry Chigirev <source at mvista.com>
- *	    Vitaly Wool <vitalywool at gmail.com>
- *
- * register initialization is based on code examples provided by Philips
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * NOTE: This driver does not have suspend/resume functionality
- * This driver is intended for engineering development purposes only
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-
-#include <mach/hardware.h>
-#include <asm/io.h>
-
-#include <mach/platform.h>
-#include <mach/irqs.h>
-#include <asm/gpio.h>
-
-#define USB_CTRL	IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64)
-
-/* USB_CTRL bit defines */
-#define USB_SLAVE_HCLK_EN	(1 << 24)
-#define USB_HOST_NEED_CLK_EN	(1 << 21)
-
-#define USB_OTG_CLK_CTRL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF4)
-#define USB_OTG_CLK_STAT	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF8)
-
-/* USB_OTG_CLK_CTRL bit defines */
-#define AHB_M_CLOCK_ON		(1 << 4)
-#define OTG_CLOCK_ON		(1 << 3)
-#define I2C_CLOCK_ON		(1 << 2)
-#define DEV_CLOCK_ON		(1 << 1)
-#define HOST_CLOCK_ON		(1 << 0)
-
-#define USB_OTG_STAT_CONTROL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x110)
-
-/* USB_OTG_STAT_CONTROL bit defines */
-#define TRANSPARENT_I2C_EN	(1 << 7)
-#define HOST_EN			(1 << 0)
-
-/* ISP1301 USB transceiver I2C registers */
-#define	ISP1301_MODE_CONTROL_1		0x04	/* u8 read, set, +1 clear */
-
-#define	MC1_SPEED_REG		(1 << 0)
-#define	MC1_SUSPEND_REG		(1 << 1)
-#define	MC1_DAT_SE0		(1 << 2)
-#define	MC1_TRANSPARENT		(1 << 3)
-#define	MC1_BDIS_ACON_EN	(1 << 4)
-#define	MC1_OE_INT_EN		(1 << 5)
-#define	MC1_UART_EN		(1 << 6)
-#define	MC1_MASK		0x7f
-
-#define	ISP1301_MODE_CONTROL_2		0x12	/* u8 read, set, +1 clear */
-
-#define	MC2_GLOBAL_PWR_DN	(1 << 0)
-#define	MC2_SPD_SUSP_CTRL	(1 << 1)
-#define	MC2_BI_DI		(1 << 2)
-#define	MC2_TRANSP_BDIR0	(1 << 3)
-#define	MC2_TRANSP_BDIR1	(1 << 4)
-#define	MC2_AUDIO_EN		(1 << 5)
-#define	MC2_PSW_EN		(1 << 6)
-#define	MC2_EN2V7		(1 << 7)
-
-#define	ISP1301_OTG_CONTROL_1		0x06	/* u8 read, set, +1 clear */
-#	define	OTG1_DP_PULLUP		(1 << 0)
-#	define	OTG1_DM_PULLUP		(1 << 1)
-#	define	OTG1_DP_PULLDOWN	(1 << 2)
-#	define	OTG1_DM_PULLDOWN	(1 << 3)
-#	define	OTG1_ID_PULLDOWN	(1 << 4)
-#	define	OTG1_VBUS_DRV		(1 << 5)
-#	define	OTG1_VBUS_DISCHRG	(1 << 6)
-#	define	OTG1_VBUS_CHRG		(1 << 7)
-#define	ISP1301_OTG_STATUS		0x10	/* u8 readonly */
-#	define	OTG_B_SESS_END		(1 << 6)
-#	define	OTG_B_SESS_VLD		(1 << 7)
-
-#define ISP1301_I2C_ADDR 0x2C
-
-#define ISP1301_I2C_MODE_CONTROL_1 0x4
-#define ISP1301_I2C_MODE_CONTROL_2 0x12
-#define ISP1301_I2C_OTG_CONTROL_1 0x6
-#define ISP1301_I2C_OTG_CONTROL_2 0x10
-#define ISP1301_I2C_INTERRUPT_SOURCE 0x8
-#define ISP1301_I2C_INTERRUPT_LATCH 0xA
-#define ISP1301_I2C_INTERRUPT_FALLING 0xC
-#define ISP1301_I2C_INTERRUPT_RISING 0xE
-#define ISP1301_I2C_REG_CLEAR_ADDR 1
-
-static struct i2c_driver isp1301_driver;
-static struct i2c_client *isp1301_i2c_client;
-
-extern int usb_disabled(void);
-extern int ocpi_enable(void);
-
-static struct clk *usb_clk;
-
-static const unsigned short normal_i2c[] =
-    { ISP1301_I2C_ADDR, ISP1301_I2C_ADDR + 1, I2C_CLIENT_END };
-
-static int isp1301_probe(struct i2c_client *client,
-			 const struct i2c_device_id *id)
-{
-	return 0;
-}
-
-static int isp1301_remove(struct i2c_client *client)
-{
-	return 0;
-}
-
-static const struct i2c_device_id isp1301_id[] = {
-	{ "isp1301_pnx", 0 },
-	{ }
-};
-
-static struct i2c_driver isp1301_driver = {
-	.driver = {
-		.name = "isp1301_pnx",
-	},
-	.probe = isp1301_probe,
-	.remove = isp1301_remove,
-	.id_table = isp1301_id,
-};
-
-static void i2c_write(u8 buf, u8 subaddr)
-{
-	char tmpbuf[2];
-
-	tmpbuf[0] = subaddr;	/*register number */
-	tmpbuf[1] = buf;	/*register data */
-	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
-}
-
-static void isp1301_configure(void)
-{
-	/* PNX4008 only supports DAT_SE0 USB mode */
-	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
-	/* Power up externel charge-pump */
-
-	i2c_write(MC1_DAT_SE0 | MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
-	i2c_write(~(MC1_DAT_SE0 | MC1_SPEED_REG),
-		  ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL,
-		  ISP1301_I2C_MODE_CONTROL_2);
-	i2c_write(~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
-		  ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN,
-		  ISP1301_I2C_OTG_CONTROL_1);
-	i2c_write(~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
-		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
-
-}
-
-static inline void isp1301_vbus_on(void)
-{
-	i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1);
-}
-
-static inline void isp1301_vbus_off(void)
-{
-	i2c_write(OTG1_VBUS_DRV,
-		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-}
-
-static void pnx4008_start_hc(void)
-{
-	unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
-	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
-	isp1301_vbus_on();
-}
-
-static void pnx4008_stop_hc(void)
-{
-	unsigned long tmp;
-	isp1301_vbus_off();
-	tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN;
-	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
-}
-
-static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd)
-{
-	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
-	int ret;
-
-	if ((ret = ohci_init(ohci)) < 0)
-		return ret;
-
-	if ((ret = ohci_run(ohci)) < 0) {
-		dev_err(hcd->self.controller, "can't start\n");
-		ohci_stop(hcd);
-		return ret;
-	}
-	return 0;
-}
-
-static const struct hc_driver ohci_pnx4008_hc_driver = {
-	.description = hcd_name,
-	.product_desc =		"pnx4008 OHCI",
-
-	/*
-	 * generic hardware linkage
-	 */
-	.irq = ohci_irq,
-	.flags = HCD_USB11 | HCD_MEMORY,
-
-	.hcd_priv_size =	sizeof(struct ohci_hcd),
-	/*
-	 * basic lifecycle operations
-	 */
-	.start = ohci_pnx4008_start,
-	.stop = ohci_stop,
-	.shutdown = ohci_shutdown,
-
-	/*
-	 * managing i/o requests and associated device resources
-	 */
-	.urb_enqueue = ohci_urb_enqueue,
-	.urb_dequeue = ohci_urb_dequeue,
-	.endpoint_disable = ohci_endpoint_disable,
-
-	/*
-	 * scheduling support
-	 */
-	.get_frame_number = ohci_get_frame,
-
-	/*
-	 * root hub support
-	 */
-	.hub_status_data = ohci_hub_status_data,
-	.hub_control = ohci_hub_control,
-#ifdef	CONFIG_PM
-	.bus_suspend = ohci_bus_suspend,
-	.bus_resume = ohci_bus_resume,
-#endif
-	.start_port_reset = ohci_start_port_reset,
-};
-
-#define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON)
-
-static void pnx4008_set_usb_bits(void)
-{
-	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-	start_int_ack(SE_USB_OTG_ATX_INT_N);
-	start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-	start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-	start_int_ack(SE_USB_OTG_TIMER_INT);
-	start_int_umask(SE_USB_OTG_TIMER_INT);
-
-	start_int_set_rising_edge(SE_USB_I2C_INT);
-	start_int_ack(SE_USB_I2C_INT);
-	start_int_umask(SE_USB_I2C_INT);
-
-	start_int_set_rising_edge(SE_USB_INT);
-	start_int_ack(SE_USB_INT);
-	start_int_umask(SE_USB_INT);
-
-	start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-	start_int_ack(SE_USB_NEED_CLK_INT);
-	start_int_umask(SE_USB_NEED_CLK_INT);
-
-	start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-	start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
-}
-
-static void pnx4008_unset_usb_bits(void)
-{
-	start_int_mask(SE_USB_OTG_ATX_INT_N);
-	start_int_mask(SE_USB_OTG_TIMER_INT);
-	start_int_mask(SE_USB_I2C_INT);
-	start_int_mask(SE_USB_INT);
-	start_int_mask(SE_USB_NEED_CLK_INT);
-	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
-}
-
-static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
-{
-	struct usb_hcd *hcd = 0;
-	struct ohci_hcd *ohci;
-	const struct hc_driver *driver = &ohci_pnx4008_hc_driver;
-	struct i2c_adapter *i2c_adap;
-	struct i2c_board_info i2c_info;
-
-	int ret = 0, irq;
-
-	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (pnx4008)\n", hcd_name);
-	if (usb_disabled()) {
-		err("USB is disabled");
-		ret = -ENODEV;
-		goto out;
-	}
-
-	if (pdev->num_resources != 2
-	    || pdev->resource[0].flags != IORESOURCE_MEM
-	    || pdev->resource[1].flags != IORESOURCE_IRQ) {
-		err("Invalid resource configuration");
-		ret = -ENODEV;
-		goto out;
-	}
-
-	/* Enable AHB slave USB clock, needed for further USB clock control */
-	__raw_writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
-
-	ret = i2c_add_driver(&isp1301_driver);
-	if (ret < 0) {
-		err("failed to add ISP1301 driver");
-		goto out;
-	}
-	i2c_adap = i2c_get_adapter(2);
-	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
-	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
-	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
-						   normal_i2c, NULL);
-	i2c_put_adapter(i2c_adap);
-	if (!isp1301_i2c_client) {
-		err("failed to connect I2C to ISP1301 USB Transceiver");
-		ret = -ENODEV;
-		goto out_i2c_driver;
-	}
-
-	isp1301_configure();
-
-	/* Enable USB PLL */
-	usb_clk = clk_get(&pdev->dev, "ck_pll5");
-	if (IS_ERR(usb_clk)) {
-		err("failed to acquire USB PLL");
-		ret = PTR_ERR(usb_clk);
-		goto out1;
-	}
-
-	ret = clk_enable(usb_clk);
-	if (ret < 0) {
-		err("failed to start USB PLL");
-		goto out2;
-	}
-
-	ret = clk_set_rate(usb_clk, 48000);
-	if (ret < 0) {
-		err("failed to set USB clock rate");
-		goto out3;
-	}
-
-	__raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL);
-
-	/* Set to enable all needed USB clocks */
-	__raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL);
-
-	while ((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) !=
-	       USB_CLOCK_MASK) ;
-
-	hcd = usb_create_hcd (driver, &pdev->dev, dev_name(&pdev->dev));
-	if (!hcd) {
-		err("Failed to allocate HC buffer");
-		ret = -ENOMEM;
-		goto out3;
-	}
-
-	/* Set all USB bits in the Start Enable register */
-	pnx4008_set_usb_bits();
-
-	hcd->rsrc_start = pdev->resource[0].start;
-	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
-	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
-		dev_dbg(&pdev->dev, "request_mem_region failed\n");
-		ret =  -ENOMEM;
-		goto out4;
-	}
-	hcd->regs = (void __iomem *)pdev->resource[0].start;
-
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
-		ret = -ENXIO;
-		goto out4;
-	}
-
-	pnx4008_start_hc();
-	platform_set_drvdata(pdev, hcd);
-	ohci = hcd_to_ohci(hcd);
-	ohci_hcd_init(ohci);
-
-	dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq);
-	ret = usb_add_hcd(hcd, irq, 0);
-	if (ret == 0)
-		return ret;
-
-	pnx4008_stop_hc();
-out4:
-	pnx4008_unset_usb_bits();
-	usb_put_hcd(hcd);
-out3:
-	clk_disable(usb_clk);
-out2:
-	clk_put(usb_clk);
-out1:
-	i2c_unregister_device(isp1301_i2c_client);
-	isp1301_i2c_client = NULL;
-out_i2c_driver:
-	i2c_del_driver(&isp1301_driver);
-out:
-	return ret;
-}
-
-static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
-{
-	struct usb_hcd *hcd = platform_get_drvdata(pdev);
-
-	usb_remove_hcd(hcd);
-	pnx4008_stop_hc();
-	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-	usb_put_hcd(hcd);
-	pnx4008_unset_usb_bits();
-	clk_disable(usb_clk);
-	clk_put(usb_clk);
-	i2c_unregister_device(isp1301_i2c_client);
-	isp1301_i2c_client = NULL;
-	i2c_del_driver(&isp1301_driver);
-
-	platform_set_drvdata(pdev, NULL);
-
-	return 0;
-}
-
-/* work with hotplug and coldplug */
-MODULE_ALIAS("platform:usb-ohci");
-
-static struct platform_driver usb_hcd_pnx4008_driver = {
-	.driver = {
-		.name = "usb-ohci",
-		.owner	= THIS_MODULE,
-	},
-	.probe = usb_hcd_pnx4008_probe,
-	.remove = usb_hcd_pnx4008_remove,
-};
-


From olof at lixom.net  Sat Mar 10 13:10:38 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 10:10:38 -0800
Subject: [GIT PULL 3/4] Samsung devel-mmc for v3.4
In-Reply-To: <CAOesGMgx-86rUuOfjTN8BeYZD+S=04oj+N9u-m9dr8JQA1Oxiw@mail.gmail.com>
References: <4F5B7C8D.5000805@samsung.com>
 <CAOesGMgx-86rUuOfjTN8BeYZD+S=04oj+N9u-m9dr8JQA1Oxiw@mail.gmail.com>
Message-ID: <CAOesGMjPqWbKQ+kSKa6EfTpBwE3-3aBWTRoDDr9bGF-HuLcpGg@mail.gmail.com>

On Sat, Mar 10, 2012 at 10:08 AM, Olof Johansson <olof at lixom.net> wrote:
> Hi,
>
> On Sat, Mar 10, 2012 at 8:08 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>> Hi Arnd, Olof
>>
>> This is regarding Samsung mmc for v3.4.
>>
>> As a note, v3.4-for-cjb branch is merged into mmc/mmc-next like following:
>> http://git.kernel.org/?p=linux/kernel/git/cjb/mmc.git;a=commit;h=fcd9bdae386753531a9cb6b2577359a83f4e121c
>
> Looking at this series, there's really only one patch that is not in
> the mmc tree:
>
> ARM: SAMSUNG: change the name from s3c-sdhci to exynos4-sdhci
>
> And all it does is change the platform device string contents.
>
> Since there are no build-time dependencies between this and the MMC
> change, I suggest you send only this patch so that we avoid having
> merge dependencies where not strictly needed.
>
> Would that be OK with you? If so, please send a fresh pull request
> with only the above change in it.

Sorry, I misread the series when browsing it. Looks like there are two
more patches in it:

mmc: sdhci-s3c: add platform data for the second capability
ARM: SAMSUNG: support the second capability for samsung-soc

But the original suggestion remains, since those two seem to be
unrelated to the branch sent to Chris. So please resend with just
those patches, please?


Thanks,

-Olof


From tomi.valkeinen at ti.com  Fri Mar  9 03:11:58 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 09 Mar 2012 10:11:58 +0200
Subject: [PATCH] ARM: OMAP2+: Fix compile error when FB_OMAP2 is not set
In-Reply-To: <20120308204607.GX12083@atomide.com>
References: <20120308204328.GW12083@atomide.com>
 <20120308204607.GX12083@atomide.com>
Message-ID: <1331280718.1927.10.camel@deskari>

On Thu, 2012-03-08 at 12:46 -0800, Tony Lindgren wrote:
> * Tony Lindgren <tony at atomide.com> [120308 12:11]:
> > Otherwise we will get:
> > 
> > arch/arm/plat-omap/fb.c:101: error: expected ?)? before ?*? token
> > 
> > Signed-off-by: Tony Lindgren <tony at atomide.com>
> > 
> > ---
> > 
> > Tomi, you need something like this for what you have in for-next.
> > 
> > --- a/arch/arm/plat-omap/fb.c
> > +++ b/arch/arm/plat-omap/fb.c
> > @@ -98,6 +98,8 @@ arch_initcall(omap_init_fb);
> >  
> >  #else
> >  
> > -void __init omapfb_set_lcd_config(omap_lcd_config *config) { }
> > +void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
> > +{
> > +}
> >  
> >  #endif
> 
> Also now seeing the following with what you have in for-next:
> 
> drivers/video/omap2/displays/panel-taal.c: In function ?taal_num_errors_show?:
> drivers/video/omap2/displays/panel-taal.c:605: warning: ?errors? may be used uninitialized in this function

Hmm, my compiler doesn't complain (codesourcery 2010.09-50), so I didn't
notice that. Which compiler version reports the warning?

I'm not 100% sure, but I think it's a false warning, the code path that
uses "errors" should only be ran when "errors" has been set.

 Tomi

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From grant.likely at secretlab.ca  Fri Mar  9 10:24:10 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 09 Mar 2012 08:24:10 -0700
Subject: [PATCH v2 1/7] serial: pxa: add OF support
In-Reply-To: <1330950111-30797-2-git-send-email-haojian.zhuang@marvell.com>
References: <1330950111-30797-1-git-send-email-haojian.zhuang@marvell.com>
 <1330950111-30797-2-git-send-email-haojian.zhuang@marvell.com>
Message-ID: <20120309152410.4E59C3E0908@localhost>

On Mon,  5 Mar 2012 20:21:45 +0800, Haojian Zhuang <haojian.zhuang at marvell.com> wrote:
> Parse uart device id from alias in DTS file.
> 
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
> ---
>  drivers/tty/serial/pxa.c |   65 +++++++++++++++++++++++++++++++++++++--------
>  1 files changed, 53 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
> index 5c8e3bb..a71855b 100644
> --- a/drivers/tty/serial/pxa.c
> +++ b/drivers/tty/serial/pxa.c
> @@ -36,6 +36,7 @@
>  #include <linux/circ_buf.h>
>  #include <linux/delay.h>
>  #include <linux/interrupt.h>
> +#include <linux/of.h>
>  #include <linux/platform_device.h>
>  #include <linux/tty.h>
>  #include <linux/tty_flip.h>
> @@ -44,6 +45,8 @@
>  #include <linux/io.h>
>  #include <linux/slab.h>
>  
> +#define PXA_NAME_LEN		8
> +
>  struct uart_pxa_port {
>  	struct uart_port        port;
>  	unsigned char           ier;
> @@ -781,6 +784,39 @@ static const struct dev_pm_ops serial_pxa_pm_ops = {
>  };
>  #endif
>  
> +static struct of_device_id serial_pxa_dt_ids[] = {
> +	{ .compatible = "mrvl,pxa-uart", },
> +	{ .compatible = "mrvl,mmp-uart", },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids);
> +
> +#ifdef CONFIG_OF
> +static int serial_pxa_probe_dt(struct platform_device *pdev,
> +			       struct uart_pxa_port *sport)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	int ret;
> +
> +	if (!np)
> +		return 1;
> +
> +	ret = of_alias_get_id(np, "serial");
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
> +		return ret;
> +	}
> +	sport->port.line = ret;
> +	return 0;
> +}
> +#else
> +static int serial_pxa_probe_dt(struct platform_device *pdev,
> +			       struct uart_pxa_port *sport)
> +{
> +	return 1;
> +}
> +#endif

Returning 1 on success is rather odd... see comment below.

> +
>  static int serial_pxa_probe(struct platform_device *dev)
>  {
>  	struct uart_pxa_port *sport;
> @@ -808,34 +844,37 @@ static int serial_pxa_probe(struct platform_device *dev)
>  	sport->port.irq = irqres->start;
>  	sport->port.fifosize = 64;
>  	sport->port.ops = &serial_pxa_pops;
> -	sport->port.line = dev->id;
>  	sport->port.dev = &dev->dev;
>  	sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
>  	sport->port.uartclk = clk_get_rate(sport->clk);
> -
> -	switch (dev->id) {
> -	case 0: sport->name = "FFUART"; break;
> -	case 1: sport->name = "BTUART"; break;
> -	case 2: sport->name = "STUART"; break;
> -	case 3: sport->name = "HWUART"; break;
> -	default:
> -		sport->name = "???";
> -		break;
> +	sport->name = kzalloc(PXA_NAME_LEN, GFP_KERNEL);

devm_kzalloc().  Then you don't need to unwind the allocation on failure.

> +	if (!sport->name) {
> +		ret = -ENOMEM;
> +		goto err_clk;
>  	}
>  
> +	ret = serial_pxa_probe_dt(dev, sport);
> +	if (ret > 0)
> +		sport->port.line = dev->id;
> +	else if (ret < 0)
> +		goto err_clk;
> +	snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);

returning a -/0/+ value from serial_pxa_probe_dt() is rather odd.  It's easier
to follow code which sticks to the convention of <0 for error, 0 for success.
I would do:

	sport->port.line = dev->id;
	ret = serial_pxa_probe_dt(dev, sport);
	if (ret < 0)
		goto err_clk;

Then serial_pxa_probe_dt() can return an error code on failure, or 0 on
success or no-devicetree.


> +
>  	sport->port.membase = ioremap(mmres->start, resource_size(mmres));
>  	if (!sport->port.membase) {
>  		ret = -ENOMEM;
> -		goto err_clk;
> +		goto err_name;
>  	}
>  
> -	serial_pxa_ports[dev->id] = sport;
> +	serial_pxa_ports[sport->port.line] = sport;
>  
>  	uart_add_one_port(&serial_pxa_reg, &sport->port);
>  	platform_set_drvdata(dev, sport);
>  
>  	return 0;
>  
> + err_name:
> +	kfree(sport->name);
>   err_clk:
>  	clk_put(sport->clk);
>   err_free:
> @@ -850,6 +889,7 @@ static int serial_pxa_remove(struct platform_device *dev)
>  	platform_set_drvdata(dev, NULL);
>  
>  	uart_remove_one_port(&serial_pxa_reg, &sport->port);
> +	kfree(sport->name);
>  	clk_put(sport->clk);
>  	kfree(sport);
>  
> @@ -866,6 +906,7 @@ static struct platform_driver serial_pxa_driver = {
>  #ifdef CONFIG_PM
>  		.pm	= &serial_pxa_pm_ops,
>  #endif
> +		.of_match_table = serial_pxa_dt_ids,

	.of_match_table = of_match_ptr(serial_pxa_dt_ids),

Otherwise looks great to me.

g.


From joerg.roedel at amd.com  Mon Mar 12 11:01:56 2012
From: joerg.roedel at amd.com (Joerg Roedel)
Date: Mon, 12 Mar 2012 16:01:56 +0100
Subject: [PATCH v11 3/3] iommu/exynos: Add iommu driver for Exynos
 Platforms
In-Reply-To: <017a01ccfdee$4e5e7a00$eb1b6e00$%cho@samsung.com>
References: <017a01ccfdee$4e5e7a00$eb1b6e00$%cho@samsung.com>
Message-ID: <20120312150156.GF18973@amd.com>

On Fri, Mar 09, 2012 at 09:15:24PM +0900, Cho KyongHo wrote:
> +/* We does not consider super section mapping (16MB) */
> +struct iommu_client {
> +	struct list_head node;
> +	struct device *dev;
> +};
> +
> +struct exynos_iommu_domain {
> +	struct list_head clients; /* list of iommu_client */
> +	unsigned long *pgtable; /* lv1 page table, 16KB */
> +	short *lv2entcnt; /* free lv2 entry counter for each section */
> +	spinlock_t lock; /* lock for this structure and attached iommu_client */
> +	spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
> +};
> +
> +struct sysmmu_drvdata {
> +	struct device *sysmmu;
> +	char *dbgname;
> +	int nsfrs;
> +	void __iomem **sfrbases;
> +	struct clk *clk[2];
> +	int activations;
> +	rwlock_t lock;
> +	struct iommu_domain *domain;
> +	sysmmu_fault_handler_t fault_handler;
> +	unsigned long pgtable;
> +	struct iommu_client client;
> +};

Is there any reason why 'struct iommu_client' is a seperate data
structure? Otherwise it can be merged with 'truct sysmmu_drvdata'.

> +static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
> +{
> +	struct exynos_iommu_domain *priv = domain->priv;
> +	struct list_head *pos, *n;
> +	unsigned long flags;
> +	int i;
> +
> +	WARN_ON(!list_empty(&priv->clients));
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +
> +	list_for_each_safe(pos, n, &priv->clients) {
> +		struct iommu_client *client;
> +
> +		client = list_entry(pos, struct iommu_client, node);
> +		exynos_sysmmu_disable(client->dev);
> +		kfree(client);
> +	}

Why this kfree here? Aren't all iommu_clients just a part of another
data-structre?


-- 
AMD Operating System Research Center

Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632



From marek.vasut at gmail.com  Mon Mar 12 13:44:24 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 12 Mar 2012 18:44:24 +0100
Subject: [PATCH 1/2] ARM: Add Kconfig option to use mkimage -T
 kernel_noload
In-Reply-To: <4F4EBA8C.1040408@gmail.com>
References: <1330473804-23348-1-git-send-email-swarren@nvidia.com>
 <20120229194409.GO14173@pengutronix.de> <4F4EBA8C.1040408@gmail.com>
Message-ID: <201203121844.24744.marek.vasut@gmail.com>

Dear Ryan Mallon,

> On 01/03/12 06:44, Uwe Kleine-K?nig wrote:
> > On Wed, Feb 29, 2012 at 11:17:41AM -0800, Stephen Warren wrote:
> >> Uwe Kleine-K?nig wrote at Wednesday, February 29, 2012 12:12 PM:
> >>> On Wed, Feb 29, 2012 at 10:33:58AM -0800, Tim Bird wrote:
> >>>> On 02/29/2012 10:14 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>>>> On 08:58 Wed 29 Feb     , Stephen Warren wrote:
> >>>>>> Jean-Christophe PLAGNIOL-VILLARD wrote at Wednesday, February 29, 2012 
5:30 AM:
> >>>>>>> On 17:03 Tue 28 Feb     , Stephen Warren wrote:
> <snip>
> 
> >> The existing target works just fine today.
> > 
> > It depends what you want to achieve. If you want to make everything
> > maximally easy for everyone you can optimize the uImage target.
> > 
> > If you want to give incentive for U-Boot to improve, drop the target
> > today.
> 
> This assumes that people will upgrade their bootloaders, which is not
> always possible or desirable.
> 
> ~Ryan
> 

Agreed 201%

Best regards,
Marek Vasut


From jonsmirl at gmail.com  Mon Mar 12 16:03:09 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Mon, 12 Mar 2012 16:03:09 -0400
Subject: ARM926EJS boot failure on v3.3, __iounmap
Message-ID: <CAKON4OzL9HtF+3bxzC9zexd7QgAFd5R7Wr=QTShYR+Kk1b4L+g@mail.gmail.com>

I'm working on getting out of tree support for the NXP LPC31xx
ARM926EJS based CPUs ready for submission. Everything was working fine
on v3.2 but I lost the ability to boot with v3.3. The boot failure is
very early in the boot process. I did a bisect and came up with:

[6ee723a6570a897208b76ab3e9a495e9106b2f8c] ARM: simplify __iounmap()
when dealing with section based mapping

I tried to revert it but there have been a bunch of edits in this
file. Not sure how to go about debugging this.

-- 
Jon Smirl
jonsmirl at gmail.com


From shawn.guo at linaro.org  Mon Mar 12 07:58:52 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 12 Mar 2012 19:58:52 +0800
Subject: [PATCH v4 05/10] ASoC: fsl: remove helper fsl_asoc_get_codec_dev_name
In-Reply-To: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331553537-19789-6-git-send-email-shawn.guo@linaro.org>

The ASoC core now can support matching codec with device node besides
name, so we can save helper function fsl_asoc_get_codec_dev_name.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_utils.c    |   44 ------------------------------------------
 sound/soc/fsl/fsl_utils.h    |    1 -
 sound/soc/fsl/mpc8610_hpcd.c |   13 +----------
 sound/soc/fsl/p1022_ds.c     |   13 +----------
 4 files changed, 4 insertions(+), 67 deletions(-)

diff --git a/sound/soc/fsl/fsl_utils.c b/sound/soc/fsl/fsl_utils.c
index 4370c28..b9e42b5 100644
--- a/sound/soc/fsl/fsl_utils.c
+++ b/sound/soc/fsl/fsl_utils.c
@@ -12,55 +12,11 @@
 
 #include <linux/module.h>
 #include <linux/of_address.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 
 #include "fsl_utils.h"
 
 /**
- * fsl_asoc_get_codec_dev_name - determine the dev_name for a codec node
- *
- * @np: pointer to the I2C device tree node
- * @buf: buffer to be filled with the dev_name of the I2C device
- * @len: the length of the buffer
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270.0-004f".
- */
-int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	u32 addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c) {
-		put_device(&i2c->dev);
-		return -ENODEV;
-	}
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-	put_device(&i2c->dev);
-
-	return 0;
-}
-EXPORT_SYMBOL(fsl_asoc_get_codec_dev_name);
-
-/**
  * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
  *
  * @ssi_np: pointer to the SSI device tree node
diff --git a/sound/soc/fsl/fsl_utils.h b/sound/soc/fsl/fsl_utils.h
index 44d1436..b295112 100644
--- a/sound/soc/fsl/fsl_utils.h
+++ b/sound/soc/fsl/fsl_utils.h
@@ -18,7 +18,6 @@
 struct snd_soc_dai_link;
 struct device_node;
 
-int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len);
 int fsl_asoc_get_dma_channel(struct device_node *ssi_np, const char *name,
 			     struct snd_soc_dai_link *dai,
 			     unsigned int *dma_channel_id,
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index 7ead1e5..354b753 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -41,7 +41,6 @@ struct mpc8610_hpcd_data {
 	unsigned int dma_id[2];		/* 0 = DMA1, 1 = DMA2, etc */
 	unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
 	char codec_dai_name[DAI_NAME_SIZE];
-	char codec_name[DAI_NAME_SIZE];
 	char platform_name[2][DAI_NAME_SIZE]; /* One for each DMA channel */
 };
 
@@ -215,16 +214,8 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 	machine_data->dai[0].cpu_dai_name = dev_name(&ssi_pdev->dev);
 	machine_data->dai[0].ops = &mpc8610_hpcd_ops;
 
-	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = fsl_asoc_get_codec_dev_name(codec_np, machine_data->codec_name,
-					  DAI_NAME_SIZE);
-	if (ret) {
-		dev_err(&pdev->dev, "invalid codec node %s\n",
-			codec_np->full_name);
-		ret = -EINVAL;
-		goto error;
-	}
-	machine_data->dai[0].codec_name = machine_data->codec_name;
+	/* ASoC core can match codec with device node */
+	machine_data->dai[0].codec_of_node = codec_np;
 
 	/* The DAI name from the codec (snd_soc_dai_driver.name) */
 	machine_data->dai[0].codec_dai_name = "cs4270-hifi";
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index 60f7bb8..e87cb41 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -73,7 +73,6 @@ struct machine_data {
 	unsigned int ssi_id;		/* 0 = SSI1, 1 = SSI2, etc */
 	unsigned int dma_id[2];		/* 0 = DMA1, 1 = DMA2, etc */
 	unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
-	char codec_name[DAI_NAME_SIZE];
 	char platform_name[2][DAI_NAME_SIZE]; /* One for each DMA channel */
 };
 
@@ -225,16 +224,8 @@ static int p1022_ds_probe(struct platform_device *pdev)
 	mdata->dai[0].cpu_dai_name = dev_name(&ssi_pdev->dev);
 	mdata->dai[0].ops = &p1022_ds_ops;
 
-	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = fsl_asoc_get_codec_dev_name(codec_np, mdata->codec_name,
-					  DAI_NAME_SIZE);
-	if (ret) {
-		dev_err(&pdev->dev, "invalid codec node %s\n",
-			codec_np->full_name);
-		ret = -EINVAL;
-		goto error;
-	}
-	mdata->dai[0].codec_name = mdata->codec_name;
+	/* ASoC core can match codec with device node */
+	mdata->dai[0].codec_of_node = codec_np;
 
 	/* We register two DAIs per SSI, one for playback and the other for
 	 * capture.  We support codecs that have separate DAIs for both playback
-- 
1.7.5.4



From thomas.abraham at linaro.org  Mon Mar 12 16:59:58 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 02:29:58 +0530
Subject: [PATCH v2 2/3] video: s3c-fb: remove 'default_win' element from
 platform data
In-Reply-To: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1331585999-8604-3-git-send-email-thomas.abraham@linaro.org>

The decision to enable or disable the data output to the lcd panel from
the controller need not be based on the value of 'default_win' element
in the platform data. Instead, the data output to the panel is enabled
if any of the windows are active, else data output is disabled.

Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Jingoo Han <jg1.han at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/plat-samsung/include/plat/fb.h |    2 --
 drivers/video/s3c-fb.c                  |   28 ++++++----------------------
 2 files changed, 6 insertions(+), 24 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 39d6bd7..536002f 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -62,8 +62,6 @@ struct s3c_fb_platdata {
 	struct s3c_fb_pd_win	*win[S3C_FB_MAX_WIN];
 	struct fb_videomode     *vtiming;
 
-	u32			 default_win;
-
 	u32			 vidcon0;
 	u32			 vidcon1;
 };
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 60d1c12..cfe5113 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -531,8 +531,8 @@ static int s3c_fb_set_par(struct fb_info *info)
 	/* disable the window whilst we update it */
 	writel(0, regs + WINCON(win_no));
 
-	if (win_no == sfb->pdata->default_win)
- 		s3c_fb_enable(sfb, 1);
+	if (!sfb->output_on)
+		s3c_fb_enable(sfb, 1);
 
 	/* write the buffer address */
 
@@ -798,7 +798,7 @@ static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 	struct s3c_fb_win *win = info->par;
 	struct s3c_fb *sfb = win->parent;
 	unsigned int index = win->index;
-	u32 wincon;
+	u32 wincon, output_on = sfb->output_on;
 
 	dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
 
@@ -837,34 +837,18 @@ static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 
 	shadow_protect_win(win, 1);
 	writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
-	shadow_protect_win(win, 0);
 
 	/* Check the enabled state to see if we need to be running the
 	 * main LCD interface, as if there are no active windows then
 	 * it is highly likely that we also do not need to output
 	 * anything.
 	 */
-
-	/* We could do something like the following code, but the current
-	 * system of using framebuffer events means that we cannot make
-	 * the distinction between just window 0 being inactive and all
-	 * the windows being down.
-	 *
-	 * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
-	*/
-
-	/* we're stuck with this until we can do something about overriding
-	 * the power control using the blanking event for a single fb.
-	 */
-	if (index == sfb->pdata->default_win) {
-		shadow_protect_win(win, 1);
-		s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
-		shadow_protect_win(win, 0);
-	}
+	s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
+	shadow_protect_win(win, 0);
 
 	pm_runtime_put_sync(sfb->dev);
 
-	return 0;
+	return output_on == sfb->output_on;
 }
 
 /**
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Mon Mar 12 16:59:59 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 02:29:59 +0530
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>

For all the Samsung SoC based boards which have the platform data for
s3c-fb driver, the 'default_win' element in the platform data is removed
and the lcd panel video timing values are moved out of individual window
configuration data.

Cc: Jingoo Han <jg1.han at samsung.com>
Cc: Kyungmin Park <kyungmin.park at samsung.com>
Cc: JeongHyeon Kim <jhkim at insignal.co.kr>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Heiko Stuebner <heiko at sntech.de>
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Kwangwoo Lee <kwangwoo.lee at gmail.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Peter Korsgaard <jacmet at sunsite.dk>
Cc: Darius Augulis <augulis.darius at gmail.com>
Cc: Maurus Cuelenaere <mcuelenaere at gmail.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/mach-nuri.c           |   26 ++++++++++-------
 arch/arm/mach-exynos/mach-origen.c         |   24 ++++++++++-------
 arch/arm/mach-exynos/mach-smdkv310.c       |   28 +++++++++++--------
 arch/arm/mach-exynos/mach-universal_c210.c |   26 ++++++++++-------
 arch/arm/mach-s3c24xx/mach-smdk2416.c      |   27 ++++++++++--------
 arch/arm/mach-s3c64xx/mach-anw6410.c       |   25 ++++++++++-------
 arch/arm/mach-s3c64xx/mach-crag6410.c      |   25 ++++++++++-------
 arch/arm/mach-s3c64xx/mach-hmt.c           |   24 ++++++++++-------
 arch/arm/mach-s3c64xx/mach-mini6410.c      |   40 ++++++++++++---------------
 arch/arm/mach-s3c64xx/mach-real6410.c      |   40 ++++++++++++---------------
 arch/arm/mach-s3c64xx/mach-smartq5.c       |   26 ++++++++++-------
 arch/arm/mach-s3c64xx/mach-smartq7.c       |   26 ++++++++++-------
 arch/arm/mach-s3c64xx/mach-smdk6410.c      |   25 ++++++++++-------
 arch/arm/mach-s5p64x0/mach-smdk6440.c      |   24 ++++++++++-------
 arch/arm/mach-s5p64x0/mach-smdk6450.c      |   24 ++++++++++-------
 arch/arm/mach-s5pc100/mach-smdkc100.c      |   27 ++++++++++--------
 arch/arm/mach-s5pv210/mach-aquila.c        |   36 +++++++++++--------------
 arch/arm/mach-s5pv210/mach-goni.c          |   26 ++++++++++-------
 arch/arm/mach-s5pv210/mach-smdkv210.c      |   24 ++++++++++-------
 19 files changed, 285 insertions(+), 238 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 7ac81ce..a7e6731 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -212,25 +212,29 @@ static struct platform_device nuri_gpio_keys = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win nuri_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 64,
-		.right_margin	= 16,
-		.upper_margin	= 64,
-		.lower_margin	= 1,
-		.hsync_len	= 48,
-		.vsync_len	= 3,
-		.xres		= 1024,
-		.yres		= 600,
-		.refresh	= 60,
-	},
 	.max_bpp	= 24,
 	.default_bpp	= 16,
+	.xres		= 1024,
+	.yres		= 600,
 	.virtual_x	= 1024,
 	.virtual_y	= 2 * 600,
 };
 
+static struct fb_videomode nuri_lcd_timing = {
+	.left_margin	= 64,
+	.right_margin	= 16,
+	.upper_margin	= 64,
+	.lower_margin	= 1,
+	.hsync_len	= 48,
+	.vsync_len	= 3,
+	.xres		= 1024,
+	.yres		= 600,
+	.refresh	= 60,
+};
+
 static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
 	.win[0]		= &nuri_fb_win0,
+	.vtiming	= &nuri_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
 			  VIDCON0_CLKSEL_LCD,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 25c9b46..de71237 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -583,22 +583,26 @@ static struct platform_device origen_lcd_hv070wsa = {
 };
 
 static struct s3c_fb_pd_win origen_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 64,
-		.right_margin	= 16,
-		.upper_margin	= 64,
-		.lower_margin	= 16,
-		.hsync_len	= 48,
-		.vsync_len	= 3,
-		.xres		= 1024,
-		.yres		= 600,
-	},
+	.xres			= 1024,
+	.yres			= 600,
 	.max_bpp		= 32,
 	.default_bpp		= 24,
 };
 
+static struct fb_videomode origen_lcd_timing = {
+	.left_margin	= 64,
+	.right_margin	= 16,
+	.upper_margin	= 64,
+	.lower_margin	= 16,
+	.hsync_len	= 48,
+	.vsync_len	= 3,
+	.xres		= 1024,
+	.yres		= 600,
+};
+
 static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
 	.win[0]		= &origen_fb_win0,
+	.vtiming	= &origen_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
 				VIDCON1_INV_VCLK,
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index f08529f..6c00fa6 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -157,22 +157,26 @@ static struct platform_device smdkv310_lcd_lte480wv = {
 };
 
 static struct s3c_fb_pd_win smdkv310_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 13,
-		.right_margin	= 8,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
-	.max_bpp		= 32,
-	.default_bpp		= 24,
+	.max_bpp	= 32,
+	.default_bpp	= 24,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smdkv310_lcd_timing = {
+	.left_margin	= 13,
+	.right_margin	= 8,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
 	.win[0]		= &smdkv310_fb_win0,
+	.vtiming	= &smdkv310_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 57e4418..67a9547 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -813,25 +813,29 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win universal_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 16,
-		.right_margin	= 16,
-		.upper_margin	= 2,
-		.lower_margin	= 28,
-		.hsync_len	= 2,
-		.vsync_len	= 1,
-		.xres		= 480,
-		.yres		= 800,
-		.refresh	= 55,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 480,
+	.yres		= 800,
 	.virtual_x	= 480,
 	.virtual_y	= 2 * 800,
 };
 
+static struct fb_videomode universal_lcd_timing = {
+	.left_margin	= 16,
+	.right_margin	= 16,
+	.upper_margin	= 2,
+	.lower_margin	= 28,
+	.hsync_len	= 2,
+	.vsync_len	= 1,
+	.xres		= 480,
+	.yres		= 800,
+	.refresh	= 55,
+};
+
 static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
 	.win[0]		= &universal_fb_win0,
+	.vtiming	= &universal_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
 			  VIDCON0_CLKSEL_LCD,
 	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index 30a44f8..c3100a0 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -148,23 +148,25 @@ static struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
 
 static struct s3c_fb_pd_win smdk2416_fb_win[] = {
 	[0] = {
-		/* think this is the same as the smdk6410 */
-		.win_mode	= {
-			.pixclock	= 41094,
-			.left_margin	= 8,
-			.right_margin	= 13,
-			.upper_margin	= 7,
-			.lower_margin	= 5,
-			.hsync_len	= 3,
-			.vsync_len	= 1,
-			.xres           = 800,
-			.yres           = 480,
-		},
 		.default_bpp	= 16,
 		.max_bpp	= 32,
+		.xres           = 800,
+		.yres           = 480,
 	},
 };
 
+static struct fb_videomode smdk2416_lcd_timing = {
+	.pixclock	= 41094,
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres           = 800,
+	.yres           = 480,
+};
+
 static void s3c2416_fb_gpio_setup_24bpp(void)
 {
 	unsigned int gpio;
@@ -187,6 +189,7 @@ static void s3c2416_fb_gpio_setup_24bpp(void)
 
 static struct s3c_fb_platdata smdk2416_fb_platdata = {
 	.win[0]		= &smdk2416_fb_win[0],
+	.vtiming	= &smdk2416_lcd_timing,
 	.setup_gpio	= s3c2416_fb_gpio_setup_24bpp,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index b86f277..58fd0e3 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -134,24 +134,27 @@ static struct platform_device anw6410_lcd_powerdev = {
 };
 
 static struct s3c_fb_pd_win anw6410_fb_win0 = {
-	/* this is to ensure we use win0 */
-	.win_mode	= {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode anw6410_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
 static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &anw6410_lcd_timing,
 	.win[0]		= &anw6410_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index e20bf58..c1ef57e 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -151,26 +151,29 @@ static struct platform_device crag6410_lcd_powerdev = {
 
 /* 640x480 URT */
 static struct s3c_fb_pd_win crag6410_fb_win0 = {
-	/* this is to ensure we use win0 */
-	.win_mode	= {
-		.left_margin	= 150,
-		.right_margin	= 80,
-		.upper_margin	= 40,
-		.lower_margin	= 5,
-		.hsync_len	= 40,
-		.vsync_len	= 5,
-		.xres		= 640,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 640,
+	.yres		= 480,
 	.virtual_y	= 480 * 2,
 	.virtual_x	= 640,
 };
 
+static struct fb_videomode crag6410_lcd_timing = {
+	.left_margin	= 150,
+	.right_margin	= 80,
+	.upper_margin	= 40,
+	.lower_margin	= 5,
+	.hsync_len	= 40,
+	.vsync_len	= 5,
+	.xres		= 640,
+	.yres		= 480,
+};
+
 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
 static struct s3c_fb_platdata crag6410_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &crag6410_lcd_timing,
 	.win[0]		= &crag6410_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 521e07b..4e9b1ac 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -129,23 +129,27 @@ static struct platform_device hmt_backlight_device = {
 };
 
 static struct s3c_fb_pd_win hmt_fb_win0 = {
-	.win_mode	= {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode hmt_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
 static struct s3c_fb_platdata hmt_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &hmt_lcd_timing,
 	.win[0]		= &hmt_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index c34c2ab..24dcdc9 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -153,36 +153,32 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
 
 static struct s3c_fb_pd_win mini6410_fb_win[] = {
 	{
-		.win_mode	= {	/* 4.3" 480x272 */
-			.left_margin	= 3,
-			.right_margin	= 2,
-			.upper_margin	= 1,
-			.lower_margin	= 1,
-			.hsync_len	= 40,
-			.vsync_len	= 1,
-			.xres		= 480,
-			.yres		= 272,
-		},
 		.max_bpp	= 32,
 		.default_bpp	= 16,
+		.xres		= 480,
+		.yres		= 272,
 	}, {
-		.win_mode	= {	/* 7.0" 800x480 */
-			.left_margin	= 8,
-			.right_margin	= 13,
-			.upper_margin	= 7,
-			.lower_margin	= 5,
-			.hsync_len	= 3,
-			.vsync_len	= 1,
-			.xres		= 800,
-			.yres		= 480,
-		},
 		.max_bpp	= 32,
 		.default_bpp	= 16,
+		.xres		= 800,
+		.yres		= 480,
 	},
 };
 
+static struct fb_videomode mini6410_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
+};
+
 static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &mini6410_lcd_timing,
 	.win[0]		= &mini6410_fb_win[0],
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
@@ -310,8 +306,8 @@ static void __init mini6410_machine_init(void)
 	mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
 
 	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
-		mini6410_lcd_pdata.win[0]->win_mode.xres,
-		mini6410_lcd_pdata.win[0]->win_mode.yres);
+		mini6410_lcd_pdata.win[0]->xres,
+		mini6410_lcd_pdata.win[0]->yres);
 
 	s3c_nand_set_platdata(&mini6410_nand_info);
 	s3c_fb_set_platdata(&mini6410_lcd_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index be2a9a2..41e4f74 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -119,36 +119,32 @@ static struct platform_device real6410_device_eth = {
 
 static struct s3c_fb_pd_win real6410_fb_win[] = {
 	{
-		.win_mode	= {	/* 4.3" 480x272 */
-			.left_margin	= 3,
-			.right_margin	= 2,
-			.upper_margin	= 1,
-			.lower_margin	= 1,
-			.hsync_len	= 40,
-			.vsync_len	= 1,
-			.xres		= 480,
-			.yres		= 272,
-		},
 		.max_bpp	= 32,
 		.default_bpp	= 16,
+		.xres		= 480,
+		.yres		= 272,
 	}, {
-		.win_mode	= {	/* 7.0" 800x480 */
-			.left_margin	= 8,
-			.right_margin	= 13,
-			.upper_margin	= 7,
-			.lower_margin	= 5,
-			.hsync_len	= 3,
-			.vsync_len	= 1,
-			.xres		= 800,
-			.yres		= 480,
-		},
 		.max_bpp	= 32,
 		.default_bpp	= 16,
+		.xres		= 800,
+		.yres		= 480,
 	},
 };
 
+static struct fb_videomode real6410_lcd_timing = {
+	.left_margin	= 3,
+	.right_margin	= 2,
+	.upper_margin	= 1,
+	.lower_margin	= 1,
+	.hsync_len	= 40,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
+};
+
 static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &real6410_lcd_timing,
 	.win[0]		= &real6410_fb_win[0],
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
@@ -291,8 +287,8 @@ static void __init real6410_machine_init(void)
 	real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
 
 	printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
-		real6410_lcd_pdata.win[0]->win_mode.xres,
-		real6410_lcd_pdata.win[0]->win_mode.yres);
+		real6410_lcd_pdata.win[0]->xres,
+		real6410_lcd_pdata.win[0]->yres);
 
 	s3c_fb_set_platdata(&real6410_lcd_pdata);
 	s3c_nand_set_platdata(&real6410_nand_info);
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index 3f42431..03a2f88 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -108,23 +108,27 @@ static struct platform_device smartq5_buttons_device  = {
 };
 
 static struct s3c_fb_pd_win smartq5_fb_win0 = {
-	.win_mode	= {
-		.left_margin	= 216,
-		.right_margin	= 40,
-		.upper_margin	= 35,
-		.lower_margin	= 10,
-		.hsync_len	= 1,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-		.refresh	= 80,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smartq5_lcd_timing = {
+	.left_margin	= 216,
+	.right_margin	= 40,
+	.upper_margin	= 35,
+	.lower_margin	= 10,
+	.hsync_len	= 1,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
+	.refresh	= 80,
 };
 
 static struct s3c_fb_platdata smartq5_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &smartq5_lcd_timing,
 	.win[0]		= &smartq5_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index e5c09b6..4e3b038 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -124,23 +124,27 @@ static struct platform_device smartq7_buttons_device  = {
 };
 
 static struct s3c_fb_pd_win smartq7_fb_win0 = {
-	.win_mode	= {
-		.left_margin	= 3,
-		.right_margin	= 5,
-		.upper_margin	= 1,
-		.lower_margin	= 20,
-		.hsync_len	= 10,
-		.vsync_len	= 3,
-		.xres		= 800,
-		.yres		= 480,
-		.refresh	= 80,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smartq7_lcd_timing = {
+	.left_margin	= 3,
+	.right_margin	= 5,
+	.upper_margin	= 1,
+	.lower_margin	= 20,
+	.hsync_len	= 10,
+	.vsync_len	= 3,
+	.xres		= 800,
+	.yres		= 480,
+	.refresh	= 80,
 };
 
 static struct s3c_fb_platdata smartq7_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &smartq7_lcd_timing,
 	.win[0]		= &smartq7_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index d55bc96..3cfc90f 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -146,26 +146,29 @@ static struct platform_device smdk6410_lcd_powerdev = {
 };
 
 static struct s3c_fb_pd_win smdk6410_fb_win0 = {
-	/* this is to ensure we use win0 */
-	.win_mode	= {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
 	.virtual_y	= 480 * 2,
 	.virtual_x	= 800,
 };
 
+static struct fb_videomode smdk6410_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
+};
+
 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
 static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &smdk6410_lcd_timing,
 	.win[0]		= &smdk6410_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index a40e325..92fefad 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -103,22 +103,26 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win smdk6440_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 24,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smdk6440_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = {
 	.win[0]		= &smdk6440_fb_win0,
+	.vtiming	= &smdk6440_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= s5p64x0_fb_gpio_setup_24bpp,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index efb69e2..e2335ec 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -121,22 +121,26 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win smdk6450_fb_win0 = {
-	.win_mode	= {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 24,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smdk6450_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = {
 	.win[0]		= &smdk6450_fb_win0,
+	.vtiming	= &smdk6450_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= s5p64x0_fb_gpio_setup_24bpp,
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 674d229..0c3ae38 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -136,24 +136,27 @@ static struct platform_device smdkc100_lcd_powerdev = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win smdkc100_fb_win0 = {
-	/* this is to ensure we use win0 */
-	.win_mode	= {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-		.refresh	= 80,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smdkc100_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
+	.refresh	= 80,
 };
 
 static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
 	.win[0]		= &smdkc100_fb_win0,
+	.vtiming	= &smdkc100_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= s5pc100_fb_gpio_setup_24bpp,
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index a9ea64e..7b91bbf 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -96,38 +96,34 @@ static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win aquila_fb_win0 = {
-	.win_mode = {
-		.left_margin = 16,
-		.right_margin = 16,
-		.upper_margin = 3,
-		.lower_margin = 28,
-		.hsync_len = 2,
-		.vsync_len = 2,
-		.xres = 480,
-		.yres = 800,
-	},
 	.max_bpp = 32,
 	.default_bpp = 16,
+	.xres = 480,
+	.yres = 800,
 };
 
 static struct s3c_fb_pd_win aquila_fb_win1 = {
-	.win_mode = {
-		.left_margin = 16,
-		.right_margin = 16,
-		.upper_margin = 3,
-		.lower_margin = 28,
-		.hsync_len = 2,
-		.vsync_len = 2,
-		.xres = 480,
-		.yres = 800,
-	},
 	.max_bpp = 32,
 	.default_bpp = 16,
+	.xres = 480,
+	.yres = 800,
+};
+
+static struct fb_videomode aquila_lcd_timing = {
+	.left_margin = 16,
+	.right_margin = 16,
+	.upper_margin = 3,
+	.lower_margin = 28,
+	.hsync_len = 2,
+	.vsync_len = 2,
+	.xres = 480,
+	.yres = 800,
 };
 
 static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
 	.win[0]		= &aquila_fb_win0,
 	.win[1]		= &aquila_fb_win1,
+	.vtiming	= &aquila_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
 			  VIDCON1_INV_VCLK | VIDCON1_INV_VDEN,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 2cf5ed7..07a840d 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -105,25 +105,29 @@ static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win goni_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 16,
-		.right_margin	= 16,
-		.upper_margin	= 2,
-		.lower_margin	= 28,
-		.hsync_len	= 2,
-		.vsync_len	= 1,
-		.xres		= 480,
-		.yres		= 800,
-		.refresh	= 55,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 480,
+	.yres		= 800,
 	.virtual_x	= 480,
 	.virtual_y	= 2 * 800,
 };
 
+static struct fb_videomode goni_lcd_timing = {
+	.left_margin	= 16,
+	.right_margin	= 16,
+	.upper_margin	= 2,
+	.lower_margin	= 28,
+	.hsync_len	= 2,
+	.vsync_len	= 1,
+	.xres		= 480,
+	.yres		= 800,
+	.refresh	= 55,
+};
+
 static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
 	.win[0]		= &goni_fb_win0,
+	.vtiming	= &goni_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
 			  VIDCON0_CLKSEL_LCD,
 	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 91d4ad8..5e0c955 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -189,22 +189,26 @@ static struct platform_device smdkv210_lcd_lte480wv = {
 };
 
 static struct s3c_fb_pd_win smdkv210_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 13,
-		.right_margin	= 8,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 24,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smdkv210_lcd_timing = {
+	.left_margin	= 13,
+	.right_margin	= 8,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
 	.win[0]		= &smdkv210_fb_win0,
+	.vtiming	= &smdkv210_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= s5pv210_fb_gpio_setup_24bpp,
-- 
1.6.6.rc2



From linus.walleij at linaro.org  Mon Mar 12 09:56:56 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 12 Mar 2012 14:56:56 +0100
Subject: [PATCH 1/4] pinctrl: introduce generic pin config
In-Reply-To: <4F57E1DB.3020605@wwwdotorg.org>
References: <1331071509-24661-1-git-send-email-linus.walleij@stericsson.com>
 <4F57E1DB.3020605@wwwdotorg.org>
Message-ID: <CACRpkdY_PV0UvMYCKBnrd1bnfgVSBWhLjFfV4m_i_+jpkc453Q@mail.gmail.com>

On Wed, Mar 7, 2012 at 11:31 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 03/06/2012 03:05 PM, Linus Walleij wrote:
>> From: Linus Walleij <linus.walleij at linaro.org>
>>
>> This is a split-off from the earlier patch set which adds generic
>> pin configuration for the pin controllers that want it. Since
>> we may have a system with mixed generic and custom pin controllers,
>> we pass a boolean in the pin controller ops vtable to indicate
>> if it is generic.
>>
>> ChangeLog v1->v5:
>> - Follow parent patch versioning number system.
>> - Document the semantic meaning of return values from pin config
>> ? get functions, so we can iterate over pins and check their
>> ? properties from debugfs as part of the generic config code.
>> - Use proper cast functions in the generic debugfs pin config
>> ? file.
>> - Expand generic config to optionally cover groups too.
>> ChangeLog v5->v6:
>> - Update to match underlying changes.
>>
>> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
>
>> diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
> ...
>> +/**
>> + * enum pin_config_param - possible pin configuration parameters
>> + * @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a
>> + * ? ? transition from say pull-up to pull-down implies that you disable
>> + * ? ? pull-up in the process, this setting disables all biasing.
>
> What's the use-case for that? It seems like if one state's mapping table
> entry says:
>
> PIN_CONFIG_BIAS_PULL_UP, value

The mapping table only has an unsigned long really, but yes it
might look something like that syntactically speaking (albeit being
compiled into a constant)

> and another state wants to switch to pull-down, it'd be best to just be
> explicit, and say:
>
> PIN_CONFIG_BIAS_PULL_UP, disabled
> PIN_CONFIG_BIAS_PULL_DOWN, value

I tried to avoid ging state-switching capabilities to arguments.
So going put of bias mode is a state changes and thus has its
own enumerator. Conflating parameters and their arguments
is less elegant IMO.

>> + * @PIN_CONFIG_BIAS_HIGH_IMPEDANCE: the pin will be set to a high impedance
>> + * ? ? mode, also know as "third-state" (tristate) or "high-Z" or "floating".
>> + * ? ? On output pins this effectively disconnects the pin, which is useful
>> + * ? ? if for example some other pin is going to drive the signal connected
>> + * ? ? to it for a while. Pins used for input are usually always high
>> + * ? ? impedance.
>
> Isn't this the same as DRIVE_OFF?

Yeah probably, so I'll drop DRIVE_OFF and kee? high impedance, because
it's more precise.

>> + * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
>> + * ? ? impedance to VDD), if the controller supports specifying a certain
>> + * ? ? pull-up resistance, this is given as an argument (in Ohms) when
>> + * ? ? setting this parameter.
>> + * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
>> + * ? ? impedance to GROUND), if the controller supports specifying a certain
>> + * ? ? pull-down resistance, this is given as an argument (in Ohms) when
>> + * ? ? setting this parameter.
>
> I don't think its a good idea to combine enabling/disabling features
> with configuring values for those features. If an SoC only has on/off
> control for pull-up, and the resistance isn't documented, what value
> does the driver author guess and require as the value here?
>
> Even when multiple pull-up/down strengths are available, it's quite
> plausible they're just documented as "weak" and "strong", and requiring
> someone to go find out what the exact values are rather than just using
> an enum disabled/enabled,weak=0/enabled,strong=1/ is going to be annoying.
>
> In other words, I think we'd be better off with:
>
> PIN_CONFIG_BIAS_PULL_UP = enabled/disabled 0/1
> PIN_CONFIG_BIAS_PULL_DOWN = enabled/disabled 0/1
> PIN_CONFIG_PULL_UP_STRENGTH = enumerated value 0..n-1
> PIN_CONFIG_PULL_DOWN_STRENGTH = enumerated value 0..n-1

Hm! I like the looks of this. I'm going to split them anyway.

But what's wrong with just using Ohms as the parameter?
That's what it's all about in the end is it not?
(The U300 GPIOs are 50 kOhm BTW, clearly specified.)

(Here I'm vaguely remembering some implementers not having a
clue what their enumerators really meant and me being alien to
the concept of incomplete hardware docs.)

I'm taking strength out for adding later, I only need
enable/disable for the U300 driver anyway.

>> + * @PIN_CONFIG_BIAS_HIGH: the pin will be wired high, connected to VDD
>> + * @PIN_CONFIG_BIAS_GROUND: the pin will be grounded, connected to GROUND
>
> Aren't these special cases of pull-up/down, with nominally zero
> resistance? I suppose I could see these having separate control bits
> though, so I suppose having explicit PIN_CONFIG_* values is reasonable.

Hm right, following my own argument above to encode pull up/down
arguments as Ohms I'll just delete them. Can be added back if we
encounter a HW like that.

>> + * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
>> + * ? ? low, this is the most typical case and is typically achieved with two
>> + * ? ? active transistors on the output. If the pin can support different
>> + * ? ? drive strengths for push/pull, the strength is given in the argument
>> + * ? ? as the number of driving stages vs nominal load impedance, so say
>> + * ? ? quadruple driving stages (usually 8 transistors rather than two) will
>> + * ? ? be configured with the 8 passed as argument.
>> + * @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open
>> + * ? ? collector) which means it is usually wired with other output ports
>> + * ? ? which are then pulled up with an external resistor. If the pin can
>> + * ? ? support different drive strengths for the open drain pin, the format
>> + * ? ? is the same as for PIN_CONFIG_DRIVE_PUSH_PULL.
>> + * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open drain
>> + * ? ? (open emitter) which is the same as open drain but pulled to ground.
>> + * ? ? If the pin can support different drive strengths for the open drain
>> + * ? ? pin, the format is the same as for PIN_CONFIG_DRIVE_PUSH_PULL.
>> + * @PIN_CONFIG_DRIVE_OFF: the pin is set to inactive drive mode, off.
>
> Again, I don't think that explicitly documenting the units (# of
> transistors) here is helpful. Datasheets may just be written in terms of
> weak/normal/strong...

Since I don't need these for this implementation I'll just delete them
and postpone the inclusion to the day we have a hardware that needs
them.

> Again, this mixes selection of drive type with configuring that drive
> type. For example, on some SoCs, PUSH_PULL might have a different set of
> available drive strengths for PUSH and PULL hence need two parameters.

Hm, interesting! But that very fact again underscores the underlying
silicon construct as a number of driver stages.

> Equally, the parameter for OPEN_DRAIN is the same as for PUSH_PULL, so
> why not separate selecting the drive type and setting the drive strength
> so that the setting of the drive strength can be shared between the
> drive types?

OK atleast I'm taking the argument out and replacing with just
enable/disable for now, so we can discuss that separately.

> So, I think this should be:
>
> PIN_CONFIG_DRIVE = push_pull/open_drain/open_source/tristate

Tristate is not a drive mode but equivalent to
BIAS_HIGH_IMPEDANCE.

I'll go for three parameters for each drive mode and the
argument ignored, I'm not copying the schem from pull up/down
with an enable/disable argument since you probably cannot "disable"
push-pull but rather have to set the pin to high impedance or OD, or
OS rather i.e. an implicit state transition, then it's better to have
that explicit.

> PIN_CONFIG_DRIVE_STRENGTH_UP = enumerated value 0..n-1
> PIN_CONFIG_DRIVE_STRENGTH_DOWN = enumerated value 0..n-1

Saving this stuff for later. Let's agree on a starting
point first.

> Note that PIN_CONFIG_SLEW_RATE_* are essentially parameterizations of
> the drive type just like drive strength is, and they're already separate
> config parameters.

True.

>> + * @PIN_CONFIG_SLEW_RATE_RISING: this will configure the slew rate for rising
>> + * ? ? signals on the pin. The argument gives the rise time in fractions
>> + * ? ? compared to maximum rise time, 0 means nominal rise time. If you can
>> + * ? ? control slew rate in 4 steps these will likely be equidistant like
>> + * ? ? 1/4, 1/2, 3/4 or full nominal slew rate, which means argument 4 gives
>> + * ? ? you 1/4 of nominal slew rate and the argument 4 has the same meaning
>> + * ? ? as 0 - nominal slew rate (fastest possible, steep edges). You may want
>> + * ? ? to adjust slew rates so that signal edges don't get too steep, causing
>> + * ? ? disturbances in surrounding electronics known as electromagnetic
>> + * ? ? interference (EMI) for example.
>> + * @PIN_CONFIG_SLEW_RATE_FALLING: this will configure the slew rate for falling
>> + * ? ? signals on the pin. The argument gives the fall time in fractions
>> + * ? ? compared to nominal fall time.
>
> The same comment here; I think the value of those two should just be an
> enumeration 0..n-1 to avoid documenting specific units.

I'm taking them out for later discussion alongside the first driver that
need them.

>> + * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
>> + * ? ? supplies, the argument to this parameter (on a custom format) tells
>> + * ? ? the driver which alternative power source to use.
>> + * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
>> + * ? ? operation, if several modes of operation are supported these can be
>> + * ? ? passed in the argument on a custom form, else just use argument 1
>> + * ? ? to indicate low power mode, argument 0 turns low power mode off.
>
>> + * @PIN_CONFIG_WAKEUP: this will configure an input pin such that if a
>> + * ? ? signal transition arrives at the pin when the pin controller/system
>> + * ? ? is sleeping, it will wake up the system if argument 1 is passed along.
>> + * ? ? Pass argument 0 to turn wakeup enablement off.
>
> Is this something that's controlled at the pinmux level? I would have
> expected it to be controlled by whatever HW input signals were routed to
> - i.e. a GPIO controller could control which GPIO inputs provided
> wakeup, or a USB controller would wake if some bus condition was seen
> etc. I suppose it's possible that a pin controller itself could wake the
> system, but how would the wake reason be mapped to something that could
> interpret that? If co-ordination between e.g. the GPIO driver an pinctrl
> driver is needed to achieve this, shouldn't the GPIO driver call into
> some private API in the pinctrl driver to set this up, similar to how
> pinctrl_gpio_direction_input() works?
>
> Still, if there's a specific reason for this I don't see any need to
> oppose it; it just seems surprising it'd be needed.

No I think it's plain wrong actually.

The struct irq_chip already provides methods for setting pins to
wakeup, so I'm just deleteing this.

There could be a usecase for a complex pin controller that can wake
up the system on a pin which however isn't going to generate an IRQ,
but that sounds backwards to me, and we can add it the day we
need it in that case.

>> + * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
>> + * ? ? you need to pass in custom configurations to the pin controller, use
>> + * ? ? PIN_CONFIG_END+1 as the base offset.
>> + */
>> +enum pin_config_param {
>> + ? ? ? PIN_CONFIG_BIAS_DISABLE,
>> + ? ? ? PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
>> + ? ? ? PIN_CONFIG_BIAS_PULL_UP,
>> + ? ? ? PIN_CONFIG_BIAS_PULL_DOWN,
>> + ? ? ? PIN_CONFIG_BIAS_HIGH,
>> + ? ? ? PIN_CONFIG_BIAS_GROUND,
>> + ? ? ? PIN_CONFIG_DRIVE_PUSH_PULL,
>> + ? ? ? PIN_CONFIG_DRIVE_OPEN_DRAIN,
>> + ? ? ? PIN_CONFIG_DRIVE_OPEN_SOURCE,
>> + ? ? ? PIN_CONFIG_DRIVE_OFF,
>> + ? ? ? PIN_CONFIG_INPUT_SCHMITT,
>> + ? ? ? PIN_CONFIG_INPUT_DEBOUNCE,
>> + ? ? ? PIN_CONFIG_SLEW_RATE_RISING,
>> + ? ? ? PIN_CONFIG_SLEW_RATE_FALLING,
>> + ? ? ? PIN_CONFIG_POWER_SOURCE,
>> + ? ? ? PIN_CONFIG_LOW_POWER_MODE,
>> + ? ? ? PIN_CONFIG_WAKEUP,
>> + ? ? ? PIN_CONFIG_END,
>> +};
>
> I think this should be given a large static value, e.g. 0x8000. That way
> the value will never change, and hence the values of custom enumerations
> will never change.

PIN_CONFIG_END you mean?

> That isn't important for mapping tables/... provided by data in the
> kernel since a recompile would trivially adapt to changes, but it might
> be for device tree; someone might want to represent the raw custom
> pin_config_param enumeration values directly in device tree (so they
> could read an int from device tree and cast it directly to an enum
> pin_config_param without using a lookup table to do the conversion), and
> the meanings of values in device tree need to stay static.
>
> Of course, you could argue that drivers parsing DT and creating mapping
> tables from it must always do an explicit mapping, in which case having
> PIN_CONFIG_END floating is fine.

We can have both. But I will set it to 0x7fff and let 0x8000 be the first
custom parameter...

>> +static inline enum pin_config_param to_config_param(unsigned long config)
>> +{
>> + ? ? ? return (enum pin_config_param) (config & 0xffffUL);
>> +}
>> +
>> +static inline u16 to_config_argument(unsigned long config)
>> +{
>> + ? ? ? return (enum pin_config_param) ((config >> 16) & 0xffffUL);
>> +}
>> +
>> +static inline unsigned long to_config_packed(enum pin_config_param param,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?u16 argument)
>> +{
>> + ? ? ? return (argument << 16) | ((unsigned long) param & 0xffffUL);
>> +}
>
> Those function names all have very generic names; shouldn't they be
> name-spaced e.g. pinconfig_to_param()/pinconfig_to_argument()?

Yep, I'll fix.

> Shouldn't to_config_packed() either be removed, or rewritten to use
> PIN_CONF_PACKED() to remove the duplication?

Ah. The latter was for tables so needed to be compile-time
resolvable. Didn't see the duplication. Will move the macro
above the function and use the macro in the static inline!

>> diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
>
>> +void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct seq_file *s, unsigned pin)
> ...
>> + ? ? ? ? ? ? ? /* We want to check out this parameter */
>> + ? ? ? ? ? ? ? config = to_config_packed(conf_items[i].param, 0);
>> + ? ? ? ? ? ? ? ret = pin_config_get_for_pin(pctldev, pin, &config);
>> + ? ? ? ? ? ? ? /* These are legal errors */
>> + ? ? ? ? ? ? ? if (ret == -EINVAL || ret == -ENOTSUPP)
>> + ? ? ? ? ? ? ? ? ? ? ? continue;
>
> What's the meaning of -EINVAL and -ENOTSUPP in this context? I don't
> understand why you'd need two "legal errors" rather than just -ENOTSUPP.

The reasoning is that -ENOTSUPP cannot be done by this
pin controller at all while -EINVAL is returned when the pin controller
does support the parameter, bit it has no meaning right now.

For example the pin controller might not support pull down
at all and then returns -ENOTSUPP for any attempt to read that
code.

However it might be that it does support pull-down, but right now
it is in output (drive) mode so there is nothing relevant to say
about pull-down right now.

I gave these two different error codes so we could tell them
apart, semantically speaking, practically you can write code doing
the same thing with just -ENOTSUPP but then this return code
means one of two things and you don't know which one it is.

The use cases in debugfs is:

(A) Show all settings right now (current implementation)
   iterate/skip over all error codes like above

(B) Show all *possible* settings (can be added if we can
  tell these two apart) show "available" for anything
  -EINVAL but do not show at all anything reporting
  -ENOTSUPP.

I think I had this documented at some point and it got lost..
will reinsert it somewhere.

> ...
>> + ? ? ? ? ? ? ? seq_puts(s, conf_items[i].display);
>> + ? ? ? ? ? ? ? /* Print unit if available */
>> + ? ? ? ? ? ? ? if (conf_items[i].format && to_config_argument(config) != 0)
>> + ? ? ? ? ? ? ? ? ? ? ? seq_printf(s, " (%u %s)", to_config_argument(config),
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?conf_items[i].format);
>
> Wouldn't you always want to dump the value, or if not, wouldn't you only
> want to print conf_items[i].display if you're going to print the value too?

We have some parameters where the value is meaningless so
we don't want to show these at all.

Let me post v7 so we can discuss from there.

Yours,
Linus Walleij


From grant.likely at secretlab.ca  Mon Mar 12 12:35:03 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 10:35:03 -0600
Subject: [PATCH] gpio/mxs: support irqs triggered by both edges
In-Reply-To: <1329745925-7868-1-git-send-email-enrico.scholz@sigma-chemnitz.de>
References: <1329745925-7868-1-git-send-email-enrico.scholz@sigma-chemnitz.de>
Message-ID: <20120312163503.AEBC73E07B0@localhost>

On Mon, 20 Feb 2012 14:52:05 +0100, Enrico Scholz <enrico.scholz at sigma-chemnitz.de> wrote:
> iMX28 silicon does not support irqs triggered by both gpio edges. Patch
> emulates this behavior by configuring such irqs as level triggered and
> by switching polarity in the interrupt handler.
> 
> Signed-off-by: Enrico Scholz <enrico.scholz at sigma-chemnitz.de>

That looks dodgy and hacky.  This will definitely miss interrupts if they
come in too fast.  I don't like this approach.  What do you need it for?

g.

> ---
>  drivers/gpio/gpio-mxs.c |   31 +++++++++++++++++++++++++++++--
>  1 files changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
> index 385c58e..ab973be 100644
> --- a/drivers/gpio/gpio-mxs.c
> +++ b/drivers/gpio/gpio-mxs.c
> @@ -57,6 +57,7 @@ struct mxs_gpio_port {
>  	int id;
>  	int irq;
>  	int virtual_irq_start;
> +	unsigned long both_edge;
>  	struct bgpio_chip bgc;
>  };
>  
> @@ -68,9 +69,12 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
>  	u32 pin_mask = 1 << (gpio & 31);
>  	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
>  	struct mxs_gpio_port *port = gc->private;
> +	int lvl;
>  	void __iomem *pin_addr;
>  	int edge;
>  
> +	clear_bit(gpio & 31, &port->both_edge);
> +
>  	switch (type) {
>  	case IRQ_TYPE_EDGE_RISING:
>  		edge = GPIO_INT_RISE_EDGE;
> @@ -84,6 +88,14 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
>  	case IRQ_TYPE_LEVEL_HIGH:
>  		edge = GPIO_INT_HIGH_LEV;
>  		break;
> +	case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
> +		/* mx28 does not support triggering irq by both edges; emulate
> +		 * behavior by configuring irq as level triggered and update
> +		 * irq polarity in the irq handler */
> +		set_bit(gpio & 31, &port->both_edge);
> +		lvl  = readl(port->base + PINCTRL_DIN(port->id));
> +		edge = (lvl & pin_mask) ? GPIO_INT_LOW_LEV : GPIO_INT_HIGH_LEV;
> +		break;
>  	default:
>  		return -EINVAL;
>  	}
> @@ -114,11 +126,26 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
>  	u32 irq_stat;
>  	struct mxs_gpio_port *port = irq_get_handler_data(irq);
>  	u32 gpio_irq_no_base = port->virtual_irq_start;
> +	void __iomem *base = port->base;
> +	u32 pol_msk;
>  
>  	desc->irq_data.chip->irq_ack(&desc->irq_data);
>  
> -	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
> -			readl(port->base + PINCTRL_IRQEN(port->id));
> +	irq_stat = readl(base + PINCTRL_IRQSTAT(port->id)) &
> +			readl(base + PINCTRL_IRQEN(port->id));
> +
> +	/* handle irqs triggered by both edges */
> +	pol_msk = irq_stat & port->both_edge;
> +	if (pol_msk) {
> +		void __iomem *reg = base + PINCTRL_IRQPOL(port->id);
> +		u32 port_lvl = readl(base + PINCTRL_DIN(port->id));
> +
> +		/* \todo write into the TOGGLE register (without reading port
> +		 * level register); this requires a special unmask operation
> +		 * which updates the IRQPOL register */
> +		writel(pol_msk & port_lvl, reg + MXS_CLR);
> +		writel(pol_msk & ~port_lvl, reg + MXS_SET);
> +	}
>  
>  	while (irq_stat != 0) {
>  		int irqoffset = fls(irq_stat) - 1;
> -- 
> 1.7.7.6
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From joancarles at fqingenieria.es  Mon Mar 12 09:12:02 2012
From: joancarles at fqingenieria.es (joancarles)
Date: Mon, 12 Mar 2012 14:12:02 +0100
Subject: [MX25][MMC] mmc esdhc failure in 3.3-rc5 (still present in rc7)
In-Reply-To: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
Message-ID: <49e17e1a8ded2e38805a5caebae62abc@mail.fqingenieria.es>

Hi

On Tue, 06 Mar 2012 11:29:50 +0000, joancarles wrote:
> Hi
>
> I have the following error when trying to access the SD-card on my 
> MX25
> device:
>
> root at mx25-noah:~$> mount /media/card/
> root at mx25-noah:~$> df -kh /media/card
> Filesystem                Size      Used Available Use% Mounted on
> /dev/mmcblk0p1          123.6M      2.7M    120.9M   2% /media/card
> root at mx25-noah:~$> touch /media/card/file
> [   82.982920] mmcblk0: error -110 transferring data, sector 559, nr 
> 1,
> cmd response 0x900, card status 0x0
> [   82.993544] end_request: I/O error, dev mmcblk0, sector 559
> [   82.999169] Buffer I/O error on device mmcblk0p1, logical block 
> 497
> [   83.005458] lost page write due to I/O error on mmcblk0p1
> [   83.013922] mmcblk0: error -84 transferring data, sector 559, nr 
> 1, cmd
> response 0x900, card status 0x0
> [   83.024114] end_request: I/O error, dev mmcblk0, sector 559
> [   83.029965] FAT-fs (mmcblk0p1): Directory bread(block 497) failed
> [   83.038051] mmcblk0: error -84 transferring data, sector 560, nr 
> 1, cmd
> response 0x900, card status 0x0
> [   83.048579] end_request: I/O error, dev mmcblk0, sector 560
> [   83.054205] Buffer I/O error on device mmcblk0p1, logical block 
> 498
> [   83.060494] lost page write due to I/O error on mmcblk0p1
> touch: /media/card/file: Input/output error
>
> I have compiled the kernel 3.3-rc5 with driver core debug support and 
> I
> get the following information:
>
> root at mx25-noah:~$> dmesg | grep -i mmc
> [    0.228098] bus: 'mmc': registered
> [    0.228139] device class 'mmc_host': registering
> [    1.405180] bus: 'mmc': add driver mmcblk
> [    1.429969] device: 'mmc0::': device_add
> [    1.430249] PM: Adding info for No Bus:mmc0::
> [    1.430837] Registered led device: mmc0::
> [    1.430884] device: 'mmc0': device_add
> [    1.431114] PM: Adding info for No Bus:mmc0
> [    1.432953] mmc0: SDHCI controller on sdhci-esdhc-imx25.0
> [sdhci-esdhc-imx25.0] using DMA
> [    1.771322] mmc0: host does not support reading read-only switch.
> assuming write-enable.
> [    1.798584] mmc0: new high speed SD card at address 0002
> [    1.804018] device: 'mmc0:0002': device_add
> [    1.804283] bus: 'mmc': add device mmc0:0002
> [    1.804445] PM: Adding info for mmc:mmc0:0002
> [    1.815198] bus: 'mmc': driver_probe_device: matched device 
> mmc0:0002
> with driver mmcblk
> [    1.815256] bus: 'mmc': really_probe: probing driver mmcblk with 
> device
> mmc0:0002
> [    1.825154] mmcblk0: mmc0:0002 00000 1.86 GiB
> [    1.835076] device: 'mmcblk0': device_add
> [    1.835680] PM: Adding info for No Bus:mmcblk0
> [    1.849286]  mmcblk0: p1 p2
> [    1.852252] device: 'mmcblk0p1': device_add
> [    1.855232] PM: Adding info for No Bus:mmcblk0p1
> [    1.855371] device: 'mmcblk0p2': device_add
> [    1.855874] PM: Adding info for No Bus:mmcblk0p2
> [    1.866667] driver: 'mmc0:0002': driver_bound: bound to device 
> 'mmcblk'
> [    1.866720] bus: 'mmc': really_probe: bound device mmc0:0002 to 
> driver
> mmcblk
> [   82.982920] mmcblk0: error -110 transferring data, sector 559, nr 
> 1,
> cmd response 0x900, card status 0x0
> [   82.993544] end_request: I/O error, dev mmcblk0, sector 559
> [   82.999169] Buffer I/O error on device mmcblk0p1, logical block 
> 497
> [   83.005458] lost page write due to I/O error on mmcblk0p1
> [   83.013922] mmcblk0: error -84 transferring data, sector 559, nr 
> 1, cmd
> response 0x900, card status 0x0
> [   83.024114] end_request: I/O error, dev mmcblk0, sector 559
> [   83.029965] FAT-fs (mmcblk0p1): Directory bread(block 497) failed
> [   83.038051] mmcblk0: error -84 transferring data, sector 560, nr 
> 1, cmd
> response 0x900, card status 0x0
> [   83.048579] end_request: I/O error, dev mmcblk0, sector 560
> [   83.054205] Buffer I/O error on device mmcblk0p1, logical block 
> 498
> [   83.060494] lost page write due to I/O error on mmcblk0p1
>
> The same device booted into a 2.6.39.3 kernel works just fine. The
> initialization of the esdhc driver in the device section is as 
> follows:
>
> imx25_add_sdhci_esdhc_imx(0, NULL);
>
> Changing it to a pdata init as shown below does not change anything 
> with
> regard to the failure:
>
> imx25_add_sdhci_esdhc_imx(0, &noah_esdhc_pdata);
> static const struct esdhc_platform_data noah_esdhc_pdata __initconst 
> = {
>         .wp_gpio = -EINVAL,
>         .cd_gpio = -EINVAL,
>         .wp_type = ESDHC_WP_NONE,
>         .cd_type = ESDHC_CD_NONE,
> };
>
> What could have changed between 2.6.39.3 and 3.3-rc5 to trigger this
> behaviour? A quick look at
>
> git diff v2.6.39 drivers/mmc/host/sdhci-esdhc-imx.c
>
> only confuses me with regard to this issue.
>
> Regards

This is still present in 3.3-rc7. Anyone? Where could I start debugging 
this? The same device works just fine with the 2.6.39.3 kernel based 
sdhci driver (drivers/mmc/host/sdhci-esdhc-imx.c). Unfortunately, due to 
out-of-tree device support for a custom i.MX25 board that I have started 
with a fresh 3.3-rc2 git tree, I cannot bisect the tree down to 2.6.39, 
or at least I don't know how.

Best regards
-- 
Joan C. Abelaira


From nsekhar at ti.com  Mon Mar 12 16:05:38 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Mon, 12 Mar 2012 20:05:38 +0000
Subject: [PATCH] ARM: davinci: cpufreq: fix compiler warning
In-Reply-To: <1331235404-15565-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1331235404-15565-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <DF0F476B391FA8409C78302C7BA518B6317F2E08@DBDE01.ent.ti.com>

Hi Uwe,

On Fri, Mar 09, 2012 at 01:06:44, Uwe Kleine-K?nig wrote:
> This fixes:
> 	arch/arm/mach-davinci/cpufreq.c: In function davinci_target:
> 	arch/arm/mach-davinci/cpufreq.c:98: warning: passing argument 2 of dev_printk from incompatible pointer type
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Applying this, thanks!

Regards,
Sekhar



From grant.likely at secretlab.ca  Fri Mar  9 00:37:04 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 08 Mar 2012 22:37:04 -0700
Subject: [PATCH 4/4] misc: emif: add device tree support to emif driver
In-Reply-To: <1331224437-4808-5-git-send-email-aneesh@ti.com>
References: <1331224437-4808-1-git-send-email-aneesh@ti.com>
 <1331224437-4808-5-git-send-email-aneesh@ti.com>
Message-ID: <20120309053704.E40433E0901@localhost>

On Thu,  8 Mar 2012 22:03:57 +0530, Aneesh V <aneesh at ti.com> wrote:
> Cc: Rajendra Nayak <rnayak at ti.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Signed-off-by: Aneesh V <aneesh at ti.com>
> ---
> Changes since RFC v4:
> - Rebased to the latest version of EMIF series
> - Replace kzalloc()/kfree() with devm_* variants
> ---
>  drivers/misc/emif.c |  289 ++++++++++++++++++++++++++++++++++++++++++++++++++-
>  1 files changed, 288 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
> index 79fb161..0aaa61e 100644
> --- a/drivers/misc/emif.c
> +++ b/drivers/misc/emif.c
> @@ -18,6 +18,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/interrupt.h>
>  #include <linux/slab.h>
> +#include <linux/of.h>
>  #include <linux/debugfs.h>
>  #include <linux/seq_file.h>
>  #include <linux/module.h>
> @@ -49,6 +50,7 @@
>   *				frequency in effect at the moment)
>   * @plat_data:			Pointer to saved platform data.
>   * @debugfs_root:		dentry to the root folder for EMIF in debugfs
> + * @np_ddr:			Pointer to ddr device tree node
>   */
>  struct emif_data {
>  	u8				duplicate;
> @@ -63,6 +65,9 @@ struct emif_data {
>  	struct emif_regs		*curr_regs;
>  	struct emif_platform_data	*plat_data;
>  	struct dentry			*debugfs_root;
> +#if defined(CONFIG_OF)
> +	struct device_node		*np_ddr;
> +#endif

Don't bother with the #if/#endif wrapper here.

>  };
>  
>  static struct emif_data *emif1;
> @@ -1147,6 +1152,270 @@ static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
>  	return valid;
>  }
>  
> +#if defined(CONFIG_OF)
> +static void __init of_get_custom_configs(struct device_node *np_emif,

__devinit. Same through the rest of the file.

[...]
> +	return NULL;
> +out:
> +	return emif;
> +}
> +#endif
> +
>  static struct emif_data * __init get_device_details(

This function also must be __devinit

>  		struct platform_device *pdev)
>  {
> @@ -1266,7 +1535,13 @@ static int __init emif_probe(struct platform_device *pdev)
>  	struct resource		*res;
>  	int			irq;
>  
> -	emif = get_device_details(pdev);
> +#if defined(CONFIG_OF)
> +	if (pdev->dev.of_node)
> +		emif = of_get_device_details(pdev->dev.of_node, &pdev->dev);
> +	else
> +#endif
> +		emif = get_device_details(pdev);
> +
>  	if (!emif) {
>  		pr_err("%s: error getting device data\n", __func__);
>  		goto error;
> @@ -1643,11 +1918,23 @@ static void __attribute__((unused)) freq_post_notify_handling(void)
>  	spin_unlock_irqrestore(&emif_lock, irq_state);
>  }
>  
> +#if defined(CONFIG_OF)
> +static const struct of_device_id emif_of_match[] = {
> +		{ .compatible = "ti,emif-4d" },
> +		{ .compatible = "ti,emif-4d5" },
> +		{},
> +};
> +MODULE_DEVICE_TABLE(of, emif_of_match);
> +#endif
> +
>  static struct platform_driver emif_driver = {
>  	.remove		= __exit_p(emif_remove),

Not part of this patch I realize, but this is a bug.  .remove must
be in the __devexit section and the __devexit_p() wrapper must
be used.  Similarly, emif_probe must be in the __devinit section.

>  	.shutdown	= emif_shutdown,
>  	.driver = {
>  		.name = "emif",
> +#if defined(CONFIG_OF)
> +		.of_match_table = of_match_ptr(emif_of_match),
> +#endif

The of_match_ptr() macro makes the #if/#endif wrapper redundant.

Otherwise, on brief review this patch looks right.

g.


>  	},
>  };
>  
> -- 
> 1.7.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From grant.likely at secretlab.ca  Fri Mar  9 00:42:13 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 08 Mar 2012 22:42:13 -0700
Subject: [PATCH v2 1/4] mmc: omap_hsmmc: Convert hsmmc driver to use
 device tree
In-Reply-To: <1329998490-27555-2-git-send-email-rnayak@ti.com>
References: <1329998490-27555-1-git-send-email-rnayak@ti.com>
 <1329998490-27555-2-git-send-email-rnayak@ti.com>
Message-ID: <20120309054213.9E69C3E0901@localhost>

On Thu, 23 Feb 2012 17:31:27 +0530, Rajendra Nayak <rnayak at ti.com> wrote:
> Define dt bindings for the ti-omap-hsmmc, and adapt
> the driver to extract data (which was earlier passed as
> platform_data) from device tree.
> 
> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> ---
>  .../devicetree/bindings/mmc/ti-omap-hsmmc.txt      |   31 +++++++++
>  drivers/mmc/host/omap_hsmmc.c                      |   68 ++++++++++++++++++++
>  2 files changed, 99 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> 
> diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> new file mode 100644
> index 0000000..e4fa8f0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> @@ -0,0 +1,31 @@
> +* TI Highspeed MMC host controller for OMAP
> +
> +The Highspeed MMC Host Controller on TI OMAP family
> +provides an interface for MMC, SD, and SDIO types of memory cards.
> +
> +Required properties:
> +- compatible:
> + Should be "ti,omap2-hsmmc", for OMAP2/3 controllers
> + Should be "ti,omap4-hsmmc", for OMAP4 controllers
> +- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
> +- reg : should contain hsmmc registers location and length
> +
> +Optional properties:
> +ti,dual-volt: boolean, supports dual voltage cards
> +<supply-name>-supply: phandle to the regulator device tree node
> +"supply-name" examples are "vmmc", "vmmc_aux" etc
> +ti,bus-width: Number of data lines, default assumed is 1 if the property is missing.
> +cd-gpios: GPIOs for card detection
> +wp-gpios: GPIOs for write protection
> +ti,non-removable: non-removable slot (like eMMC)

Binding looks okay.  A couple comments below...

[...]
> +static const struct of_device_id omap_mmc_of_match[];

If you move the omap_mmc_of_match[] table up to here then there is no
need for the forward declaration.

> +
>  static int __init omap_hsmmc_probe(struct platform_device *pdev)
>  {
>  	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
> @@ -1725,6 +1768,14 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>  	struct omap_hsmmc_host *host = NULL;
>  	struct resource *res;
>  	int ret, irq;
> +	const struct of_device_id *match;
> +
> +	match = of_match_device(omap_mmc_of_match, &pdev->dev);
> +	if (match) {
> +		pdata = of_get_hsmmc_pdata(&pdev->dev);
> +		if (match->data)
> +			pdata->reg_offset = *(u16 *)match->data;

Blech on the ugly cast.  It is slightly safer to do thusly:

	u16 *offsetp = match->data;
	pdata->reg_offset = *offsetp

> +	}
>  
>  	if (pdata == NULL) {
>  		dev_err(&pdev->dev, "Platform Data is missing\n");
> @@ -2120,12 +2171,29 @@ static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
>  	.runtime_resume = omap_hsmmc_runtime_resume,
>  };
>  
> +#if defined(CONFIG_OF)
> +static u16 omap4_reg_offset = 0x100;
> +
> +static const struct of_device_id omap_mmc_of_match[] = {
> +	{
> +		.compatible = "ti,omap2-hsmmc",
> +	},
> +	{
> +		.compatible = "ti,omap4-hsmmc",
> +		.data = &omap4_reg_offset,
> +	},
> +	{},
> +}
> +MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
> +#endif
> +
>  static struct platform_driver omap_hsmmc_driver = {
>  	.remove		= omap_hsmmc_remove,
>  	.driver		= {
>  		.name = DRIVER_NAME,
>  		.owner = THIS_MODULE,
>  		.pm = &omap_hsmmc_dev_pm_ops,
> +		.of_match_table = of_match_ptr(omap_mmc_of_match),
>  	},
>  };
>  
> -- 
> 1.7.1
> 
> 
> _______________________________________________
> linaro-dev mailing list
> linaro-dev at lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-dev

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From s.hauer at pengutronix.de  Fri Mar  9 09:22:05 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 9 Mar 2012 15:22:05 +0100
Subject: [RFC] i.MX: drop secondary clocks
In-Reply-To: <20313.60910.420339.905973@ipc1.ka-ro>
References: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
 <20313.52782.832292.580932@ipc1.ka-ro>
 <20120309102931.GY3852@pengutronix.de>
 <20313.60910.420339.905973@ipc1.ka-ro>
Message-ID: <20120309142205.GF3852@pengutronix.de>

On Fri, Mar 09, 2012 at 12:47:58PM +0100, Lothar Wa?mann wrote:
> Hi,
> 
> Sascha Hauer writes:
> > On Fri, Mar 09, 2012 at 10:32:30AM +0100, Lothar Wa?mann wrote:
> > > Hi,
> > > 
> > > Sascha Hauer writes:
> > > > Hi All,
> > > > 
> [...]
> > > I think that's a bad idea! Drivers should not have to know intimate
> > > details about the clock logic of the CPU core they are running on!
> > 
> > They don't have to. There really are different clocks connected to the
> > devices. If for example you have a look eSDHC Block diagram in the
> > reference Manual  you'll see that this has three clock inputs. All
> > we do is to tell the driver about these three clocks which are device
> > specific and not SoC specific. Which of these clocks are actually
> > gatetable varies from SoC to SoC. Also on some SoCs two of the three
> > clocks may be actually the same.
> > 
> At least this should be done in a way that is independent from the
> name of the clock on a specific SoC, but is related to the function of
> the clock for the driver. Thus instead of e.g. CLK_IPG and CLK_PER use
> CLK_REG and CLK_BITRATE.

'per', 'ipg' and 'ahb' seems to be a common pattern with all i.MXs. Only
ahb is sometimes refered to as hclk. Do you also have a name for
ahb/hclk? I don't insist on specific names, in the end they are just
names and the pattern I used at least seems mostly consistent.

> 
> > > They should simply request a clock for the unit they operate on and
> > > the clock core code should figure out which other clocks need to be
> > > enabled on a specific machine to get the unit working.
> > 
> > Yes, that's what we want to do, except that devices do not need 'a'
> > clock but several. And the clock core figures out which other clocks
> > have to be activated, these are the parent clocks.
> > 
> What about devices which have multiple 'parent' clocks that are
> completely unrelated wrt. each other? In the current clock system you
> can model this by having secondary clocks.
> How would you represent the current structure on i.MX53:
> uart_ipg_clk <- aips_tz1_clk <-+- ahb_clk
>                                +-> ahb_max_clk
> in the new model?
> Should every driver have to request the ahb_max_clk in addition to the
> uart_ipg_clk?

No.

The dependeny to the aips_tz1_clk comes in because the UART is behind
the AIPS bridge. That's a dependency on bus topology level but not on clock
topology level. If we really have to handle this then on bus level. The
i.MX5 devicetree already shows this bus topology, it should be doable
to hook drivers on fsl,aips-bus which handle the clock.

Unfortunately the documentation where these clocks are really used goes
to zero and the FSL sourcecode is rather confusing in this area. I think
we will learn more about it once we have something in the generic clock
framework which disables the unused clocks.

> 
> What, if you have a device on a number of SoCs with a certain set of
> clocks, but on a later SoC another clock is required for the device?

I assume that any given device has a set of clocks as inputs which
should get device specific names. It's the job of the clock tree
to know which SoC clocks map to which device clocks. If now a newer
UART block has an additional clock, then we would depending on the
device id (fsl,imx7-uart) know that it requires the additional clock
and request it.

> You would not only have to change the driver to add the new clock but
> also would have to add that clock as a dummy clock in the core clock
> code for all previous SoCs that did not provide that clock.
> 
> > I also don't really like exposing this to the drivers, but it's a clean
> > way to do so. A framebuffer driver needs a pixel clock which must be
> > enabled when the display is turned on. It may also have a register clock
> > which has to be turned on when we want to access registers. These are
> > two different clocks and the driver can make use of this (not that we
> > currently do though...)
> > 
> But we could do so without any problem.

Not without exposing the individual clocks to the devices.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From alan at signal11.us  Sat Mar 10 13:44:55 2012
From: alan at signal11.us (Alan Ott)
Date: Sat, 10 Mar 2012 13:44:55 -0500
Subject: [PATCH 2/2] ARM: at91: Use proper __iomem annotations
In-Reply-To: <1331405049-3186-1-git-send-email-alan@signal11.us>
References: <1331405049-3186-1-git-send-email-alan@signal11.us>
Message-ID: <1331405095-3299-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

MMIO addresses should be of type 'void __iomem *', not integer,
in order to make the build-time type system of the kernel work.

This changes some of the locations in the at91 platform that
I noticed, but there may be more, since I have not yet built
every configuration.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-at91/at91rm9200.c            |    2 +-
 arch/arm/mach-at91/include/mach/hardware.h |    4 ++++
 arch/arm/mach-at91/setup.c                 |    4 ++--
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 99c3174..239b657 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -27,7 +27,7 @@
 
 static struct map_desc at91rm9200_io_desc[] __initdata = {
 	{
-		.virtual	= AT91_VA_BASE_EMAC,
+		.virtual	= (unsigned long)AT91_VA_BASE_EMAC,
 		.pfn		= __phys_to_pfn(AT91RM9200_BASE_EMAC),
 		.length		= SZ_16K,
 		.type		= MT_DEVICE,
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 2d0e4e9..91375e2 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -75,8 +75,12 @@
  * to 0xFEF78000 .. 0xFF000000.  (544Kb)
  */
 #define AT91_IO_PHYS_BASE	0xFFF78000
+#ifdef __ASSEMBLER__
 #define AT91_IO_VIRT_BASE	(0xFF000000 - AT91_IO_SIZE)
 #else
+#define AT91_IO_VIRT_BASE	(void __iomem *)(0xFF000000 - AT91_IO_SIZE)
+#endif
+#else
 /*
  * Identity mapping for the non MMU case.
  */
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 69d3fc4..809da35 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -57,7 +57,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 {
 	struct map_desc *desc = &sram_desc[bank];
 
-	desc->virtual = AT91_IO_VIRT_BASE - length;
+	desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
 	if (bank > 0)
 		desc->virtual -= sram_desc[bank - 1].length;
 
@@ -72,7 +72,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 }
 
 static struct map_desc at91_io_desc __initdata = {
-	.virtual	= AT91_VA_BASE_SYS,
+	.virtual	= (unsigned long)AT91_VA_BASE_SYS,
 	.pfn		= __phys_to_pfn(AT91_BASE_SYS),
 	.length		= SZ_16K,
 	.type		= MT_DEVICE,
-- 
1.7.0.4



From thierry.reding at avionic-design.de  Mon Mar 12 10:17:05 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Mon, 12 Mar 2012 15:17:05 +0100
Subject: [PATCH 11/11] ARM: tegra: pcie: Add device tree support
In-Reply-To: <20120312120610.GA14020@sirena.org.uk>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-12-git-send-email-thierry.reding@avionic-design.de>
 <4F59253D.7070100@wwwdotorg.org>
 <20120312120610.GA14020@sirena.org.uk>
Message-ID: <20120312141705.GA16395@avionic-0098.mockup.avionic-design.de>

* Mark Brown wrote:
> On Thu, Mar 08, 2012 at 02:31:41PM -0700, Stephen Warren wrote:
> > On 03/08/2012 07:51 AM, Thierry Reding wrote:
> 
> > > +- vdd-supply: power supply for controller (1.05V)
> 
> > Should those *-supply properties really be optional? I got the
> > impression talking to Mark in a different thread that all regulators
> > should exist, although their implementation may be via a fixed
> > regulator, with no GPIO, as determined by the board design.
> 
> Depends on the electronics, if the device can function without a supply
> then it is OK for it to be optional.  This is moderately unusual but not
> unknown.  It's obviously also OK to omit the supply if the system
> doesn't use software regulators at all, though a kernel with regulator
> support enabled would need to use dummy regulators to stub things out.

The PCIe controller actually needs those supplies and won't work without
them. However on TrimSlice both of these supplies seem to be hardwired and
always on. At least that's what I deduce from the code because there is no
code that enables either the 1.05V or the pex-clk supplies.

My understanding of the fixed regulator was that it was meant to be used for
fixed voltage supplies that can still be enabled or disabled (for example as
supplied by a GPIO) but not regulators that are fix in the sense that they
cannot be enabled or disabled at all but are always on.

Then again, the fixed regulator binding says that the gpio property is
optional, so perhaps doing something like the following will work:

	pex_clk_reg: fixedregulator at 0 {
		compatible = "regulator-fixed";
		regulator-name = "PCIE CLK";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	pcie_reg: fixedregulator at 1 {
		compatible = "regulator-fixed";
		regulator-name = "PCIE VDD";
		regulator-min-microvolt = <1050000>;
		regulator-max-microvolt = <1050000>;
		regulator-always-on;
	};

Is that how it is supposed to work?

Thierry
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From thierry.reding at avionic-design.de  Fri Mar  9 01:50:04 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 9 Mar 2012 07:50:04 +0100
Subject: [PATCH 10/11] ARM: tegra: pcie: Add MSI support
In-Reply-To: <4F59213F.6070107@wwwdotorg.org>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-11-git-send-email-thierry.reding@avionic-design.de>
 <4F59213F.6070107@wwwdotorg.org>
Message-ID: <20120309065004.GD25208@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> On 03/08/2012 07:51 AM, Thierry Reding wrote:
> > This commit adds support for message signaled interrupts to the Tegra
> > PCIe controller.
> > 
> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> > ---
> > This code is taken from the NVIDIA Vibrante kernel and therefore has no
> > appropriate Signed-off-by from the original author. Maybe someone at
> > NVIDIA can find out who wrote this code and maybe provide a proper
> > Signed-off-by that I can add?
> 
> I think if you look in:
> git://nv-tegra.nvidia.com/linux-2.6.git android-tegra-2.6.36
> 
> the following commits are what you're after:
> 
> de7fd8768b32da66eaf4eaf58473c65f7a76808d
> arm: tegra: pcie: enabling MSI support for pcie
> 
> ac1f8310811c64a084511d2afc27f66334b31a81
> ARM: tegra: pcie: fix return value from MSI irq routine
> 
> Although the patch below only partially resembles those patches, I guess
> because you've rewritten the code a lot to conform to the current kernel
> APIs, clean stuff up, etc. Perhaps just saying "based on code by Krishna
> Kishore <kthota at nvidia.com>" is enough...

Yes, it is indeed a major rewrite because the original code had some
peculiarities and FIXME that I thought wouldn't make it through the review
anyway so I fixed them up.

I'll add some comment about the original authorship. There is no official
Signed-off-by in the original commit. Do I still need one or is it enough to
mention the original authors in the commit message and add keep my own
Signed-off-by?

Thierry

> 
> > diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
> 
> > +static int tegra_pcie_enable_msi(struct platform_device *pdev)
> > +{
> > +	struct tegra_pcie_info *pcie = platform_get_drvdata(pdev);
> > +	volatile void *pages;
> > +	unsigned long base;
> > +	unsigned int msi;
> > +	int msi_base;
> > +	int err;
> > +	u32 reg;
> > +
> > +	mutex_init(&pcie->msi_lock);
> > +
> > +	msi_base = irq_alloc_descs(-1, 0, INT_PCI_MSI_NR, 0);
> > +	if (msi_base < 0) {
> > +		dev_err(&pdev->dev, "failed to allocate IRQs\n");
> > +		return msi_base;
> > +	}
> > +
> > +	pcie->msi_domain = irq_domain_add_legacy(pcie->dev->of_node,
> > +						 INT_PCI_MSI_NR, msi_base,
> > +						 0, &irq_domain_simple_ops,
> > +						 NULL);
> > +	if (!pcie->msi_domain) {
> > +		dev_err(&pdev->dev, "failed to create IRQ domain\n");
> 
> Free the IRQ descriptors in the error paths?

Yes, that would make sense.

> > +		return -ENOMEM;
> > +	}
> > +
> > +	pcie->msi_chip.name = "PCIe-MSI";
> > +	pcie->msi_chip.irq_enable = unmask_msi_irq;
> > +	pcie->msi_chip.irq_disable = mask_msi_irq;
> > +	pcie->msi_chip.irq_mask = mask_msi_irq;
> > +	pcie->msi_chip.irq_unmask = unmask_msi_irq;
> > +
> > +	for (msi = 0; msi < INT_PCI_MSI_NR; msi++) {
> > +		unsigned int irq = irq_find_mapping(pcie->msi_domain, msi);
> > +
> > +		irq_set_chip_data(irq, pcie);
> > +		irq_set_chip_and_handler(irq, &pcie->msi_chip,
> > +					 handle_simple_irq);
> > +		set_irq_flags(irq, IRQF_VALID);
> > +	}
> > +
> > +	err = platform_get_irq(pdev, 1);
> > +	if (err < 0) {
> > +		dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
> 
> Same here, and undo setting IRQF_VALID?

Right. I assume it would be best to also free the struct irq_domain and set
the chip data and handler back to NULL? AFAICT there is no canonical way to
teardown an irq_domain.

> > +		return err;
> > +	}
> ...
> 
> > +static int tegra_pcie_disable_msi(struct platform_device *pdev)
> > +{
> > +	return 0;
> > +}
> 
> This is empty in both the ifdef(CONFIG_PCI_MSI) case and otherwise. It
> should probably clean everything up here right?

Yes, initially this contained a call to free_irq(), which I removed when I
switched to using a chained handler. I can probably put all of the cleanup
code from your comments above in here and perhaps even call that in the error
paths of tegra_pcie_enable_msi().

Thierry
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From lost.distance at yahoo.com  Sat Mar 10 13:11:20 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Sat, 10 Mar 2012 18:11:20 +0000 (GMT)
Subject: [PATCH] pxa/hx4700: Reduce sleep mode power consumption by 35%
Message-ID: <1331403080.2319.YahooMailClassic@web29002.mail.ird.yahoo.com>

Drive the two Bluetooth UART output GPIOs (GPIO43_BTUART_TXD, GPIO45_BTUART_RTS)
LOW during sleep mode instead of HIGH. This reduces sleep mode power consumption
from approximately 46 mA/h to approximately 30 mA/h.

Signed-off-by: Oliver Winker <oliver at oli1170.net>
Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
---

Thanks to Oliver Winker for finding this.

diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c
--- clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-04 01:08:09.000000000 +0000
+++ linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-10 15:44:18.597238757 +0000
@@ -97,9 +97,9 @@ static unsigned long hx4700_pin_config[]
 
 	/* BTUART */
 	GPIO42_BTUART_RXD,
-	GPIO43_BTUART_TXD,
+	GPIO43_GPIO | MFP_AF2 | MFP_LPM_DRIVE_LOW,
 	GPIO44_BTUART_CTS,
-	GPIO45_BTUART_RTS,
+	GPIO45_GPIO | MFP_AF2 | MFP_LPM_DRIVE_LOW,
 
 	/* PWM 1 (Backlight) */
 	GPIO17_PWM1_OUT,



From grant.likely at secretlab.ca  Fri Mar  9 00:15:06 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 08 Mar 2012 22:15:06 -0700
Subject: [PATCH 05/11] tps6586x: Add device-tree support
In-Reply-To: <20120308151545.GA23934@avionic-0098.mockup.avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-6-git-send-email-thierry.reding@avionic-design.de>
 <20120308150607.GP3638@opensource.wolfsonmicro.com>
 <20120308151545.GA23934@avionic-0098.mockup.avionic-design.de>
Message-ID: <20120309051506.761B63E090F@localhost>

On Thu, 8 Mar 2012 16:15:46 +0100, Thierry Reding <thierry.reding at avionic-design.de> wrote:
> * Mark Brown wrote:
> > On Thu, Mar 08, 2012 at 03:51:25PM +0100, Thierry Reding wrote:
> > 
> > > +- gpio-controller: mark the device as a GPIO controller
> > > +- regulators: list of regulators provided by this controller, must be in the
> > > +  following order:
> > > +    SM0, SM1, SM2, LDO0, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9
> > 
> > This ordering requirement is fairly sad, if there are unused regulators
> > they still need to be listed even though...

It's worse than that; the DT provides absolutely no guarantees about the
ordering of either child nodes or properties.

> > 
> > > +			sm0_reg: sm0 {
> > > +				regulator-min-microvolt = < 725000>;
> > > +				regulator-max-microvolt = <1500000>;
> > > +				regulator-boot-on;
> > > +				regulator-always-on;
> > > +			};
> > > +
> > > +			sm1_reg: sm1 {
> > 
> > ...they all seem to be explicitly named in the device tree so presumably
> > there's enough information in there for the driver to pick any set of
> > regulators in any order.  This would be much nicer to use.
> 
> I don't like it much either. The only reason that requirement exists is
> because it makes the assignment of the regulator ID (as defined in the
> include/linux/mfd/tps6586x.h header) very trivial. Would it be better to
> look up the ID based on the node name (sm0 --> TPS6586X_ID_SM_0, ...)?
> 
> Then the only requirement would be that the names match.

Yes, please look up id via name.  Alternately you can give each child node
a 'reg' property and put #address-cells = <1>; #size-cells = <0>; in the
parent (assuming the regulator number is a documented attribute of the
hardware and not just a convenient linux construct).

g.


From rob.lee at linaro.org  Fri Mar  9 17:26:00 2012
From: rob.lee at linaro.org (Rob Lee)
Date: Fri, 9 Mar 2012 16:26:00 -0600
Subject: linux-next: manual merge of the cpuidle-cons tree with the
 arm-soc tree
In-Reply-To: <20120309183732.512d3676599da324f4747219@canb.auug.org.au>
References: <20120309183732.512d3676599da324f4747219@canb.auug.org.au>
Message-ID: <CAMXH7KE5En7U-2zydT3MfJ7C7B164-zsQuBoHMUqzD-Kb_nh1w@mail.gmail.com>

Hello Stephen,

Yes, your resolution looks correct to me.

Thanks,
Rob Lee


On Fri, Mar 9, 2012 at 1:37 AM, Stephen Rothwell <sfr at canb.auug.org.au> wrote:
> Hi Rob,
>
> Today's linux-next merge of the cpuidle-cons tree got a conflict in
> arch/arm/mach-at91/cpuidle.c between commit 00482a4078f4 ("ARM: at91:
> implement the standby function for pm/cpuidle") from the arm-soc tree and
> commit 7a1f6e72dce1 ("ARM: at91: Consolidate time keeping and irq
> enable") from the cpuidle-cons tree.
>
> I fixed it up (I think - see below) and can carry the fix as necessary.
> --
> Cheers,
> Stephen Rothwell ? ? ? ? ? ? ? ? ? ?sfr at canb.auug.org.au
>
> diff --cc arch/arm/mach-at91/cpuidle.c
> index 555d956,d40b3f3..0000000
> --- a/arch/arm/mach-at91/cpuidle.c
> +++ b/arch/arm/mach-at91/cpuidle.c
> @@@ -37,23 -33,15 +33,8 @@@ static int at91_enter_idle(struct cpuid
> ? ? ? ? ? ? ? ? ? ? ? ?struct cpuidle_driver *drv,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int index)
> ?{
> - ? ? ? struct timeval before, after;
> - ? ? ? int idle_time;
> -
> - ? ? ? local_irq_disable();
> - ? ? ? do_gettimeofday(&before);
> - ? ? ? if (index == 0)
> - ? ? ? ? ? ? ? /* Wait for interrupt state */
> - ? ? ? ? ? ? ? cpu_do_idle();
> - ? ? ? else if (index == 1)
> - ? ? ? ? ? ? ? at91_standby();
> ?- ? ? ?u32 saved_lpr;
> ?-
> ?- ? ? ?__asm__("b 1f; .align 5; 1:\n"
> ?- ? ? ?" ? ? ? mcr p15, 0, r0, c7, c10, 4"); ? /* drain write buffer */
> ?-
> ?- ? ? ?saved_lpr = sdram_selfrefresh_enable();
> ?- ? ? ?cpu_do_idle();
> ?- ? ? ?sdram_selfrefresh_disable(saved_lpr);
> ++ ? ? ?at91_standby();
>
> - ? ? ? do_gettimeofday(&after);
> - ? ? ? local_irq_enable();
> - ? ? ? idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
> - ? ? ? ? ? ? ? ? ? ? ? (after.tv_usec - before.tv_usec);
> -
> - ? ? ? dev->last_residency = idle_time;
> ? ? ? ?return index;
> ?}
>


From hustgqyang at gmail.com  Sat Mar 10 09:37:09 2012
From: hustgqyang at gmail.com (yang gqyang)
Date: Sat, 10 Mar 2012 22:37:09 +0800
Subject: implementing "suspend to ram" on cortex A8 based on linux 3.0.8
In-Reply-To: <CAFawwkWQd=y=kVm97UjSs37=-MRmJiy9f7sy8ChYzCHZ9Y-gyA@mail.gmail.com>
References: <CAFawwkXQhyj+c8LEDnD7q4mXDJV2jYCAHV0tBrqxrEaNGk+_0w@mail.gmail.com>
 <CACNz9cVbULxVSGvo60V+JLL=15BDEaYwgd5k9ZMNu09Kfwz4WQ@mail.gmail.com>
 <CAFawwkWQd=y=kVm97UjSs37=-MRmJiy9f7sy8ChYzCHZ9Y-gyA@mail.gmail.com>
Message-ID: <CAFawwkVuCTijwLr6UWVRh9XNGCt-8brr2f4aDrpM_YwkWSGP+A@mail.gmail.com>

 Thanks for your comment.
 Finally, i find out that i made a mistake.  The uart(8250) have not been
 restore after resume, instead, it use the configuration got from boot. The
 uart have not been restored correctly, so that "ls" can not output result
 correctly resulting in it seems that the busybox can not work correctly.
 Now, i still have a question about the uart: why the "printk" can work
 correctly, but the "printf" not?

 Before this, i believe that the "printk" work correctly, then the uart
 work ok. but now, i  need more reconsidaration about
 the relation between the "printk", "printf" and "uart".
 Can anyone give me some suggestion? Any comment is welcome, thanks a
 lot.


> ? 2012?3?9? ??10:08?Chenglie He <chengjie.he at linaro.org>???
>
>> Hi,
>>
>> I am doing this on A9, echo mem >/sys/power/state is right, will trigger
>> kernel to sleep.
>>
>> -jack

>
some recipient promote:
"The message contains HTML subpart, therefore we consider it SPAM or
Outlook Virus"
so i resend the email, hope it not disturb u. thanks a lot.


From khilman at ti.com  Fri Mar  9 10:23:16 2012
From: khilman at ti.com (Kevin Hilman)
Date: Fri, 09 Mar 2012 07:23:16 -0800
Subject: [PATCH 0/2] ARM: OMAP2+: PM: code consolidation for 3.4
In-Reply-To: <1331273702.18015.92.camel@cumari> (Luciano Coelho's message of
 "Fri, 09 Mar 2012 08:15:02 +0200")
References: <20120202093600.12509.35052.stgit@dusk> <87ty39cc7s.fsf@ti.com>
 <alpine.DEB.2.00.1202021140060.586@utopia.booyaka.com>
 <alpine.DEB.2.00.1202021328450.586@utopia.booyaka.com>
 <CAKd1q9rq67gUyXn+rOL348YwaYQiqHR8UQCSd68fpxhZHHsYGA@mail.gmail.com>
 <87sjhjaqyi.fsf@ti.com> <1331232433.18015.69.camel@cumari>
 <alpine.DEB.2.00.1203081153540.9551@utopia.booyaka.com>
 <1331233547.18015.74.camel@cumari> <87d38mbxfu.fsf@ti.com>
 <1331273702.18015.92.camel@cumari>
Message-ID: <87haxx6bob.fsf@ti.com>

Luciano Coelho <coelho at ti.com> writes:

> Hi Kevin,
>
> On Thu, 2012-03-08 at 13:21 -0800, Kevin Hilman wrote: 
>> Luciano Coelho <coelho at ti.com> writes:
>> 
>> [...]
>> 
>> > Thanks, Paul! I was just chatting with Kevin about this on IRC.  With
>> > your patch and no_console_suspend, it works. :)
>> 
>> Just FYI... I've queued this patch from Paul and it's now queued by Tony
>> for v3.4 in his cleanup-pm branch.
>
> Great, thanks for the info!
>
> BTW, you and Paul said that it was not recommended to use
> no_console_suspend, but Ido (on CC) said that it can be useful for us,
> because we need to see if our own (wireless) stuff goes into suspend
> correctly.

no_console_suspend should not be needed there.  It is really only
intended as a *temporary* debug feature when suspend fails.

Since the console is disabled during suspend, if suspend fails, you
might not see the reason for failure.  So in this case, you enable
no_console_suspend just to see the suspend output, and why it's failing.

If suspend/resume succeed, you will see all the console output after
resume because even though the console is disabled, the printks are
buffered, so you will see them eventually.

So with a working suspend/resume, you will eventually see all the
console output.

So basically, any usage of no_console_suspend should be temporary, until
you figure out why suspend if failing. 

> Are there any real problems with no_console_suspend besides power
> consumption? Is it safe for us to simply apply Paul's patch when we need
> it?

There are important side effects of leaving the console enabled.
Namely, the console UART will stay clocked, and thus prevent it's
surrounding powerdomain from reaching a low power state.  UARTs can be
in either the PER or CORE powerdomains, so preventing them from reaching
the low powerstate will affect other drivers in those powerdomains.

For example, if your device is in the same powerdomain as the UART, it
will not be clock gated (or power gated) so the context save/restore
paths of those devices will not be exercised.


Kevin


From s.hauer at pengutronix.de  Fri Mar  9 02:23:50 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 9 Mar 2012 08:23:50 +0100
Subject: linux-next: manual merge of the arm-soc tree with the sound tree
In-Reply-To: <20120309180647.a27cc03a8997f9b38eb8ad0e@canb.auug.org.au>
References: <20120309180647.a27cc03a8997f9b38eb8ad0e@canb.auug.org.au>
Message-ID: <20120309072350.GV3852@pengutronix.de>

On Fri, Mar 09, 2012 at 06:06:47PM +1100, Stephen Rothwell wrote:
> Hi all,
> 
> Today's linux-next merge of the arm-soc tree got conflicts in
> arch/arm/mach-imx/mm-imx3.c and arch/arm/mach-imx/mm-imx5.c between
> commit 3bc34a614335 ("ARM: imx: convert audmux to a platform driver")
> from the sound tree and commits 38bb3630bcba ("ARM: mx35: Setup the AIPS
> registers") and aa6a9fa1f274 ("ARM: mx5: Use common function for
> configuring AIPS") from the arm-soc tree.
> 
> I fixed it up (see below) and can carry the fix as necessary.

Looks good, thanks

Sascha


> -- 
> Cheers,
> Stephen Rothwell                    sfr at canb.auug.org.au
> 
> diff --cc arch/arm/mach-imx/mm-imx3.c
> index 9c9b7f9,1646991..0000000
> --- a/arch/arm/mach-imx/mm-imx3.c
> +++ b/arch/arm/mach-imx/mm-imx3.c
> @@@ -177,8 -175,9 +179,12 @@@ void __init imx31_soc_init(void
>   	}
>   
>   	imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
> + 
> + 	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
> + 	imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
> ++
>  +	platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
>  +					ARRAY_SIZE(imx31_audmux_res));
>   }
>   #endif /* ifdef CONFIG_SOC_IMX31 */
>   
> @@@ -267,8 -262,9 +273,13 @@@ void __init imx35_soc_init(void
>   	}
>   
>   	imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
> + 
> + 	/* Setup AIPS registers */
> + 	imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
> + 	imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
> ++
>  +	/* i.mx35 has the i.mx31 type audmux */
>  +	platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
>  +					ARRAY_SIZE(imx35_audmux_res));
>   }
>   #endif /* ifdef CONFIG_SOC_IMX35 */
> diff --cc arch/arm/mach-imx/mm-imx5.c
> index dc7c4ed,92efece..0000000
> --- a/arch/arm/mach-imx/mm-imx5.c
> +++ b/arch/arm/mach-imx/mm-imx5.c
> @@@ -201,9 -185,10 +201,14 @@@ void __init imx51_soc_init(void
>   
>   	/* i.mx51 has the i.mx35 type sdma */
>   	imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
> + 
> + 	/* Setup AIPS registers */
> + 	imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
> + 	imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
> ++
>  +	/* i.mx51 has the i.mx31 type audmux */
>  +	platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
>  +					ARRAY_SIZE(imx51_audmux_res));
>   }
>   
>   void __init imx53_soc_init(void)
> @@@ -219,7 -204,8 +224,12 @@@
>   
>   	/* i.mx53 has the i.mx35 type sdma */
>   	imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
> + 
> + 	/* Setup AIPS registers */
> + 	imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
> + 	imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
> ++
>  +	/* i.mx53 has the i.mx31 type audmux */
>  +	platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
>  +					ARRAY_SIZE(imx53_audmux_res));
>   }



-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From grant.likely at secretlab.ca  Mon Mar 12 12:16:17 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 10:16:17 -0600
Subject: [PATCH] gpio/omap: fix wakeups on level-triggered GPIOs
In-Reply-To: <1330989004-9855-1-git-send-email-khilman@ti.com>
References: <1330989004-9855-1-git-send-email-khilman@ti.com>
Message-ID: <20120312161618.3EBD33E07B0@localhost>

On Mon,  5 Mar 2012 15:10:04 -0800, Kevin Hilman <khilman at ti.com> wrote:
> While both level- and edge-triggered GPIOs are capable of generating
> interrupts, only edge-triggered GPIOs are capable of generating a
> module-level wakeup to the PRCM (c.f. 34xx NDA TRM section 25.5.3.2.)
> 
> In order to ensure that devices using level-triggered GPIOs as
> interrupts can also cause wakeups (e.g. from idle), this patch enables
> edge-triggering for wakeup-enabled, level-triggered GPIOs when a GPIO
> bank is runtime-suspended (which also happens during idle.)
> 
> This fixes a problem found in GPMC-connected network cards with GPIO
> interrupts (e.g. smsc911x on Zoom3, Overo, ...) where network booting
> with NFSroot was very slow since the GPIO IRQs used by the NIC were
> not generating PRCM wakeups, and thus not waking the system from idle.
> NOTE: until v3.3, this boot-time problem was somewhat masked because
> the UART init prevented WFI during boot until the full serial driver
> was available.  Preventing WFI allowed regular GPIO interrupts to fire
> and this problem was not seen.  After the UART runtime PM cleanups, we
> no longer avoid WFI during boot, so GPIO IRQs that were not causing
> wakeups resulted in very slow IRQ response times.
> 
> Tested on platforms using level-triggered GPIOs for network IRQs using
> the SMSC911x NIC: 3530/Overo and 3630/Zoom3.
> 
> Reported-by: Tony Lindgren <tony at atomide.com>
> Tested-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> Tested-by: Tony Lindgren <tony at atomide.com>
> Signed-off-by: Kevin Hilman <khilman at ti.com>

Applied, thx.

g.

> ---
> Grant, here's another one for your gpio/next branch, and applies on
> top of the for_3.4/gpio/runtime-pm-cleanup branch you've already
> pulled from me.  While it's a fix, it's not a regressions since
> this problem has been around for awhile, so it can be for 3.4.
> 
>  drivers/gpio/gpio-omap.c |   34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index f49bd6f..752ae9b 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -1196,8 +1196,30 @@ static int omap_gpio_runtime_suspend(struct device *dev)
>  	struct gpio_bank *bank = platform_get_drvdata(pdev);
>  	u32 l1 = 0, l2 = 0;
>  	unsigned long flags;
> +	u32 wake_low, wake_hi;
>  
>  	spin_lock_irqsave(&bank->lock, flags);
> +
> +	/*
> +	 * Only edges can generate a wakeup event to the PRCM.
> +	 *
> +	 * Therefore, ensure any wake-up capable GPIOs have
> +	 * edge-detection enabled before going idle to ensure a wakeup
> +	 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
> +	 * NDA TRM 25.5.3.1)
> +	 *
> +	 * The normal values will be restored upon ->runtime_resume()
> +	 * by writing back the values saved in bank->context.
> +	 */
> +	wake_low = bank->context.leveldetect0 & bank->context.wake_en;
> +	if (wake_low)
> +		__raw_writel(wake_low | bank->context.fallingdetect,
> +			     bank->base + bank->regs->fallingdetect);
> +	wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
> +	if (wake_hi)
> +		__raw_writel(wake_hi | bank->context.risingdetect,
> +			     bank->base + bank->regs->risingdetect);
> +
>  	if (bank->power_mode != OFF_MODE) {
>  		bank->power_mode = 0;
>  		goto update_gpio_context_count;
> @@ -1246,6 +1268,18 @@ static int omap_gpio_runtime_resume(struct device *dev)
>  
>  	spin_lock_irqsave(&bank->lock, flags);
>  	_gpio_dbck_enable(bank);
> +
> +	/*
> +	 * In ->runtime_suspend(), level-triggered, wakeup-enabled
> +	 * GPIOs were set to edge trigger also in order to be able to
> +	 * generate a PRCM wakeup.  Here we restore the
> +	 * pre-runtime_suspend() values for edge triggering.
> +	 */
> +	__raw_writel(bank->context.fallingdetect,
> +		     bank->base + bank->regs->fallingdetect);
> +	__raw_writel(bank->context.risingdetect,
> +		     bank->base + bank->regs->risingdetect);
> +
>  	if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
>  		spin_unlock_irqrestore(&bank->lock, flags);
>  		return 0;
> -- 
> 1.7.9.2
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From philippe.retornaz at epfl.ch  Fri Mar  9 09:55:13 2012
From: philippe.retornaz at epfl.ch (=?utf-8?q?Philippe=20R=C3=A9tornaz?=)
Date: Fri,  9 Mar 2012 15:55:13 +0100
Subject: [PATCH 1/4] add a mc13783 codec driver
In-Reply-To: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>

From: Sascha Hauer <s.hauer at pengutronix.de>

sha 20111307:
- rebased to 3.0-rc2
- implement tdm slot settings
- made it work with single ssi port
- more register names instead of hardcoded numbers

philippe 20120803:
- Add headset detection
- add mic2 bias
- enable headset output by default

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Signed-off-by: Philippe R?tornaz <philippe.retornaz at epfl.ch>
---
 drivers/mfd/mc13xxx-core.c  |    3 +-
 include/linux/mfd/mc13xxx.h |   11 +
 sound/soc/codecs/Kconfig    |    4 +
 sound/soc/codecs/Makefile   |    2 +
 sound/soc/codecs/mc13783.c  | 1036 +++++++++++++++++++++++++++++++++++++++++++
 sound/soc/codecs/mc13783.h  |   30 ++
 6 files changed, 1085 insertions(+), 1 deletions(-)
 create mode 100644 sound/soc/codecs/mc13783.c
 create mode 100644 sound/soc/codecs/mc13783.h

diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index 7122386..7b7b55e 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -807,7 +807,8 @@ err_revision:
 		mc13xxx_add_subdevice(mc13xxx, "%s-adc");
 
 	if (mc13xxx->flags & MC13XXX_USE_CODEC)
-		mc13xxx_add_subdevice(mc13xxx, "%s-codec");
+		mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
+					pdata->codec, sizeof(*pdata->codec));
 
 	if (mc13xxx->flags & MC13XXX_USE_RTC)
 		mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h
index b86ee45..3ce5f3c 100644
--- a/include/linux/mfd/mc13xxx.h
+++ b/include/linux/mfd/mc13xxx.h
@@ -157,6 +157,16 @@ struct mc13xxx_buttons_platform_data {
 	unsigned short b3on_key;
 };
 
+enum mc13783_ssi_port {
+	MC13783_SSI1_PORT,
+	MC13783_SSI2_PORT,
+};
+
+struct mc13xxx_codec_platform_data {
+	enum mc13783_ssi_port adc_ssi_port;
+	enum mc13783_ssi_port dac_ssi_port;
+};
+
 struct mc13xxx_platform_data {
 #define MC13XXX_USE_TOUCHSCREEN (1 << 0)
 #define MC13XXX_USE_CODEC	(1 << 1)
@@ -167,6 +177,7 @@ struct mc13xxx_platform_data {
 	struct mc13xxx_regulator_platform_data regulators;
 	struct mc13xxx_leds_platform_data *leds;
 	struct mc13xxx_buttons_platform_data *buttons;
+	struct mc13xxx_codec_platform_data *codec;
 };
 
 #define MC13XXX_ADC_MODE_TS		1
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 7c205e7..5d58ffa 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -41,6 +41,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_MAX98095 if I2C
 	select SND_SOC_MAX9850 if I2C
 	select SND_SOC_MAX9877 if I2C
+	select SND_SOC_MC13783 if SPI
 	select SND_SOC_PCM3008
 	select SND_SOC_RT5631 if I2C
 	select SND_SOC_SGTL5000 if I2C
@@ -224,6 +225,9 @@ config SND_SOC_MAX98095
 config SND_SOC_MAX9850
 	tristate
 
+config SND_SOC_MC13783
+	tristate
+
 config SND_SOC_PCM3008
        tristate
 
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index de80781..4c00c64 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -28,6 +28,7 @@ snd-soc-lm4857-objs := lm4857.o
 snd-soc-max98088-objs := max98088.o
 snd-soc-max98095-objs := max98095.o
 snd-soc-max9850-objs := max9850.o
+snd-soc-mc13783-objs := mc13783.o
 snd-soc-pcm3008-objs := pcm3008.o
 snd-soc-rt5631-objs := rt5631.o
 snd-soc-sgtl5000-objs := sgtl5000.o
@@ -132,6 +133,7 @@ obj-$(CONFIG_SND_SOC_JZ4740_CODEC)	+= snd-soc-jz4740-codec.o
 obj-$(CONFIG_SND_SOC_MAX98088)	+= snd-soc-max98088.o
 obj-$(CONFIG_SND_SOC_MAX98095)	+= snd-soc-max98095.o
 obj-$(CONFIG_SND_SOC_MAX9850)	+= snd-soc-max9850.o
+obj-$(CONFIG_SND_SOC_MC13783)	+= snd-soc-mc13783.o
 obj-$(CONFIG_SND_SOC_PCM3008)	+= snd-soc-pcm3008.o
 obj-$(CONFIG_SND_SOC_RT5631)	+= snd-soc-rt5631.o
 obj-$(CONFIG_SND_SOC_SGTL5000)  += snd-soc-sgtl5000.o
diff --git a/sound/soc/codecs/mc13783.c b/sound/soc/codecs/mc13783.c
new file mode 100644
index 0000000..d172691
--- /dev/null
+++ b/sound/soc/codecs/mc13783.c
@@ -0,0 +1,1036 @@
+/*
+ * Copyright 2008 Juergen Beisert, kernel at pengutronix.de
+ * Copyright 2009 Sascha Hauer, s.hauer at pengutronix.de
+ *
+ * Initial development of this code was funded by
+ * Phytec Messtechnik GmbH, http://www.phytec.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/mfd/mc13xxx.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/control.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/soc-dapm.h>
+
+#include "mc13783.h"
+
+#define MC13783_AUDIO_RX0	36
+#define MC13783_AUDIO_RX1	37
+#define MC13783_AUDIO_TX	38
+#define MC13783_SSI_NETWORK	39
+#define MC13783_AUDIO_CODEC	40
+#define MC13783_AUDIO_DAC	41
+
+#define AUDIO_RX0_ALSPEN		(1 << 5)
+#define AUDIO_RX0_ALSPSEL		(1 << 7)
+#define AUDIO_RX0_ADDCDC		(1 << 21)
+#define AUDIO_RX0_ADDSTDC		(1 << 22)
+#define AUDIO_RX0_ADDRXIN		(1 << 23)
+
+#define AUDIO_RX1_PGARXEN		(1 << 0);
+#define AUDIO_RX1_PGASTEN		(1 << 5)
+#define AUDIO_RX1_ARXINEN		(1 << 10)
+
+#define AUDIO_TX_AMC1REN		(1 << 5)
+#define AUDIO_TX_AMC1LEN		(1 << 7)
+#define AUDIO_TX_AMC2EN			(1 << 9)
+#define AUDIO_TX_ATXINEN		(1 << 11)
+#define AUDIO_TX_RXINREC		(1 << 13)
+
+#define SSI_NETWORK_CDCTXRXSLOT(x)	(((x) & 0x3) << 2)
+#define SSI_NETWORK_CDCTXSECSLOT(x)	(((x) & 0x3) << 4)
+#define SSI_NETWORK_CDCRXSECSLOT(x)	(((x) & 0x3) << 6)
+#define SSI_NETWORK_CDCRXSECGAIN(x)	(((x) & 0x3) << 8)
+#define SSI_NETWORK_CDCSUMGAIN(x)	(1 << 10)
+#define SSI_NETWORK_CDCFSDLY(x)		(1 << 11)
+#define SSI_NETWORK_DAC_SLOTS_8		(1 << 12)
+#define SSI_NETWORK_DAC_SLOTS_4		(2 << 12)
+#define SSI_NETWORK_DAC_SLOTS_2		(3 << 12)
+#define SSI_NETWORK_DAC_SLOT_MASK	(3 << 12)
+#define SSI_NETWORK_DAC_RXSLOT_0_1	(0 << 14)
+#define SSI_NETWORK_DAC_RXSLOT_2_3	(1 << 14)
+#define SSI_NETWORK_DAC_RXSLOT_4_5	(2 << 14)
+#define SSI_NETWORK_DAC_RXSLOT_6_7	(3 << 14)
+#define SSI_NETWORK_DAC_RXSLOT_MASK	(3 << 14)
+#define SSI_NETWORK_STDCRXSECSLOT(x)	(((x) & 0x3) << 16)
+#define SSI_NETWORK_STDCRXSECGAIN(x)	(((x) & 0x3) << 18)
+#define SSI_NETWORK_STDCSUMGAIN		(1 << 20)
+
+/*
+ * MC13783_AUDIO_CODEC and MC13783_AUDIO_DAC mostly share the same
+ * register layout
+ */
+#define AUDIO_SSI_SEL			(1 << 0)
+#define AUDIO_CLK_SEL			(1 << 1)
+#define AUDIO_CSM			(1 << 2)
+#define AUDIO_BCL_INV			(1 << 3)
+#define AUDIO_CFS_INV			(1 << 4)
+#define AUDIO_CFS(x)			(((x) & 0x3) << 5)
+#define AUDIO_CLK(x)			(((x) & 0x7) << 7)
+#define AUDIO_C_EN			(1 << 11)
+#define AUDIO_C_CLK_EN			(1 << 12)
+#define AUDIO_C_RESET			(1 << 15)
+
+#define AUDIO_CODEC_CDCFS8K16K		(1 << 10)
+#define AUDIO_DAC_CFS_DLY_B		(1 << 10)
+
+struct mc13783_priv {
+	struct snd_soc_codec codec;
+	struct mc13xxx *mc13xxx;
+
+	u32 reg_cache[42];
+
+	int mc13783_asp_val;
+	int mc13783_alsp_val;
+	enum mc13783_ssi_port adc_ssi_port;
+	enum mc13783_ssi_port dac_ssi_port;
+	int mc13783_ahsout_val;
+};
+
+static unsigned int mc13783_read(struct snd_soc_codec *codec,
+	unsigned int reg)
+{
+	struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
+
+	return priv->reg_cache[reg];
+}
+
+static int mc13783_write(struct snd_soc_codec *codec,
+	unsigned int reg, unsigned int value)
+{
+	struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
+	int ret;
+
+	mc13xxx_lock(priv->mc13xxx);
+	priv->reg_cache[reg] = value;
+
+	ret = mc13xxx_reg_write(priv->mc13xxx, reg, value);
+
+	mc13xxx_unlock(priv->mc13xxx);
+
+	return ret;
+}
+
+/* Mapping between sample rates and register value */
+static unsigned int mc13783_rates[] = {
+	8000, 11025, 12000, 16000,
+	22050, 24000, 32000, 44100,
+	48000, 64000, 96000
+};
+
+static int mc13783_pcm_hw_params_dac(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params,
+				struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_codec *codec = rtd->codec;
+	unsigned int rate = params_rate(params);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(mc13783_rates); i++) {
+		if (rate == mc13783_rates[i]) {
+			snd_soc_update_bits(codec, MC13783_AUDIO_DAC,
+					0xf << 17, i << 17);
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int mc13783_pcm_hw_params_codec(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params,
+				struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_codec *codec = rtd->codec;
+	unsigned int rate = params_rate(params);
+	unsigned int val;
+
+	switch (rate) {
+	case 8000:
+		val = 0;
+		break;
+	case 16000:
+		val = AUDIO_CODEC_CDCFS8K16K;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	snd_soc_update_bits(codec, MC13783_AUDIO_CODEC, AUDIO_CODEC_CDCFS8K16K,
+			val);
+
+	return 0;
+}
+
+static int mc13783_pcm_hw_params_sync(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params,
+				struct snd_soc_dai *dai)
+{
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		return mc13783_pcm_hw_params_dac(substream, params, dai);
+	else
+		return mc13783_pcm_hw_params_codec(substream, params, dai);
+}
+
+static int mc13783_set_fmt(struct snd_soc_dai *dai, unsigned int fmt, unsigned int reg)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	unsigned int val;
+
+	val = mc13783_read(codec, reg);
+
+	val &= ~AUDIO_CFS(3);
+	val &= ~AUDIO_BCL_INV;
+	val &= ~AUDIO_CFS_INV;
+	val &= ~AUDIO_CSM;
+	val &= ~AUDIO_C_CLK_EN;
+
+	/* DAI mode */
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		val |= AUDIO_CFS(2);
+		break;
+	case SND_SOC_DAIFMT_DSP_A:
+		val |= AUDIO_CFS(1);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* DAI clock inversion */
+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+	case SND_SOC_DAIFMT_NB_NF:
+		val |= AUDIO_BCL_INV;
+		break;
+	case SND_SOC_DAIFMT_NB_IF:
+		val |= AUDIO_BCL_INV;
+		val |= AUDIO_CFS_INV;
+		break;
+	case SND_SOC_DAIFMT_IB_NF:
+		break;
+	case SND_SOC_DAIFMT_IB_IF:
+		val |= AUDIO_CFS_INV;
+		break;
+	}
+
+	/* DAI clock master masks */
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBM_CFM:
+		val |= AUDIO_C_CLK_EN;
+		break;
+	case SND_SOC_DAIFMT_CBS_CFS:
+		val |= AUDIO_CSM;
+		break;
+	case SND_SOC_DAIFMT_CBM_CFS:
+	case SND_SOC_DAIFMT_CBS_CFM:
+		return -EINVAL;
+	}
+
+	val |= AUDIO_C_RESET;
+
+	mc13783_write(codec, reg, val);
+
+	return 0;
+}
+
+static int mc13783_set_fmt_async(struct snd_soc_dai *dai, unsigned int fmt)
+{
+	if (dai->id == MC13783_ID_STEREO_DAC)
+		return mc13783_set_fmt(dai, fmt, MC13783_AUDIO_DAC);
+	else
+		return mc13783_set_fmt(dai, fmt, MC13783_AUDIO_CODEC);
+}
+
+static int mc13783_set_fmt_sync(struct snd_soc_dai *dai, unsigned int fmt)
+{
+	int ret;
+
+	ret = mc13783_set_fmt(dai, fmt, MC13783_AUDIO_DAC);
+	if (ret)
+		return ret;
+
+	/*
+	 * In synchronous mode force the voice codec into slave mode
+	 * so that the clock / framesync from the stereo DAC is used
+	 */
+	fmt &= ~SND_SOC_DAIFMT_MASTER_MASK;
+	fmt |= SND_SOC_DAIFMT_CBS_CFS;
+	ret = mc13783_set_fmt(dai, fmt, MC13783_AUDIO_CODEC);
+
+	return ret;
+}
+
+static int mc13783_sysclk[] = {
+	13000000,
+	15360000,
+	16800000,
+	-1,
+	26000000,
+	-1, /* 12000000, invalid for voice codec */
+	-1, /* 3686400, invalid for voice codec */
+	33600000,
+};
+
+static int mc13783_set_sysclk(struct snd_soc_dai *dai,
+				  int clk_id, unsigned int freq, int dir,
+				  unsigned int reg)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	int clk;
+	unsigned int val;
+
+	val = mc13783_read(codec, reg);
+
+	val &= ~AUDIO_CLK(0x7);
+	val &= ~AUDIO_CLK_SEL;
+
+	for (clk = 0; clk < ARRAY_SIZE(mc13783_sysclk); clk++) {
+		if (mc13783_sysclk[clk] < 0)
+			continue;
+		if (mc13783_sysclk[clk] == freq)
+			break;
+	}
+
+	if (clk == ARRAY_SIZE(mc13783_sysclk))
+		return -EINVAL;
+
+	if (clk_id == MC13783_CLK_CLIB)
+		val |= AUDIO_CLK_SEL;
+
+	val |= AUDIO_CLK(clk);
+
+	mc13783_write(codec, reg, val);
+
+	return 0;
+}
+
+static int mc13783_set_sysclk_dac(struct snd_soc_dai *dai,
+				  int clk_id, unsigned int freq, int dir)
+{
+	return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC);
+}
+
+static int mc13783_set_sysclk_codec(struct snd_soc_dai *dai,
+				  int clk_id, unsigned int freq, int dir)
+{
+	return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC);
+}
+
+static int mc13783_set_sysclk_sync(struct snd_soc_dai *dai,
+				  int clk_id, unsigned int freq, int dir)
+{
+	int ret;
+
+	ret = mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC);
+	if (ret)
+		return ret;
+
+	return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC);
+}
+
+static int mc13783_set_tdm_slot_dac(struct snd_soc_dai *dai,
+	unsigned int tx_mask, unsigned int rx_mask, int slots,
+	int slot_width)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	unsigned int val;
+
+	val = mc13783_read(codec, MC13783_SSI_NETWORK);
+
+	val &= ~SSI_NETWORK_DAC_SLOT_MASK;
+	val &= ~SSI_NETWORK_DAC_RXSLOT_MASK;
+
+	switch (slots) {
+	case 2:
+		val |= SSI_NETWORK_DAC_SLOTS_2;
+		break;
+	case 4:
+		val |= SSI_NETWORK_DAC_SLOTS_4;
+		break;
+	case 8:
+		val |= SSI_NETWORK_DAC_SLOTS_8;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch (rx_mask) {
+	case 0xfffffffc:
+		val |= SSI_NETWORK_DAC_RXSLOT_0_1;
+		break;
+	case 0xfffffff3:
+		val |= SSI_NETWORK_DAC_RXSLOT_2_3;
+		break;
+	case 0xffffffcf:
+		val |= SSI_NETWORK_DAC_RXSLOT_4_5;
+		break;
+	case 0xffffff3f:
+		val |= SSI_NETWORK_DAC_RXSLOT_6_7;
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	mc13783_write(codec, MC13783_SSI_NETWORK, val);
+
+	return 0;
+}
+
+static int mc13783_set_tdm_slot_codec(struct snd_soc_dai *dai,
+	unsigned int tx_mask, unsigned int rx_mask, int slots,
+	int slot_width)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	unsigned int val;
+
+	if (slots != 4)
+		return -EINVAL;
+
+	if (tx_mask != 0xfffffffc)
+		return -EINVAL;
+
+	val = mc13783_read(codec, MC13783_SSI_NETWORK);
+
+	val &= ~(0x3f << 0);
+	val |= (0x00 << 2);	/* primary timeslot RX/TX(?) is 0 */
+	val |= (0x01 << 4);	/* secondary timeslot TX is 1 */
+
+	mc13783_write(codec, MC13783_SSI_NETWORK, val);
+
+	return 0;
+}
+
+static int mc13783_set_tdm_slot_sync(struct snd_soc_dai *dai,
+	unsigned int tx_mask, unsigned int rx_mask, int slots,
+	int slot_width)
+{
+	int ret;
+
+	ret = mc13783_set_tdm_slot_dac(dai, tx_mask, rx_mask, slots,
+			slot_width);
+	if (ret)
+		return ret;
+
+	ret = mc13783_set_tdm_slot_codec(dai, tx_mask, rx_mask, slots,
+			slot_width);
+
+	return ret;
+}
+
+static void mc13783_startup(struct snd_soc_dai *dai, int reg)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	unsigned int val;
+
+	val = mc13783_read(codec, reg);
+	val &= ~AUDIO_C_RESET;
+	val |= AUDIO_C_EN;
+	mc13783_write(codec, reg, val);
+}
+
+static int mc13783_startup_dac(struct snd_pcm_substream *stream,
+		struct snd_soc_dai *dai)
+{
+	mc13783_startup(dai, MC13783_AUDIO_DAC);
+	return 0;
+}
+
+static int mc13783_startup_codec(struct snd_pcm_substream *substream,
+		struct snd_soc_dai *dai)
+{
+	mc13783_startup(dai, MC13783_AUDIO_CODEC);
+	return 0;
+}
+
+static int mc13783_startup_sync(struct snd_pcm_substream *substream,
+		struct snd_soc_dai *dai)
+{
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		mc13783_startup(dai, MC13783_AUDIO_DAC);
+	else
+		mc13783_startup(dai, MC13783_AUDIO_CODEC);
+	return 0;
+}
+
+static void mc13783_shutdown(struct snd_soc_dai *dai, int reg)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	unsigned int val;
+
+	val = mc13783_read(codec, reg);
+	mc13783_write(codec, reg, val & ~AUDIO_C_EN);
+}
+
+static void mc13783_shutdown_dac(struct snd_pcm_substream *substream,
+		struct snd_soc_dai *dai)
+{
+	mc13783_shutdown(dai, MC13783_AUDIO_DAC);
+}
+
+static void mc13783_shutdown_codec(struct snd_pcm_substream *substream,
+		struct snd_soc_dai *dai)
+{
+	mc13783_shutdown(dai, MC13783_AUDIO_CODEC);
+}
+
+static void mc13783_shutdown_sync(struct snd_pcm_substream *substream,
+		struct snd_soc_dai *dai)
+{
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		mc13783_shutdown(dai, MC13783_AUDIO_DAC);
+	else
+		mc13783_shutdown(dai, MC13783_AUDIO_CODEC);
+}
+
+static int mc13783_get_alsp(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+	struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
+
+	ucontrol->value.integer.value[0] = priv->mc13783_alsp_val;
+
+	return 0;
+}
+
+static int mc13783_put_alsp(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec =  snd_kcontrol_chip(kcontrol);
+	struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
+	unsigned int val;
+
+	priv->mc13783_alsp_val = ucontrol->value.integer.value[0];
+
+	val = mc13783_read(codec, MC13783_AUDIO_RX0);
+
+	val &= ~(AUDIO_RX0_ALSPEN | AUDIO_RX0_ALSPSEL);
+
+	if (priv->mc13783_alsp_val)
+		val |= AUDIO_RX0_ALSPEN;
+
+	if (priv->mc13783_alsp_val == 2)
+		val |= AUDIO_RX0_ALSPSEL;
+
+	mc13783_write(codec, MC13783_AUDIO_RX0, val);
+
+	return 0;
+}
+
+static int mc13783_ahsout_i_get(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+	struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
+
+	ucontrol->value.integer.value[0] = priv->mc13783_ahsout_val;
+
+	return 0;
+}
+
+static int mc13783_ahsout_i_put(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+	struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
+	unsigned int reg;
+
+	priv->mc13783_ahsout_val = ucontrol->value.integer.value[0];
+
+	reg = mc13783_read(codec, MC13783_AUDIO_RX0);
+
+	reg &= ~((1 << 13) | (1 << 14));
+
+	if (priv->mc13783_ahsout_val == 1)
+		reg |= 1 << 13;
+	else if (priv->mc13783_ahsout_val == 2)
+		reg |= 1 << 14;
+
+
+	mc13783_write(codec, MC13783_AUDIO_RX0, reg);
+
+	return 0;
+}
+
+static int mc13783_pcm_get(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec =  snd_kcontrol_chip(kcontrol);
+	int val;
+
+	val = mc13783_read(codec, MC13783_AUDIO_RX0);
+	ucontrol->value.enumerated.item[0] = (val >> 22) & 1;
+
+	return 0;
+}
+
+static int mc13783_pcm_put(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec =  snd_kcontrol_chip(kcontrol);
+	unsigned int r36, r37;
+
+	r36 = mc13783_read(codec, MC13783_AUDIO_RX0);
+	r37 = mc13783_read(codec, MC13783_AUDIO_RX1);
+
+	r36 &= ~AUDIO_RX0_ADDSTDC;
+	r37 &= ~AUDIO_RX1_PGASTEN;
+
+	if (ucontrol->value.enumerated.item[0]) {
+		r36 |= AUDIO_RX0_ADDSTDC;
+		r37 |= AUDIO_RX1_PGASTEN;
+	}
+
+	mc13783_write(codec, MC13783_AUDIO_RX0, r36);
+	mc13783_write(codec, MC13783_AUDIO_RX1, r37);
+
+	return 0;
+}
+
+static int mc13783_linein_get(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec =  snd_kcontrol_chip(kcontrol);
+	int val;
+
+	val = mc13783_read(codec, MC13783_AUDIO_RX0);
+	ucontrol->value.enumerated.item[0] = (val >> 23) & 1;
+
+	return 0;
+}
+
+static int mc13783_linein_put(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec =  snd_kcontrol_chip(kcontrol);
+	unsigned int r36, r37;
+
+	r36 = mc13783_read(codec, MC13783_AUDIO_RX0);
+	r37 = mc13783_read(codec, MC13783_AUDIO_RX1);
+
+	r36 &= ~AUDIO_RX0_ADDRXIN;
+	r37 &= ~AUDIO_RX1_ARXINEN;
+
+	if (ucontrol->value.enumerated.item[0]) {
+		r36 |= AUDIO_RX0_ADDRXIN;
+		r37 |= AUDIO_RX1_ARXINEN;
+	}
+
+	mc13783_write(codec, MC13783_AUDIO_RX0, r36);
+	mc13783_write(codec, MC13783_AUDIO_RX1, r37);
+
+	return 0;
+}
+
+static int mc13783_voice_get(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec =  snd_kcontrol_chip(kcontrol);
+	int val;
+
+	val = mc13783_read(codec, MC13783_AUDIO_RX0);
+	ucontrol->value.enumerated.item[0] = (val >> 21) & 1;
+
+	return 0;
+}
+
+static int mc13783_voice_put(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec =  snd_kcontrol_chip(kcontrol);
+	unsigned int r36, r37;
+
+	r36 = mc13783_read(codec, MC13783_AUDIO_RX0);
+	r37 = mc13783_read(codec, MC13783_AUDIO_RX1);
+
+	r36 &= ~AUDIO_RX0_ADDCDC;
+	r37 &= ~AUDIO_RX1_PGARXEN;
+
+	if (ucontrol->value.enumerated.item[0]) {
+		r36 |= AUDIO_RX0_ADDCDC;
+		r37 |= AUDIO_RX1_PGARXEN;
+	}
+
+	mc13783_write(codec, MC13783_AUDIO_RX0, r36);
+	mc13783_write(codec, MC13783_AUDIO_RX1, r37);
+
+	return 0;
+}
+
+static int mc13783_capure_cache;
+
+static int mc13783_get_capture(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.enumerated.item[0] = mc13783_capure_cache;
+	return 0;
+}
+
+static int mc13783_put_capture(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec =  snd_kcontrol_chip(kcontrol);
+	unsigned int r38, change;
+
+	r38 = mc13783_read(codec, MC13783_AUDIO_TX);
+
+	change = (mc13783_capure_cache != ucontrol->value.enumerated.item[0]);
+	mc13783_capure_cache = ucontrol->value.enumerated.item[0];
+	r38 &= ~(AUDIO_TX_AMC1REN | AUDIO_TX_AMC2EN | AUDIO_TX_ATXINEN |
+			AUDIO_TX_RXINREC | AUDIO_TX_AMC1LEN);
+
+	switch (mc13783_capure_cache) {
+	case 0:
+		break;
+	case 1:
+		r38 |= AUDIO_TX_RXINREC;
+		break;
+	case 2:
+		r38 |= AUDIO_TX_AMC1REN | AUDIO_TX_AMC1LEN;
+		break;
+	case 3:
+		r38 |= AUDIO_TX_AMC1REN;
+		break;
+	case 4:
+		r38 |= AUDIO_TX_AMC2EN;
+		break;
+	case 5:
+		r38 |= AUDIO_TX_AMC1LEN | AUDIO_TX_AMC2EN;
+		break;
+	case 6:
+		r38 |= AUDIO_TX_ATXINEN;
+		break;
+	case 7:
+		r38 |= AUDIO_TX_AMC1LEN | AUDIO_TX_ATXINEN;
+		break;
+	case 8:
+		r38 |= AUDIO_TX_AMC1LEN | AUDIO_TX_RXINREC;
+		break;
+	case 9:
+		r38 |= AUDIO_TX_AMC1LEN;
+		break;
+	default:
+		break;
+	}
+
+	mc13783_write(codec, MC13783_AUDIO_TX, r38);
+
+	return change;
+}
+
+static const char *mc13783_asp[] = {"Off", "Codec", "Right"};
+static const char *mc13783_alsp[] = {"Off", "Codec", "Right"};
+
+static const char *mc13783_ahs[] = {"Codec", "Mixer"};
+
+static const char *mc13783_ahsout[] = {"Off", "Auto", "On"};
+
+static const char *mc13783_arxout[] = {"Codec", "Mixer"};
+
+static const char *mc13783_capture[] = {"off/off", "rxinl/rxinr",
+	"mc1lin/mc1rin", "off/mc1rin", "off/mc2in", "mc1lin/mc2in",
+	"off/txin", "mc1lin/txin", "mc1lin/rxinr", "mc1lin/off"};
+
+static const char *mc13783_3d_mixer[] =	{"Stereo", "Phase Mix",
+	"Mono", "Mono Mix"};
+
+static const struct soc_enum mc13783_enum_asp =
+	SOC_ENUM_SINGLE(MC13783_AUDIO_RX0, 3, ARRAY_SIZE(mc13783_asp), mc13783_asp);
+
+static const struct soc_enum mc13783_enum_alsp =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mc13783_alsp), mc13783_alsp);
+
+static const struct soc_enum mc13783_enum_ahs =
+	SOC_ENUM_SINGLE(MC13783_AUDIO_RX0, 11, ARRAY_SIZE(mc13783_ahs),
+			mc13783_ahs);
+
+static const struct soc_enum mc13783_enum_ahsout =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mc13783_ahsout), mc13783_ahsout);
+
+static const struct soc_enum mc13783_enum_arxout =
+	SOC_ENUM_SINGLE(MC13783_AUDIO_RX0, 17, ARRAY_SIZE(mc13783_arxout),
+			mc13783_arxout);
+
+static const struct soc_enum mc13783_enum_capture =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mc13783_capture), mc13783_capture);
+
+static const struct soc_enum mc13783_enum_3d_mixer =
+	SOC_ENUM_SINGLE(MC13783_AUDIO_RX1, 16, ARRAY_SIZE(mc13783_3d_mixer),
+			mc13783_3d_mixer);
+
+static struct snd_kcontrol_new mc13783_control_list[] = {
+	/* Output Routing */
+	SOC_ENUM("Asp Source", mc13783_enum_asp),
+	SOC_ENUM_EXT("Alsp Source", mc13783_enum_alsp, mc13783_get_alsp,
+			mc13783_put_alsp),
+	SOC_ENUM("Ahs Source", mc13783_enum_ahs),
+	SOC_SINGLE("Ahsr enable", MC13783_AUDIO_RX0, 9, 1, 0),
+	SOC_SINGLE("Ahsl enable", MC13783_AUDIO_RX0, 10, 1, 0),
+	SOC_ENUM_EXT("Ahs enable", mc13783_enum_ahsout, mc13783_ahsout_i_get,
+			mc13783_ahsout_i_put),
+	SOC_ENUM("Arxout Source", mc13783_enum_arxout),
+	SOC_SINGLE("ArxoutR enable", MC13783_AUDIO_RX0, 16, 1, 0),
+	SOC_SINGLE("ArxoutL enable", MC13783_AUDIO_RX0, 15, 1, 0),
+	SOC_SINGLE_EXT("PCM Playback Switch", 0, 0, 1, 0, mc13783_pcm_get,
+			mc13783_pcm_put),
+	SOC_SINGLE("PCM Playback Volume", MC13783_AUDIO_RX1, 6, 15, 0),
+	SOC_SINGLE_EXT("Line in Switch", 0, 0, 1, 0, mc13783_linein_get,
+			mc13783_linein_put),
+	SOC_SINGLE("Line in Volume", MC13783_AUDIO_RX1, 12, 15, 0),
+	SOC_ENUM_EXT("Capture Source", mc13783_enum_capture, mc13783_get_capture,
+			mc13783_put_capture),
+	SOC_DOUBLE("PCM Capture Volume", MC13783_AUDIO_TX, 19, 14, 31, 0),
+	SOC_ENUM("3D Control", mc13783_enum_3d_mixer),
+	SOC_SINGLE("MC1 Bias enable", 38, 0, 1, 0),
+	SOC_SINGLE("MC2 Bias enable", 38, 1, 1, 0),
+	SOC_SINGLE("Codec Bypass enable", MC13783_AUDIO_CODEC, 16, 1, 0),
+	SOC_SINGLE_EXT("Voice Codec Switch", 0, 0, 1, 0, mc13783_voice_get,
+			mc13783_voice_put),
+	SOC_SINGLE("Voice Codec Volume", MC13783_AUDIO_RX1, 1, 15, 0),
+};
+
+static int mc13783_probe(struct snd_soc_codec *codec)
+{
+	struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
+	int i, ret = 0, val;
+
+	/* these are the reset values */
+	priv->reg_cache[MC13783_AUDIO_RX0]  = 0x001E00;
+	priv->reg_cache[MC13783_AUDIO_RX1]  = 0x00d35A;
+	priv->reg_cache[MC13783_AUDIO_TX]    = 0x420000;
+	priv->reg_cache[MC13783_SSI_NETWORK] = 0x013060;
+	priv->reg_cache[MC13783_AUDIO_CODEC] = 0x180027;
+	priv->reg_cache[MC13783_AUDIO_DAC]   = 0x0e0004;
+
+	/* VAUDIOON -> supply audio part, BIAS enable */
+	priv->reg_cache[MC13783_AUDIO_RX0] |= 0x3;
+
+	priv->mc13783_ahsout_val = 2;
+
+	for (i = 36; i < 42; i++)
+		mc13783_write(codec, i, priv->reg_cache[i]);
+
+	snd_soc_add_controls(codec, mc13783_control_list,
+			     ARRAY_SIZE(mc13783_control_list));
+
+	val = mc13783_read(codec, MC13783_AUDIO_CODEC);
+	if (priv->adc_ssi_port == MC13783_SSI1_PORT)
+		val &= ~AUDIO_SSI_SEL;
+	else
+		val |= AUDIO_SSI_SEL;
+	mc13783_write(codec, MC13783_AUDIO_CODEC, val);
+
+	val = mc13783_read(codec, MC13783_AUDIO_DAC);
+	if (priv->dac_ssi_port == MC13783_SSI1_PORT)
+		val &= ~AUDIO_SSI_SEL;
+	else
+		val |= AUDIO_SSI_SEL;
+	mc13783_write(codec, MC13783_AUDIO_DAC, val);
+
+	return ret;
+}
+
+static int mc13783_remove(struct snd_soc_codec *codec)
+{
+	unsigned int val;
+
+	val = mc13783_read(codec, MC13783_AUDIO_RX0);
+
+	/* VAUDIOON -> switch off audio part, BIAS disable */
+	val &= ~0x3;
+
+	mc13783_write(codec, MC13783_AUDIO_RX0, val);
+
+	return 0;
+}
+
+#define MC13783_RATES_RECORD (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000)
+
+#define MC13783_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
+	SNDRV_PCM_FMTBIT_S24_LE)
+
+static struct snd_soc_dai_ops mc13783_ops_dac = {
+	.hw_params	= mc13783_pcm_hw_params_dac,
+	.set_fmt	= mc13783_set_fmt_async,
+	.set_sysclk	= mc13783_set_sysclk_dac,
+	.set_tdm_slot	= mc13783_set_tdm_slot_dac,
+	.prepare	= mc13783_startup_dac,
+	.shutdown	= mc13783_shutdown_dac,
+};
+
+static struct snd_soc_dai_ops mc13783_ops_codec = {
+	.hw_params	= mc13783_pcm_hw_params_codec,
+	.set_fmt	= mc13783_set_fmt_async,
+	.set_sysclk	= mc13783_set_sysclk_codec,
+	.set_tdm_slot	= mc13783_set_tdm_slot_codec,
+	.prepare	= mc13783_startup_codec,
+	.shutdown	= mc13783_shutdown_codec,
+};
+
+/* 
+ * The mc13783 has two SSI ports, both of them can be routed either
+ * to the voice codec or the stereo DAC. When two different SSI ports
+ * are used for the voice codec and the stereo DAC we can do different
+ * formats and sysclock settings for playback and capture
+ * (mc13783-hifi-playback and mc13783-hifi-capture). Using the same port
+ * forces us to use symmetric rates (mc13783-hifi).
+ */
+static struct snd_soc_dai_driver mc13783_dai_async[] = {
+	{
+		.name = "mc13783-hifi-playback",
+		.id = MC13783_ID_STEREO_DAC,
+		.playback = {
+			.stream_name = "Playback",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_8000_96000,
+			.formats = MC13783_FORMATS,
+		},
+		.ops = &mc13783_ops_dac,
+	}, {
+		.name = "mc13783-hifi-capture",
+		.id = MC13783_ID_STEREO_CODEC,
+		.capture = {
+			.stream_name = "Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = MC13783_RATES_RECORD,
+			.formats = MC13783_FORMATS,
+		},
+		.ops = &mc13783_ops_codec,
+	},
+};
+
+static struct snd_soc_dai_ops mc13783_ops_sync = {
+	.hw_params	= mc13783_pcm_hw_params_sync,
+	.set_fmt	= mc13783_set_fmt_sync,
+	.set_sysclk	= mc13783_set_sysclk_sync,
+	.set_tdm_slot	= mc13783_set_tdm_slot_sync,
+	.prepare	= mc13783_startup_sync,
+	.shutdown	= mc13783_shutdown_sync,
+};
+
+static struct snd_soc_dai_driver mc13783_dai_sync[] = {
+	{
+		.name = "mc13783-hifi",
+		.id = MC13783_ID_SYNC,
+		.playback = {
+			.stream_name = "Playback",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = SNDRV_PCM_RATE_8000_96000,
+			.formats = MC13783_FORMATS,
+		},
+		.capture = {
+			.stream_name = "Capture",
+			.channels_min = 1,
+			.channels_max = 2,
+			.rates = MC13783_RATES_RECORD,
+			.formats = MC13783_FORMATS,
+		},
+		.ops = &mc13783_ops_sync,
+		.symmetric_rates = 1,
+	}
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_mc13783 = {
+	.probe		= mc13783_probe,
+	.remove		= mc13783_remove,
+	.read		= mc13783_read,
+	.write		= mc13783_write,
+};
+
+static int mc13783_codec_probe(struct platform_device *pdev)
+{
+	struct mc13xxx *mc13xxx;
+	struct mc13783_priv *priv;
+	struct mc13xxx_codec_platform_data *pdata = pdev->dev.platform_data;
+	int ret;
+
+	mc13xxx = dev_get_drvdata(pdev->dev.parent);
+
+	priv = kzalloc(sizeof(struct mc13783_priv), GFP_KERNEL);
+	if (priv == NULL)
+		return -ENOMEM;
+
+	dev_set_drvdata(&pdev->dev, priv);
+	priv->mc13xxx = mc13xxx;
+	if (pdata) {
+		priv->adc_ssi_port = pdata->adc_ssi_port;
+		priv->dac_ssi_port = pdata->dac_ssi_port;
+	} else {
+		priv->adc_ssi_port = MC13783_SSI1_PORT;
+		priv->dac_ssi_port = MC13783_SSI2_PORT;
+	}
+
+	if (priv->adc_ssi_port == priv->dac_ssi_port)
+		ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_mc13783,
+					mc13783_dai_sync, ARRAY_SIZE(mc13783_dai_sync));
+	else
+		ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_mc13783,
+					mc13783_dai_async, ARRAY_SIZE(mc13783_dai_async));
+
+	if (ret)
+		goto err_register_codec;
+
+	return 0;
+
+err_register_codec:
+	dev_err(&pdev->dev, "register codec failed with %d\n", ret);
+	kfree(priv);
+
+	return ret;
+}
+
+static int mc13783_codec_remove(struct platform_device *pdev)
+{
+	snd_soc_unregister_codec(&pdev->dev);
+
+	return 0;
+}
+
+static struct platform_driver mc13783_codec_driver = {
+	.driver = {
+		   .name = "mc13783-codec",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = mc13783_codec_probe,
+	.remove = __devexit_p(mc13783_codec_remove),
+};
+
+static __init int mc13783_init(void)
+{
+	return platform_driver_register(&mc13783_codec_driver);
+}
+
+static __exit void mc13783_exit(void)
+{
+	platform_driver_unregister(&mc13783_codec_driver);
+}
+
+module_init(mc13783_init);
+module_exit(mc13783_exit);
+
+MODULE_DESCRIPTION("ASoC MC13783 driver");
+MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/mc13783.h b/sound/soc/codecs/mc13783.h
new file mode 100644
index 0000000..ae37e99
--- /dev/null
+++ b/sound/soc/codecs/mc13783.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2008 Juergen Beisert, kernel at pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef MC13783_MIXER_H
+#define MC13783_MIXER_H
+
+extern int mc13783_add_ctl(struct snd_card*, void *);
+
+#define MC13783_CLK_CLIA	1
+#define MC13783_CLK_CLIB	2
+
+#define MC13783_ID_STEREO_DAC	1
+#define MC13783_ID_STEREO_CODEC	2
+#define MC13783_ID_SYNC		3
+
+#endif /* MC13783_MIXER_H */
-- 
1.6.3.3



From sfr at canb.auug.org.au  Fri Mar  9 02:09:48 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 9 Mar 2012 18:09:48 +1100
Subject: linux-next: manual merge of the arm-soc tree with the omap_dss2 tree
Message-ID: <20120309180948.a75b0a5378de34443c32963d@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-omap1/board-palmz71.c between commit ddba6c7f7ec6 ("OMAP1:
pass LCD config with omapfb_set_lcd_config()") from the omap_dss2 tree
and commit 2e3ee9f45b3c ("ARM: OMAP1: Move most of plat/io.h into local
iomap.h") from the arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-omap1/board-palmz71.c
index 9924c70,c1cd0f2..0000000
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@@ -27,9 -27,9 +27,10 @@@
  #include <linux/mtd/mtd.h>
  #include <linux/mtd/partitions.h>
  #include <linux/mtd/physmap.h>
 +#include <linux/omapfb.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/ads7846.h>
  
- #include <mach/hardware.h>
  #include <asm/mach-types.h>
  #include <asm/mach/arch.h>
  #include <asm/mach/map.h>
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From andrew at lunn.ch  Sat Mar 10 12:51:13 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sat, 10 Mar 2012 18:51:13 +0100
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <1331366064-1273-3-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
Message-ID: <20120310175113.GK16608@lunn.ch>

On Fri, Mar 09, 2012 at 11:54:23PM -0800, Mike Turquette wrote:
> The common clock framework defines a common struct clk useful across
> most platforms as well as an implementation of the clk api that drivers
> can use safely for managing clocks.

Hi Mike

Please feel free to add:

Tested-by: Andrew Lunn <andrew at lunn.ch>

	   Andrew


From mturquette at ti.com  Fri Mar  9 18:38:39 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 9 Mar 2012 15:38:39 -0800
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <20120305101708.GF24858@lunn.ch>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
 <20120304174229.GD11546@lunn.ch>
 <CAJOA=zNWN6L+-YEkNKoQnjnrrswNpCBmtnhKBm04HekWP46i5w@mail.gmail.com>
 <20120305084823.GD24858@lunn.ch> <20120305092948.GV3852@pengutronix.de>
 <20120305101708.GF24858@lunn.ch>
Message-ID: <CAJOA=zNS+s+b1_KvBeur0KxnBkUbXeu0Pyj9n877dvUQF22VPw@mail.gmail.com>

On Mon, Mar 5, 2012 at 2:17 AM, Andrew Lunn <andrew at lunn.ch> wrote:
>> > I think i can wrap your simple gate clock, to make my "complex" gate
>> > clock. What would help is if you would EXPORT_SYMBOL_GPL
>> > clk_gate_enable() and clk_gate_disable(), since they do exactly what i
>> > want. I can then build my own clk_ops structure, with my own
>> > unprepare() function. I would probably use DEFINE_CLK_GATE as is, and
>> > then at run time, before calling __clk_init() overwrite the .ops with
>> > my own version.
>>
>> Maybe I don't get your point, but clk_unprepare should be used when
>> you have to sleep to disable your clock. When clk_gate_disable() is
>> exactly why do you want to use clk_unprepare instead of clk_disable?
>
> I'm trying to avoid having to implement a new clock provider. The
> whole point of the generic clk code is to consolidate code. It seems
> silly to create a new clk provider which is 95% identical to Mike's
> gated provider, if i can avoid it.

I will export the operations in my next patchset, but I'm concerned
over how useful this might be...

Using your example of struct clk_gate, both clk_gate_enable and
clk_gate_disable call to_clk_gate.  So you would either have to re-use
struct clk_gate for your own needs (which involves hacking up a
specific struct clk_gate_foo_ops for your needs) or you could not use
struct clk_gate and pack your data identically (struct clk_hw must be
the first member) which is too horrible to imagine.

Hmm, or you could re-use struct clk_gate but provide your own struct
clk_ops AND your own registration functions (since you won't be able
to pass in the ops to your clk_register_gate).  So that sounds sane,
if a bit convoluted.  It does re-use code though...

Regards,
Mike

>
> If i stuff it into clk_disable(), it means i cannot use the basic gate
> clock Mike provides in the generic clock framework. Which is a shame,
> since it does exactly what i want in terms of gating the clock.
>
> If i can use unprepare(), which basic gate does not use, i can use
> Mikes code, and just extend it. It is there, it is unused, so why not
> use it?
>
> ? ?Andrew


From robherring2 at gmail.com  Fri Mar  9 08:59:17 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 09 Mar 2012 07:59:17 -0600
Subject: [PATCH 2/5 v3] ARM: at91: sam9g20 add i2c DT support
In-Reply-To: <20120309095336.GK27213@game.jcrosoft.org>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <1331196635-27203-2-git-send-email-plagnioj@jcrosoft.com>
 <4F58E77B.4010500@gmail.com> <20120309095336.GK27213@game.jcrosoft.org>
Message-ID: <4F5A0CB5.2020203@gmail.com>

On 03/09/2012 03:53 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 11:08 Thu 08 Mar     , Rob Herring wrote:
>> On 03/08/2012 02:50 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> For now on use i2c-gpio driver on the same pin as the hardware IP.
>>>
>>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>>> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
>>> Cc: devicetree-discuss at lists.ozlabs.org
>>> ---
>>> v3:
>>>
>>> 	update i2c binding (Rob comments)
>>>
>>> Best Regards,
>>> J.
>>>  arch/arm/boot/dts/at91sam9g20.dtsi |   13 +++++++++++++
>>>  1 files changed, 13 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
>>> index 4b0dc99..072b2da 100644
>>> --- a/arch/arm/boot/dts/at91sam9g20.dtsi
>>> +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
>>> @@ -189,4 +189,17 @@
>>>  			status = "disabled";
>>>  		};
>>>  	};
>>> +> > +	i2c-gpio at 0 {
>>
>> You updated the example, but not all the actual uses to i2c at 0.
> on purpose as on some soc we will have HW and soft binding
> 
> on the board you put the alias
> 

I'm not sure I follow.

If you use the h/w block, then you would have i2c@<addr> while for gpio
it's basically an index.

Also, I don't think you need an alias for i2c. You should not care about
bus numbering as devices should be sub nodes.

Rob

> Best Regards,
> J.
>>
>> Rob
>>
>>> +		compatible = "i2c-gpio";
>>> +		gpios = <&pioA 23 0 /* sda */
>>> +			 &pioA 24 0 /* scl */
>>> +			>;
>>> +		i2c-gpio,sda-open-drain;
>>> +		i2c-gpio,scl-open-drain;
>>> +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +		status = "disabled";
>>> +	};
>>>  };
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From peppe.cavallaro at st.com  Mon Mar 12 12:46:16 2012
From: peppe.cavallaro at st.com (Giuseppe CAVALLARO)
Date: Mon, 12 Mar 2012 17:46:16 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <201203121723.38411.sr@denx.de>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <201203121606.26926.sr@denx.de> <4F5E169D.3070508@st.com>
 <201203121723.38411.sr@denx.de>
Message-ID: <4F5E2858.4000708@st.com>

On 3/12/2012 5:23 PM, Stefan Roese wrote:
> On Monday 12 March 2012 16:30:37 Giuseppe CAVALLARO wrote:
>>>>> +Required properties:
>>>>> +- compatible: Should be "stm,gmac"
>>>>
>>>> This is too generic. This should be 1 string per version of h/w.
>>>
>>> Viresh, Giuseppe, can you please suggest a proper string for the SPEAr600
>>> STMMAC core, including version?
>>>
>>>> 'stm' should be 'st' according to vendor-prefixes.txt.
>>
>> I'm not familiar with devicetree; maybe we should have:
>>
>> "stmicro,mac100"
>> "stmicro,gmac"
>>
>> or: st instead of stmicro if you prefer.
>>
>> in fact, stmmac is for mac100 and gmac devices.
> 
> How about "st,spear600-gmac" for SPEAr600 then?

IIUC, as final result we should have something like this... that sounds
quite good to me.

ST/ARM SPEAr
"st,spear600-gmac"
"st,spear1310-gmac"
  ...

ST/SH

"st,stx7108-gmac"
"st,stx7106-gmac"
"st,stx7109-mac"    ->>> mac10/100
...

MIPS
"st,Loongson1B"

>  
>>> Okay.
>>>
>>>>> +- reg: Address and length of the register set for the device
>>>>> +- interrupt-parent: Should be the phandle for the interrupt controller
>>>>> +  that services interrupts for this device
>>>>> +- interrupts: Should contain the STMMAC interrupts
>>>>> +- interrupt-names: Should contain the interrupt names "macirq"
>>>>> +  "eth_wake_irq" if this interrupt is supported in the "interrupts"
>>>>> +  property
>>>>
>>>> You should be able to tell this from the compatible string and number of
>>>> interrupts.
>>>
>>> Yes. Currently the driver uses platform_get_irq_byname() to register the
>>> irq's. That's why I added these properties. Is there something wrong with
>>> using it this way?
>>>
>>>>> +- phy-mode: String, operation mode of the PHY interface.
>>>>> +  Supported values are: "mii", "rmii", "gmii", "rgmii".
>>>>> +- phy-addr: MDIO address of the PHY
>>>>
>>>> This is normally probed or the mdio bus is a sub-node of the MAC node.
>>>> See arch/powerpc/boot/dts/mpc8377_mds.dts for an example.
>>>
>>> Okay, I'll rework this.
>>>
>>>>> +
>>>>> +Optional properties:
>>>>> +- stm,prog-burst-len: Specify the burst length
>>>>> +- stm,has-gmac: Indicates that the controller supports 1000Mbps
>>>>> +- stm,has-pmt: Indicates that the controller supports power management
>>>>
>>>> I think these should all be encoded by the compatible string.
>>
>> and should we have all the other flags e.g. tx_coe etc?
>> (see stmmac.txt)
> 
> As Rob suggested, some of these flags/parameters are implicitly defined by the 
> compatible string. If this is not the case, then sure, those flags/parameters 
> need to be provided via the device-tree as well. I just don't need "tx_coe" 
> etc. for my platform (SPEAr600) as far as I know. I suggest to add support for 
> them once they are really needed/used by other platforms.

Ok, but on SPEAr indeed some of these are not used at all.
If you agree, we can go head with these and then we will add new ones
next time. In the meantime, I will try to be more familiar with
devicetree and provide further patches

peppe

> 
> Thanks,
> Stefan
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 



From festevam at gmail.com  Fri Mar  9 16:00:46 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 9 Mar 2012 18:00:46 -0300
Subject: [PATCH v2] ARM : mx35: 3ds-board: add framebuffer device
In-Reply-To: <1320381217-28711-1-git-send-email-b39297@freescale.com>
References: <1320381217-28711-1-git-send-email-b39297@freescale.com>
Message-ID: <CAOMZO5AvJ1SxOBkHom97MeNOktodj=si3moq+VJB_FaHXwpHOQ@mail.gmail.com>

On Fri, Nov 4, 2011 at 2:33 AM, wu guoxing <b39297 at freescale.com> wrote:

> +static int mc9s08dz60_lcd_gpio_get(void)
> +{
> + ? ? ? int ret;
> + ? ? ? struct gpio_chip *chip;
> + ? ? ? chip = gpiochip_find(
> + ? ? ? ? ? ? ? ? ? ? ? "mc9s08dz60", mc9s08dz60_gpiochip_match);
> + ? ? ? if (chip)
> + ? ? ? ? ? ? ? ret = chip->base + 6;

Please add a define to replace this magic "6".

The extra defines would be also useful for people that want to access
the other GPIOs from mc9s08dz60.

Regards,

Fabio Estevam


From mad_soft at inbox.ru  Mon Mar 12 15:30:21 2012
From: mad_soft at inbox.ru (Dmitry Artamonow)
Date: Mon, 12 Mar 2012 23:30:21 +0400
Subject: [PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection
 loop
In-Reply-To: <4F5E3BE7.4080207@wwwdotorg.org>
References: <20120306201538.GA14350@rainbow>
 <1331287760-10546-1-git-send-email-mad_soft@inbox.ru>
 <4F5E3BE7.4080207@wwwdotorg.org>
Message-ID: <20120312193020.GA1584@rainbow>

On 12:09 Mon 12 Mar     , Stephen Warren wrote:
> Thierry pointed out that one of NVIDIA's downstream kernels uses a
> timeout of 300 here, rather than 2000 above. Do you see a specific need
> for this timeout for be 2000 rather than 300? It might be nice to be
> consistent.
No, there's no specific need for it to be 2000 - it may as well be 300.
I just wanted to stay on the safe side, but I think 300 should be still
more than enough time for PLL to lock.

> 
> Olof, I notice you've already applied V1 of this, which has the return
> statement issue. Can you replace it with this, or should Dmitry send an
> incremental patch?

Yes, V1 breaks more things than it fixes, so it would be nice if
it can be replaced with fixed version (I hope it's not too late yet).
BTW, regarding timeout discussion above - should I resend patch with
adjusted timeout, or can you change it while applying? (of course,
if we settle on incremental patch, I'll roll this change in)

-- 
Best regards,
Dmitry "MAD" Artamonow



From mturquette at ti.com  Fri Mar  9 13:18:58 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 9 Mar 2012 10:18:58 -0800
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120308062739.GE18513@lunn.ch>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
 <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
 <20120308062739.GE18513@lunn.ch>
Message-ID: <CAJOA=zOV769hz8Bam7TvdXN5AYep66h8H596nK1ETkNAMJBsvQ@mail.gmail.com>

On Wed, Mar 7, 2012 at 10:27 PM, Andrew Lunn <andrew at lunn.ch> wrote:
>> Assuming that some day OMAP code can be refactored to allow for lazy
>> (or at least initcall-based) registration of clocks then perhaps your
>> suggestion can take root. ?Which leads me to this question: are there
>> any other platforms out there that require the level of expose to
>> struct clk present in this patchset? ?OMAP does, for now, but if that
>> changes then I need to know if others require this as well.
>
> Hi Mike
>
> For kirkwood, i use static clk's for all but my root clock. I cannot
> statically know the rate of the root clock, so i have to determine it
> at boot time using heuristics, PCI ID, etc.
>
> I used statics thinking it would be less code. No idea if it actually
> is, and there is nothing stopping me moving to creating the clocks
> after creating the root clock.
>
> One comment i have about the current static clks. I completely missing
> you need to call __clk_init() on them and so ended up with lots of
> division by zero errors, since they did not have a parent, and so the
> code seemed not be to able to determine the rate.
>
> So
>
> 1) Please add __clk_init() to the documentation in the section about
> ? static clocks.

Done.

>
> 2) Should maybe the name change? It seems strange having to call a
> ? __X() function. If this is a function which is supposed to be used,
> ? drop the __. Maybe clk_static_register()?

That function is used internally by clk_register and is only exposed
by clk-private.h, so I think the naming scheme is sane.  I basically
want to create a sense of worry in anyone using clk-private.h :-)

>
> 3) Maybe, if the parent is missing, clk_get_rate() should return an
> ? error?

Non-root, non-fixed-rate, orphan clocks can return an error in this
case.  Will update for V6.  Any idea on best -EERROR?  I'm thinking
ENODEV, but ECHILD and EPIPE are kinda funny in this context.

Regards,
Mike

>
> Andrew


From robherring2 at gmail.com  Sun Mar 11 17:08:18 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sun, 11 Mar 2012 16:08:18 -0500
Subject: [PATCH 2/4] ARM: iop13xx: fix missing declaration of
 iop13xx_init_early
In-Reply-To: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331500100-31351-3-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Commit 1dfe34ae794c13 (ARM: iop13xx: use runtime ioremap hook) missed
a declaration of iop13xx_init_early resulting in a build error.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/mach-iop13xx/include/mach/iop13xx.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index 07e9ff7..e190dcd 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -5,6 +5,7 @@
 /* The ATU offsets can change based on the strapping */
 extern u32 iop13xx_atux_pmmr_offset;
 extern u32 iop13xx_atue_pmmr_offset;
+void iop13xx_init_early(void);
 void iop13xx_init_irq(void);
 void iop13xx_map_io(void);
 void iop13xx_platform_init(void);
-- 
1.7.5.4



From santosh.shilimkar at ti.com  Mon Mar 12 11:33:08 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Mon, 12 Mar 2012 21:03:08 +0530
Subject: [PATCH] ARM: OMAP4: Workaround the OCP synchronisation issue with 32K
 synctimer.
Message-ID: <1331566388-2397-1-git-send-email-santosh.shilimkar@ti.com>

On OMAP4, recently a synchronisation bug is discovered by hardware
team, which leads to incorrect timer value read from 32K sync timer
IP when the IP is comming out of idle.

The issue is due to the synchronization methodology used in the SYNCTIMER IP.
The value of the counter register in 32kHz domain is synchronized to the OCP
domain register only at count up event, and if the OCP clock is switched off,
the OCP register gets out of synch until the first count up event after the
clock is switched back -at the next falling edge of the 32kHz clock.

Further investigation revealed that it applies to gptimer1 and watchdog timer2
as well which may run on 32KHz. This patch fixes the issue for all the
applicable modules.

The BUG has not made it yet to the OMAP errata list and it is applicable to
OMAP1/2/3/4/5. OMAP1/2/3 it is taken care indirectly by autodeps.

Reported-Tested-by: dave.long at linaro.org
[dave.long at linaro.org: Reported the oprofile time stamp issue with synctimer
and helped to test this patch]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/pm44xx.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index c264ef7..974f7ea 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -196,7 +196,7 @@ static void omap_default_idle(void)
 static int __init omap4_pm_init(void)
 {
 	int ret;
-	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
+	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
 	struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
 
 	if (!cpu_is_omap44xx())
@@ -220,14 +220,19 @@ static int __init omap4_pm_init(void)
 	 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
 	 * expected. The hardware recommendation is to enable static
 	 * dependencies for these to avoid system lock ups or random crashes.
+	 * The L4 wakeup depedency is added to workaround the OCP sync hardware
+	 * BUG with 32K synctimer which lead to incorrect timer value read
+	 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
+	 * are part of L4 wakeup clockdomain.
 	 */
 	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
 	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
 	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
 	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
 	l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
+	l4wkup = clkdm_lookup("l4_wkup_clkdm");
 	ducati_clkdm = clkdm_lookup("ducati_clkdm");
-	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
+	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) ||
 		(!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
 		goto err2;
 
@@ -235,6 +240,7 @@ static int __init omap4_pm_init(void)
 	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
 	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
 	ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
+	ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup);
 	ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
 	ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
 	if (ret) {
-- 
1.7.4.1



From kumarrav at codeaurora.org  Mon Mar 12 06:30:59 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Mon, 12 Mar 2012 16:00:59 +0530
Subject: [PATCH v3 0/2] Add Qualcomm MSM ADM DMAEngine driver
Message-ID: <1331548259-26865-1-git-send-email-kumarrav@codeaurora.org>

Following are the changes we have done from the previous
v1 posted here: https://lkml.org/lkml/2011/12/22/148 

As our ADM Scatter-gather hardware needs
-32-bit command configuration parameter
 apart from 
-32-bit source address
-32-bit destination address
-16-bit length

So,we have added new parameter in struct scatterlist to support xfer descriptor
specific private data, and for supporting ADM Box mode DMA we added new
API and data structure.

Changes done from v2:

As per our previous discussion you had suggested us to follow the below patch
https://lkml.org/lkml/2012/1/26/405
Please check the below link of our discussion
https://lkml.org/lkml/2012/1/30/48
 
So we have added the new context parameter in device_prep_dma_sg and 
device_prep_interleave_dma API's to support for passing client channel specific
private data associated with every transfer descriptor. 

We are using 
Interleaved API for BOX type transfer.
SG API for SG type transfer.
 
Ravi Kumar V (2):
  dmaengine: Add support for per xfer specific privatedata
  DMAEngine: Add DMAEngine driver based on old MSM DMA APIs

 arch/arm/mach-msm/include/mach/dma.h |   30 ++
 drivers/dma/Kconfig                  |   12 +
 drivers/dma/Makefile                 |    1 +
 drivers/dma/msm-dma.c                |  724 ++++++++++++++++++++++++++++++++++
 include/linux/dmaengine.h            |    4 +-
 5 files changed, 769 insertions(+), 2 deletions(-)
 create mode 100644 drivers/dma/msm-dma.c

-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From andrew at lunn.ch  Fri Mar  9 02:57:20 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Fri, 9 Mar 2012 08:57:20 +0100
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120308232549.GU3852@pengutronix.de>
References: <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
 <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
 <20120308062739.GE18513@lunn.ch>
 <20120308232549.GU3852@pengutronix.de>
Message-ID: <20120309075720.GC16608@lunn.ch>

> I'd say use the nonstatic ones. I think using the static initializers
> will cause us much pain in the future. I've been through several rebases
> on the i.MX clock rework and everytime I wish my sed foo would be
> better. Now imagine what happens when it turns out that the internal
> struct clk layout or the structs for the muxes/dividers/gates have to
> be changed.

/*****************************************************************************
 * CLK tree
 ****************************************************************************/
static DEFINE_SPINLOCK(gating_lock);

#define DEFINE_KIRKWOOD_CLK_GATE(_name, _bit)                           \
        DEFINE_CLK_GATE(_name, "tclk", NULL, 0,                         \
                        (void __iomem *)CLOCK_GATING_CTRL,              \
                        _bit, 0, &gating_lock)

DEFINE_KIRKWOOD_CLK_GATE(clk_ge0,    CGC_BIT_GE0);
DEFINE_KIRKWOOD_CLK_GATE(clk_pex0,   CGC_BIT_PEX0);
DEFINE_KIRKWOOD_CLK_GATE(clk_usb0,   CGC_BIT_USB0);
DEFINE_KIRKWOOD_CLK_GATE(clk_sdio,   CGC_BIT_SDIO);
DEFINE_KIRKWOOD_CLK_GATE(clk_tsu,    CGC_BIT_TSU);
DEFINE_KIRKWOOD_CLK_GATE(clk_dunit,  CGC_BIT_DUNIT);
DEFINE_KIRKWOOD_CLK_GATE(clk_runit,  CGC_BIT_RUNIT);

I've so far not had any problems, and not needed an sed foo.  I do
only have a dozen or so clocks, which helps. But even so, all the real
pain is hidden inside DEFINE_CLK_GATE() which Mike maintains.

I guess the problem comes when you are not using the basic clk
providers, but your own provider. What might help is if
linux/clk-provider.h could provide some macros to do most of the
generic definitions. Something like:

#define DEFINE_CLK_GENERIC(_name, _flags, _ops)                 \
        static struct clk _name;                                \
        static char *_name##_parent_names[] = {};               \
        static struct clk _name = {                             \
                .name = #_name,                                 \
                .ops = &_ops,                                   \
                .hw = &_name##_hw.hw,                           \
                .parent_names = _name##_parent_names,           \
                .num_parents =                                  \
                        ARRAY_SIZE(_name##_parent_names),       \
                .flags = _flags,                                \
        };

and then you have something like

#define DEFINE_CLK_IMX(_name, _flags, _foo, _bar)               \
        static struct clk_imx _name##_hw = {                    \
                .hw = {                                         \
                        .clk = &_name,                          \
                },                                              \
                .foo = _foo,                                    \
                .bar = _bar,                                    \
        };                                                      \
	DEFINE_CLK_GENERIC(_name, _flags, clk_imx_ops)           

	Andrew


From s.hauer at pengutronix.de  Fri Mar  9 11:09:22 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 9 Mar 2012 17:09:22 +0100
Subject: [RFC] i.MX: drop secondary clocks
In-Reply-To: <20314.5967.278184.187691@ipc1.ka-ro>
References: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
 <20313.52782.832292.580932@ipc1.ka-ro>
 <20120309102931.GY3852@pengutronix.de>
 <20313.60910.420339.905973@ipc1.ka-ro>
 <20120309142205.GF3852@pengutronix.de>
 <20314.5967.278184.187691@ipc1.ka-ro>
Message-ID: <20120309160922.GG3852@pengutronix.de>

On Fri, Mar 09, 2012 at 03:44:31PM +0100, Lothar Wa?mann wrote:
> Hi,
> 
> Sascha Hauer writes:
> > On Fri, Mar 09, 2012 at 12:47:58PM +0100, Lothar Wa?mann wrote:
> > > Hi,
> > > 
> > > Sascha Hauer writes:
> > > > On Fri, Mar 09, 2012 at 10:32:30AM +0100, Lothar Wa?mann wrote:
> > > > > Hi,
> > > > > 
> > > > > Sascha Hauer writes:
> > > > > > Hi All,
> > > > > > 
> > > [...]
> > > > > I think that's a bad idea! Drivers should not have to know intimate
> > > > > details about the clock logic of the CPU core they are running on!
> > > > 
> > > > They don't have to. There really are different clocks connected to the
> > > > devices. If for example you have a look eSDHC Block diagram in the
> > > > reference Manual  you'll see that this has three clock inputs. All
> > > > we do is to tell the driver about these three clocks which are device
> > > > specific and not SoC specific. Which of these clocks are actually
> > > > gatetable varies from SoC to SoC. Also on some SoCs two of the three
> > > > clocks may be actually the same.
> > > > 
> > > At least this should be done in a way that is independent from the
> > > name of the clock on a specific SoC, but is related to the function of
> > > the clock for the driver. Thus instead of e.g. CLK_IPG and CLK_PER use
> > > CLK_REG and CLK_BITRATE.
> > 
> > 'per', 'ipg' and 'ahb' seems to be a common pattern with all i.MXs. Only
> > ahb is sometimes refered to as hclk. Do you also have a name for
> > ahb/hclk? I don't insist on specific names, in the end they are just
> > names and the pattern I used at least seems mostly consistent.
> > 
> CLK_BUS?
> 
> > I assume that any given device has a set of clocks as inputs which
> > should get device specific names. It's the job of the clock tree
> > to know which SoC clocks map to which device clocks. If now a newer
> > UART block has an additional clock, then we would depending on the
> > device id (fsl,imx7-uart) know that it requires the additional clock
> > and request it.
> > 
> It's also not the business of a device driver to know any details
> about clock dependencies on a specific SoC.
> We probably really need a bus layer that can hide the details of the
> bus architecture and their corresponding clocks from the device
> drivers.

I agree there's room for improvements, but I don't want to make that a
dependency for the generic clock support.

Does anyone know which clocks are really worth to be turned off for
powermanement? I have no idea whether we really save power when we for
example turn off aips_tz1_clk.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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From hunold at linuxtv.org  Mon Mar 12 10:17:02 2012
From: hunold at linuxtv.org (Michael Hunold)
Date: Mon, 12 Mar 2012 15:17:02 +0100
Subject: iMX53 SATA performance
Message-ID: <4F5E055E.9050202@linuxtv.org>

Hi,

I have tried to benchmark the performance of the SATA link on the iMX53
Quick Start Board.

I have used a TOSHIBA THNSNB030GBSJ SSD which reads about 190MB/s and
writes about 55MB/s on my host PC using "dd" and using /dev/zero as the
data source or sink.

On the iMX53 Quick Start Board both reading and writing using the same
options with "dd" is limited to about 40MB/s.

During a read test, "vmstat" shows the following:
[...]
 1  1      0 837464 185472   3192    0    0 43136     0  369  684  0 28
 0 72
 1  0      0 793320 228864   3192    0    0 43392     0  363  684  0 23
 0 77
 1  1      0 749672 272128   3192    0    0 43264     0  371  687  0 28
 0 72
 1  1      0 705900 315264   3192    0    0 43136     0  367  680  1 28
 0 71
 1  1      0 662128 358400   3192    0    0 43136     0  368  685  1 25
 0 74
[...]

"top" shows:
Cpu(s):  0.6%us, 25.1%sy,  0.0%ni,  0.0%id, 73.7%wa,  0.0%hi,  0.6%si,
0.0%st

"hdparm -t /dev/sda" says "/dev/sda: Timing buffered disk reads:  127 MB
in 3.00 seconds = 43246 kB/s"

The device is detected as follows:
[    0.550659] ata1: SATA max UDMA/133 mmio [mem 0x10000000-0x10000fff]
port 0x100 irq 28
[    0.904998] ata1: SATA link down (SStatus 0 SControl 300)
[...]
[   27.114990] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[   27.121378] ata1.00: ATA-8: TOSHIBA THNSNB030GBSJ, AJRA0201, max UDMA/100
[   27.128207] ata1.00: 58626288 sectors, multi 16: LBA48
[   27.133800] ata1.00: configured for UDMA/100
[   27.138109] ata1: EH complete
[   27.141726] scsi 0:0:0:0: Direct-Access     ATA      TOSHIBA THNSNB03
AJRA PQ: 0 ANSI: 5

The output of "vmstat" suggests that really only about 43k 1kB blocks
are travelling via the controller and the output of "top" suggests that
the CPU is really waiting for the I/O.

Does this sound like a reasonable performance for the SATA link of the
iMX53 Quick Start Board?

Of course I was hoping for a little bit more.

CU
Michael.


From mgherzan at gmail.com  Sun Mar 11 18:30:54 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Sun, 11 Mar 2012 23:30:54 +0100
Subject: [PATCH v2] ARM: OMAP: WiLink platform data for the PandaBoard
In-Reply-To: <CAHd==dp1GNov4gqMzPLkJzX1A205HUMhTPtg28399FcPQFZH0A@mail.gmail.com>
References: <1331074504-22683-1-git-send-email-mgherzan@gmail.com>
 <20120309183150.GH12083@atomide.com> <4F5D057A.3080601@gmail.com>
 <CAHd==dp1GNov4gqMzPLkJzX1A205HUMhTPtg28399FcPQFZH0A@mail.gmail.com>
Message-ID: <4F5D279E.9010800@gmail.com>

Am 11.03.2012 21:13, schrieb Pavan Savoy:
> On Sun, Mar 11, 2012 at 2:05 PM, Mircea Gherzan <mgherzan at gmail.com> wrote:
>> Am 09.03.2012 19:31, schrieb Tony Lindgren:
>>> Hi Luca,
>>>
>>> * Mircea Gherzan <mgherzan at gmail.com> [120306 14:23]:
>>>> The "uim" deamon requires sysfs entries that are filled in using
>>>> this platform data.
>>>>
>>>> Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
>>>> ---
>>>>  arch/arm/mach-omap2/board-omap4panda.c |   14 ++++++++++++--
>>>>  include/linux/ti_wilink_st.h           |    2 ++
>>>>  2 files changed, 14 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
>>>> index b1d74d6..339e781 100644
>>>> --- a/arch/arm/mach-omap2/board-omap4panda.c
>>>> +++ b/arch/arm/mach-omap2/board-omap4panda.c
>>>> @@ -27,6 +27,7 @@
>>>>  #include <linux/i2c/twl.h>
>>>>  #include <linux/regulator/machine.h>
>>>>  #include <linux/regulator/fixed.h>
>>>> +#include <linux/ti_wilink_st.h>
>>>>  #include <linux/wl12xx.h>
>>>>
>>>>  #include <mach/hardware.h>
>>>> @@ -56,12 +57,21 @@
>>>>  #define HDMI_GPIO_HPD  63 /* Hotplug detect */
>>>>
>>>>  /* wl127x BT, FM, GPS connectivity chip */
>>>> -static int wl1271_gpios[] = {46, -1, -1};
>>>> +static struct ti_st_plat_data wilink_platform_data = {
>>>> +    .nshutdown_gpio = 46,
>>>> +    .dev_name       = "/dev/ttyO1",
>>>> +    .flow_cntrl     = 1,
>>>> +    .baud_rate      = 3000000,
>>>> +    .chip_enable    = NULL,
>>>> +    .suspend        = NULL,
>>>> +    .resume         = NULL,
>>>> +};
>>>> +
>>>>  static struct platform_device wl1271_device = {
>>>>      .name   = "kim",
>>>>      .id     = -1,
>>>>      .dev    = {
>>>> -            .platform_data  = &wl1271_gpios,
>>>> +            .platform_data  = &wilink_platform_data,
>>>>      },
>>>>  };
>>>>
>>>> diff --git a/include/linux/ti_wilink_st.h b/include/linux/ti_wilink_st.h
>>>> index 2ef4385..3ca0269 100644
>>>> --- a/include/linux/ti_wilink_st.h
>>>> +++ b/include/linux/ti_wilink_st.h
>>>> @@ -25,6 +25,8 @@
>>>>  #ifndef TI_WILINK_ST_H
>>>>  #define TI_WILINK_ST_H
>>>>
>>>> +#include <linux/skbuff.h>
>>>> +
>>>>  /**
>>>>   * enum proto-type - The protocol on WiLink chips which share a
>>>>   *  common physical interface like UART.
>>>> --
>>>
>>> Just checking.. Can you please take a look at this patch
>>> and confirm that this is how things are supposed to be done?
>>>
>>> To me passing some third driver's dev_name in pdata seems
>>> pretty weird.. But then again maybe I just don't know how
>>> this is supposed to work.
>>
>> This is what the ti_st driver expects in the platform data structure.
>> More precisely, in kim_probe():
>>
>>        /* copying platform data */
>>        strncpy(kim_gdata->dev_name, pdata->dev_name,UART_DEV_NAME_LEN);
>>        kim_gdata->flow_cntrl = pdata->flow_cntrl;
>>        kim_gdata->baud_rate = pdata->baud_rate;
>>        pr_info("sysfs entries created\n");
>>
>> So IMHO the patch is a valid fix. However, one more patch [1] is still
>> required to get BT and WLAN working on the PandaBoard.
> 
> The patch looks alright to me.
> Yes, the UART to which BT chip is connected (along with other
> technologies for which shared transport is required), the baud rate
> which the UART supports & also a flag so as to check whether it
> supports flow control - ideally is supposed to come from boot-loader,
> device tree sort of configuration - if not can be hard-coded in the
> relevant platform specific files like in this case.
> 
> This is picked up from ST as platform data as is read from the
> user-space daemon, because unfortunately none of these configurations
> can be done in kernel (the right way for TTY).
> 
> 1 more patch or an addition to this patch to add the wl1271_device &
> the btwilink device is also required to get ST probe & BT probe.
> The btwilink driver is a platform device because UART devices don't
> have a probe mechanism unlike say usb, i2c..

This issue has been addressed in a previous patch [1].

[1] http://www.spinics.net/lists/linux-omap/msg65181.html


From thierry.reding at avionic-design.de  Fri Mar  9 02:53:47 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 9 Mar 2012 08:53:47 +0100
Subject: [PATCH 05/11] tps6586x: Add device-tree support
In-Reply-To: <20120309051506.761B63E090F@localhost>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-6-git-send-email-thierry.reding@avionic-design.de>
 <20120308150607.GP3638@opensource.wolfsonmicro.com>
 <20120308151545.GA23934@avionic-0098.mockup.avionic-design.de>
 <20120309051506.761B63E090F@localhost>
Message-ID: <20120309075347.GA27270@avionic-0098.mockup.avionic-design.de>

* Grant Likely wrote:
> On Thu, 8 Mar 2012 16:15:46 +0100, Thierry Reding <thierry.reding at avionic-design.de> wrote:
> > * Mark Brown wrote:
> > > ...they all seem to be explicitly named in the device tree so presumably
> > > there's enough information in there for the driver to pick any set of
> > > regulators in any order.  This would be much nicer to use.
> > 
> > I don't like it much either. The only reason that requirement exists is
> > because it makes the assignment of the regulator ID (as defined in the
> > include/linux/mfd/tps6586x.h header) very trivial. Would it be better to
> > look up the ID based on the node name (sm0 --> TPS6586X_ID_SM_0, ...)?
> > 
> > Then the only requirement would be that the names match.
> 
> Yes, please look up id via name.  Alternately you can give each child node
> a 'reg' property and put #address-cells = <1>; #size-cells = <0>; in the
> parent (assuming the regulator number is a documented attribute of the
> hardware and not just a convenient linux construct).

I'll go with the lookup via name then because as far as I can tell the
datasheet doesn't list any specific ordering of the regulators.

Thierry
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From viresh.kumar at st.com  Mon Mar 12 00:22:17 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:17 +0530
Subject: [PATCH V2 22/22] watchdog/sp805: Add clk_{un}prepare support
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <aadd8e1398e5a85fff68b3b501e32e1fe5c4c580.1331524811.git.viresh.kumar@st.com>

clk_{un}prepare() routines are required for required on some platforms to run
part of clk enable/disable() routines from contexts that can schedule.

This patch adds support for these routines in sp805 driver.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/sp805_wdt.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 5c34eda..938b8ab 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -130,9 +130,16 @@ static int wdt_config(struct watchdog_device *wdd, bool ping)
 	int ret;
 
 	if (!ping) {
+		ret = clk_prepare(wdt->clk);
+		if (ret) {
+			dev_err(&wdt->adev->dev, "clock prepare fail");
+			return ret;
+		}
+
 		ret = clk_enable(wdt->clk);
 		if (ret) {
 			dev_err(&wdt->adev->dev, "clock enable fail");
+			clk_unprepare(wdt->clk);
 			return ret;
 		}
 	}
@@ -184,6 +191,7 @@ static int wdt_disable(struct watchdog_device *wdd)
 	spin_unlock(&wdt->lock);
 
 	clk_disable(wdt->clk);
+	clk_unprepare(wdt->clk);
 
 	return 0;
 }
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:21:59 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:51:59 +0530
Subject: [PATCH V2 04/22] watchdog/mpcore_wdt: Use devm routines
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <549910322568234ac5843863c8ad9999cfd0a366.1331524811.git.viresh.kumar@st.com>

mpcore_wdt driver currently uses normal kzalloc, request_irq, ioremap, etc
routines. This patch replaces these routines with devm_kzalloc and
devm_request_mem_region etc, so that we don't need to handle freeing of
resources for error cases and module removal routine.

Also, request_irq is moved before registering misc device, so that we are ready
for irq as soon as device is registered.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   58 +++++++++++++---------------------------
 1 files changed, 19 insertions(+), 39 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index fd9f91b..63bd161 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -335,43 +335,37 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		return -ENODEV;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		ret = -ENODEV;
-		goto err_out;
-	}
+	if (!res)
+		return -ENODEV;
 
-	wdt = kzalloc(sizeof(struct mpcore_wdt), GFP_KERNEL);
-	if (!wdt) {
-		ret = -ENOMEM;
-		goto err_out;
-	}
+	wdt = devm_kzalloc(&pdev->dev, sizeof(struct mpcore_wdt), GFP_KERNEL);
+	if (!wdt)
+		return -ENOMEM;
 
 	wdt->dev = &pdev->dev;
 	wdt->irq = platform_get_irq(pdev, 0);
-	if (wdt->irq < 0) {
-		ret = -ENXIO;
-		goto err_free;
-	}
-	wdt->base = ioremap(res->start, resource_size(res));
-	if (!wdt->base) {
-		ret = -ENOMEM;
-		goto err_free;
+	if (wdt->irq < 0)
+		return -ENXIO;
+
+	ret = devm_request_irq(wdt->dev, wdt->irq, mpcore_wdt_fire, 0,
+			"mpcore_wdt", wdt);
+	if (ret) {
+		dev_printk(KERN_ERR, wdt->dev,
+			"cannot register IRQ%d for watchdog\n", wdt->irq);
+		return ret;
 	}
 
+	wdt->base = devm_ioremap(wdt->dev, res->start, resource_size(res));
+	if (!wdt->base)
+		return -ENOMEM;
+
 	mpcore_wdt_miscdev.parent = &pdev->dev;
 	ret = misc_register(&mpcore_wdt_miscdev);
 	if (ret) {
 		dev_printk(KERN_ERR, wdt->dev,
 			"cannot register miscdev on minor=%d (err=%d)\n",
 							WATCHDOG_MINOR, ret);
-		goto err_misc;
-	}
-
-	ret = request_irq(wdt->irq, mpcore_wdt_fire, 0, "mpcore_wdt", wdt);
-	if (ret) {
-		dev_printk(KERN_ERR, wdt->dev,
-			"cannot register IRQ%d for watchdog\n", wdt->irq);
-		goto err_irq;
+		return ret;
 	}
 
 	mpcore_wdt_stop(wdt);
@@ -379,30 +373,16 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 	mpcore_wdt_pdev = pdev;
 
 	return 0;
-
-err_irq:
-	misc_deregister(&mpcore_wdt_miscdev);
-err_misc:
-	iounmap(wdt->base);
-err_free:
-	kfree(wdt);
-err_out:
-	return ret;
 }
 
 static int __devexit mpcore_wdt_remove(struct platform_device *pdev)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(pdev);
-
 	platform_set_drvdata(pdev, NULL);
 
 	misc_deregister(&mpcore_wdt_miscdev);
 
 	mpcore_wdt_pdev = NULL;
 
-	free_irq(wdt->irq, wdt);
-	iounmap(wdt->base);
-	kfree(wdt);
 	return 0;
 }
 
-- 
1.7.8.110.g4cb5d



From heiko at sntech.de  Mon Mar 12 15:01:32 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Mon, 12 Mar 2012 20:01:32 +0100
Subject: [PATCH 3/6] ARM: S3C24XX: Add map entries needed by the s3c64xx-spi
 devices
In-Reply-To: <201203121959.32966.heiko@sntech.de>
References: <201203121959.32966.heiko@sntech.de>
Message-ID: <201203122001.33226.heiko@sntech.de>

The S3C_PA_SPIx constants are only used by the s3c64xx-spi driver
and don't conflict with the older SoCs as they don't support hsspi.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 arch/arm/mach-s3c24xx/include/mach/map.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h
index 78ae807..8ba381f 100644
--- a/arch/arm/mach-s3c24xx/include/mach/map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/map.h
@@ -98,6 +98,8 @@
 
 /* SPI */
 #define S3C2410_PA_SPI	   (0x59000000)
+#define S3C2443_PA_SPI0		(0x52000000)
+#define S3C2443_PA_SPI1		S3C2410_PA_SPI
 
 /* SDI */
 #define S3C2410_PA_SDI	   (0x5A000000)
@@ -162,4 +164,7 @@
 #define S3C_PA_WDT	    S3C2410_PA_WATCHDOG
 #define S3C_PA_NAND	    S3C24XX_PA_NAND
 
+#define S3C_PA_SPI0		S3C2443_PA_SPI0
+#define S3C_PA_SPI1		S3C2443_PA_SPI1
+
 #endif /* __ASM_ARCH_MAP_H */
-- 
1.7.2.3



From tomi.valkeinen at ti.com  Fri Mar  9 07:14:29 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 09 Mar 2012 14:14:29 +0200
Subject: linux-next: manual merge of the arm-soc tree with the
 omap_dss2 tree
In-Reply-To: <201203091150.11294.arnd@arndb.de>
References: <20120308170048.f1a992bca2ca2d93fa9747bf@canb.auug.org.au>
 <201203081616.12510.arnd@arndb.de> <1331285751.1927.20.camel@deskari>
 <201203091150.11294.arnd@arndb.de>
Message-ID: <1331295269.1927.54.camel@deskari>

On Fri, 2012-03-09 at 11:50 +0000, Arnd Bergmann wrote:
> On Friday 09 March 2012, Tomi Valkeinen wrote:
> > On Thu, 2012-03-08 at 16:16 +0000, Arnd Bergmann wrote:
> > > On Thursday 08 March 2012, Stephen Rothwell wrote:
> > > > Hi all,
> > > > 
> > > > Today's linux-next merge of the arm-soc tree got a conflict in
> > > > arch/arm/mach-omap1/board-palmtt.c between commit ddba6c7f7ec6 ("OMAP1:
> > > > pass LCD config with omapfb_set_lcd_config()") from the omap_dss2 tree
> > > > and commit 2e3ee9f45b3c ("ARM: OMAP1: Move most of plat/io.h into local
> > > > iomap.h") from the arm-soc tree.
> > > > 
> > > > I fixed it up (see below) and can carry the fix as necessary.
> > > 
> > > Hi Stephen,
> > > 
> > > Thanks for fixing up all the conflicts between arm-soc and omap_dss2.
> > > I think we should make sure they are resolved in one of the trees before
> > > the merge window.
> > 
> > Do we need to? The conflicts seemed to be trivial ones, like arm-soc
> > adds/removes something that just happens to be next to something else
> > that I add/remove.
> > 
> > My understanding is that it's better to leave those conflicts than to do
> > "trickery" to avoid them.
> 
> Each of the conflicts is simple enough, but I feel it's worth resolving
> them in this case because there are a number of them. Looking at them
> again now, it's probably ok either way -- resolving them now or letting
> Linus take care of them.

Florian, do you have an opinion about this?

Merging omapdss tree through arm-soc would make sense for avoiding
conflicts, because almost every merge window there are some conflicts as
I often need to edit arch/arm files also. But I'm not sure if we have
ever had a conflict in drivers/video.

But still, it's a video driver, and fbdev tree sounds more suited for a
video driver.

So I don't know =). Basically it's ok for me either way also. But it
would be nice to have a standard way of doing this, instead of, for
example, merging omapdss sometimes through fbdev, sometimes through
arm-soc, depending on the conflicts...

 Tomi

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From cjb at laptop.org  Fri Mar  9 00:08:58 2012
From: cjb at laptop.org (Chris Ball)
Date: Fri, 09 Mar 2012 00:08:58 -0500
Subject: [PATCH 2/2] mmc: sdhci-s3c: Enable runtime power management
In-Reply-To: <1330735602-22409-2-git-send-email-broonie@opensource.wolfsonmicro.com>
 (Mark Brown's message of "Sat, 3 Mar 2012 00:46:42 +0000")
References: <4F51697C.40408@samsung.com>
 <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1330735602-22409-2-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <m2vcmenyxh.fsf@bob.laptop.org>

Hi,

On Fri, Mar 02 2012, Mark Brown wrote:
> Since most of the work is already done by the core we just need to add
> runtime suspend methods and tell the PM core that runtime PM is enabled
> for this device.
>
> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---
>  drivers/mmc/host/sdhci-s3c.c |   28 ++++++++++++++++++++++++++++
>  1 files changed, 28 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index 46152d6..6926ac9 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -23,6 +23,7 @@
>  #include <linux/of.h>
>  #include <linux/of_gpio.h>
>  #include <linux/pm.h>
> +#include <linux/pm_runtime.h>
>  
>  #include <linux/mmc/host.h>
>  
> @@ -721,6 +722,11 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>  	if (pdata->host_caps2)
>  		host->mmc->caps2 |= pdata->host_caps2;
>  
> +	pm_runtime_enable(&pdev->dev);
> +	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
> +	pm_runtime_use_autosuspend(&pdev->dev);
> +	pm_suspend_ignore_children(&pdev->dev, 1);
> +
>  	ret = sdhci_add_host(host);
>  	if (ret) {
>  		dev_err(dev, "sdhci_add_host() failed\n");
> @@ -740,6 +746,8 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>  
>   err_add_host:
>  	release_resource(sc->ioarea);
> +	pm_runtime_forbid(&pdev->dev);
> +	pm_runtime_get_noresume(&pdev->dev);
>  	kfree(sc->ioarea);
>  
>   err_req_regs:
> @@ -784,6 +792,8 @@ static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
>  
>  	sdhci_remove_host(host, 1);
>  
> +	pm_runtime_disable(&pdev->dev);
> +
>  	for (ptr = 0; ptr < 3; ptr++) {
>  		if (sc->clk_bus[ptr]) {
>  			clk_disable(sc->clk_bus[ptr]);
> @@ -824,9 +834,27 @@ static int sdhci_s3c_resume(struct device *dev)
>  }
>  #endif
>  
> +#ifdef CONFIG_PM_RUNTIME
> +static int sdhci_s3c_runtime_suspend(struct device *dev)
> +{
> +	struct sdhci_host *host = dev_get_drvdata(dev);
> +
> +	return sdhci_runtime_suspend_host(host);
> +}
> +
> +static int sdhci_s3c_runtime_resume(struct device *dev)
> +{
> +	struct sdhci_host *host = dev_get_drvdata(dev);
> +
> +	return sdhci_runtime_resume_host(host);
> +}
> +#endif
> +
>  #ifdef CONFIG_PM
>  static const struct dev_pm_ops sdhci_s3c_pmops = {
>  	SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
> +	SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
> +			   NULL)
>  };
>  
>  #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)

I had to rework this patch to avoid a conflict with Julia Lawall's patch
"mmc: sdhci-s3c: use devm_ functions": https://lkml.org/lkml/2012/2/18/76

The reworked patch is below, please let me know if it looks incorrect:

From: Mark Brown <broonie at opensource.wolfsonmicro.com>
Subject: [PATCH] mmc: sdhci-s3c: Enable runtime power management

Since most of the work is already done by the core we just need to add
runtime suspend methods and tell the PM core that runtime PM is enabled
for this device.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
Acked-by: Jaehoon Chung <jh80.chung at samsung.com>
Signed-off-by: Chris Ball <cjb at laptop.org>
---
 drivers/mmc/host/sdhci-s3c.c |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 9683322..312aaf4 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -23,6 +23,7 @@
 #include <linux/of.h>
 #include <linux/of_gpio.h>
 #include <linux/pm.h>
+#include <linux/pm_runtime.h>
 
 #include <linux/mmc/host.h>
 
@@ -705,9 +706,16 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	if (pdata->host_caps)
 		host->mmc->caps |= pdata->host_caps;
 
+	pm_runtime_enable(&pdev->dev);
+	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
+	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_suspend_ignore_children(&pdev->dev, 1);
+
 	ret = sdhci_add_host(host);
 	if (ret) {
 		dev_err(dev, "sdhci_add_host() failed\n");
+		pm_runtime_forbid(&pdev->dev);
+		pm_runtime_get_noresume(&pdev->dev);
 		goto err_req_regs;
 	}
 
@@ -764,6 +772,8 @@ static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
 
 	sdhci_remove_host(host, 1);
 
+	pm_runtime_disable(&pdev->dev);
+
 	for (ptr = 0; ptr < 3; ptr++) {
 		if (sc->clk_bus[ptr]) {
 			clk_disable(sc->clk_bus[ptr]);
@@ -800,9 +810,27 @@ static int sdhci_s3c_resume(struct device *dev)
 }
 #endif
 
+#ifdef CONFIG_PM_RUNTIME
+static int sdhci_s3c_runtime_suspend(struct device *dev)
+{
+	struct sdhci_host *host = dev_get_drvdata(dev);
+
+	return sdhci_runtime_suspend_host(host);
+}
+
+static int sdhci_s3c_runtime_resume(struct device *dev)
+{
+	struct sdhci_host *host = dev_get_drvdata(dev);
+
+	return sdhci_runtime_resume_host(host);
+}
+#endif
+
 #ifdef CONFIG_PM
 static const struct dev_pm_ops sdhci_s3c_pmops = {
 	SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
+	SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
+			   NULL)
 };
 
 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From robherring2 at gmail.com  Sun Mar 11 17:08:17 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sun, 11 Mar 2012 16:08:17 -0500
Subject: [PATCH 1/4] ARM: fix ioremap/iounmap for !CONFIG_MMU
In-Reply-To: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331500100-31351-2-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

With commit 4fe7ef3a081 (ARM: provide runtime hook for ioremap/iounmap),
compiles with !CONFIG_MMU were broken. Rename nommu __iounmap to
__arm_iounmap and add arch_ioremap_caller and arch_iounmap. Its
not expected that these need to be overriden for !CONFIG_MMU, so setting
the function ptrs has no effect in this case.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
---
 arch/arm/mm/nommu.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 4fc6794..6486d2f 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -86,13 +86,17 @@ void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
+void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *);
+
 void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
 				   unsigned int mtype, void *caller)
 {
 	return __arm_ioremap(phys_addr, size, mtype);
 }
 
-void __iounmap(volatile void __iomem *addr)
+void (*arch_iounmap)(volatile void __iomem *);
+
+void __arm_iounmap(volatile void __iomem *addr)
 {
 }
-EXPORT_SYMBOL(__iounmap);
+EXPORT_SYMBOL(__arm_iounmap);
-- 
1.7.5.4



From gerg at snapgear.com  Sun Mar 11 19:48:33 2012
From: gerg at snapgear.com (Greg Ungerer)
Date: Mon, 12 Mar 2012 09:48:33 +1000
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <m3aa3nqpxz.fsf@intrepid.localdomain>
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>	<201202281945.39419.arnd@arndb.de>	<alpine.LFD.2.02.1203052035170.31242@xanadu.home>	<201203061412.00073.arnd@arndb.de>	<alpine.LFD.2.02.1203061146210.31242@xanadu.home>	<CACRpkdYQpnSMVWUizEYHTjx_AK5Ai7dos0SBd208Wf5ZJLdrCw@mail.gmail.com>	<20120307091409.GL17370@n2100.arm.linux.org.uk>	<4F574C64.7010905@snapgear.com>
 <m3aa3nqpxz.fsf@intrepid.localdomain>
Message-ID: <4F5D39D1.4050000@snapgear.com>

On 11/03/12 22:31, Krzysztof Halasa wrote:
> Greg Ungerer<gerg at snapgear.com>  writes:
>
>> The built in ethernet interfaces on the ixp4xx family are not PCI
>> based. So they at least do not suffer from the BE/LE conversions
>> at the eth driver.
>
> The problematic one is IXP42x rev. A0. It has no support for hw mixed
> mode (LE core + lane swapping where needed). Unfortunately this early

It is not problematic if you are running your core BE right?

Regards
Greg



> chip is quite popular. "Software" mixed mode means byte swapping in the
> network drivers and IIRC the crypto accelerator becomes unusable (at
> least without workarounds).
>
> Later revisions (42x rev. B0 and up, and all other IXP4[356]) can work
> in the most efficient hw mixed mode. Support is not upstream but it's
> basically ready. I think it may be incompatible with XIP.


-- 
------------------------------------------------------------------------
Greg Ungerer  --  Principal Engineer        EMAIL:     gerg at snapgear.com
SnapGear Group, McAfee                      PHONE:       +61 7 3435 2888
8 Gardner Close                             FAX:         +61 7 3217 5323
Milton, QLD, 4064, Australia                WEB: http://www.SnapGear.com


From mturquette at ti.com  Fri Mar  9 13:35:07 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 9 Mar 2012 10:35:07 -0800
Subject: [PATCH v5 0/4] common clk framework
In-Reply-To: <20120309023418.GF3261@b20223-02.ap.freescale.net>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <20120309023418.GF3261@b20223-02.ap.freescale.net>
Message-ID: <CAJOA=zOPTG-pZcQvpSPuNVduxN-3SyBGoygdALeAZFU01Bi4oQ@mail.gmail.com>

On Thu, Mar 8, 2012 at 6:34 PM, Richard Zhao <richard.zhao at freescale.com> wrote:
> Hello Mike,
>
> The main interface for clk implementer is to register clocks dynamically.
> I think it highly depends on clk DT bindings. From the patch Grant sent
> out, it looks like he doesn't like one node per clk. So how do we
> register clocks dynamically? You have any sample code?

I can only speak for my own platform, but after talks with Paul W. and
Benoit C. I believe that OMAP will not push ALL of it's on-SoC clocks
into DT.  DT is meant to solve board-level integration problems and
the majority of OMAP clocks are SoC-level, not board level.  Some
clocks will migrate out to DT such as the primary oscillator (which
varies per board) as well as some leaf clocks and modules clocks that
depend on board-specific peripherals.

Otherwise the answer to your question is 'no'.  I don't have any
sample code for DT bindings.  It should not be hard to map some sample
clock bindings onto the existing registration functions... but it will
still be one clock per node.  I'm not really a fan of making clock
black-boxes where the details of the tree are hidden from the
framework anyways... that's something that clkdev already achieves to
some degree (by not exposing the entire tree to drivers, but only the
clocks that we want exposed).

Regards,
Mike

>
> Thanks
> Richard
>


From khc at pm.waw.pl  Sun Mar 11 08:31:36 2012
From: khc at pm.waw.pl (Krzysztof Halasa)
Date: Sun, 11 Mar 2012 13:31:36 +0100
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <4F574C64.7010905@snapgear.com> (Greg Ungerer's message of "Wed, 
 7 Mar 2012 21:54:12 +1000")
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201202281945.39419.arnd@arndb.de>
 <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
 <201203061412.00073.arnd@arndb.de>
 <alpine.LFD.2.02.1203061146210.31242@xanadu.home>
 <CACRpkdYQpnSMVWUizEYHTjx_AK5Ai7dos0SBd208Wf5ZJLdrCw@mail.gmail.com>
 <20120307091409.GL17370@n2100.arm.linux.org.uk>
 <4F574C64.7010905@snapgear.com>
Message-ID: <m3aa3nqpxz.fsf@intrepid.localdomain>

Greg Ungerer <gerg at snapgear.com> writes:

> The built in ethernet interfaces on the ixp4xx family are not PCI
> based. So they at least do not suffer from the BE/LE conversions
> at the eth driver.

The problematic one is IXP42x rev. A0. It has no support for hw mixed
mode (LE core + lane swapping where needed). Unfortunately this early
chip is quite popular. "Software" mixed mode means byte swapping in the
network drivers and IIRC the crypto accelerator becomes unusable (at
least without workarounds).

Later revisions (42x rev. B0 and up, and all other IXP4[356]) can work
in the most efficient hw mixed mode. Support is not upstream but it's
basically ready. I think it may be incompatible with XIP.
-- 
Krzysztof Halasa


From broonie at opensource.wolfsonmicro.com  Fri Mar  9 06:55:44 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 11:55:44 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F591B8D.8090705@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
Message-ID: <20120309115540.GE3273@opensource.wolfsonmicro.com>

On Thu, Mar 08, 2012 at 02:50:21PM -0600, Timur Tabi wrote:
> Shawn Guo wrote:

> > More importantly, the imx machine drivers to be added working with
> > fsl_ssi will not have this property, as they use new ASoC machine
> > driver binding mechanism.

> I want to see that binding documented in Documentation/devicetree/bindings
> first.

That binding will generally be per machine driver.
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From marc at cpdesign.com.au  Sat Mar 10 20:29:59 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Sun, 11 Mar 2012 12:29:59 +1100
Subject: mfd: mc13xxx: add I2C support, V2
Message-ID: <1331429402-9639-1-git-send-email-marc@cpdesign.com.au>

Hi,                                                                                                                            

This series (based on Samuel's mfd-2.6/for-next) adds I2C support for the
mc13xxx family PMICs. Thanks to Oscar for adding dt support for the I2C driver.                       

V2 lets both I2C and SPI support be enabled at the same time and limits the 
scope of common definitions by using a private include header rather than global
one.
The only issue from V1 [0] not addressed is the use of regmap - mainly, I don't
have the time. I accept that this is a lame excuse but hope that use of regmap 
can come later if it is required.

Cheers,
Marc                        

[0] http://www.spinics.net/lists/linux-i2c/msg06992.html



From stigge at antcom.de  Sat Mar 10 20:46:15 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 11 Mar 2012 02:46:15 +0100
Subject: [PATCH v6 3/3] USB: ohci-nxp: Support for LPC32xx
In-Reply-To: <1331430375-31227-1-git-send-email-stigge@antcom.de>
References: <1331430375-31227-1-git-send-email-stigge@antcom.de>
Message-ID: <1331430375-31227-4-git-send-email-stigge@antcom.de>

This patch adds support for the LPC32xx to ohci-nxp

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 drivers/usb/host/ohci-hcd.c |    2 
 drivers/usb/host/ohci-nxp.c |  132 ++++++++++++++++++++++++++++++++------------
 2 files changed, 99 insertions(+), 35 deletions(-)

--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1050,7 +1050,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_hcd_at91_driver
 #endif
 
-#ifdef CONFIG_ARCH_PNX4008
+#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX)
 #include "ohci-nxp.c"
 #define PLATFORM_DRIVER		usb_hcd_nxp_driver
 #endif
--- linux-2.6.orig/drivers/usb/host/ohci-nxp.c
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -5,6 +5,7 @@
  *
  * Currently supported OHCI host devices:
  * - Philips PNX4008
+ * - NXP LPC32xx
  *
  * Authors: Dmitry Chigirev <source at mvista.com>
  *	    Vitaly Wool <vitalywool at gmail.com>
@@ -25,20 +26,24 @@
 #include <linux/i2c.h>
 
 #include <mach/hardware.h>
+#include <asm/mach-types.h>
 #include <asm/io.h>
 
 #include <mach/platform.h>
 #include <mach/irqs.h>
 #include <asm/gpio.h>
 
-#define USB_CTRL	IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64)
+#define USB_CONFIG_BASE		0x31020000
+#define PWRMAN_BASE		0x40004000
+
+#define USB_CTRL		IO_ADDRESS(PWRMAN_BASE + 0x64)
 
 /* USB_CTRL bit defines */
 #define USB_SLAVE_HCLK_EN	(1 << 24)
 #define USB_HOST_NEED_CLK_EN	(1 << 21)
 
-#define USB_OTG_CLK_CTRL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF4)
-#define USB_OTG_CLK_STAT	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF8)
+#define USB_OTG_CLK_CTRL	IO_ADDRESS(USB_CONFIG_BASE + 0xFF4)
+#define USB_OTG_CLK_STAT	IO_ADDRESS(USB_CONFIG_BASE + 0xFF8)
 
 /* USB_OTG_CLK_CTRL bit defines */
 #define AHB_M_CLOCK_ON		(1 << 4)
@@ -47,7 +52,7 @@
 #define DEV_CLOCK_ON		(1 << 1)
 #define HOST_CLOCK_ON		(1 << 0)
 
-#define USB_OTG_STAT_CONTROL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x110)
+#define USB_OTG_STAT_CONTROL	IO_ADDRESS(USB_CONFIG_BASE + 0x110)
 
 /* USB_OTG_STAT_CONTROL bit defines */
 #define TRANSPARENT_I2C_EN	(1 << 7)
@@ -101,6 +106,15 @@
 #define ISP1301_I2C_INTERRUPT_RISING 0xE
 #define ISP1301_I2C_REG_CLEAR_ADDR 1
 
+/* On LPC32xx, those are undefined */
+#ifndef start_int_set_falling_edge
+#define start_int_set_falling_edge(irq)
+#define start_int_set_rising_edge(irq)
+#define start_int_ack(irq)
+#define start_int_mask(irq)
+#define start_int_umask(irq)
+#endif
+
 static struct i2c_driver isp1301_driver;
 static struct i2c_client *isp1301_i2c_client;
 
@@ -146,7 +160,7 @@ static void i2c_write(u8 buf, u8 subaddr
 	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
 }
 
-static void isp1301_configure(void)
+static void isp1301_configure_pnx4008(void)
 {
 	/* PNX4008 only supports DAT_SE0 USB mode */
 	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
@@ -169,7 +183,53 @@ static void isp1301_configure(void)
 		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
 	i2c_write(0xFF,
 		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+}
+
+static void isp1301_configure_lpc32xx(void)
+{
+	/* LPC32XX only supports DAT_SE0 USB mode */
+	/* This sequence is important */
+
+	/* Disable transparent UART mode first */
+	i2c_write(MC1_UART_EN,
+		  (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(~MC1_SPEED_REG, (ISP1301_I2C_MODE_CONTROL_1 |
+				   ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
+	i2c_write(~0,
+		  (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write((MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
+		  ISP1301_I2C_MODE_CONTROL_2);
+	i2c_write(~0, (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(MC1_DAT_SE0, ISP1301_I2C_MODE_CONTROL_1);
+	i2c_write((OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
+		  ISP1301_I2C_OTG_CONTROL_1);
+	i2c_write((OTG1_DM_PULLUP | OTG1_DP_PULLUP),
+		  (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(~0,
+		  ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(~0,
+		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(~0,
+		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+
+	/* Enable usb_need_clk clock after transceiver is initialized */
+	__raw_writel((__raw_readl(USB_CTRL) | (1 << 22)), USB_CTRL);
+
+	printk(KERN_INFO "ISP1301 Vendor ID  : 0x%04x\n",
+	      i2c_smbus_read_word_data(isp1301_i2c_client, 0x00));
+	printk(KERN_INFO "ISP1301 Product ID : 0x%04x\n",
+	      i2c_smbus_read_word_data(isp1301_i2c_client, 0x02));
+	printk(KERN_INFO "ISP1301 Version ID : 0x%04x\n",
+	      i2c_smbus_read_word_data(isp1301_i2c_client, 0x14));
+}
 
+static void isp1301_configure(void)
+{
+	if (machine_is_pnx4008())
+		isp1301_configure_pnx4008();
+	else
+		isp1301_configure_lpc32xx();
 }
 
 static inline void isp1301_vbus_on(void)
@@ -260,39 +320,43 @@ static const struct hc_driver ohci_nxp_h
 
 static void nxp_set_usb_bits(void)
 {
-	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-	start_int_ack(SE_USB_OTG_ATX_INT_N);
-	start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-	start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-	start_int_ack(SE_USB_OTG_TIMER_INT);
-	start_int_umask(SE_USB_OTG_TIMER_INT);
-
-	start_int_set_rising_edge(SE_USB_I2C_INT);
-	start_int_ack(SE_USB_I2C_INT);
-	start_int_umask(SE_USB_I2C_INT);
-
-	start_int_set_rising_edge(SE_USB_INT);
-	start_int_ack(SE_USB_INT);
-	start_int_umask(SE_USB_INT);
-
-	start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-	start_int_ack(SE_USB_NEED_CLK_INT);
-	start_int_umask(SE_USB_NEED_CLK_INT);
-
-	start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-	start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+	if (machine_is_pnx4008()) {
+		start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
+		start_int_ack(SE_USB_OTG_ATX_INT_N);
+		start_int_umask(SE_USB_OTG_ATX_INT_N);
+
+		start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
+		start_int_ack(SE_USB_OTG_TIMER_INT);
+		start_int_umask(SE_USB_OTG_TIMER_INT);
+
+		start_int_set_rising_edge(SE_USB_I2C_INT);
+		start_int_ack(SE_USB_I2C_INT);
+		start_int_umask(SE_USB_I2C_INT);
+
+		start_int_set_rising_edge(SE_USB_INT);
+		start_int_ack(SE_USB_INT);
+		start_int_umask(SE_USB_INT);
+
+		start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
+		start_int_ack(SE_USB_NEED_CLK_INT);
+		start_int_umask(SE_USB_NEED_CLK_INT);
+
+		start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
+		start_int_ack(SE_USB_AHB_NEED_CLK_INT);
+		start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+	}
 }
 
 static void nxp_unset_usb_bits(void)
 {
-	start_int_mask(SE_USB_OTG_ATX_INT_N);
-	start_int_mask(SE_USB_OTG_TIMER_INT);
-	start_int_mask(SE_USB_I2C_INT);
-	start_int_mask(SE_USB_INT);
-	start_int_mask(SE_USB_NEED_CLK_INT);
-	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+	if (machine_is_pnx4008()) {
+		start_int_mask(SE_USB_OTG_ATX_INT_N);
+		start_int_mask(SE_USB_OTG_TIMER_INT);
+		start_int_mask(SE_USB_I2C_INT);
+		start_int_mask(SE_USB_INT);
+		start_int_mask(SE_USB_NEED_CLK_INT);
+		start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+	}
 }
 
 static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)


From broonie at opensource.wolfsonmicro.com  Fri Mar  9 07:26:06 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 12:26:06 +0000
Subject: [PATCH 2/2] mmc: sdhci-s3c: Enable runtime power management
In-Reply-To: <m2vcmenyxh.fsf@bob.laptop.org>
References: <4F51697C.40408@samsung.com>
 <1330735602-22409-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1330735602-22409-2-git-send-email-broonie@opensource.wolfsonmicro.com>
 <m2vcmenyxh.fsf@bob.laptop.org>
Message-ID: <20120309122606.GN3273@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 12:08:58AM -0500, Chris Ball wrote:

> The reworked patch is below, please let me know if it looks incorrect:

That looks about right, I'll find out soon enough if it doesn't work in
-next as my main development system has the rootfs on this device :)
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From rusty at rustcorp.com.au  Thu Mar  8 23:26:52 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 09 Mar 2012 14:56:52 +1030
Subject: [PATCH 8/8] ARM: KVM: don't BUG() if guest executes smc.
Message-ID: <1331267212.6033.rusty@rustcorp.com.au>


From: Rusty Russell <rusty at rustcorp.com.au>

In this case, we just kill the guest.

Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
---
 arch/arm/kvm/arm.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 1724657..9ef5bdb 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -367,6 +367,13 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 	return 0;
 }
 
+static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+	/* We don't support SMC; don't do that. */
+	kvm_debug("smc: at %08x", vcpu->arch.regs.pc);
+	return -EINVAL;
+}
+
 static int handle_dabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
 	/* The hypervisor should never cause aborts */
@@ -386,6 +393,7 @@ static int (*arm_exit_handlers[])(struct kvm_vcpu *vcpu, struct kvm_run *r) = {
 	[HSR_EC_CP10_ID]	= kvm_handle_cp10_id,
 	[HSR_EC_SVC_HYP]	= handle_svc_hyp,
 	[HSR_EC_HVC]		= handle_hvc,
+	[HSR_EC_SMC	]	= handle_smc,
 	[HSR_EC_IABT]		= kvm_handle_guest_abort,
 	[HSR_EC_DABT]		= kvm_handle_guest_abort,
 	[HSR_EC_DABT_HYP]	= handle_dabt_hyp,



From neidhard.kim at lge.com  Mon Mar 12 07:28:56 2012
From: neidhard.kim at lge.com (Kim, Jong-Sung)
Date: Mon, 12 Mar 2012 20:28:56 +0900
Subject: [PATCH] serial: PL011: clear pending interrupts
In-Reply-To: <20120312101100.GA8649@n2100.arm.linux.org.uk>
References: <1331540750-25697-1-git-send-email-linus.walleij@stericsson.com>
 <20120312083221.GW17370@n2100.arm.linux.org.uk>
 <20120312101100.GA8649@n2100.arm.linux.org.uk>
Message-ID: <01e201cd0043$5010cea0$f0326be0$@lge.com>

> On Mon, Mar 12, 2012 at 08:32:21AM +0000, Russell King - ARM Linux wrote:
> > On Mon, Mar 12, 2012 at 09:25:50AM +0100, Linus Walleij wrote:
> > > diff --git a/drivers/tty/serial/amba-pl011.c
> > > b/drivers/tty/serial/amba-pl011.c index 6800f5f..ff3fed0 100644
> > > --- a/drivers/tty/serial/amba-pl011.c
> > > +++ b/drivers/tty/serial/amba-pl011.c
> > > @@ -224,6 +224,11 @@ static int pl011_fifo_to_tty(struct
uart_amba_port
> *uap)
> > >  		uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
> > >  	}
> > >
> >
> > What if we really do end up receiving some characters here?
> >
> > > +	/* RXIS but RXFE? Just clear the interrupt */
> > > +	if(unlikely(fifotaken == 0))
> > > +		writew(UART011_RTIS | UART011_RXIS,
> > > +		       uap->port.membase + UART011_ICR);
> 
> BTW, I don't see why we need any of this stuff.

Actually, I meant my patch applied alone, not with your patch. My thought
was the problem we're trying to handle is undocumented and is not guaranteed
not to happen again.





From jm at lentin.co.uk  Mon Mar 12 10:22:24 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Mon, 12 Mar 2012 14:22:24 -0000
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <201203120817.19777.arnd@arndb.de>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <1331476406-9844-2-git-send-email-jm@lentin.co.uk>
 <20120312030232.GX5050@titan.lakedaemon.net>
 <201203120817.19777.arnd@arndb.de>
Message-ID: <op.wa197mq94cuzmg@gonzo.lentin.co.uk>

On Mon, 12 Mar 2012 08:17:19 -0000, Arnd Bergmann <arnd at arndb.de> wrote:

> On Monday 12 March 2012, Jason Cooper wrote:
>> > +     dnskw_gpio_register(39, "dnskw:power:sata0", 1);
>> > +     dnskw_gpio_register(40, "dnskw:power:sata1", 1);
>> > +
>> > +     /* Set NAS to turn back on after a power failure */
>> > +     dnskw_gpio_register(37, "dnskw:power:recover", 1);
>> > +}
>> > +
>>
>> I doubt this board is the only one that wants to be added while the
>> conversion to devicetree is progressing.  It makes more sense to me to
>> break the above out to a separate file, eg board-dnskw.c.  I'll follow
>> and break out the dreamplug code to board-dreamplug.c.  Otherwise, I see
>> board-dt.c becoming a long mess.
>>
>> Arnd, sound okay to you?
>
> Either way is fine with me. I personally wouldn't expect many more boards
> to come in before the DT conversion has mostly completed, but I guess you
> have a better feeling for what other hardware is out there that people
> are interested in.
>

It probably depends on how easy it is to add the gpiochips into  
devicetree. Being able to put the LED, buttons and fans in devicetree  
would make board-dt.c much more manageable. I started to look into it and  
wasn't immediately obvious, but will have a closer look.

Happy to resubmit, breaking it out into a board-dnskw.c though.

-- 
Jamie Lentin


From broonie at opensource.wolfsonmicro.com  Fri Mar  9 07:12:38 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 12:12:38 +0000
Subject: [PATCH v3 00/11] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <CAAQ0ZWQHm+SZgDA6x93=Q9CxAqz6uVu1F2UPBc=zafrhT71D1Q@mail.gmail.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <4F5910EE.8090408@freescale.com>
 <20120309011914.GF2499@S2101-09.ap.freescale.net>
 <4F5966DC.6090201@freescale.com>
 <20120309071347.GM2499@S2101-09.ap.freescale.net>
 <CAAQ0ZWQHm+SZgDA6x93=Q9CxAqz6uVu1F2UPBc=zafrhT71D1Q@mail.gmail.com>
Message-ID: <20120309121237.GG3273@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 03:28:22PM +0800, Shawn Guo wrote:
> On 9 March 2012 15:13, Shawn Guo <shawn.guo at linaro.org> wrote:
> > On Fri, Mar 09, 2012 at 02:11:41AM +0000, Tabi Timur-B04825 wrote:
> >> Shawn Guo wrote:
> >> > Are you testing the patch set on top of the SHA below, which I
> >> > mentioned in the cover letter?
> >> >
> >> > ? ?3030763 (Merge tag 'asoc-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into topic/asoc)

Adding Liam who I just noticed isn't on the CCs.

> >> It appears the problem is with for-3.4 itself. ?I'm running git-bisect now
> >> to narrow it down.
> >>
> > My bisect tells that the offending commit is:
> >
> > ?96acc35 (ASoC: DAPM: Make sure DAPM widget IO ops hold the component mutex)
> >
> > But I do not understand why yet.
> 
> =============================================
> [ INFO: possible recursive locking detected ]
> 3.3.0-rc4+ #159 Not tainted
> ---------------------------------------------
> aplay/395 is trying to acquire lock:
>  (&codec->mutex){+.+...}, at: [<802f7414>] soc_widget_update_bits_locked+0x88/0x
> 1a0
> 
> but task is already holding lock:
>  (&codec->mutex){+.+...}, at: [<802f9df4>] snd_soc_dapm_stream_event+0x38/0xc0

Ick, right.  We need to create that separate I/O mutex I think...
Perhaps we should punt the locking change until 3.5 too, there's no
non-CODEC DAPM in 3.4?
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From jason at lakedaemon.net  Sun Mar 11 23:23:03 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 11 Mar 2012 23:23:03 -0400
Subject: [PATCH 2/2] ARM: kirkwood: Convert orion-nand to fdt
In-Reply-To: <1331476406-9844-3-git-send-email-jm@lentin.co.uk>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <1331476406-9844-3-git-send-email-jm@lentin.co.uk>
Message-ID: <20120312032303.GZ5050@titan.lakedaemon.net>

On Sun, Mar 11, 2012 at 02:33:26PM +0000, Jamie Lentin wrote:
> The DNS-320 and 325 have a NAND partitioned to store uboot, uimage and root
> filesystem. Store this information in devicetree.
> 
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> ---
>  .../devicetree/bindings/mtd/orion-nand.txt         |   41 +++++++++++++++++++
>  arch/arm/boot/dts/kirkwood-dns320.dts              |   42 ++++++++++++++++++++
>  arch/arm/boot/dts/kirkwood-dns325.dts              |   42 ++++++++++++++++++++
>  arch/arm/mach-kirkwood/board-dt.c                  |   30 --------------
>  arch/arm/mach-kirkwood/common.c                    |    6 +++
>  drivers/mtd/nand/orion_nand.c                      |   39 +++++++++++++++++-
>  6 files changed, 168 insertions(+), 32 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt
> 
> diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
> new file mode 100644
> index 0000000..53fd469
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/orion-nand.txt
> @@ -0,0 +1,41 @@
> +NAND support for Marvell Orion SoC platforms
> +
> +Required properties:
> +- compatible : "mrvl,orion-nand".
> +- reg : Base physical address of the NAND and length of memory mapped
> +	region
> +
> +Optional properties:
> +- cle :
> +- ale :
> +- width :
> +- chip-delay :
> +
> +Examples:
> +
> +nand at f4000000 {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	cle = <0>;
> +	ale = <1>;
> +	width = <8>;
> +	chip-delay = <25>;
> +	compatible = "mrvl,orion-nand";
> +	reg = <0xf4000000 0x400>;
> +
> +	partition at 0 {
> +		label = "u-boot";
> +		reg = <0x0000000 0x100000>;
> +		read-only;
> +	};
> +
> +	partition at 100000 {
> +		label = "uImage";
> +		reg = <0x0100000 0x200000>;
> +	};
> +
> +	partition at 300000 {
> +		label = "root";
> +		reg = <0x0300000 0x7d00000>;
> +	};

You may want the example to include a partition for the dtb.

I'll let more experienced folks comment on the guts of the nand
bindings.

thx,

Jason.

> +};
> diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
> index c039041..6772f9d 100644
> --- a/arch/arm/boot/dts/kirkwood-dns320.dts
> +++ b/arch/arm/boot/dts/kirkwood-dns320.dts
> @@ -51,4 +51,46 @@
>  		dma-mask = <0xffffffff>;
>  		phy-version = "";
>  	};
> +
> +	nand at f4000000 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		cle = <0>;
> +		ale = <1>;
> +		width = <8>;
> +		chip-delay = <25>;
> +		compatible = "mrvl,orion-nand";
> +		reg = <0xf4000000 0x400>;
> +
> +		partition at 0 {
> +			label = "u-boot";
> +			reg = <0x0000000 0x100000>;
> +			read-only;
> +		};
> +
> +		partition at 100000 {
> +			label = "uImage";
> +			reg = <0x0100000 0x500000>;
> +		};
> +
> +		partition at 600000 {
> +			label = "ramdisk";
> +			reg = <0x0600000 0x500000>;
> +		};
> +
> +		partition at b00000 {
> +			label = "image";
> +			reg = <0x0b00000 0x6600000>;
> +		};
> +
> +		partition at 7100000 {
> +			label = "mini firmware";
> +			reg = <0x7100000 0xa00000>;
> +		};
> +
> +		partition at 7b00000 {
> +			label = "config";
> +			reg = <0x7b00000 0x500000>;
> +		};
> +	};
>  };
> diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
> index a7c2c26..34740ad 100644
> --- a/arch/arm/boot/dts/kirkwood-dns325.dts
> +++ b/arch/arm/boot/dts/kirkwood-dns325.dts
> @@ -37,4 +37,46 @@
>  		dma-mask = <0xffffffff>;
>  		phy-version = "";
>  	};
> +
> +	nand at f4000000 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		cle = <0>;
> +		ale = <1>;
> +		width = <8>;
> +		chip-delay = <25>;
> +		compatible = "mrvl,orion-nand";
> +		reg = <0xf4000000 0x400>;
> +
> +		partition at 0 {
> +			label = "u-boot";
> +			reg = <0x0000000 0x100000>;
> +			read-only;
> +		};
> +
> +		partition at 100000 {
> +			label = "uImage";
> +			reg = <0x0100000 0x500000>;
> +		};
> +
> +		partition at 600000 {
> +			label = "ramdisk";
> +			reg = <0x0600000 0x500000>;
> +		};
> +
> +		partition at b00000 {
> +			label = "image";
> +			reg = <0x0b00000 0x6600000>;
> +		};
> +
> +		partition at 7100000 {
> +			label = "mini firmware";
> +			reg = <0x7100000 0xa00000>;
> +		};
> +
> +		partition at 7b00000 {
> +			label = "config";
> +			reg = <0x7b00000 0x500000>;
> +		};
> +	};
>  };
> diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
> index 0885713..d5bc60a 100644
> --- a/arch/arm/mach-kirkwood/board-dt.c
> +++ b/arch/arm/mach-kirkwood/board-dt.c
> @@ -158,35 +158,6 @@ static void __init dreamplug_init(void)
>   * DNS-320 & DNS-325 specifics
>   ****************************************************************************/
>  
> -static struct mtd_partition dnskw_nand_parts[] = {
> -	{
> -		.name		= "u-boot",
> -		.offset		= 0,
> -		.size		= SZ_1M,
> -		.mask_flags	= MTD_WRITEABLE
> -	}, {
> -		.name		= "uImage",
> -		.offset		= MTDPART_OFS_NXTBLK,
> -		.size		= 5 * SZ_1M
> -	}, {
> -		.name		= "ramdisk",
> -		.offset		= MTDPART_OFS_NXTBLK,
> -		.size		= 5 * SZ_1M
> -	}, {
> -		.name		= "image",
> -		.offset		= MTDPART_OFS_NXTBLK,
> -		.size		= 102 * SZ_1M
> -	}, {
> -		.name		= "mini firmware",
> -		.offset		= MTDPART_OFS_NXTBLK,
> -		.size		= 10 * SZ_1M
> -	}, {
> -		.name		= "config",
> -		.offset		= MTDPART_OFS_NXTBLK,
> -		.size		= 5 * SZ_1M
> -	},
> -};
> -
>  static struct mv643xx_eth_platform_data dnskw_ge00_data = {
>  	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
>  };
> @@ -395,7 +366,6 @@ static void __init dnskw_init(void)
>  	u32 dev, rev;
>  
>  	kirkwood_mpp_conf(dnskw_mpp_config);
> -	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
>  
>  	kirkwood_ge00_init(&dnskw_ge00_data);
>  	kirkwood_i2c_init();
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index 70ee7ac..f135854 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -505,6 +505,12 @@ static int __init kirkwood_clock_gate(void)
>  		of_node_put(np);
>  	}
>  
> +	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-nand");
> +	if (np && of_device_is_available(np)) {
> +		kirkwood_clk_ctrl |= CGC_RUNIT;
> +		of_node_put(np);
> +	}
> +
>  	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-sata");
>  	if (np && of_device_is_available(np)) {
>  		int nr_ports;
> diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
> index 29f505a..5ae0030 100644
> --- a/drivers/mtd/nand/orion_nand.c
> +++ b/drivers/mtd/nand/orion_nand.c
> @@ -13,6 +13,7 @@
>  #include <linux/slab.h>
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
> +#include <linux/of.h>
>  #include <linux/mtd/mtd.h>
>  #include <linux/mtd/nand.h>
>  #include <linux/mtd/partitions.h>
> @@ -74,11 +75,13 @@ static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>  static int __init orion_nand_probe(struct platform_device *pdev)
>  {
>  	struct mtd_info *mtd;
> +	struct mtd_part_parser_data ppdata = {};
>  	struct nand_chip *nc;
>  	struct orion_nand_data *board;
>  	struct resource *res;
>  	void __iomem *io_base;
>  	int ret = 0;
> +	u32 val = 0;
>  
>  	nc = kzalloc(sizeof(struct nand_chip) + sizeof(struct mtd_info), GFP_KERNEL);
>  	if (!nc) {
> @@ -101,7 +104,24 @@ static int __init orion_nand_probe(struct platform_device *pdev)
>  		goto no_res;
>  	}
>  
> -	board = pdev->dev.platform_data;
> +	if (pdev->dev.of_node) {
> +		board = kzalloc(sizeof(struct orion_nand_data), GFP_KERNEL);
> +		if (!board) {
> +			printk(KERN_ERR "orion_nand: failed to allocate board structure.\n");
> +			ret = -ENOMEM;
> +			goto no_res;
> +		}
> +		if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
> +			board->cle = (u8)val;
> +		if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
> +			board->ale = (u8)val;
> +		if (!of_property_read_u32(pdev->dev.of_node, "width", &val))
> +			board->width = (u8)val;
> +		if (!of_property_read_u32(pdev->dev.of_node,
> +						"chip-delay", &val))
> +			board->chip_delay = (u8)val;
> +	} else
> +		board = pdev->dev.platform_data;
>  
>  	mtd->priv = nc;
>  	mtd->owner = THIS_MODULE;
> @@ -129,7 +149,8 @@ static int __init orion_nand_probe(struct platform_device *pdev)
>  	}
>  
>  	mtd->name = "orion_nand";
> -	ret = mtd_device_parse_register(mtd, NULL, 0,
> +	ppdata.of_node = pdev->dev.of_node;
> +	ret = mtd_device_parse_register(mtd, NULL, &ppdata,
>  			board->parts, board->nr_parts);
>  	if (ret) {
>  		nand_release(mtd);
> @@ -141,6 +162,8 @@ static int __init orion_nand_probe(struct platform_device *pdev)
>  no_dev:
>  	platform_set_drvdata(pdev, NULL);
>  	iounmap(io_base);
> +	if (pdev->dev.of_node)
> +		kfree(board);
>  no_res:
>  	kfree(nc);
>  
> @@ -156,16 +179,28 @@ static int __devexit orion_nand_remove(struct platform_device *pdev)
>  
>  	iounmap(nc->IO_ADDR_W);
>  
> +	if (pdev->dev.of_node)
> +		kfree(nc->priv);
>  	kfree(nc);
>  
>  	return 0;
>  }
>  
> +#ifdef CONFIG_OF
> +static struct of_device_id orion_nand_of_match_table[] = {
> +	{ .compatible = "mrvl,orion-nand", },
> +	{},
> +};
> +#else
> +#define orion_nand_of_match_table NULL
> +#endif
> +
>  static struct platform_driver orion_nand_driver = {
>  	.remove		= __devexit_p(orion_nand_remove),
>  	.driver		= {
>  		.name	= "orion_nand",
>  		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(orion_nand_of_match_table),
>  	},
>  };
>  
> -- 
> 1.7.9.1
> 


From Julia.Lawall at lip6.fr  Sun Mar 11 15:36:22 2012
From: Julia.Lawall at lip6.fr (Julia Lawall)
Date: Sun, 11 Mar 2012 20:36:22 +0100
Subject: [PATCH 2/7] drivers/scsi/arm/{cumana_2, eesox,
 powertec}.c: ensure arguments to request_irq and free_irq are
 compatible
In-Reply-To: <1331494587-12196-1-git-send-email-Julia.Lawall@lip6.fr>
References: <1331494587-12196-1-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1331494587-12196-3-git-send-email-Julia.Lawall@lip6.fr>

From: Julia Lawall <Julia.Lawall at lip6.fr>

Convert calls to free_irq so that the second argument is the same as the
last argument of the corresponding call to request_irq.  Without this
property, free_irq does nothing.

In each case, the problem is only in the probe function.  The corresponding
call in the remove function already has the correct second argument.

Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

---
Not tested.

 drivers/scsi/arm/cumana_2.c |    2 +-
 drivers/scsi/arm/eesox.c    |    2 +-
 drivers/scsi/arm/powertec.c |    2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/scsi/arm/cumana_2.c b/drivers/scsi/arm/cumana_2.c
index 547987b..693d383 100644
--- a/drivers/scsi/arm/cumana_2.c
+++ b/drivers/scsi/arm/cumana_2.c
@@ -480,7 +480,7 @@ cumanascsi2_probe(struct expansion_card *ec, const struct ecard_id *id)
 
 	if (info->info.scsi.dma != NO_DMA)
 		free_dma(info->info.scsi.dma);
-	free_irq(ec->irq, host);
+	free_irq(ec->irq, info);
 
  out_release:
 	fas216_release(host);
diff --git a/drivers/scsi/arm/eesox.c b/drivers/scsi/arm/eesox.c
index edfd12b..48c1a14 100644
--- a/drivers/scsi/arm/eesox.c
+++ b/drivers/scsi/arm/eesox.c
@@ -601,7 +601,7 @@ eesoxscsi_probe(struct expansion_card *ec, const struct ecard_id *id)
 
 	if (info->info.scsi.dma != NO_DMA)
 		free_dma(info->info.scsi.dma);
-	free_irq(ec->irq, host);
+	free_irq(ec->irq, info);
 
  out_remove:
 	fas216_remove(host);
diff --git a/drivers/scsi/arm/powertec.c b/drivers/scsi/arm/powertec.c
index 9274c06..c9d6e8b 100644
--- a/drivers/scsi/arm/powertec.c
+++ b/drivers/scsi/arm/powertec.c
@@ -393,7 +393,7 @@ powertecscsi_probe(struct expansion_card *ec, const struct ecard_id *id)
 
 	if (info->info.scsi.dma != NO_DMA)
 		free_dma(info->info.scsi.dma);
-	free_irq(ec->irq, host);
+	free_irq(ec->irq, info);
 
  out_release:
 	fas216_release(host);



From stigge at antcom.de  Sat Mar 10 17:29:18 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sat, 10 Mar 2012 23:29:18 +0100
Subject: [PATCH v5 3/3] USB: ohci-nxp: Support for LPC32xx
In-Reply-To: <20120310204955.GA14564@pengutronix.de>
References: <1331408166-11607-1-git-send-email-stigge@antcom.de>
 <1331408166-11607-4-git-send-email-stigge@antcom.de>
 <20120310204955.GA14564@pengutronix.de>
Message-ID: <4F5BD5BE.3000808@antcom.de>

On 10/03/12 21:49, Wolfram Sang wrote:
>> -static void isp1301_configure(void) +static u16 i2c_read16(u8
>> subaddr) +{ +	u16 data; + +	i2c_master_send(isp1301_i2c_client,
>> &subaddr, 1); +	i2c_master_recv(isp1301_i2c_client, (u8 *) &data,
>> 2); + +	return data; +}
> 
> Won't i2c_smbus_read_word_data(isp1301_i2c_client, reg) do?

Yes, thank you for the hint! Replaced i2c_read16() with
i2c_smbus_read_word_data() calls.

> And while we are at it: Could you also try replacing i2c_write()
> with i2c_smbus_write_byte_data(isp1301_i2c_client, reg, val)?

Interestingly now, replacing i2c_write() calls with
i2c_smbus_write_byte_data() did _not_ work (hardware initialization
failure). I guess this is due to the differences between i2c and
smbus, and the hardware only handles the former correctly?

Roland


From mturquette at linaro.org  Sat Mar 10 02:54:23 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Fri,  9 Mar 2012 23:54:23 -0800
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
Message-ID: <1331366064-1273-3-git-send-email-mturquette@linaro.org>

The common clock framework defines a common struct clk useful across
most platforms as well as an implementation of the clk api that drivers
can use safely for managing clocks.

The net result is consolidation of many different struct clk definitions
and platform-specific clock framework implementations.

This patch introduces the common struct clk, struct clk_ops and an
implementation of the well-known clock api in include/clk/clk.h.
Platforms may define their own hardware-specific clock structure and
their own clock operation callbacks, so long as it wraps an instance of
struct clk_hw.

See Documentation/clk.txt for more details.

This patch is based on the work of Jeremy Kerr, which in turn was based
on the work of Ben Herrenschmidt.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Mike Turquette <mturquette at ti.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Andrew Lunn <andrew at lunn.ch>
---
Changes since v5:
 * new CONFIG_COMMON_CLK_DISABLE_UNUSED feature
  * results in a new clk_op callback, .is_enabled
 * new helpers
  * __clk_get_prepare_count
  * __clk_get_enable_count
  * __clk_is_enabled
 * fix bug in __clk_get_rate for orphan clocks

 drivers/clk/Kconfig          |   39 ++
 drivers/clk/Makefile         |    1 +
 drivers/clk/clk.c            | 1424 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-private.h  |   68 ++
 include/linux/clk-provider.h |  171 +++++
 include/linux/clk.h          |   68 ++-
 6 files changed, 1766 insertions(+), 5 deletions(-)
 create mode 100644 drivers/clk/clk.c
 create mode 100644 include/linux/clk-private.h
 create mode 100644 include/linux/clk-provider.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9b3cd08..31ceb27 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -8,3 +8,42 @@ config HAVE_CLK_PREPARE
 
 config HAVE_MACH_CLKDEV
 	bool
+
+menuconfig COMMON_CLK
+	bool "Common Clock Framework"
+	select HAVE_CLK_PREPARE
+	---help---
+	  The common clock framework is a single definition of struct
+	  clk, useful across many platforms, as well as an
+	  implementation of the clock API in include/linux/clk.h.
+	  Architectures utilizing the common struct clk should select
+	  this automatically, but it may be necessary to manually select
+	  this option for loadable modules requiring the common clock
+	  framework.
+
+	  If in doubt, say "N".
+
+if COMMON_CLK
+
+config COMMON_CLK_DISABLE_UNUSED
+	bool "Disabled unused clocks at boot"
+	depends on COMMON_CLK
+	---help---
+	  Traverses the entire clock tree and disables any clocks that are
+	  enabled in hardware but have not been enabled by any device drivers.
+	  This saves power and keeps the software model of the clock in line
+	  with reality.
+
+	  If in doubt, say "N".
+
+config COMMON_CLK_DEBUG
+	bool "DebugFS representation of clock tree"
+	depends on COMMON_CLK
+	---help---
+	  Creates a directory hierchy in debugfs for visualizing the clk
+	  tree structure.  Each directory contains read-only members
+	  that export information specific to that clk node: clk_rate,
+	  clk_flags, clk_prepare_count, clk_enable_count &
+	  clk_notifier_count.
+
+endif
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 07613fa..ff362c4 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,2 +1,3 @@
 
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
+obj-$(CONFIG_COMMON_CLK)	+= clk.o
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
new file mode 100644
index 0000000..c7c3bc5
--- /dev/null
+++ b/drivers/clk/clk.c
@@ -0,0 +1,1424 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
+ * Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Standard functionality for the common clock API.  See Documentation/clk.txt
+ */
+
+#include <linux/clk-private.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/slab.h>
+
+static DEFINE_SPINLOCK(enable_lock);
+static DEFINE_MUTEX(prepare_lock);
+
+static HLIST_HEAD(clk_root_list);
+static HLIST_HEAD(clk_orphan_list);
+static LIST_HEAD(clk_notifier_list);
+
+/***        debugfs support        ***/
+
+#ifdef CONFIG_COMMON_CLK_DEBUG
+#include <linux/debugfs.h>
+
+static struct dentry *rootdir;
+static struct dentry *orphandir;
+static int inited = 0;
+
+/* caller must hold prepare_lock */
+static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
+{
+	struct dentry *d;
+	int ret = -ENOMEM;
+
+	if (!clk || !pdentry) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	d = debugfs_create_dir(clk->name, pdentry);
+	if (!d)
+		goto out;
+
+	clk->dentry = d;
+
+	d = debugfs_create_u32("clk_rate", S_IRUGO, clk->dentry,
+			(u32 *)&clk->rate);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
+			(u32 *)&clk->flags);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_u32("clk_prepare_count", S_IRUGO, clk->dentry,
+			(u32 *)&clk->prepare_count);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_u32("clk_enable_count", S_IRUGO, clk->dentry,
+			(u32 *)&clk->enable_count);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_u32("clk_notifier_count", S_IRUGO, clk->dentry,
+			(u32 *)&clk->notifier_count);
+	if (!d)
+		goto err_out;
+
+	ret = 0;
+	goto out;
+
+err_out:
+	debugfs_remove(clk->dentry);
+out:
+	return ret;
+}
+
+/* caller must hold prepare_lock */
+static int clk_debug_create_subtree(struct clk *clk, struct dentry *pdentry)
+{
+	struct clk *child;
+	struct hlist_node *tmp;
+	int ret = -EINVAL;;
+
+	if (!clk || !pdentry)
+		goto out;
+
+	ret = clk_debug_create_one(clk, pdentry);
+
+	if (ret)
+		goto out;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node)
+		clk_debug_create_subtree(child, clk->dentry);
+
+	ret = 0;
+out:
+	return ret;
+}
+
+/**
+ * clk_debug_register - add a clk node to the debugfs clk tree
+ * @clk: the clk being added to the debugfs clk tree
+ *
+ * Dynamically adds a clk to the debugfs clk tree if debugfs has been
+ * initialized.  Otherwise it bails out early since the debugfs clk tree
+ * will be created lazily by clk_debug_init as part of a late_initcall.
+ *
+ * Caller must hold prepare_lock.  Only clk_init calls this function (so
+ * far) so this is taken care.
+ */
+static int clk_debug_register(struct clk *clk)
+{
+	struct clk *parent;
+	struct dentry *pdentry;
+	int ret = 0;
+
+	if (!inited)
+		goto out;
+
+	parent = clk->parent;
+
+	/*
+	 * Check to see if a clk is a root clk.  Also check that it is
+	 * safe to add this clk to debugfs
+	 */
+	if (!parent)
+		if (clk->flags & CLK_IS_ROOT)
+			pdentry = rootdir;
+		else
+			pdentry = orphandir;
+	else
+		if (parent->dentry)
+			pdentry = parent->dentry;
+		else
+			goto out;
+
+	ret = clk_debug_create_subtree(clk, pdentry);
+
+out:
+	return ret;
+}
+
+/**
+ * clk_debug_init - lazily create the debugfs clk tree visualization
+ *
+ * clks are often initialized very early during boot before memory can
+ * be dynamically allocated and well before debugfs is setup.
+ * clk_debug_init walks the clk tree hierarchy while holding
+ * prepare_lock and creates the topology as part of a late_initcall,
+ * thus insuring that clks initialized very early will still be
+ * represented in the debugfs clk tree.  This function should only be
+ * called once at boot-time, and all other clks added dynamically will
+ * be done so with clk_debug_register.
+ */
+static int __init clk_debug_init(void)
+{
+	struct clk *clk;
+	struct hlist_node *tmp;
+
+	rootdir = debugfs_create_dir("clk", NULL);
+
+	if (!rootdir)
+		return -ENOMEM;
+
+	orphandir = debugfs_create_dir("orphans", rootdir);
+
+	if (!orphandir)
+		return -ENOMEM;
+
+	mutex_lock(&prepare_lock);
+
+	hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
+		clk_debug_create_subtree(clk, rootdir);
+
+	hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
+		clk_debug_create_subtree(clk, orphandir);
+
+	inited = 1;
+
+	mutex_unlock(&prepare_lock);
+
+	return 0;
+}
+late_initcall(clk_debug_init);
+#else
+static inline int clk_debug_register(struct clk *clk) { return 0; }
+#endif /* CONFIG_COMMON_CLK_DEBUG */
+
+#ifdef CONFIG_COMMON_CLK_DISABLE_UNUSED
+/* caller must hold prepare_lock */
+static void clk_disable_unused_subtree(struct clk *clk)
+{
+	struct clk *child;
+	struct hlist_node *tmp;
+	unsigned long flags;
+
+	if (!clk)
+		goto out;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node)
+		clk_disable_unused_subtree(child);
+
+	spin_lock_irqsave(&enable_lock, flags);
+
+	if (clk->enable_count)
+		goto unlock_out;
+
+	if (clk->flags & CLK_IGNORE_UNUSED)
+		goto unlock_out;
+
+	if (__clk_is_enabled(clk) && clk->ops->disable)
+		clk->ops->disable(clk->hw);
+
+unlock_out:
+	spin_unlock_irqrestore(&enable_lock, flags);
+
+out:
+	return;
+}
+
+static int clk_disable_unused(void)
+{
+	struct clk *clk;
+	struct hlist_node *tmp;
+
+	mutex_lock(&prepare_lock);
+
+	hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
+		clk_disable_unused_subtree(clk);
+
+	hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
+		clk_disable_unused_subtree(clk);
+
+	mutex_unlock(&prepare_lock);
+
+	return 0;
+}
+late_initcall(clk_disable_unused);
+#else
+static inline int clk_disable_unused(struct clk *clk) { return 0; }
+#endif /* CONFIG_COMMON_CLK_DISABLE_UNUSED */
+
+/***    helper functions   ***/
+
+inline const char *__clk_get_name(struct clk *clk)
+{
+	return !clk ? NULL : clk->name;
+}
+
+inline struct clk_hw *__clk_get_hw(struct clk *clk)
+{
+	return !clk ? NULL : clk->hw;
+}
+
+inline u8 __clk_get_num_parents(struct clk *clk)
+{
+	return !clk ? -EINVAL : clk->num_parents;
+}
+
+inline struct clk *__clk_get_parent(struct clk *clk)
+{
+	return !clk ? NULL : clk->parent;
+}
+
+inline unsigned long __clk_get_enable_count(struct clk *clk)
+{
+	return !clk ? -EINVAL : clk->enable_count;
+}
+
+inline unsigned long __clk_get_prepare_count(struct clk *clk)
+{
+	return !clk ? -EINVAL : clk->prepare_count;
+}
+
+unsigned long __clk_get_rate(struct clk *clk)
+{
+	unsigned long ret;
+
+	if (!clk) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = clk->rate;
+
+	if (clk->flags & CLK_IS_ROOT)
+		goto out;
+
+	if (!clk->parent)
+		ret = -ENODEV;
+
+out:
+	return ret;
+}
+
+inline unsigned long __clk_get_flags(struct clk *clk)
+{
+	return !clk ? -EINVAL : clk->flags;
+}
+
+int __clk_is_enabled(struct clk *clk)
+{
+	int ret;
+
+	if (!clk)
+		return -EINVAL;
+
+	/*
+	 * .is_enabled is only mandatory for clocks that gate
+	 * fall back to software usage counter if .is_enabled is missing
+	 */
+	if (!clk->ops->is_enabled) {
+		ret = clk->enable_count ? 1 : 0;
+		goto out;
+	}
+
+	ret = clk->ops->is_enabled(clk->hw);
+out:
+	return ret;
+}
+
+static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
+{
+	struct clk *child;
+	struct clk *ret;
+	struct hlist_node *tmp;
+
+	if (!strcmp(clk->name, name))
+		return clk;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		ret = __clk_lookup_subtree(name, child);
+		if (ret)
+			return ret;
+	}
+
+	return NULL;
+}
+
+struct clk *__clk_lookup(const char *name)
+{
+	struct clk *root_clk;
+	struct clk *ret;
+	struct hlist_node *tmp;
+
+	/* search the 'proper' clk tree first */
+	hlist_for_each_entry(root_clk, tmp, &clk_root_list, child_node) {
+		ret = __clk_lookup_subtree(name, root_clk);
+		if (ret)
+			return ret;
+	}
+
+	/* if not found, then search the orphan tree */
+	hlist_for_each_entry(root_clk, tmp, &clk_orphan_list, child_node) {
+		ret = __clk_lookup_subtree(name, root_clk);
+		if (ret)
+			return ret;
+	}
+
+	return NULL;
+}
+
+/***        clk api        ***/
+
+void __clk_unprepare(struct clk *clk)
+{
+	if (!clk)
+		return;
+
+	if (WARN_ON(clk->prepare_count == 0))
+		return;
+
+	if (--clk->prepare_count > 0)
+		return;
+
+	WARN_ON(clk->enable_count > 0);
+
+	if (clk->ops->unprepare)
+		clk->ops->unprepare(clk->hw);
+
+	__clk_unprepare(clk->parent);
+}
+
+/**
+ * clk_unprepare - undo preparation of a clock source
+ * @clk: the clk being unprepare
+ *
+ * clk_unprepare may sleep, which differentiates it from clk_disable.  In a
+ * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
+ * if the operation may sleep.  One example is a clk which is accessed over
+ * I2c.  In the complex case a clk gate operation may require a fast and a slow
+ * part.  It is this reason that clk_unprepare and clk_disable are not mutually
+ * exclusive.  In fact clk_disable must be called before clk_unprepare.
+ */
+void clk_unprepare(struct clk *clk)
+{
+	mutex_lock(&prepare_lock);
+	__clk_unprepare(clk);
+	mutex_unlock(&prepare_lock);
+}
+EXPORT_SYMBOL_GPL(clk_unprepare);
+
+int __clk_prepare(struct clk *clk)
+{
+	int ret = 0;
+
+	if (!clk)
+		return 0;
+
+	if (clk->prepare_count == 0) {
+		ret = __clk_prepare(clk->parent);
+		if (ret)
+			return ret;
+
+		if (clk->ops->prepare) {
+			ret = clk->ops->prepare(clk->hw);
+			if (ret) {
+				__clk_unprepare(clk->parent);
+				return ret;
+			}
+		}
+	}
+
+	clk->prepare_count++;
+
+	return 0;
+}
+
+/**
+ * clk_prepare - prepare a clock source
+ * @clk: the clk being prepared
+ *
+ * clk_prepare may sleep, which differentiates it from clk_enable.  In a simple
+ * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
+ * operation may sleep.  One example is a clk which is accessed over I2c.  In
+ * the complex case a clk ungate operation may require a fast and a slow part.
+ * It is this reason that clk_prepare and clk_enable are not mutually
+ * exclusive.  In fact clk_prepare must be called before clk_enable.
+ * Returns 0 on success, -EERROR otherwise.
+ */
+int clk_prepare(struct clk *clk)
+{
+	int ret;
+
+	mutex_lock(&prepare_lock);
+	ret = __clk_prepare(clk);
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_prepare);
+
+static void __clk_disable(struct clk *clk)
+{
+	if (!clk)
+		return;
+
+	if (WARN_ON(clk->enable_count == 0))
+		return;
+
+	if (--clk->enable_count > 0)
+		return;
+
+	if (clk->ops->disable)
+		clk->ops->disable(clk->hw);
+
+	if (clk->parent)
+		__clk_disable(clk->parent);
+}
+
+/**
+ * clk_disable - gate a clock
+ * @clk: the clk being gated
+ *
+ * clk_disable must not sleep, which differentiates it from clk_unprepare.  In
+ * a simple case, clk_disable can be used instead of clk_unprepare to gate a
+ * clk if the operation is fast and will never sleep.  One example is a
+ * SoC-internal clk which is controlled via simple register writes.  In the
+ * complex case a clk gate operation may require a fast and a slow part.  It is
+ * this reason that clk_unprepare and clk_disable are not mutually exclusive.
+ * In fact clk_disable must be called before clk_unprepare.
+ */
+void clk_disable(struct clk *clk)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&enable_lock, flags);
+	__clk_disable(clk);
+	spin_unlock_irqrestore(&enable_lock, flags);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+static int __clk_enable(struct clk *clk)
+{
+	int ret = 0;
+
+	if (!clk)
+		return 0;
+
+	if (WARN_ON(clk->prepare_count == 0))
+		return -ESHUTDOWN;
+
+	if (clk->enable_count == 0) {
+		if (clk->parent)
+			ret = __clk_enable(clk->parent);
+
+		if (ret)
+			return ret;
+
+		if (clk->ops->enable) {
+			ret = clk->ops->enable(clk->hw);
+			if (ret) {
+				__clk_disable(clk->parent);
+				return ret;
+			}
+		}
+	}
+
+	clk->enable_count++;
+	return 0;
+}
+
+/**
+ * clk_enable - ungate a clock
+ * @clk: the clk being ungated
+ *
+ * clk_enable must not sleep, which differentiates it from clk_prepare.  In a
+ * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
+ * if the operation will never sleep.  One example is a SoC-internal clk which
+ * is controlled via simple register writes.  In the complex case a clk ungate
+ * operation may require a fast and a slow part.  It is this reason that
+ * clk_enable and clk_prepare are not mutually exclusive.  In fact clk_prepare
+ * must be called before clk_enable.  Returns 0 on success, -EERROR
+ * otherwise.
+ */
+int clk_enable(struct clk *clk)
+{
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&enable_lock, flags);
+	ret = __clk_enable(clk);
+	spin_unlock_irqrestore(&enable_lock, flags);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+/**
+ * clk_get_rate - return the rate of clk
+ * @clk: the clk whose rate is being returned
+ *
+ * Simply returns the cached rate of the clk.  Does not query the hardware.  If
+ * clk is NULL then returns -EINVAL.
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+	unsigned long rate;
+
+	mutex_lock(&prepare_lock);
+	rate = __clk_get_rate(clk);
+	mutex_unlock(&prepare_lock);
+
+	return rate;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+/**
+ * __clk_round_rate - round the given rate for a clk
+ * @clk: round the rate of this clock
+ *
+ * Caller must hold prepare_lock.  Useful for clk_ops such as .set_rate
+ */
+unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (!clk && !clk->ops->round_rate)
+		return -EINVAL;
+
+	return clk->ops->round_rate(clk->hw, rate, NULL);
+}
+
+/**
+ * clk_round_rate - round the given rate for a clk
+ * @clk: the clk for which we are rounding a rate
+ * @rate: the rate which is to be rounded
+ *
+ * Takes in a rate as input and rounds it to a rate that the clk can actually
+ * use which is then returned.  If clk doesn't support round_rate operation
+ * then the rate passed in is returned.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long ret = rate;
+
+	mutex_lock(&prepare_lock);
+	if (clk && clk->ops->round_rate)
+		ret = __clk_round_rate(clk, rate);
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+/**
+ * __clk_notify - call clk notifier chain
+ * @clk: struct clk * that is changing rate
+ * @msg: clk notifier type (see include/linux/clk.h)
+ * @old_rate: old clk rate
+ * @new_rate: new clk rate
+ *
+ * Triggers a notifier call chain on the clk rate-change notification
+ * for 'clk'.  Passes a pointer to the struct clk and the previous
+ * and current rates to the notifier callback.  Intended to be called by
+ * internal clock code only.  Returns NOTIFY_DONE from the last driver
+ * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
+ * a driver returns that.
+ */
+static int __clk_notify(struct clk *clk, unsigned long msg,
+		unsigned long old_rate, unsigned long new_rate)
+{
+	struct clk_notifier *cn;
+	struct clk_notifier_data cnd;
+	int ret = NOTIFY_DONE;
+
+	cnd.clk = clk;
+	cnd.old_rate = old_rate;
+	cnd.new_rate = new_rate;
+
+	list_for_each_entry(cn, &clk_notifier_list, node) {
+		if (cn->clk == clk) {
+			ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
+					&cnd);
+			break;
+		}
+	}
+
+	return ret;
+}
+
+/**
+ * __clk_recalc_rates
+ * @clk: first clk in the subtree
+ * @msg: notification type (see include/linux/clk.h)
+ *
+ * Walks the subtree of clks starting with clk and recalculates rates as it
+ * goes.  Note that if a clk does not implement the recalc_rate operation then
+ * propagation of that subtree stops and all of that clks children will not
+ * have their rates updated.
+ *
+ * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
+ * if necessary.
+ *
+ * Caller must hold prepare_lock.
+ */
+static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
+{
+	unsigned long old_rate;
+	unsigned long parent_rate = 0;
+	struct hlist_node *tmp;
+	struct clk *child;
+
+	old_rate = clk->rate;
+
+	if (clk->parent)
+		parent_rate = clk->parent->rate;
+
+	if (clk->ops->recalc_rate)
+		clk->rate = clk->ops->recalc_rate(clk->hw, parent_rate);
+	else
+		clk->rate = parent_rate;
+
+	/*
+	 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
+	 * & ABORT_RATE_CHANGE notifiers
+	 */
+	if (clk->notifier_count && msg)
+		__clk_notify(clk, msg, old_rate, clk->rate);
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node)
+		__clk_recalc_rates(child, msg);
+}
+
+/**
+ * __clk_speculate_rates
+ * @clk: first clk in the subtree
+ * @parent_rate: the "future" rate of clk's parent
+ *
+ * Walks the subtree of clks starting with clk, speculating rates as it
+ * goes and firing off PRE_RATE_CHANGE notifications as necessary.
+ *
+ * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
+ * pre-rate change notifications and returns early if no clks in the
+ * subtree have subscribed to the notifications.
+ *
+ * Caller must hold prepare_lock.
+ */
+static int __clk_speculate_rates(struct clk *clk, unsigned long parent_rate)
+{
+	struct hlist_node *tmp;
+	struct clk *child;
+	unsigned long new_rate;
+	int ret = NOTIFY_DONE;
+
+	if (!clk->ops->recalc_rate)
+		goto out;
+
+	new_rate = clk->ops->recalc_rate(clk->hw, parent_rate);
+
+	/* abort the rate change if a driver returns NOTIFY_BAD */
+	if (clk->notifier_count)
+		ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
+
+	if (ret == NOTIFY_BAD)
+		goto out;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		ret = __clk_speculate_rates(child, new_rate);
+		if (ret == NOTIFY_BAD)
+			break;
+	}
+
+out:
+	return ret;
+}
+
+/**
+ * DOC: Using the CLK_SET_RATE_PARENT flag
+ *
+ * __clk_set_rate changes the child's rate before the parent's to more
+ * easily handle failure conditions.
+ *
+ * This means clk might run out of spec for a short time if its rate is
+ * increased before the parent's rate is updated.
+ *
+ * To prevent this consider setting the CLK_SET_RATE_GATE flag on any
+ * clk where you also set the CLK_SET_RATE_PARENT flag
+ *
+ * PRE_RATE_CHANGE notifications are supposed to stack as a rate change
+ * request propagates up the clk tree.  This reflects the different
+ * rates that a downstream clk might experience if left enabled while
+ * upstream parents change their rates.
+ */
+static struct clk *__clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk *fail_clk = NULL;
+	int ret = NOTIFY_DONE;
+	unsigned long old_rate = clk->rate;
+	unsigned long new_rate;
+	unsigned long parent_old_rate;
+	unsigned long parent_new_rate = 0;
+	struct clk *child;
+	struct hlist_node *tmp;
+
+	/* bail early if we can't change rate while clk is enabled */
+	if ((clk->flags & CLK_SET_RATE_GATE) && clk->enable_count)
+		return clk;
+
+	/* find the new rate and see if parent rate should change too */
+	WARN_ON(!clk->ops->round_rate);
+
+	new_rate = clk->ops->round_rate(clk->hw, rate, &parent_new_rate);
+
+	/* NOTE: pre-rate change notifications will stack */
+	if (clk->notifier_count)
+		ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
+
+	if (ret == NOTIFY_BAD)
+		return clk;
+
+	/* speculate rate changes down the tree */
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		ret = __clk_speculate_rates(child, new_rate);
+		if (ret == NOTIFY_BAD)
+			return clk;
+	}
+
+	/* change the rate of this clk */
+	if (clk->ops->set_rate)
+		ret = clk->ops->set_rate(clk->hw, new_rate);
+
+	if (ret == NOTIFY_BAD)
+		return clk;
+
+	/*
+	 * change the rate of the parent clk if necessary
+	 *
+	 * hitting the nested 'if' path implies we have hit a .set_rate
+	 * failure somewhere upstream while propagating __clk_set_rate
+	 * up the clk tree.  roll back the clk rates one by one and
+	 * return the pointer to the clk that failed.  clk_set_rate will
+	 * use the pointer to propagate a rate-change abort notifier
+	 * from the "highest" point.
+	 */
+	if ((clk->flags & CLK_SET_RATE_PARENT) && parent_new_rate) {
+		parent_old_rate = clk->parent->rate;
+		fail_clk = __clk_set_rate(clk->parent, parent_new_rate);
+
+		/* roll back changes if parent rate change failed */
+		if (fail_clk) {
+			pr_warn("%s: failed to set parent %s rate to %lu\n",
+					__func__, fail_clk->name,
+					parent_new_rate);
+
+			/*
+			 * Send PRE_RATE_CHANGE notifiers down the tree
+			 * again, since we're rolling back the rate
+			 * changes due to the abort.
+			 *
+			 * Ignore any NOTIFY_BAD's since this *is* the
+			 * exception handler.
+			 *
+			 * NOTE: pre-rate change notifications will stack
+			 */
+			__clk_speculate_rates(clk, clk->parent->rate);
+
+			clk->ops->set_rate(clk->hw, old_rate);
+		}
+		return fail_clk;
+	}
+
+	/*
+	 * set clk's rate & recalculate the rates of clk's children
+	 *
+	 * hitting this path implies we have successfully finished
+	 * propagating recursive calls to __clk_set_rate up the clk tree
+	 * (if necessary) and it is safe to propagate __clk_recalc_rates
+	 * and post-rate change notifiers down the clk tree from this
+	 * point.
+	 */
+	__clk_recalc_rates(clk, POST_RATE_CHANGE);
+
+	return NULL;
+}
+
+/**
+ * clk_set_rate - specify a new rate for clk
+ * @clk: the clk whose rate is being changed
+ * @rate: the new rate for clk
+ *
+ * In the simplest case clk_set_rate will only change the rate of clk.
+ *
+ * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call
+ * will fail; only when the clk is disabled will it be able to change
+ * its rate.
+ *
+ * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to
+ * recursively propagate up to clk's parent; whether or not this happens
+ * depends on the outcome of clk's .round_rate implementation.  If
+ * *parent_rate is 0 after calling .round_rate then upstream parent
+ * propagation is ignored.  If *parent_rate comes back with a new rate
+ * for clk's parent then we propagate up to clk's parent and set it's
+ * rate.  Upward propagation will continue until either a clk does not
+ * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting
+ * changes to clk's parent_rate.  If there is a failure during upstream
+ * propagation then clk_set_rate will unwind and restore each clk's rate
+ * that had been successfully changed.  Afterwards a rate change abort
+ * notification will be propagated downstream, starting from the clk
+ * that failed.
+ *
+ * At the end of all of the rate setting, clk_set_rate internally calls
+ * __clk_recalc_rates and propagates the rate changes downstream,
+ * starting from the highest clk whose rate was changed.  This has the
+ * added benefit of propagating post-rate change notifiers.
+ *
+ * Note that while post-rate change and rate change abort notifications
+ * are guaranteed to be sent to a clk only once per call to
+ * clk_set_rate, pre-change notifications will be sent for every clk
+ * whose rate is changed.  Stacking pre-change notifications is noisy
+ * for the drivers subscribed to them, but this allows drivers to react
+ * to intermediate clk rate changes up until the point where the final
+ * rate is achieved at the end of upstream propagation.
+ *
+ * Returns 0 on success, -EERROR otherwise.
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk *fail_clk;
+	int ret = 0;
+
+	/* prevent racing with updates to the clock topology */
+	mutex_lock(&prepare_lock);
+
+	/* bail early if nothing to do */
+	if (rate == clk->rate)
+		goto out;
+
+	fail_clk = __clk_set_rate(clk, rate);
+	if (fail_clk) {
+		pr_warn("%s: failed to set %s rate\n", __func__,
+				fail_clk->name);
+		__clk_recalc_rates(clk, ABORT_RATE_CHANGE);
+		ret = -EIO;
+	}
+
+out:
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+/**
+ * clk_get_parent - return the parent of a clk
+ * @clk: the clk whose parent gets returned
+ *
+ * Simply returns clk->parent.  Returns NULL if clk is NULL.
+ */
+struct clk *clk_get_parent(struct clk *clk)
+{
+	struct clk *parent;
+
+	mutex_lock(&prepare_lock);
+	parent = __clk_get_parent(clk);
+	mutex_unlock(&prepare_lock);
+
+	return parent;
+}
+EXPORT_SYMBOL_GPL(clk_get_parent);
+
+/*
+ * .get_parent is mandatory for clocks with multiple possible parents.  It is
+ * optional for single-parent clocks.  Always call .get_parent if it is
+ * available and WARN if it is missing for multi-parent clocks.
+ *
+ * For single-parent clocks without .get_parent, first check to see if the
+ * .parents array exists, and if so use it to avoid an expensive tree
+ * traversal.  If .parents does not exist then walk the tree with __clk_lookup.
+ */
+static struct clk *__clk_init_parent(struct clk *clk)
+{
+	struct clk *ret = NULL;
+	u8 index;
+
+	/* handle the trivial cases */
+
+	if (!clk->num_parents)
+		goto out;
+
+	if (clk->num_parents == 1) {
+		if (IS_ERR_OR_NULL(clk->parent))
+			ret = clk->parent = __clk_lookup(clk->parent_names[0]);
+		ret = clk->parent;
+		goto out;
+	}
+
+	if (!clk->ops->get_parent) {
+		WARN(!clk->ops->get_parent,
+			"%s: multi-parent clocks must implement .get_parent\n",
+			__func__);
+		goto out;
+	};
+
+	/*
+	 * Do our best to cache parent clocks in clk->parents.  This prevents
+	 * unnecessary and expensive calls to __clk_lookup.  We don't set
+	 * clk->parent here; that is done by the calling function
+	 */
+
+	index = clk->ops->get_parent(clk->hw);
+
+	if (!clk->parents)
+		clk->parents =
+			kmalloc((sizeof(struct clk*) * clk->num_parents),
+					GFP_KERNEL);
+
+	if (!clk->parents)
+		ret = __clk_lookup(clk->parent_names[index]);
+	else if (!clk->parents[index])
+		ret = clk->parents[index] =
+			__clk_lookup(clk->parent_names[index]);
+	else
+		ret = clk->parents[index];
+
+out:
+	return ret;
+}
+
+void __clk_reparent(struct clk *clk, struct clk *new_parent)
+{
+#ifdef CONFIG_COMMON_CLK_DEBUG
+	struct dentry *d;
+	struct dentry *new_parent_d;
+#endif
+
+	if (!clk || !new_parent)
+		return;
+
+	hlist_del(&clk->child_node);
+
+	if (new_parent)
+		hlist_add_head(&clk->child_node, &new_parent->children);
+	else
+		hlist_add_head(&clk->child_node, &clk_orphan_list);
+
+#ifdef CONFIG_COMMON_CLK_DEBUG
+	if (!inited)
+		goto out;
+
+	if (new_parent)
+		new_parent_d = new_parent->dentry;
+	else
+		new_parent_d = orphandir;
+
+	d = debugfs_rename(clk->dentry->d_parent, clk->dentry,
+			new_parent_d, clk->name);
+	if (d)
+		clk->dentry = d;
+	else
+		pr_debug("%s: failed to rename debugfs entry for %s\n",
+				__func__, clk->name);
+out:
+#endif
+
+	clk->parent = new_parent;
+
+	__clk_recalc_rates(clk, POST_RATE_CHANGE);
+}
+
+static int __clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct clk *old_parent;
+	unsigned long flags;
+	int ret = -EINVAL;
+	u8 i;
+
+	old_parent = clk->parent;
+
+	/* find index of new parent clock using cached parent ptrs */
+	for (i = 0; i < clk->num_parents; i++)
+		if (clk->parents[i] == parent)
+			break;
+
+	/*
+	 * find index of new parent clock using string name comparison
+	 * also try to cache the parent to avoid future calls to __clk_lookup
+	 */
+	if (i == clk->num_parents)
+		for (i = 0; i < clk->num_parents; i++)
+			if (!strcmp(clk->parent_names[i], parent->name)) {
+				clk->parents[i] = __clk_lookup(parent->name);
+				break;
+			}
+
+	if (i == clk->num_parents) {
+		pr_debug("%s: clock %s is not a possible parent of clock %s\n",
+				__func__, parent->name, clk->name);
+		goto out;
+	}
+
+	/* migrate prepare and enable */
+	if (clk->prepare_count)
+		__clk_prepare(parent);
+
+	/* FIXME replace with clk_is_enabled(clk) someday */
+	spin_lock_irqsave(&enable_lock, flags);
+	if (clk->enable_count)
+		__clk_enable(parent);
+	spin_unlock_irqrestore(&enable_lock, flags);
+
+	/* change clock input source */
+	ret = clk->ops->set_parent(clk->hw, i);
+
+	/* clean up old prepare and enable */
+	spin_lock_irqsave(&enable_lock, flags);
+	if (clk->enable_count)
+		__clk_disable(old_parent);
+	spin_unlock_irqrestore(&enable_lock, flags);
+
+	if (clk->prepare_count)
+		__clk_unprepare(old_parent);
+
+out:
+	return ret;
+}
+
+/**
+ * clk_set_parent - switch the parent of a mux clk
+ * @clk: the mux clk whose input we are switching
+ * @parent: the new input to clk
+ *
+ * Re-parent clk to use parent as it's new input source.  If clk has the
+ * CLK_SET_PARENT_GATE flag set then clk must be gated for this
+ * operation to succeed.  After successfully changing clk's parent
+ * clk_set_parent will update the clk topology, sysfs topology and
+ * propagate rate recalculation via __clk_recalc_rates.  Returns 0 on
+ * success, -EERROR otherwise.
+ */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	int ret = 0;
+
+	if (!clk || !clk->ops)
+		return -EINVAL;
+
+	if (!clk->ops->set_parent)
+		return -ENOSYS;
+
+	/* prevent racing with updates to the clock topology */
+	mutex_lock(&prepare_lock);
+
+	if (clk->parent == parent)
+		goto out;
+
+	/* propagate PRE_RATE_CHANGE notifications */
+	if (clk->notifier_count)
+		ret = __clk_speculate_rates(clk, parent->rate);
+
+	/* abort if a driver objects */
+	if (ret == NOTIFY_STOP)
+		goto out;
+
+	/* only re-parent if the clock is not in use */
+	if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count)
+		ret = -EBUSY;
+	else
+		ret = __clk_set_parent(clk, parent);
+
+	/* propagate ABORT_RATE_CHANGE if .set_parent failed */
+	if (ret) {
+		__clk_recalc_rates(clk, ABORT_RATE_CHANGE);
+		goto out;
+	}
+
+	/* propagate rate recalculation downstream */
+	__clk_reparent(clk, parent);
+
+out:
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+/**
+ * __clk_init - initialize the data structures in a struct clk
+ * @dev:	device initializing this clk, placeholder for now
+ * @clk:	clk being initialized
+ *
+ * Initializes the lists in struct clk, queries the hardware for the
+ * parent and rate and sets them both.
+ *
+ * Any struct clk passed into __clk_init must have the following members
+ * populated:
+ * 	.name
+ * 	.ops
+ * 	.hw
+ * 	.parent_names
+ * 	.num_parents
+ * 	.flags
+ *
+ * Essentially, everything that would normally be passed into clk_register is
+ * assumed to be initialized already in __clk_init.  The other members may be
+ * populated, but are optional.
+ *
+ * __clk_init is only exposed via clk-private.h and is intended for use with
+ * very large numbers of clocks that need to be statically initialized.  It is
+ * a layering violation to include clk-private.h from any code which implements
+ * a clock's .ops; as such any statically initialized clock data MUST be in a
+ * separate C file from the logic that implements it's operations.
+ */
+void __clk_init(struct device *dev, struct clk *clk)
+{
+	int i;
+	struct clk *orphan;
+	struct hlist_node *tmp;
+
+	if (!clk)
+		return;
+
+	mutex_lock(&prepare_lock);
+
+	/* check to see if a clock with this name is already registered */
+	if (__clk_lookup(clk->name))
+		goto out;
+
+	/*
+	 * Allocate an array of struct clk *'s to avoid unnecessary string
+	 * look-ups of clk's possible parents.  This can fail for clocks passed
+	 * in to clk_init during early boot; thus any access to clk->parents[]
+	 * must always check for a NULL pointer and try to populate it if
+	 * necessary.
+	 *
+	 * If clk->parents is not NULL we skip this entire block.  This allows
+	 * for clock drivers to statically initialize clk->parents.
+	 */
+	if (clk->num_parents && !clk->parents) {
+		clk->parents = kmalloc((sizeof(struct clk*) * clk->num_parents),
+				GFP_KERNEL);
+		/*
+		 * __clk_lookup returns NULL for parents that have not been
+		 * clk_init'd; thus any access to clk->parents[] must check
+		 * for a NULL pointer.  We can always perform lazy lookups for
+		 * missing parents later on.
+		 */
+		if (clk->parents)
+			for (i = 0; i < clk->num_parents; i++)
+				clk->parents[i] =
+					__clk_lookup(clk->parent_names[i]);
+	}
+
+	clk->parent = __clk_init_parent(clk);
+
+	/*
+	 * Populate clk->parent if parent has already been __clk_init'd.  If
+	 * parent has not yet been __clk_init'd then place clk in the orphan
+	 * list.  If clk has set the CLK_IS_ROOT flag then place it in the root
+	 * clk list.
+	 *
+	 * Every time a new clk is clk_init'd then we walk the list of orphan
+	 * clocks and re-parent any that are children of the clock currently
+	 * being clk_init'd.
+	 */
+	if (clk->parent)
+		hlist_add_head(&clk->child_node,
+				&clk->parent->children);
+	else if (clk->flags & CLK_IS_ROOT)
+		hlist_add_head(&clk->child_node, &clk_root_list);
+	else
+		hlist_add_head(&clk->child_node, &clk_orphan_list);
+
+	/*
+	 * Set clk's rate.  The preferred method is to use .recalc_rate.  For
+	 * simple clocks and lazy developers the default fallback is to use the
+	 * parent's rate.  If a clock doesn't have a parent (or is orphaned)
+	 * then rate is set to zero.
+	 */
+	if (clk->ops->recalc_rate)
+		clk->rate = clk->ops->recalc_rate(clk->hw,
+				__clk_get_rate(clk->parent));
+	else if (clk->parent)
+		clk->rate = clk->parent->rate;
+	else
+		clk->rate = 0;
+
+	/*
+	 * walk the list of orphan clocks and reparent any that are children of
+	 * this clock
+	 */
+	hlist_for_each_entry(orphan, tmp, &clk_orphan_list, child_node)
+		__clk_reparent(orphan, __clk_init_parent(orphan));
+
+	/*
+	 * optional platform-specific magic
+	 *
+	 * The .init callback is not used by any of the basic clock types, but
+	 * exists for weird hardware that must perform initialization magic.
+	 * Please consider other ways of solving initialization problems before
+	 * using this callback, as it's use is discouraged.
+	 */
+	if (clk->ops->init)
+		clk->ops->init(clk->hw);
+
+	clk_debug_register(clk);
+
+out:
+	mutex_unlock(&prepare_lock);
+
+	return;
+}
+
+/**
+ * clk_register - allocate a new clock, register it and return an opaque cookie
+ * @dev: device that is registering this clock
+ * @name: clock name
+ * @ops: operations this clock supports
+ * @hw: link to hardware-specific clock data
+ * @parent_names: array of string names for all possible parents
+ * @num_parents: number of possible parents
+ * @flags: framework-level hints and quirks
+ *
+ * clk_register is the primary interface for populating the clock tree with new
+ * clock nodes.  It returns a pointer to the newly allocated struct clk which
+ * cannot be dereferenced by driver code but may be used in conjuction with the
+ * rest of the clock API.
+ */
+struct clk *clk_register(struct device *dev, const char *name,
+		const struct clk_ops *ops, struct clk_hw *hw,
+		char **parent_names, u8 num_parents, unsigned long flags)
+{
+	struct clk *clk;
+
+	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+	if (!clk)
+		return NULL;
+
+	clk->name = name;
+	clk->ops = ops;
+	clk->hw = hw;
+	clk->flags = flags;
+	clk->parent_names = parent_names;
+	clk->num_parents = num_parents;
+	hw->clk = clk;
+
+	__clk_init(dev, clk);
+
+	return clk;
+}
+EXPORT_SYMBOL_GPL(clk_register);
+
+/***        clk rate change notifiers        ***/
+
+/**
+ * clk_notifier_register - add a clk rate change notifier
+ * @clk: struct clk * to watch
+ * @nb: struct notifier_block * with callback info
+ *
+ * Request notification when clk's rate changes.  This uses an SRCU
+ * notifier because we want it to block and notifier unregistrations are
+ * uncommon.  The callbacks associated with the notifier must not
+ * re-enter into the clk framework by calling any top-level clk APIs;
+ * this will cause a nested prepare_lock mutex.
+ *
+ * Pre-change notifier callbacks will be passed the current, pre-change
+ * rate of the clk via struct clk_notifier_data.old_rate.  The new,
+ * post-change rate of the clk is passed via struct
+ * clk_notifier.new_rate.
+ *
+ * Post-change notifiers will pass the now-current, post-change rate of
+ * the clk in both struct clk_notifier_data.old_rate and struct
+ * clk_notifier_data.new_rate.
+ *
+ * Abort-change notifiers are effectively the opposite of pre-change
+ * notifiers: the original pre-change clk rate is passed in via struct
+ * clk_notifier_data.new_rate and the failed post-change rate is passed
+ * in via struct clk_notifier_data.old_rate.
+ *
+ * clk_notifier_register() must be called from non-atomic context.
+ * Returns -EINVAL if called with null arguments, -ENOMEM upon
+ * allocation failure; otherwise, passes along the return value of
+ * srcu_notifier_chain_register().
+ */
+int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
+{
+	struct clk_notifier *cn;
+	int ret = -ENOMEM;
+
+	if (!clk || !nb)
+		return -EINVAL;
+
+	mutex_lock(&prepare_lock);
+
+	/* search the list of notifiers for this clk */
+	list_for_each_entry(cn, &clk_notifier_list, node)
+		if (cn->clk == clk)
+			break;
+
+	/* if clk wasn't in the notifier list, allocate new clk_notifier */
+	if (cn->clk != clk) {
+		cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
+		if (!cn)
+			goto out;
+
+		cn->clk = clk;
+		srcu_init_notifier_head(&cn->notifier_head);
+
+		list_add(&cn->node, &clk_notifier_list);
+	}
+
+	ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
+
+	clk->notifier_count++;
+
+out:
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_notifier_register);
+
+/**
+ * clk_notifier_unregister - remove a clk rate change notifier
+ * @clk: struct clk *
+ * @nb: struct notifier_block * with callback info
+ *
+ * Request no further notification for changes to 'clk' and frees memory
+ * allocated in clk_notifier_register.
+ *
+ * Returns -EINVAL if called with null arguments; otherwise, passes
+ * along the return value of srcu_notifier_chain_unregister().
+ */
+int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
+{
+	struct clk_notifier *cn = NULL;
+	int ret = -EINVAL;
+
+	if (!clk || !nb)
+		return -EINVAL;
+
+	mutex_lock(&prepare_lock);
+
+	list_for_each_entry(cn, &clk_notifier_list, node)
+		if (cn->clk == clk)
+			break;
+
+	if (cn->clk == clk) {
+		ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
+
+		clk->notifier_count--;
+
+		/* XXX the notifier code should handle this better */
+		if (!cn->notifier_head.head) {
+			srcu_cleanup_notifier_head(&cn->notifier_head);
+			kfree(cn);
+		}
+
+	} else {
+		ret = -ENOENT;
+	}
+
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_notifier_unregister);
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
new file mode 100644
index 0000000..33bf6a7
--- /dev/null
+++ b/include/linux/clk-private.h
@@ -0,0 +1,68 @@
+/*
+ *  linux/include/linux/clk-private.h
+ *
+ *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr at canonical.com>
+ *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_CLK_PRIVATE_H
+#define __LINUX_CLK_PRIVATE_H
+
+#include <linux/clk-provider.h>
+#include <linux/list.h>
+
+/*
+ * WARNING: Do not include clk-private.h from any file that implements struct
+ * clk_ops.  Doing so is a layering violation!
+ *
+ * This header exists only to allow for statically initialized clock data.  Any
+ * static clock data must be defined in a separate file from the logic that
+ * implements the clock operations for that same data.
+ */
+
+#ifdef CONFIG_COMMON_CLK
+
+struct clk {
+	const char		*name;
+	const struct clk_ops	*ops;
+	struct clk_hw		*hw;
+	struct clk		*parent;
+	char			**parent_names;
+	struct clk		**parents;
+	u8			num_parents;
+	unsigned long		rate;
+	unsigned long		flags;
+	unsigned int		enable_count;
+	unsigned int		prepare_count;
+	struct hlist_head	children;
+	struct hlist_node	child_node;
+	unsigned int		notifier_count;
+#ifdef CONFIG_COMMON_CLK_DEBUG
+	struct dentry		*dentry;
+#endif
+};
+
+/**
+ * __clk_init - initialize the data structures in a struct clk
+ * @dev:	device initializing this clk, placeholder for now
+ * @clk:	clk being initialized
+ *
+ * Initializes the lists in struct clk, queries the hardware for the
+ * parent and rate and sets them both.
+ *
+ * Any struct clk passed into __clk_init must have the following members
+ * populated:
+ * 	.name
+ * 	.ops
+ * 	.hw
+ * 	.parent_names
+ * 	.num_parents
+ * 	.flags
+ */
+void __clk_init(struct device *dev, struct clk *clk);
+
+#endif /* CONFIG_COMMON_CLK */
+#endif /* CLK_PRIVATE_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
new file mode 100644
index 0000000..09dea1f
--- /dev/null
+++ b/include/linux/clk-provider.h
@@ -0,0 +1,171 @@
+/*
+ *  linux/include/linux/clk-provider.h
+ *
+ *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr at canonical.com>
+ *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_CLK_PROVIDER_H
+#define __LINUX_CLK_PROVIDER_H
+
+#include <linux/clk.h>
+
+#ifdef CONFIG_COMMON_CLK
+
+/**
+ * struct clk_hw - handle for traversing from a struct clk to its corresponding
+ * hardware-specific structure.  struct clk_hw should be declared within struct
+ * clk_foo and then referenced by the struct clk instance that uses struct
+ * clk_foo's clk_ops
+ *
+ * clk: pointer to the struct clk instance that points back to this struct
+ * clk_hw instance
+ */
+struct clk_hw {
+	struct clk *clk;
+};
+
+/*
+ * flags used across common struct clk.  these flags should only affect the
+ * top-level framework.  custom flags for dealing with hardware specifics
+ * belong in struct clk_foo
+ */
+#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
+#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
+#define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
+#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
+#define CLK_IS_ROOT		BIT(4) /* root clk, has no parent */
+
+/**
+ * struct clk_ops -  Callback operations for hardware clocks; these are to
+ * be provided by the clock implementation, and will be called by drivers
+ * through the clk_* api.
+ *
+ * @prepare:	Prepare the clock for enabling. This must not return until
+ * 		the clock is fully prepared, and it's safe to call clk_enable.
+ * 		This callback is intended to allow clock implementations to
+ * 		do any initialisation that may sleep. Called with
+ * 		prepare_lock held.
+ *
+ * @unprepare:	Release the clock from its prepared state. This will typically
+ * 		undo any work done in the @prepare callback. Called with
+ * 		prepare_lock held.
+ *
+ * @enable:	Enable the clock atomically. This must not return until the
+ * 		clock is generating a valid clock signal, usable by consumer
+ * 		devices. Called with enable_lock held. This function must not
+ * 		sleep.
+ *
+ * @disable:	Disable the clock atomically. Called with enable_lock held.
+ * 		This function must not sleep.
+ *
+ * @recalc_rate	Recalculate the rate of this clock, by quering hardware.  The
+ * 		parent rate is an input parameter.  It is up to the caller to
+ * 		insure that the prepare_mutex is held across this call.
+ * 		Returns the calculated rate.  Optional, but recommended - if
+ * 		this op is not set then clock rate will be initialized to 0.
+ *
+ * @round_rate:	Given a target rate as input, returns the closest rate actually
+ * 		supported by the clock.
+ *
+ * @get_parent:	Queries the hardware to determine the parent of a clock.  The
+ * 		return value is a u8 which specifies the index corresponding to
+ * 		the parent clock.  This index can be applied to either the
+ * 		.parent_names or .parents arrays.  In short, this function
+ * 		translates the parent value read from hardware into an array
+ * 		index.  Currently only called when the clock is initialized by
+ * 		__clk_init.  This callback is mandatory for clocks with
+ * 		multiple parents.  It is optional (and unnecessary) for clocks
+ * 		with 0 or 1 parents.
+ *
+ * @set_parent:	Change the input source of this clock; for clocks with multiple
+ * 		possible parents specify a new parent by passing in the index
+ * 		as a u8 corresponding to the parent in either the .parent_names
+ * 		or .parents arrays.  This function in affect translates an
+ * 		array index into the value programmed into the hardware.
+ * 		Returns 0 on success, -EERROR otherwise.
+ *
+ * @set_rate:	Change the rate of this clock. If this callback returns
+ * 		CLK_SET_RATE_PARENT, the rate change will be propagated to the
+ * 		parent clock (which may propagate again if the parent clock
+ * 		also sets this flag). The requested rate of the parent is
+ * 		passed back from the callback in the second 'unsigned long *'
+ * 		argument.  Note that it is up to the hardware clock's set_rate
+ * 		implementation to insure that clocks do not run out of spec
+ * 		when propgating the call to set_rate up to the parent.  One way
+ * 		to do this is to gate the clock (via clk_disable and/or
+ * 		clk_unprepare) before calling clk_set_rate, then ungating it
+ * 		afterward.  If your clock also has the CLK_GATE_SET_RATE flag
+ * 		set then this will insure safety.  Returns 0 on success,
+ * 		-EERROR otherwise.
+ *
+ * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
+ * implementations to split any work between atomic (enable) and sleepable
+ * (prepare) contexts.  If enabling a clock requires code that might sleep,
+ * this must be done in clk_prepare.  Clock enable code that will never be
+ * called in a sleepable context may be implement in clk_enable.
+ *
+ * Typically, drivers will call clk_prepare when a clock may be needed later
+ * (eg. when a device is opened), and clk_enable when the clock is actually
+ * required (eg. from an interrupt). Note that clk_prepare MUST have been
+ * called before clk_enable.
+ */
+struct clk_ops {
+	int		(*prepare)(struct clk_hw *hw);
+	void		(*unprepare)(struct clk_hw *hw);
+	int		(*enable)(struct clk_hw *hw);
+	void		(*disable)(struct clk_hw *hw);
+	int		(*is_enabled)(struct clk_hw *hw);
+	unsigned long	(*recalc_rate)(struct clk_hw *hw,
+					unsigned long parent_rate);
+	long		(*round_rate)(struct clk_hw *hw, unsigned long,
+					unsigned long *);
+	int		(*set_parent)(struct clk_hw *hw, u8 index);
+	u8		(*get_parent)(struct clk_hw *hw);
+	int		(*set_rate)(struct clk_hw *hw, unsigned long);
+	void		(*init)(struct clk_hw *hw);
+};
+
+
+/**
+ * clk_register - allocate a new clock, register it and return an opaque cookie
+ * @dev: device that is registering this clock
+ * @name: clock name
+ * @ops: operations this clock supports
+ * @hw: link to hardware-specific clock data
+ * @parent_names: array of string names for all possible parents
+ * @num_parents: number of possible parents
+ * @flags: framework-level hints and quirks
+ *
+ * clk_register is the primary interface for populating the clock tree with new
+ * clock nodes.  It returns a pointer to the newly allocated struct clk which
+ * cannot be dereferenced by driver code but may be used in conjuction with the
+ * rest of the clock API.
+ */
+struct clk *clk_register(struct device *dev, const char *name,
+		const struct clk_ops *ops, struct clk_hw *hw,
+		char **parent_names, u8 num_parents, unsigned long flags);
+
+/* helper functions */
+const char *__clk_get_name(struct clk *clk);
+struct clk_hw *__clk_get_hw(struct clk *clk);
+u8 __clk_get_num_parents(struct clk *clk);
+struct clk *__clk_get_parent(struct clk *clk);
+unsigned long __clk_get_rate(struct clk *clk);
+unsigned long __clk_get_flags(struct clk *clk);
+int __clk_is_enabled(struct clk *clk);
+struct clk *__clk_lookup(const char *name);
+
+/*
+ * FIXME clock api without lock protection
+ */
+int __clk_prepare(struct clk *clk);
+void __clk_unprepare(struct clk *clk);
+void __clk_reparent(struct clk *clk, struct clk *new_parent);
+unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
+
+#endif /* CONFIG_COMMON_CLK */
+#endif /* CLK_PROVIDER_H */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index b9d46fa..b025272 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -3,6 +3,7 @@
  *
  *  Copyright (C) 2004 ARM Limited.
  *  Written by Deep Blue Solutions Limited.
+ *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,18 +13,75 @@
 #define __LINUX_CLK_H
 
 #include <linux/kernel.h>
+#include <linux/notifier.h>
 
 struct device;
 
-/*
- * The base API.
+struct clk;
+
+#ifdef CONFIG_COMMON_CLK
+
+/**
+ * DOC: clk notifier callback types
+ *
+ * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
+ *     to indicate that the rate change will proceed.  Drivers must
+ *     immediately terminate any operations that will be affected by the
+ *     rate change.  Callbacks may either return NOTIFY_DONE or
+ *     NOTIFY_STOP.
+ *
+ * ABORT_RATE_CHANGE: called if the rate change failed for some reason
+ *     after PRE_RATE_CHANGE.  In this case, all registered notifiers on
+ *     the clk will be called with ABORT_RATE_CHANGE. Callbacks must
+ *     always return NOTIFY_DONE.
+ *
+ * POST_RATE_CHANGE - called after the clk rate change has successfully
+ *     completed.  Callbacks must always return NOTIFY_DONE.
+ *
  */
+#define PRE_RATE_CHANGE			BIT(0)
+#define POST_RATE_CHANGE		BIT(1)
+#define ABORT_RATE_CHANGE		BIT(2)
 
+/**
+ * struct clk_notifier - associate a clk with a notifier
+ * @clk: struct clk * to associate the notifier with
+ * @notifier_head: a blocking_notifier_head for this clk
+ * @node: linked list pointers
+ *
+ * A list of struct clk_notifier is maintained by the notifier code.
+ * An entry is created whenever code registers the first notifier on a
+ * particular @clk.  Future notifiers on that @clk are added to the
+ * @notifier_head.
+ */
+struct clk_notifier {
+	struct clk			*clk;
+	struct srcu_notifier_head	notifier_head;
+	struct list_head		node;
+};
 
-/*
- * struct clk - an machine class defined object / cookie.
+/**
+ * struct clk_notifier_data - rate data to pass to the notifier callback
+ * @clk: struct clk * being changed
+ * @old_rate: previous rate of this clk
+ * @new_rate: new rate of this clk
+ *
+ * For a pre-notifier, old_rate is the clk's rate before this rate
+ * change, and new_rate is what the rate will be in the future.  For a
+ * post-notifier, old_rate and new_rate are both set to the clk's
+ * current rate (this was done to optimize the implementation).
  */
-struct clk;
+struct clk_notifier_data {
+	struct clk		*clk;
+	unsigned long		old_rate;
+	unsigned long		new_rate;
+};
+
+int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
+
+int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
+
+#endif /* !CONFIG_COMMON_CLK */
 
 /**
  * clk_get - lookup and obtain a reference to a clock producer.
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar 12 07:58:48 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 12 Mar 2012 19:58:48 +0800
Subject: [PATCH v4 01/10] ASoC: fsl: separate SSI and DMA Kconfig options
In-Reply-To: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331553537-19789-2-git-send-email-shawn.guo@linaro.org>

The fsl_ssi driver will possibly be shared between Freescale PowerPC
and ARM/IMX families, so give it a separate Kconfig option.  Then
fsl_ssi driver can possibly be selected independently from selecting
PowerPC DMA based PCM driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/Kconfig  |   15 +++++++++------
 sound/soc/fsl/Makefile |    3 ++-
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index d754d34..ca693b2 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,10 +1,11 @@
 config SND_MPC52xx_DMA
 	tristate
 
-# ASoC platform support for the Freescale PowerPC SOCs that have an SSI and
-# an Elo DMA controller, such as the MPC8610 and P1022.  You will still need to
-# select a platform driver and a codec driver.
-config SND_SOC_POWERPC_SSI
+config SND_SOC_FSL_SSI
+	tristate
+	depends on FSL_SOC
+
+config SND_SOC_POWERPC_DMA
 	tristate
 	depends on FSL_SOC
 
@@ -12,7 +13,8 @@ config SND_SOC_MPC8610_HPCD
 	tristate "ALSA SoC support for the Freescale MPC8610 HPCD board"
 	# I2C is necessary for the CS4270 driver
 	depends on MPC8610_HPCD && I2C
-	select SND_SOC_POWERPC_SSI
+	select SND_SOC_FSL_SSI
+	select SND_SOC_POWERPC_DMA
 	select SND_SOC_CS4270
 	select SND_SOC_CS4270_VD33_ERRATA
 	default y if MPC8610_HPCD
@@ -23,7 +25,8 @@ config SND_SOC_P1022_DS
 	tristate "ALSA SoC support for the Freescale P1022 DS board"
 	# I2C is necessary for the WM8776 driver
 	depends on P1022_DS && I2C
-	select SND_SOC_POWERPC_SSI
+	select SND_SOC_FSL_SSI
+	select SND_SOC_POWERPC_DMA
 	select SND_SOC_WM8776
 	default y if P1022_DS
 	help
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index b4a38c0..95d483f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -9,7 +9,8 @@ obj-$(CONFIG_SND_SOC_P1022_DS) += snd-soc-p1022-ds.o
 # Freescale PowerPC SSI/DMA Platform Support
 snd-soc-fsl-ssi-objs := fsl_ssi.o
 snd-soc-fsl-dma-objs := fsl_dma.o
-obj-$(CONFIG_SND_SOC_POWERPC_SSI) += snd-soc-fsl-ssi.o snd-soc-fsl-dma.o
+obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 
 # MPC5200 Platform Support
 obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
-- 
1.7.5.4



From kgene.kim at samsung.com  Sat Mar 10 05:19:09 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 02:19:09 -0800
Subject: [PATCH 5/5] ARM: EXYNOS: add clock registers for exynos4x12-cpufreq
In-Reply-To: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>
References: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331374749-23256-6-git-send-email-kgene.kim@samsung.com>

From: Jaecheol Lee <jc.lee at samsung.com>

Signed-off-by: Jaecheol Lee <jc.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/include/mach/regs-clock.h |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 790f525..b1a2aeb 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -160,6 +160,15 @@
 #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK	(0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
 #define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT		(24)
 #define EXYNOS4_CLKDIV_CPU0_APLL_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT		28
+#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
+
+#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT		0
+#define EXYNOS4_CLKDIV_CPU1_COPY_MASK		(0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT		4
+#define EXYNOS4_CLKDIV_CPU1_HPM_MASK		(0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT		8
+#define EXYNOS4_CLKDIV_CPU1_CORES_MASK		(0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
 
 #define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT		(0)
 #define EXYNOS4_CLKDIV_DMC0_ACP_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
-- 
1.7.4.4



From kgene.kim at samsung.com  Sat Mar 10 05:19:05 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 02:19:05 -0800
Subject: [PATCH 1/5] ARM: EXYNOS: replace clock.c for other new EXYNOS SoCs
In-Reply-To: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>
References: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331374749-23256-2-git-send-email-kgene.kim@samsung.com>

This patch changes the name of clock.c to clock-exynos4.c for other
EXYNOS series such as EXYNOS5. And since the header file of clock
is used only in arch/arm/mach-exynos, moves it in the local directory.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/Makefile                      |    3 +-
 arch/arm/mach-exynos/{clock.c => clock-exynos4.c}  |  173 ++++++++++----------
 .../mach/exynos4-clock.h => clock-exynos4.h}       |    1 -
 arch/arm/mach-exynos/clock-exynos4210.c            |    2 +-
 arch/arm/mach-exynos/clock-exynos4212.c            |    2 +-
 5 files changed, 90 insertions(+), 91 deletions(-)
 rename arch/arm/mach-exynos/{clock.c => clock-exynos4.c} (92%)
 rename arch/arm/mach-exynos/{include/mach/exynos4-clock.h => clock-exynos4.h} (95%)

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5fc202c..995e7cc 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,7 +12,8 @@ obj-				:=
 
 # Core
 
-obj-$(CONFIG_ARCH_EXYNOS4)	+= common.o clock.o
+obj-$(CONFIG_ARCH_EXYNOS)	+= common.o
+obj-$(CONFIG_ARCH_EXYNOS4)	+= clock-exynos4.o
 obj-$(CONFIG_CPU_EXYNOS4210)	+= clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)	+= clock-exynos4212.o
 
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock-exynos4.c
similarity index 92%
rename from arch/arm/mach-exynos/clock.c
rename to arch/arm/mach-exynos/clock-exynos4.c
index 187287a..1d6d64f 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -1,5 +1,4 @@
-/* linux/arch/arm/mach-exynos4/clock.c
- *
+/*
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
@@ -26,9 +25,9 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/sysmmu.h>
-#include <mach/exynos4-clock.h>
 
 #include "common.h"
+#include "clock-exynos4.h"
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4_clock_save[] = {
@@ -215,8 +214,8 @@ static struct clksrc_clk clk_mout_apll = {
 	.clk	= {
 		.name		= "mout_apll",
 	},
-	.sources	= &clk_src_apll,
-	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
+	.sources = &clk_src_apll,
+	.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 };
 
 struct clksrc_clk clk_sclk_apll = {
@@ -224,22 +223,22 @@ struct clksrc_clk clk_sclk_apll = {
 		.name		= "sclk_apll",
 		.parent		= &clk_mout_apll.clk,
 	},
-	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
+	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 };
 
 struct clksrc_clk clk_mout_epll = {
 	.clk	= {
 		.name		= "mout_epll",
 	},
-	.sources	= &clk_src_epll,
-	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
+	.sources = &clk_src_epll,
+	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 };
 
 struct clksrc_clk clk_mout_mpll = {
-	.clk = {
+	.clk	= {
 		.name		= "mout_mpll",
 	},
-	.sources	= &clk_src_mpll,
+	.sources = &clk_src_mpll,
 
 	/* reg_src will be added in each SoCs' clock */
 };
@@ -258,8 +257,8 @@ static struct clksrc_clk clk_moutcore = {
 	.clk	= {
 		.name		= "moutcore",
 	},
-	.sources	= &clkset_moutcore,
-	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
+	.sources = &clkset_moutcore,
+	.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
 };
 
 static struct clksrc_clk clk_coreclk = {
@@ -267,7 +266,7 @@ static struct clksrc_clk clk_coreclk = {
 		.name		= "core_clk",
 		.parent		= &clk_moutcore.clk,
 	},
-	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
+	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
 };
 
 static struct clksrc_clk clk_armclk = {
@@ -282,7 +281,7 @@ static struct clksrc_clk clk_aclk_corem0 = {
 		.name		= "aclk_corem0",
 		.parent		= &clk_coreclk.clk,
 	},
-	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 };
 
 static struct clksrc_clk clk_aclk_cores = {
@@ -290,7 +289,7 @@ static struct clksrc_clk clk_aclk_cores = {
 		.name		= "aclk_cores",
 		.parent		= &clk_coreclk.clk,
 	},
-	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 };
 
 static struct clksrc_clk clk_aclk_corem1 = {
@@ -298,7 +297,7 @@ static struct clksrc_clk clk_aclk_corem1 = {
 		.name		= "aclk_corem1",
 		.parent		= &clk_coreclk.clk,
 	},
-	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
+	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
 };
 
 static struct clksrc_clk clk_periphclk = {
@@ -306,7 +305,7 @@ static struct clksrc_clk clk_periphclk = {
 		.name		= "periphclk",
 		.parent		= &clk_coreclk.clk,
 	},
-	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
+	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 };
 
 /* Core list of CMU_CORE side */
@@ -325,8 +324,8 @@ static struct clksrc_clk clk_mout_corebus = {
 	.clk	= {
 		.name		= "mout_corebus",
 	},
-	.sources	= &clkset_mout_corebus,
-	.reg_src	= { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
+	.sources = &clkset_mout_corebus,
+	.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
 };
 
 static struct clksrc_clk clk_sclk_dmc = {
@@ -334,7 +333,7 @@ static struct clksrc_clk clk_sclk_dmc = {
 		.name		= "sclk_dmc",
 		.parent		= &clk_mout_corebus.clk,
 	},
-	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
+	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
 };
 
 static struct clksrc_clk clk_aclk_cored = {
@@ -342,7 +341,7 @@ static struct clksrc_clk clk_aclk_cored = {
 		.name		= "aclk_cored",
 		.parent		= &clk_sclk_dmc.clk,
 	},
-	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
+	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
 };
 
 static struct clksrc_clk clk_aclk_corep = {
@@ -350,7 +349,7 @@ static struct clksrc_clk clk_aclk_corep = {
 		.name		= "aclk_corep",
 		.parent		= &clk_aclk_cored.clk,
 	},
-	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
+	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
 };
 
 static struct clksrc_clk clk_aclk_acp = {
@@ -358,7 +357,7 @@ static struct clksrc_clk clk_aclk_acp = {
 		.name		= "aclk_acp",
 		.parent		= &clk_mout_corebus.clk,
 	},
-	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
+	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
 };
 
 static struct clksrc_clk clk_pclk_acp = {
@@ -366,7 +365,7 @@ static struct clksrc_clk clk_pclk_acp = {
 		.name		= "pclk_acp",
 		.parent		= &clk_aclk_acp.clk,
 	},
-	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
+	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
 };
 
 /* Core list of CMU_TOP side */
@@ -385,36 +384,36 @@ static struct clksrc_clk clk_aclk_200 = {
 	.clk	= {
 		.name		= "aclk_200",
 	},
-	.sources	= &clkset_aclk,
-	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
-	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
+	.sources = &clkset_aclk,
+	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
+	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
 };
 
 static struct clksrc_clk clk_aclk_100 = {
 	.clk	= {
 		.name		= "aclk_100",
 	},
-	.sources	= &clkset_aclk,
-	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
-	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
+	.sources = &clkset_aclk,
+	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
+	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
 };
 
 static struct clksrc_clk clk_aclk_160 = {
 	.clk	= {
 		.name		= "aclk_160",
 	},
-	.sources	= &clkset_aclk,
-	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
-	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
+	.sources = &clkset_aclk,
+	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
+	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 };
 
 struct clksrc_clk clk_aclk_133 = {
 	.clk	= {
 		.name		= "aclk_133",
 	},
-	.sources	= &clkset_aclk,
-	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
-	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
+	.sources = &clkset_aclk,
+	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
+	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
 };
 
 static struct clk *clkset_vpllsrc_list[] = {
@@ -433,8 +432,8 @@ static struct clksrc_clk clk_vpllsrc = {
 		.enable		= exynos4_clksrc_mask_top_ctrl,
 		.ctrlbit	= (1 << 0),
 	},
-	.sources	= &clkset_vpllsrc,
-	.reg_src	= { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
+	.sources = &clkset_vpllsrc,
+	.reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
 };
 
 static struct clk *clkset_sclk_vpll_list[] = {
@@ -451,8 +450,8 @@ struct clksrc_clk clk_sclk_vpll = {
 	.clk	= {
 		.name		= "sclk_vpll",
 	},
-	.sources	= &clkset_sclk_vpll,
-	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
+	.sources = &clkset_sclk_vpll,
+	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 };
 
 static struct clk init_clocks_off[] = {
@@ -816,8 +815,8 @@ static struct clksrc_clk clk_mout_g2d0 = {
 	.clk	= {
 		.name		= "mout_g2d0",
 	},
-	.sources	= &clkset_mout_g2d0,
-	.reg_src	= { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+	.sources = &clkset_mout_g2d0,
+	.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 };
 
 static struct clk *clkset_mout_g2d1_list[] = {
@@ -834,8 +833,8 @@ static struct clksrc_clk clk_mout_g2d1 = {
 	.clk	= {
 		.name		= "mout_g2d1",
 	},
-	.sources	= &clkset_mout_g2d1,
-	.reg_src	= { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+	.sources = &clkset_mout_g2d1,
+	.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 };
 
 static struct clk *clkset_mout_g2d_list[] = {
@@ -862,8 +861,8 @@ static struct clksrc_clk clk_mout_mfc0 = {
 	.clk	= {
 		.name		= "mout_mfc0",
 	},
-	.sources	= &clkset_mout_mfc0,
-	.reg_src	= { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
+	.sources = &clkset_mout_mfc0,
+	.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
 };
 
 static struct clk *clkset_mout_mfc1_list[] = {
@@ -880,8 +879,8 @@ static struct clksrc_clk clk_mout_mfc1 = {
 	.clk	= {
 		.name		= "mout_mfc1",
 	},
-	.sources	= &clkset_mout_mfc1,
-	.reg_src	= { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
+	.sources = &clkset_mout_mfc1,
+	.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
 };
 
 static struct clk *clkset_mout_mfc_list[] = {
@@ -917,7 +916,7 @@ static struct clksrc_clk clk_sclk_dac = {
 static struct clksrc_clk clk_sclk_pixel = {
 	.clk		= {
 		.name		= "sclk_pixel",
-		.parent = &clk_sclk_vpll.clk,
+		.parent		= &clk_sclk_vpll.clk,
 	},
 	.reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
 };
@@ -953,7 +952,7 @@ static struct clksrc_sources clkset_sclk_mixer = {
 };
 
 static struct clksrc_clk clk_sclk_mixer = {
-	.clk		= {
+	.clk	= {
 		.name		= "sclk_mixer",
 		.enable		= exynos4_clksrc_mask_tv_ctrl,
 		.ctrlbit	= (1 << 4),
@@ -970,7 +969,7 @@ static struct clksrc_clk *sclk_tv[] = {
 };
 
 static struct clksrc_clk clk_dout_mmc0 = {
-	.clk		= {
+	.clk	= {
 		.name		= "dout_mmc0",
 	},
 	.sources = &clkset_group,
@@ -979,7 +978,7 @@ static struct clksrc_clk clk_dout_mmc0 = {
 };
 
 static struct clksrc_clk clk_dout_mmc1 = {
-	.clk		= {
+	.clk	= {
 		.name		= "dout_mmc1",
 	},
 	.sources = &clkset_group,
@@ -988,7 +987,7 @@ static struct clksrc_clk clk_dout_mmc1 = {
 };
 
 static struct clksrc_clk clk_dout_mmc2 = {
-	.clk		= {
+	.clk	= {
 		.name		= "dout_mmc2",
 	},
 	.sources = &clkset_group,
@@ -997,7 +996,7 @@ static struct clksrc_clk clk_dout_mmc2 = {
 };
 
 static struct clksrc_clk clk_dout_mmc3 = {
-	.clk		= {
+	.clk	= {
 		.name		= "dout_mmc3",
 	},
 	.sources = &clkset_group,
@@ -1016,7 +1015,7 @@ static struct clksrc_clk clk_dout_mmc4 = {
 
 static struct clksrc_clk clksrcs[] = {
 	{
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_pwm",
 			.enable		= exynos4_clksrc_mask_peril0_ctrl,
 			.ctrlbit	= (1 << 24),
@@ -1025,7 +1024,7 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
 		.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_csis",
 			.devname	= "s5p-mipi-csis.0",
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
@@ -1035,7 +1034,7 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
 		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_csis",
 			.devname	= "s5p-mipi-csis.1",
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
@@ -1045,7 +1044,7 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
 		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_cam0",
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
 			.ctrlbit	= (1 << 16),
@@ -1054,7 +1053,7 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
 		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_cam1",
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
 			.ctrlbit	= (1 << 20),
@@ -1063,7 +1062,7 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
 		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_fimc",
 			.devname	= "exynos4-fimc.0",
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
@@ -1073,7 +1072,7 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
 		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_fimc",
 			.devname	= "exynos4-fimc.1",
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
@@ -1083,7 +1082,7 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
 		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_fimc",
 			.devname	= "exynos4-fimc.2",
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
@@ -1093,7 +1092,7 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
 		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_fimc",
 			.devname	= "exynos4-fimc.3",
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
@@ -1103,7 +1102,7 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
 		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_fimd",
 			.devname	= "exynos4-fb.0",
 			.enable		= exynos4_clksrc_mask_lcd0_ctrl,
@@ -1113,14 +1112,14 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
 		.reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_fimg2d",
 		},
 		.sources = &clkset_mout_g2d,
 		.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
 		.reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_mfc",
 			.devname	= "s5p-mfc",
 		},
@@ -1128,9 +1127,9 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
 		.reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
 	}, {
-		.clk		= {
+		.clk	= {
 			.name		= "sclk_dwmmc",
-			.parent         = &clk_dout_mmc4.clk,
+			.parent		= &clk_dout_mmc4.clk,
 			.enable		= exynos4_clksrc_mask_fsys_ctrl,
 			.ctrlbit	= (1 << 16),
 		},
@@ -1151,7 +1150,7 @@ static struct clksrc_clk clk_sclk_uart0 = {
 };
 
 static struct clksrc_clk clk_sclk_uart1 = {
-	.clk		= {
+	.clk	= {
 		.name		= "uclk1",
 		.devname	= "exynos4210-uart.1",
 		.enable		= exynos4_clksrc_mask_peril0_ctrl,
@@ -1163,7 +1162,7 @@ static struct clksrc_clk clk_sclk_uart1 = {
 };
 
 static struct clksrc_clk clk_sclk_uart2 = {
-	.clk		= {
+	.clk	= {
 		.name		= "uclk1",
 		.devname	= "exynos4210-uart.2",
 		.enable		= exynos4_clksrc_mask_peril0_ctrl,
@@ -1175,7 +1174,7 @@ static struct clksrc_clk clk_sclk_uart2 = {
 };
 
 static struct clksrc_clk clk_sclk_uart3 = {
-	.clk		= {
+	.clk	= {
 		.name		= "uclk1",
 		.devname	= "exynos4210-uart.3",
 		.enable		= exynos4_clksrc_mask_peril0_ctrl,
@@ -1187,7 +1186,7 @@ static struct clksrc_clk clk_sclk_uart3 = {
 };
 
 static struct clksrc_clk clk_sclk_mmc0 = {
-	.clk		= {
+	.clk	= {
 		.name		= "sclk_mmc",
 		.devname	= "s3c-sdhci.0",
 		.parent		= &clk_dout_mmc0.clk,
@@ -1198,10 +1197,10 @@ static struct clksrc_clk clk_sclk_mmc0 = {
 };
 
 static struct clksrc_clk clk_sclk_mmc1 = {
-	.clk		= {
+	.clk	= {
 		.name		= "sclk_mmc",
 		.devname	= "s3c-sdhci.1",
-		.parent         = &clk_dout_mmc1.clk,
+		.parent		= &clk_dout_mmc1.clk,
 		.enable		= exynos4_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 4),
 	},
@@ -1209,10 +1208,10 @@ static struct clksrc_clk clk_sclk_mmc1 = {
 };
 
 static struct clksrc_clk clk_sclk_mmc2 = {
-	.clk		= {
+	.clk	= {
 		.name		= "sclk_mmc",
 		.devname	= "s3c-sdhci.2",
-		.parent         = &clk_dout_mmc2.clk,
+		.parent		= &clk_dout_mmc2.clk,
 		.enable		= exynos4_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 8),
 	},
@@ -1220,10 +1219,10 @@ static struct clksrc_clk clk_sclk_mmc2 = {
 };
 
 static struct clksrc_clk clk_sclk_mmc3 = {
-	.clk		= {
+	.clk	= {
 		.name		= "sclk_mmc",
 		.devname	= "s3c-sdhci.3",
-		.parent         = &clk_dout_mmc3.clk,
+		.parent		= &clk_dout_mmc3.clk,
 		.enable		= exynos4_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 12),
 	},
@@ -1231,11 +1230,11 @@ static struct clksrc_clk clk_sclk_mmc3 = {
 };
 
 static struct clksrc_clk clk_sclk_spi0 = {
-	.clk		= {
+	.clk	= {
 		.name		= "sclk_spi",
-		.devname		= "s3c64xx-spi.0",
+		.devname	= "s3c64xx-spi.0",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
-		.ctrlbit		= (1 << 16),
+		.ctrlbit	= (1 << 16),
 	},
 	.sources = &clkset_group,
 	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
@@ -1243,11 +1242,11 @@ static struct clksrc_clk clk_sclk_spi0 = {
 };
 
 static struct clksrc_clk clk_sclk_spi1 = {
-	.clk		= {
+	.clk	= {
 		.name		= "sclk_spi",
-		.devname		= "s3c64xx-spi.1",
+		.devname	= "s3c64xx-spi.1",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
-		.ctrlbit		= (1 << 20),
+		.ctrlbit	= (1 << 20),
 	},
 	.sources = &clkset_group,
 	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
@@ -1255,11 +1254,11 @@ static struct clksrc_clk clk_sclk_spi1 = {
 };
 
 static struct clksrc_clk clk_sclk_spi2 = {
-	.clk		= {
+	.clk	= {
 		.name		= "sclk_spi",
-		.devname		= "s3c64xx-spi.2",
+		.devname	= "s3c64xx-spi.2",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
-		.ctrlbit		= (1 << 24),
+		.ctrlbit	= (1 << 24),
 	},
 	.sources = &clkset_group,
 	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/clock-exynos4.h
similarity index 95%
rename from arch/arm/mach-exynos/include/mach/exynos4-clock.h
rename to arch/arm/mach-exynos/clock-exynos4.h
index a07fcbf..f64e9f7 100644
--- a/arch/arm/mach-exynos/include/mach/exynos4-clock.h
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -1,5 +1,4 @@
 /*
- * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
  *
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 13312cc..190d94a 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -28,9 +28,9 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
 
 #include "common.h"
+#include "clock-exynos4.h"
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4210_clock_save[] = {
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 48af285..e83d4b2 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -28,9 +28,9 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
 
 #include "common.h"
+#include "clock-exynos4.h"
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4212_clock_save[] = {
-- 
1.7.4.4



From shawn.guo at linaro.org  Mon Mar 12 07:58:54 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 12 Mar 2012 19:58:54 +0800
Subject: [PATCH v4 07/10] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331553537-19789-8-git-send-email-shawn.guo@linaro.org>

Provide different pair of accessors for accessing SSI registers on
PowerPC and ARM/IMX, so that fsl_ssi driver can be built on both
architectures.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |   64 ++++++++++++++++++++++++++++++----------------
 1 files changed, 42 insertions(+), 22 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 2eb407f..db9a734 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -11,11 +11,14 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 
 #include <sound/core.h>
@@ -26,6 +29,25 @@
 
 #include "fsl_ssi.h"
 
+#ifdef PPC
+#define read_ssi(addr)			 in_be32(addr)
+#define write_ssi(val, addr)		 out_be32(addr, val)
+#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
+#elif defined ARM
+#define read_ssi(addr)			 readl(addr)
+#define write_ssi(val, addr)		 writel(val, addr)
+/*
+ * FIXME: Proper locking should be added at write_ssi_mask caller level
+ * to ensure this register read/modify/write sequence is race free.
+ */
+static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
+{
+	u32 val = readl(addr);
+	val = (val & ~clear) | set;
+	writel(val, addr);
+}
+#endif
+
 /**
  * FSLSSI_I2S_RATES: sample rates supported by the I2S
  *
@@ -145,7 +167,7 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 	   were interrupted for.  We mask it with the Interrupt Enable register
 	   so that we only check for events that we're interested in.
 	 */
-	sisr = in_be32(&ssi->sisr) & SIER_FLAGS;
+	sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
 
 	if (sisr & CCSR_SSI_SISR_RFRC) {
 		ssi_private->stats.rfrc++;
@@ -260,7 +282,7 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 
 	/* Clear the bits that we set */
 	if (sisr2)
-		out_be32(&ssi->sisr, sisr2);
+		write_ssi(sisr2, &ssi->sisr);
 
 	return ret;
 }
@@ -295,7 +317,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 * SSI needs to be disabled before updating the registers we set
 		 * here.
 		 */
-		clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
+		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
 
 		/*
 		 * Program the SSI into I2S Slave Non-Network Synchronous mode.
@@ -303,20 +325,18 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 *
 		 * FIXME: Little-endian samples require a different shift dir
 		 */
-		clrsetbits_be32(&ssi->scr,
+		write_ssi_mask(&ssi->scr,
 			CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
 			CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE
 			| (synchronous ? CCSR_SSI_SCR_SYN : 0));
 
-		out_be32(&ssi->stcr,
-			 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
+		write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
 			 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
-			 CCSR_SSI_STCR_TSCKP);
+			 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
 
-		out_be32(&ssi->srcr,
-			 CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
+		write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
 			 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
-			 CCSR_SSI_SRCR_RSCKP);
+			 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
 
 		/*
 		 * The DC and PM bits are only used if the SSI is the clock
@@ -324,7 +344,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 */
 
 		/* Enable the interrupts and DMA requests */
-		out_be32(&ssi->sier, SIER_FLAGS);
+		write_ssi(SIER_FLAGS, &ssi->sier);
 
 		/*
 		 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
@@ -339,9 +359,9 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 * make this value larger (and maybe we should), but this way
 		 * data will be written to memory as soon as it's available.
 		 */
-		out_be32(&ssi->sfcsr,
-			CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
-			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2));
+		write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
+			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2),
+			&ssi->sfcsr);
 
 		/*
 		 * We keep the SSI disabled because if we enable it, then the
@@ -417,7 +437,7 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 	unsigned int sample_size =
 		snd_pcm_format_width(params_format(hw_params));
 	u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
-	int enabled = in_be32(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
+	int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
 
 	/*
 	 * If we're in synchronous mode, and the SSI is already enabled,
@@ -439,9 +459,9 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 	/* In synchronous mode, the SSI uses STCCR for capture */
 	if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
 	    ssi_private->cpu_dai_drv.symmetric_rates)
-		clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+		write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
 	else
-		clrsetbits_be32(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+		write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
 
 	return 0;
 }
@@ -466,19 +486,19 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-			setbits32(&ssi->scr,
+			write_ssi_mask(&ssi->scr, 0,
 				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
 		else
-			setbits32(&ssi->scr,
+			write_ssi_mask(&ssi->scr, 0,
 				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
 		break;
 
 	case SNDRV_PCM_TRIGGER_STOP:
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-			clrbits32(&ssi->scr, CCSR_SSI_SCR_TE);
+			write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
 		else
-			clrbits32(&ssi->scr, CCSR_SSI_SCR_RE);
+			write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
 		break;
 
 	default:
@@ -510,7 +530,7 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
 	if (!ssi_private->first_stream) {
 		struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 
-		clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
+		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
 	}
 }
 
-- 
1.7.5.4



From grant.likely at secretlab.ca  Mon Mar 12 12:19:04 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 10:19:04 -0600
Subject: [PATCH v2 3/3] gpio/samsung: use ioremap() for EXYNOS4 GPIOlib
In-Reply-To: <1329341829-14403-4-git-send-email-kgene.kim@samsung.com>
References: <1329341829-14403-1-git-send-email-kgene.kim@samsung.com>
 <1329341829-14403-4-git-send-email-kgene.kim@samsung.com>
Message-ID: <20120312161904.E57193E07B0@localhost>

On Thu, 16 Feb 2012 06:37:09 +0900, Kukjin Kim <kgene.kim at samsung.com> wrote:
> From: Sangsu Park <sangsu4u.park at samsung.com>
> 
> This patch changes to use ioremap() for EXYNOS4210
> so that we can drop the static mapping for EXYNOS
> SoCs.
> 
> Note: Will be updated for all of Samsung GPIOlibs
> to use ioremap() next time.
> 
> Signed-off-by: Sangsu Park <sangsu4u.park at samsung.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>

Acked-by: Grant Likely <grant.likely at secretlab.ca>

Kukjin, I think you wanted to take this via your tree?  I'm fine with that.
Let me know if you'd rather it go via the gpio tree.

g.


> ---
>  arch/arm/mach-exynos/common.c |   15 ------------
>  drivers/gpio/gpio-samsung.c   |   48 +++++++++++++++++++++++++++++------------
>  2 files changed, 34 insertions(+), 29 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 63a2b04..618e7f3 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -172,21 +172,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
>  		.length		= SZ_4K,
>  		.type		= MT_DEVICE,
>  	}, {
> -		.virtual	= (unsigned long)S5P_VA_GPIO1,
> -		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO1),
> -		.length		= SZ_4K,
> -		.type		= MT_DEVICE,
> -	}, {
> -		.virtual	= (unsigned long)S5P_VA_GPIO2,
> -		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO2),
> -		.length		= SZ_4K,
> -		.type		= MT_DEVICE,
> -	}, {
> -		.virtual	= (unsigned long)S5P_VA_GPIO3,
> -		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO3),
> -		.length		= SZ_256,
> -		.type		= MT_DEVICE,
> -	}, {
>  		.virtual	= (unsigned long)S5P_VA_DMC0,
>  		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),
>  		.length		= SZ_4K,
> diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
> index d6cfdee7..4627787 100644
> --- a/drivers/gpio/gpio-samsung.c
> +++ b/drivers/gpio/gpio-samsung.c
> @@ -2331,7 +2331,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
>  			.label	= "GPY6",
>  		},
>  	}, {
> -		.base	= (S5P_VA_GPIO2 + 0xC00),
>  		.config	= &samsung_gpio_cfgs[9],
>  		.irq_base = IRQ_EINT(0),
>  		.chip	= {
> @@ -2341,7 +2340,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
>  			.to_irq	= samsung_gpiolib_to_irq,
>  		},
>  	}, {
> -		.base	= (S5P_VA_GPIO2 + 0xC20),
>  		.config	= &samsung_gpio_cfgs[9],
>  		.irq_base = IRQ_EINT(8),
>  		.chip	= {
> @@ -2351,7 +2349,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
>  			.to_irq	= samsung_gpiolib_to_irq,
>  		},
>  	}, {
> -		.base	= (S5P_VA_GPIO2 + 0xC40),
>  		.config	= &samsung_gpio_cfgs[9],
>  		.irq_base = IRQ_EINT(16),
>  		.chip	= {
> @@ -2361,7 +2358,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
>  			.to_irq	= samsung_gpiolib_to_irq,
>  		},
>  	}, {
> -		.base	= (S5P_VA_GPIO2 + 0xC60),
>  		.config	= &samsung_gpio_cfgs[9],
>  		.irq_base = IRQ_EINT(24),
>  		.chip	= {
> @@ -2789,9 +2785,16 @@ static __init int samsung_gpiolib_init(void)
>  		s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
>  #endif
>  	} else if (soc_is_exynos4210()) {
> -		group = 0;
> +#ifdef CONFIG_CPU_EXYNOS4210
> +		void __iomem *gpx_base;
>  
>  		/* gpio part1 */
> +		gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
> +		if (gpio_base1 == NULL) {
> +			pr_err("unable to ioremap for gpio_base1\n");
> +			goto err_ioremap1;
> +		}
> +
>  		chip = exynos4_gpios_1;
>  		nr_chips = ARRAY_SIZE(exynos4_gpios_1);
>  
> @@ -2800,14 +2803,25 @@ static __init int samsung_gpiolib_init(void)
>  				chip->config = &exynos_gpio_cfg;
>  				chip->group = group++;
>  			}
> -#ifdef CONFIG_CPU_EXYNOS4210
>  			exynos_gpiolib_attach_ofnode(chip,
>  					EXYNOS4_PA_GPIO1, i * 0x20);
> -#endif
>  		}
> -		samsung_gpiolib_add_4bit_chips(exynos4_gpios_1, nr_chips, S5P_VA_GPIO1);
> +		samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
> +					       nr_chips, gpio_base1);
>  
>  		/* gpio part2 */
> +		gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
> +		if (gpio_base2 == NULL) {
> +			pr_err("unable to ioremap for gpio_base2\n");
> +			goto err_ioremap2;
> +		}
> +
> +		/* need to set base address for gpx */
> +		chip = &exynos4_gpios_2[16];
> +		gpx_base = gpio_base2 + 0xC00;
> +		for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
> +			chip->base = gpx_base;
> +
>  		chip = exynos4_gpios_2;
>  		nr_chips = ARRAY_SIZE(exynos4_gpios_2);
>  
> @@ -2816,14 +2830,19 @@ static __init int samsung_gpiolib_init(void)
>  				chip->config = &exynos_gpio_cfg;
>  				chip->group = group++;
>  			}
> -#ifdef CONFIG_CPU_EXYNOS4210
>  			exynos_gpiolib_attach_ofnode(chip,
>  					EXYNOS4_PA_GPIO2, i * 0x20);
> -#endif
>  		}
> -		samsung_gpiolib_add_4bit_chips(exynos4_gpios_2, nr_chips, S5P_VA_GPIO2);
> +		samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
> +					       nr_chips, gpio_base2);
>  
>  		/* gpio part3 */
> +		gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
> +		if (gpio_base3 == NULL) {
> +			pr_err("unable to ioremap for gpio_base3\n");
> +			goto err_ioremap3;
> +		}
> +
>  		chip = exynos4_gpios_3;
>  		nr_chips = ARRAY_SIZE(exynos4_gpios_3);
>  
> @@ -2832,17 +2851,18 @@ static __init int samsung_gpiolib_init(void)
>  				chip->config = &exynos_gpio_cfg;
>  				chip->group = group++;
>  			}
> -#ifdef CONFIG_CPU_EXYNOS4210
>  			exynos_gpiolib_attach_ofnode(chip,
>  					EXYNOS4_PA_GPIO3, i * 0x20);
> -#endif
>  		}
> -		samsung_gpiolib_add_4bit_chips(exynos4_gpios_3, nr_chips, S5P_VA_GPIO3);
> +		samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
> +					       nr_chips, gpio_base3);
>  
>  #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
>  		s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
>  		s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
>  #endif
> +
> +#endif	/* CONFIG_CPU_EXYNOS4210 */
>  	} else if (soc_is_exynos5250()) {
>  #ifdef CONFIG_SOC_EXYNOS5250
>  		void __iomem *gpx_base;
> -- 
> 1.7.4.4
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From swarren at wwwdotorg.org  Mon Mar 12 12:57:10 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 12 Mar 2012 10:57:10 -0600
Subject: [PATCH 10/11] ARM: tegra: pcie: Add MSI support
In-Reply-To: <20120312080023.GA13788@avionic-0098.mockup.avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-11-git-send-email-thierry.reding@avionic-design.de>
 <4F59213F.6070107@wwwdotorg.org>
 <20120312080023.GA13788@avionic-0098.mockup.avionic-design.de>
Message-ID: <4F5E2AE6.3030404@wwwdotorg.org>

On 03/12/2012 02:00 AM, Thierry Reding wrote:
> * Stephen Warren wrote:
>> On 03/08/2012 07:51 AM, Thierry Reding wrote:
>>> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
...
>> Free the IRQ descriptors in the error paths?
...
>>> +	for (msi = 0; msi < INT_PCI_MSI_NR; msi++) {
>>> +		unsigned int irq = irq_find_mapping(pcie->msi_domain, msi);
>>> +
>>> +		irq_set_chip_data(irq, pcie);
>>> +		irq_set_chip_and_handler(irq, &pcie->msi_chip,
>>> +					 handle_simple_irq);
>>> +		set_irq_flags(irq, IRQF_VALID);
>>> +	}
>>> +
>>> +	err = platform_get_irq(pdev, 1);
>>> +	if (err < 0) {
>>> +		dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
>>
>> Same here, and undo setting IRQF_VALID?
> 
> Does it make sense to explicitly unset the IRQF_VALID flag when the IRQ
> descriptors are free'd afterwards anyway?

Good point. Probably not per my gut instinct.

...
> I'm also Cc'ing Thomas
> Gleixner as maintainer of the IRQ subsystem, he probably knows best how
> dynamically allocated interrupts should be cleaned up.

But yes, best to check with someone more familiar with interrupts.


From swarren at wwwdotorg.org  Mon Mar 12 14:09:43 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 12 Mar 2012 12:09:43 -0600
Subject: [PATCH v2 2/2] arm/tegra: add timeout to PCIe PLL lock detection
 loop
In-Reply-To: <1331287760-10546-1-git-send-email-mad_soft@inbox.ru>
References: <20120306201538.GA14350@rainbow>
 <1331287760-10546-1-git-send-email-mad_soft@inbox.ru>
Message-ID: <4F5E3BE7.4080207@wwwdotorg.org>

On 03/09/2012 03:09 AM, Dmitry Artamonow wrote:
> Tegra PCIe driver waits for PLL to lock using busy loop.
> If PLL fails to lock for some reason, this leads to silent lockup
> while booting (PCIe code is not modular).
> 
> Fix by adding timeout, so if PLL doesn't lock in a couple
> of seconds, just PCIe driver fails and machine continues to boot.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>

> diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c

>  	/* Wait for the PLL to lock */
> +	timeout = 2000;
>  	do {
>  		val = pads_readl(PADS_PLL_CTL);
> +		usleep_range(1000, 1000);
> +		if (--timeout == 0) {
> +			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
> +			return -EBUSY;
> +		}
>  	} while (!(val & PADS_PLL_CTL_LOCKDET));

Thierry pointed out that one of NVIDIA's downstream kernels uses a
timeout of 300 here, rather than 2000 above. Do you see a specific need
for this timeout for be 2000 rather than 300? It might be nice to be
consistent.

Olof, I notice you've already applied V1 of this, which has the return
statement issue. Can you replace it with this, or should Dmitry send an
incremental patch?


From khilman at ti.com  Mon Mar 12 12:51:40 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 12 Mar 2012 09:51:40 -0700
Subject: [PATCH] ARM: OMAP4: Workaround the OCP synchronisation issue with
 32K synctimer.
In-Reply-To: <1331566388-2397-1-git-send-email-santosh.shilimkar@ti.com>
 (Santosh Shilimkar's message of "Mon, 12 Mar 2012 21:03:08 +0530")
References: <1331566388-2397-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <87399d225f.fsf@ti.com>

Santosh Shilimkar <santosh.shilimkar at ti.com> writes:

> On OMAP4, recently a synchronisation bug is discovered by hardware
> team, which leads to incorrect timer value read from 32K sync timer
> IP when the IP is comming out of idle.
>
> The issue is due to the synchronization methodology used in the SYNCTIMER IP.
> The value of the counter register in 32kHz domain is synchronized to the OCP
> domain register only at count up event, and if the OCP clock is switched off,
> the OCP register gets out of synch until the first count up event after the
> clock is switched back -at the next falling edge of the 32kHz clock.
>
> Further investigation revealed that it applies to gptimer1 and watchdog timer2
> as well which may run on 32KHz. This patch fixes the issue for all the
> applicable modules.

The changelog describes the problem ver well, but doesn't actually
describe the fix (enable static dep.)  Can you update the changelog do
describe the fix, and why it fixes the problem.

Thanks,

Kevin


> The BUG has not made it yet to the OMAP errata list and it is applicable to
> OMAP1/2/3/4/5. OMAP1/2/3 it is taken care indirectly by autodeps.
>
> Reported-Tested-by: dave.long at linaro.org
> [dave.long at linaro.org: Reported the oprofile time stamp issue with synctimer
> and helped to test this patch]
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> ---
>  arch/arm/mach-omap2/pm44xx.c |   10 ++++++++--
>  1 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> index c264ef7..974f7ea 100644
> --- a/arch/arm/mach-omap2/pm44xx.c
> +++ b/arch/arm/mach-omap2/pm44xx.c
> @@ -196,7 +196,7 @@ static void omap_default_idle(void)
>  static int __init omap4_pm_init(void)
>  {
>  	int ret;
> -	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
> +	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
>  	struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
>  
>  	if (!cpu_is_omap44xx())
> @@ -220,14 +220,19 @@ static int __init omap4_pm_init(void)
>  	 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
>  	 * expected. The hardware recommendation is to enable static
>  	 * dependencies for these to avoid system lock ups or random crashes.
> +	 * The L4 wakeup depedency is added to workaround the OCP sync hardware
> +	 * BUG with 32K synctimer which lead to incorrect timer value read
> +	 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
> +	 * are part of L4 wakeup clockdomain.
>  	 */
>  	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
>  	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
>  	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
>  	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
>  	l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
> +	l4wkup = clkdm_lookup("l4_wkup_clkdm");
>  	ducati_clkdm = clkdm_lookup("ducati_clkdm");
> -	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
> +	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) ||
>  		(!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
>  		goto err2;
>  
> @@ -235,6 +240,7 @@ static int __init omap4_pm_init(void)
>  	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
>  	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
>  	ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
> +	ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup);
>  	ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
>  	ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
>  	if (ret) {


From nsekhar at ti.com  Mon Mar 12 16:46:23 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Mon, 12 Mar 2012 20:46:23 +0000
Subject: [PATCH] ARM: davinci: DA850: move da850_register_pm to .init.text
In-Reply-To: <1331157836-30527-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1331157836-30527-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <DF0F476B391FA8409C78302C7BA518B6317F2EA8@DBDE01.ent.ti.com>

Hi Uwe,

On Thu, Mar 08, 2012 at 03:33:56, Uwe Kleine-K?nig wrote:
> All callers (board-mityomapl138.c and board-da850-evm.c) use it in
> __init functions only.
> 
> This fixes:
> 
> 	WARNING: vmlinux.o(.text+0xd664): Section mismatch in reference from the function da850_register_pm() to the function .init.text:da8xx_get_mem_ctlr()
> 	The function da850_register_pm() references
> 	the function __init da8xx_get_mem_ctlr().
> 	This is often because da850_register_pm lacks a __init
> 	annotation or the annotation of da8xx_get_mem_ctlr is wrong.
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Applying this, thanks.

Regards,
Sekhar


From thomas.abraham at linaro.org  Mon Mar 12 16:59:56 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 02:29:56 +0530
Subject: [PATCH v2 0/3] video: s3c-fb: Rearrange the elements in platform data
Message-ID: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>

Changes since v1:
- Includes all changes suggested by Jingoo Han.
- Reworked s3c-fb platform data in all Samsung SoC based board files.

This patchset rearranges the elements in the platform data of the s3c-fb
driver with the intent of adding device tree support to the driver in
subsequent patches.

The first patch moves the video timing information from the individual window
setup data into the platform specific configuration section in the platform
data. The video timing is independent of the window setup. The resolution of
the window could be smaller than that of the lcd panel attached. So the video
timing data is removed from window configuration data.

The second patch removes the need for the 'default_win' element in the
platform data. This element was used to decide whether the video data
output from the controller should be enabled or disabled when the window
specified by 'default_win' is enabled or disabled. With the first patch
removing the need for atleast one window to be of the same resolution as
that of the lcd panel, it is now possible to decide when to enable/disable
the video data output based on the state of each window. If any of the
window is active, the lcd data output is enabled. Otherwise, the lcd data
output is disabled. Hence, the 'default_win' parameter from the platform
data can be removed, which anyways cannot be specified when using
device tree.

For all the Samsung SoC based boards, the third patch reworks the platform
data of the display controller based on the changes introduced in the first
two patches.

This patch series is based on
http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]

with all patches merged from
https://github.com/schandinat/linux-2.6.git [fbdev-next]

and tested one Exynos4210 based Origen board (only compile tested for
other boards)

Thomas Abraham (3):
  video: s3c-fb: move video interface timing out of window setup data
  video: s3c-fb: remove 'default_win' element from platform data
  ARM: Samsung: Rework platform data of s3c-fb driver

 arch/arm/mach-exynos/mach-nuri.c           |   26 +++---
 arch/arm/mach-exynos/mach-origen.c         |   24 +++--
 arch/arm/mach-exynos/mach-smdkv310.c       |   28 ++++---
 arch/arm/mach-exynos/mach-universal_c210.c |   26 +++---
 arch/arm/mach-s3c24xx/mach-smdk2416.c      |   27 +++---
 arch/arm/mach-s3c64xx/mach-anw6410.c       |   25 +++---
 arch/arm/mach-s3c64xx/mach-crag6410.c      |   25 +++---
 arch/arm/mach-s3c64xx/mach-hmt.c           |   24 +++--
 arch/arm/mach-s3c64xx/mach-mini6410.c      |   40 ++++-----
 arch/arm/mach-s3c64xx/mach-real6410.c      |   40 ++++-----
 arch/arm/mach-s3c64xx/mach-smartq5.c       |   26 +++---
 arch/arm/mach-s3c64xx/mach-smartq7.c       |   26 +++---
 arch/arm/mach-s3c64xx/mach-smdk6410.c      |   25 +++---
 arch/arm/mach-s5p64x0/mach-smdk6440.c      |   24 +++--
 arch/arm/mach-s5p64x0/mach-smdk6450.c      |   24 +++--
 arch/arm/mach-s5pc100/mach-smdkc100.c      |   27 +++---
 arch/arm/mach-s5pv210/mach-aquila.c        |   36 ++++----
 arch/arm/mach-s5pv210/mach-goni.c          |   26 +++---
 arch/arm/mach-s5pv210/mach-smdkv210.c      |   24 +++--
 arch/arm/plat-samsung/include/plat/fb.h    |   11 ++-
 drivers/video/s3c-fb.c                     |  136 +++++++++++++---------------
 21 files changed, 356 insertions(+), 314 deletions(-)



From thomas.abraham at linaro.org  Mon Mar 12 16:59:57 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 02:29:57 +0530
Subject: [PATCH v2 1/3] video: s3c-fb: move video interface timing out of
 window setup data
In-Reply-To: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1331585999-8604-2-git-send-email-thomas.abraham@linaro.org>

The video interface timing is independent of the window setup data.
The resolution of the window can be smaller than that of the lcd
panel to which the video data is output.

So move the video timing data from the per-window setup data to the
platform specific section in the platform data. This also removes
the restriction that atleast one window should have the same
resolution as that of the panel attached.

Cc: Ben Dooks <ben-linux at fluff.org>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
Acked-by: Jingoo Han <jg1.han at samsung.com>
---
 arch/arm/plat-samsung/include/plat/fb.h |    9 ++-
 drivers/video/s3c-fb.c                  |  114 +++++++++++++++++--------------
 2 files changed, 68 insertions(+), 55 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 0fedf47..39d6bd7 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -24,15 +24,16 @@
 
 /**
  * struct s3c_fb_pd_win - per window setup data
- * @win_mode: The display parameters to initialise (not for window 0)
+ * @xres     : The window X size.
+ * @yres     : The window Y size.
  * @virtual_x: The virtual X size.
  * @virtual_y: The virtual Y size.
  */
 struct s3c_fb_pd_win {
-	struct fb_videomode	win_mode;
-
 	unsigned short		default_bpp;
 	unsigned short		max_bpp;
+	unsigned short		xres;
+	unsigned short		yres;
 	unsigned short		virtual_x;
 	unsigned short		virtual_y;
 };
@@ -45,6 +46,7 @@ struct s3c_fb_pd_win {
  * @default_win: default window layer number to be used for UI layer.
  * @vidcon0: The base vidcon0 values to control the panel data format.
  * @vidcon1: The base vidcon1 values to control the panel data output.
+ * @vtiming: Video timing when connected to a RGB type panel.
  * @win: The setup data for each hardware window, or NULL for unused.
  * @display_mode: The LCD output display mode.
  *
@@ -58,6 +60,7 @@ struct s3c_fb_platdata {
 	void	(*setup_gpio)(void);
 
 	struct s3c_fb_pd_win	*win[S3C_FB_MAX_WIN];
+	struct fb_videomode     *vtiming;
 
 	u32			 default_win;
 
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index f310516..60d1c12 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -495,7 +495,6 @@ static int s3c_fb_set_par(struct fb_info *info)
 	u32 alpha = 0;
 	u32 data;
 	u32 pagewidth;
-	int clkdiv;
 
 	dev_dbg(sfb->dev, "setting framebuffer parameters\n");
 
@@ -532,47 +531,8 @@ static int s3c_fb_set_par(struct fb_info *info)
 	/* disable the window whilst we update it */
 	writel(0, regs + WINCON(win_no));
 
-	/* use platform specified window as the basis for the lcd timings */
-
-	if (win_no == sfb->pdata->default_win) {
-		clkdiv = s3c_fb_calc_pixclk(sfb, var->pixclock);
-
-		data = sfb->pdata->vidcon0;
-		data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
-
-		if (clkdiv > 1)
-			data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
-		else
-			data &= ~VIDCON0_CLKDIR;	/* 1:1 clock */
-
-		/* write the timing data to the panel */
-
-		if (sfb->variant.is_2443)
-			data |= (1 << 5);
-
-		writel(data, regs + VIDCON0);
-
-		s3c_fb_enable(sfb, 1);
-
-		data = VIDTCON0_VBPD(var->upper_margin - 1) |
-		       VIDTCON0_VFPD(var->lower_margin - 1) |
-		       VIDTCON0_VSPW(var->vsync_len - 1);
-
-		writel(data, regs + sfb->variant.vidtcon);
-
-		data = VIDTCON1_HBPD(var->left_margin - 1) |
-		       VIDTCON1_HFPD(var->right_margin - 1) |
-		       VIDTCON1_HSPW(var->hsync_len - 1);
-
-		/* VIDTCON1 */
-		writel(data, regs + sfb->variant.vidtcon + 4);
-
-		data = VIDTCON2_LINEVAL(var->yres - 1) |
-		       VIDTCON2_HOZVAL(var->xres - 1) |
-		       VIDTCON2_LINEVAL_E(var->yres - 1) |
-		       VIDTCON2_HOZVAL_E(var->xres - 1);
-		writel(data, regs + sfb->variant.vidtcon + 8);
-	}
+	if (win_no == sfb->pdata->default_win)
+		s3c_fb_enable(sfb, 1);
 
 	/* write the buffer address */
 
@@ -1144,11 +1104,11 @@ static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
 
 	dev_dbg(sfb->dev, "allocating memory for display\n");
 
-	real_size = windata->win_mode.xres * windata->win_mode.yres;
+	real_size = windata->xres * windata->yres;
 	virt_size = windata->virtual_x * windata->virtual_y;
 
 	dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
-		real_size, windata->win_mode.xres, windata->win_mode.yres,
+		real_size, windata->xres, windata->yres,
 		virt_size, windata->virtual_x, windata->virtual_y);
 
 	size = (real_size > virt_size) ? real_size : virt_size;
@@ -1230,7 +1190,7 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 				      struct s3c_fb_win **res)
 {
 	struct fb_var_screeninfo *var;
-	struct fb_videomode *initmode;
+	struct fb_videomode initmode;
 	struct s3c_fb_pd_win *windata;
 	struct s3c_fb_win *win;
 	struct fb_info *fbinfo;
@@ -1251,11 +1211,11 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 	}
 
 	windata = sfb->pdata->win[win_no];
-	initmode = &windata->win_mode;
+	initmode = *sfb->pdata->vtiming;
 
 	WARN_ON(windata->max_bpp == 0);
-	WARN_ON(windata->win_mode.xres == 0);
-	WARN_ON(windata->win_mode.yres == 0);
+	WARN_ON(windata->xres == 0);
+	WARN_ON(windata->yres == 0);
 
 	win = fbinfo->par;
 	*res = win;
@@ -1294,7 +1254,9 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 	}
 
 	/* setup the initial video mode from the window */
-	fb_videomode_to_var(&fbinfo->var, initmode);
+	initmode.xres = windata->xres;
+	initmode.yres = windata->yres;
+	fb_videomode_to_var(&fbinfo->var, &initmode);
 
 	fbinfo->fix.type	= FB_TYPE_PACKED_PIXELS;
 	fbinfo->fix.accel	= FB_ACCEL_NONE;
@@ -1339,6 +1301,53 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 }
 
 /**
+ * s3c_fb_set_rgb_timing() - set video timing for rgb interface.
+ * @sfb: The base resources for the hardware.
+ *
+ * Set horizontal and vertical lcd rgb interface timing.
+ */
+static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb)
+{
+	struct fb_videomode *vmode = sfb->pdata->vtiming;
+	void __iomem *regs = sfb->regs;
+	int clkdiv;
+	u32 data;
+
+	if (!vmode->pixclock)
+		s3c_fb_missing_pixclock(vmode);
+
+	clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock);
+
+	data = sfb->pdata->vidcon0;
+	data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
+
+	if (clkdiv > 1)
+		data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
+	else
+		data &= ~VIDCON0_CLKDIR;	/* 1:1 clock */
+
+	if (sfb->variant.is_2443)
+		data |= (1 << 5);
+	writel(data, regs + VIDCON0);
+
+	data = VIDTCON0_VBPD(vmode->upper_margin - 1) |
+	       VIDTCON0_VFPD(vmode->lower_margin - 1) |
+	       VIDTCON0_VSPW(vmode->vsync_len - 1);
+	writel(data, regs + sfb->variant.vidtcon);
+
+	data = VIDTCON1_HBPD(vmode->left_margin - 1) |
+	       VIDTCON1_HFPD(vmode->right_margin - 1) |
+	       VIDTCON1_HSPW(vmode->hsync_len - 1);
+	writel(data, regs + sfb->variant.vidtcon + 4);
+
+	data = VIDTCON2_LINEVAL(vmode->yres - 1) |
+	       VIDTCON2_HOZVAL(vmode->xres - 1) |
+	       VIDTCON2_LINEVAL_E(vmode->yres - 1) |
+	       VIDTCON2_HOZVAL_E(vmode->xres - 1);
+	writel(data, regs + sfb->variant.vidtcon + 8);
+}
+
+/**
  * s3c_fb_clear_win() - clear hardware window registers.
  * @sfb: The base resources for the hardware.
  * @win: The window to process.
@@ -1481,15 +1490,14 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
 		writel(0xffffff, regs + WKEYCON1);
 	}
 
+	s3c_fb_set_rgb_timing(sfb);
+
 	/* we have the register setup, start allocating framebuffers */
 
 	for (win = 0; win < fbdrv->variant.nr_windows; win++) {
 		if (!pd->win[win])
 			continue;
 
-		if (!pd->win[win]->win_mode.pixclock)
-			s3c_fb_missing_pixclock(&pd->win[win]->win_mode);
-
 		ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
 				       &sfb->windows[win]);
 		if (ret < 0) {
@@ -1623,6 +1631,8 @@ static int s3c_fb_resume(struct device *dev)
 		shadow_protect_win(win, 0);
 	}
 
+	s3c_fb_set_rgb_timing(sfb);
+
 	/* restore framebuffers */
 	for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
 		win = sfb->windows[win_no];
-- 
1.6.6.rc2



From mturquette at ti.com  Mon Mar 12 16:58:11 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Mon, 12 Mar 2012 13:58:11 -0700
Subject: [PATCH v6 3/3] clk: basic clock hardware types
In-Reply-To: <4F5E5A0C.6080604@gmail.com>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-4-git-send-email-mturquette@linaro.org>
 <4F5E5A0C.6080604@gmail.com>
Message-ID: <CAJOA=zOS44YRfg3A7D8G+jWoQ_gzRQ937A7tYDU+DxWce_khzQ@mail.gmail.com>

On Mon, Mar 12, 2012 at 1:18 PM, Rob Herring <robherring2 at gmail.com> wrote:
> On 03/10/2012 01:54 AM, Mike Turquette wrote:
>> Many platforms support simple gateable clocks, fixed-rate clocks,
>> adjustable divider clocks and multi-parent multiplexer clocks.
>>
>> This patch introduces basic clock types for the above-mentioned hardware
>> which share some common characteristics.
>>
>> Based on original work by Jeremy Kerr and contribution by Jamie Iles.
>> Dividers and multiplexor clocks originally contributed by Richard Zhao &
>> Sascha Hauer.
>>
>> Signed-off-by: Mike Turquette <mturquette at linaro.org>
>> Signed-off-by: Mike Turquette <mturquette at ti.com>
>> Cc: Russell King <linux at arm.linux.org.uk>
>> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
>> Cc: Thomas Gleixner <tglx at linutronix.de>
>> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
>> Cc: Paul Walmsley <paul at pwsan.com>
>> Cc: Shawn Guo <shawn.guo at freescale.com>
>> Cc: Sascha Hauer <s.hauer at pengutronix.de>
>> Cc: Jamie Iles <jamie at jamieiles.com>
>> Cc: Richard Zhao <richard.zhao at linaro.org>
>> Cc: Saravana Kannan <skannan at codeaurora.org>
>> Cc: Magnus Damm <magnus.damm at gmail.com>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
>> Cc: Linus Walleij <linus.walleij at stericsson.com>
>> Cc: Stephen Boyd <sboyd at codeaurora.org>
>> Cc: Amit Kucheria <amit.kucheria at linaro.org>
>> Cc: Deepak Saxena <dsaxena at linaro.org>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Cc: Andrew Lunn <andrew at lunn.ch>
>
> One issue with spinlocks below, but otherwise:
>
> Reviewed-by: Rob Herring <rob.herring at calxeda.com>
>
>> ---
>> Changes since v5:
>> ?* standardized the hw-specific locking in the basic clock types
>> ?* export the individual ops for each basic clock type
>> ?* improve registration for single-parent basic clocks (thanks Sascha)
>> ?* fixed bugs in gate clock's static initializers (thanks Andrew)
>>
>> ?drivers/clk/Makefile ? ? ? ? | ? ?3 +-
>> ?drivers/clk/clk-divider.c ? ?| ?204 ++++++++++++++++++++++++++++++++++++++++++
>> ?drivers/clk/clk-fixed-rate.c | ? 82 +++++++++++++++++
>> ?drivers/clk/clk-gate.c ? ? ? | ?157 ++++++++++++++++++++++++++++++++
>> ?drivers/clk/clk-mux.c ? ? ? ?| ?123 +++++++++++++++++++++++++
>> ?include/linux/clk-private.h ?| ?124 +++++++++++++++++++++++++
>> ?include/linux/clk-provider.h | ?127 ++++++++++++++++++++++++++
>> ?7 files changed, 819 insertions(+), 1 deletions(-)
>> ?create mode 100644 drivers/clk/clk-divider.c
>> ?create mode 100644 drivers/clk/clk-fixed-rate.c
>> ?create mode 100644 drivers/clk/clk-gate.c
>> ?create mode 100644 drivers/clk/clk-mux.c
>>
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index ff362c4..1f736bc 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -1,3 +1,4 @@
>>
>> ?obj-$(CONFIG_CLKDEV_LOOKUP) ?+= clkdev.o
>> -obj-$(CONFIG_COMMON_CLK) ? ? += clk.o
>> +obj-$(CONFIG_COMMON_CLK) ? ? += clk.o clk-fixed-rate.o clk-gate.o \
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?clk-mux.o clk-divider.o
>> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
>> new file mode 100644
>> index 0000000..c0c4e0b
>> --- /dev/null
>> +++ b/drivers/clk/clk-divider.c
>> @@ -0,0 +1,204 @@
>> +/*
>> + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
>> + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
>> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Adjustable divider clock implementation
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/string.h>
>> +
>> +/*
>> + * DOC: basic adjustable divider clock that cannot gate
>> + *
>> + * Traits of this clock:
>> + * prepare - clk_prepare only ensures that parents are prepared
>> + * enable - clk_enable only ensures that parents are enabled
>> + * rate - rate is adjustable. ?clk->rate = parent->rate / divisor
>> + * parent - fixed parent. ?No clk_set_parent support
>> + */
>> +
>> +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
>> +
>> +static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
>> + ? ? ? ? ? ? unsigned long parent_rate)
>> +{
>> + ? ? struct clk_divider *divider = to_clk_divider(hw);
>> + ? ? unsigned int div;
>> + ? ? unsigned long flags = 0;
>> +
>> + ? ? if (divider->lock)
>> + ? ? ? ? ? ? spin_lock_irqsave(divider->lock, flags);
>> +
>> + ? ? div = readl(divider->reg) >> divider->shift;
>> + ? ? div &= (1 << divider->width) - 1;
>> +
>> + ? ? if (divider->lock)
>> + ? ? ? ? ? ? spin_unlock_irqrestore(divider->lock, flags);
>
> What are you locking against? You are only reading the register.

Hi Rob,

These register-level locks originally came in from the divider &
multiplexer patches from Richard and Sascha and I'm sure they can give
you more details than I.

Basically on their platform they have some 32-bits regs that have a
lot of overlapping clock functions in them, such as enable/disable and
adjusting a divider all in one reg.  Those operations are protected by
different locks (enable spinlock and prepare mutex, respectively) so
some synchronization mechanism is necessary.  On OMAP we don't use
this since we have a billion registers that typically only map to one
clock each.  I also wonder if having device type memory for the
affected regions makes a this irrelevant on ARM... but that wouldn't
matter for non-ARM architectures.  Just a thought.

Regards,
Mike

>
>> +
>> + ? ? if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
>> + ? ? ? ? ? ? div++;
>> +
>> + ? ? return parent_rate / div;
>> +}
>> +EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
>> +
>> +static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
>> + ? ? ? ? ? ? unsigned long *best_parent_rate)
>> +{
>> + ? ? struct clk_divider *divider = to_clk_divider(hw);
>> + ? ? int i, bestdiv = 0;
>> + ? ? unsigned long parent_rate, best = 0, now, maxdiv;
>> +
>> + ? ? maxdiv = (1 << divider->width);
>> +
>> + ? ? if (divider->flags & CLK_DIVIDER_ONE_BASED)
>> + ? ? ? ? ? ? maxdiv--;
>> +
>> + ? ? if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
>> + ? ? ? ? ? ? parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
>> + ? ? ? ? ? ? bestdiv = parent_rate / rate;
>> + ? ? ? ? ? ? bestdiv = bestdiv == 0 ? 1 : bestdiv;
>> + ? ? ? ? ? ? bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
>> + ? ? ? ? ? ? goto out;
>> + ? ? }
>> +
>> + ? ? /*
>> + ? ? ?* The maximum divider we can use without overflowing
>> + ? ? ?* unsigned long in rate * i below
>> + ? ? ?*/
>> + ? ? maxdiv = min(ULONG_MAX / rate, maxdiv);
>> +
>> + ? ? for (i = 1; i <= maxdiv; i++) {
>> + ? ? ? ? ? ? int div;
>> + ? ? ? ? ? ? parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? rate * i);
>> + ? ? ? ? ? ? div = parent_rate / rate;
>> + ? ? ? ? ? ? div = div > maxdiv ? maxdiv : div;
>> + ? ? ? ? ? ? div = div < 1 ? 1 : div;
>> + ? ? ? ? ? ? now = parent_rate / div;
>> +
>> + ? ? ? ? ? ? if (now <= rate && now >= best) {
>> + ? ? ? ? ? ? ? ? ? ? bestdiv = div;
>> + ? ? ? ? ? ? ? ? ? ? best = now;
>> + ? ? ? ? ? ? ? ? ? ? *best_parent_rate = parent_rate;
>> + ? ? ? ? ? ? }
>> + ? ? }
>> +
>> + ? ? if (!bestdiv) {
>> + ? ? ? ? ? ? bestdiv = (1 << divider->width);
>> + ? ? ? ? ? ? parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
>> + ? ? } else {
>> + ? ? ? ? ? ? parent_rate = best * bestdiv;
>> + ? ? }
>> +
>> +out:
>> + ? ? if (best_parent_rate)
>> + ? ? ? ? ? ? *best_parent_rate = parent_rate;
>> +
>> + ? ? return bestdiv;
>> +}
>> +
>> +static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long *prate)
>> +{
>> + ? ? unsigned long best_parent_rate;
>> + ? ? int div = clk_divider_bestdiv(hw, rate, &best_parent_rate);
>> + ? ? if (prate) {
>> + ? ? ? ? ? ? if (best_parent_rate == __clk_get_rate(
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __clk_get_parent(hw->clk)))
>> + ? ? ? ? ? ? ? ? ? ? *prate = 0;
>> + ? ? ? ? ? ? else
>> + ? ? ? ? ? ? ? ? ? ? *prate = best_parent_rate;
>> + ? ? }
>> +
>> + ? ? return best_parent_rate / div;
>> +}
>> +EXPORT_SYMBOL_GPL(clk_divider_round_rate);
>> +
>> +static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
>> +{
>> + ? ? unsigned long best_parent_rate;
>> + ? ? struct clk_divider *divider = to_clk_divider(hw);
>> + ? ? unsigned int div;
>> + ? ? unsigned long flags = 0;
>> + ? ? u32 val;
>> +
>> + ? ? div = clk_divider_bestdiv(hw, rate, &best_parent_rate);
>> +
>> + ? ? if (divider->lock)
>> + ? ? ? ? ? ? spin_lock_irqsave(divider->lock, flags);
>> +
>> + ? ? if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
>> + ? ? ? ? ? ? div--;
>> +
>> + ? ? val = readl(divider->reg);
>> + ? ? val &= ~(((1 << divider->width) - 1) << divider->shift);
>> + ? ? val |= div << divider->shift;
>> + ? ? writel(val, divider->reg);
>> +
>> + ? ? if (divider->lock)
>> + ? ? ? ? ? ? spin_unlock_irqrestore(divider->lock, flags);
>> +
>> + ? ? return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(clk_divider_set_rate);
>> +
>> +struct clk_ops clk_divider_ops = {
>> + ? ? .recalc_rate = clk_divider_recalc_rate,
>> + ? ? .round_rate = clk_divider_round_rate,
>> + ? ? .set_rate = clk_divider_set_rate,
>> +};
>> +EXPORT_SYMBOL_GPL(clk_divider_ops);
>> +
>> +struct clk *clk_register_divider(struct device *dev, const char *name,
>> + ? ? ? ? ? ? const char *parent_name, unsigned long flags,
>> + ? ? ? ? ? ? void __iomem *reg, u8 shift, u8 width,
>> + ? ? ? ? ? ? u8 clk_divider_flags, spinlock_t *lock)
>> +{
>> + ? ? struct clk_divider *div;
>> + ? ? struct clk *clk;
>> +
>> + ? ? div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
>> +
>> + ? ? if (!div) {
>> + ? ? ? ? ? ? pr_err("%s: could not allocate divider clk\n", __func__);
>> + ? ? ? ? ? ? return NULL;
>> + ? ? }
>> +
>> + ? ? /* struct clk_divider assignments */
>> + ? ? div->reg = reg;
>> + ? ? div->shift = shift;
>> + ? ? div->width = width;
>> + ? ? div->flags = clk_divider_flags;
>> + ? ? div->lock = lock;
>> +
>> + ? ? if (parent_name) {
>> + ? ? ? ? ? ? div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
>> + ? ? ? ? ? ? if (!div->parent[0])
>> + ? ? ? ? ? ? ? ? ? ? goto out;
>> + ? ? }
>> +
>> + ? ? clk = clk_register(dev, name,
>> + ? ? ? ? ? ? ? ? ? ? &clk_divider_ops, &div->hw,
>> + ? ? ? ? ? ? ? ? ? ? div->parent,
>> + ? ? ? ? ? ? ? ? ? ? (parent_name ? 1 : 0),
>> + ? ? ? ? ? ? ? ? ? ? flags);
>> + ? ? if (clk)
>> + ? ? ? ? ? ? return clk;
>> +
>> +out:
>> + ? ? kfree(div->parent[0]);
>> + ? ? kfree(div);
>> +
>> + ? ? return NULL;
>> +}
>> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
>> new file mode 100644
>> index 0000000..90c79fb
>> --- /dev/null
>> +++ b/drivers/clk/clk-fixed-rate.c
>> @@ -0,0 +1,82 @@
>> +/*
>> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
>> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Fixed rate clock implementation
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +
>> +/*
>> + * DOC: basic fixed-rate clock that cannot gate
>> + *
>> + * Traits of this clock:
>> + * prepare - clk_(un)prepare only ensures parents are prepared
>> + * enable - clk_enable only ensures parents are enabled
>> + * rate - rate is always a fixed value. ?No clk_set_rate support
>> + * parent - fixed parent. ?No clk_set_parent support
>> + */
>> +
>> +#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
>> +
>> +static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
>> + ? ? ? ? ? ? unsigned long parent_rate)
>> +{
>> + ? ? return to_clk_fixed_rate(hw)->fixed_rate;
>> +}
>> +EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate);
>> +
>> +struct clk_ops clk_fixed_rate_ops = {
>> + ? ? .recalc_rate = clk_fixed_rate_recalc_rate,
>> +};
>> +EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
>> +
>> +struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
>> + ? ? ? ? ? ? const char *parent_name, unsigned long flags,
>> + ? ? ? ? ? ? unsigned long fixed_rate)
>> +{
>> + ? ? struct clk_fixed_rate *fixed;
>> + ? ? char **parent_names = NULL;
>> + ? ? u8 len;
>> +
>> + ? ? fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
>> +
>> + ? ? if (!fixed) {
>> + ? ? ? ? ? ? pr_err("%s: could not allocate fixed clk\n", __func__);
>> + ? ? ? ? ? ? return ERR_PTR(-ENOMEM);
>> + ? ? }
>> +
>> + ? ? /* struct clk_fixed_rate assignments */
>> + ? ? fixed->fixed_rate = fixed_rate;
>> +
>> + ? ? if (parent_name) {
>> + ? ? ? ? ? ? parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
>> +
>> + ? ? ? ? ? ? if (! parent_names)
>> + ? ? ? ? ? ? ? ? ? ? goto out;
>> +
>> + ? ? ? ? ? ? len = sizeof(char) * strlen(parent_name);
>> +
>> + ? ? ? ? ? ? parent_names[0] = kmalloc(len, GFP_KERNEL);
>> +
>> + ? ? ? ? ? ? if (!parent_names[0])
>> + ? ? ? ? ? ? ? ? ? ? goto out;
>> +
>> + ? ? ? ? ? ? strncpy(parent_names[0], parent_name, len);
>> + ? ? }
>> +
>> +out:
>> + ? ? return clk_register(dev, name,
>> + ? ? ? ? ? ? ? ? ? ? &clk_fixed_rate_ops, &fixed->hw,
>> + ? ? ? ? ? ? ? ? ? ? parent_names,
>> + ? ? ? ? ? ? ? ? ? ? (parent_name ? 1 : 0),
>> + ? ? ? ? ? ? ? ? ? ? flags);
>> +}
>> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
>> new file mode 100644
>> index 0000000..5d50efa
>> --- /dev/null
>> +++ b/drivers/clk/clk-gate.c
>> @@ -0,0 +1,157 @@
>> +/*
>> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
>> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Gated clock implementation
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/string.h>
>> +
>> +/**
>> + * DOC: basic gatable clock which can gate and ungate it's ouput
>> + *
>> + * Traits of this clock:
>> + * prepare - clk_(un)prepare only ensures parent is (un)prepared
>> + * enable - clk_enable and clk_disable are functional & control gating
>> + * rate - inherits rate from parent. ?No clk_set_rate support
>> + * parent - fixed parent. ?No clk_set_parent support
>> + */
>> +
>> +#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
>> +
>> +static void clk_gate_set_bit(struct clk_gate *gate)
>> +{
>> + ? ? u32 reg;
>> + ? ? unsigned long flags = 0;
>> +
>> + ? ? if (gate->lock)
>> + ? ? ? ? ? ? spin_lock_irqsave(gate->lock, flags);
>> +
>> + ? ? reg = readl(gate->reg);
>> + ? ? reg |= BIT(gate->bit_idx);
>> + ? ? writel(reg, gate->reg);
>> +
>> + ? ? if (gate->lock)
>> + ? ? ? ? ? ? spin_unlock_irqrestore(gate->lock, flags);
>> +}
>> +
>> +static void clk_gate_clear_bit(struct clk_gate *gate)
>> +{
>> + ? ? u32 reg;
>> + ? ? unsigned long flags = 0;
>> +
>> + ? ? if (gate->lock)
>> + ? ? ? ? ? ? spin_lock_irqsave(gate->lock, flags);
>> +
>> + ? ? reg = readl(gate->reg);
>> + ? ? reg &= ~BIT(gate->bit_idx);
>> + ? ? writel(reg, gate->reg);
>> +
>> + ? ? if (gate->lock)
>> + ? ? ? ? ? ? spin_unlock_irqrestore(gate->lock, flags);
>> +}
>> +
>> +static int clk_gate_enable(struct clk_hw *hw)
>> +{
>> + ? ? struct clk_gate *gate = to_clk_gate(hw);
>> +
>> + ? ? if (gate->flags & CLK_GATE_SET_TO_DISABLE)
>> + ? ? ? ? ? ? clk_gate_clear_bit(gate);
>> + ? ? else
>> + ? ? ? ? ? ? clk_gate_set_bit(gate);
>> +
>> + ? ? return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(clk_gate_enable);
>> +
>> +static void clk_gate_disable(struct clk_hw *hw)
>> +{
>> + ? ? struct clk_gate *gate = to_clk_gate(hw);
>> +
>> + ? ? if (gate->flags & CLK_GATE_SET_TO_DISABLE)
>> + ? ? ? ? ? ? clk_gate_set_bit(gate);
>> + ? ? else
>> + ? ? ? ? ? ? clk_gate_clear_bit(gate);
>> +}
>> +EXPORT_SYMBOL_GPL(clk_gate_disable);
>> +
>> +static int clk_gate_is_enabled(struct clk_hw *hw)
>> +{
>> + ? ? u32 reg;
>> + ? ? unsigned long flags = 0;
>> + ? ? struct clk_gate *gate = to_clk_gate(hw);
>> +
>> + ? ? if (gate->lock)
>> + ? ? ? ? ? ? spin_lock_irqsave(gate->lock, flags);
>> +
>> + ? ? reg = readl(gate->reg);
>> +
>> + ? ? if (gate->lock)
>> + ? ? ? ? ? ? spin_unlock_irqrestore(gate->lock, flags);
>> +
>
> ditto.
>
>> + ? ? /* if a set bit disables this clk, flip it before masking */
>> + ? ? if (gate->flags & CLK_GATE_SET_TO_DISABLE)
>> + ? ? ? ? ? ? reg ^= BIT(gate->bit_idx);
>> +
>> + ? ? reg &= BIT(gate->bit_idx);
>> +
>> + ? ? return reg ? 1 : 0;
>> +}
>> +EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
>> +
>> +struct clk_ops clk_gate_ops = {
>> + ? ? .enable = clk_gate_enable,
>> + ? ? .disable = clk_gate_disable,
>> + ? ? .is_enabled = clk_gate_is_enabled,
>> +};
>> +EXPORT_SYMBOL_GPL(clk_gate_ops);
>> +
>> +struct clk *clk_register_gate(struct device *dev, const char *name,
>> + ? ? ? ? ? ? const char *parent_name, unsigned long flags,
>> + ? ? ? ? ? ? void __iomem *reg, u8 bit_idx,
>> + ? ? ? ? ? ? u8 clk_gate_flags, spinlock_t *lock)
>> +{
>> + ? ? struct clk_gate *gate;
>> + ? ? struct clk *clk;
>> +
>> + ? ? gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
>> +
>> + ? ? if (!gate) {
>> + ? ? ? ? ? ? pr_err("%s: could not allocate gated clk\n", __func__);
>> + ? ? ? ? ? ? return NULL;
>> + ? ? }
>> +
>> + ? ? /* struct clk_gate assignments */
>> + ? ? gate->reg = reg;
>> + ? ? gate->bit_idx = bit_idx;
>> + ? ? gate->flags = clk_gate_flags;
>> + ? ? gate->lock = lock;
>> +
>> + ? ? if (parent_name) {
>> + ? ? ? ? ? ? gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
>> + ? ? ? ? ? ? if (!gate->parent[0])
>> + ? ? ? ? ? ? ? ? ? ? goto out;
>> + ? ? }
>> +
>> + ? ? clk = clk_register(dev, name,
>> + ? ? ? ? ? ? ? ? ? ? &clk_gate_ops, &gate->hw,
>> + ? ? ? ? ? ? ? ? ? ? gate->parent,
>> + ? ? ? ? ? ? ? ? ? ? (parent_name ? 1 : 0),
>> + ? ? ? ? ? ? ? ? ? ? flags);
>> + ? ? if (clk)
>> + ? ? ? ? ? ? return clk;
>> +out:
>> + ? ? kfree(gate->parent[0]);
>> + ? ? kfree(gate);
>> +
>> + ? ? return NULL;
>> +}
>> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
>> new file mode 100644
>> index 0000000..6fc0878
>> --- /dev/null
>> +++ b/drivers/clk/clk-mux.c
>> @@ -0,0 +1,123 @@
>> +/*
>> + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
>> + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
>> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Simple multiplexer clock implementation
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +
>> +/*
>> + * DOC: basic adjustable multiplexer clock that cannot gate
>> + *
>> + * Traits of this clock:
>> + * prepare - clk_prepare only ensures that parents are prepared
>> + * enable - clk_enable only ensures that parents are enabled
>> + * rate - rate is only affected by parent switching. ?No clk_set_rate support
>> + * parent - parent is adjustable through clk_set_parent
>> + */
>> +
>> +#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
>> +
>> +static u8 clk_mux_get_parent(struct clk_hw *hw)
>> +{
>> + ? ? struct clk_mux *mux = to_clk_mux(hw);
>> + ? ? u32 val;
>> + ? ? unsigned long flags = 0;
>> +
>> + ? ? if (mux->lock)
>> + ? ? ? ? ? ? spin_lock_irqsave(mux->lock, flags);
>> +
>> + ? ? /*
>> + ? ? ?* FIXME need a mux-specific flag to determine if val is bitwise or numeric
>> + ? ? ?* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
>> + ? ? ?* to 0x7 (index starts at one)
>> + ? ? ?* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
>> + ? ? ?* val = 0x4 really means "bit 2, index starts at bit 0"
>> + ? ? ?*/
>> + ? ? val = readl(mux->reg) >> mux->shift;
>> + ? ? val &= (1 << mux->width) - 1;
>> +
>> + ? ? if (mux->lock)
>> + ? ? ? ? ? ? spin_unlock_irqrestore(mux->lock, flags);
>
> ditto
>
>> +
>> + ? ? if (val && (mux->flags & CLK_MUX_INDEX_BIT))
>> + ? ? ? ? ? ? val = ffs(val) - 1;
>> +
>> + ? ? if (val && (mux->flags & CLK_MUX_INDEX_ONE))
>> + ? ? ? ? ? ? val--;
>> +
>> + ? ? if (val >= __clk_get_num_parents(hw->clk))
>> + ? ? ? ? ? ? return -EINVAL;
>> +
>> + ? ? return val;
>> +}
>> +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
>> +
>> +static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> +{
>> + ? ? struct clk_mux *mux = to_clk_mux(hw);
>> + ? ? u32 val;
>> + ? ? unsigned long flags = 0;
>> +
>> + ? ? if (mux->flags & CLK_MUX_INDEX_BIT)
>> + ? ? ? ? ? ? index = (1 << ffs(index));
>> +
>> + ? ? if (mux->flags & CLK_MUX_INDEX_ONE)
>> + ? ? ? ? ? ? index++;
>> +
>> + ? ? if (mux->lock)
>> + ? ? ? ? ? ? spin_lock_irqsave(mux->lock, flags);
>> +
>> + ? ? val = readl(mux->reg);
>> + ? ? val &= ~(((1 << mux->width) - 1) << mux->shift);
>> + ? ? val |= index << mux->shift;
>> + ? ? writel(val, mux->reg);
>> +
>> + ? ? if (mux->lock)
>> + ? ? ? ? ? ? spin_unlock_irqrestore(mux->lock, flags);
>> +
>> + ? ? return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(clk_mux_set_parent);
>> +
>> +struct clk_ops clk_mux_ops = {
>> + ? ? .get_parent = clk_mux_get_parent,
>> + ? ? .set_parent = clk_mux_set_parent,
>> +};
>> +EXPORT_SYMBOL_GPL(clk_mux_ops);
>> +
>> +struct clk *clk_register_mux(struct device *dev, const char *name,
>> + ? ? ? ? ? ? char **parent_names, u8 num_parents, unsigned long flags,
>> + ? ? ? ? ? ? void __iomem *reg, u8 shift, u8 width,
>> + ? ? ? ? ? ? u8 clk_mux_flags, spinlock_t *lock)
>> +{
>> + ? ? struct clk_mux *mux;
>> +
>> + ? ? mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL);
>> +
>> + ? ? if (!mux) {
>> + ? ? ? ? ? ? pr_err("%s: could not allocate mux clk\n", __func__);
>> + ? ? ? ? ? ? return ERR_PTR(-ENOMEM);
>> + ? ? }
>> +
>> + ? ? /* struct clk_mux assignments */
>> + ? ? mux->reg = reg;
>> + ? ? mux->shift = shift;
>> + ? ? mux->width = width;
>> + ? ? mux->flags = clk_mux_flags;
>> + ? ? mux->lock = lock;
>> +
>> + ? ? return clk_register(dev, name, &clk_mux_ops, &mux->hw,
>> + ? ? ? ? ? ? ? ? ? ? parent_names, num_parents, flags);
>> +}
>> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
>> index 33bf6a7..9d5c4b1 100644
>> --- a/include/linux/clk-private.h
>> +++ b/include/linux/clk-private.h
>> @@ -45,6 +45,130 @@ struct clk {
>> ?#endif
>> ?};
>>
>> +/*
>> + * DOC: Basic clock implementations common to many platforms
>> + *
>> + * Each basic clock hardware type is comprised of a structure describing the
>> + * clock hardware, implementations of the relevant callbacks in struct clk_ops,
>> + * unique flags for that hardware type, a registration function and an
>> + * alternative macro for static initialization
>> + */
>> +
>> +extern struct clk_ops clk_fixed_rate_ops;
>> +
>> +#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, ? ? ? ? ?\
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? _fixed_rate_flags) ? ? ? ? ? ? ?\
>> + ? ? static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static char *_name##_parent_names[] = {}; ? ? ? ? ? ? ? \
>> + ? ? static struct clk_fixed_rate _name##_hw = { ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? .clk = &_name, ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .fixed_rate = _rate, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .flags = _fixed_rate_flags, ? ? ? ? ? ? ? ? ? ? \
>> + ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .ops = &clk_fixed_rate_ops, ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .parent_names = _name##_parent_names, ? ? ? ? ? \
>> + ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##_parent_names), ? ? ? \
>> + ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? };
>> +
>> +extern struct clk_ops clk_gate_ops;
>> +
>> +#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, ? ?\
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? _flags, _reg, _bit_idx, ? ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? _gate_flags, _lock) ? ? ? ? ? ? \
>> + ? ? static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static char *_name##_parent_names[] = { ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? _parent_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk *_name##_parents[] = { ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? _parent_ptr, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk_gate _name##_hw = { ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? .clk = &_name, ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .reg = _reg, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .bit_idx = _bit_idx, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .flags = _gate_flags, ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .lock = _lock, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .ops = &clk_gate_ops, ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .parent_names = _name##_parent_names, ? ? ? ? ? \
>> + ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##_parent_names), ? ? ? \
>> + ? ? ? ? ? ? .parents = _name##_parents, ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? };
>> +
>> +extern struct clk_ops clk_divider_ops;
>> +
>> +#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? _flags, _reg, _shift, _width, ? \
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? _divider_flags, _lock) ? ? ? ? ?\
>> + ? ? static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static char *_name##_parent_names[] = { ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? _parent_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk *_name##_parents[] = { ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? _parent_ptr, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk_divider _name##_hw = { ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? .clk = &_name, ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .reg = _reg, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .shift = _shift, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .width = _width, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .flags = _divider_flags, ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .lock = _lock, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .ops = &clk_divider_ops, ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .parent_names = _name##_parent_names, ? ? ? ? ? \
>> + ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##_parent_names), ? ? ? \
>> + ? ? ? ? ? ? .parents = _name##_parents, ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? };
>> +
>> +extern struct clk_ops clk_mux_ops;
>> +
>> +#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? _reg, _shift, _width, ? ? ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? _mux_flags, _lock) ? ? ? ? ? ? ?\
>> + ? ? static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk_mux _name##_hw = { ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? .clk = &_name, ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .reg = _reg, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .shift = _shift, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .width = _width, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .flags = _mux_flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .lock = _lock, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .ops = &clk_mux_ops, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? .parent_names = _parent_names, ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_parent_names), ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .parents = _parents, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? };
>> +
>> ?/**
>> ? * __clk_init - initialize the data structures in a struct clk
>> ? * @dev: ? ? device initializing this clk, placeholder for now
>> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
>> index 09dea1f..853d526 100644
>> --- a/include/linux/clk-provider.h
>> +++ b/include/linux/clk-provider.h
>> @@ -129,6 +129,133 @@ struct clk_ops {
>> ? ? ? void ? ? ? ? ? ?(*init)(struct clk_hw *hw);
>> ?};
>>
>> +/*
>> + * DOC: Basic clock implementations common to many platforms
>> + *
>> + * Each basic clock hardware type is comprised of a structure describing the
>> + * clock hardware, implementations of the relevant callbacks in struct clk_ops,
>> + * unique flags for that hardware type, a registration function and an
>> + * alternative macro for static initialization
>> + */
>> +
>> +/**
>> + * struct clk_fixed_rate - fixed-rate clock
>> + * @hw: ? ? ? ? ? ? ?handle between common and hardware-specific interfaces
>> + * @fixed_rate: ? ? ?constant frequency of clock
>> + */
>> +struct clk_fixed_rate {
>> + ? ? struct ? ? ? ? ?clk_hw hw;
>> + ? ? unsigned long ? fixed_rate;
>> + ? ? u8 ? ? ? ? ? ? ?flags;
>> +};
>> +
>> +struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
>> + ? ? ? ? ? ? const char *parent_name, unsigned long flags,
>> + ? ? ? ? ? ? unsigned long fixed_rate);
>> +
>> +/**
>> + * struct clk_gate - gating clock
>> + *
>> + * @hw: ? ? ? ? ? ? ?handle between common and hardware-specific interfaces
>> + * @reg: ? ? register controlling gate
>> + * @bit_idx: single bit controlling gate
>> + * @flags: ? hardware-specific flags
>> + * @lock: ? ?register lock
>> + *
>> + * Clock which can gate its output. ?Implements .enable & .disable
>> + *
>> + * Flags:
>> + * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
>> + * ? enable the clock. ?Setting this flag does the opposite: setting the bit
>> + * ? disable the clock and clearing it enables the clock
>> + */
>> +struct clk_gate {
>> + ? ? struct clk_hw hw;
>> + ? ? void __iomem ? ?*reg;
>> + ? ? u8 ? ? ? ? ? ? ?bit_idx;
>> + ? ? u8 ? ? ? ? ? ? ?flags;
>> + ? ? spinlock_t ? ? ?*lock;
>> + ? ? char ? ? ? ? ? ?*parent[1];
>> +};
>> +
>> +#define CLK_GATE_SET_TO_DISABLE ? ? ? ? ? ? ?BIT(0)
>> +
>> +struct clk *clk_register_gate(struct device *dev, const char *name,
>> + ? ? ? ? ? ? const char *parent_name, unsigned long flags,
>> + ? ? ? ? ? ? void __iomem *reg, u8 bit_idx,
>> + ? ? ? ? ? ? u8 clk_gate_flags, spinlock_t *lock);
>> +
>> +/**
>> + * struct clk_divider - adjustable divider clock
>> + *
>> + * @hw: ? ? ? ? ? ? ?handle between common and hardware-specific interfaces
>> + * @reg: ? ? register containing the divider
>> + * @shift: ? shift to the divider bit field
>> + * @width: ? width of the divider bit field
>> + * @lock: ? ?register lock
>> + *
>> + * Clock with an adjustable divider affecting its output frequency. ?Implements
>> + * .recalc_rate, .set_rate and .round_rate
>> + *
>> + * Flags:
>> + * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
>> + * ? register plus one. ?If CLK_DIVIDER_ONE_BASED is set then the divider is
>> + * ? the raw value read from the register, with the value of zero considered
>> + * ? invalid
>> + * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
>> + * ? the hardware register
>> + */
>> +struct clk_divider {
>> + ? ? struct clk_hw ? hw;
>> + ? ? void __iomem ? ?*reg;
>> + ? ? u8 ? ? ? ? ? ? ?shift;
>> + ? ? u8 ? ? ? ? ? ? ?width;
>> + ? ? u8 ? ? ? ? ? ? ?flags;
>> + ? ? spinlock_t ? ? ?*lock;
>> + ? ? char ? ? ? ? ? ?*parent[1];
>> +};
>> +
>> +#define CLK_DIVIDER_ONE_BASED ? ? ? ? ? ? ? ?BIT(0)
>> +#define CLK_DIVIDER_POWER_OF_TWO ? ? BIT(1)
>> +
>> +struct clk *clk_register_divider(struct device *dev, const char *name,
>> + ? ? ? ? ? ? const char *parent_name, unsigned long flags,
>> + ? ? ? ? ? ? void __iomem *reg, u8 shift, u8 width,
>> + ? ? ? ? ? ? u8 clk_divider_flags, spinlock_t *lock);
>> +
>> +/**
>> + * struct clk_mux - multiplexer clock
>> + *
>> + * @hw: ? ? ? ? ? ? ?handle between common and hardware-specific interfaces
>> + * @reg: ? ? register controlling multiplexer
>> + * @shift: ? shift to multiplexer bit field
>> + * @width: ? width of mutliplexer bit field
>> + * @num_clks: ? ? ? ?number of parent clocks
>> + * @lock: ? ?register lock
>> + *
>> + * Clock with multiple selectable parents. ?Implements .get_parent, .set_parent
>> + * and .recalc_rate
>> + *
>> + * Flags:
>> + * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
>> + * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two)
>> + */
>> +struct clk_mux {
>> + ? ? struct clk_hw ? hw;
>> + ? ? void __iomem ? ?*reg;
>> + ? ? u8 ? ? ? ? ? ? ?shift;
>> + ? ? u8 ? ? ? ? ? ? ?width;
>> + ? ? u8 ? ? ? ? ? ? ?flags;
>> + ? ? spinlock_t ? ? ?*lock;
>> +};
>> +
>> +#define CLK_MUX_INDEX_ONE ? ? ? ? ? ?BIT(0)
>> +#define CLK_MUX_INDEX_BIT ? ? ? ? ? ?BIT(1)
>> +
>> +struct clk *clk_register_mux(struct device *dev, const char *name,
>> + ? ? ? ? ? ? char **parent_names, u8 num_parents, unsigned long flags,
>> + ? ? ? ? ? ? void __iomem *reg, u8 shift, u8 width,
>> + ? ? ? ? ? ? u8 clk_mux_flags, spinlock_t *lock);
>>
>> ?/**
>> ? * clk_register - allocate a new clock, register it and return an opaque cookie
>
>
> _______________________________________________
> linaro-dev mailing list
> linaro-dev at lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-dev


From robherring2 at gmail.com  Sun Mar 11 17:08:16 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sun, 11 Mar 2012 16:08:16 -0500
Subject: [PATCH 0/4] mach/io.h cleanup fixes
Message-ID: <1331500100-31351-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

This is a couple of fixes to mach/io.h clean-up series. The first 2 patches
are a couple of compile fixes. The 3rd patch creates a common definition of
IOMEM() macros. The 4th patch uses the common IOMEM() definition to fix
incorrect usages of __io() macro.

This applies on top of io-cleanup-for-3.4 branch already pulled into
arm-soc.

Rob

Rob Herring (4):
  ARM: fix ioremap/iounmap for !CONFIG_MMU
  ARM: iop13xx: fix missing declaration of iop13xx_init_early
  ARM: create a common IOMEM definition
  ARM: __io abuse cleanup

 arch/arm/include/asm/assembler.h                |    2 ++
 arch/arm/include/asm/io.h                       |    2 ++
 arch/arm/kernel/debug.S                         |    1 +
 arch/arm/kernel/entry-armv.S                    |    1 +
 arch/arm/mach-cns3xxx/core.c                    |    8 ++++----
 arch/arm/mach-cns3xxx/devices.c                 |    2 +-
 arch/arm/mach-davinci/include/mach/hardware.h   |    6 ------
 arch/arm/mach-davinci/include/mach/uncompress.h |    2 ++
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |    9 ---------
 arch/arm/mach-iop13xx/include/mach/iop13xx.h    |    1 +
 arch/arm/mach-mmp/include/mach/addr-map.h       |    6 ------
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |    6 ------
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    6 ------
 arch/arm/mach-mxs/include/mach/hardware.h       |    6 ------
 arch/arm/mach-netx/generic.c                    |    2 +-
 arch/arm/mach-netx/include/mach/hardware.h      |    2 +-
 arch/arm/mach-netx/include/mach/netx-regs.h     |   16 ++++++++--------
 arch/arm/mach-omap1/ams-delta-fiq-handler.S     |    1 +
 arch/arm/mach-omap1/iomap.h                     |    6 ------
 arch/arm/mach-omap2/clock3xxx_data.c            |    1 +
 arch/arm/mach-omap2/clock44xx_data.c            |    1 +
 arch/arm/mach-omap2/iomap.h                     |    6 ------
 arch/arm/mach-realview/include/mach/hardware.h  |    2 +-
 arch/arm/mach-rpc/include/mach/hardware.h       |    6 ------
 arch/arm/mach-shmobile/board-ag5evm.c           |    2 +-
 arch/arm/mach-shmobile/board-bonito.c           |    2 +-
 arch/arm/mach-shmobile/board-kota2.c            |    2 +-
 arch/arm/mach-shmobile/intc-r8a7779.c           |    4 ++--
 arch/arm/mach-shmobile/intc-sh73a0.c            |    4 ++--
 arch/arm/mach-shmobile/smp-r8a7779.c            |    4 ++--
 arch/arm/mach-shmobile/smp-sh73a0.c             |   20 ++++++++++----------
 arch/arm/mach-spear3xx/clock.c                  |    1 +
 arch/arm/mach-spear6xx/clock.c                  |    1 +
 arch/arm/mach-tegra/include/mach/iomap.h        |    6 ------
 arch/arm/mach-u300/include/mach/u300-regs.h     |    6 ------
 arch/arm/mach-ux500/include/mach/hardware.h     |    2 +-
 arch/arm/mm/nommu.c                             |    8 ++++++--
 arch/arm/plat-mxc/include/mach/hardware.h       |    6 ------
 arch/arm/plat-omap/include/plat/hardware.h      |    6 ------
 arch/arm/plat-omap/include/plat/usb.h           |    1 -
 arch/arm/plat-spear/include/plat/hardware.h     |    6 ------
 41 files changed, 56 insertions(+), 126 deletions(-)

-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar 12 07:58:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 12 Mar 2012 19:58:53 +0800
Subject: [PATCH v4 06/10] ASoC: fsl: check property 'compatible' for the
 machine name
In-Reply-To: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331553537-19789-7-git-send-email-shawn.guo@linaro.org>

Check /compatible rather than /model to determine the machine name.
The p1022ds older device trees get a different /model from the new
ones, while /compatible is consistent there, so checking /compatible
will save the bother of detecting older p1022ds device trees.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c      |    6 +++---
 sound/soc/fsl/mpc8610_hpcd.c |    2 +-
 sound/soc/fsl/p1022_ds.c     |   32 +++++---------------------------
 3 files changed, 9 insertions(+), 31 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 3e06696..2eb407f 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -716,12 +716,12 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 	}
 
 	/* Trigger the machine driver's probe function.  The platform driver
-	 * name of the machine driver is taken from the /model property of the
+	 * name of the machine driver is taken from /compatible property of the
 	 * device tree.  We also pass the address of the CPU DAI driver
 	 * structure.
 	 */
-	sprop = of_get_property(of_find_node_by_path("/"), "model", NULL);
-	/* Sometimes the model name has a "fsl," prefix, so we strip that. */
+	sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
+	/* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
 	p = strrchr(sprop, ',');
 	if (p)
 		sprop = p + 1;
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index 354b753..8fdc430 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -402,7 +402,7 @@ static struct platform_driver mpc8610_hpcd_driver = {
 	.probe = mpc8610_hpcd_probe,
 	.remove = __devexit_p(mpc8610_hpcd_remove),
 	.driver = {
-		/* The name must match the 'model' property in the device tree,
+		/* The name must match 'compatible' property in the device tree,
 		 * in lowercase letters.
 		 */
 		.name = "snd-soc-mpc8610hpcd",
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index e87cb41..0f42f31 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -403,6 +403,11 @@ static struct platform_driver p1022_ds_driver = {
 	.probe = p1022_ds_probe,
 	.remove = __devexit_p(p1022_ds_remove),
 	.driver = {
+		/*
+		 * The name must match 'compatible' property in the device tree,
+		 * in lowercase letters.
+		 */
+		.name = "snd-soc-p1022ds",
 		.owner = THIS_MODULE,
 	},
 };
@@ -416,33 +421,6 @@ static int __init p1022_ds_init(void)
 {
 	struct device_node *guts_np;
 	struct resource res;
-	const char *sprop;
-
-	/*
-	 * Check if we're actually running on a P1022DS.  Older device trees
-	 * have a model of "fsl,P1022" and newer ones use "fsl,P1022DS", so we
-	 * need to support both.  The SSI driver uses that property to link to
-	 * the machine driver, so have to match it.
-	 */
-	sprop = of_get_property(of_find_node_by_path("/"), "model", NULL);
-	if (!sprop) {
-		pr_err("snd-soc-p1022ds: missing /model node");
-		return -ENODEV;
-	}
-
-	pr_debug("snd-soc-p1022ds: board model name is %s\n", sprop);
-
-	/*
-	 * The name of this board, taken from the device tree.  Normally, this is a*
-	 * fixed string, but some P1022DS device trees have a /model property of
-	 * "fsl,P1022", and others have "fsl,P1022DS".
-	 */
-	if (strcasecmp(sprop, "fsl,p1022ds") == 0)
-		p1022_ds_driver.driver.name = "snd-soc-p1022ds";
-	else if (strcasecmp(sprop, "fsl,p1022") == 0)
-		p1022_ds_driver.driver.name = "snd-soc-p1022";
-	else
-		return -ENODEV;
 
 	/* Get the physical address of the global utilities registers */
 	guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
-- 
1.7.5.4



From robherring2 at gmail.com  Sun Mar 11 17:08:20 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sun, 11 Mar 2012 16:08:20 -0500
Subject: [PATCH 4/4] ARM: __io abuse cleanup
In-Reply-To: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331500100-31351-5-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Several platforms incorrectly use __io() for casting to 'void __iomem *'.
This converts all of those uses to use the common IOMEM macro.

Reported-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Anton Vorontsov <avorontsov at mvista.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Paul Mundt <lethal at linux-sh.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: linux-sh at vger.kernel.org
---
 arch/arm/mach-cns3xxx/core.c                   |    8 ++++----
 arch/arm/mach-cns3xxx/devices.c                |    2 +-
 arch/arm/mach-netx/generic.c                   |    2 +-
 arch/arm/mach-netx/include/mach/hardware.h     |    2 +-
 arch/arm/mach-netx/include/mach/netx-regs.h    |   16 ++++++++--------
 arch/arm/mach-realview/include/mach/hardware.h |    2 +-
 arch/arm/mach-shmobile/board-ag5evm.c          |    2 +-
 arch/arm/mach-shmobile/board-bonito.c          |    2 +-
 arch/arm/mach-shmobile/board-kota2.c           |    2 +-
 arch/arm/mach-shmobile/intc-r8a7779.c          |    4 ++--
 arch/arm/mach-shmobile/intc-sh73a0.c           |    4 ++--
 arch/arm/mach-shmobile/smp-r8a7779.c           |    4 ++--
 arch/arm/mach-shmobile/smp-sh73a0.c            |   20 ++++++++++----------
 arch/arm/mach-ux500/include/mach/hardware.h    |    2 +-
 14 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 941a308..031805b 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -72,13 +72,13 @@ void __init cns3xxx_map_io(void)
 /* used by entry-macro.S */
 void __init cns3xxx_init_irq(void)
 {
-	gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
-		 __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
+	gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
+		 IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
 }
 
 void cns3xxx_power_off(void)
 {
-	u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
+	u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
 	u32 clkctrl;
 
 	printk(KERN_INFO "powering system down...\n");
@@ -237,7 +237,7 @@ static void __init __cns3xxx_timer_init(unsigned int timer_irq)
 
 static void __init cns3xxx_timer_init(void)
 {
-	cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
+	cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);
 
 	__cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
 }
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
index 79d1fb0..1e40c99 100644
--- a/arch/arm/mach-cns3xxx/devices.c
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -98,7 +98,7 @@ static struct platform_device cns3xxx_sdhci_pdev = {
 
 void __init cns3xxx_sdhci_init(void)
 {
-	u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+	u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
 	u32 gpioa_pins = __raw_readl(gpioa);
 
 	/* MMC/SD pins share with GPIOA */
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 59e6797..aa62746 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -168,7 +168,7 @@ void __init netx_init_irq(void)
 {
 	int irq;
 
-	vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
+	vic_init(io_p2v(NETX_PA_VIC), 0, ~0, 0);
 
 	for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
 		irq_set_chip_and_handler(irq, &netx_hif_chip,
diff --git a/arch/arm/mach-netx/include/mach/hardware.h b/arch/arm/mach-netx/include/mach/hardware.h
index 517a2bd..b661af2 100644
--- a/arch/arm/mach-netx/include/mach/hardware.h
+++ b/arch/arm/mach-netx/include/mach/hardware.h
@@ -33,7 +33,7 @@
 #define XMAC_MEM_SIZE 0x1000
 #define SRAM_MEM_SIZE 0x8000
 
-#define io_p2v(x) ((x) - NETX_IO_PHYS + NETX_IO_VIRT)
+#define io_p2v(x) IOMEM((x) - NETX_IO_PHYS + NETX_IO_VIRT)
 #define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS)
 
 #endif
diff --git a/arch/arm/mach-netx/include/mach/netx-regs.h b/arch/arm/mach-netx/include/mach/netx-regs.h
index 5a03e7c..fdde22b 100644
--- a/arch/arm/mach-netx/include/mach/netx-regs.h
+++ b/arch/arm/mach-netx/include/mach/netx-regs.h
@@ -115,7 +115,7 @@
  *********************************/
 
 /* Registers */
-#define NETX_SYSTEM_REG(ofs)            __io(NETX_VA_SYSTEM + (ofs))
+#define NETX_SYSTEM_REG(ofs)            IOMEM(NETX_VA_SYSTEM + (ofs))
 #define NETX_SYSTEM_BOO_SR          NETX_SYSTEM_REG(0x00)
 #define NETX_SYSTEM_IOC_CR          NETX_SYSTEM_REG(0x04)
 #define NETX_SYSTEM_IOC_MR          NETX_SYSTEM_REG(0x08)
@@ -185,7 +185,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_GPIO_REG(ofs)                     __io(NETX_VA_GPIO + (ofs))
+#define NETX_GPIO_REG(ofs)                     IOMEM(NETX_VA_GPIO + (ofs))
 #define NETX_GPIO_CFG(gpio)                NETX_GPIO_REG(0x0  + ((gpio)<<2))
 #define NETX_GPIO_THRESHOLD_CAPTURE(gpio)  NETX_GPIO_REG(0x40 + ((gpio)<<2))
 #define NETX_GPIO_COUNTER_CTRL(counter)    NETX_GPIO_REG(0x80 + ((counter)<<2))
@@ -230,7 +230,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_PIO_REG(ofs)        __io(NETX_VA_PIO + (ofs))
+#define NETX_PIO_REG(ofs)        IOMEM(NETX_VA_PIO + (ofs))
 #define NETX_PIO_INPIO       NETX_PIO_REG(0x0)
 #define NETX_PIO_OUTPIO      NETX_PIO_REG(0x4)
 #define NETX_PIO_OEPIO       NETX_PIO_REG(0x8)
@@ -240,7 +240,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_MIIMU           __io(NETX_VA_MIIMU)
+#define NETX_MIIMU           IOMEM(NETX_VA_MIIMU)
 
 /* Bits */
 #define MIIMU_SNRDY        (1<<0)
@@ -317,7 +317,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_PFIFO_REG(ofs)               __io(NETX_VA_PFIFO + (ofs))
+#define NETX_PFIFO_REG(ofs)               IOMEM(NETX_VA_PFIFO + (ofs))
 #define NETX_PFIFO_BASE(pfifo)        NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
 #define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
 #define NETX_PFIFO_RESET              NETX_PFIFO_REG(0x100)
@@ -334,7 +334,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_MEMCR_REG(ofs)               __io(NETX_VA_MEMCR + (ofs))
+#define NETX_MEMCR_REG(ofs)               IOMEM(NETX_VA_MEMCR + (ofs))
 #define NETX_MEMCR_SRAM_CTRL(cs)      NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */
 #define NETX_MEMCR_SDRAM_CFG_CTRL     NETX_MEMCR_REG(0x40)
 #define NETX_MEMCR_SDRAM_TIMING_CTRL  NETX_MEMCR_REG(0x44)
@@ -355,7 +355,7 @@
  *******************************/
 
 /* Registers */
-#define NETX_DPMAS_REG(ofs)               __io(NETX_VA_DPMAS + (ofs))
+#define NETX_DPMAS_REG(ofs)               IOMEM(NETX_VA_DPMAS + (ofs))
 #define NETX_DPMAS_SYS_STAT           NETX_DPMAS_REG(0x4d8)
 #define NETX_DPMAS_INT_STAT           NETX_DPMAS_REG(0x4e0)
 #define NETX_DPMAS_INT_EN             NETX_DPMAS_REG(0x4f0)
@@ -425,7 +425,7 @@
 /*******************************
  * I2C                         *
  *******************************/
-#define NETX_I2C_REG(ofs)	__io(NETX_VA_I2C, (ofs))
+#define NETX_I2C_REG(ofs)	IOMEM(NETX_VA_I2C, (ofs))
 #define NETX_I2C_CTRL	NETX_I2C_REG(0x0)
 #define NETX_I2C_DATA	NETX_I2C_REG(0x4)
 
diff --git a/arch/arm/mach-realview/include/mach/hardware.h b/arch/arm/mach-realview/include/mach/hardware.h
index 8a638d1..281e71c 100644
--- a/arch/arm/mach-realview/include/mach/hardware.h
+++ b/arch/arm/mach-realview/include/mach/hardware.h
@@ -37,6 +37,6 @@
 #else
 #define IO_ADDRESS(x)		(x)
 #endif
-#define __io_address(n)		__io(IO_ADDRESS(n))
+#define __io_address(n)		IOMEM(IO_ADDRESS(n))
 
 #endif
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index eff8a96..5346529 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -615,7 +615,7 @@ static void __init ag5evm_init(void)
 
 #ifdef CONFIG_CACHE_L2X0
 	/* Shared attribute override enable, 64K*8way */
-	l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
+	l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
 #endif
 	sh73a0_add_standard_devices();
 	platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 4d22016..91d4c22 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -394,7 +394,7 @@ static void __init bonito_init(void)
 
 #ifdef CONFIG_CACHE_L2X0
 	/* Early BRESP enable, Shared attribute override enable, 32K*8way */
-	l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
+	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
 #endif
 
 	r8a7740_add_standard_devices();
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 857ceee..4cf6100 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -530,7 +530,7 @@ static void __init kota2_init(void)
 
 #ifdef CONFIG_CACHE_L2X0
 	/* Early BRESP enable, Shared attribute override enable, 64K*8way */
-	l2x0_init(__io(0xf0100000), 0x40460000, 0x82000fff);
+	l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
 #endif
 	sh73a0_add_standard_devices();
 	platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index 5d92fcd..550b23d 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -42,8 +42,8 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 
 void __init r8a7779_init_irq(void)
 {
-	void __iomem *gic_dist_base = __io(0xf0001000);
-	void __iomem *gic_cpu_base = __io(0xf0000100);
+	void __iomem *gic_dist_base = IOMEM(0xf0001000);
+	void __iomem *gic_cpu_base = IOMEM(0xf0000100);
 
 	/* use GIC to handle interrupts */
 	gic_init(0, 29, gic_dist_base, gic_cpu_base);
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 1eda6b0..dbb4357 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -419,8 +419,8 @@ static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
 
 void __init sh73a0_init_irq(void)
 {
-	void __iomem *gic_dist_base = __io(0xf0001000);
-	void __iomem *gic_cpu_base = __io(0xf0000100);
+	void __iomem *gic_dist_base = IOMEM(0xf0001000);
+	void __iomem *gic_cpu_base = IOMEM(0xf0000100);
 	void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
 	int k, n;
 
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 4fe2e9e..6d5e57d 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -30,7 +30,7 @@
 #include <asm/smp_twd.h>
 #include <asm/hardware/gic.h>
 
-#define AVECR 0xfe700040
+#define AVECR IOMEM(0xfe700040)
 
 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
 	.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
@@ -140,7 +140,7 @@ void __init r8a7779_smp_prepare_cpus(void)
 	scu_enable(scu_base_addr());
 
 	/* Map the reset vector (in headsmp.S) */
-	__raw_writel(__pa(shmobile_secondary_vector), __io(AVECR));
+	__raw_writel(__pa(shmobile_secondary_vector), AVECR);
 
 	/* enable cache coherency on CPU0 */
 	modify_scu_cpu_psr(0, 3 << (cpu * 8));
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 0d159d6..667d53d 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -28,11 +28,11 @@
 #include <asm/smp_twd.h>
 #include <asm/hardware/gic.h>
 
-#define WUPCR		0xe6151010
-#define SRESCR		0xe6151018
-#define PSTR		0xe6151040
-#define SBAR            0xe6180020
-#define APARMBAREA      0xe6f10020
+#define WUPCR		IOMEM(0xe6151010)
+#define SRESCR		IOMEM(0xe6151018)
+#define PSTR		IOMEM(0xe6151040)
+#define SBAR		IOMEM(0xe6180020)
+#define APARMBAREA	IOMEM(0xe6f10020)
 
 static void __iomem *scu_base_addr(void)
 {
@@ -80,10 +80,10 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
 	/* enable cache coherency */
 	modify_scu_cpu_psr(0, 3 << (cpu * 8));
 
-	if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
-		__raw_writel(1 << cpu, __io(WUPCR));	/* wake up */
+	if (((__raw_readw(PSTR) >> (4 * cpu)) & 3) == 3)
+		__raw_writel(1 << cpu, WUPCR);	/* wake up */
 	else
-		__raw_writel(1 << cpu, __io(SRESCR));	/* reset */
+		__raw_writel(1 << cpu, SRESCR);	/* reset */
 
 	return 0;
 }
@@ -95,8 +95,8 @@ void __init sh73a0_smp_prepare_cpus(void)
 	scu_enable(scu_base_addr());
 
 	/* Map the reset vector (in headsmp.S) */
-	__raw_writel(0, __io(APARMBAREA));      /* 4k */
-	__raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
+	__raw_writel(0, APARMBAREA);      /* 4k */
+	__raw_writel(__pa(shmobile_secondary_vector), SBAR);
 
 	/* enable cache coherency on CPU0 */
 	modify_scu_cpu_psr(0, 3 << (cpu * 8));
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index b6ba26a..aac7689 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -23,7 +23,7 @@
 	(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
 
 /* typesafe io address */
-#define __io_address(n)		__io(IO_ADDRESS(n))
+#define __io_address(n)		IOMEM(IO_ADDRESS(n))
 /* Used by some plat-nomadik code */
 #define io_p2v(n)		__io_address(n)
 
-- 
1.7.5.4



From kumarrav at codeaurora.org  Mon Mar 12 06:32:16 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Mon, 12 Mar 2012 16:02:16 +0530
Subject: [PATCH v3 1/2] dmaengine: Add support for per xfer specific
 privatedata
Message-ID: <1331548336-27802-1-git-send-email-kumarrav@codeaurora.org>

Add new argument to DMA SG and Interleave mode for passing
per transfer specific private data, using this it enables the
dma devices which needs to pass the parameters which changes per
each transfer.

Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
---
 include/linux/dmaengine.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 679b349..b8f0495 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -570,7 +570,7 @@ struct dma_device {
 		struct dma_chan *chan,
 		struct scatterlist *dst_sg, unsigned int dst_nents,
 		struct scatterlist *src_sg, unsigned int src_nents,
-		unsigned long flags);
+		unsigned long flags, void *context);
 
 	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
 		struct dma_chan *chan, struct scatterlist *sgl,
@@ -581,7 +581,7 @@ struct dma_device {
 		size_t period_len, enum dma_transfer_direction direction);
 	struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
 		struct dma_chan *chan, struct dma_interleaved_template *xt,
-		unsigned long flags);
+		unsigned long flags, void *context);
 	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		unsigned long arg);
 
-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From rnayak at ti.com  Fri Mar  9 04:11:49 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 9 Mar 2012 14:41:49 +0530
Subject: [PATCH 4/4] ARM: OMAP2430SDP: No support to switch to external clock
 on omap2430
In-Reply-To: <1331284309-22101-1-git-send-email-rnayak@ti.com>
References: <1331284309-22101-1-git-send-email-rnayak@ti.com>
Message-ID: <1331284309-22101-5-git-send-email-rnayak@ti.com>

As stated in the latest 2430 TRM version Z, Table 7-135 and Table 7-154,
omap2430 does not support switching between internal loopback and external
clock for MMC modules. This is supported only on some instances of MMC
modules on omap3430 only.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: Balaji TK <balajitk at ti.com>
Cc: Venkatraman S <svenkatr at ti.com>
---
 arch/arm/mach-omap2/board-2430sdp.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 7370983..eb70b00 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -249,7 +249,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
 		.caps		= MMC_CAP_4_BIT_DATA,
 		.gpio_cd	= -EINVAL,
 		.gpio_wp	= -EINVAL,
-		.ext_clock	= 1,
 	},
 	{}	/* Terminator */
 };
-- 
1.7.1



From b32955 at freescale.com  Sun Mar 11 22:22:18 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 12 Mar 2012 10:22:18 +0800
Subject: [PATCH] mtd/gpmi : fix the wrong DMA command.
Message-ID: <1331518938-24047-1-git-send-email-b32955@freescale.com>

The last DMA command of ECC read page is used to disable the BCH module.
But the original code missed to set the pio[2] which is used to set the
GPMI_HW_GPMI_ECCCTRL register. fix it now.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 5e3c505..c34dab1 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -1061,8 +1061,9 @@ int gpmi_read_page(struct gpmi_nand_data *this,
 		| BF_GPMI_CTRL0_ADDRESS(address)
 		| BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
 	pio[1] = 0;
+	pio[2] = 0; /* clear GPMI_HW_GPMI_ECCCTRL, disable the BCH. */
 	desc = channel->device->device_prep_slave_sg(channel,
-				(struct scatterlist *)pio, 2,
+				(struct scatterlist *)pio, 3,
 				DMA_TRANS_NONE,
 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 	if (!desc) {
-- 
1.7.3.2




From hvaibhav at ti.com  Mon Mar 12 05:48:20 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 12 Mar 2012 09:48:20 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <20120312093921.GA5375@legolas.emea.dhcp.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <20120305225530.GJ12083@atomide.com>
 <79CD15C6BA57404B839C016229A409A83180F73D@DBDE01.ent.ti.com>
 <20120312093921.GA5375@legolas.emea.dhcp.ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831810E32@DBDE01.ent.ti.com>

On Mon, Mar 12, 2012 at 15:09:24, Balbi, Felipe wrote:
> On Fri, Mar 09, 2012 at 05:58:00PM +0000, Hiremath, Vaibhav wrote:
> > On Tue, Mar 06, 2012 at 04:25:30, Tony Lindgren wrote:
> > > Hi,
> > > 
> > > * Vaibhav Hiremath <hvaibhav at ti.com> [120119 06:01]:
> > > > OMAP device has 32k-sync timer which is currently used as a
> > > > clocksource in the kernel (omap2plus_defconfig).
> > > > The current implementation uses compile time selection between
> > > > gp-timer and 32k-sync timer, which breaks multi-omap build for
> > > > the devices like AM33xx, where 32k-sync timer is not available.
> > > > 
> > > > So use hwmod database lookup mechanism, through which at run-time
> > > > we can identify availability of 32k-sync timer on the device,
> > > > else fall back to gp-timer.
> > > ...
> > > 
> > > > --- a/arch/arm/plat-omap/counter_32k.c
> > > > +++ b/arch/arm/plat-omap/counter_32k.c
> > > > @@ -69,52 +69,55 @@ void read_persistent_clock(struct timespec *ts)
> > > >  
> > > >  int __init omap_init_clocksource_32k(void)
> > > >  {
> > > > -	static char err[] __initdata = KERN_ERR
> > > > -			"%s: can't register clocksource!\n";
> > > > -
> > > > -	if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
> > > > -		u32 pbase;
> > > > -		unsigned long size = SZ_4K;
> > > > -		void __iomem *base;
> > > > -		struct clk *sync_32k_ick;
> > > > -
> > > > -		if (cpu_is_omap16xx()) {
> > > > -			pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > > > -			size = SZ_1K;
> > > > -		} else if (cpu_is_omap2420())
> > > > -			pbase = OMAP2420_32KSYNCT_BASE + 0x10;
> > > > -		else if (cpu_is_omap2430())
> > > > -			pbase = OMAP2430_32KSYNCT_BASE + 0x10;
> > > > -		else if (cpu_is_omap34xx())
> > > > -			pbase = OMAP3430_32KSYNCT_BASE + 0x10;
> > > > -		else if (cpu_is_omap44xx())
> > > > -			pbase = OMAP4430_32KSYNCT_BASE + 0x10;
> > > > -		else
> > > > +	u32 pbase;
> > > > +	unsigned long size = SZ_4K;
> > > > +	void __iomem *base;
> > > > +	struct clk *sync_32k_ick;
> > > > +
> > > > +	if (cpu_is_omap16xx()) {
> > > > +		pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > > > +		size = SZ_1K;
> > > > +	} else if (cpu_class_is_omap2()) {
> > > > +		struct omap_hwmod *oh;
> > > > +		const char *oh_name = "counter_32k";
> > > > +
> > > > +		oh = omap_hwmod_lookup(oh_name);
> > > > +		if (!oh || oh->slaves_cnt == 0) {
> > > > +			pr_err("Could not lookup %s hwmod\n", oh_name);
> > > >  			return -ENODEV;
> > > > +		}
> > > > +		pbase = oh->slaves[0]->addr->pa_start + 0x10;
> > > > +	} else {
> > > > +		return -ENODEV;
> > > > +	}
> > > 
> > > How about have separate omap1 and omap2+ init functions that
> > > call a common function and passes the pbase as a parameter?
> > > 
> > > That way we can get rid of the cpu_is_omapxxxx tests here.
> > > 
> > 
> > Tony,
> > 
> > In the morning, I replied very soon, without much thinking...
> > 
> > Just now I started working on the patch, I was just reviewing the code, 
> > and I felt that, it is unnecessary to split the code between omap1 and 
> > omap2+.
> > 
> > The reason is,
> > 
> > Currently Only OMAP16xx base-address is hardcoded with
> > cpu_is_omap16xx() macro, For all other omap family of devices the
> > complete information is fetched from HWDMO api's/data.
> 
> In that case, why don't you create the platform_device by hand on
> arch/arm/mach-omap1/devices.c and move the omap2+ (which is based on
> hwmod) to arch/arm/mach-omap2/devices.c ?
> 

Balbi,

32k_counter code is not a platform_device/driver, we don't build the 
any device here. We only need hwmod data to fetch the basic information like, 
base-address, size, etc...

And I am note sure whether we really intend to make it 
platform_device/driver thing.

Thanks,
Vaibhav

> -- 
> balbi
> 



From robherring2 at gmail.com  Sun Mar 11 17:08:19 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sun, 11 Mar 2012 16:08:19 -0500
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331500100-31351-4-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Several platforms create IOMEM defines for casting to 'void __iomem *',
and other platforms are incorrectly using __io() macro for the same
purpose. This creates a common definition and removes all the platform
specific versions. Rather than try to make linux/io.h and asm/io.h
assembly safe, the assembly version of IOMEM is moved into
asm/assembler.h.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Hartley Sweeten <hsweeten at visionengravers.com>
Cc: Ryan Mallon <rmallon at gmail.com>
Cc: Eric Miao <eric.y.miao at gmail.com>
Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
Cc: David Brown <davidb at codeaurora.org>
Cc: Daniel Walker <dwalker at fifo99.com>
Cc: Bryan Huntsman <bryanh at codeaurora.org>
Cc: Sascha Hauer <kernel at pengutronix.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Viresh Kumar <viresh.kumar at st.com>
Cc: Rajeev Kumar <rajeev-dlh.kumar at st.com>
Cc: Colin Cross <ccross at android.com>
Cc: Olof Johansson <olof at lixom.net>
Cc: Stephen Warren <swarren at nvidia.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/include/asm/assembler.h                |    2 ++
 arch/arm/include/asm/io.h                       |    2 ++
 arch/arm/kernel/debug.S                         |    1 +
 arch/arm/kernel/entry-armv.S                    |    1 +
 arch/arm/mach-davinci/include/mach/hardware.h   |    6 ------
 arch/arm/mach-davinci/include/mach/uncompress.h |    2 ++
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |    9 ---------
 arch/arm/mach-mmp/include/mach/addr-map.h       |    6 ------
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |    6 ------
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    6 ------
 arch/arm/mach-mxs/include/mach/hardware.h       |    6 ------
 arch/arm/mach-omap1/ams-delta-fiq-handler.S     |    1 +
 arch/arm/mach-omap1/iomap.h                     |    6 ------
 arch/arm/mach-omap2/clock3xxx_data.c            |    1 +
 arch/arm/mach-omap2/clock44xx_data.c            |    1 +
 arch/arm/mach-omap2/iomap.h                     |    6 ------
 arch/arm/mach-rpc/include/mach/hardware.h       |    6 ------
 arch/arm/mach-spear3xx/clock.c                  |    1 +
 arch/arm/mach-spear6xx/clock.c                  |    1 +
 arch/arm/mach-tegra/include/mach/iomap.h        |    6 ------
 arch/arm/mach-u300/include/mach/u300-regs.h     |    6 ------
 arch/arm/plat-mxc/include/mach/hardware.h       |    6 ------
 arch/arm/plat-omap/include/plat/hardware.h      |    6 ------
 arch/arm/plat-omap/include/plat/usb.h           |    1 -
 arch/arm/plat-spear/include/plat/hardware.h     |    6 ------
 25 files changed, 13 insertions(+), 88 deletions(-)

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 62f8095..88374dd 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -23,6 +23,8 @@
 #include <asm/ptrace.h>
 #include <asm/domain.h>
 
+#define IOMEM(x)	(x)
+
 /*
  * Endian independent macros for shifting bytes within registers.
  */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 11d2072..35d9140 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -102,6 +102,8 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 	return (void __iomem *)addr;
 }
 
+#define IOMEM(x)	((void __force __iomem *)(x))
+
 /* IO barriers */
 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 #define __iormb()		rmb()
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index 204e216..501cdbf 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -10,6 +10,7 @@
  *  32-bit debugging code
  */
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 
 		.text
 
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 22f0ed3..395f627 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -15,6 +15,7 @@
  *  that causes it to save wrong values...  Be aware!
  */
 
+#include <asm/assembler.h>
 #include <asm/memory.h>
 #include <asm/glue-df.h>
 #include <asm/glue-pf.h>
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 414e0b9..0be260b 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -32,10 +32,4 @@
 #define __IO_ADDRESS(x)			((x) + IO_OFFSET)
 #define IO_ADDRESS(pa)			IOMEM(__IO_ADDRESS(pa))
 
-#ifdef __ASSEMBLER__
-#define IOMEM(x)                	x
-#else
-#define IOMEM(x)                	((void __force __iomem *)(x))
-#endif
-
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 9dc7cf9..da2fb2c 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -25,6 +25,8 @@
 
 #include <mach/serial.h>
 
+#define IOMEM(x)	((void __force __iomem *)(x))
+
 u32 *uart;
 
 /* PORT_16C550A, in polled non-fifo mode */
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index e711d0e..c4a7b84 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -6,15 +6,6 @@
 #define __ASM_ARCH_EP93XX_REGS_H
 
 /*
- * A typesafe __io() variation for variable initialisers
- */
-#ifdef __ASSEMBLER__
-#define IOMEM(p)                p
-#else
-#define IOMEM(p)                ((void __iomem __force *)(p))
-#endif
-
-/*
  * EP93xx Physical Memory Map:
  *
  * The ASDO pin is sampled at system reset to select a synchronous or
diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h
index 3e404ac..b1ece08 100644
--- a/arch/arm/mach-mmp/include/mach/addr-map.h
+++ b/arch/arm/mach-mmp/include/mach/addr-map.h
@@ -11,12 +11,6 @@
 #ifndef __ASM_MACH_ADDR_MAP_H
 #define __ASM_MACH_ADDR_MAP_H
 
-#ifndef __ASSEMBLER__
-#define IOMEM(x)	((void __iomem *)(x))
-#else
-#define IOMEM(x)	(x)
-#endif
-
 /* APB - Application Subsystem Peripheral Bus
  *
  * NOTE: the DMA controller registers are actually on the AXI fabric #1
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 152b3b7..6c4046c 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -38,12 +38,6 @@
  *
  */
 
-#ifdef __ASSEMBLY__
-#define IOMEM(x)	x
-#else
-#define IOMEM(x)	((void __force __iomem *)(x))
-#endif
-
 #define MSM_VIC_BASE          IOMEM(0xE0000000)
 #define MSM_VIC_PHYS          0xC0000000
 #define MSM_VIC_SIZE          SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 90682f4..00afdfb 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -37,12 +37,6 @@
  *
  */
 
-#ifdef __ASSEMBLY__
-#define IOMEM(x)	x
-#else
-#define IOMEM(x)	((void __force __iomem *)(x))
-#endif
-
 #if defined(CONFIG_ARCH_MSM7X30)
 #include "msm_iomap-7x30.h"
 #elif defined(CONFIG_ARCH_QSD8X50)
diff --git a/arch/arm/mach-mxs/include/mach/hardware.h b/arch/arm/mach-mxs/include/mach/hardware.h
index 53e89a0..4c0e8a6 100644
--- a/arch/arm/mach-mxs/include/mach/hardware.h
+++ b/arch/arm/mach-mxs/include/mach/hardware.h
@@ -20,10 +20,4 @@
 #ifndef __MACH_MXS_HARDWARE_H__
 #define __MACH_MXS_HARDWARE_H__
 
-#ifdef __ASSEMBLER__
-#define IOMEM(addr)	(addr)
-#else
-#define IOMEM(addr)	((void __force __iomem *)(addr))
-#endif
-
 #endif /* __MACH_MXS_HARDWARE_H__ */
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
index 399c4c4..a051cb8 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -14,6 +14,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 
 #include <plat/board-ams-delta.h>
 
diff --git a/arch/arm/mach-omap1/iomap.h b/arch/arm/mach-omap1/iomap.h
index d681757..330c471 100644
--- a/arch/arm/mach-omap1/iomap.h
+++ b/arch/arm/mach-omap1/iomap.h
@@ -22,12 +22,6 @@
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#ifdef __ASSEMBLER__
-#define IOMEM(x)		(x)
-#else
-#define IOMEM(x)		((void __force __iomem *)(x))
-#endif
-
 #define OMAP1_IO_OFFSET		0x01000000	/* Virtual IO = 0xfefb0000 */
 #define OMAP1_IO_ADDRESS(pa)	IOMEM((pa) - OMAP1_IO_OFFSET)
 
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 981b9f9..480fb8f 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -19,6 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/list.h>
+#include <linux/io.h>
 
 #include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 79b98f2..c03c110 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -26,6 +26,7 @@
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h
index e6f9581..0812b15 100644
--- a/arch/arm/mach-omap2/iomap.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -22,12 +22,6 @@
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#ifdef __ASSEMBLER__
-#define IOMEM(x)		(x)
-#else
-#define IOMEM(x)		((void __force __iomem *)(x))
-#endif
-
 #define OMAP2_L3_IO_OFFSET	0x90000000
 #define OMAP2_L3_IO_ADDRESS(pa)	IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
 
diff --git a/arch/arm/mach-rpc/include/mach/hardware.h b/arch/arm/mach-rpc/include/mach/hardware.h
index 050d63c..257166b 100644
--- a/arch/arm/mach-rpc/include/mach/hardware.h
+++ b/arch/arm/mach-rpc/include/mach/hardware.h
@@ -14,12 +14,6 @@
 
 #include <mach/memory.h>
 
-#ifndef __ASSEMBLY__
-#define IOMEM(x) ((void __iomem *)(unsigned long)(x))
-#else
-#define IOMEM(x) x
-#endif /* __ASSEMBLY__ */
-
 /*
  * What hardware must be present
  */
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index f67860c..6c4841f 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -12,6 +12,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/kernel.h>
 #include <asm/mach-types.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index ac70e0d..9281cf8 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -12,6 +12,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/kernel.h>
 #include <plat/clock.h>
 #include <mach/misc_regs.h>
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 082b4d1..c05b311 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -281,12 +281,6 @@
  *
  */
 
-#ifdef __ASSEMBLY__
-#define IOMEM(x)	(x)
-#else
-#define IOMEM(x)	((void __force __iomem *)(x))
-#endif
-
 #define IO_IRAM_PHYS	0x40000000
 #define IO_IRAM_VIRT	IOMEM(0xFE400000)
 #define IO_IRAM_SIZE	SZ_256K
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 035fdc9..7b7cba9 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -18,12 +18,6 @@
  * the defines are used for setting up the I/O memory mapping.
  */
 
-#ifdef __ASSEMBLER__
-#define IOMEM(a) (a)
-#else
-#define IOMEM(a) (void __iomem *) a
-#endif
-
 /* NAND Flash CS0 */
 #define U300_NAND_CS0_PHYS_BASE		0x80000000
 
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index ca06a68..0630513 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -22,12 +22,6 @@
 
 #include <asm/sizes.h>
 
-#ifdef __ASSEMBLER__
-#define IOMEM(addr)	(addr)
-#else
-#define IOMEM(addr)	((void __force __iomem *)(addr))
-#endif
-
 #define addr_in_module(addr, mod) \
 	((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
 
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index 537b05a..e897978 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -43,12 +43,6 @@
 #endif
 #include <plat/serial.h>
 
-#ifdef __ASSEMBLER__
-#define IOMEM(x)		(x)
-#else
-#define IOMEM(x)		((void __force __iomem *)(x))
-#endif
-
 /*
  * ---------------------------------------------------------------------------
  * Common definitions for all OMAP processors
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index d0fc9f4..762eeb0 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -112,7 +112,6 @@ extern int omap4430_phy_suspend(struct device *dev, int suspend);
  */
 
 #define OMAP2_L4_IO_OFFSET	0xb2000000
-#define IOMEM(x)		((void __force __iomem *)(x))
 #define OMAP2_L4_IO_ADDRESS(pa)	IOMEM((pa) + OMAP2_L4_IO_OFFSET)
 
 static inline u8 omap_readb(u32 pa)
diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h
index 66d6772..70187d7 100644
--- a/arch/arm/plat-spear/include/plat/hardware.h
+++ b/arch/arm/plat-spear/include/plat/hardware.h
@@ -14,10 +14,4 @@
 #ifndef __PLAT_HARDWARE_H
 #define __PLAT_HARDWARE_H
 
-#ifndef __ASSEMBLY__
-#define IOMEM(x)	((void __iomem __force *)(x))
-#else
-#define IOMEM(x)	(x)
-#endif
-
 #endif /* __PLAT_HARDWARE_H */
-- 
1.7.5.4



From b32955 at freescale.com  Mon Mar 12 04:35:13 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 12 Mar 2012 16:35:13 +0800
Subject: [PATCH] mtd/gpmi : fix the wrong DMA command.
In-Reply-To: <20120312075107.GB3928@pengutronix.de>
References: <1331518938-24047-1-git-send-email-b32955@freescale.com>
 <20120312075107.GB3928@pengutronix.de>
Message-ID: <4F5DB541.3000107@freescale.com>

? 2012?03?12? 15:51, Wolfram Sang ??:
> On Mon, Mar 12, 2012 at 10:22:18AM +0800, Huang Shijie wrote:
>> The last DMA command of ECC read page is used to disable the BCH module.
>> But the original code missed to set the pio[2] which is used to set the
>> GPMI_HW_GPMI_ECCCTRL register. fix it now.
>>
>> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> Thanks! What does happen because of this bug? Additional checksum errors? I
> haven't seen many on MX28 IIRC, so I wonder.
>
The MX28 runs well without this patch. I guess the speed of mx28 is too
slow.

The bug only observed in mx6q. A DMA timeout occurs.

But if you apply this patch to mx28's code. A dma timeout occurs too.
This is why i sent the patch
"mxs-dma : rewrite the last parameter of mxs_dma_prep_slave_sg()"

IC guy told me to add a WAIT4END in the middle one of the ECC read page
chain, and disable the BCH in the last
DMA command of the chain. After this patch, the code follows this rule.


BR
Huang Shijie







From linus.walleij at linaro.org  Mon Mar 12 08:51:35 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 12 Mar 2012 13:51:35 +0100
Subject: [PATCH 3/4] pinctrl: support pinconfig on the U300
In-Reply-To: <4F57E3D2.40405@wwwdotorg.org>
References: <1331071533-24789-1-git-send-email-linus.walleij@stericsson.com>
 <4F57E3D2.40405@wwwdotorg.org>
Message-ID: <CACRpkdbSzU-eXCfzFVmynO_D44PYA4g7dRSvRj+0s6uZxYD+tw@mail.gmail.com>

On Wed, Mar 7, 2012 at 11:40 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 03/06/2012 03:05 PM, Linus Walleij wrote:
>> From: Linus Walleij <linus.walleij at linaro.org>
>>
>> This adds pin configuration support for the U300 driver pair,
>> we can now read out the biasing and drive mode in debugfs and
>> configure it using the new configuration API.
>
>> +int u300_pin_config_set(struct pinctrl_dev *pctldev,
>> + ? ? ? ? ? ? ? ? ? ? unsigned pin,
>> + ? ? ? ? ? ? ? ? ? ? unsigned long config)
>> +{
>> + ? ? struct pinctrl_gpio_range *range = u300_match_gpio_range(pin);
>> + ? ? int ret;
>> +
>> + ? ? if (!range)
>> + ? ? ? ? ? ? return -EINVAL;
>> +
>> + ? ? /* Note: none of these configurations take any argument */
>> + ? ? ret = u300_gpio_config_set(range->gc,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(pin - range->pin_base + range->base),
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?to_config_param(config));
>
> I'm a little confused here; the documentation for most of the
> PIN_CONFIG_* parameters that this function is passed does explicitly
> document that there is an associated argument value. For example,
> IN_CONFIG_BIAS_PULL_UP is coupled with the pull up resistance in Ohms.
> Shouldn't this code extract the argument and validate that it's a
> supported value for the HW?

It says:

 * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
 *      impedance to VDD), if the controller supports specifying a certain
 *      pull-up resistance, this is given as an argument (in Ohms) when
 *      setting this parameter.

Notice "if controller supports specifying ..." clause.

The reverse holds: if the pin controller doesn't support specifying that,
the pull-up will just be enabled, no matter what the argument was.

But maybe I should try to dig out which exact value it is, since it's
anyway a 1-1 copuling between board data and this one driver it
could be clearer (though the argument will just be checked to be
the one value the chip supports, and then discarded).

Yours,
Linus Walleij


From rnayak at ti.com  Mon Mar 12 01:52:42 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 12 Mar 2012 11:22:42 +0530
Subject: [PATCHv5 3/6] ARM: OMAP4 PM: Add IO Daisychain support
In-Reply-To: <alpine.DEB.2.00.1203092051140.30879@utopia.booyaka.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-4-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203092051140.30879@utopia.booyaka.com>
Message-ID: <4F5D8F2A.1070602@ti.com>

On Saturday 10 March 2012 09:29 AM, Paul Walmsley wrote:
> Hi
>
> On Tue, 6 Mar 2012, Tero Kristo wrote:
>
>> From: Rajendra Nayak<rnayak at ti.com>
>>
>> IO daisychain is a mechanism that allows individual IO pads to generate
>> wakeup events on their own based on a switch of an input signal level.
>> This allows the hardware module behind the pad to be powered down, but
>> still have device level capability to detect IO events, and once this
>> happens the module can be powered back up to resume IO. See section
>> 3.9.4 in OMAP4430 Public TRM for details.
>>
>> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
>> Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com>
>> Signed-off-by: Tero Kristo<t-kristo at ti.com>
>
> Here's an updated version of this patch.  Please let me know if you think
> we should remove the poll on the WUCLKOUT line to conform with the change
> that Tero made to the OMAP3 version.

Thanks Paul, for the updates patch. Just one comment below..

>
>
> - Paul
>
> From: Rajendra Nayak<rnayak at ti.com>
> Date: Fri, 2 Mar 2012 17:17:52 +0200
> Subject: [PATCH 3/6] ARM: OMAP4: PRM: Add IO Daisychain support
>
> IO daisychain is a mechanism that allows individual IO pads to generate
> wakeup events on their own based on a switch of an input signal level.
> This allows the hardware module behind the pad to be powered down, but
> still have device level capability to detect IO events, and once this
> happens the module can be powered back up to resume IO. See section
> 3.9.4 in OMAP4430 Public TRM for details.
>
> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
> Signed-off-by: Vishwanath BS<vishwanath.bs at ti.com> is just bad
documentation.

> Signed-off-by: Tero Kristo<t-kristo at ti.com>
> [paul at pwsan.com: removed MAX_IOPAD_LATCH_TIME declaration; renamed

But the code below still seems to use it. Is it now defined in some
common header so the same value is used in omap3 and omap4?

regards,
Rajendra

>   omap4_trigger_io_chain() to conform to other PRM function names;
>   added kerneldoc]
> Signed-off-by: Paul Walmsley<paul at pwsan.com>
> ---
>   arch/arm/mach-omap2/prm44xx.c |   48 +++++++++++++++++++++++++++++++++++++++++
>   arch/arm/mach-omap2/prm44xx.h |    2 +
>   2 files changed, 50 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
> index a1d6154..5868a12 100644
> --- a/arch/arm/mach-omap2/prm44xx.c
> +++ b/arch/arm/mach-omap2/prm44xx.c
> @@ -231,6 +231,54 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
>   				 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
>   }
>
> +/**
> + * omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
> + *
> + * Clear any previously-latched I/O wakeup events and ensure that the
> + * I/O wakeup gates are aligned with the current mux settings.  Works
> + * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
> + * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
> + * No return value. XXX Are the final two steps necessary?
> + */
> +void omap44xx_prm_reconfigure_io_chain(void)
> +{
> +	int i = 0;
> +
> +	/* Enable GLOBAL_WUEN */
> +	if (!(omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
> +		OMAP4_PRM_IO_PMCTRL_OFFSET)&  OMAP4430_GLOBAL_WUEN_MASK))
> +		omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
> +			OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_PRM_DEVICE_INST,
> +			OMAP4_PRM_IO_PMCTRL_OFFSET);
> +
> +	/* Trigger WUCLKIN enable */
> +	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
> +			OMAP4430_WUCLK_CTRL_MASK, OMAP4430_PRM_DEVICE_INST,
> +			OMAP4_PRM_IO_PMCTRL_OFFSET);
> +	omap_test_timeout(
> +		(((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
> +			OMAP4_PRM_IO_PMCTRL_OFFSET)&
> +			OMAP4430_WUCLK_STATUS_MASK)>>
> +			OMAP4430_WUCLK_STATUS_SHIFT) == 1),
> +		MAX_IOPAD_LATCH_TIME, i);
> +	if (i == MAX_IOPAD_LATCH_TIME)
> +		pr_warn("PRM: I/O chain clock line assertion timed out\n");
> +
> +	/* Trigger WUCLKIN disable */
> +	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
> +			OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_IO_PMCTRL_OFFSET);
> +	omap_test_timeout(
> +		(((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
> +			OMAP4_PRM_IO_PMCTRL_OFFSET)&
> +			OMAP4430_WUCLK_STATUS_MASK)>>
> +			OMAP4430_WUCLK_STATUS_SHIFT) == 0),
> +		MAX_IOPAD_LATCH_TIME, i);
> +	if (i == MAX_IOPAD_LATCH_TIME)
> +		pr_warn("PRM: I/O chain clock line deassertion timed out\n");
> +
> +	return;
> +}
> +
>   static int __init omap4xxx_prcm_init(void)
>   {
>   	if (cpu_is_omap44xx())
> diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
> index 7978092..ee72ae6 100644
> --- a/arch/arm/mach-omap2/prm44xx.h
> +++ b/arch/arm/mach-omap2/prm44xx.h
> @@ -763,6 +763,8 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
>   extern void omap4_prm_vcvp_write(u32 val, u8 offset);
>   extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
>
> +extern void omap44xx_prm_reconfigure_io_chain(void);
> +
>   /* PRM interrupt-related functions */
>   extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
>   extern void omap44xx_prm_ocp_barrier(void);



From thomas.abraham at linaro.org  Mon Mar 12 17:07:59 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 02:37:59 +0530
Subject: [PATCH v4 0/2] ARM: Exynos: Add irq_domain and device tree
 support for combiner
In-Reply-To: <1329798806-32482-1-git-send-email-thomas.abraham@linaro.org>
References: <1329798806-32482-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CAJuYYwQ3d1+UODEBOJYnQ=_+zNCc8dwZJycs_kLsEWDcteBa-A@mail.gmail.com>

Hi Rob/Grant,

On 21 February 2012 10:03, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> Changes since v3:
> - In dt case, the use of fixed gic linux irq number to map the combiner
> ?interrupt output is removed. This is replaced with the interrupt number
> ?obtained from the gic irq domain. (Thanks to Rob Herring and Grant
> ?Likely for this suggestion).
> - Split the patch into two parts - irq_domain and device tree support
> ?addition.
>
> Changes since v2:
> - Rebased to Grant's irqdomain/next branch.
>
> Changes since v1:
> - Includes all changes suggested by Rob Herring.
> - Tested with SPARSE_IRQ enabled.
>
> This patchset adds irq_domain and device tree support for the Exynos Interrupt
> Combiner controller.
>
> The first patch adds a common irq domain for the interrupts managed by the
> interrupt combiners. All the instances of irq combiner reference the common irq
> domain for translating hardware interrupts to linux irq number.
>
> The second patch adds a interrupt specifier translator to support device tree
> based instantiation. It can translate interrupt specifiers for device nodes
> which use combiner as their interrupt parent.
>
> This patchset is based on
> http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]
>
> with all irq_domain (v5) patches merged from
> http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]
>
> Thomas Abraham (2):
> ?ARM: Exynos: Add irq_domain support for interrupt combiner
> ?ARM: Exynos: Add device tree support for interrupt combiner

Any comments on this patch series? If it helps, I can repost this
patch series. This patch series is a pre-requsite for the irq-domain
and dt support for wakeup interrupts, which Rob has acked.

Thanks,
Thomas.

>
> ?.../bindings/arm/samsung/interrupt-combiner.txt ? ?| ? 48 +++++++++
> ?arch/arm/mach-exynos/common.c ? ? ? ? ? ? ? ? ? ? ?| ?112 ++++++++++++++++----
> ?2 files changed, 140 insertions(+), 20 deletions(-)
> ?create mode 100644 Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html


From tomi.valkeinen at ti.com  Mon Mar 12 09:45:30 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Mon, 12 Mar 2012 15:45:30 +0200
Subject: OMAP DSS device tree design problems
Message-ID: <1331559930.2097.100.camel@deskari>

Hi,

I'm struggling with the design of the DT data for OMAP display subsystem
driver, and any thoughts and ideas are welcome. This mail is a rather
long one, where I'm trying to show the different approaches I've
thought.

So the .dts format would be something like this, taking 4430SDP as an
example. It's just an outline, missing dispc, hwmods,
compatible-properties etc, which are not so relevant here.

ocp {
	dss {
		dsi1 {
			taal {

			};
		};
	};
};

So there we have a Taal panel, connected to DSI1 output interface, which
is part of the OMAP display subsystem.

One thing to note here is that although there's only one panel under
dsi1 in this case, the current SW supports having multiple panels under
one output interface. And while the output can support only one active
panel at a time, we do have boards where two panels are connected to one
output, and there's some kind of HW switch used to select which panel is
enabled.

The first problem here is that I don't know how to manage the switch
part. With current SW we have had the switch handling in the board
files, in functions called when a display is enabled/disabled. I guess
one option is to have the switch related code in their own drivers,
totally apart from the dss code, perhaps offering a sysfs interface or
such. And then, if the switch happens to be in the wrong position, the
panel will fail in some way.

The second problem is about the DT properties. With multiple panels it's
not possible to do this:

dsi1 {
	dsi-ddr-clk = <250000000>;

	taal {
	};

	some-other-panel {
	};
};

because the panels could require different dsi clock rates. So we need
something like this:

dsi1 {
	taal {
		dsi-ddr-clk = <250000000>;
	};

	some-other-panel {
		dsi-ddr-clk = <350000000>;
	};
};

However, here the problem is that while ultimately we're interested in
the ddr-clk rate, calculation of the rate is non-trivial and may need
customizations at times. So instead of the clock rate we actually need
to define a bunch of dividers/multipliers.

But these dividers are OMAP specific things, and do not belong to Taal
driver. So this bring the question: is the general rule about DT node
properties such that only the driver handling the particular node should
read the properties in that node? So, in the example above, should the
dsi driver only read props in the dsi1 and dsi2 nodes, and never look at
props in the taal nodes?

So basically, can we do this:

dsi1 {
	taal {
		omap-specific-clk-divs = <1 2 3 4 5 6 7>;
	};

	some-other-panel {
		omap-specific-clk-divs = <7 6 5 4 3 2 1>;
	};
};

and the Taal driver would ignore those, but dsi driver would use them?
This looks like quite easy solution to this, but also doesn't feel
right. So my current idea is to have clk-div tables in the dsi node,
something like this:

dsi1 {
	omap-specific-clk-divs = <
		250 1 2 3 4 5 6 7 /* divs that produce 250MHz clk */
		350 7 6 5 4 3 2 1 /* divs that produce 350MHz clk */
	>;

	taal {
		dsi-ddr-clk = <250000000>;
	};

	some-other-panel {
		dsi-ddr-clk = <350000000>;
	};
};

Here the panel drivers would ask the DSI driver to configure DSI DDR clk
of 250/350MHz, and the DSI driver would then use the lookup table to
find the dividers. If the lookup fails, the DSI driver could fail or try
to calculate the dividers itself. Other platforms could handle the DDR
clk configuration however they see best.

---

Another thing related to DSI command mode panels is the DSI lane
configuration, and I can't make my mind if they belong to the panel
driver in some way or not.

So, again taking SDP board and Taal as an example, we have 6 pads on
OMAP which are used for communicating with Taal. The pads need to be
muxed to DSI mode like any other OMAP pads. Currently the pad muxing is
not touched by the driver, but I think it's doable in the DSI driver (as
long as the DSI driver knows the required pad config).

However, that's not enough.

DSI uses differential pairs for communication (a "lane" consists of two
wires), and we have always one clock lane, and a number of data lanes.
In Taal's case we have a clock lane and two data lanes, which means 6
pads/wires.

We need to configure which of the OMAPs pads is used for which function,
so, for example, pad x and x+1 are used for clock lane, and x is the
negative pair and x+1 is the positive pair. And this configuration has
to match the wiring going to the panel, so that clk+ from OMAP goes to
clk+ in the panel.

So it dts data we need something, perhaps, like below. Here we define
the pad numbers and polarities in an array, where the first cell-pair is
for clk, then data1, then data2 and so on (if there are more than two
data lanes).

lanes = <
	/* pad-pair number, polarity */
	1 0	/* DSI pad pair 1 is used for clk, pol +/-  */
	2 1	/* DSI pad pair 2 is used for data1, pol -/+ */
	0 0	/* DSI pad pair 0 is used for data2, pol +/- */
>;

Now, I don't quite know where this data should be. If it's in the
dsi-node, it doesn't work with multiple panels. But then, it's quite
OMAP specific thing. While other platforms probably need some kind of
pad configuration also, it may be something totally different. And so it
doesn't feel right in the taal-node either.

And a look-up table like in the clock case doesn't make much sense
either, as we don't have a key here, as we had in the clock case (the
dsi-ddr-clk).

So basically the only option I've come up with is to define the lane
configuration in the panel's data, and let the dsi driver peek there and
configure the HW. And this doesn't feel right.

 Tomi

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From linus.walleij at stericsson.com  Mon Mar 12 17:14:40 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 12 Mar 2012 22:14:40 +0100
Subject: [PATCH 4/4 v2] ARM: u300: configure some pins as an example
Message-ID: <1331586880-15690-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

To show how the pin configuration is used on the U300, let's
include some configs for two GPIO pins.

ChangeLog v1->v2:
- Provide a better example, set the clock return pin to pull-up
  and set the card detect pin to high impedance.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 arch/arm/mach-u300/core.c |   18 ++++++++++++++++--
 1 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index f326d31..a7b3f36 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -27,6 +27,7 @@
 #include <linux/mtd/fsmc.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/dma-mapping.h>
 
 #include <asm/types.h>
@@ -1605,7 +1606,15 @@ static struct platform_device dma_device = {
 	},
 };
 
-/* Pinmux settings */
+static unsigned long pin_pullup_conf[] = {
+	PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
+};
+
+static unsigned long pin_highz_conf[] = {
+	PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
+};
+
+/* Pin control settings */
 static struct pinctrl_map __initdata u300_pinmux_map[] = {
 	/* anonymous maps for chip power and EMIFs */
 	PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
@@ -1615,6 +1624,12 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
 	PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
+	/* This pin is used for clock return rather than GPIO */
+	PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
+				    pin_pullup_conf),
+	/* This pin is used for card detect */
+	PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
+				    pin_highz_conf),
 };
 
 struct u300_mux_hog {
@@ -1640,7 +1655,6 @@ static int __init u300_pinctrl_fetch(void)
 
 	for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
 		struct pinctrl *p;
-		int ret;
 
 		p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
 		if (IS_ERR(p)) {
-- 
1.7.8



From arnd at arndb.de  Mon Mar 12 17:15:54 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 12 Mar 2012 21:15:54 +0000
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <4F5E4178.50801@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <201203112134.45302.arnd@arndb.de> <4F5E4178.50801@gmail.com>
Message-ID: <201203122115.54422.arnd@arndb.de>

On Monday 12 March 2012, Rob Herring wrote:
> On 03/11/2012 04:34 PM, Arnd Bergmann wrote:
> > On Sunday 11 March 2012, Rob Herring wrote:
> >> From: Rob Herring <rob.herring at calxeda.com>
> >>
> >> Several platforms create IOMEM defines for casting to 'void __iomem *',
> >> and other platforms are incorrectly using __io() macro for the same
> >> purpose. This creates a common definition and removes all the platform
> >> specific versions. Rather than try to make linux/io.h and asm/io.h
> >> assembly safe, the assembly version of IOMEM is moved into
> >> asm/assembler.h.
> > 
> > Looks good to me, in order to fix the problem at hand. I'm not sure
> > about spreading the IOMEM() macro further, that is largely a separate
> > problem and only a question of style, not of correctness as with __io().
> 
> Got a better suggestion? I didn't think adding IOMEM to 5 more platforms
> or inventing something different was the right path. Hopefully this is a
> shrinking problem as things move to DT.

In a cleanup series I started earlier, I used ${PLATFORM}_IO_P2V, which
is now used on at91 and imx. I'm not particularly attached to that
one either, the basic idea was that we could define them all concurrently,
but in hindsight that looks flawed now. Let's just use the patch you came
up with.

	Arnd


From mturquette at linaro.org  Sat Mar 10 02:54:24 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Fri,  9 Mar 2012 23:54:24 -0800
Subject: [PATCH v6 3/3] clk: basic clock hardware types
In-Reply-To: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
Message-ID: <1331366064-1273-4-git-send-email-mturquette@linaro.org>

Many platforms support simple gateable clocks, fixed-rate clocks,
adjustable divider clocks and multi-parent multiplexer clocks.

This patch introduces basic clock types for the above-mentioned hardware
which share some common characteristics.

Based on original work by Jeremy Kerr and contribution by Jamie Iles.
Dividers and multiplexor clocks originally contributed by Richard Zhao &
Sascha Hauer.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Mike Turquette <mturquette at ti.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Jamie Iles <jamie at jamieiles.com>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Andrew Lunn <andrew at lunn.ch>
---
Changes since v5:
 * standardized the hw-specific locking in the basic clock types
 * export the individual ops for each basic clock type
 * improve registration for single-parent basic clocks (thanks Sascha)
 * fixed bugs in gate clock's static initializers (thanks Andrew)

 drivers/clk/Makefile         |    3 +-
 drivers/clk/clk-divider.c    |  204 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/clk-fixed-rate.c |   82 +++++++++++++++++
 drivers/clk/clk-gate.c       |  157 ++++++++++++++++++++++++++++++++
 drivers/clk/clk-mux.c        |  123 +++++++++++++++++++++++++
 include/linux/clk-private.h  |  124 +++++++++++++++++++++++++
 include/linux/clk-provider.h |  127 ++++++++++++++++++++++++++
 7 files changed, 819 insertions(+), 1 deletions(-)
 create mode 100644 drivers/clk/clk-divider.c
 create mode 100644 drivers/clk/clk-fixed-rate.c
 create mode 100644 drivers/clk/clk-gate.c
 create mode 100644 drivers/clk/clk-mux.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ff362c4..1f736bc 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,3 +1,4 @@
 
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
-obj-$(CONFIG_COMMON_CLK)	+= clk.o
+obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
+				   clk-mux.o clk-divider.o
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
new file mode 100644
index 0000000..c0c4e0b
--- /dev/null
+++ b/drivers/clk/clk-divider.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Adjustable divider clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+/*
+ * DOC: basic adjustable divider clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is adjustable.  clk->rate = parent->rate / divisor
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	unsigned int div;
+	unsigned long flags = 0;
+
+	if (divider->lock)
+		spin_lock_irqsave(divider->lock, flags);
+
+	div = readl(divider->reg) >> divider->shift;
+	div &= (1 << divider->width) - 1;
+
+	if (divider->lock)
+		spin_unlock_irqrestore(divider->lock, flags);
+
+	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
+		div++;
+
+	return parent_rate / div;
+}
+EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
+
+static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+		unsigned long *best_parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	int i, bestdiv = 0;
+	unsigned long parent_rate, best = 0, now, maxdiv;
+
+	maxdiv = (1 << divider->width);
+
+	if (divider->flags & CLK_DIVIDER_ONE_BASED)
+		maxdiv--;
+
+	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
+		parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
+		bestdiv = parent_rate / rate;
+		bestdiv = bestdiv == 0 ? 1 : bestdiv;
+		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+		goto out;
+	}
+
+	/*
+	 * The maximum divider we can use without overflowing
+	 * unsigned long in rate * i below
+	 */
+	maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+	for (i = 1; i <= maxdiv; i++) {
+		int div;
+		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
+				rate * i);
+		div = parent_rate / rate;
+		div = div > maxdiv ? maxdiv : div;
+		div = div < 1 ? 1 : div;
+		now = parent_rate / div;
+
+		if (now <= rate && now >= best) {
+			bestdiv = div;
+			best = now;
+			*best_parent_rate = parent_rate;
+		}
+	}
+
+	if (!bestdiv) {
+		bestdiv = (1 << divider->width);
+		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
+	} else {
+		parent_rate = best * bestdiv;
+	}
+
+out:
+	if (best_parent_rate)
+		*best_parent_rate = parent_rate;
+
+	return bestdiv;
+}
+
+static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	unsigned long best_parent_rate;
+	int div = clk_divider_bestdiv(hw, rate, &best_parent_rate);
+	if (prate) {
+		if (best_parent_rate == __clk_get_rate(
+					__clk_get_parent(hw->clk)))
+			*prate = 0;
+		else
+			*prate = best_parent_rate;
+	}
+
+	return best_parent_rate / div;
+}
+EXPORT_SYMBOL_GPL(clk_divider_round_rate);
+
+static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
+{
+	unsigned long best_parent_rate;
+	struct clk_divider *divider = to_clk_divider(hw);
+	unsigned int div;
+	unsigned long flags = 0;
+	u32 val;
+
+	div = clk_divider_bestdiv(hw, rate, &best_parent_rate);
+
+	if (divider->lock)
+		spin_lock_irqsave(divider->lock, flags);
+
+	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
+		div--;
+
+	val = readl(divider->reg);
+	val &= ~(((1 << divider->width) - 1) << divider->shift);
+	val |= div << divider->shift;
+	writel(val, divider->reg);
+
+	if (divider->lock)
+		spin_unlock_irqrestore(divider->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(clk_divider_set_rate);
+
+struct clk_ops clk_divider_ops = {
+	.recalc_rate = clk_divider_recalc_rate,
+	.round_rate = clk_divider_round_rate,
+	.set_rate = clk_divider_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_divider_ops);
+
+struct clk *clk_register_divider(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_divider_flags, spinlock_t *lock)
+{
+	struct clk_divider *div;
+	struct clk *clk;
+
+	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
+
+	if (!div) {
+		pr_err("%s: could not allocate divider clk\n", __func__);
+		return NULL;
+	}
+
+	/* struct clk_divider assignments */
+	div->reg = reg;
+	div->shift = shift;
+	div->width = width;
+	div->flags = clk_divider_flags;
+	div->lock = lock;
+
+	if (parent_name) {
+		div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
+		if (!div->parent[0])
+			goto out;
+	}
+
+	clk = clk_register(dev, name,
+			&clk_divider_ops, &div->hw,
+			div->parent,
+			(parent_name ? 1 : 0),
+			flags);
+	if (clk)
+		return clk;
+
+out:
+	kfree(div->parent[0]);
+	kfree(div);
+
+	return NULL;
+}
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
new file mode 100644
index 0000000..90c79fb
--- /dev/null
+++ b/drivers/clk/clk-fixed-rate.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Fixed rate clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+/*
+ * DOC: basic fixed-rate clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parents are prepared
+ * enable - clk_enable only ensures parents are enabled
+ * rate - rate is always a fixed value.  No clk_set_rate support
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
+
+static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	return to_clk_fixed_rate(hw)->fixed_rate;
+}
+EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate);
+
+struct clk_ops clk_fixed_rate_ops = {
+	.recalc_rate = clk_fixed_rate_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
+
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		unsigned long fixed_rate)
+{
+	struct clk_fixed_rate *fixed;
+	char **parent_names = NULL;
+	u8 len;
+
+	fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
+
+	if (!fixed) {
+		pr_err("%s: could not allocate fixed clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_fixed_rate assignments */
+	fixed->fixed_rate = fixed_rate;
+
+	if (parent_name) {
+		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
+
+		if (! parent_names)
+			goto out;
+
+		len = sizeof(char) * strlen(parent_name);
+
+		parent_names[0] = kmalloc(len, GFP_KERNEL);
+
+		if (!parent_names[0])
+			goto out;
+
+		strncpy(parent_names[0], parent_name, len);
+	}
+
+out:
+	return clk_register(dev, name,
+			&clk_fixed_rate_ops, &fixed->hw,
+			parent_names,
+			(parent_name ? 1 : 0),
+			flags);
+}
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
new file mode 100644
index 0000000..5d50efa
--- /dev/null
+++ b/drivers/clk/clk-gate.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Gated clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+/**
+ * DOC: basic gatable clock which can gate and ungate it's ouput
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional & control gating
+ * rate - inherits rate from parent.  No clk_set_rate support
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+
+static void clk_gate_set_bit(struct clk_gate *gate)
+{
+	u32 reg;
+	unsigned long flags = 0;
+
+	if (gate->lock)
+		spin_lock_irqsave(gate->lock, flags);
+
+	reg = readl(gate->reg);
+	reg |= BIT(gate->bit_idx);
+	writel(reg, gate->reg);
+
+	if (gate->lock)
+		spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static void clk_gate_clear_bit(struct clk_gate *gate)
+{
+	u32 reg;
+	unsigned long flags = 0;
+
+	if (gate->lock)
+		spin_lock_irqsave(gate->lock, flags);
+
+	reg = readl(gate->reg);
+	reg &= ~BIT(gate->bit_idx);
+	writel(reg, gate->reg);
+
+	if (gate->lock)
+		spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int clk_gate_enable(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+
+	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+		clk_gate_clear_bit(gate);
+	else
+		clk_gate_set_bit(gate);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(clk_gate_enable);
+
+static void clk_gate_disable(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+
+	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+		clk_gate_set_bit(gate);
+	else
+		clk_gate_clear_bit(gate);
+}
+EXPORT_SYMBOL_GPL(clk_gate_disable);
+
+static int clk_gate_is_enabled(struct clk_hw *hw)
+{
+	u32 reg;
+	unsigned long flags = 0;
+	struct clk_gate *gate = to_clk_gate(hw);
+
+	if (gate->lock)
+		spin_lock_irqsave(gate->lock, flags);
+
+	reg = readl(gate->reg);
+
+	if (gate->lock)
+		spin_unlock_irqrestore(gate->lock, flags);
+
+	/* if a set bit disables this clk, flip it before masking */
+	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+		reg ^= BIT(gate->bit_idx);
+
+	reg &= BIT(gate->bit_idx);
+
+	return reg ? 1 : 0;
+}
+EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
+
+struct clk_ops clk_gate_ops = {
+	.enable = clk_gate_enable,
+	.disable = clk_gate_disable,
+	.is_enabled = clk_gate_is_enabled,
+};
+EXPORT_SYMBOL_GPL(clk_gate_ops);
+
+struct clk *clk_register_gate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 bit_idx,
+		u8 clk_gate_flags, spinlock_t *lock)
+{
+	struct clk_gate *gate;
+	struct clk *clk;
+
+	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+
+	if (!gate) {
+		pr_err("%s: could not allocate gated clk\n", __func__);
+		return NULL;
+	}
+
+	/* struct clk_gate assignments */
+	gate->reg = reg;
+	gate->bit_idx = bit_idx;
+	gate->flags = clk_gate_flags;
+	gate->lock = lock;
+
+	if (parent_name) {
+		gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
+		if (!gate->parent[0])
+			goto out;
+	}
+
+	clk = clk_register(dev, name,
+			&clk_gate_ops, &gate->hw,
+			gate->parent,
+			(parent_name ? 1 : 0),
+			flags);
+	if (clk)
+		return clk;
+out:
+	kfree(gate->parent[0]);
+	kfree(gate);
+
+	return NULL;
+}
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
new file mode 100644
index 0000000..6fc0878
--- /dev/null
+++ b/drivers/clk/clk-mux.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Simple multiplexer clock implementation
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+/*
+ * DOC: basic adjustable multiplexer clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is only affected by parent switching.  No clk_set_rate support
+ * parent - parent is adjustable through clk_set_parent
+ */
+
+#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
+
+static u8 clk_mux_get_parent(struct clk_hw *hw)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	u32 val;
+	unsigned long flags = 0;
+
+	if (mux->lock)
+		spin_lock_irqsave(mux->lock, flags);
+
+	/*
+	 * FIXME need a mux-specific flag to determine if val is bitwise or numeric
+	 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
+	 * to 0x7 (index starts at one)
+	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
+	 * val = 0x4 really means "bit 2, index starts at bit 0"
+	 */
+	val = readl(mux->reg) >> mux->shift;
+	val &= (1 << mux->width) - 1;
+
+	if (mux->lock)
+		spin_unlock_irqrestore(mux->lock, flags);
+
+	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
+		val = ffs(val) - 1;
+
+	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
+		val--;
+
+	if (val >= __clk_get_num_parents(hw->clk))
+		return -EINVAL;
+
+	return val;
+}
+EXPORT_SYMBOL_GPL(clk_mux_get_parent);
+
+static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	u32 val;
+	unsigned long flags = 0;
+
+	if (mux->flags & CLK_MUX_INDEX_BIT)
+		index = (1 << ffs(index));
+
+	if (mux->flags & CLK_MUX_INDEX_ONE)
+		index++;
+
+	if (mux->lock)
+		spin_lock_irqsave(mux->lock, flags);
+
+	val = readl(mux->reg);
+	val &= ~(((1 << mux->width) - 1) << mux->shift);
+	val |= index << mux->shift;
+	writel(val, mux->reg);
+
+	if (mux->lock)
+		spin_unlock_irqrestore(mux->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(clk_mux_set_parent);
+
+struct clk_ops clk_mux_ops = {
+	.get_parent = clk_mux_get_parent,
+	.set_parent = clk_mux_set_parent,
+};
+EXPORT_SYMBOL_GPL(clk_mux_ops);
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+		char **parent_names, u8 num_parents, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_mux_flags, spinlock_t *lock)
+{
+	struct clk_mux *mux;
+
+	mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL);
+
+	if (!mux) {
+		pr_err("%s: could not allocate mux clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_mux assignments */
+	mux->reg = reg;
+	mux->shift = shift;
+	mux->width = width;
+	mux->flags = clk_mux_flags;
+	mux->lock = lock;
+
+	return clk_register(dev, name, &clk_mux_ops, &mux->hw,
+			parent_names, num_parents, flags);
+}
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 33bf6a7..9d5c4b1 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -45,6 +45,130 @@ struct clk {
 #endif
 };
 
+/*
+ * DOC: Basic clock implementations common to many platforms
+ *
+ * Each basic clock hardware type is comprised of a structure describing the
+ * clock hardware, implementations of the relevant callbacks in struct clk_ops,
+ * unique flags for that hardware type, a registration function and an
+ * alternative macro for static initialization
+ */
+
+extern struct clk_ops clk_fixed_rate_ops;
+
+#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate,		\
+				_fixed_rate_flags)		\
+	static struct clk _name;				\
+	static char *_name##_parent_names[] = {};		\
+	static struct clk_fixed_rate _name##_hw = {		\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.fixed_rate = _rate,				\
+		.flags = _fixed_rate_flags,			\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_fixed_rate_ops,			\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _name##_parent_names,		\
+		.num_parents =					\
+			ARRAY_SIZE(_name##_parent_names),	\
+		.flags = _flags,				\
+	};
+
+extern struct clk_ops clk_gate_ops;
+
+#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,	\
+				_flags, _reg, _bit_idx,		\
+				_gate_flags, _lock)		\
+	static struct clk _name;				\
+	static char *_name##_parent_names[] = {			\
+		_parent_name,					\
+	};							\
+	static struct clk *_name##_parents[] = {		\
+		_parent_ptr,					\
+	};							\
+	static struct clk_gate _name##_hw = {			\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.reg = _reg,					\
+		.bit_idx = _bit_idx,				\
+		.flags = _gate_flags,				\
+		.lock = _lock,					\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_gate_ops,				\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _name##_parent_names,		\
+		.num_parents =					\
+			ARRAY_SIZE(_name##_parent_names),	\
+		.parents = _name##_parents,			\
+		.flags = _flags,				\
+	};
+
+extern struct clk_ops clk_divider_ops;
+
+#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
+				_flags, _reg, _shift, _width,	\
+				_divider_flags, _lock)		\
+	static struct clk _name;				\
+	static char *_name##_parent_names[] = {			\
+		_parent_name,					\
+	};							\
+	static struct clk *_name##_parents[] = {		\
+		_parent_ptr,					\
+	};							\
+	static struct clk_divider _name##_hw = {		\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.reg = _reg,					\
+		.shift = _shift,				\
+		.width = _width,				\
+		.flags = _divider_flags,			\
+		.lock = _lock,					\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_divider_ops,			\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _name##_parent_names,		\
+		.num_parents =					\
+			ARRAY_SIZE(_name##_parent_names),	\
+		.parents = _name##_parents,			\
+		.flags = _flags,				\
+	};
+
+extern struct clk_ops clk_mux_ops;
+
+#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags,	\
+				_reg, _shift, _width,		\
+				_mux_flags, _lock)		\
+	static struct clk _name;				\
+	static struct clk_mux _name##_hw = {			\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.reg = _reg,					\
+		.shift = _shift,				\
+		.width = _width,				\
+		.flags = _mux_flags,				\
+		.lock = _lock,					\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_mux_ops,				\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _parent_names,			\
+		.num_parents =					\
+			ARRAY_SIZE(_parent_names),		\
+		.parents = _parents,				\
+		.flags = _flags,				\
+	};
+
 /**
  * __clk_init - initialize the data structures in a struct clk
  * @dev:	device initializing this clk, placeholder for now
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 09dea1f..853d526 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -129,6 +129,133 @@ struct clk_ops {
 	void		(*init)(struct clk_hw *hw);
 };
 
+/*
+ * DOC: Basic clock implementations common to many platforms
+ *
+ * Each basic clock hardware type is comprised of a structure describing the
+ * clock hardware, implementations of the relevant callbacks in struct clk_ops,
+ * unique flags for that hardware type, a registration function and an
+ * alternative macro for static initialization
+ */
+
+/**
+ * struct clk_fixed_rate - fixed-rate clock
+ * @hw:		handle between common and hardware-specific interfaces
+ * @fixed_rate:	constant frequency of clock
+ */
+struct clk_fixed_rate {
+	struct		clk_hw hw;
+	unsigned long	fixed_rate;
+	u8		flags;
+};
+
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		unsigned long fixed_rate);
+
+/**
+ * struct clk_gate - gating clock
+ *
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register controlling gate
+ * @bit_idx:	single bit controlling gate
+ * @flags:	hardware-specific flags
+ * @lock:	register lock
+ *
+ * Clock which can gate its output.  Implements .enable & .disable
+ *
+ * Flags:
+ * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
+ * 	enable the clock.  Setting this flag does the opposite: setting the bit
+ * 	disable the clock and clearing it enables the clock
+ */
+struct clk_gate {
+	struct clk_hw hw;
+	void __iomem	*reg;
+	u8		bit_idx;
+	u8		flags;
+	spinlock_t	*lock;
+	char		*parent[1];
+};
+
+#define CLK_GATE_SET_TO_DISABLE		BIT(0)
+
+struct clk *clk_register_gate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 bit_idx,
+		u8 clk_gate_flags, spinlock_t *lock);
+
+/**
+ * struct clk_divider - adjustable divider clock
+ *
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register containing the divider
+ * @shift:	shift to the divider bit field
+ * @width:	width of the divider bit field
+ * @lock:	register lock
+ *
+ * Clock with an adjustable divider affecting its output frequency.  Implements
+ * .recalc_rate, .set_rate and .round_rate
+ *
+ * Flags:
+ * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
+ * 	register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
+ * 	the raw value read from the register, with the value of zero considered
+ * 	invalid
+ * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
+ * 	the hardware register
+ */
+struct clk_divider {
+	struct clk_hw	hw;
+	void __iomem	*reg;
+	u8		shift;
+	u8		width;
+	u8		flags;
+	spinlock_t	*lock;
+	char		*parent[1];
+};
+
+#define CLK_DIVIDER_ONE_BASED		BIT(0)
+#define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
+
+struct clk *clk_register_divider(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_divider_flags, spinlock_t *lock);
+
+/**
+ * struct clk_mux - multiplexer clock
+ *
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register controlling multiplexer
+ * @shift:	shift to multiplexer bit field
+ * @width:	width of mutliplexer bit field
+ * @num_clks:	number of parent clocks
+ * @lock:	register lock
+ *
+ * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
+ * and .recalc_rate
+ *
+ * Flags:
+ * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
+ * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two)
+ */
+struct clk_mux {
+	struct clk_hw	hw;
+	void __iomem	*reg;
+	u8		shift;
+	u8		width;
+	u8		flags;
+	spinlock_t	*lock;
+};
+
+#define CLK_MUX_INDEX_ONE		BIT(0)
+#define CLK_MUX_INDEX_BIT		BIT(1)
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+		char **parent_names, u8 num_parents, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_mux_flags, spinlock_t *lock);
 
 /**
  * clk_register - allocate a new clock, register it and return an opaque cookie
-- 
1.7.5.4



From mturquette at linaro.org  Sat Mar 10 02:54:22 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Fri,  9 Mar 2012 23:54:22 -0800
Subject: [PATCH v6 1/3] Documentation: common clk API
In-Reply-To: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
Message-ID: <1331366064-1273-2-git-send-email-mturquette@linaro.org>

Provide documentation for the common clk structures and APIs.  This code
can be found in drivers/clk/ and include/linux/clk*.h.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Mike Turquette <mturquette at ti.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Andrew Lunn <andrew at lunn.ch>
---
Changes since v5:
 * __clk_init must be called for statically initialized clocks
 * added "clk_ops matrix" to better clarify which ops are mandatory

 Documentation/clk.txt |  233 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 233 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/clk.txt

diff --git a/Documentation/clk.txt b/Documentation/clk.txt
new file mode 100644
index 0000000..1943fae
--- /dev/null
+++ b/Documentation/clk.txt
@@ -0,0 +1,233 @@
+		The Common Clk Framework
+		Mike Turquette <mturquette at ti.com>
+
+This document endeavours to explain the common clk framework details,
+and how to port a platform over to this framework.  It is not yet a
+detailed explanation of the clock api in include/linux/clk.h, but
+perhaps someday it will include that information.
+
+	Part 1 - introduction and interface split
+
+The common clk framework is an interface to control the clock nodes
+available on various devices today.  This may come in the form of clock
+gating, rate adjustment, muxing or other operations.  This framework is
+enabled with the CONFIG_COMMON_CLK option.
+
+The interface itself is divided into two halves, each shielded from the
+details of its counterpart.  First is the common definition of struct
+clk which unifies the framework-level accounting and infrastructure that
+has traditionally been duplicated across a variety of platforms.  Second
+is a common implementation of the clk.h api, defined in
+drivers/clk/clk.c.  Finally there is struct clk_ops, whose operations
+are invoked by the clk api implementation.
+
+The second half of the interface is comprised of the hardware-specific
+callbacks registered with struct clk_ops and the corresponding
+hardware-specific structures needed to model a particular clock.  For
+the remainder of this document any reference to a callback in struct
+clk_ops, such as .enable or .set_rate, implies the hardware-specific
+implementation of that code.  Likewise, references to struct clk_foo
+serve as a convenient shorthand for the implementation of the
+hardware-specific bits for the hypothetical "foo" hardware.
+
+Tying the two halves of this interface together is struct clk_hw, which
+is defined in struct clk_foo and pointed to within struct clk.  This
+allows easy for navigation between the two discrete halves of the common
+clock interface.
+
+	Part 2 - common data structures and api
+
+Below is the common struct clk definition from
+include/linux/clk-private.h, modified for brevity:
+
+	struct clk {
+		const char		*name;
+		const struct clk_ops	*ops;
+		struct clk_hw		*hw;
+		char			**parent_names;
+		struct clk		**parents;
+		struct clk		*parent;
+		struct hlist_head	children;
+		struct hlist_node	child_node;
+		...
+	};
+
+The members above make up the core of the clk tree topology.  The clk
+api itself defines several driver-facing functions which operate on
+struct clk.  That api is documented in include/linux/clk.h.
+
+Platforms and devices utilizing the common struct clk use the struct
+clk_ops pointer in struct clk to perform the hardware-specific parts of
+the operations defined in clk.h:
+
+	struct clk_ops {
+		int		(*prepare)(struct clk_hw *hw);
+		void		(*unprepare)(struct clk_hw *hw);
+		int		(*enable)(struct clk_hw *hw);
+		void		(*disable)(struct clk_hw *hw);
+		int		(*is_enabled)(struct clk_hw *hw);
+		unsigned long	(*recalc_rate)(struct clk_hw *hw,
+						unsigned long parent_rate);
+		long		(*round_rate)(struct clk_hw *hw, unsigned long,
+						unsigned long *);
+		int		(*set_parent)(struct clk_hw *hw, u8 index);
+		u8		(*get_parent)(struct clk_hw *hw);
+		int		(*set_rate)(struct clk_hw *hw, unsigned long);
+		void		(*init)(struct clk_hw *hw);
+	};
+
+	Part 3 - hardware clk implementations
+
+The strength of the common struct clk comes from its .ops and .hw pointers
+which abstract the details of struct clk from the hardware-specific bits, and
+vice versa.  To illustrate consider the simple gateable clk implementation in
+drivers/clk/clk-gate.c:
+
+struct clk_gate {
+	struct clk_hw	hw;
+	void __iomem    *reg;
+	u8              bit_idx;
+	...
+};
+
+struct clk_gate contains struct clk_hw hw as well as hardware-specific
+knowledge about which register and bit controls this clk's gating.
+Nothing about clock topology or accounting, such as enable_count or
+notifier_count, is needed here.  That is all handled by the common
+framework code and struct clk.
+
+Let's walk through enabling this clk from driver code:
+
+	struct clk *clk;
+	clk = clk_get(NULL, "my_gateable_clk");
+
+	clk_prepare(clk);
+	clk_enable(clk);
+
+The call graph for clk_enable is very simple:
+
+clk_enable(clk);
+	clk->ops->enable(clk->hw);
+	[resolves to...]
+		clk_gate_enable(hw);
+		[resolves struct clk gate with to_clk_gate(hw)]
+			clk_gate_set_bit(gate);
+
+And the definition of clk_gate_set_bit:
+
+static void clk_gate_set_bit(struct clk_gate *gate)
+{
+	u32 reg;
+
+	reg = __raw_readl(gate->reg);
+	reg |= BIT(gate->bit_idx);
+	writel(reg, gate->reg);
+}
+
+Note that to_clk_gate is defined as:
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, clk)
+
+This pattern of abstraction is used for every clock hardware
+representation.
+
+	Part 4 - supporting your own clk hardware
+
+When implementing support for a new type of clock it only necessary to
+include the following header:
+
+#include <linux/clk-provider.h>
+
+include/linux/clk.h is included within that header and clk-private.h
+must never be included from the code which implements the operations for
+a clock.  More on that below in Part 5.
+
+To construct a clk hardware structure for your platform you must define
+the following:
+
+struct clk_foo {
+	struct clk_hw hw;
+	... hardware specific data goes here ...
+};
+
+To take advantage of your data you'll need to support valid operations
+for your clk:
+
+struct clk_ops clk_foo_ops {
+	.enable		= &clk_foo_enable;
+	.disable	= &clk_foo_disable;
+};
+
+Implement the above functions using container_of:
+
+#define to_clk_foo(_hw) container_of(_hw, struct clk_foo, hw)
+
+int clk_foo_enable(struct clk_hw *hw)
+{
+	struct clk_foo *foo;
+
+	foo = to_clk_foo(hw);
+
+	... perform magic on foo ...
+
+	return 0;
+};
+
+Below is a matrix detailing which clk_ops are mandatory based upon the
+hardware capbilities of that clock.  A cell marked as "y" means
+mandatory, a cell marked as "n" implies that either including that
+callback is invalid or otherwise uneccesary.  Empty cells are either
+optional or must be evaluated on a case-by-case basis.
+
+                           clock hardware characteristics
+	     -----------------------------------------------------------
+             | gate | change rate | single parent | multiplexer | root |
+             |------|-------------|---------------|-------------|------|
+.prepare     |      |             |               |             |      |
+.unprepare   |      |             |               |             |      |
+             |      |             |               |             |      |
+.enable      | y    |             |               |             |      |
+.disable     | y    |             |               |             |      |
+.is_enabled  | y    |             |               |             |      |
+             |      |             |               |             |      |
+.recalc_rate |      | y           |               |             |      |
+.round_rate  |      | y           |               |             |      |
+.set_rate    |      | y           |               |             |      |
+             |      |             |               |             |      |
+.set_parent  |      |             | n             | y           | n    |
+.get_parent  |      |             | n             | y           | n    |
+             |      |             |               |             |      |
+.init        |      |             |               |             |      |
+	     -----------------------------------------------------------
+
+Finally, register your clock at run-time with a hardware-specific
+registration function.  This function simply populates struct clk_foo's
+data and then passes the common struct clk parameters to the framework
+with a call to:
+
+clk_register(...)
+
+See the basic clock types in drivers/clk/clk-*.c for examples.
+
+	Part 5 - static initialization of clock data
+
+For platforms with many clocks (often numbering into the hundreds) it
+may be desirable to statically initialize some clock data.  This
+presents a problem since the definition of struct clk should be hidden
+from everyone except for the clock core in drivers/clk/clk.c.
+
+To get around this problem struct clk's definition is exposed in
+include/linux/clk-private.h along with some macros for more easily
+initializing instances of the basic clock types.  These clocks must
+still be initialized with the common clock framework via a call to
+__clk_init.
+
+clk-private.h must NEVER be included by code which implements struct
+clk_ops callbacks, nor must it be included by any logic which pokes
+around inside of struct clk at run-time.  To do so is a layering
+violation.
+
+To better enforce this policy, always follow this simple rule: any
+statically initialized clock data MUST be defined in a separate file
+from the logic that implements its ops.  Basically separate the logic
+from the data and all is well.
-- 
1.7.5.4



From paul at pwsan.com  Fri Mar  9 23:02:41 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 9 Mar 2012 21:02:41 -0700 (MST)
Subject: [PATCHv5 6/6] ARM: OMAP3 PM: Remove IO Daisychain control from
 cpuidle
In-Reply-To: <1331046702-2472-7-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-7-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203092102030.30879@utopia.booyaka.com>

On Tue, 6 Mar 2012, Tero Kristo wrote:

> From: Vishwanath BS <vishwanath.bs at ti.com>
> 
> As IO Daisy chain sequence is triggered via hwmod mux, there is no need to
> control it from cpuidle path for OMAP3.
> 
> Also as omap3_disable_io_chain is no longer being used, just remove the
> function.
> 
> Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
> Signed-off-by: Tero Kristo <t-kristo at ti.com>
> Reviewed-by: Rajendra Nayak <rnayak at ti.com>

And here's a modified version of this one that takes into account the 
earlier changes.


- Paul

>From ad04159c4ec89eef4026fa2e2aeefc3795d98b89 Mon Sep 17 00:00:00 2001
From: Vishwanath BS <vishwanath.bs at ti.com>
Date: Fri, 2 Mar 2012 17:17:55 +0200
Subject: [PATCH 6/6] ARM: OMAP3: PM: Remove IO Daisychain control from
 cpuidle

As IO Daisy chain sequence is triggered via hwmod mux, there is no need to
control it from cpuidle path for OMAP3.

Also as omap3_disable_io_chain is no longer being used, just remove the
function.

Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
Reviewed-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/pm34xx.c |   14 --------------
 1 files changed, 0 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 378a0de..ed12bb4 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -291,13 +291,6 @@ void omap_sram_idle(void)
 	/* Enable IO-PAD and IO-CHAIN wakeups */
 	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
-	if (omap3_has_io_wakeup() &&
-	    (per_next_state < PWRDM_POWER_ON ||
-	     core_next_state < PWRDM_POWER_ON)) {
-		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
-		if (omap3_has_io_chain_ctrl())
-			omap3_reconfigure_io_chain();
-	}
 
 	pwrdm_pre_transition();
 
@@ -376,13 +369,6 @@ void omap_sram_idle(void)
 			omap3_per_restore_context();
 	}
 
-	/* Disable IO-PAD and IO-CHAIN wakeup */
-	if (omap3_has_io_wakeup() &&
-	    (per_next_state < PWRDM_POWER_ON ||
-	     core_next_state < PWRDM_POWER_ON))
-		omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
-					     PM_WKEN);
-
 	clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 }
 
-- 
1.7.9.1



From jdzheng at broadcom.com  Fri Mar  9 17:07:42 2012
From: jdzheng at broadcom.com (JD (Jiandong) Zheng)
Date: Fri, 9 Mar 2012 14:07:42 -0800
Subject: [PATCH] ARM: BCMRING: Add debug macro
Message-ID: <8628FE4E7912BF47A96AE7DD7BAC0AAD0109D7942F1D@SJEXCHCCR02.corp.ad.broadcom.com>

Add debug macro to bcmring so that it supports LL debug and early printk.

Signed-off-by: Jiandong Zheng jdzheng at broadcom.com
---
 arch/arm/mach-bcmring/include/mach/debug-macro.S |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)
 create mode 100755 arch/arm/mach-bcmring/include/mach/debug-macro.S

diff --git a/arch/arm/mach-bcmring/include/mach/debug-macro.S b/arch/arm/mach-bcmring/include/mach/debug-macro.S
new file mode 100755
index 0000000..fae01fd
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/debug-macro.S
@@ -0,0 +1,19 @@
+/* arch/arm/mach-bcmring/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Based on arch/arm/mach-versatile/include/mach/debug-macro.S 
+ *  by Jiandong Zheng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+		.macro	addruart, rp, rv, tmp
+		mov	\rp,      #0x00012000
+		orr	\rv, \rp, #0xf8000000	@ virtual base
+		orr	\rp, \rp, #0x80000000	@ physical base
+		.endm
+
+#include <asm/hardware/debug-pl01x.S>
-- 
1.7.9.1




From davidb at codeaurora.org  Fri Mar  9 14:39:32 2012
From: davidb at codeaurora.org (David Brown)
Date: Fri,  9 Mar 2012 11:39:32 -0800
Subject: [PATCH] MAINTAINERS: new git entry for arm/mach-msm
Message-ID: <1331321972-9353-1-git-send-email-davidb@codeaurora.org>

Git tree moved to
git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm.git

Signed-off-by: David Brown <davidb at codeaurora.org>
---
 MAINTAINERS |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b087b3bc..3321d75 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -962,7 +962,7 @@ F:	drivers/tty/serial/msm_serial.c
 F:	drivers/platform/msm/
 F:	drivers/*/pm8???-*
 F:	include/linux/mfd/pm8xxx/
-T:	git git://codeaurora.org/quic/kernel/davidb/linux-msm.git
+T:	git git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm.git
 S:	Maintained
 
 ARM/TOSA MACHINE SUPPORT
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From tony at atomide.com  Fri Mar  9 13:33:44 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 9 Mar 2012 10:33:44 -0800
Subject: [PATCH 1/2] ARM: OMAP: Remove CONFIG_OMAP_MCBSP references
In-Reply-To: <1331283078-14846-2-git-send-email-peter.ujfalusi@ti.com>
References: <1331283078-14846-1-git-send-email-peter.ujfalusi@ti.com>
 <1331283078-14846-2-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <20120309183344.GI12083@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120309 00:54]:
> The McBSP driver stack has been moved to ASoC. The CONFIG_OMAP_MCBSP will
> be removed since the CONFIG_SND_OMAP_SOC_MCBSP will trigger to build the
> McBSP (audio) drivers.

Great, glad to see this! Thanks for working on this:

Acked-by: Tony Lindgren <tony at atomide.com>


From tony at atomide.com  Fri Mar  9 13:26:10 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 9 Mar 2012 10:26:10 -0800
Subject: [PATCH] ARM: OMAP2+: Fix compile error when FB_OMAP2 is not set
In-Reply-To: <1331280718.1927.10.camel@deskari>
References: <20120308204328.GW12083@atomide.com>
 <20120308204607.GX12083@atomide.com>
 <1331280718.1927.10.camel@deskari>
Message-ID: <20120309182609.GG12083@atomide.com>

* Tomi Valkeinen <tomi.valkeinen at ti.com> [120309 00:14]:
> On Thu, 2012-03-08 at 12:46 -0800, Tony Lindgren wrote:
> > * Tony Lindgren <tony at atomide.com> [120308 12:11]:
> > > Otherwise we will get:
> > > 
> > > arch/arm/plat-omap/fb.c:101: error: expected ?)? before ?*? token
> > > 
> > > Signed-off-by: Tony Lindgren <tony at atomide.com>
> > > 
> > > ---
> > > 
> > > Tomi, you need something like this for what you have in for-next.
> > > 
> > > --- a/arch/arm/plat-omap/fb.c
> > > +++ b/arch/arm/plat-omap/fb.c
> > > @@ -98,6 +98,8 @@ arch_initcall(omap_init_fb);
> > >  
> > >  #else
> > >  
> > > -void __init omapfb_set_lcd_config(omap_lcd_config *config) { }
> > > +void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
> > > +{
> > > +}
> > >  
> > >  #endif
> > 
> > Also now seeing the following with what you have in for-next:
> > 
> > drivers/video/omap2/displays/panel-taal.c: In function ?taal_num_errors_show?:
> > drivers/video/omap2/displays/panel-taal.c:605: warning: ?errors? may be used uninitialized in this function
> 
> Hmm, my compiler doesn't complain (codesourcery 2010.09-50), so I didn't
> notice that. Which compiler version reports the warning?
> 
> I'm not 100% sure, but I think it's a false warning, the code path that
> uses "errors" should only be ran when "errors" has been set.

This seems to depend on the .config options somehow. Not getting
it with omap2plus_defconfig, but getting it at least with Russell's
omap4430-sdp seed config from:

http://www.arm.linux.org.uk/developer/build/

Using now emdebian 4.3.5-4 as there seems to be some issues
showing all the section warnings with CodeSourcery and Linaro
toolchains.

Regards,

Tony


From grant.likely at secretlab.ca  Fri Mar  9 10:49:11 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 09 Mar 2012 08:49:11 -0700
Subject: [PATCH v2 3/4] arm/dts: OMAP4: Add mmc controller nodes and board
 data
In-Reply-To: <4F4765EC.1000102@ti.com>
References: <1329998490-27555-1-git-send-email-rnayak@ti.com>
 <1329998490-27555-4-git-send-email-rnayak@ti.com>
 <CANrkHUaP7cV_vSKQYZkeF-aS5CEi2CAp3_9aDJKCVOX-67oNPg@mail.gmail.com>
 <4F4765EC.1000102@ti.com>
Message-ID: <20120309154911.8C23C3E08E2@localhost>

On Fri, 24 Feb 2012 15:56:52 +0530, Rajendra Nayak <rnayak at ti.com> wrote:
> On Friday 24 February 2012 03:46 PM, T Krishnamoorthy, Balaji wrote:
> >> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
> >> index 29f4589..9204f60 100644
> >> --- a/arch/arm/boot/dts/omap4.dtsi
> >> +++ b/arch/arm/boot/dts/omap4.dtsi
> >> @@ -25,6 +25,11 @@
> >>                 serial1 =&uart2;
> >>                 serial2 =&uart3;
> >>                 serial3 =&uart4;
> >> +               mmc1 =&mmc1;
> >> +               mmc2 =&mmc2;
> >> +               mmc3 =&mmc3;
> >> +               mmc4 =&mmc4;
> >> +               mmc5 =&mmc5;
> >>         };
> >>
> >>         cpus {
> >> @@ -155,5 +160,31 @@
> >>                         #size-cells =<0>;
> >>                         ti,hwmods = "i2c4";
> >>                 };
> >> +
> >> +               mmc1: mmc at 1 {
> >> +                       compatible = "ti,omap4-hsmmc";
> >> +                       ti,hwmods = "mmc1";
> >> +                       ti,dual-volt;
> >> +               };
> >> +
> >> +               mmc2: mmc at 2 {
> >> +                       compatible = "ti,omap4-hsmmc";
> >> +                       ti,hwmods = "mmc2";
> >> +               };
> >
> > Hi Rajendra,
> > Is there a way to control the device registration order,
> > eMMC connected to mmc2 needs to be registered as /dev/mmcblk0p ...
> > irrespective of whether SD card is mount or not on mmc1 card slot.
> > So that bootargs would not have to be modified when filesystem is on eMMC.
> 
> I don't know if we can, but even if we could, we take care of the same
> bootargs working on two boards (say sdp and panda) *if* on sdp I have my
> filesystem on eMMC and on panda I have it on external card.
> What happens if I want to use my filesystem on both boards on external
> card?

of_alias_get_id() may be able to help you here.  It will extract the id
numbering from the /aliases node.  That is the safe way to do global
enumeration of devices in the device tree (instead of 'cell-index' which
is strongly discouraged)

g.

> 
> >
> >> +
> >> +               mmc3: mmc at 3 {
> >> +                       compatible = "ti,omap4-hsmmc";
> >> +                       ti,hwmods = "mmc3";
> >> +               };
> >> +
> >> +               mmc4: mmc at 4 {
> >> +                       compatible = "ti,omap4-hsmmc";
> >> +                       ti,hwmods = "mmc4";
> >> +               };
> >> +
> >> +               mmc5: mmc at 5 {
> >> +                       compatible = "ti,omap4-hsmmc";
> >> +                       ti,hwmods = "mmc5";
> >> +               };
> >>         };
> >>   };
> >> --
> >> 1.7.1
> >>
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From paul at pwsan.com  Fri Mar  9 13:04:08 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 9 Mar 2012 11:04:08 -0700 (MST)
Subject: [PATCH] ARM: OMAP4: clock: Add aliases for McBSP fclk clocks
In-Reply-To: <alpine.DEB.2.00.1203091101400.7039@utopia.booyaka.com>
References: <1331024133-18201-1-git-send-email-peter.ujfalusi@ti.com>
 <4F5A258F.8050704@ti.com> <20120309180027.GF12083@atomide.com>
 <alpine.DEB.2.00.1203091101400.7039@utopia.booyaka.com>
Message-ID: <alpine.DEB.2.00.1203091103450.7039@utopia.booyaka.com>

On Fri, 9 Mar 2012, Paul Walmsley wrote:

> Please let's not merge this one yet.  It should not be necessary to change 
> the clkdev aliases, this change should occur in the hwmod code.

Sorry, sent this too quickly.  Not the hwmod code, but the opt_clks 
aliases in the hwmod data.


- Paul


From tony at atomide.com  Fri Mar  9 13:00:28 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 9 Mar 2012 10:00:28 -0800
Subject: [PATCH] ARM: OMAP4: clock: Add aliases for McBSP fclk clocks
In-Reply-To: <4F5A258F.8050704@ti.com>
References: <1331024133-18201-1-git-send-email-peter.ujfalusi@ti.com>
 <4F5A258F.8050704@ti.com>
Message-ID: <20120309180027.GF12083@atomide.com>

* Peter Ujfalusi <peter.ujfalusi at ti.com> [120309 07:47]:
> Hi Paul, Tony,
> 
> On 03/06/2012 10:55 AM, Peter Ujfalusi wrote:
> > CLKS signal for McBSP ports can be selected from internal (PRCM) or external
> > (ABE_CLKS pin) source.
> > To be able to use existing code we need to create clock aliases consistent
> > among OMAP2/3/4.
> 
> Would you be able to take a look at this patch?

To me this looks safe to merge via ASoC tree, assuming Paul
acks it too, and it does not cause merge conflicts with
Paul's changes:

Acked-by: Tony Lindgren <tony at atomide.com>


From philipp.zabel at gmail.com  Fri Mar  9 12:35:41 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Fri, 9 Mar 2012 18:35:41 +0100
Subject: [PATCH] pxa/hx4700: Remove pcmcia platform_device structure
In-Reply-To: <1331305076.23513.YahooMailClassic@web29009.mail.ird.yahoo.com>
References: <1331305076.23513.YahooMailClassic@web29009.mail.ird.yahoo.com>
Message-ID: <CA+gwMce5x8XddOoKKNhYVfowstUtfeTNegJYA41av6EBLvS7sg@mail.gmail.com>

On Fri, Mar 9, 2012 at 3:57 PM, Paul Parsons <lost.distance at yahoo.com> wrote:
> The existing pcmcia platform_device structure is not used and is not needed by
> the pending hx4700 PCMCIA/CF support. So let's remove it.
>
> Signed-off-by: Paul Parsons <lost.distance at yahoo.com>

Acked-by: Philipp Zabel <philipp.zabel at gmail.com>

regards
Philipp


From khilman at ti.com  Fri Mar  9 12:30:05 2012
From: khilman at ti.com (Kevin Hilman)
Date: Fri, 09 Mar 2012 09:30:05 -0800
Subject: [GIT PULL] ARM: OMAP: GPIO cleanup and device tree adaptation
In-Reply-To: <CACxGe6uo774Vf=rgnxxT6htFYSu7xROhgT-=Ernfbr9Lp-WvYQ@mail.gmail.com>
 (Grant Likely's message of "Fri, 9 Mar 2012 09:38:12 -0700")
References: <4F5A30DB.7060004@ti.com>
 <CACxGe6uo774Vf=rgnxxT6htFYSu7xROhgT-=Ernfbr9Lp-WvYQ@mail.gmail.com>
Message-ID: <8762ed4r8i.fsf@ti.com>

Hi Grant,

Grant Likely <grant.likely at secretlab.ca> writes:

> On Fri, Mar 9, 2012 at 9:33 AM, Cousson, Benoit <b-cousson at ti.com> wrote:
>> Hi Grant,
>>
>> Please pull the patches for OMAP GPIO DT support.
>> It is based on your current gpio/next branch.
>>
>> Thanks,
>> Benoit
>
> Merged, thanks.

Since you're queuing OMAP GPIO stuff, ping on this one:

    http://marc.info/?l=linux-omap&m=133098903909156&w=2

Thanks,

Kevin


From catalin.marinas at arm.com  Fri Mar  9 12:10:26 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 9 Mar 2012 17:10:26 +0000
Subject: [PATCH v2 5/5] Cortex-M3: Add support for exception handling
In-Reply-To: <1330967042-25612-2-git-send-email-u.kleine-koenig@pengutronix.de>
References: <CAHkRjk70x+Fn+Z4iUxSMc7Zq2cKBo_ka0tNhV0i5JWmEixpRrA@mail.gmail.com>
 <1330967042-25612-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1330967042-25612-2-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120309171026.GF14148@arm.com>

On Mon, Mar 05, 2012 at 05:04:02PM +0000, Uwe Kleine-K?nig wrote:
> To save r0, I'd readd OLD_R0 at the end of pt_regs (plus one buffer word
> to get even alignment). Or would that already be unacceptable because
> it's an ABI change, too?

If we preserve the first part of the pt_regs structure, we could add the
exception return at the end (with two additional 32-bit words to
preserve the 64-bit alignment).

> --- a/arch/arm/kernel/entry-common.S
> +++ b/arch/arm/kernel/entry-common.S
> @@ -473,7 +480,7 @@ __sys_trace:
>  
>  	adr	lr, BSYM(__sys_trace_return)	@ return address
>  	mov	scno, r0			@ syscall number (possibly new)
> -	add	r1, sp, #S_R0 + S_OFF		@ pointer to regs
> +	add	r1, sp, #S_OFF			@ pointer to regs

This change is no longer needed since S_R0 is no 0.

> --- a/arch/arm/kernel/entry-header.S
> +++ b/arch/arm/kernel/entry-header.S
> @@ -26,7 +26,7 @@
>   * The SWI code relies on the fact that R0 is at the bottom of the stack
>   * (due to slow/fast restore user regs).
>   */
> -#if S_R0 != 0
> +#if S_R0 != 0 && !defined(CONFIG_CPU_V7M)

Same here.

> +#ifdef CONFIG_CPU_V7M
> +/*
> + * ARMv7-M exception entry/exit macros.
> + *
> + * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
> + * automatically saved on the current stack (32 words) before
> + * switching to the exception stack (SP_main).
> + *
> + * If exception is taken while in user mode, SP_main is
> + * empty. Otherwise, SP_main is aligned to 64 bit automatically
> + * (CCR.STKALIGN set).
> + *
> + * Linux assumes that the interrupts are disabled when entering an
> + * exception handler and it may BUG if this is not the case. Interrupts
> + * are disabled during entry and reenabled in the exit macro.
> + *
> + * v7m_exception_fast_exit is used when returning from interrupts.
> + *
> + * v7m_exception_slow_exit is used when returning from SVC or PendSV.
> + * When returning to kernel mode, we don't return from exception.
> + */
> +	.macro	v7m_exception_entry
> +	cpsid	i
> +	sub	sp, #S_FRAME_SIZE
> +	stmia	sp, {r0-r12}
> +
> +	@ set r0 to the location of the registers saved by the core during
> +	@ exception entry. Depending on the mode the cpu was in when the
> +	@ exception happend that is either on the main or the process stack.
> +	@ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
> +	@ was used.
> +	tst	lr, #0x4
> +	mrsne	r0, psp
> +	addeq	r0, sp, #S_FRAME_SIZE

Could we use some other registers here like r8-r12 so that we keep r0-r7
for syscall handling later and avoid another ldmia?

> +	add	r0, r0, #20		@ skip over r0-r3, r12
> +	ldmia	r0!, {r1-r3}		@ load saved lr, return address and xPSR
> +
> +	@ calculate the orignal stack pointer value.
> +	@ r0 currently points to the memory location just above the auto saved
> +	@ xPSR. If the FP extension is implemented and bit 4 of EXC_RETURN is 0
> +	@ then space was allocated for FP state. That is space for 18 32-bit
> +	@ values. (If FP extension is unimplemented, bit 4 is 1.)
> +	@ Additionally the cpu might automatically 8-byte align the stack. Bit 9
> +	@ of the saved xPSR specifies if stack aligning took place. In this case
> +	@ another 32-bit value is included in the stack.
> +
> +	tst	lr, #0x10
> +	addeq	r0, r0, #576

I think you can ignore VFP for now. We could change it to do lazy
save/restore and avoid the automatic state saving. If it does this while
in kernel, it takes a bit of extra stack space.

> +	@ save original sp, lr, return address, xPSR and EXC_RETURN
> +	add	r12, sp, #52

Just use S_ARM_SP or whatever asm offsets, it's easier to read.

> +	stmia	r12, {r0-r3, lr}
> +
> +	@ restore registers for system calls
> +	ldmia	sp, {r0-r12}

We could avoid reloading r0-r7 (that's what we actually need for
syscalls) if we don't corrupt them.

> +	.endm
> +
> +	.macro	v7m_exception_fast_exit
> +	@ read r12, sp, lr, return address, xPSR and EXC_RETURN
> +	add	r12, sp, #48

S_ARM_R12?

> +	ldmia	r12, {r1-r5, lr}
> +
> +	tst     r5, #0x100
> +	subne   r2, r2, #4
> +
> +	tst	lr, #0x10
> +	subeq	r2, r2, #576
> +
> +	stmdb	r2!, {r1, r3-r5}		@ write saved r12, lr, return address and xPSR
> +
> +	ldmia	sp, {r1, r3-r5}			@ read saved r0-r3
> +	stmdb	r2!, {r1, r3-r5}		@ write r0-r3 to basic exception frame
> +
> +	tst	lr, #0x4
> +	msrne	psp, r2
> +
> +	ldmia	sp, {r0-r12}
> +	add	sp, #S_FRAME_SIZE
> +	cpsie	i
> +	bx	lr
> +	.endm

In the context v7m_exception_fast_exit is used (return from interrupts),
the previously saved r0-r4,r12 etc. are still on the return stack and
restored from there. There is no need for the ldmia/stmdb to re-create
the interrupted process stack. Here we only need to make sure that we
restore the registers that were not automatically saved and also move
the kernel SP back to the original location (add S_FRAME_SIZE).

We handle rescheduling and work pending by raising PendSV, so we get
another interrupt which would be returned via the slow_exit macro.

> +	.macro	v7m_exception_slow_exit ret_r0
> +	cpsid	i
> +	ldr	lr, [sp, #S_EXCRET]		@ read exception LR
> +	tst     lr, #0x8
> +	bne	1f				@ go to thread mode using exception return
> +
> +	/*
> +	 * return to kernel thread
> +	 * sp is already set up (and might be unset in pt_regs), so only
> +	 * restore r0-r12 and pc
> +	 */
> +	ldmia	sp, {r0-r12}
> +	ldr	lr, [sp, #S_PC]
> +	add	sp, sp, #S_FRAME_SIZE
> +	cpsie	i
> +	bx	lr
> +	/*
> +	 * return to userspace
> +	 */
> +1:
> +	@ read original r12, sp, lr, pc, xPSR
> +	add	r12, sp, #48
> +	ldmia	r12, {r1-r5}
> +
> +	/* stack aligning */
> +	tst	r5, #0x100
> +	subne	r2, r2, #4
> +
> +	/* skip over stack space for fp extension */
> +	tst	lr, #0x10
> +	subeq	r2, r2, #576
> +
> +	/* write basic exception frame */
> +	stmdb	r2!, {r1, r3-r5}		@ saved r12, lr, return address and xPSR
> +	ldmia	sp, {r1, r3-r5}			@ read saved r0-r3
> +	.if	\ret_r0
> +	stmdb	r2!, {r0, r3-r5}		@ restore r0-r3
> +	.else
> +	stmdb	r2!, {r1, r3-r5}		@ restore r0-r3
> +	.endif

This looks fine.

> +	msr	psp, r2
> +
> +	ldmia	sp, {r0-r12}			@ restore original r4-r11

Isn't this reading too much (optimisation)?

> +	add	sp, #S_FRAME_SIZE		@ restore the original MSP
> +	cpsie	i
> +	bx	lr
> +	.endm
> +#endif	/* CONFIG_CPU_V7M */
...
> --- a/arch/arm/kernel/process.c
> +++ b/arch/arm/kernel/process.c
> @@ -452,7 +452,11 @@ asm(	".pushsection .text\n"
>  #ifdef CONFIG_TRACE_IRQFLAGS
>  "	bl	trace_hardirqs_on\n"
>  #endif
> +#ifdef CONFIG_CPU_V7M
> +"	msr	primask, r7\n"
> +#else
>  "	msr	cpsr_c, r7\n"
> +#endif
>  "	mov	r0, r4\n"
>  "	mov	lr, r6\n"
>  "	mov	pc, r5\n"
> @@ -491,6 +495,10 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
>  	regs.ARM_r7 = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;
>  	regs.ARM_pc = (unsigned long)kernel_thread_helper;
>  	regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT;
> +#ifdef CONFIG_CPU_V7M
> +	/* Return to Handler mode */
> +	regs.ARM_EXCRET = 0xfffffff1L;
> +#endif

BTW, do we need to set this here? We don't return to a kernel thread via
exception return.

I currently cannot see any obvious bugs in the code. Since you said it
doesn't work, what are the symptoms?

-- 
Catalin


From linus.walleij at stericsson.com  Fri Mar  9 11:48:21 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 9 Mar 2012 17:48:21 +0100
Subject: [PATCH] ARM: smp_twd: Only wait for reprogramming on active cpus
Message-ID: <1331311701-32071-1-git-send-email-linus.walleij@stericsson.com>

From: Jonas Aaberg <jonas.aberg at stericsson.com>

During booting of cpu1, there is a short window where cpu1
is online, but not active where cpu1 is occupied by waiting
to become active. If cpu0 then decides to schedule something
on cpu1 and wait for it to complete, before cpu0 has set
cpu1 active, we have a deadlock.

Typically it's this CPU frequency transition that happens at
this time, so let's just not wait for it to happen, it will
happen whenever the CPU eventually comes online instead.

Cc: Peter Zijlstra <peterz at infradead.org>
Cc: stable at kernel.org
Signed-off-by: Jonas Aaberg <jonas.aberg at stericsson.com>
Reviewed-by: Rickard Andersson <rickard.andersson at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
This situation occurs as discussed here:
https://lkml.org/lkml/2012/2/29/141

We're also testing this patch from Peter:
https://lkml.org/lkml/2011/12/15/255
---
 arch/arm/kernel/smp_twd.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 7a79b24..692afa4 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -115,10 +115,14 @@ static int twd_cpufreq_transition(struct notifier_block *nb,
 	 * The twd clock events must be reprogrammed to account for the new
 	 * frequency.  The timer is local to a cpu, so cross-call to the
 	 * changing cpu.
+	 *
+	 * Only wait for it to finish, if the cpu is active to avoid
+	 * deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
+	 * booting of that cpu.
 	 */
 	if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
 		smp_call_function_single(freqs->cpu, twd_update_frequency,
-			NULL, 1);
+					 NULL, cpu_active(freqs->cpu));
 
 	return NOTIFY_OK;
 }
-- 
1.7.8



From lost.distance at yahoo.com  Sat Mar 10 17:05:08 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Sat, 10 Mar 2012 22:05:08 +0000 (GMT)
Subject: [PATCH] pxa/hx4700: Reduce sleep mode power consumption by 35%
In-Reply-To: <20120310182144.GA20013@n2100.arm.linux.org.uk>
Message-ID: <1331417108.99129.YahooMailClassic@web29004.mail.ird.yahoo.com>

--- On Sat, 10/3/12, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> > Drive the two Bluetooth UART output GPIOs
> (GPIO43_BTUART_TXD,
> > GPIO45_BTUART_RTS) LOW during sleep mode instead of
> HIGH. This
> > reduces sleep mode power consumption from approximately
> 46 mA/h
> > to approximately 30 mA/h.
> 
> What are you saying here?? I think you're confusing
> power with current.
> Also, current is measured in amps, not amps per second (or a
> scaled
> version of that.)

Apologies for the sloppy nomenclature; evidently electronics is not my
thing.
The figures I quoted were the reduction in accumulated current (charge)
over time. For example in the second case, the charge reduced from 1853500
?Ah to 1782750 ?Ah over 8610 seconds = 29.58 mA.
If that seems high it is: it should be nearer 4.7 mA.

> >? ??? /* BTUART */
> >? ??? GPIO42_BTUART_RXD,
> > -??? GPIO43_BTUART_TXD,
> > +??? GPIO43_GPIO | MFP_AF2 |
> MFP_LPM_DRIVE_LOW,
> 
> I don't believe that's right.
> 
> This expands to:
> 
> ??? MFP_CFG_IN(GPIO43, AF0) | MFP_AF2 |
> MFP_LPM_DRIVE_LOW
> 
> and:
> 
> ??? (MFP_CFG_DEFAULT & ~(MFP_AF_MASK |
> MFP_DIR_MASK)) |
> ??? (MFP_PIN(MFP_PIN_GPIO43) | MFP_AF0 |
> MFP_DIR_IN)
> ??? | MFP_AF2 | MFP_LPM_DRIVE_LOW
> 
> Note the presence of both MFP_AF2 and MFP_AF0 in there.
> 
> The default for GPIO43_BTUART_TXD is:
> 
> ??? MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
> 
> and I'd suggest defining a new GPIO43_BTUART_TXD_LPM_LOW to
> cover your
> case.

It wasn't right but it evaluated to the correct value because MFP_AF0 = 0.
What I intended was: MFP_PIN_GPIO43 | MFP_AF2 | MFP_LPM_DRIVE_LOW
But I'll add the new values to <mach/mfp-pxa27x.h> if that's preferable.

Oddly the absence of direction didn't seem to matter; GPIO43 and GPIO45
default to input here, yet are still being driven as outputs in low power
mode contrary to what the manual says.


From swarren at wwwdotorg.org  Fri Mar  9 11:45:22 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 09 Mar 2012 09:45:22 -0700
Subject: [PATCH 10/11] ARM: tegra: pcie: Add MSI support
In-Reply-To: <20120309065004.GD25208@avionic-0098.mockup.avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-11-git-send-email-thierry.reding@avionic-design.de>
 <4F59213F.6070107@wwwdotorg.org>
 <20120309065004.GD25208@avionic-0098.mockup.avionic-design.de>
Message-ID: <4F5A33A2.4000305@wwwdotorg.org>

On 03/08/2012 11:50 PM, Thierry Reding wrote:
> * Stephen Warren wrote:
>> On 03/08/2012 07:51 AM, Thierry Reding wrote:
>>> This commit adds support for message signaled interrupts to the Tegra
>>> PCIe controller.
>>>
>>> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
>>> ---
>>> This code is taken from the NVIDIA Vibrante kernel and therefore has no
>>> appropriate Signed-off-by from the original author. Maybe someone at
>>> NVIDIA can find out who wrote this code and maybe provide a proper
>>> Signed-off-by that I can add?
>>
>> I think if you look in:
>> git://nv-tegra.nvidia.com/linux-2.6.git android-tegra-2.6.36
>>
>> the following commits are what you're after:
>>
>> de7fd8768b32da66eaf4eaf58473c65f7a76808d
>> arm: tegra: pcie: enabling MSI support for pcie
>>
>> ac1f8310811c64a084511d2afc27f66334b31a81
>> ARM: tegra: pcie: fix return value from MSI irq routine
>>
>> Although the patch below only partially resembles those patches, I guess
>> because you've rewritten the code a lot to conform to the current kernel
>> APIs, clean stuff up, etc. Perhaps just saying "based on code by Krishna
>> Kishore <kthota at nvidia.com>" is enough...
> 
> Yes, it is indeed a major rewrite because the original code had some
> peculiarities and FIXME that I thought wouldn't make it through the review
> anyway so I fixed them up.
> 
> I'll add some comment about the original authorship. There is no official
> Signed-off-by in the original commit. Do I still need one or is it enough to
> mention the original authors in the commit message and add keep my own
> Signed-off-by?

Yes, I think just mentioning the original code author in free-form text,
and including only your S-o-b sounds good to me.


From thomas.abraham at linaro.org  Fri Mar  9 11:43:56 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 9 Mar 2012 22:13:56 +0530
Subject: [PATCH v3 0/4] ARM: Exynos4: Add irq domain and device tree
 support for wakeup interrupts
In-Reply-To: <4F5A30B8.6060801@samsung.com>
References: <1329912858-32750-1-git-send-email-thomas.abraham@linaro.org>
 <4F5A30B8.6060801@samsung.com>
Message-ID: <CAJuYYwTFzuzhWo0CXt4mn8N3pKefKgX6h-NFCkvh4ZYhsw+_OA@mail.gmail.com>

On 9 March 2012 22:02, Kukjin Kim <kgene.kim at samsung.com> wrote:
> On 02/22/12 04:14, Thomas Abraham wrote:
>>
>> Changes since v2:
>> - Reworked irq domain support based on v5 of the irq_domain generalization
>> ? patches.
>>
>> Changes since v1: (only patch 4/4 has changes)
>> - Fixes based on Rob's comments:
>> ? a. Fixed the function prototype of exynos4_init_irq_eint(void)
>> ? b. Included interrupt-parent as an optional property for wakeup
>> interrupt
>> ? ? ? controller node.
>>
>> Samsung Exynos4 includes 32 external wakeup interrupt sources. The first
>> 16
>> of these interrupts are connected to GIC SPI[31:16]. The last 16 of these
>> interrupts are grouped together into one interrupt and connected to GIC
>> SPI[32].
>>
>> This patchset adds irq domain and device tree support for these
>> interrupts.
>> Since there are users of fixed linux irq numbers of the external wakeup
>> interrupts, the legacy mapping is used for the irq domain.
>>
>> This patchset is based on
>> http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> [for-next]
>>
>> with all irq_domain (v5) patches merged from
>> http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]
>>
>> This patchset should be applied after applying the following patch.
>> [PATCH] ARM: Exynos: Add irq domain and device tree support for interrupt
>> combiner
>
>
> Looks ok to me this series, but I lost above patch in my mail box.
> Thomas, could you please send updated it so that I can apply this series?

Dear Mr. Kim,

Sure. I will test and send the patchset based on the your latest
for-next branch.

Thanks,
Thomas.

[...]


From thomas at codesourcery.com  Fri Mar  9 11:38:51 2012
From: thomas at codesourcery.com (Thomas Schwinge)
Date: Fri, 9 Mar 2012 17:38:51 +0100
Subject: [PATCH 5/7] USB: r8a66597-hcd: restore big-endian operation.
In-Reply-To: <1331311133-26937-1-git-send-email-thomas@codesourcery.com>
References: <1331311133-26937-1-git-send-email-thomas@codesourcery.com>
Message-ID: <1331311133-26937-5-git-send-email-thomas@codesourcery.com>

On SH, as of 37b7a97884ba64bf7d403351ac2a9476ab4f1bba we have to use the
endianess-agnostic I/O accessor functions.

This driver is also enabled in ARM's viper_defconfig as well as MIPS'
bcm47xx_defconfig and fuloong2e_defconfig -- I suppose none of these are
operating in big-endian mode, or this issue should already have been noticed
before.

The device is now recognized correctly for both litte-endian and big-endian
sh7785lcr, but I have not tested this any further, as the board is situated in
a remote data center.

Signed-off-by: Thomas Schwinge <thomas at codesourcery.com>
Cc: Paul Mundt <lethal at linux-sh.org>
Cc: linux-sh at vger.kernel.org
Cc: linux-usb at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-mips at linux-mips.org
---
 drivers/usb/host/r8a66597.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
index f28782d..c2ea6d1 100644
--- a/drivers/usb/host/r8a66597.h
+++ b/drivers/usb/host/r8a66597.h
@@ -170,7 +170,7 @@ static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
 
 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
 {
-	return ioread16(r8a66597->reg + offset);
+	return __raw_readw(r8a66597->reg + offset);
 }
 
 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
@@ -198,7 +198,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
 				  unsigned long offset)
 {
-	iowrite16(val, r8a66597->reg + offset);
+	__raw_writew(val, r8a66597->reg + offset);
 }
 
 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
-- 
1.7.4.1



From b-cousson at ti.com  Fri Mar  9 11:39:32 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Fri, 9 Mar 2012 17:39:32 +0100
Subject: [PATCH 08/12] gpio/twl: Allocate irq_desc dynamically for
 SPARSE_IRQ support
In-Reply-To: <4F575B21.30909@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-9-git-send-email-b-cousson@ti.com> <4F575B21.30909@ti.com>
Message-ID: <4F5A3244.3080109@ti.com>

Hi Grant,

Gentle ping for these patches.

Thanks,
Benoit


On 3/7/2012 1:57 PM, Cousson, Benoit wrote:
> Hi Grant,
>
> That fix is tightly coupled with the previous twl4030-irq change, so it
> will be good to pulled it with the twl series through MFD if you are OK
> with that?
>
> Care to ack this one and the next one?
>
> Thanks,
> Benoit
>
>
> On 3/2/2012 5:50 PM, Benoit Cousson wrote:
>> Do not use the board pdata for irq_base, but allocate them dynamically
>> to allow a proper support of SPARSE_IRQ.
>>
>> Fix an unneeded line wrap.
>>
>> Signed-off-by: Benoit Cousson<b-cousson at ti.com>
>> Acked-by: Felipe Balbi<balbi at ti.com>
>> ---
>> drivers/gpio/gpio-twl4030.c | 33 +++++++++++++++++----------------
>> 1 files changed, 17 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
>> index 697396c..49e5c6e 100644
>> --- a/drivers/gpio/gpio-twl4030.c
>> +++ b/drivers/gpio/gpio-twl4030.c
>> @@ -395,23 +395,26 @@ static int gpio_twl4030_remove(struct
>> platform_device *pdev);
>> static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
>> {
>> struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
>> - int ret;
>> + int ret, irq_base;
>>
>> /* maybe setup IRQs */
>> - if (pdata->irq_base) {
>> - if (is_module()) {
>> - dev_err(&pdev->dev,
>> - "can't dispatch IRQs from modules\n");
>> - goto no_irqs;
>> - }
>> - ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO,
>> - pdata->irq_base);
>> - if (ret< 0)
>> - return ret;
>> - WARN_ON(ret != pdata->irq_base);
>> - twl4030_gpio_irq_base = ret;
>> + if (is_module()) {
>> + dev_err(&pdev->dev, "can't dispatch IRQs from modules\n");
>> + goto no_irqs;
>> + }
>> +
>> + irq_base = irq_alloc_descs(-1, 0, TWL4030_GPIO_MAX, 0);
>> + if (irq_base< 0) {
>> + dev_err(&pdev->dev, "Failed to alloc irq_descs\n");
>> + return irq_base;
>> }
>>
>> + ret = twl4030_sih_setup(&pdev->dev, TWL4030_MODULE_GPIO, irq_base);
>> + if (ret< 0)
>> + return ret;
>> +
>> + twl4030_gpio_irq_base = irq_base;
>> +
>> no_irqs:
>> /*
>> * NOTE: boards may waste power if they don't set pullups
>> @@ -443,9 +446,7 @@ no_irqs:
>>
>> ret = gpiochip_add(&twl_gpiochip);
>> if (ret< 0) {
>> - dev_err(&pdev->dev,
>> - "could not register gpiochip, %d\n",
>> - ret);
>> + dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
>> twl_gpiochip.ngpio = 0;
>> gpio_twl4030_remove(pdev);
>> } else if (pdata->setup) {
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html



From grant.likely at secretlab.ca  Fri Mar  9 11:38:12 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 9 Mar 2012 09:38:12 -0700
Subject: [GIT PULL] ARM: OMAP: GPIO cleanup and device tree adaptation
In-Reply-To: <4F5A30DB.7060004@ti.com>
References: <4F5A30DB.7060004@ti.com>
Message-ID: <CACxGe6uo774Vf=rgnxxT6htFYSu7xROhgT-=Ernfbr9Lp-WvYQ@mail.gmail.com>

On Fri, Mar 9, 2012 at 9:33 AM, Cousson, Benoit <b-cousson at ti.com> wrote:
> Hi Grant,
>
> Please pull the patches for OMAP GPIO DT support.
> It is based on your current gpio/next branch.
>
> Thanks,
> Benoit

Merged, thanks.

g.

>
>
> The following changes since commit e4e449e82871c53ef3b22bd3a50fceabc0638926:
> ?Mark Brown (1):
> ? ? ? ?gpiolib: Add comments explaining the _cansleep() WARN_ON()s
>
> are available in the git repository at:
>
> ?git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_grant/for_3.4/dt_gpio
>
> Benoit Cousson (4):
> ? ? ?gpio/omap: Remove bank->id information and misc cleanup
> ? ? ?gpio/omap: Use devm_ API and add request_mem_region
> ? ? ?gpio/omap: Add DT support to GPIO driver
> ? ? ?gpio/omap: Fix IRQ handling for SPARSE_IRQ
>
> ?.../devicetree/bindings/gpio/gpio-omap.txt ? ? ? ? | ? 36 ++++
> ?arch/arm/plat-omap/include/plat/gpio.h ? ? ? ? ? ? | ? 22 +--
> ?drivers/gpio/gpio-omap.c ? ? ? ? ? ? ? ? ? ? ? ? ? | ?208 ++++++++++++++------
> ?3 files changed, 190 insertions(+), 76 deletions(-)
> ?create mode 100644 Documentation/devicetree/bindings/gpio/gpio-omap.txt



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From lost.distance at yahoo.com  Fri Mar  9 11:36:13 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 9 Mar 2012 16:36:13 +0000 (GMT)
Subject: [PATCH v2] pxa/hx4700: Fix basic suspend/resume
Message-ID: <1331310973.21920.YahooMailClassic@web29018.mail.ird.yahoo.com>

Basic suspend/resume is fixed by ensuring that the PGSR registers are set
correctly before sleep mode is entered. In particular four of the active low
resets need to be driven high while in sleep mode, otherwise the unit resets
itself instead of suspending. Another problem was that the PCFR_GPROD bit is set
by the HTC bootloader; this caused GPIO reset (i.e. the reset button) to fail
immediately after returning from sleep mode.

Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
---

V2:
Removed comment about mmc driver not resuming properly: 10 months later it does.
Stopped using the verboten MFP_CFG_OUT().
Changed GPIO88, GPIO72, GPIO96 from KEEP_OUTPUT to DRIVE_HIGH.
Added GPIO61, GPIO81, GPIO116 to global_gpios[].
Assign to PCFR instead of masking it, per manual: "Write 0b0 to reserved bits".
Rebased to linux-3.2-rc6.

diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c
--- clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-04 01:08:09.000000000 +0000
+++ linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-09 16:06:31.121359005 +0000
@@ -121,7 +121,11 @@ static unsigned long hx4700_pin_config[]
 	GPIO19_SSP2_SCLK,
 	GPIO86_SSP2_RXD,
 	GPIO87_SSP2_TXD,
-	GPIO88_GPIO,
+	GPIO88_GPIO | MFP_LPM_DRIVE_HIGH,	/* TSC2046_CS */
+
+	/* BQ24022 Regulator */
+	GPIO72_GPIO | MFP_LPM_DRIVE_HIGH,	/* BQ24022_nCHARGE_EN */
+	GPIO96_GPIO | MFP_LPM_DRIVE_HIGH,	/* BQ24022_ISET2 */
 
 	/* HX4700 specific input GPIOs */
 	GPIO12_GPIO,	/* ASIC3_IRQ */
@@ -134,6 +138,11 @@ static unsigned long hx4700_pin_config[]
 	GPIO108_GPIO,	/* GSM_READY */
 	GPIO58_GPIO,	/* TSC2046_nPENIRQ */
 	GPIO66_GPIO,	/* nSDIO_IRQ */
+
+	GPIO61_GPIO | MFP_LPM_DRIVE_HIGH,	/* W3220_nRESET */
+	GPIO71_GPIO | MFP_LPM_DRIVE_HIGH,	/* ASIC3_nRESET */
+	GPIO81_GPIO | MFP_LPM_DRIVE_HIGH,	/* CPU_GP_nRESET */
+	GPIO116_GPIO | MFP_LPM_DRIVE_HIGH,	/* CPU_HW_nRESET */
 };
 
 /*
@@ -828,15 +837,20 @@ static struct gpio global_gpios[] = {
 	{ GPIO110_HX4700_LCD_LVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_LVDD" },
 	{ GPIO111_HX4700_LCD_AVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_AVDD" },
 	{ GPIO32_HX4700_RS232_ON,         GPIOF_OUT_INIT_HIGH, "RS232_ON" },
+	{ GPIO61_HX4700_W3220_nRESET,     GPIOF_OUT_INIT_HIGH, "W3220_nRESET" },
 	{ GPIO71_HX4700_ASIC3_nRESET,     GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
+	{ GPIO81_HX4700_CPU_GP_nRESET,    GPIOF_OUT_INIT_HIGH, "CPU_GP_nRESET" },
 	{ GPIO82_HX4700_EUART_RESET,      GPIOF_OUT_INIT_HIGH, "EUART_RESET" },
 	{ GPIO105_HX4700_nIR_ON,          GPIOF_OUT_INIT_HIGH, "nIR_EN" },
+	{ GPIO116_HX4700_CPU_HW_nRESET,   GPIOF_OUT_INIT_HIGH, "CPU_HW_nRESET" },
 };
 
 static void __init hx4700_init(void)
 {
 	int ret;
 
+	PCFR = PCFR_GPR_EN | PCFR_OPDE;
+
 	pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
 	ret = gpio_request_array(ARRAY_AND_SIZE(global_gpios));
 	if (ret)



From b-cousson at ti.com  Fri Mar  9 11:33:31 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Fri, 9 Mar 2012 17:33:31 +0100
Subject: [GIT PULL] ARM: OMAP: GPIO cleanup and device tree adaptation
Message-ID: <4F5A30DB.7060004@ti.com>

Hi Grant,

Please pull the patches for OMAP GPIO DT support.
It is based on your current gpio/next branch.

Thanks,
Benoit


The following changes since commit e4e449e82871c53ef3b22bd3a50fceabc0638926:
  Mark Brown (1):
        gpiolib: Add comments explaining the _cansleep() WARN_ON()s

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_grant/for_3.4/dt_gpio

Benoit Cousson (4):
      gpio/omap: Remove bank->id information and misc cleanup
      gpio/omap: Use devm_ API and add request_mem_region
      gpio/omap: Add DT support to GPIO driver
      gpio/omap: Fix IRQ handling for SPARSE_IRQ

 .../devicetree/bindings/gpio/gpio-omap.txt         |   36 ++++
 arch/arm/plat-omap/include/plat/gpio.h             |   22 +--
 drivers/gpio/gpio-omap.c                           |  208 ++++++++++++++------
 3 files changed, 190 insertions(+), 76 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-omap.txt


From nicolas.pitre at linaro.org  Fri Mar  9 11:20:20 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 9 Mar 2012 11:20:20 -0500 (EST)
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <CA+wbFdfF5c+Bw6RrxCm3YThqCRDuDYzanq+HV8a6LyXaBqWrQA@mail.gmail.com>
References: <alpine.DEB.2.00.1202231714590.23091@kaball-desktop>
 <1330019314-20865-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <alpine.LFD.2.02.1203021528150.31242@xanadu.home> <4F5882BF.1030104@arm.com>
 <alpine.LFD.2.02.1203081041340.24151@xanadu.home> <4F58FEC0.8080706@arm.com>
 <CA+wbFdfF5c+Bw6RrxCm3YThqCRDuDYzanq+HV8a6LyXaBqWrQA@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1203091112050.24151@xanadu.home>

On Fri, 9 Mar 2012, Dave Martin wrote:

> Register variables feel like a red herring though.  We're only using
> those because we can't do the needful thing and actually desscribe
> these constraints in the asm constraints (which would seem to be the
> right place).  We specifically don't care where those values are
> except at the boundaries of the asm block itself.

Absolutely.

> Is there a reason why ARM gcc doesn't provide the ability to specify
> such exact-register constraints, or is this more for historical
> reasons?  It is possible?

I don't know how much things have changed since I last looked at the gcc 
code, but implementing this seemed to be pretty trivial at the time.  
The problem would be to determine a good letter scheme to map to actual 
registers.


Nicolas


From dave.martin at linaro.org  Fri Mar  9 10:58:03 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Fri, 9 Mar 2012 15:58:03 +0000
Subject: [PATCH-WIP 01/13] xen/arm: use r12 to pass the hypercall number
 to the hypervisor
In-Reply-To: <4F58FEC0.8080706@arm.com>
References: <alpine.DEB.2.00.1202231714590.23091@kaball-desktop>
 <1330019314-20865-1-git-send-email-stefano.stabellini@eu.citrix.com>
 <1330360043.8557.302.camel@zakaz.uk.xensource.com>
 <20120227180355.GB2023@linaro.org>
 <1330371219.10008.34.camel@dagon.hellion.org.uk>
 <20120228102040.GB2063@linaro.org>
 <1330426133.31269.70.camel@zakaz.uk.xensource.com>
 <alpine.DEB.2.00.1202281149210.23091@kaball-desktop>
 <20120229093436.GA2077@linaro.org>
 <1330509362.4270.20.camel@zakaz.uk.xensource.com>
 <20120229125826.GC2077@linaro.org>
 <alpine.LFD.2.02.1203021528150.31242@xanadu.home>
 <4F5882BF.1030104@arm.com>
 <alpine.LFD.2.02.1203081041340.24151@xanadu.home>
 <4F58FEC0.8080706@arm.com>
Message-ID: <CA+wbFdfF5c+Bw6RrxCm3YThqCRDuDYzanq+HV8a6LyXaBqWrQA@mail.gmail.com>

On Thu, Mar 8, 2012 at 6:47 PM, Richard Earnshaw
<Richard.Earnshaw at arm.com> wrote:
> On 08/03/12 17:21, Nicolas Pitre wrote:
>> On Thu, 8 Mar 2012, Richard Earnshaw wrote:
>>
>>> On 02/03/12 21:15, Nicolas Pitre wrote:
>>>> So, to me, the gcc documentation is perfectly clear on this topic.
>>>> there really _is_ a guarantee that those asm marked variables will be in
>>>> the expected registers on entry to the inline asm, given that the
>>>> variable is _also_ listed as an operand to the asm statement. ?But only
>>>> in that case.
>>>>
>>>> It is true that gcc may reorder other function calls or other code
>>>> around the inline asm and then intervening code can clobber any
>>>> registers. ?Then it is up to gcc to preserve the variable's content
>>>> elsewhere when its register is used for other purposes, and restore it
>>>> when some inline asm statement is referring to it.
>>>>
>>>> And if gcc does not do this then it is buggy. ?Version 3.4.0 of gcc was
>>>> buggy. ?No other gcc versions in the last 7 years had such a problem or
>>>> the __asmeq macro in the kernel would have told us.
>>>>
>>>>> Or, to summarise another way, there is no way to control which register
>>>>> is used to pass something to an inline asm in general (often we get away
>>>>> with this, and there are a lot of inline asms in the kernel that assume
>>>>> it works, but the more you inline the more likely you are to get nasty
>>>>> surprises).
>>>>
>>>> This statement is therefore unfounded and wrong. ?Please direct the
>>>> tools guy who mislead you to the above gcc documentation.
>>>>
>>>
>>> The problem is not really about re-ordering functions but about implicit
>>> functions that come from the source code; for example
>>>
>>> int foo (int a, int b)
>>> {
>>> ? register int x __asm__("r0") = 33;
>>>
>>> ? register int c __asm__("r1") = a / b; /* Ooops, clobbers r0 with
>>> division function call. ?*/
>>>
>>> ? asm ("svc 0" : : "r" (x));
>>> }
>>>
>>> There's nothing in the specification to say what happens if there's a
>>> statement in the code that causes an implicit clobber of your assembly
>>> register.
>>
>> I'm sure gcc is full of implicit behaviors that are not mentioned in
>> the specification. ?But as long as the specification is respected, then
>> there is no need to mention any unobservable side effects from a program
>> flow point of view, right?
>>
>> Why wouldn't gcc be able to respect the documented feature by
>> preventing live variable from being clobbered and reloading them in
>> the specified register at the inline asm entry point, just like it does
>> for function calls?
>>
>> Here's an example code that shows that, unfortunately, gcc is still
>> broken with regards to the documented behavior:
>>
>> extern int bar(int);
>> int foo(int y)
>> {
>> ? ? ? ? register int x __asm__("r1") = 33;
>> ? ? ? ? y += bar(x);
>> ? ? ? ? asm ("@ x should be live in %0 here" : "+r" (x) : "r" (y));
>> ? ? ? ? y += bar(x);
>> ? ? ? ? asm ("@ x should be live in %0 here" : "+r" (x) : "r" (y));
>> ? ? ? ? return x;
>> }
>>
>> Result is:
>>
>> foo:
>> ? ? ? ? stmfd ? sp!, {r4, lr}
>> ? ? ? ? mov ? ? r4, r0
>> ? ? ? ? mov ? ? r0, #33
>> ? ? ? ? bl ? ? ?bar
>> ? ? ? ? add ? ? r4, r0, r4
>> ? ? ? ? @ x should be live in r1 here
>> ? ? ? ? mov ? ? r0, r1
>> ? ? ? ? bl ? ? ?bar
>> ? ? ? ? add ? ? r0, r0, r4
>> ? ? ? ? @ x should be live in r1 here
>> ? ? ? ? mov ? ? r0, r1
>> ? ? ? ? ldmfd ? sp!, {r4, lr}
>> ? ? ? ? bx ? ? ?lr
>>
>> To me this is clearly a bug if gcc is not able to meet the documented
>> expectation. ?And the documented expectation is not at all unreasonable.
>>
> No, in this case it is presumed that /you/ know that calling bar() will
> modify x. ?Thus the code is either well defined (if you know what is in
> r1 after each call to bar), or undefined (if you can't say anything
> about r1 after each call).

It could be argued that since the set of registers involved in the PCS
are well-known, then if the programmer assigns a variable to one of
those registers, then that is a conscious aliasing of the variable
with a global register which can be destroyed at any time as a
consequence of the ABI.  Because there are few guarantees about how
the compiler will or won't transform the code, this suggessts that
asm("rX") annotations can't work reliably for r0-r3 or r12 with the
ARM PCS.

Indeed, the GCC docs do in fact have this to say:

    "register int *p1 asm ("r0") = ...;
    register int *p2 asm ("r1") = ...;
    register int *result asm ("r0");
    asm ( [...] );

[...] beware that a register that is call-clobbered by the target ABI
will be overwritten by any function call in the assignment including
library calls for arithmetic operators.  Also a register may be
clobbered when generating some operations, like variable shift, memory
copy or memory move on x86.  Assuming it is a call-clobbered register,
this may happen to `r0' above by the assignment to `p2'.  Ig you have
to use such a register, use temporary variables for expressions
between the register assignment and use:

    int t1 = ...;
    register int *p1 asm("r0") = ...;
    register int *p2 asm("r1") = t1;
    register int *result asm("r0");
    asm ( [...] )"

But this is at least somewhat in conflict with "The compiler's data
flow analysis is capable of determining where the specified registers
contain live values, and where they are available for other uses."

It also seems to assume -O0 type behaviour where the compiler is doing
a straightforward sequential translation of the code.  Why it is
guaranteed that the assignment to p2 now certainly does not clobber p1
(even as a side effect), what the implied aliasing of result with p1
actually guarantees (or whether the compiler really understands it at
all); or what constraints there are on the compiler reordering or
inserting random extraneous code into the above, I have no idea.  Such
assumptions don't feel very safe in the presence of optimisation.

In other words, all sorts of undocumented guarantees beyond the C
language are needed for it even to be possible to interpret what the
above code examples should mean in the first place.

The documentation leaves a lot of questions unanswered, but it does at
least suggest that other arches have the same kind of potential
pitfalls that we observed on ARM.


Register variables feel like a red herring though.  We're only using
those because we can't do the needful thing and actually desscribe
these constraints in the asm constraints (which would seem to be the
right place).  We specifically don't care where those values are
except at the boundaries of the asm block itself.

Is there a reason why ARM gcc doesn't provide the ability to specify
such exact-register constraints, or is this more for historical
reasons?  It is possible?

Cheers
---Dave


From kgene.kim at samsung.com  Fri Mar  9 10:33:01 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 09 Mar 2012 07:33:01 -0800
Subject: [GIT PULL] Samsung Cleanup EXYNOS clock for v3.4
In-Reply-To: <CAOesGMiWOChuMjLQTK1pGys+oXCc4A=HO-2_=37rh3M6pgUP_g@mail.gmail.com>
References: <4F589474.8050609@samsung.com>
 <CAOesGMiWOChuMjLQTK1pGys+oXCc4A=HO-2_=37rh3M6pgUP_g@mail.gmail.com>
Message-ID: <4F5A22AD.1070907@samsung.com>

On 03/08/12 07:16, Olof Johansson wrote:
> Hi,
>
> On Thu, Mar 8, 2012 at 3:13 AM, Kukjin Kim<kgene.kim at samsung.com>  wrote:
>
>> Kukjin Kim (2):
>>       ARM: EXYNOS: cleanup clock part for new EXYNOS SoCs
>
> This is one large commit that does many things in one change. As the
> patch message says:
>
> ARM: EXYNOS: cleanup clock part for new EXYNOS SoCs
>
> - the prefix of clk register replace S5P_ with EXYNOS4_
> - move mach-exynos/clock.c to mach-exynos/clock-exynos4.c
> - according to moving clock-exynos4.c,
>    move<mach/exynos4-clock.h>  to "clock-exynos4.h"
> - add prefix exynos4_ on clk declaration
>
> It makes it hard to review, especially when you combine a move with
> other changes. It's better to do the move in a separate commit that
> doesn't change code (or only changes very very little) and then do the
> other changes in separate commits later.
>
Hmm...OK, let me do as per your suggestion and will re-send this soon.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Fri Mar  9 10:34:27 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 09 Mar 2012 07:34:27 -0800
Subject: [PATCH V6 1/5] ARM: exynos: Add support AFTR mode on EXYNOS4210
In-Reply-To: <CAK44p22LOnJx=bZRfdzAHt7X_snhJGrNoBuXOfsgwBHLLuUziA@mail.gmail.com>
References: <1329805190-8874-1-git-send-email-amit.kachhap@linaro.org>	<1329805190-8874-2-git-send-email-amit.kachhap@linaro.org>	<CAMXH7KHTgzY7XZ=4rOxsu-Ra8SRTOsCg=YWOLBD1QDTskRbygw@mail.gmail.com>
 <CAK44p22LOnJx=bZRfdzAHt7X_snhJGrNoBuXOfsgwBHLLuUziA@mail.gmail.com>
Message-ID: <4F5A2303.7040403@samsung.com>

On 02/23/12 03:49, Amit Kachhap wrote:
> On 23 February 2012 11:54, Rob Lee<rob.lee at linaro.org>  wrote:

[...]

> Hi Mr kim,
>
> Can this change be accommodated in the current patch series as below
> or should i send a new patchset?
>
I did, Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


> --- a/arch/arm/mach-exynos/cpuidle.c
> +++ b/arch/arm/mach-exynos/cpuidle.c
> @@ -41,7 +41,7 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
>                                  struct cpuidle_driver *drv,
>                                  int index);
>
> -static struct cpuidle_state exynos4_cpuidle_set[] = {
> +static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
>          [0] = {
>                  .enter                  = exynos4_enter_idle,
>                  .exit_latency           = 1,
>
>


From kgene.kim at samsung.com  Fri Mar  9 10:33:15 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 09 Mar 2012 07:33:15 -0800
Subject: [GIT PULL] Samsung Cleanup EXYNOS clock for v3.4
In-Reply-To: <CAJ0PZbQebwvFrmXWn=-m7YH3Ri7t2fvm+E_EKZ45rD7cAyo2UA@mail.gmail.com>
References: <22926872.16671331267895327.JavaMail.weblogic@epml04>
 <CAJ0PZbQebwvFrmXWn=-m7YH3Ri7t2fvm+E_EKZ45rD7cAyo2UA@mail.gmail.com>
Message-ID: <4F5A22BB.2080808@samsung.com>

On 03/08/12 23:06, MyungJoo Ham wrote:
> 2012/3/9 ???<myungjoo.ham at samsung.com>:

[...]

> 
> Hello, Kgene
> 
> I've rebased the branch that was pull-requested to Kgene based on this branch.
> 

OK, thanks. Let me apply this series on top of new cleanup-exynos-clock.

> http://git.infradead.org/users/kmpark/linux-samsung/shortlog/refs/heads/devfreq-for-samsung
> 
> 
> The following changes since commit e01127814c640f6cd06a5c06731c6d1ee8c45101:
> 
>    PM / devfreq: update the name of EXYNOS clock register (2012-03-07
> 03:25:31 -0800)
> 
> are available in the git repository at:
>    git://git.infradead.org / users/kmpark/linux-samsung devfreq-for-samsung
> 
> MyungJoo Ham (4):
>        ARM: EXYNOS4: Add DMC1, allow PPMU access for DMC.
>        ARM: EXYNOS4: Add clock register addresses for Exynos4x12 bus
> devfreq driver
>        ARM Exynos4210-Nuri: support Exynos4210-bus Devfreq driver.
>        PM / devfreq: update the name of EXYNOS clock registers that were omitted.
> 
>   arch/arm/mach-exynos/common.c                  |    7 +++-
>   arch/arm/mach-exynos/include/mach/map.h        |    1 +
>   arch/arm/mach-exynos/include/mach/regs-clock.h |   42 ++++++++++++++++++++++++
>   arch/arm/mach-exynos/mach-nuri.c               |   11 ++++--
>   drivers/devfreq/exynos4_bus.c                  |    6 ++--
>   5 files changed, 60 insertions(+), 7 deletions(-)
> 

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From javier.martin at vista-silicon.com  Fri Mar  9 10:20:40 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:40 +0100
Subject: [PATCH v3 04/13] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw'
 function.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-5-git-send-email-javier.martin@vista-silicon.com>

This function is only used once in the driver and has a lot of checks
that are not needed anymore. For this reason it's been merged
with 'imxdma_enable_hw'.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   57 ++++++++++++-------------------------------------
 1 files changed, 14 insertions(+), 43 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 400082d..f86ac06 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -258,41 +258,6 @@ static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 	return now;
 }
 
-static int
-imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr)
-{
-	int channel = imxdmac->channel;
-
-	imxdmac->internal.sg = NULL;
-
-	if (!dma_address) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!dma_length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-		"dev_addr=0x%08x for write\n",
-		channel, __func__, (unsigned int)dma_address,
-		dma_length, dev_addr);
-
-	imx_dmav1_writel(dma_address, DMA_SAR(channel));
-	imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-	imx_dmav1_writel(imxdmac->internal.ccr_to_device,
-			 DMA_CCR(channel));
-
-	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
-	return 0;
-}
-
 static void imxdma_enable_hw(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -584,20 +549,26 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int ret;
 
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		ret = imxdma_config_channel_hw(imxdmac,
-					  d->config_port, d->config_mem, 0, 0);
-		if (ret < 0)
-			return ret;
-		ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
-		if (ret < 0)
-			return ret;
-		break;
+		imxdmac->internal.sg = NULL;
+
+		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+			 DMA_CCR(imxdmac->channel));
 
+		imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+
+		dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
+			"dma_length=%d\n", __func__, imxdmac->channel,
+			d->dest, d->src, d->len);
+
+		break;
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-- 
1.7.0.4



From philippe.retornaz at epfl.ch  Fri Mar  9 09:55:12 2012
From: philippe.retornaz at epfl.ch (=?utf-8?q?Philippe=20R=C3=A9tornaz?=)
Date: Fri,  9 Mar 2012 15:55:12 +0100
Subject: [PATCH 0/4] mc13783 sound support
Message-ID: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>

Hello

This is patchset enable sound support on boards with mc13783 codec.
The first patch adds the codec driver. It's Sascha's code ported to the
current kernel with some minors additions.
The second patch adds a generic SoC platform driver for imx3 boards with
mc13783 codecs.
The last two patches enable the sound on the mx31moboard boards and on 
mx31pdk_3ds boards.

This patchset has been tested on mx31moboard and mx31pdk_3ds.

It is based on a 3.3-rc6 kernel. I know there are some patches which change
how audmux is handled on i.Mx processor but they are not yet merged so
I prefer to post this patchset based on a known tree than to add another
dependency. If the audmux change is merged I will rebase this patchset.

Small note: If you want to test this, make sure you use redboot as bootloader
or that you have the patch i.MX 35/5 AIPS Setup applied.


Philippe R??tornaz (3):
  Add imx3sound sound support.
  mx31moboard: Add ssi configuration
  imx31pdk: Add sound support

Sascha Hauer (1):
  add a mc13783 codec driver

 arch/arm/mach-imx/Kconfig            |    2 +
 arch/arm/mach-imx/mach-mx31_3ds.c    |   40 ++-
 arch/arm/mach-imx/mach-mx31moboard.c |   37 ++-
 drivers/mfd/mc13xxx-core.c           |    3 +-
 include/linux/mfd/mc13xxx.h          |   11 +
 sound/soc/codecs/Kconfig             |    4 +
 sound/soc/codecs/Makefile            |    2 +
 sound/soc/codecs/mc13783.c           | 1036 ++++++++++++++++++++++++++++++++++
 sound/soc/codecs/mc13783.h           |   30 +
 sound/soc/imx/Kconfig                |   10 +
 sound/soc/imx/Makefile               |    2 +
 sound/soc/imx/imx3sound-mc13783.c    |  141 +++++
 12 files changed, 1315 insertions(+), 3 deletions(-)
 create mode 100644 sound/soc/codecs/mc13783.c
 create mode 100644 sound/soc/codecs/mc13783.h
 create mode 100644 sound/soc/imx/imx3sound-mc13783.c



From philippe.retornaz at epfl.ch  Fri Mar  9 09:55:16 2012
From: philippe.retornaz at epfl.ch (=?utf-8?q?Philippe=20R=C3=A9tornaz?=)
Date: Fri,  9 Mar 2012 15:55:16 +0100
Subject: [PATCH 4/4] imx31pdk: Add sound support
In-Reply-To: <1331304916-4724-4-git-send-email-philippe.retornaz@epfl.ch>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-3-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-4-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <1331304916-4724-5-git-send-email-philippe.retornaz@epfl.ch>


Signed-off-by: Philippe R?tornaz <philippe.retornaz at epfl.ch>
---
 arch/arm/mach-imx/Kconfig         |    1 +
 arch/arm/mach-imx/mach-mx31_3ds.c |   40 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 40 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 2c60f63..61084f2 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -468,6 +468,7 @@ config MACH_MX31_3DS
 	select IMX_HAVE_PLATFORM_IMX2_WDT
 	select IMX_HAVE_PLATFORM_IMX_I2C
 	select IMX_HAVE_PLATFORM_IMX_KEYPAD
+	select IMX_HAVE_PLATFORM_IMX_SSI
 	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_IPU_CORE
 	select IMX_HAVE_PLATFORM_MXC_EHCI
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 4d1aab1..a00efda 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -41,6 +41,8 @@
 #include <mach/iomux-mx3.h>
 #include <mach/3ds_debugboard.h>
 #include <mach/ulpi.h>
+#include <mach/audmux.h>
+#include <mach/ssi.h>
 
 #include "devices-imx31.h"
 
@@ -156,6 +158,11 @@ static int mx31_3ds_pins[] = {
 	MX31_PIN_CSI_VSYNC__CSI_VSYNC,
 	MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
 	IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
+	/* SSI */
+	MX31_PIN_STXD4__STXD4,
+	MX31_PIN_SRXD4__SRXD4,
+	MX31_PIN_SCK4__SCK4,
+	MX31_PIN_SFS4__SFS4,
 };
 
 /*
@@ -488,12 +495,23 @@ static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
 };
 
 /* MC13783 */
+static struct mc13xxx_codec_platform_data mx31pdk_codec = {
+	.dac_ssi_port = MC13783_SSI1_PORT,
+	.adc_ssi_port = MC13783_SSI1_PORT,
+};
+
 static struct mc13xxx_platform_data mc13783_pdata = {
 	.regulators = {
 		.regulators = mx31_3ds_regulators,
 		.num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
 	},
-	.flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC,
+	.codec = &mx31pdk_codec,
+	.flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC |
+		MC13XXX_USE_CODEC,
+};
+
+static struct imx_ssi_platform_data mx31pdk_ssi_pdata = {
+	.flags = IMX_SSI_DMA | IMX_SSI_NET,
 };
 
 /* SPI */
@@ -694,6 +712,24 @@ static void __init mx31_3ds_init(void)
 	mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
 				      "mx31_3ds");
 
+	mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT4_SSI_PINS_4,
+		MXC_AUDMUX_V2_PTCR_SYN,
+		MXC_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0) |
+		MXC_AUDMUX_V2_PDCR_MODE(1) |
+		MXC_AUDMUX_V2_PDCR_INMMASK(0xfc));
+
+	mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT1_SSI0,
+		MXC_AUDMUX_V2_PTCR_SYN |
+		MXC_AUDMUX_V2_PTCR_TFSDIR |
+		MXC_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT4_SSI_PINS_4) |
+		MXC_AUDMUX_V2_PTCR_TCLKDIR |
+		MXC_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT4_SSI_PINS_4) |
+		MXC_AUDMUX_V2_PTCR_RFSDIR |
+		MXC_AUDMUX_V2_PTCR_RFSEL(MX31_AUDMUX_PORT4_SSI_PINS_4) |
+		MXC_AUDMUX_V2_PTCR_RCLKDIR |
+		MXC_AUDMUX_V2_PTCR_RCSEL(MX31_AUDMUX_PORT4_SSI_PINS_4),
+		MXC_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT4_SSI_PINS_4));
+
 	imx31_add_imx_uart0(&uart_pdata);
 	imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 
@@ -741,6 +777,8 @@ static void __init mx31_3ds_init(void)
 	}
 
 	mx31_3ds_init_camera();
+
+	imx31_add_imx_ssi(0, &mx31pdk_ssi_pdata);
 }
 
 static void __init mx31_3ds_timer_init(void)
-- 
1.6.3.3



From lost.distance at yahoo.com  Fri Mar  9 09:57:56 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 9 Mar 2012 14:57:56 +0000 (GMT)
Subject: [PATCH] pxa/hx4700: Remove pcmcia platform_device structure
Message-ID: <1331305076.23513.YahooMailClassic@web29009.mail.ird.yahoo.com>

The existing pcmcia platform_device structure is not used and is not needed by
the pending hx4700 PCMCIA/CF support. So let's remove it.

Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
---

V1:
This was originally included in the pending hx4700 PCMCIA/CF support, but it is
unrelated. Consequently this does not need to wait for the pending ARM SA11x0 /
PXA / SoC-common PCMCIA cleanups.

diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c
--- clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-04 01:08:09.000000000 +0000
+++ linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-09 13:40:26.332448626 +0000
@@ -788,17 +788,6 @@ static struct platform_device audio = {
 
 
 /*
- * PCMCIA
- */
-
-static struct platform_device pcmcia = {
-	.name = "hx4700-pcmcia",
-	.dev  = {
-		.parent = &asic3.dev,
-	},
-};
-
-/*
  * Platform devices
  */
 
@@ -814,7 +803,6 @@ static struct platform_device *devices[]
 	&power_supply,
 	&strataflash,
 	&audio,
-	&pcmcia,
 };
 
 static struct gpio global_gpios[] = {



From m.szyprowski at samsung.com  Fri Mar  9 06:05:03 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 09 Mar 2012 12:05:03 +0100
Subject: [PATCH 1/3] ARM: Exynos: add platform device for core DRM subsystem
In-Reply-To: <1331291105-18152-1-git-send-email-m.szyprowski@samsung.com>
References: <1331291105-18152-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1331291105-18152-2-git-send-email-m.szyprowski@samsung.com>

Add platform device for Exynos DRM core. This device is used for
creating DRM user-space device and allocating memory for display buffers.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/Kconfig              |    5 +++++
 arch/arm/mach-exynos/Makefile             |    1 +
 arch/arm/mach-exynos/dev-drm.c            |   29 +++++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h |    2 ++
 4 files changed, 37 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/dev-drm.c

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 9f40689..5a26944 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -83,6 +83,11 @@ config EXYNOS4_DEV_AHCI
 	help
 	  Compile in platform device definitions for AHCI
 
+config EXYNOS_DEV_DRM
+	bool
+	help
+	  Compile in platform device definitions for core DRM device
+
 config EXYNOS4_SETUP_FIMD0
 	bool
 	help
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 04feed2..39a9ee4 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
 obj-y					+= dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
+obj-$(CONFIG_EXYNOS_DEV_DRM)		+= dev-drm.o
 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)	+= dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
 obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
diff --git a/arch/arm/mach-exynos/dev-drm.c b/arch/arm/mach-exynos/dev-drm.c
new file mode 100644
index 0000000..b2258c8
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-drm.c
@@ -0,0 +1,29 @@
+/*
+ * linux/arch/arm/mach-exynos/dev-drm.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - core DRM device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+#include <plat/devs.h>
+
+static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device exynos_device_drm = {
+	.name	= "exynos-drm",
+	.dev	= {
+		.dma_mask		= &exynos_drm_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	}
+};
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 2dd5267..d4075cb 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -134,6 +134,8 @@ extern struct platform_device exynos4_device_pd[];
 extern struct platform_device exynos4_device_spdif;
 extern struct platform_device exynos4_device_sysmmu;
 
+extern struct platform_device exynos_device_drm;
+
 extern struct platform_device samsung_asoc_dma;
 extern struct platform_device samsung_asoc_idma;
 extern struct platform_device samsung_device_keypad;
-- 
1.7.1.569.g6f426



From s.hauer at pengutronix.de  Fri Mar  9 06:00:28 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 9 Mar 2012 12:00:28 +0100
Subject: [PATCH v2 01/13] dmaengine: imx-dma: merge old dma-v1.c with
 imx-dma.c
In-Reply-To: <1331130825-14947-2-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
 <1331130825-14947-2-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120309110028.GB3852@pengutronix.de>

On Wed, Mar 07, 2012 at 03:33:33PM +0100, Javier Martin wrote:
> It is mainly a simple merge changing the prefix of some
> functions to fit the imx-dma namings.
> 
> As there are no users of the old dma-v1.c api we can safely
> remove this file.
> 
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> ---
> @@ -633,11 +1127,8 @@ static int __exit imxdma_remove(struct platform_device *pdev)
>  
>          dma_async_device_unregister(&imxdma->dma_device);
>  
> -	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
> -		struct imxdma_channel *imxdmac = &imxdma->channel[i];
> -
> -		 imx_dma_free(imxdmac->imxdma_channel);
> -	}
> +	for (i = 0; i < MAX_DMA_CHANNELS; i++)
> +		free_irq(MX2x_INT_DMACH0 + i, NULL);

This lacks a test for i.MX1/21/27. The above is correct for i.MX21/27,
but on i.MX1 you have to free MX1_DMA_INT/MX1_DMA_ERR.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From jm at lentin.co.uk  Sun Mar 11 10:33:26 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sun, 11 Mar 2012 14:33:26 +0000
Subject: [PATCH 2/2] ARM: kirkwood: Convert orion-nand to fdt
In-Reply-To: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1331476406-9844-3-git-send-email-jm@lentin.co.uk>

The DNS-320 and 325 have a NAND partitioned to store uboot, uimage and root
filesystem. Store this information in devicetree.

Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
 .../devicetree/bindings/mtd/orion-nand.txt         |   41 +++++++++++++++++++
 arch/arm/boot/dts/kirkwood-dns320.dts              |   42 ++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-dns325.dts              |   42 ++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c                  |   30 --------------
 arch/arm/mach-kirkwood/common.c                    |    6 +++
 drivers/mtd/nand/orion_nand.c                      |   39 +++++++++++++++++-
 6 files changed, 168 insertions(+), 32 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
new file mode 100644
index 0000000..53fd469
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/orion-nand.txt
@@ -0,0 +1,41 @@
+NAND support for Marvell Orion SoC platforms
+
+Required properties:
+- compatible : "mrvl,orion-nand".
+- reg : Base physical address of the NAND and length of memory mapped
+	region
+
+Optional properties:
+- cle :
+- ale :
+- width :
+- chip-delay :
+
+Examples:
+
+nand at f4000000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cle = <0>;
+	ale = <1>;
+	width = <8>;
+	chip-delay = <25>;
+	compatible = "mrvl,orion-nand";
+	reg = <0xf4000000 0x400>;
+
+	partition at 0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+		read-only;
+	};
+
+	partition at 100000 {
+		label = "uImage";
+		reg = <0x0100000 0x200000>;
+	};
+
+	partition at 300000 {
+		label = "root";
+		reg = <0x0300000 0x7d00000>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index c039041..6772f9d 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -51,4 +51,46 @@
 		dma-mask = <0xffffffff>;
 		phy-version = "";
 	};
+
+	nand at f4000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		cle = <0>;
+		ale = <1>;
+		width = <8>;
+		chip-delay = <25>;
+		compatible = "mrvl,orion-nand";
+		reg = <0xf4000000 0x400>;
+
+		partition at 0 {
+			label = "u-boot";
+			reg = <0x0000000 0x100000>;
+			read-only;
+		};
+
+		partition at 100000 {
+			label = "uImage";
+			reg = <0x0100000 0x500000>;
+		};
+
+		partition at 600000 {
+			label = "ramdisk";
+			reg = <0x0600000 0x500000>;
+		};
+
+		partition at b00000 {
+			label = "image";
+			reg = <0x0b00000 0x6600000>;
+		};
+
+		partition at 7100000 {
+			label = "mini firmware";
+			reg = <0x7100000 0xa00000>;
+		};
+
+		partition at 7b00000 {
+			label = "config";
+			reg = <0x7b00000 0x500000>;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index a7c2c26..34740ad 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -37,4 +37,46 @@
 		dma-mask = <0xffffffff>;
 		phy-version = "";
 	};
+
+	nand at f4000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		cle = <0>;
+		ale = <1>;
+		width = <8>;
+		chip-delay = <25>;
+		compatible = "mrvl,orion-nand";
+		reg = <0xf4000000 0x400>;
+
+		partition at 0 {
+			label = "u-boot";
+			reg = <0x0000000 0x100000>;
+			read-only;
+		};
+
+		partition at 100000 {
+			label = "uImage";
+			reg = <0x0100000 0x500000>;
+		};
+
+		partition at 600000 {
+			label = "ramdisk";
+			reg = <0x0600000 0x500000>;
+		};
+
+		partition at b00000 {
+			label = "image";
+			reg = <0x0b00000 0x6600000>;
+		};
+
+		partition at 7100000 {
+			label = "mini firmware";
+			reg = <0x7100000 0xa00000>;
+		};
+
+		partition at 7b00000 {
+			label = "config";
+			reg = <0x7b00000 0x500000>;
+		};
+	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 0885713..d5bc60a 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -158,35 +158,6 @@ static void __init dreamplug_init(void)
  * DNS-320 & DNS-325 specifics
  ****************************************************************************/
 
-static struct mtd_partition dnskw_nand_parts[] = {
-	{
-		.name		= "u-boot",
-		.offset		= 0,
-		.size		= SZ_1M,
-		.mask_flags	= MTD_WRITEABLE
-	}, {
-		.name		= "uImage",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	}, {
-		.name		= "ramdisk",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	}, {
-		.name		= "image",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 102 * SZ_1M
-	}, {
-		.name		= "mini firmware",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 10 * SZ_1M
-	}, {
-		.name		= "config",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	},
-};
-
 static struct mv643xx_eth_platform_data dnskw_ge00_data = {
 	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
 };
@@ -395,7 +366,6 @@ static void __init dnskw_init(void)
 	u32 dev, rev;
 
 	kirkwood_mpp_conf(dnskw_mpp_config);
-	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
 
 	kirkwood_ge00_init(&dnskw_ge00_data);
 	kirkwood_i2c_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 70ee7ac..f135854 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -505,6 +505,12 @@ static int __init kirkwood_clock_gate(void)
 		of_node_put(np);
 	}
 
+	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-nand");
+	if (np && of_device_is_available(np)) {
+		kirkwood_clk_ctrl |= CGC_RUNIT;
+		of_node_put(np);
+	}
+
 	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-sata");
 	if (np && of_device_is_available(np)) {
 		int nr_ports;
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index 29f505a..5ae0030 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -13,6 +13,7 @@
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
@@ -74,11 +75,13 @@ static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 static int __init orion_nand_probe(struct platform_device *pdev)
 {
 	struct mtd_info *mtd;
+	struct mtd_part_parser_data ppdata = {};
 	struct nand_chip *nc;
 	struct orion_nand_data *board;
 	struct resource *res;
 	void __iomem *io_base;
 	int ret = 0;
+	u32 val = 0;
 
 	nc = kzalloc(sizeof(struct nand_chip) + sizeof(struct mtd_info), GFP_KERNEL);
 	if (!nc) {
@@ -101,7 +104,24 @@ static int __init orion_nand_probe(struct platform_device *pdev)
 		goto no_res;
 	}
 
-	board = pdev->dev.platform_data;
+	if (pdev->dev.of_node) {
+		board = kzalloc(sizeof(struct orion_nand_data), GFP_KERNEL);
+		if (!board) {
+			printk(KERN_ERR "orion_nand: failed to allocate board structure.\n");
+			ret = -ENOMEM;
+			goto no_res;
+		}
+		if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
+			board->cle = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
+			board->ale = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node, "width", &val))
+			board->width = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node,
+						"chip-delay", &val))
+			board->chip_delay = (u8)val;
+	} else
+		board = pdev->dev.platform_data;
 
 	mtd->priv = nc;
 	mtd->owner = THIS_MODULE;
@@ -129,7 +149,8 @@ static int __init orion_nand_probe(struct platform_device *pdev)
 	}
 
 	mtd->name = "orion_nand";
-	ret = mtd_device_parse_register(mtd, NULL, 0,
+	ppdata.of_node = pdev->dev.of_node;
+	ret = mtd_device_parse_register(mtd, NULL, &ppdata,
 			board->parts, board->nr_parts);
 	if (ret) {
 		nand_release(mtd);
@@ -141,6 +162,8 @@ static int __init orion_nand_probe(struct platform_device *pdev)
 no_dev:
 	platform_set_drvdata(pdev, NULL);
 	iounmap(io_base);
+	if (pdev->dev.of_node)
+		kfree(board);
 no_res:
 	kfree(nc);
 
@@ -156,16 +179,28 @@ static int __devexit orion_nand_remove(struct platform_device *pdev)
 
 	iounmap(nc->IO_ADDR_W);
 
+	if (pdev->dev.of_node)
+		kfree(nc->priv);
 	kfree(nc);
 
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id orion_nand_of_match_table[] = {
+	{ .compatible = "mrvl,orion-nand", },
+	{},
+};
+#else
+#define orion_nand_of_match_table NULL
+#endif
+
 static struct platform_driver orion_nand_driver = {
 	.remove		= __devexit_p(orion_nand_remove),
 	.driver		= {
 		.name	= "orion_nand",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(orion_nand_of_match_table),
 	},
 };
 
-- 
1.7.9.1



From LW at KARO-electronics.de  Fri Mar  9 04:32:30 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Fri, 9 Mar 2012 10:32:30 +0100
Subject: [RFC] i.MX: drop secondary clocks
In-Reply-To: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
References: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20313.52782.832292.580932@ipc1.ka-ro>

Hi,

Sascha Hauer writes:
> Hi All,
> 
> On i.MX we currently have grouped clocks, also known as secondary clocks.
> These are clocks that get enabled when the primary clock gets enabled.  This
> doesn't integrate well into the generic clock framework. Also we often return
> the rate of one clock and really enable/disable another clock. I plan to get
> rid of these clocks by exposing the individual clocks to the drivers. The
> following is meant as an example how this can be done. I have a more complete
> series internally but this conflicts with Richards clk_prepare series.
> 
> Thanks to the nature of clk_get we can simply clk_get the individual clocks in
> the drivers and the current clock implementation will always return the one
> with con_id = NULL. Then with the generic clk implementation the drivers will
> finally get the individual clocks.
> 
> So unless there are objections I will follow up on this after the next merge
> window.
> 
I think that's a bad idea! Drivers should not have to know intimate
details about the clock logic of the CPU core they are running on!

They should simply request a clock for the unit they operate on and
the clock core code should figure out which other clocks need to be
enabled on a specific machine to get the unit working.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From tarun.kanti at ti.com  Fri Mar  9 04:25:18 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Fri, 9 Mar 2012 14:55:18 +0530
Subject: [PATCH v3 12/13] gpio/omap: fix incorrect context restore logic
 in omap_gpio_runtime_resume
In-Reply-To: <CAMQu2gzgM=Hc4fis5AsgL50e2KLttTR79iroOtExGecU7F50yw@mail.gmail.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-13-git-send-email-tarun.kanti@ti.com>
 <4F574F95.7090801@ti.com>
 <CAC83ZvLFoSppTiPw-_a=z_Mnpmk6nHeaadTShdJP8RpDWh9TLg@mail.gmail.com>
 <CAMQu2gzgM=Hc4fis5AsgL50e2KLttTR79iroOtExGecU7F50yw@mail.gmail.com>
Message-ID: <CAC83ZvKpLEBRAa1JDM5tGebD514ogqiDqeFraWERG9+x207xcA@mail.gmail.com>

On Thu, Mar 8, 2012 at 12:49 PM, Shilimkar, Santosh
<santosh.shilimkar at ti.com> wrote:
> On Thu, Mar 8, 2012 at 4:58 AM, DebBarma, Tarun Kanti
> <tarun.kanti at ti.com> wrote:
>> On Wed, Mar 7, 2012 at 5:37 PM, Santosh Shilimkar
>> <santosh.shilimkar at ti.com> wrote:
>>> On Wednesday 07 March 2012 12:16 PM, Tarun Kanti DebBarma wrote:
>>>> In omap_gpio_runtime_resume() the context restore should be independent
>>>> of bank->enabled_non_wakeup_gpios. This was preventing context restore
>>>> of GPIO lines which are not wakeup enabled.
>>>>
>>>> Reported-by: Govindraj Raja <govindraj.raja at ti.com>
>>>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>>>> ---
>>>> ?drivers/gpio/gpio-omap.c | ? ?2 +-
>>>> ?1 files changed, 1 insertions(+), 1 deletions(-)
>>>>
>>>> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
>>>> index 2e8e476..ccfbae0 100644
>>>> --- a/drivers/gpio/gpio-omap.c
>>>> +++ b/drivers/gpio/gpio-omap.c
>>>> @@ -1227,7 +1227,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
>>>> ? ? ? __raw_writel(bank->context.risingdetect,
>>>> ? ? ? ? ? ? ? ? ? ?bank->base + bank->regs->risingdetect);
>>>>
>>>> - ? ? if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
>>>> + ? ? if (!bank->workaround_enabled) {
>>> This doesn't seem to be right.
>>> Don't you want to avoid GPIO restore for banks which are in
>>> always on domain. Infact the purpose of "enabled_non_wakeup_gpios"
>>> is exactly that ? Isn't it.
>>>
>>> What am I missing ?
>> The bank->enabled_non_wakeup_gpios is set whenever a gpio line is programmed
>> as edge trigger as shown below.
>> (This is not meant to distinguish between gpios in WKUP domain vs
>> those in PER domain).
>> The context restore should happen irrespective of whether the trigger
>> type is edge or level.
>> In fact context restore was not happening for a gpio line because of
>> this condition while
>> testing suspend/resume.
>>
>> [...]
>> ? ? ? ? ? ? ? ?if (trigger & IRQ_TYPE_EDGE_BOTH)
>> ? ? ? ? ? ? ? ? ? ? ? ?bank->enabled_non_wakeup_gpios |= gpio_bit;
>> ? ? ? ? ? ? ? ?else
>> ? ? ? ? ? ? ? ? ? ? ? ?bank->enabled_non_wakeup_gpios &= ~gpio_bit;
>> [...]
>
> Make sense now. Thanks for clarification Tarun.
> You can add mine..
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Thanks.
I have missed removing the same change from omap_gpio_runtime_suspend().

@@ -1178,9 +1178,6 @@ static int omap_gpio_runtime_suspend(struct device *dev)
         * non-wakeup GPIOs.  Otherwise spurious IRQs will be
         * generated.  See OMAP2420 Errata item 1.101.
         */
-       if (!(bank->enabled_non_wakeup_gpios))
-               goto update_gpio_context_count;
-
FYI, I tested the change on OMAP5 code-base which did not have the above change.
Anyways, I have updated the change in:
git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev
for_3.4/gpio_further_cleanup_fixes
--
Tarun
>
> Regards
> Santosh


From s.hauer at pengutronix.de  Fri Mar  9 04:19:12 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 9 Mar 2012 10:19:12 +0100
Subject: [PATCH v5 0/4] common clk framework
In-Reply-To: <20120309023418.GF3261@b20223-02.ap.freescale.net>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <20120309023418.GF3261@b20223-02.ap.freescale.net>
Message-ID: <20120309091912.GD26882@pengutronix.de>

Hi Richard,

On Fri, Mar 09, 2012 at 10:34:19AM +0800, Richard Zhao wrote:
> Hello Mike,
> 
> The main interface for clk implementer is to register clocks dynamically.
> I think it highly depends on clk DT bindings. From the patch Grant sent
> out, it looks like he doesn't like one node per clk. So how do we
> register clocks dynamically? You have any sample code?

Find my current work based on this series here:

git://git.pengutronix.de/git/imx/linux-2.6.git work/imx-clkv5

This implements the generic clock support for the i.MX v4/v5 based
SoCs. i.MX1 and i.MX27 are runtime tested, i.MX21/25 are compile
tested only.

A typical clock file will then look like this, here the i.MX27
implementation:

8<-------------------------------------------------------


ARM i.MX27: implement clocks using common clock framework

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/Makefile    |    2 +-
 arch/arm/mach-imx/clk-imx27.c |  227 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 228 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-imx/clk-imx27.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d96e2ce..b39f2d6 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -6,7 +6,7 @@ obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
 obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
 
 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
-obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
+obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
 
 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
new file mode 100644
index 0000000..f54e4ee
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -0,0 +1,227 @@
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+
+#include <asm/div64.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include "clk.h"
+
+#define IO_ADDR_CCM(off)	(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
+
+/* Register offsets */
+#define CCM_CSCR		IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0		IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1		IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0		IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1		IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL		IO_ADDR_CCM(0x14)
+#define CCM_PCDR0		IO_ADDR_CCM(0x18)
+#define CCM_PCDR1		IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0		IO_ADDR_CCM(0x20)
+#define CCM_PCCR1		IO_ADDR_CCM(0x24)
+#define CCM_CCSR		IO_ADDR_CCM(0x28)
+#define CCM_PMCTL		IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT		IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL		IO_ADDR_CCM(0x34)
+
+#define CCM_CSCR_UPDATE_DIS	(1 << 31)
+#define CCM_CSCR_SSI2		(1 << 23)
+#define CCM_CSCR_SSI1		(1 << 22)
+#define CCM_CSCR_VPU		(1 << 21)
+#define CCM_CSCR_MSHC           (1 << 20)
+#define CCM_CSCR_SPLLRES        (1 << 19)
+#define CCM_CSCR_MPLLRES        (1 << 18)
+#define CCM_CSCR_SP             (1 << 17)
+#define CCM_CSCR_MCU            (1 << 16)
+#define CCM_CSCR_OSC26MDIV      (1 << 4)
+#define CCM_CSCR_OSC26M         (1 << 3)
+#define CCM_CSCR_FPM            (1 << 2)
+#define CCM_CSCR_SPEN           (1 << 1)
+#define CCM_CSCR_MPEN           (1 << 0)
+
+/* i.MX27 TO 2+ */
+#define CCM_CSCR_ARM_SRC        (1 << 15)
+
+#define CCM_SPCTL1_LF           (1 << 15)
+#define CCM_SPCTL1_BRMO         (1 << 6)
+
+static char *vpu_sel_clks[] = { "spll", "mpll_main2", };
+static char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
+
+struct clkl {
+	struct clk_lookup lookup;
+	const char *clkname;
+};
+
+#define clkdev(d, n, c) \
+	{ \
+		.lookup.dev_id = d, \
+		.lookup.con_id = n, \
+		.clkname = c, \
+	},
+
+static struct clkl lookups[] = {
+	clkdev("imx21-uart.0", "ipg", "uart1_ipg_gate")
+	clkdev("imx21-uart.0", "per", "per1_gate")
+	clkdev("imx21-uart.1", "ipg", "uart2_ipg_gate")
+	clkdev("imx21-uart.1", "per", "per1_gate")
+	clkdev("imx21-uart.2", "ipg", "uart3_ipg_gate")
+	clkdev("imx21-uart.2", "per", "per1_gate")
+	clkdev("imx21-uart.3", "ipg", "uart4_ipg_gate")
+	clkdev("imx21-uart.3", "per", "per1_gate")
+	clkdev("imx21-uart.4", "ipg", "uart5_ipg_gate")
+	clkdev("imx21-uart.4", "per", "per1_gate")
+	clkdev("imx21-uart.5", "ipg", "uart6_ipg_gate")
+	clkdev("imx21-uart.5", "per", "per1_gate")
+	clkdev("imx-gpt.0", "ipg", "gpt1_ipg_gate")
+	clkdev("imx-gpt.0", "per", "per1_gate")
+	clkdev("imx-gpt.1", "ipg", "gpt2_ipg_gate")
+	clkdev("imx-gpt.1", "per", "per1_gate")
+	clkdev("imx-gpt.2", "ipg", "gpt3_ipg_gate")
+	clkdev("imx-gpt.2", "per", "per1_gate")
+	clkdev("imx-gpt.3", "ipg", "gpt4_ipg_gate")
+	clkdev("imx-gpt.3", "per", "per1_gate")
+	clkdev("imx-gpt.4", "ipg", "gpt5_ipg_gate")
+	clkdev("imx-gpt.4", "per", "per1_gate")
+	clkdev("imx-gpt.5", "ipg", "gpt6_ipg_gate")
+	clkdev("imx-gpt.5", "per", "per1_gate")
+	clkdev("mxc_pwm.0", NULL, "pwm")
+	clkdev("mxc-mmc.0", "per", "per2_gate")
+	clkdev("mxc-mmc.0", "ipg", "sdhc1_ipg_gate")
+	clkdev("mxc-mmc.1", "per", "per2_gate")
+	clkdev("mxc-mmc.1", "ipg", "sdhc2_ipg_gate")
+	clkdev("mxc-mmc.2", "per", "per2_gate")
+	clkdev("mxc-mmc.2", "ipg", "sdhc2_ipg_gate")
+	clkdev("imx27-cspi.0", NULL, "cspi1")
+	clkdev("imx27-cspi.1", NULL, "cspi2")
+	clkdev("imx27-cspi.2", NULL, "cspi3")
+	clkdev("imx-fb.0", "per", "per3_gate")
+	clkdev("imx-fb.0", "ipg", "lcdc_ipg_gate")
+	clkdev("imx-fb.0", "ahb", "lcdc_ahb_gate")
+	clkdev("mx2-camera.0", NULL, "csi")
+	clkdev("fsl-usb2-udc", "usb", "usb")
+	clkdev("fsl-usb2-udc", "usb_ahb", "usb_ahb_gate")
+	clkdev("mxc-ehci.0", "usb", "usb")
+	clkdev("mxc-ehci.0", "usb_ahb", "usb_ahb_gate")
+	clkdev("mxc-ehci.1", "usb", "usb")
+	clkdev("mxc-ehci.1", "usb_ahb", "usb_ahb_gate")
+	clkdev("mxc-ehci.2", "usb", "usb")
+	clkdev("mxc-ehci.2", "usb_ahb", "usb_ahb_gate")
+	clkdev("imx-ssi.0", NULL, "ssi1_ipg_gate")
+	clkdev("imx-ssi.1", NULL, "ssi2_ipg_gate")
+	clkdev("mxc_nand.0", NULL, "nfc_baud_gate")
+	clkdev("imx-vpu", "per", "vpu_baud_gate")
+	clkdev("imx-vpu", "ahb", "vpu_ahb_gate")
+	clkdev("imx-dma", "ahb", "dma_ahb_gate")
+	clkdev("imx-dma", "ipg", "dma_ipg_gate")
+	clkdev("imx27-fec.0", "ipg", "fec_ipg_gate")
+	clkdev("imx27-fec.0", "ahb", "fec_ahb_gate")
+	clkdev("imx2-wdt.0", NULL, "wdog_ipg_gate")
+	clkdev("imx-i2c.0", NULL, "i2c1_ipg_gate")
+	clkdev("imx-i2c.1", NULL, "i2c2_ipg_gate")
+	clkdev("mxc_w1.0", NULL, "owire_ipg_gate")
+	clkdev("imx-keypad", NULL, "kpp_ipg_gate")
+	clkdev("imx-emma", "ahb", "emma_ahb_gate")
+	clkdev("imx-emma", "ipg", "emma_ipg_gate")
+	clkdev(NULL, "iim", "iim_ipg_gate")
+	clkdev(NULL, "gpio", "gpio_ipg_gate")
+	clkdev(NULL, "brom", "brom_ahb_gate")
+	clkdev(NULL, "ata", "ata_ahb_gate")
+	clkdev(NULL, "rtc", "rtc_ipg_gate")
+	clkdev(NULL, "scc", "scc_ipg_gate")
+	clkdev(NULL, "cpu", "cpu_div")
+};
+
+int __init mx27_clocks_init(unsigned long fref)
+{
+	int i;
+
+	imx_clk_fixed("dummy", 0);
+	imx_clk_fixed("ckih", fref);
+	imx_clk_pllv1("mpll", "ckih", CCM_MPCTL0);
+	imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
+	imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
+	imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
+	imx_clk_fixed_factor("ipg", "ahb", 1, 1);
+	imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
+	imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
+	imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
+	imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
+	imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
+	imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
+	imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
+	imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
+	imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
+	imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
+	imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
+	imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
+	imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
+	imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
+	imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
+	imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
+	imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
+	imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
+	imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
+	imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
+	imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
+	imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
+	imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
+	imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
+	imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
+	imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
+	imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
+	imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
+	imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
+	imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
+	imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
+	imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
+	imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
+	imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
+	imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
+	imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
+	imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
+	imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
+	imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
+	imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
+	imx_clk_gate("ssi2_baud_gate", "dummy", CCM_PCCR1,  4);
+	imx_clk_gate("ssi1_baud_gate", "dummy", CCM_PCCR1,  5);
+	imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1,  6);
+	imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1,  7);
+	imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1,  8);
+	imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1,  9);
+	imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
+	imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
+	imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
+	imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
+	imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
+	imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
+	imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
+	imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
+	imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
+	imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
+	imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
+	imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
+	imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
+	imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
+	imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
+	imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
+	imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
+	imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
+	imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
+	imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
+	imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
+
+	for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+		struct clkl *l = &lookups[i];
+		l->lookup.clk = __clk_lookup(l->clkname);
+		clkdev_add(&l->lookup);
+	}
+
+	mxc_timer_init(NULL, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
+			MX27_INT_GPT1);
+	return 0;
+}
-- 
1.7.9.1

-- 
Pengutronix e.K.                           |                             |
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From santosh.shilimkar at ti.com  Mon Mar 12 10:34:32 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Mon, 12 Mar 2012 20:04:32 +0530
Subject: [PATCH 1/2] ARM: OMAP: powerdomain: Wait for powerdomain transition
 in pwrdm_state_switch()
In-Reply-To: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
References: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1331562873-29535-2-git-send-email-santosh.shilimkar@ti.com>

Commit b1cbdb00d{OMAP: clockdomain: Wait for powerdomain to be ON
when using clockdomain force wakeup} was assuming that pwrdm_state_switch()
does wait for the powerdomain transition which is not the case.

Fix this API by adding the pwrdm_wait_transition().

Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
CC: Rajendra Nayak <rnayak at ti.com>
CC: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/powerdomain.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 8a18d1b..96ad3dbe 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -972,7 +972,13 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
 
 int pwrdm_state_switch(struct powerdomain *pwrdm)
 {
-	return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
+	int ret;
+
+	ret = pwrdm_wait_transition(pwrdm);
+	if (!ret)
+		ret = _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
+
+	return ret;
 }
 
 int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
-- 
1.7.4.1



From sshtylyov at mvista.com  Sat Mar 10 06:02:38 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sat, 10 Mar 2012 15:02:38 +0400
Subject: [PATCH 5/7] USB: r8a66597-hcd: restore big-endian operation.
In-Reply-To: <1331311133-26937-5-git-send-email-thomas@codesourcery.com>
References: <1331311133-26937-1-git-send-email-thomas@codesourcery.com>
 <1331311133-26937-5-git-send-email-thomas@codesourcery.com>
Message-ID: <4F5B34CE.5040900@mvista.com>

Hello.

On 09-03-2012 20:38, Thomas Schwinge wrote:

> On SH, as of 37b7a97884ba64bf7d403351ac2a9476ab4f1bba we have to use the

    Please also specify the summary of thta commit in parens.

> endianess-agnostic I/O accessor functions.

> This driver is also enabled in ARM's viper_defconfig as well as MIPS'
> bcm47xx_defconfig and fuloong2e_defconfig -- I suppose none of these are
> operating in big-endian mode, or this issue should already have been noticed
> before.

> The device is now recognized correctly for both litte-endian and big-endian
> sh7785lcr, but I have not tested this any further, as the board is situated in
> a remote data center.

> Signed-off-by: Thomas Schwinge<thomas at codesourcery.com>
> Cc: Paul Mundt<lethal at linux-sh.org>
> Cc: linux-sh at vger.kernel.org
> Cc: linux-usb at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-mips at linux-mips.org

WBR, Sergei


From santosh.shilimkar at ti.com  Mon Mar 12 10:34:31 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Mon, 12 Mar 2012 20:04:31 +0530
Subject: [PATCH 0/2] ARM: OMAP4: powerdomain: Misc powerdomain fix and
 associated cleanup
Message-ID: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>

Paul,
Can you please have at this series ?
First patch is the bug fix and second one is the cleanup which you proposed some
time back.

Santosh Shilimkar (2):
  ARM: OMAP: powerdomain: Wait for powerdomain transition in
    pwrdm_state_switch()
  ARM: OMAP: powerdomain: Get rid off duplicate
    pwrdm_clkdm_state_switch() API

 arch/arm/mach-omap2/clock.c       |    2 +-
 arch/arm/mach-omap2/clockdomain.c |    7 +++----
 arch/arm/mach-omap2/powerdomain.c |   14 +++++---------
 arch/arm/mach-omap2/powerdomain.h |    1 -
 4 files changed, 9 insertions(+), 15 deletions(-)

-- 
1.7.4.1



From shawn.guo at linaro.org  Mon Mar 12 07:58:50 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 12 Mar 2012 19:58:50 +0800
Subject: [PATCH v4 03/10] ASoC: fsl: rename imx-pcm Kconfig options and
 filename
In-Reply-To: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331553537-19789-4-git-send-email-shawn.guo@linaro.org>

Rename a couple of imx-pcm Kconfig options and filename to get them
well named and less confusing.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/Kconfig                              |   12 ++++++------
 sound/soc/fsl/Makefile                             |    4 ++--
 sound/soc/fsl/{imx-pcm-dma-mx2.c => imx-pcm-dma.c} |    0
 3 files changed, 8 insertions(+), 8 deletions(-)
 rename sound/soc/fsl/{imx-pcm-dma-mx2.c => imx-pcm-dma.c} (100%)

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 19856a0..e3f7509 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -97,12 +97,12 @@ config SND_SOC_IMX_SSI
 config SND_SOC_IMX_PCM
 	tristate
 
-config SND_MXC_SOC_FIQ
+config SND_SOC_IMX_PCM_FIQ
 	tristate
 	select FIQ
 	select SND_SOC_IMX_PCM
 
-config SND_MXC_SOC_MX2
+config SND_SOC_IMX_PCM_DMA
 	tristate
 	select SND_SOC_DMAENGINE_PCM
 	select SND_SOC_IMX_PCM
@@ -114,7 +114,7 @@ config SND_MXC_SOC_WM1133_EV1
 	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
 	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
 	select SND_SOC_WM8350
-	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_PCM_FIQ
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
@@ -125,7 +125,7 @@ config SND_SOC_MX27VIS_AIC32X4
 	tristate "SoC audio support for Visstrim M10 boards"
 	depends on MACH_IMX27_VISSTRIM_M10 && I2C
 	select SND_SOC_TLV320AIC32X4
-	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_PCM_DMA
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
@@ -137,7 +137,7 @@ config SND_SOC_PHYCORE_AC97
 	depends on MACH_PCM043 || MACH_PCA100
 	select SND_SOC_AC97_BUS
 	select SND_SOC_WM9712
-	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_PCM_FIQ
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
@@ -152,7 +152,7 @@ config SND_SOC_EUKREA_TLV320
 		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
 	depends on I2C
 	select SND_SOC_TLV320AIC23
-	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_PCM_FIQ
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 36c257f..f031409 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -30,8 +30,8 @@ obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
 
 obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
 snd-soc-imx-pcm-y := imx-pcm.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
+snd-soc-imx-pcm-$(CONFIG_SND_SOC_IMX_PCM_FIQ) += imx-pcm-fiq.o
+snd-soc-imx-pcm-$(CONFIG_SND_SOC_IMX_PCM_DMA) += imx-pcm-dma.o
 
 # i.MX Machine Support
 snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
diff --git a/sound/soc/fsl/imx-pcm-dma-mx2.c b/sound/soc/fsl/imx-pcm-dma.c
similarity index 100%
rename from sound/soc/fsl/imx-pcm-dma-mx2.c
rename to sound/soc/fsl/imx-pcm-dma.c
-- 
1.7.5.4



From peter.ujfalusi at ti.com  Fri Mar  9 03:51:18 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Fri,  9 Mar 2012 10:51:18 +0200
Subject: [PATCH 2/2] ASoC: OMAP: Build config cleanup for McBSP
In-Reply-To: <1331283078-14846-1-git-send-email-peter.ujfalusi@ti.com>
References: <1331283078-14846-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1331283078-14846-3-git-send-email-peter.ujfalusi@ti.com>

The McBSP driver stack has been moved, and rewritten resulting a single
driver - selected by CONFIG_SND_OMAP_SOC_MCBSP. There is no longer need to
have CONFIG_OMAP_MCBSP anymore.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 sound/soc/omap/Kconfig  |    6 ------
 sound/soc/omap/Makefile |    3 +--
 2 files changed, 1 insertions(+), 8 deletions(-)

diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
index 4bb7802..deafbfa 100644
--- a/sound/soc/omap/Kconfig
+++ b/sound/soc/omap/Kconfig
@@ -5,13 +5,8 @@ config SND_OMAP_SOC
 config SND_OMAP_SOC_DMIC
 	tristate
 
-config OMAP_MCBSP
-	tristate
-	depends on ARCH_OMAP
-
 config SND_OMAP_SOC_MCBSP
 	tristate
-	select OMAP_MCBSP
 
 config SND_OMAP_SOC_MCPDM
 	tristate
@@ -31,7 +26,6 @@ config SND_OMAP_SOC_N810
 config SND_OMAP_SOC_RX51
 	tristate "SoC Audio support for Nokia RX-51"
 	depends on SND_OMAP_SOC && MACH_NOKIA_RX51
-	select OMAP_MCBSP
 	select SND_OMAP_SOC_MCBSP
 	select SND_SOC_TLV320AIC3X
 	select SND_SOC_TPA6130A2
diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
index 9f8fbd5..1d656bc 100644
--- a/sound/soc/omap/Makefile
+++ b/sound/soc/omap/Makefile
@@ -1,13 +1,12 @@
 # OMAP Platform Support
 snd-soc-omap-objs := omap-pcm.o
 snd-soc-omap-dmic-objs := omap-dmic.o
-snd-soc-omap-mcbsp-objs := omap-mcbsp.o
+snd-soc-omap-mcbsp-objs := omap-mcbsp.o mcbsp.o
 snd-soc-omap-mcpdm-objs := omap-mcpdm.o
 snd-soc-omap-hdmi-objs := omap-hdmi.o
 
 obj-$(CONFIG_SND_OMAP_SOC) += snd-soc-omap.o
 obj-$(CONFIG_SND_OMAP_SOC_DMIC) += snd-soc-omap-dmic.o
-obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o
 obj-$(CONFIG_SND_OMAP_SOC_MCPDM) += snd-soc-omap-mcpdm.o
 obj-$(CONFIG_SND_OMAP_SOC_HDMI) += snd-soc-omap-hdmi.o
-- 
1.7.8.5



From tarun.kanti at ti.com  Fri Mar  9 03:46:52 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Fri, 9 Mar 2012 14:16:52 +0530
Subject: [PATCH v3 05/13] gpio/omap: get rid of retrigger variable in
 gpio_irq_handler
In-Reply-To: <1331118963-26364-6-git-send-email-tarun.kanti@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-6-git-send-email-tarun.kanti@ti.com>
Message-ID: <CAC83ZvJXK-FsiqyQT6BQxggRewkiHZkRBi44CVH15gb4dUbsjw@mail.gmail.com>

On Wed, Mar 7, 2012 at 4:45 PM, Tarun Kanti DebBarma <tarun.kanti at ti.com> wrote:
> This local variable is just assigned zero and then OR'ed
> with isr. It does not appear to serve any purpose and so
> removing it.
Missed following comments from Kevin given in v2. Sorry about that.
I have updated the change in:
git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev
for_3.4/gpio_further_cleanup_fixes

"commit 672e302e3c (ARM: OMAP: use edge/level handlers from generic IRQ
framework) removed retrigger support in favor of using generic IRQ
framework.  This patch cleans up some unused remnants of that removal.
--
Tarun
>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Acked-by: Felipe Balbi <balbi at ti.com>
> ---
> ?drivers/gpio/gpio-omap.c | ? ?3 ---
> ?1 files changed, 0 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 3765654..de5fe8f 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -626,7 +626,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
> ? ? ? ?u32 isr;
> ? ? ? ?unsigned int gpio_irq, gpio_index;
> ? ? ? ?struct gpio_bank *bank;
> - ? ? ? u32 retrigger = 0;
> ? ? ? ?int unmasked = 0;
> ? ? ? ?struct irq_chip *chip = irq_desc_get_chip(desc);
>
> @@ -663,8 +662,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
> ? ? ? ? ? ? ? ? ? ? ? ?chained_irq_exit(chip, desc);
> ? ? ? ? ? ? ? ?}
>
> - ? ? ? ? ? ? ? isr |= retrigger;
> - ? ? ? ? ? ? ? retrigger = 0;
> ? ? ? ? ? ? ? ?if (!isr)
> ? ? ? ? ? ? ? ? ? ? ? ?break;
>
> --
> 1.7.0.4
>


From coelho at ti.com  Fri Mar  9 01:15:02 2012
From: coelho at ti.com (Luciano Coelho)
Date: Fri, 09 Mar 2012 08:15:02 +0200
Subject: [PATCH 0/2] ARM: OMAP2+: PM: code consolidation for 3.4
In-Reply-To: <87d38mbxfu.fsf@ti.com>
References: <20120202093600.12509.35052.stgit@dusk> <87ty39cc7s.fsf@ti.com>
 <alpine.DEB.2.00.1202021140060.586@utopia.booyaka.com>
 <alpine.DEB.2.00.1202021328450.586@utopia.booyaka.com>
 <CAKd1q9rq67gUyXn+rOL348YwaYQiqHR8UQCSd68fpxhZHHsYGA@mail.gmail.com>
 <87sjhjaqyi.fsf@ti.com> <1331232433.18015.69.camel@cumari>
 <alpine.DEB.2.00.1203081153540.9551@utopia.booyaka.com>
 <1331233547.18015.74.camel@cumari> <87d38mbxfu.fsf@ti.com>
Message-ID: <1331273702.18015.92.camel@cumari>

Hi Kevin,

On Thu, 2012-03-08 at 13:21 -0800, Kevin Hilman wrote: 
> Luciano Coelho <coelho at ti.com> writes:
> 
> [...]
> 
> > Thanks, Paul! I was just chatting with Kevin about this on IRC.  With
> > your patch and no_console_suspend, it works. :)
> 
> Just FYI... I've queued this patch from Paul and it's now queued by Tony
> for v3.4 in his cleanup-pm branch.

Great, thanks for the info!

BTW, you and Paul said that it was not recommended to use
no_console_suspend, but Ido (on CC) said that it can be useful for us,
because we need to see if our own (wireless) stuff goes into suspend
correctly.

Are there any real problems with no_console_suspend besides power
consumption? Is it safe for us to simply apply Paul's patch when we need
it?

-- 
Cheers,
Luca.



From grant.likely at secretlab.ca  Thu Mar  8 23:54:23 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 08 Mar 2012 21:54:23 -0700
Subject: [PATCH 00/11] ARM: tegra: Add PCIe device tree support
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120309045423.F34F43E0903@localhost>

On Thu,  8 Mar 2012 15:51:20 +0100, Thierry Reding <thierry.reding at avionic-design.de> wrote:
> This patch series adds support for device tree based probing of the PCIe
> controller found on Tegra SoCs.
> 
> Patches 1 and 2 have already been posted by Grant and Mark respectively
> but I've included them here for reference. Both patches are dependencies
> for the subsequent patches.
> 
> Patches 3, 4 and 5 add support for obtaining the regulators required to
> power the PCIe controller from the device tree. Patches 6 and 7 are
> required to make some common PCI functions available after the init
> phase because the deferred probing will postpone the probing of the PCIe
> controller driver until that point.
> 
> Patches 8 and 9 make the PCIe controller code available as a driver and
> add the corresponding platform devices to the boards that enable PCIe
> (Harmony and TrimSlice). Patch 10 adds MSI support and patch 11 finally
> adds a device tree binding with documentation.
> 
> The code in patch 10 (MSI support) is based on the Vibrante kernel and I
> wasn't able to get a proper Signed-off-by or even copyright information.
> Perhaps somebody at NVIDIA can find out?
> 
> Thierry
> 
> Grant Likely (1):
>   drivercore: Add driver probe deferral mechanism
> 
> Mark Brown (1):
>   regulator: Support driver probe deferral

Greg has picked up the drivercore patch, so the regulator one can be queued
up too now.

g.

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From b39297 at freescale.com  Thu Mar  8 23:47:52 2012
From: b39297 at freescale.com (Wu Guoxing)
Date: Fri, 9 Mar 2012 12:47:52 +0800
Subject: [PATCH v5] ARM : mx35: 3ds-board: add framebuffer device
Message-ID: <1331268472-18270-1-git-send-email-b39297@freescale.com>

From: wu guoxing <b39297 at freescale.com>

This patch adds framebuffer support for freescale mx35 3ds board

Signed-off-by: Wu Guoxing <b39297 at freescale.com>
---
Changes since v4:
	1. fixed a typo error in mx35_3ds_lcd_set_power.
Changes since v3:
	1. use a static variable to save the gpio value instead of find
	the gpiochip every time.
	2. add gpio_request after found the gpio.	
Changes since v2:
	1. use gpio_set_value_cansleep instead of gpio_set_value
Changes since v1:
	1. use gpio driver for mc9s08dz60

 arch/arm/mach-imx/mach-mx35_3ds.c |  121 +++++++++++++++++++++++++++++++++++++
 1 files changed, 121 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c..fa7c7f3 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -40,9 +40,94 @@
 #include <mach/iomux-mx35.h>
 #include <mach/irqs.h>
 #include <mach/3ds_debugboard.h>
+#include <video/platform_lcd.h>
 
 #include "devices-imx35.h"
 
+static const struct fb_videomode fb_modedb[] = {
+	{
+		 /* 800x480 @ 55 Hz */
+		 .name = "Ceramate-CLAA070VC01",
+		 .refresh = 55,
+		 .xres = 800,
+		 .yres = 480,
+		 .pixclock = 40000,
+		 .left_margin = 40,
+		 .right_margin = 40,
+		 .upper_margin = 5,
+		 .lower_margin = 5,
+		 .hsync_len = 20,
+		 .vsync_len = 10,
+		 .sync = FB_SYNC_OE_ACT_HIGH,
+		 .vmode = FB_VMODE_NONINTERLACED,
+		 .flag = 0,
+	 },
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+	.irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+	.name = "Ceramate-CLAA070VC01",
+	.mode = fb_modedb,
+	.num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static struct i2c_board_info __initdata i2c_devices_3ds[] = {
+	{
+		I2C_BOARD_INFO("mc9s08dz60", 0x69),
+	},
+};
+
+static int lcd_power_gpio = -ENXIO;
+
+static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
+						     void *data)
+{
+	return !strcmp(chip->label, data);
+}
+
+static int mc9s08dz60_lcd_gpio_get(void)
+{
+	struct gpio_chip *chip;
+
+	if (!gpio_is_valid(lcd_power_gpio)) {
+		chip = gpiochip_find(
+				"mc9s08dz60", mc9s08dz60_gpiochip_match);
+		if (chip) {
+			lcd_power_gpio = chip->base + 6;
+			if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
+				pr_err("error: gpio already requested by other!\n");
+				lcd_power_gpio = -ENXIO;
+			}
+		} else {
+			pr_err("error: didn't find mc9s08dz60 gpio chip\n");
+			lcd_power_gpio = -ENXIO;
+		}
+	}
+
+	return lcd_power_gpio;
+}
+
+static void mx35_3ds_lcd_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+	int gpio;
+
+	gpio = mc9s08dz60_lcd_gpio_get();
+	if (gpio_is_valid(gpio))
+		gpio_set_value_cansleep(gpio, power);
+}
+
+static struct plat_lcd_data mx35_3ds_lcd_data = {
+	.set_power = mx35_3ds_lcd_set_power,
+};
+
+static struct platform_device mx35_3ds_lcd = {
+	.name = "platform-lcd",
+	.dev.platform_data = &mx35_3ds_lcd_data,
+};
+
 #define EXPIO_PARENT_INT	gpio_to_irq(IMX_GPIO_NR(1, 1))
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -120,6 +205,32 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
 	/* I2C1 */
 	MX35_PAD_I2C1_CLK__I2C1_SCL,
 	MX35_PAD_I2C1_DAT__I2C1_SDA,
+	/* Display */
+	MX35_PAD_LD0__IPU_DISPB_DAT_0,
+	MX35_PAD_LD1__IPU_DISPB_DAT_1,
+	MX35_PAD_LD2__IPU_DISPB_DAT_2,
+	MX35_PAD_LD3__IPU_DISPB_DAT_3,
+	MX35_PAD_LD4__IPU_DISPB_DAT_4,
+	MX35_PAD_LD5__IPU_DISPB_DAT_5,
+	MX35_PAD_LD6__IPU_DISPB_DAT_6,
+	MX35_PAD_LD7__IPU_DISPB_DAT_7,
+	MX35_PAD_LD8__IPU_DISPB_DAT_8,
+	MX35_PAD_LD9__IPU_DISPB_DAT_9,
+	MX35_PAD_LD10__IPU_DISPB_DAT_10,
+	MX35_PAD_LD11__IPU_DISPB_DAT_11,
+	MX35_PAD_LD12__IPU_DISPB_DAT_12,
+	MX35_PAD_LD13__IPU_DISPB_DAT_13,
+	MX35_PAD_LD14__IPU_DISPB_DAT_14,
+	MX35_PAD_LD15__IPU_DISPB_DAT_15,
+	MX35_PAD_LD16__IPU_DISPB_DAT_16,
+	MX35_PAD_LD17__IPU_DISPB_DAT_17,
+	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
+	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
 };
 
 static int mx35_3ds_otg_init(struct platform_device *pdev)
@@ -179,6 +290,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
  */
 static void __init mx35_3ds_init(void)
 {
+	struct platform_device *imx35_fb_pdev;
+
 	imx35_soc_init();
 
 	mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
@@ -204,6 +317,14 @@ static void __init mx35_3ds_init(void)
 		pr_warn("Init of the debugboard failed, all "
 				"devices on the debugboard are unusable.\n");
 	imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+
+	i2c_register_board_info(
+		0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
+
+	imx35_add_ipu_core(&mx3_ipu_data);
+	imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
+	mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
+	platform_device_register(&mx35_3ds_lcd);
 }
 
 static void __init mx35pdk_timer_init(void)
-- 
1.7.1




From rusty at rustcorp.com.au  Thu Mar  8 23:26:52 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 09 Mar 2012 14:56:52 +1030
Subject: [PATCH 1/8] ARM: KVM: Fix missing clobber (causes host oops on UP)
Message-ID: <1331267212.8104.rusty@rustcorp.com.au>


From: Rusty Russell <rusty at rustcorp.com.au>

Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
---
 arch/arm/kvm/arm.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 3772847..f27a96b 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -585,7 +585,7 @@ static void cpu_set_vector(void *vector)
 		"smc	#0\n\t" : :
 		[vector_ptr] "r" (vector_ptr),
 		[smc_hyp_nr] "r" (smc_hyp_nr) :
-		"r0", "r1");
+		"r0", "r1", "r7");
 }
 
 static void cpu_init_hyp_mode(void *vector)



From rusty at rustcorp.com.au  Thu Mar  8 23:26:52 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 09 Mar 2012 14:56:52 +1030
Subject: [PATCH 2/8] ARM: KVM: neaten offset calculations.
Message-ID: <1331267212.29504.rusty@rustcorp.com.au>


From: Rusty Russell <rusty at rustcorp.com.au>

If we do this the C-correct way, we use fewer casts and it's a bit clearer.

Signed-off-by: Rusty Russell <rusty at rustcorp.com.au>
---
 arch/arm/include/asm/kvm_host.h |    6 +++-
 arch/arm/kvm/emulate.c          |   60 ++++++++++++++++++++-------------------
 2 files changed, 36 insertions(+), 30 deletions(-)

diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 8002903..e211d8e 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -86,7 +86,11 @@ enum cp15_regs {
 };
 
 struct kvm_vcpu_arch {
-	struct kvm_vcpu_regs regs;
+	/* We sometimes access these as an array for simplicity. */
+	union {
+		struct kvm_vcpu_regs regs;
+		u32 reg_array[sizeof(struct kvm_vcpu_regs) / sizeof(u32)];
+	};
 
 	/* System control coprocessor (cp15) */
 	u32 cp15[nr_cp15_regs];
diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
index 4f5f2de..108db38 100644
--- a/arch/arm/kvm/emulate.c
+++ b/arch/arm/kvm/emulate.c
@@ -22,8 +22,10 @@
 
 #include "trace.h"
 
-#define USR_REG_OFFSET(_reg) \
-	offsetof(struct kvm_vcpu_arch, regs.usr_regs[_reg])
+#define REG_OFFSET(_reg) \
+	(offsetof(struct kvm_vcpu_regs, _reg) / sizeof(u32))
+
+#define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs[_num])
 
 static const unsigned long vcpu_reg_offsets[MODE_SYS + 1][16] = {
 	/* FIQ Registers */
@@ -31,14 +33,14 @@ static const unsigned long vcpu_reg_offsets[MODE_SYS + 1][16] = {
 		USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
 		USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
 		USR_REG_OFFSET(6), USR_REG_OFFSET(7),
-		offsetof(struct kvm_vcpu_arch, regs.fiq_regs[1]), /* r8 */
-		offsetof(struct kvm_vcpu_arch, regs.fiq_regs[1]), /* r9 */
-		offsetof(struct kvm_vcpu_arch, regs.fiq_regs[2]), /* r10 */
-		offsetof(struct kvm_vcpu_arch, regs.fiq_regs[3]), /* r11 */
-		offsetof(struct kvm_vcpu_arch, regs.fiq_regs[4]), /* r12 */
-		offsetof(struct kvm_vcpu_arch, regs.fiq_regs[5]), /* r13 */
-		offsetof(struct kvm_vcpu_arch, regs.fiq_regs[6]), /* r14 */
-		offsetof(struct kvm_vcpu_arch, regs.pc)		  /* r15 */
+		REG_OFFSET(fiq_regs[1]), /* r8 */
+		REG_OFFSET(fiq_regs[1]), /* r9 */
+		REG_OFFSET(fiq_regs[2]), /* r10 */
+		REG_OFFSET(fiq_regs[3]), /* r11 */
+		REG_OFFSET(fiq_regs[4]), /* r12 */
+		REG_OFFSET(fiq_regs[5]), /* r13 */
+		REG_OFFSET(fiq_regs[6]), /* r14 */
+		REG_OFFSET(pc)		 /* r15 */
 	},
 
 	/* IRQ Registers */
@@ -48,9 +50,9 @@ static const unsigned long vcpu_reg_offsets[MODE_SYS + 1][16] = {
 		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
 		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
 		USR_REG_OFFSET(12),
-		offsetof(struct kvm_vcpu_arch, regs.irq_regs[0]), /* r13 */
-		offsetof(struct kvm_vcpu_arch, regs.irq_regs[1]), /* r14 */
-		offsetof(struct kvm_vcpu_arch, regs.pc)	          /* r15 */
+		REG_OFFSET(irq_regs[0]), /* r13 */
+		REG_OFFSET(irq_regs[1]), /* r14 */
+		REG_OFFSET(pc)	         /* r15 */
 	},
 
 	/* SVC Registers */
@@ -60,9 +62,9 @@ static const unsigned long vcpu_reg_offsets[MODE_SYS + 1][16] = {
 		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
 		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
 		USR_REG_OFFSET(12),
-		offsetof(struct kvm_vcpu_arch, regs.svc_regs[0]), /* r13 */
-		offsetof(struct kvm_vcpu_arch, regs.svc_regs[1]), /* r14 */
-		offsetof(struct kvm_vcpu_arch, regs.pc)		  /* r15 */
+		REG_OFFSET(svc_regs[0]), /* r13 */
+		REG_OFFSET(svc_regs[1]), /* r14 */
+		REG_OFFSET(pc)		 /* r15 */
 	},
 
 	/* ABT Registers */
@@ -72,9 +74,9 @@ static const unsigned long vcpu_reg_offsets[MODE_SYS + 1][16] = {
 		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
 		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
 		USR_REG_OFFSET(12),
-		offsetof(struct kvm_vcpu_arch, regs.abt_regs[0]), /* r13 */
-		offsetof(struct kvm_vcpu_arch, regs.abt_regs[1]), /* r14 */
-		offsetof(struct kvm_vcpu_arch, regs.pc)	          /* r15 */
+		REG_OFFSET(abt_regs[0]), /* r13 */
+		REG_OFFSET(abt_regs[1]), /* r14 */
+		REG_OFFSET(pc)	         /* r15 */
 	},
 
 	/* UND Registers */
@@ -84,9 +86,9 @@ static const unsigned long vcpu_reg_offsets[MODE_SYS + 1][16] = {
 		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
 		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
 		USR_REG_OFFSET(12),
-		offsetof(struct kvm_vcpu_arch, regs.und_regs[0]), /* r13 */
-		offsetof(struct kvm_vcpu_arch, regs.und_regs[1]), /* r14 */
-		offsetof(struct kvm_vcpu_arch, regs.pc)	          /* r15 */
+		REG_OFFSET(und_regs[0]), /* r13 */
+		REG_OFFSET(und_regs[1]), /* r14 */
+		REG_OFFSET(pc)	         /* r15 */
 	},
 
 	/* USR Registers */
@@ -96,9 +98,9 @@ static const unsigned long vcpu_reg_offsets[MODE_SYS + 1][16] = {
 		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
 		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
 		USR_REG_OFFSET(12),
-		offsetof(struct kvm_vcpu_arch, regs.usr_regs[13]), /* r13 */
-		offsetof(struct kvm_vcpu_arch, regs.usr_regs[14]), /* r14 */
-		offsetof(struct kvm_vcpu_arch, regs.pc)	           /* r15 */
+		REG_OFFSET(usr_regs[13]), /* r13 */
+		REG_OFFSET(usr_regs[14]), /* r14 */
+		REG_OFFSET(pc)	          /* r15 */
 	},
 
 	/* SYS Registers */
@@ -108,9 +110,9 @@ static const unsigned long vcpu_reg_offsets[MODE_SYS + 1][16] = {
 		USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
 		USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
 		USR_REG_OFFSET(12),
-		offsetof(struct kvm_vcpu_arch, regs.usr_regs[13]), /* r13 */
-		offsetof(struct kvm_vcpu_arch, regs.usr_regs[14]), /* r14 */
-		offsetof(struct kvm_vcpu_arch, regs.pc)	           /* r15 */
+		REG_OFFSET(usr_regs[13]), /* r13 */
+		REG_OFFSET(usr_regs[14]), /* r14 */
+		REG_OFFSET(pc)	          /* r15 */
 	},
 };
 
@@ -123,7 +125,7 @@ u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode)
 	BUG_ON(reg_num > 15);
 	BUG_ON(mode > MODE_SYS);
 
-	return (u32 *)((void *)&vcpu->arch + vcpu_reg_offsets[mode][reg_num]);
+	return &vcpu->arch.reg_array[vcpu_reg_offsets[mode][reg_num]];
 }
 
 /******************************************************************************



From b39297 at freescale.com  Thu Mar  8 23:35:24 2012
From: b39297 at freescale.com (Wu Guoxing)
Date: Fri, 9 Mar 2012 12:35:24 +0800
Subject: [PATCH v4] ARM : mx35: 3ds-board: add framebuffer device
Message-ID: <1331267724-16432-1-git-send-email-b39297@freescale.com>

From: wu guoxing <b39297 at freescale.com>

This patch adds framebuffer support for freescale mx35 3ds board

Signed-off-by: Wu Guoxing <b39297 at freescale.com>
---
Changes since v3:
        1. use a static variable to save the gpio value instead of find
	   the gpiochip every time.
	2. add gpio_request after found the gpio.
Changes since v2:
	1. use gpio_set_value_cansleep instead of gpio_set_value Changes
Changes since v1:
	1. use gpio driver for mc9s08dz60

 arch/arm/mach-imx/mach-mx35_3ds.c |  121 +++++++++++++++++++++++++++++++++++++
 1 files changed, 121 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c..d1fb466 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -40,9 +40,94 @@
 #include <mach/iomux-mx35.h>
 #include <mach/irqs.h>
 #include <mach/3ds_debugboard.h>
+#include <video/platform_lcd.h>
 
 #include "devices-imx35.h"
 
+static const struct fb_videomode fb_modedb[] = {
+	{
+		 /* 800x480 @ 55 Hz */
+		 .name = "Ceramate-CLAA070VC01",
+		 .refresh = 55,
+		 .xres = 800,
+		 .yres = 480,
+		 .pixclock = 40000,
+		 .left_margin = 40,
+		 .right_margin = 40,
+		 .upper_margin = 5,
+		 .lower_margin = 5,
+		 .hsync_len = 20,
+		 .vsync_len = 10,
+		 .sync = FB_SYNC_OE_ACT_HIGH,
+		 .vmode = FB_VMODE_NONINTERLACED,
+		 .flag = 0,
+	 },
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+	.irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+	.name = "Ceramate-CLAA070VC01",
+	.mode = fb_modedb,
+	.num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static struct i2c_board_info __initdata i2c_devices_3ds[] = {
+	{
+		I2C_BOARD_INFO("mc9s08dz60", 0x69),
+	},
+};
+
+static int lcd_power_gpio = -ENXIO;
+
+static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
+						     void *data)
+{
+	return !strcmp(chip->label, data);
+}
+
+static int mc9s08dz60_lcd_gpio_get(void)
+{
+	struct gpio_chip *chip;
+
+	if (!gpio_is_valid(lcd_power_gpio)) {
+		chip = gpiochip_find(
+				"mc9s08dz60", mc9s08dz60_gpiochip_match);
+		if (chip) {
+			lcd_power_gpio = chip->base + 6;
+			if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
+				pr_err("error: gpio already requested by other!\n");
+				lcd_power_gpio = -ENXIO;
+			}
+		} else {
+			pr_err("error: didn't find mc9s08dz60 gpio chip\n");
+			lcd_power_gpio = -ENXIO;
+		}
+	}
+
+	return lcd_power_gpio;
+}
+
+static void mx35_3ds_lcd_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+	int gpio;
+
+	gpio = mc9s08dz60_lcd_gpio_get();
+	if (gpio_is_valid(lcd_power_gpio))
+		gpio_set_value_cansleep(gpio, power);
+}
+
+static struct plat_lcd_data mx35_3ds_lcd_data = {
+	.set_power = mx35_3ds_lcd_set_power,
+};
+
+static struct platform_device mx35_3ds_lcd = {
+	.name = "platform-lcd",
+	.dev.platform_data = &mx35_3ds_lcd_data,
+};
+
 #define EXPIO_PARENT_INT	gpio_to_irq(IMX_GPIO_NR(1, 1))
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -120,6 +205,32 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
 	/* I2C1 */
 	MX35_PAD_I2C1_CLK__I2C1_SCL,
 	MX35_PAD_I2C1_DAT__I2C1_SDA,
+	/* Display */
+	MX35_PAD_LD0__IPU_DISPB_DAT_0,
+	MX35_PAD_LD1__IPU_DISPB_DAT_1,
+	MX35_PAD_LD2__IPU_DISPB_DAT_2,
+	MX35_PAD_LD3__IPU_DISPB_DAT_3,
+	MX35_PAD_LD4__IPU_DISPB_DAT_4,
+	MX35_PAD_LD5__IPU_DISPB_DAT_5,
+	MX35_PAD_LD6__IPU_DISPB_DAT_6,
+	MX35_PAD_LD7__IPU_DISPB_DAT_7,
+	MX35_PAD_LD8__IPU_DISPB_DAT_8,
+	MX35_PAD_LD9__IPU_DISPB_DAT_9,
+	MX35_PAD_LD10__IPU_DISPB_DAT_10,
+	MX35_PAD_LD11__IPU_DISPB_DAT_11,
+	MX35_PAD_LD12__IPU_DISPB_DAT_12,
+	MX35_PAD_LD13__IPU_DISPB_DAT_13,
+	MX35_PAD_LD14__IPU_DISPB_DAT_14,
+	MX35_PAD_LD15__IPU_DISPB_DAT_15,
+	MX35_PAD_LD16__IPU_DISPB_DAT_16,
+	MX35_PAD_LD17__IPU_DISPB_DAT_17,
+	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
+	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
 };
 
 static int mx35_3ds_otg_init(struct platform_device *pdev)
@@ -179,6 +290,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
  */
 static void __init mx35_3ds_init(void)
 {
+	struct platform_device *imx35_fb_pdev;
+
 	imx35_soc_init();
 
 	mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
@@ -204,6 +317,14 @@ static void __init mx35_3ds_init(void)
 		pr_warn("Init of the debugboard failed, all "
 				"devices on the debugboard are unusable.\n");
 	imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+
+	i2c_register_board_info(
+		0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
+
+	imx35_add_ipu_core(&mx3_ipu_data);
+	imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
+	mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
+	platform_device_register(&mx35_3ds_lcd);
 }
 
 static void __init mx35pdk_timer_init(void)
-- 
1.7.1




From B04825 at freescale.com  Thu Mar  8 23:03:19 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Fri, 9 Mar 2012 04:03:19 +0000
Subject: [PATCH v3 08/11] ASoC: fsl: make fsl_ssi driver compilable on
 ARM/IMX
In-Reply-To: <20120309032128.GK2499@S2101-09.ap.freescale.net>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-9-git-send-email-shawn.guo@linaro.org>
 <4F5912D0.2090800@freescale.com>
 <20120309012653.GG2499@S2101-09.ap.freescale.net>
 <4F596674.5030405@freescale.com>
 <20120309032128.GK2499@S2101-09.ap.freescale.net>
Message-ID: <4F598106.30300@freescale.com>

Shawn Guo wrote:
> On Fri, Mar 09, 2012 at 02:09:57AM +0000, Tabi Timur-B04825 wrote:
>> >  That's the general idea, but I think it needs more study.  I don't
>> >  consider this to be a bug that needs to be fixed ASAP, since it's never
>> >  been an actual problem so far.  For instance, do we need to protect
>> >  between hw_params and _trigger?
>> >
> Ok, I will leave it to you with a big "FIXME" comment then.

Ok.

-- 
Timur Tabi
Linux kernel developer at Freescale


From arnd at arndb.de  Sun Mar 11 17:34:44 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 11 Mar 2012 21:34:44 +0000
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <1331500100-31351-4-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-4-git-send-email-robherring2@gmail.com>
Message-ID: <201203112134.45302.arnd@arndb.de>

On Sunday 11 March 2012, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> Several platforms create IOMEM defines for casting to 'void __iomem *',
> and other platforms are incorrectly using __io() macro for the same
> purpose. This creates a common definition and removes all the platform
> specific versions. Rather than try to make linux/io.h and asm/io.h
> assembly safe, the assembly version of IOMEM is moved into
> asm/assembler.h.

Looks good to me, in order to fix the problem at hand. I'm not sure
about spreading the IOMEM() macro further, that is largely a separate
problem and only a question of style, not of correctness as with __io().

Acked-by: Arnd Bergmann <arnd at arndb.de>


From t-kristo at ti.com  Mon Mar 12 06:00:27 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Mon, 12 Mar 2012 12:00:27 +0200
Subject: [PATCHv5 0/6] ARM: OMAP3+: IO daisy chain support fixes
In-Reply-To: <alpine.DEB.2.00.1203092102450.30879@utopia.booyaka.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203092102450.30879@utopia.booyaka.com>
Message-ID: <1331546427.2116.264.camel@sokoban>

On Fri, 2012-03-09 at 21:05 -0700, Paul Walmsley wrote:
> Hi
> 
> On Tue, 6 Mar 2012, Tero Kristo wrote:
> 
> > Changes compared to previous version:
> > 
> > - patch2:
> >   * fixed the timeout for waiting for ST_IO_CHAIN == 1
> >   * added clear for ST_IO_CHAIN bit (as per spec + implementation in patch 1)
> >   * replaced the timeout at the end of function with a simple register
> >     readback (timing out on a register value that we are clearing does
> >     not make that much sense, the bit is cleared the very first time CPU
> >     manages to read it)
> > - patch5:
> >   * added spinlock for protecting io_chain_trigger operation
> > 
> > Tested on omap3 beagle + omap4 blaze. Also did measurements for the
> > cost of IO chain trigger operation with ARM performance counters:
> > 
> > - omap3 approx 7...8us
> > - omap4 approx 2...4us
> 
> Thanks for the changes.  So as you probably already saw, a few changes 
> have been made.  The updated series is in the branch 
> 'io_chain_devel_3.4' on git://git.pwsan.com/linux-2.6.
> 
> The main outstanding question is whether the OMAP4 WUCLKOUT poll should be 
> removed to match the v5 changes to the OMAP3 function.  Please let me 
> know.   Any other testing or comments are of course welcome.

Just tested your branch with omap3 beagle + omap4 blaze (with my omap4
cswr set on top), and it works on both.

For the WUCLK poll bit I added detailed comments on patch 2 thread, but
my current understanding is that the implementation now on omap3 / omap4
is what they should be due to IP differences (except maybe the small
optimization for omap3 part you commented about.)

-Tero



From arnd at arndb.de  Sun Mar 11 13:46:09 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 11 Mar 2012 17:46:09 +0000
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <1331476406-9844-2-git-send-email-jm@lentin.co.uk>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <1331476406-9844-2-git-send-email-jm@lentin.co.uk>
Message-ID: <201203111746.09757.arnd@arndb.de>

On Sunday 11 March 2012, Jamie Lentin wrote:
> Add support for the DNS-320 and DNS-325. Describe as much as currently possible
> in the devicetree files, leave everything else in board-dt.c to be patched
> later.
> 
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>

Great work!

> +
> +/ {
> +	model = "D-Link DNS-320 NAS (Rev A1)";
> +	compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x8000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200n8 earlyprintk";
> +	};
> +
> +	wdt at fed20300 {
> +		compatible = "mrvl,orion-wdt";
> +		reg = <0xfed20300 0x28>;
> +		clock-frequency = <166666667>;
> +	};
> +
> +	serial at f1012000 {
> +		compatible = "ns16550a";
> +		reg = <0xf1012000 0xff>;
> +		reg-shift = <2>;
> +		interrupts = <33>;
> +		clock-frequency = <166666667>;
> +	};
> +
> +	serial at f1012100 {
> +		compatible = "ns16550a";
> +		reg = <0xf1012100 0xff>;
> +		reg-shift = <2>;
> +		interrupts = <34>;
> +		clock-frequency = <166666667>;
> +	};

I think the generic kirkwood device nodes should all be part of
the kirkwood.dtsi file, except for any properties you want to
override.

You can add a status="disabled" property in device nodes
that may not be connected in individual boards, and then
just override it by listing status="enabled" in the board.dts
file, without having to duplicate all the other properties.

I would also suggest to change the kirkwood.dtsi layout to
put all the on-chip peripherals from the 0xf1 section into
one bus in the device tree, like

	ocp at f1000000 {
		compatible = "simple-bus";
		ranges = <0xf1000000 0xf1000000 0x1000000>;
		#address-cells = 1;
		#size-cells = 1;

		serial at f1012000 {
			...
		};

		...
	};

Or even use the ranges property to remap everything into
a simpler address range:

	ocp at f1000000 {
		compatible = "simple-bus";
		ranges = <0 0xf1000000 0x1000000>;
		#address-cells = 1;
		#size-cells = 1;

		serial at 12000 {
			reg = <0x12000 0x100>;
			...
		};

		...
	};


	Arnd


From w.sang at pengutronix.de  Mon Mar 12 07:06:24 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Mon, 12 Mar 2012 12:06:24 +0100
Subject: iMX53 and MMC_CAP_SDIO_IRQ
In-Reply-To: <4F5DD28F.50600@linuxtv.org>
References: <4F5DB793.3080904@linuxtv.org>
 <20120312101037.GA2459@pengutronix.de> <4F5DD28F.50600@linuxtv.org>
Message-ID: <20120312110624.GB2459@pengutronix.de>


> Ok, to sum this up:
> 
> SDIO IRQs are working in mx_sdhci in the Freescale tree because it was
> properly implemented and tested, obviously.

Not sure about "properly", but, yes ;)

> SDIO IRQs are working for sdhci in mainline probably for other
> non-freescale platforms.

Probably, but I can't say 'yes' for sure. You'd need to find out.

> You fixed the generic sdhci driver in mainline to work with iMX53 to get
> rid of the need for mx_sdhci, but probably never got the chance to test
> if SDIO IRQs are really working.

I worked mainly with MX25/35 back then, and a little bit with MX51. IIRC
I only had an SDIO card for which no Linux drivers were available, so I
only could test that the card was detected :(

> That means, the subtle difference between mx_sdhci and sdhci to get SDIO
> IRQS to work on sdhci with iMX53 has yet to be found.

Yup. Try 'git log --follow sdhci-esdhc-imx.c' to find people who worked
with MX53 or SDIO using that driver.

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From lost.distance at yahoo.com  Sat Mar 10 10:11:10 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Sat, 10 Mar 2012 15:11:10 +0000 (GMT)
Subject: [PATCH v2] pxa/hx4700: Fix basic suspend/resume
In-Reply-To: <CA+gwMccn+rLo2Q+z+gxboE82pmGT0ud2c1Q65PzhrGhFXLrvgw@mail.gmail.com>
Message-ID: <1331392270.97238.YahooMailClassic@web29005.mail.ird.yahoo.com>

Hi Philipp,

--- On Fri, 9/3/12, Philipp Zabel <philipp.zabel at gmail.com> wrote:
> > Changed GPIO88, GPIO72, GPIO96 from KEEP_OUTPUT to
> DRIVE_HIGH.
> 
> The bq24022 GPIOs (72 and 96) should stay KEEP_OUTPUT to
> allow
> charging from the AC adapter while suspended.

I think I disabled this because I was wary of uncontrolled charging while
suspended. The SDG bootloader does have specific code to control charging
and the LEDs while suspended, but AFAIK it is not currently working.

Nonetheless, I've modified the patch.

Interestingly, the SDG bootloader seems to use LED interrupts to
periodically wake up during suspend. At last, that would explain why the
LED GPIOs are inputs, not outputs.

Paul


From nsekhar at ti.com  Sun Mar 11 03:36:55 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Sun, 11 Mar 2012 07:36:55 +0000
Subject: [GIT PULL v2] DaVinci DM644x video display support
Message-ID: <DF0F476B391FA8409C78302C7BA518B6317F13DB@DBDE01.ent.ti.com>

Hi Arnd, Olof,

Can you please pull these two patches adding support
for DaVinci DM644x V4L2 display support for v3.4.

These patches heavily depend on the clean-up series sent
earlier. I have re-generated the pull request against
v3.4/cleanup branch of my tree (already pulled earlier
and unchanged since) as suggested by Olof.

Let me know if this works for you.

Thanks,
Sekhar

The following changes since commit 12db9588ff811ae43a476b1234b27323055ab3ad:
  Manjunath Hadli (1):
        ARM: davinci: dm644x: don't force vpfe registeration on all boards

are available in the git repository at:

  git://gitorious.org/linux-davinci/linux-davinci.git v3.4/features

Manjunath Hadli (2):
      ARM: davinci: dm644x: add support for v4l2 video display
      ARM: davinci: dm644x evm: add support for VPBE display

 arch/arm/mach-davinci/board-dm644x-evm.c |  109 +++++++++++++++++++-
 arch/arm/mach-davinci/davinci.h          |    8 ++-
 arch/arm/mach-davinci/dm644x.c           |  166 +++++++++++++++++++++++++++---
 3 files changed, 268 insertions(+), 15 deletions(-)


From linux at arm.linux.org.uk  Mon Mar 12 06:11:00 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 12 Mar 2012 10:11:00 +0000
Subject: [PATCH] serial: PL011: clear pending interrupts
In-Reply-To: <20120312083221.GW17370@n2100.arm.linux.org.uk>
References: <1331540750-25697-1-git-send-email-linus.walleij@stericsson.com>
 <20120312083221.GW17370@n2100.arm.linux.org.uk>
Message-ID: <20120312101100.GA8649@n2100.arm.linux.org.uk>

On Mon, Mar 12, 2012 at 08:32:21AM +0000, Russell King - ARM Linux wrote:
> On Mon, Mar 12, 2012 at 09:25:50AM +0100, Linus Walleij wrote:
> > diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
> > index 6800f5f..ff3fed0 100644
> > --- a/drivers/tty/serial/amba-pl011.c
> > +++ b/drivers/tty/serial/amba-pl011.c
> > @@ -224,6 +224,11 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap)
> >  		uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
> >  	}
> >  
> 
> What if we really do end up receiving some characters here?
> 
> > +	/* RXIS but RXFE? Just clear the interrupt */
> > +	if(unlikely(fifotaken == 0))
> > +		writew(UART011_RTIS | UART011_RXIS,
> > +		       uap->port.membase + UART011_ICR);

BTW, I don't see why we need any of this stuff.

The problem as described is that the interrupt handler is called with one
of the receive flags set (UART011_RTIS or UART011_RXIS) but with
UART01x_FR_RXFE clear.

The problem report indicates that this is caused when we switch from FIFO
mode to non-FIFO mode, and the FIFO contained some unread characters.

That can only happen once we've enabled interrupts in the IMSC register,
which doesn't happen until later in the startup function.

So:

        spin_lock_irq(&uap->port.lock);
        uap->im = UART011_RTIM;
        if (!pl011_dma_rx_running(uap))
                uap->im |= UART011_RXIM;
        writew(uap->im, uap->port.membase + UART011_IMSC);
        spin_unlock_irq(&uap->port.lock);

clearing the transmit/receive interrupts here _before_ we unmask them
should be sufficient.

As we never turn the FIFO off after that point, we can't then cause the
condition.  So I don't see any point in adding stuff to the interrupt
handling for this.



From govindraj.raja at ti.com  Mon Mar 12 07:49:07 2012
From: govindraj.raja at ti.com (Raja, Govindraj)
Date: Mon, 12 Mar 2012 17:19:07 +0530
Subject: [PATCH] omap_hwmod: Allow io_ring wakeup configuration for all
 modules.
In-Reply-To: <CAMrsUdJq8J8dTnKcZmXgMucDX=dNXgR+9xFhYOdHvNDuw_=4Mw@mail.gmail.com>
References: <1331122775-761-1-git-send-email-govindraj.raja@ti.com>
 <CAMrsUdJq8J8dTnKcZmXgMucDX=dNXgR+9xFhYOdHvNDuw_=4Mw@mail.gmail.com>
Message-ID: <CAMrsUdLe1gq-tWeg_GgEp_HHUVXCGMgegCtfEzEp9zzMpbDfHA@mail.gmail.com>

On Wed, Mar 7, 2012 at 7:40 PM, Raja, Govindraj <govindraj.raja at ti.com> wrote:
> On Wed, Mar 7, 2012 at 5:49 PM, Govindraj.R <govindraj.raja at ti.com> wrote:
>>

[...]

>
> From b3aa1dac5909cad1b959f5b97bbf408b2f974060 Mon Sep 17 00:00:00 2001
> From: "Govindraj.R" <govindraj.raja at ti.com>
> Date: Wed, 7 Mar 2012 17:14:02 +0530
> Subject: [PATCH] omap_hwmod: Allow io_ring wakeup configuration for all
> ?modules.
>
> Some modules doesn't have SYSC_HAS_ENAWAKEUP bit available
> (ex: usb host uhh module) in absence of this flag
> omap_hwmod_enable/disable_wakeup avoids configuring
> pad mux wakeup capability.
>
> Configure sysc if SYSC_HAS_ENAWAKEUP is available and for other cases
> try enabling/disabling wakeup from mux_pad pins.
>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
> ---

Gentle Ping.

--
Thanks,
Govindraj.R



> ?arch/arm/mach-omap2/omap_hwmod.c | ? 30 ++++++++++++++++--------------
> ?1 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index eba6cd3..9605fad 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -2475,14 +2475,15 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
> ? ? ? ?unsigned long flags;
> ? ? ? ?u32 v;
>
> - ? ? ? if (!oh->class->sysc ||
> - ? ? ? ? ? !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
> - ? ? ? ? ? ? ? return -EINVAL;
> -
> ? ? ? ?spin_lock_irqsave(&oh->_lock, flags);
> - ? ? ? v = oh->_sysc_cache;
> - ? ? ? _enable_wakeup(oh, &v);
> - ? ? ? _write_sysconfig(v, oh);
> +
> + ? ? ? if (oh->class->sysc &&
> + ? ? ? ? ? (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
> + ? ? ? ? ? ? ? v = oh->_sysc_cache;
> + ? ? ? ? ? ? ? _enable_wakeup(oh, &v);
> + ? ? ? ? ? ? ? _write_sysconfig(v, oh);
> + ? ? ? }
> +
> ? ? ? ?_set_idle_ioring_wakeup(oh, true);
> ? ? ? ?spin_unlock_irqrestore(&oh->_lock, flags);
>
> @@ -2506,14 +2507,15 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
> ? ? ? ?unsigned long flags;
> ? ? ? ?u32 v;
>
> - ? ? ? if (!oh->class->sysc ||
> - ? ? ? ? ? !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
> - ? ? ? ? ? ? ? return -EINVAL;
> -
> ? ? ? ?spin_lock_irqsave(&oh->_lock, flags);
> - ? ? ? v = oh->_sysc_cache;
> - ? ? ? _disable_wakeup(oh, &v);
> - ? ? ? _write_sysconfig(v, oh);
> +
> + ? ? ? if (oh->class->sysc &&
> + ? ? ? ? ? (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
> + ? ? ? ? ? ? ? v = oh->_sysc_cache;
> + ? ? ? ? ? ? ? _disable_wakeup(oh, &v);
> + ? ? ? ? ? ? ? _write_sysconfig(v, oh);
> + ? ? ? }
> +
> ? ? ? ?_set_idle_ioring_wakeup(oh, false);
> ? ? ? ?spin_unlock_irqrestore(&oh->_lock, flags);
>
> --
> 1.7.5.4


From u.kleine-koenig at pengutronix.de  Sun Mar 11 05:33:21 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Sun, 11 Mar 2012 10:33:21 +0100
Subject: [PATCH v2 1/3] mfd: mc13xxx-core: Prepare for separate spi and
 i2c backends.
In-Reply-To: <1331429402-9639-2-git-send-email-marc@cpdesign.com.au>
References: <1331429402-9639-1-git-send-email-marc@cpdesign.com.au>
 <1331429402-9639-2-git-send-email-marc@cpdesign.com.au>
Message-ID: <20120311093321.GK14173@pengutronix.de>

On Sun, Mar 11, 2012 at 12:30:00PM +1100, Marc Reilly wrote:
> This patch abstracts the bus specific operations from the driver core.
> Read and write handlers are introduced and generic initialization is
> consolidated into mc13xxx_comon_init. The irq member is removed because
s/_comon_/_common_/

one minor nitpick below.

> it is unused.
> 
> Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
> ---
>  drivers/mfd/mc13xxx-core.c |  162 ++++++++++++++++++++++++++------------------
>  1 files changed, 97 insertions(+), 65 deletions(-)
> 
> diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
> index 7122386..19d94a1 100644
> --- a/drivers/mfd/mc13xxx-core.c
> +++ b/drivers/mfd/mc13xxx-core.c
> @@ -235,6 +234,34 @@ int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
>  
>  	return 0;
>  }
> +
> +int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
> +{
> +	int ret;
> +
> +	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
> +
> +	if (offset > MC13XXX_NUMREGS)
> +		return -EINVAL;
> +
> +	ret = mc13xxx->read_dev(mc13xxx, offset, val);
> +	dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL(mc13xxx_reg_read);
> +
> +int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
> +{
> +	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
> +
> +	dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
> +
> +	if (offset > MC13XXX_NUMREGS || val > 0xffffff)
> +		return -EINVAL;
> +
> +	return mc13xxx->write_dev(mc13xxx, offset, val);
> +}
>  EXPORT_SYMBOL(mc13xxx_reg_write);
>  
>  int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
> @@ -439,7 +466,7 @@ static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
>  			if (handled == IRQ_HANDLED)
>  				num_handled++;
>  		} else {
> -			dev_err(&mc13xxx->spidev->dev,
> +			dev_err(mc13xxx->dev,
>  					"BUG: irq %u but no handler\n",
Without having counted I think you can join these two lines.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From s.hauer at pengutronix.de  Sun Mar 11 07:34:14 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sun, 11 Mar 2012 12:34:14 +0100
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <1331366064-1273-3-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
Message-ID: <20120311113414.GM3852@pengutronix.de>

Hi Mike,

I was about to give my tested-by when I decided to test the set_rate
function. Unfortunately this is broken for several reasons. I'll try
to come up with a fixup series later the day.

On Fri, Mar 09, 2012 at 11:54:23PM -0800, Mike Turquette wrote:
> +
> +/**
> + * DOC: Using the CLK_SET_RATE_PARENT flag
> + *
> + * __clk_set_rate changes the child's rate before the parent's to more
> + * easily handle failure conditions.
> + *
> + * This means clk might run out of spec for a short time if its rate is
> + * increased before the parent's rate is updated.
> + *
> + * To prevent this consider setting the CLK_SET_RATE_GATE flag on any
> + * clk where you also set the CLK_SET_RATE_PARENT flag
> + *
> + * PRE_RATE_CHANGE notifications are supposed to stack as a rate change
> + * request propagates up the clk tree.  This reflects the different
> + * rates that a downstream clk might experience if left enabled while
> + * upstream parents change their rates.
> + */
> +static struct clk *__clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	struct clk *fail_clk = NULL;
> +	int ret = NOTIFY_DONE;
> +	unsigned long old_rate = clk->rate;
> +	unsigned long new_rate;
> +	unsigned long parent_old_rate;
> +	unsigned long parent_new_rate = 0;
> +	struct clk *child;
> +	struct hlist_node *tmp;
> +
> +	/* bail early if we can't change rate while clk is enabled */
> +	if ((clk->flags & CLK_SET_RATE_GATE) && clk->enable_count)
> +		return clk;
> +
> +	/* find the new rate and see if parent rate should change too */
> +	WARN_ON(!clk->ops->round_rate);
> +
> +	new_rate = clk->ops->round_rate(clk->hw, rate, &parent_new_rate);

You don't need a WARN_ON when you derefence clk->ops->round_rate anyway.
Also, even when the current clock does not have a set_rate function it
can still change its rate when the CLK_SET_RATE_PARENT is set.

> +
> +	/* NOTE: pre-rate change notifications will stack */
> +	if (clk->notifier_count)
> +		ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
> +
> +	if (ret == NOTIFY_BAD)
> +		return clk;
> +
> +	/* speculate rate changes down the tree */
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
> +		ret = __clk_speculate_rates(child, new_rate);
> +		if (ret == NOTIFY_BAD)
> +			return clk;
> +	}
> +
> +	/* change the rate of this clk */
> +	if (clk->ops->set_rate)
> +		ret = clk->ops->set_rate(clk->hw, new_rate);

I don't know the reason why you change the child clock before the parent
clock, but it cannot work since this clock will change its rate based on
the old parent rate and not the new one.

There are more things, as said I'll try to come up with a fixup series.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From grant.likely at secretlab.ca  Fri Mar  9 00:46:08 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 08 Mar 2012 22:46:08 -0700
Subject: [PATCH v2 4/4] arm/dts: OMAP3: Add mmc controller nodes and board
 data
In-Reply-To: <20120224184859.GN18185@atomide.com>
References: <1329998490-27555-1-git-send-email-rnayak@ti.com>
 <1329998490-27555-5-git-send-email-rnayak@ti.com>
 <20120223185718.GZ18185@atomide.com> <4F470B71.1020308@ti.com>
 <20120224184859.GN18185@atomide.com>
Message-ID: <20120309054608.647473E0901@localhost>

On Fri, 24 Feb 2012 10:49:00 -0800, Tony Lindgren <tony at atomide.com> wrote:
> * Rajendra Nayak <rnayak at ti.com> [120223 19:29]:
> > On Friday 24 February 2012 12:27 AM, Tony Lindgren wrote:
> > >>--- a/arch/arm/boot/dts/omap3.dtsi
> > >>+++ b/arch/arm/boot/dts/omap3.dtsi
> > >>@@ -113,5 +113,31 @@
> > >>  			#size-cells =<0>;
> > >>  			ti,hwmods = "i2c3";
> > >>  		};
> > >>+
> > >>+		mmc1: mmc at 1 {
> > >>+			compatible = "ti,omap2-hsmmc";
> > >>+			ti,hwmods = "mmc1";
> > >>+			ti,dual-volt;
> > >>+		};
> > >>+
> > >>+		mmc2: mmc at 2 {
> > >>+			compatible = "ti,omap2-hsmmc";
> > >>+			ti,hwmods = "mmc2";
> > >>+		};
> > >>+
> > >>+		mmc3: mmc at 3 {
> > >>+			compatible = "ti,omap2-hsmmc";
> > >>+			ti,hwmods = "mmc3";
> > >>+		};
> > >>+
> > >>+		mmc4: mmc at 4 {
> > >>+			compatible = "ti,omap2-hsmmc";
> > >>+			ti,hwmods = "mmc4";
> > >>+		};
> > >>+
> > >>+		mmc5: mmc at 5 {
> > >>+			compatible = "ti,omap2-hsmmc";
> > >>+			ti,hwmods = "mmc5";
> > >>+		};
> > >>  	};
> > >>  };
> > >
> > >These all should all be "ti,omap3-hsmmc" I guess?
> > 
> > Well, I defined the binding such that both omap2 and omap3
> > can use the same compatible "ti,omap2-hsmmc" since there is
> > no difference in the way they are defined or handled. If thats
> > confusing, I can have separate compatibles.
> > Btw, I guess we do the same with a few other re-used IPs as well,
> > I just checked and mcpsi does the same.
> 
> Yeah let's use separate compatibles to avoid confusion.
> For omap2 we also have the ti,omap2-mmc in addition to
> ti,omap2-hsmmc..

Yes, absolutely use separate compatible values.  It is always important
to be specific as to the silicon implementing the IP.  The omap3 instance
can also carry the omap2 string in its compatible list:

	compatible = "ti,omap3-hsmmc", "ti,omap2-hsmmc";

g.


From festevam at gmail.com  Mon Mar 12 09:24:35 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 12 Mar 2012 10:24:35 -0300
Subject: I.MX35 PDK
In-Reply-To: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A29@MEP-EXCH.meprolight.com>
References: <CAOMZO5DnP7+zupy9vwBPS0+2XtKM1+nLbwCqBzuCqEG5OWbZRQ@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A28@MEP-EXCH.meprolight.com>
 <CAOMZO5Amo0XFf+TV7PprCL079C5Y0qKmo+k-FfShU7k4SG7W6Q@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8913@MEP-EXCH.meprolight.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD5D8918@MEP-EXCH.meprolight.com>
 <CAOMZO5A6T+WdOE41Wx6Nctwz9wk8FKaxzjbAt_woZkCnuodNYg@mail.gmail.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A29@MEP-EXCH.meprolight.com>
Message-ID: <CAOMZO5B_mZ16zvXdNbKP_PWM5axNPzMeHQttxe8PYHET7UMufg@mail.gmail.com>

On 3/12/12, Alex Gershgorin <alexg at meprolight.com> wrote:

> 1. Back resistor 172 to the default value.
>
> 2. Removed the resistor 146, through which a voltage was applied from a PMIC
> (EXT_3V) on "CMOS_VIO".
>
> 3. Connecting a resistor 147 which supplies power from the LDO_3V3 on
> "CMOS_VIO".

The camera on the FSL BSP works fine with no hardware modification on
the mx35pdk.

As I suggested previously you should control the power rails, i2c pad
settings, etc from software so that the camera can also work in
mainline without the need of changing the hardware.

> On my display I see snow flickering and unfortunately not a live video from
> camera.

Do you have this patch applied?

http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commitdiff;h=f910fb8fcd1c97788f2291c8646597bcd87ee061

Also, try to isolate the display from this issue. Capture the image to
a file and try to play it on a PC.

Regards,

Fabio Estevam


From neidhard.kim at lge.com  Mon Mar 12 07:22:07 2012
From: neidhard.kim at lge.com (Kim, Jong-Sung)
Date: Mon, 12 Mar 2012 20:22:07 +0900
Subject: [PATCH] serial: PL011: clear pending interrupts
In-Reply-To: <20120312083221.GW17370@n2100.arm.linux.org.uk>
References: <1331540750-25697-1-git-send-email-linus.walleij@stericsson.com>
 <20120312083221.GW17370@n2100.arm.linux.org.uk>
Message-ID: <01e101cd0042$5bf692a0$13e3b7e0$@lge.com>

> > diff --git a/drivers/tty/serial/amba-pl011.c
> > b/drivers/tty/serial/amba-pl011.c index 6800f5f..ff3fed0 100644
> > --- a/drivers/tty/serial/amba-pl011.c
> > +++ b/drivers/tty/serial/amba-pl011.c
> > @@ -224,6 +224,11 @@ static int pl011_fifo_to_tty(struct uart_amba_port
> *uap)
> >  		uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
> >  	}
> >
> 
> What if we really do end up receiving some characters here?

Maybe the character is handled on next upcoming RTIS or RXIS in normal.
However, I agree with you there is possibility of already asserted RXIS at
this point. (with debugger?) In such a case, we may lose Rx interrupts
forever because it's not level-triggered, and the ISR lacks error interrupt
handling. Correct me if something wrong.
Thank you for your comment, Russell.

> 
> > +	/* RXIS but RXFE? Just clear the interrupt */
> > +	if(unlikely(fifotaken == 0))
> > +		writew(UART011_RTIS | UART011_RXIS,
> > +		       uap->port.membase + UART011_ICR);



From olof at lixom.net  Sat Mar 10 11:30:18 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 10 Mar 2012 08:30:18 -0800
Subject: [GIT PULL] DaVinci DM644x video display support
In-Reply-To: <DF0F476B391FA8409C78302C7BA518B6317EEB34@DBDE01.ent.ti.com>
References: <DF0F476B391FA8409C78302C7BA518B6317EEB34@DBDE01.ent.ti.com>
Message-ID: <CAOesGMhcowDuD9FDUG8cMy-a7s-43Ch-=WWjNvrmCtS6+3=t6g@mail.gmail.com>

Hi,

On Thu, Mar 8, 2012 at 11:23 AM, Nori, Sekhar <nsekhar at ti.com> wrote:
> Hi Arnd, Olof,
>
> Can you please pull these two patches adding support
> for DaVinci DM644x V4L2 display support for v3.4.
>
> These patches heavily depend on the clean-up series sent earlier.
> Since the clean-up series is already included in for-next branch
> of arm-soc, I have generated a request using that as baseline.
>
> Let me know if that's not desirable, and I can do it any
> other way you want.
>
> Thanks,
> Sekhar
>
> The following changes since commit 3a034af7c1a3c55014eeb15a9c9430e9f72810e4:
> ?Arnd Bergmann (1):
> ? ? ? ?Merge branch 'next/fixes-non-critical' into for-next

It looks like this branch is based on the contents of the for-next
branch. That's not a stable base so I can't pull it.

If you need it to build on contents already in arm-soc, you need to
base it on either your own cleanup branch, or the aggregate next/*
branch in arm-soc. for-next is rebuilt, and is never sent up to Linus
in it's current form.

Since you said they require the cleanup branch as a base, please
rebase them on top of next/cleanup instead.

Thanks!


-Olof


From mturquette at ti.com  Fri Mar  9 13:25:00 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 9 Mar 2012 10:25:00 -0800
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120309075720.GC16608@lunn.ch>
References: <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
 <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
 <20120308062739.GE18513@lunn.ch> <20120308232549.GU3852@pengutronix.de>
 <20120309075720.GC16608@lunn.ch>
Message-ID: <CAJOA=zPztBfTY_WDwZ5iFEa94eCtHyrzN422RTACMQXs625gRA@mail.gmail.com>

On Thu, Mar 8, 2012 at 11:57 PM, Andrew Lunn <andrew at lunn.ch> wrote:
>> I'd say use the nonstatic ones. I think using the static initializers
>> will cause us much pain in the future. I've been through several rebases
>> on the i.MX clock rework and everytime I wish my sed foo would be
>> better. Now imagine what happens when it turns out that the internal
>> struct clk layout or the structs for the muxes/dividers/gates have to
>> be changed.
>
> /*****************************************************************************
> ?* CLK tree
> ?****************************************************************************/
> static DEFINE_SPINLOCK(gating_lock);
>
> #define DEFINE_KIRKWOOD_CLK_GATE(_name, _bit) ? ? ? ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ?DEFINE_CLK_GATE(_name, "tclk", NULL, 0, ? ? ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ? ? ? ? ? ? ? ? ?(void __iomem *)CLOCK_GATING_CTRL, ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ?_bit, 0, &gating_lock)
>
> DEFINE_KIRKWOOD_CLK_GATE(clk_ge0, ? ?CGC_BIT_GE0);
> DEFINE_KIRKWOOD_CLK_GATE(clk_pex0, ? CGC_BIT_PEX0);
> DEFINE_KIRKWOOD_CLK_GATE(clk_usb0, ? CGC_BIT_USB0);
> DEFINE_KIRKWOOD_CLK_GATE(clk_sdio, ? CGC_BIT_SDIO);
> DEFINE_KIRKWOOD_CLK_GATE(clk_tsu, ? ?CGC_BIT_TSU);
> DEFINE_KIRKWOOD_CLK_GATE(clk_dunit, ?CGC_BIT_DUNIT);
> DEFINE_KIRKWOOD_CLK_GATE(clk_runit, ?CGC_BIT_RUNIT);
>
> I've so far not had any problems, and not needed an sed foo. ?I do
> only have a dozen or so clocks, which helps. But even so, all the real
> pain is hidden inside DEFINE_CLK_GATE() which Mike maintains.

It's true that if the argument list for the macros doesn't change then
the pain of static initialization is hidden from the platform data.

However if you have the ability to use the clk_foo_register functions
please do use them in place of static initialization.  The static init
stuff is only for folks backed into a corner and forced to use it...
for now.  I'm looking at ways to allow for kmalloc'ing in early boot,
as well as reducing the number of clocks that my platform registers
during early boot drastically.

>
> I guess the problem comes when you are not using the basic clk
> providers, but your own provider. What might help is if
> linux/clk-provider.h could provide some macros to do most of the
> generic definitions. Something like:

I'd rather people just used the registration functions instead.

Thanks,
Mike

>
> #define DEFINE_CLK_GENERIC(_name, _flags, _ops) ? ? ? ? ? ? ? ? \
> ? ? ? ?static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?static char *_name##_parent_names[] = {}; ? ? ? ? ? ? ? \
> ? ? ? ?static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ? ? ? ? ?.name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ? ? ? ? ?.ops = &_ops, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ? ? ? ? ?.hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ? ? ? ? ?.parent_names = _name##_parent_names, ? ? ? ? ? \
> ? ? ? ? ? ? ? ?.num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ?ARRAY_SIZE(_name##_parent_names), ? ? ? \
> ? ? ? ? ? ? ? ?.flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?};
>
> and then you have something like
>
> #define DEFINE_CLK_IMX(_name, _flags, _foo, _bar) ? ? ? ? ? ? ? \
> ? ? ? ?static struct clk_imx _name##_hw = { ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?.hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> ? ? ? ? ? ? ? ? ? ? ? ?.clk = &_name, ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?}, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?.foo = _foo, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?.bar = _bar, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?}; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?DEFINE_CLK_GENERIC(_name, _flags, clk_imx_ops)
>
> ? ? ? ?Andrew


From richard.zhao at linaro.org  Fri Mar  9 09:20:46 2012
From: richard.zhao at linaro.org (Richard Zhao)
Date: Fri, 9 Mar 2012 22:20:46 +0800
Subject: [RFC] i.MX: drop secondary clocks
In-Reply-To: <20313.60910.420339.905973@ipc1.ka-ro>
References: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
 <20313.52782.832292.580932@ipc1.ka-ro>
 <20120309102931.GY3852@pengutronix.de>
 <20313.60910.420339.905973@ipc1.ka-ro>
Message-ID: <20120309142043.GA3138@richard-laptop>

On Fri, Mar 09, 2012 at 12:47:58PM +0100, Lothar Wa?mann wrote:
> Hi,
> 
> Sascha Hauer writes:
> > On Fri, Mar 09, 2012 at 10:32:30AM +0100, Lothar Wa?mann wrote:
> > > Hi,
> > > 
> > > Sascha Hauer writes:
> > > > Hi All,
> > > > 
> [...]
> > > I think that's a bad idea! Drivers should not have to know intimate
> > > details about the clock logic of the CPU core they are running on!
> > 
> > They don't have to. There really are different clocks connected to the
> > devices. If for example you have a look eSDHC Block diagram in the
> > reference Manual  you'll see that this has three clock inputs. All
> > we do is to tell the driver about these three clocks which are device
> > specific and not SoC specific. Which of these clocks are actually
> > gatetable varies from SoC to SoC. Also on some SoCs two of the three
> > clocks may be actually the same.
> > 
> At least this should be done in a way that is independent from the
> name of the clock on a specific SoC, but is related to the function of
> the clock for the driver. Thus instead of e.g. CLK_IPG and CLK_PER use
> CLK_REG and CLK_BITRATE.
> 
> > > They should simply request a clock for the unit they operate on and
> > > the clock core code should figure out which other clocks need to be
> > > enabled on a specific machine to get the unit working.
> > 
> > Yes, that's what we want to do, except that devices do not need 'a'
> > clock but several. And the clock core figures out which other clocks
> > have to be activated, these are the parent clocks.
> > 
> What about devices which have multiple 'parent' clocks that are
> completely unrelated wrt. each other? In the current clock system you
> can model this by having secondary clocks.
> How would you represent the current structure on i.MX53:
> uart_ipg_clk <- aips_tz1_clk <-+- ahb_clk
>                                +-> ahb_max_clk
> in the new model?
> Should every driver have to request the ahb_max_clk in addition to the
> uart_ipg_clk?
Right. binding bus clock and device core clock together is only one of the
use cases of secondary clock. Sascha, I remember we ever talked about it?
Back to the above example, it's caused by bus topology. It needs other
code, maybe busfreq, to support it, and leaving clock code pure.

Thanks
Richard
> 
> What, if you have a device on a number of SoCs with a certain set of
> clocks, but on a later SoC another clock is required for the device?
> You would not only have to change the driver to add the new clock but
> also would have to add that clock as a dummy clock in the core clock
> code for all previous SoCs that did not provide that clock.
> 
> > I also don't really like exposing this to the drivers, but it's a clean
> > way to do so. A framebuffer driver needs a pixel clock which must be
> > enabled when the display is turned on. It may also have a register clock
> > which has to be turned on when we want to access registers. These are
> > two different clocks and the driver can make use of this (not that we
> > currently do though...)
> > 
> But we could do so without any problem.
> 
> 
> Lothar Wa?mann
> -- 
> ___________________________________________________________
> 
> Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
> Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
> Gesch?ftsf?hrer: Matthias Kaussen
> Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
> 
> www.karo-electronics.de | info at karo-electronics.de
> ___________________________________________________________


From b39297 at freescale.com  Mon Mar 12 00:57:59 2012
From: b39297 at freescale.com (Wu Guoxing)
Date: Mon, 12 Mar 2012 12:57:59 +0800
Subject: [PATCH v7 2/2] ARM : mx35: 3ds-board: add framebuffer device
In-Reply-To: <1331528279-2263-1-git-send-email-b39297@freescale.com>
References: <1331528279-2263-1-git-send-email-b39297@freescale.com>
Message-ID: <1331528279-2263-2-git-send-email-b39297@freescale.com>

From: wu guoxing <b39297 at freescale.com>

This patch adds framebuffer support for freescale mx35 3ds board

Signed-off-by: Wu Guoxing <b39297 at freescale.com>
---
Changes since v6:
	1. use the macro for lcd-enable that added in board_mx35_3ds.h
	2. fold mc9s08dz60_lcd_gpio_get into mx35_3ds_lcd_set_power
Changes since v5:
	1. fixed a typo error in fb_modedb[].
Changes since v4:
	1. fixed a typo error in mx35_3ds_lcd_set_power.
Changes since v3:
	1. use a static variable to save the gpio value instead of find
	the gpiochip every time.
	2. add gpio_request after found the gpio.
Changes since v2:
	1. use gpio_set_value_cansleep instead of gpio_set_value
Changes since v1:
	1. use gpio driver for mc9s08dz60

arch/arm/mach-imx/mach-mx35_3ds.c |  115 +++++++++++++++++++++++++++++++++++++
 1 files changed, 115 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c..604759f 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -40,9 +40,88 @@
 #include <mach/iomux-mx35.h>
 #include <mach/irqs.h>
 #include <mach/3ds_debugboard.h>
+#include <mach/board_mx35_3ds.h>
+#include <video/platform_lcd.h>
 
 #include "devices-imx35.h"
 
+static const struct fb_videomode fb_modedb[] = {
+	{
+		 /* 800x480 @ 55 Hz */
+		.name = "Ceramate-CLAA070VC01",
+		.refresh = 55,
+		.xres = 800,
+		.yres = 480,
+		.pixclock = 40000,
+		.left_margin = 40,
+		.right_margin = 40,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 20,
+		.vsync_len = 10,
+		.sync = FB_SYNC_OE_ACT_HIGH,
+		.vmode = FB_VMODE_NONINTERLACED,
+		.flag = 0,
+	 },
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+	.irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+	.name = "Ceramate-CLAA070VC01",
+	.mode = fb_modedb,
+	.num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static struct i2c_board_info __initdata i2c_devices_3ds[] = {
+	{
+		I2C_BOARD_INFO("mc9s08dz60", 0x69),
+	},
+};
+
+static int lcd_power_gpio = -ENXIO;
+
+static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
+						     void *data)
+{
+	return !strcmp(chip->label, data);
+}
+
+static void mx35_3ds_lcd_set_power(
+				struct plat_lcd_data *pd, unsigned int power)
+{
+	struct gpio_chip *chip;
+
+	if (!gpio_is_valid(lcd_power_gpio)) {
+		chip = gpiochip_find(
+				"mc9s08dz60", mc9s08dz60_gpiochip_match);
+		if (chip) {
+			lcd_power_gpio =
+				chip->base + GPIO_MC9S08DZ60_LCD_ENABLE;
+			if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
+				pr_err("error: gpio already requested!\n");
+				lcd_power_gpio = -ENXIO;
+			}
+		} else {
+			pr_err("error: didn't find mc9s08dz60 gpio chip\n");
+		}
+	}
+
+	if (gpio_is_valid(lcd_power_gpio))
+		gpio_set_value_cansleep(lcd_power_gpio, power);
+}
+
+static struct plat_lcd_data mx35_3ds_lcd_data = {
+	.set_power = mx35_3ds_lcd_set_power,
+};
+
+static struct platform_device mx35_3ds_lcd = {
+	.name = "platform-lcd",
+	.dev.platform_data = &mx35_3ds_lcd_data,
+};
+
 #define EXPIO_PARENT_INT	gpio_to_irq(IMX_GPIO_NR(1, 1))
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -120,6 +199,32 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
 	/* I2C1 */
 	MX35_PAD_I2C1_CLK__I2C1_SCL,
 	MX35_PAD_I2C1_DAT__I2C1_SDA,
+	/* Display */
+	MX35_PAD_LD0__IPU_DISPB_DAT_0,
+	MX35_PAD_LD1__IPU_DISPB_DAT_1,
+	MX35_PAD_LD2__IPU_DISPB_DAT_2,
+	MX35_PAD_LD3__IPU_DISPB_DAT_3,
+	MX35_PAD_LD4__IPU_DISPB_DAT_4,
+	MX35_PAD_LD5__IPU_DISPB_DAT_5,
+	MX35_PAD_LD6__IPU_DISPB_DAT_6,
+	MX35_PAD_LD7__IPU_DISPB_DAT_7,
+	MX35_PAD_LD8__IPU_DISPB_DAT_8,
+	MX35_PAD_LD9__IPU_DISPB_DAT_9,
+	MX35_PAD_LD10__IPU_DISPB_DAT_10,
+	MX35_PAD_LD11__IPU_DISPB_DAT_11,
+	MX35_PAD_LD12__IPU_DISPB_DAT_12,
+	MX35_PAD_LD13__IPU_DISPB_DAT_13,
+	MX35_PAD_LD14__IPU_DISPB_DAT_14,
+	MX35_PAD_LD15__IPU_DISPB_DAT_15,
+	MX35_PAD_LD16__IPU_DISPB_DAT_16,
+	MX35_PAD_LD17__IPU_DISPB_DAT_17,
+	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
+	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
 };
 
 static int mx35_3ds_otg_init(struct platform_device *pdev)
@@ -179,6 +284,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
  */
 static void __init mx35_3ds_init(void)
 {
+	struct platform_device *imx35_fb_pdev;
+
 	imx35_soc_init();
 
 	mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
@@ -204,6 +311,14 @@ static void __init mx35_3ds_init(void)
 		pr_warn("Init of the debugboard failed, all "
 				"devices on the debugboard are unusable.\n");
 	imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+
+	i2c_register_board_info(
+		0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
+
+	imx35_add_ipu_core(&mx3_ipu_data);
+	imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
+	mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
+	platform_device_register(&mx35_3ds_lcd);
 }
 
 static void __init mx35pdk_timer_init(void)
-- 
1.7.1




From viresh.kumar at st.com  Mon Mar 12 00:43:54 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 10:13:54 +0530
Subject: [PATCH] AMBA: Add module_amba_driver() helper macro for amba_driver
Message-ID: <e8a9a1ba29099f7d6fd374d960f030b0cbdaf359.1331527353.git.viresh.kumar@st.com>

For simple modules that contain a single amba_driver without any
additional setup code then ends up being a block of duplicated
boilerplate. This patch adds a new macro, module_amba_driver(),
which replaces the module_init()/module_exit() registrations with
template functions.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/char/hw_random/nomadik-rng.c |   13 +------------
 drivers/dma/pl330.c                  |   13 +------------
 drivers/input/serio/ambakmi.c        |   13 +------------
 drivers/mmc/host/mmci.c              |   12 +-----------
 drivers/rtc/rtc-pl030.c              |   13 +------------
 drivers/rtc/rtc-pl031.c              |   13 +------------
 drivers/watchdog/sp805_wdt.c         |   12 +-----------
 include/linux/amba/bus.h             |    9 +++++++++
 sound/arm/aaci.c                     |   13 +------------
 9 files changed, 17 insertions(+), 94 deletions(-)

diff --git a/drivers/char/hw_random/nomadik-rng.c b/drivers/char/hw_random/nomadik-rng.c
index 3d3c1e6..96de024 100644
--- a/drivers/char/hw_random/nomadik-rng.c
+++ b/drivers/char/hw_random/nomadik-rng.c
@@ -107,17 +107,6 @@ static struct amba_driver nmk_rng_driver = {
 	.id_table = nmk_rng_ids,
 };
 
-static int __init nmk_rng_init(void)
-{
-	return amba_driver_register(&nmk_rng_driver);
-}
-
-static void __devexit nmk_rng_exit(void)
-{
-	amba_driver_unregister(&nmk_rng_driver);
-}
-
-module_init(nmk_rng_init);
-module_exit(nmk_rng_exit);
+module_amba_driver(nmk_rng_driver);
 
 MODULE_LICENSE("GPL");
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 84ebea9..79df175 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -1040,18 +1040,7 @@ static struct amba_driver pl330_driver = {
 	.remove = pl330_remove,
 };
 
-static int __init pl330_init(void)
-{
-	return amba_driver_register(&pl330_driver);
-}
-module_init(pl330_init);
-
-static void __exit pl330_exit(void)
-{
-	amba_driver_unregister(&pl330_driver);
-	return;
-}
-module_exit(pl330_exit);
+module_amba_driver(pl330_driver);
 
 MODULE_AUTHOR("Jaswinder Singh <jassi.brar at samsung.com>");
 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
diff --git a/drivers/input/serio/ambakmi.c b/drivers/input/serio/ambakmi.c
index 8407d5b..2ffd110 100644
--- a/drivers/input/serio/ambakmi.c
+++ b/drivers/input/serio/ambakmi.c
@@ -208,18 +208,7 @@ static struct amba_driver ambakmi_driver = {
 	.resume		= amba_kmi_resume,
 };
 
-static int __init amba_kmi_init(void)
-{
-	return amba_driver_register(&ambakmi_driver);
-}
-
-static void __exit amba_kmi_exit(void)
-{
-	amba_driver_unregister(&ambakmi_driver);
-}
-
-module_init(amba_kmi_init);
-module_exit(amba_kmi_exit);
+module_amba_driver(ambakmi_driver);
 
 MODULE_AUTHOR("Russell King <rmk at arm.linux.org.uk>");
 MODULE_DESCRIPTION("AMBA KMI controller driver");
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index ea2236a..a7f079a 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -1598,18 +1598,8 @@ static struct amba_driver mmci_driver = {
 	.id_table	= mmci_ids,
 };
 
-static int __init mmci_init(void)
-{
-	return amba_driver_register(&mmci_driver);
-}
-
-static void __exit mmci_exit(void)
-{
-	amba_driver_unregister(&mmci_driver);
-}
+module_amba_driver(mmci_driver);
 
-module_init(mmci_init);
-module_exit(mmci_exit);
 module_param(fmax, uint, 0444);
 
 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
diff --git a/drivers/rtc/rtc-pl030.c b/drivers/rtc/rtc-pl030.c
index a4a1e53..22bacdb 100644
--- a/drivers/rtc/rtc-pl030.c
+++ b/drivers/rtc/rtc-pl030.c
@@ -185,18 +185,7 @@ static struct amba_driver pl030_driver = {
 	.id_table	= pl030_ids,
 };
 
-static int __init pl030_init(void)
-{
-	return amba_driver_register(&pl030_driver);
-}
-
-static void __exit pl030_exit(void)
-{
-	amba_driver_unregister(&pl030_driver);
-}
-
-module_init(pl030_init);
-module_exit(pl030_exit);
+module_amba_driver(pl030_driver);
 
 MODULE_AUTHOR("Russell King <rmk at arm.linux.org.uk>");
 MODULE_DESCRIPTION("ARM AMBA PL030 RTC Driver");
diff --git a/drivers/rtc/rtc-pl031.c b/drivers/rtc/rtc-pl031.c
index 3a470e2..692de73 100644
--- a/drivers/rtc/rtc-pl031.c
+++ b/drivers/rtc/rtc-pl031.c
@@ -431,18 +431,7 @@ static struct amba_driver pl031_driver = {
 	.remove = pl031_remove,
 };
 
-static int __init pl031_init(void)
-{
-	return amba_driver_register(&pl031_driver);
-}
-
-static void __exit pl031_exit(void)
-{
-	amba_driver_unregister(&pl031_driver);
-}
-
-module_init(pl031_init);
-module_exit(pl031_exit);
+module_amba_driver(pl031_driver);
 
 MODULE_AUTHOR("Deepak Saxena <dsaxena at plexity.net");
 MODULE_DESCRIPTION("ARM AMBA PL031 RTC Driver");
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index e2d5249..2b0939a 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -403,17 +403,7 @@ static struct amba_driver sp805_wdt_driver = {
 	.remove = __devexit_p(sp805_wdt_remove),
 };
 
-static int __init sp805_wdt_init(void)
-{
-	return amba_driver_register(&sp805_wdt_driver);
-}
-module_init(sp805_wdt_init);
-
-static void __exit sp805_wdt_exit(void)
-{
-	amba_driver_unregister(&sp805_wdt_driver);
-}
-module_exit(sp805_wdt_exit);
+module_amba_driver(sp805_wdt_driver);
 
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout,
diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h
index a9fab83..7847e19 100644
--- a/include/linux/amba/bus.h
+++ b/include/linux/amba/bus.h
@@ -125,4 +125,13 @@ struct amba_device name##_device = {				\
 	.periphid = id,						\
 }
 
+/*
+ * module_amba_driver() - Helper macro for drivers that don't do anything
+ * special in module init/exit.  This eliminates a lot of boilerplate.  Each
+ * module may only use this macro once, and calling it replaces module_init()
+ * and module_exit()
+ */
+#define module_amba_driver(__amba_drv) \
+	module_driver(__amba_drv, amba_driver_register, amba_driver_unregister)
+
 #endif
diff --git a/sound/arm/aaci.c b/sound/arm/aaci.c
index b37b702a..5119fda 100644
--- a/sound/arm/aaci.c
+++ b/sound/arm/aaci.c
@@ -1110,18 +1110,7 @@ static struct amba_driver aaci_driver = {
 	.id_table	= aaci_ids,
 };
 
-static int __init aaci_init(void)
-{
-	return amba_driver_register(&aaci_driver);
-}
-
-static void __exit aaci_exit(void)
-{
-	amba_driver_unregister(&aaci_driver);
-}
-
-module_init(aaci_init);
-module_exit(aaci_exit);
+module_amba_driver(aaci_driver);
 
 MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Mon Mar 12 00:22:10 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:10 +0530
Subject: [PATCH V2 15/22] watchdog/mpcore_wdt: Add support for
 WDIOC_GETBOOTSTATUS IOCTL
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <11fa6e13f63feffb2242683225531edcf8e43402.1331524811.git.viresh.kumar@st.com>

mpcore watchdog can give last boot status, whether we got a watchdog reset or
not, via bit 0 of TWD_WDOG_RESETSTAT register. This patch adds support to return
correct status if WDIOC_GETBOOTSTATUS cmd is called with ioctl.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/include/asm/smp_twd.h |    2 ++
 drivers/watchdog/mpcore_wdt.c  |    4 ++++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index ef9ffba9..a13b536 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -18,6 +18,8 @@
 #define TWD_TIMER_CONTROL_PERIODIC	(1 << 1)
 #define TWD_TIMER_CONTROL_IT_ENABLE	(1 << 2)
 
+#define TWD_WDOG_RESETSTAT_MASK		0x1
+
 struct clock_event_device;
 
 extern void __iomem *twd_base;
diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 0d2ea32..73d50c3 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -148,6 +148,7 @@ static int mpcore_wdt_set_heartbeat(struct watchdog_device *wdd, unsigned int t)
 static const struct watchdog_info mpcore_wdt_info = {
 	.options		= WDIOF_SETTIMEOUT |
 				  WDIOF_KEEPALIVEPING |
+				  WDIOF_CARDRESET |
 				  WDIOF_MAGICCLOSE,
 	.identity		= "MPcore Watchdog",
 };
@@ -213,6 +214,9 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, wdt);
 	watchdog_set_drvdata(&wdt->wdd, wdt);
 
+	wdt->wdd.bootstatus = (readl_relaxed(wdt->base + TWD_WDOG_RESETSTAT) &
+			TWD_WDOG_RESETSTAT_MASK) ? WDIOF_CARDRESET : 0;
+
 	mpcore_wdt_stop(&wdt->wdd);
 
 	ret = watchdog_register_device(&wdt->wdd);
-- 
1.7.8.110.g4cb5d



From sfr at canb.auug.org.au  Fri Mar  9 02:17:55 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 9 Mar 2012 18:17:55 +1100
Subject: linux-next: manual merge of the arm-soc tree with the regulator tree
Message-ID: <20120309181755.256b898808bd14726de0e977@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
drivers/regulator/Makefile between commit 8aa1ab9219e7 ("regulator: Sort
Kconfig and Makefile entries") from the regulator tree and commit
8a16a701ad78 ("regulator: Remove bq24022 regulator driver") from the
arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc drivers/regulator/Makefile
index 2b09c81,f53cf80..0000000
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@@ -10,17 -10,7 +10,16 @@@ obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER
  obj-$(CONFIG_REGULATOR_USERSPACE_CONSUMER) += userspace-consumer.o
  
  obj-$(CONFIG_REGULATOR_GPIO) += gpio-regulator.o
 +obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
 +obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
 +obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
 +obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
  obj-$(CONFIG_REGULATOR_AD5398) += ad5398.o
- obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o
 +obj-$(CONFIG_REGULATOR_DA903X)	+= da903x.o
 +obj-$(CONFIG_REGULATOR_DA9052)	+= da9052-regulator.o
 +obj-$(CONFIG_REGULATOR_DBX500_PRCMU) += dbx500-prcmu.o
 +obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
 +obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
  obj-$(CONFIG_REGULATOR_LP3971) += lp3971.o
  obj-$(CONFIG_REGULATOR_LP3972) += lp3972.o
  obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o
-------------- next part --------------
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From lost.distance at yahoo.com  Fri Mar  9 09:55:43 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 9 Mar 2012 14:55:43 +0000 (GMT)
Subject: [PATCH 1/2 v6] pxa/hx4700: Add PCMCIA/CF support
Message-ID: <1331304943.14160.YahooMailClassic@web29011.mail.ird.yahoo.com>

Add PCMCIA/CF support for the HP iPAQ hx4700. Underlying support is provided by
the pcmcia/pxa2xx_hx4700 platform_device implementation which hooks into the
existing pxa2xx-pcmcia driver.

Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
---

V6:
Fixed comment typo ("asci3" should have been "asic3").
Rebased to linux-3.3-rc6 with pending ARM SA11x0 / PXA / SoC-common PCMCIA
cleanups (new irq/gpio management provided by soc_common) applied.

Note:
Since V4 this is dependent on the pending ARM SA11x0 / PXA / SoC-common PCMCIA
cleanups (new irq/gpio management provided by soc_common).

diff -uprN clean-3.3-rc6/drivers/mfd/asic3.c linux-3.3-rc6/drivers/mfd/asic3.c
--- clean-3.3-rc6/drivers/mfd/asic3.c	2012-03-09 14:24:22.308058919 +0000
+++ linux-3.3-rc6/drivers/mfd/asic3.c	2012-03-09 14:20:39.278593824 +0000
@@ -992,6 +992,9 @@ static int __init asic3_probe(struct pla
 
 	asic3_mfd_probe(pdev, pdata, mem);
 
+	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
+		(ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1);
+
 	dev_info(asic->dev, "ASIC3 Core driver\n");
 
 	return 0;
@@ -1013,6 +1016,9 @@ static int __devexit asic3_remove(struct
 	int ret;
 	struct asic3 *asic = platform_get_drvdata(pdev);
 
+	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
+		(ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0);
+
 	asic3_mfd_remove(pdev);
 
 	ret = asic3_gpio_remove(pdev);
diff -uprN clean-3.3-rc6/drivers/pcmcia/Kconfig linux-3.3-rc6/drivers/pcmcia/Kconfig
--- clean-3.3-rc6/drivers/pcmcia/Kconfig	2012-03-09 14:24:41.060182102 +0000
+++ linux-3.3-rc6/drivers/pcmcia/Kconfig	2012-03-09 14:21:34.662957646 +0000
@@ -217,7 +217,7 @@ config PCMCIA_PXA2XX
 		    || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \
 		    || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2 \
 		    || MACH_VPAC270 || MACH_BALLOON3 || MACH_COLIBRI \
-		    || MACH_COLIBRI320)
+		    || MACH_COLIBRI320 || MACH_H4700)
 	select PCMCIA_SA1111 if ARCH_LUBBOCK && SA1111
 	select PCMCIA_SOC_COMMON
 	help
diff -uprN clean-3.3-rc6/drivers/pcmcia/Makefile linux-3.3-rc6/drivers/pcmcia/Makefile
--- clean-3.3-rc6/drivers/pcmcia/Makefile	2012-03-09 14:24:41.060182102 +0000
+++ linux-3.3-rc6/drivers/pcmcia/Makefile	2012-03-09 14:20:39.282593851 +0000
@@ -69,6 +69,7 @@ pxa2xx-obj-$(CONFIG_MACH_VPAC270)		+= px
 pxa2xx-obj-$(CONFIG_MACH_BALLOON3)		+= pxa2xx_balloon3.o
 pxa2xx-obj-$(CONFIG_MACH_COLIBRI)		+= pxa2xx_colibri.o
 pxa2xx-obj-$(CONFIG_MACH_COLIBRI320)		+= pxa2xx_colibri.o
+pxa2xx-obj-$(CONFIG_MACH_H4700)			+= pxa2xx_hx4700.o
 
 obj-$(CONFIG_PCMCIA_PXA2XX)			+= pxa2xx_base.o $(pxa2xx-obj-y)
 
diff -uprN clean-3.3-rc6/drivers/pcmcia/pxa2xx_hx4700.c linux-3.3-rc6/drivers/pcmcia/pxa2xx_hx4700.c
--- clean-3.3-rc6/drivers/pcmcia/pxa2xx_hx4700.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-3.3-rc6/drivers/pcmcia/pxa2xx_hx4700.c	2012-03-09 14:20:39.282593851 +0000
@@ -0,0 +1,121 @@
+/*
+ *  Copyright (C) 2012 Paul Parsons <lost.distance at yahoo.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <mach/hx4700.h>
+
+#include "soc_common.h"
+
+static struct gpio gpios[] = {
+	{ GPIO114_HX4700_CF_RESET,    GPIOF_OUT_INIT_LOW,   "CF reset"        },
+	{ EGPIO4_CF_3V3_ON,           GPIOF_OUT_INIT_LOW,   "CF 3.3V enable"  },
+};
+
+static int hx4700_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
+{
+	int ret;
+
+	ret = gpio_request_array(gpios, ARRAY_SIZE(gpios));
+	if (ret)
+		goto out;
+
+	/*
+	 * IRQ type must be set before soc_pcmcia_hw_init() calls request_irq().
+	 * The asic3 default IRQ type is level trigger low level detect, exactly
+	 * the the signal present on GPIOD4_CF_nCD when a CF card is inserted.
+	 * If the IRQ type is not changed, the asic3 interrupt handler will loop
+	 * repeatedly because it is unable to clear the level trigger interrupt.
+	 */
+	irq_set_irq_type(gpio_to_irq(GPIOD4_CF_nCD), IRQ_TYPE_EDGE_BOTH);
+
+	skt->stat[SOC_STAT_CD].gpio = GPIOD4_CF_nCD;
+	skt->stat[SOC_STAT_CD].name = "PCMCIA CD";
+	skt->stat[SOC_STAT_RDY].gpio = GPIO60_HX4700_CF_RNB;
+	skt->stat[SOC_STAT_RDY].name = "PCMCIA Ready";
+
+out:
+	return ret;
+}
+
+static void hx4700_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
+{
+	gpio_free_array(gpios, ARRAY_SIZE(gpios));
+}
+
+static void hx4700_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
+	struct pcmcia_state *state)
+{
+	state->vs_3v = 1;
+	state->vs_Xv = 0;
+}
+
+static int hx4700_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
+	const socket_state_t *state)
+{
+	switch (state->Vcc) {
+	case 0:
+		gpio_set_value(EGPIO4_CF_3V3_ON, 0);
+		break;
+	case 33:
+		gpio_set_value(EGPIO4_CF_3V3_ON, 1);
+		break;
+	default:
+		printk(KERN_ERR "pcmcia: Unsupported Vcc: %d\n", state->Vcc);
+		return -EINVAL;
+	}
+
+	gpio_set_value(GPIO114_HX4700_CF_RESET, (state->flags & SS_RESET) != 0);
+
+	return 0;
+}
+
+static struct pcmcia_low_level hx4700_pcmcia_ops = {
+	.owner          = THIS_MODULE,
+	.nr             = 1,
+	.hw_init        = hx4700_pcmcia_hw_init,
+	.hw_shutdown    = hx4700_pcmcia_hw_shutdown,
+	.socket_state   = hx4700_pcmcia_socket_state,
+	.configure_socket = hx4700_pcmcia_configure_socket,
+};
+
+static struct platform_device *hx4700_pcmcia_device;
+
+static int __init hx4700_pcmcia_init(void)
+{
+	struct platform_device *pdev;
+
+	if (!machine_is_h4700())
+		return -ENODEV;
+
+	pdev = platform_device_register_data(NULL, "pxa2xx-pcmcia", -1,
+		&hx4700_pcmcia_ops, sizeof(hx4700_pcmcia_ops));
+	if (IS_ERR(pdev))
+		return PTR_ERR(pdev);
+
+	hx4700_pcmcia_device = pdev;
+
+	return 0;
+}
+
+static void __exit hx4700_pcmcia_exit(void)
+{
+	platform_device_unregister(hx4700_pcmcia_device);
+}
+
+module_init(hx4700_pcmcia_init);
+module_exit(hx4700_pcmcia_exit);
+
+MODULE_AUTHOR("Paul Parsons <lost.distance at yahoo.com>");
+MODULE_DESCRIPTION("HP iPAQ hx4700 PCMCIA driver");
+MODULE_LICENSE("GPL");



From richard.zhao at linaro.org  Sun Mar 11 03:52:54 2012
From: richard.zhao at linaro.org (Richard Zhao)
Date: Sun, 11 Mar 2012 15:52:54 +0800
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <1331366064-1273-3-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
Message-ID: <20120311075250.GB3138@richard-laptop>

Looks like you didn't take my comments for v5.
http://www.spinics.net/lists/arm-kernel/msg162903.html 

Regards
Richard


From robherring2 at gmail.com  Sat Mar 10 14:14:52 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sat, 10 Mar 2012 13:14:52 -0600
Subject: [GIT PULL] mach/io.h clean-up and removal
In-Reply-To: <CAOesGMi1pD+1BEkXSGDA8k6UC2DD65QYt3Z_59McFkgWrdqehQ@mail.gmail.com>
References: <4F58DD30.4060704@gmail.com>
 <CAOesGMi1pD+1BEkXSGDA8k6UC2DD65QYt3Z_59McFkgWrdqehQ@mail.gmail.com>
Message-ID: <4F5BA82C.1040400@gmail.com>

On 03/10/2012 12:20 PM, Olof Johansson wrote:
> Hi,
> 
> On Thu, Mar 8, 2012 at 8:24 AM, Rob Herring <robherring2 at gmail.com> wrote:
>> Arnd, Olof,
>>
>> Please pull the mach/io.h cleanup series for 3.4. This does not include
>> the PCI i/o mapping changes. In hopes of testing, I'll wait until 3.5
>> for that. Although, it seems no one has devices with i/o.
>>
>> I'm sending this to you rather than Russell as it is based on at91 and
>> omap cleanup branches in arm-soc tree.
>>
>> Rob
>>
>> The following changes since commit d50673ed97a7ce609cf62bcd40c57517ada31806:
>>
>>  Merge remote-tracking branch 'arm-soc/at91/base2+cleanup' into
>> cleanup-base (2012-03-04 22:00:46 -0600)
>>
>> are available in the git repository at:
>>
>>  git://sources.calxeda.com/kernel/linux.git io-cleanup-for-3.4
> 
> I've pulled this into next/cleanup2. Nice diffstat!
> 

Actually, Arnd just found some abusers of __io() that I need to fix
first. They are using __io() to cast defines to a void __iomem * ptr. I
should have something out for review soon. So please drop this and I'll
send a new pull request.

Rob


From tomi.valkeinen at ti.com  Fri Mar  9 07:31:41 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Fri, 09 Mar 2012 14:31:41 +0200
Subject: linux-next: manual merge of the arm-soc tree with the
 omap_dss2 tree
In-Reply-To: <201203091226.53749.arnd@arndb.de>
References: <20120308170048.f1a992bca2ca2d93fa9747bf@canb.auug.org.au>
 <201203091150.11294.arnd@arndb.de> <1331295269.1927.54.camel@deskari>
 <201203091226.53749.arnd@arndb.de>
Message-ID: <1331296301.1927.64.camel@deskari>

On Fri, 2012-03-09 at 12:26 +0000, Arnd Bergmann wrote:
> On Friday 09 March 2012, Tomi Valkeinen wrote:

> > Merging omapdss tree through arm-soc would make sense for avoiding
> > conflicts, because almost every merge window there are some conflicts as
> > I often need to edit arch/arm files also. But I'm not sure if we have
> > ever had a conflict in drivers/video.
> > 
> > But still, it's a video driver, and fbdev tree sounds more suited for a
> > video driver.
> > 
> > So I don't know =). Basically it's ok for me either way also. But it
> > would be nice to have a standard way of doing this, instead of, for
> > example, merging omapdss sometimes through fbdev, sometimes through
> > arm-soc, depending on the conflicts...
> 
> Actually, I did not suggest omapdss through arm-soc, the idea was that
> that the same branch gets merged into both the fbdev and the arm-soc
> trees and let the fbdev tree go to Linus first.

Ah, right, now I see. This sounds ok to me. I'll cc you when I send the
pull request to Florian (presuming the arrangement is fine for him).

 Tomi

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From hvaibhav at ti.com  Fri Mar  9 12:58:00 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 9 Mar 2012 17:58:00 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <20120305225530.GJ12083@atomide.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <20120305225530.GJ12083@atomide.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83180F73D@DBDE01.ent.ti.com>

On Tue, Mar 06, 2012 at 04:25:30, Tony Lindgren wrote:
> Hi,
> 
> * Vaibhav Hiremath <hvaibhav at ti.com> [120119 06:01]:
> > OMAP device has 32k-sync timer which is currently used as a
> > clocksource in the kernel (omap2plus_defconfig).
> > The current implementation uses compile time selection between
> > gp-timer and 32k-sync timer, which breaks multi-omap build for
> > the devices like AM33xx, where 32k-sync timer is not available.
> > 
> > So use hwmod database lookup mechanism, through which at run-time
> > we can identify availability of 32k-sync timer on the device,
> > else fall back to gp-timer.
> ...
> 
> > --- a/arch/arm/plat-omap/counter_32k.c
> > +++ b/arch/arm/plat-omap/counter_32k.c
> > @@ -69,52 +69,55 @@ void read_persistent_clock(struct timespec *ts)
> >  
> >  int __init omap_init_clocksource_32k(void)
> >  {
> > -	static char err[] __initdata = KERN_ERR
> > -			"%s: can't register clocksource!\n";
> > -
> > -	if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
> > -		u32 pbase;
> > -		unsigned long size = SZ_4K;
> > -		void __iomem *base;
> > -		struct clk *sync_32k_ick;
> > -
> > -		if (cpu_is_omap16xx()) {
> > -			pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > -			size = SZ_1K;
> > -		} else if (cpu_is_omap2420())
> > -			pbase = OMAP2420_32KSYNCT_BASE + 0x10;
> > -		else if (cpu_is_omap2430())
> > -			pbase = OMAP2430_32KSYNCT_BASE + 0x10;
> > -		else if (cpu_is_omap34xx())
> > -			pbase = OMAP3430_32KSYNCT_BASE + 0x10;
> > -		else if (cpu_is_omap44xx())
> > -			pbase = OMAP4430_32KSYNCT_BASE + 0x10;
> > -		else
> > +	u32 pbase;
> > +	unsigned long size = SZ_4K;
> > +	void __iomem *base;
> > +	struct clk *sync_32k_ick;
> > +
> > +	if (cpu_is_omap16xx()) {
> > +		pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> > +		size = SZ_1K;
> > +	} else if (cpu_class_is_omap2()) {
> > +		struct omap_hwmod *oh;
> > +		const char *oh_name = "counter_32k";
> > +
> > +		oh = omap_hwmod_lookup(oh_name);
> > +		if (!oh || oh->slaves_cnt == 0) {
> > +			pr_err("Could not lookup %s hwmod\n", oh_name);
> >  			return -ENODEV;
> > +		}
> > +		pbase = oh->slaves[0]->addr->pa_start + 0x10;
> > +	} else {
> > +		return -ENODEV;
> > +	}
> 
> How about have separate omap1 and omap2+ init functions that
> call a common function and passes the pbase as a parameter?
> 
> That way we can get rid of the cpu_is_omapxxxx tests here.
> 

Tony,

In the morning, I replied very soon, without much thinking...

Just now I started working on the patch, I was just reviewing the code, 
and I felt that, it is unnecessary to split the code between omap1 and 
omap2+.

The reason is,

Currently Only OMAP16xx base-address is hardcoded with cpu_is_omap16xx() 
macro, For all other omap family of devices the complete information is fetched from HWDMO api's/data.

Thanks,
Vaibhav

> Regards,
> 
> Tony 
> 



From grant.likely at secretlab.ca  Fri Mar  9 11:26:38 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 09 Mar 2012 09:26:38 -0700
Subject: [PATCH 1/1] of: introduce helper to manage boolean
In-Reply-To: <20120309100435.GN27213@game.jcrosoft.org>
References: <1328588028-24766-1-git-send-email-plagnioj@jcrosoft.com>
 <20120309014441.8236B3E0903@localhost>
 <20120309100435.GN27213@game.jcrosoft.org>
Message-ID: <20120309162638.92E813E0880@localhost>

On Fri, 9 Mar 2012 11:04:35 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> On 18:44 Thu 08 Mar     , Grant Likely wrote:
> > On Tue,  7 Feb 2012 05:13:48 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > > of_property_read_bool
> > > 
> > > Search for a property in a device node and read a 32-bit value from
> > > it. Returns 0 if <0> or if the property does not exist, 1 if <1> or none.
> > > 
> > > this will allow to disable a boolean
> > > 
> > > is-ok;          => true
> > > is-ok = <1>;    => true
> > > is-ok = <0>;    => false
> > > 
> > > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > > Cc: devicetree-discuss at lists.ozlabs.org
> > > ---
> > > Hi,
> > > 
> > > 	if this is ok I'll rebase my mtd and i2c patch to use it
> > > 
> > > Best Regards,
> > > J.
> > >  drivers/of/base.c  |   30 ++++++++++++++++++++++++++++++
> > >  include/linux/of.h |    8 ++++++++
> > >  2 files changed, 38 insertions(+), 0 deletions(-)
> > > 
> > > diff --git a/drivers/of/base.c b/drivers/of/base.c
> > > index 133908a..a0eaf08 100644
> > > --- a/drivers/of/base.c
> > > +++ b/drivers/of/base.c
> > > @@ -686,6 +686,36 @@ int of_property_read_u64(const struct device_node *np, const char *propname,
> > >  EXPORT_SYMBOL_GPL(of_property_read_u64);
> > >  
> > >  /**
> > > + * of_property_read_bool - Find and read a boolean from a property
> > > + * @np:		device node from which the property value is to be read.
> > > + * @propname:	name of the property to be searched.
> > > + *
> > > + * Search for a property in a device node and read a 32-bit value from
> > > + * it. Returns 0 if <0> or if the property does not exist, 1 if <1> or none.
> > > + *
> > > + * is-ok;	=> true
> > > + * is-ok = <1>;	=> true
> > > + * is-ok = <0>;	=> false
> > > + */
> > > +int of_property_read_bool(const struct device_node *np, const char *propname)
> > > +{
> > > +	u32 reg;
> > > +	int ret = of_property_read_u32(np, propname, &reg);
> > > +
> > > +	switch (ret) {
> > > +	case -EINVAL:
> > > +		return false;
> > > +	case -ENODATA:
> > > +		return true;
> > > +	case 0:
> > > +		return reg == 1;
> > 
> > Ugh.  so any value other than 1 returns false?  I think that will surprise
> > most people.
> > 
> > I don't like this api or binding.  If it is a bool property, then why isn't
> > simply testing for the property existance sufficient?
> no if you want to disable it
> 
> if a bool is define in the dtsi and want to disable it int the dts
> 
> if you we can do the the invert
> 
> if !0 => true
> 
> is-ok;			=> true
> is-ok = <val != 0>;	=> true
> is-ok = <0>;		=> false

This is a failure of the dtc tool, not the binding.  Accepting this binding
means we have to live with it for a very long time.  It needs to be fixed
in dtc instead so that properties can be deleted instead of only modified.

g.



From mturquette at ti.com  Fri Mar  9 17:50:26 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 9 Mar 2012 14:50:26 -0800
Subject: [PATCH v5 4/4] clk: basic clock hardware types
In-Reply-To: <20120307212025.GC26882@pengutronix.de>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-5-git-send-email-mturquette@linaro.org>
 <20120307212025.GC26882@pengutronix.de>
Message-ID: <CAJOA=zM0rymi3r897grTbWRA2UZm07Fb4682ee15Z0Zz1RtA3g@mail.gmail.com>

On Wed, Mar 7, 2012 at 1:20 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Sat, Mar 03, 2012 at 12:29:01AM -0800, Mike Turquette wrote:
>> +struct clk *clk_register_divider(struct device *dev, const char *name,
>> + ? ? ? ? ? ? const char *parent_name, unsigned long flags,
>> + ? ? ? ? ? ? void __iomem *reg, u8 shift, u8 width,
>> + ? ? ? ? ? ? u8 clk_divider_flags, spinlock_t *lock)
>> +{
>> + ? ? struct clk_divider *div;
>> + ? ? char **parent_names = NULL;
>> + ? ? u8 len;
>> +
>> + ? ? div = kmalloc(sizeof(struct clk_divider), GFP_KERNEL);
>> +
>> + ? ? if (!div) {
>> + ? ? ? ? ? ? pr_err("%s: could not allocate divider clk\n", __func__);
>> + ? ? ? ? ? ? return ERR_PTR(-ENOMEM);
>> + ? ? }
>> +
>> + ? ? /* struct clk_divider assignments */
>> + ? ? div->reg = reg;
>> + ? ? div->shift = shift;
>> + ? ? div->width = width;
>> + ? ? div->flags = clk_divider_flags;
>> + ? ? div->lock = lock;
>> +
>> + ? ? if (parent_name) {
>> + ? ? ? ? ? ? parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
>> +
>> + ? ? ? ? ? ? if (! parent_names)
>> + ? ? ? ? ? ? ? ? ? ? goto out;
>> +
>> + ? ? ? ? ? ? len = sizeof(char) * strlen(parent_name);
>> +
>> + ? ? ? ? ? ? parent_names[0] = kmalloc(len, GFP_KERNEL);
>> +
>> + ? ? ? ? ? ? if (!parent_names[0])
>> + ? ? ? ? ? ? ? ? ? ? goto out;
>> +
>> + ? ? ? ? ? ? strncpy(parent_names[0], parent_name, len);
>> + ? ? }
>> +
>> +out:
>> + ? ? return clk_register(dev, name,
>> + ? ? ? ? ? ? ? ? ? ? &clk_divider_ops, &div->hw,
>> + ? ? ? ? ? ? ? ? ? ? parent_names,
>> + ? ? ? ? ? ? ? ? ? ? (parent_name ? 1 : 0),
>> + ? ? ? ? ? ? ? ? ? ? flags);
>> +}
>
> clk_register_divider and also clk_register_gate have some problems.
> First you allocate memory with exactly the string length without
> the terminating 0. Then the functions leak memory when clk_register
> fails. Could you fold in the following patch to fix this?

Thanks for the patch Sascha.  This has been pulled into v6 and tested.

Regards,
Mike

>
> Sascha
>
> 8<--------------------------------------------------
>
> fix divider/gate registration
>
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
> ?drivers/clk/clk-divider.c ? ?| ? 34 +++++++++++++++-------------------
> ?drivers/clk/clk-gate.c ? ? ? | ? 33 ++++++++++++++-------------------
> ?include/linux/clk-provider.h | ? ?2 ++
> ?3 files changed, 31 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 8f02930..99b6b55 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -156,14 +156,13 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
> ? ? ? ? ? ? ? ?u8 clk_divider_flags, spinlock_t *lock)
> ?{
> ? ? ? ?struct clk_divider *div;
> - ? ? ? char **parent_names = NULL;
> - ? ? ? u8 len;
> + ? ? ? struct clk *clk;
>
> - ? ? ? div = kmalloc(sizeof(struct clk_divider), GFP_KERNEL);
> + ? ? ? div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
>
> ? ? ? ?if (!div) {
> ? ? ? ? ? ? ? ?pr_err("%s: could not allocate divider clk\n", __func__);
> - ? ? ? ? ? ? ? return ERR_PTR(-ENOMEM);
> + ? ? ? ? ? ? ? return NULL;
> ? ? ? ?}
>
> ? ? ? ?/* struct clk_divider assignments */
> @@ -174,25 +173,22 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
> ? ? ? ?div->lock = lock;
>
> ? ? ? ?if (parent_name) {
> - ? ? ? ? ? ? ? parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
> -
> - ? ? ? ? ? ? ? if (! parent_names)
> - ? ? ? ? ? ? ? ? ? ? ? goto out;
> -
> - ? ? ? ? ? ? ? len = sizeof(char) * strlen(parent_name);
> -
> - ? ? ? ? ? ? ? parent_names[0] = kmalloc(len, GFP_KERNEL);
> -
> - ? ? ? ? ? ? ? if (!parent_names[0])
> + ? ? ? ? ? ? ? div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
> + ? ? ? ? ? ? ? if (!div->parent[0])
> ? ? ? ? ? ? ? ? ? ? ? ?goto out;
> -
> - ? ? ? ? ? ? ? strncpy(parent_names[0], parent_name, len);
> ? ? ? ?}
>
> -out:
> - ? ? ? return clk_register(dev, name,
> + ? ? ? clk = clk_register(dev, name,
> ? ? ? ? ? ? ? ? ? ? ? ?&clk_divider_ops, &div->hw,
> - ? ? ? ? ? ? ? ? ? ? ? parent_names,
> + ? ? ? ? ? ? ? ? ? ? ? div->parent,
> ? ? ? ? ? ? ? ? ? ? ? ?(parent_name ? 1 : 0),
> ? ? ? ? ? ? ? ? ? ? ? ?flags);
> + ? ? ? if (clk)
> + ? ? ? ? ? ? ? return clk;
> +
> +out:
> + ? ? ? kfree(div->parent[0]);
> + ? ? ? kfree(div);
> +
> + ? ? ? return NULL;
> ?}
> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> index e831f7b..92c0489 100644
> --- a/drivers/clk/clk-gate.c
> +++ b/drivers/clk/clk-gate.c
> @@ -80,14 +80,13 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
> ? ? ? ? ? ? ? ?u8 clk_gate_flags, spinlock_t *lock)
> ?{
> ? ? ? ?struct clk_gate *gate;
> - ? ? ? char **parent_names = NULL;
> - ? ? ? u8 len;
> + ? ? ? struct clk *clk;
>
> - ? ? ? gate = kmalloc(sizeof(struct clk_gate), GFP_KERNEL);
> + ? ? ? gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
>
> ? ? ? ?if (!gate) {
> ? ? ? ? ? ? ? ?pr_err("%s: could not allocate gated clk\n", __func__);
> - ? ? ? ? ? ? ? return ERR_PTR(-ENOMEM);
> + ? ? ? ? ? ? ? return NULL;
> ? ? ? ?}
>
> ? ? ? ?/* struct clk_gate assignments */
> @@ -97,25 +96,21 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
> ? ? ? ?gate->lock = lock;
>
> ? ? ? ?if (parent_name) {
> - ? ? ? ? ? ? ? parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
> -
> - ? ? ? ? ? ? ? if (! parent_names)
> - ? ? ? ? ? ? ? ? ? ? ? goto out;
> -
> - ? ? ? ? ? ? ? len = sizeof(char) * strlen(parent_name);
> -
> - ? ? ? ? ? ? ? parent_names[0] = kmalloc(len, GFP_KERNEL);
> -
> - ? ? ? ? ? ? ? if (!parent_names[0])
> + ? ? ? ? ? ? ? gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
> + ? ? ? ? ? ? ? if (!gate->parent[0])
> ? ? ? ? ? ? ? ? ? ? ? ?goto out;
> -
> - ? ? ? ? ? ? ? strncpy(parent_names[0], parent_name, len);
> ? ? ? ?}
>
> -out:
> - ? ? ? return clk_register(dev, name,
> + ? ? ? clk = clk_register(dev, name,
> ? ? ? ? ? ? ? ? ? ? ? ?&clk_gate_ops, &gate->hw,
> - ? ? ? ? ? ? ? ? ? ? ? parent_names,
> + ? ? ? ? ? ? ? ? ? ? ? gate->parent,
> ? ? ? ? ? ? ? ? ? ? ? ?(parent_name ? 1 : 0),
> ? ? ? ? ? ? ? ? ? ? ? ?flags);
> + ? ? ? if (clk)
> + ? ? ? ? ? ? ? return clk;
> +out:
> + ? ? ? kfree(gate->parent[0]);
> + ? ? ? kfree(gate);
> +
> + ? ? ? return NULL;
> ?}
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 9b7dd5e..ed1f918 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -174,6 +174,7 @@ struct clk_gate {
> ? ? ? ?u8 ? ? ? ? ? ? ?bit_idx;
> ? ? ? ?u8 ? ? ? ? ? ? ?flags;
> ? ? ? ?spinlock_t ? ? ?*lock;
> + ? ? ? char ? ? ? ? ? ?*parent[1];
> ?};
>
> ?#define CLK_GATE_SET_TO_DISABLE ? ? ? ? ? ? ? ?BIT(0)
> @@ -210,6 +211,7 @@ struct clk_divider {
> ? ? ? ?u8 ? ? ? ? ? ? ?width;
> ? ? ? ?u8 ? ? ? ? ? ? ?flags;
> ? ? ? ?spinlock_t ? ? ?*lock;
> + ? ? ? char ? ? ? ? ? ?*parent[1];
> ?};
>
> ?#define CLK_DIVIDER_ONE_BASED ? ? ? ? ?BIT(0)
> --
> 1.7.9.1
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |


From viresh.kumar at st.com  Mon Mar 12 00:22:05 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:05 +0530
Subject: [PATCH V2 10/22] watchdog/mpcore_wdt: Use dev_(crit, err,
 info) instead of dev_printk
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <6e02b1c0f3c1540da56b92a06161a800a1089145.1331524811.git.viresh.kumar@st.com>

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |    7 +++----
 1 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 19aaad7..c820e4f 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -71,8 +71,7 @@ static irqreturn_t mpcore_wdt_fire(int irq, void *arg)
 
 	/* Check it really was our interrupt */
 	if (readl(wdt->base + TWD_WDOG_INTSTAT)) {
-		dev_printk(KERN_CRIT, wdt->dev,
-					"Triggered - Reboot ignored.\n");
+		dev_crit(wdt->dev, "Triggered - Reboot ignored.\n");
 		/* Clear the interrupt on the watchdog */
 		writel(1, wdt->base + TWD_WDOG_INTSTAT);
 		return IRQ_HANDLED;
@@ -123,7 +122,7 @@ static int mpcore_wdt_start(struct watchdog_device *wdd)
 {
 	struct mpcore_wdt *wdt = watchdog_get_drvdata(wdd);
 
-	dev_printk(KERN_INFO, wdt->dev, "enabling watchdog.\n");
+	dev_info(wdt->dev, "enabling watchdog.\n");
 
 	/* This loads the count register but does NOT start the count yet */
 	mpcore_wdt_ping(wdd);
@@ -192,7 +191,7 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		ret = devm_request_irq(wdt->dev, wdt->irq, mpcore_wdt_fire, 0,
 				"mpcore_wdt", wdt);
 		if (ret) {
-			dev_printk(KERN_ERR, wdt->dev,
+			dev_err(wdt->dev,
 					"cannot register IRQ%d for watchdog\n",
 					wdt->irq);
 			return ret;
-- 
1.7.8.110.g4cb5d



From paul.liu at linaro.org  Fri Mar  9 02:57:09 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Fri,  9 Mar 2012 15:57:09 +0800
Subject: [PATCH v11] Regulator: Add Anatop regulator driver
Message-ID: <1331279829-4584-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.

Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Liam Girdwood <lrg at ti.com>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Axel Lin <axel.lin at gmail.com>
---
 drivers/regulator/Kconfig            |    8 +
 drivers/regulator/Makefile           |    1 +
 drivers/regulator/anatop-regulator.c |  238 ++++++++++++++++++++++++++++++++++
 3 files changed, 247 insertions(+), 0 deletions(-)
 create mode 100644 drivers/regulator/anatop-regulator.c

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index c733df5..a229de9 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -102,6 +102,14 @@ config REGULATOR_DA9052
 	  This driver supports the voltage regulators of DA9052-BC and
 	  DA9053-AA/Bx PMIC.
 
+config REGULATOR_ANATOP
+	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
+	depends on MFD_ANATOP
+	help
+	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
+	  regulators. It is recommended that this option be
+	  enabled on i.MX6 platform.
+
 config REGULATOR_MC13XXX_CORE
 	tristate
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 2b09c81..b5042c8 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
 obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
 obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
 obj-$(CONFIG_REGULATOR_AD5398) += ad5398.o
+obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
 obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o
 obj-$(CONFIG_REGULATOR_DA903X)	+= da903x.o
 obj-$(CONFIG_REGULATOR_DA9052)	+= da9052-regulator.o
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
new file mode 100644
index 0000000..53a2d87
--- /dev/null
+++ b/drivers/regulator/anatop-regulator.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+
+struct anatop_regulator {
+	const char *name;
+	u32 control_reg;
+	struct anatop *mfd;
+	int vol_bit_shift;
+	int vol_bit_width;
+	int min_bit_val;
+	int min_voltage;
+	int max_voltage;
+	struct regulator_desc rdesc;
+	struct regulator_init_data *initdata;
+};
+
+static int anatop_set_voltage(struct regulator_dev *reg, int min_uV,
+				  int max_uV, unsigned *selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	u32 val, sel;
+	int uv;
+
+	uv = min_uV;
+	dev_dbg(&reg->dev, "%s: uv %d, min %d, max %d\n", __func__,
+		uv, anatop_reg->min_voltage,
+		anatop_reg->max_voltage);
+
+	if (uv < anatop_reg->min_voltage) {
+		if (max_uV > anatop_reg->min_voltage)
+			uv = anatop_reg->min_voltage;
+		else
+			return -EINVAL;
+	}
+
+	if (!anatop_reg->control_reg)
+		return -ENOTSUPP;
+
+	sel = DIV_ROUND_UP(uv - anatop_reg->min_voltage, 25000);
+	if (sel * 25000 + anatop_reg->min_voltage > anatop_reg->max_voltage)
+		return -EINVAL;
+	val = anatop_reg->min_bit_val + sel;
+	*selector = sel;
+	dev_dbg(&reg->dev, "%s: calculated val %d\n", __func__, val);
+	anatop_set_bits(anatop_reg->mfd,
+			anatop_reg->control_reg,
+			anatop_reg->vol_bit_shift,
+			anatop_reg->vol_bit_width,
+			val);
+
+	return 0;
+}
+
+static int anatop_get_voltage_sel(struct regulator_dev *reg)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	u32 val;
+
+	if (!anatop_reg->control_reg)
+		return -ENOTSUPP;
+
+	val = anatop_get_bits(anatop_reg->mfd,
+			      anatop_reg->control_reg,
+			      anatop_reg->vol_bit_shift,
+			      anatop_reg->vol_bit_width);
+
+	return val - anatop_reg->min_bit_val;
+}
+
+static int anatop_list_voltage(struct regulator_dev *reg, unsigned selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int uv;
+
+	uv = anatop_reg->min_voltage + selector * 25000;
+	dev_dbg(&reg->dev, "vddio = %d, selector = %u\n", uv, selector);
+
+	return uv;
+}
+
+static struct regulator_ops anatop_rops = {
+	.set_voltage     = anatop_set_voltage,
+	.get_voltage_sel = anatop_get_voltage_sel,
+	.list_voltage    = anatop_list_voltage,
+};
+
+static int __devinit anatop_regulator_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct regulator_desc *rdesc;
+	struct regulator_dev *rdev;
+	struct anatop_regulator *sreg;
+	struct regulator_init_data *initdata;
+	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
+	int ret = 0;
+
+	initdata = of_get_regulator_init_data(dev, np);
+	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
+	if (!sreg)
+		return -ENOMEM;
+	sreg->initdata = initdata;
+	sreg->name = kstrdup(of_get_property(np, "regulator-name", NULL),
+			     GFP_KERNEL);
+	rdesc = &sreg->rdesc;
+	memset(rdesc, 0, sizeof(*rdesc));
+	rdesc->name = sreg->name;
+	rdesc->ops = &anatop_rops;
+	rdesc->type = REGULATOR_VOLTAGE;
+	rdesc->owner = THIS_MODULE;
+	sreg->mfd = anatopmfd;
+	ret = of_property_read_u32(np, "reg", &sreg->control_reg);
+	if (ret) {
+		dev_err(dev, "no reg property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-vol-bit-width",
+				   &sreg->vol_bit_width);
+	if (ret) {
+		dev_err(dev, "no anatop-vol-bit-width property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
+				   &sreg->vol_bit_shift);
+	if (ret) {
+		dev_err(dev, "no anatop-vol-bit-shift property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-min-bit-val",
+				   &sreg->min_bit_val);
+	if (ret) {
+		dev_err(dev, "no anatop-min-bit-val property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-min-voltage",
+				   &sreg->min_voltage);
+	if (ret) {
+		dev_err(dev, "no anatop-min-voltage property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-max-voltage",
+				   &sreg->max_voltage);
+	if (ret) {
+		dev_err(dev, "no anatop-max-voltage property set\n");
+		goto anatop_probe_end;
+	}
+
+	/* register regulator */
+	rdev = regulator_register(rdesc, dev,
+				  initdata, sreg, pdev->dev.of_node);
+	if (IS_ERR(rdev)) {
+		dev_err(dev, "failed to register %s\n",
+			rdesc->name);
+		ret = PTR_ERR(rdev);
+		goto anatop_probe_end;
+	}
+
+	platform_set_drvdata(pdev, rdev);
+
+anatop_probe_end:
+	if (ret)
+		kfree(sreg->name);
+
+	return ret;
+}
+
+static int __devexit anatop_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
+	const char *name = sreg->name;
+
+	regulator_unregister(rdev);
+	kfree(name);
+
+	return 0;
+}
+
+static struct of_device_id __devinitdata of_anatop_regulator_match_tbl[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ /* end */ }
+};
+
+static struct platform_driver anatop_regulator = {
+	.driver = {
+		.name	= "anatop_regulator",
+		.owner  = THIS_MODULE,
+		.of_match_table = of_anatop_regulator_match_tbl,
+	},
+	.probe	= anatop_regulator_probe,
+	.remove	= anatop_regulator_remove,
+};
+
+static int __init anatop_regulator_init(void)
+{
+	return platform_driver_register(&anatop_regulator);
+}
+postcore_initcall(anatop_regulator_init);
+
+static void __exit anatop_regulator_exit(void)
+{
+	platform_driver_unregister(&anatop_regulator);
+}
+module_exit(anatop_regulator_exit);
+
+MODULE_AUTHOR("Nancy Chen <Nancy.Chen at freescale.com>, "
+	      "Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP Regulator driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.1



From viresh.kumar at st.com  Mon Mar 12 00:22:04 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:04 +0530
Subject: [PATCH V2 09/22] watchdog/mpcore_wdt: Set default heartbeat in probe
 instead of init
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <34c24fee0a69d3dd7fa82badb8af1dd66230d0f2.1331524811.git.viresh.kumar@st.com>

Currently mpcore_margin is handled in mpcore_wdt_init routine, which will be
called even if we haven't added any device for watchdog.

This patch moves this code into probe routine, so that it only gets hit once we
add device for this driver.

This also uses dev_info() style print statements instead of printk()

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/mpcore_wdt.c |   31 +++++++++++++++----------------
 1 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index 1c37109..19aaad7 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -222,6 +222,21 @@ static int __devinit mpcore_wdt_probe(struct platform_device *pdev)
 		goto err_register;
 	}
 
+	/*
+	 * Check that the mpcore_margin value is within it's range; if not reset
+	 * to the default
+	 */
+	if (mpcore_margin < MIN_TIME || mpcore_margin > MAX_TIME) {
+		mpcore_margin = TIMER_MARGIN;
+		dev_info(wdt->dev, "mpcore_margin value must be 0 < mpcore_margin < 65536, using %d\n",
+			TIMER_MARGIN);
+	}
+
+	mpcore_wdt_set_heartbeat(NULL, mpcore_margin);
+	dev_info(wdt->dev, "MPcore Watchdog Timer: 0.1. mpcore_noboot=%d "
+			"mpcore_margin=%d sec (nowayout= %d)\n", mpcore_noboot,
+			mpcore_margin, nowayout);
+
 	return 0;
 
 err_register:
@@ -279,24 +294,8 @@ static struct platform_driver mpcore_wdt_driver = {
 	},
 };
 
-static char banner[] __initdata = KERN_INFO "MPcore Watchdog Timer: 0.1. "
-		"mpcore_noboot=%d mpcore_margin=%d sec (nowayout= %d)\n";
-
 static int __init mpcore_wdt_init(void)
 {
-	/*
-	 * Check that the mpcore_margin value is within it's range;
-	 * if not reset to the default
-	 */
-	if (mpcore_margin < MIN_TIME || mpcore_margin > MAX_TIME) {
-		mpcore_margin = TIMER_MARGIN;
-		printk(KERN_INFO "mpcore_margin value must be 0 < mpcore_margin < 65536, using %d\n",
-				TIMER_MARGIN);
-	}
-
-	mpcore_wdt_set_heartbeat(NULL, mpcore_margin);
-	printk(banner, mpcore_noboot, mpcore_margin, nowayout);
-
 	return platform_driver_register(&mpcore_wdt_driver);
 }
 
-- 
1.7.8.110.g4cb5d



From thierry.reding at avionic-design.de  Fri Mar  9 01:31:16 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 9 Mar 2012 07:31:16 +0100
Subject: [PATCH 11/11] ARM: tegra: pcie: Add device tree support
In-Reply-To: <4F59253D.7070100@wwwdotorg.org>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-12-git-send-email-thierry.reding@avionic-design.de>
 <4F59253D.7070100@wwwdotorg.org>
Message-ID: <20120309063115.GA25208@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> On 03/08/2012 07:51 AM, Thierry Reding wrote:
> > This commit adds support for instantiating the Tegra PCIe controller
> > from a device tree.
> > 
> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> 
> > diff --git a/Documentation/devicetree/bindings/pci/tegra-pcie.txt b/Documentation/devicetree/bindings/pci/tegra-pcie.txt
> 
> > +NVIDIA Tegra PCIe controller
> > +
> > +Required properties:
> > +- compatible: "nvidia,tegra20-pcie"
> > +- reg: physical base address and length of the controller's registers
> > +- interrupts: the interrupt outputs of the controller
> > +
> > +Optional properties:
> > +- pex-clk-supply: supply voltage for internal reference clock
> > +- vdd-supply: power supply for controller (1.05V)
> 
> Mark, Liam,
> 
> Should those *-supply properties really be optional? I got the
> impression talking to Mark in a different thread that all regulators
> should exist, although their implementation may be via a fixed
> regulator, with no GPIO, as determined by the board design.

If I read the TrimSlice code correctly, there is no regulator setup required
to make PCIe work there presumably because they hardwire the proper voltages.
On the other hand, maybe a better solution in this case would be to use the
dummy regulator in those cases.

Thierry
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From viresh.kumar at st.com  Mon Mar 12 00:22:13 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 12 Mar 2012 09:52:13 +0530
Subject: [PATCH V2 18/22] watchdog/sp805: Fix documentation style comment
In-Reply-To: <cover.1331524811.git.viresh.kumar@st.com>
References: <cover.1331524811.git.viresh.kumar@st.com>
Message-ID: <9928ca5b3a445b49a693dd7be48e09359cda1c94.1331524811.git.viresh.kumar@st.com>

@ was missing before variables names, in their description. Also adev is
mentioned as dev in comment. Fix both these issues.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/sp805_wdt.c |   15 +++++++--------
 1 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index e2d5249..7af1386 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -56,14 +56,13 @@
 
 /**
  * struct sp805_wdt: sp805 wdt device structure
- *
- * lock: spin lock protecting dev structure and io access
- * base: base address of wdt
- * clk: clock structure of wdt
- * dev: amba device structure of wdt
- * status: current status of wdt
- * load_val: load value to be set for current timeout
- * timeout: current programmed timeout
+ * @lock: spin lock protecting dev structure and io access
+ * @base: base address of wdt
+ * @clk: clock structure of wdt
+ * @adev: amba device structure of wdt
+ * @status: current status of wdt
+ * @load_val: load value to be set for current timeout
+ * @timeout: current programmed timeout
  */
 struct sp805_wdt {
 	spinlock_t			lock;
-- 
1.7.8.110.g4cb5d



From stigge at antcom.de  Sun Mar 11 06:53:39 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 11 Mar 2012 11:53:39 +0100
Subject: [PATCH v7 4/4] USB: ohci-nxp: Remove i2c_write(), use smbus
In-Reply-To: <1331463219-23293-1-git-send-email-stigge@antcom.de>
References: <1331463219-23293-1-git-send-email-stigge@antcom.de>
Message-ID: <1331463219-23293-5-git-send-email-stigge@antcom.de>

This patch removes the re-coded i2c_write function from the ohci-nxp driver
in favour of using just smbus functions.

Signed-off-by: Roland Stigge <stigge at antcom.de>
---
 drivers/usb/host/ohci-nxp.c |   58 ++++++++++++++++++++++----------------------
 1 file changed, 29 insertions(+), 29 deletions(-)

--- linux-2.6.orig/drivers/usb/host/ohci-nxp.c
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -151,38 +151,36 @@ static struct i2c_driver isp1301_driver
 	.id_table = isp1301_id,
 };
 
-static void i2c_write(u8 buf, u8 subaddr)
-{
-	char tmpbuf[2];
-
-	tmpbuf[0] = subaddr;	/*register number */
-	tmpbuf[1] = buf;	/*register data */
-	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
-}
-
 static void isp1301_configure_pnx4008(void)
 {
 	/* PNX4008 only supports DAT_SE0 USB mode */
 	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
 	/* Power up externel charge-pump */
 
-	i2c_write(MC1_DAT_SE0 | MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
-	i2c_write(~(MC1_DAT_SE0 | MC1_SPEED_REG),
-		  ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL,
-		  ISP1301_I2C_MODE_CONTROL_2);
-	i2c_write(~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
-		  ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN,
-		  ISP1301_I2C_OTG_CONTROL_1);
-	i2c_write(~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
-		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0 | MC1_SPEED_REG);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
+		~(MC1_DAT_SE0 | MC1_SPEED_REG));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_2,
+		MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
+		~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_OTG_CONTROL_1, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
+		~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, 0xFF);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
+		0xFF);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR,
+		0xFF);
 }
 
 static void isp1301_configure_lpc32xx(void)
@@ -244,13 +242,15 @@ static void isp1301_configure(void)
 
 static inline void isp1301_vbus_on(void)
 {
-	i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1);
+	i2c_smbus_write_byte_data(isp1301_i2c_client, ISP1301_I2C_OTG_CONTROL_1,
+				  OTG1_VBUS_DRV);
 }
 
 static inline void isp1301_vbus_off(void)
 {
-	i2c_write(OTG1_VBUS_DRV,
-		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
+		OTG1_VBUS_DRV);
 }
 
 static void nxp_start_hc(void)


From stigge at antcom.de  Sun Mar 11 06:53:36 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 11 Mar 2012 11:53:36 +0100
Subject: [PATCH v7 1/4] USB: OHCI-HCD: Rename ohci-pnx4008 to ohci-nxp
In-Reply-To: <1331463219-23293-1-git-send-email-stigge@antcom.de>
References: <1331463219-23293-1-git-send-email-stigge@antcom.de>
Message-ID: <1331463219-23293-2-git-send-email-stigge@antcom.de>

Since this driver is compatible with several NXP devices, the driver is renamed
accordingly. Please combine with the following patch which also changes the
respective symbol names.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 drivers/usb/host/ohci-hcd.c     |    2 
 drivers/usb/host/ohci-nxp.c     |  453 ++++++++++++++++++++++++++++++++++++++++
 drivers/usb/host/ohci-pnx4008.c |  453 ----------------------------------------
 3 files changed, 454 insertions(+), 454 deletions(-)

--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1051,7 +1051,7 @@ MODULE_LICENSE ("GPL");
 #endif
 
 #ifdef CONFIG_ARCH_PNX4008
-#include "ohci-pnx4008.c"
+#include "ohci-nxp.c"
 #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
 #endif
 
--- /dev/null
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -0,0 +1,453 @@
+/*
+ * drivers/usb/host/ohci-pnx4008.c
+ *
+ * driver for Philips PNX4008 USB Host
+ *
+ * Authors: Dmitry Chigirev <source at mvista.com>
+ *	    Vitaly Wool <vitalywool at gmail.com>
+ *
+ * register initialization is based on code examples provided by Philips
+ * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
+ *
+ * NOTE: This driver does not have suspend/resume functionality
+ * This driver is intended for engineering development purposes only
+ *
+ * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+
+#include <mach/platform.h>
+#include <mach/irqs.h>
+#include <asm/gpio.h>
+
+#define USB_CTRL	IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64)
+
+/* USB_CTRL bit defines */
+#define USB_SLAVE_HCLK_EN	(1 << 24)
+#define USB_HOST_NEED_CLK_EN	(1 << 21)
+
+#define USB_OTG_CLK_CTRL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF4)
+#define USB_OTG_CLK_STAT	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF8)
+
+/* USB_OTG_CLK_CTRL bit defines */
+#define AHB_M_CLOCK_ON		(1 << 4)
+#define OTG_CLOCK_ON		(1 << 3)
+#define I2C_CLOCK_ON		(1 << 2)
+#define DEV_CLOCK_ON		(1 << 1)
+#define HOST_CLOCK_ON		(1 << 0)
+
+#define USB_OTG_STAT_CONTROL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x110)
+
+/* USB_OTG_STAT_CONTROL bit defines */
+#define TRANSPARENT_I2C_EN	(1 << 7)
+#define HOST_EN			(1 << 0)
+
+/* ISP1301 USB transceiver I2C registers */
+#define	ISP1301_MODE_CONTROL_1		0x04	/* u8 read, set, +1 clear */
+
+#define	MC1_SPEED_REG		(1 << 0)
+#define	MC1_SUSPEND_REG		(1 << 1)
+#define	MC1_DAT_SE0		(1 << 2)
+#define	MC1_TRANSPARENT		(1 << 3)
+#define	MC1_BDIS_ACON_EN	(1 << 4)
+#define	MC1_OE_INT_EN		(1 << 5)
+#define	MC1_UART_EN		(1 << 6)
+#define	MC1_MASK		0x7f
+
+#define	ISP1301_MODE_CONTROL_2		0x12	/* u8 read, set, +1 clear */
+
+#define	MC2_GLOBAL_PWR_DN	(1 << 0)
+#define	MC2_SPD_SUSP_CTRL	(1 << 1)
+#define	MC2_BI_DI		(1 << 2)
+#define	MC2_TRANSP_BDIR0	(1 << 3)
+#define	MC2_TRANSP_BDIR1	(1 << 4)
+#define	MC2_AUDIO_EN		(1 << 5)
+#define	MC2_PSW_EN		(1 << 6)
+#define	MC2_EN2V7		(1 << 7)
+
+#define	ISP1301_OTG_CONTROL_1		0x06	/* u8 read, set, +1 clear */
+#	define	OTG1_DP_PULLUP		(1 << 0)
+#	define	OTG1_DM_PULLUP		(1 << 1)
+#	define	OTG1_DP_PULLDOWN	(1 << 2)
+#	define	OTG1_DM_PULLDOWN	(1 << 3)
+#	define	OTG1_ID_PULLDOWN	(1 << 4)
+#	define	OTG1_VBUS_DRV		(1 << 5)
+#	define	OTG1_VBUS_DISCHRG	(1 << 6)
+#	define	OTG1_VBUS_CHRG		(1 << 7)
+#define	ISP1301_OTG_STATUS		0x10	/* u8 readonly */
+#	define	OTG_B_SESS_END		(1 << 6)
+#	define	OTG_B_SESS_VLD		(1 << 7)
+
+#define ISP1301_I2C_ADDR 0x2C
+
+#define ISP1301_I2C_MODE_CONTROL_1 0x4
+#define ISP1301_I2C_MODE_CONTROL_2 0x12
+#define ISP1301_I2C_OTG_CONTROL_1 0x6
+#define ISP1301_I2C_OTG_CONTROL_2 0x10
+#define ISP1301_I2C_INTERRUPT_SOURCE 0x8
+#define ISP1301_I2C_INTERRUPT_LATCH 0xA
+#define ISP1301_I2C_INTERRUPT_FALLING 0xC
+#define ISP1301_I2C_INTERRUPT_RISING 0xE
+#define ISP1301_I2C_REG_CLEAR_ADDR 1
+
+static struct i2c_driver isp1301_driver;
+static struct i2c_client *isp1301_i2c_client;
+
+extern int usb_disabled(void);
+extern int ocpi_enable(void);
+
+static struct clk *usb_clk;
+
+static const unsigned short normal_i2c[] =
+    { ISP1301_I2C_ADDR, ISP1301_I2C_ADDR + 1, I2C_CLIENT_END };
+
+static int isp1301_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	return 0;
+}
+
+static int isp1301_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+static const struct i2c_device_id isp1301_id[] = {
+	{ "isp1301_pnx", 0 },
+	{ }
+};
+
+static struct i2c_driver isp1301_driver = {
+	.driver = {
+		.name = "isp1301_pnx",
+	},
+	.probe = isp1301_probe,
+	.remove = isp1301_remove,
+	.id_table = isp1301_id,
+};
+
+static void i2c_write(u8 buf, u8 subaddr)
+{
+	char tmpbuf[2];
+
+	tmpbuf[0] = subaddr;	/*register number */
+	tmpbuf[1] = buf;	/*register data */
+	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
+}
+
+static void isp1301_configure(void)
+{
+	/* PNX4008 only supports DAT_SE0 USB mode */
+	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
+	/* Power up externel charge-pump */
+
+	i2c_write(MC1_DAT_SE0 | MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
+	i2c_write(~(MC1_DAT_SE0 | MC1_SPEED_REG),
+		  ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL,
+		  ISP1301_I2C_MODE_CONTROL_2);
+	i2c_write(~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
+		  ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN,
+		  ISP1301_I2C_OTG_CONTROL_1);
+	i2c_write(~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
+		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(0xFF,
+		  ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(0xFF,
+		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(0xFF,
+		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+
+}
+
+static inline void isp1301_vbus_on(void)
+{
+	i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1);
+}
+
+static inline void isp1301_vbus_off(void)
+{
+	i2c_write(OTG1_VBUS_DRV,
+		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
+}
+
+static void pnx4008_start_hc(void)
+{
+	unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
+	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
+	isp1301_vbus_on();
+}
+
+static void pnx4008_stop_hc(void)
+{
+	unsigned long tmp;
+	isp1301_vbus_off();
+	tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN;
+	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
+}
+
+static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd)
+{
+	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+	int ret;
+
+	if ((ret = ohci_init(ohci)) < 0)
+		return ret;
+
+	if ((ret = ohci_run(ohci)) < 0) {
+		dev_err(hcd->self.controller, "can't start\n");
+		ohci_stop(hcd);
+		return ret;
+	}
+	return 0;
+}
+
+static const struct hc_driver ohci_pnx4008_hc_driver = {
+	.description = hcd_name,
+	.product_desc =		"pnx4008 OHCI",
+
+	/*
+	 * generic hardware linkage
+	 */
+	.irq = ohci_irq,
+	.flags = HCD_USB11 | HCD_MEMORY,
+
+	.hcd_priv_size =	sizeof(struct ohci_hcd),
+	/*
+	 * basic lifecycle operations
+	 */
+	.start = ohci_pnx4008_start,
+	.stop = ohci_stop,
+	.shutdown = ohci_shutdown,
+
+	/*
+	 * managing i/o requests and associated device resources
+	 */
+	.urb_enqueue = ohci_urb_enqueue,
+	.urb_dequeue = ohci_urb_dequeue,
+	.endpoint_disable = ohci_endpoint_disable,
+
+	/*
+	 * scheduling support
+	 */
+	.get_frame_number = ohci_get_frame,
+
+	/*
+	 * root hub support
+	 */
+	.hub_status_data = ohci_hub_status_data,
+	.hub_control = ohci_hub_control,
+#ifdef	CONFIG_PM
+	.bus_suspend = ohci_bus_suspend,
+	.bus_resume = ohci_bus_resume,
+#endif
+	.start_port_reset = ohci_start_port_reset,
+};
+
+#define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON)
+
+static void pnx4008_set_usb_bits(void)
+{
+	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
+	start_int_ack(SE_USB_OTG_ATX_INT_N);
+	start_int_umask(SE_USB_OTG_ATX_INT_N);
+
+	start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
+	start_int_ack(SE_USB_OTG_TIMER_INT);
+	start_int_umask(SE_USB_OTG_TIMER_INT);
+
+	start_int_set_rising_edge(SE_USB_I2C_INT);
+	start_int_ack(SE_USB_I2C_INT);
+	start_int_umask(SE_USB_I2C_INT);
+
+	start_int_set_rising_edge(SE_USB_INT);
+	start_int_ack(SE_USB_INT);
+	start_int_umask(SE_USB_INT);
+
+	start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
+	start_int_ack(SE_USB_NEED_CLK_INT);
+	start_int_umask(SE_USB_NEED_CLK_INT);
+
+	start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
+	start_int_ack(SE_USB_AHB_NEED_CLK_INT);
+	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+}
+
+static void pnx4008_unset_usb_bits(void)
+{
+	start_int_mask(SE_USB_OTG_ATX_INT_N);
+	start_int_mask(SE_USB_OTG_TIMER_INT);
+	start_int_mask(SE_USB_I2C_INT);
+	start_int_mask(SE_USB_INT);
+	start_int_mask(SE_USB_NEED_CLK_INT);
+	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+}
+
+static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = 0;
+	struct ohci_hcd *ohci;
+	const struct hc_driver *driver = &ohci_pnx4008_hc_driver;
+	struct i2c_adapter *i2c_adap;
+	struct i2c_board_info i2c_info;
+
+	int ret = 0, irq;
+
+	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (pnx4008)\n", hcd_name);
+	if (usb_disabled()) {
+		err("USB is disabled");
+		ret = -ENODEV;
+		goto out;
+	}
+
+	if (pdev->num_resources != 2
+	    || pdev->resource[0].flags != IORESOURCE_MEM
+	    || pdev->resource[1].flags != IORESOURCE_IRQ) {
+		err("Invalid resource configuration");
+		ret = -ENODEV;
+		goto out;
+	}
+
+	/* Enable AHB slave USB clock, needed for further USB clock control */
+	__raw_writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
+
+	ret = i2c_add_driver(&isp1301_driver);
+	if (ret < 0) {
+		err("failed to add ISP1301 driver");
+		goto out;
+	}
+	i2c_adap = i2c_get_adapter(2);
+	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
+	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
+	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
+						   normal_i2c, NULL);
+	i2c_put_adapter(i2c_adap);
+	if (!isp1301_i2c_client) {
+		err("failed to connect I2C to ISP1301 USB Transceiver");
+		ret = -ENODEV;
+		goto out_i2c_driver;
+	}
+
+	isp1301_configure();
+
+	/* Enable USB PLL */
+	usb_clk = clk_get(&pdev->dev, "ck_pll5");
+	if (IS_ERR(usb_clk)) {
+		err("failed to acquire USB PLL");
+		ret = PTR_ERR(usb_clk);
+		goto out1;
+	}
+
+	ret = clk_enable(usb_clk);
+	if (ret < 0) {
+		err("failed to start USB PLL");
+		goto out2;
+	}
+
+	ret = clk_set_rate(usb_clk, 48000);
+	if (ret < 0) {
+		err("failed to set USB clock rate");
+		goto out3;
+	}
+
+	__raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL);
+
+	/* Set to enable all needed USB clocks */
+	__raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL);
+
+	while ((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) !=
+	       USB_CLOCK_MASK) ;
+
+	hcd = usb_create_hcd (driver, &pdev->dev, dev_name(&pdev->dev));
+	if (!hcd) {
+		err("Failed to allocate HC buffer");
+		ret = -ENOMEM;
+		goto out3;
+	}
+
+	/* Set all USB bits in the Start Enable register */
+	pnx4008_set_usb_bits();
+
+	hcd->rsrc_start = pdev->resource[0].start;
+	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
+	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+		dev_dbg(&pdev->dev, "request_mem_region failed\n");
+		ret =  -ENOMEM;
+		goto out4;
+	}
+	hcd->regs = (void __iomem *)pdev->resource[0].start;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		ret = -ENXIO;
+		goto out4;
+	}
+
+	pnx4008_start_hc();
+	platform_set_drvdata(pdev, hcd);
+	ohci = hcd_to_ohci(hcd);
+	ohci_hcd_init(ohci);
+
+	dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq);
+	ret = usb_add_hcd(hcd, irq, 0);
+	if (ret == 0)
+		return ret;
+
+	pnx4008_stop_hc();
+out4:
+	pnx4008_unset_usb_bits();
+	usb_put_hcd(hcd);
+out3:
+	clk_disable(usb_clk);
+out2:
+	clk_put(usb_clk);
+out1:
+	i2c_unregister_device(isp1301_i2c_client);
+	isp1301_i2c_client = NULL;
+out_i2c_driver:
+	i2c_del_driver(&isp1301_driver);
+out:
+	return ret;
+}
+
+static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+	usb_remove_hcd(hcd);
+	pnx4008_stop_hc();
+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+	usb_put_hcd(hcd);
+	pnx4008_unset_usb_bits();
+	clk_disable(usb_clk);
+	clk_put(usb_clk);
+	i2c_unregister_device(isp1301_i2c_client);
+	isp1301_i2c_client = NULL;
+	i2c_del_driver(&isp1301_driver);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+/* work with hotplug and coldplug */
+MODULE_ALIAS("platform:usb-ohci");
+
+static struct platform_driver usb_hcd_pnx4008_driver = {
+	.driver = {
+		.name = "usb-ohci",
+		.owner	= THIS_MODULE,
+	},
+	.probe = usb_hcd_pnx4008_probe,
+	.remove = usb_hcd_pnx4008_remove,
+};
+
--- linux-2.6.orig/drivers/usb/host/ohci-pnx4008.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * drivers/usb/host/ohci-pnx4008.c
- *
- * driver for Philips PNX4008 USB Host
- *
- * Authors: Dmitry Chigirev <source at mvista.com>
- *	    Vitaly Wool <vitalywool at gmail.com>
- *
- * register initialization is based on code examples provided by Philips
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * NOTE: This driver does not have suspend/resume functionality
- * This driver is intended for engineering development purposes only
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-
-#include <mach/hardware.h>
-#include <asm/io.h>
-
-#include <mach/platform.h>
-#include <mach/irqs.h>
-#include <asm/gpio.h>
-
-#define USB_CTRL	IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64)
-
-/* USB_CTRL bit defines */
-#define USB_SLAVE_HCLK_EN	(1 << 24)
-#define USB_HOST_NEED_CLK_EN	(1 << 21)
-
-#define USB_OTG_CLK_CTRL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF4)
-#define USB_OTG_CLK_STAT	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF8)
-
-/* USB_OTG_CLK_CTRL bit defines */
-#define AHB_M_CLOCK_ON		(1 << 4)
-#define OTG_CLOCK_ON		(1 << 3)
-#define I2C_CLOCK_ON		(1 << 2)
-#define DEV_CLOCK_ON		(1 << 1)
-#define HOST_CLOCK_ON		(1 << 0)
-
-#define USB_OTG_STAT_CONTROL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x110)
-
-/* USB_OTG_STAT_CONTROL bit defines */
-#define TRANSPARENT_I2C_EN	(1 << 7)
-#define HOST_EN			(1 << 0)
-
-/* ISP1301 USB transceiver I2C registers */
-#define	ISP1301_MODE_CONTROL_1		0x04	/* u8 read, set, +1 clear */
-
-#define	MC1_SPEED_REG		(1 << 0)
-#define	MC1_SUSPEND_REG		(1 << 1)
-#define	MC1_DAT_SE0		(1 << 2)
-#define	MC1_TRANSPARENT		(1 << 3)
-#define	MC1_BDIS_ACON_EN	(1 << 4)
-#define	MC1_OE_INT_EN		(1 << 5)
-#define	MC1_UART_EN		(1 << 6)
-#define	MC1_MASK		0x7f
-
-#define	ISP1301_MODE_CONTROL_2		0x12	/* u8 read, set, +1 clear */
-
-#define	MC2_GLOBAL_PWR_DN	(1 << 0)
-#define	MC2_SPD_SUSP_CTRL	(1 << 1)
-#define	MC2_BI_DI		(1 << 2)
-#define	MC2_TRANSP_BDIR0	(1 << 3)
-#define	MC2_TRANSP_BDIR1	(1 << 4)
-#define	MC2_AUDIO_EN		(1 << 5)
-#define	MC2_PSW_EN		(1 << 6)
-#define	MC2_EN2V7		(1 << 7)
-
-#define	ISP1301_OTG_CONTROL_1		0x06	/* u8 read, set, +1 clear */
-#	define	OTG1_DP_PULLUP		(1 << 0)
-#	define	OTG1_DM_PULLUP		(1 << 1)
-#	define	OTG1_DP_PULLDOWN	(1 << 2)
-#	define	OTG1_DM_PULLDOWN	(1 << 3)
-#	define	OTG1_ID_PULLDOWN	(1 << 4)
-#	define	OTG1_VBUS_DRV		(1 << 5)
-#	define	OTG1_VBUS_DISCHRG	(1 << 6)
-#	define	OTG1_VBUS_CHRG		(1 << 7)
-#define	ISP1301_OTG_STATUS		0x10	/* u8 readonly */
-#	define	OTG_B_SESS_END		(1 << 6)
-#	define	OTG_B_SESS_VLD		(1 << 7)
-
-#define ISP1301_I2C_ADDR 0x2C
-
-#define ISP1301_I2C_MODE_CONTROL_1 0x4
-#define ISP1301_I2C_MODE_CONTROL_2 0x12
-#define ISP1301_I2C_OTG_CONTROL_1 0x6
-#define ISP1301_I2C_OTG_CONTROL_2 0x10
-#define ISP1301_I2C_INTERRUPT_SOURCE 0x8
-#define ISP1301_I2C_INTERRUPT_LATCH 0xA
-#define ISP1301_I2C_INTERRUPT_FALLING 0xC
-#define ISP1301_I2C_INTERRUPT_RISING 0xE
-#define ISP1301_I2C_REG_CLEAR_ADDR 1
-
-static struct i2c_driver isp1301_driver;
-static struct i2c_client *isp1301_i2c_client;
-
-extern int usb_disabled(void);
-extern int ocpi_enable(void);
-
-static struct clk *usb_clk;
-
-static const unsigned short normal_i2c[] =
-    { ISP1301_I2C_ADDR, ISP1301_I2C_ADDR + 1, I2C_CLIENT_END };
-
-static int isp1301_probe(struct i2c_client *client,
-			 const struct i2c_device_id *id)
-{
-	return 0;
-}
-
-static int isp1301_remove(struct i2c_client *client)
-{
-	return 0;
-}
-
-static const struct i2c_device_id isp1301_id[] = {
-	{ "isp1301_pnx", 0 },
-	{ }
-};
-
-static struct i2c_driver isp1301_driver = {
-	.driver = {
-		.name = "isp1301_pnx",
-	},
-	.probe = isp1301_probe,
-	.remove = isp1301_remove,
-	.id_table = isp1301_id,
-};
-
-static void i2c_write(u8 buf, u8 subaddr)
-{
-	char tmpbuf[2];
-
-	tmpbuf[0] = subaddr;	/*register number */
-	tmpbuf[1] = buf;	/*register data */
-	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
-}
-
-static void isp1301_configure(void)
-{
-	/* PNX4008 only supports DAT_SE0 USB mode */
-	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
-	/* Power up externel charge-pump */
-
-	i2c_write(MC1_DAT_SE0 | MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
-	i2c_write(~(MC1_DAT_SE0 | MC1_SPEED_REG),
-		  ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL,
-		  ISP1301_I2C_MODE_CONTROL_2);
-	i2c_write(~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
-		  ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN,
-		  ISP1301_I2C_OTG_CONTROL_1);
-	i2c_write(~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
-		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
-
-}
-
-static inline void isp1301_vbus_on(void)
-{
-	i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1);
-}
-
-static inline void isp1301_vbus_off(void)
-{
-	i2c_write(OTG1_VBUS_DRV,
-		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-}
-
-static void pnx4008_start_hc(void)
-{
-	unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
-	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
-	isp1301_vbus_on();
-}
-
-static void pnx4008_stop_hc(void)
-{
-	unsigned long tmp;
-	isp1301_vbus_off();
-	tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN;
-	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
-}
-
-static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd)
-{
-	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
-	int ret;
-
-	if ((ret = ohci_init(ohci)) < 0)
-		return ret;
-
-	if ((ret = ohci_run(ohci)) < 0) {
-		dev_err(hcd->self.controller, "can't start\n");
-		ohci_stop(hcd);
-		return ret;
-	}
-	return 0;
-}
-
-static const struct hc_driver ohci_pnx4008_hc_driver = {
-	.description = hcd_name,
-	.product_desc =		"pnx4008 OHCI",
-
-	/*
-	 * generic hardware linkage
-	 */
-	.irq = ohci_irq,
-	.flags = HCD_USB11 | HCD_MEMORY,
-
-	.hcd_priv_size =	sizeof(struct ohci_hcd),
-	/*
-	 * basic lifecycle operations
-	 */
-	.start = ohci_pnx4008_start,
-	.stop = ohci_stop,
-	.shutdown = ohci_shutdown,
-
-	/*
-	 * managing i/o requests and associated device resources
-	 */
-	.urb_enqueue = ohci_urb_enqueue,
-	.urb_dequeue = ohci_urb_dequeue,
-	.endpoint_disable = ohci_endpoint_disable,
-
-	/*
-	 * scheduling support
-	 */
-	.get_frame_number = ohci_get_frame,
-
-	/*
-	 * root hub support
-	 */
-	.hub_status_data = ohci_hub_status_data,
-	.hub_control = ohci_hub_control,
-#ifdef	CONFIG_PM
-	.bus_suspend = ohci_bus_suspend,
-	.bus_resume = ohci_bus_resume,
-#endif
-	.start_port_reset = ohci_start_port_reset,
-};
-
-#define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON)
-
-static void pnx4008_set_usb_bits(void)
-{
-	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-	start_int_ack(SE_USB_OTG_ATX_INT_N);
-	start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-	start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-	start_int_ack(SE_USB_OTG_TIMER_INT);
-	start_int_umask(SE_USB_OTG_TIMER_INT);
-
-	start_int_set_rising_edge(SE_USB_I2C_INT);
-	start_int_ack(SE_USB_I2C_INT);
-	start_int_umask(SE_USB_I2C_INT);
-
-	start_int_set_rising_edge(SE_USB_INT);
-	start_int_ack(SE_USB_INT);
-	start_int_umask(SE_USB_INT);
-
-	start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-	start_int_ack(SE_USB_NEED_CLK_INT);
-	start_int_umask(SE_USB_NEED_CLK_INT);
-
-	start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-	start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
-}
-
-static void pnx4008_unset_usb_bits(void)
-{
-	start_int_mask(SE_USB_OTG_ATX_INT_N);
-	start_int_mask(SE_USB_OTG_TIMER_INT);
-	start_int_mask(SE_USB_I2C_INT);
-	start_int_mask(SE_USB_INT);
-	start_int_mask(SE_USB_NEED_CLK_INT);
-	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
-}
-
-static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
-{
-	struct usb_hcd *hcd = 0;
-	struct ohci_hcd *ohci;
-	const struct hc_driver *driver = &ohci_pnx4008_hc_driver;
-	struct i2c_adapter *i2c_adap;
-	struct i2c_board_info i2c_info;
-
-	int ret = 0, irq;
-
-	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (pnx4008)\n", hcd_name);
-	if (usb_disabled()) {
-		err("USB is disabled");
-		ret = -ENODEV;
-		goto out;
-	}
-
-	if (pdev->num_resources != 2
-	    || pdev->resource[0].flags != IORESOURCE_MEM
-	    || pdev->resource[1].flags != IORESOURCE_IRQ) {
-		err("Invalid resource configuration");
-		ret = -ENODEV;
-		goto out;
-	}
-
-	/* Enable AHB slave USB clock, needed for further USB clock control */
-	__raw_writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
-
-	ret = i2c_add_driver(&isp1301_driver);
-	if (ret < 0) {
-		err("failed to add ISP1301 driver");
-		goto out;
-	}
-	i2c_adap = i2c_get_adapter(2);
-	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
-	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
-	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
-						   normal_i2c, NULL);
-	i2c_put_adapter(i2c_adap);
-	if (!isp1301_i2c_client) {
-		err("failed to connect I2C to ISP1301 USB Transceiver");
-		ret = -ENODEV;
-		goto out_i2c_driver;
-	}
-
-	isp1301_configure();
-
-	/* Enable USB PLL */
-	usb_clk = clk_get(&pdev->dev, "ck_pll5");
-	if (IS_ERR(usb_clk)) {
-		err("failed to acquire USB PLL");
-		ret = PTR_ERR(usb_clk);
-		goto out1;
-	}
-
-	ret = clk_enable(usb_clk);
-	if (ret < 0) {
-		err("failed to start USB PLL");
-		goto out2;
-	}
-
-	ret = clk_set_rate(usb_clk, 48000);
-	if (ret < 0) {
-		err("failed to set USB clock rate");
-		goto out3;
-	}
-
-	__raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL);
-
-	/* Set to enable all needed USB clocks */
-	__raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL);
-
-	while ((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) !=
-	       USB_CLOCK_MASK) ;
-
-	hcd = usb_create_hcd (driver, &pdev->dev, dev_name(&pdev->dev));
-	if (!hcd) {
-		err("Failed to allocate HC buffer");
-		ret = -ENOMEM;
-		goto out3;
-	}
-
-	/* Set all USB bits in the Start Enable register */
-	pnx4008_set_usb_bits();
-
-	hcd->rsrc_start = pdev->resource[0].start;
-	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
-	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
-		dev_dbg(&pdev->dev, "request_mem_region failed\n");
-		ret =  -ENOMEM;
-		goto out4;
-	}
-	hcd->regs = (void __iomem *)pdev->resource[0].start;
-
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
-		ret = -ENXIO;
-		goto out4;
-	}
-
-	pnx4008_start_hc();
-	platform_set_drvdata(pdev, hcd);
-	ohci = hcd_to_ohci(hcd);
-	ohci_hcd_init(ohci);
-
-	dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq);
-	ret = usb_add_hcd(hcd, irq, 0);
-	if (ret == 0)
-		return ret;
-
-	pnx4008_stop_hc();
-out4:
-	pnx4008_unset_usb_bits();
-	usb_put_hcd(hcd);
-out3:
-	clk_disable(usb_clk);
-out2:
-	clk_put(usb_clk);
-out1:
-	i2c_unregister_device(isp1301_i2c_client);
-	isp1301_i2c_client = NULL;
-out_i2c_driver:
-	i2c_del_driver(&isp1301_driver);
-out:
-	return ret;
-}
-
-static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
-{
-	struct usb_hcd *hcd = platform_get_drvdata(pdev);
-
-	usb_remove_hcd(hcd);
-	pnx4008_stop_hc();
-	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-	usb_put_hcd(hcd);
-	pnx4008_unset_usb_bits();
-	clk_disable(usb_clk);
-	clk_put(usb_clk);
-	i2c_unregister_device(isp1301_i2c_client);
-	isp1301_i2c_client = NULL;
-	i2c_del_driver(&isp1301_driver);
-
-	platform_set_drvdata(pdev, NULL);
-
-	return 0;
-}
-
-/* work with hotplug and coldplug */
-MODULE_ALIAS("platform:usb-ohci");
-
-static struct platform_driver usb_hcd_pnx4008_driver = {
-	.driver = {
-		.name = "usb-ohci",
-		.owner	= THIS_MODULE,
-	},
-	.probe = usb_hcd_pnx4008_probe,
-	.remove = usb_hcd_pnx4008_remove,
-};
-


From linus.walleij at stericsson.com  Mon Mar 12 16:41:10 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 12 Mar 2012 21:41:10 +0100
Subject: [PATCH] pinctrl: fix error path in pinconf_map_to_setting()
Message-ID: <1331584870-10077-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

The code was using the union member
setting->data.configs.group_or_pin to store a potential
error code, but since that member is unsigned the
< 0 comparison was not true, letting errors pass thru,
ending up as mapped to pin "-22". Fix this up and print
the error.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/pinconf.c |   27 +++++++++++++++++----------
 1 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 247b9f2..f9c9cd1 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -282,21 +282,28 @@ int pinconf_map_to_setting(struct pinctrl_map const *map,
 			  struct pinctrl_setting *setting)
 {
 	struct pinctrl_dev *pctldev = setting->pctldev;
+	int ret;
 
 	switch (setting->type) {
 	case PIN_MAP_TYPE_CONFIGS_PIN:
-		setting->data.configs.group_or_pin =
-			pin_get_from_name(pctldev,
-					  map->data.configs.group_or_pin);
-		if (setting->data.configs.group_or_pin < 0)
-			return setting->data.configs.group_or_pin;
+		ret = pin_get_from_name(pctldev,
+					map->data.configs.group_or_pin);
+		if (ret < 0) {
+			dev_err(pctldev->dev, "could not map pin config for \"%s\"",
+				map->data.configs.group_or_pin);
+			return ret;
+		}
+		setting->data.configs.group_or_pin = ret;
 		break;
 	case PIN_MAP_TYPE_CONFIGS_GROUP:
-		setting->data.configs.group_or_pin =
-			pinctrl_get_group_selector(pctldev,
-					map->data.configs.group_or_pin);
-		if (setting->data.configs.group_or_pin < 0)
-			return setting->data.configs.group_or_pin;
+		ret = pinctrl_get_group_selector(pctldev,
+					 map->data.configs.group_or_pin);
+		if (ret < 0) {
+			dev_err(pctldev->dev, "could not map group config for \"%s\"",
+				map->data.configs.group_or_pin);
+			return ret;
+		}
+		setting->data.configs.group_or_pin = ret;
 		break;
 	default:
 		return -EINVAL;
-- 
1.7.8



From thierry.reding at avionic-design.de  Mon Mar 12 10:28:58 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Mon, 12 Mar 2012 15:28:58 +0100
Subject: [PATCH 11/11] ARM: tegra: pcie: Add device tree support
In-Reply-To: <20120312142340.GI3110@opensource.wolfsonmicro.com>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-12-git-send-email-thierry.reding@avionic-design.de>
 <4F59253D.7070100@wwwdotorg.org>
 <20120312120610.GA14020@sirena.org.uk>
 <20120312141705.GA16395@avionic-0098.mockup.avionic-design.de>
 <20120312142340.GI3110@opensource.wolfsonmicro.com>
Message-ID: <20120312142857.GA6694@avionic-0098.mockup.avionic-design.de>

* Mark Brown wrote:
> On Mon, Mar 12, 2012 at 03:17:05PM +0100, Thierry Reding wrote:
> 
> > My understanding of the fixed regulator was that it was meant to be used for
> > fixed voltage supplies that can still be enabled or disabled (for example as
> > supplied by a GPIO) but not regulators that are fix in the sense that they
> > cannot be enabled or disabled at all but are always on.
> 
> No, not at all.  It's for any random supply that doesn't have much
> meaningful control - as you'll see from the code the GPIO is totally
> optional if you look at the git history you'll see that the GPIO was
> added some time after the driver was originally merged.
> 
> > Is that how it is supposed to work?
> 
> Yes.

In that case I'll mark the *-supply properties required. Would it be a good
idea to mention this (or even give an example with fixed regulators) in the
binding documentation or can I assume this to be common knowledge?

Thierry
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From swarren at wwwdotorg.org  Mon Mar 12 17:04:43 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 12 Mar 2012 15:04:43 -0600
Subject: [PATCH] pinctrl: fix error path in pinconf_map_to_setting()
In-Reply-To: <1331584870-10077-1-git-send-email-linus.walleij@stericsson.com>
References: <1331584870-10077-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <4F5E64EB.6050200@wwwdotorg.org>

On 03/12/2012 02:41 PM, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> The code was using the union member
> setting->data.configs.group_or_pin to store a potential
> error code, but since that member is unsigned the
> < 0 comparison was not true, letting errors pass thru,

"thru" is a pet peeve of mine; it'd be great to spell this correctly as
"through".

> ending up as mapped to pin "-22". Fix this up and print
> the error.

Oops. Sorry about that.

> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
...
> -		setting->data.configs.group_or_pin =
> -			pin_get_from_name(pctldev,
> -					  map->data.configs.group_or_pin);
> -		if (setting->data.configs.group_or_pin < 0)
> -			return setting->data.configs.group_or_pin;
> +		ret = pin_get_from_name(pctldev,
> +					map->data.configs.group_or_pin);
> +		if (ret < 0) {

"ret" here is named "pin" other places pin_get_from_name() is called,
and that naming seems to make a bit more sense here too.

Otherwise,
Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From t-kristo at ti.com  Mon Mar 12 05:19:08 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Mon, 12 Mar 2012 11:19:08 +0200
Subject: [PATCHv5 2/6] ARM: OMAP3 PM: Move IO Daisychain function to
 omap3 prm file
In-Reply-To: <4F5D8EBA.3060602@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-3-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203091737390.30879@utopia.booyaka.com>
 <4F5D8EBA.3060602@ti.com>
Message-ID: <1331543948.2116.259.camel@sokoban>

On Mon, 2012-03-12 at 11:20 +0530, Rajendra Nayak wrote:
> On Saturday 10 March 2012 06:10 AM, Paul Walmsley wrote:
> > cc Rajendra
> >
> > Hi Tero,
> >
> > a few comments:
> >
> > On Tue, 6 Mar 2012, Tero Kristo wrote:
> >
> > ...
> >
> >> +/* OMAP3 Daisychain enable sequence */
> >> +void omap3_trigger_io_chain(void)
> >> +{
> >> +	int i = 0;
> >> +
> >> +	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> >> +				   PM_WKEN);
> >> +	/* Do a readback to assure write has been done */
> >> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
> >
> > Looks like this barrier shouldn't be needed?  The write is immediately
> > followed by another read from the same IP block.

I think you are right here, this can be dropped.

> >
> >> +
> >> +	omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST)&
> >> +			  OMAP3430_ST_IO_CHAIN_MASK,
> >> +			  MAX_IOPAD_LATCH_TIME, i);
> >> +
> >> +	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> >> +				     PM_WKEN);
> >> +
> >> +	omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
> >> +				     PM_WKST);
> >> +
> >> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
> >> +}
> >
> > I see that you removed the second timeout test from this code, but not
> > from the OMAP4 version.  Any reason why?  Seems like if the second timeout
> > can be removed from one, then it can also be removed from the other?
> 
> Actually FWIK, its nteeded in both OMAP3 and OMAP4. The OMAP3
> documentation does no mention about it. but that is just bad
> documentation.

Both documentation and actual functionality appears to be different for
OMAP3 / OMAP4. The status bit on OMAP3 is read / write, and writing 1 to
it clears it. On OMAP4, it is read only and both values 0 / 1 indicate
something has happened. On OMAP3 the bit must be cleared by writing 1 to
it, otherwise it remains high indefinitely and will break all the
subsequent trigger calls. Also, clearing EN_IO_CHAIN on OMAP3 does not
appear to trigger any activity that would change the status of
ST_IO_CHAIN, so there is nothing to poll at the end.

Here is a sample trace I just generated for the trigger on OMAP3:

[    7.707824] omap3_trigger_io_chain(1): PM_WKST=00000000
[    7.707855] omap3_trigger_io_chain(2): PM_WKST=00000000
[    7.707855] omap3_trigger_io_chain(3): PM_WKST=00010000
[    7.707885] omap3_trigger_io_chain(4): PM_WKST=00000000
[    7.707977] omap3_trigger_io_chain(5): PM_WKST=00000000

1 = enter trigger function
2 = just after enabling io chain
3 = just after first poll loop
4 = just after clear of io status and disabling of io chain
5 = after udelay(100) from last event (you can see the status bit never
raises)

So, you can see that there is no change in the status bit between 4...5,
so there is no point for polling anything there. I even tried changing
the clear of IO status and disabling of IO chain to see if it had any
impact on this result but no. The main point is that we must clear the
status bit at #4, and thus polling for it to change at #5 makes no
sense. We just need to force the register writes to PRCM by doing some
access to the IP block.


Looking at similar trace on omap4:

[    8.097503] omap4_trigger_io_chain(1): IO=00010020
[    8.097503] omap4_trigger_io_chain(2): IO=00010320
[    8.097534] omap4_trigger_io_chain(3): IO=00010320
[    8.097534] omap4_trigger_io_chain(4): IO=00010020
[    8.097534] omap4_trigger_io_chain(5): IO=00010020

1 = enter function
2 = just after enabling WUCLK_CTRL
3 = just after poll
4 = just after disabling WUCLK_CTRL
5 = just after poll

Well, the status bit follows the state of the WUCLK_CTRL, but there is
no time to actually poll the registers it seems, their state has already
changed when the value from first read arrives back as the register
access itself is so slow. But... we are not manually clearing the status
bit, thus polling kind of makes sense (and it might make more sense if
some future version of PRCM would allow faster register access.)

I also did both of these tests by caching the register values to memory
(no immediate printks to avoid delays) but the results are still the
same.

-Tero




From rnayak at ti.com  Mon Mar 12 01:55:23 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 12 Mar 2012 11:25:23 +0530
Subject: [PATCHv5 0/6] ARM: OMAP3+: IO daisy chain support fixes
In-Reply-To: <alpine.DEB.2.00.1203101425230.27395@utopia.booyaka.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203101425230.27395@utopia.booyaka.com>
Message-ID: <4F5D8FCB.5050501@ti.com>

On Sunday 11 March 2012 02:59 AM, Paul Walmsley wrote:
>
> Hi

Hi Paul,

>
> By the way, one other thing I forgot to mention.  It would be really great
> if kerneldoc comments can be created for any new functions added to hwmod,
> PRCM, clock, or omap_device code.  The intention is to help not only
> people unfamiliar with the code, but even ourselves in the future.  I've
> been adding these by hand on Tero's last few patch series, but at some
> point I'll probably stop accepting patches without kerneldoc.

Thanks for updating the kerneldoc comments this time around. Will make
sure patches hence forth come with adequate documentation added.

thanks,
Rajendra
>
>
> thanks,
>
> - Paul



From linus.walleij at linaro.org  Mon Mar 12 06:48:36 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 12 Mar 2012 11:48:36 +0100
Subject: [PATCH] serial: PL011: clear pending interrupts
In-Reply-To: <20120312101100.GA8649@n2100.arm.linux.org.uk>
References: <1331540750-25697-1-git-send-email-linus.walleij@stericsson.com>
 <20120312083221.GW17370@n2100.arm.linux.org.uk>
 <20120312101100.GA8649@n2100.arm.linux.org.uk>
Message-ID: <CACRpkdbsa6HW63vN7CeKNpgLZokB+S6GEaU27CiaVsbvo5qA-g@mail.gmail.com>

On Mon, Mar 12, 2012 at 11:11 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:

>> > + ? /* RXIS but RXFE? Just clear the interrupt */
>> > + ? if(unlikely(fifotaken == 0))
>> > + ? ? ? ? ? writew(UART011_RTIS | UART011_RXIS,
>> > + ? ? ? ? ? ? ? ? ?uap->port.membase + UART011_ICR);
>
> BTW, I don't see why we need any of this stuff.
>
> The problem as described is that the interrupt handler is called with one
> of the receive flags set (UART011_RTIS or UART011_RXIS) but with
> UART01x_FR_RXFE clear.
>
> The problem report indicates that this is caused when we switch from FIFO
> mode to non-FIFO mode, and the FIFO contained some unread characters.
>
> That can only happen once we've enabled interrupts in the IMSC register,
> which doesn't happen until later in the startup function.
>
> So:
>
> ? ? ? ?spin_lock_irq(&uap->port.lock);
> ? ? ? ?uap->im = UART011_RTIM;
> ? ? ? ?if (!pl011_dma_rx_running(uap))
> ? ? ? ? ? ? ? ?uap->im |= UART011_RXIM;
> ? ? ? ?writew(uap->im, uap->port.membase + UART011_IMSC);
> ? ? ? ?spin_unlock_irq(&uap->port.lock);
>
> clearing the transmit/receive interrupts here _before_ we unmask them
> should be sufficient.

Right! OK I'll cook a v2 patch according to this suggestion and
request Chanho to test it.

Yours,
Linus Walleij


From hvaibhav at ti.com  Mon Mar 12 06:13:45 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 12 Mar 2012 10:13:45 +0000
Subject: [PATCH] ARM: OMAP2+: hwmod: Add new sysc_type3 into omap_hwmod
 required for am33xx
In-Reply-To: <B5906170F1614E41A8A28DE3B8D12143317A918A@DBDE01.ent.ti.com>
References: <1329481488-27771-1-git-send-email-hvaibhav@ti.com>
 <4F3E545F.8070802@ti.com>
 <B5906170F1614E41A8A28DE3B8D12143317A918A@DBDE01.ent.ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831810F02@DBDE01.ent.ti.com>

On Tue, Feb 21, 2012 at 10:49:47, Bedia, Vaibhav wrote:
> Hi Benoit,
> 
> On Fri, Feb 17, 2012 at 18:51:35, Cousson, Benoit wrote:
> > Hi Vaibhav,
> > 
> > On 2/17/2012 1:24 PM, Vaibhav Hiremath wrote:
> > > In case of AM33xx family of devices (like cpsw) have different sysc
> > > bit field offsets defined,
> > 
> > It is really used by several IPs, or it is just an unique exception?
> > 
> > For an exception, you can just define the omap_hwmod_sysc_fields for 
> > that IP.
> > This is what SmartReflex is using for example.
> > 
> 
> I haven't really check TI81xx code but we might need to share these SYSC types
> with a few IPs in that family also. How can the sharing of the sysc data be handled?
> 

Benoit,

Any comments on this patch? 

Thanks,
Vaibhav

> Regards,
> Vaibhav B.
> 



From thomas.abraham at linaro.org  Mon Mar 12 17:10:03 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 02:40:03 +0530
Subject: [PATCH v3 0/2] regulator: add irq domain and device tree support
 for MAX8997
In-Reply-To: <1330000688-11226-1-git-send-email-thomas.abraham@linaro.org>
References: <1330000688-11226-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CAJuYYwQMB0ANS6noscRe6P4d0JKmTPLP_1r2Sr6-N3amAZiD5Q@mail.gmail.com>

Hi Rob/Grant,

On 23 February 2012 18:08, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> Changes since v2:
> - Atleast one voltage level has to be specfied for Buck 1/2/5 even if GPIO
> ?DVS option is not used (suggested by MyungJoo Ham).
> - Reworked the irq_domain support based the v5 of irq_domain generalization
> ?patches.
>
> MAX8997 is a multi-function device which includes support for regulators, rtc,
> battery charger and other sub-blocks. This patchset adds device tree support
> for the pmic (regulators) sub-block.
>
> The first patch adds irq domain support for the interrupts supported by max8997
> mainly for removing the need to pass a irq_base from the platform code. The
> irq_base could not anyway be passed in case of device tree based instantiation.
> The reverse mapping method used is linear since the sub-drivers of max8997 has
> access to the max8997 irq_domain from which the linux irq number can be
> obtained.
>
> The second patch adds device tree support for max8997. This patch modifies both
> mfd and regulator portions of the max8997 code.
>
> This patchset is based on the following tree.
> http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]
>
> with all patches merged from
> http://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git [for-next]
> http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]
>
> and depends on the following patchset.
> [PATCH v3 0/4] ARM: Exynos4: Add irq domain and device tree support for wakeup interrupts.
>
> This patchset has been tested on Origen board.
>
> Thomas Abraham (2):
> ?mfd: add irq domain support for max8997 interrupts
> ?regulator: add device tree support for max8997

Any comments for this patch series?

Thanks,
Thomas.

>
> ?.../devicetree/bindings/regulator/max8997-pmic.txt | ?134 +++++++++++++++++++
> ?arch/arm/mach-exynos/mach-nuri.c ? ? ? ? ? ? ? ? ? | ? ?4 -
> ?arch/arm/mach-exynos/mach-origen.c ? ? ? ? ? ? ? ? | ? ?1 -
> ?drivers/mfd/max8997-irq.c ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 60 +++++----
> ?drivers/mfd/max8997.c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 73 ++++++++++-
> ?drivers/regulator/max8997.c ? ? ? ? ? ? ? ? ? ? ? ?| ?139 +++++++++++++++++++-
> ?include/linux/mfd/max8997-private.h ? ? ? ? ? ? ? ?| ? ?4 +-
> ?include/linux/mfd/max8997.h ? ? ? ? ? ? ? ? ? ? ? ?| ? ?2 +-
> ?8 files changed, 382 insertions(+), 35 deletions(-)
> ?create mode 100644 Documentation/devicetree/bindings/regulator/max8997-pmic.txt
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html


From linus.walleij at stericsson.com  Mon Mar 12 17:14:19 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 12 Mar 2012 22:14:19 +0100
Subject: [PATCH 1/4 v7] pinctrl: introduce generic pin config
Message-ID: <1331586859-15619-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This is a split-off from the earlier patch set which adds generic
pin configuration for the pin controllers that want it. Since
we may have a system with mixed generic and custom pin controllers,
we pass a boolean in the pin controller ops vtable to indicate
if it is generic.

ChangeLog v1->v5:
- Follow parent patch versioning number system.
- Document the semantic meaning of return values from pin config
  get functions, so we can iterate over pins and check their
  properties from debugfs as part of the generic config code.
- Use proper cast functions in the generic debugfs pin config
  file.
- Expand generic config to optionally cover groups too.
ChangeLog v5->v6:
- Update to match underlying changes.
ChangeLog v6->v7:
- Drop DRIVE_OFF parameter, use bias high impedance for this
- Delete argument for drive modes push-pull, od and os. These
  are now just state transitions.
- Delete slew rate rising/falling due to discussions on on
  proper semantics
- Drop config wakeup, struct irq_chip does this for now, add
  back if need be.
- Set PIN_CONFIG_END to 0x7fff making room for custom config
  parameters from 0x8000 and up.
- Prefix accessor functions with pinconf_
---
 drivers/pinctrl/Kconfig                 |    4 +
 drivers/pinctrl/Makefile                |    1 +
 drivers/pinctrl/pinconf-generic.c       |  120 +++++++++++++++++++++++++++++++
 drivers/pinctrl/pinconf.c               |    6 ++-
 drivers/pinctrl/pinconf.h               |   43 ++++++++++-
 include/linux/pinctrl/pinconf-generic.h |  114 +++++++++++++++++++++++++++++
 include/linux/pinctrl/pinconf.h         |    5 ++
 7 files changed, 289 insertions(+), 4 deletions(-)
 create mode 100644 drivers/pinctrl/pinconf-generic.c
 create mode 100644 include/linux/pinctrl/pinconf-generic.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6d29ff..07f3d8d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -17,6 +17,10 @@ config PINMUX
 config PINCONF
 	bool "Support pin configuration controllers"
 
+config GENERIC_PINCONF
+	bool
+	select PINCONF
+
 config DEBUG_PINCTRL
 	bool "Debug PINCTRL calls"
 	depends on DEBUG_KERNEL
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 754329b..6d4150b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -5,6 +5,7 @@ ccflags-$(CONFIG_DEBUG_PINCTRL)	+= -DDEBUG
 obj-$(CONFIG_PINCTRL)		+= core.o
 obj-$(CONFIG_PINMUX)		+= pinmux.o
 obj-$(CONFIG_PINCONF)		+= pinconf.o
+obj-$(CONFIG_GENERIC_PINCONF)	+= pinconf-generic.o
 obj-$(CONFIG_PINCTRL_PXA3xx)	+= pinctrl-pxa3xx.o
 obj-$(CONFIG_PINCTRL_MMP2)	+= pinctrl-mmp2.o
 obj-$(CONFIG_PINCTRL_PXA168)	+= pinctrl-pxa168.o
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
new file mode 100644
index 0000000..33fbaea
--- /dev/null
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -0,0 +1,120 @@
+/*
+ * Core driver for the generic pin config portions of the pin control subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ *
+ * Author: Linus Walleij <linus.walleij at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#define pr_fmt(fmt) "generic pinconfig core: " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include "core.h"
+#include "pinconf.h"
+
+#ifdef CONFIG_DEBUG_FS
+
+struct pin_config_item {
+	const enum pin_config_param param;
+	const char * const display;
+	const char * const format;
+};
+
+#define PCONFDUMP(a, b, c) { .param = a, .display = b, .format = c }
+
+struct pin_config_item conf_items[] = {
+	PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL),
+	PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL),
+	PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL),
+	PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL),
+	PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL),
+	PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL),
+	PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL),
+	PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL),
+	PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "time units"),
+	PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector"),
+	PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode"),
+};
+
+void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
+			      struct seq_file *s, unsigned pin)
+{
+	const struct pinconf_ops *ops = pctldev->desc->confops;
+	int i;
+
+	if (!ops->is_generic)
+		return;
+
+	for(i = 0; i < ARRAY_SIZE(conf_items); i++) {
+		unsigned long config;
+		int ret;
+
+		/* We want to check out this parameter */
+		config = pinconf_to_config_packed(conf_items[i].param, 0);
+		ret = pin_config_get_for_pin(pctldev, pin, &config);
+		/* These are legal errors */
+		if (ret == -EINVAL || ret == -ENOTSUPP)
+			continue;
+		if (ret) {
+			seq_printf(s, "ERROR READING CONFIG SETTING %d ", i);
+			continue;
+		}
+		/* Space between multiple configs */
+		seq_puts(s, " ");
+		seq_puts(s, conf_items[i].display);
+		/* Print unit if available */
+		if (conf_items[i].format &&
+		    pinconf_to_config_argument(config) != 0)
+			seq_printf(s, " (%u %s)",
+				   pinconf_to_config_argument(config),
+				   conf_items[i].format);
+	}
+}
+
+void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
+			      struct seq_file *s, const char *gname)
+{
+	const struct pinconf_ops *ops = pctldev->desc->confops;
+	int i;
+
+	if (!ops->is_generic)
+		return;
+
+	for(i = 0; i < ARRAY_SIZE(conf_items); i++) {
+		unsigned long config;
+		int ret;
+
+		/* We want to check out this parameter */
+		config = pinconf_to_config_packed(conf_items[i].param, 0);
+		ret = pin_config_group_get(dev_name(pctldev->dev), gname,
+					   &config);
+		/* These are legal errors */
+		if (ret == -EINVAL || ret == -ENOTSUPP)
+			continue;
+		if (ret) {
+			seq_printf(s, "ERROR READING CONFIG SETTING %d ", i);
+			continue;
+		}
+		/* Space between multiple configs */
+		seq_puts(s, " ");
+		seq_puts(s, conf_items[i].display);
+		/* Print unit if available */
+		if (conf_items[i].format && config != 0)
+			seq_printf(s, " (%u %s)",
+				   pinconf_to_config_argument(config),
+				   conf_items[i].format);
+	}
+}
+
+#endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 1e9b8cb..f9c9cd1 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -54,7 +54,7 @@ int pinconf_validate_map(struct pinctrl_map const *map, int i)
 	return 0;
 }
 
-static int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
+int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
 			   unsigned long *config)
 {
 	const struct pinconf_ops *ops = pctldev->desc->confops;
@@ -439,6 +439,8 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
 {
 	const struct pinconf_ops *ops = pctldev->desc->confops;
 
+	/* no-op when not using generic pin config */
+	pinconf_generic_dump_pin(pctldev, s, pin);
 	if (ops && ops->pin_config_dbg_show)
 		ops->pin_config_dbg_show(pctldev, s, pin);
 }
@@ -482,6 +484,8 @@ static void pinconf_dump_group(struct pinctrl_dev *pctldev,
 {
 	const struct pinconf_ops *ops = pctldev->desc->confops;
 
+	/* no-op when not using generic pin config */
+	pinconf_generic_dump_group(pctldev, s, gname);
 	if (ops && ops->pin_config_group_dbg_show)
 		ops->pin_config_group_dbg_show(pctldev, s, selector);
 }
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index 0ded227..54510de 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -14,20 +14,26 @@
 #ifdef CONFIG_PINCONF
 
 int pinconf_check_ops(struct pinctrl_dev *pctldev);
-
 int pinconf_validate_map(struct pinctrl_map const *map, int i);
-
 int pinconf_map_to_setting(struct pinctrl_map const *map,
 			  struct pinctrl_setting *setting);
 void pinconf_free_setting(struct pinctrl_setting const *setting);
 int pinconf_apply_setting(struct pinctrl_setting const *setting);
-
 void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
 void pinconf_show_setting(struct seq_file *s,
 			  struct pinctrl_setting const *setting);
 void pinconf_init_device_debugfs(struct dentry *devroot,
 				 struct pinctrl_dev *pctldev);
 
+/*
+ * You will only be interested in these if you're using PINCONF
+ * so don't supply any stubs for these.
+ */
+int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
+			   unsigned long *config);
+int pin_config_group_get(const char *dev_name, const char *pin_group,
+			 unsigned long *config);
+
 #else
 
 static inline int pinconf_check_ops(struct pinctrl_dev *pctldev)
@@ -71,3 +77,34 @@ static inline void pinconf_init_device_debugfs(struct dentry *devroot,
 }
 
 #endif
+
+/*
+ * The following functions are available if the driver uses the generic
+ * pin config.
+ */
+
+#ifdef CONFIG_GENERIC_PINCONF
+
+void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
+			      struct seq_file *s, unsigned pin);
+
+void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
+			      struct seq_file *s, const char *gname);
+
+#else
+
+static inline void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
+					    struct seq_file *s,
+					    unsigned pin)
+{
+	return;
+}
+
+static inline void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
+					      struct seq_file *s,
+					      const char *gname)
+{
+	return;
+}
+
+#endif
diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
new file mode 100644
index 0000000..4f0abb9
--- /dev/null
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -0,0 +1,114 @@
+/*
+ * Interface the generic pinconfig portions of the pinctrl subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * This interface is used in the core to keep track of pins.
+ *
+ * Author: Linus Walleij <linus.walleij at linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __LINUX_PINCTRL_PINCONF_GENERIC_H
+#define __LINUX_PINCTRL_PINCONF_GENERIC_H
+
+/*
+ * You shouldn't even be able to compile with these enums etc unless you're
+ * using generic pin config. That is why this is defined out.
+ */
+#ifdef CONFIG_GENERIC_PINCONF
+
+/**
+ * enum pin_config_param - possible pin configuration parameters
+ * @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a
+ *	transition from say pull-up to pull-down implies that you disable
+ *	pull-up in the process, this setting disables all biasing.
+ * @PIN_CONFIG_BIAS_HIGH_IMPEDANCE: the pin will be set to a high impedance
+ *	mode, also know as "third-state" (tristate) or "high-Z" or "floating".
+ *	On output pins this effectively disconnects the pin, which is useful
+ *	if for example some other pin is going to drive the signal connected
+ *	to it for a while. Pins used for input are usually always high
+ *	impedance.
+ * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
+ *	impedance to VDD). If the argument is != 0 pull-up is enabled,
+ *	if it is 0, pull-up is disabled.
+ * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
+ *	impedance to GROUND). If the argument is != 0 pull-down is enabled,
+ *	if it is 0, pull-down is disabled.
+ * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
+ *	low, this is the most typical case and is typically achieved with two
+ *	active transistors on the output. Sending this config will enabale
+ *	push-pull mode, the argument is ignored.
+ * @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open
+ *	collector) which means it is usually wired with other output ports
+ *	which are then pulled up with an external resistor. Sending this
+ *	config will enabale open drain mode, the argument is ignored.
+ * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source
+ *	(open emitter). Sending this config will enabale open drain mode, the
+ *	argument is ignored.
+ * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in
+ *	schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis,
+ *	the threshold value is given on a custom format as argument when
+ *	setting pins to this mode. The argument zero turns the schmitt trigger
+ *	off.
+ * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
+ *	which means it will wait for signals to settle when reading inputs. The
+ *	argument gives the debounce time on a custom format. Setting the
+ *	argument to zero turns debouncing off.
+ * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
+ *	supplies, the argument to this parameter (on a custom format) tells
+ *	the driver which alternative power source to use.
+ * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
+ *	operation, if several modes of operation are supported these can be
+ *	passed in the argument on a custom form, else just use argument 1
+ *	to indicate low power mode, argument 0 turns low power mode off.
+ * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
+ *	you need to pass in custom configurations to the pin controller, use
+ *	PIN_CONFIG_END+1 as the base offset.
+ */
+enum pin_config_param {
+	PIN_CONFIG_BIAS_DISABLE,
+	PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
+	PIN_CONFIG_BIAS_PULL_UP,
+	PIN_CONFIG_BIAS_PULL_DOWN,
+	PIN_CONFIG_DRIVE_PUSH_PULL,
+	PIN_CONFIG_DRIVE_OPEN_DRAIN,
+	PIN_CONFIG_DRIVE_OPEN_SOURCE,
+	PIN_CONFIG_INPUT_SCHMITT,
+	PIN_CONFIG_INPUT_DEBOUNCE,
+	PIN_CONFIG_POWER_SOURCE,
+	PIN_CONFIG_LOW_POWER_MODE,
+	PIN_CONFIG_END = 0x7FFF,
+};
+
+/*
+ * Helpful configuration macro to be used in tables etc.
+ */
+#define PIN_CONF_PACKED(p, a) ((a << 16) | ((unsigned long) p & 0xffffUL))
+
+/*
+ * The following inlines stuffs a configuration parameter and data value
+ * into and out of an unsigned long argument, as used by the generic pin config
+ * system. We put the parameter in the lower 16 bits and the argument in the
+ * upper 16 bits.
+ */
+
+static inline enum pin_config_param pinconf_to_config_param(unsigned long config)
+{
+	return (enum pin_config_param) (config & 0xffffUL);
+}
+
+static inline u16 pinconf_to_config_argument(unsigned long config)
+{
+	return (enum pin_config_param) ((config >> 16) & 0xffffUL);
+}
+
+static inline unsigned long pinconf_to_config_packed(enum pin_config_param param,
+						     u16 argument)
+{
+	return PIN_CONF_PACKED(param, argument);
+}
+
+#endif /* CONFIG_GENERIC_PINCONF */
+
+#endif /* __LINUX_PINCTRL_PINCONF_GENERIC_H */
diff --git a/include/linux/pinctrl/pinconf.h b/include/linux/pinctrl/pinconf.h
index f8cf156..ec431f0 100644
--- a/include/linux/pinctrl/pinconf.h
+++ b/include/linux/pinctrl/pinconf.h
@@ -20,6 +20,8 @@ struct seq_file;
 /**
  * struct pinconf_ops - pin config operations, to be implemented by
  * pin configuration capable drivers.
+ * @is_generic: for pin controllers that want to use the generic interface,
+ *	this flag tells the framework that it's generic.
  * @pin_config_get: get the config of a certain pin, if the requested config
  *	is not available on this controller this should return -ENOTSUPP
  *	and if it is available but disabled it should return -EINVAL
@@ -33,6 +35,9 @@ struct seq_file;
  *	per-device info for a certain group in debugfs
  */
 struct pinconf_ops {
+#ifdef CONFIG_GENERIC_PINCONF
+	bool is_generic;
+#endif
 	int (*pin_config_get) (struct pinctrl_dev *pctldev,
 			       unsigned pin,
 			       unsigned long *config);
-- 
1.7.8



From linus.walleij at stericsson.com  Mon Mar 12 17:14:31 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 12 Mar 2012 22:14:31 +0100
Subject: [PATCH 3/4 v3] pinctrl: support pinconfig on the U300
Message-ID: <1331586871-15655-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This adds pin configuration support for the U300 driver pair,
we can now read out the biasing and drive mode in debugfs and
configure it using the new configuration API.

ChangeLog v1->v2:
- Migrate to pin config and generic pin config changes.
ChangeLog v2->v3:
- Adjust to generic pin config changes in v7 patch set.

Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/pinctrl/Kconfig          |    1 +
 drivers/pinctrl/pinctrl-coh901.c |   77 ++++++++++++++++++++++++++++++++++----
 drivers/pinctrl/pinctrl-coh901.h |    5 ++
 drivers/pinctrl/pinctrl-u300.c   |   60 +++++++++++++++++++++++++++++
 4 files changed, 135 insertions(+), 8 deletions(-)
 create mode 100644 drivers/pinctrl/pinctrl-coh901.h

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 07f3d8d..abfb964 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -73,6 +73,7 @@ config PINCTRL_U300
 	bool "U300 pin controller driver"
 	depends on ARCH_U300
 	select PINMUX
+	select GENERIC_PINCONF
 
 config PINCTRL_COH901
 	bool "ST-Ericsson U300 COH 901 335/571 GPIO"
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 724234c..0797eba 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -23,7 +23,9 @@
 #include <linux/list.h>
 #include <linux/slab.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <mach/gpio-u300.h>
+#include "pinctrl-coh901.h"
 
 /*
  * Register definitions for COH 901 335 variant
@@ -418,8 +420,68 @@ static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 	return retirq;
 }
 
-static int u300_gpio_config(struct gpio_chip *chip, unsigned offset,
-			    enum pin_config_param param, unsigned long data)
+/* Returning -EINVAL means "supported but not available" */
+int u300_gpio_config_get(struct gpio_chip *chip,
+			 unsigned offset,
+			 unsigned long *config)
+{
+	struct u300_gpio *gpio = to_u300_gpio(chip);
+	enum pin_config_param param = (enum pin_config_param) *config;
+	bool biasmode;
+	u32 drmode;
+
+	/* One bit per pin, clamp to bool range */
+	biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
+
+	/* Mask out the two bits for this pin and shift to bits 0,1 */
+	drmode = readl(U300_PIN_REG(offset, pcr));
+	drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
+	drmode >>= ((offset & 0x07) << 1);
+
+	switch(param) {
+	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+		*config = 0;
+		if (biasmode)
+			return 0;
+		else
+			return -EINVAL;
+		break;
+	case PIN_CONFIG_BIAS_PULL_UP:
+		*config = 0;
+		if (!biasmode)
+			return 0;
+		else
+			return -EINVAL;
+		break;
+	case PIN_CONFIG_DRIVE_PUSH_PULL:
+		*config = 0;
+		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
+			return 0;
+		else
+			return -EINVAL;
+		break;
+	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+		*config = 0;
+		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
+			return 0;
+		else
+			return -EINVAL;
+		break;
+	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
+		*config = 0;
+		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
+			return 0;
+		else
+			return -EINVAL;
+		break;
+	default:
+		break;
+	}
+	return -ENOTSUPP;
+}
+
+int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
+			 enum pin_config_param param)
 {
 	struct u300_gpio *gpio = to_u300_gpio(chip);
 	unsigned long flags;
@@ -620,13 +682,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
 		u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
 
 		/* Deactivate bias mode for output */
-		u300_gpio_config(&gpio->chip, offset,
-				 PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
-				 0);
+		u300_gpio_config_set(&gpio->chip, offset,
+				     PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
 
 		/* Set drive mode for output */
-		u300_gpio_config(&gpio->chip, offset,
-				 PIN_CONFIG_DRIVE_PUSH_PULL, 0);
+		u300_gpio_config_set(&gpio->chip, offset,
+				     PIN_CONFIG_DRIVE_PUSH_PULL);
 
 		dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
 			offset, conf->outval);
@@ -637,7 +698,7 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
 		u300_gpio_set(&gpio->chip, offset, 0);
 
 		/* Set bias mode for input */
-		u300_gpio_config(&gpio->chip, offset, conf->bias_mode, 0);
+		u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
 
 		dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
 			offset, conf->bias_mode);
diff --git a/drivers/pinctrl/pinctrl-coh901.h b/drivers/pinctrl/pinctrl-coh901.h
new file mode 100644
index 0000000..8729422
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-coh901.h
@@ -0,0 +1,5 @@
+int u300_gpio_config_get(struct gpio_chip *chip,
+			 unsigned offset,
+			 unsigned long *config);
+int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
+			 enum pin_config_param param);
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index fc4a281..26eb8cc 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -19,6 +19,9 @@
 #include <linux/err.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include "pinctrl-coh901.h"
 
 /*
  * Register definitions for the U300 Padmux control registers in the
@@ -1044,12 +1047,69 @@ static struct pinctrl_gpio_range u300_gpio_ranges[] = {
 	U300_GPIO_RANGE(25, 181, 1),
 };
 
+static struct pinctrl_gpio_range *u300_match_gpio_range(unsigned pin)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(u300_gpio_ranges); i++) {
+		struct pinctrl_gpio_range *range;
+
+		range = &u300_gpio_ranges[i];
+		if (pin >= range->pin_base &&
+		    pin <= (range->pin_base + range->npins - 1))
+			return range;
+	}
+	return NULL;
+}
+
+int u300_pin_config_get(struct pinctrl_dev *pctldev,
+			unsigned pin,
+			unsigned long *config)
+{
+	struct pinctrl_gpio_range *range = u300_match_gpio_range(pin);
+
+	/* We get config for those pins we CAN get it for and that's it */
+	if (!range)
+		return -ENOTSUPP;
+
+	return u300_gpio_config_get(range->gc,
+				    (pin - range->pin_base + range->base),
+				    config);
+}
+
+int u300_pin_config_set(struct pinctrl_dev *pctldev,
+			unsigned pin,
+			unsigned long config)
+{
+	struct pinctrl_gpio_range *range = u300_match_gpio_range(pin);
+	int ret;
+
+	if (!range)
+		return -EINVAL;
+
+	/* Note: none of these configurations take any argument */
+	ret = u300_gpio_config_set(range->gc,
+				   (pin - range->pin_base + range->base),
+				   pinconf_to_config_param(config));
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static struct pinconf_ops u300_pconf_ops = {
+	.is_generic = true,
+	.pin_config_get = u300_pin_config_get,
+	.pin_config_set = u300_pin_config_set,
+};
+
 static struct pinctrl_desc u300_pmx_desc = {
 	.name = DRIVER_NAME,
 	.pins = u300_pads,
 	.npins = ARRAY_SIZE(u300_pads),
 	.pctlops = &u300_pctrl_ops,
 	.pmxops = &u300_pmx_ops,
+	.confops = &u300_pconf_ops,
 	.owner = THIS_MODULE,
 };
 
-- 
1.7.8



From arnd at arndb.de  Mon Mar 12 10:58:39 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 12 Mar 2012 14:58:39 +0000
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <20120312142716.GA5050@titan.lakedaemon.net>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <op.wa197mq94cuzmg@gonzo.lentin.co.uk>
 <20120312142716.GA5050@titan.lakedaemon.net>
Message-ID: <201203121458.39524.arnd@arndb.de>

On Monday 12 March 2012, Jason Cooper wrote:
> > 
> > It probably depends on how easy it is to add the gpiochips into
> > devicetree. Being able to put the LED, buttons and fans in
> > devicetree would make board-dt.c much more manageable. I started to
> > look into it and wasn't immediately obvious, but will have a closer
> > look.

I would think that gpio should not be too hard, since it has very
little dependencies on other things. GPIO on kirkwood seems to be
tightly coupled with the irq stuff, so I guess these should be done
together. We can discuss how to do these on #linaro-kernel on 
irc.freenode.net if you like.

Once interrupts and GPIO are done, that will enable a lot of
the things that already have bindings like gpio-led and gpio-key.
AFAICT, those won't even need any code changes, only a correct
specification of the device node according to the bindings in
Documentation/devicetree/bindings/gpio/*.

> > Happy to resubmit, breaking it out into a board-dnskw.c though.
> 
> Yeah, let's go ahead and do that.  pinmux and the above are going to take
> a while to sort out.  In the mean time, there's:
> 
> sheevaplug
> guruplug
> guruplug-serverplus
> Lacie-*
> Seagate-*
> rd-boards-*
> 
> just to name a few.  Plus it'll give me something to do while we wait
> for pinmux/common clock to land.

Ok, fair enough. We might also see some interest in having some of the
existing board files moved over to DT based probing in order to slim
them down, which fits in nicely with this approach.

	Arnd


From paul at pwsan.com  Fri Mar  9 23:05:45 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 9 Mar 2012 21:05:45 -0700 (MST)
Subject: [PATCHv5 0/6] ARM: OMAP3+: IO daisy chain support fixes
In-Reply-To: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203092102450.30879@utopia.booyaka.com>

Hi

On Tue, 6 Mar 2012, Tero Kristo wrote:

> Changes compared to previous version:
> 
> - patch2:
>   * fixed the timeout for waiting for ST_IO_CHAIN == 1
>   * added clear for ST_IO_CHAIN bit (as per spec + implementation in patch 1)
>   * replaced the timeout at the end of function with a simple register
>     readback (timing out on a register value that we are clearing does
>     not make that much sense, the bit is cleared the very first time CPU
>     manages to read it)
> - patch5:
>   * added spinlock for protecting io_chain_trigger operation
> 
> Tested on omap3 beagle + omap4 blaze. Also did measurements for the
> cost of IO chain trigger operation with ARM performance counters:
> 
> - omap3 approx 7...8us
> - omap4 approx 2...4us

Thanks for the changes.  So as you probably already saw, a few changes 
have been made.  The updated series is in the branch 
'io_chain_devel_3.4' on git://git.pwsan.com/linux-2.6.

The main outstanding question is whether the OMAP4 WUCLKOUT poll should be 
removed to match the v5 changes to the OMAP3 function.  Please let me 
know.   Any other testing or comments are of course welcome.


- Paul


From philippe.retornaz at epfl.ch  Fri Mar  9 09:55:15 2012
From: philippe.retornaz at epfl.ch (=?utf-8?q?Philippe=20R=C3=A9tornaz?=)
Date: Fri,  9 Mar 2012 15:55:15 +0100
Subject: [PATCH 3/4] mx31moboard: Add ssi configuration
In-Reply-To: <1331304916-4724-3-git-send-email-philippe.retornaz@epfl.ch>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-3-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <1331304916-4724-4-git-send-email-philippe.retornaz@epfl.ch>


Signed-off-by: Philippe R?tornaz <philippe.retornaz at epfl.ch>
---
 arch/arm/mach-imx/Kconfig            |    1 +
 arch/arm/mach-imx/mach-mx31moboard.c |   37 +++++++++++++++++++++++++++++++++-
 2 files changed, 37 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4defb97..2c60f63 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -493,6 +493,7 @@ config MACH_MX31MOBOARD
 	select SOC_IMX31
 	select IMX_HAVE_PLATFORM_FSL_USB2_UDC
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_SSI
 	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_IPU_CORE
 	select IMX_HAVE_PLATFORM_MXC_EHCI
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index f225262..23e9d6e 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -42,11 +42,13 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
+#include <mach/audmux.h>
 #include <mach/board-mx31moboard.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ulpi.h>
+#include <mach/ssi.h>
 
 #include "devices-imx31.h"
 
@@ -102,6 +104,9 @@ static unsigned int moboard_pins[] = {
 	MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO,
 	MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY,
 	MX31_PIN_CSPI2_SS1__CSPI3_SS1,
+	/* SSI */
+	MX31_PIN_STXD4__STXD4, MX31_PIN_SRXD4__SRXD4,
+	MX31_PIN_SCK4__SCK4, MX31_PIN_SFS4__SFS4,
 };
 
 static struct physmap_flash_data mx31moboard_flash_data = {
@@ -276,6 +281,11 @@ static struct mc13xxx_buttons_platform_data moboard_buttons = {
 	.b1on_key = KEY_POWER,
 };
 
+static struct mc13xxx_codec_platform_data moboard_codec = {
+	.dac_ssi_port = MC13783_SSI1_PORT,
+	.adc_ssi_port = MC13783_SSI1_PORT,
+};
+
 static struct mc13xxx_platform_data moboard_pmic = {
 	.regulators = {
 		.regulators = moboard_regulators,
@@ -283,7 +293,12 @@ static struct mc13xxx_platform_data moboard_pmic = {
 	},
 	.leds = &moboard_leds,
 	.buttons = &moboard_buttons,
-	.flags = MC13XXX_USE_RTC | MC13XXX_USE_ADC,
+	.codec = &moboard_codec,
+	.flags = MC13XXX_USE_RTC | MC13XXX_USE_ADC | MC13XXX_USE_CODEC,
+};
+
+static struct imx_ssi_platform_data moboard_ssi_pdata = {
+	.flags = IMX_SSI_DMA | IMX_SSI_NET,
 };
 
 static struct spi_board_info moboard_spi_board_info[] __initdata = {
@@ -527,6 +542,24 @@ static void __init mx31moboard_init(void)
 	mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
 		"moboard");
 
+	mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT4_SSI_PINS_4,
+			MXC_AUDMUX_V2_PTCR_SYN,
+			MXC_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0) |
+			MXC_AUDMUX_V2_PDCR_MODE(1) |
+			MXC_AUDMUX_V2_PDCR_INMMASK(0xfc));
+
+	mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT1_SSI0,
+		MXC_AUDMUX_V2_PTCR_SYN |
+		MXC_AUDMUX_V2_PTCR_TFSDIR |
+		MXC_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT4_SSI_PINS_4) |
+		MXC_AUDMUX_V2_PTCR_TCLKDIR |
+		MXC_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT4_SSI_PINS_4) |
+		MXC_AUDMUX_V2_PTCR_RFSDIR |
+		MXC_AUDMUX_V2_PTCR_RFSEL(MX31_AUDMUX_PORT4_SSI_PINS_4) |
+		MXC_AUDMUX_V2_PTCR_RCLKDIR |
+		MXC_AUDMUX_V2_PTCR_RCSEL(MX31_AUDMUX_PORT4_SSI_PINS_4),
+		MXC_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT4_SSI_PINS_4));
+
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 	gpio_led_register_device(-1, &mx31moboard_led_pdata);
 
@@ -552,6 +585,8 @@ static void __init mx31moboard_init(void)
 
 	moboard_usbh2_init();
 
+	imx31_add_imx_ssi(0, &moboard_ssi_pdata);
+
 	pm_power_off = mx31moboard_poweroff;
 
 	switch (mx31moboard_baseboard) {
-- 
1.6.3.3



From philippe.retornaz at epfl.ch  Fri Mar  9 09:55:14 2012
From: philippe.retornaz at epfl.ch (=?utf-8?q?Philippe=20R=C3=A9tornaz?=)
Date: Fri,  9 Mar 2012 15:55:14 +0100
Subject: [PATCH 2/4] Add imx3sound sound support.
In-Reply-To: <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <1331304916-4724-3-git-send-email-philippe.retornaz@epfl.ch>

Several boards are using the mc13783 codec with the same
configuration. Provide an unique asoc platform driver for it.

Signed-off-by: Philippe R?tornaz <philippe.retornaz at epfl.ch>
---
 sound/soc/imx/Kconfig             |   10 +++
 sound/soc/imx/Makefile            |    2 +
 sound/soc/imx/imx3sound-mc13783.c |  141 +++++++++++++++++++++++++++++++++++++
 3 files changed, 153 insertions(+), 0 deletions(-)
 create mode 100644 sound/soc/imx/imx3sound-mc13783.c

diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index 7383917..244a5fe 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -57,4 +57,14 @@ config SND_SOC_EUKREA_TLV320
 	  Enable I2S based access to the TLV320AIC23B codec attached
 	  to the SSI interface
 
+config SND_SOC_IMX3SOUND_MC13783
+	tristate "SoC Audio support for imx31 with MC13783 codecs"
+	depends on IMX_SDMA
+	select SND_MXC_SOC_SSI
+	select SND_SOC_MC13783
+	select SND_MXC_SOC_MX2
+	help
+		Say Y if you want to add support for SoC audio on mx31moboard
+		and imx31pdk_3ds boards using a MC13783 Codec.
+
 endif	# SND_IMX_SOC
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
index d6d609b..742fd35 100644
--- a/sound/soc/imx/Makefile
+++ b/sound/soc/imx/Makefile
@@ -12,8 +12,10 @@ snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
 snd-soc-phycore-ac97-objs := phycore-ac97.o
 snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
 snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+snd-soc-imx3sound-mc13783-objs := imx3sound-mc13783.o
 
 obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
 obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
 obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
 obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
+obj-$(CONFIG_SND_SOC_IMX3SOUND_MC13783) += snd-soc-imx3sound-mc13783.o
diff --git a/sound/soc/imx/imx3sound-mc13783.c b/sound/soc/imx/imx3sound-mc13783.c
new file mode 100644
index 0000000..b11e455
--- /dev/null
+++ b/sound/soc/imx/imx3sound-mc13783.c
@@ -0,0 +1,141 @@
+/*
+ * imx3sound-mc13783.c  --  SoC audio for imx31_3ds based boards
+ *
+ * Copyright 2012 Philippe Retornaz, <philippe.retornaz at epfl.ch>
+ *
+ * Heavly based on phycore-mc13783:
+ * Copyright 2009 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <asm/mach-types.h>
+
+#include "../codecs/mc13783.h"
+#include "imx-ssi.h"
+
+static struct snd_soc_card imx3sound;
+
+#define FMT_SSI (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_NF | \
+		SND_SOC_DAIFMT_CBM_CFM)
+
+static int imx3sound_hifi_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	int ret;
+
+	ret = snd_soc_dai_set_fmt(codec_dai, FMT_SSI);
+	if (ret)
+		return ret;
+
+	ret = snd_soc_dai_set_fmt(cpu_dai, FMT_SSI);
+	if (ret)
+		return ret;
+
+	ret = snd_soc_dai_set_tdm_slot(codec_dai, 0xfffffffc, 0xfffffffc, 4, 16);
+	if (ret)
+		return ret;
+
+	ret = snd_soc_dai_set_sysclk(codec_dai, MC13783_CLK_CLIA, 26000000, 0);
+	if (ret)
+		return ret;
+
+	ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0x0, 0xfffffffc, 2, 16);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int imx3sound_hifi_hw_free(struct snd_pcm_substream *substream)
+{
+	return 0;
+}
+
+static struct snd_soc_ops imx3sound_hifi_ops = {
+	.hw_params = imx3sound_hifi_hw_params,
+	.hw_free = imx3sound_hifi_hw_free,
+};
+
+static int imx3sound_probe(struct snd_soc_card *dev)
+{
+	return 0;
+}
+
+static int imx3sound_remove(struct snd_soc_card *dev)
+{
+	return 0;
+}
+
+static struct snd_soc_dai_link imx3sound_dai_mc13783[] = {
+	{
+		.name = "MC13783",
+		.stream_name	 = "Sound",
+		.codec_dai_name	 = "mc13783-hifi",
+		.codec_name	 = "mc13783-codec",
+		.cpu_dai_name	 = "imx-ssi.0",
+		.platform_name	 = "imx-pcm-audio.0",
+		.ops		 = &imx3sound_hifi_ops,
+		.symmetric_rates = 1,
+	},
+};
+
+static struct snd_soc_card imx3sound = {
+	.name		= "imx3sound",
+	.probe		= imx3sound_probe,
+	.remove		= imx3sound_remove,
+	.dai_link	= imx3sound_dai_mc13783,
+	.num_links	= ARRAY_SIZE(imx3sound_dai_mc13783),
+};
+
+static struct platform_device *imx3sound_snd_device;
+
+static int __init imx3sound_init(void)
+{
+	int ret;
+
+	if (!(machine_is_mx31moboard() || machine_is_mx31_3ds()))
+		/* return happy. We might run on a totally different machine */
+		return 0;
+
+	imx3sound_snd_device = platform_device_alloc("soc-audio", -1);
+	if (!imx3sound_snd_device)
+		return -ENOMEM;
+
+	platform_set_drvdata(imx3sound_snd_device, &imx3sound);
+	ret = platform_device_add(imx3sound_snd_device);
+
+	if (ret) {
+		printk(KERN_ERR "ASoC: Platform device allocation failed\n");
+		platform_device_put(imx3sound_snd_device);
+	}
+
+	return ret;
+}
+
+static void __exit imx3sound_exit(void)
+{
+	platform_device_unregister(imx3sound_snd_device);
+}
+
+late_initcall(imx3sound_init);
+module_exit(imx3sound_exit);
+
+MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de>");
+MODULE_AUTHOR("Philippe Retornaz <philippe.retornaz at epfl.ch");
+MODULE_DESCRIPTION("mx31moboard & mx31_3ds ALSA SoC driver");
+MODULE_LICENSE("GPL");
-- 
1.6.3.3



From w.sang at pengutronix.de  Fri Mar  9 08:26:28 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Fri, 9 Mar 2012 14:26:28 +0100
Subject: [PATCH 0/3] introduce stmp-style devices
In-Reply-To: <201203081603.12817.arnd@arndb.de>
References: <1331159314-12022-1-git-send-email-w.sang@pengutronix.de>
 <201203081603.12817.arnd@arndb.de>
Message-ID: <20120309132628.GB2554@pengutronix.de>


> I think having the stmp_device code is good, but I'm not sure about the
> location in drivers/base, which is otherwise reserved for anything related
> to 'struct device'. How about putting the same file into lib/stmpregs.c?

Fine with me in general, except that I'd go for lib/stmp_device.c.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From lost.distance at yahoo.com  Fri Mar  9 08:24:36 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 9 Mar 2012 13:24:36 +0000 (GMT)
Subject: [PATCH] MAINTAINERS: update maintainer entry for pxa/hx4700
In-Reply-To: <1330256419.3673.27.camel@flow>
Message-ID: <1331299476.1616.YahooMailClassic@web29006.mail.ird.yahoo.com>

Acked-by: Paul Parsons <lost.distance at yahoo.com>

--- On Sun, 26/2/12, Philipp Zabel <philipp.zabel at gmail.com> wrote:
> Add Paul Parsons as maintainer for
> pxa/hx4700.
> Also, add a mailing list and update the files.
> 
> Cc: Paul Parsons <lost.distance at yahoo.com>
> Signed-off-by: Philipp Zabel <philipp.zabel at gmail.com>
> ---
>  MAINTAINERS |? ? 3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9a648eb..154ab2b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -815,9 +815,12 @@ S:??? Maintained
>  
>  ARM/H4700 (HP IPAQ HX4700) MACHINE SUPPORT
>  M:??? Philipp Zabel <philipp.zabel at gmail.com>
> +M:??? Paul Parsons <lost.distance at yahoo.com>
> +L:??? linux-arm-kernel at lists.infradead.org
> (moderated for non-subscribers)
>  S:??? Maintained
>  F:??? arch/arm/mach-pxa/hx4700.c
>  F:???
> arch/arm/mach-pxa/include/mach/hx4700.h
> +F:??? sound/soc/pxa/hx4700.c
>  
>  ARM/HP JORNADA 7XX MACHINE SUPPORT
>  M:??? Kristoffer Ericson <kristoffer.ericson at gmail.com>
> -- 
> 1.7.9



From aneesh at ti.com  Fri Mar  9 07:50:51 2012
From: aneesh at ti.com (Aneesh V)
Date: Fri, 09 Mar 2012 18:20:51 +0530
Subject: [PATCH 4/4] misc: emif: add device tree support to emif driver
In-Reply-To: <20120309053704.E40433E0901@localhost>
References: <1331224437-4808-1-git-send-email-aneesh@ti.com>
 <1331224437-4808-5-git-send-email-aneesh@ti.com>
 <20120309053704.E40433E0901@localhost>
Message-ID: <4F59FCAB.5040107@ti.com>

Hi Grant,

On Friday 09 March 2012 11:07 AM, Grant Likely wrote:
> On Thu,  8 Mar 2012 22:03:57 +0530, Aneesh V<aneesh at ti.com>  wrote:
>> Cc: Rajendra Nayak<rnayak at ti.com>
>> Cc: Benoit Cousson<b-cousson at ti.com>
>> Signed-off-by: Aneesh V<aneesh at ti.com>
>> ---
>> Changes since RFC v4:
>> - Rebased to the latest version of EMIF series
>> - Replace kzalloc()/kfree() with devm_* variants
>> ---
>>   drivers/misc/emif.c |  289 ++++++++++++++++++++++++++++++++++++++++++++++++++-
>>   1 files changed, 288 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
>> index 79fb161..0aaa61e 100644
>> --- a/drivers/misc/emif.c
>> +++ b/drivers/misc/emif.c
>> @@ -18,6 +18,7 @@
>>   #include<linux/platform_device.h>
>>   #include<linux/interrupt.h>
>>   #include<linux/slab.h>
>> +#include<linux/of.h>
>>   #include<linux/debugfs.h>
>>   #include<linux/seq_file.h>
>>   #include<linux/module.h>
>> @@ -49,6 +50,7 @@
>>    *				frequency in effect at the moment)
>>    * @plat_data:			Pointer to saved platform data.
>>    * @debugfs_root:		dentry to the root folder for EMIF in debugfs
>> + * @np_ddr:			Pointer to ddr device tree node
>>    */
>>   struct emif_data {
>>   	u8				duplicate;
>> @@ -63,6 +65,9 @@ struct emif_data {
>>   	struct emif_regs		*curr_regs;
>>   	struct emif_platform_data	*plat_data;
>>   	struct dentry			*debugfs_root;
>> +#if defined(CONFIG_OF)
>> +	struct device_node		*np_ddr;
>> +#endif
>
> Don't bother with the #if/#endif wrapper here.

Ok.

>
>>   };
>>
>>   static struct emif_data *emif1;
>> @@ -1147,6 +1152,270 @@ static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
>>   	return valid;
>>   }
>>
>> +#if defined(CONFIG_OF)
>> +static void __init of_get_custom_configs(struct device_node *np_emif,
>
> __devinit. Same through the rest of the file.

I am not sure if we need __devinit. I see that __devinit will not have
any effect if CONFIG_HOTPLUG is enabled and CONFIG_HOTPLUG is always
enabled in our configuration. EMIF devices are not hot-pluggable
devices and are always added at boot-time from the board file. They are
on-chip IP modules and dynamic discovery and addition doesn't make
sense for them. So, can't we save some memory by making them __init.

AFAIU, __init doesn't have any effect in a module. However, I can make
that more explicit by using '__init_or_module'. Is that ok?

>
> [...]
>> +	return NULL;
>> +out:
>> +	return emif;
>> +}
>> +#endif
>> +
>>   static struct emif_data * __init get_device_details(
>
> This function also must be __devinit
>
>>   		struct platform_device *pdev)
>>   {
>> @@ -1266,7 +1535,13 @@ static int __init emif_probe(struct platform_device *pdev)
>>   	struct resource		*res;
>>   	int			irq;
>>
>> -	emif = get_device_details(pdev);
>> +#if defined(CONFIG_OF)
>> +	if (pdev->dev.of_node)
>> +		emif = of_get_device_details(pdev->dev.of_node,&pdev->dev);
>> +	else
>> +#endif
>> +		emif = get_device_details(pdev);
>> +
>>   	if (!emif) {
>>   		pr_err("%s: error getting device data\n", __func__);
>>   		goto error;
>> @@ -1643,11 +1918,23 @@ static void __attribute__((unused)) freq_post_notify_handling(void)
>>   	spin_unlock_irqrestore(&emif_lock, irq_state);
>>   }
>>
>> +#if defined(CONFIG_OF)
>> +static const struct of_device_id emif_of_match[] = {
>> +		{ .compatible = "ti,emif-4d" },
>> +		{ .compatible = "ti,emif-4d5" },
>> +		{},
>> +};
>> +MODULE_DEVICE_TABLE(of, emif_of_match);
>> +#endif
>> +
>>   static struct platform_driver emif_driver = {
>>   	.remove		= __exit_p(emif_remove),
>
> Not part of this patch I realize, but this is a bug.  .remove must
> be in the __devexit section and the __devexit_p() wrapper must
> be used.  Similarly, emif_probe must be in the __devinit section.

Again, in our case remove() is not needed unless the driver is built as
a module because the devices will never be un-registered. When it is
built as a module the effect is same for both:

#if defined(MODULE) || defined(CONFIG_HOTPLUG)
#define __devexit_p(x) x
#else
#define __devexit_p(x) NULL
#endif

#ifdef MODULE
#define __exit_p(x) x
#else
#define __exit_p(x) NULL
#endif

>
>>   	.shutdown	= emif_shutdown,
>>   	.driver = {
>>   		.name = "emif",
>> +#if defined(CONFIG_OF)
>> +		.of_match_table = of_match_ptr(emif_of_match),
>> +#endif
>
> The of_match_ptr() macro makes the #if/#endif wrapper redundant.

Ok. I will remove it.

>
> Otherwise, on brief review this patch looks right.

Thanks for the review. Are you ok with the bindings too?

br,
Aneesh


From arnd at arndb.de  Fri Mar  9 07:26:53 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 9 Mar 2012 12:26:53 +0000
Subject: linux-next: manual merge of the arm-soc tree with the omap_dss2
 tree
In-Reply-To: <1331295269.1927.54.camel@deskari>
References: <20120308170048.f1a992bca2ca2d93fa9747bf@canb.auug.org.au>
 <201203091150.11294.arnd@arndb.de> <1331295269.1927.54.camel@deskari>
Message-ID: <201203091226.53749.arnd@arndb.de>

On Friday 09 March 2012, Tomi Valkeinen wrote:
>   On Fri, 2012-03-09 at 11:50 +0000, Arnd Bergmann wrote:
> > On Friday 09 March 2012, Tomi Valkeinen wrote:
> > > On Thu, 2012-03-08 at 16:16 +0000, Arnd Bergmann wrote:
> > > > On Thursday 08 March 2012, Stephen Rothwell wrote:
> > > > > Hi all,
> > > > > 
> > > > > Today's linux-next merge of the arm-soc tree got a conflict in
> > > > > arch/arm/mach-omap1/board-palmtt.c between commit ddba6c7f7ec6 ("OMAP1:
> > > > > pass LCD config with omapfb_set_lcd_config()") from the omap_dss2 tree
> > > > > and commit 2e3ee9f45b3c ("ARM: OMAP1: Move most of plat/io.h into local
> > > > > iomap.h") from the arm-soc tree.
> > > > > 
> > > > > I fixed it up (see below) and can carry the fix as necessary.
> > > > 
> > > > Hi Stephen,
> > > > 
> > > > Thanks for fixing up all the conflicts between arm-soc and omap_dss2.
> > > > I think we should make sure they are resolved in one of the trees before
> > > > the merge window.
> > > 
> > > Do we need to? The conflicts seemed to be trivial ones, like arm-soc
> > > adds/removes something that just happens to be next to something else
> > > that I add/remove.
> > > 
> > > My understanding is that it's better to leave those conflicts than to do
> > > "trickery" to avoid them.
> > 
> > Each of the conflicts is simple enough, but I feel it's worth resolving
> > them in this case because there are a number of them. Looking at them
> > again now, it's probably ok either way -- resolving them now or letting
> > Linus take care of them.
> 
> Florian, do you have an opinion about this?
> 
> Merging omapdss tree through arm-soc would make sense for avoiding
> conflicts, because almost every merge window there are some conflicts as
> I often need to edit arch/arm files also. But I'm not sure if we have
> ever had a conflict in drivers/video.
> 
> But still, it's a video driver, and fbdev tree sounds more suited for a
> video driver.
> 
> So I don't know =). Basically it's ok for me either way also. But it
> would be nice to have a standard way of doing this, instead of, for
> example, merging omapdss sometimes through fbdev, sometimes through
> arm-soc, depending on the conflicts...

Actually, I did not suggest omapdss through arm-soc, the idea was that
that the same branch gets merged into both the fbdev and the arm-soc
trees and let the fbdev tree go to Linus first.

	Arnd


From broonie at opensource.wolfsonmicro.com  Fri Mar  9 06:59:59 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 11:59:59 +0000
Subject: [PATCH v3 00/11] ASoC: add imx-sgtl5000 machine driver working
 with fsl_ssi
In-Reply-To: <20120309071347.GM2499@S2101-09.ap.freescale.net>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <4F5910EE.8090408@freescale.com>
 <20120309011914.GF2499@S2101-09.ap.freescale.net>
 <4F5966DC.6090201@freescale.com>
 <20120309071347.GM2499@S2101-09.ap.freescale.net>
Message-ID: <20120309115956.GF3273@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 03:13:49PM +0800, Shawn Guo wrote:

> My bisect tells that the offending commit is:

>   96acc35 (ASoC: DAPM: Make sure DAPM widget IO ops hold the component mutex)

> But I do not understand why yet.

It'll be deadlocking somewhere I expect - turning on the soft lockup
detector will probably make it obvious.
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From broonie at opensource.wolfsonmicro.com  Fri Mar  9 06:51:41 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 11:51:41 +0000
Subject: [PATCH v3 07/11] ASoC: fsl: check property 'compatible' for the
 machine name
In-Reply-To: <1331225990-27308-8-git-send-email-shawn.guo@linaro.org>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-8-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120309115132.GC3273@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 12:59:46AM +0800, Shawn Guo wrote:

> Check /compatible rather than /model to determine the machine name.
> The p1022ds older device trees get a different /model from the new
> ones, while /compatible is consistent there, so checking /compatible
> will save the bother of detecting older p1022ds device trees.

Applied, thanks.
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From s.hauer at pengutronix.de  Fri Mar  9 05:56:45 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 9 Mar 2012 11:56:45 +0100
Subject: [PATCH v2 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120309105645.GA3852@pengutronix.de>

On Wed, Mar 07, 2012 at 03:33:32PM +0100, Javier Martin wrote:
> The following series have to be applied on top of the following patches:
> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
> 
> As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
> is deprecated and no new patches are accepted for it.
> 
> This series merges this code into the imx-dma.c dmaengine driver.
> 
> Changes since v1:
>  - Merge patch 14 with 01.
>  - Add a proper changelog to each patch of the series.
> 
> [PATCH v2 01/13] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
> [PATCH v2 02/13] dmaengine: imx-dma: remove data member from internal structure.
> [PATCH v2 03/13] dmaengine: imx-dma: remove dma_mode member of internal structure.
> [PATCH v2 04/13] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
> [PATCH v2 05/13] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
> [PATCH v2 06/13] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
> [PATCH v2 07/13] dmaengine: imx-dma: remove sg member from internal structure.
> [PATCH v2 08/13] dmaengine: imx-dma: remove 'in_use' field of 'internal' structure.
> [PATCH v2 09/13] dmaengine: imx-dma: remove 'resbytes' field of 'internal' structure.
> [PATCH v2 10/13] dmaengine: imx-dma: remove internal structure.
> [PATCH v2 11/13] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
> [PATCH v2 12/13] dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and 'dma_clk'.
> [PATCH v2 13/13] dmaengine: imx-dma: use 'dev_dbg' and 'dev_warn' for messages.

I didn't look at the individual patches but only on the end result and
overall it looks good. There are several things left for further cleanup:

- use resources for irq and base address
- use platform device id rather than cpu_is_* to distinguish
  between the different device types.
- request_irq for i.MX21/27 in alloc_chan_resources instead in probe
- Use all available channels. In the time we had dmaengine users and
  legacy API users 8 channels were reserved for the old API and 8
  channels for the dmaengine API.

I think the first three points can be done in a later series, the last
one should be trivial to fix now.

Some comments follow to the individual patches.

And, oh:

Tested-by: Sascha Hauer <s.hauer at pengutronix.de

Thanks for working on this topic, it has long been on my todo list.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar  9 05:29:31 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 9 Mar 2012 11:29:31 +0100
Subject: [RFC] i.MX: drop secondary clocks
In-Reply-To: <20313.52782.832292.580932@ipc1.ka-ro>
References: <1331242949-22780-1-git-send-email-s.hauer@pengutronix.de>
 <20313.52782.832292.580932@ipc1.ka-ro>
Message-ID: <20120309102931.GY3852@pengutronix.de>

On Fri, Mar 09, 2012 at 10:32:30AM +0100, Lothar Wa?mann wrote:
> Hi,
> 
> Sascha Hauer writes:
> > Hi All,
> > 
> > On i.MX we currently have grouped clocks, also known as secondary clocks.
> > These are clocks that get enabled when the primary clock gets enabled.  This
> > doesn't integrate well into the generic clock framework. Also we often return
> > the rate of one clock and really enable/disable another clock. I plan to get
> > rid of these clocks by exposing the individual clocks to the drivers. The
> > following is meant as an example how this can be done. I have a more complete
> > series internally but this conflicts with Richards clk_prepare series.
> > 
> > Thanks to the nature of clk_get we can simply clk_get the individual clocks in
> > the drivers and the current clock implementation will always return the one
> > with con_id = NULL. Then with the generic clk implementation the drivers will
> > finally get the individual clocks.
> > 
> > So unless there are objections I will follow up on this after the next merge
> > window.
> > 
> I think that's a bad idea! Drivers should not have to know intimate
> details about the clock logic of the CPU core they are running on!

They don't have to. There really are different clocks connected to the
devices. If for example you have a look eSDHC Block diagram in the
reference Manual  you'll see that this has three clock inputs. All
we do is to tell the driver about these three clocks which are device
specific and not SoC specific. Which of these clocks are actually
gatetable varies from SoC to SoC. Also on some SoCs two of the three
clocks may be actually the same.

> 
> They should simply request a clock for the unit they operate on and
> the clock core code should figure out which other clocks need to be
> enabled on a specific machine to get the unit working.

Yes, that's what we want to do, except that devices do not need 'a'
clock but several. And the clock core figures out which other clocks
have to be activated, these are the parent clocks.

I also don't really like exposing this to the drivers, but it's a clean
way to do so. A framebuffer driver needs a pixel clock which must be
enabled when the display is turned on. It may also have a register clock
which has to be turned on when we want to access registers. These are
two different clocks and the driver can make use of this (not that we
currently do though...)

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From andrew at lunn.ch  Sat Mar 10 13:01:21 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Sat, 10 Mar 2012 19:01:21 +0100
Subject: [PATCH v6 3/3] clk: basic clock hardware types
In-Reply-To: <1331366064-1273-4-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-4-git-send-email-mturquette@linaro.org>
Message-ID: <20120310180121.GL16608@lunn.ch>

On Fri, Mar 09, 2012 at 11:54:24PM -0800, Mike Turquette wrote:
> Many platforms support simple gateable clocks, fixed-rate clocks,
> adjustable divider clocks and multi-parent multiplexer clocks.

Hi Mike

Please feel free to add:

Reviewed-by: Andrew Lunn <andrew at lunn.ch>
Tested-by: Andrew Lunn <andrew at lunn.ch>

	   Andrew


From sfr at canb.auug.org.au  Fri Mar  9 02:37:32 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 9 Mar 2012 18:37:32 +1100
Subject: linux-next: manual merge of the cpuidle-cons tree with the arm-soc
 tree
Message-ID: <20120309183732.512d3676599da324f4747219@canb.auug.org.au>

Hi Rob,

Today's linux-next merge of the cpuidle-cons tree got a conflict in
arch/arm/mach-at91/cpuidle.c between commit 00482a4078f4 ("ARM: at91:
implement the standby function for pm/cpuidle") from the arm-soc tree and
commit 7a1f6e72dce1 ("ARM: at91: Consolidate time keeping and irq
enable") from the cpuidle-cons tree.

I fixed it up (I think - see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-at91/cpuidle.c
index 555d956,d40b3f3..0000000
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@@ -37,23 -33,15 +33,8 @@@ static int at91_enter_idle(struct cpuid
  			struct cpuidle_driver *drv,
  			       int index)
  {
- 	struct timeval before, after;
- 	int idle_time;
- 
- 	local_irq_disable();
- 	do_gettimeofday(&before);
- 	if (index == 0)
- 		/* Wait for interrupt state */
- 		cpu_do_idle();
- 	else if (index == 1)
- 		at91_standby();
 -	u32 saved_lpr;
 -
 -	__asm__("b 1f; .align 5; 1:\n"
 -	"	mcr p15, 0, r0, c7, c10, 4");	/* drain write buffer */
 -
 -	saved_lpr = sdram_selfrefresh_enable();
 -	cpu_do_idle();
 -	sdram_selfrefresh_disable(saved_lpr);
++	at91_standby();
  
- 	do_gettimeofday(&after);
- 	local_irq_enable();
- 	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
- 			(after.tv_usec - before.tv_usec);
- 
- 	dev->last_residency = idle_time;
  	return index;
  }
  
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From sfr at canb.auug.org.au  Fri Mar  9 01:40:17 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 9 Mar 2012 17:40:17 +1100
Subject: [git pull] Consolidate cpuidle functionality
In-Reply-To: <CAMXH7KEwQM37R++8moXB8Q41_fBXOnVY2hXJGFQmTQ20oeFPEQ@mail.gmail.com>
References: <1330562578-3410-1-git-send-email-rob.lee@linaro.org>
 <87y5reivhb.fsf@ti.com>
 <CAMXH7KEwQM37R++8moXB8Q41_fBXOnVY2hXJGFQmTQ20oeFPEQ@mail.gmail.com>
Message-ID: <20120309174017.081154936f57039b37c50435@canb.auug.org.au>

Hi Rob,

On Thu, 8 Mar 2012 19:58:23 -0600 Rob Lee <rob.lee at linaro.org> wrote:
>
>   git://git.linaro.org/people/rob_lee/linux.git cpuidle_consol_pull
> 
> These changes move various functionality duplicated in platform
> cpuidle drivers to the core cpuidle driver and common arch arm code. Also,
> the irq disabling in the platform code was removed as all calls into
> cpuidle_call_idle() will have already called local_irq_disable().
> 
> This patchset is bisect safe.  Also, the core cpuidle and arch changes of the
> first commit do not require any changes to the arch and platform cpuidle
> drivers, though those arch and platform change should be made to take
> advantage of the new consolidation function.
> 
> Stephen, this patch has been reviewed, tested, and ACK'd per the list above but
> cpuidle maintainer Len Brown has been out on vacation for a couple of weeks so
> I am sending you this pull request as time is running out to get this into
> v3.4.  I've had a brief communication with Andrew Morton about
> this as well so he is aware of this situation.  I am fairly new to the
> community so please let me know if you see anything that needs my attention or
> anything I should be doing differently.

I will add this tree from today.  Lets see if anyone screams.

Thanks for adding your subsystem tree as a participant of linux-next.  As
you may know, this is not a judgment of your code.  The purpose of
linux-next is for integration testing and to lower the impact of
conflicts between subsystems in the next merge window. 

You will need to ensure that the patches/commits in your tree/series have
been:
     * submitted under GPL v2 (or later) and include the Contributor's
	Signed-off-by,
     * posted to the relevant mailing list,
     * reviewed by you (or another maintainer of your subsystem tree),
     * successfully unit tested, and 
     * destined for the current or next Linux merge window.

Basically, this should be just what you would send to Linus (or ask him
to fetch).  It is allowed to be rebased if you deem it necessary.

-- 
Cheers,
Stephen Rothwell 
sfr at canb.auug.org.au

Legal Stuff:
By participating in linux-next, your subsystem tree contributions are
public and will be included in the linux-next trees.  You may be sent
e-mail messages indicating errors or other issues when the
patches/commits from your subsystem tree are merged and tested in
linux-next.  These messages may also be cross-posted to the linux-next
mailing list, the linux-kernel mailing list, etc.  The linux-next tree
project and IBM (my employer) make no warranties regarding the linux-next
project, the testing procedures, the results, the e-mails, etc.  If you
don't agree to these ground rules, let me know and I'll remove your tree
from participation in linux-next.
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From paul at pwsan.com  Mon Mar 12 06:15:08 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 04:15:08 -0600 (MDT)
Subject: [GIT PULL] ARM: OMAP3+: PRM/hwmod: fix and improve I/O chain wakeup
 support
Message-ID: <alpine.DEB.2.00.1203120413530.11332@utopia.booyaka.com>

Hi Tony

The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:

  Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)

are available in the git repository at:

  git://git.pwsan.com/linux-2.6 io_chain_devel_3.4

for you to fetch changes up to efd360a8902101148f4fc6325097b94ae1fbb451:

  ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle (2012-03-12 04:11:48 -0600)


- Paul

----------------------------------------------------------------
Mohan V (1):
      ARM: OMAP3: PM: correct enable/disable of daisy io chain

Rajendra Nayak (1):
      ARM: OMAP4: PRM: Add IO Daisychain support

Tero Kristo (1):
      ARM: OMAP3+: PRM: Enable IO wake up

Vishwanath BS (3):
      ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm file
      ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod mux
      ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle

 arch/arm/mach-omap2/omap_hwmod.c   |   37 +++++++++++++++++++++-
 arch/arm/mach-omap2/pm34xx.c       |   44 --------------------------
 arch/arm/mach-omap2/prcm-common.h  |    8 +++++
 arch/arm/mach-omap2/prm2xxx_3xxx.c |   51 ++++++++++++++++++++++++++++++-
 arch/arm/mach-omap2/prm2xxx_3xxx.h |    2 +
 arch/arm/mach-omap2/prm44xx.c      |   60 +++++++++++++++++++++++++++++++++++-
 arch/arm/mach-omap2/prm44xx.h      |    2 +
 7 files changed, 156 insertions(+), 48 deletions(-)


From jason at lakedaemon.net  Mon Mar 12 10:27:16 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 12 Mar 2012 10:27:16 -0400
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <op.wa197mq94cuzmg@gonzo.lentin.co.uk>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <1331476406-9844-2-git-send-email-jm@lentin.co.uk>
 <20120312030232.GX5050@titan.lakedaemon.net>
 <201203120817.19777.arnd@arndb.de>
 <op.wa197mq94cuzmg@gonzo.lentin.co.uk>
Message-ID: <20120312142716.GA5050@titan.lakedaemon.net>

On Mon, Mar 12, 2012 at 02:22:24PM -0000, Jamie Lentin wrote:
> On Mon, 12 Mar 2012 08:17:19 -0000, Arnd Bergmann <arnd at arndb.de> wrote:
> 
> >On Monday 12 March 2012, Jason Cooper wrote:
> >>> +     dnskw_gpio_register(39, "dnskw:power:sata0", 1);
> >>> +     dnskw_gpio_register(40, "dnskw:power:sata1", 1);
> >>> +
> >>> +     /* Set NAS to turn back on after a power failure */
> >>> +     dnskw_gpio_register(37, "dnskw:power:recover", 1);
> >>> +}
> >>> +
> >>
> >>I doubt this board is the only one that wants to be added while the
> >>conversion to devicetree is progressing.  It makes more sense to me to
> >>break the above out to a separate file, eg board-dnskw.c.  I'll follow
> >>and break out the dreamplug code to board-dreamplug.c.  Otherwise, I see
> >>board-dt.c becoming a long mess.
> >>
> >>Arnd, sound okay to you?
> >
> >Either way is fine with me. I personally wouldn't expect many more boards
> >to come in before the DT conversion has mostly completed, but I guess you
> >have a better feeling for what other hardware is out there that people
> >are interested in.
> >
> 
> It probably depends on how easy it is to add the gpiochips into
> devicetree. Being able to put the LED, buttons and fans in
> devicetree would make board-dt.c much more manageable. I started to
> look into it and wasn't immediately obvious, but will have a closer
> look.
> 
> Happy to resubmit, breaking it out into a board-dnskw.c though.

Yeah, let's go ahead and do that.  pinmux and the above are going to take
a while to sort out.  In the mean time, there's:

sheevaplug
guruplug
guruplug-serverplus
Lacie-*
Seagate-*
rd-boards-*

just to name a few.  Plus it'll give me something to do while we wait
for pinmux/common clock to land.

thx,

Jason.


From shawn.guo at linaro.org  Mon Mar 12 07:58:47 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 12 Mar 2012 19:58:47 +0800
Subject: [PATCH v4] ASoC: add imx-sgtl5000 machine driver working with fsl_ssi
Message-ID: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>

Changes since v3:
 * Change imx compatible to "fsl,imx21-ssi"
 * Leave locking issue as a FIXME for Timur to sort out separately

---
Shawn Guo (10):
      ASoC: fsl: separate SSI and DMA Kconfig options
      ASoC: imx: merge sound/soc/imx into sound/soc/fsl
      ASoC: fsl: rename imx-pcm Kconfig options and filename
      ASoC: fsl: create fsl_utils to accommodate the common functions
      ASoC: fsl: remove helper fsl_asoc_get_codec_dev_name
      ASoC: fsl: check property 'compatible' for the machine name
      ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
      ASoC: fsl: remove the fatal error checking on codec-handle
      ASoC: fsl: let fsl_ssi work with imx pcm and machine drivers
      ASoC: fsl: add imx-sgtl5000 machine driver

 .../bindings/sound/imx-audio-sgtl5000.txt          |   24 +++
 arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig   |    1 +
 arch/powerpc/configs/mpc85xx_defconfig             |    1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig         |    1 +
 sound/soc/Kconfig                                  |    1 -
 sound/soc/Makefile                                 |    1 -
 sound/soc/fsl/Kconfig                              |  124 ++++++++++++-
 sound/soc/fsl/Makefile                             |   29 +++-
 sound/soc/{imx => fsl}/eukrea-tlv320.c             |    2 +-
 sound/soc/fsl/fsl_ssi.c                            |  140 +++++++++++----
 sound/soc/fsl/fsl_utils.c                          |   91 ++++++++++
 sound/soc/fsl/fsl_utils.h                          |   26 +++
 sound/soc/{imx => fsl}/imx-audmux.c                |    0
 sound/soc/{imx => fsl}/imx-audmux.h                |    0
 .../{imx/imx-pcm-dma-mx2.c => fsl/imx-pcm-dma.c}   |    0
 sound/soc/{imx => fsl}/imx-pcm-fiq.c               |    0
 sound/soc/{imx => fsl}/imx-pcm.c                   |    0
 sound/soc/{imx => fsl}/imx-pcm.h                   |    0
 sound/soc/fsl/imx-sgtl5000.c                       |  177 ++++++++++++++++++
 sound/soc/{imx => fsl}/imx-ssi.c                   |    2 +-
 sound/soc/{imx => fsl}/imx-ssi.h                   |    0
 sound/soc/fsl/mpc8610_hpcd.c                       |  168 ++----------------
 sound/soc/{imx => fsl}/mx27vis-aic32x4.c           |    0
 sound/soc/fsl/p1022_ds.c                           |  190 ++------------------
 sound/soc/{imx => fsl}/phycore-ac97.c              |    0
 sound/soc/{imx => fsl}/wm1133-ev1.c                |    0
 sound/soc/imx/Kconfig                              |   79 --------
 sound/soc/imx/Makefile                             |   22 ---
 28 files changed, 604 insertions(+), 475 deletions(-)


From shawn.guo at linaro.org  Mon Mar 12 07:58:51 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 12 Mar 2012 19:58:51 +0800
Subject: [PATCH v4 04/10] ASoC: fsl: create fsl_utils to accommodate the
 common functions
In-Reply-To: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331553537-19789-5-git-send-email-shawn.guo@linaro.org>

There is some amount of code duplication between mpc8610_hpcd and
p1022_ds machine drivers, and the same code will be duplicated again
when another new machine driver is added.  The patch creates fsl_utils
to accommodate the common functions to stop the code duplication.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/Kconfig        |    5 ++
 sound/soc/fsl/Makefile       |    2 +
 sound/soc/fsl/fsl_utils.c    |  135 ++++++++++++++++++++++++++++++++++++
 sound/soc/fsl/fsl_utils.h    |   27 +++++++
 sound/soc/fsl/mpc8610_hpcd.c |  157 +++---------------------------------------
 sound/soc/fsl/p1022_ds.c     |  149 +++-------------------------------------
 6 files changed, 189 insertions(+), 286 deletions(-)
 create mode 100644 sound/soc/fsl/fsl_utils.c
 create mode 100644 sound/soc/fsl/fsl_utils.h

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index e3f7509..535ee73 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,6 +1,9 @@
 config SND_SOC_FSL_SSI
 	tristate
 
+config SND_SOC_FSL_UTILS
+	tristate
+
 menuconfig SND_POWERPC_SOC
 	tristate "SoC Audio for Freescale PowerPC CPUs"
 	depends on FSL_SOC
@@ -26,6 +29,7 @@ config SND_SOC_MPC8610_HPCD
 	# I2C is necessary for the CS4270 driver
 	depends on MPC8610_HPCD && I2C
 	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
 	select SND_SOC_POWERPC_DMA
 	select SND_SOC_CS4270
 	select SND_SOC_CS4270_VD33_ERRATA
@@ -38,6 +42,7 @@ config SND_SOC_P1022_DS
 	# I2C is necessary for the WM8776 driver
 	depends on P1022_DS && I2C
 	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
 	select SND_SOC_POWERPC_DMA
 	select SND_SOC_WM8776
 	default y if P1022_DS
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index f031409..fbdbed0 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -8,8 +8,10 @@ obj-$(CONFIG_SND_SOC_P1022_DS) += snd-soc-p1022-ds.o
 
 # Freescale PowerPC SSI/DMA Platform Support
 snd-soc-fsl-ssi-objs := fsl_ssi.o
+snd-soc-fsl-utils-objs := fsl_utils.o
 snd-soc-fsl-dma-objs := fsl_dma.o
 obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
 obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 
 # MPC5200 Platform Support
diff --git a/sound/soc/fsl/fsl_utils.c b/sound/soc/fsl/fsl_utils.c
new file mode 100644
index 0000000..4370c28
--- /dev/null
+++ b/sound/soc/fsl/fsl_utils.c
@@ -0,0 +1,135 @@
+/**
+ * Freescale ALSA SoC Machine driver utility
+ *
+ * Author: Timur Tabi <timur at freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_i2c.h>
+#include <sound/soc.h>
+
+#include "fsl_utils.h"
+
+/**
+ * fsl_asoc_get_codec_dev_name - determine the dev_name for a codec node
+ *
+ * @np: pointer to the I2C device tree node
+ * @buf: buffer to be filled with the dev_name of the I2C device
+ * @len: the length of the buffer
+ *
+ * This function determines the dev_name for an I2C node.  This is the name
+ * that would be returned by dev_name() if this device_node were part of a
+ * 'struct device'  It's ugly and hackish, but it works.
+ *
+ * The dev_name for such devices include the bus number and I2C address. For
+ * example, "cs4270.0-004f".
+ */
+int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len)
+{
+	const u32 *iprop;
+	u32 addr;
+	char temp[DAI_NAME_SIZE];
+	struct i2c_client *i2c;
+
+	of_modalias_node(np, temp, DAI_NAME_SIZE);
+
+	iprop = of_get_property(np, "reg", NULL);
+	if (!iprop)
+		return -EINVAL;
+
+	addr = be32_to_cpup(iprop);
+
+	/* We need the adapter number */
+	i2c = of_find_i2c_device_by_node(np);
+	if (!i2c) {
+		put_device(&i2c->dev);
+		return -ENODEV;
+	}
+
+	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
+	put_device(&i2c->dev);
+
+	return 0;
+}
+EXPORT_SYMBOL(fsl_asoc_get_codec_dev_name);
+
+/**
+ * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
+ *
+ * @ssi_np: pointer to the SSI device tree node
+ * @name: name of the phandle pointing to the dma channel
+ * @dai: ASoC DAI link pointer to be filled with platform_name
+ * @dma_channel_id: dma channel id to be returned
+ * @dma_id: dma id to be returned
+ *
+ * This function determines the dma and channel id for given SSI node.  It
+ * also discovers the platform_name for the ASoC DAI link.
+ */
+int fsl_asoc_get_dma_channel(struct device_node *ssi_np,
+			     const char *name,
+			     struct snd_soc_dai_link *dai,
+			     unsigned int *dma_channel_id,
+			     unsigned int *dma_id)
+{
+	struct resource res;
+	struct device_node *dma_channel_np, *dma_np;
+	const u32 *iprop;
+	int ret;
+
+	dma_channel_np = of_parse_phandle(ssi_np, name, 0);
+	if (!dma_channel_np)
+		return -EINVAL;
+
+	if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) {
+		of_node_put(dma_channel_np);
+		return -EINVAL;
+	}
+
+	/* Determine the dev_name for the device_node.  This code mimics the
+	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
+	 * the dev_name() of the device to match the platform (DMA) device with
+	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
+	 * now).
+	 *
+	 * dai->platform name should already point to an allocated buffer.
+	 */
+	ret = of_address_to_resource(dma_channel_np, 0, &res);
+	if (ret) {
+		of_node_put(dma_channel_np);
+		return ret;
+	}
+	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
+		 (unsigned long long) res.start, dma_channel_np->name);
+
+	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
+	if (!iprop) {
+		of_node_put(dma_channel_np);
+		return -EINVAL;
+	}
+	*dma_channel_id = be32_to_cpup(iprop);
+
+	dma_np = of_get_parent(dma_channel_np);
+	iprop = of_get_property(dma_np, "cell-index", NULL);
+	if (!iprop) {
+		of_node_put(dma_np);
+		return -EINVAL;
+	}
+	*dma_id = be32_to_cpup(iprop);
+
+	of_node_put(dma_np);
+	of_node_put(dma_channel_np);
+
+	return 0;
+}
+EXPORT_SYMBOL(fsl_asoc_get_dma_channel);
+
+MODULE_AUTHOR("Timur Tabi <timur at freescale.com>");
+MODULE_DESCRIPTION("Freescale ASoC utility code");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/fsl/fsl_utils.h b/sound/soc/fsl/fsl_utils.h
new file mode 100644
index 0000000..44d1436
--- /dev/null
+++ b/sound/soc/fsl/fsl_utils.h
@@ -0,0 +1,27 @@
+/**
+ * Freescale ALSA SoC Machine driver utility
+ *
+ * Author: Timur Tabi <timur at freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef _FSL_UTILS_H
+#define _FSL_UTILS_H
+
+#define DAI_NAME_SIZE	32
+
+struct snd_soc_dai_link;
+struct device_node;
+
+int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len);
+int fsl_asoc_get_dma_channel(struct device_node *ssi_np, const char *name,
+			     struct snd_soc_dai_link *dai,
+			     unsigned int *dma_channel_id,
+			     unsigned int *dma_id);
+
+#endif /* _FSL_UTILS_H */
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index fcf9302..7ead1e5 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -14,18 +14,16 @@
 #include <linux/interrupt.h>
 #include <linux/of_device.h>
 #include <linux/slab.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 #include <asm/fsl_guts.h>
 
 #include "fsl_dma.h"
 #include "fsl_ssi.h"
+#include "fsl_utils.h"
 
 /* There's only one global utilities register */
 static phys_addr_t guts_phys;
 
-#define DAI_NAME_SIZE	32
-
 /**
  * mpc8610_hpcd_data: machine-specific ASoC device data
  *
@@ -181,141 +179,6 @@ static struct snd_soc_ops mpc8610_hpcd_ops = {
 };
 
 /**
- * get_node_by_phandle_name - get a node by its phandle name
- *
- * This function takes a node, the name of a property in that node, and a
- * compatible string.  Assuming the property is a phandle to another node,
- * it returns that node, (optionally) if that node is compatible.
- *
- * If the property is not a phandle, or the node it points to is not compatible
- * with the specific string, then NULL is returned.
- */
-static struct device_node *get_node_by_phandle_name(struct device_node *np,
-					       const char *name,
-					       const char *compatible)
-{
-	const phandle *ph;
-	int len;
-
-	ph = of_get_property(np, name, &len);
-	if (!ph || (len != sizeof(phandle)))
-		return NULL;
-
-	np = of_find_node_by_phandle(*ph);
-	if (!np)
-		return NULL;
-
-	if (compatible && !of_device_is_compatible(np, compatible)) {
-		of_node_put(np);
-		return NULL;
-	}
-
-	return np;
-}
-
-/**
- * get_parent_cell_index -- return the cell-index of the parent of a node
- *
- * Return the value of the cell-index property of the parent of the given
- * node.  This is used for DMA channel nodes that need to know the DMA ID
- * of the controller they are on.
- */
-static int get_parent_cell_index(struct device_node *np)
-{
-	struct device_node *parent = of_get_parent(np);
-	const u32 *iprop;
-
-	if (!parent)
-		return -1;
-
-	iprop = of_get_property(parent, "cell-index", NULL);
-	of_node_put(parent);
-
-	if (!iprop)
-		return -1;
-
-	return be32_to_cpup(iprop);
-}
-
-/**
- * codec_node_dev_name - determine the dev_name for a codec node
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270.0-004f".
- */
-static int codec_node_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	int addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c)
-		return -ENODEV;
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-
-	return 0;
-}
-
-static int get_dma_channel(struct device_node *ssi_np,
-			   const char *name,
-			   struct snd_soc_dai_link *dai,
-			   unsigned int *dma_channel_id,
-			   unsigned int *dma_id)
-{
-	struct resource res;
-	struct device_node *dma_channel_np;
-	const u32 *iprop;
-	int ret;
-
-	dma_channel_np = get_node_by_phandle_name(ssi_np, name,
-						  "fsl,ssi-dma-channel");
-	if (!dma_channel_np)
-		return -EINVAL;
-
-	/* Determine the dev_name for the device_node.  This code mimics the
-	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
-	 * the dev_name() of the device to match the platform (DMA) device with
-	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
-	 * now).
-	 *
-	 * dai->platform name should already point to an allocated buffer.
-	 */
-	ret = of_address_to_resource(dma_channel_np, 0, &res);
-	if (ret)
-		return ret;
-	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
-		 (unsigned long long) res.start, dma_channel_np->name);
-
-	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
-	if (!iprop) {
-		of_node_put(dma_channel_np);
-		return -EINVAL;
-	}
-
-	*dma_channel_id = be32_to_cpup(iprop);
-	*dma_id = get_parent_cell_index(dma_channel_np);
-	of_node_put(dma_channel_np);
-
-	return 0;
-}
-
-/**
  * mpc8610_hpcd_probe: platform probe function for the machine driver
  *
  * Although this is a machine driver, the SSI node is the "master" node with
@@ -353,8 +216,8 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 	machine_data->dai[0].ops = &mpc8610_hpcd_ops;
 
 	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = codec_node_dev_name(codec_np, machine_data->codec_name,
-				  DAI_NAME_SIZE);
+	ret = fsl_asoc_get_codec_dev_name(codec_np, machine_data->codec_name,
+					  DAI_NAME_SIZE);
 	if (ret) {
 		dev_err(&pdev->dev, "invalid codec node %s\n",
 			codec_np->full_name);
@@ -458,9 +321,10 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 
 	/* Find the playback DMA channel to use. */
 	machine_data->dai[0].platform_name = machine_data->platform_name[0];
-	ret = get_dma_channel(np, "fsl,playback-dma", &machine_data->dai[0],
-			      &machine_data->dma_channel_id[0],
-			      &machine_data->dma_id[0]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma",
+				       &machine_data->dai[0],
+				       &machine_data->dma_channel_id[0],
+				       &machine_data->dma_id[0]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
 		goto error;
@@ -468,9 +332,10 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 
 	/* Find the capture DMA channel to use. */
 	machine_data->dai[1].platform_name = machine_data->platform_name[1];
-	ret = get_dma_channel(np, "fsl,capture-dma", &machine_data->dai[1],
-			      &machine_data->dma_channel_id[1],
-			      &machine_data->dma_id[1]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma",
+				       &machine_data->dai[1],
+				       &machine_data->dma_channel_id[1],
+				       &machine_data->dma_id[1]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
 		goto error;
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index d32ec46..60f7bb8 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -14,12 +14,12 @@
 #include <linux/interrupt.h>
 #include <linux/of_device.h>
 #include <linux/slab.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 #include <asm/fsl_guts.h>
 
 #include "fsl_dma.h"
 #include "fsl_ssi.h"
+#include "fsl_utils.h"
 
 /* P1022-specific PMUXCR and DMUXCR bit definitions */
 
@@ -57,8 +57,6 @@ static inline void guts_set_dmuxcr(struct ccsr_guts_85xx __iomem *guts,
 /* There's only one global utilities register */
 static phys_addr_t guts_phys;
 
-#define DAI_NAME_SIZE	32
-
 /**
  * machine_data: machine-specific ASoC device data
  *
@@ -191,136 +189,6 @@ static struct snd_soc_ops p1022_ds_ops = {
 };
 
 /**
- * get_node_by_phandle_name - get a node by its phandle name
- *
- * This function takes a node, the name of a property in that node, and a
- * compatible string.  Assuming the property is a phandle to another node,
- * it returns that node, (optionally) if that node is compatible.
- *
- * If the property is not a phandle, or the node it points to is not compatible
- * with the specific string, then NULL is returned.
- */
-static struct device_node *get_node_by_phandle_name(struct device_node *np,
-	const char *name, const char *compatible)
-{
-	np = of_parse_phandle(np, name, 0);
-	if (!np)
-		return NULL;
-
-	if (!of_device_is_compatible(np, compatible)) {
-		of_node_put(np);
-		return NULL;
-	}
-
-	return np;
-}
-
-/**
- * get_parent_cell_index -- return the cell-index of the parent of a node
- *
- * Return the value of the cell-index property of the parent of the given
- * node.  This is used for DMA channel nodes that need to know the DMA ID
- * of the controller they are on.
- */
-static int get_parent_cell_index(struct device_node *np)
-{
-	struct device_node *parent = of_get_parent(np);
-	const u32 *iprop;
-	int ret = -1;
-
-	if (!parent)
-		return -1;
-
-	iprop = of_get_property(parent, "cell-index", NULL);
-	if (iprop)
-		ret = be32_to_cpup(iprop);
-
-	of_node_put(parent);
-
-	return ret;
-}
-
-/**
- * codec_node_dev_name - determine the dev_name for a codec node
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270-codec.0-004f".
- */
-static int codec_node_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	int addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c)
-		return -ENODEV;
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-
-	return 0;
-}
-
-static int get_dma_channel(struct device_node *ssi_np,
-			   const char *name,
-			   struct snd_soc_dai_link *dai,
-			   unsigned int *dma_channel_id,
-			   unsigned int *dma_id)
-{
-	struct resource res;
-	struct device_node *dma_channel_np;
-	const u32 *iprop;
-	int ret;
-
-	dma_channel_np = get_node_by_phandle_name(ssi_np, name,
-						  "fsl,ssi-dma-channel");
-	if (!dma_channel_np)
-		return -EINVAL;
-
-	/* Determine the dev_name for the device_node.  This code mimics the
-	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
-	 * the dev_name() of the device to match the platform (DMA) device with
-	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
-	 * now).
-	 *
-	 * dai->platform name should already point to an allocated buffer.
-	 */
-	ret = of_address_to_resource(dma_channel_np, 0, &res);
-	if (ret) {
-		of_node_put(dma_channel_np);
-		return ret;
-	}
-	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
-		 (unsigned long long) res.start, dma_channel_np->name);
-
-	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
-	if (!iprop) {
-		of_node_put(dma_channel_np);
-		return -EINVAL;
-	}
-
-	*dma_channel_id = be32_to_cpup(iprop);
-	*dma_id = get_parent_cell_index(dma_channel_np);
-	of_node_put(dma_channel_np);
-
-	return 0;
-}
-
-/**
  * p1022_ds_probe: platform probe function for the machine driver
  *
  * Although this is a machine driver, the SSI node is the "master" node with
@@ -358,7 +226,8 @@ static int p1022_ds_probe(struct platform_device *pdev)
 	mdata->dai[0].ops = &p1022_ds_ops;
 
 	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = codec_node_dev_name(codec_np, mdata->codec_name, DAI_NAME_SIZE);
+	ret = fsl_asoc_get_codec_dev_name(codec_np, mdata->codec_name,
+					  DAI_NAME_SIZE);
 	if (ret) {
 		dev_err(&pdev->dev, "invalid codec node %s\n",
 			codec_np->full_name);
@@ -454,9 +323,9 @@ static int p1022_ds_probe(struct platform_device *pdev)
 
 	/* Find the playback DMA channel to use. */
 	mdata->dai[0].platform_name = mdata->platform_name[0];
-	ret = get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
-			      &mdata->dma_channel_id[0],
-			      &mdata->dma_id[0]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
+				       &mdata->dma_channel_id[0],
+				       &mdata->dma_id[0]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
 		goto error;
@@ -464,9 +333,9 @@ static int p1022_ds_probe(struct platform_device *pdev)
 
 	/* Find the capture DMA channel to use. */
 	mdata->dai[1].platform_name = mdata->platform_name[1];
-	ret = get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
-			      &mdata->dma_channel_id[1],
-			      &mdata->dma_id[1]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
+				       &mdata->dma_channel_id[1],
+				       &mdata->dma_id[1]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
 		goto error;
-- 
1.7.5.4



From shawn.guo at linaro.org  Mon Mar 12 07:58:55 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 12 Mar 2012 19:58:55 +0800
Subject: [PATCH v4 08/10] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331553537-19789-9-git-send-email-shawn.guo@linaro.org>

As Documentation/devicetree/bindings/powerpc/fsl/ssi.txt documented,
codec-handle is an optional property, so missing it should not be a
fatal error.

More importantly, the imx machine drivers to be added working with
fsl_ssi will not have this property, as they use new ASoC machine
driver binding mechanism.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index db9a734..0192c02 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -642,12 +642,6 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 	if (!of_device_is_available(np))
 		return -ENODEV;
 
-	/* Check for a codec-handle property. */
-	if (!of_get_property(np, "codec-handle", NULL)) {
-		dev_err(&pdev->dev, "missing codec-handle property\n");
-		return -ENODEV;
-	}
-
 	/* We only support the SSI in "I2S Slave" mode */
 	sprop = of_get_property(np, "fsl,mode", NULL);
 	if (!sprop || strcmp(sprop, "i2s-slave")) {
-- 
1.7.5.4



From linux at arm.linux.org.uk  Mon Mar 12 06:03:45 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 12 Mar 2012 10:03:45 +0000
Subject: [PATCH] serial: PL011: clear pending interrupts
In-Reply-To: <CAAMvbhF7-5FyzjgtK7EjFZSJg4KBxdMdd1jnTRTLA-LnsVhKyw@mail.gmail.com>
References: <1331540750-25697-1-git-send-email-linus.walleij@stericsson.com>
 <CAAMvbhF7-5FyzjgtK7EjFZSJg4KBxdMdd1jnTRTLA-LnsVhKyw@mail.gmail.com>
Message-ID: <20120312100345.GX17370@n2100.arm.linux.org.uk>

On Mon, Mar 12, 2012 at 09:27:28AM +0000, James Courtier-Dutton wrote:
> On 12 March 2012 08:25, Linus Walleij <linus.walleij at stericsson.com> wrote:
> > From: Linus Walleij <linus.walleij at linaro.org>
> >
> > Chanho Min reported that when the boot loader transfers
> > control to the kernel, there may be pending interrupts
> > causing the UART to lock up in an eternal loop trying to
> > pick tokens from the FIFO (since the RX interrupt flag
> > indicates there are tokens) while in practice there are
> > no tokens - in fact there is only a pending IRQ flag.
> >
> 
> I might be off base here, because I don't know this particular UART,
> but if an IRQ routine is called because the RX interrupt flag is set,
> shouldn't the IRQ routine be written in such a way that it can never
> lock up.

The problem is that there are two flags:

1. The receiver interrupt status flags
2. The fifo status flags

It appears that there's a condition where the receiver interrupt flags can
indicate that characters are pending, but the status flags say that there
are no characters pending in the receive buffer.

This occurs because it seems there's a hardware bug when switching from
FIFO mode to non-FIFO mode - this causes previously received characters
to be hidden from the FIFO status flags.


From arnd at arndb.de  Mon Mar 12 04:11:22 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 12 Mar 2012 08:11:22 +0000
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <20120312031751.GY5050@titan.lakedaemon.net>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <201203111746.09757.arnd@arndb.de>
 <20120312031751.GY5050@titan.lakedaemon.net>
Message-ID: <201203120811.23137.arnd@arndb.de>

On Monday 12 March 2012, Jason Cooper wrote:
> > Or even use the ranges property to remap everything into
> > a simpler address range:
> > 
> >       ocp at f1000000 {
> >               compatible = "simple-bus";
> >               ranges = <0 0xf1000000 0x1000000>;
> >               #address-cells = 1;
> >               #size-cells = 1;
> > 
> >               serial at 12000 {
> >                       reg = <0x12000 0x100>;
> >                       ...
> >               };
> > 
> >               ...
> >       };
> 
> Okay, that's pretty slick.  The wdt and intc are at 0xfed00000, is that
> another ocp bus?  Or, am I missing something?

If they are on those addresses, yes. If you have a data sheet, you should
look at what the buses are named there, "ocp" was just an example and I
took that name from the <mach/kirkwood.h> file.

It does seem though that the 0xfed00000 address is where Linux maps
the same 0xf1000000 range in its own virtual address space, so it's
not something that should appear in the device tree.

	Arnd


From olof at lixom.net  Sun Mar 11 22:02:10 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 11 Mar 2012 19:02:10 -0700
Subject: [PATCH 2/2] ARM: at91: Use proper __iomem annotations
In-Reply-To: <1331405095-3299-1-git-send-email-alan@signal11.us>
References: <1331405049-3186-1-git-send-email-alan@signal11.us>
 <1331405095-3299-1-git-send-email-alan@signal11.us>
Message-ID: <CAOesGMgBGcFuu8Vj=Y1rqowZeDvcT75745wq19COda3E0i3mWQ@mail.gmail.com>

Hi,

On Sat, Mar 10, 2012 at 10:44 AM, Alan Ott <alan at signal11.us> wrote:
> diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
> index 2d0e4e9..91375e2 100644
> --- a/arch/arm/mach-at91/include/mach/hardware.h
> +++ b/arch/arm/mach-at91/include/mach/hardware.h
> @@ -75,8 +75,12 @@
> ?* to 0xFEF78000 .. 0xFF000000. ?(544Kb)
> ?*/
> ?#define AT91_IO_PHYS_BASE ? ? ?0xFFF78000
> +#ifdef __ASSEMBLER__
> ?#define AT91_IO_VIRT_BASE ? ? ?(0xFF000000 - AT91_IO_SIZE)
> ?#else
> +#define AT91_IO_VIRT_BASE ? ? ?(void __iomem *)(0xFF000000 - AT91_IO_SIZE)
> +#endif
> +#else

This can use the IOMEM()-style macro instead, Rob Herring just moved
those to a common header file (not yet in any tree though).


-Olof


From nsekhar at ti.com  Sun Mar 11 01:10:34 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Sun, 11 Mar 2012 06:10:34 +0000
Subject: [GIT PULL] DaVinci DM644x video display support
In-Reply-To: <CAOesGMhcowDuD9FDUG8cMy-a7s-43Ch-=WWjNvrmCtS6+3=t6g@mail.gmail.com>
References: <DF0F476B391FA8409C78302C7BA518B6317EEB34@DBDE01.ent.ti.com>
 <CAOesGMhcowDuD9FDUG8cMy-a7s-43Ch-=WWjNvrmCtS6+3=t6g@mail.gmail.com>
Message-ID: <DF0F476B391FA8409C78302C7BA518B6317F13C4@DBDE01.ent.ti.com>

Hi Olof,

On Sat, Mar 10, 2012 at 22:00:18, Olof Johansson wrote:
> On Thu, Mar 8, 2012 at 11:23 AM, Nori, Sekhar <nsekhar at ti.com> wrote:

[...]

> > The following changes since commit 3a034af7c1a3c55014eeb15a9c9430e9f72810e4:
> > ?Arnd Bergmann (1):
> > ? ? ? ?Merge branch 'next/fixes-non-critical' into for-next
> 
> It looks like this branch is based on the contents of the for-next
> branch. That's not a stable base so I can't pull it.
> 
> If you need it to build on contents already in arm-soc, you need to
> base it on either your own cleanup branch, or the aggregate next/*
> branch in arm-soc. for-next is rebuilt, and is never sent up to Linus
> in it's current form.
> 
> Since you said they require the cleanup branch as a base, please
> rebase them on top of next/cleanup instead.

Thanks for the feedback. I will re-submit this pull request.

Regards,
Sekhar


From shawn.guo at linaro.org  Mon Mar 12 07:58:57 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 12 Mar 2012 19:58:57 +0800
Subject: [PATCH v4 10/10] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331553537-19789-11-git-send-email-shawn.guo@linaro.org>

This is the initial imx-sgtl5000 machine driver support with only
playback dai link implemented.  More features can be added on top
of it later.

It's a device tree only machine driver working with fsl_ssi driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 .../bindings/sound/imx-audio-sgtl5000.txt          |   24 +++
 sound/soc/fsl/Kconfig                              |   12 ++
 sound/soc/fsl/Makefile                             |    2 +
 sound/soc/fsl/imx-sgtl5000.c                       |  177 ++++++++++++++++++++
 4 files changed, 215 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
 create mode 100644 sound/soc/fsl/imx-sgtl5000.c

diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
new file mode 100644
index 0000000..421a374
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
@@ -0,0 +1,24 @@
+Freescale i.MX audio complex with SGTL5000 codec
+
+Required properties:
+- compatible : "fsl,imx-audio-sgtl5000"
+- model : The user-visible name of this sound complex
+- ssi-controller : The phandle of the i.MX SSI controller
+- audio-codec : The phandle of the SGTL5000 audio codec
+- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
+- mux-ext-port : The external port of the i.MX audio muxer
+
+Note: The AUDMUX port numbering should start at 1, which is consistent with
+hardware manual.
+
+Example:
+
+sound {
+	compatible = "fsl,imx51-babbage-sgtl5000",
+		     "fsl,imx-audio-sgtl5000";
+	model = "imx51-babbage-sgtl5000";
+	ssi-controller = <&ssi1>;
+	audio-codec = <&sgtl5000>;
+	mux-int-port = <1>;
+	mux-ext-port = <3>;
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 535ee73..aa14fc9 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -164,4 +164,16 @@ config SND_SOC_EUKREA_TLV320
 	  Enable I2S based access to the TLV320AIC23B codec attached
 	  to the SSI interface
 
+config SND_SOC_IMX_SGTL5000
+	tristate "SoC Audio support for i.MX boards with sgtl5000"
+	depends on OF && I2C
+	select SND_SOC_SGTL5000
+	select SND_SOC_IMX_PCM_DMA
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
+	help
+	  Say Y if you want to add support for SoC audio on an i.MX board with
+	  a sgtl5000 codec.
+
 endif # SND_IMX_SOC
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index fbdbed0..638d385 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -40,8 +40,10 @@ snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
 snd-soc-phycore-ac97-objs := phycore-ac97.o
 snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
 snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
 
 obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
 obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
 obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
 obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
+obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
diff --git a/sound/soc/fsl/imx-sgtl5000.c b/sound/soc/fsl/imx-sgtl5000.c
new file mode 100644
index 0000000..3786b61
--- /dev/null
+++ b/sound/soc/fsl/imx-sgtl5000.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <sound/soc.h>
+
+#include "../codecs/sgtl5000.h"
+#include "imx-audmux.h"
+
+#define DAI_NAME_SIZE	32
+
+struct imx_sgtl5000_data {
+	struct snd_soc_dai_link dai;
+	struct snd_soc_card card;
+	char codec_dai_name[DAI_NAME_SIZE];
+	char platform_name[DAI_NAME_SIZE];
+	unsigned int clk_frequency;
+};
+
+static int imx_sgtl5000_dai_init(struct snd_soc_pcm_runtime *rtd)
+{
+	struct imx_sgtl5000_data *data = container_of(rtd->card,
+					struct imx_sgtl5000_data, card);
+	struct device *dev = rtd->card->dev;
+	int ret;
+
+	ret = snd_soc_dai_set_sysclk(rtd->codec_dai, SGTL5000_SYSCLK,
+				     data->clk_frequency, SND_SOC_CLOCK_IN);
+	if (ret) {
+		dev_err(dev, "could not set codec driver clock params\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __devinit imx_sgtl5000_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *ssi_np, *codec_np;
+	struct platform_device *ssi_pdev;
+	struct imx_sgtl5000_data *data;
+	int int_port, ext_port;
+	int ret;
+
+	ret = of_property_read_u32(np, "mux-int-port", &int_port);
+	if (ret) {
+		dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
+		return ret;
+	}
+	ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
+	if (ret) {
+		dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
+		return ret;
+	}
+
+	/*
+	 * The port numbering in the hardware manual starts at 1, while
+	 * the audmux API expects it starts at 0.
+	 */
+	int_port--;
+	ext_port--;
+	ret = imx_audmux_v2_configure_port(int_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TFSDIR |
+			IMX_AUDMUX_V2_PTCR_TCLKDIR,
+			IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
+	if (ret) {
+		dev_err(&pdev->dev, "audmux internal port setup failed\n");
+		return ret;
+	}
+	imx_audmux_v2_configure_port(ext_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TCSEL(int_port),
+			IMX_AUDMUX_V2_PDCR_RXDSEL(int_port));
+	if (ret) {
+		dev_err(&pdev->dev, "audmux external port setup failed\n");
+		return ret;
+	}
+
+	ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
+	codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
+	if (!ssi_np || !codec_np) {
+		dev_err(&pdev->dev, "phandle missing or invalid\n");
+		return -EINVAL;
+	}
+
+	ssi_pdev = of_find_device_by_node(ssi_np);
+	if (!ssi_pdev) {
+		dev_err(&pdev->dev, "failed to find SSI platform device\n");
+		return -EINVAL;
+	}
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	ret = of_property_read_u32(codec_np, "clock-frequency",
+				   &data->clk_frequency);
+	if (ret) {
+		dev_err(&pdev->dev, "clock-frequency missing or invalid\n");
+		return ret;
+	}
+
+	data->dai.name = "HiFi";
+	data->dai.stream_name = "HiFi";
+	data->dai.codec_dai_name = "sgtl5000";
+	data->dai.codec_of_node = codec_np;
+	data->dai.cpu_dai_name = dev_name(&ssi_pdev->dev);
+	data->dai.platform_name = "imx-pcm-audio";
+	data->dai.init = &imx_sgtl5000_dai_init;
+	data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+			    SND_SOC_DAIFMT_CBM_CFM;
+
+	data->card.dev = &pdev->dev;
+	ret = snd_soc_of_parse_card_name(&data->card, "model");
+	if (ret)
+		return ret;
+	data->card.num_links = 1;
+	data->card.dai_link = &data->dai;
+
+	ret = snd_soc_register_card(&data->card);
+	if (ret) {
+		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, data);
+	of_node_put(ssi_np);
+	of_node_put(codec_np);
+
+	return 0;
+}
+
+static int __devexit imx_sgtl5000_remove(struct platform_device *pdev)
+{
+	struct imx_sgtl5000_data *data = platform_get_drvdata(pdev);
+
+	snd_soc_unregister_card(&data->card);
+
+	return 0;
+}
+
+static const struct of_device_id imx_sgtl5000_dt_ids[] = {
+	{ .compatible = "fsl,imx-audio-sgtl5000", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_sgtl5000_dt_ids);
+
+static struct platform_driver imx_sgtl5000_driver = {
+	.driver = {
+		.name = "imx-sgtl5000",
+		.owner = THIS_MODULE,
+		.of_match_table = imx_sgtl5000_dt_ids,
+	},
+	.probe = imx_sgtl5000_probe,
+	.remove = __devexit_p(imx_sgtl5000_remove),
+};
+module_platform_driver(imx_sgtl5000_driver);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo at linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX SGTL5000 ASoC machine driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx-sgtl5000");
-- 
1.7.5.4



From javier.martin at vista-silicon.com  Mon Mar 12 07:18:52 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon, 12 Mar 2012 12:18:52 +0100
Subject: [PATCH] dmaengine: i.MX: Add support for interleaved transfers.
Message-ID: <1331551132-29383-1-git-send-email-javier.martin@vista-silicon.com>

i.MX2 and i.MX1 chips have the possibility to do
interleaved transfers with two constraints:
* Only one chunk can be used (i.e. only 2D transfers are allowed).
* Only 2 interleaved configurations can be applied at the same time
for all channels.

Since this patch adds a new resource 'slots_2d' which is shared
by all the DMA channels and to avoid disgustin locking BUGs, the
'lock' member has been moved to the global 'imxdma_engine' structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 NOTE: This patch must be applied on top of the following series:
 [PATCH v3 00/13] dmaengine: imx-dma: merge dma arch code into dmaengine.

---
 drivers/dma/imx-dma.c |  151 +++++++++++++++++++++++++++++++++++++++++++------
 1 files changed, 134 insertions(+), 17 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 4584012..5931e02 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -35,6 +35,10 @@
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
 #define IMX_DMA_CHANNELS  16
 
+#define IMX_DMA_2D_SLOTS	2
+#define IMX_DMA_2D_SLOT_A	0
+#define IMX_DMA_2D_SLOT_B	1
+
 #define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
 #define IMX_DMA_MEMSIZE_32	(0 << 4)
 #define IMX_DMA_MEMSIZE_8	(1 << 4)
@@ -110,6 +114,13 @@ enum  imxdma_prep_type {
 	IMXDMA_DESC_CYCLIC,
 };
 
+struct imx_dma_2d_config {
+	u16		xsr;
+	u16		ysr;
+	u16		wsr;
+	int		count;
+};
+
 struct imxdma_desc {
 	struct list_head		node;
 	struct dma_async_tx_descriptor	desc;
@@ -146,12 +157,13 @@ struct imxdma_channel {
 	dma_addr_t			per_address;
 	u32				watermark_level;
 	struct dma_chan			chan;
-	spinlock_t			lock;
 	dma_cookie_t			last_completed;
 	int				dma_request;
 	struct scatterlist		*sg_list;
 	u32				ccr_from_device;
 	u32				ccr_to_device;
+	bool				enabled_2d;
+	int				slot_2d;
 };
 
 struct imxdma_engine {
@@ -160,6 +172,8 @@ struct imxdma_engine {
 	struct dma_device		dma_device;
 	void __iomem			*base;
 	struct clk			*dma_clk;
+	spinlock_t			lock;
+	struct imx_dma_2d_config	slots_2d[IMX_DMA_2D_SLOTS];
 	struct imxdma_channel		channel[IMX_DMA_CHANNELS];
 };
 
@@ -359,16 +373,16 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
-	spin_lock(&imxdmac->lock);
+	spin_lock(&imxdma->lock);
 	if (list_empty(&imxdmac->ld_active)) {
-		spin_unlock(&imxdmac->lock);
+		spin_unlock(&imxdma->lock);
 		goto out;
 	}
 
 	desc = list_first_entry(&imxdmac->ld_active,
 				struct imxdma_desc,
 				node);
-	spin_unlock(&imxdmac->lock);
+	spin_unlock(&imxdma->lock);
 
 	if (desc->sg) {
 		u32 tmp;
@@ -440,9 +454,53 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
+	unsigned long flags;
+	int slot = -1;
+	int i;
 
 	/* Configure and enable */
 	switch (d->type) {
+	case IMXDMA_DESC_INTERLEAVED:
+		/* Try to get a free 2D slot */
+		spin_lock_irqsave(&imxdma->lock, flags);
+		for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
+			if ((imxdma->slots_2d[i].count > 0) &&
+			((imxdma->slots_2d[i].xsr != d->x) ||
+			(imxdma->slots_2d[i].ysr != d->y) ||
+			(imxdma->slots_2d[i].wsr != d->w)))
+				continue;
+			slot = i;
+			break;
+		}
+		if (slot < 0)
+			return -EBUSY;
+
+		imxdma->slots_2d[slot].xsr = d->x;
+		imxdma->slots_2d[slot].ysr = d->y;
+		imxdma->slots_2d[slot].wsr = d->w;
+		imxdma->slots_2d[slot].count++;
+
+		imxdmac->slot_2d = slot;
+		imxdmac->enabled_2d = true;
+		spin_unlock_irqrestore(&imxdma->lock, flags);
+
+		if (slot == IMX_DMA_2D_SLOT_A) {
+			d->config_mem &= ~CCR_MSEL_B;
+			d->config_port &= ~CCR_MSEL_B;
+			imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
+			imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
+			imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
+		} else {
+			d->config_mem |= CCR_MSEL_B;
+			d->config_port |= CCR_MSEL_B;
+			imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
+			imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
+			imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
+		}
+		/*
+		 * We fall-through here intentionally, since a 2D transfer is
+		 * similar to MEMCPY just adding the 2D slot configuration.
+		 */
 	case IMXDMA_DESC_MEMCPY:
 		imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
 		imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
@@ -501,7 +559,7 @@ static void imxdma_tasklet(unsigned long data)
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	struct imxdma_desc *desc;
 
-	spin_lock(&imxdmac->lock);
+	spin_lock(&imxdma->lock);
 
 	if (list_empty(&imxdmac->ld_active)) {
 		/* Someone might have called terminate all */
@@ -518,6 +576,12 @@ static void imxdma_tasklet(unsigned long data)
 	if (imxdma_chan_is_doing_cyclic(imxdmac))
 		goto out;
 
+	/* Free 2D slot if it was an interleaved transfer */
+	if (imxdmac->enabled_2d) {
+		imxdma->slots_2d[imxdmac->slot_2d].count--;
+		imxdmac->enabled_2d = false;
+	}
+
 	list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
 
 	if (!list_empty(&imxdmac->ld_queue)) {
@@ -529,7 +593,7 @@ static void imxdma_tasklet(unsigned long data)
 				 __func__, imxdmac->channel);
 	}
 out:
-	spin_unlock(&imxdmac->lock);
+	spin_unlock(&imxdma->lock);
 }
 
 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
@@ -545,10 +609,10 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 	case DMA_TERMINATE_ALL:
 		imxdma_disable_hw(imxdmac);
 
-		spin_lock_irqsave(&imxdmac->lock, flags);
+		spin_lock_irqsave(&imxdma->lock, flags);
 		list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 		list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
-		spin_unlock_irqrestore(&imxdmac->lock, flags);
+		spin_unlock_irqrestore(&imxdma->lock, flags);
 		return 0;
 	case DMA_SLAVE_CONFIG:
 		if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
@@ -603,16 +667,17 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 					    struct dma_tx_state *txstate)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	dma_cookie_t last_used;
 	enum dma_status ret;
 	unsigned long flags;
 
-	spin_lock_irqsave(&imxdmac->lock, flags);
+	spin_lock_irqsave(&imxdma->lock, flags);
 	last_used = chan->cookie;
 
 	ret = dma_async_is_complete(cookie, imxdmac->last_completed, last_used);
 	dma_set_tx_state(txstate, imxdmac->last_completed, last_used, 0);
-	spin_unlock_irqrestore(&imxdmac->lock, flags);
+	spin_unlock_irqrestore(&imxdma->lock, flags);
 
 	return ret;
 }
@@ -632,16 +697,17 @@ static dma_cookie_t imxdma_assign_cookie(struct imxdma_channel *imxdma)
 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	dma_cookie_t cookie;
 	unsigned long flags;
 
-	spin_lock_irqsave(&imxdmac->lock, flags);
+	spin_lock_irqsave(&imxdma->lock, flags);
 
 	list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
 	cookie = imxdma_assign_cookie(imxdmac);
 	tx->cookie = cookie;
 
-	spin_unlock_irqrestore(&imxdmac->lock, flags);
+	spin_unlock_irqrestore(&imxdma->lock, flags);
 
 	return cookie;
 }
@@ -680,16 +746,17 @@ static int imxdma_alloc_chan_resources(struct dma_chan *chan)
 static void imxdma_free_chan_resources(struct dma_chan *chan)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	struct imxdma_desc *desc, *_desc;
 	unsigned long flags;
 
-	spin_lock_irqsave(&imxdmac->lock, flags);
+	spin_lock_irqsave(&imxdma->lock, flags);
 
 	imxdma_disable_hw(imxdmac);
 	list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 	list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 
-	spin_unlock_irqrestore(&imxdmac->lock, flags);
+	spin_unlock_irqrestore(&imxdma->lock, flags);
 
 	list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
 		kfree(desc);
@@ -843,6 +910,49 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
 	return &desc->desc;
 }
 
+static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
+	struct dma_chan *chan, struct dma_interleaved_template *xt,
+	unsigned long flags)
+{
+	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
+	struct imxdma_desc *desc;
+
+	dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
+		"   src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
+		imxdmac->channel, xt->src_start, xt->dst_start,
+		xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
+		xt->numf, xt->frame_size);
+
+	if (list_empty(&imxdmac->ld_free) ||
+	    imxdma_chan_is_doing_cyclic(imxdmac))
+		return NULL;
+
+	if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
+		return NULL;
+
+	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
+
+	desc->type = IMXDMA_DESC_INTERLEAVED;
+	desc->src = xt->src_start;
+	desc->dest = xt->dst_start;
+	desc->x = xt->sgl[0].size;
+	desc->y = xt->numf;
+	desc->w = xt->sgl[0].icg + desc->x;
+	desc->len = desc->x * desc->y;
+	desc->direction = DMA_MEM_TO_MEM;
+	desc->config_port = IMX_DMA_MEMSIZE_32;
+	desc->config_mem = IMX_DMA_MEMSIZE_32;
+	if (xt->src_sgl)
+		desc->config_mem |= IMX_DMA_TYPE_2D;
+	if (xt->dst_sgl)
+		desc->config_port |= IMX_DMA_TYPE_2D;
+	desc->desc.callback = NULL;
+	desc->desc.callback_param = NULL;
+
+	return &desc->desc;
+}
+
 static void imxdma_issue_pending(struct dma_chan *chan)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
@@ -850,7 +960,7 @@ static void imxdma_issue_pending(struct dma_chan *chan)
 	struct imxdma_desc *desc;
 	unsigned long flags;
 
-	spin_lock_irqsave(&imxdmac->lock, flags);
+	spin_lock_irqsave(&imxdma->lock, flags);
 	if (list_empty(&imxdmac->ld_active) &&
 	    !list_empty(&imxdmac->ld_queue)) {
 		desc = list_first_entry(&imxdmac->ld_queue,
@@ -865,7 +975,7 @@ static void imxdma_issue_pending(struct dma_chan *chan)
 				       &imxdmac->ld_active);
 		}
 	}
-	spin_unlock_irqrestore(&imxdmac->lock, flags);
+	spin_unlock_irqrestore(&imxdma->lock, flags);
 }
 
 static int __init imxdma_probe(struct platform_device *pdev)
@@ -928,6 +1038,13 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
 	dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
 	dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
+	dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
+
+	/* Initialize 2D global parameters */
+	for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
+		imxdma->slots_2d[i].count = 0;
+
+	spin_lock_init(&imxdma->lock);
 
 	/* Initialize channel parameters */
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
@@ -948,7 +1065,6 @@ static int __init imxdma_probe(struct platform_device *pdev)
 		}
 
 		imxdmac->imxdma = imxdma;
-		spin_lock_init(&imxdmac->lock);
 
 		INIT_LIST_HEAD(&imxdmac->ld_queue);
 		INIT_LIST_HEAD(&imxdmac->ld_free);
@@ -973,6 +1089,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
 	imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
 	imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
+	imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
 	imxdma->dma_device.device_control = imxdma_control;
 	imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
 
-- 
1.7.0.4



From jm at lentin.co.uk  Sun Mar 11 10:33:25 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sun, 11 Mar 2012 14:33:25 +0000
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1331476406-9844-2-git-send-email-jm@lentin.co.uk>

Add support for the DNS-320 and DNS-325. Describe as much as currently possible
in the devicetree files, leave everything else in board-dt.c to be patched
later.

Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
 arch/arm/boot/dts/kirkwood-dns320.dts |   54 ++++++
 arch/arm/boot/dts/kirkwood-dns325.dts |   40 +++++
 arch/arm/mach-kirkwood/Kconfig        |   18 ++
 arch/arm/mach-kirkwood/Makefile.boot  |    2 +
 arch/arm/mach-kirkwood/board-dt.c     |  294 +++++++++++++++++++++++++++++++++
 5 files changed, 408 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-dns320.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-dns325.dts

diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
new file mode 100644
index 0000000..c039041
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -0,0 +1,54 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "D-Link DNS-320 NAS (Rev A1)";
+	compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	wdt at fed20300 {
+		compatible = "mrvl,orion-wdt";
+		reg = <0xfed20300 0x28>;
+		clock-frequency = <166666667>;
+	};
+
+	serial at f1012000 {
+		compatible = "ns16550a";
+		reg = <0xf1012000 0xff>;
+		reg-shift = <2>;
+		interrupts = <33>;
+		clock-frequency = <166666667>;
+	};
+
+	serial at f1012100 {
+		compatible = "ns16550a";
+		reg = <0xf1012100 0xff>;
+		reg-shift = <2>;
+		interrupts = <34>;
+		clock-frequency = <166666667>;
+	};
+
+	sata at f1080000 {
+		compatible = "mrvl,orion-sata";
+		reg = <0xf1080000 0x5000>;
+		interrupts = <21>;
+		nr-ports = <2>;
+	};
+
+	ehci at f1050000 {
+		compatible = "mrvl,orion-ehci";
+		reg = <0xf1050000 0x1000>;
+		interrupts = <19>;
+		dma-mask = <0xffffffff>;
+		phy-version = "";
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
new file mode 100644
index 0000000..a7c2c26
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -0,0 +1,40 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "D-Link DNS-325 NAS (Rev A1)";
+	compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	serial at f1012000 {
+		compatible = "ns16550a";
+		reg = <0xf1012000 0xff>;
+		reg-shift = <2>;
+		interrupts = <33>;
+		clock-frequency = <200000000>;
+	};
+
+	sata at f1080000 {
+		compatible = "mrvl,orion-sata";
+		reg = <0xf1080000 0x5000>;
+		interrupts = <21>;
+		nr-ports = <2>;
+	};
+
+	ehci at f1050000 {
+		compatible = "mrvl,orion-ehci";
+		reg = <0xf1050000 0x1000>;
+		interrupts = <19>;
+		dma-mask = <0xffffffff>;
+		phy-version = "";
+	};
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 90ceab7..6c76e18 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -58,6 +58,24 @@ config MACH_DREAMPLUG_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell DreamPlug (Flattened Device Tree).
 
+config MACH_DNS320_DT
+	bool "D-Link DNS-320 (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	select CONFIG_MTD_OF_PARTS
+	select CONFIG_SERIAL_OF_PLATFORM
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  D-Link DNS-320 (Flattened Device Tree).
+
+config MACH_DNS325_DT
+	bool "D-Link DNS-325 (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	select CONFIG_MTD_OF_PARTS
+	select CONFIG_SERIAL_OF_PLATFORM
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  D-Link DNS-325 (Flattened Device Tree).
+
 config MACH_TS219
 	bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
 	help
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 16f9385..9c5e45f 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -3,3 +3,5 @@ params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
 
 dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
+dtb-$(CONFIG_MACH_DNS320_DT) += kirkwood-dns320.dtb
+dtb-$(CONFIG_MACH_DNS325_DT) += kirkwood-dns325.dtb
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 12dec38..0885713 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/irqdomain.h>
 #include <linux/mtd/partitions.h>
+#include <linux/i2c.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/of.h>
@@ -23,6 +24,9 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio-fan.h>
 #include <linux/leds.h>
 #include <linux/mtd/physmap.h>
 #include <linux/spi/flash.h>
@@ -150,6 +154,291 @@ static void __init dreamplug_init(void)
 	platform_device_register(&dreamplug_leds);
 }
 
+/*****************************************************************************
+ * DNS-320 & DNS-325 specifics
+ ****************************************************************************/
+
+static struct mtd_partition dnskw_nand_parts[] = {
+	{
+		.name		= "u-boot",
+		.offset		= 0,
+		.size		= SZ_1M,
+		.mask_flags	= MTD_WRITEABLE
+	}, {
+		.name		= "uImage",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 5 * SZ_1M
+	}, {
+		.name		= "ramdisk",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 5 * SZ_1M
+	}, {
+		.name		= "image",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 102 * SZ_1M
+	}, {
+		.name		= "mini firmware",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 10 * SZ_1M
+	}, {
+		.name		= "config",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 5 * SZ_1M
+	},
+};
+
+static struct mv643xx_eth_platform_data dnskw_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
+};
+
+static unsigned int dnskw_mpp_config[] __initdata = {
+	MPP13_UART1_TXD,	/* Custom ... */
+	MPP14_UART1_RXD,	/* ... Controller (DNS-320 only) */
+	MPP20_SATA1_ACTn,	/* LED: White Right HDD */
+	MPP21_SATA0_ACTn,	/* LED: White Left HDD */
+	MPP24_GPIO,
+	MPP25_GPIO,
+	MPP26_GPIO,	/* LED: Power */
+	MPP27_GPIO,	/* LED: Red Right HDD */
+	MPP28_GPIO,	/* LED: Red Left HDD */
+	MPP29_GPIO,	/* LED: Red USB (DNS-325 only) */
+	MPP30_GPIO,
+	MPP31_GPIO,
+	MPP32_GPIO,
+	MPP33_GPO,
+	MPP34_GPIO,	/* Button: Front power */
+	MPP35_GPIO,	/* LED: Red USB (DNS-320 only) */
+	MPP36_GPIO,	/* Power: MV88F6281_DEV_ID Board */
+	MPP37_GPIO,	/* Power: Boot when power applied */
+	MPP38_GPIO,
+	MPP39_GPIO,	/* Power: SATA0 */
+	MPP40_GPIO,	/* Power: SATA1 */
+	MPP41_GPIO,
+	MPP42_GPIO,
+	MPP43_GPIO,	/* LED: White USB */
+	MPP44_GPIO,	/* Fan: Tachometer Pin */
+	MPP45_GPIO,	/* Fan: high speed */
+	MPP46_GPIO,	/* Fan: low speed */
+	MPP47_GPIO,	/* Button: Back unmount */
+	MPP48_GPIO,	/* Button: Back reset */
+	MPP49_GPIO,	/* Pin of unused U5 (DNS-320 only) */
+	0
+};
+
+static struct gpio_led dns325_led_pins[] = {
+	{
+		.name	= "dns325:white:power",
+		.gpio	= 26,
+		.active_low = 1,
+		.default_trigger = "default-on",
+	},
+	{
+		.name	= "dns325:white:usb",
+		.gpio	= 43,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns325:red:l_hdd",
+		.gpio	= 28,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns325:red:r_hdd",
+		.gpio	= 27,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns325:red:usb",
+		.gpio	= 29,
+		.active_low = 1,
+	},
+};
+
+static struct gpio_led_platform_data dns325_led_data = {
+	.num_leds	= ARRAY_SIZE(dns325_led_pins),
+	.leds		= dns325_led_pins,
+};
+
+static struct platform_device dns325_led_device = {
+	.name		= "leds-gpio",
+	.id		= -1,
+	.dev		= {
+		.platform_data	= &dns325_led_data,
+	},
+};
+
+static struct gpio_led dns320_led_pins[] = {
+	{
+		.name	= "dns320:blue:power",
+		.gpio	= 26,
+		.active_low = 1,
+		.default_trigger = "default-on",
+	},
+	{
+		.name	= "dns320:blue:usb",
+		.gpio	= 43,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns320:orange:l_hdd",
+		.gpio	= 28,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns320:orange:r_hdd",
+		.gpio	= 27,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns320:orange:usb",
+		.gpio	= 35,
+		.active_low = 1,
+	},
+};
+
+static struct gpio_led_platform_data dns320_led_data = {
+	.num_leds	= ARRAY_SIZE(dns320_led_pins),
+	.leds		= dns320_led_pins,
+};
+
+static struct platform_device dns320_led_device = {
+	.name		= "leds-gpio",
+	.id		= -1,
+	.dev		= {
+		.platform_data	= &dns320_led_data,
+	},
+};
+
+static struct i2c_board_info dns325_i2c_board_info[] __initdata = {
+	{
+		I2C_BOARD_INFO("lm75", 0x48),
+	},
+	/* Something at 0x0c also */
+};
+
+static struct gpio_keys_button dnskw_button_pins[] = {
+	{
+		.code		= KEY_POWER,
+		.gpio		= 34,
+		.desc		= "Power button",
+		.active_low	= 1,
+	},
+	{
+		.code		= KEY_EJECTCD,
+		.gpio		= 47,
+		.desc		= "USB unmount button",
+		.active_low	= 1,
+	},
+	{
+		.code		= KEY_RESTART,
+		.gpio		= 48,
+		.desc		= "Reset button",
+		.active_low	= 1,
+	},
+};
+
+static struct gpio_keys_platform_data dnskw_button_data = {
+	.buttons	= dnskw_button_pins,
+	.nbuttons	= ARRAY_SIZE(dnskw_button_pins),
+};
+
+static struct platform_device dnskw_button_device = {
+	.name		= "gpio-keys",
+	.id		= -1,
+	.num_resources	= 0,
+	.dev		= {
+		.platform_data	= &dnskw_button_data,
+	}
+};
+
+/* Fan: ADDA AD045HB-G73 40mm 6000rpm at 5v */
+static struct gpio_fan_speed dnskw_fan_speed[] = {
+	{    0,  0 },
+	{ 3000,	 1 },
+	{ 6000,	 2 },
+};
+static unsigned dnskw_fan_pins[] = {46, 45};
+
+static struct gpio_fan_platform_data dnskw_fan_data = {
+	.num_ctrl	= ARRAY_SIZE(dnskw_fan_pins),
+	.ctrl		= dnskw_fan_pins,
+	.num_speed	= ARRAY_SIZE(dnskw_fan_speed),
+	.speed		= dnskw_fan_speed,
+};
+
+static struct platform_device dnskw_fan_device = {
+	.name	= "gpio-fan",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &dnskw_fan_data,
+	},
+};
+
+static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
+{
+	if (gpio_request(gpio, name) == 0 &&
+	    gpio_direction_output(gpio, 0) == 0) {
+		gpio_set_value(gpio, def);
+		if (gpio_export(gpio, 0) != 0)
+			pr_err("dnskw: Failed to export GPIO %s\n", name);
+	} else
+		pr_err("dnskw: Failed to register %s\n", name);
+}
+
+static void dnskw_power_off(void)
+{
+	gpio_set_value(36, 1);
+}
+
+static void __init dnskw_init(void)
+{
+	u32 dev, rev;
+
+	kirkwood_mpp_conf(dnskw_mpp_config);
+	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
+
+	kirkwood_ge00_init(&dnskw_ge00_data);
+	kirkwood_i2c_init();
+
+	platform_device_register(&dnskw_button_device);
+	platform_device_register(&dnskw_fan_device);
+
+	if (of_machine_is_compatible("dlink,dns-325")) {
+		i2c_register_board_info(0, dns325_i2c_board_info,
+					ARRAY_SIZE(dns325_i2c_board_info));
+		platform_device_register(&dns325_led_device);
+
+	} else if (of_machine_is_compatible("dlink,dns-320")) {
+		platform_device_register(&dns320_led_device);
+	}
+
+	/* Register power off routine */
+	kirkwood_pcie_id(&dev, &rev);
+	if (dev == MV88F6281_DEV_ID) {
+		pr_info("PCI-E Device ID: MV88F6281, configuring power-off");
+		if (gpio_request(36, "dnskw:power:off") == 0 &&
+		    gpio_direction_output(36, 0) == 0)
+			pm_power_off = dnskw_power_off;
+		else
+			pr_err("dnskw: failed to configure power-off GPIO\n");
+	} else {
+		/*
+		 * Dlink code also defines 0x6192, and sets LOW_BASE +
+		 * 0x01000000 high. Either cargo-culted code or another model.
+		 */
+		pr_err("Unknown PCI-E Device ID %x, no power-off", dev);
+	}
+
+	/*
+	 * Supply power to HDDs. Bootloader should have turned on sata0 already
+	 */
+	dnskw_gpio_register(39, "dnskw:power:sata0", 1);
+	dnskw_gpio_register(40, "dnskw:power:sata1", 1);
+
+	/* Set NAS to turn back on after a power failure */
+	dnskw_gpio_register(37, "dnskw:power:recover", 1);
+}
+
 static void __init kirkwood_dt_init(void)
 {
 	struct device_node *node;
@@ -186,11 +475,16 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("globalscale,dreamplug"))
 		dreamplug_init();
 
+	if (of_machine_is_compatible("dlink,dns-kirkwood"))
+		dnskw_init();
+
 	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
 }
 
 static const char *kirkwood_dt_board_compat[] = {
 	"globalscale,dreamplug",
+	"dlink,dns-320",
+	"dlink,dns-325",
 	NULL
 };
 
-- 
1.7.9.1



From jkrzyszt at tis.icnet.pl  Sat Mar 10 04:55:04 2012
From: jkrzyszt at tis.icnet.pl (Janusz Krzysztofik)
Date: Sat, 10 Mar 2012 10:55:04 +0100
Subject: linux-next: manual merge of the arm-soc tree with the omap_dss2
 tree
In-Reply-To: <20120308165116.d400947f35e40a923e9c6ad0@canb.auug.org.au>
References: <20120308165116.d400947f35e40a923e9c6ad0@canb.auug.org.au>
Message-ID: <1678557.FviZqEVemH@vclass>

On Thursday 08 of March 2012 16:51:16 Stephen Rothwell wrote:
> Hi all,
> 
> Today's linux-next merge of the arm-soc tree got a conflict in
> arch/arm/mach-omap1/board-ams-delta.c between commit ddba6c7f7ec6
> ("OMAP1: pass LCD config with omapfb_set_lcd_config()") from the
> omap_dss2 tree and commits 5ca6180fa6d7 ("ARM: OMAP1: ams-delta:
> supersede custom led device by leds-gpio") and 2e3ee9f45b3c ("ARM: OMAP1:
> Move most of plat/io.h into local iomap.h") from the arm-soc tree.
> 
> I fixed it up (see below) and can carry the fix as necessary.

Hi,
Your resolution looks good to me, thanks!
Janusz


From arnd at arndb.de  Mon Mar 12 04:46:28 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 12 Mar 2012 08:46:28 +0000
Subject: [PATCH v7 1/4] USB: OHCI-HCD: Rename ohci-pnx4008 to ohci-nxp
In-Reply-To: <1331463219-23293-2-git-send-email-stigge@antcom.de>
References: <1331463219-23293-1-git-send-email-stigge@antcom.de>
 <1331463219-23293-2-git-send-email-stigge@antcom.de>
Message-ID: <201203120846.29070.arnd@arndb.de>

On Sunday 11 March 2012, Roland Stigge wrote:
> Since this driver is compatible with several NXP devices, the driver is renamed
> accordingly. Please combine with the following patch which also changes the
> respective symbol names.
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>
> 

Hi Roland,

As a general comment, it's helpful to use the "-M" flag to git-format-patch
whenever you rename files, because that makes it obvious whether you have
changed anything in the file or not.

> --- /dev/null
> +++ linux-2.6/drivers/usb/host/ohci-nxp.c
> @@ -0,0 +1,453 @@
> +/*
> + * drivers/usb/host/ohci-pnx4008.c
> + *
> + * driver for Philips PNX4008 USB Host
> + *

I think your second patch does not change this comment and probably should.

Just remove the file name from the comment because that one is generally
not helpful.

	Arnd



From s.hauer at pengutronix.de  Mon Mar 12 07:51:17 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 12 Mar 2012 12:51:17 +0100
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zMdkLB-DCPOk=kz5mn6BK6A_swocyCHJHeGE6H7FxBbmQ@mail.gmail.com>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
 <20120311113414.GM3852@pengutronix.de>
 <CAJOA=zMdkLB-DCPOk=kz5mn6BK6A_swocyCHJHeGE6H7FxBbmQ@mail.gmail.com>
Message-ID: <20120312115117.GN3852@pengutronix.de>

On Sun, Mar 11, 2012 at 02:24:46PM -0700, Turquette, Mike wrote:
> On Sun, Mar 11, 2012 at 4:34 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > Hi Mike,
> >
> > I was about to give my tested-by when I decided to test the set_rate
> > function. Unfortunately this is broken for several reasons. I'll try
> > to come up with a fixup series later the day.
> 
> I haven't tested clk_set_rate since V4, but I also haven't changed the
> code appreciably.  I'll retest on my end also.
> 
> > On Fri, Mar 09, 2012 at 11:54:23PM -0800, Mike Turquette wrote:
> >> + ? ? /* find the new rate and see if parent rate should change too */
> >> + ? ? WARN_ON(!clk->ops->round_rate);
> >> +
> >> + ? ? new_rate = clk->ops->round_rate(clk->hw, rate, &parent_new_rate);
> >
> > You don't need a WARN_ON when you derefence clk->ops->round_rate anyway.
> 
> Agreed that the WARN_ON should not be there.
> 
> The v6 Documentation/clk.txt states that .round_rate is mandatory for
> clocks that can adjust their rate, but I need to clarify this a bit
> more.  Ideally we want to be able to call clk_set_rate on any clock
> and get a changed rate (if possible) by either adjusting that clocks
> rate direction (e.g. a PLL or an adjustable divider) or by propagating
> __clk_set_rate up the parents (assuming of course that
> CLK_SET_RATE_PARENT flag is set appropriately).
> 
> > Also, even when the current clock does not have a set_rate function it
> > can still change its rate when the CLK_SET_RATE_PARENT is set.
> 
> Correct.  I'll clean this up and make the documentation a bit more
> verbose on when .set_rate/.round_rate/.recalc_rate are mandatory.
> 
> >
> >> +
> >> + ? ? /* NOTE: pre-rate change notifications will stack */
> >> + ? ? if (clk->notifier_count)
> >> + ? ? ? ? ? ? ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
> >> +
> >> + ? ? if (ret == NOTIFY_BAD)
> >> + ? ? ? ? ? ? return clk;
> >> +
> >> + ? ? /* speculate rate changes down the tree */
> >> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node) {
> >> + ? ? ? ? ? ? ret = __clk_speculate_rates(child, new_rate);
> >> + ? ? ? ? ? ? if (ret == NOTIFY_BAD)
> >> + ? ? ? ? ? ? ? ? ? ? return clk;
> >> + ? ? }
> >> +
> >> + ? ? /* change the rate of this clk */
> >> + ? ? if (clk->ops->set_rate)
> >> + ? ? ? ? ? ? ret = clk->ops->set_rate(clk->hw, new_rate);
> >
> > I don't know the reason why you change the child clock before the parent
> > clock, but it cannot work since this clock will change its rate based on
> > the old parent rate and not the new one.
> 
> This depends on the .round_rate implementation, which I admit to
> having lost some sleep over.  A clever .round_rate will request the
> "intermediate" rate for a clock when propagating a request to change
> the parent rate later on.  Take for instance the following:
> 
> pll @ 200MHz (locked)
>     |
> parent @ 100MHz (can divide by 1 or 2; currently divider is 2)
>     |
> child @ 25MHz (can divide by 2 or 4; currently divider is 4)
> 
> If we want child to run at 100MHz then the desirable configuration
> would be to have parent divide-by-1 and child divide-by-2.  When we
> call,
> 
> clk_set_rate(child, 100MHz);
> 
> Its .round_rate should return 50MHz, and &parent_new_rate should be
> 200MHz.  So 50MHz is an "intermediate" rate, but it gets us the
> divider we want.  And in fact 50MHz reflects reality because that will
> be the rate of child until the parent propagation completes and we can
> adjust parent's dividers.  (this is one reason why I prefer for
> pre-rate change notifiers to stack on top of each other).
> 
> So now that &parent_new_rate is > 0, __clk_set_rate will propagate the
> request up and parent's .round_rate will simply return 200MHz and
> leave it's own &parent_new_rate at 0.  This will change from
> divide-by-2 to divide-by-1 and from this highest point in the tree we
> will propagate post-rate change notifiers downstream, as part of the
> recalc_rate tree walk.
> 
> I have tested this with OMAP4's CPUfreq driver and I think, while
> complicated, it is a sound way to approach the problem.  Maybe the API
> can be cleaned up, if you have any suggestions.

I cannot see all implications this way will have. All this rate
propagation is more complex than I thought it would be. I tried another
approach on the weekend which basically does not try to do all in a
single recursion but instead sets the rate in multiple steps:

1) call a function which calculates all new rates of affected clocks
   in a rate change and safes the value in a clk->new_rate field. This
   function returns the topmost clock which has to be changed.
2) starting from the topmost clock notify all clients. This walks the
   whole subtree even if a notfifier refuses the change. If necessary
   we can walk the whole subtree again to abort the change.
3) actually change rates starting from the topmost clocks and notify
   all clients on the way. I changed the set_rate callback to void.
   Instead of failing (what is failing in case of set_rate? The clock
   will still have some rate) I check for the result with
   clk_ops->recalc_rate.

In the end what's more important than the implementation details is that
it actually works. I created a little test module which sets up two
cascaded dividers, tries to change the rate at the output and checks the
result.  We might want to add something like this (and maybe similar
tests for reparenting and other stuff) to the generic clock framework
later.  It's good to have something generic to test the framework with
without depending on some particular SoC.

Sascha

8<----------------------------------------------------

clk: Add clock test module

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/clk-test.c |  169 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 169 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-test.c

diff --git a/drivers/clk/clk-test.c b/drivers/clk/clk-test.c
new file mode 100644
index 0000000..6f901fd
--- /dev/null
+++ b/drivers/clk/clk-test.c
@@ -0,0 +1,169 @@
+#include <linux/spinlock.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+
+/*
+ * We build a fixed rate source clock with two cascaded 2bit dividers:
+ *
+ * f1 -> div1 -> div2
+ *
+ * and try set the rate of div2 from 0Hz to f1 + 1 Hz.
+ *
+ * This makes the following resulting dividers possible:
+ *
+ * 1, 2, 4, 6, 8, 9, 12, 16
+ *
+ * Sometimes there are different results possible due to integer maths.
+ * For example if we have an input frequency of 100Hz and request an
+ * output of 16Hz the best divider values would be 2 and 4 resulting
+ * in a real frequency of 12.5Hz. We also accept 2 and 3 as result
+ * because 100 / (3 * 2) = 16.6667 which is too high, but multiplying
+ * 16 * 3 * 2 results in 96Hz which is lower than 100Hz.
+ *
+ */
+
+static unsigned long div1_reg, div2_reg;
+
+static struct clk *f1, *div1, *div2;
+
+static DEFINE_SPINLOCK(imx_ccm_lock);
+
+//#define FIXED_RATE 144
+#define FIXED_RATE 100
+
+static inline struct clk *register_divider(const char *name, const char *parent,
+		void __iomem *reg, u8 shift, u8 width)
+{
+	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+			reg, shift, width, 0, &imx_ccm_lock);
+}
+
+static unsigned long divs[] = {
+	1, 2, 3, 4, 6, 8, 9, 12, 16,
+};
+
+static int check_rounded_rate(unsigned long want, unsigned long rounded)
+{
+	int i, j;
+	unsigned long best1 = 0, best2 = 0, now;
+
+	if (want > FIXED_RATE) {
+		best1 = best2 = FIXED_RATE;
+		goto found2;
+	}
+
+	for (i = 1; i <= 4; i++) {
+		for (j = 1; j <= 4; j++) {
+			now = FIXED_RATE / i / j;
+			if (now <= want && now > best1)
+				best1 = now;
+		}
+	}
+
+	if (!best1)
+		best1 = (FIXED_RATE / 4) / 4;
+
+	for (i = 0; i < ARRAY_SIZE(divs); i++) {
+		if (FIXED_RATE <= want * divs[i]) {
+			best2 = FIXED_RATE / divs[i];
+			goto found2;
+		}
+	}
+
+	if (!best2)
+		best2 = FIXED_RATE / 16;
+found2:
+	if (rounded != best1 && rounded != best2) {
+		if (best1 == best2)
+			printk("clk-test: wanted rate %ld, best result would be %ld,"
+					" but we have %ld\n",
+					want, best1, rounded);
+		else
+			printk("clk-test: wanted rate %ld, best result would be %ld or %ld,"
+					" but we have %ld\n",
+					want, best1, best2, rounded);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int check_real_rate(unsigned long rate)
+{
+	unsigned long realrate1, realrate2;
+
+	realrate1 = FIXED_RATE / (div1_reg + 1) / (div2_reg + 1);
+	realrate2 = FIXED_RATE / ((div1_reg + 1) * (div2_reg + 1));
+
+	if (rate != realrate1 && rate != realrate2) {
+		if (realrate1 == realrate2)
+			printk("clk-test: divider returns rate %ld, but instead has %ld\n",
+					rate, realrate1);
+		else
+			printk("clk-test: divider returns rate %ld, but instead has %ld or %ld\n",
+					rate, realrate1, realrate2);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int set_rate_test(void)
+{
+	unsigned long i, rate, rounded;
+	int ret, errors = 0;
+
+	for (i = 0; i < FIXED_RATE + 1; i++) {
+		rounded = clk_round_rate(div2, i);
+		ret = check_rounded_rate(i, rounded);
+		if (ret)
+			errors++;
+		ret = clk_set_rate(div2, i);
+		if (ret) {
+			printk("%s: setting rate of div2 to %ld failed with %d\n",
+					__func__, i, ret);
+			errors++;
+		}
+
+		rate = clk_get_rate(div2);
+
+		if (rounded != rate) {
+			printk("clk_test: wanted %ld, core rounded to %ld, have now: %ld\n",
+					i, rounded, rate);
+			errors++;
+		}
+
+		ret = check_real_rate(rate);
+		if (ret)
+			errors++;
+	}
+
+	return errors;
+}
+
+static int clk_test_init(void)
+{
+	int errors;
+
+	f1 = clk_register_fixed_rate(NULL, "f1", NULL, CLK_IS_ROOT, FIXED_RATE);
+	div1 = register_divider("div1", "f1", &div1_reg, 0, 2);
+	div2 = register_divider("div2", "div1", &div2_reg, 0, 2);
+
+	if (!f1 || !div1 || !div2) {
+		printk("clk-test: failed to register clocks\n");
+		return -EINVAL;
+	}
+
+	errors = set_rate_test();
+
+	printk("clk-test: finished with %d errors\n", errors);
+#if 0
+	/* Oh, oh */
+	clk_unregister(f1);
+	clk_unregister(div1);
+	clk_unregister(div2);
+#endif
+	return -EINVAL;
+}
+subsys_initcall(clk_test_init);
-- 
1.7.9.1



-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From jason at lakedaemon.net  Mon Mar 12 14:56:06 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 12 Mar 2012 14:56:06 -0400
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <op.wa2j90zu4cuzmg@gonzo.lentin.co.uk>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <1331476406-9844-2-git-send-email-jm@lentin.co.uk>
 <20120312030232.GX5050@titan.lakedaemon.net>
 <op.wa2j90zu4cuzmg@gonzo.lentin.co.uk>
Message-ID: <20120312185606.GC5050@titan.lakedaemon.net>

On Mon, Mar 12, 2012 at 05:59:50PM -0000, Jamie Lentin wrote:
> On Mon, 12 Mar 2012 03:02:32 -0000, Jason Cooper
> <jason at lakedaemon.net> wrote:
> 
> >On Sun, Mar 11, 2012 at 02:33:25PM +0000, Jamie Lentin wrote:
> >>Add support for the DNS-320 and DNS-325. Describe as much as
> >>currently possible
> >>in the devicetree files, leave everything else in board-dt.c to
> >>be patched
> >>later.
> >>
> >>Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> >
> >Great work!  comments, below.
> >>---
> >> arch/arm/boot/dts/kirkwood-dns320.dts |   54 ++++++
> >> arch/arm/boot/dts/kirkwood-dns325.dts |   40 +++++
> >> arch/arm/mach-kirkwood/Kconfig        |   18 ++
> >> arch/arm/mach-kirkwood/Makefile.boot  |    2 +
> >> arch/arm/mach-kirkwood/board-dt.c     |  294
> >>+++++++++++++++++++++++++++++++++
> >> 5 files changed, 408 insertions(+), 0 deletions(-)
> >> create mode 100644 arch/arm/boot/dts/kirkwood-dns320.dts
> >> create mode 100644 arch/arm/boot/dts/kirkwood-dns325.dts
> >>
> >>diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts
> >>b/arch/arm/boot/dts/kirkwood-dns320.dts
> >>new file mode 100644
> >>index 0000000..c039041
> >>--- /dev/null
> >>+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
> >>@@ -0,0 +1,54 @@
> >>+/dts-v1/;
> >>+
> >>+/include/ "kirkwood.dtsi"
> >>+
> >>+/ {
> >>+	model = "D-Link DNS-320 NAS (Rev A1)";
> >>+	compatible = "dlink,dns-320-a1", "dlink,dns-320",
> >>"dlink,dns-kirkwood", "marvell,kirkwood-88f6281",
> >>"marvell,kirkwood";
> >
> >s/marvell/mrvl/g for compatible properties.
> >
> 
> Okay.
> 
> >>+	memory {
> >>+		device_type = "memory";
> >>+		reg = <0x00000000 0x8000000>;
> >>+	};
> >>+
> >>+	chosen {
> >>+		bootargs = "console=ttyS0,115200n8 earlyprintk";
> >>+	};
> >>+
> >>+	wdt at fed20300 {
> >>+		compatible = "mrvl,orion-wdt";
> >>+		reg = <0xfed20300 0x28>;
> >>+		clock-frequency = <166666667>;
> >>+	};
> >
> >This hasn't made it into my stable branch yet, waiting on common clock
> >to land (may be 3.5).  Please use kirkwood_wdt_init() in the mean time.
> >
> 
> So just to be clear kirkwood_dt_stable on git.infradead.org, as
> opposed to any branches on arm-soc?

For now.  I'm still learning the git integration/upstream piece.  Give
me a few more hours and I should have a new version up for review.  It's
a reshuffle and edit of the whole series.

It also redoes serial@ based on Arnd's comments to your patches.

> >>+	serial at f1012000 {
> >>+		compatible = "ns16550a";
> >>+		reg = <0xf1012000 0xff>;
> >>+		reg-shift = <2>;
> >>+		interrupts = <33>;
> >>+		clock-frequency = <166666667>;
> >>+	};
> >>+
> >>+	serial at f1012100 {
> >>+		compatible = "ns16550a";
> >>+		reg = <0xf1012100 0xff>;
> >>+		reg-shift = <2>;
> >>+		interrupts = <34>;
> >>+		clock-frequency = <166666667>;
> >>+	};
> >>+
> >>+	sata at f1080000 {
> >>+		compatible = "mrvl,orion-sata";
> >>+		reg = <0xf1080000 0x5000>;
> >>+		interrupts = <21>;
> >>+		nr-ports = <2>;
> >>+	};
> >>+
> >>+	ehci at f1050000 {
> >>+		compatible = "mrvl,orion-ehci";
> >>+		reg = <0xf1050000 0x1000>;
> >>+		interrupts = <19>;
> >>+		dma-mask = <0xffffffff>;
> >>+		phy-version = "";
> >>+	};
> >
> >sata and ehci both require working dma and interrupt controller.  I
> >should have the interrupt controller done soon.  mv_cesa will then work.
> >dma will be after that.
> 
> I found this out the hard way, but saw that dma-mask was supported
> in staging/kirkwood/dt on arm-soc and managed to get working USB
> using it. I'll switch back for now.

Yes, that "support" was a mistake on my part.  It does not appear to be
the correct answer.

> >Basically, anything in mach-kirkwood/common.c that passes kirkwood_tclk
> >is on hold for devicetree.
> 
> Including serial ports?

serial is different because it's not a kirkwood/orion-specific driver.
It's clock-frequency is not (as my understanding goes) tied to the
system clock, it just happens to be so in this case.

The other drivers want tclk because they want to know the system clock.

...
> >>diff --git a/arch/arm/mach-kirkwood/board-dt.c
> >>b/arch/arm/mach-kirkwood/board-dt.c
> >>index 12dec38..0885713 100644
> >>--- a/arch/arm/mach-kirkwood/board-dt.c
> >>+++ b/arch/arm/mach-kirkwood/board-dt.c
> >>@@ -15,6 +15,7 @@
> >> #include <linux/platform_device.h>
> >> #include <linux/irqdomain.h>
> >> #include <linux/mtd/partitions.h>
> >>+#include <linux/i2c.h>
> >> #include <linux/ata_platform.h>
> >> #include <linux/mv643xx_eth.h>
> >> #include <linux/of.h>
> >>@@ -23,6 +24,9 @@
> >> #include <linux/of_irq.h>
> >> #include <linux/of_platform.h>
> >> #include <linux/gpio.h>
> >>+#include <linux/input.h>
> >>+#include <linux/gpio_keys.h>
> >>+#include <linux/gpio-fan.h>
> >> #include <linux/leds.h>
> >> #include <linux/mtd/physmap.h>
> >> #include <linux/spi/flash.h>
> >>@@ -150,6 +154,291 @@ static void __init dreamplug_init(void)
> >> 	platform_device_register(&dreamplug_leds);
> >> }
> >>
> >>+/*****************************************************************************
> >>+ * DNS-320 & DNS-325 specifics
> >>+ ****************************************************************************/
> >>+
> >>+static struct mtd_partition dnskw_nand_parts[] = {
> >>+	{
> >>+		.name		= "u-boot",
> >>+		.offset		= 0,
> >>+		.size		= SZ_1M,
> >>+		.mask_flags	= MTD_WRITEABLE
> >>+	}, {
> >>+		.name		= "uImage",
> >>+		.offset		= MTDPART_OFS_NXTBLK,
> >>+		.size		= 5 * SZ_1M
> >>+	}, {
> >>+		.name		= "ramdisk",
> >>+		.offset		= MTDPART_OFS_NXTBLK,
> >>+		.size		= 5 * SZ_1M
> >>+	}, {
> >>+		.name		= "image",
> >>+		.offset		= MTDPART_OFS_NXTBLK,
> >>+		.size		= 102 * SZ_1M
> >>+	}, {
> >>+		.name		= "mini firmware",
> >>+		.offset		= MTDPART_OFS_NXTBLK,
> >>+		.size		= 10 * SZ_1M
> >>+	}, {
> >>+		.name		= "config",
> >>+		.offset		= MTDPART_OFS_NXTBLK,
> >>+		.size		= 5 * SZ_1M
> >>+	},
> >>+};
> >
> >You should probably squeeze in a partition for the dtb.  ;-)
> >
> >Is the config partition the u-boot environment?  That usually is much
> >smaller than what you have alotted.  So, you might be able to split that
> >to make room for the dtb.
> >
> 
> The partition scheme is the same as D-Link's kernel. The config area
> is a jffs2 filesystem that contains their config files. It seemed to
> me that copying the partition table was the right thing to do to
> allow the NAND to be read, even though in practice it's not that
> useful---I'm not sure even D-Link pay much attention to it, there's
> all sorts of odd offsets in their code.
> 
> The other option would be to ignore the nonsense and replace it with
> something useful. This would be more convenient for me because it'd
> mean I don't have to replace it with my partition scheme :). Any
> opinions?

No, reverse-compatible is a good thing if we can swing it.  How about
giving uImage 4MB and then 1MB for the dtb?  Most of my dtbs haven't
even reached 2k...

Although, that'll change device numbering, eg ramdisk = /dev/mtdblock3
where it was /dev/mtdblock2 before.

Is there any unallocated space at the end of the flash?

...
> >>+
> >>+	/* Register power off routine */
> >>+	kirkwood_pcie_id(&dev, &rev);
> >>+	if (dev == MV88F6281_DEV_ID) {
> >>+		pr_info("PCI-E Device ID: MV88F6281, configuring power-off");
> >>+		if (gpio_request(36, "dnskw:power:off") == 0 &&
> >>+		    gpio_direction_output(36, 0) == 0)
> >>+			pm_power_off = dnskw_power_off;
> >>+		else
> >>+			pr_err("dnskw: failed to configure power-off GPIO\n");
> >>+	} else {
> >>+		/*
> >>+		 * Dlink code also defines 0x6192, and sets LOW_BASE +
> >>+		 * 0x01000000 high. Either cargo-culted code or another model.
> >>+		 */
> >
> >I'm just curious, what is cargo-culted?
> >
> 
> http://en.wikipedia.org/wiki/Cargo_cult_programming

It's okay, feel free to link me to lmgtfy.  ;-)

> In this case, I originally thought that the line was relevant to
> supporting the DNS-320 (I assumed it had a MV88F6192 based on it's
> lower TCLK), but it seems it uses the MV88F6281 too. So either
> D-link have been blindly including this logic or there is a model
> somewhere that uses the different SoC.
> 
> On reflection, it's probably best to remove this entirely. Testing
> the pcie_id isn't achieving anything and is likely to confuse when
> it comes to porting the power-off to devicetree.
> 
> >>+		pr_err("Unknown PCI-E Device ID %x, no power-off", dev);
> >>+	}
> >>+
> >>+	/*
> >>+	 * Supply power to HDDs. Bootloader should have turned on
> >>sata0 already
> >>+	 */
> >
> >Don't assume the bootloader does or doesn't do anything.  Put the
> >peripheral into a known state and work from there.
> >
> 
> It doesn't, it turns both HDDs on. I'll clarify the comment though.
              ^^ bootloader or kernel?

Users (especially me) may roll their own u-boot, or swapout for redboot,
whatever.

> >>+	dnskw_gpio_register(39, "dnskw:power:sata0", 1);
> >>+	dnskw_gpio_register(40, "dnskw:power:sata1", 1);
> >>+
> >>+	/* Set NAS to turn back on after a power failure */
> >>+	dnskw_gpio_register(37, "dnskw:power:recover", 1);
> >>+}
> >>+
> >
> >I doubt this board is the only one that wants to be added while the
> >conversion to devicetree is progressing.  It makes more sense to me to
> >break the above out to a separate file, eg board-dnskw.c.  I'll follow
> >and break out the dreamplug code to board-dreamplug.c.  Otherwise, I see
> >board-dt.c becoming a long mess.
> >
> >Arnd, sound okay to you?
> >
> >> static void __init kirkwood_dt_init(void)
> >> {
> >> 	struct device_node *node;
> >>@@ -186,11 +475,16 @@ static void __init kirkwood_dt_init(void)
> >> 	if (of_machine_is_compatible("globalscale,dreamplug"))
> >> 		dreamplug_init();
> >>
> >>+	if (of_machine_is_compatible("dlink,dns-kirkwood"))
> >>+		dnskw_init();
> >>+
> >> 	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
> >> }
> >>
> >> static const char *kirkwood_dt_board_compat[] = {
> >> 	"globalscale,dreamplug",
> >>+	"dlink,dns-320",
> >>+	"dlink,dns-325",
> >> 	NULL
> >> };
> >>
> >>--
> >>1.7.9.1
> >>
> 
> 
> -- 
> Jamie Lentin


From paul at pwsan.com  Mon Mar 12 07:01:48 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 05:01:48 -0600 (MDT)
Subject: [GIT PULL] ARM: OMAP2+: hwmod/PRM: miscellaneous patches for 3.4
Message-ID: <alpine.DEB.2.00.1203120500260.11332@utopia.booyaka.com>

Hi Tony

The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:

  Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)

are available in the git repository at:

  git://git.pwsan.com/linux-2.6 misc_devel_3.4

for you to fetch changes up to 553e322282655f213d131903ce7019aa25880273:

  ARM: OMAP4: prm: fix interrupt register offsets (2012-03-12 04:30:02 -0600)


- Paul
----------------------------------------------------------------
Rajendra Nayak (1):
      ARM: OMAP: hwmod: Use sysc_fields->srst_shift and get rid of hardcoded SYSC_TYPE2_SOFTRESET_MASK

Tero Kristo (1):
      ARM: OMAP4: prm: fix interrupt register offsets

 arch/arm/mach-omap2/omap_hwmod.c |    8 +++++---
 arch/arm/mach-omap2/prm44xx.c    |   21 +++++++++++----------
 2 files changed, 16 insertions(+), 13 deletions(-)


From jason at lakedaemon.net  Mon Mar 12 12:10:04 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 12 Mar 2012 12:10:04 -0400
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <201203120811.23137.arnd@arndb.de>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <201203111746.09757.arnd@arndb.de>
 <20120312031751.GY5050@titan.lakedaemon.net>
 <201203120811.23137.arnd@arndb.de>
Message-ID: <20120312161004.GB5050@titan.lakedaemon.net>

On Mon, Mar 12, 2012 at 08:11:22AM +0000, Arnd Bergmann wrote:
> On Monday 12 March 2012, Jason Cooper wrote:
> > > Or even use the ranges property to remap everything into
> > > a simpler address range:
> > > 
> > >       ocp at f1000000 {
> > >               compatible = "simple-bus";
> > >               ranges = <0 0xf1000000 0x1000000>;
> > >               #address-cells = 1;
> > >               #size-cells = 1;
> > > 
> > >               serial at 12000 {
> > >                       reg = <0x12000 0x100>;
> > >                       ...
> > >               };
> > > 
> > >               ...
> > >       };
> > 
> > Okay, that's pretty slick.  The wdt and intc are at 0xfed00000, is that
> > another ocp bus?  Or, am I missing something?
> 
> If they are on those addresses, yes. If you have a data sheet, you should
> look at what the buses are named there, "ocp" was just an example and I
> took that name from the <mach/kirkwood.h> file.
> 
> It does seem though that the 0xfed00000 address is where Linux maps
> the same 0xf1000000 range in its own virtual address space, so it's
> not something that should appear in the device tree.

Okay, that's what smelled funny.  wdt and intc both only have registers
in virtual address space defined.  Can I assume they map like everything
else to corresponding physical addresses?

eg wdt at fed20300 -> wdt at f1020300 ?

thx,

Jason.


From shawn.guo at linaro.org  Mon Mar 12 07:58:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 12 Mar 2012 19:58:49 +0800
Subject: [PATCH v4 02/10] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331553537-19789-3-git-send-email-shawn.guo@linaro.org>

Freescale PowerPC and ARM/IMX families share the same SSI IP block.
The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
code sharing and consolidation can happen.

This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
IMX platform.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig |    1 +
 arch/powerpc/configs/mpc85xx_defconfig           |    1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig       |    1 +
 sound/soc/Kconfig                                |    1 -
 sound/soc/Makefile                               |    1 -
 sound/soc/fsl/Kconfig                            |   92 ++++++++++++++++++++++
 sound/soc/fsl/Makefile                           |   22 +++++
 sound/soc/{imx => fsl}/eukrea-tlv320.c           |    2 +-
 sound/soc/{imx => fsl}/imx-audmux.c              |    0
 sound/soc/{imx => fsl}/imx-audmux.h              |    0
 sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c         |    0
 sound/soc/{imx => fsl}/imx-pcm-fiq.c             |    0
 sound/soc/{imx => fsl}/imx-pcm.c                 |    0
 sound/soc/{imx => fsl}/imx-pcm.h                 |    0
 sound/soc/{imx => fsl}/imx-ssi.c                 |    2 +-
 sound/soc/{imx => fsl}/imx-ssi.h                 |    0
 sound/soc/{imx => fsl}/mx27vis-aic32x4.c         |    0
 sound/soc/{imx => fsl}/phycore-ac97.c            |    0
 sound/soc/{imx => fsl}/wm1133-ev1.c              |    0
 sound/soc/imx/Kconfig                            |   79 -------------------
 sound/soc/imx/Makefile                           |   22 -----
 21 files changed, 119 insertions(+), 105 deletions(-)
 rename sound/soc/{imx => fsl}/eukrea-tlv320.c (99%)
 rename sound/soc/{imx => fsl}/imx-audmux.c (100%)
 rename sound/soc/{imx => fsl}/imx-audmux.h (100%)
 rename sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm-fiq.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm.h (100%)
 rename sound/soc/{imx => fsl}/imx-ssi.c (99%)
 rename sound/soc/{imx => fsl}/imx-ssi.h (100%)
 rename sound/soc/{imx => fsl}/mx27vis-aic32x4.c (100%)
 rename sound/soc/{imx => fsl}/phycore-ac97.c (100%)
 rename sound/soc/{imx => fsl}/wm1133-ev1.c (100%)
 delete mode 100644 sound/soc/imx/Kconfig
 delete mode 100644 sound/soc/imx/Makefile

diff --git a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
index 0db9ba0..c09598b 100644
--- a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
+++ b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
@@ -100,6 +100,7 @@ CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
 CONFIG_SND_SOC=y
+CONFIG_SND_POWERPC_SOC=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_EXT2_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index f37a2ab..44605f8 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -139,6 +139,7 @@ CONFIG_SND_INTEL8X0=y
 # CONFIG_SND_PPC is not set
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=y
+CONFIG_SND_POWERPC_SOC=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index abdcd31..98e227e 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -141,6 +141,7 @@ CONFIG_SND_INTEL8X0=y
 # CONFIG_SND_PPC is not set
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=y
+CONFIG_SND_POWERPC_SOC=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 91c9855..0f85f6d 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -35,7 +35,6 @@ source "sound/soc/blackfin/Kconfig"
 source "sound/soc/davinci/Kconfig"
 source "sound/soc/ep93xx/Kconfig"
 source "sound/soc/fsl/Kconfig"
-source "sound/soc/imx/Kconfig"
 source "sound/soc/jz4740/Kconfig"
 source "sound/soc/nuc900/Kconfig"
 source "sound/soc/omap/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 2feaf37..363dfd6 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_SND_SOC)	+= blackfin/
 obj-$(CONFIG_SND_SOC)	+= davinci/
 obj-$(CONFIG_SND_SOC)	+= ep93xx/
 obj-$(CONFIG_SND_SOC)	+= fsl/
-obj-$(CONFIG_SND_SOC)   += imx/
 obj-$(CONFIG_SND_SOC)	+= jz4740/
 obj-$(CONFIG_SND_SOC)	+= mid-x86/
 obj-$(CONFIG_SND_SOC)	+= mxs/
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index ca693b2..19856a0 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,3 +1,15 @@
+config SND_SOC_FSL_SSI
+	tristate
+
+menuconfig SND_POWERPC_SOC
+	tristate "SoC Audio for Freescale PowerPC CPUs"
+	depends on FSL_SOC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the PowerPC CPUs.
+
+if SND_POWERPC_SOC
+
 config SND_MPC52xx_DMA
 	tristate
 
@@ -68,3 +80,83 @@ config SND_MPC52xx_SOC_EFIKA
 	help
 	  Say Y if you want to add support for sound on the Efika.
 
+endif # SND_POWERPC_SOC
+
+menuconfig SND_IMX_SOC
+	tristate "SoC Audio for Freescale i.MX CPUs"
+	depends on ARCH_MXC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the i.MX CPUs.
+
+if SND_IMX_SOC
+
+config SND_SOC_IMX_SSI
+	tristate
+
+config SND_SOC_IMX_PCM
+	tristate
+
+config SND_MXC_SOC_FIQ
+	tristate
+	select FIQ
+	select SND_SOC_IMX_PCM
+
+config SND_MXC_SOC_MX2
+	tristate
+	select SND_SOC_DMAENGINE_PCM
+	select SND_SOC_IMX_PCM
+
+config SND_SOC_IMX_AUDMUX
+	tristate
+
+config SND_MXC_SOC_WM1133_EV1
+	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
+	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
+	select SND_SOC_WM8350
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
+	  PMIC board with WM8835x fitted.
+
+config SND_SOC_MX27VIS_AIC32X4
+	tristate "SoC audio support for Visstrim M10 boards"
+	depends on MACH_IMX27_VISSTRIM_M10 && I2C
+	select SND_SOC_TLV320AIC32X4
+	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Say Y if you want to add support for SoC audio on Visstrim SM10
+	  board with TLV320AIC32X4 codec.
+
+config SND_SOC_PHYCORE_AC97
+	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
+	depends on MACH_PCM043 || MACH_PCA100
+	select SND_SOC_AC97_BUS
+	select SND_SOC_WM9712
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Say Y if you want to add support for SoC audio on Phytec phyCORE
+	  and phyCARD boards in AC97 mode
+
+config SND_SOC_EUKREA_TLV320
+	tristate "Eukrea TLV320"
+	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
+	depends on I2C
+	select SND_SOC_TLV320AIC23
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Enable I2S based access to the TLV320AIC23B codec attached
+	  to the SSI interface
+
+endif # SND_IMX_SOC
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 95d483f..36c257f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -21,3 +21,25 @@ obj-$(CONFIG_SND_SOC_MPC5200_AC97) += mpc5200_psc_ac97.o
 obj-$(CONFIG_SND_MPC52xx_SOC_PCM030) += pcm030-audio-fabric.o
 obj-$(CONFIG_SND_MPC52xx_SOC_EFIKA) += efika-audio-fabric.o
 
+# i.MX Platform Support
+snd-soc-imx-ssi-objs := imx-ssi.o
+snd-soc-imx-audmux-objs := imx-audmux.o
+
+obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
+obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
+
+obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
+snd-soc-imx-pcm-y := imx-pcm.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
+
+# i.MX Machine Support
+snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
+snd-soc-phycore-ac97-objs := phycore-ac97.o
+snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
+snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+
+obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
+obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
+obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
+obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/fsl/eukrea-tlv320.c
similarity index 99%
rename from sound/soc/imx/eukrea-tlv320.c
rename to sound/soc/fsl/eukrea-tlv320.c
index 7d4475c..efb9ede 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/fsl/eukrea-tlv320.c
@@ -7,7 +7,7 @@
  * which is Copyright 2009 Simtec Electronics
  * and on sound/soc/imx/phycore-ac97.c which is
  * Copyright 2009 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
- * 
+ *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
  *  Free Software Foundation;  either version 2 of the  License, or (at your
diff --git a/sound/soc/imx/imx-audmux.c b/sound/soc/fsl/imx-audmux.c
similarity index 100%
rename from sound/soc/imx/imx-audmux.c
rename to sound/soc/fsl/imx-audmux.c
diff --git a/sound/soc/imx/imx-audmux.h b/sound/soc/fsl/imx-audmux.h
similarity index 100%
rename from sound/soc/imx/imx-audmux.h
rename to sound/soc/fsl/imx-audmux.h
diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/fsl/imx-pcm-dma-mx2.c
similarity index 100%
rename from sound/soc/imx/imx-pcm-dma-mx2.c
rename to sound/soc/fsl/imx-pcm-dma-mx2.c
diff --git a/sound/soc/imx/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
similarity index 100%
rename from sound/soc/imx/imx-pcm-fiq.c
rename to sound/soc/fsl/imx-pcm-fiq.c
diff --git a/sound/soc/imx/imx-pcm.c b/sound/soc/fsl/imx-pcm.c
similarity index 100%
rename from sound/soc/imx/imx-pcm.c
rename to sound/soc/fsl/imx-pcm.c
diff --git a/sound/soc/imx/imx-pcm.h b/sound/soc/fsl/imx-pcm.h
similarity index 100%
rename from sound/soc/imx/imx-pcm.h
rename to sound/soc/fsl/imx-pcm.h
diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
similarity index 99%
rename from sound/soc/imx/imx-ssi.c
rename to sound/soc/fsl/imx-ssi.c
index 4f81ed4..cf3ed03 100644
--- a/sound/soc/imx/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -28,7 +28,7 @@
  * value. When we read the same register two times (and the register still
  * contains the same value) these status bits are not set. We work
  * around this by not polling these bits but only wait a fixed delay.
- * 
+ *
  */
 
 #include <linux/clk.h>
diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/fsl/imx-ssi.h
similarity index 100%
rename from sound/soc/imx/imx-ssi.h
rename to sound/soc/fsl/imx-ssi.h
diff --git a/sound/soc/imx/mx27vis-aic32x4.c b/sound/soc/fsl/mx27vis-aic32x4.c
similarity index 100%
rename from sound/soc/imx/mx27vis-aic32x4.c
rename to sound/soc/fsl/mx27vis-aic32x4.c
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/fsl/phycore-ac97.c
similarity index 100%
rename from sound/soc/imx/phycore-ac97.c
rename to sound/soc/fsl/phycore-ac97.c
diff --git a/sound/soc/imx/wm1133-ev1.c b/sound/soc/fsl/wm1133-ev1.c
similarity index 100%
rename from sound/soc/imx/wm1133-ev1.c
rename to sound/soc/fsl/wm1133-ev1.c
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
deleted file mode 100644
index 810acaa..0000000
--- a/sound/soc/imx/Kconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-menuconfig SND_IMX_SOC
-	tristate "SoC Audio for Freescale i.MX CPUs"
-	depends on ARCH_MXC
-	help
-	  Say Y or M if you want to add support for codecs attached to
-	  the i.MX SSI interface.
-
-
-if SND_IMX_SOC
-
-config SND_SOC_IMX_SSI
-	tristate
-
-config SND_SOC_IMX_PCM
-	tristate
-
-config SND_MXC_SOC_FIQ
-	tristate
-	select FIQ
-	select SND_SOC_IMX_PCM
-
-config SND_MXC_SOC_MX2
-	select SND_SOC_DMAENGINE_PCM
-	tristate
-	select SND_SOC_IMX_PCM
-
-config SND_SOC_IMX_AUDMUX
-	tristate
-
-config SND_MXC_SOC_WM1133_EV1
-	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
-	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
-	select SND_SOC_WM8350
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
-	  PMIC board with WM8835x fitted.
-
-config SND_SOC_MX27VIS_AIC32X4
-	tristate "SoC audio support for Visstrim M10 boards"
-	depends on MACH_IMX27_VISSTRIM_M10 && I2C
-	select SND_SOC_TLV320AIC32X4
-	select SND_MXC_SOC_MX2
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Say Y if you want to add support for SoC audio on Visstrim SM10
-	  board with TLV320AIC32X4 codec.
-
-config SND_SOC_PHYCORE_AC97
-	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
-	depends on MACH_PCM043 || MACH_PCA100
-	select SND_SOC_AC97_BUS
-	select SND_SOC_WM9712
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Say Y if you want to add support for SoC audio on Phytec phyCORE
-	  and phyCARD boards in AC97 mode
-
-config SND_SOC_EUKREA_TLV320
-	tristate "Eukrea TLV320"
-	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
-	depends on I2C
-	select SND_SOC_TLV320AIC23
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Enable I2S based access to the TLV320AIC23B codec attached
-	  to the SSI interface
-
-endif	# SND_IMX_SOC
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
deleted file mode 100644
index f5db3e9..0000000
--- a/sound/soc/imx/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-# i.MX Platform Support
-snd-soc-imx-ssi-objs := imx-ssi.o
-snd-soc-imx-audmux-objs := imx-audmux.o
-
-obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
-obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
-
-obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
-snd-soc-imx-pcm-y := imx-pcm.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
-
-# i.MX Machine Support
-snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
-snd-soc-phycore-ac97-objs := phycore-ac97.o
-snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
-snd-soc-wm1133-ev1-objs := wm1133-ev1.o
-
-obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
-obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
-obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
-obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
-- 
1.7.5.4



From linus.walleij at linaro.org  Mon Mar 12 17:42:48 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 12 Mar 2012 22:42:48 +0100
Subject: [PATCH V2 2/3] pinctrl: allow concurrent gpio and mux function
 ownership of pins
In-Reply-To: <4F5E3F63.5080506@wwwdotorg.org>
References: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
 <1330993336-9538-2-git-send-email-swarren@nvidia.com>
 <CACRpkdYdSaNsrr34o2Cc4vS12ee9oY7FG0pxB92mefHZKwdEpA@mail.gmail.com>
 <4F5E3F63.5080506@wwwdotorg.org>
Message-ID: <CACRpkdYsD2LCNoox6ztHTP76X8a_qxjiZFO4ou=BgZ4oE0qHtg@mail.gmail.com>

On Mon, Mar 12, 2012 at 7:24 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:

> Linus, now that Grant has ack'd and applied the documentation change
> behind this, could you take this one patch into the pinctrl tree.

Of course, applied.

> I assume it's 3.5 material.

No it goes in now, we can't have documentation that is misleading...
Besides, I like it.

Yours,
Linus Walleij


From stigge at antcom.de  Mon Mar 12 17:52:47 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 12 Mar 2012 22:52:47 +0100
Subject: [PATCH v7 0/4] USB: OHCI-HCD: Support for LPC32xx
In-Reply-To: <20120312190241.GA28087@pengutronix.de>
References: <1331463219-23293-1-git-send-email-stigge@antcom.de>
 <20120312190241.GA28087@pengutronix.de>
Message-ID: <4F5E702F.8040703@antcom.de>

Hi Wolfram,

On 12/03/12 20:02, Wolfram Sang wrote:
> On Sun, Mar 11, 2012 at 11:53:35AM +0100, Roland Stigge wrote:
>> These patches add support for the LPC32xx to the ohci-pnx4008
>> driver and make the driver use smbus functions.
> 
> Do you have a branch ready to test (USB driver fixes + mach
> additions)? I'd like to test but I get lots of conflicts when
> adding the mach related stuff. I probably have a different base?

I just pushed into the following branches at
git://git.antcom.de/linux-2.6.git :

* lpc32xx/usb - The ohci-pnx driver as submitted on the USB mailing list
* lpc32xx/eth - The ethernet driver as submitted on the ethernet
                mailing list
* lpc32xx/baseline - Patches on top of v3.3-rc7 which have already been
                     accepted into the various subsystem maintainer's
                     repos. This is the baseline on top of which the
                     next two branches are forked from
* lpc32xx/mach-lpc32xx-usb - Mach specific USB part
* lpc32xx/mach-lpc32xx-eth - Mach specific ethernet part

Roland


From stigge at antcom.de  Mon Mar 12 17:54:51 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 12 Mar 2012 22:54:51 +0100
Subject: [PATCH v8 3/4] USB: ohci-nxp: Support for LPC32xx
In-Reply-To: <1331589292-18986-1-git-send-email-stigge@antcom.de>
References: <1331589292-18986-1-git-send-email-stigge@antcom.de>
Message-ID: <1331589292-18986-4-git-send-email-stigge@antcom.de>

This patch adds support for the LPC32xx to ohci-nxp

Signed-off-by: Roland Stigge <stigge at antcom.de>
---
 drivers/usb/host/ohci-hcd.c |    2 +-
 drivers/usb/host/ohci-nxp.c |  142 ++++++++++++++++++++++++++++++++----------
 2 files changed, 109 insertions(+), 35 deletions(-)

diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index c190962..1c1a506 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1050,7 +1050,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_hcd_at91_driver
 #endif
 
-#ifdef CONFIG_ARCH_PNX4008
+#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX)
 #include "ohci-nxp.c"
 #define PLATFORM_DRIVER		usb_hcd_nxp_driver
 #endif
diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c
index a12c6b4..e7cc7b6 100644
--- a/drivers/usb/host/ohci-nxp.c
+++ b/drivers/usb/host/ohci-nxp.c
@@ -3,6 +3,7 @@
  *
  * Currently supported OHCI host devices:
  * - Philips PNX4008
+ * - NXP LPC32xx
  *
  * Authors: Dmitry Chigirev <source at mvista.com>
  *	    Vitaly Wool <vitalywool at gmail.com>
@@ -23,20 +24,24 @@
 #include <linux/i2c.h>
 
 #include <mach/hardware.h>
+#include <asm/mach-types.h>
 #include <asm/io.h>
 
 #include <mach/platform.h>
 #include <mach/irqs.h>
 #include <asm/gpio.h>
 
-#define USB_CTRL	IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64)
+#define USB_CONFIG_BASE		0x31020000
+#define PWRMAN_BASE		0x40004000
+
+#define USB_CTRL		IO_ADDRESS(PWRMAN_BASE + 0x64)
 
 /* USB_CTRL bit defines */
 #define USB_SLAVE_HCLK_EN	(1 << 24)
 #define USB_HOST_NEED_CLK_EN	(1 << 21)
 
-#define USB_OTG_CLK_CTRL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF4)
-#define USB_OTG_CLK_STAT	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF8)
+#define USB_OTG_CLK_CTRL	IO_ADDRESS(USB_CONFIG_BASE + 0xFF4)
+#define USB_OTG_CLK_STAT	IO_ADDRESS(USB_CONFIG_BASE + 0xFF8)
 
 /* USB_OTG_CLK_CTRL bit defines */
 #define AHB_M_CLOCK_ON		(1 << 4)
@@ -45,7 +50,7 @@
 #define DEV_CLOCK_ON		(1 << 1)
 #define HOST_CLOCK_ON		(1 << 0)
 
-#define USB_OTG_STAT_CONTROL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x110)
+#define USB_OTG_STAT_CONTROL	IO_ADDRESS(USB_CONFIG_BASE + 0x110)
 
 /* USB_OTG_STAT_CONTROL bit defines */
 #define TRANSPARENT_I2C_EN	(1 << 7)
@@ -99,6 +104,15 @@
 #define ISP1301_I2C_INTERRUPT_RISING 0xE
 #define ISP1301_I2C_REG_CLEAR_ADDR 1
 
+/* On LPC32xx, those are undefined */
+#ifndef start_int_set_falling_edge
+#define start_int_set_falling_edge(irq)
+#define start_int_set_rising_edge(irq)
+#define start_int_ack(irq)
+#define start_int_mask(irq)
+#define start_int_umask(irq)
+#endif
+
 static struct i2c_driver isp1301_driver;
 static struct i2c_client *isp1301_i2c_client;
 
@@ -144,7 +158,7 @@ static void i2c_write(u8 buf, u8 subaddr)
 	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
 }
 
-static void isp1301_configure(void)
+static void isp1301_configure_pnx4008(void)
 {
 	/* PNX4008 only supports DAT_SE0 USB mode */
 	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
@@ -167,7 +181,63 @@ static void isp1301_configure(void)
 		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
 	i2c_write(0xFF,
 		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+}
 
+static void isp1301_configure_lpc32xx(void)
+{
+	/* LPC32XX only supports DAT_SE0 USB mode */
+	/* This sequence is important */
+
+	/* Disable transparent UART mode first */
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		(ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
+		MC1_UART_EN);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		(ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
+		~MC1_SPEED_REG);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+				  ISP1301_I2C_MODE_CONTROL_1, MC1_SPEED_REG);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		  (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR),
+		  ~0);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_2,
+		(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_OTG_CONTROL_1,
+		(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
+		(OTG1_DM_PULLUP | OTG1_DP_PULLUP));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
+		~0);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
+
+	/* Enable usb_need_clk clock after transceiver is initialized */
+	__raw_writel((__raw_readl(USB_CTRL) | (1 << 22)), USB_CTRL);
+
+	printk(KERN_INFO "ISP1301 Vendor ID  : 0x%04x\n",
+	      i2c_smbus_read_word_data(isp1301_i2c_client, 0x00));
+	printk(KERN_INFO "ISP1301 Product ID : 0x%04x\n",
+	      i2c_smbus_read_word_data(isp1301_i2c_client, 0x02));
+	printk(KERN_INFO "ISP1301 Version ID : 0x%04x\n",
+	      i2c_smbus_read_word_data(isp1301_i2c_client, 0x14));
+}
+
+static void isp1301_configure(void)
+{
+	if (machine_is_pnx4008())
+		isp1301_configure_pnx4008();
+	else
+		isp1301_configure_lpc32xx();
 }
 
 static inline void isp1301_vbus_on(void)
@@ -258,39 +328,43 @@ static const struct hc_driver ohci_nxp_hc_driver = {
 
 static void nxp_set_usb_bits(void)
 {
-	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-	start_int_ack(SE_USB_OTG_ATX_INT_N);
-	start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-	start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-	start_int_ack(SE_USB_OTG_TIMER_INT);
-	start_int_umask(SE_USB_OTG_TIMER_INT);
-
-	start_int_set_rising_edge(SE_USB_I2C_INT);
-	start_int_ack(SE_USB_I2C_INT);
-	start_int_umask(SE_USB_I2C_INT);
-
-	start_int_set_rising_edge(SE_USB_INT);
-	start_int_ack(SE_USB_INT);
-	start_int_umask(SE_USB_INT);
-
-	start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-	start_int_ack(SE_USB_NEED_CLK_INT);
-	start_int_umask(SE_USB_NEED_CLK_INT);
-
-	start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-	start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+	if (machine_is_pnx4008()) {
+		start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
+		start_int_ack(SE_USB_OTG_ATX_INT_N);
+		start_int_umask(SE_USB_OTG_ATX_INT_N);
+
+		start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
+		start_int_ack(SE_USB_OTG_TIMER_INT);
+		start_int_umask(SE_USB_OTG_TIMER_INT);
+
+		start_int_set_rising_edge(SE_USB_I2C_INT);
+		start_int_ack(SE_USB_I2C_INT);
+		start_int_umask(SE_USB_I2C_INT);
+
+		start_int_set_rising_edge(SE_USB_INT);
+		start_int_ack(SE_USB_INT);
+		start_int_umask(SE_USB_INT);
+
+		start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
+		start_int_ack(SE_USB_NEED_CLK_INT);
+		start_int_umask(SE_USB_NEED_CLK_INT);
+
+		start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
+		start_int_ack(SE_USB_AHB_NEED_CLK_INT);
+		start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+	}
 }
 
 static void nxp_unset_usb_bits(void)
 {
-	start_int_mask(SE_USB_OTG_ATX_INT_N);
-	start_int_mask(SE_USB_OTG_TIMER_INT);
-	start_int_mask(SE_USB_I2C_INT);
-	start_int_mask(SE_USB_INT);
-	start_int_mask(SE_USB_NEED_CLK_INT);
-	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+	if (machine_is_pnx4008()) {
+		start_int_mask(SE_USB_OTG_ATX_INT_N);
+		start_int_mask(SE_USB_OTG_TIMER_INT);
+		start_int_mask(SE_USB_I2C_INT);
+		start_int_mask(SE_USB_INT);
+		start_int_mask(SE_USB_NEED_CLK_INT);
+		start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+	}
 }
 
 static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
-- 
1.7.9



From stigge at antcom.de  Mon Mar 12 17:54:49 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 12 Mar 2012 22:54:49 +0100
Subject: [PATCH v8 1/4] USB: OHCI-HCD: Rename ohci-pnx4008 to ohci-nxp
In-Reply-To: <1331589292-18986-1-git-send-email-stigge@antcom.de>
References: <1331589292-18986-1-git-send-email-stigge@antcom.de>
Message-ID: <1331589292-18986-2-git-send-email-stigge@antcom.de>

Since this driver is compatible with several NXP devices, the driver is renamed
accordingly. Please combine with the following patch which also changes the
respective symbol names.

Signed-off-by: Roland Stigge <stigge at antcom.de>
---
 drivers/usb/host/ohci-hcd.c                     |    2 +-
 drivers/usb/host/{ohci-pnx4008.c => ohci-nxp.c} |    0
 2 files changed, 1 insertions(+), 1 deletions(-)
 rename drivers/usb/host/{ohci-pnx4008.c => ohci-nxp.c} (100%)

diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 34b9edd..713c66c 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1051,7 +1051,7 @@ MODULE_LICENSE ("GPL");
 #endif
 
 #ifdef CONFIG_ARCH_PNX4008
-#include "ohci-pnx4008.c"
+#include "ohci-nxp.c"
 #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
 #endif
 
diff --git a/drivers/usb/host/ohci-pnx4008.c b/drivers/usb/host/ohci-nxp.c
similarity index 100%
rename from drivers/usb/host/ohci-pnx4008.c
rename to drivers/usb/host/ohci-nxp.c
-- 
1.7.9



From stigge at antcom.de  Mon Mar 12 17:54:48 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 12 Mar 2012 22:54:48 +0100
Subject: [PATCH v8 0/4] USB: OHCI-HCD: Support for LPC32xx
Message-ID: <1331589292-18986-1-git-send-email-stigge@antcom.de>

These patches add support for the LPC32xx to the ohci-pnx4008 driver and make
the driver use smbus functions.

As discussed with Greg-KH on the USB mailing list, the ohci-pnx4008 driver is
first renamed to reflect its multi-platform support. The second patch also
renames the respective pnx4008_* symbols accordingly.

The third patch adds the actual lpc32xx support.

The fourth patch removes the re-coded i2c_write() by using an existing smbus
function. You can leave out this very single patch to still have the desired
LPC32xx support. It just fixes existing kernel code to only use smbus calls in
this driver.

Applies to v3.3-rc7

Changes since v7:

* Removed pnx4008 filename reference
* Rename via git format-patch -M

Thanks to Arnd Bergmann and Wolfram Sang for reviewing!

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Roland Stigge (4):
  USB: OHCI-HCD: Rename ohci-pnx4008 to ohci-nxp
  USB: ohci-nxp: Rename symbols from pnx4008 to nxp
  USB: ohci-nxp: Support for LPC32xx
  USB: ohci-nxp: Remove i2c_write(), use smbus

 Documentation/i2c/instantiating-devices         |    6 +-
 drivers/usb/host/ohci-hcd.c                     |    6 +-
 drivers/usb/host/{ohci-pnx4008.c => ohci-nxp.c} |  253 +++++++++++++++--------
 3 files changed, 170 insertions(+), 95 deletions(-)
 rename drivers/usb/host/{ohci-pnx4008.c => ohci-nxp.c} (57%)

-- 
1.7.9



From stigge at antcom.de  Mon Mar 12 17:54:52 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 12 Mar 2012 22:54:52 +0100
Subject: [PATCH v8 4/4] USB: ohci-nxp: Remove i2c_write(), use smbus
In-Reply-To: <1331589292-18986-1-git-send-email-stigge@antcom.de>
References: <1331589292-18986-1-git-send-email-stigge@antcom.de>
Message-ID: <1331589292-18986-5-git-send-email-stigge@antcom.de>

This patch removes the re-coded i2c_write function from the ohci-nxp driver
in favour of using just smbus functions.

Signed-off-by: Roland Stigge <stigge at antcom.de>
---
 drivers/usb/host/ohci-nxp.c |   58 +++++++++++++++++++++---------------------
 1 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c
index e7cc7b6..6618de1 100644
--- a/drivers/usb/host/ohci-nxp.c
+++ b/drivers/usb/host/ohci-nxp.c
@@ -149,38 +149,36 @@ static struct i2c_driver isp1301_driver = {
 	.id_table = isp1301_id,
 };
 
-static void i2c_write(u8 buf, u8 subaddr)
-{
-	char tmpbuf[2];
-
-	tmpbuf[0] = subaddr;	/*register number */
-	tmpbuf[1] = buf;	/*register data */
-	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
-}
-
 static void isp1301_configure_pnx4008(void)
 {
 	/* PNX4008 only supports DAT_SE0 USB mode */
 	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
 	/* Power up externel charge-pump */
 
-	i2c_write(MC1_DAT_SE0 | MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
-	i2c_write(~(MC1_DAT_SE0 | MC1_SPEED_REG),
-		  ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL,
-		  ISP1301_I2C_MODE_CONTROL_2);
-	i2c_write(~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
-		  ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN,
-		  ISP1301_I2C_OTG_CONTROL_1);
-	i2c_write(~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
-		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
-	i2c_write(0xFF,
-		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0 | MC1_SPEED_REG);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
+		~(MC1_DAT_SE0 | MC1_SPEED_REG));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_2,
+		MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
+		~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_OTG_CONTROL_1, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
+		~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, 0xFF);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
+		0xFF);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR,
+		0xFF);
 }
 
 static void isp1301_configure_lpc32xx(void)
@@ -242,13 +240,15 @@ static void isp1301_configure(void)
 
 static inline void isp1301_vbus_on(void)
 {
-	i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1);
+	i2c_smbus_write_byte_data(isp1301_i2c_client, ISP1301_I2C_OTG_CONTROL_1,
+				  OTG1_VBUS_DRV);
 }
 
 static inline void isp1301_vbus_off(void)
 {
-	i2c_write(OTG1_VBUS_DRV,
-		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
+		OTG1_VBUS_DRV);
 }
 
 static void nxp_start_hc(void)
-- 
1.7.9



From khilman at ti.com  Mon Mar 12 17:54:17 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 12 Mar 2012 14:54:17 -0700
Subject: [PATCH v3 11/13] gpio/omap: fix dataout register overwrite in
 _set_gpio_dataout_*
In-Reply-To: <1331118963-26364-12-git-send-email-tarun.kanti@ti.com> (Tarun
 Kanti DebBarma's message of "Wed, 7 Mar 2012 16:46:01 +0530")
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-12-git-send-email-tarun.kanti@ti.com>
Message-ID: <87y5r5wkmu.fsf@ti.com>

Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:

> In the existing _set_gpio_dataout_*() implementation, the dataout
> register is overwritten every time the function is called. This is
> not intended behavior because that would end up one user of a GPIO
> line overwriting what is written by another. Fix this so that previous
> value is always preserved until explicitly changed by respective
> user/driver of the GPIO line.
>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> ---
>  drivers/gpio/gpio-omap.c |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 04c2677..2e8e476 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -114,6 +114,7 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
>  	else
>  		reg += bank->regs->clr_dataout;
>  
> +	l |= __raw_readl(bank->base + bank->regs->set_dataout);

minor: IMO, it's more reader-friendly if this looks like

       l = __raw_read(...)
       l |= GPIO_BIT(...)
       __raw_write(...)

>  	__raw_writel(l, reg);
>  	bank->context.dataout = l;
>  }
> @@ -130,6 +131,8 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
>  		l |= gpio_bit;
>  	else
>  		l &= ~gpio_bit;
> +
> +	l |= __raw_readl(bank->base + bank->regs->set_dataout);

There's already a __raw_read() in this function just above.

>  	__raw_writel(l, reg);
>  	bank->context.dataout = l;
>  }


From robherring2 at gmail.com  Mon Mar 12 18:00:57 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 12 Mar 2012 17:00:57 -0500
Subject: [PATCH v6 3/3] clk: basic clock hardware types
In-Reply-To: <CAJOA=zOS44YRfg3A7D8G+jWoQ_gzRQ937A7tYDU+DxWce_khzQ@mail.gmail.com>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-4-git-send-email-mturquette@linaro.org>
 <4F5E5A0C.6080604@gmail.com>
 <CAJOA=zOS44YRfg3A7D8G+jWoQ_gzRQ937A7tYDU+DxWce_khzQ@mail.gmail.com>
Message-ID: <4F5E7219.7020301@gmail.com>

On 03/12/2012 03:58 PM, Turquette, Mike wrote:
> On Mon, Mar 12, 2012 at 1:18 PM, Rob Herring <robherring2 at gmail.com> wrote:
>> On 03/10/2012 01:54 AM, Mike Turquette wrote:
>>> Many platforms support simple gateable clocks, fixed-rate clocks,
>>> adjustable divider clocks and multi-parent multiplexer clocks.
>>>
>>> This patch introduces basic clock types for the above-mentioned hardware
>>> which share some common characteristics.
>>>
>>> Based on original work by Jeremy Kerr and contribution by Jamie Iles.
>>> Dividers and multiplexor clocks originally contributed by Richard Zhao &
>>> Sascha Hauer.
>>>

snip

>>> +static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
>>> +             unsigned long parent_rate)
>>> +{
>>> +     struct clk_divider *divider = to_clk_divider(hw);
>>> +     unsigned int div;
>>> +     unsigned long flags = 0;
>>> +
>>> +     if (divider->lock)
>>> +             spin_lock_irqsave(divider->lock, flags);
>>> +
>>> +     div = readl(divider->reg) >> divider->shift;
>>> +     div &= (1 << divider->width) - 1;
>>> +
>>> +     if (divider->lock)
>>> +             spin_unlock_irqrestore(divider->lock, flags);
>>
>> What are you locking against? You are only reading the register.
> 
> Hi Rob,
> 
> These register-level locks originally came in from the divider &
> multiplexer patches from Richard and Sascha and I'm sure they can give
> you more details than I.
> 
> Basically on their platform they have some 32-bits regs that have a
> lot of overlapping clock functions in them, such as enable/disable and
> adjusting a divider all in one reg.  Those operations are protected by
> different locks (enable spinlock and prepare mutex, respectively) so
> some synchronization mechanism is necessary.  On OMAP we don't use
> this since we have a billion registers that typically only map to one
> clock each.  I also wonder if having device type memory for the
> affected regions makes a this irrelevant on ARM... but that wouldn't
> matter for non-ARM architectures.  Just a thought.
> 

In fact, I pointed out that locking for a register access was needed in
an early version of this series as well. However, locking is only needed
if you are doing a read-mod-write on a field in a shared register or
reading from multiple registers. It makes no sense if you are *only*
reading a single shared register as is the case here. That's already an
atomic operation.

Rob



From stigge at antcom.de  Mon Mar 12 17:54:50 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 12 Mar 2012 22:54:50 +0100
Subject: [PATCH v8 2/4] USB: ohci-nxp: Rename symbols from pnx4008 to nxp
In-Reply-To: <1331589292-18986-1-git-send-email-stigge@antcom.de>
References: <1331589292-18986-1-git-send-email-stigge@antcom.de>
Message-ID: <1331589292-18986-3-git-send-email-stigge@antcom.de>

Since this driver is compatible with several NXP devices, the driver was renamed
accordingly. This patch also changes the respective symbol names.

Signed-off-by: Roland Stigge <stigge at antcom.de>
---
 Documentation/i2c/instantiating-devices |    6 ++--
 drivers/usb/host/ohci-hcd.c             |    2 +-
 drivers/usb/host/ohci-nxp.c             |   53 ++++++++++++++++---------------
 3 files changed, 31 insertions(+), 30 deletions(-)

diff --git a/Documentation/i2c/instantiating-devices b/Documentation/i2c/instantiating-devices
index 9edb75d..abf6361 100644
--- a/Documentation/i2c/instantiating-devices
+++ b/Documentation/i2c/instantiating-devices
@@ -87,11 +87,11 @@ it may have different addresses from one board to the next (manufacturer
 changing its design without notice). In this case, you can call
 i2c_new_probed_device() instead of i2c_new_device().
 
-Example (from the pnx4008 OHCI driver):
+Example (from the nxp OHCI driver):
 
 static const unsigned short normal_i2c[] = { 0x2c, 0x2d, I2C_CLIENT_END };
 
-static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
+static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
 	(...)
 	struct i2c_adapter *i2c_adap;
@@ -100,7 +100,7 @@ static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
 	(...)
 	i2c_adap = i2c_get_adapter(2);
 	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
-	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
+	strlcpy(i2c_info.type, "isp1301_nxp", I2C_NAME_SIZE);
 	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
 						   normal_i2c, NULL);
 	i2c_put_adapter(i2c_adap);
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 713c66c..c190962 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1052,7 +1052,7 @@ MODULE_LICENSE ("GPL");
 
 #ifdef CONFIG_ARCH_PNX4008
 #include "ohci-nxp.c"
-#define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
+#define PLATFORM_DRIVER		usb_hcd_nxp_driver
 #endif
 
 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c
index 0013db7..a12c6b4 100644
--- a/drivers/usb/host/ohci-nxp.c
+++ b/drivers/usb/host/ohci-nxp.c
@@ -1,7 +1,8 @@
 /*
- * drivers/usb/host/ohci-pnx4008.c
+ * driver for NXP USB Host devices
  *
- * driver for Philips PNX4008 USB Host
+ * Currently supported OHCI host devices:
+ * - Philips PNX4008
  *
  * Authors: Dmitry Chigirev <source at mvista.com>
  *	    Vitaly Wool <vitalywool at gmail.com>
@@ -121,13 +122,13 @@ static int isp1301_remove(struct i2c_client *client)
 }
 
 static const struct i2c_device_id isp1301_id[] = {
-	{ "isp1301_pnx", 0 },
+	{ "isp1301_nxp", 0 },
 	{ }
 };
 
 static struct i2c_driver isp1301_driver = {
 	.driver = {
-		.name = "isp1301_pnx",
+		.name = "isp1301_nxp",
 	},
 	.probe = isp1301_probe,
 	.remove = isp1301_remove,
@@ -180,14 +181,14 @@ static inline void isp1301_vbus_off(void)
 		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
 }
 
-static void pnx4008_start_hc(void)
+static void nxp_start_hc(void)
 {
 	unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
 	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
 	isp1301_vbus_on();
 }
 
-static void pnx4008_stop_hc(void)
+static void nxp_stop_hc(void)
 {
 	unsigned long tmp;
 	isp1301_vbus_off();
@@ -195,7 +196,7 @@ static void pnx4008_stop_hc(void)
 	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
 }
 
-static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd)
+static int __devinit ohci_nxp_start(struct usb_hcd *hcd)
 {
 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
 	int ret;
@@ -211,9 +212,9 @@ static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd)
 	return 0;
 }
 
-static const struct hc_driver ohci_pnx4008_hc_driver = {
+static const struct hc_driver ohci_nxp_hc_driver = {
 	.description = hcd_name,
-	.product_desc =		"pnx4008 OHCI",
+	.product_desc =		"nxp OHCI",
 
 	/*
 	 * generic hardware linkage
@@ -225,7 +226,7 @@ static const struct hc_driver ohci_pnx4008_hc_driver = {
 	/*
 	 * basic lifecycle operations
 	 */
-	.start = ohci_pnx4008_start,
+	.start = ohci_nxp_start,
 	.stop = ohci_stop,
 	.shutdown = ohci_shutdown,
 
@@ -255,7 +256,7 @@ static const struct hc_driver ohci_pnx4008_hc_driver = {
 
 #define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON)
 
-static void pnx4008_set_usb_bits(void)
+static void nxp_set_usb_bits(void)
 {
 	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
 	start_int_ack(SE_USB_OTG_ATX_INT_N);
@@ -282,7 +283,7 @@ static void pnx4008_set_usb_bits(void)
 	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
 }
 
-static void pnx4008_unset_usb_bits(void)
+static void nxp_unset_usb_bits(void)
 {
 	start_int_mask(SE_USB_OTG_ATX_INT_N);
 	start_int_mask(SE_USB_OTG_TIMER_INT);
@@ -292,17 +293,17 @@ static void pnx4008_unset_usb_bits(void)
 	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
 }
 
-static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
+static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd = 0;
 	struct ohci_hcd *ohci;
-	const struct hc_driver *driver = &ohci_pnx4008_hc_driver;
+	const struct hc_driver *driver = &ohci_nxp_hc_driver;
 	struct i2c_adapter *i2c_adap;
 	struct i2c_board_info i2c_info;
 
 	int ret = 0, irq;
 
-	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (pnx4008)\n", hcd_name);
+	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (nxp)\n", hcd_name);
 	if (usb_disabled()) {
 		err("USB is disabled");
 		ret = -ENODEV;
@@ -327,7 +328,7 @@ static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
 	}
 	i2c_adap = i2c_get_adapter(2);
 	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
-	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
+	strlcpy(i2c_info.type, "isp1301_nxp", I2C_NAME_SIZE);
 	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
 						   normal_i2c, NULL);
 	i2c_put_adapter(i2c_adap);
@@ -375,7 +376,7 @@ static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
 	}
 
 	/* Set all USB bits in the Start Enable register */
-	pnx4008_set_usb_bits();
+	nxp_set_usb_bits();
 
 	hcd->rsrc_start = pdev->resource[0].start;
 	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
@@ -392,7 +393,7 @@ static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
 		goto out4;
 	}
 
-	pnx4008_start_hc();
+	nxp_start_hc();
 	platform_set_drvdata(pdev, hcd);
 	ohci = hcd_to_ohci(hcd);
 	ohci_hcd_init(ohci);
@@ -402,9 +403,9 @@ static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
 	if (ret == 0)
 		return ret;
 
-	pnx4008_stop_hc();
+	nxp_stop_hc();
 out4:
-	pnx4008_unset_usb_bits();
+	nxp_unset_usb_bits();
 	usb_put_hcd(hcd);
 out3:
 	clk_disable(usb_clk);
@@ -419,15 +420,15 @@ out:
 	return ret;
 }
 
-static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
+static int usb_hcd_nxp_remove(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd = platform_get_drvdata(pdev);
 
 	usb_remove_hcd(hcd);
-	pnx4008_stop_hc();
+	nxp_stop_hc();
 	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 	usb_put_hcd(hcd);
-	pnx4008_unset_usb_bits();
+	nxp_unset_usb_bits();
 	clk_disable(usb_clk);
 	clk_put(usb_clk);
 	i2c_unregister_device(isp1301_i2c_client);
@@ -442,12 +443,12 @@ static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
 /* work with hotplug and coldplug */
 MODULE_ALIAS("platform:usb-ohci");
 
-static struct platform_driver usb_hcd_pnx4008_driver = {
+static struct platform_driver usb_hcd_nxp_driver = {
 	.driver = {
 		.name = "usb-ohci",
 		.owner	= THIS_MODULE,
 	},
-	.probe = usb_hcd_pnx4008_probe,
-	.remove = usb_hcd_pnx4008_remove,
+	.probe = usb_hcd_nxp_probe,
+	.remove = usb_hcd_nxp_remove,
 };
 
-- 
1.7.9



From stigge at antcom.de  Sun Mar 11 06:53:37 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 11 Mar 2012 11:53:37 +0100
Subject: [PATCH v7 2/4] USB: ohci-nxp: Rename symbols from pnx4008 to nxp
In-Reply-To: <1331463219-23293-1-git-send-email-stigge@antcom.de>
References: <1331463219-23293-1-git-send-email-stigge@antcom.de>
Message-ID: <1331463219-23293-3-git-send-email-stigge@antcom.de>

Since this driver is compatible with several NXP devices, the driver was renamed
accordingly. This patch also changes the respective symbol names.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 Documentation/i2c/instantiating-devices |    6 +--
 drivers/usb/host/ohci-hcd.c             |    2 -
 drivers/usb/host/ohci-nxp.c             |   55 ++++++++++++++++----------------
 3 files changed, 33 insertions(+), 30 deletions(-)

--- linux-2.6.orig/Documentation/i2c/instantiating-devices
+++ linux-2.6/Documentation/i2c/instantiating-devices
@@ -87,11 +87,11 @@ it may have different addresses from one
 changing its design without notice). In this case, you can call
 i2c_new_probed_device() instead of i2c_new_device().
 
-Example (from the pnx4008 OHCI driver):
+Example (from the nxp OHCI driver):
 
 static const unsigned short normal_i2c[] = { 0x2c, 0x2d, I2C_CLIENT_END };
 
-static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
+static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
 	(...)
 	struct i2c_adapter *i2c_adap;
@@ -100,7 +100,7 @@ static int __devinit usb_hcd_pnx4008_pro
 	(...)
 	i2c_adap = i2c_get_adapter(2);
 	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
-	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
+	strlcpy(i2c_info.type, "isp1301_nxp", I2C_NAME_SIZE);
 	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
 						   normal_i2c, NULL);
 	i2c_put_adapter(i2c_adap);
--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1052,7 +1052,7 @@ MODULE_LICENSE ("GPL");
 
 #ifdef CONFIG_ARCH_PNX4008
 #include "ohci-nxp.c"
-#define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
+#define PLATFORM_DRIVER		usb_hcd_nxp_driver
 #endif
 
 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
--- linux-2.6.orig/drivers/usb/host/ohci-nxp.c
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -1,7 +1,10 @@
 /*
- * drivers/usb/host/ohci-pnx4008.c
+ * drivers/usb/host/ohci-nxp.c
  *
- * driver for Philips PNX4008 USB Host
+ * driver for NXP USB Host devices
+ *
+ * Currently supported OHCI host devices:
+ * - Philips PNX4008
  *
  * Authors: Dmitry Chigirev <source at mvista.com>
  *	    Vitaly Wool <vitalywool at gmail.com>
@@ -121,13 +124,13 @@ static int isp1301_remove(struct i2c_cli
 }
 
 static const struct i2c_device_id isp1301_id[] = {
-	{ "isp1301_pnx", 0 },
+	{ "isp1301_nxp", 0 },
 	{ }
 };
 
 static struct i2c_driver isp1301_driver = {
 	.driver = {
-		.name = "isp1301_pnx",
+		.name = "isp1301_nxp",
 	},
 	.probe = isp1301_probe,
 	.remove = isp1301_remove,
@@ -180,14 +183,14 @@ static inline void isp1301_vbus_off(void
 		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
 }
 
-static void pnx4008_start_hc(void)
+static void nxp_start_hc(void)
 {
 	unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
 	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
 	isp1301_vbus_on();
 }
 
-static void pnx4008_stop_hc(void)
+static void nxp_stop_hc(void)
 {
 	unsigned long tmp;
 	isp1301_vbus_off();
@@ -195,7 +198,7 @@ static void pnx4008_stop_hc(void)
 	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
 }
 
-static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd)
+static int __devinit ohci_nxp_start(struct usb_hcd *hcd)
 {
 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
 	int ret;
@@ -211,9 +214,9 @@ static int __devinit ohci_pnx4008_start(
 	return 0;
 }
 
-static const struct hc_driver ohci_pnx4008_hc_driver = {
+static const struct hc_driver ohci_nxp_hc_driver = {
 	.description = hcd_name,
-	.product_desc =		"pnx4008 OHCI",
+	.product_desc =		"nxp OHCI",
 
 	/*
 	 * generic hardware linkage
@@ -225,7 +228,7 @@ static const struct hc_driver ohci_pnx40
 	/*
 	 * basic lifecycle operations
 	 */
-	.start = ohci_pnx4008_start,
+	.start = ohci_nxp_start,
 	.stop = ohci_stop,
 	.shutdown = ohci_shutdown,
 
@@ -255,7 +258,7 @@ static const struct hc_driver ohci_pnx40
 
 #define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON)
 
-static void pnx4008_set_usb_bits(void)
+static void nxp_set_usb_bits(void)
 {
 	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
 	start_int_ack(SE_USB_OTG_ATX_INT_N);
@@ -282,7 +285,7 @@ static void pnx4008_set_usb_bits(void)
 	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
 }
 
-static void pnx4008_unset_usb_bits(void)
+static void nxp_unset_usb_bits(void)
 {
 	start_int_mask(SE_USB_OTG_ATX_INT_N);
 	start_int_mask(SE_USB_OTG_TIMER_INT);
@@ -292,17 +295,17 @@ static void pnx4008_unset_usb_bits(void)
 	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
 }
 
-static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
+static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd = 0;
 	struct ohci_hcd *ohci;
-	const struct hc_driver *driver = &ohci_pnx4008_hc_driver;
+	const struct hc_driver *driver = &ohci_nxp_hc_driver;
 	struct i2c_adapter *i2c_adap;
 	struct i2c_board_info i2c_info;
 
 	int ret = 0, irq;
 
-	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (pnx4008)\n", hcd_name);
+	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (nxp)\n", hcd_name);
 	if (usb_disabled()) {
 		err("USB is disabled");
 		ret = -ENODEV;
@@ -327,7 +330,7 @@ static int __devinit usb_hcd_pnx4008_pro
 	}
 	i2c_adap = i2c_get_adapter(2);
 	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
-	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
+	strlcpy(i2c_info.type, "isp1301_nxp", I2C_NAME_SIZE);
 	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
 						   normal_i2c, NULL);
 	i2c_put_adapter(i2c_adap);
@@ -375,7 +378,7 @@ static int __devinit usb_hcd_pnx4008_pro
 	}
 
 	/* Set all USB bits in the Start Enable register */
-	pnx4008_set_usb_bits();
+	nxp_set_usb_bits();
 
 	hcd->rsrc_start = pdev->resource[0].start;
 	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
@@ -392,7 +395,7 @@ static int __devinit usb_hcd_pnx4008_pro
 		goto out4;
 	}
 
-	pnx4008_start_hc();
+	nxp_start_hc();
 	platform_set_drvdata(pdev, hcd);
 	ohci = hcd_to_ohci(hcd);
 	ohci_hcd_init(ohci);
@@ -402,9 +405,9 @@ static int __devinit usb_hcd_pnx4008_pro
 	if (ret == 0)
 		return ret;
 
-	pnx4008_stop_hc();
+	nxp_stop_hc();
 out4:
-	pnx4008_unset_usb_bits();
+	nxp_unset_usb_bits();
 	usb_put_hcd(hcd);
 out3:
 	clk_disable(usb_clk);
@@ -419,15 +422,15 @@ out:
 	return ret;
 }
 
-static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
+static int usb_hcd_nxp_remove(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd = platform_get_drvdata(pdev);
 
 	usb_remove_hcd(hcd);
-	pnx4008_stop_hc();
+	nxp_stop_hc();
 	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 	usb_put_hcd(hcd);
-	pnx4008_unset_usb_bits();
+	nxp_unset_usb_bits();
 	clk_disable(usb_clk);
 	clk_put(usb_clk);
 	i2c_unregister_device(isp1301_i2c_client);
@@ -442,12 +445,12 @@ static int usb_hcd_pnx4008_remove(struct
 /* work with hotplug and coldplug */
 MODULE_ALIAS("platform:usb-ohci");
 
-static struct platform_driver usb_hcd_pnx4008_driver = {
+static struct platform_driver usb_hcd_nxp_driver = {
 	.driver = {
 		.name = "usb-ohci",
 		.owner	= THIS_MODULE,
 	},
-	.probe = usb_hcd_pnx4008_probe,
-	.remove = usb_hcd_pnx4008_remove,
+	.probe = usb_hcd_nxp_probe,
+	.remove = usb_hcd_nxp_remove,
 };
 


From stigge at antcom.de  Sat Mar 10 14:36:05 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sat, 10 Mar 2012 20:36:05 +0100
Subject: [PATCH v5 2/3] USB: ohci-nxp: Rename symbols from pnx4008 to nxp
In-Reply-To: <1331408166-11607-1-git-send-email-stigge@antcom.de>
References: <1331408166-11607-1-git-send-email-stigge@antcom.de>
Message-ID: <1331408166-11607-3-git-send-email-stigge@antcom.de>

Since this driver is compatible with several NXP devices, the driver was renamed
accordingly. This patch also changes the respective symbol names.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 Documentation/i2c/instantiating-devices |    6 +--
 drivers/usb/host/ohci-hcd.c             |    2 -
 drivers/usb/host/ohci-nxp.c             |   55 ++++++++++++++++----------------
 3 files changed, 33 insertions(+), 30 deletions(-)

--- linux-2.6.orig/Documentation/i2c/instantiating-devices
+++ linux-2.6/Documentation/i2c/instantiating-devices
@@ -87,11 +87,11 @@ it may have different addresses from one
 changing its design without notice). In this case, you can call
 i2c_new_probed_device() instead of i2c_new_device().
 
-Example (from the pnx4008 OHCI driver):
+Example (from the nxp OHCI driver):
 
 static const unsigned short normal_i2c[] = { 0x2c, 0x2d, I2C_CLIENT_END };
 
-static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
+static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
 	(...)
 	struct i2c_adapter *i2c_adap;
@@ -100,7 +100,7 @@ static int __devinit usb_hcd_pnx4008_pro
 	(...)
 	i2c_adap = i2c_get_adapter(2);
 	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
-	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
+	strlcpy(i2c_info.type, "isp1301_nxp", I2C_NAME_SIZE);
 	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
 						   normal_i2c, NULL);
 	i2c_put_adapter(i2c_adap);
--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1052,7 +1052,7 @@ MODULE_LICENSE ("GPL");
 
 #ifdef CONFIG_ARCH_PNX4008
 #include "ohci-nxp.c"
-#define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
+#define PLATFORM_DRIVER		usb_hcd_nxp_driver
 #endif
 
 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
--- linux-2.6.orig/drivers/usb/host/ohci-nxp.c
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -1,7 +1,10 @@
 /*
- * drivers/usb/host/ohci-pnx4008.c
+ * drivers/usb/host/ohci-nxp.c
  *
- * driver for Philips PNX4008 USB Host
+ * driver for NXP USB Host devices
+ *
+ * Currently supported OHCI host devices:
+ * - Philips PNX4008
  *
  * Authors: Dmitry Chigirev <source at mvista.com>
  *	    Vitaly Wool <vitalywool at gmail.com>
@@ -121,13 +124,13 @@ static int isp1301_remove(struct i2c_cli
 }
 
 static const struct i2c_device_id isp1301_id[] = {
-	{ "isp1301_pnx", 0 },
+	{ "isp1301_nxp", 0 },
 	{ }
 };
 
 static struct i2c_driver isp1301_driver = {
 	.driver = {
-		.name = "isp1301_pnx",
+		.name = "isp1301_nxp",
 	},
 	.probe = isp1301_probe,
 	.remove = isp1301_remove,
@@ -180,14 +183,14 @@ static inline void isp1301_vbus_off(void
 		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
 }
 
-static void pnx4008_start_hc(void)
+static void nxp_start_hc(void)
 {
 	unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
 	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
 	isp1301_vbus_on();
 }
 
-static void pnx4008_stop_hc(void)
+static void nxp_stop_hc(void)
 {
 	unsigned long tmp;
 	isp1301_vbus_off();
@@ -195,7 +198,7 @@ static void pnx4008_stop_hc(void)
 	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
 }
 
-static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd)
+static int __devinit ohci_nxp_start(struct usb_hcd *hcd)
 {
 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
 	int ret;
@@ -211,9 +214,9 @@ static int __devinit ohci_pnx4008_start(
 	return 0;
 }
 
-static const struct hc_driver ohci_pnx4008_hc_driver = {
+static const struct hc_driver ohci_nxp_hc_driver = {
 	.description = hcd_name,
-	.product_desc =		"pnx4008 OHCI",
+	.product_desc =		"nxp OHCI",
 
 	/*
 	 * generic hardware linkage
@@ -225,7 +228,7 @@ static const struct hc_driver ohci_pnx40
 	/*
 	 * basic lifecycle operations
 	 */
-	.start = ohci_pnx4008_start,
+	.start = ohci_nxp_start,
 	.stop = ohci_stop,
 	.shutdown = ohci_shutdown,
 
@@ -255,7 +258,7 @@ static const struct hc_driver ohci_pnx40
 
 #define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON)
 
-static void pnx4008_set_usb_bits(void)
+static void nxp_set_usb_bits(void)
 {
 	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
 	start_int_ack(SE_USB_OTG_ATX_INT_N);
@@ -282,7 +285,7 @@ static void pnx4008_set_usb_bits(void)
 	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
 }
 
-static void pnx4008_unset_usb_bits(void)
+static void nxp_unset_usb_bits(void)
 {
 	start_int_mask(SE_USB_OTG_ATX_INT_N);
 	start_int_mask(SE_USB_OTG_TIMER_INT);
@@ -292,17 +295,17 @@ static void pnx4008_unset_usb_bits(void)
 	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
 }
 
-static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
+static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd = 0;
 	struct ohci_hcd *ohci;
-	const struct hc_driver *driver = &ohci_pnx4008_hc_driver;
+	const struct hc_driver *driver = &ohci_nxp_hc_driver;
 	struct i2c_adapter *i2c_adap;
 	struct i2c_board_info i2c_info;
 
 	int ret = 0, irq;
 
-	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (pnx4008)\n", hcd_name);
+	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (nxp)\n", hcd_name);
 	if (usb_disabled()) {
 		err("USB is disabled");
 		ret = -ENODEV;
@@ -327,7 +330,7 @@ static int __devinit usb_hcd_pnx4008_pro
 	}
 	i2c_adap = i2c_get_adapter(2);
 	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
-	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
+	strlcpy(i2c_info.type, "isp1301_nxp", I2C_NAME_SIZE);
 	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
 						   normal_i2c, NULL);
 	i2c_put_adapter(i2c_adap);
@@ -375,7 +378,7 @@ static int __devinit usb_hcd_pnx4008_pro
 	}
 
 	/* Set all USB bits in the Start Enable register */
-	pnx4008_set_usb_bits();
+	nxp_set_usb_bits();
 
 	hcd->rsrc_start = pdev->resource[0].start;
 	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
@@ -392,7 +395,7 @@ static int __devinit usb_hcd_pnx4008_pro
 		goto out4;
 	}
 
-	pnx4008_start_hc();
+	nxp_start_hc();
 	platform_set_drvdata(pdev, hcd);
 	ohci = hcd_to_ohci(hcd);
 	ohci_hcd_init(ohci);
@@ -402,9 +405,9 @@ static int __devinit usb_hcd_pnx4008_pro
 	if (ret == 0)
 		return ret;
 
-	pnx4008_stop_hc();
+	nxp_stop_hc();
 out4:
-	pnx4008_unset_usb_bits();
+	nxp_unset_usb_bits();
 	usb_put_hcd(hcd);
 out3:
 	clk_disable(usb_clk);
@@ -419,15 +422,15 @@ out:
 	return ret;
 }
 
-static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
+static int usb_hcd_nxp_remove(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd = platform_get_drvdata(pdev);
 
 	usb_remove_hcd(hcd);
-	pnx4008_stop_hc();
+	nxp_stop_hc();
 	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 	usb_put_hcd(hcd);
-	pnx4008_unset_usb_bits();
+	nxp_unset_usb_bits();
 	clk_disable(usb_clk);
 	clk_put(usb_clk);
 	i2c_unregister_device(isp1301_i2c_client);
@@ -442,12 +445,12 @@ static int usb_hcd_pnx4008_remove(struct
 /* work with hotplug and coldplug */
 MODULE_ALIAS("platform:usb-ohci");
 
-static struct platform_driver usb_hcd_pnx4008_driver = {
+static struct platform_driver usb_hcd_nxp_driver = {
 	.driver = {
 		.name = "usb-ohci",
 		.owner	= THIS_MODULE,
 	},
-	.probe = usb_hcd_pnx4008_probe,
-	.remove = usb_hcd_pnx4008_remove,
+	.probe = usb_hcd_nxp_probe,
+	.remove = usb_hcd_nxp_remove,
 };
 


From stigge at antcom.de  Sat Mar 10 14:36:03 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sat, 10 Mar 2012 20:36:03 +0100
Subject: [PATCH v5 0/3] USB: OHCI-HCD: Support for LPC32xx
Message-ID: <1331408166-11607-1-git-send-email-stigge@antcom.de>

This patch adds support for the LPC32xx to the ohci-pnx4008 driver.

As discussed with Greg-KH on the USB mailing list, the ohci-pnx4008 driver is
first renamed to reflect its multi-platform support. The second patch also
renames the respective pnx4008_* symbols accordingly. The third and final patch
adds the actual lpc32xx support.

Applies to v3.3-rc6

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Roland Stigge (3):
 USB: OHCI-HCD: Rename ohci-pnx4008 to ohci-nxp
 USB: ohci-nxp: Rename symbols from pnx4008 to nxp
 USB: ohci-nxp: Support for LPC32xx

 Documentation/i2c/instantiating-devices |    6 
 drivers/usb/host/ohci-hcd.c             |    6 
 drivers/usb/host/ohci-nxp.c             |  652 ++++++++++++++++++++++++++++----
 drivers/usb/host/ohci-pnx4008.c         |  453 ----------------------
 4 files changed, 596 insertions(+), 521 deletions(-)


From stigge at antcom.de  Sat Mar 10 20:46:14 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 11 Mar 2012 02:46:14 +0100
Subject: [PATCH v6 2/3] USB: ohci-nxp: Rename symbols from pnx4008 to nxp
In-Reply-To: <1331430375-31227-1-git-send-email-stigge@antcom.de>
References: <1331430375-31227-1-git-send-email-stigge@antcom.de>
Message-ID: <1331430375-31227-3-git-send-email-stigge@antcom.de>

Since this driver is compatible with several NXP devices, the driver was renamed
accordingly. This patch also changes the respective symbol names.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 Documentation/i2c/instantiating-devices |    6 +--
 drivers/usb/host/ohci-hcd.c             |    2 -
 drivers/usb/host/ohci-nxp.c             |   55 ++++++++++++++++----------------
 3 files changed, 33 insertions(+), 30 deletions(-)

--- linux-2.6.orig/Documentation/i2c/instantiating-devices
+++ linux-2.6/Documentation/i2c/instantiating-devices
@@ -87,11 +87,11 @@ it may have different addresses from one
 changing its design without notice). In this case, you can call
 i2c_new_probed_device() instead of i2c_new_device().
 
-Example (from the pnx4008 OHCI driver):
+Example (from the nxp OHCI driver):
 
 static const unsigned short normal_i2c[] = { 0x2c, 0x2d, I2C_CLIENT_END };
 
-static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
+static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
 	(...)
 	struct i2c_adapter *i2c_adap;
@@ -100,7 +100,7 @@ static int __devinit usb_hcd_pnx4008_pro
 	(...)
 	i2c_adap = i2c_get_adapter(2);
 	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
-	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
+	strlcpy(i2c_info.type, "isp1301_nxp", I2C_NAME_SIZE);
 	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
 						   normal_i2c, NULL);
 	i2c_put_adapter(i2c_adap);
--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1052,7 +1052,7 @@ MODULE_LICENSE ("GPL");
 
 #ifdef CONFIG_ARCH_PNX4008
 #include "ohci-nxp.c"
-#define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
+#define PLATFORM_DRIVER		usb_hcd_nxp_driver
 #endif
 
 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
--- linux-2.6.orig/drivers/usb/host/ohci-nxp.c
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -1,7 +1,10 @@
 /*
- * drivers/usb/host/ohci-pnx4008.c
+ * drivers/usb/host/ohci-nxp.c
  *
- * driver for Philips PNX4008 USB Host
+ * driver for NXP USB Host devices
+ *
+ * Currently supported OHCI host devices:
+ * - Philips PNX4008
  *
  * Authors: Dmitry Chigirev <source at mvista.com>
  *	    Vitaly Wool <vitalywool at gmail.com>
@@ -121,13 +124,13 @@ static int isp1301_remove(struct i2c_cli
 }
 
 static const struct i2c_device_id isp1301_id[] = {
-	{ "isp1301_pnx", 0 },
+	{ "isp1301_nxp", 0 },
 	{ }
 };
 
 static struct i2c_driver isp1301_driver = {
 	.driver = {
-		.name = "isp1301_pnx",
+		.name = "isp1301_nxp",
 	},
 	.probe = isp1301_probe,
 	.remove = isp1301_remove,
@@ -180,14 +183,14 @@ static inline void isp1301_vbus_off(void
 		  ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR);
 }
 
-static void pnx4008_start_hc(void)
+static void nxp_start_hc(void)
 {
 	unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN;
 	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
 	isp1301_vbus_on();
 }
 
-static void pnx4008_stop_hc(void)
+static void nxp_stop_hc(void)
 {
 	unsigned long tmp;
 	isp1301_vbus_off();
@@ -195,7 +198,7 @@ static void pnx4008_stop_hc(void)
 	__raw_writel(tmp, USB_OTG_STAT_CONTROL);
 }
 
-static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd)
+static int __devinit ohci_nxp_start(struct usb_hcd *hcd)
 {
 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
 	int ret;
@@ -211,9 +214,9 @@ static int __devinit ohci_pnx4008_start(
 	return 0;
 }
 
-static const struct hc_driver ohci_pnx4008_hc_driver = {
+static const struct hc_driver ohci_nxp_hc_driver = {
 	.description = hcd_name,
-	.product_desc =		"pnx4008 OHCI",
+	.product_desc =		"nxp OHCI",
 
 	/*
 	 * generic hardware linkage
@@ -225,7 +228,7 @@ static const struct hc_driver ohci_pnx40
 	/*
 	 * basic lifecycle operations
 	 */
-	.start = ohci_pnx4008_start,
+	.start = ohci_nxp_start,
 	.stop = ohci_stop,
 	.shutdown = ohci_shutdown,
 
@@ -255,7 +258,7 @@ static const struct hc_driver ohci_pnx40
 
 #define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON)
 
-static void pnx4008_set_usb_bits(void)
+static void nxp_set_usb_bits(void)
 {
 	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
 	start_int_ack(SE_USB_OTG_ATX_INT_N);
@@ -282,7 +285,7 @@ static void pnx4008_set_usb_bits(void)
 	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
 }
 
-static void pnx4008_unset_usb_bits(void)
+static void nxp_unset_usb_bits(void)
 {
 	start_int_mask(SE_USB_OTG_ATX_INT_N);
 	start_int_mask(SE_USB_OTG_TIMER_INT);
@@ -292,17 +295,17 @@ static void pnx4008_unset_usb_bits(void)
 	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
 }
 
-static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
+static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd = 0;
 	struct ohci_hcd *ohci;
-	const struct hc_driver *driver = &ohci_pnx4008_hc_driver;
+	const struct hc_driver *driver = &ohci_nxp_hc_driver;
 	struct i2c_adapter *i2c_adap;
 	struct i2c_board_info i2c_info;
 
 	int ret = 0, irq;
 
-	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (pnx4008)\n", hcd_name);
+	dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (nxp)\n", hcd_name);
 	if (usb_disabled()) {
 		err("USB is disabled");
 		ret = -ENODEV;
@@ -327,7 +330,7 @@ static int __devinit usb_hcd_pnx4008_pro
 	}
 	i2c_adap = i2c_get_adapter(2);
 	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
-	strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
+	strlcpy(i2c_info.type, "isp1301_nxp", I2C_NAME_SIZE);
 	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
 						   normal_i2c, NULL);
 	i2c_put_adapter(i2c_adap);
@@ -375,7 +378,7 @@ static int __devinit usb_hcd_pnx4008_pro
 	}
 
 	/* Set all USB bits in the Start Enable register */
-	pnx4008_set_usb_bits();
+	nxp_set_usb_bits();
 
 	hcd->rsrc_start = pdev->resource[0].start;
 	hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
@@ -392,7 +395,7 @@ static int __devinit usb_hcd_pnx4008_pro
 		goto out4;
 	}
 
-	pnx4008_start_hc();
+	nxp_start_hc();
 	platform_set_drvdata(pdev, hcd);
 	ohci = hcd_to_ohci(hcd);
 	ohci_hcd_init(ohci);
@@ -402,9 +405,9 @@ static int __devinit usb_hcd_pnx4008_pro
 	if (ret == 0)
 		return ret;
 
-	pnx4008_stop_hc();
+	nxp_stop_hc();
 out4:
-	pnx4008_unset_usb_bits();
+	nxp_unset_usb_bits();
 	usb_put_hcd(hcd);
 out3:
 	clk_disable(usb_clk);
@@ -419,15 +422,15 @@ out:
 	return ret;
 }
 
-static int usb_hcd_pnx4008_remove(struct platform_device *pdev)
+static int usb_hcd_nxp_remove(struct platform_device *pdev)
 {
 	struct usb_hcd *hcd = platform_get_drvdata(pdev);
 
 	usb_remove_hcd(hcd);
-	pnx4008_stop_hc();
+	nxp_stop_hc();
 	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 	usb_put_hcd(hcd);
-	pnx4008_unset_usb_bits();
+	nxp_unset_usb_bits();
 	clk_disable(usb_clk);
 	clk_put(usb_clk);
 	i2c_unregister_device(isp1301_i2c_client);
@@ -442,12 +445,12 @@ static int usb_hcd_pnx4008_remove(struct
 /* work with hotplug and coldplug */
 MODULE_ALIAS("platform:usb-ohci");
 
-static struct platform_driver usb_hcd_pnx4008_driver = {
+static struct platform_driver usb_hcd_nxp_driver = {
 	.driver = {
 		.name = "usb-ohci",
 		.owner	= THIS_MODULE,
 	},
-	.probe = usb_hcd_pnx4008_probe,
-	.remove = usb_hcd_pnx4008_remove,
+	.probe = usb_hcd_nxp_probe,
+	.remove = usb_hcd_nxp_remove,
 };
 


From stigge at antcom.de  Sat Mar 10 20:46:12 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 11 Mar 2012 02:46:12 +0100
Subject: [PATCH v6 0/3] USB: OHCI-HCD: Support for LPC32xx
Message-ID: <1331430375-31227-1-git-send-email-stigge@antcom.de>

This patch adds support for the LPC32xx to the ohci-pnx4008 driver.

As discussed with Greg-KH on the USB mailing list, the ohci-pnx4008 driver is
first renamed to reflect its multi-platform support. The second patch also
renames the respective pnx4008_* symbols accordingly. The third and final patch
adds the actual lpc32xx support.

Applies to v3.3-rc6

Since v5, i2c_read16() has been removed in favour of i2c_smbus_read_word_data()

Thanks to Wolfram Sang for reviewing!

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Roland Stigge (3):
 USB: OHCI-HCD: Rename ohci-pnx4008 to ohci-nxp
 USB: ohci-nxp: Rename symbols from pnx4008 to nxp
 USB: ohci-nxp: Support for LPC32xx

 Documentation/i2c/instantiating-devices |    6 
 drivers/usb/host/ohci-hcd.c             |    6 
 drivers/usb/host/ohci-nxp.c             |  652 ++++++++++++++++++++++++++++----
 drivers/usb/host/ohci-pnx4008.c         |  453 ----------------------
 4 files changed, 596 insertions(+), 521 deletions(-)


From broonie at opensource.wolfsonmicro.com  Sun Mar 11 08:58:00 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 11 Mar 2012 12:58:00 +0000
Subject: [PATCH 03/11] regulator: fixed: Support driver probe deferral
In-Reply-To: <1331218291-16119-4-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-4-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120311125759.GH3233@opensource.wolfsonmicro.com>

On Thu, Mar 08, 2012 at 03:51:23PM +0100, Thierry Reding wrote:
> If the specified GPIO is not found, return -EPROBE_DEFER. This will
> cause the driver to be probed again later when the required GPIO may
> have become available.

Might be worth pushing this into gpiolib?  It seems like wanting to
defer if a GPIO is not found will be the overwhelmingly common case
given that the GPIO numbers need to be explicitly specified.
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From stigge at antcom.de  Sat Mar 10 14:36:06 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sat, 10 Mar 2012 20:36:06 +0100
Subject: [PATCH v5 3/3] USB: ohci-nxp: Support for LPC32xx
In-Reply-To: <1331408166-11607-1-git-send-email-stigge@antcom.de>
References: <1331408166-11607-1-git-send-email-stigge@antcom.de>
Message-ID: <1331408166-11607-4-git-send-email-stigge@antcom.de>

This patch adds support for the LPC32xx to ohci-nxp

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 drivers/usb/host/ohci-hcd.c |    2 
 drivers/usb/host/ohci-nxp.c |  140 +++++++++++++++++++++++++++++++++-----------
 2 files changed, 107 insertions(+), 35 deletions(-)

--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1050,7 +1050,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_hcd_at91_driver
 #endif
 
-#ifdef CONFIG_ARCH_PNX4008
+#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX)
 #include "ohci-nxp.c"
 #define PLATFORM_DRIVER		usb_hcd_nxp_driver
 #endif
--- linux-2.6.orig/drivers/usb/host/ohci-nxp.c
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -5,6 +5,7 @@
  *
  * Currently supported OHCI host devices:
  * - Philips PNX4008
+ * - NXP LPC32xx
  *
  * Authors: Dmitry Chigirev <source at mvista.com>
  *	    Vitaly Wool <vitalywool at gmail.com>
@@ -25,20 +26,24 @@
 #include <linux/i2c.h>
 
 #include <mach/hardware.h>
+#include <asm/mach-types.h>
 #include <asm/io.h>
 
 #include <mach/platform.h>
 #include <mach/irqs.h>
 #include <asm/gpio.h>
 
-#define USB_CTRL	IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64)
+#define USB_CONFIG_BASE		0x31020000
+#define PWRMAN_BASE		0x40004000
+
+#define USB_CTRL		IO_ADDRESS(PWRMAN_BASE + 0x64)
 
 /* USB_CTRL bit defines */
 #define USB_SLAVE_HCLK_EN	(1 << 24)
 #define USB_HOST_NEED_CLK_EN	(1 << 21)
 
-#define USB_OTG_CLK_CTRL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF4)
-#define USB_OTG_CLK_STAT	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF8)
+#define USB_OTG_CLK_CTRL	IO_ADDRESS(USB_CONFIG_BASE + 0xFF4)
+#define USB_OTG_CLK_STAT	IO_ADDRESS(USB_CONFIG_BASE + 0xFF8)
 
 /* USB_OTG_CLK_CTRL bit defines */
 #define AHB_M_CLOCK_ON		(1 << 4)
@@ -47,7 +52,7 @@
 #define DEV_CLOCK_ON		(1 << 1)
 #define HOST_CLOCK_ON		(1 << 0)
 
-#define USB_OTG_STAT_CONTROL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x110)
+#define USB_OTG_STAT_CONTROL	IO_ADDRESS(USB_CONFIG_BASE + 0x110)
 
 /* USB_OTG_STAT_CONTROL bit defines */
 #define TRANSPARENT_I2C_EN	(1 << 7)
@@ -101,6 +106,15 @@
 #define ISP1301_I2C_INTERRUPT_RISING 0xE
 #define ISP1301_I2C_REG_CLEAR_ADDR 1
 
+/* On LPC32xx, those are undefined */
+#ifndef start_int_set_falling_edge
+#define start_int_set_falling_edge(irq)
+#define start_int_set_rising_edge(irq)
+#define start_int_ack(irq)
+#define start_int_mask(irq)
+#define start_int_umask(irq)
+#endif
+
 static struct i2c_driver isp1301_driver;
 static struct i2c_client *isp1301_i2c_client;
 
@@ -146,7 +160,17 @@ static void i2c_write(u8 buf, u8 subaddr
 	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
 }
 
-static void isp1301_configure(void)
+static u16 i2c_read16(u8 subaddr)
+{
+	u16 data;
+
+	i2c_master_send(isp1301_i2c_client, &subaddr, 1);
+	i2c_master_recv(isp1301_i2c_client, (u8 *) &data, 2);
+
+	return data;
+}
+
+static void isp1301_configure_pnx4008(void)
 {
 	/* PNX4008 only supports DAT_SE0 USB mode */
 	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
@@ -169,7 +193,51 @@ static void isp1301_configure(void)
 		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
 	i2c_write(0xFF,
 		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+}
+
+static void isp1301_configure_lpc32xx(void)
+{
+	/* LPC32XX only supports DAT_SE0 USB mode */
+	/* This sequence is important */
 
+	/* Disable transparent UART mode first */
+	i2c_write(MC1_UART_EN, (ISP1301_I2C_MODE_CONTROL_1 |
+		ISP1301_I2C_REG_CLEAR_ADDR));
+
+	i2c_write(~MC1_SPEED_REG, (ISP1301_I2C_MODE_CONTROL_1 |
+		ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1);
+	i2c_write(~0,
+		(ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write((MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL),
+		ISP1301_I2C_MODE_CONTROL_2);
+	i2c_write(~0, (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(MC1_DAT_SE0, ISP1301_I2C_MODE_CONTROL_1);
+	i2c_write((OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
+		ISP1301_I2C_OTG_CONTROL_1);
+	i2c_write((OTG1_DM_PULLUP | OTG1_DP_PULLUP),
+		(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write(~0,
+		 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(~0,
+		ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(~0,
+		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+
+	/* Enable usb_need_clk clock after transceiver is initialized */
+	__raw_writel((__raw_readl(USB_CTRL) | (1 << 22)), USB_CTRL);
+
+	printk(KERN_INFO "ISP1301 Vendor ID  : 0x%04x\n", i2c_read16(0x00));
+	printk(KERN_INFO "ISP1301 Product ID : 0x%04x\n", i2c_read16(0x02));
+	printk(KERN_INFO "ISP1301 Version ID : 0x%04x\n", i2c_read16(0x14));
+}
+
+static void isp1301_configure(void)
+{
+	if (machine_is_pnx4008())
+		isp1301_configure_pnx4008();
+	else
+		isp1301_configure_lpc32xx();
 }
 
 static inline void isp1301_vbus_on(void)
@@ -260,39 +328,43 @@ static const struct hc_driver ohci_nxp_h
 
 static void nxp_set_usb_bits(void)
 {
-	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-	start_int_ack(SE_USB_OTG_ATX_INT_N);
-	start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-	start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-	start_int_ack(SE_USB_OTG_TIMER_INT);
-	start_int_umask(SE_USB_OTG_TIMER_INT);
-
-	start_int_set_rising_edge(SE_USB_I2C_INT);
-	start_int_ack(SE_USB_I2C_INT);
-	start_int_umask(SE_USB_I2C_INT);
-
-	start_int_set_rising_edge(SE_USB_INT);
-	start_int_ack(SE_USB_INT);
-	start_int_umask(SE_USB_INT);
-
-	start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-	start_int_ack(SE_USB_NEED_CLK_INT);
-	start_int_umask(SE_USB_NEED_CLK_INT);
-
-	start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-	start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+	if (machine_is_pnx4008()) {
+		start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
+		start_int_ack(SE_USB_OTG_ATX_INT_N);
+		start_int_umask(SE_USB_OTG_ATX_INT_N);
+
+		start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
+		start_int_ack(SE_USB_OTG_TIMER_INT);
+		start_int_umask(SE_USB_OTG_TIMER_INT);
+
+		start_int_set_rising_edge(SE_USB_I2C_INT);
+		start_int_ack(SE_USB_I2C_INT);
+		start_int_umask(SE_USB_I2C_INT);
+
+		start_int_set_rising_edge(SE_USB_INT);
+		start_int_ack(SE_USB_INT);
+		start_int_umask(SE_USB_INT);
+
+		start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
+		start_int_ack(SE_USB_NEED_CLK_INT);
+		start_int_umask(SE_USB_NEED_CLK_INT);
+
+		start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
+		start_int_ack(SE_USB_AHB_NEED_CLK_INT);
+		start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+	}
 }
 
 static void nxp_unset_usb_bits(void)
 {
-	start_int_mask(SE_USB_OTG_ATX_INT_N);
-	start_int_mask(SE_USB_OTG_TIMER_INT);
-	start_int_mask(SE_USB_I2C_INT);
-	start_int_mask(SE_USB_INT);
-	start_int_mask(SE_USB_NEED_CLK_INT);
-	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+	if (machine_is_pnx4008()) {
+		start_int_mask(SE_USB_OTG_ATX_INT_N);
+		start_int_mask(SE_USB_OTG_TIMER_INT);
+		start_int_mask(SE_USB_I2C_INT);
+		start_int_mask(SE_USB_INT);
+		start_int_mask(SE_USB_NEED_CLK_INT);
+		start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+	}
 }
 
 static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)


From broonie at opensource.wolfsonmicro.com  Fri Mar  9 06:47:36 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 11:47:36 +0000
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators for
 v3.4
In-Reply-To: <20120309003217.GB12083@atomide.com>
References: <877gywjhht.fsf@ti.com> <20120308021843.GQ12083@atomide.com>
 <87399jc6cj.fsf@ti.com> <20120309003217.GB12083@atomide.com>
Message-ID: <20120309114731.GA3273@opensource.wolfsonmicro.com>

On Thu, Mar 08, 2012 at 04:32:18PM -0800, Tony Lindgren wrote:
> * Kevin Hilman <khilman at ti.com> [120308 09:37]:
> > Tony Lindgren <tony at atomide.com> writes:

> > Oh, that's because it depends on the regulator core changes that are in
> > Mark's regulator tree.  You need the for-next branch of :

> > git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git 

> > For this to compile correctly.

> > Sorry, I should've been more clear above about the build dependency.

> Hmm just checking.. Recently Mark replied to Peter:

...

> So can you guys please confirm that if is indeed an immutable
> commit to use as a base to merge in something?

Absolutely not, the for-next branch is rebuilt frequently especially
since it includes stuff sent to Linus and he complained about bugfixes
merged up into development code.  What is the actual dependency here?
The topic branches are more or less static, though some more than
others.

In general you should warn people if you've got a dependency on their
tree, it makes life easier.
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From broonie at opensource.wolfsonmicro.com  Sun Mar 11 07:38:48 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 11 Mar 2012 11:38:48 +0000
Subject: [PATCH 1/4] add a mc13783 codec driver
In-Reply-To: <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <20120311113848.GA3233@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 03:55:13PM +0100, Philippe R?tornaz wrote:

> From: Sascha Hauer <s.hauer at pengutronix.de>
> 
> sha 20111307:
> - rebased to 3.0-rc2
> - implement tdm slot settings
> - made it work with single ssi port
> - more register names instead of hardcoded numbers
> 
> philippe 20120803:
> - Add headset detection
> - add mic2 bias
> - enable headset output by default

If including stuff like this please include it after the ---.  Things
like notes about the odd arrangements with the SSI ports which will have
ongoing meaning are much more useful in the changelog.

Overall this looks fairly clean but very out of date, for example
there's a custom register cache impelementation and no DAPM.

> diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
> index 7122386..7b7b55e 100644
> --- a/drivers/mfd/mc13xxx-core.c
> +++ b/drivers/mfd/mc13xxx-core.c
> @@ -807,7 +807,8 @@ err_revision:
>  		mc13xxx_add_subdevice(mc13xxx, "%s-adc");
>  
>  	if (mc13xxx->flags & MC13XXX_USE_CODEC)
> -		mc13xxx_add_subdevice(mc13xxx, "%s-codec");
> +		mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
> +					pdata->codec, sizeof(*pdata->codec));
>  
>  	if (mc13xxx->flags & MC13XXX_USE_RTC)
>  		mc13xxx_add_subdevice(mc13xxx, "%s-rtc");

It's probably worth pushing the MFD updates separately to Samuel,
ideally they could go in during the next merge window even if the CODEC
driver doesn't make it.

>  	select SND_SOC_MAX98095 if I2C
>  	select SND_SOC_MAX9850 if I2C
>  	select SND_SOC_MAX9877 if I2C
> +	select SND_SOC_MC13783 if SPI
>  	select SND_SOC_PCM3008

This should depend on the MFD core, not the bus - it won't build without
the MFD core.

> +struct mc13783_priv {
> +	struct snd_soc_codec codec;
> +	struct mc13xxx *mc13xxx;
> +
> +	u32 reg_cache[42];

No custom register caches please (use the framework), and magic numbers
are generally bad.  Ideally the MFD would be converted over to regmap
which would give even more of a win.

> +	/* DAI clock master masks */
> +	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
> +	case SND_SOC_DAIFMT_CBM_CFM:
> +		val |= AUDIO_C_CLK_EN;
> +		break;
> +	case SND_SOC_DAIFMT_CBS_CFS:
> +		val |= AUDIO_CSM;
> +		break;
> +	case SND_SOC_DAIFMT_CBM_CFS:
> +	case SND_SOC_DAIFMT_CBS_CFM:
> +		return -EINVAL;
> +	}
> +
> +	val |= AUDIO_C_RESET;
> +
> +	mc13783_write(codec, reg, val);

This would be better using snd_soc_update_bits(), that way repeated
calls won't actually write to the hardware.  A similar issue applies
throughout, in some cases it looks like this will also fix locking
issues with doing read/modify/writes on partial register bits.

> +static int mc13783_set_fmt_sync(struct snd_soc_dai *dai, unsigned int fmt)
> +{
> +	int ret;
> +
> +	ret = mc13783_set_fmt(dai, fmt, MC13783_AUDIO_DAC);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * In synchronous mode force the voice codec into slave mode
> +	 * so that the clock / framesync from the stereo DAC is used
> +	 */
> +	fmt &= ~SND_SOC_DAIFMT_MASTER_MASK;
> +	fmt |= SND_SOC_DAIFMT_CBS_CFS;
> +	ret = mc13783_set_fmt(dai, fmt, MC13783_AUDIO_CODEC);

This looks like you want to be complaining about some invalid setups?

> +static void mc13783_startup(struct snd_soc_dai *dai, int reg)
> +{
> +	struct snd_soc_codec *codec = dai->codec;
> +	unsigned int val;
> +
> +	val = mc13783_read(codec, reg);
> +	val &= ~AUDIO_C_RESET;
> +	val |= AUDIO_C_EN;
> +	mc13783_write(codec, reg, val);
> +}

This looks like it should be either DAPM or set_bias_level...

> +static void mc13783_shutdown(struct snd_soc_dai *dai, int reg)
> +{
> +	struct snd_soc_codec *codec = dai->codec;
> +	unsigned int val;
> +
> +	val = mc13783_read(codec, reg);
> +	mc13783_write(codec, reg, val & ~AUDIO_C_EN);
> +}

...and I suspect there's issues with simultaneous playback and record.

> +static int mc13783_capure_cache;

Don't use global statics, use the private data.

> +static const char *mc13783_asp[] = {"Off", "Codec", "Right"};
> +static const char *mc13783_alsp[] = {"Off", "Codec", "Right"};
> +
> +static const char *mc13783_ahs[] = {"Codec", "Mixer"};
> +
> +static const char *mc13783_ahsout[] = {"Off", "Auto", "On"};
> +
> +static const char *mc13783_arxout[] = {"Codec", "Mixer"};

A lot of this looks like it should be in DAPM - it looks like routing
control.

> +static const char *mc13783_capture[] = {"off/off", "rxinl/rxinr",
> +	"mc1lin/mc1rin", "off/mc1rin", "off/mc2in", "mc1lin/mc2in",
> +	"off/txin", "mc1lin/txin", "mc1lin/rxinr", "mc1lin/off"};

This does too, looking at the code that implements the enum it appears
that the chip is more flexible than the what's being offered here, it
looks like there's a bunch of separate controls.

> +	SOC_SINGLE("MC1 Bias enable", 38, 0, 1, 0),
> +	SOC_SINGLE("MC2 Bias enable", 38, 1, 1, 0),

This should definitely be DAPM, users shouldn't have to manually control
the bias from userspace.

> +	priv = kzalloc(sizeof(struct mc13783_priv), GFP_KERNEL);
> +	if (priv == NULL)
> +		return -ENOMEM;

devm_kzalloc() (which will fix a memory leak on remove).

> +static __init int mc13783_init(void)
> +{
> +	return platform_driver_register(&mc13783_codec_driver);
> +}

module_platform_driver().
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From arnd at arndb.de  Sun Mar 11 17:35:10 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 11 Mar 2012 21:35:10 +0000
Subject: [PATCH 4/4] ARM: __io abuse cleanup
In-Reply-To: <1331500100-31351-5-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-5-git-send-email-robherring2@gmail.com>
Message-ID: <201203112135.10240.arnd@arndb.de>

On Sunday 11 March 2012, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> Several platforms incorrectly use __io() for casting to 'void __iomem *'.
> This converts all of those uses to use the common IOMEM macro.
> 
> Reported-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Anton Vorontsov <avorontsov at mvista.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Paul Mundt <lethal at linux-sh.org>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: linux-sh at vger.kernel.org

Acked-by: Arnd Bergmann <arnd at arndb.de>


From broonie at opensource.wolfsonmicro.com  Mon Mar 12 13:32:16 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 12 Mar 2012 17:32:16 +0000
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators for
 v3.4
In-Reply-To: <87399dzq5e.fsf@ti.com>
References: <877gywjhht.fsf@ti.com> <20120308021843.GQ12083@atomide.com>
 <87399jc6cj.fsf@ti.com> <20120309003217.GB12083@atomide.com>
 <20120309114731.GA3273@opensource.wolfsonmicro.com>
 <87zkbp4wtj.fsf@ti.com>
 <20120311204232.GC3171@opensource.wolfsonmicro.com>
 <87399dzq5e.fsf@ti.com>
Message-ID: <20120312173215.GL3110@opensource.wolfsonmicro.com>

On Mon, Mar 12, 2012 at 10:26:53AM -0700, Kevin Hilman wrote:
> Mark Brown <broonie at opensource.wolfsonmicro.com> writes:

> > The branch itself is essentially stable but I'm not enthused about the
> > idea of merging the whole thing via the OMAP tree.  

> Right, I wasn't suggesting we merge it via OMAP tree.   I was just
> looking for a stable point we could use as s dependency when merging
> everything together for the arm-soc tree.

Well, if you don't base the OMAP changes that depend on it off the
regulator changes then you'll break bisection as you'll have a bunch of
commits which won't have all their dependencies present on a branch
(since they're not present in the branch point and aren't otherwise
merged in), if bisect goes down that branch it'll be miserable.  That
seems bad and while I've not run into it with OMAP in particular it's
rather painful when it does happen.

It's much better if the branch has the required changes merged into it
prior to their being used.
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From broonie at opensource.wolfsonmicro.com  Fri Mar  9 07:23:59 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 12:23:59 +0000
Subject: linux-next: manual merge of the arm-soc tree with the regulator
 tree
In-Reply-To: <20120309181755.256b898808bd14726de0e977@canb.auug.org.au>
References: <20120309181755.256b898808bd14726de0e977@canb.auug.org.au>
Message-ID: <20120309122358.GM3273@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 06:17:55PM +1100, Stephen Rothwell wrote:

> Today's linux-next merge of the arm-soc tree got a conflict in
> drivers/regulator/Makefile between commit 8aa1ab9219e7 ("regulator: Sort
> Kconfig and Makefile entries") from the regulator tree and commit
> 8a16a701ad78 ("regulator: Remove bq24022 regulator driver") from the
> arm-soc tree.

Both fixups look good, thanks.
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From broonie at opensource.wolfsonmicro.com  Sun Mar 11 07:41:04 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 11 Mar 2012 11:41:04 +0000
Subject: [PATCH 3/4] mx31moboard: Add ssi configuration
In-Reply-To: <1331304916-4724-4-git-send-email-philippe.retornaz@epfl.ch>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-3-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-4-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <20120311114104.GC3233@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 03:55:15PM +0100, Philippe R?tornaz wrote:

> +	mxc_audmux_v2_configure_port(MX31_AUDMUX_PORT1_SSI0,
> +		MXC_AUDMUX_V2_PTCR_SYN |
> +		MXC_AUDMUX_V2_PTCR_TFSDIR |

This will need to be rebased off current code, the audmux has been moved
into sound/soc.
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From broonie at opensource.wolfsonmicro.com  Mon Mar 12 06:58:53 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 12 Mar 2012 10:58:53 +0000
Subject: [PATCH 1/4] add a mc13783 codec driver
In-Reply-To: <1496586.ebXd01ibP4@laptop>
References: <1331304916-4724-1-git-send-email-philippe.retornaz@epfl.ch>
 <1331304916-4724-2-git-send-email-philippe.retornaz@epfl.ch>
 <20120311113848.GA3233@opensource.wolfsonmicro.com>
 <1496586.ebXd01ibP4@laptop>
Message-ID: <20120312105852.GE3110@opensource.wolfsonmicro.com>

On Mon, Mar 12, 2012 at 09:11:08AM +0100, Philippe R?tornaz wrote:

> Thank you for this detailed review. I will redo the patch based on your 
> comments. I had a quick look at DAPM (dapm.txt in asoc documentation), but is 
> there any good "reference" implementation which is in the kernel where I could 
> have a look ? 

Pretty much all ASoC drivers use DAPM and there's really not much
variation in quality in terms of how they do so, it's mostly an either
it works or doesn't thing.  Just look for something maintained that you
can follow and/or which is fairly close to your hardware.
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From stigge at antcom.de  Sun Mar 11 06:53:38 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 11 Mar 2012 11:53:38 +0100
Subject: [PATCH v7 3/4] USB: ohci-nxp: Support for LPC32xx
In-Reply-To: <1331463219-23293-1-git-send-email-stigge@antcom.de>
References: <1331463219-23293-1-git-send-email-stigge@antcom.de>
Message-ID: <1331463219-23293-4-git-send-email-stigge@antcom.de>

This patch adds support for the LPC32xx to ohci-nxp

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 drivers/usb/host/ohci-hcd.c |    2 
 drivers/usb/host/ohci-nxp.c |  142 +++++++++++++++++++++++++++++++++-----------
 2 files changed, 109 insertions(+), 35 deletions(-)

--- linux-2.6.orig/drivers/usb/host/ohci-hcd.c
+++ linux-2.6/drivers/usb/host/ohci-hcd.c
@@ -1050,7 +1050,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER		ohci_hcd_at91_driver
 #endif
 
-#ifdef CONFIG_ARCH_PNX4008
+#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX)
 #include "ohci-nxp.c"
 #define PLATFORM_DRIVER		usb_hcd_nxp_driver
 #endif
--- linux-2.6.orig/drivers/usb/host/ohci-nxp.c
+++ linux-2.6/drivers/usb/host/ohci-nxp.c
@@ -5,6 +5,7 @@
  *
  * Currently supported OHCI host devices:
  * - Philips PNX4008
+ * - NXP LPC32xx
  *
  * Authors: Dmitry Chigirev <source at mvista.com>
  *	    Vitaly Wool <vitalywool at gmail.com>
@@ -25,20 +26,24 @@
 #include <linux/i2c.h>
 
 #include <mach/hardware.h>
+#include <asm/mach-types.h>
 #include <asm/io.h>
 
 #include <mach/platform.h>
 #include <mach/irqs.h>
 #include <asm/gpio.h>
 
-#define USB_CTRL	IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64)
+#define USB_CONFIG_BASE		0x31020000
+#define PWRMAN_BASE		0x40004000
+
+#define USB_CTRL		IO_ADDRESS(PWRMAN_BASE + 0x64)
 
 /* USB_CTRL bit defines */
 #define USB_SLAVE_HCLK_EN	(1 << 24)
 #define USB_HOST_NEED_CLK_EN	(1 << 21)
 
-#define USB_OTG_CLK_CTRL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF4)
-#define USB_OTG_CLK_STAT	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF8)
+#define USB_OTG_CLK_CTRL	IO_ADDRESS(USB_CONFIG_BASE + 0xFF4)
+#define USB_OTG_CLK_STAT	IO_ADDRESS(USB_CONFIG_BASE + 0xFF8)
 
 /* USB_OTG_CLK_CTRL bit defines */
 #define AHB_M_CLOCK_ON		(1 << 4)
@@ -47,7 +52,7 @@
 #define DEV_CLOCK_ON		(1 << 1)
 #define HOST_CLOCK_ON		(1 << 0)
 
-#define USB_OTG_STAT_CONTROL	IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x110)
+#define USB_OTG_STAT_CONTROL	IO_ADDRESS(USB_CONFIG_BASE + 0x110)
 
 /* USB_OTG_STAT_CONTROL bit defines */
 #define TRANSPARENT_I2C_EN	(1 << 7)
@@ -101,6 +106,15 @@
 #define ISP1301_I2C_INTERRUPT_RISING 0xE
 #define ISP1301_I2C_REG_CLEAR_ADDR 1
 
+/* On LPC32xx, those are undefined */
+#ifndef start_int_set_falling_edge
+#define start_int_set_falling_edge(irq)
+#define start_int_set_rising_edge(irq)
+#define start_int_ack(irq)
+#define start_int_mask(irq)
+#define start_int_umask(irq)
+#endif
+
 static struct i2c_driver isp1301_driver;
 static struct i2c_client *isp1301_i2c_client;
 
@@ -146,7 +160,7 @@ static void i2c_write(u8 buf, u8 subaddr
 	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
 }
 
-static void isp1301_configure(void)
+static void isp1301_configure_pnx4008(void)
 {
 	/* PNX4008 only supports DAT_SE0 USB mode */
 	/* PNX4008 R2A requires setting the MAX603 to output 3.6V */
@@ -169,7 +183,63 @@ static void isp1301_configure(void)
 		  ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
 	i2c_write(0xFF,
 		  ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+}
+
+static void isp1301_configure_lpc32xx(void)
+{
+	/* LPC32XX only supports DAT_SE0 USB mode */
+	/* This sequence is important */
 
+	/* Disable transparent UART mode first */
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		(ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
+		MC1_UART_EN);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		(ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
+		~MC1_SPEED_REG);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+				  ISP1301_I2C_MODE_CONTROL_1, MC1_SPEED_REG);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		  (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR),
+		  ~0);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_2,
+		(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_OTG_CONTROL_1,
+		(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
+		(OTG1_DM_PULLUP | OTG1_DP_PULLUP));
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
+		~0);
+	i2c_smbus_write_byte_data(isp1301_i2c_client,
+		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
+
+	/* Enable usb_need_clk clock after transceiver is initialized */
+	__raw_writel((__raw_readl(USB_CTRL) | (1 << 22)), USB_CTRL);
+
+	printk(KERN_INFO "ISP1301 Vendor ID  : 0x%04x\n",
+	      i2c_smbus_read_word_data(isp1301_i2c_client, 0x00));
+	printk(KERN_INFO "ISP1301 Product ID : 0x%04x\n",
+	      i2c_smbus_read_word_data(isp1301_i2c_client, 0x02));
+	printk(KERN_INFO "ISP1301 Version ID : 0x%04x\n",
+	      i2c_smbus_read_word_data(isp1301_i2c_client, 0x14));
+}
+
+static void isp1301_configure(void)
+{
+	if (machine_is_pnx4008())
+		isp1301_configure_pnx4008();
+	else
+		isp1301_configure_lpc32xx();
 }
 
 static inline void isp1301_vbus_on(void)
@@ -260,39 +330,43 @@ static const struct hc_driver ohci_nxp_h
 
 static void nxp_set_usb_bits(void)
 {
-	start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
-	start_int_ack(SE_USB_OTG_ATX_INT_N);
-	start_int_umask(SE_USB_OTG_ATX_INT_N);
-
-	start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
-	start_int_ack(SE_USB_OTG_TIMER_INT);
-	start_int_umask(SE_USB_OTG_TIMER_INT);
-
-	start_int_set_rising_edge(SE_USB_I2C_INT);
-	start_int_ack(SE_USB_I2C_INT);
-	start_int_umask(SE_USB_I2C_INT);
-
-	start_int_set_rising_edge(SE_USB_INT);
-	start_int_ack(SE_USB_INT);
-	start_int_umask(SE_USB_INT);
-
-	start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
-	start_int_ack(SE_USB_NEED_CLK_INT);
-	start_int_umask(SE_USB_NEED_CLK_INT);
-
-	start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
-	start_int_ack(SE_USB_AHB_NEED_CLK_INT);
-	start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+	if (machine_is_pnx4008()) {
+		start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
+		start_int_ack(SE_USB_OTG_ATX_INT_N);
+		start_int_umask(SE_USB_OTG_ATX_INT_N);
+
+		start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
+		start_int_ack(SE_USB_OTG_TIMER_INT);
+		start_int_umask(SE_USB_OTG_TIMER_INT);
+
+		start_int_set_rising_edge(SE_USB_I2C_INT);
+		start_int_ack(SE_USB_I2C_INT);
+		start_int_umask(SE_USB_I2C_INT);
+
+		start_int_set_rising_edge(SE_USB_INT);
+		start_int_ack(SE_USB_INT);
+		start_int_umask(SE_USB_INT);
+
+		start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
+		start_int_ack(SE_USB_NEED_CLK_INT);
+		start_int_umask(SE_USB_NEED_CLK_INT);
+
+		start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
+		start_int_ack(SE_USB_AHB_NEED_CLK_INT);
+		start_int_umask(SE_USB_AHB_NEED_CLK_INT);
+	}
 }
 
 static void nxp_unset_usb_bits(void)
 {
-	start_int_mask(SE_USB_OTG_ATX_INT_N);
-	start_int_mask(SE_USB_OTG_TIMER_INT);
-	start_int_mask(SE_USB_I2C_INT);
-	start_int_mask(SE_USB_INT);
-	start_int_mask(SE_USB_NEED_CLK_INT);
-	start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+	if (machine_is_pnx4008()) {
+		start_int_mask(SE_USB_OTG_ATX_INT_N);
+		start_int_mask(SE_USB_OTG_TIMER_INT);
+		start_int_mask(SE_USB_I2C_INT);
+		start_int_mask(SE_USB_INT);
+		start_int_mask(SE_USB_NEED_CLK_INT);
+		start_int_mask(SE_USB_AHB_NEED_CLK_INT);
+	}
 }
 
 static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)


From khilman at ti.com  Mon Mar 12 18:09:54 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 12 Mar 2012 15:09:54 -0700
Subject: [PATCH v3 13/13] gpio/omap: fix incorrect update to
 context.irqenable1
In-Reply-To: <1331118963-26364-14-git-send-email-tarun.kanti@ti.com> (Tarun
 Kanti DebBarma's message of "Wed, 7 Mar 2012 16:46:03 +0530")
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-14-git-send-email-tarun.kanti@ti.com>
Message-ID: <87haxtwjwt.fsf@ti.com>

Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:

> In _enable_gpio_irqbank() when bank->regs->set_irqenable is valid,
> gpio_mask can be directly set by writing to set_irqenable register
> without overwriting current value. 

Ouch.  Nice catch.

> In order to ensure the same is
> stored in context.irqenable1, we must read from regs->irqenable
> instead of overwriting it with gpio_mask.
> The overwriting makes sense only in the second case where irqenable
> is explicitly read and updated with new gpio_mask before writing it
> back. However, for consistency reading regs->irqenable into the
> bank->context.irqenable1 takes care of both the scenarios.

...takes care of both scenarios, but adds and extra duplicate read for
the second.

Instead, how about just move the context update into each side of the
if/else?  untested patch below to show what I mean.

Kevin


diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 752ae9b..f8b7099 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -442,6 +442,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 	if (bank->regs->set_irqenable) {
 		reg += bank->regs->set_irqenable;
 		l = gpio_mask;
+		bank->context.irqenable1 |= gpio_mask;
 	} else {
 		reg += bank->regs->irqenable;
 		l = __raw_readl(reg);
@@ -449,10 +450,10 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 			l &= ~gpio_mask;
 		else
 			l |= gpio_mask;
+		bank->context.irqenable1 = l;
 	}
 
 	__raw_writel(l, reg);
-	bank->context.irqenable1 = l;
 }
 
 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
@@ -463,6 +464,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 	if (bank->regs->clr_irqenable) {
 		reg += bank->regs->clr_irqenable;
 		l = gpio_mask;
+		bank->context.irqenable1 &= ~gpio_mask;
 	} else {
 		reg += bank->regs->irqenable;
 		l = __raw_readl(reg);
@@ -470,10 +472,10 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 			l |= gpio_mask;
 		else
 			l &= ~gpio_mask;
+		bank->context.irqenable1 = l;
 	}
 
 	__raw_writel(l, reg);
-	bank->context.irqenable1 = l;
 }
 
 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)



From linux at arm.linux.org.uk  Mon Mar 12 18:12:31 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 12 Mar 2012 22:12:31 +0000
Subject: Regression in 3.2.9 for omap-serial (at least)
In-Reply-To: <CAGGh5h0sC1mYFpDj973Xgbh7CQ3eGZEYVTy8qZwbsPBA_z4MRQ@mail.gmail.com>
References: <lyk42vxsz2.fsf@ensc-virt.intern.sigma-chemnitz.de>
 <alpine.LFD.2.02.1203081246130.2742@ionos>
 <CAGGh5h3-1XhMO1-jiBdUJYgh4unRcPonvp=zcXLKMJBfS+qpuQ@mail.gmail.com>
 <alpine.LFD.2.02.1203082024450.2742@ionos>
 <CAGGh5h0sC1mYFpDj973Xgbh7CQ3eGZEYVTy8qZwbsPBA_z4MRQ@mail.gmail.com>
Message-ID: <20120312221231.GB10830@n2100.arm.linux.org.uk>

On Fri, Mar 09, 2012 at 08:34:44AM +0100, jean-philippe francois wrote:
> Le 8 mars 2012 20:26, Thomas Gleixner <tglx at linutronix.de> a ?crit :
> > It's in Linus tree.
> >
> > http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=52abb700e16a9aa4cbc03f3d7f80206cbbc80680
> 
> Thank you !
> In fact I don't know how to use this interface to search by commit number.
> Do you know if it is possible ?

There is no direct way to do it.

You can replace <commit-id> below with either the long commit id, or an
abbreviated commit id:

http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=<commit-id>

So, for commit id 52abb70,

http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=52abb70

will work.


From khilman at ti.com  Mon Mar 12 18:17:04 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 12 Mar 2012 15:17:04 -0700
Subject: [PATCH v3 00/13] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <CAC83ZvJDfDBcRU1isYaxRe-fWN8F2+QW6W5EeWWuTRcFBGpYNg@mail.gmail.com>
 (Tarun Kanti DebBarma's message of "Tue, 13 Mar 2012 01:57:03 +0530")
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <878vj5y7iv.fsf@ti.com>
 <CAC83Zv+8AjCHBOJbtvSQS-URvCE5Xm9oPk9_X7h4Kz7FZ_7Otw@mail.gmail.com>
 <CAC83ZvJKS34Py6vVtk_Si9q3A-9CVN6v4ixNM+HJ37AATcGNPA@mail.gmail.com>
 <CAC83ZvJDfDBcRU1isYaxRe-fWN8F2+QW6W5EeWWuTRcFBGpYNg@mail.gmail.com>
Message-ID: <87boo1wjkv.fsf@ti.com>

"DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:

[...]

>>> Oops... I am sorry.
>>> I was in the process of updating the branch with latest comments after
>>> base-lining on Grant's:
>>> git://git.secretlab.ca/git/linux-2.6.git
>>> Branch: gpio/next
>>> Because this has all the gpio changes including Benoit's latest gpio
>>> devicetree changes.
>>> Should I go ahead?
>> Anyways, for the time being I am updating on top of your changes as before.
>> You should be able to see the branch shortly.
> Please note that the branch has your following patch:
> gpio/omap: fix wakeups on level-triggered GPIOs

After addressing my comments on the series, please go ahead and rebase
on Grant's gpio/next branch.

Thanks,

Kevin


From khilman at ti.com  Mon Mar 12 18:28:42 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 12 Mar 2012 15:28:42 -0700
Subject: [PATCH v3 00/13] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <CAC83ZvJDfDBcRU1isYaxRe-fWN8F2+QW6W5EeWWuTRcFBGpYNg@mail.gmail.com>
 (Tarun Kanti DebBarma's message of "Tue, 13 Mar 2012 01:57:03 +0530")
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <878vj5y7iv.fsf@ti.com>
 <CAC83Zv+8AjCHBOJbtvSQS-URvCE5Xm9oPk9_X7h4Kz7FZ_7Otw@mail.gmail.com>
 <CAC83ZvJKS34Py6vVtk_Si9q3A-9CVN6v4ixNM+HJ37AATcGNPA@mail.gmail.com>
 <CAC83ZvJDfDBcRU1isYaxRe-fWN8F2+QW6W5EeWWuTRcFBGpYNg@mail.gmail.com>
Message-ID: <87vcm9v4h1.fsf@ti.com>

"DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:

[...]

>>> Oops... I am sorry.
>>> I was in the process of updating the branch with latest comments after
>>> base-lining on Grant's:
>>> git://git.secretlab.ca/git/linux-2.6.git
>>> Branch: gpio/next
>>> Because this has all the gpio changes including Benoit's latest gpio
>>> devicetree changes.
>>> Should I go ahead?
>> Anyways, for the time being I am updating on top of your changes as before.
>> You should be able to see the branch shortly.
> Please note that the branch has your following patch:
> gpio/omap: fix wakeups on level-triggered GPIOs

Please be sure to Cc the GPIO maintainer (added now.)

Grant can we consider your gpio/next a stable baseline for further
GPIO fixes?

If so, Tarun, please base your branch there.  Otherwise, continue to use
my for_3.4/gpio/runtime-pm-cleanup, but please test it by merging with
the gpio/next branch.

Thanks,

Kevin


From paul at pwsan.com  Mon Mar 12 18:42:55 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 16:42:55 -0600
Subject: [PATCH 3/5] ARM: OMAP2+: GPMC: resolve type-conversion warning from
 sparse
In-Reply-To: <20120312224006.4103.29464.stgit@dusk>
References: <20120312224006.4103.29464.stgit@dusk>
Message-ID: <20120312224253.4103.35418.stgit@dusk>

arch/arm/mach-omap2/gpmc.c passes a return value from ioremap() as the
fifth argument to request_irq() without casting it.  This causes
sparse to generate the following warning:

arch/arm/mach-omap2/gpmc.c:759:63: warning: incorrect type in argument 5 (different address spaces)
arch/arm/mach-omap2/gpmc.c:759:63:    expected void *dev
arch/arm/mach-omap2/gpmc.c:759:63:    got void [noderef] <asn:2>*static [toplevel] [assigned] gpmc_base

It turns out that it's not necessary to pass this.  gpmc_base is a
file-scoped static variable, the ISR is located in the same file ... and
the ISR doesn't even touch the passed-in variable.  So, just replace it with
NULL in request_irq().

Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/gpmc.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index dfffbbf..aae584c 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -755,8 +755,7 @@ static int __init gpmc_init(void)
 		irq++;
 	}
 
-	ret = request_irq(gpmc_irq,
-			gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
+	ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
 	if (ret)
 		pr_err("gpmc: irq-%d could not claim: err %d\n",
 						gpmc_irq, ret);




From paul at pwsan.com  Mon Mar 12 18:42:53 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 16:42:53 -0600
Subject: [PATCH 2/5] ARM: OMAP2+: add includes for missing prototypes
In-Reply-To: <20120312224006.4103.29464.stgit@dusk>
References: <20120312224006.4103.29464.stgit@dusk>
Message-ID: <20120312224252.4103.75837.stgit@dusk>

Several C files in arch/arm/mach-omap2 declare functions that are used
by other files, but don't include the header file where the prototype is
declared.  This results in the following warnings from sparse:

    arch/arm/mach-omap2/irq.c:114:5: warning: symbol 'omap_irq_pending' was not declared. Should it be static?
    arch/arm/mach-omap2/irq.c:186:13: warning: symbol 'omap2_init_irq' was not declared. Should it be static?
    arch/arm/mach-omap2/irq.c:191:13: warning: symbol 'omap3_init_irq' was not declared. Should it be static?
    arch/arm/mach-omap2/irq.c:196:13: warning: symbol 'ti81xx_init_irq' was not declared. Should it be static?
    arch/arm/mach-omap2/irq.c:233:39: warning: symbol 'omap2_intc_handle_irq' was not declared. Should it be static?
    arch/arm/mach-omap2/irq.c:242:6: warning: symbol 'omap_intc_save_context' was not declared. Should it be static?
    arch/arm/mach-omap2/irq.c:265:6: warning: symbol 'omap_intc_restore_context' was not declared. Should it be static?
    arch/arm/mach-omap2/irq.c:291:6: warning: symbol 'omap3_intc_suspend' was not declared. Should it be static?
    arch/arm/mach-omap2/irq.c:297:6: warning: symbol 'omap3_intc_prepare_idle' was not declared. Should it be static?
    arch/arm/mach-omap2/irq.c:306:6: warning: symbol 'omap3_intc_resume_idle' was not declared. Should it be static?
    arch/arm/mach-omap2/irq.c:312:39: warning: symbol 'omap3_intc_handle_irq' was not declared. Should it be static?
    arch/arm/mach-omap2/omap-secure.c:59:12: warning: symbol 'omap_secure_ram_reserve_memblock' was not declared. Should it be static?
    arch/arm/mach-omap2/board-zoom-display.c:133:13: warning: symbol 'zoom_display_init' was not declared. Should it be static?

Fix by including the appropriate header files.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Senthilvadivu Guruswamy <svadivu at ti.com>
---
 arch/arm/mach-omap2/board-zoom-display.c |    1 +
 arch/arm/mach-omap2/irq.c                |    1 +
 arch/arm/mach-omap2/omap-secure.c        |    1 +
 3 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index d4683ba..75ff74e 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -16,6 +16,7 @@
 #include <linux/spi/spi.h>
 #include <plat/mcspi.h>
 #include <video/omapdss.h>
+#include <mach/board-zoom.h>
 
 #define LCD_PANEL_RESET_GPIO_PROD	96
 #define LCD_PANEL_RESET_GPIO_PILOT	55
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 1fef061..8247c51 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -18,6 +18,7 @@
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
 
+#include "common.h"
 
 /* selected INTC register offsets */
 
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index d8f8ef4..d9ae4a5 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -18,6 +18,7 @@
 #include <asm/cacheflush.h>
 #include <asm/memblock.h>
 
+#include <plat/omap-secure.h>
 #include <mach/omap-secure.h>
 
 static phys_addr_t omap_secure_memblock_base;




From paul at pwsan.com  Mon Mar 12 18:42:51 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 16:42:51 -0600
Subject: [PATCH 0/5] ARM: OMAP2+: resolve some warnings from sparse, cppcheck
Message-ID: <20120312224006.4103.29464.stgit@dusk>

Hello

This series resolves all of the current sparse warnings and many of
the meaningful cppcheck warnings in arch/arm/mach-omap2.

This series is also available from git://git.pwsan.com/linux-2.6 in the
branch 'sparse_cppcheck_fixes_3.4'.


- Paul

---

sparse_cppcheck_fixes_3.4
   text	   data	    bss	    dec	    hex	filename
6588152	 692980	5594140	12875272	 c47608	vmlinux.omap2plus_defconfig.orig
6588028	 692956	5594140	12875124	 c47574	vmlinux.omap2plus_defconfig

Paul Walmsley (5):
      ARM: OMAP2+: declare file-local functions as static
      ARM: OMAP2+: add includes for missing prototypes
      ARM: OMAP2+: GPMC: resolve type-conversion warning from sparse
      ARM: OMAP2+: fix 'using plain integer as NULL pointer' sparse warnings
      ARM: OMAP2+: clean up some cppcheck warnings


 arch/arm/mach-omap2/board-am3517evm.c        |    6 +-----
 arch/arm/mach-omap2/board-omap3evm.c         |    8 ++++----
 arch/arm/mach-omap2/board-omap4panda.c       |    8 ++++----
 arch/arm/mach-omap2/board-rx51-peripherals.c |    4 ++--
 arch/arm/mach-omap2/board-zoom-display.c     |    1 +
 arch/arm/mach-omap2/devices.c                |    3 +--
 arch/arm/mach-omap2/gpio.c                   |    4 ++--
 arch/arm/mach-omap2/gpmc-onenand.c           |    3 +--
 arch/arm/mach-omap2/gpmc.c                   |    3 +--
 arch/arm/mach-omap2/hsmmc.c                  |    2 +-
 arch/arm/mach-omap2/hwspinlock.c             |    2 +-
 arch/arm/mach-omap2/irq.c                    |    3 ++-
 arch/arm/mach-omap2/mcbsp.c                  |    2 +-
 arch/arm/mach-omap2/mux.c                    |    2 +-
 arch/arm/mach-omap2/omap-secure.c            |    1 +
 arch/arm/mach-omap2/omap-wakeupgen.c         |    2 +-
 arch/arm/mach-omap2/pm24xx.c                 |    3 ---
 arch/arm/mach-omap2/pm34xx.c                 |    4 +---
 arch/arm/mach-omap2/prm_common.c             |    4 +++-
 arch/arm/mach-omap2/serial.c                 |    2 +-
 arch/arm/mach-omap2/usb-tusb6010.c           |    2 +-
 arch/arm/plat-omap/include/plat/dmtimer.h    |    4 ++--
 22 files changed, 33 insertions(+), 40 deletions(-)



From paul at pwsan.com  Mon Mar 12 18:42:57 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 16:42:57 -0600
Subject: [PATCH 4/5] ARM: OMAP2+: fix 'using plain integer as NULL pointer'
 sparse warnings
In-Reply-To: <20120312224006.4103.29464.stgit@dusk>
References: <20120312224006.4103.29464.stgit@dusk>
Message-ID: <20120312224255.4103.6182.stgit@dusk>

sparse warns when 0 is passed to a function expecting a pointer argument.
Resolve these warnings by replacing the 0 with NULL.

arch/arm/plat-omap/include/plat/dmtimer.h:319:34: warning: Using plain integer as NULL pointer
arch/arm/plat-omap/include/plat/dmtimer.h:324:35: warning: Using plain integer as NULL pointer
arch/arm/mach-omap2/irq.c:294:22: warning: Using plain integer as NULL pointer

Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/irq.c                 |    2 +-
 arch/arm/plat-omap/include/plat/dmtimer.h |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 8247c51..22d9f6b 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -292,7 +292,7 @@ void omap_intc_restore_context(void)
 void omap3_intc_suspend(void)
 {
 	/* A pending interrupt would prevent OMAP from entering suspend */
-	omap_ack_irq(0);
+	omap_ack_irq(NULL);
 }
 
 void omap3_intc_prepare_idle(void)
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 9418f00..230ff91 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -316,12 +316,12 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
 				OMAP_TIMER_V1_SYS_STAT_OFFSET;
 		timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
 		timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
-		timer->irq_dis = 0;
+		timer->irq_dis = NULL;
 		timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
 		timer->func_base = timer->io_base;
 	} else {
 		timer->revision = 2;
-		timer->sys_stat = 0;
+		timer->sys_stat = NULL;
 		timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
 		timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
 		timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;




From paul at pwsan.com  Mon Mar 12 18:42:52 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 16:42:52 -0600
Subject: [PATCH 1/5] ARM: OMAP2+: declare file-local functions as static
In-Reply-To: <20120312224006.4103.29464.stgit@dusk>
References: <20120312224006.4103.29464.stgit@dusk>
Message-ID: <20120312224251.4103.76124.stgit@dusk>

Several function declarations used only in the files in which they're
declared should include the static keyboard, but don't:

    arch/arm/mach-omap2/serial.c:248:6: warning: symbol 'cmdline_find_option' was not declared. Should it be static?
    arch/arm/mach-omap2/omap-wakeupgen.c:259:6: warning: symbol 'irq_sar_clear' was not declared. Should it be static?
    arch/arm/mach-omap2/board-rx51-peripherals.c:878:27: warning: symbol 'rx51_vibra_data' was not declared. Should it be static?
    arch/arm/mach-omap2/board-rx51-peripherals.c:882:27: warning: symbol 'rx51_audio_data' was not declared. Should it be static?
    arch/arm/mach-omap2/board-omap4panda.c:201:29: warning: symbol 'omap_panda_wlan_data' was not declared. Should it be static?
    arch/arm/mach-omap2/board-omap4panda.c:393:24: warning: symbol 'omap4_panda_dvi_device' was not declared. Should it be static?
    arch/arm/mach-omap2/board-omap4panda.c:403:12: warning: symbol 'omap4_panda_dvi_init' was not declared. Should it be static?
    arch/arm/mach-omap2/board-omap4panda.c:464:6: warning: symbol 'omap4_panda_display_init' was not declared. Should it be static?
    arch/arm/mach-omap2/hsmmc.c:434:6: warning: symbol 'omap_init_hsmmc' was not declared. Should it be static?
    arch/arm/mach-omap2/hwspinlock.c:31:12: warning: symbol 'hwspinlocks_init' was not declared. Should it be static?

Mark all of these as static.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Govindraj R <govindraj.raja at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: David Anders <x0132446 at ti.com>
Cc: Simon Que <sque at ti.com>
---
 arch/arm/mach-omap2/board-omap4panda.c       |    8 ++++----
 arch/arm/mach-omap2/board-rx51-peripherals.c |    4 ++--
 arch/arm/mach-omap2/hsmmc.c                  |    2 +-
 arch/arm/mach-omap2/hwspinlock.c             |    2 +-
 arch/arm/mach-omap2/omap-wakeupgen.c         |    2 +-
 arch/arm/mach-omap2/serial.c                 |    2 +-
 6 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 28fc271..6424eb5 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -198,7 +198,7 @@ static struct platform_device omap_vwlan_device = {
 	},
 };
 
-struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
+static struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
 	.irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
 	/* PANDA ref clock is 38.4 MHz */
 	.board_ref_clock = 2,
@@ -390,7 +390,7 @@ static struct panel_dvi_platform_data omap4_dvi_panel = {
 	.i2c_bus_num = 3,
 };
 
-struct omap_dss_device omap4_panda_dvi_device = {
+static struct omap_dss_device omap4_panda_dvi_device = {
 	.type			= OMAP_DISPLAY_TYPE_DPI,
 	.name			= "dvi",
 	.driver_name		= "dvi",
@@ -400,7 +400,7 @@ struct omap_dss_device omap4_panda_dvi_device = {
 	.channel		= OMAP_DSS_CHANNEL_LCD2,
 };
 
-int __init omap4_panda_dvi_init(void)
+static int __init omap4_panda_dvi_init(void)
 {
 	int r;
 
@@ -461,7 +461,7 @@ static struct omap_dss_board_info omap4_panda_dss_data = {
 	.default_device	= &omap4_panda_dvi_device,
 };
 
-void omap4_panda_display_init(void)
+static void omap4_panda_display_init(void)
 {
 	int r;
 
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index acb4e77..17674d9 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -875,11 +875,11 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
 	.resource_config = twl4030_rconfig,
 };
 
-struct twl4030_vibra_data rx51_vibra_data __initdata = {
+static struct twl4030_vibra_data rx51_vibra_data __initdata = {
 	.coexist	= 0,
 };
 
-struct twl4030_audio_data rx51_audio_data __initdata = {
+static struct twl4030_audio_data rx51_audio_data __initdata = {
 	.audio_mclk	= 26000000,
 	.vibra		= &rx51_vibra_data,
 };
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 19dd165..cd15a58 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -431,7 +431,7 @@ static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 static int omap_hsmmc_done;
 #define MAX_OMAP_MMC_HWMOD_NAME_LEN		16
 
-void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
+static void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
 {
 	struct omap_hwmod *oh;
 	struct platform_device *pdev;
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 454dfce..8763c85 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -28,7 +28,7 @@ static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = {
 	.base_id = 0,
 };
 
-int __init hwspinlocks_init(void)
+static int __init hwspinlocks_init(void)
 {
 	int retval = 0;
 	struct omap_hwmod *oh;
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index d3d8971..5dac606 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -256,7 +256,7 @@ static void irq_save_context(void)
 /*
  * Clear WakeupGen SAR backup status.
  */
-void irq_sar_clear(void)
+static void irq_sar_clear(void)
 {
 	u32 val;
 	val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index f590afc..f558cc1 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -245,7 +245,7 @@ static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
 static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
 #endif
 
-char *cmdline_find_option(char *str)
+static char *cmdline_find_option(char *str)
 {
 	extern char *saved_command_line;
 




From paul at pwsan.com  Mon Mar 12 18:43:04 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 16:43:04 -0600
Subject: [PATCH 5/5] ARM: OMAP2+: clean up some cppcheck warnings
In-Reply-To: <20120312224006.4103.29464.stgit@dusk>
References: <20120312224006.4103.29464.stgit@dusk>
Message-ID: <20120312224257.4103.11096.stgit@dusk>

Resolve some warnings identified by cppcheck in arch/arm/mach-omap2:

    [arch/arm/mach-omap2/usb-tusb6010.c:129]: (style) Checking if unsigned variable 'tmp' is less than zero.
    [arch/arm/mach-omap2/prm_common.c:241]: (error) Possible null pointer dereference: irq_setup - otherwise it is redundant to check if irq_setup is null at line 247
    [arch/arm/mach-omap2/pm34xx.c:790]: (style) Variable 'per_clkdm' is assigned a value that is never used
    [arch/arm/mach-omap2/pm34xx.c:790]: (style) Variable 'core_clkdm' is assigned a value that is never used
    [arch/arm/mach-omap2/pm24xx.c:185]: (style) Variable 'only_idle' is assigned a value that is never used
    [arch/arm/mach-omap2/mux.c:254]: (error) Possible null pointer dereference: mux
    [arch/arm/mach-omap2/mux.c:258]: (error) Possible null pointer dereference: mux
    [arch/arm/mach-omap2/mcbsp.c:133]: (warning) scanf without field width limits can crash with huge input data
    [arch/arm/mach-omap2/gpmc-onenand.c:178]: (style) Variable 'tick_ns' is assigned a value that is never used
    [arch/arm/mach-omap2/gpio.c:43]: (warning) scanf without field width limits can crash with huge input data
    [arch/arm/mach-omap2/gpio.c:56]: (error) Possible null pointer dereference: pdata - otherwise it is redundant to check if pdata is null at line 57
    [arch/arm/mach-omap2/devices.c:45]: (style) Variable 'l' is assigned a value that is never used
    [arch/arm/mach-omap2/board-am3517evm.c:134]: (style) Variable 'regval' is assigned a value that is never used

Some of them are pretty good catches, such the gpio.c:56 and
usb-tusb6010.c:129.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Peter Ujfalusi <peter.ujfalusi at ti.com>
Cc: Jarkko Nikula <jarkko.nikula at bitmer.com>
Cc: Charulatha Varadarajan <charu at ti.com>
---
 arch/arm/mach-omap2/board-am3517evm.c |    6 +-----
 arch/arm/mach-omap2/board-omap3evm.c  |    8 ++++----
 arch/arm/mach-omap2/devices.c         |    3 +--
 arch/arm/mach-omap2/gpio.c            |    4 ++--
 arch/arm/mach-omap2/gpmc-onenand.c    |    3 +--
 arch/arm/mach-omap2/mcbsp.c           |    2 +-
 arch/arm/mach-omap2/mux.c             |    2 +-
 arch/arm/mach-omap2/pm24xx.c          |    3 ---
 arch/arm/mach-omap2/pm34xx.c          |    4 +---
 arch/arm/mach-omap2/prm_common.c      |    4 +++-
 arch/arm/mach-omap2/usb-tusb6010.c    |    2 +-
 11 files changed, 16 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 4b1cfe3..24b1f9a 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -150,13 +150,9 @@ static void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
 	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 	regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
 	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
-	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-
-	return ;
+	omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 }
 
-
-
 #define LCD_PANEL_PWR		176
 #define LCD_PANEL_BKLIGHT_PWR	182
 #define LCD_PANEL_PWM		181
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c877236..becf41d 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -634,12 +634,12 @@ static void __init omap3_evm_wl12xx_init(void)
 
 static void __init omap3_evm_init(void)
 {
+	static struct omap_board_mux *obm;
+
 	omap3_evm_get_revision();
 
-	if (cpu_is_omap3630())
-		omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
-	else
-		omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
+	obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
+	omap3_mux_init(obm, OMAP_PACKAGE_CBB);
 
 	omap_board_config = omap3_evm_config;
 	omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 283d11e..b52cd16 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -42,7 +42,6 @@
 
 static int __init omap3_l3_init(void)
 {
-	int l;
 	struct omap_hwmod *oh;
 	struct platform_device *pdev;
 	char oh_name[L3_MODULES_MAX_LEN];
@@ -54,7 +53,7 @@ static int __init omap3_l3_init(void)
 	if (!(cpu_is_omap34xx()))
 		return -ENODEV;
 
-	l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
+	snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
 
 	oh = omap_hwmod_lookup(oh_name);
 
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 8cbfbc2..f64fcb2 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -40,7 +40,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 	 * not change. If changed, make corresponding change here
 	 * or make use of static variable mechanism to handle this.
 	 */
-	sscanf(oh->name, "gpio%d", &id);
+	sscanf(oh->name, "gpio%1d", &id);
 
 	pdata = kzalloc(sizeof(struct omap_gpio_platform_data), GFP_KERNEL);
 	if (!pdata) {
@@ -54,7 +54,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 	pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
 
 	pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
-	if (!pdata) {
+	if (!pdata->regs) {
 		pr_err("gpio%d: Memory allocation failed\n", id);
 		return -ENOMEM;
 	}
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 5cdce10..6ab726f 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -175,7 +175,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 	const int t_wpl  = 40;
 	const int t_wph  = 30;
 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
-	int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
+	int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
 	int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
 	int err, ticks_cez;
 	int cs = cfg->cs, freq = *freq_ptr;
@@ -239,7 +239,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 		break;
 	}
 
-	tick_ns = gpmc_ticks_to_ns(1);
 	div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
 	gpmc_clk_ns = gpmc_ticks_to_ns(div);
 	if (gpmc_clk_ns < 15) /* >66Mhz */
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index fb4bcf8..efe59c7 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -130,7 +130,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 	struct omap_mcbsp_platform_data *pdata = NULL;
 	struct platform_device *pdev;
 
-	sscanf(oh->name, "mcbsp%d", &id);
+	sscanf(oh->name, "mcbsp%1d", &id);
 
 	pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
 	if (!pdata) {
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 611a0e3..552225a 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -248,7 +248,7 @@ int omap_mux_init_signal(const char *muxname, int val)
 	int mux_mode;
 
 	mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
-	if (mux_mode < 0)
+	if (mux_mode < 0 || !mux)
 		return mux_mode;
 
 	old_mode = omap_mux_read(partition, mux->reg_offset);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 23de98d..b3a4765 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -182,8 +182,6 @@ static int omap2_allow_mpu_retention(void)
 
 static void omap2_enter_mpu_retention(void)
 {
-	int only_idle = 0;
-
 	/* Putting MPU into the WFI state while a transfer is active
 	 * seems to cause the I2C block to timeout. Why? Good question. */
 	if (omap2_i2c_active())
@@ -206,7 +204,6 @@ static void omap2_enter_mpu_retention(void)
 
 		omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 						 OMAP2_PM_PWSTCTRL);
-		only_idle = 1;
 	}
 
 	omap2_sram_idle();
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc69875..0b65785 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -787,7 +787,7 @@ static void __init pm_errata_configure(void)
 static int __init omap3_pm_init(void)
 {
 	struct power_state *pwrst, *tmp;
-	struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
+	struct clockdomain *neon_clkdm, *mpu_clkdm;
 	int ret;
 
 	if (!cpu_is_omap34xx())
@@ -841,8 +841,6 @@ static int __init omap3_pm_init(void)
 
 	neon_clkdm = clkdm_lookup("neon_clkdm");
 	mpu_clkdm = clkdm_lookup("mpu_clkdm");
-	per_clkdm = clkdm_lookup("per_clkdm");
-	core_clkdm = clkdm_lookup("core_clkdm");
 
 #ifdef CONFIG_SUSPEND
 	suspend_set_ops(&omap_pm_ops);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 860118a..c7c7373 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -238,7 +238,7 @@ void omap_prcm_irq_complete(void)
  */
 int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 {
-	int nr_regs = irq_setup->nr_regs;
+	int nr_regs;
 	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
 	int offset, i;
 	struct irq_chip_generic *gc;
@@ -247,6 +247,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 	if (!irq_setup)
 		return -EINVAL;
 
+	nr_regs = irq_setup->nr_regs;
+
 	if (prcm_irq_setup) {
 		pr_err("PRCM: already initialized; won't reinitialize\n");
 		return -EINVAL;
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 994d8f5..db84a46 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -126,7 +126,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
 	tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
 	if (tmp > 4)
 		return -ERANGE;
-	if (tmp <= 0)
+	if (tmp == 0)
 		tmp = 1;
 	t.page_burst_access = (fclk_ps * tmp) / 1000;
 




From rmallon at gmail.com  Mon Mar 12 18:48:11 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:11 +1100
Subject: [PATCH v4 00/11] ep93xx: Move SoC private bits to core
Message-ID: <1331592502-9083-1-git-send-email-rmallon@gmail.com>

This patch series is an effort to move the ep93xx SoC specific code out
of drivers and include/mach into arch/arm/mach-ep93xx. This work
involves the following changes:

 - Create a new private header called soc.h to replace most of 
   mach/include/ep93xx-regs.h
 - Move the Maverick crunch code from arch/arm/kernel to mach-ep93xx
 - Convert the ep93xx backlight and watchdog drivers to properly
   ioremap memory.
 - Move all system controller access to the ep93xx core code

The only defines left in ep93xx-regs.h are for the APB UARTS which
are also needed in include/mach/uncompress.h and
include/mach/debug-macro.S.

Patch 2 has already been merged to the ASoC tree and patch 5 has
already been merged to the watchdog tree. Neither patch has been
modified since they were applied, and are included here for
completeness and to avoid build errors. 

All of the patches are against v3.3-rc7 and  now have reviewed-by
and/or acked-by tags except for patch 4 which has been changed
since the last version. Arnd, once I get an ack for the final patch
I can prepare a git branch for you to pull. I understand if this is
now too late for v3.4.

Changes since v3:
 - Removed the request_mem_region calls from both the backlight
   and framebuffer drivers since it causes problems due to the
   fact that the two drivers sharing parts of the same register
   space. This needs to be fixed properly in future.

Changes since v2:
 - Added Hartley's patch to convert watchdog driver to a
   proper platform driver
 - Fix the backlight driver to pass a proper memory
   resource, and ioremap, but not request it.

Changes since v1:
 - Moved syscon access functions to the bottom of soc.h
 - Don't include soc.h in crunch in the same patch as moving it
 - Removed unnecessary whitespace
 - Added commit message to gpio define move patch
 - Remove the arch_reset change since this is already done by
   the reset rework

H Hartley Sweeten (1):
  ep93xx: Convert the watchdog driver into a platform device.

Ryan Mallon (10):
  ep93xx: Move PHYS_BASE defines to local SoC header file
  ep93xx: Don't use system controller defines in audio drivers
  ep93xx: Move GPIO defines to gpio-ep93xx.h
  ep93xx: Use ioremap for backlight driver
  ep93xx: Move peripheral defines to local SoC header
  ep93xx: Configure GPIO ports in core code
  ep93xx: Make syscon access functions private to SoC
  ep93xx: Move crunch code to mach-ep93xx directory
  ep93xx: Move EP93XX_SYSCON defines to SoC private header
  ep93xx: Remove unnecessary includes of ep93xx-regs.h

 arch/arm/kernel/Makefile                        |    3 -
 arch/arm/kernel/crunch-bits.S                   |  305 -----------------------
 arch/arm/kernel/crunch.c                        |   88 -------
 arch/arm/mach-ep93xx/Makefile                   |    3 +
 arch/arm/mach-ep93xx/adssphere.c                |    1 +
 arch/arm/mach-ep93xx/clock.c                    |    1 +
 arch/arm/mach-ep93xx/core.c                     |   54 +++--
 arch/arm/mach-ep93xx/crunch-bits.S              |  305 +++++++++++++++++++++++
 arch/arm/mach-ep93xx/crunch.c                   |   90 +++++++
 arch/arm/mach-ep93xx/dma.c                      |    2 +
 arch/arm/mach-ep93xx/edb93xx.c                  |    1 +
 arch/arm/mach-ep93xx/gesbc9312.c                |    1 +
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |  191 +--------------
 arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h |   10 +
 arch/arm/mach-ep93xx/include/mach/hardware.h    |    1 -
 arch/arm/mach-ep93xx/include/mach/platform.h    |   16 +--
 arch/arm/mach-ep93xx/micro9.c                   |    1 +
 arch/arm/mach-ep93xx/simone.c                   |    2 +
 arch/arm/mach-ep93xx/snappercl15.c              |    2 +
 arch/arm/mach-ep93xx/soc.h                      |  213 ++++++++++++++++
 arch/arm/mach-ep93xx/ts72xx.c                   |    1 +
 arch/arm/mach-ep93xx/vision_ep9307.c            |    2 +
 drivers/gpio/gpio-ep93xx.c                      |    7 -
 drivers/video/backlight/ep93xx_bl.c             |   25 +-
 drivers/video/ep93xx-fb.c                       |   15 +-
 drivers/watchdog/ep93xx_wdt.c                   |   51 +++-
 sound/soc/ep93xx/edb93xx.c                      |    4 +-
 sound/soc/ep93xx/snappercl15.c                  |    4 +-
 28 files changed, 736 insertions(+), 663 deletions(-)
 delete mode 100644 arch/arm/kernel/crunch-bits.S
 delete mode 100644 arch/arm/kernel/crunch.c
 create mode 100644 arch/arm/mach-ep93xx/crunch-bits.S
 create mode 100644 arch/arm/mach-ep93xx/crunch.c
 create mode 100644 arch/arm/mach-ep93xx/soc.h



From rmallon at gmail.com  Mon Mar 12 18:48:12 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:12 +1100
Subject: [PATCH v4 01/11] ep93xx: Move PHYS_BASE defines to local SoC header
 file
Message-ID: <1331592502-9083-2-git-send-email-rmallon@gmail.com>

The PHYS_BASE defines in arch/arm/mach-ep93xx/include/mach-ep93xx-regs.h are
only used in the SoC code. Move the defines to a local header file.

Signed-off-by: Ryan Mallon <rmallon at gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>
---
 arch/arm/mach-ep93xx/adssphere.c                |    1 +
 arch/arm/mach-ep93xx/edb93xx.c                  |    1 +
 arch/arm/mach-ep93xx/gesbc9312.c                |    1 +
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |   34 ---------------
 arch/arm/mach-ep93xx/micro9.c                   |    1 +
 arch/arm/mach-ep93xx/simone.c                   |    2 +
 arch/arm/mach-ep93xx/snappercl15.c              |    2 +
 arch/arm/mach-ep93xx/soc.h                      |   50 +++++++++++++++++++++++
 arch/arm/mach-ep93xx/ts72xx.c                   |    1 +
 arch/arm/mach-ep93xx/vision_ep9307.c            |    2 +
 10 files changed, 61 insertions(+), 34 deletions(-)
 create mode 100644 arch/arm/mach-ep93xx/soc.h

diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 681e939..2d45947 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -20,6 +20,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static struct ep93xx_eth_data __initdata adssphere_eth_data = {
 	.phy_id		= 1,
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index d115653..da9047d 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -43,6 +43,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static void __init edb93xx_register_flash(void)
 {
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index af46970..fcdffbe 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -20,6 +20,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
 	.phy_id		= 1,
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index c4a7b84..b029305 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -6,40 +6,6 @@
 #define __ASM_ARCH_EP93XX_REGS_H
 
 /*
- * EP93xx Physical Memory Map:
- *
- * The ASDO pin is sampled at system reset to select a synchronous or
- * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
- * the synchronous boot mode is selected.  When ASDO is "0" (i.e
- * pulled-down) the asynchronous boot mode is selected.
- *
- * In synchronous boot mode nSDCE3 is decoded starting at physical address
- * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
- * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
- * decoded at 0xf0000000.
- *
- * There is known errata for the EP93xx dealing with External Memory
- * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
- * Guidelines" for more information.  This document can be found at:
- *
- *	http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
- */
-
-#define EP93XX_CS0_PHYS_BASE_ASYNC	0x00000000	/* ASDO Pin = 0 */
-#define EP93XX_SDCE3_PHYS_BASE_SYNC	0x00000000	/* ASDO Pin = 1 */
-#define EP93XX_CS1_PHYS_BASE		0x10000000
-#define EP93XX_CS2_PHYS_BASE		0x20000000
-#define EP93XX_CS3_PHYS_BASE		0x30000000
-#define EP93XX_PCMCIA_PHYS_BASE		0x40000000
-#define EP93XX_CS6_PHYS_BASE		0x60000000
-#define EP93XX_CS7_PHYS_BASE		0x70000000
-#define EP93XX_SDCE0_PHYS_BASE		0xc0000000
-#define EP93XX_SDCE1_PHYS_BASE		0xd0000000
-#define EP93XX_SDCE2_PHYS_BASE		0xe0000000
-#define EP93XX_SDCE3_PHYS_BASE_ASYNC	0xf0000000	/* ASDO Pin = 0 */
-#define EP93XX_CS0_PHYS_BASE_SYNC	0xf0000000	/* ASDO Pin = 1 */
-
-/*
  * EP93xx linux memory map:
  *
  * virt		phys		size
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 7b98084..dc431c5 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -22,6 +22,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 /*************************************************************************
  * Micro9 NOR Flash
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index f4e553e..f40c298 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -29,6 +29,8 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
+
 static struct ep93xx_eth_data __initdata simone_eth_data = {
 	.phy_id		= 1,
 };
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index fd84633..0c00852 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -35,6 +35,8 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
+
 #define SNAPPERCL15_NAND_BASE	(EP93XX_CS7_PHYS_BASE + SZ_16M)
 
 #define SNAPPERCL15_NAND_WPN	(1 << 8)  /* Write protect (active low) */
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
new file mode 100644
index 0000000..74703e7
--- /dev/null
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-ep93xx/soc.h
+ *
+ * Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
+ * Copyright (C) 2012 Ryan Mallon <rmallon at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#ifndef _EP93XX_SOC_H
+#define _EP93XX_SOC_H
+
+/*
+ * EP93xx Physical Memory Map:
+ *
+ * The ASDO pin is sampled at system reset to select a synchronous or
+ * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
+ * the synchronous boot mode is selected.  When ASDO is "0" (i.e
+ * pulled-down) the asynchronous boot mode is selected.
+ *
+ * In synchronous boot mode nSDCE3 is decoded starting at physical address
+ * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
+ * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
+ * decoded at 0xf0000000.
+ *
+ * There is known errata for the EP93xx dealing with External Memory
+ * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
+ * Guidelines" for more information.  This document can be found at:
+ *
+ *	http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
+ */
+
+#define EP93XX_CS0_PHYS_BASE_ASYNC	0x00000000	/* ASDO Pin = 0 */
+#define EP93XX_SDCE3_PHYS_BASE_SYNC	0x00000000	/* ASDO Pin = 1 */
+#define EP93XX_CS1_PHYS_BASE		0x10000000
+#define EP93XX_CS2_PHYS_BASE		0x20000000
+#define EP93XX_CS3_PHYS_BASE		0x30000000
+#define EP93XX_PCMCIA_PHYS_BASE		0x40000000
+#define EP93XX_CS6_PHYS_BASE		0x60000000
+#define EP93XX_CS7_PHYS_BASE		0x70000000
+#define EP93XX_SDCE0_PHYS_BASE		0xc0000000
+#define EP93XX_SDCE1_PHYS_BASE		0xd0000000
+#define EP93XX_SDCE2_PHYS_BASE		0xe0000000
+#define EP93XX_SDCE3_PHYS_BASE_ASYNC	0xf0000000	/* ASDO Pin = 0 */
+#define EP93XX_CS0_PHYS_BASE_SYNC	0xf0000000	/* ASDO Pin = 1 */
+
+#endif /* _EP93XX_PHYS_BASE_H */
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 79f8ecf..5ea7909 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -28,6 +28,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static struct map_desc ts72xx_io_desc[] __initdata = {
 	{
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index d67d0b4..ba156eb 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -39,6 +39,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
+
 /*************************************************************************
  * Static I/O mappings for the FPGA
  *************************************************************************/
-- 
1.7.0.4



From rmallon at gmail.com  Mon Mar 12 18:48:13 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:13 +1100
Subject: [PATCH v4 02/11] ep93xx: Don't use system controller defines in audio
 drivers
Message-ID: <1331592502-9083-3-git-send-email-rmallon@gmail.com>

Both the Snapper CL15 and EDB93xx audio drivers set the same audio
configuration in ep93xx_i2s_acquire. Remove the arguments to
ep93xx_i2s_acquire so that the audio drivers no longer need the
EP93XX_SYSCON defines exported.

Signed-off-by: Ryan Mallon <rmallon at gmail.com>
Cc: Liam Girdwood <lrg at ti.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>
---
This patch has already been applied in Mark's tree. It is posted
for inclusion here because this series is against v3.3-rc7 and
will cause build failures without it. There have been no changes
to the patch since Mark applied it, so it should be okay to
merge into both his tree and the arm-soc tree.

 arch/arm/mach-ep93xx/core.c                  |   19 ++++---------------
 arch/arm/mach-ep93xx/include/mach/platform.h |    2 +-
 sound/soc/ep93xx/edb93xx.c                   |    4 +---
 sound/soc/ep93xx/snappercl15.c               |    4 +---
 4 files changed, 7 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 24203f9..b5c1dae 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -817,23 +817,12 @@ void __init ep93xx_register_i2s(void)
 #define EP93XX_I2SCLKDIV_MASK		(EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
 					 EP93XX_SYSCON_I2SCLKDIV_SPOL)
 
-int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config)
+int ep93xx_i2s_acquire(void)
 {
 	unsigned val;
 
-	/* Sanity check */
-	if (i2s_pins & ~EP93XX_SYSCON_DEVCFG_I2S_MASK)
-		return -EINVAL;
-	if (i2s_config & ~EP93XX_I2SCLKDIV_MASK)
-		return -EINVAL;
-
-	/* Must have only one of I2SONSSP/I2SONAC97 set */
-	if ((i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONSSP) ==
-	    (i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONAC97))
-		return -EINVAL;
-
-	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
-	ep93xx_devcfg_set_bits(i2s_pins);
+	ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
+			EP93XX_SYSCON_DEVCFG_I2S_MASK);
 
 	/*
 	 * This is potentially racy with the clock api for i2s_mclk, sclk and 
@@ -843,7 +832,7 @@ int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config)
 	 */
 	val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
 	val &= ~EP93XX_I2SCLKDIV_MASK;
-	val |= i2s_config;
+	val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
 	ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
 
 	return 0;
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index d4c9349..ad63d4b 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -59,7 +59,7 @@ void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
 int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
 void ep93xx_keypad_release_gpio(struct platform_device *pdev);
 void ep93xx_register_i2s(void);
-int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config);
+int ep93xx_i2s_acquire(void);
 void ep93xx_i2s_release(void);
 void ep93xx_register_ac97(void);
 
diff --git a/sound/soc/ep93xx/edb93xx.c b/sound/soc/ep93xx/edb93xx.c
index bae5cbb..e01cb02 100644
--- a/sound/soc/ep93xx/edb93xx.c
+++ b/sound/soc/ep93xx/edb93xx.c
@@ -85,9 +85,7 @@ static int __devinit edb93xx_probe(struct platform_device *pdev)
 	struct snd_soc_card *card = &snd_soc_edb93xx;
 	int ret;
 
-	ret = ep93xx_i2s_acquire(EP93XX_SYSCON_DEVCFG_I2SONAC97,
-				 EP93XX_SYSCON_I2SCLKDIV_ORIDE |
-				 EP93XX_SYSCON_I2SCLKDIV_SPOL);
+	ret = ep93xx_i2s_acquire();
 	if (ret)
 		return ret;
 
diff --git a/sound/soc/ep93xx/snappercl15.c b/sound/soc/ep93xx/snappercl15.c
index ccae34a..a193cea 100644
--- a/sound/soc/ep93xx/snappercl15.c
+++ b/sound/soc/ep93xx/snappercl15.c
@@ -103,9 +103,7 @@ static int __devinit snappercl15_probe(struct platform_device *pdev)
 	struct snd_soc_card *card = &snd_soc_snappercl15;
 	int ret;
 
-	ret = ep93xx_i2s_acquire(EP93XX_SYSCON_DEVCFG_I2SONAC97,
-				 EP93XX_SYSCON_I2SCLKDIV_ORIDE |
-				 EP93XX_SYSCON_I2SCLKDIV_SPOL);
+	ret = ep93xx_i2s_acquire();
 	if (ret)
 		return ret;
 
-- 
1.7.0.4



From rmallon at gmail.com  Mon Mar 12 18:48:14 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:14 +1100
Subject: [PATCH v4 03/11] ep93xx: Move GPIO defines to gpio-ep93xx.h
Message-ID: <1331592502-9083-4-git-send-email-rmallon@gmail.com>

Move the GPIO related defines out of ep93xx-regs.h and into
gpio-ep93xx.h where they belong.

Signed-off-by: Ryan Mallon <rmallon at gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>
---
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |    8 --------
 arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h |   10 ++++++++++
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index b029305..72b8687 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -64,14 +64,6 @@
 
 #define EP93XX_SECURITY_BASE		EP93XX_APB_IOMEM(0x00030000)
 
-#define EP93XX_GPIO_PHYS_BASE		EP93XX_APB_PHYS(0x00040000)
-#define EP93XX_GPIO_BASE		EP93XX_APB_IOMEM(0x00040000)
-#define EP93XX_GPIO_REG(x)		(EP93XX_GPIO_BASE + (x))
-#define EP93XX_GPIO_F_INT_STATUS	EP93XX_GPIO_REG(0x5c)
-#define EP93XX_GPIO_A_INT_STATUS	EP93XX_GPIO_REG(0xa0)
-#define EP93XX_GPIO_B_INT_STATUS	EP93XX_GPIO_REG(0xbc)
-#define EP93XX_GPIO_EEDRIVE		EP93XX_GPIO_REG(0xc8)
-
 #define EP93XX_AAC_PHYS_BASE		EP93XX_APB_PHYS(0x00080000)
 #define EP93XX_AAC_BASE			EP93XX_APB_IOMEM(0x00080000)
 
diff --git a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h b/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
index 8aff2ea..6d7c571 100644
--- a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
@@ -3,6 +3,16 @@
 #ifndef __GPIO_EP93XX_H
 #define __GPIO_EP93XX_H
 
+#include <mach/ep93xx-regs.h>
+
+#define EP93XX_GPIO_PHYS_BASE		EP93XX_APB_PHYS(0x00040000)
+#define EP93XX_GPIO_BASE		EP93XX_APB_IOMEM(0x00040000)
+#define EP93XX_GPIO_REG(x)		(EP93XX_GPIO_BASE + (x))
+#define EP93XX_GPIO_F_INT_STATUS	EP93XX_GPIO_REG(0x5c)
+#define EP93XX_GPIO_A_INT_STATUS	EP93XX_GPIO_REG(0xa0)
+#define EP93XX_GPIO_B_INT_STATUS	EP93XX_GPIO_REG(0xbc)
+#define EP93XX_GPIO_EEDRIVE		EP93XX_GPIO_REG(0xc8)
+
 /* GPIO port A.  */
 #define EP93XX_GPIO_LINE_A(x)		((x) + 0)
 #define EP93XX_GPIO_LINE_EGPIO0		EP93XX_GPIO_LINE_A(0)
-- 
1.7.0.4



From rmallon at gmail.com  Mon Mar 12 18:48:15 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:15 +1100
Subject: [PATCH v4 04/11] ep93xx: Use ioremap for backlight driver
Message-ID: <1331592502-9083-5-git-send-email-rmallon@gmail.com>

The ep93xx backlight driver uses a single register within the
framebuffer's register space. Currently the backlight driver uses a
static IO mapping for the register since the memory cannot be
requested by both drivers.

Convert the static mapping to use ioremap so that we can remove the
dependency on mach/hardware.h. To do so, we need remove the
request_mem_region from both the backlight and framebuffer drivers,
since whichever driver is loaded second will fail with -EBUSY
otherwise.

A proper fix is still required, and a FIXME comment has been added to
both drivers.

Signed-off-by: Ryan Mallon <rmallon at gmail.com>
Suggested-by: Arnd Bergmann <arnd at arndb.de>
Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
Cc: Mika Westerberg <mika.westerberg at iki.fi>
Cc: Richard Purdie <rpurdie at rpsys.net>
Cc: Florian Tobias Schandinat <FlorianSchandinat at gmx.de>
---
 arch/arm/mach-ep93xx/core.c         |   10 ++++++++++
 drivers/video/backlight/ep93xx_bl.c |   25 ++++++++++++++-----------
 drivers/video/ep93xx-fb.c           |   15 +++++++++------
 3 files changed, 33 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index b5c1dae..c73e299 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -682,9 +682,19 @@ static struct platform_device ep93xx_fb_device = {
 	.resource		= ep93xx_fb_resource,
 };
 
+/* The backlight use a single register in the framebuffer's register space */
+#define EP93XX_RASTER_REG_BRIGHTNESS 0x20
+
+static struct resource ep93xx_bl_resources[] = {
+	DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
+		       EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
+};
+
 static struct platform_device ep93xx_bl_device = {
 	.name		= "ep93xx-bl",
 	.id		= -1,
+	.num_resources	= ARRAY_SIZE(ep93xx_bl_resources),
+	.resource	= ep93xx_bl_resources,
 };
 
 /**
diff --git a/drivers/video/backlight/ep93xx_bl.c b/drivers/video/backlight/ep93xx_bl.c
index b62b8b9..08214e1 100644
--- a/drivers/video/backlight/ep93xx_bl.c
+++ b/drivers/video/backlight/ep93xx_bl.c
@@ -17,11 +17,6 @@
 #include <linux/fb.h>
 #include <linux/backlight.h>
 
-#include <mach/hardware.h>
-
-#define EP93XX_RASTER_REG(x)		(EP93XX_RASTER_BASE + (x))
-#define EP93XX_RASTER_BRIGHTNESS	EP93XX_RASTER_REG(0x20)
-
 #define EP93XX_MAX_COUNT		255
 #define EP93XX_MAX_BRIGHT		255
 #define EP93XX_DEF_BRIGHT		128
@@ -35,7 +30,7 @@ static int ep93xxbl_set(struct backlight_device *bl, int brightness)
 {
 	struct ep93xxbl *ep93xxbl = bl_get_data(bl);
 
-	__raw_writel((brightness << 8) | EP93XX_MAX_COUNT, ep93xxbl->mmio);
+	writel((brightness << 8) | EP93XX_MAX_COUNT, ep93xxbl->mmio);
 
 	ep93xxbl->brightness = brightness;
 
@@ -70,21 +65,29 @@ static int __init ep93xxbl_probe(struct platform_device *dev)
 	struct ep93xxbl *ep93xxbl;
 	struct backlight_device *bl;
 	struct backlight_properties props;
+	struct resource *res;
 
 	ep93xxbl = devm_kzalloc(&dev->dev, sizeof(*ep93xxbl), GFP_KERNEL);
 	if (!ep93xxbl)
 		return -ENOMEM;
 
+	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENXIO;
+
 	/*
-	 * This register is located in the range already ioremap'ed by
-	 * the framebuffer driver.  A MFD driver seems a bit of overkill
-	 * to handle this so use the static I/O mapping; this address
-	 * is already virtual.
+	 * FIXME - We don't do a request_mem_region here because we are
+	 * sharing the register space with the framebuffer driver (see
+	 * drivers/video/ep93xx-fb.c) and doing so will cause the second
+	 * loaded driver to return -EBUSY.
 	 *
 	 * NOTE: No locking is required; the framebuffer does not touch
 	 * this register.
 	 */
-	ep93xxbl->mmio = EP93XX_RASTER_BRIGHTNESS;
+	ep93xxbl->mmio = devm_ioremap(&dev->dev, res->start,
+				      resource_size(res));
+	if (!ep93xxbl->mmio)
+		return -ENXIO;
 
 	memset(&props, 0, sizeof(struct backlight_properties));
 	props.type = BACKLIGHT_RAW;
diff --git a/drivers/video/ep93xx-fb.c b/drivers/video/ep93xx-fb.c
index 2e830ec..5301275 100644
--- a/drivers/video/ep93xx-fb.c
+++ b/drivers/video/ep93xx-fb.c
@@ -519,12 +519,15 @@ static int __devinit ep93xxfb_probe(struct platform_device *pdev)
 		goto failed;
 	}
 
-	res = request_mem_region(res->start, resource_size(res), pdev->name);
-	if (!res) {
-		err = -EBUSY;
-		goto failed;
-	}
-
+	/*
+	 * FIXME - We don't do a request_mem_region here because we are
+	 * sharing the register space with the backlight driver (see
+	 * drivers/video/backlight/ep93xx_bl.c) and doing so will cause
+	 * the second loaded driver to return -EBUSY.
+	 *
+	 * NOTE: No locking is required; the backlight does not touch
+	 * any of the framebuffer registers.
+	 */
 	fbi->res = res;
 	fbi->mmio_base = ioremap(res->start, resource_size(res));
 	if (!fbi->mmio_base) {
-- 
1.7.0.4



From rmallon at gmail.com  Mon Mar 12 18:48:16 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:16 +1100
Subject: [PATCH v4 05/11] ep93xx: Convert the watchdog driver into a platform
 device.
Message-ID: <1331592502-9083-6-git-send-email-rmallon@gmail.com>

From: H Hartley Sweeten <hsweeten at visionengravers.com>

From: H Hartley Sweeten <hsweeten at visionengravers.com>

Convert the ep93xx watchdog driver into a platform device and
remove it's dependency on <mach/hardware.h>.

Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Signed-off-by: Ryan Mallon <rmallon at gmail.com>
Signed-off-by: Wim Van Sebroeck <wim at iguana.be>
Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
Cc: Arnd Bergmann <arnd at arndb.de>
---
This patch has already been applied to Wim's watchdog tree. It has
included here for completeness because this patch series is against
v3.3-rc7.

 arch/arm/mach-ep93xx/core.c                     |   15 +++++++
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |    1 +
 drivers/watchdog/ep93xx_wdt.c                   |   51 ++++++++++++++++------
 3 files changed, 53 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index c73e299..3134baf 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -889,6 +889,20 @@ void __init ep93xx_register_ac97(void)
 	platform_device_register(&ep93xx_pcm_device);
 }
 
+/*************************************************************************
+ * EP93xx Watchdog
+ *************************************************************************/
+static struct resource ep93xx_wdt_resources[] = {
+	DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08),
+};
+
+static struct platform_device ep93xx_wdt_device = {
+	.name		= "ep93xx-wdt",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(ep93xx_wdt_resources),
+	.resource	= ep93xx_wdt_resources,
+};
+
 void __init ep93xx_init_devices(void)
 {
 	/* Disallow access to MaverickCrunch initially */
@@ -904,6 +918,7 @@ void __init ep93xx_init_devices(void)
 	platform_device_register(&ep93xx_rtc_device);
 	platform_device_register(&ep93xx_ohci_device);
 	platform_device_register(&ep93xx_leds);
+	platform_device_register(&ep93xx_wdt_device);
 }
 
 void ep93xx_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 72b8687..f28afcf 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -182,6 +182,7 @@
 #define EP93XX_SYSCON_SYSCFG_LCSN1	(1<<0)
 #define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)
 
+#define EP93XX_WATCHDOG_PHYS_BASE	EP93XX_APB_PHYS(0x00140000)
 #define EP93XX_WATCHDOG_BASE		EP93XX_APB_IOMEM(0x00140000)
 
 
diff --git a/drivers/watchdog/ep93xx_wdt.c b/drivers/watchdog/ep93xx_wdt.c
index 726b7df..09cd888 100644
--- a/drivers/watchdog/ep93xx_wdt.c
+++ b/drivers/watchdog/ep93xx_wdt.c
@@ -23,6 +23,7 @@
  *	- Add a few missing ioctls
  */
 
+#include <linux/platform_device.h>
 #include <linux/module.h>
 #include <linux/fs.h>
 #include <linux/miscdevice.h>
@@ -30,7 +31,6 @@
 #include <linux/timer.h>
 #include <linux/uaccess.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
 
 #define WDT_VERSION	"0.3"
 #define PFX		"ep93xx_wdt: "
@@ -41,6 +41,7 @@
 static int nowayout = WATCHDOG_NOWAYOUT;
 static int timeout = WDT_TIMEOUT;
 
+static void __iomem *mmio_base;
 static struct timer_list timer;
 static unsigned long next_heartbeat;
 static unsigned long wdt_status;
@@ -49,26 +50,25 @@ static unsigned long boot_status;
 #define WDT_IN_USE		0
 #define WDT_OK_TO_CLOSE		1
 
-#define EP93XX_WDT_REG(x)	(EP93XX_WATCHDOG_BASE + (x))
-#define EP93XX_WDT_WATCHDOG	EP93XX_WDT_REG(0x00)
-#define EP93XX_WDT_WDSTATUS	EP93XX_WDT_REG(0x04)
+#define EP93XX_WATCHDOG		0x00
+#define EP93XX_WDSTATUS		0x04
 
 /* reset the wdt every ~200ms */
 #define WDT_INTERVAL (HZ/5)
 
 static void wdt_enable(void)
 {
-	__raw_writew(0xaaaa, EP93XX_WDT_WATCHDOG);
+	writel(0xaaaa, mmio_base + EP93XX_WATCHDOG);
 }
 
 static void wdt_disable(void)
 {
-	__raw_writew(0xaa55, EP93XX_WDT_WATCHDOG);
+	writel(0xaa55, mmio_base + EP93XX_WATCHDOG);
 }
 
 static inline void wdt_ping(void)
 {
-	__raw_writew(0x5555, EP93XX_WDT_WATCHDOG);
+	writel(0x5555, mmio_base + EP93XX_WATCHDOG);
 }
 
 static void wdt_startup(void)
@@ -206,18 +206,32 @@ static void ep93xx_timer_ping(unsigned long data)
 	mod_timer(&timer, jiffies + WDT_INTERVAL);
 }
 
-static int __init ep93xx_wdt_init(void)
+static int __devinit ep93xx_wdt_probe(struct platform_device *pdev)
 {
+	struct resource *res;
+	unsigned long val;
 	int err;
 
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENXIO;
+
+	if (!devm_request_mem_region(&pdev->dev, res->start,
+				     resource_size(res), pdev->name))
+		return -EBUSY;
+
+	mmio_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+	if (!mmio_base)
+		return -ENXIO;
+
 	err = misc_register(&ep93xx_wdt_miscdev);
 
-	boot_status = __raw_readl(EP93XX_WDT_WATCHDOG) & 0x01 ? 1 : 0;
+	val = readl(mmio_base + EP93XX_WATCHDOG);
+	boot_status = val & 0x01 ? 1 : 0;
 
 	printk(KERN_INFO PFX "EP93XX watchdog, driver version "
 		WDT_VERSION "%s\n",
-		(__raw_readl(EP93XX_WDT_WATCHDOG) & 0x08)
-		? " (nCS1 disable detected)" : "");
+		(val & 0x08) ? " (nCS1 disable detected)" : "");
 
 	if (timeout < 1 || timeout > 3600) {
 		timeout = WDT_TIMEOUT;
@@ -230,14 +244,23 @@ static int __init ep93xx_wdt_init(void)
 	return err;
 }
 
-static void __exit ep93xx_wdt_exit(void)
+static int __devexit ep93xx_wdt_remove(struct platform_device *pdev)
 {
 	wdt_shutdown();
 	misc_deregister(&ep93xx_wdt_miscdev);
+	return 0;
 }
 
-module_init(ep93xx_wdt_init);
-module_exit(ep93xx_wdt_exit);
+static struct platform_driver ep93xx_wdt_driver = {
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "ep93xx-wdt",
+	},
+	.probe		= ep93xx_wdt_probe,
+	.remove		= __devexit_p(ep93xx_wdt_remove),
+};
+
+module_platform_driver(ep93xx_wdt_driver);
 
 module_param(nowayout, int, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
-- 
1.7.0.4



From rmallon at gmail.com  Mon Mar 12 18:48:17 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:17 +1100
Subject: [PATCH v4 06/11] ep93xx: Move peripheral defines to local SoC header
Message-ID: <1331592502-9083-7-git-send-email-rmallon@gmail.com>

Move the AHB/APB peripheral defines to local SoC header since they are
only needed by the core SoC code. The UART defines are not moved
because they are used by the mach/uncompress.h header.

Signed-off-by: Ryan Mallon <rmallon at gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>
---
 arch/arm/mach-ep93xx/core.c                     |    1 +
 arch/arm/mach-ep93xx/dma.c                      |    2 +
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |   61 +----------------------
 arch/arm/mach-ep93xx/soc.h                      |   57 +++++++++++++++++++++
 4 files changed, 61 insertions(+), 60 deletions(-)

diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 3134baf..776b346 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -46,6 +46,7 @@
 
 #include <asm/hardware/vic.h>
 
+#include "soc.h"
 
 /*************************************************************************
  * Static I/O mappings that are needed for all EP93xx platforms
diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c
index 5a25708..16976d7 100644
--- a/arch/arm/mach-ep93xx/dma.c
+++ b/arch/arm/mach-ep93xx/dma.c
@@ -28,6 +28,8 @@
 #include <mach/dma.h>
 #include <mach/hardware.h>
 
+#include "soc.h"
+
 #define DMA_CHANNEL(_name, _base, _irq) \
 	{ .name = (_name), .base = (_base), .irq = (_irq) }
 
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index f28afcf..fbda7b4 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -28,50 +28,7 @@
 #define EP93XX_APB_PHYS(x)		(EP93XX_APB_PHYS_BASE + (x))
 #define EP93XX_APB_IOMEM(x)		IOMEM(EP93XX_APB_VIRT_BASE + (x))
 
-
-/* AHB peripherals */
-#define EP93XX_DMA_BASE			EP93XX_AHB_IOMEM(0x00000000)
-
-#define EP93XX_ETHERNET_PHYS_BASE	EP93XX_AHB_PHYS(0x00010000)
-#define EP93XX_ETHERNET_BASE		EP93XX_AHB_IOMEM(0x00010000)
-
-#define EP93XX_USB_PHYS_BASE		EP93XX_AHB_PHYS(0x00020000)
-#define EP93XX_USB_BASE			EP93XX_AHB_IOMEM(0x00020000)
-
-#define EP93XX_RASTER_PHYS_BASE		EP93XX_AHB_PHYS(0x00030000)
-#define EP93XX_RASTER_BASE		EP93XX_AHB_IOMEM(0x00030000)
-
-#define EP93XX_GRAPHICS_ACCEL_BASE	EP93XX_AHB_IOMEM(0x00040000)
-
-#define EP93XX_SDRAM_CONTROLLER_BASE	EP93XX_AHB_IOMEM(0x00060000)
-
-#define EP93XX_PCMCIA_CONTROLLER_BASE	EP93XX_AHB_IOMEM(0x00080000)
-
-#define EP93XX_BOOT_ROM_BASE		EP93XX_AHB_IOMEM(0x00090000)
-
-#define EP93XX_IDE_BASE			EP93XX_AHB_IOMEM(0x000a0000)
-
-#define EP93XX_VIC1_BASE		EP93XX_AHB_IOMEM(0x000b0000)
-
-#define EP93XX_VIC2_BASE		EP93XX_AHB_IOMEM(0x000c0000)
-
-
-/* APB peripherals */
-#define EP93XX_TIMER_BASE		EP93XX_APB_IOMEM(0x00010000)
-
-#define EP93XX_I2S_PHYS_BASE		EP93XX_APB_PHYS(0x00020000)
-#define EP93XX_I2S_BASE			EP93XX_APB_IOMEM(0x00020000)
-
-#define EP93XX_SECURITY_BASE		EP93XX_APB_IOMEM(0x00030000)
-
-#define EP93XX_AAC_PHYS_BASE		EP93XX_APB_PHYS(0x00080000)
-#define EP93XX_AAC_BASE			EP93XX_APB_IOMEM(0x00080000)
-
-#define EP93XX_SPI_PHYS_BASE		EP93XX_APB_PHYS(0x000a0000)
-#define EP93XX_SPI_BASE			EP93XX_APB_IOMEM(0x000a0000)
-
-#define EP93XX_IRDA_BASE		EP93XX_APB_IOMEM(0x000b0000)
-
+/* APB UARTs */
 #define EP93XX_UART1_PHYS_BASE		EP93XX_APB_PHYS(0x000c0000)
 #define EP93XX_UART1_BASE		EP93XX_APB_IOMEM(0x000c0000)
 
@@ -81,18 +38,6 @@
 #define EP93XX_UART3_PHYS_BASE		EP93XX_APB_PHYS(0x000e0000)
 #define EP93XX_UART3_BASE		EP93XX_APB_IOMEM(0x000e0000)
 
-#define EP93XX_KEY_MATRIX_PHYS_BASE	EP93XX_APB_PHYS(0x000f0000)
-#define EP93XX_KEY_MATRIX_BASE		EP93XX_APB_IOMEM(0x000f0000)
-
-#define EP93XX_ADC_BASE			EP93XX_APB_IOMEM(0x00100000)
-#define EP93XX_TOUCHSCREEN_BASE		EP93XX_APB_IOMEM(0x00100000)
-
-#define EP93XX_PWM_PHYS_BASE		EP93XX_APB_PHYS(0x00110000)
-#define EP93XX_PWM_BASE			EP93XX_APB_IOMEM(0x00110000)
-
-#define EP93XX_RTC_PHYS_BASE		EP93XX_APB_PHYS(0x00120000)
-#define EP93XX_RTC_BASE			EP93XX_APB_IOMEM(0x00120000)
-
 #define EP93XX_SYSCON_BASE		EP93XX_APB_IOMEM(0x00130000)
 #define EP93XX_SYSCON_REG(x)		(EP93XX_SYSCON_BASE + (x))
 #define EP93XX_SYSCON_POWER_STATE	EP93XX_SYSCON_REG(0x00)
@@ -182,8 +127,4 @@
 #define EP93XX_SYSCON_SYSCFG_LCSN1	(1<<0)
 #define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)
 
-#define EP93XX_WATCHDOG_PHYS_BASE	EP93XX_APB_PHYS(0x00140000)
-#define EP93XX_WATCHDOG_BASE		EP93XX_APB_IOMEM(0x00140000)
-
-
 #endif
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
index 74703e7..a22e11b 100644
--- a/arch/arm/mach-ep93xx/soc.h
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -47,4 +47,61 @@
 #define EP93XX_SDCE3_PHYS_BASE_ASYNC	0xf0000000	/* ASDO Pin = 0 */
 #define EP93XX_CS0_PHYS_BASE_SYNC	0xf0000000	/* ASDO Pin = 1 */
 
+/* AHB peripherals */
+#define EP93XX_DMA_BASE			EP93XX_AHB_IOMEM(0x00000000)
+
+#define EP93XX_ETHERNET_PHYS_BASE	EP93XX_AHB_PHYS(0x00010000)
+#define EP93XX_ETHERNET_BASE		EP93XX_AHB_IOMEM(0x00010000)
+
+#define EP93XX_USB_PHYS_BASE		EP93XX_AHB_PHYS(0x00020000)
+#define EP93XX_USB_BASE			EP93XX_AHB_IOMEM(0x00020000)
+
+#define EP93XX_RASTER_PHYS_BASE		EP93XX_AHB_PHYS(0x00030000)
+#define EP93XX_RASTER_BASE		EP93XX_AHB_IOMEM(0x00030000)
+
+#define EP93XX_GRAPHICS_ACCEL_BASE	EP93XX_AHB_IOMEM(0x00040000)
+
+#define EP93XX_SDRAM_CONTROLLER_BASE	EP93XX_AHB_IOMEM(0x00060000)
+
+#define EP93XX_PCMCIA_CONTROLLER_BASE	EP93XX_AHB_IOMEM(0x00080000)
+
+#define EP93XX_BOOT_ROM_BASE		EP93XX_AHB_IOMEM(0x00090000)
+
+#define EP93XX_IDE_BASE			EP93XX_AHB_IOMEM(0x000a0000)
+
+#define EP93XX_VIC1_BASE		EP93XX_AHB_IOMEM(0x000b0000)
+
+#define EP93XX_VIC2_BASE		EP93XX_AHB_IOMEM(0x000c0000)
+
+/* APB peripherals */
+#define EP93XX_TIMER_BASE		EP93XX_APB_IOMEM(0x00010000)
+
+#define EP93XX_I2S_PHYS_BASE		EP93XX_APB_PHYS(0x00020000)
+#define EP93XX_I2S_BASE			EP93XX_APB_IOMEM(0x00020000)
+
+#define EP93XX_SECURITY_BASE		EP93XX_APB_IOMEM(0x00030000)
+
+#define EP93XX_AAC_PHYS_BASE		EP93XX_APB_PHYS(0x00080000)
+#define EP93XX_AAC_BASE			EP93XX_APB_IOMEM(0x00080000)
+
+#define EP93XX_SPI_PHYS_BASE		EP93XX_APB_PHYS(0x000a0000)
+#define EP93XX_SPI_BASE			EP93XX_APB_IOMEM(0x000a0000)
+
+#define EP93XX_IRDA_BASE		EP93XX_APB_IOMEM(0x000b0000)
+
+#define EP93XX_KEY_MATRIX_PHYS_BASE	EP93XX_APB_PHYS(0x000f0000)
+#define EP93XX_KEY_MATRIX_BASE		EP93XX_APB_IOMEM(0x000f0000)
+
+#define EP93XX_ADC_BASE			EP93XX_APB_IOMEM(0x00100000)
+#define EP93XX_TOUCHSCREEN_BASE		EP93XX_APB_IOMEM(0x00100000)
+
+#define EP93XX_PWM_PHYS_BASE		EP93XX_APB_PHYS(0x00110000)
+#define EP93XX_PWM_BASE			EP93XX_APB_IOMEM(0x00110000)
+
+#define EP93XX_RTC_PHYS_BASE		EP93XX_APB_PHYS(0x00120000)
+#define EP93XX_RTC_BASE			EP93XX_APB_IOMEM(0x00120000)
+
+#define EP93XX_WATCHDOG_PHYS_BASE	EP93XX_APB_PHYS(0x00140000)
+#define EP93XX_WATCHDOG_BASE		EP93XX_APB_IOMEM(0x00140000)
+
 #endif /* _EP93XX_PHYS_BASE_H */
-- 
1.7.0.4



From rmallon at gmail.com  Mon Mar 12 18:48:18 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:18 +1100
Subject: [PATCH v4 07/11] ep93xx: Configure GPIO ports in core code
Message-ID: <1331592502-9083-8-git-send-email-rmallon@gmail.com>

Move the pinmux setting of the EP93xx GPIOs to the core code. This
removes the need for the GPIO driver to have access to the system
controller registers.

Signed-off-by: Ryan Mallon <rmallon at gmail.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>
---
 arch/arm/mach-ep93xx/core.c |    7 +++++++
 drivers/gpio/gpio-ep93xx.c  |    7 -------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 776b346..bab6e47 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -909,6 +909,13 @@ void __init ep93xx_init_devices(void)
 	/* Disallow access to MaverickCrunch initially */
 	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
 
+	/* Default all ports to GPIO */
+	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
+			       EP93XX_SYSCON_DEVCFG_GONK |
+			       EP93XX_SYSCON_DEVCFG_EONIDE |
+			       EP93XX_SYSCON_DEVCFG_GONIDE |
+			       EP93XX_SYSCON_DEVCFG_HONIDE);
+
 	/* Get the GPIO working early, other devices need it */
 	platform_device_register(&ep93xx_gpio_device);
 
diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c
index 1c0fc37..4ca5642 100644
--- a/drivers/gpio/gpio-ep93xx.c
+++ b/drivers/gpio/gpio-ep93xx.c
@@ -378,13 +378,6 @@ static int __devinit ep93xx_gpio_probe(struct platform_device *pdev)
 	}
 	ep93xx_gpio->mmio_base = mmio;
 
-	/* Default all ports to GPIO */
-	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
-			       EP93XX_SYSCON_DEVCFG_GONK |
-			       EP93XX_SYSCON_DEVCFG_EONIDE |
-			       EP93XX_SYSCON_DEVCFG_GONIDE |
-			       EP93XX_SYSCON_DEVCFG_HONIDE);
-
 	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
 		struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
 		struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
-- 
1.7.0.4



From rmallon at gmail.com  Mon Mar 12 18:48:19 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:19 +1100
Subject: [PATCH v4 08/11] ep93xx: Make syscon access functions private to SoC
Message-ID: <1331592502-9083-9-git-send-email-rmallon@gmail.com>

The syscon access functions are no longer used outside of the core
EP93xx code. Move their definitions into the SoC code.

Signed-off-by: Ryan Mallon <rmallon at gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>
---
 arch/arm/mach-ep93xx/clock.c                 |    1 +
 arch/arm/mach-ep93xx/core.c                  |    2 --
 arch/arm/mach-ep93xx/include/mach/platform.h |   14 --------------
 arch/arm/mach-ep93xx/soc.h                   |   14 ++++++++++++++
 4 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index ca4de71..c95dbce 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -25,6 +25,7 @@
 
 #include <asm/div64.h>
 
+#include "soc.h"
 
 struct clk {
 	struct clk	*parent;
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index bab6e47..c9511fe 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -205,7 +205,6 @@ void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
 
 	spin_unlock_irqrestore(&syscon_swlock, flags);
 }
-EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
 
 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
 {
@@ -222,7 +221,6 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
 
 	spin_unlock_irqrestore(&syscon_swlock, flags);
 }
-EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
 
 /**
  * ep93xx_chip_revision() - returns the EP93xx chip revision
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index ad63d4b..602bd87 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -21,20 +21,6 @@ struct ep93xx_eth_data
 void ep93xx_map_io(void);
 void ep93xx_init_irq(void);
 
-/* EP93xx System Controller software locked register write */
-void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
-void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
-
-static inline void ep93xx_devcfg_set_bits(unsigned int bits)
-{
-	ep93xx_devcfg_set_clear(bits, 0x00);
-}
-
-static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
-{
-	ep93xx_devcfg_set_clear(0x00, bits);
-}
-
 #define EP93XX_CHIP_REV_D0	3
 #define EP93XX_CHIP_REV_D1	4
 #define EP93XX_CHIP_REV_E0	5
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
index a22e11b..1273013 100644
--- a/arch/arm/mach-ep93xx/soc.h
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -104,4 +104,18 @@
 #define EP93XX_WATCHDOG_PHYS_BASE	EP93XX_APB_PHYS(0x00140000)
 #define EP93XX_WATCHDOG_BASE		EP93XX_APB_IOMEM(0x00140000)
 
+/* EP93xx System Controller software locked register write */
+void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
+void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
+
+static inline void ep93xx_devcfg_set_bits(unsigned int bits)
+{
+	ep93xx_devcfg_set_clear(bits, 0x00);
+}
+
+static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
+{
+	ep93xx_devcfg_set_clear(0x00, bits);
+}
+
 #endif /* _EP93XX_PHYS_BASE_H */
-- 
1.7.0.4



From rmallon at gmail.com  Mon Mar 12 18:48:22 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:22 +1100
Subject: [PATCH v4 11/11] ep93xx: Remove unnecessary includes of ep93xx-regs.h
Message-ID: <1331592502-9083-12-git-send-email-rmallon@gmail.com>

Remove the include of ep93xx-regs.h from files which no longer need
it, notably include/mach/hardware.h.

Signed-off-by: Ryan Mallon <rmallon at gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>
---
 arch/arm/mach-ep93xx/crunch.c                |    2 +-
 arch/arm/mach-ep93xx/include/mach/hardware.h |    1 -
 arch/arm/mach-ep93xx/soc.h                   |    2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-ep93xx/crunch.c b/arch/arm/mach-ep93xx/crunch.c
index d05ed0b..74753e2 100644
--- a/arch/arm/mach-ep93xx/crunch.c
+++ b/arch/arm/mach-ep93xx/crunch.c
@@ -16,7 +16,7 @@
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <mach/ep93xx-regs.h>
+
 #include <asm/thread_notify.h>
 
 #include "soc.h"
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 4df8428..efcd478 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -5,7 +5,6 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
-#include <mach/ep93xx-regs.h>
 #include <mach/platform.h>
 
 /*
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
index ce32c2c..a20e558 100644
--- a/arch/arm/mach-ep93xx/soc.h
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -13,6 +13,8 @@
 #ifndef _EP93XX_SOC_H
 #define _EP93XX_SOC_H
 
+#include <mach/ep93xx-regs.h>
+
 /*
  * EP93xx Physical Memory Map:
  *
-- 
1.7.0.4



From rmallon at gmail.com  Mon Mar 12 18:48:21 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:21 +1100
Subject: [PATCH v4 10/11] ep93xx: Move EP93XX_SYSCON defines to SoC private
 header
Message-ID: <1331592502-9083-11-git-send-email-rmallon@gmail.com>

The EP93XX_SYSCON defines are now no longer needed outside of the
EP93xx SoC core code, so they can be moved to a private header.

Signed-off-by: Ryan Mallon <rmallon at gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>
---
 arch/arm/mach-ep93xx/crunch.c                   |    2 +
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |   89 ----------------------
 arch/arm/mach-ep93xx/soc.h                      |   90 +++++++++++++++++++++++
 3 files changed, 92 insertions(+), 89 deletions(-)

diff --git a/arch/arm/mach-ep93xx/crunch.c b/arch/arm/mach-ep93xx/crunch.c
index 25ef223..d05ed0b 100644
--- a/arch/arm/mach-ep93xx/crunch.c
+++ b/arch/arm/mach-ep93xx/crunch.c
@@ -19,6 +19,8 @@
 #include <mach/ep93xx-regs.h>
 #include <asm/thread_notify.h>
 
+#include "soc.h"
+
 struct crunch_state *crunch_owner;
 
 void crunch_task_release(struct thread_info *thread)
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index fbda7b4..c64d742 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -38,93 +38,4 @@
 #define EP93XX_UART3_PHYS_BASE		EP93XX_APB_PHYS(0x000e0000)
 #define EP93XX_UART3_BASE		EP93XX_APB_IOMEM(0x000e0000)
 
-#define EP93XX_SYSCON_BASE		EP93XX_APB_IOMEM(0x00130000)
-#define EP93XX_SYSCON_REG(x)		(EP93XX_SYSCON_BASE + (x))
-#define EP93XX_SYSCON_POWER_STATE	EP93XX_SYSCON_REG(0x00)
-#define EP93XX_SYSCON_PWRCNT		EP93XX_SYSCON_REG(0x04)
-#define EP93XX_SYSCON_PWRCNT_FIR_EN	(1<<31)
-#define EP93XX_SYSCON_PWRCNT_UARTBAUD	(1<<29)
-#define EP93XX_SYSCON_PWRCNT_USH_EN	(1<<28)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M1	(1<<27)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M0	(1<<26)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P8	(1<<25)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P9	(1<<24)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P6	(1<<23)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P7	(1<<22)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P4	(1<<21)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P5	(1<<20)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P2	(1<<19)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P3	(1<<18)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P0	(1<<17)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)
-#define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)
-#define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)
-#define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLKSET1_NBYP1	(1<<23)
-#define EP93XX_SYSCON_CLKSET2		EP93XX_SYSCON_REG(0x24)
-#define EP93XX_SYSCON_CLKSET2_NBYP2	(1<<19)
-#define EP93XX_SYSCON_CLKSET2_PLL2_EN	(1<<18)
-#define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)
-#define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30)
-#define EP93XX_SYSCON_DEVCFG_D0ONG	(1<<29)
-#define EP93XX_SYSCON_DEVCFG_IONU2	(1<<28)
-#define EP93XX_SYSCON_DEVCFG_GONK	(1<<27)
-#define EP93XX_SYSCON_DEVCFG_TONG	(1<<26)
-#define EP93XX_SYSCON_DEVCFG_MONG	(1<<25)
-#define EP93XX_SYSCON_DEVCFG_U3EN	(1<<24)
-#define EP93XX_SYSCON_DEVCFG_CPENA	(1<<23)
-#define EP93XX_SYSCON_DEVCFG_A2ONG	(1<<22)
-#define EP93XX_SYSCON_DEVCFG_A1ONG	(1<<21)
-#define EP93XX_SYSCON_DEVCFG_U2EN	(1<<20)
-#define EP93XX_SYSCON_DEVCFG_EXVC	(1<<19)
-#define EP93XX_SYSCON_DEVCFG_U1EN	(1<<18)
-#define EP93XX_SYSCON_DEVCFG_TIN	(1<<17)
-#define EP93XX_SYSCON_DEVCFG_HC3IN	(1<<15)
-#define EP93XX_SYSCON_DEVCFG_HC3EN	(1<<14)
-#define EP93XX_SYSCON_DEVCFG_HC1IN	(1<<13)
-#define EP93XX_SYSCON_DEVCFG_HC1EN	(1<<12)
-#define EP93XX_SYSCON_DEVCFG_HONIDE	(1<<11)
-#define EP93XX_SYSCON_DEVCFG_GONIDE	(1<<10)
-#define EP93XX_SYSCON_DEVCFG_PONG	(1<<9)
-#define EP93XX_SYSCON_DEVCFG_EONIDE	(1<<8)
-#define EP93XX_SYSCON_DEVCFG_I2SONSSP	(1<<7)
-#define EP93XX_SYSCON_DEVCFG_I2SONAC97	(1<<6)
-#define EP93XX_SYSCON_DEVCFG_RASONP3	(1<<4)
-#define EP93XX_SYSCON_DEVCFG_RAS	(1<<3)
-#define EP93XX_SYSCON_DEVCFG_ADCPD	(1<<2)
-#define EP93XX_SYSCON_DEVCFG_KEYS	(1<<1)
-#define EP93XX_SYSCON_DEVCFG_SHENA	(1<<0)
-#define EP93XX_SYSCON_VIDCLKDIV		EP93XX_SYSCON_REG(0x84)
-#define EP93XX_SYSCON_CLKDIV_ENABLE	(1<<15)
-#define EP93XX_SYSCON_CLKDIV_ESEL	(1<<14)
-#define EP93XX_SYSCON_CLKDIV_PSEL	(1<<13)
-#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT	8
-#define EP93XX_SYSCON_I2SCLKDIV		EP93XX_SYSCON_REG(0x8c)
-#define EP93XX_SYSCON_I2SCLKDIV_SENA	(1<<31)
-#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
-#define EP93XX_SYSCON_I2SCLKDIV_SPOL	(1<<19)
-#define EP93XX_I2SCLKDIV_SDIV		(1 << 16)
-#define EP93XX_I2SCLKDIV_LRDIV32	(0 << 17)
-#define EP93XX_I2SCLKDIV_LRDIV64	(1 << 17)
-#define EP93XX_I2SCLKDIV_LRDIV128 	(2 << 17)
-#define EP93XX_I2SCLKDIV_LRDIV_MASK 	(3 << 17)
-#define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN	(1<<15)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV	(1<<0)
-#define EP93XX_SYSCON_SYSCFG		EP93XX_SYSCON_REG(0x9c)
-#define EP93XX_SYSCON_SYSCFG_REV_MASK	(0xf0000000)
-#define EP93XX_SYSCON_SYSCFG_REV_SHIFT	(28)
-#define EP93XX_SYSCON_SYSCFG_SBOOT	(1<<8)
-#define EP93XX_SYSCON_SYSCFG_LCSN7	(1<<7)
-#define EP93XX_SYSCON_SYSCFG_LCSN6	(1<<6)
-#define EP93XX_SYSCON_SYSCFG_LASDO	(1<<5)
-#define EP93XX_SYSCON_SYSCFG_LEEDA	(1<<4)
-#define EP93XX_SYSCON_SYSCFG_LEECLK	(1<<3)
-#define EP93XX_SYSCON_SYSCFG_LCSN2	(1<<1)
-#define EP93XX_SYSCON_SYSCFG_LCSN1	(1<<0)
-#define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)
-
 #endif
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
index 1273013..ce32c2c 100644
--- a/arch/arm/mach-ep93xx/soc.h
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -104,6 +104,96 @@
 #define EP93XX_WATCHDOG_PHYS_BASE	EP93XX_APB_PHYS(0x00140000)
 #define EP93XX_WATCHDOG_BASE		EP93XX_APB_IOMEM(0x00140000)
 
+/* System controller */
+#define EP93XX_SYSCON_BASE		EP93XX_APB_IOMEM(0x00130000)
+#define EP93XX_SYSCON_REG(x)		(EP93XX_SYSCON_BASE + (x))
+#define EP93XX_SYSCON_POWER_STATE	EP93XX_SYSCON_REG(0x00)
+#define EP93XX_SYSCON_PWRCNT		EP93XX_SYSCON_REG(0x04)
+#define EP93XX_SYSCON_PWRCNT_FIR_EN	(1<<31)
+#define EP93XX_SYSCON_PWRCNT_UARTBAUD	(1<<29)
+#define EP93XX_SYSCON_PWRCNT_USH_EN	(1<<28)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M1	(1<<27)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M0	(1<<26)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P8	(1<<25)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P9	(1<<24)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P6	(1<<23)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P7	(1<<22)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P4	(1<<21)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P5	(1<<20)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P2	(1<<19)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P3	(1<<18)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P0	(1<<17)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P1	(1<<16)
+#define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)
+#define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)
+#define EP93XX_SYSCON_CLKSET1		EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1_NBYP1	(1<<23)
+#define EP93XX_SYSCON_CLKSET2		EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET2_NBYP2	(1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN	(1<<18)
+#define EP93XX_SYSCON_DEVCFG		EP93XX_SYSCON_REG(0x80)
+#define EP93XX_SYSCON_DEVCFG_SWRST	(1<<31)
+#define EP93XX_SYSCON_DEVCFG_D1ONG	(1<<30)
+#define EP93XX_SYSCON_DEVCFG_D0ONG	(1<<29)
+#define EP93XX_SYSCON_DEVCFG_IONU2	(1<<28)
+#define EP93XX_SYSCON_DEVCFG_GONK	(1<<27)
+#define EP93XX_SYSCON_DEVCFG_TONG	(1<<26)
+#define EP93XX_SYSCON_DEVCFG_MONG	(1<<25)
+#define EP93XX_SYSCON_DEVCFG_U3EN	(1<<24)
+#define EP93XX_SYSCON_DEVCFG_CPENA	(1<<23)
+#define EP93XX_SYSCON_DEVCFG_A2ONG	(1<<22)
+#define EP93XX_SYSCON_DEVCFG_A1ONG	(1<<21)
+#define EP93XX_SYSCON_DEVCFG_U2EN	(1<<20)
+#define EP93XX_SYSCON_DEVCFG_EXVC	(1<<19)
+#define EP93XX_SYSCON_DEVCFG_U1EN	(1<<18)
+#define EP93XX_SYSCON_DEVCFG_TIN	(1<<17)
+#define EP93XX_SYSCON_DEVCFG_HC3IN	(1<<15)
+#define EP93XX_SYSCON_DEVCFG_HC3EN	(1<<14)
+#define EP93XX_SYSCON_DEVCFG_HC1IN	(1<<13)
+#define EP93XX_SYSCON_DEVCFG_HC1EN	(1<<12)
+#define EP93XX_SYSCON_DEVCFG_HONIDE	(1<<11)
+#define EP93XX_SYSCON_DEVCFG_GONIDE	(1<<10)
+#define EP93XX_SYSCON_DEVCFG_PONG	(1<<9)
+#define EP93XX_SYSCON_DEVCFG_EONIDE	(1<<8)
+#define EP93XX_SYSCON_DEVCFG_I2SONSSP	(1<<7)
+#define EP93XX_SYSCON_DEVCFG_I2SONAC97	(1<<6)
+#define EP93XX_SYSCON_DEVCFG_RASONP3	(1<<4)
+#define EP93XX_SYSCON_DEVCFG_RAS	(1<<3)
+#define EP93XX_SYSCON_DEVCFG_ADCPD	(1<<2)
+#define EP93XX_SYSCON_DEVCFG_KEYS	(1<<1)
+#define EP93XX_SYSCON_DEVCFG_SHENA	(1<<0)
+#define EP93XX_SYSCON_VIDCLKDIV		EP93XX_SYSCON_REG(0x84)
+#define EP93XX_SYSCON_CLKDIV_ENABLE	(1<<15)
+#define EP93XX_SYSCON_CLKDIV_ESEL	(1<<14)
+#define EP93XX_SYSCON_CLKDIV_PSEL	(1<<13)
+#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT	8
+#define EP93XX_SYSCON_I2SCLKDIV		EP93XX_SYSCON_REG(0x8c)
+#define EP93XX_SYSCON_I2SCLKDIV_SENA	(1<<31)
+#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
+#define EP93XX_SYSCON_I2SCLKDIV_SPOL	(1<<19)
+#define EP93XX_I2SCLKDIV_SDIV		(1 << 16)
+#define EP93XX_I2SCLKDIV_LRDIV32	(0 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV64	(1 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV128 	(2 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV_MASK 	(3 << 17)
+#define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN	(1<<15)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV	(1<<0)
+#define EP93XX_SYSCON_SYSCFG		EP93XX_SYSCON_REG(0x9c)
+#define EP93XX_SYSCON_SYSCFG_REV_MASK	(0xf0000000)
+#define EP93XX_SYSCON_SYSCFG_REV_SHIFT	(28)
+#define EP93XX_SYSCON_SYSCFG_SBOOT	(1<<8)
+#define EP93XX_SYSCON_SYSCFG_LCSN7	(1<<7)
+#define EP93XX_SYSCON_SYSCFG_LCSN6	(1<<6)
+#define EP93XX_SYSCON_SYSCFG_LASDO	(1<<5)
+#define EP93XX_SYSCON_SYSCFG_LEEDA	(1<<4)
+#define EP93XX_SYSCON_SYSCFG_LEECLK	(1<<3)
+#define EP93XX_SYSCON_SYSCFG_LCSN2	(1<<1)
+#define EP93XX_SYSCON_SYSCFG_LCSN1	(1<<0)
+#define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)
+
 /* EP93xx System Controller software locked register write */
 void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
-- 
1.7.0.4



From rmallon at gmail.com  Mon Mar 12 18:48:20 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Tue, 13 Mar 2012 09:48:20 +1100
Subject: [PATCH v4 09/11] ep93xx: Move crunch code to mach-ep93xx directory
Message-ID: <1331592502-9083-10-git-send-email-rmallon@gmail.com>

The crunch code in arch/arm/kernel is specific to the EP93xx. Move it
to the mach-ep93xx directory. This removes the need for the
EP93XX_SYSCON defines to be exported to arch/arm/kernel.

Signed-off-by: Ryan Mallon <rmallon at gmail.com>
Cc: Russell King <linux at arm.linux.org.uk>
Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>
---
 arch/arm/kernel/Makefile           |    3 -
 arch/arm/kernel/crunch-bits.S      |  305 ------------------------------------
 arch/arm/kernel/crunch.c           |   88 -----------
 arch/arm/mach-ep93xx/Makefile      |    3 +
 arch/arm/mach-ep93xx/crunch-bits.S |  305 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-ep93xx/crunch.c      |   88 +++++++++++
 6 files changed, 396 insertions(+), 396 deletions(-)
 delete mode 100644 arch/arm/kernel/crunch-bits.S
 delete mode 100644 arch/arm/kernel/crunch.c
 create mode 100644 arch/arm/mach-ep93xx/crunch-bits.S
 create mode 100644 arch/arm/mach-ep93xx/crunch.c

diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 43b740d..f16d765 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -62,9 +62,6 @@ obj-$(CONFIG_SWP_EMULATE)	+= swp_emulate.o
 CFLAGS_swp_emulate.o		:= -Wa,-march=armv7-a
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)	+= hw_breakpoint.o
 
-obj-$(CONFIG_CRUNCH)		+= crunch.o crunch-bits.o
-AFLAGS_crunch-bits.o		:= -Wa,-mcpu=ep9312
-
 obj-$(CONFIG_CPU_XSCALE)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_XSC3)		+= xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)	+= xscale-cp0.o
diff --git a/arch/arm/kernel/crunch-bits.S b/arch/arm/kernel/crunch-bits.S
deleted file mode 100644
index 0ec9bb4..0000000
--- a/arch/arm/kernel/crunch-bits.S
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
- * arch/arm/kernel/crunch-bits.S
- * Cirrus MaverickCrunch context switching and handling
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh at wantstofly.org>
- *
- * Shamelessly stolen from the iWMMXt code by Nicolas Pitre, which is
- * Copyright (c) 2003-2004, MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/thread_info.h>
-#include <asm/asm-offsets.h>
-#include <mach/ep93xx-regs.h>
-
-/*
- * We can't use hex constants here due to a bug in gas.
- */
-#define CRUNCH_MVDX0		0
-#define CRUNCH_MVDX1		8
-#define CRUNCH_MVDX2		16
-#define CRUNCH_MVDX3		24
-#define CRUNCH_MVDX4		32
-#define CRUNCH_MVDX5		40
-#define CRUNCH_MVDX6		48
-#define CRUNCH_MVDX7		56
-#define CRUNCH_MVDX8		64
-#define CRUNCH_MVDX9		72
-#define CRUNCH_MVDX10		80
-#define CRUNCH_MVDX11		88
-#define CRUNCH_MVDX12		96
-#define CRUNCH_MVDX13		104
-#define CRUNCH_MVDX14		112
-#define CRUNCH_MVDX15		120
-#define CRUNCH_MVAX0L		128
-#define CRUNCH_MVAX0M		132
-#define CRUNCH_MVAX0H		136
-#define CRUNCH_MVAX1L		140
-#define CRUNCH_MVAX1M		144
-#define CRUNCH_MVAX1H		148
-#define CRUNCH_MVAX2L		152
-#define CRUNCH_MVAX2M		156
-#define CRUNCH_MVAX2H		160
-#define CRUNCH_MVAX3L		164
-#define CRUNCH_MVAX3M		168
-#define CRUNCH_MVAX3H		172
-#define CRUNCH_DSPSC		176
-
-#define CRUNCH_SIZE		184
-
-	.text
-
-/*
- * Lazy switching of crunch coprocessor context
- *
- * r10 = struct thread_info pointer
- * r9  = ret_from_exception
- * lr  = undefined instr exit
- *
- * called from prefetch exception handler with interrupts disabled
- */
-ENTRY(crunch_task_enable)
-	ldr	r8, =(EP93XX_APB_VIRT_BASE + 0x00130000)	@ syscon addr
-
-	ldr	r1, [r8, #0x80]
-	tst	r1, #0x00800000			@ access to crunch enabled?
-	movne	pc, lr				@ if so no business here
-	mov	r3, #0xaa			@ unlock syscon swlock
-	str	r3, [r8, #0xc0]
-	orr	r1, r1, #0x00800000		@ enable access to crunch
-	str	r1, [r8, #0x80]
-
-	ldr	r3, =crunch_owner
-	add	r0, r10, #TI_CRUNCH_STATE	@ get task crunch save area
-	ldr	r2, [sp, #60]			@ current task pc value
-	ldr	r1, [r3]			@ get current crunch owner
-	str	r0, [r3]			@ this task now owns crunch
-	sub	r2, r2, #4			@ adjust pc back
-	str	r2, [sp, #60]
-
-	ldr	r2, [r8, #0x80]
-	mov	r2, r2				@ flush out enable (@@@)
-
-	teq	r1, #0				@ test for last ownership
-	mov	lr, r9				@ normal exit from exception
-	beq	crunch_load			@ no owner, skip save
-
-crunch_save:
-	cfstr64		mvdx0, [r1, #CRUNCH_MVDX0]	@ save 64b registers
-	cfstr64		mvdx1, [r1, #CRUNCH_MVDX1]
-	cfstr64		mvdx2, [r1, #CRUNCH_MVDX2]
-	cfstr64		mvdx3, [r1, #CRUNCH_MVDX3]
-	cfstr64		mvdx4, [r1, #CRUNCH_MVDX4]
-	cfstr64		mvdx5, [r1, #CRUNCH_MVDX5]
-	cfstr64		mvdx6, [r1, #CRUNCH_MVDX6]
-	cfstr64		mvdx7, [r1, #CRUNCH_MVDX7]
-	cfstr64		mvdx8, [r1, #CRUNCH_MVDX8]
-	cfstr64		mvdx9, [r1, #CRUNCH_MVDX9]
-	cfstr64		mvdx10, [r1, #CRUNCH_MVDX10]
-	cfstr64		mvdx11, [r1, #CRUNCH_MVDX11]
-	cfstr64		mvdx12, [r1, #CRUNCH_MVDX12]
-	cfstr64		mvdx13, [r1, #CRUNCH_MVDX13]
-	cfstr64		mvdx14, [r1, #CRUNCH_MVDX14]
-	cfstr64		mvdx15, [r1, #CRUNCH_MVDX15]
-
-#ifdef __ARMEB__
-#error fix me for ARMEB
-#endif
-
-	cfmv32al	mvfx0, mvax0			@ save 72b accumulators
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX0L]
-	cfmv32am	mvfx0, mvax0
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX0M]
-	cfmv32ah	mvfx0, mvax0
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX0H]
-	cfmv32al	mvfx0, mvax1
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX1L]
-	cfmv32am	mvfx0, mvax1
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX1M]
-	cfmv32ah	mvfx0, mvax1
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX1H]
-	cfmv32al	mvfx0, mvax2
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX2L]
-	cfmv32am	mvfx0, mvax2
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX2M]
-	cfmv32ah	mvfx0, mvax2
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX2H]
-	cfmv32al	mvfx0, mvax3
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX3L]
-	cfmv32am	mvfx0, mvax3
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX3M]
-	cfmv32ah	mvfx0, mvax3
-	cfstr32		mvfx0, [r1, #CRUNCH_MVAX3H]
-
-	cfmv32sc	mvdx0, dspsc			@ save status word
-	cfstr64		mvdx0, [r1, #CRUNCH_DSPSC]
-
-	teq		r0, #0				@ anything to load?
-	cfldr64eq	mvdx0, [r1, #CRUNCH_MVDX0]	@ mvdx0 was clobbered
-	moveq		pc, lr
-
-crunch_load:
-	cfldr64		mvdx0, [r0, #CRUNCH_DSPSC]	@ load status word
-	cfmvsc32	dspsc, mvdx0
-
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX0L]	@ load 72b accumulators
-	cfmval32	mvax0, mvfx0
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX0M]
-	cfmvam32	mvax0, mvfx0
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX0H]
-	cfmvah32	mvax0, mvfx0
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX1L]
-	cfmval32	mvax1, mvfx0
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX1M]
-	cfmvam32	mvax1, mvfx0
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX1H]
-	cfmvah32	mvax1, mvfx0
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX2L]
-	cfmval32	mvax2, mvfx0
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX2M]
-	cfmvam32	mvax2, mvfx0
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX2H]
-	cfmvah32	mvax2, mvfx0
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX3L]
-	cfmval32	mvax3, mvfx0
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX3M]
-	cfmvam32	mvax3, mvfx0
-	cfldr32		mvfx0, [r0, #CRUNCH_MVAX3H]
-	cfmvah32	mvax3, mvfx0
-
-	cfldr64		mvdx0, [r0, #CRUNCH_MVDX0]	@ load 64b registers
-	cfldr64		mvdx1, [r0, #CRUNCH_MVDX1]
-	cfldr64		mvdx2, [r0, #CRUNCH_MVDX2]
-	cfldr64		mvdx3, [r0, #CRUNCH_MVDX3]
-	cfldr64		mvdx4, [r0, #CRUNCH_MVDX4]
-	cfldr64		mvdx5, [r0, #CRUNCH_MVDX5]
-	cfldr64		mvdx6, [r0, #CRUNCH_MVDX6]
-	cfldr64		mvdx7, [r0, #CRUNCH_MVDX7]
-	cfldr64		mvdx8, [r0, #CRUNCH_MVDX8]
-	cfldr64		mvdx9, [r0, #CRUNCH_MVDX9]
-	cfldr64		mvdx10, [r0, #CRUNCH_MVDX10]
-	cfldr64		mvdx11, [r0, #CRUNCH_MVDX11]
-	cfldr64		mvdx12, [r0, #CRUNCH_MVDX12]
-	cfldr64		mvdx13, [r0, #CRUNCH_MVDX13]
-	cfldr64		mvdx14, [r0, #CRUNCH_MVDX14]
-	cfldr64		mvdx15, [r0, #CRUNCH_MVDX15]
-
-	mov	pc, lr
-
-/*
- * Back up crunch regs to save area and disable access to them
- * (mainly for gdb or sleep mode usage)
- *
- * r0 = struct thread_info pointer of target task or NULL for any
- */
-ENTRY(crunch_task_disable)
-	stmfd	sp!, {r4, r5, lr}
-
-	mrs	ip, cpsr
-	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
-	msr	cpsr_c, r2
-
-	ldr	r4, =(EP93XX_APB_VIRT_BASE + 0x00130000)	@ syscon addr
-
-	ldr	r3, =crunch_owner
-	add	r2, r0, #TI_CRUNCH_STATE	@ get task crunch save area
-	ldr	r1, [r3]			@ get current crunch owner
-	teq	r1, #0				@ any current owner?
-	beq	1f				@ no: quit
-	teq	r0, #0				@ any owner?
-	teqne	r1, r2				@ or specified one?
-	bne	1f				@ no: quit
-
-	ldr	r5, [r4, #0x80]			@ enable access to crunch
-	mov	r2, #0xaa
-	str	r2, [r4, #0xc0]
-	orr	r5, r5, #0x00800000
-	str	r5, [r4, #0x80]
-
-	mov	r0, #0				@ nothing to load
-	str	r0, [r3]			@ no more current owner
-	ldr	r2, [r4, #0x80]			@ flush out enable (@@@)
-	mov	r2, r2
-	bl	crunch_save
-
-	mov	r2, #0xaa			@ disable access to crunch
-	str	r2, [r4, #0xc0]
-	bic	r5, r5, #0x00800000
-	str	r5, [r4, #0x80]
-	ldr	r5, [r4, #0x80]			@ flush out enable (@@@)
-	mov	r5, r5
-
-1:	msr	cpsr_c, ip			@ restore interrupt mode
-	ldmfd	sp!, {r4, r5, pc}
-
-/*
- * Copy crunch state to given memory address
- *
- * r0 = struct thread_info pointer of target task
- * r1 = memory address where to store crunch state
- *
- * this is called mainly in the creation of signal stack frames
- */
-ENTRY(crunch_task_copy)
-	mrs	ip, cpsr
-	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
-	msr	cpsr_c, r2
-
-	ldr	r3, =crunch_owner
-	add	r2, r0, #TI_CRUNCH_STATE	@ get task crunch save area
-	ldr	r3, [r3]			@ get current crunch owner
-	teq	r2, r3				@ does this task own it...
-	beq	1f
-
-	@ current crunch values are in the task save area
-	msr	cpsr_c, ip			@ restore interrupt mode
-	mov	r0, r1
-	mov	r1, r2
-	mov	r2, #CRUNCH_SIZE
-	b	memcpy
-
-1:	@ this task owns crunch regs -- grab a copy from there
-	mov	r0, #0				@ nothing to load
-	mov	r3, lr				@ preserve return address
-	bl	crunch_save
-	msr	cpsr_c, ip			@ restore interrupt mode
-	mov	pc, r3
-
-/*
- * Restore crunch state from given memory address
- *
- * r0 = struct thread_info pointer of target task
- * r1 = memory address where to get crunch state from
- *
- * this is used to restore crunch state when unwinding a signal stack frame
- */
-ENTRY(crunch_task_restore)
-	mrs	ip, cpsr
-	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
-	msr	cpsr_c, r2
-
-	ldr	r3, =crunch_owner
-	add	r2, r0, #TI_CRUNCH_STATE	@ get task crunch save area
-	ldr	r3, [r3]			@ get current crunch owner
-	teq	r2, r3				@ does this task own it...
-	beq	1f
-
-	@ this task doesn't own crunch regs -- use its save area
-	msr	cpsr_c, ip			@ restore interrupt mode
-	mov	r0, r2
-	mov	r2, #CRUNCH_SIZE
-	b	memcpy
-
-1:	@ this task owns crunch regs -- load them directly
-	mov	r0, r1
-	mov	r1, #0				@ nothing to save
-	mov	r3, lr				@ preserve return address
-	bl	crunch_load
-	msr	cpsr_c, ip			@ restore interrupt mode
-	mov	pc, r3
diff --git a/arch/arm/kernel/crunch.c b/arch/arm/kernel/crunch.c
deleted file mode 100644
index 25ef223..0000000
--- a/arch/arm/kernel/crunch.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * arch/arm/kernel/crunch.c
- * Cirrus MaverickCrunch context switching and handling
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh at wantstofly.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <mach/ep93xx-regs.h>
-#include <asm/thread_notify.h>
-
-struct crunch_state *crunch_owner;
-
-void crunch_task_release(struct thread_info *thread)
-{
-	local_irq_disable();
-	if (crunch_owner == &thread->crunchstate)
-		crunch_owner = NULL;
-	local_irq_enable();
-}
-
-static int crunch_enabled(u32 devcfg)
-{
-	return !!(devcfg & EP93XX_SYSCON_DEVCFG_CPENA);
-}
-
-static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t)
-{
-	struct thread_info *thread = (struct thread_info *)t;
-	struct crunch_state *crunch_state;
-	u32 devcfg;
-
-	crunch_state = &thread->crunchstate;
-
-	switch (cmd) {
-	case THREAD_NOTIFY_FLUSH:
-		memset(crunch_state, 0, sizeof(*crunch_state));
-
-		/*
-		 * FALLTHROUGH: Ensure we don't try to overwrite our newly
-		 * initialised state information on the first fault.
-		 */
-
-	case THREAD_NOTIFY_EXIT:
-		crunch_task_release(thread);
-		break;
-
-	case THREAD_NOTIFY_SWITCH:
-		devcfg = __raw_readl(EP93XX_SYSCON_DEVCFG);
-		if (crunch_enabled(devcfg) || crunch_owner == crunch_state) {
-			/*
-			 * We don't use ep93xx_syscon_swlocked_write() here
-			 * because we are on the context switch path and
-			 * preemption is already disabled.
-			 */
-			devcfg ^= EP93XX_SYSCON_DEVCFG_CPENA;
-			__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-			__raw_writel(devcfg, EP93XX_SYSCON_DEVCFG);
-		}
-		break;
-	}
-
-	return NOTIFY_DONE;
-}
-
-static struct notifier_block crunch_notifier_block = {
-	.notifier_call	= crunch_do,
-};
-
-static int __init crunch_init(void)
-{
-	thread_register_notifier(&crunch_notifier_block);
-	elf_hwcap |= HWCAP_CRUNCH;
-
-	return 0;
-}
-
-late_initcall(crunch_init);
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 574209d..0dc51f9 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -8,6 +8,9 @@ obj-			:=
 
 obj-$(CONFIG_EP93XX_DMA)	+= dma.o
 
+obj-$(CONFIG_CRUNCH)		+= crunch.o crunch-bits.o
+AFLAGS_crunch-bits.o		:= -Wa,-mcpu=ep9312
+
 obj-$(CONFIG_MACH_ADSSPHERE)	+= adssphere.o
 obj-$(CONFIG_MACH_EDB93XX)	+= edb93xx.o
 obj-$(CONFIG_MACH_GESBC9312)	+= gesbc9312.o
diff --git a/arch/arm/mach-ep93xx/crunch-bits.S b/arch/arm/mach-ep93xx/crunch-bits.S
new file mode 100644
index 0000000..0ec9bb4
--- /dev/null
+++ b/arch/arm/mach-ep93xx/crunch-bits.S
@@ -0,0 +1,305 @@
+/*
+ * arch/arm/kernel/crunch-bits.S
+ * Cirrus MaverickCrunch context switching and handling
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh at wantstofly.org>
+ *
+ * Shamelessly stolen from the iWMMXt code by Nicolas Pitre, which is
+ * Copyright (c) 2003-2004, MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/ptrace.h>
+#include <asm/thread_info.h>
+#include <asm/asm-offsets.h>
+#include <mach/ep93xx-regs.h>
+
+/*
+ * We can't use hex constants here due to a bug in gas.
+ */
+#define CRUNCH_MVDX0		0
+#define CRUNCH_MVDX1		8
+#define CRUNCH_MVDX2		16
+#define CRUNCH_MVDX3		24
+#define CRUNCH_MVDX4		32
+#define CRUNCH_MVDX5		40
+#define CRUNCH_MVDX6		48
+#define CRUNCH_MVDX7		56
+#define CRUNCH_MVDX8		64
+#define CRUNCH_MVDX9		72
+#define CRUNCH_MVDX10		80
+#define CRUNCH_MVDX11		88
+#define CRUNCH_MVDX12		96
+#define CRUNCH_MVDX13		104
+#define CRUNCH_MVDX14		112
+#define CRUNCH_MVDX15		120
+#define CRUNCH_MVAX0L		128
+#define CRUNCH_MVAX0M		132
+#define CRUNCH_MVAX0H		136
+#define CRUNCH_MVAX1L		140
+#define CRUNCH_MVAX1M		144
+#define CRUNCH_MVAX1H		148
+#define CRUNCH_MVAX2L		152
+#define CRUNCH_MVAX2M		156
+#define CRUNCH_MVAX2H		160
+#define CRUNCH_MVAX3L		164
+#define CRUNCH_MVAX3M		168
+#define CRUNCH_MVAX3H		172
+#define CRUNCH_DSPSC		176
+
+#define CRUNCH_SIZE		184
+
+	.text
+
+/*
+ * Lazy switching of crunch coprocessor context
+ *
+ * r10 = struct thread_info pointer
+ * r9  = ret_from_exception
+ * lr  = undefined instr exit
+ *
+ * called from prefetch exception handler with interrupts disabled
+ */
+ENTRY(crunch_task_enable)
+	ldr	r8, =(EP93XX_APB_VIRT_BASE + 0x00130000)	@ syscon addr
+
+	ldr	r1, [r8, #0x80]
+	tst	r1, #0x00800000			@ access to crunch enabled?
+	movne	pc, lr				@ if so no business here
+	mov	r3, #0xaa			@ unlock syscon swlock
+	str	r3, [r8, #0xc0]
+	orr	r1, r1, #0x00800000		@ enable access to crunch
+	str	r1, [r8, #0x80]
+
+	ldr	r3, =crunch_owner
+	add	r0, r10, #TI_CRUNCH_STATE	@ get task crunch save area
+	ldr	r2, [sp, #60]			@ current task pc value
+	ldr	r1, [r3]			@ get current crunch owner
+	str	r0, [r3]			@ this task now owns crunch
+	sub	r2, r2, #4			@ adjust pc back
+	str	r2, [sp, #60]
+
+	ldr	r2, [r8, #0x80]
+	mov	r2, r2				@ flush out enable (@@@)
+
+	teq	r1, #0				@ test for last ownership
+	mov	lr, r9				@ normal exit from exception
+	beq	crunch_load			@ no owner, skip save
+
+crunch_save:
+	cfstr64		mvdx0, [r1, #CRUNCH_MVDX0]	@ save 64b registers
+	cfstr64		mvdx1, [r1, #CRUNCH_MVDX1]
+	cfstr64		mvdx2, [r1, #CRUNCH_MVDX2]
+	cfstr64		mvdx3, [r1, #CRUNCH_MVDX3]
+	cfstr64		mvdx4, [r1, #CRUNCH_MVDX4]
+	cfstr64		mvdx5, [r1, #CRUNCH_MVDX5]
+	cfstr64		mvdx6, [r1, #CRUNCH_MVDX6]
+	cfstr64		mvdx7, [r1, #CRUNCH_MVDX7]
+	cfstr64		mvdx8, [r1, #CRUNCH_MVDX8]
+	cfstr64		mvdx9, [r1, #CRUNCH_MVDX9]
+	cfstr64		mvdx10, [r1, #CRUNCH_MVDX10]
+	cfstr64		mvdx11, [r1, #CRUNCH_MVDX11]
+	cfstr64		mvdx12, [r1, #CRUNCH_MVDX12]
+	cfstr64		mvdx13, [r1, #CRUNCH_MVDX13]
+	cfstr64		mvdx14, [r1, #CRUNCH_MVDX14]
+	cfstr64		mvdx15, [r1, #CRUNCH_MVDX15]
+
+#ifdef __ARMEB__
+#error fix me for ARMEB
+#endif
+
+	cfmv32al	mvfx0, mvax0			@ save 72b accumulators
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX0L]
+	cfmv32am	mvfx0, mvax0
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX0M]
+	cfmv32ah	mvfx0, mvax0
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX0H]
+	cfmv32al	mvfx0, mvax1
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX1L]
+	cfmv32am	mvfx0, mvax1
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX1M]
+	cfmv32ah	mvfx0, mvax1
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX1H]
+	cfmv32al	mvfx0, mvax2
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX2L]
+	cfmv32am	mvfx0, mvax2
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX2M]
+	cfmv32ah	mvfx0, mvax2
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX2H]
+	cfmv32al	mvfx0, mvax3
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX3L]
+	cfmv32am	mvfx0, mvax3
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX3M]
+	cfmv32ah	mvfx0, mvax3
+	cfstr32		mvfx0, [r1, #CRUNCH_MVAX3H]
+
+	cfmv32sc	mvdx0, dspsc			@ save status word
+	cfstr64		mvdx0, [r1, #CRUNCH_DSPSC]
+
+	teq		r0, #0				@ anything to load?
+	cfldr64eq	mvdx0, [r1, #CRUNCH_MVDX0]	@ mvdx0 was clobbered
+	moveq		pc, lr
+
+crunch_load:
+	cfldr64		mvdx0, [r0, #CRUNCH_DSPSC]	@ load status word
+	cfmvsc32	dspsc, mvdx0
+
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX0L]	@ load 72b accumulators
+	cfmval32	mvax0, mvfx0
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX0M]
+	cfmvam32	mvax0, mvfx0
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX0H]
+	cfmvah32	mvax0, mvfx0
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX1L]
+	cfmval32	mvax1, mvfx0
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX1M]
+	cfmvam32	mvax1, mvfx0
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX1H]
+	cfmvah32	mvax1, mvfx0
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX2L]
+	cfmval32	mvax2, mvfx0
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX2M]
+	cfmvam32	mvax2, mvfx0
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX2H]
+	cfmvah32	mvax2, mvfx0
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX3L]
+	cfmval32	mvax3, mvfx0
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX3M]
+	cfmvam32	mvax3, mvfx0
+	cfldr32		mvfx0, [r0, #CRUNCH_MVAX3H]
+	cfmvah32	mvax3, mvfx0
+
+	cfldr64		mvdx0, [r0, #CRUNCH_MVDX0]	@ load 64b registers
+	cfldr64		mvdx1, [r0, #CRUNCH_MVDX1]
+	cfldr64		mvdx2, [r0, #CRUNCH_MVDX2]
+	cfldr64		mvdx3, [r0, #CRUNCH_MVDX3]
+	cfldr64		mvdx4, [r0, #CRUNCH_MVDX4]
+	cfldr64		mvdx5, [r0, #CRUNCH_MVDX5]
+	cfldr64		mvdx6, [r0, #CRUNCH_MVDX6]
+	cfldr64		mvdx7, [r0, #CRUNCH_MVDX7]
+	cfldr64		mvdx8, [r0, #CRUNCH_MVDX8]
+	cfldr64		mvdx9, [r0, #CRUNCH_MVDX9]
+	cfldr64		mvdx10, [r0, #CRUNCH_MVDX10]
+	cfldr64		mvdx11, [r0, #CRUNCH_MVDX11]
+	cfldr64		mvdx12, [r0, #CRUNCH_MVDX12]
+	cfldr64		mvdx13, [r0, #CRUNCH_MVDX13]
+	cfldr64		mvdx14, [r0, #CRUNCH_MVDX14]
+	cfldr64		mvdx15, [r0, #CRUNCH_MVDX15]
+
+	mov	pc, lr
+
+/*
+ * Back up crunch regs to save area and disable access to them
+ * (mainly for gdb or sleep mode usage)
+ *
+ * r0 = struct thread_info pointer of target task or NULL for any
+ */
+ENTRY(crunch_task_disable)
+	stmfd	sp!, {r4, r5, lr}
+
+	mrs	ip, cpsr
+	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
+	msr	cpsr_c, r2
+
+	ldr	r4, =(EP93XX_APB_VIRT_BASE + 0x00130000)	@ syscon addr
+
+	ldr	r3, =crunch_owner
+	add	r2, r0, #TI_CRUNCH_STATE	@ get task crunch save area
+	ldr	r1, [r3]			@ get current crunch owner
+	teq	r1, #0				@ any current owner?
+	beq	1f				@ no: quit
+	teq	r0, #0				@ any owner?
+	teqne	r1, r2				@ or specified one?
+	bne	1f				@ no: quit
+
+	ldr	r5, [r4, #0x80]			@ enable access to crunch
+	mov	r2, #0xaa
+	str	r2, [r4, #0xc0]
+	orr	r5, r5, #0x00800000
+	str	r5, [r4, #0x80]
+
+	mov	r0, #0				@ nothing to load
+	str	r0, [r3]			@ no more current owner
+	ldr	r2, [r4, #0x80]			@ flush out enable (@@@)
+	mov	r2, r2
+	bl	crunch_save
+
+	mov	r2, #0xaa			@ disable access to crunch
+	str	r2, [r4, #0xc0]
+	bic	r5, r5, #0x00800000
+	str	r5, [r4, #0x80]
+	ldr	r5, [r4, #0x80]			@ flush out enable (@@@)
+	mov	r5, r5
+
+1:	msr	cpsr_c, ip			@ restore interrupt mode
+	ldmfd	sp!, {r4, r5, pc}
+
+/*
+ * Copy crunch state to given memory address
+ *
+ * r0 = struct thread_info pointer of target task
+ * r1 = memory address where to store crunch state
+ *
+ * this is called mainly in the creation of signal stack frames
+ */
+ENTRY(crunch_task_copy)
+	mrs	ip, cpsr
+	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
+	msr	cpsr_c, r2
+
+	ldr	r3, =crunch_owner
+	add	r2, r0, #TI_CRUNCH_STATE	@ get task crunch save area
+	ldr	r3, [r3]			@ get current crunch owner
+	teq	r2, r3				@ does this task own it...
+	beq	1f
+
+	@ current crunch values are in the task save area
+	msr	cpsr_c, ip			@ restore interrupt mode
+	mov	r0, r1
+	mov	r1, r2
+	mov	r2, #CRUNCH_SIZE
+	b	memcpy
+
+1:	@ this task owns crunch regs -- grab a copy from there
+	mov	r0, #0				@ nothing to load
+	mov	r3, lr				@ preserve return address
+	bl	crunch_save
+	msr	cpsr_c, ip			@ restore interrupt mode
+	mov	pc, r3
+
+/*
+ * Restore crunch state from given memory address
+ *
+ * r0 = struct thread_info pointer of target task
+ * r1 = memory address where to get crunch state from
+ *
+ * this is used to restore crunch state when unwinding a signal stack frame
+ */
+ENTRY(crunch_task_restore)
+	mrs	ip, cpsr
+	orr	r2, ip, #PSR_I_BIT		@ disable interrupts
+	msr	cpsr_c, r2
+
+	ldr	r3, =crunch_owner
+	add	r2, r0, #TI_CRUNCH_STATE	@ get task crunch save area
+	ldr	r3, [r3]			@ get current crunch owner
+	teq	r2, r3				@ does this task own it...
+	beq	1f
+
+	@ this task doesn't own crunch regs -- use its save area
+	msr	cpsr_c, ip			@ restore interrupt mode
+	mov	r0, r2
+	mov	r2, #CRUNCH_SIZE
+	b	memcpy
+
+1:	@ this task owns crunch regs -- load them directly
+	mov	r0, r1
+	mov	r1, #0				@ nothing to save
+	mov	r3, lr				@ preserve return address
+	bl	crunch_load
+	msr	cpsr_c, ip			@ restore interrupt mode
+	mov	pc, r3
diff --git a/arch/arm/mach-ep93xx/crunch.c b/arch/arm/mach-ep93xx/crunch.c
new file mode 100644
index 0000000..25ef223
--- /dev/null
+++ b/arch/arm/mach-ep93xx/crunch.c
@@ -0,0 +1,88 @@
+/*
+ * arch/arm/kernel/crunch.c
+ * Cirrus MaverickCrunch context switching and handling
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh at wantstofly.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <mach/ep93xx-regs.h>
+#include <asm/thread_notify.h>
+
+struct crunch_state *crunch_owner;
+
+void crunch_task_release(struct thread_info *thread)
+{
+	local_irq_disable();
+	if (crunch_owner == &thread->crunchstate)
+		crunch_owner = NULL;
+	local_irq_enable();
+}
+
+static int crunch_enabled(u32 devcfg)
+{
+	return !!(devcfg & EP93XX_SYSCON_DEVCFG_CPENA);
+}
+
+static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t)
+{
+	struct thread_info *thread = (struct thread_info *)t;
+	struct crunch_state *crunch_state;
+	u32 devcfg;
+
+	crunch_state = &thread->crunchstate;
+
+	switch (cmd) {
+	case THREAD_NOTIFY_FLUSH:
+		memset(crunch_state, 0, sizeof(*crunch_state));
+
+		/*
+		 * FALLTHROUGH: Ensure we don't try to overwrite our newly
+		 * initialised state information on the first fault.
+		 */
+
+	case THREAD_NOTIFY_EXIT:
+		crunch_task_release(thread);
+		break;
+
+	case THREAD_NOTIFY_SWITCH:
+		devcfg = __raw_readl(EP93XX_SYSCON_DEVCFG);
+		if (crunch_enabled(devcfg) || crunch_owner == crunch_state) {
+			/*
+			 * We don't use ep93xx_syscon_swlocked_write() here
+			 * because we are on the context switch path and
+			 * preemption is already disabled.
+			 */
+			devcfg ^= EP93XX_SYSCON_DEVCFG_CPENA;
+			__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+			__raw_writel(devcfg, EP93XX_SYSCON_DEVCFG);
+		}
+		break;
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block crunch_notifier_block = {
+	.notifier_call	= crunch_do,
+};
+
+static int __init crunch_init(void)
+{
+	thread_register_notifier(&crunch_notifier_block);
+	elf_hwcap |= HWCAP_CRUNCH;
+
+	return 0;
+}
+
+late_initcall(crunch_init);
-- 
1.7.0.4



From paul at pwsan.com  Fri Mar  9 22:48:40 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 9 Mar 2012 20:48:40 -0700 (MST)
Subject: [PATCHv5 1/6] ARM: OMAP3 PM: correct enable/disable of daisy io
 chain
In-Reply-To: <1331046702-2472-2-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-2-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203092047410.30879@utopia.booyaka.com>

Hi

On Tue, 6 Mar 2012, Tero Kristo wrote:

> From: Mohan V <mohanv at ti.com>
> 
> Currently the enabling and disabling of IO Daisy chain is not
> according to the TRM. The below steps are followed to enable/
> disable the IO chain according to the "Sec 3.5.7.2.2
> I/O Wake-Up Mechanism" in OMAP3630 Public TRM[1].
> 
> Steps to enable IO chain:
> [a] Set PM_WKEN_WKUP.EN_IO bit
> [b] Set the PM_WKEN_WKUP.EN_IO_CHAIN bit
> [c] Poll for PM_WKST_WKUP.ST_IO_CHAIN.
> [d] When ST_IO_CHAIN bit set to 1, clear PM_WKEN_WKUP.EN_IO_CHAIN
> [e] Clear ST_IO_CHAIN bit.
> 
> Steps to disable IO chain:
> [a] Clear PM_WKEN_WKUP.EN_IO_CHAIN bit
> [b] Clear PM_WKEN_WKUP.EN_IO bit
> [c] Clear PM_WKST_WKUP.ST_IO bit by writing 1 to it.
> 
> Step [e] & [c] in each case can be skipped, as these are handled
> by the PRCM interrupt handler later.
> 
> [1] http://focus.ti.com/pdfs/wtbu/OMAP36xx_ES1.x_PUBLIC_TRM_vV.zip
> 
> Signed-off-by: Mohan V <mohanv at ti.com>
> Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
> Reviewed-by: Rajendra Nayak <rnayak at ti.com>

I modified the commit message to better reflect the reality of what's in 
the TRM.  Updated version is below.


- Paul

From: Mohan V <mohanv at ti.com>
Date: Fri, 2 Mar 2012 17:17:50 +0200
Subject: [PATCH 1/6] ARM: OMAP3: PM: correct enable/disable of daisy io chain

Currently the enabling and disabling of IO Daisy chain is not
according to the TRM. The below steps are followed to enable/
disable the IO chain, based loosely on the "Sec 3.5.7.2.2
I/O Wake-Up Mechanism" section in OMAP3630 Public TRM[1].

Steps to enable IO chain:
[a] Set PM_WKEN_WKUP.EN_IO bit
[b] Set the PM_WKEN_WKUP.EN_IO_CHAIN bit
[c] Poll for PM_WKST_WKUP.ST_IO_CHAIN.
[d] When ST_IO_CHAIN bit set to 1, clear PM_WKEN_WKUP.EN_IO_CHAIN
[e] Clear ST_IO_CHAIN bit.

Steps to disable IO chain:
[a] Clear PM_WKEN_WKUP.EN_IO_CHAIN bit
[b] Clear PM_WKEN_WKUP.EN_IO bit
[c] Clear PM_WKST_WKUP.ST_IO bit by writing 1 to it.

Step [e] & [c] in each case can be skipped, as these are handled
by the PRCM interrupt handler later.

[1] http://focus.ti.com/pdfs/wtbu/OMAP36xx_ES1.x_PUBLIC_TRM_vV.zip

Signed-off-by: Mohan V <mohanv at ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
[paul at pwsan.com: modified commit message to clarify that these steps are
 based loosely on the TRM section, rather than documented exactly]
Reviewed-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/pm34xx.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc69875..b0821a8 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -94,16 +94,17 @@ static void omap3_enable_io_chain(void)
 	/* Do a readback to assure write has been done */
 	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 
-	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
+	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
 		 OMAP3430_ST_IO_CHAIN_MASK)) {
 		timeout++;
 		if (timeout > 1000) {
 			pr_err("Wake up daisy chain activation failed.\n");
 			return;
 		}
-		omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
-					   WKUP_MOD, PM_WKEN);
 	}
+	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+			PM_WKEN);
+
 }
 
 static void omap3_disable_io_chain(void)
-- 
1.7.9.1



From paul at pwsan.com  Fri Mar  9 23:00:35 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 9 Mar 2012 21:00:35 -0700 (MST)
Subject: [PATCHv5 4/6] ARM: OMAP3+: PRM: Enable IO wake up
In-Reply-To: <1331046702-2472-5-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-5-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203092100060.30879@utopia.booyaka.com>

On Tue, 6 Mar 2012, Tero Kristo wrote:

> Enable IO Wake up for OMAP3/4 as part of PRM Init. Currently this has been
> managed in cpuidle path which is not the right place. Subsequent patch
> will remove IO Daisy chain handling in cpuidle path once daisy chain is
> handled as part of hwmod mux. This patch also moves the OMAP4 IO wakeup
> enable code from the trigger function to init time setup.
> 
> Signed-off-by: Tero Kristo <t-kristo at ti.com>
> Reviewed-by: Rajendra Nayak <rnayak at ti.com>

Here's an updated version of this patch.  Please let me know if you have 
any comments.

- Paul

From: Tero Kristo <t-kristo at ti.com>
Date: Fri, 2 Mar 2012 17:17:53 +0200
Subject: [PATCH 4/6] ARM: OMAP3+: PRM: Enable IO wake up

Enable IO Wake up for OMAP3/4 as part of PRM Init. Currently this has been
managed in cpuidle path which is not the right place. Subsequent patch
will remove IO Daisy chain handling in cpuidle path once daisy chain is
handled as part of hwmod mux. This patch also moves the OMAP4 IO wakeup
enable code from the trigger function to init time setup.

Signed-off-by: Tero Kristo <t-kristo at ti.com>
[paul at pwsan.com: harmonize function names with other PRM functions; add
 kerneldoc]
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/prm2xxx_3xxx.c |   20 +++++++++++++++++++-
 arch/arm/mach-omap2/prm44xx.c      |   26 ++++++++++++++++++--------
 2 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 7d62bd6..1471a33 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -332,10 +332,28 @@ void omap3xxx_prm_reconfigure_io_chain(void)
 	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
 }
 
+/**
+ * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
+ *
+ * Activates the I/O wakeup event latches and allows events logged by
+ * those latches to signal a wakeup event to the PRCM.  For I/O
+ * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
+ * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
+ * No return value.
+ */
+static void __init omap3xxx_prm_enable_io_wakeup(void)
+{
+	if (omap3_has_io_wakeup())
+		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+					   PM_WKEN);
+}
+
 static int __init omap3xxx_prcm_init(void)
 {
-	if (cpu_is_omap34xx())
+	if (cpu_is_omap34xx()) {
+		omap3xxx_prm_enable_io_wakeup();
 		return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
+	}
 	return 0;
 }
 subsys_initcall(omap3xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 5868a12..af251c7 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -244,13 +244,6 @@ void omap44xx_prm_reconfigure_io_chain(void)
 {
 	int i = 0;
 
-	/* Enable GLOBAL_WUEN */
-	if (!(omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
-		OMAP4_PRM_IO_PMCTRL_OFFSET) & OMAP4430_GLOBAL_WUEN_MASK))
-		omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
-			OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_PRM_DEVICE_INST,
-			OMAP4_PRM_IO_PMCTRL_OFFSET);
-
 	/* Trigger WUCLKIN enable */
 	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
 			OMAP4430_WUCLK_CTRL_MASK, OMAP4430_PRM_DEVICE_INST,
@@ -279,10 +272,27 @@ void omap44xx_prm_reconfigure_io_chain(void)
 	return;
 }
 
+/**
+ * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
+ *
+ * Activates the I/O wakeup event latches and allows events logged by
+ * those latches to signal a wakeup event to the PRCM.  For I/O wakeups
+ * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
+ * omap44xx_prm_reconfigure_io_chain() must be called.  No return value.
+ */
+static void __init omap44xx_prm_enable_io_wakeup(void)
+{
+	omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
+			OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET);
+}
+
 static int __init omap4xxx_prcm_init(void)
 {
-	if (cpu_is_omap44xx())
+	if (cpu_is_omap44xx()) {
+		omap44xx_prm_enable_io_wakeup();
 		return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+	}
 	return 0;
 }
 subsys_initcall(omap4xxx_prcm_init);
-- 
1.7.9.1



From paul at pwsan.com  Fri Mar  9 13:02:15 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 9 Mar 2012 11:02:15 -0700 (MST)
Subject: [PATCH] ARM: OMAP4: clock: Add aliases for McBSP fclk clocks
In-Reply-To: <20120309180027.GF12083@atomide.com>
References: <1331024133-18201-1-git-send-email-peter.ujfalusi@ti.com>
 <4F5A258F.8050704@ti.com> <20120309180027.GF12083@atomide.com>
Message-ID: <alpine.DEB.2.00.1203091101400.7039@utopia.booyaka.com>

On Fri, 9 Mar 2012, Tony Lindgren wrote:

> * Peter Ujfalusi <peter.ujfalusi at ti.com> [120309 07:47]:
> > Hi Paul, Tony,
> > 
> > On 03/06/2012 10:55 AM, Peter Ujfalusi wrote:
> > > CLKS signal for McBSP ports can be selected from internal (PRCM) or external
> > > (ABE_CLKS pin) source.
> > > To be able to use existing code we need to create clock aliases consistent
> > > among OMAP2/3/4.
> > 
> > Would you be able to take a look at this patch?
> 
> To me this looks safe to merge via ASoC tree, assuming Paul
> acks it too, and it does not cause merge conflicts with
> Paul's changes:
> 
> Acked-by: Tony Lindgren <tony at atomide.com>

Please let's not merge this one yet.  It should not be necessary to change 
the clkdev aliases, this change should occur in the hwmod code.


- Paul


From arnd at arndb.de  Sun Mar 11 13:52:32 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 11 Mar 2012 17:52:32 +0000
Subject: [PATCH 2/2] ARM: kirkwood: Convert orion-nand to fdt
In-Reply-To: <1331476406-9844-3-git-send-email-jm@lentin.co.uk>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <1331476406-9844-3-git-send-email-jm@lentin.co.uk>
Message-ID: <201203111752.32497.arnd@arndb.de>

On Sunday 11 March 2012, Jamie Lentin wrote:
> The DNS-320 and 325 have a NAND partitioned to store uboot, uimage and root
> filesystem. Store this information in devicetree.

All the important parts  look good to me, just two small details:

> -	board = pdev->dev.platform_data;
> +	if (pdev->dev.of_node) {
> +		board = kzalloc(sizeof(struct orion_nand_data), GFP_KERNEL);
> +		if (!board) {
> +			printk(KERN_ERR "orion_nand: failed to allocate board structure.\n");
> +			ret = -ENOMEM;
> +			goto no_res;
> +		}
> +		if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
> +			board->cle = (u8)val;
> +		if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
> +			board->ale = (u8)val;
> +		if (!of_property_read_u32(pdev->dev.of_node, "width", &val))
> +			board->width = (u8)val;
> +		if (!of_property_read_u32(pdev->dev.of_node,
> +						"chip-delay", &val))
> +			board->chip_delay = (u8)val;
> +	} else
> +		board = pdev->dev.platform_data;

If you use devm_kzalloc, the memory will get freed automatically during cleanup.
  
> +#ifdef CONFIG_OF
> +static struct of_device_id orion_nand_of_match_table[] = {
> +	{ .compatible = "mrvl,orion-nand", },
> +	{},
> +};
> +#else
> +#define orion_nand_of_match_table NULL
> +#endif
> +
>  static struct platform_driver orion_nand_driver = {
>  	.remove		= __devexit_p(orion_nand_remove),
>  	.driver		= {
>  		.name	= "orion_nand",
>  		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(orion_nand_of_match_table),
>  	},
>  };

When you use of_match_ptr(), you can leave out the "#else\n#define orion_nand_of_match_table NULL".

	Arnd


From broonie at opensource.wolfsonmicro.com  Fri Mar  9 06:53:31 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 11:53:31 +0000
Subject: [PATCH v3 08/11] ASoC: fsl: make fsl_ssi driver compilable on
 ARM/IMX
In-Reply-To: <20120309032128.GK2499@S2101-09.ap.freescale.net>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-9-git-send-email-shawn.guo@linaro.org>
 <4F5912D0.2090800@freescale.com>
 <20120309012653.GG2499@S2101-09.ap.freescale.net>
 <4F596674.5030405@freescale.com>
 <20120309032128.GK2499@S2101-09.ap.freescale.net>
Message-ID: <20120309115327.GD3273@opensource.wolfsonmicro.com>

On Fri, Mar 09, 2012 at 11:21:31AM +0800, Shawn Guo wrote:
> On Fri, Mar 09, 2012 at 02:09:57AM +0000, Tabi Timur-B04825 wrote:

> > That's the general idea, but I think it needs more study.  I don't 
> > consider this to be a bug that needs to be fixed ASAP, since it's never 
> > been an actual problem so far.  For instance, do we need to protect 
> > between hw_params and _trigger?

Yes, the capture and playback streams may run in parallel.

> Ok, I will leave it to you with a big "FIXME" comment then.

You probably just need a read/modify/write function to do the locking in
the style of update_bits().
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From paul at pwsan.com  Fri Mar  9 23:01:52 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 9 Mar 2012 21:01:52 -0700 (MST)
Subject: [PATCHv5 5/6] ARM: OMAP3PLUS PM: Add IO Daisychain support via
 hwmod mux
In-Reply-To: <1331046702-2472-6-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-6-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203092100390.30879@utopia.booyaka.com>

Hi

On Tue, 6 Mar 2012, Tero Kristo wrote:

> From: Vishwanath BS <vishwanath.bs at ti.com>
> 
> IO Daisychain feature has to be triggered whenever there is a change in
> device's mux configuration (See section 3.9.4 in OMAP4 Public TRM vP).
> 
> Now devices can idle independent of the powerdomain, there can be a
> window where device is idled and corresponding powerdomain can be
> ON/INACTIVE state. In such situations, since both module wake up is
> enabled at padlevel as well as io daisychain sequence is triggered,
> there will be 2 PRCM interrupts (Module async wake up via swakeup and
> IO Pad interrupt). But as PRCM Interrupt handler clears the Module
> Padlevel WKST bit in the first interrupt, module specific interrupt
> handler will not triggered for the second time
> 
> Also look at detailed explanation given by Rajendra at
> http://www.spinics.net/lists/linux-serial/msg04480.html
> 
> Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
> Signed-off-by: Tero Kristo <t-kristo at ti.com>

Here's an updated version of this patch that removes the dependency on 
mach-omap2/pm.*.


- Paul

From: Vishwanath BS <vishwanath.bs at ti.com>
Date: Fri, 2 Mar 2012 17:17:54 +0200
Subject: [PATCH 5/6] ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during
 hwmod mux

IO Daisychain feature has to be triggered whenever there is a change in
device's mux configuration (See section 3.9.4 in OMAP4 Public TRM vP).

Now devices can idle independent of the powerdomain, there can be a
window where device is idled and corresponding powerdomain can be
ON/INACTIVE state. In such situations, since both module wake up is
enabled at padlevel as well as io daisychain sequence is triggered,
there will be 2 PRCM interrupts (Module async wake up via swakeup and
IO Pad interrupt). But as PRCM Interrupt handler clears the Module
Padlevel WKST bit in the first interrupt, module specific interrupt
handler will not triggered for the second time

Also look at detailed explanation given by Rajendra at
http://www.spinics.net/lists/linux-serial/msg04480.html

Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
[paul at pwsan.com: remove dependency on pm.c & pm.h; add kerneldoc]
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   37 +++++++++++++++++++++++++++++++++++--
 1 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index eba6cd3..58a5920 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -152,6 +152,7 @@
 #include "prm44xx.h"
 #include "prminst44xx.h"
 #include "mux.h"
+#include "pm.h"
 
 /* Maximum microseconds to wait for OMAP module to softreset */
 #define MAX_MODULE_SOFTRESET_WAIT	10000
@@ -165,6 +166,8 @@ static LIST_HEAD(omap_hwmod_list);
 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
 static struct omap_hwmod *mpu_oh;
 
+/* io_chain_lock: used to serialize reconfigurations of the I/O chain */
+static DEFINE_SPINLOCK(io_chain_lock);
 
 /* Private functions */
 
@@ -1481,6 +1484,32 @@ static int _reset(struct omap_hwmod *oh)
 }
 
 /**
+ * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain
+ *
+ * Call the appropriate PRM function to clear any logged I/O chain
+ * wakeups and to reconfigure the chain.  This apparently needs to be
+ * done upon every mux change.  Since hwmods can be concurrently
+ * enabled and idled, hold a spinlock around the I/O chain
+ * reconfiguration sequence.  No return value.
+ *
+ * XXX When the PRM code is moved to drivers, this function can be removed,
+ * as the PRM infrastructure should abstract this.
+ */
+static void _reconfigure_io_chain(void)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&io_chain_lock, flags);
+
+	if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl())
+		omap3xxx_prm_reconfigure_io_chain();
+	else if (cpu_is_omap44xx())
+		omap44xx_prm_reconfigure_io_chain();
+
+	spin_unlock_irqrestore(&io_chain_lock, flags);
+}
+
+/**
  * _enable - enable an omap_hwmod
  * @oh: struct omap_hwmod *
  *
@@ -1535,8 +1564,10 @@ static int _enable(struct omap_hwmod *oh)
 	/* Mux pins for device runtime if populated */
 	if (oh->mux && (!oh->mux->enabled ||
 			((oh->_state == _HWMOD_STATE_IDLE) &&
-			 oh->mux->pads_dynamic)))
+			 oh->mux->pads_dynamic))) {
 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+		_reconfigure_io_chain();
+	}
 
 	_add_initiator_dep(oh, mpu_oh);
 
@@ -1622,8 +1653,10 @@ static int _idle(struct omap_hwmod *oh)
 		clkdm_hwmod_disable(oh->clkdm, oh);
 
 	/* Mux pins for device idle if populated */
-	if (oh->mux && oh->mux->pads_dynamic)
+	if (oh->mux && oh->mux->pads_dynamic) {
 		omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+		_reconfigure_io_chain();
+	}
 
 	oh->_state = _HWMOD_STATE_IDLE;
 
-- 
1.7.9.1



From broonie at opensource.wolfsonmicro.com  Mon Mar 12 12:12:18 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 12 Mar 2012 16:12:18 +0000
Subject: [PATCH 5/5] mmc: sdhci-s3c: setup pins using pinctrl interface
In-Reply-To: <CAJuYYwQ=vhcrbH3gsMBuLG1D_p=mx_RFbN86+ETPT4bLYrRgEA@mail.gmail.com>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
 <20120312142143.GC14020@sirena.org.uk>
 <CAJuYYwQ=vhcrbH3gsMBuLG1D_p=mx_RFbN86+ETPT4bLYrRgEA@mail.gmail.com>
Message-ID: <20120312161218.GK3110@opensource.wolfsonmicro.com>

On Mon, Mar 12, 2012 at 08:01:34PM +0530, Thomas Abraham wrote:

> Yes, I agree with your comment. I did refer to manuals of s3c24xx to
> Exynos to ensure that the samsung pinctrl driver is generic and
> reusable on all samsung soc's. I hope I have not missed out something
> important that would require additional tweaks in the samsung pinctrl
> driver. The missing bits now are gpio interrupt and wakeup interrupt
> support in the samsung pinctrl driver. Once that is complete, I
> believe it should be easy to add support for other SoC and convert the
> drivers to use pinctrl (other option being to let pinctrl driver hog
> all the mappings at boot and remove the cfg_gpio platform callbacks
> from the driver).

Yes, I don't see any fundamental problems here - it's more that either
we'll need to get all the SoCs converted over (which is a lot of work)
or we'll need to have drivers be able to cope with running either way.
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From paul at pwsan.com  Fri Mar  9 11:55:18 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 9 Mar 2012 09:55:18 -0700 (MST)
Subject: [PATCH 5/9] ARM: OMAP36xx: hwmod data: fix SmartReflex interface
 data
In-Reply-To: <CAORVsuV8YXNRF=UjBOd8hoYbJ+ksg6RT1dZYC=TuUTmLiuD+ow@mail.gmail.com>
References: <20120228110943.808.73639.stgit@dusk>
 <20120228111054.808.16941.stgit@dusk>
 <alpine.DEB.2.00.1203082051150.26656@utopia.booyaka.com>
 <CAORVsuV8YXNRF=UjBOd8hoYbJ+ksg6RT1dZYC=TuUTmLiuD+ow@mail.gmail.com>
Message-ID: <alpine.DEB.2.00.1203090949130.17504@utopia.booyaka.com>

Hi

On Fri, 9 Mar 2012, Jean Pihet wrote:

> On Fri, Mar 9, 2012 at 4:51 AM, Paul Walmsley <paul at pwsan.com> wrote:
> >
> > Dropping this patch from this series due to conflicts with the SmartReflex
> > branch. ?It will be moved to a subsequent series.
> I can take this change as part of the series I am preparing for the SR
> conversion to drivers/.
> What do you thin?

I've already included it as part of another pull request...


- Paul

From broonie at opensource.wolfsonmicro.com  Mon Mar 12 10:32:11 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 12 Mar 2012 14:32:11 +0000
Subject: [PATCH 11/11] ARM: tegra: pcie: Add device tree support
In-Reply-To: <20120312142857.GA6694@avionic-0098.mockup.avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-12-git-send-email-thierry.reding@avionic-design.de>
 <4F59253D.7070100@wwwdotorg.org>
 <20120312120610.GA14020@sirena.org.uk>
 <20120312141705.GA16395@avionic-0098.mockup.avionic-design.de>
 <20120312142340.GI3110@opensource.wolfsonmicro.com>
 <20120312142857.GA6694@avionic-0098.mockup.avionic-design.de>
Message-ID: <20120312143210.GJ3110@opensource.wolfsonmicro.com>

On Mon, Mar 12, 2012 at 03:28:58PM +0100, Thierry Reding wrote:

> In that case I'll mark the *-supply properties required. Would it be a good
> idea to mention this (or even give an example with fixed regulators) in the
> binding documentation or can I assume this to be common knowledge?

Probably the best thing here is to just reference the regulator binding
documentation which mentions -supply properties (or should do) and then
clarify that if need be.  No sense in putting things like this into the
binding document for a specific driver, there's nothing driver specific.
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From arnd at arndb.de  Sat Mar 10 14:24:31 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 10 Mar 2012 19:24:31 +0000
Subject: [PATCH 1/2] ARM: at91: only RM9200 has ISA-style PIO
In-Reply-To: <1331405075-3231-1-git-send-email-alan@signal11.us>
References: <1331405049-3186-1-git-send-email-alan@signal11.us>
 <1331405075-3231-1-git-send-email-alan@signal11.us>
Message-ID: <201203101924.31710.arnd@arndb.de>

On Saturday 10 March 2012, Alan Ott wrote:
> 
> From: Arnd Bergmann <arnd at arndb.de>
> 
> Most at91 systems have no support for PCMCIA or other
> PC-style buses, so we can select NO_IOPORT in order to
> disable compilationf or all drivers that need these.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Alan Ott <alan at signal11.us>

Hi Alan,

You forgot to Cc the at91 maintainers on this patch (and on patch 0).
Also, this patch relies on the another series I did to redefine
the meaning of CONFIG_NO_IOPORT while renaming the existing one to
CONFIG_NO_IOPORT_MAP. This patch will have to wait for the other
series.

	Arnd


From arnd at arndb.de  Fri Mar  9 06:50:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 9 Mar 2012 11:50:11 +0000
Subject: linux-next: manual merge of the arm-soc tree with the omap_dss2
 tree
In-Reply-To: <1331285751.1927.20.camel@deskari>
References: <20120308170048.f1a992bca2ca2d93fa9747bf@canb.auug.org.au>
 <201203081616.12510.arnd@arndb.de> <1331285751.1927.20.camel@deskari>
Message-ID: <201203091150.11294.arnd@arndb.de>

On Friday 09 March 2012, Tomi Valkeinen wrote:
> On Thu, 2012-03-08 at 16:16 +0000, Arnd Bergmann wrote:
> > On Thursday 08 March 2012, Stephen Rothwell wrote:
> > > Hi all,
> > > 
> > > Today's linux-next merge of the arm-soc tree got a conflict in
> > > arch/arm/mach-omap1/board-palmtt.c between commit ddba6c7f7ec6 ("OMAP1:
> > > pass LCD config with omapfb_set_lcd_config()") from the omap_dss2 tree
> > > and commit 2e3ee9f45b3c ("ARM: OMAP1: Move most of plat/io.h into local
> > > iomap.h") from the arm-soc tree.
> > > 
> > > I fixed it up (see below) and can carry the fix as necessary.
> > 
> > Hi Stephen,
> > 
> > Thanks for fixing up all the conflicts between arm-soc and omap_dss2.
> > I think we should make sure they are resolved in one of the trees before
> > the merge window.
> 
> Do we need to? The conflicts seemed to be trivial ones, like arm-soc
> adds/removes something that just happens to be next to something else
> that I add/remove.
> 
> My understanding is that it's better to leave those conflicts than to do
> "trickery" to avoid them.

Each of the conflicts is simple enough, but I feel it's worth resolving
them in this case because there are a number of them. Looking at them
again now, it's probably ok either way -- resolving them now or letting
Linus take care of them.

> > Tomi, what are your plans for the omap_dss2 branch to get merged?
> 
> Normally my tree goes via fbdev-tree (Florian's tree) to mainline.

ok.

> > Do you think you should send it to Linus first and we merge it into
> > arm-soc to resolve the conflicts?
> > Or do you want to merge it through the arm-soc tree?
> > Or should we go first and you fix up the conflicts by pulling in the
> > necessary topic branches from arm-soc into your tree?
> 
> If we want to resolve the conflicts, perhaps it's simplest if the dss
> tree is merged to arm-soc.

Ok. Maybe we'll just merge them in case Florian is upstream faster and
not merge them otherwise.

	Arnd


From paul at pwsan.com  Fri Mar  9 22:59:25 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 9 Mar 2012 20:59:25 -0700 (MST)
Subject: [PATCHv5 3/6] ARM: OMAP4 PM: Add IO Daisychain support
In-Reply-To: <1331046702-2472-4-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-4-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203092051140.30879@utopia.booyaka.com>

Hi

On Tue, 6 Mar 2012, Tero Kristo wrote:

> From: Rajendra Nayak <rnayak at ti.com>
> 
> IO daisychain is a mechanism that allows individual IO pads to generate
> wakeup events on their own based on a switch of an input signal level.
> This allows the hardware module behind the pad to be powered down, but
> still have device level capability to detect IO events, and once this
> happens the module can be powered back up to resume IO. See section
> 3.9.4 in OMAP4430 Public TRM for details.
> 
> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
> Signed-off-by: Tero Kristo <t-kristo at ti.com>

Here's an updated version of this patch.  Please let me know if you think 
we should remove the poll on the WUCLKOUT line to conform with the change 
that Tero made to the OMAP3 version.


- Paul

From: Rajendra Nayak <rnayak at ti.com>
Date: Fri, 2 Mar 2012 17:17:52 +0200
Subject: [PATCH 3/6] ARM: OMAP4: PRM: Add IO Daisychain support

IO daisychain is a mechanism that allows individual IO pads to generate
wakeup events on their own based on a switch of an input signal level.
This allows the hardware module behind the pad to be powered down, but
still have device level capability to detect IO events, and once this
happens the module can be powered back up to resume IO. See section
3.9.4 in OMAP4430 Public TRM for details.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
[paul at pwsan.com: removed MAX_IOPAD_LATCH_TIME declaration; renamed
 omap4_trigger_io_chain() to conform to other PRM function names;
 added kerneldoc]
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/prm44xx.c |   48 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm44xx.h |    2 +
 2 files changed, 50 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a1d6154..5868a12 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -231,6 +231,54 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
 				 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
 }
 
+/**
+ * omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
+ *
+ * Clear any previously-latched I/O wakeup events and ensure that the
+ * I/O wakeup gates are aligned with the current mux settings.  Works
+ * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
+ * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
+ * No return value. XXX Are the final two steps necessary?
+ */
+void omap44xx_prm_reconfigure_io_chain(void)
+{
+	int i = 0;
+
+	/* Enable GLOBAL_WUEN */
+	if (!(omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+		OMAP4_PRM_IO_PMCTRL_OFFSET) & OMAP4430_GLOBAL_WUEN_MASK))
+		omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
+			OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET);
+
+	/* Trigger WUCLKIN enable */
+	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
+			OMAP4430_WUCLK_CTRL_MASK, OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET);
+	omap_test_timeout(
+		(((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET) &
+			OMAP4430_WUCLK_STATUS_MASK) >>
+			OMAP4430_WUCLK_STATUS_SHIFT) == 1),
+		MAX_IOPAD_LATCH_TIME, i);
+	if (i == MAX_IOPAD_LATCH_TIME)
+		pr_warn("PRM: I/O chain clock line assertion timed out\n");
+
+	/* Trigger WUCLKIN disable */
+	omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
+			OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_IO_PMCTRL_OFFSET);
+	omap_test_timeout(
+		(((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+			OMAP4_PRM_IO_PMCTRL_OFFSET) &
+			OMAP4430_WUCLK_STATUS_MASK) >>
+			OMAP4430_WUCLK_STATUS_SHIFT) == 0),
+		MAX_IOPAD_LATCH_TIME, i);
+	if (i == MAX_IOPAD_LATCH_TIME)
+		pr_warn("PRM: I/O chain clock line deassertion timed out\n");
+
+	return;
+}
+
 static int __init omap4xxx_prcm_init(void)
 {
 	if (cpu_is_omap44xx())
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7978092..ee72ae6 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -763,6 +763,8 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 
+extern void omap44xx_prm_reconfigure_io_chain(void);
+
 /* PRM interrupt-related functions */
 extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
 extern void omap44xx_prm_ocp_barrier(void);
-- 
1.7.9.1



From paul at pwsan.com  Fri Mar  9 22:50:57 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 9 Mar 2012 20:50:57 -0700 (MST)
Subject: [PATCHv5 2/6] ARM: OMAP3 PM: Move IO Daisychain function to
 omap3 prm file
In-Reply-To: <1331046702-2472-3-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-3-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203092049210.30879@utopia.booyaka.com>

Hi

On Tue, 6 Mar 2012, Tero Kristo wrote:

> From: Vishwanath BS <vishwanath.bs at ti.com>
> 
> Since IO Daisychain modifies only PRM registers, it makes sense to move
> it to PRM File. Also changed the timeout value for IO chain enable to
> 100us and added a wait for status disable at the end.
> 
> Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
> Signed-off-by: Tero Kristo <t-kristo at ti.com>

This patch has been updated in a few different ways, described below.  
Please let me know if you're okay with it.


- Paul

From: Vishwanath BS <vishwanath.bs at ti.com>
Date: Fri, 2 Mar 2012 17:17:51 +0200
Subject: [PATCH 2/6] ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm
 file

Since IO Daisychain modifies only PRM registers, it makes sense to move
it to PRM File. Also changed the timeout value for IO chain enable to
100us and added a wait for status disable at the end.

Thanks to Nishanth Menon <nm at ti.com> for contributing a fix to the
timeout code waiting for WUCLKOUT to go high.

Signed-off-by: Vishwanath BS <vishwanath.bs at ti.com>
Signed-off-by: Tero Kristo <t-kristo at ti.com>
Cc: Nishanth Menon <nm at ti.com>
[paul at pwsan.com: renamed omap3_trigger_io_chain() to better describe the
 end result and to match other PRM functions; removed
 omap3_disable_io_chain(); moved MAX_IOPAD_LATCH_TIME to prcm-common as it
 will also be used by the OMAP4 code; removed unnecessary barrier;
 added kerneldoc; added credit for fix from Nishanth]
Signed-off-by: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/pm34xx.c       |   35 ++---------------------------------
 arch/arm/mach-omap2/prcm-common.h  |    8 ++++++++
 arch/arm/mach-omap2/prm2xxx_3xxx.c |   31 +++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm2xxx_3xxx.h |    2 ++
 4 files changed, 43 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b0821a8..378a0de 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -85,34 +85,6 @@ static inline void omap3_per_restore_context(void)
 	omap_gpio_restore_context();
 }
 
-static void omap3_enable_io_chain(void)
-{
-	int timeout = 0;
-
-	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-				   PM_WKEN);
-	/* Do a readback to assure write has been done */
-	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
-
-	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
-		 OMAP3430_ST_IO_CHAIN_MASK)) {
-		timeout++;
-		if (timeout > 1000) {
-			pr_err("Wake up daisy chain activation failed.\n");
-			return;
-		}
-	}
-	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-			PM_WKEN);
-
-}
-
-static void omap3_disable_io_chain(void)
-{
-	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-				     PM_WKEN);
-}
-
 static void omap3_core_save_context(void)
 {
 	omap3_ctrl_save_padconf();
@@ -324,7 +296,7 @@ void omap_sram_idle(void)
 	     core_next_state < PWRDM_POWER_ON)) {
 		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 		if (omap3_has_io_chain_ctrl())
-			omap3_enable_io_chain();
+			omap3_reconfigure_io_chain();
 	}
 
 	pwrdm_pre_transition();
@@ -407,12 +379,9 @@ void omap_sram_idle(void)
 	/* Disable IO-PAD and IO-CHAIN wakeup */
 	if (omap3_has_io_wakeup() &&
 	    (per_next_state < PWRDM_POWER_ON ||
-	     core_next_state < PWRDM_POWER_ON)) {
+	     core_next_state < PWRDM_POWER_ON))
 		omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 					     PM_WKEN);
-		if (omap3_has_io_chain_ctrl())
-			omap3_disable_io_chain();
-	}
 
 	clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 }
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 5aa5435..f057c15 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -406,6 +406,14 @@
  */
 #define MAX_MODULE_HARDRESET_WAIT		10000
 
+/*
+ * Maximum time(us) it takes to output the signal WUCLKOUT of the last
+ * pad of the I/O ring after asserting WUCLKIN high.  Tero measured
+ * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4
+ * microseconds on OMAP4, so this timeout may be too high.
+ */
+#define MAX_IOPAD_LATCH_TIME			100
+
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
 extern void __iomem *cm_base;
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 9ce7654..7d62bd6 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -301,6 +301,37 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 				OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 }
 
+/**
+ * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
+ *
+ * Clear any previously-latched I/O wakeup events and ensure that the
+ * I/O wakeup gates are aligned with the current mux settings.  Works
+ * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
+ * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
+ * return value.
+ */
+void omap3xxx_prm_reconfigure_io_chain(void)
+{
+	int i = 0;
+
+	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+				   PM_WKEN);
+
+	omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
+			  OMAP3430_ST_IO_CHAIN_MASK,
+			  MAX_IOPAD_LATCH_TIME, i);
+	if (i == MAX_IOPAD_LATCH_TIME)
+		pr_warn("PRM: I/O chain clock line assertion timed out\n");
+
+	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+				     PM_WKEN);
+
+	omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
+				   PM_WKST);
+
+	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
+}
+
 static int __init omap3xxx_prcm_init(void)
 {
 	if (cpu_is_omap34xx())
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 70ac2a1..1ba3d65 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -315,6 +315,8 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 
+extern void omap3xxx_prm_reconfigure_io_chain(void);
+
 /* PRM interrupt-related functions */
 extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
 extern void omap3xxx_prm_ocp_barrier(void);
-- 
1.7.9.1



From paul at pwsan.com  Fri Mar  9 19:40:18 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 9 Mar 2012 17:40:18 -0700 (MST)
Subject: [PATCHv5 2/6] ARM: OMAP3 PM: Move IO Daisychain function to
 omap3 prm file
In-Reply-To: <1331046702-2472-3-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-3-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203091737390.30879@utopia.booyaka.com>

cc Rajendra

Hi Tero,

a few comments:

On Tue, 6 Mar 2012, Tero Kristo wrote:

...

> +/* OMAP3 Daisychain enable sequence */
> +void omap3_trigger_io_chain(void)
> +{
> +	int i = 0;
> +
> +	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> +				   PM_WKEN);
> +	/* Do a readback to assure write has been done */
> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);

Looks like this barrier shouldn't be needed?  The write is immediately 
followed by another read from the same IP block.

> +
> +	omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
> +			  OMAP3430_ST_IO_CHAIN_MASK,
> +			  MAX_IOPAD_LATCH_TIME, i);
> +
> +	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
> +				     PM_WKEN);
> +
> +	omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
> +				     PM_WKST);
> +
> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
> +}

I see that you removed the second timeout test from this code, but not 
from the OMAP4 version.  Any reason why?  Seems like if the second timeout 
can be removed from one, then it can also be removed from the other?


- Paul


From paul at pwsan.com  Mon Mar 12 06:09:10 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 04:09:10 -0600 (MDT)
Subject: [GIT PULL] ARM: OMAP: clock: clock patches for 3.4
Message-ID: <alpine.DEB.2.00.1203120407460.11332@utopia.booyaka.com>

Hi Tony

The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:

  Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)

are available in the git repository at:

  git://git.pwsan.com/linux-2.6 clock_devel_3.4

for you to fetch changes up to ae6f0a61f6a30f387ff0ce883b4ca8ff23424b11:

  ARM: OMAP: clock: cleanup CPUfreq leftovers (2012-03-12 03:24:45 -0600)


- Paul

----------------------------------------------------------------
Ameya Palande (1):
      ARM: OMAP4: clock data: fix mult and div mask for USB_DPLL

Ilya Yanok (1):
      ARM: OMAP3: clock3xxx_data: change EMAC clocks aliases

Kevin Hilman (1):
      ARM: OMAP: clock: cleanup CPUfreq leftovers

Paul Walmsley (1):
      ARM: OMAP3: clock data: fill in some missing clockdomains

Rajendra Nayak (1):
      ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock

 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c |   80 --------------------------
 arch/arm/mach-omap2/clock.c                  |    5 --
 arch/arm/mach-omap2/clock.h                  |    8 ---
 arch/arm/mach-omap2/clock3xxx_data.c         |   10 +++-
 arch/arm/mach-omap2/clock44xx_data.c         |    5 +-
 arch/arm/plat-omap/clock.c                   |   26 --------
 arch/arm/plat-omap/include/plat/clock.h      |   10 ---
 7 files changed, 11 insertions(+), 133 deletions(-)


From arnd at arndb.de  Mon Mar 12 04:17:19 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 12 Mar 2012 08:17:19 +0000
Subject: [PATCH 1/2] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <20120312030232.GX5050@titan.lakedaemon.net>
References: <1331476406-9844-1-git-send-email-jm@lentin.co.uk>
 <1331476406-9844-2-git-send-email-jm@lentin.co.uk>
 <20120312030232.GX5050@titan.lakedaemon.net>
Message-ID: <201203120817.19777.arnd@arndb.de>

On Monday 12 March 2012, Jason Cooper wrote:
> > +     dnskw_gpio_register(39, "dnskw:power:sata0", 1);
> > +     dnskw_gpio_register(40, "dnskw:power:sata1", 1);
> > +
> > +     /* Set NAS to turn back on after a power failure */
> > +     dnskw_gpio_register(37, "dnskw:power:recover", 1);
> > +}
> > +
> 
> I doubt this board is the only one that wants to be added while the
> conversion to devicetree is progressing.  It makes more sense to me to
> break the above out to a separate file, eg board-dnskw.c.  I'll follow
> and break out the dreamplug code to board-dreamplug.c.  Otherwise, I see
> board-dt.c becoming a long mess.
> 
> Arnd, sound okay to you?

Either way is fine with me. I personally wouldn't expect many more boards
to come in before the DT conversion has mostly completed, but I guess you
have a better feeling for what other hardware is out there that people
are interested in.

	Arnd


From broonie at opensource.wolfsonmicro.com  Fri Mar  9 07:41:19 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 9 Mar 2012 12:41:19 +0000
Subject: [PATCH v6 1/5] Extcon (external connector): import Android's
 switch class and modify.
In-Reply-To: <1330344939-18394-2-git-send-email-myungjoo.ham@samsung.com>
References: <1328856038-21912-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-2-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <20120309124119.GV3273@opensource.wolfsonmicro.com>

On Mon, Feb 27, 2012 at 09:15:35PM +0900, MyungJoo Ham wrote:

> +#ifdef CONFIG_ANDROID
> +		extcon_class = class_create(THIS_MODULE, "switch");
> +#else /* !CONFIG_ANDROID */
> +		extcon_class = class_create(THIS_MODULE, "extcon");
> +#endif /* CONFIG_ANDROID */

This seems somewhat sad - if ANDROID is turned on the standard ABI
vanishes.  It'd be much nicer to do this with a symlink (or with
symlinks within the android directory if the driver core doesn't support
that).  That way userspace code can be written to the new ABI and will
work on Android systems without ifdefery.
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From paul at pwsan.com  Sat Mar 10 16:29:45 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Sat, 10 Mar 2012 14:29:45 -0700 (MST)
Subject: [PATCHv5 0/6] ARM: OMAP3+: IO daisy chain support fixes
In-Reply-To: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
Message-ID: <alpine.DEB.2.00.1203101425230.27395@utopia.booyaka.com>


Hi

By the way, one other thing I forgot to mention.  It would be really great 
if kerneldoc comments can be created for any new functions added to hwmod, 
PRCM, clock, or omap_device code.  The intention is to help not only 
people unfamiliar with the code, but even ourselves in the future.  I've 
been adding these by hand on Tero's last few patch series, but at some 
point I'll probably stop accepting patches without kerneldoc.


thanks,

- Paul


From paul at pwsan.com  Fri Mar  9 01:51:05 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 8 Mar 2012 23:51:05 -0700 (MST)
Subject: [PATCH v2 4/4] arm/dts: OMAP3: Add mmc controller nodes and
 board data
In-Reply-To: <20120309054608.647473E0901@localhost>
References: <1329998490-27555-1-git-send-email-rnayak@ti.com>
 <1329998490-27555-5-git-send-email-rnayak@ti.com>
 <20120223185718.GZ18185@atomide.com> <4F470B71.1020308@ti.com>
 <20120224184859.GN18185@atomide.com> <20120309054608.647473E0901@localhost>
Message-ID: <alpine.DEB.2.00.1203082348200.26656@utopia.booyaka.com>

On Thu, 8 Mar 2012, Grant Likely wrote:

> Yes, absolutely use separate compatible values.  It is always important
> to be specific as to the silicon implementing the IP.

In that case, it is probably best to use the full chip name in the 
compatible string, e.g., omap2420 or omap2430 rather than just "omap2".  
Particularly in the case of "OMAP3," which is a largely meaningless group 
these days with AM33xx, OMAP34xx, OMAP36xx, and AM3517, many of which are 
quite different from each other...


- Paul


From paul at pwsan.com  Thu Mar  8 23:27:27 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 8 Mar 2012 21:27:27 -0700 (MST)
Subject: [PATCH 00/12] ARM: OMAP2+: hwmod: remove link arrays
In-Reply-To: <20120308023614.8205.78768.stgit@dusk>
References: <20120308023614.8205.78768.stgit@dusk>
Message-ID: <alpine.DEB.2.00.1203082123540.26656@utopia.booyaka.com>


This series has been rebased on top of a merge of the hwmod_misc_devel_3.4 
branch and the hwmod_data_cleanup_3.4 branch, both previously posted.  
Fortunately the auto-merger came up with something reasonable.  Patches 5 
and 7 have been trivially updated to take account of the SmartReflex 
changes.  The updated series has been posted at:

http://www.pwsan.com/omap/patches-hwmod_remove_link_arrays_cleanup_3.4_2

since the two patches that changed were the ones that were too big to make 
it onto the lists.

The updated branch is in the same place as before: 
git://git.pwsan.com/linux-2.6 in the 
'hwmod_remove_link_arrays_cleanup_3.4' branch.


- Paul


From arnd at arndb.de  Sun Mar 11 17:36:47 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 11 Mar 2012 21:36:47 +0000
Subject: [PATCH v2 1/2] ARM: AT91: Add parameter for AT91_HAS_PATA
In-Reply-To: <20120311183856.GA13869@game.jcrosoft.org>
References: <1331415380-10928-1-git-send-email-alan@signal11.us>
 <1331415531-10961-1-git-send-email-alan@signal11.us>
 <20120311183856.GA13869@game.jcrosoft.org>
Message-ID: <201203112136.47694.arnd@arndb.de>

On Sunday 11 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > 
> > diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> > index 71feb00..9eeeabe 100644
> > --- a/arch/arm/mach-at91/Kconfig
> > +++ b/arch/arm/mach-at91/Kconfig
> > @@ -24,6 +24,9 @@ config AT91_SAM9_ALT_RESET
> >  config AT91_SAM9G45_RESET
> >       bool
> >  
> > +config AT91_HAS_PATA
> > +     bool
> what is the need for this?
> 
> As we switch to DT, I don't want to track the soc list in the Kconfig anymore
> if the soc support the PATA will be describe in the DT
> 

When I originally wrote the patch, I was hitting build errors when trying
to enable the at91 pata driver on socs that don't have the right declarations
in their headers. If that has been resolved in a better way already, this
patch can be dropped.

	Arnd


From paul at pwsan.com  Mon Mar 12 02:51:29 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 00:51:29 -0600 (MDT)
Subject: [PATCHv5 3/6] ARM: OMAP4 PM: Add IO Daisychain support
In-Reply-To: <4F5D8F2A.1070602@ti.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-4-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203092051140.30879@utopia.booyaka.com>
 <4F5D8F2A.1070602@ti.com>
Message-ID: <alpine.DEB.2.00.1203120050360.11332@utopia.booyaka.com>

On Mon, 12 Mar 2012, Rajendra Nayak wrote:

> > Signed-off-by: Tero Kristo<t-kristo at ti.com>
> > [paul at pwsan.com: removed MAX_IOPAD_LATCH_TIME declaration; renamed
> 
> But the code below still seems to use it. Is it now defined in some
> common header so the same value is used in omap3 and omap4?

Yes, I put it into prcm-common.h in the previous patch that added it for 
OMAP3.  I'll update that comment to clarify.


- Paul


From paul at pwsan.com  Mon Mar 12 06:13:16 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Mon, 12 Mar 2012 04:13:16 -0600 (MDT)
Subject: [PATCHv5 0/6] ARM: OMAP3+: IO daisy chain support fixes
In-Reply-To: <1331546427.2116.264.camel@sokoban>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203092102450.30879@utopia.booyaka.com>
 <1331546427.2116.264.camel@sokoban>
Message-ID: <alpine.DEB.2.00.1203120412230.11332@utopia.booyaka.com>

Hi Tero, Rajendra,

On Mon, 12 Mar 2012, Tero Kristo wrote:

> Just tested your branch with omap3 beagle + omap4 blaze (with my omap4
> cswr set on top), and it works on both.
> 
> For the WUCLK poll bit I added detailed comments on patch 2 thread, but
> my current understanding is that the implementation now on omap3 / omap4
> is what they should be due to IP differences (except maybe the small
> optimization for omap3 part you commented about.)

Thank you both for the detailed comments and explanation on this series, 
and the testing... sounds like this set is okay to go.


- Paul


From paul at pwsan.com  Sat Mar 10 02:08:40 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Sat, 10 Mar 2012 00:08:40 -0700 (MST)
Subject: [PATCH] ARM: OMAP4: clock: Add aliases for McBSP fclk clocks
In-Reply-To: <alpine.DEB.2.00.1203091103450.7039@utopia.booyaka.com>
References: <1331024133-18201-1-git-send-email-peter.ujfalusi@ti.com>
 <4F5A258F.8050704@ti.com> <20120309180027.GF12083@atomide.com>
 <alpine.DEB.2.00.1203091101400.7039@utopia.booyaka.com>
 <alpine.DEB.2.00.1203091103450.7039@utopia.booyaka.com>
Message-ID: <alpine.DEB.2.00.1203092355280.27395@utopia.booyaka.com>


Hello P?ter

could you please try this patch instead of the clkdev change?

It is based on my 'hwmod_enable_remaining_hwmods_devel_3.4' branch, but 
the basic idea should work on v3.3-rc6 as well.

If it works for you, please let us know and we can queue this up along 
with the hwmod data changes.  Probably we should replace the changelog 
also with the one from your patch, it might be a little more useful?  
Suggestions welcome.


- Paul

From: Paul Walmsley <paul at pwsan.com>
Date: Fri, 9 Mar 2012 23:28:28 -0700
Subject: [PATCH] ARM: OMAP4: hwmod data: add McBSP parent clock aliases

Add optional parent clocks for the OMAP4 McBSP modules so the driver
can switch between parent clocks.

Based on a patch from P?ter Ujfalusi <peter.ujfalusi at ti.com>.
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e029992..b4a061d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1921,6 +1921,11 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
 	{ .dma_req = -1 }
 };
 
+static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
+	{ .role = "pad_fck", .clk = "pad_clks_ck" },
+	{ .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
+};
+
 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
 	.name		= "mcbsp1",
 	.class		= &omap44xx_mcbsp_hwmod_class,
@@ -1935,6 +1940,8 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
 			.modulemode   = MODULEMODE_SWCTRL,
 		},
 	},
+	.opt_clks	= mcbsp1_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcbsp1_opt_clks),
 };
 
 /* mcbsp2 */
@@ -1949,6 +1956,11 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
 	{ .dma_req = -1 }
 };
 
+static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
+	{ .role = "pad_fck", .clk = "pad_clks_ck" },
+	{ .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
+};
+
 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
 	.name		= "mcbsp2",
 	.class		= &omap44xx_mcbsp_hwmod_class,
@@ -1963,6 +1975,8 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
 			.modulemode   = MODULEMODE_SWCTRL,
 		},
 	},
+	.opt_clks	= mcbsp2_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcbsp2_opt_clks),
 };
 
 /* mcbsp3 */
@@ -1977,6 +1991,11 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
 	{ .dma_req = -1 }
 };
 
+static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
+	{ .role = "pad_fck", .clk = "pad_clks_ck" },
+	{ .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
+};
+
 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
 	.name		= "mcbsp3",
 	.class		= &omap44xx_mcbsp_hwmod_class,
@@ -1991,6 +2010,8 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
 			.modulemode   = MODULEMODE_SWCTRL,
 		},
 	},
+	.opt_clks	= mcbsp3_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcbsp3_opt_clks),
 };
 
 /* mcbsp4 */
@@ -2005,6 +2026,11 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
 	{ .dma_req = -1 }
 };
 
+static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
+	{ .role = "pad_fck", .clk = "pad_clks_ck" },
+	{ .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
+};
+
 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
 	.name		= "mcbsp4",
 	.class		= &omap44xx_mcbsp_hwmod_class,
@@ -2019,6 +2045,8 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
 			.modulemode   = MODULEMODE_SWCTRL,
 		},
 	},
+	.opt_clks	= mcbsp4_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(mcbsp4_opt_clks),
 };
 
 /*
-- 
1.7.9.1

From sfr at canb.auug.org.au  Mon Mar 12 19:06:25 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Tue, 13 Mar 2012 10:06:25 +1100
Subject: linux-next: manual merge of the cpuidle-cons tree with the
 arm-soc tree
In-Reply-To: <CAMXH7KH_vgri3EPRvkXR+LddRUc=0ve=4u7yr51utBfgV5bF3w@mail.gmail.com>
References: <20120309183732.512d3676599da324f4747219@canb.auug.org.au>
 <4F5E1ECC.1040605@atmel.com>
 <CAMXH7KH_vgri3EPRvkXR+LddRUc=0ve=4u7yr51utBfgV5bF3w@mail.gmail.com>
Message-ID: <20120313100625.b500f0efb546a9f4ceeb12ba@canb.auug.org.au>

Hi Rob,

On Mon, 12 Mar 2012 12:03:48 -0500 Rob Lee <rob.lee at linaro.org> wrote:
>
> On Mon, Mar 12, 2012 at 11:05 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
> > -----BEGIN PGP SIGNED MESSAGE-----
> > Hash: SHA1
> >
> > On 03/09/2012 08:37 AM, Stephen Rothwell :
> >>
> >> Today's linux-next merge of the cpuidle-cons tree got a conflict
> >> in arch/arm/mach-at91/cpuidle.c between commit 00482a4078f4 ("ARM:
> >> at91: implement the standby function for pm/cpuidle") from the
> >> arm-soc tree and commit 7a1f6e72dce1 ("ARM: at91: Consolidate time
> >> keeping and irq enable") from the cpuidle-cons tree.
> >>
> >> I fixed it up (I think - see below) and can carry the fix as
> >> necessary.
> >
> > Yes: resolution correct. Please carry it.
> 
> Who should carry this fixup and related necessary at91 changes?  Me?
> FYI, my at91 changes are dependent on my core cpuidle change, but my
> core cpuidle changes do not require any at91 changes as the at91 and
> other platform changes were only made to consolidate duplicate code.

I will carry the fixup and Linus will presumably do the same fix when he
merges these trees in his tree.  I am not sure what you mean by "related
at91 changes".

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From linux at arm.linux.org.uk  Mon Mar 12 19:10:16 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 12 Mar 2012 23:10:16 +0000
Subject: Conflict between Versatile Express DT conversion and local timer
 updates
Message-ID: <20120312231016.GC10830@n2100.arm.linux.org.uk>

Marc, Pawel,

Your changes are conflicting badly.  Seriously badly.  So badly that I'm
not bothering to fix the conflicts because I can't work out what the fix
should be.

You both work for the same frigging organization and yet you seem to
work completely independently (I really don't care if you work in
different departments - the fact of the matter is you're touching the
same code in completely different ways with zero coordination between
yourselves.  That's simply broken workflow.)

For example, Marc's deleting arch/arm/plat-versatile/localtimer.c, but
Pawel is modifying it to add DT support for Versatile Express.  The
correct solution?  Hell knows.  And I don't want a solution to the merge
conflict.  I want the merge conflict to go away (because I'm not frigging
around applying the same git-rerere immune fixes to a tree I'm regenerating
each night for the kernel autobuilder.)

I'm getting conflicts in arch/arm/mach-vexpress/ct-ca9x4.c and
arch/arm/mach-ux500/timer.c as well, which I'm not going to bother trying
to sort out - the obvious solution for ux500/timer.c doesn't look right.

I've a mind to drop the localtimer changes on the floor until after this
merge window, but unfortunately they're part of devel-stable so I can't.

How do we fix this?

(In the mean time, I've had to reset the kernel autobuilder back to last
nights tree, which is -rc6 based.)

diff --cc arch/arm/mach-ux500/timer.c
index cadf982,fd00024..0000000
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@@ -15,38 -15,22 +15,52 @@@
  #include <mach/setup.h>
  #include <mach/hardware.h>
  
 +#ifdef CONFIG_HAVE_ARM_TWD
 +static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer,
 +			      U5500_TWD_BASE, IRQ_LOCALTIMER);
 +static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
 +			      U8500_TWD_BASE, IRQ_LOCALTIMER);
 +
 +static void __init ux500_twd_init(void)
 +{
 +	struct twd_local_timer *twd_local_timer;
 +	int err;
 +
 +	twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer :
 +					   &u8500_twd_local_timer;
 +
 +	err = twd_local_timer_register(twd_local_timer);
 +	if (err)
 +		pr_err("twd_local_timer_register failed %d\n", err);
 +}
 +#else
 +#define ux500_twd_init()	do { } while(0)
 +#endif
 +
  static void __init ux500_timer_init(void)
  {
+ 	void __iomem *mtu_timer_base;
  	void __iomem *prcmu_timer_base;
 +	int err;
  
  	if (cpu_is_u5500()) {
++<<<<<<< HEAD
 +		mtu_base = __io_address(U5500_MTU0_BASE);
 +		prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
 +	} else if (cpu_is_u8500()) {
 +		mtu_base = __io_address(U8500_MTU0_BASE);
++=======
+ #ifdef CONFIG_LOCAL_TIMERS
+ 		twd_base = __io_address(U5500_TWD_BASE);
+ #endif
+ 		mtu_timer_base = __io_address(U5500_MTU0_BASE);
+ 		prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
+ 	} else if (cpu_is_u8500()) {
+ #ifdef CONFIG_LOCAL_TIMERS
+ 		twd_base = __io_address(U8500_TWD_BASE);
+ #endif
+ 		mtu_timer_base = __io_address(U8500_MTU0_BASE);
++>>>>>>> arm-soc
  		prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
  	} else {
  		ux500_unknown_soc();
@@@ -69,9 -53,8 +83,9 @@@
  	 *
  	 */
  
- 	nmdk_timer_init();
+ 	nmdk_timer_init(mtu_timer_base);
  	clksrc_dbx500_prcmu_init(prcmu_timer_base);
 +	ux500_twd_init();
  }
  
  static void ux500_timer_reset(void)
diff --cc arch/arm/mach-vexpress/ct-ca9x4.c
index b391538,73791f0..0000000
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@@ -54,44 -42,17 +42,50 @@@ static struct map_desc ct_ca9x4_io_desc
  static void __init ct_ca9x4_map_io(void)
  {
  	iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
++<<<<<<< HEAD
++=======
+ #ifdef CONFIG_LOCAL_TIMERS
+ 	twd_base = ioremap(A9_MPCORE_TWD, SZ_32);
+ #endif
++>>>>>>> arm-soc
  }
  
 +#ifdef CONFIG_HAVE_ARM_TWD
 +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
 +
 +static void __init ca9x4_twd_init(void)
 +{
 +	int err = twd_local_timer_register(&twd_local_timer);
 +	if (err)
 +		pr_err("twd_local_timer_register failed %d\n", err);
 +}
 +#else
 +#define ca9x4_twd_init()	do {} while(0)
 +#endif
 +
  static void __init ct_ca9x4_init_irq(void)
  {
++<<<<<<< HEAD
 +	gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
 +		 MMIO_P2V(A9_MPCORE_GIC_CPU));
 +	ca9x4_twd_init();
 +}
 +
 +#if 0
 +static void __init ct_ca9x4_timer_init(void)
 +{
 +	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
 +	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
 +
 +	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
 +	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
 +		"ct-timer0");
++=======
+ 	gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
+ 		 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
++>>>>>>> arm-soc
  }
  
- static struct sys_timer ct_ca9x4_timer = {
- 	.init	= ct_ca9x4_timer_init,
- };
- #endif
- 
  static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
  {
  	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);



From rnayak at ti.com  Fri Mar  9 04:11:48 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 9 Mar 2012 14:41:48 +0530
Subject: [PATCH 3/4] ARM: OMAP2+: hsmmc: Let board files specify if an
 external transceiver exists
In-Reply-To: <1331284309-22101-1-git-send-email-rnayak@ti.com>
References: <1331284309-22101-1-git-send-email-rnayak@ti.com>
Message-ID: <1331284309-22101-4-git-send-email-rnayak@ti.com>

The omap2_hsmmc_info structure provides a way for board files to specify
if an external transciever exists for the mmc module. So get rid of the
assumption based on external clock.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: Balaji TK <balajitk at ti.com>
Cc: Venkatraman S <svenkatr at ti.com>
---
 arch/arm/mach-omap2/hsmmc.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 0133b29..0aa4587 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -387,8 +387,6 @@ static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 			mmc->select_input_clk_src = hsmmc1_select_input_clk_src;
 		break;
 	case 2:
-		if (c->ext_clock)
-			c->transceiver = 1;
 		if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
 			c->caps &= ~MMC_CAP_8_BIT_DATA;
 			c->caps |= MMC_CAP_4_BIT_DATA;
-- 
1.7.1



From plagnioj at jcrosoft.com  Fri Mar  9 13:25:44 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri,  9 Mar 2012 19:25:44 +0100
Subject: [PATCH 1/4 v5] of_spi: add generic binding support to specify cs gpio
In-Reply-To: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.co>
References: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.co>
Message-ID: <1331317544-21735-1-git-send-email-plagnioj@jcrosoft.com>

This will allow to use gpio for chip select with no modification in the
driver binding

When use the cs-gpios, the gpio number will be passed via the cs_gpio field
and the number of chip select will automatically increased.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: spi-devel-general at lists.sourceforge.net
---
v5:
	update grant comment to simplify the cs_gpio management

Best Regards,
J.
 Documentation/devicetree/bindings/spi/spi-bus.txt |    6 ++
 drivers/spi/spi.c                                 |   55 +++++++++++++++++++-
 include/linux/spi/spi.h                           |    4 ++
 3 files changed, 62 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
index e782add..c253379 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -12,6 +12,7 @@ The SPI master node requires the following properties:
 - #size-cells     - should be zero.
 - compatible      - name of SPI bus controller following generic names
     		recommended practice.
+- cs-gpios	  - (optional) gpios chip select.
 No other properties are required in the SPI bus node.  It is assumed
 that a driver for an SPI bus device will understand that it is an SPI bus.
 However, the binding does not attempt to define the specific method for
@@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
 chip selects.  Individual drivers can define additional properties to
 support describing the chip select layout.
 
+If cs-gpios is used the number of chip select will automatically increased.
+
 SPI slave nodes must be children of the SPI master node and can
 contain the following properties.
 - reg             - (required) chip select address of device.
@@ -34,6 +37,9 @@ contain the following properties.
 - spi-cs-high     - (optional) Empty property indicating device requires
     		chip select active high
 
+If a gpio chipselect is used for the SPI slave the gpio number will be passed
+via the cs_gpio
+
 SPI example for an MPC5200 SPI bus:
 	spi at f00 {
 		#address-cells = <1>;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index b2ccdea..446eee5 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -28,6 +28,7 @@
 #include <linux/mod_devicetable.h>
 #include <linux/spi/spi.h>
 #include <linux/of_spi.h>
+#include <linux/of_gpio.h>
 #include <linux/pm_runtime.h>
 #include <linux/export.h>
 
@@ -322,6 +323,7 @@ struct spi_device *spi_alloc_device(struct spi_master *master)
 	spi->dev.parent = &master->dev;
 	spi->dev.bus = &spi_bus_type;
 	spi->dev.release = spidev_release;
+	spi->cs_gpio = -EINVAL;
 	device_initialize(&spi->dev);
 	return spi;
 }
@@ -339,15 +341,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
 int spi_add_device(struct spi_device *spi)
 {
 	static DEFINE_MUTEX(spi_add_lock);
-	struct device *dev = spi->master->dev.parent;
+	struct spi_master *master = spi->master;
+	struct device *dev = master->dev.parent;
 	struct device *d;
 	int status;
 
 	/* Chipselects are numbered 0..max; validate. */
-	if (spi->chip_select >= spi->master->num_chipselect) {
+	if (spi->chip_select >= master->num_chipselect) {
 		dev_err(dev, "cs%d >= max %d\n",
 			spi->chip_select,
-			spi->master->num_chipselect);
+			master->num_chipselect);
 		return -EINVAL;
 	}
 
@@ -371,6 +374,9 @@ int spi_add_device(struct spi_device *spi)
 		goto done;
 	}
 
+	if (master->cs_gpios)
+		spi->cs_gpio = master->cs_gpios[spi->chip_select];
+
 	/* Drivers may modify this initial i/o setup, but will
 	 * normally rely on the device being setup.  Devices
 	 * using SPI_CS_HIGH can't coexist well otherwise...
@@ -561,6 +567,45 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
 }
 EXPORT_SYMBOL_GPL(spi_alloc_master);
 
+#ifdef CONFIG_OF
+static int of_spi_register_master(struct spi_master *master)
+{
+	int nb, i;
+	int *cs;
+	struct device_node *np = master->dev.of_node;
+
+	if (!np)
+		return 0;
+
+	nb = of_gpio_named_count(np, "cs-gpios");
+
+	if (nb < 1)
+		return 0;
+
+	cs = devm_kzalloc(&master->dev,
+			  sizeof(int) * (master->num_chipselect + nb),
+			  GFP_KERNEL);
+	master->cs_gpios = cs;
+
+	if (!master->cs_gpios)
+		return -ENOMEM;
+
+	memset(cs, -EINVAL, master->num_chipselect);
+	master->num_chipselect += nb;
+	cs += master->num_chipselect;
+
+	for (i = 0; i < nb; i++)
+		cs[i] = of_get_named_gpio(np, "cs-gpios", i);
+
+	return 0;
+}
+#else
+static int of_spi_register_master(struct spi_master *master)
+{
+	return 0;
+}
+#endif
+
 /**
  * spi_register_master - register SPI master controller
  * @master: initialized master, originally from spi_alloc_master()
@@ -592,6 +637,10 @@ int spi_register_master(struct spi_master *master)
 	if (!dev)
 		return -ENODEV;
 
+	status = of_spi_register_master(master);
+	if (status)
+		return status;
+
 	/* even if it's just one always-selected device, there must
 	 * be at least one chipselect
 	 */
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 176fce9..328d492 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -89,6 +89,7 @@ struct spi_device {
 	void			*controller_state;
 	void			*controller_data;
 	char			modalias[SPI_NAME_SIZE];
+	int			cs_gpio;	/* chip select gpio */
 
 	/*
 	 * likely need more hooks for more protocol options affecting how
@@ -318,6 +319,9 @@ struct spi_master {
 
 	/* called on release() to free memory provided by spi_master */
 	void			(*cleanup)(struct spi_device *spi);
+
+	/* gpio chip select */
+	int			*cs_gpios;
 };
 
 static inline void *spi_master_get_devdata(struct spi_master *master)
-- 
1.7.7



From rnayak at ti.com  Fri Mar  9 04:21:06 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 09 Mar 2012 14:51:06 +0530
Subject: [PATCH v2 1/4] mmc: omap_hsmmc: Convert hsmmc driver to use device
 tree
In-Reply-To: <20120309054213.9E69C3E0901@localhost>
References: <1329998490-27555-1-git-send-email-rnayak@ti.com>
 <1329998490-27555-2-git-send-email-rnayak@ti.com>
 <20120309054213.9E69C3E0901@localhost>
Message-ID: <4F59CB82.9050607@ti.com>

Hi Grant,

On Friday 09 March 2012 11:12 AM, Grant Likely wrote:
> On Thu, 23 Feb 2012 17:31:27 +0530, Rajendra Nayak<rnayak at ti.com>  wrote:
>> Define dt bindings for the ti-omap-hsmmc, and adapt
>> the driver to extract data (which was earlier passed as
>> platform_data) from device tree.
>>
>> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
>> ---
>>   .../devicetree/bindings/mmc/ti-omap-hsmmc.txt      |   31 +++++++++
>>   drivers/mmc/host/omap_hsmmc.c                      |   68 ++++++++++++++++++++
>>   2 files changed, 99 insertions(+), 0 deletions(-)
>>   create mode 100644 Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>> new file mode 100644
>> index 0000000..e4fa8f0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
>> @@ -0,0 +1,31 @@
>> +* TI Highspeed MMC host controller for OMAP
>> +
>> +The Highspeed MMC Host Controller on TI OMAP family
>> +provides an interface for MMC, SD, and SDIO types of memory cards.
>> +
>> +Required properties:
>> +- compatible:
>> + Should be "ti,omap2-hsmmc", for OMAP2/3 controllers
>> + Should be "ti,omap4-hsmmc", for OMAP4 controllers
>> +- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
>> +- reg : should contain hsmmc registers location and length
>> +
>> +Optional properties:
>> +ti,dual-volt: boolean, supports dual voltage cards
>> +<supply-name>-supply: phandle to the regulator device tree node
>> +"supply-name" examples are "vmmc", "vmmc_aux" etc
>> +ti,bus-width: Number of data lines, default assumed is 1 if the property is missing.
>> +cd-gpios: GPIOs for card detection
>> +wp-gpios: GPIOs for write protection
>> +ti,non-removable: non-removable slot (like eMMC)
>
> Binding looks okay.  A couple comments below...
>
> [...]
>> +static const struct of_device_id omap_mmc_of_match[];
>
> If you move the omap_mmc_of_match[] table up to here then there is no
> need for the forward declaration.
>
>> +
>>   static int __init omap_hsmmc_probe(struct platform_device *pdev)
>>   {
>>   	struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
>> @@ -1725,6 +1768,14 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
>>   	struct omap_hsmmc_host *host = NULL;
>>   	struct resource *res;
>>   	int ret, irq;
>> +	const struct of_device_id *match;
>> +
>> +	match = of_match_device(omap_mmc_of_match,&pdev->dev);
>> +	if (match) {
>> +		pdata = of_get_hsmmc_pdata(&pdev->dev);
>> +		if (match->data)
>> +			pdata->reg_offset = *(u16 *)match->data;
>
> Blech on the ugly cast.  It is slightly safer to do thusly:
>
> 	u16 *offsetp = match->data;
> 	pdata->reg_offset = *offsetp

thanks for the review. I'll repost with these changes.

regards,
Rajendra

>
>> +	}
>>
>>   	if (pdata == NULL) {
>>   		dev_err(&pdev->dev, "Platform Data is missing\n");
>> @@ -2120,12 +2171,29 @@ static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
>>   	.runtime_resume = omap_hsmmc_runtime_resume,
>>   };
>>
>> +#if defined(CONFIG_OF)
>> +static u16 omap4_reg_offset = 0x100;
>> +
>> +static const struct of_device_id omap_mmc_of_match[] = {
>> +	{
>> +		.compatible = "ti,omap2-hsmmc",
>> +	},
>> +	{
>> +		.compatible = "ti,omap4-hsmmc",
>> +		.data =&omap4_reg_offset,
>> +	},
>> +	{},
>> +}
>> +MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
>> +#endif
>> +
>>   static struct platform_driver omap_hsmmc_driver = {
>>   	.remove		= omap_hsmmc_remove,
>>   	.driver		= {
>>   		.name = DRIVER_NAME,
>>   		.owner = THIS_MODULE,
>>   		.pm =&omap_hsmmc_dev_pm_ops,
>> +		.of_match_table = of_match_ptr(omap_mmc_of_match),
>>   	},
>>   };
>>
>> --
>> 1.7.1
>>
>>
>> _______________________________________________
>> linaro-dev mailing list
>> linaro-dev at lists.linaro.org
>> http://lists.linaro.org/mailman/listinfo/linaro-dev
>



From rnayak at ti.com  Fri Mar  9 04:11:45 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 9 Mar 2012 14:41:45 +0530
Subject: [PATCH 0/4] hsmmc cleanups in platform callback routines
Message-ID: <1331284309-22101-1-git-send-email-rnayak@ti.com>

This series mainly splits the platform callbacks implemented in
hsmmc.c (for clk source selection and pbiascell programming)
rather than doing everything in a single callback which
is what is done today. This cleanup is ground work before all these
callbacks are moved into hsmmc/system-control module driver
out of machine folder.

Patches tested on omap3 beagle-Xm and omap4 panda boards.

regards,
Rajendra

Rajendra Nayak (4):
  ARM: OMAP2+: hsmmc: Add a flag to identify modules supporting clock
    src selection
  ARM: OMAP2+: hsmmc: Split the clock src selection and pbias
    programming
  ARM: OMAP2+: hsmmc: Let board files specify if an external
    transceiver exists
  ARM: OMAP2430SDP: No support to switch to external clock on omap2430

 arch/arm/mach-omap2/board-2430sdp.c        |    1 -
 arch/arm/mach-omap2/hsmmc.c                |  101 ++++++++++++----------------
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   14 +++-
 arch/arm/plat-omap/include/plat/mmc.h      |    2 +
 drivers/mmc/host/omap_hsmmc.c              |    3 +
 5 files changed, 58 insertions(+), 63 deletions(-)



From plagnioj at jcrosoft.com  Fri Mar  9 13:02:32 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 9 Mar 2012 19:02:32 +0100
Subject: [PATCH 1/4 v4] of_spi: add generic binding support to specify
 cs gpio
In-Reply-To: <20120309151445.97E2B3E0901@localhost>
References: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.com>
 <20120309151445.97E2B3E0901@localhost>
Message-ID: <20120309180232.GR27213@game.jcrosoft.org>

On 08:14 Fri 09 Mar     , Grant Likely wrote:
> On Wed,  7 Mar 2012 13:23:06 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > This will allow to use gpio for chip select with no modification in the
> > driver binding
> > 
> > When use the cs-gpios, the gpio number will be passed via the cs_gpio field
> > and the number of chip select will automatically increased.
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Cc: devicetree-discuss at lists.ozlabs.org
> > Cc: spi-devel-general at lists.sourceforge.net
> > ---
> > v4:
> > 	use cs_gpio to pass the gpio number
> > 
> > Best Regards,
> > J.
> >  Documentation/devicetree/bindings/spi/spi-bus.txt |    6 ++
> >  drivers/spi/spi.c                                 |   57 +++++++++++++++++++-
> >  include/linux/spi/spi.h                           |    6 ++
> >  3 files changed, 66 insertions(+), 3 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
> > index e782add..c253379 100644
> > --- a/Documentation/devicetree/bindings/spi/spi-bus.txt
> > +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
> > @@ -12,6 +12,7 @@ The SPI master node requires the following properties:
> >  - #size-cells     - should be zero.
> >  - compatible      - name of SPI bus controller following generic names
> >      		recommended practice.
> > +- cs-gpios	  - (optional) gpios chip select.
> >  No other properties are required in the SPI bus node.  It is assumed
> >  that a driver for an SPI bus device will understand that it is an SPI bus.
> >  However, the binding does not attempt to define the specific method for
> > @@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
> >  chip selects.  Individual drivers can define additional properties to
> >  support describing the chip select layout.
> >  
> > +If cs-gpios is used the number of chip select will automatically increased.
> > +
> >  SPI slave nodes must be children of the SPI master node and can
> >  contain the following properties.
> >  - reg             - (required) chip select address of device.
> > @@ -34,6 +37,9 @@ contain the following properties.
> >  - spi-cs-high     - (optional) Empty property indicating device requires
> >      		chip select active high
> >  
> > +If a gpio chipselect is used for the SPI slave the gpio number will be passed
> > +via the controller_data
> > +
> >  SPI example for an MPC5200 SPI bus:
> >  	spi at f00 {
> >  		#address-cells = <1>;
> > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> > index b2ccdea..c1d0955 100644
> > --- a/drivers/spi/spi.c
> > +++ b/drivers/spi/spi.c
> > @@ -28,6 +28,7 @@
> >  #include <linux/mod_devicetable.h>
> >  #include <linux/spi/spi.h>
> >  #include <linux/of_spi.h>
> > +#include <linux/of_gpio.h>
> >  #include <linux/pm_runtime.h>
> >  #include <linux/export.h>
> >  
> > @@ -322,6 +323,7 @@ struct spi_device *spi_alloc_device(struct spi_master *master)
> >  	spi->dev.parent = &master->dev;
> >  	spi->dev.bus = &spi_bus_type;
> >  	spi->dev.release = spidev_release;
> > +	spi->cs_gpio = -EINVAL;
> >  	device_initialize(&spi->dev);
> >  	return spi;
> >  }
> > @@ -339,15 +341,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
> >  int spi_add_device(struct spi_device *spi)
> >  {
> >  	static DEFINE_MUTEX(spi_add_lock);
> > -	struct device *dev = spi->master->dev.parent;
> > +	struct spi_master *master = spi->master;
> > +	struct device *dev = master->dev.parent;
> >  	struct device *d;
> >  	int status;
> >  
> >  	/* Chipselects are numbered 0..max; validate. */
> > -	if (spi->chip_select >= spi->master->num_chipselect) {
> > +	if (spi->chip_select >= master->num_chipselect) {
> >  		dev_err(dev, "cs%d >= max %d\n",
> >  			spi->chip_select,
> > -			spi->master->num_chipselect);
> > +			master->num_chipselect);
> >  		return -EINVAL;
> >  	}
> >  
> > @@ -371,6 +374,13 @@ int spi_add_device(struct spi_device *spi)
> >  		goto done;
> >  	}
> >  
> > +	if (master->num_gpio_cs &&
> > +	    spi->chip_select >= master->first_gpio_cs) {
> > +		int num = spi->chip_select - master->first_gpio_cs;
> > +
> > +		spi->cs_gpio = master->cs_gpios[num];
> 
> spi->cs_gpio isn't used anywhere.
driver
as example atmel spi

I choose to let the driver to manage it as they may need to manange specific
register when using both hw and gpio cs
> 
> > +	}
> > +
> >  	/* Drivers may modify this initial i/o setup, but will
> >  	 * normally rely on the device being setup.  Devices
> >  	 * using SPI_CS_HIGH can't coexist well otherwise...
> > @@ -561,6 +571,43 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
> >  }
> >  EXPORT_SYMBOL_GPL(spi_alloc_master);
> >  
> > +#ifdef CONFIG_OF
> > +static int of_spi_register_master(struct spi_master *master)
> > +{
> > +	int nb, i;
> > +	int *cs;
> > +	struct device_node *np = master->dev.of_node;
> > +
> > +	if (!np)
> > +		return 0;
> > +
> > +	nb = of_gpio_named_count(np, "cs-gpios");
> > +
> > +	if (nb < 1)
> > +		return 0;
> > +
> > +	cs = devm_kzalloc(&master->dev, sizeof(int) * nb, GFP_KERNEL);
> > +	master->cs_gpios = cs;
> > +
> > +	if (!master->cs_gpios)
> > +		return -ENOMEM;
> > +
> > +	master->first_gpio_cs = master->num_chipselect;
> > +	master->num_chipselect += nb;
> > +	master->num_gpio_cs = nb;
> 
> I think this can be simplified.  Rather than trying to optimize by having
> a set of integrated cs lines followed by a gpio set, I think it would be
> better to have a single cs_gpios table that covers the whole range of
> num_chipselect; even if they overlap natural cs lines.  That will make for
> an easier to use binding since users won't need to remember how many natural
> cs lines are on the device when filling the cs-gpios property.  It will
> also make the code simpler because first_gpio_cs and num_gpio_cs can both
> be eliminated.  It also means the core can have exact knowledge about which
> gpio is associated with which cs number.
ok why not so I feel the array with -EINVAL for hw cs;

Best Regards,
J.


From plagnioj at jcrosoft.com  Mon Mar 12 13:11:47 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 12 Mar 2012 18:11:47 +0100
Subject: [PATCH 1/4 v5] of_spi: add generic binding support to specify
 cs gpio
In-Reply-To: <20120312154019.1DB653E0950@localhost>
References: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.co>
 <1331317544-21735-1-git-send-email-plagnioj@jcrosoft.com>
 <20120311140731.2D4F93E0979@localhost>
 <20120311182537.GS27213@game.jcrosoft.org>
 <20120312154019.1DB653E0950@localhost>
Message-ID: <20120312171147.GF13869@game.jcrosoft.org>

On 09:40 Mon 12 Mar     , Grant Likely wrote:
> On Sun, 11 Mar 2012 19:25:37 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > On 08:07 Sun 11 Mar     , Grant Likely wrote:
> > > On Fri,  9 Mar 2012 19:25:44 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > > > This will allow to use gpio for chip select with no modification in the
> > > > driver binding
> > > > 
> > > > When use the cs-gpios, the gpio number will be passed via the cs_gpio field
> > > > and the number of chip select will automatically increased.
> > > > 
> > > > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > > > Cc: devicetree-discuss at lists.ozlabs.org
> > > > Cc: spi-devel-general at lists.sourceforge.net
> > > > ---
> > > > v5:
> > > > 	update grant comment to simplify the cs_gpio management
> > > > 
> > > > Best Regards,
> > > > J.
> > > >  Documentation/devicetree/bindings/spi/spi-bus.txt |    6 ++
> > > >  drivers/spi/spi.c                                 |   55 +++++++++++++++++++-
> > > >  include/linux/spi/spi.h                           |    4 ++
> > > >  3 files changed, 62 insertions(+), 3 deletions(-)
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
> > > > index e782add..c253379 100644
> > > > --- a/Documentation/devicetree/bindings/spi/spi-bus.txt
> > > > +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
> > > > @@ -12,6 +12,7 @@ The SPI master node requires the following properties:
> > > >  - #size-cells     - should be zero.
> > > >  - compatible      - name of SPI bus controller following generic names
> > > >      		recommended practice.
> > > > +- cs-gpios	  - (optional) gpios chip select.
> > > >  No other properties are required in the SPI bus node.  It is assumed
> > > >  that a driver for an SPI bus device will understand that it is an SPI bus.
> > > >  However, the binding does not attempt to define the specific method for
> > > > @@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
> > > >  chip selects.  Individual drivers can define additional properties to
> > > >  support describing the chip select layout.
> > > >  
> > > > +If cs-gpios is used the number of chip select will automatically increased.
> > > > +
> > > >  SPI slave nodes must be children of the SPI master node and can
> > > >  contain the following properties.
> > > >  - reg             - (required) chip select address of device.
> > > > @@ -34,6 +37,9 @@ contain the following properties.
> > > >  - spi-cs-high     - (optional) Empty property indicating device requires
> > > >      		chip select active high
> > > >  
> > > > +If a gpio chipselect is used for the SPI slave the gpio number will be passed
> > > > +via the cs_gpio
> > > > +
> > > >  SPI example for an MPC5200 SPI bus:
> > > >  	spi at f00 {
> > > >  		#address-cells = <1>;
> > > > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> > > > index b2ccdea..446eee5 100644
> > > > --- a/drivers/spi/spi.c
> > > > +++ b/drivers/spi/spi.c
> > > > @@ -28,6 +28,7 @@
> > > >  #include <linux/mod_devicetable.h>
> > > >  #include <linux/spi/spi.h>
> > > >  #include <linux/of_spi.h>
> > > > +#include <linux/of_gpio.h>
> > > >  #include <linux/pm_runtime.h>
> > > >  #include <linux/export.h>
> > > >  
> > > > @@ -322,6 +323,7 @@ struct spi_device *spi_alloc_device(struct spi_master *master)
> > > >  	spi->dev.parent = &master->dev;
> > > >  	spi->dev.bus = &spi_bus_type;
> > > >  	spi->dev.release = spidev_release;
> > > > +	spi->cs_gpio = -EINVAL;
> > > >  	device_initialize(&spi->dev);
> > > >  	return spi;
> > > >  }
> > > > @@ -339,15 +341,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
> > > >  int spi_add_device(struct spi_device *spi)
> > > >  {
> > > >  	static DEFINE_MUTEX(spi_add_lock);
> > > > -	struct device *dev = spi->master->dev.parent;
> > > > +	struct spi_master *master = spi->master;
> > > > +	struct device *dev = master->dev.parent;
> > > >  	struct device *d;
> > > >  	int status;
> > > >  
> > > >  	/* Chipselects are numbered 0..max; validate. */
> > > > -	if (spi->chip_select >= spi->master->num_chipselect) {
> > > > +	if (spi->chip_select >= master->num_chipselect) {
> > > >  		dev_err(dev, "cs%d >= max %d\n",
> > > >  			spi->chip_select,
> > > > -			spi->master->num_chipselect);
> > > > +			master->num_chipselect);
> > > >  		return -EINVAL;
> > > >  	}
> > > >  
> > > > @@ -371,6 +374,9 @@ int spi_add_device(struct spi_device *spi)
> > > >  		goto done;
> > > >  	}
> > > >  
> > > > +	if (master->cs_gpios)
> > > > +		spi->cs_gpio = master->cs_gpios[spi->chip_select];
> > > > +
> > > 
> > > I still don't understand the need for this.  Only the master driver will need
> > > this data, and it is already stored in the master->cs_gpios array.  Why
> > > does it need to get duplicated into the spi_device?
> > yeah can drop it
> > > 
> > > >  	/* Drivers may modify this initial i/o setup, but will
> > > >  	 * normally rely on the device being setup.  Devices
> > > >  	 * using SPI_CS_HIGH can't coexist well otherwise...
> > > > @@ -561,6 +567,45 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
> > > >  }
> > > >  EXPORT_SYMBOL_GPL(spi_alloc_master);
> > > >  
> > > > +#ifdef CONFIG_OF
> > > > +static int of_spi_register_master(struct spi_master *master)
> > > > +{
> > > > +	int nb, i;
> > > > +	int *cs;
> > > > +	struct device_node *np = master->dev.of_node;
> > > > +
> > > > +	if (!np)
> > > > +		return 0;
> > > > +
> > > > +	nb = of_gpio_named_count(np, "cs-gpios");
> > > > +
> > > > +	if (nb < 1)
> > > > +		return 0;
> > > > +
> > > > +	cs = devm_kzalloc(&master->dev,
> > > > +			  sizeof(int) * (master->num_chipselect + nb),
> > > > +			  GFP_KERNEL);
> > > 
> > > sizeof(*cs)
> > > 
> > > > +	master->cs_gpios = cs;
> > > > +
> > > > +	if (!master->cs_gpios)
> > > > +		return -ENOMEM;
> > > > +
> > > > +	memset(cs, -EINVAL, master->num_chipselect);
> > > > +	master->num_chipselect += nb;
> > > 
> > > Looks buggy.  Should be:
> > > 	if (nb > master->num_chipselect)
> > > 		master->num_chipselect = nb;
> > > 
> > > However, this is actually quite risky.  Changing the size of
> > > num_chipselect without the driver knowing about it will most likely
> > > cause breakage in drivers.  Drivers may use it as an array index, and
> > > if it gets increased then there will be problems.  In fact, drivers
> > > are probably using spi->chip_select as an array or register index so I
> > > don't think it can be transparently extended to include gpios.
> > > 
> > > So, this function must change.  It cannot be called automatically
> > > from spi_register_master().  It needs to be a library function that spi bus
> > > drivers must call explicitly so they are prepared for a change in the
> > > num_chipselect value.
> > I'll prefer to let the spi framework manage it
> 
> I understand your preference, but it must not carry the risk of breakage.
so can we do this in two step add the new generic gpio management and them
make it manage by the spi framework when everyone switch to it
> 
> spi devices cannot be added if the cs number is larger than num_chipselect;
> even if those devices are backed by gpios.  The controller driver still
> needs to understand they are there and modify it's own num_chipselects
> value.  Otherwise transfer requests will pass a CS number larger than
> the bus drivers know what to do with.
> 
> > > Also, if we're doing this, then the gpio cs manipulation hook should be
> > > moved out of spi_bitbang and into the core spi_master.  There should
> > > also be a stock function for manipulating gpio chip selects. I don't want
> > > spi driver authors under the impression that they should open code the
> > > chip select manipulation.
> > yeah I was thinking about it too
> > 
> > how about we split it in two
> > 
> > num_hw_cs manage by the drivers
> > 
> > and
> > 
> > num_gpio_cs for cs gpio
> > 
> > and num_chipselect (hw + cs) will for internal use
> > 
> > the gpio cs will be after the hw cs.
> 
> As already discussed, don't split the number space.  Keep gpio cs numbers
> based at zero and let them overlap the hw cs numbers.
I did not want it, and agreed with the overlap

I just want to let drivers just manage the hw cs, the gpio one are manage by
the spi framework

Best Regards,
J.


From rnayak at ti.com  Mon Mar 12 11:02:38 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 12 Mar 2012 20:32:38 +0530
Subject: [PATCH v2 2/4] mmc: omap_hsmmc: Avoid a regulator voltage change with
 dt
In-Reply-To: <1331564560-23276-1-git-send-email-rnayak@ti.com>
References: <1331564560-23276-1-git-send-email-rnayak@ti.com>
Message-ID: <1331564560-23276-3-git-send-email-rnayak@ti.com>

When booting with Device tree, the omap_hsmmc driver does not
program the pbias cell (inside OMAP control module) during
a regulator voltage change.
In case of non-dt boot, this is handled using callbacks
from within platform_data and implemented in machine code.
To be able to do this with device tree, without invoking
any machine code, a OMAP control module driver is needed
which is yet missing.

The pbias cell is used to provide a 1.8v or 3.0v reference
to the mmc/sd/sdio1 interface supporting both 1.8v and 3.0v
voltages.

Until a OMAP control module driver is available to handle this,
when booting with a device tree blob, never change the regulator
voltage which might then require a pbias cell re-program.
There are 2 instances where in the mmc regulator voltage can be
changed.
-1- when the regulator is turned OFF.
-2- when attempting a switch to 1.8v from 3.0v for dual volt cards

This patch avoids a voltage change in both cases when booting from
device tree, and hence compromises on power savings.
Once the OMAP control module driver is available and hsmmc driver
is modified to then do pbias programming even when booting
with device tree, these limitaions can be removed to achieve better
power savings.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
---
 drivers/mmc/host/omap_hsmmc.c |   15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 38ae8c0..f29e1a2 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -244,6 +244,13 @@ static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
 	 */
 	if (!host->vcc)
 		return 0;
+	/*
+	 * With DT, never turn OFF the regulator. This is because
+	 * the pbias cell programming support is still missing when
+	 * booting with Device tree
+	 */
+	if (of_have_populated_dt() && !vdd)
+		return 0;
 
 	if (mmc_slot(host).before_set_reg)
 		mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
@@ -1516,7 +1523,13 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		 * of external transceiver; but they all handle 1.8V.
 		 */
 		if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
-			(ios->vdd == DUAL_VOLT_OCR_BIT)) {
+			(ios->vdd == DUAL_VOLT_OCR_BIT) &&
+			/*
+			 * With pbias cell programming missing, this
+			 * can't be allowed when booting with device
+			 * tree.
+			 */
+			(!of_have_populated_dt())) {
 				/*
 				 * The mmc_select_voltage fn of the core does
 				 * not seem to set the power_mode to
-- 
1.7.1



From plagnioj at jcrosoft.com  Sun Mar 11 14:38:56 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 11 Mar 2012 19:38:56 +0100
Subject: [PATCH v2 1/2] ARM: AT91: Add parameter for AT91_HAS_PATA
In-Reply-To: <1331415531-10961-1-git-send-email-alan@signal11.us>
References: <1331415380-10928-1-git-send-email-alan@signal11.us>
 <1331415531-10961-1-git-send-email-alan@signal11.us>
Message-ID: <20120311183856.GA13869@game.jcrosoft.org>

On 16:38 Sat 10 Mar     , Alan Ott wrote:
> Not all at91 chips have PATA, this parameter will identify which
> chips do. The determining of which chips support PATA was done
> by Arnd Bergmann.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Alan Ott <alan at signal11.us>
> CC: Ben Dooks <ben-linux at fluff.org>
> ---
>  arch/arm/mach-at91/Kconfig |   11 +++++++++++
>  1 files changed, 11 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index 71feb00..9eeeabe 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -24,6 +24,9 @@ config AT91_SAM9_ALT_RESET
>  config AT91_SAM9G45_RESET
>  	bool
>  
> +config AT91_HAS_PATA
> +	bool
what is the need for this?

As we switch to DT, I don't want to track the soc list in the Kconfig anymore
if the soc support the PATA will be describe in the DT

Best Regards,
J.


From rnayak at ti.com  Fri Mar  9 04:11:47 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 9 Mar 2012 14:41:47 +0530
Subject: [PATCH 2/4] ARM: OMAP2+: hsmmc: Split the clock src selection and
 pbias programming
In-Reply-To: <1331284309-22101-1-git-send-email-rnayak@ti.com>
References: <1331284309-22101-1-git-send-email-rnayak@ti.com>
Message-ID: <1331284309-22101-3-git-send-email-rnayak@ti.com>

While the pbias programming is something needed every time a regulator
output voltage is changed, the clock source selection to select between
an internal loopback and external clock seems like a one time setting.

These are today clubbed into a single platform callback, called from
the driver for every regulator voltage switch. Split these into seperate
callbacks and make the driver do this once at setup.

Also some platforms like AM35x seem to be doing this using a .set_power
callback, which seems completely orthogonal to what the callback is
expected to do.

Lastly, though the System control module has the registers to control
clock source selection, even on OMAP2430, the latest 2430 TRM version Z
clearly mentions in Table 7-135 and Table 7-154, that these bits are not
useful/used on OMAP2430. So get rid of control_devconf1_offset and just
use the OMAP3 based offsets for the register.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: Balaji TK <balajitk at ti.com>
Cc: Venkatraman S <svenkatr at ti.com>
Cc: Chris Ball <cjb at laptop.org>
---
 arch/arm/mach-omap2/hsmmc.c           |   86 ++++++++++++++-------------------
 arch/arm/plat-omap/include/plat/mmc.h |    1 +
 drivers/mmc/host/omap_hsmmc.c         |    3 +
 3 files changed, 40 insertions(+), 50 deletions(-)

diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 11e26fc..0133b29 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -27,7 +27,6 @@
 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 
 static u16 control_pbias_offset;
-static u16 control_devconf1_offset;
 static u16 control_mmc1;
 
 #define HSMMC_NAME_LEN	9
@@ -43,6 +42,32 @@ static int hsmmc_get_context_loss(struct device *dev)
 #define hsmmc_get_context_loss NULL
 #endif
 
+static void hsmmc1_select_input_clk_src(struct device *dev)
+{
+	u32 reg;
+	struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+	reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+	if (mmc->slots[0].internal_clock)
+		reg |= OMAP2_MMCSDIO1ADPCLKISEL;
+	else
+		reg &= ~OMAP2_MMCSDIO1ADPCLKISEL;
+	omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void hsmmc2_select_input_clk_src(struct device *dev)
+{
+	u32 reg;
+	struct omap_mmc_platform_data *mmc = dev->platform_data;
+
+	reg = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
+	if (mmc->slots[0].internal_clock)
+		reg |= OMAP2_MMCSDIO2ADPCLKISEL;
+	else
+		reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
+	omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
+}
+
 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
 				  int power_on, int vdd)
 {
@@ -72,12 +97,6 @@ static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
 			omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
 		}
 
-		if (mmc->slots[0].internal_clock) {
-			reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-			reg |= OMAP2_MMCSDIO1ADPCLKISEL;
-			omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
-		}
-
 		reg = omap_ctrl_readl(control_pbias_offset);
 		if (cpu_is_omap3630()) {
 			/* Set MMC I/O to 52Mhz */
@@ -171,17 +190,6 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
 	}
 }
 
-static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
-{
-	u32 reg;
-
-	reg = omap_ctrl_readl(control_devconf1_offset);
-	if (mmc->slots[0].internal_clock)
-		reg |= OMAP2_MMCSDIO2ADPCLKISEL;
-	else
-		reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
-	omap_ctrl_writel(reg, control_devconf1_offset);
-}
 
 static void hsmmc2_before_set_reg(struct device *dev, int slot,
 				   int power_on, int vdd)
@@ -190,26 +198,6 @@ static void hsmmc2_before_set_reg(struct device *dev, int slot,
 
 	if (mmc->slots[0].remux)
 		mmc->slots[0].remux(dev, slot, power_on);
-
-	if (power_on)
-		hsmmc2_select_input_clk_src(mmc);
-}
-
-static int am35x_hsmmc2_set_power(struct device *dev, int slot,
-				  int power_on, int vdd)
-{
-	struct omap_mmc_platform_data *mmc = dev->platform_data;
-
-	if (power_on)
-		hsmmc2_select_input_clk_src(mmc);
-
-	return 0;
-}
-
-static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
-							int vdd)
-{
-	return 0;
 }
 
 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
@@ -387,9 +375,6 @@ static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 			}
 		}
 
-		if (cpu_is_omap3517() || cpu_is_omap3505())
-			mmc->slots[0].set_power = nop_mmc_set_power;
-
 		/* OMAP3630 HSMMC1 supports only 4-bit */
 		if (cpu_is_omap3630() &&
 				(c->caps & MMC_CAP_8_BIT_DATA)) {
@@ -397,21 +382,25 @@ static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 			c->caps |= MMC_CAP_4_BIT_DATA;
 			mmc->slots[0].caps = c->caps;
 		}
+
+		if (mmc->controller_flags & OMAP_HSMMC_SUPPORTS_CLKSRC_SELECT)
+			mmc->select_input_clk_src = hsmmc1_select_input_clk_src;
 		break;
 	case 2:
-		if (cpu_is_omap3517() || cpu_is_omap3505())
-			mmc->slots[0].set_power = am35x_hsmmc2_set_power;
-
 		if (c->ext_clock)
 			c->transceiver = 1;
 		if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
 			c->caps &= ~MMC_CAP_8_BIT_DATA;
 			c->caps |= MMC_CAP_4_BIT_DATA;
 		}
-		if (mmc->controller_flags & OMAP_HSMMC_SUPPORTS_CLKSRC_SELECT) {
+
+		if (cpu_is_omap34xx()) {
 			mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
 			mmc->slots[0].after_set_reg = NULL;
 		}
+
+		if (mmc->controller_flags & OMAP_HSMMC_SUPPORTS_CLKSRC_SELECT)
+			mmc->select_input_clk_src = hsmmc2_select_input_clk_src;
 		break;
 	case 3:
 	case 4:
@@ -497,13 +486,10 @@ void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
 	omap_hsmmc_done = 1;
 
 	if (!cpu_is_omap44xx()) {
-		if (cpu_is_omap2430()) {
+		if (cpu_is_omap2430())
 			control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
-			control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
-		} else {
+		else
 			control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
-			control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
-		}
 	} else {
 		control_pbias_offset =
 			OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 5d9c98b..a155eb8 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -80,6 +80,7 @@ struct omap_mmc_platform_data {
 
 	/* Return context loss count due to PM states changing */
 	int (*get_context_loss_count)(struct device *dev);
+	void (*select_input_clk_src)(struct device *dev);
 
 	u64 dma_mask;
 
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index fd0c661..ce658e4 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -2020,6 +2020,9 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
 		}
 	}
 
+	if (pdata->select_input_clk_src)
+		pdata->select_input_clk_src(&pdev->dev);
+
 	if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
 		ret = omap_hsmmc_reg_get(host);
 		if (ret)
-- 
1.7.1



From rnayak at ti.com  Fri Mar  9 04:11:46 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 9 Mar 2012 14:41:46 +0530
Subject: [PATCH 1/4] ARM: OMAP2+: hsmmc: Add a flag to identify modules
 supporting clock src selection
In-Reply-To: <1331284309-22101-1-git-send-email-rnayak@ti.com>
References: <1331284309-22101-1-git-send-email-rnayak@ti.com>
Message-ID: <1331284309-22101-2-git-send-email-rnayak@ti.com>

hsmmc2_before_set_reg() seems to do a clock source selection (supported
only on some mmc IP blocks) but decides to do so based on a 'HSMMC_HAS_PBIAS'
feature flag which seems completely wrong. Fix this by adding a new controller
flag 'OMAP_HSMMC_SUPPORTS_CLKSRC_SELECT' which can be then used to identify which
controller instance supports this feature.

Looking at the TRM for OMAP2/3/4, it turns out only the 2 controller instances on
OMAP3 support this, so update this flag in the .dev_attr structure for the
corresponding hwmods.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: Balaji TK <balajitk at ti.com>
Cc: Venkatraman S <svenkatr at ti.com>
Cc: Chris Ball <cjb at laptop.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Benoit Cousson <b-cousson at ti.com>
---
 arch/arm/mach-omap2/hsmmc.c                |   15 +++++++--------
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   14 +++++++++++---
 arch/arm/plat-omap/include/plat/mmc.h      |    1 +
 3 files changed, 19 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 19dd165..11e26fc 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -408,8 +408,7 @@ static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 			c->caps &= ~MMC_CAP_8_BIT_DATA;
 			c->caps |= MMC_CAP_4_BIT_DATA;
 		}
-		if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
-			/* off-chip level shifting, or none */
+		if (mmc->controller_flags & OMAP_HSMMC_SUPPORTS_CLKSRC_SELECT) {
 			mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
 			mmc->slots[0].after_set_reg = NULL;
 		}
@@ -447,12 +446,6 @@ void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
 		goto done;
 	}
 
-	if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
-		pr_err("%s fails!\n", __func__);
-		goto done;
-	}
-	omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
-
 	name = "omap_hsmmc";
 
 	l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
@@ -471,6 +464,12 @@ void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
 		mmc_data->controller_flags = mmc_dev_attr->flags;
 	}
 
+	if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
+		pr_err("%s fails!\n", __func__);
+		goto done;
+	}
+	omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
+
 	pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
 		sizeof(struct omap_mmc_platform_data), NULL, 0, false);
 	if (IS_ERR(pdev)) {
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3c8dd92..236785f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3145,13 +3145,15 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
 };
 
 static struct omap_mmc_dev_attr mmc1_dev_attr = {
-	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+	.flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
+		  OMAP_HSMMC_SUPPORTS_CLKSRC_SELECT),
 };
 
 /* See 35xx errata 2.1.1.128 in SPRZ278F */
 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
 	.flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
-		  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
+		  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ |
+		  OMAP_HSMMC_SUPPORTS_CLKSRC_SELECT),
 };
 
 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
@@ -3219,9 +3221,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
 	&omap3xxx_l4_core__mmc2,
 };
 
+static struct omap_mmc_dev_attr mmc2_dev_attr = {
+	.flags = OMAP_HSMMC_SUPPORTS_CLKSRC_SELECT,
+};
+
 /* See 35xx errata 2.1.1.128 in SPRZ278F */
 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
-	.flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
+	.flags = (OMAP_HSMMC_BROKEN_MULTIBLOCK_READ |
+		  OMAP_HSMMC_SUPPORTS_CLKSRC_SELECT),
 };
 
 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
@@ -3262,6 +3269,7 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
 			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
 		},
 	},
+	.dev_attr	= &mmc2_dev_attr,
 	.slaves		= omap3xxx_mmc2_slaves,
 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_mmc2_slaves),
 	.class		= &omap34xx_mmc_class,
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index f75946c..5d9c98b 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -49,6 +49,7 @@
  */
 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT		BIT(0)
 #define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ	BIT(1)
+#define OMAP_HSMMC_SUPPORTS_CLKSRC_SELECT	BIT(2)
 
 struct omap_mmc_dev_attr {
 	u8 flags;
-- 
1.7.1



From rnayak at ti.com  Mon Mar 12 01:53:41 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 12 Mar 2012 11:23:41 +0530
Subject: [PATCHv5 0/6] ARM: OMAP3+: IO daisy chain support fixes
In-Reply-To: <alpine.DEB.2.00.1203092102450.30879@utopia.booyaka.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203092102450.30879@utopia.booyaka.com>
Message-ID: <4F5D8F65.7000205@ti.com>

On Saturday 10 March 2012 09:35 AM, Paul Walmsley wrote:
> The main outstanding question is whether the OMAP4 WUCLKOUT poll should be
> removed to match the v5 changes to the OMAP3 function.  Please let me
> know.   Any other testing or comments are of course welcome.

I think we should instead add it back in omap3 and keep the omap4 as is.



From plagnioj at jcrosoft.com  Mon Mar 12 10:38:25 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 12 Mar 2012 15:38:25 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <1331561157-3820-1-git-send-email-sr@denx.de>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
Message-ID: <20120312143825.GB13869@game.jcrosoft.org>

On 15:05 Mon 12 Mar     , Stefan Roese wrote:
> This patch adds support to configure the STMMAC ethernet driver via
> device-tree instead of platform_data.
> 
> Currently, only the properties needed on SPEAr600 are provided. All
> other properties should be added once needed on other platforms.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> ---
>  Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
>  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66 +++++++++++++++++++-
>  2 files changed, 103 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt
> 
> diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
> new file mode 100644
> index 0000000..386a47f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/stmmac.txt
> @@ -0,0 +1,38 @@
> +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
> +
> +Required properties:
> +- compatible: Should be "stm,gmac"
this IP have 2 version at least the GMAC for the second generation and mac for
the first generation
> +- reg: Address and length of the register set for the device
> +- interrupt-parent: Should be the phandle for the interrupt controller
> +  that services interrupts for this device
> +- interrupts: Should contain the STMMAC interrupts
> +- interrupt-names: Should contain the interrupt names "macirq"
> +  "eth_wake_irq" if this interrupt is supported in the "interrupts"
> +  property
optionnal
> +- phy-mode: String, operation mode of the PHY interface.
> +  Supported values are: "mii", "rmii", "gmii", "rgmii".
> +- phy-addr: MDIO address of the PHY
> +
> +Optional properties:
> +- stm,prog-burst-len: Specify the burst length
> +- stm,has-gmac: Indicates that the controller supports 1000Mbps
this IP support more mode 10/100/300/1000
> +- stm,has-pmt: Indicates that the controller supports power management
> +- mac-address: 6 bytes, mac address
> +
> +Examples:
> +
> +	gmac0: stmmac at e0800000 {
> +		compatible = "stm,gmac";
> +		reg = <0xe0800000 0x8000>;
> +		interrupt-parent = <&vic1>;
> +		interrupts = <24 23>;
> +		interrupt-names = "macirq", "eth_wake_irq";
> +		mac-address = [000000000000]; /* Filled in by U-Boot */
> +
> +		stm,prog-burst-len = <8>;
> +		stm,has-gmac;
> +		stm,has-pmt;
> +
> +		phy-mode = "gmii";
> +		phy-addr = <0>;
> +	};
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> index 3aad981..fcf46c7 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> @@ -24,8 +24,43 @@
>  
>  #include <linux/platform_device.h>
>  #include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_net.h>
>  #include "stmmac.h"
>  
> +#ifdef CONFIG_OF
> +static int __devinit stmmac_probe_config_dt(struct platform_device *pdev,
> +					    struct plat_stmmacenet_data *plat,
> +					    const char **mac)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +
> +	if (!np)
> +		return -ENODEV;
> +
> +	*mac = of_get_mac_address(np);
> +
> +	plat->interface = of_get_phy_mode(np);
> +	of_property_read_u32(np, "phy-addr", &plat->phy_addr);
> +	plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
> +					   sizeof(struct stmmac_mdio_bus_data),
> +					   GFP_KERNEL);
> +
> +	/*
> +	 * Currently only the properties needed on SPEAr600
> +	 * are provided. All other properties should be added
> +	 * once needed on other platforms.
> +	 */
> +	of_property_read_u32(np, "stm,prog-burst-len", &plat->pbl);
> +	if (of_get_property(np, "stm,has-gmac", NULL))
> +		plat->has_gmac = 1;
> +	if (of_get_property(np, "stm,has-pmt", NULL))
> +		plat->pmt = 1;
> +
> +	return 0;
> +}
> +#endif /* CONFIG_OF */
> +
>  /**
>   * stmmac_pltfr_probe
>   * @pdev: platform device pointer
> @@ -39,7 +74,8 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>  	struct resource *res;
>  	void __iomem *addr = NULL;
>  	struct stmmac_priv *priv = NULL;
> -	struct plat_stmmacenet_data *plat_dat;
> +	struct plat_stmmacenet_data *plat_dat = NULL;
> +	const char *mac = NULL;
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	if (!res)
> @@ -58,6 +94,22 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>  		ret = -ENOMEM;
>  		goto out_release_region;
>  	}
> +
> +#ifdef CONFIG_OF
> +	plat_dat = devm_kzalloc(&pdev->dev, sizeof(struct plat_stmmacenet_data),
> +				GFP_KERNEL);
> +	if (!plat_dat) {
> +		pr_err("%s: ERROR: no memory", __func__);
> +		ret = -ENOMEM;
> +		goto out_unmap;
> +	}
> +
> +	ret = stmmac_probe_config_dt(pdev, plat_dat, &mac);
> +	if (ret) {
> +		pr_err("%s: main dt probe failed", __func__);
> +		goto out_unmap;
> +	}
> +#else
This must be check at runtime, we can boot a kernel with or without DT.

Best Reards,
J.
>  	plat_dat = pdev->dev.platform_data;
>  
>  	/* Custom initialisation (if needed)*/
> @@ -66,6 +118,7 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>  		if (unlikely(ret))
>  			goto out_unmap;
>  	}
> +#endif
>  
>  	priv = stmmac_dvr_probe(&(pdev->dev), plat_dat, addr);
>  	if (!priv) {
> @@ -73,6 +126,10 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>  		goto out_unmap;
>  	}
>  
> +	/* Get MAC address if available (DT) */
> +	if (mac)
> +		memcpy(priv->dev->dev_addr, mac, ETH_ALEN);
> +
>  	/* Get the MAC information */
>  	priv->dev->irq = platform_get_irq_byname(pdev, "macirq");
>  	if (priv->dev->irq == -ENXIO) {
> @@ -178,6 +235,12 @@ static const struct dev_pm_ops stmmac_pltfr_pm_ops = {
>  static const struct dev_pm_ops stmmac_pltfr_pm_ops;
>  #endif /* CONFIG_PM */
>  
> +static const struct of_device_id stmmac_dt_ids[] = {
> +	{ .compatible = "stm,gmac", },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, stmmac_dt_ids);
> +
>  static struct platform_driver stmmac_driver = {
>  	.probe = stmmac_pltfr_probe,
>  	.remove = stmmac_pltfr_remove,
> @@ -185,6 +248,7 @@ static struct platform_driver stmmac_driver = {
>  		   .name = STMMAC_RESOURCE_NAME,
>  		   .owner = THIS_MODULE,
>  		   .pm = &stmmac_pltfr_pm_ops,
> +		   .of_match_table = of_match_ptr(stmmac_dt_ids),
>  		   },
>  };
>  
> -- 
> 1.7.9.2
> 
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
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> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From rnayak at ti.com  Mon Mar 12 11:02:36 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 12 Mar 2012 20:32:36 +0530
Subject: [PATCH v2 0/4] omap hsmmc device tree support
Message-ID: <1331564560-23276-1-git-send-email-rnayak@ti.com>

The series adds device tree support for OMAP hsmmc
driver.

Changes in V2:
-1- Minor fixes based on comments from Grant.
-2- Added a seperate compatible for omap3.
-3- Added a new binding "ti,needs-special-reset"
to handle some mmc modules which need special
softreset sequence.
-4- Updated board dts files with "status = disable;"
for unused mmc modules.

Rob,
I retained your ack on patch 1 despite the additional
binding that I added to handle the special softreset
sequence. Let me know if you have any issues with it.

Chris.
Patch 1 and Patch 2 apply cleanly on mmc-next and can
be taken in from the mmc tree after relevent acks from
DT folks.
Patch 3 and Patch 4 which update dts files, I plan to
push via linux-omap/Tony's tree.

The series is tested on omap4sdp (both external and emmc),
omap4panda amd omap3beagle boards.

Things to do:
-1- Card detect isn't functional and needs twl4030 gpio
to be DT converted.
-2- pbias cell programming is missing and needs an OMAP
control module driver.

Rajendra Nayak (4):
  mmc: omap_hsmmc: Convert hsmmc driver to use device tree
  mmc: omap_hsmmc: Avoid a regulator voltage change with dt
  arm/dts: OMAP4: Add mmc controller nodes and board data
  arm/dts: OMAP3: Add mmc controller nodes and board data

 .../devicetree/bindings/mmc/ti-omap-hsmmc.txt      |   33 +++++++
 arch/arm/boot/dts/omap3-beagle.dts                 |   14 +++
 arch/arm/boot/dts/omap3.dtsi                       |   16 ++++
 arch/arm/boot/dts/omap4-panda.dts                  |   22 +++++
 arch/arm/boot/dts/omap4-sdp.dts                    |   24 ++++++
 arch/arm/boot/dts/omap4.dtsi                       |   31 +++++++
 drivers/mmc/host/omap_hsmmc.c                      |   88 +++++++++++++++++++-
 7 files changed, 227 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt



From rnayak at ti.com  Mon Mar 12 11:02:40 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 12 Mar 2012 20:32:40 +0530
Subject: [PATCH v2 4/4] arm/dts: OMAP3: Add mmc controller nodes and board data
In-Reply-To: <1331564560-23276-1-git-send-email-rnayak@ti.com>
References: <1331564560-23276-1-git-send-email-rnayak@ti.com>
Message-ID: <1331564560-23276-5-git-send-email-rnayak@ti.com>

Add omap mmc related device tree data for OMAP3.
Currenly limited to only omap3-beagle board.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/boot/dts/omap3-beagle.dts |   14 ++++++++++++++
 arch/arm/boot/dts/omap3.dtsi       |   16 ++++++++++++++++
 2 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 714ba5d..5cf67d1 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -47,3 +47,17 @@
 		reg = <0x50>;
 	};
 };
+
+&mmc1 {
+	vmmc-supply = <&vmmc1>;
+	vmmc_aux-supply = <&vsim>;
+	ti,bus-width = <8>;
+};
+
+&mmc2 {
+	status = "disable";
+};
+
+&mmc3 {
+	status = "disable";
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index ca37ba5..3892e34 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -113,5 +113,21 @@
 			#size-cells = <0>;
 			ti,hwmods = "i2c3";
 		};
+
+		mmc1: mmc at 1 {
+			compatible = "ti,omap3-hsmmc";
+			ti,hwmods = "mmc1";
+			ti,dual-volt;
+		};
+
+		mmc2: mmc at 2 {
+			compatible = "ti,omap3-hsmmc";
+			ti,hwmods = "mmc2";
+		};
+
+		mmc3: mmc at 3 {
+			compatible = "ti,omap3-hsmmc";
+			ti,hwmods = "mmc3";
+		};
 	};
 };
-- 
1.7.1



From plagnioj at jcrosoft.com  Fri Mar  9 11:36:08 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 9 Mar 2012 17:36:08 +0100
Subject: [PATCH 1/1] of: introduce helper to manage boolean
In-Reply-To: <20120309162638.92E813E0880@localhost>
References: <1328588028-24766-1-git-send-email-plagnioj@jcrosoft.com>
 <20120309014441.8236B3E0903@localhost>
 <20120309100435.GN27213@game.jcrosoft.org>
 <20120309162638.92E813E0880@localhost>
Message-ID: <20120309163608.GQ27213@game.jcrosoft.org>

> > > > +int of_property_read_bool(const struct device_node *np, const char *propname)
> > > > +{
> > > > +	u32 reg;
> > > > +	int ret = of_property_read_u32(np, propname, &reg);
> > > > +
> > > > +	switch (ret) {
> > > > +	case -EINVAL:
> > > > +		return false;
> > > > +	case -ENODATA:
> > > > +		return true;
> > > > +	case 0:
> > > > +		return reg == 1;
> > > 
> > > Ugh.  so any value other than 1 returns false?  I think that will surprise
> > > most people.
> > > 
> > > I don't like this api or binding.  If it is a bool property, then why isn't
> > > simply testing for the property existance sufficient?
> > no if you want to disable it
> > 
> > if a bool is define in the dtsi and want to disable it int the dts
> > 
> > if you we can do the the invert
> > 
> > if !0 => true
> > 
> > is-ok;			=> true
> > is-ok = <val != 0>;	=> true
> > is-ok = <0>;		=> false
> 
> This is a failure of the dtc tool, not the binding.  Accepting this binding
> means we have to live with it for a very long time.  It needs to be fixed
> in dtc instead so that properties can be deleted instead of only modified.
I understand your idea but today if you put and value in the property it's true.

So is-ok = <0>; is true also which is illogical as in any language a boolean is
true (1) or false (0). When I read the property I will understand false not true

And I see no good way to add the "delete" in dtc.

Best Regards,
J.


From rnayak at ti.com  Mon Mar 12 01:50:50 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 12 Mar 2012 11:20:50 +0530
Subject: [PATCHv5 2/6] ARM: OMAP3 PM: Move IO Daisychain function to omap3
 prm file
In-Reply-To: <alpine.DEB.2.00.1203091737390.30879@utopia.booyaka.com>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>
 <1331046702-2472-3-git-send-email-t-kristo@ti.com>
 <alpine.DEB.2.00.1203091737390.30879@utopia.booyaka.com>
Message-ID: <4F5D8EBA.3060602@ti.com>

On Saturday 10 March 2012 06:10 AM, Paul Walmsley wrote:
> cc Rajendra
>
> Hi Tero,
>
> a few comments:
>
> On Tue, 6 Mar 2012, Tero Kristo wrote:
>
> ...
>
>> +/* OMAP3 Daisychain enable sequence */
>> +void omap3_trigger_io_chain(void)
>> +{
>> +	int i = 0;
>> +
>> +	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
>> +				   PM_WKEN);
>> +	/* Do a readback to assure write has been done */
>> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
>
> Looks like this barrier shouldn't be needed?  The write is immediately
> followed by another read from the same IP block.
>
>> +
>> +	omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST)&
>> +			  OMAP3430_ST_IO_CHAIN_MASK,
>> +			  MAX_IOPAD_LATCH_TIME, i);
>> +
>> +	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
>> +				     PM_WKEN);
>> +
>> +	omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
>> +				     PM_WKST);
>> +
>> +	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
>> +}
>
> I see that you removed the second timeout test from this code, but not
> from the OMAP4 version.  Any reason why?  Seems like if the second timeout
> can be removed from one, then it can also be removed from the other?

Actually FWIK, its nteeded in both OMAP3 and OMAP4. The OMAP3
documentation does no mention about it. but that is just bad
documentation.

>
>
> - Paul



From rnayak at ti.com  Mon Mar 12 06:15:21 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 12 Mar 2012 15:45:21 +0530
Subject: [PATCHv5 2/6] ARM: OMAP3 PM: Move IO Daisychain function to omap3
 prm file
In-Reply-To: <1331543948.2116.259.camel@sokoban>
References: <1331046702-2472-1-git-send-email-t-kristo@ti.com>	
 <1331046702-2472-3-git-send-email-t-kristo@ti.com>	
 <alpine.DEB.2.00.1203091737390.30879@utopia.booyaka.com>	
 <4F5D8EBA.3060602@ti.com> <1331543948.2116.259.camel@sokoban>
Message-ID: <4F5DCCB9.900@ti.com>

Hi Tero,

On Monday 12 March 2012 02:49 PM, Tero Kristo wrote:
>>> I see that you removed the second timeout test from this code, but not
>>> >  >  from the OMAP4 version.  Any reason why?  Seems like if the second timeout
>>> >  >  can be removed from one, then it can also be removed from the other?
>> >
>> >  Actually FWIK, its nteeded in both OMAP3 and OMAP4. The OMAP3
>> >  documentation does no mention about it. but that is just bad
>> >  documentation.
> Both documentation and actual functionality appears to be different for
> OMAP3 / OMAP4. The status bit on OMAP3 is read / write, and writing 1 to
> it clears it. On OMAP4, it is read only and both values 0 / 1 indicate
> something has happened. On OMAP3 the bit must be cleared by writing 1 to
> it, otherwise it remains high indefinitely and will break all the
> subsequent trigger calls. Also, clearing EN_IO_CHAIN on OMAP3 does not
> appear to trigger any activity that would change the status of
> ST_IO_CHAIN, so there is nothing to poll at the end.
>
> Here is a sample trace I just generated for the trigger on OMAP3:
>
> [    7.707824] omap3_trigger_io_chain(1): PM_WKST=00000000
> [    7.707855] omap3_trigger_io_chain(2): PM_WKST=00000000
> [    7.707855] omap3_trigger_io_chain(3): PM_WKST=00010000
> [    7.707885] omap3_trigger_io_chain(4): PM_WKST=00000000
> [    7.707977] omap3_trigger_io_chain(5): PM_WKST=00000000
>
> 1 = enter trigger function
> 2 = just after enabling io chain
> 3 = just after first poll loop
> 4 = just after clear of io status and disabling of io chain
> 5 = after udelay(100) from last event (you can see the status bit never
> raises)

Ok, I guess then the omap3 and omap4 implementations are indeed
different and should be handled differently. Thanks for the explanation.

regards,
Rajendra

>
> So, you can see that there is no change in the status bit between 4...5,
> so there is no point for polling anything there. I even tried changing
> the clear of IO status and disabling of IO chain to see if it had any
> impact on this result but no. The main point is that we must clear the
> status bit at #4, and thus polling for it to change at #5 makes no
> sense. We just need to force the register writes to PRCM by doing some
> access to the IP block.
>
>
> Looking at similar trace on omap4:
>
> [    8.097503] omap4_trigger_io_chain(1): IO=00010020
> [    8.097503] omap4_trigger_io_chain(2): IO=00010320
> [    8.097534] omap4_trigger_io_chain(3): IO=00010320
> [    8.097534] omap4_trigger_io_chain(4): IO=00010020
> [    8.097534] omap4_trigger_io_chain(5): IO=00010020
>
> 1 = enter function
> 2 = just after enabling WUCLK_CTRL
> 3 = just after poll
> 4 = just after disabling WUCLK_CTRL
> 5 = just after poll
>
> Well, the status bit follows the state of the WUCLK_CTRL, but there is
> no time to actually poll the registers it seems, their state has already
> changed when the value from first read arrives back as the register
> access itself is so slow. But... we are not manually clearing the status
> bit, thus polling kind of makes sense (and it might make more sense if
> some future version of PRCM would allow faster register access.)
>
> I also did both of these tests by caching the register values to memory
> (no immediate printks to avoid delays) but the results are still the
> same.
>



From rnayak at ti.com  Fri Mar  9 04:36:56 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Fri, 09 Mar 2012 15:06:56 +0530
Subject: [PATCH v2 4/4] arm/dts: OMAP3: Add mmc controller nodes and board
 data
In-Reply-To: <alpine.DEB.2.00.1203082348200.26656@utopia.booyaka.com>
References: <1329998490-27555-1-git-send-email-rnayak@ti.com>
 <1329998490-27555-5-git-send-email-rnayak@ti.com>
 <20120223185718.GZ18185@atomide.com> <4F470B71.1020308@ti.com>
 <20120224184859.GN18185@atomide.com> <20120309054608.647473E0901@localhost>
 <alpine.DEB.2.00.1203082348200.26656@utopia.booyaka.com>
Message-ID: <4F59CF38.6090706@ti.com>

Hi Paul,

On Friday 09 March 2012 12:21 PM, Paul Walmsley wrote:
> On Thu, 8 Mar 2012, Grant Likely wrote:
>
>> Yes, absolutely use separate compatible values.  It is always important
>> to be specific as to the silicon implementing the IP.
>
> In that case, it is probably best to use the full chip name in the
> compatible string, e.g., omap2420 or omap2430 rather than just "omap2".

Since omap2420 and omap2430 have different MMC controllers (and these
bindings only cover the hsmmc controller used in 2430 and beyond, I
haven't done the bindings for the legacy one yet), the idea was
to differentiate between omap2420 and omap2430 by using
compatible of "ti,omap2-hsmmc" for the High-Speed controller used in
OMAP2 (2430) and "ti,omap2-mmc" for the legacy one used in OMAP2 (2420).
Does that sound good to you?

> Particularly in the case of "OMAP3," which is a largely meaningless group
> these days with AM33xx, OMAP34xx, OMAP36xx, and AM3517, many of which are
> quite different from each other...

But these bindings are specific and limited to HSMMC module which is
not quite different in the different SoC variants. There is a single
driver to handle hsmmc module on all the SoCs which does not need to
differentiate which SoC it is on.

regards,
Rajendra

>
>
> - Paul



From plagnioj at jcrosoft.com  Mon Mar 12 13:44:49 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 12 Mar 2012 18:44:49 +0100
Subject: [PATCH 1/2] ARM: Add Kconfig option to use mkimage -T
 kernel_noload
In-Reply-To: <201203121840.49776.marek.vasut@gmail.com>
References: <1330473804-23348-1-git-send-email-swarren@nvidia.com>
 <4F4E6F96.8080907@am.sony.com>
 <20120229185013.GJ3318@game.jcrosoft.org>
 <201203121840.49776.marek.vasut@gmail.com>
Message-ID: <20120312174449.GG13869@game.jcrosoft.org>

On 18:40 Mon 12 Mar     , Marek Vasut wrote:
> Dear Jean-Christophe PLAGNIOL-VILLARD,
> 
> > On 10:33 Wed 29 Feb     , Tim Bird wrote:
> > > On 02/29/2012 10:14 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > > On 08:58 Wed 29 Feb     , Stephen Warren wrote:
> > > >> Jean-Christophe PLAGNIOL-VILLARD wrote at Wednesday, February 29, 2012 
> 5:30 AM:
> > > >>> On 17:03 Tue 28 Feb     , Stephen Warren wrote:
> > > >>>> uImage files typically encode a single absolute load and entry
> > > >>>> address. This is inconvenient when attempting to share that uImage
> > > >>>> across multiple SoCs with different physical RAM addresses. Recent
> > > >>>> versions of mkimage implement a "kernel_noload" image type which
> > > >>>> encodes no absolute load address, and a relative entry address.
> > > >>>> This works well for uImage-wrapped ARM zImages, since they are
> > > >>>> relocatable.
> > > >>>> 
> > > >>>> This is enabled by commit b9b50e89d317c58becd0e2d7fac2e21e3a81dd0a
> > > >>>> "image: Implement IH_TYPE_KERNEL_NOLOAD" in U-Boot.
> > > >>>> 
> > > >>>> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> > > >>>> ---
> > > >>>> I assume I should put this into the ARM patch tracker if it's OK?
> > > >>> 
> > > >>> Again a new option for uImage no why not just boot the zImage
> > > >>> 
> > > >>> in this case the uImage is useless
> > > >> 
> > > >> U-Boot doesn't support zImage at present.
> > > >> 
> > > >> A patch was posted to support it at least for ARM, but needed a little
> > > >> work before it could be committed.
> > > > 
> > > > Sorry I see no advantage to have the uImage build by the kernel anymore
> > > > as we have a relocatable zImage
> > > > 
> > > > I'll even drop its support
> > > 
> > > This seems at least premature, and possibly ill-advised in general.
> > > There are lots of U-Boot images out in the field, many of which that
> > > are rarely updated. A lot of workflow will be disrupted unnecessarily
> > > by a change like this.
> > > 
> > > Could you wait to drop uImage build support in the kernel until
> > > U-Boot supports zImage, and has worked it's way into the field
> > > for a few years?
> > 
> > I'm fine to keep for now on but not to add new feature
> > 
> > Barebox (former U-Boot v2) support zImage for quite a while and
> > relocable one for too.
> 
> On the other hand, noone uses barebox and you should stop with this obvious 
> malice towards uboot please. I believe for most people it's easier to spend time 
> only on implementing their hardware support into U-Boot, not waste time 
> implementing basic components that are still missing in barebox.
Speak for yourself please
> 
> Last but not least, the uImage contains additional checksum on the whole image, 
> which is useful on flash media.
>
> That said, I'm all for having uImage support in kernel and for adding this 
> NOLOAD option.
I'm going to repeat myself, we work on kernel here NOT bootloader specific bla
bla. The standard image for the kernel is zImage. After if you want to use
your specifc bootloader stuff do it outside of the kernel.

My comment is the same for ANY bootloader. Do your specifc stuff at your place
not HERE.

Best Regards,
J.


From plagnioj at jcrosoft.com  Fri Mar  9 06:40:02 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 9 Mar 2012 12:40:02 +0100
Subject: [PULL] of nand generic binding
In-Reply-To: <20120309014439.235C23E0901@localhost>
References: <20120217155707.GR1214@game.jcrosoft.org>
 <20120229152534.GH3318@game.jcrosoft.org>
 <20120307082945.GJ21255@game.jcrosoft.org>
 <4F576602.8020808@gmail.com> <20120309014439.235C23E0901@localhost>
Message-ID: <20120309114002.GP27213@game.jcrosoft.org>

On 18:44 Thu 08 Mar     , Grant Likely wrote:
> On Wed, 07 Mar 2012 07:43:30 -0600, Rob Herring <robherring2 at gmail.com> wrote:
> > On 03/07/2012 02:29 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 16:25 Wed 29 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> > >> On 16:57 Fri 17 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> > >>> HI,
> > >>>
> > >>> 	please find attached the generic binding for the MTD nand
> > >>>
> > >>> 	This will add boolean and nand helpers
> > >> is it ok?
> > > I need this for 3.4
> > > 
> > > will you apply it or can I apply it via AT91
> > 
> > Looks fine to me and Grant acked it, so go ahead and take with your at91
> > branch.
> 
> Actually, taking another look at the of_mtd patch, that stuff really
> belongs in the drivers/mtd directory.  I'm not nacking the patch, but
> you should send a follow up to move it into the correct place.
ok

Best Regards,
J.


From khilman at ti.com  Mon Mar 12 19:28:31 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 12 Mar 2012 16:28:31 -0700
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators for
 v3.4
In-Reply-To: <20120312173215.GL3110@opensource.wolfsonmicro.com> (Mark Brown's
 message of "Mon, 12 Mar 2012 17:32:16 +0000")
References: <877gywjhht.fsf@ti.com> <20120308021843.GQ12083@atomide.com>
 <87399jc6cj.fsf@ti.com> <20120309003217.GB12083@atomide.com>
 <20120309114731.GA3273@opensource.wolfsonmicro.com>
 <87zkbp4wtj.fsf@ti.com>
 <20120311204232.GC3171@opensource.wolfsonmicro.com>
 <87399dzq5e.fsf@ti.com>
 <20120312173215.GL3110@opensource.wolfsonmicro.com>
Message-ID: <87pqchv1pc.fsf@ti.com>

Mark Brown <broonie at opensource.wolfsonmicro.com> writes:

> On Mon, Mar 12, 2012 at 10:26:53AM -0700, Kevin Hilman wrote:
>> Mark Brown <broonie at opensource.wolfsonmicro.com> writes:
>
>> > The branch itself is essentially stable but I'm not enthused about the
>> > idea of merging the whole thing via the OMAP tree.  
>
>> Right, I wasn't suggesting we merge it via OMAP tree.   I was just
>> looking for a stable point we could use as s dependency when merging
>> everything together for the arm-soc tree.
>
> Well, if you don't base the OMAP changes that depend on it off the
> regulator changes then you'll break bisection as you'll have a bunch of
> commits which won't have all their dependencies present on a branch
> (since they're not present in the branch point and aren't otherwise
> merged in), if bisect goes down that branch it'll be miserable.  That
> seems bad and while I've not run into it with OMAP in particular it's
> rather painful when it does happen.
>
> It's much better if the branch has the required changes merged into it
> prior to their being used.

OK.

Tony, updated pull request below.  This includes all the TWL depencies
merged from the 'topic/twl' tag in Mark's tree.

Kevin


The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:

  Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/pm/smps-regulator

for you to fetch changes up to 39358f2b57f37fe079eff4159307c844a0bfb176:

  Merge branch 'pm-wip/smps-regulator' into for_3.4/pm/smps-regulator (2012-03-12 15:36:45 -0700)

----------------------------------------------------------------

Kevin Hilman (3):
      ARM: OMAP2+: voltage: ensure voltage used is exact voltage from OPP table
      Merge tag 'topic/twl' into for_3.4/pm/smps-regulator
      Merge branch 'pm-wip/smps-regulator' into for_3.4/pm/smps-regulator

Laxman Dewangan (1):
      regulator: twl6030: Fix voltage selection logic

Peter Ujfalusi (2):
      regulator: twl-regulator: Add fixed LDO for V1V8, V2V1 supply
      mfd: twl-core: regulator configuration for twl6030 V1V8, V2V1 SMPS

Rajendra Nayak (1):
      regulator: twl: adapt twl-regulator driver to dt

Tero Kristo (6):
      arm: omap3: voltage: fix channel configuration
      arm: omap3: add common twl configurations for vdd1 and vdd2
      arm: omap3: twl: add external controllers for core voltage regulators
      arm: omap4: add common twl configurations for vdd1, vdd2 and vdd3
      regulator: twl4030: add support for external voltage get/set
      regulator: twl6030: add support for vdd1, vdd2 and vdd3 regulators

 .../bindings/regulator/twl-regulator.txt           |   68 ++++
 arch/arm/mach-omap2/twl-common.c                   |  147 +++++++++
 arch/arm/mach-omap2/vc3xxx_data.c                  |    1 +
 arch/arm/mach-omap2/voltage.c                      |   21 +-
 drivers/mfd/twl-core.c                             |   41 ++-
 drivers/regulator/twl-regulator.c                  |  327 +++++++++++++++-----
 include/linux/i2c/twl.h                            |   14 +-
 7 files changed, 532 insertions(+), 87 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/twl-regulator.txt


From linux at arm.linux.org.uk  Mon Mar 12 19:28:19 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 12 Mar 2012 23:28:19 +0000
Subject: [PATCH v6 1/3] USB: OHCI-HCD: Rename ohci-pnx4008 to ohci-nxp
In-Reply-To: <1331430375-31227-2-git-send-email-stigge@antcom.de>
References: <1331430375-31227-1-git-send-email-stigge@antcom.de>
 <1331430375-31227-2-git-send-email-stigge@antcom.de>
Message-ID: <20120312232819.GD10830@n2100.arm.linux.org.uk>

On Sun, Mar 11, 2012 at 02:46:13AM +0100, Roland Stigge wrote:
> Since this driver is compatible with several NXP devices, the driver is renamed
> accordingly. Please combine with the following patch which also changes the
> respective symbol names.
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

Please use -C or -M when generating these kinds of patches.  It makes
it possible to see what if anything has changed in the renamed file
(and makes the diff smaller.)

Thanks.


From jonsmirl at gmail.com  Mon Mar 12 19:31:58 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Mon, 12 Mar 2012 19:31:58 -0400
Subject: ARM926EJS boot failure on v3.3, __iounmap
In-Reply-To: <CAKON4OzL9HtF+3bxzC9zexd7QgAFd5R7Wr=QTShYR+Kk1b4L+g@mail.gmail.com>
References: <CAKON4OzL9HtF+3bxzC9zexd7QgAFd5R7Wr=QTShYR+Kk1b4L+g@mail.gmail.com>
Message-ID: <CAKON4OyURmGP79oJaCkAw1dx3orynZDZSqZOC_t=PTKwHWaRJQ@mail.gmail.com>

The answer to this is that as of v3.3 you can't have overlapping IO
regions. The code I was porting has a large define covering peripheral
space and then many smaller ones inside the region, one for each
device. I needed to delete the defines for those inner devices.

-- 
Jon Smirl
jonsmirl at gmail.com


From dhowells at redhat.com  Mon Mar 12 19:36:37 2012
From: dhowells at redhat.com (David Howells)
Date: Mon, 12 Mar 2012 23:36:37 +0000
Subject: [PATCH 03/35] Disintegrate asm/system.h for ARM [ver #2]
In-Reply-To: <20120312233602.13888.27659.stgit@warthog.procyon.org.uk>
References: <20120312233602.13888.27659.stgit@warthog.procyon.org.uk>
Message-ID: <20120312233636.13888.21843.stgit@warthog.procyon.org.uk>

Signed-off-by: David Howells <dhowells at redhat.com>
cc: linux-arm-kernel at lists.infradead.org
---

 arch/arm/common/via82c505.c               |    1 
 arch/arm/include/asm/atomic.h             |    4 
 arch/arm/include/asm/barrier.h            |   64 +++
 arch/arm/include/asm/bitops.h             |    2 
 arch/arm/include/asm/bug.h                |   30 ++
 arch/arm/include/asm/cmpxchg.h            |  295 +++++++++++++++
 arch/arm/include/asm/compiler.h           |   15 +
 arch/arm/include/asm/cr_reg.h             |   85 ++++
 arch/arm/include/asm/div64.h              |    2 
 arch/arm/include/asm/dma.h                |    1 
 arch/arm/include/asm/domain.h             |    2 
 arch/arm/include/asm/exec.h               |    6 
 arch/arm/include/asm/io.h                 |    1 
 arch/arm/include/asm/mmu.h                |    7 
 arch/arm/include/asm/processor.h          |    1 
 arch/arm/include/asm/switch_to.h          |   18 +
 arch/arm/include/asm/system.h             |  552 -----------------------------
 arch/arm/include/asm/system_info.h        |   27 +
 arch/arm/include/asm/system_misc.h        |   35 ++
 arch/arm/include/asm/uaccess.h            |    2 
 arch/arm/kernel/armksyms.c                |    1 
 arch/arm/kernel/elf.c                     |    1 
 arch/arm/kernel/entry-armv.S              |    1 
 arch/arm/kernel/fiq.c                     |    1 
 arch/arm/kernel/head-nommu.S              |    1 
 arch/arm/kernel/head.S                    |    2 
 arch/arm/kernel/hw_breakpoint.c           |    1 
 arch/arm/kernel/irq.c                     |    1 
 arch/arm/kernel/machine_kexec.c           |    1 
 arch/arm/kernel/process.c                 |    1 
 arch/arm/kernel/ptrace.c                  |    1 
 arch/arm/kernel/setup.c                   |    4 
 arch/arm/kernel/sleep.S                   |    1 
 arch/arm/kernel/traps.c                   |    2 
 arch/arm/mach-clps711x/p720t-leds.c       |    1 
 arch/arm/mach-ebsa110/core.c              |    1 
 arch/arm/mach-ebsa110/leds.c              |    1 
 arch/arm/mach-footbridge/dc21285.c        |    1 
 arch/arm/mach-footbridge/ebsa285-leds.c   |    1 
 arch/arm/mach-footbridge/netwinder-leds.c |    1 
 arch/arm/mach-imx/dma-v1.c                |    1 
 arch/arm/mach-integrator/core.c           |    1 
 arch/arm/mach-integrator/leds.c           |    1 
 arch/arm/mach-integrator/pci.c            |    1 
 arch/arm/mach-integrator/pci_v3.c         |    1 
 arch/arm/mach-iop33x/uart.c               |    1 
 arch/arm/mach-ixp2000/core.c              |    1 
 arch/arm/mach-ixp2000/enp2611.c           |    1 
 arch/arm/mach-ixp2000/ixdp2400.c          |    1 
 arch/arm/mach-ixp2000/ixdp2800.c          |    1 
 arch/arm/mach-ixp2000/ixdp2x00.c          |    1 
 arch/arm/mach-ixp2000/ixdp2x01.c          |    1 
 arch/arm/mach-ixp2000/pci.c               |    1 
 arch/arm/mach-ixp23xx/core.c              |    1 
 arch/arm/mach-ixp23xx/espresso.c          |    1 
 arch/arm/mach-ixp23xx/ixdp2351.c          |    1 
 arch/arm/mach-ixp23xx/pci.c               |    1 
 arch/arm/mach-ixp23xx/roadrunner.c        |    1 
 arch/arm/mach-ixp4xx/common-pci.c         |    1 
 arch/arm/mach-ixp4xx/goramo_mlr.c         |    1 
 arch/arm/mach-msm/board-sapphire.c        |    1 
 arch/arm/mach-mxs/system.c                |    1 
 arch/arm/mach-omap1/leds-h2p2-debug.c     |    1 
 arch/arm/mach-omap1/leds-innovator.c      |    1 
 arch/arm/mach-omap1/leds-osk.c            |    1 
 arch/arm/mach-omap1/mux.c                 |    1 
 arch/arm/mach-omap1/time.c                |    1 
 arch/arm/mach-omap1/timer32k.c            |    1 
 arch/arm/mach-omap2/mux.c                 |    1 
 arch/arm/mach-omap2/omap-mpuss-lowpower.c |    1 
 arch/arm/mach-omap2/sleep44xx.S           |    1 
 arch/arm/mach-orion5x/ls-chl-setup.c      |    1 
 arch/arm/mach-orion5x/ls_hgl-setup.c      |    1 
 arch/arm/mach-orion5x/lsmini-setup.c      |    1 
 arch/arm/mach-pnx4008/core.c              |    1 
 arch/arm/mach-pnx4008/dma.c               |    1 
 arch/arm/mach-pnx4008/irq.c               |    1 
 arch/arm/mach-pnx4008/time.c              |    1 
 arch/arm/mach-pxa/corgi.c                 |    1 
 arch/arm/mach-pxa/generic.c               |    1 
 arch/arm/mach-pxa/leds-idp.c              |    1 
 arch/arm/mach-pxa/leds-lubbock.c          |    1 
 arch/arm/mach-pxa/leds-mainstone.c        |    1 
 arch/arm/mach-pxa/poodle.c                |    1 
 arch/arm/mach-realview/core.c             |    1 
 arch/arm/mach-sa1100/dma.c                |    1 
 arch/arm/mach-sa1100/generic.c            |    1 
 arch/arm/mach-sa1100/leds-assabet.c       |    1 
 arch/arm/mach-sa1100/leds-badge4.c        |    1 
 arch/arm/mach-sa1100/leds-cerf.c          |    1 
 arch/arm/mach-sa1100/leds-hackkit.c       |    1 
 arch/arm/mach-sa1100/leds-lart.c          |    1 
 arch/arm/mach-sa1100/pm.c                 |    1 
 arch/arm/mach-shark/leds.c                |    1 
 arch/arm/mach-shmobile/cpuidle.c          |    1 
 arch/arm/mach-shmobile/pm-r8a7779.c       |    1 
 arch/arm/mach-shmobile/pm-sh7372.c        |    1 
 arch/arm/mach-shmobile/suspend.c          |    1 
 arch/arm/mach-tegra/cpu-tegra.c           |    1 
 arch/arm/mach-versatile/core.c            |    1 
 arch/arm/mach-versatile/pci.c             |    1 
 arch/arm/mach-vexpress/hotplug.c          |    1 
 arch/arm/mm/alignment.c                   |    3 
 arch/arm/mm/cache-xsc3l2.c                |    1 
 arch/arm/mm/fault.c                       |    3 
 arch/arm/mm/flush.c                       |    1 
 arch/arm/mm/idmap.c                       |    1 
 arch/arm/mm/ioremap.c                     |    2 
 arch/arm/mm/mmu.c                         |    2 
 arch/arm/mm/pgd.c                         |    1 
 arch/arm/mm/proc-fa526.S                  |    1 
 arch/arm/nwfpe/fpa11.c                    |    1 
 arch/arm/plat-iop/i2c.c                   |    1 
 arch/arm/plat-iop/pci.c                   |    1 
 arch/arm/plat-mxc/system.c                |    1 
 arch/arm/plat-omap/debug-leds.c           |    1 
 arch/arm/plat-omap/dma.c                  |    1 
 arch/arm/plat-omap/mux.c                  |    1 
 arch/arm/plat-pxa/dma.c                   |    1 
 arch/arm/plat-s3c24xx/dma.c               |    1 
 arch/arm/plat-samsung/cpu.c               |    1 
 arch/arm/plat-samsung/time.c              |    1 
 arch/arm/vfp/vfpmodule.c                  |    2 
 123 files changed, 617 insertions(+), 648 deletions(-)
 create mode 100644 arch/arm/include/asm/barrier.h
 create mode 100644 arch/arm/include/asm/cmpxchg.h
 create mode 100644 arch/arm/include/asm/compiler.h
 create mode 100644 arch/arm/include/asm/cr_reg.h
 create mode 100644 arch/arm/include/asm/exec.h
 create mode 100644 arch/arm/include/asm/switch_to.h
 create mode 100644 arch/arm/include/asm/system_info.h
 create mode 100644 arch/arm/include/asm/system_misc.h

diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c
index 67dd2af..1171a50 100644
--- a/arch/arm/common/via82c505.c
+++ b/arch/arm/common/via82c505.c
@@ -6,7 +6,6 @@
 #include <linux/ioport.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 
 #include <asm/mach/pci.h>
 
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 86976d0..68374ba 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -13,7 +13,9 @@
 
 #include <linux/compiler.h>
 #include <linux/types.h>
-#include <asm/system.h>
+#include <linux/irqflags.h>
+#include <asm/barrier.h>
+#include <asm/cmpxchg.h>
 
 #define ATOMIC_INIT(i)	{ (i) }
 
diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
new file mode 100644
index 0000000..81b24b6
--- /dev/null
+++ b/arch/arm/include/asm/barrier.h
@@ -0,0 +1,64 @@
+#ifndef __ASM_BARRIER_H
+#define __ASM_BARRIER_H
+
+
+#if __LINUX_ARM_ARCH__ >= 7 ||		\
+	(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
+#define sev()	__asm__ __volatile__ ("sev" : : : "memory")
+#define wfe()	__asm__ __volatile__ ("wfe" : : : "memory")
+#define wfi()	__asm__ __volatile__ ("wfi" : : : "memory")
+#endif
+
+#if __LINUX_ARM_ARCH__ >= 7
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+				    : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+				    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
+				    : : "r" (0) : "memory")
+#elif defined(CONFIG_CPU_FA526)
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+				    : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+				    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+				    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#endif
+
+#ifdef CONFIG_ARCH_HAS_BARRIERS
+#include <mach/barriers.h>
+#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
+#define mb()		do { dsb(); outer_sync(); } while (0)
+#define rmb()		dsb()
+#define wmb()		mb()
+#else
+#include <asm/memory.h>
+#define mb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
+#define rmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
+#define wmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
+#endif
+
+#ifndef CONFIG_SMP
+#define smp_mb()	barrier()
+#define smp_rmb()	barrier()
+#define smp_wmb()	barrier()
+#else
+#define smp_mb()	dmb()
+#define smp_rmb()	dmb()
+#define smp_wmb()	dmb()
+#endif
+
+#define read_barrier_depends()		do { } while(0)
+#define smp_read_barrier_depends()	do { } while(0)
+
+#define set_mb(var, value)	do { var = value; smp_mb(); } while (0)
+
+#endif /* __ASM_BARRIER_H */
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index f7419ef..e691ec9 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -24,7 +24,7 @@
 #endif
 
 #include <linux/compiler.h>
-#include <asm/system.h>
+#include <linux/irqflags.h>
 
 #define smp_mb__before_clear_bit()	smp_mb()
 #define smp_mb__after_clear_bit()	smp_mb()
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index fac79dc..7af5c6c 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -1,6 +1,7 @@
 #ifndef _ASMARM_BUG_H
 #define _ASMARM_BUG_H
 
+#include <linux/linkage.h>
 
 #ifdef CONFIG_BUG
 
@@ -57,4 +58,33 @@ do {								\
 
 #include <asm-generic/bug.h>
 
+struct pt_regs;
+void die(const char *msg, struct pt_regs *regs, int err);
+
+struct siginfo;
+void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
+		unsigned long err, unsigned long trap);
+
+#ifdef CONFIG_ARM_LPAE
+#define FAULT_CODE_ALIGNMENT	33
+#define FAULT_CODE_DEBUG	34
+#else
+#define FAULT_CODE_ALIGNMENT	1
+#define FAULT_CODE_DEBUG	2
+#endif
+
+void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
+				       struct pt_regs *),
+		     int sig, int code, const char *name);
+
+void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
+				       struct pt_regs *),
+		     int sig, int code, const char *name);
+
+extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
+
+struct mm_struct;
+extern void show_pte(struct mm_struct *mm, unsigned long addr);
+extern void __show_regs(struct pt_regs *);
+
 #endif
diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
new file mode 100644
index 0000000..d41d7cb
--- /dev/null
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -0,0 +1,295 @@
+#ifndef __ASM_ARM_CMPXCHG_H
+#define __ASM_ARM_CMPXCHG_H
+
+#include <linux/irqflags.h>
+#include <asm/barrier.h>
+
+#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
+/*
+ * On the StrongARM, "swp" is terminally broken since it bypasses the
+ * cache totally.  This means that the cache becomes inconsistent, and,
+ * since we use normal loads/stores as well, this is really bad.
+ * Typically, this causes oopsen in filp_close, but could have other,
+ * more disastrous effects.  There are two work-arounds:
+ *  1. Disable interrupts and emulate the atomic swap
+ *  2. Clean the cache, perform atomic swap, flush the cache
+ *
+ * We choose (1) since its the "easiest" to achieve here and is not
+ * dependent on the processor type.
+ *
+ * NOTE that this solution won't work on an SMP system, so explcitly
+ * forbid it here.
+ */
+#define swp_is_buggy
+#endif
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+{
+	extern void __bad_xchg(volatile void *, int);
+	unsigned long ret;
+#ifdef swp_is_buggy
+	unsigned long flags;
+#endif
+#if __LINUX_ARM_ARCH__ >= 6
+	unsigned int tmp;
+#endif
+
+	smp_mb();
+
+	switch (size) {
+#if __LINUX_ARM_ARCH__ >= 6
+	case 1:
+		asm volatile("@	__xchg1\n"
+		"1:	ldrexb	%0, [%3]\n"
+		"	strexb	%1, %2, [%3]\n"
+		"	teq	%1, #0\n"
+		"	bne	1b"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+	case 4:
+		asm volatile("@	__xchg4\n"
+		"1:	ldrex	%0, [%3]\n"
+		"	strex	%1, %2, [%3]\n"
+		"	teq	%1, #0\n"
+		"	bne	1b"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+#elif defined(swp_is_buggy)
+#ifdef CONFIG_SMP
+#error SMP is not supported on this platform
+#endif
+	case 1:
+		raw_local_irq_save(flags);
+		ret = *(volatile unsigned char *)ptr;
+		*(volatile unsigned char *)ptr = x;
+		raw_local_irq_restore(flags);
+		break;
+
+	case 4:
+		raw_local_irq_save(flags);
+		ret = *(volatile unsigned long *)ptr;
+		*(volatile unsigned long *)ptr = x;
+		raw_local_irq_restore(flags);
+		break;
+#else
+	case 1:
+		asm volatile("@	__xchg1\n"
+		"	swpb	%0, %1, [%2]"
+			: "=&r" (ret)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+	case 4:
+		asm volatile("@	__xchg4\n"
+		"	swp	%0, %1, [%2]"
+			: "=&r" (ret)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+#endif
+	default:
+		__bad_xchg(ptr, size), ret = 0;
+		break;
+	}
+	smp_mb();
+
+	return ret;
+}
+
+#define xchg(ptr,x) \
+	((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+#include <asm-generic/cmpxchg-local.h>
+
+#if __LINUX_ARM_ARCH__ < 6
+/* min ARCH < ARMv6 */
+
+#ifdef CONFIG_SMP
+#error "SMP is not supported on this platform"
+#endif
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+#define cmpxchg_local(ptr, o, n)				  	       \
+	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
+			(unsigned long)(n), sizeof(*(ptr))))
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+#ifndef CONFIG_SMP
+#include <asm-generic/cmpxchg.h>
+#endif
+
+#else	/* min ARCH >= ARMv6 */
+
+extern void __bad_cmpxchg(volatile void *ptr, int size);
+
+/*
+ * cmpxchg only support 32-bits operands on ARMv6.
+ */
+
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+				      unsigned long new, int size)
+{
+	unsigned long oldval, res;
+
+	switch (size) {
+#ifndef CONFIG_CPU_V6	/* min ARCH >= ARMv6K */
+	case 1:
+		do {
+			asm volatile("@ __cmpxchg1\n"
+			"	ldrexb	%1, [%2]\n"
+			"	mov	%0, #0\n"
+			"	teq	%1, %3\n"
+			"	strexbeq %0, %4, [%2]\n"
+				: "=&r" (res), "=&r" (oldval)
+				: "r" (ptr), "Ir" (old), "r" (new)
+				: "memory", "cc");
+		} while (res);
+		break;
+	case 2:
+		do {
+			asm volatile("@ __cmpxchg1\n"
+			"	ldrexh	%1, [%2]\n"
+			"	mov	%0, #0\n"
+			"	teq	%1, %3\n"
+			"	strexheq %0, %4, [%2]\n"
+				: "=&r" (res), "=&r" (oldval)
+				: "r" (ptr), "Ir" (old), "r" (new)
+				: "memory", "cc");
+		} while (res);
+		break;
+#endif
+	case 4:
+		do {
+			asm volatile("@ __cmpxchg4\n"
+			"	ldrex	%1, [%2]\n"
+			"	mov	%0, #0\n"
+			"	teq	%1, %3\n"
+			"	strexeq %0, %4, [%2]\n"
+				: "=&r" (res), "=&r" (oldval)
+				: "r" (ptr), "Ir" (old), "r" (new)
+				: "memory", "cc");
+		} while (res);
+		break;
+	default:
+		__bad_cmpxchg(ptr, size);
+		oldval = 0;
+	}
+
+	return oldval;
+}
+
+static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
+					 unsigned long new, int size)
+{
+	unsigned long ret;
+
+	smp_mb();
+	ret = __cmpxchg(ptr, old, new, size);
+	smp_mb();
+
+	return ret;
+}
+
+#define cmpxchg(ptr,o,n)						\
+	((__typeof__(*(ptr)))__cmpxchg_mb((ptr),			\
+					  (unsigned long)(o),		\
+					  (unsigned long)(n),		\
+					  sizeof(*(ptr))))
+
+static inline unsigned long __cmpxchg_local(volatile void *ptr,
+					    unsigned long old,
+					    unsigned long new, int size)
+{
+	unsigned long ret;
+
+	switch (size) {
+#ifdef CONFIG_CPU_V6	/* min ARCH == ARMv6 */
+	case 1:
+	case 2:
+		ret = __cmpxchg_local_generic(ptr, old, new, size);
+		break;
+#endif
+	default:
+		ret = __cmpxchg(ptr, old, new, size);
+	}
+
+	return ret;
+}
+
+#define cmpxchg_local(ptr,o,n)						\
+	((__typeof__(*(ptr)))__cmpxchg_local((ptr),			\
+				       (unsigned long)(o),		\
+				       (unsigned long)(n),		\
+				       sizeof(*(ptr))))
+
+#ifndef CONFIG_CPU_V6	/* min ARCH >= ARMv6K */
+
+/*
+ * Note : ARMv7-M (currently unsupported by Linux) does not support
+ * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
+ * not be allowed to use __cmpxchg64.
+ */
+static inline unsigned long long __cmpxchg64(volatile void *ptr,
+					     unsigned long long old,
+					     unsigned long long new)
+{
+	register unsigned long long oldval asm("r0");
+	register unsigned long long __old asm("r2") = old;
+	register unsigned long long __new asm("r4") = new;
+	unsigned long res;
+
+	do {
+		asm volatile(
+		"	@ __cmpxchg8\n"
+		"	ldrexd	%1, %H1, [%2]\n"
+		"	mov	%0, #0\n"
+		"	teq	%1, %3\n"
+		"	teqeq	%H1, %H3\n"
+		"	strexdeq %0, %4, %H4, [%2]\n"
+			: "=&r" (res), "=&r" (oldval)
+			: "r" (ptr), "Ir" (__old), "r" (__new)
+			: "memory", "cc");
+	} while (res);
+
+	return oldval;
+}
+
+static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
+						unsigned long long old,
+						unsigned long long new)
+{
+	unsigned long long ret;
+
+	smp_mb();
+	ret = __cmpxchg64(ptr, old, new);
+	smp_mb();
+
+	return ret;
+}
+
+#define cmpxchg64(ptr,o,n)						\
+	((__typeof__(*(ptr)))__cmpxchg64_mb((ptr),			\
+					    (unsigned long long)(o),	\
+					    (unsigned long long)(n)))
+
+#define cmpxchg64_local(ptr,o,n)					\
+	((__typeof__(*(ptr)))__cmpxchg64((ptr),				\
+					 (unsigned long long)(o),	\
+					 (unsigned long long)(n)))
+
+#else /* min ARCH = ARMv6 */
+
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+#endif
+
+#endif	/* __LINUX_ARM_ARCH__ >= 6 */
+
+#endif /* __ASM_ARM_CMPXCHG_H */
diff --git a/arch/arm/include/asm/compiler.h b/arch/arm/include/asm/compiler.h
new file mode 100644
index 0000000..8155db2
--- /dev/null
+++ b/arch/arm/include/asm/compiler.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_ARM_COMPILER_H
+#define __ASM_ARM_COMPILER_H
+
+/*
+ * This is used to ensure the compiler did actually allocate the register we
+ * asked it for some inline assembly sequences.  Apparently we can't trust
+ * the compiler from one version to another so a bit of paranoia won't hurt.
+ * This string is meant to be concatenated with the inline asm string and
+ * will cause compilation to stop on mismatch.
+ * (for details, see gcc PR 15089)
+ */
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+
+#endif /* __ASM_ARM_COMPILER_H */
diff --git a/arch/arm/include/asm/cr_reg.h b/arch/arm/include/asm/cr_reg.h
new file mode 100644
index 0000000..df83b5b
--- /dev/null
+++ b/arch/arm/include/asm/cr_reg.h
@@ -0,0 +1,85 @@
+#ifndef __ASM_ARM_CR_REG_H
+#define __ASM_ARM_CR_REG_H
+
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M	(1 << 0)	/* MMU enable				*/
+#define CR_A	(1 << 1)	/* Alignment abort enable		*/
+#define CR_C	(1 << 2)	/* Dcache enable			*/
+#define CR_W	(1 << 3)	/* Write buffer enable			*/
+#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
+#define CR_D	(1 << 5)	/* 32-bit data address range		*/
+#define CR_L	(1 << 6)	/* Implementation defined		*/
+#define CR_B	(1 << 7)	/* Big endian				*/
+#define CR_S	(1 << 8)	/* System MMU protection		*/
+#define CR_R	(1 << 9)	/* ROM MMU protection			*/
+#define CR_F	(1 << 10)	/* Implementation defined		*/
+#define CR_Z	(1 << 11)	/* Implementation defined		*/
+#define CR_I	(1 << 12)	/* Icache enable			*/
+#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
+#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
+#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
+#define CR_DT	(1 << 16)
+#define CR_IT	(1 << 18)
+#define CR_ST	(1 << 19)
+#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
+#define CR_U	(1 << 22)	/* Unaligned access operation		*/
+#define CR_XP	(1 << 23)	/* Extended page tables			*/
+#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
+#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
+#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
+#define CR_AFE	(1 << 29)	/* Access flag enable			*/
+#define CR_TE	(1 << 30)	/* Thumb exception enable		*/
+
+#ifndef __ASSEMBLY__
+
+extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */
+extern unsigned long cr_alignment;	/* defined in entry-armv.S */
+
+#if __LINUX_ARM_ARCH__ >= 4
+#define vectors_high()	(cr_alignment & CR_V)
+#else
+#define vectors_high()	(0)
+#endif
+
+static inline unsigned int get_cr(void)
+{
+	unsigned int val;
+	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");
+	return val;
+}
+
+static inline void set_cr(unsigned int val)
+{
+	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"
+	  : : "r" (val) : "cc");
+	isb();
+}
+
+#ifndef CONFIG_SMP
+extern void adjust_cr(unsigned long mask, unsigned long set);
+#endif
+
+#define CPACC_FULL(n)		(3 << (n * 2))
+#define CPACC_SVC(n)		(1 << (n * 2))
+#define CPACC_DISABLE(n)	(0 << (n * 2))
+
+static inline unsigned int get_copro_access(void)
+{
+	unsigned int val;
+	asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
+	  : "=r" (val) : : "cc");
+	return val;
+}
+
+static inline void set_copro_access(unsigned int val)
+{
+	asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
+	  : : "r" (val) : "cc");
+	isb();
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_ARM_CR_REG_H */
diff --git a/arch/arm/include/asm/div64.h b/arch/arm/include/asm/div64.h
index d3f0a9e..fe92ccf 100644
--- a/arch/arm/include/asm/div64.h
+++ b/arch/arm/include/asm/div64.h
@@ -1,8 +1,8 @@
 #ifndef __ASM_ARM_DIV64
 #define __ASM_ARM_DIV64
 
-#include <asm/system.h>
 #include <linux/types.h>
+#include <asm/compiler.h>
 
 /*
  * The semantics of do_div() are:
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 69a5b0b..5694a0d 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -19,7 +19,6 @@
  * It should not be re-used except for that purpose.
  */
 #include <linux/spinlock.h>
-#include <asm/system.h>
 #include <asm/scatterlist.h>
 
 #include <mach/isa-dma.h>
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index b5dc173..489f160 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -10,6 +10,8 @@
 #ifndef __ASM_PROC_DOMAIN_H
 #define __ASM_PROC_DOMAIN_H
 
+#include <asm/barrier.h>
+
 /*
  * Domain numbers
  *
diff --git a/arch/arm/include/asm/exec.h b/arch/arm/include/asm/exec.h
new file mode 100644
index 0000000..7c4fbef
--- /dev/null
+++ b/arch/arm/include/asm/exec.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARM_EXEC_H
+#define __ASM_ARM_EXEC_H
+
+#define arch_align_stack(x) (x)
+
+#endif /* __ASM_ARM_EXEC_H */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 9275828..0a34bf7 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -26,7 +26,6 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 #include <asm/memory.h>
-#include <asm/system.h>
 #include <asm-generic/pci_iomap.h>
 
 /*
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 1496565..b8e580a 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -34,4 +34,11 @@ typedef struct {
 
 #endif
 
+/*
+ * switch_mm() may do a full cache flush over the context switch,
+ * so enable interrupts over the context switch to avoid high
+ * latency.
+ */
+#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
+
 #endif
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index cb8d638..ce280b8 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -22,7 +22,6 @@
 #include <asm/hw_breakpoint.h>
 #include <asm/ptrace.h>
 #include <asm/types.h>
-#include <asm/system.h>
 
 #ifdef __KERNEL__
 #define STACK_TOP	((current->personality & ADDR_LIMIT_32BIT) ? \
diff --git a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h
new file mode 100644
index 0000000..fa09e6b
--- /dev/null
+++ b/arch/arm/include/asm/switch_to.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_ARM_SWITCH_TO_H
+#define __ASM_ARM_SWITCH_TO_H
+
+#include <linux/thread_info.h>
+
+/*
+ * switch_to(prev, next) should switch from task `prev' to `next'
+ * `prev' will never be the same as `next'.  schedule() itself
+ * contains the memory barrier to tell GCC not to cache `current'.
+ */
+extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
+
+#define switch_to(prev,next,last)					\
+do {									\
+	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
+} while (0)
+
+#endif /* __ASM_ARM_SWITCH_TO_H */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index e4c96cc..ae2c8c2 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -1,543 +1,9 @@
-#ifndef __ASM_ARM_SYSTEM_H
-#define __ASM_ARM_SYSTEM_H
-
-#ifdef __KERNEL__
-
-#define CPU_ARCH_UNKNOWN	0
-#define CPU_ARCH_ARMv3		1
-#define CPU_ARCH_ARMv4		2
-#define CPU_ARCH_ARMv4T		3
-#define CPU_ARCH_ARMv5		4
-#define CPU_ARCH_ARMv5T		5
-#define CPU_ARCH_ARMv5TE	6
-#define CPU_ARCH_ARMv5TEJ	7
-#define CPU_ARCH_ARMv6		8
-#define CPU_ARCH_ARMv7		9
-
-/*
- * CR1 bits (CP#15 CR1)
- */
-#define CR_M	(1 << 0)	/* MMU enable				*/
-#define CR_A	(1 << 1)	/* Alignment abort enable		*/
-#define CR_C	(1 << 2)	/* Dcache enable			*/
-#define CR_W	(1 << 3)	/* Write buffer enable			*/
-#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
-#define CR_D	(1 << 5)	/* 32-bit data address range		*/
-#define CR_L	(1 << 6)	/* Implementation defined		*/
-#define CR_B	(1 << 7)	/* Big endian				*/
-#define CR_S	(1 << 8)	/* System MMU protection		*/
-#define CR_R	(1 << 9)	/* ROM MMU protection			*/
-#define CR_F	(1 << 10)	/* Implementation defined		*/
-#define CR_Z	(1 << 11)	/* Implementation defined		*/
-#define CR_I	(1 << 12)	/* Icache enable			*/
-#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
-#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
-#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
-#define CR_DT	(1 << 16)
-#define CR_IT	(1 << 18)
-#define CR_ST	(1 << 19)
-#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
-#define CR_U	(1 << 22)	/* Unaligned access operation		*/
-#define CR_XP	(1 << 23)	/* Extended page tables			*/
-#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
-#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
-#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
-#define CR_AFE	(1 << 29)	/* Access flag enable			*/
-#define CR_TE	(1 << 30)	/* Thumb exception enable		*/
-
-/*
- * This is used to ensure the compiler did actually allocate the register we
- * asked it for some inline assembly sequences.  Apparently we can't trust
- * the compiler from one version to another so a bit of paranoia won't hurt.
- * This string is meant to be concatenated with the inline asm string and
- * will cause compilation to stop on mismatch.
- * (for details, see gcc PR 15089)
- */
-#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
-
-#ifndef __ASSEMBLY__
-
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-#include <linux/irqflags.h>
-
-#include <asm/outercache.h>
-
-struct thread_info;
-struct task_struct;
-
-/* information about the system we're running on */
-extern unsigned int system_rev;
-extern unsigned int system_serial_low;
-extern unsigned int system_serial_high;
-extern unsigned int mem_fclk_21285;
-
-struct pt_regs;
-
-void die(const char *msg, struct pt_regs *regs, int err);
-
-struct siginfo;
-void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
-		unsigned long err, unsigned long trap);
-
-#ifdef CONFIG_ARM_LPAE
-#define FAULT_CODE_ALIGNMENT	33
-#define FAULT_CODE_DEBUG	34
-#else
-#define FAULT_CODE_ALIGNMENT	1
-#define FAULT_CODE_DEBUG	2
-#endif
-
-void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
-				       struct pt_regs *),
-		     int sig, int code, const char *name);
-
-void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
-				       struct pt_regs *),
-		     int sig, int code, const char *name);
-
-#define xchg(ptr,x) \
-	((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
-
-struct mm_struct;
-extern void show_pte(struct mm_struct *mm, unsigned long addr);
-extern void __show_regs(struct pt_regs *);
-
-extern int __pure cpu_architecture(void);
-extern void cpu_init(void);
-
-void soft_restart(unsigned long);
-extern void (*arm_pm_restart)(char str, const char *cmd);
-
-#define UDBG_UNDEFINED	(1 << 0)
-#define UDBG_SYSCALL	(1 << 1)
-#define UDBG_BADABORT	(1 << 2)
-#define UDBG_SEGV	(1 << 3)
-#define UDBG_BUS	(1 << 4)
-
-extern unsigned int user_debug;
-
-#if __LINUX_ARM_ARCH__ >= 4
-#define vectors_high()	(cr_alignment & CR_V)
-#else
-#define vectors_high()	(0)
-#endif
-
-#if __LINUX_ARM_ARCH__ >= 7 ||		\
-	(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
-#define sev()	__asm__ __volatile__ ("sev" : : : "memory")
-#define wfe()	__asm__ __volatile__ ("wfe" : : : "memory")
-#define wfi()	__asm__ __volatile__ ("wfi" : : : "memory")
-#endif
-
-#if __LINUX_ARM_ARCH__ >= 7
-#define isb() __asm__ __volatile__ ("isb" : : : "memory")
-#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
-#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
-#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
-#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
-				    : : "r" (0) : "memory")
-#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
-				    : : "r" (0) : "memory")
-#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
-				    : : "r" (0) : "memory")
-#elif defined(CONFIG_CPU_FA526)
-#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
-				    : : "r" (0) : "memory")
-#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
-				    : : "r" (0) : "memory")
-#define dmb() __asm__ __volatile__ ("" : : : "memory")
-#else
-#define isb() __asm__ __volatile__ ("" : : : "memory")
-#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
-				    : : "r" (0) : "memory")
-#define dmb() __asm__ __volatile__ ("" : : : "memory")
-#endif
-
-#ifdef CONFIG_ARCH_HAS_BARRIERS
-#include <mach/barriers.h>
-#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
-#define mb()		do { dsb(); outer_sync(); } while (0)
-#define rmb()		dsb()
-#define wmb()		mb()
-#else
-#include <asm/memory.h>
-#define mb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
-#define rmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
-#define wmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
-#endif
-
-#ifndef CONFIG_SMP
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#else
-#define smp_mb()	dmb()
-#define smp_rmb()	dmb()
-#define smp_wmb()	dmb()
-#endif
-
-#define read_barrier_depends()		do { } while(0)
-#define smp_read_barrier_depends()	do { } while(0)
-
-#define set_mb(var, value)	do { var = value; smp_mb(); } while (0)
-#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
-
-extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */
-extern unsigned long cr_alignment;	/* defined in entry-armv.S */
-
-static inline unsigned int get_cr(void)
-{
-	unsigned int val;
-	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");
-	return val;
-}
-
-static inline void set_cr(unsigned int val)
-{
-	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"
-	  : : "r" (val) : "cc");
-	isb();
-}
-
-#ifndef CONFIG_SMP
-extern void adjust_cr(unsigned long mask, unsigned long set);
-#endif
-
-#define CPACC_FULL(n)		(3 << (n * 2))
-#define CPACC_SVC(n)		(1 << (n * 2))
-#define CPACC_DISABLE(n)	(0 << (n * 2))
-
-static inline unsigned int get_copro_access(void)
-{
-	unsigned int val;
-	asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
-	  : "=r" (val) : : "cc");
-	return val;
-}
-
-static inline void set_copro_access(unsigned int val)
-{
-	asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
-	  : : "r" (val) : "cc");
-	isb();
-}
-
-/*
- * switch_mm() may do a full cache flush over the context switch,
- * so enable interrupts over the context switch to avoid high
- * latency.
- */
-#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
-
-/*
- * switch_to(prev, next) should switch from task `prev' to `next'
- * `prev' will never be the same as `next'.  schedule() itself
- * contains the memory barrier to tell GCC not to cache `current'.
- */
-extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
-
-#define switch_to(prev,next,last)					\
-do {									\
-	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
-} while (0)
-
-#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
-/*
- * On the StrongARM, "swp" is terminally broken since it bypasses the
- * cache totally.  This means that the cache becomes inconsistent, and,
- * since we use normal loads/stores as well, this is really bad.
- * Typically, this causes oopsen in filp_close, but could have other,
- * more disastrous effects.  There are two work-arounds:
- *  1. Disable interrupts and emulate the atomic swap
- *  2. Clean the cache, perform atomic swap, flush the cache
- *
- * We choose (1) since its the "easiest" to achieve here and is not
- * dependent on the processor type.
- *
- * NOTE that this solution won't work on an SMP system, so explcitly
- * forbid it here.
- */
-#define swp_is_buggy
-#endif
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
-{
-	extern void __bad_xchg(volatile void *, int);
-	unsigned long ret;
-#ifdef swp_is_buggy
-	unsigned long flags;
-#endif
-#if __LINUX_ARM_ARCH__ >= 6
-	unsigned int tmp;
-#endif
-
-	smp_mb();
-
-	switch (size) {
-#if __LINUX_ARM_ARCH__ >= 6
-	case 1:
-		asm volatile("@	__xchg1\n"
-		"1:	ldrexb	%0, [%3]\n"
-		"	strexb	%1, %2, [%3]\n"
-		"	teq	%1, #0\n"
-		"	bne	1b"
-			: "=&r" (ret), "=&r" (tmp)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
-		break;
-	case 4:
-		asm volatile("@	__xchg4\n"
-		"1:	ldrex	%0, [%3]\n"
-		"	strex	%1, %2, [%3]\n"
-		"	teq	%1, #0\n"
-		"	bne	1b"
-			: "=&r" (ret), "=&r" (tmp)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
-		break;
-#elif defined(swp_is_buggy)
-#ifdef CONFIG_SMP
-#error SMP is not supported on this platform
-#endif
-	case 1:
-		raw_local_irq_save(flags);
-		ret = *(volatile unsigned char *)ptr;
-		*(volatile unsigned char *)ptr = x;
-		raw_local_irq_restore(flags);
-		break;
-
-	case 4:
-		raw_local_irq_save(flags);
-		ret = *(volatile unsigned long *)ptr;
-		*(volatile unsigned long *)ptr = x;
-		raw_local_irq_restore(flags);
-		break;
-#else
-	case 1:
-		asm volatile("@	__xchg1\n"
-		"	swpb	%0, %1, [%2]"
-			: "=&r" (ret)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
-		break;
-	case 4:
-		asm volatile("@	__xchg4\n"
-		"	swp	%0, %1, [%2]"
-			: "=&r" (ret)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
-		break;
-#endif
-	default:
-		__bad_xchg(ptr, size), ret = 0;
-		break;
-	}
-	smp_mb();
-
-	return ret;
-}
-
-extern void disable_hlt(void);
-extern void enable_hlt(void);
-
-void cpu_idle_wait(void);
-
-#include <asm-generic/cmpxchg-local.h>
-
-#if __LINUX_ARM_ARCH__ < 6
-/* min ARCH < ARMv6 */
-
-#ifdef CONFIG_SMP
-#error "SMP is not supported on this platform"
-#endif
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n)				  	       \
-	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
-			(unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#ifndef CONFIG_SMP
-#include <asm-generic/cmpxchg.h>
-#endif
-
-#else	/* min ARCH >= ARMv6 */
-
-extern void __bad_cmpxchg(volatile void *ptr, int size);
-
-/*
- * cmpxchg only support 32-bits operands on ARMv6.
- */
-
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
-				      unsigned long new, int size)
-{
-	unsigned long oldval, res;
-
-	switch (size) {
-#ifndef CONFIG_CPU_V6	/* min ARCH >= ARMv6K */
-	case 1:
-		do {
-			asm volatile("@ __cmpxchg1\n"
-			"	ldrexb	%1, [%2]\n"
-			"	mov	%0, #0\n"
-			"	teq	%1, %3\n"
-			"	strexbeq %0, %4, [%2]\n"
-				: "=&r" (res), "=&r" (oldval)
-				: "r" (ptr), "Ir" (old), "r" (new)
-				: "memory", "cc");
-		} while (res);
-		break;
-	case 2:
-		do {
-			asm volatile("@ __cmpxchg1\n"
-			"	ldrexh	%1, [%2]\n"
-			"	mov	%0, #0\n"
-			"	teq	%1, %3\n"
-			"	strexheq %0, %4, [%2]\n"
-				: "=&r" (res), "=&r" (oldval)
-				: "r" (ptr), "Ir" (old), "r" (new)
-				: "memory", "cc");
-		} while (res);
-		break;
-#endif
-	case 4:
-		do {
-			asm volatile("@ __cmpxchg4\n"
-			"	ldrex	%1, [%2]\n"
-			"	mov	%0, #0\n"
-			"	teq	%1, %3\n"
-			"	strexeq %0, %4, [%2]\n"
-				: "=&r" (res), "=&r" (oldval)
-				: "r" (ptr), "Ir" (old), "r" (new)
-				: "memory", "cc");
-		} while (res);
-		break;
-	default:
-		__bad_cmpxchg(ptr, size);
-		oldval = 0;
-	}
-
-	return oldval;
-}
-
-static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
-					 unsigned long new, int size)
-{
-	unsigned long ret;
-
-	smp_mb();
-	ret = __cmpxchg(ptr, old, new, size);
-	smp_mb();
-
-	return ret;
-}
-
-#define cmpxchg(ptr,o,n)						\
-	((__typeof__(*(ptr)))__cmpxchg_mb((ptr),			\
-					  (unsigned long)(o),		\
-					  (unsigned long)(n),		\
-					  sizeof(*(ptr))))
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
-					    unsigned long old,
-					    unsigned long new, int size)
-{
-	unsigned long ret;
-
-	switch (size) {
-#ifdef CONFIG_CPU_V6	/* min ARCH == ARMv6 */
-	case 1:
-	case 2:
-		ret = __cmpxchg_local_generic(ptr, old, new, size);
-		break;
-#endif
-	default:
-		ret = __cmpxchg(ptr, old, new, size);
-	}
-
-	return ret;
-}
-
-#define cmpxchg_local(ptr,o,n)						\
-	((__typeof__(*(ptr)))__cmpxchg_local((ptr),			\
-				       (unsigned long)(o),		\
-				       (unsigned long)(n),		\
-				       sizeof(*(ptr))))
-
-#ifndef CONFIG_CPU_V6	/* min ARCH >= ARMv6K */
-
-/*
- * Note : ARMv7-M (currently unsupported by Linux) does not support
- * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
- * not be allowed to use __cmpxchg64.
- */
-static inline unsigned long long __cmpxchg64(volatile void *ptr,
-					     unsigned long long old,
-					     unsigned long long new)
-{
-	register unsigned long long oldval asm("r0");
-	register unsigned long long __old asm("r2") = old;
-	register unsigned long long __new asm("r4") = new;
-	unsigned long res;
-
-	do {
-		asm volatile(
-		"	@ __cmpxchg8\n"
-		"	ldrexd	%1, %H1, [%2]\n"
-		"	mov	%0, #0\n"
-		"	teq	%1, %3\n"
-		"	teqeq	%H1, %H3\n"
-		"	strexdeq %0, %4, %H4, [%2]\n"
-			: "=&r" (res), "=&r" (oldval)
-			: "r" (ptr), "Ir" (__old), "r" (__new)
-			: "memory", "cc");
-	} while (res);
-
-	return oldval;
-}
-
-static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
-						unsigned long long old,
-						unsigned long long new)
-{
-	unsigned long long ret;
-
-	smp_mb();
-	ret = __cmpxchg64(ptr, old, new);
-	smp_mb();
-
-	return ret;
-}
-
-#define cmpxchg64(ptr,o,n)						\
-	((__typeof__(*(ptr)))__cmpxchg64_mb((ptr),			\
-					    (unsigned long long)(o),	\
-					    (unsigned long long)(n)))
-
-#define cmpxchg64_local(ptr,o,n)					\
-	((__typeof__(*(ptr)))__cmpxchg64((ptr),				\
-					 (unsigned long long)(o),	\
-					 (unsigned long long)(n)))
-
-#else /* min ARCH = ARMv6 */
-
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#endif
-
-#endif	/* __LINUX_ARM_ARCH__ >= 6 */
-
-#endif /* __ASSEMBLY__ */
-
-#define arch_align_stack(x) (x)
-
-#endif /* __KERNEL__ */
-
-#endif
+/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
+#include <asm/barrier.h>
+#include <asm/compiler.h>
+#include <asm/cr_reg.h>
+#include <asm/cmpxchg.h>
+#include <asm/exec.h>
+#include <asm/switch_to.h>
+#include <asm/system_info.h>
+#include <asm/system_misc.h>
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
new file mode 100644
index 0000000..dfd386d
--- /dev/null
+++ b/arch/arm/include/asm/system_info.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_ARM_SYSTEM_INFO_H
+#define __ASM_ARM_SYSTEM_INFO_H
+
+#define CPU_ARCH_UNKNOWN	0
+#define CPU_ARCH_ARMv3		1
+#define CPU_ARCH_ARMv4		2
+#define CPU_ARCH_ARMv4T		3
+#define CPU_ARCH_ARMv5		4
+#define CPU_ARCH_ARMv5T		5
+#define CPU_ARCH_ARMv5TE	6
+#define CPU_ARCH_ARMv5TEJ	7
+#define CPU_ARCH_ARMv6		8
+#define CPU_ARCH_ARMv7		9
+
+#ifndef __ASSEMBLY__
+
+/* information about the system we're running on */
+extern unsigned int system_rev;
+extern unsigned int system_serial_low;
+extern unsigned int system_serial_high;
+extern unsigned int mem_fclk_21285;
+
+extern int __pure cpu_architecture(void);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_ARM_SYSTEM_INFO_H */
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
new file mode 100644
index 0000000..f5cf1e8
--- /dev/null
+++ b/arch/arm/include/asm/system_misc.h
@@ -0,0 +1,35 @@
+#ifndef __ASM_ARM_SYSTEM_MISC_H
+#define __ASM_ARM_SYSTEM_MISC_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/irqflags.h>
+
+#include <asm/outercache.h>
+
+extern int __pure cpu_architecture(void);
+extern void cpu_init(void);
+
+void soft_restart(unsigned long);
+extern void (*arm_pm_restart)(char str, const char *cmd);
+
+#define UDBG_UNDEFINED	(1 << 0)
+#define UDBG_SYSCALL	(1 << 1)
+#define UDBG_BADABORT	(1 << 2)
+#define UDBG_SEGV	(1 << 3)
+#define UDBG_BUS	(1 << 4)
+
+extern unsigned int user_debug;
+
+#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
+
+extern void disable_hlt(void);
+extern void enable_hlt(void);
+
+void cpu_idle_wait(void);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_ARM_SYSTEM_MISC_H */
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 2958976..71f6536 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -16,8 +16,8 @@
 #include <asm/errno.h>
 #include <asm/memory.h>
 #include <asm/domain.h>
-#include <asm/system.h>
 #include <asm/unified.h>
+#include <asm/compiler.h>
 
 #define VERIFY_READ 0
 #define VERIFY_WRITE 1
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 5b0bce6..b57c75e 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -18,7 +18,6 @@
 #include <linux/io.h>
 
 #include <asm/checksum.h>
-#include <asm/system.h>
 #include <asm/ftrace.h>
 
 /*
diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c
index ddba41d..d0d1e83 100644
--- a/arch/arm/kernel/elf.c
+++ b/arch/arm/kernel/elf.c
@@ -3,6 +3,7 @@
 #include <linux/personality.h>
 #include <linux/binfmts.h>
 #include <linux/elf.h>
+#include <asm/system_info.h>
 
 int elf_check_arch(const struct elf32_hdr *x)
 {
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index be16a48..0260594 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -24,7 +24,6 @@
 #include <asm/unwind.h>
 #include <asm/unistd.h>
 #include <asm/tls.h>
-#include <asm/system.h>
 
 #include "entry-header.S"
 #include <asm/entry-macro-multi.S>
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 4c164ec..0b484c2 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -44,7 +44,6 @@
 #include <asm/cacheflush.h>
 #include <asm/fiq.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/traps.h>
 
 static unsigned long no_fiq_insn;
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index d46f259..601d2fd 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -18,7 +18,6 @@
 #include <asm/ptrace.h>
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
-#include <asm/system.h>
 
 /*
  * Kernel startup entry point.
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 6d57911..db344db 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -20,8 +20,8 @@
 #include <asm/asm-offsets.h>
 #include <asm/memory.h>
 #include <asm/thread_info.h>
-#include <asm/system.h>
 #include <asm/pgtable.h>
+#include <asm/cr_reg.h>
 
 #ifdef CONFIG_DEBUG_LL
 #include <mach/debug-macro.S>
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index d6a95ef..ba386bd 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -34,7 +34,6 @@
 #include <asm/current.h>
 #include <asm/hw_breakpoint.h>
 #include <asm/kdebug.h>
-#include <asm/system.h>
 #include <asm/traps.h>
 
 /* Breakpoint currently in use for each BRP. */
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 3efd82c..6a6a097 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -36,7 +36,6 @@
 #include <linux/proc_fs.h>
 
 #include <asm/exception.h>
-#include <asm/system.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 764bd45..e097865 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -12,7 +12,6 @@
 #include <asm/mmu_context.h>
 #include <asm/cacheflush.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
 
 extern const unsigned char relocate_new_kernel[];
 extern const unsigned int relocate_new_kernel_size;
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 971d65c..784222c 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -35,7 +35,6 @@
 #include <asm/cacheflush.h>
 #include <asm/leds.h>
 #include <asm/processor.h>
-#include <asm/system.h>
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index ede6443..45956c9 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -26,7 +26,6 @@
 #include <linux/audit.h>
 
 #include <asm/pgtable.h>
-#include <asm/system.h>
 #include <asm/traps.h>
 
 #define REG_PC	15
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index a255c39..e20ed9b 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -44,7 +44,6 @@
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
 #include <asm/tlbflush.h>
-#include <asm/system.h>
 
 #include <asm/prom.h>
 #include <asm/mach/arch.h>
@@ -53,6 +52,9 @@
 #include <asm/traps.h>
 #include <asm/unwind.h>
 #include <asm/memblock.h>
+#include <asm/system_info.h>
+#include <asm/system_misc.h>
+#include <asm/cr_reg.h>
 
 #if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 #include "compat.h"
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 1f268bd..987dcf3 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -4,7 +4,6 @@
 #include <asm/assembler.h>
 #include <asm/glue-cache.h>
 #include <asm/glue-proc.h>
-#include <asm/system.h>
 	.text
 
 /*
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index f84dfe6..cd77743 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -29,11 +29,11 @@
 #include <linux/atomic.h>
 #include <asm/cacheflush.h>
 #include <asm/exception.h>
-#include <asm/system.h>
 #include <asm/unistd.h>
 #include <asm/traps.h>
 #include <asm/unwind.h>
 #include <asm/tls.h>
+#include <asm/system_misc.h>
 
 #include "signal.h"
 
diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c
index 1512144..dd9a6cd 100644
--- a/arch/arm/mach-clps711x/p720t-leds.c
+++ b/arch/arm/mach-clps711x/p720t-leds.c
@@ -25,7 +25,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 
 #include <asm/hardware/clps7111.h>
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 294aad0..e43dcc0 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -22,7 +22,6 @@
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-ebsa110/leds.c b/arch/arm/mach-ebsa110/leds.c
index 6a6ea57..101a320 100644
--- a/arch/arm/mach-ebsa110/leds.c
+++ b/arch/arm/mach-ebsa110/leds.c
@@ -17,7 +17,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 
 static spinlock_t leds_lock;
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index f685650..94a7087 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -21,7 +21,6 @@
 #include <video/vga.h>
 
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 #include <asm/hardware/dec21285.h>
 
diff --git a/arch/arm/mach-footbridge/ebsa285-leds.c b/arch/arm/mach-footbridge/ebsa285-leds.c
index 4e10090..5bd2667 100644
--- a/arch/arm/mach-footbridge/ebsa285-leds.c
+++ b/arch/arm/mach-footbridge/ebsa285-leds.c
@@ -24,7 +24,6 @@
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
 
 #define LED_STATE_ENABLED	1
 #define LED_STATE_CLAIMED	2
diff --git a/arch/arm/mach-footbridge/netwinder-leds.c b/arch/arm/mach-footbridge/netwinder-leds.c
index e57102e..5a2bd89 100644
--- a/arch/arm/mach-footbridge/netwinder-leds.c
+++ b/arch/arm/mach-footbridge/netwinder-leds.c
@@ -24,7 +24,6 @@
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
 
 #define LED_STATE_ENABLED	1
 #define LED_STATE_CLAIMED	2
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index 42afc29..3189a60 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -32,7 +32,6 @@
 #include <linux/scatterlist.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <mach/dma-v1.h>
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 019f0ab..d2fd9f3 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -27,7 +27,6 @@
 #include <mach/platform.h>
 #include <asm/irq.h>
 #include <mach/cm.h>
-#include <asm/system.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index 28be186..466defa 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -29,7 +29,6 @@
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 #include <mach/cm.h>
 
diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c
index 520b6bf..36068f4 100644
--- a/arch/arm/mach-integrator/pci.c
+++ b/arch/arm/mach-integrator/pci.c
@@ -27,7 +27,6 @@
 #include <linux/init.h>
 
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 3c82566..9d47b4c 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -32,7 +32,6 @@
 #include <mach/platform.h>
 #include <asm/irq.h>
 #include <asm/signal.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 #include <asm/irq_regs.h>
 
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
index cdae24e..bbf54d7 100644
--- a/arch/arm/mach-iop33x/uart.c
+++ b/arch/arm/mach-iop33x/uart.c
@@ -22,7 +22,6 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
-#include <asm/system.h>
 #include <asm/memory.h>
 #include <mach/hardware.h>
 #include <asm/hardware/iop3xx.h>
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 81c4537..f214cdf 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -32,7 +32,6 @@
 #include <asm/memory.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
 
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index e872d23..4867f40 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -36,7 +36,6 @@
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index f53e911..558f5f8 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -29,7 +29,6 @@
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index a2e7c39..33c6d5f 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -29,7 +29,6 @@
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 634b6c8..910426a 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -30,7 +30,6 @@
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 7632bea..5196c39 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -34,7 +34,6 @@
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 626fda4..7e9a1f3 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -26,7 +26,6 @@
 #include <linux/io.h>
 
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index 0923bb9..ccdec42 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -34,7 +34,6 @@
 #include <asm/memory.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
 
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
index 8f2487e..d142d45 100644
--- a/arch/arm/mach-ixp23xx/espresso.c
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -32,7 +32,6 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
 
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index 5d5dd3e..b0e07db 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -36,7 +36,6 @@
 #include <asm/memory.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
 
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 25b5c46..bdf2866 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -28,7 +28,6 @@
 
 #include <asm/irq.h>
 #include <asm/sizes.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
index 377283f..eaaa3fa 100644
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -36,7 +36,6 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
 
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 5eff15f..0f445d3 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -32,7 +32,6 @@
 #include <asm/cputype.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index c0e3d69..78ae12c 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -12,7 +12,6 @@
 #include <linux/pci.h>
 #include <linux/serial_8250.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 97b8191..4a8ea0d 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -27,7 +27,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
-#include <asm/system.h>
 #include <mach/system.h>
 #include <mach/vreg.h>
 #include <mach/board.h>
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 54f91ad..32fe638 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -25,7 +25,6 @@
 #include <linux/module.h>
 
 #include <asm/proc-fns.h>
-#include <asm/system.h>
 
 #include <mach/mxs.h>
 #include <mach/common.h>
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
index 4b818eb..f6b14a1 100644
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ b/arch/arm/mach-omap1/leds-h2p2-debug.c
@@ -17,7 +17,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 
 #include <plat/fpga.h>
diff --git a/arch/arm/mach-omap1/leds-innovator.c b/arch/arm/mach-omap1/leds-innovator.c
index 9b99c28..3a066ee 100644
--- a/arch/arm/mach-omap1/leds-innovator.c
+++ b/arch/arm/mach-omap1/leds-innovator.c
@@ -5,7 +5,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
index da09f43..936ed42 100644
--- a/arch/arm/mach-omap1/leds-osk.c
+++ b/arch/arm/mach-omap1/leds-osk.c
@@ -8,7 +8,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 5fdef7a..087dba0 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -27,7 +27,6 @@
 #include <linux/io.h>
 #include <linux/spinlock.h>
 
-#include <asm/system.h>
 
 #include <plat/mux.h>
 
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index b8faffa..7595e0a 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -44,7 +44,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 9a54ef4..10bcd13 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -46,7 +46,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 611a0e3..e974d33 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -35,7 +35,6 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 
-#include <asm/system.h>
 
 #include <plat/omap_hwmod.h>
 
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 1d5d010..069f8fc 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -46,7 +46,6 @@
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
 #include <asm/smp_scu.h>
-#include <asm/system.h>
 #include <asm/pgalloc.h>
 #include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index abd2834..9f6b83d 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -10,7 +10,6 @@
  */
 
 #include <linux/linkage.h>
-#include <asm/system.h>
 #include <asm/smp_scu.h>
 #include <asm/memory.h>
 #include <asm/hardware/cache-l2x0.h>
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 5272131..0c9e413 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -22,7 +22,6 @@
 #include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/system.h>
 #include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 9a8697b..c1b5d8a 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -21,7 +21,6 @@
 #include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/system.h>
 #include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 09c7365..949eaa8 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -21,7 +21,6 @@
 #include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/system.h>
 #include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index 4cfb40b..977538f 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -32,7 +32,6 @@
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
index 7fa4bf2..a4739e9 100644
--- a/arch/arm/mach-pnx4008/dma.c
+++ b/arch/arm/mach-pnx4008/dma.c
@@ -24,7 +24,6 @@
 #include <linux/io.h>
 #include <linux/gfp.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <mach/dma.h>
 #include <asm/dma-mapping.h>
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 7608c7a..41e4201 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -28,7 +28,6 @@
 #include <asm/setup.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
index 0c8aad4..0cfe8af 100644
--- a/arch/arm/mach-pnx4008/time.c
+++ b/arch/arm/mach-pnx4008/time.c
@@ -24,7 +24,6 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 11f1e73..de9d45e 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -40,7 +40,6 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 5432ecb..4225417 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -22,7 +22,6 @@
 #include <linux/init.h>
 
 #include <mach/hardware.h>
-#include <asm/system.h>
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-pxa/leds-idp.c b/arch/arm/mach-pxa/leds-idp.c
index 8b9c171..06b0600 100644
--- a/arch/arm/mach-pxa/leds-idp.c
+++ b/arch/arm/mach-pxa/leds-idp.c
@@ -16,7 +16,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include <mach/pxa25x.h>
 #include <mach/idp.h>
diff --git a/arch/arm/mach-pxa/leds-lubbock.c b/arch/arm/mach-pxa/leds-lubbock.c
index e26d5ef..0bd85c8 100644
--- a/arch/arm/mach-pxa/leds-lubbock.c
+++ b/arch/arm/mach-pxa/leds-lubbock.c
@@ -15,7 +15,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <mach/pxa25x.h>
 #include <mach/lubbock.h>
 
diff --git a/arch/arm/mach-pxa/leds-mainstone.c b/arch/arm/mach-pxa/leds-mainstone.c
index db4af5e..4058ab3 100644
--- a/arch/arm/mach-pxa/leds-mainstone.c
+++ b/arch/arm/mach-pxa/leds-mainstone.c
@@ -14,7 +14,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include <mach/pxa27x.h>
 #include <mach/mainstone.h>
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 744baee..89d98c8 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -34,7 +34,6 @@
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
-#include <asm/system.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index acd329a..45868bb 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -33,7 +33,6 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c
index ad66035..56e1333 100644
--- a/arch/arm/mach-sa1100/dma.c
+++ b/arch/arm/mach-sa1100/dma.c
@@ -16,7 +16,6 @@
 #include <linux/spinlock.h>
 #include <linux/errno.h>
 
-#include <asm/system.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <mach/dma.h>
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index bb10ee2..17caece 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -21,7 +21,6 @@
 
 #include <asm/div64.h>
 #include <mach/hardware.h>
-#include <asm/system.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-sa1100/leds-assabet.c b/arch/arm/mach-sa1100/leds-assabet.c
index 64e9b4b..3699176 100644
--- a/arch/arm/mach-sa1100/leds-assabet.c
+++ b/arch/arm/mach-sa1100/leds-assabet.c
@@ -13,7 +13,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <mach/assabet.h>
 
 #include "leds.h"
diff --git a/arch/arm/mach-sa1100/leds-badge4.c b/arch/arm/mach-sa1100/leds-badge4.c
index cf1e384..f99fac3 100644
--- a/arch/arm/mach-sa1100/leds-badge4.c
+++ b/arch/arm/mach-sa1100/leds-badge4.c
@@ -14,7 +14,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-sa1100/leds-cerf.c b/arch/arm/mach-sa1100/leds-cerf.c
index 259b48e..040540f 100644
--- a/arch/arm/mach-sa1100/leds-cerf.c
+++ b/arch/arm/mach-sa1100/leds-cerf.c
@@ -7,7 +7,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-sa1100/leds-hackkit.c b/arch/arm/mach-sa1100/leds-hackkit.c
index 2bce137..6a23524 100644
--- a/arch/arm/mach-sa1100/leds-hackkit.c
+++ b/arch/arm/mach-sa1100/leds-hackkit.c
@@ -13,7 +13,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-sa1100/leds-lart.c b/arch/arm/mach-sa1100/leds-lart.c
index 0505a1f..a51830c 100644
--- a/arch/arm/mach-sa1100/leds-lart.c
+++ b/arch/arm/mach-sa1100/leds-lart.c
@@ -13,7 +13,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index bf85b8b..2fa499e 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -30,7 +30,6 @@
 #include <mach/hardware.h>
 #include <asm/memory.h>
 #include <asm/suspend.h>
-#include <asm/system.h>
 #include <asm/mach/time.h>
 
 extern int sa1100_finish_suspend(unsigned long);
diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c
index ccd4918..2560907 100644
--- a/arch/arm/mach-shark/leds.c
+++ b/arch/arm/mach-shark/leds.c
@@ -23,7 +23,6 @@
 #include <linux/io.h>
 
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #define LED_STATE_ENABLED	1
 #define LED_STATE_CLAIMED	2
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
index 1b23342..21b09b6 100644
--- a/arch/arm/mach-shmobile/cpuidle.c
+++ b/arch/arm/mach-shmobile/cpuidle.c
@@ -13,7 +13,6 @@
 #include <linux/suspend.h>
 #include <linux/module.h>
 #include <linux/err.h>
-#include <asm/system.h>
 #include <asm/io.h>
 
 static void shmobile_enter_wfi(void)
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index c38ba7b..a18a4ae 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -18,7 +18,6 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/console.h>
-#include <asm/system.h>
 #include <asm/io.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index fcf8b17..a3bdb12 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -21,7 +21,6 @@
 #include <linux/irq.h>
 #include <linux/bitrev.h>
 #include <linux/console.h>
-#include <asm/system.h>
 #include <asm/io.h>
 #include <asm/tlbflush.h>
 #include <asm/suspend.h>
diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
index c1febe1..12d760c 100644
--- a/arch/arm/mach-shmobile/suspend.c
+++ b/arch/arm/mach-shmobile/suspend.c
@@ -12,7 +12,6 @@
 #include <linux/suspend.h>
 #include <linux/module.h>
 #include <linux/err.h>
-#include <asm/system.h>
 #include <asm/io.h>
 
 static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index bb5ce39..7a065f0 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -30,7 +30,6 @@
 #include <linux/io.h>
 #include <linux/suspend.h>
 
-#include <asm/system.h>
 
 #include <mach/clk.h>
 
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 02b7b93..f0932b5 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -36,7 +36,6 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 
-#include <asm/system.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/hardware/arm_timer.h>
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 90069bc..787cf5f 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -24,7 +24,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 
 /*
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
index 3034a4d..e352494 100644
--- a/arch/arm/mach-vexpress/hotplug.c
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -14,7 +14,6 @@
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
-#include <asm/system.h>
 
 extern volatile int pen_release;
 
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index caf14dc..b524eb2 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -22,8 +22,9 @@
 #include <linux/sched.h>
 #include <linux/uaccess.h>
 
-#include <asm/system.h>
 #include <asm/unaligned.h>
+#include <asm/cr_reg.h>
+#include <asm/system_info.h>
 
 #include "fault.h"
 
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index 5a32020..c4ae2b4 100644
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -18,7 +18,6 @@
  */
 #include <linux/init.h>
 #include <linux/highmem.h>
-#include <asm/system.h>
 #include <asm/cputype.h>
 #include <asm/cacheflush.h>
 
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index bb7eac3..2da5df7 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -21,9 +21,10 @@
 #include <linux/perf_event.h>
 
 #include <asm/exception.h>
-#include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
+#include <asm/system_misc.h>
+#include <asm/system_info.h>
 
 #include "fault.h"
 
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 1a8d4aa..062d61a 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -16,7 +16,6 @@
 #include <asm/cachetype.h>
 #include <asm/highmem.h>
 #include <asm/smp_plat.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 
 #include "mm.h"
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index feacf4c..ab88ed4 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -5,6 +5,7 @@
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
 #include <asm/sections.h>
+#include <asm/system_info.h>
 
 pgd_t *idmap_pgd;
 
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 80632e8..436ebee 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -32,6 +32,8 @@
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
 #include <asm/sizes.h>
+#include <asm/system_info.h>
+#include <asm/cr_reg.h>
 
 #include <asm/mach/map.h>
 #include "mm.h"
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 94c5a0c..bd48a73 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -26,6 +26,8 @@
 #include <asm/tlb.h>
 #include <asm/highmem.h>
 #include <asm/traps.h>
+#include <asm/cr_reg.h>
+#include <asm/system_info.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c
index a3e78cc..8121294 100644
--- a/arch/arm/mm/pgd.c
+++ b/arch/arm/mm/pgd.c
@@ -15,6 +15,7 @@
 #include <asm/pgalloc.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
+#include <asm/cr_reg.h>
 
 #include "mm.h"
 
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 272558a..d217e97 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -22,7 +22,6 @@
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
-#include <asm/system.h>
 
 #include "proc-macros.S"
 
diff --git a/arch/arm/nwfpe/fpa11.c b/arch/arm/nwfpe/fpa11.c
index cc60acd..2782ebc 100644
--- a/arch/arm/nwfpe/fpa11.c
+++ b/arch/arm/nwfpe/fpa11.c
@@ -28,7 +28,6 @@
 
 #include <linux/compiler.h>
 #include <linux/string.h>
-#include <asm/system.h>
 
 /* Reset the FPA11 chip.  Called to initialize and reset the emulator. */
 static void resetFPA11(void)
diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c
index 4efe392..88215ad 100644
--- a/arch/arm/plat-iop/i2c.c
+++ b/arch/arm/plat-iop/i2c.c
@@ -23,7 +23,6 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
-#include <asm/system.h>
 #include <asm/memory.h>
 #include <mach/hardware.h>
 #include <asm/hardware/iop3xx.h>
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index f4d40a2..bb26981 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -20,7 +20,6 @@
 #include <linux/io.h>
 #include <asm/irq.h>
 #include <asm/signal.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach/pci.h>
 #include <asm/hardware/iop3xx.h>
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 3599bf2..8f12074 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -26,7 +26,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <asm/proc-fns.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 
 void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 61a1ec2..39407cb 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -15,7 +15,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 
 #include <plat/fpga.h>
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 002fb4d..dbb1049 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,7 +36,6 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <plat/dma.h>
 
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 0d4aa0d..976fc80 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -26,7 +26,6 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/system.h>
 #include <linux/spinlock.h>
 #include <plat/mux.h>
 
diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c
index 2d3c19d..79ef102 100644
--- a/arch/arm/plat-pxa/dma.c
+++ b/arch/arm/plat-pxa/dma.c
@@ -20,7 +20,6 @@
 #include <linux/errno.h>
 #include <linux/dma-mapping.h>
 
-#include <asm/system.h>
 #include <asm/irq.h>
 #include <asm/memory.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 2bab4c9..28f898f 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -27,7 +27,6 @@
 #include <linux/errno.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <mach/dma.h>
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
index 81c06d4..46b426e 100644
--- a/arch/arm/plat-samsung/cpu.c
+++ b/arch/arm/plat-samsung/cpu.c
@@ -15,7 +15,6 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 
 #include <mach/map.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index e3bb806..4dcb11c 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -28,7 +28,6 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 
-#include <asm/system.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 8f3ccdd..f5cc605 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -21,6 +21,8 @@
 #include <asm/cputype.h>
 #include <asm/thread_notify.h>
 #include <asm/vfp.h>
+#include <asm/cr_reg.h>
+#include <asm/system_info.h>
 
 #include "vfpinstr.h"
 #include "vfp.h"



From b-cousson at ti.com  Mon Mar 12 19:41:40 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Tue, 13 Mar 2012 00:41:40 +0100
Subject: [GIT PULL] ARM: OMAP: i2c, gpio, spi and regulator DTS updates
Message-ID: <4F5E89B4.4010505@ti.com>

Hi Tony,

Here are the remaining DTS patches for 3.4.

Ideally all the driver DT adaptation should have been merged before that one.

This series is based on your lo/dt-part2 branch.

Thanks,
Benoit


The following changes since commit 328ae2cb50af2f96b6061eb462aa92966a462bbc:
  Ilya Yanok (1):
        arm/dts: mt_ventoux: very basic support for TeeJet Mt.Ventoux board

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/dts/all

Benoit Cousson (11):
      arm/dts: twl6030: Add DTS file for twl6030 PMIC
      arm/dts: twl4030: Add DTS file for twl4030 PM + Audio IC
      arm/dts: omap4-panda: Add twl6030 and i2c EEPROM
      arm/dts: omap4-sdp: Add twl6030, i2c3 and i2c4 devices
      arm/dts: omap3-beagle: Add twl4030 and i2c EEPROM
      ARM: OMAP2+: board-generic: Remove i2c static init
      arm/dts: OMAP4: Add gpio nodes
      arm/dts: OMAP3: Add gpio nodes
      arm/dts: OMAP4: Add SPI controller nodes
      arm/dts: OMAP3: Add SPI controller nodes
      arm/dts: omap4-sdp: Add ks8851 ethernet SPI device

Rajendra Nayak (1):
      arm/dts: twl: Pass regulator data from dt

 arch/arm/boot/dts/omap3-beagle.dts  |   35 ++++++++++++++
 arch/arm/boot/dts/omap3.dtsi        |   86 +++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap4-panda.dts   |   34 ++++++++++++++
 arch/arm/boot/dts/omap4-sdp.dts     |   73 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi        |   86 +++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/twl4030.dtsi      |   39 ++++++++++++++++
 arch/arm/boot/dts/twl6030.dtsi      |   86 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/board-generic.c |   37 +--------------
 arch/arm/mach-omap2/devices.c       |    4 +-
 arch/arm/mach-omap2/gpio.c          |    8 +++-
 10 files changed, 450 insertions(+), 38 deletions(-)
 create mode 100644 arch/arm/boot/dts/twl4030.dtsi
 create mode 100644 arch/arm/boot/dts/twl6030.dtsi



From linux at arm.linux.org.uk  Mon Mar 12 19:59:51 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 12 Mar 2012 23:59:51 +0000
Subject: Conflict between Versatile Express DT conversion and local
 timer updates
In-Reply-To: <20120312231016.GC10830@n2100.arm.linux.org.uk>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
Message-ID: <20120312235951.GA31601@n2100.arm.linux.org.uk>

On Mon, Mar 12, 2012 at 11:10:16PM +0000, Russell King - ARM Linux wrote:
> Marc, Pawel,
> 
> Your changes are conflicting badly.  Seriously badly.  So badly that I'm
> not bothering to fix the conflicts because I can't work out what the fix
> should be.
> 
> You both work for the same frigging organization and yet you seem to
> work completely independently (I really don't care if you work in
> different departments - the fact of the matter is you're touching the
> same code in completely different ways with zero coordination between
> yourselves.  That's simply broken workflow.)
> 
> For example, Marc's deleting arch/arm/plat-versatile/localtimer.c, but
> Pawel is modifying it to add DT support for Versatile Express.  The
> correct solution?  Hell knows.  And I don't want a solution to the merge
> conflict.  I want the merge conflict to go away (because I'm not frigging
> around applying the same git-rerere immune fixes to a tree I'm regenerating
> each night for the kernel autobuilder.)
> 
> I'm getting conflicts in arch/arm/mach-vexpress/ct-ca9x4.c and
> arch/arm/mach-ux500/timer.c as well, which I'm not going to bother trying
> to sort out - the obvious solution for ux500/timer.c doesn't look right.
> 
> I've a mind to drop the localtimer changes on the floor until after this
> merge window, but unfortunately they're part of devel-stable so I can't.

Correction: I haven't been pushing out my devel-stable branch for
apparantly two months (according to gitweb, and no one noticed?), so I
_could_ drop the merge of Marc's tree until the conflicts can be sanely
resolved.

> 
> How do we fix this?
> 
> (In the mean time, I've had to reset the kernel autobuilder back to last
> nights tree, which is -rc6 based.)
> 
> diff --cc arch/arm/mach-ux500/timer.c
> index cadf982,fd00024..0000000
> --- a/arch/arm/mach-ux500/timer.c
> +++ b/arch/arm/mach-ux500/timer.c
> @@@ -15,38 -15,22 +15,52 @@@
>   #include <mach/setup.h>
>   #include <mach/hardware.h>
>   
>  +#ifdef CONFIG_HAVE_ARM_TWD
>  +static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer,
>  +			      U5500_TWD_BASE, IRQ_LOCALTIMER);
>  +static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
>  +			      U8500_TWD_BASE, IRQ_LOCALTIMER);
>  +
>  +static void __init ux500_twd_init(void)
>  +{
>  +	struct twd_local_timer *twd_local_timer;
>  +	int err;
>  +
>  +	twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer :
>  +					   &u8500_twd_local_timer;
>  +
>  +	err = twd_local_timer_register(twd_local_timer);
>  +	if (err)
>  +		pr_err("twd_local_timer_register failed %d\n", err);
>  +}
>  +#else
>  +#define ux500_twd_init()	do { } while(0)
>  +#endif
>  +
>   static void __init ux500_timer_init(void)
>   {
> + 	void __iomem *mtu_timer_base;
>   	void __iomem *prcmu_timer_base;
>  +	int err;
>   
>   	if (cpu_is_u5500()) {
> ++<<<<<<< HEAD
>  +		mtu_base = __io_address(U5500_MTU0_BASE);
>  +		prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
>  +	} else if (cpu_is_u8500()) {
>  +		mtu_base = __io_address(U8500_MTU0_BASE);
> ++=======
> + #ifdef CONFIG_LOCAL_TIMERS
> + 		twd_base = __io_address(U5500_TWD_BASE);
> + #endif
> + 		mtu_timer_base = __io_address(U5500_MTU0_BASE);
> + 		prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
> + 	} else if (cpu_is_u8500()) {
> + #ifdef CONFIG_LOCAL_TIMERS
> + 		twd_base = __io_address(U8500_TWD_BASE);
> + #endif
> + 		mtu_timer_base = __io_address(U8500_MTU0_BASE);
> ++>>>>>>> arm-soc
>   		prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
>   	} else {
>   		ux500_unknown_soc();
> @@@ -69,9 -53,8 +83,9 @@@
>   	 *
>   	 */
>   
> - 	nmdk_timer_init();
> + 	nmdk_timer_init(mtu_timer_base);
>   	clksrc_dbx500_prcmu_init(prcmu_timer_base);
>  +	ux500_twd_init();
>   }
>   
>   static void ux500_timer_reset(void)
> diff --cc arch/arm/mach-vexpress/ct-ca9x4.c
> index b391538,73791f0..0000000
> --- a/arch/arm/mach-vexpress/ct-ca9x4.c
> +++ b/arch/arm/mach-vexpress/ct-ca9x4.c
> @@@ -54,44 -42,17 +42,50 @@@ static struct map_desc ct_ca9x4_io_desc
>   static void __init ct_ca9x4_map_io(void)
>   {
>   	iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
> ++<<<<<<< HEAD
> ++=======
> + #ifdef CONFIG_LOCAL_TIMERS
> + 	twd_base = ioremap(A9_MPCORE_TWD, SZ_32);
> + #endif
> ++>>>>>>> arm-soc
>   }
>   
>  +#ifdef CONFIG_HAVE_ARM_TWD
>  +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
>  +
>  +static void __init ca9x4_twd_init(void)
>  +{
>  +	int err = twd_local_timer_register(&twd_local_timer);
>  +	if (err)
>  +		pr_err("twd_local_timer_register failed %d\n", err);
>  +}
>  +#else
>  +#define ca9x4_twd_init()	do {} while(0)
>  +#endif
>  +
>   static void __init ct_ca9x4_init_irq(void)
>   {
> ++<<<<<<< HEAD
>  +	gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
>  +		 MMIO_P2V(A9_MPCORE_GIC_CPU));
>  +	ca9x4_twd_init();
>  +}
>  +
>  +#if 0
>  +static void __init ct_ca9x4_timer_init(void)
>  +{
>  +	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
>  +	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
>  +
>  +	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
>  +	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
>  +		"ct-timer0");
> ++=======
> + 	gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
> + 		 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
> ++>>>>>>> arm-soc
>   }
>   
> - static struct sys_timer ct_ca9x4_timer = {
> - 	.init	= ct_ca9x4_timer_init,
> - };
> - #endif
> - 
>   static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
>   {
>   	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
> 


From kgene.kim at samsung.com  Sat Mar 10 05:19:08 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 02:19:08 -0800
Subject: [PATCH 4/5] PM / devfreq: update the name of EXYNOS clock register
In-Reply-To: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>
References: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331374749-23256-5-git-send-email-kgene.kim@samsung.com>

According to replacing the name of EXYNOS clock registers,
this patch updates exynos4_bus.c file where it is used.

Acked-by: MyungJoo Ham <myungjoo.ham at samsung.com>
Cc: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 drivers/devfreq/exynos4_bus.c |  224 ++++++++++++++++++++--------------------
 1 files changed, 112 insertions(+), 112 deletions(-)

diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
index 6460577..565aa98 100644
--- a/drivers/devfreq/exynos4_bus.c
+++ b/drivers/devfreq/exynos4_bus.c
@@ -311,51 +311,51 @@ static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp)
 	/* Change Divider - DMC0 */
 	tmp = data->dmc_divtable[index];
 
-	__raw_writel(tmp, S5P_CLKDIV_DMC0);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
 	} while (tmp & 0x11111111);
 
 	/* Change Divider - TOP */
 	tmp = data->top_divtable[index];
 
-	__raw_writel(tmp, S5P_CLKDIV_TOP);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
 	} while (tmp & 0x11111);
 
 	/* Change Divider - LEFTBUS */
-	tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
 
-	tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
+	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
 
 	tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
-				S5P_CLKDIV_BUS_GDLR_SHIFT) |
+				EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
 		(exynos4210_clkdiv_lr_bus[index][1] <<
-				S5P_CLKDIV_BUS_GPLR_SHIFT));
+				EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
 
-	__raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
 	} while (tmp & 0x11);
 
 	/* Change Divider - RIGHTBUS */
-	tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
 
-	tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
+	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
 
 	tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
-				S5P_CLKDIV_BUS_GDLR_SHIFT) |
+				EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
 		(exynos4210_clkdiv_lr_bus[index][1] <<
-				S5P_CLKDIV_BUS_GPLR_SHIFT));
+				EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
 
-	__raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
 	} while (tmp & 0x11);
 
 	return 0;
@@ -376,137 +376,137 @@ static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp)
 	/* Change Divider - DMC0 */
 	tmp = data->dmc_divtable[index];
 
-	__raw_writel(tmp, S5P_CLKDIV_DMC0);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
 	} while (tmp & 0x11111111);
 
 	/* Change Divider - DMC1 */
-	tmp = __raw_readl(S5P_CLKDIV_DMC1);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
 
-	tmp &= ~(S5P_CLKDIV_DMC1_G2D_ACP_MASK |
-		S5P_CLKDIV_DMC1_C2C_MASK |
-		S5P_CLKDIV_DMC1_C2CACLK_MASK);
+	tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK |
+		EXYNOS4_CLKDIV_DMC1_C2C_MASK |
+		EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK);
 
 	tmp |= ((exynos4x12_clkdiv_dmc1[index][0] <<
-				S5P_CLKDIV_DMC1_G2D_ACP_SHIFT) |
+				EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) |
 		(exynos4x12_clkdiv_dmc1[index][1] <<
-				S5P_CLKDIV_DMC1_C2C_SHIFT) |
+				EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) |
 		(exynos4x12_clkdiv_dmc1[index][2] <<
-				S5P_CLKDIV_DMC1_C2CACLK_SHIFT));
+				EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT));
 
-	__raw_writel(tmp, S5P_CLKDIV_DMC1);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_DMC1);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1);
 	} while (tmp & 0x111111);
 
 	/* Change Divider - TOP */
-	tmp = __raw_readl(S5P_CLKDIV_TOP);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
 
-	tmp &= ~(S5P_CLKDIV_TOP_ACLK266_GPS_MASK |
-		S5P_CLKDIV_TOP_ACLK100_MASK |
-		S5P_CLKDIV_TOP_ACLK160_MASK |
-		S5P_CLKDIV_TOP_ACLK133_MASK |
-		S5P_CLKDIV_TOP_ONENAND_MASK);
+	tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK |
+		EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
+		EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
+		EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
+		EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
 
 	tmp |= ((exynos4x12_clkdiv_top[index][0] <<
-				S5P_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
+				EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
 		(exynos4x12_clkdiv_top[index][1] <<
-				S5P_CLKDIV_TOP_ACLK100_SHIFT) |
+				EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
 		(exynos4x12_clkdiv_top[index][2] <<
-				S5P_CLKDIV_TOP_ACLK160_SHIFT) |
+				EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
 		(exynos4x12_clkdiv_top[index][3] <<
-				S5P_CLKDIV_TOP_ACLK133_SHIFT) |
+				EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
 		(exynos4x12_clkdiv_top[index][4] <<
-				S5P_CLKDIV_TOP_ONENAND_SHIFT));
+				EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
 
-	__raw_writel(tmp, S5P_CLKDIV_TOP);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
 	} while (tmp & 0x11111);
 
 	/* Change Divider - LEFTBUS */
-	tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
 
-	tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
+	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
 
 	tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
-				S5P_CLKDIV_BUS_GDLR_SHIFT) |
+				EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
 		(exynos4x12_clkdiv_lr_bus[index][1] <<
-				S5P_CLKDIV_BUS_GPLR_SHIFT));
+				EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
 
-	__raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
 	} while (tmp & 0x11);
 
 	/* Change Divider - RIGHTBUS */
-	tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
 
-	tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
+	tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
 
 	tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
-				S5P_CLKDIV_BUS_GDLR_SHIFT) |
+				EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
 		(exynos4x12_clkdiv_lr_bus[index][1] <<
-				S5P_CLKDIV_BUS_GPLR_SHIFT));
+				EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
 
-	__raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
 	} while (tmp & 0x11);
 
 	/* Change Divider - MFC */
-	tmp = __raw_readl(S5P_CLKDIV_MFC);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_MFC);
 
-	tmp &= ~(S5P_CLKDIV_MFC_MASK);
+	tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK);
 
 	tmp |= ((exynos4x12_clkdiv_sclkip[index][0] <<
-				S5P_CLKDIV_MFC_SHIFT));
+				EXYNOS4_CLKDIV_MFC_SHIFT));
 
-	__raw_writel(tmp, S5P_CLKDIV_MFC);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_MFC);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_MFC);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC);
 	} while (tmp & 0x1);
 
 	/* Change Divider - JPEG */
-	tmp = __raw_readl(S5P_CLKDIV_CAM1);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1);
 
-	tmp &= ~(S5P_CLKDIV_CAM1_JPEG_MASK);
+	tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK);
 
 	tmp |= ((exynos4x12_clkdiv_sclkip[index][1] <<
-				S5P_CLKDIV_CAM1_JPEG_SHIFT));
+				EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT));
 
-	__raw_writel(tmp, S5P_CLKDIV_CAM1);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CAM1);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
 	} while (tmp & 0x1);
 
 	/* Change Divider - FIMC0~3 */
-	tmp = __raw_readl(S5P_CLKDIV_CAM);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_CAM);
 
-	tmp &= ~(S5P_CLKDIV_CAM_FIMC0_MASK | S5P_CLKDIV_CAM_FIMC1_MASK |
-		S5P_CLKDIV_CAM_FIMC2_MASK | S5P_CLKDIV_CAM_FIMC3_MASK);
+	tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK |
+		EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK);
 
 	tmp |= ((exynos4x12_clkdiv_sclkip[index][2] <<
-				S5P_CLKDIV_CAM_FIMC0_SHIFT) |
+				EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) |
 		(exynos4x12_clkdiv_sclkip[index][2] <<
-				S5P_CLKDIV_CAM_FIMC1_SHIFT) |
+				EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) |
 		(exynos4x12_clkdiv_sclkip[index][2] <<
-				S5P_CLKDIV_CAM_FIMC2_SHIFT) |
+				EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) |
 		(exynos4x12_clkdiv_sclkip[index][2] <<
-				S5P_CLKDIV_CAM_FIMC3_SHIFT));
+				EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT));
 
-	__raw_writel(tmp, S5P_CLKDIV_CAM);
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CAM);
 
 	do {
-		tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1);
+		tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
 	} while (tmp & 0x1111);
 
 	return 0;
@@ -760,55 +760,55 @@ static int exynos4210_init_tables(struct busfreq_data *data)
 	int mgrp;
 	int i, err = 0;
 
-	tmp = __raw_readl(S5P_CLKDIV_DMC0);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
 	for (i = LV_0; i < EX4210_LV_NUM; i++) {
-		tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK |
-			S5P_CLKDIV_DMC0_ACPPCLK_MASK |
-			S5P_CLKDIV_DMC0_DPHY_MASK |
-			S5P_CLKDIV_DMC0_DMC_MASK |
-			S5P_CLKDIV_DMC0_DMCD_MASK |
-			S5P_CLKDIV_DMC0_DMCP_MASK |
-			S5P_CLKDIV_DMC0_COPY2_MASK |
-			S5P_CLKDIV_DMC0_CORETI_MASK);
+		tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
+			EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
+			EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMC_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMCP_MASK |
+			EXYNOS4_CLKDIV_DMC0_COPY2_MASK |
+			EXYNOS4_CLKDIV_DMC0_CORETI_MASK);
 
 		tmp |= ((exynos4210_clkdiv_dmc0[i][0] <<
-					S5P_CLKDIV_DMC0_ACP_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
 			(exynos4210_clkdiv_dmc0[i][1] <<
-					S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
 			(exynos4210_clkdiv_dmc0[i][2] <<
-					S5P_CLKDIV_DMC0_DPHY_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
 			(exynos4210_clkdiv_dmc0[i][3] <<
-					S5P_CLKDIV_DMC0_DMC_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
 			(exynos4210_clkdiv_dmc0[i][4] <<
-					S5P_CLKDIV_DMC0_DMCD_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
 			(exynos4210_clkdiv_dmc0[i][5] <<
-					S5P_CLKDIV_DMC0_DMCP_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
 			(exynos4210_clkdiv_dmc0[i][6] <<
-					S5P_CLKDIV_DMC0_COPY2_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
 			(exynos4210_clkdiv_dmc0[i][7] <<
-					S5P_CLKDIV_DMC0_CORETI_SHIFT));
+					EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT));
 
 		data->dmc_divtable[i] = tmp;
 	}
 
-	tmp = __raw_readl(S5P_CLKDIV_TOP);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
 	for (i = LV_0; i <  EX4210_LV_NUM; i++) {
-		tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK |
-			S5P_CLKDIV_TOP_ACLK100_MASK |
-			S5P_CLKDIV_TOP_ACLK160_MASK |
-			S5P_CLKDIV_TOP_ACLK133_MASK |
-			S5P_CLKDIV_TOP_ONENAND_MASK);
+		tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK |
+			EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
+			EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
+			EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
+			EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
 
 		tmp |= ((exynos4210_clkdiv_top[i][0] <<
-					S5P_CLKDIV_TOP_ACLK200_SHIFT) |
+					EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
 			(exynos4210_clkdiv_top[i][1] <<
-					S5P_CLKDIV_TOP_ACLK100_SHIFT) |
+					EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
 			(exynos4210_clkdiv_top[i][2] <<
-					S5P_CLKDIV_TOP_ACLK160_SHIFT) |
+					EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
 			(exynos4210_clkdiv_top[i][3] <<
-					S5P_CLKDIV_TOP_ACLK133_SHIFT) |
+					EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
 			(exynos4210_clkdiv_top[i][4] <<
-					S5P_CLKDIV_TOP_ONENAND_SHIFT));
+					EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
 
 		data->top_divtable[i] = tmp;
 	}
@@ -872,28 +872,28 @@ static int exynos4x12_init_tables(struct busfreq_data *data)
 	tmp |= DMC_PAUSE_ENABLE;
 	__raw_writel(tmp, S5P_DMC_PAUSE_CTRL);
 
-	tmp = __raw_readl(S5P_CLKDIV_DMC0);
+	tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
 
 	for (i = 0; i <  EX4x12_LV_NUM; i++) {
-		tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK |
-			S5P_CLKDIV_DMC0_ACPPCLK_MASK |
-			S5P_CLKDIV_DMC0_DPHY_MASK |
-			S5P_CLKDIV_DMC0_DMC_MASK |
-			S5P_CLKDIV_DMC0_DMCD_MASK |
-			S5P_CLKDIV_DMC0_DMCP_MASK);
+		tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
+			EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
+			EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMC_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
+			EXYNOS4_CLKDIV_DMC0_DMCP_MASK);
 
 		tmp |= ((exynos4x12_clkdiv_dmc0[i][0] <<
-					S5P_CLKDIV_DMC0_ACP_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
 			(exynos4x12_clkdiv_dmc0[i][1] <<
-					S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
 			(exynos4x12_clkdiv_dmc0[i][2] <<
-					S5P_CLKDIV_DMC0_DPHY_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
 			(exynos4x12_clkdiv_dmc0[i][3] <<
-					S5P_CLKDIV_DMC0_DMC_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
 			(exynos4x12_clkdiv_dmc0[i][4] <<
-					S5P_CLKDIV_DMC0_DMCD_SHIFT) |
+					EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
 			(exynos4x12_clkdiv_dmc0[i][5] <<
-					S5P_CLKDIV_DMC0_DMCP_SHIFT));
+					EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT));
 
 		data->dmc_divtable[i] = tmp;
 	}
-- 
1.7.4.4



From plagnioj at jcrosoft.com  Mon Mar 12 11:14:37 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 12 Mar 2012 16:14:37 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <201203121606.26926.sr@denx.de>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <4F5E0993.9020000@gmail.com> <201203121606.26926.sr@denx.de>
Message-ID: <20120312151437.GC13869@game.jcrosoft.org>

On 16:06 Mon 12 Mar     , Stefan Roese wrote:
> Hi Rob,
> 
> On Monday 12 March 2012 15:34:59 Rob Herring wrote:
> > On 03/12/2012 09:05 AM, Stefan Roese wrote:
> > > This patch adds support to configure the STMMAC ethernet driver via
> > > device-tree instead of platform_data.
> > > 
> > > Currently, only the properties needed on SPEAr600 are provided. All
> > > other properties should be added once needed on other platforms.
> > > 
> > > Signed-off-by: Stefan Roese <sr at denx.de>
> > > Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
> > > Cc: Viresh Kumar <viresh.kumar at st.com>
> > > ---
> > > 
> > >  Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
> > >  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66
> > >  +++++++++++++++++++- 2 files changed, 103 insertions(+), 1 deletion(-)
> > >  create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt
> > > 
> > > diff --git a/Documentation/devicetree/bindings/net/stmmac.txt
> > > b/Documentation/devicetree/bindings/net/stmmac.txt new file mode 100644
> > > index 0000000..386a47f
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/net/stmmac.txt
> > > @@ -0,0 +1,38 @@
> > > +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
> > > +
> > > +Required properties:
> > > +- compatible: Should be "stm,gmac"
> > 
> > This is too generic. This should be 1 string per version of h/w.
> 
> Viresh, Giuseppe, can you please suggest a proper string for the SPEAr600 
> STMMAC core, including version?
IIRC this IP is the same as the sti7108

st,sti7018-gmac

as this IP has been used first on SH4

Best Regards,
J.


From javier.martin at vista-silicon.com  Fri Mar  9 10:20:41 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:41 +0100
Subject: [PATCH v3 05/13] dmaengine: imx-dma: remove
 'imxdma_config_channel_hw' function.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-6-git-send-email-javier.martin@vista-silicon.com>

This function is only used once in the driver and uses some
intermediary variables that are not needed anymore. For this
reason it's been merged with 'imxdma_control'.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   46 +++++++++++++---------------------------------
 1 files changed, 13 insertions(+), 33 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index f86ac06..d86b3d5 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -312,32 +312,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 }
 
 static int
-imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
-	int channel = imxdmac->channel;
-	u32 dreq = 0;
-
-	imxdmac->internal.hw_chaining = 0;
-
-	if (hw_chaining) {
-		imxdmac->internal.hw_chaining = 1;
-		if (!imxdma_hw_chain(&imxdmac->internal))
-			return -EINVAL;
-	}
-
-	if (dmareq)
-		dreq = CCR_REN;
-
-	imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
-	imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
-
-	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
-	return 0;
-}
-
-static int
 imxdma_setup_sg_hw(struct imxdma_desc *d,
 		 struct scatterlist *sg, unsigned int sgcount,
 		 unsigned int dma_length, unsigned int dev_addr,
@@ -626,7 +600,6 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct dma_slave_config *dmaengine_cfg = (void *)arg;
-	int ret;
 	unsigned long flags;
 	unsigned int mode = 0;
 
@@ -662,13 +635,20 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			mode = IMX_DMA_MEMSIZE_32;
 			break;
 		}
-		ret = imxdma_config_channel_hw(imxdmac,
-				mode | IMX_DMA_TYPE_FIFO,
-				IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
-				imxdmac->dma_request, 1);
 
-		if (ret)
-			return ret;
+		imxdmac->internal.hw_chaining = 1;
+		if (!imxdma_hw_chain(&imxdmac->internal))
+			return -EINVAL;
+		imxdmac->internal.ccr_from_device =
+			(mode | IMX_DMA_TYPE_FIFO) |
+			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
+			CCR_REN;
+		imxdmac->internal.ccr_to_device =
+			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
+			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
+		imx_dmav1_writel(imxdmac->dma_request,
+				 DMA_RSSR(imxdmac->channel));
+
 		/* Set burst length */
 		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
 				 DMA_BLR(imxdmac->channel));
-- 
1.7.0.4



From kgene.kim at samsung.com  Sun Mar 11 17:25:23 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 14:25:23 -0700
Subject: [PATCH 5/5] mmc: sdhci-s3c: setup pins using pinctrl interface
In-Reply-To: <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
Message-ID: <4F5D1843.1010608@samsung.com>

Thomas Abraham wrote:
> The platform specific callback to setup the sdhci pin mux and pin config
> is removed and the pinctrl subsystem interface is used to setup the
> mux and config.
> 
> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
> ---
>   drivers/mmc/host/sdhci-s3c.c |   15 +++++++++++++--
>   1 files changed, 13 insertions(+), 2 deletions(-)
> 
[...]

> 
> +#include<plat/map-s5p.h>
> +#include<plat/map-base.h>

You can add <mach/map.h> instead of above.

> +
>   static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>   {
>   	struct s3c_sdhci_platdata *pdata;
> @@ -538,6 +543,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>   	struct sdhci_s3c *sc;
>   	struct resource *res;
>   	int ret, irq, ptr, clks;
> +	char *pstate;
> 
>   	if (!pdev->dev.platform_data&&  !pdev->dev.of_node) {
>   		dev_err(dev, "no device data specified\n");
> @@ -643,8 +649,13 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>   	}
> 
>   	/* Ensure we have minimal gpio selected CMD/CLK/Detect */
> -	if (pdata->cfg_gpio)
> -		pdata->cfg_gpio(pdev, pdata->max_width);

I'm not sure we can remove above now for all of Samsung stuff?

> +	pstate = pdata->max_width ? "sdhci-pcfg8" : "sdhci-pcfg4";

Is this right? Current max_width can be 4 or 8 in each board file now.

> +	sc->pinctrl = pinctrl_get_select(&pdev->dev, pstate);
> +	if (IS_ERR(sc->pinctrl)) {
> +		dev_err(dev, "failed to setup pin configuration\n");
> +		ret = -ENXIO;
> +		goto err_req_regs;
> +	}
> 
>   	host->hw_name = "samsung-hsmmc";
>   	host->ops =&sdhci_s3c_ops;

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From plagnioj at jcrosoft.com  Sun Mar 11 14:25:37 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Sun, 11 Mar 2012 19:25:37 +0100
Subject: [PATCH 1/4 v5] of_spi: add generic binding support to specify
 cs gpio
In-Reply-To: <20120311140731.2D4F93E0979@localhost>
References: <1331122989-14451-1-git-send-email-plagnioj@jcrosoft.co>
 <1331317544-21735-1-git-send-email-plagnioj@jcrosoft.com>
 <20120311140731.2D4F93E0979@localhost>
Message-ID: <20120311182537.GS27213@game.jcrosoft.org>

On 08:07 Sun 11 Mar     , Grant Likely wrote:
> On Fri,  9 Mar 2012 19:25:44 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > This will allow to use gpio for chip select with no modification in the
> > driver binding
> > 
> > When use the cs-gpios, the gpio number will be passed via the cs_gpio field
> > and the number of chip select will automatically increased.
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Cc: devicetree-discuss at lists.ozlabs.org
> > Cc: spi-devel-general at lists.sourceforge.net
> > ---
> > v5:
> > 	update grant comment to simplify the cs_gpio management
> > 
> > Best Regards,
> > J.
> >  Documentation/devicetree/bindings/spi/spi-bus.txt |    6 ++
> >  drivers/spi/spi.c                                 |   55 +++++++++++++++++++-
> >  include/linux/spi/spi.h                           |    4 ++
> >  3 files changed, 62 insertions(+), 3 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
> > index e782add..c253379 100644
> > --- a/Documentation/devicetree/bindings/spi/spi-bus.txt
> > +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
> > @@ -12,6 +12,7 @@ The SPI master node requires the following properties:
> >  - #size-cells     - should be zero.
> >  - compatible      - name of SPI bus controller following generic names
> >      		recommended practice.
> > +- cs-gpios	  - (optional) gpios chip select.
> >  No other properties are required in the SPI bus node.  It is assumed
> >  that a driver for an SPI bus device will understand that it is an SPI bus.
> >  However, the binding does not attempt to define the specific method for
> > @@ -21,6 +22,8 @@ assumption that board specific platform code will be used to manage
> >  chip selects.  Individual drivers can define additional properties to
> >  support describing the chip select layout.
> >  
> > +If cs-gpios is used the number of chip select will automatically increased.
> > +
> >  SPI slave nodes must be children of the SPI master node and can
> >  contain the following properties.
> >  - reg             - (required) chip select address of device.
> > @@ -34,6 +37,9 @@ contain the following properties.
> >  - spi-cs-high     - (optional) Empty property indicating device requires
> >      		chip select active high
> >  
> > +If a gpio chipselect is used for the SPI slave the gpio number will be passed
> > +via the cs_gpio
> > +
> >  SPI example for an MPC5200 SPI bus:
> >  	spi at f00 {
> >  		#address-cells = <1>;
> > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> > index b2ccdea..446eee5 100644
> > --- a/drivers/spi/spi.c
> > +++ b/drivers/spi/spi.c
> > @@ -28,6 +28,7 @@
> >  #include <linux/mod_devicetable.h>
> >  #include <linux/spi/spi.h>
> >  #include <linux/of_spi.h>
> > +#include <linux/of_gpio.h>
> >  #include <linux/pm_runtime.h>
> >  #include <linux/export.h>
> >  
> > @@ -322,6 +323,7 @@ struct spi_device *spi_alloc_device(struct spi_master *master)
> >  	spi->dev.parent = &master->dev;
> >  	spi->dev.bus = &spi_bus_type;
> >  	spi->dev.release = spidev_release;
> > +	spi->cs_gpio = -EINVAL;
> >  	device_initialize(&spi->dev);
> >  	return spi;
> >  }
> > @@ -339,15 +341,16 @@ EXPORT_SYMBOL_GPL(spi_alloc_device);
> >  int spi_add_device(struct spi_device *spi)
> >  {
> >  	static DEFINE_MUTEX(spi_add_lock);
> > -	struct device *dev = spi->master->dev.parent;
> > +	struct spi_master *master = spi->master;
> > +	struct device *dev = master->dev.parent;
> >  	struct device *d;
> >  	int status;
> >  
> >  	/* Chipselects are numbered 0..max; validate. */
> > -	if (spi->chip_select >= spi->master->num_chipselect) {
> > +	if (spi->chip_select >= master->num_chipselect) {
> >  		dev_err(dev, "cs%d >= max %d\n",
> >  			spi->chip_select,
> > -			spi->master->num_chipselect);
> > +			master->num_chipselect);
> >  		return -EINVAL;
> >  	}
> >  
> > @@ -371,6 +374,9 @@ int spi_add_device(struct spi_device *spi)
> >  		goto done;
> >  	}
> >  
> > +	if (master->cs_gpios)
> > +		spi->cs_gpio = master->cs_gpios[spi->chip_select];
> > +
> 
> I still don't understand the need for this.  Only the master driver will need
> this data, and it is already stored in the master->cs_gpios array.  Why
> does it need to get duplicated into the spi_device?
yeah can drop it
> 
> >  	/* Drivers may modify this initial i/o setup, but will
> >  	 * normally rely on the device being setup.  Devices
> >  	 * using SPI_CS_HIGH can't coexist well otherwise...
> > @@ -561,6 +567,45 @@ struct spi_master *spi_alloc_master(struct device *dev, unsigned size)
> >  }
> >  EXPORT_SYMBOL_GPL(spi_alloc_master);
> >  
> > +#ifdef CONFIG_OF
> > +static int of_spi_register_master(struct spi_master *master)
> > +{
> > +	int nb, i;
> > +	int *cs;
> > +	struct device_node *np = master->dev.of_node;
> > +
> > +	if (!np)
> > +		return 0;
> > +
> > +	nb = of_gpio_named_count(np, "cs-gpios");
> > +
> > +	if (nb < 1)
> > +		return 0;
> > +
> > +	cs = devm_kzalloc(&master->dev,
> > +			  sizeof(int) * (master->num_chipselect + nb),
> > +			  GFP_KERNEL);
> 
> sizeof(*cs)
> 
> > +	master->cs_gpios = cs;
> > +
> > +	if (!master->cs_gpios)
> > +		return -ENOMEM;
> > +
> > +	memset(cs, -EINVAL, master->num_chipselect);
> > +	master->num_chipselect += nb;
> 
> Looks buggy.  Should be:
> 	if (nb > master->num_chipselect)
> 		master->num_chipselect = nb;
> 
> However, this is actually quite risky.  Changing the size of
> num_chipselect without the driver knowing about it will most likely
> cause breakage in drivers.  Drivers may use it as an array index, and
> if it gets increased then there will be problems.  In fact, drivers
> are probably using spi->chip_select as an array or register index so I
> don't think it can be transparently extended to include gpios.
> 
> So, this function must change.  It cannot be called automatically
> from spi_register_master().  It needs to be a library function that spi bus
> drivers must call explicitly so they are prepared for a change in the
> num_chipselect value.
I'll prefer to let the spi framework manage it
> 
> Also, if we're doing this, then the gpio cs manipulation hook should be
> moved out of spi_bitbang and into the core spi_master.  There should
> also be a stock function for manipulating gpio chip selects. I don't want
> spi driver authors under the impression that they should open code the
> chip select manipulation.
yeah I was thinking about it too

how about we split it in two

num_hw_cs manage by the drivers

and

num_gpio_cs for cs gpio

and num_chipselect (hw + cs) will for internal use

the gpio cs will be after the hw cs.

and we move the gpio cs from spi_bitbang to spi_master

Best Regards,
J.

> > +	cs += master->num_chipselect;
> > +
> > +	for (i = 0; i < nb; i++)
> > +		cs[i] = of_get_named_gpio(np, "cs-gpios", i);
> > +
> > +	return 0;
> > +}
> > +#else
> > +static int of_spi_register_master(struct spi_master *master)
> > +{
> > +	return 0;
> > +}
> > +#endif
> > +
> >  /**
> >   * spi_register_master - register SPI master controller
> >   * @master: initialized master, originally from spi_alloc_master()
> > @@ -592,6 +637,10 @@ int spi_register_master(struct spi_master *master)
> >  	if (!dev)
> >  		return -ENODEV;
> >  
> > +	status = of_spi_register_master(master);
> > +	if (status)
> > +		return status;
> > +
> >  	/* even if it's just one always-selected device, there must
> >  	 * be at least one chipselect
> >  	 */
> > diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> > index 176fce9..328d492 100644
> > --- a/include/linux/spi/spi.h
> > +++ b/include/linux/spi/spi.h
> > @@ -89,6 +89,7 @@ struct spi_device {
> >  	void			*controller_state;
> >  	void			*controller_data;
> >  	char			modalias[SPI_NAME_SIZE];
> > +	int			cs_gpio;	/* chip select gpio */
> >  
> >  	/*
> >  	 * likely need more hooks for more protocol options affecting how
> > @@ -318,6 +319,9 @@ struct spi_master {
> >  
> >  	/* called on release() to free memory provided by spi_master */
> >  	void			(*cleanup)(struct spi_device *spi);
> > +
> > +	/* gpio chip select */
> > +	int			*cs_gpios;
> >  };
> >  
> >  static inline void *spi_master_get_devdata(struct spi_master *master)
> > -- 
> > 1.7.7
> > 
> > _______________________________________________
> > devicetree-discuss mailing list
> > devicetree-discuss at lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/devicetree-discuss
> 
> -- 
> Grant Likely, B.Sc, P.Eng.
> Secret Lab Technologies,Ltd.


From thomas.abraham at linaro.org  Mon Mar 12 00:28:06 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 12 Mar 2012 09:58:06 +0530
Subject: [PATCH 5/5] mmc: sdhci-s3c: setup pins using pinctrl interface
In-Reply-To: <4F5D1843.1010608@samsung.com>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
 <4F5D1843.1010608@samsung.com>
Message-ID: <CAJuYYwToq0pHVQG2yuywe0Dxahy5vGbHjjpphtzQH6t9pp7LLQ@mail.gmail.com>

2012/3/12 Kukjin Kim <kgene.kim at samsung.com>:
> Thomas Abraham wrote:
>> The platform specific callback to setup the sdhci pin mux and pin config
>> is removed and the pinctrl subsystem interface is used to setup the
>> mux and config.
>>
>> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
>> ---
>> ? drivers/mmc/host/sdhci-s3c.c | ? 15 +++++++++++++--
>> ? 1 files changed, 13 insertions(+), 2 deletions(-)
>>
> [...]
>
>>
>> +#include<plat/map-s5p.h>
>> +#include<plat/map-base.h>
>
> You can add <mach/map.h> instead of above.
>
>> +
>> ? static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>> ? {
>> ? ? ? struct s3c_sdhci_platdata *pdata;
>> @@ -538,6 +543,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>> ? ? ? struct sdhci_s3c *sc;
>> ? ? ? struct resource *res;
>> ? ? ? int ret, irq, ptr, clks;
>> + ? ? char *pstate;
>>
>> ? ? ? if (!pdev->dev.platform_data&& ?!pdev->dev.of_node) {
>> ? ? ? ? ? ? ? dev_err(dev, "no device data specified\n");
>> @@ -643,8 +649,13 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>> ? ? ? }
>>
>> ? ? ? /* Ensure we have minimal gpio selected CMD/CLK/Detect */
>> - ? ? if (pdata->cfg_gpio)
>> - ? ? ? ? ? ? pdata->cfg_gpio(pdev, pdata->max_width);
>
> I'm not sure we can remove above now for all of Samsung stuff?

We the pin map table is fully populated for each SoC (and board as
necessary), then the platform callback functions to setup the pinmux
and pinconfig can be removed for the drivers. But before doing that,
the next step would be to add gpio interrupts and wakeup interrupts
support into the samsung pinctrl driver. When we have a fully
functional pinctrl driver, we could add the required bits in SoC and
board files and switch over to the pinctrl driver.

>
>> + ? ? pstate = pdata->max_width ? "sdhci-pcfg8" : "sdhci-pcfg4";
>
> Is this right? Current max_width can be 4 or 8 in each board file now.

Sorry, that is not correct. I will fix it. Thanks.

Regards,
Thomas.


From javier.martin at vista-silicon.com  Fri Mar  9 10:20:46 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:46 +0100
Subject: [PATCH v3 10/13] dmaengine: imx-dma: remove internal structure.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-11-git-send-email-javier.martin@vista-silicon.com>

This structure was created to allow an smoothless
merge but was meant to be removed. Remaining members
'hw_chaining' and 'watchdog' are moved to the channel
structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   64 +++++++++++++-----------------------------------
 1 files changed, 18 insertions(+), 46 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 84ac93b..0b831a7 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -110,29 +110,6 @@ enum  imxdma_prep_type {
 	IMXDMA_DESC_CYCLIC,
 };
 
-/*
- * struct imxdma_channel_internal - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- *            (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imxdma_channel_internal only as extension to it.
- */
-
-struct imxdma_channel_internal {
-	struct timer_list watchdog;
-
-	int hw_chaining;
-};
-
 struct imxdma_desc {
 	struct list_head		node;
 	struct dma_async_tx_descriptor	desc;
@@ -155,7 +132,8 @@ struct imxdma_desc {
 };
 
 struct imxdma_channel {
-	struct imxdma_channel_internal	internal;
+	int				hw_chaining;
+	struct timer_list		watchdog;
 	struct imxdma_engine		*imxdma;
 	unsigned int			channel;
 
@@ -215,10 +193,10 @@ static unsigned imx_dmav1_readl(unsigned offset)
 	return __raw_readl(imx_dmav1_baseaddr + offset);
 }
 
-static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
+static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 {
 	if (cpu_is_mx27())
-		return imxdma->hw_chaining;
+		return imxdmac->hw_chaining;
 	else
 		return 0;
 }
@@ -267,7 +245,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+			d->sg && imxdma_hw_chain(imxdmac)) {
 		d->sg = sg_next(d->sg);
 		if (d->sg) {
 			u32 tmp;
@@ -288,8 +266,8 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 
 	pr_debug("imxdma%d: imx_dma_disable\n", channel);
 
-	if (imxdma_hw_chain(&imxdmac->internal))
-		del_timer(&imxdmac->internal.watchdog);
+	if (imxdma_hw_chain(imxdmac))
+		del_timer(&imxdmac->watchdog);
 
 	local_irq_save(flags);
 	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
@@ -314,7 +292,6 @@ static void imxdma_watchdog(unsigned long data)
 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 {
 	struct imxdma_engine *imxdma = dev_id;
-	struct imxdma_channel_internal *internal;
 	unsigned int err_mask;
 	int i, disr;
 	int errcode;
@@ -334,7 +311,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (!(err_mask & (1 << i)))
 			continue;
-		internal = &imxdma->channel[i].internal;
 		errcode = 0;
 
 		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
@@ -368,7 +344,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 
 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
-	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
@@ -392,11 +367,11 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
-			if (imxdma_hw_chain(imxdma)) {
+			if (imxdma_hw_chain(imxdmac)) {
 				/* FIXME: The timeout should probably be
 				 * configurable
 				 */
-				mod_timer(&imxdma->watchdog,
+				mod_timer(&imxdmac->watchdog,
 					jiffies + msecs_to_jiffies(500));
 
 				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
@@ -415,8 +390,8 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 			return;
 		}
 
-		if (imxdma_hw_chain(imxdma)) {
-			del_timer(&imxdma->watchdog);
+		if (imxdma_hw_chain(imxdmac)) {
+			del_timer(&imxdmac->watchdog);
 			return;
 		}
 	}
@@ -430,7 +405,6 @@ out:
 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 {
 	struct imxdma_engine *imxdma = dev_id;
-	struct imxdma_channel_internal *internal;
 	int i, disr;
 
 	if (cpu_is_mx21() || cpu_is_mx27())
@@ -443,10 +417,8 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 
 	imx_dmav1_writel(disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (disr & (1 << i)) {
-			internal = &imxdma->channel[i].internal;
+		if (disr & (1 << i))
 			dma_irq_handle_channel(&imxdma->channel[i]);
-		}
 	}
 
 	return IRQ_HANDLED;
@@ -589,8 +561,8 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			break;
 		}
 
-		imxdmac->internal.hw_chaining = 1;
-		if (!imxdma_hw_chain(&imxdmac->internal))
+		imxdmac->hw_chaining = 1;
+		if (!imxdma_hw_chain(imxdmac))
 			return -EINVAL;
 		imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
 			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
@@ -942,7 +914,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	/* Initialize channel parameters */
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-		memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+
 		if (cpu_is_mx21() || cpu_is_mx27()) {
 			ret = request_irq(MX2x_INT_DMACH0 + i,
 					dma_irq_handler, 0, "DMA", imxdma);
@@ -951,9 +923,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
 						MX2x_INT_DMACH0 + i, i);
 				goto err_init;
 			}
-			init_timer(&imxdmac->internal.watchdog);
-			imxdmac->internal.watchdog.function = &imxdma_watchdog;
-			imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
+			init_timer(&imxdmac->watchdog);
+			imxdmac->watchdog.function = &imxdma_watchdog;
+			imxdmac->watchdog.data = (unsigned long)imxdmac;
 		}
 
 		imxdmac->imxdma = imxdma;
-- 
1.7.0.4



From kgene.kim at samsung.com  Sat Mar 10 11:08:17 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 08:08:17 -0800
Subject: [GIT PULL 1/4] Samsung devel for v3.4
Message-ID: <4F5B7C71.2090303@samsung.com>

Hi Arnd, Olof,

This is various develop regarding Samsung stuff for v3.4.
Please pull following:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/devel-samsung

I think, you can pull this cleanly without any conflicts.
If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

   Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/devel-samsung

Amit Daniel Kachhap (5):
       ARM: EXYNOS: Add support AFTR mode on EXYNOS4210
       ARM: S5P: add L2 early resume code
       ARM: EXYNOS: save L2 settings during bootup
       ARM: EXYNOS: remove useless code to save/restore L2
       ARM: EXYNOS: Enable l2 configuration through device tree

Andrzej Pietrasiewicz (1):
       ARM: EXYNOS: add support JPEG

Changhwan Youn (1):
       ARM: EXYNOS: fix cycle count for periodic mode of clock event timers

Jingoo Han (1):
       ARM: SAMSUNG: Add a callback 'notify_after' for PWM backlight control

Joonyoung Shim (2):
       ARM: S3C64XX: Add usb otg phy control
       ARM: S5PV210: Add usb otg phy control

Kamil Debski (1):
       ARM: SAMSUNG: add G2D to plat-s5p and mach-exynos

Mark Brown (4):
       ARM: S3C64XX: Add basic cpuidle driver
       ARM: S3C64XX: Gate some more clocks by default
       ARM: S3C64XX: Reduce residency requirement for cpuidle WFI mode
       ARM: S3C64XX: Define some additional always off clocks

Minho Ban (1):
       ARM: SAMSUNG: use spin_lock_irqsave() in clk_{enable,disable}

MyungJoo Ham (1):
       ARM: EXYNOS: Add DMC1, allow PPMU access for DMC

Sylwester Nawrocki (1):
       ARM: SAMSUNG: Correct MIPI-CSIS io memory resource definition

Tushar Behera (2):
       ARM: SAMSUNG: Add __init attribute to samsung_bl_set()
       ARM: SAMSUNG: fix __init attribute on regarding s3c_set_platdata()

  arch/arm/mach-exynos/clock.c                       |    5 +
  arch/arm/mach-exynos/common.c                      |   60 ++++++--
  arch/arm/mach-exynos/cpuidle.c                     |  151 
+++++++++++++++++++-
  arch/arm/mach-exynos/include/mach/map.h            |    7 +
  arch/arm/mach-exynos/include/mach/pmu.h            |    2 +
  arch/arm/mach-exynos/mct.c                         |   21 ++-
  arch/arm/mach-exynos/pm.c                          |   15 --
  arch/arm/mach-s3c64xx/Kconfig                      |    8 +
  arch/arm/mach-s3c64xx/Makefile                     |    2 +
  arch/arm/mach-s3c64xx/clock.c                      |  121 ++++++++++++++--
  arch/arm/mach-s3c64xx/cpuidle.c                    |   91 ++++++++++++
  arch/arm/mach-s3c64xx/mach-crag6410.c              |    4 +
  arch/arm/mach-s3c64xx/mach-smartq.c                |    3 +
  arch/arm/mach-s3c64xx/mach-smdk6410.c              |    4 +
  arch/arm/mach-s3c64xx/setup-usb-phy.c              |   90 ++++++++++++
  arch/arm/mach-s5pv210/Kconfig                      |    6 +
  arch/arm/mach-s5pv210/Makefile                     |    1 +
  arch/arm/mach-s5pv210/include/mach/regs-sys.h      |    4 -
  arch/arm/mach-s5pv210/setup-usb-phy.c              |   90 ++++++++++++
  arch/arm/plat-s5p/Kconfig                          |   10 ++
  arch/arm/plat-s5p/sleep.S                          |   44 +++++-
  arch/arm/plat-samsung/clock.c                      |   12 +-
  arch/arm/plat-samsung/dev-backlight.c              |    4 +-
  arch/arm/plat-samsung/devs.c                       |   68 ++++++++-
  arch/arm/plat-samsung/include/plat/devs.h          |    2 +
  .../plat-samsung/include/plat/regs-usb-hsotg-phy.h |    7 +-
  arch/arm/plat-samsung/include/plat/udc-hs.h        |    5 +
  27 files changed, 765 insertions(+), 72 deletions(-)
  create mode 100644 arch/arm/mach-s3c64xx/cpuidle.c
  create mode 100644 arch/arm/mach-s3c64xx/setup-usb-phy.c
  create mode 100644 arch/arm/mach-s5pv210/setup-usb-phy.c


From kgene.kim at samsung.com  Sun Mar 11 04:47:20 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 00:47:20 -0800
Subject: [GIT PULL 1/4] Samsung devel for v3.4
In-Reply-To: <CAOesGMgec=KVBQJjVs3p3B2GGj9q9mwC2XCdxLNvvJL61u+f8g@mail.gmail.com>
References: <4F5B7C71.2090303@samsung.com>
 <CAOesGMgec=KVBQJjVs3p3B2GGj9q9mwC2XCdxLNvvJL61u+f8g@mail.gmail.com>
Message-ID: <4F5C6698.2030904@samsung.com>

On 03/10/12 10:20, Olof Johansson wrote:
> On Sat, Mar 10, 2012 at 8:08 AM, Kukjin Kim<kgene.kim at samsung.com>  wrote:
>> Hi Arnd, Olof,
>>
>> This is various develop regarding Samsung stuff for v3.4.
>> Please pull following:
>>   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> next/devel-samsung
>>
>> I think, you can pull this cleanly without any conflicts.
>> If any problems, please kindly let me know.
>
>
> Thanks, pulled into next/soc.
>
Olof, thanks.

And as a note, will happen merge conflict between this and 
cleanup-exynos-clock. Here is resolution.

diff --git a/arch/arm/mach-exynos/clock-exynos4.c 
b/arch/arm/mach-exynos/clock-exynos4.c
index 31b59e6..060dde7 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -471,6 +471,11 @@ static struct clk exynos4_init_clocks_off[] = {
  		.enable		= exynos4_clk_ip_cam_ctrl,
  		.ctrlbit	= (1 << 5),
  	}, {
+		.name		= "jpeg",
+		.id		= 0,
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
  		.name		= "fimc",
  		.devname	= "exynos4-fimc.0",
  		.enable		= exynos4_clk_ip_cam_ctrl,


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Sat Mar 10 11:09:11 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 08:09:11 -0800
Subject: [GIT PULL 4/4] Samsung devel-dma for v3.4
Message-ID: <4F5B7CA7.2010604@samsung.com>

Hi Arnd, Olof,

This is for Samsung dma stuff for v3.4 and depends on following:
   next/cleanup-use-static
   next/cleanup-exynos-clock

Please pull from:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/devel-samsung-dma

And conflicts will be happened in clock part. Here is my preferred 
resolution. The mach-exynos/clock.c can be removed with following:

arch/arm/mach-exynos/exynos-clock4.c

[...]

+ 		.ctrlbit	= (1 << 0),
+ 	}, {
+ 		.name		= "hsmmc",
  -		.devname	= "s3c-sdhci.0",
++		.devname	= "exynos4-sdhci.0",
+ 		.parent		= &exynos4_clk_aclk_133.clk,
+ 		.enable		= exynos4_clk_ip_fsys_ctrl,
+ 		.ctrlbit	= (1 << 5),
+ 	}, {
+ 		.name		= "hsmmc",
  -		.devname	= "s3c-sdhci.1",
++		.devname	= "exynos4-sdhci.1",
+ 		.parent		= &exynos4_clk_aclk_133.clk,
+ 		.enable		= exynos4_clk_ip_fsys_ctrl,
+ 		.ctrlbit	= (1 << 6),
+ 	}, {
+ 		.name		= "hsmmc",
  -		.devname	= "s3c-sdhci.2",
++		.devname	= "exynos4-sdhci.2",
+ 		.parent		= &exynos4_clk_aclk_133.clk,
+ 		.enable		= exynos4_clk_ip_fsys_ctrl,
+ 		.ctrlbit	= (1 << 7),
+ 	}, {
+ 		.name		= "hsmmc",
  -		.devname	= "s3c-sdhci.3",
++		.devname	= "exynos4-sdhci.3",
+ 		.parent		= &exynos4_clk_aclk_133.clk,
+ 		.enable		= exynos4_clk_ip_fsys_ctrl,
+ 		.ctrlbit	= (1 << 8),

[...]

+ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
+ 	.clk	= {
+ 		.name		= "sclk_mmc",
  -		.devname	= "s3c-sdhci.0",
++		.devname	= "exynos4-sdhci.0",
+ 		.parent		= &exynos4_clk_dout_mmc0.clk,
+ 		.enable		= exynos4_clksrc_mask_fsys_ctrl,
+ 		.ctrlbit	= (1 << 0),
[...]
+ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
+ 	.clk	= {
+ 		.name		= "sclk_mmc",
  -		.devname	= "s3c-sdhci.1",
++		.devname	= "exynos4-sdhci.1",
+ 		.parent		= &exynos4_clk_dout_mmc1.clk,
+ 		.enable		= exynos4_clksrc_mask_fsys_ctrl,
+ 		.ctrlbit	= (1 << 4),
[...]
+ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
+ 	.clk	= {
+ 		.name		= "sclk_mmc",
  -		.devname	= "s3c-sdhci.2",
++		.devname	= "exynos4-sdhci.2",
+ 		.parent		= &exynos4_clk_dout_mmc2.clk,
+ 		.enable		= exynos4_clksrc_mask_fsys_ctrl,
+ 		.ctrlbit	= (1 << 8),
[...]
+ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
+ 	.clk	= {
+ 		.name		= "sclk_mmc",
  -		.devname	= "s3c-sdhci.3",
++		.devname	= "exynos4-sdhci.3",
+ 		.parent		= &exynos4_clk_dout_mmc3.clk,
+ 		.enable		= exynos4_clksrc_mask_fsys_ctrl,
+ 		.ctrlbit	= (1 << 12),

[...]

+ static struct clk_lookup exynos4_clk_lookup[] = {
+ 	CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", 
&exynos4_clk_sclk_uart0.clk),
+ 	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", 
&exynos4_clk_sclk_uart1.clk),
+ 	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", 
&exynos4_clk_sclk_uart2.clk),
+ 	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", 
&exynos4_clk_sclk_uart3.clk),
  -	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
  -	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
  -	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
  -	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
++	CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", 
&exynos4_clk_sclk_mmc0.clk),
++	CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", 
&exynos4_clk_sclk_mmc1.clk),
++	CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", 
&exynos4_clk_sclk_mmc2.clk),
++	CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", 
&exynos4_clk_sclk_mmc3.clk),
+ 	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
+ 	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
+ 	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit e914c89254a8f943d8d06a0bda67769fd27bf9c6:

   Merge branch 'next/cleanup-exynos-clock' into next/devel-samsung-dma 
(2012-03-10 03:32:19 -0800)

are available in the git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/devel-samsung-dma

Boojin Kim (2):
       ARM: EXYNOS: Enable MDMA driver
       ARM: EXYNOS: add support DMA for EXYNOS4X12 SoC

Tushar Behera (1):
       ARM: EXYNOS: Add apb_pclk clkdev entry for mdma1

  arch/arm/mach-exynos/Kconfig                   |    3 +
  arch/arm/mach-exynos/clock-exynos4.c           |    9 ++
  arch/arm/mach-exynos/dma.c                     |  117 
++++++++++++++++++++++--
  arch/arm/mach-exynos/include/mach/irqs.h       |    2 +
  arch/arm/mach-exynos/include/mach/map.h        |    3 +-
  arch/arm/plat-samsung/include/plat/dma-pl330.h |   16 +++
  6 files changed, 141 insertions(+), 9 deletions(-)


From kgene.kim at samsung.com  Sun Mar 11 04:00:39 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 00:00:39 -0800
Subject: [GIT PULL] Samsung Cleanup EXYNOS clock for v3.4
In-Reply-To: <20120310173526.GB5972@quad.lixom.net>
References: <4F589474.8050609@samsung.com>
 <CAOesGMiWOChuMjLQTK1pGys+oXCc4A=HO-2_=37rh3M6pgUP_g@mail.gmail.com>
 <4F5A22AD.1070907@samsung.com> <4F5B74C1.3080200@samsung.com>
 <20120310173526.GB5972@quad.lixom.net>
Message-ID: <4F5C5BA7.8050904@samsung.com>

On 03/10/12 09:35, Olof Johansson wrote:

[...]

>
> The contents of the branch itself looks good, but now you have introduced
> a modified/delete conflict with yourself.
>
> You modify arch/arm/mach-exynos/clock.c in your cleanup-use-static branch, and
> then you move it here. That means that when I merge in this branch, git throws
> a conflict and I have to do manual edits to make the contents match.
>
> It's better if you base this branch on your cleanup-use-static branch, so that
> the move includes those edits. That way there is no conflict resolution to do
> at our end either.
>
> Can you please do that rebase and send a fresh pull request? I'll continue
> looking at your other requests meanwhile.
>
Hi Olof,

Sorry for late response. OK I see and your suggestion sounds good to me. 
Let me send a new pull request after that.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From thomas.abraham at linaro.org  Mon Mar 12 00:22:10 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 12 Mar 2012 09:52:10 +0530
Subject: [PATCH 3/5] ARM: Exynos4: Add pinctrl devices and pin maps
In-Reply-To: <4F5D1661.4090007@samsung.com>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <1331469965-28846-4-git-send-email-thomas.abraham@linaro.org>
 <4F5D1661.4090007@samsung.com>
Message-ID: <CAJuYYwQPrOte4EjpfBbUW0vg+qFJwYgZcSM88iZ95C8LwWuptg@mail.gmail.com>

2012/3/12 Kukjin Kim <kgene.kim at samsung.com>:
> Thomas Abraham wrote:
>> Add the three pinctrl platform devices and the pin maps for Exynos4.
>>
>> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
>> ---
>> ? arch/arm/mach-exynos/Kconfig ? ? ? ? ? ? ?| ? ?1 +
>> ? arch/arm/mach-exynos/Makefile ? ? ? ? ? ? | ? ?1 +
>> ? arch/arm/mach-exynos/common.h ? ? ? ? ? ? | ? ?6 ++
>> ? arch/arm/mach-exynos/dev-pinctrl.c ? ? ? ?| ?115 +++++++++++++++++++++++++++++
>> ? arch/arm/plat-samsung/include/plat/devs.h | ? ?3 +
>> ? 5 files changed, 126 insertions(+), 0 deletions(-)
>> ? create mode 100644 arch/arm/mach-exynos/dev-pinctrl.c
>
> [...]
>
>> +#include<linux/kernel.h>
>> +#include<linux/dma-mapping.h>
>> +#include<linux/platform_device.h>
>> +#include<linux/interrupt.h>
>> +#include<linux/pinctrl/machine.h>
>
> #include <linux/ioport.h> for DEFINE_RES_xxx at below.
>
>> +
>> +#include<plat/devs.h>
>> +#include<plat/pinctrl.h>
>> +
>> +#include<mach/map.h>
>> +
>> +static struct resource exynos4_pinctrl_resource0[] = {
>> + ? ? [0] = {
>> + ? ? ? ? ? ? .start ?= EXYNOS4_PA_GPIO1,
>> + ? ? ? ? ? ? .end ? ?= EXYNOS4_PA_GPIO1 + SZ_4K - 1,
>> + ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
>> + ? ? },
>
> [0] = DEFINE_RES_MEM(EXYNOS4_PA_GPIO1, SZ_4K),
>
>> + ? ? [1] = {
>> + ? ? ? ? ? ? .start ?= IRQ_GPIO_XA,
>> + ? ? ? ? ? ? .end ? ?= IRQ_GPIO_XA,
>> + ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
>> + ? ? },
>
> [1] = DEFINE_RES_IRQ(IRQ_GPIO_XA),
>
> But I'm thinking, we need to move to use EXYNOS4_IRQ_GPIO_XA here for
> both EXYNOS4 and EXYNOS5 and as a note, I'm working on updating IRQ
> naming you can see it in this week :)

Thanks for reviewing this patch series. I will use DEFINE_RES_xxx for
resource instantiation.

Regards,
Thomas.

[...]


From kgene.kim at samsung.com  Sat Mar 10 05:37:51 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 02:37:51 -0800
Subject: [GIT PULL] Samsung Cleanup EXYNOS clock for v3.4
In-Reply-To: <4F5A22BB.2080808@samsung.com>
References: <22926872.16671331267895327.JavaMail.weblogic@epml04>
 <CAJ0PZbQebwvFrmXWn=-m7YH3Ri7t2fvm+E_EKZ45rD7cAyo2UA@mail.gmail.com>
 <4F5A22BB.2080808@samsung.com>
Message-ID: <4F5B2EFF.3020407@samsung.com>

On 03/09/12 07:33, Kukjin Kim wrote:
> On 03/08/12 23:06, MyungJoo Ham wrote:
>> 2012/3/9 ???<myungjoo.ham at samsung.com>:
> 
> [...]
> 
>>
>> Hello, Kgene
>>
>> I've rebased the branch that was pull-requested to Kgene based on this branch.
>>
> 
> OK, thanks. Let me apply this series on top of new cleanup-exynos-clock.
> 
Applied, thanks.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Sat Mar 10 05:19:06 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 02:19:06 -0800
Subject: [PATCH 2/5] ARM: EXYNOS: use static declaration on regarding clock
In-Reply-To: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>
References: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331374749-23256-3-git-send-email-kgene.kim@samsung.com>

This patch uses static declaration struct which is not
used in other file and re-arrange with group in header
file.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/clock-exynos4.c |   18 +++++++++---------
 arch/arm/mach-exynos/clock-exynos4.h |   13 +------------
 2 files changed, 10 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 1d6d64f..7dde81b 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -95,21 +95,21 @@ static struct sleep_save exynos4_clock_save[] = {
 };
 #endif
 
-struct clk clk_sclk_hdmi27m = {
+static struct clk clk_sclk_hdmi27m = {
 	.name		= "sclk_hdmi27m",
 	.rate		= 27000000,
 };
 
-struct clk clk_sclk_hdmiphy = {
+static struct clk clk_sclk_hdmiphy = {
 	.name		= "sclk_hdmiphy",
 };
 
-struct clk clk_sclk_usbphy0 = {
+static struct clk clk_sclk_usbphy0 = {
 	.name		= "sclk_usbphy0",
 	.rate		= 27000000,
 };
 
-struct clk clk_sclk_usbphy1 = {
+static struct clk clk_sclk_usbphy1 = {
 	.name		= "sclk_usbphy1",
 };
 
@@ -218,7 +218,7 @@ static struct clksrc_clk clk_mout_apll = {
 	.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 };
 
-struct clksrc_clk clk_sclk_apll = {
+static struct clksrc_clk clk_sclk_apll = {
 	.clk	= {
 		.name		= "sclk_apll",
 		.parent		= &clk_mout_apll.clk,
@@ -226,7 +226,7 @@ struct clksrc_clk clk_sclk_apll = {
 	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 };
 
-struct clksrc_clk clk_mout_epll = {
+static struct clksrc_clk clk_mout_epll = {
 	.clk	= {
 		.name		= "mout_epll",
 	},
@@ -310,7 +310,7 @@ static struct clksrc_clk clk_periphclk = {
 
 /* Core list of CMU_CORE side */
 
-struct clk *clkset_corebus_list[] = {
+static struct clk *clkset_corebus_list[] = {
 	[0] = &clk_mout_mpll.clk,
 	[1] = &clk_sclk_apll.clk,
 };
@@ -375,7 +375,7 @@ struct clk *clkset_aclk_top_list[] = {
 	[1] = &clk_sclk_apll.clk,
 };
 
-struct clksrc_sources clkset_aclk = {
+static struct clksrc_sources clkset_aclk = {
 	.sources	= clkset_aclk_top_list,
 	.nr_sources	= ARRAY_SIZE(clkset_aclk_top_list),
 };
@@ -446,7 +446,7 @@ static struct clksrc_sources clkset_sclk_vpll = {
 	.nr_sources	= ARRAY_SIZE(clkset_sclk_vpll_list),
 };
 
-struct clksrc_clk clk_sclk_vpll = {
+static struct clksrc_clk clk_sclk_vpll = {
 	.clk	= {
 		.name		= "sclk_vpll",
 	},
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
index f64e9f7..d2ef305 100644
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -15,25 +15,14 @@
 
 #include <linux/clk.h>
 
-extern struct clk clk_sclk_hdmi27m;
-extern struct clk clk_sclk_usbphy0;
-extern struct clk clk_sclk_usbphy1;
-extern struct clk clk_sclk_hdmiphy;
-
-extern struct clksrc_clk clk_sclk_apll;
 extern struct clksrc_clk clk_mout_mpll;
 extern struct clksrc_clk clk_aclk_133;
-extern struct clksrc_clk clk_mout_epll;
-extern struct clksrc_clk clk_sclk_vpll;
 
-extern struct clk *clkset_corebus_list[];
 extern struct clksrc_sources clkset_mout_corebus;
+extern struct clksrc_sources clkset_group;
 
 extern struct clk *clkset_aclk_top_list[];
-extern struct clksrc_sources clkset_aclk;
-
 extern struct clk *clkset_group_list[];
-extern struct clksrc_sources clkset_group;
 
 extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-- 
1.7.4.4



From plagnioj at jcrosoft.com  Fri Mar  9 05:09:32 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 9 Mar 2012 11:09:32 +0100
Subject: [PULL] of nand generic binding
In-Reply-To: <20120309014439.235C23E0901@localhost>
References: <20120217155707.GR1214@game.jcrosoft.org>
 <20120229152534.GH3318@game.jcrosoft.org>
 <20120307082945.GJ21255@game.jcrosoft.org>
 <4F576602.8020808@gmail.com> <20120309014439.235C23E0901@localhost>
Message-ID: <20120309100932.GO27213@game.jcrosoft.org>

On 18:44 Thu 08 Mar     , Grant Likely wrote:
> On Wed, 07 Mar 2012 07:43:30 -0600, Rob Herring <robherring2 at gmail.com> wrote:
> > On 03/07/2012 02:29 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > On 16:25 Wed 29 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> > >> On 16:57 Fri 17 Feb     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> > >>> HI,
> > >>>
> > >>> 	please find attached the generic binding for the MTD nand
> > >>>
> > >>> 	This will add boolean and nand helpers
> > >> is it ok?
> > > I need this for 3.4
> > > 
> > > will you apply it or can I apply it via AT91
> > 
> > Looks fine to me and Grant acked it, so go ahead and take with your at91
> > branch.
> 
> Actually, taking another look at the of_mtd patch, that stuff really
> belongs in the drivers/mtd directory.  I'm not nacking the patch, but
> you should send a follow up to move it into the correct place.
today of generic binding are all in drivers/of


> 
> I don't like the of_property_read_bool patch.  I don't want the
> of_property_read_ functions to mix data return and error codes.
> Either return a bool with an error code in the parameter list, or the
> other way around.  Otherwise we'll end up with the same problem as
> APIs that use the ERR_PTR() pattern where callers will use it without
> understanding that the return value isn't necessarily a bool.
I update as I reply

and can I've a go I've all the binding for at91 reallying on it

Best Regards,
J.


From javier.martin at vista-silicon.com  Fri Mar  9 10:20:42 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:42 +0100
Subject: [PATCH v3 06/13] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw'
 function.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-7-git-send-email-javier.martin@vista-silicon.com>

Removing this function allows moving 'ccr_to_device' and
'ccr_from_device' from internal struct to channel struct.
This repesents a step forward towards removing auxiliary
'internal' structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   98 +++++++++++++++++-------------------------------
 1 files changed, 35 insertions(+), 63 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index d86b3d5..e8b6efa 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -133,9 +133,6 @@ struct imxdma_channel_internal {
 
 	int in_use;
 
-	u32 ccr_from_device;
-	u32 ccr_to_device;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -180,6 +177,8 @@ struct imxdma_channel {
 	dma_cookie_t			last_completed;
 	int				dma_request;
 	struct scatterlist		*sg_list;
+	u32				ccr_from_device;
+	u32				ccr_to_device;
 };
 
 struct imxdma_engine {
@@ -311,58 +310,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	local_irq_restore(flags);
 }
 
-static int
-imxdma_setup_sg_hw(struct imxdma_desc *d,
-		 struct scatterlist *sg, unsigned int sgcount,
-		 unsigned int dma_length, unsigned int dev_addr,
-		 enum dma_transfer_direction direction)
-{
-	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
-	int channel = imxdmac->channel;
-
-	if (imxdmac->internal.in_use)
-		return -EBUSY;
-
-	imxdmac->internal.sg = sg;
-	imxdmac->internal.resbytes = dma_length;
-
-	if (!sg || !sgcount) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!sg->length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (direction == DMA_DEV_TO_MEM) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if (direction == DMA_MEM_TO_DEV) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imxdma_sg_next(d, sg);
-
-	return 0;
-}
-
 static void imxdma_watchdog(unsigned long data)
 {
 	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
@@ -524,7 +471,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
-	int ret;
 
 	/* Configure and enable */
 	switch (d->type) {
@@ -546,10 +492,37 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
-					 imxdmac->per_address, d->direction);
-		if (ret < 0)
-			return ret;
+		imxdmac->internal.sg = d->sg;
+		imxdmac->internal.resbytes = d->len;
+
+		if (d->direction == DMA_DEV_TO_MEM) {
+			imx_dmav1_writel(imxdmac->per_address,
+					 DMA_SAR(imxdmac->channel));
+			imx_dmav1_writel(imxdmac->ccr_from_device,
+					 DMA_CCR(imxdmac->channel));
+
+			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+				"total length=%d dev_addr=0x%08x (dev2mem)\n",
+				__func__, imxdmac->channel, d->sg, d->sgcount,
+				d->len, imxdmac->per_address);
+		} else if (d->direction == DMA_MEM_TO_DEV) {
+			imx_dmav1_writel(imxdmac->per_address,
+					 DMA_DAR(imxdmac->channel));
+			imx_dmav1_writel(imxdmac->ccr_to_device,
+					 DMA_CCR(imxdmac->channel));
+
+			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+				"total length=%d dev_addr=0x%08x (mem2dev)\n",
+				__func__, imxdmac->channel, d->sg, d->sgcount,
+				d->len, imxdmac->per_address);
+		} else {
+			dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
+				__func__, imxdmac->channel);
+			return -EINVAL;
+		}
+
+		imxdma_sg_next(d, d->sg);
+
 		break;
 	default:
 		return -EINVAL;
@@ -639,11 +612,10 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		imxdmac->internal.hw_chaining = 1;
 		if (!imxdma_hw_chain(&imxdmac->internal))
 			return -EINVAL;
-		imxdmac->internal.ccr_from_device =
-			(mode | IMX_DMA_TYPE_FIFO) |
+		imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
 			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
 			CCR_REN;
-		imxdmac->internal.ccr_to_device =
+		imxdmac->ccr_to_device =
 			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
 			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
 		imx_dmav1_writel(imxdmac->dma_request,
-- 
1.7.0.4



From thomas.abraham at linaro.org  Sun Mar 11 08:46:04 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sun, 11 Mar 2012 18:16:04 +0530
Subject: [PATCH 4/5] ARM: Exynos: Enable pinctrl driver support for Origen
 board
In-Reply-To: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1331469965-28846-5-git-send-email-thomas.abraham@linaro.org>

Add the pinctrl platform devices for static registration and add
default pin maps.

Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/mach-origen.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 02c242e..4e39a9b 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -21,6 +21,8 @@
 #include <linux/mfd/max8997.h>
 #include <linux/lcd.h>
 #include <linux/rfkill-gpio.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -41,6 +43,7 @@
 #include <plat/pd.h>
 #include <plat/fb.h>
 #include <plat/mfc.h>
+#include <plat/pinctrl.h>
 
 #include <mach/ohci.h>
 #include <mach/map.h>
@@ -622,6 +625,9 @@ static struct platform_device origen_device_bluetooth = {
 };
 
 static struct platform_device *origen_devices[] __initdata = {
+	&exynos4_pinctrl0,
+	&exynos4_pinctrl1,
+	&exynos4_pinctrl2,
 	&s3c_device_hsmmc2,
 	&s3c_device_hsmmc0,
 	&s3c_device_i2c0,
@@ -697,6 +703,7 @@ static void __init origen_reserve(void)
 
 static void __init origen_machine_init(void)
 {
+	exynos4210_pinctrl_register_def_mappings();
 	origen_power_init();
 
 	s3c_i2c0_set_platdata(NULL);
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sun Mar 11 08:46:02 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sun, 11 Mar 2012 18:16:02 +0530
Subject: [PATCH 2/5] pinctrl: add exynos4 specific pins, groups,
 functions and gpio chip data
In-Reply-To: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1331469965-28846-3-git-send-email-thomas.abraham@linaro.org>

Add Exynos4 specific information about pins, groups, functions and gpio
chip data that will be used as driver data by the Samsung pinctrl driver.

Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 drivers/pinctrl/Kconfig           |    7 +
 drivers/pinctrl/Makefile          |    1 +
 drivers/pinctrl/pinctrl-exynos4.c |  522 +++++++++++++++++++++++++++++++++++++
 3 files changed, 530 insertions(+), 0 deletions(-)
 create mode 100644 drivers/pinctrl/pinctrl-exynos4.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index a068d16..b798a52 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -82,6 +82,13 @@ config PINCTRL_COH901
 config PINCTRL_SAMSUNG
 	bool "Samsung pinctrl driver"
 
+config PINCTRL_EXYNOS4
+	bool "Pinctrl driver data for Exynos4 SoC"
+	depends on ARCH_EXYNOS4
+	select PINCTRL_SAMSUNG
+	select PINMUX
+	select PINCONF
+
 endmenu
 
 endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index eaccc1b..79b6cda 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o
+obj-$(CONFIG_PINCTRL_EXYNOS4)	+= pinctrl-exynos4.o
diff --git a/drivers/pinctrl/pinctrl-exynos4.c b/drivers/pinctrl/pinctrl-exynos4.c
new file mode 100644
index 0000000..5eb6168
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-exynos4.c
@@ -0,0 +1,522 @@
+/*
+ * Exynos4 specific driver data for Samsung pinctrl and gpiolib driver.
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2011 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * This file contains the Exynos4 specific driver data for the Samsung
+ * pinctrl/gpiolib interface drivers.
+ *
+ * ToDo: Add additional pin functions and pin groups available on Exynos4210.
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/gpio.h>
+
+#include <plat/pinctrl.h>
+
+#include "pinctrl-samsung.h"
+
+/* Exynos4210 Pin-Controller 0 pin list */
+static unsigned int exynos4210_i2c2_pins[] = {
+	EXYNOS4_GPA0(6), EXYNOS4_GPA0(7),
+};
+
+static unsigned int exynos4210_i2c3_pins[] = {
+	EXYNOS4_GPA1(2), EXYNOS4_GPA1(3),
+};
+
+static unsigned int exynos4210_spi0_pins[] = {
+	EXYNOS4_GPB(0), EXYNOS4_GPB(1), EXYNOS4_GPB(2), EXYNOS4_GPB(3),
+};
+
+static unsigned int exynos4210_i2c4_pins[] = {
+	EXYNOS4_GPB(2), EXYNOS4_GPB(3),
+};
+
+static unsigned int exynos4210_spi1_pins[] = {
+	EXYNOS4_GPB(4), EXYNOS4_GPB(5), EXYNOS4_GPB(6), EXYNOS4_GPB(7),
+};
+
+static unsigned int exynos4210_i2c5_pins[] = {
+	EXYNOS4_GPB(6), EXYNOS4_GPB(7),
+};
+
+static unsigned int exynos4210_i2s1_pcm1_ac97_pins[] = {
+	EXYNOS4_GPC0(0), EXYNOS4_GPC0(1), EXYNOS4_GPC0(2), EXYNOS4_GPC0(3),
+	EXYNOS4_GPC0(4),
+};
+
+static unsigned int exynos4210_i2s2_pcm2_pins[] = {
+	EXYNOS4_GPC1(0), EXYNOS4_GPC1(1), EXYNOS4_GPC1(2), EXYNOS4_GPC1(3),
+	EXYNOS4_GPC1(4),
+};
+
+static unsigned int exynos4210_spdif_pins[] = {
+	EXYNOS4_GPC1(0), EXYNOS4_GPC1(1),
+};
+
+static unsigned int exynos4210_spi2_pins[] = {
+	EXYNOS4_GPC1(1), EXYNOS4_GPC1(2), EXYNOS4_GPC1(3), EXYNOS4_GPC1(4),
+};
+
+static unsigned int exynos4210_i2c6_pins[] = {
+	EXYNOS4_GPC1(3), EXYNOS4_GPC1(4),
+};
+
+static unsigned int exynos4210_i2c7_pins[] = {
+	EXYNOS4_GPD0(2), EXYNOS4_GPD0(3),
+};
+
+static unsigned int exynos4210_i2c0_pins[] = {
+	EXYNOS4_GPD1(0), EXYNOS4_GPD1(1),
+};
+
+static unsigned int exynos4210_cam_b_pins[] = {
+	EXYNOS4_GPE0(0), EXYNOS4_GPE0(1), EXYNOS4_GPE0(2), EXYNOS4_GPE0(3),
+	EXYNOS4_GPE0(4), EXYNOS4_GPE1(0), EXYNOS4_GPE1(1), EXYNOS4_GPE1(2),
+	EXYNOS4_GPE1(3), EXYNOS4_GPE1(4), EXYNOS4_GPE1(5), EXYNOS4_GPE1(6),
+	EXYNOS4_GPE1(7),
+};
+
+static unsigned int exynos4210_lcd_pins[] = {
+	EXYNOS4_GPF0(0), EXYNOS4_GPF0(1), EXYNOS4_GPF0(2), EXYNOS4_GPF0(3),
+	EXYNOS4_GPF0(4), EXYNOS4_GPF0(5), EXYNOS4_GPF0(6), EXYNOS4_GPF0(7),
+	EXYNOS4_GPF1(0), EXYNOS4_GPF1(1), EXYNOS4_GPF1(2), EXYNOS4_GPF1(3),
+	EXYNOS4_GPF1(4), EXYNOS4_GPF1(5), EXYNOS4_GPF1(6), EXYNOS4_GPF1(7),
+	EXYNOS4_GPF2(0), EXYNOS4_GPF2(1), EXYNOS4_GPF2(2), EXYNOS4_GPF2(3),
+	EXYNOS4_GPF2(4), EXYNOS4_GPF2(5), EXYNOS4_GPF2(6), EXYNOS4_GPF2(7),
+	EXYNOS4_GPF3(0), EXYNOS4_GPF3(1), EXYNOS4_GPF3(2), EXYNOS4_GPF3(3),
+};
+
+/* Exynos4210 Pin-Controller 1 pin list */
+static unsigned int exynos4210_cam_a_pins[] = {
+	EXYNOS4_GPJ0(0), EXYNOS4_GPJ0(1), EXYNOS4_GPJ0(2), EXYNOS4_GPJ0(3),
+	EXYNOS4_GPJ0(4), EXYNOS4_GPJ0(5), EXYNOS4_GPJ0(6), EXYNOS4_GPJ0(7),
+	EXYNOS4_GPJ1(0), EXYNOS4_GPJ1(1), EXYNOS4_GPJ1(2), EXYNOS4_GPJ1(3),
+	EXYNOS4_GPJ1(4),
+};
+
+static unsigned int exynos4210_sdhci0_4_ctrl_pins[] = {
+	EXYNOS4_GPK0(0), EXYNOS4_GPK0(1)
+};
+
+static unsigned int exynos4210_sdhci0_4_cd_pins[] = {
+	EXYNOS4_GPK0(2)
+};
+
+static unsigned int exynos4210_sdhci0_4_4bit_pins[] = {
+	EXYNOS4_GPK0(3), EXYNOS4_GPK0(4), EXYNOS4_GPK0(5), EXYNOS4_GPK0(6)
+};
+
+static unsigned int exynos4210_sdhci0_4_8bit_pins[] = {
+	EXYNOS4_GPK1(3), EXYNOS4_GPK1(4), EXYNOS4_GPK1(5), EXYNOS4_GPK1(6)
+};
+
+static unsigned int exynos4210_sdhci1_ctrl_pins[] = {
+	EXYNOS4_GPK1(0), EXYNOS4_GPK1(1)
+};
+
+static unsigned int exynos4210_sdhci1_cd_pins[] = {
+	EXYNOS4_GPK1(2)
+};
+
+static unsigned int exynos4210_sdhci1_4bit_pins[] = {
+	EXYNOS4_GPK1(3), EXYNOS4_GPK1(4), EXYNOS4_GPK1(5), EXYNOS4_GPK1(6)
+};
+
+static unsigned int exynos4210_sdhci2_ctrl_pins[] = {
+	EXYNOS4_GPK2(0), EXYNOS4_GPK2(1)
+};
+
+static unsigned int exynos4210_sdhci2_cd_pins[] = {
+	EXYNOS4_GPK2(2)
+};
+
+static unsigned int exynos4210_sdhci2_4bit_pins[] = {
+	EXYNOS4_GPK2(3), EXYNOS4_GPK2(4), EXYNOS4_GPK2(5), EXYNOS4_GPK2(6)
+};
+
+static unsigned int exynos4210_sdhci2_8bit_pins[] = {
+	EXYNOS4_GPK3(3), EXYNOS4_GPK3(4), EXYNOS4_GPK3(5), EXYNOS4_GPK3(6)
+};
+
+static unsigned int exynos4210_sdhci3_ctrl_pins[] = {
+	EXYNOS4_GPK3(0), EXYNOS4_GPK3(1)
+};
+
+static unsigned int exynos4210_sdhci3_cd_pins[] = {
+	EXYNOS4_GPK3(2)
+};
+
+static unsigned int exynos4210_sdhci3_4bit_pins[] = {
+	EXYNOS4_GPK3(3), EXYNOS4_GPK3(4), EXYNOS4_GPK3(5), EXYNOS4_GPK3(6)
+};
+
+/* Exynos4210 Pin-Controller 2 pin list */
+static unsigned int exynos4210_i2s0_pins[] = {
+	EXYNOS4_GPZ(0), EXYNOS4_GPZ(1), EXYNOS4_GPZ(2), EXYNOS4_GPZ(3),
+	EXYNOS4_GPZ(4), EXYNOS4_GPZ(5), EXYNOS4_GPZ(6), EXYNOS4_GPZ(7)
+};
+
+static unsigned int exynos4210_pcm0_pins[] = {
+	EXYNOS4_GPZ(0), EXYNOS4_GPZ(1), EXYNOS4_GPZ(2), EXYNOS4_GPZ(3),
+	EXYNOS4_GPZ(4), EXYNOS4_GPZ(5),
+};
+
+/*
+ * list of pin groups available for pin-controller[0] of Exynos4210.
+ */
+static const struct samsung_pin_group exynos4210_pin_groups0[] = {
+	PIN_GROUP("i2c2_grp", exynos4210_i2c2_pins, 3),
+	PIN_GROUP("i2c3_grp", exynos4210_i2c3_pins, 3),
+	PIN_GROUP("spi0_grp", exynos4210_spi0_pins, 2),
+	PIN_GROUP("i2c4_grp", exynos4210_i2c4_pins, 3),
+	PIN_GROUP("spi1_grp", exynos4210_spi1_pins, 2),
+	PIN_GROUP("i2c5_grp", exynos4210_i2c5_pins, 3),
+	PIN_GROUP("i2s1_grp", exynos4210_i2s1_pcm1_ac97_pins, 2),
+	PIN_GROUP("pcm1_grp", exynos4210_i2s1_pcm1_ac97_pins, 3),
+	PIN_GROUP("ac97_grp", exynos4210_i2s1_pcm1_ac97_pins, 4),
+	PIN_GROUP("i2s2_grp", exynos4210_i2s2_pcm2_pins, 2),
+	PIN_GROUP("pcm2_grp", exynos4210_i2s2_pcm2_pins, 3),
+	PIN_GROUP("spdif_grp", exynos4210_spdif_pins, 4),
+	PIN_GROUP("spi2_grp", exynos4210_spi2_pins, 5),
+	PIN_GROUP("i2c6_grp", exynos4210_i2c6_pins, 4),
+	PIN_GROUP("i2c7_grp", exynos4210_i2c7_pins, 3),
+	PIN_GROUP("i2c0_grp", exynos4210_i2c0_pins, 2),
+	PIN_GROUP("camb_grp", exynos4210_cam_b_pins, 3),
+	PIN_GROUP("lcd_grp", exynos4210_lcd_pins, 2),
+};
+
+/*
+ * list of pin groups available for pin-controller[1] of Exynos4210.
+ */
+static const struct samsung_pin_group exynos4210_pin_groups1[] = {
+	PIN_GROUP("cama_grp", exynos4210_cam_a_pins, 2),
+	PIN_GROUP("sdhci0_ctrl_grp", exynos4210_sdhci0_4_ctrl_pins, 2),
+	PIN_GROUP("sdhci0_cd_grp", exynos4210_sdhci0_4_cd_pins, 2),
+	PIN_GROUP("sdhci0_4bit_grp", exynos4210_sdhci0_4_4bit_pins, 2),
+	PIN_GROUP("sdhci0_8bit_grp", exynos4210_sdhci0_4_8bit_pins, 3),
+	PIN_GROUP("sdhci1_ctrl_grp", exynos4210_sdhci1_ctrl_pins, 2),
+	PIN_GROUP("sdhci1_cd_grp", exynos4210_sdhci1_cd_pins, 2),
+	PIN_GROUP("sdhci1_4bit_grp", exynos4210_sdhci1_4bit_pins, 2),
+	PIN_GROUP("sdhci2_ctrl_grp", exynos4210_sdhci2_ctrl_pins, 2),
+	PIN_GROUP("sdhci2_cd_grp", exynos4210_sdhci2_cd_pins, 2),
+	PIN_GROUP("sdhci2_4bit_grp", exynos4210_sdhci2_4bit_pins, 2),
+	PIN_GROUP("sdhci2_8bit_grp", exynos4210_sdhci2_8bit_pins, 3),
+	PIN_GROUP("sdhci3_ctrl_grp", exynos4210_sdhci3_ctrl_pins, 2),
+	PIN_GROUP("sdhci3_cd_grp", exynos4210_sdhci3_cd_pins, 2),
+	PIN_GROUP("sdhci3_4bit_grp", exynos4210_sdhci3_4bit_pins, 2),
+	PIN_GROUP("sdhci4_ctrl_grp", exynos4210_sdhci0_4_ctrl_pins, 3),
+	PIN_GROUP("sdhci4_cd_grp", exynos4210_sdhci0_4_cd_pins, 3),
+	PIN_GROUP("sdhci4_4bit_grp", exynos4210_sdhci0_4_4bit_pins, 3),
+	PIN_GROUP("sdhci4_8bit_grp", exynos4210_sdhci0_4_8bit_pins, 4),
+};
+
+/*
+ * list of pin groups available for pin-controller[2] of Exynos4210.
+ */
+static const struct samsung_pin_group exynos4210_pin_groups2[] = {
+	PIN_GROUP("i2s0_grp", exynos4210_i2s0_pins, 2),
+	PIN_GROUP("pcm0_grp", exynos4210_pcm0_pins, 3),
+};
+
+/*
+ * list of group names which are included per pin-function of Exynos4210
+ * pin controller 0
+ */
+static const char * const i2c2_groups[] = { "i2c2_grp" };
+static const char * const i2c3_groups[] = { "i2c3_grp" };
+static const char * const spi0_groups[] = { "spi0_grp" };
+static const char * const i2c4_groups[] = { "i2c4_grp" };
+static const char * const spi1_groups[] = { "spi1_grp" };
+static const char * const i2c5_groups[] = { "i2c5_grp" };
+static const char * const i2s1_groups[] = { "i2s1_grp" };
+static const char * const pcm1_groups[] = { "pcm1_grp" };
+static const char * const ac97_groups[] = { "ac97_grp" };
+static const char * const i2s2_groups[] = { "i2s2_grp" };
+static const char * const pcm2_groups[] = { "pcm2_grp" };
+static const char * const spdif_groups[] = { "spdif_grp" };
+static const char * const spi2_groups[] = { "spi2_grp" };
+static const char * const i2c6_groups[] = { "i2c6_grp" };
+static const char * const i2c7_groups[] = { "i2c7_grp" };
+static const char * const i2c0_groups[] = { "i2c0_grp" };
+static const char * const camb_groups[] = { "camb_grp" };
+static const char * const lcd_groups[] = { "lcd_grp" };
+
+/*
+ * list of group names which are included per pin-function of Exynos4210
+ * pin controller 1
+ */
+static const char * const cama_groups[] = { "cama_grp" };
+static const char * const sdhci0_groups[] = { "sdhci0_ctrl_grp",
+		"sdhci0_cd_grp", "sdhci0_4bit_grp", "sdhci0_8bit_grp" };
+static const char * const sdhci1_groups[] = { "sdhci1_ctrl_grp",
+		"sdhci1_cd_grp", "sdhci1_4bit_grp" };
+static const char * const sdhci2_groups[] = { "sdhci2_ctrl_grp",
+		"sdhci2_cd_grp", "sdhci2_4bit_grp", "sdhci2_8bit_grp" };
+static const char * const sdhci3_groups[] = { "sdhci3_ctrl_grp",
+		"sdhci3_cd_grp", "sdhci3_4bit_grp" };
+static const char * const sdhci4_groups[] = { "sdhci4_ctrl_grp",
+		"sdhci4_cd_grp", "sdhci4_4bit_grp", "sdhci4_8bit_grp" };
+
+/*
+ * list of group names which are included per pin-function of Exynos4210
+ * pin controller 2
+ */
+static const char * const i2s0_groups[] = { "i2s0_grp" };
+static const char * const pcm0_groups[] = { "pcm0_grp" };
+
+/*
+ * list of function names supported by the pinmux controller 0 of exynos4210.
+ */
+static const struct samsung_pmx_func exynos4210_pmx_functions0[] = {
+	PMX_FUNC("i2c2-mux", i2c2_groups),
+	PMX_FUNC("i2c3-mux", i2c3_groups),
+	PMX_FUNC("spi0-mux", i2c3_groups),
+	PMX_FUNC("spi0-mux", i2c3_groups),
+	PMX_FUNC("i2c4-mux", i2c4_groups),
+	PMX_FUNC("spi1-mux", spi1_groups),
+	PMX_FUNC("i2c5-mux", i2c5_groups),
+	PMX_FUNC("i2s1-mux", i2s1_groups),
+	PMX_FUNC("pcm1-mux", pcm1_groups),
+	PMX_FUNC("ac97-mux", ac97_groups),
+	PMX_FUNC("i2s2-mux", i2s2_groups),
+	PMX_FUNC("pcm2-mux", pcm2_groups),
+	PMX_FUNC("spdif-mux", spdif_groups),
+	PMX_FUNC("spi2-mux", spi2_groups),
+	PMX_FUNC("i2c6-mux", i2c6_groups),
+	PMX_FUNC("i2c7-mux", i2c7_groups),
+	PMX_FUNC("i2c0-mux", i2c0_groups),
+	PMX_FUNC("camb-mux", camb_groups),
+	PMX_FUNC("lcd-mux", lcd_groups),
+};
+
+/*
+ * list of function names supported by the pinmux controller 1 of exynos4210.
+ */
+static const struct samsung_pmx_func exynos4210_pmx_functions1[] = {
+	PMX_FUNC("cama-mux", cama_groups),
+	PMX_FUNC("sdhci0-mux", sdhci0_groups),
+	PMX_FUNC("sdhci1-mux", sdhci1_groups),
+	PMX_FUNC("sdhci2-mux", sdhci2_groups),
+	PMX_FUNC("sdhci3-mux", sdhci3_groups),
+	PMX_FUNC("sdhci4-mux", sdhci4_groups),
+};
+
+/*
+ * list of function names supported by the pinmux controller 1 of exynos4210.
+ */
+static const struct samsung_pmx_func exynos4210_pmx_functions2[] = {
+	PMX_FUNC("i2s0-mux", i2s0_groups),
+	PMX_FUNC("pcm0-mux", pcm0_groups),
+};
+
+#define EXYNOS4_PIN_BANK(offset, __gpio, id)		\
+	{						\
+		.reg_offset	= offset,		\
+		.pin_base	= (__gpio##_START),	\
+		.nr_pins	= (__gpio##_NR),	\
+		.func_width	= 4,			\
+		.pud_width	= 2,			\
+		.drv_width	= 2,			\
+		.name		= id			\
+	}
+
+/* pin banks of pin-controller 0 */
+static struct samsung_pin_bank exynos4210_pin_banks0[] = {
+	EXYNOS4_PIN_BANK(0x000, EXYNOS4_GPIO_A0, "gpa0"),
+	EXYNOS4_PIN_BANK(0x020, EXYNOS4_GPIO_A1, "gpa1"),
+	EXYNOS4_PIN_BANK(0x040, EXYNOS4_GPIO_B, "gpb"),
+	EXYNOS4_PIN_BANK(0x060, EXYNOS4_GPIO_C0, "gpc0"),
+	EXYNOS4_PIN_BANK(0x080, EXYNOS4_GPIO_C1, "gpc1"),
+	EXYNOS4_PIN_BANK(0x0A0, EXYNOS4_GPIO_D0, "gpd0"),
+	EXYNOS4_PIN_BANK(0x0C0, EXYNOS4_GPIO_D1, "gpd1"),
+	EXYNOS4_PIN_BANK(0x0E0, EXYNOS4_GPIO_E0, "gpe0"),
+	EXYNOS4_PIN_BANK(0x100, EXYNOS4_GPIO_E1, "gpe1"),
+	EXYNOS4_PIN_BANK(0x120, EXYNOS4_GPIO_E2, "gpe2"),
+	EXYNOS4_PIN_BANK(0x140, EXYNOS4_GPIO_E3, "gpe3"),
+	EXYNOS4_PIN_BANK(0x160, EXYNOS4_GPIO_E4, "gpe4"),
+	EXYNOS4_PIN_BANK(0x180, EXYNOS4_GPIO_F0, "gpf0"),
+	EXYNOS4_PIN_BANK(0x1A0, EXYNOS4_GPIO_F1, "gpf1"),
+	EXYNOS4_PIN_BANK(0x1C0, EXYNOS4_GPIO_F2, "gpf2"),
+	EXYNOS4_PIN_BANK(0x1E0, EXYNOS4_GPIO_F3, "gpf3"),
+};
+
+#define EXYNOS4_PIN_BANK1(offset, __gpio, id)		\
+	{						\
+		.reg_offset	= offset,		\
+		.pin_base	= (__gpio##_START) - EXYNOS4_GPIO_J0_START,\
+		.nr_pins	= (__gpio##_NR),	\
+		.func_width	= 4,			\
+		.pud_width	= 2,			\
+		.drv_width	= 2,			\
+		.name		= id,			\
+	}
+
+/* pin banks of pin-controller 1 */
+static struct samsung_pin_bank exynos4210_pin_banks1[] = {
+	EXYNOS4_PIN_BANK1(0x000, EXYNOS4_GPIO_J0, "gpj0"),
+	EXYNOS4_PIN_BANK1(0x020, EXYNOS4_GPIO_J1, "gpj1"),
+	EXYNOS4_PIN_BANK1(0x040, EXYNOS4_GPIO_K0, "gpk0"),
+	EXYNOS4_PIN_BANK1(0x060, EXYNOS4_GPIO_K1, "gpk1"),
+	EXYNOS4_PIN_BANK1(0x080, EXYNOS4_GPIO_K2, "gpk2"),
+	EXYNOS4_PIN_BANK1(0x0A0, EXYNOS4_GPIO_K3, "gpk3"),
+	EXYNOS4_PIN_BANK1(0x0C0, EXYNOS4_GPIO_L0, "gpl0"),
+	EXYNOS4_PIN_BANK1(0x0E0, EXYNOS4_GPIO_L1, "gpl1"),
+	EXYNOS4_PIN_BANK1(0x100, EXYNOS4_GPIO_L2, "gpl2"),
+	EXYNOS4_PIN_BANK1(0x120, EXYNOS4_GPIO_Y0, "gpy0"),
+	EXYNOS4_PIN_BANK1(0x140, EXYNOS4_GPIO_Y1, "gpy1"),
+	EXYNOS4_PIN_BANK1(0x160, EXYNOS4_GPIO_Y2, "gpy2"),
+	EXYNOS4_PIN_BANK1(0x180, EXYNOS4_GPIO_Y3, "gpy3"),
+	EXYNOS4_PIN_BANK1(0x1A0, EXYNOS4_GPIO_Y4, "gpy4"),
+	EXYNOS4_PIN_BANK1(0x1C0, EXYNOS4_GPIO_Y5, "gpy5"),
+	EXYNOS4_PIN_BANK1(0x1E0, EXYNOS4_GPIO_Y6, "gpy6"),
+	EXYNOS4_PIN_BANK1(0xC00, EXYNOS4_GPIO_X0, "gpx0"),
+	EXYNOS4_PIN_BANK1(0xC20, EXYNOS4_GPIO_X1, "gpx1"),
+	EXYNOS4_PIN_BANK1(0xC40, EXYNOS4_GPIO_X2, "gpx2"),
+	EXYNOS4_PIN_BANK1(0xC60, EXYNOS4_GPIO_X3, "gpx3"),
+};
+
+#define EXYNOS4_PIN_BANK2(offset, __gpio, id)		\
+	{						\
+		.reg_offset	= offset,		\
+		.pin_base	= (__gpio##_START) - EXYNOS4_GPIO_Z_START,\
+		.nr_pins	= (__gpio##_NR),	\
+		.func_width	= 4,			\
+		.pud_width	= 2,			\
+		.drv_width	= 2,			\
+		.name		= id,			\
+	}
+
+/* pin banks of pin-controller 2 */
+static struct samsung_pin_bank exynos4210_pin_banks2[] = {
+	EXYNOS4_PIN_BANK2(0x000, EXYNOS4_GPIO_Z, "gpz"),
+};
+
+/* gpio range instance for pinctrl 0 */
+static struct pinctrl_gpio_range exynos4210_pctrl0_gpio_range = {
+	.name		= "exynos4210_gpio_range0",
+	.id		= 0,
+};
+
+/* gpio range instance for pinctrl 1 */
+static struct pinctrl_gpio_range exynos4210_pctrl1_gpio_range = {
+	.name		= "exynos4210_gpio_range1",
+	.id		= 0,
+};
+
+/* gpio range instance for pinctrl 2 */
+static struct pinctrl_gpio_range exynos4210_pctrl2_gpio_range = {
+	.name		= "exynos4210_gpio_range2",
+	.id		= 0,
+};
+
+/*
+ * Exynos4210 specific callback to translate PUD_xxx values into Exynos4210
+ * specific register values.
+ */
+static int exynos4210_xlate_pud(unsigned int pud)
+{
+	if (pud == PUD_UP)
+		return 3;
+	else
+		return pud;
+}
+
+/*
+ * Exynos4210 specific callback to translate DRV_xxx values into Exynos4210
+ * specific register values.
+ */
+static int exynos4210_xlate_drv(unsigned int drv)
+{
+	switch (drv) {
+	case DRV_3X:
+		return 1;
+	case DRV_2X:
+		return 2;
+	default:
+		return drv;
+	}
+}
+
+/*
+ * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
+ * three gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pinctrl_drv_data exynos4210_pinctrl_drv_data[] = {
+	{
+		/* pin-controller instance 0 data */
+		.ctrl = &(struct samsung_pin_ctrl) {
+			.grange		= &exynos4210_pctrl0_gpio_range,
+			.pin_banks	= exynos4210_pin_banks0,
+			.nr_banks	= ARRAY_SIZE(exynos4210_pin_banks0),
+			.base		= EXYNOS4_GPIO_A0_START,
+			.nr_pins	= EXYNOS4_GPIO_J0_START - 1,
+			.xlate_pud	= exynos4210_xlate_pud,
+			.xlate_drv	= exynos4210_xlate_drv,
+			.label		= "exynos4210-gpio-ctrl0",
+		},
+		.pctl = &(struct pinctrl_desc) {
+			.name		= "exynos4210_pinctrl",
+			.owner		= THIS_MODULE,
+		},
+		.pin_groups = exynos4210_pin_groups0,
+		.nr_groups = ARRAY_SIZE(exynos4210_pin_groups0),
+		.pmx_functions = exynos4210_pmx_functions0,
+		.nr_functions = ARRAY_SIZE(exynos4210_pmx_functions0),
+	}, {
+		/* pin-controller instance 1 data */
+		.ctrl = &(struct samsung_pin_ctrl) {
+			.grange		= &exynos4210_pctrl1_gpio_range,
+			.pin_banks	= exynos4210_pin_banks1,
+			.nr_banks	= ARRAY_SIZE(exynos4210_pin_banks1),
+			.base		= EXYNOS4_GPIO_J0_START,
+			.nr_pins	= EXYNOS4_GPIO_Z_START -
+						EXYNOS4_GPIO_J0_START,
+			.xlate_pud	= exynos4210_xlate_pud,
+			.xlate_drv	= exynos4210_xlate_drv,
+			.label		= "exynos4210-gpio-ctrl1",
+		},
+		.pctl = &(struct pinctrl_desc) {
+			.name		= "exynos4210_pinctrl",
+			.owner		= THIS_MODULE,
+		},
+		.pin_groups = exynos4210_pin_groups1,
+		.nr_groups = ARRAY_SIZE(exynos4210_pin_groups1),
+		.pmx_functions = exynos4210_pmx_functions1,
+		.nr_functions = ARRAY_SIZE(exynos4210_pmx_functions1),
+	}, {
+		/* pin-controller instance 2 data */
+		.ctrl = &(struct samsung_pin_ctrl) {
+			.grange		= &exynos4210_pctrl2_gpio_range,
+			.pin_banks	= exynos4210_pin_banks2,
+			.nr_banks	= ARRAY_SIZE(exynos4210_pin_banks2),
+			.base		= EXYNOS4_GPIO_Z_START,
+			.nr_pins	= EXYNOS4_GPIO_Z_NR,
+			.xlate_pud	= exynos4210_xlate_pud,
+			.xlate_drv	= exynos4210_xlate_drv,
+			.label		= "exynos4210-gpio-ctrl2",
+		},
+		.pctl = &(struct pinctrl_desc) {
+			.name		= "exynos4210_pinctrl",
+			.owner		= THIS_MODULE,
+		},
+		.pin_groups = exynos4210_pin_groups2,
+		.nr_groups = ARRAY_SIZE(exynos4210_pin_groups2),
+		.pmx_functions = exynos4210_pmx_functions2,
+		.nr_functions = ARRAY_SIZE(exynos4210_pmx_functions2),
+	},
+};
-- 
1.6.6.rc2



From kgene.kim at samsung.com  Sat Mar 10 05:59:22 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 02:59:22 -0800
Subject: [PATCH v2 RE-SEND] [CPUFREQ] EXYNOS4X12: Add support cpufreq for
 EXYNOS4X12
Message-ID: <1331377162-25134-1-git-send-email-kgene.kim@samsung.com>

From: Jaecheol Lee <jc.lee at samsung.com>

This patch adds support cpufreq for EXYNOS4X12 SoCs. Basically,
the exynos-cpufreq.c is used commonly and exynos4x12-cpufreq.c
is used for EXYNOS4212(two Cortex-A9 cores) and EXYNOS4412(four
Cortex-A9 cores) SoCs.

Signed-off-by: Jaecheol Lee <jc.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
Changes since v1:
Address comments from Sylwester

 arch/arm/mach-exynos/include/mach/cpufreq.h |    1 +
 drivers/cpufreq/Kconfig.arm                 |    7 +
 drivers/cpufreq/Makefile                    |    1 +
 drivers/cpufreq/exynos-cpufreq.c            |    2 +
 drivers/cpufreq/exynos4x12-cpufreq.c        |  536 +++++++++++++++++++++++++++
 5 files changed, 547 insertions(+), 0 deletions(-)
 create mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c

diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
index 3df27f2..96ac0cb 100644
--- a/arch/arm/mach-exynos/include/mach/cpufreq.h
+++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
@@ -32,3 +32,4 @@ struct exynos_dvfs_info {
 };
 
 extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
+extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index dc59abf..9b99a96 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -47,6 +47,7 @@ config ARM_EXYNOS_CPUFREQ
 	bool "SAMSUNG EXYNOS SoCs"
 	depends on ARCH_EXYNOS
 	select ARM_EXYNOS4210_CPUFREQ if CPU_EXYNOS4210
+	select ARM_EXYNOS4X12_CPUFREQ if (SOC_EXYNOS4212 || SOC_EXYNOS4412)
 	default y
 	help
 	  This adds the CPUFreq driver common part for Samsung
@@ -60,3 +61,9 @@ config ARM_EXYNOS4210_CPUFREQ
 	help
 	  This adds the CPUFreq driver for Samsung EXYNOS4210
 	  SoC (S5PV310 or S5PC210).
+
+config ARM_EXYNOS4X12_CPUFREQ
+	bool "Samsung EXYNOS4X12"
+	help
+	  This adds the CPUFreq driver for Samsung EXYNOS4X12
+	  SoC (EXYNOS4212 or EXYNOS4412).
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 042fbae..f37bbcc 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_ARM_S3C64XX_CPUFREQ)	+= s3c64xx-cpufreq.o
 obj-$(CONFIG_ARM_S5PV210_CPUFREQ)	+= s5pv210-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
+obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)	+= exynos4x12-cpufreq.o
 obj-$(CONFIG_ARCH_OMAP2PLUS)            += omap-cpufreq.o
 
 ##################################################################################
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index 7cfb516..2c63b68 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -254,6 +254,8 @@ static int __init exynos_cpufreq_init(void)
 
 	if (soc_is_exynos4210())
 		ret = exynos4210_cpufreq_init(exynos_info);
+	else if (soc_is_exynos4212() || soc_is_exynos4412())
+		ret = exynos4x12_cpufreq_init(exynos_info);
 	else
 		pr_err("%s: CPU type not found\n", __func__);
 
diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
new file mode 100644
index 0000000..8c5a7af
--- /dev/null
+++ b/drivers/cpufreq/exynos4x12-cpufreq.c
@@ -0,0 +1,536 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS4X12 - CPU frequency scaling support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/cpufreq.h>
+
+#include <mach/regs-clock.h>
+#include <mach/cpufreq.h>
+
+#define CPUFREQ_LEVEL_END	(L13 + 1)
+
+static int max_support_idx;
+static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
+
+static struct clk *cpu_clk;
+static struct clk *moutcore;
+static struct clk *mout_mpll;
+static struct clk *mout_apll;
+
+struct cpufreq_clkdiv {
+	unsigned int	index;
+	unsigned int	clkdiv;
+	unsigned int	clkdiv1;
+};
+
+static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END];
+
+static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
+	{L0, 1500 * 1000},
+	{L1, 1400 * 1000},
+	{L2, 1300 * 1000},
+	{L3, 1200 * 1000},
+	{L4, 1100 * 1000},
+	{L5, 1000 * 1000},
+	{L6,  900 * 1000},
+	{L7,  800 * 1000},
+	{L8,  700 * 1000},
+	{L9,  600 * 1000},
+	{L10, 500 * 1000},
+	{L11, 400 * 1000},
+	{L12, 300 * 1000},
+	{L13, 200 * 1000},
+	{0, CPUFREQ_TABLE_END},
+};
+
+static struct cpufreq_clkdiv exynos4x12_clkdiv_table[CPUFREQ_LEVEL_END];
+
+static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
+	 *		DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
+	 */
+	/* ARM L0: 1500 MHz */
+	{ 0, 3, 7, 0, 6, 1, 2, 0 },
+
+	/* ARM L1: 1400 MHz */
+	{ 0, 3, 7, 0, 6, 1, 2, 0 },
+
+	/* ARM L2: 1300 MHz */
+	{ 0, 3, 7, 0, 5, 1, 2, 0 },
+
+	/* ARM L3: 1200 MHz */
+	{ 0, 3, 7, 0, 5, 1, 2, 0 },
+
+	/* ARM L4: 1100 MHz */
+	{ 0, 3, 6, 0, 4, 1, 2, 0 },
+
+	/* ARM L5: 1000 MHz */
+	{ 0, 2, 5, 0, 4, 1, 1, 0 },
+
+	/* ARM L6: 900 MHz */
+	{ 0, 2, 5, 0, 3, 1, 1, 0 },
+
+	/* ARM L7: 800 MHz */
+	{ 0, 2, 5, 0, 3, 1, 1, 0 },
+
+	/* ARM L8: 700 MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L9: 600 MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L10: 500 MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L11: 400 MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L12: 300 MHz */
+	{ 0, 2, 4, 0, 2, 1, 1, 0 },
+
+	/* ARM L13: 200 MHz */
+	{ 0, 1, 3, 0, 1, 1, 1, 0 },
+};
+
+static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = {
+	/*
+	 * Clock divider value for following
+	 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
+	 *		DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
+	 */
+	/* ARM L0: 1500 MHz */
+	{ 0, 3, 7, 0, 6, 1, 2, 0 },
+
+	/* ARM L1: 1400 MHz */
+	{ 0, 3, 7, 0, 6, 1, 2, 0 },
+
+	/* ARM L2: 1300 MHz */
+	{ 0, 3, 7, 0, 5, 1, 2, 0 },
+
+	/* ARM L3: 1200 MHz */
+	{ 0, 3, 7, 0, 5, 1, 2, 0 },
+
+	/* ARM L4: 1100 MHz */
+	{ 0, 3, 6, 0, 4, 1, 2, 0 },
+
+	/* ARM L5: 1000 MHz */
+	{ 0, 2, 5, 0, 4, 1, 1, 0 },
+
+	/* ARM L6: 900 MHz */
+	{ 0, 2, 5, 0, 3, 1, 1, 0 },
+
+	/* ARM L7: 800 MHz */
+	{ 0, 2, 5, 0, 3, 1, 1, 0 },
+
+	/* ARM L8: 700 MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L9: 600 MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L10: 500 MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L11: 400 MHz */
+	{ 0, 2, 4, 0, 3, 1, 1, 0 },
+
+	/* ARM L12: 300 MHz */
+	{ 0, 2, 4, 0, 2, 1, 1, 0 },
+
+	/* ARM L13: 200 MHz */
+	{ 0, 1, 3, 0, 1, 1, 1, 0 },
+};
+
+static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = {
+	/* Clock divider value for following
+	 * { DIVCOPY, DIVHPM }
+	 */
+	/* ARM L0: 1500 MHz */
+	{ 6, 0 },
+
+	/* ARM L1: 1400 MHz */
+	{ 6, 0 },
+
+	/* ARM L2: 1300 MHz */
+	{ 5, 0 },
+
+	/* ARM L3: 1200 MHz */
+	{ 5, 0 },
+
+	/* ARM L4: 1100 MHz */
+	{ 4, 0 },
+
+	/* ARM L5: 1000 MHz */
+	{ 4, 0 },
+
+	/* ARM L6: 900 MHz */
+	{ 3, 0 },
+
+	/* ARM L7: 800 MHz */
+	{ 3, 0 },
+
+	/* ARM L8: 700 MHz */
+	{ 3, 0 },
+
+	/* ARM L9: 600 MHz */
+	{ 3, 0 },
+
+	/* ARM L10: 500 MHz */
+	{ 3, 0 },
+
+	/* ARM L11: 400 MHz */
+	{ 3, 0 },
+
+	/* ARM L12: 300 MHz */
+	{ 3, 0 },
+
+	/* ARM L13: 200 MHz */
+	{ 3, 0 },
+};
+
+static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = {
+	/* Clock divider value for following
+	 * { DIVCOPY, DIVHPM, DIVCORES }
+	 */
+	/* ARM L0: 1500 MHz */
+	{ 6, 0, 7 },
+
+	/* ARM L1: 1400 MHz */
+	{ 6, 0, 6 },
+
+	/* ARM L2: 1300 MHz */
+	{ 5, 0, 6 },
+
+	/* ARM L3: 1200 MHz */
+	{ 5, 0, 5 },
+
+	/* ARM L4: 1100 MHz */
+	{ 4, 0, 5 },
+
+	/* ARM L5: 1000 MHz */
+	{ 4, 0, 4 },
+
+	/* ARM L6: 900 MHz */
+	{ 3, 0, 4 },
+
+	/* ARM L7: 800 MHz */
+	{ 3, 0, 3 },
+
+	/* ARM L8: 700 MHz */
+	{ 3, 0, 3 },
+
+	/* ARM L9: 600 MHz */
+	{ 3, 0, 2 },
+
+	/* ARM L10: 500 MHz */
+	{ 3, 0, 2 },
+
+	/* ARM L11: 400 MHz */
+	{ 3, 0, 1 },
+
+	/* ARM L12: 300 MHz */
+	{ 3, 0, 1 },
+
+	/* ARM L13: 200 MHz */
+	{ 3, 0, 0 },
+};
+
+static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {
+	/* APLL FOUT L0: 1500 MHz */
+	((250 << 16) | (4 << 8) | (0x0)),
+
+	/* APLL FOUT L1: 1400 MHz */
+	((175 << 16) | (3 << 8) | (0x0)),
+
+	/* APLL FOUT L2: 1300 MHz */
+	((325 << 16) | (6 << 8) | (0x0)),
+
+	/* APLL FOUT L3: 1200 MHz */
+	((200 << 16) | (4 << 8) | (0x0)),
+
+	/* APLL FOUT L4: 1100 MHz */
+	((275 << 16) | (6 << 8) | (0x0)),
+
+	/* APLL FOUT L5: 1000 MHz */
+	((125 << 16) | (3 << 8) | (0x0)),
+
+	/* APLL FOUT L6: 900 MHz */
+	((150 << 16) | (4 << 8) | (0x0)),
+
+	/* APLL FOUT L7: 800 MHz */
+	((100 << 16) | (3 << 8) | (0x0)),
+
+	/* APLL FOUT L8: 700 MHz */
+	((175 << 16) | (3 << 8) | (0x1)),
+
+	/* APLL FOUT L9: 600 MHz */
+	((200 << 16) | (4 << 8) | (0x1)),
+
+	/* APLL FOUT L10: 500 MHz */
+	((125 << 16) | (3 << 8) | (0x1)),
+
+	/* APLL FOUT L11 400 MHz */
+	((100 << 16) | (3 << 8) | (0x1)),
+
+	/* APLL FOUT L12: 300 MHz */
+	((200 << 16) | (4 << 8) | (0x2)),
+
+	/* APLL FOUT L13: 200 MHz */
+	((100 << 16) | (3 << 8) | (0x2)),
+};
+
+static const unsigned int asv_voltage_4x12[CPUFREQ_LEVEL_END] = {
+	1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
+	1000000,  987500,  975000,  950000,  925000,  900000,  900000
+};
+
+static void exynos4x12_set_clkdiv(unsigned int div_index)
+{
+	unsigned int tmp;
+	unsigned int stat_cpu1;
+
+	/* Change Divider - CPU0 */
+
+	tmp = exynos4x12_clkdiv_table[div_index].clkdiv;
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+
+	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
+		cpu_relax();
+
+	/* Change Divider - CPU1 */
+	tmp = exynos4x12_clkdiv_table[div_index].clkdiv1;
+
+	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+	if (soc_is_exynos4212())
+		stat_cpu1 = 0x11;
+	else
+		stat_cpu1 = 0x111;
+
+	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
+		cpu_relax();
+}
+
+static void exynos4x12_set_apll(unsigned int index)
+{
+	unsigned int tmp, pdiv;
+
+	/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
+	clk_set_parent(moutcore, mout_mpll);
+
+	do {
+		cpu_relax();
+		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
+		tmp &= 0x7;
+	} while (tmp != 0x2);
+
+	/* 2. Set APLL Lock time */
+	pdiv = ((exynos4x12_apll_pms_table[index] >> 8) & 0x3f);
+
+	__raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK);
+
+	/* 3. Change PLL PMS values */
+	tmp = __raw_readl(EXYNOS4_APLL_CON0);
+	tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
+	tmp |= exynos4x12_apll_pms_table[index];
+	__raw_writel(tmp, EXYNOS4_APLL_CON0);
+
+	/* 4. wait_lock_time */
+	do {
+		cpu_relax();
+		tmp = __raw_readl(EXYNOS4_APLL_CON0);
+	} while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
+
+	/* 5. MUX_CORE_SEL = APLL */
+	clk_set_parent(moutcore, mout_apll);
+
+	do {
+		cpu_relax();
+		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
+	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
+}
+
+bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index)
+{
+	unsigned int old_pm = exynos4x12_apll_pms_table[old_index] >> 8;
+	unsigned int new_pm = exynos4x12_apll_pms_table[new_index] >> 8;
+
+	return (old_pm == new_pm) ? 0 : 1;
+}
+
+static void exynos4x12_set_frequency(unsigned int old_index,
+				  unsigned int new_index)
+{
+	unsigned int tmp;
+
+	if (old_index > new_index) {
+		if (!exynos4x12_pms_change(old_index, new_index)) {
+			/* 1. Change the system clock divider values */
+			exynos4x12_set_clkdiv(new_index);
+			/* 2. Change just s value in apll m,p,s value */
+			tmp = __raw_readl(EXYNOS4_APLL_CON0);
+			tmp &= ~(0x7 << 0);
+			tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7);
+			__raw_writel(tmp, EXYNOS4_APLL_CON0);
+
+		} else {
+			/* Clock Configuration Procedure */
+			/* 1. Change the system clock divider values */
+			exynos4x12_set_clkdiv(new_index);
+			/* 2. Change the apll m,p,s value */
+			exynos4x12_set_apll(new_index);
+		}
+	} else if (old_index < new_index) {
+		if (!exynos4x12_pms_change(old_index, new_index)) {
+			/* 1. Change just s value in apll m,p,s value */
+			tmp = __raw_readl(EXYNOS4_APLL_CON0);
+			tmp &= ~(0x7 << 0);
+			tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7);
+			__raw_writel(tmp, EXYNOS4_APLL_CON0);
+			/* 2. Change the system clock divider values */
+			exynos4x12_set_clkdiv(new_index);
+		} else {
+			/* Clock Configuration Procedure */
+			/* 1. Change the apll m,p,s value */
+			exynos4x12_set_apll(new_index);
+			/* 2. Change the system clock divider values */
+			exynos4x12_set_clkdiv(new_index);
+		}
+	}
+}
+
+static void __init set_volt_table(void)
+{
+	unsigned int i;
+
+	max_support_idx = L1;
+
+	/* Not supported */
+	exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
+
+	for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
+		exynos4x12_volt_table[i] = asv_voltage_4x12[i];
+}
+
+int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
+{
+	int i;
+	unsigned int tmp;
+	unsigned long rate;
+
+	set_volt_table();
+
+	cpu_clk = clk_get(NULL, "armclk");
+	if (IS_ERR(cpu_clk))
+		return PTR_ERR(cpu_clk);
+
+	moutcore = clk_get(NULL, "moutcore");
+	if (IS_ERR(moutcore))
+		goto err_moutcore;
+
+	mout_mpll = clk_get(NULL, "mout_mpll");
+	if (IS_ERR(mout_mpll))
+		goto err_mout_mpll;
+
+	rate = clk_get_rate(mout_mpll) / 1000;
+
+	mout_apll = clk_get(NULL, "mout_apll");
+	if (IS_ERR(mout_apll))
+		goto err_mout_apll;
+
+	for (i = L0; i <  CPUFREQ_LEVEL_END; i++) {
+
+		exynos4x12_clkdiv_table[i].index = i;
+
+		tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
+
+		tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
+			EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
+			EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
+			EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
+			EXYNOS4_CLKDIV_CPU0_ATB_MASK |
+			EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
+			EXYNOS4_CLKDIV_CPU0_APLL_MASK);
+
+		if (soc_is_exynos4212()) {
+			tmp |= ((clkdiv_cpu0_4212[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
+				(clkdiv_cpu0_4212[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
+				(clkdiv_cpu0_4212[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
+				(clkdiv_cpu0_4212[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
+				(clkdiv_cpu0_4212[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
+				(clkdiv_cpu0_4212[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
+				(clkdiv_cpu0_4212[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
+		} else {
+			tmp &= ~EXYNOS4_CLKDIV_CPU0_CORE2_MASK;
+
+			tmp |= ((clkdiv_cpu0_4412[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
+				(clkdiv_cpu0_4412[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
+				(clkdiv_cpu0_4412[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
+				(clkdiv_cpu0_4412[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
+				(clkdiv_cpu0_4412[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
+				(clkdiv_cpu0_4412[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
+				(clkdiv_cpu0_4412[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
+				(clkdiv_cpu0_4412[i][7] << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT));
+		}
+
+		exynos4x12_clkdiv_table[i].clkdiv = tmp;
+
+		tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
+
+		if (soc_is_exynos4212()) {
+			tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
+				EXYNOS4_CLKDIV_CPU1_HPM_MASK);
+			tmp |= ((clkdiv_cpu1_4212[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
+				(clkdiv_cpu1_4212[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT));
+		} else {
+			tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
+				EXYNOS4_CLKDIV_CPU1_HPM_MASK |
+				EXYNOS4_CLKDIV_CPU1_CORES_MASK);
+			tmp |= ((clkdiv_cpu1_4412[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
+				(clkdiv_cpu1_4412[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
+				(clkdiv_cpu1_4412[i][2] << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT));
+		}
+		exynos4x12_clkdiv_table[i].clkdiv1 = tmp;
+	}
+
+	info->mpll_freq_khz = rate;
+	info->pm_lock_idx = L5;
+	info->pll_safe_idx = L7;
+	info->max_support_idx = max_support_idx;
+	info->min_support_idx = min_support_idx;
+	info->cpu_clk = cpu_clk;
+	info->volt_table = exynos4x12_volt_table;
+	info->freq_table = exynos4x12_freq_table;
+	info->set_freq = exynos4x12_set_frequency;
+	info->need_apll_change = exynos4x12_pms_change;
+
+	return 0;
+
+err_mout_apll:
+	clk_put(mout_mpll);
+err_mout_mpll:
+	clk_put(moutcore);
+err_moutcore:
+	clk_put(cpu_clk);
+
+	pr_debug("%s: failed initialization\n", __func__);
+	return -EINVAL;
+}
+EXPORT_SYMBOL(exynos4x12_cpufreq_init);
-- 
1.7.0.4



From tony at atomide.com  Mon Mar 12 14:05:01 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 12 Mar 2012 11:05:01 -0700
Subject: [PATCH 4/8] ARM: OMAP1: Move 16xx GPIO system clock to
 platform init code
In-Reply-To: <20120312173005.A11093E07B0@localhost>
References: <20120221233619.18709.87982.stgit@kaulin.local>
 <20120221234042.18709.57610.stgit@kaulin.local>
 <20120312173005.A11093E07B0@localhost>
Message-ID: <20120312180500.GJ12083@atomide.com>

* Grant Likely <grant.likely at secretlab.ca> [120312 10:32]:
> On Tue, 21 Feb 2012 15:40:42 -0800, Tony Lindgren <tony at atomide.com> wrote:
> > This way we can remove omap_read/write call from the GPIO driver
> > and remove include to linux/io.h.
> > 
> > Cc: Grant Likely <grant.likely at secretlab.ca>
> > Signed-off-by: Tony Lindgren <tony at atomide.com>
> 
> Acked-by: Grant Likely <grant.likely at secretlab.ca>
> 
> Who will be picking up this series?  How intertwined is it with your tree Tony?

Thanks for following up on this, no need to do anything on this.

This popped up few weeks ago and was resolved by pulling your GPIO
branch into arm-soc. For more info, please see:

Subject: linux-next: manual merge of the arm-soc tree with the gpio tree

http://lkml.org/lkml/2012/3/1/7

Regards,

Tony


From plagnioj at jcrosoft.com  Fri Mar  9 04:53:36 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 9 Mar 2012 10:53:36 +0100
Subject: [PATCH 2/5 v3] ARM: at91: sam9g20 add i2c DT support
In-Reply-To: <4F58E77B.4010500@gmail.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <1331196635-27203-2-git-send-email-plagnioj@jcrosoft.com>
 <4F58E77B.4010500@gmail.com>
Message-ID: <20120309095336.GK27213@game.jcrosoft.org>

On 11:08 Thu 08 Mar     , Rob Herring wrote:
> On 03/08/2012 02:50 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > For now on use i2c-gpio driver on the same pin as the hardware IP.
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> > Cc: devicetree-discuss at lists.ozlabs.org
> > ---
> > v3:
> > 
> > 	update i2c binding (Rob comments)
> > 
> > Best Regards,
> > J.
> >  arch/arm/boot/dts/at91sam9g20.dtsi |   13 +++++++++++++
> >  1 files changed, 13 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
> > index 4b0dc99..072b2da 100644
> > --- a/arch/arm/boot/dts/at91sam9g20.dtsi
> > +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
> > @@ -189,4 +189,17 @@
> >  			status = "disabled";
> >  		};
> >  	};
> > +> > +	i2c-gpio at 0 {
> 
> You updated the example, but not all the actual uses to i2c at 0.
on purpose as on some soc we will have HW and soft binding

on the board you put the alias

Best Regards,
J.
> 
> Rob
> 
> > +		compatible = "i2c-gpio";
> > +		gpios = <&pioA 23 0 /* sda */
> > +			 &pioA 24 0 /* scl */
> > +			>;
> > +		i2c-gpio,sda-open-drain;
> > +		i2c-gpio,scl-open-drain;
> > +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		status = "disabled";
> > +	};
> >  };
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From kgene.kim at samsung.com  Sat Mar 10 06:00:02 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 03:00:02 -0800
Subject: [PATCH v2 RE-SEND] [CPUFREQ] EXYNOS5250: Add support cpufreq for
 EXYNOS5250
Message-ID: <1331377202-25173-1-git-send-email-kgene.kim@samsung.com>

From: Jaecheol Lee <jc.lee at samsung.com>

This patch adds support cpufreq for EXYNOS5250 SoC. Basically,
the exynos-cpufreq.c is used commonly and exynos5250-cpufreq.c
is used for EXYNOS5250(two Cortex-A15 cores) SoC.

Signed-off-by: Jaecheol Lee <jc.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/include/mach/cpufreq.h |    1 +
 drivers/cpufreq/Kconfig.arm                 |    7 +
 drivers/cpufreq/Makefile                    |    1 +
 drivers/cpufreq/exynos-cpufreq.c            |    2 +
 drivers/cpufreq/exynos5250-cpufreq.c        |  347 +++++++++++++++++++++++++++
 5 files changed, 358 insertions(+), 0 deletions(-)
 create mode 100644 drivers/cpufreq/exynos5250-cpufreq.c

diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
index 96ac0cb..7517c3f 100644
--- a/arch/arm/mach-exynos/include/mach/cpufreq.h
+++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
@@ -33,3 +33,4 @@ struct exynos_dvfs_info {
 
 extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
 extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
+extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 9b99a96..2e33515 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -48,6 +48,7 @@ config ARM_EXYNOS_CPUFREQ
 	depends on ARCH_EXYNOS
 	select ARM_EXYNOS4210_CPUFREQ if CPU_EXYNOS4210
 	select ARM_EXYNOS4X12_CPUFREQ if (SOC_EXYNOS4212 || SOC_EXYNOS4412)
+	select ARM_EXYNOS5250_CPUFREQ if SOC_EXYNOS5250
 	default y
 	help
 	  This adds the CPUFreq driver common part for Samsung
@@ -67,3 +68,9 @@ config ARM_EXYNOS4X12_CPUFREQ
 	help
 	  This adds the CPUFreq driver for Samsung EXYNOS4X12
 	  SoC (EXYNOS4212 or EXYNOS4412).
+
+config ARM_EXYNOS5250_CPUFREQ
+	bool "Samsung EXYNOS5250"
+	help
+	  This adds the CPUFreq driver for Samsung EXYNOS5250
+	  SoC.
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index f37bbcc..3cbbcd0 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_ARM_S5PV210_CPUFREQ)	+= s5pv210-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)	+= exynos4x12-cpufreq.o
+obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ)	+= exynos5250-cpufreq.o
 obj-$(CONFIG_ARCH_OMAP2PLUS)            += omap-cpufreq.o
 
 ##################################################################################
diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index 2c63b68..b243a7e 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -256,6 +256,8 @@ static int __init exynos_cpufreq_init(void)
 		ret = exynos4210_cpufreq_init(exynos_info);
 	else if (soc_is_exynos4212() || soc_is_exynos4412())
 		ret = exynos4x12_cpufreq_init(exynos_info);
+	else if (soc_is_exynos5250())
+		ret = exynos5250_cpufreq_init(exynos_info);
 	else
 		pr_err("%s: CPU type not found\n", __func__);
 
diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c
new file mode 100644
index 0000000..a883316
--- /dev/null
+++ b/drivers/cpufreq/exynos5250-cpufreq.c
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS5250 - CPU frequency scaling support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/cpufreq.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/cpufreq.h>
+
+#define CPUFREQ_LEVEL_END	(L15 + 1)
+
+static int max_support_idx;
+static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
+static struct clk *cpu_clk;
+static struct clk *moutcore;
+static struct clk *mout_mpll;
+static struct clk *mout_apll;
+
+struct cpufreq_clkdiv {
+	unsigned int	index;
+	unsigned int	clkdiv;
+	unsigned int	clkdiv1;
+};
+
+static unsigned int exynos5250_volt_table[CPUFREQ_LEVEL_END];
+
+static struct cpufreq_frequency_table exynos5250_freq_table[] = {
+	{L0, 1700 * 1000},
+	{L1, 1600 * 1000},
+	{L2, 1500 * 1000},
+	{L3, 1400 * 1000},
+	{L4, 1300 * 1000},
+	{L5, 1200 * 1000},
+	{L6, 1100 * 1000},
+	{L7, 1000 * 1000},
+	{L8, 900 * 1000},
+	{L9, 800 * 1000},
+	{L10, 700 * 1000},
+	{L11, 600 * 1000},
+	{L12, 500 * 1000},
+	{L13, 400 * 1000},
+	{L14, 300 * 1000},
+	{L15, 200 * 1000},
+	{0, CPUFREQ_TABLE_END},
+};
+
+static struct cpufreq_clkdiv exynos5250_clkdiv_table[CPUFREQ_LEVEL_END];
+
+static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = {
+	/*
+	 * Clock divider value for following
+	 * { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 }
+	 */
+	{ 0, 3, 7, 7, 6, 1, 3, 0 },	/* 1700 MHz - N/A */
+	{ 0, 3, 7, 7, 6, 1, 3, 0 },	/* 1600 MHz - N/A */
+	{ 0, 3, 7, 7, 5, 1, 3, 0 },	/* 1500 MHz - N/A */
+	{ 0, 3, 7, 7, 6, 1, 3, 0 },	/* 1400 MHz */
+	{ 0, 3, 7, 7, 6, 1, 3, 0 },	/* 1300 MHz */
+	{ 0, 3, 7, 7, 5, 1, 3, 0 },	/* 1200 MHz */
+	{ 0, 2, 7, 7, 5, 1, 2, 0 },	/* 1100 MHz */
+	{ 0, 2, 7, 7, 4, 1, 2, 0 },	/* 1000 MHz */
+	{ 0, 2, 7, 7, 4, 1, 2, 0 },	/* 900 MHz */
+	{ 0, 2, 7, 7, 3, 1, 1, 0 },	/* 800 MHz */
+	{ 0, 1, 7, 7, 3, 1, 1, 0 },	/* 700 MHz */
+	{ 0, 1, 7, 7, 2, 1, 1, 0 },	/* 600 MHz */
+	{ 0, 1, 7, 7, 2, 1, 1, 0 },	/* 500 MHz */
+	{ 0, 1, 7, 7, 1, 1, 1, 0 },	/* 400 MHz */
+	{ 0, 1, 7, 7, 1, 1, 1, 0 },	/* 300 MHz */
+	{ 0, 1, 7, 7, 1, 1, 1, 0 },	/* 200 MHz */
+};
+
+static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
+	/* Clock divider value for following
+	 * { COPY, HPM }
+	 */
+	{ 0, 2 },	/* 1700 MHz - N/A */
+	{ 0, 2 },	/* 1600 MHz - N/A */
+	{ 0, 2 },	/* 1500 MHz - N/A */
+	{ 0, 2 },	/* 1400 MHz */
+	{ 0, 2 },	/* 1300 MHz */
+	{ 0, 2 },	/* 1200 MHz */
+	{ 0, 2 },	/* 1100 MHz */
+	{ 0, 2 },	/* 1000 MHz */
+	{ 0, 2 },	/* 900 MHz */
+	{ 0, 2 },	/* 800 MHz */
+	{ 0, 2 },	/* 700 MHz */
+	{ 0, 2 },	/* 600 MHz */
+	{ 0, 2 },	/* 500 MHz */
+	{ 0, 2 },	/* 400 MHz */
+	{ 0, 2 },	/* 300 MHz */
+	{ 0, 2 },	/* 200 MHz */
+};
+
+static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
+	(0),				/* 1700 MHz - N/A */
+	(0),				/* 1600 MHz - N/A */
+	(0),				/* 1500 MHz - N/A */
+	(0),				/* 1400 MHz */
+	((325 << 16) | (6 << 8) | 0),	/* 1300 MHz */
+	((200 << 16) | (4 << 8) | 0),	/* 1200 MHz */
+	((275 << 16) | (6 << 8) | 0),	/* 1100 MHz */
+	((125 << 16) | (3 << 8) | 0),	/* 1000 MHz */
+	((150 << 16) | (4 << 8) | 0),	/* 900 MHz */
+	((100 << 16) | (3 << 8) | 0),	/* 800 MHz */
+	((175 << 16) | (3 << 8) | 1),	/* 700 MHz */
+	((200 << 16) | (4 << 8) | 1),	/* 600 MHz */
+	((125 << 16) | (3 << 8) | 1),	/* 500 MHz */
+	((100 << 16) | (3 << 8) | 1),	/* 400 MHz */
+	((200 << 16) | (4 << 8) | 2),	/* 300 MHz */
+	((100 << 16) | (3 << 8) | 2),	/* 200 MHz */
+};
+
+/* ASV group voltage table */
+static const unsigned int asv_voltage_5250[CPUFREQ_LEVEL_END] = {
+	0, 0, 0, 0, 0, 0, 0,	/* 1700 MHz ~ 1100 MHz Not supported */
+	1175000, 1125000, 1075000, 1050000, 1000000,
+	950000, 925000, 925000, 900000
+};
+
+static void set_clkdiv(unsigned int div_index)
+{
+	unsigned int tmp;
+
+	/* Change Divider - CPU0 */
+
+	tmp = exynos5250_clkdiv_table[div_index].clkdiv;
+
+	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
+
+	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
+		cpu_relax();
+
+	/* Change Divider - CPU1 */
+	tmp = exynos5250_clkdiv_table[div_index].clkdiv1;
+
+	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
+
+	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
+		cpu_relax();
+}
+
+static void set_apll(unsigned int new_index,
+			     unsigned int old_index)
+{
+	unsigned int tmp, pdiv;
+
+	/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
+	clk_set_parent(moutcore, mout_mpll);
+
+	do {
+		cpu_relax();
+		tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
+		tmp &= 0x7;
+	} while (tmp != 0x2);
+
+	/* 2. Set APLL Lock time */
+	pdiv = ((exynos5_apll_pms_table[new_index] >> 8) & 0x3f);
+
+	__raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK);
+
+	/* 3. Change PLL PMS values */
+	tmp = __raw_readl(EXYNOS5_APLL_CON0);
+	tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
+	tmp |= exynos5_apll_pms_table[new_index];
+	__raw_writel(tmp, EXYNOS5_APLL_CON0);
+
+	/* 4. wait_lock_time */
+	do {
+		cpu_relax();
+		tmp = __raw_readl(EXYNOS5_APLL_CON0);
+	} while (!(tmp & (0x1 << 29)));
+
+	/* 5. MUX_CORE_SEL = APLL */
+	clk_set_parent(moutcore, mout_apll);
+
+	do {
+		cpu_relax();
+		tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
+		tmp &= (0x7 << 16);
+	} while (tmp != (0x1 << 16));
+
+}
+
+bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index)
+{
+	unsigned int old_pm = (exynos5_apll_pms_table[old_index] >> 8);
+	unsigned int new_pm = (exynos5_apll_pms_table[new_index] >> 8);
+
+	return (old_pm == new_pm) ? 0 : 1;
+}
+
+static void exynos5250_set_frequency(unsigned int old_index,
+				  unsigned int new_index)
+{
+	unsigned int tmp;
+
+	if (old_index > new_index) {
+		if (!exynos5250_pms_change(old_index, new_index)) {
+			/* 1. Change the system clock divider values */
+			set_clkdiv(new_index);
+			/* 2. Change just s value in apll m,p,s value */
+			tmp = __raw_readl(EXYNOS5_APLL_CON0);
+			tmp &= ~(0x7 << 0);
+			tmp |= (exynos5_apll_pms_table[new_index] & 0x7);
+			__raw_writel(tmp, EXYNOS5_APLL_CON0);
+
+		} else {
+			/* Clock Configuration Procedure */
+			/* 1. Change the system clock divider values */
+			set_clkdiv(new_index);
+			/* 2. Change the apll m,p,s value */
+			set_apll(new_index, old_index);
+		}
+	} else if (old_index < new_index) {
+		if (!exynos5250_pms_change(old_index, new_index)) {
+			/* 1. Change just s value in apll m,p,s value */
+			tmp = __raw_readl(EXYNOS5_APLL_CON0);
+			tmp &= ~(0x7 << 0);
+			tmp |= (exynos5_apll_pms_table[new_index] & 0x7);
+			__raw_writel(tmp, EXYNOS5_APLL_CON0);
+			/* 2. Change the system clock divider values */
+			set_clkdiv(new_index);
+		} else {
+			/* Clock Configuration Procedure */
+			/* 1. Change the apll m,p,s value */
+			set_apll(new_index, old_index);
+			/* 2. Change the system clock divider values */
+			set_clkdiv(new_index);
+		}
+	}
+}
+
+static void __init set_volt_table(void)
+{
+	unsigned int i;
+
+	exynos5250_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
+	exynos5250_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
+	exynos5250_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID;
+	exynos5250_freq_table[L3].frequency = CPUFREQ_ENTRY_INVALID;
+	exynos5250_freq_table[L4].frequency = CPUFREQ_ENTRY_INVALID;
+	exynos5250_freq_table[L5].frequency = CPUFREQ_ENTRY_INVALID;
+	exynos5250_freq_table[L6].frequency = CPUFREQ_ENTRY_INVALID;
+
+	max_support_idx = L7;
+
+	for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
+		exynos5250_volt_table[i] = asv_voltage_5250[i];
+}
+
+int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
+{
+	int i;
+	unsigned int tmp;
+	unsigned long rate;
+
+	set_volt_table();
+
+	cpu_clk = clk_get(NULL, "armclk");
+	if (IS_ERR(cpu_clk))
+		return PTR_ERR(cpu_clk);
+
+	moutcore = clk_get(NULL, "mout_cpu");
+	if (IS_ERR(moutcore))
+		goto err_moutcore;
+
+	mout_mpll = clk_get(NULL, "mout_mpll");
+	if (IS_ERR(mout_mpll))
+		goto err_mout_mpll;
+
+	rate = clk_get_rate(mout_mpll) / 1000;
+
+	mout_apll = clk_get(NULL, "mout_apll");
+	if (IS_ERR(mout_apll))
+		goto err_mout_apll;
+
+	for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
+
+		exynos5250_clkdiv_table[i].index = i;
+
+		tmp = __raw_readl(EXYNOS5_CLKDIV_CPU0);
+
+		tmp &= ~((0x7 << 0) | (0x7 << 4) | (0x7 << 8) |
+			(0x7 << 12) | (0x7 << 16) | (0x7 << 20) |
+			(0x7 << 24) | (0x7 << 28));
+
+		tmp |= ((clkdiv_cpu0_5250[i][0] << 0) |
+			(clkdiv_cpu0_5250[i][1] << 4) |
+			(clkdiv_cpu0_5250[i][2] << 8) |
+			(clkdiv_cpu0_5250[i][3] << 12) |
+			(clkdiv_cpu0_5250[i][4] << 16) |
+			(clkdiv_cpu0_5250[i][5] << 20) |
+			(clkdiv_cpu0_5250[i][6] << 24) |
+			(clkdiv_cpu0_5250[i][7] << 28));
+
+		exynos5250_clkdiv_table[i].clkdiv = tmp;
+
+		tmp = __raw_readl(EXYNOS5_CLKDIV_CPU1);
+
+		tmp &= ~((0x7 << 0) | (0x7 << 4));
+
+		tmp |= ((clkdiv_cpu1_5250[i][0] << 0) |
+			(clkdiv_cpu1_5250[i][1] << 4));
+
+		exynos5250_clkdiv_table[i].clkdiv1 = tmp;
+	}
+
+	info->mpll_freq_khz = rate;
+	/* 1000Mhz */
+	info->pm_lock_idx = L7;
+	/* 800Mhz */
+	info->pll_safe_idx = L9;
+	info->max_support_idx = max_support_idx;
+	info->min_support_idx = min_support_idx;
+	info->cpu_clk = cpu_clk;
+	info->volt_table = exynos5250_volt_table;
+	info->freq_table = exynos5250_freq_table;
+	info->set_freq = exynos5250_set_frequency;
+	info->need_apll_change = exynos5250_pms_change;
+
+	return 0;
+
+err_mout_apll:
+	clk_put(mout_mpll);
+err_mout_mpll:
+	clk_put(moutcore);
+err_moutcore:
+	clk_put(cpu_clk);
+
+	pr_err("%s: failed initialization\n", __func__);
+	return -EINVAL;
+}
+EXPORT_SYMBOL(exynos5250_cpufreq_init);
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Fri Mar  9 06:57:21 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Fri, 9 Mar 2012 12:57:21 +0100
Subject: [PATCH v2 01/13] dmaengine: imx-dma: merge old dma-v1.c with
 imx-dma.c
In-Reply-To: <20120309110028.GB3852@pengutronix.de>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
 <1331130825-14947-2-git-send-email-javier.martin@vista-silicon.com>
 <20120309110028.GB3852@pengutronix.de>
Message-ID: <CACKLOr0QOhy9-GbEOeU0ExYwDrcoPKcv2=W8-4hT6vM5oCOyBQ@mail.gmail.com>

On 9 March 2012 12:00, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Wed, Mar 07, 2012 at 03:33:33PM +0100, Javier Martin wrote:
>> It is mainly a simple merge changing the prefix of some
>> functions to fit the imx-dma namings.
>>
>> As there are no users of the old dma-v1.c api we can safely
>> remove this file.
>>
>> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
>> ---
>> @@ -633,11 +1127,8 @@ static int __exit imxdma_remove(struct platform_device *pdev)
>>
>> ? ? ? ? ?dma_async_device_unregister(&imxdma->dma_device);
>>
>> - ? ? for (i = 0; i < MAX_DMA_CHANNELS; i++) {
>> - ? ? ? ? ? ? struct imxdma_channel *imxdmac = &imxdma->channel[i];
>> -
>> - ? ? ? ? ? ? ?imx_dma_free(imxdmac->imxdma_channel);
>> - ? ? }
>> + ? ? for (i = 0; i < MAX_DMA_CHANNELS; i++)
>> + ? ? ? ? ? ? free_irq(MX2x_INT_DMACH0 + i, NULL);
>
> This lacks a test for i.MX1/21/27. The above is correct for i.MX21/27,
> but on i.MX1 you have to free MX1_DMA_INT/MX1_DMA_ERR.

This series has only been tested for i.MX27. So, to those reviewing
the code, please pay special attention to i.MX1 part.

Sascha, thank you for your comment, I will fix it for the next version.

Regards.
-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From javier.martin at vista-silicon.com  Fri Mar  9 07:04:36 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Fri, 9 Mar 2012 13:04:36 +0100
Subject: [PATCH v2 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <20120309105645.GA3852@pengutronix.de>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
 <20120309105645.GA3852@pengutronix.de>
Message-ID: <CACKLOr3Y9BW_pMUnr6q4eH2c+2=jQ2WHEjWprb=O5wFrS9=T=A@mail.gmail.com>

Hi Sascha,
thank you for your time.

On 9 March 2012 11:56, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Wed, Mar 07, 2012 at 03:33:32PM +0100, Javier Martin wrote:
>> The following series have to be applied on top of the following patches:
>> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
>> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
>>
>> As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
>> is deprecated and no new patches are accepted for it.
>>
>> This series merges this code into the imx-dma.c dmaengine driver.
>>
>> Changes since v1:
>> ?- Merge patch 14 with 01.
>> ?- Add a proper changelog to each patch of the series.
>>
>> [PATCH v2 01/13] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
>> [PATCH v2 02/13] dmaengine: imx-dma: remove data member from internal structure.
>> [PATCH v2 03/13] dmaengine: imx-dma: remove dma_mode member of internal structure.
>> [PATCH v2 04/13] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
>> [PATCH v2 05/13] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
>> [PATCH v2 06/13] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
>> [PATCH v2 07/13] dmaengine: imx-dma: remove sg member from internal structure.
>> [PATCH v2 08/13] dmaengine: imx-dma: remove 'in_use' field of 'internal' structure.
>> [PATCH v2 09/13] dmaengine: imx-dma: remove 'resbytes' field of 'internal' structure.
>> [PATCH v2 10/13] dmaengine: imx-dma: remove internal structure.
>> [PATCH v2 11/13] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
>> [PATCH v2 12/13] dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and 'dma_clk'.
>> [PATCH v2 13/13] dmaengine: imx-dma: use 'dev_dbg' and 'dev_warn' for messages.
>
> I didn't look at the individual patches but only on the end result and
> overall it looks good. There are several things left for further cleanup:
>
> - use resources for irq and base address
> - use platform device id rather than cpu_is_* to distinguish
> ?between the different device types.
> - request_irq for i.MX21/27 in alloc_chan_resources instead in probe
> - Use all available channels. In the time we had dmaengine users and
> ?legacy API users 8 channels were reserved for the old API and 8
> ?channels for the dmaengine API.
>
> I think the first three points can be done in a later series, the last
> one should be trivial to fix now.

I agree. Let me fix the last issue you mention in a v3 of the involved patch.

> Some comments follow to the individual patches.
>
> And, oh:
>
> Tested-by: Sascha Hauer <s.hauer at pengutronix.de

Cool. Did you test it for any other platform than i.MX27?

Regards.
-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From kgene.kim at samsung.com  Sun Mar 11 05:03:41 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 01:03:41 -0800
Subject: [GIT PULL v2 4/4] Samsung devel-dma for v3.4
Message-ID: <4F5C6A6D.9010400@samsung.com>

Hi Arnd, Olof,

I rebased devel-samsung-dma on top of new next-exynos-clock as per 
Olof's suggestion.

Please pull it from:
  git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/devel-samsung-dma

If any problems, please let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit 44b2cef5ae6da48523fa634230ca66107110a7dd:

   ARM: EXYNOS: Add clock register addresses for EXYNOS4X12 bus devfreq 
driver (2012-03-10 22:30:32 -0800)

are available in the git repository at:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/devel-samsung-dma

Boojin Kim (2):
       ARM: EXYNOS: Enable MDMA driver
       ARM: EXYNOS: add support DMA for EXYNOS4X12 SoC

Tushar Behera (1):
       ARM: EXYNOS: Add apb_pclk clkdev entry for mdma1

  arch/arm/mach-exynos/Kconfig                   |    3 +
  arch/arm/mach-exynos/clock-exynos4.c           |    9 ++
  arch/arm/mach-exynos/dma.c                     |  117 
++++++++++++++++++++++--
  arch/arm/mach-exynos/include/mach/irqs.h       |    2 +
  arch/arm/mach-exynos/include/mach/map.h        |    3 +-
  arch/arm/plat-samsung/include/plat/dma-pl330.h |   16 +++
  6 files changed, 141 insertions(+), 9 deletions(-)



From alan at signal11.us  Sat Mar 10 18:14:41 2012
From: alan at signal11.us (Alan Ott)
Date: Sat, 10 Mar 2012 18:14:41 -0500
Subject: [PATCH v2 0/1] ARM: AT91: cleanup patches from Arnd Bergmann
In-Reply-To: <1331405049-3186-1-git-send-email-alan@signal11.us>
References: <1331405049-3186-1-git-send-email-alan@signal11.us>
Message-ID: <1331421281-11570-1-git-send-email-alan@signal11.us>

Version 2 of the patchset.
	* NO_IOPORT for RM9200 patch has been removed.
	* Hopefully all the right people are on this one.

Arnd Bergmann (1):
  ARM: at91: Use proper __iomem annotations

 arch/arm/mach-at91/at91rm9200.c            |    2 +-
 arch/arm/mach-at91/include/mach/hardware.h |    4 ++++
 arch/arm/mach-at91/setup.c                 |    4 ++--
 3 files changed, 7 insertions(+), 3 deletions(-)



From kgene.kim at samsung.com  Sun Mar 11 04:32:16 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 00:32:16 -0800
Subject: [GIT PULL v2] Samsung cleanup EXYNOS clock for v3.4
Message-ID: <4F5C6310.5010402@samsung.com>

Hi Arnd, Olof,

I rebased cleanup-exynos-clock on top of cleanup-use-static as per 
Olof's suggestion.

Please pull it from:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/cleanup-exynos-clock

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit c15a04338b5a6d4305d107a5b6c0cd43418b7f3e:

   Merge branch 'next/cleanup-use-static' into next/cleanup-exynos-clock 
(2012-03-10 22:21:36 -0800)

are available in the git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/cleanup-exynos-clock

Jaecheol Lee (1):
       ARM: EXYNOS: add clock registers for exynos4x12-cpufreq

Kukjin Kim (4):
       ARM: EXYNOS: replace clock.c for other new EXYNOS SoCs
       ARM: EXYNOS: use static declaration on regarding clock
       ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock
       PM / devfreq: update the name of EXYNOS clock register

MyungJoo Ham (2):
       PM / devfreq: update the name of EXYNOS clock registers that were 
omitted
       ARM: EXYNOS: Add clock register addresses for EXYNOS4X12 bus 
devfreq driver

  arch/arm/mach-exynos/Makefile                     |    3 +-
  arch/arm/mach-exynos/clock-exynos4.c              | 1563 
++++++++++++++++++++
  arch/arm/mach-exynos/clock-exynos4.h              |   30 +
  arch/arm/mach-exynos/clock-exynos4210.c           |   46 +-
  arch/arm/mach-exynos/clock-exynos4212.c           |   30 +-
  arch/arm/mach-exynos/clock.c                      | 1564 
---------------------
  arch/arm/mach-exynos/common.h                     |    9 +
  arch/arm/mach-exynos/include/mach/exynos4-clock.h |   43 -
  arch/arm/mach-exynos/include/mach/regs-clock.h    |  416 +++---
  arch/arm/mach-exynos/pm.c                         |   40 +-
  drivers/devfreq/exynos4_bus.c                     |  230 ++--
  11 files changed, 2009 insertions(+), 1965 deletions(-)
  create mode 100644 arch/arm/mach-exynos/clock-exynos4.c
  create mode 100644 arch/arm/mach-exynos/clock-exynos4.h
  delete mode 100644 arch/arm/mach-exynos/clock.c
  delete mode 100644 arch/arm/mach-exynos/include/mach/exynos4-clock.h


From thomas.abraham at linaro.org  Sun Mar 11 08:46:03 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sun, 11 Mar 2012 18:16:03 +0530
Subject: [PATCH 3/5] ARM: Exynos4: Add pinctrl devices and pin maps
In-Reply-To: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1331469965-28846-4-git-send-email-thomas.abraham@linaro.org>

Add the three pinctrl platform devices and the pin maps for Exynos4.

Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/Kconfig              |    1 +
 arch/arm/mach-exynos/Makefile             |    1 +
 arch/arm/mach-exynos/common.h             |    6 ++
 arch/arm/mach-exynos/dev-pinctrl.c        |  115 +++++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h |    3 +
 5 files changed, 126 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/dev-pinctrl.c

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index c49d450..3e6a1cd 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -18,6 +18,7 @@ choice
 config ARCH_EXYNOS4
 	bool "SAMSUNG EXYNOS4"
 	select HAVE_SMP
+	select PINCTRL
 	select MIGHT_HAVE_CACHE_L2X0
 	help
 	  Samsung EXYNOS4 SoCs based systems
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 6fd8dd9..dbac5f9 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)	+= dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
 obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o
+obj-$(CONFIG_PINCTRL_SAMSUNG)		+= dev-pinctrl.o
 
 obj-$(CONFIG_ARCH_EXYNOS)		+= setup-i2c0.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)	+= setup-fimc.o
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 677b546..64f3c57 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -52,4 +52,10 @@ void exynos4212_register_clocks(void);
 #define exynos4212_register_clocks()
 #endif
 
+#ifdef CONFIG_PINCTRL_SAMSUNG
+extern int exynos4210_pinctrl_register_def_mappings(void);
+#else
+#define exynos4210_pinctrl_register_def_mappings()
+#endif
+
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/dev-pinctrl.c b/arch/arm/mach-exynos/dev-pinctrl.c
new file mode 100644
index 0000000..d909052
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-pinctrl.c
@@ -0,0 +1,115 @@
+/*
+ * platform device for all the instances of pinctrl.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/pinctrl/machine.h>
+
+#include <plat/devs.h>
+#include <plat/pinctrl.h>
+
+#include <mach/map.h>
+
+static struct resource exynos4_pinctrl_resource0[] = {
+	[0] = {
+		.start  = EXYNOS4_PA_GPIO1,
+		.end    = EXYNOS4_PA_GPIO1 + SZ_4K - 1,
+		.flags  = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start  = IRQ_GPIO_XA,
+		.end    = IRQ_GPIO_XA,
+		.flags  = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device exynos4_pinctrl0 = {
+	.name		= "exynos4-pinctrl",
+	.id		= 0,
+	.resource	= exynos4_pinctrl_resource0,
+	.num_resources	= ARRAY_SIZE(exynos4_pinctrl_resource0),
+};
+
+static struct resource exynos4_pinctrl_resource1[] = {
+	[0] = {
+		.start  = EXYNOS4_PA_GPIO2,
+		.end    = EXYNOS4_PA_GPIO2 + SZ_4K - 1,
+		.flags  = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start  = IRQ_GPIO_XB,
+		.end    = IRQ_GPIO_XB,
+		.flags  = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device exynos4_pinctrl1 = {
+	.name		= "exynos4-pinctrl",
+	.id		= 1,
+	.resource	= exynos4_pinctrl_resource1,
+	.num_resources	= ARRAY_SIZE(exynos4_pinctrl_resource1),
+};
+
+static struct resource exynos4_pinctrl_resource2[] = {
+	[0] = {
+		.start  = EXYNOS4_PA_GPIO3,
+		.end    = EXYNOS4_PA_GPIO3 + SZ_4K - 1,
+		.flags  = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device exynos4_pinctrl2 = {
+	.name		= "exynos4-pinctrl",
+	.id		= 2,
+	.resource	= exynos4_pinctrl_resource2,
+	.num_resources	= ARRAY_SIZE(exynos4_pinctrl_resource2),
+};
+
+/* pin config options. todo: add other options here. */
+static unsigned long pcfg_pu_drv3[] __initdata = {
+	PINCTRL_CFG_PACK(PUD_UP, DRV_4X),
+};
+
+static unsigned long pcfg_pn_drv3[] __initdata = {
+	PINCTRL_CFG_PACK(PUD_NONE, DRV_4X),
+};
+
+/* Exynos4210 SoC default pin-maps reusable by Exynos4210 based boards*/
+
+static struct pinctrl_map __initdata exynos4210_sdhci2_8bit_map[] = {
+	PIN_MAP_MUX_GROUP("exynos4-sdhci.2", "sdhci-pcfg8", "exynos4-pinctrl.1", "sdhci2_ctrl_grp", "sdhci2-mux"),
+	PIN_MAP_MUX_GROUP("exynos4-sdhci.2", "sdhci-pcfg8", "exynos4-pinctrl.1", "sdhci2_cd_grp", "sdhci2-mux"),
+	PIN_MAP_MUX_GROUP("exynos4-sdhci.2", "sdhci-pcfg8", "exynos4-pinctrl.1", "sdhci2_4bit_grp", "sdhci2-mux"),
+	PIN_MAP_MUX_GROUP("exynos4-sdhci.2", "sdhci-pcfg8", "exynos4-pinctrl.1", "sdhci2_8bit_grp", "sdhci2-mux"),
+	PIN_MAP_CONFIGS_GROUP("exynos4-sdhci.2", "sdhci-pcfg8", "exynos4-pinctrl.1", "sdhci2_ctrl_grp", pcfg_pn_drv3),
+	PIN_MAP_CONFIGS_GROUP("exynos4-sdhci.2", "sdhci-pcfg8", "exynos4-pinctrl.1", "sdhci2_cd_grp", pcfg_pu_drv3),
+	PIN_MAP_CONFIGS_GROUP("exynos4-sdhci.2", "sdhci-pcfg8", "exynos4-pinctrl.1", "sdhci2_4bit_grp", pcfg_pu_drv3),
+	PIN_MAP_CONFIGS_GROUP("exynos4-sdhci.2", "sdhci-pcfg8", "exynos4-pinctrl.1", "sdhci2_8bit_grp", pcfg_pu_drv3),
+};
+
+static struct pinctrl_map __initdata exynos4210_sdhci2_4bit_map[] = {
+	PIN_MAP_MUX_GROUP("exynos4-sdhci.2", "sdhci-pcfg4", "exynos4-pinctrl.1", "sdhci2_ctrl_grp", "sdhci2-mux"),
+	PIN_MAP_MUX_GROUP("exynos4-sdhci.2", "sdhci-pcfg4", "exynos4-pinctrl.1", "sdhci2_cd_grp", "sdhci2-mux"),
+	PIN_MAP_MUX_GROUP("exynos4-sdhci.2", "sdhci-pcfg4", "exynos4-pinctrl.1", "sdhci2_4bit_grp", "sdhci2-mux"),
+	PIN_MAP_CONFIGS_GROUP("exynos4-sdhci.2", "sdhci-pcfg4", "exynos4-pinctrl.1", "sdhci2_ctrl_grp", pcfg_pn_drv3),
+	PIN_MAP_CONFIGS_GROUP("exynos4-sdhci.2", "sdhci-pcfg4", "exynos4-pinctrl.1", "sdhci2_cd_grp", pcfg_pu_drv3),
+	PIN_MAP_CONFIGS_GROUP("exynos4-sdhci.2", "sdhci-pcfg4", "exynos4-pinctrl.1", "sdhci2_4bit_grp", pcfg_pu_drv3),
+};
+
+int __init exynos4210_pinctrl_register_def_mappings(void)
+{
+	pinctrl_register_mappings(exynos4210_sdhci2_8bit_map, ARRAY_SIZE(exynos4210_sdhci2_8bit_map));
+	pinctrl_register_mappings(exynos4210_sdhci2_4bit_map, ARRAY_SIZE(exynos4210_sdhci2_4bit_map));
+	return 0;
+}
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 2dd5267..760445f 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -133,6 +133,9 @@ extern struct platform_device exynos4_device_pcm2;
 extern struct platform_device exynos4_device_pd[];
 extern struct platform_device exynos4_device_spdif;
 extern struct platform_device exynos4_device_sysmmu;
+extern struct platform_device exynos4_pinctrl0;
+extern struct platform_device exynos4_pinctrl1;
+extern struct platform_device exynos4_pinctrl2;
 
 extern struct platform_device samsung_asoc_dma;
 extern struct platform_device samsung_asoc_idma;
-- 
1.6.6.rc2



From javier.martin at vista-silicon.com  Fri Mar  9 10:20:43 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:43 +0100
Subject: [PATCH v3 07/13] dmaengine: imx-dma: remove sg member from internal
 structure.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-8-git-send-email-javier.martin@vista-silicon.com>

This member is redundant, because it is already present in
descriptor structure. Removing it will make further removing
of 'internal' structure easier.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   42 ++++++++++++++++++------------------------
 1 files changed, 18 insertions(+), 24 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index e8b6efa..dba62bc 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -128,7 +128,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	struct scatterlist *sg;
 	unsigned int resbytes;
 
 	int in_use;
@@ -276,11 +275,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
-		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
-		if (imxdmac->internal.sg) {
+			d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+		d->sg = sg_next(d->sg);
+		if (d->sg) {
 			u32 tmp;
-			imxdma_sg_next(d, imxdmac->internal.sg);
+			imxdma_sg_next(d, d->sg);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -317,7 +316,6 @@ static void imxdma_watchdog(unsigned long data)
 
 	imx_dmav1_writel(0, DMA_CCR(channel));
 	imxdmac->internal.in_use = 0;
-	imxdmac->internal.sg = NULL;
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -385,24 +383,23 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
-	if (imxdma->sg) {
-		u32 tmp;
-		imxdma->sg = sg_next(imxdma->sg);
-
-		if (imxdma->sg) {
+	spin_lock(&imxdmac->lock);
+	if (list_empty(&imxdmac->ld_active)) {
+		spin_unlock(&imxdmac->lock);
+		goto out;
+	}
 
-			spin_lock(&imxdmac->lock);
-			if (list_empty(&imxdmac->ld_active)) {
-				spin_unlock(&imxdmac->lock);
-				goto out;
-			}
+	desc = list_first_entry(&imxdmac->ld_active,
+				struct imxdma_desc,
+				node);
+	spin_unlock(&imxdmac->lock);
 
-			desc = list_first_entry(&imxdmac->ld_active,
-						struct imxdma_desc,
-						node);
-			spin_unlock(&imxdmac->lock);
+	if (desc->sg) {
+		u32 tmp;
+		desc->sg = sg_next(desc->sg);
 
-			imxdma_sg_next(desc, imxdma->sg);
+		if (desc->sg) {
+			imxdma_sg_next(desc, desc->sg);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -475,8 +472,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		imxdmac->internal.sg = NULL;
-
 		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
 		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
 		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
@@ -492,7 +487,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		imxdmac->internal.sg = d->sg;
 		imxdmac->internal.resbytes = d->len;
 
 		if (d->direction == DMA_DEV_TO_MEM) {
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Fri Mar  9 10:20:48 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:48 +0100
Subject: [PATCH v3 12/13] dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and
 'dma_clk'.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-13-git-send-email-javier.martin@vista-silicon.com>

These global variables are integrated into the dmaengine structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |  169 +++++++++++++++++++++++++++----------------------
 1 files changed, 93 insertions(+), 76 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 7b67371..c4a039c 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -158,6 +158,8 @@ struct imxdma_engine {
 	struct device			*dev;
 	struct device_dma_parameters	dma_parms;
 	struct dma_device		dma_device;
+	void __iomem			*base;
+	struct clk			*dma_clk;
 	struct imxdma_channel		channel[IMX_DMA_CHANNELS];
 };
 
@@ -179,18 +181,17 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 	return false;
 }
 
-/* TODO: put this inside any struct */
-static void __iomem *imx_dmav1_baseaddr;
-static struct clk *dma_clk;
 
-static void imx_dmav1_writel(unsigned val, unsigned offset)
+
+static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
+			     unsigned offset)
 {
-	__raw_writel(val, imx_dmav1_baseaddr + offset);
+	__raw_writel(val, imxdma->base + offset);
 }
 
-static unsigned imx_dmav1_readl(unsigned offset)
+static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
 {
-	return __raw_readl(imx_dmav1_baseaddr + offset);
+	return __raw_readl(imxdma->base + offset);
 }
 
 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
@@ -207,6 +208,7 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 static inline int imxdma_sg_next(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	struct scatterlist *sg = d->sg;
 	unsigned long now;
 
@@ -215,17 +217,19 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 		d->len -= now;
 
 	if (d->direction == DMA_DEV_TO_MEM)
-		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, sg->dma_address,
+				 DMA_DAR(imxdmac->channel));
 	else
-		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, sg->dma_address,
+				 DMA_SAR(imxdmac->channel));
 
-	imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+	imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
 
 	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
 		"size 0x%08x\n", imxdmac->channel,
-		 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
-		 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
-		 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
+		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
+		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
 
 	return now;
 }
@@ -233,6 +237,7 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 static void imxdma_enable_hw(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -240,10 +245,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 	local_irq_save(flags);
 
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
-		CCR_ACRPT, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
+			 ~(1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
+			 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
 			d->sg && imxdma_hw_chain(imxdmac)) {
@@ -251,9 +257,9 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		if (d->sg) {
 			u32 tmp;
 			imxdma_sg_next(d);
-			tmp = imx_dmav1_readl(DMA_CCR(channel));
-			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
-				DMA_CCR(channel));
+			tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
+			imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
+					 DMA_CCR(channel));
 		}
 	}
 
@@ -262,6 +268,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 {
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -271,19 +278,21 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 		del_timer(&imxdmac->watchdog);
 
 	local_irq_save(flags);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
-			DMA_CCR(channel));
-	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
+			 (1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
+			 ~CCR_CEN, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
 	local_irq_restore(flags);
 }
 
 static void imxdma_watchdog(unsigned long data)
 {
 	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 
-	imx_dmav1_writel(0, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -297,37 +306,37 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 	int i, disr;
 	int errcode;
 
-	disr = imx_dmav1_readl(DMA_DISR);
+	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
-	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
-		   imx_dmav1_readl(DMA_DRTOSR) |
-		   imx_dmav1_readl(DMA_DSESR)  |
-		   imx_dmav1_readl(DMA_DBOSR);
+	err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
+		   imx_dmav1_readl(imxdma, DMA_DRTOSR) |
+		   imx_dmav1_readl(imxdma, DMA_DSESR)  |
+		   imx_dmav1_readl(imxdma, DMA_DBOSR);
 
 	if (!err_mask)
 		return IRQ_HANDLED;
 
-	imx_dmav1_writel(disr & err_mask, DMA_DISR);
+	imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
 
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (!(err_mask & (1 << i)))
 			continue;
 		errcode = 0;
 
-		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBTOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
 			errcode |= IMX_DMA_ERR_BURST;
 		}
-		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DRTOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
 			errcode |= IMX_DMA_ERR_REQUEST;
 		}
-		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DSESR);
+		if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
 			errcode |= IMX_DMA_ERR_TRANSFER;
 		}
-		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
 			errcode |= IMX_DMA_ERR_BUFFER;
 		}
 		/* Tasklet error handler */
@@ -345,6 +354,7 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 
 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
@@ -366,7 +376,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		if (desc->sg) {
 			imxdma_sg_next(desc);
 
-			tmp = imx_dmav1_readl(DMA_CCR(chno));
+			tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
 
 			if (imxdma_hw_chain(imxdmac)) {
 				/* FIXME: The timeout should probably be
@@ -376,13 +386,14 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 					jiffies + msecs_to_jiffies(500));
 
 				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
-				imx_dmav1_writel(tmp, DMA_CCR(chno));
+				imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 			} else {
-				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+				imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
+						 DMA_CCR(chno));
 				tmp |= CCR_CEN;
 			}
 
-			imx_dmav1_writel(tmp, DMA_CCR(chno));
+			imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 
 			if (imxdma_chan_is_doing_cyclic(imxdmac))
 				/* Tasklet progression */
@@ -398,7 +409,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 	}
 
 out:
-	imx_dmav1_writel(0, DMA_CCR(chno));
+	imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
 	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
@@ -411,12 +422,12 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 	if (cpu_is_mx21() || cpu_is_mx27())
 		imxdma_err_handler(irq, dev_id);
 
-	disr = imx_dmav1_readl(DMA_DISR);
+	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
 	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
 		     disr);
 
-	imx_dmav1_writel(disr, DMA_DISR);
+	imx_dmav1_writel(imxdma, disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (disr & (1 << i))
 			dma_irq_handle_channel(&imxdma->channel[i]);
@@ -433,12 +444,12 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
-		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
-		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+		imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
 			 DMA_CCR(imxdmac->channel));
 
-		imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
 
 		dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
 			"dma_length=%d\n", __func__, imxdmac->channel,
@@ -449,9 +460,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
 		if (d->direction == DMA_DEV_TO_MEM) {
-			imx_dmav1_writel(imxdmac->per_address,
+			imx_dmav1_writel(imxdma, imxdmac->per_address,
 					 DMA_SAR(imxdmac->channel));
-			imx_dmav1_writel(imxdmac->ccr_from_device,
+			imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
 					 DMA_CCR(imxdmac->channel));
 
 			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -459,9 +470,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 				__func__, imxdmac->channel, d->sg, d->sgcount,
 				d->len, imxdmac->per_address);
 		} else if (d->direction == DMA_MEM_TO_DEV) {
-			imx_dmav1_writel(imxdmac->per_address,
+			imx_dmav1_writel(imxdma, imxdmac->per_address,
 					 DMA_DAR(imxdmac->channel));
-			imx_dmav1_writel(imxdmac->ccr_to_device,
+			imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
 					 DMA_CCR(imxdmac->channel));
 
 			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -526,6 +537,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct dma_slave_config *dmaengine_cfg = (void *)arg;
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	unsigned long flags;
 	unsigned int mode = 0;
 
@@ -571,12 +583,12 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		imxdmac->ccr_to_device =
 			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
 			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
-		imx_dmav1_writel(imxdmac->dma_request,
+		imx_dmav1_writel(imxdma, imxdmac->dma_request,
 				 DMA_RSSR(imxdmac->channel));
 
 		/* Set burst length */
-		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
-				 DMA_BLR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, imxdmac->watermark_level *
+				imxdmac->word_size, DMA_BLR(imxdmac->channel));
 
 		return 0;
 	default:
@@ -861,27 +873,35 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	struct imxdma_engine *imxdma;
 	int ret, i;
 
-	if (cpu_is_mx1())
-		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
-	else if (cpu_is_mx21())
-		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
-	else if (cpu_is_mx27())
-		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
-	else
+
+	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
+	if (!imxdma)
+		return -ENOMEM;
+
+	if (cpu_is_mx1()) {
+		imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+	} else if (cpu_is_mx21()) {
+		imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+	} else if (cpu_is_mx27()) {
+		imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+	} else {
+		kfree(imxdma);
 		return 0;
+	}
 
-	dma_clk = clk_get(NULL, "dma");
-	if (IS_ERR(dma_clk))
-		return PTR_ERR(dma_clk);
-	clk_enable(dma_clk);
+	imxdma->dma_clk = clk_get(NULL, "dma");
+	if (IS_ERR(imxdma->dma_clk))
+		return PTR_ERR(imxdma->dma_clk);
+	clk_enable(imxdma->dma_clk);
 
 	/* reset DMA module */
-	imx_dmav1_writel(DCR_DRST, DMA_DCR);
+	imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
 
 	if (cpu_is_mx1()) {
 		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
 		if (ret) {
 			pr_crit("Can't register IRQ for DMA\n");
+			kfree(imxdma);
 			return ret;
 		}
 
@@ -889,22 +909,19 @@ static int __init imxdma_probe(struct platform_device *pdev)
 		if (ret) {
 			pr_crit("Can't register ERRIRQ for DMA\n");
 			free_irq(MX1_DMA_INT, NULL);
+			kfree(imxdma);
 			return ret;
 		}
 	}
 
 	/* enable DMA module */
-	imx_dmav1_writel(DCR_DEN, DMA_DCR);
+	imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
 
 	/* clear all interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
 
 	/* disable interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
-	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
-	if (!imxdma)
-		return -ENOMEM;
+	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
 
 	INIT_LIST_HEAD(&imxdma->dma_device.channels);
 
-- 
1.7.0.4



From m.szyprowski at samsung.com  Fri Mar  9 09:53:32 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 09 Mar 2012 15:53:32 +0100
Subject: [PATCH] ARM: dma-mapping: fix calculation of iova bitmap size
In-Reply-To: <011701ccfc83$78030180$68090480$%szyprowski@samsung.com>
References: <011701ccfc83$78030180$68090480$%szyprowski@samsung.com>
Message-ID: <1331304812-10386-1-git-send-email-m.szyprowski@samsung.com>

Fix calculation of iova address space for IOMMU-aware dma mapping.

Reported-by: Krishna Reddy <vdumpa at nvidia.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/mm/dma-mapping.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index ea5a0ad..f0f600a 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1601,11 +1601,14 @@ struct dma_iommu_mapping *
 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
 			 int order)
 {
-	unsigned int count = (size >> PAGE_SHIFT) - order;
+	unsigned int count = size >> (PAGE_SHIFT + order);
 	unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
 	struct dma_iommu_mapping *mapping;
 	int err = -ENOMEM;
 
+	if (!count)
+		return ERR_PTR(-EINVAL);
+
 	mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
 	if (!mapping)
 		goto err;
-- 
1.7.1.569.g6f426



From thomas.abraham at linaro.org  Sun Mar 11 08:46:00 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sun, 11 Mar 2012 18:16:00 +0530
Subject: [PATCH 0/5] pinctrl: add new Samsung pinctrl driver and add Exynos4
 support
Message-ID: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>

This patch series adds new pinctrl driver for Samsung SoC's. The driver supports
a gpiolib interface as well since Samsung SoC's have a combined pinmux/pinctrl
and gpio controller.

The intention of this driver is to replace the existing gpiolib driver and
provide drivers pinctrl subsystem interface to configure the pins/mux instead
of existing platform callbacks. At this point, the pinmux and pinconfig
functionality fully supported and gpiolib is partially supported. Additional
work is required to add gpio interrupts and wakeup interrupts support.

Hence, this is not ready for merge yet. The first two patches can be looked at
in detail. The last three patches are mainly work-in-progress and can be
glanced over.

The first patch adds a new pinctrl driver for Samsung. It provides interfaces
to the pinctrl and gpiolib subsystems. This driver provides a common framework
for all Samsung SoC's to enable the pinctrl and gpiolib support. The driver
accepts the information about pins, groups, functions and gpio chips using
the driver data.

The second patch adds information about the pins, groups, functions and gpio
chips for the Exynos4210 SoC's. This information is supplied to the Samsung
pinctrl driver using driver data. The pinctrl driver registers this information
with the pinctrl and gpiolib subsystems. Note: The information about the
commonly used groups and functions are added, this list is not exhaustive.

The third patch add support for all three pinctrl devices on Exynos4210 SoC.
It also adds a minimal common reusable pin maps for boards which are based on
Exynos4210 as an example. The pin maps is listed only for the sdhci2 controller
for now and this list needs to be expanded.

The fourth patch enables pinctrl driver support for Exynos4210 based Origen
board as an example of using pinctrl driver.

The fifth patch updates the sdhci-s3c driver to use the pinctrl driver
interface to setup the pin mux and config settings. This is only intended
to be a an example of how to replace the platform callbacks with the
pinctrl driver call.

This patchset is based on
http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git

with all patches merged from
http://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git [for-next]

and tested working of sdhci2 controller on Origen board.

Thomas Abraham (5):
  pinctrl: add samsung pinctrl and gpiolib driver
  pinctrl: add exynos4 specific pins, groups, functions and gpio chip data
  ARM: Exynos4: Add pinctrl devices and pin maps
  ARM: Exynos: Enable pinctrl driver support for Origen board
  mmc: sdhci-s3c: setup pins using pinctrl interface

 arch/arm/mach-exynos/Kconfig                 |    1 +
 arch/arm/mach-exynos/Makefile                |    1 +
 arch/arm/mach-exynos/common.h                |    6 +
 arch/arm/mach-exynos/dev-pinctrl.c           |  115 +++++
 arch/arm/mach-exynos/mach-origen.c           |    7 +
 arch/arm/plat-samsung/include/plat/devs.h    |    3 +
 arch/arm/plat-samsung/include/plat/pinctrl.h |   35 ++
 drivers/mmc/host/sdhci-s3c.c                 |   15 +-
 drivers/pinctrl/Kconfig                      |   10 +
 drivers/pinctrl/Makefile                     |    2 +
 drivers/pinctrl/pinctrl-exynos4.c            |  522 +++++++++++++++++++++++
 drivers/pinctrl/pinctrl-samsung.c            |  589 ++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-samsung.h            |  143 +++++++
 13 files changed, 1447 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-exynos/dev-pinctrl.c
 create mode 100644 arch/arm/plat-samsung/include/plat/pinctrl.h
 create mode 100644 drivers/pinctrl/pinctrl-exynos4.c
 create mode 100644 drivers/pinctrl/pinctrl-samsung.c
 create mode 100644 drivers/pinctrl/pinctrl-samsung.h



From javier.martin at vista-silicon.com  Fri Mar  9 10:20:45 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:45 +0100
Subject: [PATCH v3 09/13] dmaengine: imx-dma: remove 'resbytes' field of
 'internal' structure.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-10-git-send-email-javier.martin@vista-silicon.com>

Use per-descriptor 'len' field to keep track of the remaining bytes
instead. This goes on the direction of eventually removing the
'internal' structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   11 +++--------
 1 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 8499f15..84ac93b 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -128,8 +128,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	unsigned int resbytes;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -231,12 +229,11 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
 static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
-	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	unsigned long now;
 
-	now = min(imxdma->resbytes, sg->length);
-	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
-		imxdma->resbytes -= now;
+	now = min(d->len, sg->length);
+	if (d->len != IMX_DMA_LENGTH_LOOP)
+		d->len -= now;
 
 	if (d->direction == DMA_DEV_TO_MEM)
 		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
@@ -478,8 +475,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		imxdmac->internal.resbytes = d->len;
-
 		if (d->direction == DMA_DEV_TO_MEM) {
 			imx_dmav1_writel(imxdmac->per_address,
 					 DMA_SAR(imxdmac->channel));
-- 
1.7.0.4



From kgene.kim at samsung.com  Sun Mar 11 04:05:40 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 00:05:40 -0800
Subject: [GIT PULL 2/4] Samsung devel-pd for v3.4
In-Reply-To: <201203102209.22451.rjw@sisk.pl>
References: <4F5B7C81.6080301@samsung.com>
 <CAOesGMjff3gVNJQ5FpJuSf+uvVDW8k22b+Xcikot-isM-4-6iw@mail.gmail.com>
 <201203102209.22451.rjw@sisk.pl>
Message-ID: <4F5C5CD4.7020804@samsung.com>

On 03/10/12 13:09, Rafael J. Wysocki wrote:
> Hi,
>
> On Saturday, March 10, 2012, Olof Johansson wrote:
>> Hi Rafael,
>>
>> The below series contains two patches that have been sent to you, and
>> that are sitting in the pm-domains branch.
>>
>> Two questions before I pull this into arm-soc:
>>
>> 1) Are you 100% sure this will be submitted to 3.4? And if so, will
>> you send it early during the merge window?
>
> Yes and yes.
>
>> 2) Are you 100% sure you will not rebase the branch into which you
>> pulled the v3.4-for-rafael branch?
>
> Yes, I am.
>
>> I am asking because if we pull this in, and you rebase between now and
>> when it's sent in, we're risking merge conflicts that will be painful
>> to resolve. We've been bitten by that from other dependencies in the
>> past so we're being careful.
>
> Sure, I understand that.
>
> As a general rule, topic braches in my tree whose names start with pm- are
> never rebased (exactly for this reason).
>
Hi,

Rafael, thanks.

Olof, please pull devel-samsung-pd from following:

git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/devel-samsung-pd

And if any problems, please let me know.
Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Sat Mar 10 11:08:45 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 08:08:45 -0800
Subject: [GIT PULL 3/4] Samsung devel-mmc for v3.4
Message-ID: <4F5B7C8D.5000805@samsung.com>

Hi Arnd, Olof

This is regarding Samsung mmc for v3.4.

As a note, v3.4-for-cjb branch is merged into mmc/mmc-next like following:
http://git.kernel.org/?p=linux/kernel/git/cjb/mmc.git;a=commit;h=fcd9bdae386753531a9cb6b2577359a83f4e121c

And others are accordingly changes on regarding mmc.

Please pull and if any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

   Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/devel-samsung-mmc

Jaehoon Chung (3):
       ARM: SAMSUNG: support the second capability for samsung-soc
       mmc: sdhci-s3c: add platform data for the second capability
       ARM: SAMSUNG: change the name from s3c-sdhci to exynos4-sdhci

Kukjin Kim (1):
       Merge branch 'v3.4-for-cjb' into next/devel-samsung-mmc

Thomas Abraham (6):
       mmc: sdhci-s3c: Remove usage of clk_type member in platform data
       ARM: EXYNOS: use 'exynos4-sdhci' as device name for sdhci controllers
       ARM: SAMSUNG: remove all uses of clk_type member in sdhci 
platform data
       mmc: sdhci-s3c: derive transfer width host capability from 
max_width in platform data
       mmc: sdhci-s3c: Keep a copy of platform data and use it
       mmc: sdhci-s3c: Add device tree support

  .../devicetree/bindings/mmc/samsung-sdhci.txt      |   70 ++++++
  arch/arm/mach-exynos/clock.c                       |   24 +-
  arch/arm/mach-exynos/common.c                      |    5 +
  arch/arm/mach-exynos/mach-armlex4210.c             |    3 -
  arch/arm/mach-exynos/mach-nuri.c                   |    7 +-
  arch/arm/mach-exynos/mach-origen.c                 |    2 -
  arch/arm/mach-exynos/mach-smdk4x12.c               |    2 -
  arch/arm/mach-exynos/mach-smdkv310.c               |    4 -
  arch/arm/mach-exynos/mach-universal_c210.c         |    4 +-
  arch/arm/plat-samsung/devs.c                       |    4 -
  arch/arm/plat-samsung/include/plat/sdhci.h         |   37 +++-
  arch/arm/plat-samsung/platformdata.c               |    4 +-
  drivers/mmc/host/sdhci-s3c.c                       |  238 
+++++++++++++++++++-
  13 files changed, 351 insertions(+), 53 deletions(-)
  create mode 100644 Documentation/devicetree/bindings/mmc/samsung-sdhci.txt


From kgene.kim at samsung.com  Sun Mar 11 04:13:53 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 00:13:53 -0800
Subject: [GIT PULL 3/4] Samsung devel-mmc for v3.4
In-Reply-To: <CAOesGMgx-86rUuOfjTN8BeYZD+S=04oj+N9u-m9dr8JQA1Oxiw@mail.gmail.com>
References: <4F5B7C8D.5000805@samsung.com>
 <CAOesGMgx-86rUuOfjTN8BeYZD+S=04oj+N9u-m9dr8JQA1Oxiw@mail.gmail.com>
Message-ID: <4F5C5EC1.7000102@samsung.com>


On 03/10/12 10:10, Olof Johansson wrote:
 > On 03/10/12 10:08, Olof Johansson wrote:
>> Hi,
>>
>> On Sat, Mar 10, 2012 at 8:08 AM, Kukjin Kim<kgene.kim at samsung.com>  wrote:
>>> Hi Arnd, Olof
>>>
>>> This is regarding Samsung mmc for v3.4.
>>>
>>> As a note, v3.4-for-cjb branch is merged into mmc/mmc-next like following:
>>> http://git.kernel.org/?p=linux/kernel/git/cjb/mmc.git;a=commit;h=fcd9bdae386753531a9cb6b2577359a83f4e121c
>>
>> Looking at this series, there's really only one patch that is not in
>> the mmc tree:
>>
>> ARM: SAMSUNG: change the name from s3c-sdhci to exynos4-sdhci
>>
>> And all it does is change the platform device string contents.
>>
>> Since there are no build-time dependencies between this and the MMC
>> change, I suggest you send only this patch so that we avoid having
>> merge dependencies where not strictly needed.
>>
>> Would that be OK with you? If so, please send a fresh pull request
>> with only the above change in it.
>>
>>
>Sorry, I misread the series when browsing it. Looks like there are two
 > more patches in it:
 >
 > mmc: sdhci-s3c: add platform data for the second capability
 > ARM: SAMSUNG: support the second capability for samsung-soc
 >
 > But the original suggestion remains, since those two seem to be
 > unrelated to the branch sent to Chris. So please resend with just
 > those patches, please?
 >
OK, I agree. Let me do it soon.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From linux at arm.linux.org.uk  Sat Mar 10 13:21:44 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 10 Mar 2012 18:21:44 +0000
Subject: [PATCH] pxa/hx4700: Reduce sleep mode power consumption by 35%
In-Reply-To: <1331403080.2319.YahooMailClassic@web29002.mail.ird.yahoo.com>
References: <1331403080.2319.YahooMailClassic@web29002.mail.ird.yahoo.com>
Message-ID: <20120310182144.GA20013@n2100.arm.linux.org.uk>

On Sat, Mar 10, 2012 at 06:11:20PM +0000, Paul Parsons wrote:
> Drive the two Bluetooth UART output GPIOs (GPIO43_BTUART_TXD,
> GPIO45_BTUART_RTS) LOW during sleep mode instead of HIGH. This
> reduces sleep mode power consumption from approximately 46 mA/h
> to approximately 30 mA/h.

What are you saying here?  I think you're confusing power with current.
Also, current is measured in amps, not amps per second (or a scaled
version of that.)

> Signed-off-by: Oliver Winker <oliver at oli1170.net>
> Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
> ---
> 
> Thanks to Oliver Winker for finding this.
> 
> diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c
> --- clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-04 01:08:09.000000000 +0000
> +++ linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c	2012-03-10 15:44:18.597238757 +0000
> @@ -97,9 +97,9 @@ static unsigned long hx4700_pin_config[]
>  
>  	/* BTUART */
>  	GPIO42_BTUART_RXD,
> -	GPIO43_BTUART_TXD,
> +	GPIO43_GPIO | MFP_AF2 | MFP_LPM_DRIVE_LOW,

I don't believe that's right.

This expands to:

	MFP_CFG_IN(GPIO43, AF0) | MFP_AF2 | MFP_LPM_DRIVE_LOW

and:

	(MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |
	(MFP_PIN(MFP_PIN_GPIO43) | MFP_AF0 | MFP_DIR_IN)
	| MFP_AF2 | MFP_LPM_DRIVE_LOW

Note the presence of both MFP_AF2 and MFP_AF0 in there.

The default for GPIO43_BTUART_TXD is:

	MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)

and I'd suggest defining a new GPIO43_BTUART_TXD_LPM_LOW to cover your
case.


From plagnioj at jcrosoft.com  Fri Mar  9 04:55:46 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 9 Mar 2012 10:55:46 +0100
Subject: [PATCH 2/5 v3] ARM: at91: sam9g20 add i2c DT support
In-Reply-To: <20120309052600.B13BA3E0649@localhost>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <1331196635-27203-2-git-send-email-plagnioj@jcrosoft.com>
 <20120309052600.B13BA3E0649@localhost>
Message-ID: <20120309095546.GL27213@game.jcrosoft.org>

On 22:26 Thu 08 Mar     , Grant Likely wrote:
> On Thu,  8 Mar 2012 09:50:32 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > For now on use i2c-gpio driver on the same pin as the hardware IP.
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> > Cc: devicetree-discuss at lists.ozlabs.org
> > ---
> > v3:
> > 
> > 	update i2c binding (Rob comments)
> > 
> > Best Regards,
> > J.
> >  arch/arm/boot/dts/at91sam9g20.dtsi |   13 +++++++++++++
> >  1 files changed, 13 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
> > index 4b0dc99..072b2da 100644
> > --- a/arch/arm/boot/dts/at91sam9g20.dtsi
> > +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
> > @@ -189,4 +189,17 @@
> >  			status = "disabled";
> >  		};
> >  	};
> > +
> > +	i2c-gpio at 0 {
> 
> i2c at 0
> 
> > +		compatible = "i2c-gpio";
> > +		gpios = <&pioA 23 0 /* sda */
> > +			 &pioA 24 0 /* scl */
> > +			>;
> > +		i2c-gpio,sda-open-drain;
> > +		i2c-gpio,scl-open-drain;
> > +		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		status = "disabled";
> > +	};
> 
> gpio-driven i2c busses are inherently board-specific.  Why is this
> in the SoC include file?
because they use the hw pin and all board will use the same as on some soc
(old) we can not use the hw IP
> 
> Otherwise I think this patch series looks okay.

Best Regards,
J.


From kgene.kim at samsung.com  Fri Mar  9 11:32:56 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 09 Mar 2012 08:32:56 -0800
Subject: [PATCH v3 0/4] ARM: Exynos4: Add irq domain and device tree
 support for wakeup interrupts
In-Reply-To: <1329912858-32750-1-git-send-email-thomas.abraham@linaro.org>
References: <1329912858-32750-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <4F5A30B8.6060801@samsung.com>

On 02/22/12 04:14, Thomas Abraham wrote:
> Changes since v2:
> - Reworked irq domain support based on v5 of the irq_domain generalization
>    patches.
>
> Changes since v1: (only patch 4/4 has changes)
> - Fixes based on Rob's comments:
>    a. Fixed the function prototype of exynos4_init_irq_eint(void)
>    b. Included interrupt-parent as an optional property for wakeup interrupt
>        controller node.
>
> Samsung Exynos4 includes 32 external wakeup interrupt sources. The first 16
> of these interrupts are connected to GIC SPI[31:16]. The last 16 of these
> interrupts are grouped together into one interrupt and connected to GIC
> SPI[32].
>
> This patchset adds irq domain and device tree support for these interrupts.
> Since there are users of fixed linux irq numbers of the external wakeup
> interrupts, the legacy mapping is used for the irq domain.
>
> This patchset is based on
> http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]
>
> with all irq_domain (v5) patches merged from
> http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]
>
> This patchset should be applied after applying the following patch.
> [PATCH] ARM: Exynos: Add irq domain and device tree support for interrupt combiner

Looks ok to me this series, but I lost above patch in my mail box.
Thomas, could you please send updated it so that I can apply this series?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

>
> Thomas Abraham (4):
>    ARM: Exynos4: Simplify EINT number to linux irq number translation
>    ARM: Exynos4: Add irq_domain support for gpio wakeup interrupts
>    ARM: Exynos4: Remove arch_initcall for wakeup interrupt initialization
>    ARM: Exynos4: Add device tree support for gpio wakeup interrupt controller
>
>   .../bindings/arm/samsung/wakeup-eint.txt           |   37 +++++
>   arch/arm/mach-exynos/common.c                      |  148 ++++++++++++--------
>   arch/arm/mach-exynos/include/mach/regs-gpio.h      |    4 +-
>   3 files changed, 131 insertions(+), 58 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt


From w.sang at pengutronix.de  Sat Mar 10 15:53:51 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Sat, 10 Mar 2012 21:53:51 +0100
Subject: [PATCH v5 3/3] USB: ohci-nxp: Support for LPC32xx
In-Reply-To: <20120310204955.GA14564@pengutronix.de>
References: <1331408166-11607-1-git-send-email-stigge@antcom.de>
 <1331408166-11607-4-git-send-email-stigge@antcom.de>
 <20120310204955.GA14564@pengutronix.de>
Message-ID: <20120310205351.GB14564@pengutronix.de>

On Sat, Mar 10, 2012 at 09:49:55PM +0100, Wolfram Sang wrote:
> 
> > -static void isp1301_configure(void)
> > +static u16 i2c_read16(u8 subaddr)
> > +{
> > +	u16 data;
> > +
> > +	i2c_master_send(isp1301_i2c_client, &subaddr, 1);
> > +	i2c_master_recv(isp1301_i2c_client, (u8 *) &data, 2);
> > +
> > +	return data;
> > +}
> 
> Won't i2c_smbus_read_word_data(isp1301_i2c_client, reg) do?
> 
> And while we are at it: Could you also try replacing i2c_write() with
> i2c_smbus_write_byte_data(isp1301_i2c_client, reg, val)?
> 
> No need to recode it (and in general, those solutions will also work with SMBus
> for free)

"no need to recode it" means "no need to recode these already existing functions"

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From alan at signal11.us  Sat Mar 10 13:44:35 2012
From: alan at signal11.us (Alan Ott)
Date: Sat, 10 Mar 2012 13:44:35 -0500
Subject: [PATCH 1/2] ARM: at91: only RM9200 has ISA-style PIO
In-Reply-To: <1331405049-3186-1-git-send-email-alan@signal11.us>
References: <1331405049-3186-1-git-send-email-alan@signal11.us>
Message-ID: <1331405075-3231-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

Most at91 systems have no support for PCMCIA or other
PC-style buses, so we can select NO_IOPORT in order to
disable compilationf or all drivers that need these.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dfb0312..1306f0d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -322,6 +322,7 @@ config ARCH_AT91
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_CLK
 	select CLKDEV_LOOKUP
+	select NO_IOPORT if !ARCH_AT91RM9200
 	help
 	  This enables support for systems based on the Atmel AT91RM9200,
 	  AT91SAM9 and AT91CAP9 processors.
-- 
1.7.0.4



From kgene.kim at samsung.com  Sat Mar 10 10:35:29 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 07:35:29 -0800
Subject: [GIT PULL] Samsung Cleanup EXYNOS clock for v3.4
In-Reply-To: <4F5A22AD.1070907@samsung.com>
References: <4F589474.8050609@samsung.com>
 <CAOesGMiWOChuMjLQTK1pGys+oXCc4A=HO-2_=37rh3M6pgUP_g@mail.gmail.com>
 <4F5A22AD.1070907@samsung.com>
Message-ID: <4F5B74C1.3080200@samsung.com>

On 03/09/12 07:33, Kukjin Kim wrote:
> On 03/08/12 07:16, Olof Johansson wrote:
>> Hi,
>>
>> On Thu, Mar 8, 2012 at 3:13 AM, Kukjin Kim<kgene.kim at samsung.com> wrote:
>>
>>> Kukjin Kim (2):
>>> ARM: EXYNOS: cleanup clock part for new EXYNOS SoCs
>>
>> This is one large commit that does many things in one change. As the
>> patch message says:
>>
>> ARM: EXYNOS: cleanup clock part for new EXYNOS SoCs
>>
>> - the prefix of clk register replace S5P_ with EXYNOS4_
>> - move mach-exynos/clock.c to mach-exynos/clock-exynos4.c
>> - according to moving clock-exynos4.c,
>> move<mach/exynos4-clock.h> to "clock-exynos4.h"
>> - add prefix exynos4_ on clk declaration
>>
>> It makes it hard to review, especially when you combine a move with
>> other changes. It's better to do the move in a separate commit that
>> doesn't change code (or only changes very very little) and then do the
>> other changes in separate commits later.
>>
> Hmm...OK, let me do as per your suggestion and will re-send this soon.
>
Hi Olof,

I addressed comments from you and I think it should be ok to you.

Please pull from:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/cleanup-exynos-clock

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

   Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/cleanup-exynos-clock

Jaecheol Lee (1):
       ARM: EXYNOS: add clock registers for exynos4x12-cpufreq

Kukjin Kim (4):
       ARM: EXYNOS: replace clock.c for other new EXYNOS SoCs
       ARM: EXYNOS: use static declaration on regarding clock
       ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock
       PM / devfreq: update the name of EXYNOS clock register

MyungJoo Ham (2):
       PM / devfreq: update the name of EXYNOS clock registers that were 
omitted
       ARM: EXYNOS: Add clock register addresses for EXYNOS4X12 bus 
devfreq driver

  arch/arm/mach-exynos/Makefile                     |    3 +-
  arch/arm/mach-exynos/clock-exynos4.c              | 1563 
++++++++++++++++++++
  arch/arm/mach-exynos/clock-exynos4.h              |   30 +
  arch/arm/mach-exynos/clock-exynos4210.c           |   46 +-
  arch/arm/mach-exynos/clock-exynos4212.c           |   30 +-
  arch/arm/mach-exynos/clock.c                      | 1564 
---------------------
  arch/arm/mach-exynos/common.h                     |    9 +
  arch/arm/mach-exynos/include/mach/exynos4-clock.h |   43 -
  arch/arm/mach-exynos/include/mach/regs-clock.h    |  416 +++---
  arch/arm/mach-exynos/pm.c                         |   40 +-
  drivers/devfreq/exynos4_bus.c                     |  230 ++--
  11 files changed, 2009 insertions(+), 1965 deletions(-)
  create mode 100644 arch/arm/mach-exynos/clock-exynos4.c
  create mode 100644 arch/arm/mach-exynos/clock-exynos4.h
  delete mode 100644 arch/arm/mach-exynos/clock.c
  delete mode 100644 arch/arm/mach-exynos/include/mach/exynos4-clock.h


From alan at signal11.us  Sat Mar 10 13:44:09 2012
From: alan at signal11.us (Alan Ott)
Date: Sat, 10 Mar 2012 13:44:09 -0500
Subject: [PATCH 0/2] ARM: AT91: cleanup patches from Arnd Bergmann
Message-ID: <1331405049-3186-1-git-send-email-alan@signal11.us>

Hello,

I'm helping Arnd Bergmann get some of his cleanup patches upstream. This
set covers the AT91 and is based off of torvalds/linux.git.

Thanks,

Alan.

Arnd Bergmann (2):
  ARM: at91: only RM9200 has ISA-style PIO
  ARM: at91: Use proper __iomem annotations

 arch/arm/Kconfig                           |    1 +
 arch/arm/mach-at91/at91rm9200.c            |    2 +-
 arch/arm/mach-at91/include/mach/hardware.h |    4 ++++
 arch/arm/mach-at91/setup.c                 |    4 ++--
 4 files changed, 8 insertions(+), 3 deletions(-)



From swarren at wwwdotorg.org  Fri Mar  9 11:47:11 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 09 Mar 2012 09:47:11 -0700
Subject: [PATCH 11/11] ARM: tegra: pcie: Add device tree support
In-Reply-To: <20120309063115.GA25208@avionic-0098.mockup.avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-12-git-send-email-thierry.reding@avionic-design.de>
 <4F59253D.7070100@wwwdotorg.org>
 <20120309063115.GA25208@avionic-0098.mockup.avionic-design.de>
Message-ID: <4F5A340F.6080303@wwwdotorg.org>

On 03/08/2012 11:31 PM, Thierry Reding wrote:
> * Stephen Warren wrote:
>> On 03/08/2012 07:51 AM, Thierry Reding wrote:
>>> This commit adds support for instantiating the Tegra PCIe controller
>>> from a device tree.
>>>
>>> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
>>
>>> diff --git a/Documentation/devicetree/bindings/pci/tegra-pcie.txt b/Documentation/devicetree/bindings/pci/tegra-pcie.txt
>>
>>> +NVIDIA Tegra PCIe controller
>>> +
>>> +Required properties:
>>> +- compatible: "nvidia,tegra20-pcie"
>>> +- reg: physical base address and length of the controller's registers
>>> +- interrupts: the interrupt outputs of the controller
>>> +
>>> +Optional properties:
>>> +- pex-clk-supply: supply voltage for internal reference clock
>>> +- vdd-supply: power supply for controller (1.05V)
>>
>> Mark, Liam,
>>
>> Should those *-supply properties really be optional? I got the
>> impression talking to Mark in a different thread that all regulators
>> should exist, although their implementation may be via a fixed
>> regulator, with no GPIO, as determined by the board design.
> 
> If I read the TrimSlice code correctly, there is no regulator setup required
> to make PCIe work there presumably because they hardwire the proper voltages.

Yes. I believe that's exactly what the fixed regulator is for.

> On the other hand, maybe a better solution in this case would be to use the
> dummy regulator in those cases.

Mark indicated dummy regulators weren't the preferred mechanism:

http://lkml.org/lkml/2012/2/25/30


From thomas.abraham at linaro.org  Sun Mar 11 08:46:01 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sun, 11 Mar 2012 18:16:01 +0530
Subject: [PATCH 1/5] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1331469965-28846-2-git-send-email-thomas.abraham@linaro.org>

Add a new pinctrl and gpiolib driver for Samsung SoC's. This driver provides a
common framework for all Samsung SoC's to interface with the pinctrl and
gpiolib subsystems.

This driver is split into two parts: the pinctrl interface and the gpiolib
interface. The pinctrl interface registers pinctrl devices with the pinctrl
subsystem and gpiolib interface registers gpio chips with the gpiolib
subsystem. The information about the pins, pin groups, pin functions and
gpio chips, which are SoC specific, are all provided to the driver using
driver data. The driver registers all the pinctrl devices and gpio chips
which are found in the driver data.

Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/plat-samsung/include/plat/pinctrl.h |   35 ++
 drivers/pinctrl/Kconfig                      |    3 +
 drivers/pinctrl/Makefile                     |    1 +
 drivers/pinctrl/pinctrl-samsung.c            |  589 ++++++++++++++++++++++++++
 drivers/pinctrl/pinctrl-samsung.h            |  143 +++++++
 5 files changed, 771 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/include/plat/pinctrl.h
 create mode 100644 drivers/pinctrl/pinctrl-samsung.c
 create mode 100644 drivers/pinctrl/pinctrl-samsung.h

diff --git a/arch/arm/plat-samsung/include/plat/pinctrl.h b/arch/arm/plat-samsung/include/plat/pinctrl.h
new file mode 100644
index 0000000..0c226b2
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pinctrl.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2012 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * Samsung Pinctrl driver helper macros
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PLAT_SAMSUNG_PINCTRL_H
+#define __PLAT_SAMSUNG_PINCTRL_H __FILE__
+
+#define _PUD_MASK	0xF
+#define PUD_NONE	0
+#define PUD_DOWN	1
+#define PUD_UP		2
+
+#define _DRV_SHIFT	4
+#define _DRV_MASK	0xF
+#define DRV_1X		0
+#define DRV_2X		1
+#define DRV_3X		2
+#define DRV_4X		3
+
+#define PINCTRL_CFG_PACK(PUD, DRV)	((DRV << _DRV_SHIFT) | PUD)
+#define PINCTRL_CFG_UNPACK_PUD(CFG)	(CFG & _PUD_MASK)
+#define PINCTRL_CFG_UNPACK_DRV(CFG)	((CFG >> _DRV_SHIFT) & _DRV_MASK)
+
+#endif /* __PLAT_SAMSUNG_PINCTRL_H */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c6d29ff..a068d16 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -79,6 +79,9 @@ config PINCTRL_COH901
 	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
 	  ports of 8 GPIO pins each.
 
+config PINCTRL_SAMSUNG
+	bool "Samsung pinctrl driver"
+
 endmenu
 
 endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 754329b..eaccc1b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
new file mode 100644
index 0000000..262dc3b
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -0,0 +1,589 @@
+/*
+ * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2012 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This driver is divided into two main components, gpiolib subsystem interface
+ * and the pin-controller subsystem interface. This model help to better
+ * abstract the details of pad controller for all the Samsung SoC's. The driver
+ * is designed to be reusuable on all the Samsung SoC's providing both gpiolib
+ * and pinctrl subsystem interfaces.
+ *
+ * The driver functions are kept as generic as possible such that they are
+ * usable across multiple Samsung SoC's. The driver data differentiates the
+ * operation of the driver for each SoC by describing the complete
+ * pad-controller structure to the driver and the generic driver code operates
+ * on the SoC specific driver data. The driver data also includes runtime data
+ * required for the operation of the driver.
+ *
+ * List of ToDo's:
+ * 1. Add GPIO Interrupt support.
+ * 2. Add external interrupt (wakeup) support.
+ * 3  Add power management support.
+ * 4. Find a better way to populate data about pins and functions.
+ * 5. Add driver data, pins, groups, functions for all Samsung SoC's and test.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/gpio.h>
+
+#include <plat/pinctrl.h>
+
+#include "pinctrl-samsung.h"
+
+/* check if the selector is a valid pin group selector */
+static int samsung_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	if (selector >= drvdata->nr_groups)
+		return -EINVAL;
+	return 0;
+}
+
+/* return the name of the group selected by the group selector */
+static const char *samsung_get_group_name(struct pinctrl_dev *pctldev,
+						unsigned selector)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	return drvdata->pin_groups[selector].name;
+}
+
+/* return the pin numbers associated with the specified group */
+static int samsung_get_group_pins(struct pinctrl_dev *pctldev,
+		unsigned selector, const unsigned **pins, unsigned *num_pins)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	*pins = drvdata->pin_groups[selector].pins;
+	*num_pins = drvdata->pin_groups[selector].num_pins;
+	return 0;
+}
+
+/* list of pinctrl callbacks for the pinctrl core */
+static struct pinctrl_ops samsung_pctrl_ops = {
+	.list_groups	= samsung_list_groups,
+	.get_group_name	= samsung_get_group_name,
+	.get_group_pins	= samsung_get_group_pins,
+};
+
+
+/* check if the selector is a valid pin function selector */
+static int samsung_pinmux_list_funcs(struct pinctrl_dev *pctldev,
+					unsigned selector)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	if (selector >= drvdata->nr_groups)
+		return -EINVAL;
+	return 0;
+}
+
+/* return the name of the pin function specified */
+static const char *samsung_pinmux_get_fname(struct pinctrl_dev *pctldev,
+						unsigned selector)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	return drvdata->pmx_functions[selector].name;
+}
+
+/* return the groups associated for the specified function selector */
+static int samsung_pinmux_get_groups(struct pinctrl_dev *pctldev,
+		unsigned selector, const char * const **groups,
+		unsigned * const num_groups)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	*groups = drvdata->pmx_functions[selector].groups;
+	*num_groups = drvdata->pmx_functions[selector].num_groups;
+	return 0;
+}
+
+/*
+ * given a pin number that is local to a pin controller, find out the pin bank
+ * and the register base of the pin bank.
+ */
+static void pin_to_reg_bank(struct gpio_chip *gc, unsigned pin,
+			void __iomem **reg, unsigned long *offset,
+			struct samsung_pin_bank **bank)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	struct samsung_pin_bank *b;
+
+	drvdata = dev_get_drvdata(gc->dev);
+	b = drvdata->ctrl->pin_banks;
+
+	while (b->pin_base + b->nr_pins < pin)
+		b++;
+
+	*reg = drvdata->virt_base + b->reg_offset;
+	*offset = pin - b->pin_base;
+	if (bank)
+		*bank = b;
+
+	/* some banks have two config registers in a single bank */
+	if (*offset * b->func_width > BITS_PER_LONG)
+		*reg += 4;
+}
+
+/* enable or disable a pinmux function */
+static void samsung_pimux_setup(struct pinctrl_dev *pctldev, unsigned selector,
+					unsigned group, bool enable)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	const unsigned int *pin;
+	unsigned long data, pin_offset, cnt;
+	struct samsung_pin_bank *bank;
+	void __iomem *reg;
+	unsigned int mask, shift;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	pin = drvdata->pin_groups[group].pins;
+
+	/*
+	 * for each pin in the pin group selected, program the correspoding pin
+	 * pin function number in the config register.
+	 */
+	for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++, pin++) {
+		pin_to_reg_bank(drvdata->gc, *pin - drvdata->ctrl->base,
+				&reg, &pin_offset, &bank);
+		mask = (1 << bank->func_width) - 1;
+		shift = pin_offset * bank->func_width;
+
+		data = readl(reg);
+		data &= ~(mask << shift);
+		if (enable)
+			data |= drvdata->pin_groups[group].func << shift;
+		writel(data, reg);
+	}
+}
+
+/* enable a specified pinmux by writing to registers */
+static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
+					unsigned group)
+{
+	samsung_pimux_setup(pctldev, selector, group, true);
+	return 0;
+}
+
+/* disable a specified pinmux by writing to registers */
+static void samsung_pinmux_disable(struct pinctrl_dev *pctldev,
+					unsigned selector, unsigned group)
+{
+	samsung_pimux_setup(pctldev, selector, group, false);
+}
+
+/*
+ * The calls to gpio_direction_output() and gpio_direction_input()
+ * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
+ * function called from the gpiolib interface).
+ */
+static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+		struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+	unsigned long data, pin_offset;
+	struct samsung_pin_bank *bank;
+	void __iomem *reg;
+	unsigned int mask, shift;
+
+	pin_to_reg_bank(range->gc, offset, &reg, &pin_offset, &bank);
+	mask = (1 << bank->func_width) - 1;
+	shift = pin_offset * bank->func_width;
+
+	data = readl(reg);
+	data &= ~(mask << shift);
+	if (!input)
+		data |= FUNC_OUTPUT << shift;
+	writel(data, reg);
+	return 0;
+}
+
+/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
+static struct pinmux_ops samsung_pinmux_ops = {
+	.list_functions		= samsung_pinmux_list_funcs,
+	.get_function_name	= samsung_pinmux_get_fname,
+	.get_function_groups	= samsung_pinmux_get_groups,
+	.enable			= samsung_pinmux_enable,
+	.disable		= samsung_pinmux_disable,
+	.gpio_set_direction	= samsung_pinmux_gpio_set_direction,
+};
+
+/* set the pull up/down and driver strength settings for a specified pin */
+static int samsung_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+					unsigned long config)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	unsigned long data, pin_offset;
+	struct samsung_pin_bank *bank;
+	void __iomem *reg;
+	unsigned int mask, shift;
+	unsigned int pud, drv;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	pin_to_reg_bank(drvdata->gc, pin - drvdata->ctrl->base, &reg,
+					&pin_offset, &bank);
+
+	/* update the pull up/down configuration */
+	mask = (1 << bank->pud_width) - 1;
+	shift = pin_offset * bank->pud_width;
+	pud =  PINCTRL_CFG_UNPACK_PUD(config);
+
+	if (drvdata->ctrl->xlate_pud)
+		pud = drvdata->ctrl->xlate_pud(pud);
+
+	data = readl(reg + PUD_REG);
+	data &= ~(mask << shift);
+	data |= (pud << shift);
+	writel(data, reg + PUD_REG);
+
+	/* update the drive strength configuration */
+	mask = (1 << bank->drv_width) - 1;
+	shift = pin_offset * bank->drv_width;
+	drv = PINCTRL_CFG_UNPACK_DRV(config);
+
+	if (drvdata->ctrl->xlate_drv)
+		drv = drvdata->ctrl->xlate_drv(drv);
+
+	data = readl(reg + DRV_REG);
+	data &= ~(mask << shift);
+	data |= (drv << shift);
+	writel(data, reg + DRV_REG);
+
+	return 0;
+}
+
+/*
+ * set the pull up/down and driver strength settings for all the pins in a
+ * specified pin group
+ */
+static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev,
+			unsigned group, unsigned long config)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	const unsigned int *pin;
+	unsigned int cnt;
+
+	drvdata = pinctrl_dev_get_drvdata(pctldev);
+	pin = drvdata->pin_groups[group].pins;
+
+	for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++, pin++)
+		samsung_pinconf_set(pctldev, *pin, config);
+
+	return 0;
+}
+
+/* reading pin pull up/down and driver strength settings not implemented */
+static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
+					unsigned long *config)
+{
+	return -ENOTSUPP;
+}
+
+/* reading pin pull up/down and driver strength settings not implemented */
+static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev,
+				unsigned int group, unsigned long *config)
+{
+	return -ENOTSUPP;
+}
+
+/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
+static struct pinconf_ops samsung_pinconf_ops = {
+	.pin_config_get		= samsung_pinconf_get,
+	.pin_config_set		= samsung_pinconf_set,
+	.pin_config_group_get	= samsung_pinconf_group_get,
+	.pin_config_group_set	= samsung_pinconf_group_set,
+};
+
+/* gpiolib gpio_set callback function */
+static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
+{
+	void __iomem *reg;
+	unsigned long pin_offset, data;
+
+	pin_to_reg_bank(gc, offset, &reg, &pin_offset, NULL);
+	data = readl(reg + DAT_REG);
+	data &= ~(1 << pin_offset);
+	if (value)
+		data |= 1 << pin_offset;
+	__raw_writel(data, reg + DAT_REG);
+}
+
+/* gpiolib gpio_get callback function */
+static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+	void __iomem *reg;
+	unsigned long pin_offset, data;
+
+	pin_to_reg_bank(gc, offset, &reg, &pin_offset, NULL);
+	data = readl(reg + DAT_REG);
+	data >>= pin_offset;
+	data &= 1;
+	return data;
+}
+
+/*
+ * gpiolib gpio_direction_input callback function. The setting of the pin
+ * mux function as 'gpio input' will be handled by the pinctrl susbsystem
+ * interface.
+ */
+static int samsung_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
+{
+	return pinctrl_gpio_direction_input(gc->base + offset);
+}
+
+/*
+* gpiolib gpio_direction_output callback function. The setting of the pin
+* mux function as 'gpio output' will be handled by the pinctrl susbsystem
+* interface.
+*/
+static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
+							int value)
+{
+	int ret;
+
+	ret = pinctrl_gpio_direction_output(gc->base + offset);
+	if (!ret)
+		samsung_gpio_set(gc, offset, value);
+	return ret;
+}
+
+/* register the pinctrl interface with the pinctrl subsystem */
+static int __init samsung_pinctrl_register(struct platform_device *pdev,
+				struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct pinctrl_desc *ctrldesc = drvdata->pctl;
+	struct pinctrl_pin_desc *pindesc, *pdesc;
+	struct samsung_pin_bank *pin_bank;
+	char *pin_names;
+	int pin, bank;
+
+	drvdata->pctl->pctlops = &samsung_pctrl_ops;
+	drvdata->pctl->pmxops = &samsung_pinmux_ops;
+	drvdata->pctl->confops = &samsung_pinconf_ops;
+
+	pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
+			drvdata->ctrl->nr_pins, GFP_KERNEL);
+	if (!pindesc) {
+		dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
+		return -ENOMEM;
+	}
+	ctrldesc->pins = pindesc;
+	ctrldesc->npins = drvdata->ctrl->nr_pins;
+	ctrldesc->npins = drvdata->ctrl->nr_pins;
+
+	/* dynamically populate the pin number and  pin name for pindesc */
+	for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
+		pdesc->number = pin + drvdata->ctrl->base;
+
+	/*
+	 * allocate space for storing the dynamically generated names for all
+	 * the pins which belong to this pin-controller.
+	 */
+	pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
+					drvdata->ctrl->nr_pins, GFP_KERNEL);
+	if (!pin_names) {
+		dev_err(&pdev->dev, "mem alloc for pin names failed\n");
+		return -ENOMEM;
+	}
+
+	/* for each pin, the name of the pin is pin-bank name + pin number */
+	for (bank = 0; bank < drvdata->ctrl->nr_banks; bank++) {
+		pin_bank = &drvdata->ctrl->pin_banks[bank];
+		for (pin = 0; pin < pin_bank->nr_pins; pin++) {
+			sprintf(pin_names, "%s-%d", pin_bank->name, pin);
+			pdesc = pindesc + pin_bank->pin_base + pin;
+			pdesc->name = pin_names;
+			pin_names += PIN_NAME_LENGTH;
+		}
+	}
+
+	drvdata->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, drvdata);
+	if (!drvdata->pctl_dev) {
+		dev_err(&pdev->dev, "could not register pinctrl driver\n");
+		return -EINVAL;
+	}
+
+	drvdata->ctrl->grange->base = drvdata->ctrl->base;
+	drvdata->ctrl->grange->npins = drvdata->ctrl->nr_pins;
+	drvdata->ctrl->grange->gc = drvdata->gc;
+	pinctrl_add_gpio_range(drvdata->pctl_dev, drvdata->ctrl->grange);
+
+	return 0;
+}
+
+/* register the gpiolib interface with the gpiolib subsystem */
+static int __init samsung_gpiolib_register(struct platform_device *pdev,
+				struct samsung_pinctrl_drv_data *drvdata)
+{
+	struct gpio_chip *gc;
+	int ret;
+
+	gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
+	if (!gc) {
+		dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
+		return -ENOMEM;
+	}
+
+	drvdata->gc = gc;
+	gc->base = drvdata->ctrl->base;
+	gc->ngpio = drvdata->ctrl->nr_pins;
+	gc->dev = &pdev->dev;
+	gc->set = samsung_gpio_set;
+	gc->get = samsung_gpio_get;
+	gc->direction_input = samsung_gpio_direction_input;
+	gc->direction_output = samsung_gpio_direction_output;
+	gc->label = drvdata->ctrl->label;
+	gc->owner = THIS_MODULE;
+	ret = gpiochip_add(gc);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
+					"code: %d\n", gc->label, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct of_device_id samsung_pinctrl_dt_match[];
+
+static inline struct samsung_pinctrl_drv_data *samsung_pinctrl_get_driver_data(
+				struct platform_device *pdev)
+{
+#ifdef CONFIG_OF
+	if (pdev->dev.of_node) {
+		const struct of_device_id *match;
+		const struct of_node *node = pdev->dev.of_node;
+		match = of_match_node(samsung_pinctrl_dt_match, node);
+		return (struct samsung_pinctrl_drv_data *)match->data;
+	}
+#endif
+	return (struct samsung_pinctrl_drv_data *)
+		platform_get_device_id(pdev)->driver_data + (pdev->id);
+}
+
+static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
+{
+	struct samsung_pinctrl_drv_data *drvdata;
+	struct resource *res;
+	int ret;
+
+	drvdata = samsung_pinctrl_get_driver_data(pdev);
+	if (!drvdata) {
+		dev_err(&pdev->dev, "driver data not available\n");
+		return -EINVAL;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "cannot find IO resource\n");
+		return -ENOENT;
+	}
+
+	res = request_mem_region(res->start, resource_size(res),
+					pdev->name);
+	if (!res) {
+		dev_err(&pdev->dev, "request for mem region failed\n");
+		return -EBUSY;
+	}
+
+	drvdata->virt_base = ioremap(res->start, resource_size(res));
+	if (!drvdata->virt_base) {
+		dev_err(&pdev->dev, "ioremap failed\n");
+		return -EINVAL;
+	}
+
+	ret = samsung_gpiolib_register(pdev, drvdata);
+	if (ret)
+		return ret;
+
+	ret = samsung_pinctrl_register(pdev, drvdata);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, drvdata);
+	return 0;
+}
+
+/* driver data for various samsung soc's */
+#ifdef CONFIG_CPU_EXYNOS4210
+
+#define EXYNOS4210_PCTRL_DRVDATA ((kernel_ulong_t)&exynos4210_pinctrl_drv_data)
+#else
+#define EXYNOS4210_PCTRL_DRVDATA ((kernel_ulong_t)NULL)
+#endif /* CONFIG_CPU_EXYNOS4210 */
+
+static struct platform_device_id samsung_pinctrl_driver_ids[] = {
+	{
+		.name		= "exynos4-pinctrl",
+		.driver_data	= EXYNOS4210_PCTRL_DRVDATA,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(platform, samsung_pinctrl_driver_ids);
+
+#ifdef CONFIG_OF
+static const struct of_device_id samsung_pinctrl_dt_match[] = {
+#ifdef CONFIG_CPU_EXYNOS4210
+	{ .compatible = "samsung,exynos4210-pinctrl0",
+		.data = (void *)&exynos4210_pinctrl_drv_data[0] },
+	{ .compatible = "samsung,exynos4210-pinctrl1",
+		.data = (void *)&exynos4210_pinctrl_drv_data[1] },
+	{ .compatible = "samsung,exynos4210-pinctrl2",
+		.data = (void *)&exynos4210_pinctrl_drv_data[2] },
+#endif /* CONFIG_CPU_EXYNOS4210 */
+	{},
+};
+MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);
+#endif /* CONFIG_OF */
+
+static struct platform_driver samsung_pinctrl_driver = {
+	.probe		= samsung_pinctrl_probe,
+	.id_table	= samsung_pinctrl_driver_ids,
+	.driver = {
+		.name	= "samsung-pinctrl",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(samsung_pinctrl_dt_match),
+	},
+};
+
+static int __init samsung_pinctrl_drv_register(void)
+{
+	return platform_driver_register(&samsung_pinctrl_driver);
+}
+postcore_initcall(samsung_pinctrl_drv_register);
+
+static void __exit samsung_pinctrl_drv_unregister(void)
+{
+	platform_driver_unregister(&samsung_pinctrl_driver);
+}
+module_exit(samsung_pinctrl_drv_unregister);
+
+MODULE_AUTHOR("Thomas Abraham <thomas.ab at samsung.com>");
+MODULE_DESCRIPTION("Samsung pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
new file mode 100644
index 0000000..d28bd46
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -0,0 +1,143 @@
+/*
+ * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ * Copyright (c) 2012 Linaro Ltd
+ *		http://www.linaro.org
+ *
+ * Author: Thomas Abraham <thomas.ab at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __PINCTRL_SAMSUNG_H
+#define __PINCTRL_SAMSUNG_H
+
+/* register offsets within a pin bank */
+#define DAT_REG		0x4
+#define PUD_REG		0x8
+#define DRV_REG		0xC
+
+/* pinmux function number for pin as gpio output line */
+#define FUNC_OUTPUT	0x1
+
+/* maximum length of a pin in pin descriptor */
+#define PIN_NAME_LENGTH	10
+
+#define PIN_GROUP(n, p, f)				\
+	{						\
+		.name		= n,			\
+		.pins		= p,			\
+		.num_pins	= ARRAY_SIZE(p),	\
+		.func		= f			\
+	}
+
+#define PMX_FUNC(n, g)					\
+	{						\
+		.name		= n,			\
+		.groups		= g,			\
+		.num_groups	= ARRAY_SIZE(g),	\
+	}
+
+/**
+ * struct samsung_pin_bank: represent a controller pin-bank.
+ * @reg_offset: starting offset of the pin-bank registers.
+ * @pin_base: starting pin number of the bank.
+ * @nr_pins: number of pins included in this bank.
+ * @func_width: width of the function selector bit field.
+ * @pud_width: width of the pin pull up/down selector bit field.
+ * @drc_width: width of the pin driver strength selector bit field.
+ * @irq_base: starting eint number of the bank.
+ * @name: name to be prefixed for each pin in this pin bank.
+ */
+struct samsung_pin_bank {
+	unsigned int		reg_offset;
+	unsigned int		pin_base;
+	unsigned int		nr_pins;
+	unsigned int		func_width;
+	unsigned int		pud_width;
+	unsigned int		drv_width;
+	unsigned int		irq_base;
+	char			*name;
+};
+
+/**
+ * struct samsung_pin_ctrl: represent a pin controller.
+ * @pin_banks: list of pin banks included in this controller.
+ * @nr_banks: number of pin banks.
+ * @base: starting system wide pin number.
+ * @nr_pins: number of pins supported by the controller.
+ * @xlate_pud: soc specific callback to translate PUD_XXX values to soc
+ *	specific pull up/down register values (optional).
+ * @xlate_drv: soc specific callback to translate DRV_XXX values to soc
+ *	specific driver strength register values (optional).
+ * @label: for debug information.
+ */
+struct samsung_pin_ctrl {
+	struct pinctrl_gpio_range	*grange;
+	struct samsung_pin_bank		*pin_banks;
+	unsigned int			nr_banks;
+	unsigned int			base;
+	unsigned int			nr_pins;
+	int (*xlate_pud)(unsigned int pud);
+	int (*xlate_drv)(unsigned int drv);
+	char				*label;
+};
+
+/**
+ * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
+ * @virt_base: register base address of the controller.
+ * @ctrl: pin controller instance managed by the driver.
+ * @pctl: pin controller descriptor registered with the pinctrl subsystem.
+ * @pctl_dev: cookie representing pinctrl device instance.
+ * @pin_groups: list of pin groups available to the driver.
+ * @nr_groups: number of such pin groups.
+ * @pmx_functions: list of pin functions available to the driver.
+ * @nr_function: number of such pin functions.
+ * @gc: gpio_chip instance registered with gpiolib.
+ */
+struct samsung_pinctrl_drv_data {
+	void __iomem			*virt_base;
+	struct samsung_pin_ctrl		*ctrl;
+	struct pinctrl_desc		*pctl;
+	struct pinctrl_dev		*pctl_dev;
+	const struct samsung_pin_group	*pin_groups;
+	unsigned int			nr_groups;
+	const struct samsung_pmx_func	*pmx_functions;
+	unsigned int			nr_functions;
+	struct gpio_chip		*gc;
+};
+
+/**
+ * struct samsung_pin_group: represent group of pins of a pinmux function.
+ * @name: name of the pin group, used to lookup the group.
+ * @pins: the pins included in this group.
+ * @num_pins: number of pins included in this group.
+ * @func: the function number to be programmed when selected.
+ */
+struct samsung_pin_group {
+	const char		*name;
+	const unsigned int	*pins;
+	const unsigned int	num_pins;
+	unsigned int		func;
+};
+
+/**
+ * struct samsung_pmx_func: represent a pin function.
+ * @name: name of the pin function, used to lookup the function.
+ * @groups: one or more names of pin groups that provide this function.
+ * @num_groups: number of groups included in @groups.
+ */
+struct samsung_pmx_func {
+	const char		*name;
+	const char * const	*groups;
+	const unsigned		num_groups;
+};
+
+extern struct samsung_pinctrl_drv_data exynos4210_pinctrl_drv_data[];
+
+#endif /* __PINCTRL_SAMSUNG_H */
-- 
1.6.6.rc2



From javier.martin at vista-silicon.com  Fri Mar  9 10:20:49 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:49 +0100
Subject: [PATCH v3 13/13] dmaengine: imx-dma: use 'dev_dbg' and 'dev_warn' for
 messages.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-14-git-send-email-javier.martin@vista-silicon.com>

There were some 'pr_crit' and 'pr_debug' messages due to the
initial merge. Replace them by 'dev_dbg' and 'dev_warn' to be
consistent.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   23 ++++++++++++-----------
 1 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index c4a039c..4584012 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -225,8 +225,8 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 
 	imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
 
-	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
-		"size 0x%08x\n", imxdmac->channel,
+	dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
+		"size 0x%08x\n", __func__, imxdmac->channel,
 		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
 		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
 		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
@@ -241,7 +241,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
-	pr_debug("imxdma%d: imx_dma_enable\n", channel);
+	dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
 
 	local_irq_save(flags);
 
@@ -272,7 +272,7 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
-	pr_debug("imxdma%d: imx_dma_disable\n", channel);
+	dev_dbg(imxdma->dev,"%s channel %d\n", __func__, channel);
 
 	if (imxdma_hw_chain(imxdmac))
 		del_timer(&imxdmac->watchdog);
@@ -296,7 +296,8 @@ static void imxdma_watchdog(unsigned long data)
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
-	pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+	dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
+		imxdmac->channel);
 }
 
 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
@@ -424,8 +425,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 
 	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
-	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
-		     disr);
+	dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
 
 	imx_dmav1_writel(imxdma, disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
@@ -900,14 +900,14 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	if (cpu_is_mx1()) {
 		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
 		if (ret) {
-			pr_crit("Can't register IRQ for DMA\n");
+			dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
 			kfree(imxdma);
 			return ret;
 		}
 
 		ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
 		if (ret) {
-			pr_crit("Can't register ERRIRQ for DMA\n");
+			dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
 			free_irq(MX1_DMA_INT, NULL);
 			kfree(imxdma);
 			return ret;
@@ -937,8 +937,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
 			ret = request_irq(MX2x_INT_DMACH0 + i,
 					dma_irq_handler, 0, "DMA", imxdma);
 			if (ret) {
-				pr_crit("Can't register IRQ %d for DMA channel %d\n",
-						MX2x_INT_DMACH0 + i, i);
+				dev_warn(imxdma->dev, "Can't register IRQ %d "
+					 "for DMA channel %d\n",
+					 MX2x_INT_DMACH0 + i, i);
 				goto err_init;
 			}
 			init_timer(&imxdmac->watchdog);
-- 
1.7.0.4



From alan at signal11.us  Sat Mar 10 15:06:06 2012
From: alan at signal11.us (Alan Ott)
Date: Sat, 10 Mar 2012 15:06:06 -0500
Subject: [PATCH 1/2] ARM: at91: only RM9200 has ISA-style PIO
In-Reply-To: <201203101924.31710.arnd@arndb.de>
References: <1331405049-3186-1-git-send-email-alan@signal11.us>
 <1331405075-3231-1-git-send-email-alan@signal11.us>
 <201203101924.31710.arnd@arndb.de>
Message-ID: <4F5BB42E.3090201@signal11.us>

On 03/10/2012 02:24 PM, Arnd Bergmann wrote:
> On Saturday 10 March 2012, Alan Ott wrote:
>> From: Arnd Bergmann <arnd at arndb.de>
>>
>> Most at91 systems have no support for PCMCIA or other
>> PC-style buses, so we can select NO_IOPORT in order to
>> disable compilationf or all drivers that need these.
>>
>> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
>> Signed-off-by: Alan Ott <alan at signal11.us>
> You forgot to Cc the at91 maintainers on this patch (and on patch 0).
> Also, this patch relies on the another series I did to redefine
> the meaning of CONFIG_NO_IOPORT while renaming the existing one to
> CONFIG_NO_IOPORT_MAP. This patch will have to wait for the other
> series.

Hi Arnd,

I'm going to assume you mean randconfig/ioport in
git://git.linaro.org/people/arnd/linux.git .
I'll take this patch out for v2 and make a note that it needs to go with
the patches in randconfig/ioport.

I used scripts/get_maintainers.pl for the recipient list, but I now see
how that failed, since this patch modifies the AT91 section of a file
not in arc/arm/mach-at91.

Alan.



From tony at atomide.com  Fri Mar  9 13:31:51 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 9 Mar 2012 10:31:51 -0800
Subject: [PATCH v2] ARM: OMAP: WiLink platform data for the PandaBoard
In-Reply-To: <1331074504-22683-1-git-send-email-mgherzan@gmail.com>
References: <1331074504-22683-1-git-send-email-mgherzan@gmail.com>
Message-ID: <20120309183150.GH12083@atomide.com>

Hi Luca,

* Mircea Gherzan <mgherzan at gmail.com> [120306 14:23]:
> The "uim" deamon requires sysfs entries that are filled in using
> this platform data.
> 
> Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
> ---
>  arch/arm/mach-omap2/board-omap4panda.c |   14 ++++++++++++--
>  include/linux/ti_wilink_st.h           |    2 ++
>  2 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
> index b1d74d6..339e781 100644
> --- a/arch/arm/mach-omap2/board-omap4panda.c
> +++ b/arch/arm/mach-omap2/board-omap4panda.c
> @@ -27,6 +27,7 @@
>  #include <linux/i2c/twl.h>
>  #include <linux/regulator/machine.h>
>  #include <linux/regulator/fixed.h>
> +#include <linux/ti_wilink_st.h>
>  #include <linux/wl12xx.h>
>  
>  #include <mach/hardware.h>
> @@ -56,12 +57,21 @@
>  #define HDMI_GPIO_HPD  63 /* Hotplug detect */
>  
>  /* wl127x BT, FM, GPS connectivity chip */
> -static int wl1271_gpios[] = {46, -1, -1};
> +static struct ti_st_plat_data wilink_platform_data = {
> +	.nshutdown_gpio	= 46,
> +	.dev_name	= "/dev/ttyO1",
> +	.flow_cntrl	= 1,
> +	.baud_rate	= 3000000,
> +	.chip_enable	= NULL,
> +	.suspend	= NULL,
> +	.resume		= NULL,
> +};
> +
>  static struct platform_device wl1271_device = {
>  	.name	= "kim",
>  	.id	= -1,
>  	.dev	= {
> -		.platform_data	= &wl1271_gpios,
> +		.platform_data	= &wilink_platform_data,
>  	},
>  };
>  
> diff --git a/include/linux/ti_wilink_st.h b/include/linux/ti_wilink_st.h
> index 2ef4385..3ca0269 100644
> --- a/include/linux/ti_wilink_st.h
> +++ b/include/linux/ti_wilink_st.h
> @@ -25,6 +25,8 @@
>  #ifndef TI_WILINK_ST_H
>  #define TI_WILINK_ST_H
>  
> +#include <linux/skbuff.h>
> +
>  /**
>   * enum proto-type - The protocol on WiLink chips which share a
>   *	common physical interface like UART.
> -- 

Just checking.. Can you please take a look at this patch
and confirm that this is how things are supposed to be done?

To me passing some third driver's dev_name in pdata seems
pretty weird.. But then again maybe I just don't know how
this is supposed to work.

Regards,

Tony


From kgene.kim at samsung.com  Sun Mar 11 04:56:14 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 00:56:14 -0800
Subject: [GIT PULL v2 3/4] Samsung devel-mmc for v3.4
Message-ID: <4F5C68AE.4000101@samsung.com>

Hi Arnd, Olof

Please pull Samsung devel-mmc for v3.4 and I rebased it on top of 
v3.3-rc7 without v3.4-for-cjb.

Please pull it from:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/devel-samsung-mmc

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:

   Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)

are available in the git repository at:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/devel-samsung-mmc

Jaehoon Chung (3):
       ARM: SAMSUNG: support the second capability for samsung-soc
       mmc: sdhci-s3c: add platform data for the second capability
       ARM: SAMSUNG: change the name from s3c-sdhci to exynos4-sdhci

  arch/arm/mach-exynos/mach-nuri.c           |    4 ++--
  arch/arm/mach-exynos/mach-universal_c210.c |    2 +-
  arch/arm/plat-samsung/include/plat/sdhci.h |    2 ++
  arch/arm/plat-samsung/platformdata.c       |    2 ++
  drivers/mmc/host/sdhci-s3c.c               |    6 +++---
  5 files changed, 10 insertions(+), 6 deletions(-)


From thomas.abraham at linaro.org  Mon Mar 12 00:37:54 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 12 Mar 2012 10:07:54 +0530
Subject: [PATCH 5/5] mmc: sdhci-s3c: setup pins using pinctrl interface
In-Reply-To: <CAH9JG2XJ3HrQROc-_6Lq6zccgF-QZupVozXCQnXYGN7+DBnq+A@mail.gmail.com>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
 <CAH9JG2XJ3HrQROc-_6Lq6zccgF-QZupVozXCQnXYGN7+DBnq+A@mail.gmail.com>
Message-ID: <CAJuYYwSbtJvOM_EY7MXRJ-wEk-vNZvjk64+yKgYRxXABSFk2AQ@mail.gmail.com>

On 12 March 2012 08:08, Kyungmin Park <kmpark at infradead.org> wrote:
> On 3/11/12, Thomas Abraham <thomas.abraham at linaro.org> wrote:
>> The platform specific callback to setup the sdhci pin mux and pin config
>> is removed and the pinctrl subsystem interface is used to setup the
>> mux and config.
>>
>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
>> ---
>> ?drivers/mmc/host/sdhci-s3c.c | ? 15 +++++++++++++--
>> ?1 files changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
>> index ea0767e..76c1c36 100644
>> --- a/drivers/mmc/host/sdhci-s3c.c
>> +++ b/drivers/mmc/host/sdhci-s3c.c
>> @@ -22,6 +22,7 @@
>> ?#include <linux/module.h>
>> ?#include <linux/of.h>
>> ?#include <linux/of_gpio.h>
>> +#include <linux/pinctrl/consumer.h>
>>
>> ?#include <linux/mmc/host.h>
>>
>> @@ -50,6 +51,7 @@ struct sdhci_s3c {
>> ? ? ? struct platform_device ?*pdev;
>> ? ? ? struct resource ? ? ? ? *ioarea;
>> ? ? ? struct s3c_sdhci_platdata *pdata;
>> + ? ? struct pinctrl ? ? ? ? ?*pinctrl;
>> ? ? ? unsigned int ? ? ? ? ? ?cur_clk;
>> ? ? ? int ? ? ? ? ? ? ? ? ? ? ext_cd_irq;
>> ? ? ? int ? ? ? ? ? ? ? ? ? ? ext_cd_gpio;
>> @@ -529,6 +531,9 @@ static inline struct sdhci_s3c_drv_data
>> *sdhci_s3c_get_driver_data(
>> ? ? ? ? ? ? ? ? ? ? ? platform_get_device_id(pdev)->driver_data;
>> ?}
>>
>> +#include <plat/map-s5p.h>
>> +#include <plat/map-base.h>
>
> Why this header files are required?

Sorry, that was a mistake. This was left over here after adding it
here for some debugging. I will take care next time.

>> +
>> ?static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>> ?{
>> ? ? ? struct s3c_sdhci_platdata *pdata;
>> @@ -538,6 +543,7 @@ static int __devinit sdhci_s3c_probe(struct
>> platform_device *pdev)
>> ? ? ? struct sdhci_s3c *sc;
>> ? ? ? struct resource *res;
>> ? ? ? int ret, irq, ptr, clks;
>> + ? ? char *pstate;
>>
>> ? ? ? if (!pdev->dev.platform_data && !pdev->dev.of_node) {
>> ? ? ? ? ? ? ? dev_err(dev, "no device data specified\n");
>> @@ -643,8 +649,13 @@ static int __devinit sdhci_s3c_probe(struct
>> platform_device *pdev)
>> ? ? ? }
>>
>> ? ? ? /* Ensure we have minimal gpio selected CMD/CLK/Detect */
>> - ? ? if (pdata->cfg_gpio)
>> - ? ? ? ? ? ? pdata->cfg_gpio(pdev, pdata->max_width);
>> + ? ? pstate = pdata->max_width ? "sdhci-pcfg8" : "sdhci-pcfg4";
> You should check pdata->max_width == 8 instead of max_width itself.

Thanks. I will fix that.

> BTW if platform set the amx_width as 1. How do you handle this?

If the bus width is 1, we need to add pin map entry for 1 bit bus
width and correspondingly change the code here. I used the sdhci-s3c
driver for testing the samsung pinctrl driver and only tested with
4-bit and 8-bit bus width. The changes in this patch are not final yet
and was mainly included in this series to show how platform callbacks
can be removed.

Thanks,
Thomas.


From m.szyprowski at samsung.com  Fri Mar  9 06:05:05 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 09 Mar 2012 12:05:05 +0100
Subject: [PATCH 3/3] ARM: Exynos: Add DRM core support for NURI board
In-Reply-To: <1331291105-18152-1-git-send-email-m.szyprowski@samsung.com>
References: <1331291105-18152-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1331291105-18152-4-git-send-email-m.szyprowski@samsung.com>

Add core DRM device and alternative platform device data for FIMD DRM
subdriver. Based on the initial patch by Joonyoung Shim
<jy0922.shim at samsung.com>

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/Kconfig     |    1 +
 arch/arm/mach-exynos/mach-nuri.c |   31 +++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index c73eeba..e996b5d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -293,6 +293,7 @@ config MACH_NURI
 	select S5P_DEV_USB_EHCI
 	select S5P_SETUP_MIPIPHY
 	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DRM
 	select EXYNOS4_SETUP_FIMC
 	select EXYNOS4_SETUP_FIMD0
 	select EXYNOS4_SETUP_I2C1
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index a6b9162..682203a 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -25,6 +25,7 @@
 #include <linux/mmc/host.h>
 #include <linux/fb.h>
 #include <linux/pwm_backlight.h>
+#include <drm/exynos_drm.h>
 
 #include <video/platform_lcd.h>
 #include <media/m5mols.h>
@@ -210,6 +211,27 @@ static struct platform_device nuri_gpio_keys = {
 	},
 };
 
+#ifdef CONFIG_DRM_EXYNOS
+static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
+	.timing	= {
+		.xres		= 1024,
+		.yres		= 600,
+		.hsync_len	= 40,
+		.left_margin	= 79,
+		.right_margin	= 200,
+		.vsync_len	= 10,
+		.upper_margin	= 10,
+		.lower_margin	= 11,
+		.refresh	= 60,
+	},
+	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+			  VIDCON0_CLKSEL_LCD,
+	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+	.default_win	= 3,
+	.bpp		= 32,
+};
+
+#else
 /* Frame Buffer */
 static struct s3c_fb_pd_win nuri_fb_win0 = {
 	.win_mode = {
@@ -236,6 +258,7 @@ static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
 };
+#endif
 
 static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
 {
@@ -1335,6 +1358,9 @@ static struct platform_device *nuri_devices[] __initdata = {
 	&cam_vt_cam15_fixed_rdev,
 	&cam_vdda_fixed_rdev,
 	&cam_8m_12v_fixed_rdev,
+#ifdef CONFIG_DRM_EXYNOS
+	&exynos_device_drm,
+#endif
 };
 
 static void __init nuri_map_io(void)
@@ -1366,7 +1392,12 @@ static void __init nuri_machine_init(void)
 	i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
 	s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
 
+#ifdef CONFIG_DRM_EXYNOS
+	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
+	exynos4_fimd0_gpio_setup_24bpp();
+#else
 	s5p_fimd0_set_platdata(&nuri_fb_pdata);
+#endif
 
 	nuri_camera_init();
 
-- 
1.7.1.569.g6f426



From javier.martin at vista-silicon.com  Fri Mar  9 10:20:39 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:39 +0100
Subject: [PATCH v3 03/13] dmaengine: imx-dma: remove dma_mode member of
 internal structure.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-4-git-send-email-javier.martin@vista-silicon.com>

dmaengine now provides 'enum dma_transfer_direction' to properly
specify DMA transfer direction. For this reason, DMA_MODE_* defines
are replaced by this new type and therefore dma_mode member becomes
redundant.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |  103 +++++++++++++++++++++---------------------------
 1 files changed, 45 insertions(+), 58 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index a5bb9bd..400082d 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -35,10 +35,6 @@
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
 #define IMX_DMA_CHANNELS  16
 
-#define DMA_MODE_READ		0
-#define DMA_MODE_WRITE		1
-#define DMA_MODE_MASK		1
-
 #define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
 #define IMX_DMA_MEMSIZE_32	(0 << 4)
 #define IMX_DMA_MEMSIZE_8	(1 << 4)
@@ -132,7 +128,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	unsigned int dma_mode;
 	struct scatterlist *sg;
 	unsigned int resbytes;
 
@@ -153,7 +148,7 @@ struct imxdma_desc {
 	dma_addr_t			src;
 	dma_addr_t			dest;
 	size_t				len;
-	unsigned int			dmamode;
+	enum dma_transfer_direction	direction;
 	enum imxdma_prep_type		type;
 	/* For memcpy and interleaved */
 	unsigned int			config_port;
@@ -237,8 +232,9 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
 /*
  * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
  */
-static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	unsigned long now;
 
@@ -246,7 +242,7 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
 	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
 		imxdma->resbytes -= now;
 
-	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+	if (d->direction == DMA_DEV_TO_MEM)
 		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
 	else
 		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
@@ -263,14 +259,12 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
 }
 
 static int
-imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr,
-		     unsigned int dmamode)
+imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+		     unsigned int dma_length, unsigned int dev_addr)
 {
 	int channel = imxdmac->channel;
 
 	imxdmac->internal.sg = NULL;
-	imxdmac->internal.dma_mode = dmamode;
 
 	if (!dma_address) {
 		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
@@ -284,38 +278,24 @@ imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
 		return -EINVAL;
 	}
 
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
+	pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+		"dev_addr=0x%08x for write\n",
+		channel, __func__, (unsigned int)dma_address,
+		dma_length, dev_addr);
 
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(dma_address, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dma_address, DMA_SAR(channel));
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_to_device,
-				DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
+	imx_dmav1_writel(dma_address, DMA_SAR(channel));
+	imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+	imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+			 DMA_CCR(channel));
 
 	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
 
 	return 0;
 }
 
-static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+static void imxdma_enable_hw(struct imxdma_desc *d)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -336,7 +316,7 @@ static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
 		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
 		if (imxdmac->internal.sg) {
 			u32 tmp;
-			imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+			imxdma_sg_next(d, imxdmac->internal.sg);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -393,18 +373,18 @@ imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_por
 }
 
 static int
-imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+imxdma_setup_sg_hw(struct imxdma_desc *d,
 		 struct scatterlist *sg, unsigned int sgcount,
 		 unsigned int dma_length, unsigned int dev_addr,
-		 unsigned int dmamode)
+		 enum dma_transfer_direction direction)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	int channel = imxdmac->channel;
 
 	if (imxdmac->internal.in_use)
 		return -EBUSY;
 
 	imxdmac->internal.sg = sg;
-	imxdmac->internal.dma_mode = dmamode;
 	imxdmac->internal.resbytes = dma_length;
 
 	if (!sg || !sgcount) {
@@ -419,14 +399,14 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
 		return -EINVAL;
 	}
 
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+	if (direction == DMA_DEV_TO_MEM) {
 		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
 			"dev_addr=0x%08x for read\n",
 			channel, __func__, sg, sgcount, dma_length, dev_addr);
 
 		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
 		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+	} else if (direction == DMA_MEM_TO_DEV) {
 		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
 			"dev_addr=0x%08x for write\n",
 			channel, __func__, sg, sgcount, dma_length, dev_addr);
@@ -439,7 +419,7 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
 		return -EINVAL;
 	}
 
-	imxdma_sg_next(imxdmac, sg);
+	imxdma_sg_next(d, sg);
 
 	return 0;
 }
@@ -517,13 +497,26 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
 	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	int chno = imxdmac->channel;
+	struct imxdma_desc *desc;
 
 	if (imxdma->sg) {
 		u32 tmp;
 		imxdma->sg = sg_next(imxdma->sg);
 
 		if (imxdma->sg) {
-			imxdma_sg_next(imxdmac, imxdma->sg);
+
+			spin_lock(&imxdmac->lock);
+			if (list_empty(&imxdmac->ld_active)) {
+				spin_unlock(&imxdmac->lock);
+				goto out;
+			}
+
+			desc = list_first_entry(&imxdmac->ld_active,
+						struct imxdma_desc,
+						node);
+			spin_unlock(&imxdmac->lock);
+
+			imxdma_sg_next(desc, imxdma->sg);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -556,6 +549,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		}
 	}
 
+out:
 	imx_dmav1_writel(0, DMA_CCR(chno));
 	imxdma->in_use = 0;
 	/* Tasklet irq */
@@ -599,8 +593,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 					  d->config_port, d->config_mem, 0, 0);
 		if (ret < 0)
 			return ret;
-		ret = imxdma_setup_single_hw(imxdmac, d->src,
-					   d->len, d->dest, d->dmamode);
+		ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
 		if (ret < 0)
 			return ret;
 		break;
@@ -608,19 +601,15 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		if (d->dmamode == DMA_MODE_READ)
-			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
-				       d->sgcount, d->len, d->src, d->dmamode);
-		else
-			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
-				      d->sgcount, d->len, d->dest, d->dmamode);
+		ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
+					 imxdmac->per_address, d->direction);
 		if (ret < 0)
 			return ret;
 		break;
 	default:
 		return -EINVAL;
 	}
-	imxdma_enable_hw(imxdmac);
+	imxdma_enable_hw(d);
 	return 0;
 }
 
@@ -865,11 +854,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
 	desc->sg = sgl;
 	desc->sgcount = sg_len;
 	desc->len = dma_length;
+	desc->direction = direction;
 	if (direction == DMA_DEV_TO_MEM) {
-		desc->dmamode = DMA_MODE_READ;
 		desc->src = imxdmac->per_address;
 	} else {
-		desc->dmamode = DMA_MODE_WRITE;
 		desc->dest = imxdmac->per_address;
 	}
 	desc->desc.callback = NULL;
@@ -925,11 +913,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
 	desc->sg = imxdmac->sg_list;
 	desc->sgcount = periods;
 	desc->len = IMX_DMA_LENGTH_LOOP;
+	desc->direction = direction;
 	if (direction == DMA_DEV_TO_MEM) {
-		desc->dmamode = DMA_MODE_READ;
 		desc->src = imxdmac->per_address;
 	} else {
-		desc->dmamode = DMA_MODE_WRITE;
 		desc->dest = imxdmac->per_address;
 	}
 	desc->desc.callback = NULL;
@@ -959,7 +946,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
 	desc->src = src;
 	desc->dest = dest;
 	desc->len = len;
-	desc->dmamode = DMA_MODE_WRITE;
+	desc->direction = DMA_MEM_TO_MEM;
 	desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 	desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 	desc->desc.callback = NULL;
-- 
1.7.0.4



From linux at arm.linux.org.uk  Mon Mar 12 07:28:41 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 12 Mar 2012 11:28:41 +0000
Subject: [PATCH] serial: PL011: clear pending interrupts
In-Reply-To: <01e101cd0042$5bf692a0$13e3b7e0$@lge.com>
References: <1331540750-25697-1-git-send-email-linus.walleij@stericsson.com>
 <20120312083221.GW17370@n2100.arm.linux.org.uk>
 <01e101cd0042$5bf692a0$13e3b7e0$@lge.com>
Message-ID: <20120312112841.GY17370@n2100.arm.linux.org.uk>

On Mon, Mar 12, 2012 at 08:22:07PM +0900, Kim, Jong-Sung wrote:
> Maybe the character is handled on next upcoming RTIS or RXIS in normal.
> However, I agree with you there is possibility of already asserted RXIS at
> this point. (with debugger?) In such a case, we may lose Rx interrupts
> forever because it's not level-triggered, and the ISR lacks error interrupt
> handling. Correct me if something wrong.

The handler does not lack error handling - error handling is associated
with a character, and we deal with errors when we read the associated
character from the receive register.

So, we have no need for the error interrupts.

The PL011, as with all serial drivers I write, has full error handling
incorporated.


From swarren at wwwdotorg.org  Fri Mar  9 11:42:32 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 09 Mar 2012 09:42:32 -0700
Subject: [PATCH 09/11] ARM: tegra: Rewrite PCIe support as a driver
In-Reply-To: <20120309063739.GC25208@avionic-0098.mockup.avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-10-git-send-email-thierry.reding@avionic-design.de>
 <4F5911E0.6060802@wwwdotorg.org>
 <20120309063739.GC25208@avionic-0098.mockup.avionic-design.de>
Message-ID: <4F5A32F8.80001@wwwdotorg.org>

On 03/08/2012 11:37 PM, Thierry Reding wrote:
> * Stephen Warren wrote:
>> On 03/08/2012 07:51 AM, Thierry Reding wrote:
>>> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
...
>>> diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
>>
>>> +#define TEGRA_PCIE_MAX_PORTS 2
>>> +
>>> +struct tegra_pcie_pdata {
>>> +	int (*init)(struct platform_device *pdev);
>>> +	int (*exit)(struct platform_device *pdev);
>>> +	bool enable_ports[TEGRA_PCIE_MAX_PORTS];
>>> +};
>>
>> That's a somewhat odd place to put the header; a dedicated
>> mach-tegra/include/mach/tegra_pcie_pdata.h or
>> include/linux/platform_data/tegra_pcie.h might make more sense.
> 
> mach-tegra/include/mach/pcie.h perhaps? That would be less redundant.

New files in that directory should have tegra in the name somewhere, so
that when multi-SoC kernels are built, and multiple mach-*/include/mach
directories are in the include path (or files get moved from those paths
into a single common place), you know which include file you're getting.


From kgene.kim at samsung.com  Sat Mar 10 11:16:46 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 08:16:46 -0800
Subject: [GIT PULL] Samsung Cleanup S3C24XX for v3.4
In-Reply-To: <CAOesGMhbmnWSrfEQC5tVrskhjQPMSj1aki1CQ-UM_=mv0-re+A@mail.gmail.com>
References: <4F589313.1050706@samsung.com>
 <CAOesGMhbmnWSrfEQC5tVrskhjQPMSj1aki1CQ-UM_=mv0-re+A@mail.gmail.com>
Message-ID: <4F5B7E6E.2010909@samsung.com>

On 03/08/12 08:56, Olof Johansson wrote:
> On Thu, Mar 8, 2012 at 3:08 AM, Kukjin Kim<kgene.kim at samsung.com>  wrote:
>> Hi Arnd, Olof,
>>
>> Please pull cleanup s3c24xx from following:
>> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> next/cleanup-s3c24xx
>>
>> As I said before, this is including merge of mach-s3c24.. directories into
>> just one mach-s3c24xx directory.
>>
>> If any problems, please kindly let me know.
>
> Thanks, pulled. Nice first step on making all of this common!
>
Thanks and as a note, will happen conflicts when this is on top of 
latest mainline.

Just FYI.

arch/arm/mach-s3c2440/common.h can be deleted with following

diff --cc arch/arm/mach-s3c24xx/common.h
index f65dc80,62a2e19..a7cd62f
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@@ -12,6 -12,12 +12,12 @@@
   #ifndef __ARCH_ARM_MACH_S3C2410_COMMON_H
   #define __ARCH_ARM_MACH_S3C2410_COMMON_H

+ #ifdef CONFIG_CPU_S3C2410
   void s3c2410_restart(char mode, const char *cmd);
+ #endif
+
  -#ifdef CONFIG_CPU_S3C2440
  -void s3c2440_restart(char mode, const char *cmd);
++#ifdef CONFIG_CPU_S3C244X
++void s3c244x_restart(char mode, const char *cmd);
+ #endif

   #endif /* __ARCH_ARM_MACH_S3C2410_COMMON_H */

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From javier.martin at vista-silicon.com  Fri Mar  9 10:20:44 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:44 +0100
Subject: [PATCH v3 08/13] dmaengine: imx-dma: remove 'in_use' field of
 'internal' structure.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-9-git-send-email-javier.martin@vista-silicon.com>

It makes no sense keeping an 'in_use' flag when the multiple descriptor
mechanism already prevents a new DMA transfer to be issued when another
one is in course.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |    9 ---------
 1 files changed, 0 insertions(+), 9 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index dba62bc..8499f15 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -130,8 +130,6 @@ enum  imxdma_prep_type {
 struct imxdma_channel_internal {
 	unsigned int resbytes;
 
-	int in_use;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -264,9 +262,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 	pr_debug("imxdma%d: imx_dma_enable\n", channel);
 
-	if (imxdmac->internal.in_use)
-		return;
-
 	local_irq_save(flags);
 
 	imx_dmav1_writel(1 << channel, DMA_DISR);
@@ -285,7 +280,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 				DMA_CCR(channel));
 		}
 	}
-	imxdmac->internal.in_use = 1;
 
 	local_irq_restore(flags);
 }
@@ -305,7 +299,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
 			DMA_CCR(channel));
 	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdmac->internal.in_use = 0;
 	local_irq_restore(flags);
 }
 
@@ -315,7 +308,6 @@ static void imxdma_watchdog(unsigned long data)
 	int channel = imxdmac->channel;
 
 	imx_dmav1_writel(0, DMA_CCR(channel));
-	imxdmac->internal.in_use = 0;
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -434,7 +426,6 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 
 out:
 	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
 	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
-- 
1.7.0.4



From m.szyprowski at samsung.com  Fri Mar  9 06:05:04 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 09 Mar 2012 12:05:04 +0100
Subject: [PATCH 2/3] ARM: Exynos: Add DRM core device support for Universal
 C210 board
In-Reply-To: <1331291105-18152-1-git-send-email-m.szyprowski@samsung.com>
References: <1331291105-18152-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1331291105-18152-3-git-send-email-m.szyprowski@samsung.com>

Add core DRM device and alternative platform device data for FIMD DRM
subdriver. Based on the initial patch by Joonyoung Shim
<jy0922.shim at samsung.com>

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/Kconfig               |    1 +
 arch/arm/mach-exynos/mach-universal_c210.c |   31 ++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5a26944..c73eeba 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -257,6 +257,7 @@ config MACH_UNIVERSAL_C210
 	select S5P_DEV_ONENAND
 	select S5P_DEV_TV
 	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DRM
 	select EXYNOS4_SETUP_FIMD0
 	select EXYNOS4_SETUP_I2C1
 	select EXYNOS4_SETUP_I2C3
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 322b272..30a3ff3 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -23,6 +23,7 @@
 #include <linux/i2c-gpio.h>
 #include <linux/i2c/mcs.h>
 #include <linux/i2c/atmel_mxt_ts.h>
+#include <drm/exynos_drm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -811,6 +812,27 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
 	/* Gyro, To be updated */
 };
 
+#ifdef CONFIG_DRM_EXYNOS
+static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
+	.timing	= {
+		.left_margin	= 16,
+		.right_margin	= 16,
+		.upper_margin	= 2,
+		.lower_margin	= 28,
+		.hsync_len	= 2,
+		.vsync_len	= 1,
+		.xres		= 480,
+		.yres		= 800,
+		.refresh	= 55,
+	},
+	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+			  VIDCON0_CLKSEL_LCD,
+	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
+			  | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+	.default_win	= 3,
+	.bpp		= 32,
+};
+#else
 /* Frame Buffer */
 static struct s3c_fb_pd_win universal_fb_win0 = {
 	.win_mode = {
@@ -838,6 +860,7 @@ static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
 			  | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
 };
+#endif
 
 static struct regulator_consumer_supply cam_vt_dio_supply =
 	REGULATOR_SUPPLY("vdd_core", "0-003c");
@@ -1046,6 +1069,9 @@ static struct platform_device *universal_devices[] __initdata = {
 	&universal_gpio_keys,
 	&s5p_device_onenand,
 	&s5p_device_fimd0,
+#ifdef CONFIG_DRM_EXYNOS
+	&exynos_device_drm,
+#endif
 	&s5p_device_mfc,
 	&s5p_device_mfc_l,
 	&s5p_device_mfc_r,
@@ -1091,7 +1117,12 @@ static void __init universal_machine_init(void)
 	s5p_i2c_hdmiphy_set_platdata(NULL);
 	i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
 
+#ifdef CONFIG_DRM_EXYNOS
+	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
+	exynos4_fimd0_gpio_setup_24bpp();
+#else
 	s5p_fimd0_set_platdata(&universal_lcd_pdata);
+#endif
 
 	universal_touchkey_init();
 	i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
-- 
1.7.1.569.g6f426



From plagnioj at jcrosoft.com  Fri Mar  9 05:04:35 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 9 Mar 2012 11:04:35 +0100
Subject: [PATCH 1/1] of: introduce helper to manage boolean
In-Reply-To: <20120309014441.8236B3E0903@localhost>
References: <1328588028-24766-1-git-send-email-plagnioj@jcrosoft.com>
 <20120309014441.8236B3E0903@localhost>
Message-ID: <20120309100435.GN27213@game.jcrosoft.org>

On 18:44 Thu 08 Mar     , Grant Likely wrote:
> On Tue,  7 Feb 2012 05:13:48 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > of_property_read_bool
> > 
> > Search for a property in a device node and read a 32-bit value from
> > it. Returns 0 if <0> or if the property does not exist, 1 if <1> or none.
> > 
> > this will allow to disable a boolean
> > 
> > is-ok;          => true
> > is-ok = <1>;    => true
> > is-ok = <0>;    => false
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Cc: devicetree-discuss at lists.ozlabs.org
> > ---
> > Hi,
> > 
> > 	if this is ok I'll rebase my mtd and i2c patch to use it
> > 
> > Best Regards,
> > J.
> >  drivers/of/base.c  |   30 ++++++++++++++++++++++++++++++
> >  include/linux/of.h |    8 ++++++++
> >  2 files changed, 38 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/of/base.c b/drivers/of/base.c
> > index 133908a..a0eaf08 100644
> > --- a/drivers/of/base.c
> > +++ b/drivers/of/base.c
> > @@ -686,6 +686,36 @@ int of_property_read_u64(const struct device_node *np, const char *propname,
> >  EXPORT_SYMBOL_GPL(of_property_read_u64);
> >  
> >  /**
> > + * of_property_read_bool - Find and read a boolean from a property
> > + * @np:		device node from which the property value is to be read.
> > + * @propname:	name of the property to be searched.
> > + *
> > + * Search for a property in a device node and read a 32-bit value from
> > + * it. Returns 0 if <0> or if the property does not exist, 1 if <1> or none.
> > + *
> > + * is-ok;	=> true
> > + * is-ok = <1>;	=> true
> > + * is-ok = <0>;	=> false
> > + */
> > +int of_property_read_bool(const struct device_node *np, const char *propname)
> > +{
> > +	u32 reg;
> > +	int ret = of_property_read_u32(np, propname, &reg);
> > +
> > +	switch (ret) {
> > +	case -EINVAL:
> > +		return false;
> > +	case -ENODATA:
> > +		return true;
> > +	case 0:
> > +		return reg == 1;
> 
> Ugh.  so any value other than 1 returns false?  I think that will surprise
> most people.
> 
> I don't like this api or binding.  If it is a bool property, then why isn't
> simply testing for the property existance sufficient?
no if you want to disable it

if a bool is define in the dtsi and want to disable it int the dts

if you we can do the the invert

if !0 => true

is-ok;			=> true
is-ok = <val != 0>;	=> true
is-ok = <0>;		=> false

Best Regards,
J.


From w.sang at pengutronix.de  Mon Mar 12 03:51:07 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Mon, 12 Mar 2012 08:51:07 +0100
Subject: [PATCH] mtd/gpmi : fix the wrong DMA command.
In-Reply-To: <1331518938-24047-1-git-send-email-b32955@freescale.com>
References: <1331518938-24047-1-git-send-email-b32955@freescale.com>
Message-ID: <20120312075107.GB3928@pengutronix.de>

On Mon, Mar 12, 2012 at 10:22:18AM +0800, Huang Shijie wrote:
> The last DMA command of ECC read page is used to disable the BCH module.
> But the original code missed to set the pio[2] which is used to set the
> GPMI_HW_GPMI_ECCCTRL register. fix it now.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>

Thanks! What does happen because of this bug? Additional checksum errors? I
haven't seen many on MX28 IIRC, so I wonder.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From kgene.kim at samsung.com  Sun Mar 11 04:38:57 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 00:38:57 -0800
Subject: [GIT PULL v2] Samsung board patches for v3.4
Message-ID: <4F5C64A1.1090900@samsung.com>

Hi Arnd, Olof,

Please pull regarding rebased Samsung board patches without the non-dt 
board file addition for v3.4.

If any problems, please let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:

   Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)

are available in the git repository at:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/board-samsung

Andrzej Pietrasiewicz (2):
       ARM: EXYNOS: Register JPEG on universal_c210
       ARM: EXYNOS: Register JPEG on nuri

Kamil Debski (2):
       ARM: EXYNOS: add G2D to mach-nuri
       ARM: EXYNOS: add G2D to mach-universal

Mark Brown (8):
       ARM: S3C64XX: Support GPIO LEDs on Cragganmore
       ARM: S3C64XX: Fix build of Cragganmore after SPI changes
       ARM: S3C64XX: Enable power management for disk on Cragganmore
       ARM: S3C64XX: Enable power management for WiFi on Cragganmore
       ARM: S3C64XX: Add hookup for Tomatin module on Cragganmore
       ARM: S3C64XX: Add a SPKVDD supply for CODECs on Cragganmore
       ARM: S3C64XX: Add some more Cragganmore module IDs to the table
       ARM: S3C64XX: Supply platform data for SPI on Cragganmore

MyungJoo Ham (1):
       ARM: EXYNOS: support Exynos4210-bus Devfreq driver on Nuri board

Sachin Kamat (13):
       ARM: EXYNOS: Enable G2D on ORIGEN
       ARM: S5PV210: Add missing FIMC media device to Aquila
       ARM: EXYNOS: Add missing FIMC media device to SMDKV310
       ARM: EXYNOS: Add missing FIMC media device to Origen
       ARM: EXYNOS: Enable G2D on SMDKV310
       ARM: S5PV210: Enable MFC on SMDKV210
       ARM: S5PV210: Enable MFC on SMDKC110
       ARM: S5PV210: Enable FIMC on SMDKV210
       ARM: S5PV210: Enable FIMC on SMDKC110
       ARM: EXYNOS: Enable JPEG on SMDKV310
       ARM: EXYNOS: Enable JPEG on Origen
       ARM: S5PV210: Add JPEG board definition
       ARM: S5PV210: Enable JPEG on SMDKV210

Sangwook Lee (1):
       ARM: EXYNOS: Enable Bluetooth on ORIGEN

Sylwester Nawrocki (3):
       ARM: EXYNOS: Increase virtual framebuffer size on Universal C210 
board
       ARM: EXYNOS: Add support for S5K6AAFX image sensor on Universal 
C210 board
       ARM: SAMSUNG: Add support for S5K6AAFX camera on Nuri board

Tushar Behera (2):
       ARM: EXYNOS: Add __init attribute to nuri_camera_init()
       ARM: EXYNOS: Add __init attribute to universal_camera_init()

  arch/arm/mach-exynos/Kconfig                 |   10 +++
  arch/arm/mach-exynos/mach-nuri.c             |   80 
++++++++++++++++++++++++-
  arch/arm/mach-exynos/mach-origen.c           |   37 ++++++++++++
  arch/arm/mach-exynos/mach-smdkv310.c         |    3 +
  arch/arm/mach-exynos/mach-universal_c210.c   |   80 
++++++++++++++++++++++++--
  arch/arm/mach-s3c64xx/Kconfig                |    1 +
  arch/arm/mach-s3c64xx/mach-crag6410-module.c |   31 ++++++++++-
  arch/arm/mach-s3c64xx/mach-crag6410.c        |   67 +++++++++++++++++++++-
  arch/arm/mach-s5pv210/Kconfig                |    9 +++
  arch/arm/mach-s5pv210/clock.c                |    5 ++
  arch/arm/mach-s5pv210/include/mach/map.h     |    4 +
  arch/arm/mach-s5pv210/mach-aquila.c          |    1 +
  arch/arm/mach-s5pv210/mach-smdkc110.c        |   14 +++++
  arch/arm/mach-s5pv210/mach-smdkv210.c        |   15 +++++
  14 files changed, 346 insertions(+), 11 deletions(-)


From plagnioj at jcrosoft.com  Mon Mar 12 13:02:26 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 12 Mar 2012 18:02:26 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <4F5E169D.3070508@st.com>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <4F5E0993.9020000@gmail.com> <201203121606.26926.sr@denx.de>
 <4F5E169D.3070508@st.com>
Message-ID: <20120312170226.GE13869@game.jcrosoft.org>

On 16:30 Mon 12 Mar     , Giuseppe CAVALLARO wrote:
> On 3/12/2012 4:06 PM, Stefan Roese wrote:
> > Hi Rob,
> > 
> > On Monday 12 March 2012 15:34:59 Rob Herring wrote:
> >> On 03/12/2012 09:05 AM, Stefan Roese wrote:
> >>> This patch adds support to configure the STMMAC ethernet driver via
> >>> device-tree instead of platform_data.
> >>>
> >>> Currently, only the properties needed on SPEAr600 are provided. All
> >>> other properties should be added once needed on other platforms.
> >>>
> >>> Signed-off-by: Stefan Roese <sr at denx.de>
> >>> Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
> >>> Cc: Viresh Kumar <viresh.kumar at st.com>
> >>> ---
> >>>
> >>>  Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
> >>>  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66
> >>>  +++++++++++++++++++- 2 files changed, 103 insertions(+), 1 deletion(-)
> >>>  create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/net/stmmac.txt
> >>> b/Documentation/devicetree/bindings/net/stmmac.txt new file mode 100644
> >>> index 0000000..386a47f
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/net/stmmac.txt
> >>> @@ -0,0 +1,38 @@
> >>> +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
> >>> +
> >>> +Required properties:
> >>> +- compatible: Should be "stm,gmac"
> >>
> >> This is too generic. This should be 1 string per version of h/w.
> > 
> > Viresh, Giuseppe, can you please suggest a proper string for the SPEAr600 
> > STMMAC core, including version?
> >  
> >> 'stm' should be 'st' according to vendor-prefixes.txt.
> 
> I'm not familiar with devicetree; maybe we should have:
> 
> "stmicro,mac100"
> "stmicro,gmac"
> 
> or: st instead of stmicro if you prefer.
you need to put the first soc where the ip appear on gmac it's sti7105

but with PM IIRC it's sti7108

Best Regards,
J.


From kgene.kim at samsung.com  Sun Mar 11 17:17:21 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 14:17:21 -0700
Subject: [PATCH 3/5] ARM: Exynos4: Add pinctrl devices and pin maps
In-Reply-To: <1331469965-28846-4-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <1331469965-28846-4-git-send-email-thomas.abraham@linaro.org>
Message-ID: <4F5D1661.4090007@samsung.com>

Thomas Abraham wrote:
> Add the three pinctrl platform devices and the pin maps for Exynos4.
> 
> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
> ---
>   arch/arm/mach-exynos/Kconfig              |    1 +
>   arch/arm/mach-exynos/Makefile             |    1 +
>   arch/arm/mach-exynos/common.h             |    6 ++
>   arch/arm/mach-exynos/dev-pinctrl.c        |  115 +++++++++++++++++++++++++++++
>   arch/arm/plat-samsung/include/plat/devs.h |    3 +
>   5 files changed, 126 insertions(+), 0 deletions(-)
>   create mode 100644 arch/arm/mach-exynos/dev-pinctrl.c

[...]

> +#include<linux/kernel.h>
> +#include<linux/dma-mapping.h>
> +#include<linux/platform_device.h>
> +#include<linux/interrupt.h>
> +#include<linux/pinctrl/machine.h>

#include <linux/ioport.h> for DEFINE_RES_xxx at below.

> +
> +#include<plat/devs.h>
> +#include<plat/pinctrl.h>
> +
> +#include<mach/map.h>
> +
> +static struct resource exynos4_pinctrl_resource0[] = {
> +	[0] = {
> +		.start  = EXYNOS4_PA_GPIO1,
> +		.end    = EXYNOS4_PA_GPIO1 + SZ_4K - 1,
> +		.flags  = IORESOURCE_MEM,
> +	},

[0] = DEFINE_RES_MEM(EXYNOS4_PA_GPIO1, SZ_4K),

> +	[1] = {
> +		.start  = IRQ_GPIO_XA,
> +		.end    = IRQ_GPIO_XA,
> +		.flags  = IORESOURCE_IRQ,
> +	},

[1] = DEFINE_RES_IRQ(IRQ_GPIO_XA),

But I'm thinking, we need to move to use EXYNOS4_IRQ_GPIO_XA here for
both EXYNOS4 and EXYNOS5 and as a note, I'm working on updating IRQ
naming you can see it in this week :)

> +};
> +
> +struct platform_device exynos4_pinctrl0 = {
> +	.name		= "exynos4-pinctrl",
> +	.id		= 0,
> +	.resource	= exynos4_pinctrl_resource0,
> +	.num_resources	= ARRAY_SIZE(exynos4_pinctrl_resource0),
> +};
> +
> +static struct resource exynos4_pinctrl_resource1[] = {
> +	[0] = {
> +		.start  = EXYNOS4_PA_GPIO2,
> +		.end    = EXYNOS4_PA_GPIO2 + SZ_4K - 1,
> +		.flags  = IORESOURCE_MEM,
> +	},

same as above.

> +	[1] = {
> +		.start  = IRQ_GPIO_XB,
> +		.end    = IRQ_GPIO_XB,
> +		.flags  = IORESOURCE_IRQ,
> +	},

same.

> +};
> +
> +struct platform_device exynos4_pinctrl1 = {
> +	.name		= "exynos4-pinctrl",
> +	.id		= 1,
> +	.resource	= exynos4_pinctrl_resource1,
> +	.num_resources	= ARRAY_SIZE(exynos4_pinctrl_resource1),
> +};
> +
> +static struct resource exynos4_pinctrl_resource2[] = {
> +	[0] = {
> +		.start  = EXYNOS4_PA_GPIO3,
> +		.end    = EXYNOS4_PA_GPIO3 + SZ_4K - 1,
> +		.flags  = IORESOURCE_MEM,
> +	},

same.

> +};
> +
> +struct platform_device exynos4_pinctrl2 = {
> +	.name		= "exynos4-pinctrl",
> +	.id		= 2,
> +	.resource	= exynos4_pinctrl_resource2,
> +	.num_resources	= ARRAY_SIZE(exynos4_pinctrl_resource2),
> +};
> +

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From linux at arm.linux.org.uk  Mon Mar 12 12:11:43 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 12 Mar 2012 16:11:43 +0000
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <1331128466.24656.421.camel@vkoul-udesk3>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <1331128466.24656.421.camel@vkoul-udesk3>
Message-ID: <20120312161143.GA10830@n2100.arm.linux.org.uk>

On Wed, Mar 07, 2012 at 07:24:26PM +0530, Vinod Koul wrote:
> On Tue, 2012-03-06 at 22:33 +0000, Russell King - ARM Linux wrote:
> > [v2 - more or less same description.  Including lakml in cc for the full
> > set]
> > 
> > This patch series cleans up the handling of cookies in DMA engine drivers.
> > This is done by providing a set of inline library functions for common
> > tasks:
> > 
> > - moving the 'last completed cookie' into struct dma_chan - everyone
> >   has this in their driver private channel data structure
> > 
> > - consolidate allocation of cookies to DMA descriptors
> > 
> > - common way to update 'last completed cookie' value
> > 
> > - standard way to implement tx_status callback and update the residue
> > 
> > - consolidate initialization of cookies
> > 
> > - update implementations differing from the majority of DMA engine drivers
> >   to behave the same as the majority implementation in respect of cookies
> > 
> > What this means is that we get to the point where all DMA engine drivers
> > will hand out cookie value '2' as the first, and incrementing cookie
> > values up to INT_MAX, returning to cookie '1' as the next cookie.
> > 
> > Think of this patch series as round 1...  I am hoping over time that more
> > code can be consolidated between the DMA engine drivers and end up with a
> > consistent way to handle various common themes in DMA engine hardware
> > (like physical channel<->peripheral request signal selection.)
> Thanks Russell,
> 
> I have tested this on atom today, and as expected works flawlessly :)
> After all acks, I can merge or these can go thru your tree with my Ack.
> Either way is okay.
> 
> I applied the v2 on a branch and also rebased on top of slave-dma.next.
> There were few conflicts in imx-dma.c. Sacha, Javier, pls see that merge
> is right.
> 
> This branch (rmk_cookie_fixes2_rebased) is not yet pushed, as I am not
> able to connect to infradead.org, should be done when server is back.

Are you going to pick up Shawn Guo's tested-by for these patches, or are
we saying its too late for that now?


From javier.martin at vista-silicon.com  Fri Mar  9 10:20:37 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:37 +0100
Subject: [PATCH v3 01/13] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-2-git-send-email-javier.martin@vista-silicon.com>

It is mainly a simple merge changing the prefix of some
functions to fit the imx-dma namings.

As there are no users of the old dma-v1.c api we can safely
remove this file.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/mach-imx/Kconfig               |    6 -
 arch/arm/mach-imx/Makefile              |    2 -
 arch/arm/mach-imx/dma-v1.c              |  846 -------------------------------
 arch/arm/mach-imx/include/mach/dma-v1.h |  103 ----
 drivers/dma/Kconfig                     |    1 -
 drivers/dma/imx-dma.c                   |  604 ++++++++++++++++++++--
 6 files changed, 552 insertions(+), 1010 deletions(-)
 delete mode 100644 arch/arm/mach-imx/dma-v1.c
 delete mode 100644 arch/arm/mach-imx/include/mach/dma-v1.h

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0e6de36..3da1421 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,6 +1,3 @@
-config IMX_HAVE_DMA_V1
-	bool
-
 config HAVE_IMX_GPC
 	bool
 
@@ -26,7 +23,6 @@ config SOC_IMX1
 	bool
 	select ARCH_MX1
 	select CPU_ARM920T
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
@@ -35,7 +31,6 @@ config SOC_IMX21
 	select MACH_MX21
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
@@ -52,7 +47,6 @@ config SOC_IMX27
 	select MACH_MX27
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f5920c2..a62dc3a 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,5 +1,3 @@
-obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
-
 obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
 obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
 
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
deleted file mode 100644
index 42afc29..0000000
--- a/arch/arm/mach-imx/dma-v1.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/*
- *  linux/arch/arm/plat-mxc/dma-v1.c
- *
- *  i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/scatterlist.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/dma-v1.h>
-
-#define DMA_DCR     0x00		/* Control Register */
-#define DMA_DISR    0x04		/* Interrupt status Register */
-#define DMA_DIMR    0x08		/* Interrupt mask Register */
-#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
-#define DMA_DRTOSR  0x10		/* Request timeout Register */
-#define DMA_DSESR   0x14		/* Transfer Error Status Register */
-#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
-#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
-#define DMA_WSRA    0x40		/* W-Size Register A */
-#define DMA_XSRA    0x44		/* X-Size Register A */
-#define DMA_YSRA    0x48		/* Y-Size Register A */
-#define DMA_WSRB    0x4c		/* W-Size Register B */
-#define DMA_XSRB    0x50		/* X-Size Register B */
-#define DMA_YSRB    0x54		/* Y-Size Register B */
-#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
-#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
-#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
-#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
-#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
-#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
-#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
-#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
-#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */
-
-#define DCR_DRST           (1<<1)
-#define DCR_DEN            (1<<0)
-#define DBTOCR_EN          (1<<15)
-#define DBTOCR_CNT(x)      ((x) & 0x7fff)
-#define CNTR_CNT(x)        ((x) & 0xffffff)
-#define CCR_ACRPT          (1<<14)
-#define CCR_DMOD_LINEAR    (0x0 << 12)
-#define CCR_DMOD_2D        (0x1 << 12)
-#define CCR_DMOD_FIFO      (0x2 << 12)
-#define CCR_DMOD_EOBFIFO   (0x3 << 12)
-#define CCR_SMOD_LINEAR    (0x0 << 10)
-#define CCR_SMOD_2D        (0x1 << 10)
-#define CCR_SMOD_FIFO      (0x2 << 10)
-#define CCR_SMOD_EOBFIFO   (0x3 << 10)
-#define CCR_MDIR_DEC       (1<<9)
-#define CCR_MSEL_B         (1<<8)
-#define CCR_DSIZ_32        (0x0 << 6)
-#define CCR_DSIZ_8         (0x1 << 6)
-#define CCR_DSIZ_16        (0x2 << 6)
-#define CCR_SSIZ_32        (0x0 << 4)
-#define CCR_SSIZ_8         (0x1 << 4)
-#define CCR_SSIZ_16        (0x2 << 4)
-#define CCR_REN            (1<<3)
-#define CCR_RPT            (1<<2)
-#define CCR_FRC            (1<<1)
-#define CCR_CEN            (1<<0)
-#define RTOR_EN            (1<<15)
-#define RTOR_CLK           (1<<14)
-#define RTOR_PSC           (1<<13)
-
-/*
- * struct imx_dma_channel - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- *            (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imx_dma_channel only as extension to it.
- */
-
-struct imx_dma_channel {
-	const char *name;
-	void (*irq_handler) (int, void *);
-	void (*err_handler) (int, void *, int errcode);
-	void (*prog_handler) (int, void *, struct scatterlist *);
-	void *data;
-	unsigned int dma_mode;
-	struct scatterlist *sg;
-	unsigned int resbytes;
-	int dma_num;
-
-	int in_use;
-
-	u32 ccr_from_device;
-	u32 ccr_to_device;
-
-	struct timer_list watchdog;
-
-	int hw_chaining;
-};
-
-static void __iomem *imx_dmav1_baseaddr;
-
-static void imx_dmav1_writel(unsigned val, unsigned offset)
-{
-	__raw_writel(val, imx_dmav1_baseaddr + offset);
-}
-
-static unsigned imx_dmav1_readl(unsigned offset)
-{
-	return __raw_readl(imx_dmav1_baseaddr + offset);
-}
-
-static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
-
-static struct clk *dma_clk;
-
-static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
-{
-	if (cpu_is_mx27())
-		return imxdma->hw_chaining;
-	else
-		return 0;
-}
-
-/*
- * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
- */
-static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long now;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return 0;
-	}
-
-	now = min(imxdma->resbytes, sg->length);
-	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
-		imxdma->resbytes -= now;
-
-	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
-		imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
-	else
-		imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
-
-	imx_dmav1_writel(now, DMA_CNTR(channel));
-
-	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
-		"size 0x%08x\n", channel,
-		 imx_dmav1_readl(DMA_DAR(channel)),
-		 imx_dmav1_readl(DMA_SAR(channel)),
-		 imx_dmav1_readl(DMA_CNTR(channel)));
-
-	return now;
-}
-
-/**
- * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
- * device transfer
- *
- * @channel: i.MX DMA channel number
- * @dma_address: the DMA/physical memory address of the linear data block
- *		to transfer
- * @dma_length: length of the data block in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- *		Zero indicates success.
- */
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr,
-		     unsigned int dmamode)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	imxdma->sg = NULL;
-	imxdma->dma_mode = dmamode;
-
-	if (!dma_address) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!dma_length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(dma_address, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dma_address, DMA_SAR(channel));
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_to_device,
-				DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_single);
-
-/**
- * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
- * @channel: i.MX DMA channel number
- * @sg: pointer to the scatter-gather list/vector
- * @sgcount: scatter-gather list hungs count
- * @dma_length: total length of the transfer request in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * The function sets up DMA channel state and registers to be ready for
- * transfer specified by provided parameters. The scatter-gather emulation
- * is set up according to the parameters.
- *
- * The full preparation of the transfer requires setup of more register
- * by the caller before imx_dma_enable() can be called.
- *
- * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
- *
- * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
- *
- * %CCR(channel) has to specify transfer parameters, the next settings is
- * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
- * specified
- *
- * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
- *
- * The typical setup for %DMA_MODE_WRITE is specified by next options
- * combination
- *
- * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
- *
- * Be careful here and do not mistakenly mix source and target device
- * port sizes constants, they are really different:
- * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
- * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- * Zero indicates success.
- */
-int
-imx_dma_setup_sg(int channel,
-		 struct scatterlist *sg, unsigned int sgcount,
-		 unsigned int dma_length, unsigned int dev_addr,
-		 unsigned int dmamode)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	if (imxdma->in_use)
-		return -EBUSY;
-
-	imxdma->sg = sg;
-	imxdma->dma_mode = dmamode;
-	imxdma->resbytes = dma_length;
-
-	if (!sg || !sgcount) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!sg->length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imx_dma_sg_next(channel, sg);
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_sg);
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	u32 dreq = 0;
-
-	imxdma->hw_chaining = 0;
-
-	if (hw_chaining) {
-		imxdma->hw_chaining = 1;
-		if (!imx_dma_hw_chain(imxdma))
-			return -EINVAL;
-	}
-
-	if (dmareq)
-		dreq = CCR_REN;
-
-	imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
-	imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
-
-	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_config_channel);
-
-void imx_dma_config_burstlen(int channel, unsigned int burstlen)
-{
-	imx_dmav1_writel(burstlen, DMA_BLR(channel));
-}
-EXPORT_SYMBOL(imx_dma_config_burstlen);
-
-/**
- * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
- * handlers
- * @channel: i.MX DMA channel number
- * @irq_handler: the pointer to the function called if the transfer
- *		ends successfully
- * @err_handler: the pointer to the function called if the premature
- *		end caused by error occurs
- * @data: user specified value to be passed to the handlers
- */
-int
-imx_dma_setup_handlers(int channel,
-		       void (*irq_handler) (int, void *),
-		       void (*err_handler) (int, void *, int),
-		       void *data)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return -ENODEV;
-	}
-
-	local_irq_save(flags);
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdma->irq_handler = irq_handler;
-	imxdma->err_handler = err_handler;
-	imxdma->data = data;
-	local_irq_restore(flags);
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_handlers);
-
-/**
- * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
- * handlers
- * @channel: i.MX DMA channel number
- * @prog_handler: the pointer to the function called if the transfer progresses
- */
-int
-imx_dma_setup_progression_handler(int channel,
-			void (*prog_handler) (int, void*, struct scatterlist*))
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return -ENODEV;
-	}
-
-	local_irq_save(flags);
-	imxdma->prog_handler = prog_handler;
-	local_irq_restore(flags);
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_progression_handler);
-
-/**
- * imx_dma_enable - function to start i.MX DMA channel operation
- * @channel: i.MX DMA channel number
- *
- * The channel has to be allocated by driver through imx_dma_request()
- * or imx_dma_request_by_prio() function.
- * The transfer parameters has to be set to the channel registers through
- * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
- * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
- * be set prior this function call by the channel user.
- */
-void imx_dma_enable(int channel)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	pr_debug("imxdma%d: imx_dma_enable\n", channel);
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return;
-	}
-
-	if (imxdma->in_use)
-		return;
-
-	local_irq_save(flags);
-
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
-		CCR_ACRPT, DMA_CCR(channel));
-
-	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			imxdma->sg && imx_dma_hw_chain(imxdma)) {
-		imxdma->sg = sg_next(imxdma->sg);
-		if (imxdma->sg) {
-			u32 tmp;
-			imx_dma_sg_next(channel, imxdma->sg);
-			tmp = imx_dmav1_readl(DMA_CCR(channel));
-			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
-				DMA_CCR(channel));
-		}
-	}
-	imxdma->in_use = 1;
-
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_enable);
-
-/**
- * imx_dma_disable - stop, finish i.MX DMA channel operatin
- * @channel: i.MX DMA channel number
- */
-void imx_dma_disable(int channel)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	pr_debug("imxdma%d: imx_dma_disable\n", channel);
-
-	if (imx_dma_hw_chain(imxdma))
-		del_timer(&imxdma->watchdog);
-
-	local_irq_save(flags);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
-			DMA_CCR(channel));
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdma->in_use = 0;
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_disable);
-
-static void imx_dma_watchdog(unsigned long chno)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
-	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
-	imxdma->sg = NULL;
-
-	if (imxdma->err_handler)
-		imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
-}
-
-static irqreturn_t dma_err_handler(int irq, void *dev_id)
-{
-	int i, disr;
-	struct imx_dma_channel *imxdma;
-	unsigned int err_mask;
-	int errcode;
-
-	disr = imx_dmav1_readl(DMA_DISR);
-
-	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
-		   imx_dmav1_readl(DMA_DRTOSR) |
-		   imx_dmav1_readl(DMA_DSESR)  |
-		   imx_dmav1_readl(DMA_DBOSR);
-
-	if (!err_mask)
-		return IRQ_HANDLED;
-
-	imx_dmav1_writel(disr & err_mask, DMA_DISR);
-
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (!(err_mask & (1 << i)))
-			continue;
-		imxdma = &imx_dma_channels[i];
-		errcode = 0;
-
-		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBTOSR);
-			errcode |= IMX_DMA_ERR_BURST;
-		}
-		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DRTOSR);
-			errcode |= IMX_DMA_ERR_REQUEST;
-		}
-		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DSESR);
-			errcode |= IMX_DMA_ERR_TRANSFER;
-		}
-		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBOSR);
-			errcode |= IMX_DMA_ERR_BUFFER;
-		}
-		if (imxdma->name && imxdma->err_handler) {
-			imxdma->err_handler(i, imxdma->data, errcode);
-			continue;
-		}
-
-		imx_dma_channels[i].sg = NULL;
-
-		printk(KERN_WARNING
-		       "DMA timeout on channel %d (%s) -%s%s%s%s\n",
-		       i, imxdma->name,
-		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
-		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
-		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
-		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
-	}
-	return IRQ_HANDLED;
-}
-
-static void dma_irq_handle_channel(int chno)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
-	if (!imxdma->name) {
-		/*
-		 * IRQ for an unregistered DMA channel:
-		 * let's clear the interrupts and disable it.
-		 */
-		printk(KERN_WARNING
-		       "spurious IRQ for DMA channel %d\n", chno);
-		return;
-	}
-
-	if (imxdma->sg) {
-		u32 tmp;
-		struct scatterlist *current_sg = imxdma->sg;
-		imxdma->sg = sg_next(imxdma->sg);
-
-		if (imxdma->sg) {
-			imx_dma_sg_next(chno, imxdma->sg);
-
-			tmp = imx_dmav1_readl(DMA_CCR(chno));
-
-			if (imx_dma_hw_chain(imxdma)) {
-				/* FIXME: The timeout should probably be
-				 * configurable
-				 */
-				mod_timer(&imxdma->watchdog,
-					jiffies + msecs_to_jiffies(500));
-
-				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
-				imx_dmav1_writel(tmp, DMA_CCR(chno));
-			} else {
-				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
-				tmp |= CCR_CEN;
-			}
-
-			imx_dmav1_writel(tmp, DMA_CCR(chno));
-
-			if (imxdma->prog_handler)
-				imxdma->prog_handler(chno, imxdma->data,
-						current_sg);
-
-			return;
-		}
-
-		if (imx_dma_hw_chain(imxdma)) {
-			del_timer(&imxdma->watchdog);
-			return;
-		}
-	}
-
-	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
-	if (imxdma->irq_handler)
-		imxdma->irq_handler(chno, imxdma->data);
-}
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-	int i, disr;
-
-	if (cpu_is_mx21() || cpu_is_mx27())
-		dma_err_handler(irq, dev_id);
-
-	disr = imx_dmav1_readl(DMA_DISR);
-
-	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
-		     disr);
-
-	imx_dmav1_writel(disr, DMA_DISR);
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (disr & (1 << i))
-			dma_irq_handle_channel(i);
-	}
-
-	return IRQ_HANDLED;
-}
-
-/**
- * imx_dma_request - request/allocate specified channel number
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- */
-int imx_dma_request(int channel, const char *name)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-	int ret = 0;
-
-	/* basic sanity checks */
-	if (!name)
-		return -EINVAL;
-
-	if (channel >= IMX_DMA_CHANNELS) {
-		printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
-		       __func__, channel);
-		return -EINVAL;
-	}
-
-	local_irq_save(flags);
-	if (imxdma->name) {
-		local_irq_restore(flags);
-		return -EBUSY;
-	}
-	memset(imxdma, 0, sizeof(*imxdma));
-	imxdma->name = name;
-	local_irq_restore(flags); /* request_irq() can block */
-
-	if (cpu_is_mx21() || cpu_is_mx27()) {
-		ret = request_irq(MX2x_INT_DMACH0 + channel,
-				dma_irq_handler, 0, "DMA", NULL);
-		if (ret) {
-			imxdma->name = NULL;
-			pr_crit("Can't register IRQ %d for DMA channel %d\n",
-					MX2x_INT_DMACH0 + channel, channel);
-			return ret;
-		}
-		init_timer(&imxdma->watchdog);
-		imxdma->watchdog.function = &imx_dma_watchdog;
-		imxdma->watchdog.data = channel;
-	}
-
-	return ret;
-}
-EXPORT_SYMBOL(imx_dma_request);
-
-/**
- * imx_dma_free - release previously acquired channel
- * @channel: i.MX DMA channel number
- */
-void imx_dma_free(int channel)
-{
-	unsigned long flags;
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT
-		       "%s: trying to free free channel %d\n",
-		       __func__, channel);
-		return;
-	}
-
-	local_irq_save(flags);
-	/* Disable interrupts */
-	imx_dma_disable(channel);
-	imxdma->name = NULL;
-
-	if (cpu_is_mx21() || cpu_is_mx27())
-		free_irq(MX2x_INT_DMACH0 + channel, NULL);
-
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_free);
-
-/**
- * imx_dma_request_by_prio - find and request some of free channels best
- * suiting requested priority
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- *
- * This function tries to find a free channel in the specified priority group
- * if the priority cannot be achieved it tries to look for free channel
- * in the higher and then even lower priority groups.
- *
- * Return value: If there is no free channel to allocate, -%ENODEV is returned.
- *               On successful allocation channel is returned.
- */
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
-{
-	int i;
-	int best;
-
-	switch (prio) {
-	case (DMA_PRIO_HIGH):
-		best = 8;
-		break;
-	case (DMA_PRIO_MEDIUM):
-		best = 4;
-		break;
-	case (DMA_PRIO_LOW):
-	default:
-		best = 0;
-		break;
-	}
-
-	for (i = best; i < IMX_DMA_CHANNELS; i++)
-		if (!imx_dma_request(i, name))
-			return i;
-
-	for (i = best - 1; i >= 0; i--)
-		if (!imx_dma_request(i, name))
-			return i;
-
-	printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
-
-	return -ENODEV;
-}
-EXPORT_SYMBOL(imx_dma_request_by_prio);
-
-static int __init imx_dma_init(void)
-{
-	int ret = 0;
-	int i;
-
-	if (cpu_is_mx1())
-		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
-	else if (cpu_is_mx21())
-		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
-	else if (cpu_is_mx27())
-		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
-	else
-		return 0;
-
-	dma_clk = clk_get(NULL, "dma");
-	if (IS_ERR(dma_clk))
-		return PTR_ERR(dma_clk);
-	clk_enable(dma_clk);
-
-	/* reset DMA module */
-	imx_dmav1_writel(DCR_DRST, DMA_DCR);
-
-	if (cpu_is_mx1()) {
-		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
-		if (ret) {
-			pr_crit("Wow!  Can't register IRQ for DMA\n");
-			return ret;
-		}
-
-		ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
-		if (ret) {
-			pr_crit("Wow!  Can't register ERRIRQ for DMA\n");
-			free_irq(MX1_DMA_INT, NULL);
-			return ret;
-		}
-	}
-
-	/* enable DMA module */
-	imx_dmav1_writel(DCR_DEN, DMA_DCR);
-
-	/* clear all interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
-
-	/* disable interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		imx_dma_channels[i].sg = NULL;
-		imx_dma_channels[i].dma_num = i;
-	}
-
-	return ret;
-}
-
-arch_initcall(imx_dma_init);
diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h
deleted file mode 100644
index ac6fd71..0000000
--- a/arch/arm/mach-imx/include/mach/dma-v1.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- *  linux/arch/arm/mach-imx/include/mach/dma-v1.h
- *
- *  i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_DMA_V1_H__
-#define __MACH_DMA_V1_H__
-
-#define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
-
-#include <mach/dma.h>
-
-#define IMX_DMA_CHANNELS  16
-
-#define DMA_MODE_READ		0
-#define DMA_MODE_WRITE		1
-#define DMA_MODE_MASK		1
-
-#define MX1_DMA_REG(offset)	MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
-
-/* DMA Interrupt Mask Register */
-#define MX1_DMA_DIMR		MX1_DMA_REG(0x08)
-
-/* Channel Control Register */
-#define MX1_DMA_CCR(x)		MX1_DMA_REG(0x8c + ((x) << 6))
-
-#define IMX_DMA_MEMSIZE_32	(0 << 4)
-#define IMX_DMA_MEMSIZE_8	(1 << 4)
-#define IMX_DMA_MEMSIZE_16	(2 << 4)
-#define IMX_DMA_TYPE_LINEAR	(0 << 10)
-#define IMX_DMA_TYPE_2D		(1 << 10)
-#define IMX_DMA_TYPE_FIFO	(2 << 10)
-
-#define IMX_DMA_ERR_BURST     (1 << 0)
-#define IMX_DMA_ERR_REQUEST   (1 << 1)
-#define IMX_DMA_ERR_TRANSFER  (1 << 2)
-#define IMX_DMA_ERR_BUFFER    (1 << 3)
-#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining);
-
-void
-imx_dma_config_burstlen(int channel, unsigned int burstlen);
-
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
-		unsigned int dma_length, unsigned int dev_addr,
-		unsigned int dmamode);
-
-
-/*
- * Use this flag as the dma_length argument to imx_dma_setup_sg()
- * to create an endless running dma loop. The end of the scatterlist
- * must be linked to the beginning for this to work.
- */
-#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
-
-int
-imx_dma_setup_sg(int channel, struct scatterlist *sg,
-		unsigned int sgcount, unsigned int dma_length,
-		unsigned int dev_addr, unsigned int dmamode);
-
-int
-imx_dma_setup_handlers(int channel,
-		void (*irq_handler) (int, void *),
-		void (*err_handler) (int, void *, int), void *data);
-
-int
-imx_dma_setup_progression_handler(int channel,
-		void (*prog_handler) (int, void*, struct scatterlist*));
-
-void imx_dma_enable(int channel);
-
-void imx_dma_disable(int channel);
-
-int imx_dma_request(int channel, const char *name);
-
-void imx_dma_free(int channel);
-
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
-
-#endif	/* __MACH_DMA_V1_H__ */
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f1a2749..eb58b91 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -231,7 +231,6 @@ config IMX_SDMA
 
 config IMX_DMA
 	tristate "i.MX DMA support"
-	depends on IMX_HAVE_DMA_V1
 	select DMA_ENGINE
 	help
 	  Support the i.MX DMA engine. This engine is integrated into
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index c32103f..a34de17 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -14,7 +14,6 @@
  * http://www.opensource.org/licenses/gpl-license.html
  * http://www.gnu.org/copyleft/gpl.html
  */
-
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/types.h>
@@ -25,14 +24,88 @@
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 #include <linux/dmaengine.h>
 #include <linux/module.h>
 
 #include <asm/irq.h>
-#include <mach/dma-v1.h>
+#include <mach/dma.h>
 #include <mach/hardware.h>
 
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
+#define IMX_DMA_CHANNELS  16
+
+#define DMA_MODE_READ		0
+#define DMA_MODE_WRITE		1
+#define DMA_MODE_MASK		1
+
+#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
+#define IMX_DMA_MEMSIZE_32	(0 << 4)
+#define IMX_DMA_MEMSIZE_8	(1 << 4)
+#define IMX_DMA_MEMSIZE_16	(2 << 4)
+#define IMX_DMA_TYPE_LINEAR	(0 << 10)
+#define IMX_DMA_TYPE_2D		(1 << 10)
+#define IMX_DMA_TYPE_FIFO	(2 << 10)
+
+#define IMX_DMA_ERR_BURST     (1 << 0)
+#define IMX_DMA_ERR_REQUEST   (1 << 1)
+#define IMX_DMA_ERR_TRANSFER  (1 << 2)
+#define IMX_DMA_ERR_BUFFER    (1 << 3)
+#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
+
+#define DMA_DCR     0x00		/* Control Register */
+#define DMA_DISR    0x04		/* Interrupt status Register */
+#define DMA_DIMR    0x08		/* Interrupt mask Register */
+#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
+#define DMA_DRTOSR  0x10		/* Request timeout Register */
+#define DMA_DSESR   0x14		/* Transfer Error Status Register */
+#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
+#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
+#define DMA_WSRA    0x40		/* W-Size Register A */
+#define DMA_XSRA    0x44		/* X-Size Register A */
+#define DMA_YSRA    0x48		/* Y-Size Register A */
+#define DMA_WSRB    0x4c		/* W-Size Register B */
+#define DMA_XSRB    0x50		/* X-Size Register B */
+#define DMA_YSRB    0x54		/* Y-Size Register B */
+#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
+#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
+#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
+#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
+#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
+#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
+#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
+#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
+#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff)
+#define CNTR_CNT(x)        ((x) & 0xffffff)
+#define CCR_ACRPT          (1<<14)
+#define CCR_DMOD_LINEAR    (0x0 << 12)
+#define CCR_DMOD_2D        (0x1 << 12)
+#define CCR_DMOD_FIFO      (0x2 << 12)
+#define CCR_DMOD_EOBFIFO   (0x3 << 12)
+#define CCR_SMOD_LINEAR    (0x0 << 10)
+#define CCR_SMOD_2D        (0x1 << 10)
+#define CCR_SMOD_FIFO      (0x2 << 10)
+#define CCR_SMOD_EOBFIFO   (0x3 << 10)
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        (0x0 << 6)
+#define CCR_DSIZ_8         (0x1 << 6)
+#define CCR_DSIZ_16        (0x2 << 6)
+#define CCR_SSIZ_32        (0x0 << 4)
+#define CCR_SSIZ_8         (0x1 << 4)
+#define CCR_SSIZ_16        (0x2 << 4)
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
 
 enum  imxdma_prep_type {
 	IMXDMA_DESC_MEMCPY,
@@ -41,6 +114,39 @@ enum  imxdma_prep_type {
 	IMXDMA_DESC_CYCLIC,
 };
 
+/*
+ * struct imxdma_channel_internal - i.MX specific DMA extension
+ * @name: name specified by DMA client
+ * @irq_handler: client callback for end of transfer
+ * @err_handler: client callback for error condition
+ * @data: clients context data for callbacks
+ * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
+ * @sg: pointer to the actual read/written chunk for scatter-gather emulation
+ * @resbytes: total residual number of bytes to transfer
+ *            (it can be lower or same as sum of SG mapped chunk sizes)
+ * @sgcount: number of chunks to be read/written
+ *
+ * Structure is used for IMX DMA processing. It would be probably good
+ * @struct dma_struct in the future for external interfacing and use
+ * @struct imxdma_channel_internal only as extension to it.
+ */
+
+struct imxdma_channel_internal {
+	void *data;
+	unsigned int dma_mode;
+	struct scatterlist *sg;
+	unsigned int resbytes;
+
+	int in_use;
+
+	u32 ccr_from_device;
+	u32 ccr_to_device;
+
+	struct timer_list watchdog;
+
+	int hw_chaining;
+};
+
 struct imxdma_desc {
 	struct list_head		node;
 	struct dma_async_tx_descriptor	desc;
@@ -63,9 +169,9 @@ struct imxdma_desc {
 };
 
 struct imxdma_channel {
+	struct imxdma_channel_internal	internal;
 	struct imxdma_engine		*imxdma;
 	unsigned int			channel;
-	unsigned int			imxdma_channel;
 
 	struct tasklet_struct		dma_tasklet;
 	struct list_head		ld_free;
@@ -82,13 +188,11 @@ struct imxdma_channel {
 	struct scatterlist		*sg_list;
 };
 
-#define MAX_DMA_CHANNELS 8
-
 struct imxdma_engine {
 	struct device			*dev;
 	struct device_dma_parameters	dma_parms;
 	struct dma_device		dma_device;
-	struct imxdma_channel		channel[MAX_DMA_CHANNELS];
+	struct imxdma_channel		channel[IMX_DMA_CHANNELS];
 };
 
 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
@@ -109,28 +213,381 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 	return false;
 }
 
-static void imxdma_irq_handler(int channel, void *data)
+/* TODO: put this inside any struct */
+static void __iomem *imx_dmav1_baseaddr;
+static struct clk *dma_clk;
+
+static void imx_dmav1_writel(unsigned val, unsigned offset)
+{
+	__raw_writel(val, imx_dmav1_baseaddr + offset);
+}
+
+static unsigned imx_dmav1_readl(unsigned offset)
 {
-	struct imxdma_channel *imxdmac = data;
+	return __raw_readl(imx_dmav1_baseaddr + offset);
+}
 
-	tasklet_schedule(&imxdmac->dma_tasklet);
+static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
+{
+	if (cpu_is_mx27())
+		return imxdma->hw_chaining;
+	else
+		return 0;
+}
+
+/*
+ * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
+ */
+static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+{
+	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+	unsigned long now;
+
+	now = min(imxdma->resbytes, sg->length);
+	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
+		imxdma->resbytes -= now;
+
+	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+	else
+		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+
+	imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+
+	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
+		"size 0x%08x\n", imxdmac->channel,
+		 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
+		 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
+		 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+
+	return now;
+}
+
+static int
+imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+		     unsigned int dma_length, unsigned int dev_addr,
+		     unsigned int dmamode)
+{
+	int channel = imxdmac->channel;
+
+	imxdmac->internal.sg = NULL;
+	imxdmac->internal.dma_mode = dmamode;
+
+	if (!dma_address) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if (!dma_length) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+			"dev_addr=0x%08x for read\n",
+			channel, __func__, (unsigned int)dma_address,
+			dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+		imx_dmav1_writel(dma_address, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+			"dev_addr=0x%08x for write\n",
+			channel, __func__, (unsigned int)dma_address,
+			dma_length, dev_addr);
+
+		imx_dmav1_writel(dma_address, DMA_SAR(channel));
+		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+				DMA_CCR(channel));
+	} else {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
+
+	return 0;
+}
+
+static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+{
+	int channel = imxdmac->channel;
+	unsigned long flags;
+
+	pr_debug("imxdma%d: imx_dma_enable\n", channel);
+
+	if (imxdmac->internal.in_use)
+		return;
+
+	local_irq_save(flags);
+
+	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
+		CCR_ACRPT, DMA_CCR(channel));
+
+	if ((cpu_is_mx21() || cpu_is_mx27()) &&
+			imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
+		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
+		if (imxdmac->internal.sg) {
+			u32 tmp;
+			imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+			tmp = imx_dmav1_readl(DMA_CCR(channel));
+			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
+				DMA_CCR(channel));
+		}
+	}
+	imxdmac->internal.in_use = 1;
+
+	local_irq_restore(flags);
+}
+
+static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
+{
+	int channel = imxdmac->channel;
+	unsigned long flags;
+
+	pr_debug("imxdma%d: imx_dma_disable\n", channel);
+
+	if (imxdma_hw_chain(&imxdmac->internal))
+		del_timer(&imxdmac->internal.watchdog);
+
+	local_irq_save(flags);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
+			DMA_CCR(channel));
+	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imxdmac->internal.in_use = 0;
+	local_irq_restore(flags);
+}
+
+static int
+imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
+	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
+{
+	int channel = imxdmac->channel;
+	u32 dreq = 0;
+
+	imxdmac->internal.hw_chaining = 0;
+
+	if (hw_chaining) {
+		imxdmac->internal.hw_chaining = 1;
+		if (!imxdma_hw_chain(&imxdmac->internal))
+			return -EINVAL;
+	}
+
+	if (dmareq)
+		dreq = CCR_REN;
+
+	imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
+	imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
+
+	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
+
+	return 0;
+}
+
+static int
+imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+		 struct scatterlist *sg, unsigned int sgcount,
+		 unsigned int dma_length, unsigned int dev_addr,
+		 unsigned int dmamode)
+{
+	int channel = imxdmac->channel;
+
+	if (imxdmac->internal.in_use)
+		return -EBUSY;
+
+	imxdmac->internal.sg = sg;
+	imxdmac->internal.dma_mode = dmamode;
+	imxdmac->internal.resbytes = dma_length;
+
+	if (!sg || !sgcount) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if (!sg->length) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+			"dev_addr=0x%08x for read\n",
+			channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+			"dev_addr=0x%08x for write\n",
+			channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
+	} else {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	imxdma_sg_next(imxdmac, sg);
+
+	return 0;
 }
 
-static void imxdma_err_handler(int channel, void *data, int error)
+static void imxdma_watchdog(unsigned long data)
 {
-	struct imxdma_channel *imxdmac = data;
+	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+	int channel = imxdmac->channel;
 
+	imx_dmav1_writel(0, DMA_CCR(channel));
+	imxdmac->internal.in_use = 0;
+	imxdmac->internal.sg = NULL;
+
+	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
+	pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+}
+
+static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
+{
+	struct imxdma_engine *imxdma = dev_id;
+	struct imxdma_channel_internal *internal;
+	unsigned int err_mask;
+	int i, disr;
+	int errcode;
+
+	disr = imx_dmav1_readl(DMA_DISR);
+
+	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
+		   imx_dmav1_readl(DMA_DRTOSR) |
+		   imx_dmav1_readl(DMA_DSESR)  |
+		   imx_dmav1_readl(DMA_DBOSR);
+
+	if (!err_mask)
+		return IRQ_HANDLED;
+
+	imx_dmav1_writel(disr & err_mask, DMA_DISR);
+
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+		if (!(err_mask & (1 << i)))
+			continue;
+		internal = &imxdma->channel[i].internal;
+		errcode = 0;
+
+		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DBTOSR);
+			errcode |= IMX_DMA_ERR_BURST;
+		}
+		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DRTOSR);
+			errcode |= IMX_DMA_ERR_REQUEST;
+		}
+		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DSESR);
+			errcode |= IMX_DMA_ERR_TRANSFER;
+		}
+		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DBOSR);
+			errcode |= IMX_DMA_ERR_BUFFER;
+		}
+		/* Tasklet error handler */
+		tasklet_schedule(&imxdma->channel[i].dma_tasklet);
+
+		printk(KERN_WARNING
+		       "DMA timeout on channel %d -%s%s%s%s\n", i,
+		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
+		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
+		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
+		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
+	}
+	return IRQ_HANDLED;
 }
 
-static void imxdma_progression(int channel, void *data,
-		struct scatterlist *sg)
+static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
-	struct imxdma_channel *imxdmac = data;
+	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+	int chno = imxdmac->channel;
+
+	if (imxdma->sg) {
+		u32 tmp;
+		imxdma->sg = sg_next(imxdma->sg);
+
+		if (imxdma->sg) {
+			imxdma_sg_next(imxdmac, imxdma->sg);
+
+			tmp = imx_dmav1_readl(DMA_CCR(chno));
+
+			if (imxdma_hw_chain(imxdma)) {
+				/* FIXME: The timeout should probably be
+				 * configurable
+				 */
+				mod_timer(&imxdma->watchdog,
+					jiffies + msecs_to_jiffies(500));
+
+				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
+				imx_dmav1_writel(tmp, DMA_CCR(chno));
+			} else {
+				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+				tmp |= CCR_CEN;
+			}
+
+			imx_dmav1_writel(tmp, DMA_CCR(chno));
+
+			if (imxdma_chan_is_doing_cyclic(imxdmac))
+				/* Tasklet progression */
+				tasklet_schedule(&imxdmac->dma_tasklet);
 
+			return;
+		}
+
+		if (imxdma_hw_chain(imxdma)) {
+			del_timer(&imxdma->watchdog);
+			return;
+		}
+	}
+
+	imx_dmav1_writel(0, DMA_CCR(chno));
+	imxdma->in_use = 0;
+	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
 
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+	struct imxdma_engine *imxdma = dev_id;
+	struct imxdma_channel_internal *internal;
+	int i, disr;
+
+	if (cpu_is_mx21() || cpu_is_mx27())
+		imxdma_err_handler(irq, dev_id);
+
+	disr = imx_dmav1_readl(DMA_DISR);
+
+	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
+		     disr);
+
+	imx_dmav1_writel(disr, DMA_DISR);
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+		if (disr & (1 << i)) {
+			internal = &imxdma->channel[i].internal;
+			dma_irq_handle_channel(&imxdma->channel[i]);
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
 static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -139,31 +596,24 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+		ret = imxdma_config_channel_hw(imxdmac,
 					  d->config_port, d->config_mem, 0, 0);
 		if (ret < 0)
 			return ret;
-		ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
+		ret = imxdma_setup_single_hw(imxdmac, d->src,
 					   d->len, d->dest, d->dmamode);
 		if (ret < 0)
 			return ret;
 		break;
+
+	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
-		ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
-							imxdma_progression);
-		if (ret < 0)
-			return ret;
-		/*
-		 * We fall through here since cyclic transfer is the same as
-		 * slave_sg adding a progression handler and a specific sg
-		 * configuration which is done in 'imxdma_prep_dma_cyclic'.
-		 */
 	case IMXDMA_DESC_SLAVE_SG:
 		if (d->dmamode == DMA_MODE_READ)
-			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
 				       d->sgcount, d->len, d->src, d->dmamode);
 		else
-			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
 				      d->sgcount, d->len, d->dest, d->dmamode);
 		if (ret < 0)
 			return ret;
@@ -171,7 +621,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	default:
 		return -EINVAL;
 	}
-	imx_dma_enable(imxdmac->imxdma_channel);
+	imxdma_enable_hw(imxdmac);
 	return 0;
 }
 
@@ -223,7 +673,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 
 	switch (cmd) {
 	case DMA_TERMINATE_ALL:
-		imx_dma_disable(imxdmac->imxdma_channel);
+		imxdma_disable_hw(imxdmac);
 
 		spin_lock_irqsave(&imxdmac->lock, flags);
 		list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
@@ -253,16 +703,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			mode = IMX_DMA_MEMSIZE_32;
 			break;
 		}
-		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+		ret = imxdma_config_channel_hw(imxdmac,
 				mode | IMX_DMA_TYPE_FIFO,
 				IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
 				imxdmac->dma_request, 1);
 
 		if (ret)
 			return ret;
-
-		imx_dma_config_burstlen(imxdmac->imxdma_channel,
-				imxdmac->watermark_level * imxdmac->word_size);
+		/* Set burst length */
+		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
+				 DMA_BLR(imxdmac->channel));
 
 		return 0;
 	default:
@@ -359,7 +809,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
 
 	spin_lock_irqsave(&imxdmac->lock, flags);
 
-	imx_dma_disable(imxdmac->imxdma_channel);
+	imxdma_disable_hw(imxdmac);
 	list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 	list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 
@@ -545,10 +995,51 @@ static void imxdma_issue_pending(struct dma_chan *chan)
 }
 
 static int __init imxdma_probe(struct platform_device *pdev)
-{
+	{
 	struct imxdma_engine *imxdma;
 	int ret, i;
 
+	if (cpu_is_mx1())
+		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+	else if (cpu_is_mx21())
+		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+	else if (cpu_is_mx27())
+		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+	else
+		return 0;
+
+	dma_clk = clk_get(NULL, "dma");
+	if (IS_ERR(dma_clk))
+		return PTR_ERR(dma_clk);
+	clk_enable(dma_clk);
+
+	/* reset DMA module */
+	imx_dmav1_writel(DCR_DRST, DMA_DCR);
+
+	if (cpu_is_mx1()) {
+		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
+		if (ret) {
+			pr_crit("Can't register IRQ for DMA\n");
+			return ret;
+		}
+
+		ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
+		if (ret) {
+			pr_crit("Can't register ERRIRQ for DMA\n");
+			free_irq(MX1_DMA_INT, NULL);
+			return ret;
+		}
+	}
+
+	/* enable DMA module */
+	imx_dmav1_writel(DCR_DEN, DMA_DCR);
+
+	/* clear all interrupts */
+	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+
+	/* disable interrupts */
+	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
+
 	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
 	if (!imxdma)
 		return -ENOMEM;
@@ -560,19 +1051,22 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
 
 	/* Initialize channel parameters */
-	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
-		imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
-				DMA_PRIO_MEDIUM);
-		if ((int)imxdmac->channel < 0) {
-			ret = -ENODEV;
-			goto err_init;
+		memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+		if (cpu_is_mx21() || cpu_is_mx27()) {
+			ret = request_irq(MX2x_INT_DMACH0 + i,
+					dma_irq_handler, 0, "DMA", imxdma);
+			if (ret) {
+				pr_crit("Can't register IRQ %d for DMA channel %d\n",
+						MX2x_INT_DMACH0 + i, i);
+				goto err_init;
+			}
+			init_timer(&imxdmac->internal.watchdog);
+			imxdmac->internal.watchdog.function = &imxdma_watchdog;
+			imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
 		}
 
-		imx_dma_setup_handlers(imxdmac->imxdma_channel,
-		       imxdma_irq_handler, imxdma_err_handler, imxdmac);
-
 		imxdmac->imxdma = imxdma;
 		spin_lock_init(&imxdmac->lock);
 
@@ -617,9 +1111,13 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	return 0;
 
 err_init:
-	while (--i >= 0) {
-		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-		imx_dma_free(imxdmac->imxdma_channel);
+
+	if (cpu_is_mx21() || cpu_is_mx27()) {
+		while (--i >= 0)
+			free_irq(MX2x_INT_DMACH0 + i, NULL);
+	} else if cpu_is_mx1() {
+		free_irq(MX1_DMA_INT, NULL);
+		free_irq(MX1_DMA_ERR, NULL);
 	}
 
 	kfree(imxdma);
@@ -633,10 +1131,12 @@ static int __exit imxdma_remove(struct platform_device *pdev)
 
         dma_async_device_unregister(&imxdma->dma_device);
 
-	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
-		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
-		 imx_dma_free(imxdmac->imxdma_channel);
+	if (cpu_is_mx21() || cpu_is_mx27()) {
+		for (i = 0; i < IMX_DMA_CHANNELS; i++)
+			free_irq(MX2x_INT_DMACH0 + i, NULL);
+	} else if cpu_is_mx1() {
+		free_irq(MX1_DMA_INT, NULL);
+		free_irq(MX1_DMA_ERR, NULL);
 	}
 
         kfree(imxdma);
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Fri Mar  9 10:20:38 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:38 +0100
Subject: [PATCH v3 02/13] dmaengine: imx-dma: remove data member from internal
 structure.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-3-git-send-email-javier.martin@vista-silicon.com>

Internal structure is just an auxiliary structure used for the initial
merge which is meant to be gone. As data member is not use anywhere
we can simply remove it.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index a34de17..a5bb9bd 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -132,7 +132,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	void *data;
 	unsigned int dma_mode;
 	struct scatterlist *sg;
 	unsigned int resbytes;
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Fri Mar  9 10:20:36 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:36 +0100
Subject: [PATCH v3 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
Message-ID: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>

The following series have to be applied on top of the following patches:
[PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
[PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.

As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
is deprecated and no new patches are accepted for it.

This series merges this code into the imx-dma.c dmaengine driver.

Notes for v3:
 - I send the whole series again despite some patches being the same. I think
 this is more comfortable for Vinod than just sending those patches that have
 been modified.
 - I've generated my series with the following command this time:
 'git format-patch -s -13 -M -B --subject-prefix="PATCH v3"' as suggested by
 Sascha but still removing two files in 01/13 generates a lot of noisy diffs.
 Sorry about that.
 - I don't include Sascha's Tested-by since maybe he wants to test this last
 version.

Changes since v2:
 - Alloc all DMA channels (16) instead of 8.
 - Free IRQs properly for i.MX1


[PATCH v3 01/13] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
[PATCH v3 02/13] dmaengine: imx-dma: remove data member from internal structure.
[PATCH v3 03/13] dmaengine: imx-dma: remove dma_mode member of internal structure.
[PATCH v3 04/13] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
[PATCH v3 05/13] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
[PATCH v3 06/13] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
[PATCH v3 07/13] dmaengine: imx-dma: remove sg member from internal structure.
[PATCH v3 08/13] dmaengine: imx-dma: remove 'in_use' field of 'internal' structure.
[PATCH v3 09/13] dmaengine: imx-dma: remove 'resbytes' field of 'internal' structure.
[PATCH v3 10/13] dmaengine: imx-dma: remove internal structure.
[PATCH v3 11/13] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
[PATCH v3 12/13] dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and 'dma_clk'.
[PATCH v3 13/13] dmaengine: imx-dma: use 'dev_dbg' and 'dev_warn' for messages.


From kgene.kim at samsung.com  Sat Mar 10 10:34:35 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 07:34:35 -0800
Subject: [GIT PULL] Samsung board stuff for v3.4
Message-ID: <4F5B748B.6050404@samsung.com>

Hi Arnd, Olof,

Please pull regarding Samsung board patches for v3.4.

Most are enabling some features(IPs) on each board and
one is adding new board file, Samsung Mobile's TRATS board.

If any problems, please let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

   Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/board-samsung

Andrzej Pietrasiewicz (2):
       ARM: EXYNOS: Register JPEG on universal_c210
       ARM: EXYNOS: Register JPEG on nuri

HeungJun, Kim (1):
       ARM: EXYNOS: Adds Samsung TRATS board support

Kamil Debski (2):
       ARM: EXYNOS: add G2D to mach-nuri
       ARM: EXYNOS: add G2D to mach-universal

Mark Brown (8):
       ARM: S3C64XX: Support GPIO LEDs on Cragganmore
       ARM: S3C64XX: Fix build of Cragganmore after SPI changes
       ARM: S3C64XX: Enable power management for disk on Cragganmore
       ARM: S3C64XX: Enable power management for WiFi on Cragganmore
       ARM: S3C64XX: Add hookup for Tomatin module on Cragganmore
       ARM: S3C64XX: Add a SPKVDD supply for CODECs on Cragganmore
       ARM: S3C64XX: Add some more Cragganmore module IDs to the table
       ARM: S3C64XX: Supply platform data for SPI on Cragganmore

MyungJoo Ham (1):
       ARM: EXYNOS: support Exynos4210-bus Devfreq driver on Nuri board

Sachin Kamat (13):
       ARM: EXYNOS: Enable G2D on ORIGEN
       ARM: S5PV210: Add missing FIMC media device to Aquila
       ARM: EXYNOS: Add missing FIMC media device to SMDKV310
       ARM: EXYNOS: Add missing FIMC media device to Origen
       ARM: EXYNOS: Enable G2D on SMDKV310
       ARM: S5PV210: Enable MFC on SMDKV210
       ARM: S5PV210: Enable MFC on SMDKC110
       ARM: S5PV210: Enable FIMC on SMDKV210
       ARM: S5PV210: Enable FIMC on SMDKC110
       ARM: EXYNOS: Enable JPEG on SMDKV310
       ARM: EXYNOS: Enable JPEG on Origen
       ARM: S5PV210: Add JPEG board definition
       ARM: S5PV210: Enable JPEG on SMDKV210

Sangwook Lee (1):
       ARM: EXYNOS: Enable Bluetooth on ORIGEN

Sylwester Nawrocki (3):
       ARM: EXYNOS: Increase virtual framebuffer size on Universal C210 
board
       ARM: EXYNOS: Add support for S5K6AAFX image sensor on Universal 
C210 board
       ARM: SAMSUNG: Add support for S5K6AAFX camera on Nuri board

Tushar Behera (2):
       ARM: EXYNOS: Add __init attribute to nuri_camera_init()
       ARM: EXYNOS: Add __init attribute to universal_camera_init()

  arch/arm/mach-exynos/Kconfig                 |   21 ++
  arch/arm/mach-exynos/Makefile                |    1 +
  arch/arm/mach-exynos/mach-nuri.c             |   80 ++++++-
  arch/arm/mach-exynos/mach-origen.c           |   37 +++
  arch/arm/mach-exynos/mach-smdkv310.c         |    3 +
  arch/arm/mach-exynos/mach-trats.c            |  344 
++++++++++++++++++++++++++
  arch/arm/mach-exynos/mach-universal_c210.c   |   80 ++++++-
  arch/arm/mach-s3c64xx/Kconfig                |    1 +
  arch/arm/mach-s3c64xx/mach-crag6410-module.c |   31 +++-
  arch/arm/mach-s3c64xx/mach-crag6410.c        |   67 +++++-
  arch/arm/mach-s5pv210/Kconfig                |    9 +
  arch/arm/mach-s5pv210/clock.c                |    5 +
  arch/arm/mach-s5pv210/include/mach/map.h     |    4 +
  arch/arm/mach-s5pv210/mach-aquila.c          |    1 +
  arch/arm/mach-s5pv210/mach-smdkc110.c        |   14 +
  arch/arm/mach-s5pv210/mach-smdkv210.c        |   15 ++
  16 files changed, 702 insertions(+), 11 deletions(-)
  create mode 100644 arch/arm/mach-exynos/mach-trats.c


From kgene.kim at samsung.com  Fri Mar  9 11:04:04 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 09 Mar 2012 08:04:04 -0800
Subject: [PATCH 0/4] ARM: SAMSUNG: Add __init attribute to functions
 calling s3c_set_platdata
In-Reply-To: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
References: <1330593446-663-1-git-send-email-tushar.behera@linaro.org>
Message-ID: <4F5A29F4.7020308@samsung.com>

On 03/01/12 01:17, Tushar Behera wrote:
> The function s3c_set_platdata is defined with __init attribute, hence the
> functions calling s3c_set_platdata should also be defined with __init
> attribute.
>
> Even though all the modified functions are called from xxx_machine_init()
> functions, it is still better to define each of them with __init attribute.
>
> Tushar Behera (4):
>    ARM: EXYNOS: Add __init attribute to nuri_camera_init()
>    ARM: EXYNOS: Add __init attribute to universal_camera_init()
>    ARM: SAMSUNG: Add __init attribute to samsung_bl_set()
>    ARM: SAMSUNG: Add __init attribute to xxx_set_platdata() wrappers
>
>   arch/arm/mach-exynos/mach-nuri.c           |    2 +-
>   arch/arm/mach-exynos/mach-universal_c210.c |    2 +-
>   arch/arm/plat-samsung/dev-backlight.c      |    2 +-
>   arch/arm/plat-samsung/devs.c               |    4 ++--
>   4 files changed, 5 insertions(+), 5 deletions(-)
>
Looks good to me, applied.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From javier.martin at vista-silicon.com  Fri Mar  9 03:00:35 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Fri, 9 Mar 2012 09:00:35 +0100
Subject: [PATCH v2 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <20120308200448.GR3852@pengutronix.de>
References: <1331130825-14947-1-git-send-email-javier.martin@vista-silicon.com>
 <20120308200448.GR3852@pengutronix.de>
Message-ID: <CACKLOr2_y9aw+-79d4FfKsOuiDdOvDHAanQ6j+qF4Ynf2r5rag@mail.gmail.com>

Hi Sascha,

On 8 March 2012 21:04, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Wed, Mar 07, 2012 at 03:33:32PM +0100, Javier Martin wrote:
>> The following series have to be applied on top of the following patches:
>> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
>> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
>>
>> As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
>> is deprecated and no new patches are accepted for it.
>>
>> This series merges this code into the imx-dma.c dmaengine driver.
>>
>
> I can't find a branch to apply this on. Could you provide a git tree?

I'm developing and testing here:

git://git.infradead.org/users/vkoul/slave-dma.git next

> If you have to repost this series please consider using -M with git
> format-patch.

OK, thanks for the suggestion.

Regards.
-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From kgene.kim at samsung.com  Sun Mar 11 04:02:30 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 00:02:30 -0800
Subject: [GIT PULL] Samsung board stuff for v3.4
In-Reply-To: <CAOesGMjiYDFhkjS=2e+3YdPJHExupt3Wm_NS3x1XW-17eEZM=A@mail.gmail.com>
References: <4F5B748B.6050404@samsung.com>
 <CAOesGMjiYDFhkjS=2e+3YdPJHExupt3Wm_NS3x1XW-17eEZM=A@mail.gmail.com>
Message-ID: <4F5C5C16.6020106@samsung.com>

On 03/10/12 09:45, Olof Johansson wrote:
> Hi,
>
> On Sat, Mar 10, 2012 at 7:34 AM, Kukjin Kim<kgene.kim at samsung.com>  wrote:
>> Hi Arnd, Olof,
>>
>> Please pull regarding Samsung board patches for v3.4.
>>
>> Most are enabling some features(IPs) on each board and
>> one is adding new board file, Samsung Mobile's TRATS board.
>
> Given that exynos has started conversion to device tree, there should
> not be any  additions of non-devicetree-probed board files being
> added.
>
> At the very least, you should move over to using DT_MACHINE instead of
> MACHINE for the new board, and probe using device tree. Even better
> would be if you added support for this board through mach-exynos4-dt.c
> instead of adding a brand new board file.
>
> I also see a large number of the same additions of devices, done to a
> number of board files. I don't think you need to rework those patches
> now, but please consider how you can make it less "churny" to add a
> device on the SoC in the future without touching all board files.
>
>
> If you rebase without the board file addition I can take the rest of
> the branch while that part is being reworked. Please send a new pull
> request with the rebased tree.
>
OK, I see. let me send a new pull request soon as per your suggestion.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From plagnioj at jcrosoft.com  Fri Mar  9 04:58:34 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 9 Mar 2012 10:58:34 +0100
Subject: [PATCH v10] Regulator: Add Anatop regulator driver
In-Reply-To: <4F59B899.2080704@linaro.org>
References: <1331200744-5986-1-git-send-email-paul.liu@linaro.org>
 <20120308141847.GG27213@game.jcrosoft.org>
 <4F59B899.2080704@linaro.org>
Message-ID: <20120309095834.GM27213@game.jcrosoft.org>

On 16:00 Fri 09 Mar     , Ying-Chun Liu (PaulLiu) wrote:
> (2012?03?08? 22:18), Jean-Christophe PLAGNIOL-VILLARD wrote:
> >> +static int __devexit anatop_regulator_remove(struct platform_device *pdev)
> >> +{
> >> +	struct regulator_dev *rdev = platform_get_drvdata(pdev);
> >> +	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
> >> +	kfree(sreg->name);
> >> +	regulator_unregister(rdev);
> > return from the unregister
> >> +	return 0;
> >> +}
> > Best Regards,
> > J.
> 
> Hi Jean-Christophe,
> 
> I've modify the patch based on your review. However, the last one cannot
> be made because regulator_unregister is void return.
so we have a issue here regulator_unregister MUST return an error conde

Best Regards,
J.


From kgene.kim at samsung.com  Sun Mar 11 04:09:56 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sun, 11 Mar 2012 00:09:56 -0800
Subject: [GIT PULL 4/4] Samsung devel-dma for v3.4
In-Reply-To: <20120310182149.GA656@quad.lixom.net>
References: <4F5B7CA7.2010604@samsung.com>
 <20120310182149.GA656@quad.lixom.net>
Message-ID: <4F5C5DD4.60309@samsung.com>

On 03/10/12 10:21, Olof Johansson wrote:
> On Sat, Mar 10, 2012 at 08:09:11AM -0800, Kukjin Kim wrote:
>> Hi Arnd, Olof,
>>
>> This is for Samsung dma stuff for v3.4 and depends on following:
>>    next/cleanup-use-static
>>    next/cleanup-exynos-clock
>>
>> Please pull from:
>
>> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> next/devel-samsung-dma
>>
>> And conflicts will be happened in clock part. Here is my preferred
>> resolution. The mach-exynos/clock.c can be removed with following:
>>
>> arch/arm/mach-exynos/exynos-clock4.c
>
> Hi,
>
> given my feedback on the cleanup-exynos-clock pull request, I'm holding off on
> this one waiting on you to do the resolution of the conflicts. :-)
>
Yes, your suggestion can avoid bad conflicts.

Olof, let me rebase this on top of new cleanup-exynos-clock you 
suggested and will send a new pull request.

Thanks.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From plagnioj at jcrosoft.com  Mon Mar 12 11:17:02 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Mon, 12 Mar 2012 16:17:02 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <201203121625.50283.sr@denx.de>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <20120312143825.GB13869@game.jcrosoft.org>
 <201203121625.50283.sr@denx.de>
Message-ID: <20120312151702.GD13869@game.jcrosoft.org>

On 16:25 Mon 12 Mar     , Stefan Roese wrote:
> On Monday 12 March 2012 15:38:25 Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > @@ -58,6 +94,22 @@ static int stmmac_pltfr_probe(struct platform_device
> > > *pdev)
> > > 
> > >  		ret = -ENOMEM;
> > >  		goto out_release_region;
> > >  	
> > >  	}
> > > 
> > > +
> > > +#ifdef CONFIG_OF
> > > +	plat_dat = devm_kzalloc(&pdev->dev, sizeof(struct
> > > plat_stmmacenet_data), +				GFP_KERNEL);
> > > +	if (!plat_dat) {
> > > +		pr_err("%s: ERROR: no memory", __func__);
> > > +		ret = -ENOMEM;
> > > +		goto out_unmap;
> > > +	}
> > > +
> > > +	ret = stmmac_probe_config_dt(pdev, plat_dat, &mac);
> > > +	if (ret) {
> > > +		pr_err("%s: main dt probe failed", __func__);
> > > +		goto out_unmap;
> > > +	}
> > > +#else
> > 
> > This must be check at runtime, we can boot a kernel with or without DT.
> 
> Are you referring to using "if (pdev->dev.of_node)" to distinguish between DT 
> and non-DT version instead of this #ifdef?
yes

Best Regards,
J.


From alan at signal11.us  Sat Mar 10 16:38:51 2012
From: alan at signal11.us (Alan Ott)
Date: Sat, 10 Mar 2012 16:38:51 -0500
Subject: [PATCH v2 1/2] ARM: AT91: Add parameter for AT91_HAS_PATA
In-Reply-To: <1331415380-10928-1-git-send-email-alan@signal11.us>
References: <1331415380-10928-1-git-send-email-alan@signal11.us>
Message-ID: <1331415531-10961-1-git-send-email-alan@signal11.us>

Not all at91 chips have PATA, this parameter will identify which
chips do. The determining of which chips support PATA was done
by Arnd Bergmann.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
CC: Ben Dooks <ben-linux at fluff.org>
---
 arch/arm/mach-at91/Kconfig |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 71feb00..9eeeabe 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -24,6 +24,9 @@ config AT91_SAM9_ALT_RESET
 config AT91_SAM9G45_RESET
 	bool
 
+config AT91_HAS_PATA
+	bool
+
 menu "Atmel AT91 System-on-Chip"
 
 choice
@@ -46,6 +49,7 @@ config ARCH_AT91SAM9260
 	select HAVE_AT91_USART5
 	select HAVE_NET_MACB
 	select AT91_SAM9_ALT_RESET
+	select AT91_HAS_PATA
 
 config ARCH_AT91SAM9261
 	bool "AT91SAM9261"
@@ -54,6 +58,7 @@ config ARCH_AT91SAM9261
 	select HAVE_FB_ATMEL
 	select HAVE_AT91_DBGU0
 	select AT91_SAM9_ALT_RESET
+	select AT91_HAS_PATA
 
 config ARCH_AT91SAM9G10
 	bool "AT91SAM9G10"
@@ -62,6 +67,7 @@ config ARCH_AT91SAM9G10
 	select HAVE_AT91_DBGU0
 	select HAVE_FB_ATMEL
 	select AT91_SAM9_ALT_RESET
+	select AT91_HAS_PATA
 
 config ARCH_AT91SAM9263
 	bool "AT91SAM9263"
@@ -71,6 +77,7 @@ config ARCH_AT91SAM9263
 	select HAVE_NET_MACB
 	select HAVE_AT91_DBGU1
 	select AT91_SAM9_ALT_RESET
+	select AT91_HAS_PATA
 
 config ARCH_AT91SAM9RL
 	bool "AT91SAM9RL"
@@ -80,6 +87,7 @@ config ARCH_AT91SAM9RL
 	select HAVE_FB_ATMEL
 	select HAVE_AT91_DBGU0
 	select AT91_SAM9_ALT_RESET
+	select AT91_HAS_PATA
 
 config ARCH_AT91SAM9G20
 	bool "AT91SAM9G20"
@@ -91,6 +99,7 @@ config ARCH_AT91SAM9G20
 	select HAVE_AT91_USART5
 	select HAVE_NET_MACB
 	select AT91_SAM9_ALT_RESET
+	select AT91_HAS_PATA
 
 config ARCH_AT91SAM9G45
 	bool "AT91SAM9G45"
@@ -101,6 +110,7 @@ config ARCH_AT91SAM9G45
 	select HAVE_NET_MACB
 	select HAVE_AT91_DBGU1
 	select AT91_SAM9G45_RESET
+	select AT91_HAS_PATA
 
 config ARCH_AT91CAP9
 	bool "AT91CAP9"
@@ -110,6 +120,7 @@ config ARCH_AT91CAP9
 	select HAVE_NET_MACB
 	select HAVE_AT91_DBGU1
 	select AT91_SAM9G45_RESET
+	select AT91_HAS_PATA
 
 config ARCH_AT91X40
 	bool "AT91x40"
-- 
1.7.0.4



From kgene.kim at samsung.com  Sat Mar 10 05:19:07 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 02:19:07 -0800
Subject: [PATCH 3/5] ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock
In-Reply-To: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>
References: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331374749-23256-4-git-send-email-kgene.kim@samsung.com>

This patch changes prefix of the clk register from S5P_ to
EXYNOS4_ for new EXYNOS SoCs such as EXYNOS5 and adds prefix
exynos4_ on clk declarations.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/clock-exynos4.c           | 1028 ++++++++++++------------
 arch/arm/mach-exynos/clock-exynos4.h           |   15 +-
 arch/arm/mach-exynos/clock-exynos4210.c        |   44 +-
 arch/arm/mach-exynos/clock-exynos4212.c        |   28 +-
 arch/arm/mach-exynos/common.h                  |    9 +
 arch/arm/mach-exynos/include/mach/regs-clock.h |  364 +++++-----
 arch/arm/mach-exynos/pm.c                      |   40 +-
 7 files changed, 766 insertions(+), 762 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 7dde81b..8ebf411 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
  * EXYNOS4 - Clock support
@@ -31,85 +31,85 @@
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4_clock_save[] = {
-	SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
-	SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
-	SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
-	SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-	SAVE_ITEM(S5P_CLKSRC_TOP0),
-	SAVE_ITEM(S5P_CLKSRC_TOP1),
-	SAVE_ITEM(S5P_CLKSRC_CAM),
-	SAVE_ITEM(S5P_CLKSRC_TV),
-	SAVE_ITEM(S5P_CLKSRC_MFC),
-	SAVE_ITEM(S5P_CLKSRC_G3D),
-	SAVE_ITEM(S5P_CLKSRC_LCD0),
-	SAVE_ITEM(S5P_CLKSRC_MAUDIO),
-	SAVE_ITEM(S5P_CLKSRC_FSYS),
-	SAVE_ITEM(S5P_CLKSRC_PERIL0),
-	SAVE_ITEM(S5P_CLKSRC_PERIL1),
-	SAVE_ITEM(S5P_CLKDIV_CAM),
-	SAVE_ITEM(S5P_CLKDIV_TV),
-	SAVE_ITEM(S5P_CLKDIV_MFC),
-	SAVE_ITEM(S5P_CLKDIV_G3D),
-	SAVE_ITEM(S5P_CLKDIV_LCD0),
-	SAVE_ITEM(S5P_CLKDIV_MAUDIO),
-	SAVE_ITEM(S5P_CLKDIV_FSYS0),
-	SAVE_ITEM(S5P_CLKDIV_FSYS1),
-	SAVE_ITEM(S5P_CLKDIV_FSYS2),
-	SAVE_ITEM(S5P_CLKDIV_FSYS3),
-	SAVE_ITEM(S5P_CLKDIV_PERIL0),
-	SAVE_ITEM(S5P_CLKDIV_PERIL1),
-	SAVE_ITEM(S5P_CLKDIV_PERIL2),
-	SAVE_ITEM(S5P_CLKDIV_PERIL3),
-	SAVE_ITEM(S5P_CLKDIV_PERIL4),
-	SAVE_ITEM(S5P_CLKDIV_PERIL5),
-	SAVE_ITEM(S5P_CLKDIV_TOP),
-	SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
-	SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
-	SAVE_ITEM(S5P_CLKSRC_MASK_TV),
-	SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
-	SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
-	SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
-	SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
-	SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
-	SAVE_ITEM(S5P_CLKDIV2_RATIO),
-	SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
-	SAVE_ITEM(S5P_CLKGATE_IP_CAM),
-	SAVE_ITEM(S5P_CLKGATE_IP_TV),
-	SAVE_ITEM(S5P_CLKGATE_IP_MFC),
-	SAVE_ITEM(S5P_CLKGATE_IP_G3D),
-	SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
-	SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
-	SAVE_ITEM(S5P_CLKGATE_IP_GPS),
-	SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
-	SAVE_ITEM(S5P_CLKGATE_BLOCK),
-	SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
-	SAVE_ITEM(S5P_CLKSRC_DMC),
-	SAVE_ITEM(S5P_CLKDIV_DMC0),
-	SAVE_ITEM(S5P_CLKDIV_DMC1),
-	SAVE_ITEM(S5P_CLKGATE_IP_DMC),
-	SAVE_ITEM(S5P_CLKSRC_CPU),
-	SAVE_ITEM(S5P_CLKDIV_CPU),
-	SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
-	SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
-	SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+	SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
+	SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
+	SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
+	SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
+	SAVE_ITEM(EXYNOS4_CLKSRC_TV),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
+	SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
+	SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
+	SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
+	SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
+	SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
+	SAVE_ITEM(EXYNOS4_CLKDIV_TV),
+	SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
+	SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
+	SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
+	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
+	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
+	SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
+	SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
+	SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
+	SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
+	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
+	SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
+	SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
+	SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
+	SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
+	SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
+	SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
+	SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
+	SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
 };
 #endif
 
-static struct clk clk_sclk_hdmi27m = {
+static struct clk exynos4_clk_sclk_hdmi27m = {
 	.name		= "sclk_hdmi27m",
 	.rate		= 27000000,
 };
 
-static struct clk clk_sclk_hdmiphy = {
+static struct clk exynos4_clk_sclk_hdmiphy = {
 	.name		= "sclk_hdmiphy",
 };
 
-static struct clk clk_sclk_usbphy0 = {
+static struct clk exynos4_clk_sclk_usbphy0 = {
 	.name		= "sclk_usbphy0",
 	.rate		= 27000000,
 };
 
-static struct clk clk_sclk_usbphy1 = {
+static struct clk exynos4_clk_sclk_usbphy1 = {
 	.name		= "sclk_usbphy1",
 };
 
@@ -120,82 +120,82 @@ static struct clk dummy_apb_pclk = {
 
 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
 }
 
 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
 }
 
 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
 }
 
 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
 }
 
 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
 }
 
 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
 }
 
 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
 }
 
 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
 }
 
 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
 }
 
 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
 }
 
 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
 }
 
 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
 }
 
 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
+	return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
 }
 
 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
 }
 
 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
 }
 
 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
 }
 
 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
@@ -210,31 +210,31 @@ static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 
 /* Core list of CMU_CPU side */
 
-static struct clksrc_clk clk_mout_apll = {
+static struct clksrc_clk exynos4_clk_mout_apll = {
 	.clk	= {
 		.name		= "mout_apll",
 	},
 	.sources = &clk_src_apll,
-	.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
+	.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
 };
 
-static struct clksrc_clk clk_sclk_apll = {
+static struct clksrc_clk exynos4_clk_sclk_apll = {
 	.clk	= {
 		.name		= "sclk_apll",
-		.parent		= &clk_mout_apll.clk,
+		.parent		= &exynos4_clk_mout_apll.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
 };
 
-static struct clksrc_clk clk_mout_epll = {
+static struct clksrc_clk exynos4_clk_mout_epll = {
 	.clk	= {
 		.name		= "mout_epll",
 	},
 	.sources = &clk_src_epll,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
 };
 
-struct clksrc_clk clk_mout_mpll = {
+struct clksrc_clk exynos4_clk_mout_mpll = {
 	.clk	= {
 		.name		= "mout_mpll",
 	},
@@ -243,221 +243,221 @@ struct clksrc_clk clk_mout_mpll = {
 	/* reg_src will be added in each SoCs' clock */
 };
 
-static struct clk *clkset_moutcore_list[] = {
-	[0] = &clk_mout_apll.clk,
-	[1] = &clk_mout_mpll.clk,
+static struct clk *exynos4_clkset_moutcore_list[] = {
+	[0] = &exynos4_clk_mout_apll.clk,
+	[1] = &exynos4_clk_mout_mpll.clk,
 };
 
-static struct clksrc_sources clkset_moutcore = {
-	.sources	= clkset_moutcore_list,
-	.nr_sources	= ARRAY_SIZE(clkset_moutcore_list),
+static struct clksrc_sources exynos4_clkset_moutcore = {
+	.sources	= exynos4_clkset_moutcore_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_moutcore_list),
 };
 
-static struct clksrc_clk clk_moutcore = {
+static struct clksrc_clk exynos4_clk_moutcore = {
 	.clk	= {
 		.name		= "moutcore",
 	},
-	.sources = &clkset_moutcore,
-	.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
+	.sources = &exynos4_clkset_moutcore,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
 };
 
-static struct clksrc_clk clk_coreclk = {
+static struct clksrc_clk exynos4_clk_coreclk = {
 	.clk	= {
 		.name		= "core_clk",
-		.parent		= &clk_moutcore.clk,
+		.parent		= &exynos4_clk_moutcore.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
 };
 
-static struct clksrc_clk clk_armclk = {
+static struct clksrc_clk exynos4_clk_armclk = {
 	.clk	= {
 		.name		= "armclk",
-		.parent		= &clk_coreclk.clk,
+		.parent		= &exynos4_clk_coreclk.clk,
 	},
 };
 
-static struct clksrc_clk clk_aclk_corem0 = {
+static struct clksrc_clk exynos4_clk_aclk_corem0 = {
 	.clk	= {
 		.name		= "aclk_corem0",
-		.parent		= &clk_coreclk.clk,
+		.parent		= &exynos4_clk_coreclk.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_cores = {
+static struct clksrc_clk exynos4_clk_aclk_cores = {
 	.clk	= {
 		.name		= "aclk_cores",
-		.parent		= &clk_coreclk.clk,
+		.parent		= &exynos4_clk_coreclk.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_corem1 = {
+static struct clksrc_clk exynos4_clk_aclk_corem1 = {
 	.clk	= {
 		.name		= "aclk_corem1",
-		.parent		= &clk_coreclk.clk,
+		.parent		= &exynos4_clk_coreclk.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
 };
 
-static struct clksrc_clk clk_periphclk = {
+static struct clksrc_clk exynos4_clk_periphclk = {
 	.clk	= {
 		.name		= "periphclk",
-		.parent		= &clk_coreclk.clk,
+		.parent		= &exynos4_clk_coreclk.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
 };
 
 /* Core list of CMU_CORE side */
 
-static struct clk *clkset_corebus_list[] = {
-	[0] = &clk_mout_mpll.clk,
-	[1] = &clk_sclk_apll.clk,
+static struct clk *exynos4_clkset_corebus_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
 };
 
-struct clksrc_sources clkset_mout_corebus = {
-	.sources	= clkset_corebus_list,
-	.nr_sources	= ARRAY_SIZE(clkset_corebus_list),
+struct clksrc_sources exynos4_clkset_mout_corebus = {
+	.sources	= exynos4_clkset_corebus_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_corebus_list),
 };
 
-static struct clksrc_clk clk_mout_corebus = {
+static struct clksrc_clk exynos4_clk_mout_corebus = {
 	.clk	= {
 		.name		= "mout_corebus",
 	},
-	.sources = &clkset_mout_corebus,
-	.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
+	.sources = &exynos4_clkset_mout_corebus,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
 };
 
-static struct clksrc_clk clk_sclk_dmc = {
+static struct clksrc_clk exynos4_clk_sclk_dmc = {
 	.clk	= {
 		.name		= "sclk_dmc",
-		.parent		= &clk_mout_corebus.clk,
+		.parent		= &exynos4_clk_mout_corebus.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_cored = {
+static struct clksrc_clk exynos4_clk_aclk_cored = {
 	.clk	= {
 		.name		= "aclk_cored",
-		.parent		= &clk_sclk_dmc.clk,
+		.parent		= &exynos4_clk_sclk_dmc.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_corep = {
+static struct clksrc_clk exynos4_clk_aclk_corep = {
 	.clk	= {
 		.name		= "aclk_corep",
-		.parent		= &clk_aclk_cored.clk,
+		.parent		= &exynos4_clk_aclk_cored.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_acp = {
+static struct clksrc_clk exynos4_clk_aclk_acp = {
 	.clk	= {
 		.name		= "aclk_acp",
-		.parent		= &clk_mout_corebus.clk,
+		.parent		= &exynos4_clk_mout_corebus.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
 };
 
-static struct clksrc_clk clk_pclk_acp = {
+static struct clksrc_clk exynos4_clk_pclk_acp = {
 	.clk	= {
 		.name		= "pclk_acp",
-		.parent		= &clk_aclk_acp.clk,
+		.parent		= &exynos4_clk_aclk_acp.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
 };
 
 /* Core list of CMU_TOP side */
 
-struct clk *clkset_aclk_top_list[] = {
-	[0] = &clk_mout_mpll.clk,
-	[1] = &clk_sclk_apll.clk,
+struct clk *exynos4_clkset_aclk_top_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources clkset_aclk = {
-	.sources	= clkset_aclk_top_list,
-	.nr_sources	= ARRAY_SIZE(clkset_aclk_top_list),
+static struct clksrc_sources exynos4_clkset_aclk = {
+	.sources	= exynos4_clkset_aclk_top_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_aclk_top_list),
 };
 
-static struct clksrc_clk clk_aclk_200 = {
+static struct clksrc_clk exynos4_clk_aclk_200 = {
 	.clk	= {
 		.name		= "aclk_200",
 	},
-	.sources = &clkset_aclk,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
-	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_100 = {
+static struct clksrc_clk exynos4_clk_aclk_100 = {
 	.clk	= {
 		.name		= "aclk_100",
 	},
-	.sources = &clkset_aclk,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
-	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
 };
 
-static struct clksrc_clk clk_aclk_160 = {
+static struct clksrc_clk exynos4_clk_aclk_160 = {
 	.clk	= {
 		.name		= "aclk_160",
 	},
-	.sources = &clkset_aclk,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
-	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
 };
 
-struct clksrc_clk clk_aclk_133 = {
+struct clksrc_clk exynos4_clk_aclk_133 = {
 	.clk	= {
 		.name		= "aclk_133",
 	},
-	.sources = &clkset_aclk,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
-	.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
+	.sources = &exynos4_clkset_aclk,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
 };
 
-static struct clk *clkset_vpllsrc_list[] = {
+static struct clk *exynos4_clkset_vpllsrc_list[] = {
 	[0] = &clk_fin_vpll,
-	[1] = &clk_sclk_hdmi27m,
+	[1] = &exynos4_clk_sclk_hdmi27m,
 };
 
-static struct clksrc_sources clkset_vpllsrc = {
-	.sources	= clkset_vpllsrc_list,
-	.nr_sources	= ARRAY_SIZE(clkset_vpllsrc_list),
+static struct clksrc_sources exynos4_clkset_vpllsrc = {
+	.sources	= exynos4_clkset_vpllsrc_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
 };
 
-static struct clksrc_clk clk_vpllsrc = {
+static struct clksrc_clk exynos4_clk_vpllsrc = {
 	.clk	= {
 		.name		= "vpll_src",
 		.enable		= exynos4_clksrc_mask_top_ctrl,
 		.ctrlbit	= (1 << 0),
 	},
-	.sources = &clkset_vpllsrc,
-	.reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
+	.sources = &exynos4_clkset_vpllsrc,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
 };
 
-static struct clk *clkset_sclk_vpll_list[] = {
-	[0] = &clk_vpllsrc.clk,
+static struct clk *exynos4_clkset_sclk_vpll_list[] = {
+	[0] = &exynos4_clk_vpllsrc.clk,
 	[1] = &clk_fout_vpll,
 };
 
-static struct clksrc_sources clkset_sclk_vpll = {
-	.sources	= clkset_sclk_vpll_list,
-	.nr_sources	= ARRAY_SIZE(clkset_sclk_vpll_list),
+static struct clksrc_sources exynos4_clkset_sclk_vpll = {
+	.sources	= exynos4_clkset_sclk_vpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
 };
 
-static struct clksrc_clk clk_sclk_vpll = {
+static struct clksrc_clk exynos4_clk_sclk_vpll = {
 	.clk	= {
 		.name		= "sclk_vpll",
 	},
-	.sources = &clkset_sclk_vpll,
-	.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
+	.sources = &exynos4_clkset_sclk_vpll,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
 };
 
-static struct clk init_clocks_off[] = {
+static struct clk exynos4_init_clocks_off[] = {
 	{
 		.name		= "timers",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1<<24),
 	}, {
@@ -498,30 +498,30 @@ static struct clk init_clocks_off[] = {
 	}, {
 		.name		= "hsmmc",
 		.devname	= "s3c-sdhci.0",
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 5),
 	}, {
 		.name		= "hsmmc",
 		.devname	= "s3c-sdhci.1",
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 6),
 	}, {
 		.name		= "hsmmc",
 		.devname	= "s3c-sdhci.2",
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 7),
 	}, {
 		.name		= "hsmmc",
 		.devname	= "s3c-sdhci.3",
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 8),
 	}, {
 		.name		= "dwmmc",
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 9),
 	}, {
@@ -568,7 +568,7 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= (1 << 15),
 	}, {
 		.name		= "watchdog",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_perir_ctrl,
 		.ctrlbit	= (1 << 14),
 	}, {
@@ -626,55 +626,55 @@ static struct clk init_clocks_off[] = {
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.0",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 6),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.1",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 7),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.2",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 8),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.3",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 9),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.4",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 10),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.5",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 11),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.6",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 12),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-i2c.7",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 13),
 	}, {
 		.name		= "i2c",
 		.devname	= "s3c2440-hdmiphy-i2c",
-		.parent		= &clk_aclk_100.clk,
+		.parent		= &exynos4_clk_aclk_100.clk,
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 14),
 	}, {
@@ -736,7 +736,7 @@ static struct clk init_clocks_off[] = {
 	}
 };
 
-static struct clk init_clocks[] = {
+static struct clk exynos4_init_clocks_on[] = {
 	{
 		.name		= "uart",
 		.devname	= "s5pv210-uart.0",
@@ -770,259 +770,259 @@ static struct clk init_clocks[] = {
 	}
 };
 
-static struct clk clk_pdma0 = {
+static struct clk exynos4_clk_pdma0 = {
 	.name		= "dma",
 	.devname	= "dma-pl330.0",
 	.enable		= exynos4_clk_ip_fsys_ctrl,
 	.ctrlbit	= (1 << 0),
 };
 
-static struct clk clk_pdma1 = {
+static struct clk exynos4_clk_pdma1 = {
 	.name		= "dma",
 	.devname	= "dma-pl330.1",
 	.enable		= exynos4_clk_ip_fsys_ctrl,
 	.ctrlbit	= (1 << 1),
 };
 
-struct clk *clkset_group_list[] = {
+struct clk *exynos4_clkset_group_list[] = {
 	[0] = &clk_ext_xtal_mux,
 	[1] = &clk_xusbxti,
-	[2] = &clk_sclk_hdmi27m,
-	[3] = &clk_sclk_usbphy0,
-	[4] = &clk_sclk_usbphy1,
-	[5] = &clk_sclk_hdmiphy,
-	[6] = &clk_mout_mpll.clk,
-	[7] = &clk_mout_epll.clk,
-	[8] = &clk_sclk_vpll.clk,
+	[2] = &exynos4_clk_sclk_hdmi27m,
+	[3] = &exynos4_clk_sclk_usbphy0,
+	[4] = &exynos4_clk_sclk_usbphy1,
+	[5] = &exynos4_clk_sclk_hdmiphy,
+	[6] = &exynos4_clk_mout_mpll.clk,
+	[7] = &exynos4_clk_mout_epll.clk,
+	[8] = &exynos4_clk_sclk_vpll.clk,
 };
 
-struct clksrc_sources clkset_group = {
-	.sources	= clkset_group_list,
-	.nr_sources	= ARRAY_SIZE(clkset_group_list),
+struct clksrc_sources exynos4_clkset_group = {
+	.sources	= exynos4_clkset_group_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_group_list),
 };
 
-static struct clk *clkset_mout_g2d0_list[] = {
-	[0] = &clk_mout_mpll.clk,
-	[1] = &clk_sclk_apll.clk,
+static struct clk *exynos4_clkset_mout_g2d0_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources clkset_mout_g2d0 = {
-	.sources	= clkset_mout_g2d0_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_g2d0_list),
+static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
+	.sources	= exynos4_clkset_mout_g2d0_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
 };
 
-static struct clksrc_clk clk_mout_g2d0 = {
+static struct clksrc_clk exynos4_clk_mout_g2d0 = {
 	.clk	= {
 		.name		= "mout_g2d0",
 	},
-	.sources = &clkset_mout_g2d0,
-	.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+	.sources = &exynos4_clkset_mout_g2d0,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 };
 
-static struct clk *clkset_mout_g2d1_list[] = {
-	[0] = &clk_mout_epll.clk,
-	[1] = &clk_sclk_vpll.clk,
+static struct clk *exynos4_clkset_mout_g2d1_list[] = {
+	[0] = &exynos4_clk_mout_epll.clk,
+	[1] = &exynos4_clk_sclk_vpll.clk,
 };
 
-static struct clksrc_sources clkset_mout_g2d1 = {
-	.sources	= clkset_mout_g2d1_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_g2d1_list),
+static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
+	.sources	= exynos4_clkset_mout_g2d1_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
 };
 
-static struct clksrc_clk clk_mout_g2d1 = {
+static struct clksrc_clk exynos4_clk_mout_g2d1 = {
 	.clk	= {
 		.name		= "mout_g2d1",
 	},
-	.sources = &clkset_mout_g2d1,
-	.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+	.sources = &exynos4_clkset_mout_g2d1,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 };
 
-static struct clk *clkset_mout_g2d_list[] = {
-	[0] = &clk_mout_g2d0.clk,
-	[1] = &clk_mout_g2d1.clk,
+static struct clk *exynos4_clkset_mout_g2d_list[] = {
+	[0] = &exynos4_clk_mout_g2d0.clk,
+	[1] = &exynos4_clk_mout_g2d1.clk,
 };
 
-static struct clksrc_sources clkset_mout_g2d = {
-	.sources	= clkset_mout_g2d_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_g2d_list),
+static struct clksrc_sources exynos4_clkset_mout_g2d = {
+	.sources	= exynos4_clkset_mout_g2d_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
 };
 
-static struct clk *clkset_mout_mfc0_list[] = {
-	[0] = &clk_mout_mpll.clk,
-	[1] = &clk_sclk_apll.clk,
+static struct clk *exynos4_clkset_mout_mfc0_list[] = {
+	[0] = &exynos4_clk_mout_mpll.clk,
+	[1] = &exynos4_clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources clkset_mout_mfc0 = {
-	.sources	= clkset_mout_mfc0_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_mfc0_list),
+static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
+	.sources	= exynos4_clkset_mout_mfc0_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
 };
 
-static struct clksrc_clk clk_mout_mfc0 = {
+static struct clksrc_clk exynos4_clk_mout_mfc0 = {
 	.clk	= {
 		.name		= "mout_mfc0",
 	},
-	.sources = &clkset_mout_mfc0,
-	.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
+	.sources = &exynos4_clkset_mout_mfc0,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
 };
 
-static struct clk *clkset_mout_mfc1_list[] = {
-	[0] = &clk_mout_epll.clk,
-	[1] = &clk_sclk_vpll.clk,
+static struct clk *exynos4_clkset_mout_mfc1_list[] = {
+	[0] = &exynos4_clk_mout_epll.clk,
+	[1] = &exynos4_clk_sclk_vpll.clk,
 };
 
-static struct clksrc_sources clkset_mout_mfc1 = {
-	.sources	= clkset_mout_mfc1_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_mfc1_list),
+static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
+	.sources	= exynos4_clkset_mout_mfc1_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
 };
 
-static struct clksrc_clk clk_mout_mfc1 = {
+static struct clksrc_clk exynos4_clk_mout_mfc1 = {
 	.clk	= {
 		.name		= "mout_mfc1",
 	},
-	.sources = &clkset_mout_mfc1,
-	.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
+	.sources = &exynos4_clkset_mout_mfc1,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
 };
 
-static struct clk *clkset_mout_mfc_list[] = {
-	[0] = &clk_mout_mfc0.clk,
-	[1] = &clk_mout_mfc1.clk,
+static struct clk *exynos4_clkset_mout_mfc_list[] = {
+	[0] = &exynos4_clk_mout_mfc0.clk,
+	[1] = &exynos4_clk_mout_mfc1.clk,
 };
 
-static struct clksrc_sources clkset_mout_mfc = {
-	.sources	= clkset_mout_mfc_list,
-	.nr_sources	= ARRAY_SIZE(clkset_mout_mfc_list),
+static struct clksrc_sources exynos4_clkset_mout_mfc = {
+	.sources	= exynos4_clkset_mout_mfc_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
 };
 
-static struct clk *clkset_sclk_dac_list[] = {
-	[0] = &clk_sclk_vpll.clk,
-	[1] = &clk_sclk_hdmiphy,
+static struct clk *exynos4_clkset_sclk_dac_list[] = {
+	[0] = &exynos4_clk_sclk_vpll.clk,
+	[1] = &exynos4_clk_sclk_hdmiphy,
 };
 
-static struct clksrc_sources clkset_sclk_dac = {
-	.sources	= clkset_sclk_dac_list,
-	.nr_sources	= ARRAY_SIZE(clkset_sclk_dac_list),
+static struct clksrc_sources exynos4_clkset_sclk_dac = {
+	.sources	= exynos4_clkset_sclk_dac_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
 };
 
-static struct clksrc_clk clk_sclk_dac = {
+static struct clksrc_clk exynos4_clk_sclk_dac = {
 	.clk		= {
 		.name		= "sclk_dac",
 		.enable		= exynos4_clksrc_mask_tv_ctrl,
 		.ctrlbit	= (1 << 8),
 	},
-	.sources = &clkset_sclk_dac,
-	.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
+	.sources = &exynos4_clkset_sclk_dac,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
 };
 
-static struct clksrc_clk clk_sclk_pixel = {
+static struct clksrc_clk exynos4_clk_sclk_pixel = {
 	.clk		= {
 		.name		= "sclk_pixel",
-		.parent		= &clk_sclk_vpll.clk,
+		.parent		= &exynos4_clk_sclk_vpll.clk,
 	},
-	.reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
 };
 
-static struct clk *clkset_sclk_hdmi_list[] = {
-	[0] = &clk_sclk_pixel.clk,
-	[1] = &clk_sclk_hdmiphy,
+static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
+	[0] = &exynos4_clk_sclk_pixel.clk,
+	[1] = &exynos4_clk_sclk_hdmiphy,
 };
 
-static struct clksrc_sources clkset_sclk_hdmi = {
-	.sources	= clkset_sclk_hdmi_list,
-	.nr_sources	= ARRAY_SIZE(clkset_sclk_hdmi_list),
+static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
+	.sources	= exynos4_clkset_sclk_hdmi_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
 };
 
-static struct clksrc_clk clk_sclk_hdmi = {
+static struct clksrc_clk exynos4_clk_sclk_hdmi = {
 	.clk		= {
 		.name		= "sclk_hdmi",
 		.enable		= exynos4_clksrc_mask_tv_ctrl,
 		.ctrlbit	= (1 << 0),
 	},
-	.sources = &clkset_sclk_hdmi,
-	.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
+	.sources = &exynos4_clkset_sclk_hdmi,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
 };
 
-static struct clk *clkset_sclk_mixer_list[] = {
-	[0] = &clk_sclk_dac.clk,
-	[1] = &clk_sclk_hdmi.clk,
+static struct clk *exynos4_clkset_sclk_mixer_list[] = {
+	[0] = &exynos4_clk_sclk_dac.clk,
+	[1] = &exynos4_clk_sclk_hdmi.clk,
 };
 
-static struct clksrc_sources clkset_sclk_mixer = {
-	.sources	= clkset_sclk_mixer_list,
-	.nr_sources	= ARRAY_SIZE(clkset_sclk_mixer_list),
+static struct clksrc_sources exynos4_clkset_sclk_mixer = {
+	.sources	= exynos4_clkset_sclk_mixer_list,
+	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
 };
 
-static struct clksrc_clk clk_sclk_mixer = {
+static struct clksrc_clk exynos4_clk_sclk_mixer = {
 	.clk	= {
 		.name		= "sclk_mixer",
 		.enable		= exynos4_clksrc_mask_tv_ctrl,
 		.ctrlbit	= (1 << 4),
 	},
-	.sources = &clkset_sclk_mixer,
-	.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
+	.sources = &exynos4_clkset_sclk_mixer,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
 };
 
-static struct clksrc_clk *sclk_tv[] = {
-	&clk_sclk_dac,
-	&clk_sclk_pixel,
-	&clk_sclk_hdmi,
-	&clk_sclk_mixer,
+static struct clksrc_clk *exynos4_sclk_tv[] = {
+	&exynos4_clk_sclk_dac,
+	&exynos4_clk_sclk_pixel,
+	&exynos4_clk_sclk_hdmi,
+	&exynos4_clk_sclk_mixer,
 };
 
-static struct clksrc_clk clk_dout_mmc0 = {
+static struct clksrc_clk exynos4_clk_dout_mmc0 = {
 	.clk	= {
 		.name		= "dout_mmc0",
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 };
 
-static struct clksrc_clk clk_dout_mmc1 = {
+static struct clksrc_clk exynos4_clk_dout_mmc1 = {
 	.clk	= {
 		.name		= "dout_mmc1",
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 };
 
-static struct clksrc_clk clk_dout_mmc2 = {
+static struct clksrc_clk exynos4_clk_dout_mmc2 = {
 	.clk	= {
 		.name		= "dout_mmc2",
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 };
 
-static struct clksrc_clk clk_dout_mmc3 = {
+static struct clksrc_clk exynos4_clk_dout_mmc3 = {
 	.clk	= {
 		.name		= "dout_mmc3",
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
 };
 
-static struct clksrc_clk clk_dout_mmc4 = {
+static struct clksrc_clk exynos4_clk_dout_mmc4 = {
 	.clk		= {
 		.name		= "dout_mmc4",
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
 };
 
-static struct clksrc_clk clksrcs[] = {
+static struct clksrc_clk exynos4_clksrcs[] = {
 	{
 		.clk	= {
 			.name		= "sclk_pwm",
 			.enable		= exynos4_clksrc_mask_peril0_ctrl,
 			.ctrlbit	= (1 << 24),
 		},
-		.sources = &clkset_group,
-		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
-		.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_csis",
@@ -1030,9 +1030,9 @@ static struct clksrc_clk clksrcs[] = {
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
 			.ctrlbit	= (1 << 24),
 		},
-		.sources = &clkset_group,
-		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
-		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_csis",
@@ -1040,27 +1040,27 @@ static struct clksrc_clk clksrcs[] = {
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
 			.ctrlbit	= (1 << 28),
 		},
-		.sources = &clkset_group,
-		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
-		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_cam0",
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
 			.ctrlbit	= (1 << 16),
 		},
-		.sources = &clkset_group,
-		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
-		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_cam1",
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
 			.ctrlbit	= (1 << 20),
 		},
-		.sources = &clkset_group,
-		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
-		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_fimc",
@@ -1068,9 +1068,9 @@ static struct clksrc_clk clksrcs[] = {
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
 			.ctrlbit	= (1 << 0),
 		},
-		.sources = &clkset_group,
-		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
-		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_fimc",
@@ -1078,9 +1078,9 @@ static struct clksrc_clk clksrcs[] = {
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
 			.ctrlbit	= (1 << 4),
 		},
-		.sources = &clkset_group,
-		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
-		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_fimc",
@@ -1088,9 +1088,9 @@ static struct clksrc_clk clksrcs[] = {
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
 			.ctrlbit	= (1 << 8),
 		},
-		.sources = &clkset_group,
-		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
-		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_fimc",
@@ -1098,9 +1098,9 @@ static struct clksrc_clk clksrcs[] = {
 			.enable		= exynos4_clksrc_mask_cam_ctrl,
 			.ctrlbit	= (1 << 12),
 		},
-		.sources = &clkset_group,
-		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
-		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_fimd",
@@ -1108,231 +1108,231 @@ static struct clksrc_clk clksrcs[] = {
 			.enable		= exynos4_clksrc_mask_lcd0_ctrl,
 			.ctrlbit	= (1 << 0),
 		},
-		.sources = &clkset_group,
-		.reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
-		.reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_fimg2d",
 		},
-		.sources = &clkset_mout_g2d,
-		.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-		.reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+		.sources = &exynos4_clkset_mout_g2d,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_mfc",
 			.devname	= "s5p-mfc",
 		},
-		.sources = &clkset_mout_mfc,
-		.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
-		.reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
+		.sources = &exynos4_clkset_mout_mfc,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
 	}, {
 		.clk	= {
 			.name		= "sclk_dwmmc",
-			.parent		= &clk_dout_mmc4.clk,
+			.parent		= &exynos4_clk_dout_mmc4.clk,
 			.enable		= exynos4_clksrc_mask_fsys_ctrl,
 			.ctrlbit	= (1 << 16),
 		},
-		.reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
 	}
 };
 
-static struct clksrc_clk clk_sclk_uart0 = {
+static struct clksrc_clk exynos4_clk_sclk_uart0 = {
 	.clk	= {
 		.name		= "uclk1",
 		.devname	= "exynos4210-uart.0",
 		.enable		= exynos4_clksrc_mask_peril0_ctrl,
 		.ctrlbit	= (1 << 0),
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
 };
 
-static struct clksrc_clk clk_sclk_uart1 = {
+static struct clksrc_clk exynos4_clk_sclk_uart1 = {
 	.clk	= {
 		.name		= "uclk1",
 		.devname	= "exynos4210-uart.1",
 		.enable		= exynos4_clksrc_mask_peril0_ctrl,
 		.ctrlbit	= (1 << 4),
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
 };
 
-static struct clksrc_clk clk_sclk_uart2 = {
+static struct clksrc_clk exynos4_clk_sclk_uart2 = {
 	.clk	= {
 		.name		= "uclk1",
 		.devname	= "exynos4210-uart.2",
 		.enable		= exynos4_clksrc_mask_peril0_ctrl,
 		.ctrlbit	= (1 << 8),
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
 };
 
-static struct clksrc_clk clk_sclk_uart3 = {
+static struct clksrc_clk exynos4_clk_sclk_uart3 = {
 	.clk	= {
 		.name		= "uclk1",
 		.devname	= "exynos4210-uart.3",
 		.enable		= exynos4_clksrc_mask_peril0_ctrl,
 		.ctrlbit	= (1 << 12),
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
 };
 
-static struct clksrc_clk clk_sclk_mmc0 = {
+static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
 	.clk	= {
 		.name		= "sclk_mmc",
 		.devname	= "s3c-sdhci.0",
-		.parent		= &clk_dout_mmc0.clk,
+		.parent		= &exynos4_clk_dout_mmc0.clk,
 		.enable		= exynos4_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 0),
 	},
-	.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
 };
 
-static struct clksrc_clk clk_sclk_mmc1 = {
+static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
 	.clk	= {
 		.name		= "sclk_mmc",
 		.devname	= "s3c-sdhci.1",
-		.parent		= &clk_dout_mmc1.clk,
+		.parent		= &exynos4_clk_dout_mmc1.clk,
 		.enable		= exynos4_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 4),
 	},
-	.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
 };
 
-static struct clksrc_clk clk_sclk_mmc2 = {
+static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
 	.clk	= {
 		.name		= "sclk_mmc",
 		.devname	= "s3c-sdhci.2",
-		.parent		= &clk_dout_mmc2.clk,
+		.parent		= &exynos4_clk_dout_mmc2.clk,
 		.enable		= exynos4_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 8),
 	},
-	.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
 };
 
-static struct clksrc_clk clk_sclk_mmc3 = {
+static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
 	.clk	= {
 		.name		= "sclk_mmc",
 		.devname	= "s3c-sdhci.3",
-		.parent		= &clk_dout_mmc3.clk,
+		.parent		= &exynos4_clk_dout_mmc3.clk,
 		.enable		= exynos4_clksrc_mask_fsys_ctrl,
 		.ctrlbit	= (1 << 12),
 	},
-	.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
 };
 
-static struct clksrc_clk clk_sclk_spi0 = {
+static struct clksrc_clk exynos4_clk_sclk_spi0 = {
 	.clk	= {
 		.name		= "sclk_spi",
 		.devname	= "s3c64xx-spi.0",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
 		.ctrlbit	= (1 << 16),
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
 };
 
-static struct clksrc_clk clk_sclk_spi1 = {
+static struct clksrc_clk exynos4_clk_sclk_spi1 = {
 	.clk	= {
 		.name		= "sclk_spi",
 		.devname	= "s3c64xx-spi.1",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
 		.ctrlbit	= (1 << 20),
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
 };
 
-static struct clksrc_clk clk_sclk_spi2 = {
+static struct clksrc_clk exynos4_clk_sclk_spi2 = {
 	.clk	= {
 		.name		= "sclk_spi",
 		.devname	= "s3c64xx-spi.2",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
 		.ctrlbit	= (1 << 24),
 	},
-	.sources = &clkset_group,
-	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-	.reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+	.sources = &exynos4_clkset_group,
+	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
 };
 
 /* Clock initialization code */
-static struct clksrc_clk *sysclks[] = {
-	&clk_mout_apll,
-	&clk_sclk_apll,
-	&clk_mout_epll,
-	&clk_mout_mpll,
-	&clk_moutcore,
-	&clk_coreclk,
-	&clk_armclk,
-	&clk_aclk_corem0,
-	&clk_aclk_cores,
-	&clk_aclk_corem1,
-	&clk_periphclk,
-	&clk_mout_corebus,
-	&clk_sclk_dmc,
-	&clk_aclk_cored,
-	&clk_aclk_corep,
-	&clk_aclk_acp,
-	&clk_pclk_acp,
-	&clk_vpllsrc,
-	&clk_sclk_vpll,
-	&clk_aclk_200,
-	&clk_aclk_100,
-	&clk_aclk_160,
-	&clk_aclk_133,
-	&clk_dout_mmc0,
-	&clk_dout_mmc1,
-	&clk_dout_mmc2,
-	&clk_dout_mmc3,
-	&clk_dout_mmc4,
-	&clk_mout_mfc0,
-	&clk_mout_mfc1,
-};
-
-static struct clk *clk_cdev[] = {
-	&clk_pdma0,
-	&clk_pdma1,
-};
-
-static struct clksrc_clk *clksrc_cdev[] = {
-	&clk_sclk_uart0,
-	&clk_sclk_uart1,
-	&clk_sclk_uart2,
-	&clk_sclk_uart3,
-	&clk_sclk_mmc0,
-	&clk_sclk_mmc1,
-	&clk_sclk_mmc2,
-	&clk_sclk_mmc3,
-	&clk_sclk_spi0,
-	&clk_sclk_spi1,
-	&clk_sclk_spi2,
+static struct clksrc_clk *exynos4_sysclks[] = {
+	&exynos4_clk_mout_apll,
+	&exynos4_clk_sclk_apll,
+	&exynos4_clk_mout_epll,
+	&exynos4_clk_mout_mpll,
+	&exynos4_clk_moutcore,
+	&exynos4_clk_coreclk,
+	&exynos4_clk_armclk,
+	&exynos4_clk_aclk_corem0,
+	&exynos4_clk_aclk_cores,
+	&exynos4_clk_aclk_corem1,
+	&exynos4_clk_periphclk,
+	&exynos4_clk_mout_corebus,
+	&exynos4_clk_sclk_dmc,
+	&exynos4_clk_aclk_cored,
+	&exynos4_clk_aclk_corep,
+	&exynos4_clk_aclk_acp,
+	&exynos4_clk_pclk_acp,
+	&exynos4_clk_vpllsrc,
+	&exynos4_clk_sclk_vpll,
+	&exynos4_clk_aclk_200,
+	&exynos4_clk_aclk_100,
+	&exynos4_clk_aclk_160,
+	&exynos4_clk_aclk_133,
+	&exynos4_clk_dout_mmc0,
+	&exynos4_clk_dout_mmc1,
+	&exynos4_clk_dout_mmc2,
+	&exynos4_clk_dout_mmc3,
+	&exynos4_clk_dout_mmc4,
+	&exynos4_clk_mout_mfc0,
+	&exynos4_clk_mout_mfc1,
+};
+
+static struct clk *exynos4_clk_cdev[] = {
+	&exynos4_clk_pdma0,
+	&exynos4_clk_pdma1,
+};
+
+static struct clksrc_clk *exynos4_clksrc_cdev[] = {
+	&exynos4_clk_sclk_uart0,
+	&exynos4_clk_sclk_uart1,
+	&exynos4_clk_sclk_uart2,
+	&exynos4_clk_sclk_uart3,
+	&exynos4_clk_sclk_mmc0,
+	&exynos4_clk_sclk_mmc1,
+	&exynos4_clk_sclk_mmc2,
+	&exynos4_clk_sclk_mmc3,
+	&exynos4_clk_sclk_spi0,
+	&exynos4_clk_sclk_spi1,
+	&exynos4_clk_sclk_spi2,
 
 };
 
 static struct clk_lookup exynos4_clk_lookup[] = {
-	CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
-	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
-	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
-	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
-	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
-	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
-	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
-	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
-	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
-	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
-	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
+	CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
+	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
+	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
+	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
+	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
+	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
+	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
+	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
+	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
+	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
+	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
 };
 
 static int xtal_rate;
@@ -1340,10 +1340,10 @@ static int xtal_rate;
 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
 {
 	if (soc_is_exynos4210())
-		return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
+		return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
 					pll_4508);
 	else if (soc_is_exynos4212() || soc_is_exynos4412())
-		return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
+		return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
 	else
 		return 0;
 }
@@ -1352,7 +1352,7 @@ static struct clk_ops exynos4_fout_apll_ops = {
 	.get_rate = exynos4_fout_apll_get_rate,
 };
 
-static u32 vpll_div[][8] = {
+static u32 exynos4_vpll_div[][8] = {
 	{  54000000, 3, 53, 3, 1024, 0, 17, 0 },
 	{ 108000000, 3, 53, 2, 1024, 0, 17, 0 },
 };
@@ -1371,41 +1371,41 @@ static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
 	if (clk->rate == rate)
 		return 0;
 
-	vpll_con0 = __raw_readl(S5P_VPLL_CON0);
+	vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
 	vpll_con0 &= ~(0x1 << 27 |					\
 			PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |	\
 			PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |	\
 			PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
 
-	vpll_con1 = __raw_readl(S5P_VPLL_CON1);
+	vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
 	vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |	\
 			PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT |	\
 			PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
 
-	for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
-		if (vpll_div[i][0] == rate) {
-			vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
-			vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
-			vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
-			vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
-			vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
-			vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
-			vpll_con0 |= vpll_div[i][7] << 27;
+	for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
+		if (exynos4_vpll_div[i][0] == rate) {
+			vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
+			vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
+			vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
+			vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
+			vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
+			vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
+			vpll_con0 |= exynos4_vpll_div[i][7] << 27;
 			break;
 		}
 	}
 
-	if (i == ARRAY_SIZE(vpll_div)) {
+	if (i == ARRAY_SIZE(exynos4_vpll_div)) {
 		printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
 				__func__);
 		return -EINVAL;
 	}
 
-	__raw_writel(vpll_con0, S5P_VPLL_CON0);
-	__raw_writel(vpll_con1, S5P_VPLL_CON1);
+	__raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
+	__raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
 
 	/* Wait for VPLL lock */
-	while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
+	while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
 		continue;
 
 	clk->rate = rate;
@@ -1448,25 +1448,25 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
 	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 
 	if (soc_is_exynos4210()) {
-		apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
+		apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
 					pll_4508);
-		mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
+		mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
 					pll_4508);
-		epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
-					__raw_readl(S5P_EPLL_CON1), pll_4600);
+		epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+					__raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
 
-		vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-		vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-					__raw_readl(S5P_VPLL_CON1), pll_4650c);
+		vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+		vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+					__raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
 	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-		apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
-		mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
-		epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
-					__raw_readl(S5P_EPLL_CON1));
-
-		vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-		vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-					__raw_readl(S5P_VPLL_CON1));
+		apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
+		mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
+		epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+					__raw_readl(EXYNOS4_EPLL_CON1));
+
+		vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+		vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+					__raw_readl(EXYNOS4_VPLL_CON1));
 	} else {
 		/* nothing */
 	}
@@ -1480,13 +1480,13 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
 	printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
 			apll, mpll, epll, vpll);
 
-	armclk = clk_get_rate(&clk_armclk.clk);
-	sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
+	armclk = clk_get_rate(&exynos4_clk_armclk.clk);
+	sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
 
-	aclk_200 = clk_get_rate(&clk_aclk_200.clk);
-	aclk_100 = clk_get_rate(&clk_aclk_100.clk);
-	aclk_160 = clk_get_rate(&clk_aclk_160.clk);
-	aclk_133 = clk_get_rate(&clk_aclk_133.clk);
+	aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
+	aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
+	aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
+	aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
 
 	printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
 			 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
@@ -1497,15 +1497,15 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
 	clk_h.rate = sclk_dmc;
 	clk_p.rate = aclk_100;
 
-	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-		s3c_set_clksrc(&clksrcs[ptr], true);
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
+		s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
 }
 
-static struct clk *clks[] __initdata = {
-	&clk_sclk_hdmi27m,
-	&clk_sclk_hdmiphy,
-	&clk_sclk_usbphy0,
-	&clk_sclk_usbphy1,
+static struct clk *exynos4_clks[] __initdata = {
+	&exynos4_clk_sclk_hdmi27m,
+	&exynos4_clk_sclk_hdmiphy,
+	&exynos4_clk_sclk_usbphy0,
+	&exynos4_clk_sclk_usbphy1,
 };
 
 #ifdef CONFIG_PM_SLEEP
@@ -1534,26 +1534,26 @@ void __init exynos4_register_clocks(void)
 {
 	int ptr;
 
-	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+	s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
 
-	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-		s3c_register_clksrc(sysclks[ptr], 1);
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
+		s3c_register_clksrc(exynos4_sysclks[ptr], 1);
 
-	for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
-		s3c_register_clksrc(sclk_tv[ptr], 1);
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
+		s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
 
-	for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
-		s3c_register_clksrc(clksrc_cdev[ptr], 1);
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
+		s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
 
-	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+	s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
+	s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
 
-	s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
-	for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
-		s3c_disable_clocks(clk_cdev[ptr], 1);
+	s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
+		s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
 
-	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+	s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+	s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
 	clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
 
 	register_syscore_ops(&exynos4_clock_syscore_ops);
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
index d2ef305..cb71c29 100644
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -1,6 +1,5 @@
 /*
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
  * Header file for exynos4 clock support
@@ -15,14 +14,14 @@
 
 #include <linux/clk.h>
 
-extern struct clksrc_clk clk_mout_mpll;
-extern struct clksrc_clk clk_aclk_133;
+extern struct clksrc_clk exynos4_clk_aclk_133;
+extern struct clksrc_clk exynos4_clk_mout_mpll;
 
-extern struct clksrc_sources clkset_mout_corebus;
-extern struct clksrc_sources clkset_group;
+extern struct clksrc_sources exynos4_clkset_mout_corebus;
+extern struct clksrc_sources exynos4_clkset_group;
 
-extern struct clk *clkset_aclk_top_list[];
-extern struct clk *clkset_group_list[];
+extern struct clk *exynos4_clkset_aclk_top_list[];
+extern struct clk *exynos4_clkset_group_list[];
 
 extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 190d94a..bb8c7f4 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/clock-exynos4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
  * EXYNOS4210 - Clock support
@@ -34,14 +32,14 @@
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4210_clock_save[] = {
-	SAVE_ITEM(S5P_CLKSRC_IMAGE),
-	SAVE_ITEM(S5P_CLKSRC_LCD1),
-	SAVE_ITEM(S5P_CLKDIV_IMAGE),
-	SAVE_ITEM(S5P_CLKDIV_LCD1),
-	SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
-	SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
-	SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
-	SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+	SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+	SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+	SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
+	SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
+	SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
+	SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
+	SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
+	SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
 };
 #endif
 
@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
 
 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
 {
-	return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+	return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
 }
 
 static struct clksrc_clk clksrcs[] = {
@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
 			.enable		= exynos4_clksrc_mask_fsys_ctrl,
 			.ctrlbit	= (1 << 24),
 		},
-		.sources = &clkset_mout_corebus,
-		.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
-		.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+		.sources = &exynos4_clkset_mout_corebus,
+		.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
+		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
 	}, {
 		.clk		= {
 			.name		= "sclk_fimd",
@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
 			.enable		= exynos4_clksrc_mask_lcd1_ctrl,
 			.ctrlbit	= (1 << 0),
 		},
-		.sources = &clkset_group,
-		.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
-		.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+		.sources = &exynos4_clkset_group,
+		.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
 	},
 };
 
@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
 	{
 		.name		= "sataphy",
 		.id		= -1,
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 3),
 	}, {
 		.name		= "sata",
 		.id		= -1,
-		.parent		= &clk_aclk_133.clk,
+		.parent		= &exynos4_clk_aclk_133.clk,
 		.enable		= exynos4_clk_ip_fsys_ctrl,
 		.ctrlbit	= (1 << 10),
 	}, {
@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
 {
 	int ptr;
 
-	clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
-	clk_mout_mpll.reg_src.shift = 8;
-	clk_mout_mpll.reg_src.size = 1;
+	exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
+	exynos4_clk_mout_mpll.reg_src.shift = 8;
+	exynos4_clk_mout_mpll.reg_src.size = 1;
 
 	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 		s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index e83d4b2..b478f44 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/clock-exynos4212.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
  * EXYNOS4212 - Clock support
@@ -34,16 +32,16 @@
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4212_clock_save[] = {
-	SAVE_ITEM(S5P_CLKSRC_IMAGE),
-	SAVE_ITEM(S5P_CLKDIV_IMAGE),
-	SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
-	SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
+	SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+	SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
+	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
 };
 #endif
 
 static struct clk *clk_src_mpll_user_list[] = {
 	[0] = &clk_fin_mpll,
-	[1] = &clk_mout_mpll.clk,
+	[1] = &exynos4_clk_mout_mpll.clk,
 };
 
 static struct clksrc_sources clk_src_mpll_user = {
@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
 		.name		= "mout_mpll_user",
 	},
 	.sources	= &clk_src_mpll_user,
-	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
+	.reg_src	= { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
 };
 
 static struct clksrc_clk *sysclks[] = {
@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void)
 	int ptr;
 
 	/* usbphy1 is removed */
-	clkset_group_list[4] = NULL;
+	exynos4_clkset_group_list[4] = NULL;
 
 	/* mout_mpll_user is used */
-	clkset_group_list[6] = &clk_mout_mpll_user.clk;
-	clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+	exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
+	exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
 
-	clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
-	clk_mout_mpll.reg_src.shift = 12;
-	clk_mout_mpll.reg_src.size = 1;
+	exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
+	exynos4_clk_mout_mpll.reg_src.shift = 12;
+	exynos4_clk_mout_mpll.reg_src.size = 1;
 
 	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 		s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 1ac49de..8c1efe6 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -15,12 +15,21 @@
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
 
+#ifdef CONFIG_ARCH_EXYNOS4
 void exynos4_register_clocks(void);
 void exynos4_setup_clocks(void);
 
 void exynos4210_register_clocks(void);
 void exynos4212_register_clocks(void);
 
+#else
+#define exynos4_register_clocks()
+#define exynos4_setup_clocks()
+
+#define exynos4210_register_clocks()
+#define exynos4212_register_clocks()
+#endif
+
 void exynos4_restart(char mode, const char *cmd);
 
 extern struct sys_timer exynos4_timer;
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 6c37ebe..790f525 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -16,195 +16,195 @@
 #include <plat/cpu.h>
 #include <mach/map.h>
 
-#define S5P_CLKREG(x)			(S5P_VA_CMU + (x))
-
-#define S5P_CLKDIV_LEFTBUS		S5P_CLKREG(0x04500)
-#define S5P_CLKDIV_STAT_LEFTBUS		S5P_CLKREG(0x04600)
-#define S5P_CLKGATE_IP_LEFTBUS		S5P_CLKREG(0x04800)
-
-#define S5P_CLKDIV_RIGHTBUS		S5P_CLKREG(0x08500)
-#define S5P_CLKDIV_STAT_RIGHTBUS	S5P_CLKREG(0x08600)
-#define S5P_CLKGATE_IP_RIGHTBUS		S5P_CLKREG(0x08800)
-
-#define S5P_EPLL_LOCK			S5P_CLKREG(0x0C010)
-#define S5P_VPLL_LOCK			S5P_CLKREG(0x0C020)
-
-#define S5P_EPLL_CON0			S5P_CLKREG(0x0C110)
-#define S5P_EPLL_CON1			S5P_CLKREG(0x0C114)
-#define S5P_VPLL_CON0			S5P_CLKREG(0x0C120)
-#define S5P_VPLL_CON1			S5P_CLKREG(0x0C124)
-
-#define S5P_CLKSRC_TOP0			S5P_CLKREG(0x0C210)
-#define S5P_CLKSRC_TOP1			S5P_CLKREG(0x0C214)
-#define S5P_CLKSRC_CAM			S5P_CLKREG(0x0C220)
-#define S5P_CLKSRC_TV			S5P_CLKREG(0x0C224)
-#define S5P_CLKSRC_MFC			S5P_CLKREG(0x0C228)
-#define S5P_CLKSRC_G3D			S5P_CLKREG(0x0C22C)
-#define S5P_CLKSRC_IMAGE		S5P_CLKREG(0x0C230)
-#define S5P_CLKSRC_LCD0			S5P_CLKREG(0x0C234)
-#define S5P_CLKSRC_MAUDIO		S5P_CLKREG(0x0C23C)
-#define S5P_CLKSRC_FSYS			S5P_CLKREG(0x0C240)
-#define S5P_CLKSRC_PERIL0		S5P_CLKREG(0x0C250)
-#define S5P_CLKSRC_PERIL1		S5P_CLKREG(0x0C254)
-
-#define S5P_CLKSRC_MASK_TOP		S5P_CLKREG(0x0C310)
-#define S5P_CLKSRC_MASK_CAM		S5P_CLKREG(0x0C320)
-#define S5P_CLKSRC_MASK_TV		S5P_CLKREG(0x0C324)
-#define S5P_CLKSRC_MASK_LCD0		S5P_CLKREG(0x0C334)
-#define S5P_CLKSRC_MASK_MAUDIO		S5P_CLKREG(0x0C33C)
-#define S5P_CLKSRC_MASK_FSYS		S5P_CLKREG(0x0C340)
-#define S5P_CLKSRC_MASK_PERIL0		S5P_CLKREG(0x0C350)
-#define S5P_CLKSRC_MASK_PERIL1		S5P_CLKREG(0x0C354)
-
-#define S5P_CLKDIV_TOP			S5P_CLKREG(0x0C510)
-#define S5P_CLKDIV_CAM			S5P_CLKREG(0x0C520)
-#define S5P_CLKDIV_TV			S5P_CLKREG(0x0C524)
-#define S5P_CLKDIV_MFC			S5P_CLKREG(0x0C528)
-#define S5P_CLKDIV_G3D			S5P_CLKREG(0x0C52C)
-#define S5P_CLKDIV_IMAGE		S5P_CLKREG(0x0C530)
-#define S5P_CLKDIV_LCD0			S5P_CLKREG(0x0C534)
-#define S5P_CLKDIV_MAUDIO		S5P_CLKREG(0x0C53C)
-#define S5P_CLKDIV_FSYS0		S5P_CLKREG(0x0C540)
-#define S5P_CLKDIV_FSYS1		S5P_CLKREG(0x0C544)
-#define S5P_CLKDIV_FSYS2		S5P_CLKREG(0x0C548)
-#define S5P_CLKDIV_FSYS3		S5P_CLKREG(0x0C54C)
-#define S5P_CLKDIV_PERIL0		S5P_CLKREG(0x0C550)
-#define S5P_CLKDIV_PERIL1		S5P_CLKREG(0x0C554)
-#define S5P_CLKDIV_PERIL2		S5P_CLKREG(0x0C558)
-#define S5P_CLKDIV_PERIL3		S5P_CLKREG(0x0C55C)
-#define S5P_CLKDIV_PERIL4		S5P_CLKREG(0x0C560)
-#define S5P_CLKDIV_PERIL5		S5P_CLKREG(0x0C564)
-#define S5P_CLKDIV2_RATIO		S5P_CLKREG(0x0C580)
-
-#define S5P_CLKDIV_STAT_TOP		S5P_CLKREG(0x0C610)
-
-#define S5P_CLKGATE_SCLKCAM		S5P_CLKREG(0x0C820)
-#define S5P_CLKGATE_IP_CAM		S5P_CLKREG(0x0C920)
-#define S5P_CLKGATE_IP_TV		S5P_CLKREG(0x0C924)
-#define S5P_CLKGATE_IP_MFC		S5P_CLKREG(0x0C928)
-#define S5P_CLKGATE_IP_G3D		S5P_CLKREG(0x0C92C)
-#define S5P_CLKGATE_IP_IMAGE		(soc_is_exynos4210() ? \
-					S5P_CLKREG(0x0C930) : \
-					S5P_CLKREG(0x04930))
-#define S5P_CLKGATE_IP_IMAGE_4210	S5P_CLKREG(0x0C930)
-#define S5P_CLKGATE_IP_IMAGE_4212	S5P_CLKREG(0x04930)
-#define S5P_CLKGATE_IP_LCD0		S5P_CLKREG(0x0C934)
-#define S5P_CLKGATE_IP_FSYS		S5P_CLKREG(0x0C940)
-#define S5P_CLKGATE_IP_GPS		S5P_CLKREG(0x0C94C)
-#define S5P_CLKGATE_IP_PERIL		S5P_CLKREG(0x0C950)
-#define S5P_CLKGATE_IP_PERIR		(soc_is_exynos4210() ? \
-					S5P_CLKREG(0x0C960) : \
-					S5P_CLKREG(0x08960))
-#define S5P_CLKGATE_IP_PERIR_4210	S5P_CLKREG(0x0C960)
-#define S5P_CLKGATE_IP_PERIR_4212	S5P_CLKREG(0x08960)
-#define S5P_CLKGATE_BLOCK		S5P_CLKREG(0x0C970)
-
-#define S5P_CLKSRC_MASK_DMC		S5P_CLKREG(0x10300)
-#define S5P_CLKSRC_DMC			S5P_CLKREG(0x10200)
-#define S5P_CLKDIV_DMC0			S5P_CLKREG(0x10500)
-#define S5P_CLKDIV_DMC1			S5P_CLKREG(0x10504)
-#define S5P_CLKDIV_STAT_DMC0		S5P_CLKREG(0x10600)
-#define S5P_CLKGATE_IP_DMC		S5P_CLKREG(0x10900)
-
-#define S5P_APLL_LOCK			S5P_CLKREG(0x14000)
-#define S5P_MPLL_LOCK			(soc_is_exynos4210() ? \
-					S5P_CLKREG(0x14004) :  \
-					S5P_CLKREG(0x10008))
-#define S5P_APLL_CON0			S5P_CLKREG(0x14100)
-#define S5P_APLL_CON1			S5P_CLKREG(0x14104)
-#define S5P_MPLL_CON0			(soc_is_exynos4210() ? \
-					S5P_CLKREG(0x14108) : \
-					S5P_CLKREG(0x10108))
-#define S5P_MPLL_CON1			(soc_is_exynos4210() ? \
-					S5P_CLKREG(0x1410C) : \
-					S5P_CLKREG(0x1010C))
-
-#define S5P_CLKSRC_CPU			S5P_CLKREG(0x14200)
-#define S5P_CLKMUX_STATCPU		S5P_CLKREG(0x14400)
-
-#define S5P_CLKDIV_CPU			S5P_CLKREG(0x14500)
-#define S5P_CLKDIV_CPU1			S5P_CLKREG(0x14504)
-#define S5P_CLKDIV_STATCPU		S5P_CLKREG(0x14600)
-#define S5P_CLKDIV_STATCPU1		S5P_CLKREG(0x14604)
-
-#define S5P_CLKGATE_SCLKCPU		S5P_CLKREG(0x14800)
-#define S5P_CLKGATE_IP_CPU		S5P_CLKREG(0x14900)
-
-#define S5P_APLL_LOCKTIME		(0x1C20)	/* 300us */
-
-#define S5P_APLLCON0_ENABLE_SHIFT	(31)
-#define S5P_APLLCON0_LOCKED_SHIFT	(29)
-#define S5P_APLL_VAL_1000		((250 << 16) | (6 << 8) | 1)
-#define S5P_APLL_VAL_800		((200 << 16) | (6 << 8) | 1)
-
-#define S5P_EPLLCON0_ENABLE_SHIFT	(31)
-#define S5P_EPLLCON0_LOCKED_SHIFT	(29)
-
-#define S5P_VPLLCON0_ENABLE_SHIFT	(31)
-#define S5P_VPLLCON0_LOCKED_SHIFT	(29)
-
-#define S5P_CLKSRC_CPU_MUXCORE_SHIFT	(16)
-#define S5P_CLKMUX_STATCPU_MUXCORE_MASK	(0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
-
-#define S5P_CLKDIV_CPU0_CORE_SHIFT	(0)
-#define S5P_CLKDIV_CPU0_CORE_MASK	(0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM0_SHIFT	(4)
-#define S5P_CLKDIV_CPU0_COREM0_MASK	(0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM1_SHIFT	(8)
-#define S5P_CLKDIV_CPU0_COREM1_MASK	(0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
-#define S5P_CLKDIV_CPU0_PERIPH_SHIFT	(12)
-#define S5P_CLKDIV_CPU0_PERIPH_MASK	(0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
-#define S5P_CLKDIV_CPU0_ATB_SHIFT	(16)
-#define S5P_CLKDIV_CPU0_ATB_MASK	(0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
-#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT	(20)
-#define S5P_CLKDIV_CPU0_PCLKDBG_MASK	(0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
-#define S5P_CLKDIV_CPU0_APLL_SHIFT	(24)
-#define S5P_CLKDIV_CPU0_APLL_MASK	(0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
-
-#define S5P_CLKDIV_DMC0_ACP_SHIFT	(0)
-#define S5P_CLKDIV_DMC0_ACP_MASK	(0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
-#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT	(4)
-#define S5P_CLKDIV_DMC0_ACPPCLK_MASK	(0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
-#define S5P_CLKDIV_DMC0_DPHY_SHIFT	(8)
-#define S5P_CLKDIV_DMC0_DPHY_MASK	(0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
-#define S5P_CLKDIV_DMC0_DMC_SHIFT	(12)
-#define S5P_CLKDIV_DMC0_DMC_MASK	(0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCD_SHIFT	(16)
-#define S5P_CLKDIV_DMC0_DMCD_MASK	(0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCP_SHIFT	(20)
-#define S5P_CLKDIV_DMC0_DMCP_MASK	(0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
-#define S5P_CLKDIV_DMC0_COPY2_SHIFT	(24)
-#define S5P_CLKDIV_DMC0_COPY2_MASK	(0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
-#define S5P_CLKDIV_DMC0_CORETI_SHIFT	(28)
-#define S5P_CLKDIV_DMC0_CORETI_MASK	(0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
-
-#define S5P_CLKDIV_TOP_ACLK200_SHIFT	(0)
-#define S5P_CLKDIV_TOP_ACLK200_MASK	(0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK100_SHIFT	(4)
-#define S5P_CLKDIV_TOP_ACLK100_MASK	(0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK160_SHIFT	(8)
-#define S5P_CLKDIV_TOP_ACLK160_MASK	(0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK133_SHIFT	(12)
-#define S5P_CLKDIV_TOP_ACLK133_MASK	(0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
-#define S5P_CLKDIV_TOP_ONENAND_SHIFT	(16)
-#define S5P_CLKDIV_TOP_ONENAND_MASK	(0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
-
-#define S5P_CLKDIV_BUS_GDLR_SHIFT	(0)
-#define S5P_CLKDIV_BUS_GDLR_MASK	(0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
-#define S5P_CLKDIV_BUS_GPLR_SHIFT	(4)
-#define S5P_CLKDIV_BUS_GPLR_MASK	(0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
+#define EXYNOS_CLKREG(x)			(S5P_VA_CMU + (x))
+
+#define EXYNOS4_CLKDIV_LEFTBUS			EXYNOS_CLKREG(0x04500)
+#define EXYNOS4_CLKDIV_STAT_LEFTBUS		EXYNOS_CLKREG(0x04600)
+#define EXYNOS4_CLKGATE_IP_LEFTBUS		EXYNOS_CLKREG(0x04800)
+
+#define EXYNOS4_CLKDIV_RIGHTBUS			EXYNOS_CLKREG(0x08500)
+#define EXYNOS4_CLKDIV_STAT_RIGHTBUS		EXYNOS_CLKREG(0x08600)
+#define EXYNOS4_CLKGATE_IP_RIGHTBUS		EXYNOS_CLKREG(0x08800)
+
+#define EXYNOS4_EPLL_LOCK			EXYNOS_CLKREG(0x0C010)
+#define EXYNOS4_VPLL_LOCK			EXYNOS_CLKREG(0x0C020)
+
+#define EXYNOS4_EPLL_CON0			EXYNOS_CLKREG(0x0C110)
+#define EXYNOS4_EPLL_CON1			EXYNOS_CLKREG(0x0C114)
+#define EXYNOS4_VPLL_CON0			EXYNOS_CLKREG(0x0C120)
+#define EXYNOS4_VPLL_CON1			EXYNOS_CLKREG(0x0C124)
+
+#define EXYNOS4_CLKSRC_TOP0			EXYNOS_CLKREG(0x0C210)
+#define EXYNOS4_CLKSRC_TOP1			EXYNOS_CLKREG(0x0C214)
+#define EXYNOS4_CLKSRC_CAM			EXYNOS_CLKREG(0x0C220)
+#define EXYNOS4_CLKSRC_TV			EXYNOS_CLKREG(0x0C224)
+#define EXYNOS4_CLKSRC_MFC			EXYNOS_CLKREG(0x0C228)
+#define EXYNOS4_CLKSRC_G3D			EXYNOS_CLKREG(0x0C22C)
+#define EXYNOS4_CLKSRC_IMAGE			EXYNOS_CLKREG(0x0C230)
+#define EXYNOS4_CLKSRC_LCD0			EXYNOS_CLKREG(0x0C234)
+#define EXYNOS4_CLKSRC_MAUDIO			EXYNOS_CLKREG(0x0C23C)
+#define EXYNOS4_CLKSRC_FSYS			EXYNOS_CLKREG(0x0C240)
+#define EXYNOS4_CLKSRC_PERIL0			EXYNOS_CLKREG(0x0C250)
+#define EXYNOS4_CLKSRC_PERIL1			EXYNOS_CLKREG(0x0C254)
+
+#define EXYNOS4_CLKSRC_MASK_TOP			EXYNOS_CLKREG(0x0C310)
+#define EXYNOS4_CLKSRC_MASK_CAM			EXYNOS_CLKREG(0x0C320)
+#define EXYNOS4_CLKSRC_MASK_TV			EXYNOS_CLKREG(0x0C324)
+#define EXYNOS4_CLKSRC_MASK_LCD0		EXYNOS_CLKREG(0x0C334)
+#define EXYNOS4_CLKSRC_MASK_MAUDIO		EXYNOS_CLKREG(0x0C33C)
+#define EXYNOS4_CLKSRC_MASK_FSYS		EXYNOS_CLKREG(0x0C340)
+#define EXYNOS4_CLKSRC_MASK_PERIL0		EXYNOS_CLKREG(0x0C350)
+#define EXYNOS4_CLKSRC_MASK_PERIL1		EXYNOS_CLKREG(0x0C354)
+
+#define EXYNOS4_CLKDIV_TOP			EXYNOS_CLKREG(0x0C510)
+#define EXYNOS4_CLKDIV_CAM			EXYNOS_CLKREG(0x0C520)
+#define EXYNOS4_CLKDIV_TV			EXYNOS_CLKREG(0x0C524)
+#define EXYNOS4_CLKDIV_MFC			EXYNOS_CLKREG(0x0C528)
+#define EXYNOS4_CLKDIV_G3D			EXYNOS_CLKREG(0x0C52C)
+#define EXYNOS4_CLKDIV_IMAGE			EXYNOS_CLKREG(0x0C530)
+#define EXYNOS4_CLKDIV_LCD0			EXYNOS_CLKREG(0x0C534)
+#define EXYNOS4_CLKDIV_MAUDIO			EXYNOS_CLKREG(0x0C53C)
+#define EXYNOS4_CLKDIV_FSYS0			EXYNOS_CLKREG(0x0C540)
+#define EXYNOS4_CLKDIV_FSYS1			EXYNOS_CLKREG(0x0C544)
+#define EXYNOS4_CLKDIV_FSYS2			EXYNOS_CLKREG(0x0C548)
+#define EXYNOS4_CLKDIV_FSYS3			EXYNOS_CLKREG(0x0C54C)
+#define EXYNOS4_CLKDIV_PERIL0			EXYNOS_CLKREG(0x0C550)
+#define EXYNOS4_CLKDIV_PERIL1			EXYNOS_CLKREG(0x0C554)
+#define EXYNOS4_CLKDIV_PERIL2			EXYNOS_CLKREG(0x0C558)
+#define EXYNOS4_CLKDIV_PERIL3			EXYNOS_CLKREG(0x0C55C)
+#define EXYNOS4_CLKDIV_PERIL4			EXYNOS_CLKREG(0x0C560)
+#define EXYNOS4_CLKDIV_PERIL5			EXYNOS_CLKREG(0x0C564)
+#define EXYNOS4_CLKDIV2_RATIO			EXYNOS_CLKREG(0x0C580)
+
+#define EXYNOS4_CLKDIV_STAT_TOP			EXYNOS_CLKREG(0x0C610)
+
+#define EXYNOS4_CLKGATE_SCLKCAM			EXYNOS_CLKREG(0x0C820)
+#define EXYNOS4_CLKGATE_IP_CAM			EXYNOS_CLKREG(0x0C920)
+#define EXYNOS4_CLKGATE_IP_TV			EXYNOS_CLKREG(0x0C924)
+#define EXYNOS4_CLKGATE_IP_MFC			EXYNOS_CLKREG(0x0C928)
+#define EXYNOS4_CLKGATE_IP_G3D			EXYNOS_CLKREG(0x0C92C)
+#define EXYNOS4_CLKGATE_IP_IMAGE		(soc_is_exynos4210() ? \
+						EXYNOS_CLKREG(0x0C930) : \
+						EXYNOS_CLKREG(0x04930))
+#define EXYNOS4210_CLKGATE_IP_IMAGE		EXYNOS_CLKREG(0x0C930)
+#define EXYNOS4212_CLKGATE_IP_IMAGE		EXYNOS_CLKREG(0x04930)
+#define EXYNOS4_CLKGATE_IP_LCD0			EXYNOS_CLKREG(0x0C934)
+#define EXYNOS4_CLKGATE_IP_FSYS			EXYNOS_CLKREG(0x0C940)
+#define EXYNOS4_CLKGATE_IP_GPS			EXYNOS_CLKREG(0x0C94C)
+#define EXYNOS4_CLKGATE_IP_PERIL		EXYNOS_CLKREG(0x0C950)
+#define EXYNOS4_CLKGATE_IP_PERIR		(soc_is_exynos4210() ? \
+						EXYNOS_CLKREG(0x0C960) : \
+						EXYNOS_CLKREG(0x08960))
+#define EXYNOS4210_CLKGATE_IP_PERIR		EXYNOS_CLKREG(0x0C960)
+#define EXYNOS4212_CLKGATE_IP_PERIR		EXYNOS_CLKREG(0x08960)
+#define EXYNOS4_CLKGATE_BLOCK			EXYNOS_CLKREG(0x0C970)
+
+#define EXYNOS4_CLKSRC_MASK_DMC			EXYNOS_CLKREG(0x10300)
+#define EXYNOS4_CLKSRC_DMC			EXYNOS_CLKREG(0x10200)
+#define EXYNOS4_CLKDIV_DMC0			EXYNOS_CLKREG(0x10500)
+#define EXYNOS4_CLKDIV_DMC1			EXYNOS_CLKREG(0x10504)
+#define EXYNOS4_CLKDIV_STAT_DMC0		EXYNOS_CLKREG(0x10600)
+#define EXYNOS4_CLKGATE_IP_DMC			EXYNOS_CLKREG(0x10900)
+
+#define EXYNOS4_APLL_LOCK			EXYNOS_CLKREG(0x14000)
+#define EXYNOS4_MPLL_LOCK			(soc_is_exynos4210() ? \
+						EXYNOS_CLKREG(0x14004) :  \
+						EXYNOS_CLKREG(0x10008))
+#define EXYNOS4_APLL_CON0			EXYNOS_CLKREG(0x14100)
+#define EXYNOS4_APLL_CON1			EXYNOS_CLKREG(0x14104)
+#define EXYNOS4_MPLL_CON0			(soc_is_exynos4210() ? \
+						EXYNOS_CLKREG(0x14108) : \
+						EXYNOS_CLKREG(0x10108))
+#define EXYNOS4_MPLL_CON1			(soc_is_exynos4210() ? \
+						EXYNOS_CLKREG(0x1410C) : \
+						EXYNOS_CLKREG(0x1010C))
+
+#define EXYNOS4_CLKSRC_CPU			EXYNOS_CLKREG(0x14200)
+#define EXYNOS4_CLKMUX_STATCPU			EXYNOS_CLKREG(0x14400)
+
+#define EXYNOS4_CLKDIV_CPU			EXYNOS_CLKREG(0x14500)
+#define EXYNOS4_CLKDIV_CPU1			EXYNOS_CLKREG(0x14504)
+#define EXYNOS4_CLKDIV_STATCPU			EXYNOS_CLKREG(0x14600)
+#define EXYNOS4_CLKDIV_STATCPU1			EXYNOS_CLKREG(0x14604)
+
+#define EXYNOS4_CLKGATE_SCLKCPU			EXYNOS_CLKREG(0x14800)
+#define EXYNOS4_CLKGATE_IP_CPU			EXYNOS_CLKREG(0x14900)
+
+#define EXYNOS4_APLL_LOCKTIME			(0x1C20)	/* 300us */
+
+#define EXYNOS4_APLLCON0_ENABLE_SHIFT		(31)
+#define EXYNOS4_APLLCON0_LOCKED_SHIFT		(29)
+#define EXYNOS4_APLL_VAL_1000			((250 << 16) | (6 << 8) | 1)
+#define EXYNOS4_APLL_VAL_800			((200 << 16) | (6 << 8) | 1)
+
+#define EXYNOS4_EPLLCON0_ENABLE_SHIFT		(31)
+#define EXYNOS4_EPLLCON0_LOCKED_SHIFT		(29)
+
+#define EXYNOS4_VPLLCON0_ENABLE_SHIFT		(31)
+#define EXYNOS4_VPLLCON0_LOCKED_SHIFT		(29)
+
+#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT	(16)
+#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK	(0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
+
+#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT		(0)
+#define EXYNOS4_CLKDIV_CPU0_CORE_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT	(4)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT	(8)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT	(12)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT		(16)
+#define EXYNOS4_CLKDIV_CPU0_ATB_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT	(20)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK	(0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT		(24)
+#define EXYNOS4_CLKDIV_CPU0_APLL_MASK		(0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
+
+#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT		(0)
+#define EXYNOS4_CLKDIV_DMC0_ACP_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT	(4)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT		(8)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT		(12)
+#define EXYNOS4_CLKDIV_DMC0_DMC_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT		(16)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT		(20)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT		(24)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT	(28)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
+
+#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT	(0)
+#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT	(4)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK		(0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT	(8)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT	(12)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT	(16)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
+
+#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT		(0)
+#define EXYNOS4_CLKDIV_BUS_GDLR_MASK		(0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
+#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT		(4)
+#define EXYNOS4_CLKDIV_BUS_GPLR_MASK		(0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
 
 /* Only for EXYNOS4210 */
 
-#define S5P_CLKSRC_LCD1			S5P_CLKREG(0x0C238)
-#define S5P_CLKSRC_MASK_LCD1		S5P_CLKREG(0x0C338)
-#define S5P_CLKDIV_LCD1			S5P_CLKREG(0x0C538)
-#define S5P_CLKGATE_IP_LCD1		S5P_CLKREG(0x0C938)
+#define EXYNOS4210_CLKSRC_LCD1			EXYNOS_CLKREG(0x0C238)
+#define EXYNOS4210_CLKSRC_MASK_LCD1		EXYNOS_CLKREG(0x0C338)
+#define EXYNOS4210_CLKDIV_LCD1			EXYNOS_CLKREG(0x0C538)
+#define EXYNOS4210_CLKGATE_IP_LCD1		EXYNOS_CLKREG(0x0C938)
 
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>
 
-#define S5P_EPLL_CON			S5P_EPLL_CON0
+#define S5P_EPLL_CON				EXYNOS4_EPLL_CON0
 
 #endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e190130..f105bd2 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -38,29 +38,29 @@
 #include <mach/pmu.h>
 
 static struct sleep_save exynos4_set_clksrc[] = {
-	{ .reg = S5P_CLKSRC_MASK_TOP			, .val = 0x00000001, },
-	{ .reg = S5P_CLKSRC_MASK_CAM			, .val = 0x11111111, },
-	{ .reg = S5P_CLKSRC_MASK_TV			, .val = 0x00000111, },
-	{ .reg = S5P_CLKSRC_MASK_LCD0			, .val = 0x00001111, },
-	{ .reg = S5P_CLKSRC_MASK_MAUDIO			, .val = 0x00000001, },
-	{ .reg = S5P_CLKSRC_MASK_FSYS			, .val = 0x01011111, },
-	{ .reg = S5P_CLKSRC_MASK_PERIL0			, .val = 0x01111111, },
-	{ .reg = S5P_CLKSRC_MASK_PERIL1			, .val = 0x01110111, },
-	{ .reg = S5P_CLKSRC_MASK_DMC			, .val = 0x00010000, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_TOP		, .val = 0x00000001, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_CAM		, .val = 0x11111111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_TV			, .val = 0x00000111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_LCD0		, .val = 0x00001111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_MAUDIO		, .val = 0x00000001, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_FSYS		, .val = 0x01011111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_PERIL0		, .val = 0x01111111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_PERIL1		, .val = 0x01110111, },
+	{ .reg = EXYNOS4_CLKSRC_MASK_DMC		, .val = 0x00010000, },
 };
 
 static struct sleep_save exynos4210_set_clksrc[] = {
-	{ .reg = S5P_CLKSRC_MASK_LCD1			, .val = 0x00001111, },
+	{ .reg = EXYNOS4210_CLKSRC_MASK_LCD1		, .val = 0x00001111, },
 };
 
 static struct sleep_save exynos4_epll_save[] = {
-	SAVE_ITEM(S5P_EPLL_CON0),
-	SAVE_ITEM(S5P_EPLL_CON1),
+	SAVE_ITEM(EXYNOS4_EPLL_CON0),
+	SAVE_ITEM(EXYNOS4_EPLL_CON1),
 };
 
 static struct sleep_save exynos4_vpll_save[] = {
-	SAVE_ITEM(S5P_VPLL_CON0),
-	SAVE_ITEM(S5P_VPLL_CON1),
+	SAVE_ITEM(EXYNOS4_VPLL_CON0),
+	SAVE_ITEM(EXYNOS4_VPLL_CON1),
 };
 
 static struct sleep_save exynos4_core_save[] = {
@@ -239,7 +239,7 @@ static void exynos4_restore_pll(void)
 		locktime = (3000 / pll_in_rate) * p_div;
 		lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 
-		__raw_writel(lockcnt, S5P_EPLL_LOCK);
+		__raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
 
 		s3c_pm_do_restore_core(exynos4_epll_save,
 					ARRAY_SIZE(exynos4_epll_save));
@@ -257,7 +257,7 @@ static void exynos4_restore_pll(void)
 		locktime = 750;
 		lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 
-		__raw_writel(lockcnt, S5P_VPLL_LOCK);
+		__raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
 
 		s3c_pm_do_restore_core(exynos4_vpll_save,
 					ARRAY_SIZE(exynos4_vpll_save));
@@ -268,14 +268,14 @@ static void exynos4_restore_pll(void)
 
 	do {
 		if (epll_wait) {
-			pll_con = __raw_readl(S5P_EPLL_CON0);
-			if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+			pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
+			if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
 				epll_wait = 0;
 		}
 
 		if (vpll_wait) {
-			pll_con = __raw_readl(S5P_VPLL_CON0);
-			if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+			pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
+			if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
 				vpll_wait = 0;
 		}
 	} while (epll_wait || vpll_wait);
-- 
1.7.4.4



From thomas.abraham at linaro.org  Sun Mar 11 08:46:05 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sun, 11 Mar 2012 18:16:05 +0530
Subject: [PATCH 5/5] mmc: sdhci-s3c: setup pins using pinctrl interface
In-Reply-To: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>

The platform specific callback to setup the sdhci pin mux and pin config
is removed and the pinctrl subsystem interface is used to setup the
mux and config.

Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 drivers/mmc/host/sdhci-s3c.c |   15 +++++++++++++--
 1 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index ea0767e..76c1c36 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -22,6 +22,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <linux/mmc/host.h>
 
@@ -50,6 +51,7 @@ struct sdhci_s3c {
 	struct platform_device	*pdev;
 	struct resource		*ioarea;
 	struct s3c_sdhci_platdata *pdata;
+	struct pinctrl 		*pinctrl;
 	unsigned int		cur_clk;
 	int			ext_cd_irq;
 	int			ext_cd_gpio;
@@ -529,6 +531,9 @@ static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
 			platform_get_device_id(pdev)->driver_data;
 }
 
+#include <plat/map-s5p.h>
+#include <plat/map-base.h>
+
 static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 {
 	struct s3c_sdhci_platdata *pdata;
@@ -538,6 +543,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	struct sdhci_s3c *sc;
 	struct resource *res;
 	int ret, irq, ptr, clks;
+	char *pstate;
 
 	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
 		dev_err(dev, "no device data specified\n");
@@ -643,8 +649,13 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	}
 
 	/* Ensure we have minimal gpio selected CMD/CLK/Detect */
-	if (pdata->cfg_gpio)
-		pdata->cfg_gpio(pdev, pdata->max_width);
+	pstate = pdata->max_width ? "sdhci-pcfg8" : "sdhci-pcfg4";
+	sc->pinctrl = pinctrl_get_select(&pdev->dev, pstate);
+	if (IS_ERR(sc->pinctrl)) {
+		dev_err(dev, "failed to setup pin configuration\n");
+		ret = -ENXIO;
+		goto err_req_regs;
+	}
 
 	host->hw_name = "samsung-hsmmc";
 	host->ops = &sdhci_s3c_ops;
-- 
1.6.6.rc2



From kgene.kim at samsung.com  Sat Mar 10 11:08:33 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 08:08:33 -0800
Subject: [GIT PULL 2/4] Samsung devel-pd for v3.4
Message-ID: <4F5B7C81.6080301@samsung.com>

Hi Arnd, Olof,

This is Generic Power Domain patches for EXYNOS. Basically, Thomas' 
patches, adding support Generic Power Domain patches are in Rafael's 
tree, linux-pm/linux-next and see below merge commit.
http://git.kernel.org/?p=linux/kernel/git/rafael/linux-pm.git;a=commit;h=dcaad77a8074b6de58e745546bc543d5538404f2
And this adds hooking up G2D and JPEG to Generic PD.

Please pull and here is my preferred resolution when merge this after 
next/board-samsung.

diff --cc arch/arm/mach-exynos/mach-universal_c210.c
index 3663aee,0262417..0b944eb
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@@ -1053,10 -981,6 +1052,7 @@@ static struct platform_device *universa
         &s5p_device_mfc,
         &s5p_device_mfc_l,
         &s5p_device_mfc_r,
-       &exynos4_device_pd[PD_MFC],
-       &exynos4_device_pd[PD_LCD0],
-       &exynos4_device_pd[PD_CAM],
  +      &cam_vt_dio_fixed_reg_dev,
         &cam_i_core_fixed_reg_dev,
         &cam_s_if_fixed_reg_dev,
         &s5p_device_fimc_md,

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

   Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/devel-samsung-pd

Sachin Kamat (2):
       ARM: EXYNOS: Hook up G2D PD to generic PD infrastructure
       ARM: EXYNOS: Hook up JPEG PD to generic PD infrastructure

Thomas Abraham (2):
       PM / Domains: Add OF support
       ARM: EXYNOS: Hook up power domains to generic power domain 
infrastructure

  .../bindings/arm/exynos/power_domain.txt           |   21 ++
  arch/arm/mach-exynos/Kconfig                       |   10 +-
  arch/arm/mach-exynos/Makefile                      |    2 +-
  arch/arm/mach-exynos/dev-pd.c                      |  139 --------------
  arch/arm/mach-exynos/mach-nuri.c                   |   11 -
  arch/arm/mach-exynos/mach-origen.c                 |   14 --
  arch/arm/mach-exynos/mach-smdkv310.c               |   12 --
  arch/arm/mach-exynos/mach-universal_c210.c         |   17 --
  arch/arm/mach-exynos/pm_domains.c                  |  201 
++++++++++++++++++++
  drivers/base/power/domain.c                        |   32 +++
  include/linux/pm_domain.h                          |   12 ++
  11 files changed, 268 insertions(+), 203 deletions(-)
  create mode 100644 
Documentation/devicetree/bindings/arm/exynos/power_domain.txt
  delete mode 100644 arch/arm/mach-exynos/dev-pd.c
  create mode 100644 arch/arm/mach-exynos/pm_domains.c


From w.sang at pengutronix.de  Mon Mar 12 15:02:41 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Mon, 12 Mar 2012 20:02:41 +0100
Subject: [PATCH v7 0/4] USB: OHCI-HCD: Support for LPC32xx
In-Reply-To: <1331463219-23293-1-git-send-email-stigge@antcom.de>
References: <1331463219-23293-1-git-send-email-stigge@antcom.de>
Message-ID: <20120312190241.GA28087@pengutronix.de>

On Sun, Mar 11, 2012 at 11:53:35AM +0100, Roland Stigge wrote:
> These patches add support for the LPC32xx to the ohci-pnx4008 driver and make
> the driver use smbus functions.

Do you have a branch ready to test (USB driver fixes + mach additions)? I'd
like to test but I get lots of conflicts when adding the mach related stuff.
I probably have a different base?

Thanks,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From javier.martin at vista-silicon.com  Fri Mar  9 10:20:47 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Fri,  9 Mar 2012 16:20:47 +0100
Subject: [PATCH v3 11/13] dmaengine: imx-dma: remove unused arg of
 imxdma_sg_next.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1331306449-28591-12-git-send-email-javier.martin@vista-silicon.com>

Since this function is always used with 'desc' as first argument
and 'desc->sg' as second argument, the latter is clearly redundant
and can be removed.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 0b831a7..7b67371 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -204,9 +204,10 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 /*
  * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
  */
-static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct scatterlist *sg = d->sg;
 	unsigned long now;
 
 	now = min(d->len, sg->length);
@@ -249,7 +250,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		d->sg = sg_next(d->sg);
 		if (d->sg) {
 			u32 tmp;
-			imxdma_sg_next(d, d->sg);
+			imxdma_sg_next(d);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -363,7 +364,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		desc->sg = sg_next(desc->sg);
 
 		if (desc->sg) {
-			imxdma_sg_next(desc, desc->sg);
+			imxdma_sg_next(desc);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -473,7 +474,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 			return -EINVAL;
 		}
 
-		imxdma_sg_next(d, d->sg);
+		imxdma_sg_next(d);
 
 		break;
 	default:
-- 
1.7.0.4



From kgene.kim at samsung.com  Sat Mar 10 05:19:04 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 10 Mar 2012 02:19:04 -0800
Subject: [PATCH 0/5] ARM: EXYNOS: update clock part for new EXYNOS SoC
Message-ID: <1331374749-23256-1-git-send-email-kgene.kim@samsung.com>

This patches are splited out as per Olof's suggestion.

And this series is including following:

- move mach-exynos/clock.c to mach-exynos/clock-exynos4.c
- according to moving clock-exynos4.c,
  move <mach/exynos4-clock.h> to "clock-exynos4.h"
- the prefix of clk register replace S5P_ with EXYNOS4_
- add prefix exynos4_ on clk declaration
- add clock registers for exynos4x12-cpufreq

[PATCH 1/5] ARM: EXYNOS: replace clock.c for other new EXYNOS SoCs
[PATCH 2/5] ARM: EXYNOS: use static declaration on regarding clock
[PATCH 3/5] ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for
[PATCH 4/5] PM / devfreq: update the name of EXYNOS clock register
[PATCH 5/5] ARM: EXYNOS: add clock registers for exynos4x12-cpufreq


From alan at signal11.us  Sat Mar 10 18:15:20 2012
From: alan at signal11.us (Alan Ott)
Date: Sat, 10 Mar 2012 18:15:20 -0500
Subject: [PATCH v2 1/1] ARM: at91: Use proper __iomem annotations
In-Reply-To: <1331421281-11570-1-git-send-email-alan@signal11.us>
References: <1331421281-11570-1-git-send-email-alan@signal11.us>
Message-ID: <1331421320-11639-1-git-send-email-alan@signal11.us>

From: Arnd Bergmann <arnd at arndb.de>

MMIO addresses should be of type 'void __iomem *', not integer,
in order to make the build-time type system of the kernel work.

This changes some of the locations in the at91 platform that
I noticed, but there may be more, since I have not yet built
every configuration.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Alan Ott <alan at signal11.us>
---
 arch/arm/mach-at91/at91rm9200.c            |    2 +-
 arch/arm/mach-at91/include/mach/hardware.h |    4 ++++
 arch/arm/mach-at91/setup.c                 |    4 ++--
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 99c3174..239b657 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -27,7 +27,7 @@
 
 static struct map_desc at91rm9200_io_desc[] __initdata = {
 	{
-		.virtual	= AT91_VA_BASE_EMAC,
+		.virtual	= (unsigned long)AT91_VA_BASE_EMAC,
 		.pfn		= __phys_to_pfn(AT91RM9200_BASE_EMAC),
 		.length		= SZ_16K,
 		.type		= MT_DEVICE,
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 2d0e4e9..91375e2 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -75,8 +75,12 @@
  * to 0xFEF78000 .. 0xFF000000.  (544Kb)
  */
 #define AT91_IO_PHYS_BASE	0xFFF78000
+#ifdef __ASSEMBLER__
 #define AT91_IO_VIRT_BASE	(0xFF000000 - AT91_IO_SIZE)
 #else
+#define AT91_IO_VIRT_BASE	(void __iomem *)(0xFF000000 - AT91_IO_SIZE)
+#endif
+#else
 /*
  * Identity mapping for the non MMU case.
  */
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 69d3fc4..809da35 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -57,7 +57,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 {
 	struct map_desc *desc = &sram_desc[bank];
 
-	desc->virtual = AT91_IO_VIRT_BASE - length;
+	desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
 	if (bank > 0)
 		desc->virtual -= sram_desc[bank - 1].length;
 
@@ -72,7 +72,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 }
 
 static struct map_desc at91_io_desc __initdata = {
-	.virtual	= AT91_VA_BASE_SYS,
+	.virtual	= (unsigned long)AT91_VA_BASE_SYS,
 	.pfn		= __phys_to_pfn(AT91_BASE_SYS),
 	.length		= SZ_16K,
 	.type		= MT_DEVICE,
-- 
1.7.0.4



From davem at davemloft.net  Mon Mar 12 20:08:47 2012
From: davem at davemloft.net (David Miller)
Date: Mon, 12 Mar 2012 17:08:47 -0700 (PDT)
Subject: [PATCH v7] lpc32xx: Added ethernet driver
In-Reply-To: <1331243357-27497-1-git-send-email-stigge@antcom.de>
References: <1331243357-27497-1-git-send-email-stigge@antcom.de>
Message-ID: <20120312.170847.850148121128150069.davem@davemloft.net>

From: Roland Stigge <stigge at antcom.de>
Date: Thu,  8 Mar 2012 22:49:17 +0100

> This patch adds an ethernet driver for the LPC32xx ARM SoC.
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

Applied to net-next, thanks.


From w.sang at pengutronix.de  Sun Mar 11 07:50:18 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Sun, 11 Mar 2012 12:50:18 +0100
Subject: mfd: mc13xxx: add I2C support, V2
In-Reply-To: <1331429402-9639-1-git-send-email-marc@cpdesign.com.au>
References: <1331429402-9639-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <20120311115018.GA16825@pengutronix.de>


> The only issue from V1 [0] not addressed is the use of regmap - mainly, I don't
> have the time. I accept that this is a lame excuse but hope that use of regmap 
> can come later if it is required.

I really appreciate the effort, yet I fear that this is a show stopper. It gets
open coded what regmap is trying to abstract, adding complexity to the driver
instead of (probably) reducing it. We could also get caching basically for
free, if this is desired. I think the regmap approach should have been tried
before we go custom. sound/soc/codecs/ad193x.c might give an impression how
regmap spi/i2c in one driver could look like.

Thanks,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From w.sang at pengutronix.de  Sat Mar 10 15:49:55 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Sat, 10 Mar 2012 21:49:55 +0100
Subject: [PATCH v5 3/3] USB: ohci-nxp: Support for LPC32xx
In-Reply-To: <1331408166-11607-4-git-send-email-stigge@antcom.de>
References: <1331408166-11607-1-git-send-email-stigge@antcom.de>
 <1331408166-11607-4-git-send-email-stigge@antcom.de>
Message-ID: <20120310204955.GA14564@pengutronix.de>


> -static void isp1301_configure(void)
> +static u16 i2c_read16(u8 subaddr)
> +{
> +	u16 data;
> +
> +	i2c_master_send(isp1301_i2c_client, &subaddr, 1);
> +	i2c_master_recv(isp1301_i2c_client, (u8 *) &data, 2);
> +
> +	return data;
> +}

Won't i2c_smbus_read_word_data(isp1301_i2c_client, reg) do?

And while we are at it: Could you also try replacing i2c_write() with
i2c_smbus_write_byte_data(isp1301_i2c_client, reg, val)?

No need to recode it (and in general, those solutions will also work with SMBus
for free)

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From w.sang at pengutronix.de  Sun Mar 11 03:43:23 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Sun, 11 Mar 2012 08:43:23 +0100
Subject: [PATCH v5 3/3] USB: ohci-nxp: Support for LPC32xx
In-Reply-To: <4F5BD5BE.3000808@antcom.de>
References: <1331408166-11607-1-git-send-email-stigge@antcom.de>
 <1331408166-11607-4-git-send-email-stigge@antcom.de>
 <20120310204955.GA14564@pengutronix.de>
 <4F5BD5BE.3000808@antcom.de>
Message-ID: <20120311074323.GA30894@pengutronix.de>

> > And while we are at it: Could you also try replacing i2c_write()
> > with i2c_smbus_write_byte_data(isp1301_i2c_client, reg, val)?
> 
> Interestingly now, replacing i2c_write() calls with
> i2c_smbus_write_byte_data() did _not_ work (hardware initialization
> failure). I guess this is due to the differences between i2c and
> smbus, and the hardware only handles the former correctly?

Did you take into consideration that the smbus-call has (client, reg, val) as
arguments while i2c_write has (val, reg), that is you have to swap the
arguments?

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From w.sang at pengutronix.de  Mon Mar 12 15:16:50 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Mon, 12 Mar 2012 20:16:50 +0100
Subject: [PATCH v7 4/4] USB: ohci-nxp: Remove i2c_write(), use smbus
In-Reply-To: <1331463219-23293-5-git-send-email-stigge@antcom.de>
References: <1331463219-23293-1-git-send-email-stigge@antcom.de>
 <1331463219-23293-5-git-send-email-stigge@antcom.de>
Message-ID: <20120312191650.GB28087@pengutronix.de>


> +	i2c_smbus_write_byte_data(isp1301_i2c_client,
> +		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR,
> +		0xFF);

No need to resend, still: Breaking the 80 char limit for such cases is usually
more readable.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From olof at lixom.net  Mon Mar 12 21:23:53 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 12 Mar 2012 18:23:53 -0700
Subject: Conflict between Versatile Express DT conversion and local timer
 updates
In-Reply-To: <20120312235951.GA31601@n2100.arm.linux.org.uk>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <20120312235951.GA31601@n2100.arm.linux.org.uk>
Message-ID: <CAOesGMjt26JgySpcqVT+PsSgGq9cxQWn+msG4DSwo=2ykGz91A@mail.gmail.com>

Hi,

On Mon, Mar 12, 2012 at 4:59 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Mar 12, 2012 at 11:10:16PM +0000, Russell King - ARM Linux wrote:
>> Marc, Pawel,
>>
>> Your changes are conflicting badly. ?Seriously badly. ?So badly that I'm
>> not bothering to fix the conflicts because I can't work out what the fix
>> should be.
>>
>> You both work for the same frigging organization and yet you seem to
>> work completely independently (I really don't care if you work in
>> different departments - the fact of the matter is you're touching the
>> same code in completely different ways with zero coordination between
>> yourselves. ?That's simply broken workflow.)
>>
>> For example, Marc's deleting arch/arm/plat-versatile/localtimer.c, but
>> Pawel is modifying it to add DT support for Versatile Express. ?The
>> correct solution? ?Hell knows. ?And I don't want a solution to the merge
>> conflict. ?I want the merge conflict to go away (because I'm not frigging
>> around applying the same git-rerere immune fixes to a tree I'm regenerating
>> each night for the kernel autobuilder.)
>>
>> I'm getting conflicts in arch/arm/mach-vexpress/ct-ca9x4.c and
>> arch/arm/mach-ux500/timer.c as well, which I'm not going to bother trying
>> to sort out - the obvious solution for ux500/timer.c doesn't look right.
>>
>> I've a mind to drop the localtimer changes on the floor until after this
>> merge window, but unfortunately they're part of devel-stable so I can't.
>
> Correction: I haven't been pushing out my devel-stable branch for
> apparantly two months (according to gitweb, and no one noticed?), so I
> _could_ drop the merge of Marc's tree until the conflicts can be sanely
> resolved.

I haven't noticed because I stopped tracking your tree directly when
you were having server load issues; I tend to have kept an eye on
linux-next-level breakage instead, but probably not as close as I
should have.

Dropping Marc's branch and having him either resubmit on top of
arm-soc like the io cleanup was done, or pull it in as an early
dependency for 3.5 and stage it in an for-armsoc branch sounds like
two good options to me, with no real preference in either direction.



-Olof


From robherring2 at gmail.com  Mon Mar 12 21:34:51 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 12 Mar 2012 20:34:51 -0500
Subject: [PATCH v4 0/2] ARM: Exynos: Add irq_domain and device tree support
 for combiner
In-Reply-To: <1329798806-32482-1-git-send-email-thomas.abraham@linaro.org>
References: <1329798806-32482-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <4F5EA43B.8040802@gmail.com>

On 02/20/2012 10:33 PM, Thomas Abraham wrote:
> Changes since v3:
> - In dt case, the use of fixed gic linux irq number to map the combiner
>   interrupt output is removed. This is replaced with the interrupt number
>   obtained from the gic irq domain. (Thanks to Rob Herring and Grant
>   Likely for this suggestion).
> - Split the patch into two parts - irq_domain and device tree support
>   addition.
> 
> Changes since v2:
> - Rebased to Grant's irqdomain/next branch.
> 
> Changes since v1:
> - Includes all changes suggested by Rob Herring.
> - Tested with SPARSE_IRQ enabled.
> 
> This patchset adds irq_domain and device tree support for the Exynos Interrupt
> Combiner controller.
> 
> The first patch adds a common irq domain for the interrupts managed by the
> interrupt combiners. All the instances of irq combiner reference the common irq
> domain for translating hardware interrupts to linux irq number.
> 
> The second patch adds a interrupt specifier translator to support device tree
> based instantiation. It can translate interrupt specifiers for device nodes
> which use combiner as their interrupt parent.
> 
> This patchset is based on
> http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]
> 
> with all irq_domain (v5) patches merged from
> http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]
> 
> Thomas Abraham (2):
>   ARM: Exynos: Add irq_domain support for interrupt combiner
>   ARM: Exynos: Add device tree support for interrupt combiner
> 
>  .../bindings/arm/samsung/interrupt-combiner.txt    |   48 +++++++++
>  arch/arm/mach-exynos/common.c                      |  112 ++++++++++++++++----
>  2 files changed, 140 insertions(+), 20 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt

Acked-by: Rob Herring <rob.herring at calxeda.com>

Rob


From rob.lee at linaro.org  Mon Mar 12 21:50:14 2012
From: rob.lee at linaro.org (Rob Lee)
Date: Mon, 12 Mar 2012 20:50:14 -0500
Subject: linux-next: manual merge of the cpuidle-cons tree with the
 arm-soc tree
In-Reply-To: <20120313100625.b500f0efb546a9f4ceeb12ba@canb.auug.org.au>
References: <20120309183732.512d3676599da324f4747219@canb.auug.org.au>
 <4F5E1ECC.1040605@atmel.com>
 <CAMXH7KH_vgri3EPRvkXR+LddRUc=0ve=4u7yr51utBfgV5bF3w@mail.gmail.com>
 <20120313100625.b500f0efb546a9f4ceeb12ba@canb.auug.org.au>
Message-ID: <CAMXH7KFw703n3UyXFj0cGZ_scpvHR8c+iguuUQPuEQgfswnaRw@mail.gmail.com>

On Mon, Mar 12, 2012 at 6:06 PM, Stephen Rothwell <sfr at canb.auug.org.au> wrote:
> Hi Rob,
>
> On Mon, 12 Mar 2012 12:03:48 -0500 Rob Lee <rob.lee at linaro.org> wrote:
>>
>> On Mon, Mar 12, 2012 at 11:05 AM, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
>> > -----BEGIN PGP SIGNED MESSAGE-----
>> > Hash: SHA1
>> >
>> > On 03/09/2012 08:37 AM, Stephen Rothwell :
>> >>
>> >> Today's linux-next merge of the cpuidle-cons tree got a conflict
>> >> in arch/arm/mach-at91/cpuidle.c between commit 00482a4078f4 ("ARM:
>> >> at91: implement the standby function for pm/cpuidle") from the
>> >> arm-soc tree and commit 7a1f6e72dce1 ("ARM: at91: Consolidate time
>> >> keeping and irq enable") from the cpuidle-cons tree.
>> >>
>> >> I fixed it up (I think - see below) and can carry the fix as
>> >> necessary.
>> >
>> > Yes: resolution correct. Please carry it.
>>
>> Who should carry this fixup and related necessary at91 changes? ?Me?
>> FYI, my at91 changes are dependent on my core cpuidle change, but my
>> core cpuidle changes do not require any at91 changes as the at91 and
>> other platform changes were only made to consolidate duplicate code.
>
> I will carry the fixup and Linus will presumably do the same fix when he
> merges these trees in his tree. ?I am not sure what you mean by "related
> at91 changes".
>

Thanks Stephen.  By "related changes" I just meant that if I were to
make a branch to carry the fixup, I'd need to all merge in the at91
related changes that are on linux-next but not on an rc tag yet.  But
please ignore this statement if it doesn't make sense.  I'm not yet
knowledgeable on the workflow once submitted patchsets reach this
level.

> --
> Cheers,
> Stephen Rothwell ? ? ? ? ? ? ? ? ? ?sfr at canb.auug.org.au


From jason at lakedaemon.net  Mon Mar 12 21:57:42 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 13 Mar 2012 01:57:42 +0000
Subject: [PATCH 0/7 v4] ARM: kirkwood: fdt: convert kirkwood to fdt
In-Reply-To: <cover.1330625877.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
Message-ID: <cover.1331601448.git.jason@lakedaemon.net>

This series begins the process of converting all of the drivers initialized
from kirkwood_init() to devicetree.

The first three patches are code cleanup from Andrew Lunn.

The rest of the series is the initial conversion to devicetree for kirkwood,
use by dreamplug, and devicetree bindings for drivers that don't use tclk or
pinux.  These should be safe to merge as they won't interfere with the
clk/clkdev work Andrew Lunn is working on.

Overall changes since v3:

	- squashed several fixup patches into the series (use mrvl, use
	  inclusive address sizes)
	- applied Arnd's suggestion for serial ports in kirkwood.dtsi, added my
	  idea of defining serial clock in dts.
	- moved dreamplug_init() out of board-dt.c (into board-dreamplug.c) to
	  facilitate the orderly arrival of new boards with fdt support (Jamie
	  Lentin's boards)
	- moved all non-fdt cleanups to the beginning of the series.
	- removed mv_cesa, mv_sata, and orion-ehci from this series as they
	  depend on intc/dma/clock to work properly
	- removed Ack's and Reviewed-By's on patches with significant changes
		- Grant's Ack remains on the "wdt: use resource" patch as it is
		  a reduced scope version (no fdt bindings), otherwise,
		  identical to code originally Acked.  Please let me know if
		  that's not appropriate.

Overall changes since v2:

	- added Andrew Lunn's cleanup patches
	- reshuffled to more logical order
	- wrapped all struct of_device_id[]'s in #ifdef CONFIG_OF
	- s/marvell,/mrvl,/g
	- added orion-ehci
	- added mv_sata
	- prevent clocks from gating when booting from devicetree

Drivers yet to be converted are:

	mv_cesa:    needs intc in fdt (next on list)
	mv_sata:    needs dma, intc
	orion-ehci: needs dma, intc
	orion-spi:  uses tclk
	orion-wdt:  uses tclk
	mvsdio:     uses tclk
	i2c:        uses freq_m/freq_n, not sure if that should use clk/clkdev
	mv_xor:     haven't figured out howto do shared resources/dma in fdt
	ge0/ge1:    haven't looked at it yet
	nand:       not needed for dreamplug, Jamie Lentin is working on it

Please be aware that this is a complete reshuffle of the whole series and is
based purely against v3.3-rc3.

Interested folks can pull from:

git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_for_3.4


Andrew Lunn (3):
  ARM: orion: spi: remove enable_clock_fix which is not used
  ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data.
  ARM: orion: wdt: use resource vice direct access

Jason Cooper (4):
  ARM: kirkwood: add dreamplug (fdt) support.
  ARM: kirkwood: convert uart0 to devicetree.
  ARM: kirkwood: rtc-mv devicetree bindings
  ARM: kirkwood: use devicetree for rtc-mv

 arch/arm/boot/dts/kirkwood-dreamplug.dts |   24 +++++
 arch/arm/boot/dts/kirkwood.dtsi          |   36 +++++++
 arch/arm/mach-kirkwood/Kconfig           |   14 +++
 arch/arm/mach-kirkwood/Makefile          |    2 +
 arch/arm/mach-kirkwood/Makefile.boot     |    2 +
 arch/arm/mach-kirkwood/board-dreamplug.c |  149 ++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c        |   75 +++++++++++++++
 arch/arm/mach-kirkwood/common.c          |   11 +-
 arch/arm/mach-kirkwood/common.h          |   11 ++
 arch/arm/plat-orion/common.c             |    7 +-
 arch/arm/plat-orion/include/plat/audio.h |    1 -
 drivers/rtc/rtc-mv.c                     |    9 ++
 drivers/spi/spi-orion.c                  |    5 -
 drivers/watchdog/orion_wdt.c             |   24 +++--
 include/linux/spi/orion_spi.h            |    1 -
 15 files changed, 348 insertions(+), 23 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-dreamplug.dts
 create mode 100644 arch/arm/boot/dts/kirkwood.dtsi
 create mode 100644 arch/arm/mach-kirkwood/board-dreamplug.c
 create mode 100644 arch/arm/mach-kirkwood/board-dt.c

-- 
1.7.3.4



From jason at lakedaemon.net  Mon Mar 12 21:57:43 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 13 Mar 2012 01:57:43 +0000
Subject: [PATCH 1/7] ARM: orion: spi: remove enable_clock_fix which is not used
In-Reply-To: <cover.1331601448.git.jason@lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
Message-ID: <09fda0555ea860b7b6bfdf3fef0ebe08926edaa1.1331601448.git.jason@lakedaemon.net>

From: Andrew Lunn <andrew at lunn.ch>

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
---
 drivers/spi/spi-orion.c       |    5 -----
 include/linux/spi/orion_spi.h |    1 -
 2 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index 13448c8..e496f79 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -359,11 +359,6 @@ static int orion_spi_setup(struct spi_device *spi)
 
 	orion_spi = spi_master_get_devdata(spi->master);
 
-	/* Fix ac timing if required.   */
-	if (orion_spi->spi_info->enable_clock_fix)
-		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
-				  (1 << 14));
-
 	if ((spi->max_speed_hz == 0)
 			|| (spi->max_speed_hz > orion_spi->max_speed))
 		spi->max_speed_hz = orion_spi->max_speed;
diff --git a/include/linux/spi/orion_spi.h b/include/linux/spi/orion_spi.h
index decf6d8..b4d9fa6 100644
--- a/include/linux/spi/orion_spi.h
+++ b/include/linux/spi/orion_spi.h
@@ -11,7 +11,6 @@
 
 struct orion_spi_info {
 	u32	tclk;		/* no <linux/clk.h> support yet */
-	u32	enable_clock_fix;
 };
 
 
-- 
1.7.3.4



From jason at lakedaemon.net  Mon Mar 12 21:57:47 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 13 Mar 2012 01:57:47 +0000
Subject: [PATCH 5/7 v2] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <cover.1331601448.git.jason@lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
Message-ID: <970083c931bbd5c58be3aa982a66fddc48ceb534.1331601448.git.jason@lakedaemon.net>

This uart is the primary console for the dreamplug.  Removed
kirkwood_uart0_init() call from board-dreamplug.c.

There are two uarts on the kirkwood SoC, all or none of them may be
enabled, and the clock-frequency is board-dependant.  So, enabling and
clock-frequency are left to the board dts.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes from v1:

* moved on-chip peripherals (uart's here) in kirkwood.dtsi and used ranges to
  simplify addressing
* disable uarts by default as not all boards enable them.  Can be enabled in
  board file
* specify clock-frequency in board file as it is board specific.  of_serial
  prints an error message if it isn't specified (view with earlyprintk)
* removed previous versions Reviewed-By's and Acked-By's as this is
  significantly different from the previous version.

 arch/arm/boot/dts/kirkwood-dreamplug.dts |    7 +++++++
 arch/arm/boot/dts/kirkwood.dtsi          |   26 +++++++++++++++++++++++++-
 arch/arm/mach-kirkwood/board-dreamplug.c |    2 --
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 9946d01..a5376b8 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -14,4 +14,11 @@
 	chosen {
 		bootargs = "console=ttyS0,115200n8 earlyprintk";
 	};
+
+	ocp at f1000000 {
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 702b955..825310b 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -2,5 +2,29 @@
 
 / {
 	compatible = "mrvl,kirkwood";
-};
 
+	ocp at f1000000 {
+		compatible = "simple-bus";
+		ranges = <0 0xf1000000 0x1000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		serial at 12000 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x100>;
+			reg-shift = <2>;
+			interrupts = <33>;
+			/* set clock-frequency in board dts */
+			status = "disabled";
+		};
+
+		serial at 12100 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x100>;
+			reg-shift = <2>;
+			interrupts = <34>;
+			/* set clock-frequency in board dts */
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index 3b37315..3fbfb7d 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -135,8 +135,6 @@ void __init dreamplug_init(void)
 	 */
 	kirkwood_mpp_conf(dreamplug_mpp_config);
 
-	kirkwood_uart0_init();
-
 	spi_register_board_info(dreamplug_spi_slave_info,
 				ARRAY_SIZE(dreamplug_spi_slave_info));
 	kirkwood_spi_init();
-- 
1.7.3.4



From jason at lakedaemon.net  Mon Mar 12 21:57:49 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 13 Mar 2012 01:57:49 +0000
Subject: [PATCH 7/7] ARM: kirkwood: use devicetree for rtc-mv
In-Reply-To: <cover.1331601448.git.jason@lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
Message-ID: <92d02581e0fce75f84d61edf55678108237e881a.1331601448.git.jason@lakedaemon.net>

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
 arch/arm/mach-kirkwood/board-dt.c |    1 -
 arch/arm/mach-kirkwood/common.c   |    2 +-
 arch/arm/mach-kirkwood/common.h   |    1 -
 4 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 825310b..3474ef8 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -26,5 +26,11 @@
 			/* set clock-frequency in board dts */
 			status = "disabled";
 		};
+
+		rtc at 10300 {
+			compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc";
+			reg = <0x10300 0x20>;
+			interrupts = <53>;
+		};
 	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index ce008f2..0819240 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -43,7 +43,6 @@ static void __init kirkwood_dt_init(void)
 #endif
 
 	/* internal devices that every board has */
-	kirkwood_rtc_init();
 	kirkwood_wdt_init();
 	kirkwood_xor0_init();
 	kirkwood_xor1_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index ae90f60..ef45244 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -162,7 +162,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-void __init kirkwood_rtc_init(void)
+static void __init kirkwood_rtc_init(void)
 {
 	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 194daa9..d7063eb 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -57,7 +57,6 @@ void dreamplug_init(void);
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-void kirkwood_rtc_init(void);
 void kirkwood_wdt_init(void);
 void kirkwood_xor0_init(void);
 void kirkwood_xor1_init(void);
-- 
1.7.3.4



From jason at lakedaemon.net  Mon Mar 12 21:57:44 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 13 Mar 2012 01:57:44 +0000
Subject: [PATCH 2/7] ARM: Kirkwood: Remove tclk from
 kirkwood_asoc_platform_data.
In-Reply-To: <cover.1331601448.git.jason@lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
Message-ID: <9d2db81e89358f51a24f4d189586ac7b1aef8547.1331601448.git.jason@lakedaemon.net>

From: Andrew Lunn <andrew at lunn.ch>

It is not used anywhere in the sound driver.

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/mach-kirkwood/common.c          |    1 -
 arch/arm/plat-orion/include/plat/audio.h |    1 -
 2 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index cc15426..eacf7f5 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -449,7 +449,6 @@ void __init kirkwood_init(void)
 {
 	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
 		kirkwood_id(), kirkwood_tclk);
-	kirkwood_i2s_data.tclk = kirkwood_tclk;
 
 	/*
 	 * Disable propagation of mbus errors to the CPU local bus,
diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h
index 885f8ab..d6a55bd 100644
--- a/arch/arm/plat-orion/include/plat/audio.h
+++ b/arch/arm/plat-orion/include/plat/audio.h
@@ -2,7 +2,6 @@
 #define __PLAT_AUDIO_H
 
 struct kirkwood_asoc_platform_data {
-	u32 tclk;
 	int burst;
 };
 #endif
-- 
1.7.3.4



From jason at lakedaemon.net  Mon Mar 12 21:57:48 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 13 Mar 2012 01:57:48 +0000
Subject: [PATCH 6/7] ARM: kirkwood: rtc-mv devicetree bindings
In-Reply-To: <cover.1331601448.git.jason@lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
Message-ID: <0b9921e304cb46af9c4fbc8b7b8c8b9ba3d18654.1331601448.git.jason@lakedaemon.net>

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 drivers/rtc/rtc-mv.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c
index 768e2ed..0dd8421 100644
--- a/drivers/rtc/rtc-mv.c
+++ b/drivers/rtc/rtc-mv.c
@@ -12,6 +12,7 @@
 #include <linux/bcd.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/delay.h>
 #include <linux/gfp.h>
 #include <linux/module.h>
@@ -294,11 +295,19 @@ static int __exit mv_rtc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id rtc_mv_of_match_table[] = {
+	{ .compatible = "mrvl,orion-rtc", },
+	{}
+};
+#endif
+
 static struct platform_driver mv_rtc_driver = {
 	.remove		= __exit_p(mv_rtc_remove),
 	.driver		= {
 		.name	= "rtc-mv",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(rtc_mv_of_match_table),
 	},
 };
 
-- 
1.7.3.4



From jason at lakedaemon.net  Mon Mar 12 21:57:45 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 13 Mar 2012 01:57:45 +0000
Subject: [PATCH 3/7 v2] ARM: orion: wdt: use resource vice direct access
In-Reply-To: <cover.1331601448.git.jason@lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
Message-ID: <e8cd3863d70b322ee7625d0e49af0acdb82644fc.1331601448.git.jason@lakedaemon.net>

From: Andrew Lunn <andrew at lunn.ch>

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
---
Note: This code is the exact same as that originally Acked by Grant.  I've
simply removed the fdt bindings, as I need to hold off until common clock is
added.  If it's not appropriate to retain his Ack here, please let me know.

 arch/arm/plat-orion/common.c |    7 ++++++-
 drivers/watchdog/orion_wdt.c |   24 +++++++++++++++---------
 2 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index e5a2fde..eadd1cd 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -21,6 +21,7 @@
 #include <plat/orion_wdt.h>
 #include <plat/mv_xor.h>
 #include <plat/ehci-orion.h>
+#include <mach/bridge-regs.h>
 
 /* Fill in the resources structure and link it into the platform
    device structure. There is always a memory region, and nearly
@@ -568,13 +569,17 @@ void __init orion_spi_1_init(unsigned long mapbase,
  ****************************************************************************/
 static struct orion_wdt_platform_data orion_wdt_data;
 
+static struct resource orion_wdt_resource =
+		DEFINE_RES_MEM(TIMER_VIRT_BASE, 0x28);
+
 static struct platform_device orion_wdt_device = {
 	.name		= "orion_wdt",
 	.id		= -1,
 	.dev		= {
 		.platform_data	= &orion_wdt_data,
 	},
-	.num_resources	= 0,
+	.resource	= &orion_wdt_resource,
+	.num_resources	= 1,
 };
 
 void __init orion_wdt_init(unsigned long tclk)
diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
index 4ad78f8..1368e4c 100644
--- a/drivers/watchdog/orion_wdt.c
+++ b/drivers/watchdog/orion_wdt.c
@@ -28,9 +28,9 @@
 /*
  * Watchdog timer block registers.
  */
-#define TIMER_CTRL		(TIMER_VIRT_BASE + 0x0000)
+#define TIMER_CTRL		0x0000
 #define  WDT_EN			0x0010
-#define WDT_VAL			(TIMER_VIRT_BASE + 0x0024)
+#define WDT_VAL			0x0024
 
 #define WDT_MAX_CYCLE_COUNT	0xffffffff
 #define WDT_IN_USE		0
@@ -40,6 +40,7 @@ static int nowayout = WATCHDOG_NOWAYOUT;
 static int heartbeat = -1;		/* module parameter (seconds) */
 static unsigned int wdt_max_duration;	/* (seconds) */
 static unsigned int wdt_tclk;
+static void __iomem *wdt_reg;
 static unsigned long wdt_status;
 static DEFINE_SPINLOCK(wdt_lock);
 
@@ -48,7 +49,7 @@ static void orion_wdt_ping(void)
 	spin_lock(&wdt_lock);
 
 	/* Reload watchdog duration */
-	writel(wdt_tclk * heartbeat, WDT_VAL);
+	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
 
 	spin_unlock(&wdt_lock);
 }
@@ -60,7 +61,7 @@ static void orion_wdt_enable(void)
 	spin_lock(&wdt_lock);
 
 	/* Set watchdog duration */
-	writel(wdt_tclk * heartbeat, WDT_VAL);
+	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
 
 	/* Clear watchdog timer interrupt */
 	reg = readl(BRIDGE_CAUSE);
@@ -68,9 +69,9 @@ static void orion_wdt_enable(void)
 	writel(reg, BRIDGE_CAUSE);
 
 	/* Enable watchdog timer */
-	reg = readl(TIMER_CTRL);
+	reg = readl(wdt_reg + TIMER_CTRL);
 	reg |= WDT_EN;
-	writel(reg, TIMER_CTRL);
+	writel(reg, wdt_reg + TIMER_CTRL);
 
 	/* Enable reset on watchdog */
 	reg = readl(RSTOUTn_MASK);
@@ -92,9 +93,9 @@ static void orion_wdt_disable(void)
 	writel(reg, RSTOUTn_MASK);
 
 	/* Disable watchdog timer */
-	reg = readl(TIMER_CTRL);
+	reg = readl(wdt_reg + TIMER_CTRL);
 	reg &= ~WDT_EN;
-	writel(reg, TIMER_CTRL);
+	writel(reg, wdt_reg + TIMER_CTRL);
 
 	spin_unlock(&wdt_lock);
 }
@@ -102,7 +103,7 @@ static void orion_wdt_disable(void)
 static int orion_wdt_get_timeleft(int *time_left)
 {
 	spin_lock(&wdt_lock);
-	*time_left = readl(WDT_VAL) / wdt_tclk;
+	*time_left = readl(wdt_reg + WDT_VAL) / wdt_tclk;
 	spin_unlock(&wdt_lock);
 	return 0;
 }
@@ -236,6 +237,7 @@ static struct miscdevice orion_wdt_miscdev = {
 static int __devinit orion_wdt_probe(struct platform_device *pdev)
 {
 	struct orion_wdt_platform_data *pdata = pdev->dev.platform_data;
+	struct resource *res;
 	int ret;
 
 	if (pdata) {
@@ -245,6 +247,10 @@ static int __devinit orion_wdt_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	wdt_reg = ioremap(res->start, resource_size(res));
+
 	if (orion_wdt_miscdev.parent)
 		return -EBUSY;
 	orion_wdt_miscdev.parent = &pdev->dev;
-- 
1.7.3.4



From jason at lakedaemon.net  Mon Mar 12 21:57:46 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 13 Mar 2012 01:57:46 +0000
Subject: [PATCH 4/7 v4] ARM: kirkwood: add dreamplug (fdt) support.
In-Reply-To: <cover.1331601448.git.jason@lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
Message-ID: <0032addd7e94c5d4d1a3a0be77fe79bcffee53db.1331601448.git.jason@lakedaemon.net>

Initially, copied guruplug-setup.c and did s/guruplug/dreamplug/g.
Then, switched to SPI based NOR flash.

After talking to Arnd Bergman, chose an incremental approach to adding
devicetree support.  First, we use the dtb to tell us we are on the
dreamplug, then we gradually port over drivers.

Driver porting will start with the uart (see next patch), and progress
from there.  Next, all drivers not needing common clock (kirkwood_tclk)
or pinmux.  Then, remain drivers as that support hits the tree.

We need to absorb kirkwood_init() into kirkwood_dt_init() so that as we
convert drivers, we can remove the platform call, eg
kirkwood_rtc_init().  This maintains compatibility with non-fdt
configurations because they still call kirkwood_init() in common.c.

As drivers are converted, we will reinstate the 'static' qualifier in
common.c.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes from v3:

* squashed absorbing kirkwood_init() into board-dt.c into this patch
* split dreamplug_init() out of board-dt.c into board-dreamplug.c to facilitate
  other boards coming in during conversion process.
* removed Acked's and Reviewed-By's as code has changed significantly and
  absorbed several other patches.

Changes from v2:

* s/marvell,/mrvl,/g for compatible properties

 arch/arm/boot/dts/kirkwood-dreamplug.dts |   17 ++++
 arch/arm/boot/dts/kirkwood.dtsi          |    6 +
 arch/arm/mach-kirkwood/Kconfig           |   14 +++
 arch/arm/mach-kirkwood/Makefile          |    2 +
 arch/arm/mach-kirkwood/Makefile.boot     |    2 +
 arch/arm/mach-kirkwood/board-dreamplug.c |  151 ++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c        |   76 +++++++++++++++
 arch/arm/mach-kirkwood/common.c          |   12 +-
 arch/arm/mach-kirkwood/common.h          |   12 +++
 9 files changed, 286 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-dreamplug.dts
 create mode 100644 arch/arm/boot/dts/kirkwood.dtsi
 create mode 100644 arch/arm/mach-kirkwood/board-dreamplug.c
 create mode 100644 arch/arm/mach-kirkwood/board-dt.c

diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
new file mode 100644
index 0000000..9946d01
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -0,0 +1,17 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "Globalscale Technologies Dreamplug";
+	compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
new file mode 100644
index 0000000..702b955
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -0,0 +1,6 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "mrvl,kirkwood";
+};
+
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7fc603b..90ceab7 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -44,6 +44,20 @@ config MACH_GURUPLUG
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell GuruPlug Reference Board.
 
+config ARCH_KIRKWOOD_DT
+	bool "Marvell Kirkwood Flattened Device Tree"
+	select USE_OF
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell Kirkwood using flattened device tree.
+
+config MACH_DREAMPLUG_DT
+	bool "Marvell DreamPlug (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell DreamPlug (Flattened Device Tree).
+
 config MACH_TS219
 	bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
 	help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 5dcaa81..e299a95 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -20,3 +20,5 @@ obj-$(CONFIG_MACH_NET5BIG_V2)		+= netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_T5325)		+= t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
+obj-$(CONFIG_ARCH_KIRKWOOD_DT)		+= board-dt.o
+obj-$(CONFIG_MACH_DREAMPLUG_DT)		+= board-dreamplug.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 760a0ef..16f9385 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -1,3 +1,5 @@
    zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
new file mode 100644
index 0000000..3b37315
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2012 (C), Jason Cooper <jason at lakedaemon.net>
+ *
+ * arch/arm/mach-kirkwood/board-dt.c
+ *
+ * Marvell DreamPlug Reference Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+struct mtd_partition dreamplug_partitions[] = {
+	{
+		.name	= "u-boot",
+		.size	= SZ_512K,
+		.offset = 0,
+	},
+	{
+		.name	= "u-boot env",
+		.size	= SZ_64K,
+		.offset = SZ_512K + SZ_512K,
+	},
+	{
+		.name	= "dtb",
+		.size	= SZ_64K,
+		.offset = SZ_512K + SZ_512K + SZ_512K,
+	},
+};
+
+static const struct flash_platform_data dreamplug_spi_slave_data = {
+	.type		= "mx25l1606e",
+	.name		= "spi_flash",
+	.parts		= dreamplug_partitions,
+	.nr_parts	= ARRAY_SIZE(dreamplug_partitions),
+};
+
+static struct spi_board_info __initdata dreamplug_spi_slave_info[] = {
+	{
+		.modalias	= "m25p80",
+		.platform_data	= &dreamplug_spi_slave_data,
+		.irq		= -1,
+		.max_speed_hz	= 50000000,
+		.bus_num	= 0,
+		.chip_select	= 0,
+	},
+};
+
+static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
+};
+
+static struct mv_sata_platform_data dreamplug_sata_data = {
+	.n_ports	= 1,
+};
+
+static struct mvsdio_platform_data dreamplug_mvsdio_data = {
+	/* unfortunately the CD signal has not been connected */
+};
+
+static struct gpio_led dreamplug_led_pins[] = {
+	{
+		.name			= "dreamplug:blue:bluetooth",
+		.gpio			= 47,
+		.active_low		= 1,
+	},
+	{
+		.name			= "dreamplug:green:wifi",
+		.gpio			= 48,
+		.active_low		= 1,
+	},
+	{
+		.name			= "dreamplug:green:wifi_ap",
+		.gpio			= 49,
+		.active_low		= 1,
+	},
+};
+
+static struct gpio_led_platform_data dreamplug_led_data = {
+	.leds		= dreamplug_led_pins,
+	.num_leds	= ARRAY_SIZE(dreamplug_led_pins),
+};
+
+static struct platform_device dreamplug_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &dreamplug_led_data,
+	}
+};
+
+static unsigned int dreamplug_mpp_config[] __initdata = {
+	MPP0_SPI_SCn,
+	MPP1_SPI_MOSI,
+	MPP2_SPI_SCK,
+	MPP3_SPI_MISO,
+	MPP47_GPIO,	/* Bluetooth LED */
+	MPP48_GPIO,	/* Wifi LED */
+	MPP49_GPIO,	/* Wifi AP LED */
+	0
+};
+
+void __init dreamplug_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_mpp_conf(dreamplug_mpp_config);
+
+	kirkwood_uart0_init();
+
+	spi_register_board_info(dreamplug_spi_slave_info,
+				ARRAY_SIZE(dreamplug_spi_slave_info));
+	kirkwood_spi_init();
+
+	kirkwood_ehci_init();
+	kirkwood_ge00_init(&dreamplug_ge00_data);
+	kirkwood_ge01_init(&dreamplug_ge01_data);
+	kirkwood_sata_init(&dreamplug_sata_data);
+	kirkwood_sdio_init(&dreamplug_mvsdio_data);
+
+	platform_device_register(&dreamplug_leds);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
new file mode 100644
index 0000000..ce008f2
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2012 (C), Jason Cooper <jason at lakedaemon.net>
+ *
+ * arch/arm/mach-kirkwood/board-dt.c
+ *
+ * Marvell DreamPlug Reference Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/bridge-regs.h>
+#include "common.h"
+
+static struct of_device_id kirkwood_dt_match_table[] __initdata = {
+	{ .compatible = "simple-bus", },
+	{ }
+};
+
+static void __init kirkwood_dt_init(void)
+{
+	pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
+
+	/*
+	 * Disable propagation of mbus errors to the CPU local bus,
+	 * as this causes mbus errors (which can occur for example
+	 * for PCI aborts) to throw CPU aborts, which we're not set
+	 * up to deal with.
+	 */
+	writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
+
+	kirkwood_setup_cpu_mbus();
+
+#ifdef CONFIG_CACHE_FEROCEON_L2
+	kirkwood_l2_init();
+#endif
+
+	/* internal devices that every board has */
+	kirkwood_rtc_init();
+	kirkwood_wdt_init();
+	kirkwood_xor0_init();
+	kirkwood_xor1_init();
+	kirkwood_crypto_init();
+
+#ifdef CONFIG_KEXEC
+	kexec_reinit = kirkwood_enable_pcie;
+#endif
+
+	if (of_machine_is_compatible("globalscale,dreamplug"))
+		dreamplug_init();
+
+	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
+}
+
+static const char *kirkwood_dt_board_compat[] = {
+	"globalscale,dreamplug",
+	NULL
+};
+
+DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
+	/* Maintainer: Jason Cooper <jason at lakedaemon.net> */
+	.map_io		= kirkwood_map_io,
+	.init_early	= kirkwood_init_early,
+	.init_irq	= kirkwood_init_irq,
+	.timer		= &kirkwood_timer,
+	.init_machine	= kirkwood_dt_init,
+	.restart	= kirkwood_restart,
+	.dt_compat	= kirkwood_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index eacf7f5..ae90f60 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -162,7 +162,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-static void __init kirkwood_rtc_init(void)
+void __init kirkwood_rtc_init(void)
 {
 	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
@@ -278,7 +278,7 @@ void __init kirkwood_crypto_init(void)
 /*****************************************************************************
  * XOR0
  ****************************************************************************/
-static void __init kirkwood_xor0_init(void)
+void __init kirkwood_xor0_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_XOR0;
 
@@ -290,7 +290,7 @@ static void __init kirkwood_xor0_init(void)
 /*****************************************************************************
  * XOR1
  ****************************************************************************/
-static void __init kirkwood_xor1_init(void)
+void __init kirkwood_xor1_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_XOR1;
 
@@ -302,7 +302,7 @@ static void __init kirkwood_xor1_init(void)
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-static void __init kirkwood_wdt_init(void)
+void __init kirkwood_wdt_init(void)
 {
 	orion_wdt_init(kirkwood_tclk);
 }
@@ -391,7 +391,7 @@ void __init kirkwood_audio_init(void)
 /*
  * Identify device ID and revision.
  */
-static char * __init kirkwood_id(void)
+char * __init kirkwood_id(void)
 {
 	u32 dev, rev;
 
@@ -434,7 +434,7 @@ static char * __init kirkwood_id(void)
 	}
 }
 
-static void __init kirkwood_l2_init(void)
+void __init kirkwood_l2_init(void)
 {
 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
 	writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 9071a39..194daa9 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -51,6 +51,18 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev
 void kirkwood_audio_init(void);
 void kirkwood_restart(char, const char *);
 
+/* board init functions for drivers not converted to fdt */
+void dreamplug_init(void);
+
+/* early init functions not converted to fdt yet */
+char *kirkwood_id(void);
+void kirkwood_l2_init(void);
+void kirkwood_rtc_init(void);
+void kirkwood_wdt_init(void);
+void kirkwood_xor0_init(void);
+void kirkwood_xor1_init(void);
+void kirkwood_crypto_init(void);
+
 extern int kirkwood_tclk;
 extern struct sys_timer kirkwood_timer;
 
-- 
1.7.3.4



From jason at lakedaemon.net  Mon Mar 12 22:07:34 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 12 Mar 2012 22:07:34 -0400
Subject: ARM926EJS boot failure on v3.3, __iounmap
In-Reply-To: <CAKON4OyURmGP79oJaCkAw1dx3orynZDZSqZOC_t=PTKwHWaRJQ@mail.gmail.com>
References: <CAKON4OzL9HtF+3bxzC9zexd7QgAFd5R7Wr=QTShYR+Kk1b4L+g@mail.gmail.com>
 <CAKON4OyURmGP79oJaCkAw1dx3orynZDZSqZOC_t=PTKwHWaRJQ@mail.gmail.com>
Message-ID: <20120313020734.GE5050@titan.lakedaemon.net>

On Mon, Mar 12, 2012 at 07:31:58PM -0400, jonsmirl at gmail.com wrote:
> The answer to this is that as of v3.3 you can't have overlapping IO
> regions. The code I was porting has a large define covering peripheral
> space and then many smaller ones inside the region, one for each
> device. I needed to delete the defines for those inner devices.

I got bit by this last week with the dreamplug (kirkwood), I worked
around it by disabling CONFIG_ARM_PATCH_PHYS_VIRT.  Could you elaborate
on your solution so I can work towards a real fix on
plat-orion/mach-kirkwood?

Thanks,

Jason.


From jonsmirl at gmail.com  Mon Mar 12 22:13:41 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Mon, 12 Mar 2012 22:13:41 -0400
Subject: ARM926EJS boot failure on v3.3, __iounmap
In-Reply-To: <20120313020734.GE5050@titan.lakedaemon.net>
References: <CAKON4OzL9HtF+3bxzC9zexd7QgAFd5R7Wr=QTShYR+Kk1b4L+g@mail.gmail.com>
 <CAKON4OyURmGP79oJaCkAw1dx3orynZDZSqZOC_t=PTKwHWaRJQ@mail.gmail.com>
 <20120313020734.GE5050@titan.lakedaemon.net>
Message-ID: <CAKON4OzvF-MgEV2AabZ3gWeC+-7T8GpGMMTLpSba6_OERCAyvw@mail.gmail.com>

On Mon, Mar 12, 2012 at 10:07 PM, Jason Cooper <jason at lakedaemon.net> wrote:
> On Mon, Mar 12, 2012 at 07:31:58PM -0400, jonsmirl at gmail.com wrote:
>> The answer to this is that as of v3.3 you can't have overlapping IO
>> regions. The code I was porting has a large define covering peripheral
>> space and then many smaller ones inside the region, one for each
>> device. I needed to delete the defines for those inner devices.
>
> I got bit by this last week with the dreamplug (kirkwood), I worked
> around it by disabling CONFIG_ARM_PATCH_PHYS_VIRT. ?Could you elaborate
> on your solution so I can work towards a real fix on
> plat-orion/mach-kirkwood?

Somewhere you are allocating an array of map_desc. These regions can't
overlap anymore.

static struct map_desc lpc313x_io_desc[] __initdata = {
	{
		.virtual	= io_p2v(IO_INTC_PHYS),
		.pfn		= __phys_to_pfn(IO_INTC_PHYS),
		.length		= IO_INTC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= io_p2v(IO_APB01_PHYS),
		.pfn		= __phys_to_pfn(IO_APB01_PHYS),
		.length		= IO_APB01_SIZE,
		.type		= MT_DEVICE
	},
....



>
> Thanks,
>
> Jason.



-- 
Jon Smirl
jonsmirl at gmail.com


From mturquette at ti.com  Mon Mar 12 23:16:36 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Mon, 12 Mar 2012 20:16:36 -0700
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <20120312115117.GN3852@pengutronix.de>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
 <20120311113414.GM3852@pengutronix.de>
 <CAJOA=zMdkLB-DCPOk=kz5mn6BK6A_swocyCHJHeGE6H7FxBbmQ@mail.gmail.com>
 <20120312115117.GN3852@pengutronix.de>
Message-ID: <CAJOA=zPx0ARsoO4ueSTMe_z2Gs4xG4P2qn1=-vHFf7_k=+K6hQ@mail.gmail.com>

On Mon, Mar 12, 2012 at 4:51 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Sun, Mar 11, 2012 at 02:24:46PM -0700, Turquette, Mike wrote:
>> On Sun, Mar 11, 2012 at 4:34 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>> > Hi Mike,
>> >
>> > I was about to give my tested-by when I decided to test the set_rate
>> > function. Unfortunately this is broken for several reasons. I'll try
>> > to come up with a fixup series later the day.
>>
>> I haven't tested clk_set_rate since V4, but I also haven't changed the
>> code appreciably. ?I'll retest on my end also.
>>
>> > On Fri, Mar 09, 2012 at 11:54:23PM -0800, Mike Turquette wrote:
>> >> + ? ? /* find the new rate and see if parent rate should change too */
>> >> + ? ? WARN_ON(!clk->ops->round_rate);
>> >> +
>> >> + ? ? new_rate = clk->ops->round_rate(clk->hw, rate, &parent_new_rate);
>> >
>> > You don't need a WARN_ON when you derefence clk->ops->round_rate anyway.
>>
>> Agreed that the WARN_ON should not be there.
>>
>> The v6 Documentation/clk.txt states that .round_rate is mandatory for
>> clocks that can adjust their rate, but I need to clarify this a bit
>> more. ?Ideally we want to be able to call clk_set_rate on any clock
>> and get a changed rate (if possible) by either adjusting that clocks
>> rate direction (e.g. a PLL or an adjustable divider) or by propagating
>> __clk_set_rate up the parents (assuming of course that
>> CLK_SET_RATE_PARENT flag is set appropriately).
>>
>> > Also, even when the current clock does not have a set_rate function it
>> > can still change its rate when the CLK_SET_RATE_PARENT is set.
>>
>> Correct. ?I'll clean this up and make the documentation a bit more
>> verbose on when .set_rate/.round_rate/.recalc_rate are mandatory.
>>
>> >
>> >> +
>> >> + ? ? /* NOTE: pre-rate change notifications will stack */
>> >> + ? ? if (clk->notifier_count)
>> >> + ? ? ? ? ? ? ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
>> >> +
>> >> + ? ? if (ret == NOTIFY_BAD)
>> >> + ? ? ? ? ? ? return clk;
>> >> +
>> >> + ? ? /* speculate rate changes down the tree */
>> >> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node) {
>> >> + ? ? ? ? ? ? ret = __clk_speculate_rates(child, new_rate);
>> >> + ? ? ? ? ? ? if (ret == NOTIFY_BAD)
>> >> + ? ? ? ? ? ? ? ? ? ? return clk;
>> >> + ? ? }
>> >> +
>> >> + ? ? /* change the rate of this clk */
>> >> + ? ? if (clk->ops->set_rate)
>> >> + ? ? ? ? ? ? ret = clk->ops->set_rate(clk->hw, new_rate);
>> >
>> > I don't know the reason why you change the child clock before the parent
>> > clock, but it cannot work since this clock will change its rate based on
>> > the old parent rate and not the new one.
>>
>> This depends on the .round_rate implementation, which I admit to
>> having lost some sleep over. ?A clever .round_rate will request the
>> "intermediate" rate for a clock when propagating a request to change
>> the parent rate later on. ?Take for instance the following:
>>
>> pll @ 200MHz (locked)
>> ? ? |
>> parent @ 100MHz (can divide by 1 or 2; currently divider is 2)
>> ? ? |
>> child @ 25MHz (can divide by 2 or 4; currently divider is 4)
>>
>> If we want child to run at 100MHz then the desirable configuration
>> would be to have parent divide-by-1 and child divide-by-2. ?When we
>> call,
>>
>> clk_set_rate(child, 100MHz);
>>
>> Its .round_rate should return 50MHz, and &parent_new_rate should be
>> 200MHz. ?So 50MHz is an "intermediate" rate, but it gets us the
>> divider we want. ?And in fact 50MHz reflects reality because that will
>> be the rate of child until the parent propagation completes and we can
>> adjust parent's dividers. ?(this is one reason why I prefer for
>> pre-rate change notifiers to stack on top of each other).
>>
>> So now that &parent_new_rate is > 0, __clk_set_rate will propagate the
>> request up and parent's .round_rate will simply return 200MHz and
>> leave it's own &parent_new_rate at 0. ?This will change from
>> divide-by-2 to divide-by-1 and from this highest point in the tree we
>> will propagate post-rate change notifiers downstream, as part of the
>> recalc_rate tree walk.
>>
>> I have tested this with OMAP4's CPUfreq driver and I think, while
>> complicated, it is a sound way to approach the problem. ?Maybe the API
>> can be cleaned up, if you have any suggestions.
>
> I cannot see all implications this way will have. All this rate
> propagation is more complex than I thought it would be.

Hi Sascha,

Yes it is very complicated.  The solution I have now (recursive
__clk_set_rate, clever .round_rate which requests parent rate) was not
something I arrived at immediately.

I decided to validate the v6 patches more thoroughly today, based on
your claim that clk_set_rate is broken and here is what I found:

1) clk_set_rate works.  I pulled in the latest OMAP4 CPUfreq code into
my common clk branch and it Just Worked.  This is a dumb
implementation involving no upwards parent propagation, and the clock
changing is of type struct clk_hw_omap (relocking a PLL)

2) while I was at it I verified the rate change notifiers +
clk_set_parent, which also work (I had not touched these since v4 and
wanted to make sure nothing was broken)

Here is where things get interesting.  I tried the same parent rate
propagation via CPUfreq that I had done previously in the v4 series
(http://article.gmane.org/gmane.linux.ports.arm.omap/68225), but this
time it didn't work.  The difference is that back in v4 all of my
clocks in that propagation chain were struct clk_hw_omap, none of them
were any of the basic clock types.  Now in v6, one of the clocks in
the chain is struct clk_divider.  I started looking at the divider's
.round_rate code and for the case where CLK_PARENT_SET_RATE flag is
set the code doesn't make any sense.  I spent some time today trying
to fix struct clk_divider's .round_rate implementation and came to
realize that there might not be a sane default for how such code
should work.  A sane default for the common divider that works
correctly on OMAP may not be what you want on iMX.

To illustrate: if CLK_SET_RATE_PARENT flag is set for my clk_divider
I'd really like to divide by 1 and pass the exact same rate that was
requested for my clk_divider up to the parent.  But the existing
divider code tries to find the largest div for clk_divider and request
a faster rate from the parent (well, I assume this is what it is
supposed to do as the code doesn't quite get this right).

Do you have any ideas on this?  Also, can you verify if this is what
was failing for you, or maybe provide a log if the bug you mentioned
exists elsewhere?  An extreme solution to the problem would be for
clk_divider to not support the CLK_SET_PARENT flag if we cannot agree
on a sane default for this behavior.  I like the idea of the divider
choosing the smallest div possible and requesting the balance from the
parent, but I need feedback from others on that point.  For non-rate
adjustable clocks (clk_gate in particular) it is very easy to continue
supporting this flag as the .round_rate implementation should just be
a "pass through" up to the parent.  In fact this behavior is what some
of my omap clocks are doing and that is why parent propagation for
CPUfreq was working for me back in v4.

> I tried another
> approach on the weekend which basically does not try to do all in a
> single recursion but instead sets the rate in multiple steps:
>
> 1) call a function which calculates all new rates of affected clocks
> ? in a rate change and safes the value in a clk->new_rate field. This
> ? function returns the topmost clock which has to be changed.
> 2) starting from the topmost clock notify all clients. This walks the
> ? whole subtree even if a notfifier refuses the change. If necessary
> ? we can walk the whole subtree again to abort the change.
> 3) actually change rates starting from the topmost clocks and notify
> ? all clients on the way. I changed the set_rate callback to void.
> ? Instead of failing (what is failing in case of set_rate? The clock
> ? will still have some rate) I check for the result with
> ? clk_ops->recalc_rate.

I've considered something like this for "clock groups", especially
when the set of clocks changing are all on the same device and the
permutations are well known ahead of time.  Is this working for you
now?

>
> In the end what's more important than the implementation details is that
> it actually works. I created a little test module which sets up two
> cascaded dividers, tries to change the rate at the output and checks the
> result. ?We might want to add something like this (and maybe similar
> tests for reparenting and other stuff) to the generic clock framework
> later. ?It's good to have something generic to test the framework with
> without depending on some particular SoC.

Agreed about the generic test.  I'm not taking it into the current
series, but we can grow the test cases and submit them later on.

Thanks,
Mike

>
> Sascha
>
> 8<----------------------------------------------------
>
> clk: Add clock test module
>
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
> ?drivers/clk/clk-test.c | ?169 ++++++++++++++++++++++++++++++++++++++++++++++++
> ?1 files changed, 169 insertions(+), 0 deletions(-)
> ?create mode 100644 drivers/clk/clk-test.c
>
> diff --git a/drivers/clk/clk-test.c b/drivers/clk/clk-test.c
> new file mode 100644
> index 0000000..6f901fd
> --- /dev/null
> +++ b/drivers/clk/clk-test.c
> @@ -0,0 +1,169 @@
> +#include <linux/spinlock.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +#include <linux/module.h>
> +
> +/*
> + * We build a fixed rate source clock with two cascaded 2bit dividers:
> + *
> + * f1 -> div1 -> div2
> + *
> + * and try set the rate of div2 from 0Hz to f1 + 1 Hz.
> + *
> + * This makes the following resulting dividers possible:
> + *
> + * 1, 2, 4, 6, 8, 9, 12, 16
> + *
> + * Sometimes there are different results possible due to integer maths.
> + * For example if we have an input frequency of 100Hz and request an
> + * output of 16Hz the best divider values would be 2 and 4 resulting
> + * in a real frequency of 12.5Hz. We also accept 2 and 3 as result
> + * because 100 / (3 * 2) = 16.6667 which is too high, but multiplying
> + * 16 * 3 * 2 results in 96Hz which is lower than 100Hz.
> + *
> + */
> +
> +static unsigned long div1_reg, div2_reg;
> +
> +static struct clk *f1, *div1, *div2;
> +
> +static DEFINE_SPINLOCK(imx_ccm_lock);
> +
> +//#define FIXED_RATE 144
> +#define FIXED_RATE 100
> +
> +static inline struct clk *register_divider(const char *name, const char *parent,
> + ? ? ? ? ? ? ? void __iomem *reg, u8 shift, u8 width)
> +{
> + ? ? ? return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
> + ? ? ? ? ? ? ? ? ? ? ? reg, shift, width, 0, &imx_ccm_lock);
> +}
> +
> +static unsigned long divs[] = {
> + ? ? ? 1, 2, 3, 4, 6, 8, 9, 12, 16,
> +};
> +
> +static int check_rounded_rate(unsigned long want, unsigned long rounded)
> +{
> + ? ? ? int i, j;
> + ? ? ? unsigned long best1 = 0, best2 = 0, now;
> +
> + ? ? ? if (want > FIXED_RATE) {
> + ? ? ? ? ? ? ? best1 = best2 = FIXED_RATE;
> + ? ? ? ? ? ? ? goto found2;
> + ? ? ? }
> +
> + ? ? ? for (i = 1; i <= 4; i++) {
> + ? ? ? ? ? ? ? for (j = 1; j <= 4; j++) {
> + ? ? ? ? ? ? ? ? ? ? ? now = FIXED_RATE / i / j;
> + ? ? ? ? ? ? ? ? ? ? ? if (now <= want && now > best1)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? best1 = now;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (!best1)
> + ? ? ? ? ? ? ? best1 = (FIXED_RATE / 4) / 4;
> +
> + ? ? ? for (i = 0; i < ARRAY_SIZE(divs); i++) {
> + ? ? ? ? ? ? ? if (FIXED_RATE <= want * divs[i]) {
> + ? ? ? ? ? ? ? ? ? ? ? best2 = FIXED_RATE / divs[i];
> + ? ? ? ? ? ? ? ? ? ? ? goto found2;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (!best2)
> + ? ? ? ? ? ? ? best2 = FIXED_RATE / 16;
> +found2:
> + ? ? ? if (rounded != best1 && rounded != best2) {
> + ? ? ? ? ? ? ? if (best1 == best2)
> + ? ? ? ? ? ? ? ? ? ? ? printk("clk-test: wanted rate %ld, best result would be %ld,"
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? " but we have %ld\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? want, best1, rounded);
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? printk("clk-test: wanted rate %ld, best result would be %ld or %ld,"
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? " but we have %ld\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? want, best1, best2, rounded);
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? return 0;
> +}
> +
> +static int check_real_rate(unsigned long rate)
> +{
> + ? ? ? unsigned long realrate1, realrate2;
> +
> + ? ? ? realrate1 = FIXED_RATE / (div1_reg + 1) / (div2_reg + 1);
> + ? ? ? realrate2 = FIXED_RATE / ((div1_reg + 1) * (div2_reg + 1));
> +
> + ? ? ? if (rate != realrate1 && rate != realrate2) {
> + ? ? ? ? ? ? ? if (realrate1 == realrate2)
> + ? ? ? ? ? ? ? ? ? ? ? printk("clk-test: divider returns rate %ld, but instead has %ld\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rate, realrate1);
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? printk("clk-test: divider returns rate %ld, but instead has %ld or %ld\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rate, realrate1, realrate2);
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? return 0;
> +}
> +
> +static int set_rate_test(void)
> +{
> + ? ? ? unsigned long i, rate, rounded;
> + ? ? ? int ret, errors = 0;
> +
> + ? ? ? for (i = 0; i < FIXED_RATE + 1; i++) {
> + ? ? ? ? ? ? ? rounded = clk_round_rate(div2, i);
> + ? ? ? ? ? ? ? ret = check_rounded_rate(i, rounded);
> + ? ? ? ? ? ? ? if (ret)
> + ? ? ? ? ? ? ? ? ? ? ? errors++;
> + ? ? ? ? ? ? ? ret = clk_set_rate(div2, i);
> + ? ? ? ? ? ? ? if (ret) {
> + ? ? ? ? ? ? ? ? ? ? ? printk("%s: setting rate of div2 to %ld failed with %d\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __func__, i, ret);
> + ? ? ? ? ? ? ? ? ? ? ? errors++;
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? rate = clk_get_rate(div2);
> +
> + ? ? ? ? ? ? ? if (rounded != rate) {
> + ? ? ? ? ? ? ? ? ? ? ? printk("clk_test: wanted %ld, core rounded to %ld, have now: %ld\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i, rounded, rate);
> + ? ? ? ? ? ? ? ? ? ? ? errors++;
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? ret = check_real_rate(rate);
> + ? ? ? ? ? ? ? if (ret)
> + ? ? ? ? ? ? ? ? ? ? ? errors++;
> + ? ? ? }
> +
> + ? ? ? return errors;
> +}
> +
> +static int clk_test_init(void)
> +{
> + ? ? ? int errors;
> +
> + ? ? ? f1 = clk_register_fixed_rate(NULL, "f1", NULL, CLK_IS_ROOT, FIXED_RATE);
> + ? ? ? div1 = register_divider("div1", "f1", &div1_reg, 0, 2);
> + ? ? ? div2 = register_divider("div2", "div1", &div2_reg, 0, 2);
> +
> + ? ? ? if (!f1 || !div1 || !div2) {
> + ? ? ? ? ? ? ? printk("clk-test: failed to register clocks\n");
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? errors = set_rate_test();
> +
> + ? ? ? printk("clk-test: finished with %d errors\n", errors);
> +#if 0
> + ? ? ? /* Oh, oh */
> + ? ? ? clk_unregister(f1);
> + ? ? ? clk_unregister(div1);
> + ? ? ? clk_unregister(div2);
> +#endif
> + ? ? ? return -EINVAL;
> +}
> +subsys_initcall(clk_test_init);
> --
> 1.7.9.1
>
>
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |


From grant.likely at secretlab.ca  Mon Mar 12 23:28:32 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 21:28:32 -0600
Subject: [PATCH v3 1/2] mfd: add irq domain support for max8997 interrupts
In-Reply-To: <1330000688-11226-2-git-send-email-thomas.abraham@linaro.org>
References: <1330000688-11226-1-git-send-email-thomas.abraham@linaro.org>
 <1330000688-11226-2-git-send-email-thomas.abraham@linaro.org>
Message-ID: <20120313032832.655983E07E4@localhost>

On Thu, 23 Feb 2012 18:08:07 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> Add irq domain support for max8997 interrupts. The reverse mapping method
> used is linear mapping since the sub-drivers of max8997 such as regulator
> and charger drivers can use the max8997 irq_domain to get the linux irq
> number for max8997 interrupts. All uses of irq_base in platform data and
> max8997 driver private data are removed.
> 
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: MyungJoo Ham <myungjoo.ham at samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> ---
>  arch/arm/mach-exynos/mach-nuri.c    |    4 --
>  arch/arm/mach-exynos/mach-origen.c  |    1 -
>  drivers/mfd/max8997-irq.c           |   60 ++++++++++++++++++++--------------
>  drivers/mfd/max8997.c               |    1 -
>  include/linux/mfd/max8997-private.h |    4 ++-
>  include/linux/mfd/max8997.h         |    1 -
>  6 files changed, 38 insertions(+), 33 deletions(-)

Nice patch.  Nice diffstat too.  Some comments below, but I'm happy with where
this is at.

Acked-by: Grant Likely <grant.likely at secretlab.ca>

> 
> diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
> index a6b9162..1e9ba12 100644
> --- a/arch/arm/mach-exynos/mach-nuri.c
> +++ b/arch/arm/mach-exynos/mach-nuri.c
> @@ -1078,12 +1078,8 @@ static struct platform_device nuri_max8903_device = {
>  static void __init nuri_power_init(void)
>  {
>  	int gpio;
> -	int irq_base = IRQ_GPIO_END + 1;
>  	int ta_en = 0;
>  
> -	nuri_max8997_pdata.irq_base = irq_base;
> -	irq_base += MAX8997_IRQ_NR;
> -
>  	gpio = EXYNOS4_GPX0(7);
>  	gpio_request(gpio, "AP_PMIC_IRQ");
>  	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
> diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
> index 02c242e..328dadb 100644
> --- a/arch/arm/mach-exynos/mach-origen.c
> +++ b/arch/arm/mach-exynos/mach-origen.c
> @@ -424,7 +424,6 @@ static struct max8997_platform_data __initdata origen_max8997_pdata = {
>  	.buck1_gpiodvs	= false,
>  	.buck2_gpiodvs	= false,
>  	.buck5_gpiodvs	= false,
> -	.irq_base	= IRQ_GPIO_END + 1,
>  
>  	.ignore_gpiodvs_side_effect = true,
>  	.buck125_default_idx = 0x0,
> diff --git a/drivers/mfd/max8997-irq.c b/drivers/mfd/max8997-irq.c
> index 09274cf..3d8c9d1 100644
> --- a/drivers/mfd/max8997-irq.c
> +++ b/drivers/mfd/max8997-irq.c
> @@ -142,7 +142,8 @@ static void max8997_irq_sync_unlock(struct irq_data *data)
>  static const inline struct max8997_irq_data *
>  irq_to_max8997_irq(struct max8997_dev *max8997, int irq)
>  {
> -	return &max8997_irqs[irq - max8997->irq_base];
> +	struct irq_data *data = irq_get_irq_data(irq);
> +	return &max8997_irqs[data->hwirq];

Hahaha.  The max8997_irqs table is kind of overdone when the group and mask values
can be arithmetically derived from the hwirq number..

This change is fine, but the driver could use some refactoring.  :-)

>  }
>  
>  static void max8997_irq_mask(struct irq_data *data)
> @@ -182,7 +183,7 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
>  	u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
>  	u8 irq_src;
>  	int ret;
> -	int i;
> +	int i, cur_irq;
>  
>  	ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
>  	if (ret < 0) {
> @@ -269,8 +270,10 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
>  
>  	/* Report */
>  	for (i = 0; i < MAX8997_IRQ_NR; i++) {
> -		if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask)
> -			handle_nested_irq(max8997->irq_base + i);
> +		if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
> +			cur_irq = irq_find_mapping(max8997->irq_domain, i);
> +			handle_nested_irq(cur_irq);
> +		}

Well, if you're using the linear mapping, then only actually allocated irqs will
have a mapping set up.  So the driver could simply do:

	for (i = 0; i < MAX8997_IRQ_NR; i++) {
		cur_irq = irq_find_mapping(max8997->irq_domain, i);
		if (cur_irq)
			handle_nested_irq(cur_irq);
	}

>  	}
>  
>  	return IRQ_HANDLED;
> @@ -278,26 +281,40 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
>  
>  int max8997_irq_resume(struct max8997_dev *max8997)
>  {
> -	if (max8997->irq && max8997->irq_base)
> -		max8997_irq_thread(max8997->irq_base, max8997);
> +	if (max8997->irq && max8997->irq_domain)
> +		max8997_irq_thread(0, max8997);
> +	return 0;
> +}
> +
> +static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
> +					irq_hw_number_t hw)
> +{
> +	struct max8997_dev *max8997 = d->host_data;
> +
> +	irq_set_chip_data(irq, max8997);
> +	irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
> +	irq_set_nested_thread(irq, 1);
> +#ifdef CONFIG_ARM
> +	set_irq_flags(irq, IRQF_VALID);
> +#else
> +	irq_set_noprobe(irq);
> +#endif
>  	return 0;
>  }
>  
> +static struct irq_domain_ops max8997_irq_domain_ops = {
> +	.map = max8997_irq_domain_map,
> +};
> +
>  int max8997_irq_init(struct max8997_dev *max8997)
>  {
> +	struct irq_domain *domain;
>  	int i;
> -	int cur_irq;
>  	int ret;
>  	u8 val;
>  
>  	if (!max8997->irq) {
>  		dev_warn(max8997->dev, "No interrupt specified.\n");
> -		max8997->irq_base = 0;
> -		return 0;
> -	}
> -
> -	if (!max8997->irq_base) {
> -		dev_err(max8997->dev, "No interrupt base specified.\n");
>  		return 0;
>  	}
>  
> @@ -327,18 +344,11 @@ int max8997_irq_init(struct max8997_dev *max8997)
>  					true : false;
>  	}
>  
> -	/* Register with genirq */
> -	for (i = 0; i < MAX8997_IRQ_NR; i++) {
> -		cur_irq = i + max8997->irq_base;
> -		irq_set_chip_data(cur_irq, max8997);
> -		irq_set_chip_and_handler(cur_irq, &max8997_irq_chip,
> -				handle_edge_irq);
> -		irq_set_nested_thread(cur_irq, 1);
> -#ifdef CONFIG_ARM
> -		set_irq_flags(cur_irq, IRQF_VALID);
> -#else
> -		irq_set_noprobe(cur_irq);
> -#endif
> +	domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR,
> +					&max8997_irq_domain_ops, &max8997);
> +	if (!domain) {
> +		dev_err(max8997->dev, "could not create irq domain\n");
> +		return -ENODEV;
>  	}
>  
>  	ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
> diff --git a/drivers/mfd/max8997.c b/drivers/mfd/max8997.c
> index cb83a7a..20ecad3 100644
> --- a/drivers/mfd/max8997.c
> +++ b/drivers/mfd/max8997.c
> @@ -143,7 +143,6 @@ static int max8997_i2c_probe(struct i2c_client *i2c,
>  	if (!pdata)
>  		goto err;
>  
> -	max8997->irq_base = pdata->irq_base;
>  	max8997->ono = pdata->ono;
>  
>  	mutex_init(&max8997->iolock);
> diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
> index 3f4deb6..830152c 100644
> --- a/include/linux/mfd/max8997-private.h
> +++ b/include/linux/mfd/max8997-private.h
> @@ -23,6 +23,8 @@
>  #define __LINUX_MFD_MAX8997_PRIV_H
>  
>  #include <linux/i2c.h>
> +#include <linux/export.h>
> +#include <linux/irqdomain.h>
>  
>  #define MAX8997_REG_INVALID	(0xff)
>  
> @@ -325,7 +327,7 @@ struct max8997_dev {
>  
>  	int irq;
>  	int ono;
> -	int irq_base;
> +	struct irq_domain *irq_domain;
>  	struct mutex irqlock;
>  	int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
>  	int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
> diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
> index fff5905..818486c 100644
> --- a/include/linux/mfd/max8997.h
> +++ b/include/linux/mfd/max8997.h
> @@ -155,7 +155,6 @@ struct max8997_led_platform_data {
>  
>  struct max8997_platform_data {
>  	/* IRQ */
> -	int irq_base;
>  	int ono;
>  	int wakeup;
>  
> -- 
> 1.6.6.rc2
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From plagnioj at jcrosoft.com  Mon Mar 12 23:17:39 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 04:17:39 +0100
Subject: [PATCH 1/1] of: introduce helper to manage boolean
In-Reply-To: <4F5E50DA.6080000@freescale.com>
References: <1328588028-24766-1-git-send-email-plagnioj@jcrosoft.com>
 <20120309014441.8236B3E0903@localhost>
 <20120309100435.GN27213@game.jcrosoft.org>
 <20120309162638.92E813E0880@localhost>
 <20120309163608.GQ27213@game.jcrosoft.org>
 <4F5E50DA.6080000@freescale.com>
Message-ID: <20120313031739.GA18320@game.jcrosoft.org>

On 14:39 Mon 12 Mar     , Scott Wood wrote:
> On 03/09/2012 10:36 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>>> Ugh.  so any value other than 1 returns false?  I think that will surprise
> >>>> most people.
> >>>>
> >>>> I don't like this api or binding.  If it is a bool property, then why isn't
> >>>> simply testing for the property existance sufficient?
> >>> no if you want to disable it
> >>>
> >>> if a bool is define in the dtsi and want to disable it int the dts
> >>>
> >>> if you we can do the the invert
> >>>
> >>> if !0 => true
> >>>
> >>> is-ok;			=> true
> >>> is-ok = <val != 0>;	=> true
> >>> is-ok = <0>;		=> false
> >>
> >> This is a failure of the dtc tool, not the binding.  Accepting this binding
> >> means we have to live with it for a very long time.  It needs to be fixed
> >> in dtc instead so that properties can be deleted instead of only modified.
> > I understand your idea but today if you put and value in the property it's true.
> > 
> > So is-ok = <0>; is true also which is illogical as in any language a boolean is
> > true (1) or false (0). When I read the property I will understand false not true
> 
> You could say similar things about is-ok = "no" or is-ok = "" or is-ok =
> "I'd rather you didn't"... it's expected that violating the binding may
> produce illogical results.
today is most of the binding people use a number whe the want to be able to
delete it and it's the same in most of the promgramming language

Best Regards,
J.


From grant.likely at secretlab.ca  Mon Mar 12 23:43:06 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 21:43:06 -0600
Subject: [PATCH v3 2/2] regulator: add device tree support for max8997
In-Reply-To: <1330000688-11226-3-git-send-email-thomas.abraham@linaro.org>
References: <1330000688-11226-1-git-send-email-thomas.abraham@linaro.org>
 <1330000688-11226-3-git-send-email-thomas.abraham@linaro.org>
Message-ID: <20120313034306.16CF73E07E4@localhost>

On Thu, 23 Feb 2012 18:08:08 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> Add device tree based discovery support for max8997.
> 
> Cc: MyungJoo Ham <myungjoo.ham at samsung.com>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> ---
>  .../devicetree/bindings/regulator/max8997-pmic.txt |  134 +++++++++++++++++++
>  drivers/mfd/max8997.c                              |   72 ++++++++++-
>  drivers/regulator/max8997.c                        |  139 +++++++++++++++++++-
>  include/linux/mfd/max8997.h                        |    1 +
>  4 files changed, 344 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/regulator/max8997-pmic.txt
> 
> diff --git a/Documentation/devicetree/bindings/regulator/max8997-pmic.txt b/Documentation/devicetree/bindings/regulator/max8997-pmic.txt
> new file mode 100644
> index 0000000..d282635
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/regulator/max8997-pmic.txt
> @@ -0,0 +1,134 @@
> +* Maxim MAX8997 Voltage and Current Regulator
> +
> +The Maxim MAX8997 is a multi-function device which includes volatage and
> +current regulators, rtc, charger controller and other sub-blocks. It is
> +interfaced to the host controller using a i2c interface. Each sub-block is
> +addressed by the host system using different i2c slave address. This document
> +describes the bindings for 'pmic' sub-block of max8997.
> +
> +Required properties:
> +- compatible: Should be "maxim,max8997-pmic".
> +- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
> +
> +- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
> +  units for buck1 when changing voltage using gpio dvs. Refer to [1] below
> +  for additional information.
> +
> +- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
> +  units for buck2 when changing voltage using gpio dvs. Refer to [1] below
> +  for additional information.
> +
> +- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
> +  units for buck5 when changing voltage using gpio dvs. Refer to [1] below
> +  for additional information.
> +
> +[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
> +    property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage'
> +    property should specify atleast one voltage level (which would be a
> +    safe operating voltage).
> +
> +    If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
> +    property is specified, then all the eigth voltage values for the
> +    'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified.
> +
> +Optional properties:
> +- interrupt-parent: Specifies the phandle of the interrupt controller to which
> +  the interrupts from max8997 are delivered to.
> +- interrupts: Interrupt specifiers for two interrupt sources.
> +  - First interrupt specifier is for 'irq1' interrupt.
> +  - Second interrupt specifier is for 'alert' interrupt.
> +- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs.
> +- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
> +- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs.
> +
> +Additional properties required if either of the optional properties are used:
> +- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for
> +  multiple bucks, changing the voltage value of one of the bucks may affect
> +  that of another buck, which is the side effect of the change (set_voltage).
> +  Use this property to ignore such side effects and change the voltage.
> +
> +- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from
> +  the possible 8 options selectable by the dvs gpios. The value of this
> +  property should be between 0 and 7. If not specified or if out of range, the
> +  default value of this property is set to 0.
> +
> +- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used
> +  for dvs. The format of the gpio specifier depends in the gpio controller.
> +
> +
> +Regulators: The regulators of max8997 that have to be instantiated should be
> +included in a sub-node named 'regulators'. Regulator nodes included in this
> +sub-node should be of the format as below. Note: The 'n' in LDOn and BUCKn
> +represents the LDO or BUCK number as per the datasheet of max8997.
> +
> +    For LDO's:
> +		LDOn {
> +			standard regulator bindings here
> +		};
> +
> +    For BUCK's:
> +		BUCKn {
> +			standard regulator bindings here
> +		};
> +
> +The bindings inside the regulator nodes use the standard regulator bindings
> +which are documented elsewhere.
> +
> +Example:
> +
> +	max8997_pmic at 66 {
> +		compatible = "maxim,max8997-pmic";
> +		interrupt-parent = <&wakeup_eint>;
> +		reg = <0x66>;
> +		interrupts = <4 0>, <3 0>;
> +
> +		max8997,pmic-buck1-uses-gpio-dvs;
> +		max8997,pmic-buck2-uses-gpio-dvs;
> +		max8997,pmic-buck5-uses-gpio-dvs;
> +
> +		max8997,pmic-ignore-gpiodvs-side-effect;
> +		max8997,pmic-buck125-default-dvs-idx = <0>;
> +
> +		max8997,pmic-buck125-dvs-gpios = <&gpx0 0 1 0 0>, /* SET1 */
> +						 <&gpx0 1 1 0 0>, /* SET2 */
> +						 <&gpx0 2 1 0 0>; /* SET3 */
> +
> +		max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
> +						 <1250000>, <1200000>,
> +						 <1150000>, <1100000>,
> +						 <1000000>, <950000>;
> +
> +		max8997,pmic-buck2-dvs-voltage = <1100000>, <1100000>,
> +				    		 <1100000>, <1100000>,
> +						 <1000000>, <1000000>,
> +						 <1000000>, <1000000>;
> +
> +		max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
> +						 <1200000>, <1200000>,
> +						 <1200000>, <1200000>,
> +						 <1200000>, <1200000>;
> +
> +		regulators {
> +			ldo1_reg: LDO1 {
> +				regulator-name = "VDD_ABB_3.3V";
> +				regulator-min-microvolt = <3300000>;
> +				regulator-max-microvolt = <3300000>;
> +			};
> +
> +			ldo2_reg: LDO2 {
> +				regulator-name = "VDD_ALIVE_1.1V";
> +				regulator-min-microvolt = <1100000>;
> +				regulator-max-microvolt = <1100000>;
> +				regulator-always-on;
> +			};
> +
> +			buck1_reg: BUCK1 {
> +				regulator-name = "VDD_ARM_1.2V";
> +				regulator-min-microvolt = <950000>;
> +				regulator-max-microvolt = <1350000>;
> +				regulator-always-on;
> +				regulator-boot-on;
> +			};
> +		};
> +	};
> +

Good documentation

> diff --git a/drivers/mfd/max8997.c b/drivers/mfd/max8997.c
> index 20ecad3..13180be 100644
> --- a/drivers/mfd/max8997.c
> +++ b/drivers/mfd/max8997.c
> @@ -23,6 +23,7 @@
>  
>  #include <linux/slab.h>
>  #include <linux/i2c.h>
> +#include <linux/of_irq.h>
>  #include <linux/interrupt.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/module.h>
> @@ -123,6 +124,60 @@ int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask)
>  }
>  EXPORT_SYMBOL_GPL(max8997_update_reg);
>  
> +#ifdef CONFIG_OF
> +/*
> + * Only the common platform data elements for max8997 are parsed here from the
> + * device tree. Other sub-modules of max8997 such as pmic, rtc and others have
> + * to parse their own platform data elements from device tree.
> + *
> + * The max8997 platform data structure is instantiated here and the drivers for
> + * the sub-modules need not instantiate another instance while parsing their
> + * platform data.
> + */
> +static int max8997_i2c_parse_dt_pdata(struct device *dev,
> +					struct max8997_platform_data **pdata)
> +{
> +	struct max8997_platform_data *pd;
> +
> +	pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
> +	if (!pd) {
> +		dev_err(dev, "could not allocate memory for pdata\n");
> +		return -ENOMEM;
> +	}
> +
> +	pd->ono = irq_of_parse_and_map(dev->of_node, 1);
> +
> +	/*
> +	 * ToDo: the 'wakeup' member in the platform data is more of a linux
> +	 * specfic information. Hence, there is no binding for that yet and
> +	 * not parsed here.
> +	 */
> +
> +	*pdata = pd;
> +	return 0;
> +}
> +#else
> +static int max8997_i2c_parse_dt_pdata(struct device *dev,
> +					struct max8997_platform_data **pdata)
> +{
> +	return 0;
> +}
> +#endif
> +
> +static struct of_device_id __devinitdata max8997_pmic_dt_match[];

Move the actual definition of this structure up to here so that a forward
declaration becomes unnecessary.

> +static inline int max8997_i2c_get_driver_data(struct i2c_client *i2c,
> +						const struct i2c_device_id *id)
> +{
> +#ifdef CONFIG_OF
> +	if (i2c->dev.of_node) {
> +		const struct of_device_id *match;
> +		match = of_match_node(max8997_pmic_dt_match, i2c->dev.of_node);
> +		return (int)match->data;
> +	}
> +#endif
> +	return (int)id->driver_data;
> +}
> +
>  static int max8997_i2c_probe(struct i2c_client *i2c,
>  			    const struct i2c_device_id *id)
>  {
> @@ -137,9 +192,16 @@ static int max8997_i2c_probe(struct i2c_client *i2c,
>  	i2c_set_clientdata(i2c, max8997);
>  	max8997->dev = &i2c->dev;
>  	max8997->i2c = i2c;
> -	max8997->type = id->driver_data;
> +	max8997->type = max8997_i2c_get_driver_data(i2c, id);
>  	max8997->irq = i2c->irq;
>  
> +	if (max8997->dev->of_node) {
> +		ret = max8997_i2c_parse_dt_pdata(max8997->dev, &pdata);
> +		if (ret)
> +			goto err;
> +		i2c->dev.platform_data = pdata;

This line is illegal.  Drivers must *not* change the value of dev->platform_data.
instead the valid pdata pointer needs to be stored in the max8997 private data
structure.

> +	}
> +

If you tweak the definition of max8997_i2c_parse_dt_pdata() then this block can
be simplified to:

	pdata = max8997_i2c_parse_dt_pdata(max8997->dev, &pdata);
	if (!pdata) 
		pdata = i2c->dev.platform_data,
	if (!pdata)
		goto err;


Otherwise, the patch looks pretty good.  (although seeing the decode function
has got me thinking that we need a much better way of decoding the dt data).

g.

>  
> @@ -429,11 +491,19 @@ const struct dev_pm_ops max8997_pm = {
>  	.restore = max8997_restore,
>  };
>  
> +#ifdef CONFIG_OF
> +static struct of_device_id __devinitdata max8997_pmic_dt_match[] = {
> +	{ .compatible = "maxim,max8997-pmic", .data = TYPE_MAX8997 },
> +	{},
> +};
> +#endif
> +
>  static struct i2c_driver max8997_i2c_driver = {
>  	.driver = {
>  		   .name = "max8997",
>  		   .owner = THIS_MODULE,
>  		   .pm = &max8997_pm,
> +		   .of_match_table = of_match_ptr(max8997_pmic_dt_match),
>  	},
>  	.probe = max8997_i2c_probe,
>  	.remove = max8997_i2c_remove,
> diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
> index bb7cd9d..b31c4c9 100644
> --- a/drivers/regulator/max8997.c
> +++ b/drivers/regulator/max8997.c
> @@ -25,6 +25,7 @@
>  #include <linux/delay.h>
>  #include <linux/err.h>
>  #include <linux/gpio.h>
> +#include <linux/of_gpio.h>
>  #include <linux/slab.h>
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
> @@ -32,6 +33,7 @@
>  #include <linux/regulator/machine.h>
>  #include <linux/mfd/max8997.h>
>  #include <linux/mfd/max8997-private.h>
> +#include <linux/regulator/of_regulator.h>
>  
>  struct max8997_data {
>  	struct device *dev;
> @@ -958,6 +960,134 @@ static struct regulator_desc regulators[] = {
>  	},
>  };
>  
> +#ifdef CONFIG_OF
> +static int max8997_pmic_dt_parse_dvs_gpio(struct max8997_dev *iodev,
> +			struct max8997_platform_data *pdata,
> +			struct device_node *pmic_np)
> +{
> +	int i, gpio;
> +
> +	for (i = 0; i < 3; i++) {
> +		gpio = of_get_named_gpio(pmic_np,
> +					"max8997,pmic-buck125-dvs-gpios", i);
> +		if (!gpio_is_valid(gpio)) {
> +			dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
> +			return -EINVAL;
> +		}
> +		pdata->buck125_gpios[i] = gpio;
> +	}
> +	return 0;
> +}
> +
> +static int max8997_pmic_dt_parse_pdata(struct max8997_dev *iodev,
> +					struct max8997_platform_data *pdata)
> +{
> +	struct device_node *pmic_np, *regulators_np, *reg_np;
> +	struct max8997_regulator_data *rdata;
> +	unsigned int i, dvs_voltage_nr = 1, ret;
> +
> +	pmic_np = iodev->dev->of_node;
> +	if (!pmic_np) {
> +		dev_err(iodev->dev, "could not find pmic sub-node\n");
> +		return -ENODEV;
> +	}
> +
> +	regulators_np = of_find_node_by_name(pmic_np, "regulators");
> +	if (!regulators_np) {
> +		dev_err(iodev->dev, "could not find regulators sub-node\n");
> +		return -EINVAL;
> +	}
> +
> +	/* count the number of regulators to be supported in pmic */
> +	pdata->num_regulators = 0;
> +	for_each_child_of_node(regulators_np, reg_np)
> +		pdata->num_regulators++;
> +
> +	rdata = devm_kzalloc(iodev->dev, sizeof(*rdata) *
> +				pdata->num_regulators, GFP_KERNEL);
> +	if (!rdata) {
> +		dev_err(iodev->dev, "could not allocate memory for "
> +						"regulator data\n");
> +		return -ENOMEM;
> +	}
> +
> +	pdata->regulators = rdata;
> +	for_each_child_of_node(regulators_np, reg_np) {
> +		for (i = 0; i < ARRAY_SIZE(regulators); i++)
> +			if (!of_node_cmp(reg_np->name, regulators[i].name))
> +				break;
> +		rdata->id = i;
> +		rdata->initdata = of_get_regulator_init_data(
> +						iodev->dev, reg_np);
> +		rdata->reg_node = reg_np;
> +		rdata++;
> +	}
> +
> +	if (of_get_property(pmic_np, "max8997,pmic-buck1-uses-gpio-dvs", NULL))
> +		pdata->buck1_gpiodvs = true;
> +
> +	if (of_get_property(pmic_np, "max8997,pmic-buck2-uses-gpio-dvs", NULL))
> +		pdata->buck2_gpiodvs = true;
> +
> +	if (of_get_property(pmic_np, "max8997,pmic-buck5-uses-gpio-dvs", NULL))
> +		pdata->buck5_gpiodvs = true;
> +
> +	if (pdata->buck1_gpiodvs || pdata->buck2_gpiodvs ||
> +						pdata->buck5_gpiodvs) {
> +		ret = max8997_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np);
> +		if (ret)
> +			return -EINVAL;
> +
> +		if (of_property_read_u32(pmic_np,
> +				"max8997,pmic-buck125-default-dvs-idx",
> +				&pdata->buck125_default_idx)) {
> +			pdata->buck125_default_idx = 0;
> +		} else {
> +			if (pdata->buck125_default_idx >= 8) {
> +				pdata->buck125_default_idx = 0;
> +				dev_info(iodev->dev, "invalid value for "
> +				"default dvs index, using 0 instead\n");
> +			}
> +		}
> +
> +		if (of_get_property(pmic_np,
> +			"max8997,pmic-ignore-gpiodvs-side-effect", NULL))
> +			pdata->ignore_gpiodvs_side_effect = true;
> +
> +		dvs_voltage_nr = 8;
> +	}
> +
> +	if (of_property_read_u32_array(pmic_np,
> +				"max8997,pmic-buck1-dvs-voltage",
> +				pdata->buck1_voltage, dvs_voltage_nr)) {
> +		dev_err(iodev->dev, "buck1 voltages not specified\n");
> +		return -EINVAL;
> +	}
> +
> +	if (of_property_read_u32_array(pmic_np,
> +				"max8997,pmic-buck2-dvs-voltage",
> +				pdata->buck2_voltage, dvs_voltage_nr)) {
> +		dev_err(iodev->dev, "buck2 voltages not specified\n");
> +		return -EINVAL;
> +	}
> +
> +	if (of_property_read_u32_array(pmic_np,
> +				"max8997,pmic-buck5-dvs-voltage",
> +				pdata->buck5_voltage, dvs_voltage_nr)) {
> +		dev_err(iodev->dev, "buck5 voltages not specified\n");
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +#else
> +static int max8997_pmic_dt_parse_pdata(struct max8997_dev *iodev,
> +					struct max8997_platform_data *pdata)
> +{
> +	return 0;
> +}
> +#endif /* CONFIG_OF */
> +
>  static __devinit int max8997_pmic_probe(struct platform_device *pdev)
>  {
>  	struct max8997_dev *iodev = dev_get_drvdata(pdev->dev.parent);
> @@ -968,6 +1098,12 @@ static __devinit int max8997_pmic_probe(struct platform_device *pdev)
>  	int i, ret, size;
>  	u8 max_buck1 = 0, max_buck2 = 0, max_buck5 = 0;
>  
> +	if (iodev->dev->of_node) {
> +		ret = max8997_pmic_dt_parse_pdata(iodev, pdata);
> +		if (ret)
> +			return ret;
> +	}
> +
>  	if (!pdata) {
>  		dev_err(pdev->dev.parent, "No platform init data supplied.\n");
>  		return -ENODEV;
> @@ -1146,7 +1282,8 @@ static __devinit int max8997_pmic_probe(struct platform_device *pdev)
>  			regulators[id].n_voltages = 16;
>  
>  		rdev[i] = regulator_register(&regulators[id], max8997->dev,
> -				pdata->regulators[i].initdata, max8997, NULL);
> +				pdata->regulators[i].initdata, max8997,
> +				pdata->regulators[i].reg_node);
>  		if (IS_ERR(rdev[i])) {
>  			ret = PTR_ERR(rdev[i]);
>  			dev_err(max8997->dev, "regulator init failed for %d\n",
> diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
> index 818486c..ba92375 100644
> --- a/include/linux/mfd/max8997.h
> +++ b/include/linux/mfd/max8997.h
> @@ -75,6 +75,7 @@ enum max8998_regulators {
>  struct max8997_regulator_data {
>  	int id;
>  	struct regulator_init_data *initdata;
> +	struct device_node *reg_node;
>  };
>  
>  enum max8997_muic_usb_type {
> -- 
> 1.6.6.rc2
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From matt at genesi-usa.com  Mon Mar 12 23:50:09 2012
From: matt at genesi-usa.com (Matt Sealey)
Date: Mon, 12 Mar 2012 22:50:09 -0500
Subject: [PATCH v6 3/3] clk: basic clock hardware types
In-Reply-To: <1331366064-1273-4-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-4-git-send-email-mturquette@linaro.org>
Message-ID: <CAKGA1b=huAnG6tLoaGqoFoJnuEg-+rs8KLYVB1KF6_q73ot63A@mail.gmail.com>

Hi Mike,

Can I suggest/we discuss that we support fractional (i.e. represented
by fixed point value with integer and fractional part) dividers in the
common divider clock case, simplistically just adding a divider
fractional width and shifting all the calculations by it (and fixing
the "maxdiv" calculation as in a fractional case width of the divider
area in the register is not an indicator of the actual maximum
divider)? (I guess for the standard integer divider case, it would be
continually shifting by 0 which might make the code a bit bigger, I
don't think that would truly be a concern though?)

Is there a particular reason why this case also cannot support set_parent?

I have a use case here (i.MX51/53/6 IPU DI output "pixel" clock) which
could be handled by this code if only those two were solved, it would
save reimplementing the whole thing as a special case. I am at a loss
to think of another particular case in any other SoC where there is a
fractional divider on a clock where it might come in handy, though, I
thought maybe someone could speak up and give an example that would
come in handy for them (I can think of Marvel PXA and OMAP DSS display
units having the exact same need which could be implemented using the
clock API rather than opencoded inside the framebuffer drivers, but
whether anyone actually cares about that is another matter
entirely...)

-- 
Matt Sealey <matt at genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.



On Sat, Mar 10, 2012 at 1:54 AM, Mike Turquette <mturquette at linaro.org> wrote:
> Many platforms support simple gateable clocks, fixed-rate clocks,
> adjustable divider clocks and multi-parent multiplexer clocks.
>
> This patch introduces basic clock types for the above-mentioned hardware
> which share some common characteristics.
>
> Based on original work by Jeremy Kerr and contribution by Jamie Iles.
> Dividers and multiplexor clocks originally contributed by Richard Zhao &
> Sascha Hauer.
>
> Signed-off-by: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Mike Turquette <mturquette at ti.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Shawn Guo <shawn.guo at freescale.com>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Jamie Iles <jamie at jamieiles.com>
> Cc: Richard Zhao <richard.zhao at linaro.org>
> Cc: Saravana Kannan <skannan at codeaurora.org>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Stephen Boyd <sboyd at codeaurora.org>
> Cc: Amit Kucheria <amit.kucheria at linaro.org>
> Cc: Deepak Saxena <dsaxena at linaro.org>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Andrew Lunn <andrew at lunn.ch>
> ---
> Changes since v5:
> ?* standardized the hw-specific locking in the basic clock types
> ?* export the individual ops for each basic clock type
> ?* improve registration for single-parent basic clocks (thanks Sascha)
> ?* fixed bugs in gate clock's static initializers (thanks Andrew)
>
> ?drivers/clk/Makefile ? ? ? ? | ? ?3 +-
> ?drivers/clk/clk-divider.c ? ?| ?204 ++++++++++++++++++++++++++++++++++++++++++
> ?drivers/clk/clk-fixed-rate.c | ? 82 +++++++++++++++++
> ?drivers/clk/clk-gate.c ? ? ? | ?157 ++++++++++++++++++++++++++++++++
> ?drivers/clk/clk-mux.c ? ? ? ?| ?123 +++++++++++++++++++++++++
> ?include/linux/clk-private.h ?| ?124 +++++++++++++++++++++++++
> ?include/linux/clk-provider.h | ?127 ++++++++++++++++++++++++++
> ?7 files changed, 819 insertions(+), 1 deletions(-)
> ?create mode 100644 drivers/clk/clk-divider.c
> ?create mode 100644 drivers/clk/clk-fixed-rate.c
> ?create mode 100644 drivers/clk/clk-gate.c
> ?create mode 100644 drivers/clk/clk-mux.c
>
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index ff362c4..1f736bc 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -1,3 +1,4 @@
>
> ?obj-$(CONFIG_CLKDEV_LOOKUP) ? ?+= clkdev.o
> -obj-$(CONFIG_COMMON_CLK) ? ? ? += clk.o
> +obj-$(CONFIG_COMMON_CLK) ? ? ? += clk.o clk-fixed-rate.o clk-gate.o \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?clk-mux.o clk-divider.o
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> new file mode 100644
> index 0000000..c0c4e0b
> --- /dev/null
> +++ b/drivers/clk/clk-divider.c
> @@ -0,0 +1,204 @@
> +/*
> + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
> + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Adjustable divider clock implementation
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +
> +/*
> + * DOC: basic adjustable divider clock that cannot gate
> + *
> + * Traits of this clock:
> + * prepare - clk_prepare only ensures that parents are prepared
> + * enable - clk_enable only ensures that parents are enabled
> + * rate - rate is adjustable. ?clk->rate = parent->rate / divisor
> + * parent - fixed parent. ?No clk_set_parent support
> + */
> +
> +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
> +
> +static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> + ? ? ? ? ? ? ? unsigned long parent_rate)
> +{
> + ? ? ? struct clk_divider *divider = to_clk_divider(hw);
> + ? ? ? unsigned int div;
> + ? ? ? unsigned long flags = 0;
> +
> + ? ? ? if (divider->lock)
> + ? ? ? ? ? ? ? spin_lock_irqsave(divider->lock, flags);
> +
> + ? ? ? div = readl(divider->reg) >> divider->shift;
> + ? ? ? div &= (1 << divider->width) - 1;
> +
> + ? ? ? if (divider->lock)
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(divider->lock, flags);
> +
> + ? ? ? if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
> + ? ? ? ? ? ? ? div++;
> +
> + ? ? ? return parent_rate / div;
> +}
> +EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
> +
> +static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
> + ? ? ? ? ? ? ? unsigned long *best_parent_rate)
> +{
> + ? ? ? struct clk_divider *divider = to_clk_divider(hw);
> + ? ? ? int i, bestdiv = 0;
> + ? ? ? unsigned long parent_rate, best = 0, now, maxdiv;
> +
> + ? ? ? maxdiv = (1 << divider->width);
> +
> + ? ? ? if (divider->flags & CLK_DIVIDER_ONE_BASED)
> + ? ? ? ? ? ? ? maxdiv--;
> +
> + ? ? ? if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
> + ? ? ? ? ? ? ? parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
> + ? ? ? ? ? ? ? bestdiv = parent_rate / rate;
> + ? ? ? ? ? ? ? bestdiv = bestdiv == 0 ? 1 : bestdiv;
> + ? ? ? ? ? ? ? bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
> + ? ? ? ? ? ? ? goto out;
> + ? ? ? }
> +
> + ? ? ? /*
> + ? ? ? ?* The maximum divider we can use without overflowing
> + ? ? ? ?* unsigned long in rate * i below
> + ? ? ? ?*/
> + ? ? ? maxdiv = min(ULONG_MAX / rate, maxdiv);
> +
> + ? ? ? for (i = 1; i <= maxdiv; i++) {
> + ? ? ? ? ? ? ? int div;
> + ? ? ? ? ? ? ? parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rate * i);
> + ? ? ? ? ? ? ? div = parent_rate / rate;
> + ? ? ? ? ? ? ? div = div > maxdiv ? maxdiv : div;
> + ? ? ? ? ? ? ? div = div < 1 ? 1 : div;
> + ? ? ? ? ? ? ? now = parent_rate / div;
> +
> + ? ? ? ? ? ? ? if (now <= rate && now >= best) {
> + ? ? ? ? ? ? ? ? ? ? ? bestdiv = div;
> + ? ? ? ? ? ? ? ? ? ? ? best = now;
> + ? ? ? ? ? ? ? ? ? ? ? *best_parent_rate = parent_rate;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (!bestdiv) {
> + ? ? ? ? ? ? ? bestdiv = (1 << divider->width);
> + ? ? ? ? ? ? ? parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
> + ? ? ? } else {
> + ? ? ? ? ? ? ? parent_rate = best * bestdiv;
> + ? ? ? }
> +
> +out:
> + ? ? ? if (best_parent_rate)
> + ? ? ? ? ? ? ? *best_parent_rate = parent_rate;
> +
> + ? ? ? return bestdiv;
> +}
> +
> +static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long *prate)
> +{
> + ? ? ? unsigned long best_parent_rate;
> + ? ? ? int div = clk_divider_bestdiv(hw, rate, &best_parent_rate);
> + ? ? ? if (prate) {
> + ? ? ? ? ? ? ? if (best_parent_rate == __clk_get_rate(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __clk_get_parent(hw->clk)))
> + ? ? ? ? ? ? ? ? ? ? ? *prate = 0;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? *prate = best_parent_rate;
> + ? ? ? }
> +
> + ? ? ? return best_parent_rate / div;
> +}
> +EXPORT_SYMBOL_GPL(clk_divider_round_rate);
> +
> +static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
> +{
> + ? ? ? unsigned long best_parent_rate;
> + ? ? ? struct clk_divider *divider = to_clk_divider(hw);
> + ? ? ? unsigned int div;
> + ? ? ? unsigned long flags = 0;
> + ? ? ? u32 val;
> +
> + ? ? ? div = clk_divider_bestdiv(hw, rate, &best_parent_rate);
> +
> + ? ? ? if (divider->lock)
> + ? ? ? ? ? ? ? spin_lock_irqsave(divider->lock, flags);
> +
> + ? ? ? if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
> + ? ? ? ? ? ? ? div--;
> +
> + ? ? ? val = readl(divider->reg);
> + ? ? ? val &= ~(((1 << divider->width) - 1) << divider->shift);
> + ? ? ? val |= div << divider->shift;
> + ? ? ? writel(val, divider->reg);
> +
> + ? ? ? if (divider->lock)
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(divider->lock, flags);
> +
> + ? ? ? return 0;
> +}
> +EXPORT_SYMBOL_GPL(clk_divider_set_rate);
> +
> +struct clk_ops clk_divider_ops = {
> + ? ? ? .recalc_rate = clk_divider_recalc_rate,
> + ? ? ? .round_rate = clk_divider_round_rate,
> + ? ? ? .set_rate = clk_divider_set_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_divider_ops);
> +
> +struct clk *clk_register_divider(struct device *dev, const char *name,
> + ? ? ? ? ? ? ? const char *parent_name, unsigned long flags,
> + ? ? ? ? ? ? ? void __iomem *reg, u8 shift, u8 width,
> + ? ? ? ? ? ? ? u8 clk_divider_flags, spinlock_t *lock)
> +{
> + ? ? ? struct clk_divider *div;
> + ? ? ? struct clk *clk;
> +
> + ? ? ? div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
> +
> + ? ? ? if (!div) {
> + ? ? ? ? ? ? ? pr_err("%s: could not allocate divider clk\n", __func__);
> + ? ? ? ? ? ? ? return NULL;
> + ? ? ? }
> +
> + ? ? ? /* struct clk_divider assignments */
> + ? ? ? div->reg = reg;
> + ? ? ? div->shift = shift;
> + ? ? ? div->width = width;
> + ? ? ? div->flags = clk_divider_flags;
> + ? ? ? div->lock = lock;
> +
> + ? ? ? if (parent_name) {
> + ? ? ? ? ? ? ? div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
> + ? ? ? ? ? ? ? if (!div->parent[0])
> + ? ? ? ? ? ? ? ? ? ? ? goto out;
> + ? ? ? }
> +
> + ? ? ? clk = clk_register(dev, name,
> + ? ? ? ? ? ? ? ? ? ? ? &clk_divider_ops, &div->hw,
> + ? ? ? ? ? ? ? ? ? ? ? div->parent,
> + ? ? ? ? ? ? ? ? ? ? ? (parent_name ? 1 : 0),
> + ? ? ? ? ? ? ? ? ? ? ? flags);
> + ? ? ? if (clk)
> + ? ? ? ? ? ? ? return clk;
> +
> +out:
> + ? ? ? kfree(div->parent[0]);
> + ? ? ? kfree(div);
> +
> + ? ? ? return NULL;
> +}
> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
> new file mode 100644
> index 0000000..90c79fb
> --- /dev/null
> +++ b/drivers/clk/clk-fixed-rate.c
> @@ -0,0 +1,82 @@
> +/*
> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Fixed rate clock implementation
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +
> +/*
> + * DOC: basic fixed-rate clock that cannot gate
> + *
> + * Traits of this clock:
> + * prepare - clk_(un)prepare only ensures parents are prepared
> + * enable - clk_enable only ensures parents are enabled
> + * rate - rate is always a fixed value. ?No clk_set_rate support
> + * parent - fixed parent. ?No clk_set_parent support
> + */
> +
> +#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
> +
> +static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
> + ? ? ? ? ? ? ? unsigned long parent_rate)
> +{
> + ? ? ? return to_clk_fixed_rate(hw)->fixed_rate;
> +}
> +EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate);
> +
> +struct clk_ops clk_fixed_rate_ops = {
> + ? ? ? .recalc_rate = clk_fixed_rate_recalc_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
> +
> +struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> + ? ? ? ? ? ? ? const char *parent_name, unsigned long flags,
> + ? ? ? ? ? ? ? unsigned long fixed_rate)
> +{
> + ? ? ? struct clk_fixed_rate *fixed;
> + ? ? ? char **parent_names = NULL;
> + ? ? ? u8 len;
> +
> + ? ? ? fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
> +
> + ? ? ? if (!fixed) {
> + ? ? ? ? ? ? ? pr_err("%s: could not allocate fixed clk\n", __func__);
> + ? ? ? ? ? ? ? return ERR_PTR(-ENOMEM);
> + ? ? ? }
> +
> + ? ? ? /* struct clk_fixed_rate assignments */
> + ? ? ? fixed->fixed_rate = fixed_rate;
> +
> + ? ? ? if (parent_name) {
> + ? ? ? ? ? ? ? parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
> +
> + ? ? ? ? ? ? ? if (! parent_names)
> + ? ? ? ? ? ? ? ? ? ? ? goto out;
> +
> + ? ? ? ? ? ? ? len = sizeof(char) * strlen(parent_name);
> +
> + ? ? ? ? ? ? ? parent_names[0] = kmalloc(len, GFP_KERNEL);
> +
> + ? ? ? ? ? ? ? if (!parent_names[0])
> + ? ? ? ? ? ? ? ? ? ? ? goto out;
> +
> + ? ? ? ? ? ? ? strncpy(parent_names[0], parent_name, len);
> + ? ? ? }
> +
> +out:
> + ? ? ? return clk_register(dev, name,
> + ? ? ? ? ? ? ? ? ? ? ? &clk_fixed_rate_ops, &fixed->hw,
> + ? ? ? ? ? ? ? ? ? ? ? parent_names,
> + ? ? ? ? ? ? ? ? ? ? ? (parent_name ? 1 : 0),
> + ? ? ? ? ? ? ? ? ? ? ? flags);
> +}
> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> new file mode 100644
> index 0000000..5d50efa
> --- /dev/null
> +++ b/drivers/clk/clk-gate.c
> @@ -0,0 +1,157 @@
> +/*
> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Gated clock implementation
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +
> +/**
> + * DOC: basic gatable clock which can gate and ungate it's ouput
> + *
> + * Traits of this clock:
> + * prepare - clk_(un)prepare only ensures parent is (un)prepared
> + * enable - clk_enable and clk_disable are functional & control gating
> + * rate - inherits rate from parent. ?No clk_set_rate support
> + * parent - fixed parent. ?No clk_set_parent support
> + */
> +
> +#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
> +
> +static void clk_gate_set_bit(struct clk_gate *gate)
> +{
> + ? ? ? u32 reg;
> + ? ? ? unsigned long flags = 0;
> +
> + ? ? ? if (gate->lock)
> + ? ? ? ? ? ? ? spin_lock_irqsave(gate->lock, flags);
> +
> + ? ? ? reg = readl(gate->reg);
> + ? ? ? reg |= BIT(gate->bit_idx);
> + ? ? ? writel(reg, gate->reg);
> +
> + ? ? ? if (gate->lock)
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(gate->lock, flags);
> +}
> +
> +static void clk_gate_clear_bit(struct clk_gate *gate)
> +{
> + ? ? ? u32 reg;
> + ? ? ? unsigned long flags = 0;
> +
> + ? ? ? if (gate->lock)
> + ? ? ? ? ? ? ? spin_lock_irqsave(gate->lock, flags);
> +
> + ? ? ? reg = readl(gate->reg);
> + ? ? ? reg &= ~BIT(gate->bit_idx);
> + ? ? ? writel(reg, gate->reg);
> +
> + ? ? ? if (gate->lock)
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(gate->lock, flags);
> +}
> +
> +static int clk_gate_enable(struct clk_hw *hw)
> +{
> + ? ? ? struct clk_gate *gate = to_clk_gate(hw);
> +
> + ? ? ? if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> + ? ? ? ? ? ? ? clk_gate_clear_bit(gate);
> + ? ? ? else
> + ? ? ? ? ? ? ? clk_gate_set_bit(gate);
> +
> + ? ? ? return 0;
> +}
> +EXPORT_SYMBOL_GPL(clk_gate_enable);
> +
> +static void clk_gate_disable(struct clk_hw *hw)
> +{
> + ? ? ? struct clk_gate *gate = to_clk_gate(hw);
> +
> + ? ? ? if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> + ? ? ? ? ? ? ? clk_gate_set_bit(gate);
> + ? ? ? else
> + ? ? ? ? ? ? ? clk_gate_clear_bit(gate);
> +}
> +EXPORT_SYMBOL_GPL(clk_gate_disable);
> +
> +static int clk_gate_is_enabled(struct clk_hw *hw)
> +{
> + ? ? ? u32 reg;
> + ? ? ? unsigned long flags = 0;
> + ? ? ? struct clk_gate *gate = to_clk_gate(hw);
> +
> + ? ? ? if (gate->lock)
> + ? ? ? ? ? ? ? spin_lock_irqsave(gate->lock, flags);
> +
> + ? ? ? reg = readl(gate->reg);
> +
> + ? ? ? if (gate->lock)
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(gate->lock, flags);
> +
> + ? ? ? /* if a set bit disables this clk, flip it before masking */
> + ? ? ? if (gate->flags & CLK_GATE_SET_TO_DISABLE)
> + ? ? ? ? ? ? ? reg ^= BIT(gate->bit_idx);
> +
> + ? ? ? reg &= BIT(gate->bit_idx);
> +
> + ? ? ? return reg ? 1 : 0;
> +}
> +EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
> +
> +struct clk_ops clk_gate_ops = {
> + ? ? ? .enable = clk_gate_enable,
> + ? ? ? .disable = clk_gate_disable,
> + ? ? ? .is_enabled = clk_gate_is_enabled,
> +};
> +EXPORT_SYMBOL_GPL(clk_gate_ops);
> +
> +struct clk *clk_register_gate(struct device *dev, const char *name,
> + ? ? ? ? ? ? ? const char *parent_name, unsigned long flags,
> + ? ? ? ? ? ? ? void __iomem *reg, u8 bit_idx,
> + ? ? ? ? ? ? ? u8 clk_gate_flags, spinlock_t *lock)
> +{
> + ? ? ? struct clk_gate *gate;
> + ? ? ? struct clk *clk;
> +
> + ? ? ? gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
> +
> + ? ? ? if (!gate) {
> + ? ? ? ? ? ? ? pr_err("%s: could not allocate gated clk\n", __func__);
> + ? ? ? ? ? ? ? return NULL;
> + ? ? ? }
> +
> + ? ? ? /* struct clk_gate assignments */
> + ? ? ? gate->reg = reg;
> + ? ? ? gate->bit_idx = bit_idx;
> + ? ? ? gate->flags = clk_gate_flags;
> + ? ? ? gate->lock = lock;
> +
> + ? ? ? if (parent_name) {
> + ? ? ? ? ? ? ? gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
> + ? ? ? ? ? ? ? if (!gate->parent[0])
> + ? ? ? ? ? ? ? ? ? ? ? goto out;
> + ? ? ? }
> +
> + ? ? ? clk = clk_register(dev, name,
> + ? ? ? ? ? ? ? ? ? ? ? &clk_gate_ops, &gate->hw,
> + ? ? ? ? ? ? ? ? ? ? ? gate->parent,
> + ? ? ? ? ? ? ? ? ? ? ? (parent_name ? 1 : 0),
> + ? ? ? ? ? ? ? ? ? ? ? flags);
> + ? ? ? if (clk)
> + ? ? ? ? ? ? ? return clk;
> +out:
> + ? ? ? kfree(gate->parent[0]);
> + ? ? ? kfree(gate);
> +
> + ? ? ? return NULL;
> +}
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> new file mode 100644
> index 0000000..6fc0878
> --- /dev/null
> +++ b/drivers/clk/clk-mux.c
> @@ -0,0 +1,123 @@
> +/*
> + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
> + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Simple multiplexer clock implementation
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +
> +/*
> + * DOC: basic adjustable multiplexer clock that cannot gate
> + *
> + * Traits of this clock:
> + * prepare - clk_prepare only ensures that parents are prepared
> + * enable - clk_enable only ensures that parents are enabled
> + * rate - rate is only affected by parent switching. ?No clk_set_rate support
> + * parent - parent is adjustable through clk_set_parent
> + */
> +
> +#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
> +
> +static u8 clk_mux_get_parent(struct clk_hw *hw)
> +{
> + ? ? ? struct clk_mux *mux = to_clk_mux(hw);
> + ? ? ? u32 val;
> + ? ? ? unsigned long flags = 0;
> +
> + ? ? ? if (mux->lock)
> + ? ? ? ? ? ? ? spin_lock_irqsave(mux->lock, flags);
> +
> + ? ? ? /*
> + ? ? ? ?* FIXME need a mux-specific flag to determine if val is bitwise or numeric
> + ? ? ? ?* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
> + ? ? ? ?* to 0x7 (index starts at one)
> + ? ? ? ?* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
> + ? ? ? ?* val = 0x4 really means "bit 2, index starts at bit 0"
> + ? ? ? ?*/
> + ? ? ? val = readl(mux->reg) >> mux->shift;
> + ? ? ? val &= (1 << mux->width) - 1;
> +
> + ? ? ? if (mux->lock)
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(mux->lock, flags);
> +
> + ? ? ? if (val && (mux->flags & CLK_MUX_INDEX_BIT))
> + ? ? ? ? ? ? ? val = ffs(val) - 1;
> +
> + ? ? ? if (val && (mux->flags & CLK_MUX_INDEX_ONE))
> + ? ? ? ? ? ? ? val--;
> +
> + ? ? ? if (val >= __clk_get_num_parents(hw->clk))
> + ? ? ? ? ? ? ? return -EINVAL;
> +
> + ? ? ? return val;
> +}
> +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
> +
> +static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> + ? ? ? struct clk_mux *mux = to_clk_mux(hw);
> + ? ? ? u32 val;
> + ? ? ? unsigned long flags = 0;
> +
> + ? ? ? if (mux->flags & CLK_MUX_INDEX_BIT)
> + ? ? ? ? ? ? ? index = (1 << ffs(index));
> +
> + ? ? ? if (mux->flags & CLK_MUX_INDEX_ONE)
> + ? ? ? ? ? ? ? index++;
> +
> + ? ? ? if (mux->lock)
> + ? ? ? ? ? ? ? spin_lock_irqsave(mux->lock, flags);
> +
> + ? ? ? val = readl(mux->reg);
> + ? ? ? val &= ~(((1 << mux->width) - 1) << mux->shift);
> + ? ? ? val |= index << mux->shift;
> + ? ? ? writel(val, mux->reg);
> +
> + ? ? ? if (mux->lock)
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(mux->lock, flags);
> +
> + ? ? ? return 0;
> +}
> +EXPORT_SYMBOL_GPL(clk_mux_set_parent);
> +
> +struct clk_ops clk_mux_ops = {
> + ? ? ? .get_parent = clk_mux_get_parent,
> + ? ? ? .set_parent = clk_mux_set_parent,
> +};
> +EXPORT_SYMBOL_GPL(clk_mux_ops);
> +
> +struct clk *clk_register_mux(struct device *dev, const char *name,
> + ? ? ? ? ? ? ? char **parent_names, u8 num_parents, unsigned long flags,
> + ? ? ? ? ? ? ? void __iomem *reg, u8 shift, u8 width,
> + ? ? ? ? ? ? ? u8 clk_mux_flags, spinlock_t *lock)
> +{
> + ? ? ? struct clk_mux *mux;
> +
> + ? ? ? mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL);
> +
> + ? ? ? if (!mux) {
> + ? ? ? ? ? ? ? pr_err("%s: could not allocate mux clk\n", __func__);
> + ? ? ? ? ? ? ? return ERR_PTR(-ENOMEM);
> + ? ? ? }
> +
> + ? ? ? /* struct clk_mux assignments */
> + ? ? ? mux->reg = reg;
> + ? ? ? mux->shift = shift;
> + ? ? ? mux->width = width;
> + ? ? ? mux->flags = clk_mux_flags;
> + ? ? ? mux->lock = lock;
> +
> + ? ? ? return clk_register(dev, name, &clk_mux_ops, &mux->hw,
> + ? ? ? ? ? ? ? ? ? ? ? parent_names, num_parents, flags);
> +}
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> index 33bf6a7..9d5c4b1 100644
> --- a/include/linux/clk-private.h
> +++ b/include/linux/clk-private.h
> @@ -45,6 +45,130 @@ struct clk {
> ?#endif
> ?};
>
> +/*
> + * DOC: Basic clock implementations common to many platforms
> + *
> + * Each basic clock hardware type is comprised of a structure describing the
> + * clock hardware, implementations of the relevant callbacks in struct clk_ops,
> + * unique flags for that hardware type, a registration function and an
> + * alternative macro for static initialization
> + */
> +
> +extern struct clk_ops clk_fixed_rate_ops;
> +
> +#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _fixed_rate_flags) ? ? ? ? ? ? ?\
> + ? ? ? static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static char *_name##_parent_names[] = {}; ? ? ? ? ? ? ? \
> + ? ? ? static struct clk_fixed_rate _name##_hw = { ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? .clk = &_name, ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .fixed_rate = _rate, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .flags = _fixed_rate_flags, ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .ops = &clk_fixed_rate_ops, ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .parent_names = _name##_parent_names, ? ? ? ? ? \
> + ? ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##_parent_names), ? ? ? \
> + ? ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? };
> +
> +extern struct clk_ops clk_gate_ops;
> +
> +#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, ? ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _flags, _reg, _bit_idx, ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _gate_flags, _lock) ? ? ? ? ? ? \
> + ? ? ? static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static char *_name##_parent_names[] = { ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? _parent_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk *_name##_parents[] = { ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? _parent_ptr, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk_gate _name##_hw = { ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? .clk = &_name, ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .reg = _reg, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .bit_idx = _bit_idx, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .flags = _gate_flags, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .lock = _lock, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .ops = &clk_gate_ops, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .parent_names = _name##_parent_names, ? ? ? ? ? \
> + ? ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##_parent_names), ? ? ? \
> + ? ? ? ? ? ? ? .parents = _name##_parents, ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? };
> +
> +extern struct clk_ops clk_divider_ops;
> +
> +#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, ? \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _flags, _reg, _shift, _width, ? \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _divider_flags, _lock) ? ? ? ? ?\
> + ? ? ? static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static char *_name##_parent_names[] = { ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? _parent_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk *_name##_parents[] = { ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? _parent_ptr, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk_divider _name##_hw = { ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? .clk = &_name, ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .reg = _reg, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .shift = _shift, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .width = _width, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .flags = _divider_flags, ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .lock = _lock, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .ops = &clk_divider_ops, ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .parent_names = _name##_parent_names, ? ? ? ? ? \
> + ? ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_name##_parent_names), ? ? ? \
> + ? ? ? ? ? ? ? .parents = _name##_parents, ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? };
> +
> +extern struct clk_ops clk_mux_ops;
> +
> +#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _reg, _shift, _width, ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _mux_flags, _lock) ? ? ? ? ? ? ?\
> + ? ? ? static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk_mux _name##_hw = { ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? .clk = &_name, ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .reg = _reg, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .shift = _shift, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .width = _width, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .flags = _mux_flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .lock = _lock, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk _name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .name = #_name, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .ops = &clk_mux_ops, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .hw = &_name##_hw.hw, ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .parent_names = _parent_names, ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .num_parents = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? ARRAY_SIZE(_parent_names), ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .parents = _parents, ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? .flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? };
> +
> ?/**
> ?* __clk_init - initialize the data structures in a struct clk
> ?* @dev: ? ? ? device initializing this clk, placeholder for now
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 09dea1f..853d526 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -129,6 +129,133 @@ struct clk_ops {
> ? ? ? ?void ? ? ? ? ? ?(*init)(struct clk_hw *hw);
> ?};
>
> +/*
> + * DOC: Basic clock implementations common to many platforms
> + *
> + * Each basic clock hardware type is comprised of a structure describing the
> + * clock hardware, implementations of the relevant callbacks in struct clk_ops,
> + * unique flags for that hardware type, a registration function and an
> + * alternative macro for static initialization
> + */
> +
> +/**
> + * struct clk_fixed_rate - fixed-rate clock
> + * @hw: ? ? ? ? ? ? ? ?handle between common and hardware-specific interfaces
> + * @fixed_rate: ? ? ? ?constant frequency of clock
> + */
> +struct clk_fixed_rate {
> + ? ? ? struct ? ? ? ? ?clk_hw hw;
> + ? ? ? unsigned long ? fixed_rate;
> + ? ? ? u8 ? ? ? ? ? ? ?flags;
> +};
> +
> +struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> + ? ? ? ? ? ? ? const char *parent_name, unsigned long flags,
> + ? ? ? ? ? ? ? unsigned long fixed_rate);
> +
> +/**
> + * struct clk_gate - gating clock
> + *
> + * @hw: ? ? ? ? ? ? ? ?handle between common and hardware-specific interfaces
> + * @reg: ? ? ? register controlling gate
> + * @bit_idx: ? single bit controlling gate
> + * @flags: ? ? hardware-specific flags
> + * @lock: ? ? ?register lock
> + *
> + * Clock which can gate its output. ?Implements .enable & .disable
> + *
> + * Flags:
> + * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
> + * ? ? enable the clock. ?Setting this flag does the opposite: setting the bit
> + * ? ? disable the clock and clearing it enables the clock
> + */
> +struct clk_gate {
> + ? ? ? struct clk_hw hw;
> + ? ? ? void __iomem ? ?*reg;
> + ? ? ? u8 ? ? ? ? ? ? ?bit_idx;
> + ? ? ? u8 ? ? ? ? ? ? ?flags;
> + ? ? ? spinlock_t ? ? ?*lock;
> + ? ? ? char ? ? ? ? ? ?*parent[1];
> +};
> +
> +#define CLK_GATE_SET_TO_DISABLE ? ? ? ? ? ? ? ?BIT(0)
> +
> +struct clk *clk_register_gate(struct device *dev, const char *name,
> + ? ? ? ? ? ? ? const char *parent_name, unsigned long flags,
> + ? ? ? ? ? ? ? void __iomem *reg, u8 bit_idx,
> + ? ? ? ? ? ? ? u8 clk_gate_flags, spinlock_t *lock);
> +
> +/**
> + * struct clk_divider - adjustable divider clock
> + *
> + * @hw: ? ? ? ? ? ? ? ?handle between common and hardware-specific interfaces
> + * @reg: ? ? ? register containing the divider
> + * @shift: ? ? shift to the divider bit field
> + * @width: ? ? width of the divider bit field
> + * @lock: ? ? ?register lock
> + *
> + * Clock with an adjustable divider affecting its output frequency. ?Implements
> + * .recalc_rate, .set_rate and .round_rate
> + *
> + * Flags:
> + * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
> + * ? ? register plus one. ?If CLK_DIVIDER_ONE_BASED is set then the divider is
> + * ? ? the raw value read from the register, with the value of zero considered
> + * ? ? invalid
> + * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
> + * ? ? the hardware register
> + */
> +struct clk_divider {
> + ? ? ? struct clk_hw ? hw;
> + ? ? ? void __iomem ? ?*reg;
> + ? ? ? u8 ? ? ? ? ? ? ?shift;
> + ? ? ? u8 ? ? ? ? ? ? ?width;
> + ? ? ? u8 ? ? ? ? ? ? ?flags;
> + ? ? ? spinlock_t ? ? ?*lock;
> + ? ? ? char ? ? ? ? ? ?*parent[1];
> +};
> +
> +#define CLK_DIVIDER_ONE_BASED ? ? ? ? ?BIT(0)
> +#define CLK_DIVIDER_POWER_OF_TWO ? ? ? BIT(1)
> +
> +struct clk *clk_register_divider(struct device *dev, const char *name,
> + ? ? ? ? ? ? ? const char *parent_name, unsigned long flags,
> + ? ? ? ? ? ? ? void __iomem *reg, u8 shift, u8 width,
> + ? ? ? ? ? ? ? u8 clk_divider_flags, spinlock_t *lock);
> +
> +/**
> + * struct clk_mux - multiplexer clock
> + *
> + * @hw: ? ? ? ? ? ? ? ?handle between common and hardware-specific interfaces
> + * @reg: ? ? ? register controlling multiplexer
> + * @shift: ? ? shift to multiplexer bit field
> + * @width: ? ? width of mutliplexer bit field
> + * @num_clks: ?number of parent clocks
> + * @lock: ? ? ?register lock
> + *
> + * Clock with multiple selectable parents. ?Implements .get_parent, .set_parent
> + * and .recalc_rate
> + *
> + * Flags:
> + * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
> + * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two)
> + */
> +struct clk_mux {
> + ? ? ? struct clk_hw ? hw;
> + ? ? ? void __iomem ? ?*reg;
> + ? ? ? u8 ? ? ? ? ? ? ?shift;
> + ? ? ? u8 ? ? ? ? ? ? ?width;
> + ? ? ? u8 ? ? ? ? ? ? ?flags;
> + ? ? ? spinlock_t ? ? ?*lock;
> +};
> +
> +#define CLK_MUX_INDEX_ONE ? ? ? ? ? ? ?BIT(0)
> +#define CLK_MUX_INDEX_BIT ? ? ? ? ? ? ?BIT(1)
> +
> +struct clk *clk_register_mux(struct device *dev, const char *name,
> + ? ? ? ? ? ? ? char **parent_names, u8 num_parents, unsigned long flags,
> + ? ? ? ? ? ? ? void __iomem *reg, u8 shift, u8 width,
> + ? ? ? ? ? ? ? u8 clk_mux_flags, spinlock_t *lock);
>
> ?/**
> ?* clk_register - allocate a new clock, register it and return an opaque cookie
> --
> 1.7.5.4
>
>
> _______________________________________________
> linaro-dev mailing list
> linaro-dev at lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-dev

From grant.likely at secretlab.ca  Mon Mar 12 23:52:46 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 21:52:46 -0600
Subject: [PATCH v4 2/2] ARM: Exynos: Add device tree support for interrupt
 combiner
In-Reply-To: <1329798806-32482-3-git-send-email-thomas.abraham@linaro.org>
References: <1329798806-32482-1-git-send-email-thomas.abraham@linaro.org>
 <1329798806-32482-3-git-send-email-thomas.abraham@linaro.org>
Message-ID: <20120313035246.6BC8A3E07E4@localhost>

On Tue, 21 Feb 2012 10:03:26 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> Add device tree based instantiation of the interrupt combiner controller.
> 
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> ---
> @@ -406,13 +432,33 @@ void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
>  
>  	for (i = 0; i < MAX_COMBINER_NR; i++) {
>  		combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
> -		combiner_cascade_irq(i, IRQ_SPI(i));
> +#ifdef CONFIG_OF
> +		irq = np ? irq_of_parse_and_map(np, i) : IRQ_SPI(i);
> +#else
> +		irq = IRQ_SPI(i);
> +#endif

Hmmm, the #ifdef is rather ugly.  I'd rather have an empty
irq_of_parse_and_map() that always returns 0.

The patch series is fine, and you can add my acked-by, but please send
a follow-up patch to clean it up.

Acked-by: Grant Likely <grant.likely at secretlab.ca>



From grant.likely at secretlab.ca  Mon Mar 12 23:57:28 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 21:57:28 -0600
Subject: [PATCH v3 00/13] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <87vcm9v4h1.fsf@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <878vj5y7iv.fsf@ti.com>
 <CAC83Zv+8AjCHBOJbtvSQS-URvCE5Xm9oPk9_X7h4Kz7FZ_7Otw@mail.gmail.com>
 <CAC83ZvJKS34Py6vVtk_Si9q3A-9CVN6v4ixNM+HJ37AATcGNPA@mail.gmail.com>
 <CAC83ZvJDfDBcRU1isYaxRe-fWN8F2+QW6W5EeWWuTRcFBGpYNg@mail.gmail.com>
 <87vcm9v4h1.fsf@ti.com>
Message-ID: <20120313035728.B56993E0FAA@localhost>

On Mon, 12 Mar 2012 15:28:42 -0700, Kevin Hilman <khilman at ti.com> wrote:
> "DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:
> 
> [...]
> 
> >>> Oops... I am sorry.
> >>> I was in the process of updating the branch with latest comments after
> >>> base-lining on Grant's:
> >>> git://git.secretlab.ca/git/linux-2.6.git
> >>> Branch: gpio/next
> >>> Because this has all the gpio changes including Benoit's latest gpio
> >>> devicetree changes.
> >>> Should I go ahead?
> >> Anyways, for the time being I am updating on top of your changes as before.
> >> You should be able to see the branch shortly.
> > Please note that the branch has your following patch:
> > gpio/omap: fix wakeups on level-triggered GPIOs
> 
> Please be sure to Cc the GPIO maintainer (added now.)
> 
> Grant can we consider your gpio/next a stable baseline for further
> GPIO fixes?
> 
> If so, Tarun, please base your branch there.  Otherwise, continue to use
> my for_3.4/gpio/runtime-pm-cleanup, but please test it by merging with
> the gpio/next branch.

I'm not going to rebase gpio/next before the merge window; you can base on it with
confidence.

g.



From grant.likely at secretlab.ca  Tue Mar 13 00:16:52 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 12 Mar 2012 22:16:52 -0600
Subject: [PATCH 1/1] of: introduce helper to manage boolean
In-Reply-To: <20120313031739.GA18320@game.jcrosoft.org>
References: <1328588028-24766-1-git-send-email-plagnioj@jcrosoft.com>
 <20120309014441.8236B3E0903@localhost>
 <20120309100435.GN27213@game.jcrosoft.org>
 <20120309162638.92E813E0880@localhost>
 <20120309163608.GQ27213@game.jcrosoft.org> <4F5E50DA.6080000@freescale.com>
 <20120313031739.GA18320@game.jcrosoft.org>
Message-ID: <20120313041652.563B63E0536@localhost>

On Tue, 13 Mar 2012 04:17:39 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> On 14:39 Mon 12 Mar     , Scott Wood wrote:
> > On 03/09/2012 10:36 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > >>>> Ugh.  so any value other than 1 returns false?  I think that will surprise
> > >>>> most people.
> > >>>>
> > >>>> I don't like this api or binding.  If it is a bool property, then why isn't
> > >>>> simply testing for the property existance sufficient?
> > >>> no if you want to disable it
> > >>>
> > >>> if a bool is define in the dtsi and want to disable it int the dts
> > >>>
> > >>> if you we can do the the invert
> > >>>
> > >>> if !0 => true
> > >>>
> > >>> is-ok;			=> true
> > >>> is-ok = <val != 0>;	=> true
> > >>> is-ok = <0>;		=> false
> > >>
> > >> This is a failure of the dtc tool, not the binding.  Accepting this binding
> > >> means we have to live with it for a very long time.  It needs to be fixed
> > >> in dtc instead so that properties can be deleted instead of only modified.
> > > I understand your idea but today if you put and value in the property it's true.
> > > 
> > > So is-ok = <0>; is true also which is illogical as in any language a boolean is
> > > true (1) or false (0). When I read the property I will understand false not true
> > 
> > You could say similar things about is-ok = "no" or is-ok = "" or is-ok =
> > "I'd rather you didn't"... it's expected that violating the binding may
> > produce illogical results.
> today is most of the binding people use a number whe the want to be able to
> delete it and it's the same in most of the promgramming language

It isn't yet a big pain point, so there isn't time pressure here.  Fixing the tool
is the better solution, and since the kernel carries a copy of the tool we don't
need to worry about adding a feature that isn't available by the dtc packaged by
a distribution.

Fixing the tool is the correct thing to do.

g.



From sachin.kamat at linaro.org  Tue Mar 13 00:33:44 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Tue, 13 Mar 2012 10:03:44 +0530
Subject: [PATCH 2/3] ARM: Exynos: Add DRM core device support for
 Universal C210 board
In-Reply-To: <1331291105-18152-3-git-send-email-m.szyprowski@samsung.com>
References: <1331291105-18152-1-git-send-email-m.szyprowski@samsung.com>
 <1331291105-18152-3-git-send-email-m.szyprowski@samsung.com>
Message-ID: <CAK9yfHyHoDucPwvZbb_ireRTohkd9hCDf3ER_yp3Rv_7BmNwhg@mail.gmail.com>

Hi Marek,
Thanks for the patch.

On 09/03/2012, Marek Szyprowski <m.szyprowski at samsung.com> wrote:
> Add core DRM device and alternative platform device data for FIMD DRM
> subdriver. Based on the initial patch by Joonyoung Shim
> <jy0922.shim at samsung.com>
>
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-exynos/Kconfig               |    1 +
>  arch/arm/mach-exynos/mach-universal_c210.c |   31
> ++++++++++++++++++++++++++++
>  2 files changed, 32 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 5a26944..c73eeba 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -257,6 +257,7 @@ config MACH_UNIVERSAL_C210
>  	select S5P_DEV_ONENAND
>  	select S5P_DEV_TV
>  	select EXYNOS4_DEV_DMA
> +	select EXYNOS_DEV_DRM
>  	select EXYNOS4_SETUP_FIMD0
>  	select EXYNOS4_SETUP_I2C1
>  	select EXYNOS4_SETUP_I2C3
> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c
> b/arch/arm/mach-exynos/mach-universal_c210.c
> index 322b272..30a3ff3 100644
> --- a/arch/arm/mach-exynos/mach-universal_c210.c
> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
> @@ -23,6 +23,7 @@
>  #include <linux/i2c-gpio.h>
>  #include <linux/i2c/mcs.h>
>  #include <linux/i2c/atmel_mxt_ts.h>
> +#include <drm/exynos_drm.h>
>
>  #include <asm/mach/arch.h>
>  #include <asm/hardware/gic.h>
> @@ -811,6 +812,27 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
>  	/* Gyro, To be updated */
>  };
>
> +#ifdef CONFIG_DRM_EXYNOS
> +static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
> +	.timing	= {
> +		.left_margin	= 16,
> +		.right_margin	= 16,
> +		.upper_margin	= 2,
> +		.lower_margin	= 28,
> +		.hsync_len	= 2,
> +		.vsync_len	= 1,
> +		.xres		= 480,
> +		.yres		= 800,
> +		.refresh	= 55,
> +	},

Shouldn't this be:
               .panel = {
                      .timing	= {
		                .left_margin	= 16,
                        	.right_margin	= 16,
                                .upper_margin	= 2,
                        	.lower_margin	= 28,
                		.hsync_len	= 2,
                          	.vsync_len	= 1,
                 		.xres		= 480,
                                .yres		= 800,
                        	.refresh	= 55,
                         },
                 },
	

> +	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
> +			  VIDCON0_CLKSEL_LCD,
> +	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
> +			  | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> +	.default_win	= 3,
> +	.bpp		= 32,
> +};
> +#else
>  /* Frame Buffer */
>  static struct s3c_fb_pd_win universal_fb_win0 = {
>  	.win_mode = {
> @@ -838,6 +860,7 @@ static struct s3c_fb_platdata universal_lcd_pdata
> __initdata = {
>  			  | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>  	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
>  };
> +#endif
>
>  static struct regulator_consumer_supply cam_vt_dio_supply =
>  	REGULATOR_SUPPLY("vdd_core", "0-003c");
> @@ -1046,6 +1069,9 @@ static struct platform_device *universal_devices[]
> __initdata = {
>  	&universal_gpio_keys,
>  	&s5p_device_onenand,
>  	&s5p_device_fimd0,
> +#ifdef CONFIG_DRM_EXYNOS
> +	&exynos_device_drm,
> +#endif
>  	&s5p_device_mfc,
>  	&s5p_device_mfc_l,
>  	&s5p_device_mfc_r,
> @@ -1091,7 +1117,12 @@ static void __init universal_machine_init(void)
>  	s5p_i2c_hdmiphy_set_platdata(NULL);
>  	i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
>
> +#ifdef CONFIG_DRM_EXYNOS
> +	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
> +	exynos4_fimd0_gpio_setup_24bpp();
> +#else
>  	s5p_fimd0_set_platdata(&universal_lcd_pdata);
> +#endif
>
>  	universal_touchkey_init();
>  	i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
> --
> 1.7.1.569.g6f426
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


-- 
With warm regards,
Sachin


From tarun.kanti at ti.com  Tue Mar 13 00:35:41 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Tue, 13 Mar 2012 10:05:41 +0530
Subject: [PATCH v3 00/13] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <20120313035728.B56993E0FAA@localhost>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <878vj5y7iv.fsf@ti.com>
 <CAC83Zv+8AjCHBOJbtvSQS-URvCE5Xm9oPk9_X7h4Kz7FZ_7Otw@mail.gmail.com>
 <CAC83ZvJKS34Py6vVtk_Si9q3A-9CVN6v4ixNM+HJ37AATcGNPA@mail.gmail.com>
 <CAC83ZvJDfDBcRU1isYaxRe-fWN8F2+QW6W5EeWWuTRcFBGpYNg@mail.gmail.com>
 <87vcm9v4h1.fsf@ti.com> <20120313035728.B56993E0FAA@localhost>
Message-ID: <CAC83ZvJUpoEhfmMRSNWrObEd8x5JR0hHc40ucU1pqT8zn9PbGw@mail.gmail.com>

On Tue, Mar 13, 2012 at 9:27 AM, Grant Likely <grant.likely at secretlab.ca> wrote:
> On Mon, 12 Mar 2012 15:28:42 -0700, Kevin Hilman <khilman at ti.com> wrote:
>> "DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:
>>
>> [...]
>>
>> >>> Oops... I am sorry.
>> >>> I was in the process of updating the branch with latest comments after
>> >>> base-lining on Grant's:
>> >>> git://git.secretlab.ca/git/linux-2.6.git
>> >>> Branch: gpio/next
>> >>> Because this has all the gpio changes including Benoit's latest gpio
>> >>> devicetree changes.
>> >>> Should I go ahead?
>> >> Anyways, for the time being I am updating on top of your changes as before.
>> >> You should be able to see the branch shortly.
>> > Please note that the branch has your following patch:
>> > gpio/omap: fix wakeups on level-triggered GPIOs
>>
>> Please be sure to Cc the GPIO maintainer (added now.)
Sure.

>>
>> Grant can we consider your gpio/next a stable baseline for further
>> GPIO fixes?
>>
>> If so, Tarun, please base your branch there. ?Otherwise, continue to use
>> my for_3.4/gpio/runtime-pm-cleanup, but please test it by merging with
>> the gpio/next branch.
>
> I'm not going to rebase gpio/next before the merge window; you can base on it with
> confidence.
I will base and start doing the tests.
In the mean time I will wait for Kevin's comments on the series.
Thanks.
--
Tarun

>
> g.
>


From sachin.kamat at linaro.org  Tue Mar 13 00:35:46 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Tue, 13 Mar 2012 10:05:46 +0530
Subject: [PATCH 3/3] ARM: Exynos: Add DRM core support for NURI board
In-Reply-To: <1331291105-18152-4-git-send-email-m.szyprowski@samsung.com>
References: <1331291105-18152-1-git-send-email-m.szyprowski@samsung.com>
 <1331291105-18152-4-git-send-email-m.szyprowski@samsung.com>
Message-ID: <CAK9yfHznrJeBWmA167tfBbxawEmPypsjhQ56c9=ppiCXLC9ZNQ@mail.gmail.com>

Hi Marek,

On 09/03/2012, Marek Szyprowski <m.szyprowski at samsung.com> wrote:
> Add core DRM device and alternative platform device data for FIMD DRM
> subdriver. Based on the initial patch by Joonyoung Shim
> <jy0922.shim at samsung.com>
>
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-exynos/Kconfig     |    1 +
>  arch/arm/mach-exynos/mach-nuri.c |   31 +++++++++++++++++++++++++++++++
>  2 files changed, 32 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index c73eeba..e996b5d 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -293,6 +293,7 @@ config MACH_NURI
>  	select S5P_DEV_USB_EHCI
>  	select S5P_SETUP_MIPIPHY
>  	select EXYNOS4_DEV_DMA
> +	select EXYNOS_DEV_DRM
>  	select EXYNOS4_SETUP_FIMC
>  	select EXYNOS4_SETUP_FIMD0
>  	select EXYNOS4_SETUP_I2C1
> diff --git a/arch/arm/mach-exynos/mach-nuri.c
> b/arch/arm/mach-exynos/mach-nuri.c
> index a6b9162..682203a 100644
> --- a/arch/arm/mach-exynos/mach-nuri.c
> +++ b/arch/arm/mach-exynos/mach-nuri.c
> @@ -25,6 +25,7 @@
>  #include <linux/mmc/host.h>
>  #include <linux/fb.h>
>  #include <linux/pwm_backlight.h>
> +#include <drm/exynos_drm.h>
>
>  #include <video/platform_lcd.h>
>  #include <media/m5mols.h>
> @@ -210,6 +211,27 @@ static struct platform_device nuri_gpio_keys = {
>  	},
>  };
>
> +#ifdef CONFIG_DRM_EXYNOS
> +static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
> +	.timing	= {
> +		.xres		= 1024,
> +		.yres		= 600,
> +		.hsync_len	= 40,
> +		.left_margin	= 79,
> +		.right_margin	= 200,
> +		.vsync_len	= 10,
> +		.upper_margin	= 10,
> +		.lower_margin	= 11,
> +		.refresh	= 60,
> +	},

Same comment as given for the previous patch [2/3] in this series.

> +	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
> +			  VIDCON0_CLKSEL_LCD,
> +	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> +	.default_win	= 3,
> +	.bpp		= 32,
> +};
> +
> +#else
>  /* Frame Buffer */
>  static struct s3c_fb_pd_win nuri_fb_win0 = {
>  	.win_mode = {
> @@ -236,6 +258,7 @@ static struct s3c_fb_platdata nuri_fb_pdata __initdata =
> {
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>  	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
>  };
> +#endif
>
>  static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
>  {
> @@ -1335,6 +1358,9 @@ static struct platform_device *nuri_devices[]
> __initdata = {
>  	&cam_vt_cam15_fixed_rdev,
>  	&cam_vdda_fixed_rdev,
>  	&cam_8m_12v_fixed_rdev,
> +#ifdef CONFIG_DRM_EXYNOS
> +	&exynos_device_drm,
> +#endif
>  };
>
>  static void __init nuri_map_io(void)
> @@ -1366,7 +1392,12 @@ static void __init nuri_machine_init(void)
>  	i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
>  	s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
>
> +#ifdef CONFIG_DRM_EXYNOS
> +	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
> +	exynos4_fimd0_gpio_setup_24bpp();
> +#else
>  	s5p_fimd0_set_platdata(&nuri_fb_pdata);
> +#endif
>
>  	nuri_camera_init();
>
> --
> 1.7.1.569.g6f426
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


-- 
With warm regards,
Sachin


From kyungmin.park at samsung.com  Tue Mar 13 00:38:49 2012
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Tue, 13 Mar 2012 13:38:49 +0900
Subject: [PATCH 2/3] ARM: Exynos: Add DRM core device support for
 Universal C210 board
In-Reply-To: <CAK9yfHyHoDucPwvZbb_ireRTohkd9hCDf3ER_yp3Rv_7BmNwhg@mail.gmail.com>
References: <1331291105-18152-1-git-send-email-m.szyprowski@samsung.com>
 <1331291105-18152-3-git-send-email-m.szyprowski@samsung.com>
 <CAK9yfHyHoDucPwvZbb_ireRTohkd9hCDf3ER_yp3Rv_7BmNwhg@mail.gmail.com>
Message-ID: <CAH9JG2UWE1CNOrHVtMawS9TrPHHZrgpbVwvgmXb4OiLObnxdsA@mail.gmail.com>

On 3/13/12, Sachin Kamat <sachin.kamat at linaro.org> wrote:
> Hi Marek,
> Thanks for the patch.
>
> On 09/03/2012, Marek Szyprowski <m.szyprowski at samsung.com> wrote:
>> Add core DRM device and alternative platform device data for FIMD DRM
>> subdriver. Based on the initial patch by Joonyoung Shim
>> <jy0922.shim at samsung.com>
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> ---
>>  arch/arm/mach-exynos/Kconfig               |    1 +
>>  arch/arm/mach-exynos/mach-universal_c210.c |   31
>> ++++++++++++++++++++++++++++
>>  2 files changed, 32 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index 5a26944..c73eeba 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -257,6 +257,7 @@ config MACH_UNIVERSAL_C210
>>  	select S5P_DEV_ONENAND
>>  	select S5P_DEV_TV
>>  	select EXYNOS4_DEV_DMA
>> +	select EXYNOS_DEV_DRM
>>  	select EXYNOS4_SETUP_FIMD0
>>  	select EXYNOS4_SETUP_I2C1
>>  	select EXYNOS4_SETUP_I2C3
>> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c
>> b/arch/arm/mach-exynos/mach-universal_c210.c
>> index 322b272..30a3ff3 100644
>> --- a/arch/arm/mach-exynos/mach-universal_c210.c
>> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
>> @@ -23,6 +23,7 @@
>>  #include <linux/i2c-gpio.h>
>>  #include <linux/i2c/mcs.h>
>>  #include <linux/i2c/atmel_mxt_ts.h>
>> +#include <drm/exynos_drm.h>
>>
>>  #include <asm/mach/arch.h>
>>  #include <asm/hardware/gic.h>
>> @@ -811,6 +812,27 @@ static struct i2c_board_info i2c1_devs[] __initdata =
>> {
>>  	/* Gyro, To be updated */
>>  };
>>
>> +#ifdef CONFIG_DRM_EXYNOS
>> +static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
>> +	.timing	= {
>> +		.left_margin	= 16,
>> +		.right_margin	= 16,
>> +		.upper_margin	= 2,
>> +		.lower_margin	= 28,
>> +		.hsync_len	= 2,
>> +		.vsync_len	= 1,
>> +		.xres		= 480,
>> +		.yres		= 800,
>> +		.refresh	= 55,
>> +	},
>
> Shouldn't this be:
Right, recently we added the panel information. It should be drm-next soon.

Thank you,
Kyungmin Park
>                .panel = {
>                       .timing	= {
> 		                .left_margin	= 16,
>                         	.right_margin	= 16,
>                                 .upper_margin	= 2,
>                         	.lower_margin	= 28,
>                 		.hsync_len	= 2,
>                           	.vsync_len	= 1,
>                  		.xres		= 480,
>                                 .yres		= 800,
>                         	.refresh	= 55,
>                          },
>                  },
> 	
>
>> +	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
>> +			  VIDCON0_CLKSEL_LCD,
>> +	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
>> +			  | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>> +	.default_win	= 3,
>> +	.bpp		= 32,
>> +};
>> +#else
>>  /* Frame Buffer */
>>  static struct s3c_fb_pd_win universal_fb_win0 = {
>>  	.win_mode = {
>> @@ -838,6 +860,7 @@ static struct s3c_fb_platdata universal_lcd_pdata
>> __initdata = {
>>  			  | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>>  	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
>>  };
>> +#endif
>>
>>  static struct regulator_consumer_supply cam_vt_dio_supply =
>>  	REGULATOR_SUPPLY("vdd_core", "0-003c");
>> @@ -1046,6 +1069,9 @@ static struct platform_device *universal_devices[]
>> __initdata = {
>>  	&universal_gpio_keys,
>>  	&s5p_device_onenand,
>>  	&s5p_device_fimd0,
>> +#ifdef CONFIG_DRM_EXYNOS
>> +	&exynos_device_drm,
>> +#endif
>>  	&s5p_device_mfc,
>>  	&s5p_device_mfc_l,
>>  	&s5p_device_mfc_r,
>> @@ -1091,7 +1117,12 @@ static void __init universal_machine_init(void)
>>  	s5p_i2c_hdmiphy_set_platdata(NULL);
>>  	i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
>>
>> +#ifdef CONFIG_DRM_EXYNOS
>> +	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
>> +	exynos4_fimd0_gpio_setup_24bpp();
>> +#else
>>  	s5p_fimd0_set_platdata(&universal_lcd_pdata);
>> +#endif
>>
>>  	universal_touchkey_init();
>>  	i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
>> --
>> 1.7.1.569.g6f426
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe
>> linux-samsung-soc"
>> in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>
>
> --
> With warm regards,
> Sachin
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


From viresh.kumar at st.com  Tue Mar 13 00:42:19 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Tue, 13 Mar 2012 10:12:19 +0530
Subject: [PATCH] MAINTAINERS: Update ST's Mailing list for SPEAr
Message-ID: <ed5b5fcb0dc149e7541d03e1bf13d28fd2bc4ade.1331613701.git.viresh.kumar@st.com>

We have created a ST's Mailing list for SPEAr. This can be accessed from non-st
email ids. I want people to cc this list, when they have changes specific to
SPEAr. So, its better to get this updated in MAINTAINERS file.

Over that, linux-arm-kernel at lists.infradead.org is also added for SPEAr

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 MAINTAINERS |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a1fa89b..93d6780 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5884,6 +5884,7 @@ F:	drivers/mmc/host/sdhci-s3c.c
 
 SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) ST SPEAR DRIVER
 M:	Viresh Kumar <viresh.kumar at st.com>
+L:	spear-devel at list.st.com
 L:	linux-mmc at vger.kernel.org
 S:	Maintained
 F:	drivers/mmc/host/sdhci-spear.c
@@ -6226,24 +6227,32 @@ F:	drivers/tty/serial/sunzilog.h
 
 SPEAR PLATFORM SUPPORT
 M:	Viresh Kumar <viresh.kumar at st.com>
+L:	spear-devel at list.st.com
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 W:	http://www.st.com/spear
 S:	Maintained
 F:	arch/arm/plat-spear/
 
 SPEAR3XX MACHINE SUPPORT
 M:	Viresh Kumar <viresh.kumar at st.com>
+L:	spear-devel at list.st.com
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 W:	http://www.st.com/spear
 S:	Maintained
 F:	arch/arm/mach-spear3xx/
 
 SPEAR6XX MACHINE SUPPORT
 M:	Rajeev Kumar <rajeev-dlh.kumar at st.com>
+L:	spear-devel at list.st.com
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 W:	http://www.st.com/spear
 S:	Maintained
 F:	arch/arm/mach-spear6xx/
 
 SPEAR CLOCK FRAMEWORK SUPPORT
 M:	Viresh Kumar <viresh.kumar at st.com>
+L:	spear-devel at list.st.com
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 W:	http://www.st.com/spear
 S:	Maintained
 F:	arch/arm/mach-spear*/clock.c
@@ -6252,6 +6261,8 @@ F:	arch/arm/plat-spear/include/plat/clock.h
 
 SPEAR PAD MULTIPLEXING SUPPORT
 M:	Viresh Kumar <viresh.kumar at st.com>
+L:	spear-devel at list.st.com
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 W:	http://www.st.com/spear
 S:	Maintained
 F:	arch/arm/plat-spear/include/plat/padmux.h
-- 
1.7.8.110.g4cb5d



From pintu.k at samsung.com  Tue Mar 13 00:53:46 2012
From: pintu.k at samsung.com (PINTU KUMAR)
Date: Tue, 13 Mar 2012 04:53:46 +0000 (GMT)
Subject: [INFO] : Hibernation and Resume between 2 similar devices
Message-ID: <28119509.96581331614425960.JavaMail.weblogic@epml27>

Dear All,

I am just curious to know if it is possible to "Hibernate in one device" and "Resume the hibernated image from another similar device".

Suppose, I have 2 exactly similar device (Laptop or mobile phone) with me.
At one time I will be working on only one device at a time.
Suppose I started my work on "Device 1"  with few opened application and later I wanted to switch to "Device 2" which is exactly similar to Device 1.
I thought to hibernate (suspend to disk) the Device 1 and store the hibernated image as a swap file and later transfer to sd card.
Then take of the sd card from Device 1 and put it into Device 2.
Copy the swap file from sd card to Device 2 in some swap partition.
Then reboot the Device 2 to Resume from this swap file.
I will get back my Device 1 content in Device 2.

Hope this is possible ?

Any comments.....

Regards,
Pintu





From tarun.kanti at ti.com  Tue Mar 13 01:31:57 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Tue, 13 Mar 2012 11:01:57 +0530
Subject: [PATCH v3 13/13] gpio/omap: fix incorrect update to
 context.irqenable1
In-Reply-To: <87haxtwjwt.fsf@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-14-git-send-email-tarun.kanti@ti.com>
 <87haxtwjwt.fsf@ti.com>
Message-ID: <CAC83Zv+_kOTe1rThNC2_KEqc+cMdt6YzEbCqyr9pnT8Z41u9Vw@mail.gmail.com>

On Tue, Mar 13, 2012 at 3:39 AM, Kevin Hilman <khilman at ti.com> wrote:
> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>
>> In _enable_gpio_irqbank() when bank->regs->set_irqenable is valid,
>> gpio_mask can be directly set by writing to set_irqenable register
>> without overwriting current value.
>
> Ouch. ?Nice catch.
>
>> In order to ensure the same is
>> stored in context.irqenable1, we must read from regs->irqenable
>> instead of overwriting it with gpio_mask.
>> The overwriting makes sense only in the second case where irqenable
>> is explicitly read and updated with new gpio_mask before writing it
>> back. However, for consistency reading regs->irqenable into the
>> bank->context.irqenable1 takes care of both the scenarios.
>
> ...takes care of both scenarios, but adds and extra duplicate read for
> the second.
Right. I wanted to keep code change minimum.
>
> Instead, how about just move the context update into each side of the
> if/else? ?untested patch below to show what I mean.
Yes, initially I thought of doing in this way as well. I will make the change.
--
Tarun
>
> Kevin
>
>
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 752ae9b..f8b7099 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -442,6 +442,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
> ? ? ? ?if (bank->regs->set_irqenable) {
> ? ? ? ? ? ? ? ?reg += bank->regs->set_irqenable;
> ? ? ? ? ? ? ? ?l = gpio_mask;
> + ? ? ? ? ? ? ? bank->context.irqenable1 |= gpio_mask;
> ? ? ? ?} else {
> ? ? ? ? ? ? ? ?reg += bank->regs->irqenable;
> ? ? ? ? ? ? ? ?l = __raw_readl(reg);
> @@ -449,10 +450,10 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
> ? ? ? ? ? ? ? ? ? ? ? ?l &= ~gpio_mask;
> ? ? ? ? ? ? ? ?else
> ? ? ? ? ? ? ? ? ? ? ? ?l |= gpio_mask;
> + ? ? ? ? ? ? ? bank->context.irqenable1 = l;
> ? ? ? ?}
>
> ? ? ? ?__raw_writel(l, reg);
> - ? ? ? bank->context.irqenable1 = l;
> ?}
>
> ?static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
> @@ -463,6 +464,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
> ? ? ? ?if (bank->regs->clr_irqenable) {
> ? ? ? ? ? ? ? ?reg += bank->regs->clr_irqenable;
> ? ? ? ? ? ? ? ?l = gpio_mask;
> + ? ? ? ? ? ? ? bank->context.irqenable1 &= ~gpio_mask;
> ? ? ? ?} else {
> ? ? ? ? ? ? ? ?reg += bank->regs->irqenable;
> ? ? ? ? ? ? ? ?l = __raw_readl(reg);
> @@ -470,10 +472,10 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
> ? ? ? ? ? ? ? ? ? ? ? ?l |= gpio_mask;
> ? ? ? ? ? ? ? ?else
> ? ? ? ? ? ? ? ? ? ? ? ?l &= ~gpio_mask;
> + ? ? ? ? ? ? ? bank->context.irqenable1 = l;
> ? ? ? ?}
>
> ? ? ? ?__raw_writel(l, reg);
> - ? ? ? bank->context.irqenable1 = l;
> ?}
>
> ?static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
>


From mika.westerberg at iki.fi  Tue Mar 13 01:45:09 2012
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Tue, 13 Mar 2012 07:45:09 +0200
Subject: [PATCH v4 04/11] ep93xx: Use ioremap for backlight driver
In-Reply-To: <1331592502-9083-5-git-send-email-rmallon@gmail.com>
References: <1331592502-9083-5-git-send-email-rmallon@gmail.com>
Message-ID: <20120313054509.GC4596@mwesterb-mobl.ger.corp.intel.com>

On Tue, Mar 13, 2012 at 09:48:15AM +1100, Ryan Mallon wrote:
> The ep93xx backlight driver uses a single register within the
> framebuffer's register space. Currently the backlight driver uses a
> static IO mapping for the register since the memory cannot be
> requested by both drivers.
> 
> Convert the static mapping to use ioremap so that we can remove the
> dependency on mach/hardware.h. To do so, we need remove the
> request_mem_region from both the backlight and framebuffer drivers,
> since whichever driver is loaded second will fail with -EBUSY
> otherwise.
> 
> A proper fix is still required, and a FIXME comment has been added to
> both drivers.
> 
> Signed-off-by: Ryan Mallon <rmallon at gmail.com>
> Suggested-by: Arnd Bergmann <arnd at arndb.de>
> Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Mika Westerberg <mika.westerberg at iki.fi>

Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>


From mad_soft at inbox.ru  Tue Mar 13 01:46:27 2012
From: mad_soft at inbox.ru (Dmitry Artamonow)
Date: Tue, 13 Mar 2012 09:46:27 +0400
Subject: [PATCH] arm/tegra: pcie: fix return value of function
In-Reply-To: <CAOesGMi0aqCjLsJ5wWXwFVQL2T8wtUuE14rFZ9h7NKHXcWAoqQ@mail.gmail.com>
References: <CAOesGMi0aqCjLsJ5wWXwFVQL2T8wtUuE14rFZ9h7NKHXcWAoqQ@mail.gmail.com>
Message-ID: <1331617587-10714-1-git-send-email-mad_soft@inbox.ru>

In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
tegra_pcie_enable_controller() function type has been changed from
void to int, but the last return statement wasn't converted, so
function returns undefined value. Fix it.

Also while at it, address couple of minor concerns raised by reviewers:
use usleep_range for delay, and lower the value of timeout to 300ms
to be consistent with Nvidia Vibrante kernel.

Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>
---
 arch/arm/mach-tegra/pcie.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 7313059..54a816f 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -639,10 +639,10 @@ static int tegra_pcie_enable_controller(void)
 	pads_writel(0xfa5cfa5c, 0xc8);
 
 	/* Wait for the PLL to lock */
-	timeout = 2000;
+	timeout = 300;
 	do {
 		val = pads_readl(PADS_PLL_CTL);
-		mdelay(1);
+		usleep_range(1000, 1000);
 		if (--timeout == 0) {
 			pr_err("Tegra PCIe error: timeout waiting for PLL\n");
 			return -EBUSY;
@@ -677,7 +677,7 @@ static int tegra_pcie_enable_controller(void)
 	/* Disable all execptions */
 	afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-	return;
+	return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
-- 
1.7.5.1.300.gc565c



From tarun.kanti at ti.com  Tue Mar 13 02:03:17 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Tue, 13 Mar 2012 11:33:17 +0530
Subject: [PATCH v3 11/13] gpio/omap: fix dataout register overwrite in
 _set_gpio_dataout_*
In-Reply-To: <87y5r5wkmu.fsf@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-12-git-send-email-tarun.kanti@ti.com>
 <87y5r5wkmu.fsf@ti.com>
Message-ID: <CAC83ZvJ5rjNJoSZW=j=DXQWKWGgr_Wqu8ukOubxKd7xuEQ4pzQ@mail.gmail.com>

On Tue, Mar 13, 2012 at 3:24 AM, Kevin Hilman <khilman at ti.com> wrote:
> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>
>> In the existing _set_gpio_dataout_*() implementation, the dataout
>> register is overwritten every time the function is called. This is
>> not intended behavior because that would end up one user of a GPIO
>> line overwriting what is written by another. Fix this so that previous
>> value is always preserved until explicitly changed by respective
>> user/driver of the GPIO line.
>>
>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>> ---
>> ?drivers/gpio/gpio-omap.c | ? ?3 +++
>> ?1 files changed, 3 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
>> index 04c2677..2e8e476 100644
>> --- a/drivers/gpio/gpio-omap.c
>> +++ b/drivers/gpio/gpio-omap.c
>> @@ -114,6 +114,7 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
>> ? ? ? else
>> ? ? ? ? ? ? ? reg += bank->regs->clr_dataout;
>>
>> + ? ? l |= __raw_readl(bank->base + bank->regs->set_dataout);
>
> minor: IMO, it's more reader-friendly if this looks like
>
> ? ? ? l = __raw_read(...)
> ? ? ? l |= GPIO_BIT(...)
> ? ? ? __raw_write(...)
Agreed. I will make the change.

>
>> ? ? ? __raw_writel(l, reg);
>> ? ? ? bank->context.dataout = l;
>> ?}
>> @@ -130,6 +131,8 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
>> ? ? ? ? ? ? ? l |= gpio_bit;
>> ? ? ? else
>> ? ? ? ? ? ? ? l &= ~gpio_bit;
>> +
>> + ? ? l |= __raw_readl(bank->base + bank->regs->set_dataout);
>
> There's already a __raw_read() in this function just above.
Right. Thanks.
--
Tarun
>
>> ? ? ? __raw_writel(l, reg);
>> ? ? ? bank->context.dataout = l;
>> ?}


From thomas.abraham at linaro.org  Tue Mar 13 02:05:53 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 11:35:53 +0530
Subject: [PATCH v3 1/2] mfd: add irq domain support for max8997 interrupts
In-Reply-To: <20120313032832.655983E07E4@localhost>
References: <1330000688-11226-1-git-send-email-thomas.abraham@linaro.org>
 <1330000688-11226-2-git-send-email-thomas.abraham@linaro.org>
 <20120313032832.655983E07E4@localhost>
Message-ID: <CAJuYYwTKMWgits6xd0UUvRPwr40NwJfO2HncUOW9J=EZbFs8=Q@mail.gmail.com>

On 13 March 2012 08:58, Grant Likely <grant.likely at secretlab.ca> wrote:
> On Thu, 23 Feb 2012 18:08:07 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
>> Add irq domain support for max8997 interrupts. The reverse mapping method
>> used is linear mapping since the sub-drivers of max8997 such as regulator
>> and charger drivers can use the max8997 irq_domain to get the linux irq
>> number for max8997 interrupts. All uses of irq_base in platform data and
>> max8997 driver private data are removed.
>>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Cc: MyungJoo Ham <myungjoo.ham at samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
>> ---
>> ?arch/arm/mach-exynos/mach-nuri.c ? ?| ? ?4 --
>> ?arch/arm/mach-exynos/mach-origen.c ?| ? ?1 -
>> ?drivers/mfd/max8997-irq.c ? ? ? ? ? | ? 60 ++++++++++++++++++++--------------
>> ?drivers/mfd/max8997.c ? ? ? ? ? ? ? | ? ?1 -
>> ?include/linux/mfd/max8997-private.h | ? ?4 ++-
>> ?include/linux/mfd/max8997.h ? ? ? ? | ? ?1 -
>> ?6 files changed, 38 insertions(+), 33 deletions(-)
>
> Nice patch. ?Nice diffstat too. ?Some comments below, but I'm happy with where
> this is at.
>
> Acked-by: Grant Likely <grant.likely at secretlab.ca>

Thank you Grant for reviewing this patch.

>
>>
>> diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
>> index a6b9162..1e9ba12 100644
>> --- a/arch/arm/mach-exynos/mach-nuri.c
>> +++ b/arch/arm/mach-exynos/mach-nuri.c
>> @@ -1078,12 +1078,8 @@ static struct platform_device nuri_max8903_device = {
>> ?static void __init nuri_power_init(void)
>> ?{
>> ? ? ? int gpio;
>> - ? ? int irq_base = IRQ_GPIO_END + 1;
>> ? ? ? int ta_en = 0;
>>
>> - ? ? nuri_max8997_pdata.irq_base = irq_base;
>> - ? ? irq_base += MAX8997_IRQ_NR;
>> -
>> ? ? ? gpio = EXYNOS4_GPX0(7);
>> ? ? ? gpio_request(gpio, "AP_PMIC_IRQ");
>> ? ? ? s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
>> diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
>> index 02c242e..328dadb 100644
>> --- a/arch/arm/mach-exynos/mach-origen.c
>> +++ b/arch/arm/mach-exynos/mach-origen.c
>> @@ -424,7 +424,6 @@ static struct max8997_platform_data __initdata origen_max8997_pdata = {
>> ? ? ? .buck1_gpiodvs ?= false,
>> ? ? ? .buck2_gpiodvs ?= false,
>> ? ? ? .buck5_gpiodvs ?= false,
>> - ? ? .irq_base ? ? ? = IRQ_GPIO_END + 1,
>>
>> ? ? ? .ignore_gpiodvs_side_effect = true,
>> ? ? ? .buck125_default_idx = 0x0,
>> diff --git a/drivers/mfd/max8997-irq.c b/drivers/mfd/max8997-irq.c
>> index 09274cf..3d8c9d1 100644
>> --- a/drivers/mfd/max8997-irq.c
>> +++ b/drivers/mfd/max8997-irq.c
>> @@ -142,7 +142,8 @@ static void max8997_irq_sync_unlock(struct irq_data *data)
>> ?static const inline struct max8997_irq_data *
>> ?irq_to_max8997_irq(struct max8997_dev *max8997, int irq)
>> ?{
>> - ? ? return &max8997_irqs[irq - max8997->irq_base];
>> + ? ? struct irq_data *data = irq_get_irq_data(irq);
>> + ? ? return &max8997_irqs[data->hwirq];
>
> Hahaha. ?The max8997_irqs table is kind of overdone when the group and mask values
> can be arithmetically derived from the hwirq number..

Yes, I agree. Each group could have maximum of 8 interrupts. Then,
data->hwirq % 8 will be the group number and data->hwirq & 7 would be
the mask. The enum max8997_irq can then be adjusted to accommodate
unused irq numbers.

>
> This change is fine, but the driver could use some refactoring. ?:-)

Ok.

>
>> ?}
>>
>> ?static void max8997_irq_mask(struct irq_data *data)
>> @@ -182,7 +183,7 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
>> ? ? ? u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
>> ? ? ? u8 irq_src;
>> ? ? ? int ret;
>> - ? ? int i;
>> + ? ? int i, cur_irq;
>>
>> ? ? ? ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
>> ? ? ? if (ret < 0) {
>> @@ -269,8 +270,10 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
>>
>> ? ? ? /* Report */
>> ? ? ? for (i = 0; i < MAX8997_IRQ_NR; i++) {
>> - ? ? ? ? ? ? if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask)
>> - ? ? ? ? ? ? ? ? ? ? handle_nested_irq(max8997->irq_base + i);
>> + ? ? ? ? ? ? if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
>> + ? ? ? ? ? ? ? ? ? ? cur_irq = irq_find_mapping(max8997->irq_domain, i);
>> + ? ? ? ? ? ? ? ? ? ? handle_nested_irq(cur_irq);
>> + ? ? ? ? ? ? }
>
> Well, if you're using the linear mapping, then only actually allocated irqs will
> have a mapping set up. ?So the driver could simply do:
>
> ? ? ? ?for (i = 0; i < MAX8997_IRQ_NR; i++) {
> ? ? ? ? ? ? ? ?cur_irq = irq_find_mapping(max8997->irq_domain, i);
> ? ? ? ? ? ? ? ?if (cur_irq)
> ? ? ? ? ? ? ? ? ? ? ? ?handle_nested_irq(cur_irq);
> ? ? ? ?}

Thanks for the suggestion. I will include this change and repost this patch.

Regards,
Thomas.

[...]


From tarun.kanti at ti.com  Tue Mar 13 02:33:34 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Tue, 13 Mar 2012 12:03:34 +0530
Subject: [PATCH v3 11/13] gpio/omap: fix dataout register overwrite in
 _set_gpio_dataout_*
In-Reply-To: <CAC83ZvJ5rjNJoSZW=j=DXQWKWGgr_Wqu8ukOubxKd7xuEQ4pzQ@mail.gmail.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-12-git-send-email-tarun.kanti@ti.com>
 <87y5r5wkmu.fsf@ti.com>
 <CAC83ZvJ5rjNJoSZW=j=DXQWKWGgr_Wqu8ukOubxKd7xuEQ4pzQ@mail.gmail.com>
Message-ID: <CAC83Zv+CZOGnSpOJgfCgEv-eyWXZzV+_mmd37CBMKM6iMtEksQ@mail.gmail.com>

On Tue, Mar 13, 2012 at 11:33 AM, DebBarma, Tarun Kanti
<tarun.kanti at ti.com> wrote:
> On Tue, Mar 13, 2012 at 3:24 AM, Kevin Hilman <khilman at ti.com> wrote:
>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>>
>>> In the existing _set_gpio_dataout_*() implementation, the dataout
>>> register is overwritten every time the function is called. This is
>>> not intended behavior because that would end up one user of a GPIO
>>> line overwriting what is written by another. Fix this so that previous
>>> value is always preserved until explicitly changed by respective
>>> user/driver of the GPIO line.
>>>
>>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>>> ---
>>> ?drivers/gpio/gpio-omap.c | ? ?3 +++
>>> ?1 files changed, 3 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
>>> index 04c2677..2e8e476 100644
>>> --- a/drivers/gpio/gpio-omap.c
>>> +++ b/drivers/gpio/gpio-omap.c
>>> @@ -114,6 +114,7 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
>>> ? ? ? else
>>> ? ? ? ? ? ? ? reg += bank->regs->clr_dataout;
>>>
>>> + ? ? l |= __raw_readl(bank->base + bank->regs->set_dataout);
>>
>> minor: IMO, it's more reader-friendly if this looks like
>>
>> ? ? ? l = __raw_read(...)
>> ? ? ? l |= GPIO_BIT(...)
>> ? ? ? __raw_write(...)
> Agreed. I will make the change.
Also, the read should be: __raw_readl(bank->base + bank->regs->dataout);
instead of bank->regs->set_dataout.
--
Tarun
>
>>
>>> ? ? ? __raw_writel(l, reg);
>>> ? ? ? bank->context.dataout = l;
>>> ?}
>>> @@ -130,6 +131,8 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
>>> ? ? ? ? ? ? ? l |= gpio_bit;
>>> ? ? ? else
>>> ? ? ? ? ? ? ? l &= ~gpio_bit;
>>> +
>>> + ? ? l |= __raw_readl(bank->base + bank->regs->set_dataout);
>>
>> There's already a __raw_read() in this function just above.
> Right. Thanks.
> --
> Tarun
>>
>>> ? ? ? __raw_writel(l, reg);
>>> ? ? ? bank->context.dataout = l;
>>> ?}


From thomas.abraham at linaro.org  Tue Mar 13 02:44:42 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 12:14:42 +0530
Subject: [PATCH v3 2/2] regulator: add device tree support for max8997
In-Reply-To: <20120313034306.16CF73E07E4@localhost>
References: <1330000688-11226-1-git-send-email-thomas.abraham@linaro.org>
 <1330000688-11226-3-git-send-email-thomas.abraham@linaro.org>
 <20120313034306.16CF73E07E4@localhost>
Message-ID: <CAJuYYwRAXyU7d7qhGUX-=qWUJ0M1KB3XCGPOnUxToP=0XOhzqg@mail.gmail.com>

On 13 March 2012 09:13, Grant Likely <grant.likely at secretlab.ca> wrote:
> On Thu, 23 Feb 2012 18:08:08 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
>> Add device tree based discovery support for max8997.
>>
>> Cc: MyungJoo Ham <myungjoo.ham at samsung.com>
>> Cc: Rajendra Nayak <rnayak at ti.com>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
>> ---
>> ?.../devicetree/bindings/regulator/max8997-pmic.txt | ?134 +++++++++++++++++++
>> ?drivers/mfd/max8997.c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 72 ++++++++++-
>> ?drivers/regulator/max8997.c ? ? ? ? ? ? ? ? ? ? ? ?| ?139 +++++++++++++++++++-
>> ?include/linux/mfd/max8997.h ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
>> ?4 files changed, 344 insertions(+), 2 deletions(-)
>> ?create mode 100644 Documentation/devicetree/bindings/regulator/max8997-pmic.txt
>>

[...]

>> diff --git a/drivers/mfd/max8997.c b/drivers/mfd/max8997.c
>> index 20ecad3..13180be 100644
>> --- a/drivers/mfd/max8997.c
>> +++ b/drivers/mfd/max8997.c
>> @@ -23,6 +23,7 @@
>>
>> ?#include <linux/slab.h>
>> ?#include <linux/i2c.h>
>> +#include <linux/of_irq.h>
>> ?#include <linux/interrupt.h>
>> ?#include <linux/pm_runtime.h>
>> ?#include <linux/module.h>
>> @@ -123,6 +124,60 @@ int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask)
>> ?}
>> ?EXPORT_SYMBOL_GPL(max8997_update_reg);
>>
>> +#ifdef CONFIG_OF
>> +/*
>> + * Only the common platform data elements for max8997 are parsed here from the
>> + * device tree. Other sub-modules of max8997 such as pmic, rtc and others have
>> + * to parse their own platform data elements from device tree.
>> + *
>> + * The max8997 platform data structure is instantiated here and the drivers for
>> + * the sub-modules need not instantiate another instance while parsing their
>> + * platform data.
>> + */
>> +static int max8997_i2c_parse_dt_pdata(struct device *dev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct max8997_platform_data **pdata)
>> +{
>> + ? ? struct max8997_platform_data *pd;
>> +
>> + ? ? pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
>> + ? ? if (!pd) {
>> + ? ? ? ? ? ? dev_err(dev, "could not allocate memory for pdata\n");
>> + ? ? ? ? ? ? return -ENOMEM;
>> + ? ? }
>> +
>> + ? ? pd->ono = irq_of_parse_and_map(dev->of_node, 1);
>> +
>> + ? ? /*
>> + ? ? ?* ToDo: the 'wakeup' member in the platform data is more of a linux
>> + ? ? ?* specfic information. Hence, there is no binding for that yet and
>> + ? ? ?* not parsed here.
>> + ? ? ?*/
>> +
>> + ? ? *pdata = pd;
>> + ? ? return 0;
>> +}
>> +#else
>> +static int max8997_i2c_parse_dt_pdata(struct device *dev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct max8997_platform_data **pdata)
>> +{
>> + ? ? return 0;
>> +}
>> +#endif
>> +
>> +static struct of_device_id __devinitdata max8997_pmic_dt_match[];
>
> Move the actual definition of this structure up to here so that a forward
> declaration becomes unnecessary.
>

Ok.

>> +static inline int max8997_i2c_get_driver_data(struct i2c_client *i2c,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const struct i2c_device_id *id)
>> +{
>> +#ifdef CONFIG_OF
>> + ? ? if (i2c->dev.of_node) {
>> + ? ? ? ? ? ? const struct of_device_id *match;
>> + ? ? ? ? ? ? match = of_match_node(max8997_pmic_dt_match, i2c->dev.of_node);
>> + ? ? ? ? ? ? return (int)match->data;
>> + ? ? }
>> +#endif
>> + ? ? return (int)id->driver_data;
>> +}
>> +
>> ?static int max8997_i2c_probe(struct i2c_client *i2c,
>> ? ? ? ? ? ? ? ? ? ? ? ? ? const struct i2c_device_id *id)
>> ?{
>> @@ -137,9 +192,16 @@ static int max8997_i2c_probe(struct i2c_client *i2c,
>> ? ? ? i2c_set_clientdata(i2c, max8997);
>> ? ? ? max8997->dev = &i2c->dev;
>> ? ? ? max8997->i2c = i2c;
>> - ? ? max8997->type = id->driver_data;
>> + ? ? max8997->type = max8997_i2c_get_driver_data(i2c, id);
>> ? ? ? max8997->irq = i2c->irq;
>>
>> + ? ? if (max8997->dev->of_node) {
>> + ? ? ? ? ? ? ret = max8997_i2c_parse_dt_pdata(max8997->dev, &pdata);
>> + ? ? ? ? ? ? if (ret)
>> + ? ? ? ? ? ? ? ? ? ? goto err;
>> + ? ? ? ? ? ? i2c->dev.platform_data = pdata;
>
> This line is illegal. ?Drivers must *not* change the value of dev->platform_data.
> instead the valid pdata pointer needs to be stored in the max8997 private data
> structure.

The intention here was to let the max8897 driver's mfd portion create
an 'common' instance of max8897 platform data and allow the max8997
sub-drivers such as the pmic driver and charger driver use that
'common' instance to populate their respective platform data portions
from dt. But, assigning that allocated pdata pointer to
i2c->dev.platform_data was not correct, I agree.

Instead, a new pointer to 'struct max8997_platform_data' will be added
to 'struct max8997_dev', assign the pdata in the mfd driver to this
new member and let the sub-drivers use the pdata pointer in 'struct
max8997_dev'. I will do this change and repost this patch.

>
>> + ? ? }
>> +
>
> If you tweak the definition of max8997_i2c_parse_dt_pdata() then this block can
> be simplified to:
>
> ? ? ? ?pdata = max8997_i2c_parse_dt_pdata(max8997->dev, &pdata);
> ? ? ? ?if (!pdata)
> ? ? ? ? ? ? ? ?pdata = i2c->dev.platform_data,
> ? ? ? ?if (!pdata)
> ? ? ? ? ? ? ? ?goto err;
>
>
> Otherwise, the patch looks pretty good. ?(although seeing the decode function
> has got me thinking that we need a much better way of decoding the dt data).

The parsing function looks huge since there is lot of data to pick up
from the dt node.

Thanks for your comments.

Regards,
Thomas.

[...]

>
> g.


From thomas.abraham at linaro.org  Tue Mar 13 02:46:17 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 12:16:17 +0530
Subject: [PATCH v4 2/2] ARM: Exynos: Add device tree support for interrupt
 combiner
In-Reply-To: <20120313035246.6BC8A3E07E4@localhost>
References: <1329798806-32482-1-git-send-email-thomas.abraham@linaro.org>
 <1329798806-32482-3-git-send-email-thomas.abraham@linaro.org>
 <20120313035246.6BC8A3E07E4@localhost>
Message-ID: <CAJuYYwQGbhtxNg0G=QMooMfH8Mkf8KwSzLk61OkpwL4ZuR1fDQ@mail.gmail.com>

On 13 March 2012 09:22, Grant Likely <grant.likely at secretlab.ca> wrote:
> On Tue, 21 Feb 2012 10:03:26 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
>> Add device tree based instantiation of the interrupt combiner controller.
>>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
>> ---
>> @@ -406,13 +432,33 @@ void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
>>
>> ? ? ? for (i = 0; i < MAX_COMBINER_NR; i++) {
>> ? ? ? ? ? ? ? combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
>> - ? ? ? ? ? ? combiner_cascade_irq(i, IRQ_SPI(i));
>> +#ifdef CONFIG_OF
>> + ? ? ? ? ? ? irq = np ? irq_of_parse_and_map(np, i) : IRQ_SPI(i);
>> +#else
>> + ? ? ? ? ? ? irq = IRQ_SPI(i);
>> +#endif
>
> Hmmm, the #ifdef is rather ugly. ?I'd rather have an empty
> irq_of_parse_and_map() that always returns 0.
>
> The patch series is fine, and you can add my acked-by, but please send
> a follow-up patch to clean it up.
>
> Acked-by: Grant Likely <grant.likely at secretlab.ca>
>

Thanks. I will send a follow-up to clean it.

Regards,
Thomas.


From tarun.kanti at ti.com  Tue Mar 13 02:52:28 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Tue, 13 Mar 2012 12:22:28 +0530
Subject: [PATCH v3 11/13] gpio/omap: fix dataout register overwrite in
 _set_gpio_dataout_*
In-Reply-To: <CAC83Zv+CZOGnSpOJgfCgEv-eyWXZzV+_mmd37CBMKM6iMtEksQ@mail.gmail.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-12-git-send-email-tarun.kanti@ti.com>
 <87y5r5wkmu.fsf@ti.com>
 <CAC83ZvJ5rjNJoSZW=j=DXQWKWGgr_Wqu8ukOubxKd7xuEQ4pzQ@mail.gmail.com>
 <CAC83Zv+CZOGnSpOJgfCgEv-eyWXZzV+_mmd37CBMKM6iMtEksQ@mail.gmail.com>
Message-ID: <CAC83ZvLmaLOr4_eZZzKyP2=KvkG+LjHjeOwvxdQHhuiB8+2L0w@mail.gmail.com>

On Tue, Mar 13, 2012 at 12:03 PM, DebBarma, Tarun Kanti
<tarun.kanti at ti.com> wrote:
> On Tue, Mar 13, 2012 at 11:33 AM, DebBarma, Tarun Kanti
> <tarun.kanti at ti.com> wrote:
>> On Tue, Mar 13, 2012 at 3:24 AM, Kevin Hilman <khilman at ti.com> wrote:
>>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>>>
>>>> In the existing _set_gpio_dataout_*() implementation, the dataout
>>>> register is overwritten every time the function is called. This is
>>>> not intended behavior because that would end up one user of a GPIO
>>>> line overwriting what is written by another. Fix this so that previous
>>>> value is always preserved until explicitly changed by respective
>>>> user/driver of the GPIO line.
>>>>
>>>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>>>> ---
>>>> ?drivers/gpio/gpio-omap.c | ? ?3 +++
>>>> ?1 files changed, 3 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
>>>> index 04c2677..2e8e476 100644
>>>> --- a/drivers/gpio/gpio-omap.c
>>>> +++ b/drivers/gpio/gpio-omap.c
>>>> @@ -114,6 +114,7 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
>>>> ? ? ? else
>>>> ? ? ? ? ? ? ? reg += bank->regs->clr_dataout;
>>>>
>>>> + ? ? l |= __raw_readl(bank->base + bank->regs->set_dataout);
>>>
>>> minor: IMO, it's more reader-friendly if this looks like
>>>
>>> ? ? ? l = __raw_read(...)
>>> ? ? ? l |= GPIO_BIT(...)
>>> ? ? ? __raw_write(...)
>> Agreed. I will make the change.
> Also, the read should be: __raw_readl(bank->base + bank->regs->dataout);
> instead of bank->regs->set_dataout.
I see a problem with this implementation. It is not correct to write l
|= GPIO_BIT(...).
For example if we write to clr_dataout register we would end up
clearing bits which
we are not supposed to. We should just be operating on current GPIO_BIT(...).
The l |= GPIO_BIT(...) is needed just to make sure that we have the
right context
stored. So the overall sequence should be something like this:

        void __iomem *reg = bank->base;
        u32 l = GPIO_BIT(bank, gpio);

        if (enable)
                reg += bank->regs->set_dataout;
        else
                reg += bank->regs->clr_dataout;

        __raw_writel(l, reg);
        l |= __raw_readl(bank->base + bank->regs->dataout);
        bank->context.dataout = l;
--
Tarun
>>
>>>
>>>> ? ? ? __raw_writel(l, reg);
>>>> ? ? ? bank->context.dataout = l;
>>>> ?}
>>>> @@ -130,6 +131,8 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
>>>> ? ? ? ? ? ? ? l |= gpio_bit;
>>>> ? ? ? else
>>>> ? ? ? ? ? ? ? l &= ~gpio_bit;
>>>> +
>>>> + ? ? l |= __raw_readl(bank->base + bank->regs->set_dataout);
>>>
>>> There's already a __raw_read() in this function just above.
>> Right. Thanks.
>> --
>> Tarun
>>>
>>>> ? ? ? __raw_writel(l, reg);
>>>> ? ? ? bank->context.dataout = l;
>>>> ?}


From santosh.shilimkar at ti.com  Tue Mar 13 02:53:14 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 13 Mar 2012 12:23:14 +0530
Subject: [PATCH 2/5] ARM: OMAP2+: add includes for missing prototypes
In-Reply-To: <20120312224252.4103.75837.stgit@dusk>
References: <20120312224006.4103.29464.stgit@dusk>
 <20120312224252.4103.75837.stgit@dusk>
Message-ID: <CAMQu2gytxATib1HzKNL65jgaNvQ_vf-isKL_RiKDO7ef75u-hA@mail.gmail.com>

On Tue, Mar 13, 2012 at 4:12 AM, Paul Walmsley <paul at pwsan.com> wrote:
>
> Several C files in arch/arm/mach-omap2 declare functions that are used
> by other files, but don't include the header file where the prototype is
> declared. ?This results in the following warnings from sparse:
>
> ? ?arch/arm/mach-omap2/irq.c:114:5: warning: symbol 'omap_irq_pending' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/irq.c:186:13: warning: symbol 'omap2_init_irq' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/irq.c:191:13: warning: symbol 'omap3_init_irq' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/irq.c:196:13: warning: symbol 'ti81xx_init_irq' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/irq.c:233:39: warning: symbol 'omap2_intc_handle_irq' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/irq.c:242:6: warning: symbol 'omap_intc_save_context' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/irq.c:265:6: warning: symbol 'omap_intc_restore_context' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/irq.c:291:6: warning: symbol 'omap3_intc_suspend' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/irq.c:297:6: warning: symbol 'omap3_intc_prepare_idle' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/irq.c:306:6: warning: symbol 'omap3_intc_resume_idle' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/irq.c:312:39: warning: symbol 'omap3_intc_handle_irq' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/omap-secure.c:59:12: warning: symbol 'omap_secure_ram_reserve_memblock' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/board-zoom-display.c:133:13: warning: symbol 'zoom_display_init' was not declared. Should it be static?
>
> Fix by including the appropriate header files.
>
> Signed-off-by: Paul Walmsley <paul at pwsan.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Cc: Senthilvadivu Guruswamy <svadivu at ti.com>
> ---
Thanks Paul for the fix.
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>


From jarkko.nikula at bitmer.com  Tue Mar 13 03:10:02 2012
From: jarkko.nikula at bitmer.com (Jarkko Nikula)
Date: Tue, 13 Mar 2012 09:10:02 +0200
Subject: [PATCH 5/5] ARM: OMAP2+: clean up some cppcheck warnings
In-Reply-To: <20120312224257.4103.11096.stgit@dusk>
References: <20120312224006.4103.29464.stgit@dusk>
 <20120312224257.4103.11096.stgit@dusk>
Message-ID: <4F5EF2CA.70703@bitmer.com>

On 03/13/2012 12:43 AM, Paul Walmsley wrote:
> Resolve some warnings identified by cppcheck in arch/arm/mach-omap2:
...
>     [arch/arm/mach-omap2/mcbsp.c:133]: (warning) scanf without field width limits can crash with huge input data
...
> diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
> index fb4bcf8..efe59c7 100644

> --- a/arch/arm/mach-omap2/mcbsp.c
> +++ b/arch/arm/mach-omap2/mcbsp.c
> @@ -130,7 +130,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
>  	struct omap_mcbsp_platform_data *pdata = NULL;
>  	struct platform_device *pdev;
>  
> -	sscanf(oh->name, "mcbsp%d", &id);
> +	sscanf(oh->name, "mcbsp%1d", &id);
>  
Correct if I'm wrong but is this a false alarm? Can %d scan more than
sizeof(int)?

Anyway this shouldn't be fatal issue since name comes from kernel
omap_hwmod data, i.e. only developer can hit it.

Peter: worth to check and possible add this Paul's fix to your mcbsp
change set.

-- 
Jarkko


From santosh.shilimkar at ti.com  Tue Mar 13 03:12:59 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 13 Mar 2012 12:42:59 +0530
Subject: [PATCH 1/5] ARM: OMAP2+: declare file-local functions as static
In-Reply-To: <20120312224251.4103.76124.stgit@dusk>
References: <20120312224006.4103.29464.stgit@dusk>
 <20120312224251.4103.76124.stgit@dusk>
Message-ID: <CAMQu2gwJGGL8VKuNxUmH5BbCYhTQCBDW7TbsE4RjCziE9TWCVQ@mail.gmail.com>

On Tue, Mar 13, 2012 at 4:12 AM, Paul Walmsley <paul at pwsan.com> wrote:
> Several function declarations used only in the files in which they're
> declared should include the static keyboard, but don't:
>
> ? ?arch/arm/mach-omap2/serial.c:248:6: warning: symbol 'cmdline_find_option' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/omap-wakeupgen.c:259:6: warning: symbol 'irq_sar_clear' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/board-rx51-peripherals.c:878:27: warning: symbol 'rx51_vibra_data' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/board-rx51-peripherals.c:882:27: warning: symbol 'rx51_audio_data' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/board-omap4panda.c:201:29: warning: symbol 'omap_panda_wlan_data' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/board-omap4panda.c:393:24: warning: symbol 'omap4_panda_dvi_device' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/board-omap4panda.c:403:12: warning: symbol 'omap4_panda_dvi_init' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/board-omap4panda.c:464:6: warning: symbol 'omap4_panda_display_init' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/hsmmc.c:434:6: warning: symbol 'omap_init_hsmmc' was not declared. Should it be static?
> ? ?arch/arm/mach-omap2/hwspinlock.c:31:12: warning: symbol 'hwspinlocks_init' was not declared. Should it be static?
>
> Mark all of these as static.
>
> Signed-off-by: Paul Walmsley <paul at pwsan.com>
> Cc: Govindraj R <govindraj.raja at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Cc: David Anders <x0132446 at ti.com>
> Cc: Simon Que <sque at ti.com>
> ---
For the wakeupgen change,
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>


From plagnioj at jcrosoft.com  Tue Mar 13 03:03:24 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 08:03:24 +0100
Subject: [PATCH 1/1] of: introduce helper to manage boolean
In-Reply-To: <20120313041652.563B63E0536@localhost>
References: <1328588028-24766-1-git-send-email-plagnioj@jcrosoft.com>
 <20120309014441.8236B3E0903@localhost>
 <20120309100435.GN27213@game.jcrosoft.org>
 <20120309162638.92E813E0880@localhost>
 <20120309163608.GQ27213@game.jcrosoft.org>
 <4F5E50DA.6080000@freescale.com>
 <20120313031739.GA18320@game.jcrosoft.org>
 <20120313041652.563B63E0536@localhost>
Message-ID: <20120313070324.GB18320@game.jcrosoft.org>

On 22:16 Mon 12 Mar     , Grant Likely wrote:
> On Tue, 13 Mar 2012 04:17:39 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > On 14:39 Mon 12 Mar     , Scott Wood wrote:
> > > On 03/09/2012 10:36 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > >>>> Ugh.  so any value other than 1 returns false?  I think that will surprise
> > > >>>> most people.
> > > >>>>
> > > >>>> I don't like this api or binding.  If it is a bool property, then why isn't
> > > >>>> simply testing for the property existance sufficient?
> > > >>> no if you want to disable it
> > > >>>
> > > >>> if a bool is define in the dtsi and want to disable it int the dts
> > > >>>
> > > >>> if you we can do the the invert
> > > >>>
> > > >>> if !0 => true
> > > >>>
> > > >>> is-ok;			=> true
> > > >>> is-ok = <val != 0>;	=> true
> > > >>> is-ok = <0>;		=> false
> > > >>
> > > >> This is a failure of the dtc tool, not the binding.  Accepting this binding
> > > >> means we have to live with it for a very long time.  It needs to be fixed
> > > >> in dtc instead so that properties can be deleted instead of only modified.
> > > > I understand your idea but today if you put and value in the property it's true.
> > > > 
> > > > So is-ok = <0>; is true also which is illogical as in any language a boolean is
> > > > true (1) or false (0). When I read the property I will understand false not true
> > > 
> > > You could say similar things about is-ok = "no" or is-ok = "" or is-ok =
> > > "I'd rather you didn't"... it's expected that violating the binding may
> > > produce illogical results.
> > today is most of the binding people use a number whe the want to be able to
> > delete it and it's the same in most of the promgramming language
> 
> It isn't yet a big pain point, so there isn't time pressure here.  Fixing the tool
> is the better solution, and since the kernel carries a copy of the tool we don't
> need to worry about adding a feature that isn't available by the dtc packaged by
> a distribution.
> 
> Fixing the tool is the correct thing to do.
I don't like it but ok

Can I get the ack on it and apply via my tree I've more tan 10 patches pending
because of this

Best Regards,
J.


From plagnioj at jcrosoft.com  Tue Mar 13 03:07:39 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 08:07:39 +0100
Subject: [PATCH 1/5 v3] i2c/gpio: add DT support
In-Reply-To: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120313070739.GC18320@game.jcrosoft.org>

On 09:50 Thu 08 Mar     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-i2c at vger.kernel.org
> Cc: devicetree-discuss at lists.ozlabs.org
> ---
> v3:
> 
> 	update i2c binding (Rob comments)
> 
> 	Jean can I have a ack to apply it?
> 
I update with last comment can one of hte i2c maintainer give a ack to apply
via at91 as I've long list of depedency

Best Regards,
J.


From plagnioj at jcrosoft.com  Tue Mar 13 03:08:13 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 08:08:13 +0100
Subject: [PATCH 2/5 v3] ARM: at91: sam9g20 add i2c DT support
In-Reply-To: <4F5A0CB5.2020203@gmail.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <1331196635-27203-2-git-send-email-plagnioj@jcrosoft.com>
 <4F58E77B.4010500@gmail.com>
 <20120309095336.GK27213@game.jcrosoft.org>
 <4F5A0CB5.2020203@gmail.com>
Message-ID: <20120313070813.GD18320@game.jcrosoft.org>

On 07:59 Fri 09 Mar     , Rob Herring wrote:
> On 03/09/2012 03:53 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 11:08 Thu 08 Mar     , Rob Herring wrote:
> >> On 03/08/2012 02:50 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>> For now on use i2c-gpio driver on the same pin as the hardware IP.
> >>>
> >>> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> >>> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> >>> Cc: devicetree-discuss at lists.ozlabs.org
> >>> ---
> >>> v3:
> >>>
> >>> 	update i2c binding (Rob comments)
> >>>
> >>> Best Regards,
> >>> J.
> >>>  arch/arm/boot/dts/at91sam9g20.dtsi |   13 +++++++++++++
> >>>  1 files changed, 13 insertions(+), 0 deletions(-)
> >>>
> >>> diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
> >>> index 4b0dc99..072b2da 100644
> >>> --- a/arch/arm/boot/dts/at91sam9g20.dtsi
> >>> +++ b/arch/arm/boot/dts/at91sam9g20.dtsi
> >>> @@ -189,4 +189,17 @@
> >>>  			status = "disabled";
> >>>  		};
> >>>  	};
> >>> +> > +	i2c-gpio at 0 {
> >>
> >> You updated the example, but not all the actual uses to i2c at 0.
> > on purpose as on some soc we will have HW and soft binding
> > 
> > on the board you put the alias
> > 
> 
> I'm not sure I follow.
> 
> If you use the h/w block, then you would have i2c@<addr> while for gpio
> it's basically an index.
> 
> Also, I don't think you need an alias for i2c. You should not care about
> bus numbering as devices should be sub nodes.
forget about it tired when I reply

Best Regards,
J.


From w.sang at pengutronix.de  Tue Mar 13 03:37:48 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 13 Mar 2012 08:37:48 +0100
Subject: [PATCH 1/5 v3] i2c/gpio: add DT support
In-Reply-To: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120313073748.GA7746@pengutronix.de>

On Thu, Mar 08, 2012 at 09:50:31AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-i2c at vger.kernel.org
> Cc: devicetree-discuss at lists.ozlabs.org

Your patch description says "add DT support" but you are doing a bit more.
This should at least be described here.

> ---
> v3:
> 
> 	update i2c binding (Rob comments)
> 
> 	Jean can I have a ack to apply it?
> 
> Best Regards,
> J.
>  .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 +++++++
>  drivers/i2c/busses/i2c-gpio.c                      |   94 +++++++++++++++----
>  2 files changed, 106 insertions(+), 20 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> 
> diff --git a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> new file mode 100644
> index 0000000..4f8ec94
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> @@ -0,0 +1,32 @@
> +Device-Tree bindings for i2c gpio driver
> +
> +Required properties:
> +	- compatible = "i2c-gpio";

I assume people at "devicetree-discuss" have taken care of that, yet I wonder
that this breaks the "vendor,product" syntax I know of for compatible entries.

> +	- gpios: sda and scl gpio
> +
> +
> +Optional properties:
> +	- i2c-gpio,sda-open-drain: sda as open drain
> +	- i2c-gpio,scl-open-drain: scl as open drain
> +	- i2c-gpio,scl-output-only: scl as output only
> +	- i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform)
> +	- i2c-gpio,timeout-ms: timeout to get data
> +
> +Example nodes:
> +
> +i2c at 0 {
> +	compatible = "i2c-gpio";
> +	gpios = <&pioA 23 0 /* sda */
> +		 &pioA 24 0 /* scl */
> +		>;
> +	i2c-gpio,sda-open-drain;
> +	i2c-gpio,scl-open-drain;
> +	i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	rv3029c2 at 56 {
> +		compatible = "rv3029c2";
> +		reg = <0x56>;
> +	};
> +};
> diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
> index a651779..98ae85b 100644
> --- a/drivers/i2c/busses/i2c-gpio.c
> +++ b/drivers/i2c/busses/i2c-gpio.c
> @@ -14,8 +14,15 @@
>  #include <linux/module.h>
>  #include <linux/slab.h>
>  #include <linux/platform_device.h>
> +#include <linux/gpio.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_i2c.h>
>  
> -#include <asm/gpio.h>
> +struct i2c_gpio_private_data {
> +	struct i2c_adapter adap;
> +	struct i2c_algo_bit_data bit_data;
> +	struct i2c_gpio_platform_data pdata;
> +};
>  
>  /* Toggle SDA by changing the direction of the pin */
>  static void i2c_gpio_setsda_dir(void *data, int state)
> @@ -78,24 +85,62 @@ static int i2c_gpio_getscl(void *data)
>  	return gpio_get_value(pdata->scl_pin);
>  }
>  
> +static int __devinit of_i2c_gpio_probe(struct device_node *np,
> +			     struct i2c_gpio_platform_data *pdata)
> +{
> +	u32 reg;
> +
> +	if (of_gpio_count(np) < 2)
> +		return -ENODEV;
> +
> +	pdata->sda_pin = of_get_gpio(np, 0);
> +	pdata->scl_pin = of_get_gpio(np, 1);
> +
> +	if (pdata->sda_pin < 0 || pdata->scl_pin < 0) {

gpio_is_valid()?

> +		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
> +		       np->full_name, pdata->sda_pin, pdata->scl_pin);
> +		return -ENODEV;
> +	}
> +
> +	of_property_read_u32(np, "i2c-gpio,delay-us", &pdata->udelay);
> +
> +	if (of_property_read_u32(np, "i2c-gpio,timeout-ms", &reg))
> +		pdata->timeout = msecs_to_jiffies(reg);
> +
> +	pdata->sda_is_open_drain =
> +		!!of_property_read_bool(np, "i2c-gpio,sda-open-drain");
> +	pdata->scl_is_open_drain =
> +		!!of_property_read_bool(np, "i2c-gpio,scl-open-drain");
> +	pdata->scl_is_output_only =
> +		!!of_property_read_bool(np, "i2c-gpio,scl-output-only");
> +
> +	return 0;
> +}
> +
>  static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  {
> +	struct i2c_gpio_private_data *priv;
>  	struct i2c_gpio_platform_data *pdata;
>  	struct i2c_algo_bit_data *bit_data;
>  	struct i2c_adapter *adap;
>  	int ret;
>  
> -	pdata = pdev->dev.platform_data;
> -	if (!pdata)
> -		return -ENXIO;
> +	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +	adap = &priv->adap;
> +	bit_data = &priv->bit_data;
> +	pdata = &priv->pdata;
>  
> -	ret = -ENOMEM;
> -	adap = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
> -	if (!adap)
> -		goto err_alloc_adap;
> -	bit_data = kzalloc(sizeof(struct i2c_algo_bit_data), GFP_KERNEL);
> -	if (!bit_data)
> -		goto err_alloc_bit_data;
> +	if (pdev->dev.of_node) {
> +		ret = of_i2c_gpio_probe(pdev->dev.of_node, pdata);
> +		if (ret)
> +			return ret;
> +	} else {
> +		if (!pdev->dev.platform_data)
> +			return -ENXIO;
> +		memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
> +	}
>  
>  	ret = gpio_request(pdata->sda_pin, "sda");
>  	if (ret)
> @@ -143,6 +188,7 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  	adap->algo_data = bit_data;
>  	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
>  	adap->dev.parent = &pdev->dev;
> +	adap->dev.of_node = pdev->dev.of_node;
>  
>  	/*
>  	 * If "dev->id" is negative we consider it as zero.
> @@ -154,7 +200,9 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto err_add_bus;
>  
> -	platform_set_drvdata(pdev, adap);
> +	of_i2c_register_devices(adap);
> +
> +	platform_set_drvdata(pdev, priv);
>  
>  	dev_info(&pdev->dev, "using pins %u (SDA) and %u (SCL%s)\n",
>  		 pdata->sda_pin, pdata->scl_pin,
> @@ -168,34 +216,40 @@ err_add_bus:
>  err_request_scl:
>  	gpio_free(pdata->sda_pin);
>  err_request_sda:
> -	kfree(bit_data);
> -err_alloc_bit_data:
> -	kfree(adap);
> -err_alloc_adap:
>  	return ret;
>  }
>  
>  static int __devexit i2c_gpio_remove(struct platform_device *pdev)
>  {
> +	struct i2c_gpio_private_data *priv;
>  	struct i2c_gpio_platform_data *pdata;
>  	struct i2c_adapter *adap;
>  
> -	adap = platform_get_drvdata(pdev);
> -	pdata = pdev->dev.platform_data;
> +	priv = platform_get_drvdata(pdev);
> +	adap = &priv->adap;
> +	pdata = &priv->pdata;
>  
>  	i2c_del_adapter(adap);
>  	gpio_free(pdata->scl_pin);
>  	gpio_free(pdata->sda_pin);
> -	kfree(adap->algo_data);
> -	kfree(adap);
>  
>  	return 0;
>  }
>  
> +#if defined(CONFIG_OF)
> +static const struct of_device_id i2c_gpio_dt_ids[] = {
> +	{ .compatible = "i2c-gpio", },
> +	{ /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, i2c_gpio_dt_ids);
> +#endif
> +
>  static struct platform_driver i2c_gpio_driver = {
>  	.driver		= {
>  		.name	= "i2c-gpio",
>  		.owner	= THIS_MODULE,
> +		.of_match_table	= of_match_ptr(i2c_gpio_dt_ids),
>  	},
>  	.probe		= i2c_gpio_probe,
>  	.remove		= __devexit_p(i2c_gpio_remove),

Otherwise looks good in general. What was your test scenario?

Thanks,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From paul at pwsan.com  Tue Mar 13 04:07:27 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 13 Mar 2012 02:07:27 -0600 (MDT)
Subject: [PATCH 5/5] ARM: OMAP2+: clean up some cppcheck warnings
In-Reply-To: <4F5EF2CA.70703@bitmer.com>
References: <20120312224006.4103.29464.stgit@dusk>
 <20120312224257.4103.11096.stgit@dusk> <4F5EF2CA.70703@bitmer.com>
Message-ID: <alpine.DEB.2.00.1203130154120.22211@utopia.booyaka.com>

On Tue, 13 Mar 2012, Jarkko Nikula wrote:

> On 03/13/2012 12:43 AM, Paul Walmsley wrote:
> > Resolve some warnings identified by cppcheck in arch/arm/mach-omap2:
> ...
> >     [arch/arm/mach-omap2/mcbsp.c:133]: (warning) scanf without field width limits can crash with huge input data
> ...
> > diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
> > index fb4bcf8..efe59c7 100644
> 
> > --- a/arch/arm/mach-omap2/mcbsp.c
> > +++ b/arch/arm/mach-omap2/mcbsp.c
> > @@ -130,7 +130,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
> >  	struct omap_mcbsp_platform_data *pdata = NULL;
> >  	struct platform_device *pdev;
> >  
> > -	sscanf(oh->name, "mcbsp%d", &id);
> > +	sscanf(oh->name, "mcbsp%1d", &id);
> >  
> Correct if I'm wrong but is this a false alarm? Can %d scan more than
> sizeof(int)?
> 
> Anyway this shouldn't be fatal issue since name comes from kernel
> omap_hwmod data, i.e. only developer can hit it.

Yes, I wasn't too worried about this one.  At the time, I didn't audit the 
kernel sscanf(), so I wasn't sure what its behavior was here. Glancing at 
that code now, it seems to ignore the field width for %d anyway.  So this 
is probably a pointless change that can be dropped from the patch.

Thanks for the review.


- Paul


From paul at pwsan.com  Tue Mar 13 04:12:05 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 13 Mar 2012 02:12:05 -0600 (MDT)
Subject: [PATCH v2 5/5] ARM: OMAP2+: clean up some cppcheck warnings
In-Reply-To: <20120312224257.4103.11096.stgit@dusk>
References: <20120312224006.4103.29464.stgit@dusk>
 <20120312224257.4103.11096.stgit@dusk>
Message-ID: <alpine.DEB.2.00.1203130211300.22211@utopia.booyaka.com>


Resolve some warnings identified by cppcheck in arch/arm/mach-omap2:

    [arch/arm/mach-omap2/usb-tusb6010.c:129]: (style) Checking if unsigned variable 'tmp' is less than zero.
    [arch/arm/mach-omap2/prm_common.c:241]: (error) Possible null pointer dereference: irq_setup - otherwise it is redundant to check if irq_setup is null at line 247
    [arch/arm/mach-omap2/pm34xx.c:790]: (style) Variable 'per_clkdm' is assigned a value that is never used
    [arch/arm/mach-omap2/pm34xx.c:790]: (style) Variable 'core_clkdm' is assigned a value that is never used
    [arch/arm/mach-omap2/pm24xx.c:185]: (style) Variable 'only_idle' is assigned a value that is never used
    [arch/arm/mach-omap2/mux.c:254]: (error) Possible null pointer dereference: mux
    [arch/arm/mach-omap2/mux.c:258]: (error) Possible null pointer dereference: mux
    [arch/arm/mach-omap2/gpmc-onenand.c:178]: (style) Variable 'tick_ns' is assigned a value that is never used
    [arch/arm/mach-omap2/gpio.c:56]: (error) Possible null pointer dereference: pdata - otherwise it is redundant to check if pdata is null at line 57
    [arch/arm/mach-omap2/devices.c:45]: (style) Variable 'l' is assigned a value that is never used
    [arch/arm/mach-omap2/board-am3517evm.c:134]: (style) Variable 'regval' is assigned a value that is never used

Some of them are pretty good catches, such the gpio.c:56 and
usb-tusb6010.c:129.

Thanks to Jarkko Nikula for some comments on the sscanf() warnings.
It seems that the kernel sscanf() ignores the field width anyway for the
%d format, so those changes have been dropped from this second version.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Peter Ujfalusi <peter.ujfalusi at ti.com>
Cc: Jarkko Nikula <jarkko.nikula at bitmer.com>
Cc: Charulatha Varadarajan <charu at ti.com>
---
 arch/arm/mach-omap2/board-am3517evm.c |    6 +-----
 arch/arm/mach-omap2/board-omap3evm.c  |    8 ++++----
 arch/arm/mach-omap2/devices.c         |    3 +--
 arch/arm/mach-omap2/gpio.c            |    2 +-
 arch/arm/mach-omap2/gpmc-onenand.c    |    3 +--
 arch/arm/mach-omap2/mux.c             |    2 +-
 arch/arm/mach-omap2/pm24xx.c          |    3 ---
 arch/arm/mach-omap2/pm34xx.c          |    4 +---
 arch/arm/mach-omap2/prm_common.c      |    4 +++-
 arch/arm/mach-omap2/usb-tusb6010.c    |    2 +-
 10 files changed, 14 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 4b1cfe3..24b1f9a 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -150,13 +150,9 @@ static void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
 	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 	regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
 	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
-	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-
-	return ;
+	omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 }
 
-
-
 #define LCD_PANEL_PWR		176
 #define LCD_PANEL_BKLIGHT_PWR	182
 #define LCD_PANEL_PWM		181
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c877236..becf41d 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -634,12 +634,12 @@ static void __init omap3_evm_wl12xx_init(void)
 
 static void __init omap3_evm_init(void)
 {
+	static struct omap_board_mux *obm;
+
 	omap3_evm_get_revision();
 
-	if (cpu_is_omap3630())
-		omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
-	else
-		omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
+	obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
+	omap3_mux_init(obm, OMAP_PACKAGE_CBB);
 
 	omap_board_config = omap3_evm_config;
 	omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 283d11e..b52cd16 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -42,7 +42,6 @@
 
 static int __init omap3_l3_init(void)
 {
-	int l;
 	struct omap_hwmod *oh;
 	struct platform_device *pdev;
 	char oh_name[L3_MODULES_MAX_LEN];
@@ -54,7 +53,7 @@ static int __init omap3_l3_init(void)
 	if (!(cpu_is_omap34xx()))
 		return -ENODEV;
 
-	l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
+	snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
 
 	oh = omap_hwmod_lookup(oh_name);
 
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 8cbfbc2..2803ff8 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -54,7 +54,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 	pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
 
 	pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
-	if (!pdata) {
+	if (!pdata->regs) {
 		pr_err("gpio%d: Memory allocation failed\n", id);
 		return -ENOMEM;
 	}
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 5cdce10..6ab726f 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -175,7 +175,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 	const int t_wpl  = 40;
 	const int t_wph  = 30;
 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
-	int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
+	int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
 	int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
 	int err, ticks_cez;
 	int cs = cfg->cs, freq = *freq_ptr;
@@ -239,7 +239,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 		break;
 	}
 
-	tick_ns = gpmc_ticks_to_ns(1);
 	div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
 	gpmc_clk_ns = gpmc_ticks_to_ns(div);
 	if (gpmc_clk_ns < 15) /* >66Mhz */
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 611a0e3..552225a 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -248,7 +248,7 @@ int omap_mux_init_signal(const char *muxname, int val)
 	int mux_mode;
 
 	mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
-	if (mux_mode < 0)
+	if (mux_mode < 0 || !mux)
 		return mux_mode;
 
 	old_mode = omap_mux_read(partition, mux->reg_offset);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 23de98d..b3a4765 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -182,8 +182,6 @@ static int omap2_allow_mpu_retention(void)
 
 static void omap2_enter_mpu_retention(void)
 {
-	int only_idle = 0;
-
 	/* Putting MPU into the WFI state while a transfer is active
 	 * seems to cause the I2C block to timeout. Why? Good question. */
 	if (omap2_i2c_active())
@@ -206,7 +204,6 @@ static void omap2_enter_mpu_retention(void)
 
 		omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 						 OMAP2_PM_PWSTCTRL);
-		only_idle = 1;
 	}
 
 	omap2_sram_idle();
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc69875..0b65785 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -787,7 +787,7 @@ static void __init pm_errata_configure(void)
 static int __init omap3_pm_init(void)
 {
 	struct power_state *pwrst, *tmp;
-	struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
+	struct clockdomain *neon_clkdm, *mpu_clkdm;
 	int ret;
 
 	if (!cpu_is_omap34xx())
@@ -841,8 +841,6 @@ static int __init omap3_pm_init(void)
 
 	neon_clkdm = clkdm_lookup("neon_clkdm");
 	mpu_clkdm = clkdm_lookup("mpu_clkdm");
-	per_clkdm = clkdm_lookup("per_clkdm");
-	core_clkdm = clkdm_lookup("core_clkdm");
 
 #ifdef CONFIG_SUSPEND
 	suspend_set_ops(&omap_pm_ops);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 860118a..c7c7373 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -238,7 +238,7 @@ void omap_prcm_irq_complete(void)
  */
 int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 {
-	int nr_regs = irq_setup->nr_regs;
+	int nr_regs;
 	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
 	int offset, i;
 	struct irq_chip_generic *gc;
@@ -247,6 +247,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 	if (!irq_setup)
 		return -EINVAL;
 
+	nr_regs = irq_setup->nr_regs;
+
 	if (prcm_irq_setup) {
 		pr_err("PRCM: already initialized; won't reinitialize\n");
 		return -EINVAL;
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 994d8f5..db84a46 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -126,7 +126,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
 	tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
 	if (tmp > 4)
 		return -ERANGE;
-	if (tmp <= 0)
+	if (tmp == 0)
 		tmp = 1;
 	t.page_burst_access = (fclk_ps * tmp) / 1000;
 
-- 
1.7.9.1



From thomas.abraham at linaro.org  Tue Mar 13 04:15:24 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 13:45:24 +0530
Subject: [PATCH v3 1/2] mfd: add irq domain support for max8997 interrupts
In-Reply-To: <CAJuYYwTKMWgits6xd0UUvRPwr40NwJfO2HncUOW9J=EZbFs8=Q@mail.gmail.com>
References: <1330000688-11226-1-git-send-email-thomas.abraham@linaro.org>
 <1330000688-11226-2-git-send-email-thomas.abraham@linaro.org>
 <20120313032832.655983E07E4@localhost>
 <CAJuYYwTKMWgits6xd0UUvRPwr40NwJfO2HncUOW9J=EZbFs8=Q@mail.gmail.com>
Message-ID: <CAJuYYwSQ-HRBU31=nWyzwqEBxj9LeAMOLQQVcAdf89dO9U0-sQ@mail.gmail.com>

On 13 March 2012 11:35, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> On 13 March 2012 08:58, Grant Likely <grant.likely at secretlab.ca> wrote:
>> On Thu, 23 Feb 2012 18:08:07 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
>>> Add irq domain support for max8997 interrupts. The reverse mapping method
>>> used is linear mapping since the sub-drivers of max8997 such as regulator
>>> and charger drivers can use the max8997 irq_domain to get the linux irq
>>> number for max8997 interrupts. All uses of irq_base in platform data and
>>> max8997 driver private data are removed.
>>>
>>> Cc: Grant Likely <grant.likely at secretlab.ca>
>>> Cc: MyungJoo Ham <myungjoo.ham at samsung.com>
>>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
>>> ---
>>> ?arch/arm/mach-exynos/mach-nuri.c ? ?| ? ?4 --
>>> ?arch/arm/mach-exynos/mach-origen.c ?| ? ?1 -
>>> ?drivers/mfd/max8997-irq.c ? ? ? ? ? | ? 60 ++++++++++++++++++++--------------
>>> ?drivers/mfd/max8997.c ? ? ? ? ? ? ? | ? ?1 -
>>> ?include/linux/mfd/max8997-private.h | ? ?4 ++-
>>> ?include/linux/mfd/max8997.h ? ? ? ? | ? ?1 -
>>> ?6 files changed, 38 insertions(+), 33 deletions(-)

[...]

>>
>> Hahaha. ?The max8997_irqs table is kind of overdone when the group and mask values
>> can be arithmetically derived from the hwirq number..
>
> Yes, I agree. Each group could have maximum of 8 interrupts. Then,
> data->hwirq % 8 will be the group number and data->hwirq & 7 would be

Typo here. group number = data->hwirq >> 3 and mask = data->hwirq & 7.

Thanks,
Thomas.


From sfr at canb.auug.org.au  Tue Mar 13 04:21:37 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Tue, 13 Mar 2012 19:21:37 +1100
Subject: linux-next: manual merge of the arm-soc tree with the omap_dss2 tree
Message-ID: <20120313192137.613a8bd8888c07597cba6307@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-omap1/board-ams-delta.c between commit ddba6c7f7ec6
("OMAP1: pass LCD config with omapfb_set_lcd_config()") from the
omap_dss2 tree and commits 2e3ee9f45b3c ("ARM: OMAP1: Move most of
plat/io.h into local iomap.h") and several others from the arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-omap1/board-ams-delta.c
index e0e8245,7dd3099..0000000
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@@ -18,9 -19,12 +19,13 @@@
  #include <linux/interrupt.h>
  #include <linux/leds.h>
  #include <linux/platform_device.h>
+ #include <linux/regulator/consumer.h>
+ #include <linux/regulator/fixed.h>
+ #include <linux/regulator/machine.h>
  #include <linux/serial_8250.h>
  #include <linux/export.h>
 +#include <linux/omapfb.h>
+ #include <linux/io.h>
  
  #include <media/soc_camera.h>
  
@@@ -170,6 -165,151 +166,147 @@@ static struct omap_usb_config ams_delta
  	.pins[0]	= 2,
  };
  
 -static struct omap_board_config_kernel ams_delta_config[] __initdata = {
 -	{ OMAP_TAG_LCD,		&ams_delta_lcd_config },
 -};
 -
+ #define LATCH1_GPIO_BASE	232
+ #define LATCH1_NGPIO		8
+ 
+ static struct resource latch1_resources[] = {
+ 	[0] = {
+ 		.name	= "dat",
+ 		.start	= LATCH1_PHYS,
+ 		.end	= LATCH1_PHYS + (LATCH1_NGPIO - 1) / 8,
+ 		.flags	= IORESOURCE_MEM,
+ 	},
+ };
+ 
+ static struct bgpio_pdata latch1_pdata = {
+ 	.base	= LATCH1_GPIO_BASE,
+ 	.ngpio	= LATCH1_NGPIO,
+ };
+ 
+ static struct platform_device latch1_gpio_device = {
+ 	.name		= "basic-mmio-gpio",
+ 	.id		= 0,
+ 	.resource	= latch1_resources,
+ 	.num_resources	= ARRAY_SIZE(latch1_resources),
+ 	.dev		= {
+ 		.platform_data	= &latch1_pdata,
+ 	},
+ };
+ 
+ static struct resource latch2_resources[] = {
+ 	[0] = {
+ 		.name	= "dat",
+ 		.start	= LATCH2_PHYS,
+ 		.end	= LATCH2_PHYS + (AMS_DELTA_LATCH2_NGPIO - 1) / 8,
+ 		.flags	= IORESOURCE_MEM,
+ 	},
+ };
+ 
+ static struct bgpio_pdata latch2_pdata = {
+ 	.base	= AMS_DELTA_LATCH2_GPIO_BASE,
+ 	.ngpio	= AMS_DELTA_LATCH2_NGPIO,
+ };
+ 
+ static struct platform_device latch2_gpio_device = {
+ 	.name		= "basic-mmio-gpio",
+ 	.id		= 1,
+ 	.resource	= latch2_resources,
+ 	.num_resources	= ARRAY_SIZE(latch2_resources),
+ 	.dev		= {
+ 		.platform_data	= &latch2_pdata,
+ 	},
+ };
+ 
+ static const struct gpio latch_gpios[] __initconst = {
+ 	{
+ 		.gpio	= LATCH1_GPIO_BASE + 6,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "dockit1",
+ 	},
+ 	{
+ 		.gpio	= LATCH1_GPIO_BASE + 7,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "dockit2",
+ 	},
+ 	{
+ 		.gpio	= AMS_DELTA_GPIO_PIN_SCARD_RSTIN,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "scard_rstin",
+ 	},
+ 	{
+ 		.gpio	= AMS_DELTA_GPIO_PIN_SCARD_CMDVCC,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "scard_cmdvcc",
+ 	},
+ 	{
+ 		.gpio	= AMS_DELTA_GPIO_PIN_MODEM_CODEC,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "modem_codec",
+ 	},
+ 	{
+ 		.gpio	= AMS_DELTA_LATCH2_GPIO_BASE + 14,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "hookflash1",
+ 	},
+ 	{
+ 		.gpio	= AMS_DELTA_LATCH2_GPIO_BASE + 15,
+ 		.flags	= GPIOF_OUT_INIT_LOW,
+ 		.label	= "hookflash2",
+ 	},
+ };
+ 
+ static struct regulator_consumer_supply modem_nreset_consumers[] = {
+ 	REGULATOR_SUPPLY("RESET#", "serial8250.1"),
+ 	REGULATOR_SUPPLY("POR", "cx20442-codec"),
+ };
+ 
+ static struct regulator_init_data modem_nreset_data = {
+ 	.constraints		= {
+ 		.valid_ops_mask		= REGULATOR_CHANGE_STATUS,
+ 		.boot_on		= 1,
+ 	},
+ 	.num_consumer_supplies	= ARRAY_SIZE(modem_nreset_consumers),
+ 	.consumer_supplies	= modem_nreset_consumers,
+ };
+ 
+ static struct fixed_voltage_config modem_nreset_config = {
+ 	.supply_name		= "modem_nreset",
+ 	.microvolts		= 3300000,
+ 	.gpio			= AMS_DELTA_GPIO_PIN_MODEM_NRESET,
+ 	.startup_delay		= 25000,
+ 	.enable_high		= 1,
+ 	.enabled_at_boot	= 1,
+ 	.init_data		= &modem_nreset_data,
+ };
+ 
+ static struct platform_device modem_nreset_device = {
+ 	.name	= "reg-fixed-voltage",
+ 	.id	= -1,
+ 	.dev	= {
+ 		.platform_data	= &modem_nreset_config,
+ 	},
+ };
+ 
+ struct modem_private_data {
+ 	struct regulator *regulator;
+ };
+ 
+ static struct modem_private_data modem_priv;
+ 
+ void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value)
+ {
+ 	int bit = 0;
+ 	u16 bitpos = 1 << bit;
+ 
+ 	for (; bit < ngpio; bit++, bitpos = bitpos << 1) {
+ 		if (!(mask & bitpos))
+ 			continue;
+ 		else
+ 			gpio_set_value(base + bit, (value & bitpos) != 0);
+ 	}
+ }
+ EXPORT_SYMBOL(ams_delta_latch_write);
+ 
  static struct resource ams_delta_nand_resources[] = {
  	[0] = {
  		.start	= OMAP1_MPUIO_BASE,
@@@ -316,14 -496,28 +491,30 @@@ static void __init ams_delta_init(void
  	ams_delta_init_fiq();
  
  	omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
 +
 +	omapfb_set_lcd_config(&ams_delta_lcd_config);
  }
  
+ static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
+ {
+ 	struct modem_private_data *priv = port->private_data;
+ 
+ 	if (IS_ERR(priv->regulator))
+ 		return;
+ 
+ 	if (state == old)
+ 		return;
+ 
+ 	if (state == 0)
+ 		regulator_enable(priv->regulator);
+ 	else if (old == 0)
+ 		regulator_disable(priv->regulator);
+ }
+ 
  static struct plat_serial8250_port ams_delta_modem_ports[] = {
  	{
- 		.membase	= IOMEM(AMS_DELTA_MODEM_VIRT),
- 		.mapbase	= AMS_DELTA_MODEM_PHYS,
+ 		.membase	= IOMEM(MODEM_VIRT),
+ 		.mapbase	= MODEM_PHYS,
  		.irq		= -EINVAL, /* changed later */
  		.flags		= UPF_BOOT_AUTOCONF,
  		.irqflags	= IRQF_TRIGGER_RISING,
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From charu at ti.com  Tue Mar 13 04:21:41 2012
From: charu at ti.com (Varadarajan, Charulatha)
Date: Tue, 13 Mar 2012 13:51:41 +0530
Subject: [PATCH v2 5/5] ARM: OMAP2+: clean up some cppcheck warnings
In-Reply-To: <alpine.DEB.2.00.1203130211300.22211@utopia.booyaka.com>
References: <20120312224006.4103.29464.stgit@dusk>
 <20120312224257.4103.11096.stgit@dusk>
 <alpine.DEB.2.00.1203130211300.22211@utopia.booyaka.com>
Message-ID: <CA+HSevoVd-pU968DxMsYtHw58gUid9pAyY8gp1u1NdOc3orTzA@mail.gmail.com>

On Tue, Mar 13, 2012 at 13:42, Paul Walmsley <paul at pwsan.com> wrote:
>
>
> Resolve some warnings identified by cppcheck in arch/arm/mach-omap2:
>
> ? ?[arch/arm/mach-omap2/usb-tusb6010.c:129]: (style) Checking if unsigned
> variable 'tmp' is less than zero.
> ? ?[arch/arm/mach-omap2/prm_common.c:241]: (error) Possible null pointer
> dereference: irq_setup - otherwise it is redundant to check if irq_setup is
> null at line 247
> ? ?[arch/arm/mach-omap2/pm34xx.c:790]: (style) Variable 'per_clkdm' is
> assigned a value that is never used
> ? ?[arch/arm/mach-omap2/pm34xx.c:790]: (style) Variable 'core_clkdm' is
> assigned a value that is never used
> ? ?[arch/arm/mach-omap2/pm24xx.c:185]: (style) Variable 'only_idle' is
> assigned a value that is never used
> ? ?[arch/arm/mach-omap2/mux.c:254]: (error) Possible null pointer
> dereference: mux
> ? ?[arch/arm/mach-omap2/mux.c:258]: (error) Possible null pointer
> dereference: mux
> ? ?[arch/arm/mach-omap2/gpmc-onenand.c:178]: (style) Variable 'tick_ns' is
> assigned a value that is never used
> ? ?[arch/arm/mach-omap2/gpio.c:56]: (error) Possible null pointer
> dereference: pdata - otherwise it is redundant to check if pdata is null at
> line 57
> ? ?[arch/arm/mach-omap2/devices.c:45]: (style) Variable 'l' is assigned a
> value that is never used
> ? ?[arch/arm/mach-omap2/board-am3517evm.c:134]: (style) Variable 'regval'
> is assigned a value that is never used
>
> Some of them are pretty good catches, such the gpio.c:56 and
> usb-tusb6010.c:129.
>
> Thanks to Jarkko Nikula for some comments on the sscanf() warnings.
> It seems that the kernel sscanf() ignores the field width anyway for the
> %d format, so those changes have been dropped from this second version.
>
> Signed-off-by: Paul Walmsley <paul at pwsan.com>
> Cc: Felipe Balbi <balbi at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Peter Ujfalusi <peter.ujfalusi at ti.com>
> Cc: Jarkko Nikula <jarkko.nikula at bitmer.com>
> Cc: Charulatha Varadarajan <charu at ti.com>
> ---
> ?arch/arm/mach-omap2/board-am3517evm.c | ? ?6 +-----
> ?arch/arm/mach-omap2/board-omap3evm.c ?| ? ?8 ++++----
> ?arch/arm/mach-omap2/devices.c ? ? ? ? | ? ?3 +--
> ?arch/arm/mach-omap2/gpio.c ? ? ? ? ? ?| ? ?2 +-
> ?arch/arm/mach-omap2/gpmc-onenand.c ? ?| ? ?3 +--
> ?arch/arm/mach-omap2/mux.c ? ? ? ? ? ? | ? ?2 +-
> ?arch/arm/mach-omap2/pm24xx.c ? ? ? ? ?| ? ?3 ---
> ?arch/arm/mach-omap2/pm34xx.c ? ? ? ? ?| ? ?4 +---
> ?arch/arm/mach-omap2/prm_common.c ? ? ?| ? ?4 +++-
> ?arch/arm/mach-omap2/usb-tusb6010.c ? ?| ? ?2 +-
> ?10 files changed, 14 insertions(+), 23 deletions(-)
>

[snip]

> diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
> index 8cbfbc2..2803ff8 100644
> --- a/arch/arm/mach-omap2/gpio.c
> +++ b/arch/arm/mach-omap2/gpio.c
> @@ -54,7 +54,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh,
> void *unused)
> ? ? ? ?pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
>
> ? ? ? ?pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs),
> GFP_KERNEL);
> - ? ? ? if (!pdata) {
> + ? ? ? if (!pdata->regs) {
> ? ? ? ? ? ? ? ?pr_err("gpio%d: Memory allocation failed\n", id);
> ? ? ? ? ? ? ? ?return -ENOMEM;
> ? ? ? ?}

Reviewed-by: Charulatha Varadarajan <charu at ti.com>


From sfr at canb.auug.org.au  Tue Mar 13 04:28:44 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Tue, 13 Mar 2012 19:28:44 +1100
Subject: linux-next: manual merge of the arm-soc tree with the sound tree
Message-ID: <20120313192844.34278a4baa0b475391191d40@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-omap2/board-omap4panda.c between commit 3c90c98a1ebb
("OMAP4: omap4panda: Enable audio support") from the sound tree and
commit 65f19159ddc4 ("ARM: OMAP: enable Bluetooth on the PandaBoard")
from the arm-soc tree.

Just context changes.  I fixed it up (see below) and can carry the fix as
necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-omap2/board-omap4panda.c
index e441591,3f3055d..0000000
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@@ -92,34 -91,15 +92,40 @@@ static struct platform_device leds_gpi
  	},
  };
  
 +static struct omap_abe_twl6040_data panda_abe_audio_data = {
 +	/* Audio out */
 +	.has_hs		= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
 +	/* HandsFree through expasion connector */
 +	.has_hf		= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
 +	/* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */
 +	.has_aux	= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
 +	/* PandaBoard: FM RX, PandaBoardES: audio in */
 +	.has_afm	= ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
 +	/* No jack detection. */
 +	.jack_detection	= 0,
 +	/* MCLK input is 38.4MHz */
 +	.mclk_freq	= 38400000,
 +
 +};
 +
 +static struct platform_device panda_abe_audio = {
 +	.name		= "omap-abe-twl6040",
 +	.id		= -1,
 +	.dev = {
 +		.platform_data = &panda_abe_audio_data,
 +	},
 +};
 +
+ static struct platform_device btwilink_device = {
+ 	.name	= "btwilink",
+ 	.id	= -1,
+ };
+ 
  static struct platform_device *panda_devices[] __initdata = {
  	&leds_gpio,
  	&wl1271_device,
 +	&panda_abe_audio,
+ 	&btwilink_device,
  };
  
  static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
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From vinod.koul at intel.com  Tue Mar 13 04:40:36 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Tue, 13 Mar 2012 14:10:36 +0530
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <1331569438.1727.3.camel@vkoul-udesk3>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <1331128466.24656.421.camel@vkoul-udesk3>
 <20120312161143.GA10830@n2100.arm.linux.org.uk>
 <1331569438.1727.3.camel@vkoul-udesk3>
Message-ID: <1331628036.1727.22.camel@vkoul-udesk3>

On Mon, 2012-03-12 at 21:53 +0530, Vinod Koul wrote:
> > > I applied the v2 on a branch and also rebased on top of
> slave-dma.next.
> > > There were few conflicts in imx-dma.c. Sacha, Javier, pls see that
> merge
> > > is right.
> > > 
> > > This branch (rmk_cookie_fixes2_rebased) is not yet pushed, as I am
> not
> > > able to connect to infradead.org, should be done when server is
> back.
> > 
> > Are you going to pick up Shawn Guo's tested-by for these patches, or
> are
> > we saying its too late for that now?
> Sure, his and others we have received on this series.
> Also, IIRC there was one fixup from Jassi on pl330?
> 
> I should be able to merge this tomorrow, if thats fine with you. 
I have merged this to my next, but haven't pushed out yet. This is
available on branch next_cookie2_merge.
Also I got few (more than expected build failures) and a merge issue on
imx driver. Sascha, Russell can you see if fix on imx is right

Please see if the below patch is the right fix for build failures in
addition to one suggested by Jassi.

-------------------x-------------------------x----------------------

>From 949ff5b8d46b5e3435d21b2651ce3a2599208d44 Mon Sep 17 00:00:00 2001
From: Vinod Koul <vinod.koul at linux.intel.com>
Date: Tue, 13 Mar 2012 11:58:12 +0530
Subject: [PATCH] dmaengine: fix for cookie changes and merge

Fixed trivial issues in drivers:
	drivers/dma/imx-sdma.c
	drivers/dma/intel_mid_dma.c
	drivers/dma/ioat/dma_v3.c
	drivers/dma/iop-adma.c
	drivers/dma/sirf-dma.c
	drivers/dma/timb_dma.c

Signed-off-by: Vinod Koul <vinod.koul at linux.intel.com>
---
 drivers/dma/imx-sdma.c      |    1 +
 drivers/dma/intel_mid_dma.c |    1 +
 drivers/dma/ioat/dma_v3.c   |    1 +
 drivers/dma/iop-adma.c      |    1 +
 drivers/dma/sirf-dma.c      |    2 ++
 drivers/dma/timb_dma.c      |    6 +-----
 6 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index ccfc7c4..81f9d57 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1127,6 +1127,7 @@ static void sdma_issue_pending(struct dma_chan *chan)
 	struct sdma_engine *sdma = sdmac->sdma;
 
 	if (sdmac->status == DMA_IN_PROGRESS)
+		sdma_enable_channel(sdma, sdmac->channel);
 }
 
 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1	34
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index d599d96..2449812 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -477,6 +477,7 @@ static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
 						dma_cookie_t cookie,
 						struct dma_tx_state *txstate)
 {
+	struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
 	enum dma_status ret;
 
 	ret = dma_cookie_status(chan, cookie, txstate);
diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
index 145eda2..2c4476c 100644
--- a/drivers/dma/ioat/dma_v3.c
+++ b/drivers/dma/ioat/dma_v3.c
@@ -61,6 +61,7 @@
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
 #include <linux/prefetch.h>
+#include "../dmaengine.h"
 #include "registers.h"
 #include "hw.h"
 #include "dma.h"
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index 1f3a703..4499f88 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -894,6 +894,7 @@ static enum dma_status iop_adma_status(struct dma_chan *chan,
 					struct dma_tx_state *txstate)
 {
 	struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
+	int ret;
 
 	ret = dma_cookie_status(chan, cookie, txstate);
 	if (ret == DMA_SUCCESS)
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index a2cde85..45ba352 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -18,6 +18,8 @@
 #include <linux/of_platform.h>
 #include <linux/sirfsoc_dma.h>
 
+#include "dmaengine.h"
+
 #define SIRFSOC_DMA_DESCRIPTORS                 16
 #define SIRFSOC_DMA_CHANNELS                    16
 
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index 7805996..d408c22 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -510,17 +510,13 @@ static void td_free_chan_resources(struct dma_chan *chan)
 static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 				    struct dma_tx_state *txstate)
 {
-	struct timb_dma_chan *td_chan =
-		container_of(chan, struct timb_dma_chan, chan);
 	enum dma_status ret;
 
 	dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
 
 	ret = dma_cookie_status(chan, cookie, txstate);
 
-	dev_dbg(chan2dev(chan),
-		"%s: exit, ret: %d, last_complete: %d, last_used: %d\n",
-		__func__, ret, last_complete, last_used);
+	dev_dbg(chan2dev(chan), "%s: exit, ret: %d\n", 	__func__, ret);
 
 	return ret;
 }
-- 
1.7.0.4




-- 
~Vinod



From sfr at canb.auug.org.au  Tue Mar 13 04:36:41 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Tue, 13 Mar 2012 19:36:41 +1100
Subject: linux-next: manual merge of the arm-soc tree with the arm tree
Message-ID: <20120313193641.674b271a134d9dba201cd644@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-ux500/timer.c between commit 8eed6eac103b ("ARM: ux500:
convert to twd_local_timer_register() interface") from the arm tree and
commit b9576623c421 ("ARM: plat-nomadik: get rid of global mtu base
pointer") from the arm-soc tree.

I fixed it up (I think - see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-ux500/timer.c
index cadf982,fd00024..0000000
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@@ -15,38 -15,22 +15,39 @@@
  #include <mach/setup.h>
  #include <mach/hardware.h>
  
 +#ifdef CONFIG_HAVE_ARM_TWD
 +static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer,
 +			      U5500_TWD_BASE, IRQ_LOCALTIMER);
 +static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
 +			      U8500_TWD_BASE, IRQ_LOCALTIMER);
 +
 +static void __init ux500_twd_init(void)
 +{
 +	struct twd_local_timer *twd_local_timer;
 +	int err;
 +
 +	twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer :
 +					   &u8500_twd_local_timer;
 +
 +	err = twd_local_timer_register(twd_local_timer);
 +	if (err)
 +		pr_err("twd_local_timer_register failed %d\n", err);
 +}
 +#else
 +#define ux500_twd_init()	do { } while(0)
 +#endif
 +
  static void __init ux500_timer_init(void)
  {
+ 	void __iomem *mtu_timer_base;
  	void __iomem *prcmu_timer_base;
 +	int err;
  
  	if (cpu_is_u5500()) {
- 		mtu_base = __io_address(U5500_MTU0_BASE);
 -#ifdef CONFIG_LOCAL_TIMERS
 -		twd_base = __io_address(U5500_TWD_BASE);
 -#endif
+ 		mtu_timer_base = __io_address(U5500_MTU0_BASE);
  		prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
  	} else if (cpu_is_u8500()) {
- 		mtu_base = __io_address(U8500_MTU0_BASE);
 -#ifdef CONFIG_LOCAL_TIMERS
 -		twd_base = __io_address(U8500_TWD_BASE);
 -#endif
+ 		mtu_timer_base = __io_address(U8500_MTU0_BASE);
  		prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
  	} else {
  		ux500_unknown_soc();
@@@ -69,9 -53,8 +70,9 @@@
  	 *
  	 */
  
- 	nmdk_timer_init();
+ 	nmdk_timer_init(mtu_timer_base);
  	clksrc_dbx500_prcmu_init(prcmu_timer_base);
 +	ux500_twd_init();
  }
  
  static void ux500_timer_reset(void)
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From sfr at canb.auug.org.au  Tue Mar 13 04:42:43 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Tue, 13 Mar 2012 19:42:43 +1100
Subject: linux-next: manual merge of the arm-soc tree with the arm tree
Message-ID: <20120313194243.4b330327115d48b34bc556c4@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-vexpress/ct-ca9x4.c between commit e9f07fbc5f5b ("ARM:
plat-versatile: convert to twd_local_timer_register() interface") from
the arm tree and commit 98ed4ceb93ba ("ARM: vexpress: Get rid of
MMIO_P2V") from the arm-soc tree.

I fixed it up (I think - see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-vexpress/ct-ca9x4.c
index b391538,73791f0..0000000
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@@ -54,44 -42,17 +42,28 @@@ static struct map_desc ct_ca9x4_io_desc
  static void __init ct_ca9x4_map_io(void)
  {
  	iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 -#ifdef CONFIG_LOCAL_TIMERS
 -	twd_base = ioremap(A9_MPCORE_TWD, SZ_32);
 -#endif
  }
  
 +#ifdef CONFIG_HAVE_ARM_TWD
 +static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
 +
 +static void __init ca9x4_twd_init(void)
 +{
 +	int err = twd_local_timer_register(&twd_local_timer);
 +	if (err)
 +		pr_err("twd_local_timer_register failed %d\n", err);
 +}
 +#else
 +#define ca9x4_twd_init()	do {} while(0)
 +#endif
 +
  static void __init ct_ca9x4_init_irq(void)
  {
- 	gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
- 		 MMIO_P2V(A9_MPCORE_GIC_CPU));
+ 	gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
+ 		 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
 +	ca9x4_twd_init();
  }
  
- #if 0
- static void __init ct_ca9x4_timer_init(void)
- {
- 	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
- 	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
- 
- 	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
- 	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
- 		"ct-timer0");
- }
- 
- static struct sys_timer ct_ca9x4_timer = {
- 	.init	= ct_ca9x4_timer_init,
- };
- #endif
- 
  static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
  {
  	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
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From paul at pwsan.com  Tue Mar 13 04:44:21 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 13 Mar 2012 02:44:21 -0600 (MDT)
Subject: [PATCH v3 5/5] ARM: OMAP2+: clean up some cppcheck warnings
In-Reply-To: <alpine.DEB.2.00.1203130211300.22211@utopia.booyaka.com>
References: <20120312224006.4103.29464.stgit@dusk>
 <20120312224257.4103.11096.stgit@dusk>
 <alpine.DEB.2.00.1203130211300.22211@utopia.booyaka.com>
Message-ID: <alpine.DEB.2.00.1203130243030.22211@utopia.booyaka.com>


Resolve some warnings identified by cppcheck in arch/arm/mach-omap2:

    [arch/arm/mach-omap2/usb-tusb6010.c:129]: (style) Checking if unsigned variable 'tmp' is less than zero.
    [arch/arm/mach-omap2/prm_common.c:241]: (error) Possible null pointer dereference: irq_setup - otherwise it is redundant to check if irq_setup is null at line 247
    [arch/arm/mach-omap2/pm34xx.c:790]: (style) Variable 'per_clkdm' is assigned a value that is never used
    [arch/arm/mach-omap2/pm34xx.c:790]: (style) Variable 'core_clkdm' is assigned a value that is never used
    [arch/arm/mach-omap2/pm24xx.c:185]: (style) Variable 'only_idle' is assigned a value that is never used
    [arch/arm/mach-omap2/mux.c:254]: (error) Possible null pointer dereference: mux
    [arch/arm/mach-omap2/mux.c:258]: (error) Possible null pointer dereference: mux
    [arch/arm/mach-omap2/gpmc-onenand.c:178]: (style) Variable 'tick_ns' is assigned a value that is never used
    [arch/arm/mach-omap2/gpio.c:56]: (error) Possible null pointer dereference: pdata - otherwise it is redundant to check if pdata is null at line 57
    [arch/arm/mach-omap2/devices.c:45]: (style) Variable 'l' is assigned a value that is never used
    [arch/arm/mach-omap2/board-am3517evm.c:134]: (style) Variable 'regval' is assigned a value that is never used
    [arch/arm/mach-omap2/board-omap3evm.c:641] -> [arch/arm/mach-omap2/board-omap3evm.c:639]: (style) Found duplicate branches for if and else.

Some of them are pretty good catches, such the gpio.c:56 and
usb-tusb6010.c:129.

Thanks to Jarkko Nikula for some comments on the sscanf() warnings.
It seems that the kernel sscanf() ignores the field width anyway for the
%d format, so those changes have been dropped from this second version.

Thanks to Daniel Marjam?ki <daniel.marjamaki at gmail.com> for pointing
out that a variable was unnecessarily marked static in the 
board-omap3evm.c change.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Peter Ujfalusi <peter.ujfalusi at ti.com>
Cc: Jarkko Nikula <jarkko.nikula at bitmer.com>
Cc: Charulatha Varadarajan <charu at ti.com>
Cc: Daniel Marjam?ki <daniel.marjamaki at gmail.com>
Reviewed-by: Charulatha Varadarajan <charu at ti.com> # for gpio.c
---
 arch/arm/mach-omap2/board-am3517evm.c |    6 +-----
 arch/arm/mach-omap2/board-omap3evm.c  |    8 ++++----
 arch/arm/mach-omap2/devices.c         |    3 +--
 arch/arm/mach-omap2/gpio.c            |    2 +-
 arch/arm/mach-omap2/gpmc-onenand.c    |    3 +--
 arch/arm/mach-omap2/mux.c             |    2 +-
 arch/arm/mach-omap2/pm24xx.c          |    3 ---
 arch/arm/mach-omap2/pm34xx.c          |    4 +---
 arch/arm/mach-omap2/prm_common.c      |    4 +++-
 arch/arm/mach-omap2/usb-tusb6010.c    |    2 +-
 10 files changed, 14 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 4b1cfe3..24b1f9a 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -150,13 +150,9 @@ static void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
 	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 	regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
 	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
-	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-
-	return ;
+	omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
 }
 
-
-
 #define LCD_PANEL_PWR		176
 #define LCD_PANEL_BKLIGHT_PWR	182
 #define LCD_PANEL_PWM		181
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c877236..7a45d1e 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -634,12 +634,12 @@ static void __init omap3_evm_wl12xx_init(void)
 
 static void __init omap3_evm_init(void)
 {
+	struct omap_board_mux *obm;
+
 	omap3_evm_get_revision();
 
-	if (cpu_is_omap3630())
-		omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
-	else
-		omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
+	obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
+	omap3_mux_init(obm, OMAP_PACKAGE_CBB);
 
 	omap_board_config = omap3_evm_config;
 	omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 283d11e..b52cd16 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -42,7 +42,6 @@
 
 static int __init omap3_l3_init(void)
 {
-	int l;
 	struct omap_hwmod *oh;
 	struct platform_device *pdev;
 	char oh_name[L3_MODULES_MAX_LEN];
@@ -54,7 +53,7 @@ static int __init omap3_l3_init(void)
 	if (!(cpu_is_omap34xx()))
 		return -ENODEV;
 
-	l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
+	snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
 
 	oh = omap_hwmod_lookup(oh_name);
 
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 8cbfbc2..2803ff8 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -54,7 +54,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 	pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
 
 	pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
-	if (!pdata) {
+	if (!pdata->regs) {
 		pr_err("gpio%d: Memory allocation failed\n", id);
 		return -ENOMEM;
 	}
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 5cdce10..6ab726f 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -175,7 +175,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 	const int t_wpl  = 40;
 	const int t_wph  = 30;
 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
-	int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
+	int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
 	int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
 	int err, ticks_cez;
 	int cs = cfg->cs, freq = *freq_ptr;
@@ -239,7 +239,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 		break;
 	}
 
-	tick_ns = gpmc_ticks_to_ns(1);
 	div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
 	gpmc_clk_ns = gpmc_ticks_to_ns(div);
 	if (gpmc_clk_ns < 15) /* >66Mhz */
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 611a0e3..552225a 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -248,7 +248,7 @@ int omap_mux_init_signal(const char *muxname, int val)
 	int mux_mode;
 
 	mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
-	if (mux_mode < 0)
+	if (mux_mode < 0 || !mux)
 		return mux_mode;
 
 	old_mode = omap_mux_read(partition, mux->reg_offset);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 23de98d..b3a4765 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -182,8 +182,6 @@ static int omap2_allow_mpu_retention(void)
 
 static void omap2_enter_mpu_retention(void)
 {
-	int only_idle = 0;
-
 	/* Putting MPU into the WFI state while a transfer is active
 	 * seems to cause the I2C block to timeout. Why? Good question. */
 	if (omap2_i2c_active())
@@ -206,7 +204,6 @@ static void omap2_enter_mpu_retention(void)
 
 		omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 						 OMAP2_PM_PWSTCTRL);
-		only_idle = 1;
 	}
 
 	omap2_sram_idle();
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc69875..0b65785 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -787,7 +787,7 @@ static void __init pm_errata_configure(void)
 static int __init omap3_pm_init(void)
 {
 	struct power_state *pwrst, *tmp;
-	struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
+	struct clockdomain *neon_clkdm, *mpu_clkdm;
 	int ret;
 
 	if (!cpu_is_omap34xx())
@@ -841,8 +841,6 @@ static int __init omap3_pm_init(void)
 
 	neon_clkdm = clkdm_lookup("neon_clkdm");
 	mpu_clkdm = clkdm_lookup("mpu_clkdm");
-	per_clkdm = clkdm_lookup("per_clkdm");
-	core_clkdm = clkdm_lookup("core_clkdm");
 
 #ifdef CONFIG_SUSPEND
 	suspend_set_ops(&omap_pm_ops);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 860118a..c7c7373 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -238,7 +238,7 @@ void omap_prcm_irq_complete(void)
  */
 int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 {
-	int nr_regs = irq_setup->nr_regs;
+	int nr_regs;
 	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
 	int offset, i;
 	struct irq_chip_generic *gc;
@@ -247,6 +247,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 	if (!irq_setup)
 		return -EINVAL;
 
+	nr_regs = irq_setup->nr_regs;
+
 	if (prcm_irq_setup) {
 		pr_err("PRCM: already initialized; won't reinitialize\n");
 		return -EINVAL;
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 994d8f5..db84a46 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -126,7 +126,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
 	tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
 	if (tmp > 4)
 		return -ERANGE;
-	if (tmp <= 0)
+	if (tmp == 0)
 		tmp = 1;
 	t.page_burst_access = (fclk_ps * tmp) / 1000;
 
-- 
1.7.9.1

From b29396 at freescale.com  Tue Mar 13 04:47:03 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 13 Mar 2012 16:47:03 +0800
Subject: [PATCH v1 0/5] dt: add basic imx28 support
Message-ID: <1331628428-24017-1-git-send-email-b29396@freescale.com>

This patch series adds basic imx28 dt support including fec, mmc and dma.

Tested on mx28evk.

TODO:
Convert the remaining devices to support dt.
mxs-auart, mxs-gpio, i2c, flexcan, saif, rtc, pwm, fb.

Dong Aisheng (5):
  ARM: imx28: add basic dt support
  mmc: mxs-mmc: add dt probe support
  ARM: imx28evk: add mmc dt support
  dma: mxs-dma: add dt probe support
  ARM: mxs: add mxs dma dt support

 Documentation/devicetree/bindings/arm/fsl.txt      |    4 +
 .../devicetree/bindings/dma/fsl-mxs-dma.txt        |   17 +++
 .../devicetree/bindings/mmc/fsl-mxs-mmc.txt        |   23 ++++
 arch/arm/boot/dts/imx28-evk.dts                    |   45 +++++++
 arch/arm/boot/dts/imx28.dtsi                       |  131 ++++++++++++++++++++
 arch/arm/mach-mxs/Kconfig                          |    9 ++
 arch/arm/mach-mxs/Makefile                         |    1 +
 arch/arm/mach-mxs/devices-mx23.h                   |    2 +
 arch/arm/mach-mxs/devices-mx28.h                   |    2 +
 arch/arm/mach-mxs/devices/platform-dma.c           |    3 +-
 arch/arm/mach-mxs/imx28-dt.c                       |   71 +++++++++++
 arch/arm/mach-mxs/include/mach/devices-common.h    |    3 +
 arch/arm/mach-mxs/mach-apx4devkit.c                |    1 +
 arch/arm/mach-mxs/mach-m28evk.c                    |    1 +
 arch/arm/mach-mxs/mach-mx23evk.c                   |    1 +
 arch/arm/mach-mxs/mach-mx28evk.c                   |    1 +
 arch/arm/mach-mxs/mach-stmp378x_devb.c             |    1 +
 arch/arm/mach-mxs/mach-tx28.c                      |    1 +
 drivers/dma/mxs-dma.c                              |   44 +++++--
 drivers/mmc/host/mxs-mmc.c                         |   82 ++++++++++++-
 20 files changed, 424 insertions(+), 19 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
 create mode 100644 Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
 create mode 100644 arch/arm/boot/dts/imx28-evk.dts
 create mode 100644 arch/arm/boot/dts/imx28.dtsi
 create mode 100644 arch/arm/mach-mxs/imx28-dt.c




From b29396 at freescale.com  Tue Mar 13 04:47:05 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 13 Mar 2012 16:47:05 +0800
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <1331628428-24017-1-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
Message-ID: <1331628428-24017-3-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>

---
The patch is still using a private way for dma part binding
since the common dma binding is still under discussion.
http://www.spinics.net/lists/linux-omap/msg65528.html

Will update to use common dma binding when it hits mainline.
---
 .../devicetree/bindings/mmc/fsl-mxs-mmc.txt        |   23 ++++++
 drivers/mmc/host/mxs-mmc.c                         |   82 +++++++++++++++++++-
 2 files changed, 102 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
new file mode 100644
index 0000000..adc1142
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
@@ -0,0 +1,23 @@
+* FREESCALE MXS MMC peripheral
+
+Required properties:
+- compatible : Should be "fsl,<chip>-mmc"
+- reg : Should contain registers location and length
+- interrupts : Should contain interrupt.
+  The format is <irq_err irq_dma>.
+- dma_channel: Should contain the dma channel it uses
+
+Optional properties:
+- wp-gpios : Specify GPIOs for write protection
+- slot-4bit: Specify 4 bit mode support
+- slot-8bit: Specify 8 bit and 4 bit mode support
+
+Examples:
+mmc1: ssp at 80010000 {
+	compatible = "fsl,imx28-mmc";
+	reg = <0x80010000 2000>;
+	/* <irq_err irq_dma> */
+	interrupts = <96 82>;
+	dma_channel = <0>;
+	slot-8bit;
+};
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index 382c835..6cf2d17 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -38,6 +38,10 @@
 #include <linux/gpio.h>
 #include <linux/regulator/consumer.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/slab.h>
 
 #include <mach/mxs.h>
 #include <mach/common.h>
@@ -673,17 +677,79 @@ static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
 	return true;
 }
 
+#ifdef CONFIG_OF
+static struct resource * __devinit mxs_mmc_get_of_dmares(
+				struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *dmares;
+	int ret;
+
+	if (!np)
+		return NULL;
+
+	dmares = kzalloc(sizeof(*dmares), GFP_KERNEL);
+	dmares->flags = IORESOURCE_DMA;
+	ret = of_property_read_u32(np, "dma_channel", &dmares->start);
+	if (ret) {
+		dev_err(&pdev->dev, "unable to get dmares from dt\n");
+		return NULL;
+	}
+	dmares->end = dmares->start;
+
+	return dmares;
+}
+
+static int __devinit mxs_mmc_get_of_property(struct platform_device *pdev,
+				struct mxs_mmc_platform_data **ppdata)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct mxs_mmc_platform_data *pdata = *ppdata;
+
+	if (!np)
+		return -ENODEV;
+
+	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+
+	if (of_get_property(np, "slot-8bit", NULL))
+		pdata->flags |= SLOTF_8_BIT_CAPABLE;
+
+	if (of_get_property(np, "slot-4bit", NULL))
+		pdata->flags |= SLOTF_4_BIT_CAPABLE;
+
+	pdata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
+
+	dev_dbg(&pdev->dev, "wp-gpios %d flags %d\n", pdata->wp_gpio,
+		pdata->flags);
+
+	return 0;
+}
+#else
+static struct resource * __devinit mxs_mmc_get_of_dmares(
+				struct platform_device *pdev)
+{
+	return NULL;
+}
+static inline int mxs_mmc_get_of_property(struct platform_device *pdev,
+			struct mxs_mmc_platform_data *pdata)
+{
+	return -ENODEV;
+}
+#endif
+
 static int mxs_mmc_probe(struct platform_device *pdev)
 {
 	struct mxs_mmc_host *host;
 	struct mmc_host *mmc;
 	struct resource *iores, *dmares, *r;
-	struct mxs_mmc_platform_data *pdata;
+	struct mxs_mmc_platform_data *pdata = NULL;
 	int ret = 0, irq_err, irq_dma;
 	dma_cap_mask_t mask;
 
 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+	dmares = mxs_mmc_get_of_dmares(pdev);
+	if (dmares == NULL)
+		dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 	irq_err = platform_get_irq(pdev, 0);
 	irq_dma = platform_get_irq(pdev, 1);
 	if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
@@ -740,7 +806,9 @@ static int mxs_mmc_probe(struct platform_device *pdev)
 	mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
 		    MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
 
-	pdata =	mmc_dev(host->mmc)->platform_data;
+	mxs_mmc_get_of_property(pdev, &pdata);
+	if (pdata == NULL)
+		pdata =	mmc_dev(host->mmc)->platform_data;
 	if (pdata) {
 		if (pdata->flags & SLOTF_8_BIT_CAPABLE)
 			mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
@@ -851,6 +919,13 @@ static const struct dev_pm_ops mxs_mmc_pm_ops = {
 };
 #endif
 
+static const struct of_device_id mxs_mmc_dt_ids[] = {
+	{ .compatible = "fsl,imx23-mmc", .data = NULL, },
+	{ .compatible = "fsl,imx28-mmc", .data = NULL, },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
+
 static struct platform_driver mxs_mmc_driver = {
 	.probe		= mxs_mmc_probe,
 	.remove		= mxs_mmc_remove,
@@ -860,6 +935,7 @@ static struct platform_driver mxs_mmc_driver = {
 #ifdef CONFIG_PM
 		.pm	= &mxs_mmc_pm_ops,
 #endif
+		.of_match_table = mxs_mmc_dt_ids,
 	},
 };
 
-- 
1.7.0.4




From b29396 at freescale.com  Tue Mar 13 04:47:04 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 13 Mar 2012 16:47:04 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <1331628428-24017-1-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
Message-ID: <1331628428-24017-2-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

This patch includes basic dt support which can boot via nfs rootfs.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 Documentation/devicetree/bindings/arm/fsl.txt |    4 +
 arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
 arch/arm/boot/dts/imx28.dtsi                  |   88 +++++++++++++++++++++++++
 arch/arm/mach-mxs/Kconfig                     |    9 +++
 arch/arm/mach-mxs/Makefile                    |    1 +
 arch/arm/mach-mxs/imx28-dt.c                  |   67 +++++++++++++++++++
 6 files changed, 200 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 54bddda..9f21faf 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -1,6 +1,10 @@
 Freescale i.MX Platforms Device Tree Bindings
 -----------------------------------------------
 
+i.MX28 Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx28-evk", "fsl,imx28";
+
 i.MX51 Babbage Board
 Required root node properties:
     - compatible = "fsl,imx51-babbage", "fsl,imx51";
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
new file mode 100644
index 0000000..9758dc4
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+	model = "Freescale i.MX28 Evaluation Kit";
+	compatible = "fsl,imx28-evk", "fsl,imx28";
+
+	memory {
+		device_type = "memory";
+		reg = <0x40000000 0x08000000>;
+	};
+
+	ahb at 80080000 {
+		fec at 800f0000 {
+			phy-mode = "rmii";
+			local-mac-address = [00 04 9F 01 7D 5B];
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
new file mode 100644
index 0000000..acf0dab
--- /dev/null
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&icoll>;
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	apb at 80000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80000000 0x80000>;
+		ranges;
+
+		apbh at 80000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x80000000 0x3c900>;
+			ranges;
+
+			icoll: interrupt-controller at 80000000 {
+				compatible = "fsl,imx28-icoll";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x80000000 0x2000>;
+			};
+		};
+
+		apbx at 80040000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x80040000 0x40000>;
+			ranges;
+
+			uart1: uart at 80074000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x80074000 0x2000>;
+				interrupts = <47>;
+			};
+		};
+	};
+
+	ahb at 80080000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80080000 0x80000>;
+		ranges;
+
+		fec at 800f0000 {
+			compatible = "fsl,imx28-fec";
+			reg = <0x800f0000 0x4000>;
+			interrupts = <101>;
+			status = "disabled";
+		};
+
+		fec at 800f4000 {
+			compatible = "fsl,imx28-fec";
+			reg = <0x800f4000 0x4000>;
+			interrupts = <102>;
+			status = "disabled";
+		};
+
+	};
+};
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c57f996..6ab66af 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -17,6 +17,15 @@ config SOC_IMX28
 
 comment "MXS platforms:"
 
+config MACH_IMX28_DT
+	bool "Support i.MX28 platforms from device tree"
+	select SOC_IMX28
+	select USE_OF
+	select MACH_MX28EVK
+	help
+	  Include support for Freescale i.MX28 based platforms
+	  using the device tree for discovery
+
 config MACH_STMP378X_DEVB
 	bool "Support STMP378x_devb Platform"
 	select SOC_IMX23
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 908bf9a..25a4122 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
 obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
 obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
 
+obj-$(CONFIG_MACH_IMX28_DT) += imx28-dt.o
 obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
diff --git a/arch/arm/mach-mxs/imx28-dt.c b/arch/arm/mach-mxs/imx28-dt.c
new file mode 100644
index 0000000..78d1129
--- /dev/null
+++ b/arch/arm/mach-mxs/imx28-dt.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx28.h>
+
+static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
+	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
+	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
+	{ /* sentinel */ }
+};
+
+static void __init imx28_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     imx28_auxdata_lookup, NULL);
+}
+
+static const struct of_device_id icoll_of_match[] __initconst = {
+	{ .compatible = "fsl,imx28-icoll", },
+	{},
+};
+
+static void __init imx28_dt_init_irq(void)
+{
+	irq_domain_generate_simple(icoll_of_match, MX28_ICOLL_BASE_ADDR, 0);
+	mx28_init_irq();
+}
+
+static void __init imx28_timer_init(void)
+{
+	mx28_clocks_init();
+}
+
+static struct sys_timer imx28_timer = {
+	.init = imx28_timer_init,
+};
+
+static const char *imx28_dt_compat[] __initdata = {
+	"fsl,imx28-evk",
+	NULL,
+};
+
+DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
+	.map_io		= mx28_map_io,
+	.init_irq	= imx28_dt_init_irq,
+	.timer		= &imx28_timer,
+	.init_machine	= imx28_init,
+	.dt_compat	= imx28_dt_compat,
+	.restart	= mxs_restart,
+MACHINE_END
-- 
1.7.0.4




From b29396 at freescale.com  Tue Mar 13 04:47:06 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 13 Mar 2012 16:47:06 +0800
Subject: [PATCH v1 3/5] ARM: imx28evk: add mmc dt support
In-Reply-To: <1331628428-24017-1-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
Message-ID: <1331628428-24017-4-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx28-evk.dts |   14 ++++++++++++++
 arch/arm/boot/dts/imx28.dtsi    |   33 +++++++++++++++++++++++++++++++++
 arch/arm/mach-mxs/imx28-dt.c    |    2 ++
 3 files changed, 49 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 9758dc4..61350ab 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -21,6 +21,20 @@
 		reg = <0x40000000 0x08000000>;
 	};
 
+        apb at 80000000 {
+                apbh at 80000000 {
+			mmc1: ssp at 80010000 {
+				slot-8bit;
+				status = "okay";
+			};
+
+			mmc2: ssp at 80012000 {
+				slot-8bit;
+				status = "okay";
+			};
+		};
+	};
+
 	ahb at 80080000 {
 		fec at 800f0000 {
 			phy-mode = "rmii";
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index acf0dab..71c7bfb 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -46,6 +46,39 @@
 				#interrupt-cells = <1>;
 				reg = <0x80000000 0x2000>;
 			};
+
+			ssp at 80010000 {
+				compatible = "fsl,imx28-mmc";
+				reg = <0x80010000 2000>;
+				/* <irq_err irq_dma> */
+				interrupts = <96 82>;
+				dma_channel = <0>;
+				status = "disabled";
+			};
+
+			ssp at 80012000 {
+				compatible = "fsl,imx28-mmc";
+				reg = <0x80012000 2000>;
+				interrupts = <97 83>;
+				dma_channel = <1>;
+				status = "disabled";
+			};
+
+			ssp at 80014000 {
+				compatible = "fsl,imx28-mmc";
+				reg = <0x80014000 2000>;
+				interrupts = <98 84>;
+				dma_channel = <2>;
+				status = "disabled";
+			};
+
+			ssp at 80016000 {
+				compatible = "fsl,imx28-mmc";
+				reg = <0x80016000 2000>;
+				interrupts = <99 85>;
+				dma_channel = <3>;
+				status = "disabled";
+			};
 		};
 
 		apbx at 80040000 {
diff --git a/arch/arm/mach-mxs/imx28-dt.c b/arch/arm/mach-mxs/imx28-dt.c
index 78d1129..429b88e 100644
--- a/arch/arm/mach-mxs/imx28-dt.c
+++ b/arch/arm/mach-mxs/imx28-dt.c
@@ -23,6 +23,8 @@ static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
 	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
 	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
+	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP0_BASE_ADDR, "mxs-mmc.0", NULL),
+	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP1_BASE_ADDR, "mxs-mmc.1", NULL),
 	{ /* sentinel */ }
 };
 
-- 
1.7.0.4




From b29396 at freescale.com  Tue Mar 13 04:47:08 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 13 Mar 2012 16:47:08 +0800
Subject: [PATCH v1 5/5] ARM: mxs: add mxs dma dt support
In-Reply-To: <1331628428-24017-1-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
Message-ID: <1331628428-24017-6-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Originally the dma device will be added by default via
arch_initcall(mxs_add_mxs_dma);

Now change to call it explicitly in board file to avoid conflict
with device tree support.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 arch/arm/boot/dts/imx28.dtsi                    |   12 +++++++++++-
 arch/arm/mach-mxs/devices-mx23.h                |    2 ++
 arch/arm/mach-mxs/devices-mx28.h                |    2 ++
 arch/arm/mach-mxs/devices/platform-dma.c        |    3 +--
 arch/arm/mach-mxs/imx28-dt.c                    |    2 ++
 arch/arm/mach-mxs/include/mach/devices-common.h |    3 +++
 arch/arm/mach-mxs/mach-apx4devkit.c             |    1 +
 arch/arm/mach-mxs/mach-m28evk.c                 |    1 +
 arch/arm/mach-mxs/mach-mx23evk.c                |    1 +
 arch/arm/mach-mxs/mach-mx28evk.c                |    1 +
 arch/arm/mach-mxs/mach-stmp378x_devb.c          |    1 +
 arch/arm/mach-mxs/mach-tx28.c                   |    1 +
 12 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 71c7bfb..f0322e9 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -47,6 +47,11 @@
 				reg = <0x80000000 0x2000>;
 			};
 
+			dma-apbh at 80004000 {
+				compatible = "fsl,mxs-dma-apbh";
+				reg = <0x80004000 2000>;
+			};
+
 			ssp at 80010000 {
 				compatible = "fsl,imx28-mmc";
 				reg = <0x80010000 2000>;
@@ -79,7 +84,12 @@
 				dma_channel = <3>;
 				status = "disabled";
 			};
-		};
+
+			dma-apbx at 80024000 {
+				compatible = "fsl,mxs-dma-apbx";
+				reg = <0x80024000 2000>;
+			};
+                };
 
 		apbx at 80040000 {
 			compatible = "simple-bus";
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 3fa651d..721c91a 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -31,3 +31,5 @@ struct platform_device *__init mx23_add_mxsfb(
 		const struct mxsfb_platform_data *pdata);
 
 struct platform_device *__init mx23_add_rtc_stmp3xxx(void);
+
+#define mx23_add_dma()	mxs_add_mxs_dma()
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 4f50094..c0cfd4e 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -51,3 +51,5 @@ extern const struct mxs_saif_data mx28_saif_data[] __initconst;
 	mxs_add_saif(&mx28_saif_data[id], pdata)
 
 struct platform_device *__init mx28_add_rtc_stmp3xxx(void);
+
+#define mx28_add_dma()	mxs_add_mxs_dma()
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
index 6a0202b..57f851e 100644
--- a/arch/arm/mach-mxs/devices/platform-dma.c
+++ b/arch/arm/mach-mxs/devices/platform-dma.c
@@ -30,7 +30,7 @@ static struct platform_device *__init mxs_add_dma(const char *devid,
 				DMA_BIT_MASK(32));
 }
 
-static int __init mxs_add_mxs_dma(void)
+int __init mxs_add_mxs_dma(void)
 {
 	char *apbh = "mxs-dma-apbh";
 	char *apbx = "mxs-dma-apbx";
@@ -47,4 +47,3 @@ static int __init mxs_add_mxs_dma(void)
 
 	return 0;
 }
-arch_initcall(mxs_add_mxs_dma);
diff --git a/arch/arm/mach-mxs/imx28-dt.c b/arch/arm/mach-mxs/imx28-dt.c
index 429b88e..1c4d317 100644
--- a/arch/arm/mach-mxs/imx28-dt.c
+++ b/arch/arm/mach-mxs/imx28-dt.c
@@ -25,6 +25,8 @@ static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
 	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP0_BASE_ADDR, "mxs-mmc.0", NULL),
 	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP1_BASE_ADDR, "mxs-mmc.1", NULL),
+	OF_DEV_AUXDATA("fsl,mxs-dma-apbh", MX28_APBH_DMA_BASE_ADDR, "mxs-dma-apbh", NULL),
+	OF_DEV_AUXDATA("fsl,mxs-dma-apbx", MX28_APBX_DMA_BASE_ADDR, "mxs-dma-apbx", NULL),
 	{ /* sentinel */ }
 };
 
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index dc369c1..87939a2 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -106,3 +106,6 @@ struct mxs_saif_data {
 struct platform_device *__init mxs_add_saif(
 		const struct mxs_saif_data *data,
 		const struct mxs_saif_platform_data *pdata);
+
+/* dma */
+int __init mxs_add_mxs_dma(void);
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
index 48a7fab..92f47e9 100644
--- a/arch/arm/mach-mxs/mach-apx4devkit.c
+++ b/arch/arm/mach-mxs/mach-apx4devkit.c
@@ -210,6 +210,7 @@ static void __init apx4devkit_init(void)
 	mxs_iomux_setup_multiple_pads(apx4devkit_pads,
 			ARRAY_SIZE(apx4devkit_pads));
 
+	mx28_add_dma();
 	mx28_add_duart();
 	mx28_add_auart0();
 	mx28_add_auart1();
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
index 06d7996..9a74ce6 100644
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -321,6 +321,7 @@ static void __init m28evk_init(void)
 {
 	mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
 
+	mx28_add_dma();
 	mx28_add_duart();
 	mx28_add_auart0();
 	mx28_add_auart3();
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index 5ea1c57..cabc884 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -143,6 +143,7 @@ static void __init mx23evk_init(void)
 
 	mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
 
+	mx23_add_dma();
 	mx23_add_duart();
 	mx23_add_auart0();
 
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index e386c14..4b645eb 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -415,6 +415,7 @@ static void __init mx28evk_init(void)
 
 	mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
 
+	mx28_add_dma();
 	mx28_add_duart();
 	mx28_add_auart0();
 	mx28_add_auart3();
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
index a626c07..a391b9e 100644
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -88,6 +88,7 @@ static void __init stmp378x_dvb_init(void)
 	mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
 			ARRAY_SIZE(stmp378x_dvb_pads));
 
+	mx23_add_dma();
 	mx23_add_duart();
 	mx23_add_auart0();
 	mx23_add_rtc_stmp3xxx();
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
index 2c0862e..e17e262 100644
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -149,6 +149,7 @@ static void __init tx28_stk5v3_init(void)
 	mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
 			ARRAY_SIZE(tx28_stk5v3_pads));
 
+	mx28_add_dma();
 	mx28_add_duart(); /* UART1 */
 	mx28_add_auart(1); /* UART2 */
 
-- 
1.7.0.4




From b29396 at freescale.com  Tue Mar 13 04:47:07 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 13 Mar 2012 16:47:07 +0800
Subject: [PATCH v1 4/5] dma: mxs-dma: add dt probe support
In-Reply-To: <1331628428-24017-1-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
Message-ID: <1331628428-24017-5-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 .../devicetree/bindings/dma/fsl-mxs-dma.txt        |   17 ++++++++
 drivers/dma/mxs-dma.c                              |   44 +++++++++++++------
 2 files changed, 47 insertions(+), 14 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
new file mode 100644
index 0000000..cfa1730
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
@@ -0,0 +1,17 @@
+* Freescale MXS DMA
+
+Required properties:
+- compatible : Should be "fsl,mxs-dma-apbh" or "fsl,mxs-dma-apbx"
+- reg : Should contain registers location and length
+
+Examples:
+
+dma-apbh at 80004000 {
+	compatible = "fsl,mxs-dma-apbh";
+	reg = <0x80004000 2000>;
+};
+
+dma-apbx at 80024000 {
+	compatible = "fsl,mxs-dma-apbx";
+	reg = <0x80024000 2000>;
+};
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index b06cd4c..45e8d46 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -22,6 +22,9 @@
 #include <linux/platform_device.h>
 #include <linux/dmaengine.h>
 #include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 
 #include <asm/irq.h>
 #include <mach/mxs.h>
@@ -130,6 +133,25 @@ struct mxs_dma_engine {
 	struct mxs_dma_chan		mxs_chans[MXS_DMA_CHANNELS];
 };
 
+static struct platform_device_id mxs_dma_type[] = {
+	{
+		.name = "mxs-dma-apbh",
+		.driver_data = MXS_DMA_APBH,
+	}, {
+		.name = "mxs-dma-apbx",
+		.driver_data = MXS_DMA_APBX,
+	}, {
+		/* end of list */
+	}
+};
+
+static const struct of_device_id mxs_dma_dt_ids[] = {
+	{ .compatible = "fsl,mxs-dma-apbh", .data = &mxs_dma_type[0], },
+	{ .compatible = "fsl,mxs-dma-apbx", .data = &mxs_dma_type[1], },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
+
 static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
 {
 	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
@@ -587,8 +609,8 @@ err_out:
 
 static int __init mxs_dma_probe(struct platform_device *pdev)
 {
-	const struct platform_device_id *id_entry =
-				platform_get_device_id(pdev);
+	const struct platform_device_id *id_entry;
+	const struct of_device_id *of_id;
 	struct mxs_dma_engine *mxs_dma;
 	struct resource *iores;
 	int ret, i;
@@ -597,6 +619,11 @@ static int __init mxs_dma_probe(struct platform_device *pdev)
 	if (!mxs_dma)
 		return -ENOMEM;
 
+	of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev);
+	if (of_id)
+		id_entry = of_id->data;
+	else
+		id_entry = platform_get_device_id(pdev);
 	mxs_dma->dev_id = id_entry->driver_data;
 
 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -679,21 +706,10 @@ err_request_region:
 	return ret;
 }
 
-static struct platform_device_id mxs_dma_type[] = {
-	{
-		.name = "mxs-dma-apbh",
-		.driver_data = MXS_DMA_APBH,
-	}, {
-		.name = "mxs-dma-apbx",
-		.driver_data = MXS_DMA_APBX,
-	}, {
-		/* end of list */
-	}
-};
-
 static struct platform_driver mxs_dma_driver = {
 	.driver		= {
 		.name	= "mxs-dma",
+		.of_match_table = mxs_dma_dt_ids,
 	},
 	.id_table	= mxs_dma_type,
 };
-- 
1.7.0.4




From santosh.shilimkar at ti.com  Tue Mar 13 04:47:10 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Tue, 13 Mar 2012 14:17:10 +0530
Subject: [PATCH] ARM: OMAP4: Workaround the OCP synchronisation issue
 with 32K synctimer.
In-Reply-To: <87399d225f.fsf@ti.com>
References: <1331566388-2397-1-git-send-email-santosh.shilimkar@ti.com>
 <87399d225f.fsf@ti.com>
Message-ID: <4F5F098E.4040006@ti.com>

On Monday 12 March 2012 10:21 PM, Kevin Hilman wrote:
> Santosh Shilimkar <santosh.shilimkar at ti.com> writes:
> 
>> On OMAP4, recently a synchronisation bug is discovered by hardware
>> team, which leads to incorrect timer value read from 32K sync timer
>> IP when the IP is comming out of idle.
>>
>> The issue is due to the synchronization methodology used in the SYNCTIMER IP.
>> The value of the counter register in 32kHz domain is synchronized to the OCP
>> domain register only at count up event, and if the OCP clock is switched off,
>> the OCP register gets out of synch until the first count up event after the
>> clock is switched back -at the next falling edge of the 32kHz clock.
>>
>> Further investigation revealed that it applies to gptimer1 and watchdog timer2
>> as well which may run on 32KHz. This patch fixes the issue for all the
>> applicable modules.
> 
> The changelog describes the problem ver well, but doesn't actually
> describe the fix (enable static dep.)  Can you update the changelog do
> describe the fix, and why it fixes the problem.
> 
Sure. Updated patch below. The idea is to ensure that synctimer is
syncronised before software does any reads on the counter. The BUG
will get fixed in future OMAP designs

Attaching the patch in case thunderbird email client eats the tabs.

Regards
Santosh

>From 2edeebbd434627d1d0a9d96f6c5bda044a68fa70 Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar at ti.com>
Date: Mon, 12 Mar 2012 20:34:45 +0530
Subject: [PATCH] ARM: OMAP4: Workaround the OCP synchronisation issue
with 32K synctimer.

On OMAP4, recently a synchronisation bug is discovered by hardware
team, which leads to incorrect timer value read from 32K sync timer
IP when the IP is comming out of idle.

The issue is due to the synchronization methodology used in the
SYNCTIMER IP.
The value of the counter register in 32kHz domain is synchronized to the OCP
domain register only at count up event, and if the OCP clock is switched
off,
the OCP register gets out of synch until the first count up event after the
clock is switched back -at the next falling edge of the 32kHz clock.

Further investigation revealed that it applies to gptimer1 and watchdog
timer2
as well which may run on 32KHz. This patch fixes the issue for all the
applicable modules.

The BUG has not made it yet to the OMAP errata list and it is applicable to
OMAP1/2/3/4/5. OMAP1/2/3 it is taken care indirectly by autodeps.

By enabling static depedency of wakeup clockdomain with MPU, as soon as MPU
is woken up from lowpower state(idle) or whenever MPU is active, PRCM forces
the OCP clock to be running and allow the counter value to be updated
properly
in the OCP clock domain.

The bug is going to fixed in future OMAP versions.

Reported-Tested-by: dave.long at linaro.org
[dave.long at linaro.org: Reported the oprofile time stamp issue with synctimer
and helped to test this patch]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/pm44xx.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index c264ef7..974f7ea 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -196,7 +196,7 @@ static void omap_default_idle(void)
 static int __init omap4_pm_init(void)
 {
 	int ret;
-	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
+	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
 	struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;

 	if (!cpu_is_omap44xx())
@@ -220,14 +220,19 @@ static int __init omap4_pm_init(void)
 	 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
 	 * expected. The hardware recommendation is to enable static
 	 * dependencies for these to avoid system lock ups or random crashes.
+	 * The L4 wakeup depedency is added to workaround the OCP sync hardware
+	 * BUG with 32K synctimer which lead to incorrect timer value read
+	 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
+	 * are part of L4 wakeup clockdomain.
 	 */
 	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
 	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
 	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
 	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
 	l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
+	l4wkup = clkdm_lookup("l4_wkup_clkdm");
 	ducati_clkdm = clkdm_lookup("ducati_clkdm");
-	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
+	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) ||
 		(!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
 		goto err2;

@@ -235,6 +240,7 @@ static int __init omap4_pm_init(void)
 	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
 	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
 	ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
+	ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup);
 	ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
 	ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
 	if (ret) {
-- 
1.7.4.1





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From sfr at canb.auug.org.au  Tue Mar 13 04:47:27 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Tue, 13 Mar 2012 19:47:27 +1100
Subject: linux-next: manual merge of the arm-soc tree with the arm tree
Message-ID: <20120313194727.9d5939c174d54ea1569403f5@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/plat-versatile/localtimer.c between commit e9f07fbc5f5b ("ARM:
plat-versatile: convert to twd_local_timer_register() interface") from
the arm tree and commit e129440af638 ("ARM: versatile: Map local timers
using Device Tree when possible") from the arm-soc tree.

I did the obvious thing and removed the file (as the former does), but
there is probably more to be fixed up.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From pullip.cho at samsung.com  Tue Mar 13 04:50:16 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Tue, 13 Mar 2012 17:50:16 +0900
Subject: [PATCH v11 3/3] iommu/exynos: Add iommu driver for Exynos
 Platforms
In-Reply-To: <20120312150156.GF18973@amd.com>
References: <017a01ccfdee$4e5e7a00$eb1b6e00$%cho@samsung.com>
 <20120312150156.GF18973@amd.com>
Message-ID: <CAHQjnOOCQb4G1aeFB0FQVBstXpaXmahnQO8+FoinPcQNZEieGg@mail.gmail.com>

On Tue, Mar 13, 2012 at 12:01 AM, Joerg Roedel <joerg.roedel at amd.com> wrote:
> On Fri, Mar 09, 2012 at 09:15:24PM +0900, Cho KyongHo wrote:
>> +/* We does not consider super section mapping (16MB) */
>> +struct iommu_client {
>> + ? ? struct list_head node;
>> + ? ? struct device *dev;
>> +};
>> +
>> +struct exynos_iommu_domain {
>> + ? ? struct list_head clients; /* list of iommu_client */
>> + ? ? unsigned long *pgtable; /* lv1 page table, 16KB */
>> + ? ? short *lv2entcnt; /* free lv2 entry counter for each section */
>> + ? ? spinlock_t lock; /* lock for this structure and attached iommu_client */
>> + ? ? spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
>> +};
>> +
>> +struct sysmmu_drvdata {
>> + ? ? struct device *sysmmu;
>> + ? ? char *dbgname;
>> + ? ? int nsfrs;
>> + ? ? void __iomem **sfrbases;
>> + ? ? struct clk *clk[2];
>> + ? ? int activations;
>> + ? ? rwlock_t lock;
>> + ? ? struct iommu_domain *domain;
>> + ? ? sysmmu_fault_handler_t fault_handler;
>> + ? ? unsigned long pgtable;
>> + ? ? struct iommu_client client;
>> +};
>
> Is there any reason why 'struct iommu_client' is a seperate data
> structure? Otherwise it can be merged with 'truct sysmmu_drvdata'.
>

There is no reason to separate it.
It is not cleanly refactored since patch version 10.

>> +static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
>> +{
>> + ? ? struct exynos_iommu_domain *priv = domain->priv;
>> + ? ? struct list_head *pos, *n;
>> + ? ? unsigned long flags;
>> + ? ? int i;
>> +
>> + ? ? WARN_ON(!list_empty(&priv->clients));
>> +
>> + ? ? spin_lock_irqsave(&priv->lock, flags);
>> +
>> + ? ? list_for_each_safe(pos, n, &priv->clients) {
>> + ? ? ? ? ? ? struct iommu_client *client;
>> +
>> + ? ? ? ? ? ? client = list_entry(pos, struct iommu_client, node);
>> + ? ? ? ? ? ? exynos_sysmmu_disable(client->dev);
>> + ? ? ? ? ? ? kfree(client);
>> + ? ? }
>
> Why this kfree here? Aren't all iommu_clients just a part of another
> data-structre?

It is absolutely my fault. It must be removed.
I have forgot to care about updating iommu_domain_destroy()
when modifying exynos_iommu_attach/detach_device().

Thank you.

The problems will be soon fixed and I will post next patch tomorrow.

Cho KyongHo/


From bryan.wu at canonical.com  Tue Mar 13 04:50:51 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Tue, 13 Mar 2012 16:50:51 +0800
Subject: [PATCH 2/3] led-triggers: use atomic kzalloc during led trigger
 registering
In-Reply-To: <CACRpkdYvfzrdAC1vjT5WD4rk0ozpbXkPtkQpBVMv_WYhdkg7ag@mail.gmail.com>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
 <1331197863-25564-2-git-send-email-bryan.wu@canonical.com>
 <20120308092913.GF14173@pengutronix.de>
 <CAK5ve-+L9gVBOp4RVe2pTUbBnrb-PEn7ERbWWkb=7A=4qOrdTQ@mail.gmail.com>
 <CACRpkdYvfzrdAC1vjT5WD4rk0ozpbXkPtkQpBVMv_WYhdkg7ag@mail.gmail.com>
Message-ID: <CAK5ve-+ZNoiS3qdQ6O543uSAO9L0rr2c=WwuXm-biAqfGfjc7w@mail.gmail.com>

On Tue, Mar 13, 2012 at 3:37 AM, Linus Walleij <linus.walleij at linaro.org> wrote:
> 2012/3/10 Bryan Wu <bryan.wu at canonical.com>:
>> 2012/3/8 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
>>> On Thu, Mar 08, 2012 at 05:11:02PM +0800, Bryan Wu wrote:
>>>> kzalloc might cause sleep and will generate some warning detected by lockdep,
>>>> when call led_trigger_register_simple on each cpu cores in SMP. This patch fix
>>>> this.
>>> The obvious (and IMHO better) alternative is to call
>>> led_trigger_register_simple from non-atomic context.
>>>
>>> For registering this should be OK, shouldn't it?
>>>
>> Thanks Uwe, it's my bad. I think I should not use on_each_cpu() API to
>> run led_trigger_register_simple. on_each_cpu() will disable interrupt.
>
> It might have been my mistake even so not your fault ... :-)
>

No problem, man. I just simply replaced GFP_KERNEL with GFP_ATOMIC
without thinking deeper.

Best Regards,
-- 
Bryan Wu <bryan.wu at canonical.com>
Kernel Developer ? ?+86.138-1617-6545 Mobile
Canonical Ltd. ? ? ?www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com


From linus.walleij at linaro.org  Tue Mar 13 04:51:59 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 13 Mar 2012 09:51:59 +0100
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <1331500100-31351-4-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-4-git-send-email-robherring2@gmail.com>
Message-ID: <CACRpkda=WDTkSAwF8TYWfhnSX_FjJDwzKRhcuk6=pn9j96Eu=w@mail.gmail.com>

On Sun, Mar 11, 2012 at 10:08 PM, Rob Herring <robherring2 at gmail.com> wrote:

> From: Rob Herring <rob.herring at calxeda.com>
>
> Several platforms create IOMEM defines for casting to 'void __iomem *',
> and other platforms are incorrectly using __io() macro for the same
> purpose. This creates a common definition and removes all the platform
> specific versions. Rather than try to make linux/io.h and asm/io.h
> assembly safe, the assembly version of IOMEM is moved into
> asm/assembler.h.
>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

For:

> ?arch/arm/mach-u300/include/mach/u300-regs.h ? ? | ? ?6 ------

Yours,
Linus Walleij


From linus.walleij at linaro.org  Tue Mar 13 04:56:03 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 13 Mar 2012 09:56:03 +0100
Subject: [PATCH 4/4] ARM: __io abuse cleanup
In-Reply-To: <1331500100-31351-5-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-5-git-send-email-robherring2@gmail.com>
Message-ID: <CACRpkdZ_y3=vcj99C34SZ=hKQUmXdqoj0mqKJg2MLGqyUFsB0g@mail.gmail.com>

On Sun, Mar 11, 2012 at 10:08 PM, Rob Herring <robherring2 at gmail.com> wrote:

> From: Rob Herring <rob.herring at calxeda.com>
>
> Several platforms incorrectly use __io() for casting to 'void __iomem *'.
> This converts all of those uses to use the common IOMEM macro.
>
> Reported-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Anton Vorontsov <avorontsov at mvista.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Paul Mundt <lethal at linux-sh.org>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: linux-sh at vger.kernel.org

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Thanks Rob!
Linus Walleij


From plagnioj at jcrosoft.com  Tue Mar 13 05:11:04 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 10:11:04 +0100
Subject: [PATCH 1/5 v3] i2c/gpio: add DT support
In-Reply-To: <20120313073748.GA7746@pengutronix.de>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <20120313073748.GA7746@pengutronix.de>
Message-ID: <20120313091104.GE18320@game.jcrosoft.org>

On 08:37 Tue 13 Mar     , Wolfram Sang wrote:
> On Thu, Mar 08, 2012 at 09:50:31AM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> > Cc: linux-i2c at vger.kernel.org
> > Cc: devicetree-discuss at lists.ozlabs.org
> 
> Your patch description says "add DT support" but you are doing a bit more.
> This should at least be described here.
> 
> > ---
> > v3:
> > 
> > 	update i2c binding (Rob comments)
> > 
> > 	Jean can I have a ack to apply it?
> > 
> > Best Regards,
> > J.
> >  .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 +++++++
> >  drivers/i2c/busses/i2c-gpio.c                      |   94 +++++++++++++++----
> >  2 files changed, 106 insertions(+), 20 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> > new file mode 100644
> > index 0000000..4f8ec94
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
> > @@ -0,0 +1,32 @@
> > +Device-Tree bindings for i2c gpio driver
> > +
> > +Required properties:
> > +	- compatible = "i2c-gpio";
> 
> I assume people at "devicetree-discuss" have taken care of that, yet I wonder
> that this breaks the "vendor,product" syntax I know of for compatible entries.
yes but there no vendor here
get ack from Grant and Rob
> 
> > +	- gpios: sda and scl gpio
> > +
> > +
> > +Optional properties:
> > +	- i2c-gpio,sda-open-drain: sda as open drain
> > +	- i2c-gpio,scl-open-drain: scl as open drain
> > +	- i2c-gpio,scl-output-only: scl as output only
> > +	- i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform)
> > +	- i2c-gpio,timeout-ms: timeout to get data
> > +
> > +Example nodes:
> > +
> > +i2c at 0 {
> > +	compatible = "i2c-gpio";
> > +	gpios = <&pioA 23 0 /* sda */
> > +		 &pioA 24 0 /* scl */
> > +		>;
> > +	i2c-gpio,sda-open-drain;
> > +	i2c-gpio,scl-open-drain;
> > +	i2c-gpio,delay-us = <2>;	/* ~100 kHz */
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> > +
> > +	rv3029c2 at 56 {
> > +		compatible = "rv3029c2";
> > +		reg = <0x56>;
> > +	};
> > +};
> > diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
> > index a651779..98ae85b 100644
> > --- a/drivers/i2c/busses/i2c-gpio.c
> > +++ b/drivers/i2c/busses/i2c-gpio.c
> > @@ -14,8 +14,15 @@
> >  #include <linux/module.h>
> >  #include <linux/slab.h>
> >  #include <linux/platform_device.h>
> > +#include <linux/gpio.h>
> > +#include <linux/of_gpio.h>
> > +#include <linux/of_i2c.h>
> >  
> > -#include <asm/gpio.h>
> > +struct i2c_gpio_private_data {
> > +	struct i2c_adapter adap;
> > +	struct i2c_algo_bit_data bit_data;
> > +	struct i2c_gpio_platform_data pdata;
> > +};
> >  
> >  /* Toggle SDA by changing the direction of the pin */
> >  static void i2c_gpio_setsda_dir(void *data, int state)
> > @@ -78,24 +85,62 @@ static int i2c_gpio_getscl(void *data)
> >  	return gpio_get_value(pdata->scl_pin);
> >  }
> >  
> > +static int __devinit of_i2c_gpio_probe(struct device_node *np,
> > +			     struct i2c_gpio_platform_data *pdata)
> > +{
> > +	u32 reg;
> > +
> > +	if (of_gpio_count(np) < 2)
> > +		return -ENODEV;
> > +
> > +	pdata->sda_pin = of_get_gpio(np, 0);
> > +	pdata->scl_pin = of_get_gpio(np, 1);
> > +
> > +	if (pdata->sda_pin < 0 || pdata->scl_pin < 0) {
> 
> gpio_is_valid()?
> 
> > +		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
> > +		       np->full_name, pdata->sda_pin, pdata->scl_pin);
> > +		return -ENODEV;
> > +	}
> > +
> > +	of_property_read_u32(np, "i2c-gpio,delay-us", &pdata->udelay);
> > +
> > +	if (of_property_read_u32(np, "i2c-gpio,timeout-ms", &reg))
> > +		pdata->timeout = msecs_to_jiffies(reg);
> > +
> > +	pdata->sda_is_open_drain =
> > +		!!of_property_read_bool(np, "i2c-gpio,sda-open-drain");
> > +	pdata->scl_is_open_drain =
> > +		!!of_property_read_bool(np, "i2c-gpio,scl-open-drain");
> > +	pdata->scl_is_output_only =
> > +		!!of_property_read_bool(np, "i2c-gpio,scl-output-only");
> > +
> > +	return 0;
> > +}
> > +
> >  static int __devinit i2c_gpio_probe(struct platform_device *pdev)
> >  {
> > +	struct i2c_gpio_private_data *priv;
> >  	struct i2c_gpio_platform_data *pdata;
> >  	struct i2c_algo_bit_data *bit_data;
> >  	struct i2c_adapter *adap;
> >  	int ret;
> >  
> > -	pdata = pdev->dev.platform_data;
> > -	if (!pdata)
> > -		return -ENXIO;
> > +	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> > +	if (!priv)
> > +		return -ENOMEM;
> > +	adap = &priv->adap;
> > +	bit_data = &priv->bit_data;
> > +	pdata = &priv->pdata;
> >  
> > -	ret = -ENOMEM;
> > -	adap = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
> > -	if (!adap)
> > -		goto err_alloc_adap;
> > -	bit_data = kzalloc(sizeof(struct i2c_algo_bit_data), GFP_KERNEL);
> > -	if (!bit_data)
> > -		goto err_alloc_bit_data;
> > +	if (pdev->dev.of_node) {
> > +		ret = of_i2c_gpio_probe(pdev->dev.of_node, pdata);
> > +		if (ret)
> > +			return ret;
> > +	} else {
> > +		if (!pdev->dev.platform_data)
> > +			return -ENXIO;
> > +		memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
> > +	}
> >  
> >  	ret = gpio_request(pdata->sda_pin, "sda");
> >  	if (ret)
> > @@ -143,6 +188,7 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
> >  	adap->algo_data = bit_data;
> >  	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
> >  	adap->dev.parent = &pdev->dev;
> > +	adap->dev.of_node = pdev->dev.of_node;
> >  
> >  	/*
> >  	 * If "dev->id" is negative we consider it as zero.
> > @@ -154,7 +200,9 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
> >  	if (ret)
> >  		goto err_add_bus;
> >  
> > -	platform_set_drvdata(pdev, adap);
> > +	of_i2c_register_devices(adap);
> > +
> > +	platform_set_drvdata(pdev, priv);
> >  
> >  	dev_info(&pdev->dev, "using pins %u (SDA) and %u (SCL%s)\n",
> >  		 pdata->sda_pin, pdata->scl_pin,
> > @@ -168,34 +216,40 @@ err_add_bus:
> >  err_request_scl:
> >  	gpio_free(pdata->sda_pin);
> >  err_request_sda:
> > -	kfree(bit_data);
> > -err_alloc_bit_data:
> > -	kfree(adap);
> > -err_alloc_adap:
> >  	return ret;
> >  }
> >  
> >  static int __devexit i2c_gpio_remove(struct platform_device *pdev)
> >  {
> > +	struct i2c_gpio_private_data *priv;
> >  	struct i2c_gpio_platform_data *pdata;
> >  	struct i2c_adapter *adap;
> >  
> > -	adap = platform_get_drvdata(pdev);
> > -	pdata = pdev->dev.platform_data;
> > +	priv = platform_get_drvdata(pdev);
> > +	adap = &priv->adap;
> > +	pdata = &priv->pdata;
> >  
> >  	i2c_del_adapter(adap);
> >  	gpio_free(pdata->scl_pin);
> >  	gpio_free(pdata->sda_pin);
> > -	kfree(adap->algo_data);
> > -	kfree(adap);
> >  
> >  	return 0;
> >  }
> >  
> > +#if defined(CONFIG_OF)
> > +static const struct of_device_id i2c_gpio_dt_ids[] = {
> > +	{ .compatible = "i2c-gpio", },
> > +	{ /* sentinel */ }
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, i2c_gpio_dt_ids);
> > +#endif
> > +
> >  static struct platform_driver i2c_gpio_driver = {
> >  	.driver		= {
> >  		.name	= "i2c-gpio",
> >  		.owner	= THIS_MODULE,
> > +		.of_match_table	= of_match_ptr(i2c_gpio_dt_ids),
> >  	},
> >  	.probe		= i2c_gpio_probe,
> >  	.remove		= __devexit_p(i2c_gpio_remove),
> 
> Otherwise looks good in general. What was your test scenario?
AT91 support on 3 different SoC

will update and send it via AT91  with your ack

Best Regards,
J.
> 
> Thanks,
> 
>    Wolfram
> 
> -- 
> Pengutronix e.K.                           | Wolfram Sang                |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |




From jg1.han at samsung.com  Tue Mar 13 05:34:32 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Tue, 13 Mar 2012 18:34:32 +0900
Subject: [PATCH v3 2/3] video: s3c-fb: remove 'default_win' element from
 platform data
In-Reply-To: <1331585999-8604-3-git-send-email-thomas.abraham@linaro.org>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-3-git-send-email-thomas.abraham@linaro.org>
Message-ID: <002e01cd00fc$7efad9e0$7cf08da0$%han@samsung.com>

From: Thomas Abraham <thomas.abraham at linaro.org>

The decision to enable or disable the data output to the lcd panel from
the controller need not be based on the value of 'default_win' element
in the platform data. Instead, the data output to the panel is enabled
if any of the windows are active, else data output is disabled.

Cc: Ben Dooks <ben-linux at fluff.org>
Signed-off-by: Jingoo Han <jg1.han at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
v3: fix some minor coding styles

 arch/arm/plat-samsung/include/plat/fb.h |    3 ---
 drivers/video/s3c-fb.c                  |   24 +++++-------------------
 2 files changed, 5 insertions(+), 22 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 39d6bd7..b885322 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -43,7 +43,6 @@ struct s3c_fb_pd_win {
  * @setup_gpio: Setup the external GPIO pins to the right state to transfer
  *		the data from the display system to the connected display
  *		device.
- * @default_win: default window layer number to be used for UI layer.
  * @vidcon0: The base vidcon0 values to control the panel data format.
  * @vidcon1: The base vidcon1 values to control the panel data output.
  * @vtiming: Video timing when connected to a RGB type panel.
@@ -62,8 +61,6 @@ struct s3c_fb_platdata {
 	struct s3c_fb_pd_win	*win[S3C_FB_MAX_WIN];
 	struct fb_videomode     *vtiming;
 
-	u32			 default_win;
-
 	u32			 vidcon0;
 	u32			 vidcon1;
 };
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index c94f40d..dd816fb 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -531,7 +531,7 @@ static int s3c_fb_set_par(struct fb_info *info)
 	/* disable the window whilst we update it */
 	writel(0, regs + WINCON(win_no));
 
-	if (win_no == sfb->pdata->default_win)
+	if (!sfb->output_on)
 		s3c_fb_enable(sfb, 1);
 
 	/* write the buffer address */
@@ -799,6 +799,7 @@ static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 	struct s3c_fb *sfb = win->parent;
 	unsigned int index = win->index;
 	u32 wincon;
+	u32 output_on = sfb->output_on;
 
 	dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
 
@@ -844,27 +845,12 @@ static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 	 * it is highly likely that we also do not need to output
 	 * anything.
 	 */
-
-	/* We could do something like the following code, but the current
-	 * system of using framebuffer events means that we cannot make
-	 * the distinction between just window 0 being inactive and all
-	 * the windows being down.
-	 *
-	 * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
-	*/
-
-	/* we're stuck with this until we can do something about overriding
-	 * the power control using the blanking event for a single fb.
-	 */
-	if (index == sfb->pdata->default_win) {
-		shadow_protect_win(win, 1);
-		s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
-		shadow_protect_win(win, 0);
-	}
+	s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
+	shadow_protect_win(win, 0);
 
 	pm_runtime_put_sync(sfb->dev);
 
-	return 0;
+	return output_on == sfb->output_on;
 }
 
 /**
-- 
1.7.1




From marc.zyngier at arm.com  Tue Mar 13 05:39:57 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 13 Mar 2012 09:39:57 +0000
Subject: Conflict between Versatile Express DT conversion and local timer
 updates
In-Reply-To: <CAOesGMjt26JgySpcqVT+PsSgGq9cxQWn+msG4DSwo=2ykGz91A@mail.gmail.com>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <20120312235951.GA31601@n2100.arm.linux.org.uk>
 <CAOesGMjt26JgySpcqVT+PsSgGq9cxQWn+msG4DSwo=2ykGz91A@mail.gmail.com>
Message-ID: <4F5F15ED.2010602@arm.com>

On 13/03/12 01:23, Olof Johansson wrote:
> Hi,
> 
> On Mon, Mar 12, 2012 at 4:59 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
>> On Mon, Mar 12, 2012 at 11:10:16PM +0000, Russell King - ARM Linux wrote:
>>> Marc, Pawel,
>>>
>>> Your changes are conflicting badly.  Seriously badly.  So badly that I'm
>>> not bothering to fix the conflicts because I can't work out what the fix
>>> should be.
>>>
>>> You both work for the same frigging organization and yet you seem to
>>> work completely independently (I really don't care if you work in
>>> different departments - the fact of the matter is you're touching the
>>> same code in completely different ways with zero coordination between
>>> yourselves.  That's simply broken workflow.)
>>>
>>> For example, Marc's deleting arch/arm/plat-versatile/localtimer.c, but
>>> Pawel is modifying it to add DT support for Versatile Express.  The
>>> correct solution?  Hell knows.  And I don't want a solution to the merge
>>> conflict.  I want the merge conflict to go away (because I'm not frigging
>>> around applying the same git-rerere immune fixes to a tree I'm regenerating
>>> each night for the kernel autobuilder.)
>>>
>>> I'm getting conflicts in arch/arm/mach-vexpress/ct-ca9x4.c and
>>> arch/arm/mach-ux500/timer.c as well, which I'm not going to bother trying
>>> to sort out - the obvious solution for ux500/timer.c doesn't look right.
>>>
>>> I've a mind to drop the localtimer changes on the floor until after this
>>> merge window, but unfortunately they're part of devel-stable so I can't.
>>
>> Correction: I haven't been pushing out my devel-stable branch for
>> apparantly two months (according to gitweb, and no one noticed?), so I
>> _could_ drop the merge of Marc's tree until the conflicts can be sanely
>> resolved.
> 
> I haven't noticed because I stopped tracking your tree directly when
> you were having server load issues; I tend to have kept an eye on
> linux-next-level breakage instead, but probably not as close as I
> should have.
> 
> Dropping Marc's branch and having him either resubmit on top of
> arm-soc like the io cleanup was done, or pull it in as an early
> dependency for 3.5 and stage it in an for-armsoc branch sounds like
> two good options to me, with no real preference in either direction.

I'm happy to rebase my patches on anything that will make the merge
easier (IOW conflict-less).

Russell, would you prefer this series to go via armsoc? This seems the
cleanest solution for the time being.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From jg1.han at samsung.com  Tue Mar 13 05:47:56 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Tue, 13 Mar 2012 18:47:56 +0900
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
Message-ID: <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>

> -----Original Message-----
> From: Thomas Abraham [mailto:thomas.abraham at linaro.org]
> Sent: Tuesday, March 13, 2012 6:00 AM
> To: linux-fbdev at vger.kernel.org
> Cc: FlorianSchandinat at gmx.de; linux-arm-kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org;
> kgene.kim at samsung.com; jg1.han at samsung.com; ben-linux at fluff.org; patches at linaro.org; Kyungmin Park;
> JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter Korsgaard; Darius Augulis; Maurus
> Cuelenaere
> Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> 
> For all the Samsung SoC based boards which have the platform data for
> s3c-fb driver, the 'default_win' element in the platform data is removed
> and the lcd panel video timing values are moved out of individual window
> configuration data.
> 
> Cc: Jingoo Han <jg1.han at samsung.com>
> Cc: Kyungmin Park <kyungmin.park at samsung.com>
> Cc: JeongHyeon Kim <jhkim at insignal.co.kr>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Cc: Heiko Stuebner <heiko at sntech.de>
> Cc: Ben Dooks <ben-linux at fluff.org>
> Cc: Kwangwoo Lee <kwangwoo.lee at gmail.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Peter Korsgaard <jacmet at sunsite.dk>
> Cc: Darius Augulis <augulis.darius at gmail.com>
> Cc: Maurus Cuelenaere <mcuelenaere at gmail.com>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> ---
>  arch/arm/mach-exynos/mach-nuri.c           |   26 ++++++++++-------
>  arch/arm/mach-exynos/mach-origen.c         |   24 ++++++++++-------
>  arch/arm/mach-exynos/mach-smdkv310.c       |   28 +++++++++++--------
>  arch/arm/mach-exynos/mach-universal_c210.c |   26 ++++++++++-------
>  arch/arm/mach-s3c24xx/mach-smdk2416.c      |   27 ++++++++++--------
>  arch/arm/mach-s3c64xx/mach-anw6410.c       |   25 ++++++++++-------
>  arch/arm/mach-s3c64xx/mach-crag6410.c      |   25 ++++++++++-------
>  arch/arm/mach-s3c64xx/mach-hmt.c           |   24 ++++++++++-------
>  arch/arm/mach-s3c64xx/mach-mini6410.c      |   40 ++++++++++++---------------
>  arch/arm/mach-s3c64xx/mach-real6410.c      |   40 ++++++++++++---------------
>  arch/arm/mach-s3c64xx/mach-smartq5.c       |   26 ++++++++++-------
>  arch/arm/mach-s3c64xx/mach-smartq7.c       |   26 ++++++++++-------
>  arch/arm/mach-s3c64xx/mach-smdk6410.c      |   25 ++++++++++-------
>  arch/arm/mach-s5p64x0/mach-smdk6440.c      |   24 ++++++++++-------
>  arch/arm/mach-s5p64x0/mach-smdk6450.c      |   24 ++++++++++-------
>  arch/arm/mach-s5pc100/mach-smdkc100.c      |   27 ++++++++++--------
>  arch/arm/mach-s5pv210/mach-aquila.c        |   36 +++++++++++--------------
>  arch/arm/mach-s5pv210/mach-goni.c          |   26 ++++++++++-------
>  arch/arm/mach-s5pv210/mach-smdkv210.c      |   24 ++++++++++-------
>  19 files changed, 285 insertions(+), 238 deletions(-)
> 

[.....]

> diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
> index c34c2ab..24dcdc9 100644
> --- a/arch/arm/mach-s3c64xx/mach-mini6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
> @@ -153,36 +153,32 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
> 
>  static struct s3c_fb_pd_win mini6410_fb_win[] = {
>  	{
> -		.win_mode	= {	/* 4.3" 480x272 */
> -			.left_margin	= 3,
> -			.right_margin	= 2,
> -			.upper_margin	= 1,
> -			.lower_margin	= 1,
> -			.hsync_len	= 40,
> -			.vsync_len	= 1,
> -			.xres		= 480,
> -			.yres		= 272,
> -		},
>  		.max_bpp	= 32,
>  		.default_bpp	= 16,
> +		.xres		= 480,
> +		.yres		= 272,
>  	}, {
> -		.win_mode	= {	/* 7.0" 800x480 */
> -			.left_margin	= 8,
> -			.right_margin	= 13,
> -			.upper_margin	= 7,
> -			.lower_margin	= 5,
> -			.hsync_len	= 3,
> -			.vsync_len	= 1,
> -			.xres		= 800,
> -			.yres		= 480,
> -		},
>  		.max_bpp	= 32,
>  		.default_bpp	= 16,
> +		.xres		= 800,
> +		.yres		= 480,
>  	},
>  };
> 
> +static struct fb_videomode mini6410_lcd_timing = {
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
>  static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
>  	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +	.vtiming	= &mini6410_lcd_timing,
>  	.win[0]		= &mini6410_fb_win[0],
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> @@ -310,8 +306,8 @@ static void __init mini6410_machine_init(void)
>  	mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
> 
>  	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
> -		mini6410_lcd_pdata.win[0]->win_mode.xres,
> -		mini6410_lcd_pdata.win[0]->win_mode.yres);
> +		mini6410_lcd_pdata.win[0]->xres,
> +		mini6410_lcd_pdata.win[0]->yres);
> 
>  	s3c_nand_set_platdata(&mini6410_nand_info);
>  	s3c_fb_set_platdata(&mini6410_lcd_pdata);
> diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
> index be2a9a2..41e4f74 100644
> --- a/arch/arm/mach-s3c64xx/mach-real6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-real6410.c
> @@ -119,36 +119,32 @@ static struct platform_device real6410_device_eth = {
> 
>  static struct s3c_fb_pd_win real6410_fb_win[] = {
>  	{
> -		.win_mode	= {	/* 4.3" 480x272 */
> -			.left_margin	= 3,
> -			.right_margin	= 2,
> -			.upper_margin	= 1,
> -			.lower_margin	= 1,
> -			.hsync_len	= 40,
> -			.vsync_len	= 1,
> -			.xres		= 480,
> -			.yres		= 272,
> -		},
>  		.max_bpp	= 32,
>  		.default_bpp	= 16,
> +		.xres		= 480,
> +		.yres		= 272,
>  	}, {
> -		.win_mode	= {	/* 7.0" 800x480 */
> -			.left_margin	= 8,
> -			.right_margin	= 13,
> -			.upper_margin	= 7,
> -			.lower_margin	= 5,
> -			.hsync_len	= 3,
> -			.vsync_len	= 1,
> -			.xres		= 800,
> -			.yres		= 480,
> -		},
>  		.max_bpp	= 32,
>  		.default_bpp	= 16,
> +		.xres		= 800,
> +		.yres		= 480,
>  	},
>  };
> 
> +static struct fb_videomode real6410_lcd_timing = {
> +	.left_margin	= 3,
> +	.right_margin	= 2,
> +	.upper_margin	= 1,
> +	.lower_margin	= 1,
> +	.hsync_len	= 40,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
> +};


What is the difference between mini6410_lcd_timing and real6410_lcd_timing?
In my opinion, it would be good as follows:

+static struct fb_videomode real6410_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
+};


> +
>  static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
>  	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +	.vtiming	= &real6410_lcd_timing,
>  	.win[0]		= &real6410_fb_win[0],
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> @@ -291,8 +287,8 @@ static void __init real6410_machine_init(void)
>  	real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
> 
>  	printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
> -		real6410_lcd_pdata.win[0]->win_mode.xres,
> -		real6410_lcd_pdata.win[0]->win_mode.yres);
> +		real6410_lcd_pdata.win[0]->xres,
> +		real6410_lcd_pdata.win[0]->yres);
> 
>  	s3c_fb_set_platdata(&real6410_lcd_pdata);
>  	s3c_nand_set_platdata(&real6410_nand_info);
[.....]




From arnd at arndb.de  Tue Mar 13 05:52:24 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 09:52:24 +0000
Subject: [PATCH v4 04/11] ep93xx: Use ioremap for backlight driver
In-Reply-To: <1331592502-9083-5-git-send-email-rmallon@gmail.com>
References: <1331592502-9083-5-git-send-email-rmallon@gmail.com>
Message-ID: <201203130952.24401.arnd@arndb.de>

On Monday 12 March 2012, Ryan Mallon wrote:
> The ep93xx backlight driver uses a single register within the
> framebuffer's register space. Currently the backlight driver uses a
> static IO mapping for the register since the memory cannot be
> requested by both drivers.
> 
> Convert the static mapping to use ioremap so that we can remove the
> dependency on mach/hardware.h. To do so, we need remove the
> request_mem_region from both the backlight and framebuffer drivers,
> since whichever driver is loaded second will fail with -EBUSY
> otherwise.
> 
> A proper fix is still required, and a FIXME comment has been added to
> both drivers.

Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Tue Mar 13 05:54:17 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 09:54:17 +0000
Subject: [PATCH 3/7 v2] ARM: orion: wdt: use resource vice direct access
In-Reply-To: <e8cd3863d70b322ee7625d0e49af0acdb82644fc.1331601448.git.jason@lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
 <e8cd3863d70b322ee7625d0e49af0acdb82644fc.1331601448.git.jason@lakedaemon.net>
Message-ID: <201203130954.17559.arnd@arndb.de>

On Tuesday 13 March 2012, Jason Cooper wrote:
> From: Andrew Lunn <andrew at lunn.ch>
> 
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> Acked-by: Grant Likely <grant.likely at secretlab.ca>

Acked-by: Arnd Bergmann <arnd at arndb.de>



From arnd at arndb.de  Tue Mar 13 05:57:26 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 09:57:26 +0000
Subject: [PATCH 6/7] ARM: kirkwood: rtc-mv devicetree bindings
In-Reply-To: <0b9921e304cb46af9c4fbc8b7b8c8b9ba3d18654.1331601448.git.jason@lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
 <0b9921e304cb46af9c4fbc8b7b8c8b9ba3d18654.1331601448.git.jason@lakedaemon.net>
Message-ID: <201203130957.26274.arnd@arndb.de>

On Tuesday 13 March 2012, Jason Cooper wrote:
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  drivers/rtc/rtc-mv.c |    9 +++++++++
>  1 files changed, 9 insertions(+), 0 deletions(-)

Acked-by: Arnd Bergmann <arnd at arndb.de>

It would be nice to have a small patch description here, saying that
this device is trivial to convert to device tree by just adding the
match table.

	Arnd


From arnd at arndb.de  Tue Mar 13 05:58:30 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 09:58:30 +0000
Subject: [PATCH 7/7] ARM: kirkwood: use devicetree for rtc-mv
In-Reply-To: <92d02581e0fce75f84d61edf55678108237e881a.1331601448.git.jason@lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
 <92d02581e0fce75f84d61edf55678108237e881a.1331601448.git.jason@lakedaemon.net>
Message-ID: <201203130958.31223.arnd@arndb.de>

On Tuesday 13 March 2012, Jason Cooper wrote:
> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
>  arch/arm/mach-kirkwood/board-dt.c |    1 -
>  arch/arm/mach-kirkwood/common.c   |    2 +-
>  arch/arm/mach-kirkwood/common.h   |    1 -
>  4 files changed, 7 insertions(+), 3 deletions(-)
> 

Acked-by: Arnd Bergmann <arnd at arndb.de>

I think you can just merge this with patch 6, as they are two halves
of the same work.

	Arnd


From joerg.roedel at amd.com  Tue Mar 13 06:00:24 2012
From: joerg.roedel at amd.com (Joerg Roedel)
Date: Tue, 13 Mar 2012 11:00:24 +0100
Subject: [PATCH v11 3/3] iommu/exynos: Add iommu driver for Exynos
 Platforms
In-Reply-To: <CAHQjnOOCQb4G1aeFB0FQVBstXpaXmahnQO8+FoinPcQNZEieGg@mail.gmail.com>
References: <017a01ccfdee$4e5e7a00$eb1b6e00$%cho@samsung.com>
 <20120312150156.GF18973@amd.com>
 <CAHQjnOOCQb4G1aeFB0FQVBstXpaXmahnQO8+FoinPcQNZEieGg@mail.gmail.com>
Message-ID: <20120313100024.GG18973@amd.com>

On Tue, Mar 13, 2012 at 05:50:16PM +0900, KyongHo Cho wrote:
> >> +struct sysmmu_drvdata {
> >> + ? ? struct device *sysmmu;
> >> + ? ? char *dbgname;
> >> + ? ? int nsfrs;
> >> + ? ? void __iomem **sfrbases;
> >> + ? ? struct clk *clk[2];
> >> + ? ? int activations;
> >> + ? ? rwlock_t lock;
> >> + ? ? struct iommu_domain *domain;
> >> + ? ? sysmmu_fault_handler_t fault_handler;
> >> + ? ? unsigned long pgtable;
> >> + ? ? struct iommu_client client;
> >> +};
> >
> > Is there any reason why 'struct iommu_client' is a seperate data
> > structure? Otherwise it can be merged with 'truct sysmmu_drvdata'.

Of course this doesn't need to be changed immediatly. I just asked if
there was a specific reason for this seperation.

> The problems will be soon fixed and I will post next patch tomorrow.

Fine. Please also get the Acked-bys from the Exynos maintainer on
patches 1 and 2 at least. I'll merge it then.


	Joerg

-- 
AMD Operating System Research Center

Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632



From u.kleine-koenig at pengutronix.de  Tue Mar 13 06:03:47 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Tue, 13 Mar 2012 11:03:47 +0100
Subject: [PATCH 6/7] ARM: kirkwood: rtc-mv devicetree bindings
In-Reply-To: <0b9921e304cb46af9c4fbc8b7b8c8b9ba3d18654.1331601448.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <cover.1331601448.git.jason@lakedaemon.net>
 <0b9921e304cb46af9c4fbc8b7b8c8b9ba3d18654.1331601448.git.jason@lakedaemon.net>
Message-ID: <20120313100347.GA10400@pengutronix.de>

On Tue, Mar 13, 2012 at 01:57:48AM +0000, Jason Cooper wrote:
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
>  drivers/rtc/rtc-mv.c |    9 +++++++++
>  1 files changed, 9 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c
> index 768e2ed..0dd8421 100644
> --- a/drivers/rtc/rtc-mv.c
> +++ b/drivers/rtc/rtc-mv.c
> @@ -12,6 +12,7 @@
>  #include <linux/bcd.h>
>  #include <linux/io.h>
>  #include <linux/platform_device.h>
> +#include <linux/of.h>
>  #include <linux/delay.h>
>  #include <linux/gfp.h>
>  #include <linux/module.h>
> @@ -294,11 +295,19 @@ static int __exit mv_rtc_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +#ifdef CONFIG_OF
> +static struct of_device_id rtc_mv_of_match_table[] = {
> +	{ .compatible = "mrvl,orion-rtc", },
> +	{}
> +};
> +#endif
I guess it's a matter of taste, but you could use __maybe_unused instead
of #ifdef .. #endif.

Best regards
Uwe

> +
>  static struct platform_driver mv_rtc_driver = {
>  	.remove		= __exit_p(mv_rtc_remove),
>  	.driver		= {
>  		.name	= "rtc-mv",
>  		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(rtc_mv_of_match_table),
>  	},
>  };
>  
> -- 
> 1.7.3.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From thomas.abraham at linaro.org  Tue Mar 13 06:10:51 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 15:40:51 +0530
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
Message-ID: <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>

On 13 March 2012 15:17, Jingoo Han <jg1.han at samsung.com> wrote:
>> -----Original Message-----
>> From: Thomas Abraham [mailto:thomas.abraham at linaro.org]
>> Sent: Tuesday, March 13, 2012 6:00 AM
>> To: linux-fbdev at vger.kernel.org
>> Cc: FlorianSchandinat at gmx.de; linux-arm-kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org;
>> kgene.kim at samsung.com; jg1.han at samsung.com; ben-linux at fluff.org; patches at linaro.org; Kyungmin Park;
>> JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter Korsgaard; Darius Augulis; Maurus
>> Cuelenaere
>> Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
>>
>> For all the Samsung SoC based boards which have the platform data for
>> s3c-fb driver, the 'default_win' element in the platform data is removed
>> and the lcd panel video timing values are moved out of individual window
>> configuration data.
>>
>> Cc: Jingoo Han <jg1.han at samsung.com>
>> Cc: Kyungmin Park <kyungmin.park at samsung.com>
>> Cc: JeongHyeon Kim <jhkim at insignal.co.kr>
>> Cc: Kukjin Kim <kgene.kim at samsung.com>
>> Cc: Heiko Stuebner <heiko at sntech.de>
>> Cc: Ben Dooks <ben-linux at fluff.org>
>> Cc: Kwangwoo Lee <kwangwoo.lee at gmail.com>
>> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
>> Cc: Peter Korsgaard <jacmet at sunsite.dk>
>> Cc: Darius Augulis <augulis.darius at gmail.com>
>> Cc: Maurus Cuelenaere <mcuelenaere at gmail.com>
>> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
>> ---
>> ?arch/arm/mach-exynos/mach-nuri.c ? ? ? ? ? | ? 26 ++++++++++-------
>> ?arch/arm/mach-exynos/mach-origen.c ? ? ? ? | ? 24 ++++++++++-------
>> ?arch/arm/mach-exynos/mach-smdkv310.c ? ? ? | ? 28 +++++++++++--------
>> ?arch/arm/mach-exynos/mach-universal_c210.c | ? 26 ++++++++++-------
>> ?arch/arm/mach-s3c24xx/mach-smdk2416.c ? ? ?| ? 27 ++++++++++--------
>> ?arch/arm/mach-s3c64xx/mach-anw6410.c ? ? ? | ? 25 ++++++++++-------
>> ?arch/arm/mach-s3c64xx/mach-crag6410.c ? ? ?| ? 25 ++++++++++-------
>> ?arch/arm/mach-s3c64xx/mach-hmt.c ? ? ? ? ? | ? 24 ++++++++++-------
>> ?arch/arm/mach-s3c64xx/mach-mini6410.c ? ? ?| ? 40 ++++++++++++---------------
>> ?arch/arm/mach-s3c64xx/mach-real6410.c ? ? ?| ? 40 ++++++++++++---------------
>> ?arch/arm/mach-s3c64xx/mach-smartq5.c ? ? ? | ? 26 ++++++++++-------
>> ?arch/arm/mach-s3c64xx/mach-smartq7.c ? ? ? | ? 26 ++++++++++-------
>> ?arch/arm/mach-s3c64xx/mach-smdk6410.c ? ? ?| ? 25 ++++++++++-------
>> ?arch/arm/mach-s5p64x0/mach-smdk6440.c ? ? ?| ? 24 ++++++++++-------
>> ?arch/arm/mach-s5p64x0/mach-smdk6450.c ? ? ?| ? 24 ++++++++++-------
>> ?arch/arm/mach-s5pc100/mach-smdkc100.c ? ? ?| ? 27 ++++++++++--------
>> ?arch/arm/mach-s5pv210/mach-aquila.c ? ? ? ?| ? 36 +++++++++++--------------
>> ?arch/arm/mach-s5pv210/mach-goni.c ? ? ? ? ?| ? 26 ++++++++++-------
>> ?arch/arm/mach-s5pv210/mach-smdkv210.c ? ? ?| ? 24 ++++++++++-------
>> ?19 files changed, 285 insertions(+), 238 deletions(-)
>>
>
> [.....]
>
>> diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
>> index c34c2ab..24dcdc9 100644
>> --- a/arch/arm/mach-s3c64xx/mach-mini6410.c
>> +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
>> @@ -153,36 +153,32 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
>>
>> ?static struct s3c_fb_pd_win mini6410_fb_win[] = {
>> ? ? ? {
>> - ? ? ? ? ? ? .win_mode ? ? ? = { ? ? /* 4.3" 480x272 */
>> - ? ? ? ? ? ? ? ? ? ? .left_margin ? ?= 3,
>> - ? ? ? ? ? ? ? ? ? ? .right_margin ? = 2,
>> - ? ? ? ? ? ? ? ? ? ? .upper_margin ? = 1,
>> - ? ? ? ? ? ? ? ? ? ? .lower_margin ? = 1,
>> - ? ? ? ? ? ? ? ? ? ? .hsync_len ? ? ?= 40,
>> - ? ? ? ? ? ? ? ? ? ? .vsync_len ? ? ?= 1,
>> - ? ? ? ? ? ? ? ? ? ? .xres ? ? ? ? ? = 480,
>> - ? ? ? ? ? ? ? ? ? ? .yres ? ? ? ? ? = 272,
>> - ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .max_bpp ? ? ? ?= 32,
>> ? ? ? ? ? ? ? .default_bpp ? ?= 16,
>> + ? ? ? ? ? ? .xres ? ? ? ? ? = 480,
>> + ? ? ? ? ? ? .yres ? ? ? ? ? = 272,
>> ? ? ? }, {
>> - ? ? ? ? ? ? .win_mode ? ? ? = { ? ? /* 7.0" 800x480 */
>> - ? ? ? ? ? ? ? ? ? ? .left_margin ? ?= 8,
>> - ? ? ? ? ? ? ? ? ? ? .right_margin ? = 13,
>> - ? ? ? ? ? ? ? ? ? ? .upper_margin ? = 7,
>> - ? ? ? ? ? ? ? ? ? ? .lower_margin ? = 5,
>> - ? ? ? ? ? ? ? ? ? ? .hsync_len ? ? ?= 3,
>> - ? ? ? ? ? ? ? ? ? ? .vsync_len ? ? ?= 1,
>> - ? ? ? ? ? ? ? ? ? ? .xres ? ? ? ? ? = 800,
>> - ? ? ? ? ? ? ? ? ? ? .yres ? ? ? ? ? = 480,
>> - ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .max_bpp ? ? ? ?= 32,
>> ? ? ? ? ? ? ? .default_bpp ? ?= 16,
>> + ? ? ? ? ? ? .xres ? ? ? ? ? = 800,
>> + ? ? ? ? ? ? .yres ? ? ? ? ? = 480,
>> ? ? ? },
>> ?};
>>
>> +static struct fb_videomode mini6410_lcd_timing = {
>> + ? ? .left_margin ? ?= 8,
>> + ? ? .right_margin ? = 13,
>> + ? ? .upper_margin ? = 7,
>> + ? ? .lower_margin ? = 5,
>> + ? ? .hsync_len ? ? ?= 3,
>> + ? ? .vsync_len ? ? ?= 1,
>> + ? ? .xres ? ? ? ? ? = 800,
>> + ? ? .yres ? ? ? ? ? = 480,
>> +};
>> +
>> ?static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
>> ? ? ? .setup_gpio ? ? = s3c64xx_fb_gpio_setup_24bpp,
>> + ? ? .vtiming ? ? ? ?= &mini6410_lcd_timing,
>> ? ? ? .win[0] ? ? ? ? = &mini6410_fb_win[0],
>> ? ? ? .vidcon0 ? ? ? ?= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>> ? ? ? .vidcon1 ? ? ? ?= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>> @@ -310,8 +306,8 @@ static void __init mini6410_machine_init(void)
>> ? ? ? mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
>>
>> ? ? ? printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
>> - ? ? ? ? ? ? mini6410_lcd_pdata.win[0]->win_mode.xres,
>> - ? ? ? ? ? ? mini6410_lcd_pdata.win[0]->win_mode.yres);
>> + ? ? ? ? ? ? mini6410_lcd_pdata.win[0]->xres,
>> + ? ? ? ? ? ? mini6410_lcd_pdata.win[0]->yres);
>>
>> ? ? ? s3c_nand_set_platdata(&mini6410_nand_info);
>> ? ? ? s3c_fb_set_platdata(&mini6410_lcd_pdata);
>> diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
>> index be2a9a2..41e4f74 100644
>> --- a/arch/arm/mach-s3c64xx/mach-real6410.c
>> +++ b/arch/arm/mach-s3c64xx/mach-real6410.c
>> @@ -119,36 +119,32 @@ static struct platform_device real6410_device_eth = {
>>
>> ?static struct s3c_fb_pd_win real6410_fb_win[] = {
>> ? ? ? {
>> - ? ? ? ? ? ? .win_mode ? ? ? = { ? ? /* 4.3" 480x272 */
>> - ? ? ? ? ? ? ? ? ? ? .left_margin ? ?= 3,
>> - ? ? ? ? ? ? ? ? ? ? .right_margin ? = 2,
>> - ? ? ? ? ? ? ? ? ? ? .upper_margin ? = 1,
>> - ? ? ? ? ? ? ? ? ? ? .lower_margin ? = 1,
>> - ? ? ? ? ? ? ? ? ? ? .hsync_len ? ? ?= 40,
>> - ? ? ? ? ? ? ? ? ? ? .vsync_len ? ? ?= 1,
>> - ? ? ? ? ? ? ? ? ? ? .xres ? ? ? ? ? = 480,
>> - ? ? ? ? ? ? ? ? ? ? .yres ? ? ? ? ? = 272,
>> - ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .max_bpp ? ? ? ?= 32,
>> ? ? ? ? ? ? ? .default_bpp ? ?= 16,
>> + ? ? ? ? ? ? .xres ? ? ? ? ? = 480,
>> + ? ? ? ? ? ? .yres ? ? ? ? ? = 272,
>> ? ? ? }, {
>> - ? ? ? ? ? ? .win_mode ? ? ? = { ? ? /* 7.0" 800x480 */
>> - ? ? ? ? ? ? ? ? ? ? .left_margin ? ?= 8,
>> - ? ? ? ? ? ? ? ? ? ? .right_margin ? = 13,
>> - ? ? ? ? ? ? ? ? ? ? .upper_margin ? = 7,
>> - ? ? ? ? ? ? ? ? ? ? .lower_margin ? = 5,
>> - ? ? ? ? ? ? ? ? ? ? .hsync_len ? ? ?= 3,
>> - ? ? ? ? ? ? ? ? ? ? .vsync_len ? ? ?= 1,
>> - ? ? ? ? ? ? ? ? ? ? .xres ? ? ? ? ? = 800,
>> - ? ? ? ? ? ? ? ? ? ? .yres ? ? ? ? ? = 480,
>> - ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .max_bpp ? ? ? ?= 32,
>> ? ? ? ? ? ? ? .default_bpp ? ?= 16,
>> + ? ? ? ? ? ? .xres ? ? ? ? ? = 800,
>> + ? ? ? ? ? ? .yres ? ? ? ? ? = 480,
>> ? ? ? },
>> ?};
>>
>> +static struct fb_videomode real6410_lcd_timing = {
>> + ? ? .left_margin ? ?= 3,
>> + ? ? .right_margin ? = 2,
>> + ? ? .upper_margin ? = 1,
>> + ? ? .lower_margin ? = 1,
>> + ? ? .hsync_len ? ? ?= 40,
>> + ? ? .vsync_len ? ? ?= 1,
>> + ? ? .xres ? ? ? ? ? = 800,
>> + ? ? .yres ? ? ? ? ? = 480,
>> +};
>
>
> What is the difference between mini6410_lcd_timing and real6410_lcd_timing?
> In my opinion, it would be good as follows:
>
> +static struct fb_videomode real6410_lcd_timing = {
> + ? ? ? .left_margin ? ?= 8,
> + ? ? ? .right_margin ? = 13,
> + ? ? ? .upper_margin ? = 7,
> + ? ? ? .lower_margin ? = 5,
> + ? ? ? .hsync_len ? ? ?= 3,
> + ? ? ? .vsync_len ? ? ?= 1,
> + ? ? ? .xres ? ? ? ? ? = 800,
> + ? ? ? .yres ? ? ? ? ? = 480,
> +};
>
>

Before this patch series, both real6410 and mini6410 had 'default_win'
= 0 in the platform data. And, the s3c-fb driver selected the video
timing from the window selected by the default_win parameter in s3c-fb
platform data, i.e window 0 for both mini6440 and real6410. So, in
this patch, while moving the timing values out of window data, the
timing values for window 0 was selected.

The timing value for window 1 was never used on mini6410 and real6410.
So I would suggest to use timing value of window 0 in this patch.

Thanks for your comments.

Regards,
Thomas.


From arnd at arndb.de  Tue Mar 13 06:10:42 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 10:10:42 +0000
Subject: [PATCH 4/7 v4] ARM: kirkwood: add dreamplug (fdt) support.
In-Reply-To: <0032addd7e94c5d4d1a3a0be77fe79bcffee53db.1331601448.git.jason@lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
 <0032addd7e94c5d4d1a3a0be77fe79bcffee53db.1331601448.git.jason@lakedaemon.net>
Message-ID: <201203131010.43095.arnd@arndb.de>

On Tuesday 13 March 2012, Jason Cooper wrote:
> Initially, copied guruplug-setup.c and did s/guruplug/dreamplug/g.
> Then, switched to SPI based NOR flash.
> 
> After talking to Arnd Bergman, chose an incremental approach to adding
> devicetree support.  First, we use the dtb to tell us we are on the
> dreamplug, then we gradually port over drivers.
> 
> Driver porting will start with the uart (see next patch), and progress
> from there.  Next, all drivers not needing common clock (kirkwood_tclk)
> or pinmux.  Then, remain drivers as that support hits the tree.
> 
> We need to absorb kirkwood_init() into kirkwood_dt_init() so that as we
> convert drivers, we can remove the platform call, eg
> kirkwood_rtc_init().  This maintains compatibility with non-fdt
> configurations because they still call kirkwood_init() in common.c.
> 
> As drivers are converted, we will reinstate the 'static' qualifier in
> common.c.
> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>

Patches 4 and 5 both look ok, but since I merged the earlier versions
of these into the stable next/board branch of arm-soc.git, you will have
to generate these as incremental patches now, and adapt the changeset
comments accordingly.

One small issue:

> --- a/arch/arm/mach-kirkwood/Kconfig
> +++ b/arch/arm/mach-kirkwood/Kconfig
> @@ -44,6 +44,20 @@ config MACH_GURUPLUG
>  	  Say 'Y' here if you want your kernel to support the
>  	  Marvell GuruPlug Reference Board.
>  
> +config ARCH_KIRKWOOD_DT
> +	bool "Marvell Kirkwood Flattened Device Tree"
> +	select USE_OF
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  Marvell Kirkwood using flattened device tree.
> +
> +config MACH_DREAMPLUG_DT
> +	bool "Marvell DreamPlug (Flattened Device Tree)"
> +	select ARCH_KIRKWOOD_DT
> +	help
> +	  Say 'Y' here if you want your kernel to support the
> +	  Marvell DreamPlug (Flattened Device Tree).
> +

You allow ARCH_KIRKWOOD_DT to be enabled without also enabling
dreamplug. That is ok, but

> +
> +	if (of_machine_is_compatible("globalscale,dreamplug"))
> +		dreamplug_init();
> +

you call a function from dreamplug.o in board-dt.o and

> +/* board init functions for drivers not converted to fdt */
> +void dreamplug_init(void);

you have an unconditional forward declaration in the header.

The idiomatic way to deal with this is to replace turn the
declaration into

#ifdef CONFIG_DREAMPLUG_DT
void dreamplug_init(void);
#else
static inline void dreamplug_init(void) {}
#endif

	Arnd


From linus.walleij at linaro.org  Tue Mar 13 06:13:26 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 13 Mar 2012 11:13:26 +0100
Subject: [PATCH 0/5] pinctrl: add new Samsung pinctrl driver and add
 Exynos4 support
In-Reply-To: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CACRpkdYB4ambuDeMUX1kZn793xxfaaNjQ56EB4C8OAykMxoPJQ@mail.gmail.com>

On Sun, Mar 11, 2012 at 1:46 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:

> This patch series adds new pinctrl driver for Samsung SoC's. The driver supports
> a gpiolib interface as well since Samsung SoC's have a combined pinmux/pinctrl
> and gpio controller.

Overall this all looks good to me Thomas!
I will provide detailed review if/when it is more ripe for merge.

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Tue Mar 13 06:15:25 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 13 Mar 2012 10:15:25 +0000
Subject: Conflict between Versatile Express DT conversion and local
 timer updates
In-Reply-To: <4F5F15ED.2010602@arm.com>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <20120312235951.GA31601@n2100.arm.linux.org.uk>
 <CAOesGMjt26JgySpcqVT+PsSgGq9cxQWn+msG4DSwo=2ykGz91A@mail.gmail.com>
 <4F5F15ED.2010602@arm.com>
Message-ID: <20120313101525.GA569@n2100.arm.linux.org.uk>

On Tue, Mar 13, 2012 at 09:39:57AM +0000, Marc Zyngier wrote:
> On 13/03/12 01:23, Olof Johansson wrote:
> > Hi,
> > 
> > On Mon, Mar 12, 2012 at 4:59 PM, Russell King - ARM Linux
> > <linux at arm.linux.org.uk> wrote:
> >> On Mon, Mar 12, 2012 at 11:10:16PM +0000, Russell King - ARM Linux wrote:
> >>> Marc, Pawel,
> >>>
> >>> Your changes are conflicting badly.  Seriously badly.  So badly that I'm
> >>> not bothering to fix the conflicts because I can't work out what the fix
> >>> should be.
> >>>
> >>> You both work for the same frigging organization and yet you seem to
> >>> work completely independently (I really don't care if you work in
> >>> different departments - the fact of the matter is you're touching the
> >>> same code in completely different ways with zero coordination between
> >>> yourselves.  That's simply broken workflow.)
> >>>
> >>> For example, Marc's deleting arch/arm/plat-versatile/localtimer.c, but
> >>> Pawel is modifying it to add DT support for Versatile Express.  The
> >>> correct solution?  Hell knows.  And I don't want a solution to the merge
> >>> conflict.  I want the merge conflict to go away (because I'm not frigging
> >>> around applying the same git-rerere immune fixes to a tree I'm regenerating
> >>> each night for the kernel autobuilder.)
> >>>
> >>> I'm getting conflicts in arch/arm/mach-vexpress/ct-ca9x4.c and
> >>> arch/arm/mach-ux500/timer.c as well, which I'm not going to bother trying
> >>> to sort out - the obvious solution for ux500/timer.c doesn't look right.
> >>>
> >>> I've a mind to drop the localtimer changes on the floor until after this
> >>> merge window, but unfortunately they're part of devel-stable so I can't.
> >>
> >> Correction: I haven't been pushing out my devel-stable branch for
> >> apparantly two months (according to gitweb, and no one noticed?), so I
> >> _could_ drop the merge of Marc's tree until the conflicts can be sanely
> >> resolved.
> > 
> > I haven't noticed because I stopped tracking your tree directly when
> > you were having server load issues; I tend to have kept an eye on
> > linux-next-level breakage instead, but probably not as close as I
> > should have.
> > 
> > Dropping Marc's branch and having him either resubmit on top of
> > arm-soc like the io cleanup was done, or pull it in as an early
> > dependency for 3.5 and stage it in an for-armsoc branch sounds like
> > two good options to me, with no real preference in either direction.
> 
> I'm happy to rebase my patches on anything that will make the merge
> easier (IOW conflict-less).
> 
> Russell, would you prefer this series to go via armsoc? This seems the
> cleanest solution for the time being.

With a lot of these core ARM changes, there's a very fine line between
whether they are core ARM changes or whether they're platform level
changes (many core ARM changes will impact lots of platforms.)  I'm just
wondering if there's any point to taking these changes through my tree.
It seems utterly pointless if they're going to keep conflicting with
platform stuff.


From thomas.abraham at linaro.org  Tue Mar 13 06:18:24 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 13 Mar 2012 15:48:24 +0530
Subject: [PATCH 0/5] pinctrl: add new Samsung pinctrl driver and add
 Exynos4 support
In-Reply-To: <CACRpkdYB4ambuDeMUX1kZn793xxfaaNjQ56EB4C8OAykMxoPJQ@mail.gmail.com>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <CACRpkdYB4ambuDeMUX1kZn793xxfaaNjQ56EB4C8OAykMxoPJQ@mail.gmail.com>
Message-ID: <CAJuYYwSUepRJuwdtDUGu6frCsHvvtmDEUrXEHKitYJppWwL0aw@mail.gmail.com>

On 13 March 2012 15:43, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Sun, Mar 11, 2012 at 1:46 PM, Thomas Abraham
> <thomas.abraham at linaro.org> wrote:
>
>> This patch series adds new pinctrl driver for Samsung SoC's. The driver supports
>> a gpiolib interface as well since Samsung SoC's have a combined pinmux/pinctrl
>> and gpio controller.
>
> Overall this all looks good to me Thomas!
> I will provide detailed review if/when it is more ripe for merge.

Thanks linus for having a look. The missing bits in the driver are
wakeup interrupt and gpio interrupt support. Without these, it would
not be possible to meaningfully demonstrate a fully functional system
using the pinctrl and gpiolib driver for Exynos4.

Regards,
Thomas.

>
> Yours,
> Linus Walleij


From w.sang at pengutronix.de  Tue Mar 13 06:22:08 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 13 Mar 2012 11:22:08 +0100
Subject: [PATCH 1/5 v3] i2c/gpio: add DT support
In-Reply-To: <20120313091104.GE18320@game.jcrosoft.org>
References: <1331196635-27203-1-git-send-email-plagnioj@jcrosoft.com>
 <20120313073748.GA7746@pengutronix.de>
 <20120313091104.GE18320@game.jcrosoft.org>
Message-ID: <20120313102208.GA2488@pengutronix.de>


> will update and send it via AT91  with your ack

Please wait with my ack until I saw the update.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From jean.pihet at newoldbits.com  Tue Mar 13 06:26:15 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Tue, 13 Mar 2012 11:26:15 +0100
Subject: [PATCH 0/6] ARM: OMAP3+: smartreflex: add class support
Message-ID: <1331634381-31436-1-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Add the class support so that various classes of operation can be
implemented (class 1p5 etc.).

Based on linux-omap's master branch (3.3.0-rc6), commit
85244e0edd240da2004bb2ab7cbcbc67a336f20d


Nishanth Menon (6):
  ARM: OMAP3+: SmartReflex: introduce class init, deinit and priv data
  ARM: OMAP3+: SmartReflex: introduce notifiers flags
  ARM: OMAP3+: SmartReflex: introduce notifier_control
  ARM: OMAP3+: SmartReflex: disable spamming interrupts
  ARM: OMAP3+: SmartReflex: introduce class private data per voltage
    domain
  ARM: OMAP3+: SmartReflex Class3: restrict CPU to run on

 arch/arm/mach-omap2/smartreflex-class3.c |   15 ++-
 arch/arm/mach-omap2/smartreflex.c        |  193 ++++++++++++++++++++++++++++--
 arch/arm/mach-omap2/smartreflex.h        |   30 ++++-
 3 files changed, 222 insertions(+), 16 deletions(-)

-- 
1.7.5.4



From jean.pihet at newoldbits.com  Tue Mar 13 06:26:16 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Tue, 13 Mar 2012 11:26:16 +0100
Subject: [PATCH 1/6] ARM: OMAP3+: SmartReflex: introduce class init,
 deinit and priv data
In-Reply-To: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
References: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331634381-31436-2-git-send-email-j-pihet@ti.com>

From: Nishanth Menon <nm at ti.com>

Certain class drivers such as class 1.5 drivers, will need specific
notification that they have to be inited up or deinited independent
of smart reflex operation. They also may need private data to be
used for operations of their own, provide the same.
This allows the class driver to initialize it's internal data structures
on a need basis in preparation for the specific domain's autocomp usage.
The resultant operation is as follows:
when autocomp is set to 1 -> class drivers' init is called
The existing enable/disable is still used as before by the SmartReflex
core driver to enable disable the class operation.
When autocomp is set to 0 -> class drivers' deinit is called, signaling
the end of usage for that domain.

Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |   15 +++++++++++++++
 arch/arm/mach-omap2/smartreflex.h |    6 ++++++
 2 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 008fbd7..058255a 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -226,6 +226,13 @@ static void sr_start_vddautocomp(struct omap_sr *sr)
 		return;
 	}
 
+	if (sr_class->init &&
+	    sr_class->init(sr->voltdm, sr_class->class_priv_data)) {
+		dev_err(&sr->pdev->dev,
+			"%s: SRClass initialization failed\n", __func__);
+		return;
+	}
+
 	if (!sr_class->enable(sr->voltdm))
 		sr->autocomp_active = true;
 }
@@ -241,6 +248,14 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
 
 	if (sr->autocomp_active) {
 		sr_class->disable(sr->voltdm, 1);
+		if (sr_class->deinit &&
+		    sr_class->deinit(sr->voltdm,
+			    sr_class->class_priv_data)) {
+			dev_err(&sr->pdev->dev,
+				"%s: SR[%d]Class deinitialization failed\n",
+				__func__, sr->srid);
+		}
+
 		sr->autocomp_active = false;
 	}
 }
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 5809141..dd5b21e 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -177,6 +177,8 @@ struct omap_smartreflex_dev_attr {
  *
  * @enable:		API to enable a particular class smaartreflex.
  * @disable:		API to disable a particular class smartreflex.
+ * @init:		API to do class specific initialization (optional)
+ * @deinit:		API to do class specific deinitialization (optional)
  * @configure:		API to configure a particular class smartreflex.
  * @notify:		API to notify the class driver about an event in SR.
  *			Not needed for class3.
@@ -184,14 +186,18 @@ struct omap_smartreflex_dev_attr {
  * @class_type:		specify which smartreflex class.
  *			Can be used by the SR driver to take any class
  *			based decisions.
+ * @class_priv_data:	Class specific private data (optional)
  */
 struct omap_sr_class_data {
 	int (*enable)(struct voltagedomain *voltdm);
 	int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
+	int (*init)(struct voltagedomain *voltdm, void *class_priv_data);
+	int (*deinit)(struct voltagedomain *voltdm, void *class_priv_data);
 	int (*configure)(struct voltagedomain *voltdm);
 	int (*notify)(struct voltagedomain *voltdm, u32 status);
 	u8 notify_flags;
 	u8 class_type;
+	void *class_priv_data;
 };
 
 /**
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Tue Mar 13 06:26:17 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Tue, 13 Mar 2012 11:26:17 +0100
Subject: [PATCH 2/6] ARM: OMAP3+: SmartReflex: introduce notifiers flags
In-Reply-To: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
References: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331634381-31436-3-git-send-email-j-pihet@ti.com>

From: Nishanth Menon <nm at ti.com>

SmartReflex IP V1 and V2 have different registers and offsets.
Currently, we pass the status as is to the class driver. However,
since we don't pass the version of the underlying SR hardware
to the Class driver, it will not be unable to make consistent
sense of the status bits coming over to it.

A class driver should be able to function without dependency
on the exact IP version it is actually running on. We hence
introduce our own translation in software level for a generic
notification flag.

As part of this change, we will now call the notifier if we get
a match with the notifier flags that the class driver requested.

Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |   79 ++++++++++++++++++++++++++++++++++++-
 arch/arm/mach-omap2/smartreflex.h |    6 +++
 2 files changed, 83 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 058255a..7977018 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -121,25 +121,100 @@ static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
 	return ERR_PTR(-ENODATA);
 }
 
+static inline u32 notifier_to_irqen_v1(u8 notify_flags)
+{
+	u32 val;
+
+	val = (notify_flags & SR_NOTIFY_MCUACCUM) ?
+		ERRCONFIG_MCUACCUMINTEN : 0;
+	val |= (notify_flags & SR_NOTIFY_MCUVALID) ?
+		ERRCONFIG_MCUVALIDINTEN : 0;
+	val |= (notify_flags & SR_NOTIFY_MCUBOUND) ?
+		ERRCONFIG_MCUBOUNDINTEN : 0;
+	val |= (notify_flags & SR_NOTIFY_MCUDISACK) ?
+		ERRCONFIG_MCUDISACKINTEN : 0;
+
+	return val;
+}
+
+static inline u32 notifier_to_irqen_v2(u8 notify_flags)
+{
+	u32 val;
+
+	val = (notify_flags & SR_NOTIFY_MCUACCUM) ?
+		IRQENABLE_MCUACCUMINT : 0;
+	val |= (notify_flags & SR_NOTIFY_MCUVALID) ?
+		IRQENABLE_MCUVALIDINT : 0;
+	val |= (notify_flags & SR_NOTIFY_MCUBOUND) ?
+		IRQENABLE_MCUBOUNDSINT : 0;
+	val |= (notify_flags & SR_NOTIFY_MCUDISACK) ?
+		IRQENABLE_MCUDISABLEACKINT : 0;
+
+	return val;
+}
+
+static inline u8 irqstat_to_notifier_v1(u32 status)
+{
+	u8 val;
+
+	val = (status & ERRCONFIG_MCUACCUMINTST) ?
+		SR_NOTIFY_MCUACCUM : 0;
+	val |= (status & ERRCONFIG_MCUVALIDINTEN) ?
+		SR_NOTIFY_MCUVALID : 0;
+	val |= (status & ERRCONFIG_MCUBOUNDINTEN) ?
+		SR_NOTIFY_MCUBOUND : 0;
+	val |= (status & ERRCONFIG_MCUDISACKINTEN) ?
+		SR_NOTIFY_MCUDISACK : 0;
+
+	return val;
+}
+
+static inline u8 irqstat_to_notifier_v2(u32 status)
+{
+	u8 val;
+
+	val = (status & IRQENABLE_MCUACCUMINT) ?
+		SR_NOTIFY_MCUACCUM : 0;
+	val |= (status & IRQENABLE_MCUVALIDINT) ?
+		SR_NOTIFY_MCUVALID : 0;
+	val |= (status & IRQENABLE_MCUBOUNDSINT) ?
+		SR_NOTIFY_MCUBOUND : 0;
+	val |= (status & IRQENABLE_MCUDISABLEACKINT) ?
+		SR_NOTIFY_MCUDISACK : 0;
+
+	return val;
+}
+
+
 static irqreturn_t sr_interrupt(int irq, void *data)
 {
 	struct omap_sr *sr_info = data;
 	u32 status = 0;
+	u32 value = 0;
 
 	switch (sr_info->ip_type) {
 	case SR_TYPE_V1:
+		/* Status bits are one bit before enable bits in v1 */
+		value = notifier_to_irqen_v1(sr_class->notify_flags) >> 1;
+
 		/* Read the status bits */
 		status = sr_read_reg(sr_info, ERRCONFIG_V1);
+		status &= value;
 
 		/* Clear them by writing back */
-		sr_write_reg(sr_info, ERRCONFIG_V1, status);
+		sr_modify_reg(sr_info, ERRCONFIG_V1, value, status);
+
+		value = irqstat_to_notifier_v1(status);
 		break;
 	case SR_TYPE_V2:
+		value = notifier_to_irqen_v2(sr_class->notify_flags);
 		/* Read the status bits */
 		status = sr_read_reg(sr_info, IRQSTATUS);
+		status &= value;
 
 		/* Clear them by writing back */
 		sr_write_reg(sr_info, IRQSTATUS, status);
+		value = irqstat_to_notifier_v2(status);
 		break;
 	default:
 		dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n",
@@ -148,7 +223,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
 	}
 
 	if (sr_class->notify)
-		sr_class->notify(sr_info->voltdm, status);
+		sr_class->notify(sr_info->voltdm, value);
 
 	return IRQ_HANDLED;
 }
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index dd5b21e..da00f8c 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -142,6 +142,12 @@
 #define OMAP3430_SR_ERRWEIGHT		0x04
 #define OMAP3430_SR_ERRMAXLIMIT		0x02
 
+/* Smart reflex notifiers for class drivers to use */
+#define SR_NOTIFY_MCUDISACK		BIT(3)
+#define SR_NOTIFY_MCUBOUND		BIT(2)
+#define SR_NOTIFY_MCUVALID		BIT(1)
+#define SR_NOTIFY_MCUACCUM		BIT(0)
+
 /**
  * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
  *				pmic specific info to smartreflex driver
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Tue Mar 13 06:26:18 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Tue, 13 Mar 2012 11:26:18 +0100
Subject: [PATCH 3/6] ARM: OMAP3+: SmartReflex: introduce notifier_control
In-Reply-To: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
References: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331634381-31436-4-git-send-email-j-pihet@ti.com>

From: Nishanth Menon <nm at ti.com>

We need some mechanism from class drivers to control when notifiers
should be triggered and when not, currently we have none, which makes
Class driver usage of the interrupt events almost impossible.

We also ensure that disable/enable or irq is always guarenteed to be
paired. The need to do this is because of the mixture of interrupt based
and polling based operations that is implemented as the most optimal
strategy for various SmartReflex AVS class

Introduce an SmartReflex driver API for doing the same. This is useful
for SmartReflex AVS class 1.5 or 2 drivers.

Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |   65 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/smartreflex.h |    6 +++
 2 files changed, 71 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 7977018..dfe8075 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -45,6 +45,7 @@ struct omap_sr {
 	int				srid;
 	int				ip_type;
 	int				nvalue_count;
+	bool				irq_enabled;
 	bool				autocomp_active;
 	u32				clk_length;
 	u32				err_weight;
@@ -799,6 +800,70 @@ void sr_disable(struct voltagedomain *voltdm)
 }
 
 /**
+ * sr_notifier_control() - control the notifier mechanism
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ * @enable:	true to enable notifiers and false to disable the same
+ *
+ * SR modules allow an MCU interrupt mechanism that vary based on the IP
+ * revision, we allow the system to generate interrupt if the class driver
+ * has capability to handle the same. it is upto the class driver to ensure
+ * the proper sequencing and handling for a clean implementation. returns
+ * 0 if all goes fine, else returns failure results
+ */
+int sr_notifier_control(struct voltagedomain *voltdm, bool enable)
+{
+	struct omap_sr *sr = _sr_lookup(voltdm);
+	u32 value = 0;
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: sr corresponding to domain not found\n",
+				__func__);
+		return PTR_ERR(sr);
+	}
+	if (!sr->autocomp_active)
+		return -EINVAL;
+
+	/* If I could never register an ISR, why bother?? */
+	if (!(sr_class && sr_class->notify && sr_class->notify_flags &&
+			sr->irq)) {
+		dev_warn(&sr->pdev->dev,
+			"%s: unable to setup IRQ without handling mechanism\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	switch (sr->ip_type) {
+	case SR_TYPE_V1:
+		value = notifier_to_irqen_v1(sr_class->notify_flags);
+		sr_modify_reg(sr, ERRCONFIG_V1, value,
+				(enable) ? value : 0);
+		break;
+	case SR_TYPE_V2:
+		value = notifier_to_irqen_v2(sr_class->notify_flags);
+		sr_write_reg(sr, (enable) ? IRQENABLE_SET : IRQENABLE_CLR,
+				value);
+		break;
+	default:
+		 dev_warn(&sr->pdev->dev, "%s: unknown type of sr??\n",
+				 __func__);
+		return -EINVAL;
+	}
+
+	if (!enable)
+		sr_write_reg(sr, IRQSTATUS, value);
+
+	if (enable != sr->irq_enabled) {
+		if (enable)
+			enable_irq(sr->irq);
+		else
+			disable_irq(sr->irq);
+		sr->irq_enabled = enable;
+	}
+
+	return 0;
+}
+
+/**
  * sr_register_class() - API to register a smartreflex class parameters.
  * @class_data:	The structure containing various sr class specific data.
  *
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index da00f8c..2b0ef0e 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -251,6 +251,7 @@ void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
 /* Smartreflex driver hooks to be called from Smartreflex class driver */
 int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
 void sr_disable(struct voltagedomain *voltdm);
+int sr_notifier_control(struct voltagedomain *voltdm, bool enable);
 int sr_configure_errgen(struct voltagedomain *voltdm);
 int sr_disable_errgen(struct voltagedomain *voltdm);
 int sr_configure_minmax(struct voltagedomain *voltdm);
@@ -260,6 +261,11 @@ int sr_register_class(struct omap_sr_class_data *class_data);
 #else
 static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
 static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+static inline int sr_notifier_control(struct voltagedomain *voltdm,
+		bool enable)
+{
+	return -EINVAL;
+}
 static inline void omap_sr_disable_reset_volt(
 		struct voltagedomain *voltdm) {}
 static inline void omap_sr_register_pmic(
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Tue Mar 13 06:26:19 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Tue, 13 Mar 2012 11:26:19 +0100
Subject: [PATCH 4/6] ARM: OMAP3+: SmartReflex: disable spamming interrupts
In-Reply-To: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
References: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331634381-31436-5-git-send-email-j-pihet@ti.com>

From: Nishanth Menon <nm at ti.com>

At times with bad SR configurations, especially during silicon bring-ups,
we could get continuous spurious interrupts which end up hanging the
platform in the form of an ISR call for status bits that are
automatically enabled by the hardware without any software clearing
option.

If we detect scenarios where ISR was called without the corresponding
notification bit being set, instead of hanging up the system,
we will disable interrupt after noting the event in the system log
to try and keep system sanity and allow developer to debug and fix
the condition.

Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |   21 +++++++++++++++++++--
 1 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index dfe8075..8a10c0a 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -223,8 +223,25 @@ static irqreturn_t sr_interrupt(int irq, void *data)
 		return IRQ_NONE;
 	}
 
-	if (sr_class->notify)
-		sr_class->notify(sr_info->voltdm, value);
+	/* Attempt some resemblance of recovery! */
+	if (!value) {
+		dev_err(&sr_info->pdev->dev, "%s: Spurious interrupt!"
+			"status = 0x%08x. Disabling to prevent spamming!!\n",
+			__func__, status);
+		disable_irq_nosync(sr_info->irq);
+		sr_info->irq_enabled = false;
+	} else {
+		/* If the caller reports inability to handle, disable as well */
+		if (sr_class->notify &&
+		    sr_class->notify(sr_info->voltdm, value)) {
+			dev_err(&sr_info->pdev->dev, "%s: Callback cant handle!"
+				"status=0x%08x. Disabling to prevent spam!!\n",
+				__func__, status);
+			disable_irq_nosync(sr_info->irq);
+			sr_info->irq_enabled = false;
+		}
+
+	}
 
 	return IRQ_HANDLED;
 }
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Tue Mar 13 06:26:21 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Tue, 13 Mar 2012 11:26:21 +0100
Subject: [PATCH 6/6] ARM: OMAP3+: SmartReflex Class3: restrict CPU to run on
In-Reply-To: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
References: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331634381-31436-7-git-send-email-j-pihet@ti.com>

From: Nishanth Menon <nm at ti.com>

Use SmartReflex AVS Class3 initialization only for OMAP343x family of
processors.

Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/smartreflex-class3.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 9dcda93..735937a 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -11,6 +11,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <plat/cpu.h>
 #include "smartreflex.h"
 
 static int sr_class3_enable(struct voltagedomain *voltdm,
@@ -58,6 +59,10 @@ static struct omap_sr_class_data class3_data = {
 /* Smartreflex Class3 init API to be called from board file */
 static int __init sr_class3_init(void)
 {
+	/* Enable this class only for OMAP343x */
+	if (!cpu_is_omap343x())
+		return -EINVAL;
+
 	pr_info("SmartReflex Class3 initialized\n");
 	return sr_register_class(&class3_data);
 }
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Tue Mar 13 06:26:20 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Tue, 13 Mar 2012 11:26:20 +0100
Subject: [PATCH 5/6] ARM: OMAP3+: SmartReflex: introduce class private data
 per voltage domain
In-Reply-To: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
References: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331634381-31436-6-git-send-email-j-pihet@ti.com>

From: Nishanth Menon <nm at ti.com>

Introduce private data for class drivers to operate on per
voltage domain. This removes the necessity for drivers such
as SmartReflex AVS Class 1.5 drivers from maintaining
a special lookup table which does not scale when number of
voltage domains change depending on silicon. It also makes
the life of such class drivers to be faster without having
to do a double lookup to get to their voltage domain specific
private data

Signed-off-by: Nishanth Menon <nm at ti.com>
Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/smartreflex-class3.c |   10 +++++++---
 arch/arm/mach-omap2/smartreflex.c        |   23 +++++++++++++----------
 arch/arm/mach-omap2/smartreflex.h        |   16 ++++++++++------
 3 files changed, 30 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 955566e..9dcda93 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -13,7 +13,8 @@
 
 #include "smartreflex.h"
 
-static int sr_class3_enable(struct voltagedomain *voltdm)
+static int sr_class3_enable(struct voltagedomain *voltdm,
+			    void *voltdm_cdata)
 {
 	unsigned long volt = voltdm_get_voltage(voltdm);
 
@@ -27,7 +28,9 @@ static int sr_class3_enable(struct voltagedomain *voltdm)
 	return sr_enable(voltdm, volt);
 }
 
-static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
+static int sr_class3_disable(struct voltagedomain *voltdm,
+			     void *voltdm_cdata,
+			     int is_volt_reset)
 {
 	sr_disable_errgen(voltdm);
 	omap_vp_disable(voltdm);
@@ -38,7 +41,8 @@ static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
 	return 0;
 }
 
-static int sr_class3_configure(struct voltagedomain *voltdm)
+static int sr_class3_configure(struct voltagedomain *voltdm,
+			       void *voltdm_cdata)
 {
 	return sr_configure_errgen(voltdm);
 }
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 8a10c0a..c351af6 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -40,6 +40,8 @@ struct omap_sr {
 	struct platform_device		*pdev;
 	struct omap_sr_nvalue_table	*nvalue_table;
 	struct voltagedomain		*voltdm;
+	/* Managed by class driver as needed */
+	void				*voltdm_cdata;
 	struct dentry			*dbg_dir;
 	unsigned int			irq;
 	int				srid;
@@ -232,8 +234,8 @@ static irqreturn_t sr_interrupt(int irq, void *data)
 		sr_info->irq_enabled = false;
 	} else {
 		/* If the caller reports inability to handle, disable as well */
-		if (sr_class->notify &&
-		    sr_class->notify(sr_info->voltdm, value)) {
+		if (sr_class->notify && sr_class->notify(sr_info->voltdm,
+						sr_info->voltdm_cdata, value)) {
 			dev_err(&sr_info->pdev->dev, "%s: Callback cant handle!"
 				"status=0x%08x. Disabling to prevent spam!!\n",
 				__func__, status);
@@ -320,13 +322,14 @@ static void sr_start_vddautocomp(struct omap_sr *sr)
 	}
 
 	if (sr_class->init &&
-	    sr_class->init(sr->voltdm, sr_class->class_priv_data)) {
+	    sr_class->init(sr->voltdm, &sr->voltdm_cdata,
+			   sr_class->class_priv_data)) {
 		dev_err(&sr->pdev->dev,
 			"%s: SRClass initialization failed\n", __func__);
 		return;
 	}
 
-	if (!sr_class->enable(sr->voltdm))
+	if (!sr_class->enable(sr->voltdm, sr->voltdm_cdata))
 		sr->autocomp_active = true;
 }
 
@@ -340,9 +343,9 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
 	}
 
 	if (sr->autocomp_active) {
-		sr_class->disable(sr->voltdm, 1);
+		sr_class->disable(sr->voltdm, sr->voltdm_cdata, 1);
 		if (sr_class->deinit &&
-		    sr_class->deinit(sr->voltdm,
+		    sr_class->deinit(sr->voltdm, &sr->voltdm_cdata,
 			    sr_class->class_priv_data)) {
 			dev_err(&sr->pdev->dev,
 				"%s: SR[%d]Class deinitialization failed\n",
@@ -763,7 +766,7 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 		return 0;
 
 	/* Configure SR */
-	ret = sr_class->configure(voltdm);
+	ret = sr_class->configure(voltdm, sr->voltdm_cdata);
 	if (ret)
 		return ret;
 
@@ -945,7 +948,7 @@ void omap_sr_enable(struct voltagedomain *voltdm)
 		return;
 	}
 
-	sr_class->enable(voltdm);
+	sr_class->enable(voltdm, sr->voltdm_cdata);
 }
 
 /**
@@ -978,7 +981,7 @@ void omap_sr_disable(struct voltagedomain *voltdm)
 		return;
 	}
 
-	sr_class->disable(voltdm, 0);
+	sr_class->disable(voltdm, sr->voltdm_cdata, 0);
 }
 
 /**
@@ -1011,7 +1014,7 @@ void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
 		return;
 	}
 
-	sr_class->disable(voltdm, 1);
+	sr_class->disable(voltdm, sr->voltdm_cdata, 1);
 }
 
 /**
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 2b0ef0e..1fbafe7 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -195,12 +195,16 @@ struct omap_smartreflex_dev_attr {
  * @class_priv_data:	Class specific private data (optional)
  */
 struct omap_sr_class_data {
-	int (*enable)(struct voltagedomain *voltdm);
-	int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
-	int (*init)(struct voltagedomain *voltdm, void *class_priv_data);
-	int (*deinit)(struct voltagedomain *voltdm, void *class_priv_data);
-	int (*configure)(struct voltagedomain *voltdm);
-	int (*notify)(struct voltagedomain *voltdm, u32 status);
+	int (*enable)(struct voltagedomain *voltdm, void *voltdm_cdata);
+	int (*disable)(struct voltagedomain *voltdm, void *voltdm_cdata,
+		       int is_volt_reset);
+	int (*init)(struct voltagedomain *voltdm, void **voltdm_cdata,
+		    void *class_priv_data);
+	int (*deinit)(struct voltagedomain *voltdm, void **voltdm_cdata,
+		      void *class_priv_data);
+	int (*configure)(struct voltagedomain *voltdm, void *voltdm_cdata);
+	int (*notify)(struct voltagedomain *voltdm, void *voltdm_cdata,
+		      u32 status);
 	u8 notify_flags;
 	u8 class_type;
 	void *class_priv_data;
-- 
1.7.5.4



From vishwanath.bs at ti.com  Tue Mar 13 06:34:13 2012
From: vishwanath.bs at ti.com (Vishwanath Sripathy)
Date: Tue, 13 Mar 2012 16:04:13 +0530
Subject: [PATCH 6/6] ARM: OMAP3+: SmartReflex Class3: restrict CPU to run
 on
In-Reply-To: <1331634381-31436-7-git-send-email-j-pihet@ti.com>
References: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
 <1331634381-31436-7-git-send-email-j-pihet@ti.com>
Message-ID: <ef588847b5162cc1174c7cdeffc74ffd@mail.gmail.com>

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of jean.pihet at newoldbits.com
> Sent: Tuesday, March 13, 2012 3:56 PM
> To: linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; Kevin Hilman
> Cc: Nishanth Menon; Jean Pihet
> Subject: [PATCH 6/6] ARM: OMAP3+: SmartReflex Class3: restrict CPU
> to run on
>
> From: Nishanth Menon <nm at ti.com>
>
> Use SmartReflex AVS Class3 initialization only for OMAP343x family
> of
> processors.
>
> Signed-off-by: Nishanth Menon <nm at ti.com>
> Signed-off-by: Jean Pihet <j-pihet at ti.com>
> ---
>  arch/arm/mach-omap2/smartreflex-class3.c |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/smartreflex-class3.c
> b/arch/arm/mach-omap2/smartreflex-class3.c
> index 9dcda93..735937a 100644
> --- a/arch/arm/mach-omap2/smartreflex-class3.c
> +++ b/arch/arm/mach-omap2/smartreflex-class3.c
> @@ -11,6 +11,7 @@
>   * published by the Free Software Foundation.
>   */
>
> +#include <plat/cpu.h>
>  #include "smartreflex.h"
>
>  static int sr_class3_enable(struct voltagedomain *voltdm,
> @@ -58,6 +59,10 @@ static struct omap_sr_class_data class3_data = {
>  /* Smartreflex Class3 init API to be called from board file */
>  static int __init sr_class3_init(void)
>  {
> +	/* Enable this class only for OMAP343x */
> +	if (!cpu_is_omap343x())
> +		return -EINVAL;
Wouldn't this break SR on OMAP3630 and OMAP4? Shouldn't this be done once
you have SR1.5 support in mainline?

Vishwa
> +
>  	pr_info("SmartReflex Class3 initialized\n");
>  	return sr_register_class(&class3_data);
>  }
> --
> 1.7.5.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-
> omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From s.hauer at pengutronix.de  Tue Mar 13 06:38:29 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 13 Mar 2012 11:38:29 +0100
Subject: [PATCH v6 3/3] clk: basic clock hardware types
In-Reply-To: <CAKGA1b=huAnG6tLoaGqoFoJnuEg-+rs8KLYVB1KF6_q73ot63A@mail.gmail.com>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-4-git-send-email-mturquette@linaro.org>
 <CAKGA1b=huAnG6tLoaGqoFoJnuEg-+rs8KLYVB1KF6_q73ot63A@mail.gmail.com>
Message-ID: <20120313103829.GR3852@pengutronix.de>

On Mon, Mar 12, 2012 at 10:50:09PM -0500, Matt Sealey wrote:
> Hi Mike,
> 
> Can I suggest/we discuss that we support fractional (i.e. represented
> by fixed point value with integer and fractional part) dividers in the
> common divider clock case, simplistically just adding a divider
> fractional width and shifting all the calculations by it (and fixing
> the "maxdiv" calculation as in a fractional case width of the divider
> area in the register is not an indicator of the actual maximum
> divider)? (I guess for the standard integer divider case, it would be
> continually shifting by 0 which might make the code a bit bigger, I
> don't think that would truly be a concern though?)

I have patches for this, see

git://git.pengutronix.de/git/imx/linux-2.6.git imx/work/imx-clkv6

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From m.szyprowski at samsung.com  Tue Mar 13 06:39:36 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 13 Mar 2012 11:39:36 +0100
Subject: [PATCHv2 0/3] Add support for DRM display subsystem
Message-ID: <1331635180-7207-1-git-send-email-m.szyprowski@samsung.com>

Hello,

This patch set adds support for Exynos DRM display subsystem for
Universal C210 and NURI boards. Exynos DRM driver has been merged to 3.3
kernel tree and provides unified and more powerful alternative for
s3c-fb and s5p-tv drivers. V2 includes update for the latest changes in
platform data structure (added 'panel' entry).

Best regards

Marek Szyprowski
Samsung Poland R&D Center

Patch summary:

Marek Szyprowski (3):
  ARM: Exynos: add platform device for core DRM subsystem
  ARM: Exynos: Add DRM core device support for Universal C210 board
  ARM: Exynos: Add DRM core support for NURI board

 arch/arm/mach-exynos/Kconfig               |    7 ++++++
 arch/arm/mach-exynos/Makefile              |    1 +
 arch/arm/mach-exynos/dev-drm.c             |   29 ++++++++++++++++++++++++
 arch/arm/mach-exynos/mach-nuri.c           |   33 ++++++++++++++++++++++++++++
 arch/arm/mach-exynos/mach-universal_c210.c |   33 ++++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h  |    2 +
 6 files changed, 105 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/dev-drm.c

-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 13 06:39:39 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 13 Mar 2012 11:39:39 +0100
Subject: [PATCHv2 3/3] ARM: Exynos: Add DRM core support for NURI board
In-Reply-To: <1331635180-7207-1-git-send-email-m.szyprowski@samsung.com>
References: <1331635180-7207-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1331635180-7207-4-git-send-email-m.szyprowski@samsung.com>

Add core DRM device and alternative platform device data for FIMD DRM
subdriver. Based on the initial patch by Joonyoung Shim
<jy0922.shim at samsung.com>

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/Kconfig     |    1 +
 arch/arm/mach-exynos/mach-nuri.c |   33 +++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 52cb248..db4b897 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -299,6 +299,7 @@ config MACH_NURI
 	select S5P_DEV_USB_EHCI
 	select S5P_SETUP_MIPIPHY
 	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DRM
 	select EXYNOS4_SETUP_FIMC
 	select EXYNOS4_SETUP_FIMD0
 	select EXYNOS4_SETUP_I2C1
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 7ac81ce..8049f93 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -25,6 +25,7 @@
 #include <linux/mmc/host.h>
 #include <linux/fb.h>
 #include <linux/pwm_backlight.h>
+#include <drm/exynos_drm.h>
 
 #include <video/platform_lcd.h>
 #include <media/m5mols.h>
@@ -210,6 +211,29 @@ static struct platform_device nuri_gpio_keys = {
 	},
 };
 
+#ifdef CONFIG_DRM_EXYNOS
+static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
+	.panel = {
+		.timing	= {
+			.xres		= 1024,
+			.yres		= 600,
+			.hsync_len	= 40,
+			.left_margin	= 79,
+			.right_margin	= 200,
+			.vsync_len	= 10,
+			.upper_margin	= 10,
+			.lower_margin	= 11,
+			.refresh	= 60,
+		},
+	},
+	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+			  VIDCON0_CLKSEL_LCD,
+	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+	.default_win	= 3,
+	.bpp		= 32,
+};
+
+#else
 /* Frame Buffer */
 static struct s3c_fb_pd_win nuri_fb_win0 = {
 	.win_mode = {
@@ -236,6 +260,7 @@ static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
 };
+#endif
 
 static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
 {
@@ -1341,6 +1366,9 @@ static struct platform_device *nuri_devices[] __initdata = {
 	&cam_vdda_fixed_rdev,
 	&cam_8m_12v_fixed_rdev,
 	&exynos4_bus_devfreq,
+#ifdef CONFIG_DRM_EXYNOS
+	&exynos_device_drm,
+#endif
 };
 
 static void __init nuri_map_io(void)
@@ -1372,7 +1400,12 @@ static void __init nuri_machine_init(void)
 	i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
 	s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
 
+#ifdef CONFIG_DRM_EXYNOS
+	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
+	exynos4_fimd0_gpio_setup_24bpp();
+#else
 	s5p_fimd0_set_platdata(&nuri_fb_pdata);
+#endif
 
 	nuri_camera_init();
 
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 13 06:39:38 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 13 Mar 2012 11:39:38 +0100
Subject: [PATCHv2 2/3] ARM: Exynos: Add DRM core device support for Universal
 C210 board
In-Reply-To: <1331635180-7207-1-git-send-email-m.szyprowski@samsung.com>
References: <1331635180-7207-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1331635180-7207-3-git-send-email-m.szyprowski@samsung.com>

Add core DRM device and alternative platform device data for FIMD DRM
subdriver. Based on the initial patch by Joonyoung Shim
<jy0922.shim at samsung.com>

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/Kconfig               |    1 +
 arch/arm/mach-exynos/mach-universal_c210.c |   33 ++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 9124ce9..52cb248 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -262,6 +262,7 @@ config MACH_UNIVERSAL_C210
 	select S5P_DEV_ONENAND
 	select S5P_DEV_TV
 	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DRM
 	select EXYNOS4_SETUP_FIMD0
 	select EXYNOS4_SETUP_I2C1
 	select EXYNOS4_SETUP_I2C3
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 57e4418..b8bd8ab 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -23,6 +23,7 @@
 #include <linux/i2c-gpio.h>
 #include <linux/i2c/mcs.h>
 #include <linux/i2c/atmel_mxt_ts.h>
+#include <drm/exynos_drm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -811,6 +812,29 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
 	/* Gyro, To be updated */
 };
 
+#ifdef CONFIG_DRM_EXYNOS
+static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
+	.panel = {
+		.timing	= {
+			.left_margin	= 16,
+			.right_margin	= 16,
+			.upper_margin	= 2,
+			.lower_margin	= 28,
+			.hsync_len	= 2,
+			.vsync_len	= 1,
+			.xres		= 480,
+			.yres		= 800,
+			.refresh	= 55,
+		},
+	},
+	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+			  VIDCON0_CLKSEL_LCD,
+	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
+			  | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+	.default_win	= 3,
+	.bpp		= 32,
+};
+#else
 /* Frame Buffer */
 static struct s3c_fb_pd_win universal_fb_win0 = {
 	.win_mode = {
@@ -838,6 +862,7 @@ static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
 			  | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
 };
+#endif
 
 static struct regulator_consumer_supply cam_vt_dio_supply =
 	REGULATOR_SUPPLY("vdd_core", "0-003c");
@@ -1047,6 +1072,9 @@ static struct platform_device *universal_devices[] __initdata = {
 	&s5p_device_onenand,
 	&s5p_device_fimd0,
 	&s5p_device_jpeg,
+#ifdef CONFIG_DRM_EXYNOS
+	&exynos_device_drm,
+#endif
 	&s5p_device_mfc,
 	&s5p_device_mfc_l,
 	&s5p_device_mfc_r,
@@ -1092,7 +1120,12 @@ static void __init universal_machine_init(void)
 	s5p_i2c_hdmiphy_set_platdata(NULL);
 	i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
 
+#ifdef CONFIG_DRM_EXYNOS
+	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
+	exynos4_fimd0_gpio_setup_24bpp();
+#else
 	s5p_fimd0_set_platdata(&universal_lcd_pdata);
+#endif
 
 	universal_touchkey_init();
 	i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 13 06:39:37 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 13 Mar 2012 11:39:37 +0100
Subject: [PATCHv2 1/3] ARM: Exynos: add platform device for core DRM subsystem
In-Reply-To: <1331635180-7207-1-git-send-email-m.szyprowski@samsung.com>
References: <1331635180-7207-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1331635180-7207-2-git-send-email-m.szyprowski@samsung.com>

Add platform device for Exynos DRM core. This device is used for
creating DRM user-space device and allocating memory for display buffers.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-exynos/Kconfig              |    5 +++++
 arch/arm/mach-exynos/Makefile             |    1 +
 arch/arm/mach-exynos/dev-drm.c            |   29 +++++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h |    2 ++
 4 files changed, 37 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/dev-drm.c

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 060414e..9124ce9 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -85,6 +85,11 @@ config EXYNOS4_DEV_AHCI
 	help
 	  Compile in platform device definitions for AHCI
 
+config EXYNOS_DEV_DRM
+	bool
+	help
+	  Compile in platform device definitions for core DRM device
+
 config EXYNOS4_SETUP_FIMD0
 	bool
 	help
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8631840..f67e882 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
 obj-y					+= dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
+obj-$(CONFIG_EXYNOS_DEV_DRM)		+= dev-drm.o
 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)	+= dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
 obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
diff --git a/arch/arm/mach-exynos/dev-drm.c b/arch/arm/mach-exynos/dev-drm.c
new file mode 100644
index 0000000..17c9c6e
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-drm.c
@@ -0,0 +1,29 @@
+/*
+ * linux/arch/arm/mach-exynos/dev-drm.c
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * EXYNOS - core DRM device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+#include <plat/devs.h>
+
+static u64 exynos_drm_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device exynos_device_drm = {
+	.name	= "exynos-drm",
+	.dev	= {
+		.dma_mask		= &exynos_drm_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	}
+};
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 2155d4a..62e6251 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -135,6 +135,8 @@ extern struct platform_device exynos4_device_pd[];
 extern struct platform_device exynos4_device_spdif;
 extern struct platform_device exynos4_device_sysmmu;
 
+extern struct platform_device exynos_device_drm;
+
 extern struct platform_device samsung_asoc_dma;
 extern struct platform_device samsung_asoc_idma;
 extern struct platform_device samsung_device_keypad;
-- 
1.7.1.569.g6f426



From b29396 at freescale.com  Tue Mar 13 06:58:22 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 13 Mar 2012 18:58:22 +0800
Subject: [PATCH 1/1] net: phylib: add error checking if no phy found
Message-ID: <1331636302-18256-1-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 drivers/net/phy/mdio_bus.c |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index 88cc5db..d8e044d 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -101,6 +101,7 @@ static struct class mdio_bus_class = {
 int mdiobus_register(struct mii_bus *bus)
 {
 	int i, err;
+	u32 phynum = 0;
 
 	if (NULL == bus || NULL == bus->name ||
 			NULL == bus->read ||
@@ -134,12 +135,20 @@ int mdiobus_register(struct mii_bus *bus)
 			if (IS_ERR(phydev)) {
 				err = PTR_ERR(phydev);
 				goto error;
+			} else if (phydev != NULL) {
+				phynum++;
 			}
 		}
 	}
 
+	if (!phynum) {
+		err = -ENODEV;
+		printk(KERN_ERR "%s: no phys found\n", bus->name);
+		goto error;
+	}
+
 	bus->state = MDIOBUS_REGISTERED;
-	pr_info("%s: probed\n", bus->name);
+	pr_info("%s: %d phys probed\n", bus->name, phynum);
 	return 0;
 
 error:
-- 
1.7.0.4




From marc.zyngier at arm.com  Tue Mar 13 06:58:33 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 13 Mar 2012 10:58:33 +0000
Subject: Conflict between Versatile Express DT conversion and local timer
 updates
In-Reply-To: <20120313101525.GA569@n2100.arm.linux.org.uk>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <20120312235951.GA31601@n2100.arm.linux.org.uk>
 <CAOesGMjt26JgySpcqVT+PsSgGq9cxQWn+msG4DSwo=2ykGz91A@mail.gmail.com>
 <4F5F15ED.2010602@arm.com> <20120313101525.GA569@n2100.arm.linux.org.uk>
Message-ID: <4F5F2859.5020407@arm.com>

On 13/03/12 10:15, Russell King - ARM Linux wrote:
> On Tue, Mar 13, 2012 at 09:39:57AM +0000, Marc Zyngier wrote:
>> On 13/03/12 01:23, Olof Johansson wrote:
>>> Hi,
>>>
>>> On Mon, Mar 12, 2012 at 4:59 PM, Russell King - ARM Linux
>>> <linux at arm.linux.org.uk> wrote:
>>>> On Mon, Mar 12, 2012 at 11:10:16PM +0000, Russell King - ARM Linux wrote:
>>>>> Marc, Pawel,
>>>>>
>>>>> Your changes are conflicting badly.  Seriously badly.  So badly that I'm
>>>>> not bothering to fix the conflicts because I can't work out what the fix
>>>>> should be.
>>>>>
>>>>> You both work for the same frigging organization and yet you seem to
>>>>> work completely independently (I really don't care if you work in
>>>>> different departments - the fact of the matter is you're touching the
>>>>> same code in completely different ways with zero coordination between
>>>>> yourselves.  That's simply broken workflow.)
>>>>>
>>>>> For example, Marc's deleting arch/arm/plat-versatile/localtimer.c, but
>>>>> Pawel is modifying it to add DT support for Versatile Express.  The
>>>>> correct solution?  Hell knows.  And I don't want a solution to the merge
>>>>> conflict.  I want the merge conflict to go away (because I'm not frigging
>>>>> around applying the same git-rerere immune fixes to a tree I'm regenerating
>>>>> each night for the kernel autobuilder.)
>>>>>
>>>>> I'm getting conflicts in arch/arm/mach-vexpress/ct-ca9x4.c and
>>>>> arch/arm/mach-ux500/timer.c as well, which I'm not going to bother trying
>>>>> to sort out - the obvious solution for ux500/timer.c doesn't look right.
>>>>>
>>>>> I've a mind to drop the localtimer changes on the floor until after this
>>>>> merge window, but unfortunately they're part of devel-stable so I can't.
>>>>
>>>> Correction: I haven't been pushing out my devel-stable branch for
>>>> apparantly two months (according to gitweb, and no one noticed?), so I
>>>> _could_ drop the merge of Marc's tree until the conflicts can be sanely
>>>> resolved.
>>>
>>> I haven't noticed because I stopped tracking your tree directly when
>>> you were having server load issues; I tend to have kept an eye on
>>> linux-next-level breakage instead, but probably not as close as I
>>> should have.
>>>
>>> Dropping Marc's branch and having him either resubmit on top of
>>> arm-soc like the io cleanup was done, or pull it in as an early
>>> dependency for 3.5 and stage it in an for-armsoc branch sounds like
>>> two good options to me, with no real preference in either direction.
>>
>> I'm happy to rebase my patches on anything that will make the merge
>> easier (IOW conflict-less).
>>
>> Russell, would you prefer this series to go via armsoc? This seems the
>> cleanest solution for the time being.
> 
> With a lot of these core ARM changes, there's a very fine line between
> whether they are core ARM changes or whether they're platform level
> changes (many core ARM changes will impact lots of platforms.)  I'm just
> wondering if there's any point to taking these changes through my tree.
> It seems utterly pointless if they're going to keep conflicting with
> platform stuff.

Fair enough.

Olof, Arnd: which is the most base for you to take this series?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...



From s.hauer at pengutronix.de  Tue Mar 13 07:24:47 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 13 Mar 2012 12:24:47 +0100
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <1330763341-3437-4-git-send-email-mturquette@linaro.org>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
Message-ID: <20120313112447.GA29317@pengutronix.de>

On Sat, Mar 03, 2012 at 12:29:00AM -0800, Mike Turquette wrote:
> The common clock framework defines a common struct clk useful across
> most platforms as well as an implementation of the clk api that drivers
> can use safely for managing clocks.
> 
> The net result is consolidation of many different struct clk definitions
> and platform-specific clock framework implementations.
> 
> This patch introduces the common struct clk, struct clk_ops and an
> implementation of the well-known clock api in include/clk/clk.h.
> Platforms may define their own hardware-specific clock structure and
> their own clock operation callbacks, so long as it wraps an instance of
> struct clk_hw.
> 
> See Documentation/clk.txt for more details.
> 
> This patch is based on the work of Jeremy Kerr, which in turn was based
> on the work of Ben Herrenschmidt.
> 
> Signed-off-by: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Mike Turquette <mturquette at ti.com>
> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Shawn Guo <shawn.guo at freescale.com>
> Cc: Richard Zhao <richard.zhao at linaro.org>
> Cc: Saravana Kannan <skannan at codeaurora.org>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Stephen Boyd <sboyd at codeaurora.org>
> Cc: Amit Kucheria <amit.kucheria at linaro.org>
> Cc: Deepak Saxena <dsaxena at linaro.org>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Andrew Lunn <andrew at lunn.ch>
> ---
>  drivers/clk/Kconfig          |   28 +
>  drivers/clk/Makefile         |    1 +
>  drivers/clk/clk.c            | 1323 ++++++++++++++++++++++++++++++++++++++++++
>  include/linux/clk-private.h  |   68 +++
>  include/linux/clk-provider.h |  169 ++++++
>  include/linux/clk.h          |   68 ++-
>  6 files changed, 1652 insertions(+), 5 deletions(-)
>  create mode 100644 drivers/clk/clk.c
>  create mode 100644 include/linux/clk-private.h
>  create mode 100644 include/linux/clk-provider.h
> 
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 3912576..18eb8c2 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -11,3 +11,31 @@ config HAVE_MACH_CLKDEV
>  
>  config HAVE_CLK_PREPARE
>  	bool
> +
> +menuconfig COMMON_CLK
> +	bool "Common Clock Framework"
> +	select HAVE_CLK_PREPARE
> +	---help---
> +	  The common clock framework is a single definition of struct
> +	  clk, useful across many platforms, as well as an
> +	  implementation of the clock API in include/linux/clk.h.
> +	  Architectures utilizing the common struct clk should select
> +	  this automatically, but it may be necessary to manually select
> +	  this option for loadable modules requiring the common clock
> +	  framework.
> +
> +	  If in doubt, say "N".
> +
> +if COMMON_CLK
> +
> +config COMMON_CLK_DEBUG
> +	bool "DebugFS representation of clock tree"
> +	depends on COMMON_CLK
> +	---help---
> +	  Creates a directory hierchy in debugfs for visualizing the clk
> +	  tree structure.  Each directory contains read-only members
> +	  that export information specific to that clk node: clk_rate,
> +	  clk_flags, clk_prepare_count, clk_enable_count &
> +	  clk_notifier_count.
> +
> +endif
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 07613fa..ff362c4 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -1,2 +1,3 @@
>  
>  obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
> +obj-$(CONFIG_COMMON_CLK)	+= clk.o
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> new file mode 100644
> index 0000000..b979d74
> --- /dev/null
> +++ b/drivers/clk/clk.c
> @@ -0,0 +1,1323 @@
> +/*
> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
> + * Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Standard functionality for the common clock API.  See Documentation/clk.txt
> + */
> +
> +#include <linux/clk-private.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/spinlock.h>
> +#include <linux/err.h>
> +#include <linux/list.h>
> +#include <linux/slab.h>
> +
> +static DEFINE_SPINLOCK(enable_lock);
> +static DEFINE_MUTEX(prepare_lock);
> +
> +static HLIST_HEAD(clk_root_list);
> +static HLIST_HEAD(clk_orphan_list);
> +static LIST_HEAD(clk_notifier_list);
> +
> +/***        debugfs support        ***/
> +
> +#ifdef CONFIG_COMMON_CLK_DEBUG
> +#include <linux/debugfs.h>
> +
> +static struct dentry *rootdir;
> +static struct dentry *orphandir;
> +static int inited = 0;
> +
> +/* caller must hold prepare_lock */
> +static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
> +{
> +	struct dentry *d;
> +	int ret = -ENOMEM;
> +
> +	if (!clk || !pdentry) {
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	d = debugfs_create_dir(clk->name, pdentry);
> +	if (!d)
> +		goto out;
> +
> +	clk->dentry = d;
> +
> +	d = debugfs_create_u32("clk_rate", S_IRUGO, clk->dentry,
> +			(u32 *)&clk->rate);
> +	if (!d)
> +		goto err_out;
> +
> +	d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
> +			(u32 *)&clk->flags);
> +	if (!d)
> +		goto err_out;
> +
> +	d = debugfs_create_u32("clk_prepare_count", S_IRUGO, clk->dentry,
> +			(u32 *)&clk->prepare_count);
> +	if (!d)
> +		goto err_out;
> +
> +	d = debugfs_create_u32("clk_enable_count", S_IRUGO, clk->dentry,
> +			(u32 *)&clk->enable_count);
> +	if (!d)
> +		goto err_out;
> +
> +	d = debugfs_create_u32("clk_notifier_count", S_IRUGO, clk->dentry,
> +			(u32 *)&clk->notifier_count);
> +	if (!d)
> +		goto err_out;
> +
> +	ret = 0;
> +	goto out;
> +
> +err_out:
> +	debugfs_remove(clk->dentry);
> +out:
> +	return ret;
> +}
> +
> +/* caller must hold prepare_lock */
> +static int clk_debug_create_subtree(struct clk *clk, struct dentry *pdentry)
> +{
> +	struct clk *child;
> +	struct hlist_node *tmp;
> +	int ret = -EINVAL;;
> +
> +	if (!clk || !pdentry)
> +		goto out;
> +
> +	ret = clk_debug_create_one(clk, pdentry);
> +
> +	if (ret)
> +		goto out;
> +
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node)
> +		clk_debug_create_subtree(child, clk->dentry);
> +
> +	ret = 0;
> +out:
> +	return ret;
> +}
> +
> +/**
> + * clk_debug_register - add a clk node to the debugfs clk tree
> + * @clk: the clk being added to the debugfs clk tree
> + *
> + * Dynamically adds a clk to the debugfs clk tree if debugfs has been
> + * initialized.  Otherwise it bails out early since the debugfs clk tree
> + * will be created lazily by clk_debug_init as part of a late_initcall.
> + *
> + * Caller must hold prepare_lock.  Only clk_init calls this function (so
> + * far) so this is taken care.
> + */
> +static int clk_debug_register(struct clk *clk)
> +{
> +	struct clk *parent;
> +	struct dentry *pdentry;
> +	int ret = 0;
> +
> +	if (!inited)
> +		goto out;
> +
> +	parent = clk->parent;
> +
> +	/*
> +	 * Check to see if a clk is a root clk.  Also check that it is
> +	 * safe to add this clk to debugfs
> +	 */
> +	if (!parent)
> +		if (clk->flags & CLK_IS_ROOT)
> +			pdentry = rootdir;
> +		else
> +			pdentry = orphandir;
> +	else
> +		if (parent->dentry)
> +			pdentry = parent->dentry;
> +		else
> +			goto out;
> +
> +	ret = clk_debug_create_subtree(clk, pdentry);
> +
> +out:
> +	return ret;
> +}
> +
> +/**
> + * clk_debug_init - lazily create the debugfs clk tree visualization
> + *
> + * clks are often initialized very early during boot before memory can
> + * be dynamically allocated and well before debugfs is setup.
> + * clk_debug_init walks the clk tree hierarchy while holding
> + * prepare_lock and creates the topology as part of a late_initcall,
> + * thus insuring that clks initialized very early will still be
> + * represented in the debugfs clk tree.  This function should only be
> + * called once at boot-time, and all other clks added dynamically will
> + * be done so with clk_debug_register.
> + */
> +static int __init clk_debug_init(void)
> +{
> +	struct clk *clk;
> +	struct hlist_node *tmp;
> +
> +	rootdir = debugfs_create_dir("clk", NULL);
> +
> +	if (!rootdir)
> +		return -ENOMEM;
> +
> +	orphandir = debugfs_create_dir("orphans", rootdir);
> +
> +	if (!orphandir)
> +		return -ENOMEM;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
> +		clk_debug_create_subtree(clk, rootdir);
> +
> +	hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
> +		clk_debug_create_subtree(clk, orphandir);
> +
> +	inited = 1;
> +
> +	mutex_unlock(&prepare_lock);
> +
> +	return 0;
> +}
> +late_initcall(clk_debug_init);
> +#else
> +static inline int clk_debug_register(struct clk *clk) { return 0; }
> +#endif /* CONFIG_COMMON_CLK_DEBUG */
> +
> +/***    helper functions   ***/
> +
> +inline const char *__clk_get_name(struct clk *clk)
> +{
> +	return !clk ? NULL : clk->name;
> +}
> +
> +inline struct clk_hw *__clk_get_hw(struct clk *clk)
> +{
> +	return !clk ? NULL : clk->hw;
> +}
> +
> +inline u8 __clk_get_num_parents(struct clk *clk)
> +{
> +	return !clk ? -EINVAL : clk->num_parents;
> +}
> +
> +inline struct clk *__clk_get_parent(struct clk *clk)
> +{
> +	return !clk ? NULL : clk->parent;
> +}
> +
> +inline unsigned long __clk_get_rate(struct clk *clk)
> +{
> +	return !clk ? -EINVAL : clk->rate;
> +}
> +
> +inline unsigned long __clk_get_flags(struct clk *clk)
> +{
> +	return !clk ? -EINVAL : clk->flags;
> +}
> +
> +static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
> +{
> +	struct clk *child;
> +	struct clk *ret;
> +	struct hlist_node *tmp;
> +
> +	if (!strcmp(clk->name, name))
> +		return clk;
> +
> +	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
> +		ret = __clk_lookup_subtree(name, child);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	return NULL;
> +}
> +
> +struct clk *__clk_lookup(const char *name)
> +{
> +	struct clk *root_clk;
> +	struct clk *ret;
> +	struct hlist_node *tmp;
> +

This should have a check for NULL pointers. NULL pointers can happen
here if a mux has holes in it. In this case the parent name array would
look like this:

{ "parentclk1", "parentclk2", NULL /* reserved */, "parentclk3" }

Without checking for NULL pointers we dereference the NULL pointer here.

> +
> +/**
> + * __clk_round_rate - round the given rate for a clk
> + * @clk: round the rate of this clock
> + *
> + * Caller must hold prepare_lock.  Useful for clk_ops such as .set_rate
> + */
> +unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	if (!clk && !clk->ops->round_rate)
> +		return -EINVAL;

This should return the parents rate if the clock itself does not
have a round_rate function. Also, must be || instead of &&

> +
> +	return clk->ops->round_rate(clk->hw, rate, NULL);
> +}
> +
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From T.Mehnert at eckelmann.de  Tue Mar 13 07:35:22 2012
From: T.Mehnert at eckelmann.de (Mehnert, Torsten)
Date: Tue, 13 Mar 2012 11:35:22 +0000
Subject: [PATCH] iomux-mx25.h slew rate adjusted for LCD __LD pins
Message-ID: <3F263ABB4EDE344D974E1983B56807739E868EAB@EX-DAG01.eckelmann.group>

From: Mehnert <tmehnert at eckelmann.de>
Date: Mon, 13 Mar 2012 12:13:51 +0100
Subject: [PATCH] iomux-mx25.h slew rate adjusted for LCD __LD pins

For some reason (sadly i don't identifying the patch right now)
two LCD data lines configured PAD_CTL_SRE_SLOW (wrong slew rate)
since Kernel 3.1. MX25_PAD_GPIO_E__LD16 and MX25_PAD_GPIO_F__LD17
This results in an fauly behaviour and strange color effects.

To ensure that all LCD data pins configured with the proper slew rate,
this patch changes to IOMUX define of all LCD __LDxx pins to PAD_CTL_SRE_FAST.

This problem may affect other mx25 platforms like mx25pdk. Sadly i can't test
it. Of course this problem shouldn't occur when you done your LCD muxing 
correctly in the bootloader.

Best regards,
Torsten

---
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h	2012-02-28 00:43:05.000000000 +0100
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h	2012-03-13 12:08:39.920736789 +0100
@@ -139,15 +139,15 @@
 #define MX25_PAD_NFRB__GPIO_3_31	IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D15__D15		IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D15__LD16		IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D15__LD16		IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D15__GPIO_4_5		IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D14__D14		IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D14__LD17		IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D14__LD17		IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D14__GPIO_4_6		IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D13__D13		IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D13__LD18		IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D13__LD18		IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D13__GPIO_4_7		IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D12__D12		IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
@@ -192,54 +192,54 @@
 #define MX25_PAD_D0__D0			IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_D0__GPIO_4_20		IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD0__LD0		IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD0__LD0		IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD0__CSI_D0		IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD0__GPIO_2_15		IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD1__LD1		IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD1__LD1		IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD1__CSI_D1		IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD1__GPIO_2_16		IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD2__LD2		IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD2__LD2		IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD2__GPIO_2_17		IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD3__LD3		IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD3__LD3		IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD3__GPIO_2_18		IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD4__LD4		IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD4__LD4		IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD4__GPIO_2_19		IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD5__LD5		IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD5__LD5		IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD5__GPIO_1_19		IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD6__LD6		IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD6__LD6		IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD6__GPIO_1_20		IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD7__LD7		IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD7__LD7		IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD7__GPIO_1_21		IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD8__LD8		IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD8__LD8		IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD8__FEC_TX_ERR	IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD9__LD9		IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD9__LD9		IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD9__FEC_COL		IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD10__LD10		IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD10__LD10		IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD10__FEC_RX_ER	IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD11__LD11		IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD11__LD11		IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD11__FEC_RDATA2	IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD12__LD12		IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD12__LD12		IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD12__FEC_RDATA3	IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD13__LD13		IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD13__LD13		IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD13__FEC_TDATA2	IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD14__LD14		IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD14__LD14		IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD14__FEC_TDATA3	IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD15__LD15		IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD15__LD15		IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD15__FEC_RX_CLK	IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
 
 #define MX25_PAD_HSYNC__HSYNC		IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
@@ -468,11 +468,11 @@
 #define MX25_PAD_GPIO_C__CAN2_TX	IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
 
 #define MX25_PAD_GPIO_D__GPIO_D		IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_E__LD16		IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_E__LD16		IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_GPIO_D__CAN2_RX	IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
 
 #define MX25_PAD_GPIO_E__GPIO_E		IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__LD17		IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_F__LD17		IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_GPIO_E__AUD7_TXD	IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_GPIO_F__GPIO_F		IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
---
Torsten Mehnert
K?lte- und Geb?udeleittechnik (KGL)
?
ECKELMANN AG
Berliner Stra?e 161
D - 65205 Wiesbaden
?
Phone:	+49 (0) 611 / 7103 - 370
Fax:	+49 (0) 611 / 7103 - 133

e-Mail:	mailto:t.mehnert at eckelmann.de
Web:	http://www.eckelmann.de



From tom.leiming at gmail.com  Tue Mar 13 07:37:16 2012
From: tom.leiming at gmail.com (Ming Lei)
Date: Tue, 13 Mar 2012 19:37:16 +0800
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <87mx9ej8fp.fsf@ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <87mx9ej8fp.fsf@ti.com>
Message-ID: <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>

Hi,

On Tue, Jan 24, 2012 at 7:38 AM, Kevin Hilman <khilman at ti.com> wrote:
> Vaibhav Hiremath <hvaibhav at ti.com> writes:
>
>> OMAP device has 32k-sync timer which is currently used as a
>> clocksource in the kernel (omap2plus_defconfig).
>> The current implementation uses compile time selection between
>> gp-timer and 32k-sync timer, which breaks multi-omap build for
>> the devices like AM33xx, where 32k-sync timer is not available.
>>
>> So use hwmod database lookup mechanism, through which at run-time
>> we can identify availability of 32k-sync timer on the device,
>> else fall back to gp-timer.
>
> With the runtime detection & fallback, I suggest also removing the
> Kconfig choice between the two as well.

IMO, under some situations, gp timer clocksource has high precision
and is very useful, so hope the Kconfig choice can be kept, or using
kernel parameter way,  and the patch need to be changed to support the
selection.


thanks,
-- 
Ming Lei


From nicolas.ferre at atmel.com  Tue Mar 13 07:45:56 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 13 Mar 2012 12:45:56 +0100
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <20120306223321.GD15201@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
Message-ID: <4F5F3374.8000506@atmel.com>

On 03/06/2012 11:33 PM, Russell King - ARM Linux :
> [v2 - more or less same description.  Including lakml in cc for the full
> set]
> 
> This patch series cleans up the handling of cookies in DMA engine drivers.
> This is done by providing a set of inline library functions for common
> tasks:
> 
> - moving the 'last completed cookie' into struct dma_chan - everyone
>   has this in their driver private channel data structure
> 
> - consolidate allocation of cookies to DMA descriptors
> 
> - common way to update 'last completed cookie' value
> 
> - standard way to implement tx_status callback and update the residue
> 
> - consolidate initialization of cookies
> 
> - update implementations differing from the majority of DMA engine drivers
>   to behave the same as the majority implementation in respect of cookies
> 
> What this means is that we get to the point where all DMA engine drivers
> will hand out cookie value '2' as the first, and incrementing cookie
> values up to INT_MAX, returning to cookie '1' as the next cookie.
> 
> Think of this patch series as round 1...  I am hoping over time that more
> code can be consolidated between the DMA engine drivers and end up with a
> consistent way to handle various common themes in DMA engine hardware
> (like physical channel<->peripheral request signal selection.)
> 
> Overall, the diffstat looks like this:
> 
>  arch/arm/include/asm/hardware/iop_adma.h |    2 -
>  drivers/dma/amba-pl08x.c                 |   38 ++++---------
>  drivers/dma/at_hdmac.c                   |   48 ++++------------
>  drivers/dma/at_hdmac_regs.h              |    2 -

For at_hdmac Atmel DMA driver:

Tested-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Thanks a lot Russell.

Best regards,
-- 
Nicolas Ferre


From joancarles at fqingenieria.es  Tue Mar 13 07:59:12 2012
From: joancarles at fqingenieria.es (joancarles)
Date: Tue, 13 Mar 2012 12:59:12 +0100
Subject: [PATCH] iomux-mx25.h slew rate adjusted for LCD __LD pins
In-Reply-To: <3F263ABB4EDE344D974E1983B56807739E868EAB@EX-DAG01.eckelmann.group>
References: <3F263ABB4EDE344D974E1983B56807739E868EAB@EX-DAG01.eckelmann.group>
Message-ID: <efb4350f3d236ae7feb088b9a5072b8c@mail.fqingenieria.es>

Hi

What a coincidence, we have been fighting with the LCD color issue on 
an i.MX258 about two weeks ago and came up with almost the same patch.

> For some reason (sadly i don't identifying the patch right now)
> two LCD data lines configured PAD_CTL_SRE_SLOW (wrong slew rate)
> since Kernel 3.1. MX25_PAD_GPIO_E__LD16 and MX25_PAD_GPIO_F__LD17
> This results in an fauly behaviour and strange color effects.
>
> To ensure that all LCD data pins configured with the proper slew 
> rate,
> this patch changes to IOMUX define of all LCD __LDxx pins to
> PAD_CTL_SRE_FAST.

For us it was enough to change the MX25_PAD_GPIO_E__LD16 and 
MX25_PAD_GPIO_F__LD17 pins to PAD_CTL_SRE_FAST. Why do you need to 
change the others too? Could this introduce undesired signal noise on 
the board? We actually experience a weird effect on the ADC lines. It's 
all been discussed here:



> This problem may affect other mx25 platforms like mx25pdk. Sadly i 
> can't test
> it. Of course this problem shouldn't occur when you done your LCD 
> muxing
> correctly in the bootloader.

Would you care to explain how to perform the "LCD muxing correctly" in 
the bootloader and why it should influence what the kernel does?

I will test your patch (adding PAD_CTL_SRE_FAST to all __LDxx pins 
instead of just LD16 and LD17) and report back. In any case, I can 
confirm that without this patch the LCD has weird colors. Juergen 
Beisert has more iomux-mx25.h changes, especially with regard to PWM, so 
I reckon he'll send them upstream soon enough.

> @@ -468,11 +468,11 @@
>  #define MX25_PAD_GPIO_C__CAN2_TX	IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0,
> PAD_CTL_PUS_22K_UP)
>
>  #define MX25_PAD_GPIO_D__GPIO_D		IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0,
> NO_PAD_CTRL)
> -#define MX25_PAD_GPIO_E__LD16		IOMUX_PAD(0x400, 0x204, 0x02, 0, 0,
> NO_PAD_CTRL)
> +#define MX25_PAD_GPIO_E__LD16		IOMUX_PAD(0x400, 0x204, 0x02, 0, 0,
> PAD_CTL_SRE_FAST)
>  #define MX25_PAD_GPIO_D__CAN2_RX	IOMUX_PAD(0x3fc, 0x200, 0x16,
> 0x484, 1, PAD_CTL_PUS_22K_UP)
>
>  #define MX25_PAD_GPIO_E__GPIO_E		IOMUX_PAD(0x400, 0x204, 0x10, 0, 0,
> NO_PAD_CTRL)
> -#define MX25_PAD_GPIO_F__LD17		IOMUX_PAD(0x404, 0x208, 0x02, 0, 0,
> NO_PAD_CTRL)
> +#define MX25_PAD_GPIO_F__LD17		IOMUX_PAD(0x404, 0x208, 0x02, 0, 0,
> PAD_CTL_SRE_FAST)
>  #define MX25_PAD_GPIO_E__AUD7_TXD	IOMUX_PAD(0x400, 0x204, 0x14, 0,
> 0, NO_PAD_CTRL)
>
>  #define MX25_PAD_GPIO_F__GPIO_F		IOMUX_PAD(0x404, 0x208, 0x10, 0, 0,
> NO_PAD_CTRL)

As mentioned above, this is the only part we needed from the patch to 
address the wrong slew rate for the LCD color wash-out. But I am curious 
as to hear your explanation with regard to changing the slew rate of the 
other __LDxx pins.

Best regards
-- 
Joan C. Abelaira



From s.hauer at pengutronix.de  Tue Mar 13 08:05:08 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 13 Mar 2012 13:05:08 +0100
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zPx0ARsoO4ueSTMe_z2Gs4xG4P2qn1=-vHFf7_k=+K6hQ@mail.gmail.com>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
 <20120311113414.GM3852@pengutronix.de>
 <CAJOA=zMdkLB-DCPOk=kz5mn6BK6A_swocyCHJHeGE6H7FxBbmQ@mail.gmail.com>
 <20120312115117.GN3852@pengutronix.de>
 <CAJOA=zPx0ARsoO4ueSTMe_z2Gs4xG4P2qn1=-vHFf7_k=+K6hQ@mail.gmail.com>
Message-ID: <20120313120507.GS3852@pengutronix.de>

Hi Mike,

On Mon, Mar 12, 2012 at 08:16:36PM -0700, Turquette, Mike wrote:
> On Mon, Mar 12, 2012 at 4:51 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > On Sun, Mar 11, 2012 at 02:24:46PM -0700, Turquette, Mike wrote:
> >> On Sun, Mar 11, 2012 at 4:34 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> >> > Hi Mike,
> >> >
> >> > I was about to give my tested-by when I decided to test the set_rate
> >> > function. Unfortunately this is broken for several reasons. I'll try
> >> > to come up with a fixup series later the day.
> >>
> >> I haven't tested clk_set_rate since V4, but I also haven't changed the
> >> code appreciably. ?I'll retest on my end also.
> >>
> >> > On Fri, Mar 09, 2012 at 11:54:23PM -0800, Mike Turquette wrote:
> >> >> + ? ? /* find the new rate and see if parent rate should change too */
> >> >> + ? ? WARN_ON(!clk->ops->round_rate);
> >> >> +
> >> >> + ? ? new_rate = clk->ops->round_rate(clk->hw, rate, &parent_new_rate);
> >> >
> >> > You don't need a WARN_ON when you derefence clk->ops->round_rate anyway.
> >>
> >> Agreed that the WARN_ON should not be there.
> >>
> >> The v6 Documentation/clk.txt states that .round_rate is mandatory for
> >> clocks that can adjust their rate, but I need to clarify this a bit
> >> more. ?Ideally we want to be able to call clk_set_rate on any clock
> >> and get a changed rate (if possible) by either adjusting that clocks
> >> rate direction (e.g. a PLL or an adjustable divider) or by propagating
> >> __clk_set_rate up the parents (assuming of course that
> >> CLK_SET_RATE_PARENT flag is set appropriately).
> >>
> >> > Also, even when the current clock does not have a set_rate function it
> >> > can still change its rate when the CLK_SET_RATE_PARENT is set.
> >>
> >> Correct. ?I'll clean this up and make the documentation a bit more
> >> verbose on when .set_rate/.round_rate/.recalc_rate are mandatory.
> >>
> >> >
> >> >> +
> >> >> + ? ? /* NOTE: pre-rate change notifications will stack */
> >> >> + ? ? if (clk->notifier_count)
> >> >> + ? ? ? ? ? ? ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
> >> >> +
> >> >> + ? ? if (ret == NOTIFY_BAD)
> >> >> + ? ? ? ? ? ? return clk;
> >> >> +
> >> >> + ? ? /* speculate rate changes down the tree */
> >> >> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node) {
> >> >> + ? ? ? ? ? ? ret = __clk_speculate_rates(child, new_rate);
> >> >> + ? ? ? ? ? ? if (ret == NOTIFY_BAD)
> >> >> + ? ? ? ? ? ? ? ? ? ? return clk;
> >> >> + ? ? }
> >> >> +
> >> >> + ? ? /* change the rate of this clk */
> >> >> + ? ? if (clk->ops->set_rate)
> >> >> + ? ? ? ? ? ? ret = clk->ops->set_rate(clk->hw, new_rate);
> >> >
> >> > I don't know the reason why you change the child clock before the parent
> >> > clock, but it cannot work since this clock will change its rate based on
> >> > the old parent rate and not the new one.
> >>
> >> This depends on the .round_rate implementation, which I admit to
> >> having lost some sleep over. ?A clever .round_rate will request the
> >> "intermediate" rate for a clock when propagating a request to change
> >> the parent rate later on. ?Take for instance the following:
> >>
> >> pll @ 200MHz (locked)
> >> ? ? |
> >> parent @ 100MHz (can divide by 1 or 2; currently divider is 2)
> >> ? ? |
> >> child @ 25MHz (can divide by 2 or 4; currently divider is 4)
> >>
> >> If we want child to run at 100MHz then the desirable configuration
> >> would be to have parent divide-by-1 and child divide-by-2. ?When we
> >> call,
> >>
> >> clk_set_rate(child, 100MHz);
> >>
> >> Its .round_rate should return 50MHz, and &parent_new_rate should be
> >> 200MHz. ?So 50MHz is an "intermediate" rate, but it gets us the
> >> divider we want. ?And in fact 50MHz reflects reality because that will
> >> be the rate of child until the parent propagation completes and we can
> >> adjust parent's dividers. ?(this is one reason why I prefer for
> >> pre-rate change notifiers to stack on top of each other).
> >>
> >> So now that &parent_new_rate is > 0, __clk_set_rate will propagate the
> >> request up and parent's .round_rate will simply return 200MHz and
> >> leave it's own &parent_new_rate at 0. ?This will change from
> >> divide-by-2 to divide-by-1 and from this highest point in the tree we
> >> will propagate post-rate change notifiers downstream, as part of the
> >> recalc_rate tree walk.
> >>
> >> I have tested this with OMAP4's CPUfreq driver and I think, while
> >> complicated, it is a sound way to approach the problem. ?Maybe the API
> >> can be cleaned up, if you have any suggestions.
> >
> > I cannot see all implications this way will have. All this rate
> > propagation is more complex than I thought it would be.
> 
> Hi Sascha,
> 
> Yes it is very complicated.  The solution I have now (recursive
> __clk_set_rate, clever .round_rate which requests parent rate) was not
> something I arrived at immediately.
> 
> I decided to validate the v6 patches more thoroughly today, based on
> your claim that clk_set_rate is broken and here is what I found:
> 
> 1) clk_set_rate works.  I pulled in the latest OMAP4 CPUfreq code into
> my common clk branch and it Just Worked.  This is a dumb
> implementation involving no upwards parent propagation, and the clock
> changing is of type struct clk_hw_omap (relocking a PLL)
> 
> 2) while I was at it I verified the rate change notifiers +
> clk_set_parent, which also work (I had not touched these since v4 and
> wanted to make sure nothing was broken)
> 
> Here is where things get interesting.  I tried the same parent rate
> propagation via CPUfreq that I had done previously in the v4 series
> (http://article.gmane.org/gmane.linux.ports.arm.omap/68225), but this
> time it didn't work.  The difference is that back in v4 all of my
> clocks in that propagation chain were struct clk_hw_omap, none of them
> were any of the basic clock types.  Now in v6, one of the clocks in
> the chain is struct clk_divider.  I started looking at the divider's
> .round_rate code and for the case where CLK_PARENT_SET_RATE flag is
> set the code doesn't make any sense.  I spent some time today trying
> to fix struct clk_divider's .round_rate implementation and came to
> realize that there might not be a sane default for how such code
> should work.  A sane default for the common divider that works
> correctly on OMAP may not be what you want on iMX.
> 
> To illustrate: if CLK_SET_RATE_PARENT flag is set for my clk_divider
> I'd really like to divide by 1 and pass the exact same rate that was
> requested for my clk_divider up to the parent.

I don't understand this. If you use the CLK_SET_RATE_PARENT to force
a divider value to 1 then why do you register a divider at all?

> But the existing
> divider code tries to find the largest div for clk_divider and request
> a faster rate from the parent (well, I assume this is what it is
> supposed to do as the code doesn't quite get this right).

That's indeed different assumptions. When I set CLK_SET_RATE_PARENT I
want to say to the divider that it is allowed to change the parent rate.
So what it does (or should do) is to loop around its divider values and
tries to round the parent rate to (rate * div). This way it can find the
best divider values for this divider and the parent divider to get the
wanted rate. This was done (almost) correctly in the version of the
divider I posted to the list, but indeed the current version is broken.

> 
> Do you have any ideas on this?  Also, can you verify if this is what
> was failing for you, or maybe provide a log if the bug you mentioned
> exists elsewhere?  An extreme solution to the problem would be for
> clk_divider to not support the CLK_SET_PARENT flag if we cannot agree
> on a sane default for this behavior.  I like the idea of the divider
> choosing the smallest div possible and requesting the balance from the
> parent, but I need feedback from others on that point.

As said, the divider tries to get the *best* value for itself and the
parent divider (if exists), not the smallest.
I think the current divider implements something between what I thought
it should should do and what you thought it should do.

> For non-rate
> adjustable clocks (clk_gate in particular) it is very easy to continue
> supporting this flag as the .round_rate implementation should just be
> a "pass through" up to the parent.  In fact this behavior is what some
> of my omap clocks are doing and that is why parent propagation for
> CPUfreq was working for me back in v4.
> 
> > I tried another
> > approach on the weekend which basically does not try to do all in a
> > single recursion but instead sets the rate in multiple steps:
> >
> > 1) call a function which calculates all new rates of affected clocks
> > ? in a rate change and safes the value in a clk->new_rate field. This
> > ? function returns the topmost clock which has to be changed.
> > 2) starting from the topmost clock notify all clients. This walks the
> > ? whole subtree even if a notfifier refuses the change. If necessary
> > ? we can walk the whole subtree again to abort the change.
> > 3) actually change rates starting from the topmost clocks and notify
> > ? all clients on the way. I changed the set_rate callback to void.
> > ? Instead of failing (what is failing in case of set_rate? The clock
> > ? will still have some rate) I check for the result with
> > ? clk_ops->recalc_rate.
> 
> I've considered something like this for "clock groups", especially
> when the set of clocks changing are all on the same device and the
> permutations are well known ahead of time.  Is this working for you
> now?

The way described above works for me now, see this branch:

git://git.pengutronix.de/git/imx/linux-2.6.git v3.3-rc6-clkv6-fixup

You may not necessarily like it as it changes quite a lot in the rate
changing code.

For the clock groups I plan to drop them at least for i.MX as the concept
of clk groups seems somewhat broken. What we are grouping together are
really different clocks and the driver should know about it and could
even make use of it. We may not want to have more clocks in the driver
though and may need something handling this on the bus layer, but that's
another topic. The clock framework seems to be the wrong place for it.

> 
> >
> > In the end what's more important than the implementation details is that
> > it actually works. I created a little test module which sets up two
> > cascaded dividers, tries to change the rate at the output and checks the
> > result. ?We might want to add something like this (and maybe similar
> > tests for reparenting and other stuff) to the generic clock framework
> > later. ?It's good to have something generic to test the framework with
> > without depending on some particular SoC.
> 
> Agreed about the generic test.  I'm not taking it into the current
> series, but we can grow the test cases and submit them later on.

Have you tried running it? It's not i.MX specific. I attached an updated
version of the test. It fails with several NULL pointer exceptions,
mostly because it has the CLK_SET_RATE_PARENT flag set for a divider
whose parent is a fixed clock. If I don't set this flag no more NULL
pointer exceptions occur, but the rate is not correct because the
divider has to use DIV_ROUND_UP in its calc_best_div function. Otherwise
it always returns a higher frequency if parentrate/rate is not an
integer.

Apart from these little details we are discussing about here I really
like your patches and can't wait to see them mainline. Thanks for
working on this.

Sascha

8<---------------------------------------------------------------

clk: Add clock test module

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/Makefile   |    2 +-
 drivers/clk/clk-test.c |  218 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 219 insertions(+), 1 deletions(-)
 create mode 100644 drivers/clk/clk-test.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1f736bc..ba9a779 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,4 +1,4 @@
 
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
-				   clk-mux.o clk-divider.o
+				   clk-mux.o clk-divider.o clk-test.o
diff --git a/drivers/clk/clk-test.c b/drivers/clk/clk-test.c
new file mode 100644
index 0000000..cdee544
--- /dev/null
+++ b/drivers/clk/clk-test.c
@@ -0,0 +1,218 @@
+#include <linux/spinlock.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+
+/*
+ * We build a fixed rate source clock with two cascaded 2bit dividers:
+ *
+ * f1 -> div1 -> div2
+ *
+ * and try set the rate of div2 from 0Hz to f1 + 1 Hz.
+ *
+ * Note that we expect the core to divide the dividers one after
+ * another:
+ *
+ * fout = (f1 / div1) / div
+ *
+ * and not like this:
+ *
+ * fout = f1 / (div1 * div2)
+ * This has in some cases different results due to integer maths
+ */
+
+static unsigned long div1_reg, div2_reg;
+static int div1_width = 3;
+static int div2_width = 3;
+
+#define MAX_DIV(x)	(1 << (x))
+
+static struct clk *f1, *div1, *div2;
+
+static DEFINE_SPINLOCK(clk_test_lock);
+
+#define FIXED_RATE 1000
+
+static int check_rounded_rate_div2(unsigned long want, unsigned long rounded)
+{
+	int i, j;
+	unsigned long best = 0, now;
+
+	if (want > FIXED_RATE) {
+		best = FIXED_RATE;
+		goto found;
+	}
+
+	for (i = 1; i <= MAX_DIV(div1_width); i++) {
+		for (j = 1; j <= MAX_DIV(div2_width); j++) {
+			now = FIXED_RATE / i / j;
+			if (now <= want && now > best)
+				best = now;
+		}
+	}
+
+	if (!best)
+		best = (FIXED_RATE / MAX_DIV(div1_width)) / MAX_DIV(div2_width);
+found:
+	if (rounded != best) {
+		printk("clk-test: wanted rate %ld, best result would be %ld,"
+				" but we have %ld\n",
+				want, best, rounded);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int check_real_rate_div2(unsigned long rate)
+{
+	unsigned long realrate;
+
+	realrate = FIXED_RATE / (div1_reg + 1) / (div2_reg + 1);
+
+	if (rate != realrate) {
+		printk("clk-test: divider returns rate %ld, but instead has %ld\n",
+				rate, realrate);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int set_rate_test_div2(void)
+{
+	unsigned long i, rate, rounded;
+	int ret, errors = 0;
+
+	for (i = 0; i < FIXED_RATE + 1; i++) {
+		rounded = clk_round_rate(div2, i);
+		ret = check_rounded_rate_div2(i, rounded);
+		if (ret)
+			errors++;
+		ret = clk_set_rate(div2, i);
+		if (ret) {
+			printk("%s: setting rate of div2 to %ld failed with %d\n",
+					__func__, i, ret);
+			errors++;
+		}
+
+		rate = clk_get_rate(div2);
+
+		if (rounded != rate) {
+			printk("clk_test: wanted %ld, core rounded to %ld, have now: %ld\n",
+					i, rounded, rate);
+			errors++;
+		}
+
+		ret = check_real_rate_div2(rate);
+		if (ret)
+			errors++;
+	}
+
+	return errors;
+}
+
+static int check_rounded_rate_div1(unsigned long want, unsigned long rounded)
+{
+	unsigned long best;
+	int i;
+
+	for (i = 1; i <= MAX_DIV(div1_width); i++)
+		if (FIXED_RATE / i <= want) {
+			best = FIXED_RATE / i;
+			goto found;
+		}
+
+	best = FIXED_RATE / MAX_DIV(div1_width);
+found:
+	if (rounded != best) {
+		printk("clk-test: wanted rate %ld, best result would be %ld,"
+				" but we have %ld\n",
+				want, best, rounded);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int check_real_rate_div1(unsigned long rate)
+{
+	unsigned long realrate;
+
+	realrate = FIXED_RATE / (div1_reg + 1);
+
+	if (rate != realrate) {
+		printk("clk-test: divider returns rate %ld, but instead has %ld\n",
+				rate, realrate);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int set_rate_test_div1(void)
+{
+	unsigned long i, rate, rounded;
+	int ret, errors = 0;
+
+	for (i = 0; i < FIXED_RATE + 1; i++) {
+		rounded = clk_round_rate(div1, i);
+		ret = check_rounded_rate_div1(i, rounded);
+		if (ret)
+			errors++;
+		ret = clk_set_rate(div1, i);
+		if (ret) {
+			printk("%s: setting rate of div2 to %ld failed with %d\n",
+					__func__, i, ret);
+			errors++;
+		}
+
+		rate = clk_get_rate(div1);
+
+		if (rounded != rate) {
+			printk("clk_test: wanted %ld, core rounded to %ld, have now: %ld\n",
+					i, rounded, rate);
+			errors++;
+		}
+
+		ret = check_real_rate_div1(rate);
+		if (ret)
+			errors++;
+	}
+
+	return errors;
+}
+
+/* The core does not like this flag when the parent is not adjustable */
+#define DIV1_FLAGS CLK_SET_RATE_PARENT
+
+static int clk_test_init(void)
+{
+	int errors = 0;
+
+	f1 = clk_register_fixed_rate(NULL, "f1", NULL, CLK_IS_ROOT, FIXED_RATE);
+	div1 = clk_register_divider(NULL, "div1", "f1", DIV1_FLAGS,
+			&div1_reg, 0, div1_width, 0, &clk_test_lock);
+	div2 = clk_register_divider(NULL, "div2", "div1", CLK_SET_RATE_PARENT,
+			&div2_reg, 0, div2_width, 0, &clk_test_lock);
+
+	if (!f1 || !div1 || !div2) {
+		printk("clk-test: failed to register clocks\n");
+		return -EINVAL;
+	}
+
+	/* First pass: no cascaded divider, only f1 -> div1 */
+	errors = set_rate_test_div1();
+	/* Second pass: cascaded divider, f1 -> div1 -> div2 */
+	errors += set_rate_test_div2();
+
+	printk("clk-test: finished with %d errors\n", errors);
+#if 0
+	/* we should be able to unregister clocks */
+	clk_unregister(f1);
+	clk_unregister(div1);
+	clk_unregister(div2);
+#endif
+	return -EINVAL;
+}
+subsys_initcall(clk_test_init);
-- 
1.7.9.1

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Tue Mar 13 07:55:16 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 11:55:16 +0000
Subject: Conflict between Versatile Express DT conversion and local timer
 updates
In-Reply-To: <4F5F2859.5020407@arm.com>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <20120313101525.GA569@n2100.arm.linux.org.uk> <4F5F2859.5020407@arm.com>
Message-ID: <201203131155.16454.arnd@arndb.de>

On Tuesday 13 March 2012, Marc Zyngier wrote:
> On 13/03/12 10:15, Russell King - ARM Linux wrote:
> > On Tue, Mar 13, 2012 at 09:39:57AM +0000, Marc Zyngier wrote:
> >> On 13/03/12 01:23, Olof Johansson wrote:
> >>> Hi,
> >>>
> >>> On Mon, Mar 12, 2012 at 4:59 PM, Russell King - ARM Linux
> >>> <linux at arm.linux.org.uk> wrote:
> >>>>
> >>>> Correction: I haven't been pushing out my devel-stable branch for
> >>>> apparantly two months (according to gitweb, and no one noticed?), so I
> >>>> could drop the merge of Marc's tree until the conflicts can be sanely
> >>>> resolved.
> >>>
> >>> I haven't noticed because I stopped tracking your tree directly when
> >>> you were having server load issues; I tend to have kept an eye on
> >>> linux-next-level breakage instead, but probably not as close as I
> >>> should have.
> >>>
> >>> Dropping Marc's branch and having him either resubmit on top of
> >>> arm-soc like the io cleanup was done, or pull it in as an early
> >>> dependency for 3.5 and stage it in an for-armsoc branch sounds like
> >>> two good options to me, with no real preference in either direction.
> >>
> >> I'm happy to rebase my patches on anything that will make the merge
> >> easier (IOW conflict-less).
> >>
> >> Russell, would you prefer this series to go via armsoc? This seems the
> >> cleanest solution for the time being.
> > 
> > With a lot of these core ARM changes, there's a very fine line between
> > whether they are core ARM changes or whether they're platform level
> > changes (many core ARM changes will impact lots of platforms.)  I'm just
> > wondering if there's any point to taking these changes through my tree.
> > It seems utterly pointless if they're going to keep conflicting with
> > platform stuff.
> 
> Fair enough.
> 
> Olof, Arnd: which is the most base for you to take this series?

I'm not sure I understand your question. The conflicts that Russell
mentioned are with the ux500/timer (in next/soc) and with the
vexpress/dt (in next/dt) branches. There are multiple ways out of
here:

a) take your series first, but merge it into the next/dt and next/soc
   branches, resolving the conflicts in the process. This would be
   fairly easy to do if you can provide the merge resolution as
   a git pull and let Russell still take your series as is.

b) rebase your series on top of vexpress/dt, merge it into the next/soc
   branch.

c) rebase your series on top of ux500/timer, merge it into the next/dt
   branch.

d) create a new next/timer branch in arm-soc that has Pawel's     
   98ed4ceb "ARM: vexpress: Get rid of MMIO_P2V" (the first patch from
   vexpress/dt, your patches and the ux500/timer series. Also put
   98ed4ceb into the next/cleanup branch.

Any of those will work for us, my preference would be on #4. I have
created the next/timer branch in the arm-soc tree, so you can use
that and either rebase your patches on top or merge your tree into
it and fix up the merge conflicts.

	Arnd


From arnd at arndb.de  Tue Mar 13 08:09:51 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 12:09:51 +0000
Subject: [PATCH v4 02/11] ep93xx: Don't use system controller defines in
 audio drivers
In-Reply-To: <1331592502-9083-3-git-send-email-rmallon@gmail.com>
References: <1331592502-9083-3-git-send-email-rmallon@gmail.com>
Message-ID: <201203131209.52031.arnd@arndb.de>

On Monday 12 March 2012, Ryan Mallon wrote:
> This patch has already been applied in Mark's tree. It is posted
> for inclusion here because this series is against v3.3-rc7 and
> will cause build failures without it. There have been no changes
> to the patch since Mark applied it, so it should be okay to
> merge into both his tree and the arm-soc tree.

Ok, that should work. However, in the future when you anticipate
having to do something like this, I would suggest you do any patches
that you want to see applied to multiple branches as git-pull
requests, because that allows us to use the same changeset ids.

When we apply one patch separately to two branches, we end up
with multiple changesets in the git history, which is something
we normally try to avoid.

	Arnd


From arnd at arndb.de  Tue Mar 13 08:11:19 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 12:11:19 +0000
Subject: [PATCH v4 05/11] ep93xx: Convert the watchdog driver into a
 platform device.
In-Reply-To: <1331592502-9083-6-git-send-email-rmallon@gmail.com>
References: <1331592502-9083-6-git-send-email-rmallon@gmail.com>
Message-ID: <201203131211.19422.arnd@arndb.de>

On Monday 12 March 2012, Ryan Mallon wrote:
> From: H Hartley Sweeten <hsweeten at visionengravers.com>
> 
> From: H Hartley Sweeten <hsweeten at visionengravers.com>
> 
> Convert the ep93xx watchdog driver into a platform device and
> remove it's dependency on <mach/hardware.h>.
> 
> Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
> Signed-off-by: Ryan Mallon <rmallon at gmail.com>
> Signed-off-by: Wim Van Sebroeck <wim at iguana.be>
> Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
> Cc: Arnd Bergmann <arnd at arndb.de>

Acked-by: Arnd Bergmann <arnd at arndb.de>

Note that you have an extra From: line in the beginning.

	Arnd


From arnd at arndb.de  Tue Mar 13 08:11:46 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 12:11:46 +0000
Subject: [PATCH v4 06/11] ep93xx: Move peripheral defines to local SoC
 header
In-Reply-To: <1331592502-9083-7-git-send-email-rmallon@gmail.com>
References: <1331592502-9083-7-git-send-email-rmallon@gmail.com>
Message-ID: <201203131211.46289.arnd@arndb.de>

On Monday 12 March 2012, Ryan Mallon wrote:
> Move the AHB/APB peripheral defines to local SoC header since they are
> only needed by the core SoC code. The UART defines are not moved
> because they are used by the mach/uncompress.h header.
> 
> Signed-off-by: Ryan Mallon <rmallon at gmail.com>
> Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
> Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From linus.walleij at stericsson.com  Tue Mar 13 08:27:23 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 13 Mar 2012 13:27:23 +0100
Subject: [PATCH v3] serial: PL011: clear pending interrupts
Message-ID: <1331641643-25929-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

Chanho Min reported that when the boot loader transfers
control to the kernel, there may be pending interrupts
causing the UART to lock up in an eternal loop trying to
pick tokens from the FIFO (since the RX interrupt flag
indicates there are tokens) while in practice there are
no tokens - in fact there is only a pending IRQ flag.

This patch address the issue with a combination of two
patches suggested by Russell King that clears and mask
all interrupts at probe() and clears any pending error
and RX interrupts at port startup time.

We suspect the spurious interrupts are a side-effect of
switching the UART from FIFO to non-FIFO mode.

Cc: stable at kernel.org
Cc: Shreshtha Kumar Sahu <shreshthakumar.sahu at stericsson.com>
Cc: Jong-Sung Kim <neidhard.kim at lge.com>
Reported-by: Chanho Min <chanho0207 at gmail.com>
Suggested-by: Russell King <linux at arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Instead of making the IRQ fastpath account for spurious
  IRQs with zero characters, make sure to clear out any
  pending IRQ flags in startup().
ChangeLog v2->v3:
- Attempt to clear out any spuriously appearing RX interrups
  in startup() instead of in the interrupt handler. Let's
  see if this works.
---
 drivers/tty/serial/amba-pl011.c |   15 +++++++++++----
 1 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 6800f5f..7e01399 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1381,6 +1381,10 @@ static int pl011_startup(struct uart_port *port)
 
 	uap->port.uartclk = clk_get_rate(uap->clk);
 
+	/* Clear pending error and receive interrupts */
+	writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
+	       UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
+
 	/*
 	 * Allocate the IRQ
 	 */
@@ -1417,10 +1421,6 @@ static int pl011_startup(struct uart_port *port)
 	cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
 	writew(cr, uap->port.membase + UART011_CR);
 
-	/* Clear pending error interrupts */
-	writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
-	       uap->port.membase + UART011_ICR);
-
 	/*
 	 * initialise the old status of the modem signals
 	 */
@@ -1435,6 +1435,9 @@ static int pl011_startup(struct uart_port *port)
 	 * as well.
 	 */
 	spin_lock_irq(&uap->port.lock);
+	/* Clear out any spuriously appearing RX interrupts */
+	 writew(UART011_RTIS | UART011_RXIS,
+		uap->port.membase + UART011_ICR);
 	uap->im = UART011_RTIM;
 	if (!pl011_dma_rx_running(uap))
 		uap->im |= UART011_RXIM;
@@ -1927,6 +1930,10 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 		goto unmap;
 	}
 
+	/* Ensure interrupts from this UART are masked and cleared */
+	writew(0, uap->port.membase + UART011_IMSC);
+	writew(0xffff, uap->port.membase + UART011_ICR);
+
 	uap->vendor = vendor;
 	uap->lcrh_rx = vendor->lcrh_rx;
 	uap->lcrh_tx = vendor->lcrh_tx;
-- 
1.7.8



From linux at arm.linux.org.uk  Tue Mar 13 08:31:21 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 13 Mar 2012 12:31:21 +0000
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <1331628036.1727.22.camel@vkoul-udesk3>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <1331128466.24656.421.camel@vkoul-udesk3>
 <20120312161143.GA10830@n2100.arm.linux.org.uk>
 <1331569438.1727.3.camel@vkoul-udesk3>
 <1331628036.1727.22.camel@vkoul-udesk3>
Message-ID: <20120313123121.GA20133@n2100.arm.linux.org.uk>

On Tue, Mar 13, 2012 at 02:10:36PM +0530, Vinod Koul wrote:
> Please see if the below patch is the right fix for build failures in
> addition to one suggested by Jassi.

I'm not sure that Jassi's solution is correct - and I'm wondering whether
any of the DMA engine drivers do the right thing when transfers are
terminated.  Is it right for the DMA status function to return IN_PROGRESS
for a previously submitted cookie which has been terminated?

I can see two answers to that, both equally valid:

1. It allows you to find out exactly where the DMA engine got to before
   the transfer was terminated, and therefore recover from the termination
   if you wish to.

2. Returning in-progress when a cookie will never be completed is
   misleading, and could be misinterpreted by users of the tx_status
   function, especially if they are waiting for a particular transaction
   to complete.

Maybe we need to introduce a DMA_TERMINATED status?

> -------------------x-------------------------x----------------------
> 
> >From 949ff5b8d46b5e3435d21b2651ce3a2599208d44 Mon Sep 17 00:00:00 2001
> From: Vinod Koul <vinod.koul at linux.intel.com>
> Date: Tue, 13 Mar 2012 11:58:12 +0530
> Subject: [PATCH] dmaengine: fix for cookie changes and merge
> 
> Fixed trivial issues in drivers:
> 	drivers/dma/imx-sdma.c
> 	drivers/dma/intel_mid_dma.c
> 	drivers/dma/ioat/dma_v3.c
> 	drivers/dma/iop-adma.c
> 	drivers/dma/sirf-dma.c
> 	drivers/dma/timb_dma.c
> 
> Signed-off-by: Vinod Koul <vinod.koul at linux.intel.com>
> ---
>  drivers/dma/imx-sdma.c      |    1 +
>  drivers/dma/intel_mid_dma.c |    1 +
>  drivers/dma/ioat/dma_v3.c   |    1 +
>  drivers/dma/iop-adma.c      |    1 +
>  drivers/dma/sirf-dma.c      |    2 ++
>  drivers/dma/timb_dma.c      |    6 +-----
>  6 files changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index ccfc7c4..81f9d57 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -1127,6 +1127,7 @@ static void sdma_issue_pending(struct dma_chan *chan)
>  	struct sdma_engine *sdma = sdmac->sdma;
>  
>  	if (sdmac->status == DMA_IN_PROGRESS)
> +		sdma_enable_channel(sdma, sdmac->channel);
>  }
>  
>  #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1	34

This looks like a merge conflict resolution.  I don't see this being
caused by my patches as I haven't touched this function.

> diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
> index d599d96..2449812 100644
> --- a/drivers/dma/intel_mid_dma.c
> +++ b/drivers/dma/intel_mid_dma.c
> @@ -477,6 +477,7 @@ static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
>  						dma_cookie_t cookie,
>  						struct dma_tx_state *txstate)
>  {
> +	struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
>  	enum dma_status ret;
>  
>  	ret = dma_cookie_status(chan, cookie, txstate);

Ditto (my patches don't introduce new this new midc, nor do they remove
that line.)

> diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
> index 145eda2..2c4476c 100644
> --- a/drivers/dma/ioat/dma_v3.c
> +++ b/drivers/dma/ioat/dma_v3.c
> @@ -61,6 +61,7 @@
>  #include <linux/dmaengine.h>
>  #include <linux/dma-mapping.h>
>  #include <linux/prefetch.h>
> +#include "../dmaengine.h"
>  #include "registers.h"
>  #include "hw.h"
>  #include "dma.h"
> diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
> index 1f3a703..4499f88 100644
> --- a/drivers/dma/iop-adma.c
> +++ b/drivers/dma/iop-adma.c
> @@ -894,6 +894,7 @@ static enum dma_status iop_adma_status(struct dma_chan *chan,
>  					struct dma_tx_state *txstate)
>  {
>  	struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
> +	int ret;

This was "enum dma_status ret;" before I accidentally removed it.  It
probably should be again, rather than an int.

>  
>  	ret = dma_cookie_status(chan, cookie, txstate);
>  	if (ret == DMA_SUCCESS)
> diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
> index a2cde85..45ba352 100644
> --- a/drivers/dma/sirf-dma.c
> +++ b/drivers/dma/sirf-dma.c
> @@ -18,6 +18,8 @@
>  #include <linux/of_platform.h>
>  #include <linux/sirfsoc_dma.h>
>  
> +#include "dmaengine.h"
> +
>  #define SIRFSOC_DMA_DESCRIPTORS                 16
>  #define SIRFSOC_DMA_CHANNELS                    16
>  

Hmm, guess that's what happens when old patches are brought forward and
things from the original series are forgotten...

> diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
> index 7805996..d408c22 100644
> --- a/drivers/dma/timb_dma.c
> +++ b/drivers/dma/timb_dma.c
> @@ -510,17 +510,13 @@ static void td_free_chan_resources(struct dma_chan *chan)
>  static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
>  				    struct dma_tx_state *txstate)
>  {
> -	struct timb_dma_chan *td_chan =
> -		container_of(chan, struct timb_dma_chan, chan);
>  	enum dma_status ret;
>  
>  	dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
>  
>  	ret = dma_cookie_status(chan, cookie, txstate);
>  
> -	dev_dbg(chan2dev(chan),
> -		"%s: exit, ret: %d, last_complete: %d, last_used: %d\n",
> -		__func__, ret, last_complete, last_used);
> +	dev_dbg(chan2dev(chan), "%s: exit, ret: %d\n", 	__func__, ret);
>  
>  	return ret;
>  }
> -- 
> 1.7.0.4
> 
> 
> 
> 
> -- 
> ~Vinod
> 


From artem.bityutskiy at intel.com  Tue Mar 13 08:33:22 2012
From: artem.bityutskiy at intel.com (Bityutskiy, Artem)
Date: Tue, 13 Mar 2012 12:33:22 +0000
Subject: [PATCH] mtd/gpmi : fix the wrong DMA command.
In-Reply-To: <1331518938-24047-1-git-send-email-b32955@freescale.com>
References: <1331518938-24047-1-git-send-email-b32955@freescale.com>
Message-ID: <1331642159.3595.28.camel@sauron.fi.intel.com>

On Mon, 2012-03-12 at 10:22 +0800, Huang Shijie wrote:
> The last DMA command of ECC read page is used to disable the BCH module.
> But the original code missed to set the pio[2] which is used to set the
> GPMI_HW_GPMI_ECCCTRL register. fix it now.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
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From arnd at arndb.de  Tue Mar 13 08:35:53 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 12:35:53 +0000
Subject: [PATCH v4 00/11] ep93xx: Move SoC private bits to core
In-Reply-To: <1331592502-9083-1-git-send-email-rmallon@gmail.com>
References: <1331592502-9083-1-git-send-email-rmallon@gmail.com>
Message-ID: <201203131235.53593.arnd@arndb.de>

On Monday 12 March 2012, Ryan Mallon wrote:
> This patch series is an effort to move the ep93xx SoC specific code out
> of drivers and include/mach into arch/arm/mach-ep93xx. This work
> involves the following changes:
> 
>  - Create a new private header called soc.h to replace most of 
>    mach/include/ep93xx-regs.h
>  - Move the Maverick crunch code from arch/arm/kernel to mach-ep93xx
>  - Convert the ep93xx backlight and watchdog drivers to properly
>    ioremap memory.
>  - Move all system controller access to the ep93xx core code
> 
> The only defines left in ep93xx-regs.h are for the APB UARTS which
> are also needed in include/mach/uncompress.h and
> include/mach/debug-macro.S.
> 
> Patch 2 has already been merged to the ASoC tree and patch 5 has
> already been merged to the watchdog tree. Neither patch has been
> modified since they were applied, and are included here for
> completeness and to avoid build errors. 

Looks all very nice, great work!

> All of the patches are against v3.3-rc7 and  now have reviewed-by
> and/or acked-by tags except for patch 4 which has been changed
> since the last version. Arnd, once I get an ack for the final patch
> I can prepare a git branch for you to pull. I understand if this is
> now too late for v3.4.

If there are no conflicts against the for-next branch and Olof agrees,
I would probably let this one go in for v3.4. It's a nice cleanup
and it will be easier to do your v3.5 patches if it's all merged.

On a related note, I would like to understand better what your plans
are for the future of ep93xx. My undestanding is that the product line
is a dead end and there won't be any other compatible socs, but the
Linux support is very much alive and supports all the existing hardware,
is that correct?

There are currently eight board files (since all the dev boards got
merged into one file), which seems very manageable and there should be
no problem adding a few more over the years to come, if necessary.

At the same time, the platform seems simple enough that you could
also do a device tree port in rather in a fairly short time if you
like, which would let you obsolete all the board files and add new
machines just through device tree blobs.

	Arnd


From plagnioj at jcrosoft.com  Tue Mar 13 08:33:41 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 13:33:41 +0100
Subject: [PATCH 2/5 v4] ARM: at91: sam9g20 add i2c DT support
In-Reply-To: <a>
References: <a>
Message-ID: <1331642024-19869-2-git-send-email-plagnioj@jcrosoft.com>

For now on use i2c-gpio driver on the same pin as the hardware IP.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: devicetree-discuss at lists.ozlabs.org
---
 arch/arm/boot/dts/at91sam9g20.dtsi |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 4b0dc99..a885a30 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -189,4 +189,17 @@
 			status = "disabled";
 		};
 	};
+
+	i2c at 0 {
+		compatible = "i2c-gpio";
+		gpios = <&pioA 23 0 /* sda */
+			 &pioA 24 0 /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
-- 
1.7.7



From plagnioj at jcrosoft.com  Tue Mar 13 08:33:42 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 13:33:42 +0100
Subject: [PATCH 3/5 v4] ARM: at91: usb_a9g20 add DT i2c support
In-Reply-To: <a>
References: <a>
Message-ID: <1331642024-19869-3-git-send-email-plagnioj@jcrosoft.com>

Use i2c-gpio and enable rv3029 RTC.

Enable the rtc in the sam9g20 defconfig.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: devicetree-discuss at lists.ozlabs.org
---
 arch/arm/boot/dts/usb_a9g20.dts        |    9 +++++++++
 arch/arm/configs/at91sam9g20_defconfig |    3 +++
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 71d83ef..0ea90b5 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -97,4 +97,13 @@
 			gpio-key,wakeup;
 		};
 	};
+
+	i2c at 0 {
+		status = "okay";
+
+		rv3029c2 at 56 {
+			compatible = "rv3029c2";
+			reg = <0x56>;
+		};
+	};
 };
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index 9123568..994d331 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -74,6 +74,8 @@ CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_SPI_SPIDEV=y
@@ -105,6 +107,7 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_EXT2_FS=y
 CONFIG_MSDOS_FS=y
-- 
1.7.7



From plagnioj at jcrosoft.com  Tue Mar 13 08:33:43 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 13:33:43 +0100
Subject: [PATCH 4/5 v4] ARM: at91: sam9g45 add i2c DT support
In-Reply-To: <a>
References: <a>
Message-ID: <1331642024-19869-4-git-send-email-plagnioj@jcrosoft.com>

For now on use i2c-gpio driver on the same pin as the hardware IP.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: devicetree-discuss at lists.ozlabs.org
---
 arch/arm/boot/dts/at91sam9g45.dtsi |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index d79021b..92fe5a5 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -197,4 +197,17 @@
 			status = "disabled";
 		};
 	};
+
+	i2c at 0 {
+		compatible = "i2c-gpio";
+		gpios = <&pioA 20 0 /* sda */
+			 &pioA 21 0 /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <5>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
-- 
1.7.7



From plagnioj at jcrosoft.com  Tue Mar 13 08:33:44 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 13:33:44 +0100
Subject: [PATCH 5/5 v4] ARM: at91: sam9x5 add i2c DT support
In-Reply-To: <a>
References: <a>
Message-ID: <1331642024-19869-5-git-send-email-plagnioj@jcrosoft.com>

For now on use i2c-gpio driver on the same pin as the hardware IP.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: devicetree-discuss at lists.ozlabs.org
---
 arch/arm/boot/dts/at91sam9x5.dtsi |   39 +++++++++++++++++++++++++++++++++++++
 1 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index c294657..f0104f4 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -188,4 +188,43 @@
 			status = "disabled";
 		};
 	};
+
+	i2c at 0 {
+		compatible = "i2c-gpio";
+		gpios = <&pioA 30 0 /* sda */
+			 &pioA 31 0 /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c at 1 {
+		compatible = "i2c-gpio";
+		gpios = <&pioC 0 0 /* sda */
+			 &pioC 1 0 /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c at 2 {
+		compatible = "i2c-gpio";
+		gpios = <&pioB 4 0 /* sda */
+			 &pioB 5 0 /* scl */
+			>;
+		i2c-gpio,sda-open-drain;
+		i2c-gpio,scl-open-drain;
+		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
 };
-- 
1.7.7



From plagnioj at jcrosoft.com  Tue Mar 13 08:33:40 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 13:33:40 +0100
Subject: [PATCH 1/5 v4] i2c/gpio: add DT support
In-Reply-To: <a>
References: <a>
Message-ID: <1331642024-19869-1-git-send-email-plagnioj@jcrosoft.com>

update to use devm_kzalloc for private data

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: linux-i2c at vger.kernel.org
Cc: devicetree-discuss at lists.ozlabs.org
---
v4:

	fix timeout
	use gpio_is_valid
 .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 +++++++
 drivers/i2c/busses/i2c-gpio.c                      |   94 +++++++++++++++----
 2 files changed, 106 insertions(+), 20 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
new file mode 100644
index 0000000..4f8ec94
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
@@ -0,0 +1,32 @@
+Device-Tree bindings for i2c gpio driver
+
+Required properties:
+	- compatible = "i2c-gpio";
+	- gpios: sda and scl gpio
+
+
+Optional properties:
+	- i2c-gpio,sda-open-drain: sda as open drain
+	- i2c-gpio,scl-open-drain: scl as open drain
+	- i2c-gpio,scl-output-only: scl as output only
+	- i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform)
+	- i2c-gpio,timeout-ms: timeout to get data
+
+Example nodes:
+
+i2c at 0 {
+	compatible = "i2c-gpio";
+	gpios = <&pioA 23 0 /* sda */
+		 &pioA 24 0 /* scl */
+		>;
+	i2c-gpio,sda-open-drain;
+	i2c-gpio,scl-open-drain;
+	i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	rv3029c2 at 56 {
+		compatible = "rv3029c2";
+		reg = <0x56>;
+	};
+};
diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
index a651779..c0330a4 100644
--- a/drivers/i2c/busses/i2c-gpio.c
+++ b/drivers/i2c/busses/i2c-gpio.c
@@ -14,8 +14,15 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/of_i2c.h>
 
-#include <asm/gpio.h>
+struct i2c_gpio_private_data {
+	struct i2c_adapter adap;
+	struct i2c_algo_bit_data bit_data;
+	struct i2c_gpio_platform_data pdata;
+};
 
 /* Toggle SDA by changing the direction of the pin */
 static void i2c_gpio_setsda_dir(void *data, int state)
@@ -78,24 +85,62 @@ static int i2c_gpio_getscl(void *data)
 	return gpio_get_value(pdata->scl_pin);
 }
 
+static int __devinit of_i2c_gpio_probe(struct device_node *np,
+			     struct i2c_gpio_platform_data *pdata)
+{
+	u32 reg;
+
+	if (of_gpio_count(np) < 2)
+		return -ENODEV;
+
+	pdata->sda_pin = of_get_gpio(np, 0);
+	pdata->scl_pin = of_get_gpio(np, 1);
+
+	if (!gpio_is_valid(pdata->sda_pin) || !gpio_is_valid(pdata->scl_pin)) {
+		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
+		       np->full_name, pdata->sda_pin, pdata->scl_pin);
+		return -ENODEV;
+	}
+
+	of_property_read_u32(np, "i2c-gpio,delay-us", &pdata->udelay);
+
+	if (!of_property_read_u32(np, "i2c-gpio,timeout-ms", &reg))
+		pdata->timeout = msecs_to_jiffies(reg);
+
+	pdata->sda_is_open_drain =
+		of_property_read_bool(np, "i2c-gpio,sda-open-drain");
+	pdata->scl_is_open_drain =
+		of_property_read_bool(np, "i2c-gpio,scl-open-drain");
+	pdata->scl_is_output_only =
+		of_property_read_bool(np, "i2c-gpio,scl-output-only");
+
+	return 0;
+}
+
 static int __devinit i2c_gpio_probe(struct platform_device *pdev)
 {
+	struct i2c_gpio_private_data *priv;
 	struct i2c_gpio_platform_data *pdata;
 	struct i2c_algo_bit_data *bit_data;
 	struct i2c_adapter *adap;
 	int ret;
 
-	pdata = pdev->dev.platform_data;
-	if (!pdata)
-		return -ENXIO;
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	adap = &priv->adap;
+	bit_data = &priv->bit_data;
+	pdata = &priv->pdata;
 
-	ret = -ENOMEM;
-	adap = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
-	if (!adap)
-		goto err_alloc_adap;
-	bit_data = kzalloc(sizeof(struct i2c_algo_bit_data), GFP_KERNEL);
-	if (!bit_data)
-		goto err_alloc_bit_data;
+	if (pdev->dev.of_node) {
+		ret = of_i2c_gpio_probe(pdev->dev.of_node, pdata);
+		if (ret)
+			return ret;
+	} else {
+		if (!pdev->dev.platform_data)
+			return -ENXIO;
+		memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
+	}
 
 	ret = gpio_request(pdata->sda_pin, "sda");
 	if (ret)
@@ -143,6 +188,7 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
 	adap->algo_data = bit_data;
 	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 	adap->dev.parent = &pdev->dev;
+	adap->dev.of_node = pdev->dev.of_node;
 
 	/*
 	 * If "dev->id" is negative we consider it as zero.
@@ -154,7 +200,9 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_add_bus;
 
-	platform_set_drvdata(pdev, adap);
+	of_i2c_register_devices(adap);
+
+	platform_set_drvdata(pdev, priv);
 
 	dev_info(&pdev->dev, "using pins %u (SDA) and %u (SCL%s)\n",
 		 pdata->sda_pin, pdata->scl_pin,
@@ -168,34 +216,40 @@ err_add_bus:
 err_request_scl:
 	gpio_free(pdata->sda_pin);
 err_request_sda:
-	kfree(bit_data);
-err_alloc_bit_data:
-	kfree(adap);
-err_alloc_adap:
 	return ret;
 }
 
 static int __devexit i2c_gpio_remove(struct platform_device *pdev)
 {
+	struct i2c_gpio_private_data *priv;
 	struct i2c_gpio_platform_data *pdata;
 	struct i2c_adapter *adap;
 
-	adap = platform_get_drvdata(pdev);
-	pdata = pdev->dev.platform_data;
+	priv = platform_get_drvdata(pdev);
+	adap = &priv->adap;
+	pdata = &priv->pdata;
 
 	i2c_del_adapter(adap);
 	gpio_free(pdata->scl_pin);
 	gpio_free(pdata->sda_pin);
-	kfree(adap->algo_data);
-	kfree(adap);
 
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id i2c_gpio_dt_ids[] = {
+	{ .compatible = "i2c-gpio", },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, i2c_gpio_dt_ids);
+#endif
+
 static struct platform_driver i2c_gpio_driver = {
 	.driver		= {
 		.name	= "i2c-gpio",
 		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(i2c_gpio_dt_ids),
 	},
 	.probe		= i2c_gpio_probe,
 	.remove		= __devexit_p(i2c_gpio_remove),
-- 
1.7.7



From kumarrav at codeaurora.org  Tue Mar 13 08:46:39 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Tue, 13 Mar 2012 18:16:39 +0530
Subject: [PATCH v3 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 DMA APIs
In-Reply-To: <20120312201421.GA3459@fifo99.com>
References: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>
 <20120312201421.GA3459@fifo99.com>
Message-ID: <4F5F41AF.1090907@codeaurora.org>

On 3/13/2012 1:44 AM, Daniel Walker wrote:
> On Mon, Mar 12, 2012 at 04:02:44PM +0530, Ravi Kumar V wrote:
>> Add DMAEngine based driver using the old MSM DMA APIs internally.
>
> What do you mean by this?
>
There is a MSM DMA driver in arch/arm/mach-msm/ which is not in
dmaengine framework standards, but that driver is been used by client 
drivers nand, eMMC and serial drivers. Now if we implement the whole dma 
driver using dmaengine framework then nand, eMMC like drivers will be 
failed as they are using old dma driver API's, so instead of 
implementing new driver from scratch we are keeping the old dma API's as 
it is and using those API's in new dmaengine framework.So that we can 
convert clients drivers to use dma engine framework.

>> The benefit of this approach is that not all the drivers
>> have to get converted to DMAEngine APIs simultaneosly while
>> both the drivers can stay enabled in the kernel. The client
>> drivers using the old MSM APIs directly can now convert to
>> DMAEngine one by one.
>
> Which drivers?

client drivers which are using dma.
>
> Daniel
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From arnd at arndb.de  Tue Mar 13 09:09:21 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 13:09:21 +0000
Subject: [PATCH v8 0/4] USB: OHCI-HCD: Support for LPC32xx
In-Reply-To: <1331589292-18986-1-git-send-email-stigge@antcom.de>
References: <1331589292-18986-1-git-send-email-stigge@antcom.de>
Message-ID: <201203131309.21529.arnd@arndb.de>

On Monday 12 March 2012, Roland Stigge wrote:
> These patches add support for the LPC32xx to the ohci-pnx4008 driver and make
> the driver use smbus functions.
> 
> As discussed with Greg-KH on the USB mailing list, the ohci-pnx4008 driver is
> first renamed to reflect its multi-platform support. The second patch also
> renames the respective pnx4008_* symbols accordingly.
> 
> The third patch adds the actual lpc32xx support.
> 
> The fourth patch removes the re-coded i2c_write() by using an existing smbus
> function. You can leave out this very single patch to still have the desired
> LPC32xx support. It just fixes existing kernel code to only use smbus calls in
> this driver.
> 
> Applies to v3.3-rc7
> 
> Changes since v7:
> 
> * Removed pnx4008 filename reference
> * Rename via git format-patch -M
> 
> Thanks to Arnd Bergmann and Wolfram Sang for reviewing!
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From lost.distance at yahoo.com  Tue Mar 13 09:11:30 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Tue, 13 Mar 2012 13:11:30 +0000 (GMT)
Subject: [PATCH] pxa/hx4700: Remove unwanted request for GPIO105
Message-ID: <1331644290.41945.YahooMailClassic@web29009.mail.ird.yahoo.com>

GPIO105 (nIR_ON) is requested twice: first in gpio_request_array(), then in
pxa_irda_probe(). Consequently the second request fails with EBUSY:

pxa2xx-ir: probe of pxa2xx-ir failed with error -16

This patch removes the first request, allowing pxa_irda_probe() to succeed.

Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
---

--- clean-3.3-rc7/arch/arm/mach-pxa/hx4700.c	2012-03-10 21:49:52.000000000 +0000
+++ linux-3.3-rc7/arch/arm/mach-pxa/hx4700.c	2012-03-13 12:55:41.258719320 +0000
@@ -830,7 +830,6 @@ static struct gpio global_gpios[] = {
 	{ GPIO32_HX4700_RS232_ON,         GPIOF_OUT_INIT_HIGH, "RS232_ON" },
 	{ GPIO71_HX4700_ASIC3_nRESET,     GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
 	{ GPIO82_HX4700_EUART_RESET,      GPIOF_OUT_INIT_HIGH, "EUART_RESET" },
-	{ GPIO105_HX4700_nIR_ON,          GPIOF_OUT_INIT_HIGH, "nIR_EN" },
 };
 
 static void __init hx4700_init(void)



From jason at lakedaemon.net  Tue Mar 13 09:12:27 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 13 Mar 2012 09:12:27 -0400
Subject: [PATCH 4/7 v4] ARM: kirkwood: add dreamplug (fdt) support.
In-Reply-To: <201203131010.43095.arnd@arndb.de>
References: <cover.1331601448.git.jason@lakedaemon.net>
 <0032addd7e94c5d4d1a3a0be77fe79bcffee53db.1331601448.git.jason@lakedaemon.net>
 <201203131010.43095.arnd@arndb.de>
Message-ID: <20120313131227.GG5050@titan.lakedaemon.net>

On Tue, Mar 13, 2012 at 10:10:42AM +0000, Arnd Bergmann wrote:
> On Tuesday 13 March 2012, Jason Cooper wrote:
> > Initially, copied guruplug-setup.c and did s/guruplug/dreamplug/g.
> > Then, switched to SPI based NOR flash.
> > 
> > After talking to Arnd Bergman, chose an incremental approach to adding
> > devicetree support.  First, we use the dtb to tell us we are on the
> > dreamplug, then we gradually port over drivers.
> > 
> > Driver porting will start with the uart (see next patch), and progress
> > from there.  Next, all drivers not needing common clock (kirkwood_tclk)
> > or pinmux.  Then, remain drivers as that support hits the tree.
> > 
> > We need to absorb kirkwood_init() into kirkwood_dt_init() so that as we
> > convert drivers, we can remove the platform call, eg
> > kirkwood_rtc_init().  This maintains compatibility with non-fdt
> > configurations because they still call kirkwood_init() in common.c.
> > 
> > As drivers are converted, we will reinstate the 'static' qualifier in
> > common.c.
> > 
> > Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> 
> Patches 4 and 5 both look ok, but since I merged the earlier versions
> of these into the stable next/board branch of arm-soc.git, you will have
> to generate these as incremental patches now, and adapt the changeset
> comments accordingly.

Ok.

> One small issue:
> 
> > --- a/arch/arm/mach-kirkwood/Kconfig
> > +++ b/arch/arm/mach-kirkwood/Kconfig
> > @@ -44,6 +44,20 @@ config MACH_GURUPLUG
> >  	  Say 'Y' here if you want your kernel to support the
> >  	  Marvell GuruPlug Reference Board.
> >  
> > +config ARCH_KIRKWOOD_DT
> > +	bool "Marvell Kirkwood Flattened Device Tree"
> > +	select USE_OF
> > +	help
> > +	  Say 'Y' here if you want your kernel to support the
> > +	  Marvell Kirkwood using flattened device tree.
> > +
> > +config MACH_DREAMPLUG_DT
> > +	bool "Marvell DreamPlug (Flattened Device Tree)"
> > +	select ARCH_KIRKWOOD_DT
> > +	help
> > +	  Say 'Y' here if you want your kernel to support the
> > +	  Marvell DreamPlug (Flattened Device Tree).
> > +
> 
> You allow ARCH_KIRKWOOD_DT to be enabled without also enabling
> dreamplug. That is ok, but
> 
> > +
> > +	if (of_machine_is_compatible("globalscale,dreamplug"))
> > +		dreamplug_init();
> > +
> 
> you call a function from dreamplug.o in board-dt.o and
> 
> > +/* board init functions for drivers not converted to fdt */
> > +void dreamplug_init(void);
> 
> you have an unconditional forward declaration in the header.
> 
> The idiomatic way to deal with this is to replace turn the
> declaration into
> 
> #ifdef CONFIG_DREAMPLUG_DT
> void dreamplug_init(void);
> #else
> static inline void dreamplug_init(void) {}
> #endif

Will do, thanks.

Jason.


From jason at lakedaemon.net  Tue Mar 13 09:18:07 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 13 Mar 2012 09:18:07 -0400
Subject: [PATCH 5/7 v2] ARM: kirkwood: convert uart0 to devicetree.
In-Reply-To: <970083c931bbd5c58be3aa982a66fddc48ceb534.1331601448.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <cover.1331601448.git.jason@lakedaemon.net>
 <970083c931bbd5c58be3aa982a66fddc48ceb534.1331601448.git.jason@lakedaemon.net>
Message-ID: <20120313131807.GH5050@titan.lakedaemon.net>

On Tue, Mar 13, 2012 at 01:57:47AM +0000, Jason Cooper wrote:
> This uart is the primary console for the dreamplug.  Removed
> kirkwood_uart0_init() call from board-dreamplug.c.
> 
> There are two uarts on the kirkwood SoC, all or none of them may be
> enabled, and the clock-frequency is board-dependant.  So, enabling and
> clock-frequency are left to the board dts.
> 
> Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> ---
> 
> Changes from v1:
> 
> * moved on-chip peripherals (uart's here) in kirkwood.dtsi and used ranges to
>   simplify addressing
> * disable uarts by default as not all boards enable them.  Can be enabled in
>   board file
> * specify clock-frequency in board file as it is board specific.  of_serial
>   prints an error message if it isn't specified (view with earlyprintk)
> * removed previous versions Reviewed-By's and Acked-By's as this is
>   significantly different from the previous version.
> 
>  arch/arm/boot/dts/kirkwood-dreamplug.dts |    7 +++++++
>  arch/arm/boot/dts/kirkwood.dtsi          |   26 +++++++++++++++++++++++++-
>  arch/arm/mach-kirkwood/board-dreamplug.c |    2 --
>  3 files changed, 32 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
> index 9946d01..a5376b8 100644
> --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
> +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
> @@ -14,4 +14,11 @@
>  	chosen {
>  		bootargs = "console=ttyS0,115200n8 earlyprintk";
>  	};
> +
> +	ocp at f1000000 {
> +		serial at 12000 {
> +			clock-frequency = <200000000>;
> +			status = "ok";
> +		};
> +	};

While this works on my board (I see console messages without
earlyprintk), I get the following:

Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
f1012000.serial: ttyS0 at MMIO 0xf1012000 (irq = 0) is a 16550A

Obviously, the interrupt should be 33.  Is this a bug?  Or, do I need to
re-specify all of the attributes when enabling a driver which was
/included/?

This could be an artifact of interrupt-controller not being defined in
the dt, yet.  I'll dig into it more.

thx,

Jason.

>  };
> diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
> index 702b955..825310b 100644
> --- a/arch/arm/boot/dts/kirkwood.dtsi
> +++ b/arch/arm/boot/dts/kirkwood.dtsi
> @@ -2,5 +2,29 @@
>  
>  / {
>  	compatible = "mrvl,kirkwood";
> -};
>  
> +	ocp at f1000000 {
> +		compatible = "simple-bus";
> +		ranges = <0 0xf1000000 0x1000000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		serial at 12000 {
> +			compatible = "ns16550a";
> +			reg = <0x12000 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <33>;
> +			/* set clock-frequency in board dts */
> +			status = "disabled";
> +		};
> +
> +		serial at 12100 {
> +			compatible = "ns16550a";
> +			reg = <0x12100 0x100>;
> +			reg-shift = <2>;
> +			interrupts = <34>;
> +			/* set clock-frequency in board dts */
> +			status = "disabled";
> +		};
> +	};
> +};
> diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
> index 3b37315..3fbfb7d 100644
> --- a/arch/arm/mach-kirkwood/board-dreamplug.c
> +++ b/arch/arm/mach-kirkwood/board-dreamplug.c
> @@ -135,8 +135,6 @@ void __init dreamplug_init(void)
>  	 */
>  	kirkwood_mpp_conf(dreamplug_mpp_config);
>  
> -	kirkwood_uart0_init();
> -
>  	spi_register_board_info(dreamplug_spi_slave_info,
>  				ARRAY_SIZE(dreamplug_spi_slave_info));
>  	kirkwood_spi_init();
> -- 
> 1.7.3.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From jason at lakedaemon.net  Tue Mar 13 09:22:16 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Tue, 13 Mar 2012 09:22:16 -0400
Subject: [PATCH 7/7] ARM: kirkwood: use devicetree for rtc-mv
In-Reply-To: <201203130958.31223.arnd@arndb.de>
References: <cover.1331601448.git.jason@lakedaemon.net>
 <92d02581e0fce75f84d61edf55678108237e881a.1331601448.git.jason@lakedaemon.net>
 <201203130958.31223.arnd@arndb.de>
Message-ID: <20120313132216.GI5050@titan.lakedaemon.net>

On Tue, Mar 13, 2012 at 09:58:30AM +0000, Arnd Bergmann wrote:
> On Tuesday 13 March 2012, Jason Cooper wrote:
> > 
> > Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> > ---
> >  arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
> >  arch/arm/mach-kirkwood/board-dt.c |    1 -
> >  arch/arm/mach-kirkwood/common.c   |    2 +-
> >  arch/arm/mach-kirkwood/common.h   |    1 -
> >  4 files changed, 7 insertions(+), 3 deletions(-)
> > 
> 
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> 
> I think you can just merge this with patch 6, as they are two halves
> of the same work.

Others working on kirkwood and dt asked me to separate the two to
facilitate integrating with their existing work.  I can undo if you
think it's best.

thx,

Jason.


From T.Mehnert at eckelmann.de  Tue Mar 13 09:22:25 2012
From: T.Mehnert at eckelmann.de (Mehnert, Torsten)
Date: Tue, 13 Mar 2012 13:22:25 +0000
Subject: AW: [PATCH] iomux-mx25.h slew rate adjusted for LCD __LD pins
In-Reply-To: <efb4350f3d236ae7feb088b9a5072b8c@mail.fqingenieria.es>
References: <3F263ABB4EDE344D974E1983B56807739E868EAB@EX-DAG01.eckelmann.group>
 <efb4350f3d236ae7feb088b9a5072b8c@mail.fqingenieria.es>
Message-ID: <3F263ABB4EDE344D974E1983B56807739E868F97@EX-DAG01.eckelmann.group>

> Hi

Hi again

> What a coincidence, we have been fighting with the LCD color issue on an i.MX258 about two weeks ago and came up with almost the same patch.
Sounds like we hit the problem in the right way. Super! :)

> > For some reason (sadly i don't identifying the patch right now) two 
> > LCD data lines configured PAD_CTL_SRE_SLOW (wrong slew rate) since 
> > Kernel 3.1. MX25_PAD_GPIO_E__LD16 and MX25_PAD_GPIO_F__LD17 This 
> > results in an fauly behaviour and strange color effects.
> >
> > To ensure that all LCD data pins configured with the proper slew rate, 
> > this patch changes to IOMUX define of all LCD __LDxx pins to 
> > PAD_CTL_SRE_FAST.

> For us it was enough to change the MX25_PAD_GPIO_E__LD16 and
> MX25_PAD_GPIO_F__LD17 pins to PAD_CTL_SRE_FAST. Why do you need to change the others too? Could this introduce undesired signal noise on the board? We actually experience a weird effect on the ADC lines. It's all 
> been discussed here:
For our display problem it's also enough to set MX25_PAD_GPIO_E__LD16 and MX25_PAD_GPIO_F__LD17 to fast slew rate. So far i can confirm that your patch solves the problem.

The reason I decided to change the other line muxings too is the tought, that when these two lines need to set to fast slew rate, all other line need to set to fast slew rate too.
For some reason (I actually don't know) the other lines seems to be set >implicit< correctly to fast slew rate. In order to avoid future problems I set them explicit to fast slew rate.

Seeing the aspect that all LD lines implicit set to fast slew rate, there would no electrical change if you set them explicit. For all the other lines (not LD16 and LD17)
The code effectivly changes nothing, but ensures the fast slew rate in future. 
That's the idea, but I can't confirm my assumption by measurement.
What's your opinion? 

I checked my ADC right now. We use it to read out touchscreen. I can't find any problems, all seems to be okay.
What's your use of it?

>  It's all been discussed here
shame on me, I missed the post.^^ But I will read it now.

> > This problem may affect other mx25 platforms like mx25pdk. Sadly i 
> > can't test it. Of course this problem shouldn't occur when you done 
> > your LCD muxing correctly in the bootloader.

> Would you care to explain how to perform the "LCD muxing correctly" in the bootloader and why it should influence what the kernel does?

We have moved our Kernel from 3.0 to 3.2 the LCD problem occurs.
When booting the 3.0 kernel and the reboot and "warm starting" the 3.2 kernel the display running fine.
When "cold starting" the 3.2 kernel the display problem occurs.

So that lead to the knowledge that there must be an initialization problem. What happened?
The 3.0 kernel starts and init the pins correctly. These pin settings kept by "warm starting" the 3.2
Kernel, so it can drive the display correctly. So the 3.2 seems not touching these settings.

So far I've come to the idea, that the problem shouldn't occur on boards where the muxing of the LCD
completely done by bootloader. Which is not in my case, but I think this theory could explain it
when some mx25 board dons't have the problem with the lcd.


> I will test your patch (adding PAD_CTL_SRE_FAST to all __LDxx pins instead of just LD16 and LD17) and report back. In any case, I can confirm that without this patch the LCD has weird colors. Juergen Beisert has more iomux
> mx25.h changes, especially with regard to PWM, so I reckon he'll send them upstream soon enough.
Thanks

> @@ -468,11 +468,11 @@
>  #define MX25_PAD_GPIO_C__CAN2_TX	IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0,
> PAD_CTL_PUS_22K_UP)
>
>  #define MX25_PAD_GPIO_D__GPIO_D		IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0,
> NO_PAD_CTRL)
> -#define MX25_PAD_GPIO_E__LD16		IOMUX_PAD(0x400, 0x204, 0x02, 0, 0,
> NO_PAD_CTRL)
> +#define MX25_PAD_GPIO_E__LD16		IOMUX_PAD(0x400, 0x204, 0x02, 0, 0,
> PAD_CTL_SRE_FAST)
>  #define MX25_PAD_GPIO_D__CAN2_RX	IOMUX_PAD(0x3fc, 0x200, 0x16,
> 0x484, 1, PAD_CTL_PUS_22K_UP)
>
>  #define MX25_PAD_GPIO_E__GPIO_E		IOMUX_PAD(0x400, 0x204, 0x10, 0, 0,
> NO_PAD_CTRL)
> -#define MX25_PAD_GPIO_F__LD17		IOMUX_PAD(0x404, 0x208, 0x02, 0, 0,
> NO_PAD_CTRL)
> +#define MX25_PAD_GPIO_F__LD17		IOMUX_PAD(0x404, 0x208, 0x02, 0, 0,
> PAD_CTL_SRE_FAST)
>  #define MX25_PAD_GPIO_E__AUD7_TXD	IOMUX_PAD(0x400, 0x204, 0x14, 0,
> 0, NO_PAD_CTRL)
>
>  #define MX25_PAD_GPIO_F__GPIO_F		IOMUX_PAD(0x404, 0x208, 0x10, 0, 0,
> NO_PAD_CTRL)

> As mentioned above, this is the only part we needed from the patch to address the wrong slew rate for the LCD color wash-out. But I am curious as to hear your explanation with regard to changing the slew rate of the other > __LDxx pins.

I must admit that I'm not the most experienced kernel developer, so far it would be possible that the idea of setting all LDxx pins explicit fast is not the best idea.
So I hoping for a divine inspiration :)

Thanks for your answer
Torsten

Best regards
--
Joan C. Abelaira


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From s.hauer at pengutronix.de  Tue Mar 13 09:30:06 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 13 Mar 2012 14:30:06 +0100
Subject: [PATCH 1/2] ARM: mx35: 3ds: add mc9s08dz60 gpio definitions
In-Reply-To: <1331528279-2263-1-git-send-email-b39297@freescale.com>
References: <1331528279-2263-1-git-send-email-b39297@freescale.com>
Message-ID: <20120313133006.GF3852@pengutronix.de>

On Mon, Mar 12, 2012 at 12:57:58PM +0800, Wu Guoxing wrote:
> add a new header file for mx35 3ds board
> add the mc9s08dz60 gpio definitions
> 
> Signed-off-by: Wu Guoxing <b39297 at freescale.com>
> ---
>  arch/arm/plat-mxc/include/mach/board_mx35_3ds.h |   26 +++++++++++++++++++++++
>  1 files changed, 26 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/plat-mxc/include/mach/board_mx35_3ds.h
> 
> diff --git a/arch/arm/plat-mxc/include/mach/board_mx35_3ds.h b/arch/arm/plat-mxc/include/mach/board_mx35_3ds.h
> new file mode 100644
> index 0000000..df0d5f7
> --- /dev/null
> +++ b/arch/arm/plat-mxc/include/mach/board_mx35_3ds.h
> @@ -0,0 +1,26 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + * Author: Wu Guoxing <b39297 at freescale.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __ASM_ARCH_MXC_BOARD_MX35_3DS_H__
> +#define __ASM_ARCH_MXC_BOARD_MX35_3DS_H__
> +
> +#define GPIO_MC9S08DZ60_GPS_ENABLE 0
> +#define GPIO_MC9S08DZ60_HDD_ENABLE 4
> +#define GPIO_MC9S08DZ60_WIFI_ENABLE 5
> +#define GPIO_MC9S08DZ60_LCD_ENABLE 6
> +#define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8

Please add these to the board file instead. They are not useful outside
the board.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From s.hauer at pengutronix.de  Tue Mar 13 09:35:04 2012
From: s.hauer at pengutronix.de (Sascha Hauer [s.hauer@pengutronix.de] (s.hauer@pengutronix.de))
Date: Tue, 13 Mar 2012 14:35:04 +0100
Subject: [PATCH] iomux-mx25.h slew rate adjusted for LCD __LD pins
In-Reply-To: <3F263ABB4EDE344D974E1983B56807739E868EAB@EX-DAG01.eckelmann.group>
References: <3F263ABB4EDE344D974E1983B56807739E868EAB@EX-DAG01.eckelmann.group>
Message-ID: <20120313133504.GN26642@pengutronix.de>

On Tue, Mar 13, 2012 at 11:35:22AM +0000, Mehnert, Torsten wrote:
> From: Mehnert <tmehnert at eckelmann.de>
> Date: Mon, 13 Mar 2012 12:13:51 +0100
> Subject: [PATCH] iomux-mx25.h slew rate adjusted for LCD __LD pins
> 
> For some reason (sadly i don't identifying the patch right now)
> two LCD data lines configured PAD_CTL_SRE_SLOW (wrong slew rate)
> since Kernel 3.1. MX25_PAD_GPIO_E__LD16 and MX25_PAD_GPIO_F__LD17
> This results in an fauly behaviour and strange color effects.
> 
> To ensure that all LCD data pins configured with the proper slew rate,
> this patch changes to IOMUX define of all LCD __LDxx pins to PAD_CTL_SRE_FAST.
> 
> This problem may affect other mx25 platforms like mx25pdk. Sadly i can't test
> it. Of course this problem shouldn't occur when you done your LCD muxing 
> correctly in the bootloader.

Applied, thanks

Sascha

> 
> Best regards,
> Torsten
> 
> ---
> --- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h	2012-02-28 00:43:05.000000000 +0100
> +++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h	2012-03-13 12:08:39.920736789 +0100
> @@ -139,15 +139,15 @@
>  #define MX25_PAD_NFRB__GPIO_3_31	IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
>  
>  #define MX25_PAD_D15__D15		IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
> -#define MX25_PAD_D15__LD16		IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_D15__LD16		IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_D15__GPIO_4_5		IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
>  
>  #define MX25_PAD_D14__D14		IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
> -#define MX25_PAD_D14__LD17		IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_D14__LD17		IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_D14__GPIO_4_6		IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
>  
>  #define MX25_PAD_D13__D13		IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
> -#define MX25_PAD_D13__LD18		IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_D13__LD18		IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_D13__GPIO_4_7		IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
>  
>  #define MX25_PAD_D12__D12		IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
> @@ -192,54 +192,54 @@
>  #define MX25_PAD_D0__D0			IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
>  #define MX25_PAD_D0__GPIO_4_20		IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD0__LD0		IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD0__LD0		IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD0__CSI_D0		IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
>  #define MX25_PAD_LD0__GPIO_2_15		IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD1__LD1		IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD1__LD1		IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD1__CSI_D1		IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
>  #define MX25_PAD_LD1__GPIO_2_16		IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD2__LD2		IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD2__LD2		IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD2__GPIO_2_17		IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD3__LD3		IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD3__LD3		IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD3__GPIO_2_18		IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD4__LD4		IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD4__LD4		IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD4__GPIO_2_19		IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD5__LD5		IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD5__LD5		IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD5__GPIO_1_19		IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD6__LD6		IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD6__LD6		IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD6__GPIO_1_20		IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD7__LD7		IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD7__LD7		IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD7__GPIO_1_21		IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD8__LD8		IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD8__LD8		IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD8__FEC_TX_ERR	IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD9__LD9		IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD9__LD9		IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD9__FEC_COL		IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD10__LD10		IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD10__LD10		IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD10__FEC_RX_ER	IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD11__LD11		IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD11__LD11		IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD11__FEC_RDATA2	IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD12__LD12		IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD12__LD12		IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD12__FEC_RDATA3	IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD13__LD13		IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD13__LD13		IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD13__FEC_TDATA2	IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD14__LD14		IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD14__LD14		IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD14__FEC_TDATA3	IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
>  
> -#define MX25_PAD_LD15__LD15		IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_LD15__LD15		IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_LD15__FEC_RX_CLK	IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
>  
>  #define MX25_PAD_HSYNC__HSYNC		IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
> @@ -468,11 +468,11 @@
>  #define MX25_PAD_GPIO_C__CAN2_TX	IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
>  
>  #define MX25_PAD_GPIO_D__GPIO_D		IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
> -#define MX25_PAD_GPIO_E__LD16		IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_GPIO_E__LD16		IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_GPIO_D__CAN2_RX	IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
>  
>  #define MX25_PAD_GPIO_E__GPIO_E		IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
> -#define MX25_PAD_GPIO_F__LD17		IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL)
> +#define MX25_PAD_GPIO_F__LD17		IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
>  #define MX25_PAD_GPIO_E__AUD7_TXD	IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
>  
>  #define MX25_PAD_GPIO_F__GPIO_F		IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
> ---
> Torsten Mehnert
> K?lte- und Geb?udeleittechnik (KGL)
> ?
> ECKELMANN AG
> Berliner Stra?e 161
> D - 65205 Wiesbaden
> ?
> Phone:	+49 (0) 611 / 7103 - 370
> Fax:	+49 (0) 611 / 7103 - 133
> 
> e-Mail:	mailto:t.mehnert at eckelmann.de
> Web:	http://www.eckelmann.de
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Mar 13 09:36:10 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 13 Mar 2012 14:36:10 +0100
Subject: [GIT PULL] i.MX25 iomux fix
Message-ID: <20120313133610.GH3852@pengutronix.de>

Hi Arnd, Olof,

Please pull the following (non urgent, for next) fix for the i.MX25
iomux.

Sascha

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

  Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:

  git://git.pengutronix.de/git/imx/linux-2.6.git tags/imx25-iomux-ds

for you to fetch changes up to 1dde9f75b658edcd4fb7e00259206d727702ce61:

  iomux-mx25.h slew rate adjusted for LCD __LD pins (2012-03-13 13:57:07 +0100)

----------------------------------------------------------------
ARM i.MX25: iomux lcd drivestrength fixes

----------------------------------------------------------------
Mehnert (1):
      iomux-mx25.h slew rate adjusted for LCD __LD pins

 arch/arm/plat-mxc/include/mach/iomux-mx25.h |   42 +++++++++++++-------------
 1 files changed, 21 insertions(+), 21 deletions(-)
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Tue Mar 13 09:44:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 13:44:37 +0000
Subject: [PATCH 7/7] ARM: kirkwood: use devicetree for rtc-mv
In-Reply-To: <20120313132216.GI5050@titan.lakedaemon.net>
References: <cover.1331601448.git.jason@lakedaemon.net>
 <201203130958.31223.arnd@arndb.de>
 <20120313132216.GI5050@titan.lakedaemon.net>
Message-ID: <201203131344.37661.arnd@arndb.de>

On Tuesday 13 March 2012, Jason Cooper wrote:
> On Tue, Mar 13, 2012 at 09:58:30AM +0000, Arnd Bergmann wrote:
> > On Tuesday 13 March 2012, Jason Cooper wrote:
> > > 
> > > Signed-off-by: Jason Cooper <jason at lakedaemon.net>
> > > ---
> > >  arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
> > >  arch/arm/mach-kirkwood/board-dt.c |    1 -
> > >  arch/arm/mach-kirkwood/common.c   |    2 +-
> > >  arch/arm/mach-kirkwood/common.h   |    1 -
> > >  4 files changed, 7 insertions(+), 3 deletions(-)
> > > 
> > 
> > Acked-by: Arnd Bergmann <arnd at arndb.de>
> > 
> > I think you can just merge this with patch 6, as they are two halves
> > of the same work.
> 
> Others working on kirkwood and dt asked me to separate the two to
> facilitate integrating with their existing work.  I can undo if you
> think it's best.

No, just ignore my comment in that case. If it helps anyone to
split the patches, it's definitely ok to do so, I just didn't
see any reason why you would.

	Arnd


From alexg at meprolight.com  Tue Mar 13 09:50:35 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Tue, 13 Mar 2012 15:50:35 +0200
Subject: [PATCH] i.MX35-PDK: Add Camera support
In-Reply-To: <20120313133333.GG3852@pengutronix.de>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A2A@MEP-EXCH.meprolight.com>

Hi Sascha,

Thanks for you comments.
 
> In i.MX35-PDK, OV2640  camera is populated on the
> personality board. This camera is registered as a subdevice via soc-camera interface.
> 
> Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
> ---
>  arch/arm/mach-imx/mach-mx35_3ds.c |   87 +++++++++++++++++++++++++++++++++++++
>  1 files changed, 87 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c

> > This one does not apply as it is obviously based on (an earlier version
> > of) the framebuffer patches of this board. Please always base your stuff
> > on some -rc kernel. We can resolve conflicts later upstream, but we
> > cannot easily apply a patch when we do not have the correct base.

> >Please add the linux arm kernel mailing list next time.

Oh what a stupid mistake, I will correct it.

Regards,

Alex Gershgorin


From rnayak at ti.com  Tue Mar 13 09:55:27 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 13 Mar 2012 19:25:27 +0530
Subject: [PATCH 1/2] ARM: omap: hwmod: Restore sysc after a reset
In-Reply-To: <1331646928-31119-1-git-send-email-rnayak@ti.com>
References: <1331646928-31119-1-git-send-email-rnayak@ti.com>
Message-ID: <1331646928-31119-2-git-send-email-rnayak@ti.com>

After a softreset, make sure the sysc settings are correctly
restored.

Reported-by: Anand Gadiyar <gadiyar at ti.com>
Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index eba6cd3..ae56939 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2270,6 +2270,10 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
 
 	spin_lock_irqsave(&oh->_lock, flags);
 	r = _reset(oh);
+	if (oh->class->sysc) {
+		_update_sysc_cache(oh);
+		_enable_sysc(oh);
+	}
 	spin_unlock_irqrestore(&oh->_lock, flags);
 
 	return r;
-- 
1.7.1



From rnayak at ti.com  Tue Mar 13 09:55:28 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 13 Mar 2012 19:25:28 +0530
Subject: [PATCH 2/2] ARM: omap: hwmod: Make omap_hwmod_softreset wait for
 reset status
In-Reply-To: <1331646928-31119-1-git-send-email-rnayak@ti.com>
References: <1331646928-31119-1-git-send-email-rnayak@ti.com>
Message-ID: <1331646928-31119-3-git-send-email-rnayak@ti.com>

omap_hwmod_softreset() does not seem to wait for reset status
after doing a softreset. Make it use _ocp_softreset() instead
which does this correctly.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Anand Gadiyar <gadiyar at ti.com>
Cc: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   14 +++-----------
 1 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index ae56939..9b49440 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1907,20 +1907,12 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
  */
 int omap_hwmod_softreset(struct omap_hwmod *oh)
 {
-	u32 v;
-	int ret;
-
-	if (!oh || !(oh->_sysc_cache))
+	if (!oh)
 		return -EINVAL;
 
-	v = oh->_sysc_cache;
-	ret = _set_softreset(oh, &v);
-	if (ret)
-		goto error;
-	_write_sysconfig(v, oh);
+	_ocp_softreset(oh);
 
-error:
-	return ret;
+	return 0;
 }
 
 /**
-- 
1.7.1



From rnayak at ti.com  Tue Mar 13 09:55:26 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 13 Mar 2012 19:25:26 +0530
Subject: [PATCH 0/2] Fixes in hwmod reset code
Message-ID: <1331646928-31119-1-git-send-email-rnayak@ti.com>

This fixes a couple of issues around hwmod reset
APIs'.
Patches are based on 3.3.-rc7.

Rajendra Nayak (2):
  ARM: omap: hwmod: Restore sysc after a reset
  ARM: omap: hwmod: Make omap_hwmod_softreset wait for reset status

 arch/arm/mach-omap2/omap_hwmod.c |   18 +++++++-----------
 1 files changed, 7 insertions(+), 11 deletions(-)



From joancarles at fqingenieria.es  Tue Mar 13 09:58:10 2012
From: joancarles at fqingenieria.es (joancarles)
Date: Tue, 13 Mar 2012 14:58:10 +0100
Subject: AW: [PATCH] iomux-mx25.h slew rate adjusted for LCD __LD pins
In-Reply-To: <3F263ABB4EDE344D974E1983B56807739E868F97@EX-DAG01.eckelmann.group>
References: <3F263ABB4EDE344D974E1983B56807739E868EAB@EX-DAG01.eckelmann.group>
 <efb4350f3d236ae7feb088b9a5072b8c@mail.fqingenieria.es>
 <3F263ABB4EDE344D974E1983B56807739E868F97@EX-DAG01.eckelmann.group>
Message-ID: <09e474eba58108ebf43032efbe40e244@mail.fqingenieria.es>

Hi

>> What a coincidence, we have been fighting with the LCD color issue 
>> on an i.MX258 about two weeks ago and came up with almost the same 
>> patch.
> Sounds like we hit the problem in the right way. Super! :)

I am glad there's someone else with the same issue and solution ;).

>> For us it was enough to change the MX25_PAD_GPIO_E__LD16 and
>> MX25_PAD_GPIO_F__LD17 pins to PAD_CTL_SRE_FAST. Why do you need to 
>> change the others too? Could this introduce undesired signal noise on 
>> the board? We actually experience a weird effect on the ADC lines. 
>> It's all
>> been discussed here:
> For our display problem it's also enough to set MX25_PAD_GPIO_E__LD16
> and MX25_PAD_GPIO_F__LD17 to fast slew rate. So far i can confirm 
> that
> your patch solves the problem.

Good to know.

> The reason I decided to change the other line muxings too is the
> tought, that when these two lines need to set to fast slew rate, all
> other line need to set to fast slew rate too.
> For some reason (I actually don't know) the other lines seems to be
> set >implicit< correctly to fast slew rate. In order to avoid future
> problems I set them explicit to fast slew rate.

I see. Well, we shouldn't be taping possible future failures of 
hardware configuration, since the original change wasn't provoked in any 
way by a change of the slew rate of the before mentioned pins. I reckon 
it has more to do with the different ways the mx25 is initialized these 
days compared to, let's say 2.6.39.x (which was the last kernel our LCD 
screen worked without wash-out and no changes to the slew rate of said 
pins).

> Seeing the aspect that all LD lines implicit set to fast slew rate,

How do you see that?

> there would no electrical change if you set them explicit. For all 
> the
> other lines (not LD16 and LD17)
> The code effectivly changes nothing, but ensures the fast slew rate
> in future.
> That's the idea, but I can't confirm my assumption by measurement.
> What's your opinion?

I could give it a go on the oscilloscope, however the changes in the 
signal tangent might be really tiny.

> I checked my ADC right now. We use it to read out touchscreen. I
> can't find any problems, all seems to be okay.
> What's your use of it?

Touchscreen only, however we've been having our share of fun with it. 
It's still not stable, but that's largely off-topic here at the moment. 
Juergen Beisert (our local hero) has written a ADC/TS driver from 
scratch for the i.MX25 platforms, which is very nicely engineered and 
seems to work just fine. He's posted it to this list a couple of days 
ago for initial comment. After some changes with regard to 
HSYNC/Polarity settings to his driver and some capacitors to the lines 
between the LCD and the ADC, we have a more or less stable reading, with 
a jitter of +-8px.

>>  It's all been discussed here
> shame on me, I missed the post.^^ But I will read it now.

No, shame on me, I forgot to post the link to the discussion, which has 
not at all happened on this mailing list. Here it is:

http://news.gmane.org/gmane.comp.embedded.ptxdist.oselas.community

Search for the "Kernel 3.3 custom mx25 device touchscreen issues" 
thread to find the whole development of two issues: the touchscreen not 
working because of other hardware failures and an initially flaky TS/ADC 
driver, and this issue with regard to the LCD washout effects.

>> Would you care to explain how to perform the "LCD muxing correctly" 
>> in the bootloader and why it should influence what the kernel does?
>
> We have moved our Kernel from 3.0 to 3.2 the LCD problem occurs.
> When booting the 3.0 kernel and the reboot and "warm starting" the
> 3.2 kernel the display running fine.
> When "cold starting" the 3.2 kernel the display problem occurs.

Interesting! What's your device? A custom mx25 board?

> So that lead to the knowledge that there must be an initialization
> problem. What happened?
> The 3.0 kernel starts and init the pins correctly. These pin settings
> kept by "warm starting" the 3.2
> Kernel, so it can drive the display correctly. So the 3.2 seems not
> touching these settings.

For us this did not happen. Booting a 2.6.39.3 kernel worked correctly 
and subsequently "warm starting" or rebooting  with an unpatched 3.3 
kernel created these wash-out effects on our LCD.

> So far I've come to the idea, that the problem shouldn't occur on
> boards where the muxing of the LCD
> completely done by bootloader. Which is not in my case, but I think
> this theory could explain it
> when some mx25 board dons't have the problem with the lcd.

I haven't had a look at the bootloader yet, we're using an old version 
(2010) of u-boot. The issue there is that we boot from NOR and made a 
lot of patches to support our device. Forward porting to a newer release 
of u-boot right now seems like a daunting task, as too many things have 
changed since.

> I must admit that I'm not the most experienced kernel developer, so
> far it would be possible that the idea of setting all LDxx pins
> explicit fast is not the best idea.

 From many years ago, working on the Intel side of kernel hacking, I 
remember that in the community there was always some resistance in 
accepting patches where the origins of the failure of a component wasn't 
really 100% clear. It's clear here, but your patch seems to change 
additional default values for no apparent reason, other than preventing 
another debugging session in the future, should this incidence occur 
again with regard to the other __LDxx pins.

> So I hoping for a divine inspiration :)

That's two of us now ;).

Thanks for your time and insightful discussion.

Cheers
-- 
Joan C. Abelaira
  FQ Ingenier?a Electr?nica, S.A.
Pol?gon Industrial Vilanoveta
Av. de les Roquetes, 9
E-08812 Sant Pere de Ribes (Barcelona)
SPAIN
Telf: +34 932 080 258
Fax: +34 934 592 893
M?vil: +34 638 331 745

http://www.fqingenieria.es/
email: joancarles at fqingenieria.es


From rnayak at ti.com  Tue Mar 13 09:59:09 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 13 Mar 2012 19:29:09 +0530
Subject: [PATCH 2/2] ARM: omap: hwmod: Make omap_hwmod_softreset wait
 for reset status
In-Reply-To: <1331646928-31119-3-git-send-email-rnayak@ti.com>
References: <1331646928-31119-1-git-send-email-rnayak@ti.com>
 <1331646928-31119-3-git-send-email-rnayak@ti.com>
Message-ID: <4F5F52AD.6090009@ti.com>

On Tuesday 13 March 2012 07:25 PM, Rajendra Nayak wrote:
> omap_hwmod_softreset() does not seem to wait for reset status
> after doing a softreset. Make it use _ocp_softreset() instead
> which does this correctly.
>
> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
> Cc: Benoit Cousson<b-cousson at ti.com>
> Cc: Paul Walmsley<paul at pwsan.com>
> Cc: Anand Gadiyar<gadiyar at ti.com>
> Cc: Shubhrajyoti D<shubhrajyoti at ti.com>
> ---
>   arch/arm/mach-omap2/omap_hwmod.c |   14 +++-----------
>   1 files changed, 3 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index ae56939..9b49440 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -1907,20 +1907,12 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
>    */
>   int omap_hwmod_softreset(struct omap_hwmod *oh)
>   {
> -	u32 v;
> -	int ret;
> -
> -	if (!oh || !(oh->_sysc_cache))
> +	if (!oh)
>   		return -EINVAL;
>
> -	v = oh->_sysc_cache;
> -	ret = _set_softreset(oh,&v);
> -	if (ret)
> -		goto error;
> -	_write_sysconfig(v, oh);
> +	_ocp_softreset(oh);
>
> -error:
> -	return ret;
> +	return 0;

Just realized, this should be 'return _ocp_softreset(oh);'
instead. will fix and repost.

>   }
>
>   /**



From marc.zyngier at arm.com  Tue Mar 13 09:58:58 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 13 Mar 2012 13:58:58 +0000
Subject: Conflict between Versatile Express DT conversion and local timer
 updates
In-Reply-To: <201203131155.16454.arnd@arndb.de>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <20120313101525.GA569@n2100.arm.linux.org.uk> <4F5F2859.5020407@arm.com>
 <201203131155.16454.arnd@arndb.de>
Message-ID: <4F5F52A2.3050005@arm.com>

On 13/03/12 11:55, Arnd Bergmann wrote:
> On Tuesday 13 March 2012, Marc Zyngier wrote:
>> On 13/03/12 10:15, Russell King - ARM Linux wrote:
>>> On Tue, Mar 13, 2012 at 09:39:57AM +0000, Marc Zyngier wrote:
>>>> On 13/03/12 01:23, Olof Johansson wrote:
>>>>> Hi,
>>>>>
>>>>> On Mon, Mar 12, 2012 at 4:59 PM, Russell King - ARM Linux
>>>>> <linux at arm.linux.org.uk> wrote:
>>>>>>
>>>>>> Correction: I haven't been pushing out my devel-stable branch for
>>>>>> apparantly two months (according to gitweb, and no one noticed?), so I
>>>>>> could drop the merge of Marc's tree until the conflicts can be sanely
>>>>>> resolved.
>>>>>
>>>>> I haven't noticed because I stopped tracking your tree directly when
>>>>> you were having server load issues; I tend to have kept an eye on
>>>>> linux-next-level breakage instead, but probably not as close as I
>>>>> should have.
>>>>>
>>>>> Dropping Marc's branch and having him either resubmit on top of
>>>>> arm-soc like the io cleanup was done, or pull it in as an early
>>>>> dependency for 3.5 and stage it in an for-armsoc branch sounds like
>>>>> two good options to me, with no real preference in either direction.
>>>>
>>>> I'm happy to rebase my patches on anything that will make the merge
>>>> easier (IOW conflict-less).
>>>>
>>>> Russell, would you prefer this series to go via armsoc? This seems the
>>>> cleanest solution for the time being.
>>>
>>> With a lot of these core ARM changes, there's a very fine line between
>>> whether they are core ARM changes or whether they're platform level
>>> changes (many core ARM changes will impact lots of platforms.)  I'm just
>>> wondering if there's any point to taking these changes through my tree.
>>> It seems utterly pointless if they're going to keep conflicting with
>>> platform stuff.
>>
>> Fair enough.
>>
>> Olof, Arnd: which is the most base for you to take this series?
> 
> I'm not sure I understand your question. The conflicts that Russell
> mentioned are with the ux500/timer (in next/soc) and with the
> vexpress/dt (in next/dt) branches. There are multiple ways out of
> here:
> 
> a) take your series first, but merge it into the next/dt and next/soc
>    branches, resolving the conflicts in the process. This would be
>    fairly easy to do if you can provide the merge resolution as
>    a git pull and let Russell still take your series as is.
> 
> b) rebase your series on top of vexpress/dt, merge it into the next/soc
>    branch.
> 
> c) rebase your series on top of ux500/timer, merge it into the next/dt
>    branch.
> 
> d) create a new next/timer branch in arm-soc that has Pawel's     
>    98ed4ceb "ARM: vexpress: Get rid of MMIO_P2V" (the first patch from
>    vexpress/dt, your patches and the ux500/timer series. Also put
>    98ed4ceb into the next/cleanup branch.
> 
> Any of those will work for us, my preference would be on #4. I have
> created the next/timer branch in the arm-soc tree, so you can use
> that and either rebase your patches on top or merge your tree into
> it and fix up the merge conflicts.

Thanks for doing that Arnd.

I've thus created a new branch:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
local_timers-for-arm-soc

which contains the arm-soc next/timers branch as well as my local timers
series. I'd greatly appreciate if you could pull it for 3.4.

Thanks again,

	M.
-- 
Jazz is not dead. It just smells funny...



From rnayak at ti.com  Tue Mar 13 10:03:53 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 13 Mar 2012 19:33:53 +0530
Subject: [PATCH v2 0/2] Fixes in hwmod reset code
Message-ID: <1331647435-31666-1-git-send-email-rnayak@ti.com>

This fixes a couple of issues around hwmod reset
APIs'.
Patches are based on 3.3.-rc7.

Rajendra Nayak (2):
  ARM: omap: hwmod: Restore sysc after a reset
  ARM: omap: hwmod: Make omap_hwmod_softreset wait for reset status

 arch/arm/mach-omap2/omap_hwmod.c |   18 ++++++------------
 1 files changed, 6 insertions(+), 12 deletions(-)



From rnayak at ti.com  Tue Mar 13 10:03:54 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 13 Mar 2012 19:33:54 +0530
Subject: [PATCH v2 1/2] ARM: omap: hwmod: Restore sysc after a reset
In-Reply-To: <1331647435-31666-1-git-send-email-rnayak@ti.com>
References: <1331647435-31666-1-git-send-email-rnayak@ti.com>
Message-ID: <1331647435-31666-2-git-send-email-rnayak@ti.com>

After a softreset, make sure the sysc settings are correctly
restored.

Reported-by: Anand Gadiyar <gadiyar at ti.com>
Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index eba6cd3..ae56939 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2270,6 +2270,10 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
 
 	spin_lock_irqsave(&oh->_lock, flags);
 	r = _reset(oh);
+	if (oh->class->sysc) {
+		_update_sysc_cache(oh);
+		_enable_sysc(oh);
+	}
 	spin_unlock_irqrestore(&oh->_lock, flags);
 
 	return r;
-- 
1.7.1



From rnayak at ti.com  Tue Mar 13 10:03:55 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 13 Mar 2012 19:33:55 +0530
Subject: [PATCH v2 2/2] ARM: omap: hwmod: Make omap_hwmod_softreset wait for
 reset status
In-Reply-To: <1331647435-31666-1-git-send-email-rnayak@ti.com>
References: <1331647435-31666-1-git-send-email-rnayak@ti.com>
Message-ID: <1331647435-31666-3-git-send-email-rnayak@ti.com>

omap_hwmod_softreset() does not seem to wait for reset status
after doing a softreset. Make it use _ocp_softreset() instead
which does this correctly.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Anand Gadiyar <gadiyar at ti.com>
Cc: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   14 ++------------
 1 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index ae56939..489f82d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1907,20 +1907,10 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
  */
 int omap_hwmod_softreset(struct omap_hwmod *oh)
 {
-	u32 v;
-	int ret;
-
-	if (!oh || !(oh->_sysc_cache))
+	if (!oh)
 		return -EINVAL;
 
-	v = oh->_sysc_cache;
-	ret = _set_softreset(oh, &v);
-	if (ret)
-		goto error;
-	_write_sysconfig(v, oh);
-
-error:
-	return ret;
+	return _ocp_softreset(oh);
 }
 
 /**
-- 
1.7.1



From alexg at meprolight.com  Tue Mar 13 10:04:50 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Tue, 13 Mar 2012 16:04:50 +0200
Subject: [PATCH] i.MX35-PDK: Add Camera support
In-Reply-To: <CAOMZO5Dmf3mqDZkrhnFLrFyc90vk8Vyfv5mwrFfWsY-05=AyJg@mail.gmail.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CBD666A2B@MEP-EXCH.meprolight.com>

Hi Fabio,



On Mon, Mar 12, 2012 at 1:28 PM, Alex <alexg at meprolight.com> wrote:
> In i.MX35-PDK, OV2640 ?camera is populated on the
> personality board. This camera is registered as a subdevice via soc-camera interface.
>
> Signed-off-by: Alex Gershgorin <alexg at meprolight.com>

> >Are you able to get the camera working correctly now?

> >Or are you still facing the issues you reported earlier?

This problem not solved, I'm still doing testing

Thanks
Alex Gershgorin


From w.sang at pengutronix.de  Tue Mar 13 10:08:22 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 13 Mar 2012 15:08:22 +0100
Subject: [PATCH 1/5 v4] i2c/gpio: add DT support
In-Reply-To: <1331642024-19869-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331642024-19869-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120313140822.GD2488@pengutronix.de>

On Tue, Mar 13, 2012 at 01:33:40PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:

> update to use devm_kzalloc for private data

Hmm, you need really to work on the commit messages, not everybody is
familiar with DT and its implications:

"To achieve DT support, we need to populate a custom platform_data in a
private struct from DT information. To simplify code, the adapter and
algorithm are also put into the private struct."

Something like this?

> ---
> v4:
> 
> 	fix timeout

You need to work on the changelogs as well :)

> 	use gpio_is_valid

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From m.szyprowski at samsung.com  Tue Mar 13 10:14:20 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 13 Mar 2012 15:14:20 +0100
Subject: [PATCH 2/3] ARM: Exynos: Add DRM core device support for Universal
 C210 board
In-Reply-To: <CAH9JG2UWE1CNOrHVtMawS9TrPHHZrgpbVwvgmXb4OiLObnxdsA@mail.gmail.com>
References: <1331291105-18152-1-git-send-email-m.szyprowski@samsung.com>
 <1331291105-18152-3-git-send-email-m.szyprowski@samsung.com>
 <CAK9yfHyHoDucPwvZbb_ireRTohkd9hCDf3ER_yp3Rv_7BmNwhg@mail.gmail.com>
 <CAH9JG2UWE1CNOrHVtMawS9TrPHHZrgpbVwvgmXb4OiLObnxdsA@mail.gmail.com>
Message-ID: <031601cd0123$9626a2d0$c273e870$%szyprowski@samsung.com>

Hello,

On Tuesday, March 13, 2012 5:39 AM Kyungmin Park wrote:

> On 3/13/12, Sachin Kamat <sachin.kamat at linaro.org> wrote:
> > Hi Marek,
> > Thanks for the patch.
> >
> > On 09/03/2012, Marek Szyprowski <m.szyprowski at samsung.com> wrote:
> >> Add core DRM device and alternative platform device data for FIMD DRM
> >> subdriver. Based on the initial patch by Joonyoung Shim
> >> <jy0922.shim at samsung.com>
> >>
> >> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> >> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> >> ---
> >>  arch/arm/mach-exynos/Kconfig               |    1 +
> >>  arch/arm/mach-exynos/mach-universal_c210.c |   31
> >> ++++++++++++++++++++++++++++
> >>  2 files changed, 32 insertions(+), 0 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> >> index 5a26944..c73eeba 100644
> >> --- a/arch/arm/mach-exynos/Kconfig
> >> +++ b/arch/arm/mach-exynos/Kconfig
> >> @@ -257,6 +257,7 @@ config MACH_UNIVERSAL_C210
> >>  	select S5P_DEV_ONENAND
> >>  	select S5P_DEV_TV
> >>  	select EXYNOS4_DEV_DMA
> >> +	select EXYNOS_DEV_DRM
> >>  	select EXYNOS4_SETUP_FIMD0
> >>  	select EXYNOS4_SETUP_I2C1
> >>  	select EXYNOS4_SETUP_I2C3
> >> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c
> >> b/arch/arm/mach-exynos/mach-universal_c210.c
> >> index 322b272..30a3ff3 100644
> >> --- a/arch/arm/mach-exynos/mach-universal_c210.c
> >> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
> >> @@ -23,6 +23,7 @@
> >>  #include <linux/i2c-gpio.h>
> >>  #include <linux/i2c/mcs.h>
> >>  #include <linux/i2c/atmel_mxt_ts.h>
> >> +#include <drm/exynos_drm.h>
> >>
> >>  #include <asm/mach/arch.h>
> >>  #include <asm/hardware/gic.h>
> >> @@ -811,6 +812,27 @@ static struct i2c_board_info i2c1_devs[] __initdata =
> >> {
> >>  	/* Gyro, To be updated */
> >>  };
> >>
> >> +#ifdef CONFIG_DRM_EXYNOS
> >> +static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
> >> +	.timing	= {
> >> +		.left_margin	= 16,
> >> +		.right_margin	= 16,
> >> +		.upper_margin	= 2,
> >> +		.lower_margin	= 28,
> >> +		.hsync_len	= 2,
> >> +		.vsync_len	= 1,
> >> +		.xres		= 480,
> >> +		.yres		= 800,
> >> +		.refresh	= 55,
> >> +	},
> >
> > Shouldn't this be:
> Right, recently we added the panel information. It should be drm-next soon.

I'm sorry for the confusion, I've sent patches which were based on 3.3-rc5 without 
drm-next/fixes. I've just sent v2 patchset which reflects latest changes in drm-next/fixes
branches.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From paul at pwsan.com  Tue Mar 13 10:22:51 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 13 Mar 2012 08:22:51 -0600 (MDT)
Subject: [PATCH v2 0/2] Fixes in hwmod reset code
In-Reply-To: <1331647435-31666-1-git-send-email-rnayak@ti.com>
References: <1331647435-31666-1-git-send-email-rnayak@ti.com>
Message-ID: <alpine.DEB.2.00.1203130819480.22211@utopia.booyaka.com>

Hi Rajendra

On Tue, 13 Mar 2012, Rajendra Nayak wrote:

> This fixes a couple of issues around hwmod reset
> APIs'.
> Patches are based on 3.3.-rc7.
> 
> Rajendra Nayak (2):
>   ARM: omap: hwmod: Restore sysc after a reset
>   ARM: omap: hwmod: Make omap_hwmod_softreset wait for reset status
> 
>  arch/arm/mach-omap2/omap_hwmod.c |   18 ++++++------------
>  1 files changed, 6 insertions(+), 12 deletions(-)

Could you base this on either my 'hwmod_code_cleanup_3.4' branch or 
'hwmod_enable_remaining_hwmods_devel_3.4' branch?  There are some reset 
changes in there also.


- Paul


From arnd at arndb.de  Tue Mar 13 10:33:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 14:33:07 +0000
Subject: Conflict between Versatile Express DT conversion and local timer
 updates
In-Reply-To: <4F5F52A2.3050005@arm.com>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <201203131155.16454.arnd@arndb.de> <4F5F52A2.3050005@arm.com>
Message-ID: <201203131433.07214.arnd@arndb.de>

On Tuesday 13 March 2012, Marc Zyngier wrote:
> On 13/03/12 11:55, Arnd Bergmann wrote:
> > On Tuesday 13 March 2012, Marc Zyngier wrote:
> >> On 13/03/12 10:15, Russell King - ARM Linux wrote:

> > d) create a new next/timer branch in arm-soc that has Pawel's     
> >    98ed4ceb "ARM: vexpress: Get rid of MMIO_P2V" (the first patch from
> >    vexpress/dt, your patches and the ux500/timer series. Also put
> >    98ed4ceb into the next/cleanup branch.
> > 
> > Any of those will work for us, my preference would be on #4. I have
> > created the next/timer branch in the arm-soc tree, so you can use
> > that and either rebase your patches on top or merge your tree into
> > it and fix up the merge conflicts.
> 
> Thanks for doing that Arnd.
> 
> I've thus created a new branch:
> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> local_timers-for-arm-soc
> 
> which contains the arm-soc next/timers branch as well as my local timers
> series. I'd greatly appreciate if you could pull it for 3.4.
> 

I've updated the next/timer branch with your changes now, but did not
put it into the for-next branch because Olof is currently handling that.

Olof, can you add it to for-next please? The timer branch should have
no dependencies other than rmk/for-armsoc, so it can be fairly close to
the start.

	Arnd


From vinod.koul at intel.com  Tue Mar 13 10:38:54 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Tue, 13 Mar 2012 20:08:54 +0530
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <20120313123121.GA20133@n2100.arm.linux.org.uk>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <1331128466.24656.421.camel@vkoul-udesk3>
 <20120312161143.GA10830@n2100.arm.linux.org.uk>
 <1331569438.1727.3.camel@vkoul-udesk3>
 <1331628036.1727.22.camel@vkoul-udesk3>
 <20120313123121.GA20133@n2100.arm.linux.org.uk>
Message-ID: <1331649534.1727.27.camel@vkoul-udesk3>

On Tue, 2012-03-13 at 12:31 +0000, Russell King - ARM Linux wrote:
> On Tue, Mar 13, 2012 at 02:10:36PM +0530, Vinod Koul wrote:
> > Please see if the below patch is the right fix for build failures in
> > addition to one suggested by Jassi.
> 
> I'm not sure that Jassi's solution is correct - and I'm wondering whether
> any of the DMA engine drivers do the right thing when transfers are
> terminated.  Is it right for the DMA status function to return IN_PROGRESS
> for a previously submitted cookie which has been terminated?
> 
> I can see two answers to that, both equally valid:
> 
> 1. It allows you to find out exactly where the DMA engine got to before
>    the transfer was terminated, and therefore recover from the termination
>    if you wish to.
> 
> 2. Returning in-progress when a cookie will never be completed is
>    misleading, and could be misinterpreted by users of the tx_status
>    function, especially if they are waiting for a particular transaction
>    to complete.
> 
> Maybe we need to introduce a DMA_TERMINATED status?
I would agree with you that DMA_TERMINATED seems to be correct option.
IN_PROGRESS would certainly confuse... 
I will drop Jassi's fix from this branch. Care to send the patch?
> 
> > -------------------x-------------------------x----------------------
> > 
> > >From 949ff5b8d46b5e3435d21b2651ce3a2599208d44 Mon Sep 17 00:00:00 2001
> > From: Vinod Koul <vinod.koul at linux.intel.com>
> > Date: Tue, 13 Mar 2012 11:58:12 +0530
> > Subject: [PATCH] dmaengine: fix for cookie changes and merge
> > 
> > Fixed trivial issues in drivers:
> > 	drivers/dma/imx-sdma.c
> > 	drivers/dma/intel_mid_dma.c
> > 	drivers/dma/ioat/dma_v3.c
> > 	drivers/dma/iop-adma.c
> > 	drivers/dma/sirf-dma.c
> > 	drivers/dma/timb_dma.c
> > 
> > Signed-off-by: Vinod Koul <vinod.koul at linux.intel.com>
> > ---
> >  drivers/dma/imx-sdma.c      |    1 +
> >  drivers/dma/intel_mid_dma.c |    1 +
> >  drivers/dma/ioat/dma_v3.c   |    1 +
> >  drivers/dma/iop-adma.c      |    1 +
> >  drivers/dma/sirf-dma.c      |    2 ++
> >  drivers/dma/timb_dma.c      |    6 +-----
> >  6 files changed, 7 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> > index ccfc7c4..81f9d57 100644
> > --- a/drivers/dma/imx-sdma.c
> > +++ b/drivers/dma/imx-sdma.c
> > @@ -1127,6 +1127,7 @@ static void sdma_issue_pending(struct dma_chan *chan)
> >  	struct sdma_engine *sdma = sdmac->sdma;
> >  
> >  	if (sdmac->status == DMA_IN_PROGRESS)
> > +		sdma_enable_channel(sdma, sdmac->channel);
> >  }
> >  
> >  #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1	34
> 
> This looks like a merge conflict resolution.  I don't see this being
> caused by my patches as I haven't touched this function.
> 
> > diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
> > index d599d96..2449812 100644
> > --- a/drivers/dma/intel_mid_dma.c
> > +++ b/drivers/dma/intel_mid_dma.c
> > @@ -477,6 +477,7 @@ static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
> >  						dma_cookie_t cookie,
> >  						struct dma_tx_state *txstate)
> >  {
> > +	struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
> >  	enum dma_status ret;
> >  
> >  	ret = dma_cookie_status(chan, cookie, txstate);
> 
> Ditto (my patches don't introduce new this new midc, nor do they remove
> that line.)
> 
> > diff --git a/drivers/dma/ioat/dma_v3.c b/drivers/dma/ioat/dma_v3.c
> > index 145eda2..2c4476c 100644
> > --- a/drivers/dma/ioat/dma_v3.c
> > +++ b/drivers/dma/ioat/dma_v3.c
> > @@ -61,6 +61,7 @@
> >  #include <linux/dmaengine.h>
> >  #include <linux/dma-mapping.h>
> >  #include <linux/prefetch.h>
> > +#include "../dmaengine.h"
> >  #include "registers.h"
> >  #include "hw.h"
> >  #include "dma.h"
> > diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
> > index 1f3a703..4499f88 100644
> > --- a/drivers/dma/iop-adma.c
> > +++ b/drivers/dma/iop-adma.c
> > @@ -894,6 +894,7 @@ static enum dma_status iop_adma_status(struct dma_chan *chan,
> >  					struct dma_tx_state *txstate)
> >  {
> >  	struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
> > +	int ret;
> 
> This was "enum dma_status ret;" before I accidentally removed it.  It
> probably should be again, rather than an int.
> 
> >  
> >  	ret = dma_cookie_status(chan, cookie, txstate);
> >  	if (ret == DMA_SUCCESS)
> > diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
> > index a2cde85..45ba352 100644
> > --- a/drivers/dma/sirf-dma.c
> > +++ b/drivers/dma/sirf-dma.c
> > @@ -18,6 +18,8 @@
> >  #include <linux/of_platform.h>
> >  #include <linux/sirfsoc_dma.h>
> >  
> > +#include "dmaengine.h"
> > +
> >  #define SIRFSOC_DMA_DESCRIPTORS                 16
> >  #define SIRFSOC_DMA_CHANNELS                    16
> >  
> 
> Hmm, guess that's what happens when old patches are brought forward and
> things from the original series are forgotten...
> 
> > diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
> > index 7805996..d408c22 100644
> > --- a/drivers/dma/timb_dma.c
> > +++ b/drivers/dma/timb_dma.c
> > @@ -510,17 +510,13 @@ static void td_free_chan_resources(struct dma_chan *chan)
> >  static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
> >  				    struct dma_tx_state *txstate)
> >  {
> > -	struct timb_dma_chan *td_chan =
> > -		container_of(chan, struct timb_dma_chan, chan);
> >  	enum dma_status ret;
> >  
> >  	dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
> >  
> >  	ret = dma_cookie_status(chan, cookie, txstate);
> >  
> > -	dev_dbg(chan2dev(chan),
> > -		"%s: exit, ret: %d, last_complete: %d, last_used: %d\n",
> > -		__func__, ret, last_complete, last_used);
> > +	dev_dbg(chan2dev(chan), "%s: exit, ret: %d\n", 	__func__, ret);
> >  
> >  	return ret;
> >  }
> > -- 
> > 1.7.0.4
> > 
> > 
> > 
> > 
> > -- 
> > ~Vinod
> > 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


-- 
~Vinod



From florian at openwrt.org  Tue Mar 13 10:33:35 2012
From: florian at openwrt.org (Florian Fainelli)
Date: Tue, 13 Mar 2012 15:33:35 +0100
Subject: [PATCH 1/1] net: phylib: add error checking if no phy found
In-Reply-To: <1331636302-18256-1-git-send-email-b29396@freescale.com>
References: <1331636302-18256-1-git-send-email-b29396@freescale.com>
Message-ID: <4F5F5ABF.5030103@openwrt.org>

Hi,

Le 03/13/12 11:58, Dong Aisheng a ?crit :
> From: Dong Aisheng<dong.aisheng at linaro.org>
>
> Signed-off-by: Dong Aisheng<dong.aisheng at linaro.org>
> ---
>   drivers/net/phy/mdio_bus.c |   11 ++++++++++-
>   1 files changed, 10 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
> index 88cc5db..d8e044d 100644
> --- a/drivers/net/phy/mdio_bus.c
> +++ b/drivers/net/phy/mdio_bus.c
> @@ -101,6 +101,7 @@ static struct class mdio_bus_class = {
>   int mdiobus_register(struct mii_bus *bus)
>   {
>   	int i, err;
> +	u32 phynum = 0;
>
>   	if (NULL == bus || NULL == bus->name ||
>   			NULL == bus->read ||
> @@ -134,12 +135,20 @@ int mdiobus_register(struct mii_bus *bus)
>   			if (IS_ERR(phydev)) {
>   				err = PTR_ERR(phydev);
>   				goto error;
> +			} else if (phydev != NULL) {
> +				phynum++;
>   			}
>   		}
>   	}
>
> +	if (!phynum) {
> +		err = -ENODEV;
> +		printk(KERN_ERR "%s: no phys found\n", bus->name);
> +		goto error;
> +	}

I am not sure if this is a good idea to change it, especially if:
- the MII bus probing is also done later (quite some drivers do this)
- if we want to attach a fixed PHY because we could not probe one at 
registration time

> +
>   	bus->state = MDIOBUS_REGISTERED;
> -	pr_info("%s: probed\n", bus->name);
> +	pr_info("%s: %d phys probed\n", bus->name, phynum);
>   	return 0;
>
>   error:


From 21cnbao at gmail.com  Tue Mar 13 10:34:18 2012
From: 21cnbao at gmail.com (Barry Song)
Date: Tue, 13 Mar 2012 22:34:18 +0800
Subject: implementing "suspend to ram" on cortex A8 based on linux 3.0.8
In-Reply-To: <CAFawwkVuCTijwLr6UWVRh9XNGCt-8brr2f4aDrpM_YwkWSGP+A@mail.gmail.com>
References: <CAFawwkXQhyj+c8LEDnD7q4mXDJV2jYCAHV0tBrqxrEaNGk+_0w@mail.gmail.com>
 <CACNz9cVbULxVSGvo60V+JLL=15BDEaYwgd5k9ZMNu09Kfwz4WQ@mail.gmail.com>
 <CAFawwkWQd=y=kVm97UjSs37=-MRmJiy9f7sy8ChYzCHZ9Y-gyA@mail.gmail.com>
 <CAFawwkVuCTijwLr6UWVRh9XNGCt-8brr2f4aDrpM_YwkWSGP+A@mail.gmail.com>
Message-ID: <CAGsJ_4yDjDLSPwXubcecmCzpeJTwvGz30-awSAZfC+YtTwB_-w@mail.gmail.com>

hi yang,

? 2012?3?10? ??10:37?yang gqyang <hustgqyang at gmail.com> ???
> ?Thanks for your comment.
> ?Finally, i find out that i made a mistake. ?The uart(8250) have not been
> ?restore after resume, instead, it use the configuration got from boot. The
> ?uart have not been restored correctly, so that "ls" can not output result
> ?correctly resulting in it seems that the busybox can not work correctly.
> ?Now, i still have a question about the uart: why the "printk" can work
> ?correctly, but the "printf" not?
>
> ?Before this, i believe that the "printk" work correctly, then the uart
> ?work ok. but now, i ?need more reconsidaration about
> ?the relation between the "printk", "printf" and "uart".
> ?Can anyone give me some suggestion? Any comment is welcome, thanks a
> ?lot.

printk use "struct console" driver, it doesn't depend on a device node
for userspace.
printf actaully depends on uart_driver and a /dev/ttySx device node,
stdout and stderr are redirected to /dev/ttySx
uart is just a hardware which can be a tty or kernel console output.


>
>
-barry


From robherring2 at gmail.com  Tue Mar 13 10:35:43 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 09:35:43 -0500
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <1331628428-24017-2-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
Message-ID: <4F5F5B3F.2000303@gmail.com>

On 03/13/2012 03:47 AM, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> This patch includes basic dt support which can boot via nfs rootfs.
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
>  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
>  arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
>  arch/arm/boot/dts/imx28.dtsi                  |   88 +++++++++++++++++++++++++
>  arch/arm/mach-mxs/Kconfig                     |    9 +++
>  arch/arm/mach-mxs/Makefile                    |    1 +
>  arch/arm/mach-mxs/imx28-dt.c                  |   67 +++++++++++++++++++
>  6 files changed, 200 insertions(+), 0 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> index 54bddda..9f21faf 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -1,6 +1,10 @@
>  Freescale i.MX Platforms Device Tree Bindings
>  -----------------------------------------------
>  
> +i.MX28 Evaluation Kit
> +Required root node properties:
> +    - compatible = "fsl,imx28-evk", "fsl,imx28";
> +
>  i.MX51 Babbage Board
>  Required root node properties:
>      - compatible = "fsl,imx51-babbage", "fsl,imx51";
> diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
> new file mode 100644
> index 0000000..9758dc4
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx28-evk.dts
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "imx28.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX28 Evaluation Kit";
> +	compatible = "fsl,imx28-evk", "fsl,imx28";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x40000000 0x08000000>;
> +	};
> +
> +	ahb at 80080000 {
> +		fec at 800f0000 {

Use generic names: ethernet at 800f0000

> +			phy-mode = "rmii";
> +			local-mac-address = [00 04 9F 01 7D 5B];
> +			status = "okay";
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> new file mode 100644
> index 0000000..acf0dab
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -0,0 +1,88 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	interrupt-parent = <&icoll>;
> +
> +	aliases {
> +		serial0 = &uart1;
> +	};
> +
> +	cpus {
> +		cpu at 0 {
> +			compatible = "arm,arm926ejs";
> +		};
> +	};
> +
> +	apb at 80000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x80000000 0x80000>;
> +		ranges;
> +
> +		apbh at 80000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x80000000 0x3c900>;
> +			ranges;
> +
> +			icoll: interrupt-controller at 80000000 {
> +				compatible = "fsl,imx28-icoll";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +				reg = <0x80000000 0x2000>;
> +			};
> +		};
> +
> +		apbx at 80040000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x80040000 0x40000>;
> +			ranges;
> +
> +			uart1: uart at 80074000 {

Use generic names: uart1: serial at ...

> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x80074000 0x2000>;

This is really only 0x1000 in length.

> +				interrupts = <47>;
> +			};
> +		};
> +	};
> +
> +	ahb at 80080000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x80080000 0x80000>;
> +		ranges;
> +
> +		fec at 800f0000 {
> +			compatible = "fsl,imx28-fec";
> +			reg = <0x800f0000 0x4000>;

This too IIRC.

> +			interrupts = <101>;
> +			status = "disabled";
> +		};
> +
> +		fec at 800f4000 {
> +			compatible = "fsl,imx28-fec";
> +			reg = <0x800f4000 0x4000>;
> +			interrupts = <102>;
> +			status = "disabled";
> +		};
> +
> +	};
> +};
> diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
> index c57f996..6ab66af 100644
> --- a/arch/arm/mach-mxs/Kconfig
> +++ b/arch/arm/mach-mxs/Kconfig
> @@ -17,6 +17,15 @@ config SOC_IMX28
>  
>  comment "MXS platforms:"
>  
> +config MACH_IMX28_DT

Perhaps this should be more generic like MACH_MXS_DT to eventually
support MX23 as well?

> +	bool "Support i.MX28 platforms from device tree"
> +	select SOC_IMX28
> +	select USE_OF
> +	select MACH_MX28EVK

This should not be selected here.

> +	help
> +	  Include support for Freescale i.MX28 based platforms
> +	  using the device tree for discovery
> +
>  config MACH_STMP378X_DEVB
>  	bool "Support STMP378x_devb Platform"
>  	select SOC_IMX23
> diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
> index 908bf9a..25a4122 100644
> --- a/arch/arm/mach-mxs/Makefile
> +++ b/arch/arm/mach-mxs/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
>  obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
>  obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
>  
> +obj-$(CONFIG_MACH_IMX28_DT) += imx28-dt.o
>  obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
>  obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
>  obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
> diff --git a/arch/arm/mach-mxs/imx28-dt.c b/arch/arm/mach-mxs/imx28-dt.c
> new file mode 100644
> index 0000000..78d1129
> --- /dev/null
> +++ b/arch/arm/mach-mxs/imx28-dt.c
> @@ -0,0 +1,67 @@
> +/*
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.

It's 2012 now.

> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/init.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +#include <mach/common.h>
> +#include <mach/mx28.h>
> +
> +static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
> +	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
> +	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),

Why do you need the old names?

> +	{ /* sentinel */ }
> +};
> +
> +static void __init imx28_init(void)
> +{
> +	of_platform_populate(NULL, of_default_bus_match_table,
> +			     imx28_auxdata_lookup, NULL);
> +}
> +
> +static const struct of_device_id icoll_of_match[] __initconst = {
> +	{ .compatible = "fsl,imx28-icoll", },
> +	{},
> +};
> +
> +static void __init imx28_dt_init_irq(void)
> +{
> +	irq_domain_generate_simple(icoll_of_match, MX28_ICOLL_BASE_ADDR, 0);

Please do "proper" domain support for the interrupt controller and use
of_irq_init.

> +	mx28_init_irq();
> +}
> +
> +static void __init imx28_timer_init(void)
> +{
> +	mx28_clocks_init();
> +}
> +
> +static struct sys_timer imx28_timer = {
> +	.init = imx28_timer_init,
> +};
> +
> +static const char *imx28_dt_compat[] __initdata = {
> +	"fsl,imx28-evk",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
> +	.map_io		= mx28_map_io,
> +	.init_irq	= imx28_dt_init_irq,
> +	.timer		= &imx28_timer,
> +	.init_machine	= imx28_init,
> +	.dt_compat	= imx28_dt_compat,
> +	.restart	= mxs_restart,
> +MACHINE_END



From robherring2 at gmail.com  Tue Mar 13 10:39:30 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 09:39:30 -0500
Subject: [PATCH v1 3/5] ARM: imx28evk: add mmc dt support
In-Reply-To: <1331628428-24017-4-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-4-git-send-email-b29396@freescale.com>
Message-ID: <4F5F5C22.1080506@gmail.com>

On 03/13/2012 03:47 AM, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
>  arch/arm/boot/dts/imx28-evk.dts |   14 ++++++++++++++
>  arch/arm/boot/dts/imx28.dtsi    |   33 +++++++++++++++++++++++++++++++++
>  arch/arm/mach-mxs/imx28-dt.c    |    2 ++
>  3 files changed, 49 insertions(+), 0 deletions(-)

snip

> diff --git a/arch/arm/mach-mxs/imx28-dt.c b/arch/arm/mach-mxs/imx28-dt.c
> index 78d1129..429b88e 100644
> --- a/arch/arm/mach-mxs/imx28-dt.c
> +++ b/arch/arm/mach-mxs/imx28-dt.c
> @@ -23,6 +23,8 @@ static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
>  	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP0_BASE_ADDR, "mxs-mmc.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP1_BASE_ADDR, "mxs-mmc.1", NULL),

Why is this needed?

>  	{ /* sentinel */ }
>  };
>  



From sr at denx.de  Tue Mar 13 10:47:12 2012
From: sr at denx.de (Stefan Roese)
Date: Tue, 13 Mar 2012 15:47:12 +0100
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
Message-ID: <1331650032-15274-1-git-send-email-sr@denx.de>

This patch adds a generic target for SPEAr600 board that can be
configured via the device-tree. Currently only interrupts are
configured via device-tree. Other peripheral devices (e.g.
ethernet, I2C, SMI flash, FSMC NAND flash etc) will follow in
later patches.

Only the spear600-evb is currently supported. Other SPEAr600
based boards will follow later.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Viresh Kumar <viresh.kumar at st.com>
---
 Documentation/devicetree/bindings/arm/spear.txt |    6 ++
 arch/arm/boot/dts/spear600-evb.dts              |   23 +++++++
 arch/arm/boot/dts/spear600.dtsi                 |   49 +++++++++++++++
 arch/arm/mach-spear6xx/Kconfig                  |    7 +++
 arch/arm/mach-spear6xx/Makefile                 |    1 +
 arch/arm/mach-spear6xx/board-dt.c               |   75 +++++++++++++++++++++++
 6 files changed, 161 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
 create mode 100644 arch/arm/boot/dts/spear600-evb.dts
 create mode 100644 arch/arm/boot/dts/spear600.dtsi
 create mode 100644 arch/arm/mach-spear6xx/board-dt.c

diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
new file mode 100644
index 0000000..8e9f83e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -0,0 +1,6 @@
+ST SPEAr Platforms Device Tree Bindings
+---------------------------------------
+
+SPEAr600 EVB (Evaluation Board)
+Required root node properties:
+    - compatible = "st,spear600-evb";
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
new file mode 100644
index 0000000..f92d099
--- /dev/null
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear600.dtsi"
+
+/ {
+	model = "ST SPEAr600 Evaluation Board";
+	compatible = "st,spear600-evb";
+	#address-cells = <1>;
+	#size-cells = <1>;
+};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
new file mode 100644
index 0000000..82b086d
--- /dev/null
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0>; /* Filled by U-Boot */
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vic0: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		vic1: interrupt-controller at f1000000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+	};
+};
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
index ff4ae5b..7777f72 100644
--- a/arch/arm/mach-spear6xx/Kconfig
+++ b/arch/arm/mach-spear6xx/Kconfig
@@ -11,6 +11,13 @@ config BOARD_SPEAR600_EVB
 	help
 	  Supports ST SPEAr600 Evaluation Board
 
+config BOARD_SPEAR600_DT
+	bool "SPEAr600 generic board configured via device-tree"
+	select MACH_SPEAR600
+	select USE_OF
+	help
+	  Supports ST SPEAr600 boards configured via the device-tree
+
 endmenu
 
 config MACH_SPEAR600
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index cc1a4d8..e2d79b8 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_MACH_SPEAR600) += spear600.o
 
 # spear600 boards files
 obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
+obj-$(CONFIG_BOARD_SPEAR600_DT) += board-dt.o
diff --git a/arch/arm/mach-spear6xx/board-dt.c b/arch/arm/mach-spear6xx/board-dt.c
new file mode 100644
index 0000000..ee4ff33
--- /dev/null
+++ b/arch/arm/mach-spear6xx/board-dt.c
@@ -0,0 +1,75 @@
+/*
+ * arch/arm/mach-spear6xx/board-dt.c
+ *
+ * Generic SPEAr600 platform support
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar at st.com>
+ *
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+	&gpio_device[0],
+	&gpio_device[1],
+	&gpio_device[2],
+	&uart_device[0],
+	&uart_device[1],
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+};
+
+static void __init spear600_dt_init(void)
+{
+	unsigned int i;
+
+	/* call spear600 machine init function */
+	spear600_init();
+
+	/* Add Platform Devices */
+	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+	/* Add Amba Devices */
+	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+		amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+static const char *spear600_dt_board_compat[] = {
+	"st,spear600-evb",
+	NULL
+};
+
+static const struct of_device_id vic_of_match[] __initconst = {
+	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ /* Sentinel */ }
+};
+
+static void __init spear6xx_dt_init_irq(void)
+{
+	of_irq_init(vic_of_match);
+}
+
+DT_MACHINE_START(SPEAR600_DT, "ST-SPEAR600-DT")
+	.map_io		=	spear6xx_map_io,
+	.init_irq	=	spear6xx_dt_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear6xx_timer,
+	.init_machine	=	spear600_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear600_dt_board_compat,
+MACHINE_END
-- 
1.7.9.2



From vincent.sanders at collabora.co.uk  Tue Mar 13 10:34:17 2012
From: vincent.sanders at collabora.co.uk (Vincent Sanders)
Date: Tue, 13 Mar 2012 14:34:17 +0000
Subject: [PATCH] Improve build environment isolation
Message-ID: <20120313143417.GA5615@mail.collabora.co.uk>

Increasingly distributions are setting default build environments to
have LDFLAGS with hardening options. There seems to be an assumption
with those options that LDFLAGS are passed to the compiler frontend
rather than used directly with ld (which the kernel build process
assumes)

To prevent build failures in such environments this patch changes the
ARM architecture Makefile to override the LDFLAGS from the environment
similar to the behaviour on other common architectures e.g. x86

Signed-off-by: Vincent Sanders <vince at collabora.co.uk>
--

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1683bfb..0a05c44 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -10,6 +10,9 @@
 #
 # Copyright (C) 1995-2001 by Russell King
 
+# Ensure linker flags are correct
+LDFLAGS		:=
+
 LDFLAGS_vmlinux	:=-p --no-undefined -X
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux	+= --be8


From zsadecki at itwatchdogs.com  Tue Mar 13 10:59:39 2012
From: zsadecki at itwatchdogs.com (Zach Sadecki)
Date: Tue, 13 Mar 2012 09:59:39 -0500
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <4F5F5B3F.2000303@gmail.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <4F5F5B3F.2000303@gmail.com>
Message-ID: <4F5F60DB.9090801@itwatchdogs.com>

On 03/13/2012 09:35 AM, Rob Herring wrote:
> +	ahb at 80080000 {
> +		fec at 800f0000 {
> Use generic names: ethernet at 800f0000
Generic is good, but consistency is better, IMHO.  grepping existing dts 
files in 3.2.9 finds 6 instances of "fec@" and 0 instances of "ethernet@"
>> +			uart1: uart at 80074000 {
> Use generic names: uart1: serial at ...
Same comment here, but unfortunately there is already inconsistency in 
existing files...  25 instances of "serial@" and 35 instances of "uart@"



From marc.zyngier at arm.com  Tue Mar 13 11:00:26 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Tue, 13 Mar 2012 15:00:26 +0000
Subject: Conflict between Versatile Express DT conversion and local timer
 updates
In-Reply-To: <201203131433.07214.arnd@arndb.de>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <201203131155.16454.arnd@arndb.de> <4F5F52A2.3050005@arm.com>
 <201203131433.07214.arnd@arndb.de>
Message-ID: <4F5F610A.9050701@arm.com>

On 13/03/12 14:33, Arnd Bergmann wrote:
> On Tuesday 13 March 2012, Marc Zyngier wrote:
>> On 13/03/12 11:55, Arnd Bergmann wrote:
>>> On Tuesday 13 March 2012, Marc Zyngier wrote:
>>>> On 13/03/12 10:15, Russell King - ARM Linux wrote:
> 
>>> d) create a new next/timer branch in arm-soc that has Pawel's     
>>>    98ed4ceb "ARM: vexpress: Get rid of MMIO_P2V" (the first patch from
>>>    vexpress/dt, your patches and the ux500/timer series. Also put
>>>    98ed4ceb into the next/cleanup branch.
>>>
>>> Any of those will work for us, my preference would be on #4. I have
>>> created the next/timer branch in the arm-soc tree, so you can use
>>> that and either rebase your patches on top or merge your tree into
>>> it and fix up the merge conflicts.
>>
>> Thanks for doing that Arnd.
>>
>> I've thus created a new branch:
>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>> local_timers-for-arm-soc
>>
>> which contains the arm-soc next/timers branch as well as my local timers
>> series. I'd greatly appreciate if you could pull it for 3.4.
>>
> 
> I've updated the next/timer branch with your changes now, but did not
> put it into the for-next branch because Olof is currently handling that.
> 
> Olof, can you add it to for-next please? The timer branch should have
> no dependencies other than rmk/for-armsoc, so it can be fairly close to
> the start.

Thank you very much guys.

	M.
-- 
Jazz is not dead. It just smells funny...



From alexg at meprolight.com  Tue Mar 13 11:05:29 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Tue, 13 Mar 2012 17:05:29 +0200
Subject: [PATCH v1] i.MX35-PDK: Add Camera support
Message-ID: <1331651129-30540-1-git-send-email-alexg@meprolight.com>

In i.MX35-PDK, OV2640  camera is populated on the
personality board. This camera is registered as a subdevice via soc-camera interface.

Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
---
 arch/arm/mach-imx/mach-mx35_3ds.c |   96 +++++++++++++++++++++++++++++++++++++
 1 files changed, 96 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c..a7dd8e6 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -4,6 +4,11 @@
  *
  * Author: Fabio Estevam <fabio.estevam at freescale.com>
  *
+ * Copyright (C) 2011 Meprolight, Ltd.
+ * Alex Gershgorin <alexg at meprolight.com>
+ *
+ * Modified from i.MX31 3-Stack Development System
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -34,6 +39,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <asm/memblock.h>
 
 #include <mach/hardware.h>
 #include <mach/common.h>
@@ -41,6 +47,8 @@
 #include <mach/irqs.h>
 #include <mach/3ds_debugboard.h>
 
+#include <media/soc_camera.h>
+
 #include "devices-imx35.h"
 
 #define EXPIO_PARENT_INT	gpio_to_irq(IMX_GPIO_NR(1, 1))
@@ -120,6 +128,83 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
 	/* I2C1 */
 	MX35_PAD_I2C1_CLK__I2C1_SCL,
 	MX35_PAD_I2C1_DAT__I2C1_SDA,
+	/* CSI */
+	MX35_PAD_TX1__IPU_CSI_D_6,
+	MX35_PAD_TX0__IPU_CSI_D_7,
+	MX35_PAD_CSI_D8__IPU_CSI_D_8,
+	MX35_PAD_CSI_D9__IPU_CSI_D_9,
+	MX35_PAD_CSI_D10__IPU_CSI_D_10,
+	MX35_PAD_CSI_D11__IPU_CSI_D_11,
+	MX35_PAD_CSI_D12__IPU_CSI_D_12,
+	MX35_PAD_CSI_D13__IPU_CSI_D_13,
+	MX35_PAD_CSI_D14__IPU_CSI_D_14,
+	MX35_PAD_CSI_D15__IPU_CSI_D_15,
+	MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC,
+	MX35_PAD_CSI_MCLK__IPU_CSI_MCLK,
+	MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK,
+	MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC,
+};
+
+/*
+ * Camera support
+*/
+static phys_addr_t mx3_camera_base __initdata;
+#define MX35_3DS_CAMERA_BUF_SIZE SZ_8M
+
+static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = {
+	.flags = MX3_CAMERA_DATAWIDTH_8,
+	.mclk_10khz = 2000,
+};
+
+static int __init imx35_3ds_init_camera(void)
+{
+	int dma, ret = -ENOMEM;
+	struct platform_device *pdev =
+		imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata);
+
+	if (IS_ERR(pdev))
+		return PTR_ERR(pdev);
+
+	if (!mx3_camera_base)
+		goto err;
+
+	dma = dma_declare_coherent_memory(&pdev->dev,
+					mx3_camera_base, mx3_camera_base,
+					MX35_3DS_CAMERA_BUF_SIZE,
+					DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+
+	if (!(dma & DMA_MEMORY_MAP))
+		goto err;
+
+	ret = platform_device_add(pdev);
+	if (ret)
+err:
+		platform_device_put(pdev);
+
+	return ret;
+}
+
+static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = {
+	.irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct i2c_board_info mx35_3ds_i2c_camera = {
+	I2C_BOARD_INFO("ov2640", 0x30),
+};
+
+static struct soc_camera_link iclink_ov2640 = {
+	.bus_id		= 0,
+	.board_info	= &mx35_3ds_i2c_camera,
+	.i2c_adapter_id	= 0,
+	.power		= NULL,
+};
+
+static struct platform_device mx35_3ds_ov2640 = {
+	.name	= "soc-camera-pdrv",
+	.id	= 0,
+	.dev	= {
+		.platform_data = &iclink_ov2640,
+	},
 };
 
 static int mx35_3ds_otg_init(struct platform_device *pdev)
@@ -204,6 +289,9 @@ static void __init mx35_3ds_init(void)
 		pr_warn("Init of the debugboard failed, all "
 				"devices on the debugboard are unusable.\n");
 	imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+	imx35_add_ipu_core(&mx35_3ds_ipu_data);
+	platform_device_register(&mx35_3ds_ov2640);
+	imx35_3ds_init_camera();
 }
 
 static void __init mx35pdk_timer_init(void)
@@ -215,6 +303,13 @@ struct sys_timer mx35pdk_timer = {
 	.init	= mx35pdk_timer_init,
 };
 
+static void __init mx35_3ds_reserve(void)
+{
+	/* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
+	mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE,
+					 MX35_3DS_CAMERA_BUF_SIZE);
+}
+
 MACHINE_START(MX35_3DS, "Freescale MX35PDK")
 	/* Maintainer: Freescale Semiconductor, Inc */
 	.atag_offset = 0x100,
@@ -224,5 +319,6 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
 	.handle_irq = imx35_handle_irq,
 	.timer = &mx35pdk_timer,
 	.init_machine = mx35_3ds_init,
+	.reserve = mx35_3ds_reserve,
 	.restart	= mxc_restart,
 MACHINE_END
-- 
1.7.0.4



From prakash.pm at ti.com  Tue Mar 13 11:03:35 2012
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 13 Mar 2012 20:33:35 +0530
Subject: [PATCH] arm:da850: register musb device
Message-ID: <1331651015-32586-1-git-send-email-prakash.pm@ti.com>

Properly set up the OTG mode thru the CFGCHIP2 register, enable the
USB0_DRVVBUS pin, and finally register the MUSB platform device.

Signed-off-by: Ajay Kumar Gupta <ajay.gupta at ti.com>
Signed-off-by: Manjunathappa, Prakash <prakash.pm at ti.com>
---
Patche are on top below posted patches:
http://www.spinics.net/lists/linux-usb/msg59656.html

 arch/arm/mach-davinci/board-da850-evm.c |   12 ++++++++++++
 arch/arm/mach-davinci/usb.c             |    9 +++++++++
 2 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 178d178..539e12c 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -787,6 +787,18 @@ static __init void da850_evm_usb_init(void)
 	 */
 	cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX;
 	cfgchip2 |=  CFGCHIP2_USB2PHYCLKMUX;
+	/*
+	 * We have to override VBUS/ID signals when MUSB is configured into the
+	 * host-only mode -- ID pin will float if no cable is connected, so the
+	 * controller won't be able to drive VBUS thinking that it's a B-device.
+	 * Otherwise, we want to use the OTG mode and enable VBUS comparators.
+	 */
+	cfgchip2 &= ~CFGCHIP2_OTGMODE;
+#if CONFIG_USB_MUSB_DA8XX
+	cfgchip2 |=  CFGCHIP2_FORCE_HOST;
+#else
+	cfgchip2 |=  CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
+#endif
 
 	__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
 
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 25c3520..a941dc5 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -284,6 +284,15 @@ void __init da8xx_board_usb_init(const short pins[],
 		goto usb11_setup_fail;
 	}
 
+	/*
+	 * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A),
+	 * with the power on to power good time of 3 ms.
+	 */
+	ret = da8xx_register_usb20(1000, 3);
+	if (ret)
+		pr_warning("%s: USB 2.0 registration failed: %d\n",
+			   __func__, ret);
+
 	return;
 
 usb11_setup_fail:
-- 
1.7.1



From kgene.kim at samsung.com  Tue Mar 13 11:30:32 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:32 -0700
Subject: [PATCH v3 01/12] ARM: EXYNOS: to declare static for
 mach-exynos/common.c
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-2-git-send-email-kgene.kim@samsung.com>

According to commit cc511b8d84d8 ("ARM: 7257/1: EXYNOS: introduce
arch/arm/mach-exynos/common.[ch]"), we don't need to declare extern
for exynos4_map_io(), exynos4_init_clocks(), exynos4_init_uarts(),
and exynos_init(). And the exynos4210_register_clocks() and
exynos4212_register_clocks depend on each SoC not ARCH_EXYNOS4.
So this patch fixed above.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/common.c |   13 +++++++++----
 arch/arm/mach-exynos/common.h |   28 +++++++++++-----------------
 2 files changed, 20 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 34e8190..a1f8a99 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -50,6 +50,11 @@ static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
 
+static void exynos4_map_io(void);
+static void exynos4_init_clocks(int xtal);
+static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+static int exynos_init(void);
+
 static struct cpu_table cpu_ids[] __initdata = {
 	{
 		.idcode		= EXYNOS4210_CPU_ID,
@@ -225,7 +230,7 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
 	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
 
-void __init exynos4_map_io(void)
+static void __init exynos4_map_io(void)
 {
 	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 
@@ -256,7 +261,7 @@ void __init exynos4_map_io(void)
 	s5p_hdmi_setname("exynos4-hdmi");
 }
 
-void __init exynos4_init_clocks(int xtal)
+static void __init exynos4_init_clocks(int xtal)
 {
 	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 
@@ -456,7 +461,7 @@ static int __init exynos4_l2x0_cache_init(void)
 early_initcall(exynos4_l2x0_cache_init);
 #endif
 
-int __init exynos_init(void)
+static int __init exynos_init(void)
 {
 	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 	return device_register(&exynos4_dev);
@@ -464,7 +469,7 @@ int __init exynos_init(void)
 
 /* uart registration process */
 
-void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
 	struct s3c2410_uartcfg *tcfg = cfg;
 	u32 ucnt;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 8c1efe6..b32c6b5 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,39 +12,33 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+extern struct sys_timer exynos4_timer;
+
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
+void exynos4_restart(char mode, const char *cmd);
 
 #ifdef CONFIG_ARCH_EXYNOS4
 void exynos4_register_clocks(void);
 void exynos4_setup_clocks(void);
 
-void exynos4210_register_clocks(void);
-void exynos4212_register_clocks(void);
-
 #else
 #define exynos4_register_clocks()
 #define exynos4_setup_clocks()
-
-#define exynos4210_register_clocks()
-#define exynos4212_register_clocks()
 #endif
 
-void exynos4_restart(char mode, const char *cmd);
+#ifdef CONFIG_CPU_EXYNOS4210
+void exynos4210_register_clocks(void);
 
-extern struct sys_timer exynos4_timer;
+#else
+#define exynos4210_register_clocks()
+#endif
 
-#ifdef CONFIG_ARCH_EXYNOS
-extern  int exynos_init(void);
-extern void exynos4_map_io(void);
-extern void exynos4_init_clocks(int xtal);
-extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#ifdef CONFIG_SOC_EXYNOS4212
+void exynos4212_register_clocks(void);
 
 #else
-#define exynos4_init_clocks NULL
-#define exynos4_init_uarts NULL
-#define exynos4_map_io NULL
-#define exynos_init NULL
+#define exynos4212_register_clocks()
 #endif
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
-- 
1.7.4.4



From kgene.kim at samsung.com  Tue Mar 13 11:30:34 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:34 -0700
Subject: [PATCH v3 03/12] ARM: EXYNOS: add clock part for EXYNOS5250 SoC
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-4-git-send-email-kgene.kim@samsung.com>

This patch adds clock-exynos5.c for EXYNOS5250 now
and that can be used for other EXYNOS5 SoCs later.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/clock-exynos5.c           | 1247 ++++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/regs-clock.h |   62 ++
 arch/arm/plat-s5p/clock.c                      |   36 +
 arch/arm/plat-samsung/include/plat/s5p-clock.h |    6 +
 4 files changed, 1351 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/clock-exynos5.c

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644
index 0000000..d013982
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -0,0 +1,1247 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Clock support for EXYNOS5 SoCs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+
+#include "common.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos5_clock_save[] = {
+	/* will be implemented */
+};
+#endif
+
+static struct clk exynos5_clk_sclk_dptxphy = {
+	.name		= "sclk_dptx",
+};
+
+static struct clk exynos5_clk_sclk_hdmi24m = {
+	.name		= "sclk_hdmi24m",
+	.rate		= 24000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmi27m = {
+	.name		= "sclk_hdmi27m",
+	.rate		= 27000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmiphy = {
+	.name		= "sclk_hdmiphy",
+};
+
+static struct clk exynos5_clk_sclk_usbphy = {
+	.name		= "sclk_usbphy",
+	.rate		= 48000000,
+};
+
+static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
+}
+
+static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
+}
+
+static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
+}
+
+static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
+}
+
+static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
+}
+
+static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
+}
+
+static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
+}
+
+static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
+}
+
+static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
+}
+
+static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos5_clk_mout_apll = {
+	.clk	= {
+		.name		= "mout_apll",
+	},
+	.sources = &clk_src_apll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_apll = {
+	.clk	= {
+		.name		= "sclk_apll",
+		.parent		= &exynos5_clk_mout_apll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll = {
+	.clk	= {
+		.name		= "mout_bpll",
+	},
+	.sources = &clk_src_bpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_user_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll_user = {
+	.sources	= exynos5_clk_src_bpll_user_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_user = {
+	.clk	= {
+		.name		= "mout_bpll_user",
+	},
+	.sources = &exynos5_clk_src_bpll_user,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpll = {
+	.clk	= {
+		.name		= "mout_cpll",
+	},
+	.sources = &clk_src_cpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_epll = {
+	.clk	= {
+		.name		= "mout_epll",
+	},
+	.sources = &clk_src_epll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
+};
+
+struct clksrc_clk exynos5_clk_mout_mpll = {
+	.clk = {
+		.name		= "mout_mpll",
+	},
+	.sources = &clk_src_mpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
+};
+
+static struct clk *exynos_clkset_vpllsrc_list[] = {
+	[0] = &clk_fin_vpll,
+	[1] = &exynos5_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos5_clkset_vpllsrc = {
+	.sources	= exynos_clkset_vpllsrc_list,
+	.nr_sources	= ARRAY_SIZE(exynos_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos5_clk_vpllsrc = {
+	.clk	= {
+		.name		= "vpll_src",
+		.enable		= exynos5_clksrc_mask_top_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos5_clkset_vpllsrc,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_sclk_vpll_list[] = {
+	[0] = &exynos5_clk_vpllsrc.clk,
+	[1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_vpll = {
+	.sources	= exynos5_clkset_sclk_vpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_vpll = {
+	.clk	= {
+		.name		= "sclk_vpll",
+	},
+	.sources = &exynos5_clkset_sclk_vpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_pixel = {
+	.clk	= {
+		.name		= "sclk_pixel",
+		.parent		= &exynos5_clk_sclk_vpll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
+	[0] = &exynos5_clk_sclk_pixel.clk,
+	[1] = &exynos5_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
+	.sources	= exynos5_clkset_sclk_hdmi_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_hdmi = {
+	.clk	= {
+		.name		= "sclk_hdmi",
+		.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
+		.ctrlbit	= (1 << 20),
+	},
+	.sources = &exynos5_clkset_sclk_hdmi,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk *exynos5_sclk_tv[] = {
+	&exynos5_clk_sclk_pixel,
+	&exynos5_clk_sclk_hdmi,
+};
+
+static struct clk *exynos5_clk_src_mpll_user_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll_user = {
+	.sources	= exynos5_clk_src_mpll_user_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_user = {
+	.clk	= {
+		.name		= "mout_mpll_user",
+	},
+	.sources = &exynos5_clk_src_mpll_user,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_mout_cpu_list[] = {
+	[0] = &exynos5_clk_mout_apll.clk,
+	[1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_cpu = {
+	.sources	= exynos5_clkset_mout_cpu_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpu = {
+	.clk	= {
+		.name		= "mout_cpu",
+	},
+	.sources = &exynos5_clkset_mout_cpu,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_armclk = {
+	.clk	= {
+		.name		= "dout_armclk",
+		.parent		= &exynos5_clk_mout_cpu.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_arm2clk = {
+	.clk	= {
+		.name		= "dout_arm2clk",
+		.parent		= &exynos5_clk_dout_armclk.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
+};
+
+static struct clk exynos5_clk_armclk = {
+	.name		= "armclk",
+	.parent		= &exynos5_clk_dout_arm2clk.clk,
+};
+
+/* Core list of CMU_CDREX side */
+
+static struct clk *exynos5_clkset_cdrex_list[] = {
+	[0] = &exynos5_clk_mout_mpll.clk,
+	[1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_cdrex = {
+	.sources	= exynos5_clkset_cdrex_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_cdrex_list),
+};
+
+static struct clksrc_clk exynos5_clk_cdrex = {
+	.clk	= {
+		.name		= "clk_cdrex",
+	},
+	.sources = &exynos5_clkset_cdrex,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_acp = {
+	.clk	= {
+		.name		= "aclk_acp",
+		.parent		= &exynos5_clk_mout_mpll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_pclk_acp = {
+	.clk	= {
+		.name		= "pclk_acp",
+		.parent		= &exynos5_clk_aclk_acp.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos5_clkset_aclk_top_list[] = {
+	[0] = &exynos5_clk_mout_mpll_user.clk,
+	[1] = &exynos5_clk_mout_bpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk = {
+	.sources	= exynos5_clkset_aclk_top_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400 = {
+	.clk	= {
+		.name		= "aclk_400",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+};
+
+struct clk *exynos5_clkset_aclk_333_166_list[] = {
+	[0] = &exynos5_clk_mout_cpll.clk,
+	[1] = &exynos5_clk_mout_mpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_333_166 = {
+	.sources	= exynos5_clkset_aclk_333_166_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_333 = {
+	.clk	= {
+		.name		= "aclk_333",
+	},
+	.sources = &exynos5_clkset_aclk_333_166,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_166 = {
+	.clk	= {
+		.name		= "aclk_166",
+	},
+	.sources = &exynos5_clkset_aclk_333_166,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266 = {
+	.clk	= {
+		.name		= "aclk_266",
+		.parent		= &exynos5_clk_mout_mpll_user.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_200 = {
+	.clk	= {
+		.name		= "aclk_200",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66_pre = {
+	.clk	= {
+		.name		= "aclk_66_pre",
+		.parent		= &exynos5_clk_mout_mpll_user.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66 = {
+	.clk	= {
+		.name		= "aclk_66",
+		.parent		= &exynos5_clk_aclk_66_pre.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
+};
+
+static struct clk exynos5_init_clocks_off[] = {
+	{
+		.name		= "timers",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= "rtc",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peris_ctrl,
+		.ctrlbit	= (1 << 20),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.0",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.1",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.2",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.3",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "dwmci",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "sata",
+		.devname	= "ahci",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "sata_phy",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= "sata_phy_i2c",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 25),
+	}, {
+		.name		= "mfc",
+		.devname	= "s5p-mfc",
+		.enable		= exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "hdmi",
+		.devname	= "exynos4-hdmi",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "mixer",
+		.devname	= "s5p-mixer",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "jpeg",
+		.enable		= exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "dsim0",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 20),
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 21),
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 22),
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 23),
+	}, {
+		.name		= "spdif",
+		.devname	= "samsung-spdif",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 26),
+	}, {
+		.name		= "ac97",
+		.devname	= "samsung-ac97",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 27),
+	}, {
+		.name		= "usbhost",
+		.enable		= exynos5_clk_ip_fsys_ctrl ,
+		.ctrlbit	= (1 << 18),
+	}, {
+		.name		= "usbotg",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "gps",
+		.enable		= exynos5_clk_ip_gps_ctrl,
+		.ctrlbit	= ((1 << 3) | (1 << 2) | (1 << 0)),
+	}, {
+		.name		= "nfcon",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 22),
+	}, {
+		.name		= "iop",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= ((1 << 30) | (1 << 26) | (1 << 23)),
+	}, {
+		.name		= "core_iop",
+		.enable		= exynos5_clk_ip_core_ctrl,
+		.ctrlbit	= ((1 << 21) | (1 << 3)),
+	}, {
+		.name		= "mcu_iop",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.0",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.1",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.2",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.3",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.4",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.5",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.6",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.7",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-hdmiphy-i2c",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 14),
+	}
+};
+
+static struct clk exynos5_init_clocks_on[] = {
+	{
+		.name		= "uart",
+		.devname	= "s5pv210-uart.0",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.3",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.4",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.5",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 5),
+	}
+};
+
+static struct clk exynos5_clk_pdma0 = {
+	.name		= "dma",
+	.devname	= "dma-pl330.0",
+	.enable		= exynos5_clk_ip_fsys_ctrl,
+	.ctrlbit	= (1 << 1),
+};
+
+static struct clk exynos5_clk_pdma1 = {
+	.name		= "dma",
+	.devname	= "dma-pl330.1",
+	.enable		= exynos5_clk_ip_fsys_ctrl,
+	.ctrlbit	= (1 << 1),
+};
+
+static struct clk exynos5_clk_mdma1 = {
+	.name		= "dma",
+	.devname	= "dma-pl330.2",
+	.enable		= exynos5_clk_ip_gen_ctrl,
+	.ctrlbit	= (1 << 4),
+};
+
+struct clk *exynos5_clkset_group_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = NULL,
+	[2] = &exynos5_clk_sclk_hdmi24m,
+	[3] = &exynos5_clk_sclk_dptxphy,
+	[4] = &exynos5_clk_sclk_usbphy,
+	[5] = &exynos5_clk_sclk_hdmiphy,
+	[6] = &exynos5_clk_mout_mpll_user.clk,
+	[7] = &exynos5_clk_mout_epll.clk,
+	[8] = &exynos5_clk_sclk_vpll.clk,
+	[9] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_group = {
+	.sources	= exynos5_clkset_group_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_group_list),
+};
+
+/* Possible clock sources for aclk_266_gscl_sub Mux */
+static struct clk *clk_src_gscl_266_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = &exynos5_clk_aclk_266.clk,
+};
+
+static struct clksrc_sources clk_src_gscl_266 = {
+	.sources	= clk_src_gscl_266_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_gscl_266_list),
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc0 = {
+	.clk		= {
+		.name		= "dout_mmc0",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc1 = {
+	.clk		= {
+		.name		= "dout_mmc1",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc2 = {
+	.clk		= {
+		.name		= "dout_mmc2",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc3 = {
+	.clk		= {
+		.name		= "dout_mmc3",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc4 = {
+	.clk		= {
+		.name		= "dout_mmc4",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart0 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.0",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart1 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.1",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 4),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart2 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.2",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 8),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart3 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.3",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 12),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.0",
+		.parent		= &exynos5_clk_dout_mmc0.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.1",
+		.parent		= &exynos5_clk_dout_mmc1.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 4),
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.2",
+		.parent		= &exynos5_clk_dout_mmc2.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 8),
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.3",
+		.parent		= &exynos5_clk_dout_mmc3.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 12),
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clksrcs[] = {
+	{
+		.clk	= {
+			.name		= "sclk_dwmci",
+			.parent		= &exynos5_clk_dout_mmc4.clk,
+			.enable		= exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimd",
+			.devname	= "s3cfb.1",
+			.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "aclk_266_gscl",
+		},
+		.sources = &clk_src_gscl_266,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
+	}, {
+		.clk	= {
+			.name		= "sclk_g3d",
+			.devname	= "mali-t604.0",
+			.enable		= exynos5_clk_block_ctrl,
+			.ctrlbit	= (1 << 1),
+		},
+		.sources = &exynos5_clkset_aclk,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+	}, {
+		.clk	= {
+			.name		= "sclk_gscl_wrap",
+			.devname	= "s5p-mipi-csis.0",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_gscl_wrap",
+			.devname	= "s5p-mipi-csis.1",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 28),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_cam0",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_cam1",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 20),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_jpeg",
+			.parent		= &exynos5_clk_mout_cpll.clk,
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+	},
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos5_sysclks[] = {
+	&exynos5_clk_mout_apll,
+	&exynos5_clk_sclk_apll,
+	&exynos5_clk_mout_bpll,
+	&exynos5_clk_mout_bpll_user,
+	&exynos5_clk_mout_cpll,
+	&exynos5_clk_mout_epll,
+	&exynos5_clk_mout_mpll,
+	&exynos5_clk_mout_mpll_user,
+	&exynos5_clk_vpllsrc,
+	&exynos5_clk_sclk_vpll,
+	&exynos5_clk_mout_cpu,
+	&exynos5_clk_dout_armclk,
+	&exynos5_clk_dout_arm2clk,
+	&exynos5_clk_cdrex,
+	&exynos5_clk_aclk_400,
+	&exynos5_clk_aclk_333,
+	&exynos5_clk_aclk_266,
+	&exynos5_clk_aclk_200,
+	&exynos5_clk_aclk_166,
+	&exynos5_clk_aclk_66_pre,
+	&exynos5_clk_aclk_66,
+	&exynos5_clk_dout_mmc0,
+	&exynos5_clk_dout_mmc1,
+	&exynos5_clk_dout_mmc2,
+	&exynos5_clk_dout_mmc3,
+	&exynos5_clk_dout_mmc4,
+	&exynos5_clk_aclk_acp,
+	&exynos5_clk_pclk_acp,
+};
+
+static struct clk *exynos5_clk_cdev[] = {
+	&exynos5_clk_pdma0,
+	&exynos5_clk_pdma1,
+	&exynos5_clk_mdma1,
+};
+
+static struct clksrc_clk *exynos5_clksrc_cdev[] = {
+	&exynos5_clk_sclk_uart0,
+	&exynos5_clk_sclk_uart1,
+	&exynos5_clk_sclk_uart2,
+	&exynos5_clk_sclk_uart3,
+	&exynos5_clk_sclk_mmc0,
+	&exynos5_clk_sclk_mmc1,
+	&exynos5_clk_sclk_mmc2,
+	&exynos5_clk_sclk_mmc3,
+};
+
+static struct clk_lookup exynos5_clk_lookup[] = {
+	CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
+	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
+	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
+	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
+	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
+	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
+	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
+	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
+	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
+	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+};
+
+static unsigned long exynos5_epll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static struct clk *exynos5_clks[] __initdata = {
+	&exynos5_clk_sclk_hdmi27m,
+	&exynos5_clk_sclk_hdmiphy,
+	&clk_fout_bpll,
+	&clk_fout_cpll,
+	&exynos5_clk_armclk,
+};
+
+static u32 epll_div[][6] = {
+	{ 192000000, 0, 48, 3, 1, 0 },
+	{ 180000000, 0, 45, 3, 1, 0 },
+	{  73728000, 1, 73, 3, 3, 47710 },
+	{  67737600, 1, 90, 4, 3, 20762 },
+	{  49152000, 0, 49, 3, 3, 9961 },
+	{  45158400, 0, 45, 3, 3, 10381 },
+	{ 180633600, 0, 45, 3, 1, 10381 },
+};
+
+static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int epll_con, epll_con_k;
+	unsigned int i;
+	unsigned int tmp;
+	unsigned int epll_rate;
+	unsigned int locktime;
+	unsigned int lockcnt;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	if (clk->parent)
+		epll_rate = clk_get_rate(clk->parent);
+	else
+		epll_rate = clk_ext_xtal_mux.rate;
+
+	if (epll_rate != 24000000) {
+		pr_err("Invalid Clock : recommended clock is 24MHz.\n");
+		return -EINVAL;
+	}
+
+	epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
+	epll_con &= ~(0x1 << 27 | \
+			PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
+			PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+			PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+		if (epll_div[i][0] == rate) {
+			epll_con_k = epll_div[i][5] << 0;
+			epll_con |= epll_div[i][1] << 27;
+			epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
+			epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
+			epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(epll_div)) {
+		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	epll_rate /= 1000000;
+
+	/* 3000 max_cycls : specification data */
+	locktime = 3000 / epll_rate * epll_div[i][3];
+	lockcnt = locktime * 10000 / (10000 / epll_rate);
+
+	__raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
+
+	__raw_writel(epll_con, EXYNOS5_EPLL_CON0);
+	__raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_EPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+static struct clk_ops exynos5_epll_ops = {
+	.get_rate = exynos5_epll_get_rate,
+	.set_rate = exynos5_epll_set_rate,
+};
+
+static int xtal_rate;
+
+static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
+{
+	return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
+}
+
+static struct clk_ops exynos5_fout_apll_ops = {
+	.get_rate = exynos5_fout_apll_get_rate,
+};
+
+#ifdef CONFIG_PM
+static int exynos5_clock_suspend(void)
+{
+	s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+
+	return 0;
+}
+
+static void exynos5_clock_resume(void)
+{
+	s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+}
+#else
+#define exynos5_clock_suspend NULL
+#define exynos5_clock_resume NULL
+#endif
+
+struct syscore_ops exynos5_clock_syscore_ops = {
+	.suspend	= exynos5_clock_suspend,
+	.resume		= exynos5_clock_resume,
+};
+
+void __init_or_cpufreq exynos5_setup_clocks(void)
+{
+	struct clk *xtal_clk;
+	unsigned long apll;
+	unsigned long bpll;
+	unsigned long cpll;
+	unsigned long mpll;
+	unsigned long epll;
+	unsigned long vpll;
+	unsigned long vpllsrc;
+	unsigned long xtal;
+	unsigned long armclk;
+	unsigned long mout_cdrex;
+	unsigned long aclk_400;
+	unsigned long aclk_333;
+	unsigned long aclk_266;
+	unsigned long aclk_200;
+	unsigned long aclk_166;
+	unsigned long aclk_66;
+	unsigned int ptr;
+
+	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+	xtal_clk = clk_get(NULL, "xtal");
+	BUG_ON(IS_ERR(xtal_clk));
+
+	xtal = clk_get_rate(xtal_clk);
+
+	xtal_rate = xtal;
+
+	clk_put(xtal_clk);
+
+	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+	apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
+	bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
+	cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
+	mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
+	epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
+			__raw_readl(EXYNOS5_EPLL_CON1));
+
+	vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
+	vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
+			__raw_readl(EXYNOS5_VPLL_CON1));
+
+	clk_fout_apll.ops = &exynos5_fout_apll_ops;
+	clk_fout_bpll.rate = bpll;
+	clk_fout_cpll.rate = cpll;
+	clk_fout_mpll.rate = mpll;
+	clk_fout_epll.rate = epll;
+	clk_fout_vpll.rate = vpll;
+
+	printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
+			"M=%ld, E=%ld V=%ld",
+			apll, bpll, cpll, mpll, epll, vpll);
+
+	armclk = clk_get_rate(&exynos5_clk_armclk);
+	mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
+
+	aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
+	aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
+	aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
+	aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
+	aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
+	aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
+
+	printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
+			"ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
+			"ACLK166=%ld, ACLK66=%ld\n",
+			armclk, mout_cdrex, aclk_400,
+			aclk_333, aclk_266, aclk_200,
+			aclk_166, aclk_66);
+
+
+	clk_fout_epll.ops = &exynos5_epll_ops;
+
+	if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
+
+	clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
+	clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
+
+	clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
+	clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
+		s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
+}
+
+void __init exynos5_register_clocks(void)
+{
+	int ptr;
+
+	s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
+		s3c_register_clksrc(exynos5_sysclks[ptr], 1);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
+		s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
+		s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
+
+	s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
+	s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
+
+	s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
+		s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
+
+	s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+	s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+	clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
+
+	register_syscore_ops(&exynos5_clock_syscore_ops);
+	s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 1e4abd6..e141c1f 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -253,6 +253,68 @@
 #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT		(0)
 #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK		(0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
 
+/* For EXYNOS5250 */
+
+#define EXYNOS5_APLL_CON0			EXYNOS_CLKREG(0x00100)
+#define EXYNOS5_CLKSRC_CPU			EXYNOS_CLKREG(0x00200)
+#define EXYNOS5_CLKDIV_CPU0			EXYNOS_CLKREG(0x00500)
+#define EXYNOS5_MPLL_CON0			EXYNOS_CLKREG(0x04100)
+#define EXYNOS5_CLKSRC_CORE1			EXYNOS_CLKREG(0x04204)
+
+#define EXYNOS5_CLKGATE_IP_CORE			EXYNOS_CLKREG(0x04900)
+
+#define EXYNOS5_CLKDIV_ACP			EXYNOS_CLKREG(0x08500)
+
+#define EXYNOS5_CLKSRC_TOP2			EXYNOS_CLKREG(0x10218)
+#define EXYNOS5_EPLL_CON0			EXYNOS_CLKREG(0x10130)
+#define EXYNOS5_EPLL_CON1			EXYNOS_CLKREG(0x10134)
+#define EXYNOS5_VPLL_CON0			EXYNOS_CLKREG(0x10140)
+#define EXYNOS5_VPLL_CON1			EXYNOS_CLKREG(0x10144)
+#define EXYNOS5_CPLL_CON0			EXYNOS_CLKREG(0x10120)
+
+#define EXYNOS5_CLKSRC_TOP0			EXYNOS_CLKREG(0x10210)
+#define EXYNOS5_CLKSRC_TOP3			EXYNOS_CLKREG(0x1021C)
+#define EXYNOS5_CLKSRC_GSCL			EXYNOS_CLKREG(0x10220)
+#define EXYNOS5_CLKSRC_DISP1_0			EXYNOS_CLKREG(0x1022C)
+#define EXYNOS5_CLKSRC_FSYS			EXYNOS_CLKREG(0x10244)
+#define EXYNOS5_CLKSRC_PERIC0			EXYNOS_CLKREG(0x10250)
+
+#define EXYNOS5_CLKSRC_MASK_TOP			EXYNOS_CLKREG(0x10310)
+#define EXYNOS5_CLKSRC_MASK_GSCL		EXYNOS_CLKREG(0x10320)
+#define EXYNOS5_CLKSRC_MASK_DISP1_0		EXYNOS_CLKREG(0x1032C)
+#define EXYNOS5_CLKSRC_MASK_FSYS		EXYNOS_CLKREG(0x10340)
+#define EXYNOS5_CLKSRC_MASK_PERIC0		EXYNOS_CLKREG(0x10350)
+
+#define EXYNOS5_CLKDIV_TOP0			EXYNOS_CLKREG(0x10510)
+#define EXYNOS5_CLKDIV_TOP1			EXYNOS_CLKREG(0x10514)
+#define EXYNOS5_CLKDIV_GSCL			EXYNOS_CLKREG(0x10520)
+#define EXYNOS5_CLKDIV_DISP1_0			EXYNOS_CLKREG(0x1052C)
+#define EXYNOS5_CLKDIV_GEN			EXYNOS_CLKREG(0x1053C)
+#define EXYNOS5_CLKDIV_FSYS0			EXYNOS_CLKREG(0x10548)
+#define EXYNOS5_CLKDIV_FSYS1			EXYNOS_CLKREG(0x1054C)
+#define EXYNOS5_CLKDIV_FSYS2			EXYNOS_CLKREG(0x10550)
+#define EXYNOS5_CLKDIV_FSYS3			EXYNOS_CLKREG(0x10554)
+#define EXYNOS5_CLKDIV_PERIC0			EXYNOS_CLKREG(0x10558)
+
+#define EXYNOS5_CLKGATE_IP_ACP			EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_GSCL			EXYNOS_CLKREG(0x10920)
+#define EXYNOS5_CLKGATE_IP_DISP1		EXYNOS_CLKREG(0x10928)
+#define EXYNOS5_CLKGATE_IP_MFC			EXYNOS_CLKREG(0x1092C)
+#define EXYNOS5_CLKGATE_IP_GEN			EXYNOS_CLKREG(0x10934)
+#define EXYNOS5_CLKGATE_IP_FSYS			EXYNOS_CLKREG(0x10944)
+#define EXYNOS5_CLKGATE_IP_GPS			EXYNOS_CLKREG(0x1094C)
+#define EXYNOS5_CLKGATE_IP_PERIC		EXYNOS_CLKREG(0x10950)
+#define EXYNOS5_CLKGATE_IP_PERIS		EXYNOS_CLKREG(0x10960)
+#define EXYNOS5_CLKGATE_BLOCK			EXYNOS_CLKREG(0x10980)
+
+#define EXYNOS5_BPLL_CON0			EXYNOS_CLKREG(0x20110)
+#define EXYNOS5_CLKSRC_CDREX			EXYNOS_CLKREG(0x20200)
+#define EXYNOS5_CLKDIV_CDREX			EXYNOS_CLKREG(0x20500)
+
+#define EXYNOS5_EPLL_LOCK			EXYNOS_CLKREG(0x10030)
+
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT		(29)
+
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 963edea..f68a9bb 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -61,6 +61,20 @@ struct clk clk_fout_apll = {
 	.id		= -1,
 };
 
+/* BPLL clock output */
+
+struct clk clk_fout_bpll = {
+	.name		= "fout_bpll",
+	.id		= -1,
+};
+
+/* CPLL clock output */
+
+struct clk clk_fout_cpll = {
+	.name		= "fout_cpll",
+	.id		= -1,
+};
+
 /* MPLL clock output
  * No need .ctrlbit, this is always on
 */
@@ -101,6 +115,28 @@ struct clksrc_sources clk_src_apll = {
 	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
 };
 
+/* Possible clock sources for BPLL Mux */
+static struct clk *clk_src_bpll_list[] = {
+	[0] = &clk_fin_bpll,
+	[1] = &clk_fout_bpll,
+};
+
+struct clksrc_sources clk_src_bpll = {
+	.sources	= clk_src_bpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
+};
+
+/* Possible clock sources for CPLL Mux */
+static struct clk *clk_src_cpll_list[] = {
+	[0] = &clk_fin_cpll,
+	[1] = &clk_fout_cpll,
+};
+
+struct clksrc_sources clk_src_cpll = {
+	.sources	= clk_src_cpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_cpll_list),
+};
+
 /* Possible clock sources for MPLL Mux */
 static struct clk *clk_src_mpll_list[] = {
 	[0] = &clk_fin_mpll,
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 984bf9e..1de4b32 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -18,6 +18,8 @@
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 
 #define clk_fin_apll clk_ext_xtal_mux
+#define clk_fin_bpll clk_ext_xtal_mux
+#define clk_fin_cpll clk_ext_xtal_mux
 #define clk_fin_mpll clk_ext_xtal_mux
 #define clk_fin_epll clk_ext_xtal_mux
 #define clk_fin_dpll clk_ext_xtal_mux
@@ -29,6 +31,8 @@ extern struct clk clk_xusbxti;
 extern struct clk clk_48m;
 extern struct clk s5p_clk_27m;
 extern struct clk clk_fout_apll;
+extern struct clk clk_fout_bpll;
+extern struct clk clk_fout_cpll;
 extern struct clk clk_fout_mpll;
 extern struct clk clk_fout_epll;
 extern struct clk clk_fout_dpll;
@@ -37,6 +41,8 @@ extern struct clk clk_arm;
 extern struct clk clk_vpll;
 
 extern struct clksrc_sources clk_src_apll;
+extern struct clksrc_sources clk_src_bpll;
+extern struct clksrc_sources clk_src_cpll;
 extern struct clksrc_sources clk_src_mpll;
 extern struct clksrc_sources clk_src_epll;
 extern struct clksrc_sources clk_src_dpll;
-- 
1.7.4.4



From kgene.kim at samsung.com  Tue Mar 13 11:30:37 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:37 -0700
Subject: [PATCH v3 06/12] ARM: EXYNOS: add support for EXYNOS5250 SoC
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-7-git-send-email-kgene.kim@samsung.com>

This patch add support for EXYNOS5250 SoC has two Cortex-A15 cores.
Since actually, most codes in mach-exynos/ are used commonly for
EXYNOS4 and EXYNOS5 the EXYNOS5/EXYNOS5250 has been implemented
in mach-exynos/.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/Makefile                            |    1 +
 arch/arm/mach-exynos/common.c                |  191 ++++++++++++++++++++++++--
 arch/arm/mach-exynos/common.h                |   11 ++
 arch/arm/mach-exynos/include/mach/map.h      |   21 +++-
 arch/arm/mach-exynos/include/mach/regs-pmu.h |    1 +
 arch/arm/plat-s5p/Kconfig                    |    4 +-
 arch/arm/plat-samsung/include/plat/cpu.h     |   10 ++
 7 files changed, 223 insertions(+), 16 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1683bfb..a826ffc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0)		:= s5p64x0
 machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100
 machine-$(CONFIG_ARCH_S5PV210)		:= s5pv210
 machine-$(CONFIG_ARCH_EXYNOS4)		:= exynos
+machine-$(CONFIG_ARCH_EXYNOS5)		:= exynos
 machine-$(CONFIG_ARCH_SA1100)		:= sa1100
 machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4a82cf0..7fdb139 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -49,9 +49,12 @@
 static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
+static const char name_exynos5250[] = "EXYNOS5250";
 
 static void exynos4_map_io(void);
+static void exynos5_map_io(void);
 static void exynos4_init_clocks(int xtal);
+static void exynos5_init_clocks(int xtal);
 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
@@ -80,6 +83,14 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4412,
+	}, {
+		.idcode		= EXYNOS5250_SOC_ID,
+		.idmask		= EXYNOS5_SOC_MASK,
+		.map_io		= exynos5_map_io,
+		.init_clocks	= exynos5_init_clocks,
+		.init_uarts	= exynos_init_uarts,
+		.init		= exynos_init,
+		.name		= name_exynos5250,
 	},
 };
 
@@ -88,10 +99,14 @@ static struct cpu_table cpu_ids[] __initdata = {
 static struct map_desc exynos_iodesc[] __initdata = {
 	{
 		.virtual	= (unsigned long)S5P_VA_CHIPID,
-		.pfn		= __phys_to_pfn(EXYNOS4_PA_CHIPID),
+		.pfn		= __phys_to_pfn(EXYNOS_PA_CHIPID),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
-	}, {
+	},
+};
+
+static struct map_desc exynos4_iodesc[] __initdata = {
+	{
 		.virtual	= (unsigned long)S3C_VA_SYS,
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSCON),
 		.length		= SZ_64K,
@@ -141,11 +156,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_UART),
 		.length		= SZ_512K,
 		.type		= MT_DEVICE,
-	},
-};
-
-static struct map_desc exynos4_iodesc[] __initdata = {
-	{
+	}, {
 		.virtual	= (unsigned long)S5P_VA_CMU,
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),
 		.length		= SZ_128K,
@@ -206,11 +217,80 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
 	},
 };
 
+static struct map_desc exynos5_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S3C_VA_SYS,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSCON),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_TIMER,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_TIMER),
+		.length		= SZ_16K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SROMC,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SROMC),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SYSRAM,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSRAM),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_CMU,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),
+		.length		= 144 * SZ_1K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_PMU,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_COMBINER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_UART,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_UART),
+		.length		= SZ_512K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	},
+};
+
 void exynos4_restart(char mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
 
+void exynos5_restart(char mode, const char *cmd)
+{
+	__raw_writel(0x1, EXYNOS_SWRESET);
+}
+
 /*
  * exynos_map_io
  *
@@ -261,6 +341,16 @@ static void __init exynos4_map_io(void)
 	s5p_hdmi_setname("exynos4-hdmi");
 }
 
+static void __init exynos5_map_io(void)
+{
+	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+
+	/* The I2C bus controllers are directly compatible with s3c2440 */
+	s3c_i2c0_setname("s3c2440-i2c");
+	s3c_i2c1_setname("s3c2440-i2c");
+	s3c_i2c2_setname("s3c2440-i2c");
+}
+
 static void __init exynos4_init_clocks(int xtal)
 {
 	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -277,6 +367,17 @@ static void __init exynos4_init_clocks(int xtal)
 	exynos4_setup_clocks();
 }
 
+static void __init exynos5_init_clocks(int xtal)
+{
+	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+	s3c24xx_register_baseclocks(xtal);
+	s5p_register_clocks(xtal);
+
+	exynos5_register_clocks();
+	exynos5_setup_clocks();
+}
+
 #define COMBINER_ENABLE_SET	0x0
 #define COMBINER_ENABLE_CLEAR	0x4
 #define COMBINER_INT_STATUS	0xC
@@ -420,24 +521,59 @@ void __init exynos4_init_irq(void)
 	s5p_init_irq(NULL, 0);
 }
 
+void __init exynos5_init_irq(void)
+{
+	int irq;
+
+	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+
+	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+				COMBINER_IRQ(irq, 0));
+		combiner_cascade_irq(irq, IRQ_SPI(irq));
+	}
+
+	/*
+	 * The parameters of s5p_init_irq() are for VIC init.
+	 * Theses parameters should be NULL and 0 because EXYNOS4
+	 * uses GIC instead of VIC.
+	 */
+	s5p_init_irq(NULL, 0);
+}
+
 struct bus_type exynos4_subsys = {
 	.name		= "exynos4-core",
 	.dev_name	= "exynos4-core",
 };
 
+struct bus_type exynos5_subsys = {
+	.name		= "exynos5-core",
+	.dev_name	= "exynos5-core",
+};
+
 static struct device exynos4_dev = {
 	.bus	= &exynos4_subsys,
 };
 
-static int __init exynos4_core_init(void)
+static struct device exynos5_dev = {
+	.bus	= &exynos5_subsys,
+};
+
+static int __init exynos_core_init(void)
 {
-	return subsys_system_register(&exynos4_subsys, NULL);
+	if (soc_is_exynos5250())
+		return subsys_system_register(&exynos5_subsys, NULL);
+	else
+		return subsys_system_register(&exynos4_subsys, NULL);
 }
-core_initcall(exynos4_core_init);
+core_initcall(exynos_core_init);
 
 #ifdef CONFIG_CACHE_L2X0
 static int __init exynos4_l2x0_cache_init(void)
 {
+	if (soc_is_exynos5250())
+		return 0;
+
 	/* TAG, Data Latency Control: 2cycle */
 	__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 
@@ -457,14 +593,42 @@ static int __init exynos4_l2x0_cache_init(void)
 
 	return 0;
 }
-
 early_initcall(exynos4_l2x0_cache_init);
 #endif
 
+static int __init exynos5_l2_cache_init(void)
+{
+	unsigned int val;
+
+	if (!soc_is_exynos5250())
+		return 0;
+
+	asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+		     "bic %0, %0, #(1 << 2)\n"	/* cache disable */
+		     "mcr p15, 0, %0, c1, c0, 0\n"
+		     "mrc p15, 1, %0, c9, c0, 2\n"
+		     : "=r"(val));
+
+	val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
+
+	asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
+	asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+		     "orr %0, %0, #(1 << 2)\n"	/* cache enable */
+		     "mcr p15, 0, %0, c1, c0, 0\n"
+		     : : "r"(val));
+
+	return 0;
+}
+early_initcall(exynos5_l2_cache_init);
+
 static int __init exynos_init(void)
 {
 	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
-	return device_register(&exynos4_dev);
+
+	if (soc_is_exynos5250())
+		return device_register(&exynos5_dev);
+	else
+		return device_register(&exynos4_dev);
 }
 
 /* uart registration process */
@@ -673,6 +837,9 @@ static int __init exynos4_init_irq_eint(void)
 {
 	int irq;
 
+	if (soc_is_exynos5250())
+		return 0;
+
 	for (irq = 0 ; irq <= 31 ; irq++) {
 		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
 					 handle_level_irq);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index b32c6b5..677b546 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -16,7 +16,9 @@ extern struct sys_timer exynos4_timer;
 
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
+void exynos5_init_irq(void);
 void exynos4_restart(char mode, const char *cmd);
+void exynos5_restart(char mode, const char *cmd);
 
 #ifdef CONFIG_ARCH_EXYNOS4
 void exynos4_register_clocks(void);
@@ -27,6 +29,15 @@ void exynos4_setup_clocks(void);
 #define exynos4_setup_clocks()
 #endif
 
+#ifdef CONFIG_ARCH_EXYNOS5
+void exynos5_register_clocks(void);
+void exynos5_setup_clocks(void);
+
+#else
+#define exynos5_register_clocks()
+#define exynos5_setup_clocks()
+#endif
+
 #ifdef CONFIG_CPU_EXYNOS4210
 void exynos4210_register_clocks(void);
 
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index e8a7801..ac60533 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -25,6 +25,7 @@
 
 #define EXYNOS4_PA_SYSRAM0		0x02025000
 #define EXYNOS4_PA_SYSRAM1		0x02020000
+#define EXYNOS5_PA_SYSRAM		0x02020000
 
 #define EXYNOS4_PA_FIMC0		0x11800000
 #define EXYNOS4_PA_FIMC1		0x11810000
@@ -44,14 +45,23 @@
 #define EXYNOS4_PA_ONENAND		0x0C000000
 #define EXYNOS4_PA_ONENAND_DMA		0x0C600000
 
-#define EXYNOS4_PA_CHIPID		0x10000000
+#define EXYNOS_PA_CHIPID		0x10000000
 
 #define EXYNOS4_PA_SYSCON		0x10010000
+#define EXYNOS5_PA_SYSCON		0x10050100
+
 #define EXYNOS4_PA_PMU			0x10020000
+#define EXYNOS5_PA_PMU			0x10040000
+
 #define EXYNOS4_PA_CMU			0x10030000
+#define EXYNOS5_PA_CMU			0x10010000
 
 #define EXYNOS4_PA_SYSTIMER		0x10050000
+#define EXYNOS5_PA_SYSTIMER		0x101C0000
+
 #define EXYNOS4_PA_WATCHDOG		0x10060000
+#define EXYNOS5_PA_WATCHDOG		0x101D0000
+
 #define EXYNOS4_PA_RTC			0x10070000
 
 #define EXYNOS4_PA_KEYPAD		0x100A0000
@@ -59,9 +69,12 @@
 #define EXYNOS4_PA_DMC0			0x10400000
 
 #define EXYNOS4_PA_COMBINER		0x10440000
+#define EXYNOS5_PA_COMBINER		0x10440000
 
 #define EXYNOS4_PA_GIC_CPU		0x10480000
 #define EXYNOS4_PA_GIC_DIST		0x10490000
+#define EXYNOS5_PA_GIC_CPU		0x10480000
+#define EXYNOS5_PA_GIC_DIST		0x10490000
 
 #define EXYNOS4_PA_COREPERI		0x10500000
 #define EXYNOS4_PA_TWD			0x10500600
@@ -91,7 +104,6 @@
 #define EXYNOS4_PA_SPI1			0x13930000
 #define EXYNOS4_PA_SPI2			0x13940000
 
-
 #define EXYNOS4_PA_GPIO1		0x11400000
 #define EXYNOS4_PA_GPIO2		0x11000000
 #define EXYNOS4_PA_GPIO3		0x03860000
@@ -109,6 +121,7 @@
 #define EXYNOS4_PA_SATAPHY_CTRL		0x126B0000
 
 #define EXYNOS4_PA_SROMC		0x12570000
+#define EXYNOS5_PA_SROMC		0x12250000
 
 #define EXYNOS4_PA_EHCI			0x12580000
 #define EXYNOS4_PA_OHCI			0x12590000
@@ -116,6 +129,7 @@
 #define EXYNOS4_PA_MFC			0x13400000
 
 #define EXYNOS4_PA_UART			0x13800000
+#define EXYNOS5_PA_UART			0x12C00000
 
 #define EXYNOS4_PA_VP			0x12C00000
 #define EXYNOS4_PA_MIXER		0x12C10000
@@ -124,6 +138,7 @@
 #define EXYNOS4_PA_IIC_HDMIPHY		0x138E0000
 
 #define EXYNOS4_PA_IIC(x)		(0x13860000 + ((x) * 0x10000))
+#define EXYNOS5_PA_IIC(x)		(0x12C60000 + ((x) * 0x10000))
 
 #define EXYNOS4_PA_ADC			0x13910000
 #define EXYNOS4_PA_ADC1			0x13911000
@@ -133,8 +148,10 @@
 #define EXYNOS4_PA_SPDIF		0x139B0000
 
 #define EXYNOS4_PA_TIMER		0x139D0000
+#define EXYNOS5_PA_TIMER		0x12DD0000
 
 #define EXYNOS4_PA_SDRAM		0x40000000
+#define EXYNOS5_PA_SDRAM		0x40000000
 
 /* Compatibiltiy Defines */
 
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4fff8e9..4c53f38 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
 #define S5P_USE_STANDBYWFE_ISP_ARM		(1 << 26)
 
 #define S5P_SWRESET				S5P_PMUREG(0x0400)
+#define EXYNOS_SWRESET				S5P_PMUREG(0x0400)
 
 #define S5P_WAKEUP_STAT				S5P_PMUREG(0x0600)
 #define S5P_EINT_WAKEUP_MASK			S5P_PMUREG(0x0604)
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 10e235cc7..88795ea 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -9,8 +9,8 @@ config PLAT_S5P
 	bool
 	depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
 	default y
-	select ARM_VIC if !ARCH_EXYNOS4
-	select ARM_GIC if ARCH_EXYNOS4
+	select ARM_VIC if !ARCH_EXYNOS
+	select ARM_GIC if ARCH_EXYNOS
 	select GIC_NON_BANKED if ARCH_EXYNOS4
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 73cb3cf..787ceac 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -42,6 +42,9 @@ extern unsigned long samsung_cpu_id;
 #define EXYNOS4412_CPU_ID	0xE4412200
 #define EXYNOS4_CPU_MASK	0xFFFE0000
 
+#define EXYNOS5250_SOC_ID	0x43520000
+#define EXYNOS5_SOC_MASK	0xFFFFF000
+
 #define IS_SAMSUNG_CPU(name, id, mask)		\
 static inline int is_samsung_##name(void)	\
 {						\
@@ -58,6 +61,7 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
 
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
     defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -120,6 +124,12 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 #define EXYNOS4210_REV_1_0	(0x10)
 #define EXYNOS4210_REV_1_1	(0x11)
 
+#if defined(CONFIG_SOC_EXYNOS5250)
+# define soc_is_exynos5250()	is_samsung_exynos5250()
+#else
+# define soc_is_exynos5250()	0
+#endif
+
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 
 #ifndef MHZ
-- 
1.7.4.4



From kgene.kim at samsung.com  Tue Mar 13 11:30:31 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:31 -0700
Subject: [PATCH v3 00/12] ARM: EXYNOS: add support new EXYNOS5250
Message-ID: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>

This patch adds support EXYNOS5250 SoC which has two A15 cores
can be used on mobile and tablet devices.

Changes since v2:
- update interrupt number declaration for single zImage
  of exynos4 and exynos5
- allow to select for exynos4 and exynos5 together
- add support EINT for exynos4 and exynos5
- add l2 cache initializer for exynos5250

Changes since v1:
- address comments from mailing list
- update the option accordingly common.[ch]
- update clock part
- get rid of static mapping for uart
- add device tree enabled board file(mach-exynos5-dt.c)
- add initial dts file for EXYNOS5250(SoC), SMDK5250(Board)

[PATCH v3 01/12] ARM: EXYNOS: to declare static for mach-exynos/common.c
[PATCH v3 02/12] ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts()
[PATCH v3 03/12] ARM: EXYNOS: add clock part for EXYNOS5250 SoC
[PATCH v3 04/12] ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
[PATCH v3 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
[PATCH v3 06/12] ARM: EXYNOS: add support for EXYNOS5250 SoC
[PATCH v3 07/12] ARM: EXYNOS: add interrupt definitions for EXYNOS5250
[PATCH v3 08/12] ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5
[PATCH v3 09/12] ARM: EXYNOS: add support get_core_count() for EXYNOS5250
[PATCH v3 10/12] ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5 SoCs
[PATCH v3 11/12] ARM: EXYNOS: add support device tree enabled board file for EXYNOS5
[PATCH v3 12/12] ARM: dts: add initial dts file for EXYNOS5250, SMDK5250


From kgene.kim at samsung.com  Tue Mar 13 11:30:39 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:39 -0700
Subject: [PATCH v3 08/12] ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-9-git-send-email-kgene.kim@samsung.com>

From: Eunki Kim <eunki_kim at samsung.com>

The GPIOs of EXYNOS4 and EXYNOS5 are changed to use
ioremap instead of static mapping. It alse causes the
change of external interrupt IO mapping. This patch
changes EXYNOS4 to EXYNOS for common use and changes
EINT_x macros for supporting dynamic IO mapping.

Signed-off-by: Eunki Kim <eunki_kim at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/common.c                 |  102 ++++++++++++-------------
 arch/arm/mach-exynos/include/mach/gpio.h      |   29 +++++++
 arch/arm/mach-exynos/include/mach/regs-gpio.h |   20 ++---
 3 files changed, 86 insertions(+), 65 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 0b53018..72f21e4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -665,6 +665,8 @@ static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 		s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 }
 
+static void __iomem *exynos_eint_base;
+
 static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
@@ -706,41 +708,41 @@ static unsigned int exynos5_eint0_15_src_int[16] = {
 	EXYNOS5_IRQ_EINT14,
 	EXYNOS5_IRQ_EINT15,
 };
-static inline void exynos4_irq_eint_mask(struct irq_data *data)
+static inline void exynos_irq_eint_mask(struct irq_data *data)
 {
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-	mask |= eint_irq_to_bit(data->irq);
-	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
+	mask |= EINT_OFFSET_BIT(data->irq);
+	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 	spin_unlock(&eint_lock);
 }
 
-static void exynos4_irq_eint_unmask(struct irq_data *data)
+static void exynos_irq_eint_unmask(struct irq_data *data)
 {
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-	mask &= ~(eint_irq_to_bit(data->irq));
-	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
+	mask &= ~(EINT_OFFSET_BIT(data->irq));
+	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 	spin_unlock(&eint_lock);
 }
 
-static inline void exynos4_irq_eint_ack(struct irq_data *data)
+static inline void exynos_irq_eint_ack(struct irq_data *data)
 {
-	__raw_writel(eint_irq_to_bit(data->irq),
-		     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+	__raw_writel(EINT_OFFSET_BIT(data->irq),
+		     EINT_PEND(exynos_eint_base, data->irq));
 }
 
-static void exynos4_irq_eint_maskack(struct irq_data *data)
+static void exynos_irq_eint_maskack(struct irq_data *data)
 {
-	exynos4_irq_eint_mask(data);
-	exynos4_irq_eint_ack(data);
+	exynos_irq_eint_mask(data);
+	exynos_irq_eint_ack(data);
 }
 
-static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
+static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
 	int offs = EINT_OFFSET(data->irq);
 	int shift;
@@ -777,39 +779,24 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
 	mask = 0x7 << shift;
 
 	spin_lock(&eint_lock);
-	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 	ctrl &= ~mask;
 	ctrl |= newvalue << shift;
-	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 	spin_unlock(&eint_lock);
 
-	switch (offs) {
-	case 0 ... 7:
-		s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
-		break;
-	case 8 ... 15:
-		s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
-		break;
-	case 16 ... 23:
-		s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
-		break;
-	case 24 ... 31:
-		s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
-		break;
-	default:
-		printk(KERN_ERR "No such irq number %d", offs);
-	}
+	s3c_gpio_cfgpin(irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 
 	return 0;
 }
 
-static struct irq_chip exynos4_irq_eint = {
-	.name		= "exynos4-eint",
-	.irq_mask	= exynos4_irq_eint_mask,
-	.irq_unmask	= exynos4_irq_eint_unmask,
-	.irq_mask_ack	= exynos4_irq_eint_maskack,
-	.irq_ack	= exynos4_irq_eint_ack,
-	.irq_set_type	= exynos4_irq_eint_set_type,
+static struct irq_chip exynos_irq_eint = {
+	.name		= "exynos-eint",
+	.irq_mask	= exynos_irq_eint_mask,
+	.irq_unmask	= exynos_irq_eint_unmask,
+	.irq_mask_ack	= exynos_irq_eint_maskack,
+	.irq_ack	= exynos_irq_eint_ack,
+	.irq_set_type	= exynos_irq_eint_set_type,
 #ifdef CONFIG_PM
 	.irq_set_wake	= s3c_irqext_wake,
 #endif
@@ -824,12 +811,12 @@ static struct irq_chip exynos4_irq_eint = {
  *
  * Each EINT pend/mask registers handle eight of them.
  */
-static inline void exynos4_irq_demux_eint(unsigned int start)
+static inline void exynos_irq_demux_eint(unsigned int start)
 {
 	unsigned int irq;
 
-	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
-	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+	u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
+	u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 
 	status &= ~mask;
 	status &= 0xff;
@@ -841,16 +828,16 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
 	}
 }
 
-static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_get_chip(irq);
 	chained_irq_enter(chip, desc);
-	exynos4_irq_demux_eint(IRQ_EINT(16));
-	exynos4_irq_demux_eint(IRQ_EINT(24));
+	exynos_irq_demux_eint(IRQ_EINT(16));
+	exynos_irq_demux_eint(IRQ_EINT(24));
 	chained_irq_exit(chip, desc);
 }
 
-static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 {
 	u32 *irq_data = irq_get_handler_data(irq);
 	struct irq_chip *chip = irq_get_chip(irq);
@@ -867,20 +854,27 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
-static int __init exynos4_init_irq_eint(void)
+static int __init exynos_init_irq_eint(void)
 {
 	int irq;
 
 	if (soc_is_exynos5250())
-		return 0;
+		exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
+	else
+		exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
+
+	if (exynos_eint_base == NULL) {
+		pr_err("unable to ioremap for EINT base address\n");
+		return -ENOMEM;
+	}
 
 	for (irq = 0 ; irq <= 31 ; irq++) {
-		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
+		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 					 handle_level_irq);
 		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 	}
 
-	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 
 	for (irq = 0 ; irq <= 15 ; irq++) {
 		eint0_15_data[irq] = IRQ_EINT(irq);
@@ -889,15 +883,15 @@ static int __init exynos4_init_irq_eint(void)
 			irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 					     &eint0_15_data[irq]);
 			irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
-						exynos4_irq_eint0_15);
+						exynos_irq_eint0_15);
 		} else {
 			irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 					     &eint0_15_data[irq]);
 			irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
-					exynos4_irq_eint0_15);
+					exynos_irq_eint0_15);
 		}
 	}
 
 	return 0;
 }
-arch_initcall(exynos4_init_irq_eint);
+arch_initcall(exynos_init_irq_eint);
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 80523ca..c09deb6 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -146,4 +146,33 @@ enum s5p_gpio_number {
 #define ARCH_NR_GPIOS		(EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) +	\
 				 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
 
+#include <linux/types.h>
+#include <linux/err.h>
+#include <mach/irqs.h>
+#include <plat/cpu.h>
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+	if (irq < IRQ_EINT(0))
+		return -EINVAL;
+
+	irq -= IRQ_EINT(0);
+	if (irq < 8)
+		return soc_is_exynos5250() ?  EXYNOS5_GPX0(irq) :
+					 EXYNOS4_GPX0(irq);
+	irq -= 8;
+	if (irq < 8)
+		return soc_is_exynos5250() ?  EXYNOS5_GPX1(irq) :
+					 EXYNOS4_GPX1(irq);
+	irq -= 8;
+	if (irq < 8)
+		return soc_is_exynos5250() ?  EXYNOS5_GPX2(irq) :
+					 EXYNOS4_GPX2(irq);
+	irq -= 8;
+	if (irq < 8)
+		return soc_is_exynos5250() ?  EXYNOS5_GPX3(irq) :
+					 EXYNOS4_GPX3(irq);
+	return -EINVAL;
+}
+
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index 1401b21..e4b5b60 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -16,6 +16,15 @@
 #include <mach/map.h>
 #include <mach/irqs.h>
 
+#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
+#define EINT_CON(b, x)			(b + 0xE00 + (EINT_REG_NR(x) * 4))
+#define EINT_FLTCON(b, x)		(b + 0xE80 + (EINT_REG_NR(x) * 4))
+#define EINT_MASK(b, x)			(b + 0xF00 + (EINT_REG_NR(x) * 4))
+#define EINT_PEND(b, x)			(b + 0xF40 + (EINT_REG_NR(x) * 4))
+
+#define EINT_OFFSET_BIT(x)		(1 << (EINT_OFFSET(x) & 0x7))
+
+/* compatibility for plat-s5p/irq-pm.c */
 #define EXYNOS4_EINT40CON		(S5P_VA_GPIO2 + 0xE00)
 #define S5P_EINT_CON(x)			(EXYNOS4_EINT40CON + ((x) * 0x4))
 
@@ -28,15 +37,4 @@
 #define EXYNOS4_EINT40PEND		(S5P_VA_GPIO2 + 0xF40)
 #define S5P_EINT_PEND(x)		(EXYNOS4_EINT40PEND + ((x) * 0x4))
 
-#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
-
-#define eint_irq_to_bit(irq)		(1 << (EINT_OFFSET(irq) & 0x7))
-
-#define EINT_MODE			S3C_GPIO_SFN(0xf)
-
-#define EINT_GPIO_0(x)			EXYNOS4_GPX0(x)
-#define EINT_GPIO_1(x)			EXYNOS4_GPX1(x)
-#define EINT_GPIO_2(x)			EXYNOS4_GPX2(x)
-#define EINT_GPIO_3(x)			EXYNOS4_GPX3(x)
-
 #endif /* __ASM_ARCH_REGS_GPIO_H */
-- 
1.7.4.4



From kgene.kim at samsung.com  Tue Mar 13 11:30:40 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:40 -0700
Subject: [PATCH v3 09/12] ARM: EXYNOS: add support get_core_count() for
 EXYNOS5250
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-10-git-send-email-kgene.kim@samsung.com>

The EXYNOS5250 has two Cortex-A15 cores and there's no
need to call scu_enable() in platform_smp_prepare_cpus().

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/platsmp.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 0f2035a..36c3984 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -166,7 +166,10 @@ void __init smp_init_cpus(void)
 	void __iomem *scu_base = scu_base_addr();
 	unsigned int i, ncores;
 
-	ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+	if (soc_is_exynos5250())
+		ncores = 2;
+	else
+		ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
 	/* sanity check */
 	if (ncores > nr_cpu_ids) {
@@ -183,8 +186,8 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
-
-	scu_enable(scu_base_addr());
+	if (!soc_is_exynos5250())
+		scu_enable(scu_base_addr());
 
 	/*
 	 * Write the address of secondary startup into the
-- 
1.7.4.4



From kgene.kim at samsung.com  Tue Mar 13 11:30:42 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:42 -0700
Subject: [PATCH v3 11/12] ARM: EXYNOS: add support device tree enabled board
 file for EXYNOS5
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-12-git-send-email-kgene.kim@samsung.com>

This patch adds a new EXYNOS5 compatible device tree enabled board
When using this, a corresponding device tree blob which describes the
board's properties should be supplied at boot time to the kernel.

Cc: Thomas Abraham <thomas.abraham at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/Kconfig           |   22 +++++++++-
 arch/arm/mach-exynos/Makefile          |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c |   78 ++++++++++++++++++++++++++++++++
 3 files changed, 100 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-exynos/mach-exynos5-dt.c

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 31ef33f..bca0ded 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -358,7 +358,18 @@ config MACH_SMDK4412
 	  Machine support for Samsung SMDK4412
 endif
 
-comment "Flattened Device Tree based board for Exynos4 based SoC"
+if ARCH_EXYNOS5
+
+comment "EXYNOS5250 Boards"
+
+config MACH_SMDK5250
+	bool "SMDK5250"
+	select SOC_EXYNOS5250
+	help
+	  Machine support for Samsung SMDK5250
+endif
+
+comment "Flattened Device Tree based board for EXYNOS SoCs"
 
 config MACH_EXYNOS4_DT
 	bool "Samsung Exynos4 Machine using device tree"
@@ -372,6 +383,15 @@ config MACH_EXYNOS4_DT
 	  Note: This is under development and not all peripherals can be supported
 	  with this machine file.
 
+config MACH_EXYNOS5_DT
+	bool "SAMSUNG EXYNOS5 Machine using device tree"
+	select SOC_EXYNOS5250
+	select USE_OF
+	select ARM_AMBA
+	help
+	  Machine support for Samsung Exynos4 machine with device tree enabled.
+	  Select this if a fdt blob is available for the EXYNOS4 SoC based board.
+
 if ARCH_EXYNOS4
 
 comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 7214092..29967ef 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_MACH_SMDK4212)		+= mach-smdk4x12.o
 obj-$(CONFIG_MACH_SMDK4412)		+= mach-smdk4x12.o
 
 obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o
+obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
 
 # device support
 
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
new file mode 100644
index 0000000..0d26f50
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -0,0 +1,78 @@
+/*
+ * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/of_platform.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/regs-serial.h>
+
+#include "common.h"
+
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the EXYNOS5 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
+				"exynos4210-uart.0", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
+				"exynos4210-uart.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
+				"exynos4210-uart.2", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
+				"exynos4210-uart.3", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
+	{},
+};
+
+static void __init exynos5250_dt_map_io(void)
+{
+	exynos_init_io(NULL, 0);
+	s3c24xx_init_clocks(24000000);
+}
+
+static void __init exynos5250_dt_machine_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+				exynos5250_auxdata_lookup, NULL);
+}
+
+static char const *exynos5250_dt_compat[] __initdata = {
+	"samsung,exynos5250",
+	NULL
+};
+
+DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
+	/* Maintainer: Kukjin Kim <kgene.kim at samsung.com> */
+	.init_irq	= exynos5_init_irq,
+	.map_io		= exynos5250_dt_map_io,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= exynos5250_dt_machine_init,
+	.timer		= &exynos4_timer,
+	.dt_compat	= exynos5250_dt_compat,
+	.restart        = exynos5_restart,
+MACHINE_END
-- 
1.7.4.4



From kgene.kim at samsung.com  Tue Mar 13 11:30:43 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:43 -0700
Subject: [PATCH v3 12/12] ARM: dts: add initial dts file for EXYNOS5250,
 SMDK5250
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-13-git-send-email-kgene.kim@samsung.com>

This patch adds initial dts file for EXYNOS5250 SoC. This dts
file is including the SoC specific devices and properties. And
adds the dts file for SMDK5250 board which uses the EXYNOS5250
dts file. Its board specific properites will be added later.

Cc: Thomas Abraham <thomas.abraham at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   26 ++
 arch/arm/boot/dts/exynos5250.dtsi         |  413 +++++++++++++++++++++++++++++
 2 files changed, 439 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos5250-smdk5250.dts
 create mode 100644 arch/arm/boot/dts/exynos5250.dtsi

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
new file mode 100644
index 0000000..491539a
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -0,0 +1,26 @@
+/*
+ * SAMSUNG SMDK5250 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+	compatible = "samsung,smdk5250", "samsung,exynos5250";
+
+	memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	chosen {
+		bootargs = "root=/dev/ram0 rw ramdisk=8192 rootfstype=squashfs initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
+	};
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
new file mode 100644
index 0000000..3e70608
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -0,0 +1,413 @@
+/*
+ * SAMSUNG EXYNOS5250 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
+ * EXYNOS5250 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
+ * additional nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "samsung,exynos5250";
+	interrupt-parent = <&gic>;
+
+	gic:interrupt-controller at 10490000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+	};
+
+	watchdog at 101D0000 {
+		compatible = "samsung,s3c2410-wdt";
+		reg = <0x101D0000 0x100>;
+		interrupts = <0 42 0>;
+	};
+
+	rtc at 101E0000 {
+		compatible = "samsung,s3c6410-rtc";
+		reg = <0x101E0000 0x100>;
+		interrupts = <0 43 0>, <0 44 0>;
+	};
+
+	sdhci at 12200000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12200000 0x100>;
+		interrupts = <0 75 0>;
+	};
+
+	sdhci at 12210000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12210000 0x100>;
+		interrupts = <0 76 0>;
+	};
+
+	sdhci at 12220000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12220000 0x100>;
+		interrupts = <0 77 0>;
+	};
+
+	sdhci at 12230000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12230000 0x100>;
+		interrupts = <0 78 0>;
+	};
+
+	serial at 12C00000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 51 0>;
+	};
+
+	serial at 12C10000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C10000 0x100>;
+		interrupts = <0 52 0>;
+	};
+
+	serial at 12C20000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C20000 0x100>;
+		interrupts = <0 53 0>;
+	};
+
+	serial at 12C30000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C30000 0x100>;
+		interrupts = <0 54 0>;
+	};
+
+	i2c at 12C60000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C60000 0x100>;
+		interrupts = <0 56 0>;
+	};
+
+	i2c at 12C70000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C70000 0x100>;
+		interrupts = <0 57 0>;
+	};
+
+	i2c at 12C80000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C80000 0x100>;
+		interrupts = <0 58 0>;
+	};
+
+	i2c at 12C90000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C90000 0x100>;
+		interrupts = <0 59 0>;
+	};
+
+	i2c at 12CA0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CA0000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c at 12CB0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CB0000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c at 12CC0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CC0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c at 12CD0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CD0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		pdma0: pdma at 121A0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x121A0000 0x1000>;
+			interrupts = <0 34 0>;
+		};
+
+		pdma1: pdma at 121B0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x121B0000 0x1000>;
+			interrupts = <0 35 0>;
+		};
+
+		mdma0: pdma at 10800000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x10800000 0x1000>;
+			interrupts = <0 33 0>;
+		};
+
+		mdma1: pdma at 11C10000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x11C10000 0x1000>;
+			interrupts = <0 124 0>;
+		};
+	};
+
+	gpio-controllers {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		gpio-controller;
+		ranges;
+
+		gpa0: gpio-controller at 11400000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpa1: gpio-controller at 11400020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpa2: gpio-controller at 11400040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb0: gpio-controller at 11400060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb1: gpio-controller at 11400080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb2: gpio-controller at 114000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb3: gpio-controller at 114000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc0: gpio-controller at 114000E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc1: gpio-controller at 11400100 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400100 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc2: gpio-controller at 11400120 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400120 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc3: gpio-controller at 11400140 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400140 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd0: gpio-controller at 11400160 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400160 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd1: gpio-controller at 11400180 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400180 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy0: gpio-controller at 114001A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy1: gpio-controller at 114001C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy2: gpio-controller at 114001E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy3: gpio-controller at 11400200 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400200 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy4: gpio-controller at 11400220 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400220 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy5: gpio-controller at 11400240 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400240 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy6: gpio-controller at 11400260 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400260 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx0: gpio-controller at 11400C00 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C00 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx1: gpio-controller at 11400C20 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C20 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx2: gpio-controller at 11400C40 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C40 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx3: gpio-controller at 11400C60 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C60 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpe0: gpio-controller at 13400000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpe1: gpio-controller at 13400020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf0: gpio-controller at 13400040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf1: gpio-controller at 13400060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpg0: gpio-controller at 13400080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpg1: gpio-controller at 134000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x134000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpg2: gpio-controller at 134000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x134000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gph0: gpio-controller at 134000E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x134000E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gph1: gpio-controller at 13400100 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400100 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv0: gpio-controller at 10D10000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv1: gpio-controller at 10D10020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv2: gpio-controller at 10D10040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv3: gpio-controller at 10D10060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv4: gpio-controller at 10D10080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpz: gpio-controller at 03860000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x03860000 0x20>;
+			#gpio-cells = <4>;
+		};
+	};
+};
-- 
1.7.4.4



From kgene.kim at samsung.com  Tue Mar 13 11:30:38 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:38 -0700
Subject: [PATCH v3 07/12] ARM: EXYNOS: add interrupt definitions for EXYNOS5250
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-8-git-send-email-kgene.kim@samsung.com>

ARM: EXYNOS: irqs.h for exynos4 and exynos5 - WIP
This patch adds the interrupt definitions for EXYNOS5250 at
<mach/irqs.h> file. Basically, now it is needed for EXYNOS5250
interrupt and will be updated for single zImage next time.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/common.c            |   97 ++++--
 arch/arm/mach-exynos/dev-ahci.c          |    4 +-
 arch/arm/mach-exynos/dev-audio.c         |    4 +-
 arch/arm/mach-exynos/include/mach/irqs.h |  580 ++++++++++++++++++++++--------
 arch/arm/mach-exynos/mct.c               |   23 +-
 arch/arm/plat-s5p/irq-pm.c               |   25 +-
 arch/arm/plat-samsung/irq-vic-timer.c    |   16 +
 7 files changed, 548 insertions(+), 201 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 7fdb139..0b53018 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -345,6 +345,11 @@ static void __init exynos5_map_io(void)
 {
 	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 
+	s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
+	s3c_device_i2c0.resource[0].end   = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
+	s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
+	s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
+
 	/* The I2C bus controllers are directly compatible with s3c2440 */
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
@@ -451,7 +456,14 @@ static struct irq_chip combiner_chip = {
 
 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 {
-	if (combiner_nr >= MAX_COMBINER_NR)
+	unsigned int max_nr;
+
+	if (soc_is_exynos5250())
+		max_nr = EXYNOS5_MAX_COMBINER_NR;
+	else
+		max_nr = EXYNOS4_MAX_COMBINER_NR;
+
+	if (combiner_nr >= max_nr)
 		BUG();
 	if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 		BUG();
@@ -462,8 +474,14 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
 			  unsigned int irq_start)
 {
 	unsigned int i;
+	unsigned int max_nr;
 
-	if (combiner_nr >= MAX_COMBINER_NR)
+	if (soc_is_exynos5250())
+		max_nr = EXYNOS5_MAX_COMBINER_NR;
+	else
+		max_nr = EXYNOS4_MAX_COMBINER_NR;
+
+	if (combiner_nr >= max_nr)
 		BUG();
 
 	combiner_data[combiner_nr].base = base;
@@ -506,7 +524,7 @@ void __init exynos4_init_irq(void)
 		of_irq_init(exynos4_dt_irq_match);
 #endif
 
-	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+	for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
 
 		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 				COMBINER_IRQ(irq, 0));
@@ -527,7 +545,7 @@ void __init exynos5_init_irq(void)
 
 	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 
-	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+	for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
 		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 				COMBINER_IRQ(irq, 0));
 		combiner_cascade_irq(irq, IRQ_SPI(irq));
@@ -651,27 +669,43 @@ static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
 
-static unsigned int exynos4_get_irq_nr(unsigned int number)
-{
-	u32 ret = 0;
-
-	switch (number) {
-	case 0 ... 3:
-		ret = (number + IRQ_EINT0);
-		break;
-	case 4 ... 7:
-		ret = (number + (IRQ_EINT4 - 4));
-		break;
-	case 8 ... 15:
-		ret = (number + (IRQ_EINT8 - 8));
-		break;
-	default:
-		printk(KERN_ERR "number available : %d\n", number);
-	}
-
-	return ret;
-}
+static unsigned int exynos4_eint0_15_src_int[16] = {
+	EXYNOS4_IRQ_EINT0,
+	EXYNOS4_IRQ_EINT1,
+	EXYNOS4_IRQ_EINT2,
+	EXYNOS4_IRQ_EINT3,
+	EXYNOS4_IRQ_EINT4,
+	EXYNOS4_IRQ_EINT5,
+	EXYNOS4_IRQ_EINT6,
+	EXYNOS4_IRQ_EINT7,
+	EXYNOS4_IRQ_EINT8,
+	EXYNOS4_IRQ_EINT9,
+	EXYNOS4_IRQ_EINT10,
+	EXYNOS4_IRQ_EINT11,
+	EXYNOS4_IRQ_EINT12,
+	EXYNOS4_IRQ_EINT13,
+	EXYNOS4_IRQ_EINT14,
+	EXYNOS4_IRQ_EINT15,
+};
 
+static unsigned int exynos5_eint0_15_src_int[16] = {
+	EXYNOS5_IRQ_EINT0,
+	EXYNOS5_IRQ_EINT1,
+	EXYNOS5_IRQ_EINT2,
+	EXYNOS5_IRQ_EINT3,
+	EXYNOS5_IRQ_EINT4,
+	EXYNOS5_IRQ_EINT5,
+	EXYNOS5_IRQ_EINT6,
+	EXYNOS5_IRQ_EINT7,
+	EXYNOS5_IRQ_EINT8,
+	EXYNOS5_IRQ_EINT9,
+	EXYNOS5_IRQ_EINT10,
+	EXYNOS5_IRQ_EINT11,
+	EXYNOS5_IRQ_EINT12,
+	EXYNOS5_IRQ_EINT13,
+	EXYNOS5_IRQ_EINT14,
+	EXYNOS5_IRQ_EINT15,
+};
 static inline void exynos4_irq_eint_mask(struct irq_data *data)
 {
 	u32 mask;
@@ -846,15 +880,22 @@ static int __init exynos4_init_irq_eint(void)
 		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 	}
 
-	irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
 
 	for (irq = 0 ; irq <= 15 ; irq++) {
 		eint0_15_data[irq] = IRQ_EINT(irq);
 
-		irq_set_handler_data(exynos4_get_irq_nr(irq),
-				     &eint0_15_data[irq]);
-		irq_set_chained_handler(exynos4_get_irq_nr(irq),
+		if (soc_is_exynos5250()) {
+			irq_set_handler_data(exynos4_eint0_15_src_int[irq],
+					     &eint0_15_data[irq]);
+			irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
+						exynos4_irq_eint0_15);
+		} else {
+			irq_set_handler_data(exynos5_eint0_15_src_int[irq],
+					     &eint0_15_data[irq]);
+			irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 					exynos4_irq_eint0_15);
+		}
 	}
 
 	return 0;
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
index f57a3de..50ce5b0 100644
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ b/arch/arm/mach-exynos/dev-ahci.c
@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= IRQ_SATA,
-		.end	= IRQ_SATA,
+		.start	= EXYNOS4_IRQ_SATA,
+		.end	= EXYNOS4_IRQ_SATA,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index 5a9f9c2e..7199e1a 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
 		.flags	= IORESOURCE_DMA,
 	},
 	[4] = {
-		.start	= IRQ_AC97,
-		.end	= IRQ_AC97,
+		.start	= EXYNOS4_IRQ_AC97,
+		.end	= EXYNOS4_IRQ_AC97,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index e27e0f9..6f51361 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * EXYNOS4 - IRQ definitions
+ * EXYNOS - IRQ definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,170 +16,445 @@
 
 /* PPI: Private Peripheral Interrupt */
 
-#define IRQ_PPI(x)		(x+16)
-
-#define IRQ_MCT_LOCALTIMER	IRQ_PPI(12)
+#define IRQ_PPI(x)			(x + 16)
 
 /* SPI: Shared Peripheral Interrupt */
 
-#define IRQ_SPI(x)		(x+32)
-
-#define IRQ_EINT0		IRQ_SPI(16)
-#define IRQ_EINT1		IRQ_SPI(17)
-#define IRQ_EINT2		IRQ_SPI(18)
-#define IRQ_EINT3		IRQ_SPI(19)
-#define IRQ_EINT4		IRQ_SPI(20)
-#define IRQ_EINT5		IRQ_SPI(21)
-#define IRQ_EINT6		IRQ_SPI(22)
-#define IRQ_EINT7		IRQ_SPI(23)
-#define IRQ_EINT8		IRQ_SPI(24)
-#define IRQ_EINT9		IRQ_SPI(25)
-#define IRQ_EINT10		IRQ_SPI(26)
-#define IRQ_EINT11		IRQ_SPI(27)
-#define IRQ_EINT12		IRQ_SPI(28)
-#define IRQ_EINT13		IRQ_SPI(29)
-#define IRQ_EINT14		IRQ_SPI(30)
-#define IRQ_EINT15		IRQ_SPI(31)
-#define IRQ_EINT16_31		IRQ_SPI(32)
-
-#define IRQ_PDMA0		IRQ_SPI(35)
-#define IRQ_PDMA1		IRQ_SPI(36)
-#define IRQ_TIMER0_VIC		IRQ_SPI(37)
-#define IRQ_TIMER1_VIC		IRQ_SPI(38)
-#define IRQ_TIMER2_VIC		IRQ_SPI(39)
-#define IRQ_TIMER3_VIC		IRQ_SPI(40)
-#define IRQ_TIMER4_VIC		IRQ_SPI(41)
-#define IRQ_MCT_L0		IRQ_SPI(42)
-#define IRQ_WDT			IRQ_SPI(43)
-#define IRQ_RTC_ALARM		IRQ_SPI(44)
-#define IRQ_RTC_TIC		IRQ_SPI(45)
-#define IRQ_GPIO_XB		IRQ_SPI(46)
-#define IRQ_GPIO_XA		IRQ_SPI(47)
-#define IRQ_MCT_L1		IRQ_SPI(48)
-
-#define IRQ_UART0		IRQ_SPI(52)
-#define IRQ_UART1		IRQ_SPI(53)
-#define IRQ_UART2		IRQ_SPI(54)
-#define IRQ_UART3		IRQ_SPI(55)
-#define IRQ_UART4		IRQ_SPI(56)
-#define IRQ_MCT_G0		IRQ_SPI(57)
-#define IRQ_IIC			IRQ_SPI(58)
-#define IRQ_IIC1		IRQ_SPI(59)
-#define IRQ_IIC2		IRQ_SPI(60)
-#define IRQ_IIC3		IRQ_SPI(61)
-#define IRQ_IIC4		IRQ_SPI(62)
-#define IRQ_IIC5		IRQ_SPI(63)
-#define IRQ_IIC6		IRQ_SPI(64)
-#define IRQ_IIC7		IRQ_SPI(65)
-#define IRQ_SPI0		IRQ_SPI(66)
-#define IRQ_SPI1		IRQ_SPI(67)
-#define IRQ_SPI2		IRQ_SPI(68)
-
-#define IRQ_USB_HOST		IRQ_SPI(70)
-#define IRQ_USB_HSOTG		IRQ_SPI(71)
-#define IRQ_MODEM_IF		IRQ_SPI(72)
-#define IRQ_HSMMC0		IRQ_SPI(73)
-#define IRQ_HSMMC1		IRQ_SPI(74)
-#define IRQ_HSMMC2		IRQ_SPI(75)
-#define IRQ_HSMMC3		IRQ_SPI(76)
-#define IRQ_DWMCI		IRQ_SPI(77)
-
-#define IRQ_MIPI_CSIS0		IRQ_SPI(78)
-#define IRQ_MIPI_CSIS1		IRQ_SPI(80)
-
-#define IRQ_ONENAND_AUDI	IRQ_SPI(82)
-#define IRQ_ROTATOR		IRQ_SPI(83)
-#define IRQ_FIMC0		IRQ_SPI(84)
-#define IRQ_FIMC1		IRQ_SPI(85)
-#define IRQ_FIMC2		IRQ_SPI(86)
-#define IRQ_FIMC3		IRQ_SPI(87)
-#define IRQ_JPEG		IRQ_SPI(88)
-#define IRQ_2D			IRQ_SPI(89)
-#define IRQ_PCIE		IRQ_SPI(90)
-
-#define IRQ_MIXER		IRQ_SPI(91)
-#define IRQ_HDMI		IRQ_SPI(92)
-#define IRQ_IIC_HDMIPHY		IRQ_SPI(93)
-#define IRQ_MFC			IRQ_SPI(94)
-#define IRQ_SDO			IRQ_SPI(95)
-
-#define IRQ_AUDIO_SS		IRQ_SPI(96)
-#define IRQ_I2S0		IRQ_SPI(97)
-#define IRQ_I2S1		IRQ_SPI(98)
-#define IRQ_I2S2		IRQ_SPI(99)
-#define IRQ_AC97		IRQ_SPI(100)
-
-#define IRQ_SPDIF		IRQ_SPI(104)
-#define IRQ_ADC0		IRQ_SPI(105)
-#define IRQ_PEN0		IRQ_SPI(106)
-#define IRQ_ADC1		IRQ_SPI(107)
-#define IRQ_PEN1		IRQ_SPI(108)
-#define IRQ_KEYPAD		IRQ_SPI(109)
-#define IRQ_PMU			IRQ_SPI(110)
-#define IRQ_GPS			IRQ_SPI(111)
-#define IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
-#define IRQ_SLIMBUS		IRQ_SPI(113)
-
-#define IRQ_TSI			IRQ_SPI(115)
-#define IRQ_SATA		IRQ_SPI(116)
-
-#define MAX_IRQ_IN_COMBINER	8
-#define COMBINER_GROUP(x)	((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y)	(COMBINER_GROUP(x) + y)
-
-#define IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
-#define IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
-#define IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
-#define IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
-#define IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
-#define IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
-#define IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
-#define IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
-
-#define IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
-#define IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
-#define IRQ_SYSMMU_LCD0_M0_0	COMBINER_IRQ(5, 2)
-#define IRQ_SYSMMU_LCD1_M1_0	COMBINER_IRQ(5, 3)
-#define IRQ_SYSMMU_TV_M0_0	COMBINER_IRQ(5, 4)
-#define IRQ_SYSMMU_MFC_M0_0	COMBINER_IRQ(5, 5)
-#define IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
-#define IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
-
-#define IRQ_FIMD0_FIFO		COMBINER_IRQ(11, 0)
-#define IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
-#define IRQ_FIMD0_SYSTEM	COMBINER_IRQ(11, 2)
-
-#define MAX_COMBINER_NR		16
-
-#define IRQ_ADC			IRQ_ADC0
-#define IRQ_TC			IRQ_PEN0
-
-#define S5P_IRQ_EINT_BASE	COMBINER_IRQ(MAX_COMBINER_NR, 0)
-
-#define S5P_EINT_BASE1		(S5P_IRQ_EINT_BASE + 0)
-#define S5P_EINT_BASE2		(S5P_IRQ_EINT_BASE + 16)
-
-/* optional GPIO interrupts */
-#define S5P_GPIOINT_BASE	(S5P_IRQ_EINT_BASE + 32)
-#define IRQ_GPIO1_NR_GROUPS	16
-#define IRQ_GPIO2_NR_GROUPS	9
-#define IRQ_GPIO_END		(S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-
-#define IRQ_TIMER_BASE		(IRQ_GPIO_END + 64)
+#define IRQ_SPI(x)			(x + 32)
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+/* COMBINER */
+
+#define MAX_IRQ_IN_COMBINER		8
+#define COMBINER_GROUP(x)		((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
+#define COMBINER_IRQ(x, y)		(COMBINER_GROUP(x) + y)
+
+/* For EXYNOS4 and EXYNOS5 */
+
+#define EXYNOS_IRQ_MCT_LOCALTIMER	IRQ_PPI(12)
+
+#define EXYNOS_IRQ_EINT16_31		IRQ_SPI(32)
+
+/* For EXYNOS4 SoCs */
+
+#define EXYNOS4_IRQ_EINT0		IRQ_SPI(16)
+#define EXYNOS4_IRQ_EINT1		IRQ_SPI(17)
+#define EXYNOS4_IRQ_EINT2		IRQ_SPI(18)
+#define EXYNOS4_IRQ_EINT3		IRQ_SPI(19)
+#define EXYNOS4_IRQ_EINT4		IRQ_SPI(20)
+#define EXYNOS4_IRQ_EINT5		IRQ_SPI(21)
+#define EXYNOS4_IRQ_EINT6		IRQ_SPI(22)
+#define EXYNOS4_IRQ_EINT7		IRQ_SPI(23)
+#define EXYNOS4_IRQ_EINT8		IRQ_SPI(24)
+#define EXYNOS4_IRQ_EINT9		IRQ_SPI(25)
+#define EXYNOS4_IRQ_EINT10		IRQ_SPI(26)
+#define EXYNOS4_IRQ_EINT11		IRQ_SPI(27)
+#define EXYNOS4_IRQ_EINT12		IRQ_SPI(28)
+#define EXYNOS4_IRQ_EINT13		IRQ_SPI(29)
+#define EXYNOS4_IRQ_EINT14		IRQ_SPI(30)
+#define EXYNOS4_IRQ_EINT15		IRQ_SPI(31)
+
+#define EXYNOS4_IRQ_PDMA0		IRQ_SPI(35)
+#define EXYNOS4_IRQ_PDMA1		IRQ_SPI(36)
+#define EXYNOS4_IRQ_TIMER0_VIC		IRQ_SPI(37)
+#define EXYNOS4_IRQ_TIMER1_VIC		IRQ_SPI(38)
+#define EXYNOS4_IRQ_TIMER2_VIC		IRQ_SPI(39)
+#define EXYNOS4_IRQ_TIMER3_VIC		IRQ_SPI(40)
+#define EXYNOS4_IRQ_TIMER4_VIC		IRQ_SPI(41)
+#define EXYNOS4_IRQ_MCT_L0		IRQ_SPI(42)
+#define EXYNOS4_IRQ_WDT			IRQ_SPI(43)
+#define EXYNOS4_IRQ_RTC_ALARM		IRQ_SPI(44)
+#define EXYNOS4_IRQ_RTC_TIC		IRQ_SPI(45)
+#define EXYNOS4_IRQ_GPIO_XB		IRQ_SPI(46)
+#define EXYNOS4_IRQ_GPIO_XA		IRQ_SPI(47)
+#define EXYNOS4_IRQ_MCT_L1		IRQ_SPI(48)
 
 #define EXYNOS4_IRQ_UART0		IRQ_SPI(52)
 #define EXYNOS4_IRQ_UART1		IRQ_SPI(53)
 #define EXYNOS4_IRQ_UART2		IRQ_SPI(54)
 #define EXYNOS4_IRQ_UART3		IRQ_SPI(55)
 #define EXYNOS4_IRQ_UART4		IRQ_SPI(56)
+#define EXYNOS4_IRQ_MCT_G0		IRQ_SPI(57)
+#define EXYNOS4_IRQ_IIC			IRQ_SPI(58)
+#define EXYNOS4_IRQ_IIC1		IRQ_SPI(59)
+#define EXYNOS4_IRQ_IIC2		IRQ_SPI(60)
+#define EXYNOS4_IRQ_IIC3		IRQ_SPI(61)
+#define EXYNOS4_IRQ_IIC4		IRQ_SPI(62)
+#define EXYNOS4_IRQ_IIC5		IRQ_SPI(63)
+#define EXYNOS4_IRQ_IIC6		IRQ_SPI(64)
+#define EXYNOS4_IRQ_IIC7		IRQ_SPI(65)
+#define EXYNOS4_IRQ_SPI0		IRQ_SPI(66)
+#define EXYNOS4_IRQ_SPI1		IRQ_SPI(67)
+#define EXYNOS4_IRQ_SPI2		IRQ_SPI(68)
+
+#define EXYNOS4_IRQ_USB_HOST		IRQ_SPI(70)
+#define EXYNOS4_IRQ_USB_HSOTG		IRQ_SPI(71)
+#define EXYNOS4_IRQ_MODEM_IF		IRQ_SPI(72)
+#define EXYNOS4_IRQ_HSMMC0		IRQ_SPI(73)
+#define EXYNOS4_IRQ_HSMMC1		IRQ_SPI(74)
+#define EXYNOS4_IRQ_HSMMC2		IRQ_SPI(75)
+#define EXYNOS4_IRQ_HSMMC3		IRQ_SPI(76)
+#define EXYNOS4_IRQ_DWMCI		IRQ_SPI(77)
+
+#define EXYNOS4_IRQ_MIPI_CSIS0		IRQ_SPI(78)
+#define EXYNOS4_IRQ_MIPI_CSIS1		IRQ_SPI(80)
+
+#define EXYNOS4_IRQ_ONENAND_AUDI	IRQ_SPI(82)
+#define EXYNOS4_IRQ_ROTATOR		IRQ_SPI(83)
+#define EXYNOS4_IRQ_FIMC0		IRQ_SPI(84)
+#define EXYNOS4_IRQ_FIMC1		IRQ_SPI(85)
+#define EXYNOS4_IRQ_FIMC2		IRQ_SPI(86)
+#define EXYNOS4_IRQ_FIMC3		IRQ_SPI(87)
+#define EXYNOS4_IRQ_JPEG		IRQ_SPI(88)
+#define EXYNOS4_IRQ_2D			IRQ_SPI(89)
+#define EXYNOS4_IRQ_PCIE		IRQ_SPI(90)
+
+#define EXYNOS4_IRQ_MIXER		IRQ_SPI(91)
+#define EXYNOS4_IRQ_HDMI		IRQ_SPI(92)
+#define EXYNOS4_IRQ_IIC_HDMIPHY		IRQ_SPI(93)
+#define EXYNOS4_IRQ_MFC			IRQ_SPI(94)
+#define EXYNOS4_IRQ_SDO			IRQ_SPI(95)
+
+#define EXYNOS4_IRQ_AUDIO_SS		IRQ_SPI(96)
+#define EXYNOS4_IRQ_I2S0		IRQ_SPI(97)
+#define EXYNOS4_IRQ_I2S1		IRQ_SPI(98)
+#define EXYNOS4_IRQ_I2S2		IRQ_SPI(99)
+#define EXYNOS4_IRQ_AC97		IRQ_SPI(100)
+
+#define EXYNOS4_IRQ_SPDIF		IRQ_SPI(104)
+#define EXYNOS4_IRQ_ADC0		IRQ_SPI(105)
+#define EXYNOS4_IRQ_PEN0		IRQ_SPI(106)
+#define EXYNOS4_IRQ_ADC1		IRQ_SPI(107)
+#define EXYNOS4_IRQ_PEN1		IRQ_SPI(108)
+#define EXYNOS4_IRQ_KEYPAD		IRQ_SPI(109)
+#define EXYNOS4_IRQ_PMU			IRQ_SPI(110)
+#define EXYNOS4_IRQ_GPS			IRQ_SPI(111)
+#define EXYNOS4_IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
+#define EXYNOS4_IRQ_SLIMBUS		IRQ_SPI(113)
+
+#define EXYNOS4_IRQ_TSI			IRQ_SPI(115)
+#define EXYNOS4_IRQ_SATA		IRQ_SPI(116)
+
+#define EXYNOS4_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
+#define EXYNOS4_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
+#define EXYNOS4_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
+#define EXYNOS4_IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
+
+#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
+#define EXYNOS4_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
+#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0	COMBINER_IRQ(5, 2)
+#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0	COMBINER_IRQ(5, 3)
+#define EXYNOS4_IRQ_SYSMMU_TV_M0_0	COMBINER_IRQ(5, 4)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0	COMBINER_IRQ(5, 5)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
+#define EXYNOS4_IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
+
+#define EXYNOS4_IRQ_FIMD0_FIFO		COMBINER_IRQ(11, 0)
+#define EXYNOS4_IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
+#define EXYNOS4_IRQ_FIMD0_SYSTEM	COMBINER_IRQ(11, 2)
+
+#define EXYNOS4_MAX_COMBINER_NR		16
+
+#define EXYNOS4_IRQ_GPIO1_NR_GROUPS	16
+#define EXYNOS4_IRQ_GPIO2_NR_GROUPS	9
+
+/*
+ * For Compatibility:
+ * the default is for EXYNOS4, and
+ * for exynos5, should be re-mapped at function
+ */
+
+#define IRQ_TIMER0_VIC			EXYNOS4_IRQ_TIMER0_VIC
+#define IRQ_TIMER1_VIC			EXYNOS4_IRQ_TIMER1_VIC
+#define IRQ_TIMER2_VIC			EXYNOS4_IRQ_TIMER2_VIC
+#define IRQ_TIMER3_VIC			EXYNOS4_IRQ_TIMER3_VIC
+#define IRQ_TIMER4_VIC			EXYNOS4_IRQ_TIMER4_VIC
+
+#define IRQ_WDT				EXYNOS4_IRQ_WDT
+#define IRQ_RTC_ALARM			EXYNOS4_IRQ_RTC_ALARM
+#define IRQ_RTC_TIC			EXYNOS4_IRQ_RTC_TIC
+#define IRQ_GPIO_XB			EXYNOS4_IRQ_GPIO_XB
+#define IRQ_GPIO_XA			EXYNOS4_IRQ_GPIO_XA
+
+#define IRQ_IIC				EXYNOS4_IRQ_IIC
+#define IRQ_IIC1			EXYNOS4_IRQ_IIC1
+#define IRQ_IIC3			EXYNOS4_IRQ_IIC3
+#define IRQ_IIC5			EXYNOS4_IRQ_IIC5
+#define IRQ_IIC7			EXYNOS4_IRQ_IIC7
+
+#define IRQ_USB_HOST			EXYNOS4_IRQ_USB_HOST
+
+#define IRQ_HSMMC0			EXYNOS4_IRQ_HSMMC0
+#define IRQ_HSMMC1			EXYNOS4_IRQ_HSMMC1
+#define IRQ_HSMMC2			EXYNOS4_IRQ_HSMMC2
+#define IRQ_HSMMC3			EXYNOS4_IRQ_HSMMC3
+
+#define IRQ_MIPI_CSIS0			EXYNOS4_IRQ_MIPI_CSIS0
+
+#define IRQ_ONENAND_AUDI		EXYNOS4_IRQ_ONENAND_AUDI
+
+#define IRQ_FIMC0			EXYNOS4_IRQ_FIMC0
+#define IRQ_FIMC1			EXYNOS4_IRQ_FIMC1
+#define IRQ_FIMC2			EXYNOS4_IRQ_FIMC2
+#define IRQ_FIMC3			EXYNOS4_IRQ_FIMC3
+
+#define IRQ_MIXER			EXYNOS4_IRQ_MIXER
+#define IRQ_HDMI			EXYNOS4_IRQ_HDMI
+#define IRQ_IIC_HDMIPHY			EXYNOS4_IRQ_IIC_HDMIPHY
+#define IRQ_MFC				EXYNOS4_IRQ_MFC
+#define IRQ_SDO				EXYNOS4_IRQ_SDO
+
+#define IRQ_ADC				EXYNOS4_IRQ_ADC0
+#define IRQ_TC				EXYNOS4_IRQ_PEN0
+
+#define IRQ_KEYPAD			EXYNOS4_IRQ_KEYPAD
+#define IRQ_PMU				EXYNOS4_IRQ_PMU
+
+#define IRQ_SYSMMU_MDMA0_0		EXYNOS4_IRQ_SYSMMU_MDMA0_0
+#define IRQ_SYSMMU_SSS_0                EXYNOS4_IRQ_SYSMMU_SSS_0
+#define IRQ_SYSMMU_FIMC0_0              EXYNOS4_IRQ_SYSMMU_FIMC0_0
+#define IRQ_SYSMMU_FIMC1_0              EXYNOS4_IRQ_SYSMMU_FIMC1_0
+#define IRQ_SYSMMU_FIMC2_0              EXYNOS4_IRQ_SYSMMU_FIMC2_0
+#define IRQ_SYSMMU_FIMC3_0              EXYNOS4_IRQ_SYSMMU_FIMC3_0
+#define IRQ_SYSMMU_JPEG_0               EXYNOS4_IRQ_SYSMMU_JPEG_0
+#define IRQ_SYSMMU_2D_0                 EXYNOS4_IRQ_SYSMMU_2D_0
 
+#define IRQ_SYSMMU_ROTATOR_0            EXYNOS4_IRQ_SYSMMU_ROTATOR_0
+#define IRQ_SYSMMU_MDMA1_0              EXYNOS4_IRQ_SYSMMU_MDMA1_0
+#define IRQ_SYSMMU_LCD0_M0_0            EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
+#define IRQ_SYSMMU_LCD1_M1_0            EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
+#define IRQ_SYSMMU_TV_M0_0              EXYNOS4_IRQ_SYSMMU_TV_M0_0
+#define IRQ_SYSMMU_MFC_M0_0             EXYNOS4_IRQ_SYSMMU_MFC_M0_0
+#define IRQ_SYSMMU_MFC_M1_0             EXYNOS4_IRQ_SYSMMU_MFC_M1_0
+#define IRQ_SYSMMU_PCIE_0               EXYNOS4_IRQ_SYSMMU_PCIE_0
+
+#define IRQ_FIMD0_FIFO			EXYNOS4_IRQ_FIMD0_FIFO
+#define IRQ_FIMD0_VSYNC			EXYNOS4_IRQ_FIMD0_VSYNC
+#define IRQ_FIMD0_SYSTEM		EXYNOS4_IRQ_FIMD0_SYSTEM
+
+#define IRQ_GPIO1_NR_GROUPS		EXYNOS4_IRQ_GPIO1_NR_GROUPS
+#define IRQ_GPIO2_NR_GROUPS		EXYNOS4_IRQ_GPIO2_NR_GROUPS
+
+/* For EXYNOS5 SoCs */
+
+#define EXYNOS5_IRQ_MDMA0		IRQ_SPI(33)
+#define EXYNOS5_IRQ_PDMA0		IRQ_SPI(34)
+#define EXYNOS5_IRQ_PDMA1		IRQ_SPI(35)
+#define EXYNOS5_IRQ_TIMER0_VIC		IRQ_SPI(36)
+#define EXYNOS5_IRQ_TIMER1_VIC		IRQ_SPI(37)
+#define EXYNOS5_IRQ_TIMER2_VIC		IRQ_SPI(38)
+#define EXYNOS5_IRQ_TIMER3_VIC		IRQ_SPI(39)
+#define EXYNOS5_IRQ_TIMER4_VIC		IRQ_SPI(40)
+#define EXYNOS5_IRQ_RTIC		IRQ_SPI(41)
+#define EXYNOS5_IRQ_WDT			IRQ_SPI(42)
+#define EXYNOS5_IRQ_RTC_ALARM		IRQ_SPI(43)
+#define EXYNOS5_IRQ_RTC_TIC		IRQ_SPI(44)
+#define EXYNOS5_IRQ_GPIO_XB		IRQ_SPI(45)
+#define EXYNOS5_IRQ_GPIO_XA		IRQ_SPI(46)
+#define EXYNOS5_IRQ_GPIO		IRQ_SPI(47)
+#define EXYNOS5_IRQ_IEM_IEC		IRQ_SPI(48)
+#define EXYNOS5_IRQ_IEM_APC		IRQ_SPI(49)
+#define EXYNOS5_IRQ_GPIO_C2C		IRQ_SPI(50)
 #define EXYNOS5_IRQ_UART0		IRQ_SPI(51)
 #define EXYNOS5_IRQ_UART1		IRQ_SPI(52)
 #define EXYNOS5_IRQ_UART2		IRQ_SPI(53)
 #define EXYNOS5_IRQ_UART3		IRQ_SPI(54)
 #define EXYNOS5_IRQ_UART4		IRQ_SPI(55)
+#define EXYNOS5_IRQ_IIC			IRQ_SPI(56)
+#define EXYNOS5_IRQ_IIC1		IRQ_SPI(57)
+#define EXYNOS5_IRQ_IIC2		IRQ_SPI(58)
+#define EXYNOS5_IRQ_IIC3		IRQ_SPI(59)
+#define EXYNOS5_IRQ_IIC4		IRQ_SPI(60)
+#define EXYNOS5_IRQ_IIC5		IRQ_SPI(61)
+#define EXYNOS5_IRQ_IIC6		IRQ_SPI(62)
+#define EXYNOS5_IRQ_IIC7		IRQ_SPI(63)
+#define EXYNOS5_IRQ_IIC_HDMIPHY		IRQ_SPI(64)
+#define EXYNOS5_IRQ_TMU			IRQ_SPI(65)
+#define EXYNOS5_IRQ_FIQ_0		IRQ_SPI(66)
+#define EXYNOS5_IRQ_FIQ_1		IRQ_SPI(67)
+#define EXYNOS5_IRQ_SPI0		IRQ_SPI(68)
+#define EXYNOS5_IRQ_SPI1		IRQ_SPI(69)
+#define EXYNOS5_IRQ_SPI2		IRQ_SPI(70)
+#define EXYNOS5_IRQ_USB_HOST		IRQ_SPI(71)
+#define EXYNOS5_IRQ_USB3_DRD		IRQ_SPI(72)
+#define EXYNOS5_IRQ_MIPI_HSI		IRQ_SPI(73)
+#define EXYNOS5_IRQ_USB_HSOTG		IRQ_SPI(74)
+#define EXYNOS5_IRQ_HSMMC0		IRQ_SPI(75)
+#define EXYNOS5_IRQ_HSMMC1		IRQ_SPI(76)
+#define EXYNOS5_IRQ_HSMMC2		IRQ_SPI(77)
+#define EXYNOS5_IRQ_HSMMC3		IRQ_SPI(78)
+#define EXYNOS5_IRQ_MIPICSI0		IRQ_SPI(79)
+#define EXYNOS5_IRQ_MIPICSI1		IRQ_SPI(80)
+#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT	IRQ_SPI(81)
+#define EXYNOS5_IRQ_MIPIDSI0		IRQ_SPI(82)
+#define EXYNOS5_IRQ_ROTATOR		IRQ_SPI(84)
+#define EXYNOS5_IRQ_GSC0		IRQ_SPI(85)
+#define EXYNOS5_IRQ_GSC1		IRQ_SPI(86)
+#define EXYNOS5_IRQ_GSC2		IRQ_SPI(87)
+#define EXYNOS5_IRQ_GSC3		IRQ_SPI(88)
+#define EXYNOS5_IRQ_JPEG		IRQ_SPI(89)
+#define EXYNOS5_IRQ_EFNFCON_DMA		IRQ_SPI(90)
+#define EXYNOS5_IRQ_2D			IRQ_SPI(91)
+#define EXYNOS5_IRQ_SFMC0		IRQ_SPI(92)
+#define EXYNOS5_IRQ_SFMC1		IRQ_SPI(93)
+#define EXYNOS5_IRQ_MIXER		IRQ_SPI(94)
+#define EXYNOS5_IRQ_HDMI		IRQ_SPI(95)
+#define EXYNOS5_IRQ_MFC			IRQ_SPI(96)
+#define EXYNOS5_IRQ_AUDIO_SS		IRQ_SPI(97)
+#define EXYNOS5_IRQ_I2S0		IRQ_SPI(98)
+#define EXYNOS5_IRQ_I2S1		IRQ_SPI(99)
+#define EXYNOS5_IRQ_I2S2		IRQ_SPI(100)
+#define EXYNOS5_IRQ_AC97		IRQ_SPI(101)
+#define EXYNOS5_IRQ_PCM0		IRQ_SPI(102)
+#define EXYNOS5_IRQ_PCM1		IRQ_SPI(103)
+#define EXYNOS5_IRQ_PCM2		IRQ_SPI(104)
+#define EXYNOS5_IRQ_SPDIF		IRQ_SPI(105)
+#define EXYNOS5_IRQ_ADC0		IRQ_SPI(106)
+
+#define EXYNOS5_IRQ_SATA_PHY		IRQ_SPI(108)
+#define EXYNOS5_IRQ_SATA_PMEMREQ	IRQ_SPI(109)
+#define EXYNOS5_IRQ_CAM_C		IRQ_SPI(110)
+#define EXYNOS5_IRQ_EAGLE_PMU		IRQ_SPI(111)
+#define EXYNOS5_IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
+#define EXYNOS5_IRQ_DP1_INTP1		IRQ_SPI(113)
+#define EXYNOS5_IRQ_CEC			IRQ_SPI(114)
+#define EXYNOS5_IRQ_SATA		IRQ_SPI(115)
+#define EXYNOS5_IRQ_NFCON		IRQ_SPI(116)
+
+#define EXYNOS5_IRQ_MMC44		IRQ_SPI(123)
+#define EXYNOS5_IRQ_MDMA1		IRQ_SPI(124)
+#define EXYNOS5_IRQ_FIMC_LITE0		IRQ_SPI(125)
+#define EXYNOS5_IRQ_FIMC_LITE1		IRQ_SPI(126)
+#define EXYNOS5_IRQ_RP_TIMER		IRQ_SPI(127)
+
+#define EXYNOS5_IRQ_PMU			COMBINER_IRQ(1, 2)
+#define EXYNOS5_IRQ_PMU_CPU1		COMBINER_IRQ(1, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_GSC0_0	COMBINER_IRQ(2, 0)
+#define EXYNOS5_IRQ_SYSMMU_GSC0_1	COMBINER_IRQ(2, 1)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_0	COMBINER_IRQ(2, 2)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_1	COMBINER_IRQ(2, 3)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_0	COMBINER_IRQ(2, 4)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_1	COMBINER_IRQ(2, 5)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_0	COMBINER_IRQ(2, 6)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_1	COMBINER_IRQ(2, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(3, 2)
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_1	COMBINER_IRQ(3, 3)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(3, 4)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_1	COMBINER_IRQ(3, 5)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0	COMBINER_IRQ(3, 6)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1	COMBINER_IRQ(3, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(4, 0)
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1	COMBINER_IRQ(4, 1)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 2)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_1	COMBINER_IRQ(4, 3)
+
+#define EXYNOS5_IRQ_SYSMMU_FD_0		COMBINER_IRQ(5, 0)
+#define EXYNOS5_IRQ_SYSMMU_FD_1		COMBINER_IRQ(5, 1)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0	COMBINER_IRQ(5, 2)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1	COMBINER_IRQ(5, 3)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_0	COMBINER_IRQ(5, 4)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_1	COMBINER_IRQ(5, 5)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_0	COMBINER_IRQ(5, 6)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_1	COMBINER_IRQ(5, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ARM_0	COMBINER_IRQ(6, 0)
+#define EXYNOS5_IRQ_SYSMMU_ARM_1	COMBINER_IRQ(6, 1)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_0	COMBINER_IRQ(6, 4)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_1	COMBINER_IRQ(6, 5)
+#define EXYNOS5_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(6, 6)
+#define EXYNOS5_IRQ_SYSMMU_SSS_1	COMBINER_IRQ(6, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(7, 0)
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_1	COMBINER_IRQ(7, 1)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(7, 2)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_1	COMBINER_IRQ(7, 3)
+#define EXYNOS5_IRQ_SYSMMU_TV_0		COMBINER_IRQ(7, 4)
+#define EXYNOS5_IRQ_SYSMMU_TV_1		COMBINER_IRQ(7, 5)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_0	COMBINER_IRQ(7, 6)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_1	COMBINER_IRQ(7, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(8, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_DIS1_0	COMBINER_IRQ(9, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS1_1	COMBINER_IRQ(9, 5)
+
+#define EXYNOS5_IRQ_DP			COMBINER_IRQ(10, 3)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_0	COMBINER_IRQ(10, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_1	COMBINER_IRQ(10, 5)
+#define EXYNOS5_IRQ_SYSMMU_ISP_0	COMBINER_IRQ(10, 6)
+#define EXYNOS5_IRQ_SYSMMU_ISP_1	COMBINER_IRQ(10, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ODC_0	COMBINER_IRQ(11, 0)
+#define EXYNOS5_IRQ_SYSMMU_ODC_1	COMBINER_IRQ(11, 1)
+#define EXYNOS5_IRQ_SYSMMU_DRC_0	COMBINER_IRQ(11, 6)
+#define EXYNOS5_IRQ_SYSMMU_DRC_1	COMBINER_IRQ(11, 7)
+
+#define EXYNOS5_IRQ_FIMD1_FIFO		COMBINER_IRQ(18, 4)
+#define EXYNOS5_IRQ_FIMD1_VSYNC		COMBINER_IRQ(18, 5)
+#define EXYNOS5_IRQ_FIMD1_SYSTEM	COMBINER_IRQ(18, 6)
+
+#define EXYNOS5_IRQ_EINT0		COMBINER_IRQ(23, 0)
+#define EXYNOS5_IRQ_MCT_L0		COMBINER_IRQ(23, 1)
+#define EXYNOS5_IRQ_MCT_L1		COMBINER_IRQ(23, 2)
+#define EXYNOS5_IRQ_MCT_G0		COMBINER_IRQ(23, 3)
+#define EXYNOS5_IRQ_MCT_G1		COMBINER_IRQ(23, 4)
+#define EXYNOS5_IRQ_MCT_G2		COMBINER_IRQ(23, 5)
+#define EXYNOS5_IRQ_MCT_G3		COMBINER_IRQ(23, 6)
+
+#define EXYNOS5_IRQ_EINT1		COMBINER_IRQ(24, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(24, 1)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_1	COMBINER_IRQ(24, 2)
+#define EXYNOS5_IRQ_SYSMMU_2D_0		COMBINER_IRQ(24, 5)
+#define EXYNOS5_IRQ_SYSMMU_2D_1		COMBINER_IRQ(24, 6)
+
+#define EXYNOS5_IRQ_EINT2		COMBINER_IRQ(25, 0)
+#define EXYNOS5_IRQ_EINT3		COMBINER_IRQ(25, 1)
+
+#define EXYNOS5_IRQ_EINT4		COMBINER_IRQ(26, 0)
+#define EXYNOS5_IRQ_EINT5		COMBINER_IRQ(26, 1)
+
+#define EXYNOS5_IRQ_EINT6		COMBINER_IRQ(27, 0)
+#define EXYNOS5_IRQ_EINT7		COMBINER_IRQ(27, 1)
+
+#define EXYNOS5_IRQ_EINT8		COMBINER_IRQ(28, 0)
+#define EXYNOS5_IRQ_EINT9		COMBINER_IRQ(28, 1)
+
+#define EXYNOS5_IRQ_EINT10		COMBINER_IRQ(29, 0)
+#define EXYNOS5_IRQ_EINT11		COMBINER_IRQ(29, 1)
+
+#define EXYNOS5_IRQ_EINT12		COMBINER_IRQ(30, 0)
+#define EXYNOS5_IRQ_EINT13		COMBINER_IRQ(30, 1)
+
+#define EXYNOS5_IRQ_EINT14		COMBINER_IRQ(31, 0)
+#define EXYNOS5_IRQ_EINT15		COMBINER_IRQ(31, 1)
+
+#define EXYNOS5_MAX_COMBINER_NR		32
+
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS	13
+#define EXYNOS5_IRQ_GPIO2_NR_GROUPS	9
+#define EXYNOS5_IRQ_GPIO3_NR_GROUPS	5
+#define EXYNOS5_IRQ_GPIO4_NR_GROUPS	1
+
+#define MAX_COMBINER_NR			(EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
+					EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
+
+#define S5P_EINT_BASE1			COMBINER_IRQ(MAX_COMBINER_NR, 0)
+#define S5P_EINT_BASE2			(S5P_EINT_BASE1 + 16)
+#define S5P_GPIOINT_BASE		(S5P_EINT_BASE1 + 32)
+#define IRQ_GPIO_END			(S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
+#define IRQ_TIMER_BASE			(IRQ_GPIO_END + 64)
+
+/* Set the default NR_IRQS */
+
+#define NR_IRQS				(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
 
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 85b5527..1016515 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -258,7 +258,10 @@ static void exynos4_clockevent_init(void)
 	mct_comp_device.cpumask = cpumask_of(0);
 	clockevents_register_device(&mct_comp_device);
 
-	setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
+	if (soc_is_exynos5250())
+		setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
+	else
+		setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
 }
 
 #ifdef CONFIG_LOCAL_TIMERS
@@ -406,16 +409,16 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
 	if (mct_int_type == MCT_INT_SPI) {
 		if (cpu == 0) {
 			mct_tick0_event_irq.dev_id = mevt;
-			evt->irq = IRQ_MCT_L0;
-			setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+			evt->irq = EXYNOS4_IRQ_MCT_L0;
+			setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
 		} else {
 			mct_tick1_event_irq.dev_id = mevt;
-			evt->irq = IRQ_MCT_L1;
-			setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
-			irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+			evt->irq = EXYNOS4_IRQ_MCT_L1;
+			setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
+			irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
 		}
 	} else {
-		enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
+		enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
 	}
 }
 
@@ -437,7 +440,7 @@ void local_timer_stop(struct clock_event_device *evt)
 		else
 			remove_irq(evt->irq, &mct_tick1_event_irq);
 	else
-		disable_percpu_irq(IRQ_MCT_LOCALTIMER);
+		disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
 }
 #endif /* CONFIG_LOCAL_TIMERS */
 
@@ -452,11 +455,11 @@ static void __init exynos4_timer_resources(void)
 	if (mct_int_type == MCT_INT_PPI) {
 		int err;
 
-		err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
+		err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
 					 exynos4_mct_tick_isr, "MCT",
 					 &percpu_mct_tick);
 		WARN(err, "MCT: can't request IRQ %d (%d)\n",
-		     IRQ_MCT_LOCALTIMER, err);
+		     EXYNOS_IRQ_MCT_LOCALTIMER, err);
 	}
 #endif /* CONFIG_LOCAL_TIMERS */
 }
diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
index 327acb3..d1bfeca 100644
--- a/arch/arm/plat-s5p/irq-pm.c
+++ b/arch/arm/plat-s5p/irq-pm.c
@@ -39,19 +39,32 @@ unsigned long s3c_irqwake_eintallow	= 0xffffffffL;
 int s3c_irq_wake(struct irq_data *data, unsigned int state)
 {
 	unsigned long irqbit;
+	unsigned int irq_rtc_tic, irq_rtc_alarm;
+
+#ifdef CONFIG_ARCH_EXYNOS
+	if (soc_is_exynos5250()) {
+		irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC;
+		irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM;
+	} else {
+		irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC;
+		irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM;
+	}
+#else
+	irq_rtc_tic = IRQ_RTC_TIC;
+	irq_rtc_alarm = IRQ_RTC_ALARM;
+#endif
+
+	if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
+		irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
 
-	switch (data->irq) {
-	case IRQ_RTC_TIC:
-	case IRQ_RTC_ALARM:
-		irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
 		if (!state)
 			s3c_irqwake_intmask |= irqbit;
 		else
 			s3c_irqwake_intmask &= ~irqbit;
-		break;
-	default:
+	} else {
 		return -ENOENT;
 	}
+
 	return 0;
 }
 
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index 51583cd..f980cf3 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 
 #include <mach/map.h>
+#include <plat/cpu.h>
 #include <plat/irq-vic-timer.h>
 #include <plat/regs-timer.h>
 
@@ -57,6 +58,21 @@ void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
 	struct irq_chip_type *ct;
 	unsigned int i;
 
+#ifdef CONFIG_ARCH_EXYNOS
+	if (soc_is_exynos5250()) {
+		pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
+		pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
+		pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
+		pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
+		pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
+	} else {
+		pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
+		pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
+		pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
+		pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
+		pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
+	}
+#endif
 	s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
 					 S3C64XX_TINT_CSTAT, handle_level_irq);
 
-- 
1.7.4.4



From kgene.kim at samsung.com  Tue Mar 13 11:30:41 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:41 -0700
Subject: [PATCH v3 10/12] ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5
 SoCs
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-11-git-send-email-kgene.kim@samsung.com>

This patch adds CONFIG_ARCH_EXYNOS5 and CONFIG_SOC_EXYNOS5250
for supporting EXYNOS5250 SoC and allows supporting EXYNOS4
and EXYNOS5 together.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/Kconfig  |   17 ++++++++++++-----
 arch/arm/mach-exynos/Makefile |    1 +
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5d602f6..31ef33f 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -11,10 +11,6 @@ if ARCH_EXYNOS
 
 menu "SAMSUNG EXYNOS SoCs Support"
 
-choice
-	prompt "EXYNOS System Type"
-	default ARCH_EXYNOS4
-
 config ARCH_EXYNOS4
 	bool "SAMSUNG EXYNOS4"
 	select HAVE_SMP
@@ -22,7 +18,11 @@ config ARCH_EXYNOS4
 	help
 	  Samsung EXYNOS4 SoCs based systems
 
-endchoice
+config ARCH_EXYNOS5
+	bool "SAMSUNG EXYNOS5"
+	select HAVE_SMP
+	help
+	  Samsung EXYNOS5 (Cortex-A15) SoC based systems
 
 comment "EXYNOS SoCs"
 
@@ -53,6 +53,13 @@ config SOC_EXYNOS4412
 	help
 	  Enable EXYNOS4412 SoC support
 
+config SOC_EXYNOS5250
+	bool "SAMSUNG EXYNOS5250"
+	default y
+	depends on ARCH_EXYNOS5
+	help
+	  Enable EXYNOS5250 SoC support
+
 config EXYNOS4_MCT
 	bool
 	default y
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index f8a3770..7214092 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -14,6 +14,7 @@ obj-				:=
 
 obj-$(CONFIG_ARCH_EXYNOS)	+= common.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clock-exynos4.o
+obj-$(CONFIG_ARCH_EXYNOS5)	+= clock-exynos5.o
 obj-$(CONFIG_CPU_EXYNOS4210)	+= clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)	+= clock-exynos4212.o
 
-- 
1.7.4.4



From kgene.kim at samsung.com  Tue Mar 13 11:30:33 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:33 -0700
Subject: [PATCH v3 02/12] ARM: EXYNOS: use exynos_init_uarts() instead of
 exynos4_init_uarts()
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-3-git-send-email-kgene.kim@samsung.com>

Since exynos4_init_uarts() can be used for EXYNOS5 SoCs,
this patch changes the name of function to exynos_init_uarts().

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/common.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index a1f8a99..02eed29 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,7 +52,7 @@ static const char name_exynos4412[] = "EXYNOS4412";
 
 static void exynos4_map_io(void);
 static void exynos4_init_clocks(int xtal);
-static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
 static struct cpu_table cpu_ids[] __initdata = {
@@ -61,7 +61,7 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.idmask		= EXYNOS4_CPU_MASK,
 		.map_io		= exynos4_map_io,
 		.init_clocks	= exynos4_init_clocks,
-		.init_uarts	= exynos4_init_uarts,
+		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4210,
 	}, {
@@ -69,7 +69,7 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.idmask		= EXYNOS4_CPU_MASK,
 		.map_io		= exynos4_map_io,
 		.init_clocks	= exynos4_init_clocks,
-		.init_uarts	= exynos4_init_uarts,
+		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4212,
 	}, {
@@ -77,7 +77,7 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.idmask		= EXYNOS4_CPU_MASK,
 		.map_io		= exynos4_map_io,
 		.init_clocks	= exynos4_init_clocks,
-		.init_uarts	= exynos4_init_uarts,
+		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4412,
 	},
@@ -469,7 +469,7 @@ static int __init exynos_init(void)
 
 /* uart registration process */
 
-static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
 	struct s3c2410_uartcfg *tcfg = cfg;
 	u32 ucnt;
-- 
1.7.4.4



From kgene.kim at samsung.com  Tue Mar 13 11:30:36 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:36 -0700
Subject: [PATCH v3 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-6-git-send-email-kgene.kim@samsung.com>

Actually, the base address of uart is different between EXYNOS4
and EXYNOS5 and this patch enables to support uart for EXYNOS4
and EXYNOS5 SoCs at runtime.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/Makefile                   |    1 +
 arch/arm/mach-exynos/common.c                   |    5 +-
 arch/arm/mach-exynos/dev-uart.c                 |   78 +++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/debug-macro.S |    9 ++-
 arch/arm/mach-exynos/include/mach/irqs.h        |   12 ++++
 arch/arm/mach-exynos/include/mach/map.h         |   20 +++---
 arch/arm/mach-exynos/include/mach/uncompress.h  |   17 ++++--
 arch/arm/plat-s5p/Kconfig                       |    4 +
 arch/arm/plat-s5p/Makefile                      |    3 +-
 arch/arm/plat-samsung/include/plat/devs.h       |    2 +
 arch/arm/plat-samsung/include/plat/uncompress.h |    2 +
 11 files changed, 135 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/mach-exynos/dev-uart.c

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 2117f02..f8a3770 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o
 
 # device support
 
+obj-y					+= dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_PD)		+= dev-pd.o
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 02eed29..4a82cf0 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -477,7 +477,10 @@ static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 	for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 		tcfg->has_fracval = 1;
 
-	s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
+	if (soc_is_exynos5250())
+		s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
+	else
+		s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 }
 
 static DEFINE_SPINLOCK(eint_lock);
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
new file mode 100644
index 0000000..2e85c02
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Base EXYNOS UART resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+#define EXYNOS_UART_RESOURCE(_series, _nr)	\
+static struct resource exynos##_series##_uart##_nr##_resource[] = {	\
+	[0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART),	\
+	[1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr),	\
+};
+
+EXYNOS_UART_RESOURCE(4, 0)
+EXYNOS_UART_RESOURCE(4, 1)
+EXYNOS_UART_RESOURCE(4, 2)
+EXYNOS_UART_RESOURCE(4, 3)
+
+struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
+	[0] = {
+		.resources	= exynos4_uart0_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart0_resource),
+	},
+	[1] = {
+		.resources	= exynos4_uart1_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart1_resource),
+	},
+	[2] = {
+		.resources	= exynos4_uart2_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart2_resource),
+	},
+	[3] = {
+		.resources	= exynos4_uart3_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart3_resource),
+	},
+};
+
+EXYNOS_UART_RESOURCE(5, 0)
+EXYNOS_UART_RESOURCE(5, 1)
+EXYNOS_UART_RESOURCE(5, 2)
+EXYNOS_UART_RESOURCE(5, 3)
+
+struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
+	[0] = {
+		.resources	= exynos5_uart0_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart0_resource),
+	},
+	[1] = {
+		.resources	= exynos5_uart1_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart0_resource),
+	},
+	[2] = {
+		.resources	= exynos5_uart2_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart2_resource),
+	},
+	[3] = {
+		.resources	= exynos5_uart3_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart3_resource),
+	},
+};
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
index 6cacf16..6c857ff 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -21,8 +21,13 @@
 	 */
 
 	.macro addruart, rp, rv, tmp
-		ldr	\rp, = S3C_PA_UART
-		ldr	\rv, = S3C_VA_UART
+		mov	\rp, #0x10000000
+		ldr	\rp, [\rp, #0x0]
+		and	\rp, \rp, #0xf00000
+		teq	\rp, #0x500000		@@ EXYNOS5
+		ldreq	\rp, =EXYNOS5_PA_UART
+		movne	\rp, #EXYNOS4_PA_UART	@@ EXYNOS4
+		ldr	\rv, =S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
 		add	\rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
 		add	\rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index f77bce0..e27e0f9 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -171,4 +171,16 @@
 /* Set the default NR_IRQS */
 #define NR_IRQS			(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
 
+#define EXYNOS4_IRQ_UART0		IRQ_SPI(52)
+#define EXYNOS4_IRQ_UART1		IRQ_SPI(53)
+#define EXYNOS4_IRQ_UART2		IRQ_SPI(54)
+#define EXYNOS4_IRQ_UART3		IRQ_SPI(55)
+#define EXYNOS4_IRQ_UART4		IRQ_SPI(56)
+
+#define EXYNOS5_IRQ_UART0		IRQ_SPI(51)
+#define EXYNOS5_IRQ_UART1		IRQ_SPI(52)
+#define EXYNOS5_IRQ_UART2		IRQ_SPI(53)
+#define EXYNOS5_IRQ_UART3		IRQ_SPI(54)
+#define EXYNOS5_IRQ_UART4		IRQ_SPI(55)
+
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c754a22..e8a7801 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -152,7 +152,6 @@
 #define S3C_PA_IIC7			EXYNOS4_PA_IIC(7)
 #define S3C_PA_RTC			EXYNOS4_PA_RTC
 #define S3C_PA_WDT			EXYNOS4_PA_WATCHDOG
-#define S3C_PA_UART			EXYNOS4_PA_UART
 #define S3C_PA_SPI0			EXYNOS4_PA_SPI0
 #define S3C_PA_SPI1			EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2			EXYNOS4_PA_SPI2
@@ -181,15 +180,18 @@
 
 /* Compatibility UART */
 
-#define S3C_VA_UARTx(x)			(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define EXYNOS4_PA_UART0		0x13800000
+#define EXYNOS4_PA_UART1		0x13810000
+#define EXYNOS4_PA_UART2		0x13820000
+#define EXYNOS4_PA_UART3		0x13830000
+#define EXYNOS4_SZ_UART			SZ_256
 
-#define S5P_PA_UART(x)			(EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0			S5P_PA_UART(0)
-#define S5P_PA_UART1			S5P_PA_UART(1)
-#define S5P_PA_UART2			S5P_PA_UART(2)
-#define S5P_PA_UART3			S5P_PA_UART(3)
-#define S5P_PA_UART4			S5P_PA_UART(4)
+#define EXYNOS5_PA_UART0		0x12C00000
+#define EXYNOS5_PA_UART1		0x12C10000
+#define EXYNOS5_PA_UART2		0x12C20000
+#define EXYNOS5_PA_UART3		0x12C30000
+#define EXYNOS5_SZ_UART			SZ_256
 
-#define S5P_SZ_UART			SZ_256
+#define S3C_VA_UARTx(x)			(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 21d97bc..493f4f3 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * EXYNOS4 - uncompress code
+ * EXYNOS - uncompress code
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,12 +12,20 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H __FILE__
 
+#include <asm/mach-types.h>
+
 #include <mach/map.h>
+
+volatile u8 *uart_base;
+
 #include <plat/uncompress.h>
 
 static void arch_detect_cpu(void)
 {
-	/* we do not need to do any cpu detection here at the moment. */
+	if (machine_is_smdk5250())
+		uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+	else
+		uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 
 	/*
 	 * For preventing FIFO overrun or infinite loop of UART console,
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 8167ce6..10e235cc7 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -40,6 +40,10 @@ config S5P_HRT
 	help
 	  Use the High Resolution timer support
 
+config S5P_DEV_UART
+	def_bool y
+	depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
+
 config S5P_PM
 	bool
 	help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 30d8c30..4bd8241 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -12,7 +12,6 @@ obj-				:=
 
 # Core files
 
-obj-y				+= dev-uart.o
 obj-y				+= clock.o
 obj-y				+= irq.o
 obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
@@ -23,5 +22,7 @@ obj-$(CONFIG_S5P_SLEEP)		+= sleep.o
 obj-$(CONFIG_S5P_HRT) 		+= s5p-time.o
 
 # devices
+
+obj-$(CONFIG_S5P_DEV_UART)	+= dev-uart.o
 obj-$(CONFIG_S5P_DEV_MFC)	+= dev-mfc.o
 obj-$(CONFIG_S5P_SETUP_MIPIPHY)	+= setup-mipiphy.o
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 4214ea0..32cc67e 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -26,6 +26,8 @@ struct s3c24xx_uart_resources {
 extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
 extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
 extern struct s3c24xx_uart_resources s5p_uart_resources[];
+extern struct s3c24xx_uart_resources exynos4_uart_resources[];
+extern struct s3c24xx_uart_resources exynos5_uart_resources[];
 
 extern struct platform_device *s3c24xx_uart_devs[];
 extern struct platform_device *s3c24xx_uart_src[];
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index ee48e12..7e068d1 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -37,7 +37,9 @@ static void arch_detect_cpu(void);
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX	 (14)
 
+#ifdef S3C_PA_UART
 #define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
+#endif
 
 static __inline__ void
 uart_wr(unsigned int reg, unsigned int val)
-- 
1.7.4.4



From kgene.kim at samsung.com  Tue Mar 13 11:30:35 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 08:30:35 -0700
Subject: [PATCH v3 04/12] ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331652643-12626-5-git-send-email-kgene.kim@samsung.com>

In all of Samsung platform, the setup-i2c0.c file for I2C channel 0
is always compiled. So when supporting new SoC,it should be updated
for it. Since EXYNOS5 GPIO will be supported after this, there is no
setup gpio in there now. It will be implemented with that, of course.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/Makefile     |    2 +-
 arch/arm/mach-exynos/setup-i2c0.c |    9 ++++++---
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 995e7cc..2117f02 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -52,7 +52,7 @@ obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
 obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o
 
-obj-$(CONFIG_ARCH_EXYNOS4)		+= setup-i2c0.o
+obj-$(CONFIG_ARCH_EXYNOS)		+= setup-i2c0.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)	+= setup-fimc.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)	+= setup-fimd0.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C1)	+= setup-i2c1.o
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index d395bd1..b90d94c 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/setup-i2c0.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com/
  *
  * I2C0 GPIO configuration.
@@ -18,9 +16,14 @@ struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
 #include <plat/iic.h>
 #include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
+	if (soc_is_exynos5250())
+		/* will be implemented with gpio function */
+		return;
+
 	s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
 			      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
-- 
1.7.4.4



From balajitk at ti.com  Tue Mar 13 11:43:30 2012
From: balajitk at ti.com (T Krishnamoorthy, Balaji)
Date: Tue, 13 Mar 2012 21:13:30 +0530
Subject: [PATCH v2 0/4] omap hsmmc device tree support
In-Reply-To: <1331564560-23276-1-git-send-email-rnayak@ti.com>
References: <1331564560-23276-1-git-send-email-rnayak@ti.com>
Message-ID: <CANrkHUb3Aypm7H44-6efiEoka_WO20hW1vMy-wBV1RzkRPt_UQ@mail.gmail.com>

On Mon, Mar 12, 2012 at 8:32 PM, Rajendra Nayak <rnayak at ti.com> wrote:
> The series adds device tree support for OMAP hsmmc
> driver.
>
> Changes in V2:
> -1- Minor fixes based on comments from Grant.
> -2- Added a seperate compatible for omap3.
> -3- Added a new binding "ti,needs-special-reset"
> to handle some mmc modules which need special
> softreset sequence.
> -4- Updated board dts files with "status = disable;"
> for unused mmc modules.
>
> Rob,
> I retained your ack on patch 1 despite the additional
> binding that I added to handle the special softreset
> sequence. Let me know if you have any issues with it.
>
> Chris.
> Patch 1 and Patch 2 apply cleanly on mmc-next and can
> be taken in from the mmc tree after relevent acks from
> DT folks.
> Patch 3 and Patch 4 which update dts files, I plan to
> push via linux-omap/Tony's tree.
Hi Rajendra,

Tested this series on omap4sdp, so feel free to add
Tested-by: Balaji T K <balajitk at ti.com>

>
> The series is tested on omap4sdp (both external and emmc),
> omap4panda amd omap3beagle boards.
>
> Things to do:
> -1- Card detect isn't functional and needs twl4030 gpio
> to be DT converted.
> -2- pbias cell programming is missing and needs an OMAP
> control module driver.
>
> Rajendra Nayak (4):
> ?mmc: omap_hsmmc: Convert hsmmc driver to use device tree
> ?mmc: omap_hsmmc: Avoid a regulator voltage change with dt
> ?arm/dts: OMAP4: Add mmc controller nodes and board data
> ?arm/dts: OMAP3: Add mmc controller nodes and board data
>
> ?.../devicetree/bindings/mmc/ti-omap-hsmmc.txt ? ? ?| ? 33 +++++++
> ?arch/arm/boot/dts/omap3-beagle.dts ? ? ? ? ? ? ? ? | ? 14 +++
> ?arch/arm/boot/dts/omap3.dtsi ? ? ? ? ? ? ? ? ? ? ? | ? 16 ++++
> ?arch/arm/boot/dts/omap4-panda.dts ? ? ? ? ? ? ? ? ?| ? 22 +++++
> ?arch/arm/boot/dts/omap4-sdp.dts ? ? ? ? ? ? ? ? ? ?| ? 24 ++++++
> ?arch/arm/boot/dts/omap4.dtsi ? ? ? ? ? ? ? ? ? ? ? | ? 31 +++++++
> ?drivers/mmc/host/omap_hsmmc.c ? ? ? ? ? ? ? ? ? ? ?| ? 88 +++++++++++++++++++-
> ?7 files changed, 227 insertions(+), 1 deletions(-)
> ?create mode 100644 Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt


From sshtylyov at mvista.com  Tue Mar 13 13:10:41 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Tue, 13 Mar 2012 20:10:41 +0300
Subject: [PATCH] arm:da850: register musb device
In-Reply-To: <1331651015-32586-1-git-send-email-prakash.pm@ti.com>
References: <1331651015-32586-1-git-send-email-prakash.pm@ti.com>
Message-ID: <4F5F7F91.8010301@mvista.com>

On 03/13/2012 06:03 PM, Manjunathappa, Prakash wrote:

> Properly set up the OTG mode thru the CFGCHIP2 register, enable the
> USB0_DRVVBUS pin,

    I don't see where you are enabling it.

> and finally register the MUSB platform device.
>
> Signed-off-by: Ajay Kumar Gupta<ajay.gupta at ti.com>
> Signed-off-by: Manjunathappa, Prakash<prakash.pm at ti.com>
> ---
> Patche are on top below posted patches:
> http://www.spinics.net/lists/linux-usb/msg59656.html

>   arch/arm/mach-davinci/board-da850-evm.c |   12 ++++++++++++
>   arch/arm/mach-davinci/usb.c             |    9 +++++++++
>   2 files changed, 21 insertions(+), 0 deletions(-)

> diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
> index 178d178..539e12c 100644
> --- a/arch/arm/mach-davinci/board-da850-evm.c
> +++ b/arch/arm/mach-davinci/board-da850-evm.c
> @@ -787,6 +787,18 @@ static __init void da850_evm_usb_init(void)
>   	 */
>   	cfgchip2&= ~CFGCHIP2_USB1PHYCLKMUX;
>   	cfgchip2 |=  CFGCHIP2_USB2PHYCLKMUX;
> +	/*
> +	 * We have to override VBUS/ID signals when MUSB is configured into the
> +	 * host-only mode -- ID pin will float if no cable is connected, so the
> +	 * controller won't be able to drive VBUS thinking that it's a B-device.
> +	 * Otherwise, we want to use the OTG mode and enable VBUS comparators.
> +	 */
> +	cfgchip2 &= ~CFGCHIP2_OTGMODE;
> +#if CONFIG_USB_MUSB_DA8XX

    This #ifdef doesn't make sense. It will make driver always work in host mode.

> +	cfgchip2 |=  CFGCHIP2_FORCE_HOST;
> +#else
> +	cfgchip2 |=  CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;

    This is what you need to leave. The driver should always work in OTG mode now.

> +#endif
>
>   	__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
>
> diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
> index 25c3520..a941dc5 100644
> --- a/arch/arm/mach-davinci/usb.c
> +++ b/arch/arm/mach-davinci/usb.c
> @@ -284,6 +284,15 @@ void __init da8xx_board_usb_init(const short pins[],
>   		goto usb11_setup_fail;
>   	}
>
> +	/*
> +	 * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A),
> +	 * with the power on to power good time of 3 ms.
> +	 */
> +	ret = da8xx_register_usb20(1000, 3);
> +	if (ret)
> +		pr_warning("%s: USB 2.0 registration failed: %d\n",
> +			   __func__, ret);

    Er, why this code is moved there? And how will this work on DA830 -- try to 
register MUSB twice? Place this in the board file please where it belongs.

WBR, Sergei


From arnd at arndb.de  Tue Mar 13 12:13:10 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 16:13:10 +0000
Subject: [PATCH v3 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and
 EXYNOS5
In-Reply-To: <1331652643-12626-6-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <1331652643-12626-6-git-send-email-kgene.kim@samsung.com>
Message-ID: <201203131613.10620.arnd@arndb.de>

On Tuesday 13 March 2012, Kukjin Kim wrote:
> Actually, the base address of uart is different between EXYNOS4
> and EXYNOS5 and this patch enables to support uart for EXYNOS4
> and EXYNOS5 SoCs at runtime.

Can you explain why this patch is still needed? The exynos5250_dt_map_io
function does not call s3c24xx_init_uarts() at all, so it seems that most
of this patch just adds dead code that would only be needed for the non-dt
case.

	Arnd


From arnd at arndb.de  Tue Mar 13 12:15:49 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 16:15:49 +0000
Subject: [PATCH v3 09/12] ARM: EXYNOS: add support get_core_count() for
 EXYNOS5250
In-Reply-To: <1331652643-12626-10-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <1331652643-12626-10-git-send-email-kgene.kim@samsung.com>
Message-ID: <201203131615.49846.arnd@arndb.de>

On Tuesday 13 March 2012, Kukjin Kim wrote:
> The EXYNOS5250 has two Cortex-A15 cores and there's no
> need to call scu_enable() in platform_smp_prepare_cpus().
> 
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>

Can you explain this patch more? It only seems to make the
code less generic, but there is no indication if calling
the scu_get_core_count() function is actually wrong on
exynos5.

	Arnd

> diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
> index 0f2035a..36c3984 100644
> --- a/arch/arm/mach-exynos/platsmp.c
> +++ b/arch/arm/mach-exynos/platsmp.c
> @@ -166,7 +166,10 @@ void __init smp_init_cpus(void)
>         void __iomem *scu_base = scu_base_addr();
>         unsigned int i, ncores;
>  
> -       ncores = scu_base ? scu_get_core_count(scu_base) : 1;
> +       if (soc_is_exynos5250())
> +               ncores = 2;
> +       else
> +               ncores = scu_base ? scu_get_core_count(scu_base) : 1;
>  
>         /* sanity check */
>         if (ncores > nr_cpu_ids) {
> @@ -183,8 +186,8 @@ void __init smp_init_cpus(void)
>  
>  void __init platform_smp_prepare_cpus(unsigned int max_cpus)
>  {
> -
> -       scu_enable(scu_base_addr());
> +       if (!soc_is_exynos5250())
> +               scu_enable(scu_base_addr());
>  
>         /*
>          * Write the address of secondary startup into the



From arnd at arndb.de  Tue Mar 13 12:22:08 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 16:22:08 +0000
Subject: [PATCH v3 00/12] ARM: EXYNOS: add support new EXYNOS5250
In-Reply-To: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <201203131622.09048.arnd@arndb.de>

On Tuesday 13 March 2012, Kukjin Kim wrote:
> 
> This patch adds support EXYNOS5250 SoC which has two A15 cores
> can be used on mobile and tablet devices.

Looks basically ok to me. I've commented on patches 5 and 9 and
in both cases, I would either like to see the patch get dropped
or the changeset description expanded to give a good explanation
why the change is actually needed.

	Arnd


From khilman at ti.com  Tue Mar 13 12:27:21 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 13 Mar 2012 09:27:21 -0700
Subject: [PATCH v3 11/13] gpio/omap: fix dataout register overwrite in
 _set_gpio_dataout_*
In-Reply-To: <CAC83ZvLmaLOr4_eZZzKyP2=KvkG+LjHjeOwvxdQHhuiB8+2L0w@mail.gmail.com>
 (Tarun Kanti DebBarma's message of "Tue, 13 Mar 2012 12:22:28 +0530")
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-12-git-send-email-tarun.kanti@ti.com>
 <87y5r5wkmu.fsf@ti.com>
 <CAC83ZvJ5rjNJoSZW=j=DXQWKWGgr_Wqu8ukOubxKd7xuEQ4pzQ@mail.gmail.com>
 <CAC83Zv+CZOGnSpOJgfCgEv-eyWXZzV+_mmd37CBMKM6iMtEksQ@mail.gmail.com>
 <CAC83ZvLmaLOr4_eZZzKyP2=KvkG+LjHjeOwvxdQHhuiB8+2L0w@mail.gmail.com>
Message-ID: <8762e8v53q.fsf@ti.com>

"DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:

> On Tue, Mar 13, 2012 at 12:03 PM, DebBarma, Tarun Kanti
> <tarun.kanti at ti.com> wrote:
>> On Tue, Mar 13, 2012 at 11:33 AM, DebBarma, Tarun Kanti
>> <tarun.kanti at ti.com> wrote:
>>> On Tue, Mar 13, 2012 at 3:24 AM, Kevin Hilman <khilman at ti.com> wrote:
>>>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>>>>
>>>>> In the existing _set_gpio_dataout_*() implementation, the dataout
>>>>> register is overwritten every time the function is called. This is
>>>>> not intended behavior because that would end up one user of a GPIO
>>>>> line overwriting what is written by another. Fix this so that previous
>>>>> value is always preserved until explicitly changed by respective
>>>>> user/driver of the GPIO line.
>>>>>
>>>>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>>>>> ---
>>>>> ?drivers/gpio/gpio-omap.c | ? ?3 +++
>>>>> ?1 files changed, 3 insertions(+), 0 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
>>>>> index 04c2677..2e8e476 100644
>>>>> --- a/drivers/gpio/gpio-omap.c
>>>>> +++ b/drivers/gpio/gpio-omap.c
>>>>> @@ -114,6 +114,7 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
>>>>> ? ? ? else
>>>>> ? ? ? ? ? ? ? reg += bank->regs->clr_dataout;
>>>>>
>>>>> + ? ? l |= __raw_readl(bank->base + bank->regs->set_dataout);
>>>>
>>>> minor: IMO, it's more reader-friendly if this looks like
>>>>
>>>> ? ? ? l = __raw_read(...)
>>>> ? ? ? l |= GPIO_BIT(...)
>>>> ? ? ? __raw_write(...)
>>> Agreed. I will make the change.
>> Also, the read should be: __raw_readl(bank->base + bank->regs->dataout);
>> instead of bank->regs->set_dataout.
> I see a problem with this implementation. It is not correct to write l
> |= GPIO_BIT(...).
> For example if we write to clr_dataout register we would end up
> clearing bits which
> we are not supposed to. We should just be operating on current GPIO_BIT(...).
> The l |= GPIO_BIT(...) is needed just to make sure that we have the
> right context
> stored. So the overall sequence should be something like this:
>
>         void __iomem *reg = bank->base;
>         u32 l = GPIO_BIT(bank, gpio);
>
>         if (enable)
>                 reg += bank->regs->set_dataout;
>         else
>                 reg += bank->regs->clr_dataout;
>
>         __raw_writel(l, reg);
>         l |= __raw_readl(bank->base + bank->regs->dataout);
>         bank->context.dataout = l;

Again, you don't need the extra read-back here.  Just set/clear the bit
in the context.  Untested patch below.

Kevin


diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 0b05629..db905c0 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -111,10 +111,13 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
 	void __iomem *reg = bank->base;
 	u32 l = GPIO_BIT(bank, gpio);
 
-	if (enable)
+	if (enable) {
 		reg += bank->regs->set_dataout;
-	else
+		bank->context.dataout |= l;
+	} else {
 		reg += bank->regs->clr_dataout;
+		bank->context.dataout &= ~l;
+	}


From khilman at ti.com  Tue Mar 13 12:31:46 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 13 Mar 2012 09:31:46 -0700
Subject: [PATCH] ARM: OMAP4: Workaround the OCP synchronisation issue with
 32K synctimer.
In-Reply-To: <4F5F098E.4040006@ti.com> (Santosh Shilimkar's message of "Tue,
 13 Mar 2012 14:17:10 +0530")
References: <1331566388-2397-1-git-send-email-santosh.shilimkar@ti.com>
 <87399d225f.fsf@ti.com> <4F5F098E.4040006@ti.com>
Message-ID: <87vcm8tqbx.fsf@ti.com>

Santosh Shilimkar <santosh.shilimkar at ti.com> writes:

> On Monday 12 March 2012 10:21 PM, Kevin Hilman wrote:
>> Santosh Shilimkar <santosh.shilimkar at ti.com> writes:
>> 
>>> On OMAP4, recently a synchronisation bug is discovered by hardware
>>> team, which leads to incorrect timer value read from 32K sync timer
>>> IP when the IP is comming out of idle.
>>>
>>> The issue is due to the synchronization methodology used in the SYNCTIMER IP.
>>> The value of the counter register in 32kHz domain is synchronized to the OCP
>>> domain register only at count up event, and if the OCP clock is switched off,
>>> the OCP register gets out of synch until the first count up event after the
>>> clock is switched back -at the next falling edge of the 32kHz clock.
>>>
>>> Further investigation revealed that it applies to gptimer1 and watchdog timer2
>>> as well which may run on 32KHz. This patch fixes the issue for all the
>>> applicable modules.
>> 
>> The changelog describes the problem ver well, but doesn't actually
>> describe the fix (enable static dep.)  Can you update the changelog do
>> describe the fix, and why it fixes the problem.
>> 
> Sure. Updated patch below. The idea is to ensure that synctimer is
> syncronised before software does any reads on the counter. The BUG
> will get fixed in future OMAP designs

Thanks for the updated changelog.

Since this doesn't qualify as a regression, queuing for v3.4 (branch: for_3.4/fixes/pm)

Kevin


From hartleys at visionengravers.com  Tue Mar 13 12:32:12 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 13 Mar 2012 11:32:12 -0500
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <1331500100-31351-4-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-4-git-send-email-robherring2@gmail.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020695AB97DC@AUSP01VMBX24.collaborationhost.net>

On Sunday, March 11, 2012 2:08 PM, Rob Herring wrote:
>
> Several platforms create IOMEM defines for casting to 'void __iomem *',
> and other platforms are incorrectly using __io() macro for the same
> purpose. This creates a common definition and removes all the platform
> specific versions. Rather than try to make linux/io.h and asm/io.h
> assembly safe, the assembly version of IOMEM is moved into
> asm/assembler.h.
>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Sekhar Nori <nsekhar at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <rmallon at gmail.com>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
> Cc: David Brown <davidb at codeaurora.org>
> Cc: Daniel Walker <dwalker at fifo99.com>
> Cc: Bryan Huntsman <bryanh at codeaurora.org>
> Cc: Sascha Hauer <kernel at pengutronix.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> Cc: Rajeev Kumar <rajeev-dlh.kumar at st.com>
> Cc: Colin Cross <ccross at android.com>
> Cc: Olof Johansson <olof at lixom.net>
> Cc: Stephen Warren <swarren at nvidia.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> ---
>  arch/arm/include/asm/assembler.h                |    2 ++
>  arch/arm/include/asm/io.h                       |    2 ++
>  arch/arm/kernel/debug.S                         |    1 +
>  arch/arm/kernel/entry-armv.S                    |    1 +
>  arch/arm/mach-davinci/include/mach/hardware.h   |    6 ------
>  arch/arm/mach-davinci/include/mach/uncompress.h |    2 ++
>  arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |    9 ---------
>  arch/arm/mach-mmp/include/mach/addr-map.h       |    6 ------
>  arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |    6 ------
>  arch/arm/mach-msm/include/mach/msm_iomap.h      |    6 ------
>  arch/arm/mach-mxs/include/mach/hardware.h       |    6 ------
>  arch/arm/mach-omap1/ams-delta-fiq-handler.S     |    1 +
>  arch/arm/mach-omap1/iomap.h                     |    6 ------
>  arch/arm/mach-omap2/clock3xxx_data.c            |    1 +
>  arch/arm/mach-omap2/clock44xx_data.c            |    1 +
>  arch/arm/mach-omap2/iomap.h                     |    6 ------
>  arch/arm/mach-rpc/include/mach/hardware.h       |    6 ------
>  arch/arm/mach-spear3xx/clock.c                  |    1 +
>  arch/arm/mach-spear6xx/clock.c                  |    1 +
>  arch/arm/mach-tegra/include/mach/iomap.h        |    6 ------
>  arch/arm/mach-u300/include/mach/u300-regs.h     |    6 ------
>  arch/arm/plat-mxc/include/mach/hardware.h       |    6 ------
>  arch/arm/plat-omap/include/plat/hardware.h      |    6 ------
>  arch/arm/plat-omap/include/plat/usb.h           |    1 -
>  arch/arm/plat-spear/include/plat/hardware.h     |    6 ------
>  25 files changed, 13 insertions(+), 88 deletions(-)
>

For ep93xx:

Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>



From pullip.cho at samsung.com  Tue Mar 13 12:38:05 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Wed, 14 Mar 2012 01:38:05 +0900
Subject: [PATCH v11 3/3] iommu/exynos: Add iommu driver for Exynos
 Platforms
In-Reply-To: <20120313100024.GG18973@amd.com>
References: <017a01ccfdee$4e5e7a00$eb1b6e00$%cho@samsung.com>
 <20120312150156.GF18973@amd.com>
 <CAHQjnOOCQb4G1aeFB0FQVBstXpaXmahnQO8+FoinPcQNZEieGg@mail.gmail.com>
 <20120313100024.GG18973@amd.com>
Message-ID: <CAHQjnOO2Me5C6it=M0OFKdRcK0LObDR8+hPGyuUb21oqGwsg0g@mail.gmail.com>

On Tue, Mar 13, 2012 at 7:00 PM, Joerg Roedel <joerg.roedel at amd.com> wrote:
> On Tue, Mar 13, 2012 at 05:50:16PM +0900, KyongHo Cho wrote:
>> >> +struct sysmmu_drvdata {
>> >> + ? ? struct device *sysmmu;
>> >> + ? ? char *dbgname;
>> >> + ? ? int nsfrs;
>> >> + ? ? void __iomem **sfrbases;
>> >> + ? ? struct clk *clk[2];
>> >> + ? ? int activations;
>> >> + ? ? rwlock_t lock;
>> >> + ? ? struct iommu_domain *domain;
>> >> + ? ? sysmmu_fault_handler_t fault_handler;
>> >> + ? ? unsigned long pgtable;
>> >> + ? ? struct iommu_client client;
>> >> +};
>> >
>> > Is there any reason why 'struct iommu_client' is a seperate data
>> > structure? Otherwise it can be merged with 'truct sysmmu_drvdata'.
>
> Of course this doesn't need to be changed immediatly. I just asked if
> there was a specific reason for this seperation.
>
>> The problems will be soon fixed and I will post next patch tomorrow.
>
> Fine. Please also get the Acked-bys from the Exynos maintainer on
> patches 1 and 2 at least. I'll merge it then.
>
Thank you.
AFAIK, Exynos maintainer is somewhat busy for his own job.
I will ask him to ack my patch soon.

Best regards,

Cho KyongHo.


From santosh.shilimkar at ti.com  Tue Mar 13 12:40:09 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 13 Mar 2012 22:10:09 +0530
Subject: [PATCH] ARM: OMAP4: Workaround the OCP synchronisation issue with
 32K synctimer.
In-Reply-To: <87vcm8tqbx.fsf@ti.com>
References: <1331566388-2397-1-git-send-email-santosh.shilimkar@ti.com>
 <87399d225f.fsf@ti.com> <4F5F098E.4040006@ti.com> <87vcm8tqbx.fsf@ti.com>
Message-ID: <CAMQu2gxwH5oK4C6OBMZqBfijwfC8=eQYJv3jqh55qpZEqOhx0w@mail.gmail.com>

On Tue, Mar 13, 2012 at 10:01 PM, Kevin Hilman <khilman at ti.com> wrote:
> Santosh Shilimkar <santosh.shilimkar at ti.com> writes:
>
>> On Monday 12 March 2012 10:21 PM, Kevin Hilman wrote:
>>> Santosh Shilimkar <santosh.shilimkar at ti.com> writes:
>>>
>>>> On OMAP4, recently a synchronisation bug is discovered by hardware
>>>> team, which leads to incorrect timer value read from 32K sync timer
>>>> IP when the IP is comming out of idle.
>>>>
>>>> The issue is due to the synchronization methodology used in the SYNCTIMER IP.
>>>> The value of the counter register in 32kHz domain is synchronized to the OCP
>>>> domain register only at count up event, and if the OCP clock is switched off,
>>>> the OCP register gets out of synch until the first count up event after the
>>>> clock is switched back -at the next falling edge of the 32kHz clock.
>>>>
>>>> Further investigation revealed that it applies to gptimer1 and watchdog timer2
>>>> as well which may run on 32KHz. This patch fixes the issue for all the
>>>> applicable modules.
>>>
>>> The changelog describes the problem ver well, but doesn't actually
>>> describe the fix (enable static dep.) ?Can you update the changelog do
>>> describe the fix, and why it fixes the problem.
>>>
>> Sure. Updated patch below. The idea is to ensure that synctimer is
>> syncronised before software does any reads on the counter. The BUG
>> will get fixed in future OMAP designs
>
> Thanks for the updated changelog.
>
> Since this doesn't qualify as a regression, queuing for v3.4 (branch: for_3.4/fixes/pm)
>
Thanks Kevin.

Regards
Santosh


From arnd at arndb.de  Tue Mar 13 12:44:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 16:44:11 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <1331650032-15274-1-git-send-email-sr@denx.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
Message-ID: <201203131644.12048.arnd@arndb.de>

On Tuesday 13 March 2012, Stefan Roese wrote:
> This patch adds a generic target for SPEAr600 board that can be
> configured via the device-tree. Currently only interrupts are
> configured via device-tree. Other peripheral devices (e.g.
> ethernet, I2C, SMI flash, FSMC NAND flash etc) will follow in
> later patches.
> 
> Only the spear600-evb is currently supported. Other SPEAr600
> based boards will follow later.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Viresh Kumar <viresh.kumar at st.com>

Hi Stefan,

This is very cool, welcome onboard for the DT conversion with spear600!

> +static struct amba_device *amba_devs[] __initdata = {
> +	&gpio_device[0],
> +	&gpio_device[1],
> +	&gpio_device[2],
> +	&uart_device[0],
> +	&uart_device[1],
> +};

I would suggest you convert these to DT next so you can remove the
amba_devs list. Which devices are these? If they are pl061 and
pl010/pl011, the binding should be really easy to do.

> +static struct platform_device *plat_devs[] __initdata = {
> +};

This could be dropped right away, because you would never
add anything here.

> +static void __init spear600_dt_init(void)
> +{
> +	unsigned int i;
> +
> +	/* call spear600 machine init function */
> +	spear600_init();

spear600_init currently is an empty function, I think you can
drop that one too.

> +	/* Add Platform Devices */
> +	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
> +
> +	/* Add Amba Devices */
> +	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
> +		amba_device_register(amba_devs[i], &iomem_resource);

So although all of this can go away soon, you will have to
add a call to of_platform_populate() here in order to add the
devices from the device tree.

> +}
> +
> +static const char *spear600_dt_board_compat[] = {
> +	"st,spear600-evb",
> +	NULL
> +};
> +
> +static const struct of_device_id vic_of_match[] __initconst = {
> +	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
> +	{ /* Sentinel */ }
> +};
> +
> +static void __init spear6xx_dt_init_irq(void)
> +{
> +	of_irq_init(vic_of_match);
> +}
> +
> +DT_MACHINE_START(SPEAR600_DT, "ST-SPEAR600-DT")
> +	.map_io		=	spear6xx_map_io,
> +	.init_irq	=	spear6xx_dt_init_irq,
> +	.handle_irq	=	vic_handle_irq,
> +	.timer		=	&spear6xx_timer,
> +	.init_machine	=	spear600_dt_init,
> +	.restart	=	spear_restart,
> +	.dt_compat	=	spear600_dt_board_compat,
> +MACHINE_END

Since there is only one upstream board file and that is for the same board,
we can soon collapse all of it into the base platform support.

I think you should add all the code from this file to spear6xx.c instead
of adding a new file. We can then delete the spear600.c and spear600_evb.c
files once the DT support has matured.

	Arnd


From hartleys at visionengravers.com  Tue Mar 13 12:49:54 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 13 Mar 2012 11:49:54 -0500
Subject: [PATCH v4 04/11] ep93xx: Use ioremap for backlight driver
In-Reply-To: <1331592502-9083-5-git-send-email-rmallon@gmail.com>
References: <1331592502-9083-5-git-send-email-rmallon@gmail.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020695AB97F3@AUSP01VMBX24.collaborationhost.net>

On Monday, March 12, 2012 3:48 PM, Ryan Mallon wrote:
>
> The ep93xx backlight driver uses a single register within the
> framebuffer's register space. Currently the backlight driver uses a
> static IO mapping for the register since the memory cannot be
> requested by both drivers.
>
> Convert the static mapping to use ioremap so that we can remove the
> dependency on mach/hardware.h. To do so, we need remove the
> request_mem_region from both the backlight and framebuffer drivers,
> since whichever driver is loaded second will fail with -EBUSY
> otherwise.
>
> A proper fix is still required, and a FIXME comment has been added to
> both drivers.
>
> Signed-off-by: Ryan Mallon <rmallon at gmail.com>
> Suggested-by: Arnd Bergmann <arnd at arndb.de>
> Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Mika Westerberg <mika.westerberg at iki.fi>
> Cc: Richard Purdie <rpurdie at rpsys.net>
> Cc: Florian Tobias Schandinat <FlorianSchandinat at gmx.de>
> ---
>  arch/arm/mach-ep93xx/core.c         |   10 ++++++++++
>  drivers/video/backlight/ep93xx_bl.c |   25 ++++++++++++++-----------
>  drivers/video/ep93xx-fb.c           |   15 +++++++++------
>  3 files changed, 33 insertions(+), 17 deletions(-)

Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>



From s.hauer at pengutronix.de  Tue Mar 13 12:52:14 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 13 Mar 2012 17:52:14 +0100
Subject: [PATCH v1 3/5] ARM: imx28evk: add mmc dt support
In-Reply-To: <4F5F5C22.1080506@gmail.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-4-git-send-email-b29396@freescale.com>
 <4F5F5C22.1080506@gmail.com>
Message-ID: <20120313165214.GO26642@pengutronix.de>

On Tue, Mar 13, 2012 at 09:39:30AM -0500, Rob Herring wrote:
> On 03/13/2012 03:47 AM, Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > ---
> >  arch/arm/boot/dts/imx28-evk.dts |   14 ++++++++++++++
> >  arch/arm/boot/dts/imx28.dtsi    |   33 +++++++++++++++++++++++++++++++++
> >  arch/arm/mach-mxs/imx28-dt.c    |    2 ++
> >  3 files changed, 49 insertions(+), 0 deletions(-)
> 
> snip
> 
> > diff --git a/arch/arm/mach-mxs/imx28-dt.c b/arch/arm/mach-mxs/imx28-dt.c
> > index 78d1129..429b88e 100644
> > --- a/arch/arm/mach-mxs/imx28-dt.c
> > +++ b/arch/arm/mach-mxs/imx28-dt.c
> > @@ -23,6 +23,8 @@ static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
> >  	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
> >  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
> >  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP0_BASE_ADDR, "mxs-mmc.0", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP1_BASE_ADDR, "mxs-mmc.1", NULL),
> 
> Why is this needed?

These are needed for the drivers which have still the mxs-mmc.* names
to find their clocks. Alternatively we could also add the appropriate
clocks to the clock file. Don't know if that's better though.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From plagnioj at jcrosoft.com  Tue Mar 13 12:47:56 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 17:47:56 +0100
Subject: [PATCH 1/5 v4] i2c/gpio: add DT support
In-Reply-To: <20120313140822.GD2488@pengutronix.de>
References: <1331642024-19869-1-git-send-email-plagnioj@jcrosoft.com>
 <20120313140822.GD2488@pengutronix.de>
Message-ID: <20120313164756.GF18320@game.jcrosoft.org>

On 15:08 Tue 13 Mar     , Wolfram Sang wrote:
> On Tue, Mar 13, 2012 at 01:33:40PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> > update to use devm_kzalloc for private data
> 
> Hmm, you need really to work on the commit messages, not everybody is
> familiar with DT and its implications:
> 
> "To achieve DT support, we need to populate a custom platform_data in a
> private struct from DT information. To simplify code, the adapter and
> algorithm are also put into the private struct."
> 
ok I put this can I get the Ack ?

I need to send the pull asap

Best Regards,
J.


From tony at atomide.com  Tue Mar 13 13:07:57 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 13 Mar 2012 10:07:57 -0700
Subject: [PATCH 12/12] ARM: OMAP2+: board-omap4-*: Do not use anymore
 TWL6030_IRQ_BASE in board files
In-Reply-To: <1330707024-23730-13-git-send-email-b-cousson@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-13-git-send-email-b-cousson@ti.com>
Message-ID: <20120313170756.GK12083@atomide.com>

* Benoit Cousson <b-cousson at ti.com> [120302 08:19]:
> With the introduction of dynamically allocated IRQ in the twl6030 driver,
> the board files can no longer rely of static IRQ defines like before.
> 
> Retrieve the value dynamically allocated from the mmc -> twl6030 init
> callback.
> 
> Note: The Panda board does not seems to use the card detect IRQ.

Looks like this one is safe to merge via MFD and does not seem to
cause any merge conflicts.

This one should be folded into patch 08/12 to avoid boot issues
for between patches 08 and 12 in this series. Other than that:

Acked-by: Tony Lindgren <tony at atomide.com>


From hartleys at visionengravers.com  Tue Mar 13 13:15:34 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 13 Mar 2012 12:15:34 -0500
Subject: [PATCH v4 04/11] ep93xx: Use ioremap for backlight driver
In-Reply-To: <1331592502-9083-5-git-send-email-rmallon@gmail.com>
References: <1331592502-9083-5-git-send-email-rmallon@gmail.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020695AB9819@AUSP01VMBX24.collaborationhost.net>

On Monday, March 12, 2012 3:48 PM, Ryan Mallon wrote:
> The ep93xx backlight driver uses a single register within the
> framebuffer's register space. Currently the backlight driver uses a
> static IO mapping for the register since the memory cannot be
> requested by both drivers.
>
> Convert the static mapping to use ioremap so that we can remove the
> dependency on mach/hardware.h. To do so, we need remove the
> request_mem_region from both the backlight and framebuffer drivers,
> since whichever driver is loaded second will fail with -EBUSY
> otherwise.
>
> A proper fix is still required, and a FIXME comment has been added to
> both drivers.
>
> Signed-off-by: Ryan Mallon <rmallon at gmail.com>
> Suggested-by: Arnd Bergmann <arnd at arndb.de>
> Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Mika Westerberg <mika.westerberg at iki.fi>
> Cc: Richard Purdie <rpurdie at rpsys.net>
> Cc: Florian Tobias Schandinat <FlorianSchandinat at gmx.de>
> ---
>  arch/arm/mach-ep93xx/core.c         |   10 ++++++++++
>  drivers/video/backlight/ep93xx_bl.c |   25 ++++++++++++++-----------
>  drivers/video/ep93xx-fb.c           |   15 +++++++++------
>  3 files changed, 33 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
> index b5c1dae..c73e299 100644
> --- a/arch/arm/mach-ep93xx/core.c
> +++ b/arch/arm/mach-ep93xx/core.c
> @@ -682,9 +682,19 @@ static struct platform_device ep93xx_fb_device = {
>  	.resource		= ep93xx_fb_resource,
>  };
>  
> +/* The backlight use a single register in the framebuffer's register space */
> +#define EP93XX_RASTER_REG_BRIGHTNESS 0x20
> +
> +static struct resource ep93xx_bl_resources[] = {
> +	DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
> +		       EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
> +};
> +
>  static struct platform_device ep93xx_bl_device = {
>  	.name		= "ep93xx-bl",
>  	.id		= -1,
> +	.num_resources	= ARRAY_SIZE(ep93xx_bl_resources),
> +	.resource	= ep93xx_bl_resources,
>  };
>  
>  /**
> diff --git a/drivers/video/backlight/ep93xx_bl.c b/drivers/video/backlight/ep93xx_bl.c
> index b62b8b9..08214e1 100644
> --- a/drivers/video/backlight/ep93xx_bl.c
> +++ b/drivers/video/backlight/ep93xx_bl.c
> @@ -17,11 +17,6 @@
>  #include <linux/fb.h>
>  #include <linux/backlight.h>
>  
> -#include <mach/hardware.h>
> -
> -#define EP93XX_RASTER_REG(x)		(EP93XX_RASTER_BASE + (x))
> -#define EP93XX_RASTER_BRIGHTNESS	EP93XX_RASTER_REG(0x20)
> -
>  #define EP93XX_MAX_COUNT		255
>  #define EP93XX_MAX_BRIGHT		255
>  #define EP93XX_DEF_BRIGHT		128
> @@ -35,7 +30,7 @@ static int ep93xxbl_set(struct backlight_device *bl, int brightness)
>  {
>  	struct ep93xxbl *ep93xxbl = bl_get_data(bl);
>  
> -	__raw_writel((brightness << 8) | EP93XX_MAX_COUNT, ep93xxbl->mmio);
> +	writel((brightness << 8) | EP93XX_MAX_COUNT, ep93xxbl->mmio);
>  
>  	ep93xxbl->brightness = brightness;
>  
> @@ -70,21 +65,29 @@ static int __init ep93xxbl_probe(struct platform_device *dev)
>  	struct ep93xxbl *ep93xxbl;
>  	struct backlight_device *bl;
>  	struct backlight_properties props;
> +	struct resource *res;
>  
>  	ep93xxbl = devm_kzalloc(&dev->dev, sizeof(*ep93xxbl), GFP_KERNEL);
>  	if (!ep93xxbl)
>  		return -ENOMEM;
>  
> +	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
> +	if (!res)
> +		return -ENXIO;
> +
>  	/*
> -	 * This register is located in the range already ioremap'ed by
> -	 * the framebuffer driver.  A MFD driver seems a bit of overkill
> -	 * to handle this so use the static I/O mapping; this address
> -	 * is already virtual.
> +	 * FIXME - We don't do a request_mem_region here because we are
> +	 * sharing the register space with the framebuffer driver (see
> +	 * drivers/video/ep93xx-fb.c) and doing so will cause the second
> +	 * loaded driver to return -EBUSY.
>  	 *
>  	 * NOTE: No locking is required; the framebuffer does not touch
>  	 * this register.
>  	 */
> -	ep93xxbl->mmio = EP93XX_RASTER_BRIGHTNESS;
> +	ep93xxbl->mmio = devm_ioremap(&dev->dev, res->start,
> +				      resource_size(res));
> +	if (!ep93xxbl->mmio)
> +		return -ENXIO;
>  
>  	memset(&props, 0, sizeof(struct backlight_properties));
>  	props.type = BACKLIGHT_RAW;
> diff --git a/drivers/video/ep93xx-fb.c b/drivers/video/ep93xx-fb.c
> index 2e830ec..5301275 100644
> --- a/drivers/video/ep93xx-fb.c
> +++ b/drivers/video/ep93xx-fb.c
> @@ -519,12 +519,15 @@ static int __devinit ep93xxfb_probe(struct platform_device *pdev)
>  		goto failed;
>  	}
>  
> -	res = request_mem_region(res->start, resource_size(res), pdev->name);
> -	if (!res) {
> -		err = -EBUSY;
> -		goto failed;
> -	}
> -

Oops... Just took another look at this...

You removed the request_mem_region but left the release_mem_region in the
error path and in ep93xxfb_remove.

Regards,
Hartley

> +	/*
> +	 * FIXME - We don't do a request_mem_region here because we are
> +	 * sharing the register space with the backlight driver (see
> +	 * drivers/video/backlight/ep93xx_bl.c) and doing so will cause
> +	 * the second loaded driver to return -EBUSY.
> +	 *
> +	 * NOTE: No locking is required; the backlight does not touch
> +	 * any of the framebuffer registers.
> +	 */
>  	fbi->res = res;
>  	fbi->mmio_base = ioremap(res->start, resource_size(res));
>  	if (!fbi->mmio_base) {


From plagnioj at jcrosoft.com  Tue Mar 13 13:03:49 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 18:03:49 +0100
Subject: [PATCH v3] of: introduce helper to manage boolean
Message-ID: <1331658229-3401-1-git-send-email-plagnioj@jcrosoft.com>

of_property_read_bool

Search for a property in a device node.
Returns true if the property exist false otherwise.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
---
v3:

	include Grant comment

	Grant can I get the go please?

Best Regards,
J.
 include/linux/of.h |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/include/linux/of.h b/include/linux/of.h
index a75a831..a992cdf 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -342,6 +342,22 @@ static inline int of_machine_is_compatible(const char *compat)
 #define of_match_node(_matches, _node)	NULL
 #endif /* CONFIG_OF */
 
+/**
+ * of_property_read_bool - Findfrom a property
+ * @np:		device node from which the property value is to be read.
+ * @propname:	name of the property to be searched.
+ *
+ * Search for a property in a device node.
+ * Returns true if the property exist false otherwise.
+ */
+static inline bool of_property_read_bool(const struct device_node *np,
+					 const char *propname)
+{
+	struct property *prop = of_find_property(np, propname, NULL);
+
+	return prop ? false : true;
+}
+
 static inline int of_property_read_u32(const struct device_node *np,
 				       const char *propname,
 				       u32 *out_value)
-- 
1.7.7



From arnd at arndb.de  Tue Mar 13 13:21:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 13 Mar 2012 17:21:11 +0000
Subject: [PATCH v3] of: introduce helper to manage boolean
In-Reply-To: <1331658229-3401-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331658229-3401-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <201203131721.11973.arnd@arndb.de>

On Tuesday 13 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> of_property_read_bool
> 
> Search for a property in a device node.
> Returns true if the property exist false otherwise.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Acked-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From tony at atomide.com  Tue Mar 13 13:21:49 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 13 Mar 2012 10:21:49 -0700
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <1331500100-31351-4-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-4-git-send-email-robherring2@gmail.com>
Message-ID: <20120313172148.GL12083@atomide.com>

* Rob Herring <robherring2 at gmail.com> [120311 14:11]:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> Several platforms create IOMEM defines for casting to 'void __iomem *',
> and other platforms are incorrectly using __io() macro for the same
> purpose. This creates a common definition and removes all the platform
> specific versions. Rather than try to make linux/io.h and asm/io.h
> assembly safe, the assembly version of IOMEM is moved into
> asm/assembler.h.

Glad to see this:

Acked-by: Tony Lindgren <tony at atomide.com>


From grant.likely at secretlab.ca  Tue Mar 13 13:23:51 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 13 Mar 2012 11:23:51 -0600
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <1331628428-24017-2-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
Message-ID: <20120313172351.97C5E3E053B@localhost>

On Tue, 13 Mar 2012 16:47:04 +0800, Dong Aisheng <b29396 at freescale.com> wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> This patch includes basic dt support which can boot via nfs rootfs.
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
>  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
>  arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
>  arch/arm/boot/dts/imx28.dtsi                  |   88 +++++++++++++++++++++++++
>  arch/arm/mach-mxs/Kconfig                     |    9 +++
>  arch/arm/mach-mxs/Makefile                    |    1 +
>  arch/arm/mach-mxs/imx28-dt.c                  |   67 +++++++++++++++++++
>  6 files changed, 200 insertions(+), 0 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> index 54bddda..9f21faf 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -1,6 +1,10 @@
>  Freescale i.MX Platforms Device Tree Bindings
>  -----------------------------------------------
>  
> +i.MX28 Evaluation Kit
> +Required root node properties:
> +    - compatible = "fsl,imx28-evk", "fsl,imx28";
> +
>  i.MX51 Babbage Board
>  Required root node properties:
>      - compatible = "fsl,imx51-babbage", "fsl,imx51";
> diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
> new file mode 100644
> index 0000000..9758dc4
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx28-evk.dts
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "imx28.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX28 Evaluation Kit";
> +	compatible = "fsl,imx28-evk", "fsl,imx28";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x40000000 0x08000000>;
> +	};
> +
> +	ahb at 80080000 {
> +		fec at 800f0000 {
> +			phy-mode = "rmii";
> +			local-mac-address = [00 04 9F 01 7D 5B];

Generally a bad idea to put a specific mac address into the device tree.
Better to fill it with zeros.  Otherwise all the dev boards will end up using
the same value.

> +			status = "okay";
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> new file mode 100644
> index 0000000..acf0dab
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -0,0 +1,88 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	interrupt-parent = <&icoll>;
> +
> +	aliases {
> +		serial0 = &uart1;
> +	};
> +
> +	cpus {
> +		cpu at 0 {
> +			compatible = "arm,arm926ejs";
> +		};
> +	};
> +
> +	apb at 80000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x80000000 0x80000>;
> +		ranges;
> +
> +		apbh at 80000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x80000000 0x3c900>;
> +			ranges;
> +
> +			icoll: interrupt-controller at 80000000 {
> +				compatible = "fsl,imx28-icoll";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +				reg = <0x80000000 0x2000>;
> +			};
> +		};
> +
> +		apbx at 80040000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x80040000 0x40000>;
> +			ranges;
> +
> +			uart1: uart at 80074000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x80074000 0x2000>;
> +				interrupts = <47>;
> +			};
> +		};

What is the purpose of the apbh and apbx busses?  Will more device nodes
get added to them later, or does each only contain a single device?

g.


From rnayak at ti.com  Tue Mar 13 13:24:24 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 13 Mar 2012 22:54:24 +0530
Subject: [PATCH v2 0/2] Fixes in hwmod reset code
In-Reply-To: <alpine.DEB.2.00.1203130819480.22211@utopia.booyaka.com>
References: <1331647435-31666-1-git-send-email-rnayak@ti.com>
 <alpine.DEB.2.00.1203130819480.22211@utopia.booyaka.com>
Message-ID: <4F5F82C8.7000002@ti.com>

Hi Paul,

On Tuesday 13 March 2012 07:52 PM, Paul Walmsley wrote:
> Hi Rajendra
>
> On Tue, 13 Mar 2012, Rajendra Nayak wrote:
>
>> This fixes a couple of issues around hwmod reset
>> APIs'.
>> Patches are based on 3.3.-rc7.
>>
>> Rajendra Nayak (2):
>>    ARM: omap: hwmod: Restore sysc after a reset
>>    ARM: omap: hwmod: Make omap_hwmod_softreset wait for reset status
>>
>>   arch/arm/mach-omap2/omap_hwmod.c |   18 ++++++------------
>>   1 files changed, 6 insertions(+), 12 deletions(-)
>
> Could you base this on either my 'hwmod_code_cleanup_3.4' branch or
> 'hwmod_enable_remaining_hwmods_devel_3.4' branch?  There are some reset
> changes in there also.

Sure, will send them out shortly.

regards,
Rajendra
>
>
> - Paul



From rnayak at ti.com  Tue Mar 13 13:25:22 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 13 Mar 2012 22:55:22 +0530
Subject: [PATCH v2 0/2] Fixes in hwmod reset code
Message-ID: <1331659524-7635-1-git-send-email-rnayak@ti.com>

This fixes a couple of issues around hwmod reset
APIs'.
Patches are based on 'hwmod_enable_remaining_hwmods_devel_3.4'
of git://git.pwsan.com/linux-2.6

Rajendra Nayak (2):
  ARM: omap: hwmod: Restore sysc after a reset
  ARM: omap: hwmod: Make omap_hwmod_softreset wait for reset status

 arch/arm/mach-omap2/omap_hwmod.c |   18 ++++++------------
 1 files changed, 6 insertions(+), 12 deletions(-)



From rnayak at ti.com  Tue Mar 13 13:25:23 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 13 Mar 2012 22:55:23 +0530
Subject: [PATCH v2 1/2] ARM: omap: hwmod: Restore sysc after a reset
In-Reply-To: <1331659524-7635-1-git-send-email-rnayak@ti.com>
References: <1331659524-7635-1-git-send-email-rnayak@ti.com>
Message-ID: <1331659524-7635-2-git-send-email-rnayak@ti.com>

After a softreset, make sure the sysc settings are correctly
restored.

Reported-by: Anand Gadiyar <gadiyar at ti.com>
Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 8ac26f2..6c0e7eb 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2767,6 +2767,10 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
 
 	spin_lock_irqsave(&oh->_lock, flags);
 	r = _reset(oh);
+	if (oh->class->sysc) {
+		_update_sysc_cache(oh);
+		_enable_sysc(oh);
+	}
 	spin_unlock_irqrestore(&oh->_lock, flags);
 
 	return r;
-- 
1.7.1



From rnayak at ti.com  Tue Mar 13 13:25:24 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 13 Mar 2012 22:55:24 +0530
Subject: [PATCH v2 2/2] ARM: omap: hwmod: Make omap_hwmod_softreset wait for
 reset status
In-Reply-To: <1331659524-7635-1-git-send-email-rnayak@ti.com>
References: <1331659524-7635-1-git-send-email-rnayak@ti.com>
Message-ID: <1331659524-7635-3-git-send-email-rnayak@ti.com>

omap_hwmod_softreset() does not seem to wait for reset status
after doing a softreset. Make it use _ocp_softreset() instead
which does this correctly.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Anand Gadiyar <gadiyar at ti.com>
Cc: Shubhrajyoti D <shubhrajyoti at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |   14 ++------------
 1 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6c0e7eb..0c64853 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2423,20 +2423,10 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
  */
 int omap_hwmod_softreset(struct omap_hwmod *oh)
 {
-	u32 v;
-	int ret;
-
-	if (!oh || !(oh->_sysc_cache))
+	if (!oh)
 		return -EINVAL;
 
-	v = oh->_sysc_cache;
-	ret = _set_softreset(oh, &v);
-	if (ret)
-		goto error;
-	_write_sysconfig(v, oh);
-
-error:
-	return ret;
+	return _ocp_softreset(oh);
 }
 
 /**
-- 
1.7.1



From grant.likely at secretlab.ca  Tue Mar 13 13:28:07 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 13 Mar 2012 11:28:07 -0600
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <4F5F60DB.9090801@itwatchdogs.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <4F5F5B3F.2000303@gmail.com> <4F5F60DB.9090801@itwatchdogs.com>
Message-ID: <20120313172807.AC4763E053B@localhost>

On Tue, 13 Mar 2012 09:59:39 -0500, Zach Sadecki <zsadecki at itwatchdogs.com> wrote:
> On 03/13/2012 09:35 AM, Rob Herring wrote:
> > +	ahb at 80080000 {
> > +		fec at 800f0000 {
> > Use generic names: ethernet at 800f0000
> Generic is good, but consistency is better, IMHO.  grepping existing dts 
> files in 3.2.9 finds 6 instances of "fec@" and 0 instances of "ethernet@"
> >> +			uart1: uart at 80074000 {
> > Use generic names: uart1: serial at ...
> Same comment here, but unfortunately there is already inconsistency in 
> existing files...  25 instances of "serial@" and 35 instances of "uart@"

No, Rob is correct.  The generic names recommended practice is well
established and documented.  Expand your grep search to include
arch/powerpc/bot/dts/*.

See section 2.2.2 of ePAPR[1]

[1]https://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.1.pdf

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From tony at atomide.com  Tue Mar 13 13:31:17 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 13 Mar 2012 10:31:17 -0700
Subject: [PATCH 0/6] ARM: OMAP3+: smartreflex: add class support
In-Reply-To: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
References: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
Message-ID: <20120313173117.GM12083@atomide.com>

* jean.pihet at newoldbits.com <jean.pihet at newoldbits.com> [120313 03:29]:
> From: Jean Pihet <j-pihet at ti.com>
> 
> Add the class support so that various classes of operation can be
> implemented (class 1p5 etc.).
> 
> Based on linux-omap's master branch (3.3.0-rc6), commit
> 85244e0edd240da2004bb2ab7cbcbc67a336f20d

We need to move smartreflex into drivers before adding
anything new to it.

Tony


From hartleys at visionengravers.com  Tue Mar 13 13:33:52 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 13 Mar 2012 12:33:52 -0500
Subject: [PATCH v4 08/11] ep93xx: Make syscon access functions private
 to SoC
In-Reply-To: <1331592502-9083-9-git-send-email-rmallon@gmail.com>
References: <1331592502-9083-9-git-send-email-rmallon@gmail.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020695AB9832@AUSP01VMBX24.collaborationhost.net>

On Monday, March 12, 2012 3:48 PM, Ryan Mallon wrote:
>
> The syscon access functions are no longer used outside of the core
> EP93xx code. Move their definitions into the SoC code.
>
> Signed-off-by: Ryan Mallon <rmallon at gmail.com>
> Reviewed-by: Mika Westerberg <mika.westerberg at iki.fi>
> Acked-by: Hartley Sweeten <hsweeten at visionengravers.com>
> ---

<snip>

> diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
> index a22e11b..1273013 100644
> --- a/arch/arm/mach-ep93xx/soc.h
> +++ b/arch/arm/mach-ep93xx/soc.h
> @@ -104,4 +104,18 @@
>  #define EP93XX_WATCHDOG_PHYS_BASE	EP93XX_APB_PHYS(0x00140000)
>  #define EP93XX_WATCHDOG_BASE		EP93XX_APB_IOMEM(0x00140000)
>  
> +/* EP93xx System Controller software locked register write */
> +void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
> +void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
> +
> +static inline void ep93xx_devcfg_set_bits(unsigned int bits)
> +{
> +	ep93xx_devcfg_set_clear(bits, 0x00);
> +}
> +
> +static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
> +{
> +	ep93xx_devcfg_set_clear(0x00, bits);
> +}
> +
>  #endif /* _EP93XX_PHYS_BASE_H */

Ryan,

I just noticed that the comment after the #endif is wrong.

It should either be /* _EP93XX_SOC_H */ or should just be removed.

Regards,
Hartley



From nm at ti.com  Tue Mar 13 13:40:01 2012
From: nm at ti.com (Menon, Nishanth)
Date: Tue, 13 Mar 2012 12:40:01 -0500
Subject: [PATCH 3/6] ARM: OMAP3+: SmartReflex: introduce notifier_control
In-Reply-To: <1331634381-31436-4-git-send-email-j-pihet@ti.com>
References: <1331634381-31436-1-git-send-email-j-pihet@ti.com>
 <1331634381-31436-4-git-send-email-j-pihet@ti.com>
Message-ID: <CAOMWX4fauZQccPhHn+f4-SOAXRbaU135xUKva0QsGgJoXDQzwA@mail.gmail.com>

On Tue, Mar 13, 2012 at 05:26, <jean.pihet at newoldbits.com> wrote:
>
> diff --git a/arch/arm/mach-omap2/smartreflex.c
> b/arch/arm/mach-omap2/smartreflex.c
> index 7977018..dfe8075 100644
> --- a/arch/arm/mach-omap2/smartreflex.c
> +++ b/arch/arm/mach-omap2/smartreflex.c
...
> + ? ? ? switch (sr->ip_type) {
> + ? ? ? case SR_TYPE_V1:
> + ? ? ? ? ? ? ? value = notifier_to_irqen_v1(sr_class->notify_flags);
> + ? ? ? ? ? ? ? sr_modify_reg(sr, ERRCONFIG_V1, value,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (enable) ? value : 0);
> + ? ? ? ? ? ? ? break;
> + ? ? ? case SR_TYPE_V2:
> + ? ? ? ? ? ? ? value = notifier_to_irqen_v2(sr_class->notify_flags);
> + ? ? ? ? ? ? ? sr_write_reg(sr, (enable) ? IRQENABLE_SET : IRQENABLE_CLR,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? value);
> + ? ? ? ? ? ? ? break;
> + ? ? ? default:
> + ? ? ? ? ? ? ? ?dev_warn(&sr->pdev->dev, "%s: unknown type of sr??\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?__func__);
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? if (!enable)
> + ? ? ? ? ? ? ? sr_write_reg(sr, IRQSTATUS, value);

can you move this to before we disable the interrupt? it took a while,
but we caught a bug recently when we disable IRQ and then attempt to
clear the status[1]

Regards,
Nishanth Menon
[1] http://review.omapzoom.org/#/c/20231/


From grant.likely at secretlab.ca  Tue Mar 13 13:42:38 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 13 Mar 2012 11:42:38 -0600
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <1331628428-24017-3-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-3-git-send-email-b29396@freescale.com>
Message-ID: <20120313174238.CE9133E053B@localhost>

On Tue, 13 Mar 2012 16:47:05 +0800, Dong Aisheng <b29396 at freescale.com> wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> 
> ---
> The patch is still using a private way for dma part binding
> since the common dma binding is still under discussion.
> http://www.spinics.net/lists/linux-omap/msg65528.html
> 
> Will update to use common dma binding when it hits mainline.
> ---
>  .../devicetree/bindings/mmc/fsl-mxs-mmc.txt        |   23 ++++++
>  drivers/mmc/host/mxs-mmc.c                         |   82 +++++++++++++++++++-
>  2 files changed, 102 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> new file mode 100644
> index 0000000..adc1142
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> @@ -0,0 +1,23 @@
> +* FREESCALE MXS MMC peripheral
> +
> +Required properties:
> +- compatible : Should be "fsl,<chip>-mmc"
> +- reg : Should contain registers location and length
> +- interrupts : Should contain interrupt.
> +  The format is <irq_err irq_dma>.
> +- dma_channel: Should contain the dma channel it uses

Don't use '_' in property names.

The is a generic dma binding being drafted that uses a phandle to the dma
controller and the ability to encode channel numbers.  You may want to take
a look at it.

> +
> +Optional properties:
> +- wp-gpios : Specify GPIOs for write protection
> +- slot-4bit: Specify 4 bit mode support
> +- slot-8bit: Specify 8 bit and 4 bit mode support
> +
> +Examples:
> +mmc1: ssp at 80010000 {
> +	compatible = "fsl,imx28-mmc";
> +	reg = <0x80010000 2000>;
> +	/* <irq_err irq_dma> */
> +	interrupts = <96 82>;
> +	dma_channel = <0>;
> +	slot-8bit;
> +};
> diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
> index 382c835..6cf2d17 100644
> --- a/drivers/mmc/host/mxs-mmc.c
> +++ b/drivers/mmc/host/mxs-mmc.c
> @@ -38,6 +38,10 @@
>  #include <linux/gpio.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
> +#include <linux/slab.h>
>  
>  #include <mach/mxs.h>
>  #include <mach/common.h>
> @@ -673,17 +677,79 @@ static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
>  	return true;
>  }
>  
> +#ifdef CONFIG_OF
> +static struct resource * __devinit mxs_mmc_get_of_dmares(
> +				struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct resource *dmares;
> +	int ret;
> +
> +	if (!np)
> +		return NULL;
> +
> +	dmares = kzalloc(sizeof(*dmares), GFP_KERNEL);

devm_kzalloc()

> +	dmares->flags = IORESOURCE_DMA;
> +	ret = of_property_read_u32(np, "dma_channel", &dmares->start);
> +	if (ret) {
> +		dev_err(&pdev->dev, "unable to get dmares from dt\n");
> +		return NULL;
> +	}
> +	dmares->end = dmares->start;
> +
> +	return dmares;
> +}
> +
> +static int __devinit mxs_mmc_get_of_property(struct platform_device *pdev,
> +				struct mxs_mmc_platform_data **ppdata)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct mxs_mmc_platform_data *pdata = *ppdata;
> +
> +	if (!np)
> +		return -ENODEV;
> +
> +	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);

Ditto

Fix up those comments and you can add my:

Acked-by: Grant Likely <grant.likely at secretlab.ca>

> +
> +	if (of_get_property(np, "slot-8bit", NULL))
> +		pdata->flags |= SLOTF_8_BIT_CAPABLE;
> +
> +	if (of_get_property(np, "slot-4bit", NULL))
> +		pdata->flags |= SLOTF_4_BIT_CAPABLE;
> +
> +	pdata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
> +
> +	dev_dbg(&pdev->dev, "wp-gpios %d flags %d\n", pdata->wp_gpio,
> +		pdata->flags);
> +
> +	return 0;
> +}
> +#else
> +static struct resource * __devinit mxs_mmc_get_of_dmares(
> +				struct platform_device *pdev)
> +{
> +	return NULL;
> +}
> +static inline int mxs_mmc_get_of_property(struct platform_device *pdev,
> +			struct mxs_mmc_platform_data *pdata)
> +{
> +	return -ENODEV;
> +}
> +#endif
> +
>  static int mxs_mmc_probe(struct platform_device *pdev)
>  {
>  	struct mxs_mmc_host *host;
>  	struct mmc_host *mmc;
>  	struct resource *iores, *dmares, *r;
> -	struct mxs_mmc_platform_data *pdata;
> +	struct mxs_mmc_platform_data *pdata = NULL;
>  	int ret = 0, irq_err, irq_dma;
>  	dma_cap_mask_t mask;
>  
>  	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
> +	dmares = mxs_mmc_get_of_dmares(pdev);
> +	if (dmares == NULL)
> +		dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
>  	irq_err = platform_get_irq(pdev, 0);
>  	irq_dma = platform_get_irq(pdev, 1);
>  	if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
> @@ -740,7 +806,9 @@ static int mxs_mmc_probe(struct platform_device *pdev)
>  	mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
>  		    MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
>  
> -	pdata =	mmc_dev(host->mmc)->platform_data;
> +	mxs_mmc_get_of_property(pdev, &pdata);
> +	if (pdata == NULL)
> +		pdata =	mmc_dev(host->mmc)->platform_data;
>  	if (pdata) {
>  		if (pdata->flags & SLOTF_8_BIT_CAPABLE)
>  			mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
> @@ -851,6 +919,13 @@ static const struct dev_pm_ops mxs_mmc_pm_ops = {
>  };
>  #endif
>  
> +static const struct of_device_id mxs_mmc_dt_ids[] = {
> +	{ .compatible = "fsl,imx23-mmc", .data = NULL, },
> +	{ .compatible = "fsl,imx28-mmc", .data = NULL, },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
> +
>  static struct platform_driver mxs_mmc_driver = {
>  	.probe		= mxs_mmc_probe,
>  	.remove		= mxs_mmc_remove,
> @@ -860,6 +935,7 @@ static struct platform_driver mxs_mmc_driver = {
>  #ifdef CONFIG_PM
>  		.pm	= &mxs_mmc_pm_ops,
>  #endif
> +		.of_match_table = mxs_mmc_dt_ids,
>  	},
>  };
>  
> -- 
> 1.7.0.4
> 
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From robherring2 at gmail.com  Tue Mar 13 13:45:02 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 12:45:02 -0500
Subject: [PATCH v1 3/5] ARM: imx28evk: add mmc dt support
In-Reply-To: <20120313165214.GO26642@pengutronix.de>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-4-git-send-email-b29396@freescale.com>
 <4F5F5C22.1080506@gmail.com> <20120313165214.GO26642@pengutronix.de>
Message-ID: <4F5F879E.4030407@gmail.com>

On 03/13/2012 11:52 AM, Sascha Hauer wrote:
> On Tue, Mar 13, 2012 at 09:39:30AM -0500, Rob Herring wrote:
>> On 03/13/2012 03:47 AM, Dong Aisheng wrote:
>>> From: Dong Aisheng <dong.aisheng at linaro.org>
>>>
>>> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
>>> ---
>>>  arch/arm/boot/dts/imx28-evk.dts |   14 ++++++++++++++
>>>  arch/arm/boot/dts/imx28.dtsi    |   33 +++++++++++++++++++++++++++++++++
>>>  arch/arm/mach-mxs/imx28-dt.c    |    2 ++
>>>  3 files changed, 49 insertions(+), 0 deletions(-)
>>
>> snip
>>
>>> diff --git a/arch/arm/mach-mxs/imx28-dt.c b/arch/arm/mach-mxs/imx28-dt.c
>>> index 78d1129..429b88e 100644
>>> --- a/arch/arm/mach-mxs/imx28-dt.c
>>> +++ b/arch/arm/mach-mxs/imx28-dt.c
>>> @@ -23,6 +23,8 @@ static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
>>>  	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
>>>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
>>>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
>>> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP0_BASE_ADDR, "mxs-mmc.0", NULL),
>>> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP1_BASE_ADDR, "mxs-mmc.1", NULL),
>>
>> Why is this needed?
> 
> These are needed for the drivers which have still the mxs-mmc.* names
> to find their clocks. Alternatively we could also add the appropriate
> clocks to the clock file. Don't know if that's better though.

Ah, yes I should have known that... If clk lookup is all that's needed,
I'd suggest adding the necessary clk lookups either here or in the clock
code. Not much difference, but at least it removes the use of
*_BASE_ADDR defines.

Rob


From plagnioj at jcrosoft.com  Tue Mar 13 13:48:23 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Tue, 13 Mar 2012 18:48:23 +0100
Subject: [PATCH v4] of: introduce helper to manage boolean
Message-ID: <1331660903-10193-1-git-send-email-plagnioj@jcrosoft.com>

of_property_read_bool

Search for a property in a device node.
Returns true if the property exist false otherwise.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Cc: Grant Likely <grant.likely at secretlab.ca>
---
v4:

	send the right version

	include Grant comment

	Grant can I get the go please?

Best Regards,
J.
 include/linux/of.h |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/include/linux/of.h b/include/linux/of.h
index a75a831..a992cdf 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -342,6 +342,22 @@ static inline int of_machine_is_compatible(const char *compat)
 #define of_match_node(_matches, _node)	NULL
 #endif /* CONFIG_OF */
 
+/**
+ * of_property_read_bool - Findfrom a property
+ * @np:		device node from which the property value is to be read.
+ * @propname:	name of the property to be searched.
+ *
+ * Search for a property in a device node.
+ * Returns true if the property exist false otherwise.
+ */
+static inline bool of_property_read_bool(const struct device_node *np,
+					 const char *propname)
+{
+	struct property *prop = of_find_property(np, propname, NULL);
+
+	return prop ? true : false;
+}
+
 static inline int of_property_read_u32(const struct device_node *np,
 				       const char *propname,
 				       u32 *out_value)
-- 
1.7.7



From hector.oron at gmail.com  Tue Mar 13 14:05:40 2012
From: hector.oron at gmail.com (Hector Oron)
Date: Tue, 13 Mar 2012 19:05:40 +0100
Subject: [PATCH] efikamx: match machine descriptions with legacy
In-Reply-To: <CAODfWeE86mUf17CAZ+aa1bKxX4Toq9ogm01tDEMVYcnqu96LAg@mail.gmail.com>
References: <1329779368-27878-1-git-send-email-hector.oron@gmail.com>
 <CAODfWeE86mUf17CAZ+aa1bKxX4Toq9ogm01tDEMVYcnqu96LAg@mail.gmail.com>
Message-ID: <CAODfWeGKRqbQuB20rFOJC6wgwqTGt9eZOog8fOWfB-3GQC0cFw@mail.gmail.com>

Sending as I forgot to CC Sascha

2012/3/11 Hector Oron <hector.oron at gmail.com>:
> Hello,
>
> 2012/2/21 Hector Oron <hector.oron at gmail.com>:
>> ?Rename machine descriptions to match legacy descriptions distributed by
>> ?manufacturer BSP. This way distributions can do clean upgrades from
>> ?userspace scripts which check for these values to differentiate platforms
>> ?with single kernel binaries.
>>
>> Signed-off-by: Hector Oron <hector.oron at gmail.com>
>> Acked-by: Matt Sealey <matt at genesi-usa.com>
>> ---
>> ?arch/arm/mach-mx5/board-mx51_efikamx.c | ? ?3 +--
>> ?arch/arm/mach-mx5/board-mx51_efikasb.c | ? ?2 +-
>> ?2 files changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
>> index 3a5ed2d..fbfccc7 100644
>> --- a/arch/arm/mach-mx5/board-mx51_efikamx.c
>> +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
>> @@ -283,8 +283,7 @@ static struct sys_timer mx51_efikamx_timer = {
>> ? ? ? ?.init = mx51_efikamx_timer_init,
>> ?};
>>
>> -MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
>> - ? ? ? /* Maintainer: Amit Kucheria <amit.kucheria at linaro.org> */
>> +MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)")
>> ? ? ? ?.atag_offset = 0x100,
>> ? ? ? ?.map_io = mx51_map_io,
>> ? ? ? ?.init_early = imx51_init_early,
>> diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
>> index 4baf05c..dedbca5 100644
>> --- a/arch/arm/mach-mx5/board-mx51_efikasb.c
>> +++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
>> @@ -483,7 +483,7 @@ static struct sys_timer mx51_efikasb_timer = {
>> ? ? ? ?.init ? = mx51_efikasb_timer_init,
>> ?};
>>
>> -MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
>> +MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)")
>> ? ? ? ?.atag_offset = 0x100,
>> ? ? ? ?.map_io = mx51_map_io,
>> ? ? ? ?.init_early = imx51_init_early,
>> --
>> 1.7.9
>>
>
> Ping!
> I dont see the patch being applied. Is there any problem with it?
>
> Cheers,
> --
> ?H?ctor Or?n ?-.. . -... .. .- -. ? -.. . ...- . .-.. --- .--. . .-.



-- 
?H?ctor Or?n ?-.. . -... .. .- -. ? -.. . ...- . .-.. --- .--. . .-.


From grant.likely at secretlab.ca  Tue Mar 13 14:18:03 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 13 Mar 2012 12:18:03 -0600
Subject: [PATCH v3 2/2] regulator: add device tree support for max8997
In-Reply-To: <CAJuYYwRAXyU7d7qhGUX-=qWUJ0M1KB3XCGPOnUxToP=0XOhzqg@mail.gmail.com>
References: <1330000688-11226-1-git-send-email-thomas.abraham@linaro.org>
 <1330000688-11226-3-git-send-email-thomas.abraham@linaro.org>
 <20120313034306.16CF73E07E4@localhost>
 <CAJuYYwRAXyU7d7qhGUX-=qWUJ0M1KB3XCGPOnUxToP=0XOhzqg@mail.gmail.com>
Message-ID: <20120313181803.B45073E053B@localhost>

On Tue, 13 Mar 2012 12:14:42 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> On 13 March 2012 09:13, Grant Likely <grant.likely at secretlab.ca> wrote:
> > On Thu, 23 Feb 2012 18:08:08 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> > Otherwise, the patch looks pretty good. ??(although seeing the decode function
> > has got me thinking that we need a much better way of decoding the dt data).
> 
> The parsing function looks huge since there is lot of data to pick up
> from the dt node.

Oh, I understand that you have to do it this way; I just think the core code
should make it a lot easier.  :-)

g.


From tony at atomide.com  Tue Mar 13 14:33:52 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 13 Mar 2012 11:33:52 -0700
Subject: [GIT PULL] one kernel panic fix for v3.3-rc7
Message-ID: <20120313183352.GN12083@atomide.com>

Hi Olof,

Here's one more kernel panic fix that I dropped from last weeks
fixes as it was still being discussed.

This is a fix for the regression caused by fixing an earlier
regression for smsc911x fixed regulators :(

Turns out that we have more than one smsc911x on some boards,
and the earlier fix causes a kernel panic for board trying to
register second smsc911x instance, even if the second smsc911x
is on an add-on board that is not connected.

Note that the boards with second smsc911x will also need to be
patched later on to provide their own regulators.

Regards,

Tony


The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
  Linus Torvalds (1):
        Linux 3.3-rc7

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fix-smsc911x-regulator

Kevin Hilman (1):
      ARM: OMAP2+: gpmc-smsc911x: only register regulator for first instance

 arch/arm/mach-omap2/gpmc-smsc911x.c |   11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)


From tim.bird at am.sony.com  Tue Mar 13 15:10:04 2012
From: tim.bird at am.sony.com (Tim Bird)
Date: Tue, 13 Mar 2012 12:10:04 -0700
Subject: RFC: Stack overrun detector on ARM - ideas?
Message-ID: <4F5F9B8C.2060105@am.sony.com>

Hello smart ARM people...

I've been asked to forward port a patch that Sony was using in previous
kernel versions, for detecting stack overruns on ARM processors.
I'm having trouble getting it working on current kernels, and
was wondering if this was the best approach anyway.  I just wanted
to get some feedback and see if there were possibly other ideas
for approaches that would work for this purpose.  This has been
primarily used for our group using 4K stacks, for testing
prior to product shipment. But it might be useful in other
circumstances, so hopefully there is some interest in the feature.

What we did in the past:
1) Add a config option to map all kernel pages individually (as
4K units)
2) Add a config option to support marking individual pages as
non-readable (or absent), so that if ever accessed they would
result in a kernel fault.
3) Add code to mark the bottom page of each kernel stack as
non-readable, thus creating a guard page.
4) Add a config option to put the thread info at the top of stack
rather than at the bottom.  This allows the stack to grow down
and hit the guard page, without overruning the threadinfo struct.
5) Add a config value to allow specifying the start size of
the kernel stack, to allow experimentation with different stack
sizes.  (That is, the stack could be initialized at 4K above the
guard page, or 6k, or 8k, etc.)

The main idea is to allow the product team to get a fault on a
stack overrun for a selectable value of stack size.

I have most of the code working (parts 3-5), but 1-2 seems to
be a problem. In reading this thread:

http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/084899.html
and
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086955.html

it appears that 4K kernel mappings is not supported, and would
be hard to re-instate.  (I have a patch that worked in previous
kernels, but frankly I'm having a hard time understanding it - I'm
not an ARM memory management guru.)

My questions are - Did the kernel used to map memory with 4K section
mappings, or has it been 1MB for a long time?
How hard would it be to implement 4K mappings (ie get my patch
working again)?  Is there another way to do this that would be
better?  I was thinking of maybe setting a hardware breakpoint
region below the stack, rather than using a guard page.  It seems
like these are limited in number, so I would have to change them with
context switches to reflect each newly active stack.  This stack monitoring
feature is not turned on in products - it is only used for internal
testing - so performance impact is not an issue.

In looking at the ARM hardware debug capabilities, they appear to
be quite complex.  Has anyone done something with per-task
hardware breakpoints before, or is there some place I can look
for an example?

Any other ideas for ways to detect stack overruns?

Note that we already use static stack analysis
on the kernel executable image, as well as runtime stack monitoring
using tracers.  The former doesn't catch runtime-nested stack depth,
and the latter doesn't catch leaves with deep stack usage very well.
Possibly I could create a table of leaf function depths, or do
runtime scanning of the function prefix, to make the tracer-based
stack monitoring more accurate.

Thanks for any help, ideas or pointers you can provide.
 -- Tim

=============================
Tim Bird
Architecture Group Chair, CE Workgroup of the Linux Foundation
Senior Staff Engineer, Sony Network Entertainment
=============================



From davidb at codeaurora.org  Tue Mar 13 15:34:32 2012
From: davidb at codeaurora.org (David Brown)
Date: Tue, 13 Mar 2012 12:34:32 -0700
Subject: [PATCH v3 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 DMA APIs
In-Reply-To: <CAPDArRLs23VDJSWpX8xJsXfn+_SV2FcyzLYBF9UAxf=Rv9svGQ@mail.gmail.com>
References: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>
 <20120312201421.GA3459@fifo99.com>
 <CAPDArRLs23VDJSWpX8xJsXfn+_SV2FcyzLYBF9UAxf=Rv9svGQ@mail.gmail.com>
Message-ID: <20120313193432.GA13046@codeaurora.org>

On Tue, Mar 13, 2012 at 04:27:37PM +0530, Shantanu Gupta wrote:

> Any info available(publicly) on so as to what all chipsets have this capability
> ?

The ADM hardware is in every currently available MSM that can run
Linux.  It is being phased out, to be replaced by a new DMA system
(SPS/BAM).  Fortunately, there are some chips (MSM8960) that have both
ADM and SPS/BAM so there should be time to get those drivers in.

At least as my memory serves me:

  7201 - ADM
  8250 - ADM
  8660 - 2 ADMs, SPS/BAM
  8960 - 1 ADM, SPS/BAM

The ADM is mostly a regular DMA-type device.  Each channel can be
associated with a rate-control channel, which is needed for some
devices.  It also has a mode called "box mode", which works kind of
like a self-repeating scatter list.  This mode is needed for some of
the peripherals also on the MSM.

David

> On Tue, Mar 13, 2012 at 1:44 AM, Daniel Walker <dwalker at fifo99.com> wrote:
> 
>     On Mon, Mar 12, 2012 at 04:02:44PM +0530, Ravi Kumar V wrote:
>     > Add DMAEngine based driver using the old MSM DMA APIs internally.
> 
>     What do you mean by this?
> 
>     > The benefit of this approach is that not all the drivers
>     > have to get converted to DMAEngine APIs simultaneosly while
>     > both the drivers can stay enabled in the kernel. The client
>     > drivers using the old MSM APIs directly can now convert to
>     > DMAEngine one by one.
> 
>     Which drivers?
>    
>     Daniel
>     --
>     To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
>     the body of a message to majordomo at vger.kernel.org
>     More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From swarren at wwwdotorg.org  Tue Mar 13 15:36:27 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 13 Mar 2012 13:36:27 -0600
Subject: [PATCH] arm/tegra: pcie: fix return value of function
In-Reply-To: <1331617587-10714-1-git-send-email-mad_soft@inbox.ru>
References: <CAOesGMi0aqCjLsJ5wWXwFVQL2T8wtUuE14rFZ9h7NKHXcWAoqQ@mail.gmail.com>
 <1331617587-10714-1-git-send-email-mad_soft@inbox.ru>
Message-ID: <4F5FA1BB.5050002@wwwdotorg.org>

On 03/12/2012 11:46 PM, Dmitry Artamonow wrote:
> In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
> tegra_pcie_enable_controller() function type has been changed from
> void to int, but the last return statement wasn't converted, so
> function returns undefined value. Fix it.
> 
> Also while at it, address couple of minor concerns raised by reviewers:
> use usleep_range for delay, and lower the value of timeout to 300ms
> to be consistent with Nvidia Vibrante kernel.
> 
> Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From w.sang at pengutronix.de  Tue Mar 13 15:46:17 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 13 Mar 2012 20:46:17 +0100
Subject: [PATCH 1/5 v4] i2c/gpio: add DT support
In-Reply-To: <20120313164756.GF18320@game.jcrosoft.org>
References: <1331642024-19869-1-git-send-email-plagnioj@jcrosoft.com>
 <20120313140822.GD2488@pengutronix.de>
 <20120313164756.GF18320@game.jcrosoft.org>
Message-ID: <20120313194616.GE2488@pengutronix.de>

On Tue, Mar 13, 2012 at 05:47:56PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:08 Tue 13 Mar     , Wolfram Sang wrote:
> > On Tue, Mar 13, 2012 at 01:33:40PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > 
> > > update to use devm_kzalloc for private data
> > 
> > Hmm, you need really to work on the commit messages, not everybody is
> > familiar with DT and its implications:
> > 
> > "To achieve DT support, we need to populate a custom platform_data in a
> > private struct from DT information. To simplify code, the adapter and
> > algorithm are also put into the private struct."
> > 
> ok I put this can I get the Ack ?

Yes.

> I need to send the pull asap

Please, no rush. Makes it too easy for bugs to slip in...

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From rjw at sisk.pl  Tue Mar 13 16:36:56 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Tue, 13 Mar 2012 21:36:56 +0100
Subject: [INFO] : Hibernation and Resume between 2 similar devices
In-Reply-To: <28119509.96581331614425960.JavaMail.weblogic@epml27>
References: <28119509.96581331614425960.JavaMail.weblogic@epml27>
Message-ID: <201203132136.56353.rjw@sisk.pl>

On Tuesday, March 13, 2012, PINTU KUMAR wrote:
> Dear All,
> 
> I am just curious to know if it is possible to "Hibernate in one device" and "Resume the hibernated image from another similar device".

Not out of the box (you'd need to hack the kernel for that to work I think,
at least on x86) and the devices would need to be _exactly_ identical.
Moreover, if there is read-write mass storage in them, the filesystems on
both would have to be exactly identical as well (including metadata and data
layout etc.).

> Suppose, I have 2 exactly similar device (Laptop or mobile phone) with me.
> At one time I will be working on only one device at a time.
> Suppose I started my work on "Device 1"  with few opened application and later I wanted to switch to "Device 2" which is exactly similar to Device 1.
> I thought to hibernate (suspend to disk) the Device 1 and store the hibernated image as a swap file and later transfer to sd card.
> Then take of the sd card from Device 1 and put it into Device 2.
> Copy the swap file from sd card to Device 2 in some swap partition.
> Then reboot the Device 2 to Resume from this swap file.
> I will get back my Device 1 content in Device 2.
> 
> Hope this is possible ?

It may be possible to make it kind of work, but I wouldn't recommend it to
anyone.

Thanks,
Rafael


From u.kleine-koenig at pengutronix.de  Tue Mar 13 16:39:30 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Tue, 13 Mar 2012 21:39:30 +0100
Subject: [PATCH v2 5/5] Cortex-M3: Add support for exception handling
In-Reply-To: <20120309171026.GF14148@arm.com>
References: <CAHkRjk70x+Fn+Z4iUxSMc7Zq2cKBo_ka0tNhV0i5JWmEixpRrA@mail.gmail.com>
 <1330967042-25612-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <1330967042-25612-2-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120309171026.GF14148@arm.com>
Message-ID: <20120313203930.GD10400@pengutronix.de>

Hello Catalin,

On Fri, Mar 09, 2012 at 05:10:26PM +0000, Catalin Marinas wrote:
> On Mon, Mar 05, 2012 at 05:04:02PM +0000, Uwe Kleine-K?nig wrote:
> > To save r0, I'd readd OLD_R0 at the end of pt_regs (plus one buffer word
> > to get even alignment). Or would that already be unacceptable because
> > it's an ABI change, too?
> 
> If we preserve the first part of the pt_regs structure, we could add the
> exception return at the end (with two additional 32-bit words to
> preserve the 64-bit alignment).
I will do that.

> > --- a/arch/arm/kernel/entry-common.S
> > +++ b/arch/arm/kernel/entry-common.S
> > @@ -473,7 +480,7 @@ __sys_trace:
> >  
> >  	adr	lr, BSYM(__sys_trace_return)	@ return address
> >  	mov	scno, r0			@ syscall number (possibly new)
> > -	add	r1, sp, #S_R0 + S_OFF		@ pointer to regs
> > +	add	r1, sp, #S_OFF			@ pointer to regs
> 
> This change is no longer needed since S_R0 is no 0.
hmm, I thought I had removed them. Seems I didn't.
 
> > --- a/arch/arm/kernel/entry-header.S
> > +++ b/arch/arm/kernel/entry-header.S
> > @@ -26,7 +26,7 @@
> >   * The SWI code relies on the fact that R0 is at the bottom of the stack
> >   * (due to slow/fast restore user regs).
> >   */
> > -#if S_R0 != 0
> > +#if S_R0 != 0 && !defined(CONFIG_CPU_V7M)
> 
> Same here.
Same here ;-)
> 
> > +#ifdef CONFIG_CPU_V7M
> > +/*
> > + * ARMv7-M exception entry/exit macros.
> > + *
> > + * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
> > + * automatically saved on the current stack (32 words) before
> > + * switching to the exception stack (SP_main).
> > + *
> > + * If exception is taken while in user mode, SP_main is
> > + * empty. Otherwise, SP_main is aligned to 64 bit automatically
> > + * (CCR.STKALIGN set).
> > + *
> > + * Linux assumes that the interrupts are disabled when entering an
> > + * exception handler and it may BUG if this is not the case. Interrupts
> > + * are disabled during entry and reenabled in the exit macro.
> > + *
> > + * v7m_exception_fast_exit is used when returning from interrupts.
> > + *
> > + * v7m_exception_slow_exit is used when returning from SVC or PendSV.
> > + * When returning to kernel mode, we don't return from exception.
> > + */
> > +	.macro	v7m_exception_entry
> > +	cpsid	i
> > +	sub	sp, #S_FRAME_SIZE
> > +	stmia	sp, {r0-r12}
> > +
> > +	@ set r0 to the location of the registers saved by the core during
> > +	@ exception entry. Depending on the mode the cpu was in when the
> > +	@ exception happend that is either on the main or the process stack.
> > +	@ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
> > +	@ was used.
> > +	tst	lr, #0x4
> > +	mrsne	r0, psp
> > +	addeq	r0, sp, #S_FRAME_SIZE
> 
> Could we use some other registers here like r8-r12 so that we keep r0-r7
> for syscall handling later and avoid another ldmia?
One upside of using r0 is that

	addeq	r0, sp, #S_FRAME_SIZE

can be encoded in 16 bits while this is not possible and 32 bits are
needed. And I wonder if it's allowed to corrupt r8-r12?

> > +	add	r0, r0, #20		@ skip over r0-r3, r12
> > +	ldmia	r0!, {r1-r3}		@ load saved lr, return address and xPSR
> > +
> > +	@ calculate the orignal stack pointer value.
> > +	@ r0 currently points to the memory location just above the auto saved
> > +	@ xPSR. If the FP extension is implemented and bit 4 of EXC_RETURN is 0
> > +	@ then space was allocated for FP state. That is space for 18 32-bit
> > +	@ values. (If FP extension is unimplemented, bit 4 is 1.)
> > +	@ Additionally the cpu might automatically 8-byte align the stack. Bit 9
> > +	@ of the saved xPSR specifies if stack aligning took place. In this case
> > +	@ another 32-bit value is included in the stack.
> > +
> > +	tst	lr, #0x10
> > +	addeq	r0, r0, #576
> 
> I think you can ignore VFP for now. We could change it to do lazy
> save/restore and avoid the automatic state saving. If it does this while
> in kernel, it takes a bit of extra stack space.
If I understood correctly this will never trigger for kernel tasks,
won't it?

> > +	@ save original sp, lr, return address, xPSR and EXC_RETURN
> > +	add	r12, sp, #52
> 
> Just use S_ARM_SP or whatever asm offsets, it's easier to read.
OK, right.

> > +	stmia	r12, {r0-r3, lr}
> > +
> > +	@ restore registers for system calls
> > +	ldmia	sp, {r0-r12}
> 
> We could avoid reloading r0-r7 (that's what we actually need for
> syscalls) if we don't corrupt them.
See question above. And I noticed that because of tail-chaining we need
to load the register values from the exception frame at least once
anyhow. I will try to optimise here.

> > +	.endm
> > +
> > +	.macro	v7m_exception_fast_exit
> > +	@ read r12, sp, lr, return address, xPSR and EXC_RETURN
> > +	add	r12, sp, #48
> 
> S_ARM_R12?
> 
> > +	ldmia	r12, {r1-r5, lr}
> > +
> > +	tst     r5, #0x100
> > +	subne   r2, r2, #4
> > +
> > +	tst	lr, #0x10
> > +	subeq	r2, r2, #576
> > +
> > +	stmdb	r2!, {r1, r3-r5}		@ write saved r12, lr, return address and xPSR
> > +
> > +	ldmia	sp, {r1, r3-r5}			@ read saved r0-r3
> > +	stmdb	r2!, {r1, r3-r5}		@ write r0-r3 to basic exception frame
> > +
> > +	tst	lr, #0x4
> > +	msrne	psp, r2
> > +
> > +	ldmia	sp, {r0-r12}
> > +	add	sp, #S_FRAME_SIZE
> > +	cpsie	i
> > +	bx	lr
> > +	.endm
> 
> In the context v7m_exception_fast_exit is used (return from interrupts),
> the previously saved r0-r4,r12 etc. are still on the return stack and
> restored from there. There is no need for the ldmia/stmdb to re-create
> the interrupted process stack. Here we only need to make sure that we
> restore the registers that were not automatically saved and also move
> the kernel SP back to the original location (add S_FRAME_SIZE).
>
> We handle rescheduling and work pending by raising PendSV, so we get
> another interrupt which would be returned via the slow_exit macro.
I was not sure if a task could be preempted during an exception. So I
choosed to play save.

> > +	.macro	v7m_exception_slow_exit ret_r0
> > +	cpsid	i
> > +	ldr	lr, [sp, #S_EXCRET]		@ read exception LR
> > +	tst     lr, #0x8
> > +	bne	1f				@ go to thread mode using exception return
> > +
> > +	/*
> > +	 * return to kernel thread
> > +	 * sp is already set up (and might be unset in pt_regs), so only
> > +	 * restore r0-r12 and pc
> > +	 */
> > +	ldmia	sp, {r0-r12}
> > +	ldr	lr, [sp, #S_PC]
> > +	add	sp, sp, #S_FRAME_SIZE
> > +	cpsie	i
> > +	bx	lr
> > +	/*
> > +	 * return to userspace
> > +	 */
> > +1:
> > +	@ read original r12, sp, lr, pc, xPSR
> > +	add	r12, sp, #48
> > +	ldmia	r12, {r1-r5}
> > +
> > +	/* stack aligning */
> > +	tst	r5, #0x100
> > +	subne	r2, r2, #4
> > +
> > +	/* skip over stack space for fp extension */
> > +	tst	lr, #0x10
> > +	subeq	r2, r2, #576
> > +
> > +	/* write basic exception frame */
> > +	stmdb	r2!, {r1, r3-r5}		@ saved r12, lr, return address and xPSR
> > +	ldmia	sp, {r1, r3-r5}			@ read saved r0-r3
> > +	.if	\ret_r0
> > +	stmdb	r2!, {r0, r3-r5}		@ restore r0-r3
> > +	.else
> > +	stmdb	r2!, {r1, r3-r5}		@ restore r0-r3
> > +	.endif
> 
> This looks fine.
> 
> > +	msr	psp, r2
> > +
> > +	ldmia	sp, {r0-r12}			@ restore original r4-r11
> 
> Isn't this reading too much (optimisation)?
yeah, I think r12 isn't needed. For r0-r3 I'm not sure which is better:

	ldmia	sp, {r0-r11}
	add	sp, #S_FRAME_SIZE

vs.

	add	sp, #S_R4
	ldmia	sp, {r4-r11}
	add	sp, #S_FRAME_SIZE - S_R4

It's not described in the V7-M reverence. Do you know a document where I
can look that up?

> > +	add	sp, #S_FRAME_SIZE		@ restore the original MSP
> > +	cpsie	i
> > +	bx	lr
> > +	.endm
> > +#endif	/* CONFIG_CPU_V7M */
> ...
> > --- a/arch/arm/kernel/process.c
> > +++ b/arch/arm/kernel/process.c
> > @@ -452,7 +452,11 @@ asm(	".pushsection .text\n"
> >  #ifdef CONFIG_TRACE_IRQFLAGS
> >  "	bl	trace_hardirqs_on\n"
> >  #endif
> > +#ifdef CONFIG_CPU_V7M
> > +"	msr	primask, r7\n"
> > +#else
> >  "	msr	cpsr_c, r7\n"
> > +#endif
> >  "	mov	r0, r4\n"
> >  "	mov	lr, r6\n"
> >  "	mov	pc, r5\n"
> > @@ -491,6 +495,10 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
> >  	regs.ARM_r7 = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;
> >  	regs.ARM_pc = (unsigned long)kernel_thread_helper;
> >  	regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT;
> > +#ifdef CONFIG_CPU_V7M
> > +	/* Return to Handler mode */
> > +	regs.ARM_EXCRET = 0xfffffff1L;
> > +#endif
> 
> BTW, do we need to set this here? We don't return to a kernel thread via
> exception return.
But we need it to decide in slow_return if we should use exception
return or not. So yes, I think it's needed.

> I currently cannot see any obvious bugs in the code. Since you said it
> doesn't work, what are the symptoms?
I found two problems. One is I wasn't aware that r0-r3,r12 doesn't
necessarily need to match the values on exception entry (because of
tail-chaining) and in start_thread decreasing sp is wrong.

I will reimplement the three macros now with the new lessons learned.

Best regards and thanks for your input (here and on irc)
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From davidb at codeaurora.org  Tue Mar 13 16:47:10 2012
From: davidb at codeaurora.org (David Brown)
Date: Tue, 13 Mar 2012 13:47:10 -0700
Subject: [PATCH] arm: Add unwinding support for memset and memzero.
In-Reply-To: <1331574027-28542-1-git-send-email-lauraa@codeaurora.org>
References: <1331574027-28542-1-git-send-email-lauraa@codeaurora.org>
Message-ID: <20120313204710.GA1772@codeaurora.org>

On Mon, Mar 12, 2012 at 10:40:27AM -0700, Laura Abbott wrote:
> @@ -41,7 +43,7 @@ ENTRY(memset)
>  	blt	4f
>  
>  #if ! CALGN(1)+0
> -
> +UNWIND(.save {lr})
>  /*
>   * We need an extra register for this loop - save the return address and
>   * use the LR

Did you intend to remove these blank lines?

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From khc at pm.waw.pl  Tue Mar 13 17:15:29 2012
From: khc at pm.waw.pl (Krzysztof Halasa)
Date: Tue, 13 Mar 2012 22:15:29 +0100
Subject: [PATCH] ARM: remove ixp2000 platform
In-Reply-To: <4F5D39D1.4050000@snapgear.com> (Greg Ungerer's message of "Mon, 
 12 Mar 2012 09:48:33 +1000")
References: <1330450426-14639-1-git-send-email-robherring2@gmail.com>
 <201202281945.39419.arnd@arndb.de>
 <alpine.LFD.2.02.1203052035170.31242@xanadu.home>
 <201203061412.00073.arnd@arndb.de>
 <alpine.LFD.2.02.1203061146210.31242@xanadu.home>
 <CACRpkdYQpnSMVWUizEYHTjx_AK5Ai7dos0SBd208Wf5ZJLdrCw@mail.gmail.com>
 <20120307091409.GL17370@n2100.arm.linux.org.uk>
 <4F574C64.7010905@snapgear.com> <m3aa3nqpxz.fsf@intrepid.localdomain>
 <4F5D39D1.4050000@snapgear.com>
Message-ID: <m3sjhcdwy6.fsf@intrepid.localdomain>

Greg Ungerer <gerg at snapgear.com> writes:

>> The problematic one is IXP42x rev. A0. It has no support for hw mixed
>> mode (LE core + lane swapping where needed). Unfortunately this early
>
> It is not problematic if you are running your core BE right?

Right.
Of course it requires lane-swapping between PCI and the core/RAM. The
chip is set to hardware swap these accesses (block transfers and binary
structure layouts are correct, including bus master transfers) and
integer data (mostly u16/u32) are swapped again by the core
(readl/writel, also in-memory descriptors etc). All other peripherals
are always BE (NPE net coprocessors, EXP bus).

This all works fine on all revisions including the IXP425-A0.
-- 
Krzysztof Halasa


From b-cousson at ti.com  Tue Mar 13 17:35:22 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Tue, 13 Mar 2012 22:35:22 +0100
Subject: [PATCH 12/12] ARM: OMAP2+: board-omap4-*: Do not use anymore
 TWL6030_IRQ_BASE in board files
In-Reply-To: <20120313170756.GK12083@atomide.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-13-git-send-email-b-cousson@ti.com>
 <20120313170756.GK12083@atomide.com>
Message-ID: <4F5FBD9A.4030607@ti.com>

On 3/13/2012 6:07 PM, Tony Lindgren wrote:
> * Benoit Cousson<b-cousson at ti.com>  [120302 08:19]:
>> With the introduction of dynamically allocated IRQ in the twl6030 driver,
>> the board files can no longer rely of static IRQ defines like before.
>>
>> Retrieve the value dynamically allocated from the mmc ->  twl6030 init
>> callback.
>>
>> Note: The Panda board does not seems to use the card detect IRQ.
>
> Looks like this one is safe to merge via MFD and does not seem to
> cause any merge conflicts.
>
> This one should be folded into patch 08/12 to avoid boot issues
> for between patches 08 and 12 in this series. Other than that:

In fact there is no need to merge them. They should just be at the 
beginning of the series.

The first patch...
  mfd: twl6030-irq: Return twl6030_mmc_card_detect IRQ for board setup

-       return 0;
+
+       return twl6030_irq_base + MMCDETECT_INTR_OFFSET;

...will just return the proper interrupt number instead of 0, but at 
that time, the board is still using the static TWL6030_IRQ_BASE + 
MMCDETECT_INTR_OFFSET value.

Only the next one...
  ARM: OMAP2+: board-omap4-*: Do not use anymore TWL6030_IRQ_BASE in 
board files
...will switch from the static to the value returned by 
twl6030_mmc_card_detect and then it keeps working.

> Acked-by: Tony Lindgren<tony at atomide.com>

Cool, I'll send the pull request to Samuel ASAP.

Thanks,
Benoit


From davidb at codeaurora.org  Tue Mar 13 17:40:52 2012
From: davidb at codeaurora.org (David Brown)
Date: Tue, 13 Mar 2012 14:40:52 -0700
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <1331500100-31351-4-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-4-git-send-email-robherring2@gmail.com>
Message-ID: <20120313214052.GA16221@codeaurora.org>

On Sun, Mar 11, 2012 at 04:08:19PM -0500, Rob Herring wrote:

>  arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |    6 ------
>  arch/arm/mach-msm/include/mach/msm_iomap.h      |    6 ------

Acked-by: David Brown <davidb at codeaurora.org>

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From robherring2 at gmail.com  Tue Mar 13 17:48:00 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 16:48:00 -0500
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <1331366064-1273-3-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
Message-ID: <4F5FC090.90005@gmail.com>

Mike,

On 03/10/2012 01:54 AM, Mike Turquette wrote:
> The common clock framework defines a common struct clk useful across
> most platforms as well as an implementation of the clk api that drivers
> can use safely for managing clocks.
> 
> The net result is consolidation of many different struct clk definitions
> and platform-specific clock framework implementations.
> 
> This patch introduces the common struct clk, struct clk_ops and an
> implementation of the well-known clock api in include/clk/clk.h.
> Platforms may define their own hardware-specific clock structure and
> their own clock operation callbacks, so long as it wraps an instance of
> struct clk_hw.
> 
> See Documentation/clk.txt for more details.
> 
> This patch is based on the work of Jeremy Kerr, which in turn was based
> on the work of Ben Herrenschmidt.
> 
> Signed-off-by: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Mike Turquette <mturquette at ti.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Shawn Guo <shawn.guo at freescale.com>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Richard Zhao <richard.zhao at linaro.org>
> Cc: Saravana Kannan <skannan at codeaurora.org>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Stephen Boyd <sboyd at codeaurora.org>
> Cc: Amit Kucheria <amit.kucheria at linaro.org>
> Cc: Deepak Saxena <dsaxena at linaro.org>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Andrew Lunn <andrew at lunn.ch>

snip

> +
> +	/*
> +	 * walk the list of orphan clocks and reparent any that are children of
> +	 * this clock
> +	 */
> +	hlist_for_each_entry(orphan, tmp, &clk_orphan_list, child_node)

In __clk_init, this needs to be hlist_for_each_entry_safe as entries can
be removed.

Rob


From paul.gortmaker at windriver.com  Tue Mar 13 18:00:49 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Tue, 13 Mar 2012 18:00:49 -0400
Subject: Inconsistent kallsyms data on ARM.
Message-ID: <CAP=VYLoStscdVJretZ-Rkbp7V3Vsm8N0oWcjih7ruHFiDN7CiA@mail.gmail.com>

This bug(?)  has been seen to float from one ARM build to another since
I started tracking the day-to-day changes in Stephen's linux-next builds.

I see it was discussed earlier:

   https://lkml.org/lkml/2011/8/2/233
   https://lkml.org/lkml/2011/10/8/70

but no concrete cause was nailed down.  Can the linux-next build results
help shed some light on this in any way?  Since it seems sporadic, is
there value in embedding a diagnostic of some sort in the infrastructure
so that when the error is detected, that it prints out more detailed info?

I can provide links to failed linux-next builds, but at the moment, all they
really seem to have is the same repeated error message, like this one:

   http://kisskb.ellerman.id.au/kisskb/buildresult/5869367/

and I don't see that helping folks all that much....

Paul.


From stigge at antcom.de  Tue Mar 13 18:15:58 2012
From: stigge at antcom.de (Roland Stigge)
Date: Tue, 13 Mar 2012 23:15:58 +0100
Subject: [GIT PULL] LPC32xx: USB Support
Message-ID: <4F5FC71E.30907@antcom.de>

Hi Arnd and Olof,

now that Greg-KH has accepted the LPC32xx OHCI patches into usb-next,
I'm providing the respective lpc32xx platform code as described below.

It's on top of v3.3-rc5 and the LPC32xx patches in arm-soc. Thanks
Arnd for helping woth this.

Thanks in advance,

Roland



The following changes since commit a7e4c6a7145ee375a688e1701ae4c975d6c6419a:

  Merge branch 'lpc32xx/drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into lpc32xx/tmp (2012-03-13 21:15:40 +0100)

are available in the git repository at:


  git://git.antcom.de/linux-2.6.git lpc32xx/mach-lpc32xx-usb

for you to fetch changes up to 48a5dedfa78899dad50b3b4ae30f07e27e6591ab:

  ARM: LPC32xx: USB Support (2012-03-13 21:15:50 +0100)

----------------------------------------------------------------
Roland Stigge (1):
      ARM: LPC32xx: USB Support

 arch/arm/mach-lpc32xx/clock.c   |   87 ++++++++++++++++++++++++++++-----------
 arch/arm/mach-lpc32xx/common.c  |   26 ++++++++++++
 arch/arm/mach-lpc32xx/common.h  |    1 +
 arch/arm/mach-lpc32xx/phy3250.c |    1 +
 4 files changed, 91 insertions(+), 24 deletions(-)


From stigge at antcom.de  Tue Mar 13 18:21:30 2012
From: stigge at antcom.de (Roland Stigge)
Date: Tue, 13 Mar 2012 23:21:30 +0100
Subject: [GIT PULL] LPC32xx: Ethernet support
Message-ID: <4F5FC86A.70501@antcom.de>

Hi Arnd and Olof,

now that David Miller has accepted the LPC32xx Ethernet patches into
net-next, I'm providing the respective LPC32xx platform code as described
below.

It's on top of v3.3-rc5, the already existing LPC32xx patches in arm-soc
and the USB support patch. So please first pull the USB patch.

Thanks in advance,

Roland



The following changes since commit 48a5dedfa78899dad50b3b4ae30f07e27e6591ab:

  ARM: LPC32xx: USB Support (2012-03-13 21:15:50 +0100)

are available in the git repository at:

  git://git.antcom.de/linux-2.6.git lpc32xx/mach-lpc32xx-eth

for you to fetch changes up to c20b909be9ba27173294a52d08cab293ec030a2c:

  ARM: LPC32xx: Ethernet support (2012-03-13 21:23:07 +0100)

----------------------------------------------------------------
Roland Stigge (1):
      ARM: LPC32xx: Ethernet support

 arch/arm/mach-lpc32xx/Kconfig              |   25 +++++++++++++++++++++++++
 arch/arm/mach-lpc32xx/clock.c              |    2 +-
 arch/arm/mach-lpc32xx/common.c             |   21 +++++++++++++++++++++
 arch/arm/mach-lpc32xx/common.h             |    4 ++--
 arch/arm/mach-lpc32xx/include/mach/board.h |   24 ++++++++++++++++++++++++
 arch/arm/mach-lpc32xx/irq.c                |    4 ++++
 arch/arm/mach-lpc32xx/phy3250.c            |    2 ++
 7 files changed, 79 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-lpc32xx/include/mach/board.h


From rmallon at gmail.com  Tue Mar 13 18:22:37 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Wed, 14 Mar 2012 09:22:37 +1100
Subject: [PATCH v4 00/11] ep93xx: Move SoC private bits to core
In-Reply-To: <201203131235.53593.arnd@arndb.de>
References: <1331592502-9083-1-git-send-email-rmallon@gmail.com>
 <201203131235.53593.arnd@arndb.de>
Message-ID: <4F5FC8AD.4070505@gmail.com>

On 13/03/12 23:35, Arnd Bergmann wrote:

> On Monday 12 March 2012, Ryan Mallon wrote:
>> This patch series is an effort to move the ep93xx SoC specific code out
>> of drivers and include/mach into arch/arm/mach-ep93xx. This work
>> involves the following changes:
>>
>>  - Create a new private header called soc.h to replace most of 
>>    mach/include/ep93xx-regs.h
>>  - Move the Maverick crunch code from arch/arm/kernel to mach-ep93xx
>>  - Convert the ep93xx backlight and watchdog drivers to properly
>>    ioremap memory.
>>  - Move all system controller access to the ep93xx core code
>>
>> The only defines left in ep93xx-regs.h are for the APB UARTS which
>> are also needed in include/mach/uncompress.h and
>> include/mach/debug-macro.S.
>>
>> Patch 2 has already been merged to the ASoC tree and patch 5 has
>> already been merged to the watchdog tree. Neither patch has been
>> modified since they were applied, and are included here for
>> completeness and to avoid build errors. 
> 
> Looks all very nice, great work!
> 
>> All of the patches are against v3.3-rc7 and  now have reviewed-by
>> and/or acked-by tags except for patch 4 which has been changed
>> since the last version. Arnd, once I get an ack for the final patch
>> I can prepare a git branch for you to pull. I understand if this is
>> now too late for v3.4.
> 
> If there are no conflicts against the for-next branch and Olof agrees,
> I would probably let this one go in for v3.4. It's a nice cleanup
> and it will be easier to do your v3.5 patches if it's all merged.


Okay thanks. I'll try and fix up the minor bits and pieces that you and
Hartley pointed out and send a pull request later tonight.

I'm planning on using my tree for future ep93xx development, so that I
can aggregate any patches there to be included in arm-soc.

> 
> On a related note, I would like to understand better what your plans
> are for the future of ep93xx. My undestanding is that the product line
> is a dead end and there won't be any other compatible socs, but the
> Linux support is very much alive and supports all the existing hardware,
> is that correct?

Yeah, the product line is dead, but there are a handful of boards still
being used in production systems and we now support most of the
peripherals, I think IDE is the only major device missing support.

> There are currently eight board files (since all the dev boards got
> merged into one file), which seems very manageable and there should be
> no problem adding a few more over the years to come, if necessary.

I doubt there will be many new boards added.

> At the same time, the platform seems simple enough that you could
> also do a device tree port in rather in a fairly short time if you
> like, which would let you obsolete all the board files and add new
> machines just through device tree blobs.


Yeah, converting to device tree is one of my goals. I need to spend some
time reading through the device tree specification first.

~Ryan


From b-cousson at ti.com  Tue Mar 13 18:47:00 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Tue, 13 Mar 2012 23:47:00 +0100
Subject: OMAP DSS device tree design problems
In-Reply-To: <1331559930.2097.100.camel@deskari>
References: <1331559930.2097.100.camel@deskari>
Message-ID: <4F5FCE64.5070902@ti.com>

+ devicetree list and Mike T. for the clock aspect

Hi Tomi,

On 3/12/2012 2:45 PM, Tomi Valkeinen wrote:
> Hi,
>
> I'm struggling with the design of the DT data for OMAP display subsystem
> driver, and any thoughts and ideas are welcome. This mail is a rather
> long one, where I'm trying to show the different approaches I've
> thought.
>
> So the .dts format would be something like this, taking 4430SDP as an
> example. It's just an outline, missing dispc, hwmods,
> compatible-properties etc, which are not so relevant here.
>
> ocp {
> 	dss {
> 		dsi1 {
> 			taal {
>
> 			};
> 		};
> 	};
> };
>
> So there we have a Taal panel, connected to DSI1 output interface, which
> is part of the OMAP display subsystem.
>
> One thing to note here is that although there's only one panel under
> dsi1 in this case, the current SW supports having multiple panels under
> one output interface. And while the output can support only one active
> panel at a time, we do have boards where two panels are connected to one
> output, and there's some kind of HW switch used to select which panel is
> enabled.
>
> The first problem here is that I don't know how to manage the switch
> part. With current SW we have had the switch handling in the board
> files, in functions called when a display is enabled/disabled. I guess
> one option is to have the switch related code in their own drivers,
> totally apart from the dss code, perhaps offering a sysfs interface or
> such. And then, if the switch happens to be in the wrong position, the
> panel will fail in some way.

DT is supposed to reflect the HW capability, so if you do have two 
panels on a board, then both should be described in the DTS.

I'm just wondering if the multiple panels is something supported by the 
DSI protocol or it is a HW hacks done on TI board only?

Maybe in that case the DSI mux HW will have to be represented in the DT 
hierarchy as well.

> The second problem is about the DT properties. With multiple panels it's
> not possible to do this:
>
> dsi1 {
> 	dsi-ddr-clk =<250000000>;
>
> 	taal {
> 	};
>
> 	some-other-panel {
> 	};
> };
>
> because the panels could require different dsi clock rates. So we need
> something like this:
>
> dsi1 {
> 	taal {
> 		dsi-ddr-clk =<250000000>;
> 	};
>
> 	some-other-panel {
> 		dsi-ddr-clk =<350000000>;
> 	};
> };
>
> However, here the problem is that while ultimately we're interested in
> the ddr-clk rate, calculation of the rate is non-trivial and may need
> customizations at times. So instead of the clock rate we actually need
> to define a bunch of dividers/multipliers.

Well, in theory you should not. This is up to the clock provider to 
convert the clock rate in the proper n/m value. This is how it is done 
for the regular OMAP DPLLs.

> But these dividers are OMAP specific things, and do not belong to Taal
> driver. So this bring the question: is the general rule about DT node
> properties such that only the driver handling the particular node should
> read the properties in that node? So, in the example above, should the
> dsi driver only read props in the dsi1 and dsi2 nodes, and never look at
> props in the taal nodes?

Yes, because the taal parameters should be relative to the Taal HW spec 
that should not have a clue about the current DSI bus in used.

This is the clock provider that will have to handle that.

> So basically, can we do this:
>
> dsi1 {
> 	taal {
> 		omap-specific-clk-divs =<1 2 3 4 5 6 7>;
> 	};
>
> 	some-other-panel {
> 		omap-specific-clk-divs =<7 6 5 4 3 2 1>;
> 	};
> };
>
> and the Taal driver would ignore those, but dsi driver would use them?
> This looks like quite easy solution to this, but also doesn't feel
> right. So my current idea is to have clk-div tables in the dsi node,
> something like this:
>
> dsi1 {
> 	omap-specific-clk-divs =<
> 		250 1 2 3 4 5 6 7 /* divs that produce 250MHz clk */
> 		350 7 6 5 4 3 2 1 /* divs that produce 350MHz clk */
> 	>;

That's the idea, except that this will represent the clock provider.

>
> 	taal {
> 		dsi-ddr-clk =<250000000>;

And here you will have a phandle to the clock provider. And use it to 
set the proper clock rate.

> 	};
>
> 	some-other-panel {
> 		dsi-ddr-clk =<350000000>;
> 	};
> };
>
> Here the panel drivers would ask the DSI driver to configure DSI DDR clk
> of 250/350MHz, and the DSI driver would then use the lookup table to
> find the dividers. If the lookup fails, the DSI driver could fail or try
> to calculate the dividers itself. Other platforms could handle the DDR
> clk configuration however they see best.
>

Grant was working on the clock device tree binding. I'm not sure it got 
merged yet. But that should not there soon.

> ---
>
> Another thing related to DSI command mode panels is the DSI lane
> configuration, and I can't make my mind if they belong to the panel
> driver in some way or not.
>
> So, again taking SDP board and Taal as an example, we have 6 pads on
> OMAP which are used for communicating with Taal. The pads need to be
> muxed to DSI mode like any other OMAP pads. Currently the pad muxing is
> not touched by the driver, but I think it's doable in the DSI driver (as
> long as the DSI driver knows the required pad config).
>
> However, that's not enough.
>
> DSI uses differential pairs for communication (a "lane" consists of two
> wires), and we have always one clock lane, and a number of data lanes.
> In Taal's case we have a clock lane and two data lanes, which means 6
> pads/wires.
>
> We need to configure which of the OMAPs pads is used for which function,
> so, for example, pad x and x+1 are used for clock lane, and x is the
> negative pair and x+1 is the positive pair. And this configuration has
> to match the wiring going to the panel, so that clk+ from OMAP goes to
> clk+ in the panel.
>
> So it dts data we need something, perhaps, like below. Here we define
> the pad numbers and polarities in an array, where the first cell-pair is
> for clk, then data1, then data2 and so on (if there are more than two
> data lanes).
>
> lanes =<
> 	/* pad-pair number, polarity */
> 	1 0	/* DSI pad pair 1 is used for clk, pol +/-  */
> 	2 1	/* DSI pad pair 2 is used for data1, pol -/+ */
> 	0 0	/* DSI pad pair 0 is used for data2, pol +/- */
>> ;
>
> Now, I don't quite know where this data should be. If it's in the
> dsi-node, it doesn't work with multiple panels.

Is the lane configuration only dependent of the panel?

> But then, it's quite
> OMAP specific thing. While other platforms probably need some kind of
> pad configuration also, it may be something totally different. And so it
> doesn't feel right in the taal-node either.
>
> And a look-up table like in the clock case doesn't make much sense
> either, as we don't have a key here, as we had in the clock case (the
> dsi-ddr-clk).

The lane configuration code will belong to the DSI driver. The data will 
belong to the panel. The panel might use some phandle to the various DSI 
lane config a provide the needed information.

This look pretty similar to the pinmux device tree binding that is 
currently under discussion.

> So basically the only option I've come up with is to define the lane
> configuration in the panel's data, and let the dsi driver peek there and
> configure the HW. And this doesn't feel right.

This is fine, except for the last part. The panel driver should retrieve 
the data from the panel node, and call some DSI configuration API using 
the DSI phandle retrieved from the panel node as well or using the 
parent node directly if the hierarchy is always the same.

You should have a look at pinmux and clock binding discussion. Even the 
way GPIO binding is working should give you some hints.

Regards,
Benoit


From mturquette at ti.com  Tue Mar 13 18:41:21 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 13 Mar 2012 15:41:21 -0700
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <4F5FC090.90005@gmail.com>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
 <4F5FC090.90005@gmail.com>
Message-ID: <CAJOA=zMtaiHWmUJJO7eWEmGQkNmkzHnr0B4zneDrEEirFn3hAw@mail.gmail.com>

On Tue, Mar 13, 2012 at 2:48 PM, Rob Herring <robherring2 at gmail.com> wrote:
> Mike,
>
> On 03/10/2012 01:54 AM, Mike Turquette wrote:
>> The common clock framework defines a common struct clk useful across
>> most platforms as well as an implementation of the clk api that drivers
>> can use safely for managing clocks.
>>
>> The net result is consolidation of many different struct clk definitions
>> and platform-specific clock framework implementations.
>>
>> This patch introduces the common struct clk, struct clk_ops and an
>> implementation of the well-known clock api in include/clk/clk.h.
>> Platforms may define their own hardware-specific clock structure and
>> their own clock operation callbacks, so long as it wraps an instance of
>> struct clk_hw.
>>
>> See Documentation/clk.txt for more details.
>>
>> This patch is based on the work of Jeremy Kerr, which in turn was based
>> on the work of Ben Herrenschmidt.
>>
>> Signed-off-by: Mike Turquette <mturquette at linaro.org>
>> Signed-off-by: Mike Turquette <mturquette at ti.com>
>> Cc: Russell King <linux at arm.linux.org.uk>
>> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
>> Cc: Thomas Gleixner <tglx at linutronix.de>
>> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
>> Cc: Paul Walmsley <paul at pwsan.com>
>> Cc: Shawn Guo <shawn.guo at freescale.com>
>> Cc: Sascha Hauer <s.hauer at pengutronix.de>
>> Cc: Richard Zhao <richard.zhao at linaro.org>
>> Cc: Saravana Kannan <skannan at codeaurora.org>
>> Cc: Magnus Damm <magnus.damm at gmail.com>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
>> Cc: Linus Walleij <linus.walleij at stericsson.com>
>> Cc: Stephen Boyd <sboyd at codeaurora.org>
>> Cc: Amit Kucheria <amit.kucheria at linaro.org>
>> Cc: Deepak Saxena <dsaxena at linaro.org>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Cc: Andrew Lunn <andrew at lunn.ch>
>
> snip
>
>> +
>> + ? ? /*
>> + ? ? ?* walk the list of orphan clocks and reparent any that are children of
>> + ? ? ?* this clock
>> + ? ? ?*/
>> + ? ? hlist_for_each_entry(orphan, tmp, &clk_orphan_list, child_node)
>
> In __clk_init, this needs to be hlist_for_each_entry_safe as entries can
> be removed.

Thanks for the catch Rob.  I'll take this in.

Regards,
Mike

>
> Rob
>
> _______________________________________________
> linaro-dev mailing list
> linaro-dev at lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-dev


From olof at lixom.net  Tue Mar 13 18:49:54 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 15:49:54 -0700
Subject: [GIT PULL] one kernel panic fix for v3.3-rc7
In-Reply-To: <20120313183352.GN12083@atomide.com>
References: <20120313183352.GN12083@atomide.com>
Message-ID: <CAOesGMi+ySz9QZNZAZYRBD8J8i5TzmfVd+fBrpvSFsHOOQ3_aA@mail.gmail.com>

On Tue, Mar 13, 2012 at 11:33 AM, Tony Lindgren <tony at atomide.com> wrote:
> Hi Olof,
>
> Here's one more kernel panic fix that I dropped from last weeks
> fixes as it was still being discussed.
>
> This is a fix for the regression caused by fixing an earlier
> regression for smsc911x fixed regulators :(
>
> Turns out that we have more than one smsc911x on some boards,
> and the earlier fix causes a kernel panic for board trying to
> register second smsc911x instance, even if the second smsc911x
> is on an add-on board that is not connected.
>
> Note that the boards with second smsc911x will also need to be
> patched later on to provide their own regulators.
>
> Regards,
>
> Tony
>
>
> The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
> ?Linus Torvalds (1):
> ? ? ? ?Linux 3.3-rc7
>
> are available in the git repository at:
>
> ?git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fix-smsc911x-regulator
>
> Kevin Hilman (1):
> ? ? ?ARM: OMAP2+: gpmc-smsc911x: only register regulator for first instance

Thanks, pulled.


-Olof


From robherring2 at gmail.com  Tue Mar 13 18:54:47 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 17:54:47 -0500
Subject: [PULL] generic irq chip and pl061 irqdomain support
In-Reply-To: <4F5437FE.2000306@gmail.com>
References: <4F3ADFE7.4090409@gmail.com> <4F5437FE.2000306@gmail.com>
Message-ID: <4F5FD037.5000703@gmail.com>

On 03/04/2012 09:50 PM, Rob Herring wrote:
> Grant,
> 
> On 02/14/2012 04:27 PM, Rob Herring wrote:
>> Grant,
>>
>> Please pull. This is based on your current branch which you have said
>> you plan to rebase, so feel free to rebase these as you need to. This
>> has been tested on highbank and i.MX5.
>>
> 
> Ping.
> 
> I've rebased onto your current tree. Updated pull request:
> 
> The following changes since commit 280ad7fda5f95211857fda38960f2b6fdf6edd3e:
> 
>   mfd: twl-core: Add IRQ_DOMAIN dependency (2012-02-26 16:48:06 -0700)
> 
> are available in the git repository at:
>   git://sources.calxeda.com/kernel/linux.git irqdomain-for-grant
> 
> Rob Herring (3):
>       ARM: kconfig: always select IRQ_DOMAIN
>       irq: add irq_domain support to generic-chip
>       gpio: pl061: enable interrupts with DT style binding
> 
>  .../devicetree/bindings/gpio/pl061-gpio.txt        |   15 ++
>  arch/arm/Kconfig                                   |    2 +-
>  arch/arm/common/Kconfig                            |    2 -
>  drivers/gpio/gpio-pl061.c                          |   48 ++++---
>  include/linux/irq.h                                |   15 ++
>  kernel/irq/generic-chip.c                          |  152
> +++++++++++++++++---
>  6 files changed, 186 insertions(+), 48 deletions(-)
> 

Ping again...

Rob


From akpm at linux-foundation.org  Tue Mar 13 19:11:38 2012
From: akpm at linux-foundation.org (Andrew Morton)
Date: Tue, 13 Mar 2012 16:11:38 -0700
Subject: [PATCH 3/3] led-triggers: create a trigger for CPU activity
In-Reply-To: <1331197863-25564-3-git-send-email-bryan.wu@canonical.com>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
 <1331197863-25564-3-git-send-email-bryan.wu@canonical.com>
Message-ID: <20120313161138.cbeb594d.akpm@linux-foundation.org>

On Thu,  8 Mar 2012 17:11:03 +0800
Bryan Wu <bryan.wu at canonical.com> wrote:

> Attempting to consolidate the ARM LED code, this removes the
> custom RealView LED trigger code to turn LEDs on and off in
> response to CPU activity and replace it with a standard trigger.
> 
> (bryan.wu at canonical.com:
> It moves arch/arm/kernel/leds.c syscore stubs into this trigger.
> It also provides ledtrig_cpu trigger event stub in <linux/leds.h>.
> Although it was inspired by ARM work, it can be used in other arch.)

The patch doesn't "remove" or "move" anything.  It wholly consists of
additions.  Confused.

> Cc: Richard Purdie <rpurdie at rpsys.net>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
> 
> Reviewed-by: Jamie Iles <jamie at jamieiles.com>
> Tested-by: Jochen Friedrich <jochen at scram.de>

The authorship is a bit unclear.  You're the primary author, yes?

> --- /dev/null
> +++ b/drivers/leds/ledtrig-cpu.c
> @@ -0,0 +1,119 @@
> +/*
> + * ledtrig-cpu.c - LED trigger based on CPU activity
> + *
> + * Copyright 2011 Linus Walleij <linus.walleij at linaro.org>
> + * Copyright 2011 Bryan Wu <bryan.wu at canonical.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/slab.h>
> +#include <linux/percpu.h>
> +#include <linux/syscore_ops.h>
> +#include "leds.h"
> +
> +static DEFINE_PER_CPU(struct led_trigger *, cpu_trig);
> +static DEFINE_PER_CPU(char [8], trig_name);
> +
> +void ledtrig_cpu(enum cpu_led_event ledevt)
> +{
> +	struct led_trigger *trig = __get_cpu_var(cpu_trig);
> +
> +	if (!trig)
> +		return;
> +
> +	/* Locate the correct CPU LED */
> +	switch (ledevt) {
> +	case CPU_LED_IDLE_END:
> +	case CPU_LED_START:
> +		/* Will turn the LED on, max brightness */
> +		led_trigger_event(trig, LED_FULL);
> +		break;
> +
> +	case CPU_LED_IDLE_START:
> +	case CPU_LED_STOP:
> +	case CPU_LED_HALTED:
> +		/* Will turn the LED off */
> +		led_trigger_event(trig, LED_OFF);
> +		break;
> +
> +	default:
> +		/* Will leave the LED as it is */
> +		break;
> +	}
> +}
> +EXPORT_SYMBOL(ledtrig_cpu);

This is a global, exported-to-modules API function.  It should be
documented.

It should especially be documented if it has tricky unobvious calling
conditions, as this function does.  AFAICT it must be called by code
which is running on the target CPU and which is pinned to that CPU via
either preempt_disable() or set_cpus_allowed().

Or something else - I don't have a clue, and the author didn't tell me :(

> +static int ledtrig_cpu_syscore_suspend(void)
> +{
> +	ledtrig_cpu(CPU_LED_STOP);
> +	return 0;
> +}
> +
> +static void ledtrig_cpu_syscore_resume(void)
> +{
> +	ledtrig_cpu(CPU_LED_START);
> +}
> +
> +static void ledtrig_cpu_syscore_shutdown(void)
> +{
> +	ledtrig_cpu(CPU_LED_HALTED);
> +}
> +
> +static struct syscore_ops ledtrig_cpu_syscore_ops = {
> +	.shutdown	= ledtrig_cpu_syscore_shutdown,
> +	.suspend	= ledtrig_cpu_syscore_suspend,
> +	.resume		= ledtrig_cpu_syscore_resume,
> +};
> +
> +static void __init ledtrig_cpu_register(void *info)
> +{
> +	int cpuid = smp_processor_id();
> +	struct led_trigger *trig;
> +	char *name = __get_cpu_var(trig_name);
> +
> +	snprintf(name, 8, "cpu%d", cpuid);

This explodes at 10,000 CPUS ;)

> +	led_trigger_register_simple(name, &trig);
> +
> +	pr_info("LED trigger %s indicate activity on CPU %d\n",
> +		trig->name, cpuid);
> +
> +	__get_cpu_var(cpu_trig) = trig;
> +}
> +
> +static void __exit ledtrig_cpu_unregister(void *info)
> +{
> +	struct led_trigger *trig = __get_cpu_var(cpu_trig);
> +	char *name = __get_cpu_var(trig_name);
> +
> +	led_trigger_unregister_simple(trig);
> +	__get_cpu_var(cpu_trig) = NULL;
> +	memset(name, 0, 8);
> +}
> +
> +static int __init ledtrig_cpu_init(void)
> +{
> +	on_each_cpu(ledtrig_cpu_register, NULL, 1);

on_each_cpu() only calls the function on presently-onlined CPUs.  How
does this code interact with CPU hotplug?

And as you've already noted, led_trigger_register_simple() is totally
not callable from interrupt context.  And we're not just talking about
under local_irq_disable() here: on_each_cpu() will raise cross-cpu hard
interrupts to call the function on remote CPUs.  We end up trying to do
down_write() and who knows what else from within a hard interrupt
handler.

> --- a/include/linux/leds.h
> +++ b/include/linux/leds.h
> @@ -210,4 +210,19 @@ struct gpio_led_platform_data {
>  struct platform_device *gpio_led_register_device(
>  		int id, const struct gpio_led_platform_data *pdata);
>  
> +#if defined(CONFIG_LEDS_TRIGGER_CPU) || defined(CONFIG_LEDS_TRIGGER_CPU_MODULE)
> +enum cpu_led_event {
> +	CPU_LED_IDLE_START,	/* CPU enters idle */
> +	CPU_LED_IDLE_END,	/* CPU idle ends */
> +	CPU_LED_START,		/* Machine starts, especially resume */
> +	CPU_LED_STOP,		/* Machine stops, especially suspend */
> +	CPU_LED_HALTED,		/* Machine shutdown */
> +};
> +
> +/* Use this routine to handle LEDs */
> +extern void ledtrig_cpu(enum cpu_led_event evt);
> +#else
> +#define ledtrig_cpu(evt) do {} while (0)
> +#endif

a) the stub function should be written in C, not CPP please

b) it makes no sense to provide the stub function when the
   definition of its argument type (enum cpu_led_event) is not
   also available.



From timur at freescale.com  Tue Mar 13 19:12:58 2012
From: timur at freescale.com (Timur Tabi)
Date: Tue, 13 Mar 2012 18:12:58 -0500
Subject: [PATCH v4 06/10] ASoC: fsl: check property 'compatible' for the
 machine name
In-Reply-To: <1331553537-19789-7-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
 <1331553537-19789-7-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F5FD47A.9040808@freescale.com>

Shawn Guo wrote:
> Check /compatible rather than /model to determine the machine name.
> The p1022ds older device trees get a different /model from the new
> ones, while /compatible is consistent there, so checking /compatible
> will save the bother of detecting older p1022ds device trees.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---

I'm pretty sure I ack'd this patch already.  Regardless, it does not apply
to for-3.4.

Applying: ASoC: fsl: check property 'compatible' for the machine name
error: patch failed: sound/soc/fsl/fsl_ssi.c:716
error: sound/soc/fsl/fsl_ssi.c: patch does not apply
error: patch failed: sound/soc/fsl/mpc8610_hpcd.c:402
error: sound/soc/fsl/mpc8610_hpcd.c: patch does not apply
error: patch failed: sound/soc/fsl/p1022_ds.c:403
error: sound/soc/fsl/p1022_ds.c: patch does not apply

-- 
Timur Tabi
Linux kernel developer at Freescale



From broonie at opensource.wolfsonmicro.com  Tue Mar 13 19:15:02 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 13 Mar 2012 23:15:02 +0000
Subject: [PATCH v4 06/10] ASoC: fsl: check property 'compatible' for the
 machine name
In-Reply-To: <4F5FD47A.9040808@freescale.com>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
 <1331553537-19789-7-git-send-email-shawn.guo@linaro.org>
 <4F5FD47A.9040808@freescale.com>
Message-ID: <20120313231502.GR3177@opensource.wolfsonmicro.com>

On Tue, Mar 13, 2012 at 06:12:58PM -0500, Timur Tabi wrote:

> I'm pretty sure I ack'd this patch already.  Regardless, it does not apply
> to for-3.4.

You did, it doesn't apply because it's already applied.
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From grant.likely at secretlab.ca  Tue Mar 13 19:18:34 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 13 Mar 2012 17:18:34 -0600
Subject: [PULL] generic irq chip and pl061 irqdomain support
In-Reply-To: <4F5FD037.5000703@gmail.com>
References: <4F3ADFE7.4090409@gmail.com> <4F5437FE.2000306@gmail.com>
 <4F5FD037.5000703@gmail.com>
Message-ID: <20120313231834.8B6AE3E050F@localhost>

On Tue, 13 Mar 2012 17:54:47 -0500, Rob Herring <robherring2 at gmail.com> wrote:
> On 03/04/2012 09:50 PM, Rob Herring wrote:
> > Grant,
> > 
> > On 02/14/2012 04:27 PM, Rob Herring wrote:
> >> Grant,
> >>
> >> Please pull. This is based on your current branch which you have said
> >> you plan to rebase, so feel free to rebase these as you need to. This
> >> has been tested on highbank and i.MX5.
> >>
> > 
> > Ping.
> > 
> > I've rebased onto your current tree. Updated pull request:
> > 
> > The following changes since commit 280ad7fda5f95211857fda38960f2b6fdf6edd3e:
> > 
> >   mfd: twl-core: Add IRQ_DOMAIN dependency (2012-02-26 16:48:06 -0700)
> > 
> > are available in the git repository at:
> >   git://sources.calxeda.com/kernel/linux.git irqdomain-for-grant
> > 
> > Rob Herring (3):
> >       ARM: kconfig: always select IRQ_DOMAIN
> >       irq: add irq_domain support to generic-chip
> >       gpio: pl061: enable interrupts with DT style binding
> > 
> >  .../devicetree/bindings/gpio/pl061-gpio.txt        |   15 ++
> >  arch/arm/Kconfig                                   |    2 +-
> >  arch/arm/common/Kconfig                            |    2 -
> >  drivers/gpio/gpio-pl061.c                          |   48 ++++---
> >  include/linux/irq.h                                |   15 ++
> >  kernel/irq/generic-chip.c                          |  152
> > +++++++++++++++++---
> >  6 files changed, 186 insertions(+), 48 deletions(-)
> > 
> 
> Ping again...

Okay, I've pulled this in.  I need to do some compile testing before I push
it out.

g.


From shawn.guo at linaro.org  Tue Mar 13 19:21:51 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 14 Mar 2012 07:21:51 +0800
Subject: [PATCH v4 06/10] ASoC: fsl: check property 'compatible' for the
 machine name
In-Reply-To: <20120313231502.GR3177@opensource.wolfsonmicro.com>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
 <1331553537-19789-7-git-send-email-shawn.guo@linaro.org>
 <4F5FD47A.9040808@freescale.com>
 <20120313231502.GR3177@opensource.wolfsonmicro.com>
Message-ID: <20120313232149.GA21337@S2101-09.ap.freescale.net>

On Tue, Mar 13, 2012 at 11:15:02PM +0000, Mark Brown wrote:
> On Tue, Mar 13, 2012 at 06:12:58PM -0500, Timur Tabi wrote:
> 
> > I'm pretty sure I ack'd this patch already.  Regardless, it does not apply
> > to for-3.4.
> 
> You did, it doesn't apply because it's already applied.

My bad.  I forgot rebasing the series on the latest sound tree.

-- 
Regards,
Shawn


From robherring2 at gmail.com  Tue Mar 13 19:22:20 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 18:22:20 -0500
Subject: [PATCH 0/7] Highbank clock support using DT
Message-ID: <1331680947-29861-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

This series adds clock support to highbank using common clock
infrastructure and DT clock bindings. This is based on DT clock
support cherry-picked from Grant's devicetree/test-clocks branch
and Mike T's v6 common clock infrastructure series.

It supports initialization of the clocks in any order at least in my
relatively simple case of 1 clock output per DT node. 

Rob

Grant Likely (3):
  of: add clock providers
  of: Add of_property_match_string() to find index into a string list
  dt/clock: Add handling for fixed clocks and a clock node setup
    iterator

Rob Herring (4):
  clk: fix orphan list iterator to be safe
  dt/clock: add a simple provider get function
  dt/clock: add function to get parent clock name
  clk: add highbank clock support

 .../devicetree/bindings/clock/clock-bindings.txt   |  116 +++++++
 .../devicetree/bindings/clock/fixed-clock.txt      |   21 ++
 arch/arm/Kconfig                                   |    1 +
 arch/arm/boot/dts/highbank.dts                     |   76 +++++
 arch/arm/boot/dts/testcases/tests-phandle.dtsi     |    2 +
 arch/arm/mach-highbank/Makefile                    |    2 +-
 arch/arm/mach-highbank/clock.c                     |   62 ----
 arch/arm/mach-highbank/highbank.c                  |   16 +
 drivers/clk/Makefile                               |    2 +
 drivers/clk/clk-highbank.c                         |  335 ++++++++++++++++++++
 drivers/clk/clk.c                                  |    4 +-
 drivers/clk/clkdev.c                               |    9 +
 drivers/of/Kconfig                                 |    6 +
 drivers/of/Makefile                                |    1 +
 drivers/of/base.c                                  |   36 ++
 drivers/of/clock.c                                 |  236 ++++++++++++++
 drivers/of/selftest.c                              |   29 ++
 include/linux/of.h                                 |    3 +
 include/linux/of_clk.h                             |   43 +++
 19 files changed, 935 insertions(+), 65 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/clock-bindings.txt
 create mode 100644 Documentation/devicetree/bindings/clock/fixed-clock.txt
 delete mode 100644 arch/arm/mach-highbank/clock.c
 create mode 100644 drivers/clk/clk-highbank.c
 create mode 100644 drivers/of/clock.c
 create mode 100644 include/linux/of_clk.h

-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar 13 19:22:21 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 18:22:21 -0500
Subject: [PATCH 1/7] clk: fix orphan list iterator to be safe
In-Reply-To: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331680947-29861-2-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

__clk_reparent can remove orphans, so the list iterator needs to be the
safe from removal version.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 drivers/clk/clk.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index c7c3bc5..802eda4 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1172,7 +1172,7 @@ void __clk_init(struct device *dev, struct clk *clk)
 {
 	int i;
 	struct clk *orphan;
-	struct hlist_node *tmp;
+	struct hlist_node *tmp, *tmp2;
 
 	if (!clk)
 		return;
@@ -1246,7 +1246,7 @@ void __clk_init(struct device *dev, struct clk *clk)
 	 * walk the list of orphan clocks and reparent any that are children of
 	 * this clock
 	 */
-	hlist_for_each_entry(orphan, tmp, &clk_orphan_list, child_node)
+	hlist_for_each_entry_safe(orphan, tmp, tmp2, &clk_orphan_list, child_node)
 		__clk_reparent(orphan, __clk_init_parent(orphan));
 
 	/*
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar 13 19:22:22 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 18:22:22 -0500
Subject: [PATCH 2/7] of: add clock providers
In-Reply-To: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331680947-29861-3-git-send-email-robherring2@gmail.com>

From: Grant Likely <grant.likely at secretlab.ca>

Based on work by Ben Herrenschmidt and Jeremy Kerr, this patch adds an
of_clk_get function to allow platforms to retrieve clock data from the
device tree.

Platform register a provider through of_clk_add_provider, which will be
called when a device references the provider's OF node for a clock
reference.

v3: - Clarified documentation

v2: - fixed errant ';' causing compile error
    - Editorial fixes from Shawn Guo
    - merged in adding lookup to clkdev
    - changed property names to match established convention. After
      working with the binding a bit it really made more sense to follow the
      lead of 'reg', 'gpios' and 'interrupts' by making the input simply
      'clocks' & 'clock-names' instead of 'clock-input-*', and to only use
      clock-output* for the producer nodes. (Sorry Shawn, this will mean
      you need to change some code, but it should be trivial)
    - Add ability to inherit clocks from parent nodes by using an empty
      'clock-ranges' property.  Useful for busses.  I could use some feedback
      on the new property name, 'clock-ranges' doesn't feel right to me.

Signed-off-by: Grant Likely <grant.likely at secretlab.ca>
Reviewed-by: Shawn Guo <shawn.guo at freescale.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Sascha Hauer <kernel at pengutronix.de>
Cc: Mike Turquette <mturquette at ti.com>
---
 .../devicetree/bindings/clock/clock-bindings.txt   |  116 ++++++++++++++
 .../devicetree/bindings/clock/fixed-clock.txt      |   21 +++
 drivers/clk/clkdev.c                               |    9 +
 drivers/of/Kconfig                                 |    6 +
 drivers/of/Makefile                                |    1 +
 drivers/of/clock.c                                 |  165 ++++++++++++++++++++
 include/linux/of_clk.h                             |   37 +++++
 7 files changed, 355 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/clock-bindings.txt
 create mode 100644 Documentation/devicetree/bindings/clock/fixed-clock.txt
 create mode 100644 drivers/of/clock.c
 create mode 100644 include/linux/of_clk.h

diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
new file mode 100644
index 0000000..3cb6746
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -0,0 +1,116 @@
+This binding is a work-in-progress, and are based on some experimental
+work by benh[1].
+
+Sources of clock signal can be represented by any node in the device
+tree.  Those nodes are designated as clock providers.  Clock consumer
+nodes use a phandle and clock specifier pair to connect clock provider
+outputs to clock inputs.  Similar to the gpio specifiers, a clock
+specifier is an array of one more more cells identifying the clock
+output on a device.  The length of a clock specifier is defined by the
+value of a #clock-cells property in the clock provider node.
+
+[1] http://patchwork.ozlabs.org/patch/31551/
+
+==Clock providers==
+
+Required properties:
+#clock-cells:	   Number of cells in a clock specifier; typically will be
+		   set to 1
+
+Optional properties:
+clock-output-names: Recommended to be a list of strings of clock output signal
+		    names indexed by the first cell in the clock specifier.
+		    However, the meaning of clock-output-name is domain
+		    specific to the clock provider, and is only provided to
+		    encourage using the same meaning for the majority of clock
+		    providers.  This format may not work for clock providers
+		    using a complex clock specifier format.  In those cases it
+		    is recommended to omit this property and create a binding
+		    specific names property.
+
+		    Clock consumer nodes must never directly reference
+		    the provider's clock-output-name property.
+
+For example:
+
+    oscillator {
+        #clock-cells = <1>;
+        clock-output-names = "ckil", "ckih";
+    };
+
+- this node defines a device with two clock outputs, the first named
+  "ckil" and the second named "ckih".  Consumer nodes always reference
+  clocks by index. The names should reflect the clock output signal
+  names for the device.
+
+==Clock consumers==
+
+Required properties:
+clocks:		List of phandle and clock specifier pairs, one pair
+		for each clock input to the device.  Note: if the
+		clock provider specifies '0' for #clock-cells, then
+		only the phandle portion of the pair will appear.
+
+Optional properties:
+clock-names:	List of clock input name strings sorted in the same
+		order as the clocks property.  Consumers drivers
+		will use clock-names to match clock input names
+		with clocks specifiers.
+clock-ranges:	Empty property indicating that child nodes can inherit named
+		clocks from this node. Useful for bus nodes to provide a
+		clock to their children.
+
+For example:
+
+    device {
+        clocks = <&osc 1>, <&ref 0>;
+        clock-names = "baud", "register";
+    };
+
+
+This represents a device with two clock inputs, named "baud" and "register".
+The baud clock is connected to output 1 of the &osc device, and the register
+clock is connected to output 0 of the &ref.
+
+==Example==
+
+    /* external oscillator */
+    osc: oscillator {
+        compatible = "fixed-clock";
+        #clock-cells = <1>;
+        clock-frequency  = <32678>;
+        clock-output-names = "osc";
+    };
+
+    /* phase-locked-loop device, generates a higher frequency clock
+     * from the external oscillator reference */
+    pll: pll at 4c000 {
+        compatible = "vendor,some-pll-interface"
+        #clock-cells = <1>;
+        clocks = <&osc 0>;
+        clock-names = "ref";
+        reg = <0x4c000 0x1000>;
+        clock-output-names = "pll", "pll-switched";
+    };
+
+    /* UART, using the low frequency oscillator for the baud clock,
+     * and the high frequency switched PLL output for register
+     * clocking */
+    uart at a000 {
+        compatible = "fsl,imx-uart";
+        reg = <0xa000 0x1000>;
+        interrupts = <33>;
+        clocks = <&osc 0>, <&pll 1>;
+        clock-names = "baud", "register";
+    };
+
+This DT fragment defines three devices: an external oscillator to provide a
+low-frequency reference clock, a PLL device to generate a higher frequency
+clock signal, and a UART.
+
+* The oscillator is fixed-frequency, and provides one clock output, named "osc".
+* The PLL is both a clock provider and a clock consumer. It uses the clock
+  signal generated by the external oscillator, and provides two output signals
+  ("pll" and "pll-switched").
+* The UART has its baud clock connected the external oscillator and its
+  register clock connected to the PLL clock (the "pll-switched" signal)
diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.txt b/Documentation/devicetree/bindings/clock/fixed-clock.txt
new file mode 100644
index 0000000..9a75342
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fixed-clock.txt
@@ -0,0 +1,21 @@
+Binding for simple fixed-rate clock sources.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
+
+Required properties:
+- compatible : shall be "fixed-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clock-frequency : frequency of clock in Hz. May be multiple cells.
+
+Optional properties:
+- gpios : From common gpio binding; gpio connection to clock enable pin.
+- clock-output-names : From common clock binding
+
+Example:
+	clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000000>;
+	};
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 6db161f..43628d0 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -19,6 +19,8 @@
 #include <linux/mutex.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_clk.h>
 
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
@@ -78,6 +80,13 @@ EXPORT_SYMBOL(clk_get_sys);
 struct clk *clk_get(struct device *dev, const char *con_id)
 {
 	const char *dev_id = dev ? dev_name(dev) : NULL;
+	struct clk *clk;
+
+	if (dev) {
+		clk = of_clk_get_by_name(dev->of_node, con_id);
+		if (clk && __clk_get(clk))
+			return clk;
+	}
 
 	return clk_get_sys(dev_id, con_id);
 }
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index 268163d..b49ab9c 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -47,6 +47,12 @@ config OF_IRQ
 	def_bool y
 	depends on !SPARC
 
+config OF_CLOCK
+	def_bool y
+	depends on HAVE_CLK
+	help
+	  OpenFirmware clock accessors
+
 config OF_DEVICE
 	def_bool y
 
diff --git a/drivers/of/Makefile b/drivers/of/Makefile
index a73f5a5..e7ad1e9 100644
--- a/drivers/of/Makefile
+++ b/drivers/of/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_OF_ADDRESS)  += address.o
 obj-$(CONFIG_OF_IRQ)    += irq.o
 obj-$(CONFIG_OF_DEVICE) += device.o platform.o
 obj-$(CONFIG_OF_GPIO)   += gpio.o
+obj-$(CONFIG_OF_CLOCK)	+= clock.o
 obj-$(CONFIG_OF_I2C)	+= of_i2c.o
 obj-$(CONFIG_OF_NET)	+= of_net.o
 obj-$(CONFIG_OF_SPI)	+= of_spi.o
diff --git a/drivers/of/clock.c b/drivers/of/clock.c
new file mode 100644
index 0000000..6519e96
--- /dev/null
+++ b/drivers/of/clock.c
@@ -0,0 +1,165 @@
+/*
+ * Clock infrastructure for device tree platforms
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_clk.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+
+/**
+ * struct of_clk_provider - Clock provider registration structure
+ * @link: Entry in global list of clock providers
+ * @node: Pointer to device tree node of clock provider
+ * @get: Get clock callback.  Returns NULL or a struct clk for the
+ *       given clock specifier
+ * @data: context pointer to be passed into @get callback
+ */
+struct of_clk_provider {
+	struct list_head link;
+
+	struct device_node *node;
+	struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
+	void *data;
+};
+
+static LIST_HEAD(of_clk_providers);
+static DEFINE_MUTEX(of_clk_lock);
+
+/**
+ * of_clk_add_provider() - Register a clock provider for a node
+ * @np: Device node pointer associated with clock provider
+ * @clk_src_get: callback for decoding clock
+ * @data: context pointer for @clk_src_get callback.
+ */
+int of_clk_add_provider(struct device_node *np,
+			struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
+						   void *data),
+			void *data)
+{
+	struct of_clk_provider *cp;
+
+	cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
+	if (!cp)
+		return -ENOMEM;
+
+	cp->node = of_node_get(np);
+	cp->data = data;
+	cp->get = clk_src_get;
+
+	mutex_lock(&of_clk_lock);
+	list_add(&cp->link, &of_clk_providers);
+	mutex_unlock(&of_clk_lock);
+	pr_debug("Added clock from %s\n", np->full_name);
+
+	return 0;
+}
+
+/**
+ * of_clk_del_provider() - Remove a previously registered clock provider
+ * @np: Device node pointer associated with clock provider
+ */
+void of_clk_del_provider(struct device_node *np)
+{
+	struct of_clk_provider *cp;
+
+	mutex_lock(&of_clk_lock);
+	list_for_each_entry(cp, &of_clk_providers, link) {
+		if (cp->node == np) {
+			list_del(&cp->link);
+			of_node_put(cp->node);
+			kfree(cp);
+			break;
+		}
+	}
+	mutex_unlock(&of_clk_lock);
+}
+
+static struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec)
+{
+	struct of_clk_provider *provider;
+	struct clk *clk = NULL;
+
+	/* Check if we have such a provider in our array */
+	mutex_lock(&of_clk_lock);
+	list_for_each_entry(provider, &of_clk_providers, link) {
+		if (provider->node == clkspec->np)
+			clk = provider->get(clkspec, provider->data);
+		if (clk)
+			break;
+	}
+	mutex_unlock(&of_clk_lock);
+
+	return clk;
+}
+
+struct clk *of_clk_get(struct device_node *np, int index)
+{
+	struct of_phandle_args clkspec;
+	struct clk *clk;
+	int rc;
+
+	if (index < 0)
+		return NULL;
+
+	rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
+					&clkspec);
+	if (rc)
+		return NULL;
+
+	clk = __of_clk_get_from_provider(&clkspec);
+	of_node_put(clkspec.np);
+	return clk;
+}
+
+/**
+ * of_clk_get_by_name() - Parse and lookup a clock referenced by a device node
+ * @np: pointer to clock consumer node
+ * @name: name of consumer's clock input, or NULL for the first clock reference
+ *
+ * This function parses the clocks and clock-names properties,
+ * and uses them to look up the struct clk from the registered list of clock
+ * providers.
+ */
+struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
+{
+	struct clk *clk = NULL;
+
+	/* Walk up the tree of devices looking for a clock that matches */
+	while (np) {
+		int index = 0;
+
+		/*
+		 * For named clocks, first look up the name in the
+		 * "clock-names" property.  If it cannot be found, then
+		 * index will be an error code, and of_clk_get() will fail.
+		 */
+		if (name)
+			index = of_property_match_string(np, "clock-names", name);
+		clk = of_clk_get(np, index);
+		if (clk)
+			break;
+		else if (name && index >= 0) {
+			pr_err("ERROR: could not get clock %s:%s(%i)\n",
+				 np->full_name, name ? name : "", index);
+			return NULL;
+		}
+
+		/*
+		 * No matching clock found on this node.  If the parent node
+		 * has a "clock-ranges" property, then we can try one of its
+		 * clocks.
+		 */
+		np = np->parent;
+		if (np && !of_get_property(np, "clock-ranges", NULL))
+			break;
+	}
+
+	return clk;
+}
diff --git a/include/linux/of_clk.h b/include/linux/of_clk.h
new file mode 100644
index 0000000..dcbd27b
--- /dev/null
+++ b/include/linux/of_clk.h
@@ -0,0 +1,37 @@
+/*
+ * Clock infrastructure for device tree platforms
+ */
+#ifndef __OF_CLK_H
+#define __OF_CLK_H
+
+struct device;
+struct clk;
+
+#ifdef CONFIG_OF_CLOCK
+
+struct device_node;
+
+int of_clk_add_provider(struct device_node *np,
+			struct clk *(*clk_src_get)(struct of_phandle_args *args,
+						   void *data),
+			void *data);
+
+void of_clk_del_provider(struct device_node *np);
+
+struct clk *of_clk_get(struct device_node *np, int index);
+struct clk *of_clk_get_by_name(struct device_node *np, const char *name);
+
+#else
+static struct clk *of_clk_get(struct device_node *np, int index)
+{
+	return NULL;
+}
+
+static struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
+{
+	return NULL;
+}
+#endif
+
+#endif /* __OF_CLK_H */
+
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar 13 19:22:23 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 18:22:23 -0500
Subject: [PATCH 3/7] of: Add of_property_match_string() to find index into a
 string list
In-Reply-To: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331680947-29861-4-git-send-email-robherring2@gmail.com>

From: Grant Likely <grant.likely at secretlab.ca>

Add a helper function for finding the index of a string in a string
list property.  This helper is useful for bindings that use a separate
*-name property for attaching names to tuples in another property such
as 'reg' or 'gpios'.

Signed-off-by: Grant Likely <grant.likely at secretlab.ca>
---
 arch/arm/boot/dts/testcases/tests-phandle.dtsi |    2 +
 drivers/of/base.c                              |   36 ++++++++++++++++++++++++
 drivers/of/selftest.c                          |   29 +++++++++++++++++++
 include/linux/of.h                             |    3 ++
 4 files changed, 70 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/testcases/tests-phandle.dtsi b/arch/arm/boot/dts/testcases/tests-phandle.dtsi
index ec0c4e6..0007d3c 100644
--- a/arch/arm/boot/dts/testcases/tests-phandle.dtsi
+++ b/arch/arm/boot/dts/testcases/tests-phandle.dtsi
@@ -31,6 +31,8 @@
 				phandle-list-bad-phandle = <12345678 0 0>;
 				phandle-list-bad-args = <&provider2 1 0>,
 							<&provider3 0>;
+				empty-property;
+				unterminated-string = [40 41 42 43];
 			};
 		};
 	};
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 133908a..13ba728 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -761,6 +761,42 @@ int of_property_read_string_index(struct device_node *np, const char *propname,
 }
 EXPORT_SYMBOL_GPL(of_property_read_string_index);
 
+/**
+ * of_property_match_string() - Find string in a list and return index
+ * @np: pointer to node containing string list property
+ * @propname: string list property name
+ * @string: pointer to string to search for in string list
+ *
+ * This function searches a string list property and returns the index
+ * of a specific string value.
+ */
+int of_property_match_string(struct device_node *np, const char *propname,
+			     const char *string)
+{
+	struct property *prop = of_find_property(np, propname, NULL);
+	size_t l;
+	int i;
+	const char *p, *end;
+
+	if (!prop)
+		return -EINVAL;
+	if (!prop->value)
+		return -ENODATA;
+
+	p = prop->value;
+	end = p + prop->length;
+
+	for (i = 0; p < end; i++, p += l) {
+		l = strlen(p) + 1;
+		if (p + l > end)
+			return -EILSEQ;
+		pr_debug("comparing %s with %s\n", string, p);
+		if (strcmp(string, p) == 0)
+			return i; /* Found it; return index */
+	}
+	return -ENODATA;
+}
+EXPORT_SYMBOL_GPL(of_property_match_string);
 
 /**
  * of_property_count_strings - Find and return the number of strings from a
diff --git a/drivers/of/selftest.c b/drivers/of/selftest.c
index 9d2b480..f24ffd7 100644
--- a/drivers/of/selftest.c
+++ b/drivers/of/selftest.c
@@ -120,6 +120,34 @@ static void __init of_selftest_parse_phandle_with_args(void)
 	pr_info("end - %s\n", passed_all ? "PASS" : "FAIL");
 }
 
+static void __init of_selftest_property_match_string(void)
+{
+	struct device_node *np;
+	int rc;
+
+	pr_info("start\n");
+	np = of_find_node_by_path("/testcase-data/phandle-tests/consumer-a");
+	if (!np) {
+		pr_err("No testcase data in device tree\n");
+		return;
+	}
+
+	rc = of_property_match_string(np, "phandle-list-names", "first");
+	selftest(rc == 0, "first expected:0 got:%i\n", rc);
+	rc = of_property_match_string(np, "phandle-list-names", "second");
+	selftest(rc == 1, "second expected:0 got:%i\n", rc);
+	rc = of_property_match_string(np, "phandle-list-names", "third");
+	selftest(rc == 2, "third expected:0 got:%i\n", rc);
+	rc = of_property_match_string(np, "phandle-list-names", "fourth");
+	selftest(rc == -ENODATA, "unmatched string; rc=%i", rc);
+	rc = of_property_match_string(np, "missing-property", "blah");
+	selftest(rc == -EINVAL, "missing property; rc=%i", rc);
+	rc = of_property_match_string(np, "empty-property", "blah");
+	selftest(rc == -ENODATA, "empty property; rc=%i", rc);
+	rc = of_property_match_string(np, "unterminated-string", "blah");
+	selftest(rc == -EILSEQ, "unterminated string; rc=%i", rc);
+}
+
 static int __init of_selftest(void)
 {
 	struct device_node *np;
@@ -133,6 +161,7 @@ static int __init of_selftest(void)
 
 	pr_info("start of selftest - you will see error messages\n");
 	of_selftest_parse_phandle_with_args();
+	of_selftest_property_match_string();
 	pr_info("end of selftest - %s\n", selftest_passed ? "PASS" : "FAIL");
 	return 0;
 }
diff --git a/include/linux/of.h b/include/linux/of.h
index a75a831..5a4a3ad 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -217,6 +217,9 @@ extern int of_property_read_string(struct device_node *np,
 extern int of_property_read_string_index(struct device_node *np,
 					 const char *propname,
 					 int index, const char **output);
+extern int of_property_match_string(struct device_node *np,
+				    const char *propname,
+				    const char *string);
 extern int of_property_count_strings(struct device_node *np,
 				     const char *propname);
 extern int of_device_is_compatible(const struct device_node *device,
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar 13 19:22:24 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 18:22:24 -0500
Subject: [PATCH 4/7] dt/clock: Add handling for fixed clocks and a clock node
 setup iterator
In-Reply-To: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331680947-29861-5-git-send-email-robherring2@gmail.com>

From: Grant Likely <grant.likely at secretlab.ca>

Signed-off-by: Grant Likely <grant.likely at secretlab.ca>
[Rob Herring] Rework to use common clock infrastructure
Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 drivers/of/clock.c     |   45 ++++++++++++++++++++++++++++++++++++++++++++-
 include/linux/of_clk.h |    4 ++++
 2 files changed, 48 insertions(+), 1 deletions(-)

diff --git a/drivers/of/clock.c b/drivers/of/clock.c
index 6519e96..06fd5ad 100644
--- a/drivers/of/clock.c
+++ b/drivers/of/clock.c
@@ -2,7 +2,8 @@
  * Clock infrastructure for device tree platforms
  */
 
-#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
 #include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/module.h>
@@ -163,3 +164,45 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
 
 	return clk;
 }
+
+/**
+ * of_clk_init() - Scan and init clock providers from the DT
+ * @matches: array of compatible values and init functions for providers.
+ *
+ * This function scans the device tree for matching clock providers and
+ * calls their initialization functions
+ */
+void __init of_clk_init(const struct of_device_id *matches)
+{
+	struct device_node *np;
+
+	for_each_matching_node(np, matches) {
+		const struct of_device_id *match = of_match_node(matches, np);
+		of_clk_init_cb_t clk_init_cb = match->data;
+		clk_init_cb(np);
+	}
+}
+
+static struct clk *of_fixed_clk_get(struct of_phandle_args *a, void *data)
+{
+	return data;
+}
+
+/**
+ * of_fixed_clk_setup() - Setup function for simple fixed rate clock
+ */
+void __init of_fixed_clk_setup(struct device_node *node)
+{
+	struct clk *clk;
+	const char *clk_name = node->name;
+	u32 rate;
+
+	if (of_property_read_u32(node, "clock-frequency", &rate))
+		return;
+
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate);
+	if (clk)
+		of_clk_add_provider(node, of_fixed_clk_get, clk);
+}
diff --git a/include/linux/of_clk.h b/include/linux/of_clk.h
index dcbd27b..02ecc98 100644
--- a/include/linux/of_clk.h
+++ b/include/linux/of_clk.h
@@ -10,6 +10,7 @@ struct clk;
 #ifdef CONFIG_OF_CLOCK
 
 struct device_node;
+typedef void (*of_clk_init_cb_t)(struct device_node *);
 
 int of_clk_add_provider(struct device_node *np,
 			struct clk *(*clk_src_get)(struct of_phandle_args *args,
@@ -21,6 +22,9 @@ void of_clk_del_provider(struct device_node *np);
 struct clk *of_clk_get(struct device_node *np, int index);
 struct clk *of_clk_get_by_name(struct device_node *np, const char *name);
 
+void of_clk_init(const struct of_device_id *matches);
+extern void of_fixed_clk_setup(struct device_node *np);
+
 #else
 static struct clk *of_clk_get(struct device_node *np, int index)
 {
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar 13 19:22:25 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 18:22:25 -0500
Subject: [PATCH 5/7] dt/clock: add a simple provider get function
In-Reply-To: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331680947-29861-6-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

For simple cases, the clock provider data can simply be the struct clk ptr.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 drivers/of/clock.c |   18 +++++++++++-------
 1 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/of/clock.c b/drivers/of/clock.c
index 06fd5ad..f4a0965 100644
--- a/drivers/of/clock.c
+++ b/drivers/of/clock.c
@@ -33,6 +33,12 @@ struct of_clk_provider {
 static LIST_HEAD(of_clk_providers);
 static DEFINE_MUTEX(of_clk_lock);
 
+static struct clk *of_clk_simple_get(struct of_phandle_args *clkspec,
+				     void *data)
+{
+	return data;
+}
+
 /**
  * of_clk_add_provider() - Register a clock provider for a node
  * @np: Device node pointer associated with clock provider
@@ -52,7 +58,10 @@ int of_clk_add_provider(struct device_node *np,
 
 	cp->node = of_node_get(np);
 	cp->data = data;
-	cp->get = clk_src_get;
+	if (clk_src_get)
+		cp->get = clk_src_get;
+	else
+		cp->get = of_clk_simple_get;
 
 	mutex_lock(&of_clk_lock);
 	list_add(&cp->link, &of_clk_providers);
@@ -183,11 +192,6 @@ void __init of_clk_init(const struct of_device_id *matches)
 	}
 }
 
-static struct clk *of_fixed_clk_get(struct of_phandle_args *a, void *data)
-{
-	return data;
-}
-
 /**
  * of_fixed_clk_setup() - Setup function for simple fixed rate clock
  */
@@ -204,5 +208,5 @@ void __init of_fixed_clk_setup(struct device_node *node)
 
 	clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate);
 	if (clk)
-		of_clk_add_provider(node, of_fixed_clk_get, clk);
+		of_clk_add_provider(node, NULL, clk);
 }
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar 13 19:22:26 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 18:22:26 -0500
Subject: [PATCH 6/7] dt/clock: add function to get parent clock name
In-Reply-To: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331680947-29861-7-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 drivers/of/clock.c     |   24 ++++++++++++++++++++++++
 include/linux/of_clk.h |    2 ++
 2 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/drivers/of/clock.c b/drivers/of/clock.c
index f4a0965..8ad2dbd 100644
--- a/drivers/of/clock.c
+++ b/drivers/of/clock.c
@@ -128,6 +128,30 @@ struct clk *of_clk_get(struct device_node *np, int index)
 	return clk;
 }
 
+const char *of_clk_get_parent_name(struct device_node *np, int index)
+{
+	struct of_phandle_args clkspec;
+	const char *clk_name;
+	int rc;
+
+	if (index < 0)
+		return NULL;
+
+	rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
+					&clkspec);
+	if (rc)
+		return NULL;
+
+	if (of_property_read_string_index(clkspec.np, "clock-output-names",
+					  clkspec.args_count ? clkspec.args[0] : 0,
+					  &clk_name) < 0)
+		clk_name = clkspec.np->name;
+
+	of_node_put(clkspec.np);
+	return clk_name;
+}
+
+
 /**
  * of_clk_get_by_name() - Parse and lookup a clock referenced by a device node
  * @np: pointer to clock consumer node
diff --git a/include/linux/of_clk.h b/include/linux/of_clk.h
index 02ecc98..6a07071 100644
--- a/include/linux/of_clk.h
+++ b/include/linux/of_clk.h
@@ -22,6 +22,8 @@ void of_clk_del_provider(struct device_node *np);
 struct clk *of_clk_get(struct device_node *np, int index);
 struct clk *of_clk_get_by_name(struct device_node *np, const char *name);
 
+const char *of_clk_get_parent_name(struct device_node *np, int index);
+
 void of_clk_init(const struct of_device_id *matches);
 extern void of_fixed_clk_setup(struct device_node *np);
 
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar 13 19:22:27 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 18:22:27 -0500
Subject: [PATCH 7/7] clk: add highbank clock support
In-Reply-To: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
Message-ID: <1331680947-29861-8-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

This adds real clock support to Calxeda Highbank SOC using the common
clock infrastructure.

Signed-off-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/Kconfig                  |    1 +
 arch/arm/boot/dts/highbank.dts    |   76 +++++++++
 arch/arm/mach-highbank/Makefile   |    2 +-
 arch/arm/mach-highbank/clock.c    |   62 -------
 arch/arm/mach-highbank/highbank.c |   16 ++
 drivers/clk/Makefile              |    2 +
 drivers/clk/clk-highbank.c        |  335 +++++++++++++++++++++++++++++++++++++
 7 files changed, 431 insertions(+), 63 deletions(-)
 delete mode 100644 arch/arm/mach-highbank/clock.c
 create mode 100644 drivers/clk/clk-highbank.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a48aecc..2019548 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -346,6 +346,7 @@ config ARCH_HIGHBANK
 	select ARM_TIMER_SP804
 	select CACHE_L2X0
 	select CLKDEV_LOOKUP
+	select COMMON_CLK
 	select CPU_V7
 	select GENERIC_CLOCKEVENTS
 	select HAVE_ARM_SCU
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 305635b..06194d5 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -24,6 +24,7 @@
 	compatible = "calxeda,highbank";
 	#address-cells = <1>;
 	#size-cells = <1>;
+	clock-ranges;
 
 	cpus {
 		#address-cells = <1>;
@@ -75,12 +76,14 @@
 			compatible = "arm,smp-twd";
 			reg = <0xfff10600 0x20>;
 			interrupts = <1 13 0xf04>;
+			clocks = <&a9periphclk>;
 		};
 
 		watchdog at fff10620 {
 			compatible = "arm,cortex-a9-wdt";
 			reg = <0xfff10620 0x20>;
 			interrupts = <1 14 0xf04>;
+			clocks = <&a9periphclk>;
 		};
 
 		intc: interrupt-controller at fff11000 {
@@ -117,12 +120,14 @@
 			compatible = "calxeda,hb-sdhci";
 			reg = <0xffe0e000 0x1000>;
 			interrupts = <0 90 4>;
+			clocks = <&eclk>;
 		};
 
 		ipc at fff20000 {
 			compatible = "arm,pl320", "arm,primecell";
 			reg = <0xfff20000 0x1000>;
 			interrupts = <0 7 4>;
+			clocks = <&pclk>;
 		};
 
 		gpioe: gpio at fff30000 {
@@ -131,6 +136,7 @@
 			gpio-controller;
 			reg = <0xfff30000 0x1000>;
 			interrupts = <0 14 4>;
+			clocks = <&pclk>;
 		};
 
 		gpiof: gpio at fff31000 {
@@ -139,6 +145,7 @@
 			gpio-controller;
 			reg = <0xfff31000 0x1000>;
 			interrupts = <0 15 4>;
+			clocks = <&pclk>;
 		};
 
 		gpiog: gpio at fff32000 {
@@ -147,6 +154,7 @@
 			gpio-controller;
 			reg = <0xfff32000 0x1000>;
 			interrupts = <0 16 4>;
+			clocks = <&pclk>;
 		};
 
 		gpioh: gpio at fff33000 {
@@ -155,24 +163,30 @@
 			gpio-controller;
 			reg = <0xfff33000 0x1000>;
 			interrupts = <0 17 4>;
+			clocks = <&pclk>;
 		};
 
 		timer {
 			compatible = "arm,sp804", "arm,primecell";
 			reg = <0xfff34000 0x1000>;
 			interrupts = <0 18 4>;
+			clocks = <&pclk>, <&pclk>;
+			clock-names = "apb_pclk", "bus";
 		};
 
 		rtc at fff35000 {
 			compatible = "arm,pl031", "arm,primecell";
 			reg = <0xfff35000 0x1000>;
 			interrupts = <0 19 4>;
+			clocks = <&pclk>;
 		};
 
 		serial at fff36000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0xfff36000 0x1000>;
 			interrupts = <0 20 4>;
+			clocks = <&pclk>, <&pclk>;
+			clock-names = "apb_pclk", "bus";
 		};
 
 		smic at fff3a000 {
@@ -187,12 +201,74 @@
 		sregs at fff3c000 {
 			compatible = "calxeda,hb-sregs";
 			reg = <0xfff3c000 0x1000>;
+
+			clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				osc: oscillator {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+					clock-frequency = <33333000>;
+				};
+
+				ddrpll: ddrpll {
+					#clock-cells = <0>;
+					compatible = "calxeda,hb-pll-clock";
+					clocks = <&osc>;
+					reg = <0x108>;
+				};
+
+				a9pll: a9pll {
+					#clock-cells = <0>;
+					compatible = "calxeda,hb-pll-clock";
+					clocks = <&osc>;
+					reg = <0x100>;
+				};
+
+				a9periphclk: a9periphclk {
+					#clock-cells = <0>;
+					compatible = "calxeda,hb-a9periph-clock";
+					clocks = <&a9pll>;
+					reg = <0x104>;
+					clock-divider = <4>;
+				};
+
+				a9bclk: a9bclk {
+					#clock-cells = <0>;
+					compatible = "calxeda,hb-a9bus-clock";
+					clocks = <&a9pll>;
+					reg = <0x104>;
+					clock-divider = <4>;
+				};
+
+				emmcpll: emmcpll {
+					#clock-cells = <0>;
+					compatible = "calxeda,hb-pll-clock";
+					clocks = <&osc>;
+					reg = <0x10C>;
+				};
+
+				eclk: eclk {
+					#clock-cells = <0>;
+					compatible = "calxeda,hb-emmc-clock";
+					clocks = <&emmcpll>;
+					reg = <0x114>;
+				};
+
+				pclk: pclk {
+					#clock-cells = <0>;
+					compatible = "fixed-clock";
+					clock-frequency = <150000000>;
+				};
+			};
 		};
 
 		dma at fff3d000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0xfff3d000 0x1000>;
 			interrupts = <0 92 4>;
+			clocks = <&pclk>;
 		};
 
 		ethernet at fff50000 {
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
index 986958a..8bf3868 100644
--- a/arch/arm/mach-highbank/Makefile
+++ b/arch/arm/mach-highbank/Makefile
@@ -1,4 +1,4 @@
-obj-y					:= clock.o highbank.o system.o
+obj-y					:= highbank.o system.o
 obj-$(CONFIG_DEBUG_HIGHBANK_UART)	+= lluart.o
 obj-$(CONFIG_SMP)			+= platsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)		+= localtimer.o
diff --git a/arch/arm/mach-highbank/clock.c b/arch/arm/mach-highbank/clock.c
deleted file mode 100644
index c25a2ae..0000000
--- a/arch/arm/mach-highbank/clock.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2011 Calxeda, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-
-struct clk {
-	unsigned long rate;
-};
-
-int clk_enable(struct clk *clk)
-{
-	return 0;
-}
-
-void clk_disable(struct clk *clk)
-{}
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	return clk->rate;
-}
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-	return clk->rate;
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	return 0;
-}
-
-static struct clk eclk = { .rate = 200000000 };
-static struct clk pclk = { .rate = 150000000 };
-
-static struct clk_lookup lookups[] = {
-	{ .clk = &pclk, .con_id = "apb_pclk", },
-	{ .clk = &pclk, .dev_id = "sp804", },
-	{ .clk = &eclk, .dev_id = "ffe0e000.sdhci", },
-	{ .clk = &pclk, .dev_id = "fff36000.serial", },
-};
-
-void __init highbank_clocks_init(void)
-{
-	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 8394d51..5c0cdaa 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -23,6 +23,7 @@
 #include <linux/of_platform.h>
 #include <linux/of_address.h>
 #include <linux/smp.h>
+#include <linux/of_clk.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -91,6 +92,16 @@ static void __init highbank_init_irq(void)
 	l2x0_of_init(0, ~0UL);
 }
 
+static struct clk_lookup lookups[] = {
+	{
+		.dev_id = "sp804",
+		.con_id = NULL,
+	}, {
+		.dev_id = "smp_twd",
+		.con_id = NULL,
+	}
+};
+
 static void __init highbank_timer_init(void)
 {
 	int irq;
@@ -108,6 +119,11 @@ static void __init highbank_timer_init(void)
 	irq = irq_of_parse_and_map(np, 0);
 
 	highbank_clocks_init();
+	lookups[0].clk = of_clk_get(np, 0);
+
+	np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
+	lookups[1].clk = of_clk_get(np, 0);
+	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
 	sp804_clocksource_init(timer_base + 0x20, "timer1");
 	sp804_clockevents_init(timer_base, irq, "timer0");
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1f736bc..70c713f 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -2,3 +2,5 @@
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
 				   clk-mux.o clk-divider.o
+
+obj-$(CONFIG_ARCH_HIGHBANK)	+= clk-highbank.o
diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
new file mode 100644
index 0000000..722fc67
--- /dev/null
+++ b/drivers/clk/clk-highbank.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_clk.h>
+
+extern void __iomem *sregs_base;
+
+#define HB_PLL_LOCK_500		0x20000000
+#define HB_PLL_LOCK		0x10000000
+#define HB_PLL_DIVF_SHIFT	20
+#define HB_PLL_DIVF_MASK	0x0ff00000
+#define HB_PLL_DIVQ_SHIFT	16
+#define HB_PLL_DIVQ_MASK	0x00070000
+#define HB_PLL_DIVR_SHIFT	8
+#define HB_PLL_DIVR_MASK	0x00001f00
+#define HB_PLL_RANGE_SHIFT	4
+#define HB_PLL_RANGE_MASK	0x00000070
+#define HB_PLL_BYPASS		0x00000008
+#define HB_PLL_RESET		0x00000004
+#define HB_PLL_EXT_BYPASS	0x00000002
+#define HB_PLL_EXT_ENA		0x00000001
+
+#define HB_PLL_VCO_MIN_FREQ	2133000000
+#define HB_PLL_MAX_FREQ		HB_PLL_VCO_MIN_FREQ
+#define HB_PLL_MIN_FREQ		(HB_PLL_VCO_MIN_FREQ / 64)
+
+#define HB_A9_BCLK_DIV_MASK	0x00000006
+#define HB_A9_BCLK_DIV_SHIFT	1
+
+struct hb_clk {
+        struct clk_hw	hw;
+	void __iomem	*reg;
+	char *parent_name;
+};
+#define to_hb_clk(p) container_of(p, struct hb_clk, hw)
+
+static int clk_pll_prepare(struct clk_hw *clk)
+	{
+	struct hb_clk *hbclk = to_hb_clk(clk);
+	u32 reg;
+
+	reg = readl(hbclk->reg);
+	reg &= ~HB_PLL_RESET;
+	writel(reg, hbclk->reg);
+
+	while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
+		;
+	while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
+		;
+
+	return 0;
+}
+
+static void clk_pll_unprepare(struct clk_hw *clk)
+{
+	struct hb_clk *hbclk = to_hb_clk(clk);
+	u32 reg;
+
+	reg = readl(hbclk->reg);
+	reg |= HB_PLL_RESET;
+	writel(reg, hbclk->reg);
+}
+
+static int clk_pll_enable(struct clk_hw *clk)
+{
+	struct hb_clk *hbclk = to_hb_clk(clk);
+	u32 reg;
+
+	reg = readl(hbclk->reg);
+	reg |= HB_PLL_EXT_ENA;
+	writel(reg, hbclk->reg);
+
+	return 0;
+}
+
+static void clk_pll_disable(struct clk_hw *clk)
+{
+	struct hb_clk *hbclk = to_hb_clk(clk);
+	u32 reg;
+
+	reg = readl(hbclk->reg);
+	reg &= ~HB_PLL_EXT_ENA;
+	writel(reg, hbclk->reg);
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *clk,
+					 unsigned long parent_rate)
+{
+	struct hb_clk *hbclk = to_hb_clk(clk);
+	unsigned long divf, divq, vco_freq, reg;
+
+	reg = readl(hbclk->reg);
+	if (reg & HB_PLL_EXT_BYPASS)
+		return parent_rate;
+
+	divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
+	divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
+	vco_freq = parent_rate * (divf + 1);
+
+	return vco_freq / (1 << divq);
+}
+
+static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
+			u32 *pdivq, u32 *pdivf)
+{
+	u32 divq, divf;
+	unsigned long vco_freq;
+
+	if (rate < HB_PLL_MIN_FREQ)
+		rate = HB_PLL_MIN_FREQ;
+	if (rate > HB_PLL_MAX_FREQ)
+		rate = HB_PLL_MAX_FREQ;
+
+	for (divq = 1; divq <= 6; divq++) {
+		if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
+			break;
+	}
+
+	vco_freq = rate * (1 << divq);
+	divf = (vco_freq + (ref_freq / 2)) / ref_freq;
+	divf--;
+
+	*pdivq = divq;
+	*pdivf = divf;
+}
+
+static long clk_pll_round_rate(struct clk_hw *clk, unsigned long rate,
+			       unsigned long *unused)
+{
+	u32 divq, divf;
+	unsigned long ref_freq = clk_get_rate(clk_get_parent(clk->clk));
+
+	clk_pll_calc(rate, ref_freq, &divq, &divf);
+
+	return (ref_freq * (divf + 1)) / (1 << divq);
+}
+
+static int clk_pll_set_rate(struct clk_hw *clk, unsigned long rate)
+{
+	struct hb_clk *hbclk = to_hb_clk(clk);
+	unsigned long parent_rate;
+	u32 divq, divf;
+	u32 reg;
+
+	parent_rate = clk_get_rate(clk_get_parent(clk->clk));
+	clk_pll_calc(rate, parent_rate, &divq, &divf);
+
+	reg = readl(hbclk->reg);
+	if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
+		/* Need to re-lock PLL, so put it into bypass mode */
+		reg |= HB_PLL_EXT_BYPASS;
+		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
+
+		reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
+		reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
+		writel(reg | HB_PLL_RESET, hbclk->reg);
+		writel(reg, hbclk->reg);
+
+		while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
+			;
+		while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
+			;
+		reg |= HB_PLL_EXT_ENA;
+		reg &= ~HB_PLL_EXT_BYPASS;
+	} else {
+		reg &= ~HB_PLL_DIVQ_MASK;
+		reg |= divq << HB_PLL_DIVQ_SHIFT;
+	}
+	writel(reg, hbclk->reg);
+
+	return 0;
+}
+
+static const struct clk_ops clk_pll_ops = {
+	.prepare = clk_pll_prepare,
+	.unprepare = clk_pll_unprepare,
+	.enable = clk_pll_enable,
+	.disable = clk_pll_disable,
+	.recalc_rate = clk_pll_recalc_rate,
+	.round_rate = clk_pll_round_rate,
+	.set_rate = clk_pll_set_rate,
+};
+
+static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *clk,
+						   unsigned long parent_rate)
+{
+	return parent_rate / 2;
+}
+
+static const struct clk_ops a9periphclk_ops = {
+	.recalc_rate = clk_cpu_periphclk_recalc_rate,
+};
+
+static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *clk,
+						unsigned long parent_rate)
+{
+	struct hb_clk *hbclk = to_hb_clk(clk);
+	u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
+
+	return parent_rate / (div + 2);
+}
+
+static const struct clk_ops a9bclk_ops = {
+	.recalc_rate = clk_cpu_a9bclk_recalc_rate,
+};
+
+static unsigned long clk_periclk_recalc_rate(struct clk_hw *clk,
+					     unsigned long parent_rate)
+{
+	struct hb_clk *hbclk = to_hb_clk(clk);
+	u32 div;
+
+	div = readl(hbclk->reg);
+	div++;
+	div *= 2;
+
+	return parent_rate / div;
+}
+
+static long clk_periclk_round_rate(struct clk_hw *clk, unsigned long rate,
+				   unsigned long *unused)
+{
+	unsigned long parent_rate = clk_get_rate(clk_get_parent(clk->clk));
+	u32 div;
+
+	div = parent_rate / rate;
+	div++;
+	div &= ~0x1;
+
+	return parent_rate / div;
+}
+
+static int clk_periclk_set_rate(struct clk_hw *clk, unsigned long rate)
+{
+	struct hb_clk *hbclk = to_hb_clk(clk);
+	u32 div;
+
+	div = clk_get_rate(clk_get_parent(clk->clk)) / rate;
+	if (div & 0x1)
+		return -EINVAL;
+
+	writel(div >> 1, hbclk->reg);
+	return 0;
+}
+
+static const struct clk_ops periclk_ops = {
+	.recalc_rate = clk_periclk_recalc_rate,
+	.round_rate = clk_periclk_round_rate,
+	.set_rate = clk_periclk_set_rate,
+};
+
+static void __init hb_clk_init(struct device_node *node, const struct clk_ops *ops)
+{
+	u32 reg;
+	struct clk *clk;
+	struct hb_clk *hb_clk;
+	const char *clk_name = node->name;
+	int rc;
+
+	rc = of_property_read_u32(node, "reg", &reg);
+	if (WARN_ON(rc))
+		return;
+
+	hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
+	if (WARN_ON(!hb_clk))
+		return;
+
+	hb_clk->reg = sregs_base + reg;
+
+	of_property_read_string(node, "clock-outputs", &clk_name);
+
+	hb_clk->parent_name = of_clk_get_parent_name(node, 0);
+
+	printk("registering clk %s, parent = %s\n", clk_name, hb_clk->parent_name);
+	clk = clk_register(NULL, clk_name, ops, &hb_clk->hw,
+			   &hb_clk->parent_name, 1, 0);
+	if (WARN_ON(!clk)) {
+		kfree(hb_clk);
+		return;
+	}
+	rc = of_clk_add_provider(node, NULL, clk);
+}
+
+static void __init hb_pll_init(struct device_node *node)
+{
+	hb_clk_init(node, &clk_pll_ops);
+}
+
+static void __init hb_a9periph_init(struct device_node *node)
+{
+	hb_clk_init(node, &a9periphclk_ops);
+}
+
+static void __init hb_a9bus_init(struct device_node *node)
+{
+	hb_clk_init(node, &a9bclk_ops);
+}
+
+static void __init hb_emmc_init(struct device_node *node)
+{
+	hb_clk_init(node, &periclk_ops);
+}
+
+static const __initconst struct of_device_id clk_match[] = {
+	{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
+	{ .compatible = "calxeda,hb-pll-clock", .data = hb_pll_init, },
+	{ .compatible = "calxeda,hb-a9periph-clock", .data = hb_a9periph_init, },
+	{ .compatible = "calxeda,hb-a9bus-clock", .data = hb_a9bus_init, },
+	{ .compatible = "calxeda,hb-emmc-clock", .data = hb_emmc_init, },
+	{}
+};
+
+void __init highbank_clocks_init(void)
+{
+	of_clk_init(clk_match);
+}
-- 
1.7.5.4



From timur at freescale.com  Tue Mar 13 19:23:50 2012
From: timur at freescale.com (Timur Tabi)
Date: Tue, 13 Mar 2012 18:23:50 -0500
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120309013216.GH2499@S2101-09.ap.freescale.net>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
Message-ID: <4F5FD706.8040209@freescale.com>

Shawn Guo wrote:
> Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt, which
> takes Documentation/devicetree/bindings/sound/tegra-audio-wm8903.txt
> as the example.

sound {
	compatible = "fsl,imx51-babbage-sgtl5000",
		     "fsl,imx-audio-sgtl5000";
	model = "imx51-babbage-sgtl5000";
	ssi-controller = <&ssi1>;
	audio-codec = <&sgtl5000>;
	mux-int-port = <1>;
	mux-ext-port = <3>;
};

How does this handle multiple SSIs, each connected to its own codec?

And where's the binding for the DMA controller?

I honestly don't see how this is an improvement over what I came up with.

-- 
Timur Tabi
Linux kernel developer at Freescale



From mturquette at ti.com  Tue Mar 13 19:43:57 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 13 Mar 2012 16:43:57 -0700
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120313112447.GA29317@pengutronix.de>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120313112447.GA29317@pengutronix.de>
Message-ID: <CAJOA=zMTY+4dU9VUa-TkEbdE-WJd7V4tCG-af6vgq0CPN6rWpg@mail.gmail.com>

On Tue, Mar 13, 2012 at 4:24 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Sat, Mar 03, 2012 at 12:29:00AM -0800, Mike Turquette wrote:
>> The common clock framework defines a common struct clk useful across
>> most platforms as well as an implementation of the clk api that drivers
>> can use safely for managing clocks.
>>
>> The net result is consolidation of many different struct clk definitions
>> and platform-specific clock framework implementations.
>>
>> This patch introduces the common struct clk, struct clk_ops and an
>> implementation of the well-known clock api in include/clk/clk.h.
>> Platforms may define their own hardware-specific clock structure and
>> their own clock operation callbacks, so long as it wraps an instance of
>> struct clk_hw.
>>
>> See Documentation/clk.txt for more details.
>>
>> This patch is based on the work of Jeremy Kerr, which in turn was based
>> on the work of Ben Herrenschmidt.
>>
>> Signed-off-by: Mike Turquette <mturquette at linaro.org>
>> Signed-off-by: Mike Turquette <mturquette at ti.com>
>> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
>> Cc: Thomas Gleixner <tglx at linutronix.de>
>> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
>> Cc: Paul Walmsley <paul at pwsan.com>
>> Cc: Shawn Guo <shawn.guo at freescale.com>
>> Cc: Richard Zhao <richard.zhao at linaro.org>
>> Cc: Saravana Kannan <skannan at codeaurora.org>
>> Cc: Magnus Damm <magnus.damm at gmail.com>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
>> Cc: Linus Walleij <linus.walleij at stericsson.com>
>> Cc: Stephen Boyd <sboyd at codeaurora.org>
>> Cc: Amit Kucheria <amit.kucheria at linaro.org>
>> Cc: Deepak Saxena <dsaxena at linaro.org>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Cc: Andrew Lunn <andrew at lunn.ch>
>> ---
>> ?drivers/clk/Kconfig ? ? ? ? ?| ? 28 +
>> ?drivers/clk/Makefile ? ? ? ? | ? ?1 +
>> ?drivers/clk/clk.c ? ? ? ? ? ?| 1323 ++++++++++++++++++++++++++++++++++++++++++
>> ?include/linux/clk-private.h ?| ? 68 +++
>> ?include/linux/clk-provider.h | ?169 ++++++
>> ?include/linux/clk.h ? ? ? ? ?| ? 68 ++-
>> ?6 files changed, 1652 insertions(+), 5 deletions(-)
>> ?create mode 100644 drivers/clk/clk.c
>> ?create mode 100644 include/linux/clk-private.h
>> ?create mode 100644 include/linux/clk-provider.h
>>
>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>> index 3912576..18eb8c2 100644
>> --- a/drivers/clk/Kconfig
>> +++ b/drivers/clk/Kconfig
>> @@ -11,3 +11,31 @@ config HAVE_MACH_CLKDEV
>>
>> ?config HAVE_CLK_PREPARE
>> ? ? ? bool
>> +
>> +menuconfig COMMON_CLK
>> + ? ? bool "Common Clock Framework"
>> + ? ? select HAVE_CLK_PREPARE
>> + ? ? ---help---
>> + ? ? ? The common clock framework is a single definition of struct
>> + ? ? ? clk, useful across many platforms, as well as an
>> + ? ? ? implementation of the clock API in include/linux/clk.h.
>> + ? ? ? Architectures utilizing the common struct clk should select
>> + ? ? ? this automatically, but it may be necessary to manually select
>> + ? ? ? this option for loadable modules requiring the common clock
>> + ? ? ? framework.
>> +
>> + ? ? ? If in doubt, say "N".
>> +
>> +if COMMON_CLK
>> +
>> +config COMMON_CLK_DEBUG
>> + ? ? bool "DebugFS representation of clock tree"
>> + ? ? depends on COMMON_CLK
>> + ? ? ---help---
>> + ? ? ? Creates a directory hierchy in debugfs for visualizing the clk
>> + ? ? ? tree structure. ?Each directory contains read-only members
>> + ? ? ? that export information specific to that clk node: clk_rate,
>> + ? ? ? clk_flags, clk_prepare_count, clk_enable_count &
>> + ? ? ? clk_notifier_count.
>> +
>> +endif
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 07613fa..ff362c4 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -1,2 +1,3 @@
>>
>> ?obj-$(CONFIG_CLKDEV_LOOKUP) ?+= clkdev.o
>> +obj-$(CONFIG_COMMON_CLK) ? ? += clk.o
>> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
>> new file mode 100644
>> index 0000000..b979d74
>> --- /dev/null
>> +++ b/drivers/clk/clk.c
>> @@ -0,0 +1,1323 @@
>> +/*
>> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
>> + * Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Standard functionality for the common clock API. ?See Documentation/clk.txt
>> + */
>> +
>> +#include <linux/clk-private.h>
>> +#include <linux/module.h>
>> +#include <linux/mutex.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/err.h>
>> +#include <linux/list.h>
>> +#include <linux/slab.h>
>> +
>> +static DEFINE_SPINLOCK(enable_lock);
>> +static DEFINE_MUTEX(prepare_lock);
>> +
>> +static HLIST_HEAD(clk_root_list);
>> +static HLIST_HEAD(clk_orphan_list);
>> +static LIST_HEAD(clk_notifier_list);
>> +
>> +/*** ? ? ? ?debugfs support ? ? ? ?***/
>> +
>> +#ifdef CONFIG_COMMON_CLK_DEBUG
>> +#include <linux/debugfs.h>
>> +
>> +static struct dentry *rootdir;
>> +static struct dentry *orphandir;
>> +static int inited = 0;
>> +
>> +/* caller must hold prepare_lock */
>> +static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
>> +{
>> + ? ? struct dentry *d;
>> + ? ? int ret = -ENOMEM;
>> +
>> + ? ? if (!clk || !pdentry) {
>> + ? ? ? ? ? ? ret = -EINVAL;
>> + ? ? ? ? ? ? goto out;
>> + ? ? }
>> +
>> + ? ? d = debugfs_create_dir(clk->name, pdentry);
>> + ? ? if (!d)
>> + ? ? ? ? ? ? goto out;
>> +
>> + ? ? clk->dentry = d;
>> +
>> + ? ? d = debugfs_create_u32("clk_rate", S_IRUGO, clk->dentry,
>> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->rate);
>> + ? ? if (!d)
>> + ? ? ? ? ? ? goto err_out;
>> +
>> + ? ? d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
>> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->flags);
>> + ? ? if (!d)
>> + ? ? ? ? ? ? goto err_out;
>> +
>> + ? ? d = debugfs_create_u32("clk_prepare_count", S_IRUGO, clk->dentry,
>> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->prepare_count);
>> + ? ? if (!d)
>> + ? ? ? ? ? ? goto err_out;
>> +
>> + ? ? d = debugfs_create_u32("clk_enable_count", S_IRUGO, clk->dentry,
>> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->enable_count);
>> + ? ? if (!d)
>> + ? ? ? ? ? ? goto err_out;
>> +
>> + ? ? d = debugfs_create_u32("clk_notifier_count", S_IRUGO, clk->dentry,
>> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->notifier_count);
>> + ? ? if (!d)
>> + ? ? ? ? ? ? goto err_out;
>> +
>> + ? ? ret = 0;
>> + ? ? goto out;
>> +
>> +err_out:
>> + ? ? debugfs_remove(clk->dentry);
>> +out:
>> + ? ? return ret;
>> +}
>> +
>> +/* caller must hold prepare_lock */
>> +static int clk_debug_create_subtree(struct clk *clk, struct dentry *pdentry)
>> +{
>> + ? ? struct clk *child;
>> + ? ? struct hlist_node *tmp;
>> + ? ? int ret = -EINVAL;;
>> +
>> + ? ? if (!clk || !pdentry)
>> + ? ? ? ? ? ? goto out;
>> +
>> + ? ? ret = clk_debug_create_one(clk, pdentry);
>> +
>> + ? ? if (ret)
>> + ? ? ? ? ? ? goto out;
>> +
>> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node)
>> + ? ? ? ? ? ? clk_debug_create_subtree(child, clk->dentry);
>> +
>> + ? ? ret = 0;
>> +out:
>> + ? ? return ret;
>> +}
>> +
>> +/**
>> + * clk_debug_register - add a clk node to the debugfs clk tree
>> + * @clk: the clk being added to the debugfs clk tree
>> + *
>> + * Dynamically adds a clk to the debugfs clk tree if debugfs has been
>> + * initialized. ?Otherwise it bails out early since the debugfs clk tree
>> + * will be created lazily by clk_debug_init as part of a late_initcall.
>> + *
>> + * Caller must hold prepare_lock. ?Only clk_init calls this function (so
>> + * far) so this is taken care.
>> + */
>> +static int clk_debug_register(struct clk *clk)
>> +{
>> + ? ? struct clk *parent;
>> + ? ? struct dentry *pdentry;
>> + ? ? int ret = 0;
>> +
>> + ? ? if (!inited)
>> + ? ? ? ? ? ? goto out;
>> +
>> + ? ? parent = clk->parent;
>> +
>> + ? ? /*
>> + ? ? ?* Check to see if a clk is a root clk. ?Also check that it is
>> + ? ? ?* safe to add this clk to debugfs
>> + ? ? ?*/
>> + ? ? if (!parent)
>> + ? ? ? ? ? ? if (clk->flags & CLK_IS_ROOT)
>> + ? ? ? ? ? ? ? ? ? ? pdentry = rootdir;
>> + ? ? ? ? ? ? else
>> + ? ? ? ? ? ? ? ? ? ? pdentry = orphandir;
>> + ? ? else
>> + ? ? ? ? ? ? if (parent->dentry)
>> + ? ? ? ? ? ? ? ? ? ? pdentry = parent->dentry;
>> + ? ? ? ? ? ? else
>> + ? ? ? ? ? ? ? ? ? ? goto out;
>> +
>> + ? ? ret = clk_debug_create_subtree(clk, pdentry);
>> +
>> +out:
>> + ? ? return ret;
>> +}
>> +
>> +/**
>> + * clk_debug_init - lazily create the debugfs clk tree visualization
>> + *
>> + * clks are often initialized very early during boot before memory can
>> + * be dynamically allocated and well before debugfs is setup.
>> + * clk_debug_init walks the clk tree hierarchy while holding
>> + * prepare_lock and creates the topology as part of a late_initcall,
>> + * thus insuring that clks initialized very early will still be
>> + * represented in the debugfs clk tree. ?This function should only be
>> + * called once at boot-time, and all other clks added dynamically will
>> + * be done so with clk_debug_register.
>> + */
>> +static int __init clk_debug_init(void)
>> +{
>> + ? ? struct clk *clk;
>> + ? ? struct hlist_node *tmp;
>> +
>> + ? ? rootdir = debugfs_create_dir("clk", NULL);
>> +
>> + ? ? if (!rootdir)
>> + ? ? ? ? ? ? return -ENOMEM;
>> +
>> + ? ? orphandir = debugfs_create_dir("orphans", rootdir);
>> +
>> + ? ? if (!orphandir)
>> + ? ? ? ? ? ? return -ENOMEM;
>> +
>> + ? ? mutex_lock(&prepare_lock);
>> +
>> + ? ? hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
>> + ? ? ? ? ? ? clk_debug_create_subtree(clk, rootdir);
>> +
>> + ? ? hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
>> + ? ? ? ? ? ? clk_debug_create_subtree(clk, orphandir);
>> +
>> + ? ? inited = 1;
>> +
>> + ? ? mutex_unlock(&prepare_lock);
>> +
>> + ? ? return 0;
>> +}
>> +late_initcall(clk_debug_init);
>> +#else
>> +static inline int clk_debug_register(struct clk *clk) { return 0; }
>> +#endif /* CONFIG_COMMON_CLK_DEBUG */
>> +
>> +/*** ? ?helper functions ? ***/
>> +
>> +inline const char *__clk_get_name(struct clk *clk)
>> +{
>> + ? ? return !clk ? NULL : clk->name;
>> +}
>> +
>> +inline struct clk_hw *__clk_get_hw(struct clk *clk)
>> +{
>> + ? ? return !clk ? NULL : clk->hw;
>> +}
>> +
>> +inline u8 __clk_get_num_parents(struct clk *clk)
>> +{
>> + ? ? return !clk ? -EINVAL : clk->num_parents;
>> +}
>> +
>> +inline struct clk *__clk_get_parent(struct clk *clk)
>> +{
>> + ? ? return !clk ? NULL : clk->parent;
>> +}
>> +
>> +inline unsigned long __clk_get_rate(struct clk *clk)
>> +{
>> + ? ? return !clk ? -EINVAL : clk->rate;
>> +}
>> +
>> +inline unsigned long __clk_get_flags(struct clk *clk)
>> +{
>> + ? ? return !clk ? -EINVAL : clk->flags;
>> +}
>> +
>> +static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
>> +{
>> + ? ? struct clk *child;
>> + ? ? struct clk *ret;
>> + ? ? struct hlist_node *tmp;
>> +
>> + ? ? if (!strcmp(clk->name, name))
>> + ? ? ? ? ? ? return clk;
>> +
>> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node) {
>> + ? ? ? ? ? ? ret = __clk_lookup_subtree(name, child);
>> + ? ? ? ? ? ? if (ret)
>> + ? ? ? ? ? ? ? ? ? ? return ret;
>> + ? ? }
>> +
>> + ? ? return NULL;
>> +}
>> +
>> +struct clk *__clk_lookup(const char *name)
>> +{
>> + ? ? struct clk *root_clk;
>> + ? ? struct clk *ret;
>> + ? ? struct hlist_node *tmp;
>> +
>
> This should have a check for NULL pointers. NULL pointers can happen
> here if a mux has holes in it. In this case the parent name array would
> look like this:
>
> { "parentclk1", "parentclk2", NULL /* reserved */, "parentclk3" }
>
> Without checking for NULL pointers we dereference the NULL pointer here.

I will add the check.  I had not considered having NULL as one of the
parent names.  It seems to me that the only time this would happen is
if we are wiring up discrete devices.  For instance:

Device A has a fixed-rate clock named "dpll"
Device B has a mux clock named "leaf" with parent_names = { "32k",
"oscillator", "clkin" }

On a given board, leaf's "pll" parent might map to the output of the
dpll clock.  I had considered that DT would step in here by creating
an intermediate clock with no functional clk_ops that would "connect"
these two clocks.  The benefit of this is that it is easier to match
up clock names when staring at some data sheets.  It is common for a
downstream device's data sheets to assign names to the external inputs
originating from some unknown device; unsurprisingly the data sheet
for the device supplying the external upstream clocks often has
different names for the output signals than the one in the downstream
device's data sheet.  Using the method described above it is easy for
a person with both data sheets to see how the devices are wired up
since all of the clock names are represented by nodes in the clock
tree.  In short, the final outcome would looking something like:

dpll (device a's driver registered this clock)
  |
clkin (one of device b's possible parents)
  |    (it is a dummy clock from DT since it is board-level topology)
  |
leaf (device b's driver registered this clock)

clkin would have a single parent named "dpll" in this case, and again,
it would have no meaningful clk_ops.

A caveat to the above scenario is that parent_names shouldn't have
holes in it, but a null pointer check is reasonable anyways.

What do you think?  Even if we allow for muxes to have holes in
parent_names we'll still have to solve these sort of device
integration issues and DT will likely play a roll here.  I'll roll in
the null pointer check regardless.

Also, do you forsee needing hole in parent_names for any reason other
than described above?

Thanks,
Mike

>
>> +
>> +/**
>> + * __clk_round_rate - round the given rate for a clk
>> + * @clk: round the rate of this clock
>> + *
>> + * Caller must hold prepare_lock. ?Useful for clk_ops such as .set_rate
>> + */
>> +unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
>> +{
>> + ? ? if (!clk && !clk->ops->round_rate)
>> + ? ? ? ? ? ? return -EINVAL;
>
> This should return the parents rate if the clock itself does not
> have a round_rate function. Also, must be || instead of &&
>
>> +
>> + ? ? return clk->ops->round_rate(clk->hw, rate, NULL);
>> +}
>> +
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |


From broonie at opensource.wolfsonmicro.com  Tue Mar 13 19:46:39 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 13 Mar 2012 23:46:39 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F5FD706.8040209@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
Message-ID: <20120313234638.GY3177@opensource.wolfsonmicro.com>

On Tue, Mar 13, 2012 at 06:23:50PM -0500, Timur Tabi wrote:

> sound {
> 	compatible = "fsl,imx51-babbage-sgtl5000",
> 		     "fsl,imx-audio-sgtl5000";
> 	model = "imx51-babbage-sgtl5000";
> 	ssi-controller = <&ssi1>;
> 	audio-codec = <&sgtl5000>;
> 	mux-int-port = <1>;
> 	mux-ext-port = <3>;
> };

> How does this handle multiple SSIs, each connected to its own codec?

With this card those would just be separate CODECs.  This is a binding
for a simple card.

> And where's the binding for the DMA controller?

The DMA controller is transparently instantiated on Tegra systems, there
really isn't a meaningfully separate DMA controller - the I2S controller
specifies the signal to use.  Currently the card takes care of the ASoC
level driver stuff but it really should be done by the I2S controller.

> I honestly don't see how this is an improvement over what I came up with.

The biggest improvement is that the SoC binding knows nothing about the
card binding at all, cards are completely separate and are free to
define any binding they choose using any number of on-SoC and off-SoC
devices.
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From olof at lixom.net  Tue Mar 13 19:46:56 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 16:46:56 -0700
Subject: [GIT PULL 2/4] Samsung devel-pd for v3.4
In-Reply-To: <201203102209.22451.rjw@sisk.pl>
References: <4F5B7C81.6080301@samsung.com>
 <CAOesGMjff3gVNJQ5FpJuSf+uvVDW8k22b+Xcikot-isM-4-6iw@mail.gmail.com>
 <201203102209.22451.rjw@sisk.pl>
Message-ID: <CAOesGMiOXKV03YC=6eG6rHhWw+ObGYoVJCqrPdHAsZLmjjzmtw@mail.gmail.com>

Hi,

On Sat, Mar 10, 2012 at 1:09 PM, Rafael J. Wysocki <rjw at sisk.pl> wrote:
> Hi,
>
> On Saturday, March 10, 2012, Olof Johansson wrote:
>> Hi Rafael,
>>
>> The below series contains two patches that have been sent to you, and
>> that are sitting in the pm-domains branch.
>>
>> Two questions before I pull this into arm-soc:
>>
>> 1) Are you 100% sure this will be submitted to 3.4? And if so, will
>> you send it early during the merge window?
>
> Yes and yes.
>
>> 2) Are you 100% sure you will not rebase the branch into which you
>> pulled the v3.4-for-rafael branch?
>
> Yes, I am.
>
>> I am asking because if we pull this in, and you rebase between now and
>> when it's sent in, we're risking merge conflicts that will be painful
>> to resolve. We've been bitten by that from other dependencies in the
>> past so we're being careful.
>
> Sure, I understand that.
>
> As a general rule, topic braches in my tree whose names start with pm- are
> never rebased (exactly for this reason).

Excellent, thanks! I'll pull that in as a depends/ branch in arm-soc
(since that's how we document it), and mark it in our notes so the
Samsung branch gets merged after yours when going to Linus.



-Olof


From khilman at ti.com  Tue Mar 13 19:52:49 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 13 Mar 2012 16:52:49 -0700
Subject: [PATCH 0/3] coupled cpuidle state support
In-Reply-To: <4F1929E9.7070707@linaro.org> (Daniel Lezcano's message of "Fri, 
 20 Jan 2012 09:46:33 +0100")
References: <1324426147-16735-1-git-send-email-ccross@android.com>
 <4F1929E9.7070707@linaro.org>
Message-ID: <8762e8kqi6.fsf@ti.com>

Hi Colin,

On 12/21/2011 01:09 AM, Colin Cross wrote:

> To use coupled cpuidle states, a cpuidle driver must:

[...]

>     Provide a struct cpuidle_state.enter function for each state
>     that affects multiple cpus.  This function is guaranteed to be
>     called on all cpus at approximately the same time.  The driver
>     should ensure that the cpus all abort together if any cpu tries
>     to abort once the function is called.

I've discoved the last sentence above is crucial, and in order to catch
all the corner cases I found it useful to have the struct
cpuidle_coupled in cpuidle.h so that the driver can check ready_count
itself (patch below, on top of $SUBJECT series.)

As you know, on OMAP4, when entering the coupled state, CPU0 has to wait
for CPU1 to enter its low power state before entering itself.  The first
pass at implementing this was to just spin waiting for the powerdomain
of CPU1 to hit off.  That works... most of the time.

If CPU1 wakes up immediately (or before CPU0 starts checking), or more
likely, fails to hit the low-power state because of other hardware
"conditions", CPU0 will end up stuck in the loop waiting for CPU1.

To solve this, in addition to checking the power state of CPU1, I also 
check if (coupled->ready_count != cpumask_weight(&coupled->alive_coupled_cpus)).
If true, it means that CPU1 has already exited/aborted so CPU0 had
better abort as well.

Checking the ready_count seemed like an easy way to do this, but did you
have any other mechanisms in mind for CPUs to communicate that they've
exited/aborted?

Kevin


diff --git a/drivers/cpuidle/cpuidle.h b/drivers/cpuidle/cpuidle.h
index bf34d67..16e00cc 100644
--- a/drivers/cpuidle/cpuidle.h
+++ b/drivers/cpuidle/cpuidle.h
@@ -32,15 +32,6 @@ extern void cpuidle_remove_state_sysfs(struct cpuidle_device *device);
 extern int cpuidle_add_sysfs(struct device *dev);
 extern void cpuidle_remove_sysfs(struct device *dev);
 
-/* coupled states */
-struct cpuidle_coupled {
-	spinlock_t lock;
-	int requested_state[NR_CPUS];
-	int ready_count;
-	cpumask_t alive_coupled_cpus;
-	int refcnt;
-};
-
 #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
 bool cpuidle_state_is_coupled(struct cpuidle_device *dev,
 		struct cpuidle_driver *drv, int state);
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 71f2fba..dbc1f2e 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -51,6 +51,15 @@ struct cpuidle_state {
 			int index);
 };
 
+/* coupled states */
+struct cpuidle_coupled {
+	spinlock_t lock;
+	int requested_state[NR_CPUS];
+	int ready_count;
+	cpumask_t alive_coupled_cpus;
+	int refcnt;
+};
+
 /* Idle State Flags */
 #define CPUIDLE_FLAG_TIME_VALID	(0x01) /* is residency time measurable? */
 #define CPUIDLE_FLAG_COUPLED	(0x02) /* state applies to multiple cpus */



From ccross at android.com  Tue Mar 13 20:28:15 2012
From: ccross at android.com (Colin Cross)
Date: Tue, 13 Mar 2012 17:28:15 -0700
Subject: [PATCH 0/3] coupled cpuidle state support
In-Reply-To: <8762e8kqi6.fsf@ti.com>
References: <1324426147-16735-1-git-send-email-ccross@android.com>
 <4F1929E9.7070707@linaro.org> <8762e8kqi6.fsf@ti.com>
Message-ID: <CAMbhsRRZ+xt179RN32-+eBWngbRow=MpKV1XcLvG-sHGF6VOJA@mail.gmail.com>

On Tue, Mar 13, 2012 at 4:52 PM, Kevin Hilman <khilman at ti.com> wrote:
> Hi Colin,
>
> On 12/21/2011 01:09 AM, Colin Cross wrote:
>
>> To use coupled cpuidle states, a cpuidle driver must:
>
> [...]
>
>> ? ? Provide a struct cpuidle_state.enter function for each state
>> ? ? that affects multiple cpus. ?This function is guaranteed to be
>> ? ? called on all cpus at approximately the same time. ?The driver
>> ? ? should ensure that the cpus all abort together if any cpu tries
>> ? ? to abort once the function is called.
>
> I've discoved the last sentence above is crucial, and in order to catch
> all the corner cases I found it useful to have the struct
> cpuidle_coupled in cpuidle.h so that the driver can check ready_count
> itself (patch below, on top of $SUBJECT series.)

ready_count is an internal state of core coupled code, and will change
significantly in the next version of the patches.  Drivers cannot
depend on it.

> As you know, on OMAP4, when entering the coupled state, CPU0 has to wait
> for CPU1 to enter its low power state before entering itself. ?The first
> pass at implementing this was to just spin waiting for the powerdomain
> of CPU1 to hit off. ?That works... most of the time.
>
> If CPU1 wakes up immediately (or before CPU0 starts checking), or more
> likely, fails to hit the low-power state because of other hardware
> "conditions", CPU0 will end up stuck in the loop waiting for CPU1.
>
> To solve this, in addition to checking the power state of CPU1, I also
> check if (coupled->ready_count != cpumask_weight(&coupled->alive_coupled_cpus)).
> If true, it means that CPU1 has already exited/aborted so CPU0 had
> better abort as well.
>
> Checking the ready_count seemed like an easy way to do this, but did you
> have any other mechanisms in mind for CPUs to communicate that they've
> exited/aborted?

Why not set a flag from CPU1 when it exits the low power state, and
have CPU0 spin on the powerdomain register or the flag?  You can then
use the parallel barrier function to ensure both cpus have seen the
flag and reset it to 0 before returning.


From ccross at android.com  Tue Mar 13 20:39:54 2012
From: ccross at android.com (Colin Cross)
Date: Tue, 13 Mar 2012 17:39:54 -0700
Subject: [PATCH 0/3] coupled cpuidle state support
In-Reply-To: <4EF1CD49.9020800@linux.intel.com>
References: <1324426147-16735-1-git-send-email-ccross@android.com>
 <4EF1A0B4.5080307@linux.intel.com>
 <CAMbhsRRP7s9xsHqxhb=iMfHAJFcqAea-6CDORZS34RCPNo+UWw@mail.gmail.com>
 <4EF1AA8A.8060304@linux.intel.com>
 <CAMbhsRSNTUvou9Gf6T4Ggq=jfxsWUcn7M2yNsKQz6aNrt6gLDg@mail.gmail.com>
 <4EF1CD49.9020800@linux.intel.com>
Message-ID: <CAMbhsRS00BFgun=vA21LnuCW9HEH-72uFnNoB6A3GbVqkJEuWQ@mail.gmail.com>

On Wed, Dec 21, 2011 at 4:12 AM, Arjan van de Ven <arjan at linux.intel.com> wrote:
> On 12/21/2011 10:55 AM, Colin Cross wrote:
>> On Wed, Dec 21, 2011 at 1:44 AM, Arjan van de Ven <arjan at linux.intel.com> wrote:
>>> On 12/21/2011 10:40 AM, Colin Cross wrote:
>>>
>>>>> this smells fundamentally racey to me; you can get an interrupt one
>>>>> cycle after you think you're done, but before the last guy enters WFI...
>>>>>
>>>>> how do you solve that issue ?
>>>>
>>>> All the cpus have interrupts off when they increment the counter, so
>>>> they cannot receive an interrupt. ?If an interrupt is pending on one
>>>> of those cpus, it will be handled later when WFI aborts due to the
>>>> pending interrupt.
>>>
>>> ... but this leads to cases where you're aborting before other cpus are
>>> entering..... so your "last guy in" doesn't really work, since while cpu
>>> 0 thinks it's the last guy, cpu 1 is already on the way out/out
>>> already... ?(heck it might already be going back to sleep if your idle
>>> code can run fast, like in the size of a cache miss)
>>
>> Once a cpu has incremented the counter, it has no way out unless either
>> 1: another cpu (that hasn't incremented the counter yet) receives an
>> interrupt, aborts idle, and clears its idle flag
>> or
>> 2: all cpus enter the ready counter, and call the cpuidle driver's
>> enter function.
>
> .. or it enters WFI, and a physical device sends it an interrupt,
> at which point it exits.

Rereading this, I think I understand what you meant.  I misunderstood
because of your reference to WFI, which is not entered at this point.
WFI generally refers to the shallowest idle state, which only affects
a single cpu.  For deeper states, the cpu may or may not execute the
WFI instruction to trigger the transition (depending on the platform),
but it's not really entering WFI, and the cpu will generally not ever
execute the next instruction (again, depending on the platform).

For coupled cpus, only one cpu is capable of booting first, so all
interrupts should be masked on cpu1 by the time it gets to its low
power state, so it should never abort.  If it does abort (like the
example Kevin Hillman just posted to the end of this thread), cpu1
needs to set a flag to say it is not going to get to idle, and cpu0
needs to wait for cpu1 to be in idle (by polling a power controller
register), or for the flag to be set.  Afterwards, the cpus need to
resynchronize and reset the flag, which will be easy with the parallel
barrier helper function that will be included in the next patch set.


From ccross at android.com  Tue Mar 13 20:47:20 2012
From: ccross at android.com (Colin Cross)
Date: Tue, 13 Mar 2012 17:47:20 -0700
Subject: [PATCH 0/3] coupled cpuidle state support
In-Reply-To: <CAMbhsRRZ+xt179RN32-+eBWngbRow=MpKV1XcLvG-sHGF6VOJA@mail.gmail.com>
References: <1324426147-16735-1-git-send-email-ccross@android.com>
 <4F1929E9.7070707@linaro.org> <8762e8kqi6.fsf@ti.com>
 <CAMbhsRRZ+xt179RN32-+eBWngbRow=MpKV1XcLvG-sHGF6VOJA@mail.gmail.com>
Message-ID: <CAMbhsRRD2bdkcUZvScb-cF05e=R3h69bNVaTPFX4jBKBBOjuMg@mail.gmail.com>

On Tue, Mar 13, 2012 at 5:28 PM, Colin Cross <ccross at android.com> wrote:
> On Tue, Mar 13, 2012 at 4:52 PM, Kevin Hilman <khilman at ti.com> wrote:
>> Hi Colin,
>>
>> On 12/21/2011 01:09 AM, Colin Cross wrote:
>>
>>> To use coupled cpuidle states, a cpuidle driver must:
>>
>> [...]
>>
>>> ? ? Provide a struct cpuidle_state.enter function for each state
>>> ? ? that affects multiple cpus. ?This function is guaranteed to be
>>> ? ? called on all cpus at approximately the same time. ?The driver
>>> ? ? should ensure that the cpus all abort together if any cpu tries
>>> ? ? to abort once the function is called.
>>
>> I've discoved the last sentence above is crucial, and in order to catch
>> all the corner cases I found it useful to have the struct
>> cpuidle_coupled in cpuidle.h so that the driver can check ready_count
>> itself (patch below, on top of $SUBJECT series.)
>
> ready_count is an internal state of core coupled code, and will change
> significantly in the next version of the patches. ?Drivers cannot
> depend on it.
>
>> As you know, on OMAP4, when entering the coupled state, CPU0 has to wait
>> for CPU1 to enter its low power state before entering itself. ?The first
>> pass at implementing this was to just spin waiting for the powerdomain
>> of CPU1 to hit off. ?That works... most of the time.
>>
>> If CPU1 wakes up immediately (or before CPU0 starts checking), or more
>> likely, fails to hit the low-power state because of other hardware
>> "conditions", CPU0 will end up stuck in the loop waiting for CPU1.
>>
>> To solve this, in addition to checking the power state of CPU1, I also
>> check if (coupled->ready_count != cpumask_weight(&coupled->alive_coupled_cpus)).
>> If true, it means that CPU1 has already exited/aborted so CPU0 had
>> better abort as well.
>>
>> Checking the ready_count seemed like an easy way to do this, but did you
>> have any other mechanisms in mind for CPUs to communicate that they've
>> exited/aborted?
>
> Why not set a flag from CPU1 when it exits the low power state, and
> have CPU0 spin on the powerdomain register or the flag? ?You can then
> use the parallel barrier function to ensure both cpus have seen the
> flag and reset it to 0 before returning.

I realized the parallel barrier helper was not included in the patch
set I posted, it will be in the next patch set.  Short version, no
caller to cpuidle_coupled_parallel_barrier will return before all cpus
in the coupled set have called it.  It allows you to resynchronize the
cpus after an abort to ensure they have all seen the abort flag before
clearing it and returning, leaving everything in the correct state for
the next idle attempt.


From olof at lixom.net  Tue Mar 13 20:52:13 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 17:52:13 -0700
Subject: Conflict between Versatile Express DT conversion and local timer
 updates
In-Reply-To: <201203131433.07214.arnd@arndb.de>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <201203131155.16454.arnd@arndb.de> <4F5F52A2.3050005@arm.com>
 <201203131433.07214.arnd@arndb.de>
Message-ID: <CAOesGMjo=JT3TKwne+m5XUpkBMQFKQLZrr1T60m+Wx7YgqMiOA@mail.gmail.com>

On Tue, Mar 13, 2012 at 7:33 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Tuesday 13 March 2012, Marc Zyngier wrote:
>> On 13/03/12 11:55, Arnd Bergmann wrote:
>> > On Tuesday 13 March 2012, Marc Zyngier wrote:
>> >> On 13/03/12 10:15, Russell King - ARM Linux wrote:
>
>> > d) create a new next/timer branch in arm-soc that has Pawel's
>> > ? ?98ed4ceb "ARM: vexpress: Get rid of MMIO_P2V" (the first patch from
>> > ? ?vexpress/dt, your patches and the ux500/timer series. Also put
>> > ? ?98ed4ceb into the next/cleanup branch.
>> >
>> > Any of those will work for us, my preference would be on #4. I have
>> > created the next/timer branch in the arm-soc tree, so you can use
>> > that and either rebase your patches on top or merge your tree into
>> > it and fix up the merge conflicts.
>>
>> Thanks for doing that Arnd.
>>
>> I've thus created a new branch:
>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>> local_timers-for-arm-soc
>>
>> which contains the arm-soc next/timers branch as well as my local timers
>> series. I'd greatly appreciate if you could pull it for 3.4.
>>
>
> I've updated the next/timer branch with your changes now, but did not
> put it into the for-next branch because Olof is currently handling that.
>
> Olof, can you add it to for-next please? The timer branch should have
> no dependencies other than rmk/for-armsoc, so it can be fairly close to
> the start.


Thanks. I merged into for-next, but since there's already a history in
there and I didn't rebuild it, it's on top of everything else.

I got two trivial merge conflicts (and a few that git sorted out
automatically): one with the tegra makefile, the other with shmobile's
timer init.

Marc, please take a look at the next/timers merge in the arm-soc
for-next branch and let me know if they're OK. I'm pretty sure they
are though.


-Olof


From olof at lixom.net  Tue Mar 13 20:52:40 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 17:52:40 -0700
Subject: [GIT PULL v2] Samsung cleanup EXYNOS clock for v3.4
In-Reply-To: <4F5C6310.5010402@samsung.com>
References: <4F5C6310.5010402@samsung.com>
Message-ID: <CAOesGMjPxTL8EDKgbJ7Ubsn2-Esgj+vobwGPkRNJWRW8CZd8+g@mail.gmail.com>

On Sun, Mar 11, 2012 at 12:32 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Hi Arnd, Olof,
>
> I rebased cleanup-exynos-clock on top of cleanup-use-static as per Olof's
> suggestion.
>
> Please pull it from:
> ?git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/cleanup-exynos-clock
>
> If any problems, please kindly let me know.
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> The following changes since commit c15a04338b5a6d4305d107a5b6c0cd43418b7f3e:
>
> ?Merge branch 'next/cleanup-use-static' into next/cleanup-exynos-clock
> (2012-03-10 22:21:36 -0800)
>
> are available in the git repository at:
>
> ?git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/cleanup-exynos-clock

Thanks, pulled into next/cleanup.


-Olof


From olof at lixom.net  Tue Mar 13 20:52:47 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 17:52:47 -0700
Subject: [GIT PULL v2] Samsung board patches for v3.4
In-Reply-To: <4F5C64A1.1090900@samsung.com>
References: <4F5C64A1.1090900@samsung.com>
Message-ID: <CAOesGMjZF1BHMdeR3Gvp9jm0u5DEYPTXELP0XKOPr8hQuNLCvA@mail.gmail.com>

Hi,

On Sun, Mar 11, 2012 at 12:38 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Hi Arnd, Olof,
>
> Please pull regarding rebased Samsung board patches without the non-dt board
> file addition for v3.4.
>
> If any problems, please let me know.
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
>
> ?Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)
>
> are available in the git repository at:
> ?git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/board-samsung

Pulled into next/boards. Thanks.


-Olof


From olof at lixom.net  Tue Mar 13 20:52:54 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 17:52:54 -0700
Subject: [GIT PULL v2 3/4] Samsung devel-mmc for v3.4
In-Reply-To: <4F5C68AE.4000101@samsung.com>
References: <4F5C68AE.4000101@samsung.com>
Message-ID: <CAOesGMh3T-aioauhEBXE3_t6HpY=9ejUK6OE=nvR_VxcRzv4xQ@mail.gmail.com>

Hi,

On Sun, Mar 11, 2012 at 12:56 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Hi Arnd, Olof
>
> Please pull Samsung devel-mmc for v3.4 and I rebased it on top of v3.3-rc7
> without v3.4-for-cjb.
>
> Please pull it from:
> ?git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/devel-samsung-mmc
>
>
> If any problems, please kindly let me know.
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
>
> ?Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)
>
>
> are available in the git repository at:
> ?git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/devel-samsung-mmc

Thanks, pulled into next/drivers.


-Olof


From olof at lixom.net  Tue Mar 13 20:53:00 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 17:53:00 -0700
Subject: [GIT PULL v2 4/4] Samsung devel-dma for v3.4
In-Reply-To: <4F5C6A6D.9010400@samsung.com>
References: <4F5C6A6D.9010400@samsung.com>
Message-ID: <CAOesGMh6S5hBB2n+5nzonnGQ8r-B3984Dyg1QTAkNpawV+dYeA@mail.gmail.com>

Hi,

On Sun, Mar 11, 2012 at 1:03 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Hi Arnd, Olof,
>
> I rebased devel-samsung-dma on top of new next-exynos-clock as per Olof's
> suggestion.
>
> Please pull it from:
> ?git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/devel-samsung-dma
>
> If any problems, please let me know.
>
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> The following changes since commit 44b2cef5ae6da48523fa634230ca66107110a7dd:
>
> ?ARM: EXYNOS: Add clock register addresses for EXYNOS4X12 bus devfreq driver
> (2012-03-10 22:30:32 -0800)
>
>
> are available in the git repository at:
> ?git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/devel-samsung-dma

Thanks, pulled into next/drivers.


-Olof


From olof at lixom.net  Tue Mar 13 20:53:06 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 17:53:06 -0700
Subject: [GIT PULL 2/4] Samsung devel-pd for v3.4
In-Reply-To: <4F5B7C81.6080301@samsung.com>
References: <4F5B7C81.6080301@samsung.com>
Message-ID: <CAOesGMg8iv=jE52sFs-np4HXuokMstZt8igHTQBJ4wJNOCae9A@mail.gmail.com>

Hi,

On Sat, Mar 10, 2012 at 8:08 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Hi Arnd, Olof,
>
> This is Generic Power Domain patches for EXYNOS. Basically, Thomas' patches,
> adding support Generic Power Domain patches are in Rafael's tree,
> linux-pm/linux-next and see below merge commit.
> http://git.kernel.org/?p=linux/kernel/git/rafael/linux-pm.git;a=commit;h=dcaad77a8074b6de58e745546bc543d5538404f2
> And this adds hooking up G2D and JPEG to Generic PD.
>
> Please pull and here is my preferred resolution when merge this after
> next/board-samsung.
>
> diff --cc arch/arm/mach-exynos/mach-universal_c210.c
> index 3663aee,0262417..0b944eb
> --- a/arch/arm/mach-exynos/mach-universal_c210.c
> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
> @@@ -1053,10 -981,6 +1052,7 @@@ static struct platform_device *universa
> ? ? ? ?&s5p_device_mfc,
> ? ? ? ?&s5p_device_mfc_l,
> ? ? ? ?&s5p_device_mfc_r,
> - ? ? ? &exynos4_device_pd[PD_MFC],
> - ? ? ? &exynos4_device_pd[PD_LCD0],
> - ? ? ? &exynos4_device_pd[PD_CAM],
> ?+ ? ? ?&cam_vt_dio_fixed_reg_dev,
> ? ? ? ?&cam_i_core_fixed_reg_dev,
> ? ? ? ?&cam_s_if_fixed_reg_dev,
> ? ? ? ?&s5p_device_fimc_md,
>
> If any problems, please kindly let me know.
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:
>
> ?Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)
>
> are available in the git repository at:
> ?git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> next/devel-samsung-pd


Pulled, thanks!


-Olof


From rmallon at gmail.com  Tue Mar 13 21:18:21 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Wed, 14 Mar 2012 12:18:21 +1100
Subject: [PATCH v4 02/11] ep93xx: Don't use system controller defines
 in audio drivers
In-Reply-To: <201203131209.52031.arnd@arndb.de>
References: <1331592502-9083-3-git-send-email-rmallon@gmail.com>
 <201203131209.52031.arnd@arndb.de>
Message-ID: <4F5FF1DD.5020003@gmail.com>

On 13/03/12 23:09, Arnd Bergmann wrote:

> On Monday 12 March 2012, Ryan Mallon wrote:
>> This patch has already been applied in Mark's tree. It is posted
>> for inclusion here because this series is against v3.3-rc7 and
>> will cause build failures without it. There have been no changes
>> to the patch since Mark applied it, so it should be okay to
>> merge into both his tree and the arm-soc tree.
> 
> Ok, that should work. However, in the future when you anticipate
> having to do something like this, I would suggest you do any patches
> that you want to see applied to multiple branches as git-pull
> requests, because that allows us to use the same changeset ids.

Okay, the patches still need to be posted as a series for review before
doing a pull request though right? Should I just put a note on such
patches (below the changelog) that I am expecting to send them all via
arm-soc so that other maintainers don't grab individual patches for
driver support?

> When we apply one patch separately to two branches, we end up
> with multiple changesets in the git history, which is something
> we normally try to avoid.


Okay, thanks for the heads up.

~Ryan



From chanho0207 at gmail.com  Tue Mar 13 21:47:37 2012
From: chanho0207 at gmail.com (Chanho Min)
Date: Wed, 14 Mar 2012 10:47:37 +0900
Subject: [PATCH v3] serial: PL011: clear pending interrupts
In-Reply-To: <1331641643-25929-1-git-send-email-linus.walleij@stericsson.com>
References: <1331641643-25929-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CAOAMb1AKmsNQbmVAaYq5G8cdafCVpRyA=5xgocqYfLsQ6BLXMw@mail.gmail.com>

On Tue, Mar 13, 2012 at 9:27 PM, Linus Walleij
<linus.walleij at stericsson.com> wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
>
> Chanho Min reported that when the boot loader transfers
> control to the kernel, there may be pending interrupts
> causing the UART to lock up in an eternal loop trying to
> pick tokens from the FIFO (since the RX interrupt flag
> indicates there are tokens) while in practice there are
> no tokens - in fact there is only a pending IRQ flag.
>
> This patch address the issue with a combination of two
> patches suggested by Russell King that clears and mask
> all interrupts at probe() and clears any pending error
> and RX interrupts at port startup time.
>
> We suspect the spurious interrupts are a side-effect of
> switching the UART from FIFO to non-FIFO mode.
I've tested this patch, and have confirmed that the issue is resolved
on our CA9 platform.
In addition, May I ask to change the tag as follows.

Reported-by: Chanho Min <chanho.min at lge.com>
Reviewed-by: Jong-Sung Kim <neidhard.kim at lge.com>

Thanks a lot !
Chanho Min


From jg1.han at samsung.com  Tue Mar 13 21:51:14 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Wed, 14 Mar 2012 10:51:14 +0900
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
Message-ID: <000501cd0184$f088cb20$d19a6160$%han@samsung.com>

> -----Original Message-----
> From: Thomas Abraham [mailto:thomas.abraham at linaro.org]
> Sent: Tuesday, March 13, 2012 7:11 PM
> To: Jingoo Han
> Cc: linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-kernel at lists.infradead.org; linux-
> samsung-soc at vger.kernel.org; kgene.kim at samsung.com; ben-linux at fluff.org; patches at linaro.org; Kyungmin
> Park; JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter Korsgaard; Darius Augulis; Maurus
> Cuelenaere
> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> 
> On 13 March 2012 15:17, Jingoo Han <jg1.han at samsung.com> wrote:
> >> -----Original Message-----
> >> From: Thomas Abraham [mailto:thomas.abraham at linaro.org]
> >> Sent: Tuesday, March 13, 2012 6:00 AM
> >> To: linux-fbdev at vger.kernel.org
> >> Cc: FlorianSchandinat at gmx.de; linux-arm-kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org;
> >> kgene.kim at samsung.com; jg1.han at samsung.com; ben-linux at fluff.org; patches at linaro.org; Kyungmin Park;
> >> JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter Korsgaard; Darius Augulis; Maurus
> >> Cuelenaere
> >> Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> >>
> >> For all the Samsung SoC based boards which have the platform data for
> >> s3c-fb driver, the 'default_win' element in the platform data is removed
> >> and the lcd panel video timing values are moved out of individual window
> >> configuration data.
> >>
> >> Cc: Jingoo Han <jg1.han at samsung.com>
> >> Cc: Kyungmin Park <kyungmin.park at samsung.com>
> >> Cc: JeongHyeon Kim <jhkim at insignal.co.kr>
> >> Cc: Kukjin Kim <kgene.kim at samsung.com>
> >> Cc: Heiko Stuebner <heiko at sntech.de>
> >> Cc: Ben Dooks <ben-linux at fluff.org>
> >> Cc: Kwangwoo Lee <kwangwoo.lee at gmail.com>
> >> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> >> Cc: Peter Korsgaard <jacmet at sunsite.dk>
> >> Cc: Darius Augulis <augulis.darius at gmail.com>
> >> Cc: Maurus Cuelenaere <mcuelenaere at gmail.com>
> >> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> >> ---
> >> ?arch/arm/mach-exynos/mach-nuri.c ? ? ? ? ? | ? 26 ++++++++++-------
> >> ?arch/arm/mach-exynos/mach-origen.c ? ? ? ? | ? 24 ++++++++++-------
> >> ?arch/arm/mach-exynos/mach-smdkv310.c ? ? ? | ? 28 +++++++++++--------
> >> ?arch/arm/mach-exynos/mach-universal_c210.c | ? 26 ++++++++++-------
> >> ?arch/arm/mach-s3c24xx/mach-smdk2416.c ? ? ?| ? 27 ++++++++++--------
> >> ?arch/arm/mach-s3c64xx/mach-anw6410.c ? ? ? | ? 25 ++++++++++-------
> >> ?arch/arm/mach-s3c64xx/mach-crag6410.c ? ? ?| ? 25 ++++++++++-------
> >> ?arch/arm/mach-s3c64xx/mach-hmt.c ? ? ? ? ? | ? 24 ++++++++++-------
> >> ?arch/arm/mach-s3c64xx/mach-mini6410.c ? ? ?| ? 40 ++++++++++++---------------
> >> ?arch/arm/mach-s3c64xx/mach-real6410.c ? ? ?| ? 40 ++++++++++++---------------
> >> ?arch/arm/mach-s3c64xx/mach-smartq5.c ? ? ? | ? 26 ++++++++++-------
> >> ?arch/arm/mach-s3c64xx/mach-smartq7.c ? ? ? | ? 26 ++++++++++-------
> >> ?arch/arm/mach-s3c64xx/mach-smdk6410.c ? ? ?| ? 25 ++++++++++-------
> >> ?arch/arm/mach-s5p64x0/mach-smdk6440.c ? ? ?| ? 24 ++++++++++-------
> >> ?arch/arm/mach-s5p64x0/mach-smdk6450.c ? ? ?| ? 24 ++++++++++-------
> >> ?arch/arm/mach-s5pc100/mach-smdkc100.c ? ? ?| ? 27 ++++++++++--------
> >> ?arch/arm/mach-s5pv210/mach-aquila.c ? ? ? ?| ? 36 +++++++++++--------------
> >> ?arch/arm/mach-s5pv210/mach-goni.c ? ? ? ? ?| ? 26 ++++++++++-------
> >> ?arch/arm/mach-s5pv210/mach-smdkv210.c ? ? ?| ? 24 ++++++++++-------
> >> ?19 files changed, 285 insertions(+), 238 deletions(-)
> >>
> >
> > [.....]
> >
> >> diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
> >> index c34c2ab..24dcdc9 100644
> >> --- a/arch/arm/mach-s3c64xx/mach-mini6410.c
> >> +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
> >> @@ -153,36 +153,32 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
> >>
> >> ?static struct s3c_fb_pd_win mini6410_fb_win[] = {
> >> ? ? ? {
> >> - ? ? ? ? ? ? .win_mode ? ? ? = { ? ? /* 4.3" 480x272 */
> >> - ? ? ? ? ? ? ? ? ? ? .left_margin ? ?= 3,
> >> - ? ? ? ? ? ? ? ? ? ? .right_margin ? = 2,
> >> - ? ? ? ? ? ? ? ? ? ? .upper_margin ? = 1,
> >> - ? ? ? ? ? ? ? ? ? ? .lower_margin ? = 1,
> >> - ? ? ? ? ? ? ? ? ? ? .hsync_len ? ? ?= 40,
> >> - ? ? ? ? ? ? ? ? ? ? .vsync_len ? ? ?= 1,
> >> - ? ? ? ? ? ? ? ? ? ? .xres ? ? ? ? ? = 480,
> >> - ? ? ? ? ? ? ? ? ? ? .yres ? ? ? ? ? = 272,
> >> - ? ? ? ? ? ? },
> >> ? ? ? ? ? ? ? .max_bpp ? ? ? ?= 32,
> >> ? ? ? ? ? ? ? .default_bpp ? ?= 16,
> >> + ? ? ? ? ? ? .xres ? ? ? ? ? = 480,
> >> + ? ? ? ? ? ? .yres ? ? ? ? ? = 272,
> >> ? ? ? }, {
> >> - ? ? ? ? ? ? .win_mode ? ? ? = { ? ? /* 7.0" 800x480 */
> >> - ? ? ? ? ? ? ? ? ? ? .left_margin ? ?= 8,
> >> - ? ? ? ? ? ? ? ? ? ? .right_margin ? = 13,
> >> - ? ? ? ? ? ? ? ? ? ? .upper_margin ? = 7,
> >> - ? ? ? ? ? ? ? ? ? ? .lower_margin ? = 5,
> >> - ? ? ? ? ? ? ? ? ? ? .hsync_len ? ? ?= 3,
> >> - ? ? ? ? ? ? ? ? ? ? .vsync_len ? ? ?= 1,
> >> - ? ? ? ? ? ? ? ? ? ? .xres ? ? ? ? ? = 800,
> >> - ? ? ? ? ? ? ? ? ? ? .yres ? ? ? ? ? = 480,
> >> - ? ? ? ? ? ? },
> >> ? ? ? ? ? ? ? .max_bpp ? ? ? ?= 32,
> >> ? ? ? ? ? ? ? .default_bpp ? ?= 16,
> >> + ? ? ? ? ? ? .xres ? ? ? ? ? = 800,
> >> + ? ? ? ? ? ? .yres ? ? ? ? ? = 480,
> >> ? ? ? },
> >> ?};
> >>
> >> +static struct fb_videomode mini6410_lcd_timing = {
> >> + ? ? .left_margin ? ?= 8,
> >> + ? ? .right_margin ? = 13,
> >> + ? ? .upper_margin ? = 7,
> >> + ? ? .lower_margin ? = 5,
> >> + ? ? .hsync_len ? ? ?= 3,
> >> + ? ? .vsync_len ? ? ?= 1,
> >> + ? ? .xres ? ? ? ? ? = 800,
> >> + ? ? .yres ? ? ? ? ? = 480,
> >> +};
> >> +
> >> ?static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
> >> ? ? ? .setup_gpio ? ? = s3c64xx_fb_gpio_setup_24bpp,
> >> + ? ? .vtiming ? ? ? ?= &mini6410_lcd_timing,
> >> ? ? ? .win[0] ? ? ? ? = &mini6410_fb_win[0],
> >> ? ? ? .vidcon0 ? ? ? ?= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> >> ? ? ? .vidcon1 ? ? ? ?= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> >> @@ -310,8 +306,8 @@ static void __init mini6410_machine_init(void)
> >> ? ? ? mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
> >>
> >> ? ? ? printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
> >> - ? ? ? ? ? ? mini6410_lcd_pdata.win[0]->win_mode.xres,
> >> - ? ? ? ? ? ? mini6410_lcd_pdata.win[0]->win_mode.yres);
> >> + ? ? ? ? ? ? mini6410_lcd_pdata.win[0]->xres,
> >> + ? ? ? ? ? ? mini6410_lcd_pdata.win[0]->yres);
> >>
> >> ? ? ? s3c_nand_set_platdata(&mini6410_nand_info);
> >> ? ? ? s3c_fb_set_platdata(&mini6410_lcd_pdata);
> >> diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
> >> index be2a9a2..41e4f74 100644
> >> --- a/arch/arm/mach-s3c64xx/mach-real6410.c
> >> +++ b/arch/arm/mach-s3c64xx/mach-real6410.c
> >> @@ -119,36 +119,32 @@ static struct platform_device real6410_device_eth = {
> >>
> >> ?static struct s3c_fb_pd_win real6410_fb_win[] = {
> >> ? ? ? {
> >> - ? ? ? ? ? ? .win_mode ? ? ? = { ? ? /* 4.3" 480x272 */
> >> - ? ? ? ? ? ? ? ? ? ? .left_margin ? ?= 3,
> >> - ? ? ? ? ? ? ? ? ? ? .right_margin ? = 2,
> >> - ? ? ? ? ? ? ? ? ? ? .upper_margin ? = 1,
> >> - ? ? ? ? ? ? ? ? ? ? .lower_margin ? = 1,
> >> - ? ? ? ? ? ? ? ? ? ? .hsync_len ? ? ?= 40,
> >> - ? ? ? ? ? ? ? ? ? ? .vsync_len ? ? ?= 1,
> >> - ? ? ? ? ? ? ? ? ? ? .xres ? ? ? ? ? = 480,
> >> - ? ? ? ? ? ? ? ? ? ? .yres ? ? ? ? ? = 272,
> >> - ? ? ? ? ? ? },
> >> ? ? ? ? ? ? ? .max_bpp ? ? ? ?= 32,
> >> ? ? ? ? ? ? ? .default_bpp ? ?= 16,
> >> + ? ? ? ? ? ? .xres ? ? ? ? ? = 480,
> >> + ? ? ? ? ? ? .yres ? ? ? ? ? = 272,
> >> ? ? ? }, {
> >> - ? ? ? ? ? ? .win_mode ? ? ? = { ? ? /* 7.0" 800x480 */
> >> - ? ? ? ? ? ? ? ? ? ? .left_margin ? ?= 8,
> >> - ? ? ? ? ? ? ? ? ? ? .right_margin ? = 13,
> >> - ? ? ? ? ? ? ? ? ? ? .upper_margin ? = 7,
> >> - ? ? ? ? ? ? ? ? ? ? .lower_margin ? = 5,
> >> - ? ? ? ? ? ? ? ? ? ? .hsync_len ? ? ?= 3,
> >> - ? ? ? ? ? ? ? ? ? ? .vsync_len ? ? ?= 1,
> >> - ? ? ? ? ? ? ? ? ? ? .xres ? ? ? ? ? = 800,
> >> - ? ? ? ? ? ? ? ? ? ? .yres ? ? ? ? ? = 480,
> >> - ? ? ? ? ? ? },
> >> ? ? ? ? ? ? ? .max_bpp ? ? ? ?= 32,
> >> ? ? ? ? ? ? ? .default_bpp ? ?= 16,
> >> + ? ? ? ? ? ? .xres ? ? ? ? ? = 800,
> >> + ? ? ? ? ? ? .yres ? ? ? ? ? = 480,
> >> ? ? ? },
> >> ?};
> >>
> >> +static struct fb_videomode real6410_lcd_timing = {
> >> + ? ? .left_margin ? ?= 3,
> >> + ? ? .right_margin ? = 2,
> >> + ? ? .upper_margin ? = 1,
> >> + ? ? .lower_margin ? = 1,
> >> + ? ? .hsync_len ? ? ?= 40,
> >> + ? ? .vsync_len ? ? ?= 1,
> >> + ? ? .xres ? ? ? ? ? = 800,
> >> + ? ? .yres ? ? ? ? ? = 480,
> >> +};
> >
> >
> > What is the difference between mini6410_lcd_timing and real6410_lcd_timing?
> > In my opinion, it would be good as follows:
> >
> > +static struct fb_videomode real6410_lcd_timing = {
> > + ? ? ? .left_margin ? ?= 8,
> > + ? ? ? .right_margin ? = 13,
> > + ? ? ? .upper_margin ? = 7,
> > + ? ? ? .lower_margin ? = 5,
> > + ? ? ? .hsync_len ? ? ?= 3,
> > + ? ? ? .vsync_len ? ? ?= 1,
> > + ? ? ? .xres ? ? ? ? ? = 800,
> > + ? ? ? .yres ? ? ? ? ? = 480,
> > +};
> >
> >
> 
> Before this patch series, both real6410 and mini6410 had 'default_win'
> = 0 in the platform data. And, the s3c-fb driver selected the video
> timing from the window selected by the default_win parameter in s3c-fb
> platform data, i.e window 0 for both mini6440 and real6410. So, in
> this patch, while moving the timing values out of window data, the
> timing values for window 0 was selected.
> 
> The timing value for window 1 was never used on mini6410 and real6410.
> So I would suggest to use timing value of window 0 in this patch.

OK, I see.
Then, as you mentioned above, the timing value of mini6410 and real6410 should be same.
Also, the mini6410 should use the timing value for window 0 as below.

Also, this timing value is used for 4.3" 480x272 LCD.
So, xres and yres would be 480 and 272, respectively, instead of 800 and 480.

The mini6410 seems to use 4.3" 480x272 LCD as default LCD.
Please refer to 'http://www.friendlyarm.net/products/mini6410'.

Also, real6410 seems to use 4.3" 480x272 LCD as default LCD.
http://s3c6410kits.googlecode.com/files/overview_Real6410.pdf

Therefore, given this, the timing value of mini6410 and real6410 would be as follows.

+static struct fb_videomode mini6410_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 480,
+	.yres		= 272,
+};

+static struct fb_videomode real6410_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 480,
+	.yres		= 272,
+};

Darius Augulis, can you confirm it?
(Darius Augulis is a maintainer for real6410 and mini6410 boards.)

Best regards,
Jingoo Han

> 
> Thanks for your comments.
> 
> Regards,
> Thomas.



From tarun.kanti at ti.com  Tue Mar 13 21:53:20 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Wed, 14 Mar 2012 07:23:20 +0530
Subject: [PATCH v3 11/13] gpio/omap: fix dataout register overwrite in
 _set_gpio_dataout_*
In-Reply-To: <8762e8v53q.fsf@ti.com>
References: <1331118963-26364-1-git-send-email-tarun.kanti@ti.com>
 <1331118963-26364-12-git-send-email-tarun.kanti@ti.com>
 <87y5r5wkmu.fsf@ti.com>
 <CAC83ZvJ5rjNJoSZW=j=DXQWKWGgr_Wqu8ukOubxKd7xuEQ4pzQ@mail.gmail.com>
 <CAC83Zv+CZOGnSpOJgfCgEv-eyWXZzV+_mmd37CBMKM6iMtEksQ@mail.gmail.com>
 <CAC83ZvLmaLOr4_eZZzKyP2=KvkG+LjHjeOwvxdQHhuiB8+2L0w@mail.gmail.com>
 <8762e8v53q.fsf@ti.com>
Message-ID: <CAC83ZvLkPEu5usQsS9-5nVGdhz69vq3XQYaTwFBjo0FSnS8_Ng@mail.gmail.com>

On Tue, Mar 13, 2012 at 9:57 PM, Kevin Hilman <khilman at ti.com> wrote:
> "DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:
>
>> On Tue, Mar 13, 2012 at 12:03 PM, DebBarma, Tarun Kanti
>> <tarun.kanti at ti.com> wrote:
>>> On Tue, Mar 13, 2012 at 11:33 AM, DebBarma, Tarun Kanti
>>> <tarun.kanti at ti.com> wrote:
>>>> On Tue, Mar 13, 2012 at 3:24 AM, Kevin Hilman <khilman at ti.com> wrote:
>>>>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>>>>>
>>>>>> In the existing _set_gpio_dataout_*() implementation, the dataout
>>>>>> register is overwritten every time the function is called. This is
>>>>>> not intended behavior because that would end up one user of a GPIO
>>>>>> line overwriting what is written by another. Fix this so that previous
>>>>>> value is always preserved until explicitly changed by respective
>>>>>> user/driver of the GPIO line.
>>>>>>
>>>>>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>>>>>> ---
>>>>>> ?drivers/gpio/gpio-omap.c | ? ?3 +++
>>>>>> ?1 files changed, 3 insertions(+), 0 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
>>>>>> index 04c2677..2e8e476 100644
>>>>>> --- a/drivers/gpio/gpio-omap.c
>>>>>> +++ b/drivers/gpio/gpio-omap.c
>>>>>> @@ -114,6 +114,7 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
>>>>>> ? ? ? else
>>>>>> ? ? ? ? ? ? ? reg += bank->regs->clr_dataout;
>>>>>>
>>>>>> + ? ? l |= __raw_readl(bank->base + bank->regs->set_dataout);
>>>>>
>>>>> minor: IMO, it's more reader-friendly if this looks like
>>>>>
>>>>> ? ? ? l = __raw_read(...)
>>>>> ? ? ? l |= GPIO_BIT(...)
>>>>> ? ? ? __raw_write(...)
>>>> Agreed. I will make the change.
>>> Also, the read should be: __raw_readl(bank->base + bank->regs->dataout);
>>> instead of bank->regs->set_dataout.
>> I see a problem with this implementation. It is not correct to write l
>> |= GPIO_BIT(...).
>> For example if we write to clr_dataout register we would end up
>> clearing bits which
>> we are not supposed to. We should just be operating on current GPIO_BIT(...).
>> The l |= GPIO_BIT(...) is needed just to make sure that we have the
>> right context
>> stored. So the overall sequence should be something like this:
>>
>> ? ? ? ? void __iomem *reg = bank->base;
>> ? ? ? ? u32 l = GPIO_BIT(bank, gpio);
>>
>> ? ? ? ? if (enable)
>> ? ? ? ? ? ? ? ? reg += bank->regs->set_dataout;
>> ? ? ? ? else
>> ? ? ? ? ? ? ? ? reg += bank->regs->clr_dataout;
>>
>> ? ? ? ? __raw_writel(l, reg);
>> ? ? ? ? l |= __raw_readl(bank->base + bank->regs->dataout);
>> ? ? ? ? bank->context.dataout = l;
>
> Again, you don't need the extra read-back here. ?Just set/clear the bit
> in the context. ?Untested patch below.
Alright.
--
Tarun
>
> Kevin
>
>
> diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
> index 0b05629..db905c0 100644
> --- a/drivers/gpio/gpio-omap.c
> +++ b/drivers/gpio/gpio-omap.c
> @@ -111,10 +111,13 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
> ? ? ? ?void __iomem *reg = bank->base;
> ? ? ? ?u32 l = GPIO_BIT(bank, gpio);
>
> - ? ? ? if (enable)
> + ? ? ? if (enable) {
> ? ? ? ? ? ? ? ?reg += bank->regs->set_dataout;
> - ? ? ? else
> + ? ? ? ? ? ? ? bank->context.dataout |= l;
> + ? ? ? } else {
> ? ? ? ? ? ? ? ?reg += bank->regs->clr_dataout;
> + ? ? ? ? ? ? ? bank->context.dataout &= ~l;
> + ? ? ? }


From mturquette at ti.com  Tue Mar 13 22:03:17 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 13 Mar 2012 19:03:17 -0700
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120305092202.GC3261@b20223-02.ap.freescale.net>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120305092202.GC3261@b20223-02.ap.freescale.net>
Message-ID: <CAJOA=zN+pyCZSbJQ+AWyby8y26RfHMjwYU=+8pRDhpCZLofXCQ@mail.gmail.com>

On Mon, Mar 5, 2012 at 1:22 AM, Richard Zhao <richard.zhao at freescale.com> wrote:
> Hi Mike,

Hi Richard,

Sorry for missing this earlier.  I've taken in most of your
suggestions and commented on some of them below.  Any of your feedback
that I cut from this mail was taken in as a fix in v7 :-)

> On Sat, Mar 03, 2012 at 12:29:00AM -0800, Mike Turquette wrote:
>> +/**
>> + * __clk_round_rate - round the given rate for a clk
>> + * @clk: round the rate of this clock
>> + *
>> + * Caller must hold prepare_lock. ?Useful for clk_ops such as .set_rate
>> + */
>> +unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
>> +{
>> + ? ? if (!clk && !clk->ops->round_rate)
> be ? ? ? ? ? ? ? || ?

This is fixed in v7 by a refactor of how clk_round_rate and
__clk_round_rate work.

>> +long clk_round_rate(struct clk *clk, unsigned long rate)
>> +{
>> + ? ? unsigned long ret = rate;
>> +
>> + ? ? mutex_lock(&prepare_lock);
>> + ? ? if (clk && clk->ops->round_rate)
>> + ? ? ? ? ? ? ret = __clk_round_rate(clk, rate);
>> + ? ? mutex_unlock(&prepare_lock);
>> +
>> + ? ? return ret;
> If clk is NULL, clk_round_rate and __clk_round_rate return different
> values. Do you mean it?

This also is fixed in v7 by a refactor of how clk_round_rate and
__clk_round_rate work.

>> +static int __clk_speculate_rates(struct clk *clk, unsigned long parent_rate)
>> +{
>> + ? ? struct hlist_node *tmp;
>> + ? ? struct clk *child;
>> + ? ? unsigned long new_rate;
>> + ? ? int ret = NOTIFY_DONE;
>> +
>> + ? ? if (!clk->ops->recalc_rate)
>> + ? ? ? ? ? ? goto out;
> When recalc_rate is NULL, it's possible for it and its children to have
> notifier too.

Fixed by assuming parent rate without .recalc_rate callback.  This
mirrors __clk_recalc_rates.

>> +
>> + ? ? new_rate = clk->ops->recalc_rate(clk->hw, parent_rate);
>> +
>> + ? ? /* abort the rate change if a driver returns NOTIFY_BAD */
>> + ? ? if (clk->notifier_count)
>> + ? ? ? ? ? ? ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
>> +
>> + ? ? if (ret == NOTIFY_BAD)
>> + ? ? ? ? ? ? goto out;
>> +
>> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node) {
>> + ? ? ? ? ? ? ret = __clk_speculate_rates(child, new_rate);
>> + ? ? ? ? ? ? if (ret == NOTIFY_BAD)
>> + ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? }
> Tell the notifier that already receive PRE_RATE_CHANGE abort?

All of this stuff might change due to existing thread with Sascha on
how clk_set_rate should propagate parent rate changes.  But for
completeness sake, a single ABORT goes out at the end of clk_set_rate
in this implementation, so there isn't a problem here.

>> +static struct clk *__clk_set_rate(struct clk *clk, unsigned long rate)
>> +{
>> + ? ? struct clk *fail_clk = NULL;
>> + ? ? int ret = NOTIFY_DONE;
>> + ? ? unsigned long old_rate = clk->rate;
>> + ? ? unsigned long new_rate;
>> + ? ? unsigned long parent_old_rate;
>> + ? ? unsigned long parent_new_rate = 0;
>> + ? ? struct clk *child;
>> + ? ? struct hlist_node *tmp;
>> +
>> + ? ? /* bail early if we can't change rate while clk is enabled */
>> + ? ? if ((clk->flags & CLK_SET_RATE_GATE) && clk->enable_count)
>> + ? ? ? ? ? ? return clk;
>> +
>> + ? ? /* find the new rate and see if parent rate should change too */
>> + ? ? WARN_ON(!clk->ops->round_rate);
>> +
>> + ? ? new_rate = clk->ops->round_rate(clk->hw, rate, &parent_new_rate);
>> +
>> + ? ? /* NOTE: pre-rate change notifications will stack */
>> + ? ? if (clk->notifier_count)
>> + ? ? ? ? ? ? ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
>
> if ((clk->flags & CLK_SET_RATE_PARENT) && parent_new_rate)
> ? ? ? ?dowstream notify from parent clk?

The pre-rate change notifiers stack; also no problem here.

>> +
>> + ? ? if (ret == NOTIFY_BAD)
>> + ? ? ? ? ? ? return clk;
>> +
>> + ? ? /* speculate rate changes down the tree */
>> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node) {
>> + ? ? ? ? ? ? ret = __clk_speculate_rates(child, new_rate);
>> + ? ? ? ? ? ? if (ret == NOTIFY_BAD)
> roll back?

Similar to the above.  The post-rate change notifiers are sent out
once from the top of the subtree in __clk_set_rate; no problem here.

>> + ? ? ? ? ? ? ? ? ? ? return clk;
>> + ? ? }
>> +
>> + ? ? /* change the rate of this clk */
>> + ? ? if (clk->ops->set_rate)
> If set_rate is NULL, it can fail at the beginning of this function.

We don't want to fail.  In the conditional block below we allow for
propagating the rate request up to the parent.  This would allow for a
gate clock at the bottom of the tree to have clk_set_rate called
against it, even though its hardware doesn't support it, and it will
propagate the request up the tree until it finds a clock that can
adjust the rate.  This feature is very desirable for driver folks who
do not want to know about the tree topology in their driver beyond the
clocks needed by their device.

>> + ? ? ? ? ? ? ret = clk->ops->set_rate(clk->hw, new_rate);
>> +
>> + ? ? if (ret == NOTIFY_BAD)
> you mean to check set_rate fail? Notify ABORT_RATE_CHANGE?

As stated, this happens once in clk_set_rate.

>> + ? ? ? ? ? ? return clk;
>> +
>> + ? ? /*
>> + ? ? ?* change the rate of the parent clk if necessary
>> + ? ? ?*
>> + ? ? ?* hitting the nested 'if' path implies we have hit a .set_rate
>> + ? ? ?* failure somewhere upstream while propagating __clk_set_rate
>> + ? ? ?* up the clk tree. ?roll back the clk rates one by one and
>> + ? ? ?* return the pointer to the clk that failed. ?clk_set_rate will
>> + ? ? ?* use the pointer to propagate a rate-change abort notifier
>> + ? ? ?* from the "highest" point.
>> + ? ? ?*/
>> + ? ? if ((clk->flags & CLK_SET_RATE_PARENT) && parent_new_rate) {
>> + ? ? ? ? ? ? parent_old_rate = clk->parent->rate;
>> + ? ? ? ? ? ? fail_clk = __clk_set_rate(clk->parent, parent_new_rate);
>> +
>> + ? ? ? ? ? ? /* roll back changes if parent rate change failed */
>> + ? ? ? ? ? ? if (fail_clk) {
>> + ? ? ? ? ? ? ? ? ? ? pr_warn("%s: failed to set parent %s rate to %lu\n",
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __func__, fail_clk->name,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? parent_new_rate);
>> +
>> + ? ? ? ? ? ? ? ? ? ? /*
>> + ? ? ? ? ? ? ? ? ? ? ?* Send PRE_RATE_CHANGE notifiers down the tree
>> + ? ? ? ? ? ? ? ? ? ? ?* again, since we're rolling back the rate
>> + ? ? ? ? ? ? ? ? ? ? ?* changes due to the abort.
>> + ? ? ? ? ? ? ? ? ? ? ?*
>> + ? ? ? ? ? ? ? ? ? ? ?* Ignore any NOTIFY_BAD's since this *is* the
>> + ? ? ? ? ? ? ? ? ? ? ?* exception handler.
>> + ? ? ? ? ? ? ? ? ? ? ?*
>> + ? ? ? ? ? ? ? ? ? ? ?* NOTE: pre-rate change notifications will stack
>> + ? ? ? ? ? ? ? ? ? ? ?*/
>> + ? ? ? ? ? ? ? ? ? ? __clk_speculate_rates(clk, clk->parent->rate);
> IMHO, driver can not be happy to receive multiple PRE_RATE_CHANGE.
> Notify ABORT_RATE_CHANGE?

This is getting looked at again in the v6 thread :-)

>> +int clk_set_rate(struct clk *clk, unsigned long rate)
>> +{
>> + ? ? struct clk *fail_clk;
>> + ? ? int ret = 0;
>> +
>> + ? ? /* prevent racing with updates to the clock topology */
>> + ? ? mutex_lock(&prepare_lock);
>> +
>> + ? ? /* bail early if nothing to do */
>> + ? ? if (rate == clk->rate)
>> + ? ? ? ? ? ? goto out;
>> +
>> + ? ? fail_clk = __clk_set_rate(clk, rate);
>> + ? ? if (fail_clk) {
>> + ? ? ? ? ? ? pr_warn("%s: failed to set %s rate\n", __func__,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? fail_clk->name);
>> + ? ? ? ? ? ? __clk_recalc_rates(clk, ABORT_RATE_CHANGE);
> It might need to begin from parent clk. move it to __clk_set_rate?

That should be __clk_recalc_rates(fail_clk, ABORT_RATE_CHANGE), which
is the parent clk.  Thanks for catching that.

>> +void __clk_init(struct device *dev, struct clk *clk)
>> +{
...
>> + ? ? /*
>> + ? ? ?* walk the list of orphan clocks and reparent any that are children of
>> + ? ? ?* this clock
>> + ? ? ?*/
>> + ? ? hlist_for_each_entry(orphan, tmp, &clk_orphan_list, child_node)
>> + ? ? ? ? ? ? __clk_reparent(orphan, __clk_init_parent(orphan));
> check whether orphan->parent is the value of ?__clk_init_parent(orphan)
> before reparent?

Good point.  I cleaned this up a bit to only check orphan's parents
against the clock being registered.  I can't think of any reason why
that wouldn't be adequate.

>> +int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
>> +{
>> + ? ? struct clk_notifier *cn;
>> + ? ? int ret = -ENOMEM;
>> +
>> + ? ? if (!clk || !nb)
>> + ? ? ? ? ? ? return -EINVAL;
>> +
>> + ? ? mutex_lock(&prepare_lock);
>> +
>> + ? ? /* search the list of notifiers for this clk */
>> + ? ? list_for_each_entry(cn, &clk_notifier_list, node)
>> + ? ? ? ? ? ? if (cn->clk == clk)
>> + ? ? ? ? ? ? ? ? ? ? break;
>> +
>> + ? ? /* if clk wasn't in the notifier list, allocate new clk_notifier */
>> + ? ? if (cn->clk != clk) {
>> + ? ? ? ? ? ? cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
>> + ? ? ? ? ? ? if (!cn)
>> + ? ? ? ? ? ? ? ? ? ? goto out;
>> +
>> + ? ? ? ? ? ? cn->clk = clk;
>> + ? ? ? ? ? ? srcu_init_notifier_head(&cn->notifier_head);
>> +
>> + ? ? ? ? ? ? list_add(&cn->node, &clk_notifier_list);
>> + ? ? }
> why not embedd notifier_head to struct clk?

It is assumed that the vast majority of clocks will not have drivers
subscribed to their notifiers.  This saves space over having the
notifier_head in every single struct clk.

Thanks for the great review.

Mike

> Thanks
> Richard
>


From arjan at linux.intel.com  Tue Mar 13 22:04:49 2012
From: arjan at linux.intel.com (Arjan van de Ven)
Date: Tue, 13 Mar 2012 19:04:49 -0700
Subject: [PATCH 0/3] coupled cpuidle state support
In-Reply-To: <8762e8kqi6.fsf@ti.com>
References: <1324426147-16735-1-git-send-email-ccross@android.com>
 <4F1929E9.7070707@linaro.org> <8762e8kqi6.fsf@ti.com>
Message-ID: <4F5FFCC1.2030702@linux.intel.com>

On 3/13/2012 4:52 PM, Kevin Hilman wrote:
> Checking the ready_count seemed like an easy way to do this, but did you
> have any other mechanisms in mind for CPUs to communicate that they've
> exited/aborted?

this indeed is the tricky part (which I warned about earlier);
I've spent quite a lot of time (weeks) to get this provably working for
an Intel system with similar requirements... and it's extremely unfunny,
and needed firmware support to close some of the race conditions.

I sure hope that hardware with these requirements is on the way out...
it's not very OS friendly.



From mturquette at ti.com  Tue Mar 13 22:10:59 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 13 Mar 2012 19:10:59 -0700
Subject: [PATCH 1/7] clk: fix orphan list iterator to be safe
In-Reply-To: <1331680947-29861-2-git-send-email-robherring2@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
 <1331680947-29861-2-git-send-email-robherring2@gmail.com>
Message-ID: <CAJOA=zMRnnQmSzOf_Vtvk_1tVooXoKD0oeKeyFWRzLkneRmKiA@mail.gmail.com>

On Tue, Mar 13, 2012 at 4:22 PM, Rob Herring <robherring2 at gmail.com> wrote:
> From: Rob Herring <rob.herring at calxeda.com>
>
> __clk_reparent can remove orphans, so the list iterator needs to be the
> safe from removal version.
>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>

Thanks Rob.  I've taken this in for the next series.

Regards,
Mike

> ---
> ?drivers/clk/clk.c | ? ?4 ++--
> ?1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index c7c3bc5..802eda4 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1172,7 +1172,7 @@ void __clk_init(struct device *dev, struct clk *clk)
> ?{
> ? ? ? ?int i;
> ? ? ? ?struct clk *orphan;
> - ? ? ? struct hlist_node *tmp;
> + ? ? ? struct hlist_node *tmp, *tmp2;
>
> ? ? ? ?if (!clk)
> ? ? ? ? ? ? ? ?return;
> @@ -1246,7 +1246,7 @@ void __clk_init(struct device *dev, struct clk *clk)
> ? ? ? ? * walk the list of orphan clocks and reparent any that are children of
> ? ? ? ? * this clock
> ? ? ? ? */
> - ? ? ? hlist_for_each_entry(orphan, tmp, &clk_orphan_list, child_node)
> + ? ? ? hlist_for_each_entry_safe(orphan, tmp, tmp2, &clk_orphan_list, child_node)
> ? ? ? ? ? ? ? ?__clk_reparent(orphan, __clk_init_parent(orphan));
>
> ? ? ? ?/*
> --
> 1.7.5.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From b39297 at freescale.com  Tue Mar 13 22:10:54 2012
From: b39297 at freescale.com (Wu Guoxing)
Date: Wed, 14 Mar 2012 10:10:54 +0800
Subject: [PATCH v8] ARM : mx35: 3ds-board: add framebuffer device
Message-ID: <1331691054-6442-1-git-send-email-b39297@freescale.com>

From: wu guoxing <b39297 at freescale.com>

This patch adds framebuffer support for freescale mx35 3ds board

Signed-off-by: Wu Guoxing <b39297 at freescale.com>
---
Changes since v7:
	1. move mc9s08dz60 gpio definitions into mx35 3ds board file
Changes since v6:
	1. use the macro for lcd-enable that added in board_mx35_3ds.h
	2. fold mc9s08dz60_lcd_gpio_get into mx35_3ds_lcd_set_power
Changes since v5:
	1. fixed a typo error in fb_modedb[].
Changes since v4:
	1. fixed a typo error in mx35_3ds_lcd_set_power.
Changes since v3:
	1. use a static variable to save the gpio value instead of find
	the gpiochip every time.
	2. add gpio_request after found the gpio.
Changes since v2:
	1. use gpio_set_value_cansleep instead of gpio_set_value
Changes since v1:
	1. use gpio driver for mc9s08dz60

arch/arm/mach-imx/mach-mx35_3ds.c |  120 +++++++++++++++++++++++++++++++++++++
 1 files changed, 120 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c..e6c64d0 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -40,9 +40,93 @@
 #include <mach/iomux-mx35.h>
 #include <mach/irqs.h>
 #include <mach/3ds_debugboard.h>
+#include <video/platform_lcd.h>
 
 #include "devices-imx35.h"
 
+#define GPIO_MC9S08DZ60_GPS_ENABLE 0
+#define GPIO_MC9S08DZ60_HDD_ENABLE 4
+#define GPIO_MC9S08DZ60_WIFI_ENABLE 5
+#define GPIO_MC9S08DZ60_LCD_ENABLE 6
+#define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8
+
+static const struct fb_videomode fb_modedb[] = {
+	{
+		 /* 800x480 @ 55 Hz */
+		.name = "Ceramate-CLAA070VC01",
+		.refresh = 55,
+		.xres = 800,
+		.yres = 480,
+		.pixclock = 40000,
+		.left_margin = 40,
+		.right_margin = 40,
+		.upper_margin = 5,
+		.lower_margin = 5,
+		.hsync_len = 20,
+		.vsync_len = 10,
+		.sync = FB_SYNC_OE_ACT_HIGH,
+		.vmode = FB_VMODE_NONINTERLACED,
+		.flag = 0,
+	 },
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+	.irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+	.name = "Ceramate-CLAA070VC01",
+	.mode = fb_modedb,
+	.num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static struct i2c_board_info __initdata i2c_devices_3ds[] = {
+	{
+		I2C_BOARD_INFO("mc9s08dz60", 0x69),
+	},
+};
+
+static int lcd_power_gpio = -ENXIO;
+
+static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
+						     void *data)
+{
+	return !strcmp(chip->label, data);
+}
+
+static void mx35_3ds_lcd_set_power(
+				struct plat_lcd_data *pd, unsigned int power)
+{
+	struct gpio_chip *chip;
+
+	if (!gpio_is_valid(lcd_power_gpio)) {
+		chip = gpiochip_find(
+				"mc9s08dz60", mc9s08dz60_gpiochip_match);
+		if (chip) {
+			lcd_power_gpio =
+				chip->base + GPIO_MC9S08DZ60_LCD_ENABLE;
+			if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
+				pr_err("error: gpio already requested!\n");
+				lcd_power_gpio = -ENXIO;
+			}
+		} else {
+			pr_err("error: didn't find mc9s08dz60 gpio chip\n");
+		}
+	}
+
+	if (gpio_is_valid(lcd_power_gpio))
+		gpio_set_value_cansleep(lcd_power_gpio, power);
+}
+
+static struct plat_lcd_data mx35_3ds_lcd_data = {
+	.set_power = mx35_3ds_lcd_set_power,
+};
+
+static struct platform_device mx35_3ds_lcd = {
+	.name = "platform-lcd",
+	.dev.platform_data = &mx35_3ds_lcd_data,
+};
+
 #define EXPIO_PARENT_INT	gpio_to_irq(IMX_GPIO_NR(1, 1))
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -120,6 +204,32 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
 	/* I2C1 */
 	MX35_PAD_I2C1_CLK__I2C1_SCL,
 	MX35_PAD_I2C1_DAT__I2C1_SDA,
+	/* Display */
+	MX35_PAD_LD0__IPU_DISPB_DAT_0,
+	MX35_PAD_LD1__IPU_DISPB_DAT_1,
+	MX35_PAD_LD2__IPU_DISPB_DAT_2,
+	MX35_PAD_LD3__IPU_DISPB_DAT_3,
+	MX35_PAD_LD4__IPU_DISPB_DAT_4,
+	MX35_PAD_LD5__IPU_DISPB_DAT_5,
+	MX35_PAD_LD6__IPU_DISPB_DAT_6,
+	MX35_PAD_LD7__IPU_DISPB_DAT_7,
+	MX35_PAD_LD8__IPU_DISPB_DAT_8,
+	MX35_PAD_LD9__IPU_DISPB_DAT_9,
+	MX35_PAD_LD10__IPU_DISPB_DAT_10,
+	MX35_PAD_LD11__IPU_DISPB_DAT_11,
+	MX35_PAD_LD12__IPU_DISPB_DAT_12,
+	MX35_PAD_LD13__IPU_DISPB_DAT_13,
+	MX35_PAD_LD14__IPU_DISPB_DAT_14,
+	MX35_PAD_LD15__IPU_DISPB_DAT_15,
+	MX35_PAD_LD16__IPU_DISPB_DAT_16,
+	MX35_PAD_LD17__IPU_DISPB_DAT_17,
+	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
+	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
 };
 
 static int mx35_3ds_otg_init(struct platform_device *pdev)
@@ -179,6 +289,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
  */
 static void __init mx35_3ds_init(void)
 {
+	struct platform_device *imx35_fb_pdev;
+
 	imx35_soc_init();
 
 	mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
@@ -204,6 +316,14 @@ static void __init mx35_3ds_init(void)
 		pr_warn("Init of the debugboard failed, all "
 				"devices on the debugboard are unusable.\n");
 	imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+
+	i2c_register_board_info(
+		0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
+
+	imx35_add_ipu_core(&mx3_ipu_data);
+	imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
+	mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
+	platform_device_register(&mx35_3ds_lcd);
 }
 
 static void __init mx35pdk_timer_init(void)
-- 
1.7.1




From ccross at android.com  Tue Mar 13 22:21:33 2012
From: ccross at android.com (Colin Cross)
Date: Tue, 13 Mar 2012 19:21:33 -0700
Subject: [PATCH 0/3] coupled cpuidle state support
In-Reply-To: <4F5FFCC1.2030702@linux.intel.com>
References: <1324426147-16735-1-git-send-email-ccross@android.com>
 <4F1929E9.7070707@linaro.org> <8762e8kqi6.fsf@ti.com>
 <4F5FFCC1.2030702@linux.intel.com>
Message-ID: <CAMbhsRSrS-gwu20Ba5=n_LNUwDh3p+5bQPOymGJ9x5O2Fn28kA@mail.gmail.com>

On Tue, Mar 13, 2012 at 7:04 PM, Arjan van de Ven <arjan at linux.intel.com> wrote:
> On 3/13/2012 4:52 PM, Kevin Hilman wrote:
>> Checking the ready_count seemed like an easy way to do this, but did you
>> have any other mechanisms in mind for CPUs to communicate that they've
>> exited/aborted?
>
> this indeed is the tricky part (which I warned about earlier);
> I've spent quite a lot of time (weeks) to get this provably working for
> an Intel system with similar requirements... and it's extremely unfunny,
> and needed firmware support to close some of the race conditions.

As long as you can tell from cpu0 that cpu1 has succesfully entered
the low power state, this should be easy, and the
coupled_cpuidle_parallel_barrier helper should make it even easier.
This series just allows the exact same sequence of transitions used by
hotplug cpufreq governors to happen from the idle thread:

1. cpu0 forces cpu1 offline.  From a wakeup perspective, this is
exactly like hotplug removing cpu1.  Unlike hotplug, the state of cpu1
has to be saved, and the scheduler is not told that the cpu is gone.
Instead of using the IPI signalling that hotplug uses, we call the
same function on both cpus, and one cpu runs the equivalent of
platform_cpu_kill, and the other the equivalent of platform_cpu_die.
Wakeup events that are only targeted at cpu1 will need to be
temporarily migrated to cpu0.
2. If the hotplug is successful, cpu0 goes to a low power state, the
same way it would when the hotplug cpufreq governor had removed cpu1.
3. cpu0 wakes up, because all wakeup events are pointed at it.
4. After restoring its own state, cpu0 brings cpu1 back online,
exactly like hotplug online would, except that the boot vector has to
point to a cpu_resume handler instead of secondary start.

> I sure hope that hardware with these requirements is on the way out...
> it's not very OS friendly.

Even hardware that was designed not not have these requirements
sometimes has bugs that require this kind of sequencing.  OMAP4430
should theoretically support idle without sequencing, but OMAP4460
introduced a ROM code bug that requires sequencing again (turning on
cpu1 corrupts the interrupt controller, so cpu0 has to be waiting with
interrupts off to run a workaround whenever cpu1 turns on).

Out of curiosity, what Intel hardware needs this?


From paul.liu at linaro.org  Tue Mar 13 22:29:12 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Wed, 14 Mar 2012 10:29:12 +0800
Subject: [PATCH v13] Regulator: Add Anatop regulator driver
Message-ID: <1331692152-9256-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.

Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
Reviewed-by: Axel Lin <axel.lin at gmail.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Liam Girdwood <lrg at ti.com>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 drivers/regulator/Kconfig            |    8 +
 drivers/regulator/Makefile           |    1 +
 drivers/regulator/anatop-regulator.c |  241 ++++++++++++++++++++++++++++++++++
 3 files changed, 250 insertions(+), 0 deletions(-)
 create mode 100644 drivers/regulator/anatop-regulator.c

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index c733df5..a229de9 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -102,6 +102,14 @@ config REGULATOR_DA9052
 	  This driver supports the voltage regulators of DA9052-BC and
 	  DA9053-AA/Bx PMIC.
 
+config REGULATOR_ANATOP
+	tristate "Freescale i.MX on-chip ANATOP LDO regulators"
+	depends on MFD_ANATOP
+	help
+	  Say y here to support Freescale i.MX on-chip ANATOP LDOs
+	  regulators. It is recommended that this option be
+	  enabled on i.MX6 platform.
+
 config REGULATOR_MC13XXX_CORE
 	tristate
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index cf0934b..ab06474 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_REGULATOR_AAT2870) += aat2870-regulator.o
 obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
 obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
 obj-$(CONFIG_REGULATOR_AD5398) += ad5398.o
+obj-$(CONFIG_REGULATOR_ANATOP) += anatop-regulator.o
 obj-$(CONFIG_REGULATOR_BQ24022) += bq24022.o
 obj-$(CONFIG_REGULATOR_DA903X)	+= da903x.o
 obj-$(CONFIG_REGULATOR_DA9052)	+= da9052-regulator.o
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
new file mode 100644
index 0000000..17499a5
--- /dev/null
+++ b/drivers/regulator/anatop-regulator.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+
+struct anatop_regulator {
+	const char *name;
+	u32 control_reg;
+	struct anatop *mfd;
+	int vol_bit_shift;
+	int vol_bit_width;
+	int min_bit_val;
+	int min_voltage;
+	int max_voltage;
+	struct regulator_desc rdesc;
+	struct regulator_init_data *initdata;
+};
+
+static int anatop_set_voltage(struct regulator_dev *reg, int min_uV,
+				  int max_uV, unsigned *selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	u32 val, sel;
+	int uv;
+
+	uv = min_uV;
+	dev_dbg(&reg->dev, "%s: uv %d, min %d, max %d\n", __func__,
+		uv, anatop_reg->min_voltage,
+		anatop_reg->max_voltage);
+
+	if (uv < anatop_reg->min_voltage) {
+		if (max_uV > anatop_reg->min_voltage)
+			uv = anatop_reg->min_voltage;
+		else
+			return -EINVAL;
+	}
+
+	if (!anatop_reg->control_reg)
+		return -ENOTSUPP;
+
+	sel = DIV_ROUND_UP(uv - anatop_reg->min_voltage, 25000);
+	if (sel * 25000 + anatop_reg->min_voltage > anatop_reg->max_voltage)
+		return -EINVAL;
+	val = anatop_reg->min_bit_val + sel;
+	*selector = sel;
+	dev_dbg(&reg->dev, "%s: calculated val %d\n", __func__, val);
+	anatop_set_bits(anatop_reg->mfd,
+			anatop_reg->control_reg,
+			anatop_reg->vol_bit_shift,
+			anatop_reg->vol_bit_width,
+			val);
+
+	return 0;
+}
+
+static int anatop_get_voltage_sel(struct regulator_dev *reg)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	u32 val;
+
+	if (!anatop_reg->control_reg)
+		return -ENOTSUPP;
+
+	val = anatop_get_bits(anatop_reg->mfd,
+			      anatop_reg->control_reg,
+			      anatop_reg->vol_bit_shift,
+			      anatop_reg->vol_bit_width);
+
+	return val - anatop_reg->min_bit_val;
+}
+
+static int anatop_list_voltage(struct regulator_dev *reg, unsigned selector)
+{
+	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+	int uv;
+
+	uv = anatop_reg->min_voltage + selector * 25000;
+	dev_dbg(&reg->dev, "vddio = %d, selector = %u\n", uv, selector);
+
+	return uv;
+}
+
+static struct regulator_ops anatop_rops = {
+	.set_voltage     = anatop_set_voltage,
+	.get_voltage_sel = anatop_get_voltage_sel,
+	.list_voltage    = anatop_list_voltage,
+};
+
+static int __devinit anatop_regulator_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct regulator_desc *rdesc;
+	struct regulator_dev *rdev;
+	struct anatop_regulator *sreg;
+	struct regulator_init_data *initdata;
+	struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
+	int ret = 0;
+
+	initdata = of_get_regulator_init_data(dev, np);
+	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
+	if (!sreg)
+		return -ENOMEM;
+	sreg->initdata = initdata;
+	sreg->name = kstrdup(of_get_property(np, "regulator-name", NULL),
+			     GFP_KERNEL);
+	rdesc = &sreg->rdesc;
+	memset(rdesc, 0, sizeof(*rdesc));
+	rdesc->name = sreg->name;
+	rdesc->ops = &anatop_rops;
+	rdesc->type = REGULATOR_VOLTAGE;
+	rdesc->owner = THIS_MODULE;
+	sreg->mfd = anatopmfd;
+	ret = of_property_read_u32(np, "reg", &sreg->control_reg);
+	if (ret) {
+		dev_err(dev, "no reg property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-vol-bit-width",
+				   &sreg->vol_bit_width);
+	if (ret) {
+		dev_err(dev, "no anatop-vol-bit-width property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
+				   &sreg->vol_bit_shift);
+	if (ret) {
+		dev_err(dev, "no anatop-vol-bit-shift property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-min-bit-val",
+				   &sreg->min_bit_val);
+	if (ret) {
+		dev_err(dev, "no anatop-min-bit-val property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-min-voltage",
+				   &sreg->min_voltage);
+	if (ret) {
+		dev_err(dev, "no anatop-min-voltage property set\n");
+		goto anatop_probe_end;
+	}
+	ret = of_property_read_u32(np, "anatop-max-voltage",
+				   &sreg->max_voltage);
+	if (ret) {
+		dev_err(dev, "no anatop-max-voltage property set\n");
+		goto anatop_probe_end;
+	}
+
+	rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage)
+		/ 25000 + 1;
+
+	/* register regulator */
+	rdev = regulator_register(rdesc, dev,
+				  initdata, sreg, pdev->dev.of_node);
+	if (IS_ERR(rdev)) {
+		dev_err(dev, "failed to register %s\n",
+			rdesc->name);
+		ret = PTR_ERR(rdev);
+		goto anatop_probe_end;
+	}
+
+	platform_set_drvdata(pdev, rdev);
+
+anatop_probe_end:
+	if (ret)
+		kfree(sreg->name);
+
+	return ret;
+}
+
+static int __devexit anatop_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+	struct anatop_regulator *sreg = rdev_get_drvdata(rdev);
+	const char *name = sreg->name;
+
+	regulator_unregister(rdev);
+	kfree(name);
+
+	return 0;
+}
+
+static struct of_device_id __devinitdata of_anatop_regulator_match_tbl[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ /* end */ }
+};
+
+static struct platform_driver anatop_regulator = {
+	.driver = {
+		.name	= "anatop_regulator",
+		.owner  = THIS_MODULE,
+		.of_match_table = of_anatop_regulator_match_tbl,
+	},
+	.probe	= anatop_regulator_probe,
+	.remove	= anatop_regulator_remove,
+};
+
+static int __init anatop_regulator_init(void)
+{
+	return platform_driver_register(&anatop_regulator);
+}
+postcore_initcall(anatop_regulator_init);
+
+static void __exit anatop_regulator_exit(void)
+{
+	platform_driver_unregister(&anatop_regulator);
+}
+module_exit(anatop_regulator_exit);
+
+MODULE_AUTHOR("Nancy Chen <Nancy.Chen at freescale.com>, "
+	      "Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP Regulator driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.1



From robherring2 at gmail.com  Tue Mar 13 22:34:19 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 13 Mar 2012 21:34:19 -0500
Subject: [GIT PULL] mach/io.h cleanup fixes
Message-ID: <4F6003AB.2030005@gmail.com>

Arnd, Olof,

Please pull these fixes for mach/io.h cleanup series. They apply on top
of my previous pull request.

Cheers,
Rob

The following changes since commit 5621caac1d9514b568f986b55ce5494b1d119d40:

  ARM: kill off __mem_pci (2012-03-06 21:34:45 -0600)

are available in the git repository at:
  git://sources.calxeda.com/kernel/linux.git io-cleanup-for-3.4

Rob Herring (4):
      ARM: fix ioremap/iounmap for !CONFIG_MMU
      ARM: iop13xx: fix missing declaration of iop13xx_init_early
      ARM: create a common IOMEM definition
      ARM: __io abuse cleanup

 arch/arm/include/asm/assembler.h                |    2 ++
 arch/arm/include/asm/io.h                       |    2 ++
 arch/arm/kernel/debug.S                         |    1 +
 arch/arm/kernel/entry-armv.S                    |    1 +
 arch/arm/mach-cns3xxx/core.c                    |    8 ++++----
 arch/arm/mach-cns3xxx/devices.c                 |    2 +-
 arch/arm/mach-davinci/include/mach/hardware.h   |    6 ------
 arch/arm/mach-davinci/include/mach/uncompress.h |    2 ++
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |    9 ---------
 arch/arm/mach-iop13xx/include/mach/iop13xx.h    |    1 +
 arch/arm/mach-mmp/include/mach/addr-map.h       |    6 ------
 arch/arm/mach-msm/include/mach/msm_iomap-7x00.h |    6 ------
 arch/arm/mach-msm/include/mach/msm_iomap.h      |    6 ------
 arch/arm/mach-mxs/include/mach/hardware.h       |    6 ------
 arch/arm/mach-netx/generic.c                    |    2 +-
 arch/arm/mach-netx/include/mach/hardware.h      |    2 +-
 arch/arm/mach-netx/include/mach/netx-regs.h     |   16 ++++++++--------
 arch/arm/mach-omap1/ams-delta-fiq-handler.S     |    1 +
 arch/arm/mach-omap1/iomap.h                     |    6 ------
 arch/arm/mach-omap2/clock3xxx_data.c            |    1 +
 arch/arm/mach-omap2/clock44xx_data.c            |    1 +
 arch/arm/mach-omap2/iomap.h                     |    6 ------
 arch/arm/mach-realview/include/mach/hardware.h  |    2 +-
 arch/arm/mach-rpc/include/mach/hardware.h       |    6 ------
 arch/arm/mach-shmobile/board-ag5evm.c           |    2 +-
 arch/arm/mach-shmobile/board-bonito.c           |    2 +-
 arch/arm/mach-shmobile/board-kota2.c            |    2 +-
 arch/arm/mach-shmobile/intc-r8a7779.c           |    4 ++--
 arch/arm/mach-shmobile/intc-sh73a0.c            |    4 ++--
 arch/arm/mach-shmobile/smp-r8a7779.c            |    4 ++--
 arch/arm/mach-shmobile/smp-sh73a0.c             |   20 ++++++++++----------
 arch/arm/mach-spear3xx/clock.c                  |    1 +
 arch/arm/mach-spear6xx/clock.c                  |    1 +
 arch/arm/mach-tegra/include/mach/iomap.h        |    6 ------
 arch/arm/mach-u300/include/mach/u300-regs.h     |    6 ------
 arch/arm/mach-ux500/include/mach/hardware.h     |    2 +-
 arch/arm/mm/nommu.c                             |    8 ++++++--
 arch/arm/plat-mxc/include/mach/hardware.h       |    6 ------
 arch/arm/plat-omap/include/plat/hardware.h      |    6 ------
 arch/arm/plat-omap/include/plat/usb.h           |    1 -
 arch/arm/plat-spear/include/plat/hardware.h     |    6 ------
 41 files changed, 56 insertions(+), 126 deletions(-)


From B04825 at freescale.com  Tue Mar 13 22:57:00 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Wed, 14 Mar 2012 02:57:00 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120313234638.GY3177@opensource.wolfsonmicro.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
Message-ID: <4F6008FA.3040805@freescale.com>

Mark Brown wrote:

> With this card those would just be separate CODECs.  This is a binding
> for a simple card.

But that is insufficient for the SSI driver, which is expected to handle 
multiple SSIs.  If you're going to document a binding for the SSI driver, 
then you need to document how to handle multiple SSIs.

> The biggest improvement is that the SoC binding knows nothing about the
> card binding at all, cards are completely separate and are free to
> define any binding they choose using any number of on-SoC and off-SoC
> devices.

Ok, I don't understand that at all.

I also don't understand why you insist on perverting my driver to support 
two incompatible bindings, especially since I still haven't heard an 
explanation as to what's wrong with the binding that I defined.

-- 
Timur Tabi
Linux kernel developer at Freescale


From festevam at gmail.com  Tue Mar 13 23:24:37 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 14 Mar 2012 00:24:37 -0300
Subject: Want to Get Suggestion for MX28 USB Submisson
In-Reply-To: <201202100447.14248.marek.vasut@gmail.com>
References: <35AB98346D25394A9354ED89C4D76587225CFF@039-SN1MPN1-002.039d.mgd.msft.net>
 <201202041117.48190.marek.vasut@gmail.com>
 <F281D0F91ED19E4D8E63A7504E8A6498033336@039-SN2MPN1-021.039d.mgd.msft.net>
 <201202100447.14248.marek.vasut@gmail.com>
Message-ID: <CAOMZO5C3Y3kP5k_CKkCVMVdDem2T82g6F3uL=8GCVfNKHpdymA@mail.gmail.com>

Hi Peter,

On Fri, Feb 10, 2012 at 1:47 AM, Marek Vasut <marek.vasut at gmail.com> wrote:

> Oh, so you're still working on it. All right then, I'll now dive into the IIO
> LRADC driver and let you handle this.

Do you plan to re-submit the mxs usb driver?

Regards,

Fabio Estevam


From olof at lixom.net  Tue Mar 13 23:24:57 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 20:24:57 -0700
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <1331500100-31351-4-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-4-git-send-email-robherring2@gmail.com>
Message-ID: <CAOesGMjwnAHNBHC7SR0qkFO0yiZ3kAEPhQwfTp00pHh6W4QsMQ@mail.gmail.com>

On Sun, Mar 11, 2012 at 2:08 PM, Rob Herring <robherring2 at gmail.com> wrote:
> From: Rob Herring <rob.herring at calxeda.com>
>
> Several platforms create IOMEM defines for casting to 'void __iomem *',
> and other platforms are incorrectly using __io() macro for the same
> purpose. This creates a common definition and removes all the platform
> specific versions. Rather than try to make linux/io.h and asm/io.h
> assembly safe, the assembly version of IOMEM is moved into
> asm/assembler.h.
>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Sekhar Nori <nsekhar at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <rmallon at gmail.com>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
> Cc: David Brown <davidb at codeaurora.org>
> Cc: Daniel Walker <dwalker at fifo99.com>
> Cc: Bryan Huntsman <bryanh at codeaurora.org>
> Cc: Sascha Hauer <kernel at pengutronix.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> Cc: Rajeev Kumar <rajeev-dlh.kumar at st.com>
> Cc: Colin Cross <ccross at android.com>
> Cc: Olof Johansson <olof at lixom.net>
> Cc: Stephen Warren <swarren at nvidia.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>

Acked-by: Olof Johansson <olof at lixom.net>  Tegra portions


From B29397 at freescale.com  Tue Mar 13 23:30:26 2012
From: B29397 at freescale.com (Chen Peter-B29397)
Date: Wed, 14 Mar 2012 03:30:26 +0000
Subject: Want to Get Suggestion for MX28 USB Submisson
In-Reply-To: <CAOMZO5C3Y3kP5k_CKkCVMVdDem2T82g6F3uL=8GCVfNKHpdymA@mail.gmail.com>
References: <35AB98346D25394A9354ED89C4D76587225CFF@039-SN1MPN1-002.039d.mgd.msft.net>
 <201202041117.48190.marek.vasut@gmail.com>
 <F281D0F91ED19E4D8E63A7504E8A6498033336@039-SN2MPN1-021.039d.mgd.msft.net>
 <201202100447.14248.marek.vasut@gmail.com>
 <CAOMZO5C3Y3kP5k_CKkCVMVdDem2T82g6F3uL=8GCVfNKHpdymA@mail.gmail.com>
Message-ID: <F281D0F91ED19E4D8E63A7504E8A6498093839@039-SN2MPN1-021.039d.mgd.msft.net>

 
> 
> Hi Peter,
> 
> On Fri, Feb 10, 2012 at 1:47 AM, Marek Vasut <marek.vasut at gmail.com>
> wrote:
> 
> > Oh, so you're still working on it. All right then, I'll now dive into
> the IIO
> > LRADC driver and let you handle this.
> 
> Do you plan to re-submit the mxs usb driver?
> 
According to sascha's suggestion, it is better to re-submit after we have
a generic USB PHY Layer in mainline.

Currently, Heikki's split PHY from OTG structure patches have mainlined, 
next step is to submit a generic USB PHY driver.

> Regards,
> 
> Fabio Estevam


From olof at lixom.net  Tue Mar 13 23:42:46 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 20:42:46 -0700
Subject: [PATCH v3 07/12] ARM: EXYNOS: add interrupt definitions for
 EXYNOS5250
In-Reply-To: <1331652643-12626-8-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <1331652643-12626-8-git-send-email-kgene.kim@samsung.com>
Message-ID: <CAOesGMgEg3Pem4ZMCEp341MxSrW7uajZ0wB1YWgQM-k=KSdiXA@mail.gmail.com>

Hi

On Tue, Mar 13, 2012 at 8:30 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> ARM: EXYNOS: irqs.h for exynos4 and exynos5 - WIP
> This patch adds the interrupt definitions for EXYNOS5250 at
> <mach/irqs.h> file. Basically, now it is needed for EXYNOS5250
> interrupt and will be updated for single zImage next time.

Nit for when you stage the branch: Update the commit message a bit, I think?


-Olof


From olof at lixom.net  Tue Mar 13 23:52:03 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 20:52:03 -0700
Subject: [PATCH v3 08/12] ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5
In-Reply-To: <1331652643-12626-9-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <1331652643-12626-9-git-send-email-kgene.kim@samsung.com>
Message-ID: <20120314035203.GA2531@quad.lixom.net>

Hi,

A couple of comments below.


On Tue, Mar 13, 2012 at 08:30:39AM -0700, Kukjin Kim wrote:
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 0b53018..72f21e4 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -777,39 +779,24 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
>  	mask = 0x7 << shift;
>  
>  	spin_lock(&eint_lock);
> -	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
> +	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
>  	ctrl &= ~mask;
>  	ctrl |= newvalue << shift;
> -	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
> +	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
>  	spin_unlock(&eint_lock);
>  
> -	switch (offs) {
> -	case 0 ... 7:
> -		s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
> -		break;
> -	case 8 ... 15:
> -		s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
> -		break;
> -	case 16 ... 23:
> -		s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
> -		break;
> -	case 24 ... 31:
> -		s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
> -		break;
> -	default:
> -		printk(KERN_ERR "No such irq number %d", offs);
> -	}
> +	s3c_gpio_cfgpin(irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));

irq_to_gpio is going away, so it's not a good idea to add it under that name.

Add a local function locally at the top of this file instead. and call
it something else.

> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
> index 80523ca..c09deb6 100644
> --- a/arch/arm/mach-exynos/include/mach/gpio.h
> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
> @@ -146,4 +146,33 @@ enum s5p_gpio_number {
>  #define ARCH_NR_GPIOS		(EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) +	\
>  				 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
>  
> +#include <linux/types.h>
> +#include <linux/err.h>
> +#include <mach/irqs.h>
> +#include <plat/cpu.h>
> +
> +static inline int irq_to_gpio(unsigned int irq)
> +{
> +	if (irq < IRQ_EINT(0))
> +		return -EINVAL;
> +
> +	irq -= IRQ_EINT(0);
> +	if (irq < 8)
> +		return soc_is_exynos5250() ?  EXYNOS5_GPX0(irq) :
> +					 EXYNOS4_GPX0(irq);
> +	irq -= 8;
> +	if (irq < 8)
> +		return soc_is_exynos5250() ?  EXYNOS5_GPX1(irq) :
> +					 EXYNOS4_GPX1(irq);
> +	irq -= 8;
> +	if (irq < 8)
> +		return soc_is_exynos5250() ?  EXYNOS5_GPX2(irq) :
> +					 EXYNOS4_GPX2(irq);
> +	irq -= 8;
> +	if (irq < 8)
> +		return soc_is_exynos5250() ?  EXYNOS5_GPX3(irq) :
> +					 EXYNOS4_GPX3(irq);
> +	return -EINVAL;
> +}

I think this would be cleaner as two small helpers and one check for SoC
version instead.


-Olof


From olof at lixom.net  Tue Mar 13 23:56:55 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 20:56:55 -0700
Subject: [PATCH v3 12/12] ARM: dts: add initial dts file for EXYNOS5250,
 SMDK5250
In-Reply-To: <1331652643-12626-13-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <1331652643-12626-13-git-send-email-kgene.kim@samsung.com>
Message-ID: <20120314035655.GB2531@quad.lixom.net>

On Tue, Mar 13, 2012 at 08:30:43AM -0700, Kukjin Kim wrote:
> This patch adds initial dts file for EXYNOS5250 SoC. This dts
> file is including the SoC specific devices and properties. And
> adds the dts file for SMDK5250 board which uses the EXYNOS5250
> dts file. Its board specific properites will be added later.
> 
> Cc: Thomas Abraham <thomas.abraham at linaro.org>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250-smdk5250.dts |   26 ++
>  arch/arm/boot/dts/exynos5250.dtsi         |  413 +++++++++++++++++++++++++++++
>  2 files changed, 439 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/exynos5250-smdk5250.dts
>  create mode 100644 arch/arm/boot/dts/exynos5250.dtsi
> 
> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> new file mode 100644
> index 0000000..491539a
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
> @@ -0,0 +1,26 @@
> +/*
> + * SAMSUNG SMDK5250 board device tree source
> + *
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/dts-v1/;
> +/include/ "exynos5250.dtsi"
> +
> +/ {
> +	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
> +	compatible = "samsung,smdk5250", "samsung,exynos5250";
> +
> +	memory {
> +		reg = <0x40000000 0x80000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "root=/dev/ram0 rw ramdisk=8192 rootfstype=squashfs initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";

Having these specific bootargs in the include file rarely makes sense, it's
better to have firmware update from the settings in firmware and just have a very
simple fallback here.

In particular initrd is quite custom to hardcode like that.

> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -0,0 +1,413 @@
> +/*
> + * SAMSUNG EXYNOS5250 SoC device tree source
> + *
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
> + * EXYNOS5250 based board files can include this file and provide
> + * values for board specfic bindings.
> + *
> + * Note: This file does not include device nodes for all the controllers in
> + * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
> + * additional nodes can be added to this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	compatible = "samsung,exynos5250";
> +	interrupt-parent = <&gic>;
> +
> +	gic:interrupt-controller at 10490000 {
> +		compatible = "arm,cortex-a9-gic";
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
> +	};
> +
> +	watchdog at 101D0000 {

lowercase hex here and elsewhere in these files, please.

Also, technically no need to specify a unit address (@<foo>) in the device node
name unless you need it to tell more than one entry apart, but it's become
customary to always add them on ARM for some reason.


-Olof


From olof at lixom.net  Tue Mar 13 23:57:28 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 20:57:28 -0700
Subject: [PATCH v3 00/12] ARM: EXYNOS: add support new EXYNOS5250
In-Reply-To: <201203131622.09048.arnd@arndb.de>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <201203131622.09048.arnd@arndb.de>
Message-ID: <20120314035728.GC2531@quad.lixom.net>

On Tue, Mar 13, 2012 at 04:22:08PM +0000, Arnd Bergmann wrote:
> On Tuesday 13 March 2012, Kukjin Kim wrote:
> > 
> > This patch adds support EXYNOS5250 SoC which has two A15 cores
> > can be used on mobile and tablet devices.
> 
> Looks basically ok to me. I've commented on patches 5 and 9 and
> in both cases, I would either like to see the patch get dropped
> or the changeset description expanded to give a good explanation
> why the change is actually needed.

Agree, looks quite reasonable. I had a few nits as well but nothing
major.


Thanks,

-Olof


From olof at lixom.net  Wed Mar 14 00:08:44 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 13 Mar 2012 21:08:44 -0700
Subject: [GIT PULL] mach/io.h cleanup fixes
In-Reply-To: <4F6003AB.2030005@gmail.com>
References: <4F6003AB.2030005@gmail.com>
Message-ID: <CAOesGMg-ybrAEDYZZEx20BZCcuH5pygUEMtOOD1YETkE66BgGA@mail.gmail.com>

Hi,

On Tue, Mar 13, 2012 at 7:34 PM, Rob Herring <robherring2 at gmail.com> wrote:
> Arnd, Olof,
>
> Please pull these fixes for mach/io.h cleanup series. They apply on top
> of my previous pull request.
>
> Cheers,
> Rob
>
> The following changes since commit 5621caac1d9514b568f986b55ce5494b1d119d40:
>
> ?ARM: kill off __mem_pci (2012-03-06 21:34:45 -0600)
>
> are available in the git repository at:
> ?git://sources.calxeda.com/kernel/linux.git io-cleanup-for-3.4

Pulled into next/cleanup2. It had a couple of new conflicts, please
double check arm-soc for-next but they should be alright.


-Olof


From dmitry.torokhov at gmail.com  Wed Mar 14 00:42:05 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Tue, 13 Mar 2012 21:42:05 -0700
Subject: [PATCH v4] Input: keyboard - add device tree bindings for simple
 key matrixes
In-Reply-To: <74CDBE0F657A3D45AFBB94109FB122FF17761F11FF@HQMAIL01.nvidia.com>
References: <1325484557-27695-1-git-send-email-olof@lixom.net>
 <1325626648-9425-1-git-send-email-olof@lixom.net>
 <74CDBE0F657A3D45AFBB94109FB122FF17761F11FF@HQMAIL01.nvidia.com>
Message-ID: <20120314044205.GA3964@core.coreip.homeip.net>

On Tue, Jan 03, 2012 at 02:37:44PM -0800, Stephen Warren wrote:
> Olof Johansson wrote at Tuesday, January 03, 2012 2:37 PM:
> > This adds a simple device tree binding for simple key matrix data and
> > a helper to fill in the platform data.
> > 
> > The implementation is in a shared file outside if drivers/input/keyboard
> > since some drivers in drivers/input/misc might be making use of it
> > as well.
> > 
> > Changes since v3:
> >  * Dropped compatible field in matrix-keymap.txt
> >  * Dropped linux,fn-key
> >  * Dropped linux,fn-keymap optional property but included guideline on
> >    naming convention
> >  * Now passing property name in to the helper function (or will assume
> >    "linux,keymap" if passed NULL)
> 
> > diff --git a/drivers/input/of_keymap.c b/drivers/input/of_keymap.c
> 
> > +struct matrix_keymap_data *
> > +matrix_keyboard_of_fill_keymap(struct device_node *np, char *propname)
> > +{
> ...
> > +	kd = kmalloc(sizeof(*kd), GFP_KERNEL);
> > +	if (!kd)
> > +		return NULL;
> 
> Should that use kzalloc in case struct matrix_keymap_data grows some
> new fields that people will assume are set to zero since the struct
> would usually be in .data? Still, people should probably grep the code
> when making such changes...
> 
> Otherwise,
> 
> Acked-by: Stephen Warren <swarren at nvidia.com>
> 

Applied, thanks everyone.

-- 
Dmitry


From baruch at tkos.co.il  Wed Mar 14 01:02:38 2012
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed, 14 Mar 2012 07:02:38 +0200
Subject: [PATCH v8] ARM : mx35: 3ds-board: add framebuffer device
In-Reply-To: <1331691054-6442-1-git-send-email-b39297@freescale.com>
References: <1331691054-6442-1-git-send-email-b39297@freescale.com>
Message-ID: <20120314050238.GA15933@sapphire.tkos.co.il>

Hi Wu,

On Wed, Mar 14, 2012 at 10:10:54AM +0800, Wu Guoxing wrote:
> From: wu guoxing <b39297 at freescale.com>
> 
> This patch adds framebuffer support for freescale mx35 3ds board
> 
> Signed-off-by: Wu Guoxing <b39297 at freescale.com>
> ---

[snip]

> +static int lcd_power_gpio = -ENXIO;

Since this is only used in mx35_3ds_lcd_set_power() below, can't it be local 
to that routine?

> +
> +static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
> +						     void *data)
> +{
> +	return !strcmp(chip->label, data);
> +}
> +
> +static void mx35_3ds_lcd_set_power(
> +				struct plat_lcd_data *pd, unsigned int power)
> +{
> +	struct gpio_chip *chip;
> +
> +	if (!gpio_is_valid(lcd_power_gpio)) {
> +		chip = gpiochip_find(
> +				"mc9s08dz60", mc9s08dz60_gpiochip_match);
> +		if (chip) {
> +			lcd_power_gpio =
> +				chip->base + GPIO_MC9S08DZ60_LCD_ENABLE;
> +			if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
> +				pr_err("error: gpio already requested!\n");
> +				lcd_power_gpio = -ENXIO;
> +			}
> +		} else {
> +			pr_err("error: didn't find mc9s08dz60 gpio chip\n");
> +		}
> +	}
> +
> +	if (gpio_is_valid(lcd_power_gpio))
> +		gpio_set_value_cansleep(lcd_power_gpio, power);
> +}

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From shawn.guo at linaro.org  Wed Mar 14 01:08:40 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 14 Mar 2012 13:08:40 +0800
Subject: [GIT PULL] imx irq_domain migration
In-Reply-To: <4F3D41D2.5090203@gmail.com>
References: <20120216154941.GB11758@r65073-Latitude-D630>
 <4F3D41D2.5090203@gmail.com>
Message-ID: <20120314050837.GB21337@S2101-09.ap.freescale.net>

On Thu, Feb 16, 2012 at 11:50:10AM -0600, Rob Herring wrote:
> Shawn,
> 
> On 02/16/2012 09:49 AM, Shawn Guo wrote:
> > Hi Rob,
> > 
> > Please pull imx irq_domain support below. It's based on Grant's
> > irqdomain/next today with your generic-chip series applied on top
> > of it.
> 
> You're asking me to pull changes on top of a branch that I don't even
> have as you've rebased my changes. While it would work I don't think
> this is the right flow. Plus there is not really any reason for iMX
> changes to go thru me.
> 
> Either Grant needs to stabilize his branch so you and I can send him
> pull requests or he can pull in our changes and rebase them as he
> rebases. I already asked him to do just that with my 1 patch others are
> dependent on.
> 
Hi Grant,

Would you consider to take this request after you take Rob's
generic_irq one?

-- 
Regards,
Shawn


From thomas.abraham at linaro.org  Wed Mar 14 01:27:32 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 14 Mar 2012 10:57:32 +0530
Subject: [PATCH v3 07/12] ARM: EXYNOS: add interrupt definitions for
 EXYNOS5250
In-Reply-To: <1331652643-12626-8-git-send-email-kgene.kim@samsung.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <1331652643-12626-8-git-send-email-kgene.kim@samsung.com>
Message-ID: <CAJuYYwTFEV06C+gWEoXDtKoqhujA8HphNuLLJs3EBzaKnTvcfQ@mail.gmail.com>

On 13 March 2012 21:00, Kukjin Kim <kgene.kim at samsung.com> wrote:
> ARM: EXYNOS: irqs.h for exynos4 and exynos5 - WIP
> This patch adds the interrupt definitions for EXYNOS5250 at
> <mach/irqs.h> file. Basically, now it is needed for EXYNOS5250
> interrupt and will be updated for single zImage next time.
>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
> ?arch/arm/mach-exynos/common.c ? ? ? ? ? ?| ? 97 ++++--
> ?arch/arm/mach-exynos/dev-ahci.c ? ? ? ? ?| ? ?4 +-
> ?arch/arm/mach-exynos/dev-audio.c ? ? ? ? | ? ?4 +-
> ?arch/arm/mach-exynos/include/mach/irqs.h | ?580 ++++++++++++++++++++++--------
> ?arch/arm/mach-exynos/mct.c ? ? ? ? ? ? ? | ? 23 +-
> ?arch/arm/plat-s5p/irq-pm.c ? ? ? ? ? ? ? | ? 25 +-
> ?arch/arm/plat-samsung/irq-vic-timer.c ? ?| ? 16 +
> ?7 files changed, 548 insertions(+), 201 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 7fdb139..0b53018 100644
> --- a/arch/arm/mach-exynos/common.c


[...]

> ? ? ? ?for (irq = 0 ; irq <= 15 ; irq++) {
> ? ? ? ? ? ? ? ?eint0_15_data[irq] = IRQ_EINT(irq);
>
> - ? ? ? ? ? ? ? irq_set_handler_data(exynos4_get_irq_nr(irq),
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?&eint0_15_data[irq]);
> - ? ? ? ? ? ? ? irq_set_chained_handler(exynos4_get_irq_nr(irq),
> + ? ? ? ? ? ? ? if (soc_is_exynos5250()) {
> + ? ? ? ? ? ? ? ? ? ? ? irq_set_handler_data(exynos4_eint0_15_src_int[irq],
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?&eint0_15_data[irq]);
> + ? ? ? ? ? ? ? ? ? ? ? irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? exynos4_irq_eint0_15);
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? irq_set_handler_data(exynos5_eint0_15_src_int[irq],
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?&eint0_15_data[irq]);
> + ? ? ? ? ? ? ? ? ? ? ? irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?exynos4_irq_eint0_15);
> + ? ? ? ? ? ? ? }
> ? ? ? ?}

The external interrupt numbers for Exynos4 and Exynos5 have been
swapped. This needs to be fixed.

Thanks,
Thomas.


From shawn.guo at linaro.org  Wed Mar 14 01:38:16 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 14 Mar 2012 13:38:16 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120313172807.AC4763E053B@localhost>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <4F5F5B3F.2000303@gmail.com> <4F5F60DB.9090801@itwatchdogs.com>
 <20120313172807.AC4763E053B@localhost>
Message-ID: <20120314053814.GC21337@S2101-09.ap.freescale.net>

On Tue, Mar 13, 2012 at 11:28:07AM -0600, Grant Likely wrote:
> On Tue, 13 Mar 2012 09:59:39 -0500, Zach Sadecki <zsadecki at itwatchdogs.com> wrote:
> > On 03/13/2012 09:35 AM, Rob Herring wrote:
> > > +	ahb at 80080000 {
> > > +		fec at 800f0000 {
> > > Use generic names: ethernet at 800f0000
> > Generic is good, but consistency is better, IMHO.  grepping existing dts 
> > files in 3.2.9 finds 6 instances of "fec@" and 0 instances of "ethernet@"
> > >> +			uart1: uart at 80074000 {
> > > Use generic names: uart1: serial at ...
> > Same comment here, but unfortunately there is already inconsistency in 
> > existing files...  25 instances of "serial@" and 35 instances of "uart@"
> 
> No, Rob is correct.  The generic names recommended practice is well
> established and documented.  Expand your grep search to include
> arch/powerpc/bot/dts/*.
> 
> See section 2.2.2 of ePAPR[1]
> 
> [1]https://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.1.pdf
> 
I will probably need to patch imx5 and imx6 dts files with the
inconsistency fixed.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Wed Mar 14 01:41:20 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 14 Mar 2012 13:41:20 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120313172351.97C5E3E053B@localhost>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
Message-ID: <20120314054116.GD21337@S2101-09.ap.freescale.net>

On Tue, Mar 13, 2012 at 11:23:51AM -0600, Grant Likely wrote:
...
> > +	apb at 80000000 {
> > +		compatible = "simple-bus";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		reg = <0x80000000 0x80000>;
> > +		ranges;
> > +
> > +		apbh at 80000000 {
> > +			compatible = "simple-bus";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			reg = <0x80000000 0x3c900>;
> > +			ranges;
> > +
> > +			icoll: interrupt-controller at 80000000 {
> > +				compatible = "fsl,imx28-icoll";
> > +				interrupt-controller;
> > +				#interrupt-cells = <1>;
> > +				reg = <0x80000000 0x2000>;
> > +			};
> > +		};
> > +
> > +		apbx at 80040000 {
> > +			compatible = "simple-bus";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			reg = <0x80040000 0x40000>;
> > +			ranges;
> > +
> > +			uart1: uart at 80074000 {
> > +				compatible = "arm,pl011", "arm,primecell";
> > +				reg = <0x80074000 0x2000>;
> > +				interrupts = <47>;
> > +			};
> > +		};
> 
> What is the purpose of the apbh and apbx busses?  Will more device nodes
> get added to them later, or does each only contain a single device?
> 
Since our ultimate goal is to convert mach-mxs over to device tree,
I would also suggest we have all the hardware blocks defined in dts
from the beginning.

-- 
Regards,
Shawn


From marek.vasut at gmail.com  Wed Mar 14 01:56:23 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 14 Mar 2012 06:56:23 +0100
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120314054116.GD21337@S2101-09.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314054116.GD21337@S2101-09.ap.freescale.net>
Message-ID: <201203140656.24301.marek.vasut@gmail.com>

Dear Shawn Guo,

> On Tue, Mar 13, 2012 at 11:23:51AM -0600, Grant Likely wrote:
> ...
> 
> > > +	apb at 80000000 {
> > > +		compatible = "simple-bus";
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		reg = <0x80000000 0x80000>;
> > > +		ranges;
> > > +
> > > +		apbh at 80000000 {
> > > +			compatible = "simple-bus";
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +			reg = <0x80000000 0x3c900>;
> > > +			ranges;
> > > +
> > > +			icoll: interrupt-controller at 80000000 {
> > > +				compatible = "fsl,imx28-icoll";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +				reg = <0x80000000 0x2000>;
> > > +			};
> > > +		};
> > > +
> > > +		apbx at 80040000 {
> > > +			compatible = "simple-bus";
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +			reg = <0x80040000 0x40000>;
> > > +			ranges;
> > > +
> > > +			uart1: uart at 80074000 {
> > > +				compatible = "arm,pl011", "arm,primecell";
> > > +				reg = <0x80074000 0x2000>;
> > > +				interrupts = <47>;
> > > +			};
> > > +		};
> > 
> > What is the purpose of the apbh and apbx busses?  Will more device nodes
> > get added to them later, or does each only contain a single device?
> 
> Since our ultimate goal is to convert mach-mxs over to device tree,
> I would also suggest we have all the hardware blocks defined in dts
> from the beginning.

Agreed.

Best regards,
Marek Vasut


From marek.vasut at gmail.com  Wed Mar 14 01:58:25 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 14 Mar 2012 06:58:25 +0100
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <1331628428-24017-3-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-3-git-send-email-b29396@freescale.com>
Message-ID: <201203140658.25854.marek.vasut@gmail.com>

Dear Dong Aisheng,

> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> 
> ---
> The patch is still using a private way for dma part binding
> since the common dma binding is still under discussion.
> http://www.spinics.net/lists/linux-omap/msg65528.html
> 
> Will update to use common dma binding when it hits mainline.
> ---
>  .../devicetree/bindings/mmc/fsl-mxs-mmc.txt        |   23 ++++++
>  drivers/mmc/host/mxs-mmc.c                         |   82
> +++++++++++++++++++- 2 files changed, 102 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt new file mode
> 100644
> index 0000000..adc1142
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> @@ -0,0 +1,23 @@
> +* FREESCALE MXS MMC peripheral
> +
> +Required properties:
> +- compatible : Should be "fsl,<chip>-mmc"
> +- reg : Should contain registers location and length
> +- interrupts : Should contain interrupt.
> +  The format is <irq_err irq_dma>.
> +- dma_channel: Should contain the dma channel it uses
> +
> +Optional properties:
> +- wp-gpios : Specify GPIOs for write protection
> +- slot-4bit: Specify 4 bit mode support
> +- slot-8bit: Specify 8 bit and 4 bit mode support
> +
> +Examples:
> +mmc1: ssp at 80010000 {
> +	compatible = "fsl,imx28-mmc";
> +	reg = <0x80010000 2000>;
> +	/* <irq_err irq_dma> */
> +	interrupts = <96 82>;
> +	dma_channel = <0>;
> +	slot-8bit;
> +};
> diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
> index 382c835..6cf2d17 100644
> --- a/drivers/mmc/host/mxs-mmc.c
> +++ b/drivers/mmc/host/mxs-mmc.c
> @@ -38,6 +38,10 @@
>  #include <linux/gpio.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
> +#include <linux/slab.h>
> 
>  #include <mach/mxs.h>
>  #include <mach/common.h>
> @@ -673,17 +677,79 @@ static bool mxs_mmc_dma_filter(struct dma_chan *chan,
> void *param) return true;
>  }
> 
> +#ifdef CONFIG_OF
> +static struct resource * __devinit mxs_mmc_get_of_dmares(
> +				struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct resource *dmares;
> +	int ret;
> +
> +	if (!np)
> +		return NULL;
> +
> +	dmares = kzalloc(sizeof(*dmares), GFP_KERNEL);
> +	dmares->flags = IORESOURCE_DMA;
> +	ret = of_property_read_u32(np, "dma_channel", &dmares->start);
> +	if (ret) {
> +		dev_err(&pdev->dev, "unable to get dmares from dt\n");
> +		return NULL;
> +	}
> +	dmares->end = dmares->start;
> +
> +	return dmares;
> +}
> +
> +static int __devinit mxs_mmc_get_of_property(struct platform_device *pdev,
> +				struct mxs_mmc_platform_data **ppdata)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct mxs_mmc_platform_data *pdata = *ppdata;
> +
> +	if (!np)
> +		return -ENODEV;
> +
> +	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> +
> +	if (of_get_property(np, "slot-8bit", NULL))
> +		pdata->flags |= SLOTF_8_BIT_CAPABLE;
> +
> +	if (of_get_property(np, "slot-4bit", NULL))
> +		pdata->flags |= SLOTF_4_BIT_CAPABLE;
> +
> +	pdata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
> +
> +	dev_dbg(&pdev->dev, "wp-gpios %d flags %d\n", pdata->wp_gpio,
> +		pdata->flags);
> +
> +	return 0;
> +}
> +#else
> +static struct resource * __devinit mxs_mmc_get_of_dmares(
> +				struct platform_device *pdev)
> +{
> +	return NULL;
> +}
> +static inline int mxs_mmc_get_of_property(struct platform_device *pdev,
> +			struct mxs_mmc_platform_data *pdata)
> +{
> +	return -ENODEV;
> +}
> +#endif
> +
>  static int mxs_mmc_probe(struct platform_device *pdev)
>  {
>  	struct mxs_mmc_host *host;
>  	struct mmc_host *mmc;
>  	struct resource *iores, *dmares, *r;
> -	struct mxs_mmc_platform_data *pdata;
> +	struct mxs_mmc_platform_data *pdata = NULL;
>  	int ret = 0, irq_err, irq_dma;
>  	dma_cap_mask_t mask;
> 
>  	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
> +	dmares = mxs_mmc_get_of_dmares(pdev);
> +	if (dmares == NULL)
> +		dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
>  	irq_err = platform_get_irq(pdev, 0);
>  	irq_dma = platform_get_irq(pdev, 1);
>  	if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
> @@ -740,7 +806,9 @@ static int mxs_mmc_probe(struct platform_device *pdev)
>  	mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
>  		    MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
> 
> -	pdata =	mmc_dev(host->mmc)->platform_data;
> +	mxs_mmc_get_of_property(pdev, &pdata);
> +	if (pdata == NULL)
> +		pdata =	mmc_dev(host->mmc)->platform_data;
>  	if (pdata) {
>  		if (pdata->flags & SLOTF_8_BIT_CAPABLE)
>  			mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
> @@ -851,6 +919,13 @@ static const struct dev_pm_ops mxs_mmc_pm_ops = {
>  };
>  #endif
> 
> +static const struct of_device_id mxs_mmc_dt_ids[] = {
> +	{ .compatible = "fsl,imx23-mmc", .data = NULL, },
> +	{ .compatible = "fsl,imx28-mmc", .data = NULL, },

Do you really need two distinct ones here?

> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
> +
>  static struct platform_driver mxs_mmc_driver = {
>  	.probe		= mxs_mmc_probe,
>  	.remove		= mxs_mmc_remove,
> @@ -860,6 +935,7 @@ static struct platform_driver mxs_mmc_driver = {
>  #ifdef CONFIG_PM
>  		.pm	= &mxs_mmc_pm_ops,
>  #endif
> +		.of_match_table = mxs_mmc_dt_ids,
>  	},
>  };


From marek.vasut at gmail.com  Wed Mar 14 02:01:06 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 14 Mar 2012 07:01:06 +0100
Subject: [PATCH v1 0/5] dt: add basic imx28 support
In-Reply-To: <1331628428-24017-1-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
Message-ID: <201203140701.07111.marek.vasut@gmail.com>

Dear Dong Aisheng,

> This patch series adds basic imx28 dt support including fec, mmc and dma.
> 
> Tested on mx28evk.
> 
> TODO:
> Convert the remaining devices to support dt.
> mxs-auart, mxs-gpio, i2c, flexcan, saif, rtc, pwm, fb.
> 
> Dong Aisheng (5):
>   ARM: imx28: add basic dt support
>   mmc: mxs-mmc: add dt probe support
>   ARM: imx28evk: add mmc dt support
>   dma: mxs-dma: add dt probe support
>   ARM: mxs: add mxs dma dt support
> 
Can you keep me in Cc on new versions of these patches? Thanks!

Best regards,
Marek Vasut


From rmallon at gmail.com  Wed Mar 14 02:04:06 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Wed, 14 Mar 2012 17:04:06 +1100
Subject: [GIT PULL] ep93xx for v3.4
Message-ID: <4F6034D6.1030208@gmail.com>

Hi Arnd,

This my first attempt at doing at git pull request, so hopefully I
haven't messed it up :-).

Thanks,
~Ryan

The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
  Linus Torvalds (1):
        Linux 3.3-rc7

are available in the git repository at:

  git://github.com/RyanMallon/linux-2.6.git ep93xx-for-arm-soc

H Hartley Sweeten (1):
      ep93xx: Convert the watchdog driver into a platform device.

Ryan Mallon (10):
      ep93xx: Move PHYS_BASE defines to local SoC header file
      ep93xx: Don't use system controller defines in audio drivers
      ep93xx: Move GPIO defines to gpio-ep93xx.h
      ep93xx: Use ioremap for backlight driver
      ep93xx: Move peripheral defines to local SoC header
      ep93xx: Configure GPIO ports in core code
      ep93xx: Make syscon access functions private to SoC
      ep93xx: Move crunch code to mach-ep93xx directory
      ep93xx: Move EP93XX_SYSCON defines to SoC private header
      ep93xx: Remove unnecessary includes of ep93xx-regs.h

 arch/arm/kernel/Makefile                        |    3 -
 arch/arm/mach-ep93xx/Makefile                   |    3 +
 arch/arm/mach-ep93xx/adssphere.c                |    1 +
 arch/arm/mach-ep93xx/clock.c                    |    1 +
 arch/arm/mach-ep93xx/core.c                     |   54 ++++--
 arch/arm/{kernel => mach-ep93xx}/crunch-bits.S  |    0
 arch/arm/{kernel => mach-ep93xx}/crunch.c       |    4 +-
 arch/arm/mach-ep93xx/dma.c                      |    2 +
 arch/arm/mach-ep93xx/edb93xx.c                  |    1 +
 arch/arm/mach-ep93xx/gesbc9312.c                |    1 +
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |  191 +--------------------
 arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h |   10 +
 arch/arm/mach-ep93xx/include/mach/hardware.h    |    1 -
 arch/arm/mach-ep93xx/include/mach/platform.h    |   16 +--
 arch/arm/mach-ep93xx/micro9.c                   |    1 +
 arch/arm/mach-ep93xx/simone.c                   |    2 +
 arch/arm/mach-ep93xx/snappercl15.c              |    2 +
 arch/arm/mach-ep93xx/soc.h                      |  213 +++++++++++++++++++++++
 arch/arm/mach-ep93xx/ts72xx.c                   |    1 +
 arch/arm/mach-ep93xx/vision_ep9307.c            |    2 +
 drivers/gpio/gpio-ep93xx.c                      |    7 -
 drivers/video/backlight/ep93xx_bl.c             |   25 ++--
 drivers/video/ep93xx-fb.c                       |   18 +-
 drivers/watchdog/ep93xx_wdt.c                   |   51 ++++--
 sound/soc/ep93xx/edb93xx.c                      |    4 +-
 sound/soc/ep93xx/snappercl15.c                  |    4 +-
 26 files changed, 344 insertions(+), 274 deletions(-)
 rename arch/arm/{kernel => mach-ep93xx}/crunch-bits.S (100%)
 rename arch/arm/{kernel => mach-ep93xx}/crunch.c (98%)
 create mode 100644 arch/arm/mach-ep93xx/soc.h



From sfr at canb.auug.org.au  Wed Mar 14 02:06:28 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Wed, 14 Mar 2012 17:06:28 +1100
Subject: linux-next: manual merge of the arm-soc tree with the sound-asoc tree
Message-ID: <20120314170628.4b0b5688441624a7a080d7cd@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-imx/mach-imx27_visstrim_m10.c between commit 5ec65ee589fd
("ASoC: mx27vis-aic32x4: Convert it to platform driver") from the
sound-asoc tree and commit f52f5a5503b5 ("i.MX27: visstrim_m10: Add video
support") from the arm-soc tree.

I fixed it up (see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 428459f,0a1643c..0000000
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@@ -263,7 -393,10 +393,11 @@@ static void __init visstrim_m10_board_i
  	imx27_add_fec(NULL);
  	imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
  	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+ 	platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
+ 				      &iclink_tvp5150, sizeof(iclink_tvp5150));
+ 	gpio_led_register_device(0, &visstrim_m10_led_data);
+ 	visstrim_camera_init();
 +	imx_add_platform_device("mx27vis", 0, NULL, 0, NULL, 0);
  }
  
  static void __init visstrim_m10_timer_init(void)
-------------- next part --------------
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From prakash.pm at ti.com  Wed Mar 14 02:16:54 2012
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Wed, 14 Mar 2012 06:16:54 +0000
Subject: [PATCH] arm:da850: register musb device
In-Reply-To: <4F5F7F91.8010301@mvista.com>
References: <1331651015-32586-1-git-send-email-prakash.pm@ti.com>
 <4F5F7F91.8010301@mvista.com>
Message-ID: <A73F36158E33644199EB82C5EC81C7BC3178406C@DBDE01.ent.ti.com>

Hi Sergei,

On Tue, Mar 13, 2012 at 22:40:41, Sergei Shtylyov wrote:
> On 03/13/2012 06:03 PM, Manjunathappa, Prakash wrote:
> 
> > Properly set up the OTG mode thru the CFGCHIP2 register, enable the
> > USB0_DRVVBUS pin,
> 
>     I don't see where you are enabling it.
> 

Yes, I will correct the message.

> > and finally register the MUSB platform device.
> >
> > Signed-off-by: Ajay Kumar Gupta<ajay.gupta at ti.com>
> > Signed-off-by: Manjunathappa, Prakash<prakash.pm at ti.com>
> > ---
> > Patche are on top below posted patches:
> > http://www.spinics.net/lists/linux-usb/msg59656.html
> 
> >   arch/arm/mach-davinci/board-da850-evm.c |   12 ++++++++++++
> >   arch/arm/mach-davinci/usb.c             |    9 +++++++++
> >   2 files changed, 21 insertions(+), 0 deletions(-)
> 
> > diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
> > index 178d178..539e12c 100644
> > --- a/arch/arm/mach-davinci/board-da850-evm.c
> > +++ b/arch/arm/mach-davinci/board-da850-evm.c
> > @@ -787,6 +787,18 @@ static __init void da850_evm_usb_init(void)
> >   	 */
> >   	cfgchip2&= ~CFGCHIP2_USB1PHYCLKMUX;
> >   	cfgchip2 |=  CFGCHIP2_USB2PHYCLKMUX;
> > +	/*
> > +	 * We have to override VBUS/ID signals when MUSB is configured into the
> > +	 * host-only mode -- ID pin will float if no cable is connected, so the
> > +	 * controller won't be able to drive VBUS thinking that it's a B-device.
> > +	 * Otherwise, we want to use the OTG mode and enable VBUS comparators.
> > +	 */
> > +	cfgchip2 &= ~CFGCHIP2_OTGMODE;
> > +#if CONFIG_USB_MUSB_DA8XX
> 
>     This #ifdef doesn't make sense. It will make driver always work in host mode.
> 

I will change it to support OTG.

> > +	cfgchip2 |=  CFGCHIP2_FORCE_HOST;
> > +#else
> > +	cfgchip2 |=  CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
> 
>     This is what you need to leave. The driver should always work in OTG mode now.
> 

Correct, I will fix this.

> > +#endif
> >
> >   	__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
> >
> > diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
> > index 25c3520..a941dc5 100644
> > --- a/arch/arm/mach-davinci/usb.c
> > +++ b/arch/arm/mach-davinci/usb.c
> > @@ -284,6 +284,15 @@ void __init da8xx_board_usb_init(const short pins[],
> >   		goto usb11_setup_fail;
> >   	}
> >
> > +	/*
> > +	 * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A),
> > +	 * with the power on to power good time of 3 ms.
> > +	 */
> > +	ret = da8xx_register_usb20(1000, 3);
> > +	if (ret)
> > +		pr_warning("%s: USB 2.0 registration failed: %d\n",
> > +			   __func__, ret);
> 
>     Er, why this code is moved there? And how will this work on DA830 -- try to 
> register MUSB twice? Place this in the board file please where it belongs.
> 

Yes, I will revert this change.

Thanks,
Prakash

> WBR, Sergei
> 



From aisheng.dong at freescale.com  Wed Mar 14 02:23:55 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 14 Mar 2012 14:23:55 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <4F5F5B3F.2000303@gmail.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <4F5F5B3F.2000303@gmail.com>
Message-ID: <20120314062354.GA8494@shlinux2.ap.freescale.net>

On Tue, Mar 13, 2012 at 09:35:43AM -0500, Rob Herring wrote:
> On 03/13/2012 03:47 AM, Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > This patch includes basic dt support which can boot via nfs rootfs.
> > 
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > ---
> >  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
> >  arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
> >  arch/arm/boot/dts/imx28.dtsi                  |   88 +++++++++++++++++++++++++
> >  arch/arm/mach-mxs/Kconfig                     |    9 +++
> >  arch/arm/mach-mxs/Makefile                    |    1 +
> >  arch/arm/mach-mxs/imx28-dt.c                  |   67 +++++++++++++++++++
> >  6 files changed, 200 insertions(+), 0 deletions(-)
....
> > +				interrupts = <47>;
> > +			};
> > +		};
> > +	};
> > +
> > +	ahb at 80080000 {
> > +		compatible = "simple-bus";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		reg = <0x80080000 0x80000>;
> > +		ranges;
> > +
> > +		fec at 800f0000 {
> > +			compatible = "fsl,imx28-fec";
> > +			reg = <0x800f0000 0x4000>;
> 
> This too IIRC.
> 
The size is 16KB/0x4000 in iMX28 spec. :)

> > +			interrupts = <101>;
> > +			status = "disabled";
> > +		};
> > +
> > +		fec at 800f4000 {
> > +			compatible = "fsl,imx28-fec";
> > +			reg = <0x800f4000 0x4000>;
> > +			interrupts = <102>;
> > +			status = "disabled";
> > +		};
> > +
> > +	};
> > +};
> > diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
> > index c57f996..6ab66af 100644
> > --- a/arch/arm/mach-mxs/Kconfig
> > +++ b/arch/arm/mach-mxs/Kconfig
> > @@ -17,6 +17,15 @@ config SOC_IMX28
> >  
> >  comment "MXS platforms:"
> >  
> > +config MACH_IMX28_DT
> 
> Perhaps this should be more generic like MACH_MXS_DT to eventually
> support MX23 as well?
> 
I just did like the imx ways.
But yes if we see the need when do imx23 dt support.

> > +	bool "Support i.MX28 platforms from device tree"
> > +	select SOC_IMX28
> > +	select USE_OF
> > +	select MACH_MX28EVK
> 
> This should not be selected here.
> 
Like other imx soc dt board files, the imx28-dt.c may need to use some bits
like pinmux in mx28evk.c board file.

Yes, currently i can remove it since it is using uboot pinmux setting.
But when add other devices support which is not covered in u-boot like flexcan,
i may need to use non-dt board's pinmux setting.
So maybe we can keep it first and remove it when totally not dependent
on non-dt files.

> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +#include <linux/init.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_platform.h>
> > +#include <asm/mach/arch.h>
> > +#include <asm/mach/time.h>
> > +#include <mach/common.h>
> > +#include <mach/mx28.h>
> > +
> > +static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
> > +	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
> > +	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
> 
> Why do you need the old names?
> 
To keep align with the old clocks.
See arch/arm/mach-mxs/clock-mx28.c:
_REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
_REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
Is there any better way to avoid this?

> > +	{ /* sentinel */ }
> > +};
> > +
> > +static void __init imx28_init(void)
> > +{
> > +	of_platform_populate(NULL, of_default_bus_match_table,
> > +			     imx28_auxdata_lookup, NULL);
> > +}
> > +
> > +static const struct of_device_id icoll_of_match[] __initconst = {
> > +	{ .compatible = "fsl,imx28-icoll", },
> > +	{},
> > +};
> > +
> > +static void __init imx28_dt_init_irq(void)
> > +{
> > +	irq_domain_generate_simple(icoll_of_match, MX28_ICOLL_BASE_ADDR, 0);
> 
> Please do "proper" domain support for the interrupt controller and use
> of_irq_init.
> 
Ok, i will see it.

For others, will fix them all.
Thanks for the review.

Regards
Dong Aisheng



From aisheng.dong at freescale.com  Wed Mar 14 02:30:13 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 14 Mar 2012 14:30:13 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120314054116.GD21337@S2101-09.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314054116.GD21337@S2101-09.ap.freescale.net>
Message-ID: <20120314063012.GB8494@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 01:41:20PM +0800, Shawn Guo wrote:
> On Tue, Mar 13, 2012 at 11:23:51AM -0600, Grant Likely wrote:
> ...
> > > +	apb at 80000000 {
> > > +		compatible = "simple-bus";
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		reg = <0x80000000 0x80000>;
> > > +		ranges;
> > > +
> > > +		apbh at 80000000 {
> > > +			compatible = "simple-bus";
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +			reg = <0x80000000 0x3c900>;
> > > +			ranges;
> > > +
> > > +			icoll: interrupt-controller at 80000000 {
> > > +				compatible = "fsl,imx28-icoll";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +				reg = <0x80000000 0x2000>;
> > > +			};
> > > +		};
> > > +
> > > +		apbx at 80040000 {
> > > +			compatible = "simple-bus";
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +			reg = <0x80040000 0x40000>;
> > > +			ranges;
> > > +
> > > +			uart1: uart at 80074000 {
> > > +				compatible = "arm,pl011", "arm,primecell";
> > > +				reg = <0x80074000 0x2000>;
> > > +				interrupts = <47>;
> > > +			};
> > > +		};
> > 
> > What is the purpose of the apbh and apbx busses?  Will more device nodes
> > get added to them later, or does each only contain a single device?
> > 
> Since our ultimate goal is to convert mach-mxs over to device tree,
> I would also suggest we have all the hardware blocks defined in dts
> from the beginning.
> 
Also agree.
Will add them all in later patches.

Regards
Dong Aisheng



From kgene.kim at samsung.com  Wed Mar 14 02:30:22 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 23:30:22 -0700
Subject: [PATCH v3 07/12] ARM: EXYNOS: add interrupt definitions for
 EXYNOS5250
In-Reply-To: <CAOesGMgEg3Pem4ZMCEp341MxSrW7uajZ0wB1YWgQM-k=KSdiXA@mail.gmail.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>	<1331652643-12626-8-git-send-email-kgene.kim@samsung.com>
 <CAOesGMgEg3Pem4ZMCEp341MxSrW7uajZ0wB1YWgQM-k=KSdiXA@mail.gmail.com>
Message-ID: <4F603AFE.9040303@samsung.com>

On 03/13/12 20:42, Olof Johansson wrote:
> Hi
>
> On Tue, Mar 13, 2012 at 8:30 AM, Kukjin Kim<kgene.kim at samsung.com>  wrote:
>> ARM: EXYNOS: irqs.h for exynos4 and exynos5 - WIP
>> This patch adds the interrupt definitions for EXYNOS5250 at
>> <mach/irqs.h>  file. Basically, now it is needed for EXYNOS5250
>> interrupt and will be updated for single zImage next time.
>
> Nit for when you stage the branch: Update the commit message a bit, I think?
>
Oops, what's happened :( Let me update it.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Wed Mar 14 02:32:14 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 23:32:14 -0700
Subject: [PATCH v3 07/12] ARM: EXYNOS: add interrupt definitions for
 EXYNOS5250
In-Reply-To: <CAJuYYwTFEV06C+gWEoXDtKoqhujA8HphNuLLJs3EBzaKnTvcfQ@mail.gmail.com>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>	<1331652643-12626-8-git-send-email-kgene.kim@samsung.com>
 <CAJuYYwTFEV06C+gWEoXDtKoqhujA8HphNuLLJs3EBzaKnTvcfQ@mail.gmail.com>
Message-ID: <4F603B6E.7000103@samsung.com>

On 03/13/12 22:27, Thomas Abraham wrote:
> On 13 March 2012 21:00, Kukjin Kim<kgene.kim at samsung.com>  wrote:
>> ARM: EXYNOS: irqs.h for exynos4 and exynos5 - WIP
>> This patch adds the interrupt definitions for EXYNOS5250 at
>> <mach/irqs.h>  file. Basically, now it is needed for EXYNOS5250
>> interrupt and will be updated for single zImage next time.
>>
>> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
>> ---
>>   arch/arm/mach-exynos/common.c            |   97 ++++--
>>   arch/arm/mach-exynos/dev-ahci.c          |    4 +-
>>   arch/arm/mach-exynos/dev-audio.c         |    4 +-
>>   arch/arm/mach-exynos/include/mach/irqs.h |  580 ++++++++++++++++++++++--------
>>   arch/arm/mach-exynos/mct.c               |   23 +-
>>   arch/arm/plat-s5p/irq-pm.c               |   25 +-
>>   arch/arm/plat-samsung/irq-vic-timer.c    |   16 +
>>   7 files changed, 548 insertions(+), 201 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
>> index 7fdb139..0b53018 100644
>> --- a/arch/arm/mach-exynos/common.c
>
>
> [...]
>
>>         for (irq = 0 ; irq<= 15 ; irq++) {
>>                 eint0_15_data[irq] = IRQ_EINT(irq);
>>
>> -               irq_set_handler_data(exynos4_get_irq_nr(irq),
>> -&eint0_15_data[irq]);
>> -               irq_set_chained_handler(exynos4_get_irq_nr(irq),
>> +               if (soc_is_exynos5250()) {
>> +                       irq_set_handler_data(exynos4_eint0_15_src_int[irq],
>> +&eint0_15_data[irq]);
>> +                       irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
>> +                                               exynos4_irq_eint0_15);
>> +               } else {
>> +                       irq_set_handler_data(exynos5_eint0_15_src_int[irq],
>> +&eint0_15_data[irq]);
>> +                       irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
>>                                         exynos4_irq_eint0_15);
>> +               }
>>         }
>
> The external interrupt numbers for Exynos4 and Exynos5 have been
> swapped. This needs to be fixed.
>
Oops again :-( let me fix it.

Thanks, Thomas.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Wed Mar 14 02:33:44 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 23:33:44 -0700
Subject: [PATCH v3 08/12] ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5
In-Reply-To: <20120314035203.GA2531@quad.lixom.net>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <1331652643-12626-9-git-send-email-kgene.kim@samsung.com>
 <20120314035203.GA2531@quad.lixom.net>
Message-ID: <4F603BC8.3020900@samsung.com>

On 03/13/12 20:52, Olof Johansson wrote:
> Hi,
>
> A couple of comments below.
>
I agree, and will address comments from you.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

>
> On Tue, Mar 13, 2012 at 08:30:39AM -0700, Kukjin Kim wrote:
>> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
>> index 0b53018..72f21e4 100644
>> --- a/arch/arm/mach-exynos/common.c
>> +++ b/arch/arm/mach-exynos/common.c
>> @@ -777,39 +779,24 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
>>   	mask = 0x7<<  shift;
>>
>>   	spin_lock(&eint_lock);
>> -	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
>> +	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
>>   	ctrl&= ~mask;
>>   	ctrl |= newvalue<<  shift;
>> -	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
>> +	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
>>   	spin_unlock(&eint_lock);
>>
>> -	switch (offs) {
>> -	case 0 ... 7:
>> -		s3c_gpio_cfgpin(EINT_GPIO_0(offs&  0x7), EINT_MODE);
>> -		break;
>> -	case 8 ... 15:
>> -		s3c_gpio_cfgpin(EINT_GPIO_1(offs&  0x7), EINT_MODE);
>> -		break;
>> -	case 16 ... 23:
>> -		s3c_gpio_cfgpin(EINT_GPIO_2(offs&  0x7), EINT_MODE);
>> -		break;
>> -	case 24 ... 31:
>> -		s3c_gpio_cfgpin(EINT_GPIO_3(offs&  0x7), EINT_MODE);
>> -		break;
>> -	default:
>> -		printk(KERN_ERR "No such irq number %d", offs);
>> -	}
>> +	s3c_gpio_cfgpin(irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
>
> irq_to_gpio is going away, so it's not a good idea to add it under that name.
>
> Add a local function locally at the top of this file instead. and call
> it something else.
>
>> diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
>> index 80523ca..c09deb6 100644
>> --- a/arch/arm/mach-exynos/include/mach/gpio.h
>> +++ b/arch/arm/mach-exynos/include/mach/gpio.h
>> @@ -146,4 +146,33 @@ enum s5p_gpio_number {
>>   #define ARCH_NR_GPIOS		(EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) +	\
>>   				 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
>>
>> +#include<linux/types.h>
>> +#include<linux/err.h>
>> +#include<mach/irqs.h>
>> +#include<plat/cpu.h>
>> +
>> +static inline int irq_to_gpio(unsigned int irq)
>> +{
>> +	if (irq<  IRQ_EINT(0))
>> +		return -EINVAL;
>> +
>> +	irq -= IRQ_EINT(0);
>> +	if (irq<  8)
>> +		return soc_is_exynos5250() ?  EXYNOS5_GPX0(irq) :
>> +					 EXYNOS4_GPX0(irq);
>> +	irq -= 8;
>> +	if (irq<  8)
>> +		return soc_is_exynos5250() ?  EXYNOS5_GPX1(irq) :
>> +					 EXYNOS4_GPX1(irq);
>> +	irq -= 8;
>> +	if (irq<  8)
>> +		return soc_is_exynos5250() ?  EXYNOS5_GPX2(irq) :
>> +					 EXYNOS4_GPX2(irq);
>> +	irq -= 8;
>> +	if (irq<  8)
>> +		return soc_is_exynos5250() ?  EXYNOS5_GPX3(irq) :
>> +					 EXYNOS4_GPX3(irq);
>> +	return -EINVAL;
>> +}
>
> I think this would be cleaner as two small helpers and one check for SoC
> version instead.


From aisheng.dong at freescale.com  Wed Mar 14 02:42:25 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 14 Mar 2012 14:42:25 +0800
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <20120313174238.CE9133E053B@localhost>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-3-git-send-email-b29396@freescale.com>
 <20120313174238.CE9133E053B@localhost>
Message-ID: <20120314064224.GA25735@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 01:42:38AM +0800, Grant Likely wrote:
> On Tue, 13 Mar 2012 16:47:05 +0800, Dong Aisheng <b29396 at freescale.com> wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > ---
> > The patch is still using a private way for dma part binding
> > since the common dma binding is still under discussion.
> > http://www.spinics.net/lists/linux-omap/msg65528.html
> > 
> > Will update to use common dma binding when it hits mainline.
> > ---
> >  .../devicetree/bindings/mmc/fsl-mxs-mmc.txt        |   23 ++++++
> >  drivers/mmc/host/mxs-mmc.c                         |   82 +++++++++++++++++++-
> >  2 files changed, 102 insertions(+), 3 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> > new file mode 100644
> > index 0000000..adc1142
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> > @@ -0,0 +1,23 @@
> > +* FREESCALE MXS MMC peripheral
> > +
> > +Required properties:
> > +- compatible : Should be "fsl,<chip>-mmc"
> > +- reg : Should contain registers location and length
> > +- interrupts : Should contain interrupt.
> > +  The format is <irq_err irq_dma>.
> > +- dma_channel: Should contain the dma channel it uses
> 
> Don't use '_' in property names.
> 
Yes, my mistake.

> The is a generic dma binding being drafted that uses a phandle to the dma
> controller and the ability to encode channel numbers.  You may want to take
> a look at it.
> 
I will look at it.
Thanks for the reminder.

...
> > +	dmares->flags = IORESOURCE_DMA;
> > +	ret = of_property_read_u32(np, "dma_channel", &dmares->start);
> > +	if (ret) {
> > +		dev_err(&pdev->dev, "unable to get dmares from dt\n");
> > +		return NULL;
> > +	}
> > +	dmares->end = dmares->start;
> > +
> > +	return dmares;
> > +}
> > +
> > +static int __devinit mxs_mmc_get_of_property(struct platform_device *pdev,
> > +				struct mxs_mmc_platform_data **ppdata)
> > +{
> > +	struct device_node *np = pdev->dev.of_node;
> > +	struct mxs_mmc_platform_data *pdata = *ppdata;
> > +
> > +	if (!np)
> > +		return -ENODEV;
> > +
> > +	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> 
> Ditto
> 
Got it.

> Fix up those comments and you can add my:
> 
> Acked-by: Grant Likely <grant.likely at secretlab.ca>
> 
Thanks.

Regards
Dong Aisheng



From kgene.kim at samsung.com  Wed Mar 14 02:43:57 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 23:43:57 -0700
Subject: [PATCH v3 12/12] ARM: dts: add initial dts file for EXYNOS5250,
 SMDK5250
In-Reply-To: <20120314035655.GB2531@quad.lixom.net>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <1331652643-12626-13-git-send-email-kgene.kim@samsung.com>
 <20120314035655.GB2531@quad.lixom.net>
Message-ID: <4F603E2D.1050007@samsung.com>

On 03/13/12 20:56, Olof Johansson wrote:
> On Tue, Mar 13, 2012 at 08:30:43AM -0700, Kukjin Kim wrote:
>> This patch adds initial dts file for EXYNOS5250 SoC. This dts
>> file is including the SoC specific devices and properties. And
>> adds the dts file for SMDK5250 board which uses the EXYNOS5250
>> dts file. Its board specific properites will be added later.
>>
>> Cc: Thomas Abraham<thomas.abraham at linaro.org>
>> Cc: Grant Likely<grant.likely at secretlab.ca>
>> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
>> ---
>>   arch/arm/boot/dts/exynos5250-smdk5250.dts |   26 ++
>>   arch/arm/boot/dts/exynos5250.dtsi         |  413 +++++++++++++++++++++++++++++
>>   2 files changed, 439 insertions(+), 0 deletions(-)
>>   create mode 100644 arch/arm/boot/dts/exynos5250-smdk5250.dts
>>   create mode 100644 arch/arm/boot/dts/exynos5250.dtsi
>>
>> diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
>> new file mode 100644
>> index 0000000..491539a
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts

[...]

>> +	chosen {
>> +		bootargs = "root=/dev/ram0 rw ramdisk=8192 rootfstype=squashfs initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
>
> Having these specific bootargs in the include file rarely makes sense, it's
> better to have firmware update from the settings in firmware and just have a very
> simple fallback here.
>
> In particular initrd is quite custom to hardcode like that.
>
Yes, the bootargs is no mandatory in dts file and u-boot bootargs can be 
set. OK, we can simplify it here like following.

bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200"

[...]

>> +	watchdog at 101D0000 {
>
> lowercase hex here and elsewhere in these files, please.
>
OK, I see.

> Also, technically no need to specify a unit address (@<foo>) in the device node
> name unless you need it to tell more than one entry apart, but it's become
> customary to always add them on ARM for some reason.
>
OK, just to be consistent in writing device nodes, prefer to add address 
to the names for all device nodes.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From nsekhar at ti.com  Wed Mar 14 02:46:57 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 14 Mar 2012 06:46:57 +0000
Subject: [GIT PULL] DaVinci fixes for v3.3
Message-ID: <DF0F476B391FA8409C78302C7BA518B6317F5E48@DBDE01.ent.ti.com>

Hi Arnd, Olof,

Can you please pull the following DaVinci fixes for v3.3.
They fix a build and section mismatch warning.

Thanks,
Sekhar

The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
  Linus Torvalds (1):
        Linux 3.3-rc7

are available in the git repository at:

  git://gitorious.org/linux-davinci/linux-davinci.git fixes

Uwe Kleine-K??????nig (2):
      ARM: davinci: cpufreq: fix compiler warning
      ARM: davinci: DA850: move da850_register_pm to .init.text

 arch/arm/mach-davinci/cpufreq.c |    2 +-
 arch/arm/mach-davinci/da850.c   |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-


From kgene.kim at samsung.com  Wed Mar 14 02:49:37 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 13 Mar 2012 23:49:37 -0700
Subject: [PATCH v3 09/12] ARM: EXYNOS: add support get_core_count() for
 EXYNOS5250
In-Reply-To: <201203131615.49846.arnd@arndb.de>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <1331652643-12626-10-git-send-email-kgene.kim@samsung.com>
 <201203131615.49846.arnd@arndb.de>
Message-ID: <4F603F81.8040505@samsung.com>

On 03/13/12 09:15, Arnd Bergmann wrote:
> On Tuesday 13 March 2012, Kukjin Kim wrote:
>> The EXYNOS5250 has two Cortex-A15 cores and there's no
>> need to call scu_enable() in platform_smp_prepare_cpus().
>>
>> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
>
> Can you explain this patch more? It only seems to make the
> code less generic, but there is no indication if calling
> the scu_get_core_count() function is actually wrong on
> exynos5.
>
Contrary to Cortex-A9, Cortex-A15 has no regarding scu register so 
EXYNO5250 can not get the number of core from that like EXYNOS4 SoCs.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From marek.vasut at gmail.com  Wed Mar 14 02:51:30 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 14 Mar 2012 07:51:30 +0100
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120314062354.GA8494@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <4F5F5B3F.2000303@gmail.com>
 <20120314062354.GA8494@shlinux2.ap.freescale.net>
Message-ID: <201203140751.30747.marek.vasut@gmail.com>

Dear Dong Aisheng,

> On Tue, Mar 13, 2012 at 09:35:43AM -0500, Rob Herring wrote:
> > On 03/13/2012 03:47 AM, Dong Aisheng wrote:
> > > From: Dong Aisheng <dong.aisheng at linaro.org>
> > > 
> > > This patch includes basic dt support which can boot via nfs rootfs.
> > > 
> > > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > > ---
> > > 
> > >  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
> > >  arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
> > >  arch/arm/boot/dts/imx28.dtsi                  |   88
> > >  +++++++++++++++++++++++++ arch/arm/mach-mxs/Kconfig                  
> > >    |    9 +++
> > >  arch/arm/mach-mxs/Makefile                    |    1 +
> > >  arch/arm/mach-mxs/imx28-dt.c                  |   67
> > >  +++++++++++++++++++ 6 files changed, 200 insertions(+), 0
> > >  deletions(-)
> 
> ....
> 
> > > +				interrupts = <47>;
> > > +			};
> > > +		};
> > > +	};
> > > +
> > > +	ahb at 80080000 {
> > > +		compatible = "simple-bus";
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		reg = <0x80080000 0x80000>;
> > > +		ranges;
> > > +
> > > +		fec at 800f0000 {
> > > +			compatible = "fsl,imx28-fec";
> > > +			reg = <0x800f0000 0x4000>;
> > 
> > This too IIRC.
> 
> The size is 16KB/0x4000 in iMX28 spec. :)

Agreed, the memory map is slightly non-standard.

> 
> > > +			interrupts = <101>;
> > > +			status = "disabled";
> > > +		};
> > > +
> > > +		fec at 800f4000 {
> > > +			compatible = "fsl,imx28-fec";
> > > +			reg = <0x800f4000 0x4000>;
> > > +			interrupts = <102>;
> > > +			status = "disabled";
> > > +		};
> > > +
> > > +	};
> > > +};
> > > diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
> > > index c57f996..6ab66af 100644
> > > --- a/arch/arm/mach-mxs/Kconfig
> > > +++ b/arch/arm/mach-mxs/Kconfig
> > > @@ -17,6 +17,15 @@ config SOC_IMX28
> > > 
> > >  comment "MXS platforms:"
> > > 
> > > +config MACH_IMX28_DT
> > 
> > Perhaps this should be more generic like MACH_MXS_DT to eventually
> > support MX23 as well?
> 
> I just did like the imx ways.
> But yes if we see the need when do imx23 dt support.

Let's do it all in one swipe, there's not so much difference between these two 
chips.
> 
> > > +	bool "Support i.MX28 platforms from device tree"
> > > +	select SOC_IMX28
> > > +	select USE_OF
> > > +	select MACH_MX28EVK
> > 
> > This should not be selected here.
> 
> Like other imx soc dt board files, the imx28-dt.c may need to use some bits
> like pinmux in mx28evk.c board file.
> 
> Yes, currently i can remove it since it is using uboot pinmux setting.
> But when add other devices support which is not covered in u-boot like
> flexcan, i may need to use non-dt board's pinmux setting.
> So maybe we can keep it first and remove it when totally not dependent
> on non-dt files.

I'd be all in for the "decremental approach" -- keep in whatever is needed and 
remove is as it becomes redundant.

> 
> > > + * The code contained herein is licensed under the GNU General Public
> > > + * License. You may obtain a copy of the GNU General Public License
> > > + * Version 2 or later at the following locations:
> > > + *
> > > + * http://www.opensource.org/licenses/gpl-license.html
> > > + * http://www.gnu.org/copyleft/gpl.html
> > > + */
> > > +
> > > +#include <linux/init.h>
> > > +#include <linux/irqdomain.h>
> > > +#include <linux/of_irq.h>
> > > +#include <linux/of_platform.h>
> > > +#include <asm/mach/arch.h>
> > > +#include <asm/mach/time.h>
> > > +#include <mach/common.h>
> > > +#include <mach/mx28.h>
> > > +
> > > +static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst
> > > = { +	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart",
> > > NULL), +	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR,
> > > "imx28-fec.0", NULL), +	OF_DEV_AUXDATA("fsl,imx28-fec",
> > > MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
> > 
> > Why do you need the old names?
> 
> To keep align with the old clocks.
> See arch/arm/mach-mxs/clock-mx28.c:
> _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
> _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
> Is there any better way to avoid this?
> 
> > > +	{ /* sentinel */ }
> > > +};
> > > +
> > > +static void __init imx28_init(void)
> > > +{
> > > +	of_platform_populate(NULL, of_default_bus_match_table,
> > > +			     imx28_auxdata_lookup, NULL);
> > > +}
> > > +
> > > +static const struct of_device_id icoll_of_match[] __initconst = {
> > > +	{ .compatible = "fsl,imx28-icoll", },
> > > +	{},
> > > +};
> > > +
> > > +static void __init imx28_dt_init_irq(void)
> > > +{
> > > +	irq_domain_generate_simple(icoll_of_match, MX28_ICOLL_BASE_ADDR, 0);
> > 
> > Please do "proper" domain support for the interrupt controller and use
> > of_irq_init.
> 
> Ok, i will see it.
> 
> For others, will fix them all.
> Thanks for the review.
> 
> Regards
> Dong Aisheng


Best regards,
Marek Vasut


From aisheng.dong at freescale.com  Wed Mar 14 02:55:13 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 14 Mar 2012 14:55:13 +0800
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <201203140658.25854.marek.vasut@gmail.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-3-git-send-email-b29396@freescale.com>
 <201203140658.25854.marek.vasut@gmail.com>
Message-ID: <20120314065512.GB25735@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 01:58:25PM +0800, Marek Vasut wrote:
> Dear Dong Aisheng,
> 
> > 
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
........

> > +static const struct of_device_id mxs_mmc_dt_ids[] = {
> > +	{ .compatible = "fsl,imx23-mmc", .data = NULL, },
> > +	{ .compatible = "fsl,imx28-mmc", .data = NULL, },
> 
> Do you really need two distinct ones here?
> 
Hmm, my original purpose is to put soc difference data in .data
to remove cpu_is_* function calls in the driver later.
Do you think if any issue?

Regards
Dong Aisheng



From viresh.kumar at st.com  Wed Mar 14 03:05:05 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 14 Mar 2012 12:35:05 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <1331650032-15274-1-git-send-email-sr@denx.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
Message-ID: <4F604321.9000204@st.com>


Other than Arnd's comments:

On 3/13/2012 8:17 PM, Stefan Roese wrote:

> diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
> new file mode 100644
> index 0000000..f92d099
> --- /dev/null
> +++ b/arch/arm/boot/dts/spear600-evb.dts
> @@ -0,0 +1,23 @@
> +/*
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *

Just for knowledge, why are above two here? Is including them suggested for
all dts files?

> + * Copyright 2012 Stefan Roese <sr at denx.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +


> diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
> index ff4ae5b..7777f72 100644
> --- a/arch/arm/mach-spear6xx/Kconfig
> +++ b/arch/arm/mach-spear6xx/Kconfig
> @@ -11,6 +11,13 @@ config BOARD_SPEAR600_EVB
>  	help
>  	  Supports ST SPEAr600 Evaluation Board
>  
> +config BOARD_SPEAR600_DT
> +	bool "SPEAr600 generic board configured via device-tree"
> +	select MACH_SPEAR600
> +	select USE_OF
> +	help
> +	  Supports ST SPEAr600 boards configured via the device-tree
> +
>  endmenu
>  
>  config MACH_SPEAR600
> diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
> index cc1a4d8..e2d79b8 100644
> --- a/arch/arm/mach-spear6xx/Makefile
> +++ b/arch/arm/mach-spear6xx/Makefile
> @@ -10,3 +10,4 @@ obj-$(CONFIG_MACH_SPEAR600) += spear600.o
>  
>  # spear600 boards files
>  obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
> +obj-$(CONFIG_BOARD_SPEAR600_DT) += board-dt.o
> diff --git a/arch/arm/mach-spear6xx/board-dt.c b/arch/arm/mach-spear6xx/board-dt.c
> new file mode 100644
> index 0000000..ee4ff33
> --- /dev/null
> +++ b/arch/arm/mach-spear6xx/board-dt.c
> @@ -0,0 +1,75 @@
> +/*
> + * arch/arm/mach-spear6xx/board-dt.c
> + *
> + * Generic SPEAr600 platform support
> + *
> + * Copyright (C) 2009 ST Microelectronics
> + * Viresh Kumar<viresh.kumar at st.com>

                  ^
Thanks for this. Can add space here between r & <.

> + *
> + * Copyright 2012 Stefan Roese <sr at denx.de>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>

keeping header files in alphabetical order makes life easy at
later stages. :)

> +#include <asm/hardware/vic.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach-types.h>
> +#include <mach/generic.h>
> +#include <mach/hardware.h>
> +
> +static struct amba_device *amba_devs[] __initdata = {
> +	&gpio_device[0],
> +	&gpio_device[1],
> +	&gpio_device[2],
> +	&uart_device[0],
> +	&uart_device[1],
> +};
> +
> +static struct platform_device *plat_devs[] __initdata = {
> +};
> +
> +static void __init spear600_dt_init(void)
> +{
> +	unsigned int i;
> +
> +	/* call spear600 machine init function */
> +	spear600_init();
> +
> +	/* Add Platform Devices */
> +	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
> +
> +	/* Add Amba Devices */
> +	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
> +		amba_device_register(amba_devs[i], &iomem_resource);
> +}
> +
> +static const char *spear600_dt_board_compat[] = {
> +	"st,spear600-evb",
> +	NULL
> +};
> +
> +static const struct of_device_id vic_of_match[] __initconst = {
> +	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
> +	{ /* Sentinel */ }
> +};
> +
> +static void __init spear6xx_dt_init_irq(void)
> +{
> +	of_irq_init(vic_of_match);
> +}
> +

What about adding this routine in vic.c file, which can then be used 
by all platforms, instead of replicating this code.

> +DT_MACHINE_START(SPEAR600_DT, "ST-SPEAR600-DT")

It looks this is not a generic file for all boards, but for a
single board? And that would be evb only?

If above is true, we may name this file and internal stuff more
appropriately.

> +	.map_io		=	spear6xx_map_io,
> +	.init_irq	=	spear6xx_dt_init_irq,
> +	.handle_irq	=	vic_handle_irq,
> +	.timer		=	&spear6xx_timer,
> +	.init_machine	=	spear600_dt_init,
> +	.restart	=	spear_restart,
> +	.dt_compat	=	spear600_dt_board_compat,
> +MACHINE_END

Thanks for the patch. :)

-- 
viresh


From kgene.kim at samsung.com  Wed Mar 14 03:06:26 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 00:06:26 -0700
Subject: [PATCH v3 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and
 EXYNOS5
In-Reply-To: <201203131613.10620.arnd@arndb.de>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <1331652643-12626-6-git-send-email-kgene.kim@samsung.com>
 <201203131613.10620.arnd@arndb.de>
Message-ID: <4F604372.3040507@samsung.com>

On 03/13/12 09:13, Arnd Bergmann wrote:
> On Tuesday 13 March 2012, Kukjin Kim wrote:
>> Actually, the base address of uart is different between EXYNOS4
>> and EXYNOS5 and this patch enables to support uart for EXYNOS4
>> and EXYNOS5 SoCs at runtime.
>
> Can you explain why this patch is still needed? The exynos5250_dt_map_io
> function does not call s3c24xx_init_uarts() at all, so it seems that most
> of this patch just adds dead code that would only be needed for the non-dt
> case.
>
Yes, as you said, dt can support uart without most of this changes so we 
can drop adding/setup platform devices for uart here. But I thought 
non-dt exynos4 supporting is still available in mach-exynos/ and 
actually it is used for many product now and exynos5 can be selected for 
single zImage without CONFIG_OF. Even though we will move to only 
supporting dt world in mach-exynos/ for all of EXYNOS SoCs in the near 
future. So would be removed it when non-dt exynos4 does not support.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From thierry.reding at avionic-design.de  Wed Mar 14 03:07:28 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 08:07:28 +0100
Subject: [PATCH 2/7] of: add clock providers
In-Reply-To: <1331680947-29861-3-git-send-email-robherring2@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
 <1331680947-29861-3-git-send-email-robherring2@gmail.com>
Message-ID: <20120314070728.GC2659@avionic-0098.mockup.avionic-design.de>

* Rob Herring wrote:
> diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
[...]
> +clock-output-names: Recommended to be a list of strings of clock output signal
> +		    names indexed by the first cell in the clock specifier.
> +		    However, the meaning of clock-output-name is domain

"clock-output-names"?

> +		    specific to the clock provider, and is only provided to
> +		    encourage using the same meaning for the majority of clock
> +		    providers.  This format may not work for clock providers
> +		    using a complex clock specifier format.  In those cases it
> +		    is recommended to omit this property and create a binding
> +		    specific names property.
> +
> +		    Clock consumer nodes must never directly reference
> +		    the provider's clock-output-name property.

Ditto.

[...]
> diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.txt b/Documentation/devicetree/bindings/clock/fixed-clock.txt
> new file mode 100644
> index 0000000..9a75342
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/fixed-clock.txt
> @@ -0,0 +1,21 @@
> +Binding for simple fixed-rate clock sources.
> +
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/fixed-clock.txt

This document references itself.

Thierry
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From kgene.kim at samsung.com  Wed Mar 14 03:08:17 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 00:08:17 -0700
Subject: [PATCH v3 00/12] ARM: EXYNOS: add support new EXYNOS5250
In-Reply-To: <20120314035728.GC2531@quad.lixom.net>
References: <1331652643-12626-1-git-send-email-kgene.kim@samsung.com>
 <201203131622.09048.arnd@arndb.de> <20120314035728.GC2531@quad.lixom.net>
Message-ID: <4F6043E1.2090507@samsung.com>

On 03/13/12 20:57, Olof Johansson wrote:
> On Tue, Mar 13, 2012 at 04:22:08PM +0000, Arnd Bergmann wrote:
>> On Tuesday 13 March 2012, Kukjin Kim wrote:
>>>
>>> This patch adds support EXYNOS5250 SoC which has two A15 cores
>>> can be used on mobile and tablet devices.
>>
>> Looks basically ok to me. I've commented on patches 5 and 9 and
>> in both cases, I would either like to see the patch get dropped
>> or the changeset description expanded to give a good explanation
>> why the change is actually needed.
>
> Agree, looks quite reasonable. I had a few nits as well but nothing
> major.
>
Hi Arnd, Olof,

Thank you for kindly comments on this.
Let me address comments from you and re-submit in a couple of hours.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From marek.vasut at gmail.com  Wed Mar 14 03:09:22 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 14 Mar 2012 08:09:22 +0100
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <20120314065512.GB25735@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <201203140658.25854.marek.vasut@gmail.com>
 <20120314065512.GB25735@shlinux2.ap.freescale.net>
Message-ID: <201203140809.22676.marek.vasut@gmail.com>

Dear Dong Aisheng,

> On Wed, Mar 14, 2012 at 01:58:25PM +0800, Marek Vasut wrote:
> > Dear Dong Aisheng,
> > 
> > > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> 
> ........
> 
> > > +static const struct of_device_id mxs_mmc_dt_ids[] = {
> > > +	{ .compatible = "fsl,imx23-mmc", .data = NULL, },
> > > +	{ .compatible = "fsl,imx28-mmc", .data = NULL, },
> > 
> > Do you really need two distinct ones here?
> 
> Hmm, my original purpose is to put soc difference data in .data
> to remove cpu_is_* function calls in the driver later.
> Do you think if any issue?
> 

Well, what's the difference between the interfaces on mx233 and mx28? Is it 
something that can't be encoded otherwise? I think they're not so different.

Best regards,
Marek Vasut


From viresh.kumar at st.com  Wed Mar 14 03:08:48 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 14 Mar 2012 12:38:48 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203131644.12048.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203131644.12048.arnd@arndb.de>
Message-ID: <4F604400.1040805@st.com>

On 3/13/2012 10:14 PM, Arnd Bergmann wrote:
> I think you should add all the code from this file to spear6xx.c instead
> of adding a new file. We can then delete the spear600.c and spear600_evb.c
> files once the DT support has matured.

But what if have another board in future, and this is what Stefan is going
to do soon, as they have another board.

So we may actually move this code to spear600_evb.c instead.

Sorry for any bad suggestions, i am new to DT. :)

-- 
viresh


From haojian.zhuang at gmail.com  Wed Mar 14 03:11:16 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 15:11:16 +0800
Subject: [PATCH 3/4] ARM: create a common IOMEM definition
In-Reply-To: <1331500100-31351-4-git-send-email-robherring2@gmail.com>
References: <1331500100-31351-1-git-send-email-robherring2@gmail.com>
 <1331500100-31351-4-git-send-email-robherring2@gmail.com>
Message-ID: <CAN1soZwAq8yDc2ka8hPUme9WM-fw4XRV6bAVEabgndFLA1fmoQ@mail.gmail.com>

On Mon, Mar 12, 2012 at 5:08 AM, Rob Herring <robherring2 at gmail.com> wrote:
> From: Rob Herring <rob.herring at calxeda.com>
>
> Several platforms create IOMEM defines for casting to 'void __iomem *',
> and other platforms are incorrectly using __io() macro for the same
> purpose. This creates a common definition and removes all the platform
> specific versions. Rather than try to make linux/io.h and asm/io.h
> assembly safe, the assembly version of IOMEM is moved into
> asm/assembler.h.
>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
>
> ?arch/arm/mach-mmp/include/mach/addr-map.h ? ? ? | ? ?6 ------

Acked-by: Haojian Zhuang <haojian.zhuang at gmail.com>


From s.hauer at pengutronix.de  Wed Mar 14 03:13:07 2012
From: s.hauer at pengutronix.de (s.hauer at pengutronix.de)
Date: Wed, 14 Mar 2012 08:13:07 +0100
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <201203140809.22676.marek.vasut@gmail.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <201203140658.25854.marek.vasut@gmail.com>
 <20120314065512.GB25735@shlinux2.ap.freescale.net>
 <201203140809.22676.marek.vasut@gmail.com>
Message-ID: <20120314071307.GK3852@pengutronix.de>

On Wed, Mar 14, 2012 at 08:09:22AM +0100, Marek Vasut wrote:
> Dear Dong Aisheng,
> 
> > On Wed, Mar 14, 2012 at 01:58:25PM +0800, Marek Vasut wrote:
> > > Dear Dong Aisheng,
> > > 
> > > > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > ........
> > 
> > > > +static const struct of_device_id mxs_mmc_dt_ids[] = {
> > > > +	{ .compatible = "fsl,imx23-mmc", .data = NULL, },
> > > > +	{ .compatible = "fsl,imx28-mmc", .data = NULL, },
> > > 
> > > Do you really need two distinct ones here?
> > 
> > Hmm, my original purpose is to put soc difference data in .data
> > to remove cpu_is_* function calls in the driver later.
> > Do you think if any issue?
> > 
> 
> Well, what's the difference between the interfaces on mx233 and mx28? Is it 
> something that can't be encoded otherwise? I think they're not so different.

They differ in the register layout. Matching two different compatible
strings is the right way here I think.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From sr at denx.de  Wed Mar 14 03:20:18 2012
From: sr at denx.de (Stefan Roese)
Date: Wed, 14 Mar 2012 08:20:18 +0100
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <4F604321.9000204@st.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <4F604321.9000204@st.com>
Message-ID: <201203140820.18461.sr@denx.de>

On Wednesday 14 March 2012 08:05:05 Viresh Kumar wrote:
> Other than Arnd's comments:
> 
> On 3/13/2012 8:17 PM, Stefan Roese wrote:
> > diff --git a/arch/arm/boot/dts/spear600-evb.dts
> > b/arch/arm/boot/dts/spear600-evb.dts new file mode 100644
> > index 0000000..f92d099
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/spear600-evb.dts
> > @@ -0,0 +1,23 @@
> > +/*
> > + * Copyright 2011 Freescale Semiconductor, Inc.
> > + * Copyright 2011 Linaro Ltd.
> > + *
> 
> Just for knowledge, why are above two here? Is including them suggested for
> all dts files?

I cloned this file from another dtsi file, where those copyright lines were 
present. Not sure if I need to preserve them in the new file.
 
> > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > 
> > 
> > diff --git a/arch/arm/mach-spear6xx/Kconfig
> > b/arch/arm/mach-spear6xx/Kconfig index ff4ae5b..7777f72 100644
> > --- a/arch/arm/mach-spear6xx/Kconfig
> > +++ b/arch/arm/mach-spear6xx/Kconfig
> > @@ -11,6 +11,13 @@ config BOARD_SPEAR600_EVB
> > 
> >  	help
> >  	
> >  	  Supports ST SPEAr600 Evaluation Board
> > 
> > +config BOARD_SPEAR600_DT
> > +	bool "SPEAr600 generic board configured via device-tree"
> > +	select MACH_SPEAR600
> > +	select USE_OF
> > +	help
> > +	  Supports ST SPEAr600 boards configured via the device-tree
> > +
> > 
> >  endmenu
> >  
> >  config MACH_SPEAR600
> > 
> > diff --git a/arch/arm/mach-spear6xx/Makefile
> > b/arch/arm/mach-spear6xx/Makefile index cc1a4d8..e2d79b8 100644
> > --- a/arch/arm/mach-spear6xx/Makefile
> > +++ b/arch/arm/mach-spear6xx/Makefile
> > @@ -10,3 +10,4 @@ obj-$(CONFIG_MACH_SPEAR600) += spear600.o
> > 
> >  # spear600 boards files
> >  obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
> > 
> > +obj-$(CONFIG_BOARD_SPEAR600_DT) += board-dt.o
> > diff --git a/arch/arm/mach-spear6xx/board-dt.c
> > b/arch/arm/mach-spear6xx/board-dt.c new file mode 100644
> > index 0000000..ee4ff33
> > --- /dev/null
> > +++ b/arch/arm/mach-spear6xx/board-dt.c
> > @@ -0,0 +1,75 @@
> > +/*
> > + * arch/arm/mach-spear6xx/board-dt.c
> > + *
> > + * Generic SPEAr600 platform support
> > + *
> > + * Copyright (C) 2009 ST Microelectronics
> > + * Viresh Kumar<viresh.kumar at st.com>
> 
>                   ^
> Thanks for this. Can add space here between r & <.

Okay.
 
> > + *
> > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > + *
> > + * This file is licensed under the terms of the GNU General Public
> > + * License version 2. This program is licensed "as is" without any
> > + * warranty of any kind, whether express or implied.
> > + */
> > +
> > +#include <linux/of.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/of_address.h>
> 
> keeping header files in alphabetical order makes life easy at
> later stages. :)

Yes.
 
> > +#include <asm/hardware/vic.h>
> > +#include <asm/mach/arch.h>
> > +#include <asm/mach-types.h>
> > +#include <mach/generic.h>
> > +#include <mach/hardware.h>
> > +
> > +static struct amba_device *amba_devs[] __initdata = {
> > +	&gpio_device[0],
> > +	&gpio_device[1],
> > +	&gpio_device[2],
> > +	&uart_device[0],
> > +	&uart_device[1],
> > +};
> > +
> > +static struct platform_device *plat_devs[] __initdata = {
> > +};
> > +
> > +static void __init spear600_dt_init(void)
> > +{
> > +	unsigned int i;
> > +
> > +	/* call spear600 machine init function */
> > +	spear600_init();
> > +
> > +	/* Add Platform Devices */
> > +	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
> > +
> > +	/* Add Amba Devices */
> > +	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
> > +		amba_device_register(amba_devs[i], &iomem_resource);
> > +}
> > +
> > +static const char *spear600_dt_board_compat[] = {
> > +	"st,spear600-evb",
> > +	NULL
> > +};
> > +
> > +static const struct of_device_id vic_of_match[] __initconst = {
> > +	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
> > +	{ /* Sentinel */ }
> > +};
> > +
> > +static void __init spear6xx_dt_init_irq(void)
> > +{
> > +	of_irq_init(vic_of_match);
> > +}
> > +
> 
> What about adding this routine in vic.c file, which can then be used
> by all platforms, instead of replicating this code.

Let me check this.
 
> > +DT_MACHINE_START(SPEAR600_DT, "ST-SPEAR600-DT")
> 
> It looks this is not a generic file for all boards, but for a
> single board? And that would be evb only?
> 
> If above is true, we may name this file and internal stuff more
> appropriately.

This file should be a generic SPEAr600 file. Not specific for the EVB. Future 
SPEAr600 board can also use this file. The differences between the boards 
should be encapsulated in the board specific dts files.
 
Thanks,
Stefan


From aisheng.dong at freescale.com  Wed Mar 14 03:26:04 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 14 Mar 2012 15:26:04 +0800
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <201203140809.22676.marek.vasut@gmail.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <201203140658.25854.marek.vasut@gmail.com>
 <20120314065512.GB25735@shlinux2.ap.freescale.net>
 <201203140809.22676.marek.vasut@gmail.com>
Message-ID: <20120314072603.GC8494@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 08:09:22AM +0100, Marek Vasut wrote:
> Dear Dong Aisheng,
> 
> > On Wed, Mar 14, 2012 at 01:58:25PM +0800, Marek Vasut wrote:
> > > Dear Dong Aisheng,
> > > 
> > > > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > ........
> > 
> > > > +static const struct of_device_id mxs_mmc_dt_ids[] = {
> > > > +	{ .compatible = "fsl,imx23-mmc", .data = NULL, },
> > > > +	{ .compatible = "fsl,imx28-mmc", .data = NULL, },
> > > 
> > > Do you really need two distinct ones here?
> > 
> > Hmm, my original purpose is to put soc difference data in .data
> > to remove cpu_is_* function calls in the driver later.
> > Do you think if any issue?
> > 
> 
> Well, what's the difference between the interfaces on mx233 and mx28? Is it 
> something that can't be encoded otherwise? I think they're not so different.
> 
Not much difference except the one register offset and ip version.
See:
#define SSP_VERSION_LATEST      4
#define ssp_is_old()            (host->version < SSP_VERSION_LATEST)
..
#define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130)
The ip version can be handled in driver, but for offset...
it depends on cpu_is_* macro.
Putting the HW_SSP_VERSION offset difference in .data can eliminate the need
of cpu_is_*.

Despite of that, since they're two devices,
i guess it's ok to put two compatible string there, right?
Or you thought just put one as below?
{ .compatible = "fsl,mxs-mmc", .data = NULL, },

Regards
Dong Aisheng



From aisheng.dong at freescale.com  Wed Mar 14 03:34:55 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 14 Mar 2012 15:34:55 +0800
Subject: [PATCH v1 0/5] dt: add basic imx28 support
In-Reply-To: <201203140701.07111.marek.vasut@gmail.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <201203140701.07111.marek.vasut@gmail.com>
Message-ID: <20120314073454.GD8494@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 07:01:06AM +0100, Marek Vasut wrote:
> Dear Dong Aisheng,
> 
> > This patch series adds basic imx28 dt support including fec, mmc and dma.
> > 
> > Tested on mx28evk.
> > 
> > TODO:
> > Convert the remaining devices to support dt.
> > mxs-auart, mxs-gpio, i2c, flexcan, saif, rtc, pwm, fb.
> > 
> > Dong Aisheng (5):
> >   ARM: imx28: add basic dt support
> >   mmc: mxs-mmc: add dt probe support
> >   ARM: imx28evk: add mmc dt support
> >   dma: mxs-dma: add dt probe support
> >   ARM: mxs: add mxs dma dt support
> > 
> Can you keep me in Cc on new versions of these patches? Thanks!
> 
Of course yes.
Thanks for your review.

Regards
Dong Aisheng



From plagnioj at jcrosoft.com  Wed Mar 14 03:23:43 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 14 Mar 2012 08:23:43 +0100
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <1331628428-24017-3-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-3-git-send-email-b29396@freescale.com>
Message-ID: <20120314072343.GG18320@game.jcrosoft.org>

On 16:47 Tue 13 Mar     , Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> 
> ---
> The patch is still using a private way for dma part binding
> since the common dma binding is still under discussion.
> http://www.spinics.net/lists/linux-omap/msg65528.html
> 
> Will update to use common dma binding when it hits mainline.
> ---
>  .../devicetree/bindings/mmc/fsl-mxs-mmc.txt        |   23 ++++++
>  drivers/mmc/host/mxs-mmc.c                         |   82 +++++++++++++++++++-
>  2 files changed, 102 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> new file mode 100644
> index 0000000..adc1142
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> @@ -0,0 +1,23 @@
> +* FREESCALE MXS MMC peripheral
> +
> +Required properties:
> +- compatible : Should be "fsl,<chip>-mmc"
> +- reg : Should contain registers location and length
> +- interrupts : Should contain interrupt.
> +  The format is <irq_err irq_dma>.
> +- dma_channel: Should contain the dma channel it uses
> +
> +Optional properties:
> +- wp-gpios : Specify GPIOs for write protection
> +- slot-4bit: Specify 4 bit mode support
> +- slot-8bit: Specify 8 bit and 4 bit mode support
> +
> +Examples:
> +mmc1: ssp at 80010000 {
> +	compatible = "fsl,imx28-mmc";
> +	reg = <0x80010000 2000>;
> +	/* <irq_err irq_dma> */
> +	interrupts = <96 82>;
> +	dma_channel = <0>;
> +	slot-8bit;
> +};
> diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
> index 382c835..6cf2d17 100644
> --- a/drivers/mmc/host/mxs-mmc.c
> +++ b/drivers/mmc/host/mxs-mmc.c
> @@ -38,6 +38,10 @@
>  #include <linux/gpio.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
> +#include <linux/slab.h>
>  
>  #include <mach/mxs.h>
>  #include <mach/common.h>
> @@ -673,17 +677,79 @@ static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
>  	return true;
>  }
>  
> +#ifdef CONFIG_OF
> +static struct resource * __devinit mxs_mmc_get_of_dmares(
> +				struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct resource *dmares;
> +	int ret;
> +
> +	if (!np)
> +		return NULL;
> +
> +	dmares = kzalloc(sizeof(*dmares), GFP_KERNEL);
> +	dmares->flags = IORESOURCE_DMA;
> +	ret = of_property_read_u32(np, "dma_channel", &dmares->start);
> +	if (ret) {
> +		dev_err(&pdev->dev, "unable to get dmares from dt\n");
> +		return NULL;
> +	}
> +	dmares->end = dmares->start;
> +
> +	return dmares;
> +}
> +
> +static int __devinit mxs_mmc_get_of_property(struct platform_device *pdev,
> +				struct mxs_mmc_platform_data **ppdata)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct mxs_mmc_platform_data *pdata = *ppdata;
> +
> +	if (!np)
> +		return -ENODEV;
> +
> +	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> +
> +	if (of_get_property(np, "slot-8bit", NULL))
> +		pdata->flags |= SLOTF_8_BIT_CAPABLE;
> +
> +	if (of_get_property(np, "slot-4bit", NULL))
> +		pdata->flags |= SLOTF_4_BIT_CAPABLE;
it will conflit if both binding are set use a number instead

Best Regards,
J.


From sr at denx.de  Wed Mar 14 03:40:17 2012
From: sr at denx.de (Stefan Roese)
Date: Wed, 14 Mar 2012 08:40:17 +0100
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203131644.12048.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203131644.12048.arnd@arndb.de>
Message-ID: <201203140840.18333.sr@denx.de>

Hi Arnd,

On Tuesday 13 March 2012 17:44:11 Arnd Bergmann wrote:
> On Tuesday 13 March 2012, Stefan Roese wrote:
> > This patch adds a generic target for SPEAr600 board that can be
> > configured via the device-tree. Currently only interrupts are
> > configured via device-tree. Other peripheral devices (e.g.
> > ethernet, I2C, SMI flash, FSMC NAND flash etc) will follow in
> > later patches.
> > 
> > Only the spear600-evb is currently supported. Other SPEAr600
> > based boards will follow later.
> > 
> > Signed-off-by: Stefan Roese <sr at denx.de>
> > Cc: Viresh Kumar <viresh.kumar at st.com>
> 
> Hi Stefan,
> 
> This is very cool, welcome onboard for the DT conversion with spear600!
> 
> > +static struct amba_device *amba_devs[] __initdata = {
> > +	&gpio_device[0],
> > +	&gpio_device[1],
> > +	&gpio_device[2],
> > +	&uart_device[0],
> > +	&uart_device[1],
> > +};
> 
> I would suggest you convert these to DT next so you can remove the
> amba_devs list. Which devices are these? If they are pl061 and
> pl010/pl011, the binding should be really easy to do.

Yes. I really wanted to do that. But from a quick look at the pl011 driver 
(drivers/tty/serial/amba-pl011.c), this driver doesn't support DT probing. I 
might have missed something here though. And ideas?
 
> > +static struct platform_device *plat_devs[] __initdata = {
> > +};
> 
> This could be dropped right away, because you would never
> add anything here.

Yes.
 
> > +static void __init spear600_dt_init(void)
> > +{
> > +	unsigned int i;
> > +
> > +	/* call spear600 machine init function */
> > +	spear600_init();
> 
> spear600_init currently is an empty function, I think you can
> drop that one too.

Okay.
 
> > +	/* Add Platform Devices */
> > +	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
> > +
> > +	/* Add Amba Devices */
> > +	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
> > +		amba_device_register(amba_devs[i], &iomem_resource);
> 
> So although all of this can go away soon, you will have to
> add a call to of_platform_populate() here in order to add the
> devices from the device tree.

Okay.

> > +}
> > +
> > +static const char *spear600_dt_board_compat[] = {
> > +	"st,spear600-evb",
> > +	NULL
> > +};
> > +
> > +static const struct of_device_id vic_of_match[] __initconst = {
> > +	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
> > +	{ /* Sentinel */ }
> > +};
> > +
> > +static void __init spear6xx_dt_init_irq(void)
> > +{
> > +	of_irq_init(vic_of_match);
> > +}
> > +
> > +DT_MACHINE_START(SPEAR600_DT, "ST-SPEAR600-DT")
> > +	.map_io		=	spear6xx_map_io,
> > +	.init_irq	=	spear6xx_dt_init_irq,
> > +	.handle_irq	=	vic_handle_irq,
> > +	.timer		=	&spear6xx_timer,
> > +	.init_machine	=	spear600_dt_init,
> > +	.restart	=	spear_restart,
> > +	.dt_compat	=	spear600_dt_board_compat,
> > +MACHINE_END
> 
> Since there is only one upstream board file and that is for the same board,
> we can soon collapse all of it into the base platform support.
> 
> I think you should add all the code from this file to spear6xx.c instead
> of adding a new file. We can then delete the spear600.c and spear600_evb.c
> files once the DT support has matured.

Sounds like a plan. I'll rework the patch soon.

Thanks,
Stefan


From haojian.zhuang at gmail.com  Wed Mar 14 03:40:54 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 15:40:54 +0800
Subject: [PATCH] pxa/hx4700: Reduce sleep mode power consumption by 35%
In-Reply-To: <1331417108.99129.YahooMailClassic@web29004.mail.ird.yahoo.com>
References: <20120310182144.GA20013@n2100.arm.linux.org.uk>
 <1331417108.99129.YahooMailClassic@web29004.mail.ird.yahoo.com>
Message-ID: <CAN1soZy0nfSNA71a0SM1sfBMvzboOV+P4Ymd4YtsyphNCdiVbw@mail.gmail.com>

On Sun, Mar 11, 2012 at 6:05 AM, Paul Parsons <lost.distance at yahoo.com> wrote:
> --- On Sat, 10/3/12, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
>> >? ??? /* BTUART */
>> >? ??? GPIO42_BTUART_RXD,
>> > -??? GPIO43_BTUART_TXD,
>> > +??? GPIO43_GPIO | MFP_AF2 |
>> MFP_LPM_DRIVE_LOW,
>>
>> I don't believe that's right.
>>
>> This expands to:
>>
>> ??? MFP_CFG_IN(GPIO43, AF0) | MFP_AF2 |
>> MFP_LPM_DRIVE_LOW
>>
>> and:
>>
>> ??? (MFP_CFG_DEFAULT & ~(MFP_AF_MASK |
>> MFP_DIR_MASK)) |
>> ??? (MFP_PIN(MFP_PIN_GPIO43) | MFP_AF0 |
>> MFP_DIR_IN)
>> ??? | MFP_AF2 | MFP_LPM_DRIVE_LOW
>>
>> Note the presence of both MFP_AF2 and MFP_AF0 in there.
>>
>> The default for GPIO43_BTUART_TXD is:
>>
>> ??? MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
>>
>> and I'd suggest defining a new GPIO43_BTUART_TXD_LPM_LOW to
>> cover your
>> case.
>
> It wasn't right but it evaluated to the correct value because MFP_AF0 = 0.
> What I intended was: MFP_PIN_GPIO43 | MFP_AF2 | MFP_LPM_DRIVE_LOW
> But I'll add the new values to <mach/mfp-pxa27x.h> if that's preferable.
>
Yes, you can do it. It's prefer to append new values in <mfp-pxa27x.h>.


From plagnioj at jcrosoft.com  Wed Mar 14 03:28:39 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 14 Mar 2012 08:28:39 +0100
Subject: [PATCH v1 3/5] ARM: imx28evk: add mmc dt support
In-Reply-To: <1331628428-24017-4-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-4-git-send-email-b29396@freescale.com>
Message-ID: <20120314072839.GH18320@game.jcrosoft.org>

On 16:47 Tue 13 Mar     , Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
>  arch/arm/boot/dts/imx28-evk.dts |   14 ++++++++++++++
>  arch/arm/boot/dts/imx28.dtsi    |   33 +++++++++++++++++++++++++++++++++
>  arch/arm/mach-mxs/imx28-dt.c    |    2 ++
>  3 files changed, 49 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
> index 9758dc4..61350ab 100644
> --- a/arch/arm/boot/dts/imx28-evk.dts
> +++ b/arch/arm/boot/dts/imx28-evk.dts
> @@ -21,6 +21,20 @@
>  		reg = <0x40000000 0x08000000>;
>  	};
>  
> +        apb at 80000000 {
> +                apbh at 80000000 {
> +			mmc1: ssp at 80010000 {
> +				slot-8bit;
> +				status = "okay";
> +			};
> +
> +			mmc2: ssp at 80012000 {
> +				slot-8bit;
> +				status = "okay";
> +			};
> +		};
> +	};
> +
>  	ahb at 80080000 {
>  		fec at 800f0000 {
>  			phy-mode = "rmii";
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index acf0dab..71c7bfb 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -46,6 +46,39 @@
>  				#interrupt-cells = <1>;
>  				reg = <0x80000000 0x2000>;
>  			};
> +
> +			ssp at 80010000 {
> +				compatible = "fsl,imx28-mmc";
> +				reg = <0x80010000 2000>;
> +				/* <irq_err irq_dma> */
> +				interrupts = <96 82>;
> +				dma_channel = <0>;
> +				status = "disabled";
> +			};
> +
> +			ssp at 80012000 {
> +				compatible = "fsl,imx28-mmc";
> +				reg = <0x80012000 2000>;
> +				interrupts = <97 83>;
> +				dma_channel = <1>;
> +				status = "disabled";
> +			};
> +
> +			ssp at 80014000 {
> +				compatible = "fsl,imx28-mmc";
> +				reg = <0x80014000 2000>;
> +				interrupts = <98 84>;
> +				dma_channel = <2>;
> +				status = "disabled";
> +			};
> +
> +			ssp at 80016000 {
> +				compatible = "fsl,imx28-mmc";
> +				reg = <0x80016000 2000>;
> +				interrupts = <99 85>;
> +				dma_channel = <3>;
> +				status = "disabled";
> +			};
>  		};
>  
>  		apbx at 80040000 {
> diff --git a/arch/arm/mach-mxs/imx28-dt.c b/arch/arm/mach-mxs/imx28-dt.c
> index 78d1129..429b88e 100644
> --- a/arch/arm/mach-mxs/imx28-dt.c
> +++ b/arch/arm/mach-mxs/imx28-dt.c
> @@ -23,6 +23,8 @@ static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
>  	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP0_BASE_ADDR, "mxs-mmc.0", NULL),
> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP1_BASE_ADDR, "mxs-mmc.1", NULL),
do we really need to continue to add OF_DEV_AUXDATA

instead add a clkdev entry

IIRC OF_DEV_AUXDATA was a temporary solution, we need to stop to use it more
and more

Best Reards,
J.


From plagnioj at jcrosoft.com  Wed Mar 14 03:30:35 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 14 Mar 2012 08:30:35 +0100
Subject: [PATCH v1 3/5] ARM: imx28evk: add mmc dt support
In-Reply-To: <4F5F879E.4030407@gmail.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-4-git-send-email-b29396@freescale.com>
 <4F5F5C22.1080506@gmail.com>
 <20120313165214.GO26642@pengutronix.de>
 <4F5F879E.4030407@gmail.com>
Message-ID: <20120314073035.GI18320@game.jcrosoft.org>

On 12:45 Tue 13 Mar     , Rob Herring wrote:
> On 03/13/2012 11:52 AM, Sascha Hauer wrote:
> > On Tue, Mar 13, 2012 at 09:39:30AM -0500, Rob Herring wrote:
> >> On 03/13/2012 03:47 AM, Dong Aisheng wrote:
> >>> From: Dong Aisheng <dong.aisheng at linaro.org>
> >>>
> >>> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> >>> ---
> >>>  arch/arm/boot/dts/imx28-evk.dts |   14 ++++++++++++++
> >>>  arch/arm/boot/dts/imx28.dtsi    |   33 +++++++++++++++++++++++++++++++++
> >>>  arch/arm/mach-mxs/imx28-dt.c    |    2 ++
> >>>  3 files changed, 49 insertions(+), 0 deletions(-)
> >>
> >> snip
> >>
> >>> diff --git a/arch/arm/mach-mxs/imx28-dt.c b/arch/arm/mach-mxs/imx28-dt.c
> >>> index 78d1129..429b88e 100644
> >>> --- a/arch/arm/mach-mxs/imx28-dt.c
> >>> +++ b/arch/arm/mach-mxs/imx28-dt.c
> >>> @@ -23,6 +23,8 @@ static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
> >>>  	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
> >>>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
> >>>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
> >>> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP0_BASE_ADDR, "mxs-mmc.0", NULL),
> >>> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP1_BASE_ADDR, "mxs-mmc.1", NULL),
> >>
> >> Why is this needed?
> > 
> > These are needed for the drivers which have still the mxs-mmc.* names
> > to find their clocks. Alternatively we could also add the appropriate
> > clocks to the clock file. Don't know if that's better though.
> 
> Ah, yes I should have known that... If clk lookup is all that's needed,
> I'd suggest adding the necessary clk lookups either here or in the clock
> code. Not much difference, but at least it removes the use of
> *_BASE_ADDR defines.
Agreed we do this on AT91

Best Regards,
J.


From javier.martin at vista-silicon.com  Wed Mar 14 03:43:45 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Wed, 14 Mar 2012 08:43:45 +0100
Subject: [PATCH v3 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <20120309174411.GI3852@pengutronix.de>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
 <20120309174411.GI3852@pengutronix.de>
Message-ID: <CACKLOr0XzE0PZk=k5xQQvOA_5dfBk1mYDVyKCep36=3w7ugwWg@mail.gmail.com>

On 9 March 2012 18:44, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Fri, Mar 09, 2012 at 04:20:36PM +0100, Javier Martin wrote:
>> The following series have to be applied on top of the following patches:
>> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
>> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
>>
>> As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
>> is deprecated and no new patches are accepted for it.
>>
>> This series merges this code into the imx-dma.c dmaengine driver.
>
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
>

Vinod,
I think with Sascha's ack, this series is ready to be merged. It's
quite important for us that it makes it for 3.4.

Please, don't forget the following patch too, which is meant to be
applied on top of this series:

[PATCH] dmaengine: i.MX: Add support for interleaved transfers.

Regards.
-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From b32955 at freescale.com  Wed Mar 14 03:54:37 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 14 Mar 2012 15:54:37 +0800
Subject: [PATCH v1 4/5] dma: mxs-dma: add dt probe support
In-Reply-To: <1331628428-24017-5-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-5-git-send-email-b29396@freescale.com>
Message-ID: <4F604EBD.7060400@freescale.com>

Hi Aisheng:
> From: Dong Aisheng<dong.aisheng at linaro.org>
>
> Signed-off-by: Dong Aisheng<dong.aisheng at linaro.org>
> ---
>   .../devicetree/bindings/dma/fsl-mxs-dma.txt        |   17 ++++++++
>   drivers/dma/mxs-dma.c                              |   44 +++++++++++++------
>   2 files changed, 47 insertions(+), 14 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
> new file mode 100644
> index 0000000..cfa1730
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
> @@ -0,0 +1,17 @@
> +* Freescale MXS DMA
> +
> +Required properties:
> +- compatible : Should be "fsl,mxs-dma-apbh" or "fsl,mxs-dma-apbx"
> +- reg : Should contain registers location and length
> +
> +Examples:
> +
> +dma-apbh at 80004000 {
> +	compatible = "fsl,mxs-dma-apbh";
> +	reg =<0x80004000 2000>;
> +};
> +
> +dma-apbx at 80024000 {
> +	compatible = "fsl,mxs-dma-apbx";
> +	reg =<0x80024000 2000>;
> +};
> diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
> index b06cd4c..45e8d46 100644
> --- a/drivers/dma/mxs-dma.c
> +++ b/drivers/dma/mxs-dma.c
> @@ -22,6 +22,9 @@
>   #include<linux/platform_device.h>
>   #include<linux/dmaengine.h>
>   #include<linux/delay.h>
> +#include<linux/module.h>
> +#include<linux/of.h>
> +#include<linux/of_device.h>
>
>   #include<asm/irq.h>
>   #include<mach/mxs.h>
> @@ -130,6 +133,25 @@ struct mxs_dma_engine {
>   	struct mxs_dma_chan		mxs_chans[MXS_DMA_CHANNELS];
>   };
>
> +static struct platform_device_id mxs_dma_type[] = {
> +	{
> +		.name = "mxs-dma-apbh",
> +		.driver_data = MXS_DMA_APBH,
> +	}, {
> +		.name = "mxs-dma-apbx",
> +		.driver_data = MXS_DMA_APBX,
> +	}, {
> +		/* end of list */
> +	}
> +};
> +
I think you should use the platform_device_id to distinguish different 
archs.
In the mx6q,  you will meet some compiler error for the macro cpu_is_mx23().

BR
Huang Shijie



> +static const struct of_device_id mxs_dma_dt_ids[] = {
> +	{ .compatible = "fsl,mxs-dma-apbh", .data =&mxs_dma_type[0], },
> +	{ .compatible = "fsl,mxs-dma-apbx", .data =&mxs_dma_type[1], },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
> +
>   static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
>   {
>   	struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
> @@ -587,8 +609,8 @@ err_out:
>
>   static int __init mxs_dma_probe(struct platform_device *pdev)
>   {
> -	const struct platform_device_id *id_entry =
> -				platform_get_device_id(pdev);
> +	const struct platform_device_id *id_entry;
> +	const struct of_device_id *of_id;
>   	struct mxs_dma_engine *mxs_dma;
>   	struct resource *iores;
>   	int ret, i;
> @@ -597,6 +619,11 @@ static int __init mxs_dma_probe(struct platform_device *pdev)
>   	if (!mxs_dma)
>   		return -ENOMEM;
>
> +	of_id = of_match_device(mxs_dma_dt_ids,&pdev->dev);
> +	if (of_id)
> +		id_entry = of_id->data;
> +	else
> +		id_entry = platform_get_device_id(pdev);
>   	mxs_dma->dev_id = id_entry->driver_data;
>
>   	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> @@ -679,21 +706,10 @@ err_request_region:
>   	return ret;
>   }
>
> -static struct platform_device_id mxs_dma_type[] = {
> -	{
> -		.name = "mxs-dma-apbh",
> -		.driver_data = MXS_DMA_APBH,
> -	}, {
> -		.name = "mxs-dma-apbx",
> -		.driver_data = MXS_DMA_APBX,
> -	}, {
> -		/* end of list */
> -	}
> -};
> -
>   static struct platform_driver mxs_dma_driver = {
>   	.driver		= {
>   		.name	= "mxs-dma",
> +		.of_match_table = mxs_dma_dt_ids,
>   	},
>   	.id_table	= mxs_dma_type,
>   };




From shawn.guo at linaro.org  Wed Mar 14 03:55:55 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 14 Mar 2012 15:55:55 +0800
Subject: [PATCH 2/7] of: add clock providers
In-Reply-To: <1331680947-29861-3-git-send-email-robherring2@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
 <1331680947-29861-3-git-send-email-robherring2@gmail.com>
Message-ID: <20120314075553.GE21337@S2101-09.ap.freescale.net>

On Tue, Mar 13, 2012 at 06:22:22PM -0500, Rob Herring wrote:
> From: Grant Likely <grant.likely at secretlab.ca>
> 
> Based on work by Ben Herrenschmidt and Jeremy Kerr, this patch adds an
> of_clk_get function to allow platforms to retrieve clock data from the
> device tree.
> 
> Platform register a provider through of_clk_add_provider, which will be
> called when a device references the provider's OF node for a clock
> reference.
> 
> v3: - Clarified documentation
> 
> v2: - fixed errant ';' causing compile error
>     - Editorial fixes from Shawn Guo
>     - merged in adding lookup to clkdev
>     - changed property names to match established convention. After
>       working with the binding a bit it really made more sense to follow the
>       lead of 'reg', 'gpios' and 'interrupts' by making the input simply
>       'clocks' & 'clock-names' instead of 'clock-input-*', and to only use
>       clock-output* for the producer nodes. (Sorry Shawn, this will mean
>       you need to change some code, but it should be trivial)
>     - Add ability to inherit clocks from parent nodes by using an empty
>       'clock-ranges' property.  Useful for busses.  I could use some feedback
>       on the new property name, 'clock-ranges' doesn't feel right to me.
> 
> Signed-off-by: Grant Likely <grant.likely at secretlab.ca>
> Reviewed-by: Shawn Guo <shawn.guo at freescale.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Sascha Hauer <kernel at pengutronix.de>
> Cc: Mike Turquette <mturquette at ti.com>
> ---
>  .../devicetree/bindings/clock/clock-bindings.txt   |  116 ++++++++++++++
>  .../devicetree/bindings/clock/fixed-clock.txt      |   21 +++
>  drivers/clk/clkdev.c                               |    9 +
>  drivers/of/Kconfig                                 |    6 +
>  drivers/of/Makefile                                |    1 +
>  drivers/of/clock.c                                 |  165 ++++++++++++++++++++
>  include/linux/of_clk.h                             |   37 +++++
>  7 files changed, 355 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/clock-bindings.txt
>  create mode 100644 Documentation/devicetree/bindings/clock/fixed-clock.txt
>  create mode 100644 drivers/of/clock.c
>  create mode 100644 include/linux/of_clk.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
> new file mode 100644
> index 0000000..3cb6746
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
> @@ -0,0 +1,116 @@
> +This binding is a work-in-progress, and are based on some experimental
> +work by benh[1].
> +
> +Sources of clock signal can be represented by any node in the device
> +tree.  Those nodes are designated as clock providers.  Clock consumer
> +nodes use a phandle and clock specifier pair to connect clock provider
> +outputs to clock inputs.  Similar to the gpio specifiers, a clock
> +specifier is an array of one more more cells identifying the clock
> +output on a device.  The length of a clock specifier is defined by the
> +value of a #clock-cells property in the clock provider node.
> +
> +[1] http://patchwork.ozlabs.org/patch/31551/
> +
> +==Clock providers==
> +
> +Required properties:
> +#clock-cells:	   Number of cells in a clock specifier; typically will be
> +		   set to 1
> +

We had a discussion[1] regarding it.

Regards,
Shawn

http://article.gmane.org/gmane.linux.drivers.devicetree/11554


From b32955 at freescale.com  Wed Mar 14 03:58:23 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 14 Mar 2012 15:58:23 +0800
Subject: [PATCH v1 5/5] ARM: mxs: add mxs dma dt support
In-Reply-To: <1331628428-24017-6-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-6-git-send-email-b29396@freescale.com>
Message-ID: <4F604F9F.1070801@freescale.com>

Hi,
> +			dma-apbh at 80004000 {
> +				compatible = "fsl,mxs-dma-apbh";
> +				reg =<0x80004000 2000>;
> +			};
> +
Why you do not add the `interrupt` for the it?
the gpmi-nand needs to parse the interrupt out.

BR
Huang Shijie




From shawn.guo at linaro.org  Wed Mar 14 03:59:42 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 14 Mar 2012 15:59:42 +0800
Subject: [PATCH 4/7] dt/clock: Add handling for fixed clocks and a clock
 node setup iterator
In-Reply-To: <1331680947-29861-5-git-send-email-robherring2@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
 <1331680947-29861-5-git-send-email-robherring2@gmail.com>
Message-ID: <20120314075930.GF21337@S2101-09.ap.freescale.net>

On Tue, Mar 13, 2012 at 06:22:24PM -0500, Rob Herring wrote:
...
> +/**
> + * of_fixed_clk_setup() - Setup function for simple fixed rate clock
> + */
> +void __init of_fixed_clk_setup(struct device_node *node)
> +{
> +	struct clk *clk;
> +	const char *clk_name = node->name;
> +	u32 rate;
> +
> +	if (of_property_read_u32(node, "clock-frequency", &rate))
> +		return;
> +
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
> +	clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate);
> +	if (clk)
> +		of_clk_add_provider(node, of_fixed_clk_get, clk);
> +}

It seems my comment[1] did not get addressed in this post.

Regards,
Shawn

[1] http://article.gmane.org/gmane.linux.drivers.devicetree/10589


From haojian.zhuang at gmail.com  Wed Mar 14 04:03:18 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 16:03:18 +0800
Subject: [PATCH] pxa/hx4700: Remove pcmcia platform_device structure
In-Reply-To: <1331305076.23513.YahooMailClassic@web29009.mail.ird.yahoo.com>
References: <1331305076.23513.YahooMailClassic@web29009.mail.ird.yahoo.com>
Message-ID: <CAN1soZwmLmTgnR+vqQtUyqsivhbuJRdd6YmDgLb5Vi+e5CVAzQ@mail.gmail.com>

On Fri, Mar 9, 2012 at 10:57 PM, Paul Parsons <lost.distance at yahoo.com> wrote:
> The existing pcmcia platform_device structure is not used and is not needed by
> the pending hx4700 PCMCIA/CF support. So let's remove it.
>
> Signed-off-by: Paul Parsons <lost.distance at yahoo.com>

Excuse me to response late. Will hx4700 support PCMCIA driver?


From haojian.zhuang at gmail.com  Wed Mar 14 04:04:56 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 16:04:56 +0800
Subject: [PATCH] pxa/hx4700: Remove pcmcia platform_device structure
In-Reply-To: <CAN1soZwmLmTgnR+vqQtUyqsivhbuJRdd6YmDgLb5Vi+e5CVAzQ@mail.gmail.com>
References: <1331305076.23513.YahooMailClassic@web29009.mail.ird.yahoo.com>
 <CAN1soZwmLmTgnR+vqQtUyqsivhbuJRdd6YmDgLb5Vi+e5CVAzQ@mail.gmail.com>
Message-ID: <CAN1soZyxEQNMVerxnjaLHiQQgW3MQKg1cqKxCqVg7av9oqf4ZA@mail.gmail.com>

On Wed, Mar 14, 2012 at 4:03 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> On Fri, Mar 9, 2012 at 10:57 PM, Paul Parsons <lost.distance at yahoo.com> wrote:
>> The existing pcmcia platform_device structure is not used and is not needed by
>> the pending hx4700 PCMCIA/CF support. So let's remove it.
>>
>> Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
>
> Excuse me to response late. Will hx4700 support PCMCIA driver?

Oh. I missed one patch. Please ignore my comments.


From aisheng.dong at freescale.com  Wed Mar 14 04:09:40 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 14 Mar 2012 16:09:40 +0800
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <20120314072343.GG18320@game.jcrosoft.org>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-3-git-send-email-b29396@freescale.com>
 <20120314072343.GG18320@game.jcrosoft.org>
Message-ID: <20120314080939.GA1180@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 03:23:43PM +0800, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 16:47 Tue 13 Mar     , Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > ---
> > The patch is still using a private way for dma part binding
> > since the common dma binding is still under discussion.
> > http://www.spinics.net/lists/linux-omap/msg65528.html
> > 
> > Will update to use common dma binding when it hits mainline.
> > ---
> >  .../devicetree/bindings/mmc/fsl-mxs-mmc.txt        |   23 ++++++
> >  drivers/mmc/host/mxs-mmc.c                         |   82 +++++++++++++++++++-
> >  2 files changed, 102 insertions(+), 3 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> > new file mode 100644
> > index 0000000..adc1142
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> > @@ -0,0 +1,23 @@
> > +* FREESCALE MXS MMC peripheral
> > +
> > +Required properties:
> > +- compatible : Should be "fsl,<chip>-mmc"
> > +- reg : Should contain registers location and length
> > +- interrupts : Should contain interrupt.
> > +  The format is <irq_err irq_dma>.
> > +- dma_channel: Should contain the dma channel it uses
> > +
> > +Optional properties:
> > +- wp-gpios : Specify GPIOs for write protection
> > +- slot-4bit: Specify 4 bit mode support
> > +- slot-8bit: Specify 8 bit and 4 bit mode support
> > +
> > +Examples:
> > +mmc1: ssp at 80010000 {
> > +	compatible = "fsl,imx28-mmc";
> > +	reg = <0x80010000 2000>;
> > +	/* <irq_err irq_dma> */
> > +	interrupts = <96 82>;
> > +	dma_channel = <0>;
> > +	slot-8bit;
> > +};
> > diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
> > index 382c835..6cf2d17 100644
> > --- a/drivers/mmc/host/mxs-mmc.c
> > +++ b/drivers/mmc/host/mxs-mmc.c
> > @@ -38,6 +38,10 @@
> >  #include <linux/gpio.h>
> >  #include <linux/regulator/consumer.h>
> >  #include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_gpio.h>
> > +#include <linux/slab.h>
> >  
> >  #include <mach/mxs.h>
> >  #include <mach/common.h>
> > @@ -673,17 +677,79 @@ static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
> >  	return true;
> >  }
> >  
> > +#ifdef CONFIG_OF
> > +static struct resource * __devinit mxs_mmc_get_of_dmares(
> > +				struct platform_device *pdev)
> > +{
> > +	struct device_node *np = pdev->dev.of_node;
> > +	struct resource *dmares;
> > +	int ret;
> > +
> > +	if (!np)
> > +		return NULL;
> > +
> > +	dmares = kzalloc(sizeof(*dmares), GFP_KERNEL);
> > +	dmares->flags = IORESOURCE_DMA;
> > +	ret = of_property_read_u32(np, "dma_channel", &dmares->start);
> > +	if (ret) {
> > +		dev_err(&pdev->dev, "unable to get dmares from dt\n");
> > +		return NULL;
> > +	}
> > +	dmares->end = dmares->start;
> > +
> > +	return dmares;
> > +}
> > +
> > +static int __devinit mxs_mmc_get_of_property(struct platform_device *pdev,
> > +				struct mxs_mmc_platform_data **ppdata)
> > +{
> > +	struct device_node *np = pdev->dev.of_node;
> > +	struct mxs_mmc_platform_data *pdata = *ppdata;
> > +
> > +	if (!np)
> > +		return -ENODEV;
> > +
> > +	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> > +
> > +	if (of_get_property(np, "slot-8bit", NULL))
> > +		pdata->flags |= SLOTF_8_BIT_CAPABLE;
> > +
> > +	if (of_get_property(np, "slot-4bit", NULL))
> > +		pdata->flags |= SLOTF_4_BIT_CAPABLE;
> it will conflit if both binding are set use a number instead
> 
Hmm, i did not see conflict, can you explain more?
The "slot-8bit" includes the support for 4bit.(see binding doc)
Even user define them two property in dt by mistake, it does not cause conflict.
See:
if (pdata) {
	if (pdata->flags & SLOTF_8_BIT_CAPABLE)
		mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
	if (pdata->flags & SLOTF_4_BIT_CAPABLE)
		mmc->caps |= MMC_CAP_4_BIT_DATA;
}

Regards
Dong Aisheng



From aisheng.dong at freescale.com  Wed Mar 14 04:20:24 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 14 Mar 2012 16:20:24 +0800
Subject: [PATCH v1 3/5] ARM: imx28evk: add mmc dt support
In-Reply-To: <20120314073035.GI18320@game.jcrosoft.org>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-4-git-send-email-b29396@freescale.com>
 <4F5F5C22.1080506@gmail.com>
 <20120313165214.GO26642@pengutronix.de>
 <4F5F879E.4030407@gmail.com>
 <20120314073035.GI18320@game.jcrosoft.org>
Message-ID: <20120314082024.GB1180@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 03:30:35PM +0800, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 12:45 Tue 13 Mar     , Rob Herring wrote:
> > On 03/13/2012 11:52 AM, Sascha Hauer wrote:
> > > On Tue, Mar 13, 2012 at 09:39:30AM -0500, Rob Herring wrote:
> > >> On 03/13/2012 03:47 AM, Dong Aisheng wrote:
> > >>> From: Dong Aisheng <dong.aisheng at linaro.org>
> > >>>
> > >>> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > >>> ---
> > >>>  arch/arm/boot/dts/imx28-evk.dts |   14 ++++++++++++++
> > >>>  arch/arm/boot/dts/imx28.dtsi    |   33 +++++++++++++++++++++++++++++++++
> > >>>  arch/arm/mach-mxs/imx28-dt.c    |    2 ++
> > >>>  3 files changed, 49 insertions(+), 0 deletions(-)
> > >>
> > >> snip
> > >>
> > >>> diff --git a/arch/arm/mach-mxs/imx28-dt.c b/arch/arm/mach-mxs/imx28-dt.c
> > >>> index 78d1129..429b88e 100644
> > >>> --- a/arch/arm/mach-mxs/imx28-dt.c
> > >>> +++ b/arch/arm/mach-mxs/imx28-dt.c
> > >>> @@ -23,6 +23,8 @@ static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
> > >>>  	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
> > >>>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
> > >>>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
> > >>> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP0_BASE_ADDR, "mxs-mmc.0", NULL),
> > >>> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP1_BASE_ADDR, "mxs-mmc.1", NULL),
> > >>
> > >> Why is this needed?
> > > 
> > > These are needed for the drivers which have still the mxs-mmc.* names
> > > to find their clocks. Alternatively we could also add the appropriate
> > > clocks to the clock file. Don't know if that's better though.
> > 
> > Ah, yes I should have known that... If clk lookup is all that's needed,
> > I'd suggest adding the necessary clk lookups either here or in the clock
> > code. Not much difference, but at least it removes the use of
> > *_BASE_ADDR defines.
> Agreed we do this on AT91
> 
I'm willing to do like that.
But i'm new to this, can you help point our where the code i can reference
in Rob suggested way?

Regards
Dong Aisheng



From haojian.zhuang at gmail.com  Wed Mar 14 04:20:05 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 16:20:05 +0800
Subject: [PATCH] pxa/hx4700: Remove unwanted request for GPIO105
In-Reply-To: <1331644290.41945.YahooMailClassic@web29009.mail.ird.yahoo.com>
References: <1331644290.41945.YahooMailClassic@web29009.mail.ird.yahoo.com>
Message-ID: <CAN1soZwB0aRvLROtJ64pmuJCRb7EVT+g7BLL2uVLw8QRCofu5A@mail.gmail.com>

On Tue, Mar 13, 2012 at 9:11 PM, Paul Parsons <lost.distance at yahoo.com> wrote:
> GPIO105 (nIR_ON) is requested twice: first in gpio_request_array(), then in
> pxa_irda_probe(). Consequently the second request fails with EBUSY:
>
> pxa2xx-ir: probe of pxa2xx-ir failed with error -16
>
> This patch removes the first request, allowing pxa_irda_probe() to succeed.
>
> Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
> ---

Applied


From aisheng.dong at freescale.com  Wed Mar 14 04:23:52 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 14 Mar 2012 16:23:52 +0800
Subject: [PATCH v1 4/5] dma: mxs-dma: add dt probe support
In-Reply-To: <4F604EBD.7060400@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-5-git-send-email-b29396@freescale.com>
 <4F604EBD.7060400@freescale.com>
Message-ID: <20120314082352.GC1180@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 03:54:37PM +0800, Huang Shijie-B32955 wrote:
> Hi Aisheng:
> > From: Dong Aisheng<dong.aisheng at linaro.org>
> >
> > Signed-off-by: Dong Aisheng<dong.aisheng at linaro.org>
> > ---
> >   .../devicetree/bindings/dma/fsl-mxs-dma.txt        |   17 ++++++++
> >   drivers/dma/mxs-dma.c                              |   44 +++++++++++++------
> >   2 files changed, 47 insertions(+), 14 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
> > new file mode 100644
> > index 0000000..cfa1730
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
> > @@ -0,0 +1,17 @@
> > +* Freescale MXS DMA
> > +
> > +Required properties:
> > +- compatible : Should be "fsl,mxs-dma-apbh" or "fsl,mxs-dma-apbx"
> > +- reg : Should contain registers location and length
> > +
> > +Examples:
> > +
> > +dma-apbh at 80004000 {
> > +	compatible = "fsl,mxs-dma-apbh";
> > +	reg =<0x80004000 2000>;
> > +};
> > +
> > +dma-apbx at 80024000 {
> > +	compatible = "fsl,mxs-dma-apbx";
> > +	reg =<0x80024000 2000>;
> > +};
> > diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
> > index b06cd4c..45e8d46 100644
> > --- a/drivers/dma/mxs-dma.c
> > +++ b/drivers/dma/mxs-dma.c
> > @@ -22,6 +22,9 @@
> >   #include<linux/platform_device.h>
> >   #include<linux/dmaengine.h>
> >   #include<linux/delay.h>
> > +#include<linux/module.h>
> > +#include<linux/of.h>
> > +#include<linux/of_device.h>
> >
> >   #include<asm/irq.h>
> >   #include<mach/mxs.h>
> > @@ -130,6 +133,25 @@ struct mxs_dma_engine {
> >   	struct mxs_dma_chan		mxs_chans[MXS_DMA_CHANNELS];
> >   };
> >
> > +static struct platform_device_id mxs_dma_type[] = {
> > +	{
> > +		.name = "mxs-dma-apbh",
> > +		.driver_data = MXS_DMA_APBH,
> > +	}, {
> > +		.name = "mxs-dma-apbx",
> > +		.driver_data = MXS_DMA_APBX,
> > +	}, {
> > +		/* end of list */
> > +	}
> > +};
> > +
> I think you should use the platform_device_id to distinguish different 
> archs.
> In the mx6q,  you will meet some compiler error for the macro cpu_is_mx23().
> 
Yes, i will remove cpu_is_*() in mxs-mmc driver by using device id.

Regards
Dong Aisheng



From haojian.zhuang at gmail.com  Wed Mar 14 04:22:34 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 16:22:34 +0800
Subject: [PATCH] pxa/hx4700: Remove pcmcia platform_device structure
In-Reply-To: <CA+gwMce5x8XddOoKKNhYVfowstUtfeTNegJYA41av6EBLvS7sg@mail.gmail.com>
References: <1331305076.23513.YahooMailClassic@web29009.mail.ird.yahoo.com>
 <CA+gwMce5x8XddOoKKNhYVfowstUtfeTNegJYA41av6EBLvS7sg@mail.gmail.com>
Message-ID: <CAN1soZwG_EyVPjfQoAz-b8Z56pjPVbQJY7k3fDqoe7+k2kw=+w@mail.gmail.com>

On Sat, Mar 10, 2012 at 1:35 AM, Philipp Zabel <philipp.zabel at gmail.com> wrote:
> On Fri, Mar 9, 2012 at 3:57 PM, Paul Parsons <lost.distance at yahoo.com> wrote:
>> The existing pcmcia platform_device structure is not used and is not needed by
>> the pending hx4700 PCMCIA/CF support. So let's remove it.
>>
>> Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
>
> Acked-by: Philipp Zabel <philipp.zabel at gmail.com>
>
Applied


From richard.zhao at linaro.org  Wed Mar 14 04:22:58 2012
From: richard.zhao at linaro.org (Richard Zhao)
Date: Wed, 14 Mar 2012 16:22:58 +0800
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
Message-ID: <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>

Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
---
 arch/arm/mach-imx/clock-imx6q.c |   85 +++++++++++++++++++++++++++++++++-----
 1 files changed, 73 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index e4e4f5e..3d5dc56 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -519,6 +519,18 @@ static int pll1_sys_set_rate(struct clk *clk, unsigned long rate)
 	return 0;
 }
 
+static unsigned long pll1_sys_round_rate(struct clk *clk, unsigned long rate)
+{
+	u32 div;
+	unsigned long parent_rate = clk_get_rate(clk->parent);
+
+	rate = rate < FREQ_650M ? FREQ_650M : rate;
+	rate = rate > FREQ_1300M ? FREQ_1300M : rate;
+
+	div = rate * 2 / parent_rate;
+	return parent_rate * div / 2;
+}
+
 static unsigned long pll8_enet_get_rate(struct clk *clk)
 {
 	u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >>
@@ -567,6 +579,20 @@ static int pll8_enet_set_rate(struct clk *clk, unsigned long rate)
 	return 0;
 }
 
+static unsigned long pll8_enet_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (rate >= 125000000)
+		rate = 125000000;
+	else if (rate >= 100000000)
+		rate = 100000000;
+	else if (rate >= 50000000)
+		rate = 50000000;
+	else
+		rate = 25000000;
+	return rate;
+}
+
+
 static unsigned long pll_av_get_rate(struct clk *clk)
 {
 	void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
@@ -606,6 +632,25 @@ static int pll_av_set_rate(struct clk *clk, unsigned long rate)
 	return 0;
 }
 
+static unsigned long pll_av_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long parent_rate = clk_get_rate(clk->parent);
+	u32 div;
+	u32 mfn, mfd = 1000000;
+	s64 temp64;
+
+	rate = rate < FREQ_650M ? FREQ_650M : rate;
+	rate = rate > FREQ_1300M ? FREQ_1300M : rate;
+
+	div = rate / parent_rate;
+	temp64 = (u64) (parent_rate - (div * parent_rate));
+        temp64 *= mfd;
+        do_div(temp64, parent_rate);
+        mfn = temp64;
+
+        return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+}
+
 static void __iomem *pll_get_div_reg_bit(struct clk *clk, u32 *bp, u32 *bm)
 {
 	void __iomem *reg;
@@ -662,18 +707,33 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
 	return 0;
 }
 
-#define pll2_bus_get_rate	pll_get_rate
-#define pll2_bus_set_rate	pll_set_rate
-#define pll3_usb_otg_get_rate	pll_get_rate
-#define pll3_usb_otg_set_rate	pll_set_rate
-#define pll7_usb_host_get_rate	pll_get_rate
-#define pll7_usb_host_set_rate	pll_set_rate
-#define pll4_audio_get_rate	pll_av_get_rate
-#define pll4_audio_set_rate	pll_av_set_rate
-#define pll5_video_get_rate	pll_av_get_rate
-#define pll5_video_set_rate	pll_av_set_rate
-#define pll6_mlb_get_rate	NULL
-#define pll6_mlb_set_rate	NULL
+static unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (rate >= FREQ_528M)
+		rate = FREQ_528M;
+	else
+		rate = FREQ_480M;
+	return rate;
+}
+
+#define pll2_bus_get_rate		pll_get_rate
+#define pll2_bus_set_rate		pll_set_rate
+#define pll2_bus_round_rate		pll_round_rate
+#define pll3_usb_otg_get_rate		pll_get_rate
+#define pll3_usb_otg_set_rate		pll_set_rate
+#define pll3_usb_otg_round_rate		pll_round_rate
+#define pll7_usb_host_get_rate		pll_get_rate
+#define pll7_usb_host_set_rate		pll_set_rate
+#define pll7_usb_host_round_rate	pll_round_rate
+#define pll4_audio_get_rate		pll_av_get_rate
+#define pll4_audio_set_rate		pll_av_set_rate
+#define pll4_audio_round_rate		pll_av_round_rate
+#define pll5_video_get_rate		pll_av_get_rate
+#define pll5_video_set_rate		pll_av_set_rate
+#define pll5_video_round_rate		pll_av_round_rate
+#define pll6_mlb_get_rate		NULL
+#define pll6_mlb_set_rate		NULL
+#define pll6_mlb_round_rate		NULL
 
 #define DEF_PLL(name)					\
 	static struct clk name = {			\
@@ -681,6 +741,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
 		.disable	= pll_disable,		\
 		.get_rate	= name##_get_rate,	\
 		.set_rate	= name##_set_rate,	\
+		.round_rate	= name##_round_rate,	\
 		.parent		= &osc_clk,		\
 	}
 
-- 
1.7.5.4




From richard.zhao at linaro.org  Wed Mar 14 04:22:57 2012
From: richard.zhao at linaro.org (Richard Zhao)
Date: Wed, 14 Mar 2012 16:22:57 +0800
Subject: [PATCH 0/2] improve imx6q arm_clk set rate
Message-ID: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>

arm_clk rate changing should also change pll1 rate.

Richard Zhao (2):
  ARM: imx6q: add pll round_rate support
  ARM: imx6q: change pll1 rate when change arm_clk rate

 arch/arm/mach-imx/clock-imx6q.c |  161 +++++++++++++++++++++++++++++++++++---
 1 files changed, 148 insertions(+), 13 deletions(-)

-- 
1.7.5.4




From richard.zhao at linaro.org  Wed Mar 14 04:22:59 2012
From: richard.zhao at linaro.org (Richard Zhao)
Date: Wed, 14 Mar 2012 16:22:59 +0800
Subject: [PATCH 2/2] ARM: imx6q: change pll1 rate when change arm_clk rate
In-Reply-To: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
Message-ID: <1331713379-8437-3-git-send-email-richard.zhao@linaro.org>

Add arm_clk's own get_rate/set_rate/round_rate functions.

set_rate steps:
 - reparent pll1_sw_clk to pll2_pfd_400m or osc_clk
 - disable pll1_sys
 - set pll1_sys rate
 - enable pll1_sys
 - reparent pll1_sw_clk back to pll1_sys

Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
---
 arch/arm/mach-imx/clock-imx6q.c |   76 ++++++++++++++++++++++++++++++++++++++-
 1 files changed, 75 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 3d5dc56..e601f52 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -1782,7 +1782,6 @@ DEF_NG_CLK(periph2_pre_clk,	&pll2_bus);
 DEF_NG_CLK(periph2_clk,		&periph2_pre_clk);
 DEF_NG_CLK(axi_clk,		&periph_clk);
 DEF_NG_CLK(emi_clk,		&axi_clk);
-DEF_NG_CLK(arm_clk,		&pll1_sw_clk);
 DEF_NG_CLK(ahb_clk,		&periph_clk);
 DEF_NG_CLK(ipg_clk,		&ahb_clk);
 DEF_NG_CLK(ipg_perclk,		&ipg_clk);
@@ -1873,6 +1872,81 @@ DEF_CLK(emi_slow_clk,	  CCGR6, CG5,  &axi_clk,	  NULL);
 DEF_CLK(vdo_axi_clk,	  CCGR6, CG6,  &axi_clk,	  NULL);
 DEF_CLK(vpu_clk,	  CCGR6, CG7,  &axi_clk,	  NULL);
 
+static unsigned long arm_clk_get_rate(struct clk *clk)
+{
+	unsigned long parent_rate = clk_get_rate(clk->parent);
+	u32 reg, div;
+
+	reg = readl_relaxed(CACRR);
+	div = (reg & BM_CACRR_ARM_PODF) >> BP_CACRR_ARM_PODF;
+
+	return parent_rate / (div + 1);
+}
+static int arm_clk_bestdiv(unsigned long rate, unsigned long *prate)
+{
+	u32 i, maxdiv, bestdiv = 0;
+	unsigned long parent_rate, best = 0, now;
+
+	*prate = 0;
+	maxdiv = (BM_CACRR_ARM_PODF >> BP_CACRR_ARM_PODF) + 1;
+	for (i = 1; i <= maxdiv; i++) {
+		int div;
+		parent_rate = clk_round_rate(&pll1_sys, rate * i);
+		div = parent_rate / rate;
+		div = div > maxdiv ? maxdiv : div;
+		div = div < 1 ? 1 : div;
+		now = parent_rate / div;
+
+		if (now <= rate && now >= best) {
+			bestdiv = div;
+			best = now;
+			*prate = parent_rate;
+			if (now == rate)
+				break;
+		}
+	}
+	return bestdiv;
+}
+
+static int arm_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg, div;
+	unsigned long parent_rate;
+	div = arm_clk_bestdiv(rate, &parent_rate);
+
+	if (pll2_pfd_400m.usecount > 0)
+		pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400m);
+	else
+		pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
+	pll1_sys.disable(&pll1_sys);
+	pll1_sys.set_rate(&pll1_sys, parent_rate);
+	pll1_sys.enable(&pll1_sys);
+	pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys);
+
+	reg = readl_relaxed(CACRR);
+	reg &= ~BM_CACRR_ARM_PODF;
+	reg |= (div - 1) << BP_CACRR_ARM_PODF;
+	writel_relaxed(reg, CACRR);
+
+	return 0;
+}
+
+static unsigned long arm_clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long div, parent_rate;
+
+	div = arm_clk_bestdiv(rate, &parent_rate);
+	return parent_rate / div;
+}
+
+static struct clk arm_clk = {
+	.get_rate	= arm_clk_get_rate,
+	.set_rate	= arm_clk_set_rate,
+	.round_rate	= arm_clk_round_rate,
+	.set_parent	= _clk_set_parent,
+	.parent		= &pll1_sw_clk,
+};
+
 static int pcie_clk_enable(struct clk *clk)
 {
 	u32 val;
-- 
1.7.5.4




From kgene.kim at samsung.com  Wed Mar 14 04:25:11 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 01:25:11 -0700
Subject: [PATCH v2 3/3] gpio/samsung: use ioremap() for EXYNOS4 GPIOlib
In-Reply-To: <4F5E45E0.9020108@samsung.com>
References: <1329341829-14403-1-git-send-email-kgene.kim@samsung.com>
 <1329341829-14403-4-git-send-email-kgene.kim@samsung.com>
 <20120312161904.E57193E07B0@localhost> <4F5E45E0.9020108@samsung.com>
Message-ID: <4F6055E7.7040609@samsung.com>

On 03/12/12 11:52, Kukjin Kim wrote:
> Grant Likely wrote:
>> On Thu, 16 Feb 2012 06:37:09 +0900, Kukjin Kim<kgene.kim at samsung.com>   wrote:
>>> From: Sangsu Park<sangsu4u.park at samsung.com>
>>>
>>> This patch changes to use ioremap() for EXYNOS4210
>>> so that we can drop the static mapping for EXYNOS
>>> SoCs.
>>>
>>> Note: Will be updated for all of Samsung GPIOlibs
>>> to use ioremap() next time.
>>>
>>> Signed-off-by: Sangsu Park<sangsu4u.park at samsung.com>
>>> Cc: Grant Likely<grant.likely at secretlab.ca>
>>> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
>>
>> Acked-by: Grant Likely<grant.likely at secretlab.ca>
>>
>> Kukjin, I think you wanted to take this via your tree?  I'm fine with that.
>> Let me know if you'd rather it go via the gpio tree.
>>
> Hi Grant,
> 
> I think, since this series has no depenency with current samsung tree
> for upcoming merge window, this can be sent to upstream via the gpio tree.
> 
Grant,

If you don't pick this up for your tree yet, let me take this series in
samsung tree.
This patches are needed for samsung tree. Sorry for bothering and if any
problems, please let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From haojian.zhuang at gmail.com  Wed Mar 14 04:26:39 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 16:26:39 +0800
Subject: [PATCH] MAINTAINERS: update maintainer entry for pxa/hx4700
In-Reply-To: <1330256419.3673.27.camel@flow>
References: <1330256419.3673.27.camel@flow>
Message-ID: <CAN1soZw_fJ+zfgmg7Lm5mDYbUvuckOfSWgDNhDGsZCOQRDYwgA@mail.gmail.com>

On Sun, Feb 26, 2012 at 7:40 PM, Philipp Zabel <philipp.zabel at gmail.com> wrote:
> Add Paul Parsons as maintainer for pxa/hx4700.
> Also, add a mailing list and update the files.
>
applied


From aisheng.dong at freescale.com  Wed Mar 14 04:30:47 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 14 Mar 2012 16:30:47 +0800
Subject: [PATCH v1 5/5] ARM: mxs: add mxs dma dt support
In-Reply-To: <4F604F9F.1070801@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-6-git-send-email-b29396@freescale.com>
 <4F604F9F.1070801@freescale.com>
Message-ID: <20120314083046.GD1180@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 03:58:23PM +0800, Huang Shijie-B32955 wrote:
> Hi,
> > +			dma-apbh at 80004000 {
> > +				compatible = "fsl,mxs-dma-apbh";
> > +				reg =<0x80004000 2000>;
> > +			};
> > +
> Why you do not add the `interrupt` for the it?
> the gpmi-nand needs to parse the interrupt out.
> 
The non-dt way also does not have interrupt resource for dma device.
It seems the channel interrupt resource is handled in each client device.
I'm not familiar with gpmi-nand, but I guess you may need to handle
it in gpmi driver, just like mxs-mmc driver.

Regards
Dong Aisheng



From haojian.zhuang at gmail.com  Wed Mar 14 04:29:05 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 16:29:05 +0800
Subject: [PATCH v2] pxa/hx4700: Reduce sleep mode battery discharge by 35%
In-Reply-To: <1331472222.71907.YahooMailClassic@web29003.mail.ird.yahoo.com>
References: <1331472222.71907.YahooMailClassic@web29003.mail.ird.yahoo.com>
Message-ID: <CAN1soZw6wcvW1=HcjLigQ8HieoB9J9neYX=tjWJVd24wfZ4Rag@mail.gmail.com>

On Sun, Mar 11, 2012 at 9:23 PM, Paul Parsons <lost.distance at yahoo.com> wrote:
> Drive the two Bluetooth UART output GPIOs (GPIO43_BTUART_TXD, GPIO45_BTUART_RTS)
> LOW during sleep mode instead of HIGH. This reduces sleep mode battery discharge
> from approximately 46 mA to approximately 30 mA.
>
> Signed-off-by: Oliver Winker <oliver at oli1170.net>
> Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
> ---
>
> V2:
> Corrected nomenclature.
> Added GPIO43_BTUART_TXD_LPM_LOW and GPIO45_BTUART_RTS_LPM_LOW to mfp-pxa27x.h
>
> diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c
> --- clean-3.3-rc6/arch/arm/mach-pxa/hx4700.c ? ?2012-03-04 01:08:09.000000000 +0000
> +++ linux-3.3-rc6/arch/arm/mach-pxa/hx4700.c ? ?2012-03-11 12:30:29.799567611 +0000
> @@ -97,9 +97,9 @@ static unsigned long hx4700_pin_config[]
>
> ? ? ? ?/* BTUART */
> ? ? ? ?GPIO42_BTUART_RXD,
> - ? ? ? GPIO43_BTUART_TXD,
> + ? ? ? GPIO43_BTUART_TXD_LPM_LOW,
> ? ? ? ?GPIO44_BTUART_CTS,
> - ? ? ? GPIO45_BTUART_RTS,
> + ? ? ? GPIO45_BTUART_RTS_LPM_LOW,
>
> ? ? ? ?/* PWM 1 (Backlight) */
> ? ? ? ?GPIO17_PWM1_OUT,
> diff -uprN clean-3.3-rc6/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h linux-3.3-rc6/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
> --- clean-3.3-rc6/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h ? 2012-03-04 01:08:09.000000000 +0000
> +++ linux-3.3-rc6/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h ? 2012-03-11 12:32:23.728285708 +0000
> @@ -158,7 +158,9 @@
> ?#define GPIO44_BTUART_CTS ? ? ?MFP_CFG_IN(GPIO44, AF1)
> ?#define GPIO42_BTUART_RXD ? ? ?MFP_CFG_IN(GPIO42, AF1)
> ?#define GPIO45_BTUART_RTS ? ? ?MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
> +#define GPIO45_BTUART_RTS_LPM_LOW ? ? ?MFP_CFG_OUT(GPIO45, AF2, DRIVE_LOW)
> ?#define GPIO43_BTUART_TXD ? ? ?MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
> +#define GPIO43_BTUART_TXD_LPM_LOW ? ? ?MFP_CFG_OUT(GPIO43, AF2, DRIVE_LOW)
>
> ?/* STUART */
> ?#define GPIO46_STUART_RXD ? ? ?MFP_CFG_IN(GPIO46, AF2)
>
>
Applied


From paul at pwsan.com  Wed Mar 14 04:38:09 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 14 Mar 2012 02:38:09 -0600 (MDT)
Subject: [GIT PULL] ARM: OMAP2+: hwmod: remove link arrays
Message-ID: <alpine.DEB.2.00.1203140231150.7269@utopia.booyaka.com>

Hi Tony

The following changes since commit 5f43ef65748c19b954756485ddaef657ac71b649:

  Merge branch 'hwmod_misc_devel_3.4' into MERGE_sr_and_hwmod_data (2012-03-08 21:03:17 -0700)

are available in the git repository at:

  git://git.pwsan.com/linux-2.6 hwmod_remove_link_arrays_cleanup_3.4

for you to fetch changes up to afce19b152eedea0402561087dd939b23b53f3cb:

  ARM: OMAP2xxx: hwmod data: start to fix the IVA1, IVA2 and DSP (2012-03-08 21:04:50 -0700)

The base commit for this pull request is a merge of your SR branch with 
the 'hwmod_misc_devel_3.4' branch, since this series has dependencies on 
both of those.


- Paul

----------------------------------------------------------------
Paul Walmsley (12):
      ARM: OMAP2+: hwmod: add _find_mpu_rt_port()
      ARM: OMAP2+: hwmod: add function to iterate over struct omap_hwmod_ocp_if
      ARM: OMAP2+: hwmod: consolidate finding the MPU port index and storing it
      ARM: OMAP2+: hwmod: add support for link registration
      ARM: OMAP2+: hwmod data: convert to link registration
      ARM: OMAP: hwmod: remove code support for direct hwmod registration
      ARM: OMAP2+: hwmod data: remove forward declarations, reorganize
      ARM: OMAP2xxx: hwmod data: share common hwmods between OMAP2420 and OMAP2430
      ARM: OMAP2xxx: hwmod data: share common interface data
      ARM: OMAP3: hwmod data: fix IVA interface clock
      ARM: OMAP3: hwmod data: add IVA hard reset lines, main clock, clockdomain
      ARM: OMAP2xxx: hwmod data: start to fix the IVA1, IVA2 and DSP

 arch/arm/mach-omap2/omap_hwmod.c                   |  410 ++-
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         | 1563 +-----
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         | 2316 +++-------
 .../mach-omap2/omap_hwmod_2xxx_interconnect_data.c |  266 +-
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |  562 +++
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         | 5081 +++++++++-----------
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         | 4882 ++++++++-----------
 arch/arm/mach-omap2/omap_hwmod_common_data.h       |   71 +-
 arch/arm/plat-omap/include/plat/omap_hwmod.h       |   31 +-
 9 files changed, 6341 insertions(+), 8841 deletions(-)


From haojian.zhuang at gmail.com  Wed Mar 14 04:38:20 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 16:38:20 +0800
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <1331242494-3157-1-git-send-email-paul.gortmaker@windriver.com>
References: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
 <1331242494-3157-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <CAN1soZzDRR4XQ34WDL48=j+Ff8t5fsCFaccqZAKOQ1OAPeDXcA@mail.gmail.com>

On Fri, Mar 9, 2012 at 5:34 AM, Paul Gortmaker
<paul.gortmaker at windriver.com> wrote:
> commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)
>
> ?"regulator: Remove support for supplies specified by struct device"
>
> deletes the field from the struct, but this platform was still trying
> to set those fields. ?Convert them to use the REGULATOR_SUPPLY macro.
>
> arch/arm/mach-pxa/magician.c:581: error: unknown field 'dev' specified in initializer
> arch/arm/mach-pxa/magician.c:581: warning: initialization from incompatible pointer type
> arch/arm/mach-pxa/magician.c:585: error: unknown field 'dev' specified in initializer
> arch/arm/mach-pxa/magician.c:585: warning: initialization from incompatible pointer type
>
> arch/arm/mach-pxa/hx4700.c:683: error: unknown field 'dev' specified in initializer
> arch/arm/mach-pxa/hx4700.c:683: warning: initialization from incompatible pointer type
> arch/arm/mach-pxa/hx4700.c:687: error: unknown field 'dev' specified in initializer
> arch/arm/mach-pxa/hx4700.c:687: warning: initialization from incompatible pointer type
>
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> ---
>
> [v3: fix arg2 in REGULATOR_SUPPLY to have correct names ]
>
> diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
> index f2c23ea..b6a338b 100644
> --- a/arch/arm/mach-pxa/hx4700.c
> +++ b/arch/arm/mach-pxa/hx4700.c
> @@ -679,14 +679,8 @@ static struct platform_device power_supply = {
> ?*/
>
> ?static struct regulator_consumer_supply bq24022_consumers[] = {
> - ? ? ? {
> - ? ? ? ? ? ? ? .dev = &gpio_vbus.dev,
> - ? ? ? ? ? ? ? .supply = "vbus_draw",
> - ? ? ? },
> - ? ? ? {
> - ? ? ? ? ? ? ? .dev = &power_supply.dev,
> - ? ? ? ? ? ? ? .supply = "ac_draw",
> - ? ? ? },
> + ? ? ? REGULATOR_SUPPLY("vbus_draw", "gpio-vbus"),
> + ? ? ? REGULATOR_SUPPLY("ac_draw", "pda-power"),

How do you think about Mark's comments? Use dev_name() at here.
> ?};
>
> ?static struct regulator_init_data bq24022_init_data = {
> diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
> index 3d6baf9..1a18e63 100644
> --- a/arch/arm/mach-pxa/magician.c
> +++ b/arch/arm/mach-pxa/magician.c
> @@ -577,14 +577,8 @@ static struct platform_device power_supply = {
> ?*/
>
> ?static struct regulator_consumer_supply bq24022_consumers[] = {
> - ? ? ? {
> - ? ? ? ? ? ? ? .dev = &gpio_vbus.dev,
> - ? ? ? ? ? ? ? .supply = "vbus_draw",
> - ? ? ? },
> - ? ? ? {
> - ? ? ? ? ? ? ? .dev = &power_supply.dev,
> - ? ? ? ? ? ? ? .supply = "ac_draw",
> - ? ? ? },
> + ? ? ? REGULATOR_SUPPLY("vbus_draw", "gpio-vbus"),
> + ? ? ? REGULATOR_SUPPLY("ac_draw", "pda-power"),
> ?};
>
> ?static struct regulator_init_data bq24022_init_data = {
> --
> 1.7.9.1
>


From b32955 at freescale.com  Wed Mar 14 04:43:21 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 14 Mar 2012 16:43:21 +0800
Subject: [PATCH v1 5/5] ARM: mxs: add mxs dma dt support
In-Reply-To: <20120314083046.GD1180@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-6-git-send-email-b29396@freescale.com>
 <4F604F9F.1070801@freescale.com>
 <20120314083046.GD1180@shlinux2.ap.freescale.net>
Message-ID: <4F605A29.6080009@freescale.com>

Hi Aisheng:
> The non-dt way also does not have interrupt resource for dma device.
> It seems the channel interrupt resource is handled in each client device.
> I'm not familiar with gpmi-nand, but I guess you may need to handle
> it in gpmi driver, just like mxs-mmc driver.
>
ok, got it.

thanks
Huang Shijie




From marc.zyngier at arm.com  Wed Mar 14 04:43:39 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Wed, 14 Mar 2012 08:43:39 +0000
Subject: Conflict between Versatile Express DT conversion and local timer
 updates
In-Reply-To: <CAOesGMjo=JT3TKwne+m5XUpkBMQFKQLZrr1T60m+Wx7YgqMiOA@mail.gmail.com>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <201203131155.16454.arnd@arndb.de>	<4F5F52A2.3050005@arm.com>
 <201203131433.07214.arnd@arndb.de>
 <CAOesGMjo=JT3TKwne+m5XUpkBMQFKQLZrr1T60m+Wx7YgqMiOA@mail.gmail.com>
Message-ID: <4F605A3B.5030800@arm.com>

On 14/03/12 00:52, Olof Johansson wrote:
> On Tue, Mar 13, 2012 at 7:33 AM, Arnd Bergmann <arnd at arndb.de> wrote:
>> On Tuesday 13 March 2012, Marc Zyngier wrote:
>>> On 13/03/12 11:55, Arnd Bergmann wrote:
>>>> On Tuesday 13 March 2012, Marc Zyngier wrote:
>>>>> On 13/03/12 10:15, Russell King - ARM Linux wrote:
>>
>>>> d) create a new next/timer branch in arm-soc that has Pawel's
>>>>    98ed4ceb "ARM: vexpress: Get rid of MMIO_P2V" (the first patch from
>>>>    vexpress/dt, your patches and the ux500/timer series. Also put
>>>>    98ed4ceb into the next/cleanup branch.
>>>>
>>>> Any of those will work for us, my preference would be on #4. I have
>>>> created the next/timer branch in the arm-soc tree, so you can use
>>>> that and either rebase your patches on top or merge your tree into
>>>> it and fix up the merge conflicts.
>>>
>>> Thanks for doing that Arnd.
>>>
>>> I've thus created a new branch:
>>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>>> local_timers-for-arm-soc
>>>
>>> which contains the arm-soc next/timers branch as well as my local timers
>>> series. I'd greatly appreciate if you could pull it for 3.4.
>>>
>>
>> I've updated the next/timer branch with your changes now, but did not
>> put it into the for-next branch because Olof is currently handling that.
>>
>> Olof, can you add it to for-next please? The timer branch should have
>> no dependencies other than rmk/for-armsoc, so it can be fairly close to
>> the start.
> 
> 
> Thanks. I merged into for-next, but since there's already a history in
> there and I didn't rebuild it, it's on top of everything else.
> 
> I got two trivial merge conflicts (and a few that git sorted out
> automatically): one with the tegra makefile, the other with shmobile's
> timer init.
> 
> Marc, please take a look at the next/timers merge in the arm-soc
> for-next branch and let me know if they're OK. I'm pretty sure they
> are though.

Had a brief look, and it seems alright to me.

Thanks Olof!

	M.
-- 
Jazz is not dead. It just smells funny...



From paul at pwsan.com  Wed Mar 14 04:45:03 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 14 Mar 2012 02:45:03 -0600 (MDT)
Subject: [GIT PULL] ARM: OMAP4: hwmod data: add almost all remaining IP blocks
Message-ID: <alpine.DEB.2.00.1203140241070.7269@utopia.booyaka.com>

Hi Tony

The following changes since commit afce19b152eedea0402561087dd939b23b53f3cb:

  ARM: OMAP2xxx: hwmod data: start to fix the IVA1, IVA2 and DSP (2012-03-08 21:04:50 -0700)

are available in the git repository at:

  git://git.pwsan.com/linux-2.6 hwmod_enable_remaining_hwmods_devel_3.4

for you to fetch changes up to de028b2eb97649d82ebb1ca1f6fabc932ca98354:

  ARM: OMAP4: hwmod data: add DEBUGSS skeleton (2012-03-08 21:29:05 -0700)

This series has a dependency on the 'hwmod_remove_link_arrays_cleanup_3.4' 
branch.


- Paul

----------------------------------------------------------------
Beno?t Cousson (6):
      ARM: OMAP4: hwmod data: add GPMC
      ARM: OMAP4: hwmod data: add the Slimbus IP blocks
      ARM: OMAP4: hwmod data: add McASP
      ARM: OMAP4: hwmod data: add remaining USB-related IP blocks
      ARM: OMAP4: hwmod data: add the OCP-WP IP block
      ARM: OMAP4: hwmod data: add DEBUGSS skeleton

Ming Lei (1):
      ARM: OMAP4: hwmod data: introduce fdif(face detect module) hwmod

Paul Walmsley (8):
      ARM: OMAP2+: clockdomains: make {prm,cm}_clkdm common
      ARM: OMAP4: hwmod data: add HDQ/1-wire
      ARM: OMAP4: hwmod data: add EMIF1 and 2
      ARM: OMAP4: hwmod data: add GPU
      ARM: OMAP4: hwmod data: add some interconnect-related IP blocks
      ARM: OMAP4: hwmod data: add OCM RAM IP block
      ARM: OMAP4: hwmod data: add System Control Module
      ARM: OMAP4: hwmod data: add PRCM and related IP blocks

 arch/arm/mach-omap2/Makefile                     |    8 +-
 arch/arm/mach-omap2/clockdomain44xx.c            |    6 +
 arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c |   10 -
 arch/arm/mach-omap2/clockdomains44xx_data.c      |    2 +
 arch/arm/mach-omap2/clockdomains_common_data.c   |   24 +
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c       | 1473 +++++++++++++++++++++-
 arch/arm/plat-omap/include/plat/omap_hwmod.h     |    1 +
 7 files changed, 1443 insertions(+), 81 deletions(-)
 create mode 100644 arch/arm/mach-omap2/clockdomains_common_data.c

From s.hauer at pengutronix.de  Wed Mar 14 04:48:57 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 14 Mar 2012 09:48:57 +0100
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zMTY+4dU9VUa-TkEbdE-WJd7V4tCG-af6vgq0CPN6rWpg@mail.gmail.com>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120313112447.GA29317@pengutronix.de>
 <CAJOA=zMTY+4dU9VUa-TkEbdE-WJd7V4tCG-af6vgq0CPN6rWpg@mail.gmail.com>
Message-ID: <20120314084857.GL3852@pengutronix.de>

On Tue, Mar 13, 2012 at 04:43:57PM -0700, Turquette, Mike wrote:
> On Tue, Mar 13, 2012 at 4:24 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > On Sat, Mar 03, 2012 at 12:29:00AM -0800, Mike Turquette wrote:
> >> The common clock framework defines a common struct clk useful across
> >> most platforms as well as an implementation of the clk api that drivers
> >> can use safely for managing clocks.
> >>
> >> The net result is consolidation of many different struct clk definitions
> >> and platform-specific clock framework implementations.
> >>
> >> This patch introduces the common struct clk, struct clk_ops and an
> >> implementation of the well-known clock api in include/clk/clk.h.
> >> Platforms may define their own hardware-specific clock structure and
> >> their own clock operation callbacks, so long as it wraps an instance of
> >> struct clk_hw.
> >>
> >> See Documentation/clk.txt for more details.
> >>
> >> This patch is based on the work of Jeremy Kerr, which in turn was based
> >> on the work of Ben Herrenschmidt.
> >>
> >> Signed-off-by: Mike Turquette <mturquette at linaro.org>
> >> Signed-off-by: Mike Turquette <mturquette at ti.com>
> >> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
> >> Cc: Thomas Gleixner <tglx at linutronix.de>
> >> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
> >> Cc: Paul Walmsley <paul at pwsan.com>
> >> Cc: Shawn Guo <shawn.guo at freescale.com>
> >> Cc: Richard Zhao <richard.zhao at linaro.org>
> >> Cc: Saravana Kannan <skannan at codeaurora.org>
> >> Cc: Magnus Damm <magnus.damm at gmail.com>
> >> Cc: Rob Herring <rob.herring at calxeda.com>
> >> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> >> Cc: Linus Walleij <linus.walleij at stericsson.com>
> >> Cc: Stephen Boyd <sboyd at codeaurora.org>
> >> Cc: Amit Kucheria <amit.kucheria at linaro.org>
> >> Cc: Deepak Saxena <dsaxena at linaro.org>
> >> Cc: Grant Likely <grant.likely at secretlab.ca>
> >> Cc: Andrew Lunn <andrew at lunn.ch>
> >> ---
> >> ?drivers/clk/Kconfig ? ? ? ? ?| ? 28 +
> >> ?drivers/clk/Makefile ? ? ? ? | ? ?1 +
> >> ?drivers/clk/clk.c ? ? ? ? ? ?| 1323 ++++++++++++++++++++++++++++++++++++++++++
> >> ?include/linux/clk-private.h ?| ? 68 +++
> >> ?include/linux/clk-provider.h | ?169 ++++++
> >> ?include/linux/clk.h ? ? ? ? ?| ? 68 ++-
> >> ?6 files changed, 1652 insertions(+), 5 deletions(-)
> >> ?create mode 100644 drivers/clk/clk.c
> >> ?create mode 100644 include/linux/clk-private.h
> >> ?create mode 100644 include/linux/clk-provider.h
> >>
> >> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> >> index 3912576..18eb8c2 100644
> >> --- a/drivers/clk/Kconfig
> >> +++ b/drivers/clk/Kconfig
> >> @@ -11,3 +11,31 @@ config HAVE_MACH_CLKDEV
> >>
> >> ?config HAVE_CLK_PREPARE
> >> ? ? ? bool
> >> +
> >> +menuconfig COMMON_CLK
> >> + ? ? bool "Common Clock Framework"
> >> + ? ? select HAVE_CLK_PREPARE
> >> + ? ? ---help---
> >> + ? ? ? The common clock framework is a single definition of struct
> >> + ? ? ? clk, useful across many platforms, as well as an
> >> + ? ? ? implementation of the clock API in include/linux/clk.h.
> >> + ? ? ? Architectures utilizing the common struct clk should select
> >> + ? ? ? this automatically, but it may be necessary to manually select
> >> + ? ? ? this option for loadable modules requiring the common clock
> >> + ? ? ? framework.
> >> +
> >> + ? ? ? If in doubt, say "N".
> >> +
> >> +if COMMON_CLK
> >> +
> >> +config COMMON_CLK_DEBUG
> >> + ? ? bool "DebugFS representation of clock tree"
> >> + ? ? depends on COMMON_CLK
> >> + ? ? ---help---
> >> + ? ? ? Creates a directory hierchy in debugfs for visualizing the clk
> >> + ? ? ? tree structure. ?Each directory contains read-only members
> >> + ? ? ? that export information specific to that clk node: clk_rate,
> >> + ? ? ? clk_flags, clk_prepare_count, clk_enable_count &
> >> + ? ? ? clk_notifier_count.
> >> +
> >> +endif
> >> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> >> index 07613fa..ff362c4 100644
> >> --- a/drivers/clk/Makefile
> >> +++ b/drivers/clk/Makefile
> >> @@ -1,2 +1,3 @@
> >>
> >> ?obj-$(CONFIG_CLKDEV_LOOKUP) ?+= clkdev.o
> >> +obj-$(CONFIG_COMMON_CLK) ? ? += clk.o
> >> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> >> new file mode 100644
> >> index 0000000..b979d74
> >> --- /dev/null
> >> +++ b/drivers/clk/clk.c
> >> @@ -0,0 +1,1323 @@
> >> +/*
> >> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
> >> + * Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License version 2 as
> >> + * published by the Free Software Foundation.
> >> + *
> >> + * Standard functionality for the common clock API. ?See Documentation/clk.txt
> >> + */
> >> +
> >> +#include <linux/clk-private.h>
> >> +#include <linux/module.h>
> >> +#include <linux/mutex.h>
> >> +#include <linux/spinlock.h>
> >> +#include <linux/err.h>
> >> +#include <linux/list.h>
> >> +#include <linux/slab.h>
> >> +
> >> +static DEFINE_SPINLOCK(enable_lock);
> >> +static DEFINE_MUTEX(prepare_lock);
> >> +
> >> +static HLIST_HEAD(clk_root_list);
> >> +static HLIST_HEAD(clk_orphan_list);
> >> +static LIST_HEAD(clk_notifier_list);
> >> +
> >> +/*** ? ? ? ?debugfs support ? ? ? ?***/
> >> +
> >> +#ifdef CONFIG_COMMON_CLK_DEBUG
> >> +#include <linux/debugfs.h>
> >> +
> >> +static struct dentry *rootdir;
> >> +static struct dentry *orphandir;
> >> +static int inited = 0;
> >> +
> >> +/* caller must hold prepare_lock */
> >> +static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
> >> +{
> >> + ? ? struct dentry *d;
> >> + ? ? int ret = -ENOMEM;
> >> +
> >> + ? ? if (!clk || !pdentry) {
> >> + ? ? ? ? ? ? ret = -EINVAL;
> >> + ? ? ? ? ? ? goto out;
> >> + ? ? }
> >> +
> >> + ? ? d = debugfs_create_dir(clk->name, pdentry);
> >> + ? ? if (!d)
> >> + ? ? ? ? ? ? goto out;
> >> +
> >> + ? ? clk->dentry = d;
> >> +
> >> + ? ? d = debugfs_create_u32("clk_rate", S_IRUGO, clk->dentry,
> >> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->rate);
> >> + ? ? if (!d)
> >> + ? ? ? ? ? ? goto err_out;
> >> +
> >> + ? ? d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
> >> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->flags);
> >> + ? ? if (!d)
> >> + ? ? ? ? ? ? goto err_out;
> >> +
> >> + ? ? d = debugfs_create_u32("clk_prepare_count", S_IRUGO, clk->dentry,
> >> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->prepare_count);
> >> + ? ? if (!d)
> >> + ? ? ? ? ? ? goto err_out;
> >> +
> >> + ? ? d = debugfs_create_u32("clk_enable_count", S_IRUGO, clk->dentry,
> >> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->enable_count);
> >> + ? ? if (!d)
> >> + ? ? ? ? ? ? goto err_out;
> >> +
> >> + ? ? d = debugfs_create_u32("clk_notifier_count", S_IRUGO, clk->dentry,
> >> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->notifier_count);
> >> + ? ? if (!d)
> >> + ? ? ? ? ? ? goto err_out;
> >> +
> >> + ? ? ret = 0;
> >> + ? ? goto out;
> >> +
> >> +err_out:
> >> + ? ? debugfs_remove(clk->dentry);
> >> +out:
> >> + ? ? return ret;
> >> +}
> >> +
> >> +/* caller must hold prepare_lock */
> >> +static int clk_debug_create_subtree(struct clk *clk, struct dentry *pdentry)
> >> +{
> >> + ? ? struct clk *child;
> >> + ? ? struct hlist_node *tmp;
> >> + ? ? int ret = -EINVAL;;
> >> +
> >> + ? ? if (!clk || !pdentry)
> >> + ? ? ? ? ? ? goto out;
> >> +
> >> + ? ? ret = clk_debug_create_one(clk, pdentry);
> >> +
> >> + ? ? if (ret)
> >> + ? ? ? ? ? ? goto out;
> >> +
> >> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node)
> >> + ? ? ? ? ? ? clk_debug_create_subtree(child, clk->dentry);
> >> +
> >> + ? ? ret = 0;
> >> +out:
> >> + ? ? return ret;
> >> +}
> >> +
> >> +/**
> >> + * clk_debug_register - add a clk node to the debugfs clk tree
> >> + * @clk: the clk being added to the debugfs clk tree
> >> + *
> >> + * Dynamically adds a clk to the debugfs clk tree if debugfs has been
> >> + * initialized. ?Otherwise it bails out early since the debugfs clk tree
> >> + * will be created lazily by clk_debug_init as part of a late_initcall.
> >> + *
> >> + * Caller must hold prepare_lock. ?Only clk_init calls this function (so
> >> + * far) so this is taken care.
> >> + */
> >> +static int clk_debug_register(struct clk *clk)
> >> +{
> >> + ? ? struct clk *parent;
> >> + ? ? struct dentry *pdentry;
> >> + ? ? int ret = 0;
> >> +
> >> + ? ? if (!inited)
> >> + ? ? ? ? ? ? goto out;
> >> +
> >> + ? ? parent = clk->parent;
> >> +
> >> + ? ? /*
> >> + ? ? ?* Check to see if a clk is a root clk. ?Also check that it is
> >> + ? ? ?* safe to add this clk to debugfs
> >> + ? ? ?*/
> >> + ? ? if (!parent)
> >> + ? ? ? ? ? ? if (clk->flags & CLK_IS_ROOT)
> >> + ? ? ? ? ? ? ? ? ? ? pdentry = rootdir;
> >> + ? ? ? ? ? ? else
> >> + ? ? ? ? ? ? ? ? ? ? pdentry = orphandir;
> >> + ? ? else
> >> + ? ? ? ? ? ? if (parent->dentry)
> >> + ? ? ? ? ? ? ? ? ? ? pdentry = parent->dentry;
> >> + ? ? ? ? ? ? else
> >> + ? ? ? ? ? ? ? ? ? ? goto out;
> >> +
> >> + ? ? ret = clk_debug_create_subtree(clk, pdentry);
> >> +
> >> +out:
> >> + ? ? return ret;
> >> +}
> >> +
> >> +/**
> >> + * clk_debug_init - lazily create the debugfs clk tree visualization
> >> + *
> >> + * clks are often initialized very early during boot before memory can
> >> + * be dynamically allocated and well before debugfs is setup.
> >> + * clk_debug_init walks the clk tree hierarchy while holding
> >> + * prepare_lock and creates the topology as part of a late_initcall,
> >> + * thus insuring that clks initialized very early will still be
> >> + * represented in the debugfs clk tree. ?This function should only be
> >> + * called once at boot-time, and all other clks added dynamically will
> >> + * be done so with clk_debug_register.
> >> + */
> >> +static int __init clk_debug_init(void)
> >> +{
> >> + ? ? struct clk *clk;
> >> + ? ? struct hlist_node *tmp;
> >> +
> >> + ? ? rootdir = debugfs_create_dir("clk", NULL);
> >> +
> >> + ? ? if (!rootdir)
> >> + ? ? ? ? ? ? return -ENOMEM;
> >> +
> >> + ? ? orphandir = debugfs_create_dir("orphans", rootdir);
> >> +
> >> + ? ? if (!orphandir)
> >> + ? ? ? ? ? ? return -ENOMEM;
> >> +
> >> + ? ? mutex_lock(&prepare_lock);
> >> +
> >> + ? ? hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
> >> + ? ? ? ? ? ? clk_debug_create_subtree(clk, rootdir);
> >> +
> >> + ? ? hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
> >> + ? ? ? ? ? ? clk_debug_create_subtree(clk, orphandir);
> >> +
> >> + ? ? inited = 1;
> >> +
> >> + ? ? mutex_unlock(&prepare_lock);
> >> +
> >> + ? ? return 0;
> >> +}
> >> +late_initcall(clk_debug_init);
> >> +#else
> >> +static inline int clk_debug_register(struct clk *clk) { return 0; }
> >> +#endif /* CONFIG_COMMON_CLK_DEBUG */
> >> +
> >> +/*** ? ?helper functions ? ***/
> >> +
> >> +inline const char *__clk_get_name(struct clk *clk)
> >> +{
> >> + ? ? return !clk ? NULL : clk->name;
> >> +}
> >> +
> >> +inline struct clk_hw *__clk_get_hw(struct clk *clk)
> >> +{
> >> + ? ? return !clk ? NULL : clk->hw;
> >> +}
> >> +
> >> +inline u8 __clk_get_num_parents(struct clk *clk)
> >> +{
> >> + ? ? return !clk ? -EINVAL : clk->num_parents;
> >> +}
> >> +
> >> +inline struct clk *__clk_get_parent(struct clk *clk)
> >> +{
> >> + ? ? return !clk ? NULL : clk->parent;
> >> +}
> >> +
> >> +inline unsigned long __clk_get_rate(struct clk *clk)
> >> +{
> >> + ? ? return !clk ? -EINVAL : clk->rate;
> >> +}
> >> +
> >> +inline unsigned long __clk_get_flags(struct clk *clk)
> >> +{
> >> + ? ? return !clk ? -EINVAL : clk->flags;
> >> +}
> >> +
> >> +static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
> >> +{
> >> + ? ? struct clk *child;
> >> + ? ? struct clk *ret;
> >> + ? ? struct hlist_node *tmp;
> >> +
> >> + ? ? if (!strcmp(clk->name, name))
> >> + ? ? ? ? ? ? return clk;
> >> +
> >> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node) {
> >> + ? ? ? ? ? ? ret = __clk_lookup_subtree(name, child);
> >> + ? ? ? ? ? ? if (ret)
> >> + ? ? ? ? ? ? ? ? ? ? return ret;
> >> + ? ? }
> >> +
> >> + ? ? return NULL;
> >> +}
> >> +
> >> +struct clk *__clk_lookup(const char *name)
> >> +{
> >> + ? ? struct clk *root_clk;
> >> + ? ? struct clk *ret;
> >> + ? ? struct hlist_node *tmp;
> >> +
> >
> > This should have a check for NULL pointers. NULL pointers can happen
> > here if a mux has holes in it. In this case the parent name array would
> > look like this:
> >
> > { "parentclk1", "parentclk2", NULL /* reserved */, "parentclk3" }
> >
> > Without checking for NULL pointers we dereference the NULL pointer here.
> 
> I will add the check.  I had not considered having NULL as one of the
> parent names.  It seems to me that the only time this would happen is
> if we are wiring up discrete devices.  For instance:
> 
> Device A has a fixed-rate clock named "dpll"
> Device B has a mux clock named "leaf" with parent_names = { "32k",
> "oscillator", "clkin" }
> 
> On a given board, leaf's "pll" parent might map to the output of the
> dpll clock.  I had considered that DT would step in here by creating
> an intermediate clock with no functional clk_ops that would "connect"
> these two clocks.  The benefit of this is that it is easier to match
> up clock names when staring at some data sheets.  It is common for a
> downstream device's data sheets to assign names to the external inputs
> originating from some unknown device; unsurprisingly the data sheet
> for the device supplying the external upstream clocks often has
> different names for the output signals than the one in the downstream
> device's data sheet.  Using the method described above it is easy for
> a person with both data sheets to see how the devices are wired up
> since all of the clock names are represented by nodes in the clock
> tree.  In short, the final outcome would looking something like:
> 
> dpll (device a's driver registered this clock)
>   |
> clkin (one of device b's possible parents)
>   |    (it is a dummy clock from DT since it is board-level topology)
>   |
> leaf (device b's driver registered this clock)
> 
> clkin would have a single parent named "dpll" in this case, and again,
> it would have no meaningful clk_ops.
> 
> A caveat to the above scenario is that parent_names shouldn't have
> holes in it, but a null pointer check is reasonable anyways.
> 
> What do you think?  Even if we allow for muxes to have holes in
> parent_names we'll still have to solve these sort of device
> integration issues and DT will likely play a roll here.  I'll roll in
> the null pointer check regardless.
> 
> Also, do you forsee needing hole in parent_names for any reason other
> than described above?

I need it only for the case where a some values in the mux are marked as
reserved in the datasheet or we simply do not have the corresponding
clock in our tree (yet). We could also say that NULL pointers are not
allowed in parent arrays, but instead "orphan" or "dummy" should be
used. Then __clk_init should check for NULL pointers to make this clear.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Mar 14 04:52:28 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 14 Mar 2012 09:52:28 +0100
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
Message-ID: <20120314085228.GM3852@pengutronix.de>

On Wed, Mar 14, 2012 at 04:22:58PM +0800, Richard Zhao wrote:
> Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> ---
>  arch/arm/mach-imx/clock-imx6q.c |   85 +++++++++++++++++++++++++++++++++-----
>  1 files changed, 73 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
> index e4e4f5e..3d5dc56 100644
> --- a/arch/arm/mach-imx/clock-imx6q.c
> +++ b/arch/arm/mach-imx/clock-imx6q.c
> @@ -519,6 +519,18 @@ static int pll1_sys_set_rate(struct clk *clk, unsigned long rate)
>  	return 0;
>  }
>  
> +static unsigned long pll1_sys_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	u32 div;
> +	unsigned long parent_rate = clk_get_rate(clk->parent);
> +
> +	rate = rate < FREQ_650M ? FREQ_650M : rate;
> +	rate = rate > FREQ_1300M ? FREQ_1300M : rate;
> +
> +	div = rate * 2 / parent_rate;
> +	return parent_rate * div / 2;
> +}
> +
>  static unsigned long pll8_enet_get_rate(struct clk *clk)
>  {
>  	u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >>
> @@ -567,6 +579,20 @@ static int pll8_enet_set_rate(struct clk *clk, unsigned long rate)
>  	return 0;
>  }
>  
> +static unsigned long pll8_enet_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	if (rate >= 125000000)
> +		rate = 125000000;
> +	else if (rate >= 100000000)
> +		rate = 100000000;
> +	else if (rate >= 50000000)
> +		rate = 50000000;
> +	else
> +		rate = 25000000;
> +	return rate;
> +}
> +
> +
>  static unsigned long pll_av_get_rate(struct clk *clk)
>  {
>  	void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
> @@ -606,6 +632,25 @@ static int pll_av_set_rate(struct clk *clk, unsigned long rate)
>  	return 0;
>  }
>  
> +static unsigned long pll_av_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	unsigned long parent_rate = clk_get_rate(clk->parent);
> +	u32 div;
> +	u32 mfn, mfd = 1000000;
> +	s64 temp64;
> +
> +	rate = rate < FREQ_650M ? FREQ_650M : rate;
> +	rate = rate > FREQ_1300M ? FREQ_1300M : rate;
> +
> +	div = rate / parent_rate;
> +	temp64 = (u64) (parent_rate - (div * parent_rate));
> +        temp64 *= mfd;
> +        do_div(temp64, parent_rate);
> +        mfn = temp64;
> +
> +        return (parent_rate * div) + ((parent_rate / mfd) * mfn);
> +}
> +
>  static void __iomem *pll_get_div_reg_bit(struct clk *clk, u32 *bp, u32 *bm)
>  {
>  	void __iomem *reg;
> @@ -662,18 +707,33 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
>  	return 0;
>  }
>  
> -#define pll2_bus_get_rate	pll_get_rate
> -#define pll2_bus_set_rate	pll_set_rate
> -#define pll3_usb_otg_get_rate	pll_get_rate
> -#define pll3_usb_otg_set_rate	pll_set_rate
> -#define pll7_usb_host_get_rate	pll_get_rate
> -#define pll7_usb_host_set_rate	pll_set_rate
> -#define pll4_audio_get_rate	pll_av_get_rate
> -#define pll4_audio_set_rate	pll_av_set_rate
> -#define pll5_video_get_rate	pll_av_get_rate
> -#define pll5_video_set_rate	pll_av_set_rate
> -#define pll6_mlb_get_rate	NULL
> -#define pll6_mlb_set_rate	NULL
> +static unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	if (rate >= FREQ_528M)
> +		rate = FREQ_528M;
> +	else
> +		rate = FREQ_480M;
> +	return rate;
> +}
> +
> +#define pll2_bus_get_rate		pll_get_rate
> +#define pll2_bus_set_rate		pll_set_rate
> +#define pll2_bus_round_rate		pll_round_rate
> +#define pll3_usb_otg_get_rate		pll_get_rate
> +#define pll3_usb_otg_set_rate		pll_set_rate
> +#define pll3_usb_otg_round_rate		pll_round_rate
> +#define pll7_usb_host_get_rate		pll_get_rate
> +#define pll7_usb_host_set_rate		pll_set_rate
> +#define pll7_usb_host_round_rate	pll_round_rate
> +#define pll4_audio_get_rate		pll_av_get_rate
> +#define pll4_audio_set_rate		pll_av_set_rate
> +#define pll4_audio_round_rate		pll_av_round_rate
> +#define pll5_video_get_rate		pll_av_get_rate
> +#define pll5_video_set_rate		pll_av_set_rate
> +#define pll5_video_round_rate		pll_av_round_rate
> +#define pll6_mlb_get_rate		NULL
> +#define pll6_mlb_set_rate		NULL
> +#define pll6_mlb_round_rate		NULL
>  
>  #define DEF_PLL(name)					\
>  	static struct clk name = {			\
> @@ -681,6 +741,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
>  		.disable	= pll_disable,		\
>  		.get_rate	= name##_get_rate,	\
>  		.set_rate	= name##_set_rate,	\
> +		.round_rate	= name##_round_rate,	\

I hope this ## stuff is gone soon with the generic clock framework. It
is so ugly and inefficient.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From richard.zhao at freescale.com  Wed Mar 14 04:54:14 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Wed, 14 Mar 2012 16:54:14 +0800
Subject: [PATCH v6 3/3] clk: basic clock hardware types
In-Reply-To: <1331366064-1273-4-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-4-git-send-email-mturquette@linaro.org>
Message-ID: <20120314085413.GG3261@b20223-02.ap.freescale.net>

Hi Mike,

> +static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
> +		unsigned long *best_parent_rate)
> +{
> +	struct clk_divider *divider = to_clk_divider(hw);
> +	int i, bestdiv = 0;
> +	unsigned long parent_rate, best = 0, now, maxdiv;
> +
> +	maxdiv = (1 << divider->width);
> +
> +	if (divider->flags & CLK_DIVIDER_ONE_BASED)
> +		maxdiv--;
> +
> +	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
> +		parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
> +		bestdiv = parent_rate / rate;
> +		bestdiv = bestdiv == 0 ? 1 : bestdiv;
> +		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
> +		goto out;
> +	}
> +
> +	/*
> +	 * The maximum divider we can use without overflowing
> +	 * unsigned long in rate * i below
> +	 */
> +	maxdiv = min(ULONG_MAX / rate, maxdiv);
> +
> +	for (i = 1; i <= maxdiv; i++) {
> +		int div;
> +		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
> +				rate * i);
> +		div = parent_rate / rate;
> +		div = div > maxdiv ? maxdiv : div;
> +		div = div < 1 ? 1 : div;
> +		now = parent_rate / div;
> +
> +		if (now <= rate && now >= best) {
> +			bestdiv = div;
> +			best = now;
> +			*best_parent_rate = parent_rate;
			if (now == rate)
				break;
we don't need it to loop to end, and smaller parent_rate is better.
> +		}
> +	}
> +
> +	if (!bestdiv) {
> +		bestdiv = (1 << divider->width);
> +		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
> +	} else {
> +		parent_rate = best * bestdiv;
> +	}
> +
> +out:
> +	if (best_parent_rate)
> +		*best_parent_rate = parent_rate;
> +
> +	return bestdiv;
> +}



From plagnioj at jcrosoft.com  Wed Mar 14 04:48:38 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 14 Mar 2012 09:48:38 +0100
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <1331650032-15274-1-git-send-email-sr@denx.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
Message-ID: <20120314084838.GJ18320@game.jcrosoft.org>

On 15:47 Tue 13 Mar     , Stefan Roese wrote:
> This patch adds a generic target for SPEAr600 board that can be
> configured via the device-tree. Currently only interrupts are
> configured via device-tree. Other peripheral devices (e.g.
> ethernet, I2C, SMI flash, FSMC NAND flash etc) will follow in
> later patches.
> 
> Only the spear600-evb is currently supported. Other SPEAr600
> based boards will follow later.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> ---
>  Documentation/devicetree/bindings/arm/spear.txt |    6 ++
>  arch/arm/boot/dts/spear600-evb.dts              |   23 +++++++
>  arch/arm/boot/dts/spear600.dtsi                 |   49 +++++++++++++++
>  arch/arm/mach-spear6xx/Kconfig                  |    7 +++
>  arch/arm/mach-spear6xx/Makefile                 |    1 +
>  arch/arm/mach-spear6xx/board-dt.c               |   75 +++++++++++++++++++++++
>  6 files changed, 161 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
>  create mode 100644 arch/arm/boot/dts/spear600-evb.dts
>  create mode 100644 arch/arm/boot/dts/spear600.dtsi
>  create mode 100644 arch/arm/mach-spear6xx/board-dt.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
> new file mode 100644
> index 0000000..8e9f83e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/spear.txt
> @@ -0,0 +1,6 @@
> +ST SPEAr Platforms Device Tree Bindings
> +---------------------------------------
> +
> +SPEAr600 EVB (Evaluation Board)
> +Required root node properties:
> +    - compatible = "st,spear600-evb";
> diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
> new file mode 100644
> index 0000000..f92d099
> --- /dev/null
> +++ b/arch/arm/boot/dts/spear600-evb.dts
> @@ -0,0 +1,23 @@
> +/*
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
freescale for a ST SoC ??
> + *
> + * Copyright 2012 Stefan Roese <sr at denx.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "spear600.dtsi"
> +
> +/ {
> +	model = "ST SPEAr600 Evaluation Board";
> +	compatible = "st,spear600-evb";
put the soc too
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +};

put the board memory
> diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
> new file mode 100644
> index 0000000..82b086d
> --- /dev/null
> +++ b/arch/arm/boot/dts/spear600.dtsi
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + * Copyright 2011 Linaro Ltd.
> + *
> + * Copyright 2012 Stefan Roese <sr at denx.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	cpus {
> +		cpu at 0 {
> +			compatible = "arm,arm926ejs";
> +		};
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0 0>; /* Filled by U-Boot */
here the max and do not expect the bootloader to do it
put the min of the board
> +	};
> +
> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		vic0: interrupt-controller at f1100000 {
> +			compatible = "arm,pl190-vic";
> +			interrupt-controller;
> +			reg = <0xf1100000 0x1000>;
> +			#interrupt-cells = <1>;
> +		};
> +
> +		vic1: interrupt-controller at f1000000 {
> +			compatible = "arm,pl190-vic";
> +			interrupt-controller;
> +			reg = <0xf1000000 0x1000>;
> +			#interrupt-cells = <1>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
> index ff4ae5b..7777f72 100644
> --- a/arch/arm/mach-spear6xx/Kconfig
> +++ b/arch/arm/mach-spear6xx/Kconfig
> @@ -11,6 +11,13 @@ config BOARD_SPEAR600_EVB
>  	help
>  	  Supports ST SPEAr600 Evaluation Board
>  
> +config BOARD_SPEAR600_DT
> +	bool "SPEAr600 generic board configured via device-tree"
> +	select MACH_SPEAR600
> +	select USE_OF
> +	help
> +	  Supports ST SPEAr600 boards configured via the device-tree
> +
>  endmenu
>  
>  config MACH_SPEAR600
> diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
> index cc1a4d8..e2d79b8 100644
> --- a/arch/arm/mach-spear6xx/Makefile
> +++ b/arch/arm/mach-spear6xx/Makefile
> @@ -10,3 +10,4 @@ obj-$(CONFIG_MACH_SPEAR600) += spear600.o
>  
>  # spear600 boards files
>  obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
> +obj-$(CONFIG_BOARD_SPEAR600_DT) += board-dt.o
> diff --git a/arch/arm/mach-spear6xx/board-dt.c b/arch/arm/mach-spear6xx/board-dt.c
> new file mode 100644
> index 0000000..ee4ff33
> --- /dev/null
> +++ b/arch/arm/mach-spear6xx/board-dt.c
> @@ -0,0 +1,75 @@
> +/*
> + * arch/arm/mach-spear6xx/board-dt.c
> + *
> + * Generic SPEAr600 platform support
> + *
> + * Copyright (C) 2009 ST Microelectronics
> + * Viresh Kumar<viresh.kumar at st.com>
> + *
> + * Copyright 2012 Stefan Roese <sr at denx.de>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <asm/hardware/vic.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach-types.h>
> +#include <mach/generic.h>
> +#include <mach/hardware.h>
> +
> +static struct amba_device *amba_devs[] __initdata = {
> +	&gpio_device[0],
> +	&gpio_device[1],
> +	&gpio_device[2],
> +	&uart_device[0],
> +	&uart_device[1],
> +};
there is no bining?
> +
> +static struct platform_device *plat_devs[] __initdata = {
> +};
> +
> +static void __init spear600_dt_init(void)
> +{
> +	unsigned int i;
> +
> +	/* call spear600 machine init function */
> +	spear600_init();
> +
> +	/* Add Platform Devices */
> +	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
> +
> +	/* Add Amba Devices */
> +	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
> +		amba_device_register(amba_devs[i], &iomem_resource);
> +}
> +
> +static const char *spear600_dt_board_compat[] = {
> +	"st,spear600-evb",
> +	NULL
> +};
put the soc instead of the list of bord

Best Regards,
J.


From linus.walleij at linaro.org  Wed Mar 14 05:01:00 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 14 Mar 2012 10:01:00 +0100
Subject: [PATCH 3/3] led-triggers: create a trigger for CPU activity
In-Reply-To: <20120313161138.cbeb594d.akpm@linux-foundation.org>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
 <1331197863-25564-3-git-send-email-bryan.wu@canonical.com>
 <20120313161138.cbeb594d.akpm@linux-foundation.org>
Message-ID: <CACRpkdYMgRsJaKSNhChWvZGj497pgGYWTh26oSCXSYjYr8_JxA@mail.gmail.com>

On Wed, Mar 14, 2012 at 12:11 AM, Andrew Morton
<akpm at linux-foundation.org> wrote:
> On Thu, ?8 Mar 2012 17:11:03 +0800
> Bryan Wu <bryan.wu at canonical.com> wrote:
>
>> Attempting to consolidate the ARM LED code, this removes the
>> custom RealView LED trigger code to turn LEDs on and off in
>> response to CPU activity and replace it with a standard trigger.
>>
>> (bryan.wu at canonical.com:
>> It moves arch/arm/kernel/leds.c syscore stubs into this trigger.
>> It also provides ledtrig_cpu trigger event stub in <linux/leds.h>.
>> Although it was inspired by ARM work, it can be used in other arch.)
>
> The patch doesn't "remove" or "move" anything. ?It wholly consists of
> additions. ?Confused.
>
>> Cc: Richard Purdie <rpurdie at rpsys.net>
>> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
>> Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
>> Reviewed-by: Jamie Iles <jamie at jamieiles.com>
>> Tested-by: Jochen Friedrich <jochen at scram.de>
>
> The authorship is a bit unclear. ?You're the primary author, yes?

It's based on a patch I wrote ages ago, but I don't care much.
Since Bryan's been driving it since, let's say Bryan wrote it.
Just remove the signoff if it's confusing.

Linus Walleij


From s.hauer at pengutronix.de  Wed Mar 14 05:01:15 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 14 Mar 2012 10:01:15 +0100
Subject: [PATCH v4] ASoC: add imx-sgtl5000 machine driver working with
 fsl_ssi
In-Reply-To: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120314090115.GN3852@pengutronix.de>

On Mon, Mar 12, 2012 at 07:58:47PM +0800, Shawn Guo wrote:
> Changes since v3:
>  * Change imx compatible to "fsl,imx21-ssi"
>  * Leave locking issue as a FIXME for Timur to sort out separately
> 
> ---
> Shawn Guo (10):
>       ASoC: fsl: separate SSI and DMA Kconfig options
>       ASoC: imx: merge sound/soc/imx into sound/soc/fsl
>       ASoC: fsl: rename imx-pcm Kconfig options and filename
>       ASoC: fsl: create fsl_utils to accommodate the common functions
>       ASoC: fsl: remove helper fsl_asoc_get_codec_dev_name
>       ASoC: fsl: check property 'compatible' for the machine name
>       ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
>       ASoC: fsl: remove the fatal error checking on codec-handle
>       ASoC: fsl: let fsl_ssi work with imx pcm and machine drivers
>       ASoC: fsl: add imx-sgtl5000 machine driver

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

What are the next steps here? Now we have fsl_ssi.c and imx-ssi.c, one
for dt bindings and the other one for platform bindings and also AC97
support. They should probably get merged some day which might be a bit
difficult since currently I don't see the platform users moving over
to devicetree and the seem to be no AC97 users in powerpc.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linus.walleij at linaro.org  Wed Mar 14 05:02:22 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 14 Mar 2012 10:02:22 +0100
Subject: [PATCH v3] serial: PL011: clear pending interrupts
In-Reply-To: <CAOAMb1AKmsNQbmVAaYq5G8cdafCVpRyA=5xgocqYfLsQ6BLXMw@mail.gmail.com>
References: <1331641643-25929-1-git-send-email-linus.walleij@stericsson.com>
 <CAOAMb1AKmsNQbmVAaYq5G8cdafCVpRyA=5xgocqYfLsQ6BLXMw@mail.gmail.com>
Message-ID: <CACRpkdZXrMW653W=tysY8ncqBKDun3TgPqnEzrdZPqwpW8shYA@mail.gmail.com>

On Wed, Mar 14, 2012 at 2:47 AM, Chanho Min <chanho0207 at gmail.com> wrote:
>
> I've tested this patch, and have confirmed that the issue is resolved
> on our CA9 platform.
> In addition, May I ask to change the tag as follows.
>
> Reported-by: Chanho Min <chanho.min at lge.com>
> Reviewed-by: Jong-Sung Kim <neidhard.kim at lge.com>

Thanks Chanho, Greg will you add the Reported/Reviewed-by
tags or do you want me to send a v4 of this?

Yours,
Linus Walleij


From plagnioj at jcrosoft.com  Wed Mar 14 04:52:52 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 14 Mar 2012 09:52:52 +0100
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <20120314080939.GA1180@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-3-git-send-email-b29396@freescale.com>
 <20120314072343.GG18320@game.jcrosoft.org>
 <20120314080939.GA1180@shlinux2.ap.freescale.net>
Message-ID: <20120314085252.GK18320@game.jcrosoft.org>

On 16:09 Wed 14 Mar     , Dong Aisheng wrote:
> On Wed, Mar 14, 2012 at 03:23:43PM +0800, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 16:47 Tue 13 Mar     , Dong Aisheng wrote:
> > > From: Dong Aisheng <dong.aisheng at linaro.org>
> > > 
> > > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > > 
> > > ---
> > > The patch is still using a private way for dma part binding
> > > since the common dma binding is still under discussion.
> > > http://www.spinics.net/lists/linux-omap/msg65528.html
> > > 
> > > Will update to use common dma binding when it hits mainline.
> > > ---
> > >  .../devicetree/bindings/mmc/fsl-mxs-mmc.txt        |   23 ++++++
> > >  drivers/mmc/host/mxs-mmc.c                         |   82 +++++++++++++++++++-
> > >  2 files changed, 102 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> > > new file mode 100644
> > > index 0000000..adc1142
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/mmc/fsl-mxs-mmc.txt
> > > @@ -0,0 +1,23 @@
> > > +* FREESCALE MXS MMC peripheral
> > > +
> > > +Required properties:
> > > +- compatible : Should be "fsl,<chip>-mmc"
> > > +- reg : Should contain registers location and length
> > > +- interrupts : Should contain interrupt.
> > > +  The format is <irq_err irq_dma>.
> > > +- dma_channel: Should contain the dma channel it uses
> > > +
> > > +Optional properties:
> > > +- wp-gpios : Specify GPIOs for write protection
> > > +- slot-4bit: Specify 4 bit mode support
> > > +- slot-8bit: Specify 8 bit and 4 bit mode support
> > > +
> > > +Examples:
> > > +mmc1: ssp at 80010000 {
> > > +	compatible = "fsl,imx28-mmc";
> > > +	reg = <0x80010000 2000>;
> > > +	/* <irq_err irq_dma> */
> > > +	interrupts = <96 82>;
> > > +	dma_channel = <0>;
> > > +	slot-8bit;
> > > +};
> > > diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
> > > index 382c835..6cf2d17 100644
> > > --- a/drivers/mmc/host/mxs-mmc.c
> > > +++ b/drivers/mmc/host/mxs-mmc.c
> > > @@ -38,6 +38,10 @@
> > >  #include <linux/gpio.h>
> > >  #include <linux/regulator/consumer.h>
> > >  #include <linux/module.h>
> > > +#include <linux/of.h>
> > > +#include <linux/of_device.h>
> > > +#include <linux/of_gpio.h>
> > > +#include <linux/slab.h>
> > >  
> > >  #include <mach/mxs.h>
> > >  #include <mach/common.h>
> > > @@ -673,17 +677,79 @@ static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
> > >  	return true;
> > >  }
> > >  
> > > +#ifdef CONFIG_OF
> > > +static struct resource * __devinit mxs_mmc_get_of_dmares(
> > > +				struct platform_device *pdev)
> > > +{
> > > +	struct device_node *np = pdev->dev.of_node;
> > > +	struct resource *dmares;
> > > +	int ret;
> > > +
> > > +	if (!np)
> > > +		return NULL;
> > > +
> > > +	dmares = kzalloc(sizeof(*dmares), GFP_KERNEL);
> > > +	dmares->flags = IORESOURCE_DMA;
> > > +	ret = of_property_read_u32(np, "dma_channel", &dmares->start);
> > > +	if (ret) {
> > > +		dev_err(&pdev->dev, "unable to get dmares from dt\n");
> > > +		return NULL;
> > > +	}
> > > +	dmares->end = dmares->start;
> > > +
> > > +	return dmares;
> > > +}
> > > +
> > > +static int __devinit mxs_mmc_get_of_property(struct platform_device *pdev,
> > > +				struct mxs_mmc_platform_data **ppdata)
> > > +{
> > > +	struct device_node *np = pdev->dev.of_node;
> > > +	struct mxs_mmc_platform_data *pdata = *ppdata;
> > > +
> > > +	if (!np)
> > > +		return -ENODEV;
> > > +
> > > +	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
> > > +
> > > +	if (of_get_property(np, "slot-8bit", NULL))
> > > +		pdata->flags |= SLOTF_8_BIT_CAPABLE;
> > > +
> > > +	if (of_get_property(np, "slot-4bit", NULL))
> > > +		pdata->flags |= SLOTF_4_BIT_CAPABLE;
> > it will conflit if both binding are set use a number instead
> > 
> Hmm, i did not see conflict, can you explain more?
> The "slot-8bit" includes the support for 4bit.(see binding doc)
> Even user define them two property in dt by mistake, it does not cause conflict.
> See:
> if (pdata) {
> 	if (pdata->flags & SLOTF_8_BIT_CAPABLE)
> 		mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
> 	if (pdata->flags & SLOTF_4_BIT_CAPABLE)
> 		mmc->caps |= MMC_CAP_4_BIT_DATA;
> }

this is mmc specifc sohould have a generic binding

Best Regards,
J.


From plagnioj at jcrosoft.com  Wed Mar 14 04:54:47 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 14 Mar 2012 09:54:47 +0100
Subject: [PATCH v1 3/5] ARM: imx28evk: add mmc dt support
In-Reply-To: <20120314082024.GB1180@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-4-git-send-email-b29396@freescale.com>
 <4F5F5C22.1080506@gmail.com>
 <20120313165214.GO26642@pengutronix.de>
 <4F5F879E.4030407@gmail.com>
 <20120314073035.GI18320@game.jcrosoft.org>
 <20120314082024.GB1180@shlinux2.ap.freescale.net>
Message-ID: <20120314085447.GL18320@game.jcrosoft.org>

On 16:20 Wed 14 Mar     , Dong Aisheng wrote:
> On Wed, Mar 14, 2012 at 03:30:35PM +0800, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 12:45 Tue 13 Mar     , Rob Herring wrote:
> > > On 03/13/2012 11:52 AM, Sascha Hauer wrote:
> > > > On Tue, Mar 13, 2012 at 09:39:30AM -0500, Rob Herring wrote:
> > > >> On 03/13/2012 03:47 AM, Dong Aisheng wrote:
> > > >>> From: Dong Aisheng <dong.aisheng at linaro.org>
> > > >>>
> > > >>> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > > >>> ---
> > > >>>  arch/arm/boot/dts/imx28-evk.dts |   14 ++++++++++++++
> > > >>>  arch/arm/boot/dts/imx28.dtsi    |   33 +++++++++++++++++++++++++++++++++
> > > >>>  arch/arm/mach-mxs/imx28-dt.c    |    2 ++
> > > >>>  3 files changed, 49 insertions(+), 0 deletions(-)
> > > >>
> > > >> snip
> > > >>
> > > >>> diff --git a/arch/arm/mach-mxs/imx28-dt.c b/arch/arm/mach-mxs/imx28-dt.c
> > > >>> index 78d1129..429b88e 100644
> > > >>> --- a/arch/arm/mach-mxs/imx28-dt.c
> > > >>> +++ b/arch/arm/mach-mxs/imx28-dt.c
> > > >>> @@ -23,6 +23,8 @@ static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
> > > >>>  	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
> > > >>>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
> > > >>>  	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
> > > >>> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP0_BASE_ADDR, "mxs-mmc.0", NULL),
> > > >>> +	OF_DEV_AUXDATA("fsl,imx28-mmc", MX28_SSP1_BASE_ADDR, "mxs-mmc.1", NULL),
> > > >>
> > > >> Why is this needed?
> > > > 
> > > > These are needed for the drivers which have still the mxs-mmc.* names
> > > > to find their clocks. Alternatively we could also add the appropriate
> > > > clocks to the clock file. Don't know if that's better though.
> > > 
> > > Ah, yes I should have known that... If clk lookup is all that's needed,
> > > I'd suggest adding the necessary clk lookups either here or in the clock
> > > code. Not much difference, but at least it removes the use of
> > > *_BASE_ADDR defines.
> > Agreed we do this on AT91
> > 
> I'm willing to do like that.
> But i'm new to this, can you help point our where the code i can reference
> in Rob suggested way?
mach-at91

Best Regards,
J.


From kumarrav at codeaurora.org  Wed Mar 14 05:18:40 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Wed, 14 Mar 2012 14:48:40 +0530
Subject: [PATCH v3 1/2] dmaengine: Add support for per xfer specific
 privatedata
In-Reply-To: <1331569796.1727.9.camel@vkoul-udesk3>
References: <1331548336-27802-1-git-send-email-kumarrav@codeaurora.org>
 <1331569796.1727.9.camel@vkoul-udesk3>
Message-ID: <4F606270.1020709@codeaurora.org>

On 3/12/2012 9:59 PM, Vinod Koul wrote:
> On Mon, 2012-03-12 at 16:02 +0530, Ravi Kumar V wrote:
>> Add new argument to DMA SG and Interleave mode for passing
>> per transfer specific private data, using this it enables the
>> dma devices which needs to pass the parameters which changes per
>> each transfer.
>>
>> Signed-off-by: Ravi Kumar V<kumarrav at codeaurora.org>
>> ---
>>   include/linux/dmaengine.h |    4 ++--
>>   1 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
>> index 679b349..b8f0495 100644
>> --- a/include/linux/dmaengine.h
>> +++ b/include/linux/dmaengine.h
>> @@ -570,7 +570,7 @@ struct dma_device {
>>   		struct dma_chan *chan,
>>   		struct scatterlist *dst_sg, unsigned int dst_nents,
>>   		struct scatterlist *src_sg, unsigned int src_nents,
>> -		unsigned long flags);
>> +		unsigned long flags, void *context);
> Please follow the related discussion we had. Alexandre had already
> posted updated and this needs to follow.
> Also this way you break the existing drivers which use this API, not
> sure why you posted without fixing them?
>
I have gone through the discussion in
https://lkml.org/lkml/2012/2/6/300
As per my understanding
1.we need to add new transaction types DMA_SG_EXT & DMA_INTERLEAVE_EXT.
2.Add context parameter to existing API's.
3.Typecast the context parameter with architecture specific structure 
there by restricting client drivers to pass only arch specific parameter.
4.Fix existing code and client drivers for using new API.

My suggestion is instead of adding context parameter in existing API's, 
how it would be if we can add a new API for each DMA transaction types 
available in dmaengine for passing transaction specific parameter?
so that existing clients and dma drivers will not be disturbed.

>>   	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
>>   		struct dma_chan *chan, struct scatterlist *sgl,
>> @@ -581,7 +581,7 @@ struct dma_device {
>>   		size_t period_len, enum dma_transfer_direction direction);
>>   	struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
>>   		struct dma_chan *chan, struct dma_interleaved_template *xt,
>> -		unsigned long flags);
>> +		unsigned long flags, void *context);
>>   	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
>>   		unsigned long arg);
>>
>
>


-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From chanho0207 at gmail.com  Wed Mar 14 05:21:58 2012
From: chanho0207 at gmail.com (Chanho Min)
Date: Wed, 14 Mar 2012 18:21:58 +0900
Subject: [PATCH v3] serial: PL011: clear pending interrupts
In-Reply-To: <CACRpkdZXrMW653W=tysY8ncqBKDun3TgPqnEzrdZPqwpW8shYA@mail.gmail.com>
References: <1331641643-25929-1-git-send-email-linus.walleij@stericsson.com>
 <CAOAMb1AKmsNQbmVAaYq5G8cdafCVpRyA=5xgocqYfLsQ6BLXMw@mail.gmail.com>
 <CACRpkdZXrMW653W=tysY8ncqBKDun3TgPqnEzrdZPqwpW8shYA@mail.gmail.com>
Message-ID: <CAOAMb1DX_-4ww7ogTb7WUeZUa4ShUa=Fqwh+kkhv7RX40xu9Sg@mail.gmail.com>

On Wed, Mar 14, 2012 at 6:02 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> Thanks Chanho, Greg will you add the Reported/Reviewed-by
> tags or do you want me to send a v4 of this?
>
> Yours,
> Linus Walleij
No, you don't need to send it again if greg will do it.

Thanks,
Chanho Min


From plagnioj at jcrosoft.com  Wed Mar 14 05:27:07 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 14 Mar 2012 10:27:07 +0100
Subject: [PATCH 7/9] usb: add Atmel USBA UDC DT support
In-Reply-To: <1331111746-21393-7-git-send-email-plagnioj@jcrosoft.com>
References: <20120307084924.GK21255@game.jcrosoft.org>
 <1331111746-21393-7-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120314092707.GM18320@game.jcrosoft.org>

Hi,

	except the boolean that I need to update is it ok?

Best Regards,
J.
On 10:15 Wed 07 Mar     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> Allow to compile the driver all the time if AT91 enabled.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: linux-usb at vger.kernel.org
> ---
> Hi Greg
> 
> 	if it's ok with you I apply with the rest of the USB patch series via
> 	at91
> 
> Best Regards,
> J. .../devicetree/bindings/usb/atmel-usb.txt          |   86 ++++++++
>  drivers/usb/gadget/Kconfig                         |    2 +-
>  drivers/usb/gadget/atmel_usba_udc.c                |  209 +++++++++++++++-----
>  drivers/usb/gadget/atmel_usba_udc.h                |    1 +
>  4 files changed, 248 insertions(+), 50 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
> index 60bd215..b44f87e 100644
> --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
> +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
> @@ -47,3 +47,89 @@ usb1: gadget at fffa4000 {
>  	interrupts = <10 4>;
>  	atmel,vbus-gpio = <&pioC 5 0>;
>  };
> +
> +Atmel High-Speed USB device controller
> +
> +Required properties:
> + - compatible: Should be "atmel,at91sam9rl-udc"
> + - reg: Address and length of the register set for the device
> + - interrupts: Should contain macb interrupt
> + - ep childnode: To specifiy the number of endpoints and their properties.
> +
> +Optional properties:
> + - atmel,vbus-gpio: If present, specifies a gpio that needs to be
> +   activated for the bus to be powered.
> +
> +Required child node properties:
> + - name: Name of the endpoint.
> + - reg: Num of the endpoint.
> + - atmel,fifo-size: Size of the fifo.
> + - atmel,nb-banks: Number of banks.
> + - atmel,can-dma: Boolean to specify if the endpoint support DMA.
> + - atmel,can-isoc: Boolean to specify if the endpoint support ISOC.
> +
> +usb2: gadget at fff78000 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	compatible = "atmel,at91sam9rl-udc";
> +	reg = <0x00600000 0x80000
> +	       0xfff78000 0x400>;
> +	interrupts = <27 4>;
> +	atmel,vbus-gpio = <&pioB 19 0>;
> +
> +	ep0 {
> +		reg = <0>;
> +		atmel,fifo-size = <64>;
> +		atmel,nb-banks = <1>;
> +		atmel,can-dma = <0>;
> +		atmel,can-isoc = <0>;
> +	};
> +
> +	ep1 {
> +		reg = <1>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <2>;
> +		atmel,can-dma = <1>;
> +		atmel,can-isoc = <1>;
> +	};
> +
> +	ep2 {
> +		reg = <2>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <2>;
> +		atmel,can-dma = <1>;
> +		atmel,can-isoc = <1>;
> +	};
> +
> +	ep3 {
> +		reg = <3>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <3>;
> +		atmel,can-dma = <1>;
> +		atmel,can-isoc = <0>;
> +	};
> +
> +	ep4 {
> +		reg = <4>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <3>;
> +		atmel,can-dma = <1>;
> +		atmel,can-isoc = <0>;
> +	};
> +
> +	ep5 {
> +		reg = <5>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <3>;
> +		atmel,can-dma = <1>;
> +		atmel,can-isoc = <1>;
> +	};
> +
> +	ep6 {
> +		reg = <6>;
> +		atmel,fifo-size = <1024>;
> +		atmel,nb-banks = <3>;
> +		atmel,can-dma = <1>;
> +		atmel,can-isoc = <1>;
> +	};
> +};
> diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
> index edf1144..1dbba6c 100644
> --- a/drivers/usb/gadget/Kconfig
> +++ b/drivers/usb/gadget/Kconfig
> @@ -150,7 +150,7 @@ config USB_AT91
>  config USB_ATMEL_USBA
>  	tristate "Atmel USBA"
>  	select USB_GADGET_DUALSPEED
> -	depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
> +	depends on AVR32 || ARCH_AT91
>  	help
>  	  USBA is the integrated high-speed USB Device controller on
>  	  the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
> diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
> index ce9dffb..234eabb 100644
> --- a/drivers/usb/gadget/atmel_usba_udc.c
> +++ b/drivers/usb/gadget/atmel_usba_udc.c
> @@ -21,6 +21,8 @@
>  #include <linux/usb/gadget.h>
>  #include <linux/usb/atmel_usba_udc.h>
>  #include <linux/delay.h>
> +#include <linux/of.h>
> +#include <linux/of_gpio.h>
>  
>  #include <asm/gpio.h>
>  #include <mach/board.h>
> @@ -1885,9 +1887,143 @@ static int atmel_usba_stop(struct usb_gadget_driver *driver)
>  	return 0;
>  }
>  
> -static int __init usba_udc_probe(struct platform_device *pdev)
> +#ifdef CONFIG_OF
> +static struct usba_ep * __devinit atmel_udc_of_init(struct platform_device *pdev,
> +						    struct usba_udc *udc)
> +{
> +	u32 val;
> +	const char *name;
> +	enum of_gpio_flags flags;
> +	struct device_node *np = pdev->dev.of_node;
> +	struct device_node *pp;
> +	int i, ret;
> +	struct usba_ep *eps, *ep;
> +
> +	udc->num_ep = 0;
> +
> +	udc->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0,
> +						&flags);
> +	udc->vbus_pin_inverted = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0;
> +
> +	pp = NULL;
> +	while ((pp = of_get_next_child(np, pp)))
> +		udc->num_ep++;
> +
> +	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * udc->num_ep,
> +			   GFP_KERNEL);
> +	if (!eps)
> +		return ERR_PTR(-ENOMEM);
> +
> +	udc->gadget.ep0 = &eps[0].ep;
> +
> +	INIT_LIST_HEAD(&eps[0].ep.ep_list);
> +
> +	pp = NULL;
> +	i = 0;
> +	while ((pp = of_get_next_child(np, pp))) {
> +		ep = &eps[i];
> +
> +		ret = of_property_read_u32(pp, "reg", &val);
> +		if (ret) {
> +			dev_err(&pdev->dev, "of_probe: reg error(%d)\n", ret);
> +			goto err;
> +		}
> +		ep->index = val;
> +
> +		ret = of_property_read_u32(pp, "atmel,fifo-size", &val);
> +		if (ret) {
> +			dev_err(&pdev->dev, "of_probe: fifo-size error(%d)\n", ret);
> +			goto err;
> +		}
> +		ep->fifo_size = val;
> +
> +		ret = of_property_read_u32(pp, "atmel,nb-banks", &val);
> +		if (ret) {
> +			dev_err(&pdev->dev, "of_probe: nb-banks error(%d)\n", ret);
> +			goto err;
> +		}
> +		ep->nr_banks = val;
> +
> +		ep->can_dma = of_property_read_bool(pp, "atmel,can-dma");
> +		ep->can_isoc = of_property_read_bool(pp, "atmel,can-isoc");
> +
> +		ret = of_property_read_string(pp, "name", &name);
> +		ep->ep.name = name;
> +
> +		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
> +		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
> +		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
> +		ep->ep.ops = &usba_ep_ops;
> +		ep->ep.maxpacket = ep->fifo_size;
> +		ep->udc = udc;
> +		INIT_LIST_HEAD(&ep->queue);
> +
> +		if (i)
> +			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
> +
> +		i++;
> +	}
> +
> +	return eps;
> +err:
> +	return ERR_PTR(ret);
> +}
> +#else
> +static struct usba_ep * __devinit atmel_udc_of_init(struct platform_device *pdev,
> +						    struct usba_udc *udc)
> +{
> +	return ERR_PTR(-ENOSYS);
> +}
> +#endif
> +
> +static struct usba_ep * __devinit usba_udc_pdata(struct platform_device *pdev,
> +						 struct usba_udc *udc)
>  {
>  	struct usba_platform_data *pdata = pdev->dev.platform_data;
> +	struct usba_ep *eps;
> +	int i;
> +
> +	if (!pdata)
> +		return ERR_PTR(-ENXIO);
> +
> +	eps = devm_kzalloc(&pdev->dev, sizeof(struct usba_ep) * pdata->num_ep,
> +			   GFP_KERNEL);
> +	if (!eps)
> +		return ERR_PTR(-ENOMEM);
> +
> +	udc->gadget.ep0 = &eps[0].ep;
> +
> +	udc->vbus_pin = pdata->vbus_pin;
> +	udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
> +	udc->num_ep = pdata->num_ep;
> +
> +	INIT_LIST_HEAD(&eps[0].ep.ep_list);
> +
> +	for (i = 0; i < pdata->num_ep; i++) {
> +		struct usba_ep *ep = &eps[i];
> +
> +		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
> +		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
> +		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
> +		ep->ep.ops = &usba_ep_ops;
> +		ep->ep.name = pdata->ep[i].name;
> +		ep->fifo_size = ep->ep.maxpacket = pdata->ep[i].fifo_size;
> +		ep->udc = udc;
> +		INIT_LIST_HEAD(&ep->queue);
> +		ep->nr_banks = pdata->ep[i].nr_banks;
> +		ep->index = pdata->ep[i].index;
> +		ep->can_dma = pdata->ep[i].can_dma;
> +		ep->can_isoc = pdata->ep[i].can_isoc;
> +
> +		if (i)
> +			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
> +	}
> +
> +	return eps;
> +}
> +
> +static int __init usba_udc_probe(struct platform_device *pdev)
> +{
>  	struct resource *regs, *fifo;
>  	struct clk *pclk, *hclk;
>  	struct usba_udc *udc = &the_udc;
> @@ -1895,7 +2031,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>  
>  	regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
>  	fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
> -	if (!regs || !fifo || !pdata)
> +	if (!regs || !fifo)
>  		return -ENXIO;
>  
>  	irq = platform_get_irq(pdev, 0);
> @@ -1945,46 +2081,14 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>  	usba_writel(udc, CTRL, USBA_DISABLE_MASK);
>  	clk_disable(pclk);
>  
> -	usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
> -			  GFP_KERNEL);
> -	if (!usba_ep)
> -		goto err_alloc_ep;
> -
> -	the_udc.gadget.ep0 = &usba_ep[0].ep;
> -
> -	INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
> -	usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
> -	usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
> -	usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
> -	usba_ep[0].ep.ops = &usba_ep_ops;
> -	usba_ep[0].ep.name = pdata->ep[0].name;
> -	usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
> -	usba_ep[0].udc = &the_udc;
> -	INIT_LIST_HEAD(&usba_ep[0].queue);
> -	usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
> -	usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
> -	usba_ep[0].index = pdata->ep[0].index;
> -	usba_ep[0].can_dma = pdata->ep[0].can_dma;
> -	usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
> -
> -	for (i = 1; i < pdata->num_ep; i++) {
> -		struct usba_ep *ep = &usba_ep[i];
> -
> -		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
> -		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
> -		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
> -		ep->ep.ops = &usba_ep_ops;
> -		ep->ep.name = pdata->ep[i].name;
> -		ep->ep.maxpacket = pdata->ep[i].fifo_size;
> -		ep->udc = &the_udc;
> -		INIT_LIST_HEAD(&ep->queue);
> -		ep->fifo_size = pdata->ep[i].fifo_size;
> -		ep->nr_banks = pdata->ep[i].nr_banks;
> -		ep->index = pdata->ep[i].index;
> -		ep->can_dma = pdata->ep[i].can_dma;
> -		ep->can_isoc = pdata->ep[i].can_isoc;
> +	if (pdev->dev.of_node)
> +		usba_ep = atmel_udc_of_init(pdev, udc);
> +	else
> +		usba_ep = usba_udc_pdata(pdev, udc);
>  
> -		list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
> +	if (IS_ERR(usba_ep)) {
> +		ret = PTR_ERR(usba_ep);
> +		goto err_alloc_ep;
>  	}
>  
>  	ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
> @@ -2001,10 +2105,8 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>  		goto err_device_add;
>  	}
>  
> -	if (gpio_is_valid(pdata->vbus_pin)) {
> -		if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
> -			udc->vbus_pin = pdata->vbus_pin;
> -			udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
> +	if (gpio_is_valid(udc->vbus_pin)) {
> +		if (!gpio_request(udc->vbus_pin, "atmel_usba_udc")) {
>  
>  			ret = request_irq(gpio_to_irq(udc->vbus_pin),
>  					usba_vbus_irq, 0,
> @@ -2029,13 +2131,13 @@ static int __init usba_udc_probe(struct platform_device *pdev)
>  		goto err_add_udc;
>  
>  	usba_init_debugfs(udc);
> -	for (i = 1; i < pdata->num_ep; i++)
> +	for (i = 1; i < udc->num_ep; i++)
>  		usba_ep_init_debugfs(udc, &usba_ep[i]);
>  
>  	return 0;
>  
>  err_add_udc:
> -	if (gpio_is_valid(pdata->vbus_pin)) {
> +	if (gpio_is_valid(udc->vbus_pin)) {
>  		free_irq(gpio_to_irq(udc->vbus_pin), udc);
>  		gpio_free(udc->vbus_pin);
>  	}
> @@ -2064,13 +2166,12 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
>  {
>  	struct usba_udc *udc;
>  	int i;
> -	struct usba_platform_data *pdata = pdev->dev.platform_data;
>  
>  	udc = platform_get_drvdata(pdev);
>  
>  	usb_del_gadget_udc(&udc->gadget);
>  
> -	for (i = 1; i < pdata->num_ep; i++)
> +	for (i = 1; i < udc->num_ep; i++)
>  		usba_ep_cleanup_debugfs(&usba_ep[i]);
>  	usba_cleanup_debugfs(udc);
>  
> @@ -2091,11 +2192,21 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +#if defined(CONFIG_OF)
> +static const struct of_device_id atmel_udc_dt_ids[] = {
> +	{ .compatible = "atmel,at91sam9rl-udc" },
> +	{ /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
> +#endif
> +
>  static struct platform_driver udc_driver = {
>  	.remove		= __exit_p(usba_udc_remove),
>  	.driver		= {
>  		.name		= "atmel_usba_udc",
>  		.owner		= THIS_MODULE,
> +		.of_match_table	= of_match_ptr(atmel_udc_dt_ids),
>  	},
>  };
>  
> diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
> index 88a2e07..2c068e7 100644
> --- a/drivers/usb/gadget/atmel_usba_udc.h
> +++ b/drivers/usb/gadget/atmel_usba_udc.h
> @@ -324,6 +324,7 @@ struct usba_udc {
>  	int irq;
>  	int vbus_pin;
>  	int vbus_pin_inverted;
> +	int num_ep;
>  	struct clk *pclk;
>  	struct clk *hclk;
>  
> -- 
> 1.7.7
> 


From arnd at arndb.de  Wed Mar 14 05:48:44 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 09:48:44 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203140840.18333.sr@denx.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203131644.12048.arnd@arndb.de> <201203140840.18333.sr@denx.de>
Message-ID: <201203140948.44823.arnd@arndb.de>

On Wednesday 14 March 2012, Stefan Roese wrote:

> > This is very cool, welcome onboard for the DT conversion with spear600!
> > 
> > > +static struct amba_device *amba_devs[] __initdata = {
> > > +	&gpio_device[0],
> > > +	&gpio_device[1],
> > > +	&gpio_device[2],
> > > +	&uart_device[0],
> > > +	&uart_device[1],
> > > +};
> > 
> > I would suggest you convert these to DT next so you can remove the
> > amba_devs list. Which devices are these? If they are pl061 and
> > pl010/pl011, the binding should be really easy to do.
> 
> Yes. I really wanted to do that. But from a quick look at the pl011 driver 
> (drivers/tty/serial/amba-pl011.c), this driver doesn't support DT probing. I 
> might have missed something here though. And ideas?

amba primecell devices don't actually need to register to a "compatible"
property, they are probed using the primecell ID, and the device tree
is just used to tell the system about memory and IRQ resources.

The pl061 driver has support for setting the gc.base and irq_base using
device tree instead of the platform data and that might be enough.

> > Since there is only one upstream board file and that is for the same board,
> > we can soon collapse all of it into the base platform support.
> > 
> > I think you should add all the code from this file to spear6xx.c instead
> > of adding a new file. We can then delete the spear600.c and spear600_evb.c
> > files once the DT support has matured.
> 
> Sounds like a plan. I'll rework the patch soon.

Great!

Don't worry about the the gpio and uart devices if they are not in the
first initial version. I do think that they should be done fairly soon
though, before we get into most of the other devices.

It's ok if you put a lot of the other devices in the dts file though,
like the ethernet device, it gives a better overview of what is actually
there, even if the driver does not actually use it yet.

	Arnd


From s.hauer at pengutronix.de  Wed Mar 14 05:50:50 2012
From: s.hauer at pengutronix.de (Sascha Hauer [s.hauer@pengutronix.de] (s.hauer@pengutronix.de))
Date: Wed, 14 Mar 2012 10:50:50 +0100
Subject: [PATCH] iomux-mx25.h slew rate adjusted for LCD __LD pins
In-Reply-To: <3F263ABB4EDE344D974E1983B56807739E868EAB@EX-DAG01.eckelmann.group>
References: <3F263ABB4EDE344D974E1983B56807739E868EAB@EX-DAG01.eckelmann.group>
Message-ID: <20120314095050.GP26642@pengutronix.de>

On Tue, Mar 13, 2012 at 11:35:22AM +0000, Mehnert, Torsten wrote:
> From: Mehnert <tmehnert at eckelmann.de>
> Date: Mon, 13 Mar 2012 12:13:51 +0100
> Subject: [PATCH] iomux-mx25.h slew rate adjusted for LCD __LD pins
> 
> For some reason (sadly i don't identifying the patch right now)
> two LCD data lines configured PAD_CTL_SRE_SLOW (wrong slew rate)
> since Kernel 3.1. MX25_PAD_GPIO_E__LD16 and MX25_PAD_GPIO_F__LD17
> This results in an fauly behaviour and strange color effects.
> 
> To ensure that all LCD data pins configured with the proper slew rate,
> this patch changes to IOMUX define of all LCD __LDxx pins to PAD_CTL_SRE_FAST.
> 
> This problem may affect other mx25 platforms like mx25pdk. Sadly i can't test
> it. Of course this problem shouldn't occur when you done your LCD muxing 
> correctly in the bootloader.

Your patch lacks a signed-off-by Tag. Please remember adding it next
time. For now it should be enough to answer your original mail with
a

Signed-off-by: Torsten Mehnert <T.Mehnert at eckelmann.de>

Sascha

-- 
Pengutronix e.K.                           |                             |
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Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Wed Mar 14 05:58:26 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 09:58:26 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <4F604400.1040805@st.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203131644.12048.arnd@arndb.de> <4F604400.1040805@st.com>
Message-ID: <201203140958.27289.arnd@arndb.de>

On Wednesday 14 March 2012, Viresh Kumar wrote:
> On 3/13/2012 10:14 PM, Arnd Bergmann wrote:
> > I think you should add all the code from this file to spear6xx.c instead
> > of adding a new file. We can then delete the spear600.c and spear600_evb.c
> > files once the DT support has matured.
> 
> But what if have another board in future, and this is what Stefan is going
> to do soon, as they have another board.
> 
> So we may actually move this code to spear600_evb.c instead.
> 
> Sorry for any bad suggestions, i am new to DT. :)

No problem, we are all learning things as we are working on them.

The idea with DT is that you no longer need any board files because all of
the information in those files is now passed as a data structure to the kernel
at boot time. Platforms that are fully converted to DT don't have any
board files but just have one DT_MACHINE_START entry for all of them in
the common platform files. Since spear600 has very little board specific
contents at the moment, it is very easy to get to this point now, and
that will actually help support other boards without having to do more
patches to add board files.

When this work is completed, we might actually be able to extend the
spear6xx DT code to also support spear3xx and spear13xx, renaming it
to mach-spear. In that case, we would probably need one DT_MACHINE_START
entry for each family and would not be able to actually build 13xx together
with the other ones, but I guess a lot of the infrastructure could be shared.

I would suggest you read Documentation/devicetree/booting-without-of.txt
to get a better understanding of what this is all about.

	Arnd


From thomas.abraham at linaro.org  Wed Mar 14 06:02:49 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 14 Mar 2012 15:32:49 +0530
Subject: [PATCH v3 0/4] ARM: Exynos4: Add irq domain and device tree
 support for wakeup interrupts
In-Reply-To: <4F5A30B8.6060801@samsung.com>
References: <1329912858-32750-1-git-send-email-thomas.abraham@linaro.org>
 <4F5A30B8.6060801@samsung.com>
Message-ID: <CAJuYYwQxiz9tcx=15MK2vvhR71yhQyFBXrVDR0QO4YDdJ4Xvbw@mail.gmail.com>

Dear Mr. Kim,

On 9 March 2012 22:02, Kukjin Kim <kgene.kim at samsung.com> wrote:
> On 02/22/12 04:14, Thomas Abraham wrote:
>>
>> Changes since v2:
>> - Reworked irq domain support based on v5 of the irq_domain generalization
>> ? patches.
>>
>> Changes since v1: (only patch 4/4 has changes)
>> - Fixes based on Rob's comments:
>> ? a. Fixed the function prototype of exynos4_init_irq_eint(void)
>> ? b. Included interrupt-parent as an optional property for wakeup
>> interrupt
>> ? ? ? controller node.
>>
>> Samsung Exynos4 includes 32 external wakeup interrupt sources. The first
>> 16
>> of these interrupts are connected to GIC SPI[31:16]. The last 16 of these
>> interrupts are grouped together into one interrupt and connected to GIC
>> SPI[32].
>>
>> This patchset adds irq domain and device tree support for these
>> interrupts.
>> Since there are users of fixed linux irq numbers of the external wakeup
>> interrupts, the legacy mapping is used for the irq domain.
>>
>> This patchset is based on
>> http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> [for-next]
>>
>> with all irq_domain (v5) patches merged from
>> http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]
>>
>> This patchset should be applied after applying the following patch.
>> [PATCH] ARM: Exynos: Add irq domain and device tree support for interrupt
>> combiner
>
>
> Looks ok to me this series, but I lost above patch in my mail box.
> Thomas, could you please send updated it so that I can apply this series?

The device tree support patches for wakeup interrupts and interrupt
combiner do not apply cleanly to the for-next branch due to the
Exynos5 additions.  So I will rebase, test and post an updated version
of these patches.

Thanks,
Thomas.


From u.kleine-koenig at pengutronix.de  Wed Mar 14 06:19:28 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 14 Mar 2012 11:19:28 +0100
Subject: [PATCH v3 0/5] ARM: Initial support for Cortex-M3
Message-ID: <20120314101928.GA29474@pengutronix.de>

Hello,

this is the result of reworking Catalin's exception handling patch to
stick to the current pt_regs layout. I extended it by two words to save
the exception return value. (The 2nd word is unused and only to maintain
stack alignment.)

Other than that only minor cleanups were done (some of them were
suggested by Catalin in reply to my v2 series).

These patches are available at

	git://git.pengutronix.de/git/ukl/linux.git cortexm3-for-rmk

basing on 3.3-rc7. There are some bits missing to allow a Cortex-M3 to
boot. They are contained in the branch efm32 in the same repository
together with support for the efm32 SoC if you're interested.
The most important parts missing (apart from SoC specific stuff) are
interrupt support and Makefile/Kconfig glue.

I'd be happy if these patches made it into 3.4-rc1. Any constructive
feedback welcome.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From u.kleine-koenig at pengutronix.de  Wed Mar 14 06:21:19 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Wed, 14 Mar 2012 11:21:19 +0100
Subject: [PATCH v3 1/5] ARM: protect usage of cr_alignment by #ifdef
 CONFIG_CPU_CP15
In-Reply-To: <20120314101928.GA29474@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
Message-ID: <1331720483-10075-1-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/include/asm/system.h |    2 ++
 arch/arm/kernel/entry-armv.S  |    4 ++++
 arch/arm/kernel/head-common.S |   10 ++++++++--
 arch/arm/kernel/setup.c       |    8 ++++++--
 arch/arm/mm/alignment.c       |    6 ++++++
 arch/arm/mm/mmu.c             |    8 +++++++-
 6 files changed, 33 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index e4c96cc..de46477 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -185,6 +185,7 @@ extern unsigned int user_debug;
 #define set_mb(var, value)	do { var = value; smp_mb(); } while (0)
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
+#ifdef CONFIG_CPU_CP15
 extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */
 extern unsigned long cr_alignment;	/* defined in entry-armv.S */
 
@@ -224,6 +225,7 @@ static inline void set_copro_access(unsigned int val)
 	  : : "r" (val) : "cc");
 	isb();
 }
+#endif
 
 /*
  * switch_mm() may do a full cache flush over the context switch,
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index be16a48..a6f2ef5 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -314,8 +314,10 @@ __pabt_svc:
 ENDPROC(__pabt_svc)
 
 	.align	5
+#ifdef CONFIG_CPU_CP15
 .LCcralign:
 	.word	cr_alignment
+#endif
 #ifdef MULTI_DABORT
 .LCprocfns:
 	.word	processor
@@ -1146,12 +1148,14 @@ __vectors_end:
 
 	.data
 
+#ifdef CONFIG_CPU_CP15
 	.globl	cr_alignment
 	.globl	cr_no_alignment
 cr_alignment:
 	.space	4
 cr_no_alignment:
 	.space	4
+#endif
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 	.globl	handle_arch_irq
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 854bd22..efeb2d0 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -98,8 +98,10 @@ __mmap_switched:
 	str	r9, [r4]			@ Save processor ID
 	str	r1, [r5]			@ Save machine type
 	str	r2, [r6]			@ Save atags pointer
-	bic	r4, r0, #CR_A			@ Clear 'A' bit
-	stmia	r7, {r0, r4}			@ Save control register values
+	cmp	r7, #0
+	itt	ne
+	bicne	r4, r0, #CR_A			@ Clear 'A' bit
+	stmneia	r7, {r0, r4}			@ Save control register values
 	b	start_kernel
 ENDPROC(__mmap_switched)
 
@@ -113,7 +115,11 @@ __mmap_switched_data:
 	.long	processor_id			@ r4
 	.long	__machine_arch_type		@ r5
 	.long	__atags_pointer			@ r6
+#ifdef CONFIG_CPU_CP15
 	.long	cr_alignment			@ r7
+#else
+	.long	0				@ r7
+#endif
 	.long	init_thread_union + THREAD_START_SP @ sp
 	.size	__mmap_switched_data, . - __mmap_switched_data
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index a255c39..50d3df8 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -472,9 +472,13 @@ static void __init setup_processor(void)
 	cpu_cache = *list->cache;
 #endif
 
-	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
+	printk("CPU: %s [%08x] revision %d (ARMv%s)",
 	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
-	       proc_arch[cpu_architecture()], cr_alignment);
+	       proc_arch[cpu_architecture()]);
+
+#ifdef CONFIG_CPU_CP15
+	printk(KERN_CONT ", cr=%08lx\n", cr_alignment);
+#endif
 
 	snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
 		 list->arch_name, ENDIANNESS);
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index caf14dc..119d178 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -89,7 +89,11 @@ core_param(alignment, ai_usermode, int, 0600);
 /* Return true if and only if the ARMv6 unaligned access model is in use. */
 static bool cpu_is_v6_unaligned(void)
 {
+#ifdef CONFIG_CPU_CP15
 	return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
+#else
+	return 0;
+#endif
 }
 
 static int safe_usermode(int new_usermode, bool warn)
@@ -961,12 +965,14 @@ static int __init alignment_init(void)
 		return -ENOMEM;
 #endif
 
+#ifdef CONFIG_CPU_CP15
 	if (cpu_is_v6_unaligned()) {
 		cr_alignment &= ~CR_A;
 		cr_no_alignment &= ~CR_A;
 		set_cr(cr_alignment);
 		ai_usermode = safe_usermode(ai_usermode, false);
 	}
+#endif
 
 	hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
 			"alignment exception");
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 94c5a0c..f6dbe1a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -109,8 +109,10 @@ static int __init early_cachepolicy(char *p)
 
 		if (memcmp(p, cache_policies[i].policy, len) == 0) {
 			cachepolicy = i;
+#ifdef CONFIG_CPU_CP15
 			cr_alignment &= ~cache_policies[i].cr_mask;
 			cr_no_alignment &= ~cache_policies[i].cr_mask;
+#endif
 			break;
 		}
 	}
@@ -128,7 +130,9 @@ static int __init early_cachepolicy(char *p)
 		cachepolicy = CPOLICY_WRITEBACK;
 	}
 	flush_cache_all();
+#ifdef CONFIG_CPU_CP15
 	set_cr(cr_alignment);
+#endif
 	return 0;
 }
 early_param("cachepolicy", early_cachepolicy);
@@ -163,6 +167,7 @@ static int __init early_ecc(char *p)
 early_param("ecc", early_ecc);
 #endif
 
+#ifdef CONFIG_CPU_CP15
 static int __init noalign_setup(char *__unused)
 {
 	cr_alignment &= ~CR_A;
@@ -171,8 +176,9 @@ static int __init noalign_setup(char *__unused)
 	return 1;
 }
 __setup("noalign", noalign_setup);
+#endif
 
-#ifndef CONFIG_SMP
+#if !defined(CONFIG_SMP) && defined(CONFIG_CPU_CP15)
 void adjust_cr(unsigned long mask, unsigned long set)
 {
 	unsigned long flags;
-- 
1.7.9.1



From pintu_agarwal at yahoo.com  Wed Mar 14 06:21:58 2012
From: pintu_agarwal at yahoo.com (PINTU KUMAR)
Date: Wed, 14 Mar 2012 03:21:58 -0700 (PDT)
Subject: [INFO] : Hibernation and Resume between 2 similar devices
In-Reply-To: <201203132136.56353.rjw@sisk.pl>
References: <28119509.96581331614425960.JavaMail.weblogic@epml27>
 <201203132136.56353.rjw@sisk.pl>
Message-ID: <1331720518.14716.YahooMailNeo@web162005.mail.bf1.yahoo.com>


>________________________________
>From: Rafael J. Wysocki <rjw at sisk.pl>
>To: pintu.k at samsung.com 
>Cc: linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org 
>Sent: Wednesday, 14 March 2012 2:06 AM
>Subject: Re: [INFO] : Hibernation and Resume between 2 similar devices
>
>On Tuesday, March 13, 2012, PINTU KUMAR wrote:
>> Dear All,
>> 
>> I am just curious to know if it is possible to "Hibernate in one device" and "Resume the hibernated image from another similar device".
>
>Not out of the box (you'd need to hack the kernel for that to work I think,
>at least on x86) and the devices would need to be _exactly_ identical.
>Moreover, if there is read-write mass storage in them, the filesystems on
>both would have to be exactly identical as well (including metadata and data
>layout etc.).
?
[Pintu]
I wanted to try this on arm based Linux mobile phone.
I have 2 exactly similar mobile phone.
Here exactly means: 
hardware is same, kernel version is same, platform is same, filesystem is same.
The only difference could be some user space application state.
Hmmm.....the metadata and data layout within file system....this is were the confusion is.
Suppose in "Device 1" during hibernation, I have a file say "file1.txt" opened whose inode number is say "123456".
This opened state of file1.txt will be captured in hibernation image.
Now assume that same "file1.txt" is also present (not opened) in "Device2" but whose inode number is say "567890".
Now if I reboot "Device 2" and try to resume from hibernated image of "Device 1", what would happen to "file1.txt" ??
And similarly other senarios.......
Will resume work, at least partially. Like discard whatever is not relevant to "Device 2" and continue to load others.


>
>> Suppose, I have 2 exactly similar device (Laptop or mobile phone) with me.
>> At one time I will be working on only one device at a time.
>> Suppose I started my work on "Device 1"? with few opened application and later I wanted to switch to "Device 2" which is exactly similar to Device 1.
>> I thought to hibernate (suspend to disk) the Device 1 and store the hibernated image as a swap file and later transfer to sd card.
>> Then take of the sd card from Device 1 and put it into Device 2.
>> Copy the swap file from sd card to Device 2 in some swap partition.
>> Then reboot the Device 2 to Resume from this swap file.
>> I will get back my Device 1 content in Device 2.
>> 
>> Hope this is possible ?
>
>It may be possible to make it kind of work, but I wouldn't recommend it to
>anyone.
?
[Pintu]
if this can be possible we can derive many use cases.
Till now we heard about hibernating and resuming from same device. And also people uses it rarely.
With the Tizen coming up (supporting multiple devices) we can think about it.
Also if "cloud" is integrated with kernel in _future_ we can save all our work from one device in cloud and restore our work from cloud in another device.
I think that make sense.


?
>
>Thanks,
>Rafael
>
>_______________________________________________
>linux-arm-kernel mailing list
>linux-arm-kernel at lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>
>


From u.kleine-koenig at pengutronix.de  Wed Mar 14 06:21:53 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Wed, 14 Mar 2012 11:21:53 +0100
Subject: [PATCH v3 2/5] ARM: Add a printk loglevel modifier
In-Reply-To: <20120314101928.GA29474@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
Message-ID: <1331720516-11801-1-git-send-email-u.kleine-koenig@pengutronix.de>

This is a needed followup for

	ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

otherwise no newline is printed for !CONFIG_CPU_CP15

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
Should this be folded into the

	ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15

patch? Or should it come before it?

 arch/arm/kernel/setup.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 50d3df8..23893b1 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -325,7 +325,7 @@ static void __init cacheid_init(void)
 		cacheid = CACHEID_VIVT;
 	}
 
-	printk("CPU: %s data cache, %s instruction cache\n",
+	printk(KERN_INFO "CPU: %s data cache, %s instruction cache\n",
 		cache_is_vivt() ? "VIVT" :
 		cache_is_vipt_aliasing() ? "VIPT aliasing" :
 		cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
-- 
1.7.9.1



From u.kleine-koenig at pengutronix.de  Wed Mar 14 06:21:54 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Wed, 14 Mar 2012 11:21:54 +0100
Subject: [PATCH v3 3/5] ARM: force branch instructions to use long distance
 encoding
In-Reply-To: <20120314101928.GA29474@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
Message-ID: <1331720516-11801-2-git-send-email-u.kleine-koenig@pengutronix.de>

This fixes a linker error when the kernel image gets bigger than approx.
1 MiB.

This is done analogous to the change to head.S in commit

	a75e524 (ARM: 6504/1: Thumb-2: Fix long-distance conditional branches in head.S for Thumb-2.)

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/kernel/head-nommu.S |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index d46f259..1aca35d 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -51,6 +51,7 @@ ENTRY(stext)
 #endif
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
+	it	eq
 	beq	__error_p				@ yes, error 'p'
 
 	adr	lr, BSYM(__after_proc_init)	@ return (PIC) address
-- 
1.7.9.1



From u.kleine-koenig at pengutronix.de  Wed Mar 14 06:21:56 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Wed, 14 Mar 2012 11:21:56 +0100
Subject: [PATCH v3 5/5] Cortex-M3: Add support for exception handling
In-Reply-To: <20120314101928.GA29474@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
Message-ID: <1331720516-11801-4-git-send-email-u.kleine-koenig@pengutronix.de>

This patch implements the exception handling for the ARMv7-M
architecture (pretty different from the A or R profiles).

It bases on work done earlier by Catalin for 2.6.33 but was nearly
completely rewritten to use a pt_regs layout compatible to the A
profile.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/kernel/entry-common.S |    4 +
 arch/arm/kernel/entry-header.S |  148 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/entry-v7m.S    |  134 ++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/process.c      |    8 ++
 arch/arm/kernel/ptrace.c       |    3 +
 arch/arm/kernel/signal.c       |   13 ++++
 arch/arm/kernel/sys_arm.c      |    1 +
 7 files changed, 311 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/kernel/entry-v7m.S

diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 9fd0ba9..cf54fd1 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -345,6 +345,9 @@ ENDPROC(ftrace_stub)
 
 	.align	5
 ENTRY(vector_swi)
+#ifdef CONFIG_CPU_V7M
+	v7m_exception_entry
+#else
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0 - r12
  ARM(	add	r8, sp, #S_PC		)
@@ -355,6 +358,7 @@ ENTRY(vector_swi)
 	str	lr, [sp, #S_PC]			@ Save calling PC
 	str	r8, [sp, #S_PSR]		@ Save CPSR
 	str	r0, [sp, #S_OLD_R0]		@ Save OLD_R0
+#endif
 	zero_fp
 
 	/*
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 9a8531e..33d9900 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -44,6 +44,145 @@
 #endif
 	.endm
 
+#ifdef CONFIG_CPU_V7M
+/*
+ * ARMv7-M exception entry/exit macros.
+ *
+ * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
+ * automatically saved on the current stack (32 words) before
+ * switching to the exception stack (SP_main).
+ *
+ * If exception is taken while in user mode, SP_main is
+ * empty. Otherwise, SP_main is aligned to 64 bit automatically
+ * (CCR.STKALIGN set).
+ *
+ * Linux assumes that the interrupts are disabled when entering an
+ * exception handler and it may BUG if this is not the case. Interrupts
+ * are disabled during entry and reenabled in the exit macro.
+ *
+ * v7m_exception_fast_exit is used when returning from interrupts.
+ *
+ * v7m_exception_slow_exit is used when returning from SVC or PendSV.
+ * When returning to kernel mode, we don't return from exception.
+ */
+	.macro	v7m_exception_entry
+	@ determine the location of the registers saved by the core during
+	@ exception entry. Depending on the mode the cpu was in when the
+	@ exception happend that is either on the main or the process stack.
+	@ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
+	@ was used.
+	tst	lr, #0x4
+	mrsne	r12, psp
+	moveq	r12, sp
+
+	@ we cannot rely on r0-r3 and r12 matching the value saved in the
+	@ exception frame because of tail-chaining. So these have to be
+	@ reloaded.
+	ldmia	r12!, {r0-r3}
+
+	@ Linux expects to have irqs off. Do it here before taking stack space
+	cpsid	i
+
+	sub	sp, #S_FRAME_SIZE-S_IP
+	stmdb	sp!, {r0-r11}
+
+	@ load saved r12, lr, return address and xPSR.
+	@ r0-r7 are used for signals and never touched from now on. Clobbering
+	@ r8-r12 is OK.
+	mov	r9, r12
+	ldmia	r9!, {r8, r10-r12}
+
+	@ calculate the original stack pointer value.
+	@ r9 currently points to the memory location just above the auto saved
+	@ xPSR. If the FP extension is implemented and bit 4 of EXC_RETURN is 0
+	@ then space was allocated for FP state. That is space for 18 32-bit
+	@ values. (If FP extension is unimplemented, bit 4 is 1.)
+	@ Additionally the cpu might automatically 8-byte align the stack. Bit 9
+	@ of the saved xPSR specifies if stack aligning took place. In this case
+	@ another 32-bit value is included in the stack.
+
+	tst	lr, #0x10
+	addeq	r9, r9, #576
+
+	tst	r12, 0x100
+	addne	r9, r9, #4
+
+	@ store saved r12 using str to have a register to hold the base for stm
+	str	r8, [sp, #S_IP]
+	add	r8, sp, #S_SP
+	@ store r13-r15, xPSR
+	stmia	r8!, {r9-r12}
+	@ store r0 once more and EXC_RETURN
+	stmia	r8, {r0, lr}
+	.endm
+
+	.macro	v7m_exception_fast_exit
+	@ registers r0-r3 and r12 are automatically restored on exception
+	@ return. r4-r7 were not clobbered in v7m_exception_entry so for
+	@ correctness they don't need to be restored. So only r8-r11 must be
+	@ restored here. The easiest way to do so is to restore r0-r7, too.
+	ldmia	sp!, {r0-r11}
+	add	sp, #S_FRAME_SIZE-S_IP
+	cpsie	i
+	bx	lr
+	.endm
+
+	.macro	v7m_exception_slow_exit ret_r0
+	cpsid	i
+	ldr	lr, [sp, #S_EXC_RET]	@ read exception LR
+	tst     lr, #0x8
+	bne	1f			@ go to thread mode using exception return
+
+	/*
+	 * return to kernel thread
+	 * sp is already set up (and might be unset in pt_regs), so only
+	 * restore r0-r12 and pc
+	 */
+	ldmia	sp, {r0-r12}
+	ldr	lr, [sp, #S_PC]
+	add	sp, sp, #S_FRAME_SIZE
+	cpsie	i
+	bx	lr
+
+1:	/*
+	 * return to userspace
+	 */
+
+	@ read original r12, sp, lr, pc and xPSR
+	add	r12, sp, #S_IP
+	ldmia	r12, {r1-r5}
+
+	@ handle stack aligning
+	tst	r5, #0x100
+	subne	r2, r2, #4
+
+	@ skip over stack space for fp saving
+	tst	lr, #0x10
+	subeq	r2, r2, #576
+
+	@ write basic exception frame
+	stmdb	r2!, {r1, r3-r5}
+	ldmia	sp, {r1, r3-r5}
+	.if	\ret_r0
+	stmdb	r2!, {r0, r3-r5}
+	.else
+	stmdb	r2!, {r1, r3-r5}
+	.endif
+
+	@ restore process sp
+	msr	psp, r2
+
+	@ restore original r4-r11
+	ldmia	sp!, {r0-r11}
+
+	@ restore main sp
+	add	sp, sp, #S_FRAME_SIZE-S_IP
+
+	cpsie	i
+	bx	lr
+	.endm
+#endif	/* CONFIG_CPU_V7M */
+
 	@
 	@ Store/load the USER SP and LR registers by switching to the SYS
 	@ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
@@ -131,6 +270,14 @@
 	rfeia	sp!
 	.endm
 
+#ifdef CONFIG_CPU_V7M
+	.macro	restore_user_regs, fast = 0, offset = 0
+	.if	\offset
+	add	sp, #\offset
+	.endif
+	v7m_exception_slow_exit ret_r0 = \fast
+	.endm
+#else	/* !CONFIG_CPU_V7M */
 	.macro	restore_user_regs, fast = 0, offset = 0
 	clrex					@ clear the exclusive monitor
 	mov	r2, sp
@@ -147,6 +294,7 @@
 	add	sp, sp, #S_FRAME_SIZE - S_SP
 	movs	pc, lr				@ return & move spsr_svc into cpsr
 	.endm
+#endif	/* CONFIG_CPU_V7M */
 
 	.macro	get_thread_info, rd
 	mov	\rd, sp
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
new file mode 100644
index 0000000..a0991dc
--- /dev/null
+++ b/arch/arm/kernel/entry-v7m.S
@@ -0,0 +1,134 @@
+/*
+ * linux/arch/arm/kernel/entry-v7m.S
+ *
+ * Copyright (C) 2008 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Low-level vector interface routines for the ARMv7-M architecture
+ */
+#include <asm/memory.h>
+#include <asm/glue.h>
+#include <asm/thread_notify.h>
+
+#include <mach/entry-macro.S>
+
+#include "entry-header.S"
+
+#ifdef CONFIG_PREEMPT
+#error "CONFIG_PREEMPT not supported on the current ARMv7M implementation"
+#endif
+#ifdef CONFIG_TRACE_IRQFLAGS
+#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
+#endif
+
+__invalid_entry:
+	v7m_exception_entry
+	adr	r0, strerr
+	mrs	r1, ipsr
+	mov	r2, lr
+	bl	printk
+	mov	r0, sp
+	bl	show_regs
+1:	b	1b
+ENDPROC(__invalid_entry)
+
+strerr:	.asciz	"\nUnhandled exception: IPSR = %08lx LR = %08lx\n"
+
+	.align	2
+__irq_entry:
+	v7m_exception_entry
+
+	@
+	@ Invoke the IRQ handler
+	@
+	mrs	r0, ipsr
+	and	r0, #0xff
+	sub	r0, #16			@ IRQ number
+	mov	r1, sp
+	@ routine called with r0 = irq number, r1 = struct pt_regs *
+	bl	asm_do_IRQ
+
+	@
+	@ Check for any pending work if returning to user
+	@
+	ldr	lr, [sp, #S_EXC_RET]
+	tst	lr, #0x8		@ check the return stack
+	beq	2f			@ returning to handler mode
+	get_thread_info tsk
+	ldr	r1, [tsk, #TI_FLAGS]
+	tst	r1, #_TIF_WORK_MASK
+	beq	2f			@ no work pending
+	ldr	r1, =0xe000ed04		@ ICSR
+	mov	r0, #1 << 28		@ ICSR.PENDSVSET
+	str	r0, [r1]		@ raise PendSV
+
+2:
+	v7m_exception_fast_exit
+ENDPROC(__irq_entry)
+
+__pendsv_entry:
+	v7m_exception_entry
+
+	ldr	r1, =0xe000ed04		@ ICSR
+	mov	r0, #1 << 27		@ ICSR.PENDSVCLR
+	str	r0, [r1]		@ clear PendSV
+
+	@ execute the pending work, including reschedule
+	get_thread_info tsk
+	mov	why, #0
+	b	ret_to_user
+ENDPROC(__pendsv_entry)
+
+/*
+ * Register switch for ARMv7-M processors.
+ * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
+ * previous and next are guaranteed not to be the same.
+ */
+ENTRY(__switch_to)
+	.fnstart
+	.cantunwind
+	add	ip, r1, #TI_CPU_SAVE
+	stmia	ip!, {r4 - r11}		@ Store most regs on stack
+	str	sp, [ip], #4
+	str	lr, [ip], #4
+	mov	r5, r0
+	add	r4, r2, #TI_CPU_SAVE
+	ldr	r0, =thread_notify_head
+	mov	r1, #THREAD_NOTIFY_SWITCH
+	bl	atomic_notifier_call_chain
+	mov	ip, r4
+	mov	r0, r5
+	ldmia	ip!, {r4 - r11}		@ Load all regs saved previously
+	ldr	sp, [ip], #4
+	ldr	pc, [ip]
+	.fnend
+ENDPROC(__switch_to)
+
+	.data
+	.align	8
+/*
+ * Vector table (64 words => 256 bytes natural alignment)
+ */
+ENTRY(vector_table)
+	.long	0			@ 0 - Reset stack pointer
+	.long	__invalid_entry		@ 1 - Reset
+	.long	__invalid_entry		@ 2 - NMI
+	.long	__invalid_entry		@ 3 - HardFault
+	.long	__invalid_entry		@ 4 - MemManage
+	.long	__invalid_entry		@ 5 - BusFault
+	.long	__invalid_entry		@ 6 - UsageFault
+	.long	__invalid_entry		@ 7 - Reserved
+	.long	__invalid_entry		@ 8 - Reserved
+	.long	__invalid_entry		@ 9 - Reserved
+	.long	__invalid_entry		@ 10 - Reserved
+	.long	vector_swi		@ 11 - SVCall
+	.long	__invalid_entry		@ 12 - Debug Monitor
+	.long	__invalid_entry		@ 13 - Reserved
+	.long	__pendsv_entry		@ 14 - PendSV
+	.long	__invalid_entry		@ 15 - SysTick
+	.rept	64 - 16
+	.long	__irq_entry		@ 16..64 - External Interrupts
+	.endr
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 971d65c..38d9fde 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -452,7 +452,11 @@ asm(	".pushsection .text\n"
 #ifdef CONFIG_TRACE_IRQFLAGS
 "	bl	trace_hardirqs_on\n"
 #endif
+#ifdef CONFIG_CPU_V7M
+"	msr	primask, r7\n"
+#else
 "	msr	cpsr_c, r7\n"
+#endif
 "	mov	r0, r4\n"
 "	mov	lr, r6\n"
 "	mov	pc, r5\n"
@@ -491,6 +495,10 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
 	regs.ARM_r7 = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;
 	regs.ARM_pc = (unsigned long)kernel_thread_helper;
 	regs.ARM_cpsr = regs.ARM_r7 | PSR_I_BIT;
+#if defined CONFIG_CPU_V7M
+	/* Return to Handler mode */
+	regs.ARM_EXC_RET = 0xfffffff1L;
+#endif
 
 	return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 }
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index ede6443..97611fd 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -83,6 +83,9 @@ static const struct pt_regs_offset regoffset_table[] = {
 	REG_OFFSET_NAME(pc),
 	REG_OFFSET_NAME(cpsr),
 	REG_OFFSET_NAME(ORIG_r0),
+#ifdef CONFIG_CPU_V7M
+	REG_OFFSET_NAME(EXC_RET),
+#endif
 	REG_OFFSET_END,
 };
 
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 9e617bd..38a6585 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -277,6 +277,8 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf)
 	sigset_t set;
 	int err;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
+
 	err = __copy_from_user(&set, &sf->uc.uc_sigmask, sizeof(set));
 	if (err == 0) {
 		sigdelsetmask(&set, ~_BLOCKABLE);
@@ -327,6 +329,7 @@ asmlinkage int sys_sigreturn(struct pt_regs *regs)
 {
 	struct sigframe __user *frame;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
 	/* Always make any pending restarted system calls return -EINTR */
 	current_thread_info()->restart_block.fn = do_no_restart_syscall;
 
@@ -357,6 +360,7 @@ asmlinkage int sys_rt_sigreturn(struct pt_regs *regs)
 {
 	struct rt_sigframe __user *frame;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
 	/* Always make any pending restarted system calls return -EINTR */
 	current_thread_info()->restart_block.fn = do_no_restart_syscall;
 
@@ -441,6 +445,7 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, int framesize)
 	unsigned long sp = regs->ARM_sp;
 	void __user *frame;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
 	/*
 	 * This is the X/Open sanctioned signal stack switching.
 	 */
@@ -470,6 +475,8 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
 	int thumb = 0;
 	unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT);
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
+
 	cpsr |= PSR_ENDSTATE;
 
 	/*
@@ -542,6 +549,8 @@ setup_frame(int usig, struct k_sigaction *ka, sigset_t *set, struct pt_regs *reg
 	struct sigframe __user *frame = get_sigframe(ka, regs, sizeof(*frame));
 	int err = 0;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
+
 	if (!frame)
 		return 1;
 
@@ -565,6 +574,8 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
 	stack_t stack;
 	int err = 0;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
+
 	if (!frame)
 		return 1;
 
@@ -609,6 +620,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
 	int usig = sig;
 	int ret;
 
+	pr_info("%s(regs=%p)\n", __func__, regs);
 	/*
 	 * translate the signal
 	 */
@@ -784,6 +796,7 @@ static void do_signal(struct pt_regs *regs, int syscall)
 asmlinkage void
 do_notify_resume(struct pt_regs *regs, unsigned int thread_flags, int syscall)
 {
+	pr_info("%s(regs=%p)\n", __func__, regs);
 	if (thread_flags & _TIF_SIGPENDING)
 		do_signal(regs, syscall);
 
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index d2b1779..4d3caca4d 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -102,6 +102,7 @@ int kernel_execve(const char *filename,
 	 * We were successful.  We won't be returning to our caller, but
 	 * instead to user space by manipulating the kernel stack.
 	 */
+	pr_info("we were successful\n");
 	asm(	"add	r0, %0, %1\n\t"
 		"mov	r1, %2\n\t"
 		"mov	r2, %3\n\t"
-- 
1.7.9.1



From u.kleine-koenig at pengutronix.de  Wed Mar 14 06:21:55 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Wed, 14 Mar 2012 11:21:55 +0100
Subject: [PATCH v3 4/5] Cortex-M3: Add base support for Cortex-M3
In-Reply-To: <20120314101928.GA29474@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
Message-ID: <1331720516-11801-3-git-send-email-u.kleine-koenig@pengutronix.de>

From: Catalin Marinas <catalin.marinas at arm.com>

This patch adds the base support for the Cortex-M3 processor (ARMv7-M
architecture). It consists of the corresponding arch/arm/mm/ files and
various #ifdef's around the kernel. Exception handling is implemented by
a subsequent patch.

[ukleinek: squash in some changes originating from commit

b5717ba (Cortex-M3: Add support for the Microcontroller Prototyping System)

from the v2.6.33-arm1 patch stack, port to post 3.2, drop zImage
support, drop reorganisation of pt_regs, and a few cosmetic changes]

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/include/asm/assembler.h  |   13 +++-
 arch/arm/include/asm/cputype.h    |    3 +
 arch/arm/include/asm/glue-cache.h |   24 ++++++
 arch/arm/include/asm/glue-df.h    |    8 ++
 arch/arm/include/asm/glue-proc.h  |    9 ++
 arch/arm/include/asm/irqflags.h   |   51 +++++++++++-
 arch/arm/include/asm/processor.h  |    7 ++
 arch/arm/include/asm/ptrace.h     |   20 +++++-
 arch/arm/include/asm/system.h     |    3 +
 arch/arm/kernel/asm-offsets.c     |    3 +
 arch/arm/kernel/head-nommu.S      |    9 ++-
 arch/arm/kernel/setup.c           |   13 +++-
 arch/arm/kernel/traps.c           |    2 +
 arch/arm/mm/nommu.c               |    2 +
 arch/arm/mm/proc-v7m.S            |  161 +++++++++++++++++++++++++++++++++++++
 15 files changed, 320 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/mm/proc-v7m.S

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 23371b1..51f3ff7 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -133,7 +133,11 @@
  * assumes FIQs are enabled, and that the processor is in SVC mode.
  */
 	.macro	save_and_disable_irqs, oldcpsr
+#ifdef CONFIG_CPU_V7M
+	mrs	\oldcpsr, primask
+#else
 	mrs	\oldcpsr, cpsr
+#endif
 	disable_irq
 	.endm
 
@@ -147,7 +151,11 @@
  * guarantee that this will preserve the flags.
  */
 	.macro	restore_irqs_notrace, oldcpsr
+#ifdef CONFIG_CPU_V7M
+	msr	primask, \oldcpsr
+#else
 	msr	cpsr_c, \oldcpsr
+#endif
 	.endm
 
 	.macro restore_irqs, oldcpsr
@@ -226,7 +234,10 @@
 #endif
 	.endm
 
-#ifdef CONFIG_THUMB2_KERNEL
+#if defined(CONFIG_CPU_V7M)
+	.macro	setmode, mode, reg
+	.endm
+#elif defined(CONFIG_THUMB2_KERNEL)
 	.macro	setmode, mode, reg
 	mov	\reg, #\mode
 	msr	cpsr_c, \reg
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index cb47d28..5bd8cb6 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -46,6 +46,9 @@ extern unsigned int processor_id;
 		    : "cc");						\
 		__val;							\
 	})
+#elif defined(CONFIG_CPU_V7M)
+#define read_cpuid(reg) (*(unsigned int *)0xe000ed00)
+#define read_cpuid_ext(reg) 0
 #else
 #define read_cpuid(reg) (processor_id)
 #define read_cpuid_ext(reg) 0
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index 7e30874..6a5fd0b 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -125,10 +125,34 @@
 //# endif
 #endif
 
+#if defined(CONFIG_CPU_V7M)
+# ifdef _CACHE
+#  error "Multi-cache not supported on ARMv7-M"
+# else
+#  define _CACHE nop
+# endif
+#endif
+
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 #error Unknown cache maintenance model
 #endif
 
+#ifndef __ASSEMBLER__
+static inline void nop_flush_icache_all(void) { }
+static inline void nop_flush_kern_cache_all(void) { }
+static inline void nop_flush_user_cache_all(void) { }
+static inline void nop_flush_user_cache_range(unsigned long a, unsigned long b, unsigned int c) { }
+
+static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
+static inline void nop_coherent_user_range(unsigned long a, unsigned long b) { }
+static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
+
+static inline void nop_dma_flush_range(const void *a, const void *b) { }
+
+static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
+static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
+#endif
+
 #ifndef MULTI_CACHE
 #define __cpuc_flush_icache_all		__glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index 354d571..26be71c 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -103,6 +103,14 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_ABRT_NOMMU
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
+# else
+#  define CPU_DABORT_HANDLER nommu_early_abort
+# endif
+#endif
+
 #ifndef CPU_DABORT_HANDLER
 #error Unknown data abort handler type
 #endif
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index e2be7f1..8f9991b 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -248,6 +248,15 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_V7M
+# ifdef CPU_NAME
+#  undef  MULTI_CPU
+#  define MULTI_CPU
+# else
+#  define CPU_NAME cpu_v7m
+# endif
+#endif
+
 #ifndef MULTI_CPU
 #define cpu_proc_init			__glue(CPU_NAME,_proc_init)
 #define cpu_proc_fin			__glue(CPU_NAME,_proc_fin)
diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h
index 1e6cca5..ac4d548 100644
--- a/arch/arm/include/asm/irqflags.h
+++ b/arch/arm/include/asm/irqflags.h
@@ -10,6 +10,18 @@
  */
 #if __LINUX_ARM_ARCH__ >= 6
 
+#ifdef CONFIG_CPU_V7M
+static inline unsigned long arch_local_irq_save(void)
+{
+	unsigned long flags;
+
+	asm volatile(
+		"	mrs	%0, primask	@ arch_local_irq_save\n"
+		"	cpsid	i"
+		: "=r" (flags) : : "memory", "cc");
+	return flags;
+}
+#else
 static inline unsigned long arch_local_irq_save(void)
 {
 	unsigned long flags;
@@ -20,6 +32,7 @@ static inline unsigned long arch_local_irq_save(void)
 		: "=r" (flags) : : "memory", "cc");
 	return flags;
 }
+#endif
 
 static inline void arch_local_irq_enable(void)
 {
@@ -122,6 +135,38 @@ static inline void arch_local_irq_disable(void)
 
 #endif
 
+#ifdef CONFIG_CPU_V7M
+/*
+ * Save the current interrupt enable state.
+ */
+static inline unsigned long arch_local_save_flags(void)
+{
+	unsigned long flags;
+	asm volatile(
+		"	mrs	%0, primask	@ local_save_flags"
+		: "=r" (flags) : : "memory", "cc");
+	return flags;
+}
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+	asm volatile(
+		"	msr	primask, %0	@ local_irq_restore"
+		:
+		: "r" (flags)
+		: "memory", "cc");
+}
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+	return flags & 1;
+}
+
+#else /* ifdef CONFIG_CPU_V7M */
+
 /*
  * Save the current interrupt enable state.
  */
@@ -151,5 +196,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags)
 	return flags & PSR_I_BIT;
 }
 
-#endif
-#endif
+#endif /* ifdef CONFIG_CPU_V7M / else */
+
+#endif /* ifdef __KERNEL__ */
+#endif /* ifndef __ASM_ARM_IRQFLAGS_H */
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index cb8d638..2c22bcc 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -50,7 +50,14 @@ struct thread_struct {
 #ifdef CONFIG_MMU
 #define nommu_start_thread(regs) do { } while (0)
 #else
+#ifndef CONFIG_CPU_V7M
 #define nommu_start_thread(regs) regs->ARM_r10 = current->mm->start_data
+#else
+#define nommu_start_thread(regs) do {					\
+	regs->ARM_r10 = current->mm->start_data;			\
+	regs->ARM_EXC_RET = 0xfffffffdL;				\
+} while (0)
+#endif
 #endif
 
 #define start_thread(regs,pc,sp)					\
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 451808b..696bbf4 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -39,16 +39,25 @@
 #define FIQ26_MODE	0x00000001
 #define IRQ26_MODE	0x00000002
 #define SVC26_MODE	0x00000003
+#ifndef CONFIG_CPU_V7M
 #define USR_MODE	0x00000010
+#define SVC_MODE	0x00000013
+#else
+#define USR_MODE	0x00000000
+#define SVC_MODE	0x00000000
+#endif
 #define FIQ_MODE	0x00000011
 #define IRQ_MODE	0x00000012
-#define SVC_MODE	0x00000013
 #define ABT_MODE	0x00000017
 #define UND_MODE	0x0000001b
 #define SYSTEM_MODE	0x0000001f
 #define MODE32_BIT	0x00000010
 #define MODE_MASK	0x0000001f
+#ifndef CONFIG_CPU_V7M
 #define PSR_T_BIT	0x00000020
+#else
+#define PSR_T_BIT	0x01000000
+#endif
 #define PSR_F_BIT	0x00000040
 #define PSR_I_BIT	0x00000080
 #define PSR_A_BIT	0x00000100
@@ -106,7 +115,11 @@ struct pt_regs {
 };
 #else /* __KERNEL__ */
 struct pt_regs {
+#ifdef CONFIG_CPU_V7M
+	unsigned long uregs[20];
+#else
 	unsigned long uregs[18];
+#endif
 };
 #endif /* __KERNEL__ */
 
@@ -128,6 +141,7 @@ struct pt_regs {
 #define ARM_r1		uregs[1]
 #define ARM_r0		uregs[0]
 #define ARM_ORIG_r0	uregs[17]
+#define ARM_EXC_RET	uregs[18]
 
 /*
  * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
@@ -165,6 +179,7 @@ struct pt_regs {
  */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
+#ifndef CONFIG_CPU_V7M
 	unsigned long mode = regs->ARM_cpsr & MODE_MASK;
 
 	/*
@@ -187,6 +202,9 @@ static inline int valid_user_regs(struct pt_regs *regs)
 		regs->ARM_cpsr |= USR_MODE;
 
 	return 0;
+#else /* ifndef CONFIG_CPU_V7M */
+	return 1;
+#endif
 }
 
 static inline long regs_return_value(struct pt_regs *regs)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index de46477..16117ed 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -13,6 +13,7 @@
 #define CPU_ARCH_ARMv5TEJ	7
 #define CPU_ARCH_ARMv6		8
 #define CPU_ARCH_ARMv7		9
+#define CPU_ARCH_ARMv7M		10
 
 /*
  * CR1 bits (CP#15 CR1)
@@ -232,7 +233,9 @@ static inline void set_copro_access(unsigned int val)
  * so enable interrupts over the context switch to avoid high
  * latency.
  */
+#ifndef CONFIG_CPU_V7M
 #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
+#endif
 
 /*
  * switch_to(prev, next) should switch from task `prev' to `next'
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 1429d89..6f6b5b6 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -91,6 +91,9 @@ int main(void)
   DEFINE(S_PC,			offsetof(struct pt_regs, ARM_pc));
   DEFINE(S_PSR,			offsetof(struct pt_regs, ARM_cpsr));
   DEFINE(S_OLD_R0,		offsetof(struct pt_regs, ARM_ORIG_r0));
+#ifdef CONFIG_CPU_V7M
+  DEFINE(S_EXC_RET,		offsetof(struct pt_regs, ARM_EXC_RET));
+#endif
   DEFINE(S_FRAME_SIZE,		sizeof(struct pt_regs));
   BLANK();
 #ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 1aca35d..61ba029 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -44,10 +44,13 @@ ENTRY(stext)
 
 	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
 						@ and irqs disabled
-#ifndef CONFIG_CPU_CP15
-	ldr	r9, =CONFIG_PROCESSOR_ID
-#else
+#if defined(CONFIG_CPU_CP15)
 	mrc	p15, 0, r9, c0, c0		@ get processor id
+#elif defined(CONFIG_CPU_V7M)
+	ldr	r9, =0xe000ed00			@ CPUID register address
+	ldr	r9, [r9]
+#else
+	ldr	r9, =CONFIG_PROCESSOR_ID
 #endif
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 23893b1..d0fc5b8 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -132,7 +132,9 @@ struct stack {
 	u32 und[3];
 } ____cacheline_aligned;
 
+#ifndef CONFIG_CPU_V7M
 static struct stack stacks[NR_CPUS];
+#endif
 
 char elf_platform[ELF_PLATFORM_SIZE];
 EXPORT_SYMBOL(elf_platform);
@@ -212,7 +214,7 @@ static const char *proc_arch[] = {
 	"5TEJ",
 	"6TEJ",
 	"7",
-	"?(11)",
+	"7M",
 	"?(12)",
 	"?(13)",
 	"?(14)",
@@ -221,6 +223,12 @@ static const char *proc_arch[] = {
 	"?(17)",
 };
 
+#ifdef CONFIG_CPU_V7M
+static int __get_cpu_architecture(void)
+{
+	return CPU_ARCH_ARMv7M;
+}
+#else
 static int __get_cpu_architecture(void)
 {
 	int cpu_arch;
@@ -253,6 +261,7 @@ static int __get_cpu_architecture(void)
 
 	return cpu_arch;
 }
+#endif
 
 int __pure cpu_architecture(void)
 {
@@ -380,6 +389,7 @@ static void __init feat_v6_fixup(void)
  */
 void cpu_init(void)
 {
+#ifndef CONFIG_CPU_V7M
 	unsigned int cpu = smp_processor_id();
 	struct stack *stk = &stacks[cpu];
 
@@ -424,6 +434,7 @@ void cpu_init(void)
 	      "I" (offsetof(struct stack, und[0])),
 	      PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
 	    : "r14");
+#endif
 }
 
 int __cpu_logical_map[NR_CPUS];
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index f84dfe6..ce7a624 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -786,6 +786,7 @@ static void __init kuser_get_tls_init(unsigned long vectors)
 
 void __init early_trap_init(void)
 {
+#ifndef CONFIG_CPU_V7M
 #if defined(CONFIG_CPU_USE_DOMAINS)
 	unsigned long vectors = CONFIG_VECTORS_BASE;
 #else
@@ -821,4 +822,5 @@ void __init early_trap_init(void)
 
 	flush_icache_range(vectors, vectors + PAGE_SIZE);
 	modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
+#endif
 }
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 4fc6794..fdd49ac 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -19,12 +19,14 @@
 
 void __init arm_mm_memblock_reserve(void)
 {
+#ifndef CONFIG_CPU_V7M
 	/*
 	 * Register the exception vector page.
 	 * some architectures which the DRAM is the exception vector to trap,
 	 * alloc_page breaks with error, although it is not NULL, but "0."
 	 */
 	memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
+#endif
 }
 
 void __init sanity_check_meminfo(void)
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
new file mode 100644
index 0000000..2b8eb97
--- /dev/null
+++ b/arch/arm/mm/proc-v7m.S
@@ -0,0 +1,161 @@
+/*
+ *  linux/arch/arm/mm/proc-v7m.S
+ *
+ *  Copyright (C) 2008 ARM Ltd.
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7-M processor support.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(cpu_v7m_proc_init)
+	mov	pc, lr
+ENDPROC(cpu_v7m_proc_init)
+
+ENTRY(cpu_v7m_proc_fin)
+	mov	pc, lr
+ENDPROC(cpu_v7m_proc_fin)
+
+/*
+ *	cpu_v7m_reset(loc)
+ *
+ *	Perform a soft reset of the system.  Put the CPU into the
+ *	same state as it would be if it had been reset, and branch
+ *	to what would be the reset vector.
+ *
+ *	- loc   - location to jump to for soft reset
+ */
+	.align	5
+ENTRY(cpu_v7m_reset)
+	mov	pc, r0
+ENDPROC(cpu_v7m_reset)
+
+/*
+ *	cpu_v7m_do_idle()
+ *
+ *	Idle the processor (eg, wait for interrupt).
+ *
+ *	IRQs are already disabled.
+ */
+ENTRY(cpu_v7m_do_idle)
+	wfi
+	mov	pc, lr
+ENDPROC(cpu_v7m_do_idle)
+
+ENTRY(cpu_v7m_dcache_clean_area)
+	mov	pc, lr
+ENDPROC(cpu_v7m_dcache_clean_area)
+
+/*
+ * There is no MMU, so here is nothing to do.
+ */
+ENTRY(cpu_v7m_switch_mm)
+	mov	pc, lr
+ENDPROC(cpu_v7m_switch_mm)
+
+cpu_v7m_name:
+	.ascii	"ARMv7-M Processor"
+	.align
+
+	.section ".text.init", #alloc, #execinstr
+
+/*
+ *	__v7m_setup
+ *
+ *	This should be able to cover all ARMv7-M cores.
+ */
+__v7m_setup:
+	@ Configure the vector table base address
+	ldr	r0, =0xe000ed08		@ vector table base address
+	ldr	r12, =vector_table
+	str	r12, [r0]
+
+	@ Lower the priority of the SVC and PendSV exceptions
+	ldr	r0, =0xe000ed1c
+	mov	r5, #0x80000000
+	str	r5, [r0]		@ set SVC priority
+	ldr	r0, =0xe000ed20
+	mov	r5, #0x00800000
+	str	r5, [r0]		@ set PendSV priority
+
+	@ SVC to run the kernel in this mode
+	adr	r0, BSYM(1f)
+	ldr	r5, [r12, #11 * 4]	@ read the SVC vector entry
+	str	r0, [r12, #11 * 4]	@ write the temporary SVC vector entry
+	mov	r6, lr			@ save LR
+	mov	r7, sp			@ save SP
+	ldr	sp, =__v7m_setup_stack_top
+	cpsie	i
+	svc	#0
+1:	cpsid	i
+	str	r5, [r12, #11 * 4]	@ restore the original SVC vector entry
+	mov	lr, r6			@ restore LR
+	mov	sp, r7			@ restore SP
+
+	@ Special-purpose control register
+	mov	r0, #1
+	msr	control, r0		@ Thread mode has unpriviledged access
+
+	@ Configure the System Control Register
+	ldr	r0, =0xe000ed14		@ system control register
+	ldr	r12, [r0]
+	orr	r12, #1 << 9		@ STKALIGN
+	str	r12, [r0]
+	mov	pc, lr
+ENDPROC(__v7m_setup)
+
+	.align	2
+	.type	v7m_processor_functions, #object
+ENTRY(v7m_processor_functions)
+	.word	nommu_early_abort
+	.word	cpu_v7m_proc_init
+	.word	cpu_v7m_proc_fin
+	.word	cpu_v7m_reset
+	.word	cpu_v7m_do_idle
+	.word	cpu_v7m_dcache_clean_area
+	.word	cpu_v7m_switch_mm
+	.word	0			@ cpu_v7m_set_pte_ext
+	.word	legacy_pabort
+	.size	v7m_processor_functions, . - v7m_processor_functions
+
+	.type	cpu_arch_name, #object
+cpu_arch_name:
+	.asciz	"armv7m"
+	.size	cpu_arch_name, . - cpu_arch_name
+
+	.type	cpu_elf_name, #object
+cpu_elf_name:
+	.asciz	"v7m"
+	.size	cpu_elf_name, . - cpu_elf_name
+	.align
+
+	.section ".proc.info.init", #alloc, #execinstr
+
+	/*
+	 * Match any ARMv7-M processor core.
+	 */
+	.type	__v7m_proc_info, #object
+__v7m_proc_info:
+	.long	0x000f0000		@ Required ID value
+	.long	0x000f0000		@ Mask for ID
+	.long   0			@ proc_info_list.__cpu_mm_mmu_flags
+	.long   0			@ proc_info_list.__cpu_io_mmu_flags
+	b	__v7m_setup		@ proc_info_list.__cpu_flush
+	.long	cpu_arch_name
+	.long	cpu_elf_name
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+	.long	cpu_v7m_name
+	.long	v7m_processor_functions	@ proc_info_list.proc
+	.long	0			@ proc_info_list.tlb
+	.long	0			@ proc_info_list.user
+	.long	0			@ proc_info_list.cache
+	.size	__v7m_proc_info, . - __v7m_proc_info
+
+__v7m_setup_stack:
+	.space	4 * 8				@ 8 registers
+__v7m_setup_stack_top:
-- 
1.7.9.1



From haojian.zhuang at gmail.com  Wed Mar 14 06:30:24 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 18:30:24 +0800
Subject: [GIT PULL][for v3.4] pull request from board-specific branch in
 arch-pxa
Message-ID: <CAN1soZyWmrzQzr0VHtrixdr2myv4ggJ1YBcS8OnuLJLOn2uVEQ@mail.gmail.com>

Hi Arnd & Olof,

First, please help to _revert_ one commit 43de6a7dda6e9a7345e2 on
arnd/pxa/board branch of arm-soc.git first. Since this commit is
duplicated, and it's already merged into v3.3-rc7. I'm sorry on
inconvenience.

commit 43de6a7dda6e9a7345e218e688f2092f991126f0
Author: Haojian Zhuang <haojian.zhuang at marvell.com>
Date:   Tue Feb 28 10:57:48 2012 +0800

    ARM: pxa: add dummy clock for pxa25x and pxa27x


Second, please help to pull these commits from arch-pxa git tree.

The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:

  Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)

are available in the git repository at:
  git://github.com/hzhuang1/linux.git board-specific

Paul Parsons (3):
      ARM: pxa/hx4700: Remove unwanted request for GPIO105
      ARM: pxa/hx4700: Reduce sleep mode battery discharge by 35%
      pxa/hx4700: Remove pcmcia platform_device structure

 arch/arm/mach-pxa/hx4700.c                  |   17 ++---------------
 arch/arm/mach-pxa/include/mach/mfp-pxa27x.h |    2 ++
 2 files changed, 4 insertions(+), 15 deletions(-)


Best Regards
Haojian


From catalin.marinas at arm.com  Wed Mar 14 06:33:52 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 14 Mar 2012 10:33:52 +0000
Subject: [PATCH v3 0/5] ARM: Initial support for Cortex-M3
In-Reply-To: <20120314101928.GA29474@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
Message-ID: <20120314103352.GA20899@arm.com>

On Wed, Mar 14, 2012 at 10:19:28AM +0000, Uwe Kleine-K?nig wrote:
> this is the result of reworking Catalin's exception handling patch to
> stick to the current pt_regs layout. I extended it by two words to save
> the exception return value. (The 2nd word is unused and only to maintain
> stack alignment.)
> 
> Other than that only minor cleanups were done (some of them were
> suggested by Catalin in reply to my v2 series).
> 
> These patches are available at
> 
> 	git://git.pengutronix.de/git/ukl/linux.git cortexm3-for-rmk
> 
> basing on 3.3-rc7. There are some bits missing to allow a Cortex-M3 to
> boot. They are contained in the branch efm32 in the same repository
> together with support for the efm32 SoC if you're interested.
> The most important parts missing (apart from SoC specific stuff) are
> interrupt support and Makefile/Kconfig glue.
> 
> I'd be happy if these patches made it into 3.4-rc1.

That's pretty ambitious. Most maintainers (including Russell) closed
their trees by now. You can still aim for 3.5-rc1 and ideally have them
in -next a few weeks before (though only once Russell is fine with the
patches).

> Any constructive feedback welcome.

I'll go through the patches sometime next week.

-- 
Catalin


From sr at denx.de  Wed Mar 14 06:36:48 2012
From: sr at denx.de (Stefan Roese)
Date: Wed, 14 Mar 2012 11:36:48 +0100
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203140948.44823.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203140840.18333.sr@denx.de> <201203140948.44823.arnd@arndb.de>
Message-ID: <201203141136.48513.sr@denx.de>

On Wednesday 14 March 2012 10:48:44 Arnd Bergmann wrote:
> > > I would suggest you convert these to DT next so you can remove the
> > > amba_devs list. Which devices are these? If they are pl061 and
> > > pl010/pl011, the binding should be really easy to do.
> > 
> > Yes. I really wanted to do that. But from a quick look at the pl011
> > driver (drivers/tty/serial/amba-pl011.c), this driver doesn't support DT
> > probing. I might have missed something here though. And ideas?
> 
> amba primecell devices don't actually need to register to a "compatible"
> property, they are probed using the primecell ID, and the device tree
> is just used to tell the system about memory and IRQ resources.

Ahh, I see. Let me see, if I can get this working...
 
> The pl061 driver has support for setting the gc.base and irq_base using
> device tree instead of the platform data and that might be enough.
> 
> > > Since there is only one upstream board file and that is for the same
> > > board, we can soon collapse all of it into the base platform support.
> > > 
> > > I think you should add all the code from this file to spear6xx.c
> > > instead of adding a new file. We can then delete the spear600.c and
> > > spear600_evb.c files once the DT support has matured.
> > 
> > Sounds like a plan. I'll rework the patch soon.
> 
> Great!
> 
> Don't worry about the the gpio and uart devices if they are not in the
> first initial version. I do think that they should be done fairly soon
> though, before we get into most of the other devices.
> 
> It's ok if you put a lot of the other devices in the dts file though,
> like the ethernet device, it gives a better overview of what is actually
> there, even if the driver does not actually use it yet.

My initial idea was to push the devices once their DT support is accepted. 
Otherwise the bindings are still not settled.

Thanks,
Stefan


From haojian.zhuang at gmail.com  Wed Mar 14 06:37:46 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 18:37:46 +0800
Subject: [GIT PULL][for 3.4] pull request from fixes-non-critical branch in
 arch-pxa git
Message-ID: <CAN1soZy5LR2vFF4BNgiuUcWubCdt1+a+nEwVM24WavOR8oJRkA@mail.gmail.com>

Hi Arnd & Olof,

Please help to pull commits from fixes-non-critical branch in arch-pxa git tree.

The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:

  Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)

are available in the git repository at:
  git://github.com/hzhuang1/linux.git fixes-non-critical

Haojian Zhuang (1):
      MAINTAINERS: update MAINTAINERS email entry

Philipp Zabel (1):
      MAINTAINERS: update maintainer entry for pxa/hx4700

 MAINTAINERS |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

Thanks
Haojian


From viresh.kumar at st.com  Wed Mar 14 06:02:42 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 14 Mar 2012 15:32:42 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203140958.27289.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203131644.12048.arnd@arndb.de> <4F604400.1040805@st.com>
 <201203140958.27289.arnd@arndb.de>
Message-ID: <4F606CC2.9000402@st.com>

On 3/14/2012 3:28 PM, Arnd Bergmann wrote:
> No problem, we are all learning things as we are working on them.
> 
> The idea with DT is that you no longer need any board files because all of
> the information in those files is now passed as a data structure to the kernel
> at boot time. Platforms that are fully converted to DT don't have any
> board files but just have one DT_MACHINE_START entry for all of them in
> the common platform files. Since spear600 has very little board specific
> contents at the moment, it is very easy to get to this point now, and
> that will actually help support other boards without having to do more
> patches to add board files.
> 
> When this work is completed, we might actually be able to extend the
> spear6xx DT code to also support spear3xx and spear13xx, renaming it
> to mach-spear. In that case, we would probably need one DT_MACHINE_START
> entry for each family and would not be able to actually build 13xx together
> with the other ones, but I guess a lot of the infrastructure could be shared.
> 
> I would suggest you read Documentation/devicetree/booting-without-of.txt
> to get a better understanding of what this is all about.

You pointed exactly to the doubt i had.
That was very helpful. I really appreciate it.

Thanks a lot.

-- 
viresh


From vinod.koul at intel.com  Wed Mar 14 07:14:54 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Wed, 14 Mar 2012 16:44:54 +0530
Subject: [PATCH v3 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <CACKLOr0XzE0PZk=k5xQQvOA_5dfBk1mYDVyKCep36=3w7ugwWg@mail.gmail.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
 <20120309174411.GI3852@pengutronix.de>
 <CACKLOr0XzE0PZk=k5xQQvOA_5dfBk1mYDVyKCep36=3w7ugwWg@mail.gmail.com>
Message-ID: <1331723694.1727.28.camel@vkoul-udesk3>

On Wed, 2012-03-14 at 08:43 +0100, javier Martin wrote:
> On 9 March 2012 18:44, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > On Fri, Mar 09, 2012 at 04:20:36PM +0100, Javier Martin wrote:
> >> The following series have to be applied on top of the following patches:
> >> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
> >> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
> >>
> >> As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
> >> is deprecated and no new patches are accepted for it.
> >>
> >> This series merges this code into the imx-dma.c dmaengine driver.
> >
> > Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> >
> 
> Vinod,
> I think with Sascha's ack, this series is ready to be merged. It's
> quite important for us that it makes it for 3.4.
> 
> Please, don't forget the following patch too, which is meant to be
> applied on top of this series:
> 
> [PATCH] dmaengine: i.MX: Add support for interleaved transfers.
> 
This is my merge queue which means I will merged it after the cookie
fixes (hate rebasing that series again)

-- 
~Vinod



From dave.martin at linaro.org  Wed Mar 14 07:15:04 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Wed, 14 Mar 2012 11:15:04 +0000
Subject: [PATCH] arm: Add unwinding support for memset and memzero.
In-Reply-To: <1331574027-28542-1-git-send-email-lauraa@codeaurora.org>
References: <1331574027-28542-1-git-send-email-lauraa@codeaurora.org>
Message-ID: <20120314111504.GA2033@linaro.org>

On Mon, Mar 12, 2012 at 10:40:27AM -0700, Laura Abbott wrote:
> Both memset and memzero lack unwinding annoations. If
> an abort occurs trying to access the pointer, the backtrace
> is incomplete. Add unwinding annotations to both functions
> so we can actually get a useful backtrace.
> 
> Signed-off-by: Laura Abbott <lauraa at codeaurora.org>
> ---
>  arch/arm/lib/memset.S  |    7 +++++--
>  arch/arm/lib/memzero.S |    7 +++++--
>  2 files changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
> index 650d592..4379912 100644
> --- a/arch/arm/lib/memset.S
> +++ b/arch/arm/lib/memset.S
> @@ -11,6 +11,7 @@
>   */
>  #include <linux/linkage.h>
>  #include <asm/assembler.h>
> +#include <asm/unwind.h>
>  
>  	.text
>  	.align	5
> @@ -29,6 +30,7 @@
>   */
>  
>  ENTRY(memset)
> +UNWIND(.fnstart)
>  	ands	r3, r0, #3		@ 1 unaligned?
>  	bne	1b			@ 1
>  /*
> @@ -41,7 +43,7 @@ ENTRY(memset)
>  	blt	4f
>  
>  #if ! CALGN(1)+0
> -
> +UNWIND(.save {lr})
>  /*
>   * We need an extra register for this loop - save the return address and
>   * use the LR
> @@ -68,7 +70,7 @@ ENTRY(memset)
>  	ldr	lr, [sp], #4
>  
>  #else
> -
> +UNWIND(.save {r4, r5, r6, r7, lr})

For functions like this, the unwinding requirements are different
depending on where we are in the function.  But the unwinder annotations
don't remember exact instruction locations; only the extent of the
whole unwind block is recorded, along with the sequence (but not
location) of unwinder directives.

As is, the unwinding may be wrong depending on which part of the function
is executing when the fault occurs.

It may be possible to split the function into multiple unwind blocks,
e.g.:

ENTRY(somefunc)
UNWIND(.fnstart)

UNWIND(.save {r4,lr})
	stfmd	sp!, {r4,lr}

	/* check something */

	blt	_the_other_way
	/* maybe carry out our job this way */

	ldmfd	sp!, {r4,lr}
UNWIND(.fnend)

_the_other_way:
UNWIND(.fnstart)
UNWIND(.save {r4,lr})
UNWIND(.save {r5-r8})
	stmfd	sp!, {r5-r8}	/* !! */

	/* carry out our job the other way */

	ldmfd	sp!, {r5-r8}
	ldmfd	sp!, {r4,pc}	/* !! */
UNWIND(.fnend)


This is still not exactly right (it's hard to be exactly right,
since the unwind tables are not meant for handling asynchronous
unwinding), but unwinding should be correct for the main bits of code
where most time is spent and/or faults are most likely (the "carry out
our job" comments).

You'd have to experiment to see whether the backtracer does something
sensible with unwind tables like this.  It might need tweaking to
find the correct function symbol if a fault occurs in the second
unwind block for example ... that perhaps it will already do the
right thing.

Cheers
---Dave



From marek.vasut at gmail.com  Wed Mar 14 07:17:19 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 14 Mar 2012 12:17:19 +0100
Subject: [PATCH v1 2/5] mmc: mxs-mmc: add dt probe support
In-Reply-To: <20120314072603.GC8494@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <201203140809.22676.marek.vasut@gmail.com>
 <20120314072603.GC8494@shlinux2.ap.freescale.net>
Message-ID: <201203141217.19842.marek.vasut@gmail.com>

Dear Dong Aisheng,

> On Wed, Mar 14, 2012 at 08:09:22AM +0100, Marek Vasut wrote:
> > Dear Dong Aisheng,
> > 
> > > On Wed, Mar 14, 2012 at 01:58:25PM +0800, Marek Vasut wrote:
> > > > Dear Dong Aisheng,
> > > > 
> > > > > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > > 
> > > ........
> > > 
> > > > > +static const struct of_device_id mxs_mmc_dt_ids[] = {
> > > > > +	{ .compatible = "fsl,imx23-mmc", .data = NULL, },
> > > > > +	{ .compatible = "fsl,imx28-mmc", .data = NULL, },
> > > > 
> > > > Do you really need two distinct ones here?
> > > 
> > > Hmm, my original purpose is to put soc difference data in .data
> > > to remove cpu_is_* function calls in the driver later.
> > > Do you think if any issue?
> > 
> > Well, what's the difference between the interfaces on mx233 and mx28? Is
> > it something that can't be encoded otherwise? I think they're not so
> > different.
> 
> Not much difference except the one register offset and ip version.
> See:
> #define SSP_VERSION_LATEST      4
> #define ssp_is_old()            (host->version < SSP_VERSION_LATEST)
> ..
> #define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130)
> The ip version can be handled in driver, but for offset...
> it depends on cpu_is_* macro.
> Putting the HW_SSP_VERSION offset difference in .data can eliminate the
> need of cpu_is_*.
> 
> Despite of that, since they're two devices,
> i guess it's ok to put two compatible string there, right?
> Or you thought just put one as below?
> { .compatible = "fsl,mxs-mmc", .data = NULL, },
> 
No, I understand now /wrt the register layout.

Best regards,
Marek Vasut


From broonie at opensource.wolfsonmicro.com  Wed Mar 14 07:28:20 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 14 Mar 2012 11:28:20 +0000
Subject: [PATCH v4 02/11] ep93xx: Don't use system controller defines in
 audio drivers
In-Reply-To: <4F5FF1DD.5020003@gmail.com>
References: <1331592502-9083-3-git-send-email-rmallon@gmail.com>
 <201203131209.52031.arnd@arndb.de> <4F5FF1DD.5020003@gmail.com>
Message-ID: <20120314112820.GA3133@opensource.wolfsonmicro.com>

On Wed, Mar 14, 2012 at 12:18:21PM +1100, Ryan Mallon wrote:

> Okay, the patches still need to be posted as a series for review before
> doing a pull request though right? Should I just put a note on such
> patches (below the changelog) that I am expecting to send them all via
> arm-soc so that other maintainers don't grab individual patches for
> driver support?

You should always say if there's some dependency.  With things like this
it's possibly easier to leave the defines hanging around for a while and
then send a followup patch which removes them, that way there's no
dependencies.
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From shawn.guo at linaro.org  Wed Mar 14 07:33:00 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 14 Mar 2012 19:33:00 +0800
Subject: [PATCH v4] ASoC: add imx-sgtl5000 machine driver working with
 fsl_ssi
In-Reply-To: <20120314090115.GN3852@pengutronix.de>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
 <20120314090115.GN3852@pengutronix.de>
Message-ID: <20120314113258.GG21337@S2101-09.ap.freescale.net>

On Wed, Mar 14, 2012 at 10:01:15AM +0100, Sascha Hauer wrote:
...
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> 
Thanks.

> What are the next steps here? Now we have fsl_ssi.c and imx-ssi.c, one
> for dt bindings and the other one for platform bindings and also AC97
> support. They should probably get merged some day which might be a bit
> difficult since currently I don't see the platform users moving over
> to devicetree and the seem to be no AC97 users in powerpc.
> 
When I was tasked to add DT support for imx5 audio driver, it was my
first attempt to add it on top of imx-ssi driver.  But Timur strongly
disagree with that.  Instead, he asked me to reuse fsl_ssi.  That's
why I came up with this series.  I did not really plan to completely
remove imx-ssi by merging it into fsl_ssi.  But if someday we have all
those imx-ssi users migrated to DT, that will become something we
should consider to do then.

-- 
Regards,
Shawn


From sshtylyov at mvista.com  Wed Mar 14 07:32:19 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 14 Mar 2012 15:32:19 +0400
Subject: [PATCH] arm:da850: register musb device
In-Reply-To: <A73F36158E33644199EB82C5EC81C7BC3178406C@DBDE01.ent.ti.com>
References: <1331651015-32586-1-git-send-email-prakash.pm@ti.com>
 <4F5F7F91.8010301@mvista.com>
 <A73F36158E33644199EB82C5EC81C7BC3178406C@DBDE01.ent.ti.com>
Message-ID: <4F6081C3.4070905@mvista.com>

Hello.

On 14-03-2012 10:16, Manjunathappa, Prakash wrote:

>>> Properly set up the OTG mode thru the CFGCHIP2 register, enable the
>>> USB0_DRVVBUS pin,

>>      I don't see where you are enabling it.

> Yes, I will correct the message.

>>> and finally register the MUSB platform device.

    Also, you're registering the MUSB device for DA850/OMAP-L138 EVM board, 
not the whole DA850/OMAP-L138 SoC, so that should be reflected in the subject.

>>> Signed-off-by: Ajay Kumar Gupta<ajay.gupta at ti.com>
>>> Signed-off-by: Manjunathappa, Prakash<prakash.pm at ti.com>

WBR, Sergei


From peppe.cavallaro at st.com  Wed Mar 14 07:38:22 2012
From: peppe.cavallaro at st.com (Giuseppe CAVALLARO)
Date: Wed, 14 Mar 2012 12:38:22 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <20120312143825.GB13869@game.jcrosoft.org>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <20120312143825.GB13869@game.jcrosoft.org>
Message-ID: <4F60832E.6060100@st.com>

On 3/12/2012 3:38 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:05 Mon 12 Mar     , Stefan Roese wrote:
>> This patch adds support to configure the STMMAC ethernet driver via
>> device-tree instead of platform_data.
>>
>> Currently, only the properties needed on SPEAr600 are provided. All
>> other properties should be added once needed on other platforms.
>>
>> Signed-off-by: Stefan Roese <sr at denx.de>
>> Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
>> Cc: Viresh Kumar <viresh.kumar at st.com>
>> ---
>>  Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
>>  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66 +++++++++++++++++++-
>>  2 files changed, 103 insertions(+), 1 deletion(-)
>>  create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt
>>
>> diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
>> new file mode 100644
>> index 0000000..386a47f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/net/stmmac.txt
>> @@ -0,0 +1,38 @@
>> +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
>> +
>> +Required properties:
>> +- compatible: Should be "stm,gmac"

> this IP have 2 version at least the GMAC for the second generation and mac for
> the first generation

yes you are right. STMMAC supports two device generations I named:
dwma10/100 and dwmac1000 (gmac).

Concerning the latter, we support several different versions of the
synopsys GMAC cores ... from 3.30 to 3.61a.

For example, stx7108 and Stx7109 have the same GMAC core (also SPEAr600
IIRC).
SPEAr13xx has 3.50a
New ST SoC Stxh415 has the 3.60a. etc.

>> +- reg: Address and length of the register set for the device
>> +- interrupt-parent: Should be the phandle for the interrupt controller
>> +  that services interrupts for this device
>> +- interrupts: Should contain the STMMAC interrupts
>> +- interrupt-names: Should contain the interrupt names "macirq"
>> +  "eth_wake_irq" if this interrupt is supported in the "interrupts"
>> +  property
> optionnal

yes

note that there will be a new field for lpi IRQ as well

>> +- phy-mode: String, operation mode of the PHY interface.
>> +  Supported values are: "mii", "rmii", "gmii", "rgmii".
>> +- phy-addr: MDIO address of the PHY
>> +
>> +Optional properties:
>> +- stm,prog-burst-len: Specify the burst length
>> +- stm,has-gmac: Indicates that the controller supports 1000Mbps
> this IP support more mode 10/100/300/1000

has_gmac was used to understand on devices w/o the HW cap registers if
the core is a gmac... another useful parameter could be : enh_desc

In fact, there are several possible HW configurations:

gmac core + enh desc
gmac core + norm_desc
mac  core + norm_des

...

W/o cap register (present in new cores newer than 3.50) we need to pass
this info from the plt.

>> +- stm,has-pmt: Indicates that the controller supports power management
>> +- mac-address: 6 bytes, mac address
>> +
>> +Examples:
>> +
>> +	gmac0: stmmac at e0800000 {
>> +		compatible = "stm,gmac";
>> +		reg = <0xe0800000 0x8000>;
>> +		interrupt-parent = <&vic1>;
>> +		interrupts = <24 23>;
>> +		interrupt-names = "macirq", "eth_wake_irq";
>> +		mac-address = [000000000000]; /* Filled in by U-Boot */
>> +
>> +		stm,prog-burst-len = <8>;
>> +		stm,has-gmac;
>> +		stm,has-pmt;
>> +
>> +		phy-mode = "gmii";
>> +		phy-addr = <0>;
>> +	};
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
>> index 3aad981..fcf46c7 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
>> @@ -24,8 +24,43 @@
>>  
>>  #include <linux/platform_device.h>
>>  #include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/of_net.h>
>>  #include "stmmac.h"
>>  
>> +#ifdef CONFIG_OF
>> +static int __devinit stmmac_probe_config_dt(struct platform_device *pdev,
>> +					    struct plat_stmmacenet_data *plat,
>> +					    const char **mac)
>> +{
>> +	struct device_node *np = pdev->dev.of_node;
>> +
>> +	if (!np)
>> +		return -ENODEV;
>> +
>> +	*mac = of_get_mac_address(np);
>> +
>> +	plat->interface = of_get_phy_mode(np);
>> +	of_property_read_u32(np, "phy-addr", &plat->phy_addr);
>> +	plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
>> +					   sizeof(struct stmmac_mdio_bus_data),
>> +					   GFP_KERNEL);
>> +
>> +	/*
>> +	 * Currently only the properties needed on SPEAr600
>> +	 * are provided. All other properties should be added
>> +	 * once needed on other platforms.
>> +	 */
>> +	of_property_read_u32(np, "stm,prog-burst-len", &plat->pbl);
>> +	if (of_get_property(np, "stm,has-gmac", NULL))
>> +		plat->has_gmac = 1;
>> +	if (of_get_property(np, "stm,has-pmt", NULL))
>> +		plat->pmt = 1;
>> +
>> +	return 0;
>> +}
>> +#endif /* CONFIG_OF */
>> +
>>  /**
>>   * stmmac_pltfr_probe
>>   * @pdev: platform device pointer
>> @@ -39,7 +74,8 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>>  	struct resource *res;
>>  	void __iomem *addr = NULL;
>>  	struct stmmac_priv *priv = NULL;
>> -	struct plat_stmmacenet_data *plat_dat;
>> +	struct plat_stmmacenet_data *plat_dat = NULL;
>> +	const char *mac = NULL;
>>  
>>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>  	if (!res)
>> @@ -58,6 +94,22 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>>  		ret = -ENOMEM;
>>  		goto out_release_region;
>>  	}
>> +
>> +#ifdef CONFIG_OF
>> +	plat_dat = devm_kzalloc(&pdev->dev, sizeof(struct plat_stmmacenet_data),
>> +				GFP_KERNEL);
>> +	if (!plat_dat) {
>> +		pr_err("%s: ERROR: no memory", __func__);
>> +		ret = -ENOMEM;
>> +		goto out_unmap;
>> +	}
>> +
>> +	ret = stmmac_probe_config_dt(pdev, plat_dat, &mac);
>> +	if (ret) {
>> +		pr_err("%s: main dt probe failed", __func__);
>> +		goto out_unmap;
>> +	}
>> +#else
> This must be check at runtime, we can boot a kernel with or without DT.
> 
> Best Reards,
> J.
>>  	plat_dat = pdev->dev.platform_data;
>>  
>>  	/* Custom initialisation (if needed)*/
>> @@ -66,6 +118,7 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>>  		if (unlikely(ret))
>>  			goto out_unmap;
>>  	}
>> +#endif
>>  
>>  	priv = stmmac_dvr_probe(&(pdev->dev), plat_dat, addr);
>>  	if (!priv) {
>> @@ -73,6 +126,10 @@ static int stmmac_pltfr_probe(struct platform_device *pdev)
>>  		goto out_unmap;
>>  	}
>>  
>> +	/* Get MAC address if available (DT) */
>> +	if (mac)
>> +		memcpy(priv->dev->dev_addr, mac, ETH_ALEN);
>> +
>>  	/* Get the MAC information */
>>  	priv->dev->irq = platform_get_irq_byname(pdev, "macirq");
>>  	if (priv->dev->irq == -ENXIO) {
>> @@ -178,6 +235,12 @@ static const struct dev_pm_ops stmmac_pltfr_pm_ops = {
>>  static const struct dev_pm_ops stmmac_pltfr_pm_ops;
>>  #endif /* CONFIG_PM */
>>  
>> +static const struct of_device_id stmmac_dt_ids[] = {
>> +	{ .compatible = "stm,gmac", },
>> +	{ /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, stmmac_dt_ids);
>> +
>>  static struct platform_driver stmmac_driver = {
>>  	.probe = stmmac_pltfr_probe,
>>  	.remove = stmmac_pltfr_remove,
>> @@ -185,6 +248,7 @@ static struct platform_driver stmmac_driver = {
>>  		   .name = STMMAC_RESOURCE_NAME,
>>  		   .owner = THIS_MODULE,
>>  		   .pm = &stmmac_pltfr_pm_ops,
>> +		   .of_match_table = of_match_ptr(stmmac_dt_ids),
>>  		   },
>>  };
>>  
>> -- 
>> 1.7.9.2
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe netdev" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 



From nicolas.ferre at atmel.com  Wed Mar 14 07:41:43 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 14 Mar 2012 12:41:43 +0100
Subject: [PATCH] dmaengine: at_hdmac: add slave config operation
Message-ID: <1331725303-26298-1-git-send-email-nicolas.ferre@atmel.com>

This patch introduces DMA_SLAVE_CONFIG to at_hdmac Atmel DMA driver.

It is needed to fix a regression in the use of atmel-mci.c driver on Atmel
AT91 platforms brouth by e2b35f3:
"dmaengine/dw_dmac: Fix dw_dmac user drivers to adapt to slave_config changes"

We remove some parts of the private structure "at_dma_slave" and use the
information provided by "struct dma_slave_config": source/destination
peripheral registers and access width.

AT_DMA_SLAVE_WIDTH_* values used previously are not needed anymore as we
now use the standard ones. Although some conversion functions are needed to
match register expected values.

Some AT91 sub-architecture specific files are slightly touched by this patch
but it cannot be split because it can break compilation.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/at91sam9g45_devices.c   |    1 -
 arch/arm/mach-at91/include/mach/at_hdmac.h |   15 -------
 drivers/dma/at_hdmac.c                     |   56 +++++++++++++++++++++------
 drivers/dma/at_hdmac_regs.h                |   32 ++++++++++++++++
 4 files changed, 75 insertions(+), 29 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 96e2adc..28d3401 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -432,7 +432,6 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
 
 	/* DMA slave channel configuration */
 	atslave->dma_dev = &at_hdmac_device.dev;
-	atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
 	atslave->cfg = ATC_FIFOCFG_HALFFIFO
 			| ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
 	atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h
index 187cb58..fff48d1 100644
--- a/arch/arm/mach-at91/include/mach/at_hdmac.h
+++ b/arch/arm/mach-at91/include/mach/at_hdmac.h
@@ -24,18 +24,6 @@ struct at_dma_platform_data {
 };
 
 /**
- * enum at_dma_slave_width - DMA slave register access width.
- * @AT_DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
- * @AT_DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
- * @AT_DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
- */
-enum at_dma_slave_width {
-	AT_DMA_SLAVE_WIDTH_8BIT = 0,
-	AT_DMA_SLAVE_WIDTH_16BIT,
-	AT_DMA_SLAVE_WIDTH_32BIT,
-};
-
-/**
  * struct at_dma_slave - Controller-specific information about a slave
  * @dma_dev: required DMA master device
  * @tx_reg: physical address of data register used for
@@ -48,9 +36,6 @@ enum at_dma_slave_width {
  */
 struct at_dma_slave {
 	struct device		*dma_dev;
-	dma_addr_t		tx_reg;
-	dma_addr_t		rx_reg;
-	enum at_dma_slave_width	reg_width;
 	u32			cfg;
 	u32			ctrla;
 };
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 5d225dd..b015a5c 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -647,6 +647,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 {
 	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
 	struct at_dma_slave	*atslave = chan->private;
+	struct dma_slave_config	*sconfig = &atchan->dma_sconfig;
 	struct at_desc		*first = NULL;
 	struct at_desc		*prev = NULL;
 	u32			ctrla;
@@ -668,19 +669,18 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 		return NULL;
 	}
 
-	reg_width = atslave->reg_width;
-
 	ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla;
 	ctrlb = ATC_IEN;
 
 	switch (direction) {
 	case DMA_MEM_TO_DEV:
+		reg_width = convert_buswidth(sconfig->dst_addr_width);
 		ctrla |=  ATC_DST_WIDTH(reg_width);
 		ctrlb |=  ATC_DST_ADDR_MODE_FIXED
 			| ATC_SRC_ADDR_MODE_INCR
 			| ATC_FC_MEM2PER
 			| ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF);
-		reg = atslave->tx_reg;
+		reg = sconfig->dst_addr;
 		for_each_sg(sgl, sg, sg_len, i) {
 			struct at_desc	*desc;
 			u32		len;
@@ -708,13 +708,14 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 		}
 		break;
 	case DMA_DEV_TO_MEM:
+		reg_width = convert_buswidth(sconfig->src_addr_width);
 		ctrla |=  ATC_SRC_WIDTH(reg_width);
 		ctrlb |=  ATC_DST_ADDR_MODE_INCR
 			| ATC_SRC_ADDR_MODE_FIXED
 			| ATC_FC_PER2MEM
 			| ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF);
 
-		reg = atslave->rx_reg;
+		reg = sconfig->src_addr;
 		for_each_sg(sgl, sg, sg_len, i) {
 			struct at_desc	*desc;
 			u32		len;
@@ -790,12 +791,15 @@ err_out:
  * atc_dma_cyclic_fill_desc - Fill one period decriptor
  */
 static int
-atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
+atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
 		unsigned int period_index, dma_addr_t buf_addr,
-		size_t period_len, enum dma_transfer_direction direction)
+		unsigned int reg_width, size_t period_len,
+		enum dma_transfer_direction direction)
 {
-	u32		ctrla;
-	unsigned int	reg_width = atslave->reg_width;
+	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
+	struct at_dma_slave	*atslave = chan->private;
+	struct dma_slave_config	*sconfig = &atchan->dma_sconfig;
+	u32			ctrla;
 
 	/* prepare common CRTLA value */
 	ctrla =   ATC_DEFAULT_CTRLA | atslave->ctrla
@@ -806,7 +810,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
 	switch (direction) {
 	case DMA_MEM_TO_DEV:
 		desc->lli.saddr = buf_addr + (period_len * period_index);
-		desc->lli.daddr = atslave->tx_reg;
+		desc->lli.daddr = sconfig->dst_addr;
 		desc->lli.ctrla = ctrla;
 		desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED
 				| ATC_SRC_ADDR_MODE_INCR
@@ -816,7 +820,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
 		break;
 
 	case DMA_DEV_TO_MEM:
-		desc->lli.saddr = atslave->rx_reg;
+		desc->lli.saddr = sconfig->src_addr;
 		desc->lli.daddr = buf_addr + (period_len * period_index);
 		desc->lli.ctrla = ctrla;
 		desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR
@@ -847,9 +851,11 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 {
 	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
 	struct at_dma_slave	*atslave = chan->private;
+	struct dma_slave_config	*sconfig = &atchan->dma_sconfig;
 	struct at_desc		*first = NULL;
 	struct at_desc		*prev = NULL;
 	unsigned long		was_cyclic;
+	unsigned int		reg_width;
 	unsigned int		periods = buf_len / period_len;
 	unsigned int		i;
 
@@ -869,8 +875,13 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 		return NULL;
 	}
 
+	if (sconfig->direction == DMA_MEM_TO_DEV)
+		reg_width = convert_buswidth(sconfig->dst_addr_width);
+	else
+		reg_width = convert_buswidth(sconfig->src_addr_width);
+
 	/* Check for too big/unaligned periods and unaligned DMA buffer */
-	if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr,
+	if (atc_dma_cyclic_check_values(reg_width, buf_addr,
 					period_len, direction))
 		goto err_out;
 
@@ -882,8 +893,8 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 		if (!desc)
 			goto err_desc_get;
 
-		if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr,
-						period_len, direction))
+		if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr,
+					     reg_width, period_len, direction))
 			goto err_desc_get;
 
 		atc_desc_chain(&first, &prev, desc);
@@ -906,6 +917,23 @@ err_out:
 	return NULL;
 }
 
+static int set_runtime_config(struct dma_chan *chan,
+			      struct dma_slave_config *sconfig)
+{
+	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
+
+	/* Check if it is chan is configured for slave transfers */
+	if (!chan->private)
+		return -EINVAL;
+
+	memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig));
+
+	convert_burst(&atchan->dma_sconfig.src_maxburst);
+	convert_burst(&atchan->dma_sconfig.dst_maxburst);
+
+	return 0;
+}
+
 
 static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		       unsigned long arg)
@@ -966,6 +994,8 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		clear_bit(ATC_IS_CYCLIC, &atchan->status);
 
 		spin_unlock_irqrestore(&atchan->lock, flags);
+	} else if (cmd == DMA_SLAVE_CONFIG) {
+		return set_runtime_config(chan, (struct dma_slave_config *)arg);
 	} else {
 		return -ENXIO;
 	}
diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
index 08fd8a0..897a8bc 100644
--- a/drivers/dma/at_hdmac_regs.h
+++ b/drivers/dma/at_hdmac_regs.h
@@ -207,6 +207,7 @@ enum atc_status {
  * @save_cfg: configuration register that is saved on suspend/resume cycle
  * @save_dscr: for cyclic operations, preserve next descriptor address in
  *             the cyclic list on suspend/resume cycle
+ * @dma_sconfig: configuration for slave transfers, passed via DMA_SLAVE_CONFIG
  * @lock: serializes enqueue/dequeue operations to descriptors lists
  * @active_list: list of descriptors dmaengine is being running on
  * @queue: list of descriptors ready to be submitted to engine
@@ -222,6 +223,7 @@ struct at_dma_chan {
 	struct tasklet_struct	tasklet;
 	u32			save_cfg;
 	u32			save_dscr;
+	struct dma_slave_config dma_sconfig;
 
 	spinlock_t		lock;
 
@@ -243,6 +245,36 @@ static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
 	return container_of(dchan, struct at_dma_chan, chan_common);
 }
 
+/*
+ * Fix sconfig's burst size according to at_hdmac. We need to convert them as:
+ * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
+ *
+ * This can be done by finding most significant bit set.
+ */
+static inline void convert_burst(u32 *maxburst)
+{
+	if (*maxburst > 1)
+		*maxburst = fls(*maxburst) - 2;
+	else
+		*maxburst = 0;
+}
+
+/*
+ * Fix sconfig's bus width according to at_hdmac.
+ * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
+ */
+static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
+{
+	switch (addr_width) {
+	case DMA_SLAVE_BUSWIDTH_2_BYTES:
+		return 1;
+	case DMA_SLAVE_BUSWIDTH_4_BYTES:
+		return 2;
+	default:
+		/* For 1 byte width or fallback */
+		return 0;
+	}
+}
 
 /*--  Controller  ------------------------------------------------------*/
 
-- 
1.7.9



From tomi.valkeinen at ti.com  Wed Mar 14 08:06:34 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Wed, 14 Mar 2012 14:06:34 +0200
Subject: OMAP DSS device tree design problems
In-Reply-To: <4F5FCE64.5070902@ti.com>
References: <1331559930.2097.100.camel@deskari>  <4F5FCE64.5070902@ti.com>
Message-ID: <1331726794.2386.66.camel@deskari>

On Tue, 2012-03-13 at 23:47 +0100, Cousson, Benoit wrote:

> I'm just wondering if the multiple panels is something supported by the 
> DSI protocol or it is a HW hacks done on TI board only?

In theory both, but the driver doesn't support multiple panels connected
to single DSI output at the same time. And that is, in a way, easier
regarding DT, as all the configuration parameters are specific to DSI
and the panel.

But the case at hand is that two panels are connected to single DSI
output, but there's an external switch/mux between the DSI output or
GPIO lines and the panels. It's not a HW hack on TI development boards
only. The means to switch between the two displays can be anything, from
setting a single GPIO to, say, sending i2c commands to some mux chip.

> > However, here the problem is that while ultimately we're interested in
> > the ddr-clk rate, calculation of the rate is non-trivial and may need
> > customizations at times. So instead of the clock rate we actually need
> > to define a bunch of dividers/multipliers.
> 
> Well, in theory you should not. This is up to the clock provider to 
> convert the clock rate in the proper n/m value. This is how it is done 
> for the regular OMAP DPLLs.

Right. But it's a non trivial problem. There are multiple
dividers/multipliers in the path, and the clocks from different points
at that path are used for different purposes. Some of the div/mul fields
are quite wide, so there are a lot of numbers to iterate. 

And in many cases it's important to get sometimes exact, and sometimes
almost exact, clock rate, but still at times go with a less exact clock
rate if that gives you lower power consumption, or some other similar
side effect.

So we currently calculate the dividers manually in most cases.

> > and the Taal driver would ignore those, but dsi driver would use them?
> > This looks like quite easy solution to this, but also doesn't feel
> > right. So my current idea is to have clk-div tables in the dsi node,
> > something like this:
> >
> > dsi1 {
> > 	omap-specific-clk-divs =<
> > 		250 1 2 3 4 5 6 7 /* divs that produce 250MHz clk */
> > 		350 7 6 5 4 3 2 1 /* divs that produce 350MHz clk */
> > 	>;
> 
> That's the idea, except that this will represent the clock provider.

Hmm... So. Should I have something like:

dsi1 {
	dsi1-pll: dsipll {
	 	clk-table = <
 			250 1 2 3 4 5 6 7 /* 250MHz clk */
 			350 7 6 5 4 3 2 1 /* 350MHz clk */
		>;
	};

	taal {
		dsi-clk-src = <&dsi1-pll>;
		dsi-clk-rate = <250000000>;
	};
}

But no, I don't think that's correct. The panel is not using the DSI
PLL. DSI protocol engine and DSI PHY are using the DSI PLL, and they
produce the output on the DSI bus, with the speed that the panel wants.

> > 	taal {
> > 		dsi-ddr-clk =<250000000>;
> 
> And here you will have a phandle to the clock provider. And use it to 
> set the proper clock rate.

I'm not sure if a "clock provider" is correct here. It's not really a
clock, in the strict sense, that goes to the panel from OMAP. It's the
speed of the DSI bus we are talking about here.

> > lanes =<
> > 	/* pad-pair number, polarity */
> > 	1 0	/* DSI pad pair 1 is used for clk, pol +/-  */
> > 	2 1	/* DSI pad pair 2 is used for data1, pol -/+ */
> > 	0 0	/* DSI pad pair 0 is used for data2, pol +/- */
> >> ;
> >
> > Now, I don't quite know where this data should be. If it's in the
> > dsi-node, it doesn't work with multiple panels.
> 
> Is the lane configuration only dependent of the panel?

If you mean, is the lane config the same on every board that uses the
panel, then no. The lane config tells which pin on OMAP is used for
which purpose in the DSI bus.

So if the DSI panel supports two datalanes, it means it has 6 DSI pins:
2 for clk +/-, 2 for data1, 2 for data2. The HW designed then connects,
say, the panel's CLK+ pin to one of OMAPs DSI pins. The OMAP pin has to
be configured in the system config level for DSI operation, and also we
need to configure the function of the pin to CLK+ in the DSI HW module.

> > But then, it's quite
> > OMAP specific thing. While other platforms probably need some kind of
> > pad configuration also, it may be something totally different. And so it
> > doesn't feel right in the taal-node either.
> >
> > And a look-up table like in the clock case doesn't make much sense
> > either, as we don't have a key here, as we had in the clock case (the
> > dsi-ddr-clk).
> 
> The lane configuration code will belong to the DSI driver. The data will 
> belong to the panel. The panel might use some phandle to the various DSI 
> lane config a provide the needed information.
> 
> This look pretty similar to the pinmux device tree binding that is 
> currently under discussion.
> 
> > So basically the only option I've come up with is to define the lane
> > configuration in the panel's data, and let the dsi driver peek there and
> > configure the HW. And this doesn't feel right.
> 
> This is fine, except for the last part. The panel driver should retrieve 
> the data from the panel node, and call some DSI configuration API using 
> the DSI phandle retrieved from the panel node as well or using the 
> parent node directly if the hierarchy is always the same.

Ok. Then the data format for the lane configuration needs to be generic
so that it fits to all platforms. The one I had is omap specific.

Hmm... Perhaps then something like this:

lanes = <
	2	/* clk + */
	3	/* clk - */
	4	/* data1 + */
	5	/* data1 - */
	0	/* data2 + */
	1	/* data2 - */
	>;

Here the number maps to a DSI pin on the particular DSI output used by
the panel. The DSI driver then needs to use some logic to decide what to
do to convert the pin number in the lane data to actual HW
configuration.

 Tomi

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From broonie at opensource.wolfsonmicro.com  Wed Mar 14 08:27:23 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 14 Mar 2012 12:27:23 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F6008FA.3040805@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
Message-ID: <20120314122723.GC3133@opensource.wolfsonmicro.com>

On Wed, Mar 14, 2012 at 02:57:00AM +0000, Tabi Timur-B04825 wrote:
> Mark Brown wrote:

> > With this card those would just be separate CODECs.  This is a binding
> > for a simple card.

> But that is insufficient for the SSI driver, which is expected to handle 
> multiple SSIs.  If you're going to document a binding for the SSI driver, 
> then you need to document how to handle multiple SSIs.

For almost all SoC audio ports this works in exactly the same way it
works for multiple instances of any other device - you do a binding that
covers a single device and then you bind multiple instances of that
device in the system each of which need know nothing about any other
instances of the IP.  

If your SoC has IP which provides more than one port in a single IP
block then the driver for that IP would need to register multiple DAIs
from a single binding which is again exactly the same thing as you'd do
with any other IP block that behaved similarly.

All of which is exactly the same as for any other device and essentially
irrelevant to how we define the bindings for the cards.

> > The biggest improvement is that the SoC binding knows nothing about the
> > card binding at all, cards are completely separate and are free to
> > define any binding they choose using any number of on-SoC and off-SoC
> > devices.

> Ok, I don't understand that at all.

Do you have some questions about the above?  What is it that you find
unclear?   

> I also don't understand why you insist on perverting my driver to support 
> two incompatible bindings, especially since I still haven't heard an 
> explanation as to what's wrong with the binding that I defined.

We've been through this *repeatedly*, including in the message you're
replying to, and we're still going back to square one every time you
decide to start talking about device tree again.  This is frustrating
in the extreme.
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From paul.gortmaker at windriver.com  Wed Mar 14 08:30:07 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Wed, 14 Mar 2012 08:30:07 -0400
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <CAN1soZzDRR4XQ34WDL48=j+Ff8t5fsCFaccqZAKOQ1OAPeDXcA@mail.gmail.com>
References: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>	<1331242494-3157-1-git-send-email-paul.gortmaker@windriver.com>
 <CAN1soZzDRR4XQ34WDL48=j+Ff8t5fsCFaccqZAKOQ1OAPeDXcA@mail.gmail.com>
Message-ID: <4F608F4F.8020106@windriver.com>

On 12-03-14 04:38 AM, Haojian Zhuang wrote:
> On Fri, Mar 9, 2012 at 5:34 AM, Paul Gortmaker
> <paul.gortmaker at windriver.com> wrote:
>> commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)
>>
>>  "regulator: Remove support for supplies specified by struct device"
>>
>> deletes the field from the struct, but this platform was still trying
>> to set those fields.  Convert them to use the REGULATOR_SUPPLY macro.
>>
>> arch/arm/mach-pxa/magician.c:581: error: unknown field 'dev' specified in initializer
>> arch/arm/mach-pxa/magician.c:581: warning: initialization from incompatible pointer type
>> arch/arm/mach-pxa/magician.c:585: error: unknown field 'dev' specified in initializer
>> arch/arm/mach-pxa/magician.c:585: warning: initialization from incompatible pointer type
>>
>> arch/arm/mach-pxa/hx4700.c:683: error: unknown field 'dev' specified in initializer
>> arch/arm/mach-pxa/hx4700.c:683: warning: initialization from incompatible pointer type
>> arch/arm/mach-pxa/hx4700.c:687: error: unknown field 'dev' specified in initializer
>> arch/arm/mach-pxa/hx4700.c:687: warning: initialization from incompatible pointer type
>>
>> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
>> ---
>>
>> [v3: fix arg2 in REGULATOR_SUPPLY to have correct names ]
>>
>> diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
>> index f2c23ea..b6a338b 100644
>> --- a/arch/arm/mach-pxa/hx4700.c
>> +++ b/arch/arm/mach-pxa/hx4700.c
>> @@ -679,14 +679,8 @@ static struct platform_device power_supply = {
>>  */
>>
>>  static struct regulator_consumer_supply bq24022_consumers[] = {
>> -       {
>> -               .dev = &gpio_vbus.dev,
>> -               .supply = "vbus_draw",
>> -       },
>> -       {
>> -               .dev = &power_supply.dev,
>> -               .supply = "ac_draw",
>> -       },
>> +       REGULATOR_SUPPLY("vbus_draw", "gpio-vbus"),
>> +       REGULATOR_SUPPLY("ac_draw", "pda-power"),
> 
> How do you think about Mark's comments? Use dev_name() at here.

Hi Haojian,

I'm not sure I quite understand you.  I'd looked up the
structs and got their respective value that would be
returned by dev_name(), which is what I thought was
requested of me.

Thanks,
Paul.


>>  };
>>
>>  static struct regulator_init_data bq24022_init_data = {
>> diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
>> index 3d6baf9..1a18e63 100644
>> --- a/arch/arm/mach-pxa/magician.c
>> +++ b/arch/arm/mach-pxa/magician.c
>> @@ -577,14 +577,8 @@ static struct platform_device power_supply = {
>>  */
>>
>>  static struct regulator_consumer_supply bq24022_consumers[] = {
>> -       {
>> -               .dev = &gpio_vbus.dev,
>> -               .supply = "vbus_draw",
>> -       },
>> -       {
>> -               .dev = &power_supply.dev,
>> -               .supply = "ac_draw",
>> -       },
>> +       REGULATOR_SUPPLY("vbus_draw", "gpio-vbus"),
>> +       REGULATOR_SUPPLY("ac_draw", "pda-power"),
>>  };
>>
>>  static struct regulator_init_data bq24022_init_data = {
>> --
>> 1.7.9.1
>>


From T.Mehnert at eckelmann.de  Wed Mar 14 08:32:15 2012
From: T.Mehnert at eckelmann.de (Mehnert, Torsten)
Date: Wed, 14 Mar 2012 12:32:15 +0000
Subject: [PATCH] iomux-mx25.h slew rate adjusted for LCD __LD pins
Message-ID: <3F263ABB4EDE344D974E1983B56807739E86E0D1@EX-DAG01.eckelmann.group>

Hi Sascha,

i added the signed-off tag and pinned a yellow marker on my monitor.

Thanks,
Torsten

From: T. Mehnert <t.mehnert at eckelmann.de>
Date: Mon, 13 Mar 2012 12:13:51 +0100
Subject: [PATCH] iomux-mx25.h slew rate adjusted for LCD __LD pins

For some reason (sadly i don't identifying the patch right now) two LCD data lines configured PAD_CTL_SRE_SLOW (wrong slew rate) since Kernel 3.1. MX25_PAD_GPIO_E__LD16 and MX25_PAD_GPIO_F__LD17 This results in an fauly behaviour and strange color effects.

To ensure that all LCD data pins configured with the proper slew rate, this patch changes to IOMUX define of all LCD __LDxx pins to PAD_CTL_SRE_FAST.

This problem may affect other mx25 platforms like mx25pdk. Sadly i can't test it. Of course this problem shouldn't occur when you done your LCD muxing correctly in the bootloader.

Signed-off-by: Torsten Mehnert <T.Mehnert at eckelmann.de>

---
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h	2012-02-28 00:43:05.000000000 +0100
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h	2012-03-13 12:08:39.920736789 +0100
@@ -139,15 +139,15 @@
 #define MX25_PAD_NFRB__GPIO_3_31	IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D15__D15		IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D15__LD16		IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D15__LD16		IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D15__GPIO_4_5		IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D14__D14		IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D14__LD17		IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D14__LD17		IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D14__GPIO_4_6		IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D13__D13		IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D13__LD18		IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D13__LD18		IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D13__GPIO_4_7		IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D12__D12		IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
@@ -192,54 +192,54 @@
 #define MX25_PAD_D0__D0			IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_D0__GPIO_4_20		IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD0__LD0		IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD0__LD0		IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD0__CSI_D0		IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD0__GPIO_2_15		IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD1__LD1		IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD1__LD1		IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD1__CSI_D1		IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD1__GPIO_2_16		IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD2__LD2		IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD2__LD2		IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD2__GPIO_2_17		IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD3__LD3		IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD3__LD3		IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD3__GPIO_2_18		IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD4__LD4		IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD4__LD4		IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD4__GPIO_2_19		IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD5__LD5		IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD5__LD5		IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD5__GPIO_1_19		IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD6__LD6		IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD6__LD6		IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD6__GPIO_1_20		IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD7__LD7		IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD7__LD7		IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD7__GPIO_1_21		IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD8__LD8		IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD8__LD8		IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD8__FEC_TX_ERR	IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD9__LD9		IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD9__LD9		IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD9__FEC_COL		IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD10__LD10		IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD10__LD10		IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD10__FEC_RX_ER	IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD11__LD11		IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD11__LD11		IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD11__FEC_RDATA2	IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD12__LD12		IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD12__LD12		IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD12__FEC_RDATA3	IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD13__LD13		IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD13__LD13		IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD13__FEC_TDATA2	IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD14__LD14		IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD14__LD14		IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD14__FEC_TDATA3	IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD15__LD15		IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD15__LD15		IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD15__FEC_RX_CLK	IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
 
 #define MX25_PAD_HSYNC__HSYNC		IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
@@ -468,11 +468,11 @@
 #define MX25_PAD_GPIO_C__CAN2_TX	IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
 
 #define MX25_PAD_GPIO_D__GPIO_D		IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_E__LD16		IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_E__LD16		IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_GPIO_D__CAN2_RX	IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
 
 #define MX25_PAD_GPIO_E__GPIO_E		IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__LD17		IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_F__LD17		IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_GPIO_E__AUD7_TXD	IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_GPIO_F__GPIO_F		IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
---

Torsten Mehnert
K?lte- und Geb?udeleittechnik (KGL)
?
ECKELMANN AG
Berliner Stra?e 161
D - 65205 Wiesbaden
?
Phone:? +49 (0) 611 / 7103 - 370
Fax:????? +49 (0) 611 / 7103 - 133

e-Mail:?? mailto:t.mehnert at eckelmann.de
Web:???? http://www.eckelmann.de




From broonie at opensource.wolfsonmicro.com  Wed Mar 14 08:32:36 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 14 Mar 2012 12:32:36 +0000
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <4F608F4F.8020106@windriver.com>
References: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
 <1331242494-3157-1-git-send-email-paul.gortmaker@windriver.com>
 <CAN1soZzDRR4XQ34WDL48=j+Ff8t5fsCFaccqZAKOQ1OAPeDXcA@mail.gmail.com>
 <4F608F4F.8020106@windriver.com>
Message-ID: <20120314123236.GE3133@opensource.wolfsonmicro.com>

On Wed, Mar 14, 2012 at 08:30:07AM -0400, Paul Gortmaker wrote:
> On 12-03-14 04:38 AM, Haojian Zhuang wrote:

> > How do you think about Mark's comments? Use dev_name() at here.

> I'm not sure I quite understand you.  I'd looked up the
> structs and got their respective value that would be
> returned by dev_name(), which is what I thought was
> requested of me.

Yes, that's what you should do.  Calling dev_name() is only possible if
you have the struct device and removing the need for the struct device
is exactly what we're trying to avoid here.
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From broonie at opensource.wolfsonmicro.com  Wed Mar 14 08:36:35 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 14 Mar 2012 12:36:35 +0000
Subject: linux-next: manual merge of the arm-soc tree with the sound-asoc
 tree
In-Reply-To: <20120314170628.4b0b5688441624a7a080d7cd@canb.auug.org.au>
References: <20120314170628.4b0b5688441624a7a080d7cd@canb.auug.org.au>
Message-ID: <20120314123635.GG3133@opensource.wolfsonmicro.com>

On Wed, Mar 14, 2012 at 05:06:28PM +1100, Stephen Rothwell wrote:

> I fixed it up (see below) and can carry the fix as necessary.

Looks good, thanks.
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From broonie at opensource.wolfsonmicro.com  Wed Mar 14 08:38:01 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 14 Mar 2012 12:38:01 +0000
Subject: [PATCH v13] Regulator: Add Anatop regulator driver
In-Reply-To: <1331692152-9256-1-git-send-email-paul.liu@linaro.org>
References: <1331692152-9256-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120314123800.GH3133@opensource.wolfsonmicro.com>

On Wed, Mar 14, 2012 at 10:29:12AM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is an integrated regulator inside i.MX6 SoC.
> There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
> And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
> This patch adds the Anatop regulator driver.

Applied, thanks.
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From aisheng.dong at freescale.com  Wed Mar 14 08:45:23 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 14 Mar 2012 20:45:23 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120313172351.97C5E3E053B@localhost>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
Message-ID: <20120314124512.GG1180@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 01:23:51AM +0800, Grant Likely wrote:
> On Tue, 13 Mar 2012 16:47:04 +0800, Dong Aisheng <b29396 at freescale.com> wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > This patch includes basic dt support which can boot via nfs rootfs.
> > 
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > ---
> >  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
> >  arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
> >  arch/arm/boot/dts/imx28.dtsi                  |   88 +++++++++++++++++++++++++
> >  arch/arm/mach-mxs/Kconfig                     |    9 +++
> >  arch/arm/mach-mxs/Makefile                    |    1 +
> >  arch/arm/mach-mxs/imx28-dt.c                  |   67 +++++++++++++++++++
> >  6 files changed, 200 insertions(+), 0 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> > index 54bddda..9f21faf 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.txt
> > +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> > @@ -1,6 +1,10 @@
> >  Freescale i.MX Platforms Device Tree Bindings
> >  -----------------------------------------------
> >  
> > +i.MX28 Evaluation Kit
> > +Required root node properties:
> > +    - compatible = "fsl,imx28-evk", "fsl,imx28";
> > +
> >  i.MX51 Babbage Board
> >  Required root node properties:
> >      - compatible = "fsl,imx51-babbage", "fsl,imx51";
> > diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
> > new file mode 100644
> > index 0000000..9758dc4
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx28-evk.dts
> > @@ -0,0 +1,31 @@
> > +/*
> > + * Copyright 2012 Freescale Semiconductor, Inc.
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/dts-v1/;
> > +/include/ "imx28.dtsi"
> > +
> > +/ {
> > +	model = "Freescale i.MX28 Evaluation Kit";
> > +	compatible = "fsl,imx28-evk", "fsl,imx28";
> > +
> > +	memory {
> > +		device_type = "memory";
> > +		reg = <0x40000000 0x08000000>;
> > +	};
> > +
> > +	ahb at 80080000 {
> > +		fec at 800f0000 {
> > +			phy-mode = "rmii";
> > +			local-mac-address = [00 04 9F 01 7D 5B];
> 
> Generally a bad idea to put a specific mac address into the device tree.
> Better to fill it with zeros.  Otherwise all the dev boards will end up using
> the same value.
> 
Yes, this issue also exists on other platfroms like mx6q.
One way is to dynamically get mac address by reading otp register as non-dt does
like:
static int __init mx28evk_fec_get_mac(void)
{
        int i;
        u32 val;
        const u32 *ocotp = mxs_get_ocotp();

        if (!ocotp)
                return -ETIMEDOUT;

        /*
         * OCOTP only stores the last 4 octets for each mac address,
         * so hard-code Freescale OUI (00:04:9f) here.
         */
        for (i = 0; i < 2; i++) {
                val = ocotp[i];
                mx28_fec_pdata[i].mac[0] = 0x00;
                mx28_fec_pdata[i].mac[1] = 0x04;
                mx28_fec_pdata[i].mac[2] = 0x9f;
                mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
                mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
                mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
        }

        return 0;
}

But it seems this needs pass mac address to fec driver via platforom data which is
not friendly to dt.

Another way may be changing fec driver to get the fixed part of mac address(first
two bytes) from device tree and read the left dynamical part from otp which i'm not
sure is better enough.

BTW, filling with zeros seems not work since it's invalid mac address.

Regards
Dong Aisheng





From lee.jones at linaro.org  Wed Mar 14 09:04:56 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 13:04:56 +0000
Subject: [PATCH 0/10] ARM: ux500: Enable Snowball for Device Tree
Message-ID: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>

Hopefully the first of many, this patch-set starts the process
of enabling Device Tree for ST-Ericsson's low-cost development
platform, Snowball.

 arch/arm/boot/dts/db8500.dtsi      |  275 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/snowball.dts     |  139 ++++++++++++++++++
 arch/arm/configs/u8500_defconfig   |    1 +
 arch/arm/mach-ux500/Kconfig        |    6 +
 arch/arm/mach-ux500/Makefile.boot  |    1 +
 arch/arm/mach-ux500/board-mop500.c |   99 +++++++++++++-
 arch/arm/mach-ux500/cache-l2x0.c   |    7 +-
 arch/arm/mach-ux500/cpu.c          |   12 ++-
 arch/arm/mach-ux500/localtimer.c   |   18 +++-
 9 files changed, 553 insertions(+), 5 deletions(-)




From lee.jones at linaro.org  Wed Mar 14 09:04:57 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 13:04:57 +0000
Subject: [PATCH 01/10] ARM: ux500: CONFIG: Enable Device Tree support for
 future endeavours
In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331730306-11461-2-git-send-email-lee.jones@linaro.org>

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/configs/u8500_defconfig |    1 +
 arch/arm/mach-ux500/Kconfig      |    6 ++++++
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 2d7b6e7..889d73a 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -13,6 +13,7 @@ CONFIG_UX500_SOC_DB8500=y
 CONFIG_MACH_HREFV60=y
 CONFIG_MACH_SNOWBALL=y
 CONFIG_MACH_U5500=y
+CONFIG_MACH_UX500_DT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 5cfa539..afb3706 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -50,6 +50,12 @@ config MACH_U5500
 	depends on UX500_SOC_DB5500
 	help
 	  Include support for the U5500 development platform.
+
+config MACH_UX500_DT
+	bool "Generic U8500 support using device tree"
+	depends on MACH_U8500
+	select USE_OF
+
 endmenu
 
 config UX500_DEBUG_UART
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 09:04:58 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 13:04:58 +0000
Subject: [PATCH 02/10] ARM: ux500: Initial Device Tree support for Snowball
In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331730306-11461-3-git-send-email-lee.jones@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

This provides very basic Device Tree support for ST-Ericsson's
low-cost development platform, Snowball. If Device Tree for
ux500 is enabled and the correct board is configured within the
Device Tree blob, the correct *_init_machine() will be called.

This patch is based on some original work completed by:
  Niklas Hernaeus <niklas.hernaeus at linaro.org>

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
Signed-off-by: Niklas Hernaeus <niklas.hernaeus at linaro.org>
---
 arch/arm/boot/dts/snowball.dts     |   31 +++++++++++++++++++++++++++++++
 arch/arm/mach-ux500/Makefile.boot  |    1 +
 arch/arm/mach-ux500/board-mop500.c |   34 ++++++++++++++++++++++++++++++++++
 3 files changed, 66 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/snowball.dts

diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
new file mode 100644
index 0000000..ebcff9a
--- /dev/null
+++ b/arch/arm/boot/dts/snowball.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2011 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+/ {
+	model = "Calao Systems Snowball platform with device tree";
+	compatible = "calaosystems,snowball-a9500";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		reg = <0x00000000 0x20000000>;
+	};
+
+	soc-u9500 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+	};
+};
diff --git a/arch/arm/mach-ux500/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot
index ff0a4b5..dd5cd00 100644
--- a/arch/arm/mach-ux500/Makefile.boot
+++ b/arch/arm/mach-ux500/Makefile.boot
@@ -2,3 +2,4 @@
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
 
+dtb-$(CONFIG_MACH_SNOWBALL) += snowball.dtb
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 04afcdf..0fb5dfd 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -30,6 +30,9 @@
 #include <linux/gpio_keys.h>
 #include <linux/delay.h>
 
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
 #include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -738,3 +741,34 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
 	.handle_irq	= gic_handle_irq,
 	.init_machine	= snowball_init_machine,
 MACHINE_END
+
+#ifdef CONFIG_MACH_UX500_DT
+static void __init u8500_init_machine(void)
+{
+	if (of_machine_is_compatible("calaosystems,snowball-a9500"))
+		return snowball_init_machine();
+	else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
+		return hrefv60_init_machine();
+	else if (of_machine_is_compatible("st-ericsson,mop500"))
+		return mop500_init_machine();
+}
+
+static const char * u8500_dt_board_compat[] = {
+	"calaosystems,snowball-a9500",
+	"st-ericsson,hrefv60+",
+	"st-ericsson,u8500",
+	"st-ericsson,mop500",
+	NULL,
+};
+
+
+DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)")
+	.map_io		= u8500_map_io,
+	.init_irq	= ux500_init_irq,
+	/* we re-use nomadik timer here */
+	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= u8500_init_machine,
+	.dt_compat      = u8500_dt_board_compat,
+MACHINE_END
+#endif
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 09:05:00 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 13:05:00 +0000
Subject: [PATCH 04/10] ARM: ux500: split dts file for snowball into generic
 part
In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331730306-11461-5-git-send-email-lee.jones@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

db8500.dtsi can be used by all systems with a db8500 or
db9500 SoC, while snowball.dts is board specific.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/db8500.dtsi  |   21 +++++++++++++++++++++
 arch/arm/boot/dts/snowball.dts |    8 +-------
 2 files changed, 22 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/boot/dts/db8500.dtsi

diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
new file mode 100644
index 0000000..50c84b2
--- /dev/null
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2012 Linaro Ltd
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	soc-u9500 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+	};
+};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index ebcff9a..0ea9470 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -10,22 +10,16 @@
  */
 
 /dts-v1/;
+/include/ "db8500.dtsi"
 
 / {
 	model = "Calao Systems Snowball platform with device tree";
 	compatible = "calaosystems,snowball-a9500";
 
-	#address-cells = <1>;
-	#size-cells = <1>;
-
 	memory {
 		reg = <0x00000000 0x20000000>;
 	};
 
 	soc-u9500 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "simple-bus";
-		ranges;
 	};
 };
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 09:05:02 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 13:05:02 +0000
Subject: [PATCH 06/10] ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt
 Controller) in Device Tree
In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331730306-11461-7-git-send-email-lee.jones@linaro.org>

This enables the embedded GIC on all u8500 based hardware using DT.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/db8500.dtsi |   11 +++++++++++
 arch/arm/mach-ux500/cpu.c     |   12 +++++++++++-
 2 files changed, 22 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index 0521cea..cce5df8 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -16,8 +16,19 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "stericsson,db8500";
+		interrupt-parent = <&intc>;
 		ranges;
 
+		intc: interrupt-controller at a0411000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			interrupt-controller;
+			interrupt-parent;
+			reg = <0xa0411000 0x1000>,
+			      <0xa0410100 0x100>;
+		};
+
 		pmu {
 			compatible = "arm,cortex-a9-pmu";
 			interrupts = <7>;
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 055fb6e..bd7f1dd 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -16,6 +16,8 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/stat.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
@@ -29,6 +31,11 @@
 
 void __iomem *_PRCMU_BASE;
 
+static const struct of_device_id ux500_dt_irq_match[] = {
+	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{},
+};
+
 void __init ux500_init_irq(void)
 {
 	void __iomem *dist_base;
@@ -43,7 +50,10 @@ void __init ux500_init_irq(void)
 	} else
 		ux500_unknown_soc();
 
-	gic_init(0, 29, dist_base, cpu_base);
+	if (of_have_populated_dt())
+		of_irq_init(ux500_dt_irq_match);
+	else
+		gic_init(0, 29, dist_base, cpu_base);
 
 	/*
 	 * Init clocks here so that they are available for system timer
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 09:05:03 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 13:05:03 +0000
Subject: [PATCH 07/10] ARM: ux500: Provide local timer support for Device Tree
In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331730306-11461-8-git-send-email-lee.jones@linaro.org>

This enables local timer (AKA: private timer) support for
all u8500 based hardware using DT.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/db8500.dtsi    |    6 ++++++
 arch/arm/mach-ux500/localtimer.c |   18 +++++++++++++++++-
 2 files changed, 23 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index cce5df8..35d0146 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -34,6 +34,12 @@
 			interrupts = <7>;
 		};
 
+		timer at a0410600 {
+			compatible = "arm,smp-twd";
+			reg = <0xa0410600 0x20>;
+			interrupts = <1 13 0x304>;
+		};
+
 		rtc at 80154000 {
 			compatible = "stericsson,db8500-rtc";
 			reg = <0x80154000 0x1000>;
diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
index 5ba1133..295e580 100644
--- a/arch/arm/mach-ux500/localtimer.c
+++ b/arch/arm/mach-ux500/localtimer.c
@@ -14,6 +14,10 @@
 #include <linux/smp.h>
 #include <linux/clockchips.h>
 
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
 #include <asm/irq.h>
 #include <asm/smp_twd.h>
 #include <asm/localtimer.h>
@@ -23,7 +27,19 @@
  */
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
-	evt->irq = IRQ_LOCALTIMER;
+	struct device_node *np;
+
+	np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
+	if (np) {
+		if (!twd_base) {
+			twd_base = of_iomap(np, 0);
+			WARN_ON(!twd_base);
+		}
+		evt->irq = irq_of_parse_and_map(np, 0);
+	}
+	else
+		evt->irq = IRQ_LOCALTIMER;
+
 	twd_timer_setup(evt);
 	return 0;
 }
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 09:04:59 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 13:04:59 +0000
Subject: [PATCH 03/10] ARM: ux500: combine the board init functions for DT boot
In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331730306-11461-4-git-send-email-lee.jones@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

This lets us move over evertything to device tree one by one.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/board-mop500.c |   57 ++++++++++++++++++++++++++++++++----
 1 files changed, 51 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 0fb5dfd..e2932fc 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -745,12 +745,57 @@ MACHINE_END
 #ifdef CONFIG_MACH_UX500_DT
 static void __init u8500_init_machine(void)
 {
-	if (of_machine_is_compatible("calaosystems,snowball-a9500"))
-		return snowball_init_machine();
-	else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
-		return hrefv60_init_machine();
-	else if (of_machine_is_compatible("st-ericsson,mop500"))
-		return mop500_init_machine();
+	struct device *parent = NULL;
+	int i2c0_devs;
+	int i;
+
+	parent = u8500_init_devices();
+	i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+
+	for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
+		mop500_platform_devs[i]->dev.parent = parent;
+	for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
+		snowball_platform_devs[i]->dev.parent = parent;
+
+
+	if (of_machine_is_compatible("st-ericsson,mop500")) {
+		mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+		mop500_pins_init();
+
+		platform_add_devices(mop500_platform_devs,
+				ARRAY_SIZE(mop500_platform_devs));
+
+		mop500_sdi_init(parent);
+	} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
+		snowball_pins_init();
+		platform_add_devices(snowball_platform_devs,
+				ARRAY_SIZE(snowball_platform_devs));
+
+		snowball_sdi_init(parent);
+	} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
+		/*
+		 * The HREFv60 board removed a GPIO expander and routed
+		 * all these GPIO pins to the internal GPIO controller
+		 * instead.
+		 */
+		mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
+		i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
+		hrefv60_pins_init();
+		platform_add_devices(mop500_platform_devs,
+				ARRAY_SIZE(mop500_platform_devs));
+
+		hrefv60_sdi_init(parent);
+	}
+	mop500_i2c_init(parent);
+	mop500_spi_init(parent);
+	mop500_uart_init(parent);
+
+	i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+	i2c_register_board_info(2, mop500_i2c2_devices,
+				ARRAY_SIZE(mop500_i2c2_devices));
+
+	/* This board has full regulator constraints */
+	regulator_has_full_constraints();
 }
 
 static const char * u8500_dt_board_compat[] = {
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 09:05:01 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 13:05:01 +0000
Subject: [PATCH 05/10] ARM: ux500: db8500: list most devices in the snowball
 device tree
In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331730306-11461-6-git-send-email-lee.jones@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

This adds all devices that are normally present through the
u8500_init_machine function in the device tree as well, which
will duplicate the devices that are visible.

This will not do much by itself because the device from the
device tree are not matched by any device driver until they
are converted as well. The next step is to move over one
device at a time to actually be used from the device tree
instead of the hardcoded device using auxdata to pass the
correct platform_data.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/db8500.dtsi      |  228 +++++++++++++++++++++++++++++++++++-
 arch/arm/boot/dts/snowball.dts     |  102 ++++++++++++++++
 arch/arm/mach-ux500/board-mop500.c |   14 +++
 3 files changed, 343 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index 50c84b2..0521cea 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -15,7 +15,233 @@
 	soc-u9500 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "simple-bus";
+		compatible = "stericsson,db8500";
 		ranges;
+
+		pmu {
+			compatible = "arm,cortex-a9-pmu";
+			interrupts = <7>;
+		};
+
+		rtc at 80154000 {
+			compatible = "stericsson,db8500-rtc";
+			reg = <0x80154000 0x1000>;
+			interrupts = <18>;
+		};
+
+		gpio0: gpio at 8012e000 {
+			compatible = "stericsson,db8500-gpio",
+				"stmicroelectronics,nomadik-gpio";
+			reg =  <0x8012e000 0x80>;
+			interrupts = <119>;
+			supports-sleepmode;
+			gpio-controller;
+		};
+
+		gpio1: gpio at 8012e080 {
+			compatible = "stericsson,db8500-gpio",
+				"stmicroelectronics,nomadik-gpio";
+			reg =  <0x8012e080 0x80>;
+			interrupts = <120>;
+			supports-sleepmode;
+			gpio-controller;
+		};
+
+		gpio2: gpio at 8000e000 {
+			compatible = "stericsson,db8500-gpio",
+				"stmicroelectronics,nomadik-gpio";
+			reg =  <0x8000e000 0x80>;
+			interrupts = <121>;
+			supports-sleepmode;
+			gpio-controller;
+		};
+
+		gpio3: gpio at 8000e080 {
+			compatible = "stericsson,db8500-gpio",
+				"stmicroelectronics,nomadik-gpio";
+			reg =  <0x8000e080 0x80>;
+			interrupts = <122>;
+			supports-sleepmode;
+			gpio-controller;
+		};
+
+		gpio4: gpio at 8000e100 {
+			compatible = "stericsson,db8500-gpio",
+				"stmicroelectronics,nomadik-gpio";
+			reg =  <0x8000e100 0x80>;
+			interrupts = <123>;
+			supports-sleepmode;
+			gpio-controller;
+		};
+
+		gpio5: gpio at 8000e180 {
+			compatible = "stericsson,db8500-gpio",
+				"stmicroelectronics,nomadik-gpio";
+			reg =  <0x8000e180 0x80>;
+			interrupts = <124>;
+			supports-sleepmode;
+			gpio-controller;
+		};
+
+		gpio6: gpio at 8011e000 {
+			compatible = "stericsson,db8500-gpio",
+				"stmicroelectronics,nomadik-gpio";
+			reg =  <0x8011e000 0x80>;
+			interrupts = <125>;
+			supports-sleepmode;
+			gpio-controller;
+		};
+
+		gpio7: gpio at 8011e080 {
+			compatible = "stericsson,db8500-gpio",
+				"stmicroelectronics,nomadik-gpio";
+			reg =  <0x8011e080 0x80>;
+			interrupts = <126>;
+			supports-sleepmode;
+			gpio-controller;
+		};
+
+		gpio8: gpio at a03fe000 {
+			compatible = "stericsson,db8500-gpio",
+				"stmicroelectronics,nomadik-gpio";
+			reg =  <0xa03fe000 0x80>;
+			interrupts = <127>;
+			supports-sleepmode;
+			gpio-controller;
+		};
+
+		usb at a03e0000 {
+			compatible = "stericsson,db8500-musb",
+				"mentor,musb";
+			reg = <0xa03e0000 0x10000>;
+			interrupts = <23>;
+		};
+
+		dma-controller at 801C0000 {
+			compatible = "stericsson,db8500-dma40",
+					"stericsson,dma40";
+			reg = <0x801C0000 0x1000 0x40010000 0x800>;
+			interrupts = <25>;
+		};
+
+		prcmu at 80157000 {
+			compatible = "stericsson,db8500-prcmu";
+			reg = <0x80157000 0x1000>;
+			interrupts = <46 47>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			ab8500 at 5 {
+				compatible = "stericsson,ab8500";
+				reg = <5>; /* mailbox 5 is i2c */
+				interrupts = <40>;
+			};
+		};
+
+		i2c at 80004000 {
+			compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+			reg = <0x80004000 0x1000>;
+			interrupts = <21>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c at 80122000 {
+			compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+			reg = <0x80122000 0x1000>;
+			interrupts = <22>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c at 80128000 {
+			compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+			reg = <0x80128000 0x1000>;
+			interrupts = <55>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c at 80110000 {
+			compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+			reg = <0x80110000 0x1000>;
+			interrupts = <12>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c at 8012a000 {
+			compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+			reg = <0x8012a000 0x1000>;
+			interrupts = <51>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		ssp at 80002000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <80002000 0x1000>;
+			interrupts = <14>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			cs-gpios = <&gpio0 31 &gpio4 14 &gpio4 16 &gpio6 22 &gpio7 0>;
+		};
+
+		uart at 80120000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x80120000 0x1000>;
+			interrupts = <11>;
+			status = "disabled";
+		};
+		uart at 80121000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x80121000 0x1000>;
+			interrupts = <19>;
+			status = "disabled";
+		};
+		uart at 80007000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x80007000 0x1000>;
+			interrupts = <26>;
+			status = "disabled";
+		};
+
+		sdi at 80126000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80126000 0x1000>;
+			interrupts = <60>;
+			status = "disabled";
+		};
+		sdi at 80118000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80118000 0x1000>;
+			interrupts = <50>;
+			status = "disabled";
+		};
+		sdi at 80005000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80005000 0x1000>;
+			interrupts = <41>;
+			status = "disabled";
+		};
+		sdi at 80119000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80119000 0x1000>;
+			interrupts = <59>;
+			status = "disabled";
+		};
+		sdi at 80114000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80114000 0x1000>;
+			interrupts = <99>;
+			status = "disabled";
+		};
+		sdi at 80008000 {
+			compatible = "arm,pl18x", "arm,primecell";
+			reg = <0x80114000 0x1000>;
+			interrupts = <100>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 0ea9470..34bfd79 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -20,6 +20,108 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
+	gpio_keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		button at 1 {
+			debounce_interval = <50>;
+			wakeup = <1>;
+			linux,code = <2>;
+			label = "userpb";
+			gpios = <&gpio1 0>;
+		};
+		button at 2 {
+			debounce_interval = <50>;
+			wakeup = <1>;
+			linux,code = <3>;
+			label = "userpb";
+			gpios = <&gpio4 23>;
+		};
+		button at 3 {
+			debounce_interval = <50>;
+			wakeup = <1>;
+			linux,code = <4>;
+			label = "userpb";
+			gpios = <&gpio4 23>;
+		};
+		button at 4 {
+			debounce_interval = <50>;
+			wakeup = <1>;
+			linux,code = <5>;
+			label = "userpb";
+			gpios = <&gpio5 1>;
+		};
+		button at 5 {
+			debounce_interval = <50>;
+			wakeup = <1>;
+			linux,code = <6>;
+			label = "userpb";
+			gpios = <&gpio5 2>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		used-led {
+			label = "user_led";
+			gpios = <&gpio4 14>;
+		};
+	};
+
 	soc-u9500 {
+
+		external-bus at 50000000 {
+			compatible = "simple-bus";
+			reg = <0x50000000 0x10000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			ethernet at 50000000 {
+				compatible = "smsc,9111";
+				reg = <0x50000000 0x10000>;
+				interrupts = <12>;
+				interrupt-parent = <&gpio4>;
+			};
+		};
+
+		sdi at 80126000 {
+			status = "enabled";
+			cd-gpios = <&gpio6 26>;
+		};
+
+		sdi at 80114000 {
+			status = "enabled";
+		};
+
+		i2c at 80004000 {
+			tc3589x at 42 {
+				//compatible = "tc3589x";
+				reg = <0x42>;
+				interrupts = <25>;
+				interrupt-parent = <&gpio6>;
+			};
+			tps61052 at 33 {
+				//compatible = "tps61052";
+				reg = <0x33>;
+			};
+		};
+
+		i2c at 80128000 {
+			lp5521 at 0x33 {
+				// compatible = "lp5521";
+				reg = <0x33>;
+			};
+			lp5521 at 0x34 {
+				// compatible = "lp5521";
+				reg = <0x34>;
+			};
+			bh1780 at 0x29 {
+				// compatible = "rohm,bh1780gli";
+				reg = <0x33>;
+			};
+		};
 	};
 };
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index e2932fc..482b86e 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -621,6 +621,7 @@ static void __init mop500_init_machine(void)
 
 	mop500_pins_init();
 
+	/* FIXME: parent of ab8500 should be prcmu */
 	for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
 		mop500_platform_devs[i]->dev.parent = parent;
 
@@ -743,6 +744,17 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
 MACHINE_END
 
 #ifdef CONFIG_MACH_UX500_DT
+
+struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
+	{},
+};
+
+static const struct of_device_id u8500_soc_node[] = {
+	/* only create devices below soc node */
+	{ .compatible = "stericsson,db8500", },
+	{ },
+};
+
 static void __init u8500_init_machine(void)
 {
 	struct device *parent = NULL;
@@ -757,6 +769,8 @@ static void __init u8500_init_machine(void)
 	for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
 		snowball_platform_devs[i]->dev.parent = parent;
 
+	/* automatically probe child nodes of db8500 device */
+	of_platform_populate(NULL, u8500_soc_node, u8500_auxdata_lookup, parent);
 
 	if (of_machine_is_compatible("st-ericsson,mop500")) {
 		mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 09:05:04 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 13:05:04 +0000
Subject: [PATCH 08/10] ARM: ux500: Enable PL011 AMBA UART Controller for
 Device Tree
In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331730306-11461-9-git-send-email-lee.jones@linaro.org>

Enables the 3 UARTs found on a u8500 using DT.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/db8500.dtsi      |    6 +++---
 arch/arm/boot/dts/snowball.dts     |   12 ++++++++++++
 arch/arm/mach-ux500/board-mop500.c |    4 +++-
 3 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index 35d0146..9b5e06e 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -208,19 +208,19 @@
 		uart at 80120000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80120000 0x1000>;
-			interrupts = <11>;
+			interrupts = <0 11 0x4>;
 			status = "disabled";
 		};
 		uart at 80121000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80121000 0x1000>;
-			interrupts = <19>;
+			interrupts = <0 19 0x4>;
 			status = "disabled";
 		};
 		uart at 80007000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x80007000 0x1000>;
-			interrupts = <26>;
+			interrupts = <0 26 0x4>;
 			status = "disabled";
 		};
 
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 34bfd79..359c6d6 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -96,6 +96,18 @@
 			status = "enabled";
 		};
 
+		uart at 80120000 {
+			status = "okay";
+		};
+
+		uart at 80121000 {
+			status = "okay";
+		};
+
+		uart at 80007000 {
+			status = "okay";
+		};
+
 		i2c at 80004000 {
 			tc3589x at 42 {
 				//compatible = "tc3589x";
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 482b86e..ea0242a 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -746,6 +746,9 @@ MACHINE_END
 #ifdef CONFIG_MACH_UX500_DT
 
 struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
+	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
+	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
 	{},
 };
 
@@ -802,7 +805,6 @@ static void __init u8500_init_machine(void)
 	}
 	mop500_i2c_init(parent);
 	mop500_spi_init(parent);
-	mop500_uart_init(parent);
 
 	i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
 	i2c_register_board_info(2, mop500_i2c2_devices,
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 09:05:05 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 13:05:05 +0000
Subject: [PATCH 09/10] ARM: ux500: Enable PL310 Level 2 Cache Controller in
 Device Tree
In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331730306-11461-10-git-send-email-lee.jones@linaro.org>

This provides PL310 Level 2 Cache Controller Device Tree
support for all u8500 based devices.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/db8500.dtsi    |    8 ++++++++
 arch/arm/mach-ux500/cache-l2x0.c |    7 ++++++-
 2 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index 9b5e06e..6ae7f69 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -29,6 +29,14 @@
 			      <0xa0410100 0x100>;
 		};
 
+		L2: l2-cache {
+			compatible = "arm,pl310-cache";
+			reg = <0xa0412000 0x1000>;
+			interrupts = <0 13 4>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
 		pmu {
 			compatible = "arm,cortex-a9-pmu";
 			interrupts = <7>;
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index da5569d..77a75ed 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -5,6 +5,8 @@
  */
 
 #include <linux/io.h>
+#include <linux/of.h>
+
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <mach/hardware.h>
@@ -45,7 +47,10 @@ static int __init ux500_l2x0_init(void)
 	ux500_l2x0_unlock();
 
 	/* 64KB way size, 8 way associativity, force WA */
-	l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
+	if (of_have_populated_dt())
+		l2x0_of_init(0x3e060000, 0xc0000fff);
+	else
+		l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
 
 	/*
 	 * We can't disable l2 as we are in non secure mode, currently
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 09:05:06 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 13:05:06 +0000
Subject: [PATCH 10/10] ARM: ux500: Enable PL022 SSP Controller in Device Tree
In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331730306-11461-11-git-send-email-lee.jones@linaro.org>

This SSP Controller supports a number of serial communication methods.

Namely:

/**
 * enum ssp_interface - interfaces allowed for this SSP Controller
 * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
 * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
 * interface
 * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
 * interface
 * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
 * &STn8815 only)
 */

... and as such cannot be registered using of_register_spi_devices.
Instead it can be registered simply as a primecell device.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/db8500.dtsi      |    5 ++++-
 arch/arm/mach-ux500/board-mop500.c |    6 +++---
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index 6ae7f69..a9866a3 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -206,11 +206,14 @@
 		ssp at 80002000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <80002000 0x1000>;
-			interrupts = <14>;
+			interrupts = <0 14 4>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
+
+			// Add one of these for each child device
 			cs-gpios = <&gpio0 31 &gpio4 14 &gpio4 16 &gpio6 22 &gpio7 0>;
+
 		};
 
 		uart at 80120000 {
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index ea0242a..d0799d5 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -443,7 +443,7 @@ static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
 };
 #endif
 
-static struct pl022_ssp_controller ssp0_platform_data = {
+static struct pl022_ssp_controller ssp0_plat = {
 	.bus_id = 0,
 #ifdef CONFIG_STE_DMA40
 	.enable_dma = 1,
@@ -461,7 +461,7 @@ static struct pl022_ssp_controller ssp0_platform_data = {
 
 static void __init mop500_spi_init(struct device *parent)
 {
-	db8500_add_ssp0(parent, &ssp0_platform_data);
+	db8500_add_ssp0(parent, &ssp0_plat);
 }
 
 #ifdef CONFIG_STE_DMA40
@@ -749,6 +749,7 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
 	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
 	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
+	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
 	{},
 };
 
@@ -804,7 +805,6 @@ static void __init u8500_init_machine(void)
 		hrefv60_sdi_init(parent);
 	}
 	mop500_i2c_init(parent);
-	mop500_spi_init(parent);
 
 	i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
 	i2c_register_board_info(2, mop500_i2c2_devices,
-- 
1.7.5.4



From robherring2 at gmail.com  Wed Mar 14 09:05:34 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 14 Mar 2012 08:05:34 -0500
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120314062354.GA8494@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <4F5F5B3F.2000303@gmail.com>
 <20120314062354.GA8494@shlinux2.ap.freescale.net>
Message-ID: <4F60979E.3060704@gmail.com>

On 03/14/2012 01:23 AM, Dong Aisheng wrote:
> On Tue, Mar 13, 2012 at 09:35:43AM -0500, Rob Herring wrote:
>> On 03/13/2012 03:47 AM, Dong Aisheng wrote:
>>> From: Dong Aisheng <dong.aisheng at linaro.org>
>>>
>>> This patch includes basic dt support which can boot via nfs rootfs.
>>>
>>> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
>>> ---
>>>  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
>>>  arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
>>>  arch/arm/boot/dts/imx28.dtsi                  |   88 +++++++++++++++++++++++++
>>>  arch/arm/mach-mxs/Kconfig                     |    9 +++
>>>  arch/arm/mach-mxs/Makefile                    |    1 +
>>>  arch/arm/mach-mxs/imx28-dt.c                  |   67 +++++++++++++++++++
>>>  6 files changed, 200 insertions(+), 0 deletions(-)
> ....
>>> +				interrupts = <47>;
>>> +			};
>>> +		};
>>> +	};
>>> +
>>> +	ahb at 80080000 {
>>> +		compatible = "simple-bus";
>>> +		#address-cells = <1>;
>>> +		#size-cells = <1>;
>>> +		reg = <0x80080000 0x80000>;
>>> +		ranges;
>>> +
>>> +		fec at 800f0000 {
>>> +			compatible = "fsl,imx28-fec";
>>> +			reg = <0x800f0000 0x4000>;
>>
>> This too IIRC.
>>
> The size is 16KB/0x4000 in iMX28 spec. :)

Yes, but the module only uses <4KB. You waste virtual memory space by
mapping all the unused area. It's not really an issue when you have
<512MB of RAM, but does become an issue.


>>> +			interrupts = <101>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		fec at 800f4000 {
>>> +			compatible = "fsl,imx28-fec";
>>> +			reg = <0x800f4000 0x4000>;
>>> +			interrupts = <102>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +	};
>>> +};
>>> diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
>>> index c57f996..6ab66af 100644
>>> --- a/arch/arm/mach-mxs/Kconfig
>>> +++ b/arch/arm/mach-mxs/Kconfig
>>> @@ -17,6 +17,15 @@ config SOC_IMX28
>>>  
>>>  comment "MXS platforms:"
>>>  
>>> +config MACH_IMX28_DT
>>
>> Perhaps this should be more generic like MACH_MXS_DT to eventually
>> support MX23 as well?
>>
> I just did like the imx ways.
> But yes if we see the need when do imx23 dt support.
> 
>>> +	bool "Support i.MX28 platforms from device tree"
>>> +	select SOC_IMX28
>>> +	select USE_OF
>>> +	select MACH_MX28EVK
>>
>> This should not be selected here.
>>
> Like other imx soc dt board files, the imx28-dt.c may need to use some bits
> like pinmux in mx28evk.c board file.
> 
> Yes, currently i can remove it since it is using uboot pinmux setting.
> But when add other devices support which is not covered in u-boot like flexcan,
> i may need to use non-dt board's pinmux setting.
> So maybe we can keep it first and remove it when totally not dependent
> on non-dt files.

Okay either way, but my vote would be add it as needed.

>>> + * The code contained herein is licensed under the GNU General Public
>>> + * License. You may obtain a copy of the GNU General Public License
>>> + * Version 2 or later at the following locations:
>>> + *
>>> + * http://www.opensource.org/licenses/gpl-license.html
>>> + * http://www.gnu.org/copyleft/gpl.html
>>> + */
>>> +
>>> +#include <linux/init.h>
>>> +#include <linux/irqdomain.h>
>>> +#include <linux/of_irq.h>
>>> +#include <linux/of_platform.h>
>>> +#include <asm/mach/arch.h>
>>> +#include <asm/mach/time.h>
>>> +#include <mach/common.h>
>>> +#include <mach/mx28.h>
>>> +
>>> +static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
>>> +	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
>>> +	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
>>> +	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
>>
>> Why do you need the old names?
>>
> To keep align with the old clocks.
> See arch/arm/mach-mxs/clock-mx28.c:
> _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
> _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
> Is there any better way to avoid this?

Yes, you can add more clock look-ups with the DT name.

Rob

> 
>>> +	{ /* sentinel */ }
>>> +};
>>> +
>>> +static void __init imx28_init(void)
>>> +{
>>> +	of_platform_populate(NULL, of_default_bus_match_table,
>>> +			     imx28_auxdata_lookup, NULL);
>>> +}
>>> +
>>> +static const struct of_device_id icoll_of_match[] __initconst = {
>>> +	{ .compatible = "fsl,imx28-icoll", },
>>> +	{},
>>> +};
>>> +
>>> +static void __init imx28_dt_init_irq(void)
>>> +{
>>> +	irq_domain_generate_simple(icoll_of_match, MX28_ICOLL_BASE_ADDR, 0);
>>
>> Please do "proper" domain support for the interrupt controller and use
>> of_irq_init.
>>
> Ok, i will see it.
> 
> For others, will fix them all.
> Thanks for the review.
> 
> Regards
> Dong Aisheng
> 



From arnd at arndb.de  Wed Mar 14 09:07:55 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 13:07:55 +0000
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <4F60832E.6060100@st.com>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <20120312143825.GB13869@game.jcrosoft.org> <4F60832E.6060100@st.com>
Message-ID: <201203141307.55808.arnd@arndb.de>

On Wednesday 14 March 2012, Giuseppe CAVALLARO wrote:
> On 3/12/2012 3:38 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 15:05 Mon 12 Mar     , Stefan Roese wrote:
> >> This patch adds support to configure the STMMAC ethernet driver via
> >> device-tree instead of platform_data.
> >>
> >> Currently, only the properties needed on SPEAr600 are provided. All
> >> other properties should be added once needed on other platforms.
> >>
> >> Signed-off-by: Stefan Roese <sr at denx.de>
> >> Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
> >> Cc: Viresh Kumar <viresh.kumar at st.com>
> >> ---
> >>  Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
> >>  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66 +++++++++++++++++++-
> >>  2 files changed, 103 insertions(+), 1 deletion(-)
> >>  create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
> >> new file mode 100644
> >> index 0000000..386a47f
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/net/stmmac.txt
> >> @@ -0,0 +1,38 @@
> >> +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
> >> +
> >> +Required properties:
> >> +- compatible: Should be "stm,gmac"
> 
> > this IP have 2 version at least the GMAC for the second generation and mac for
> > the first generation
> 
> yes you are right. STMMAC supports two device generations I named:
> dwma10/100 and dwmac1000 (gmac).
> 
> Concerning the latter, we support several different versions of the
> synopsys GMAC cores ... from 3.30 to 3.61a.
> 
> For example, stx7108 and Stx7109 have the same GMAC core (also SPEAr600
> IIRC).
> SPEAr13xx has 3.50a
> New ST SoC Stxh415 has the 3.60a. etc.

In that case, you should definitely list the exact device versions in the
compatible string, like:

compatible = "stm,spear600-gmac", "snps,dw-gmac-3.50a", "snps,dw-gmac";

When we have other socs with the same version, that lets us add quirks
for the specific version by checking the compatible property once in the
driver.

It also sounds to me that the entire stmmac driver should live in the
drivers/net/ethernet/synopsys directory, not stmicro, but that is a
different issue.


	Arnd


From robherring2 at gmail.com  Wed Mar 14 09:10:30 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 14 Mar 2012 08:10:30 -0500
Subject: [GIT PULL] imx irq_domain migration
In-Reply-To: <20120314050837.GB21337@S2101-09.ap.freescale.net>
References: <20120216154941.GB11758@r65073-Latitude-D630>
 <4F3D41D2.5090203@gmail.com>
 <20120314050837.GB21337@S2101-09.ap.freescale.net>
Message-ID: <4F6098C6.7050503@gmail.com>

On 03/14/2012 12:08 AM, Shawn Guo wrote:
> On Thu, Feb 16, 2012 at 11:50:10AM -0600, Rob Herring wrote:
>> Shawn,
>>
>> On 02/16/2012 09:49 AM, Shawn Guo wrote:
>>> Hi Rob,
>>>
>>> Please pull imx irq_domain support below. It's based on Grant's
>>> irqdomain/next today with your generic-chip series applied on top
>>> of it.
>>
>> You're asking me to pull changes on top of a branch that I don't even
>> have as you've rebased my changes. While it would work I don't think
>> this is the right flow. Plus there is not really any reason for iMX
>> changes to go thru me.
>>
>> Either Grant needs to stabilize his branch so you and I can send him
>> pull requests or he can pull in our changes and rebase them as he
>> rebases. I already asked him to do just that with my 1 patch others are
>> dependent on.
>>
> Hi Grant,
> 
> Would you consider to take this request after you take Rob's
> generic_irq one?

You'll need rebase your branch as I did since Grant did.

Rob


From arnd at arndb.de  Wed Mar 14 09:12:51 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 13:12:51 +0000
Subject: [PATCH v3 2/5] ARM: Add a printk loglevel modifier
In-Reply-To: <1331720516-11801-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
 <1331720516-11801-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <201203141312.51547.arnd@arndb.de>

On Wednesday 14 March 2012, Uwe Kleine-K?nig wrote:
> This is a needed followup for
> 
>         ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15
> 
> otherwise no newline is printed for !CONFIG_CPU_CP15
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
> Should this be folded into the
> 
>         ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15
> 
> patch? Or should it come before it?
> 

I think this patch needs a better explanation. It looks to me that
it's simply a bug fix, because every printk that is not a continuation
of a previous printk needs a KERN_* line. In that case, it should
just get applied as a bug fix independent of the other patches.

However, if you sometimes don't have a newline after the previous
printk, this patch is actually wrong and should not get applied at
all.

	Arnd


From arnd at arndb.de  Wed Mar 14 09:15:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 13:15:01 +0000
Subject: [PATCH v3 0/5] ARM: Initial support for Cortex-M3
In-Reply-To: <20120314103352.GA20899@arm.com>
References: <20120314101928.GA29474@pengutronix.de>
 <20120314103352.GA20899@arm.com>
Message-ID: <201203141315.01840.arnd@arndb.de>

On Wednesday 14 March 2012, Catalin Marinas wrote:
> > I'd be happy if these patches made it into 3.4-rc1.
> 
> That's pretty ambitious. Most maintainers (including Russell) closed
> their trees by now. You can still aim for 3.5-rc1 and ideally have them
> in -next a few weeks before (though only once Russell is fine with the
> patches).

Right. I don't see anything wrong with the patches, but now is not
the time for them. Let's do a proper review after the merge window
and then get them in early for 3.5.

	Arnd


From peppe.cavallaro at st.com  Wed Mar 14 09:16:56 2012
From: peppe.cavallaro at st.com (Giuseppe CAVALLARO)
Date: Wed, 14 Mar 2012 14:16:56 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <201203141307.55808.arnd@arndb.de>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <20120312143825.GB13869@game.jcrosoft.org> <4F60832E.6060100@st.com>
 <201203141307.55808.arnd@arndb.de>
Message-ID: <4F609A48.6050702@st.com>

On 3/14/2012 2:07 PM, Arnd Bergmann wrote:
> On Wednesday 14 March 2012, Giuseppe CAVALLARO wrote:
>> On 3/12/2012 3:38 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> On 15:05 Mon 12 Mar     , Stefan Roese wrote:
>>>> This patch adds support to configure the STMMAC ethernet driver via
>>>> device-tree instead of platform_data.
>>>>
>>>> Currently, only the properties needed on SPEAr600 are provided. All
>>>> other properties should be added once needed on other platforms.
>>>>
>>>> Signed-off-by: Stefan Roese <sr at denx.de>
>>>> Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
>>>> Cc: Viresh Kumar <viresh.kumar at st.com>
>>>> ---
>>>>  Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
>>>>  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66 +++++++++++++++++++-
>>>>  2 files changed, 103 insertions(+), 1 deletion(-)
>>>>  create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
>>>> new file mode 100644
>>>> index 0000000..386a47f
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/net/stmmac.txt
>>>> @@ -0,0 +1,38 @@
>>>> +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
>>>> +
>>>> +Required properties:
>>>> +- compatible: Should be "stm,gmac"
>>
>>> this IP have 2 version at least the GMAC for the second generation and mac for
>>> the first generation
>>
>> yes you are right. STMMAC supports two device generations I named:
>> dwma10/100 and dwmac1000 (gmac).
>>
>> Concerning the latter, we support several different versions of the
>> synopsys GMAC cores ... from 3.30 to 3.61a.
>>
>> For example, stx7108 and Stx7109 have the same GMAC core (also SPEAr600
>> IIRC).
>> SPEAr13xx has 3.50a
>> New ST SoC Stxh415 has the 3.60a. etc.
> 
> In that case, you should definitely list the exact device versions in the
> compatible string, like:
> 
> compatible = "stm,spear600-gmac", "snps,dw-gmac-3.50a", "snps,dw-gmac";

looks good to me

> 
> When we have other socs with the same version, that lets us add quirks
> for the specific version by checking the compatible property once in the
> driver.
> 
> It also sounds to me that the entire stmmac driver should live in the
> drivers/net/ethernet/synopsys directory, not stmicro, but that is a
> different issue.
> 

I had also proposed to rename it from stmmac to synmac.

peppe

> 	Arnd
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 



From arnd at arndb.de  Wed Mar 14 09:21:46 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 13:21:46 +0000
Subject: Inconsistent kallsyms data on ARM.
In-Reply-To: <CAP=VYLoStscdVJretZ-Rkbp7V3Vsm8N0oWcjih7ruHFiDN7CiA@mail.gmail.com>
References: <CAP=VYLoStscdVJretZ-Rkbp7V3Vsm8N0oWcjih7ruHFiDN7CiA@mail.gmail.com>
Message-ID: <201203141321.47010.arnd@arndb.de>

On Tuesday 13 March 2012, Paul Gortmaker wrote:
> This bug(?)  has been seen to float from one ARM build to another since
> I started tracking the day-to-day changes in Stephen's linux-next builds.
> 
> I see it was discussed earlier:
> 
>    https://lkml.org/lkml/2011/8/2/233
>    https://lkml.org/lkml/2011/10/8/70
> 
> but no concrete cause was nailed down.  Can the linux-next build results
> help shed some light on this in any way?  Since it seems sporadic, is
> there value in embedding a diagnostic of some sort in the infrastructure
> so that when the error is detected, that it prints out more detailed info?
> 
> I can provide links to failed linux-next builds, but at the moment, all they
> really seem to have is the same repeated error message, like this one:
> 
>    http://kisskb.ellerman.id.au/kisskb/buildresult/5869367/
> 
> and I don't see that helping folks all that much....
> 

I'm sure I can reproduce it if necessary, but I need to know what to
look for to find out what the problem is.

	Arnd


From robherring2 at gmail.com  Wed Mar 14 09:26:17 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 14 Mar 2012 08:26:17 -0500
Subject: [PATCH 4/7] dt/clock: Add handling for fixed clocks and a clock
 node setup iterator
In-Reply-To: <20120314075930.GF21337@S2101-09.ap.freescale.net>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
 <1331680947-29861-5-git-send-email-robherring2@gmail.com>
 <20120314075930.GF21337@S2101-09.ap.freescale.net>
Message-ID: <4F609C79.2060307@gmail.com>

On 03/14/2012 02:59 AM, Shawn Guo wrote:
> On Tue, Mar 13, 2012 at 06:22:24PM -0500, Rob Herring wrote:
> ...
>> +/**
>> + * of_fixed_clk_setup() - Setup function for simple fixed rate clock
>> + */
>> +void __init of_fixed_clk_setup(struct device_node *node)
>> +{
>> +	struct clk *clk;
>> +	const char *clk_name = node->name;
>> +	u32 rate;
>> +
>> +	if (of_property_read_u32(node, "clock-frequency", &rate))
>> +		return;
>> +
>> +	of_property_read_string(node, "clock-output-names", &clk_name);
>> +
>> +	clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate);
>> +	if (clk)
>> +		of_clk_add_provider(node, of_fixed_clk_get, clk);
>> +}
> 
> It seems my comment[1] did not get addressed in this post.
> 
> Regards,
> Shawn
> 
> [1] http://article.gmane.org/gmane.linux.drivers.devicetree/10589

I just took Grant's commit as is.

It also only works for root fixed clocks, but the common clock allows
for non-root fixed clocks. I don't think there's much use case for that
at least as a DT clock node.

Rob


From arnd at arndb.de  Wed Mar 14 09:27:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 13:27:00 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203141136.48513.sr@denx.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203140948.44823.arnd@arndb.de> <201203141136.48513.sr@denx.de>
Message-ID: <201203141327.01038.arnd@arndb.de>

On Wednesday 14 March 2012, Stefan Roese wrote:
> On Wednesday 14 March 2012 10:48:44 Arnd Bergmann wrote:
> > > > I would suggest you convert these to DT next so you can remove the
> > > > amba_devs list. Which devices are these? If they are pl061 and
> > > > pl010/pl011, the binding should be really easy to do.
> > > 
> > > Yes. I really wanted to do that. But from a quick look at the pl011
> > > driver (drivers/tty/serial/amba-pl011.c), this driver doesn't support DT
> > > probing. I might have missed something here though. And ideas?
> > 
> > amba primecell devices don't actually need to register to a "compatible"
> > property, they are probed using the primecell ID, and the device tree
> > is just used to tell the system about memory and IRQ resources.
> 
> Ahh, I see. Let me see, if I can get this working...

I just saw that there is a patch series for pl061 that Rob Herring did at  

git://sources.calxeda.com/kernel/linux.git irqdomain-for-grant

Please have a look at that branch first.

> > Don't worry about the the gpio and uart devices if they are not in the
> > first initial version. I do think that they should be done fairly soon
> > though, before we get into most of the other devices.
> > 
> > It's ok if you put a lot of the other devices in the dts file though,
> > like the ethernet device, it gives a better overview of what is actually
> > there, even if the driver does not actually use it yet.
> 
> My initial idea was to push the devices once their DT support is accepted. 
> Otherwise the bindings are still not settled.

Right, that makes sense. However, you can add a property containing

	status = "disabled;

so that the device is visible in the source but no platform device gets
generated. That would have no consequences at run time but can be helpful
for review.

	Arnd


From b-cousson at ti.com  Wed Mar 14 09:36:57 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Wed, 14 Mar 2012 14:36:57 +0100
Subject: [GIT PULL] mfd: twl: Fix for irqdomain/next + SPARSE_IRQ + MMC card
 detect
Message-ID: <4F609EF9.7040602@ti.com>

Hi Samuel,

Here is a fix + cleanup + SPARSE_IRQ series for TWL4030 and TWL6030.

I added the patch from Peter as well.

Please note that this series does depend on the irqdomain/next series
from Grant.

It is based on your current for-next branch + Grant's series merged on top.

Regards,
Benoit


The following changes since commit 81d14f4516578ca71d7f97612cb2b9cd4db0e7dd:
  Benoit Cousson (1):
        Merge remote branch 'grant/irqdomain/next' into HEAD

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/twl_irq_gpio_mmc_fix

Benoit Cousson (8):
      mfd: twl6030-irq: Return twl6030_mmc_card_detect IRQ for board setup
      ARM: OMAP2+: board-omap4-*: Do not use anymore TWL6030_IRQ_BASE in board files
      mfd: twl-core: Remove references already defined in header file
      mfd: twl-core: Move IRQ allocation into twl[4030|6030]-irq files
      mfd: twl4030-irq: Make SIH SPARSE_IRQ capable
      mfd: twl-*: Replace pr_ macros by the dev_ equivalent and do various cleanups
      gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ support
      gpio/twl: Add DT support to gpio-twl4030 driver

Felipe Balbi (3):
      mfd: twl-core: don't depend on pdata->irq_base/end
      mfd: twl-core: remove unneeded header
      mfd: twl4030-irq: micro-optimization on IRQ handler

Peter Ujfalusi (1):
      mfd: twl-core: Detach twl6040 from the pmic mfd driver

 .../devicetree/bindings/gpio/gpio-twl4030.txt      |   23 +++
 arch/arm/mach-omap2/board-4430sdp.c                |   13 +-
 arch/arm/mach-omap2/board-omap4panda.c             |   15 +-
 drivers/gpio/gpio-twl4030.c                        |  111 +++++++++------
 drivers/mfd/twl-core.c                             |  154 +++++++++-----------
 drivers/mfd/twl-core.h                             |    4 +-
 drivers/mfd/twl4030-irq.c                          |   83 ++++++-----
 drivers/mfd/twl6030-irq.c                          |   71 ++++++----
 include/linux/i2c/twl.h                            |    2 +-
 9 files changed, 267 insertions(+), 209 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-twl4030.txt



From sr at denx.de  Wed Mar 14 09:37:42 2012
From: sr at denx.de (Stefan Roese)
Date: Wed, 14 Mar 2012 14:37:42 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <4F609A48.6050702@st.com>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <201203141307.55808.arnd@arndb.de> <4F609A48.6050702@st.com>
Message-ID: <201203141437.42673.sr@denx.de>

On Wednesday 14 March 2012 14:16:56 Giuseppe CAVALLARO wrote:
> >> Concerning the latter, we support several different versions of the
> >> synopsys GMAC cores ... from 3.30 to 3.61a.
> >> 
> >> For example, stx7108 and Stx7109 have the same GMAC core (also SPEAr600
> >> IIRC).
> >> SPEAr13xx has 3.50a
> >> New ST SoC Stxh415 has the 3.60a. etc.
> > 
> > In that case, you should definitely list the exact device versions in the
> > compatible string, like:
> > 
> > compatible = "stm,spear600-gmac", "snps,dw-gmac-3.50a", "snps,dw-gmac";
> 
> looks good to me

So whats the Synopsys version for SPEAr600? 

"snps,dw-gmac-3.50a" ???

Perhaps you should add this info for all supported SoC's into the device 
driver? Or even better into the devicetree bindings Documentation?

Thanks,
Stefan


From sr at denx.de  Wed Mar 14 09:43:57 2012
From: sr at denx.de (Stefan Roese)
Date: Wed, 14 Mar 2012 14:43:57 +0100
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203141327.01038.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203141136.48513.sr@denx.de> <201203141327.01038.arnd@arndb.de>
Message-ID: <201203141443.57221.sr@denx.de>

On Wednesday 14 March 2012 14:27:00 Arnd Bergmann wrote:
> > > amba primecell devices don't actually need to register to a
> > > "compatible" property, they are probed using the primecell ID, and the
> > > device tree is just used to tell the system about memory and IRQ
> > > resources.
> > 
> > Ahh, I see. Let me see, if I can get this working...

Okay. Finally got it working. The main problem was the clock device name 
matching. Solved it via OF_DEV_AUXDATA. New patch will follow soon...
 
> I just saw that there is a patch series for pl061 that Rob Herring did at
> 
> git://sources.calxeda.com/kernel/linux.git irqdomain-for-grant
> 
> Please have a look at that branch first.

That's for GPIO interrupt support, right? I'll postpone this GPIO interrupt 
support to a later patch. This one will "only" support the plain GPIO's.
 
> > > Don't worry about the the gpio and uart devices if they are not in the
> > > first initial version. I do think that they should be done fairly soon
> > > though, before we get into most of the other devices.
> > > 
> > > It's ok if you put a lot of the other devices in the dts file though,
> > > like the ethernet device, it gives a better overview of what is
> > > actually there, even if the driver does not actually use it yet.
> > 
> > My initial idea was to push the devices once their DT support is
> > accepted. Otherwise the bindings are still not settled.
> 
> Right, that makes sense. However, you can add a property containing
> 
> 	status = "disabled;
> 
> so that the device is visible in the source but no platform device gets
> generated. That would have no consequences at run time but can be helpful
> for review.

Okay, I'll add all of what I got locally. And enable only the ones that should 
be fine.

Thanks,
Stefan


From robherring2 at gmail.com  Wed Mar 14 09:44:44 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 14 Mar 2012 08:44:44 -0500
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203141327.01038.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203140948.44823.arnd@arndb.de> <201203141136.48513.sr@denx.de>
 <201203141327.01038.arnd@arndb.de>
Message-ID: <4F60A0CC.7000906@gmail.com>

On 03/14/2012 08:27 AM, Arnd Bergmann wrote:
> On Wednesday 14 March 2012, Stefan Roese wrote:
>> On Wednesday 14 March 2012 10:48:44 Arnd Bergmann wrote:
>>>>> I would suggest you convert these to DT next so you can remove the
>>>>> amba_devs list. Which devices are these? If they are pl061 and
>>>>> pl010/pl011, the binding should be really easy to do.
>>>>
>>>> Yes. I really wanted to do that. But from a quick look at the pl011
>>>> driver (drivers/tty/serial/amba-pl011.c), this driver doesn't support DT
>>>> probing. I might have missed something here though. And ideas?
>>>
>>> amba primecell devices don't actually need to register to a "compatible"
>>> property, they are probed using the primecell ID, and the device tree
>>> is just used to tell the system about memory and IRQ resources.
>>

They do need to have "arm,primecell" for things to work as the type of
h/w is probeable, but the location of it is not. There should also be a
compatible property for the specific module (i.e. arm,pl011), but Linux
doesn't look at it. There's support for overriding the hw id in the DT
as well which some spear platforms need IIRC.

I thought I had added documentation for some of the primecells and Dave
Martin was going to do the rest, but seems it got dropped on the
floor... Off to dig in my git tree.

>> Ahh, I see. Let me see, if I can get this working...
> 
> I just saw that there is a patch series for pl061 that Rob Herring did at  
> 
> git://sources.calxeda.com/kernel/linux.git irqdomain-for-grant
> 
> Please have a look at that branch first.
> 

This is just interrupt support. The pl061 driver already supports DT.
And so do pl011, pl03x, pl022, pl330 (memory to memory only).

Rob

>>> Don't worry about the the gpio and uart devices if they are not in the
>>> first initial version. I do think that they should be done fairly soon
>>> though, before we get into most of the other devices.
>>>
>>> It's ok if you put a lot of the other devices in the dts file though,
>>> like the ethernet device, it gives a better overview of what is actually
>>> there, even if the driver does not actually use it yet.
>>
>> My initial idea was to push the devices once their DT support is accepted. 
>> Otherwise the bindings are still not settled.
> 
> Right, that makes sense. However, you can add a property containing
> 
> 	status = "disabled;
> 
> so that the device is visible in the source but no platform device gets
> generated. That would have no consequences at run time but can be helpful
> for review.
> 
> 	Arnd



From shawn.guo at linaro.org  Wed Mar 14 09:45:39 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 14 Mar 2012 21:45:39 +0800
Subject: [PATCH 4/7] dt/clock: Add handling for fixed clocks and a clock
 node setup iterator
In-Reply-To: <4F609C79.2060307@gmail.com>
References: <1331680947-29861-1-git-send-email-robherring2@gmail.com>
 <1331680947-29861-5-git-send-email-robherring2@gmail.com>
 <20120314075930.GF21337@S2101-09.ap.freescale.net>
 <4F609C79.2060307@gmail.com>
Message-ID: <20120314134535.GH21337@S2101-09.ap.freescale.net>

On Wed, Mar 14, 2012 at 08:26:17AM -0500, Rob Herring wrote:
...
> It also only works for root fixed clocks, but the common clock allows
> for non-root fixed clocks. I don't think there's much use case for that
> at least as a DT clock node.
> 
What my example demonstrates are root fixed clocks.

-- 
Regards,
Shawn


From arnd at arndb.de  Wed Mar 14 09:51:05 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 13:51:05 +0000
Subject: [PATCH v4 00/11] ep93xx: Move SoC private bits to core
In-Reply-To: <4F5FC8AD.4070505@gmail.com>
References: <1331592502-9083-1-git-send-email-rmallon@gmail.com>
 <201203131235.53593.arnd@arndb.de> <4F5FC8AD.4070505@gmail.com>
Message-ID: <201203141351.06200.arnd@arndb.de>

On Tuesday 13 March 2012, Ryan Mallon wrote:
> > There are currently eight board files (since all the dev boards got
> > merged into one file), which seems very manageable and there should be
> > no problem adding a few more over the years to come, if necessary.
> 
> I doubt there will be many new boards added.
> 
> > At the same time, the platform seems simple enough that you could
> > also do a device tree port in rather in a fairly short time if you
> > like, which would let you obsolete all the board files and add new
> > machines just through device tree blobs.
> 
> 
> Yeah, converting to device tree is one of my goals. I need to spend some
> time reading through the device tree specification first.

Ok, great!

A number of ARM9 and XScale based platforms have started the conversion
now, and there is a lot you can learn by looking at the others. I would
recommend waiting for 3.4-rc1 before you get serious with this, because
patches are pending in various trees at the moment.

There is no strict need for you to do the conversion, because you say
that the platform is basically dead and there is not much churn to be
expected in the future, but you are definitely welcome to join in.

As the first steps (after reading Documentation/devicetree/booting-without-of.txt)
the best way forward is probably to take you favourite board file and
add a DT_MACHINE_START section so you can boot the same machine
when passing an empty devicetree rather than ATAGS. Then add the interrupt
controller (should be simple for VIC), followed by gpio (needs bindings,
see Documentation/devicetree/bindings/gpio/*.txt), i2c and spi. After
you have all that infrastructure in place, you can convert every other
device, one at a time. Some (anything without platform_data) will be
trivial, others require you to come up with a new binding document
and properties to replace the platform_data. Many people try to do
the ones from board files first because it lets them remove the board
files, and only after that look at converting the core devices, but you
can do any order you like.

	Arnd


From arnd at arndb.de  Wed Mar 14 09:58:03 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 13:58:03 +0000
Subject: [PATCH 02/10] ARM: ux500: Initial Device Tree support for Snowball
In-Reply-To: <1331730306-11461-3-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-3-git-send-email-lee.jones@linaro.org>
Message-ID: <201203141358.03541.arnd@arndb.de>

On Wednesday 14 March 2012, Lee Jones wrote:
> 
> From: Arnd Bergmann <arnd at arndb.de>
> 
> This provides very basic Device Tree support for ST-Ericsson's
> low-cost development platform, Snowball. If Device Tree for
> ux500 is enabled and the correct board is configured within the
> Device Tree blob, the correct *_init_machine() will be called.
> 
> This patch is based on some original work completed by:
>   Niklas Hernaeus <niklas.hernaeus at linaro.org>
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> Signed-off-by: Niklas Hernaeus <niklas.hernaeus at linaro.org>

As mentioned on IRC, the order of the S-o-B should be such that the
person submitting a patch comes last, so this one should be

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Niklas Hernaeus <niklas.hernaeus at linaro.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>

or maybe

Signed-off-by: Niklas Hernaeus <niklas.hernaeus at linaro.org>
Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Lee Jones <lee.jones at linaro.org>

The patch itself looks good to me, but that is not surprising,
given that I wrote it ;-).

	Arnd


From arnd at arndb.de  Wed Mar 14 09:59:45 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 13:59:45 +0000
Subject: [PATCH 05/10] ARM: ux500: db8500: list most devices in the
 snowball device tree
In-Reply-To: <1331730306-11461-6-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-6-git-send-email-lee.jones@linaro.org>
Message-ID: <201203141359.46109.arnd@arndb.de>

On Wednesday 14 March 2012, Lee Jones wrote:
> +               pmu {
> +                       compatible = "arm,cortex-a9-pmu";
> +                       interrupts = <7>;
> +               };
> +
> +               rtc at 80154000 {
> +                       compatible = "stericsson,db8500-rtc";
> +                       reg = <0x80154000 0x1000>;
> +                       interrupts = <18>;
> +               };
> +
> +               gpio0: gpio at 8012e000 {
> +                       compatible = "stericsson,db8500-gpio",
> +                               "stmicroelectronics,nomadik-gpio";
> +                       reg =  <0x8012e000 0x80>;
> +                       interrupts = <119>;
> +                       supports-sleepmode;
> +                       gpio-controller;
> +               };

Reading through it one more time, I realized that all the interrupt
numbers are incorrect here and you fix them up one by one in the
later patches. I think it would be more logical if you could just
fix correct them here and then later just add the additional properties
and enable the device.

	Arnd


From arnd at arndb.de  Wed Mar 14 10:00:22 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 14:00:22 +0000
Subject: [PATCH 06/10] ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt
 Controller) in Device Tree
In-Reply-To: <1331730306-11461-7-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-7-git-send-email-lee.jones@linaro.org>
Message-ID: <201203141400.23123.arnd@arndb.de>

On Wednesday 14 March 2012, Lee Jones wrote:
> This enables the embedded GIC on all u8500 based hardware using DT.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Very nice!

Reviewed-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Wed Mar 14 10:00:47 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 14:00:47 +0000
Subject: [PATCH 07/10] ARM: ux500: Provide local timer support for Device
 Tree
In-Reply-To: <1331730306-11461-8-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-8-git-send-email-lee.jones@linaro.org>
Message-ID: <201203141400.47418.arnd@arndb.de>

On Wednesday 14 March 2012, Lee Jones wrote:
> 
> This enables local timer (AKA: private timer) support for
> all u8500 based hardware using DT.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Reviewed-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Wed Mar 14 10:01:15 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 14:01:15 +0000
Subject: [PATCH 08/10] ARM: ux500: Enable PL011 AMBA UART Controller for
 Device Tree
In-Reply-To: <1331730306-11461-9-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-9-git-send-email-lee.jones@linaro.org>
Message-ID: <201203141401.16122.arnd@arndb.de>

On Wednesday 14 March 2012, Lee Jones wrote:
> Enables the 3 UARTs found on a u8500 using DT.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Reviewed-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Wed Mar 14 10:01:33 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 14:01:33 +0000
Subject: [PATCH 09/10] ARM: ux500: Enable PL310 Level 2 Cache Controller
 in Device Tree
In-Reply-To: <1331730306-11461-10-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-10-git-send-email-lee.jones@linaro.org>
Message-ID: <201203141401.33425.arnd@arndb.de>

On Wednesday 14 March 2012, Lee Jones wrote:
> This provides PL310 Level 2 Cache Controller Device Tree
> support for all u8500 based devices.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Reviewed-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Wed Mar 14 10:05:49 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 14:05:49 +0000
Subject: [PATCH 10/10] ARM: ux500: Enable PL022 SSP Controller in Device
 Tree
In-Reply-To: <1331730306-11461-11-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-11-git-send-email-lee.jones@linaro.org>
Message-ID: <201203141405.50005.arnd@arndb.de>

On Wednesday 14 March 2012, Lee Jones wrote:
> This SSP Controller supports a number of serial communication methods.
> 
> Namely:
> 
> /**
>  * enum ssp_interface - interfaces allowed for this SSP Controller
>  * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
>  * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
>  * interface
>  * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
>  * interface
>  * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
>  * &STn8815 only)
>  */
> 
> ... and as such cannot be registered using of_register_spi_devices.
> Instead it can be registered simply as a primecell device.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Looks good to me, but this one needs review from Grant as the maintainer
for both device tree and SPI.

For this to be functional, I think you also need a way for the SPI
controller to find the child devices from the device tree, but I
don't see how ux500 currently does it, or how it should be done.

Acked-by: Arnd Bergmann <arnd at arndb.de>

> ---
>  arch/arm/boot/dts/db8500.dtsi      |    5 ++++-
>  arch/arm/mach-ux500/board-mop500.c |    6 +++---
>  2 files changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
> index 6ae7f69..a9866a3 100644
> --- a/arch/arm/boot/dts/db8500.dtsi
> +++ b/arch/arm/boot/dts/db8500.dtsi
> @@ -206,11 +206,14 @@
>  		ssp at 80002000 {
>  			compatible = "arm,pl022", "arm,primecell";
>  			reg = <80002000 0x1000>;
> -			interrupts = <14>;
> +			interrupts = <0 14 4>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
>  			status = "disabled";
> +
> +			// Add one of these for each child device
>  			cs-gpios = <&gpio0 31 &gpio4 14 &gpio4 16 &gpio6 22 &gpio7 0>;
> +
>  		};
>  
>  		uart at 80120000 {
> diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
> index ea0242a..d0799d5 100644
> --- a/arch/arm/mach-ux500/board-mop500.c
> +++ b/arch/arm/mach-ux500/board-mop500.c
> @@ -443,7 +443,7 @@ static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
>  };
>  #endif
>  
> -static struct pl022_ssp_controller ssp0_platform_data = {
> +static struct pl022_ssp_controller ssp0_plat = {
>  	.bus_id = 0,
>  #ifdef CONFIG_STE_DMA40
>  	.enable_dma = 1,
> @@ -461,7 +461,7 @@ static struct pl022_ssp_controller ssp0_platform_data = {
>  
>  static void __init mop500_spi_init(struct device *parent)
>  {
> -	db8500_add_ssp0(parent, &ssp0_platform_data);
> +	db8500_add_ssp0(parent, &ssp0_plat);
>  }
>  
>  #ifdef CONFIG_STE_DMA40
> @@ -749,6 +749,7 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
>  	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
>  	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
>  	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
> +	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
>  	{},
>  };
>  
> @@ -804,7 +805,6 @@ static void __init u8500_init_machine(void)
>  		hrefv60_sdi_init(parent);
>  	}
>  	mop500_i2c_init(parent);
> -	mop500_spi_init(parent);
>  
>  	i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
>  	i2c_register_board_info(2, mop500_i2c2_devices,
> -- 
> 1.7.5.4
> 
> 



From arnd at arndb.de  Wed Mar 14 10:09:50 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 14:09:50 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203141443.57221.sr@denx.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203141327.01038.arnd@arndb.de> <201203141443.57221.sr@denx.de>
Message-ID: <201203141409.51034.arnd@arndb.de>

On Wednesday 14 March 2012, Stefan Roese wrote:
> > I just saw that there is a patch series for pl061 that Rob Herring did at
> > 
> > git://sources.calxeda.com/kernel/linux.git irqdomain-for-grant
> > 
> > Please have a look at that branch first.
> 
> That's for GPIO interrupt support, right? I'll postpone this GPIO interrupt 
> support to a later patch. This one will "only" support the plain GPIO's.
>  

Could be. I haven't actually looked at the series myself, just saw the
email topic earlier today and thought of you.

	Arnd


From s.hauer at pengutronix.de  Wed Mar 14 10:16:43 2012
From: s.hauer at pengutronix.de (s.hauer at pengutronix.de)
Date: Wed, 14 Mar 2012 15:16:43 +0100
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120314124512.GG1180@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
Message-ID: <20120314141643.GP3852@pengutronix.de>

On Wed, Mar 14, 2012 at 08:45:23PM +0800, Dong Aisheng wrote:
> On Wed, Mar 14, 2012 at 01:23:51AM +0800, Grant Likely wrote:
> > On Tue, 13 Mar 2012 16:47:04 +0800, Dong Aisheng <b29396 at freescale.com> wrote:
> > > From: Dong Aisheng <dong.aisheng at linaro.org>
> > > 
> > > This patch includes basic dt support which can boot via nfs rootfs.
> > > 
> > > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > > ---
> > >  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
> > >  arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
> > >  arch/arm/boot/dts/imx28.dtsi                  |   88 +++++++++++++++++++++++++
> > >  arch/arm/mach-mxs/Kconfig                     |    9 +++
> > >  arch/arm/mach-mxs/Makefile                    |    1 +
> > >  arch/arm/mach-mxs/imx28-dt.c                  |   67 +++++++++++++++++++
> > >  6 files changed, 200 insertions(+), 0 deletions(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> > > index 54bddda..9f21faf 100644
> > > --- a/Documentation/devicetree/bindings/arm/fsl.txt
> > > +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> > > @@ -1,6 +1,10 @@
> > >  Freescale i.MX Platforms Device Tree Bindings
> > >  -----------------------------------------------
> > >  
> > > +i.MX28 Evaluation Kit
> > > +Required root node properties:
> > > +    - compatible = "fsl,imx28-evk", "fsl,imx28";
> > > +
> > >  i.MX51 Babbage Board
> > >  Required root node properties:
> > >      - compatible = "fsl,imx51-babbage", "fsl,imx51";
> > > diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
> > > new file mode 100644
> > > index 0000000..9758dc4
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/imx28-evk.dts
> > > @@ -0,0 +1,31 @@
> > > +/*
> > > + * Copyright 2012 Freescale Semiconductor, Inc.
> > > + *
> > > + * The code contained herein is licensed under the GNU General Public
> > > + * License. You may obtain a copy of the GNU General Public License
> > > + * Version 2 or later at the following locations:
> > > + *
> > > + * http://www.opensource.org/licenses/gpl-license.html
> > > + * http://www.gnu.org/copyleft/gpl.html
> > > + */
> > > +
> > > +/dts-v1/;
> > > +/include/ "imx28.dtsi"
> > > +
> > > +/ {
> > > +	model = "Freescale i.MX28 Evaluation Kit";
> > > +	compatible = "fsl,imx28-evk", "fsl,imx28";
> > > +
> > > +	memory {
> > > +		device_type = "memory";
> > > +		reg = <0x40000000 0x08000000>;
> > > +	};
> > > +
> > > +	ahb at 80080000 {
> > > +		fec at 800f0000 {
> > > +			phy-mode = "rmii";
> > > +			local-mac-address = [00 04 9F 01 7D 5B];
> > 
> > Generally a bad idea to put a specific mac address into the device tree.
> > Better to fill it with zeros.  Otherwise all the dev boards will end up using
> > the same value.
> > 
> Yes, this issue also exists on other platfroms like mx6q.
> One way is to dynamically get mac address by reading otp register as non-dt does
> like:
> static int __init mx28evk_fec_get_mac(void)
> {
>         int i;
>         u32 val;
>         const u32 *ocotp = mxs_get_ocotp();
> 
>         if (!ocotp)
>                 return -ETIMEDOUT;
> 
>         /*
>          * OCOTP only stores the last 4 octets for each mac address,
>          * so hard-code Freescale OUI (00:04:9f) here.
>          */
>         for (i = 0; i < 2; i++) {
>                 val = ocotp[i];
>                 mx28_fec_pdata[i].mac[0] = 0x00;
>                 mx28_fec_pdata[i].mac[1] = 0x04;
>                 mx28_fec_pdata[i].mac[2] = 0x9f;
>                 mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
>                 mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
>                 mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
>         }
> 
>         return 0;
> }
> 
> But it seems this needs pass mac address to fec driver via platforom data which is
> not friendly to dt.
> 
> Another way may be changing fec driver to get the fixed part of mac address(first
> two bytes) from device tree and read the left dynamical part from otp which i'm not
> sure is better enough.
> 
> BTW, filling with zeros seems not work since it's invalid mac address.

Yes, that's the idea of using this value...

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From dhowells at redhat.com  Wed Mar 14 10:18:08 2012
From: dhowells at redhat.com (David Howells)
Date: Wed, 14 Mar 2012 14:18:08 +0000
Subject: [PATCH] ARM: Fix missing linux/types.h #inclusion in
 asm/hardware/iop3xx.h
Message-ID: <20120314141808.2354.62573.stgit@warthog.procyon.org.uk>

arch/arm/include/asm/hardware/iop3xx.h needs to include linux/types.h to avoid
the following errors:

In file included from arch/arm/plat-iop/restart.c:10:0:
/data/fs/linux-2.6-fscache/arch/arm/include/asm/hardware/iop3xx.h:239:1: error: unknown type name 'u32'
/data/fs/linux-2.6-fscache/arch/arm/include/asm/hardware/iop3xx.h: In function 'read_tmr0':
/data/fs/linux-2.6-fscache/arch/arm/include/asm/hardware/iop3xx.h:241:2: error: unknown type name 'u32'
/data/fs/linux-2.6-fscache/arch/arm/include/asm/hardware/iop3xx.h: At top level:
/data/fs/linux-2.6-fscache/arch/arm/include/asm/hardware/iop3xx.h:246:31: error: unknown type name 'u32'
...

Signed-off-by: David Howells <dhowells at redhat.com>
---

 arch/arm/include/asm/hardware/iop3xx.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index 077c323..2ff2c75 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -231,6 +231,9 @@ extern int iop3xx_get_init_atu(void);
 
 
 #ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
 void iop3xx_map_io(void);
 void iop_init_cp6_handler(void);
 void iop_init_time(unsigned long tickrate);



From lee.jones at linaro.org  Wed Mar 14 10:19:58 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 14:19:58 +0000
Subject: [PATCH 0/5] MMC: mmci: Provide bindings for Device Tree
Message-ID: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>

This patch-set splits out ux500 and ARM specific variants from mmci
core code, applies generic bindings for use by all variants, then 
enables the ux500 variant for use with Device Tree.

 Documentation/devicetree/bindings/mmc/mmci.txt |   27 +++
 arch/arm/boot/dts/db8500.dtsi                  |    6 +-
 arch/arm/boot/dts/snowball.dts                 |   30 +++-
 arch/arm/mach-ux500/board-mop500.c             |    3 +-
 drivers/mmc/host/Makefile                      |    2 +-
 drivers/mmc/host/mmci-arm.c                    |   65 ++++++
 drivers/mmc/host/mmci-ux500.c                  |  260 ++++++++++++++++++++++++
 drivers/mmc/host/mmci.c                        |  194 +++++-------------
 drivers/mmc/host/mmci.h                        |   37 ++++
 9 files changed, 473 insertions(+), 151 deletions(-)



From lee.jones at linaro.org  Wed Mar 14 10:19:59 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 14:19:59 +0000
Subject: [PATCH 1/5] MMC: mmci: Seperate ux500 variants from generic code
In-Reply-To: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331734803-17954-2-git-send-email-lee.jones@linaro.org>

This is a step in the right direction for future Device
Tree support. It will allow variant specific attributes
to be collected from a Device Tree without overloading
the MMCI core. It will also provide additional future
variants a cleaner way to add support.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mmc/host/Makefile     |    2 +-
 drivers/mmc/host/mmci-ux500.c |   93 +++++++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/mmci.c       |   90 ++++------------------------------------
 drivers/mmc/host/mmci.h       |   37 ++++++++++++++++
 4 files changed, 139 insertions(+), 83 deletions(-)
 create mode 100644 drivers/mmc/host/mmci-ux500.c

diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 745f8fc..58e2bdc 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -2,7 +2,7 @@
 # Makefile for MMC/SD host controller drivers
 #
 
-obj-$(CONFIG_MMC_ARMMMCI)	+= mmci.o
+obj-$(CONFIG_MMC_ARMMMCI)	+= mmci.o mmci-ux500.o
 obj-$(CONFIG_MMC_PXA)		+= pxamci.o
 obj-$(CONFIG_MMC_IMX)		+= imxmmc.o
 obj-$(CONFIG_MMC_MXC)		+= mxcmmc.o
diff --git a/drivers/mmc/host/mmci-ux500.c b/drivers/mmc/host/mmci-ux500.c
new file mode 100644
index 0000000..82e60f9
--- /dev/null
+++ b/drivers/mmc/host/mmci-ux500.c
@@ -0,0 +1,93 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+/* MMCIPOWER bits */
+#define MCI_DATA2DIREN		(1 << 2)
+#define MCI_CMDDIREN		(1 << 3)
+#define MCI_DATA0DIREN		(1 << 4)
+#define MCI_DATA31DIREN	(1 << 5)
+#define MCI_FBCLKEN		(1 << 7)
+
+static struct variant_data variant_u300 = {
+	.fifosize		= 16 * 4,
+	.fifohalfsize		= 8 * 4,
+	.clkreg_enable		= MCI_ST_U300_HWFCEN,
+	.datalength_bits	= 16,
+	.sdio			= true,
+};
+
+static struct variant_data variant_ux500 = {
+	.fifosize		= 30 * 4,
+	.fifohalfsize		= 8 * 4,
+	.clkreg			= MCI_CLK_ENABLE,
+	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
+	.datalength_bits	= 24,
+	.sdio			= true,
+	.st_clkdiv		= true,
+};
+
+static struct variant_data variant_ux500v2 = {
+	.fifosize		= 30 * 4,
+	.fifohalfsize		= 8 * 4,
+	.clkreg			= MCI_CLK_ENABLE,
+	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
+	.datalength_bits	= 24,
+	.sdio			= true,
+	.st_clkdiv		= true,
+	.blksz_datactrl16	= true,
+};
+
+static struct amba_id mmci_ux500_ids[] = {
+	/* ST Micro variants */
+	{
+		.id     = 0x00180180,
+		.mask   = 0x00ffffff,
+		.data	= &variant_u300,
+	},
+	{
+		.id     = 0x00280180,
+		.mask   = 0x00ffffff,
+		.data	= &variant_u300,
+	},
+	{
+		.id     = 0x00480180,
+		.mask   = 0xf0ffffff,
+		.data	= &variant_ux500,
+	},
+	{
+		.id     = 0x10480180,
+		.mask   = 0xf0ffffff,
+		.data	= &variant_ux500v2,
+	},
+	{ 0, 0 },
+};
+
+MODULE_DEVICE_TABLE(amba, mmci_ux500_ids);
+
+static struct amba_driver mmci_ux500_driver = {
+	.drv		= {
+		.name	= DRIVER_NAME,
+	},
+	.probe		= mmci_probe,
+	.remove		= __devexit_p(mmci_remove),
+	.suspend	= mmci_suspend,
+	.resume		= mmci_resume,
+	.id_table	= mmci_ux500_ids,
+};
+
+static int __init mmci_ux500_init(void)
+{
+	return amba_driver_register(&mmci_ux500_driver);
+}
+
+static void __exit mmci_ux500_exit(void)
+{
+	amba_driver_unregister(&mmci_ux500_driver);
+}
+
+module_init(mmci_ux500_init);
+module_exit(mmci_ux500_exit);
+module_param(fmax, uint, 0444);
+
+MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 304f2f9..ff44586 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -37,34 +37,6 @@
 
 #include "mmci.h"
 
-#define DRIVER_NAME "mmci-pl18x"
-
-static unsigned int fmax = 515633;
-
-/**
- * struct variant_data - MMCI variant-specific quirks
- * @clkreg: default value for MCICLOCK register
- * @clkreg_enable: enable value for MMCICLOCK register
- * @datalength_bits: number of bits in the MMCIDATALENGTH register
- * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
- *	      is asserted (likewise for RX)
- * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
- *		  is asserted (likewise for RX)
- * @sdio: variant supports SDIO
- * @st_clkdiv: true if using a ST-specific clock divider algorithm
- * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
- */
-struct variant_data {
-	unsigned int		clkreg;
-	unsigned int		clkreg_enable;
-	unsigned int		datalength_bits;
-	unsigned int		fifosize;
-	unsigned int		fifohalfsize;
-	bool			sdio;
-	bool			st_clkdiv;
-	bool			blksz_datactrl16;
-};
-
 static struct variant_data variant_arm = {
 	.fifosize		= 16 * 4,
 	.fifohalfsize		= 8 * 4,
@@ -77,35 +49,6 @@ static struct variant_data variant_arm_extended_fifo = {
 	.datalength_bits	= 16,
 };
 
-static struct variant_data variant_u300 = {
-	.fifosize		= 16 * 4,
-	.fifohalfsize		= 8 * 4,
-	.clkreg_enable		= MCI_ST_U300_HWFCEN,
-	.datalength_bits	= 16,
-	.sdio			= true,
-};
-
-static struct variant_data variant_ux500 = {
-	.fifosize		= 30 * 4,
-	.fifohalfsize		= 8 * 4,
-	.clkreg			= MCI_CLK_ENABLE,
-	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
-	.datalength_bits	= 24,
-	.sdio			= true,
-	.st_clkdiv		= true,
-};
-
-static struct variant_data variant_ux500v2 = {
-	.fifosize		= 30 * 4,
-	.fifohalfsize		= 8 * 4,
-	.clkreg			= MCI_CLK_ENABLE,
-	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
-	.datalength_bits	= 24,
-	.sdio			= true,
-	.st_clkdiv		= true,
-	.blksz_datactrl16	= true,
-};
-
 /*
  * This must be called with host->lock held
  */
@@ -1125,7 +1068,7 @@ static const struct mmc_host_ops mmci_ops = {
 	.get_cd		= mmci_get_cd,
 };
 
-static int __devinit mmci_probe(struct amba_device *dev,
+extern int __devinit mmci_probe(struct amba_device *dev,
 	const struct amba_id *id)
 {
 	struct mmci_platform_data *plat = dev->dev.platform_data;
@@ -1376,8 +1319,9 @@ static int __devinit mmci_probe(struct amba_device *dev,
  out:
 	return ret;
 }
+EXPORT_SYMBOL_GPL(mmci_probe);
 
-static int __devexit mmci_remove(struct amba_device *dev)
+extern int __devexit mmci_remove(struct amba_device *dev)
 {
 	struct mmc_host *mmc = amba_get_drvdata(dev);
 
@@ -1428,9 +1372,10 @@ static int __devexit mmci_remove(struct amba_device *dev)
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(mmci_remove);
 
 #ifdef CONFIG_PM
-static int mmci_suspend(struct amba_device *dev, pm_message_t state)
+extern int mmci_suspend(struct amba_device *dev, pm_message_t state)
 {
 	struct mmc_host *mmc = amba_get_drvdata(dev);
 	int ret = 0;
@@ -1445,8 +1390,9 @@ static int mmci_suspend(struct amba_device *dev, pm_message_t state)
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(mmci_suspend);
 
-static int mmci_resume(struct amba_device *dev)
+extern int mmci_resume(struct amba_device *dev)
 {
 	struct mmc_host *mmc = amba_get_drvdata(dev);
 	int ret = 0;
@@ -1461,6 +1407,7 @@ static int mmci_resume(struct amba_device *dev)
 
 	return ret;
 }
+EXPORT_SYMBOL_GPL(mmci_resume);
 #else
 #define mmci_suspend	NULL
 #define mmci_resume	NULL
@@ -1482,27 +1429,6 @@ static struct amba_id mmci_ids[] = {
 		.mask	= 0x000fffff,
 		.data	= &variant_arm,
 	},
-	/* ST Micro variants */
-	{
-		.id     = 0x00180180,
-		.mask   = 0x00ffffff,
-		.data	= &variant_u300,
-	},
-	{
-		.id     = 0x00280180,
-		.mask   = 0x00ffffff,
-		.data	= &variant_u300,
-	},
-	{
-		.id     = 0x00480180,
-		.mask   = 0xf0ffffff,
-		.data	= &variant_ux500,
-	},
-	{
-		.id     = 0x10480180,
-		.mask   = 0xf0ffffff,
-		.data	= &variant_ux500v2,
-	},
 	{ 0, 0 },
 };
 
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 79e4143..4ede20d 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -7,6 +7,12 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/amba/mmci.h>
+#include <linux/scatterlist.h>
+#include <linux/amba/bus.h>
+
+#define DRIVER_NAME "mmci-pl18x"
+
 #define MMCIPOWER		0x000
 #define MCI_PWR_OFF		0x00
 #define MCI_PWR_UP		0x02
@@ -162,6 +168,8 @@
 
 #define NR_SG		16
 
+static unsigned int fmax = 515633;
+
 struct clk;
 struct variant_data;
 struct dma_chan;
@@ -218,3 +226,32 @@ struct mmci_host {
 #endif
 };
 
+/**
+ * struct variant_data - MMCI variant-specific quirks
+ * @clkreg: default value for MCICLOCK register
+ * @clkreg_enable: enable value for MMCICLOCK register
+ * @datalength_bits: number of bits in the MMCIDATALENGTH register
+ * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
+ *	      is asserted (likewise for RX)
+ * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
+ *		  is asserted (likewise for RX)
+ * @sdio: variant supports SDIO
+ * @st_clkdiv: true if using a ST-specific clock divider algorithm
+ * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
+ */
+struct variant_data {
+	unsigned int		clkreg;
+	unsigned int		clkreg_enable;
+	unsigned int		datalength_bits;
+	unsigned int		fifosize;
+	unsigned int		fifohalfsize;
+	bool			sdio;
+	bool			st_clkdiv;
+	bool			blksz_datactrl16;
+};
+
+extern int __devinit mmci_probe(struct amba_device *dev,
+				const struct amba_id *id);
+extern int __devexit mmci_remove(struct amba_device *dev);
+extern int mmci_suspend(struct amba_device *dev, pm_message_t state);
+extern int mmci_resume(struct amba_device *dev);
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 10:20:00 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 14:20:00 +0000
Subject: [PATCH 2/5] MMC: mmci: Seperate ARM variants from generic code
In-Reply-To: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331734803-17954-3-git-send-email-lee.jones@linaro.org>

This is a step in the right direction for future Device
Tree support. It will allow variant specific attributes
to be collected from a Device Tree without overloading
the MMCI core. It will also provide additional future
variants a cleaner way to add support.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mmc/host/Makefile   |    2 +-
 drivers/mmc/host/mmci-arm.c |   65 +++++++++++++++++++++++++++++++++++++++++++
 drivers/mmc/host/mmci.c     |   61 ----------------------------------------
 3 files changed, 66 insertions(+), 62 deletions(-)
 create mode 100644 drivers/mmc/host/mmci-arm.c

diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 58e2bdc..0981787 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -2,7 +2,7 @@
 # Makefile for MMC/SD host controller drivers
 #
 
-obj-$(CONFIG_MMC_ARMMMCI)	+= mmci.o mmci-ux500.o
+obj-$(CONFIG_MMC_ARMMMCI)	+= mmci.o mmci-ux500.o mmci-arm.o
 obj-$(CONFIG_MMC_PXA)		+= pxamci.o
 obj-$(CONFIG_MMC_IMX)		+= imxmmc.o
 obj-$(CONFIG_MMC_MXC)		+= mxcmmc.o
diff --git a/drivers/mmc/host/mmci-arm.c b/drivers/mmc/host/mmci-arm.c
new file mode 100644
index 0000000..be78060
--- /dev/null
+++ b/drivers/mmc/host/mmci-arm.c
@@ -0,0 +1,65 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "mmci.h"
+
+static struct variant_data variant_arm = {
+	.fifosize		= 16 * 4,
+	.fifohalfsize		= 8 * 4,
+	.datalength_bits	= 16,
+};
+
+static struct variant_data variant_arm_extended_fifo = {
+	.fifosize		= 128 * 4,
+	.fifohalfsize		= 64 * 4,
+	.datalength_bits	= 16,
+};
+
+static struct amba_id mmci_arm_ids[] = {
+	{
+		.id	= 0x00041180,
+		.mask	= 0xff0fffff,
+		.data	= &variant_arm,
+	},
+	{
+		.id	= 0x01041180,
+		.mask	= 0xff0fffff,
+		.data	= &variant_arm_extended_fifo,
+	},
+	{
+		.id	= 0x00041181,
+		.mask	= 0x000fffff,
+		.data	= &variant_arm,
+	},
+	{ 0, 0 },
+};
+
+MODULE_DEVICE_TABLE(amba, mmci_arm_ids);
+
+static struct amba_driver mmci_arm_driver = {
+	.drv		= {
+		.name	= DRIVER_NAME,
+	},
+	.probe		= mmci_probe,
+	.remove		= __devexit_p(mmci_remove),
+	.suspend	= mmci_suspend,
+	.resume		= mmci_resume,
+	.id_table	= mmci_arm_ids,
+};
+
+static int __init mmci_arm_init(void)
+{
+	return amba_driver_register(&mmci_arm_driver);
+}
+
+static void __exit mmci_arm_exit(void)
+{
+	amba_driver_unregister(&mmci_arm_driver);
+}
+
+module_init(mmci_arm_init);
+module_exit(mmci_arm_exit);
+module_param(fmax, uint, 0444);
+
+MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index ff44586..23b41a5 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -37,18 +37,6 @@
 
 #include "mmci.h"
 
-static struct variant_data variant_arm = {
-	.fifosize		= 16 * 4,
-	.fifohalfsize		= 8 * 4,
-	.datalength_bits	= 16,
-};
-
-static struct variant_data variant_arm_extended_fifo = {
-	.fifosize		= 128 * 4,
-	.fifohalfsize		= 64 * 4,
-	.datalength_bits	= 16,
-};
-
 /*
  * This must be called with host->lock held
  */
@@ -1412,52 +1400,3 @@ EXPORT_SYMBOL_GPL(mmci_resume);
 #define mmci_suspend	NULL
 #define mmci_resume	NULL
 #endif
-
-static struct amba_id mmci_ids[] = {
-	{
-		.id	= 0x00041180,
-		.mask	= 0xff0fffff,
-		.data	= &variant_arm,
-	},
-	{
-		.id	= 0x01041180,
-		.mask	= 0xff0fffff,
-		.data	= &variant_arm_extended_fifo,
-	},
-	{
-		.id	= 0x00041181,
-		.mask	= 0x000fffff,
-		.data	= &variant_arm,
-	},
-	{ 0, 0 },
-};
-
-MODULE_DEVICE_TABLE(amba, mmci_ids);
-
-static struct amba_driver mmci_driver = {
-	.drv		= {
-		.name	= DRIVER_NAME,
-	},
-	.probe		= mmci_probe,
-	.remove		= __devexit_p(mmci_remove),
-	.suspend	= mmci_suspend,
-	.resume		= mmci_resume,
-	.id_table	= mmci_ids,
-};
-
-static int __init mmci_init(void)
-{
-	return amba_driver_register(&mmci_driver);
-}
-
-static void __exit mmci_exit(void)
-{
-	amba_driver_unregister(&mmci_driver);
-}
-
-module_init(mmci_init);
-module_exit(mmci_exit);
-module_param(fmax, uint, 0444);
-
-MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
-MODULE_LICENSE("GPL");
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 10:20:01 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 14:20:01 +0000
Subject: [PATCH 3/5] MMC: mmci: Add generic Device Tree bindings to mmci core
 code
In-Reply-To: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331734803-17954-4-git-send-email-lee.jones@linaro.org>

This adds the necessary bindings for collection of shared
attributes used in the mmci driver.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/mmc/host/mmci.c |   43 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 43 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 23b41a5..9132ca8 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -30,6 +30,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/amba/mmci.h>
 #include <linux/pm_runtime.h>
+#include <linux/of_gpio.h>
 
 #include <asm/div64.h>
 #include <asm/io.h>
@@ -1056,11 +1057,47 @@ static const struct mmc_host_ops mmci_ops = {
 	.get_cd		= mmci_get_cd,
 };
 
+#ifdef CONFIG_OF
+static void mmci_dt_populate_generic_pdata(struct device_node *np,
+					struct mmci_platform_data *pdata)
+{
+	const void *prop;
+	int len;
+
+	of_property_read_u32(np, "wp-gpios", &pdata->gpio_wp);
+	if (!pdata->gpio_wp)
+		pdata->gpio_wp = -1;
+
+	of_property_read_u32(np, "cd-gpios", &pdata->gpio_cd);
+	if (!pdata->gpio_cd)
+		pdata->gpio_cd = -1;
+
+	if (of_get_property(np, "cd-invert", NULL))
+		pdata->cd_invert = true;
+	else
+		pdata->cd_invert = false;
+
+	of_property_read_u32(np, "clock_frequency", &pdata->f_max);
+	if (!pdata->f_max)
+		pr_warning("%s has no 'clock_frequency' property\n", np->full_name);
+
+	if (of_get_property(np, "mmc_cap_4_bit_data", NULL))
+		pdata->capabilities |= MMC_CAP_4_BIT_DATA;
+	if (of_get_property(np, "mmc_cap_8_bit_data", NULL))
+		pdata->capabilities |= MMC_CAP_8_BIT_DATA;
+	if (of_get_property(np, "mmc_cap_mmc_highspeed", NULL))
+		pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED;
+	if (of_get_property(np, "mmc_cap_sd_highspeed", NULL))
+		pdata->capabilities |= MMC_CAP_SD_HIGHSPEED;
+}
+#endif
+
 extern int __devinit mmci_probe(struct amba_device *dev,
 	const struct amba_id *id)
 {
 	struct mmci_platform_data *plat = dev->dev.platform_data;
 	struct variant_data *variant = id->data;
+	struct device_node *np = dev->dev.of_node;
 	struct mmci_host *host;
 	struct mmc_host *mmc;
 	int ret;
@@ -1071,6 +1108,12 @@ extern int __devinit mmci_probe(struct amba_device *dev,
 		goto out;
 	}
 
+#ifdef CONFIG_OF
+	if (np)
+		/* GPIOs, card detect invert, max freq, capabilites etc ... */
+		mmci_dt_populate_generic_pdata(np, plat);
+#endif
+
 	ret = amba_request_regions(dev, DRIVER_NAME);
 	if (ret)
 		goto out;
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 10:20:02 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 14:20:02 +0000
Subject: [PATCH 4/5] MMC: mmci: Enable Device Tree support for ux500 variants
In-Reply-To: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331734803-17954-5-git-send-email-lee.jones@linaro.org>

Provide a means to collect attributes specific to ST-Ericsson's
ux500 variant series. This patch registers itself as the AMBA
driver to be called during the probe process. Once all
attributes and ux500 specifics are are collected the normal
mmci core probe is called.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/db8500.dtsi      |    6 +-
 arch/arm/boot/dts/snowball.dts     |   30 ++++++-
 arch/arm/mach-ux500/board-mop500.c |    3 +-
 drivers/mmc/host/mmci-ux500.c      |  171 +++++++++++++++++++++++++++++++++++-
 4 files changed, 201 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index a9866a3..fd3d818 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -238,13 +238,13 @@
 		sdi at 80126000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80126000 0x1000>;
-			interrupts = <60>;
+			interrupts = <0 60 0x4>;
 			status = "disabled";
 		};
 		sdi at 80118000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80118000 0x1000>;
-			interrupts = <50>;
+			interrupts = <0 50 0x4>;
 			status = "disabled";
 		};
 		sdi at 80005000 {
@@ -262,7 +262,7 @@
 		sdi at 80114000 {
 			compatible = "arm,pl18x", "arm,primecell";
 			reg = <0x80114000 0x1000>;
-			interrupts = <99>;
+			interrupts = <0 99 0x4>;
 			status = "disabled";
 		};
 		sdi at 80008000 {
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 359c6d6..164200d 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -87,13 +87,37 @@
 			};
 		};
 
+		// External Micro SD slot
 		sdi at 80126000 {
-			status = "enabled";
-			cd-gpios = <&gpio6 26>;
+			arm,primecell-periphid = <0x10480180>;
+			#gpio-cells = <1>;
+			gpio-en   = <217>; // <&gpio6 25>;
+			gpio-vsel = <228>; // <&gpio7 4>;
+			cd-gpios  = <218>; // <&gpio6 26>;
+			cd-invert;
+
+			ocr_mask = <0x00020000>;
+			clock_frequency = <50000000>;
+			rx_src_dev_type = <29>;
+			tx_dst_dev_type = <29>;
+			mmc_cap_4_bit_data;
+			mmc_cap_mmc_highspeed;
+
+			status = "okay";
 		};
 
+		// On-board eMMC
 		sdi at 80114000 {
-			status = "enabled";
+			arm,primecell-periphid = <0x10480180>;
+			ocr_mask = <0x00020000>;
+		        clock_frequency = <50000000>;
+			mmc_cap_4_bit_data;
+			mmc_cap_8_bit_data;
+			mmc_cap_mmc_highspeed;
+			rx_src_dev_type = <42>;
+			tx_dst_dev_type = <42>;
+
+			status = "okay";
 		};
 
 		uart at 80120000 {
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index d0799d5..60c23c5 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -750,6 +750,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
 	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
 	OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
+	OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", NULL),
+	OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", NULL),
 	{},
 };
 
@@ -789,7 +791,6 @@ static void __init u8500_init_machine(void)
 		platform_add_devices(snowball_platform_devs,
 				ARRAY_SIZE(snowball_platform_devs));
 
-		snowball_sdi_init(parent);
 	} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
 		/*
 		 * The HREFv60 board removed a GPIO expander and routed
diff --git a/drivers/mmc/host/mmci-ux500.c b/drivers/mmc/host/mmci-ux500.c
index 82e60f9..75435e4 100644
--- a/drivers/mmc/host/mmci-ux500.c
+++ b/drivers/mmc/host/mmci-ux500.c
@@ -1,5 +1,11 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/of_gpio.h>
+
+#include <plat/ste_dma40.h>
+
+#include "mmci.h"
 
 /* MMCIPOWER bits */
 #define MCI_DATA2DIREN		(1 << 2)
@@ -37,6 +43,167 @@ static struct variant_data variant_ux500v2 = {
 	.blksz_datactrl16	= true,
 };
 
+struct mmci_ux500_platform_data {
+	struct mmci_platform_data pdata;
+	int gpio_en;
+	int gpio_vsel;
+};
+
+static u32 mmci_ux500_vdd_handler(struct device *dev, unsigned int vdd,
+				   unsigned char power_mode)
+{
+	struct mmci_ux500_platform_data *pdata =
+		container_of(dev->platform_data, struct mmci_ux500_platform_data, pdata);
+
+	switch (power_mode) {
+	case MMC_POWER_UP:
+	case MMC_POWER_ON:
+		/*
+		 * Level shifter voltage should depend on vdd to when deciding
+		 * on either 1.8V or 2.9V. Once the decision has been made the
+		 * level shifter must be disabled and re-enabled with a changed
+		 * select signal in order to switch the voltage. Since there is
+		 * no framework support yet for indicating 1.8V in vdd, use the
+		 * default 2.9V.
+		 */
+		if (pdata->gpio_vsel)
+			gpio_direction_output(pdata->gpio_vsel, 0);
+		if (pdata->gpio_en)
+			gpio_direction_output(pdata->gpio_en, 1);
+		break;
+	case MMC_POWER_OFF:
+		if (pdata->gpio_vsel)
+			gpio_direction_output(pdata->gpio_vsel, 0);
+		if (pdata->gpio_en)
+			gpio_direction_output(pdata->gpio_en, 0);
+		break;
+	}
+
+	return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
+	       MCI_DATA2DIREN | MCI_DATA31DIREN;
+}
+
+static int __devinit mmci_ux500_probe(struct amba_device *dev,
+				const struct amba_id *id)
+{
+	struct mmci_ux500_platform_data *ux500_pdata;
+	struct mmci_platform_data *pdata = dev->dev.platform_data;
+	struct device_node *np = dev->dev.of_node;
+	struct stedma40_chan_cfg *dma_tx_param;
+	struct stedma40_chan_cfg *dma_rx_param;
+	int val, ret = -EINVAL;
+
+	/* Check if we have already been populated by platform code. */
+	if (pdata)
+		return mmci_probe(dev, id);
+
+#ifdef CONFIG_OF
+	if (!np) {
+		pr_warning("No platform data or Device Tree found\n");
+		return -EINVAL;
+	}
+
+	ux500_pdata = kzalloc(sizeof(struct mmci_ux500_platform_data), GFP_KERNEL);
+	if (!ux500_pdata)
+		return -ENOMEM;
+
+	dma_tx_param = kzalloc(sizeof(struct stedma40_chan_cfg), GFP_KERNEL);
+	if (!dma_tx_param) {
+		ret = -ENOMEM;
+		goto out1;
+	}
+
+	dma_rx_param = kzalloc(sizeof(struct stedma40_chan_cfg), GFP_KERNEL);
+	if (!dma_rx_param) {
+		ret = -ENOMEM;
+		goto out2;
+	}
+
+	/* ST-Ericsson/Micro specific DMA attributes. */
+	ux500_pdata->gpio_vsel = 0;
+	ux500_pdata->gpio_en = 0;
+
+	of_property_read_u32(np, "gpio-en", &ux500_pdata->gpio_en);
+	of_property_read_u32(np, "gpio-vsel", &ux500_pdata->gpio_vsel);
+
+	if (ux500_pdata->gpio_vsel && ux500_pdata->gpio_en) {
+		ret  = gpio_request(ux500_pdata->gpio_en, "level shifter enable");
+		if (ret) {
+			pr_warning("GPIO request for level shifter enable failed.\n");
+			goto out3;
+		}
+
+		ret = gpio_request(ux500_pdata->gpio_vsel, "level shifter 1v8-3v select");
+		if (ret) {
+			pr_warning("GPIO request for level shifter select failed.\n");
+			goto out3;
+		}
+
+		/* Select the default 2.9V and enable level shifter */
+		gpio_direction_output(ux500_pdata->gpio_vsel, 0);
+		gpio_direction_output(ux500_pdata->gpio_en, 1);
+
+		ux500_pdata->pdata.vdd_handler = mmci_ux500_vdd_handler;
+	}
+
+	ux500_pdata->pdata.dma_filter  = stedma40_filter;
+
+	/* Mode. */
+	dma_tx_param->mode = STEDMA40_MODE_LOGICAL;
+	dma_rx_param->mode = STEDMA40_MODE_LOGICAL;
+
+	/* Direction. */
+	dma_tx_param->dir = STEDMA40_MEM_TO_PERIPH;
+	dma_rx_param->dir = STEDMA40_PERIPH_TO_MEM;
+
+	/* Device type. */
+	dma_tx_param->src_dev_type = STEDMA40_DEV_DST_MEMORY;
+
+	if (!of_property_read_u32(np, "tx_dst_dev_type", &val))
+		dma_tx_param->dst_dev_type = val;
+
+	dma_rx_param->dst_dev_type = STEDMA40_DEV_DST_MEMORY;
+
+	if (!of_property_read_u32(np, "rx_src_dev_type", &val))
+		dma_rx_param->src_dev_type = val;
+
+	/* Data width. */
+	dma_tx_param->src_info.data_width = STEDMA40_WORD_WIDTH;
+	dma_tx_param->dst_info.data_width = STEDMA40_WORD_WIDTH;
+	dma_rx_param->src_info.data_width = STEDMA40_WORD_WIDTH;
+	dma_rx_param->dst_info.data_width = STEDMA40_WORD_WIDTH;
+
+	ux500_pdata->pdata.dma_tx_param = dma_tx_param;
+	ux500_pdata->pdata.dma_rx_param = dma_rx_param;
+
+	dev->dev.platform_data = &ux500_pdata->pdata;
+
+	return mmci_probe(dev, id);
+
+out3:
+	kfree(dma_rx_param);
+out2:
+	kfree(dma_tx_param);
+out1:
+	kfree(ux500_pdata);
+#endif /* CONFIG_OF */
+
+	return ret;
+}
+
+static int __devexit mmci_ux500_remove(struct amba_device *dev)
+{
+	struct mmci_ux500_platform_data *pdata =
+		container_of(dev->dev.platform_data, struct mmci_ux500_platform_data, pdata);
+
+	kfree(pdata->pdata.dma_tx_param);
+	kfree(pdata->pdata.dma_tx_param);
+
+	mmci_remove(dev);
+
+	return 0;
+}
+
 static struct amba_id mmci_ux500_ids[] = {
 	/* ST Micro variants */
 	{
@@ -68,8 +235,8 @@ static struct amba_driver mmci_ux500_driver = {
 	.drv		= {
 		.name	= DRIVER_NAME,
 	},
-	.probe		= mmci_probe,
-	.remove		= __devexit_p(mmci_remove),
+	.probe		= mmci_ux500_probe,
+	.remove		= __devexit_p(mmci_ux500_remove),
 	.suspend	= mmci_suspend,
 	.resume		= mmci_resume,
 	.id_table	= mmci_ux500_ids,
-- 
1.7.5.4



From lee.jones at linaro.org  Wed Mar 14 10:20:03 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 14:20:03 +0000
Subject: [PATCH 5/5] MMC: mmci: Add required documentation for Device Tree
 bindings
In-Reply-To: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
Message-ID: <1331734803-17954-6-git-send-email-lee.jones@linaro.org>

This provides full documentation detailing each compulsory,
optional and device (variant) specific properties available
for use within the MMCI Device Tree.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 Documentation/devicetree/bindings/mmc/mmci.txt |   27 ++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/mmci.txt

diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt
new file mode 100644
index 0000000..946f080
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/mmci.txt
@@ -0,0 +1,27 @@
+* ARM PrimeCell MultiMedia Card Interface (MMCI) PL180/1
+
+The ARM PrimeCell MMCI PL180 and PL181 provides and interface for 
+reading and writing to MultiMedia and SD cards alike.
+
+Required properties:
+- compatible             : contains "arm,pl18x", "arm,primecell".
+- reg                    : contains pl18x registers and length.
+- interrupts             : contains the device IRQ(s).
+- arm,primecell-periphid : contains the PrimeCell Peripheral ID.
+
+Optional properties:
+- ocr_mask               : contains the regulator oscillator mask
+- wp-gpios               : contains any write protect (ro) gpios
+- cd-gpios               : contains any card detection gpios
+- cd-invert              : indicates whether the cd gpio is inverted 
+- clock_frequency        : contains the maximum operating frequency
+- mmc_cap_4_bit_data     : indicates whether device is 4 bit capable
+- mmc_cap_8_bit_data     : indicates whether device is 8 bit capable
+- mmc_cap_mmc_highspeed  : indicates whether MMC is high speed capable
+- mmc_cap_sd_highspeed   : indicates whether SD is high speed capable
+
+ux500 variant specific properties:
+- gpio-en                : contains the level-shifter enable gpio
+- gpio-vsel              : contains the level-shifter voltage select gpio
+- tx_dst_dev_type        : contains the tx destination device (DMA) 
+- rx_src_dev_type        : contains the rx source device (DMA)
-- 
1.7.5.4



From khilman at ti.com  Wed Mar 14 10:23:59 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 14 Mar 2012 07:23:59 -0700
Subject: [linux-pm] [PATCH 0/3] coupled cpuidle state support
In-Reply-To: <CAMbhsRRD2bdkcUZvScb-cF05e=R3h69bNVaTPFX4jBKBBOjuMg@mail.gmail.com>
 (Colin Cross's message of "Tue, 13 Mar 2012 17:47:20 -0700")
References: <1324426147-16735-1-git-send-email-ccross@android.com>
 <4F1929E9.7070707@linaro.org> <8762e8kqi6.fsf@ti.com>
 <CAMbhsRRZ+xt179RN32-+eBWngbRow=MpKV1XcLvG-sHGF6VOJA@mail.gmail.com>
 <CAMbhsRRD2bdkcUZvScb-cF05e=R3h69bNVaTPFX4jBKBBOjuMg@mail.gmail.com>
Message-ID: <87mx7jjm68.fsf@ti.com>

Colin Cross <ccross at android.com> writes:

> On Tue, Mar 13, 2012 at 5:28 PM, Colin Cross <ccross at android.com> wrote:
>> On Tue, Mar 13, 2012 at 4:52 PM, Kevin Hilman <khilman at ti.com> wrote:

[...]

>>>
>>> Checking the ready_count seemed like an easy way to do this, but did you
>>> have any other mechanisms in mind for CPUs to communicate that they've
>>> exited/aborted?
>>
>> Why not set a flag from CPU1 when it exits the low power state, and
>> have CPU0 spin on the powerdomain register or the flag? ?You can then
>> use the parallel barrier function to ensure both cpus have seen the
>> flag and reset it to 0 before returning.
>
> I realized the parallel barrier helper was not included in the patch
> set I posted, it will be in the next patch set.  

Do you have an ETA for the next patchset?  I'll be glad to give it a
spin on OMAP4.

> Short version, no caller to cpuidle_coupled_parallel_barrier will
> return before all cpus in the coupled set have called it.  It allows
> you to resynchronize the cpus after an abort to ensure they have all
> seen the abort flag before clearing it and returning, leaving
> everything in the correct state for the next idle attempt.

OK, this sounds like it will work well for what I need.

Kevin


From kgene.kim at samsung.com  Wed Mar 14 10:26:25 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:26:25 -0700
Subject: [PATCH 0/5] ARM: EXYNOS: add support PM for EXYNOS5250
Message-ID: <1331735190-28773-1-git-send-email-kgene.kim@samsung.com>

This patch adds support power management for EXYNOS5250 SoCs
and incudes regarding cleanup.

NOTE: this can be applied on top of next/soc-exynos5250-arch
of linux-samsung.git cleanly.

[PATCH 1/5] ARM: EXYNOS: Remove GIC save & restore function
[PATCH 2/5] ARM: EXYNOS: Rename of function for pm.c
[PATCH 3/5] ARM: EXYNOS: Add PMU table for EXYNOS5250
[PATCH 4/5] ARM: EXYNOS: Add Clock register list for save and
[PATCH 5/5] ARM: EXYNOS: Support suspend and resume for EXYNOS5250


From kgene.kim at samsung.com  Wed Mar 14 10:26:26 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:26:26 -0700
Subject: [PATCH 1/5] ARM: EXYNOS: Remove GIC save & restore function
In-Reply-To: <1331735190-28773-1-git-send-email-kgene.kim@samsung.com>
References: <1331735190-28773-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331735190-28773-2-git-send-email-kgene.kim@samsung.com>

From: Jongpill Lee <boyko.lee at samsung.com>

This patch removes GIC save & restore functino in pm.c. Because when
enalbe CPU_PM feature, GIC driver execute save and restore function
in CPU_PM notifier.
So it is not needed to GIC save & restore function at pm.c file.

Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/pm.c |   83 ---------------------------------------------
 1 files changed, 0 insertions(+), 83 deletions(-)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index f105bd2..696f0bf 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -64,89 +64,6 @@ static struct sleep_save exynos4_vpll_save[] = {
 };
 
 static struct sleep_save exynos4_core_save[] = {
-	/* GIC side */
-	SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
-	SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
-	SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
-	SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
-	SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
-	SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
-
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
-
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
-	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
-
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
-
 	/* SROM side */
 	SAVE_ITEM(S5P_SROM_BW),
 	SAVE_ITEM(S5P_SROM_BC0),
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:26:27 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:26:27 -0700
Subject: [PATCH 2/5] ARM: EXYNOS: Rename of function for pm.c
In-Reply-To: <1331735190-28773-1-git-send-email-kgene.kim@samsung.com>
References: <1331735190-28773-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331735190-28773-3-git-send-email-kgene.kim@samsung.com>

From: Jongpill Lee <boyko.lee at samsung.com>

This patch changes the function name of pmc. to support new
EXYNOS SoCs commonly.

Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/pm.c |   55 +++++++++++++++++++++++----------------------
 1 files changed, 28 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 696f0bf..abc1def 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/pm.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * EXYNOS4210 - Power Management support
+ * EXYNOS - Power Management support
  *
  * Based on arch/arm/mach-s3c2410/pm.c
  * Copyright (c) 2006 Simtec Electronics
@@ -63,7 +62,7 @@ static struct sleep_save exynos4_vpll_save[] = {
 	SAVE_ITEM(EXYNOS4_VPLL_CON1),
 };
 
-static struct sleep_save exynos4_core_save[] = {
+static struct sleep_save exynos_core_save[] = {
 	/* SROM side */
 	SAVE_ITEM(S5P_SROM_BW),
 	SAVE_ITEM(S5P_SROM_BC0),
@@ -83,7 +82,7 @@ static struct sleep_save exynos4_l2cc_save[] = {
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
 
-static int exynos4_cpu_suspend(unsigned long arg)
+static int exynos_cpu_suspend(unsigned long arg)
 {
 	outer_flush_all();
 
@@ -94,11 +93,11 @@ static int exynos4_cpu_suspend(unsigned long arg)
 	panic("sleep resumed to originator?");
 }
 
-static void exynos4_pm_prepare(void)
+static void exynos_pm_prepare(void)
 {
 	u32 tmp;
 
-	s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 	s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
 	s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
 	s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
@@ -123,10 +122,10 @@ static void exynos4_pm_prepare(void)
 
 }
 
-static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif)
+static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
 {
-	pm_cpu_prep = exynos4_pm_prepare;
-	pm_cpu_sleep = exynos4_cpu_suspend;
+	pm_cpu_prep = exynos_pm_prepare;
+	pm_cpu_sleep = exynos_cpu_suspend;
 
 	return 0;
 }
@@ -198,13 +197,13 @@ static void exynos4_restore_pll(void)
 	} while (epll_wait || vpll_wait);
 }
 
-static struct subsys_interface exynos4_pm_interface = {
+static struct subsys_interface exynos_pm_interface = {
 	.name		= "exynos4_pm",
 	.subsys		= &exynos4_subsys,
-	.add_dev	= exynos4_pm_add,
+	.add_dev	= exynos_pm_add,
 };
 
-static __init int exynos4_pm_drvinit(void)
+static __init int exynos_pm_drvinit(void)
 {
 	struct clk *pll_base;
 	unsigned int tmp;
@@ -217,18 +216,20 @@ static __init int exynos4_pm_drvinit(void)
 	tmp |= ((0xFF << 8) | (0x1F << 1));
 	__raw_writel(tmp, S5P_WAKEUP_MASK);
 
-	pll_base = clk_get(NULL, "xtal");
+	if (!soc_is_exynos5250()) {
+		pll_base = clk_get(NULL, "xtal");
 
-	if (!IS_ERR(pll_base)) {
-		pll_base_rate = clk_get_rate(pll_base);
-		clk_put(pll_base);
+		if (!IS_ERR(pll_base)) {
+			pll_base_rate = clk_get_rate(pll_base);
+			clk_put(pll_base);
+		}
 	}
 
-	return subsys_interface_register(&exynos4_pm_interface);
+	return subsys_interface_register(&exynos_pm_interface);
 }
-arch_initcall(exynos4_pm_drvinit);
+arch_initcall(exynos_pm_drvinit);
 
-static int exynos4_pm_suspend(void)
+static int exynos_pm_suspend(void)
 {
 	unsigned long tmp;
 
@@ -258,7 +259,7 @@ static int exynos4_pm_suspend(void)
 	return 0;
 }
 
-static void exynos4_pm_resume(void)
+static void exynos_pm_resume(void)
 {
 	unsigned long tmp;
 
@@ -297,7 +298,7 @@ static void exynos4_pm_resume(void)
 	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 
-	s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
 	exynos4_restore_pll();
 
@@ -316,14 +317,14 @@ early_wakeup:
 	return;
 }
 
-static struct syscore_ops exynos4_pm_syscore_ops = {
-	.suspend	= exynos4_pm_suspend,
-	.resume		= exynos4_pm_resume,
+static struct syscore_ops exynos_pm_syscore_ops = {
+	.suspend	= exynos_pm_suspend,
+	.resume		= exynos_pm_resume,
 };
 
 static __init int exynos4_pm_syscore_init(void)
 {
-	register_syscore_ops(&exynos4_pm_syscore_ops);
+	register_syscore_ops(&exynos_pm_syscore_ops);
 	return 0;
 }
 arch_initcall(exynos4_pm_syscore_init);
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:26:28 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:26:28 -0700
Subject: [PATCH 3/5] ARM: EXYNOS: Add PMU table for EXYNOS5250
In-Reply-To: <1331735190-28773-1-git-send-email-kgene.kim@samsung.com>
References: <1331735190-28773-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331735190-28773-4-git-send-email-kgene.kim@samsung.com>

From: Jongpill Lee <boyko.lee at samsung.com>

This patch adds pmu table setting feature for EXYNOS5250.

Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/include/mach/regs-pmu.h |  148 +++++++++++++++++++++++++-
 arch/arm/mach-exynos/pmu.c                   |  110 +++++++++++++++++++
 2 files changed, 254 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4c53f38..2274b83 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * EXYNOS4 - Power management unit definition
+ * EXYNOS - Power management unit definition
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -218,4 +217,145 @@
 #define S5P_SECSS_MEM_OPTION			S5P_PMUREG(0x2EC8)
 #define S5P_ROTATOR_MEM_OPTION			S5P_PMUREG(0x2F48)
 
+/* For EXYNOS5 */
+
+#define EXYNOS5_GPS_LPI						S5P_PMUREG(0x0004)
+
+#define EXYNOS5_USB_CFG						S5P_PMUREG(0x0230)
+
+#define EXYNOS5_ARM_CORE0_SYS_PWR_REG				S5P_PMUREG(0x1000)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1004)
+#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1008)
+#define EXYNOS5_ARM_CORE1_SYS_PWR_REG				S5P_PMUREG(0x1010)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1014)
+#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1018)
+#define EXYNOS5_FSYS_ARM_SYS_PWR_REG				S5P_PMUREG(0x1040)
+#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1048)
+#define EXYNOS5_ISP_ARM_SYS_PWR_REG				S5P_PMUREG(0x1050)
+#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1054)
+#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1058)
+#define EXYNOS5_ARM_COMMON_SYS_PWR_REG				S5P_PMUREG(0x1080)
+#define EXYNOS5_ARM_L2_SYS_PWR_REG				S5P_PMUREG(0x10C0)
+#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG			S5P_PMUREG(0x1100)
+#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG			S5P_PMUREG(0x1104)
+#define EXYNOS5_CMU_RESET_SYS_PWR_REG				S5P_PMUREG(0x110C)
+#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1120)
+#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1124)
+#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x112C)
+#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG			S5P_PMUREG(0x1130)
+#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG			S5P_PMUREG(0x1134)
+#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG			S5P_PMUREG(0x1138)
+#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1140)
+#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1144)
+#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1148)
+#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x114C)
+#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1150)
+#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG				S5P_PMUREG(0x1154)
+#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG			S5P_PMUREG(0x1164)
+#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG			S5P_PMUREG(0x1170)
+#define EXYNOS5_TOP_BUS_SYS_PWR_REG				S5P_PMUREG(0x1180)
+#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG			S5P_PMUREG(0x1184)
+#define EXYNOS5_TOP_PWR_SYS_PWR_REG				S5P_PMUREG(0x1188)
+#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1190)
+#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG		S5P_PMUREG(0x1194)
+#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1198)
+#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG				S5P_PMUREG(0x11A0)
+#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG				S5P_PMUREG(0x11A4)
+#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x11B0)
+#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x11B4)
+#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG				S5P_PMUREG(0x11C0)
+#define EXYNOS5_G2D_MEM_SYS_PWR_REG				S5P_PMUREG(0x11C8)
+#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG				S5P_PMUREG(0x11CC)
+#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG				S5P_PMUREG(0x11D0)
+#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG				S5P_PMUREG(0x11D4)
+#define EXYNOS5_SECSS_MEM_SYS_PWR_REG				S5P_PMUREG(0x11D8)
+#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG				S5P_PMUREG(0x11DC)
+#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG				S5P_PMUREG(0x11E0)
+#define EXYNOS5_INTROM_MEM_SYS_PWR_REG				S5P_PMUREG(0x11E4)
+#define EXYNOS5_JPEG_MEM_SYS_PWR_REG				S5P_PMUREG(0x11E8)
+#define EXYNOS5_HSI_MEM_SYS_PWR_REG				S5P_PMUREG(0x11EC)
+#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG				S5P_PMUREG(0x11F4)
+#define EXYNOS5_SATA_MEM_SYS_PWR_REG				S5P_PMUREG(0x11FC)
+#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG			S5P_PMUREG(0x1200)
+#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG			S5P_PMUREG(0x1204)
+#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG		S5P_PMUREG(0x1208)
+#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG			S5P_PMUREG(0x1220)
+#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG			S5P_PMUREG(0x1224)
+#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG			S5P_PMUREG(0x1228)
+#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG			S5P_PMUREG(0x122C)
+#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG			S5P_PMUREG(0x1230)
+#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG			S5P_PMUREG(0x1234)
+#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG			S5P_PMUREG(0x1238)
+#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG		S5P_PMUREG(0x123C)
+#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG			S5P_PMUREG(0x1240)
+#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG		S5P_PMUREG(0x1250)
+#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG				S5P_PMUREG(0x1260)
+#define EXYNOS5_XUSBXTI_SYS_PWR_REG				S5P_PMUREG(0x1280)
+#define EXYNOS5_XXTI_SYS_PWR_REG				S5P_PMUREG(0x1284)
+#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG			S5P_PMUREG(0x12C0)
+#define EXYNOS5_GPIO_MODE_SYS_PWR_REG				S5P_PMUREG(0x1300)
+#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG			S5P_PMUREG(0x1320)
+#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG			S5P_PMUREG(0x1340)
+#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG			S5P_PMUREG(0x1344)
+#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG			S5P_PMUREG(0x1348)
+#define EXYNOS5_GSCL_SYS_PWR_REG				S5P_PMUREG(0x1400)
+#define EXYNOS5_ISP_SYS_PWR_REG					S5P_PMUREG(0x1404)
+#define EXYNOS5_MFC_SYS_PWR_REG					S5P_PMUREG(0x1408)
+#define EXYNOS5_G3D_SYS_PWR_REG					S5P_PMUREG(0x140C)
+#define EXYNOS5_DISP1_SYS_PWR_REG				S5P_PMUREG(0x1414)
+#define EXYNOS5_MAU_SYS_PWR_REG					S5P_PMUREG(0x1418)
+#define EXYNOS5_GPS_SYS_PWR_REG					S5P_PMUREG(0x141C)
+#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG			S5P_PMUREG(0x1480)
+#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG			S5P_PMUREG(0x1484)
+#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG			S5P_PMUREG(0x1488)
+#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG			S5P_PMUREG(0x148C)
+#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG			S5P_PMUREG(0x1494)
+#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG			S5P_PMUREG(0x1498)
+#define EXYNOS5_CMU_CLKSTOP_GPS_SYS_PWR_REG			S5P_PMUREG(0x149C)
+#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG			S5P_PMUREG(0x14C0)
+#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG			S5P_PMUREG(0x14C4)
+#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG			S5P_PMUREG(0x14C8)
+#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG			S5P_PMUREG(0x14CC)
+#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG			S5P_PMUREG(0x14D4)
+#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG			S5P_PMUREG(0x14D8)
+#define EXYNOS5_CMU_SYSCLK_GPS_SYS_PWR_REG			S5P_PMUREG(0x14DC)
+#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG			S5P_PMUREG(0x1580)
+#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG			S5P_PMUREG(0x1584)
+#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG			S5P_PMUREG(0x1588)
+#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG			S5P_PMUREG(0x158C)
+#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG			S5P_PMUREG(0x1594)
+#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG			S5P_PMUREG(0x1598)
+#define EXYNOS5_CMU_RESET_GPS_SYS_PWR_REG			S5P_PMUREG(0x159C)
+
+#define EXYNOS5_ARM_CORE0_OPTION				S5P_PMUREG(0x2008)
+#define EXYNOS5_ARM_CORE1_OPTION				S5P_PMUREG(0x2088)
+#define EXYNOS5_FSYS_ARM_OPTION					S5P_PMUREG(0x2208)
+#define EXYNOS5_ISP_ARM_OPTION					S5P_PMUREG(0x2288)
+#define EXYNOS5_ARM_COMMON_OPTION				S5P_PMUREG(0x2408)
+#define EXYNOS5_TOP_PWR_OPTION					S5P_PMUREG(0x2C48)
+#define EXYNOS5_TOP_PWR_SYSMEM_OPTION				S5P_PMUREG(0x2CC8)
+#define EXYNOS5_JPEG_MEM_OPTION					S5P_PMUREG(0x2F48)
+#define EXYNOS5_GSCL_STATUS					S5P_PMUREG(0x4004)
+#define EXYNOS5_ISP_STATUS					S5P_PMUREG(0x4024)
+#define EXYNOS5_GSCL_OPTION					S5P_PMUREG(0x4008)
+#define EXYNOS5_ISP_OPTION					S5P_PMUREG(0x4028)
+#define EXYNOS5_MFC_OPTION					S5P_PMUREG(0x4048)
+#define EXYNOS5_G3D_CONFIGURATION				S5P_PMUREG(0x4060)
+#define EXYNOS5_G3D_STATUS					S5P_PMUREG(0x4064)
+#define EXYNOS5_G3D_OPTION					S5P_PMUREG(0x4068)
+#define EXYNOS5_DISP1_OPTION					S5P_PMUREG(0x40A8)
+#define EXYNOS5_MAU_OPTION					S5P_PMUREG(0x40C8)
+#define EXYNOS5_GPS_OPTION					S5P_PMUREG(0x40E8)
+
+#define EXYNOS5_USE_SC_FEEDBACK					(1 << 1)
+#define EXYNOS5_USE_SC_COUNTER					(1 << 0)
+
+#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL			(1 << 2)
+#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN			(1 << 7)
+
+#define EXYNOS5_OPTION_USE_STANDBYWFE				(1 << 24)
+#define EXYNOS5_OPTION_USE_STANDBYWFI				(1 << 16)
+
+#define EXYNOS5_OPTION_USE_RETENTION				(1 << 4)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index bba48f5..5c7eb15 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -202,6 +202,113 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
 	{ PMU_TABLE_END,},
 };
 
+static struct exynos4_pmu_conf exynos5250_pmu_config[] = {
+	/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+	{ EXYNOS5_ARM_CORE0_SYS_PWR_REG,		{ 0x0, 0x0, 0x2} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_ARM_CORE1_SYS_PWR_REG,		{ 0x0, 0x0, 0x2} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_FSYS_ARM_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG,	{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_ISP_ARM_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_ARM_COMMON_SYS_PWR_REG,		{ 0x0, 0x0, 0x2} },
+	{ EXYNOS5_ARM_L2_SYS_PWR_REG,			{ 0x3, 0x3, 0x3} },
+	{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_CMU_RESET_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,	{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,	{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,		{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,		{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,		{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_TOP_BUS_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_TOP_RETENTION_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_TOP_PWR_SYS_PWR_REG,			{ 0x3, 0x0, 0x3} },
+	{ EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG,		{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG,	{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,		{ 0x3, 0x0, 0x3} },
+	{ EXYNOS5_LOGIC_RESET_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_OSCCLK_GATE_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,	{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,	{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_USBOTG_MEM_SYS_PWR_REG,		{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_G2D_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_USBDRD_MEM_SYS_PWR_REG,		{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_SDMMC_MEM_SYS_PWR_REG,		{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_CSSYS_MEM_SYS_PWR_REG,		{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_SECSS_MEM_SYS_PWR_REG,		{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_ROTATOR_MEM_SYS_PWR_REG,		{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_INTRAM_MEM_SYS_PWR_REG,		{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_INTROM_MEM_SYS_PWR_REG,		{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_JPEG_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_HSI_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_MCUIOP_MEM_SYS_PWR_REG,		{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_SATA_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG,	{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_ISOLATION_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_XUSBXTI_SYS_PWR_REG,			{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_XXTI_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_EXT_REGULATOR_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_GPIO_MODE_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG,		{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG,	{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_GSCL_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_ISP_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_MFC_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_G3D_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_DISP1_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_MAU_SYS_PWR_REG,			{ 0x7, 0x7, 0x0} },
+	{ EXYNOS5_GPS_SYS_PWR_REG,			{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_GPS_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_GPS_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_CMU_RESET_GPS_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ PMU_TABLE_END,},
+};
+
 void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
 {
 	unsigned int i;
@@ -221,6 +328,9 @@ static int __init exynos4_pmu_init(void)
 	} else if (soc_is_exynos4212()) {
 		exynos4_pmu_config = exynos4212_pmu_config;
 		pr_info("EXYNOS4212 PMU Initialize\n");
+	} else if (soc_is_exynos5250()) {
+		exynos4_pmu_config = exynos5250_pmu_config;
+		pr_info("EXYNOS5250 PMU Initialize\n");
 	} else {
 		pr_info("EXYNOS4: PMU not supported\n");
 	}
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:26:29 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:26:29 -0700
Subject: [PATCH 4/5] ARM: EXYNOS: Add Clock register list for save and restore
In-Reply-To: <1331735190-28773-1-git-send-email-kgene.kim@samsung.com>
References: <1331735190-28773-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331735190-28773-5-git-send-email-kgene.kim@samsung.com>

From: Jongpill Lee <boyko.lee at samsung.com>

This patch adds clock register list for save and restore. When system
enter suspend mode and wakeup from suspend mode, All clock register is
reset.  So critical register should be saved and reset.

Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/clock-exynos5.c           |   52 +++++++++++++++++++++++-
 arch/arm/mach-exynos/include/mach/regs-clock.h |   17 +++++++-
 2 files changed, 67 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index d013982..f300941 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -30,7 +30,57 @@
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos5_clock_save[] = {
-	/* will be implemented */
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_GPS),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
+	SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
+	SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
+	SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
+	SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
+	SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
+	SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
+	SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
+	SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
+	SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
+	SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
+	SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
+	SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
+	SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
+	SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
+	SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
+	SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
+	SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
+	SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
+	SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
+	SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
+	SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
+	SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
+	SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
+	SAVE_ITEM(EXYNOS5_EPLL_CON0),
+	SAVE_ITEM(EXYNOS5_EPLL_CON1),
+	SAVE_ITEM(EXYNOS5_EPLL_CON2),
+	SAVE_ITEM(EXYNOS5_VPLL_CON0),
+	SAVE_ITEM(EXYNOS5_VPLL_CON1),
+	SAVE_ITEM(EXYNOS5_VPLL_CON2),
 };
 #endif
 
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index e141c1f..5542b8c 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -265,36 +265,51 @@
 
 #define EXYNOS5_CLKDIV_ACP			EXYNOS_CLKREG(0x08500)
 
-#define EXYNOS5_CLKSRC_TOP2			EXYNOS_CLKREG(0x10218)
 #define EXYNOS5_EPLL_CON0			EXYNOS_CLKREG(0x10130)
 #define EXYNOS5_EPLL_CON1			EXYNOS_CLKREG(0x10134)
+#define EXYNOS5_EPLL_CON2			EXYNOS_CLKREG(0x10138)
 #define EXYNOS5_VPLL_CON0			EXYNOS_CLKREG(0x10140)
 #define EXYNOS5_VPLL_CON1			EXYNOS_CLKREG(0x10144)
+#define EXYNOS5_VPLL_CON2			EXYNOS_CLKREG(0x10148)
 #define EXYNOS5_CPLL_CON0			EXYNOS_CLKREG(0x10120)
 
 #define EXYNOS5_CLKSRC_TOP0			EXYNOS_CLKREG(0x10210)
+#define EXYNOS5_CLKSRC_TOP1			EXYNOS_CLKREG(0x10214)
+#define EXYNOS5_CLKSRC_TOP2			EXYNOS_CLKREG(0x10218)
 #define EXYNOS5_CLKSRC_TOP3			EXYNOS_CLKREG(0x1021C)
 #define EXYNOS5_CLKSRC_GSCL			EXYNOS_CLKREG(0x10220)
 #define EXYNOS5_CLKSRC_DISP1_0			EXYNOS_CLKREG(0x1022C)
+#define EXYNOS5_CLKSRC_MAUDIO			EXYNOS_CLKREG(0x10240)
 #define EXYNOS5_CLKSRC_FSYS			EXYNOS_CLKREG(0x10244)
 #define EXYNOS5_CLKSRC_PERIC0			EXYNOS_CLKREG(0x10250)
+#define EXYNOS5_CLKSRC_PERIC1			EXYNOS_CLKREG(0x10254)
+#define EXYNOS5_SCLK_SRC_ISP			EXYNOS_CLKREG(0x10270)
 
 #define EXYNOS5_CLKSRC_MASK_TOP			EXYNOS_CLKREG(0x10310)
 #define EXYNOS5_CLKSRC_MASK_GSCL		EXYNOS_CLKREG(0x10320)
 #define EXYNOS5_CLKSRC_MASK_DISP1_0		EXYNOS_CLKREG(0x1032C)
+#define EXYNOS5_CLKSRC_MASK_MAUDIO		EXYNOS_CLKREG(0x10334)
 #define EXYNOS5_CLKSRC_MASK_FSYS		EXYNOS_CLKREG(0x10340)
 #define EXYNOS5_CLKSRC_MASK_PERIC0		EXYNOS_CLKREG(0x10350)
+#define EXYNOS5_CLKSRC_MASK_PERIC1		EXYNOS_CLKREG(0x10354)
 
 #define EXYNOS5_CLKDIV_TOP0			EXYNOS_CLKREG(0x10510)
 #define EXYNOS5_CLKDIV_TOP1			EXYNOS_CLKREG(0x10514)
 #define EXYNOS5_CLKDIV_GSCL			EXYNOS_CLKREG(0x10520)
 #define EXYNOS5_CLKDIV_DISP1_0			EXYNOS_CLKREG(0x1052C)
 #define EXYNOS5_CLKDIV_GEN			EXYNOS_CLKREG(0x1053C)
+#define EXYNOS5_CLKDIV_MAUDIO			EXYNOS_CLKREG(0x10544)
 #define EXYNOS5_CLKDIV_FSYS0			EXYNOS_CLKREG(0x10548)
 #define EXYNOS5_CLKDIV_FSYS1			EXYNOS_CLKREG(0x1054C)
 #define EXYNOS5_CLKDIV_FSYS2			EXYNOS_CLKREG(0x10550)
 #define EXYNOS5_CLKDIV_FSYS3			EXYNOS_CLKREG(0x10554)
 #define EXYNOS5_CLKDIV_PERIC0			EXYNOS_CLKREG(0x10558)
+#define EXYNOS5_CLKDIV_PERIC1			EXYNOS_CLKREG(0x1055C)
+#define EXYNOS5_CLKDIV_PERIC2			EXYNOS_CLKREG(0x10560)
+#define EXYNOS5_CLKDIV_PERIC3			EXYNOS_CLKREG(0x10564)
+#define EXYNOS5_CLKDIV_PERIC4			EXYNOS_CLKREG(0x10568)
+#define EXYNOS5_CLKDIV_PERIC5			EXYNOS_CLKREG(0x1056C)
+#define EXYNOS5_SCLK_DIV_ISP			EXYNOS_CLKREG(0x10580)
 
 #define EXYNOS5_CLKGATE_IP_ACP			EXYNOS_CLKREG(0x08800)
 #define EXYNOS5_CLKGATE_IP_GSCL			EXYNOS_CLKREG(0x10920)
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:26:30 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:26:30 -0700
Subject: [PATCH 5/5] ARM: EXYNOS: Support suspend and resume for EXYNOS5250
In-Reply-To: <1331735190-28773-1-git-send-email-kgene.kim@samsung.com>
References: <1331735190-28773-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331735190-28773-6-git-send-email-kgene.kim@samsung.com>

From: Jongpill Lee <boyko.lee at samsung.com>

This patch adds function for suspend and resume of Exynos5250.

Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/include/mach/pm-core.h |    2 +-
 arch/arm/mach-exynos/pm.c                   |  123 ++++++++++++++++-----------
 arch/arm/mach-exynos/pmu.c                  |   59 +++++++++++++
 arch/arm/plat-samsung/include/plat/cpu.h    |    1 +
 4 files changed, 135 insertions(+), 50 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index 9d8da51e3..a67ecfa 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -33,7 +33,7 @@ static inline void s3c_pm_arch_prepare_irqs(void)
 	__raw_writel(tmp, S5P_WAKEUP_MASK);
 
 	__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
-	__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+	__raw_writel(s3c_irqwake_eintmask & 0xFFFFFFFE, S5P_EINT_WAKEUP_MASK);
 }
 
 static inline void s3c_pm_arch_stop_clocks(void)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index abc1def..94faa3e 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -84,7 +84,14 @@ static unsigned int save_arm_register[2];
 
 static int exynos_cpu_suspend(unsigned long arg)
 {
+#ifdef CONFIG_CACHE_L2X0
 	outer_flush_all();
+#endif
+	/*
+	 * To enter suspend mode, GPS LPI register must be set.
+	 */
+	if (soc_is_exynos5250())
+		__raw_writel(0x10000, EXYNOS5_GPS_LPI);
 
 	/* issue the standby signal into the pm unit. */
 	cpu_do_idle();
@@ -95,27 +102,35 @@ static int exynos_cpu_suspend(unsigned long arg)
 
 static void exynos_pm_prepare(void)
 {
-	u32 tmp;
+	unsigned int tmp;
 
 	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-	s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
-	s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
-	s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 
-	tmp = __raw_readl(S5P_INFORM1);
+	if (!soc_is_exynos5250()) {
+		s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+		s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
+		s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
+	} else {
+		/* Disable USE_RETENTION of JPEG_MEM_OPTION */
+		tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
+		tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
+		__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
+	}
 
 	/* Set value of power down register for sleep mode */
-
 	exynos4_sys_powerdown_conf(SYS_SLEEP);
 	__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 
 	/* ensure at least INFORM0 has the resume address */
-
 	__raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
 
-	/* Before enter central sequence mode, clock src register have to set */
-
-	s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
+	/*
+	 * Before enter central sequence mode,
+	 * clock src register have to set.
+	 */
+	if (!soc_is_exynos5250())
+		s3c_pm_do_restore_core(exynos4_set_clksrc,
+				ARRAY_SIZE(exynos4_set_clksrc));
 
 	if (soc_is_exynos4210())
 		s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
@@ -197,12 +212,18 @@ static void exynos4_restore_pll(void)
 	} while (epll_wait || vpll_wait);
 }
 
-static struct subsys_interface exynos_pm_interface = {
-	.name		= "exynos4_pm",
+static struct subsys_interface exynos4_pm_interface = {
+	.name		= "exynos_pm",
 	.subsys		= &exynos4_subsys,
 	.add_dev	= exynos_pm_add,
 };
 
+static struct subsys_interface exynos5_pm_interface = {
+	.name		= "exynos_pm",
+	.subsys		= &exynos5_subsys,
+	.add_dev	= exynos_pm_add,
+};
+
 static __init int exynos_pm_drvinit(void)
 {
 	struct clk *pll_base;
@@ -224,8 +245,10 @@ static __init int exynos_pm_drvinit(void)
 			clk_put(pll_base);
 		}
 	}
-
-	return subsys_interface_register(&exynos_pm_interface);
+	if (soc_is_exynos5250())
+		return subsys_interface_register(&exynos5_pm_interface);
+	else
+		return subsys_interface_register(&exynos4_pm_interface);
 }
 arch_initcall(exynos_pm_drvinit);
 
@@ -234,27 +257,25 @@ static int exynos_pm_suspend(void)
 	unsigned long tmp;
 
 	/* Setting Central Sequence Register for power down mode */
-
 	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
-	if (soc_is_exynos4212()) {
-		tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
-		tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
-			 S5P_USE_STANDBYWFE_ISP_ARM);
-		__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-	}
-
-	/* Save Power control register */
-	asm ("mrc p15, 0, %0, c15, c0, 0"
-	     : "=r" (tmp) : : "cc");
-	save_arm_register[0] = tmp;
+	/* Setting SEQ_OPTION register */
+	tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
+	__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 
-	/* Save Diagnostic register */
-	asm ("mrc p15, 0, %0, c15, c0, 1"
-	     : "=r" (tmp) : : "cc");
-	save_arm_register[1] = tmp;
+	if (!soc_is_exynos5250()) {
+		/* Save Power control register */
+		asm ("mrc p15, 0, %0, c15, c0, 0"
+		     : "=r" (tmp) : : "cc");
+		save_arm_register[0] = tmp;
+
+		/* Save Diagnostic register */
+		asm ("mrc p15, 0, %0, c15, c0, 1"
+		     : "=r" (tmp) : : "cc");
+		save_arm_register[1] = tmp;
+	}
 
 	return 0;
 }
@@ -276,17 +297,19 @@ static void exynos_pm_resume(void)
 		/* No need to perform below restore code */
 		goto early_wakeup;
 	}
-	/* Restore Power control register */
-	tmp = save_arm_register[0];
-	asm volatile ("mcr p15, 0, %0, c15, c0, 0"
-		      : : "r" (tmp)
-		      : "cc");
-
-	/* Restore Diagnostic register */
-	tmp = save_arm_register[1];
-	asm volatile ("mcr p15, 0, %0, c15, c0, 1"
-		      : : "r" (tmp)
-		      : "cc");
+	if (!soc_is_exynos5250()) {
+		/* Restore Power control register */
+		tmp = save_arm_register[0];
+		asm volatile ("mcr p15, 0, %0, c15, c0, 0"
+			      : : "r" (tmp)
+			      : "cc");
+
+		/* Restore Diagnostic register */
+		tmp = save_arm_register[1];
+		asm volatile ("mcr p15, 0, %0, c15, c0, 1"
+			      : : "r" (tmp)
+			      : "cc");
+	}
 
 	/* For release retention */
 
@@ -300,18 +323,20 @@ static void exynos_pm_resume(void)
 
 	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 
-	exynos4_restore_pll();
+	if (!soc_is_exynos5250()) {
+		exynos4_restore_pll();
 
 #ifdef CONFIG_SMP
-	scu_enable(S5P_VA_SCU);
+		scu_enable(S5P_VA_SCU);
 #endif
 
 #ifdef CONFIG_CACHE_L2X0
-	s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
-	outer_inv_all();
-	/* enable L2X0*/
-	writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
+		s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+		outer_inv_all();
+		/* enable L2X0*/
+		writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
 #endif
+	}
 
 early_wakeup:
 	return;
@@ -322,9 +347,9 @@ static struct syscore_ops exynos_pm_syscore_ops = {
 	.resume		= exynos_pm_resume,
 };
 
-static __init int exynos4_pm_syscore_init(void)
+static __init int exynos_pm_syscore_init(void)
 {
 	register_syscore_ops(&exynos_pm_syscore_ops);
 	return 0;
 }
-arch_initcall(exynos4_pm_syscore_init);
+arch_initcall(exynos_pm_syscore_init);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 5c7eb15..51aa1ec 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -309,10 +309,69 @@ static struct exynos4_pmu_conf exynos5250_pmu_config[] = {
 	{ PMU_TABLE_END,},
 };
 
+void __iomem *exynos5_list_both_cnt_feed[] = {
+	EXYNOS5_ARM_CORE0_OPTION,
+	EXYNOS5_ARM_CORE1_OPTION,
+	EXYNOS5_ARM_COMMON_OPTION,
+	EXYNOS5_GSCL_OPTION,
+	EXYNOS5_ISP_OPTION,
+	EXYNOS5_MFC_OPTION,
+	EXYNOS5_G3D_OPTION,
+	EXYNOS5_DISP1_OPTION,
+	EXYNOS5_MAU_OPTION,
+	EXYNOS5_GPS_OPTION,
+	EXYNOS5_TOP_PWR_OPTION,
+	EXYNOS5_TOP_PWR_SYSMEM_OPTION,
+};
+
+void __iomem *exynos5_list_diable_wfi_wfe[] = {
+	EXYNOS5_ARM_CORE1_OPTION,
+	EXYNOS5_FSYS_ARM_OPTION,
+	EXYNOS5_ISP_ARM_OPTION,
+};
+
+static void exynos5_init_pmu(void)
+{
+	unsigned int i;
+	unsigned int tmp;
+
+	/*
+	 * Enable both SC_FEEDBACK and SC_COUNTER
+	 */
+	for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
+		tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
+		tmp |= (EXYNOS5_USE_SC_FEEDBACK |
+			EXYNOS5_USE_SC_COUNTER);
+		__raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
+	}
+
+	/*
+	 * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
+	 * MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable
+	 */
+	tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
+	tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL |
+		EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN);
+	__raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
+
+	/*
+	 * Disable WFI/WFE on XXX_OPTION
+	 */
+	for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
+		tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
+		tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
+			 EXYNOS5_OPTION_USE_STANDBYWFI);
+		__raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
+	}
+}
+
 void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
 {
 	unsigned int i;
 
+	if (soc_is_exynos5250())
+		exynos5_init_pmu();
+
 	for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
 		__raw_writel(exynos4_pmu_config[i].val[mode],
 				exynos4_pmu_config[i].reg);
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 787ceac..747c27d 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -203,6 +203,7 @@ extern struct bus_type s3c6410_subsys;
 extern struct bus_type s5p64x0_subsys;
 extern struct bus_type s5pv210_subsys;
 extern struct bus_type exynos4_subsys;
+extern struct bus_type exynos5_subsys;
 
 extern void (*s5pc1xx_idle)(void);
 
-- 
1.7.4.4



From haojian.zhuang at gmail.com  Wed Mar 14 10:32:23 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 14 Mar 2012 22:32:23 +0800
Subject: [PATCH] mfd: pcap: depend on arch-pxa
In-Reply-To: <1331011808-28307-1-git-send-email-haojian.zhuang@gmail.com>
References: <1331011808-28307-1-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <CAN1soZwf8fSwZeoXBg87Xb=24xmo8m=T8wR74DKJUT5WQYfjrA@mail.gmail.com>

On Tue, Mar 6, 2012 at 1:30 PM, Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
> drivers/mfd/ezx-pcap.c: In function ?pcap_isr_work?:
> drivers/mfd/ezx-pcap.c:206:2: error: implicit declaration of function
> ?pxa_irq_to_gpio?
> make[2]: *** [drivers/mfd/ezx-pcap.o] Error 1
>
> PCAP driver invokes irq_to_gpio() directly. This function isn't common
> function in most silicons. PCAP driver is enabled for EZX machine with
> arch-pxa. Now use pxa_irq_to_gpio() instead.
>
> It's only a workaround for this issue. Acutally the best solution is
> using thread irq to fix this issue.
>
> Signed-off-by: Haojian Zhuang <haojian.zhuang at gmail.com>
> ---
> ?drivers/mfd/Kconfig ? ?| ? ?2 +-
> ?drivers/mfd/ezx-pcap.c | ? ?3 ++-
> ?2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index f147395..e88d315 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -619,7 +619,7 @@ config AB3100_OTP
>
> ?config EZX_PCAP
> ? ? ? ?bool "PCAP Support"
> - ? ? ? depends on GENERIC_HARDIRQS && SPI_MASTER
> + ? ? ? depends on GENERIC_HARDIRQS && SPI_MASTER && ARCH_PXA
> ? ? ? ?help
> ? ? ? ? ?This enables the PCAP ASIC present on EZX Phones. This is
> ? ? ? ? ?needed for MMC, TouchScreen, Sound, USB, etc..
> diff --git a/drivers/mfd/ezx-pcap.c b/drivers/mfd/ezx-pcap.c
> index 43a76c4..e9320e2 100644
> --- a/drivers/mfd/ezx-pcap.c
> +++ b/drivers/mfd/ezx-pcap.c
> @@ -18,6 +18,7 @@
> ?#include <linux/mfd/ezx-pcap.h>
> ?#include <linux/spi/spi.h>
> ?#include <linux/gpio.h>
> +#include <linux/gpio-pxa.h>
> ?#include <linux/slab.h>
>
> ?#define PCAP_ADC_MAXQ ? ? ? ? ?8
> @@ -202,7 +203,7 @@ static void pcap_isr_work(struct work_struct *work)
> ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ?local_irq_enable();
> ? ? ? ? ? ? ? ?ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
> - ? ? ? } while (gpio_get_value(irq_to_gpio(pcap->spi->irq)));
> + ? ? ? } while (gpio_get_value(pxa_irq_to_gpio(pcap->spi->irq)));
> ?}
>
> ?static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
> --
> 1.7.5.4
>

Hi Samuel,

How about this patch? Is it OK?

Best Regards
Haojian


From lee.jones at linaro.org  Wed Mar 14 10:37:45 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 14:37:45 +0000
Subject: [PATCH 02/10] ARM: ux500: Initial Device Tree support for Snowball
In-Reply-To: <201203141358.03541.arnd@arndb.de>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-3-git-send-email-lee.jones@linaro.org>
 <201203141358.03541.arnd@arndb.de>
Message-ID: <4F60AD39.6020009@linaro.org>

On 14/03/12 13:58, Arnd Bergmann wrote:
> On Wednesday 14 March 2012, Lee Jones wrote:
>>
>> From: Arnd Bergmann <arnd at arndb.de>
>>
>> This provides very basic Device Tree support for ST-Ericsson's
>> low-cost development platform, Snowball. If Device Tree for
>> ux500 is enabled and the correct board is configured within the
>> Device Tree blob, the correct *_init_machine() will be called.
>>
>> This patch is based on some original work completed by:
>>   Niklas Hernaeus <niklas.hernaeus at linaro.org>
>>
>> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
>> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>> Signed-off-by: Niklas Hernaeus <niklas.hernaeus at linaro.org>
> 
> As mentioned on IRC, the order of the S-o-B should be such that the
> person submitting a patch comes last, so this one should be
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Niklas Hernaeus <niklas.hernaeus at linaro.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> or maybe
> 
> Signed-off-by: Niklas Hernaeus <niklas.hernaeus at linaro.org>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Sorry I missed that.

Just for my clarification, how important is that?

Is it re-spin a patch-set important?

> The patch itself looks good to me, but that is not surprising,
> given that I wrote it ;-).


-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From kgene.kim at samsung.com  Wed Mar 14 10:42:06 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:06 -0700
Subject: [PATCH v4 00/12] ARM: EXYNOS: add support new EXYNOS5250
Message-ID: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>

This patch adds support EXYNOS5250 SoC which has two A15 cores
can be used on mobile and tablet devices.

Changes since v3:
- fix external interrupt number
- use local helper function instead of irq_to_gpio()
- fix and expand commit descriptions
- update dts file

Changes since v2:
- update interrupt number declaration for single zImage
  of exynos4 and exynos5
- allow to select for exynos4 and exynos5 together
- add support EINT for exynos4 and exynos5
- add l2 cache initializer for exynos5250

Changes since v1:
- address comments from mailing list
- update the option accordingly common.[ch]
- update clock part
- get rid of static mapping for uart
- add device tree enabled board file(mach-exynos5-dt.c)
- add initial dts file for EXYNOS5250(SoC), SMDK5250(Board)

[PATCH v4 01/12] ARM: EXYNOS: to declare static for mach-exynos/common.c
[PATCH v4 02/12] ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts()
[PATCH v4 03/12] ARM: EXYNOS: add clock part for EXYNOS5250 SoC
[PATCH v4 04/12] ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
[PATCH v4 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
[PATCH v4 06/12] ARM: EXYNOS: add support for EXYNOS5250 SoC
[PATCH v4 07/12] ARM: EXYNOS: add interrupt definitions for EXYNOS5250
[PATCH v4 08/12] ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5
[PATCH v4 09/12] ARM: EXYNOS: add support get_core_count() for EXYNOS5250
[PATCH v4 10/12] ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5 SoCs
[PATCH v4 11/12] ARM: EXYNOS: add support device tree enabled board file for EXYNOS5
[PATCH v4 12/12] ARM: dts: add initial dts file for EXYNOS5250, SMDK5250


From kgene.kim at samsung.com  Wed Mar 14 10:42:07 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:07 -0700
Subject: [PATCH v4 01/12] ARM: EXYNOS: to declare static for
 mach-exynos/common.c
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-2-git-send-email-kgene.kim@samsung.com>

According to commit cc511b8d84d8 ("ARM: 7257/1: EXYNOS: introduce
arch/arm/mach-exynos/common.[ch]"), we don't need to declare extern
for exynos4_map_io(), exynos4_init_clocks(), exynos4_init_uarts(),
and exynos_init(). And the exynos4210_register_clocks() and
exynos4212_register_clocks depend on each SoC not ARCH_EXYNOS4.
So this patch fixed above.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/common.c |   13 +++++++++----
 arch/arm/mach-exynos/common.h |   28 +++++++++++-----------------
 2 files changed, 20 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 34e8190..a1f8a99 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -50,6 +50,11 @@ static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
 
+static void exynos4_map_io(void);
+static void exynos4_init_clocks(int xtal);
+static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+static int exynos_init(void);
+
 static struct cpu_table cpu_ids[] __initdata = {
 	{
 		.idcode		= EXYNOS4210_CPU_ID,
@@ -225,7 +230,7 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
 	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
 
-void __init exynos4_map_io(void)
+static void __init exynos4_map_io(void)
 {
 	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 
@@ -256,7 +261,7 @@ void __init exynos4_map_io(void)
 	s5p_hdmi_setname("exynos4-hdmi");
 }
 
-void __init exynos4_init_clocks(int xtal)
+static void __init exynos4_init_clocks(int xtal)
 {
 	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 
@@ -456,7 +461,7 @@ static int __init exynos4_l2x0_cache_init(void)
 early_initcall(exynos4_l2x0_cache_init);
 #endif
 
-int __init exynos_init(void)
+static int __init exynos_init(void)
 {
 	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 	return device_register(&exynos4_dev);
@@ -464,7 +469,7 @@ int __init exynos_init(void)
 
 /* uart registration process */
 
-void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
 	struct s3c2410_uartcfg *tcfg = cfg;
 	u32 ucnt;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 8c1efe6..b32c6b5 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,39 +12,33 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
+extern struct sys_timer exynos4_timer;
+
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
+void exynos4_restart(char mode, const char *cmd);
 
 #ifdef CONFIG_ARCH_EXYNOS4
 void exynos4_register_clocks(void);
 void exynos4_setup_clocks(void);
 
-void exynos4210_register_clocks(void);
-void exynos4212_register_clocks(void);
-
 #else
 #define exynos4_register_clocks()
 #define exynos4_setup_clocks()
-
-#define exynos4210_register_clocks()
-#define exynos4212_register_clocks()
 #endif
 
-void exynos4_restart(char mode, const char *cmd);
+#ifdef CONFIG_CPU_EXYNOS4210
+void exynos4210_register_clocks(void);
 
-extern struct sys_timer exynos4_timer;
+#else
+#define exynos4210_register_clocks()
+#endif
 
-#ifdef CONFIG_ARCH_EXYNOS
-extern  int exynos_init(void);
-extern void exynos4_map_io(void);
-extern void exynos4_init_clocks(int xtal);
-extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#ifdef CONFIG_SOC_EXYNOS4212
+void exynos4212_register_clocks(void);
 
 #else
-#define exynos4_init_clocks NULL
-#define exynos4_init_uarts NULL
-#define exynos4_map_io NULL
-#define exynos_init NULL
+#define exynos4212_register_clocks()
 #endif
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:42:08 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:08 -0700
Subject: [PATCH v4 02/12] ARM: EXYNOS: use exynos_init_uarts() instead of
 exynos4_init_uarts()
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-3-git-send-email-kgene.kim@samsung.com>

Since exynos4_init_uarts() can be used for EXYNOS5 SoCs,
this patch changes the name of function to exynos_init_uarts().

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/common.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index a1f8a99..02eed29 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,7 +52,7 @@ static const char name_exynos4412[] = "EXYNOS4412";
 
 static void exynos4_map_io(void);
 static void exynos4_init_clocks(int xtal);
-static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
 static struct cpu_table cpu_ids[] __initdata = {
@@ -61,7 +61,7 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.idmask		= EXYNOS4_CPU_MASK,
 		.map_io		= exynos4_map_io,
 		.init_clocks	= exynos4_init_clocks,
-		.init_uarts	= exynos4_init_uarts,
+		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4210,
 	}, {
@@ -69,7 +69,7 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.idmask		= EXYNOS4_CPU_MASK,
 		.map_io		= exynos4_map_io,
 		.init_clocks	= exynos4_init_clocks,
-		.init_uarts	= exynos4_init_uarts,
+		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4212,
 	}, {
@@ -77,7 +77,7 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.idmask		= EXYNOS4_CPU_MASK,
 		.map_io		= exynos4_map_io,
 		.init_clocks	= exynos4_init_clocks,
-		.init_uarts	= exynos4_init_uarts,
+		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4412,
 	},
@@ -469,7 +469,7 @@ static int __init exynos_init(void)
 
 /* uart registration process */
 
-static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
 	struct s3c2410_uartcfg *tcfg = cfg;
 	u32 ucnt;
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:42:10 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:10 -0700
Subject: [PATCH v4 04/12] ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-5-git-send-email-kgene.kim@samsung.com>

In all of Samsung platform, the setup-i2c0.c file for I2C channel 0
is always compiled. So when supporting new SoC,it should be updated
for it. Since EXYNOS5 GPIO will be supported after this, there is no
setup gpio in there now. It will be implemented with that, of course.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/Makefile     |    2 +-
 arch/arm/mach-exynos/setup-i2c0.c |    9 ++++++---
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 995e7cc..2117f02 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -52,7 +52,7 @@ obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
 obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o
 
-obj-$(CONFIG_ARCH_EXYNOS4)		+= setup-i2c0.o
+obj-$(CONFIG_ARCH_EXYNOS)		+= setup-i2c0.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)	+= setup-fimc.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)	+= setup-fimd0.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C1)	+= setup-i2c1.o
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
index d395bd1..b90d94c 100644
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ b/arch/arm/mach-exynos/setup-i2c0.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/setup-i2c0.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com/
  *
  * I2C0 GPIO configuration.
@@ -18,9 +16,14 @@ struct platform_device; /* don't need the contents */
 #include <linux/gpio.h>
 #include <plat/iic.h>
 #include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
+	if (soc_is_exynos5250())
+		/* will be implemented with gpio function */
+		return;
+
 	s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
 			      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:42:09 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:09 -0700
Subject: [PATCH v4 03/12] ARM: EXYNOS: add clock part for EXYNOS5250 SoC
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-4-git-send-email-kgene.kim@samsung.com>

This patch adds clock-exynos5.c for EXYNOS5250 now
and that can be used for other EXYNOS5 SoCs later.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/clock-exynos5.c           | 1247 ++++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/regs-clock.h |   62 ++
 arch/arm/plat-s5p/clock.c                      |   36 +
 arch/arm/plat-samsung/include/plat/s5p-clock.h |    6 +
 4 files changed, 1351 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-exynos/clock-exynos5.c

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644
index 0000000..d013982
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -0,0 +1,1247 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Clock support for EXYNOS5 SoCs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+
+#include "common.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos5_clock_save[] = {
+	/* will be implemented */
+};
+#endif
+
+static struct clk exynos5_clk_sclk_dptxphy = {
+	.name		= "sclk_dptx",
+};
+
+static struct clk exynos5_clk_sclk_hdmi24m = {
+	.name		= "sclk_hdmi24m",
+	.rate		= 24000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmi27m = {
+	.name		= "sclk_hdmi27m",
+	.rate		= 27000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmiphy = {
+	.name		= "sclk_hdmiphy",
+};
+
+static struct clk exynos5_clk_sclk_usbphy = {
+	.name		= "sclk_usbphy",
+	.rate		= 48000000,
+};
+
+static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
+}
+
+static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
+}
+
+static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
+}
+
+static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
+}
+
+static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
+}
+
+static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
+}
+
+static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
+}
+
+static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
+}
+
+static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
+}
+
+static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos5_clk_mout_apll = {
+	.clk	= {
+		.name		= "mout_apll",
+	},
+	.sources = &clk_src_apll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_apll = {
+	.clk	= {
+		.name		= "sclk_apll",
+		.parent		= &exynos5_clk_mout_apll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll = {
+	.clk	= {
+		.name		= "mout_bpll",
+	},
+	.sources = &clk_src_bpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_user_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll_user = {
+	.sources	= exynos5_clk_src_bpll_user_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_user = {
+	.clk	= {
+		.name		= "mout_bpll_user",
+	},
+	.sources = &exynos5_clk_src_bpll_user,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpll = {
+	.clk	= {
+		.name		= "mout_cpll",
+	},
+	.sources = &clk_src_cpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_epll = {
+	.clk	= {
+		.name		= "mout_epll",
+	},
+	.sources = &clk_src_epll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
+};
+
+struct clksrc_clk exynos5_clk_mout_mpll = {
+	.clk = {
+		.name		= "mout_mpll",
+	},
+	.sources = &clk_src_mpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
+};
+
+static struct clk *exynos_clkset_vpllsrc_list[] = {
+	[0] = &clk_fin_vpll,
+	[1] = &exynos5_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos5_clkset_vpllsrc = {
+	.sources	= exynos_clkset_vpllsrc_list,
+	.nr_sources	= ARRAY_SIZE(exynos_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos5_clk_vpllsrc = {
+	.clk	= {
+		.name		= "vpll_src",
+		.enable		= exynos5_clksrc_mask_top_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos5_clkset_vpllsrc,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_sclk_vpll_list[] = {
+	[0] = &exynos5_clk_vpllsrc.clk,
+	[1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_vpll = {
+	.sources	= exynos5_clkset_sclk_vpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_vpll = {
+	.clk	= {
+		.name		= "sclk_vpll",
+	},
+	.sources = &exynos5_clkset_sclk_vpll,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_pixel = {
+	.clk	= {
+		.name		= "sclk_pixel",
+		.parent		= &exynos5_clk_sclk_vpll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
+	[0] = &exynos5_clk_sclk_pixel.clk,
+	[1] = &exynos5_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
+	.sources	= exynos5_clkset_sclk_hdmi_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_hdmi = {
+	.clk	= {
+		.name		= "sclk_hdmi",
+		.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
+		.ctrlbit	= (1 << 20),
+	},
+	.sources = &exynos5_clkset_sclk_hdmi,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk *exynos5_sclk_tv[] = {
+	&exynos5_clk_sclk_pixel,
+	&exynos5_clk_sclk_hdmi,
+};
+
+static struct clk *exynos5_clk_src_mpll_user_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll_user = {
+	.sources	= exynos5_clk_src_mpll_user_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_user = {
+	.clk	= {
+		.name		= "mout_mpll_user",
+	},
+	.sources = &exynos5_clk_src_mpll_user,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_mout_cpu_list[] = {
+	[0] = &exynos5_clk_mout_apll.clk,
+	[1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_cpu = {
+	.sources	= exynos5_clkset_mout_cpu_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpu = {
+	.clk	= {
+		.name		= "mout_cpu",
+	},
+	.sources = &exynos5_clkset_mout_cpu,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_armclk = {
+	.clk	= {
+		.name		= "dout_armclk",
+		.parent		= &exynos5_clk_mout_cpu.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_arm2clk = {
+	.clk	= {
+		.name		= "dout_arm2clk",
+		.parent		= &exynos5_clk_dout_armclk.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
+};
+
+static struct clk exynos5_clk_armclk = {
+	.name		= "armclk",
+	.parent		= &exynos5_clk_dout_arm2clk.clk,
+};
+
+/* Core list of CMU_CDREX side */
+
+static struct clk *exynos5_clkset_cdrex_list[] = {
+	[0] = &exynos5_clk_mout_mpll.clk,
+	[1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_cdrex = {
+	.sources	= exynos5_clkset_cdrex_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_cdrex_list),
+};
+
+static struct clksrc_clk exynos5_clk_cdrex = {
+	.clk	= {
+		.name		= "clk_cdrex",
+	},
+	.sources = &exynos5_clkset_cdrex,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_acp = {
+	.clk	= {
+		.name		= "aclk_acp",
+		.parent		= &exynos5_clk_mout_mpll.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_pclk_acp = {
+	.clk	= {
+		.name		= "pclk_acp",
+		.parent		= &exynos5_clk_aclk_acp.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos5_clkset_aclk_top_list[] = {
+	[0] = &exynos5_clk_mout_mpll_user.clk,
+	[1] = &exynos5_clk_mout_bpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk = {
+	.sources	= exynos5_clkset_aclk_top_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400 = {
+	.clk	= {
+		.name		= "aclk_400",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+};
+
+struct clk *exynos5_clkset_aclk_333_166_list[] = {
+	[0] = &exynos5_clk_mout_cpll.clk,
+	[1] = &exynos5_clk_mout_mpll_user.clk,
+};
+
+struct clksrc_sources exynos5_clkset_aclk_333_166 = {
+	.sources	= exynos5_clkset_aclk_333_166_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_333 = {
+	.clk	= {
+		.name		= "aclk_333",
+	},
+	.sources = &exynos5_clkset_aclk_333_166,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_166 = {
+	.clk	= {
+		.name		= "aclk_166",
+	},
+	.sources = &exynos5_clkset_aclk_333_166,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266 = {
+	.clk	= {
+		.name		= "aclk_266",
+		.parent		= &exynos5_clk_mout_mpll_user.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_200 = {
+	.clk	= {
+		.name		= "aclk_200",
+	},
+	.sources = &exynos5_clkset_aclk,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66_pre = {
+	.clk	= {
+		.name		= "aclk_66_pre",
+		.parent		= &exynos5_clk_mout_mpll_user.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66 = {
+	.clk	= {
+		.name		= "aclk_66",
+		.parent		= &exynos5_clk_aclk_66_pre.clk,
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
+};
+
+static struct clk exynos5_init_clocks_off[] = {
+	{
+		.name		= "timers",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= "rtc",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peris_ctrl,
+		.ctrlbit	= (1 << 20),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.0",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.1",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.2",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= "hsmmc",
+		.devname	= "s3c-sdhci.3",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 15),
+	}, {
+		.name		= "dwmci",
+		.parent		= &exynos5_clk_aclk_200.clk,
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 16),
+	}, {
+		.name		= "sata",
+		.devname	= "ahci",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "sata_phy",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= "sata_phy_i2c",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 25),
+	}, {
+		.name		= "mfc",
+		.devname	= "s5p-mfc",
+		.enable		= exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "hdmi",
+		.devname	= "exynos4-hdmi",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "mixer",
+		.devname	= "s5p-mixer",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 5),
+	}, {
+		.name		= "jpeg",
+		.enable		= exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "dsim0",
+		.enable		= exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 20),
+	}, {
+		.name		= "iis",
+		.devname	= "samsung-i2s.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 21),
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 22),
+	}, {
+		.name		= "pcm",
+		.devname	= "samsung-pcm.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 23),
+	}, {
+		.name		= "spdif",
+		.devname	= "samsung-spdif",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 26),
+	}, {
+		.name		= "ac97",
+		.devname	= "samsung-ac97",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 27),
+	}, {
+		.name		= "usbhost",
+		.enable		= exynos5_clk_ip_fsys_ctrl ,
+		.ctrlbit	= (1 << 18),
+	}, {
+		.name		= "usbotg",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "gps",
+		.enable		= exynos5_clk_ip_gps_ctrl,
+		.ctrlbit	= ((1 << 3) | (1 << 2) | (1 << 0)),
+	}, {
+		.name		= "nfcon",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 22),
+	}, {
+		.name		= "iop",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= ((1 << 30) | (1 << 26) | (1 << 23)),
+	}, {
+		.name		= "core_iop",
+		.enable		= exynos5_clk_ip_core_ctrl,
+		.ctrlbit	= ((1 << 21) | (1 << 3)),
+	}, {
+		.name		= "mcu_iop",
+		.enable		= exynos5_clk_ip_fsys_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.0",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.1",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.2",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.3",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.4",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.5",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.6",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-i2c.7",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 13),
+	}, {
+		.name		= "i2c",
+		.devname	= "s3c2440-hdmiphy-i2c",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 14),
+	}
+};
+
+static struct clk exynos5_init_clocks_on[] = {
+	{
+		.name		= "uart",
+		.devname	= "s5pv210-uart.0",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.1",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.2",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.3",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.4",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= "uart",
+		.devname	= "s5pv210-uart.5",
+		.enable		= exynos5_clk_ip_peric_ctrl,
+		.ctrlbit	= (1 << 5),
+	}
+};
+
+static struct clk exynos5_clk_pdma0 = {
+	.name		= "dma",
+	.devname	= "dma-pl330.0",
+	.enable		= exynos5_clk_ip_fsys_ctrl,
+	.ctrlbit	= (1 << 1),
+};
+
+static struct clk exynos5_clk_pdma1 = {
+	.name		= "dma",
+	.devname	= "dma-pl330.1",
+	.enable		= exynos5_clk_ip_fsys_ctrl,
+	.ctrlbit	= (1 << 1),
+};
+
+static struct clk exynos5_clk_mdma1 = {
+	.name		= "dma",
+	.devname	= "dma-pl330.2",
+	.enable		= exynos5_clk_ip_gen_ctrl,
+	.ctrlbit	= (1 << 4),
+};
+
+struct clk *exynos5_clkset_group_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = NULL,
+	[2] = &exynos5_clk_sclk_hdmi24m,
+	[3] = &exynos5_clk_sclk_dptxphy,
+	[4] = &exynos5_clk_sclk_usbphy,
+	[5] = &exynos5_clk_sclk_hdmiphy,
+	[6] = &exynos5_clk_mout_mpll_user.clk,
+	[7] = &exynos5_clk_mout_epll.clk,
+	[8] = &exynos5_clk_sclk_vpll.clk,
+	[9] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_group = {
+	.sources	= exynos5_clkset_group_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_group_list),
+};
+
+/* Possible clock sources for aclk_266_gscl_sub Mux */
+static struct clk *clk_src_gscl_266_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = &exynos5_clk_aclk_266.clk,
+};
+
+static struct clksrc_sources clk_src_gscl_266 = {
+	.sources	= clk_src_gscl_266_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_gscl_266_list),
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc0 = {
+	.clk		= {
+		.name		= "dout_mmc0",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc1 = {
+	.clk		= {
+		.name		= "dout_mmc1",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc2 = {
+	.clk		= {
+		.name		= "dout_mmc2",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc3 = {
+	.clk		= {
+		.name		= "dout_mmc3",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc4 = {
+	.clk		= {
+		.name		= "dout_mmc4",
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart0 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.0",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart1 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.1",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 4),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart2 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.2",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 8),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart3 = {
+	.clk	= {
+		.name		= "uclk1",
+		.devname	= "exynos4210-uart.3",
+		.enable		= exynos5_clksrc_mask_peric0_ctrl,
+		.ctrlbit	= (1 << 12),
+	},
+	.sources = &exynos5_clkset_group,
+	.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
+	.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.0",
+		.parent		= &exynos5_clk_dout_mmc0.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 0),
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.1",
+		.parent		= &exynos5_clk_dout_mmc1.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 4),
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.2",
+		.parent		= &exynos5_clk_dout_mmc2.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 8),
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
+	.clk	= {
+		.name		= "sclk_mmc",
+		.devname	= "s3c-sdhci.3",
+		.parent		= &exynos5_clk_dout_mmc3.clk,
+		.enable		= exynos5_clksrc_mask_fsys_ctrl,
+		.ctrlbit	= (1 << 12),
+	},
+	.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clksrcs[] = {
+	{
+		.clk	= {
+			.name		= "sclk_dwmci",
+			.parent		= &exynos5_clk_dout_mmc4.clk,
+			.enable		= exynos5_clksrc_mask_fsys_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+	}, {
+		.clk	= {
+			.name		= "sclk_fimd",
+			.devname	= "s3cfb.1",
+			.enable		= exynos5_clksrc_mask_disp1_0_ctrl,
+			.ctrlbit	= (1 << 0),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "aclk_266_gscl",
+		},
+		.sources = &clk_src_gscl_266,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
+	}, {
+		.clk	= {
+			.name		= "sclk_g3d",
+			.devname	= "mali-t604.0",
+			.enable		= exynos5_clk_block_ctrl,
+			.ctrlbit	= (1 << 1),
+		},
+		.sources = &exynos5_clkset_aclk,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+	}, {
+		.clk	= {
+			.name		= "sclk_gscl_wrap",
+			.devname	= "s5p-mipi-csis.0",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_gscl_wrap",
+			.devname	= "s5p-mipi-csis.1",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 28),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_cam0",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 16),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_cam1",
+			.enable		= exynos5_clksrc_mask_gscl_ctrl,
+			.ctrlbit	= (1 << 20),
+		},
+		.sources = &exynos5_clkset_group,
+		.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
+	}, {
+		.clk	= {
+			.name		= "sclk_jpeg",
+			.parent		= &exynos5_clk_mout_cpll.clk,
+		},
+		.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+	},
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos5_sysclks[] = {
+	&exynos5_clk_mout_apll,
+	&exynos5_clk_sclk_apll,
+	&exynos5_clk_mout_bpll,
+	&exynos5_clk_mout_bpll_user,
+	&exynos5_clk_mout_cpll,
+	&exynos5_clk_mout_epll,
+	&exynos5_clk_mout_mpll,
+	&exynos5_clk_mout_mpll_user,
+	&exynos5_clk_vpllsrc,
+	&exynos5_clk_sclk_vpll,
+	&exynos5_clk_mout_cpu,
+	&exynos5_clk_dout_armclk,
+	&exynos5_clk_dout_arm2clk,
+	&exynos5_clk_cdrex,
+	&exynos5_clk_aclk_400,
+	&exynos5_clk_aclk_333,
+	&exynos5_clk_aclk_266,
+	&exynos5_clk_aclk_200,
+	&exynos5_clk_aclk_166,
+	&exynos5_clk_aclk_66_pre,
+	&exynos5_clk_aclk_66,
+	&exynos5_clk_dout_mmc0,
+	&exynos5_clk_dout_mmc1,
+	&exynos5_clk_dout_mmc2,
+	&exynos5_clk_dout_mmc3,
+	&exynos5_clk_dout_mmc4,
+	&exynos5_clk_aclk_acp,
+	&exynos5_clk_pclk_acp,
+};
+
+static struct clk *exynos5_clk_cdev[] = {
+	&exynos5_clk_pdma0,
+	&exynos5_clk_pdma1,
+	&exynos5_clk_mdma1,
+};
+
+static struct clksrc_clk *exynos5_clksrc_cdev[] = {
+	&exynos5_clk_sclk_uart0,
+	&exynos5_clk_sclk_uart1,
+	&exynos5_clk_sclk_uart2,
+	&exynos5_clk_sclk_uart3,
+	&exynos5_clk_sclk_mmc0,
+	&exynos5_clk_sclk_mmc1,
+	&exynos5_clk_sclk_mmc2,
+	&exynos5_clk_sclk_mmc3,
+};
+
+static struct clk_lookup exynos5_clk_lookup[] = {
+	CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
+	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
+	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
+	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
+	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
+	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
+	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
+	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
+	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
+	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+};
+
+static unsigned long exynos5_epll_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+static struct clk *exynos5_clks[] __initdata = {
+	&exynos5_clk_sclk_hdmi27m,
+	&exynos5_clk_sclk_hdmiphy,
+	&clk_fout_bpll,
+	&clk_fout_cpll,
+	&exynos5_clk_armclk,
+};
+
+static u32 epll_div[][6] = {
+	{ 192000000, 0, 48, 3, 1, 0 },
+	{ 180000000, 0, 45, 3, 1, 0 },
+	{  73728000, 1, 73, 3, 3, 47710 },
+	{  67737600, 1, 90, 4, 3, 20762 },
+	{  49152000, 0, 49, 3, 3, 9961 },
+	{  45158400, 0, 45, 3, 3, 10381 },
+	{ 180633600, 0, 45, 3, 1, 10381 },
+};
+
+static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int epll_con, epll_con_k;
+	unsigned int i;
+	unsigned int tmp;
+	unsigned int epll_rate;
+	unsigned int locktime;
+	unsigned int lockcnt;
+
+	/* Return if nothing changed */
+	if (clk->rate == rate)
+		return 0;
+
+	if (clk->parent)
+		epll_rate = clk_get_rate(clk->parent);
+	else
+		epll_rate = clk_ext_xtal_mux.rate;
+
+	if (epll_rate != 24000000) {
+		pr_err("Invalid Clock : recommended clock is 24MHz.\n");
+		return -EINVAL;
+	}
+
+	epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
+	epll_con &= ~(0x1 << 27 | \
+			PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
+			PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+			PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+	for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+		if (epll_div[i][0] == rate) {
+			epll_con_k = epll_div[i][5] << 0;
+			epll_con |= epll_div[i][1] << 27;
+			epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
+			epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
+			epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(epll_div)) {
+		printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	epll_rate /= 1000000;
+
+	/* 3000 max_cycls : specification data */
+	locktime = 3000 / epll_rate * epll_div[i][3];
+	lockcnt = locktime * 10000 / (10000 / epll_rate);
+
+	__raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
+
+	__raw_writel(epll_con, EXYNOS5_EPLL_CON0);
+	__raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
+
+	do {
+		tmp = __raw_readl(EXYNOS5_EPLL_CON0);
+	} while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
+
+	clk->rate = rate;
+
+	return 0;
+}
+
+static struct clk_ops exynos5_epll_ops = {
+	.get_rate = exynos5_epll_get_rate,
+	.set_rate = exynos5_epll_set_rate,
+};
+
+static int xtal_rate;
+
+static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
+{
+	return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
+}
+
+static struct clk_ops exynos5_fout_apll_ops = {
+	.get_rate = exynos5_fout_apll_get_rate,
+};
+
+#ifdef CONFIG_PM
+static int exynos5_clock_suspend(void)
+{
+	s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+
+	return 0;
+}
+
+static void exynos5_clock_resume(void)
+{
+	s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+}
+#else
+#define exynos5_clock_suspend NULL
+#define exynos5_clock_resume NULL
+#endif
+
+struct syscore_ops exynos5_clock_syscore_ops = {
+	.suspend	= exynos5_clock_suspend,
+	.resume		= exynos5_clock_resume,
+};
+
+void __init_or_cpufreq exynos5_setup_clocks(void)
+{
+	struct clk *xtal_clk;
+	unsigned long apll;
+	unsigned long bpll;
+	unsigned long cpll;
+	unsigned long mpll;
+	unsigned long epll;
+	unsigned long vpll;
+	unsigned long vpllsrc;
+	unsigned long xtal;
+	unsigned long armclk;
+	unsigned long mout_cdrex;
+	unsigned long aclk_400;
+	unsigned long aclk_333;
+	unsigned long aclk_266;
+	unsigned long aclk_200;
+	unsigned long aclk_166;
+	unsigned long aclk_66;
+	unsigned int ptr;
+
+	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+	xtal_clk = clk_get(NULL, "xtal");
+	BUG_ON(IS_ERR(xtal_clk));
+
+	xtal = clk_get_rate(xtal_clk);
+
+	xtal_rate = xtal;
+
+	clk_put(xtal_clk);
+
+	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+	apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
+	bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
+	cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
+	mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
+	epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
+			__raw_readl(EXYNOS5_EPLL_CON1));
+
+	vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
+	vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
+			__raw_readl(EXYNOS5_VPLL_CON1));
+
+	clk_fout_apll.ops = &exynos5_fout_apll_ops;
+	clk_fout_bpll.rate = bpll;
+	clk_fout_cpll.rate = cpll;
+	clk_fout_mpll.rate = mpll;
+	clk_fout_epll.rate = epll;
+	clk_fout_vpll.rate = vpll;
+
+	printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
+			"M=%ld, E=%ld V=%ld",
+			apll, bpll, cpll, mpll, epll, vpll);
+
+	armclk = clk_get_rate(&exynos5_clk_armclk);
+	mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
+
+	aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
+	aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
+	aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
+	aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
+	aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
+	aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
+
+	printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
+			"ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
+			"ACLK166=%ld, ACLK66=%ld\n",
+			armclk, mout_cdrex, aclk_400,
+			aclk_333, aclk_266, aclk_200,
+			aclk_166, aclk_66);
+
+
+	clk_fout_epll.ops = &exynos5_epll_ops;
+
+	if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
+		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+				clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
+
+	clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
+	clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
+
+	clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
+	clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
+		s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
+}
+
+void __init exynos5_register_clocks(void)
+{
+	int ptr;
+
+	s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
+		s3c_register_clksrc(exynos5_sysclks[ptr], 1);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
+		s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
+		s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
+
+	s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
+	s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
+
+	s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
+	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
+		s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
+
+	s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+	s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+	clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
+
+	register_syscore_ops(&exynos5_clock_syscore_ops);
+	s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 1e4abd6..e141c1f 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -253,6 +253,68 @@
 #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT		(0)
 #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK		(0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
 
+/* For EXYNOS5250 */
+
+#define EXYNOS5_APLL_CON0			EXYNOS_CLKREG(0x00100)
+#define EXYNOS5_CLKSRC_CPU			EXYNOS_CLKREG(0x00200)
+#define EXYNOS5_CLKDIV_CPU0			EXYNOS_CLKREG(0x00500)
+#define EXYNOS5_MPLL_CON0			EXYNOS_CLKREG(0x04100)
+#define EXYNOS5_CLKSRC_CORE1			EXYNOS_CLKREG(0x04204)
+
+#define EXYNOS5_CLKGATE_IP_CORE			EXYNOS_CLKREG(0x04900)
+
+#define EXYNOS5_CLKDIV_ACP			EXYNOS_CLKREG(0x08500)
+
+#define EXYNOS5_CLKSRC_TOP2			EXYNOS_CLKREG(0x10218)
+#define EXYNOS5_EPLL_CON0			EXYNOS_CLKREG(0x10130)
+#define EXYNOS5_EPLL_CON1			EXYNOS_CLKREG(0x10134)
+#define EXYNOS5_VPLL_CON0			EXYNOS_CLKREG(0x10140)
+#define EXYNOS5_VPLL_CON1			EXYNOS_CLKREG(0x10144)
+#define EXYNOS5_CPLL_CON0			EXYNOS_CLKREG(0x10120)
+
+#define EXYNOS5_CLKSRC_TOP0			EXYNOS_CLKREG(0x10210)
+#define EXYNOS5_CLKSRC_TOP3			EXYNOS_CLKREG(0x1021C)
+#define EXYNOS5_CLKSRC_GSCL			EXYNOS_CLKREG(0x10220)
+#define EXYNOS5_CLKSRC_DISP1_0			EXYNOS_CLKREG(0x1022C)
+#define EXYNOS5_CLKSRC_FSYS			EXYNOS_CLKREG(0x10244)
+#define EXYNOS5_CLKSRC_PERIC0			EXYNOS_CLKREG(0x10250)
+
+#define EXYNOS5_CLKSRC_MASK_TOP			EXYNOS_CLKREG(0x10310)
+#define EXYNOS5_CLKSRC_MASK_GSCL		EXYNOS_CLKREG(0x10320)
+#define EXYNOS5_CLKSRC_MASK_DISP1_0		EXYNOS_CLKREG(0x1032C)
+#define EXYNOS5_CLKSRC_MASK_FSYS		EXYNOS_CLKREG(0x10340)
+#define EXYNOS5_CLKSRC_MASK_PERIC0		EXYNOS_CLKREG(0x10350)
+
+#define EXYNOS5_CLKDIV_TOP0			EXYNOS_CLKREG(0x10510)
+#define EXYNOS5_CLKDIV_TOP1			EXYNOS_CLKREG(0x10514)
+#define EXYNOS5_CLKDIV_GSCL			EXYNOS_CLKREG(0x10520)
+#define EXYNOS5_CLKDIV_DISP1_0			EXYNOS_CLKREG(0x1052C)
+#define EXYNOS5_CLKDIV_GEN			EXYNOS_CLKREG(0x1053C)
+#define EXYNOS5_CLKDIV_FSYS0			EXYNOS_CLKREG(0x10548)
+#define EXYNOS5_CLKDIV_FSYS1			EXYNOS_CLKREG(0x1054C)
+#define EXYNOS5_CLKDIV_FSYS2			EXYNOS_CLKREG(0x10550)
+#define EXYNOS5_CLKDIV_FSYS3			EXYNOS_CLKREG(0x10554)
+#define EXYNOS5_CLKDIV_PERIC0			EXYNOS_CLKREG(0x10558)
+
+#define EXYNOS5_CLKGATE_IP_ACP			EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_GSCL			EXYNOS_CLKREG(0x10920)
+#define EXYNOS5_CLKGATE_IP_DISP1		EXYNOS_CLKREG(0x10928)
+#define EXYNOS5_CLKGATE_IP_MFC			EXYNOS_CLKREG(0x1092C)
+#define EXYNOS5_CLKGATE_IP_GEN			EXYNOS_CLKREG(0x10934)
+#define EXYNOS5_CLKGATE_IP_FSYS			EXYNOS_CLKREG(0x10944)
+#define EXYNOS5_CLKGATE_IP_GPS			EXYNOS_CLKREG(0x1094C)
+#define EXYNOS5_CLKGATE_IP_PERIC		EXYNOS_CLKREG(0x10950)
+#define EXYNOS5_CLKGATE_IP_PERIS		EXYNOS_CLKREG(0x10960)
+#define EXYNOS5_CLKGATE_BLOCK			EXYNOS_CLKREG(0x10980)
+
+#define EXYNOS5_BPLL_CON0			EXYNOS_CLKREG(0x20110)
+#define EXYNOS5_CLKSRC_CDREX			EXYNOS_CLKREG(0x20200)
+#define EXYNOS5_CLKDIV_CDREX			EXYNOS_CLKREG(0x20500)
+
+#define EXYNOS5_EPLL_LOCK			EXYNOS_CLKREG(0x10030)
+
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT		(29)
+
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 963edea..f68a9bb 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -61,6 +61,20 @@ struct clk clk_fout_apll = {
 	.id		= -1,
 };
 
+/* BPLL clock output */
+
+struct clk clk_fout_bpll = {
+	.name		= "fout_bpll",
+	.id		= -1,
+};
+
+/* CPLL clock output */
+
+struct clk clk_fout_cpll = {
+	.name		= "fout_cpll",
+	.id		= -1,
+};
+
 /* MPLL clock output
  * No need .ctrlbit, this is always on
 */
@@ -101,6 +115,28 @@ struct clksrc_sources clk_src_apll = {
 	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
 };
 
+/* Possible clock sources for BPLL Mux */
+static struct clk *clk_src_bpll_list[] = {
+	[0] = &clk_fin_bpll,
+	[1] = &clk_fout_bpll,
+};
+
+struct clksrc_sources clk_src_bpll = {
+	.sources	= clk_src_bpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
+};
+
+/* Possible clock sources for CPLL Mux */
+static struct clk *clk_src_cpll_list[] = {
+	[0] = &clk_fin_cpll,
+	[1] = &clk_fout_cpll,
+};
+
+struct clksrc_sources clk_src_cpll = {
+	.sources	= clk_src_cpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_cpll_list),
+};
+
 /* Possible clock sources for MPLL Mux */
 static struct clk *clk_src_mpll_list[] = {
 	[0] = &clk_fin_mpll,
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 984bf9e..1de4b32 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -18,6 +18,8 @@
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 
 #define clk_fin_apll clk_ext_xtal_mux
+#define clk_fin_bpll clk_ext_xtal_mux
+#define clk_fin_cpll clk_ext_xtal_mux
 #define clk_fin_mpll clk_ext_xtal_mux
 #define clk_fin_epll clk_ext_xtal_mux
 #define clk_fin_dpll clk_ext_xtal_mux
@@ -29,6 +31,8 @@ extern struct clk clk_xusbxti;
 extern struct clk clk_48m;
 extern struct clk s5p_clk_27m;
 extern struct clk clk_fout_apll;
+extern struct clk clk_fout_bpll;
+extern struct clk clk_fout_cpll;
 extern struct clk clk_fout_mpll;
 extern struct clk clk_fout_epll;
 extern struct clk clk_fout_dpll;
@@ -37,6 +41,8 @@ extern struct clk clk_arm;
 extern struct clk clk_vpll;
 
 extern struct clksrc_sources clk_src_apll;
+extern struct clksrc_sources clk_src_bpll;
+extern struct clksrc_sources clk_src_cpll;
 extern struct clksrc_sources clk_src_mpll;
 extern struct clksrc_sources clk_src_epll;
 extern struct clksrc_sources clk_src_dpll;
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:42:11 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:11 -0700
Subject: [PATCH v4 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-6-git-send-email-kgene.kim@samsung.com>

Actually, the base address of uart is different between EXYNOS4
and EXYNOS5 and this patch enables to support uart for EXYNOS4
and EXYNOS5 SoCs at runtime.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/Makefile                   |    1 +
 arch/arm/mach-exynos/common.c                   |    5 +-
 arch/arm/mach-exynos/dev-uart.c                 |   78 +++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/debug-macro.S |    9 ++-
 arch/arm/mach-exynos/include/mach/irqs.h        |   12 ++++
 arch/arm/mach-exynos/include/mach/map.h         |   20 +++---
 arch/arm/mach-exynos/include/mach/uncompress.h  |   17 ++++--
 arch/arm/plat-s5p/Kconfig                       |    4 +
 arch/arm/plat-s5p/Makefile                      |    3 +-
 arch/arm/plat-samsung/include/plat/devs.h       |    2 +
 arch/arm/plat-samsung/include/plat/uncompress.h |    2 +
 11 files changed, 135 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm/mach-exynos/dev-uart.c

diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 2117f02..f8a3770 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o
 
 # device support
 
+obj-y					+= dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_PD)		+= dev-pd.o
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 02eed29..4a82cf0 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -477,7 +477,10 @@ static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 	for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 		tcfg->has_fracval = 1;
 
-	s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
+	if (soc_is_exynos5250())
+		s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
+	else
+		s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 }
 
 static DEFINE_SPINLOCK(eint_lock);
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
new file mode 100644
index 0000000..2e85c02
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Base EXYNOS UART resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+#define EXYNOS_UART_RESOURCE(_series, _nr)	\
+static struct resource exynos##_series##_uart##_nr##_resource[] = {	\
+	[0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART),	\
+	[1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr),	\
+};
+
+EXYNOS_UART_RESOURCE(4, 0)
+EXYNOS_UART_RESOURCE(4, 1)
+EXYNOS_UART_RESOURCE(4, 2)
+EXYNOS_UART_RESOURCE(4, 3)
+
+struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
+	[0] = {
+		.resources	= exynos4_uart0_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart0_resource),
+	},
+	[1] = {
+		.resources	= exynos4_uart1_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart1_resource),
+	},
+	[2] = {
+		.resources	= exynos4_uart2_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart2_resource),
+	},
+	[3] = {
+		.resources	= exynos4_uart3_resource,
+		.nr_resources	= ARRAY_SIZE(exynos4_uart3_resource),
+	},
+};
+
+EXYNOS_UART_RESOURCE(5, 0)
+EXYNOS_UART_RESOURCE(5, 1)
+EXYNOS_UART_RESOURCE(5, 2)
+EXYNOS_UART_RESOURCE(5, 3)
+
+struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
+	[0] = {
+		.resources	= exynos5_uart0_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart0_resource),
+	},
+	[1] = {
+		.resources	= exynos5_uart1_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart0_resource),
+	},
+	[2] = {
+		.resources	= exynos5_uart2_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart2_resource),
+	},
+	[3] = {
+		.resources	= exynos5_uart3_resource,
+		.nr_resources	= ARRAY_SIZE(exynos5_uart3_resource),
+	},
+};
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
index 6cacf16..6c857ff 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -21,8 +21,13 @@
 	 */
 
 	.macro addruart, rp, rv, tmp
-		ldr	\rp, = S3C_PA_UART
-		ldr	\rv, = S3C_VA_UART
+		mov	\rp, #0x10000000
+		ldr	\rp, [\rp, #0x0]
+		and	\rp, \rp, #0xf00000
+		teq	\rp, #0x500000		@@ EXYNOS5
+		ldreq	\rp, =EXYNOS5_PA_UART
+		movne	\rp, #EXYNOS4_PA_UART	@@ EXYNOS4
+		ldr	\rv, =S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
 		add	\rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
 		add	\rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 1d401c9..f78070e 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -173,4 +173,16 @@
 /* Set the default NR_IRQS */
 #define NR_IRQS			(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
 
+#define EXYNOS4_IRQ_UART0		IRQ_SPI(52)
+#define EXYNOS4_IRQ_UART1		IRQ_SPI(53)
+#define EXYNOS4_IRQ_UART2		IRQ_SPI(54)
+#define EXYNOS4_IRQ_UART3		IRQ_SPI(55)
+#define EXYNOS4_IRQ_UART4		IRQ_SPI(56)
+
+#define EXYNOS5_IRQ_UART0		IRQ_SPI(51)
+#define EXYNOS5_IRQ_UART1		IRQ_SPI(52)
+#define EXYNOS5_IRQ_UART2		IRQ_SPI(53)
+#define EXYNOS5_IRQ_UART3		IRQ_SPI(54)
+#define EXYNOS5_IRQ_UART4		IRQ_SPI(55)
+
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 2ad4e9c..ea513c6 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -153,7 +153,6 @@
 #define S3C_PA_IIC7			EXYNOS4_PA_IIC(7)
 #define S3C_PA_RTC			EXYNOS4_PA_RTC
 #define S3C_PA_WDT			EXYNOS4_PA_WATCHDOG
-#define S3C_PA_UART			EXYNOS4_PA_UART
 #define S3C_PA_SPI0			EXYNOS4_PA_SPI0
 #define S3C_PA_SPI1			EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2			EXYNOS4_PA_SPI2
@@ -182,15 +181,18 @@
 
 /* Compatibility UART */
 
-#define S3C_VA_UARTx(x)			(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define EXYNOS4_PA_UART0		0x13800000
+#define EXYNOS4_PA_UART1		0x13810000
+#define EXYNOS4_PA_UART2		0x13820000
+#define EXYNOS4_PA_UART3		0x13830000
+#define EXYNOS4_SZ_UART			SZ_256
 
-#define S5P_PA_UART(x)			(EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0			S5P_PA_UART(0)
-#define S5P_PA_UART1			S5P_PA_UART(1)
-#define S5P_PA_UART2			S5P_PA_UART(2)
-#define S5P_PA_UART3			S5P_PA_UART(3)
-#define S5P_PA_UART4			S5P_PA_UART(4)
+#define EXYNOS5_PA_UART0		0x12C00000
+#define EXYNOS5_PA_UART1		0x12C10000
+#define EXYNOS5_PA_UART2		0x12C20000
+#define EXYNOS5_PA_UART3		0x12C30000
+#define EXYNOS5_SZ_UART			SZ_256
 
-#define S5P_SZ_UART			SZ_256
+#define S3C_VA_UARTx(x)			(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 21d97bc..493f4f3 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * EXYNOS4 - uncompress code
+ * EXYNOS - uncompress code
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,12 +12,20 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H __FILE__
 
+#include <asm/mach-types.h>
+
 #include <mach/map.h>
+
+volatile u8 *uart_base;
+
 #include <plat/uncompress.h>
 
 static void arch_detect_cpu(void)
 {
-	/* we do not need to do any cpu detection here at the moment. */
+	if (machine_is_smdk5250())
+		uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+	else
+		uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 
 	/*
 	 * For preventing FIFO overrun or infinite loop of UART console,
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 8167ce6..10e235cc7 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -40,6 +40,10 @@ config S5P_HRT
 	help
 	  Use the High Resolution timer support
 
+config S5P_DEV_UART
+	def_bool y
+	depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
+
 config S5P_PM
 	bool
 	help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 30d8c30..4bd8241 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -12,7 +12,6 @@ obj-				:=
 
 # Core files
 
-obj-y				+= dev-uart.o
 obj-y				+= clock.o
 obj-y				+= irq.o
 obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
@@ -23,5 +22,7 @@ obj-$(CONFIG_S5P_SLEEP)		+= sleep.o
 obj-$(CONFIG_S5P_HRT) 		+= s5p-time.o
 
 # devices
+
+obj-$(CONFIG_S5P_DEV_UART)	+= dev-uart.o
 obj-$(CONFIG_S5P_DEV_MFC)	+= dev-mfc.o
 obj-$(CONFIG_S5P_SETUP_MIPIPHY)	+= setup-mipiphy.o
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 4214ea0..32cc67e 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -26,6 +26,8 @@ struct s3c24xx_uart_resources {
 extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
 extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
 extern struct s3c24xx_uart_resources s5p_uart_resources[];
+extern struct s3c24xx_uart_resources exynos4_uart_resources[];
+extern struct s3c24xx_uart_resources exynos5_uart_resources[];
 
 extern struct platform_device *s3c24xx_uart_devs[];
 extern struct platform_device *s3c24xx_uart_src[];
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index ee48e12..7e068d1 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -37,7 +37,9 @@ static void arch_detect_cpu(void);
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX	 (14)
 
+#ifdef S3C_PA_UART
 #define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
+#endif
 
 static __inline__ void
 uart_wr(unsigned int reg, unsigned int val)
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:42:12 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:12 -0700
Subject: [PATCH v4 06/12] ARM: EXYNOS: add support for EXYNOS5250 SoC
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-7-git-send-email-kgene.kim@samsung.com>

This patch add support for EXYNOS5250 SoC has two Cortex-A15 cores.
Since actually, most codes in mach-exynos/ are used commonly for
EXYNOS4 and EXYNOS5 the EXYNOS5/EXYNOS5250 has been implemented
in mach-exynos/.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/Makefile                            |    1 +
 arch/arm/mach-exynos/common.c                |  191 ++++++++++++++++++++++++--
 arch/arm/mach-exynos/common.h                |   11 ++
 arch/arm/mach-exynos/include/mach/map.h      |   21 +++-
 arch/arm/mach-exynos/include/mach/regs-pmu.h |    1 +
 arch/arm/plat-s5p/Kconfig                    |    4 +-
 arch/arm/plat-samsung/include/plat/cpu.h     |   10 ++
 7 files changed, 223 insertions(+), 16 deletions(-)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1683bfb..a826ffc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0)		:= s5p64x0
 machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100
 machine-$(CONFIG_ARCH_S5PV210)		:= s5pv210
 machine-$(CONFIG_ARCH_EXYNOS4)		:= exynos
+machine-$(CONFIG_ARCH_EXYNOS5)		:= exynos
 machine-$(CONFIG_ARCH_SA1100)		:= sa1100
 machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4a82cf0..7fdb139 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -49,9 +49,12 @@
 static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
+static const char name_exynos5250[] = "EXYNOS5250";
 
 static void exynos4_map_io(void);
+static void exynos5_map_io(void);
 static void exynos4_init_clocks(int xtal);
+static void exynos5_init_clocks(int xtal);
 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
@@ -80,6 +83,14 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.init_uarts	= exynos_init_uarts,
 		.init		= exynos_init,
 		.name		= name_exynos4412,
+	}, {
+		.idcode		= EXYNOS5250_SOC_ID,
+		.idmask		= EXYNOS5_SOC_MASK,
+		.map_io		= exynos5_map_io,
+		.init_clocks	= exynos5_init_clocks,
+		.init_uarts	= exynos_init_uarts,
+		.init		= exynos_init,
+		.name		= name_exynos5250,
 	},
 };
 
@@ -88,10 +99,14 @@ static struct cpu_table cpu_ids[] __initdata = {
 static struct map_desc exynos_iodesc[] __initdata = {
 	{
 		.virtual	= (unsigned long)S5P_VA_CHIPID,
-		.pfn		= __phys_to_pfn(EXYNOS4_PA_CHIPID),
+		.pfn		= __phys_to_pfn(EXYNOS_PA_CHIPID),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
-	}, {
+	},
+};
+
+static struct map_desc exynos4_iodesc[] __initdata = {
+	{
 		.virtual	= (unsigned long)S3C_VA_SYS,
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSCON),
 		.length		= SZ_64K,
@@ -141,11 +156,7 @@ static struct map_desc exynos_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_UART),
 		.length		= SZ_512K,
 		.type		= MT_DEVICE,
-	},
-};
-
-static struct map_desc exynos4_iodesc[] __initdata = {
-	{
+	}, {
 		.virtual	= (unsigned long)S5P_VA_CMU,
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),
 		.length		= SZ_128K,
@@ -206,11 +217,80 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
 	},
 };
 
+static struct map_desc exynos5_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S3C_VA_SYS,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSCON),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_TIMER,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_TIMER),
+		.length		= SZ_16K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SROMC,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SROMC),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_SYSRAM,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSRAM),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_CMU,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),
+		.length		= 144 * SZ_1K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_PMU,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_COMBINER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_UART,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_UART),
+		.length		= SZ_512K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
+		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
+		.length		= SZ_64K,
+		.type		= MT_DEVICE,
+	},
+};
+
 void exynos4_restart(char mode, const char *cmd)
 {
 	__raw_writel(0x1, S5P_SWRESET);
 }
 
+void exynos5_restart(char mode, const char *cmd)
+{
+	__raw_writel(0x1, EXYNOS_SWRESET);
+}
+
 /*
  * exynos_map_io
  *
@@ -261,6 +341,16 @@ static void __init exynos4_map_io(void)
 	s5p_hdmi_setname("exynos4-hdmi");
 }
 
+static void __init exynos5_map_io(void)
+{
+	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+
+	/* The I2C bus controllers are directly compatible with s3c2440 */
+	s3c_i2c0_setname("s3c2440-i2c");
+	s3c_i2c1_setname("s3c2440-i2c");
+	s3c_i2c2_setname("s3c2440-i2c");
+}
+
 static void __init exynos4_init_clocks(int xtal)
 {
 	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -277,6 +367,17 @@ static void __init exynos4_init_clocks(int xtal)
 	exynos4_setup_clocks();
 }
 
+static void __init exynos5_init_clocks(int xtal)
+{
+	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+	s3c24xx_register_baseclocks(xtal);
+	s5p_register_clocks(xtal);
+
+	exynos5_register_clocks();
+	exynos5_setup_clocks();
+}
+
 #define COMBINER_ENABLE_SET	0x0
 #define COMBINER_ENABLE_CLEAR	0x4
 #define COMBINER_INT_STATUS	0xC
@@ -420,24 +521,59 @@ void __init exynos4_init_irq(void)
 	s5p_init_irq(NULL, 0);
 }
 
+void __init exynos5_init_irq(void)
+{
+	int irq;
+
+	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+
+	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+				COMBINER_IRQ(irq, 0));
+		combiner_cascade_irq(irq, IRQ_SPI(irq));
+	}
+
+	/*
+	 * The parameters of s5p_init_irq() are for VIC init.
+	 * Theses parameters should be NULL and 0 because EXYNOS4
+	 * uses GIC instead of VIC.
+	 */
+	s5p_init_irq(NULL, 0);
+}
+
 struct bus_type exynos4_subsys = {
 	.name		= "exynos4-core",
 	.dev_name	= "exynos4-core",
 };
 
+struct bus_type exynos5_subsys = {
+	.name		= "exynos5-core",
+	.dev_name	= "exynos5-core",
+};
+
 static struct device exynos4_dev = {
 	.bus	= &exynos4_subsys,
 };
 
-static int __init exynos4_core_init(void)
+static struct device exynos5_dev = {
+	.bus	= &exynos5_subsys,
+};
+
+static int __init exynos_core_init(void)
 {
-	return subsys_system_register(&exynos4_subsys, NULL);
+	if (soc_is_exynos5250())
+		return subsys_system_register(&exynos5_subsys, NULL);
+	else
+		return subsys_system_register(&exynos4_subsys, NULL);
 }
-core_initcall(exynos4_core_init);
+core_initcall(exynos_core_init);
 
 #ifdef CONFIG_CACHE_L2X0
 static int __init exynos4_l2x0_cache_init(void)
 {
+	if (soc_is_exynos5250())
+		return 0;
+
 	/* TAG, Data Latency Control: 2cycle */
 	__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 
@@ -457,14 +593,42 @@ static int __init exynos4_l2x0_cache_init(void)
 
 	return 0;
 }
-
 early_initcall(exynos4_l2x0_cache_init);
 #endif
 
+static int __init exynos5_l2_cache_init(void)
+{
+	unsigned int val;
+
+	if (!soc_is_exynos5250())
+		return 0;
+
+	asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+		     "bic %0, %0, #(1 << 2)\n"	/* cache disable */
+		     "mcr p15, 0, %0, c1, c0, 0\n"
+		     "mrc p15, 1, %0, c9, c0, 2\n"
+		     : "=r"(val));
+
+	val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
+
+	asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
+	asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
+		     "orr %0, %0, #(1 << 2)\n"	/* cache enable */
+		     "mcr p15, 0, %0, c1, c0, 0\n"
+		     : : "r"(val));
+
+	return 0;
+}
+early_initcall(exynos5_l2_cache_init);
+
 static int __init exynos_init(void)
 {
 	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
-	return device_register(&exynos4_dev);
+
+	if (soc_is_exynos5250())
+		return device_register(&exynos5_dev);
+	else
+		return device_register(&exynos4_dev);
 }
 
 /* uart registration process */
@@ -673,6 +837,9 @@ static int __init exynos4_init_irq_eint(void)
 {
 	int irq;
 
+	if (soc_is_exynos5250())
+		return 0;
+
 	for (irq = 0 ; irq <= 31 ; irq++) {
 		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
 					 handle_level_irq);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index b32c6b5..677b546 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -16,7 +16,9 @@ extern struct sys_timer exynos4_timer;
 
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
+void exynos5_init_irq(void);
 void exynos4_restart(char mode, const char *cmd);
+void exynos5_restart(char mode, const char *cmd);
 
 #ifdef CONFIG_ARCH_EXYNOS4
 void exynos4_register_clocks(void);
@@ -27,6 +29,15 @@ void exynos4_setup_clocks(void);
 #define exynos4_setup_clocks()
 #endif
 
+#ifdef CONFIG_ARCH_EXYNOS5
+void exynos5_register_clocks(void);
+void exynos5_setup_clocks(void);
+
+#else
+#define exynos5_register_clocks()
+#define exynos5_setup_clocks()
+#endif
+
 #ifdef CONFIG_CPU_EXYNOS4210
 void exynos4210_register_clocks(void);
 
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index ea513c6..bf90bb0 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -25,6 +25,7 @@
 
 #define EXYNOS4_PA_SYSRAM0		0x02025000
 #define EXYNOS4_PA_SYSRAM1		0x02020000
+#define EXYNOS5_PA_SYSRAM		0x02020000
 
 #define EXYNOS4_PA_FIMC0		0x11800000
 #define EXYNOS4_PA_FIMC1		0x11810000
@@ -44,14 +45,23 @@
 #define EXYNOS4_PA_ONENAND		0x0C000000
 #define EXYNOS4_PA_ONENAND_DMA		0x0C600000
 
-#define EXYNOS4_PA_CHIPID		0x10000000
+#define EXYNOS_PA_CHIPID		0x10000000
 
 #define EXYNOS4_PA_SYSCON		0x10010000
+#define EXYNOS5_PA_SYSCON		0x10050100
+
 #define EXYNOS4_PA_PMU			0x10020000
+#define EXYNOS5_PA_PMU			0x10040000
+
 #define EXYNOS4_PA_CMU			0x10030000
+#define EXYNOS5_PA_CMU			0x10010000
 
 #define EXYNOS4_PA_SYSTIMER		0x10050000
+#define EXYNOS5_PA_SYSTIMER		0x101C0000
+
 #define EXYNOS4_PA_WATCHDOG		0x10060000
+#define EXYNOS5_PA_WATCHDOG		0x101D0000
+
 #define EXYNOS4_PA_RTC			0x10070000
 
 #define EXYNOS4_PA_KEYPAD		0x100A0000
@@ -59,9 +69,12 @@
 #define EXYNOS4_PA_DMC0			0x10400000
 
 #define EXYNOS4_PA_COMBINER		0x10440000
+#define EXYNOS5_PA_COMBINER		0x10440000
 
 #define EXYNOS4_PA_GIC_CPU		0x10480000
 #define EXYNOS4_PA_GIC_DIST		0x10490000
+#define EXYNOS5_PA_GIC_CPU		0x10480000
+#define EXYNOS5_PA_GIC_DIST		0x10490000
 
 #define EXYNOS4_PA_COREPERI		0x10500000
 #define EXYNOS4_PA_TWD			0x10500600
@@ -92,7 +105,6 @@
 #define EXYNOS4_PA_SPI1			0x13930000
 #define EXYNOS4_PA_SPI2			0x13940000
 
-
 #define EXYNOS4_PA_GPIO1		0x11400000
 #define EXYNOS4_PA_GPIO2		0x11000000
 #define EXYNOS4_PA_GPIO3		0x03860000
@@ -110,6 +122,7 @@
 #define EXYNOS4_PA_SATAPHY_CTRL		0x126B0000
 
 #define EXYNOS4_PA_SROMC		0x12570000
+#define EXYNOS5_PA_SROMC		0x12250000
 
 #define EXYNOS4_PA_EHCI			0x12580000
 #define EXYNOS4_PA_OHCI			0x12590000
@@ -117,6 +130,7 @@
 #define EXYNOS4_PA_MFC			0x13400000
 
 #define EXYNOS4_PA_UART			0x13800000
+#define EXYNOS5_PA_UART			0x12C00000
 
 #define EXYNOS4_PA_VP			0x12C00000
 #define EXYNOS4_PA_MIXER		0x12C10000
@@ -125,6 +139,7 @@
 #define EXYNOS4_PA_IIC_HDMIPHY		0x138E0000
 
 #define EXYNOS4_PA_IIC(x)		(0x13860000 + ((x) * 0x10000))
+#define EXYNOS5_PA_IIC(x)		(0x12C60000 + ((x) * 0x10000))
 
 #define EXYNOS4_PA_ADC			0x13910000
 #define EXYNOS4_PA_ADC1			0x13911000
@@ -134,8 +149,10 @@
 #define EXYNOS4_PA_SPDIF		0x139B0000
 
 #define EXYNOS4_PA_TIMER		0x139D0000
+#define EXYNOS5_PA_TIMER		0x12DD0000
 
 #define EXYNOS4_PA_SDRAM		0x40000000
+#define EXYNOS5_PA_SDRAM		0x40000000
 
 /* Compatibiltiy Defines */
 
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4fff8e9..4c53f38 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
 #define S5P_USE_STANDBYWFE_ISP_ARM		(1 << 26)
 
 #define S5P_SWRESET				S5P_PMUREG(0x0400)
+#define EXYNOS_SWRESET				S5P_PMUREG(0x0400)
 
 #define S5P_WAKEUP_STAT				S5P_PMUREG(0x0600)
 #define S5P_EINT_WAKEUP_MASK			S5P_PMUREG(0x0604)
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 10e235cc7..88795ea 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -9,8 +9,8 @@ config PLAT_S5P
 	bool
 	depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
 	default y
-	select ARM_VIC if !ARCH_EXYNOS4
-	select ARM_GIC if ARCH_EXYNOS4
+	select ARM_VIC if !ARCH_EXYNOS
+	select ARM_GIC if ARCH_EXYNOS
 	select GIC_NON_BANKED if ARCH_EXYNOS4
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 73cb3cf..787ceac 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -42,6 +42,9 @@ extern unsigned long samsung_cpu_id;
 #define EXYNOS4412_CPU_ID	0xE4412200
 #define EXYNOS4_CPU_MASK	0xFFFE0000
 
+#define EXYNOS5250_SOC_ID	0x43520000
+#define EXYNOS5_SOC_MASK	0xFFFFF000
+
 #define IS_SAMSUNG_CPU(name, id, mask)		\
 static inline int is_samsung_##name(void)	\
 {						\
@@ -58,6 +61,7 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
 
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
     defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -120,6 +124,12 @@ IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 #define EXYNOS4210_REV_1_0	(0x10)
 #define EXYNOS4210_REV_1_1	(0x11)
 
+#if defined(CONFIG_SOC_EXYNOS5250)
+# define soc_is_exynos5250()	is_samsung_exynos5250()
+#else
+# define soc_is_exynos5250()	0
+#endif
+
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 
 #ifndef MHZ
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:42:14 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:14 -0700
Subject: [PATCH v4 08/12] ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-9-git-send-email-kgene.kim@samsung.com>

From: Eunki Kim <eunki_kim at samsung.com>

The GPIOs of EXYNOS4 and EXYNOS5 are changed to use
ioremap instead of static mapping. It alse causes the
change of external interrupt IO mapping. This patch
changes EXYNOS4 to EXYNOS for common use and changes
EINT_x macros for supporting dynamic IO mapping.

Signed-off-by: Eunki Kim <eunki_kim at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/common.c                 |  147 ++++++++++++++++---------
 arch/arm/mach-exynos/include/mach/regs-gpio.h |   20 ++--
 2 files changed, 105 insertions(+), 62 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 4ef0cb5..cbbaca5 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -665,10 +665,60 @@ static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 		s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 }
 
+static void __iomem *exynos_eint_base;
+
 static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
 
+static inline int exynos4_irq_to_gpio(unsigned int irq)
+{
+	if (irq < IRQ_EINT(0))
+		return -EINVAL;
+
+	irq -= IRQ_EINT(0);
+	if (irq < 8)
+		return EXYNOS4_GPX0(irq);
+
+	irq -= 8;
+	if (irq < 8)
+		return EXYNOS4_GPX1(irq);
+
+	irq -= 8;
+	if (irq < 8)
+		return EXYNOS4_GPX2(irq);
+
+	irq -= 8;
+	if (irq < 8)
+		return EXYNOS4_GPX3(irq);
+
+	return -EINVAL;
+}
+
+static inline int exynos5_irq_to_gpio(unsigned int irq)
+{
+	if (irq < IRQ_EINT(0))
+		return -EINVAL;
+
+	irq -= IRQ_EINT(0);
+	if (irq < 8)
+		return EXYNOS5_GPX0(irq);
+
+	irq -= 8;
+	if (irq < 8)
+		return EXYNOS5_GPX1(irq);
+
+	irq -= 8;
+	if (irq < 8)
+		return EXYNOS5_GPX2(irq);
+
+	irq -= 8;
+	if (irq < 8)
+		return EXYNOS5_GPX3(irq);
+
+	return -EINVAL;
+}
+
 static unsigned int exynos4_eint0_15_src_int[16] = {
 	EXYNOS4_IRQ_EINT0,
 	EXYNOS4_IRQ_EINT1,
@@ -706,41 +756,41 @@ static unsigned int exynos5_eint0_15_src_int[16] = {
 	EXYNOS5_IRQ_EINT14,
 	EXYNOS5_IRQ_EINT15,
 };
-static inline void exynos4_irq_eint_mask(struct irq_data *data)
+static inline void exynos_irq_eint_mask(struct irq_data *data)
 {
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-	mask |= eint_irq_to_bit(data->irq);
-	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
+	mask |= EINT_OFFSET_BIT(data->irq);
+	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 	spin_unlock(&eint_lock);
 }
 
-static void exynos4_irq_eint_unmask(struct irq_data *data)
+static void exynos_irq_eint_unmask(struct irq_data *data)
 {
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-	mask &= ~(eint_irq_to_bit(data->irq));
-	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
+	mask &= ~(EINT_OFFSET_BIT(data->irq));
+	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 	spin_unlock(&eint_lock);
 }
 
-static inline void exynos4_irq_eint_ack(struct irq_data *data)
+static inline void exynos_irq_eint_ack(struct irq_data *data)
 {
-	__raw_writel(eint_irq_to_bit(data->irq),
-		     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+	__raw_writel(EINT_OFFSET_BIT(data->irq),
+		     EINT_PEND(exynos_eint_base, data->irq));
 }
 
-static void exynos4_irq_eint_maskack(struct irq_data *data)
+static void exynos_irq_eint_maskack(struct irq_data *data)
 {
-	exynos4_irq_eint_mask(data);
-	exynos4_irq_eint_ack(data);
+	exynos_irq_eint_mask(data);
+	exynos_irq_eint_ack(data);
 }
 
-static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
+static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
 	int offs = EINT_OFFSET(data->irq);
 	int shift;
@@ -777,39 +827,27 @@ static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
 	mask = 0x7 << shift;
 
 	spin_lock(&eint_lock);
-	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 	ctrl &= ~mask;
 	ctrl |= newvalue << shift;
-	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 	spin_unlock(&eint_lock);
 
-	switch (offs) {
-	case 0 ... 7:
-		s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
-		break;
-	case 8 ... 15:
-		s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
-		break;
-	case 16 ... 23:
-		s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
-		break;
-	case 24 ... 31:
-		s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
-		break;
-	default:
-		printk(KERN_ERR "No such irq number %d", offs);
-	}
+	if (soc_is_exynos5250())
+		s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
+	else
+		s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 
 	return 0;
 }
 
-static struct irq_chip exynos4_irq_eint = {
-	.name		= "exynos4-eint",
-	.irq_mask	= exynos4_irq_eint_mask,
-	.irq_unmask	= exynos4_irq_eint_unmask,
-	.irq_mask_ack	= exynos4_irq_eint_maskack,
-	.irq_ack	= exynos4_irq_eint_ack,
-	.irq_set_type	= exynos4_irq_eint_set_type,
+static struct irq_chip exynos_irq_eint = {
+	.name		= "exynos-eint",
+	.irq_mask	= exynos_irq_eint_mask,
+	.irq_unmask	= exynos_irq_eint_unmask,
+	.irq_mask_ack	= exynos_irq_eint_maskack,
+	.irq_ack	= exynos_irq_eint_ack,
+	.irq_set_type	= exynos_irq_eint_set_type,
 #ifdef CONFIG_PM
 	.irq_set_wake	= s3c_irqext_wake,
 #endif
@@ -824,12 +862,12 @@ static struct irq_chip exynos4_irq_eint = {
  *
  * Each EINT pend/mask registers handle eight of them.
  */
-static inline void exynos4_irq_demux_eint(unsigned int start)
+static inline void exynos_irq_demux_eint(unsigned int start)
 {
 	unsigned int irq;
 
-	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
-	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+	u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
+	u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 
 	status &= ~mask;
 	status &= 0xff;
@@ -841,12 +879,12 @@ static inline void exynos4_irq_demux_eint(unsigned int start)
 	}
 }
 
-static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_get_chip(irq);
 	chained_irq_enter(chip, desc);
-	exynos4_irq_demux_eint(IRQ_EINT(16));
-	exynos4_irq_demux_eint(IRQ_EINT(24));
+	exynos_irq_demux_eint(IRQ_EINT(16));
+	exynos_irq_demux_eint(IRQ_EINT(24));
 	chained_irq_exit(chip, desc);
 }
 
@@ -867,20 +905,27 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
-static int __init exynos4_init_irq_eint(void)
+static int __init exynos_init_irq_eint(void)
 {
 	int irq;
 
 	if (soc_is_exynos5250())
-		return 0;
+		exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
+	else
+		exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
+
+	if (exynos_eint_base == NULL) {
+		pr_err("unable to ioremap for EINT base address\n");
+		return -ENOMEM;
+	}
 
 	for (irq = 0 ; irq <= 31 ; irq++) {
-		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
+		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 					 handle_level_irq);
 		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 	}
 
-	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 
 	for (irq = 0 ; irq <= 15 ; irq++) {
 		eint0_15_data[irq] = IRQ_EINT(irq);
@@ -900,4 +945,4 @@ static int __init exynos4_init_irq_eint(void)
 
 	return 0;
 }
-arch_initcall(exynos4_init_irq_eint);
+arch_initcall(exynos_init_irq_eint);
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index 1401b21..e4b5b60 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -16,6 +16,15 @@
 #include <mach/map.h>
 #include <mach/irqs.h>
 
+#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
+#define EINT_CON(b, x)			(b + 0xE00 + (EINT_REG_NR(x) * 4))
+#define EINT_FLTCON(b, x)		(b + 0xE80 + (EINT_REG_NR(x) * 4))
+#define EINT_MASK(b, x)			(b + 0xF00 + (EINT_REG_NR(x) * 4))
+#define EINT_PEND(b, x)			(b + 0xF40 + (EINT_REG_NR(x) * 4))
+
+#define EINT_OFFSET_BIT(x)		(1 << (EINT_OFFSET(x) & 0x7))
+
+/* compatibility for plat-s5p/irq-pm.c */
 #define EXYNOS4_EINT40CON		(S5P_VA_GPIO2 + 0xE00)
 #define S5P_EINT_CON(x)			(EXYNOS4_EINT40CON + ((x) * 0x4))
 
@@ -28,15 +37,4 @@
 #define EXYNOS4_EINT40PEND		(S5P_VA_GPIO2 + 0xF40)
 #define S5P_EINT_PEND(x)		(EXYNOS4_EINT40PEND + ((x) * 0x4))
 
-#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
-
-#define eint_irq_to_bit(irq)		(1 << (EINT_OFFSET(irq) & 0x7))
-
-#define EINT_MODE			S3C_GPIO_SFN(0xf)
-
-#define EINT_GPIO_0(x)			EXYNOS4_GPX0(x)
-#define EINT_GPIO_1(x)			EXYNOS4_GPX1(x)
-#define EINT_GPIO_2(x)			EXYNOS4_GPX2(x)
-#define EINT_GPIO_3(x)			EXYNOS4_GPX3(x)
-
 #endif /* __ASM_ARCH_REGS_GPIO_H */
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:42:13 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:13 -0700
Subject: [PATCH v4 07/12] ARM: EXYNOS: add interrupt definitions for EXYNOS5250
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-8-git-send-email-kgene.kim@samsung.com>

This patch adds the interrupt definitions for EXYNOS5250 at
<mach/irqs.h> file and it is needed for EXYNOS5250 SoC.
As a note, for single zImage of EXYNOS4 and EXYNOS5, prefix
of EXYNOS4_ and EXYNOS5_ has been added.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/common.c            |  101 ++++--
 arch/arm/mach-exynos/dev-ahci.c          |    4 +-
 arch/arm/mach-exynos/dev-audio.c         |    4 +-
 arch/arm/mach-exynos/dma.c               |    6 +-
 arch/arm/mach-exynos/include/mach/irqs.h |  587 ++++++++++++++++++++++--------
 arch/arm/mach-exynos/mct.c               |   23 +-
 arch/arm/plat-s5p/irq-pm.c               |   25 +-
 arch/arm/plat-samsung/irq-vic-timer.c    |   16 +
 8 files changed, 558 insertions(+), 208 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 7fdb139..4ef0cb5 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -345,6 +345,11 @@ static void __init exynos5_map_io(void)
 {
 	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 
+	s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
+	s3c_device_i2c0.resource[0].end   = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
+	s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
+	s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
+
 	/* The I2C bus controllers are directly compatible with s3c2440 */
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
@@ -451,7 +456,14 @@ static struct irq_chip combiner_chip = {
 
 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 {
-	if (combiner_nr >= MAX_COMBINER_NR)
+	unsigned int max_nr;
+
+	if (soc_is_exynos5250())
+		max_nr = EXYNOS5_MAX_COMBINER_NR;
+	else
+		max_nr = EXYNOS4_MAX_COMBINER_NR;
+
+	if (combiner_nr >= max_nr)
 		BUG();
 	if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 		BUG();
@@ -462,8 +474,14 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
 			  unsigned int irq_start)
 {
 	unsigned int i;
+	unsigned int max_nr;
 
-	if (combiner_nr >= MAX_COMBINER_NR)
+	if (soc_is_exynos5250())
+		max_nr = EXYNOS5_MAX_COMBINER_NR;
+	else
+		max_nr = EXYNOS4_MAX_COMBINER_NR;
+
+	if (combiner_nr >= max_nr)
 		BUG();
 
 	combiner_data[combiner_nr].base = base;
@@ -506,7 +524,7 @@ void __init exynos4_init_irq(void)
 		of_irq_init(exynos4_dt_irq_match);
 #endif
 
-	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+	for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
 
 		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 				COMBINER_IRQ(irq, 0));
@@ -527,7 +545,7 @@ void __init exynos5_init_irq(void)
 
 	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 
-	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+	for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
 		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 				COMBINER_IRQ(irq, 0));
 		combiner_cascade_irq(irq, IRQ_SPI(irq));
@@ -651,27 +669,43 @@ static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
 
-static unsigned int exynos4_get_irq_nr(unsigned int number)
-{
-	u32 ret = 0;
-
-	switch (number) {
-	case 0 ... 3:
-		ret = (number + IRQ_EINT0);
-		break;
-	case 4 ... 7:
-		ret = (number + (IRQ_EINT4 - 4));
-		break;
-	case 8 ... 15:
-		ret = (number + (IRQ_EINT8 - 8));
-		break;
-	default:
-		printk(KERN_ERR "number available : %d\n", number);
-	}
-
-	return ret;
-}
+static unsigned int exynos4_eint0_15_src_int[16] = {
+	EXYNOS4_IRQ_EINT0,
+	EXYNOS4_IRQ_EINT1,
+	EXYNOS4_IRQ_EINT2,
+	EXYNOS4_IRQ_EINT3,
+	EXYNOS4_IRQ_EINT4,
+	EXYNOS4_IRQ_EINT5,
+	EXYNOS4_IRQ_EINT6,
+	EXYNOS4_IRQ_EINT7,
+	EXYNOS4_IRQ_EINT8,
+	EXYNOS4_IRQ_EINT9,
+	EXYNOS4_IRQ_EINT10,
+	EXYNOS4_IRQ_EINT11,
+	EXYNOS4_IRQ_EINT12,
+	EXYNOS4_IRQ_EINT13,
+	EXYNOS4_IRQ_EINT14,
+	EXYNOS4_IRQ_EINT15,
+};
 
+static unsigned int exynos5_eint0_15_src_int[16] = {
+	EXYNOS5_IRQ_EINT0,
+	EXYNOS5_IRQ_EINT1,
+	EXYNOS5_IRQ_EINT2,
+	EXYNOS5_IRQ_EINT3,
+	EXYNOS5_IRQ_EINT4,
+	EXYNOS5_IRQ_EINT5,
+	EXYNOS5_IRQ_EINT6,
+	EXYNOS5_IRQ_EINT7,
+	EXYNOS5_IRQ_EINT8,
+	EXYNOS5_IRQ_EINT9,
+	EXYNOS5_IRQ_EINT10,
+	EXYNOS5_IRQ_EINT11,
+	EXYNOS5_IRQ_EINT12,
+	EXYNOS5_IRQ_EINT13,
+	EXYNOS5_IRQ_EINT14,
+	EXYNOS5_IRQ_EINT15,
+};
 static inline void exynos4_irq_eint_mask(struct irq_data *data)
 {
 	u32 mask;
@@ -816,7 +850,7 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
-static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 {
 	u32 *irq_data = irq_get_handler_data(irq);
 	struct irq_chip *chip = irq_get_chip(irq);
@@ -846,15 +880,22 @@ static int __init exynos4_init_irq_eint(void)
 		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 	}
 
-	irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
 
 	for (irq = 0 ; irq <= 15 ; irq++) {
 		eint0_15_data[irq] = IRQ_EINT(irq);
 
-		irq_set_handler_data(exynos4_get_irq_nr(irq),
-				     &eint0_15_data[irq]);
-		irq_set_chained_handler(exynos4_get_irq_nr(irq),
-					exynos4_irq_eint0_15);
+		if (soc_is_exynos5250()) {
+			irq_set_handler_data(exynos5_eint0_15_src_int[irq],
+					     &eint0_15_data[irq]);
+			irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
+						exynos_irq_eint0_15);
+		} else {
+			irq_set_handler_data(exynos4_eint0_15_src_int[irq],
+					     &eint0_15_data[irq]);
+			irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
+						exynos_irq_eint0_15);
+		}
 	}
 
 	return 0;
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
index f57a3de..50ce5b0 100644
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ b/arch/arm/mach-exynos/dev-ahci.c
@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= IRQ_SATA,
-		.end	= IRQ_SATA,
+		.start	= EXYNOS4_IRQ_SATA,
+		.end	= EXYNOS4_IRQ_SATA,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index 5a9f9c2e..7199e1a 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
 		.flags	= IORESOURCE_DMA,
 	},
 	[4] = {
-		.start	= IRQ_AC97,
-		.end	= IRQ_AC97,
+		.start	= EXYNOS4_IRQ_AC97,
+		.end	= EXYNOS4_IRQ_AC97,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 13607c4..3983abe 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -108,7 +108,7 @@ static u8 exynos4212_pdma0_peri[] = {
 struct dma_pl330_platdata exynos4_pdma0_pdata;
 
 static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
-	EXYNOS4_PA_PDMA0, {IRQ_PDMA0}, &exynos4_pdma0_pdata);
+	EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
 
 static u8 exynos4210_pdma1_peri[] = {
 	DMACH_PCM0_RX,
@@ -174,7 +174,7 @@ static u8 exynos4212_pdma1_peri[] = {
 static struct dma_pl330_platdata exynos4_pdma1_pdata;
 
 static AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,
-	EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata);
+	EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
 
 static u8 mdma_peri[] = {
 	DMACH_MTOM_0,
@@ -193,7 +193,7 @@ static struct dma_pl330_platdata exynos4_mdma1_pdata = {
 };
 
 static AMBA_AHB_DEVICE(exynos4_mdma1,  "dma-pl330.2", 0x00041330,
-	EXYNOS4_PA_MDMA1, {IRQ_MDMA1}, &exynos4_mdma1_pdata);
+	EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
 
 static int __init exynos4_dma_init(void)
 {
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index f78070e..9bee853 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * EXYNOS4 - IRQ definitions
+ * EXYNOS - IRQ definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,172 +16,450 @@
 
 /* PPI: Private Peripheral Interrupt */
 
-#define IRQ_PPI(x)		(x+16)
-
-#define IRQ_MCT_LOCALTIMER	IRQ_PPI(12)
+#define IRQ_PPI(x)			(x + 16)
 
 /* SPI: Shared Peripheral Interrupt */
 
-#define IRQ_SPI(x)		(x+32)
-
-#define IRQ_EINT0		IRQ_SPI(16)
-#define IRQ_EINT1		IRQ_SPI(17)
-#define IRQ_EINT2		IRQ_SPI(18)
-#define IRQ_EINT3		IRQ_SPI(19)
-#define IRQ_EINT4		IRQ_SPI(20)
-#define IRQ_EINT5		IRQ_SPI(21)
-#define IRQ_EINT6		IRQ_SPI(22)
-#define IRQ_EINT7		IRQ_SPI(23)
-#define IRQ_EINT8		IRQ_SPI(24)
-#define IRQ_EINT9		IRQ_SPI(25)
-#define IRQ_EINT10		IRQ_SPI(26)
-#define IRQ_EINT11		IRQ_SPI(27)
-#define IRQ_EINT12		IRQ_SPI(28)
-#define IRQ_EINT13		IRQ_SPI(29)
-#define IRQ_EINT14		IRQ_SPI(30)
-#define IRQ_EINT15		IRQ_SPI(31)
-#define IRQ_EINT16_31		IRQ_SPI(32)
-
-#define IRQ_MDMA0		IRQ_SPI(33)
-#define IRQ_MDMA1		IRQ_SPI(34)
-#define IRQ_PDMA0		IRQ_SPI(35)
-#define IRQ_PDMA1		IRQ_SPI(36)
-#define IRQ_TIMER0_VIC		IRQ_SPI(37)
-#define IRQ_TIMER1_VIC		IRQ_SPI(38)
-#define IRQ_TIMER2_VIC		IRQ_SPI(39)
-#define IRQ_TIMER3_VIC		IRQ_SPI(40)
-#define IRQ_TIMER4_VIC		IRQ_SPI(41)
-#define IRQ_MCT_L0		IRQ_SPI(42)
-#define IRQ_WDT			IRQ_SPI(43)
-#define IRQ_RTC_ALARM		IRQ_SPI(44)
-#define IRQ_RTC_TIC		IRQ_SPI(45)
-#define IRQ_GPIO_XB		IRQ_SPI(46)
-#define IRQ_GPIO_XA		IRQ_SPI(47)
-#define IRQ_MCT_L1		IRQ_SPI(48)
-
-#define IRQ_UART0		IRQ_SPI(52)
-#define IRQ_UART1		IRQ_SPI(53)
-#define IRQ_UART2		IRQ_SPI(54)
-#define IRQ_UART3		IRQ_SPI(55)
-#define IRQ_UART4		IRQ_SPI(56)
-#define IRQ_MCT_G0		IRQ_SPI(57)
-#define IRQ_IIC			IRQ_SPI(58)
-#define IRQ_IIC1		IRQ_SPI(59)
-#define IRQ_IIC2		IRQ_SPI(60)
-#define IRQ_IIC3		IRQ_SPI(61)
-#define IRQ_IIC4		IRQ_SPI(62)
-#define IRQ_IIC5		IRQ_SPI(63)
-#define IRQ_IIC6		IRQ_SPI(64)
-#define IRQ_IIC7		IRQ_SPI(65)
-#define IRQ_SPI0		IRQ_SPI(66)
-#define IRQ_SPI1		IRQ_SPI(67)
-#define IRQ_SPI2		IRQ_SPI(68)
-
-#define IRQ_USB_HOST		IRQ_SPI(70)
-#define IRQ_USB_HSOTG		IRQ_SPI(71)
-#define IRQ_MODEM_IF		IRQ_SPI(72)
-#define IRQ_HSMMC0		IRQ_SPI(73)
-#define IRQ_HSMMC1		IRQ_SPI(74)
-#define IRQ_HSMMC2		IRQ_SPI(75)
-#define IRQ_HSMMC3		IRQ_SPI(76)
-#define IRQ_DWMCI		IRQ_SPI(77)
-
-#define IRQ_MIPI_CSIS0		IRQ_SPI(78)
-#define IRQ_MIPI_CSIS1		IRQ_SPI(80)
-
-#define IRQ_ONENAND_AUDI	IRQ_SPI(82)
-#define IRQ_ROTATOR		IRQ_SPI(83)
-#define IRQ_FIMC0		IRQ_SPI(84)
-#define IRQ_FIMC1		IRQ_SPI(85)
-#define IRQ_FIMC2		IRQ_SPI(86)
-#define IRQ_FIMC3		IRQ_SPI(87)
-#define IRQ_JPEG		IRQ_SPI(88)
-#define IRQ_2D			IRQ_SPI(89)
-#define IRQ_PCIE		IRQ_SPI(90)
-
-#define IRQ_MIXER		IRQ_SPI(91)
-#define IRQ_HDMI		IRQ_SPI(92)
-#define IRQ_IIC_HDMIPHY		IRQ_SPI(93)
-#define IRQ_MFC			IRQ_SPI(94)
-#define IRQ_SDO			IRQ_SPI(95)
-
-#define IRQ_AUDIO_SS		IRQ_SPI(96)
-#define IRQ_I2S0		IRQ_SPI(97)
-#define IRQ_I2S1		IRQ_SPI(98)
-#define IRQ_I2S2		IRQ_SPI(99)
-#define IRQ_AC97		IRQ_SPI(100)
-
-#define IRQ_SPDIF		IRQ_SPI(104)
-#define IRQ_ADC0		IRQ_SPI(105)
-#define IRQ_PEN0		IRQ_SPI(106)
-#define IRQ_ADC1		IRQ_SPI(107)
-#define IRQ_PEN1		IRQ_SPI(108)
-#define IRQ_KEYPAD		IRQ_SPI(109)
-#define IRQ_PMU			IRQ_SPI(110)
-#define IRQ_GPS			IRQ_SPI(111)
-#define IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
-#define IRQ_SLIMBUS		IRQ_SPI(113)
-
-#define IRQ_TSI			IRQ_SPI(115)
-#define IRQ_SATA		IRQ_SPI(116)
-
-#define MAX_IRQ_IN_COMBINER	8
-#define COMBINER_GROUP(x)	((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y)	(COMBINER_GROUP(x) + y)
-
-#define IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
-#define IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
-#define IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
-#define IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
-#define IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
-#define IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
-#define IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
-#define IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
-
-#define IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
-#define IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
-#define IRQ_SYSMMU_LCD0_M0_0	COMBINER_IRQ(5, 2)
-#define IRQ_SYSMMU_LCD1_M1_0	COMBINER_IRQ(5, 3)
-#define IRQ_SYSMMU_TV_M0_0	COMBINER_IRQ(5, 4)
-#define IRQ_SYSMMU_MFC_M0_0	COMBINER_IRQ(5, 5)
-#define IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
-#define IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
-
-#define IRQ_FIMD0_FIFO		COMBINER_IRQ(11, 0)
-#define IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
-#define IRQ_FIMD0_SYSTEM	COMBINER_IRQ(11, 2)
-
-#define MAX_COMBINER_NR		16
-
-#define IRQ_ADC			IRQ_ADC0
-#define IRQ_TC			IRQ_PEN0
-
-#define S5P_IRQ_EINT_BASE	COMBINER_IRQ(MAX_COMBINER_NR, 0)
-
-#define S5P_EINT_BASE1		(S5P_IRQ_EINT_BASE + 0)
-#define S5P_EINT_BASE2		(S5P_IRQ_EINT_BASE + 16)
-
-/* optional GPIO interrupts */
-#define S5P_GPIOINT_BASE	(S5P_IRQ_EINT_BASE + 32)
-#define IRQ_GPIO1_NR_GROUPS	16
-#define IRQ_GPIO2_NR_GROUPS	9
-#define IRQ_GPIO_END		(S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-
-#define IRQ_TIMER_BASE		(IRQ_GPIO_END + 64)
+#define IRQ_SPI(x)			(x + 32)
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+/* COMBINER */
+
+#define MAX_IRQ_IN_COMBINER		8
+#define COMBINER_GROUP(x)		((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
+#define COMBINER_IRQ(x, y)		(COMBINER_GROUP(x) + y)
+
+/* For EXYNOS4 and EXYNOS5 */
+
+#define EXYNOS_IRQ_MCT_LOCALTIMER	IRQ_PPI(12)
+
+#define EXYNOS_IRQ_EINT16_31		IRQ_SPI(32)
+
+/* For EXYNOS4 SoCs */
+
+#define EXYNOS4_IRQ_EINT0		IRQ_SPI(16)
+#define EXYNOS4_IRQ_EINT1		IRQ_SPI(17)
+#define EXYNOS4_IRQ_EINT2		IRQ_SPI(18)
+#define EXYNOS4_IRQ_EINT3		IRQ_SPI(19)
+#define EXYNOS4_IRQ_EINT4		IRQ_SPI(20)
+#define EXYNOS4_IRQ_EINT5		IRQ_SPI(21)
+#define EXYNOS4_IRQ_EINT6		IRQ_SPI(22)
+#define EXYNOS4_IRQ_EINT7		IRQ_SPI(23)
+#define EXYNOS4_IRQ_EINT8		IRQ_SPI(24)
+#define EXYNOS4_IRQ_EINT9		IRQ_SPI(25)
+#define EXYNOS4_IRQ_EINT10		IRQ_SPI(26)
+#define EXYNOS4_IRQ_EINT11		IRQ_SPI(27)
+#define EXYNOS4_IRQ_EINT12		IRQ_SPI(28)
+#define EXYNOS4_IRQ_EINT13		IRQ_SPI(29)
+#define EXYNOS4_IRQ_EINT14		IRQ_SPI(30)
+#define EXYNOS4_IRQ_EINT15		IRQ_SPI(31)
+
+#define EXYNOS4_IRQ_MDMA0		IRQ_SPI(33)
+#define EXYNOS4_IRQ_MDMA1		IRQ_SPI(34)
+#define EXYNOS4_IRQ_PDMA0		IRQ_SPI(35)
+#define EXYNOS4_IRQ_PDMA1		IRQ_SPI(36)
+#define EXYNOS4_IRQ_TIMER0_VIC		IRQ_SPI(37)
+#define EXYNOS4_IRQ_TIMER1_VIC		IRQ_SPI(38)
+#define EXYNOS4_IRQ_TIMER2_VIC		IRQ_SPI(39)
+#define EXYNOS4_IRQ_TIMER3_VIC		IRQ_SPI(40)
+#define EXYNOS4_IRQ_TIMER4_VIC		IRQ_SPI(41)
+#define EXYNOS4_IRQ_MCT_L0		IRQ_SPI(42)
+#define EXYNOS4_IRQ_WDT			IRQ_SPI(43)
+#define EXYNOS4_IRQ_RTC_ALARM		IRQ_SPI(44)
+#define EXYNOS4_IRQ_RTC_TIC		IRQ_SPI(45)
+#define EXYNOS4_IRQ_GPIO_XB		IRQ_SPI(46)
+#define EXYNOS4_IRQ_GPIO_XA		IRQ_SPI(47)
+#define EXYNOS4_IRQ_MCT_L1		IRQ_SPI(48)
 
 #define EXYNOS4_IRQ_UART0		IRQ_SPI(52)
 #define EXYNOS4_IRQ_UART1		IRQ_SPI(53)
 #define EXYNOS4_IRQ_UART2		IRQ_SPI(54)
 #define EXYNOS4_IRQ_UART3		IRQ_SPI(55)
 #define EXYNOS4_IRQ_UART4		IRQ_SPI(56)
+#define EXYNOS4_IRQ_MCT_G0		IRQ_SPI(57)
+#define EXYNOS4_IRQ_IIC			IRQ_SPI(58)
+#define EXYNOS4_IRQ_IIC1		IRQ_SPI(59)
+#define EXYNOS4_IRQ_IIC2		IRQ_SPI(60)
+#define EXYNOS4_IRQ_IIC3		IRQ_SPI(61)
+#define EXYNOS4_IRQ_IIC4		IRQ_SPI(62)
+#define EXYNOS4_IRQ_IIC5		IRQ_SPI(63)
+#define EXYNOS4_IRQ_IIC6		IRQ_SPI(64)
+#define EXYNOS4_IRQ_IIC7		IRQ_SPI(65)
+#define EXYNOS4_IRQ_SPI0		IRQ_SPI(66)
+#define EXYNOS4_IRQ_SPI1		IRQ_SPI(67)
+#define EXYNOS4_IRQ_SPI2		IRQ_SPI(68)
+
+#define EXYNOS4_IRQ_USB_HOST		IRQ_SPI(70)
+#define EXYNOS4_IRQ_USB_HSOTG		IRQ_SPI(71)
+#define EXYNOS4_IRQ_MODEM_IF		IRQ_SPI(72)
+#define EXYNOS4_IRQ_HSMMC0		IRQ_SPI(73)
+#define EXYNOS4_IRQ_HSMMC1		IRQ_SPI(74)
+#define EXYNOS4_IRQ_HSMMC2		IRQ_SPI(75)
+#define EXYNOS4_IRQ_HSMMC3		IRQ_SPI(76)
+#define EXYNOS4_IRQ_DWMCI		IRQ_SPI(77)
+
+#define EXYNOS4_IRQ_MIPI_CSIS0		IRQ_SPI(78)
+#define EXYNOS4_IRQ_MIPI_CSIS1		IRQ_SPI(80)
+
+#define EXYNOS4_IRQ_ONENAND_AUDI	IRQ_SPI(82)
+#define EXYNOS4_IRQ_ROTATOR		IRQ_SPI(83)
+#define EXYNOS4_IRQ_FIMC0		IRQ_SPI(84)
+#define EXYNOS4_IRQ_FIMC1		IRQ_SPI(85)
+#define EXYNOS4_IRQ_FIMC2		IRQ_SPI(86)
+#define EXYNOS4_IRQ_FIMC3		IRQ_SPI(87)
+#define EXYNOS4_IRQ_JPEG		IRQ_SPI(88)
+#define EXYNOS4_IRQ_2D			IRQ_SPI(89)
+#define EXYNOS4_IRQ_PCIE		IRQ_SPI(90)
+
+#define EXYNOS4_IRQ_MIXER		IRQ_SPI(91)
+#define EXYNOS4_IRQ_HDMI		IRQ_SPI(92)
+#define EXYNOS4_IRQ_IIC_HDMIPHY		IRQ_SPI(93)
+#define EXYNOS4_IRQ_MFC			IRQ_SPI(94)
+#define EXYNOS4_IRQ_SDO			IRQ_SPI(95)
+
+#define EXYNOS4_IRQ_AUDIO_SS		IRQ_SPI(96)
+#define EXYNOS4_IRQ_I2S0		IRQ_SPI(97)
+#define EXYNOS4_IRQ_I2S1		IRQ_SPI(98)
+#define EXYNOS4_IRQ_I2S2		IRQ_SPI(99)
+#define EXYNOS4_IRQ_AC97		IRQ_SPI(100)
+
+#define EXYNOS4_IRQ_SPDIF		IRQ_SPI(104)
+#define EXYNOS4_IRQ_ADC0		IRQ_SPI(105)
+#define EXYNOS4_IRQ_PEN0		IRQ_SPI(106)
+#define EXYNOS4_IRQ_ADC1		IRQ_SPI(107)
+#define EXYNOS4_IRQ_PEN1		IRQ_SPI(108)
+#define EXYNOS4_IRQ_KEYPAD		IRQ_SPI(109)
+#define EXYNOS4_IRQ_PMU			IRQ_SPI(110)
+#define EXYNOS4_IRQ_GPS			IRQ_SPI(111)
+#define EXYNOS4_IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
+#define EXYNOS4_IRQ_SLIMBUS		IRQ_SPI(113)
+
+#define EXYNOS4_IRQ_TSI			IRQ_SPI(115)
+#define EXYNOS4_IRQ_SATA		IRQ_SPI(116)
+
+#define EXYNOS4_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
+#define EXYNOS4_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC1_0	COMBINER_IRQ(4, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC2_0	COMBINER_IRQ(4, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC3_0	COMBINER_IRQ(4, 5)
+#define EXYNOS4_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 6)
+#define EXYNOS4_IRQ_SYSMMU_2D_0		COMBINER_IRQ(4, 7)
+
+#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(5, 0)
+#define EXYNOS4_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(5, 1)
+#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0	COMBINER_IRQ(5, 2)
+#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0	COMBINER_IRQ(5, 3)
+#define EXYNOS4_IRQ_SYSMMU_TV_M0_0	COMBINER_IRQ(5, 4)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0	COMBINER_IRQ(5, 5)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
+#define EXYNOS4_IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
+
+#define EXYNOS4_IRQ_FIMD0_FIFO		COMBINER_IRQ(11, 0)
+#define EXYNOS4_IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
+#define EXYNOS4_IRQ_FIMD0_SYSTEM	COMBINER_IRQ(11, 2)
+
+#define EXYNOS4_MAX_COMBINER_NR		16
+
+#define EXYNOS4_IRQ_GPIO1_NR_GROUPS	16
+#define EXYNOS4_IRQ_GPIO2_NR_GROUPS	9
+
+/*
+ * For Compatibility:
+ * the default is for EXYNOS4, and
+ * for exynos5, should be re-mapped at function
+ */
+
+#define IRQ_TIMER0_VIC			EXYNOS4_IRQ_TIMER0_VIC
+#define IRQ_TIMER1_VIC			EXYNOS4_IRQ_TIMER1_VIC
+#define IRQ_TIMER2_VIC			EXYNOS4_IRQ_TIMER2_VIC
+#define IRQ_TIMER3_VIC			EXYNOS4_IRQ_TIMER3_VIC
+#define IRQ_TIMER4_VIC			EXYNOS4_IRQ_TIMER4_VIC
+
+#define IRQ_WDT				EXYNOS4_IRQ_WDT
+#define IRQ_RTC_ALARM			EXYNOS4_IRQ_RTC_ALARM
+#define IRQ_RTC_TIC			EXYNOS4_IRQ_RTC_TIC
+#define IRQ_GPIO_XB			EXYNOS4_IRQ_GPIO_XB
+#define IRQ_GPIO_XA			EXYNOS4_IRQ_GPIO_XA
+
+#define IRQ_IIC				EXYNOS4_IRQ_IIC
+#define IRQ_IIC1			EXYNOS4_IRQ_IIC1
+#define IRQ_IIC3			EXYNOS4_IRQ_IIC3
+#define IRQ_IIC5			EXYNOS4_IRQ_IIC5
+#define IRQ_IIC6			EXYNOS4_IRQ_IIC6
+#define IRQ_IIC7			EXYNOS4_IRQ_IIC7
+
+#define IRQ_USB_HOST			EXYNOS4_IRQ_USB_HOST
+
+#define IRQ_HSMMC0			EXYNOS4_IRQ_HSMMC0
+#define IRQ_HSMMC1			EXYNOS4_IRQ_HSMMC1
+#define IRQ_HSMMC2			EXYNOS4_IRQ_HSMMC2
+#define IRQ_HSMMC3			EXYNOS4_IRQ_HSMMC3
+
+#define IRQ_MIPI_CSIS0			EXYNOS4_IRQ_MIPI_CSIS0
+
+#define IRQ_ONENAND_AUDI		EXYNOS4_IRQ_ONENAND_AUDI
+
+#define IRQ_FIMC0			EXYNOS4_IRQ_FIMC0
+#define IRQ_FIMC1			EXYNOS4_IRQ_FIMC1
+#define IRQ_FIMC2			EXYNOS4_IRQ_FIMC2
+#define IRQ_FIMC3			EXYNOS4_IRQ_FIMC3
+#define IRQ_JPEG			EXYNOS4_IRQ_JPEG
+#define IRQ_2D				EXYNOS4_IRQ_2D
+
+#define IRQ_MIXER			EXYNOS4_IRQ_MIXER
+#define IRQ_HDMI			EXYNOS4_IRQ_HDMI
+#define IRQ_IIC_HDMIPHY			EXYNOS4_IRQ_IIC_HDMIPHY
+#define IRQ_MFC				EXYNOS4_IRQ_MFC
+#define IRQ_SDO				EXYNOS4_IRQ_SDO
+
+#define IRQ_ADC				EXYNOS4_IRQ_ADC0
+#define IRQ_TC				EXYNOS4_IRQ_PEN0
+
+#define IRQ_KEYPAD			EXYNOS4_IRQ_KEYPAD
+#define IRQ_PMU				EXYNOS4_IRQ_PMU
+
+#define IRQ_SYSMMU_MDMA0_0		EXYNOS4_IRQ_SYSMMU_MDMA0_0
+#define IRQ_SYSMMU_SSS_0                EXYNOS4_IRQ_SYSMMU_SSS_0
+#define IRQ_SYSMMU_FIMC0_0              EXYNOS4_IRQ_SYSMMU_FIMC0_0
+#define IRQ_SYSMMU_FIMC1_0              EXYNOS4_IRQ_SYSMMU_FIMC1_0
+#define IRQ_SYSMMU_FIMC2_0              EXYNOS4_IRQ_SYSMMU_FIMC2_0
+#define IRQ_SYSMMU_FIMC3_0              EXYNOS4_IRQ_SYSMMU_FIMC3_0
+#define IRQ_SYSMMU_JPEG_0               EXYNOS4_IRQ_SYSMMU_JPEG_0
+#define IRQ_SYSMMU_2D_0                 EXYNOS4_IRQ_SYSMMU_2D_0
 
+#define IRQ_SYSMMU_ROTATOR_0            EXYNOS4_IRQ_SYSMMU_ROTATOR_0
+#define IRQ_SYSMMU_MDMA1_0              EXYNOS4_IRQ_SYSMMU_MDMA1_0
+#define IRQ_SYSMMU_LCD0_M0_0            EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
+#define IRQ_SYSMMU_LCD1_M1_0            EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
+#define IRQ_SYSMMU_TV_M0_0              EXYNOS4_IRQ_SYSMMU_TV_M0_0
+#define IRQ_SYSMMU_MFC_M0_0             EXYNOS4_IRQ_SYSMMU_MFC_M0_0
+#define IRQ_SYSMMU_MFC_M1_0             EXYNOS4_IRQ_SYSMMU_MFC_M1_0
+#define IRQ_SYSMMU_PCIE_0               EXYNOS4_IRQ_SYSMMU_PCIE_0
+
+#define IRQ_FIMD0_FIFO			EXYNOS4_IRQ_FIMD0_FIFO
+#define IRQ_FIMD0_VSYNC			EXYNOS4_IRQ_FIMD0_VSYNC
+#define IRQ_FIMD0_SYSTEM		EXYNOS4_IRQ_FIMD0_SYSTEM
+
+#define IRQ_GPIO1_NR_GROUPS		EXYNOS4_IRQ_GPIO1_NR_GROUPS
+#define IRQ_GPIO2_NR_GROUPS		EXYNOS4_IRQ_GPIO2_NR_GROUPS
+
+/* For EXYNOS5 SoCs */
+
+#define EXYNOS5_IRQ_MDMA0		IRQ_SPI(33)
+#define EXYNOS5_IRQ_PDMA0		IRQ_SPI(34)
+#define EXYNOS5_IRQ_PDMA1		IRQ_SPI(35)
+#define EXYNOS5_IRQ_TIMER0_VIC		IRQ_SPI(36)
+#define EXYNOS5_IRQ_TIMER1_VIC		IRQ_SPI(37)
+#define EXYNOS5_IRQ_TIMER2_VIC		IRQ_SPI(38)
+#define EXYNOS5_IRQ_TIMER3_VIC		IRQ_SPI(39)
+#define EXYNOS5_IRQ_TIMER4_VIC		IRQ_SPI(40)
+#define EXYNOS5_IRQ_RTIC		IRQ_SPI(41)
+#define EXYNOS5_IRQ_WDT			IRQ_SPI(42)
+#define EXYNOS5_IRQ_RTC_ALARM		IRQ_SPI(43)
+#define EXYNOS5_IRQ_RTC_TIC		IRQ_SPI(44)
+#define EXYNOS5_IRQ_GPIO_XB		IRQ_SPI(45)
+#define EXYNOS5_IRQ_GPIO_XA		IRQ_SPI(46)
+#define EXYNOS5_IRQ_GPIO		IRQ_SPI(47)
+#define EXYNOS5_IRQ_IEM_IEC		IRQ_SPI(48)
+#define EXYNOS5_IRQ_IEM_APC		IRQ_SPI(49)
+#define EXYNOS5_IRQ_GPIO_C2C		IRQ_SPI(50)
 #define EXYNOS5_IRQ_UART0		IRQ_SPI(51)
 #define EXYNOS5_IRQ_UART1		IRQ_SPI(52)
 #define EXYNOS5_IRQ_UART2		IRQ_SPI(53)
 #define EXYNOS5_IRQ_UART3		IRQ_SPI(54)
 #define EXYNOS5_IRQ_UART4		IRQ_SPI(55)
+#define EXYNOS5_IRQ_IIC			IRQ_SPI(56)
+#define EXYNOS5_IRQ_IIC1		IRQ_SPI(57)
+#define EXYNOS5_IRQ_IIC2		IRQ_SPI(58)
+#define EXYNOS5_IRQ_IIC3		IRQ_SPI(59)
+#define EXYNOS5_IRQ_IIC4		IRQ_SPI(60)
+#define EXYNOS5_IRQ_IIC5		IRQ_SPI(61)
+#define EXYNOS5_IRQ_IIC6		IRQ_SPI(62)
+#define EXYNOS5_IRQ_IIC7		IRQ_SPI(63)
+#define EXYNOS5_IRQ_IIC_HDMIPHY		IRQ_SPI(64)
+#define EXYNOS5_IRQ_TMU			IRQ_SPI(65)
+#define EXYNOS5_IRQ_FIQ_0		IRQ_SPI(66)
+#define EXYNOS5_IRQ_FIQ_1		IRQ_SPI(67)
+#define EXYNOS5_IRQ_SPI0		IRQ_SPI(68)
+#define EXYNOS5_IRQ_SPI1		IRQ_SPI(69)
+#define EXYNOS5_IRQ_SPI2		IRQ_SPI(70)
+#define EXYNOS5_IRQ_USB_HOST		IRQ_SPI(71)
+#define EXYNOS5_IRQ_USB3_DRD		IRQ_SPI(72)
+#define EXYNOS5_IRQ_MIPI_HSI		IRQ_SPI(73)
+#define EXYNOS5_IRQ_USB_HSOTG		IRQ_SPI(74)
+#define EXYNOS5_IRQ_HSMMC0		IRQ_SPI(75)
+#define EXYNOS5_IRQ_HSMMC1		IRQ_SPI(76)
+#define EXYNOS5_IRQ_HSMMC2		IRQ_SPI(77)
+#define EXYNOS5_IRQ_HSMMC3		IRQ_SPI(78)
+#define EXYNOS5_IRQ_MIPICSI0		IRQ_SPI(79)
+#define EXYNOS5_IRQ_MIPICSI1		IRQ_SPI(80)
+#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT	IRQ_SPI(81)
+#define EXYNOS5_IRQ_MIPIDSI0		IRQ_SPI(82)
+#define EXYNOS5_IRQ_ROTATOR		IRQ_SPI(84)
+#define EXYNOS5_IRQ_GSC0		IRQ_SPI(85)
+#define EXYNOS5_IRQ_GSC1		IRQ_SPI(86)
+#define EXYNOS5_IRQ_GSC2		IRQ_SPI(87)
+#define EXYNOS5_IRQ_GSC3		IRQ_SPI(88)
+#define EXYNOS5_IRQ_JPEG		IRQ_SPI(89)
+#define EXYNOS5_IRQ_EFNFCON_DMA		IRQ_SPI(90)
+#define EXYNOS5_IRQ_2D			IRQ_SPI(91)
+#define EXYNOS5_IRQ_SFMC0		IRQ_SPI(92)
+#define EXYNOS5_IRQ_SFMC1		IRQ_SPI(93)
+#define EXYNOS5_IRQ_MIXER		IRQ_SPI(94)
+#define EXYNOS5_IRQ_HDMI		IRQ_SPI(95)
+#define EXYNOS5_IRQ_MFC			IRQ_SPI(96)
+#define EXYNOS5_IRQ_AUDIO_SS		IRQ_SPI(97)
+#define EXYNOS5_IRQ_I2S0		IRQ_SPI(98)
+#define EXYNOS5_IRQ_I2S1		IRQ_SPI(99)
+#define EXYNOS5_IRQ_I2S2		IRQ_SPI(100)
+#define EXYNOS5_IRQ_AC97		IRQ_SPI(101)
+#define EXYNOS5_IRQ_PCM0		IRQ_SPI(102)
+#define EXYNOS5_IRQ_PCM1		IRQ_SPI(103)
+#define EXYNOS5_IRQ_PCM2		IRQ_SPI(104)
+#define EXYNOS5_IRQ_SPDIF		IRQ_SPI(105)
+#define EXYNOS5_IRQ_ADC0		IRQ_SPI(106)
+
+#define EXYNOS5_IRQ_SATA_PHY		IRQ_SPI(108)
+#define EXYNOS5_IRQ_SATA_PMEMREQ	IRQ_SPI(109)
+#define EXYNOS5_IRQ_CAM_C		IRQ_SPI(110)
+#define EXYNOS5_IRQ_EAGLE_PMU		IRQ_SPI(111)
+#define EXYNOS5_IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
+#define EXYNOS5_IRQ_DP1_INTP1		IRQ_SPI(113)
+#define EXYNOS5_IRQ_CEC			IRQ_SPI(114)
+#define EXYNOS5_IRQ_SATA		IRQ_SPI(115)
+#define EXYNOS5_IRQ_NFCON		IRQ_SPI(116)
+
+#define EXYNOS5_IRQ_MMC44		IRQ_SPI(123)
+#define EXYNOS5_IRQ_MDMA1		IRQ_SPI(124)
+#define EXYNOS5_IRQ_FIMC_LITE0		IRQ_SPI(125)
+#define EXYNOS5_IRQ_FIMC_LITE1		IRQ_SPI(126)
+#define EXYNOS5_IRQ_RP_TIMER		IRQ_SPI(127)
+
+#define EXYNOS5_IRQ_PMU			COMBINER_IRQ(1, 2)
+#define EXYNOS5_IRQ_PMU_CPU1		COMBINER_IRQ(1, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_GSC0_0	COMBINER_IRQ(2, 0)
+#define EXYNOS5_IRQ_SYSMMU_GSC0_1	COMBINER_IRQ(2, 1)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_0	COMBINER_IRQ(2, 2)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_1	COMBINER_IRQ(2, 3)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_0	COMBINER_IRQ(2, 4)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_1	COMBINER_IRQ(2, 5)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_0	COMBINER_IRQ(2, 6)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_1	COMBINER_IRQ(2, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_0	COMBINER_IRQ(3, 2)
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_1	COMBINER_IRQ(3, 3)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_0	COMBINER_IRQ(3, 4)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_1	COMBINER_IRQ(3, 5)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0	COMBINER_IRQ(3, 6)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1	COMBINER_IRQ(3, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0	COMBINER_IRQ(4, 0)
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1	COMBINER_IRQ(4, 1)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_0	COMBINER_IRQ(4, 2)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_1	COMBINER_IRQ(4, 3)
+
+#define EXYNOS5_IRQ_SYSMMU_FD_0		COMBINER_IRQ(5, 0)
+#define EXYNOS5_IRQ_SYSMMU_FD_1		COMBINER_IRQ(5, 1)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0	COMBINER_IRQ(5, 2)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1	COMBINER_IRQ(5, 3)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_0	COMBINER_IRQ(5, 4)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_1	COMBINER_IRQ(5, 5)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_0	COMBINER_IRQ(5, 6)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_1	COMBINER_IRQ(5, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ARM_0	COMBINER_IRQ(6, 0)
+#define EXYNOS5_IRQ_SYSMMU_ARM_1	COMBINER_IRQ(6, 1)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0	COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1	COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_0	COMBINER_IRQ(6, 4)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_1	COMBINER_IRQ(6, 5)
+#define EXYNOS5_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(6, 6)
+#define EXYNOS5_IRQ_SYSMMU_SSS_1	COMBINER_IRQ(6, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(7, 0)
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_1	COMBINER_IRQ(7, 1)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_0	COMBINER_IRQ(7, 2)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_1	COMBINER_IRQ(7, 3)
+#define EXYNOS5_IRQ_SYSMMU_TV_0		COMBINER_IRQ(7, 4)
+#define EXYNOS5_IRQ_SYSMMU_TV_1		COMBINER_IRQ(7, 5)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_0	COMBINER_IRQ(7, 6)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_1	COMBINER_IRQ(7, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0	COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1	COMBINER_IRQ(8, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_DIS1_0	COMBINER_IRQ(9, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS1_1	COMBINER_IRQ(9, 5)
+
+#define EXYNOS5_IRQ_DP			COMBINER_IRQ(10, 3)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_0	COMBINER_IRQ(10, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_1	COMBINER_IRQ(10, 5)
+#define EXYNOS5_IRQ_SYSMMU_ISP_0	COMBINER_IRQ(10, 6)
+#define EXYNOS5_IRQ_SYSMMU_ISP_1	COMBINER_IRQ(10, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ODC_0	COMBINER_IRQ(11, 0)
+#define EXYNOS5_IRQ_SYSMMU_ODC_1	COMBINER_IRQ(11, 1)
+#define EXYNOS5_IRQ_SYSMMU_DRC_0	COMBINER_IRQ(11, 6)
+#define EXYNOS5_IRQ_SYSMMU_DRC_1	COMBINER_IRQ(11, 7)
+
+#define EXYNOS5_IRQ_FIMD1_FIFO		COMBINER_IRQ(18, 4)
+#define EXYNOS5_IRQ_FIMD1_VSYNC		COMBINER_IRQ(18, 5)
+#define EXYNOS5_IRQ_FIMD1_SYSTEM	COMBINER_IRQ(18, 6)
+
+#define EXYNOS5_IRQ_EINT0		COMBINER_IRQ(23, 0)
+#define EXYNOS5_IRQ_MCT_L0		COMBINER_IRQ(23, 1)
+#define EXYNOS5_IRQ_MCT_L1		COMBINER_IRQ(23, 2)
+#define EXYNOS5_IRQ_MCT_G0		COMBINER_IRQ(23, 3)
+#define EXYNOS5_IRQ_MCT_G1		COMBINER_IRQ(23, 4)
+#define EXYNOS5_IRQ_MCT_G2		COMBINER_IRQ(23, 5)
+#define EXYNOS5_IRQ_MCT_G3		COMBINER_IRQ(23, 6)
+
+#define EXYNOS5_IRQ_EINT1		COMBINER_IRQ(24, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_0	COMBINER_IRQ(24, 1)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_1	COMBINER_IRQ(24, 2)
+#define EXYNOS5_IRQ_SYSMMU_2D_0		COMBINER_IRQ(24, 5)
+#define EXYNOS5_IRQ_SYSMMU_2D_1		COMBINER_IRQ(24, 6)
+
+#define EXYNOS5_IRQ_EINT2		COMBINER_IRQ(25, 0)
+#define EXYNOS5_IRQ_EINT3		COMBINER_IRQ(25, 1)
+
+#define EXYNOS5_IRQ_EINT4		COMBINER_IRQ(26, 0)
+#define EXYNOS5_IRQ_EINT5		COMBINER_IRQ(26, 1)
+
+#define EXYNOS5_IRQ_EINT6		COMBINER_IRQ(27, 0)
+#define EXYNOS5_IRQ_EINT7		COMBINER_IRQ(27, 1)
+
+#define EXYNOS5_IRQ_EINT8		COMBINER_IRQ(28, 0)
+#define EXYNOS5_IRQ_EINT9		COMBINER_IRQ(28, 1)
+
+#define EXYNOS5_IRQ_EINT10		COMBINER_IRQ(29, 0)
+#define EXYNOS5_IRQ_EINT11		COMBINER_IRQ(29, 1)
+
+#define EXYNOS5_IRQ_EINT12		COMBINER_IRQ(30, 0)
+#define EXYNOS5_IRQ_EINT13		COMBINER_IRQ(30, 1)
+
+#define EXYNOS5_IRQ_EINT14		COMBINER_IRQ(31, 0)
+#define EXYNOS5_IRQ_EINT15		COMBINER_IRQ(31, 1)
+
+#define EXYNOS5_MAX_COMBINER_NR		32
+
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS	13
+#define EXYNOS5_IRQ_GPIO2_NR_GROUPS	9
+#define EXYNOS5_IRQ_GPIO3_NR_GROUPS	5
+#define EXYNOS5_IRQ_GPIO4_NR_GROUPS	1
+
+#define MAX_COMBINER_NR			(EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
+					EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
+
+#define S5P_EINT_BASE1			COMBINER_IRQ(MAX_COMBINER_NR, 0)
+#define S5P_EINT_BASE2			(S5P_EINT_BASE1 + 16)
+#define S5P_GPIOINT_BASE		(S5P_EINT_BASE1 + 32)
+#define IRQ_GPIO_END			(S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
+#define IRQ_TIMER_BASE			(IRQ_GPIO_END + 64)
+
+/* Set the default NR_IRQS */
+
+#define NR_IRQS				(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
 
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 85b5527..1016515 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -258,7 +258,10 @@ static void exynos4_clockevent_init(void)
 	mct_comp_device.cpumask = cpumask_of(0);
 	clockevents_register_device(&mct_comp_device);
 
-	setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
+	if (soc_is_exynos5250())
+		setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
+	else
+		setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
 }
 
 #ifdef CONFIG_LOCAL_TIMERS
@@ -406,16 +409,16 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
 	if (mct_int_type == MCT_INT_SPI) {
 		if (cpu == 0) {
 			mct_tick0_event_irq.dev_id = mevt;
-			evt->irq = IRQ_MCT_L0;
-			setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+			evt->irq = EXYNOS4_IRQ_MCT_L0;
+			setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
 		} else {
 			mct_tick1_event_irq.dev_id = mevt;
-			evt->irq = IRQ_MCT_L1;
-			setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
-			irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+			evt->irq = EXYNOS4_IRQ_MCT_L1;
+			setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
+			irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
 		}
 	} else {
-		enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
+		enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
 	}
 }
 
@@ -437,7 +440,7 @@ void local_timer_stop(struct clock_event_device *evt)
 		else
 			remove_irq(evt->irq, &mct_tick1_event_irq);
 	else
-		disable_percpu_irq(IRQ_MCT_LOCALTIMER);
+		disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
 }
 #endif /* CONFIG_LOCAL_TIMERS */
 
@@ -452,11 +455,11 @@ static void __init exynos4_timer_resources(void)
 	if (mct_int_type == MCT_INT_PPI) {
 		int err;
 
-		err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
+		err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
 					 exynos4_mct_tick_isr, "MCT",
 					 &percpu_mct_tick);
 		WARN(err, "MCT: can't request IRQ %d (%d)\n",
-		     IRQ_MCT_LOCALTIMER, err);
+		     EXYNOS_IRQ_MCT_LOCALTIMER, err);
 	}
 #endif /* CONFIG_LOCAL_TIMERS */
 }
diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
index 327acb3..d1bfeca 100644
--- a/arch/arm/plat-s5p/irq-pm.c
+++ b/arch/arm/plat-s5p/irq-pm.c
@@ -39,19 +39,32 @@ unsigned long s3c_irqwake_eintallow	= 0xffffffffL;
 int s3c_irq_wake(struct irq_data *data, unsigned int state)
 {
 	unsigned long irqbit;
+	unsigned int irq_rtc_tic, irq_rtc_alarm;
+
+#ifdef CONFIG_ARCH_EXYNOS
+	if (soc_is_exynos5250()) {
+		irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC;
+		irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM;
+	} else {
+		irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC;
+		irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM;
+	}
+#else
+	irq_rtc_tic = IRQ_RTC_TIC;
+	irq_rtc_alarm = IRQ_RTC_ALARM;
+#endif
+
+	if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
+		irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
 
-	switch (data->irq) {
-	case IRQ_RTC_TIC:
-	case IRQ_RTC_ALARM:
-		irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
 		if (!state)
 			s3c_irqwake_intmask |= irqbit;
 		else
 			s3c_irqwake_intmask &= ~irqbit;
-		break;
-	default:
+	} else {
 		return -ENOENT;
 	}
+
 	return 0;
 }
 
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index 51583cd..f980cf3 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 
 #include <mach/map.h>
+#include <plat/cpu.h>
 #include <plat/irq-vic-timer.h>
 #include <plat/regs-timer.h>
 
@@ -57,6 +58,21 @@ void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
 	struct irq_chip_type *ct;
 	unsigned int i;
 
+#ifdef CONFIG_ARCH_EXYNOS
+	if (soc_is_exynos5250()) {
+		pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
+		pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
+		pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
+		pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
+		pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
+	} else {
+		pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
+		pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
+		pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
+		pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
+		pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
+	}
+#endif
 	s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
 					 S3C64XX_TINT_CSTAT, handle_level_irq);
 
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:42:15 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:15 -0700
Subject: [PATCH v4 09/12] ARM: EXYNOS: add support get_core_count() for
 EXYNOS5250
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-10-git-send-email-kgene.kim@samsung.com>

The EXYNOS5250 has two Cortex-A15 cores and there's no
need to call scu_enable() in platform_smp_prepare_cpus()
because Cortex-A15 has no regarding scu register which
can be used for getting number of cores.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/platsmp.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 0f2035a..36c3984 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -166,7 +166,10 @@ void __init smp_init_cpus(void)
 	void __iomem *scu_base = scu_base_addr();
 	unsigned int i, ncores;
 
-	ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+	if (soc_is_exynos5250())
+		ncores = 2;
+	else
+		ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
 	/* sanity check */
 	if (ncores > nr_cpu_ids) {
@@ -183,8 +186,8 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
-
-	scu_enable(scu_base_addr());
+	if (!soc_is_exynos5250())
+		scu_enable(scu_base_addr());
 
 	/*
 	 * Write the address of secondary startup into the
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:42:16 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:16 -0700
Subject: [PATCH v4 10/12] ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5
 SoCs
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-11-git-send-email-kgene.kim@samsung.com>

This patch adds CONFIG_ARCH_EXYNOS5 and CONFIG_SOC_EXYNOS5250
for supporting EXYNOS5250 SoC and allows supporting EXYNOS4
and EXYNOS5 together.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/Kconfig  |   18 +++++++++++++-----
 arch/arm/mach-exynos/Makefile |    1 +
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5e0a456..a2ed05c 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -11,18 +11,19 @@ if ARCH_EXYNOS
 
 menu "SAMSUNG EXYNOS SoCs Support"
 
-choice
-	prompt "EXYNOS System Type"
-	default ARCH_EXYNOS4
-
 config ARCH_EXYNOS4
 	bool "SAMSUNG EXYNOS4"
+	default y
 	select HAVE_SMP
 	select MIGHT_HAVE_CACHE_L2X0
 	help
 	  Samsung EXYNOS4 SoCs based systems
 
-endchoice
+config ARCH_EXYNOS5
+	bool "SAMSUNG EXYNOS5"
+	select HAVE_SMP
+	help
+	  Samsung EXYNOS5 (Cortex-A15) SoC based systems
 
 comment "EXYNOS SoCs"
 
@@ -55,6 +56,13 @@ config SOC_EXYNOS4412
 	help
 	  Enable EXYNOS4412 SoC support
 
+config SOC_EXYNOS5250
+	bool "SAMSUNG EXYNOS5250"
+	default y
+	depends on ARCH_EXYNOS5
+	help
+	  Enable EXYNOS5250 SoC support
+
 config EXYNOS4_MCT
 	bool
 	default y
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index f8a3770..7214092 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -14,6 +14,7 @@ obj-				:=
 
 obj-$(CONFIG_ARCH_EXYNOS)	+= common.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clock-exynos4.o
+obj-$(CONFIG_ARCH_EXYNOS5)	+= clock-exynos5.o
 obj-$(CONFIG_CPU_EXYNOS4210)	+= clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)	+= clock-exynos4212.o
 
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:42:17 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:17 -0700
Subject: [PATCH v4 11/12] ARM: EXYNOS: add support device tree enabled board
 file for EXYNOS5
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-12-git-send-email-kgene.kim@samsung.com>

This patch adds a new EXYNOS5 compatible device tree enabled board
When using this, a corresponding device tree blob which describes the
board's properties should be supplied at boot time to the kernel.

Cc: Thomas Abraham <thomas.abraham at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-exynos/Kconfig           |   22 +++++++++-
 arch/arm/mach-exynos/Makefile          |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c |   78 ++++++++++++++++++++++++++++++++
 3 files changed, 100 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-exynos/mach-exynos5-dt.c

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index a2ed05c..ac24386 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -362,7 +362,18 @@ config MACH_SMDK4412
 	  Machine support for Samsung SMDK4412
 endif
 
-comment "Flattened Device Tree based board for Exynos4 based SoC"
+if ARCH_EXYNOS5
+
+comment "EXYNOS5250 Boards"
+
+config MACH_SMDK5250
+	bool "SMDK5250"
+	select SOC_EXYNOS5250
+	help
+	  Machine support for Samsung SMDK5250
+endif
+
+comment "Flattened Device Tree based board for EXYNOS SoCs"
 
 config MACH_EXYNOS4_DT
 	bool "Samsung Exynos4 Machine using device tree"
@@ -376,6 +387,15 @@ config MACH_EXYNOS4_DT
 	  Note: This is under development and not all peripherals can be supported
 	  with this machine file.
 
+config MACH_EXYNOS5_DT
+	bool "SAMSUNG EXYNOS5 Machine using device tree"
+	select SOC_EXYNOS5250
+	select USE_OF
+	select ARM_AMBA
+	help
+	  Machine support for Samsung Exynos4 machine with device tree enabled.
+	  Select this if a fdt blob is available for the EXYNOS4 SoC based board.
+
 if ARCH_EXYNOS4
 
 comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 7214092..29967ef 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_MACH_SMDK4212)		+= mach-smdk4x12.o
 obj-$(CONFIG_MACH_SMDK4412)		+= mach-smdk4x12.o
 
 obj-$(CONFIG_MACH_EXYNOS4_DT)		+= mach-exynos4-dt.o
+obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
 
 # device support
 
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
new file mode 100644
index 0000000..0d26f50
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -0,0 +1,78 @@
+/*
+ * SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/of_platform.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/regs-serial.h>
+
+#include "common.h"
+
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the EXYNOS5 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
+				"exynos4210-uart.0", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
+				"exynos4210-uart.1", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
+				"exynos4210-uart.2", NULL),
+	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
+				"exynos4210-uart.3", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
+	{},
+};
+
+static void __init exynos5250_dt_map_io(void)
+{
+	exynos_init_io(NULL, 0);
+	s3c24xx_init_clocks(24000000);
+}
+
+static void __init exynos5250_dt_machine_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+				exynos5250_auxdata_lookup, NULL);
+}
+
+static char const *exynos5250_dt_compat[] __initdata = {
+	"samsung,exynos5250",
+	NULL
+};
+
+DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
+	/* Maintainer: Kukjin Kim <kgene.kim at samsung.com> */
+	.init_irq	= exynos5_init_irq,
+	.map_io		= exynos5250_dt_map_io,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= exynos5250_dt_machine_init,
+	.timer		= &exynos4_timer,
+	.dt_compat	= exynos5250_dt_compat,
+	.restart        = exynos5_restart,
+MACHINE_END
-- 
1.7.4.4



From kgene.kim at samsung.com  Wed Mar 14 10:42:18 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 07:42:18 -0700
Subject: [PATCH v4 12/12] ARM: dts: add initial dts file for EXYNOS5250,
 SMDK5250
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1331736138-28964-13-git-send-email-kgene.kim@samsung.com>

This patch adds initial dts file for EXYNOS5250 SoC. This dts
file is including the SoC specific devices and properties. And
adds the dts file for SMDK5250 board which uses the EXYNOS5250
dts file. Its board specific properites will be added later.

Cc: Thomas Abraham <thomas.abraham at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   26 ++
 arch/arm/boot/dts/exynos5250.dtsi         |  413 +++++++++++++++++++++++++++++
 2 files changed, 439 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos5250-smdk5250.dts
 create mode 100644 arch/arm/boot/dts/exynos5250.dtsi

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
new file mode 100644
index 0000000..399d17b
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -0,0 +1,26 @@
+/*
+ * SAMSUNG SMDK5250 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+	compatible = "samsung,smdk5250", "samsung,exynos5250";
+
+	memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	chosen {
+		bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
+	};
+};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
new file mode 100644
index 0000000..dfc4335
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -0,0 +1,413 @@
+/*
+ * SAMSUNG EXYNOS5250 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
+ * EXYNOS5250 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
+ * additional nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "samsung,exynos5250";
+	interrupt-parent = <&gic>;
+
+	gic:interrupt-controller at 10490000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+	};
+
+	watchdog {
+		compatible = "samsung,s3c2410-wdt";
+		reg = <0x101D0000 0x100>;
+		interrupts = <0 42 0>;
+	};
+
+	rtc {
+		compatible = "samsung,s3c6410-rtc";
+		reg = <0x101E0000 0x100>;
+		interrupts = <0 43 0>, <0 44 0>;
+	};
+
+	sdhci at 12200000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12200000 0x100>;
+		interrupts = <0 75 0>;
+	};
+
+	sdhci at 12210000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12210000 0x100>;
+		interrupts = <0 76 0>;
+	};
+
+	sdhci at 12220000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12220000 0x100>;
+		interrupts = <0 77 0>;
+	};
+
+	sdhci at 12230000 {
+		compatible = "samsung,exynos4210-sdhci";
+		reg = <0x12230000 0x100>;
+		interrupts = <0 78 0>;
+	};
+
+	serial at 12C00000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C00000 0x100>;
+		interrupts = <0 51 0>;
+	};
+
+	serial at 12C10000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C10000 0x100>;
+		interrupts = <0 52 0>;
+	};
+
+	serial at 12C20000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C20000 0x100>;
+		interrupts = <0 53 0>;
+	};
+
+	serial at 12C30000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x12C30000 0x100>;
+		interrupts = <0 54 0>;
+	};
+
+	i2c at 12C60000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C60000 0x100>;
+		interrupts = <0 56 0>;
+	};
+
+	i2c at 12C70000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C70000 0x100>;
+		interrupts = <0 57 0>;
+	};
+
+	i2c at 12C80000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C80000 0x100>;
+		interrupts = <0 58 0>;
+	};
+
+	i2c at 12C90000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12C90000 0x100>;
+		interrupts = <0 59 0>;
+	};
+
+	i2c at 12CA0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CA0000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c at 12CB0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CB0000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c at 12CC0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CC0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c at 12CD0000 {
+		compatible = "samsung,s3c2440-i2c";
+		reg = <0x12CD0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		pdma0: pdma at 121A0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x121A0000 0x1000>;
+			interrupts = <0 34 0>;
+		};
+
+		pdma1: pdma at 121B0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x121B0000 0x1000>;
+			interrupts = <0 35 0>;
+		};
+
+		mdma0: pdma at 10800000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x10800000 0x1000>;
+			interrupts = <0 33 0>;
+		};
+
+		mdma1: pdma at 11C10000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x11C10000 0x1000>;
+			interrupts = <0 124 0>;
+		};
+	};
+
+	gpio-controllers {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		gpio-controller;
+		ranges;
+
+		gpa0: gpio-controller at 11400000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpa1: gpio-controller at 11400020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpa2: gpio-controller at 11400040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb0: gpio-controller at 11400060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb1: gpio-controller at 11400080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb2: gpio-controller at 114000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpb3: gpio-controller at 114000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc0: gpio-controller at 114000E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114000E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc1: gpio-controller at 11400100 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400100 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc2: gpio-controller at 11400120 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400120 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpc3: gpio-controller at 11400140 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400140 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd0: gpio-controller at 11400160 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400160 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpd1: gpio-controller at 11400180 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400180 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy0: gpio-controller at 114001A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy1: gpio-controller at 114001C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy2: gpio-controller at 114001E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x114001E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy3: gpio-controller at 11400200 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400200 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy4: gpio-controller at 11400220 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400220 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy5: gpio-controller at 11400240 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400240 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpy6: gpio-controller at 11400260 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400260 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx0: gpio-controller at 11400C00 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C00 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx1: gpio-controller at 11400C20 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C20 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx2: gpio-controller at 11400C40 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C40 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpx3: gpio-controller at 11400C60 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x11400C60 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpe0: gpio-controller at 13400000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpe1: gpio-controller at 13400020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf0: gpio-controller at 13400040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpf1: gpio-controller at 13400060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpg0: gpio-controller at 13400080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpg1: gpio-controller at 134000A0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x134000A0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpg2: gpio-controller at 134000C0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x134000C0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gph0: gpio-controller at 134000E0 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x134000E0 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gph1: gpio-controller at 13400100 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x13400100 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv0: gpio-controller at 10D10000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10000 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv1: gpio-controller at 10D10020 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10020 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv2: gpio-controller at 10D10040 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10040 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv3: gpio-controller at 10D10060 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10060 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpv4: gpio-controller at 10D10080 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x10D10080 0x20>;
+			#gpio-cells = <4>;
+		};
+
+		gpz: gpio-controller at 03860000 {
+			compatible = "samsung,exynos4-gpio";
+			reg = <0x03860000 0x20>;
+			#gpio-cells = <4>;
+		};
+	};
+};
-- 
1.7.4.4



From arnd at arndb.de  Wed Mar 14 10:56:39 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 14:56:39 +0000
Subject: [PATCH 02/10] ARM: ux500: Initial Device Tree support for Snowball
In-Reply-To: <4F60AD39.6020009@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <201203141358.03541.arnd@arndb.de> <4F60AD39.6020009@linaro.org>
Message-ID: <201203141456.40135.arnd@arndb.de>

On Wednesday 14 March 2012, Lee Jones wrote:
> Sorry I missed that.
> 
> Just for my clarification, how important is that?
> 
> Is it re-spin a patch-set important?
> 
No need to send the patches out by email for this, but
please fix it up for the pull request.

	Arnd


From robherring2 at gmail.com  Wed Mar 14 11:00:16 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 14 Mar 2012 10:00:16 -0500
Subject: [PATCH 08/10] ARM: ux500: Enable PL011 AMBA UART Controller for
 Device Tree
In-Reply-To: <1331730306-11461-9-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-9-git-send-email-lee.jones@linaro.org>
Message-ID: <4F60B280.1080404@gmail.com>

On 03/14/2012 08:05 AM, Lee Jones wrote:
> Enables the 3 UARTs found on a u8500 using DT.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/boot/dts/db8500.dtsi      |    6 +++---
>  arch/arm/boot/dts/snowball.dts     |   12 ++++++++++++
>  arch/arm/mach-ux500/board-mop500.c |    4 +++-
>  3 files changed, 18 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
> index 35d0146..9b5e06e 100644
> --- a/arch/arm/boot/dts/db8500.dtsi
> +++ b/arch/arm/boot/dts/db8500.dtsi
> @@ -208,19 +208,19 @@
>  		uart at 80120000 {
>  			compatible = "arm,pl011", "arm,primecell";
>  			reg = <0x80120000 0x1000>;
> -			interrupts = <11>;
> +			interrupts = <0 11 0x4>;
>  			status = "disabled";
>  		};
>  		uart at 80121000 {
>  			compatible = "arm,pl011", "arm,primecell";
>  			reg = <0x80121000 0x1000>;
> -			interrupts = <19>;
> +			interrupts = <0 19 0x4>;
>  			status = "disabled";
>  		};
>  		uart at 80007000 {
>  			compatible = "arm,pl011", "arm,primecell";
>  			reg = <0x80007000 0x1000>;
> -			interrupts = <26>;
> +			interrupts = <0 26 0x4>;
>  			status = "disabled";
>  		};
>  
> diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
> index 34bfd79..359c6d6 100644
> --- a/arch/arm/boot/dts/snowball.dts
> +++ b/arch/arm/boot/dts/snowball.dts
> @@ -96,6 +96,18 @@
>  			status = "enabled";
>  		};
>  
> +		uart at 80120000 {
> +			status = "okay";
> +		};
> +
> +		uart at 80121000 {
> +			status = "okay";
> +		};
> +
> +		uart at 80007000 {
> +			status = "okay";
> +		};
> +
>  		i2c at 80004000 {
>  			tc3589x at 42 {
>  				//compatible = "tc3589x";
> diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
> index 482b86e..ea0242a 100644
> --- a/arch/arm/mach-ux500/board-mop500.c
> +++ b/arch/arm/mach-ux500/board-mop500.c
> @@ -746,6 +746,9 @@ MACHINE_END
>  #ifdef CONFIG_MACH_UX500_DT
>  
>  struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
> +	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
> +	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
> +	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),

Unless I'm blind, the pl011 driver doesn't take any platform data.

Rob

>  	{},
>  };
>  
> @@ -802,7 +805,6 @@ static void __init u8500_init_machine(void)
>  	}
>  	mop500_i2c_init(parent);
>  	mop500_spi_init(parent);
> -	mop500_uart_init(parent);
>  
>  	i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
>  	i2c_register_board_info(2, mop500_i2c2_devices,



From sr at denx.de  Wed Mar 14 11:00:32 2012
From: sr at denx.de (Stefan Roese)
Date: Wed, 14 Mar 2012 16:00:32 +0100
Subject: [PATCH v2] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
Message-ID: <1331737232-25477-1-git-send-email-sr@denx.de>

This patch adds a generic target for SPEAr600 board that can be
configured via the device-tree. Currently the following devices
are supported via the devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
follow in later patches.

Only the spear600-evb is currently supported. Other SPEAr600
based boards will follow later.

Additionally the file spear600.c is deleted. It contained only
one empty function and is not needed. So lets just remove it.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Viresh Kumar <viresh.kumar at st.com>
Cc: Arnd Bergmann <arnd at arndb.de>
---
v2:
- Added DT support to spear6xx.c instead of creating board-dt.c
- Removed UART (PL011) and GPIO (PL061) platform data for
  devicetree board port. This works now via DT probing
- Added OF_DEV_AUXDATA for clock device name matching for some
  device drivers
- Removed sper600.c file completely
- Added DW I2C and ethernet nodes to the dts files
- Added other DT nodes (SMI, FSMC, ECHI, OHCI), currently disabled
  since the corresponding device drivers don't support DT probing
- Removed Linaro/FSL copyright notice from SPEAr DT files (copy-paste cruft)
- Many smaller modification to the dts/dtsi files
- Changed Documentation/devicetree/bindings/arm/spear.txt to match
  the changed bindings

 Documentation/devicetree/bindings/arm/spear.txt |    8 ++
 arch/arm/boot/dts/spear600-evb.dts              |   30 +++++
 arch/arm/boot/dts/spear600.dtsi                 |  162 +++++++++++++++++++++++
 arch/arm/mach-spear6xx/Kconfig                  |    7 +
 arch/arm/mach-spear6xx/Makefile                 |    3 -
 arch/arm/mach-spear6xx/spear600.c               |   25 ----
 arch/arm/mach-spear6xx/spear600_evb.c           |    3 -
 arch/arm/mach-spear6xx/spear6xx.c               |   69 +++++++++-
 8 files changed, 270 insertions(+), 37 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
 create mode 100644 arch/arm/boot/dts/spear600-evb.dts
 create mode 100644 arch/arm/boot/dts/spear600.dtsi
 delete mode 100644 arch/arm/mach-spear6xx/spear600.c

diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
new file mode 100644
index 0000000..f8e54f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -0,0 +1,8 @@
+ST SPEAr Platforms Device Tree Bindings
+---------------------------------------
+
+Boards with the ST SPEAr600 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear600";
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
new file mode 100644
index 0000000..cbfda8d
--- /dev/null
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear600.dtsi"
+
+/ {
+	model = "ST SPEAr600 Evaluation Board";
+	compatible = "st,spear600-evb", "st,spear600";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	soc {
+		gmac0: ethernet at e0800000 {
+			phy-mode = "gmii";
+		};
+
+		i2c at d0200000 {
+			clock-frequency = <400000>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
new file mode 100644
index 0000000..e45e58f
--- /dev/null
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "st,spear600";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0>; /* Filled by U-Boot */
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vic0: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		vic1: interrupt-controller at f1000000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		serial at d0000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xd0000000 0x1000>;
+			interrupt-parent = <&vic0>;
+			interrupts = <24>;
+		};
+
+		serial at d0080000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xd0080000 0x1000>;
+			interrupt-parent = <&vic0>;
+			interrupts = <25>;
+		};
+
+		/* local/cpu GPIO */
+		gpio0: gpio at f0100000 {
+			#gpio-cells = <2>;
+			compatible = "arm,pl061", "arm,primecell";
+			gpio-controller;
+			reg = <0xf0100000 0x1000>;
+			interrupt-parent = <&vic0>;
+			interrupts = <18>;
+		};
+
+		/* basic GPIO */
+		gpio1: gpio at fc980000 {
+			#gpio-cells = <2>;
+			compatible = "arm,pl061", "arm,primecell";
+			gpio-controller;
+			reg = <0xfc980000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <19>;
+		};
+
+		/* appl GPIO */
+		gpio2: gpio at d8100000 {
+			#gpio-cells = <2>;
+			compatible = "arm,pl061", "arm,primecell";
+			gpio-controller;
+			reg = <0xd8100000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <4>;
+		};
+
+		gmac0: ethernet at e0800000 {
+			compatible = "st,spear600-gmac";
+			reg = <0xe0800000 0x8000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <24 23>;
+			interrupt-names = "macirq", "eth_wake_irq";
+			mac-address = [000000000000]; /* Filled in by U-Boot */
+		};
+
+		i2c at d0200000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xd0200000 0x1000>;
+			interrupt-parent = <&vic0>;
+			interrupts = <28>;
+		};
+
+		fsmc0: flash at d1800000 {
+			status = "disabled";
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd1800000 0x1000	/* FSMC Register */
+			       0xd2000000 0x4000>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+		};
+
+		smi0: flash at fc000000 {
+			status = "disabled";
+			compatible = "st,spear600-smi";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xfc000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <12>;
+		};
+
+		ehci at e1800000 {
+			status = "disabled";
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe1800000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <27>;
+		};
+
+		ehci at e2000000 {
+			status = "disabled";
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe2000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <29>;
+		};
+
+		ohci at e1900000 {
+			status = "disabled";
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe1900000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <26>;
+		};
+
+		ohci at e2100000 {
+			status = "disabled";
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe2100000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <28>;
+		};
+	};
+};
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
index ff4ae5b..7777f72 100644
--- a/arch/arm/mach-spear6xx/Kconfig
+++ b/arch/arm/mach-spear6xx/Kconfig
@@ -11,6 +11,13 @@ config BOARD_SPEAR600_EVB
 	help
 	  Supports ST SPEAr600 Evaluation Board
 
+config BOARD_SPEAR600_DT
+	bool "SPEAr600 generic board configured via device-tree"
+	select MACH_SPEAR600
+	select USE_OF
+	help
+	  Supports ST SPEAr600 boards configured via the device-tree
+
 endmenu
 
 config MACH_SPEAR600
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index cc1a4d8..6f87c3a 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -5,8 +5,5 @@
 # common files
 obj-y	+= clock.o spear6xx.o
 
-# spear600 specific files
-obj-$(CONFIG_MACH_SPEAR600) += spear600.o
-
 # spear600 boards files
 obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
diff --git a/arch/arm/mach-spear6xx/spear600.c b/arch/arm/mach-spear6xx/spear600.c
deleted file mode 100644
index d0e6eea..0000000
--- a/arch/arm/mach-spear6xx/spear600.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/spear600.c
- *
- * SPEAr600 machine source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/ptrace.h>
-#include <asm/irq.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* Add spear600 specific devices here */
-
-void __init spear600_init(void)
-{
-	/* call spear6xx family common init function */
-	spear6xx_init();
-}
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index c6e4254..c4949aa 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -32,9 +32,6 @@ static void __init spear600_evb_init(void)
 {
 	unsigned int i;
 
-	/* call spear600 machine init function */
-	spear600_init();
-
 	/* Add Platform Devices */
 	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
 
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index e0f6628..aca20f0 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -6,6 +6,8 @@
  * Copyright (C) 2009 ST Microelectronics
  * Rajeev Kumar<rajeev-dlh.kumar at st.com>
  *
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
@@ -15,6 +17,10 @@
 #include <linux/amba/pl061.h>
 #include <linux/ptrace.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <asm/hardware/vic.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -99,12 +105,6 @@ struct amba_device gpio_device[] = {
 	}
 };
 
-/* This will add devices, and do machine specific tasks */
-void __init spear6xx_init(void)
-{
-	/* nothing to do for now */
-}
-
 /* This will initialize vic */
 void __init spear6xx_init_irq(void)
 {
@@ -181,3 +181,60 @@ static void __init spear6xx_timer_init(void)
 struct sys_timer spear6xx_timer = {
 	.init = spear6xx_timer_init,
 };
+
+/*
+ * Devicetree specific init structs/functions:
+ * Once the SPEAr600 devicetree support has matured, we can remove
+ * spear600_evb.c and the non-devicetree support above in this file.
+ */
+
+/*
+ * Add auxdata so that clock name matching doesn't fail in device
+ * drivers
+ */
+struct of_dev_auxdata spear600_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl011", SPEAR6XX_ICM1_UART0_BASE,
+		       "uart0", NULL),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR6XX_ICM1_UART1_BASE,
+		       "uart1", NULL),
+	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_CPU_GPIO_BASE,
+		       "gpio0", NULL),
+	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_ICM3_GPIO_BASE,
+		       "gpio1", NULL),
+	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_ICM2_GPIO_BASE,
+		       "gpio2", NULL),
+	OF_DEV_AUXDATA("snps,designware-i2c", SPEAR6XX_ICM1_I2C_BASE,
+		       "i2c_designware.0", NULL),
+	{}
+};
+
+static void __init spear600_dt_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+			     spear600_auxdata_lookup, NULL);
+}
+
+static const char *spear600_dt_board_compat[] = {
+	"st,spear600",
+	NULL
+};
+
+static const struct of_device_id vic_of_match[] __initconst = {
+	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ /* Sentinel */ }
+};
+
+static void __init spear6xx_dt_init_irq(void)
+{
+	of_irq_init(vic_of_match);
+}
+
+DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
+	.map_io		=	spear6xx_map_io,
+	.init_irq	=	spear6xx_dt_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear6xx_timer,
+	.init_machine	=	spear600_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear600_dt_board_compat,
+MACHINE_END
-- 
1.7.9.2



From robherring2 at gmail.com  Wed Mar 14 11:02:42 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 14 Mar 2012 10:02:42 -0500
Subject: [PATCH 07/10] ARM: ux500: Provide local timer support for Device
 Tree
In-Reply-To: <1331730306-11461-8-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-8-git-send-email-lee.jones@linaro.org>
Message-ID: <4F60B312.8070900@gmail.com>

On 03/14/2012 08:05 AM, Lee Jones wrote:
> This enables local timer (AKA: private timer) support for
> all u8500 based hardware using DT.
> 
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  arch/arm/boot/dts/db8500.dtsi    |    6 ++++++
>  arch/arm/mach-ux500/localtimer.c |   18 +++++++++++++++++-
>  2 files changed, 23 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
> index cce5df8..35d0146 100644
> --- a/arch/arm/boot/dts/db8500.dtsi
> +++ b/arch/arm/boot/dts/db8500.dtsi
> @@ -34,6 +34,12 @@
>  			interrupts = <7>;
>  		};
>  
> +		timer at a0410600 {
> +			compatible = "arm,smp-twd";
> +			reg = <0xa0410600 0x20>;
> +			interrupts = <1 13 0x304>;
> +		};
> +
>  		rtc at 80154000 {
>  			compatible = "stericsson,db8500-rtc";
>  			reg = <0x80154000 0x1000>;
> diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
> index 5ba1133..295e580 100644
> --- a/arch/arm/mach-ux500/localtimer.c
> +++ b/arch/arm/mach-ux500/localtimer.c
> @@ -14,6 +14,10 @@
>  #include <linux/smp.h>
>  #include <linux/clockchips.h>
>  
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
>  #include <asm/irq.h>
>  #include <asm/smp_twd.h>
>  #include <asm/localtimer.h>
> @@ -23,7 +27,19 @@
>   */
>  int __cpuinit local_timer_setup(struct clock_event_device *evt)
>  {
> -	evt->irq = IRQ_LOCALTIMER;
> +	struct device_node *np;
> +
> +	np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
> +	if (np) {
> +		if (!twd_base) {
> +			twd_base = of_iomap(np, 0);
> +			WARN_ON(!twd_base);
> +		}
> +		evt->irq = irq_of_parse_and_map(np, 0);
> +	}
> +	else
> +		evt->irq = IRQ_LOCALTIMER;
> +
>  	twd_timer_setup(evt);
>  	return 0;
>  }

FYI, this will probably collide with Marc Z's local timer changes queued
up for 3.4.

Rob



From dwalker at fifo99.com  Wed Mar 14 11:05:53 2012
From: dwalker at fifo99.com (Daniel Walker)
Date: Wed, 14 Mar 2012 08:05:53 -0700
Subject: [PATCH v3 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 DMA APIs
In-Reply-To: <4F5F41AF.1090907@codeaurora.org>
References: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>
 <20120312201421.GA3459@fifo99.com>
 <4F5F41AF.1090907@codeaurora.org>
Message-ID: <20120314150533.GA8757@fifo99.com>

On Tue, Mar 13, 2012 at 06:16:39PM +0530, Ravi Kumar V wrote:
> On 3/13/2012 1:44 AM, Daniel Walker wrote:
> >On Mon, Mar 12, 2012 at 04:02:44PM +0530, Ravi Kumar V wrote:
> >>Add DMAEngine based driver using the old MSM DMA APIs internally.
> >
> >What do you mean by this?
> >
> There is a MSM DMA driver in arch/arm/mach-msm/ which is not in
> dmaengine framework standards, but that driver is been used by
> client drivers nand, eMMC and serial drivers. Now if we implement
> the whole dma driver using dmaengine framework then nand, eMMC like
> drivers will be failed as they are using old dma driver API's, so
> instead of implementing new driver from scratch we are keeping the
> old dma API's as it is and using those API's in new dmaengine
> framework.So that we can convert clients drivers to use dma engine
> framework.

Did you investigate converting the drivers (nand, eMMC, serial) ? It
seems like there would be a 1:1 mapping between the API's , so it might
only be a find->replace operation.

Daniel


From marc.zyngier at arm.com  Wed Mar 14 11:16:56 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Wed, 14 Mar 2012 15:16:56 +0000
Subject: [PATCH 07/10] ARM: ux500: Provide local timer support for Device
 Tree
In-Reply-To: <4F60B312.8070900@gmail.com>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-8-git-send-email-lee.jones@linaro.org>
 <4F60B312.8070900@gmail.com>
Message-ID: <4F60B668.2080209@arm.com>

On 14/03/12 15:02, Rob Herring wrote:
> On 03/14/2012 08:05 AM, Lee Jones wrote:
>> This enables local timer (AKA: private timer) support for
>> all u8500 based hardware using DT.
>>
>> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>> ---
>>  arch/arm/boot/dts/db8500.dtsi    |    6 ++++++
>>  arch/arm/mach-ux500/localtimer.c |   18 +++++++++++++++++-
>>  2 files changed, 23 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
>> index cce5df8..35d0146 100644
>> --- a/arch/arm/boot/dts/db8500.dtsi
>> +++ b/arch/arm/boot/dts/db8500.dtsi
>> @@ -34,6 +34,12 @@
>>  			interrupts = <7>;
>>  		};
>>  
>> +		timer at a0410600 {
>> +			compatible = "arm,smp-twd";
>> +			reg = <0xa0410600 0x20>;
>> +			interrupts = <1 13 0x304>;
>> +		};
>> +
>>  		rtc at 80154000 {
>>  			compatible = "stericsson,db8500-rtc";
>>  			reg = <0x80154000 0x1000>;
>> diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
>> index 5ba1133..295e580 100644
>> --- a/arch/arm/mach-ux500/localtimer.c
>> +++ b/arch/arm/mach-ux500/localtimer.c
>> @@ -14,6 +14,10 @@
>>  #include <linux/smp.h>
>>  #include <linux/clockchips.h>
>>  
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +
>>  #include <asm/irq.h>
>>  #include <asm/smp_twd.h>
>>  #include <asm/localtimer.h>
>> @@ -23,7 +27,19 @@
>>   */
>>  int __cpuinit local_timer_setup(struct clock_event_device *evt)
>>  {
>> -	evt->irq = IRQ_LOCALTIMER;
>> +	struct device_node *np;
>> +
>> +	np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
>> +	if (np) {
>> +		if (!twd_base) {
>> +			twd_base = of_iomap(np, 0);
>> +			WARN_ON(!twd_base);
>> +		}
>> +		evt->irq = irq_of_parse_and_map(np, 0);
>> +	}
>> +	else
>> +		evt->irq = IRQ_LOCALTIMER;
>> +
>>  	twd_timer_setup(evt);
>>  	return 0;
>>  }
> 
> FYI, this will probably collide with Marc Z's local timer changes queued
> up for 3.4.

Indeed. localtimer.c is gone in -next. This can be replaced by a single
call to twd_local_timer_of_register() from your board file.

See arch/arm/mach-highbank/highbank.c for reference ;-).

	M.
-- 
Jazz is not dead. It just smells funny...



From nico at fluxnic.net  Wed Mar 14 11:26:19 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 14 Mar 2012 11:26:19 -0400 (EDT)
Subject: [PATCH v3 2/5] ARM: Add a printk loglevel modifier
In-Reply-To: <1331720516-11801-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
 <1331720516-11801-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <alpine.LFD.2.02.1203141125120.24151@xanadu.home>

On Wed, 14 Mar 2012, Uwe Kleine-K?nig wrote:

> This is a needed followup for
> 
> 	ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15
> 
> otherwise no newline is printed for !CONFIG_CPU_CP15
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
> Should this be folded into the
> 
> 	ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15
> 
> patch? Or should it come before it?

Given my comments on that other patch, this one could be dropped 
altogether.


Nicolas

From nico at fluxnic.net  Wed Mar 14 11:28:58 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 14 Mar 2012 11:28:58 -0400 (EDT)
Subject: [PATCH v3 3/5] ARM: force branch instructions to use long distance
 encoding
In-Reply-To: <1331720516-11801-2-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
 <1331720516-11801-2-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <alpine.LFD.2.02.1203141126470.24151@xanadu.home>

On Wed, 14 Mar 2012, Uwe Kleine-K?nig wrote:

> This fixes a linker error when the kernel image gets bigger than approx.
> 1 MiB.
> 
> This is done analogous to the change to head.S in commit
> 
> 	a75e524 (ARM: 6504/1: Thumb-2: Fix long-distance conditional 
branches in head.S for Thumb-2.)
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
>  arch/arm/kernel/head-nommu.S |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
> index d46f259..1aca35d 100644
> --- a/arch/arm/kernel/head-nommu.S
> +++ b/arch/arm/kernel/head-nommu.S
> @@ -51,6 +51,7 @@ ENTRY(stext)
>  #endif
>  	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
>  	movs	r10, r5				@ invalid processor (r5=0)?
> +	it	eq

Like in the other cases, please add a short comment on that line 
justifying it, otherwise it may look redundant.


Nicolas

From lee.jones at linaro.org  Wed Mar 14 11:36:32 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 15:36:32 +0000
Subject: [PATCH 08/10] ARM: ux500: Enable PL011 AMBA UART Controller for
 Device Tree
In-Reply-To: <4F60B280.1080404@gmail.com>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-9-git-send-email-lee.jones@linaro.org>
 <4F60B280.1080404@gmail.com>
Message-ID: <4F60BB00.2080306@linaro.org>

On 14/03/12 15:00, Rob Herring wrote:
> On 03/14/2012 08:05 AM, Lee Jones wrote:
>> Enables the 3 UARTs found on a u8500 using DT.
>>
>> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>> ---
>>  arch/arm/boot/dts/db8500.dtsi      |    6 +++---
>>  arch/arm/boot/dts/snowball.dts     |   12 ++++++++++++
>>  arch/arm/mach-ux500/board-mop500.c |    4 +++-
>>  3 files changed, 18 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
>> index 35d0146..9b5e06e 100644
>> --- a/arch/arm/boot/dts/db8500.dtsi
>> +++ b/arch/arm/boot/dts/db8500.dtsi
>> @@ -208,19 +208,19 @@
>>  		uart at 80120000 {
>>  			compatible = "arm,pl011", "arm,primecell";
>>  			reg = <0x80120000 0x1000>;
>> -			interrupts = <11>;
>> +			interrupts = <0 11 0x4>;
>>  			status = "disabled";
>>  		};
>>  		uart at 80121000 {
>>  			compatible = "arm,pl011", "arm,primecell";
>>  			reg = <0x80121000 0x1000>;
>> -			interrupts = <19>;
>> +			interrupts = <0 19 0x4>;
>>  			status = "disabled";
>>  		};
>>  		uart at 80007000 {
>>  			compatible = "arm,pl011", "arm,primecell";
>>  			reg = <0x80007000 0x1000>;
>> -			interrupts = <26>;
>> +			interrupts = <0 26 0x4>;
>>  			status = "disabled";
>>  		};
>>  
>> diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
>> index 34bfd79..359c6d6 100644
>> --- a/arch/arm/boot/dts/snowball.dts
>> +++ b/arch/arm/boot/dts/snowball.dts
>> @@ -96,6 +96,18 @@
>>  			status = "enabled";
>>  		};
>>  
>> +		uart at 80120000 {
>> +			status = "okay";
>> +		};
>> +
>> +		uart at 80121000 {
>> +			status = "okay";
>> +		};
>> +
>> +		uart at 80007000 {
>> +			status = "okay";
>> +		};
>> +
>>  		i2c at 80004000 {
>>  			tc3589x at 42 {
>>  				//compatible = "tc3589x";
>> diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
>> index 482b86e..ea0242a 100644
>> --- a/arch/arm/mach-ux500/board-mop500.c
>> +++ b/arch/arm/mach-ux500/board-mop500.c
>> @@ -746,6 +746,9 @@ MACHINE_END
>>  #ifdef CONFIG_MACH_UX500_DT
>>  
>>  struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
>> +	OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
>> +	OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
>> +	OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
> 
> Unless I'm blind, the pl011 driver doesn't take any platform data.

I guess you must be blind then? =:-)

linux/amba/serial.h:

struct amba_pl011_data {
        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
        void *dma_rx_param;
        void *dma_tx_param;
        void (*init) (void);
        void (*exit) (void);
        void (*reset) (void);
};

>>  	{},
>>  };
>>  
>> @@ -802,7 +805,6 @@ static void __init u8500_init_machine(void)
>>  	}
>>  	mop500_i2c_init(parent);
>>  	mop500_spi_init(parent);
>> -	mop500_uart_init(parent);
>>  
>>  	i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
>>  	i2c_register_board_info(2, mop500_i2c2_devices,
> 


-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From cjb at laptop.org  Wed Mar 14 11:37:24 2012
From: cjb at laptop.org (Chris Ball)
Date: Wed, 14 Mar 2012 11:37:24 -0400
Subject: [PATCH v2 0/4] omap hsmmc device tree support
In-Reply-To: <1331564560-23276-1-git-send-email-rnayak@ti.com> (Rajendra
 Nayak's message of "Mon, 12 Mar 2012 20:32:36 +0530")
References: <1331564560-23276-1-git-send-email-rnayak@ti.com>
Message-ID: <87pqcfdwi3.fsf@laptop.org>

Hi,

On Mon, Mar 12 2012, Rajendra Nayak wrote:
> The series adds device tree support for OMAP hsmmc
> driver.
>
> Changes in V2:
> -1- Minor fixes based on comments from Grant.
> -2- Added a seperate compatible for omap3.
> -3- Added a new binding "ti,needs-special-reset"
> to handle some mmc modules which need special
> softreset sequence.
> -4- Updated board dts files with "status = disable;"
> for unused mmc modules.
>
> Rob,
> I retained your ack on patch 1 despite the additional
> binding that I added to handle the special softreset
> sequence. Let me know if you have any issues with it.
>
> Chris.
> Patch 1 and Patch 2 apply cleanly on mmc-next and can
> be taken in from the mmc tree after relevent acks from
> DT folks.
> Patch 3 and Patch 4 which update dts files, I plan to
> push via linux-omap/Tony's tree.

Thanks, I've pushed patches 1 and 2 to mmc-next for 3.4, with Balaji's
Tested-by.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From grant.likely at secretlab.ca  Wed Mar 14 11:44:26 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Wed, 14 Mar 2012 09:44:26 -0600
Subject: [GIT PULL] imx irq_domain migration
In-Reply-To: <4F6098C6.7050503@gmail.com>
References: <20120216154941.GB11758@r65073-Latitude-D630>
 <4F3D41D2.5090203@gmail.com>
 <20120314050837.GB21337@S2101-09.ap.freescale.net>
 <4F6098C6.7050503@gmail.com>
Message-ID: <CACxGe6tsHWj+bHcg1uEV8x-KE7B8p1Lj-_DL9mysYn1z+Bex3g@mail.gmail.com>

On Wed, Mar 14, 2012 at 7:10 AM, Rob Herring <robherring2 at gmail.com> wrote:
> On 03/14/2012 12:08 AM, Shawn Guo wrote:
>> On Thu, Feb 16, 2012 at 11:50:10AM -0600, Rob Herring wrote:
>>> Shawn,
>>>
>>> On 02/16/2012 09:49 AM, Shawn Guo wrote:
>>>> Hi Rob,
>>>>
>>>> Please pull imx irq_domain support below. It's based on Grant's
>>>> irqdomain/next today with your generic-chip series applied on top
>>>> of it.
>>>
>>> You're asking me to pull changes on top of a branch that I don't even
>>> have as you've rebased my changes. While it would work I don't think
>>> this is the right flow. Plus there is not really any reason for iMX
>>> changes to go thru me.
>>>
>>> Either Grant needs to stabilize his branch so you and I can send him
>>> pull requests or he can pull in our changes and rebase them as he
>>> rebases. I already asked him to do just that with my 1 patch others are
>>> dependent on.
>>>
>> Hi Grant,
>>
>> Would you consider to take this request after you take Rob's
>> generic_irq one?
>
> You'll need rebase your branch as I did since Grant did.

Also, the imx changes should go via the arm-soc tree, not the
irqdomain/next branch.  irqdomain/next is stable now, so you can use
it as your base.  Rebase your changes on top of it and ask Arnd or
Olof to pull the result into an arm-soc branch.

g.


From arnd at arndb.de  Wed Mar 14 11:54:25 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 15:54:25 +0000
Subject: [PATCH v2] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <1331737232-25477-1-git-send-email-sr@denx.de>
References: <1331737232-25477-1-git-send-email-sr@denx.de>
Message-ID: <201203141554.25262.arnd@arndb.de>

On Wednesday 14 March 2012, Stefan Roese wrote:
> This patch adds a generic target for SPEAr600 board that can be
> configured via the device-tree. Currently the following devices
> are supported via the devicetree:
> 
> - VIC interrupts
> - PL011 UART
> - PL061 GPIO
> - Synopsys DW I2C
> - Synopsys DW ethernet
> 
> Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
> follow in later patches.
> 
> Only the spear600-evb is currently supported. Other SPEAr600
> based boards will follow later.
> 
> Additionally the file spear600.c is deleted. It contained only
> one empty function and is not needed. So lets just remove it.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> Cc: Arnd Bergmann <arnd at arndb.de>

Looks very good to me.

Reviewed-by: Arnd Bergmann <arnd at arndb.de>


From thierry.reding at avionic-design.de  Wed Mar 14 11:56:23 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 16:56:23 +0100
Subject: [PATCH v4 00/10] Add PWM framework and device tree support.
Message-ID: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>

This patch series adds very rudimentary device-tree support for PWM
devices. With all of these patches applied (plus one board-specific
patch that is not included), I'm able to control the backlight on the
device I'm working on using the sysfs interface provided by the pwm-bl
driver and the backlight class.

This series is based on Sascha Hauer's series of patches[0] to add a
generic PWM framework. The first patch in this series is taken from
Sascha's branch, while the second patch enables each PWM chip to provide
multiple PWM devices (the Blackfin and PXA drivers have been ported to
the framework for reference). Currently a global namespace is still
provided to keep backwards-compatibility with the legacy PWM API. In
order to achieve this, the number of global PWM devices is limited to
1024. However, patch 2 introduces per-chip indexing of PWM devices in
the core and adds an API to request a PWM device given the PWM chip or
the struct device associated with a PWM chip. They are supposed to
eventually replace pwm_request() and allow to get rid of the global
namespace. The device tree support code does not use the global
namespace.

Patch 3 adds some code to lookup a PWM chip given its device-tree
handle. This code will be used later on by the pwm-bl driver to find the
PWM device that it should be using. If the no corresponding PWM chip is
available yet, the code returns EPROBE_DEFER to have users automatically
probed again later when the PWM provider may have become available.
Device tree binding documentation is also provided.

Patch 4 was taken from the Chromium tree and is required to provide
proper clocking of the Tegra2 PWFM controller. All Chromium-specific
tags have been removed from the commit message. Some cleanup of the
clock registration for Tegra is done in patch 5 because a subsequent
patch will instantiate one PWFM controller device instead of four.

Patch 6 adds a generic PWM framework driver for the Tegra2 PWFM
controller. The code is taken from the Chromium tree with some
adjustments to integrate it with the PWM framework. Device tree based
probing of the driver is implemented in patch 7.

Patches 8 and 9 are ports of the Blackfin PWM and the PXA PWM drivers to
the PWM framework. These are only compile-tested as I do not have any
hardware to test them on. They are meant as test-bed for the framework.
Sascha already has patches that port all in-tree drivers to the
framework and will rebase them on top of this series when it is ready.

Patch 10 implements DT-based probing in the pwm-backlight driver. Note
that this code only handles the "pwm" property (by looking up the PWM
device via the new PWM DT binding). Switching power to the backlight via
GPIOs is not supported yet. The DT binding also deviates from the
platform data in that it requires a list of brightness levels to be
specified instead of assuming a linearily spaced range from 0 to a given
maximum brightness.

The whole series is based on the linux-next tree from 20120314. I think
I've addressed all of the concerns raised in the first three versions.

Thierry

[0]: http://git.pengutronix.de/?p=imx/linux-2.6.git;a=shortlog;h=refs/heads/pwmlib

Sascha Hauer (1):
  PWM: add pwm framework support

Simon Que (1):
  ARM: tegra: Fix PWM clock programming

Thierry Reding (8):
  pwm: Allow chips to support multiple PWMs.
  pwm: Add device tree support
  ARM: tegra: Provide clock for only one PWM controller
  pwm: Add NVIDIA Tegra SoC support
  pwm: tegra: Add device tree support
  pwm: Add Blackfin support
  pwm: Add PXA support
  pwm-backlight: Add rudimentary device tree support

 Documentation/devicetree/bindings/pwm/pwm.txt      |   48 ++
 .../devicetree/bindings/pwm/tegra-pwm.txt          |   18 +
 .../bindings/video/backlight/pwm-backlight         |   19 +
 Documentation/pwm.txt                              |   56 ++
 MAINTAINERS                                        |    6 +
 arch/arm/boot/dts/tegra20.dtsi                     |    6 +
 arch/arm/boot/dts/tegra30.dtsi                     |    6 +
 arch/arm/mach-tegra/board-dt-tegra20.c             |    1 +
 arch/arm/mach-tegra/board-dt-tegra30.c             |    3 +
 arch/arm/mach-tegra/tegra2_clocks.c                |   37 +-
 arch/arm/plat-pxa/Makefile                         |    1 -
 arch/arm/plat-pxa/pwm.c                            |  304 -----------
 arch/blackfin/Kconfig                              |   10 -
 arch/blackfin/kernel/Makefile                      |    1 -
 arch/blackfin/kernel/pwm.c                         |  100 ----
 drivers/Kconfig                                    |    2 +
 drivers/Makefile                                   |    1 +
 drivers/of/Kconfig                                 |    6 +
 drivers/pwm/Kconfig                                |   40 ++
 drivers/pwm/Makefile                               |    4 +
 drivers/pwm/core.c                                 |  557 ++++++++++++++++++++
 drivers/pwm/pwm-bfin.c                             |  164 ++++++
 drivers/pwm/pwm-pxa.c                              |  244 +++++++++
 drivers/pwm/pwm-tegra.c                            |  267 ++++++++++
 drivers/video/backlight/Kconfig                    |    2 +-
 drivers/video/backlight/pwm_bl.c                   |  136 ++++-
 include/linux/of_pwm.h                             |   36 ++
 include/linux/pwm.h                                |   97 ++++
 include/linux/pwm_backlight.h                      |    2 +
 29 files changed, 1732 insertions(+), 442 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pwm/pwm.txt
 create mode 100644 Documentation/devicetree/bindings/pwm/tegra-pwm.txt
 create mode 100644 Documentation/devicetree/bindings/video/backlight/pwm-backlight
 create mode 100644 Documentation/pwm.txt
 delete mode 100644 arch/arm/plat-pxa/pwm.c
 delete mode 100644 arch/blackfin/kernel/pwm.c
 create mode 100644 drivers/pwm/Kconfig
 create mode 100644 drivers/pwm/Makefile
 create mode 100644 drivers/pwm/core.c
 create mode 100644 drivers/pwm/pwm-bfin.c
 create mode 100644 drivers/pwm/pwm-pxa.c
 create mode 100644 drivers/pwm/pwm-tegra.c
 create mode 100644 include/linux/of_pwm.h

-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 14 11:56:24 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 16:56:24 +0100
Subject: [PATCH v4 01/10] PWM: add pwm framework support
In-Reply-To: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331740593-10807-2-git-send-email-thierry.reding@avionic-design.de>

From: Sascha Hauer <s.hauer at pengutronix.de>

This patch adds framework support for PWM (pulse width modulation) devices.

The is a barebone PWM API already in the kernel under include/linux/pwm.h,
but it does not allow for multiple drivers as each of them implements the
pwm_*() functions.

There are other PWM framework patches around from Bill Gatliff. Unlike
his framework this one does not change the existing API for PWMs so that
this framework can act as a drop in replacement for the existing API.

Why another framework?

Several people argue that there should not be another framework for PWMs
but they should be integrated into one of the existing frameworks like led
or hwmon. Unlike these frameworks the PWM framework is agnostic to the
purpose of the PWM. In fact, a PWM can drive a LED, but this makes the
LED framework a user of a PWM, like already done in leds-pwm.c. The gpio
framework also is not suitable for PWMs. Every gpio could be turned into
a PWM using timer based toggling, but on the other hand not every PWM hardware
device can be turned into a gpio due to the lack of hardware capabilities.

This patch does not try to improve the PWM API yet, this could be done in
subsequent patches.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Acked-by: Kurt Van Dijck <kurt.van.dijck at eia.be>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
Reviewed-by: Matthias Kaehlcke <matthias at kaehlcke.net>
---
 Documentation/pwm.txt |   56 +++++++++++++
 MAINTAINERS           |    6 ++
 drivers/Kconfig       |    2 +
 drivers/Makefile      |    1 +
 drivers/pwm/Kconfig   |   12 +++
 drivers/pwm/Makefile  |    1 +
 drivers/pwm/core.c    |  220 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/pwm.h   |   37 +++++++++
 8 files changed, 335 insertions(+)
 create mode 100644 Documentation/pwm.txt
 create mode 100644 drivers/pwm/Kconfig
 create mode 100644 drivers/pwm/Makefile
 create mode 100644 drivers/pwm/core.c

diff --git a/Documentation/pwm.txt b/Documentation/pwm.txt
new file mode 100644
index 0000000..c7c5cb1
--- /dev/null
+++ b/Documentation/pwm.txt
@@ -0,0 +1,56 @@
+Pulse Width Modulation (PWM) interface
+
+This provides an overview about the Linux PWM interface
+
+PWMs are commonly used for controlling LEDs, fans or vibrators in
+cell phones. PWMs with a fixed purpose have no need implementing
+the Linux PWM API (although they could). However, PWMs are often
+found as discrete devices on SoCs which have no fixed purpose. It's
+up to the board designer to connect them to LEDs or fans. To provide
+this kind of flexibility the generic PWM API exists.
+
+Identifying PWMs
+----------------
+
+PWMs are identified by unique ids throughout the system. A platform
+should call pwmchip_reserve() during init time to reserve the id range
+for internal PWMs so that users have a fixed id to refer to specific
+PWMs.
+
+Using PWMs
+----------
+
+A PWM can be requested using pwm_request() and freed after usage with
+pwm_free(). After being requested a PWM has to be configured using
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
+
+To start/stop toggling the PWM output use pwm_enable()/pwm_disable().
+
+Implementing a PWM driver
+-------------------------
+
+Currently there are two ways to implement pwm drivers. Traditionally
+there only has been the barebone API meaning that each driver has
+to implement the pwm_*() functions itself. This means that it's impossible
+to have multiple PWM drivers in the system. For this reason it's mandatory
+for new drivers to use the generic PWM framework.
+A new PWM device can be added using pwmchip_add() and removed again with
+pwmchip_remove(). pwmchip_add() takes a filled in struct pwm_chip as
+argument which provides the ops and the pwm id to the framework.
+
+Locking
+-------
+
+The PWM core list manipulations are protected by a mutex, so pwm_request()
+and pwm_free() may not be called from an atomic context. Currently the
+PWM core does not enforce any locking to pwm_enable(), pwm_disable() and
+pwm_config(), so the calling context is currently driver specific. This
+is an issue derived from the former barebone API and should be fixed soon.
+
+Helpers
+-------
+
+Currently a PWM can only be configured with period_ns and duty_ns. For several
+use cases freq_hz and duty_percent might be better. Instead of calculating 
+this in your driver please consider adding appropriate helpers to the framework.
diff --git a/MAINTAINERS b/MAINTAINERS
index b9a1fb31..fd2c297 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5403,6 +5403,12 @@ S:	Maintained
 F:	Documentation/video4linux/README.pvrusb2
 F:	drivers/media/video/pvrusb2/
 
+PPWM core
+M:	Sascha Hauer <s.hauer at pengutronix.de>
+L:	linux-kernel at vger.kernel.org
+S:	Maintained
+F:	drivers/pwm/
+
 PXA2xx/PXA3xx SUPPORT
 M:	Eric Miao <eric.y.miao at gmail.com>
 M:	Russell King <linux at arm.linux.org.uk>
diff --git a/drivers/Kconfig b/drivers/Kconfig
index b3ae9e5..ec094b5 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -142,4 +142,6 @@ source "drivers/devfreq/Kconfig"
 
 source "drivers/modem_shm/Kconfig"
 
+source "drivers/pwm/Kconfig"
+
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 4855a1a..52fe956 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -8,6 +8,7 @@
 # GPIO must come after pinctrl as gpios may need to mux pins etc
 obj-y				+= pinctrl/
 obj-y				+= gpio/
+obj-y				+= pwm/
 obj-$(CONFIG_PCI)		+= pci/
 obj-$(CONFIG_PARISC)		+= parisc/
 obj-$(CONFIG_RAPIDIO)		+= rapidio/
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
new file mode 100644
index 0000000..93c1052
--- /dev/null
+++ b/drivers/pwm/Kconfig
@@ -0,0 +1,12 @@
+menuconfig PWM
+	bool "PWM Support"
+	help
+	  This enables PWM support through the generic PWM framework.
+	  You only need to enable this, if you also want to enable
+	  one or more of the PWM drivers below.
+
+	  If unsure, say N.
+
+if PWM
+
+endif
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
new file mode 100644
index 0000000..3469c3d
--- /dev/null
+++ b/drivers/pwm/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PWM)		+= core.o
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
new file mode 100644
index 0000000..71de479
--- /dev/null
+++ b/drivers/pwm/core.c
@@ -0,0 +1,220 @@
+/*
+ * Generic pwmlib implementation
+ *
+ * Copyright (C) 2011 Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/module.h>
+#include <linux/pwm.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+
+struct pwm_device {
+	struct			pwm_chip *chip;
+	const char		*label;
+	unsigned long		flags;
+#define FLAG_REQUESTED	0
+#define FLAG_ENABLED	1
+	struct list_head	node;
+};
+
+static LIST_HEAD(pwm_list);
+
+static DEFINE_MUTEX(pwm_lock);
+
+static struct pwm_device *_find_pwm(int pwm_id)
+{
+	struct pwm_device *pwm;
+
+	list_for_each_entry(pwm, &pwm_list, node) {
+		if (pwm->chip->pwm_id == pwm_id)
+			return pwm;
+	}
+
+	return NULL;
+}
+
+/**
+ * pwmchip_add() - register a new pwm
+ * @chip: the pwm
+ *
+ * register a new pwm. pwm->pwm_id must be initialized. if pwm_id < 0 then
+ * a dynamically assigned id will be used, otherwise the id specified,
+ */
+int pwmchip_add(struct pwm_chip *chip)
+{
+	struct pwm_device *pwm;
+	int ret = 0;
+
+	pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
+	if (!pwm)
+		return -ENOMEM;
+
+	pwm->chip = chip;
+
+	mutex_lock(&pwm_lock);
+
+	if (chip->pwm_id >= 0 && _find_pwm(chip->pwm_id)) {
+		ret = -EBUSY;
+		goto out;
+	}
+
+	list_add_tail(&pwm->node, &pwm_list);
+out:
+	mutex_unlock(&pwm_lock);
+
+	if (ret)
+		kfree(pwm);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(pwmchip_add);
+
+/**
+ * pwmchip_remove() - remove a pwm
+ * @chip: the pwm
+ *
+ * remove a pwm. This function may return busy if the pwm is still requested.
+ */
+int pwmchip_remove(struct pwm_chip *chip)
+{
+	struct pwm_device *pwm;
+	int ret = 0;
+
+	mutex_lock(&pwm_lock);
+
+	pwm = _find_pwm(chip->pwm_id);
+	if (!pwm) {
+		ret = -ENOENT;
+		goto out;
+	}
+
+	if (test_bit(FLAG_REQUESTED, &pwm->flags)) {
+		ret = -EBUSY;
+		goto out;
+	}
+
+	list_del(&pwm->node);
+
+	kfree(pwm);
+out:
+	mutex_unlock(&pwm_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(pwmchip_remove);
+
+/*
+ * pwm_request - request a PWM device
+ */
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+	struct pwm_device *pwm;
+	int ret;
+
+	mutex_lock(&pwm_lock);
+
+	pwm = _find_pwm(pwm_id);
+	if (!pwm) {
+		pwm = ERR_PTR(-ENOENT);
+		goto out;
+	}
+
+	if (test_bit(FLAG_REQUESTED, &pwm->flags)) {
+		pwm = ERR_PTR(-EBUSY);
+		goto out;
+	}
+
+	if (!try_module_get(pwm->chip->ops->owner)) {
+		pwm = ERR_PTR(-ENODEV);
+		goto out;
+	}
+
+	if (pwm->chip->ops->request) {
+		ret = pwm->chip->ops->request(pwm->chip);
+		if (ret) {
+			pwm = ERR_PTR(ret);
+			goto out_put;
+		}
+	}
+
+	pwm->label = label;
+	set_bit(FLAG_REQUESTED, &pwm->flags);
+
+	goto out;
+
+out_put:
+	module_put(pwm->chip->ops->owner);
+out:
+	mutex_unlock(&pwm_lock);
+
+	return pwm;
+}
+EXPORT_SYMBOL_GPL(pwm_request);
+
+/*
+ * pwm_free - free a PWM device
+ */
+void pwm_free(struct pwm_device *pwm)
+{
+	mutex_lock(&pwm_lock);
+
+	if (!test_and_clear_bit(FLAG_REQUESTED, &pwm->flags)) {
+		pr_warning("PWM device already freed\n");
+		goto out;
+	}
+
+	pwm->label = NULL;
+
+	module_put(pwm->chip->ops->owner);
+out:
+	mutex_unlock(&pwm_lock);
+}
+EXPORT_SYMBOL_GPL(pwm_free);
+
+/*
+ * pwm_config - change a PWM device configuration
+ */
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+	return pwm->chip->ops->config(pwm->chip, duty_ns, period_ns);
+}
+EXPORT_SYMBOL_GPL(pwm_config);
+
+/*
+ * pwm_enable - start a PWM output toggling
+ */
+int pwm_enable(struct pwm_device *pwm)
+{
+	if (!test_and_set_bit(FLAG_ENABLED, &pwm->flags))
+		return pwm->chip->ops->enable(pwm->chip);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pwm_enable);
+
+/*
+ * pwm_disable - stop a PWM output toggling
+ */
+void pwm_disable(struct pwm_device *pwm)
+{
+	if (test_and_clear_bit(FLAG_ENABLED, &pwm->flags))
+		pwm->chip->ops->disable(pwm->chip);
+}
+EXPORT_SYMBOL_GPL(pwm_disable);
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index 7c77575..df9681b 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -28,4 +28,41 @@ int pwm_enable(struct pwm_device *pwm);
  */
 void pwm_disable(struct pwm_device *pwm);
 
+#ifdef CONFIG_PWM
+struct pwm_chip;
+
+/**
+ * struct pwm_ops - PWM operations
+ * @request: optional hook for requesting a PWM
+ * @free: optional hook for freeing a PWM
+ * @config: configure duty cycles and period length for this PWM
+ * @enable: enable PWM output toggling
+ * @disable: disable PWM output toggling
+ */
+struct pwm_ops {
+	int			(*request)(struct pwm_chip *chip);
+	void			(*free)(struct pwm_chip *chip);
+	int			(*config)(struct pwm_chip *chip, int duty_ns,
+						int period_ns);
+	int			(*enable)(struct pwm_chip *chip);
+	void			(*disable)(struct pwm_chip *chip);
+	struct module		*owner;
+};
+
+/**
+ * struct pwm_chip - abstract a PWM
+ * @label: for diagnostics
+ * @owner: helps prevent removal of modules exporting active PWMs
+ * @ops: The callbacks for this PWM
+ */
+struct pwm_chip {
+	int			pwm_id;
+	const char		*label;
+	struct pwm_ops		*ops;
+};
+
+int pwmchip_add(struct pwm_chip *chip);
+int pwmchip_remove(struct pwm_chip *chip);
+#endif
+
 #endif /* __LINUX_PWM_H */
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 14 11:56:33 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 16:56:33 +0100
Subject: [PATCH v4 10/10] pwm-backlight: Add rudimentary device tree support
In-Reply-To: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331740593-10807-11-git-send-email-thierry.reding@avionic-design.de>

This commit adds very basic support for device tree probing. Currently,
only a PWM and a list of distinct brightness levels can be specified.
Enabling or disabling backlight power via GPIOs is not yet supported.

A pointer to the exit() callback is stored in the driver data to keep it
around until the driver is unloaded.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v4:
  - store a PWM requested with of_pwm_request() in the platform data

Changes in v3:
  - use a list of distinct brightness levels instead of a linear range
    as discussed with Stephen Warren and Mitch Bradley

Changes in v2:
  - avoid oops by keeping a reference to the platform-specific exit()
    callback

TODO:
  - add fixed-regulator support for backlight enable/disable

 .../bindings/video/backlight/pwm-backlight         |   19 +++
 drivers/video/backlight/Kconfig                    |    2 +-
 drivers/video/backlight/pwm_bl.c                   |  136 +++++++++++++++++---
 include/linux/pwm_backlight.h                      |    2 +
 4 files changed, 141 insertions(+), 18 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/video/backlight/pwm-backlight

diff --git a/Documentation/devicetree/bindings/video/backlight/pwm-backlight b/Documentation/devicetree/bindings/video/backlight/pwm-backlight
new file mode 100644
index 0000000..79db3dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/backlight/pwm-backlight
@@ -0,0 +1,19 @@
+pwm-backlight bindings
+
+Required properties:
+  - compatible: "pwm-backlight"
+  - pwm: OF device-tree PWM specification
+  - num-brightness-levels: number of distinct brightness levels
+  - brightness-levels: array of distinct brightness levels
+  - default-brightness-level: the default brightness level
+
+Example:
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwm = <&pwm 0 5000000>;
+
+		num-brightness-levels = <8>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+	};
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index 7ed9991..ecfe3a0 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -233,7 +233,7 @@ config BACKLIGHT_CARILLO_RANCH
 
 config BACKLIGHT_PWM
 	tristate "Generic PWM based Backlight Driver"
-	depends on HAVE_PWM
+	depends on HAVE_PWM || PWM
 	help
 	  If you have a LCD backlight adjustable by PWM, say Y to enable
 	  this driver.
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
index 342b7d7..57ff91b 100644
--- a/drivers/video/backlight/pwm_bl.c
+++ b/drivers/video/backlight/pwm_bl.c
@@ -17,6 +17,7 @@
 #include <linux/fb.h>
 #include <linux/backlight.h>
 #include <linux/err.h>
+#include <linux/of_pwm.h>
 #include <linux/pwm.h>
 #include <linux/pwm_backlight.h>
 #include <linux/slab.h>
@@ -26,11 +27,13 @@ struct pwm_bl_data {
 	struct device		*dev;
 	unsigned int		period;
 	unsigned int		lth_brightness;
+	unsigned int		*levels;
 	int			(*notify)(struct device *,
 					  int brightness);
 	void			(*notify_after)(struct device *,
 					int brightness);
 	int			(*check_fb)(struct device *, struct fb_info *);
+	void			(*exit)(struct device *);
 };
 
 static int pwm_backlight_update_status(struct backlight_device *bl)
@@ -52,6 +55,11 @@ static int pwm_backlight_update_status(struct backlight_device *bl)
 		pwm_config(pb->pwm, 0, pb->period);
 		pwm_disable(pb->pwm);
 	} else {
+		if (pb->levels) {
+			brightness = pb->levels[brightness];
+			max = pb->levels[max];
+		}
+
 		brightness = pb->lth_brightness +
 			(brightness * (pb->period - pb->lth_brightness) / max);
 		pwm_config(pb->pwm, brightness, pb->period);
@@ -83,17 +91,102 @@ static const struct backlight_ops pwm_backlight_ops = {
 	.check_fb	= pwm_backlight_check_fb,
 };
 
+#ifdef CONFIG_OF
+static int pwm_backlight_parse_dt(struct device *dev,
+				  struct platform_pwm_backlight_data *data)
+{
+	struct device_node *node = dev->of_node;
+	struct pwm_device *pwm;
+	u32 value;
+	int ret;
+
+	if (!node)
+		return -ENODEV;
+
+	pwm = of_pwm_request(node, "pwm", 0);
+	if (IS_ERR(pwm))
+		return PTR_ERR(pwm);
+
+	memset(data, 0, sizeof(*data));
+	data->pwm_period_ns = pwm_get_period(pwm);
+	data->pwm = pwm;
+
+	ret = of_property_read_u32(node, "num-brightness-levels", &value);
+	if (ret < 0)
+		goto free;
+
+	data->max_brightness = value;
+
+	if (data->max_brightness > 0) {
+		size_t size = sizeof(*data->levels) * data->max_brightness;
+
+		data->levels = devm_kzalloc(dev, size, GFP_KERNEL);
+		if (!data->levels) {
+			ret = -ENOMEM;
+			goto free;
+		}
+
+		ret = of_property_read_u32_array(node, "brightness-levels",
+						 data->levels,
+						 data->max_brightness);
+		if (ret < 0)
+			goto free;
+
+		ret = of_property_read_u32(node, "default-brightness-level",
+					   &value);
+		if (ret < 0)
+			goto free;
+
+		data->dft_brightness = value;
+		data->max_brightness--;
+	}
+
+	/*
+	 * TODO: Most users of this driver use a number of GPIOs to control
+	 *       backlight power. Support for specifying these needs to be
+	 *       added.
+	 */
+
+	return 0;
+
+free:
+	pwm_free(pwm);
+
+	return ret;
+}
+
+static struct of_device_id pwm_backlight_of_match[] = {
+	{ .compatible = "pwm-backlight" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, pwm_backlight_of_match);
+#else
+static int pwm_backlight_parse_dt(struct device *dev,
+				  struct platform_pwm_backlight_data *data)
+{
+	return -ENODEV;
+}
+#endif
+
 static int pwm_backlight_probe(struct platform_device *pdev)
 {
 	struct backlight_properties props;
 	struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
+	struct platform_pwm_backlight_data defdata;
 	struct backlight_device *bl;
 	struct pwm_bl_data *pb;
+	unsigned int max;
 	int ret;
 
 	if (!data) {
-		dev_err(&pdev->dev, "failed to find platform data\n");
-		return -EINVAL;
+		ret = pwm_backlight_parse_dt(&pdev->dev, &defdata);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "failed to find platform data\n");
+			return ret;
+		}
+
+		data = &defdata;
 	}
 
 	if (data->init) {
@@ -109,21 +202,30 @@ static int pwm_backlight_probe(struct platform_device *pdev)
 		goto err_alloc;
 	}
 
+	if (data->levels) {
+		max = data->levels[data->max_brightness];
+		pb->levels = data->levels;
+	} else
+		max = data->max_brightness;
+
 	pb->period = data->pwm_period_ns;
 	pb->notify = data->notify;
 	pb->notify_after = data->notify_after;
 	pb->check_fb = data->check_fb;
-	pb->lth_brightness = data->lth_brightness *
-		(data->pwm_period_ns / data->max_brightness);
+	pb->exit = data->exit;
+	pb->lth_brightness = data->lth_brightness * (data->pwm_period_ns / max);
+	pb->pwm = data->pwm;
 	pb->dev = &pdev->dev;
 
-	pb->pwm = pwm_request(data->pwm_id, "backlight");
-	if (IS_ERR(pb->pwm)) {
-		dev_err(&pdev->dev, "unable to request PWM for backlight\n");
-		ret = PTR_ERR(pb->pwm);
-		goto err_alloc;
-	} else
-		dev_dbg(&pdev->dev, "got pwm for backlight\n");
+	if (!pb->pwm) {
+		pb->pwm = pwm_request(data->pwm_id, "backlight");
+		if (IS_ERR(pb->pwm)) {
+			dev_err(&pdev->dev, "unable to request PWM for backlight\n");
+			ret = PTR_ERR(pb->pwm);
+			goto err_alloc;
+		} else
+			dev_dbg(&pdev->dev, "got pwm for backlight\n");
+	}
 
 	memset(&props, 0, sizeof(struct backlight_properties));
 	props.type = BACKLIGHT_RAW;
@@ -152,7 +254,6 @@ err_alloc:
 
 static int pwm_backlight_remove(struct platform_device *pdev)
 {
-	struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
 	struct backlight_device *bl = platform_get_drvdata(pdev);
 	struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
 
@@ -160,8 +261,8 @@ static int pwm_backlight_remove(struct platform_device *pdev)
 	pwm_config(pb->pwm, 0, pb->period);
 	pwm_disable(pb->pwm);
 	pwm_free(pb->pwm);
-	if (data->exit)
-		data->exit(&pdev->dev);
+	if (pb->exit)
+		pb->exit(&pdev->dev);
 	return 0;
 }
 
@@ -195,11 +296,12 @@ static SIMPLE_DEV_PM_OPS(pwm_backlight_pm_ops, pwm_backlight_suspend,
 
 static struct platform_driver pwm_backlight_driver = {
 	.driver		= {
-		.name	= "pwm-backlight",
-		.owner	= THIS_MODULE,
+		.name		= "pwm-backlight",
+		.owner		= THIS_MODULE,
 #ifdef CONFIG_PM
-		.pm	= &pwm_backlight_pm_ops,
+		.pm		= &pwm_backlight_pm_ops,
 #endif
+		.of_match_table	= of_match_ptr(pwm_backlight_of_match),
 	},
 	.probe		= pwm_backlight_probe,
 	.remove		= pwm_backlight_remove,
diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h
index 63d2df4..3d1f0da 100644
--- a/include/linux/pwm_backlight.h
+++ b/include/linux/pwm_backlight.h
@@ -7,11 +7,13 @@
 #include <linux/backlight.h>
 
 struct platform_pwm_backlight_data {
+	struct pwm_device *pwm;
 	int pwm_id;
 	unsigned int max_brightness;
 	unsigned int dft_brightness;
 	unsigned int lth_brightness;
 	unsigned int pwm_period_ns;
+	unsigned int *levels;
 	int (*init)(struct device *dev);
 	int (*notify)(struct device *dev, int brightness);
 	void (*notify_after)(struct device *dev, int brightness);
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 14 11:56:27 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 16:56:27 +0100
Subject: [PATCH v4 04/10] ARM: tegra: Fix PWM clock programming
In-Reply-To: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331740593-10807-5-git-send-email-thierry.reding@avionic-design.de>

From: Simon Que <sque at chromium.org>

PWM clock source registers in Tegra 2 have different clock source selection bit
fields than other registers.  PWM clock source bits in CLK_SOURCE_PWM_0 register
are located at bit field bit[30:28] while others are at bit field bit[31:30] in
their respective clock source register.

This patch updates the clock programming to correctly reflect that, by adding a
flag to indicate the alternate bit field format and checking for it when
selecting a clock source (parent clock).

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
Signed-off-by: Bill Huang <bilhuang at nvidia.com>
Signed-off-by: Simon Que <sque at chromium.org>
---
Changes in v4:
  - reuse PWM flag from Tegra 30 clock programming
  - mask out bit 31 explicitly

 arch/arm/mach-tegra/tegra2_clocks.c |   32 ++++++++++++++++++++++++++++----
 1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 592a4ee..64735bd 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -69,6 +69,8 @@
 
 #define PERIPH_CLK_SOURCE_MASK		(3<<30)
 #define PERIPH_CLK_SOURCE_SHIFT		30
+#define PERIPH_CLK_SOURCE_PWM_MASK	(7<<28)
+#define PERIPH_CLK_SOURCE_PWM_SHIFT	28
 #define PERIPH_CLK_SOURCE_ENABLE	(1<<28)
 #define PERIPH_CLK_SOURCE_DIVU71_MASK	0xFF
 #define PERIPH_CLK_SOURCE_DIVU16_MASK	0xFFFF
@@ -908,9 +910,20 @@ static void tegra2_periph_clk_init(struct clk *c)
 	u32 val = clk_readl(c->reg);
 	const struct clk_mux_sel *mux = NULL;
 	const struct clk_mux_sel *sel;
+	u32 shift;
+	u32 mask;
+
+	if (c->flags & MUX_PWM) {
+		shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+		mask = PERIPH_CLK_SOURCE_PWM_MASK;
+	} else {
+		shift = PERIPH_CLK_SOURCE_SHIFT;
+		mask = PERIPH_CLK_SOURCE_MASK;
+	}
+
 	if (c->flags & MUX) {
 		for (sel = c->inputs; sel->input != NULL; sel++) {
-			if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
+			if ((val & mask) >> shift == sel->value)
 				mux = sel;
 		}
 		BUG_ON(!mux);
@@ -1023,12 +1036,23 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
 {
 	u32 val;
 	const struct clk_mux_sel *sel;
+	u32 mask, shift;
+
 	pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+
+	if (c->flags & MUX_PWM) {
+		shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+		mask = PERIPH_CLK_SOURCE_PWM_MASK;
+	} else {
+		shift = PERIPH_CLK_SOURCE_SHIFT;
+		mask = PERIPH_CLK_SOURCE_MASK;
+	}
+
 	for (sel = c->inputs; sel->input != NULL; sel++) {
 		if (sel->input == p) {
 			val = clk_readl(c->reg);
-			val &= ~PERIPH_CLK_SOURCE_MASK;
-			val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
+			val &= ~mask;
+			val |= (sel->value) << shift;
 
 			if (c->refcnt)
 				clk_enable(p);
@@ -2146,7 +2170,7 @@ static struct clk tegra_list_clks[] = {
 	PERIPH_CLK("i2s2",	"tegra-i2s.1",		NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("spdif_out",	"spdif_out",		NULL,	10,	0x108,	100000000, mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("spdif_in",	"spdif_in",		NULL,	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71),
-	PERIPH_CLK("pwm",	"pwm",			NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71),
+	PERIPH_CLK("pwm",	"pwm",			NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71 | MUX_PWM),
 	PERIPH_CLK("spi",	"spi",			NULL,	43,	0x114,	40000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("xio",	"xio",			NULL,	45,	0x120,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("twc",	"twc",			NULL,	16,	0x12c,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 14 11:56:26 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 16:56:26 +0100
Subject: [PATCH v4 03/10] pwm: Add device tree support
In-Reply-To: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331740593-10807-4-git-send-email-thierry.reding@avionic-design.de>

This patch adds helpers to support device tree bindings for the generic
PWM API. Device tree binding documentation for PWM controllers is also
provided.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v4:
  - add OF-specific code removed from patch 2
  - make of_node_to_pwmchip() and of_pwm_simple_xlate() static
  - rename of_get_named_pwm() to of_pwm_request(), return a struct
    pwm_device, get rid of the now unused spec parameter and use the
    device_node.name field as the PWM's name
  - return a requested struct pwm_device from pwm_chip.of_xlate and
    drop the now unused spec parameter
  - move OF support code into drivers/pwm/core.c
  - used deferred probing if a PWM chip is not available yet

Changes in v2:
  - add device tree binding documentation
  - add of_xlate to parse controller-specific PWM-specifier

 Documentation/devicetree/bindings/pwm/pwm.txt |   48 ++++++++++
 drivers/of/Kconfig                            |    6 ++
 drivers/pwm/core.c                            |  127 +++++++++++++++++++++++++
 include/linux/of_pwm.h                        |   36 +++++++
 include/linux/pwm.h                           |    8 ++
 5 files changed, 225 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/pwm.txt
 create mode 100644 include/linux/of_pwm.h

diff --git a/Documentation/devicetree/bindings/pwm/pwm.txt b/Documentation/devicetree/bindings/pwm/pwm.txt
new file mode 100644
index 0000000..9421fe7
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm.txt
@@ -0,0 +1,48 @@
+Specifying PWM information for devices
+======================================
+
+1) PWM user nodes
+-----------------
+
+PWM users should specify a list of PWM devices that they want to use
+with a property containing a 'pwm-list':
+
+	pwm-list ::= <single-pwm> [pwm-list]
+	single-pwm ::= <pwm-phandle> <pwm-specifier>
+	pwm-phandle : phandle to PWM controller node
+	pwm-specifier : array of #pwm-cells specifying the given PWM
+			(controller specific)
+
+PWM properties should be named "[<name>-]pwms". Exact meaning of each
+pwms property must be documented in the device tree binding for each
+device.
+
+The following example could be used to describe a PWM-based backlight
+device:
+
+	pwm: pwm {
+		#pwm-cells = <2>;
+	};
+
+	[...]
+
+	bl: backlight {
+		pwms = <&pwm 0 5000000>;
+	};
+
+pwm-specifier typically encodes the chip-relative PWM number and the PWM
+period in nanoseconds.
+
+2) PWM controller nodes
+-----------------------
+
+PWM controller nodes must specify the number of cells used for the
+specifier using the '#pwm-cells' property.
+
+An example PWM controller might look like this:
+
+	pwm: pwm at 7000a000 {
+		compatible = "nvidia,tegra20-pwm";
+		reg = <0x7000a000 0x100>;
+		#pwm-cells = <2>;
+	};
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index 6ea51dc..d47b8ee 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -57,6 +57,12 @@ config OF_GPIO
 	help
 	  OpenFirmware GPIO accessors
 
+config OF_PWM
+	def_bool y
+	depends on PWM
+	help
+	  OpenFirmware PWM accessors
+
 config OF_I2C
 	def_tristate I2C
 	depends on I2C && !SPARC
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 74dd295..c600606 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -20,6 +20,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/of_pwm.h>
 #include <linux/pwm.h>
 #include <linux/radix-tree.h>
 #include <linux/list.h>
@@ -121,6 +122,75 @@ static int pwm_device_request(struct pwm_device *pwm, const char *label)
 	return 0;
 }
 
+#ifdef CONFIG_OF_PWM
+static struct pwm_chip *of_node_to_pwmchip(struct device_node *np)
+{
+	struct pwm_chip *chip;
+
+	mutex_lock(&pwm_lock);
+
+	list_for_each_entry(chip, &pwm_chips, list)
+		if (chip->dev && chip->dev->of_node == np) {
+			mutex_unlock(&pwm_lock);
+			return chip;
+		}
+
+	mutex_unlock(&pwm_lock);
+
+	return ERR_PTR(-EPROBE_DEFER);
+}
+
+static struct pwm_device *of_pwm_simple_xlate(struct pwm_chip *pc,
+					      const struct of_phandle_args *args)
+{
+	struct pwm_device *pwm;
+
+	if (pc->of_pwm_n_cells < 2)
+		return ERR_PTR(-EINVAL);
+
+	if (args->args_count < pc->of_pwm_n_cells)
+		return ERR_PTR(-EINVAL);
+
+	if (args->args[0] >= pc->npwm)
+		return ERR_PTR(-EINVAL);
+
+	pwm = pwm_request_from_device(pc->dev, args->args[0], NULL);
+	if (IS_ERR(pwm))
+		return ERR_PTR(-ENODEV);
+
+	pwm_set_period(pwm, args->args[1]);
+
+	return pwm;
+}
+
+void of_pwmchip_add(struct pwm_chip *chip)
+{
+	if (!chip->dev || !chip->dev->of_node)
+		return;
+
+	if (!chip->of_xlate) {
+		chip->of_xlate = of_pwm_simple_xlate;
+		chip->of_pwm_n_cells = 2;
+	}
+
+	of_node_get(chip->dev->of_node);
+}
+
+void of_pwmchip_remove(struct pwm_chip *chip)
+{
+	if (chip->dev && chip->dev->of_node)
+		of_node_put(chip->dev->of_node);
+}
+#else
+static inline void of_pwmchip_add(struct pwm_chip *pc)
+{
+}
+
+static inline void of_pwmchip_remove(struct pwm_chip *pc)
+{
+}
+#endif /* CONFIG_OF_PWM */
+
 /**
  * pwm_set_chip_data - set private chip data for a PWM
  * @pwm: PWM device
@@ -184,6 +254,7 @@ int pwmchip_add(struct pwm_chip *chip)
 
 	INIT_LIST_HEAD(&chip->list);
 	list_add(&chip->list, &pwm_chips);
+	of_pwmchip_add(chip);
 
 out:
 	mutex_unlock(&pwm_lock);
@@ -215,6 +286,7 @@ int pwmchip_remove(struct pwm_chip *chip)
 	}
 
 	list_del_init(&chip->list);
+	of_pwmchip_remove(chip);
 	free_pwms(chip);
 
 out:
@@ -364,6 +436,61 @@ void pwm_disable(struct pwm_device *pwm)
 }
 EXPORT_SYMBOL_GPL(pwm_disable);
 
+#ifdef CONFIG_OF
+/**
+ * of_pwm_request() - request a PWM via the PWM framework
+ * @np: device node to get the PWM from
+ * @propname: property name containing PWM specifier(s)
+ * @index: index of the PWM
+ *
+ * Returns the PWM device parsed from the phandle specified in the given
+ * property of a device tree node or NULL on failure. Values parsed from
+ * the device tree are stored in the returned PWM device object.
+ */
+struct pwm_device *of_pwm_request(struct device_node *np,
+				  const char *propname, int index)
+{
+	struct pwm_device *pwm = NULL;
+	struct of_phandle_args args;
+	struct pwm_chip *pc;
+	int err;
+
+	err = of_parse_phandle_with_args(np, propname, "#pwm-cells", index,
+					 &args);
+	if (err) {
+		pr_debug("%s(): can't parse property \"%s\"\n", __func__,
+			 propname);
+		return ERR_PTR(err);
+	}
+
+	pc = of_node_to_pwmchip(args.np);
+	if (IS_ERR(pc)) {
+		pr_debug("%s(): PWM chip not found\n", __func__);
+		pwm = ERR_CAST(pc);
+		goto put;
+	}
+
+	if (args.args_count != pc->of_pwm_n_cells) {
+		pr_debug("%s: wrong #pwm-cells for %s\n", np->full_name,
+			 args.np->full_name);
+		pwm = ERR_PTR(-EINVAL);
+		goto put;
+	}
+
+	pwm = pc->of_xlate(pc, &args);
+	if (IS_ERR(pwm))
+		goto put;
+
+	pwm->label = np->name;
+
+put:
+	of_node_put(args.np);
+
+	return pwm;
+}
+EXPORT_SYMBOL(of_pwm_request);
+#endif
+
 #ifdef CONFIG_DEBUG_FS
 static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s)
 {
diff --git a/include/linux/of_pwm.h b/include/linux/of_pwm.h
new file mode 100644
index 0000000..a3a3da7
--- /dev/null
+++ b/include/linux/of_pwm.h
@@ -0,0 +1,36 @@
+/*
+ * OF helpers for the PWM API
+ *
+ * Copyright (c) 2011-2012 Avionic Design GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_OF_PWM_H
+#define __LINUX_OF_PWM_H
+
+#include <linux/err.h>
+#include <linux/pwm.h>
+
+struct device_node;
+
+#ifdef CONFIG_OF_PWM
+
+struct pwm_device *of_pwm_request(struct device_node *np,
+				  const char *propname, int index);
+
+#else
+
+static inline struct pwm_device *of_pwm_request(struct device_node *np,
+						const char *propname,
+						int index);
+{
+	return ERR_PTR(-ENOSYS);
+}
+
+#endif /* CONFIG_OF_PWM */
+
+#endif /* __LINUX_OF_PWM_H */
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index 7261911..7b42336 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -1,6 +1,8 @@
 #ifndef __LINUX_PWM_H
 #define __LINUX_PWM_H
 
+#include <linux/of.h>
+
 struct pwm_device;
 
 /*
@@ -102,6 +104,12 @@ struct pwm_chip {
 	unsigned int		npwm;
 
 	struct pwm_device	*pwms;
+
+#ifdef CONFIG_OF_PWM
+	struct pwm_device *	(*of_xlate)(struct pwm_chip *pc,
+					    const struct of_phandle_args *args);
+	unsigned int		of_pwm_n_cells;
+#endif
 };
 
 int pwm_set_chip_data(struct pwm_device *pwm, void *data);
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 14 11:56:25 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 16:56:25 +0100
Subject: [PATCH v4 02/10] pwm: Allow chips to support multiple PWMs.
In-Reply-To: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331740593-10807-3-git-send-email-thierry.reding@avionic-design.de>

Many PWM controllers provide access to more than a single PWM output and
may even share some resource among them. Allowing a PWM chip to provide
multiple PWM devices enables better sharing of those resources. As a
side-effect this change allows easy integration with the device tree
where a given PWM can be looked up based on the PWM chip's phandle and a
corresponding index.

This commit modifies the PWM core to support multiple PWMs per struct
pwm_chip. It achieves this in a similar way to how gpiolib works, by
allowing PWM ranges to be requested dynamically (pwm_chip.base == -1) or
starting at a given offset (pwm_chip.base >= 0). A chip specifies how
many PWMs it controls using the npwm member. Each of the functions in
the pwm_ops structure gets an additional argument that specified the PWM
number (it can be converted to a per-chip index by subtracting the
chip's base).

The total maximum number of PWM devices is currently fixed to 1024 while
the data is actually stored in a radix tree, thus saving resources if
not all of them are used.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v4:
  - remove OF-specific code to preserve bisectability
  - add pwm_request_from_device() and pwm_request_from_chip() functions
  - refactor PWM requesting code
  - store period in struct pwm_device and get rid of the unused struct
    pwm_spec

Changes in v3:
  - get rid of pwm_desc structure and keep only struct pwm_device
  - keep a list of pwm_chip structures for fast and easy lookup
  - pass struct pwm_device directly to pwm_ops
  - add debugfs file

Changes in v2:
  - add 'struct device *dev' field to pwm_chip, drop label field
  - use radix tree for PWM descriptors
  - add pwm_set_chip_data() and pwm_get_chip_data() functions to allow
    storing and retrieving chip-specific per-PWM data

 drivers/pwm/core.c  |  376 +++++++++++++++++++++++++++++++++++++++------------
 include/linux/pwm.h |   78 +++++++++--
 2 files changed, 358 insertions(+), 96 deletions(-)

diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 71de479..74dd295 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -2,6 +2,7 @@
  * Generic pwmlib implementation
  *
  * Copyright (C) 2011 Sascha Hauer <s.hauer at pengutronix.de>
+ * Copyright (C) 2011-2012 Avionic Design GmbH
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -17,105 +18,207 @@
  *  along with this program; see the file COPYING.  If not, write to
  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  */
+
 #include <linux/module.h>
 #include <linux/pwm.h>
+#include <linux/radix-tree.h>
 #include <linux/list.h>
 #include <linux/mutex.h>
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
 
-struct pwm_device {
-	struct			pwm_chip *chip;
-	const char		*label;
-	unsigned long		flags;
-#define FLAG_REQUESTED	0
-#define FLAG_ENABLED	1
-	struct list_head	node;
-};
-
-static LIST_HEAD(pwm_list);
+#define MAX_PWMS 1024
 
 static DEFINE_MUTEX(pwm_lock);
+static LIST_HEAD(pwm_chips);
+static DECLARE_BITMAP(allocated_pwms, MAX_PWMS);
+static RADIX_TREE(pwm_tree, GFP_KERNEL);
 
-static struct pwm_device *_find_pwm(int pwm_id)
+static struct pwm_device *pwm_to_device(unsigned int pwm)
 {
-	struct pwm_device *pwm;
+	return radix_tree_lookup(&pwm_tree, pwm);
+}
+
+static int alloc_pwms(int pwm, unsigned int count)
+{
+	unsigned int from = 0;
+	unsigned int start;
+
+	if (pwm >= MAX_PWMS)
+		return -EINVAL;
+
+	if (pwm >= 0)
+		from = pwm;
+
+	start = bitmap_find_next_zero_area(allocated_pwms, MAX_PWMS, from,
+					   count, 0);
+
+	if (pwm >= 0 && start != pwm)
+		return -EEXIST;
+
+	if (start + count > MAX_PWMS)
+		return -ENOSPC;
+
+	return start;
+}
+
+static void free_pwms(struct pwm_chip *chip)
+{
+	unsigned int i;
+
+	for (i = 0; i < chip->npwm; i++) {
+		struct pwm_device *pwm = &chip->pwms[i];
+		radix_tree_delete(&pwm_tree, pwm->pwm);
+	}
+
+	bitmap_clear(allocated_pwms, chip->base, chip->npwm);
+
+	kfree(chip->pwms);
+	chip->pwms = NULL;
+}
+
+static struct pwm_chip *device_to_pwmchip(struct device *dev)
+{
+	struct pwm_chip *chip;
+
+	mutex_lock(&pwm_lock);
+
+	list_for_each_entry(chip, &pwm_chips, list)
+		if (chip->dev == dev) {
+			mutex_unlock(&pwm_lock);
+			return chip;
+		}
+
+	mutex_unlock(&pwm_lock);
+
+	return ERR_PTR(-ENODEV);
+}
+
+static int pwm_device_request(struct pwm_device *pwm, const char *label)
+{
+	int err;
+
+	if (test_bit(PWMF_REQUESTED, &pwm->flags))
+		return -EBUSY;
+
+	if (!try_module_get(pwm->chip->ops->owner))
+		return -ENODEV;
 
-	list_for_each_entry(pwm, &pwm_list, node) {
-		if (pwm->chip->pwm_id == pwm_id)
-			return pwm;
+	if (pwm->chip->ops->request) {
+		err = pwm->chip->ops->request(pwm->chip, pwm);
+		if (err) {
+			module_put(pwm->chip->ops->owner);
+			return err;
+		}
 	}
 
-	return NULL;
+	set_bit(PWMF_REQUESTED, &pwm->flags);
+	pwm->label = label;
+
+	return 0;
+}
+
+/**
+ * pwm_set_chip_data - set private chip data for a PWM
+ * @pwm: PWM device
+ * @data: pointer to chip-specific data
+ */
+int pwm_set_chip_data(struct pwm_device *pwm, void *data)
+{
+	if (!pwm)
+		return -EINVAL;
+
+	pwm->chip_data = data;
+
+	return 0;
 }
 
 /**
- * pwmchip_add() - register a new pwm
- * @chip: the pwm
+ * pwm_get_chip_data - get private chip data for a PWM
+ * @pwm: PWM device
+ */
+void *pwm_get_chip_data(struct pwm_device *pwm)
+{
+	return pwm ? pwm->chip_data : NULL;
+}
+
+/**
+ * pwmchip_add() - register a new PWM chip
+ * @chip: the PWM chip to add
  *
- * register a new pwm. pwm->pwm_id must be initialized. if pwm_id < 0 then
- * a dynamically assigned id will be used, otherwise the id specified,
+ * Register a new PWM chip. If chip->base < 0 then a dynamically assigned base
+ * will be used.
  */
 int pwmchip_add(struct pwm_chip *chip)
 {
 	struct pwm_device *pwm;
-	int ret = 0;
+	unsigned int i;
+	int ret;
 
-	pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
-	if (!pwm)
+	mutex_lock(&pwm_lock);
+
+	ret = alloc_pwms(chip->base, chip->npwm);
+	if (ret < 0)
+		goto out;
+
+	chip->pwms = kzalloc(chip->npwm * sizeof(*pwm), GFP_KERNEL);
+	if (!chip->pwms)
 		return -ENOMEM;
 
-	pwm->chip = chip;
+	chip->base = ret;
 
-	mutex_lock(&pwm_lock);
+	for (i = 0; i < chip->npwm; i++) {
+		pwm = &chip->pwms[i];
 
-	if (chip->pwm_id >= 0 && _find_pwm(chip->pwm_id)) {
-		ret = -EBUSY;
-		goto out;
+		pwm->chip = chip;
+		pwm->pwm = chip->base + i;
+		pwm->hwpwm = i;
+
+		radix_tree_insert(&pwm_tree, pwm->pwm, pwm);
 	}
 
-	list_add_tail(&pwm->node, &pwm_list);
-out:
-	mutex_unlock(&pwm_lock);
+	bitmap_set(allocated_pwms, chip->base, chip->npwm);
 
-	if (ret)
-		kfree(pwm);
+	INIT_LIST_HEAD(&chip->list);
+	list_add(&chip->list, &pwm_chips);
 
+out:
+	mutex_unlock(&pwm_lock);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(pwmchip_add);
 
 /**
- * pwmchip_remove() - remove a pwm
- * @chip: the pwm
+ * pwmchip_remove() - remove a PWM chip
+ * @chip: the PWM chip to remove
  *
- * remove a pwm. This function may return busy if the pwm is still requested.
+ * Removes a PWM chip. This function may return busy if the PWM chip provides
+ * a PWM device that is still requested.
  */
 int pwmchip_remove(struct pwm_chip *chip)
 {
-	struct pwm_device *pwm;
+	unsigned int i;
 	int ret = 0;
 
 	mutex_lock(&pwm_lock);
 
-	pwm = _find_pwm(chip->pwm_id);
-	if (!pwm) {
-		ret = -ENOENT;
-		goto out;
-	}
+	for (i = 0; i < chip->npwm; i++) {
+		struct pwm_device *pwm = &chip->pwms[i];
 
-	if (test_bit(FLAG_REQUESTED, &pwm->flags)) {
-		ret = -EBUSY;
-		goto out;
+		if (test_bit(PWMF_REQUESTED, &pwm->flags)) {
+			ret = -EBUSY;
+			goto out;
+		}
 	}
 
-	list_del(&pwm->node);
+	list_del_init(&chip->list);
+	free_pwms(chip);
 
-	kfree(pwm);
 out:
 	mutex_unlock(&pwm_lock);
-
 	return ret;
 }
 EXPORT_SYMBOL_GPL(pwmchip_remove);
@@ -123,50 +226,89 @@ EXPORT_SYMBOL_GPL(pwmchip_remove);
 /*
  * pwm_request - request a PWM device
  */
-struct pwm_device *pwm_request(int pwm_id, const char *label)
+struct pwm_device *pwm_request(int pwm, const char *label)
 {
-	struct pwm_device *pwm;
-	int ret;
+	struct pwm_device *dev;
+	int err;
+
+	if (pwm < 0 || pwm >= MAX_PWMS)
+		return ERR_PTR(-EINVAL);
 
 	mutex_lock(&pwm_lock);
 
-	pwm = _find_pwm(pwm_id);
-	if (!pwm) {
-		pwm = ERR_PTR(-ENOENT);
+	dev = pwm_to_device(pwm);
+	if (!dev) {
+		dev = ERR_PTR(-ENODEV);
 		goto out;
 	}
 
-	if (test_bit(FLAG_REQUESTED, &pwm->flags)) {
-		pwm = ERR_PTR(-EBUSY);
-		goto out;
-	}
+	err = pwm_device_request(dev, label);
+	if (err < 0)
+		dev = ERR_PTR(err);
 
-	if (!try_module_get(pwm->chip->ops->owner)) {
-		pwm = ERR_PTR(-ENODEV);
-		goto out;
-	}
+out:
+	mutex_unlock(&pwm_lock);
 
-	if (pwm->chip->ops->request) {
-		ret = pwm->chip->ops->request(pwm->chip);
-		if (ret) {
-			pwm = ERR_PTR(ret);
-			goto out_put;
-		}
-	}
+	return dev;
+}
+EXPORT_SYMBOL_GPL(pwm_request);
 
-	pwm->label = label;
-	set_bit(FLAG_REQUESTED, &pwm->flags);
+/**
+ * pwm_request_from_device() - request a PWM device relative to a device
+ * @dev: device representing a PWM chip
+ * @index: per-chip index of the PWM to request
+ * @label: a literal description string of this PWM
+ *
+ * Returns the PWM at the given index of the PWM chip represented by the
+ * given device. A negative error code is returned if the device does not
+ * represent a PWM chip, the index is not valid for the specified PWM chip
+ * or if the PWM device cannot be requested.
+ */
+struct pwm_device *pwm_request_from_device(struct device *dev,
+					   unsigned int index,
+					   const char *label)
+{
+	struct pwm_chip *chip;
 
-	goto out;
+	chip = device_to_pwmchip(dev);
+	if (IS_ERR(chip))
+		return ERR_CAST(chip);
 
-out_put:
-	module_put(pwm->chip->ops->owner);
-out:
-	mutex_unlock(&pwm_lock);
+	return pwm_request_from_chip(chip, index, label);
+}
+EXPORT_SYMBOL_GPL(pwm_request_from_device);
+
+/**
+ * pwm_request_from_chip() - request a PWM device relative to a PWM chip
+ * @chip: PWM chip
+ * @index: per-chip index of the PWM to request
+ * @label: a literal description string of this PWM
+ *
+ * Returns the PWM at the given index of the given PWM chip. A negative error
+ * code is returned if the index is not valid for the specified PWM chip or
+ * if the PWM device cannot be requested.
+ */
+struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip,
+					 unsigned int index,
+					 const char *label)
+{
+	struct pwm_device *pwm;
+	int err;
+
+	if (index >= chip->npwm)
+		return ERR_PTR(-EINVAL);
+
+	mutex_lock(&pwm_lock);
+	pwm = &chip->pwms[index];
+
+	err = pwm_device_request(pwm, label);
+	if (err < 0)
+		pwm = ERR_PTR(err);
 
+	mutex_unlock(&pwm_lock);
 	return pwm;
 }
-EXPORT_SYMBOL_GPL(pwm_request);
+EXPORT_SYMBOL_GPL(pwm_request_from_chip);
 
 /*
  * pwm_free - free a PWM device
@@ -175,11 +317,14 @@ void pwm_free(struct pwm_device *pwm)
 {
 	mutex_lock(&pwm_lock);
 
-	if (!test_and_clear_bit(FLAG_REQUESTED, &pwm->flags)) {
+	if (!test_and_clear_bit(PWMF_REQUESTED, &pwm->flags)) {
 		pr_warning("PWM device already freed\n");
 		goto out;
 	}
 
+	if (pwm->chip->ops->free)
+		pwm->chip->ops->free(pwm->chip, pwm);
+
 	pwm->label = NULL;
 
 	module_put(pwm->chip->ops->owner);
@@ -193,7 +338,7 @@ EXPORT_SYMBOL_GPL(pwm_free);
  */
 int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 {
-	return pwm->chip->ops->config(pwm->chip, duty_ns, period_ns);
+	return pwm->chip->ops->config(pwm->chip, pwm, duty_ns, period_ns);
 }
 EXPORT_SYMBOL_GPL(pwm_config);
 
@@ -202,8 +347,8 @@ EXPORT_SYMBOL_GPL(pwm_config);
  */
 int pwm_enable(struct pwm_device *pwm)
 {
-	if (!test_and_set_bit(FLAG_ENABLED, &pwm->flags))
-		return pwm->chip->ops->enable(pwm->chip);
+	if (!test_and_set_bit(PWMF_ENABLED, &pwm->flags))
+		return pwm->chip->ops->enable(pwm->chip, pwm);
 
 	return 0;
 }
@@ -214,7 +359,72 @@ EXPORT_SYMBOL_GPL(pwm_enable);
  */
 void pwm_disable(struct pwm_device *pwm)
 {
-	if (test_and_clear_bit(FLAG_ENABLED, &pwm->flags))
-		pwm->chip->ops->disable(pwm->chip);
+	if (test_and_clear_bit(PWMF_ENABLED, &pwm->flags))
+		pwm->chip->ops->disable(pwm->chip, pwm);
 }
 EXPORT_SYMBOL_GPL(pwm_disable);
+
+#ifdef CONFIG_DEBUG_FS
+static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s)
+{
+	unsigned int i;
+
+	for (i = 0; i < chip->npwm; i++) {
+		struct pwm_device *pwm = &chip->pwms[i];
+
+		seq_printf(s, " pwm-%-3d (%-20.20s):", i, pwm->label);
+
+		if (test_bit(PWMF_REQUESTED, &pwm->flags))
+			seq_printf(s, " requested");
+
+		if (test_bit(PWMF_ENABLED, &pwm->flags))
+			seq_printf(s, " enabled");
+
+		seq_printf(s, "\n");
+	}
+}
+
+static int pwm_show(struct seq_file *s, void *unused)
+{
+	const char *prefix = "";
+	struct pwm_chip *chip;
+
+	list_for_each_entry(chip, &pwm_chips, list) {
+		struct device *dev = chip->dev;
+
+		seq_printf(s, "%s%s/%s, %d PWM devices\n", prefix,
+			   dev->bus ? dev->bus->name : "no-bus",
+			   dev_name(dev), chip->npwm);
+
+		if (chip->ops->dbg_show)
+			chip->ops->dbg_show(chip, s);
+		else
+			pwm_dbg_show(chip, s);
+
+		prefix = "\n";
+	}
+
+	return 0;
+}
+
+static int pwm_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pwm_show, NULL);
+}
+
+static const struct file_operations pwm_ops = {
+	.open = pwm_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static int __init pwm_debugfs_init(void)
+{
+	debugfs_create_file("pwm", S_IFREG | S_IRUGO, NULL, NULL, &pwm_ops);
+
+	return 0;
+}
+
+subsys_initcall(pwm_debugfs_init);
+#endif /* CONFIG_DEBUG_FS */
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index df9681b..7261911 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -31,38 +31,90 @@ void pwm_disable(struct pwm_device *pwm);
 #ifdef CONFIG_PWM
 struct pwm_chip;
 
+enum {
+	PWMF_REQUESTED = 1 << 0,
+	PWMF_ENABLED = 1 << 1,
+};
+
+struct pwm_device {
+	const char		*label;
+	unsigned long		flags;
+	unsigned int		hwpwm;
+	unsigned int		pwm;
+	struct pwm_chip		*chip;
+	void			*chip_data;
+
+	unsigned int		period; /* in nanoseconds */
+};
+
+static inline void pwm_set_period(struct pwm_device *pwm, unsigned int period)
+{
+	if (pwm)
+		pwm->period = period;
+}
+
+static inline unsigned int pwm_get_period(struct pwm_device *pwm)
+{
+	return pwm ? pwm->period : 0;
+}
+
 /**
- * struct pwm_ops - PWM operations
+ * struct pwm_ops - PWM controller operations
  * @request: optional hook for requesting a PWM
  * @free: optional hook for freeing a PWM
  * @config: configure duty cycles and period length for this PWM
  * @enable: enable PWM output toggling
  * @disable: disable PWM output toggling
+ * @dbg_show: optional routine to show contents in debugfs
+ * @owner: helps prevent removal of modules exporting active PWMs
  */
 struct pwm_ops {
-	int			(*request)(struct pwm_chip *chip);
-	void			(*free)(struct pwm_chip *chip);
-	int			(*config)(struct pwm_chip *chip, int duty_ns,
-						int period_ns);
-	int			(*enable)(struct pwm_chip *chip);
-	void			(*disable)(struct pwm_chip *chip);
+	int			(*request)(struct pwm_chip *chip,
+					   struct pwm_device *pwm);
+	void			(*free)(struct pwm_chip *chip,
+					struct pwm_device *pwm);
+	int			(*config)(struct pwm_chip *chip,
+					  struct pwm_device *pwm,
+					  int duty_ns, int period_ns);
+	int			(*enable)(struct pwm_chip *chip,
+					  struct pwm_device *pwm);
+	void			(*disable)(struct pwm_chip *chip,
+					   struct pwm_device *pwm);
+#ifdef CONFIG_DEBUG_FS
+	void			(*dbg_show)(struct pwm_chip *chip,
+					    struct seq_file *s);
+#endif
 	struct module		*owner;
 };
 
 /**
- * struct pwm_chip - abstract a PWM
- * @label: for diagnostics
- * @owner: helps prevent removal of modules exporting active PWMs
- * @ops: The callbacks for this PWM
+ * struct pwm_chip - abstract a PWM controller
+ * @dev: device providing the PWMs
+ * @ops: callbacks for this PWM controller
+ * @base: number of first PWM controlled by this chip
+ * @npwm: number of PWMs controlled by this chip
  */
 struct pwm_chip {
-	int			pwm_id;
-	const char		*label;
+	struct device		*dev;
+	struct list_head	list;
 	struct pwm_ops		*ops;
+	int			base;
+	unsigned int		npwm;
+
+	struct pwm_device	*pwms;
 };
 
+int pwm_set_chip_data(struct pwm_device *pwm, void *data);
+void *pwm_get_chip_data(struct pwm_device *pwm);
+
 int pwmchip_add(struct pwm_chip *chip);
 int pwmchip_remove(struct pwm_chip *chip);
+struct pwm_device *pwm_request_from_device(struct device *dev,
+					   unsigned int index,
+					   const char *label);
+struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip,
+					 unsigned int index,
+					 const char *label);
 #endif
 
 #endif /* __LINUX_PWM_H */
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 14 11:56:29 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 16:56:29 +0100
Subject: [PATCH v4 06/10] pwm: Add NVIDIA Tegra SoC support
In-Reply-To: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331740593-10807-7-git-send-email-thierry.reding@avionic-design.de>

This commit adds a generic PWM framework driver for the PWFM controller
found on NVIDIA Tegra SoCs. The driver is based on code from the
Chromium kernel tree and was originally written by Gary King (NVIDIA)
and later modified by Simon Que (Chromium).

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v4:
  - merge patch from ChromiumOS kernel to fix a rounding issue
  - move DT code to patch 7

Changes in v3:
  - use pwm_device.hwpwm instead of recomputing it
  - update pwm_ops for changes in patch 2

Changes in v2:
  - set pwm_chip.dev field
  - rename clk_enb to enable
  - introduce NUM_PWM macro instead of hard-coding the number of PWM
    devices
  - update comment in tegra_pwm_config
  - fix coding-style for multi-line comments
  - use module_platform_driver
  - change license to GPL

 drivers/pwm/Kconfig     |   10 ++
 drivers/pwm/Makefile    |    1 +
 drivers/pwm/pwm-tegra.c |  256 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 267 insertions(+)
 create mode 100644 drivers/pwm/pwm-tegra.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 93c1052..bda6f23 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -9,4 +9,14 @@ menuconfig PWM
 
 if PWM
 
+config PWM_TEGRA
+	tristate "NVIDIA Tegra PWM support"
+	depends on ARCH_TEGRA
+	help
+	  Generic PWM framework driver for the PWFM controller found on NVIDIA
+	  Tegra SoCs.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-tegra.
+
 endif
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 3469c3d..12300f5 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_PWM)		+= core.o
+obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
new file mode 100644
index 0000000..19540fc
--- /dev/null
+++ b/drivers/pwm/pwm-tegra.c
@@ -0,0 +1,256 @@
+/*
+ * drivers/pwm/pwm-tegra.c
+ *
+ * Tegra pulse-width-modulation controller driver
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pwm.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#define PWM_ENABLE	(1 << 31)
+#define PWM_DUTY_WIDTH	8
+#define PWM_DUTY_SHIFT	16
+#define PWM_SCALE_WIDTH	13
+#define PWM_SCALE_SHIFT	0
+
+#define NUM_PWM 4
+
+struct tegra_pwm_chip {
+	struct pwm_chip		chip;
+	struct device		*dev;
+
+	struct clk		*clk;
+
+	int			enable[NUM_PWM];
+	void __iomem		*mmio_base;
+};
+
+static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
+{
+	return container_of(chip, struct tegra_pwm_chip, chip);
+}
+
+static inline int pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
+		unsigned long val)
+{
+	unsigned long offset = num << 4;
+	int rc;
+
+	rc = clk_enable(chip->clk);
+	if (WARN_ON(rc))
+		return rc;
+
+	writel(val, chip->mmio_base + offset);
+	clk_disable(chip->clk);
+
+	return 0;
+}
+
+static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+		int duty_ns, int period_ns)
+{
+	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
+	unsigned long long c;
+	unsigned long rate, hz;
+	u32 val = 0;
+
+	/*
+	 * Convert from duty_ns / period_ns to a fixed number of duty ticks
+	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
+	 * nearest integer during division.
+	 */
+	c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
+	do_div(c, period_ns);
+
+	val = (u32)c << PWM_DUTY_SHIFT;
+
+	/*
+	 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
+	 * cycles at the PWM clock rate will take period_ns nanoseconds.
+	 */
+	rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
+	hz = 1000000000ul / period_ns;
+
+	rate = (rate + (hz / 2)) / hz;
+
+	/*
+	 * Since the actual PWM divider is the register's frequency divider
+	 * field minus 1, we need to decrement to get the correct value to
+	 * write to the register.
+	 */
+	if (rate > 0)
+		rate--;
+
+	/*
+	 * Make sure that the rate will fit in the register's frequency
+	 * divider field.
+	 */
+	if (rate >> PWM_SCALE_WIDTH)
+		return -EINVAL;
+
+	val |= (rate << PWM_SCALE_SHIFT);
+
+	/* If the PWM channel is enabled, keep it enabled */
+	if (pc->enable[pwm->hwpwm])
+		val |= PWM_ENABLE;
+
+	return pwm_writel(pc, pwm->hwpwm, val);
+}
+
+static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
+	int rc = 0;
+
+	if (!pc->enable[pwm->hwpwm]) {
+		rc = clk_enable(pc->clk);
+		if (!rc) {
+			unsigned long offset = pwm->hwpwm << 4;
+			u32 val;
+
+			val = readl(pc->mmio_base + offset);
+			val |= PWM_ENABLE;
+			writel(val, pc->mmio_base + offset);
+
+			pc->enable[pwm->hwpwm] = 1;
+		}
+	}
+
+	return 0;
+}
+
+static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
+
+	if (pc->enable[pwm->hwpwm]) {
+		unsigned long offset = pwm->hwpwm << 4;
+		u32 val;
+
+		val = readl(pc->mmio_base + offset);
+		val &= ~PWM_ENABLE;
+		writel(val, pc->mmio_base + offset);
+
+		clk_disable(pc->clk);
+		pc->enable[pwm->hwpwm] = 0;
+	}
+}
+
+static struct pwm_ops tegra_pwm_ops = {
+	.config = tegra_pwm_config,
+	.enable = tegra_pwm_enable,
+	.disable = tegra_pwm_disable,
+	.owner = THIS_MODULE,
+};
+
+static int tegra_pwm_probe(struct platform_device *pdev)
+{
+	struct tegra_pwm_chip *pwm;
+	struct resource *r;
+	int ret;
+
+	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
+	if (!pwm) {
+		dev_err(&pdev->dev, "failed to allocate memory\n");
+		return -ENOMEM;
+	}
+
+	pwm->dev = &pdev->dev;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r) {
+		dev_err(&pdev->dev, "no memory resources defined\n");
+		return -ENODEV;
+	}
+
+	r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
+			pdev->name);
+	if (!r) {
+		dev_err(&pdev->dev, "failed to request memory\n");
+		return -EBUSY;
+	}
+
+	pwm->mmio_base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
+	if (!pwm->mmio_base) {
+		dev_err(&pdev->dev, "failed to ioremap() region\n");
+		return -ENODEV;
+	}
+
+	platform_set_drvdata(pdev, pwm);
+
+	pwm->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(pwm->clk))
+		return PTR_ERR(pwm->clk);
+
+	pwm->chip.dev = &pdev->dev;
+	pwm->chip.ops = &tegra_pwm_ops;
+	pwm->chip.base = -1;
+	pwm->chip.npwm = NUM_PWM;
+
+	ret = pwmchip_add(&pwm->chip);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
+		clk_put(pwm->clk);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __devexit tegra_pwm_remove(struct platform_device *pdev)
+{
+	struct tegra_pwm_chip *pwm = platform_get_drvdata(pdev);
+	int i;
+
+	if (WARN_ON(!pwm))
+		return -ENODEV;
+
+	pwmchip_remove(&pwm->chip);
+
+	for (i = 0; i < NUM_PWM; i++) {
+		pwm_writel(pwm, i, 0);
+
+		if (pwm->enable[i])
+			clk_disable(pwm->clk);
+	}
+
+	clk_put(pwm->clk);
+
+	return 0;
+}
+
+static struct platform_driver tegra_pwm_driver = {
+	.driver = {
+		.name = "tegra-pwm",
+	},
+	.probe = tegra_pwm_probe,
+	.remove = __devexit_p(tegra_pwm_remove),
+};
+
+module_platform_driver(tegra_pwm_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("NVIDIA Corporation");
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 14 11:56:30 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 16:56:30 +0100
Subject: [PATCH v4 07/10] pwm: tegra: Add device tree support
In-Reply-To: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331740593-10807-8-git-send-email-thierry.reding@avionic-design.de>

Add auxdata to instantiate the PWFM controller from a device tree,
include the corresponding nodes in the dtsi files for Tegra 20 and
Tegra 30 and add binding documentation.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v4:
  - add DT binding documentation
  - allow nvidia,tegra20-pwm as fallback for nvidia,tegra30-pwm
  - export OF device table (for module auto-loading)

Changes in v3:
  - add missing include for mach/iomap.h

 .../devicetree/bindings/pwm/tegra-pwm.txt          |   18 ++++++++++++++++++
 arch/arm/boot/dts/tegra20.dtsi                     |    6 ++++++
 arch/arm/boot/dts/tegra30.dtsi                     |    6 ++++++
 arch/arm/mach-tegra/board-dt-tegra20.c             |    1 +
 arch/arm/mach-tegra/board-dt-tegra30.c             |    3 +++
 drivers/pwm/pwm-tegra.c                            |   11 +++++++++++
 6 files changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/tegra-pwm.txt

diff --git a/Documentation/devicetree/bindings/pwm/tegra-pwm.txt b/Documentation/devicetree/bindings/pwm/tegra-pwm.txt
new file mode 100644
index 0000000..bbbeedb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/tegra-pwm.txt
@@ -0,0 +1,18 @@
+Tegra SoC PWFM controller
+
+Required properties:
+- compatible: should be one of:
+  - "nvidia,tegra20-pwm"
+  - "nvidia,tegra30-pwm"
+- reg: physical base address and length of the controller's registers
+- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
+  first cell specifies the per-chip index of the PWM to use and the second
+  cell is the duty cycle in nanoseconds.
+
+Example:
+
+	pwm: pwm at 7000a000 {
+		compatible = "nvidia,tegra20-pwm";
+		reg = <0x7000a000 0x100>;
+		#pwm-cells = <2>;
+	};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 108e894..55b28fd 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -154,6 +154,12 @@
 		interrupts = < 0 91 0x04 >;
 	};
 
+	pwm: pwm at 7000a000 {
+		compatible = "nvidia,tegra20-pwm";
+		reg = <0x7000a000 0x100>;
+		#pwm-cells = <2>;
+	};
+
 	emc at 7000f400 {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 62a7b39..3fa5211 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -154,6 +154,12 @@
 		interrupts = < 0 91 0x04 >;
 	};
 
+	pwm: pwm at 7000a000 {
+		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
+		reg = <0x7000a000 0x100>;
+		#pwm-cells = <2>;
+	};
+
 	sdhci at 78000000 {
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000000 0x200>;
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index e20b419..2180954 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -73,6 +73,7 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 		       &tegra_ehci2_device.dev.platform_data),
 	OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
 		       &tegra_ehci3_device.dev.platform_data),
+	OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
 	{}
 };
 
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 5f7c03e..5e1180f 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -33,6 +33,8 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
 
+#include <mach/iomap.h>
+
 #include "board.h"
 #include "clock.h"
 
@@ -51,6 +53,7 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
 	{}
 };
 
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 19540fc..19e96c6 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -242,9 +242,20 @@ static int __devexit tegra_pwm_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id tegra_pwm_of_match[] = {
+	{ .compatible = "nvidia,tegra20-pwm" },
+	{ .compatible = "nvidia,tegra30-pwm" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
+#endif
+
 static struct platform_driver tegra_pwm_driver = {
 	.driver = {
 		.name = "tegra-pwm",
+		.of_match_table = of_match_ptr(tegra_pwm_of_match),
 	},
 	.probe = tegra_pwm_probe,
 	.remove = __devexit_p(tegra_pwm_remove),
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 14 11:56:28 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 16:56:28 +0100
Subject: [PATCH v4 05/10] ARM: tegra: Provide clock for only one PWM controller
In-Reply-To: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331740593-10807-6-git-send-email-thierry.reding@avionic-design.de>

A subsequent patch will add a generic PWM API driver for the Tegra PWFM
controller, supporting all four PWM devices with a single PWM chip. The
device will be named tegra-pwm and only one clock needs to be provided.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
Acked-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/mach-tegra/tegra2_clocks.c |    5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 64735bd..efbe2ed 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -2269,10 +2269,7 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
 	CLK_DUPLICATE("usbd", "tegra-otg", NULL),
 	CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
 	CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-	CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
-	CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
-	CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
-	CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
+	CLK_DUPLICATE("pwm", "tegra-pwm", NULL),
 	CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
 	CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
 	CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 14 11:56:32 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 16:56:32 +0100
Subject: [PATCH v4 09/10] pwm: Add PXA support
In-Reply-To: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331740593-10807-10-git-send-email-thierry.reding@avionic-design.de>

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v3:
  - update PWM ops for changes in patch 2

 arch/arm/plat-pxa/Makefile |    1 -
 arch/arm/plat-pxa/pwm.c    |  304 --------------------------------------------
 drivers/pwm/Kconfig        |    9 ++
 drivers/pwm/Makefile       |    1 +
 drivers/pwm/pwm-pxa.c      |  244 +++++++++++++++++++++++++++++++++++
 5 files changed, 254 insertions(+), 305 deletions(-)
 delete mode 100644 arch/arm/plat-pxa/pwm.c
 create mode 100644 drivers/pwm/pwm-pxa.c

diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index f302d04..af8e484 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -8,5 +8,4 @@ obj-$(CONFIG_PXA3xx)		+= mfp.o
 obj-$(CONFIG_PXA95x)		+= mfp.o
 obj-$(CONFIG_ARCH_MMP)		+= mfp.o
 
-obj-$(CONFIG_HAVE_PWM)		+= pwm.o
 obj-$(CONFIG_PXA_SSP)		+= ssp.o
diff --git a/arch/arm/plat-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c
deleted file mode 100644
index ef32686..0000000
--- a/arch/arm/plat-pxa/pwm.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/pwm.c
- *
- * simple driver for PWM (Pulse Width Modulator) controller
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * 2008-02-13	initial version
- * 		eric miao <eric.miao at marvell.com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/pwm.h>
-
-#include <asm/div64.h>
-
-#define HAS_SECONDARY_PWM	0x10
-#define PWM_ID_BASE(d)		((d) & 0xf)
-
-static const struct platform_device_id pwm_id_table[] = {
-	/*   PWM    has_secondary_pwm? */
-	{ "pxa25x-pwm", 0 },
-	{ "pxa27x-pwm", 0 | HAS_SECONDARY_PWM },
-	{ "pxa168-pwm", 1 },
-	{ "pxa910-pwm", 1 },
-	{ },
-};
-MODULE_DEVICE_TABLE(platform, pwm_id_table);
-
-/* PWM registers and bits definitions */
-#define PWMCR		(0x00)
-#define PWMDCR		(0x04)
-#define PWMPCR		(0x08)
-
-#define PWMCR_SD	(1 << 6)
-#define PWMDCR_FD	(1 << 10)
-
-struct pwm_device {
-	struct list_head	node;
-	struct pwm_device	*secondary;
-	struct platform_device	*pdev;
-
-	const char	*label;
-	struct clk	*clk;
-	int		clk_enabled;
-	void __iomem	*mmio_base;
-
-	unsigned int	use_count;
-	unsigned int	pwm_id;
-};
-
-/*
- * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
- * duty_ns   = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
- */
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
-{
-	unsigned long long c;
-	unsigned long period_cycles, prescale, pv, dc;
-
-	if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
-		return -EINVAL;
-
-	c = clk_get_rate(pwm->clk);
-	c = c * period_ns;
-	do_div(c, 1000000000);
-	period_cycles = c;
-
-	if (period_cycles < 1)
-		period_cycles = 1;
-	prescale = (period_cycles - 1) / 1024;
-	pv = period_cycles / (prescale + 1) - 1;
-
-	if (prescale > 63)
-		return -EINVAL;
-
-	if (duty_ns == period_ns)
-		dc = PWMDCR_FD;
-	else
-		dc = (pv + 1) * duty_ns / period_ns;
-
-	/* NOTE: the clock to PWM has to be enabled first
-	 * before writing to the registers
-	 */
-	clk_enable(pwm->clk);
-	__raw_writel(prescale, pwm->mmio_base + PWMCR);
-	__raw_writel(dc, pwm->mmio_base + PWMDCR);
-	__raw_writel(pv, pwm->mmio_base + PWMPCR);
-	clk_disable(pwm->clk);
-
-	return 0;
-}
-EXPORT_SYMBOL(pwm_config);
-
-int pwm_enable(struct pwm_device *pwm)
-{
-	int rc = 0;
-
-	if (!pwm->clk_enabled) {
-		rc = clk_enable(pwm->clk);
-		if (!rc)
-			pwm->clk_enabled = 1;
-	}
-	return rc;
-}
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-	if (pwm->clk_enabled) {
-		clk_disable(pwm->clk);
-		pwm->clk_enabled = 0;
-	}
-}
-EXPORT_SYMBOL(pwm_disable);
-
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-	struct pwm_device *pwm;
-	int found = 0;
-
-	mutex_lock(&pwm_lock);
-
-	list_for_each_entry(pwm, &pwm_list, node) {
-		if (pwm->pwm_id == pwm_id) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (found) {
-		if (pwm->use_count == 0) {
-			pwm->use_count++;
-			pwm->label = label;
-		} else
-			pwm = ERR_PTR(-EBUSY);
-	} else
-		pwm = ERR_PTR(-ENOENT);
-
-	mutex_unlock(&pwm_lock);
-	return pwm;
-}
-EXPORT_SYMBOL(pwm_request);
-
-void pwm_free(struct pwm_device *pwm)
-{
-	mutex_lock(&pwm_lock);
-
-	if (pwm->use_count) {
-		pwm->use_count--;
-		pwm->label = NULL;
-	} else
-		pr_warning("PWM device already freed\n");
-
-	mutex_unlock(&pwm_lock);
-}
-EXPORT_SYMBOL(pwm_free);
-
-static inline void __add_pwm(struct pwm_device *pwm)
-{
-	mutex_lock(&pwm_lock);
-	list_add_tail(&pwm->node, &pwm_list);
-	mutex_unlock(&pwm_lock);
-}
-
-static int __devinit pwm_probe(struct platform_device *pdev)
-{
-	const struct platform_device_id *id = platform_get_device_id(pdev);
-	struct pwm_device *pwm, *secondary = NULL;
-	struct resource *r;
-	int ret = 0;
-
-	pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
-	if (pwm == NULL) {
-		dev_err(&pdev->dev, "failed to allocate memory\n");
-		return -ENOMEM;
-	}
-
-	pwm->clk = clk_get(&pdev->dev, NULL);
-	if (IS_ERR(pwm->clk)) {
-		ret = PTR_ERR(pwm->clk);
-		goto err_free;
-	}
-	pwm->clk_enabled = 0;
-
-	pwm->use_count = 0;
-	pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id;
-	pwm->pdev = pdev;
-
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (r == NULL) {
-		dev_err(&pdev->dev, "no memory resource defined\n");
-		ret = -ENODEV;
-		goto err_free_clk;
-	}
-
-	r = request_mem_region(r->start, resource_size(r), pdev->name);
-	if (r == NULL) {
-		dev_err(&pdev->dev, "failed to request memory resource\n");
-		ret = -EBUSY;
-		goto err_free_clk;
-	}
-
-	pwm->mmio_base = ioremap(r->start, resource_size(r));
-	if (pwm->mmio_base == NULL) {
-		dev_err(&pdev->dev, "failed to ioremap() registers\n");
-		ret = -ENODEV;
-		goto err_free_mem;
-	}
-
-	if (id->driver_data & HAS_SECONDARY_PWM) {
-		secondary = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
-		if (secondary == NULL) {
-			ret = -ENOMEM;
-			goto err_free_mem;
-		}
-
-		*secondary = *pwm;
-		pwm->secondary = secondary;
-
-		/* registers for the second PWM has offset of 0x10 */
-		secondary->mmio_base = pwm->mmio_base + 0x10;
-		secondary->pwm_id = pdev->id + 2;
-	}
-
-	__add_pwm(pwm);
-	if (secondary)
-		__add_pwm(secondary);
-
-	platform_set_drvdata(pdev, pwm);
-	return 0;
-
-err_free_mem:
-	release_mem_region(r->start, resource_size(r));
-err_free_clk:
-	clk_put(pwm->clk);
-err_free:
-	kfree(pwm);
-	return ret;
-}
-
-static int __devexit pwm_remove(struct platform_device *pdev)
-{
-	struct pwm_device *pwm;
-	struct resource *r;
-
-	pwm = platform_get_drvdata(pdev);
-	if (pwm == NULL)
-		return -ENODEV;
-
-	mutex_lock(&pwm_lock);
-
-	if (pwm->secondary) {
-		list_del(&pwm->secondary->node);
-		kfree(pwm->secondary);
-	}
-
-	list_del(&pwm->node);
-	mutex_unlock(&pwm_lock);
-
-	iounmap(pwm->mmio_base);
-
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	release_mem_region(r->start, resource_size(r));
-
-	clk_put(pwm->clk);
-	kfree(pwm);
-	return 0;
-}
-
-static struct platform_driver pwm_driver = {
-	.driver		= {
-		.name	= "pxa25x-pwm",
-		.owner	= THIS_MODULE,
-	},
-	.probe		= pwm_probe,
-	.remove		= __devexit_p(pwm_remove),
-	.id_table	= pwm_id_table,
-};
-
-static int __init pwm_init(void)
-{
-	return platform_driver_register(&pwm_driver);
-}
-arch_initcall(pwm_init);
-
-static void __exit pwm_exit(void)
-{
-	platform_driver_unregister(&pwm_driver);
-}
-module_exit(pwm_exit);
-
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index eb54042..0ef4f30 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -18,6 +18,15 @@ config PWM_BFIN
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-bfin.
 
+config PWM_PXA
+	tristate "PXA PWM support"
+	depends on ARCH_PXA
+	help
+	  Generic PWM framework driver for PXA.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-pxa.
+
 config PWM_TEGRA
 	tristate "NVIDIA Tegra PWM support"
 	depends on ARCH_TEGRA
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 251b8d2..e859c51 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_PWM)		+= core.o
 obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
+obj-$(CONFIG_PWM_PXA)		+= pwm-pxa.o
 obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c
new file mode 100644
index 0000000..0f3ef5c
--- /dev/null
+++ b/drivers/pwm/pwm-pxa.c
@@ -0,0 +1,244 @@
+/*
+ * linux/arch/arm/mach-pxa/pwm.c
+ *
+ * simple driver for PWM (Pulse Width Modulator) controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * 2008-02-13	initial version
+ * 		eric miao <eric.miao at marvell.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/pwm.h>
+
+#include <asm/div64.h>
+
+#define HAS_SECONDARY_PWM	0x10
+#define PWM_ID_BASE(d)		((d) & 0xf)
+
+static const struct platform_device_id pwm_id_table[] = {
+	/*   PWM    has_secondary_pwm? */
+	{ "pxa25x-pwm", 0 },
+	{ "pxa27x-pwm", 0 | HAS_SECONDARY_PWM },
+	{ "pxa168-pwm", 1 },
+	{ "pxa910-pwm", 1 },
+	{ },
+};
+MODULE_DEVICE_TABLE(platform, pwm_id_table);
+
+/* PWM registers and bits definitions */
+#define PWMCR		(0x00)
+#define PWMDCR		(0x04)
+#define PWMPCR		(0x08)
+
+#define PWMCR_SD	(1 << 6)
+#define PWMDCR_FD	(1 << 10)
+
+struct pxa_pwm_chip {
+	struct pwm_chip	chip;
+	struct device	*dev;
+
+	struct clk	*clk;
+	int		clk_enabled;
+	void __iomem	*mmio_base;
+};
+
+static inline struct pxa_pwm_chip *to_pxa_pwm_chip(struct pwm_chip *chip)
+{
+	return container_of(chip, struct pxa_pwm_chip, chip);
+}
+
+/*
+ * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
+ * duty_ns   = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
+ */
+static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+			  int duty_ns, int period_ns)
+{
+	struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
+	unsigned long long c;
+	unsigned long period_cycles, prescale, pv, dc;
+	unsigned long offset;
+
+	if (period_ns == 0 || duty_ns > period_ns)
+		return -EINVAL;
+
+	offset = pwm->hwpwm ? 0x10 : 0;
+
+	c = clk_get_rate(pc->clk);
+	c = c * period_ns;
+	do_div(c, 1000000000);
+	period_cycles = c;
+
+	if (period_cycles < 1)
+		period_cycles = 1;
+	prescale = (period_cycles - 1) / 1024;
+	pv = period_cycles / (prescale + 1) - 1;
+
+	if (prescale > 63)
+		return -EINVAL;
+
+	if (duty_ns == period_ns)
+		dc = PWMDCR_FD;
+	else
+		dc = (pv + 1) * duty_ns / period_ns;
+
+	/* NOTE: the clock to PWM has to be enabled first
+	 * before writing to the registers
+	 */
+	clk_enable(pc->clk);
+	__raw_writel(prescale, pc->mmio_base + offset + PWMCR);
+	__raw_writel(dc, pc->mmio_base + offset + PWMDCR);
+	__raw_writel(pv, pc->mmio_base + offset + PWMPCR);
+	clk_disable(pc->clk);
+
+	return 0;
+}
+
+static int pxa_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
+	int rc = 0;
+
+	if (!pc->clk_enabled) {
+		rc = clk_enable(pc->clk);
+		if (!rc)
+			pc->clk_enabled++;
+	}
+	return rc;
+}
+
+static void pxa_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
+
+	if (pc->clk_enabled) {
+		clk_disable(pc->clk);
+		pc->clk_enabled--;
+	}
+}
+
+static struct pwm_ops pxa_pwm_ops = {
+	.config = pxa_pwm_config,
+	.enable = pxa_pwm_enable,
+	.disable = pxa_pwm_disable,
+	.owner = THIS_MODULE,
+};
+
+static int __devinit pwm_probe(struct platform_device *pdev)
+{
+	const struct platform_device_id *id = platform_get_device_id(pdev);
+	struct pxa_pwm_chip *pwm;
+	struct resource *r;
+	int ret = 0;
+
+	pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
+	if (pwm == NULL) {
+		dev_err(&pdev->dev, "failed to allocate memory\n");
+		return -ENOMEM;
+	}
+
+	pwm->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(pwm->clk)) {
+		ret = PTR_ERR(pwm->clk);
+		goto err_free;
+	}
+	pwm->clk_enabled = 0;
+
+	pwm->chip.dev = &pdev->dev;
+	pwm->chip.ops = &pxa_pwm_ops;
+	pwm->chip.base = -1;
+	pwm->chip.npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (r == NULL) {
+		dev_err(&pdev->dev, "no memory resource defined\n");
+		ret = -ENODEV;
+		goto err_free_clk;
+	}
+
+	r = request_mem_region(r->start, resource_size(r), pdev->name);
+	if (r == NULL) {
+		dev_err(&pdev->dev, "failed to request memory resource\n");
+		ret = -EBUSY;
+		goto err_free_clk;
+	}
+
+	pwm->mmio_base = ioremap(r->start, resource_size(r));
+	if (pwm->mmio_base == NULL) {
+		dev_err(&pdev->dev, "failed to ioremap() registers\n");
+		ret = -ENODEV;
+		goto err_free_mem;
+	}
+
+	ret = pwmchip_add(&pwm->chip);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, pwm);
+	return 0;
+
+err_free_mem:
+	release_mem_region(r->start, resource_size(r));
+err_free_clk:
+	clk_put(pwm->clk);
+err_free:
+	kfree(pwm);
+	return ret;
+}
+
+static int __devexit pwm_remove(struct platform_device *pdev)
+{
+	struct pxa_pwm_chip *chip;
+	struct resource *r;
+
+	chip = platform_get_drvdata(pdev);
+	if (chip == NULL)
+		return -ENODEV;
+
+	pwmchip_remove(&chip->chip);
+
+	iounmap(chip->mmio_base);
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(r->start, resource_size(r));
+
+	clk_put(chip->clk);
+	kfree(chip);
+	return 0;
+}
+
+static struct platform_driver pwm_driver = {
+	.driver		= {
+		.name	= "pxa25x-pwm",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= pwm_probe,
+	.remove		= __devexit_p(pwm_remove),
+	.id_table	= pwm_id_table,
+};
+
+static int __init pwm_init(void)
+{
+	return platform_driver_register(&pwm_driver);
+}
+arch_initcall(pwm_init);
+
+static void __exit pwm_exit(void)
+{
+	platform_driver_unregister(&pwm_driver);
+}
+module_exit(pwm_exit);
+
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 14 11:56:31 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 16:56:31 +0100
Subject: [PATCH v4 08/10] pwm: Add Blackfin support
In-Reply-To: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1331740593-10807-9-git-send-email-thierry.reding@avionic-design.de>

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v3:
  - update PWM ops for changes in patch 2

 arch/blackfin/Kconfig         |   10 ---
 arch/blackfin/kernel/Makefile |    1 -
 arch/blackfin/kernel/pwm.c    |  100 -------------------------
 drivers/pwm/Kconfig           |    9 +++
 drivers/pwm/Makefile          |    1 +
 drivers/pwm/pwm-bfin.c        |  164 +++++++++++++++++++++++++++++++++++++++++
 6 files changed, 174 insertions(+), 111 deletions(-)
 delete mode 100644 arch/blackfin/kernel/pwm.c
 create mode 100644 drivers/pwm/pwm-bfin.c

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index c1269a1..e08f39b 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -950,16 +950,6 @@ config BFIN_GPTIMERS
 	  To compile this driver as a module, choose M here: the module
 	  will be called gptimers.
 
-config HAVE_PWM
-	tristate "Enable PWM API support"
-	depends on BFIN_GPTIMERS
-	help
-	  Enable support for the Pulse Width Modulation framework (as
-	  found in linux/pwm.h).
-
-	  To compile this driver as a module, choose M here: the module
-	  will be called pwm.
-
 choice
 	prompt "Uncached DMA region"
 	default DMA_UNCACHED_1M
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 1f88edd..03f60a6 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_FUNCTION_TRACER)        += ftrace-entry.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)  += ftrace.o
 CFLAGS_REMOVE_ftrace.o = -pg
 
-obj-$(CONFIG_HAVE_PWM)               += pwm.o
 obj-$(CONFIG_IPIPE)                  += ipipe.o
 obj-$(CONFIG_BFIN_GPTIMERS)          += gptimers.o
 obj-$(CONFIG_CPLB_INFO)              += cplbinfo.o
diff --git a/arch/blackfin/kernel/pwm.c b/arch/blackfin/kernel/pwm.c
deleted file mode 100644
index 33f5942..0000000
--- a/arch/blackfin/kernel/pwm.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Blackfin Pulse Width Modulation (PWM) core
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/pwm.h>
-#include <linux/slab.h>
-
-#include <asm/gptimers.h>
-#include <asm/portmux.h>
-
-struct pwm_device {
-	unsigned id;
-	unsigned short pin;
-};
-
-static const unsigned short pwm_to_gptimer_per[] = {
-	P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR4, P_TMR5,
-	P_TMR6, P_TMR7, P_TMR8, P_TMR9, P_TMR10, P_TMR11,
-};
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-	struct pwm_device *pwm;
-	int ret;
-
-	/* XXX: pwm_id really should be unsigned */
-	if (pwm_id < 0)
-		return NULL;
-
-	pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
-	if (!pwm)
-		return pwm;
-
-	pwm->id = pwm_id;
-	if (pwm->id >= ARRAY_SIZE(pwm_to_gptimer_per))
-		goto err;
-
-	pwm->pin = pwm_to_gptimer_per[pwm->id];
-	ret = peripheral_request(pwm->pin, label);
-	if (ret)
-		goto err;
-
-	return pwm;
- err:
-	kfree(pwm);
-	return NULL;
-}
-EXPORT_SYMBOL(pwm_request);
-
-void pwm_free(struct pwm_device *pwm)
-{
-	peripheral_free(pwm->pin);
-	kfree(pwm);
-}
-EXPORT_SYMBOL(pwm_free);
-
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
-{
-	unsigned long period, duty;
-	unsigned long long val;
-
-	if (duty_ns < 0 || duty_ns > period_ns)
-		return -EINVAL;
-
-	val = (unsigned long long)get_sclk() * period_ns;
-	do_div(val, NSEC_PER_SEC);
-	period = val;
-
-	val = (unsigned long long)period * duty_ns;
-	do_div(val, period_ns);
-	duty = period - val;
-
-	if (duty >= period)
-		duty = period - 1;
-
-	set_gptimer_config(pwm->id, TIMER_MODE_PWM | TIMER_PERIOD_CNT);
-	set_gptimer_pwidth(pwm->id, duty);
-	set_gptimer_period(pwm->id, period);
-
-	return 0;
-}
-EXPORT_SYMBOL(pwm_config);
-
-int pwm_enable(struct pwm_device *pwm)
-{
-	enable_gptimer(pwm->id);
-	return 0;
-}
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-	disable_gptimer(pwm->id);
-}
-EXPORT_SYMBOL(pwm_disable);
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index bda6f23..eb54042 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -9,6 +9,15 @@ menuconfig PWM
 
 if PWM
 
+config PWM_BFIN
+	tristate "Blackfin PWM support"
+	depends on BFIN_GPTIMERS
+	help
+	  Generic PWM framework driver for Blackfin.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-bfin.
+
 config PWM_TEGRA
 	tristate "NVIDIA Tegra PWM support"
 	depends on ARCH_TEGRA
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 12300f5..251b8d2 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_PWM)		+= core.o
+obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
 obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
diff --git a/drivers/pwm/pwm-bfin.c b/drivers/pwm/pwm-bfin.c
new file mode 100644
index 0000000..a0c6bf9
--- /dev/null
+++ b/drivers/pwm/pwm-bfin.c
@@ -0,0 +1,164 @@
+/*
+ * Blackfin Pulse Width Modulation (PWM) core
+ *
+ * Copyright (c) 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/slab.h>
+
+#include <asm/gptimers.h>
+#include <asm/portmux.h>
+
+struct bfin_pwm_chip {
+	struct pwm_chip chip;
+};
+
+struct bfin_pwm {
+	unsigned short pin;
+};
+
+static const unsigned short pwm_to_gptimer_per[] = {
+	P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR4, P_TMR5,
+	P_TMR6, P_TMR7, P_TMR8, P_TMR9, P_TMR10, P_TMR11,
+};
+
+static int bfin_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct bfin_pwm *priv;
+	int ret;
+
+	if (pwm->hwpwm >= ARRAY_SIZE(pwm_to_gptimer_per))
+		return -EINVAL;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->pin = pwm_to_gptimer_per[pwm->hwpwm];
+
+	ret = peripheral_request(priv->pin, NULL);
+	if (ret) {
+		kfree(priv);
+		return ret;
+	}
+
+	pwm_set_chip_data(pwm, priv);
+
+	return 0;
+}
+
+static void bfin_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct bfin_pwm *priv = pwm_get_chip_data(pwm);
+
+	if (priv) {
+		peripheral_free(priv->pin);
+		kfree(priv);
+	}
+}
+
+static int bfin_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+		int duty_ns, int period_ns)
+{
+	struct bfin_pwm *priv = pwm_get_chip_data(pwm);
+	unsigned long period, duty;
+	unsigned long long val;
+
+	if (duty_ns < 0 || duty_ns > period_ns)
+		return -EINVAL;
+
+	val = (unsigned long long)get_sclk() * period_ns;
+	do_div(val, NSEC_PER_SEC);
+	period = val;
+
+	val = (unsigned long long)period * duty_ns;
+	do_div(val, period_ns);
+	duty = period - val;
+
+	if (duty >= period)
+		duty = period - 1;
+
+	set_gptimer_config(priv->pin, TIMER_MODE_PWM | TIMER_PERIOD_CNT);
+	set_gptimer_pwidth(priv->pin, duty);
+	set_gptimer_period(priv->pin, period);
+
+	return 0;
+}
+
+static int bfin_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct bfin_pwm *priv = pwm_get_chip_data(pwm);
+
+	enable_gptimer(priv->pin);
+
+	return 0;
+}
+
+static void bfin_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct bfin_pwm *priv = pwm_get_chip_data(pwm);
+
+	disable_gptimer(priv->pin);
+}
+
+static struct pwm_ops bfin_pwm_ops = {
+	.request = bfin_pwm_request,
+	.free = bfin_pwm_free,
+	.config = bfin_pwm_config,
+	.enable = bfin_pwm_enable,
+	.disable = bfin_pwm_disable,
+	.owner = THIS_MODULE,
+};
+
+static int bfin_pwm_probe(struct platform_device *pdev)
+{
+	struct bfin_pwm_chip *pwm;
+	int ret;
+
+	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
+	if (!pwm) {
+		dev_err(&pdev->dev, "failed to allocate memory\n");
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, pwm);
+
+	pwm->chip.dev = &pdev->dev;
+	pwm->chip.ops = &bfin_pwm_ops;
+	pwm->chip.base = -1;
+	pwm->chip.npwm = 12;
+
+	ret = pwmchip_add(&pwm->chip);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __devexit bfin_pwm_remove(struct platform_device *pdev)
+{
+	struct bfin_pwm_chip *pwm = platform_get_drvdata(pdev);
+
+	pwmchip_remove(&pwm->chip);
+
+	return 0;
+}
+
+static struct platform_driver bfin_pwm_driver = {
+	.driver = {
+		.name = "bfin-pwm",
+	},
+	.probe = bfin_pwm_probe,
+	.remove = __devexit_p(bfin_pwm_remove),
+};
+
+module_platform_driver(bfin_pwm_driver);
+
+MODULE_LICENSE("GPL");
-- 
1.7.9.4



From hartleys at visionengravers.com  Wed Mar 14 12:20:21 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 14 Mar 2012 11:20:21 -0500
Subject: [PATCH v4 00/11] ep93xx: Move SoC private bits to core
In-Reply-To: <201203141351.06200.arnd@arndb.de>
References: <1331592502-9083-1-git-send-email-rmallon@gmail.com>
 <201203131235.53593.arnd@arndb.de> <4F5FC8AD.4070505@gmail.com>
 <201203141351.06200.arnd@arndb.de>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020695AB9B9B@AUSP01VMBX24.collaborationhost.net>

On Wednesday, March 14, 2012 6:51 AM, Arnd Bergmann wrote:
> On Tuesday 13 March 2012, Ryan Mallon wrote:
>>> There are currently eight board files (since all the dev boards got
>>> merged into one file), which seems very manageable and there should be
>>> no problem adding a few more over the years to come, if necessary.
>> 
>> I doubt there will be many new boards added.
>> 
>>> At the same time, the platform seems simple enough that you could
>>> also do a device tree port in rather in a fairly short time if you
>>> like, which would let you obsolete all the board files and add new
>>> machines just through device tree blobs.
>> 
>> 
>> Yeah, converting to device tree is one of my goals. I need to spend some
>> time reading through the device tree specification first.
>
> Ok, great!
>
> A number of ARM9 and XScale based platforms have started the conversion
> now, and there is a lot you can learn by looking at the others. I would
> recommend waiting for 3.4-rc1 before you get serious with this, because
> patches are pending in various trees at the moment.
>
> There is no strict need for you to do the conversion, because you say
> that the platform is basically dead and there is not much churn to be
> expected in the future, but you are definitely welcome to join in.
>
> As the first steps (after reading Documentation/devicetree/booting-without-of.txt)
> the best way forward is probably to take you favourite board file and
> add a DT_MACHINE_START section so you can boot the same machine
> when passing an empty devicetree rather than ATAGS. Then add the interrupt
> controller (should be simple for VIC), followed by gpio (needs bindings,
> see Documentation/devicetree/bindings/gpio/*.txt), i2c and spi. After
> you have all that infrastructure in place, you can convert every other
> device, one at a time. Some (anything without platform_data) will be
> Trivial, others require you to come up with a new binding document
> and properties to replace the platform_data. Many people try to do
> the ones from board files first because it lets them remove the board
> files, and only after that look at converting the core devices, but you
> can do any order you like.

The main problem I see with converting the ep93xx platform to device tree
is that it requires modifying the bootloader. Correct me if I am wrong.

Most of the ep93xx boards use RedBoot for the bootloader. Unfortunately
Cirrus never released the ep93xx port to eCos so the source is not available.
You can dig it out of the stuff Cirrus has on http://arm.cirrus.com but it's
based on a pretty old version of eCos/RedBoot and might be quite a task
getting it current.

A couple years ago I tried getting Cirrus to release the source to eCos. It got
to the point where it appeared they would but nothing ever happened.

Some of the ep93xx boards use U-Boot for the bootloader but I think that
port has recently been dropped from the tree.

Regards,
Hartley



From nico at fluxnic.net  Wed Mar 14 11:24:36 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 14 Mar 2012 11:24:36 -0400 (EDT)
Subject: [PATCH v3 1/5] ARM: protect usage of cr_alignment by #ifdef
 CONFIG_CPU_CP15
In-Reply-To: <1331720483-10075-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
 <1331720483-10075-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <alpine.LFD.2.02.1203141103080.24151@xanadu.home>

On Wed, 14 Mar 2012, Uwe Kleine-K?nig wrote:

> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

I think you could reduce the amount of #ifdef's significantly here.  
While the cr_alignment variable and its sister are of no use in a 
no-CP15 system, you could still leave them there initialized to zero and 
only conditionally compile out the CP15 modifyers with a dummy version.  
This is only 2 words wasted in your kernel image to keep the code 
cleaner.

More comments below.

> index 854bd22..efeb2d0 100644
> --- a/arch/arm/kernel/head-common.S
> +++ b/arch/arm/kernel/head-common.S
> @@ -98,8 +98,10 @@ __mmap_switched:
>  	str	r9, [r4]			@ Save processor ID
>  	str	r1, [r5]			@ Save machine type
>  	str	r2, [r6]			@ Save atags pointer
> -	bic	r4, r0, #CR_A			@ Clear 'A' bit
> -	stmia	r7, {r0, r4}			@ Save control register values
> +	cmp	r7, #0
> +	itt	ne
> +	bicne	r4, r0, #CR_A			@ Clear 'A' bit
> +	stmneia	r7, {r0, r4}			@ Save control register values

The kernel is compiled with -mimplicit-it so you do not need to specify 
any it here.

> index a255c39..50d3df8 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -472,9 +472,13 @@ static void __init setup_processor(void)
>  	cpu_cache = *list->cache;
>  #endif
>  
> -	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
> +	printk("CPU: %s [%08x] revision %d (ARMv%s)",
>  	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
> -	       proc_arch[cpu_architecture()], cr_alignment);
> +	       proc_arch[cpu_architecture()]);
> +
> +#ifdef CONFIG_CPU_CP15
> +	printk(KERN_CONT ", cr=%08lx\n", cr_alignment);
> +#endif
>  

Again, you could just leave the original display, with cr=00000000 which 
is a fairly good representation of reality.

> diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
> index caf14dc..119d178 100644
> --- a/arch/arm/mm/alignment.c
> +++ b/arch/arm/mm/alignment.c
> @@ -89,7 +89,11 @@ core_param(alignment, ai_usermode, int, 0600);
>  /* Return true if and only if the ARMv6 unaligned access model is in use. */
>  static bool cpu_is_v6_unaligned(void)
>  {
> +#ifdef CONFIG_CPU_CP15
>  	return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
> +#else
> +	return 0;
> +#endif
>  }

Same here.  With cr_alignment set to zero, you don't need the above 
#ifdef.

>  static int safe_usermode(int new_usermode, bool warn)
> @@ -961,12 +965,14 @@ static int __init alignment_init(void)
>  		return -ENOMEM;
>  #endif
>  
> +#ifdef CONFIG_CPU_CP15
>  	if (cpu_is_v6_unaligned()) {
>  		cr_alignment &= ~CR_A;
>  		cr_no_alignment &= ~CR_A;
>  		set_cr(cr_alignment);
>  		ai_usermode = safe_usermode(ai_usermode, false);
>  	}
> +#endif

Here the #ifdef is probably legitimate.

>  	hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
>  			"alignment exception");
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index 94c5a0c..f6dbe1a 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -109,8 +109,10 @@ static int __init early_cachepolicy(char *p)
>  
>  		if (memcmp(p, cache_policies[i].policy, len) == 0) {
>  			cachepolicy = i;
> +#ifdef CONFIG_CPU_CP15
>  			cr_alignment &= ~cache_policies[i].cr_mask;
>  			cr_no_alignment &= ~cache_policies[i].cr_mask;
> +#endif

Probably here as well.

>  			break;
>  		}
>  	}
> @@ -128,7 +130,9 @@ static int __init early_cachepolicy(char *p)
>  		cachepolicy = CPOLICY_WRITEBACK;
>  	}
>  	flush_cache_all();
> +#ifdef CONFIG_CPU_CP15
>  	set_cr(cr_alignment);
> +#endif

However it might be best to provide a dummy set_cr() instead of 
#ifdef'ing it out everywhere.


Nicolas

From plagnioj at jcrosoft.com  Wed Mar 14 12:21:52 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 14 Mar 2012 17:21:52 +0100
Subject: [PATCH v2] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <1331737232-25477-1-git-send-email-sr@denx.de>
References: <1331737232-25477-1-git-send-email-sr@denx.de>
Message-ID: <20120314162152.GN18320@game.jcrosoft.org>

On 16:00 Wed 14 Mar     , Stefan Roese wrote:
> This patch adds a generic target for SPEAr600 board that can be
> configured via the device-tree. Currently the following devices
> are supported via the devicetree:
> 
> - VIC interrupts
> - PL011 UART
> - PL061 GPIO
> - Synopsys DW I2C
> - Synopsys DW ethernet
> 
> Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
> follow in later patches.
> 
> Only the spear600-evb is currently supported. Other SPEAr600
> based boards will follow later.
> 
> Additionally the file spear600.c is deleted. It contained only
> one empty function and is not needed. So lets just remove it.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> Cc: Arnd Bergmann <arnd at arndb.de>
> ---
> v2:
> - Added DT support to spear6xx.c instead of creating board-dt.c
> - Removed UART (PL011) and GPIO (PL061) platform data for
>   devicetree board port. This works now via DT probing
> - Added OF_DEV_AUXDATA for clock device name matching for some
>   device drivers
> - Removed sper600.c file completely
> - Added DW I2C and ethernet nodes to the dts files
> - Added other DT nodes (SMI, FSMC, ECHI, OHCI), currently disabled
>   since the corresponding device drivers don't support DT probing
> - Removed Linaro/FSL copyright notice from SPEAr DT files (copy-paste cruft)
> - Many smaller modification to the dts/dtsi files
> - Changed Documentation/devicetree/bindings/arm/spear.txt to match
>   the changed bindings
> 
>  Documentation/devicetree/bindings/arm/spear.txt |    8 ++
>  arch/arm/boot/dts/spear600-evb.dts              |   30 +++++
>  arch/arm/boot/dts/spear600.dtsi                 |  162 +++++++++++++++++++++++
>  arch/arm/mach-spear6xx/Kconfig                  |    7 +
>  arch/arm/mach-spear6xx/Makefile                 |    3 -
>  arch/arm/mach-spear6xx/spear600.c               |   25 ----
>  arch/arm/mach-spear6xx/spear600_evb.c           |    3 -
>  arch/arm/mach-spear6xx/spear6xx.c               |   69 +++++++++-
>  8 files changed, 270 insertions(+), 37 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
>  create mode 100644 arch/arm/boot/dts/spear600-evb.dts
>  create mode 100644 arch/arm/boot/dts/spear600.dtsi
>  delete mode 100644 arch/arm/mach-spear6xx/spear600.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
> new file mode 100644
> index 0000000..f8e54f0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/spear.txt
> @@ -0,0 +1,8 @@
> +ST SPEAr Platforms Device Tree Bindings
> +---------------------------------------
> +
> +Boards with the ST SPEAr600 SoC shall have the following properties:
> +
> +Required root node property:
> +
> +compatible = "st,spear600";
> diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
> new file mode 100644
> index 0000000..cbfda8d
> --- /dev/null
> +++ b/arch/arm/boot/dts/spear600-evb.dts
> @@ -0,0 +1,30 @@
> +/*
> + * Copyright 2012 Stefan Roese <sr at denx.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "spear600.dtsi"
> +
> +/ {
> +	model = "ST SPEAr600 Evaluation Board";
> +	compatible = "st,spear600-evb", "st,spear600";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
please put the mem size here


> +
> +	soc {
> +		gmac0: ethernet at e0800000 {
> +			phy-mode = "gmii";
> +		};
> +
> +		i2c at d0200000 {
> +			clock-frequency = <400000>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
> new file mode 100644
> index 0000000..e45e58f
> --- /dev/null
> +++ b/arch/arm/boot/dts/spear600.dtsi
> @@ -0,0 +1,162 @@
> +/*
> + * Copyright 2012 Stefan Roese <sr at denx.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	compatible = "st,spear600";
> +
> +	cpus {
> +		cpu at 0 {
> +			compatible = "arm,arm926ejs";
> +		};
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0 0>; /* Filled by U-Boot */
please put the max mem of the SoC here
> +	};
> +
> +	soc {
please put the name of the bus not soc
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		vic0: interrupt-controller at f1100000 {
> +			compatible = "arm,pl190-vic";
> +			interrupt-controller;
> +			reg = <0xf1100000 0x1000>;
> +			#interrupt-cells = <1>;
> +		};
> +
> +		vic1: interrupt-controller at f1000000 {
> +			compatible = "arm,pl190-vic";
> +			interrupt-controller;
> +			reg = <0xf1000000 0x1000>;
> +			#interrupt-cells = <1>;
> +		};
> +
> +		serial at d0000000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0xd0000000 0x1000>;
> +			interrupt-parent = <&vic0>;
> +			interrupts = <24>;
> +		};
> +
> +		serial at d0080000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0xd0080000 0x1000>;
> +			interrupt-parent = <&vic0>;
> +			interrupts = <25>;
> +		};
> +
> +		/* local/cpu GPIO */
> +		gpio0: gpio at f0100000 {
> +			#gpio-cells = <2>;
> +			compatible = "arm,pl061", "arm,primecell";
> +			gpio-controller;
> +			reg = <0xf0100000 0x1000>;
> +			interrupt-parent = <&vic0>;
> +			interrupts = <18>;
> +		};
> +
> +		/* basic GPIO */
> +		gpio1: gpio at fc980000 {
> +			#gpio-cells = <2>;
> +			compatible = "arm,pl061", "arm,primecell";
> +			gpio-controller;
> +			reg = <0xfc980000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <19>;
> +		};
> +
> +		/* appl GPIO */
> +		gpio2: gpio at d8100000 {
> +			#gpio-cells = <2>;
> +			compatible = "arm,pl061", "arm,primecell";
> +			gpio-controller;
> +			reg = <0xd8100000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <4>;
> +		};
> +
> +		gmac0: ethernet at e0800000 {
> +			compatible = "st,spear600-gmac";
> +			reg = <0xe0800000 0x8000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <24 23>;
> +			interrupt-names = "macirq", "eth_wake_irq";
> +			mac-address = [000000000000]; /* Filled in by U-Boot */
> +		};
> +
> +		i2c at d0200000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "snps,designware-i2c";
> +			reg = <0xd0200000 0x1000>;
> +			interrupt-parent = <&vic0>;
> +			interrupts = <28>;
> +		};
> +
> +		fsmc0: flash at d1800000 {
> +			status = "disabled";
> +			compatible = "st,spear600-fsmc-nand";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0xd1800000 0x1000	/* FSMC Register */
> +			       0xd2000000 0x4000>;	/* NAND Base */
> +			reg-names = "fsmc_regs", "nand_data";
> +		};
> +
> +		smi0: flash at fc000000 {
> +			status = "disabled";
> +			compatible = "st,spear600-smi";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0xfc000000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <12>;
> +		};
> +
> +		ehci at e1800000 {
> +			status = "disabled";
> +			compatible = "st,spear600-ehci", "usb-ehci";
> +			reg = <0xe1800000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <27>;
> +		};
> +
> +		ehci at e2000000 {
> +			status = "disabled";
> +			compatible = "st,spear600-ehci", "usb-ehci";
> +			reg = <0xe2000000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <29>;
> +		};
> +
> +		ohci at e1900000 {
> +			status = "disabled";
> +			compatible = "st,spear600-ohci", "usb-ohci";
> +			reg = <0xe1900000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <26>;
> +		};
> +
> +		ohci at e2100000 {
> +			status = "disabled";
> +			compatible = "st,spear600-ohci", "usb-ohci";
> +			reg = <0xe2100000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <28>;
> +		};
all of this need a Doc for the ST bindings
> +	};
> +};
> diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
> index ff4ae5b..7777f72 100644
> --- a/arch/arm/mach-spear6xx/Kconfig
> +++ b/arch/arm/mach-spear6xx/Kconfig
> @@ -11,6 +11,13 @@ config BOARD_SPEAR600_EVB
>  	help
>  	  Supports ST SPEAr600 Evaluation Board
>  
> +config BOARD_SPEAR600_DT
> +	bool "SPEAr600 generic board configured via device-tree"
> +	select MACH_SPEAR600
> +	select USE_OF
> +	help
> +	  Supports ST SPEAr600 boards configured via the device-tree
> +
>  endmenu
>  
>  config MACH_SPEAR600
> diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
> index cc1a4d8..6f87c3a 100644
> --- a/arch/arm/mach-spear6xx/Makefile
> +++ b/arch/arm/mach-spear6xx/Makefile
> @@ -5,8 +5,5 @@
>  # common files
>  obj-y	+= clock.o spear6xx.o
>  
> -# spear600 specific files
> -obj-$(CONFIG_MACH_SPEAR600) += spear600.o
> -
>  # spear600 boards files
>  obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
> diff --git a/arch/arm/mach-spear6xx/spear600.c b/arch/arm/mach-spear6xx/spear600.c
> deleted file mode 100644
> index d0e6eea..0000000
> --- a/arch/arm/mach-spear6xx/spear600.c
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -/*
> - * arch/arm/mach-spear6xx/spear600.c
> - *
> - * SPEAr600 machine source file
> - *
> - * Copyright (C) 2009 ST Microelectronics
> - * Rajeev Kumar<rajeev-dlh.kumar at st.com>
> - *
> - * This file is licensed under the terms of the GNU General Public
> - * License version 2. This program is licensed "as is" without any
> - * warranty of any kind, whether express or implied.
> - */
> -
> -#include <linux/ptrace.h>
> -#include <asm/irq.h>
> -#include <mach/generic.h>
> -#include <mach/hardware.h>
> -
> -/* Add spear600 specific devices here */
> -
> -void __init spear600_init(void)
> -{
> -	/* call spear6xx family common init function */
> -	spear6xx_init();
> -}
> diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
> index c6e4254..c4949aa 100644
> --- a/arch/arm/mach-spear6xx/spear600_evb.c
> +++ b/arch/arm/mach-spear6xx/spear600_evb.c
> @@ -32,9 +32,6 @@ static void __init spear600_evb_init(void)
>  {
>  	unsigned int i;
>  
> -	/* call spear600 machine init function */
> -	spear600_init();
> -
>  	/* Add Platform Devices */
>  	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
>  
> diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
> index e0f6628..aca20f0 100644
> --- a/arch/arm/mach-spear6xx/spear6xx.c
> +++ b/arch/arm/mach-spear6xx/spear6xx.c
> @@ -6,6 +6,8 @@
>   * Copyright (C) 2009 ST Microelectronics
>   * Rajeev Kumar<rajeev-dlh.kumar at st.com>
>   *
> + * Copyright 2012 Stefan Roese <sr at denx.de>
> + *
>   * This file is licensed under the terms of the GNU General Public
>   * License version 2. This program is licensed "as is" without any
>   * warranty of any kind, whether express or implied.
> @@ -15,6 +17,10 @@
>  #include <linux/amba/pl061.h>
>  #include <linux/ptrace.h>
>  #include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
>  #include <asm/hardware/vic.h>
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
> @@ -99,12 +105,6 @@ struct amba_device gpio_device[] = {
>  	}
>  };
>  
> -/* This will add devices, and do machine specific tasks */
> -void __init spear6xx_init(void)
> -{
> -	/* nothing to do for now */
> -}
> -
>  /* This will initialize vic */
>  void __init spear6xx_init_irq(void)
>  {
> @@ -181,3 +181,60 @@ static void __init spear6xx_timer_init(void)
>  struct sys_timer spear6xx_timer = {
>  	.init = spear6xx_timer_init,
>  };
> +
> +/*
> + * Devicetree specific init structs/functions:
> + * Once the SPEAr600 devicetree support has matured, we can remove
> + * spear600_evb.c and the non-devicetree support above in this file.
> + */
> +
> +/*
> + * Add auxdata so that clock name matching doesn't fail in device
> + * drivers
> + */
> +struct of_dev_auxdata spear600_auxdata_lookup[] __initdata = {
> +	OF_DEV_AUXDATA("arm,pl011", SPEAR6XX_ICM1_UART0_BASE,
> +		       "uart0", NULL),
> +	OF_DEV_AUXDATA("arm,pl011", SPEAR6XX_ICM1_UART1_BASE,
> +		       "uart1", NULL),
> +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_CPU_GPIO_BASE,
> +		       "gpio0", NULL),
> +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_ICM3_GPIO_BASE,
> +		       "gpio1", NULL),
> +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_ICM2_GPIO_BASE,
> +		       "gpio2", NULL),
> +	OF_DEV_AUXDATA("snps,designware-i2c", SPEAR6XX_ICM1_I2C_BASE,
> +		       "i2c_designware.0", NULL),
update the clkdev no more OF_DEV_AUXDATA


please keep me in Cc

Best Regards,
J.


From tony at atomide.com  Wed Mar 14 12:35:47 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 14 Mar 2012 09:35:47 -0700
Subject: [GIT PULL 1/7] non-critical fixes part3 for upcoming merge window
In-Reply-To: <20120310182425.GA698@quad.lixom.net>
References: <4f591c4d.e471340a.1f3f.3a69SMTPIN_ADDED@mx.google.com>
 <20120310182425.GA698@quad.lixom.net>
Message-ID: <20120314163547.GO12083@atomide.com>

Hi Olof,

* Olof Johansson <olof at lixom.net> [120310 10:26]:
> On Thu, Mar 08, 2012 at 12:53:29PM -0800, Tony Lindgren wrote:
> > Hi Olof,
> > 
> > Here are two more pre-emptive fixes for upcoming merge
> > window to pull into arm-soc/next/fixes-non-critical.
> > 
> > Now with the fixes finallny out of the way after all
> > the cleanup related changes, as a reply to this pull
> > request I'm posting some more pull requests for cleanup
> > and some minor board changes.
> 
> Pulled request 1-7.

Now with another -rc, can you please pull in also
2 - 7 in this series?

Regards,

Tony


From plagnioj at jcrosoft.com  Wed Mar 14 12:26:28 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 14 Mar 2012 17:26:28 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <4F60832E.6060100@st.com>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <20120312143825.GB13869@game.jcrosoft.org>
 <4F60832E.6060100@st.com>
Message-ID: <20120314162628.GO18320@game.jcrosoft.org>

On 12:38 Wed 14 Mar     , Giuseppe CAVALLARO wrote:
> On 3/12/2012 3:38 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 15:05 Mon 12 Mar     , Stefan Roese wrote:
> >> This patch adds support to configure the STMMAC ethernet driver via
> >> device-tree instead of platform_data.
> >>
> >> Currently, only the properties needed on SPEAr600 are provided. All
> >> other properties should be added once needed on other platforms.
> >>
> >> Signed-off-by: Stefan Roese <sr at denx.de>
> >> Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
> >> Cc: Viresh Kumar <viresh.kumar at st.com>
> >> ---
> >>  Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
> >>  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66 +++++++++++++++++++-
> >>  2 files changed, 103 insertions(+), 1 deletion(-)
> >>  create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
> >> new file mode 100644
> >> index 0000000..386a47f
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/net/stmmac.txt
> >> @@ -0,0 +1,38 @@
> >> +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
> >> +
> >> +Required properties:
> >> +- compatible: Should be "stm,gmac"
> 
> > this IP have 2 version at least the GMAC for the second generation and mac for
> > the first generation
> 
> yes you are right. STMMAC supports two device generations I named:
> dwma10/100 and dwmac1000 (gmac).
> 
> Concerning the latter, we support several different versions of the
> synopsys GMAC cores ... from 3.30 to 3.61a.
> 
> For example, stx7108 and Stx7109 have the same GMAC core (also SPEAr600
> IIRC).
no PM the PM was only since 7108 IIRC

7109 use mac not gmac IIRC it's 7105 that start to use the GMAC with 300Mbps
max
> SPEAr13xx has 3.50a
> New ST SoC Stxh415 has the 3.60a. etc.
> 
> >> +- reg: Address and length of the register set for the device
> >> +- interrupt-parent: Should be the phandle for the interrupt controller
> >> +  that services interrupts for this device
> >> +- interrupts: Should contain the STMMAC interrupts
> >> +- interrupt-names: Should contain the interrupt names "macirq"
> >> +  "eth_wake_irq" if this interrupt is supported in the "interrupts"
> >> +  property
> > optionnal
> 
> yes
> 
> note that there will be a new field for lpi IRQ as well
> 
> >> +- phy-mode: String, operation mode of the PHY interface.
> >> +  Supported values are: "mii", "rmii", "gmii", "rgmii".
> >> +- phy-addr: MDIO address of the PHY
> >> +
> >> +Optional properties:
> >> +- stm,prog-burst-len: Specify the burst length
> >> +- stm,has-gmac: Indicates that the controller supports 1000Mbps
> > this IP support more mode 10/100/300/1000
> 
> has_gmac was used to understand on devices w/o the HW cap registers if
> the core is a gmac... another useful parameter could be : enh_desc
this need to manage via compatible

Best Regards,
J.


From notasas at gmail.com  Wed Mar 14 12:41:51 2012
From: notasas at gmail.com (Grazvydas Ignotas)
Date: Wed, 14 Mar 2012 18:41:51 +0200
Subject: [GIT PULL] cpufreq: OMAP updates for v3.4
In-Reply-To: <87y5rci2na.fsf@ti.com>
References: <87y5rci2na.fsf@ti.com>
Message-ID: <CANOLnON91vXWb2L-FXjz3sqq-9j5SaEodtpt_yvFiN33D4Q3Ow@mail.gmail.com>

On Wed, Mar 7, 2012 at 10:20 PM, Kevin Hilman <khilman at ti.com> wrote:
> Dave,
>
> Please pull the following OMAP CPUfreq driver changes for v3.4.
>
> Thanks,
>
> Kevin
>
>
>
> The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:
>
> ?Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)
>
> are available in the git repository at:
>
> ?git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/cpufreq
>
> for you to fetch changes up to 42daffd2d6c665716d442d518022ecaad17ddf64:
>
> ?cpufreq: OMAP: specify range for voltage scaling (2012-03-02 13:55:57 -0800)
>
> ----------------------------------------------------------------
> Afzal Mohammed (1):
> ? ? ?cpufreq: OMAP: specify range for voltage scaling
>
> Kevin Hilman (1):
> ? ? ?cpufreq: OMAP: scale voltage along with frequency
>
> Russell King (1):
> ? ? ?cpufreq: OMAP driver depends CPUfreq tables

It seems this one got messed up, it says "default ARCH_OMAP2PLUS"
instead of depends.
Can it be dropped and resent, or do we need a fixup patch?

-- 
Gra?vydas


From lars at metafoo.de  Wed Mar 14 12:26:55 2012
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Wed, 14 Mar 2012 17:26:55 +0100
Subject: [PATCH v3 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 DMA APIs
In-Reply-To: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>
References: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>
Message-ID: <4F60C6CF.4090608@metafoo.de>

> [...]
> +
> +struct dma_async_tx_descriptor *msm_dma_prep_interleaved(struct dma_chan *dchan,
> +					struct dma_interleaved_template *xt,
> +					unsigned long flags, void *context)
> +{
> +
> +	struct msm_dma_chan *chan;
> +	struct msm_dma_desc_sw *new;
> +	struct adm_box_cmd_t *box_cmd_vaddr;
> +	u32 *cmd_cntrl = context;
> +
> +	if (!dchan)
> +		return ERR_PTR(-EINVAL);

This is supposed to return either NULL or a valid descriptor.

> +
> +	if (!xt)
> +		return ERR_PTR(-EINVAL);
> [...



From davej at redhat.com  Wed Mar 14 12:44:54 2012
From: davej at redhat.com (Dave Jones)
Date: Wed, 14 Mar 2012 12:44:54 -0400
Subject: [GIT PULL] cpufreq: OMAP updates for v3.4
In-Reply-To: <CANOLnON91vXWb2L-FXjz3sqq-9j5SaEodtpt_yvFiN33D4Q3Ow@mail.gmail.com>
References: <87y5rci2na.fsf@ti.com>
 <CANOLnON91vXWb2L-FXjz3sqq-9j5SaEodtpt_yvFiN33D4Q3Ow@mail.gmail.com>
Message-ID: <20120314164454.GB2968@redhat.com>

On Wed, Mar 14, 2012 at 06:41:51PM +0200, Grazvydas Ignotas wrote:

 > > Afzal Mohammed (1):
 > > ? ? ?cpufreq: OMAP: specify range for voltage scaling
 > >
 > > Kevin Hilman (1):
 > > ? ? ?cpufreq: OMAP: scale voltage along with frequency
 > >
 > > Russell King (1):
 > > ? ? ?cpufreq: OMAP driver depends CPUfreq tables
 > 
 > It seems this one got messed up, it says "default ARCH_OMAP2PLUS"
 > instead of depends.
 > Can it be dropped and resent, or do we need a fixup patch?

Please send a follow-up patch if necessary.

	Dave



From sr at denx.de  Wed Mar 14 12:49:05 2012
From: sr at denx.de (Stefan Roese)
Date: Wed, 14 Mar 2012 17:49:05 +0100
Subject: [PATCH v2] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <20120314162152.GN18320@game.jcrosoft.org>
References: <1331737232-25477-1-git-send-email-sr@denx.de>
 <20120314162152.GN18320@game.jcrosoft.org>
Message-ID: <201203141749.05899.sr@denx.de>

On Wednesday 14 March 2012 17:21:52 Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 16:00 Wed 14 Mar     , Stefan Roese wrote:
> > This patch adds a generic target for SPEAr600 board that can be
> > configured via the device-tree. Currently the following devices
> > are supported via the devicetree:
> > 
> > - VIC interrupts
> > - PL011 UART
> > - PL061 GPIO
> > - Synopsys DW I2C
> > - Synopsys DW ethernet
> > 
> > Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
> > follow in later patches.
> > 
> > Only the spear600-evb is currently supported. Other SPEAr600
> > based boards will follow later.
> > 
> > Additionally the file spear600.c is deleted. It contained only
> > one empty function and is not needed. So lets just remove it.
> > 
> > Signed-off-by: Stefan Roese <sr at denx.de>
> > Cc: Viresh Kumar <viresh.kumar at st.com>
> > Cc: Arnd Bergmann <arnd at arndb.de>
> > ---
> > v2:
> > - Added DT support to spear6xx.c instead of creating board-dt.c
> > - Removed UART (PL011) and GPIO (PL061) platform data for
> > 
> >   devicetree board port. This works now via DT probing
> > 
> > - Added OF_DEV_AUXDATA for clock device name matching for some
> > 
> >   device drivers
> > 
> > - Removed sper600.c file completely
> > - Added DW I2C and ethernet nodes to the dts files
> > - Added other DT nodes (SMI, FSMC, ECHI, OHCI), currently disabled
> > 
> >   since the corresponding device drivers don't support DT probing
> > 
> > - Removed Linaro/FSL copyright notice from SPEAr DT files (copy-paste
> > cruft) - Many smaller modification to the dts/dtsi files
> > - Changed Documentation/devicetree/bindings/arm/spear.txt to match
> > 
> >   the changed bindings
> >  
> >  Documentation/devicetree/bindings/arm/spear.txt |    8 ++
> >  arch/arm/boot/dts/spear600-evb.dts              |   30 +++++
> >  arch/arm/boot/dts/spear600.dtsi                 |  162
> >  +++++++++++++++++++++++ arch/arm/mach-spear6xx/Kconfig                 
> >  |    7 +
> >  arch/arm/mach-spear6xx/Makefile                 |    3 -
> >  arch/arm/mach-spear6xx/spear600.c               |   25 ----
> >  arch/arm/mach-spear6xx/spear600_evb.c           |    3 -
> >  arch/arm/mach-spear6xx/spear6xx.c               |   69 +++++++++-
> >  8 files changed, 270 insertions(+), 37 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
> >  create mode 100644 arch/arm/boot/dts/spear600-evb.dts
> >  create mode 100644 arch/arm/boot/dts/spear600.dtsi
> >  delete mode 100644 arch/arm/mach-spear6xx/spear600.c
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/spear.txt
> > b/Documentation/devicetree/bindings/arm/spear.txt new file mode 100644
> > index 0000000..f8e54f0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/spear.txt
> > @@ -0,0 +1,8 @@
> > +ST SPEAr Platforms Device Tree Bindings
> > +---------------------------------------
> > +
> > +Boards with the ST SPEAr600 SoC shall have the following properties:
> > +
> > +Required root node property:
> > +
> > +compatible = "st,spear600";
> > diff --git a/arch/arm/boot/dts/spear600-evb.dts
> > b/arch/arm/boot/dts/spear600-evb.dts new file mode 100644
> > index 0000000..cbfda8d
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/spear600-evb.dts
> > @@ -0,0 +1,30 @@
> > +/*
> > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/dts-v1/;
> > +/include/ "spear600.dtsi"
> > +
> > +/ {
> > +	model = "ST SPEAr600 Evaluation Board";
> > +	compatible = "st,spear600-evb", "st,spear600";
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> 
> please put the mem size here

Might I ask why? Other *.dtsi files don't have it either.

> > +
> > +	soc {
> > +		gmac0: ethernet at e0800000 {
> > +			phy-mode = "gmii";
> > +		};
> > +
> > +		i2c at d0200000 {
> > +			clock-frequency = <400000>;
> > +		};
> > +	};
> > +};
> > diff --git a/arch/arm/boot/dts/spear600.dtsi
> > b/arch/arm/boot/dts/spear600.dtsi new file mode 100644
> > index 0000000..e45e58f
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/spear600.dtsi
> > @@ -0,0 +1,162 @@
> > +/*
> > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/include/ "skeleton.dtsi"
> > +
> > +/ {
> > +	compatible = "st,spear600";
> > +
> > +	cpus {
> > +		cpu at 0 {
> > +			compatible = "arm,arm926ejs";
> > +		};
> > +	};
> > +
> > +	memory {
> > +		device_type = "memory";
> > +		reg = <0 0>; /* Filled by U-Boot */
> 
> please put the max mem of the SoC here

Why? It's always updated by the bootloader. And a max. mem size (when not 
updated to the correct mem size by the bootloader) would crash the board if it 
is equipped with less memory.
 
> > +	};
> > +
> > +	soc {
> 
> please put the name of the bus not soc

Okay.

> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		compatible = "simple-bus";
> > +		ranges;
> > +
> > +		vic0: interrupt-controller at f1100000 {
> > +			compatible = "arm,pl190-vic";
> > +			interrupt-controller;
> > +			reg = <0xf1100000 0x1000>;
> > +			#interrupt-cells = <1>;
> > +		};
> > +
> > +		vic1: interrupt-controller at f1000000 {
> > +			compatible = "arm,pl190-vic";
> > +			interrupt-controller;
> > +			reg = <0xf1000000 0x1000>;
> > +			#interrupt-cells = <1>;
> > +		};
> > +
> > +		serial at d0000000 {
> > +			compatible = "arm,pl011", "arm,primecell";
> > +			reg = <0xd0000000 0x1000>;
> > +			interrupt-parent = <&vic0>;
> > +			interrupts = <24>;
> > +		};
> > +
> > +		serial at d0080000 {
> > +			compatible = "arm,pl011", "arm,primecell";
> > +			reg = <0xd0080000 0x1000>;
> > +			interrupt-parent = <&vic0>;
> > +			interrupts = <25>;
> > +		};
> > +
> > +		/* local/cpu GPIO */
> > +		gpio0: gpio at f0100000 {
> > +			#gpio-cells = <2>;
> > +			compatible = "arm,pl061", "arm,primecell";
> > +			gpio-controller;
> > +			reg = <0xf0100000 0x1000>;
> > +			interrupt-parent = <&vic0>;
> > +			interrupts = <18>;
> > +		};
> > +
> > +		/* basic GPIO */
> > +		gpio1: gpio at fc980000 {
> > +			#gpio-cells = <2>;
> > +			compatible = "arm,pl061", "arm,primecell";
> > +			gpio-controller;
> > +			reg = <0xfc980000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <19>;
> > +		};
> > +
> > +		/* appl GPIO */
> > +		gpio2: gpio at d8100000 {
> > +			#gpio-cells = <2>;
> > +			compatible = "arm,pl061", "arm,primecell";
> > +			gpio-controller;
> > +			reg = <0xd8100000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <4>;
> > +		};
> > +
> > +		gmac0: ethernet at e0800000 {
> > +			compatible = "st,spear600-gmac";
> > +			reg = <0xe0800000 0x8000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <24 23>;
> > +			interrupt-names = "macirq", "eth_wake_irq";
> > +			mac-address = [000000000000]; /* Filled in by U-Boot 
*/
> > +		};
> > +
> > +		i2c at d0200000 {
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			compatible = "snps,designware-i2c";
> > +			reg = <0xd0200000 0x1000>;
> > +			interrupt-parent = <&vic0>;
> > +			interrupts = <28>;
> > +		};
> > +
> > +		fsmc0: flash at d1800000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-fsmc-nand";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			reg = <0xd1800000 0x1000	/* FSMC Register */
> > +			       0xd2000000 0x4000>;	/* NAND Base */
> > +			reg-names = "fsmc_regs", "nand_data";
> > +		};
> > +
> > +		smi0: flash at fc000000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-smi";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			reg = <0xfc000000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <12>;
> > +		};
> > +
> > +		ehci at e1800000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-ehci", "usb-ehci";
> > +			reg = <0xe1800000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <27>;
> > +		};
> > +
> > +		ehci at e2000000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-ehci", "usb-ehci";
> > +			reg = <0xe2000000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <29>;
> > +		};
> > +
> > +		ohci at e1900000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-ohci", "usb-ohci";
> > +			reg = <0xe1900000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <26>;
> > +		};
> > +
> > +		ohci at e2100000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-ohci", "usb-ohci";
> > +			reg = <0xe2100000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <28>;
> > +		};
> 
> all of this need a Doc for the ST bindings

Sure. I only provided those nodes on Arnd's special request. They are 
currently disabled. And documentation will follow with the DT device driver 
patches.

> > +	};
> > +};
> > diff --git a/arch/arm/mach-spear6xx/Kconfig
> > b/arch/arm/mach-spear6xx/Kconfig index ff4ae5b..7777f72 100644
> > --- a/arch/arm/mach-spear6xx/Kconfig
> > +++ b/arch/arm/mach-spear6xx/Kconfig
> > @@ -11,6 +11,13 @@ config BOARD_SPEAR600_EVB
> > 
> >  	help
> >  	
> >  	  Supports ST SPEAr600 Evaluation Board
> > 
> > +config BOARD_SPEAR600_DT
> > +	bool "SPEAr600 generic board configured via device-tree"
> > +	select MACH_SPEAR600
> > +	select USE_OF
> > +	help
> > +	  Supports ST SPEAr600 boards configured via the device-tree
> > +
> > 
> >  endmenu
> >  
> >  config MACH_SPEAR600
> > 
> > diff --git a/arch/arm/mach-spear6xx/Makefile
> > b/arch/arm/mach-spear6xx/Makefile index cc1a4d8..6f87c3a 100644
> > --- a/arch/arm/mach-spear6xx/Makefile
> > +++ b/arch/arm/mach-spear6xx/Makefile
> > @@ -5,8 +5,5 @@
> > 
> >  # common files
> >  obj-y	+= clock.o spear6xx.o
> > 
> > -# spear600 specific files
> > -obj-$(CONFIG_MACH_SPEAR600) += spear600.o
> > -
> > 
> >  # spear600 boards files
> >  obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
> > 
> > diff --git a/arch/arm/mach-spear6xx/spear600.c
> > b/arch/arm/mach-spear6xx/spear600.c deleted file mode 100644
> > index d0e6eea..0000000
> > --- a/arch/arm/mach-spear6xx/spear600.c
> > +++ /dev/null
> > @@ -1,25 +0,0 @@
> > -/*
> > - * arch/arm/mach-spear6xx/spear600.c
> > - *
> > - * SPEAr600 machine source file
> > - *
> > - * Copyright (C) 2009 ST Microelectronics
> > - * Rajeev Kumar<rajeev-dlh.kumar at st.com>
> > - *
> > - * This file is licensed under the terms of the GNU General Public
> > - * License version 2. This program is licensed "as is" without any
> > - * warranty of any kind, whether express or implied.
> > - */
> > -
> > -#include <linux/ptrace.h>
> > -#include <asm/irq.h>
> > -#include <mach/generic.h>
> > -#include <mach/hardware.h>
> > -
> > -/* Add spear600 specific devices here */
> > -
> > -void __init spear600_init(void)
> > -{
> > -	/* call spear6xx family common init function */
> > -	spear6xx_init();
> > -}
> > diff --git a/arch/arm/mach-spear6xx/spear600_evb.c
> > b/arch/arm/mach-spear6xx/spear600_evb.c index c6e4254..c4949aa 100644
> > --- a/arch/arm/mach-spear6xx/spear600_evb.c
> > +++ b/arch/arm/mach-spear6xx/spear600_evb.c
> > @@ -32,9 +32,6 @@ static void __init spear600_evb_init(void)
> > 
> >  {
> >  
> >  	unsigned int i;
> > 
> > -	/* call spear600 machine init function */
> > -	spear600_init();
> > -
> > 
> >  	/* Add Platform Devices */
> >  	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
> > 
> > diff --git a/arch/arm/mach-spear6xx/spear6xx.c
> > b/arch/arm/mach-spear6xx/spear6xx.c index e0f6628..aca20f0 100644
> > --- a/arch/arm/mach-spear6xx/spear6xx.c
> > +++ b/arch/arm/mach-spear6xx/spear6xx.c
> > @@ -6,6 +6,8 @@
> > 
> >   * Copyright (C) 2009 ST Microelectronics
> >   * Rajeev Kumar<rajeev-dlh.kumar at st.com>
> >   *
> > 
> > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > + *
> > 
> >   * This file is licensed under the terms of the GNU General Public
> >   * License version 2. This program is licensed "as is" without any
> >   * warranty of any kind, whether express or implied.
> > 
> > @@ -15,6 +17,10 @@
> > 
> >  #include <linux/amba/pl061.h>
> >  #include <linux/ptrace.h>
> >  #include <linux/io.h>
> > 
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_platform.h>
> > 
> >  #include <asm/hardware/vic.h>
> >  #include <asm/irq.h>
> >  #include <asm/mach/arch.h>
> > 
> > @@ -99,12 +105,6 @@ struct amba_device gpio_device[] = {
> > 
> >  	}
> >  
> >  };
> > 
> > -/* This will add devices, and do machine specific tasks */
> > -void __init spear6xx_init(void)
> > -{
> > -	/* nothing to do for now */
> > -}
> > -
> > 
> >  /* This will initialize vic */
> >  void __init spear6xx_init_irq(void)
> >  {
> > 
> > @@ -181,3 +181,60 @@ static void __init spear6xx_timer_init(void)
> > 
> >  struct sys_timer spear6xx_timer = {
> >  
> >  	.init = spear6xx_timer_init,
> >  
> >  };
> > 
> > +
> > +/*
> > + * Devicetree specific init structs/functions:
> > + * Once the SPEAr600 devicetree support has matured, we can remove
> > + * spear600_evb.c and the non-devicetree support above in this file.
> > + */
> > +
> > +/*
> > + * Add auxdata so that clock name matching doesn't fail in device
> > + * drivers
> > + */
> > +struct of_dev_auxdata spear600_auxdata_lookup[] __initdata = {
> > +	OF_DEV_AUXDATA("arm,pl011", SPEAR6XX_ICM1_UART0_BASE,
> > +		       "uart0", NULL),
> > +	OF_DEV_AUXDATA("arm,pl011", SPEAR6XX_ICM1_UART1_BASE,
> > +		       "uart1", NULL),
> > +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_CPU_GPIO_BASE,
> > +		       "gpio0", NULL),
> > +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_ICM3_GPIO_BASE,
> > +		       "gpio1", NULL),
> > +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_ICM2_GPIO_BASE,
> > +		       "gpio2", NULL),
> > +	OF_DEV_AUXDATA("snps,designware-i2c", SPEAR6XX_ICM1_I2C_BASE,
> > +		       "i2c_designware.0", NULL),
> 
> update the clkdev no more OF_DEV_AUXDATA

That will break non-DT boards. We can change it in clkdev later, once DT 
support has stabalized for SPEAr600. And remove all this then.
 
> 
> please keep me in Cc

Sure.

Cheers,
Stefan


From arnd at arndb.de  Wed Mar 14 12:58:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 16:58:07 +0000
Subject: [GIT PULL 1/7] non-critical fixes part3 for upcoming merge window
In-Reply-To: <20120314163547.GO12083@atomide.com>
References: <4f591c4d.e471340a.1f3f.3a69SMTPIN_ADDED@mx.google.com>
 <20120310182425.GA698@quad.lixom.net> <20120314163547.GO12083@atomide.com>
Message-ID: <201203141658.08234.arnd@arndb.de>

On Wednesday 14 March 2012, Tony Lindgren wrote:
> * Olof Johansson <olof at lixom.net> [120310 10:26]:
> > On Thu, Mar 08, 2012 at 12:53:29PM -0800, Tony Lindgren wrote:
> > > Hi Olof,
> > > 
> > > Here are two more pre-emptive fixes for upcoming merge
> > > window to pull into arm-soc/next/fixes-non-critical.
> > > 
> > > Now with the fixes finallny out of the way after all
> > > the cleanup related changes, as a reply to this pull
> > > request I'm posting some more pull requests for cleanup
> > > and some minor board changes.
> > 
> > Pulled request 1-7.
> 
> Now with another -rc, can you please pull in also
> 2 - 7 in this series?

Hi Tony,

I'm pretty sure that Olof pulled all the branches the first time
around, i.e. 1-7, not just 1/7. Please check the for-next
branch and tell us if there is anything still missing.

	Arnd


From arnd at arndb.de  Wed Mar 14 13:00:06 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 17:00:06 +0000
Subject: [PATCH v4 00/11] ep93xx: Move SoC private bits to core
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F0020695AB9B9B@AUSP01VMBX24.collaborationhost.net>
References: <1331592502-9083-1-git-send-email-rmallon@gmail.com>
 <201203141351.06200.arnd@arndb.de>
 <ADE657CA350FB648AAC2C43247A983F0020695AB9B9B@AUSP01VMBX24.collaborationhost.net>
Message-ID: <201203141700.06226.arnd@arndb.de>

On Wednesday 14 March 2012, H Hartley Sweeten wrote:
> On Wednesday, March 14, 2012 6:51 AM, Arnd Bergmann wrote:

> > As the first steps (after reading Documentation/devicetree/booting-without-of.txt)
> > the best way forward is probably to take you favourite board file and
> > add a DT_MACHINE_START section so you can boot the same machine
> > when passing an empty devicetree rather than ATAGS. Then add the interrupt
> > controller (should be simple for VIC), followed by gpio (needs bindings,
> > see Documentation/devicetree/bindings/gpio/*.txt), i2c and spi. After
> > you have all that infrastructure in place, you can convert every other
> > device, one at a time. Some (anything without platform_data) will be
> > Trivial, others require you to come up with a new binding document
> > and properties to replace the platform_data. Many people try to do
> > the ones from board files first because it lets them remove the board
> > files, and only after that look at converting the core devices, but you
> > can do any order you like.
> 
> The main problem I see with converting the ep93xx platform to device tree
> is that it requires modifying the bootloader. Correct me if I am wrong.

You can always use legacy bootloaders with an appended device tree.
It's slightly less interesting that way but it still works. You can
also use a second-stage boot loader, but that would require having
one that supports your platform.

	Arnd


From khilman at ti.com  Wed Mar 14 13:22:38 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 14 Mar 2012 10:22:38 -0700
Subject: [GIT PULL] cpufreq: OMAP updates for v3.4
In-Reply-To: <CANOLnON91vXWb2L-FXjz3sqq-9j5SaEodtpt_yvFiN33D4Q3Ow@mail.gmail.com>
 (Grazvydas Ignotas's message of "Wed, 14 Mar 2012 18:41:51 +0200")
References: <87y5rci2na.fsf@ti.com>
 <CANOLnON91vXWb2L-FXjz3sqq-9j5SaEodtpt_yvFiN33D4Q3Ow@mail.gmail.com>
Message-ID: <87wr6ngkrl.fsf@ti.com>

Grazvydas Ignotas <notasas at gmail.com> writes:

[...]

>> Russell King (1):
>> ? ? ?cpufreq: OMAP driver depends CPUfreq tables
>
> It seems this one got messed up, it says "default ARCH_OMAP2PLUS"
> instead of depends.

That was intentional.  What do you think is messed up about it?

It's the same as saying:

     depends on ARCH_OMAP2PLUS
     default y

Kevin



From tony at atomide.com  Wed Mar 14 13:26:01 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 14 Mar 2012 10:26:01 -0700
Subject: [GIT PULL 1/7] non-critical fixes part3 for upcoming merge window
In-Reply-To: <201203141658.08234.arnd@arndb.de>
References: <4f591c4d.e471340a.1f3f.3a69SMTPIN_ADDED@mx.google.com>
 <20120310182425.GA698@quad.lixom.net>
 <20120314163547.GO12083@atomide.com>
 <201203141658.08234.arnd@arndb.de>
Message-ID: <20120314172600.GP12083@atomide.com>

* Arnd Bergmann <arnd at arndb.de> [120314 10:00]:
> On Wednesday 14 March 2012, Tony Lindgren wrote:
> > * Olof Johansson <olof at lixom.net> [120310 10:26]:
> > > On Thu, Mar 08, 2012 at 12:53:29PM -0800, Tony Lindgren wrote:
> > > > Hi Olof,
> > > > 
> > > > Here are two more pre-emptive fixes for upcoming merge
> > > > window to pull into arm-soc/next/fixes-non-critical.
> > > > 
> > > > Now with the fixes finallny out of the way after all
> > > > the cleanup related changes, as a reply to this pull
> > > > request I'm posting some more pull requests for cleanup
> > > > and some minor board changes.
> > > 
> > > Pulled request 1-7.
> > 
> > Now with another -rc, can you please pull in also
> > 2 - 7 in this series?
> 
> Hi Tony,
> 
> I'm pretty sure that Olof pulled all the branches the first time
> around, i.e. 1-7, not just 1/7. Please check the for-next
> branch and tell us if there is anything still missing.

Indeed, all seven are there! Thanks,

Tony


From olof at lixom.net  Wed Mar 14 13:27:38 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 14 Mar 2012 10:27:38 -0700
Subject: [PATCH V2 2/3] pinctrl: allow concurrent gpio and mux function
 ownership of pins
In-Reply-To: <4F5E3F63.5080506@wwwdotorg.org>
References: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
 <1330993336-9538-2-git-send-email-swarren@nvidia.com>
 <CACRpkdYdSaNsrr34o2Cc4vS12ee9oY7FG0pxB92mefHZKwdEpA@mail.gmail.com>
 <4F5E3F63.5080506@wwwdotorg.org>
Message-ID: <20120314172738.GA14853@quad.lixom.net>

On Mon, Mar 12, 2012 at 12:24:35PM -0600, Stephen Warren wrote:
> On 03/06/2012 03:03 AM, Linus Walleij wrote:
> > On Tue, Mar 6, 2012 at 1:22 AM, Stephen Warren <swarren at nvidia.com> wrote:
> > 
> >> Per recent updates to Documentation/gpio.txt, gpiolib drivers should
> >> inform pinctrl when a GPIO is requested. pinctrl then marks that pin as
> >> in-use for that GPIO function.
> >>
> >> When an SoC muxes pins in a group, it's quite possible for the group to
> >> contain e.g. 6 pins, but only 4 of them actually be needed by the HW
> >> module that's mux'd to them. In this case, the other 2 pins could be
> >> used as GPIOs. However, pinctrl marks all the pins within the group as
> >> in-use by the selected mux function. To allow the expected gpiolib
> >> interaction, separate the concepts of pin ownership into two parts: One
> >> for the mux function and one for GPIO usage. Finally, allow those two
> >> ownerships to exist in parallel.
> >>
> >> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> > 
> > Good, and 100% in accordance with earlier discussions.
> > Acked-by: Linus Walleij <linus.walleij at linaro.org>
> 
> Linus, now that Grant has ack'd and applied the documentation change
> behind this, could you take this one patch into the pinctrl tree. I
> assume it's 3.5 material. After the 3.4 merge window closes, I'll
> probably come back and ask for a stable pinctrl branch that I can use as
> the basis for a Tegra branch that'll contain patch 3 in this series.
> 
> (Olof, I assume that's the right way to approach this; having Linus
> apply both patches 2/3 in this series to pinctrl is going to make life
> difficult in the Tegra tree, since my outstanding patches to convert
> Tegra to use pinctrl will touch many of the same files as patch 3 in
> this series, in conflicting or dependent ways.)

Yes, that seems like a good way to handle it.


-Olof


From olof at lixom.net  Wed Mar 14 13:29:00 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 14 Mar 2012 10:29:00 -0700
Subject: [PATCH V2 2/3] pinctrl: allow concurrent gpio and mux function
 ownership of pins
In-Reply-To: <CACRpkdYsD2LCNoox6ztHTP76X8a_qxjiZFO4ou=BgZ4oE0qHtg@mail.gmail.com>
References: <1330993336-9538-1-git-send-email-swarren@nvidia.com>
 <1330993336-9538-2-git-send-email-swarren@nvidia.com>
 <CACRpkdYdSaNsrr34o2Cc4vS12ee9oY7FG0pxB92mefHZKwdEpA@mail.gmail.com>
 <4F5E3F63.5080506@wwwdotorg.org>
 <CACRpkdYsD2LCNoox6ztHTP76X8a_qxjiZFO4ou=BgZ4oE0qHtg@mail.gmail.com>
Message-ID: <20120314172900.GB14853@quad.lixom.net>

On Mon, Mar 12, 2012 at 10:42:48PM +0100, Linus Walleij wrote:
> On Mon, Mar 12, 2012 at 7:24 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> 
> > Linus, now that Grant has ack'd and applied the documentation change
> > behind this, could you take this one patch into the pinctrl tree.
> 
> Of course, applied.
> 
> > I assume it's 3.5 material.
> 
> No it goes in now, we can't have documentation that is misleading...
> Besides, I like it.

Oops, this reply didn't show before I hit reply on the other one.

Stephen, that makes things easy for you if you still need time to sort things
out on the tegra side, since 3.4-rc1 can be the base for that work.


-Olof


From kgene.kim at samsung.com  Wed Mar 14 13:29:57 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 10:29:57 -0700
Subject: [PATCH v2 RE-SEND] [CPUFREQ] EXYNOS4X12: Add support cpufreq
 for EXYNOS4X12
In-Reply-To: <1331377162-25134-1-git-send-email-kgene.kim@samsung.com>
References: <1331377162-25134-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <4F60D595.5090208@samsung.com>

Kukjin Kim wrote:
> From: Jaecheol Lee<jc.lee at samsung.com>
> 
> This patch adds support cpufreq for EXYNOS4X12 SoCs. Basically,
> the exynos-cpufreq.c is used commonly and exynos4x12-cpufreq.c
> is used for EXYNOS4212(two Cortex-A9 cores) and EXYNOS4412(four
> Cortex-A9 cores) SoCs.
> 
> Signed-off-by: Jaecheol Lee<jc.lee at samsung.com>
> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>


Hi Dave,

If you're ok on this, please pick up for upcoming merge window.
If any problems, please kindly let us know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


> ---
> Changes since v1:
> Address comments from Sylwester
> 
>   arch/arm/mach-exynos/include/mach/cpufreq.h |    1 +
>   drivers/cpufreq/Kconfig.arm                 |    7 +
>   drivers/cpufreq/Makefile                    |    1 +
>   drivers/cpufreq/exynos-cpufreq.c            |    2 +
>   drivers/cpufreq/exynos4x12-cpufreq.c        |  536 +++++++++++++++++++++++++++
>   5 files changed, 547 insertions(+), 0 deletions(-)
>   create mode 100644 drivers/cpufreq/exynos4x12-cpufreq.c
> 
> diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
> index 3df27f2..96ac0cb 100644
> --- a/arch/arm/mach-exynos/include/mach/cpufreq.h
> +++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
> @@ -32,3 +32,4 @@ struct exynos_dvfs_info {
>   };
> 
>   extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
> +extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index dc59abf..9b99a96 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -47,6 +47,7 @@ config ARM_EXYNOS_CPUFREQ
>   	bool "SAMSUNG EXYNOS SoCs"
>   	depends on ARCH_EXYNOS
>   	select ARM_EXYNOS4210_CPUFREQ if CPU_EXYNOS4210
> +	select ARM_EXYNOS4X12_CPUFREQ if (SOC_EXYNOS4212 || SOC_EXYNOS4412)
>   	default y
>   	help
>   	  This adds the CPUFreq driver common part for Samsung
> @@ -60,3 +61,9 @@ config ARM_EXYNOS4210_CPUFREQ
>   	help
>   	  This adds the CPUFreq driver for Samsung EXYNOS4210
>   	  SoC (S5PV310 or S5PC210).
> +
> +config ARM_EXYNOS4X12_CPUFREQ
> +	bool "Samsung EXYNOS4X12"
> +	help
> +	  This adds the CPUFreq driver for Samsung EXYNOS4X12
> +	  SoC (EXYNOS4212 or EXYNOS4412).
> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> index 042fbae..f37bbcc 100644
> --- a/drivers/cpufreq/Makefile
> +++ b/drivers/cpufreq/Makefile
> @@ -45,6 +45,7 @@ obj-$(CONFIG_ARM_S3C64XX_CPUFREQ)	+= s3c64xx-cpufreq.o
>   obj-$(CONFIG_ARM_S5PV210_CPUFREQ)	+= s5pv210-cpufreq.o
>   obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
>   obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
> +obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)	+= exynos4x12-cpufreq.o
>   obj-$(CONFIG_ARCH_OMAP2PLUS)            += omap-cpufreq.o
> 
>   ##################################################################################
> diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
> index 7cfb516..2c63b68 100644
> --- a/drivers/cpufreq/exynos-cpufreq.c
> +++ b/drivers/cpufreq/exynos-cpufreq.c
> @@ -254,6 +254,8 @@ static int __init exynos_cpufreq_init(void)
> 
>   	if (soc_is_exynos4210())
>   		ret = exynos4210_cpufreq_init(exynos_info);
> +	else if (soc_is_exynos4212() || soc_is_exynos4412())
> +		ret = exynos4x12_cpufreq_init(exynos_info);
>   	else
>   		pr_err("%s: CPU type not found\n", __func__);
> 
> diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
> new file mode 100644
> index 0000000..8c5a7af
> --- /dev/null
> +++ b/drivers/cpufreq/exynos4x12-cpufreq.c
> @@ -0,0 +1,536 @@
> +/*
> + * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * EXYNOS4X12 - CPU frequency scaling support
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include<linux/module.h>
> +#include<linux/kernel.h>
> +#include<linux/err.h>
> +#include<linux/clk.h>
> +#include<linux/io.h>
> +#include<linux/slab.h>
> +#include<linux/cpufreq.h>
> +
> +#include<mach/regs-clock.h>
> +#include<mach/cpufreq.h>
> +
> +#define CPUFREQ_LEVEL_END	(L13 + 1)
> +
> +static int max_support_idx;
> +static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
> +
> +static struct clk *cpu_clk;
> +static struct clk *moutcore;
> +static struct clk *mout_mpll;
> +static struct clk *mout_apll;
> +
> +struct cpufreq_clkdiv {
> +	unsigned int	index;
> +	unsigned int	clkdiv;
> +	unsigned int	clkdiv1;
> +};
> +
> +static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END];
> +
> +static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
> +	{L0, 1500 * 1000},
> +	{L1, 1400 * 1000},
> +	{L2, 1300 * 1000},
> +	{L3, 1200 * 1000},
> +	{L4, 1100 * 1000},
> +	{L5, 1000 * 1000},
> +	{L6,  900 * 1000},
> +	{L7,  800 * 1000},
> +	{L8,  700 * 1000},
> +	{L9,  600 * 1000},
> +	{L10, 500 * 1000},
> +	{L11, 400 * 1000},
> +	{L12, 300 * 1000},
> +	{L13, 200 * 1000},
> +	{0, CPUFREQ_TABLE_END},
> +};
> +
> +static struct cpufreq_clkdiv exynos4x12_clkdiv_table[CPUFREQ_LEVEL_END];
> +
> +static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = {
> +	/*
> +	 * Clock divider value for following
> +	 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
> +	 *		DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
> +	 */
> +	/* ARM L0: 1500 MHz */
> +	{ 0, 3, 7, 0, 6, 1, 2, 0 },
> +
> +	/* ARM L1: 1400 MHz */
> +	{ 0, 3, 7, 0, 6, 1, 2, 0 },
> +
> +	/* ARM L2: 1300 MHz */
> +	{ 0, 3, 7, 0, 5, 1, 2, 0 },
> +
> +	/* ARM L3: 1200 MHz */
> +	{ 0, 3, 7, 0, 5, 1, 2, 0 },
> +
> +	/* ARM L4: 1100 MHz */
> +	{ 0, 3, 6, 0, 4, 1, 2, 0 },
> +
> +	/* ARM L5: 1000 MHz */
> +	{ 0, 2, 5, 0, 4, 1, 1, 0 },
> +
> +	/* ARM L6: 900 MHz */
> +	{ 0, 2, 5, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L7: 800 MHz */
> +	{ 0, 2, 5, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L8: 700 MHz */
> +	{ 0, 2, 4, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L9: 600 MHz */
> +	{ 0, 2, 4, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L10: 500 MHz */
> +	{ 0, 2, 4, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L11: 400 MHz */
> +	{ 0, 2, 4, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L12: 300 MHz */
> +	{ 0, 2, 4, 0, 2, 1, 1, 0 },
> +
> +	/* ARM L13: 200 MHz */
> +	{ 0, 1, 3, 0, 1, 1, 1, 0 },
> +};
> +
> +static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = {
> +	/*
> +	 * Clock divider value for following
> +	 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
> +	 *		DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
> +	 */
> +	/* ARM L0: 1500 MHz */
> +	{ 0, 3, 7, 0, 6, 1, 2, 0 },
> +
> +	/* ARM L1: 1400 MHz */
> +	{ 0, 3, 7, 0, 6, 1, 2, 0 },
> +
> +	/* ARM L2: 1300 MHz */
> +	{ 0, 3, 7, 0, 5, 1, 2, 0 },
> +
> +	/* ARM L3: 1200 MHz */
> +	{ 0, 3, 7, 0, 5, 1, 2, 0 },
> +
> +	/* ARM L4: 1100 MHz */
> +	{ 0, 3, 6, 0, 4, 1, 2, 0 },
> +
> +	/* ARM L5: 1000 MHz */
> +	{ 0, 2, 5, 0, 4, 1, 1, 0 },
> +
> +	/* ARM L6: 900 MHz */
> +	{ 0, 2, 5, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L7: 800 MHz */
> +	{ 0, 2, 5, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L8: 700 MHz */
> +	{ 0, 2, 4, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L9: 600 MHz */
> +	{ 0, 2, 4, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L10: 500 MHz */
> +	{ 0, 2, 4, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L11: 400 MHz */
> +	{ 0, 2, 4, 0, 3, 1, 1, 0 },
> +
> +	/* ARM L12: 300 MHz */
> +	{ 0, 2, 4, 0, 2, 1, 1, 0 },
> +
> +	/* ARM L13: 200 MHz */
> +	{ 0, 1, 3, 0, 1, 1, 1, 0 },
> +};
> +
> +static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = {
> +	/* Clock divider value for following
> +	 * { DIVCOPY, DIVHPM }
> +	 */
> +	/* ARM L0: 1500 MHz */
> +	{ 6, 0 },
> +
> +	/* ARM L1: 1400 MHz */
> +	{ 6, 0 },
> +
> +	/* ARM L2: 1300 MHz */
> +	{ 5, 0 },
> +
> +	/* ARM L3: 1200 MHz */
> +	{ 5, 0 },
> +
> +	/* ARM L4: 1100 MHz */
> +	{ 4, 0 },
> +
> +	/* ARM L5: 1000 MHz */
> +	{ 4, 0 },
> +
> +	/* ARM L6: 900 MHz */
> +	{ 3, 0 },
> +
> +	/* ARM L7: 800 MHz */
> +	{ 3, 0 },
> +
> +	/* ARM L8: 700 MHz */
> +	{ 3, 0 },
> +
> +	/* ARM L9: 600 MHz */
> +	{ 3, 0 },
> +
> +	/* ARM L10: 500 MHz */
> +	{ 3, 0 },
> +
> +	/* ARM L11: 400 MHz */
> +	{ 3, 0 },
> +
> +	/* ARM L12: 300 MHz */
> +	{ 3, 0 },
> +
> +	/* ARM L13: 200 MHz */
> +	{ 3, 0 },
> +};
> +
> +static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = {
> +	/* Clock divider value for following
> +	 * { DIVCOPY, DIVHPM, DIVCORES }
> +	 */
> +	/* ARM L0: 1500 MHz */
> +	{ 6, 0, 7 },
> +
> +	/* ARM L1: 1400 MHz */
> +	{ 6, 0, 6 },
> +
> +	/* ARM L2: 1300 MHz */
> +	{ 5, 0, 6 },
> +
> +	/* ARM L3: 1200 MHz */
> +	{ 5, 0, 5 },
> +
> +	/* ARM L4: 1100 MHz */
> +	{ 4, 0, 5 },
> +
> +	/* ARM L5: 1000 MHz */
> +	{ 4, 0, 4 },
> +
> +	/* ARM L6: 900 MHz */
> +	{ 3, 0, 4 },
> +
> +	/* ARM L7: 800 MHz */
> +	{ 3, 0, 3 },
> +
> +	/* ARM L8: 700 MHz */
> +	{ 3, 0, 3 },
> +
> +	/* ARM L9: 600 MHz */
> +	{ 3, 0, 2 },
> +
> +	/* ARM L10: 500 MHz */
> +	{ 3, 0, 2 },
> +
> +	/* ARM L11: 400 MHz */
> +	{ 3, 0, 1 },
> +
> +	/* ARM L12: 300 MHz */
> +	{ 3, 0, 1 },
> +
> +	/* ARM L13: 200 MHz */
> +	{ 3, 0, 0 },
> +};
> +
> +static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {
> +	/* APLL FOUT L0: 1500 MHz */
> +	((250<<  16) | (4<<  8) | (0x0)),
> +
> +	/* APLL FOUT L1: 1400 MHz */
> +	((175<<  16) | (3<<  8) | (0x0)),
> +
> +	/* APLL FOUT L2: 1300 MHz */
> +	((325<<  16) | (6<<  8) | (0x0)),
> +
> +	/* APLL FOUT L3: 1200 MHz */
> +	((200<<  16) | (4<<  8) | (0x0)),
> +
> +	/* APLL FOUT L4: 1100 MHz */
> +	((275<<  16) | (6<<  8) | (0x0)),
> +
> +	/* APLL FOUT L5: 1000 MHz */
> +	((125<<  16) | (3<<  8) | (0x0)),
> +
> +	/* APLL FOUT L6: 900 MHz */
> +	((150<<  16) | (4<<  8) | (0x0)),
> +
> +	/* APLL FOUT L7: 800 MHz */
> +	((100<<  16) | (3<<  8) | (0x0)),
> +
> +	/* APLL FOUT L8: 700 MHz */
> +	((175<<  16) | (3<<  8) | (0x1)),
> +
> +	/* APLL FOUT L9: 600 MHz */
> +	((200<<  16) | (4<<  8) | (0x1)),
> +
> +	/* APLL FOUT L10: 500 MHz */
> +	((125<<  16) | (3<<  8) | (0x1)),
> +
> +	/* APLL FOUT L11 400 MHz */
> +	((100<<  16) | (3<<  8) | (0x1)),
> +
> +	/* APLL FOUT L12: 300 MHz */
> +	((200<<  16) | (4<<  8) | (0x2)),
> +
> +	/* APLL FOUT L13: 200 MHz */
> +	((100<<  16) | (3<<  8) | (0x2)),
> +};
> +
> +static const unsigned int asv_voltage_4x12[CPUFREQ_LEVEL_END] = {
> +	1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
> +	1000000,  987500,  975000,  950000,  925000,  900000,  900000
> +};
> +
> +static void exynos4x12_set_clkdiv(unsigned int div_index)
> +{
> +	unsigned int tmp;
> +	unsigned int stat_cpu1;
> +
> +	/* Change Divider - CPU0 */
> +
> +	tmp = exynos4x12_clkdiv_table[div_index].clkdiv;
> +
> +	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
> +
> +	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU)&  0x11111111)
> +		cpu_relax();
> +
> +	/* Change Divider - CPU1 */
> +	tmp = exynos4x12_clkdiv_table[div_index].clkdiv1;
> +
> +	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
> +	if (soc_is_exynos4212())
> +		stat_cpu1 = 0x11;
> +	else
> +		stat_cpu1 = 0x111;
> +
> +	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1)&  stat_cpu1)
> +		cpu_relax();
> +}
> +
> +static void exynos4x12_set_apll(unsigned int index)
> +{
> +	unsigned int tmp, pdiv;
> +
> +	/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
> +	clk_set_parent(moutcore, mout_mpll);
> +
> +	do {
> +		cpu_relax();
> +		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
> +			>>  EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
> +		tmp&= 0x7;
> +	} while (tmp != 0x2);
> +
> +	/* 2. Set APLL Lock time */
> +	pdiv = ((exynos4x12_apll_pms_table[index]>>  8)&  0x3f);
> +
> +	__raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK);
> +
> +	/* 3. Change PLL PMS values */
> +	tmp = __raw_readl(EXYNOS4_APLL_CON0);
> +	tmp&= ~((0x3ff<<  16) | (0x3f<<  8) | (0x7<<  0));
> +	tmp |= exynos4x12_apll_pms_table[index];
> +	__raw_writel(tmp, EXYNOS4_APLL_CON0);
> +
> +	/* 4. wait_lock_time */
> +	do {
> +		cpu_relax();
> +		tmp = __raw_readl(EXYNOS4_APLL_CON0);
> +	} while (!(tmp&  (0x1<<  EXYNOS4_APLLCON0_LOCKED_SHIFT)));
> +
> +	/* 5. MUX_CORE_SEL = APLL */
> +	clk_set_parent(moutcore, mout_apll);
> +
> +	do {
> +		cpu_relax();
> +		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
> +		tmp&= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
> +	} while (tmp != (0x1<<  EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
> +}
> +
> +bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index)
> +{
> +	unsigned int old_pm = exynos4x12_apll_pms_table[old_index]>>  8;
> +	unsigned int new_pm = exynos4x12_apll_pms_table[new_index]>>  8;
> +
> +	return (old_pm == new_pm) ? 0 : 1;
> +}
> +
> +static void exynos4x12_set_frequency(unsigned int old_index,
> +				  unsigned int new_index)
> +{
> +	unsigned int tmp;
> +
> +	if (old_index>  new_index) {
> +		if (!exynos4x12_pms_change(old_index, new_index)) {
> +			/* 1. Change the system clock divider values */
> +			exynos4x12_set_clkdiv(new_index);
> +			/* 2. Change just s value in apll m,p,s value */
> +			tmp = __raw_readl(EXYNOS4_APLL_CON0);
> +			tmp&= ~(0x7<<  0);
> +			tmp |= (exynos4x12_apll_pms_table[new_index]&  0x7);
> +			__raw_writel(tmp, EXYNOS4_APLL_CON0);
> +
> +		} else {
> +			/* Clock Configuration Procedure */
> +			/* 1. Change the system clock divider values */
> +			exynos4x12_set_clkdiv(new_index);
> +			/* 2. Change the apll m,p,s value */
> +			exynos4x12_set_apll(new_index);
> +		}
> +	} else if (old_index<  new_index) {
> +		if (!exynos4x12_pms_change(old_index, new_index)) {
> +			/* 1. Change just s value in apll m,p,s value */
> +			tmp = __raw_readl(EXYNOS4_APLL_CON0);
> +			tmp&= ~(0x7<<  0);
> +			tmp |= (exynos4x12_apll_pms_table[new_index]&  0x7);
> +			__raw_writel(tmp, EXYNOS4_APLL_CON0);
> +			/* 2. Change the system clock divider values */
> +			exynos4x12_set_clkdiv(new_index);
> +		} else {
> +			/* Clock Configuration Procedure */
> +			/* 1. Change the apll m,p,s value */
> +			exynos4x12_set_apll(new_index);
> +			/* 2. Change the system clock divider values */
> +			exynos4x12_set_clkdiv(new_index);
> +		}
> +	}
> +}
> +
> +static void __init set_volt_table(void)
> +{
> +	unsigned int i;
> +
> +	max_support_idx = L1;
> +
> +	/* Not supported */
> +	exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
> +
> +	for (i = 0 ; i<  CPUFREQ_LEVEL_END ; i++)
> +		exynos4x12_volt_table[i] = asv_voltage_4x12[i];
> +}
> +
> +int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
> +{
> +	int i;
> +	unsigned int tmp;
> +	unsigned long rate;
> +
> +	set_volt_table();
> +
> +	cpu_clk = clk_get(NULL, "armclk");
> +	if (IS_ERR(cpu_clk))
> +		return PTR_ERR(cpu_clk);
> +
> +	moutcore = clk_get(NULL, "moutcore");
> +	if (IS_ERR(moutcore))
> +		goto err_moutcore;
> +
> +	mout_mpll = clk_get(NULL, "mout_mpll");
> +	if (IS_ERR(mout_mpll))
> +		goto err_mout_mpll;
> +
> +	rate = clk_get_rate(mout_mpll) / 1000;
> +
> +	mout_apll = clk_get(NULL, "mout_apll");
> +	if (IS_ERR(mout_apll))
> +		goto err_mout_apll;
> +
> +	for (i = L0; i<   CPUFREQ_LEVEL_END; i++) {
> +
> +		exynos4x12_clkdiv_table[i].index = i;
> +
> +		tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
> +
> +		tmp&= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
> +			EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
> +			EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
> +			EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
> +			EXYNOS4_CLKDIV_CPU0_ATB_MASK |
> +			EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
> +			EXYNOS4_CLKDIV_CPU0_APLL_MASK);
> +
> +		if (soc_is_exynos4212()) {
> +			tmp |= ((clkdiv_cpu0_4212[i][0]<<  EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
> +				(clkdiv_cpu0_4212[i][1]<<  EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
> +				(clkdiv_cpu0_4212[i][2]<<  EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
> +				(clkdiv_cpu0_4212[i][3]<<  EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
> +				(clkdiv_cpu0_4212[i][4]<<  EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
> +				(clkdiv_cpu0_4212[i][5]<<  EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
> +				(clkdiv_cpu0_4212[i][6]<<  EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
> +		} else {
> +			tmp&= ~EXYNOS4_CLKDIV_CPU0_CORE2_MASK;
> +
> +			tmp |= ((clkdiv_cpu0_4412[i][0]<<  EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
> +				(clkdiv_cpu0_4412[i][1]<<  EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
> +				(clkdiv_cpu0_4412[i][2]<<  EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
> +				(clkdiv_cpu0_4412[i][3]<<  EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
> +				(clkdiv_cpu0_4412[i][4]<<  EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
> +				(clkdiv_cpu0_4412[i][5]<<  EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
> +				(clkdiv_cpu0_4412[i][6]<<  EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
> +				(clkdiv_cpu0_4412[i][7]<<  EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT));
> +		}
> +
> +		exynos4x12_clkdiv_table[i].clkdiv = tmp;
> +
> +		tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
> +
> +		if (soc_is_exynos4212()) {
> +			tmp&= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
> +				EXYNOS4_CLKDIV_CPU1_HPM_MASK);
> +			tmp |= ((clkdiv_cpu1_4212[i][0]<<  EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
> +				(clkdiv_cpu1_4212[i][1]<<  EXYNOS4_CLKDIV_CPU1_HPM_SHIFT));
> +		} else {
> +			tmp&= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
> +				EXYNOS4_CLKDIV_CPU1_HPM_MASK |
> +				EXYNOS4_CLKDIV_CPU1_CORES_MASK);
> +			tmp |= ((clkdiv_cpu1_4412[i][0]<<  EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
> +				(clkdiv_cpu1_4412[i][1]<<  EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
> +				(clkdiv_cpu1_4412[i][2]<<  EXYNOS4_CLKDIV_CPU1_CORES_SHIFT));
> +		}
> +		exynos4x12_clkdiv_table[i].clkdiv1 = tmp;
> +	}
> +
> +	info->mpll_freq_khz = rate;
> +	info->pm_lock_idx = L5;
> +	info->pll_safe_idx = L7;
> +	info->max_support_idx = max_support_idx;
> +	info->min_support_idx = min_support_idx;
> +	info->cpu_clk = cpu_clk;
> +	info->volt_table = exynos4x12_volt_table;
> +	info->freq_table = exynos4x12_freq_table;
> +	info->set_freq = exynos4x12_set_frequency;
> +	info->need_apll_change = exynos4x12_pms_change;
> +
> +	return 0;
> +
> +err_mout_apll:
> +	clk_put(mout_mpll);
> +err_mout_mpll:
> +	clk_put(moutcore);
> +err_moutcore:
> +	clk_put(cpu_clk);
> +
> +	pr_debug("%s: failed initialization\n", __func__);
> +	return -EINVAL;
> +}
> +EXPORT_SYMBOL(exynos4x12_cpufreq_init);


From kgene.kim at samsung.com  Wed Mar 14 13:31:42 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 10:31:42 -0700
Subject: [PATCH v2 RE-SEND] [CPUFREQ] EXYNOS5250: Add support cpufreq
 for EXYNOS5250
In-Reply-To: <1331377202-25173-1-git-send-email-kgene.kim@samsung.com>
References: <1331377202-25173-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <4F60D5FE.7080400@samsung.com>

Kukjin Kim wrote:
> From: Jaecheol Lee<jc.lee at samsung.com>
> 
> This patch adds support cpufreq for EXYNOS5250 SoC. Basically,
> the exynos-cpufreq.c is used commonly and exynos5250-cpufreq.c
> is used for EXYNOS5250(two Cortex-A15 cores) SoC.
> 
> Signed-off-by: Jaecheol Lee<jc.lee at samsung.com>
> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>

Hi again Dave :)

Please pick up this patch for v3.4.
If any problems, please kindly let us know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

> ---
>   arch/arm/mach-exynos/include/mach/cpufreq.h |    1 +
>   drivers/cpufreq/Kconfig.arm                 |    7 +
>   drivers/cpufreq/Makefile                    |    1 +
>   drivers/cpufreq/exynos-cpufreq.c            |    2 +
>   drivers/cpufreq/exynos5250-cpufreq.c        |  347 +++++++++++++++++++++++++++
>   5 files changed, 358 insertions(+), 0 deletions(-)
>   create mode 100644 drivers/cpufreq/exynos5250-cpufreq.c
> 
> diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
> index 96ac0cb..7517c3f 100644
> --- a/arch/arm/mach-exynos/include/mach/cpufreq.h
> +++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
> @@ -33,3 +33,4 @@ struct exynos_dvfs_info {
> 
>   extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
>   extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
> +extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index 9b99a96..2e33515 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -48,6 +48,7 @@ config ARM_EXYNOS_CPUFREQ
>   	depends on ARCH_EXYNOS
>   	select ARM_EXYNOS4210_CPUFREQ if CPU_EXYNOS4210
>   	select ARM_EXYNOS4X12_CPUFREQ if (SOC_EXYNOS4212 || SOC_EXYNOS4412)
> +	select ARM_EXYNOS5250_CPUFREQ if SOC_EXYNOS5250
>   	default y
>   	help
>   	  This adds the CPUFreq driver common part for Samsung
> @@ -67,3 +68,9 @@ config ARM_EXYNOS4X12_CPUFREQ
>   	help
>   	  This adds the CPUFreq driver for Samsung EXYNOS4X12
>   	  SoC (EXYNOS4212 or EXYNOS4412).
> +
> +config ARM_EXYNOS5250_CPUFREQ
> +	bool "Samsung EXYNOS5250"
> +	help
> +	  This adds the CPUFreq driver for Samsung EXYNOS5250
> +	  SoC.
> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> index f37bbcc..3cbbcd0 100644
> --- a/drivers/cpufreq/Makefile
> +++ b/drivers/cpufreq/Makefile
> @@ -46,6 +46,7 @@ obj-$(CONFIG_ARM_S5PV210_CPUFREQ)	+= s5pv210-cpufreq.o
>   obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
>   obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
>   obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)	+= exynos4x12-cpufreq.o
> +obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ)	+= exynos5250-cpufreq.o
>   obj-$(CONFIG_ARCH_OMAP2PLUS)            += omap-cpufreq.o
> 
>   ##################################################################################
> diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
> index 2c63b68..b243a7e 100644
> --- a/drivers/cpufreq/exynos-cpufreq.c
> +++ b/drivers/cpufreq/exynos-cpufreq.c
> @@ -256,6 +256,8 @@ static int __init exynos_cpufreq_init(void)
>   		ret = exynos4210_cpufreq_init(exynos_info);
>   	else if (soc_is_exynos4212() || soc_is_exynos4412())
>   		ret = exynos4x12_cpufreq_init(exynos_info);
> +	else if (soc_is_exynos5250())
> +		ret = exynos5250_cpufreq_init(exynos_info);
>   	else
>   		pr_err("%s: CPU type not found\n", __func__);
> 
> diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c
> new file mode 100644
> index 0000000..a883316
> --- /dev/null
> +++ b/drivers/cpufreq/exynos5250-cpufreq.c
> @@ -0,0 +1,347 @@
> +/*
> + * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * EXYNOS5250 - CPU frequency scaling support
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include<linux/module.h>
> +#include<linux/kernel.h>
> +#include<linux/err.h>
> +#include<linux/clk.h>
> +#include<linux/io.h>
> +#include<linux/slab.h>
> +#include<linux/cpufreq.h>
> +
> +#include<mach/map.h>
> +#include<mach/regs-clock.h>
> +#include<mach/cpufreq.h>
> +
> +#define CPUFREQ_LEVEL_END	(L15 + 1)
> +
> +static int max_support_idx;
> +static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
> +static struct clk *cpu_clk;
> +static struct clk *moutcore;
> +static struct clk *mout_mpll;
> +static struct clk *mout_apll;
> +
> +struct cpufreq_clkdiv {
> +	unsigned int	index;
> +	unsigned int	clkdiv;
> +	unsigned int	clkdiv1;
> +};
> +
> +static unsigned int exynos5250_volt_table[CPUFREQ_LEVEL_END];
> +
> +static struct cpufreq_frequency_table exynos5250_freq_table[] = {
> +	{L0, 1700 * 1000},
> +	{L1, 1600 * 1000},
> +	{L2, 1500 * 1000},
> +	{L3, 1400 * 1000},
> +	{L4, 1300 * 1000},
> +	{L5, 1200 * 1000},
> +	{L6, 1100 * 1000},
> +	{L7, 1000 * 1000},
> +	{L8, 900 * 1000},
> +	{L9, 800 * 1000},
> +	{L10, 700 * 1000},
> +	{L11, 600 * 1000},
> +	{L12, 500 * 1000},
> +	{L13, 400 * 1000},
> +	{L14, 300 * 1000},
> +	{L15, 200 * 1000},
> +	{0, CPUFREQ_TABLE_END},
> +};
> +
> +static struct cpufreq_clkdiv exynos5250_clkdiv_table[CPUFREQ_LEVEL_END];
> +
> +static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = {
> +	/*
> +	 * Clock divider value for following
> +	 * { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 }
> +	 */
> +	{ 0, 3, 7, 7, 6, 1, 3, 0 },	/* 1700 MHz - N/A */
> +	{ 0, 3, 7, 7, 6, 1, 3, 0 },	/* 1600 MHz - N/A */
> +	{ 0, 3, 7, 7, 5, 1, 3, 0 },	/* 1500 MHz - N/A */
> +	{ 0, 3, 7, 7, 6, 1, 3, 0 },	/* 1400 MHz */
> +	{ 0, 3, 7, 7, 6, 1, 3, 0 },	/* 1300 MHz */
> +	{ 0, 3, 7, 7, 5, 1, 3, 0 },	/* 1200 MHz */
> +	{ 0, 2, 7, 7, 5, 1, 2, 0 },	/* 1100 MHz */
> +	{ 0, 2, 7, 7, 4, 1, 2, 0 },	/* 1000 MHz */
> +	{ 0, 2, 7, 7, 4, 1, 2, 0 },	/* 900 MHz */
> +	{ 0, 2, 7, 7, 3, 1, 1, 0 },	/* 800 MHz */
> +	{ 0, 1, 7, 7, 3, 1, 1, 0 },	/* 700 MHz */
> +	{ 0, 1, 7, 7, 2, 1, 1, 0 },	/* 600 MHz */
> +	{ 0, 1, 7, 7, 2, 1, 1, 0 },	/* 500 MHz */
> +	{ 0, 1, 7, 7, 1, 1, 1, 0 },	/* 400 MHz */
> +	{ 0, 1, 7, 7, 1, 1, 1, 0 },	/* 300 MHz */
> +	{ 0, 1, 7, 7, 1, 1, 1, 0 },	/* 200 MHz */
> +};
> +
> +static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
> +	/* Clock divider value for following
> +	 * { COPY, HPM }
> +	 */
> +	{ 0, 2 },	/* 1700 MHz - N/A */
> +	{ 0, 2 },	/* 1600 MHz - N/A */
> +	{ 0, 2 },	/* 1500 MHz - N/A */
> +	{ 0, 2 },	/* 1400 MHz */
> +	{ 0, 2 },	/* 1300 MHz */
> +	{ 0, 2 },	/* 1200 MHz */
> +	{ 0, 2 },	/* 1100 MHz */
> +	{ 0, 2 },	/* 1000 MHz */
> +	{ 0, 2 },	/* 900 MHz */
> +	{ 0, 2 },	/* 800 MHz */
> +	{ 0, 2 },	/* 700 MHz */
> +	{ 0, 2 },	/* 600 MHz */
> +	{ 0, 2 },	/* 500 MHz */
> +	{ 0, 2 },	/* 400 MHz */
> +	{ 0, 2 },	/* 300 MHz */
> +	{ 0, 2 },	/* 200 MHz */
> +};
> +
> +static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
> +	(0),				/* 1700 MHz - N/A */
> +	(0),				/* 1600 MHz - N/A */
> +	(0),				/* 1500 MHz - N/A */
> +	(0),				/* 1400 MHz */
> +	((325<<  16) | (6<<  8) | 0),	/* 1300 MHz */
> +	((200<<  16) | (4<<  8) | 0),	/* 1200 MHz */
> +	((275<<  16) | (6<<  8) | 0),	/* 1100 MHz */
> +	((125<<  16) | (3<<  8) | 0),	/* 1000 MHz */
> +	((150<<  16) | (4<<  8) | 0),	/* 900 MHz */
> +	((100<<  16) | (3<<  8) | 0),	/* 800 MHz */
> +	((175<<  16) | (3<<  8) | 1),	/* 700 MHz */
> +	((200<<  16) | (4<<  8) | 1),	/* 600 MHz */
> +	((125<<  16) | (3<<  8) | 1),	/* 500 MHz */
> +	((100<<  16) | (3<<  8) | 1),	/* 400 MHz */
> +	((200<<  16) | (4<<  8) | 2),	/* 300 MHz */
> +	((100<<  16) | (3<<  8) | 2),	/* 200 MHz */
> +};
> +
> +/* ASV group voltage table */
> +static const unsigned int asv_voltage_5250[CPUFREQ_LEVEL_END] = {
> +	0, 0, 0, 0, 0, 0, 0,	/* 1700 MHz ~ 1100 MHz Not supported */
> +	1175000, 1125000, 1075000, 1050000, 1000000,
> +	950000, 925000, 925000, 900000
> +};
> +
> +static void set_clkdiv(unsigned int div_index)
> +{
> +	unsigned int tmp;
> +
> +	/* Change Divider - CPU0 */
> +
> +	tmp = exynos5250_clkdiv_table[div_index].clkdiv;
> +
> +	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
> +
> +	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0)&  0x11111111)
> +		cpu_relax();
> +
> +	/* Change Divider - CPU1 */
> +	tmp = exynos5250_clkdiv_table[div_index].clkdiv1;
> +
> +	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
> +
> +	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1)&  0x11)
> +		cpu_relax();
> +}
> +
> +static void set_apll(unsigned int new_index,
> +			     unsigned int old_index)
> +{
> +	unsigned int tmp, pdiv;
> +
> +	/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
> +	clk_set_parent(moutcore, mout_mpll);
> +
> +	do {
> +		cpu_relax();
> +		tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU)>>  16);
> +		tmp&= 0x7;
> +	} while (tmp != 0x2);
> +
> +	/* 2. Set APLL Lock time */
> +	pdiv = ((exynos5_apll_pms_table[new_index]>>  8)&  0x3f);
> +
> +	__raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK);
> +
> +	/* 3. Change PLL PMS values */
> +	tmp = __raw_readl(EXYNOS5_APLL_CON0);
> +	tmp&= ~((0x3ff<<  16) | (0x3f<<  8) | (0x7<<  0));
> +	tmp |= exynos5_apll_pms_table[new_index];
> +	__raw_writel(tmp, EXYNOS5_APLL_CON0);
> +
> +	/* 4. wait_lock_time */
> +	do {
> +		cpu_relax();
> +		tmp = __raw_readl(EXYNOS5_APLL_CON0);
> +	} while (!(tmp&  (0x1<<  29)));
> +
> +	/* 5. MUX_CORE_SEL = APLL */
> +	clk_set_parent(moutcore, mout_apll);
> +
> +	do {
> +		cpu_relax();
> +		tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
> +		tmp&= (0x7<<  16);
> +	} while (tmp != (0x1<<  16));
> +
> +}
> +
> +bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index)
> +{
> +	unsigned int old_pm = (exynos5_apll_pms_table[old_index]>>  8);
> +	unsigned int new_pm = (exynos5_apll_pms_table[new_index]>>  8);
> +
> +	return (old_pm == new_pm) ? 0 : 1;
> +}
> +
> +static void exynos5250_set_frequency(unsigned int old_index,
> +				  unsigned int new_index)
> +{
> +	unsigned int tmp;
> +
> +	if (old_index>  new_index) {
> +		if (!exynos5250_pms_change(old_index, new_index)) {
> +			/* 1. Change the system clock divider values */
> +			set_clkdiv(new_index);
> +			/* 2. Change just s value in apll m,p,s value */
> +			tmp = __raw_readl(EXYNOS5_APLL_CON0);
> +			tmp&= ~(0x7<<  0);
> +			tmp |= (exynos5_apll_pms_table[new_index]&  0x7);
> +			__raw_writel(tmp, EXYNOS5_APLL_CON0);
> +
> +		} else {
> +			/* Clock Configuration Procedure */
> +			/* 1. Change the system clock divider values */
> +			set_clkdiv(new_index);
> +			/* 2. Change the apll m,p,s value */
> +			set_apll(new_index, old_index);
> +		}
> +	} else if (old_index<  new_index) {
> +		if (!exynos5250_pms_change(old_index, new_index)) {
> +			/* 1. Change just s value in apll m,p,s value */
> +			tmp = __raw_readl(EXYNOS5_APLL_CON0);
> +			tmp&= ~(0x7<<  0);
> +			tmp |= (exynos5_apll_pms_table[new_index]&  0x7);
> +			__raw_writel(tmp, EXYNOS5_APLL_CON0);
> +			/* 2. Change the system clock divider values */
> +			set_clkdiv(new_index);
> +		} else {
> +			/* Clock Configuration Procedure */
> +			/* 1. Change the apll m,p,s value */
> +			set_apll(new_index, old_index);
> +			/* 2. Change the system clock divider values */
> +			set_clkdiv(new_index);
> +		}
> +	}
> +}
> +
> +static void __init set_volt_table(void)
> +{
> +	unsigned int i;
> +
> +	exynos5250_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
> +	exynos5250_freq_table[L1].frequency = CPUFREQ_ENTRY_INVALID;
> +	exynos5250_freq_table[L2].frequency = CPUFREQ_ENTRY_INVALID;
> +	exynos5250_freq_table[L3].frequency = CPUFREQ_ENTRY_INVALID;
> +	exynos5250_freq_table[L4].frequency = CPUFREQ_ENTRY_INVALID;
> +	exynos5250_freq_table[L5].frequency = CPUFREQ_ENTRY_INVALID;
> +	exynos5250_freq_table[L6].frequency = CPUFREQ_ENTRY_INVALID;
> +
> +	max_support_idx = L7;
> +
> +	for (i = 0 ; i<  CPUFREQ_LEVEL_END ; i++)
> +		exynos5250_volt_table[i] = asv_voltage_5250[i];
> +}
> +
> +int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
> +{
> +	int i;
> +	unsigned int tmp;
> +	unsigned long rate;
> +
> +	set_volt_table();
> +
> +	cpu_clk = clk_get(NULL, "armclk");
> +	if (IS_ERR(cpu_clk))
> +		return PTR_ERR(cpu_clk);
> +
> +	moutcore = clk_get(NULL, "mout_cpu");
> +	if (IS_ERR(moutcore))
> +		goto err_moutcore;
> +
> +	mout_mpll = clk_get(NULL, "mout_mpll");
> +	if (IS_ERR(mout_mpll))
> +		goto err_mout_mpll;
> +
> +	rate = clk_get_rate(mout_mpll) / 1000;
> +
> +	mout_apll = clk_get(NULL, "mout_apll");
> +	if (IS_ERR(mout_apll))
> +		goto err_mout_apll;
> +
> +	for (i = L0; i<  CPUFREQ_LEVEL_END; i++) {
> +
> +		exynos5250_clkdiv_table[i].index = i;
> +
> +		tmp = __raw_readl(EXYNOS5_CLKDIV_CPU0);
> +
> +		tmp&= ~((0x7<<  0) | (0x7<<  4) | (0x7<<  8) |
> +			(0x7<<  12) | (0x7<<  16) | (0x7<<  20) |
> +			(0x7<<  24) | (0x7<<  28));
> +
> +		tmp |= ((clkdiv_cpu0_5250[i][0]<<  0) |
> +			(clkdiv_cpu0_5250[i][1]<<  4) |
> +			(clkdiv_cpu0_5250[i][2]<<  8) |
> +			(clkdiv_cpu0_5250[i][3]<<  12) |
> +			(clkdiv_cpu0_5250[i][4]<<  16) |
> +			(clkdiv_cpu0_5250[i][5]<<  20) |
> +			(clkdiv_cpu0_5250[i][6]<<  24) |
> +			(clkdiv_cpu0_5250[i][7]<<  28));
> +
> +		exynos5250_clkdiv_table[i].clkdiv = tmp;
> +
> +		tmp = __raw_readl(EXYNOS5_CLKDIV_CPU1);
> +
> +		tmp&= ~((0x7<<  0) | (0x7<<  4));
> +
> +		tmp |= ((clkdiv_cpu1_5250[i][0]<<  0) |
> +			(clkdiv_cpu1_5250[i][1]<<  4));
> +
> +		exynos5250_clkdiv_table[i].clkdiv1 = tmp;
> +	}
> +
> +	info->mpll_freq_khz = rate;
> +	/* 1000Mhz */
> +	info->pm_lock_idx = L7;
> +	/* 800Mhz */
> +	info->pll_safe_idx = L9;
> +	info->max_support_idx = max_support_idx;
> +	info->min_support_idx = min_support_idx;
> +	info->cpu_clk = cpu_clk;
> +	info->volt_table = exynos5250_volt_table;
> +	info->freq_table = exynos5250_freq_table;
> +	info->set_freq = exynos5250_set_frequency;
> +	info->need_apll_change = exynos5250_pms_change;
> +
> +	return 0;
> +
> +err_mout_apll:
> +	clk_put(mout_mpll);
> +err_mout_mpll:
> +	clk_put(moutcore);
> +err_moutcore:
> +	clk_put(cpu_clk);
> +
> +	pr_err("%s: failed initialization\n", __func__);
> +	return -EINVAL;
> +}
> +EXPORT_SYMBOL(exynos5250_cpufreq_init);


From Valdis.Kletnieks at vt.edu  Wed Mar 14 13:33:05 2012
From: Valdis.Kletnieks at vt.edu (Valdis.Kletnieks at vt.edu)
Date: Wed, 14 Mar 2012 13:33:05 -0400
Subject: [INFO] : Hibernation and Resume between 2 similar devices
In-Reply-To: Your message of "Wed, 14 Mar 2012 03:21:58 PDT."
 <1331720518.14716.YahooMailNeo@web162005.mail.bf1.yahoo.com>
References: <28119509.96581331614425960.JavaMail.weblogic@epml27>
 <201203132136.56353.rjw@sisk.pl>
 <1331720518.14716.YahooMailNeo@web162005.mail.bf1.yahoo.com>
Message-ID: <10238.1331746385@turing-police.cc.vt.edu>

On Wed, 14 Mar 2012 03:21:58 PDT, PINTU KUMAR said:
> > From: Rafael J. Wysocki <rjw at sisk.pl>
> > Not out of the box (you'd need to hack the kernel for that to work I think,
> > at least on x86) and the devices would need to be _exactly_ identical.
> > Moreover, if there is read-write mass storage in them, the filesystems on
> > both would have to be exactly identical as well (including metadata and data
> > layout etc.).

> Suppose in "Device 1" during hibernation, I have a file say "file1.txt" opened whose inode number is say "123456".
> This opened state of file1.txt will be captured in hibernation image.
> Now assume that same "file1.txt" is also present (not opened) in "Device2" but whose inode number is say "567890".
> Now if I reboot "Device 2" and try to resume from hibernated image of "Device 1", what would happen to "file1.txt" ??

Rafael was quite clear - the mass storage has to be *identical*.  You reboot
with the image of "Device 1", that had file1.txt open, what will happen when
you close (or write, or sync) the file is this:

1) You'll write data out to disk into whatever blocks were owned by inode
12345, no matter who actually owns them on Device2's storage.

2) You'll write out inode 12345 to disk, no matter what used to be there.

Note that you'll do this same thing for *every single* file that was open when
you hibernated, which means you'll corrupt every file that was opened *and*
every file that was closed but was using the same blocks on the new disk as the
open file was using on the original disk.

In short, you just completely corrupted the file system. 
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From plagnioj at jcrosoft.com  Wed Mar 14 13:24:35 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Wed, 14 Mar 2012 18:24:35 +0100
Subject: [PATCH v2] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <201203141749.05899.sr@denx.de>
References: <1331737232-25477-1-git-send-email-sr@denx.de>
 <20120314162152.GN18320@game.jcrosoft.org>
 <201203141749.05899.sr@denx.de>
Message-ID: <20120314172435.GP18320@game.jcrosoft.org>

On 17:49 Wed 14 Mar     , Stefan Roese wrote:
> On Wednesday 14 March 2012 17:21:52 Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 16:00 Wed 14 Mar     , Stefan Roese wrote:
> > > This patch adds a generic target for SPEAr600 board that can be
> > > configured via the device-tree. Currently the following devices
> > > are supported via the devicetree:
> > > 
> > > - VIC interrupts
> > > - PL011 UART
> > > - PL061 GPIO
> > > - Synopsys DW I2C
> > > - Synopsys DW ethernet
> > > 
> > > Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
> > > follow in later patches.
> > > 
> > > Only the spear600-evb is currently supported. Other SPEAr600
> > > based boards will follow later.
> > > 
> > > Additionally the file spear600.c is deleted. It contained only
> > > one empty function and is not needed. So lets just remove it.
> > > 
> > > Signed-off-by: Stefan Roese <sr at denx.de>
> > > Cc: Viresh Kumar <viresh.kumar at st.com>
> > > Cc: Arnd Bergmann <arnd at arndb.de>
> > > ---
> > > v2:
> > > - Added DT support to spear6xx.c instead of creating board-dt.c
> > > - Removed UART (PL011) and GPIO (PL061) platform data for
> > > 
> > >   devicetree board port. This works now via DT probing
> > > 
> > > - Added OF_DEV_AUXDATA for clock device name matching for some
> > > 
> > >   device drivers
> > > 
> > > - Removed sper600.c file completely
> > > - Added DW I2C and ethernet nodes to the dts files
> > > - Added other DT nodes (SMI, FSMC, ECHI, OHCI), currently disabled
> > > 
> > >   since the corresponding device drivers don't support DT probing
> > > 
> > > - Removed Linaro/FSL copyright notice from SPEAr DT files (copy-paste
> > > cruft) - Many smaller modification to the dts/dtsi files
> > > - Changed Documentation/devicetree/bindings/arm/spear.txt to match
> > > 
> > >   the changed bindings
> > >  
> > >  Documentation/devicetree/bindings/arm/spear.txt |    8 ++
> > >  arch/arm/boot/dts/spear600-evb.dts              |   30 +++++
> > >  arch/arm/boot/dts/spear600.dtsi                 |  162
> > >  +++++++++++++++++++++++ arch/arm/mach-spear6xx/Kconfig                 
> > >  |    7 +
> > >  arch/arm/mach-spear6xx/Makefile                 |    3 -
> > >  arch/arm/mach-spear6xx/spear600.c               |   25 ----
> > >  arch/arm/mach-spear6xx/spear600_evb.c           |    3 -
> > >  arch/arm/mach-spear6xx/spear6xx.c               |   69 +++++++++-
> > >  8 files changed, 270 insertions(+), 37 deletions(-)
> > >  create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
> > >  create mode 100644 arch/arm/boot/dts/spear600-evb.dts
> > >  create mode 100644 arch/arm/boot/dts/spear600.dtsi
> > >  delete mode 100644 arch/arm/mach-spear6xx/spear600.c
> > > 
> > > diff --git a/Documentation/devicetree/bindings/arm/spear.txt
> > > b/Documentation/devicetree/bindings/arm/spear.txt new file mode 100644
> > > index 0000000..f8e54f0
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/arm/spear.txt
> > > @@ -0,0 +1,8 @@
> > > +ST SPEAr Platforms Device Tree Bindings
> > > +---------------------------------------
> > > +
> > > +Boards with the ST SPEAr600 SoC shall have the following properties:
> > > +
> > > +Required root node property:
> > > +
> > > +compatible = "st,spear600";
> > > diff --git a/arch/arm/boot/dts/spear600-evb.dts
> > > b/arch/arm/boot/dts/spear600-evb.dts new file mode 100644
> > > index 0000000..cbfda8d
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/spear600-evb.dts
> > > @@ -0,0 +1,30 @@
> > > +/*
> > > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > > + *
> > > + * The code contained herein is licensed under the GNU General Public
> > > + * License. You may obtain a copy of the GNU General Public License
> > > + * Version 2 or later at the following locations:
> > > + *
> > > + * http://www.opensource.org/licenses/gpl-license.html
> > > + * http://www.gnu.org/copyleft/gpl.html
> > > + */
> > > +
> > > +/dts-v1/;
> > > +/include/ "spear600.dtsi"
> > > +
> > > +/ {
> > > +	model = "ST SPEAr600 Evaluation Board";
> > > +	compatible = "st,spear600-evb", "st,spear600";
> > > +	#address-cells = <1>;
> > > +	#size-cells = <1>;
> > 
> > please put the mem size here
> 
> Might I ask why? Other *.dtsi files don't have it either.
do not expect the bootloader to put it. I t's not mandatory
> 
> > > +
> > > +	soc {
> > > +		gmac0: ethernet at e0800000 {
> > > +			phy-mode = "gmii";
> > > +		};
> > > +
> > > +		i2c at d0200000 {
> > > +			clock-frequency = <400000>;
> > > +		};
> > > +	};
> > > +};
> > > diff --git a/arch/arm/boot/dts/spear600.dtsi
> > > b/arch/arm/boot/dts/spear600.dtsi new file mode 100644
> > > index 0000000..e45e58f
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/spear600.dtsi
> > > @@ -0,0 +1,162 @@
> > > +/*
> > > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > > + *
> > > + * The code contained herein is licensed under the GNU General Public
> > > + * License. You may obtain a copy of the GNU General Public License
> > > + * Version 2 or later at the following locations:
> > > + *
> > > + * http://www.opensource.org/licenses/gpl-license.html
> > > + * http://www.gnu.org/copyleft/gpl.html
> > > + */
> > > +
> > > +/include/ "skeleton.dtsi"
> > > +
> > > +/ {
> > > +	compatible = "st,spear600";
> > > +
> > > +	cpus {
> > > +		cpu at 0 {
> > > +			compatible = "arm,arm926ejs";
> > > +		};
> > > +	};
> > > +
> > > +	memory {
> > > +		device_type = "memory";
> > > +		reg = <0 0>; /* Filled by U-Boot */
> > 
> > please put the max mem of the SoC here
> 
> Why? It's always updated by the bootloader. And a max. mem size (when not 
> updated to the correct mem size by the bootloader) would crash the board if it 
> is equipped with less memory.
yes but we descripbe the soc here and on the dts you reduce it
Never expect the bootloader to update it.

It's a possibility not mandatory


>  
> > > +	};
> > > +
> > > +	soc {
> > 
> > please put the name of the bus not soc
> 
> Okay.
> 
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		compatible = "simple-bus";
> > > +		ranges;
> > > +
> > > +		vic0: interrupt-controller at f1100000 {
> > > +			compatible = "arm,pl190-vic";
> > > +			interrupt-controller;
> > > +			reg = <0xf1100000 0x1000>;
> > > +			#interrupt-cells = <1>;
> > > +		};
> > > +
> > > +		vic1: interrupt-controller at f1000000 {
> > > +			compatible = "arm,pl190-vic";
> > > +			interrupt-controller;
> > > +			reg = <0xf1000000 0x1000>;
> > > +			#interrupt-cells = <1>;
> > > +		};
> > > +
> > > +		serial at d0000000 {
> > > +			compatible = "arm,pl011", "arm,primecell";
> > > +			reg = <0xd0000000 0x1000>;
> > > +			interrupt-parent = <&vic0>;
> > > +			interrupts = <24>;
> > > +		};
> > > +
> > > +		serial at d0080000 {
> > > +			compatible = "arm,pl011", "arm,primecell";
> > > +			reg = <0xd0080000 0x1000>;
> > > +			interrupt-parent = <&vic0>;
> > > +			interrupts = <25>;
> > > +		};
> > > +
> > > +		/* local/cpu GPIO */
> > > +		gpio0: gpio at f0100000 {
> > > +			#gpio-cells = <2>;
> > > +			compatible = "arm,pl061", "arm,primecell";
> > > +			gpio-controller;
> > > +			reg = <0xf0100000 0x1000>;
> > > +			interrupt-parent = <&vic0>;
> > > +			interrupts = <18>;
> > > +		};
> > > +
> > > +		/* basic GPIO */
> > > +		gpio1: gpio at fc980000 {
> > > +			#gpio-cells = <2>;
> > > +			compatible = "arm,pl061", "arm,primecell";
> > > +			gpio-controller;
> > > +			reg = <0xfc980000 0x1000>;
> > > +			interrupt-parent = <&vic1>;
> > > +			interrupts = <19>;
> > > +		};
> > > +
> > > +		/* appl GPIO */
> > > +		gpio2: gpio at d8100000 {
> > > +			#gpio-cells = <2>;
> > > +			compatible = "arm,pl061", "arm,primecell";
> > > +			gpio-controller;
> > > +			reg = <0xd8100000 0x1000>;
> > > +			interrupt-parent = <&vic1>;
> > > +			interrupts = <4>;
> > > +		};
> > > +
> > > +		gmac0: ethernet at e0800000 {
> > > +			compatible = "st,spear600-gmac";
> > > +			reg = <0xe0800000 0x8000>;
> > > +			interrupt-parent = <&vic1>;
> > > +			interrupts = <24 23>;
> > > +			interrupt-names = "macirq", "eth_wake_irq";
> > > +			mac-address = [000000000000]; /* Filled in by U-Boot 
> */
drop this no dummy data
> > > +		};
> > > +
> > > +		i2c at d0200000 {
> > > +			#address-cells = <1>;
> > > +			#size-cells = <0>;
> > > +			compatible = "snps,designware-i2c";
> > > +			reg = <0xd0200000 0x1000>;
> > > +			interrupt-parent = <&vic0>;
> > > +			interrupts = <28>;
> > > +		};
> > > +
> > > +		fsmc0: flash at d1800000 {
> > > +			status = "disabled";
> > > +			compatible = "st,spear600-fsmc-nand";
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +			reg = <0xd1800000 0x1000	/* FSMC Register */
> > > +			       0xd2000000 0x4000>;	/* NAND Base */
> > > +			reg-names = "fsmc_regs", "nand_data";
> > > +		};
> > > +
> > > +		smi0: flash at fc000000 {
> > > +			status = "disabled";
> > > +			compatible = "st,spear600-smi";
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +			reg = <0xfc000000 0x1000>;
> > > +			interrupt-parent = <&vic1>;
> > > +			interrupts = <12>;
> > > +		};
> > > +
> > > +		ehci at e1800000 {
> > > +			status = "disabled";
> > > +			compatible = "st,spear600-ehci", "usb-ehci";
> > > +			reg = <0xe1800000 0x1000>;
> > > +			interrupt-parent = <&vic1>;
> > > +			interrupts = <27>;
> > > +		};
> > > +
> > > +		ehci at e2000000 {
> > > +			status = "disabled";
> > > +			compatible = "st,spear600-ehci", "usb-ehci";
> > > +			reg = <0xe2000000 0x1000>;
> > > +			interrupt-parent = <&vic1>;
> > > +			interrupts = <29>;
> > > +		};
> > > +
> > > +		ohci at e1900000 {
> > > +			status = "disabled";
> > > +			compatible = "st,spear600-ohci", "usb-ohci";
> > > +			reg = <0xe1900000 0x1000>;
> > > +			interrupt-parent = <&vic1>;
> > > +			interrupts = <26>;
> > > +		};
> > > +
> > > +		ohci at e2100000 {
> > > +			status = "disabled";
> > > +			compatible = "st,spear600-ohci", "usb-ohci";
> > > +			reg = <0xe2100000 0x1000>;
> > > +			interrupt-parent = <&vic1>;
> > > +			interrupts = <28>;
> > > +		};
> > 
> > all of this need a Doc for the ST bindings
> 
> Sure. I only provided those nodes on Arnd's special request. They are 
> currently disabled. And documentation will follow with the DT device driver 
> patches.
no update it after
> 
> > > +	};
> > > +};
> > > diff --git a/arch/arm/mach-spear6xx/Kconfig
> > > b/arch/arm/mach-spear6xx/Kconfig index ff4ae5b..7777f72 100644
> > > --- a/arch/arm/mach-spear6xx/Kconfig
> > > +++ b/arch/arm/mach-spear6xx/Kconfig
> > > @@ -11,6 +11,13 @@ config BOARD_SPEAR600_EVB
> > > 
> > >  	help
> > >  	
> > >  	  Supports ST SPEAr600 Evaluation Board
> > > 
> > > +config BOARD_SPEAR600_DT
> > > +	bool "SPEAr600 generic board configured via device-tree"
> > > +	select MACH_SPEAR600
> > > +	select USE_OF
> > > +	help
> > > +	  Supports ST SPEAr600 boards configured via the device-tree
> > > +
> > > 
> > >  endmenu
> > >  
> > >  config MACH_SPEAR600
> > > 
> > > diff --git a/arch/arm/mach-spear6xx/Makefile
> > > b/arch/arm/mach-spear6xx/Makefile index cc1a4d8..6f87c3a 100644
> > > --- a/arch/arm/mach-spear6xx/Makefile
> > > +++ b/arch/arm/mach-spear6xx/Makefile
> > > @@ -5,8 +5,5 @@
> > > 
> > >  # common files
> > >  obj-y	+= clock.o spear6xx.o
> > > 
> > > -# spear600 specific files
> > > -obj-$(CONFIG_MACH_SPEAR600) += spear600.o
> > > -
> > > 
> > >  # spear600 boards files
> > >  obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
> > > 
> > > diff --git a/arch/arm/mach-spear6xx/spear600.c
> > > b/arch/arm/mach-spear6xx/spear600.c deleted file mode 100644
> > > index d0e6eea..0000000
> > > --- a/arch/arm/mach-spear6xx/spear600.c
> > > +++ /dev/null
> > > @@ -1,25 +0,0 @@
> > > -/*
> > > - * arch/arm/mach-spear6xx/spear600.c
> > > - *
> > > - * SPEAr600 machine source file
> > > - *
> > > - * Copyright (C) 2009 ST Microelectronics
> > > - * Rajeev Kumar<rajeev-dlh.kumar at st.com>
> > > - *
> > > - * This file is licensed under the terms of the GNU General Public
> > > - * License version 2. This program is licensed "as is" without any
> > > - * warranty of any kind, whether express or implied.
> > > - */
> > > -
> > > -#include <linux/ptrace.h>
> > > -#include <asm/irq.h>
> > > -#include <mach/generic.h>
> > > -#include <mach/hardware.h>
> > > -
> > > -/* Add spear600 specific devices here */
> > > -
> > > -void __init spear600_init(void)
> > > -{
> > > -	/* call spear6xx family common init function */
> > > -	spear6xx_init();
> > > -}
> > > diff --git a/arch/arm/mach-spear6xx/spear600_evb.c
> > > b/arch/arm/mach-spear6xx/spear600_evb.c index c6e4254..c4949aa 100644
> > > --- a/arch/arm/mach-spear6xx/spear600_evb.c
> > > +++ b/arch/arm/mach-spear6xx/spear600_evb.c
> > > @@ -32,9 +32,6 @@ static void __init spear600_evb_init(void)
> > > 
> > >  {
> > >  
> > >  	unsigned int i;
> > > 
> > > -	/* call spear600 machine init function */
> > > -	spear600_init();
> > > -
> > > 
> > >  	/* Add Platform Devices */
> > >  	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
> > > 
> > > diff --git a/arch/arm/mach-spear6xx/spear6xx.c
> > > b/arch/arm/mach-spear6xx/spear6xx.c index e0f6628..aca20f0 100644
> > > --- a/arch/arm/mach-spear6xx/spear6xx.c
> > > +++ b/arch/arm/mach-spear6xx/spear6xx.c
> > > @@ -6,6 +6,8 @@
> > > 
> > >   * Copyright (C) 2009 ST Microelectronics
> > >   * Rajeev Kumar<rajeev-dlh.kumar at st.com>
> > >   *
> > > 
> > > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > > + *
> > > 
> > >   * This file is licensed under the terms of the GNU General Public
> > >   * License version 2. This program is licensed "as is" without any
> > >   * warranty of any kind, whether express or implied.
> > > 
> > > @@ -15,6 +17,10 @@
> > > 
> > >  #include <linux/amba/pl061.h>
> > >  #include <linux/ptrace.h>
> > >  #include <linux/io.h>
> > > 
> > > +#include <linux/of.h>
> > > +#include <linux/of_address.h>
> > > +#include <linux/of_irq.h>
> > > +#include <linux/of_platform.h>
> > > 
> > >  #include <asm/hardware/vic.h>
> > >  #include <asm/irq.h>
> > >  #include <asm/mach/arch.h>
> > > 
> > > @@ -99,12 +105,6 @@ struct amba_device gpio_device[] = {
> > > 
> > >  	}
> > >  
> > >  };
> > > 
> > > -/* This will add devices, and do machine specific tasks */
> > > -void __init spear6xx_init(void)
> > > -{
> > > -	/* nothing to do for now */
> > > -}
> > > -
> > > 
> > >  /* This will initialize vic */
> > >  void __init spear6xx_init_irq(void)
> > >  {
> > > 
> > > @@ -181,3 +181,60 @@ static void __init spear6xx_timer_init(void)
> > > 
> > >  struct sys_timer spear6xx_timer = {
> > >  
> > >  	.init = spear6xx_timer_init,
> > >  
> > >  };
> > > 
> > > +
> > > +/*
> > > + * Devicetree specific init structs/functions:
> > > + * Once the SPEAr600 devicetree support has matured, we can remove
> > > + * spear600_evb.c and the non-devicetree support above in this file.
> > > + */
> > > +
> > > +/*
> > > + * Add auxdata so that clock name matching doesn't fail in device
> > > + * drivers
> > > + */
> > > +struct of_dev_auxdata spear600_auxdata_lookup[] __initdata = {
> > > +	OF_DEV_AUXDATA("arm,pl011", SPEAR6XX_ICM1_UART0_BASE,
> > > +		       "uart0", NULL),
> > > +	OF_DEV_AUXDATA("arm,pl011", SPEAR6XX_ICM1_UART1_BASE,
> > > +		       "uart1", NULL),
> > > +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_CPU_GPIO_BASE,
> > > +		       "gpio0", NULL),
> > > +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_ICM3_GPIO_BASE,
> > > +		       "gpio1", NULL),
> > > +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_ICM2_GPIO_BASE,
> > > +		       "gpio2", NULL),
> > > +	OF_DEV_AUXDATA("snps,designware-i2c", SPEAR6XX_ICM1_I2C_BASE,
> > > +		       "i2c_designware.0", NULL),
> > 
> > update the clkdev no more OF_DEV_AUXDATA
> 
> That will break non-DT boards. We can change it in clkdev later, once DT 
> support has stabalized for SPEAr600. And remove all this then.
it will not just add new entry

as done on AT91 as example and requested for imx recently too

Best Regards,
J.


From notasas at gmail.com  Wed Mar 14 13:38:38 2012
From: notasas at gmail.com (Grazvydas Ignotas)
Date: Wed, 14 Mar 2012 19:38:38 +0200
Subject: [GIT PULL] cpufreq: OMAP updates for v3.4
In-Reply-To: <87wr6ngkrl.fsf@ti.com>
References: <87y5rci2na.fsf@ti.com>
 <CANOLnON91vXWb2L-FXjz3sqq-9j5SaEodtpt_yvFiN33D4Q3Ow@mail.gmail.com>
 <87wr6ngkrl.fsf@ti.com>
Message-ID: <CANOLnON+hHtnjo9samAqvXp_nVJMjQ7CnxMCe7ggO4UwYaz4rw@mail.gmail.com>

On Wed, Mar 14, 2012 at 7:22 PM, Kevin Hilman <khilman at ti.com> wrote:
> Grazvydas Ignotas <notasas at gmail.com> writes:
>
> [...]
>
>>> Russell King (1):
>>> ? ? ?cpufreq: OMAP driver depends CPUfreq tables
>>
>> It seems this one got messed up, it says "default ARCH_OMAP2PLUS"
>> instead of depends.
>
> That was intentional. ?What do you think is messed up about it?
>
> It's the same as saying:
>
> ? ? depends on ARCH_OMAP2PLUS
> ? ? default y

Hm, somehow I've never encountered this syntax, but it more looks like
it means "default y if ARCH_OMAP2PLUS" instead of that.

Checked this with menuconfig now:
  default ARCH_OMAP2PLUS
resolves to:
  ARCH_HAS_CPUFREQ [=y] && CPU_FREQ [=y] && ARM [=y]

..which might cause build break when OMAP is not selected, and

  depends on ARCH_OMAP2PLUS
  default y
resolves to:
  ARCH_HAS_CPUFREQ [=y] && CPU_FREQ [=y] && ARM [=y] && ARCH_OMAP2PLUS [=y]

..which should be randconfig friendly.

-- 
Gra?vydas


From mvs at tigris.de  Wed Mar 14 13:38:15 2012
From: mvs at tigris.de (Maximilian Schwerin)
Date: Wed, 14 Mar 2012 18:38:15 +0100
Subject: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting to add
 IVA OPP
Message-ID: <1331746695-24372-1-git-send-email-mvs@tigris.de>

From: Steve Sakoman <steve at sakoman.com>

Don't try to add IVA OPPs for OMAP3 versions not containing an IVA
subsystem, as this would make omap_init_opp_table fail.

Signed-off-by: Steve Sakoman <steve at sakoman.com>
Signed-off-by: Maximilian Schwerin <mvs at tigris.de>
---
 arch/arm/mach-omap2/opp.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index 9262a6b..414f2ec 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -62,6 +62,10 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
 				__func__, i);
 			return -EINVAL;
 		}
+
+		if ((strcmp(opp_def->hwmod_name,"iva") == 0) && !omap3_has_iva())
+			continue;
+
 		oh = omap_hwmod_lookup(opp_def->hwmod_name);
 		if (!oh || !oh->od) {
 			pr_warn("%s: no hwmod or odev for %s, [%d] "
-- 
1.7.0.4



From lee.jones at linaro.org  Wed Mar 14 13:39:41 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 14 Mar 2012 17:39:41 +0000
Subject: [PATCH v4 09/15] ARM: ux500: convert to twd_local_timer_register()
 interface
In-Reply-To: <CANmRt2gjhg-nznAOxQHA1g7EX+F4uEjp1nW5iT3Rtw4s8y5uGg@mail.gmail.com>
References: <1327061042-14857-1-git-send-email-marc.zyngier@arm.com>
 <1327061042-14857-10-git-send-email-marc.zyngier@arm.com>
 <CANmRt2gjhg-nznAOxQHA1g7EX+F4uEjp1nW5iT3Rtw4s8y5uGg@mail.gmail.com>
Message-ID: <4F60D7DD.50705@linaro.org>

On 14/03/12 17:12, Lee Jones wrote:
> Add support for the new smp_twd runtime registration interface
> to the ux500 platforms, and remove the old compile-time support.
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org
> <mailto:linus.walleij at linaro.org>>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com
> <mailto:marc.zyngier at arm.com>>
> ---
>  arch/arm/mach-ux500/Makefile     |    1 -
>  arch/arm/mach-ux500/cpu.c        |    1 -
>  arch/arm/mach-ux500/localtimer.c |   29 -----------------------------
>  arch/arm/mach-ux500/timer.c      |   32 +++++++++++++++++++++++++-------
>  4 files changed, 25 insertions(+), 38 deletions(-)
>  delete mode 100644 arch/arm/mach-ux500/localtimer.c
> 
> diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
> index 6bd2f45..35b3894 100644
> --- a/arch/arm/mach-ux500/Makefile
> +++ b/arch/arm/mach-ux500/Makefile
> @@ -15,7 +15,6 @@ obj-$(CONFIG_MACH_U8500)      += board-mop500.o
> board-mop500-sdi.o \
>  obj-$(CONFIG_MACH_U5500)       += board-u5500.o board-u5500-sdi.o
>  obj-$(CONFIG_SMP)              += platsmp.o headsmp.o
>  obj-$(CONFIG_HOTPLUG_CPU)      += hotplug.o
> -obj-$(CONFIG_LOCAL_TIMERS)     += localtimer.o
>  obj-$(CONFIG_U5500_MODEM_IRQ)  += modem-irq-db5500.o
>  obj-$(CONFIG_U5500_MBOX)       += mbox-db5500.o
> 
> diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
> index f418574..851308b 100644
> --- a/arch/arm/mach-ux500/cpu.c
> +++ b/arch/arm/mach-ux500/cpu.c
> @@ -14,7 +14,6 @@
> 
>  #include <asm/hardware/gic.h>
>  #include <asm/mach/map.h>
> -#include <asm/localtimer.h>
> 
>  #include <mach/hardware.h>
>  #include <mach/setup.h>
> diff --git a/arch/arm/mach-ux500/localtimer.c
> b/arch/arm/mach-ux500/localtimer.c
> deleted file mode 100644
> index 5ba1133..0000000
> --- a/arch/arm/mach-ux500/localtimer.c
> +++ /dev/null
> @@ -1,29 +0,0 @@
> -/*
> - * Copyright (C) 2008-2009 ST-Ericsson
> - * Srinidhi Kasagar <srinidhi.kasagar at stericsson.com
> <mailto:srinidhi.kasagar at stericsson.com>>
> - *
> - * This file is heavily based on relaview platform, almost a copy.
> - *
> - * Copyright (C) 2002 ARM Ltd.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -#include <linux/init.h>
> -#include <linux/smp.h>
> -#include <linux/clockchips.h>
> -
> -#include <asm/irq.h>
> -#include <asm/smp_twd.h>
> -#include <asm/localtimer.h>
> -
> -/*
> - * Setup the local clock events for a CPU.
> - */
> -int __cpuinit local_timer_setup(struct clock_event_device *evt)
> -{
> -       evt->irq = IRQ_LOCALTIMER;
> -       twd_timer_setup(evt);
> -       return 0;
> -}
> diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
> index aea467d..cadf982 100644
> --- a/arch/arm/mach-ux500/timer.c
> +++ b/arch/arm/mach-ux500/timer.c
> @@ -8,27 +8,44 @@
>  #include <linux/errno.h>
>  #include <linux/clksrc-dbx500-prcmu.h>
> 
> -#include <asm/localtimer.h>
> +#include <asm/smp_twd.h>
> 
>  #include <plat/mtu.h>
> 
>  #include <mach/setup.h>
>  #include <mach/hardware.h>
> 
> +#ifdef CONFIG_HAVE_ARM_TWD
> +static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer,
> +                             U5500_TWD_BASE, IRQ_LOCALTIMER);
> +static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
> +                             U8500_TWD_BASE, IRQ_LOCALTIMER);

I think you need to include 'mach/irqs.h' or similar for IRQ_LOCALTIMER.

> +
> +static void __init ux500_twd_init(void)
> +{
> +       struct twd_local_timer *twd_local_timer;
> +       int err;
> +
> +       twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer :
> +                                          &u8500_twd_local_timer;
> +
> +       err = twd_local_timer_register(twd_local_timer);
> +       if (err)
> +               pr_err("twd_local_timer_register failed %d\n", err);

Again, this is missing it's declaration from the above includes.

> +}
> +#else
> +#define ux500_twd_init()       do { } while(0)
> +#endif
> +
>  static void __init ux500_timer_init(void)
>  {
>        void __iomem *prcmu_timer_base;
> +       int err;

This appears to be unused.

>        if (cpu_is_u5500()) {
> -#ifdef CONFIG_LOCAL_TIMERS
> -               twd_base = __io_address(U5500_TWD_BASE);
> -#endif
>                mtu_base = __io_address(U5500_MTU0_BASE);
>                prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
>        } else if (cpu_is_u8500()) {
> -#ifdef CONFIG_LOCAL_TIMERS
> -               twd_base = __io_address(U8500_TWD_BASE);
> -#endif
>                mtu_base = __io_address(U8500_MTU0_BASE);
>                prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
>        } else {
> @@ -54,6 +71,7 @@ static void __init ux500_timer_init(void)
> 
>        nmdk_timer_init();
>        clksrc_dbx500_prcmu_init(prcmu_timer_base);
> +       ux500_twd_init();
>  }
> 
>  static void ux500_timer_reset(void)
> --
> 1.7.7.1

NAK: Won't build. :(

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From nicolas.ferre at atmel.com  Wed Mar 14 13:47:39 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 14 Mar 2012 18:47:39 +0100
Subject: [RFC PATCH] of: DMA helpers: manage generic requests specification
In-Reply-To: <20120305153648.GG27229@ponder.secretlab.ca>
References: <4F22DEF2.5000807@ti.com>
 <1330527248-4350-1-git-send-email-nicolas.ferre@atmel.com>
 <20120305153648.GG27229@ponder.secretlab.ca>
Message-ID: <4F60D9BB.9060709@atmel.com>

On 03/05/2012 04:36 PM, Grant Likely :
> On Wed, Feb 29, 2012 at 03:54:08PM +0100, Nicolas Ferre wrote:
>> By making DMA controllers register a generic translation
>> function, we allow the management of any type of DMA requests
>> specification.
>> The void * output of an of_dma_xlate() function that will be implemented
>> by the DMA controller can carry any type of "dma-request" argument.
>>
>> The DMA client will search its associated DMA controller in the list
>> and call the registered of_dam_xlate() function to retrieve the
>> request values.
>>
>> One simple xlate function is provided for the "single number" type
>> of request biding.
>>
>> This implementation is independent from dmaengine so it can also be
>> used by legacy drivers.
>>
>> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
>> Cc: Benoit Cousson <b-cousson at ti.com>
>> Cc: Stephen Warren <swarren at nvidia.com>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Cc: Russell King <linux at arm.linux.org.uk>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> ---
>> Hi all,
>>
>> Here are my thoughts about the DMA helpers for device tree.
>> This patch goes on top of Benoit's ones. My goal was to keep this separated
>> from any DMA infrastructure (dmaengine not needed, nor any other DMA
>> implementation).
>>
>> It is to keep the ball rolling, so do not hesitate to comment.
>>
>> Best regards,
>>
>>
>>  Documentation/devicetree/bindings/dma/dma.txt |   29 +++--
>>  drivers/of/dma.c                              |  161 ++++++++++++++++++++++---
>>  include/linux/of_dma.h                        |   33 +++++-
>>  3 files changed, 186 insertions(+), 37 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/dma.txt b/Documentation/devicetree/bindings/dma/dma.txt
>> index 7f2a301..c49e98d 100644
>> --- a/Documentation/devicetree/bindings/dma/dma.txt
>> +++ b/Documentation/devicetree/bindings/dma/dma.txt
>> @@ -6,9 +6,8 @@ DMA request line that goes from an IP to a DMA controller.
>>  
>>  * DMA controller
>>  
>> -Required properties:
>> -    - dma-controller: Mark the device as a DMA controller
>> -    - #dma-cells: Number of cell for each DMA line, must be one.
>> +Required property:
>> +    - #dma-cells: Number of cells for each DMA line.
>>  
>>  
>>  Example:
>> @@ -17,7 +16,6 @@ Example:
>>  		compatible = "ti,sdma-omap4"
>>  		reg = <0x48000000 0x1000>;
>>  		interrupts = <12>;
>> -        dma-controller;
>>  		#dma-cells = <1>;
>>  	};
>>  
>> @@ -25,20 +23,23 @@ Example:
>>  
>>  * DMA client
>>  
>> -Client drivers should specify the DMA request numbers using a phandle to
>> -the controller + the DMA request number on that controller.
>> +Client drivers should specify the DMA request property using a phandle to
>> +the controller. If needed, the DMA request identity on that controller is then
>> +added followed by optional request specifications.
>>  
>> -Required properties:
>> -    - dma-request: List of pair phandle + dma-request per line
>> +Required property:
>> +    - dma-request: List of phandle + dma-request + request specifications,
>> +      one group per request "line".
>> +Optional property:
>>      - dma-request-names: list of strings in the same order as the dma-request
>>        in the dma-request property.
>>  
>>  
>>  Example:
>>  
>> -    i2c1: i2c at 1 {
>> -        ...
>> -        dma-request = <&sdma 2 &sdma 3>;
>> -        dma-request-names = "tx", "rx";
>> -        ...
>> -    };
>> +	i2c1: i2c at 1 {
>> +		...
>> +		dma-request = <&sdma 2 &sdma 3>;
>> +		dma-request-names = "tx", "rx";
>> +		...
>> +	};
>> diff --git a/drivers/of/dma.c b/drivers/of/dma.c
>> index d4927e2..e0c6fd9 100644
>> --- a/drivers/of/dma.c
>> +++ b/drivers/of/dma.c
>> @@ -13,41 +13,145 @@
>>  #include <linux/device.h>
>>  #include <linux/err.h>
>>  #include <linux/module.h>
>> +#include <linux/rculist.h>
>> +#include <linux/slab.h>
>>  #include <linux/of.h>
>>  #include <linux/of_dma.h>
>>  
>> +static LIST_HEAD(of_dma_list);
>> +
>> +/**
>> + * of_dma_find_controller() - Find a DMA controller in DT DMA helpers list
>> + * @np:		device node of DMA controller
>> + */
>> +static struct of_dma *of_dma_find_controller(struct device_node *np)
>> +{
>> +	struct of_dma	*ofdma;
>> +
>> +	list_for_each_entry_rcu(ofdma, &of_dma_list, of_dma_controllers) {
>> +		if (ofdma->of_node == np)
>> +			return ofdma;
>> +	}
>> +
>> +	return NULL;
>> +}
>> +
>>  /**
>> - * of_get_dma_request() - Get a DMA request number and dma-controller node
>> + * of_dma_controller_register() - Register a DMA controller to DT DMA helpers
>> + * @np:			device node of DMA controller
>> + * @of_dma_xlate:	generic translation function which converts a phandle
>> + *			arguments list into a generic output value
>> + *
>> + * Returns 0 on success or appropriate errno value on error.
>> + *
>> + * If #dma-cells is not specified in DMA controller device tree node, we assume
>> + * that the DMA controller phandle will come without argument.
>> + *
>> + * Allocated memory sould be freed with apropriate of_dma_controller_free()
>> + * call.
>> + */
>> +int of_dma_controller_register(struct device_node *np,
>> +			int (*of_dma_xlate)(struct of_phandle_args *, void *))
>> +{
>> +	struct of_dma	*ofdma;
>> +	int		*nbcells;
>> +
>> +	if (!np || !of_dma_xlate) {
>> +		pr_err("%s: not enouth information provided\n", __func__);
>> +		return -EINVAL;
>> +	}
>> +
>> +	ofdma = kzalloc(sizeof(*ofdma), GFP_KERNEL);
>> +	if (!ofdma)
>> +		return -ENOMEM;
>> +
>> +	nbcells = (int *)of_get_property(np, "#dma-cells", NULL);
> 
> No cast required; but nbcells should be a (const __be32 *) instead of an int*.
> 
>> +	if (!nbcells)
>> +		/*
>> +		 * no #dma-cells properties: assume no argument to
>> +		 * dma-request property on slave side
>> +		 */
>> +		ofdma->of_dma_n_cells = 0;
>> +	else
>> +		ofdma->of_dma_n_cells = be32_to_cpup(nbcells);
>> +
>> +	ofdma->of_node = np;
>> +	ofdma->of_dma_xlate = of_dma_xlate;
>> +
>> +	/* Now queue of_dma controller structure in list */
>> +	list_add_tail_rcu(&ofdma->of_dma_controllers, &of_dma_list);
>> +
>> +	return 0;
>> +}
>> +EXPORT_SYMBOL(of_dma_controller_register);
> 
> EXPORT_SYMBOL_GPL
> 
>> +
>> +/**
>> + * of_dma_controller_free() - Remove a DMA controller from DT DMA helpers list
>> + * @np:		device node of DMA controller
>> + *
>> + * Memory allocated by of_dma_controller_register() is freed here.
>> + */
>> +void of_dma_controller_free(struct device_node *np)
>> +{
>> +	struct of_dma	*ofdma;
>> +
>> +	ofdma = of_dma_find_controller(np);
>> +	if (ofdma) {
>> +		list_del_rcu(&ofdma->of_dma_controllers);
>> +		kfree(ofdma);
>> +	}
>> +}
>> +EXPORT_SYMBOL(of_dma_controller_free);
>> +
>> +/**
>> + * of_get_dma_request() - Get the associated DMA request data
>>   * @np:		device node to get DMA request from
>> - * @propname:	property name containing DMA specifier(s)
>>   * @index:	index of the DMA request
>> - * @ctrl_np:	a device_node pointer to fill in
>> + * @out_data:	a output that can be filled in by the of_dma_xlate() function
>>   *
>> - * Returns DMA number along to the dma controller node, or one of the errno
>> - * value on the error condition. If @ctrl_np is not NULL the function also
>> - * fills in the DMA controller device_node pointer.
>> + * Returns return value of of_dma_xlate() and fills out_data (if provided).
>> + * On error returns the appropriate errno value.
>>   */
>>  int of_get_dma_request(struct device_node *np, int index,
>> -		       struct device_node **ctrl_np)
>> +		       void *out_data)
>>  {
>> -	int ret = -EINVAL;
>> -	struct of_phandle_args dma_spec;
>> +	struct of_phandle_args	dma_spec;
>> +	struct of_dma		*ofdma;
>> +	int			ret;
>>  
>>  	ret = of_parse_phandle_with_args(np, "dma-request", "#dma-cells",
>>  					 index, &dma_spec);
>>  	if (ret) {
>> -		pr_debug("%s: can't parse dma property\n", __func__);
>> +		pr_err("%s: can't parse dma property\n", np->full_name);
>>  		goto err0;
>>  	}
>>  
>> -	if (dma_spec.args_count > 0)
>> -		ret = dma_spec.args[0];
>> +	if (list_empty(&of_dma_list)) {
>> +		pr_debug("%s: empty DMA controller list\n",
>> +			 np->full_name);
>> +		ret = -ENOENT;
>> +		goto err1;
>> +	}
>>  
>> -	if (ctrl_np)
>> -		*ctrl_np = dma_spec.np;
>> -	else
>> -		of_node_put(dma_spec.np);
>> +	ofdma = of_dma_find_controller(dma_spec.np);
>> +	if (!ofdma) {
>> +		pr_debug("%s: DMA controller %s isn't registered\n",
>> +			 np->full_name, dma_spec.np->full_name);
>> +		ret = -ENODEV;
>> +		goto err1;
>> +	}
>>  
>> +	if (dma_spec.args_count != ofdma->of_dma_n_cells) {
>> +		pr_debug("%s: wrong #dma-cells for %s\n",
>> +			 np->full_name, dma_spec.np->full_name);
>> +		ret = -EINVAL;
>> +		goto err1;
>> +	}
>> +
>> +	ret = ofdma->of_dma_xlate(&dma_spec, out_data);
>> +
>> +err1:
>> +	of_node_put(dma_spec.np);
>>  err0:
>>  	pr_debug("%s exited with status %d\n", __func__, ret);
>>  	return ret;
>> @@ -55,6 +159,24 @@ err0:
>>  EXPORT_SYMBOL(of_get_dma_request);
>>  
>>  /**
>> + * of_dma_xlate_onenumbercell() - Generic DMA xlate for direct one cell bindings
>> + *
>> + * Device Tree DMA translation function which works with one cell bindings
>> + * where the cell values map directly to the hardware request number understood
>> + * by the DMA controller.
>> + */
>> +int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec, void *req_nbr)
>> +{
>> +	if (!dma_spec)
>> +		return -EINVAL;
>> +	if (WARN_ON(dma_spec->args_count != 1))
>> +		return -EINVAL;
>> +	*(int *)req_nbr = dma_spec->args[0];
>> +	return 0;
>> +}
>> +EXPORT_SYMBOL(of_dma_xlate_onenumbercell);
>> +
>> +/**
>>   * of_dma_count - Count DMA requests for a device
>>   * @np:		device node to count DMAs for
>>   *
>> @@ -105,13 +227,14 @@ int of_dma_to_resource(struct device_node *dev, int index, struct resource *r)
>>  {
>>  	const char *name = NULL;
>>  	int dma;
>> +	int ret;
>>  
>>  	if (!r)
>>  		return -EINVAL;
>>  
>> -	dma = of_get_dma_request(dev, index, NULL);
>> -	if (dma < 0)
>> -		return dma;
>> +	ret = of_get_dma_request(dev, index, &dma);
>> +	if (ret < 0)
>> +		return ret;
>>  
>>  	/*
>>  	 * Get optional "dma-request-names" property to add a name
>> diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
>> index 575163d..fbf98de 100644
>> --- a/include/linux/of_dma.h
>> +++ b/include/linux/of_dma.h
>> @@ -17,18 +17,38 @@
>>  
>>  struct device_node;
>>  
>> -#ifdef CONFIG_OF_GPIO
>> +#ifdef CONFIG_OF_DMA
>>  
>> +struct of_dma {
>> +	struct list_head of_dma_controllers;
>> +	struct device_node *of_node;
>> +	int of_dma_n_cells;
>> +	int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
>> +};
> 
> The api makes struct of_dma private; so this should be moved to the .c
> file.
> 
> Otherwise, this looks okay to me.

Hi Grant and Stephen,

I plan to resend a squashed version of Benoit's patch and mine about
those DMA helpers (we talked about this with Benoit). I tried to address
all remarks by Benoit and Grant.

I do have the will to avoid the treats of memory corruption in case of
malformed DT data, as Stephen was saying. But, on the other hand I do
not know really if this can happen: if the .xlate() function which is
provided by the DMA controller is well written, it should check for
proper args_count or maximum string size. I do not have the feeling that
adding an enum will enforce the security here.

Do you know a way to enforce security of this "void *" parameter or the
check of number of cells + the due diligence of .xlate() function
writers will be enough?

Best regards,
-- 
Nicolas Ferre


From davej at redhat.com  Wed Mar 14 13:57:03 2012
From: davej at redhat.com (Dave Jones)
Date: Wed, 14 Mar 2012 13:57:03 -0400
Subject: [PATCH v2 RE-SEND] [CPUFREQ] EXYNOS5250: Add support cpufreq for
 EXYNOS5250
In-Reply-To: <4F60D5FE.7080400@samsung.com>
References: <1331377202-25173-1-git-send-email-kgene.kim@samsung.com>
 <4F60D5FE.7080400@samsung.com>
Message-ID: <20120314175703.GA3803@redhat.com>

On Wed, Mar 14, 2012 at 10:31:42AM -0700, Kukjin Kim wrote:
 > Kukjin Kim wrote:
 > > From: Jaecheol Lee<jc.lee at samsung.com>
 > > 
 > > This patch adds support cpufreq for EXYNOS5250 SoC. Basically,
 > > the exynos-cpufreq.c is used commonly and exynos5250-cpufreq.c
 > > is used for EXYNOS5250(two Cortex-A15 cores) SoC.
 > > 
 > > Signed-off-by: Jaecheol Lee<jc.lee at samsung.com>
 > > Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
 > 
 > Hi again Dave :)
 > 
 > Please pick up this patch for v3.4.
 > If any problems, please kindly let us know.

this, and the other patch doesn't apply against current cpufreq.git

patching file arch/arm/mach-exynos/include/mach/cpufreq.h
patching file drivers/cpufreq/Kconfig.arm
Hunk #1 succeeded at 30 (offset -17 lines).
Hunk #2 succeeded at 43 (offset -18 lines).
patching file drivers/cpufreq/Makefile
Hunk #1 FAILED at 45.
1 out of 1 hunk FAILED -- saving rejects to file drivers/cpufreq/Makefile.rej
patching file drivers/cpufreq/exynos-cpufreq.c
Hunk #1 succeeded at 252 (offset -2 lines).
patching file drivers/cpufreq/exynos4x12-cpufreq.c
patching file arch/arm/mach-exynos/include/mach/cpufreq.h
Hunk #1 FAILED at 33.
1 out of 1 hunk FAILED -- saving rejects to file arch/arm/mach-exynos/include/mach/cpufreq.h.rej
patching file drivers/cpufreq/Kconfig.arm
Hunk #1 FAILED at 48.
Hunk #2 FAILED at 67.
2 out of 2 hunks FAILED -- saving rejects to file drivers/cpufreq/Kconfig.arm.rej
patching file drivers/cpufreq/Makefile
Hunk #1 FAILED at 46.
1 out of 1 hunk FAILED -- saving rejects to file drivers/cpufreq/Makefile.rej
patching file drivers/cpufreq/exynos-cpufreq.c
Hunk #1 FAILED at 256.
1 out of 1 hunk FAILED -- saving rejects to file drivers/cpufreq/exynos-cpufreq.c.rej
patching file drivers/cpufreq/exynos5250-cpufreq.c

	Dave



From swarren at wwwdotorg.org  Wed Mar 14 14:16:16 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 14 Mar 2012 12:16:16 -0600
Subject: [RFC PATCH] of: DMA helpers: manage generic requests specification
In-Reply-To: <4F60D9BB.9060709@atmel.com>
References: <4F22DEF2.5000807@ti.com>
 <1330527248-4350-1-git-send-email-nicolas.ferre@atmel.com>
 <20120305153648.GG27229@ponder.secretlab.ca> <4F60D9BB.9060709@atmel.com>
Message-ID: <4F60E070.8040003@wwwdotorg.org>

On 03/14/2012 11:47 AM, Nicolas Ferre wrote:
...
> I do have the will to avoid the treats of memory corruption in case of
> malformed DT data, as Stephen was saying. But, on the other hand I do
> not know really if this can happen: if the .xlate() function which is
> provided by the DMA controller is well written, it should check for
> proper args_count or maximum string size. I do not have the feeling that
> adding an enum will enforce the security here.
> 
> Do you know a way to enforce security of this "void *" parameter or the
> check of number of cells + the due diligence of .xlate() function
> writers will be enough?

I guess if the only source of the data is a driver's of_xlate function,
and it's only being passed back to that same driver and never
interpreted elsewhere, then its probably reasonable to assume that's
enough for safety.


From s.hauer at pengutronix.de  Wed Mar 14 14:23:45 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 14 Mar 2012 19:23:45 +0100
Subject: [PATCH v6 3/3] clk: basic clock hardware types
In-Reply-To: <1331366064-1273-4-git-send-email-mturquette@linaro.org>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-4-git-send-email-mturquette@linaro.org>
Message-ID: <20120314182345.GB29317@pengutronix.de>

On Fri, Mar 09, 2012 at 11:54:24PM -0800, Mike Turquette wrote:
> Many platforms support simple gateable clocks, fixed-rate clocks,
> adjustable divider clocks and multi-parent multiplexer clocks.
> 
> This patch introduces basic clock types for the above-mentioned hardware
> which share some common characteristics.
> 
> Based on original work by Jeremy Kerr and contribution by Jamie Iles.
> Dividers and multiplexor clocks originally contributed by Richard Zhao &
> Sascha Hauer.
> 
> Signed-off-by: Mike Turquette <mturquette at linaro.org>
> Signed-off-by: Mike Turquette <mturquette at ti.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Shawn Guo <shawn.guo at freescale.com>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Jamie Iles <jamie at jamieiles.com>
> Cc: Richard Zhao <richard.zhao at linaro.org>
> Cc: Saravana Kannan <skannan at codeaurora.org>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Stephen Boyd <sboyd at codeaurora.org>
> Cc: Amit Kucheria <amit.kucheria at linaro.org>
> Cc: Deepak Saxena <dsaxena at linaro.org>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Andrew Lunn <andrew at lunn.ch>
> ---
> Changes since v5:
>  * standardized the hw-specific locking in the basic clock types
>  * export the individual ops for each basic clock type
>  * improve registration for single-parent basic clocks (thanks Sascha)
>  * fixed bugs in gate clock's static initializers (thanks Andrew)
> 
>  drivers/clk/Makefile         |    3 +-
>  drivers/clk/clk-divider.c    |  204 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/clk/clk-fixed-rate.c |   82 +++++++++++++++++
>  drivers/clk/clk-gate.c       |  157 ++++++++++++++++++++++++++++++++
>  drivers/clk/clk-mux.c        |  123 +++++++++++++++++++++++++
>  include/linux/clk-private.h  |  124 +++++++++++++++++++++++++
>  include/linux/clk-provider.h |  127 ++++++++++++++++++++++++++
>  7 files changed, 819 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/clk/clk-divider.c
>  create mode 100644 drivers/clk/clk-fixed-rate.c
>  create mode 100644 drivers/clk/clk-gate.c
>  create mode 100644 drivers/clk/clk-mux.c
> 
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index ff362c4..1f736bc 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -1,3 +1,4 @@
>  
>  obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
> -obj-$(CONFIG_COMMON_CLK)	+= clk.o
> +obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
> +				   clk-mux.o clk-divider.o
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> new file mode 100644
> index 0000000..c0c4e0b
> --- /dev/null
> +++ b/drivers/clk/clk-divider.c
> @@ -0,0 +1,204 @@
> +/*
> + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
> + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Adjustable divider clock implementation
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/string.h>
> +
> +/*
> + * DOC: basic adjustable divider clock that cannot gate
> + *
> + * Traits of this clock:
> + * prepare - clk_prepare only ensures that parents are prepared
> + * enable - clk_enable only ensures that parents are enabled
> + * rate - rate is adjustable.  clk->rate = parent->rate / divisor
> + * parent - fixed parent.  No clk_set_parent support
> + */
> +
> +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
> +
> +static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> +		unsigned long parent_rate)
> +{
> +	struct clk_divider *divider = to_clk_divider(hw);
> +	unsigned int div;
> +	unsigned long flags = 0;
> +
> +	if (divider->lock)
> +		spin_lock_irqsave(divider->lock, flags);
> +
> +	div = readl(divider->reg) >> divider->shift;
> +	div &= (1 << divider->width) - 1;
> +
> +	if (divider->lock)
> +		spin_unlock_irqrestore(divider->lock, flags);
> +
> +	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
> +		div++;
> +
> +	return parent_rate / div;
> +}
> +EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
> +
> +static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
> +		unsigned long *best_parent_rate)
> +{
> +	struct clk_divider *divider = to_clk_divider(hw);
> +	int i, bestdiv = 0;
> +	unsigned long parent_rate, best = 0, now, maxdiv;
> +
> +	maxdiv = (1 << divider->width);

We need a check for rate == 0 here:

	if (rate == 0)
		rate = 1;

Otherwise we divide by zero below.

> +
> +	if (divider->flags & CLK_DIVIDER_ONE_BASED)
> +		maxdiv--;
> +
> +	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
> +		parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
> +		bestdiv = parent_rate / rate;

It's a bit strange but due to integer maths you must use DIV_ROUND_UP
in round_rate and div = parent_rate / rate in set_rate.

Example:

parent_rate = 100
rate = 34

Now the best divider would be 3 (100/3 = 33), but the above
results in 2. With DIV_ROUND_UP round_rate correctly returns
33. Now when you use DIV_ROUND_UP in set_rate the resulting
divider would be 4 which is wrong whereas 100/33 returns the correct
result.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From kgene.kim at samsung.com  Wed Mar 14 14:24:28 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 11:24:28 -0700
Subject: [PATCH v2 RE-SEND] [CPUFREQ] EXYNOS5250: Add support cpufreq
 for EXYNOS5250
In-Reply-To: <20120314175703.GA3803@redhat.com>
References: <1331377202-25173-1-git-send-email-kgene.kim@samsung.com>
 <4F60D5FE.7080400@samsung.com> <20120314175703.GA3803@redhat.com>
Message-ID: <4F60E25C.9060005@samsung.com>

2012-03-14 ?? 10:57, Dave Jones ? ?:
> On Wed, Mar 14, 2012 at 10:31:42AM -0700, Kukjin Kim wrote:
>   >  Kukjin Kim wrote:
>   >  >  From: Jaecheol Lee<jc.lee at samsung.com>
>   >  >
>   >  >  This patch adds support cpufreq for EXYNOS5250 SoC. Basically,
>   >  >  the exynos-cpufreq.c is used commonly and exynos5250-cpufreq.c
>   >  >  is used for EXYNOS5250(two Cortex-A15 cores) SoC.
>   >  >
>   >  >  Signed-off-by: Jaecheol Lee<jc.lee at samsung.com>
>   >  >  Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
>   >
>   >  Hi again Dave :)
>   >
>   >  Please pick up this patch for v3.4.
>   >  If any problems, please kindly let us know.
>
> this, and the other patch doesn't apply against current cpufreq.git
>
Oops, maybe you applied this first. Pleae try again EXYNOS4X12 first 
then, this. I applied on top of cpufreq/next and there was no complain.

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


> patching file arch/arm/mach-exynos/include/mach/cpufreq.h
> patching file drivers/cpufreq/Kconfig.arm
> Hunk #1 succeeded at 30 (offset -17 lines).
> Hunk #2 succeeded at 43 (offset -18 lines).
> patching file drivers/cpufreq/Makefile
> Hunk #1 FAILED at 45.
> 1 out of 1 hunk FAILED -- saving rejects to file drivers/cpufreq/Makefile.rej
> patching file drivers/cpufreq/exynos-cpufreq.c
> Hunk #1 succeeded at 252 (offset -2 lines).
> patching file drivers/cpufreq/exynos4x12-cpufreq.c
> patching file arch/arm/mach-exynos/include/mach/cpufreq.h
> Hunk #1 FAILED at 33.
> 1 out of 1 hunk FAILED -- saving rejects to file arch/arm/mach-exynos/include/mach/cpufreq.h.rej
> patching file drivers/cpufreq/Kconfig.arm
> Hunk #1 FAILED at 48.
> Hunk #2 FAILED at 67.
> 2 out of 2 hunks FAILED -- saving rejects to file drivers/cpufreq/Kconfig.arm.rej
> patching file drivers/cpufreq/Makefile
> Hunk #1 FAILED at 46.
> 1 out of 1 hunk FAILED -- saving rejects to file drivers/cpufreq/Makefile.rej
> patching file drivers/cpufreq/exynos-cpufreq.c
> Hunk #1 FAILED at 256.
> 1 out of 1 hunk FAILED -- saving rejects to file drivers/cpufreq/exynos-cpufreq.c.rej
> patching file drivers/cpufreq/exynos5250-cpufreq.c



From ccross at android.com  Wed Mar 14 14:29:51 2012
From: ccross at android.com (Colin Cross)
Date: Wed, 14 Mar 2012 11:29:51 -0700
Subject: [PATCHv2 2/5] cpuidle: fix error handling in __cpuidle_register_device
In-Reply-To: <1331749794-8056-1-git-send-email-ccross@android.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
Message-ID: <1331749794-8056-3-git-send-email-ccross@android.com>

Fix the error handling in __cpuidle_register_device to include
the missing list_del.  Move it to a label, which will simplify
the error handling when coupled states are added.

Signed-off-by: Colin Cross <ccross at android.com>
---
 drivers/cpuidle/cpuidle.c |   13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

v2:
   * fix after rename of sys_dev to cpu_dev
   * reorder error path to reverse of probe path

diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index 1453830..aacf2f0 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -319,13 +319,18 @@ static int __cpuidle_register_device(struct cpuidle_device *dev)
 
 	per_cpu(cpuidle_devices, dev->cpu) = dev;
 	list_add(&dev->device_list, &cpuidle_detected_devices);
-	if ((ret = cpuidle_add_sysfs(cpu_dev))) {
-		module_put(cpuidle_driver->owner);
-		return ret;
-	}
+	ret = cpuidle_add_sysfs(cpu_dev);
+	if (ret)
+		goto err_sysfs;
 
 	dev->registered = 1;
 	return 0;
+
+err_sysfs:
+	list_del(&dev->device_list);
+	per_cpu(cpuidle_devices, dev->cpu) = NULL;
+	module_put(cpuidle_driver->owner);
+	return ret;
 }
 
 /**
-- 
1.7.9.2



From ccross at android.com  Wed Mar 14 14:29:50 2012
From: ccross at android.com (Colin Cross)
Date: Wed, 14 Mar 2012 11:29:50 -0700
Subject: [PATCHv2 1/5] cpuidle: refactor out cpuidle_enter_state
In-Reply-To: <1331749794-8056-1-git-send-email-ccross@android.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
Message-ID: <1331749794-8056-2-git-send-email-ccross@android.com>

Split the code to enter a state and update the stats into a helper
function, cpuidle_enter_state, and export it.  This function will
be called by the coupled state code to handle entering the safe
state and the final coupled state.

Signed-off-by: Colin Cross <ccross at android.com>
---
 drivers/cpuidle/cpuidle.c |   44 ++++++++++++++++++++++++++++++--------------
 drivers/cpuidle/cpuidle.h |    2 ++
 2 files changed, 32 insertions(+), 14 deletions(-)

v2:
   * fixed kerneldoc comment format

diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index 59f4261..1453830 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -54,6 +54,35 @@ static void cpuidle_kick_cpus(void) {}
 static int __cpuidle_register_device(struct cpuidle_device *dev);
 
 /**
+ * cpuidle_enter_state - enter the state and update stats
+ * @dev: cpuidle device for this cpu
+ * @drv: cpuidle driver for this cpu
+ * @next_state: index into drv->states of the state to enter
+ */
+int cpuidle_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv,
+		int next_state)
+{
+	int entered_state;
+	struct cpuidle_state *target_state;
+
+	target_state = &drv->states[next_state];
+
+	entered_state = target_state->enter(dev, drv, next_state);
+
+	if (entered_state >= 0) {
+		/* Update cpuidle counters */
+		/* This can be moved to within driver enter routine
+		 * but that results in multiple copies of same code.
+		 */
+		dev->states_usage[entered_state].time +=
+				(unsigned long long)dev->last_residency;
+		dev->states_usage[entered_state].usage++;
+	}
+
+	return entered_state;
+}
+
+/**
  * cpuidle_idle_call - the main idle loop
  *
  * NOTE: no locks or semaphores should be used here
@@ -63,7 +92,6 @@ int cpuidle_idle_call(void)
 {
 	struct cpuidle_device *dev = __this_cpu_read(cpuidle_devices);
 	struct cpuidle_driver *drv = cpuidle_get_driver();
-	struct cpuidle_state *target_state;
 	int next_state, entered_state;
 
 	if (off)
@@ -92,26 +120,14 @@ int cpuidle_idle_call(void)
 		return 0;
 	}
 
-	target_state = &drv->states[next_state];
-
 	trace_power_start(POWER_CSTATE, next_state, dev->cpu);
 	trace_cpu_idle(next_state, dev->cpu);
 
-	entered_state = target_state->enter(dev, drv, next_state);
+	entered_state = cpuidle_enter_state(dev, drv, next_state);
 
 	trace_power_end(dev->cpu);
 	trace_cpu_idle(PWR_EVENT_EXIT, dev->cpu);
 
-	if (entered_state >= 0) {
-		/* Update cpuidle counters */
-		/* This can be moved to within driver enter routine
-		 * but that results in multiple copies of same code.
-		 */
-		dev->states_usage[entered_state].time +=
-				(unsigned long long)dev->last_residency;
-		dev->states_usage[entered_state].usage++;
-	}
-
 	/* give the governor an opportunity to reflect on the outcome */
 	if (cpuidle_curr_governor->reflect)
 		cpuidle_curr_governor->reflect(dev, entered_state);
diff --git a/drivers/cpuidle/cpuidle.h b/drivers/cpuidle/cpuidle.h
index 7db1866..d8a3ccc 100644
--- a/drivers/cpuidle/cpuidle.h
+++ b/drivers/cpuidle/cpuidle.h
@@ -14,6 +14,8 @@ extern struct list_head cpuidle_detected_devices;
 extern struct mutex cpuidle_lock;
 extern spinlock_t cpuidle_driver_lock;
 extern int cpuidle_disabled(void);
+extern int cpuidle_enter_state(struct cpuidle_device *dev,
+		struct cpuidle_driver *drv, int next_state);
 
 /* idle loop */
 extern void cpuidle_install_idle_handler(void);
-- 
1.7.9.2



From ccross at android.com  Wed Mar 14 14:29:49 2012
From: ccross at android.com (Colin Cross)
Date: Wed, 14 Mar 2012 11:29:49 -0700
Subject: [PATCHv2 0/5] coupled cpuidle state support
Message-ID: <1331749794-8056-1-git-send-email-ccross@android.com>

On some ARM SMP SoCs (OMAP4460, Tegra 2, and probably more), the
cpus cannot be independently powered down, either due to
sequencing restrictions (on Tegra 2, cpu 0 must be the last to
power down), or due to HW bugs (on OMAP4460, a cpu powering up
will corrupt the gic state unless the other cpu runs a work
around).  Each cpu has a power state that it can enter without
coordinating with the other cpu (usually Wait For Interrupt, or
WFI), and one or more "coupled" power states that affect blocks
shared between the cpus (L2 cache, interrupt controller, and
sometimes the whole SoC).  Entering a coupled power state must
be tightly controlled on both cpus.

The easiest solution to implementing coupled cpu power states is
to hotplug all but one cpu whenever possible, usually using a
cpufreq governor that looks at cpu load to determine when to
enable the secondary cpus.  This causes problems, as hotplug is an
expensive operation, so the number of hotplug transitions must be
minimized, leading to very slow response to loads, often on the
order of seconds.

This patch series implements an alternative solution, where each
cpu will wait in the WFI state until all cpus are ready to enter
a coupled state, at which point the coupled state function will
be called on all cpus at approximately the same time.

Once all cpus are ready to enter idle, they are woken by an smp
cross call.  At this point, there is a chance that one of the
cpus will find work to do, and choose not to enter suspend.  A
final pass is needed to guarantee that all cpus will call the
power state enter function at the same time.  During this pass,
each cpu will increment the ready counter, and continue once the
ready counter matches the number of online coupled cpus.  If any
cpu exits idle, the other cpus will decrement their counter and
retry.

To use coupled cpuidle states, a cpuidle driver must:

   Set struct cpuidle_device.coupled_cpus to the mask of all
   coupled cpus, usually the same as cpu_possible_mask if all cpus
   are part of the same cluster.  The coupled_cpus mask must be
   set in the struct cpuidle_device for each cpu.

   Set struct cpuidle_device.safe_state to a state that is not a
   coupled state.  This is usually WFI.

   Set CPUIDLE_FLAG_COUPLED in struct cpuidle_state.flags for each
   state that affects multiple cpus.

   Provide a struct cpuidle_state.enter function for each state
   that affects multiple cpus.  This function is guaranteed to be
   called on all cpus at approximately the same time.  The driver
   should ensure that the cpus all abort together if any cpu tries
   to abort once the function is called.

This series has been tested by implementing a test cpuidle state
that uses the parallel barrier helper function to verify that
all cpus call the function at the same time.

This patch set has a few disadvantages over the hotplug governor,
but I think they are all fairly minor:
   * Worst-case interrupt latency can be increased.  If one cpu
     receives an interrupt while the other is spinning in the
     ready_count loop, the second cpu will be stuck with
     interrupts off until the first cpu finished processing
     its interrupt and exits idle.  This will increase the worst
     case interrupt latency by the worst-case interrupt processing
     time, but should be very rare.
   * Interrupts are processed while still inside pm_idle.
     Normally, interrupts are only processed at the very end of
     pm_idle, just before it returns to the idle loop.  Coupled
     states requires processing interrupts inside
     cpuidle_enter_state_coupled in order to distinguish between
     the smp_cross_call from another cpu that is now idle and an
     interrupt that should cause idle to exit.
     I don't see a way to fix this without either being able to
     read the next pending irq from the interrupt chip, or
     querying the irq core for which interrupts were processed.
   * Since interrupts are processed inside cpuidle, the next
     timer event could change.  The new timer event will be
     handled correctly, but the idle state decision made by
     the governor will be out of date, and will not be revisited.
     The governor select function could be called again every time,
     but this could lead to a lot of work being done by an idle
     cpu if the other cpu was mostly busy.

v2:
   * removed the coupled lock, replacing it with atomic counters
   * added a check for outstanding pokes before beginning the
     final transition to avoid extra wakeups
   * made the cpuidle_coupled struct completely private
   * fixed kerneldoc comment formatting
   * added a patch with a helper function for resynchronizing
     cpus after aborting idle
   * added a patch (not for merging) to add trace events for
     verification and performance testing


From ccross at android.com  Wed Mar 14 14:29:54 2012
From: ccross at android.com (Colin Cross)
Date: Wed, 14 Mar 2012 11:29:54 -0700
Subject: [PATCHv2 5/5] cpuidle: coupled: add trace events
In-Reply-To: <1331749794-8056-1-git-send-email-ccross@android.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
Message-ID: <1331749794-8056-6-git-send-email-ccross@android.com>

Adds trace events to allow debugging of coupled cpuidle.
Can be used to verify cpuidle performance, including time spent
spinning and time spent in safe states.  Not intended for merging.

Signed-off-by: Colin Cross <ccross at android.com>
---
 drivers/cpuidle/coupled.c      |   48 +++++++-
 include/trace/events/cpuidle.h |  243 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 287 insertions(+), 4 deletions(-)
 create mode 100644 include/trace/events/cpuidle.h

diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
index 188a53f..3bc8a02 100644
--- a/drivers/cpuidle/coupled.c
+++ b/drivers/cpuidle/coupled.c
@@ -15,10 +15,12 @@
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  */
+#define DEBUG
 
 #include <linux/kernel.h>
 #include <linux/cpu.h>
 #include <linux/cpuidle.h>
+#include <linux/delay.h>
 #include <linux/mutex.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
@@ -26,6 +28,11 @@
 
 #include "cpuidle.h"
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/cpuidle.h>
+
+atomic_t cpuidle_trace_seq;
+
 /*
  * coupled cpuidle states
  *
@@ -154,20 +161,33 @@ static cpumask_t cpuidle_coupled_poked_mask;
 void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a)
 {
 	int n = atomic_read(&dev->coupled->alive_count);
+#ifdef DEBUG
+	int loops = 0;
+#endif
 
 	smp_mb__before_atomic_inc();
 	atomic_inc(a);
 
-	while (atomic_read(a) < n)
+	while (atomic_read(a) < n) {
+#ifdef DEBUG
+		BUG_ON(loops++ > loops_per_jiffy);
+#else
 		cpu_relax();
+#endif
+	}
 
 	if (atomic_inc_return(a) == n * 2) {
 		atomic_set(a, 0);
 		return;
 	}
 
-	while (atomic_read(a) > n)
+	while (atomic_read(a) > n) {
+#ifdef DEBUG
+		BUG_ON(loops++ > loops_per_jiffy);
+#else
 		cpu_relax();
+#endif
+	}
 }
 
 /**
@@ -232,6 +252,7 @@ static inline int cpuidle_coupled_get_state(struct cpuidle_device *dev,
 static void cpuidle_coupled_poked(void *info)
 {
 	int cpu = (unsigned long)info;
+	trace_coupled_poked(cpu);
 	cpumask_clear_cpu(cpu, &cpuidle_coupled_poked_mask);
 }
 
@@ -251,8 +272,10 @@ static void cpuidle_coupled_poke(int cpu)
 {
 	struct call_single_data *csd = &per_cpu(cpuidle_coupled_poke_cb, cpu);
 
-	if (!cpumask_test_and_set_cpu(cpu, &cpuidle_coupled_poked_mask))
+	if (!cpumask_test_and_set_cpu(cpu, &cpuidle_coupled_poked_mask)) {
+		trace_coupled_poke(cpu);
 		__smp_call_function_single(cpu, csd, 0);
+	}
 }
 
 /**
@@ -361,28 +384,37 @@ int cpuidle_enter_state_coupled(struct cpuidle_device *dev,
 	BUG_ON(atomic_read(&coupled->ready_count));
 	cpuidle_coupled_set_waiting(dev, coupled, next_state);
 
+	trace_coupled_enter(dev->cpu);
+
 retry:
 	/*
 	 * Wait for all coupled cpus to be idle, using the deepest state
 	 * allowed for a single cpu.
 	 */
 	while (!need_resched() && !cpuidle_coupled_cpus_waiting(coupled)) {
+		trace_coupled_safe_enter(dev->cpu);
 		entered_state = cpuidle_enter_state(dev, drv,
 			dev->safe_state_index);
+		trace_coupled_safe_exit(dev->cpu);
 
+		trace_coupled_spin(dev->cpu);
 		local_irq_enable();
 		while (cpumask_test_cpu(dev->cpu, &cpuidle_coupled_poked_mask))
 			cpu_relax();
 		local_irq_disable();
+		trace_coupled_unspin(dev->cpu);
 	}
 
 	/* give a chance to process any remaining pokes */
+	trace_coupled_spin(dev->cpu);
 	local_irq_enable();
 	while (cpumask_test_cpu(dev->cpu, &cpuidle_coupled_poked_mask))
 		cpu_relax();
 	local_irq_disable();
+	trace_coupled_unspin(dev->cpu);
 
 	if (need_resched()) {
+		trace_coupled_abort(dev->cpu);
 		cpuidle_coupled_set_not_waiting(dev, coupled);
 		goto out;
 	}
@@ -401,29 +433,35 @@ retry:
 	smp_mb__after_atomic_inc();
 	/* alive_count can't change while ready_count > 0 */
 	alive = atomic_read(&coupled->alive_count);
+	trace_coupled_spin(dev->cpu);
 	while (atomic_read(&coupled->ready_count) != alive) {
 		/* Check if any other cpus bailed out of idle. */
 		if (!cpuidle_coupled_cpus_waiting(coupled)) {
 			atomic_dec(&coupled->ready_count);
 			smp_mb__after_atomic_dec();
+			trace_coupled_detected_abort(dev->cpu);
 			goto retry;
 		}
 
 		cpu_relax();
 	}
+	trace_coupled_unspin(dev->cpu);
 
 	/* all cpus have acked the coupled state */
 	smp_rmb();
 
 	next_state = cpuidle_coupled_get_state(dev, coupled);
-
+	trace_coupled_idle_enter(dev->cpu);
 	entered_state = cpuidle_enter_state(dev, drv, next_state);
+	trace_coupled_idle_exit(dev->cpu);
 
 	cpuidle_coupled_set_not_waiting(dev, coupled);
 	atomic_dec(&coupled->ready_count);
 	smp_mb__after_atomic_dec();
 
 out:
+	trace_coupled_exit(dev->cpu);
+
 	/*
 	 * Normal cpuidle states are expected to return with irqs enabled.
 	 * That leads to an inefficiency where a cpu receiving an interrupt
@@ -445,8 +483,10 @@ out:
 	 * a cpu exits and re-enters the ready state because this cpu has
 	 * already decremented its waiting_count.
 	 */
+	trace_coupled_spin(dev->cpu);
 	while (atomic_read(&coupled->ready_count) != 0)
 		cpu_relax();
+	trace_coupled_unspin(dev->cpu);
 
 	smp_rmb();
 
diff --git a/include/trace/events/cpuidle.h b/include/trace/events/cpuidle.h
new file mode 100644
index 0000000..9b2cbbb
--- /dev/null
+++ b/include/trace/events/cpuidle.h
@@ -0,0 +1,243 @@
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM cpuidle
+
+#if !defined(_TRACE_CPUIDLE_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_CPUIDLE_H
+
+#include <linux/atomic.h>
+#include <linux/tracepoint.h>
+
+extern atomic_t cpuidle_trace_seq;
+
+TRACE_EVENT(coupled_enter,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+TRACE_EVENT(coupled_exit,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+TRACE_EVENT(coupled_spin,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+TRACE_EVENT(coupled_unspin,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+TRACE_EVENT(coupled_safe_enter,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+TRACE_EVENT(coupled_safe_exit,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+TRACE_EVENT(coupled_idle_enter,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+TRACE_EVENT(coupled_idle_exit,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+TRACE_EVENT(coupled_abort,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+TRACE_EVENT(coupled_detected_abort,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+TRACE_EVENT(coupled_poke,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+TRACE_EVENT(coupled_poked,
+
+	TP_PROTO(unsigned int cpu),
+
+	TP_ARGS(cpu),
+
+	TP_STRUCT__entry(
+		__field(unsigned int, cpu)
+		__field(unsigned int, seq)
+	),
+
+	TP_fast_assign(
+		__entry->cpu = cpu;
+		__entry->seq = atomic_inc_return(&cpuidle_trace_seq);
+	),
+
+	TP_printk("%u %u", __entry->seq, __entry->cpu)
+);
+
+#endif /* if !defined(_TRACE_CPUIDLE_H) || defined(TRACE_HEADER_MULTI_READ) */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
-- 
1.7.9.2



From ccross at android.com  Wed Mar 14 14:29:52 2012
From: ccross at android.com (Colin Cross)
Date: Wed, 14 Mar 2012 11:29:52 -0700
Subject: [PATCHv2 3/5] cpuidle: add support for states that affect multiple
 cpus
In-Reply-To: <1331749794-8056-1-git-send-email-ccross@android.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
Message-ID: <1331749794-8056-4-git-send-email-ccross@android.com>

On some ARM SMP SoCs (OMAP4460, Tegra 2, and probably more), the
cpus cannot be independently powered down, either due to
sequencing restrictions (on Tegra 2, cpu 0 must be the last to
power down), or due to HW bugs (on OMAP4460, a cpu powering up
will corrupt the gic state unless the other cpu runs a work
around).  Each cpu has a power state that it can enter without
coordinating with the other cpu (usually Wait For Interrupt, or
WFI), and one or more "coupled" power states that affect blocks
shared between the cpus (L2 cache, interrupt controller, and
sometimes the whole SoC).  Entering a coupled power state must
be tightly controlled on both cpus.

The easiest solution to implementing coupled cpu power states is
to hotplug all but one cpu whenever possible, usually using a
cpufreq governor that looks at cpu load to determine when to
enable the secondary cpus.  This causes problems, as hotplug is an
expensive operation, so the number of hotplug transitions must be
minimized, leading to very slow response to loads, often on the
order of seconds.

This file implements an alternative solution, where each cpu will
wait in the WFI state until all cpus are ready to enter a coupled
state, at which point the coupled state function will be called
on all cpus at approximately the same time.

Once all cpus are ready to enter idle, they are woken by an smp
cross call.  At this point, there is a chance that one of the
cpus will find work to do, and choose not to enter idle.  A
final pass is needed to guarantee that all cpus will call the
power state enter function at the same time.  During this pass,
each cpu will increment the ready counter, and continue once the
ready counter matches the number of online coupled cpus.  If any
cpu exits idle, the other cpus will decrement their counter and
retry.

To use coupled cpuidle states, a cpuidle driver must:

   Set struct cpuidle_device.coupled_cpus to the mask of all
   coupled cpus, usually the same as cpu_possible_mask if all cpus
   are part of the same cluster.  The coupled_cpus mask must be
   set in the struct cpuidle_device for each cpu.

   Set struct cpuidle_device.safe_state to a state that is not a
   coupled state.  This is usually WFI.

   Set CPUIDLE_FLAG_COUPLED in struct cpuidle_state.flags for each
   state that affects multiple cpus.

   Provide a struct cpuidle_state.enter function for each state
   that affects multiple cpus.  This function is guaranteed to be
   called on all cpus at approximately the same time.  The driver
   should ensure that the cpus all abort together if any cpu tries
   to abort once the function is called.

Signed-off-by: Colin Cross <ccross at android.com>
Cc: Len Brown <len.brown at intel.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Arjan van de Ven <arjan at linux.intel.com>
Cc: Trinabh Gupta <g.trinabh at gmail.com>
Cc: Deepthi Dharwar <deepthi at linux.vnet.ibm.com>
---
 drivers/cpuidle/Kconfig   |    3 +
 drivers/cpuidle/Makefile  |    1 +
 drivers/cpuidle/coupled.c |  568 +++++++++++++++++++++++++++++++++++++++++++++
 drivers/cpuidle/cpuidle.c |   15 +-
 drivers/cpuidle/cpuidle.h |   30 +++
 include/linux/cpuidle.h   |    7 +
 6 files changed, 623 insertions(+), 1 deletion(-)
 create mode 100644 drivers/cpuidle/coupled.c

v2:
   * removed the coupled lock, replacing it with atomic counters
   * added a check for outstanding pokes before beginning the
     final transition to avoid extra wakeups
   * made the cpuidle_coupled struct completely private
   * fixed kerneldoc comment formatting


diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index 78a666d..a76b689 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -18,3 +18,6 @@ config CPU_IDLE_GOV_MENU
 	bool
 	depends on CPU_IDLE && NO_HZ
 	default y
+
+config ARCH_NEEDS_CPU_IDLE_COUPLED
+	def_bool n
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index 5634f88..38c8f69 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
+obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
new file mode 100644
index 0000000..046fccb
--- /dev/null
+++ b/drivers/cpuidle/coupled.c
@@ -0,0 +1,568 @@
+/*
+ * coupled.c - helper functions to enter the same idle state on multiple cpus
+ *
+ * Copyright (c) 2011 Google, Inc.
+ *
+ * Author: Colin Cross <ccross at android.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/cpu.h>
+#include <linux/cpuidle.h>
+#include <linux/mutex.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "cpuidle.h"
+
+/*
+ * coupled cpuidle states
+ *
+ * On some ARM SMP SoCs (OMAP4460, Tegra 2, and probably more), the
+ * cpus cannot be independently powered down, either due to
+ * sequencing restrictions (on Tegra 2, cpu 0 must be the last to
+ * power down), or due to HW bugs (on OMAP4460, a cpu powering up
+ * will corrupt the gic state unless the other cpu runs a work
+ * around).  Each cpu has a power state that it can enter without
+ * coordinating with the other cpu (usually Wait For Interrupt, or
+ * WFI), and one or more "coupled" power states that affect blocks
+ * shared between the cpus (L2 cache, interrupt controller, and
+ * sometimes the whole SoC).  Entering a coupled power state must
+ * be tightly controlled on both cpus.
+ *
+ * The easiest solution to implementing coupled cpu power states is
+ * to hotplug all but one cpu whenever possible, usually using a
+ * cpufreq governor that looks at cpu load to determine when to
+ * enable the secondary cpus.  This causes problems, as hotplug is an
+ * expensive operation, so the number of hotplug transitions must be
+ * minimized, leading to very slow response to loads, often on the
+ * order of seconds.
+ *
+ * This file implements an alternative solution, where each cpu will
+ * wait in the WFI state until all cpus are ready to enter a coupled
+ * state, at which point the coupled state function will be called
+ * on all cpus at approximately the same time.
+ *
+ * Once all cpus are ready to enter idle, they are woken by an smp
+ * cross call.  At this point, there is a chance that one of the
+ * cpus will find work to do, and choose not to enter idle.  A
+ * final pass is needed to guarantee that all cpus will call the
+ * power state enter function at the same time.  During this pass,
+ * each cpu will increment the ready counter, and continue once the
+ * ready counter matches the number of online coupled cpus.  If any
+ * cpu exits idle, the other cpus will decrement their counter and
+ * retry.
+ *
+ * requested_state stores the deepest coupled idle state each cpu
+ * is ready for.  It is assumed that the states are indexed from
+ * shallowest (highest power, lowest exit latency) to deepest
+ * (lowest power, highest exit latency).  The requested_state
+ * variable is not locked.  It is only written from the cpu that
+ * it stores (or by the on/offlining cpu if that cpu is offline),
+ * and only read after all the cpus are ready for the coupled idle
+ * state are are no longer updating it.
+ *
+ * Three atomic counters are used.  alive_count tracks the number
+ * of cpus in the coupled set that are currently or soon will be
+ * online.  waiting_count tracks the number of cpus that are in
+ * the waiting loop, in the ready loop, or in the coupled idle state.
+ * ready_count tracks the number of cpus that are in the ready loop
+ * or in the coupled idle state.
+ *
+ * To use coupled cpuidle states, a cpuidle driver must:
+ *
+ *    Set struct cpuidle_device.coupled_cpus to the mask of all
+ *    coupled cpus, usually the same as cpu_possible_mask if all cpus
+ *    are part of the same cluster.  The coupled_cpus mask must be
+ *    set in the struct cpuidle_device for each cpu.
+ *
+ *    Set struct cpuidle_device.safe_state to a state that is not a
+ *    coupled state.  This is usually WFI.
+ *
+ *    Set CPUIDLE_FLAG_COUPLED in struct cpuidle_state.flags for each
+ *    state that affects multiple cpus.
+ *
+ *    Provide a struct cpuidle_state.enter function for each state
+ *    that affects multiple cpus.  This function is guaranteed to be
+ *    called on all cpus at approximately the same time.  The driver
+ *    should ensure that the cpus all abort together if any cpu tries
+ *    to abort once the function is called.  The function should return
+ *    with interrupts still disabled.
+ */
+
+/**
+ * struct cpuidle_coupled - data for set of cpus that share a coupled idle state
+ * @coupled_cpus: mask of cpus that are part of the coupled set
+ * @requested_state: array of requested states for cpus in the coupled set
+ * @ready_count: count of cpus that are ready for the final idle transition
+ * @waiting_count: count of cpus that are waiting for all other cpus to be idle
+ * @alive_count: count of cpus that are online or soon will be
+ * @refcnt: reference count of cpuidle devices that are using this struct
+ */
+struct cpuidle_coupled {
+	cpumask_t coupled_cpus;
+	int requested_state[NR_CPUS];
+	atomic_t ready_count;
+	atomic_t waiting_count;
+	atomic_t alive_count;
+	int refcnt;
+};
+
+#define CPUIDLE_COUPLED_NOT_IDLE	(-1)
+#define CPUIDLE_COUPLED_DEAD		(-2)
+
+static DEFINE_MUTEX(cpuidle_coupled_lock);
+static DEFINE_PER_CPU(struct call_single_data, cpuidle_coupled_poke_cb);
+
+/*
+ * The cpuidle_coupled_poked_mask masked is used to avoid calling
+ * __smp_call_function_single with the per cpu call_single_data struct already
+ * in use.  This prevents a deadlock where two cpus are waiting for each others
+ * call_single_data struct to be available
+ */
+static cpumask_t cpuidle_coupled_poked_mask;
+
+/**
+ * cpuidle_state_is_coupled - check if a state is part of a coupled set
+ * @dev: struct cpuidle_device for the current cpu
+ * @drv: struct cpuidle_driver for the platform
+ * @state: index of the target state in drv->states
+ *
+ * Returns true if the target state is coupled with cpus besides this one
+ */
+bool cpuidle_state_is_coupled(struct cpuidle_device *dev,
+	struct cpuidle_driver *drv, int state)
+{
+	return drv->states[state].flags & CPUIDLE_FLAG_COUPLED;
+}
+
+/**
+ * cpuidle_coupled_cpus_waiting - check if all cpus in a coupled set are waiting
+ * @coupled: the struct coupled that contains the current cpu
+ *
+ * Returns true if all cpus coupled to this target state are in the wait loop
+ */
+static inline bool cpuidle_coupled_cpus_waiting(struct cpuidle_coupled *coupled)
+{
+	int alive;
+	int waiting;
+
+	/*
+	 * Read alive before reading waiting so a booting cpu is not treated as
+	 * idle
+	 */
+	alive = atomic_read(&coupled->alive_count);
+	smp_rmb();
+	waiting = atomic_read(&coupled->waiting_count);
+
+	return (waiting == alive);
+}
+
+/**
+ * cpuidle_coupled_get_state - determine the deepest idle state
+ * @dev: struct cpuidle_device for this cpu
+ * @coupled: the struct coupled that contains the current cpu
+ *
+ * Returns the deepest idle state that all coupled cpus can enter
+ */
+static inline int cpuidle_coupled_get_state(struct cpuidle_device *dev,
+		struct cpuidle_coupled *coupled)
+{
+	int i;
+	int state = INT_MAX;
+
+	for_each_cpu_mask(i, coupled->coupled_cpus)
+		if (coupled->requested_state[i] != CPUIDLE_COUPLED_DEAD &&
+		    coupled->requested_state[i] < state)
+			state = coupled->requested_state[i];
+
+	BUG_ON(state >= dev->state_count || state < 0);
+
+	return state;
+}
+
+static void cpuidle_coupled_poked(void *info)
+{
+	int cpu = (unsigned long)info;
+	cpumask_clear_cpu(cpu, &cpuidle_coupled_poked_mask);
+}
+
+/**
+ * cpuidle_coupled_poke - wake up a cpu that may be waiting
+ * @cpu: target cpu
+ *
+ * Ensures that the target cpu exits it's waiting idle state (if it is in it)
+ * and will see updates to waiting_count before it re-enters it's waiting idle
+ * state.
+ *
+ * If cpuidle_coupled_poked_mask is already set for the target cpu, that cpu
+ * either has or will soon have a pending IPI that will wake it out of idle,
+ * or it is currently processing the IPI and is not in idle.
+ */
+static void cpuidle_coupled_poke(int cpu)
+{
+	struct call_single_data *csd = &per_cpu(cpuidle_coupled_poke_cb, cpu);
+
+	if (!cpumask_test_and_set_cpu(cpu, &cpuidle_coupled_poked_mask))
+		__smp_call_function_single(cpu, csd, 0);
+}
+
+/**
+ * cpuidle_coupled_poke_others - wake up all other cpus that may be waiting
+ * @dev: struct cpuidle_device for this cpu
+ * @coupled: the struct coupled that contains the current cpu
+ *
+ * Calls cpuidle_coupled_poke on all other online cpus.
+ */
+static void cpuidle_coupled_poke_others(struct cpuidle_device *dev,
+		struct cpuidle_coupled *coupled)
+{
+	int cpu;
+
+	for_each_cpu_mask(cpu, coupled->coupled_cpus)
+		if (cpu != dev->cpu && cpu_online(cpu))
+			cpuidle_coupled_poke(cpu);
+}
+
+/**
+ * cpuidle_coupled_set_waiting - mark this cpu as in the wait loop
+ * @dev: struct cpuidle_device for this cpu
+ * @coupled: the struct coupled that contains the current cpu
+ * @next_state: the index in drv->states of the requested state for this cpu
+ *
+ * Updates the requested idle state for the specified cpuidle device,
+ * poking all coupled cpus out of idle if necessary to let them see the new
+ * state.
+ *
+ * Provides memory ordering around waiting_count.
+ */
+static void cpuidle_coupled_set_waiting(struct cpuidle_device *dev,
+		struct cpuidle_coupled *coupled, int next_state)
+{
+	int alive;
+
+	BUG_ON(coupled->requested_state[dev->cpu] >= 0);
+
+	coupled->requested_state[dev->cpu] = next_state;
+
+	/*
+	 * If this is the last cpu to enter the waiting state, poke
+	 * all the other cpus out of their waiting state so they can
+	 * enter a deeper state.  This can race with one of the cpus
+	 * exiting the waiting state due to an interrupt and
+	 * decrementing waiting_count, see comment below.
+	 */
+	alive = atomic_read(&coupled->alive_count);
+	if (atomic_inc_return(&coupled->waiting_count) == alive)
+		cpuidle_coupled_poke_others(dev, coupled);
+}
+
+/**
+ * cpuidle_coupled_set_not_waiting - mark this cpu as leaving the wait loop
+ * @dev: struct cpuidle_device for this cpu
+ * @coupled: the struct coupled that contains the current cpu
+ *
+ * Removes the requested idle state for the specified cpuidle device.
+ *
+ * Provides memory ordering around waiting_count.
+ */
+static void cpuidle_coupled_set_not_waiting(struct cpuidle_device *dev,
+		struct cpuidle_coupled *coupled)
+{
+	BUG_ON(coupled->requested_state[dev->cpu] < 0);
+
+	/*
+	 * Decrementing waiting_count can race with incrementing it in
+	 * cpuidle_coupled_set_waiting, but that's OK.  Worst case, some
+	 * cpus will increment ready_count and then spin until they
+	 * notice that this cpu has cleared it's requested_state.
+	 */
+
+	smp_mb__before_atomic_dec();
+	atomic_dec(&coupled->waiting_count);
+	smp_mb__after_atomic_dec();
+
+	coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_NOT_IDLE;
+}
+
+/**
+ * cpuidle_enter_state_coupled - attempt to enter a state with coupled cpus
+ * @dev: struct cpuidle_device for the current cpu
+ * @drv: struct cpuidle_driver for the platform
+ * @next_state: index of the requested state in drv->states
+ *
+ * Coordinate with coupled cpus to enter the target state.  This is a two
+ * stage process.  In the first stage, the cpus are operating independently,
+ * and may call into cpuidle_enter_state_coupled at completely different times.
+ * To save as much power as possible, the first cpus to call this function will
+ * go to an intermediate state (the cpuidle_device's safe state), and wait for
+ * all the other cpus to call this function.  Once all coupled cpus are idle,
+ * the second stage will start.  Each coupled cpu will spin until all cpus have
+ * guaranteed that they will call the target_state.
+ */
+int cpuidle_enter_state_coupled(struct cpuidle_device *dev,
+		struct cpuidle_driver *drv, int next_state)
+{
+	int entered_state = -1;
+	struct cpuidle_coupled *coupled = dev->coupled;
+	int alive;
+
+	if (!coupled)
+		return -EINVAL;
+
+	BUG_ON(atomic_read(&coupled->ready_count));
+	cpuidle_coupled_set_waiting(dev, coupled, next_state);
+
+retry:
+	/*
+	 * Wait for all coupled cpus to be idle, using the deepest state
+	 * allowed for a single cpu.
+	 */
+	while (!need_resched() && !cpuidle_coupled_cpus_waiting(coupled)) {
+		entered_state = cpuidle_enter_state(dev, drv,
+			dev->safe_state_index);
+
+		local_irq_enable();
+		while (cpumask_test_cpu(dev->cpu, &cpuidle_coupled_poked_mask))
+			cpu_relax();
+		local_irq_disable();
+	}
+
+	/* give a chance to process any remaining pokes */
+	local_irq_enable();
+	while (cpumask_test_cpu(dev->cpu, &cpuidle_coupled_poked_mask))
+		cpu_relax();
+	local_irq_disable();
+
+	if (need_resched()) {
+		cpuidle_coupled_set_not_waiting(dev, coupled);
+		goto out;
+	}
+
+	/*
+	 * All coupled cpus are probably idle.  There is a small chance that
+	 * one of the other cpus just became active.  Increment a counter when
+	 * ready, and spin until all coupled cpus have incremented the counter.
+	 * Once a cpu has incremented the counter, it cannot abort idle and must
+	 * spin until either the count has hit alive_count, or another cpu
+	 * leaves idle.
+	 */
+
+	smp_mb__before_atomic_inc();
+	atomic_inc(&coupled->ready_count);
+	smp_mb__after_atomic_inc();
+	/* alive_count can't change while ready_count > 0 */
+	alive = atomic_read(&coupled->alive_count);
+	while (atomic_read(&coupled->ready_count) != alive) {
+		/* Check if any other cpus bailed out of idle. */
+		if (!cpuidle_coupled_cpus_waiting(coupled)) {
+			atomic_dec(&coupled->ready_count);
+			smp_mb__after_atomic_dec();
+			goto retry;
+		}
+
+		cpu_relax();
+	}
+
+	/* all cpus have acked the coupled state */
+	smp_rmb();
+
+	next_state = cpuidle_coupled_get_state(dev, coupled);
+
+	entered_state = cpuidle_enter_state(dev, drv, next_state);
+
+	cpuidle_coupled_set_not_waiting(dev, coupled);
+	atomic_dec(&coupled->ready_count);
+	smp_mb__after_atomic_dec();
+
+out:
+	/*
+	 * Normal cpuidle states are expected to return with irqs enabled.
+	 * That leads to an inefficiency where a cpu receiving an interrupt
+	 * that brings it out of idle will process that interrupt before
+	 * exiting the idle enter function and decrementing ready_count.  All
+	 * other cpus will need to spin waiting for the cpu that is processing
+	 * the interrupt.  If the driver returns with interrupts disabled,
+	 * all other cpus will loop back into the safe idle state instead of
+	 * spinning, saving power.
+	 *
+	 * Calling local_irq_enable here allows coupled states to return with
+	 * interrupts disabled, but won't cause problems for drivers that
+	 * exit with interrupts enabled.
+	 */
+	local_irq_enable();
+
+	/*
+	 * Wait until all coupled cpus have exited idle.  There is no risk that
+	 * a cpu exits and re-enters the ready state because this cpu has
+	 * already decremented its waiting_count.
+	 */
+	while (atomic_read(&coupled->ready_count) != 0)
+		cpu_relax();
+
+	smp_rmb();
+
+	return entered_state;
+}
+
+/**
+ * cpuidle_coupled_register_device - register a coupled cpuidle device
+ * @dev: struct cpuidle_device for the current cpu
+ *
+ * Called from cpuidle_register_device to handle coupled idle init.  Finds the
+ * cpuidle_coupled struct for this set of coupled cpus, or creates one if none
+ * exists yet.
+ */
+int cpuidle_coupled_register_device(struct cpuidle_device *dev)
+{
+	int cpu;
+	struct cpuidle_device *other_dev;
+	struct call_single_data *csd;
+	struct cpuidle_coupled *coupled;
+
+	if (cpumask_empty(&dev->coupled_cpus))
+		return 0;
+
+	for_each_cpu_mask(cpu, dev->coupled_cpus) {
+		other_dev = per_cpu(cpuidle_devices, cpu);
+		if (other_dev && other_dev->coupled) {
+			coupled = other_dev->coupled;
+			goto have_coupled;
+		}
+	}
+
+	/* No existing coupled info found, create a new one */
+	coupled = kzalloc(sizeof(struct cpuidle_coupled), GFP_KERNEL);
+	if (!coupled)
+		return -ENOMEM;
+
+	coupled->coupled_cpus = dev->coupled_cpus;
+	for_each_cpu_mask(cpu, coupled->coupled_cpus)
+		coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_DEAD;
+
+have_coupled:
+	dev->coupled = coupled;
+	BUG_ON(!cpumask_equal(&dev->coupled_cpus, &coupled->coupled_cpus));
+
+	if (cpu_online(dev->cpu)) {
+		coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_NOT_IDLE;
+		atomic_inc(&coupled->alive_count);
+	}
+
+	coupled->refcnt++;
+
+	csd = &per_cpu(cpuidle_coupled_poke_cb, dev->cpu);
+	csd->func = cpuidle_coupled_poked;
+	csd->info = (void *)(unsigned long)dev->cpu;
+
+	return 0;
+}
+
+/**
+ * cpuidle_coupled_unregister_device - unregister a coupled cpuidle device
+ * @dev: struct cpuidle_device for the current cpu
+ *
+ * Called from cpuidle_unregister_device to tear down coupled idle.  Removes the
+ * cpu from the coupled idle set, and frees the cpuidle_coupled_info struct if
+ * this was the last cpu in the set.
+ */
+void cpuidle_coupled_unregister_device(struct cpuidle_device *dev)
+{
+	struct cpuidle_coupled *coupled = dev->coupled;
+
+	if (cpumask_empty(&dev->coupled_cpus))
+		return;
+
+	if (--coupled->refcnt)
+		kfree(coupled);
+	dev->coupled = NULL;
+}
+
+/**
+ * cpuidle_coupled_cpu_set_alive - adjust alive_count during hotplug transitions
+ * @cpu: target cpu number
+ * @alive: whether the target cpu is going up or down
+ *
+ * Run on the cpu that is bringing up the target cpu, before the target cpu
+ * has been booted, or after the target cpu is completely dead.
+ */
+static void cpuidle_coupled_cpu_set_alive(int cpu, bool alive)
+{
+	struct cpuidle_device *dev;
+	struct cpuidle_coupled *coupled;
+
+	mutex_lock(&cpuidle_lock);
+
+	dev = per_cpu(cpuidle_devices, cpu);
+	if (!dev->coupled)
+		goto out;
+
+	coupled = dev->coupled;
+
+	/*
+	 * waiting_count must be at least 1 less than alive_count, because
+	 * this cpu is not waiting.  Spin until all cpus have noticed this cpu
+	 * is not idle and exited the ready loop before changing alive_count.
+	 */
+	while (atomic_read(&coupled->ready_count))
+		cpu_relax();
+
+	smp_mb__before_atomic_inc();
+	atomic_inc(&coupled->alive_count);
+	smp_mb__after_atomic_inc();
+
+	if (alive)
+		coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_NOT_IDLE;
+	else
+		coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_DEAD;
+
+out:
+	mutex_unlock(&cpuidle_lock);
+}
+
+/**
+ * cpuidle_coupled_cpu_notify - notifier called during hotplug transitions
+ * @nb: notifier block
+ * @action: hotplug transition
+ * @hcpu: target cpu number
+ *
+ * Called when a cpu is brought on or offline using hotplug.  Updates the
+ * coupled cpu set appropriately
+ */
+static int cpuidle_coupled_cpu_notify(struct notifier_block *nb,
+		unsigned long action, void *hcpu)
+{
+	int cpu = (unsigned long)hcpu;
+
+	switch (action & ~CPU_TASKS_FROZEN) {
+	case CPU_DEAD:
+	case CPU_UP_CANCELED:
+		cpuidle_coupled_cpu_set_alive(cpu, false);
+		break;
+	case CPU_UP_PREPARE:
+		cpuidle_coupled_cpu_set_alive(cpu, true);
+		break;
+	}
+	return NOTIFY_OK;
+}
+
+static struct notifier_block cpuidle_coupled_cpu_notifier = {
+	.notifier_call = cpuidle_coupled_cpu_notify,
+};
+
+static int __init cpuidle_coupled_init(void)
+{
+	return register_cpu_notifier(&cpuidle_coupled_cpu_notifier);
+}
+core_initcall(cpuidle_coupled_init);
diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index aacf2f0..a203437 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -123,7 +123,11 @@ int cpuidle_idle_call(void)
 	trace_power_start(POWER_CSTATE, next_state, dev->cpu);
 	trace_cpu_idle(next_state, dev->cpu);
 
-	entered_state = cpuidle_enter_state(dev, drv, next_state);
+	if (cpuidle_state_is_coupled(dev, drv, next_state))
+		entered_state = cpuidle_enter_state_coupled(dev, drv,
+							    next_state);
+	else
+		entered_state = cpuidle_enter_state(dev, drv, next_state);
 
 	trace_power_end(dev->cpu);
 	trace_cpu_idle(PWR_EVENT_EXIT, dev->cpu);
@@ -323,9 +327,16 @@ static int __cpuidle_register_device(struct cpuidle_device *dev)
 	if (ret)
 		goto err_sysfs;
 
+	ret = cpuidle_coupled_register_device(dev);
+	if (ret)
+		goto err_coupled;
+
 	dev->registered = 1;
 	return 0;
 
+err_coupled:
+	cpuidle_remove_sysfs(cpu_dev);
+	wait_for_completion(&dev->kobj_unregister);
 err_sysfs:
 	list_del(&dev->device_list);
 	per_cpu(cpuidle_devices, dev->cpu) = NULL;
@@ -380,6 +391,8 @@ void cpuidle_unregister_device(struct cpuidle_device *dev)
 	wait_for_completion(&dev->kobj_unregister);
 	per_cpu(cpuidle_devices, dev->cpu) = NULL;
 
+	cpuidle_coupled_unregister_device(dev);
+
 	cpuidle_resume_and_unlock();
 
 	module_put(cpuidle_driver->owner);
diff --git a/drivers/cpuidle/cpuidle.h b/drivers/cpuidle/cpuidle.h
index d8a3ccc..76e7f69 100644
--- a/drivers/cpuidle/cpuidle.h
+++ b/drivers/cpuidle/cpuidle.h
@@ -32,4 +32,34 @@ extern void cpuidle_remove_state_sysfs(struct cpuidle_device *device);
 extern int cpuidle_add_sysfs(struct device *dev);
 extern void cpuidle_remove_sysfs(struct device *dev);
 
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
+bool cpuidle_state_is_coupled(struct cpuidle_device *dev,
+		struct cpuidle_driver *drv, int state);
+int cpuidle_enter_state_coupled(struct cpuidle_device *dev,
+		struct cpuidle_driver *drv, int next_state);
+int cpuidle_coupled_register_device(struct cpuidle_device *dev);
+void cpuidle_coupled_unregister_device(struct cpuidle_device *dev);
+#else
+static inline bool cpuidle_state_is_coupled(struct cpuidle_device *dev,
+		struct cpuidle_driver *drv, int state)
+{
+	return false;
+}
+
+static inline int cpuidle_enter_state_coupled(struct cpuidle_device *dev,
+		struct cpuidle_driver *drv, int next_state)
+{
+	return -1;
+}
+
+static inline int cpuidle_coupled_register_device(struct cpuidle_device *dev)
+{
+	return 0;
+}
+
+static inline void cpuidle_coupled_unregister_device(struct cpuidle_device *dev)
+{
+}
+#endif
+
 #endif /* __DRIVER_CPUIDLE_H */
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 712abcc..71f2fba 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -53,6 +53,7 @@ struct cpuidle_state {
 
 /* Idle State Flags */
 #define CPUIDLE_FLAG_TIME_VALID	(0x01) /* is residency time measurable? */
+#define CPUIDLE_FLAG_COUPLED	(0x02) /* state applies to multiple cpus */
 
 #define CPUIDLE_DRIVER_FLAGS_MASK (0xFFFF0000)
 
@@ -97,6 +98,12 @@ struct cpuidle_device {
 	struct kobject		kobj;
 	struct completion	kobj_unregister;
 	void			*governor_data;
+
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
+	int			safe_state_index;
+	cpumask_t		coupled_cpus;
+	struct cpuidle_coupled	*coupled;
+#endif
 };
 
 DECLARE_PER_CPU(struct cpuidle_device *, cpuidle_devices);
-- 
1.7.9.2



From ccross at android.com  Wed Mar 14 14:29:53 2012
From: ccross at android.com (Colin Cross)
Date: Wed, 14 Mar 2012 11:29:53 -0700
Subject: [PATCHv2 4/5] cpuidle: coupled: add parallel barrier function
In-Reply-To: <1331749794-8056-1-git-send-email-ccross@android.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
Message-ID: <1331749794-8056-5-git-send-email-ccross@android.com>

Adds cpuidle_coupled_parallel_barrier, which can be used by coupled
cpuidle state enter functions to handle resynchronization after
determining if any cpu needs to abort.  The normal use case will
be:

static bool abort_flag;
static atomic_t abort_barrier;

int arch_cpuidle_enter(struct cpuidle_device *dev, ...)
{
	if (arch_turn_off_irq_controller()) {
	   	/* returns an error if an irq is pending and would be lost
		   if idle continued and turned off power */
		abort_flag = true;
	}

	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);

	if (abort_flag) {
	   	/* One of the cpus didn't turn off it's irq controller */
	   	arch_turn_on_irq_controller();
		return -EINTR;
	}

	/* continue with idle */
	...
}

This will cause all cpus to abort idle together if one of them needs
to abort.

Signed-off-by: Colin Cross <ccross at android.com>
---
 drivers/cpuidle/coupled.c |   37 +++++++++++++++++++++++++++++++++++++
 include/linux/cpuidle.h   |    4 ++++
 2 files changed, 41 insertions(+)

diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
index 046fccb..188a53f 100644
--- a/drivers/cpuidle/coupled.c
+++ b/drivers/cpuidle/coupled.c
@@ -134,6 +134,43 @@ static DEFINE_PER_CPU(struct call_single_data, cpuidle_coupled_poke_cb);
 static cpumask_t cpuidle_coupled_poked_mask;
 
 /**
+ * cpuidle_coupled_parallel_barrier - synchronize all online coupled cpus
+ * @dev: cpuidle_device of the calling cpu
+ * @a:   atomic variable to hold the barrier
+ *
+ * No caller to this function will return from this function until all online
+ * cpus in the same coupled group have called this function.  Once any caller
+ * has returned from this function, the barrier is immediately available for
+ * reuse.
+ *
+ * The atomic variable a must be initialized to 0 before any cpu calls
+ * this function, will be reset to 0 before any cpu returns from this function.
+ *
+ * Must only be called from within a coupled idle state handler
+ * (state.enter when state.flags has CPUIDLE_FLAG_COUPLED set).
+ *
+ * Provides full smp barrier semantics before and after calling.
+ */
+void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a)
+{
+	int n = atomic_read(&dev->coupled->alive_count);
+
+	smp_mb__before_atomic_inc();
+	atomic_inc(a);
+
+	while (atomic_read(a) < n)
+		cpu_relax();
+
+	if (atomic_inc_return(a) == n * 2) {
+		atomic_set(a, 0);
+		return;
+	}
+
+	while (atomic_read(a) > n)
+		cpu_relax();
+}
+
+/**
  * cpuidle_state_is_coupled - check if a state is part of a coupled set
  * @dev: struct cpuidle_device for the current cpu
  * @drv: struct cpuidle_driver for the platform
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 71f2fba..37ae622 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -167,6 +167,10 @@ static inline void cpuidle_disable_device(struct cpuidle_device *dev) { }
 
 #endif
 
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
+void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a);
+#endif
+
 /******************************
  * CPUIDLE GOVERNOR INTERFACE *
  ******************************/
-- 
1.7.9.2



From robherring2 at gmail.com  Wed Mar 14 14:38:59 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 14 Mar 2012 13:38:59 -0500
Subject: [PATCH v6 3/3] clk: basic clock hardware types
In-Reply-To: <20120314182345.GB29317@pengutronix.de>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-4-git-send-email-mturquette@linaro.org>
 <20120314182345.GB29317@pengutronix.de>
Message-ID: <4F60E5C3.1090006@gmail.com>

On 03/14/2012 01:23 PM, Sascha Hauer wrote:
> On Fri, Mar 09, 2012 at 11:54:24PM -0800, Mike Turquette wrote:
>> Many platforms support simple gateable clocks, fixed-rate clocks,
>> adjustable divider clocks and multi-parent multiplexer clocks.
>>
>> This patch introduces basic clock types for the above-mentioned hardware
>> which share some common characteristics.
>>
>> Based on original work by Jeremy Kerr and contribution by Jamie Iles.
>> Dividers and multiplexor clocks originally contributed by Richard Zhao &
>> Sascha Hauer.
>>
>> Signed-off-by: Mike Turquette <mturquette at linaro.org>
>> Signed-off-by: Mike Turquette <mturquette at ti.com>
>> Cc: Russell King <linux at arm.linux.org.uk>
>> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
>> Cc: Thomas Gleixner <tglx at linutronix.de>
>> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
>> Cc: Paul Walmsley <paul at pwsan.com>
>> Cc: Shawn Guo <shawn.guo at freescale.com>
>> Cc: Sascha Hauer <s.hauer at pengutronix.de>
>> Cc: Jamie Iles <jamie at jamieiles.com>
>> Cc: Richard Zhao <richard.zhao at linaro.org>
>> Cc: Saravana Kannan <skannan at codeaurora.org>
>> Cc: Magnus Damm <magnus.damm at gmail.com>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
>> Cc: Linus Walleij <linus.walleij at stericsson.com>
>> Cc: Stephen Boyd <sboyd at codeaurora.org>
>> Cc: Amit Kucheria <amit.kucheria at linaro.org>
>> Cc: Deepak Saxena <dsaxena at linaro.org>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Cc: Andrew Lunn <andrew at lunn.ch>
>> ---
>> Changes since v5:
>>  * standardized the hw-specific locking in the basic clock types
>>  * export the individual ops for each basic clock type
>>  * improve registration for single-parent basic clocks (thanks Sascha)
>>  * fixed bugs in gate clock's static initializers (thanks Andrew)
>>
>>  drivers/clk/Makefile         |    3 +-
>>  drivers/clk/clk-divider.c    |  204 ++++++++++++++++++++++++++++++++++++++++++
>>  drivers/clk/clk-fixed-rate.c |   82 +++++++++++++++++
>>  drivers/clk/clk-gate.c       |  157 ++++++++++++++++++++++++++++++++
>>  drivers/clk/clk-mux.c        |  123 +++++++++++++++++++++++++
>>  include/linux/clk-private.h  |  124 +++++++++++++++++++++++++
>>  include/linux/clk-provider.h |  127 ++++++++++++++++++++++++++
>>  7 files changed, 819 insertions(+), 1 deletions(-)
>>  create mode 100644 drivers/clk/clk-divider.c
>>  create mode 100644 drivers/clk/clk-fixed-rate.c
>>  create mode 100644 drivers/clk/clk-gate.c
>>  create mode 100644 drivers/clk/clk-mux.c
>>
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index ff362c4..1f736bc 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -1,3 +1,4 @@
>>  
>>  obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
>> -obj-$(CONFIG_COMMON_CLK)	+= clk.o
>> +obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
>> +				   clk-mux.o clk-divider.o
>> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
>> new file mode 100644
>> index 0000000..c0c4e0b
>> --- /dev/null
>> +++ b/drivers/clk/clk-divider.c
>> @@ -0,0 +1,204 @@
>> +/*
>> + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
>> + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
>> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Adjustable divider clock implementation
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/string.h>
>> +
>> +/*
>> + * DOC: basic adjustable divider clock that cannot gate
>> + *
>> + * Traits of this clock:
>> + * prepare - clk_prepare only ensures that parents are prepared
>> + * enable - clk_enable only ensures that parents are enabled
>> + * rate - rate is adjustable.  clk->rate = parent->rate / divisor
>> + * parent - fixed parent.  No clk_set_parent support
>> + */
>> +
>> +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
>> +
>> +static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
>> +		unsigned long parent_rate)
>> +{
>> +	struct clk_divider *divider = to_clk_divider(hw);
>> +	unsigned int div;
>> +	unsigned long flags = 0;
>> +
>> +	if (divider->lock)
>> +		spin_lock_irqsave(divider->lock, flags);
>> +
>> +	div = readl(divider->reg) >> divider->shift;
>> +	div &= (1 << divider->width) - 1;
>> +
>> +	if (divider->lock)
>> +		spin_unlock_irqrestore(divider->lock, flags);
>> +
>> +	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
>> +		div++;
>> +
>> +	return parent_rate / div;
>> +}
>> +EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
>> +
>> +static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
>> +		unsigned long *best_parent_rate)
>> +{
>> +	struct clk_divider *divider = to_clk_divider(hw);
>> +	int i, bestdiv = 0;
>> +	unsigned long parent_rate, best = 0, now, maxdiv;
>> +
>> +	maxdiv = (1 << divider->width);
> 
> We need a check for rate == 0 here:
> 
> 	if (rate == 0)
> 		rate = 1;
> 
> Otherwise we divide by zero below.
> 
>> +
>> +	if (divider->flags & CLK_DIVIDER_ONE_BASED)
>> +		maxdiv--;
>> +
>> +	if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
>> +		parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
>> +		bestdiv = parent_rate / rate;
> 
> It's a bit strange but due to integer maths you must use DIV_ROUND_UP
> in round_rate and div = parent_rate / rate in set_rate.
> 
> Example:
> 
> parent_rate = 100
> rate = 34
> 
> Now the best divider would be 3 (100/3 = 33), but the above
> results in 2. With DIV_ROUND_UP round_rate correctly returns
> 33. Now when you use DIV_ROUND_UP in set_rate the resulting
> divider would be 4 which is wrong whereas 100/33 returns the correct
> result.

This gets into the problem with round_rate. You can't specify whether to
round up or down. For something like an SD card you would want to pass
in the max freq for the card and get back something less than or equal
to it. For something like an LCD pixel clock, you need a frequency
greater than or equal to the requested freq to maintain a minimum
refresh rate. There's been some discussion about this some time back.

But for now we shouldn't fix round_rate, and your solution is right (or
at least safer).

Rob


From augulis.darius at gmail.com  Wed Mar 14 14:39:04 2012
From: augulis.darius at gmail.com (Darius Augulis)
Date: Wed, 14 Mar 2012 20:39:04 +0200
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <000501cd0184$f088cb20$d19a6160$%han@samsung.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com>
Message-ID: <4F60E5C8.3040804@gmail.com>

On 03/14/2012 03:51 AM, Jingoo Han wrote:
>> -----Original Message-----
>> From: Thomas Abraham [mailto:thomas.abraham at linaro.org]
>> Sent: Tuesday, March 13, 2012 7:11 PM
>> To: Jingoo Han
>> Cc: linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-kernel at lists.infradead.org; linux-
>> samsung-soc at vger.kernel.org; kgene.kim at samsung.com; ben-linux at fluff.org; patches at linaro.org; Kyungmin
>> Park; JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter Korsgaard; Darius Augulis; Maurus
>> Cuelenaere
>> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
>>
>> On 13 March 2012 15:17, Jingoo Han<jg1.han at samsung.com>  wrote:
>>>> -----Original Message-----
>>>> From: Thomas Abraham [mailto:thomas.abraham at linaro.org]
>>>> Sent: Tuesday, March 13, 2012 6:00 AM
>>>> To: linux-fbdev at vger.kernel.org
>>>> Cc: FlorianSchandinat at gmx.de; linux-arm-kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org;
>>>> kgene.kim at samsung.com; jg1.han at samsung.com; ben-linux at fluff.org; patches at linaro.org; Kyungmin Park;
>>>> JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter Korsgaard; Darius Augulis; Maurus
>>>> Cuelenaere
>>>> Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
>>>>
>>>> For all the Samsung SoC based boards which have the platform data for
>>>> s3c-fb driver, the 'default_win' element in the platform data is removed
>>>> and the lcd panel video timing values are moved out of individual window
>>>> configuration data.
>>>>
>>>> Cc: Jingoo Han<jg1.han at samsung.com>
>>>> Cc: Kyungmin Park<kyungmin.park at samsung.com>
>>>> Cc: JeongHyeon Kim<jhkim at insignal.co.kr>
>>>> Cc: Kukjin Kim<kgene.kim at samsung.com>
>>>> Cc: Heiko Stuebner<heiko at sntech.de>
>>>> Cc: Ben Dooks<ben-linux at fluff.org>
>>>> Cc: Kwangwoo Lee<kwangwoo.lee at gmail.com>
>>>> Cc: Mark Brown<broonie at opensource.wolfsonmicro.com>
>>>> Cc: Peter Korsgaard<jacmet at sunsite.dk>
>>>> Cc: Darius Augulis<augulis.darius at gmail.com>
>>>> Cc: Maurus Cuelenaere<mcuelenaere at gmail.com>
>>>> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
>>>> ---
>>>>   arch/arm/mach-exynos/mach-nuri.c           |   26 ++++++++++-------
>>>>   arch/arm/mach-exynos/mach-origen.c         |   24 ++++++++++-------
>>>>   arch/arm/mach-exynos/mach-smdkv310.c       |   28 +++++++++++--------
>>>>   arch/arm/mach-exynos/mach-universal_c210.c |   26 ++++++++++-------
>>>>   arch/arm/mach-s3c24xx/mach-smdk2416.c      |   27 ++++++++++--------
>>>>   arch/arm/mach-s3c64xx/mach-anw6410.c       |   25 ++++++++++-------
>>>>   arch/arm/mach-s3c64xx/mach-crag6410.c      |   25 ++++++++++-------
>>>>   arch/arm/mach-s3c64xx/mach-hmt.c           |   24 ++++++++++-------
>>>>   arch/arm/mach-s3c64xx/mach-mini6410.c      |   40 ++++++++++++---------------
>>>>   arch/arm/mach-s3c64xx/mach-real6410.c      |   40 ++++++++++++---------------
>>>>   arch/arm/mach-s3c64xx/mach-smartq5.c       |   26 ++++++++++-------
>>>>   arch/arm/mach-s3c64xx/mach-smartq7.c       |   26 ++++++++++-------
>>>>   arch/arm/mach-s3c64xx/mach-smdk6410.c      |   25 ++++++++++-------
>>>>   arch/arm/mach-s5p64x0/mach-smdk6440.c      |   24 ++++++++++-------
>>>>   arch/arm/mach-s5p64x0/mach-smdk6450.c      |   24 ++++++++++-------
>>>>   arch/arm/mach-s5pc100/mach-smdkc100.c      |   27 ++++++++++--------
>>>>   arch/arm/mach-s5pv210/mach-aquila.c        |   36 +++++++++++--------------
>>>>   arch/arm/mach-s5pv210/mach-goni.c          |   26 ++++++++++-------
>>>>   arch/arm/mach-s5pv210/mach-smdkv210.c      |   24 ++++++++++-------
>>>>   19 files changed, 285 insertions(+), 238 deletions(-)
>>>>
>>> [.....]
>>>
>>>> diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
>>>> index c34c2ab..24dcdc9 100644
>>>> --- a/arch/arm/mach-s3c64xx/mach-mini6410.c
>>>> +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
>>>> @@ -153,36 +153,32 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
>>>>
>>>>   static struct s3c_fb_pd_win mini6410_fb_win[] = {
>>>>        {
>>>> -             .win_mode       = {     /* 4.3" 480x272 */
>>>> -                     .left_margin    = 3,
>>>> -                     .right_margin   = 2,
>>>> -                     .upper_margin   = 1,
>>>> -                     .lower_margin   = 1,
>>>> -                     .hsync_len      = 40,
>>>> -                     .vsync_len      = 1,
>>>> -                     .xres           = 480,
>>>> -                     .yres           = 272,
>>>> -             },
>>>>                .max_bpp        = 32,
>>>>                .default_bpp    = 16,
>>>> +             .xres           = 480,
>>>> +             .yres           = 272,
>>>>        }, {
>>>> -             .win_mode       = {     /* 7.0" 800x480 */
>>>> -                     .left_margin    = 8,
>>>> -                     .right_margin   = 13,
>>>> -                     .upper_margin   = 7,
>>>> -                     .lower_margin   = 5,
>>>> -                     .hsync_len      = 3,
>>>> -                     .vsync_len      = 1,
>>>> -                     .xres           = 800,
>>>> -                     .yres           = 480,
>>>> -             },
>>>>                .max_bpp        = 32,
>>>>                .default_bpp    = 16,
>>>> +             .xres           = 800,
>>>> +             .yres           = 480,
>>>>        },
>>>>   };
>>>>
>>>> +static struct fb_videomode mini6410_lcd_timing = {
>>>> +     .left_margin    = 8,
>>>> +     .right_margin   = 13,
>>>> +     .upper_margin   = 7,
>>>> +     .lower_margin   = 5,
>>>> +     .hsync_len      = 3,
>>>> +     .vsync_len      = 1,
>>>> +     .xres           = 800,
>>>> +     .yres           = 480,
>>>> +};
>>>> +
>>>>   static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
>>>>        .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
>>>> +     .vtiming        =&mini6410_lcd_timing,
>>>>        .win[0]         =&mini6410_fb_win[0],
>>>>        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>>>>        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>>>> @@ -310,8 +306,8 @@ static void __init mini6410_machine_init(void)
>>>>        mini6410_lcd_pdata.win[0] =&mini6410_fb_win[features.lcd_index];
>>>>
>>>>        printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
>>>> -             mini6410_lcd_pdata.win[0]->win_mode.xres,
>>>> -             mini6410_lcd_pdata.win[0]->win_mode.yres);
>>>> +             mini6410_lcd_pdata.win[0]->xres,
>>>> +             mini6410_lcd_pdata.win[0]->yres);
>>>>
>>>>        s3c_nand_set_platdata(&mini6410_nand_info);
>>>>        s3c_fb_set_platdata(&mini6410_lcd_pdata);
>>>> diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
>>>> index be2a9a2..41e4f74 100644
>>>> --- a/arch/arm/mach-s3c64xx/mach-real6410.c
>>>> +++ b/arch/arm/mach-s3c64xx/mach-real6410.c
>>>> @@ -119,36 +119,32 @@ static struct platform_device real6410_device_eth = {
>>>>
>>>>   static struct s3c_fb_pd_win real6410_fb_win[] = {
>>>>        {
>>>> -             .win_mode       = {     /* 4.3" 480x272 */
>>>> -                     .left_margin    = 3,
>>>> -                     .right_margin   = 2,
>>>> -                     .upper_margin   = 1,
>>>> -                     .lower_margin   = 1,
>>>> -                     .hsync_len      = 40,
>>>> -                     .vsync_len      = 1,
>>>> -                     .xres           = 480,
>>>> -                     .yres           = 272,
>>>> -             },
>>>>                .max_bpp        = 32,
>>>>                .default_bpp    = 16,
>>>> +             .xres           = 480,
>>>> +             .yres           = 272,
>>>>        }, {
>>>> -             .win_mode       = {     /* 7.0" 800x480 */
>>>> -                     .left_margin    = 8,
>>>> -                     .right_margin   = 13,
>>>> -                     .upper_margin   = 7,
>>>> -                     .lower_margin   = 5,
>>>> -                     .hsync_len      = 3,
>>>> -                     .vsync_len      = 1,
>>>> -                     .xres           = 800,
>>>> -                     .yres           = 480,
>>>> -             },
>>>>                .max_bpp        = 32,
>>>>                .default_bpp    = 16,
>>>> +             .xres           = 800,
>>>> +             .yres           = 480,
>>>>        },
>>>>   };
>>>>
>>>> +static struct fb_videomode real6410_lcd_timing = {
>>>> +     .left_margin    = 3,
>>>> +     .right_margin   = 2,
>>>> +     .upper_margin   = 1,
>>>> +     .lower_margin   = 1,
>>>> +     .hsync_len      = 40,
>>>> +     .vsync_len      = 1,
>>>> +     .xres           = 800,
>>>> +     .yres           = 480,
>>>> +};
>>>
>>> What is the difference between mini6410_lcd_timing and real6410_lcd_timing?
>>> In my opinion, it would be good as follows:
>>>
>>> +static struct fb_videomode real6410_lcd_timing = {
>>> +       .left_margin    = 8,
>>> +       .right_margin   = 13,
>>> +       .upper_margin   = 7,
>>> +       .lower_margin   = 5,
>>> +       .hsync_len      = 3,
>>> +       .vsync_len      = 1,
>>> +       .xres           = 800,
>>> +       .yres           = 480,
>>> +};
>>>
>>>
>> Before this patch series, both real6410 and mini6410 had 'default_win'
>> = 0 in the platform data. And, the s3c-fb driver selected the video
>> timing from the window selected by the default_win parameter in s3c-fb
>> platform data, i.e window 0 for both mini6440 and real6410. So, in
>> this patch, while moving the timing values out of window data, the
>> timing values for window 0 was selected.
>>
>> The timing value for window 1 was never used on mini6410 and real6410.
>> So I would suggest to use timing value of window 0 in this patch.
> OK, I see.
> Then, as you mentioned above, the timing value of mini6410 and real6410 should be same.
> Also, the mini6410 should use the timing value for window 0 as below.
>
> Also, this timing value is used for 4.3" 480x272 LCD.
> So, xres and yres would be 480 and 272, respectively, instead of 800 and 480.
>
> The mini6410 seems to use 4.3" 480x272 LCD as default LCD.
> Please refer to 'http://www.friendlyarm.net/products/mini6410'.
>
> Also, real6410 seems to use 4.3" 480x272 LCD as default LCD.
> http://s3c6410kits.googlecode.com/files/overview_Real6410.pdf
>
> Therefore, given this, the timing value of mini6410 and real6410 would be as follows.
>
> +static struct fb_videomode mini6410_lcd_timing = {
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 480,
> +	.yres		= 272,
> +};
>
> +static struct fb_videomode real6410_lcd_timing = {
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 480,
> +	.yres		= 272,
> +};
>
> Darius Augulis, can you confirm it?
> (Darius Augulis is a maintainer for real6410 and mini6410 boards.)

Are you going to leave only single LCD resolution for every of two 
boards? If so, then my answer is no.
I have mini6410 with both 4.3" and 7" LCDs and real6410 with 7" LCD. Now 
we have possibility to choose LCD size dynamically - leave it there.
What you mean "default" 4.3" size LCD? The 7" size LCD is also provided 
by board sellers - I've bought it.

regards,
Darius Augulis

>
> Best regards,
> Jingoo Han
>
>> Thanks for your comments.
>>
>> Regards,
>> Thomas.
>



From davej at redhat.com  Wed Mar 14 14:40:53 2012
From: davej at redhat.com (Dave Jones)
Date: Wed, 14 Mar 2012 14:40:53 -0400
Subject: [PATCH v2 RE-SEND] [CPUFREQ] EXYNOS5250: Add support cpufreq for
 EXYNOS5250
In-Reply-To: <4F60E25C.9060005@samsung.com>
References: <1331377202-25173-1-git-send-email-kgene.kim@samsung.com>
 <4F60D5FE.7080400@samsung.com> <20120314175703.GA3803@redhat.com>
 <4F60E25C.9060005@samsung.com>
Message-ID: <20120314184053.GC3803@redhat.com>

On Wed, Mar 14, 2012 at 11:24:28AM -0700, Kukjin Kim wrote:
 > 2012-03-14 ?? 10:57, Dave Jones ? ?:
 > > On Wed, Mar 14, 2012 at 10:31:42AM -0700, Kukjin Kim wrote:
 > >   >  Kukjin Kim wrote:
 > >   >  >  From: Jaecheol Lee<jc.lee at samsung.com>
 > >   >  >
 > >   >  >  This patch adds support cpufreq for EXYNOS5250 SoC. Basically,
 > >   >  >  the exynos-cpufreq.c is used commonly and exynos5250-cpufreq.c
 > >   >  >  is used for EXYNOS5250(two Cortex-A15 cores) SoC.
 > >   >  >
 > >   >  >  Signed-off-by: Jaecheol Lee<jc.lee at samsung.com>
 > >   >  >  Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
 > >   >
 > >   >  Hi again Dave :)
 > >   >
 > >   >  Please pick up this patch for v3.4.
 > >   >  If any problems, please kindly let us know.
 > >
 > > this, and the other patch doesn't apply against current cpufreq.git
 > >
 > Oops, maybe you applied this first. Pleae try again EXYNOS4X12 first 
 > then, this. I applied on top of cpufreq/next and there was no complain.
 > 
 > If any problems, please kindly let me know.

Applied and pushed. thanks!

	Dave
 


From sr at denx.de  Wed Mar 14 15:01:58 2012
From: sr at denx.de (Stefan Roese)
Date: Wed, 14 Mar 2012 20:01:58 +0100
Subject: [PATCH v2] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <20120314172435.GP18320@game.jcrosoft.org>
References: <1331737232-25477-1-git-send-email-sr@denx.de>
 <201203141749.05899.sr@denx.de> <20120314172435.GP18320@game.jcrosoft.org>
Message-ID: <201203142001.58762.sr@denx.de>

On Wednesday 14 March 2012 18:24:35 Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > > diff --git a/arch/arm/boot/dts/spear600-evb.dts
> > > > b/arch/arm/boot/dts/spear600-evb.dts new file mode 100644
> > > > index 0000000..cbfda8d
> > > > --- /dev/null
> > > > +++ b/arch/arm/boot/dts/spear600-evb.dts
> > > > @@ -0,0 +1,30 @@
> > > > +/*
> > > > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > > > + *
> > > > + * The code contained herein is licensed under the GNU General
> > > > Public + * License. You may obtain a copy of the GNU General Public
> > > > License + * Version 2 or later at the following locations:
> > > > + *
> > > > + * http://www.opensource.org/licenses/gpl-license.html
> > > > + * http://www.gnu.org/copyleft/gpl.html
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +/include/ "spear600.dtsi"
> > > > +
> > > > +/ {
> > > > +	model = "ST SPEAr600 Evaluation Board";
> > > > +	compatible = "st,spear600-evb", "st,spear600";
> > > > +	#address-cells = <1>;
> > > > +	#size-cells = <1>;
> > > 
> > > please put the mem size here
> > 
> > Might I ask why? Other *.dtsi files don't have it either.
> 
> do not expect the bootloader to put it. I t's not mandatory

But the memory node it is already present in spear600.dtsi (see below). Do we 
really need to duplicate this in the board specific dts file?
 
> > > > +
> > > > +	soc {
> > > > +		gmac0: ethernet at e0800000 {
> > > > +			phy-mode = "gmii";
> > > > +		};
> > > > +
> > > > +		i2c at d0200000 {
> > > > +			clock-frequency = <400000>;
> > > > +		};
> > > > +	};
> > > > +};
> > > > diff --git a/arch/arm/boot/dts/spear600.dtsi
> > > > b/arch/arm/boot/dts/spear600.dtsi new file mode 100644
> > > > index 0000000..e45e58f
> > > > --- /dev/null
> > > > +++ b/arch/arm/boot/dts/spear600.dtsi
> > > > @@ -0,0 +1,162 @@
> > > > +/*
> > > > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > > > + *
> > > > + * The code contained herein is licensed under the GNU General
> > > > Public + * License. You may obtain a copy of the GNU General Public
> > > > License + * Version 2 or later at the following locations:
> > > > + *
> > > > + * http://www.opensource.org/licenses/gpl-license.html
> > > > + * http://www.gnu.org/copyleft/gpl.html
> > > > + */
> > > > +
> > > > +/include/ "skeleton.dtsi"
> > > > +
> > > > +/ {
> > > > +	compatible = "st,spear600";
> > > > +
> > > > +	cpus {
> > > > +		cpu at 0 {
> > > > +			compatible = "arm,arm926ejs";
> > > > +		};
> > > > +	};
> > > > +
> > > > +	memory {
> > > > +		device_type = "memory";
> > > > +		reg = <0 0>; /* Filled by U-Boot */
> > > 
> > > please put the max mem of the SoC here
> > 
> > Why? It's always updated by the bootloader. And a max. mem size (when not
> > updated to the correct mem size by the bootloader) would crash the board
> > if it is equipped with less memory.
> 
> yes but we descripbe the soc here and on the dts you reduce it
> Never expect the bootloader to update it.

Without update to real size we're doomed.
 
> It's a possibility not mandatory

Okay, I'll add the max. size here.
 
> > > > +	};
> > > > +
> > > > +	soc {
> > > 
> > > please put the name of the bus not soc
> > 
> > Okay.
> > 
> > > > +		#address-cells = <1>;
> > > > +		#size-cells = <1>;
> > > > +		compatible = "simple-bus";
> > > > +		ranges;
> > > > +
> > > > +		vic0: interrupt-controller at f1100000 {
> > > > +			compatible = "arm,pl190-vic";
> > > > +			interrupt-controller;
> > > > +			reg = <0xf1100000 0x1000>;
> > > > +			#interrupt-cells = <1>;
> > > > +		};
> > > > +
> > > > +		vic1: interrupt-controller at f1000000 {
> > > > +			compatible = "arm,pl190-vic";
> > > > +			interrupt-controller;
> > > > +			reg = <0xf1000000 0x1000>;
> > > > +			#interrupt-cells = <1>;
> > > > +		};
> > > > +
> > > > +		serial at d0000000 {
> > > > +			compatible = "arm,pl011", "arm,primecell";
> > > > +			reg = <0xd0000000 0x1000>;
> > > > +			interrupt-parent = <&vic0>;
> > > > +			interrupts = <24>;
> > > > +		};
> > > > +
> > > > +		serial at d0080000 {
> > > > +			compatible = "arm,pl011", "arm,primecell";
> > > > +			reg = <0xd0080000 0x1000>;
> > > > +			interrupt-parent = <&vic0>;
> > > > +			interrupts = <25>;
> > > > +		};
> > > > +
> > > > +		/* local/cpu GPIO */
> > > > +		gpio0: gpio at f0100000 {
> > > > +			#gpio-cells = <2>;
> > > > +			compatible = "arm,pl061", "arm,primecell";
> > > > +			gpio-controller;
> > > > +			reg = <0xf0100000 0x1000>;
> > > > +			interrupt-parent = <&vic0>;
> > > > +			interrupts = <18>;
> > > > +		};
> > > > +
> > > > +		/* basic GPIO */
> > > > +		gpio1: gpio at fc980000 {
> > > > +			#gpio-cells = <2>;
> > > > +			compatible = "arm,pl061", "arm,primecell";
> > > > +			gpio-controller;
> > > > +			reg = <0xfc980000 0x1000>;
> > > > +			interrupt-parent = <&vic1>;
> > > > +			interrupts = <19>;
> > > > +		};
> > > > +
> > > > +		/* appl GPIO */
> > > > +		gpio2: gpio at d8100000 {
> > > > +			#gpio-cells = <2>;
> > > > +			compatible = "arm,pl061", "arm,primecell";
> > > > +			gpio-controller;
> > > > +			reg = <0xd8100000 0x1000>;
> > > > +			interrupt-parent = <&vic1>;
> > > > +			interrupts = <4>;
> > > > +		};
> > > > +
> > > > +		gmac0: ethernet at e0800000 {
> > > > +			compatible = "st,spear600-gmac";
> > > > +			reg = <0xe0800000 0x8000>;
> > > > +			interrupt-parent = <&vic1>;
> > > > +			interrupts = <24 23>;
> > > > +			interrupt-names = "macirq", "eth_wake_irq";
> > > > +			mac-address = [000000000000]; /* Filled in 
by U-Boot
> > 
> > */
> 
> drop this no dummy data

Okay.

> > > > +		};
> > > > +
> > > > +		i2c at d0200000 {
> > > > +			#address-cells = <1>;
> > > > +			#size-cells = <0>;
> > > > +			compatible = "snps,designware-i2c";
> > > > +			reg = <0xd0200000 0x1000>;
> > > > +			interrupt-parent = <&vic0>;
> > > > +			interrupts = <28>;
> > > > +		};
> > > > +
> > > > +		fsmc0: flash at d1800000 {
> > > > +			status = "disabled";
> > > > +			compatible = "st,spear600-fsmc-nand";
> > > > +			#address-cells = <1>;
> > > > +			#size-cells = <1>;
> > > > +			reg = <0xd1800000 0x1000	/* FSMC 
Register */
> > > > +			       0xd2000000 0x4000>;	/* NAND Base 
*/
> > > > +			reg-names = "fsmc_regs", "nand_data";
> > > > +		};
> > > > +
> > > > +		smi0: flash at fc000000 {
> > > > +			status = "disabled";
> > > > +			compatible = "st,spear600-smi";
> > > > +			#address-cells = <1>;
> > > > +			#size-cells = <1>;
> > > > +			reg = <0xfc000000 0x1000>;
> > > > +			interrupt-parent = <&vic1>;
> > > > +			interrupts = <12>;
> > > > +		};
> > > > +
> > > > +		ehci at e1800000 {
> > > > +			status = "disabled";
> > > > +			compatible = "st,spear600-ehci", "usb-ehci";
> > > > +			reg = <0xe1800000 0x1000>;
> > > > +			interrupt-parent = <&vic1>;
> > > > +			interrupts = <27>;
> > > > +		};
> > > > +
> > > > +		ehci at e2000000 {
> > > > +			status = "disabled";
> > > > +			compatible = "st,spear600-ehci", "usb-ehci";
> > > > +			reg = <0xe2000000 0x1000>;
> > > > +			interrupt-parent = <&vic1>;
> > > > +			interrupts = <29>;
> > > > +		};
> > > > +
> > > > +		ohci at e1900000 {
> > > > +			status = "disabled";
> > > > +			compatible = "st,spear600-ohci", "usb-ohci";
> > > > +			reg = <0xe1900000 0x1000>;
> > > > +			interrupt-parent = <&vic1>;
> > > > +			interrupts = <26>;
> > > > +		};
> > > > +
> > > > +		ohci at e2100000 {
> > > > +			status = "disabled";
> > > > +			compatible = "st,spear600-ohci", "usb-ohci";
> > > > +			reg = <0xe2100000 0x1000>;
> > > > +			interrupt-parent = <&vic1>;
> > > > +			interrupts = <28>;
> > > > +		};
> > > 
> > > all of this need a Doc for the ST bindings
> > 
> > Sure. I only provided those nodes on Arnd's special request. They are
> > currently disabled. And documentation will follow with the DT device
> > driver patches.
> 
> no update it after

Hmmm. I'm sorry, but I fail to understand you here. Please explain.
 
> > > > +	};
> > > > +};
> > > > diff --git a/arch/arm/mach-spear6xx/Kconfig
> > > > b/arch/arm/mach-spear6xx/Kconfig index ff4ae5b..7777f72 100644
> > > > --- a/arch/arm/mach-spear6xx/Kconfig
> > > > +++ b/arch/arm/mach-spear6xx/Kconfig
> > > > @@ -11,6 +11,13 @@ config BOARD_SPEAR600_EVB
> > > > 
> > > >  	help
> > > >  	
> > > >  	  Supports ST SPEAr600 Evaluation Board
> > > > 
> > > > +config BOARD_SPEAR600_DT
> > > > +	bool "SPEAr600 generic board configured via device-tree"
> > > > +	select MACH_SPEAR600
> > > > +	select USE_OF
> > > > +	help
> > > > +	  Supports ST SPEAr600 boards configured via the device-tree
> > > > +
> > > > 
> > > >  endmenu
> > > >  
> > > >  config MACH_SPEAR600
> > > > 
> > > > diff --git a/arch/arm/mach-spear6xx/Makefile
> > > > b/arch/arm/mach-spear6xx/Makefile index cc1a4d8..6f87c3a 100644
> > > > --- a/arch/arm/mach-spear6xx/Makefile
> > > > +++ b/arch/arm/mach-spear6xx/Makefile
> > > > @@ -5,8 +5,5 @@
> > > > 
> > > >  # common files
> > > >  obj-y	+= clock.o spear6xx.o
> > > > 
> > > > -# spear600 specific files
> > > > -obj-$(CONFIG_MACH_SPEAR600) += spear600.o
> > > > -
> > > > 
> > > >  # spear600 boards files
> > > >  obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
> > > > 
> > > > diff --git a/arch/arm/mach-spear6xx/spear600.c
> > > > b/arch/arm/mach-spear6xx/spear600.c deleted file mode 100644
> > > > index d0e6eea..0000000
> > > > --- a/arch/arm/mach-spear6xx/spear600.c
> > > > +++ /dev/null
> > > > @@ -1,25 +0,0 @@
> > > > -/*
> > > > - * arch/arm/mach-spear6xx/spear600.c
> > > > - *
> > > > - * SPEAr600 machine source file
> > > > - *
> > > > - * Copyright (C) 2009 ST Microelectronics
> > > > - * Rajeev Kumar<rajeev-dlh.kumar at st.com>
> > > > - *
> > > > - * This file is licensed under the terms of the GNU General Public
> > > > - * License version 2. This program is licensed "as is" without any
> > > > - * warranty of any kind, whether express or implied.
> > > > - */
> > > > -
> > > > -#include <linux/ptrace.h>
> > > > -#include <asm/irq.h>
> > > > -#include <mach/generic.h>
> > > > -#include <mach/hardware.h>
> > > > -
> > > > -/* Add spear600 specific devices here */
> > > > -
> > > > -void __init spear600_init(void)
> > > > -{
> > > > -	/* call spear6xx family common init function */
> > > > -	spear6xx_init();
> > > > -}
> > > > diff --git a/arch/arm/mach-spear6xx/spear600_evb.c
> > > > b/arch/arm/mach-spear6xx/spear600_evb.c index c6e4254..c4949aa 100644
> > > > --- a/arch/arm/mach-spear6xx/spear600_evb.c
> > > > +++ b/arch/arm/mach-spear6xx/spear600_evb.c
> > > > @@ -32,9 +32,6 @@ static void __init spear600_evb_init(void)
> > > > 
> > > >  {
> > > >  
> > > >  	unsigned int i;
> > > > 
> > > > -	/* call spear600 machine init function */
> > > > -	spear600_init();
> > > > -
> > > > 
> > > >  	/* Add Platform Devices */
> > > >  	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
> > > > 
> > > > diff --git a/arch/arm/mach-spear6xx/spear6xx.c
> > > > b/arch/arm/mach-spear6xx/spear6xx.c index e0f6628..aca20f0 100644
> > > > --- a/arch/arm/mach-spear6xx/spear6xx.c
> > > > +++ b/arch/arm/mach-spear6xx/spear6xx.c
> > > > @@ -6,6 +6,8 @@
> > > > 
> > > >   * Copyright (C) 2009 ST Microelectronics
> > > >   * Rajeev Kumar<rajeev-dlh.kumar at st.com>
> > > >   *
> > > > 
> > > > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > > > + *
> > > > 
> > > >   * This file is licensed under the terms of the GNU General Public
> > > >   * License version 2. This program is licensed "as is" without any
> > > >   * warranty of any kind, whether express or implied.
> > > > 
> > > > @@ -15,6 +17,10 @@
> > > > 
> > > >  #include <linux/amba/pl061.h>
> > > >  #include <linux/ptrace.h>
> > > >  #include <linux/io.h>
> > > > 
> > > > +#include <linux/of.h>
> > > > +#include <linux/of_address.h>
> > > > +#include <linux/of_irq.h>
> > > > +#include <linux/of_platform.h>
> > > > 
> > > >  #include <asm/hardware/vic.h>
> > > >  #include <asm/irq.h>
> > > >  #include <asm/mach/arch.h>
> > > > 
> > > > @@ -99,12 +105,6 @@ struct amba_device gpio_device[] = {
> > > > 
> > > >  	}
> > > >  
> > > >  };
> > > > 
> > > > -/* This will add devices, and do machine specific tasks */
> > > > -void __init spear6xx_init(void)
> > > > -{
> > > > -	/* nothing to do for now */
> > > > -}
> > > > -
> > > > 
> > > >  /* This will initialize vic */
> > > >  void __init spear6xx_init_irq(void)
> > > >  {
> > > > 
> > > > @@ -181,3 +181,60 @@ static void __init spear6xx_timer_init(void)
> > > > 
> > > >  struct sys_timer spear6xx_timer = {
> > > >  
> > > >  	.init = spear6xx_timer_init,
> > > >  
> > > >  };
> > > > 
> > > > +
> > > > +/*
> > > > + * Devicetree specific init structs/functions:
> > > > + * Once the SPEAr600 devicetree support has matured, we can remove
> > > > + * spear600_evb.c and the non-devicetree support above in this file.
> > > > + */
> > > > +
> > > > +/*
> > > > + * Add auxdata so that clock name matching doesn't fail in device
> > > > + * drivers
> > > > + */
> > > > +struct of_dev_auxdata spear600_auxdata_lookup[] __initdata = {
> > > > +	OF_DEV_AUXDATA("arm,pl011", SPEAR6XX_ICM1_UART0_BASE,
> > > > +		       "uart0", NULL),
> > > > +	OF_DEV_AUXDATA("arm,pl011", SPEAR6XX_ICM1_UART1_BASE,
> > > > +		       "uart1", NULL),
> > > > +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_CPU_GPIO_BASE,
> > > > +		       "gpio0", NULL),
> > > > +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_ICM3_GPIO_BASE,
> > > > +		       "gpio1", NULL),
> > > > +	OF_DEV_AUXDATA("arm,pl061", SPEAR6XX_ICM2_GPIO_BASE,
> > > > +		       "gpio2", NULL),
> > > > +	OF_DEV_AUXDATA("snps,designware-i2c", SPEAR6XX_ICM1_I2C_BASE,
> > > > +		       "i2c_designware.0", NULL),
> > > 
> > > update the clkdev no more OF_DEV_AUXDATA
> > 
> > That will break non-DT boards. We can change it in clkdev later, once DT
> > support has stabalized for SPEAr600. And remove all this then.
> 
> it will not just add new entry
> 
> as done on AT91 as example and requested for imx recently too

Again, I fail to understand you. Sorry. Please describe in a complete sentence 
what exactly you mean.

Thanks,
Stefan


From augulis.darius at gmail.com  Wed Mar 14 15:08:11 2012
From: augulis.darius at gmail.com (Darius Augulis)
Date: Wed, 14 Mar 2012 21:08:11 +0200
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
Message-ID: <4F60EC9B.9040409@gmail.com>

On 03/13/2012 12:10 PM, Thomas Abraham wrote:
> On 13 March 2012 15:17, Jingoo Han<jg1.han at samsung.com>  wrote:
>>> -----Original Message-----
>>> From: Thomas Abraham [mailto:thomas.abraham at linaro.org]
>>> Sent: Tuesday, March 13, 2012 6:00 AM
>>> To: linux-fbdev at vger.kernel.org
>>> Cc: FlorianSchandinat at gmx.de; linux-arm-kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org;
>>> kgene.kim at samsung.com; jg1.han at samsung.com; ben-linux at fluff.org; patches at linaro.org; Kyungmin Park;
>>> JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter Korsgaard; Darius Augulis; Maurus
>>> Cuelenaere
>>> Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
>>>
>>> For all the Samsung SoC based boards which have the platform data for
>>> s3c-fb driver, the 'default_win' element in the platform data is removed
>>> and the lcd panel video timing values are moved out of individual window
>>> configuration data.
>>>
>>> Cc: Jingoo Han<jg1.han at samsung.com>
>>> Cc: Kyungmin Park<kyungmin.park at samsung.com>
>>> Cc: JeongHyeon Kim<jhkim at insignal.co.kr>
>>> Cc: Kukjin Kim<kgene.kim at samsung.com>
>>> Cc: Heiko Stuebner<heiko at sntech.de>
>>> Cc: Ben Dooks<ben-linux at fluff.org>
>>> Cc: Kwangwoo Lee<kwangwoo.lee at gmail.com>
>>> Cc: Mark Brown<broonie at opensource.wolfsonmicro.com>
>>> Cc: Peter Korsgaard<jacmet at sunsite.dk>
>>> Cc: Darius Augulis<augulis.darius at gmail.com>
>>> Cc: Maurus Cuelenaere<mcuelenaere at gmail.com>
>>> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
>>> ---
>>>   arch/arm/mach-exynos/mach-nuri.c           |   26 ++++++++++-------
>>>   arch/arm/mach-exynos/mach-origen.c         |   24 ++++++++++-------
>>>   arch/arm/mach-exynos/mach-smdkv310.c       |   28 +++++++++++--------
>>>   arch/arm/mach-exynos/mach-universal_c210.c |   26 ++++++++++-------
>>>   arch/arm/mach-s3c24xx/mach-smdk2416.c      |   27 ++++++++++--------
>>>   arch/arm/mach-s3c64xx/mach-anw6410.c       |   25 ++++++++++-------
>>>   arch/arm/mach-s3c64xx/mach-crag6410.c      |   25 ++++++++++-------
>>>   arch/arm/mach-s3c64xx/mach-hmt.c           |   24 ++++++++++-------
>>>   arch/arm/mach-s3c64xx/mach-mini6410.c      |   40 ++++++++++++---------------
>>>   arch/arm/mach-s3c64xx/mach-real6410.c      |   40 ++++++++++++---------------
>>>   arch/arm/mach-s3c64xx/mach-smartq5.c       |   26 ++++++++++-------
>>>   arch/arm/mach-s3c64xx/mach-smartq7.c       |   26 ++++++++++-------
>>>   arch/arm/mach-s3c64xx/mach-smdk6410.c      |   25 ++++++++++-------
>>>   arch/arm/mach-s5p64x0/mach-smdk6440.c      |   24 ++++++++++-------
>>>   arch/arm/mach-s5p64x0/mach-smdk6450.c      |   24 ++++++++++-------
>>>   arch/arm/mach-s5pc100/mach-smdkc100.c      |   27 ++++++++++--------
>>>   arch/arm/mach-s5pv210/mach-aquila.c        |   36 +++++++++++--------------
>>>   arch/arm/mach-s5pv210/mach-goni.c          |   26 ++++++++++-------
>>>   arch/arm/mach-s5pv210/mach-smdkv210.c      |   24 ++++++++++-------
>>>   19 files changed, 285 insertions(+), 238 deletions(-)
>>>
>> [.....]
>>
>>> diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
>>> index c34c2ab..24dcdc9 100644
>>> --- a/arch/arm/mach-s3c64xx/mach-mini6410.c
>>> +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
>>> @@ -153,36 +153,32 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
>>>
>>>   static struct s3c_fb_pd_win mini6410_fb_win[] = {
>>>        {
>>> -             .win_mode       = {     /* 4.3" 480x272 */
>>> -                     .left_margin    = 3,
>>> -                     .right_margin   = 2,
>>> -                     .upper_margin   = 1,
>>> -                     .lower_margin   = 1,
>>> -                     .hsync_len      = 40,
>>> -                     .vsync_len      = 1,
>>> -                     .xres           = 480,
>>> -                     .yres           = 272,
>>> -             },
>>>                .max_bpp        = 32,
>>>                .default_bpp    = 16,
>>> +             .xres           = 480,
>>> +             .yres           = 272,
>>>        }, {
>>> -             .win_mode       = {     /* 7.0" 800x480 */
>>> -                     .left_margin    = 8,
>>> -                     .right_margin   = 13,
>>> -                     .upper_margin   = 7,
>>> -                     .lower_margin   = 5,
>>> -                     .hsync_len      = 3,
>>> -                     .vsync_len      = 1,
>>> -                     .xres           = 800,
>>> -                     .yres           = 480,
>>> -             },
>>>                .max_bpp        = 32,
>>>                .default_bpp    = 16,
>>> +             .xres           = 800,
>>> +             .yres           = 480,
>>>        },
>>>   };
>>>
>>> +static struct fb_videomode mini6410_lcd_timing = {
>>> +     .left_margin    = 8,
>>> +     .right_margin   = 13,
>>> +     .upper_margin   = 7,
>>> +     .lower_margin   = 5,
>>> +     .hsync_len      = 3,
>>> +     .vsync_len      = 1,
>>> +     .xres           = 800,
>>> +     .yres           = 480,
>>> +};
>>> +
>>>   static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
>>>        .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
>>> +     .vtiming        =&mini6410_lcd_timing,
>>>        .win[0]         =&mini6410_fb_win[0],
>>>        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>>>        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>>> @@ -310,8 +306,8 @@ static void __init mini6410_machine_init(void)
>>>        mini6410_lcd_pdata.win[0] =&mini6410_fb_win[features.lcd_index];
>>>
>>>        printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
>>> -             mini6410_lcd_pdata.win[0]->win_mode.xres,
>>> -             mini6410_lcd_pdata.win[0]->win_mode.yres);
>>> +             mini6410_lcd_pdata.win[0]->xres,
>>> +             mini6410_lcd_pdata.win[0]->yres);
>>>
>>>        s3c_nand_set_platdata(&mini6410_nand_info);
>>>        s3c_fb_set_platdata(&mini6410_lcd_pdata);
>>> diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
>>> index be2a9a2..41e4f74 100644
>>> --- a/arch/arm/mach-s3c64xx/mach-real6410.c
>>> +++ b/arch/arm/mach-s3c64xx/mach-real6410.c
>>> @@ -119,36 +119,32 @@ static struct platform_device real6410_device_eth = {
>>>
>>>   static struct s3c_fb_pd_win real6410_fb_win[] = {
>>>        {
>>> -             .win_mode       = {     /* 4.3" 480x272 */
>>> -                     .left_margin    = 3,
>>> -                     .right_margin   = 2,
>>> -                     .upper_margin   = 1,
>>> -                     .lower_margin   = 1,
>>> -                     .hsync_len      = 40,
>>> -                     .vsync_len      = 1,
>>> -                     .xres           = 480,
>>> -                     .yres           = 272,
>>> -             },
>>>                .max_bpp        = 32,
>>>                .default_bpp    = 16,
>>> +             .xres           = 480,
>>> +             .yres           = 272,
>>>        }, {
>>> -             .win_mode       = {     /* 7.0" 800x480 */
>>> -                     .left_margin    = 8,
>>> -                     .right_margin   = 13,
>>> -                     .upper_margin   = 7,
>>> -                     .lower_margin   = 5,
>>> -                     .hsync_len      = 3,
>>> -                     .vsync_len      = 1,
>>> -                     .xres           = 800,
>>> -                     .yres           = 480,
>>> -             },
>>>                .max_bpp        = 32,
>>>                .default_bpp    = 16,
>>> +             .xres           = 800,
>>> +             .yres           = 480,
>>>        },
>>>   };
>>>
>>> +static struct fb_videomode real6410_lcd_timing = {
>>> +     .left_margin    = 3,
>>> +     .right_margin   = 2,
>>> +     .upper_margin   = 1,
>>> +     .lower_margin   = 1,
>>> +     .hsync_len      = 40,
>>> +     .vsync_len      = 1,
>>> +     .xres           = 800,
>>> +     .yres           = 480,
>>> +};
>>
>> What is the difference between mini6410_lcd_timing and real6410_lcd_timing?
>> In my opinion, it would be good as follows:
>>
>> +static struct fb_videomode real6410_lcd_timing = {
>> +       .left_margin    = 8,
>> +       .right_margin   = 13,
>> +       .upper_margin   = 7,
>> +       .lower_margin   = 5,
>> +       .hsync_len      = 3,
>> +       .vsync_len      = 1,
>> +       .xres           = 800,
>> +       .yres           = 480,
>> +};
>>
>>
> Before this patch series, both real6410 and mini6410 had 'default_win'
> = 0 in the platform data. And, the s3c-fb driver selected the video
> timing from the window selected by the default_win parameter in s3c-fb
> platform data, i.e window 0 for both mini6440 and real6410. So, in
> this patch, while moving the timing values out of window data, the
> timing values for window 0 was selected.
>
> The timing value for window 1 was never used on mini6410 and real6410.
> So I would suggest to use timing value of window 0 in this patch.

You are wrong. Please see mini6410_parse_features(). Please do not 
remove second window because it could be selected via kernel parameters 
dinamically. It's very useful and I spend my hours to create it.

>
> Thanks for your comments.
>
> Regards,
> Thomas.
>



From s.hauer at pengutronix.de  Wed Mar 14 15:22:49 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 14 Mar 2012 20:22:49 +0100
Subject: [GIT PULL] i.MX35 3ds updates
Message-ID: <20120314192249.GR3852@pengutronix.de>

Hi Arnd, Olof,

Please pull the following board updates for the i.MX35 3ds board.

Sascha

The following changes since commit 192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d:

  Linux 3.3-rc6 (2012-03-03 17:08:09 -0800)

are available in the git repository at:

  git://git.pengutronix.de/git/imx/linux-2.6.git tags/imx35-cam-fb

for you to fetch changes up to 25af2d9f85750bb129eb224b7b3a07d3c93d282d:

  i.MX35-PDK: Add Camera support (2012-03-14 20:16:09 +0100)

----------------------------------------------------------------
ARM i.MX35 3ds: Framebuffer and camera support

----------------------------------------------------------------
Alex Gershgorin (1):
      i.MX35-PDK: Add Camera support

wu guoxing (1):
      ARM : mx35: 3ds-board: add framebuffer device

 arch/arm/mach-imx/mach-mx35_3ds.c |  216 +++++++++++++++++++++++++++++++++++++
 1 files changed, 216 insertions(+), 0 deletions(-)
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Mar 14 15:24:50 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 14 Mar 2012 20:24:50 +0100
Subject: Want to Get Suggestion for MX28 USB Submisson
In-Reply-To: <F281D0F91ED19E4D8E63A7504E8A6498093839@039-SN2MPN1-021.039d.mgd.msft.net>
References: <35AB98346D25394A9354ED89C4D76587225CFF@039-SN1MPN1-002.039d.mgd.msft.net>
 <201202041117.48190.marek.vasut@gmail.com>
 <F281D0F91ED19E4D8E63A7504E8A6498033336@039-SN2MPN1-021.039d.mgd.msft.net>
 <201202100447.14248.marek.vasut@gmail.com>
 <CAOMZO5C3Y3kP5k_CKkCVMVdDem2T82g6F3uL=8GCVfNKHpdymA@mail.gmail.com>
 <F281D0F91ED19E4D8E63A7504E8A6498093839@039-SN2MPN1-021.039d.mgd.msft.net>
Message-ID: <20120314192450.GS3852@pengutronix.de>

On Wed, Mar 14, 2012 at 03:30:26AM +0000, Chen Peter-B29397 wrote:
>  
> > 
> > Hi Peter,
> > 
> > On Fri, Feb 10, 2012 at 1:47 AM, Marek Vasut <marek.vasut at gmail.com>
> > wrote:
> > 
> > > Oh, so you're still working on it. All right then, I'll now dive into
> > the IIO
> > > LRADC driver and let you handle this.
> > 
> > Do you plan to re-submit the mxs usb driver?
> > 
> According to sascha's suggestion, it is better to re-submit after we have
> a generic USB PHY Layer in mainline.
> 
> Currently, Heikki's split PHY from OTG structure patches have mainlined, 
> next step is to submit a generic USB PHY driver.
> 

Cool, sounds like we get dt bindings for the i.MX ehci/otg ;)

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Mar 14 15:41:23 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 14 Mar 2012 20:41:23 +0100
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <1331628428-24017-2-git-send-email-b29396@freescale.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
Message-ID: <20120314194123.GR26642@pengutronix.de>

On Tue, Mar 13, 2012 at 04:47:04PM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> This patch includes basic dt support which can boot via nfs rootfs.
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
>  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
>  arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
>  arch/arm/boot/dts/imx28.dtsi                  |   88 +++++++++++++++++++++++++
>  arch/arm/mach-mxs/Kconfig                     |    9 +++
>  arch/arm/mach-mxs/Makefile                    |    1 +
>  arch/arm/mach-mxs/imx28-dt.c                  |   67 +++++++++++++++++++
>  6 files changed, 200 insertions(+), 0 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> index 54bddda..9f21faf 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -1,6 +1,10 @@

> +
> +static const char *imx28_dt_compat[] __initdata = {
> +	"fsl,imx28-evk",
> +	NULL,
> +};
> +

I suggest to add a generic "fsl,imx28" entry here. It helps people to
start an unpatched kernel on their boards.

Sascha

> +DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
> +	.map_io		= mx28_map_io,
> +	.init_irq	= imx28_dt_init_irq,
> +	.timer		= &imx28_timer,
> +	.init_machine	= imx28_init,
> +	.dt_compat	= imx28_dt_compat,
> +	.restart	= mxs_restart,
> +MACHINE_END
> -- 
> 1.7.0.4
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From u.kleine-koenig at pengutronix.de  Wed Mar 14 15:51:20 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 14 Mar 2012 20:51:20 +0100
Subject: [PATCH v3 1/5] ARM: protect usage of cr_alignment by #ifdef
 CONFIG_CPU_CP15
In-Reply-To: <alpine.LFD.2.02.1203141103080.24151@xanadu.home>
References: <20120314101928.GA29474@pengutronix.de>
 <1331720483-10075-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <alpine.LFD.2.02.1203141103080.24151@xanadu.home>
Message-ID: <20120314195120.GA2391@pengutronix.de>

On Wed, Mar 14, 2012 at 11:24:36AM -0400, Nicolas Pitre wrote:
> On Wed, 14 Mar 2012, Uwe Kleine-K?nig wrote:
> 
> > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> 
> I think you could reduce the amount of #ifdef's significantly here.  
> While the cr_alignment variable and its sister are of no use in a 
> no-CP15 system, you could still leave them there initialized to zero and 
> only conditionally compile out the CP15 modifyers with a dummy version.  
> This is only 2 words wasted in your kernel image to keep the code 
> cleaner.
The main purpose to create this patch is that for v7m I don't compile
entry-armv.S. As cr_alignment is defined there I don't "have" this
variable. So I have to move the definition to a different file to waste
it :-)

> More comments below.
> 
> > index 854bd22..efeb2d0 100644
> > --- a/arch/arm/kernel/head-common.S
> > +++ b/arch/arm/kernel/head-common.S
> > @@ -98,8 +98,10 @@ __mmap_switched:
> >  	str	r9, [r4]			@ Save processor ID
> >  	str	r1, [r5]			@ Save machine type
> >  	str	r2, [r6]			@ Save atags pointer
> > -	bic	r4, r0, #CR_A			@ Clear 'A' bit
> > -	stmia	r7, {r0, r4}			@ Save control register values
> > +	cmp	r7, #0
> > +	itt	ne
> > +	bicne	r4, r0, #CR_A			@ Clear 'A' bit
> > +	stmneia	r7, {r0, r4}			@ Save control register values
> 
> The kernel is compiled with -mimplicit-it so you do not need to specify 
> any it here.
ok
 
> > index a255c39..50d3df8 100644
> > --- a/arch/arm/kernel/setup.c
> > +++ b/arch/arm/kernel/setup.c
> > @@ -472,9 +472,13 @@ static void __init setup_processor(void)
> >  	cpu_cache = *list->cache;
> >  #endif
> >  
> > -	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
> > +	printk("CPU: %s [%08x] revision %d (ARMv%s)",
> >  	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
> > -	       proc_arch[cpu_architecture()], cr_alignment);
> > +	       proc_arch[cpu_architecture()]);
> > +
> > +#ifdef CONFIG_CPU_CP15
> > +	printk(KERN_CONT ", cr=%08lx\n", cr_alignment);
> > +#endif
> >  
> 
> Again, you could just leave the original display, with cr=00000000 which 
> is a fairly good representation of reality.
Maybe having

	#define cr_alignment 0

for the !CONFIG_CPU_CP15 case would be a nice alternative. This way all
places that want to modify cr_alignment fail to compile, but reading
gives a "fairly good representation of reality".

Having said that I'm not sure about "fairly good". v7m also supports
unaligned accesses. But it's not configured in a cp15 register
(obviously) but in a system register. Quoting ARMARM-v7m:

	Configuration and Control Register, CCR
	[...]
	Bit [3] UNALIGN_TRP	Controls the trapping of unaligned word or
				halfword accesses:
				0 = Trapping disabled.
				1 = Trapping enabled.
				Unaligned load-store multiples and word
				or halfword exclusive accesses always
				fault.

So we need a more general abstraction to have correct and clean code?

But note I didn't check the two different implementations deeply to be
sure not to compare two different things.

> > diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
> > index caf14dc..119d178 100644
> > --- a/arch/arm/mm/alignment.c
> > +++ b/arch/arm/mm/alignment.c
> > @@ -89,7 +89,11 @@ core_param(alignment, ai_usermode, int, 0600);
> >  /* Return true if and only if the ARMv6 unaligned access model is in use. */
> >  static bool cpu_is_v6_unaligned(void)
> >  {
> > +#ifdef CONFIG_CPU_CP15
> >  	return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
> > +#else
> > +	return 0;
> > +#endif
> >  }
> 
> Same here.  With cr_alignment set to zero, you don't need the above 
> #ifdef.
> 
> >  static int safe_usermode(int new_usermode, bool warn)
> > @@ -961,12 +965,14 @@ static int __init alignment_init(void)
> >  		return -ENOMEM;
> >  #endif
> >  
> > +#ifdef CONFIG_CPU_CP15
> >  	if (cpu_is_v6_unaligned()) {
> >  		cr_alignment &= ~CR_A;
> >  		cr_no_alignment &= ~CR_A;
> >  		set_cr(cr_alignment);
> >  		ai_usermode = safe_usermode(ai_usermode, false);
> >  	}
> > +#endif
> 
> Here the #ifdef is probably legitimate.
> 
> >  	hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
> >  			"alignment exception");
> > diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> > index 94c5a0c..f6dbe1a 100644
> > --- a/arch/arm/mm/mmu.c
> > +++ b/arch/arm/mm/mmu.c
> > @@ -109,8 +109,10 @@ static int __init early_cachepolicy(char *p)
> >  
> >  		if (memcmp(p, cache_policies[i].policy, len) == 0) {
> >  			cachepolicy = i;
> > +#ifdef CONFIG_CPU_CP15
> >  			cr_alignment &= ~cache_policies[i].cr_mask;
> >  			cr_no_alignment &= ~cache_policies[i].cr_mask;
> > +#endif
> 
> Probably here as well.
> 
> >  			break;
> >  		}
> >  	}
> > @@ -128,7 +130,9 @@ static int __init early_cachepolicy(char *p)
> >  		cachepolicy = CPOLICY_WRITEBACK;
> >  	}
> >  	flush_cache_all();
> > +#ifdef CONFIG_CPU_CP15
> >  	set_cr(cr_alignment);
> > +#endif
> 
> However it might be best to provide a dummy set_cr() instead of 
> #ifdef'ing it out everywhere.
What should the dummy set_cr do? Print a runtime warning if called with
!= 0?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From sboyd at codeaurora.org  Wed Mar 14 16:00:56 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Wed, 14 Mar 2012 13:00:56 -0700
Subject: [PATCH] ARM: Kconfig: Remove duplicate IRQ Kconfig entries
Message-ID: <1331755256-31163-1-git-send-email-sboyd@codeaurora.org>

These kconfig entries are already defined in kernel/irq/Kconfig
so select them instead of redefining them.

Cc: Thomas Gleixner <tglx at linutronix.de>
Signed-off-by: Stephen Boyd <sboyd at codeaurora.org>
---
 arch/arm/Kconfig |   10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7a08e37..a3ae6e9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -30,6 +30,8 @@ config ARM
 	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
 	select HAVE_C_RECORDMCOUNT
 	select HAVE_GENERIC_HARDIRQS
+	select HARDIRQS_SW_RESEND
+	select GENERIC_IRQ_PROBE
 	select GENERIC_IRQ_SHOW
 	select CPU_PM if (SUSPEND || CPU_IDLE)
 	select GENERIC_PCI_IOMAP
@@ -125,14 +127,6 @@ config TRACE_IRQFLAGS_SUPPORT
 	bool
 	default y
 
-config HARDIRQS_SW_RESEND
-	bool
-	default y
-
-config GENERIC_IRQ_PROBE
-	bool
-	default y
-
 config GENERIC_LOCKBREAK
 	bool
 	default y
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From u.kleine-koenig at pengutronix.de  Wed Mar 14 16:06:30 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 14 Mar 2012 21:06:30 +0100
Subject: [PATCH v3 2/5] ARM: Add a printk loglevel modifier
In-Reply-To: <201203141312.51547.arnd@arndb.de>
References: <20120314101928.GA29474@pengutronix.de>
 <1331720516-11801-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <201203141312.51547.arnd@arndb.de>
Message-ID: <20120314200630.GB2391@pengutronix.de>

On Wed, Mar 14, 2012 at 01:12:51PM +0000, Arnd Bergmann wrote:
> On Wednesday 14 March 2012, Uwe Kleine-K?nig wrote:
> > This is a needed followup for
> > 
> >         ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15
> > 
> > otherwise no newline is printed for !CONFIG_CPU_CP15
> > 
> > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> > ---
> > Should this be folded into the
> > 
> >         ARM: protect usage of cr_alignment by #ifdef CONFIG_CPU_CP15
> > 
> > patch? Or should it come before it?
> > 
> 
> I think this patch needs a better explanation. It looks to me that
> it's simply a bug fix, because every printk that is not a continuation
> of a previous printk needs a KERN_* line. In that case, it should
> just get applied as a bug fix independent of the other patches.
> 
> However, if you sometimes don't have a newline after the previous
> printk, this patch is actually wrong and should not get applied at
> all.
I don't get your reasoning here.

An (independant) printk (that is expected to start at a new line) must
start with KERN_SOMETHING iff the previous printk always ends in \n?
Probably not. 

Independently of the correctness of the first patch that splits the
printk I'm just taking it as an example:

In this case the two printks in question are:

		printk("CPU: %s [%08x] revision %d (ARMv%s)", ...);
	#ifdef CONFIG_CPU_CP15
		printk(KERN_CONT ", cr=%08lx\n", cr_alignment);
	#endif

and

		printk("CPU: %s data cache, %s instruction cache\n", ...)

In this case it's correct to add KERN_INFO to the last printk, isn't it?
When would you consider it to be wrong?

If you want to have the first group of printks to always end in \n, I'd
have to do:

		printk("CPU: %s [%08x] revision %d (ARMv%s)", ...);
	#ifdef CONFIG_CPU_CP15
		printk(KERN_CONT ", cr=%08lx", cr_alignment);
	#endif
		printk(KERN_CONT "\n");

but ISTR Linus (Torvalds) telling me that KERN_CONT "\n" is wrong and
should just be skipped.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From s.hauer at pengutronix.de  Wed Mar 14 16:11:38 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 14 Mar 2012 21:11:38 +0100
Subject: [PATCH v4 03/10] pwm: Add device tree support
In-Reply-To: <1331740593-10807-4-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-4-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120314201138.GU3852@pengutronix.de>

On Wed, Mar 14, 2012 at 04:56:26PM +0100, Thierry Reding wrote:
> This patch adds helpers to support device tree bindings for the generic
> PWM API. Device tree binding documentation for PWM controllers is also
> provided.
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> ---
> Changes in v4:
>   - add OF-specific code removed from patch 2
>   - make of_node_to_pwmchip() and of_pwm_simple_xlate() static
>   - rename of_get_named_pwm() to of_pwm_request(), return a struct
>     pwm_device, get rid of the now unused spec parameter and use the
>     device_node.name field as the PWM's name
>   - return a requested struct pwm_device from pwm_chip.of_xlate and
>     drop the now unused spec parameter
>   - move OF support code into drivers/pwm/core.c
>   - used deferred probing if a PWM chip is not available yet
> 
> Changes in v2:
>   - add device tree binding documentation
>   - add of_xlate to parse controller-specific PWM-specifier
> 
>  Documentation/devicetree/bindings/pwm/pwm.txt |   48 ++++++++++
>  drivers/of/Kconfig                            |    6 ++
>  drivers/pwm/core.c                            |  127 +++++++++++++++++++++++++
>  include/linux/of_pwm.h                        |   36 +++++++
>  include/linux/pwm.h                           |    8 ++
>  5 files changed, 225 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pwm/pwm.txt
>  create mode 100644 include/linux/of_pwm.h
> 
> diff --git a/Documentation/devicetree/bindings/pwm/pwm.txt b/Documentation/devicetree/bindings/pwm/pwm.txt
> new file mode 100644
> index 0000000..9421fe7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/pwm.txt
> @@ -0,0 +1,48 @@
> +Specifying PWM information for devices
> +======================================
> +
> +1) PWM user nodes
> +-----------------
> +
> +PWM users should specify a list of PWM devices that they want to use
> +with a property containing a 'pwm-list':
> +
> +	pwm-list ::= <single-pwm> [pwm-list]
> +	single-pwm ::= <pwm-phandle> <pwm-specifier>
> +	pwm-phandle : phandle to PWM controller node
> +	pwm-specifier : array of #pwm-cells specifying the given PWM
> +			(controller specific)
> +
> +PWM properties should be named "[<name>-]pwms". Exact meaning of each
> +pwms property must be documented in the device tree binding for each
> +device.
> +
> +The following example could be used to describe a PWM-based backlight
> +device:
> +
> +	pwm: pwm {
> +		#pwm-cells = <2>;
> +	};
> +
> +	[...]
> +
> +	bl: backlight {
> +		pwms = <&pwm 0 5000000>;
> +	};
> +
> +pwm-specifier typically encodes the chip-relative PWM number and the PWM
> +period in nanoseconds.
> +
> +2) PWM controller nodes
> +-----------------------
> +
> +PWM controller nodes must specify the number of cells used for the
> +specifier using the '#pwm-cells' property.
> +
> +An example PWM controller might look like this:
> +
> +	pwm: pwm at 7000a000 {
> +		compatible = "nvidia,tegra20-pwm";
> +		reg = <0x7000a000 0x100>;
> +		#pwm-cells = <2>;
> +	};
> diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
> index 6ea51dc..d47b8ee 100644
> --- a/drivers/of/Kconfig
> +++ b/drivers/of/Kconfig
> @@ -57,6 +57,12 @@ config OF_GPIO
>  	help
>  	  OpenFirmware GPIO accessors
>  
> +config OF_PWM
> +	def_bool y
> +	depends on PWM
> +	help
> +	  OpenFirmware PWM accessors
> +
>  config OF_I2C
>  	def_tristate I2C
>  	depends on I2C && !SPARC
> diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
> index 74dd295..c600606 100644
> --- a/drivers/pwm/core.c
> +++ b/drivers/pwm/core.c
> @@ -20,6 +20,7 @@
>   */
>  
>  #include <linux/module.h>
> +#include <linux/of_pwm.h>
>  #include <linux/pwm.h>
>  #include <linux/radix-tree.h>
>  #include <linux/list.h>
> @@ -121,6 +122,75 @@ static int pwm_device_request(struct pwm_device *pwm, const char *label)
>  	return 0;
>  }
>  
> +#ifdef CONFIG_OF_PWM
> +static struct pwm_chip *of_node_to_pwmchip(struct device_node *np)
> +{
> +	struct pwm_chip *chip;
> +
> +	mutex_lock(&pwm_lock);
> +
> +	list_for_each_entry(chip, &pwm_chips, list)
> +		if (chip->dev && chip->dev->of_node == np) {
> +			mutex_unlock(&pwm_lock);
> +			return chip;
> +		}
> +
> +	mutex_unlock(&pwm_lock);
> +
> +	return ERR_PTR(-EPROBE_DEFER);
> +}
> +
> +static struct pwm_device *of_pwm_simple_xlate(struct pwm_chip *pc,
> +					      const struct of_phandle_args *args)
> +{
> +	struct pwm_device *pwm;
> +
> +	if (pc->of_pwm_n_cells < 2)
> +		return ERR_PTR(-EINVAL);
> +
> +	if (args->args_count < pc->of_pwm_n_cells)
> +		return ERR_PTR(-EINVAL);
> +
> +	if (args->args[0] >= pc->npwm)
> +		return ERR_PTR(-EINVAL);
> +
> +	pwm = pwm_request_from_device(pc->dev, args->args[0], NULL);
> +	if (IS_ERR(pwm))
> +		return ERR_PTR(-ENODEV);
> +
> +	pwm_set_period(pwm, args->args[1]);
> +
> +	return pwm;
> +}
> +
> +void of_pwmchip_add(struct pwm_chip *chip)
> +{
> +	if (!chip->dev || !chip->dev->of_node)
> +		return;
> +
> +	if (!chip->of_xlate) {
> +		chip->of_xlate = of_pwm_simple_xlate;
> +		chip->of_pwm_n_cells = 2;
> +	}
> +
> +	of_node_get(chip->dev->of_node);
> +}
> +
> +void of_pwmchip_remove(struct pwm_chip *chip)
> +{
> +	if (chip->dev && chip->dev->of_node)
> +		of_node_put(chip->dev->of_node);
> +}
> +#else
> +static inline void of_pwmchip_add(struct pwm_chip *pc)
> +{
> +}
> +
> +static inline void of_pwmchip_remove(struct pwm_chip *pc)
> +{
> +}
> +#endif /* CONFIG_OF_PWM */
> +
>  /**
>   * pwm_set_chip_data - set private chip data for a PWM
>   * @pwm: PWM device
> @@ -184,6 +254,7 @@ int pwmchip_add(struct pwm_chip *chip)
>  
>  	INIT_LIST_HEAD(&chip->list);
>  	list_add(&chip->list, &pwm_chips);
> +	of_pwmchip_add(chip);
>  
>  out:
>  	mutex_unlock(&pwm_lock);
> @@ -215,6 +286,7 @@ int pwmchip_remove(struct pwm_chip *chip)
>  	}
>  
>  	list_del_init(&chip->list);
> +	of_pwmchip_remove(chip);
>  	free_pwms(chip);
>  
>  out:
> @@ -364,6 +436,61 @@ void pwm_disable(struct pwm_device *pwm)
>  }
>  EXPORT_SYMBOL_GPL(pwm_disable);
>  
> +#ifdef CONFIG_OF
> +/**
> + * of_pwm_request() - request a PWM via the PWM framework
> + * @np: device node to get the PWM from
> + * @propname: property name containing PWM specifier(s)
> + * @index: index of the PWM
> + *
> + * Returns the PWM device parsed from the phandle specified in the given
> + * property of a device tree node or NULL on failure. Values parsed from
> + * the device tree are stored in the returned PWM device object.
> + */
> +struct pwm_device *of_pwm_request(struct device_node *np,
> +				  const char *propname, int index)
> +{
> +	struct pwm_device *pwm = NULL;
> +	struct of_phandle_args args;
> +	struct pwm_chip *pc;
> +	int err;
> +
> +	err = of_parse_phandle_with_args(np, propname, "#pwm-cells", index,
> +					 &args);
> +	if (err) {
> +		pr_debug("%s(): can't parse property \"%s\"\n", __func__,
> +			 propname);
> +		return ERR_PTR(err);
> +	}
> +
> +	pc = of_node_to_pwmchip(args.np);
> +	if (IS_ERR(pc)) {
> +		pr_debug("%s(): PWM chip not found\n", __func__);
> +		pwm = ERR_CAST(pc);
> +		goto put;
> +	}
> +
> +	if (args.args_count != pc->of_pwm_n_cells) {
> +		pr_debug("%s: wrong #pwm-cells for %s\n", np->full_name,
> +			 args.np->full_name);
> +		pwm = ERR_PTR(-EINVAL);
> +		goto put;
> +	}
> +
> +	pwm = pc->of_xlate(pc, &args);
> +	if (IS_ERR(pwm))
> +		goto put;
> +
> +	pwm->label = np->name;
> +
> +put:
> +	of_node_put(args.np);
> +
> +	return pwm;
> +}
> +EXPORT_SYMBOL(of_pwm_request);
> +#endif
> +
>  #ifdef CONFIG_DEBUG_FS
>  static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s)
>  {
> diff --git a/include/linux/of_pwm.h b/include/linux/of_pwm.h
> new file mode 100644
> index 0000000..a3a3da7
> --- /dev/null
> +++ b/include/linux/of_pwm.h
> @@ -0,0 +1,36 @@
> +/*
> + * OF helpers for the PWM API
> + *
> + * Copyright (c) 2011-2012 Avionic Design GmbH
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#ifndef __LINUX_OF_PWM_H
> +#define __LINUX_OF_PWM_H
> +
> +#include <linux/err.h>
> +#include <linux/pwm.h>
> +
> +struct device_node;
> +
> +#ifdef CONFIG_OF_PWM
> +
> +struct pwm_device *of_pwm_request(struct device_node *np,
> +				  const char *propname, int index);
> +
> +#else
> +
> +static inline struct pwm_device *of_pwm_request(struct device_node *np,
> +						const char *propname,
> +						int index);
                                                         ^^^

No semicolon here please.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From davidb at codeaurora.org  Wed Mar 14 16:19:29 2012
From: davidb at codeaurora.org (David Brown)
Date: Wed, 14 Mar 2012 13:19:29 -0700
Subject: [PATCH v3 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 DMA APIs
In-Reply-To: <20120314150533.GA8757@fifo99.com>
References: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>
 <20120312201421.GA3459@fifo99.com>
 <4F5F41AF.1090907@codeaurora.org>
 <20120314150533.GA8757@fifo99.com>
Message-ID: <20120314201929.GA17259@codeaurora.org>

On Wed, Mar 14, 2012 at 08:05:53AM -0700, Daniel Walker wrote:
> On Tue, Mar 13, 2012 at 06:16:39PM +0530, Ravi Kumar V wrote:
> > On 3/13/2012 1:44 AM, Daniel Walker wrote:
> > >On Mon, Mar 12, 2012 at 04:02:44PM +0530, Ravi Kumar V wrote:
> > >>Add DMAEngine based driver using the old MSM DMA APIs internally.
> > >
> > >What do you mean by this?
> > >
> > There is a MSM DMA driver in arch/arm/mach-msm/ which is not in
> > dmaengine framework standards, but that driver is been used by
> > client drivers nand, eMMC and serial drivers. Now if we implement
> > the whole dma driver using dmaengine framework then nand, eMMC like
> > drivers will be failed as they are using old dma driver API's, so
> > instead of implementing new driver from scratch we are keeping the
> > old dma API's as it is and using those API's in new dmaengine
> > framework.So that we can convert clients drivers to use dma engine
> > framework.
> 
> Did you investigate converting the drivers (nand, eMMC, serial) ? It
> seems like there would be a 1:1 mapping between the API's , so it might
> only be a find->replace operation.

Only at a very superficial level--they both do DMA.  The ADM driver
wants its scatterlists constructed manually by the caller (in DMA-able
memory) and just the pointer handed over.  The drivers will have to be
converted to use the abstracted scatterlists that dmaengine wants.
Drivers like msm_sdcc are currently fairly intimitely tied to flow
that is specific to ADM.  The msm_sdcc driver also needs use of the
ADM's "box" mode, which has to be made to work with DMAEngine as well.

Providing both APIs is really the only practical way to get this in
without having to rewrite several other drivers.

The nand driver (which doesn't seem to have made it in yet,
https://lkml.org/lkml/2011/2/28/570) is much worse.  About half of the
code is constructing ADM specific command blocks.  I'm not even sure
it will be practical to even migrate that driver to DMAEngine, since
the nand controller hardware is so intimately tied to the functioning
of the ADM.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From hartleys at visionengravers.com  Wed Mar 14 16:42:37 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 14 Mar 2012 15:42:37 -0500
Subject: [PATCH v4 02/10] pwm: Allow chips to support multiple PWMs.
In-Reply-To: <1331740593-10807-3-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-3-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020695DB57DC@AUSP01VMBX24.collaborationhost.net>

On Wednesday, March 14, 2012 8:56 AM, Thierry Reding wrote:
> 
> Many PWM controllers provide access to more than a single PWM output and
> may even share some resource among them. Allowing a PWM chip to provide
> multiple PWM devices enables better sharing of those resources. As a
> side-effect this change allows easy integration with the device tree
> where a given PWM can be looked up based on the PWM chip's phandle and a
> corresponding index.
>
> This commit modifies the PWM core to support multiple PWMs per struct
> pwm_chip. It achieves this in a similar way to how gpiolib works, by
> allowing PWM ranges to be requested dynamically (pwm_chip.base == -1) or
> starting at a given offset (pwm_chip.base >= 0). A chip specifies how
> many PWMs it controls using the npwm member. Each of the functions in
> the pwm_ops structure gets an additional argument that specified the PWM
> number (it can be converted to a per-chip index by subtracting the
> chip's base).
>
> The total maximum number of PWM devices is currently fixed to 1024 while
> the data is actually stored in a radix tree, thus saving resources if
> not all of them are used.
>
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> ---

<snip>

> diff --git a/include/linux/pwm.h b/include/linux/pwm.h
> index df9681b..7261911 100644
> --- a/include/linux/pwm.h
> +++ b/include/linux/pwm.h

<snip>

>  /**
> - * struct pwm_ops - PWM operations
> + * struct pwm_ops - PWM controller operations
>   * @request: optional hook for requesting a PWM
>   * @free: optional hook for freeing a PWM
>   * @config: configure duty cycles and period length for this PWM
>   * @enable: enable PWM output toggling
>   * @disable: disable PWM output toggling
> + * @dbg_show: optional routine to show contents in debugfs
> + * @owner: helps prevent removal of modules exporting active PWMs
>   */
>  struct pwm_ops {
> -	int			(*request)(struct pwm_chip *chip);
> -	void			(*free)(struct pwm_chip *chip);
> -	int			(*config)(struct pwm_chip *chip, int duty_ns,
> -						int period_ns);
> -	int			(*enable)(struct pwm_chip *chip);
> -	void			(*disable)(struct pwm_chip *chip);
> +	int			(*request)(struct pwm_chip *chip,
> +					   struct pwm_device *pwm);
> +	void			(*free)(struct pwm_chip *chip,
> +					struct pwm_device *pwm);
> +	int			(*config)(struct pwm_chip *chip,
> +					  struct pwm_device *pwm,
> +					  int duty_ns, int period_ns);
> +	int			(*enable)(struct pwm_chip *chip,
> +					  struct pwm_device *pwm);
> +	void			(*disable)(struct pwm_chip *chip,
> +					   struct pwm_device *pwm);
> +#ifdef CONFIG_DEBUG_FS
> +	void			(*dbg_show)(struct pwm_chip *chip,
> +					    struct seq_file *s);
> +#endif

This doesn't compile...

include/linux/pwm.h:87: warning: 'struct seq_file' declared inside parameter list
include/linux/pwm.h:87: warning: its scope is only this definition or declaration, which is probably not what you want

Regards,
Hartley



From thierry.reding at avionic-design.de  Wed Mar 14 16:46:37 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 21:46:37 +0100
Subject: [PATCH v4 03/10] pwm: Add device tree support
In-Reply-To: <20120314201138.GU3852@pengutronix.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-4-git-send-email-thierry.reding@avionic-design.de>
 <20120314201138.GU3852@pengutronix.de>
Message-ID: <20120314204637.GA12334@avionic-0098.mockup.avionic-design.de>

* Sascha Hauer wrote:
> On Wed, Mar 14, 2012 at 04:56:26PM +0100, Thierry Reding wrote:
> > +static inline struct pwm_device *of_pwm_request(struct device_node *np,
> > +						const char *propname,
> > +						int index);
>                                                          ^^^
> 
> No semicolon here please.

Ugh. I've been doing extra compile tests to make sure the series stays
bisectible, but I guess I need to add further tests with !PWM and !OF
configurations.

Thanks,
Thierry
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From mturquette at ti.com  Wed Mar 14 16:47:56 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 14 Mar 2012 13:47:56 -0700
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120314084857.GL3852@pengutronix.de>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120313112447.GA29317@pengutronix.de>
 <CAJOA=zMTY+4dU9VUa-TkEbdE-WJd7V4tCG-af6vgq0CPN6rWpg@mail.gmail.com>
 <20120314084857.GL3852@pengutronix.de>
Message-ID: <CAJOA=zMsCuZgmp1Hm0dq=EVoX6Zj62XQVqR=6GzDntSD5HnHzg@mail.gmail.com>

On Wed, Mar 14, 2012 at 1:48 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Tue, Mar 13, 2012 at 04:43:57PM -0700, Turquette, Mike wrote:
>> On Tue, Mar 13, 2012 at 4:24 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>> > On Sat, Mar 03, 2012 at 12:29:00AM -0800, Mike Turquette wrote:
>> >> The common clock framework defines a common struct clk useful across
>> >> most platforms as well as an implementation of the clk api that drivers
>> >> can use safely for managing clocks.
>> >>
>> >> The net result is consolidation of many different struct clk definitions
>> >> and platform-specific clock framework implementations.
>> >>
>> >> This patch introduces the common struct clk, struct clk_ops and an
>> >> implementation of the well-known clock api in include/clk/clk.h.
>> >> Platforms may define their own hardware-specific clock structure and
>> >> their own clock operation callbacks, so long as it wraps an instance of
>> >> struct clk_hw.
>> >>
>> >> See Documentation/clk.txt for more details.
>> >>
>> >> This patch is based on the work of Jeremy Kerr, which in turn was based
>> >> on the work of Ben Herrenschmidt.
>> >>
>> >> Signed-off-by: Mike Turquette <mturquette at linaro.org>
>> >> Signed-off-by: Mike Turquette <mturquette at ti.com>
>> >> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
>> >> Cc: Thomas Gleixner <tglx at linutronix.de>
>> >> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
>> >> Cc: Paul Walmsley <paul at pwsan.com>
>> >> Cc: Shawn Guo <shawn.guo at freescale.com>
>> >> Cc: Richard Zhao <richard.zhao at linaro.org>
>> >> Cc: Saravana Kannan <skannan at codeaurora.org>
>> >> Cc: Magnus Damm <magnus.damm at gmail.com>
>> >> Cc: Rob Herring <rob.herring at calxeda.com>
>> >> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
>> >> Cc: Linus Walleij <linus.walleij at stericsson.com>
>> >> Cc: Stephen Boyd <sboyd at codeaurora.org>
>> >> Cc: Amit Kucheria <amit.kucheria at linaro.org>
>> >> Cc: Deepak Saxena <dsaxena at linaro.org>
>> >> Cc: Grant Likely <grant.likely at secretlab.ca>
>> >> Cc: Andrew Lunn <andrew at lunn.ch>
>> >> ---
>> >> ?drivers/clk/Kconfig ? ? ? ? ?| ? 28 +
>> >> ?drivers/clk/Makefile ? ? ? ? | ? ?1 +
>> >> ?drivers/clk/clk.c ? ? ? ? ? ?| 1323 ++++++++++++++++++++++++++++++++++++++++++
>> >> ?include/linux/clk-private.h ?| ? 68 +++
>> >> ?include/linux/clk-provider.h | ?169 ++++++
>> >> ?include/linux/clk.h ? ? ? ? ?| ? 68 ++-
>> >> ?6 files changed, 1652 insertions(+), 5 deletions(-)
>> >> ?create mode 100644 drivers/clk/clk.c
>> >> ?create mode 100644 include/linux/clk-private.h
>> >> ?create mode 100644 include/linux/clk-provider.h
>> >>
>> >> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>> >> index 3912576..18eb8c2 100644
>> >> --- a/drivers/clk/Kconfig
>> >> +++ b/drivers/clk/Kconfig
>> >> @@ -11,3 +11,31 @@ config HAVE_MACH_CLKDEV
>> >>
>> >> ?config HAVE_CLK_PREPARE
>> >> ? ? ? bool
>> >> +
>> >> +menuconfig COMMON_CLK
>> >> + ? ? bool "Common Clock Framework"
>> >> + ? ? select HAVE_CLK_PREPARE
>> >> + ? ? ---help---
>> >> + ? ? ? The common clock framework is a single definition of struct
>> >> + ? ? ? clk, useful across many platforms, as well as an
>> >> + ? ? ? implementation of the clock API in include/linux/clk.h.
>> >> + ? ? ? Architectures utilizing the common struct clk should select
>> >> + ? ? ? this automatically, but it may be necessary to manually select
>> >> + ? ? ? this option for loadable modules requiring the common clock
>> >> + ? ? ? framework.
>> >> +
>> >> + ? ? ? If in doubt, say "N".
>> >> +
>> >> +if COMMON_CLK
>> >> +
>> >> +config COMMON_CLK_DEBUG
>> >> + ? ? bool "DebugFS representation of clock tree"
>> >> + ? ? depends on COMMON_CLK
>> >> + ? ? ---help---
>> >> + ? ? ? Creates a directory hierchy in debugfs for visualizing the clk
>> >> + ? ? ? tree structure. ?Each directory contains read-only members
>> >> + ? ? ? that export information specific to that clk node: clk_rate,
>> >> + ? ? ? clk_flags, clk_prepare_count, clk_enable_count &
>> >> + ? ? ? clk_notifier_count.
>> >> +
>> >> +endif
>> >> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> >> index 07613fa..ff362c4 100644
>> >> --- a/drivers/clk/Makefile
>> >> +++ b/drivers/clk/Makefile
>> >> @@ -1,2 +1,3 @@
>> >>
>> >> ?obj-$(CONFIG_CLKDEV_LOOKUP) ?+= clkdev.o
>> >> +obj-$(CONFIG_COMMON_CLK) ? ? += clk.o
>> >> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
>> >> new file mode 100644
>> >> index 0000000..b979d74
>> >> --- /dev/null
>> >> +++ b/drivers/clk/clk.c
>> >> @@ -0,0 +1,1323 @@
>> >> +/*
>> >> + * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
>> >> + * Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or modify
>> >> + * it under the terms of the GNU General Public License version 2 as
>> >> + * published by the Free Software Foundation.
>> >> + *
>> >> + * Standard functionality for the common clock API. ?See Documentation/clk.txt
>> >> + */
>> >> +
>> >> +#include <linux/clk-private.h>
>> >> +#include <linux/module.h>
>> >> +#include <linux/mutex.h>
>> >> +#include <linux/spinlock.h>
>> >> +#include <linux/err.h>
>> >> +#include <linux/list.h>
>> >> +#include <linux/slab.h>
>> >> +
>> >> +static DEFINE_SPINLOCK(enable_lock);
>> >> +static DEFINE_MUTEX(prepare_lock);
>> >> +
>> >> +static HLIST_HEAD(clk_root_list);
>> >> +static HLIST_HEAD(clk_orphan_list);
>> >> +static LIST_HEAD(clk_notifier_list);
>> >> +
>> >> +/*** ? ? ? ?debugfs support ? ? ? ?***/
>> >> +
>> >> +#ifdef CONFIG_COMMON_CLK_DEBUG
>> >> +#include <linux/debugfs.h>
>> >> +
>> >> +static struct dentry *rootdir;
>> >> +static struct dentry *orphandir;
>> >> +static int inited = 0;
>> >> +
>> >> +/* caller must hold prepare_lock */
>> >> +static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
>> >> +{
>> >> + ? ? struct dentry *d;
>> >> + ? ? int ret = -ENOMEM;
>> >> +
>> >> + ? ? if (!clk || !pdentry) {
>> >> + ? ? ? ? ? ? ret = -EINVAL;
>> >> + ? ? ? ? ? ? goto out;
>> >> + ? ? }
>> >> +
>> >> + ? ? d = debugfs_create_dir(clk->name, pdentry);
>> >> + ? ? if (!d)
>> >> + ? ? ? ? ? ? goto out;
>> >> +
>> >> + ? ? clk->dentry = d;
>> >> +
>> >> + ? ? d = debugfs_create_u32("clk_rate", S_IRUGO, clk->dentry,
>> >> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->rate);
>> >> + ? ? if (!d)
>> >> + ? ? ? ? ? ? goto err_out;
>> >> +
>> >> + ? ? d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
>> >> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->flags);
>> >> + ? ? if (!d)
>> >> + ? ? ? ? ? ? goto err_out;
>> >> +
>> >> + ? ? d = debugfs_create_u32("clk_prepare_count", S_IRUGO, clk->dentry,
>> >> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->prepare_count);
>> >> + ? ? if (!d)
>> >> + ? ? ? ? ? ? goto err_out;
>> >> +
>> >> + ? ? d = debugfs_create_u32("clk_enable_count", S_IRUGO, clk->dentry,
>> >> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->enable_count);
>> >> + ? ? if (!d)
>> >> + ? ? ? ? ? ? goto err_out;
>> >> +
>> >> + ? ? d = debugfs_create_u32("clk_notifier_count", S_IRUGO, clk->dentry,
>> >> + ? ? ? ? ? ? ? ? ? ? (u32 *)&clk->notifier_count);
>> >> + ? ? if (!d)
>> >> + ? ? ? ? ? ? goto err_out;
>> >> +
>> >> + ? ? ret = 0;
>> >> + ? ? goto out;
>> >> +
>> >> +err_out:
>> >> + ? ? debugfs_remove(clk->dentry);
>> >> +out:
>> >> + ? ? return ret;
>> >> +}
>> >> +
>> >> +/* caller must hold prepare_lock */
>> >> +static int clk_debug_create_subtree(struct clk *clk, struct dentry *pdentry)
>> >> +{
>> >> + ? ? struct clk *child;
>> >> + ? ? struct hlist_node *tmp;
>> >> + ? ? int ret = -EINVAL;;
>> >> +
>> >> + ? ? if (!clk || !pdentry)
>> >> + ? ? ? ? ? ? goto out;
>> >> +
>> >> + ? ? ret = clk_debug_create_one(clk, pdentry);
>> >> +
>> >> + ? ? if (ret)
>> >> + ? ? ? ? ? ? goto out;
>> >> +
>> >> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node)
>> >> + ? ? ? ? ? ? clk_debug_create_subtree(child, clk->dentry);
>> >> +
>> >> + ? ? ret = 0;
>> >> +out:
>> >> + ? ? return ret;
>> >> +}
>> >> +
>> >> +/**
>> >> + * clk_debug_register - add a clk node to the debugfs clk tree
>> >> + * @clk: the clk being added to the debugfs clk tree
>> >> + *
>> >> + * Dynamically adds a clk to the debugfs clk tree if debugfs has been
>> >> + * initialized. ?Otherwise it bails out early since the debugfs clk tree
>> >> + * will be created lazily by clk_debug_init as part of a late_initcall.
>> >> + *
>> >> + * Caller must hold prepare_lock. ?Only clk_init calls this function (so
>> >> + * far) so this is taken care.
>> >> + */
>> >> +static int clk_debug_register(struct clk *clk)
>> >> +{
>> >> + ? ? struct clk *parent;
>> >> + ? ? struct dentry *pdentry;
>> >> + ? ? int ret = 0;
>> >> +
>> >> + ? ? if (!inited)
>> >> + ? ? ? ? ? ? goto out;
>> >> +
>> >> + ? ? parent = clk->parent;
>> >> +
>> >> + ? ? /*
>> >> + ? ? ?* Check to see if a clk is a root clk. ?Also check that it is
>> >> + ? ? ?* safe to add this clk to debugfs
>> >> + ? ? ?*/
>> >> + ? ? if (!parent)
>> >> + ? ? ? ? ? ? if (clk->flags & CLK_IS_ROOT)
>> >> + ? ? ? ? ? ? ? ? ? ? pdentry = rootdir;
>> >> + ? ? ? ? ? ? else
>> >> + ? ? ? ? ? ? ? ? ? ? pdentry = orphandir;
>> >> + ? ? else
>> >> + ? ? ? ? ? ? if (parent->dentry)
>> >> + ? ? ? ? ? ? ? ? ? ? pdentry = parent->dentry;
>> >> + ? ? ? ? ? ? else
>> >> + ? ? ? ? ? ? ? ? ? ? goto out;
>> >> +
>> >> + ? ? ret = clk_debug_create_subtree(clk, pdentry);
>> >> +
>> >> +out:
>> >> + ? ? return ret;
>> >> +}
>> >> +
>> >> +/**
>> >> + * clk_debug_init - lazily create the debugfs clk tree visualization
>> >> + *
>> >> + * clks are often initialized very early during boot before memory can
>> >> + * be dynamically allocated and well before debugfs is setup.
>> >> + * clk_debug_init walks the clk tree hierarchy while holding
>> >> + * prepare_lock and creates the topology as part of a late_initcall,
>> >> + * thus insuring that clks initialized very early will still be
>> >> + * represented in the debugfs clk tree. ?This function should only be
>> >> + * called once at boot-time, and all other clks added dynamically will
>> >> + * be done so with clk_debug_register.
>> >> + */
>> >> +static int __init clk_debug_init(void)
>> >> +{
>> >> + ? ? struct clk *clk;
>> >> + ? ? struct hlist_node *tmp;
>> >> +
>> >> + ? ? rootdir = debugfs_create_dir("clk", NULL);
>> >> +
>> >> + ? ? if (!rootdir)
>> >> + ? ? ? ? ? ? return -ENOMEM;
>> >> +
>> >> + ? ? orphandir = debugfs_create_dir("orphans", rootdir);
>> >> +
>> >> + ? ? if (!orphandir)
>> >> + ? ? ? ? ? ? return -ENOMEM;
>> >> +
>> >> + ? ? mutex_lock(&prepare_lock);
>> >> +
>> >> + ? ? hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
>> >> + ? ? ? ? ? ? clk_debug_create_subtree(clk, rootdir);
>> >> +
>> >> + ? ? hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
>> >> + ? ? ? ? ? ? clk_debug_create_subtree(clk, orphandir);
>> >> +
>> >> + ? ? inited = 1;
>> >> +
>> >> + ? ? mutex_unlock(&prepare_lock);
>> >> +
>> >> + ? ? return 0;
>> >> +}
>> >> +late_initcall(clk_debug_init);
>> >> +#else
>> >> +static inline int clk_debug_register(struct clk *clk) { return 0; }
>> >> +#endif /* CONFIG_COMMON_CLK_DEBUG */
>> >> +
>> >> +/*** ? ?helper functions ? ***/
>> >> +
>> >> +inline const char *__clk_get_name(struct clk *clk)
>> >> +{
>> >> + ? ? return !clk ? NULL : clk->name;
>> >> +}
>> >> +
>> >> +inline struct clk_hw *__clk_get_hw(struct clk *clk)
>> >> +{
>> >> + ? ? return !clk ? NULL : clk->hw;
>> >> +}
>> >> +
>> >> +inline u8 __clk_get_num_parents(struct clk *clk)
>> >> +{
>> >> + ? ? return !clk ? -EINVAL : clk->num_parents;
>> >> +}
>> >> +
>> >> +inline struct clk *__clk_get_parent(struct clk *clk)
>> >> +{
>> >> + ? ? return !clk ? NULL : clk->parent;
>> >> +}
>> >> +
>> >> +inline unsigned long __clk_get_rate(struct clk *clk)
>> >> +{
>> >> + ? ? return !clk ? -EINVAL : clk->rate;
>> >> +}
>> >> +
>> >> +inline unsigned long __clk_get_flags(struct clk *clk)
>> >> +{
>> >> + ? ? return !clk ? -EINVAL : clk->flags;
>> >> +}
>> >> +
>> >> +static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
>> >> +{
>> >> + ? ? struct clk *child;
>> >> + ? ? struct clk *ret;
>> >> + ? ? struct hlist_node *tmp;
>> >> +
>> >> + ? ? if (!strcmp(clk->name, name))
>> >> + ? ? ? ? ? ? return clk;
>> >> +
>> >> + ? ? hlist_for_each_entry(child, tmp, &clk->children, child_node) {
>> >> + ? ? ? ? ? ? ret = __clk_lookup_subtree(name, child);
>> >> + ? ? ? ? ? ? if (ret)
>> >> + ? ? ? ? ? ? ? ? ? ? return ret;
>> >> + ? ? }
>> >> +
>> >> + ? ? return NULL;
>> >> +}
>> >> +
>> >> +struct clk *__clk_lookup(const char *name)
>> >> +{
>> >> + ? ? struct clk *root_clk;
>> >> + ? ? struct clk *ret;
>> >> + ? ? struct hlist_node *tmp;
>> >> +
>> >
>> > This should have a check for NULL pointers. NULL pointers can happen
>> > here if a mux has holes in it. In this case the parent name array would
>> > look like this:
>> >
>> > { "parentclk1", "parentclk2", NULL /* reserved */, "parentclk3" }
>> >
>> > Without checking for NULL pointers we dereference the NULL pointer here.
>>
>> I will add the check. ?I had not considered having NULL as one of the
>> parent names. ?It seems to me that the only time this would happen is
>> if we are wiring up discrete devices. ?For instance:
>>
>> Device A has a fixed-rate clock named "dpll"
>> Device B has a mux clock named "leaf" with parent_names = { "32k",
>> "oscillator", "clkin" }
>>
>> On a given board, leaf's "pll" parent might map to the output of the
>> dpll clock. ?I had considered that DT would step in here by creating
>> an intermediate clock with no functional clk_ops that would "connect"
>> these two clocks. ?The benefit of this is that it is easier to match
>> up clock names when staring at some data sheets. ?It is common for a
>> downstream device's data sheets to assign names to the external inputs
>> originating from some unknown device; unsurprisingly the data sheet
>> for the device supplying the external upstream clocks often has
>> different names for the output signals than the one in the downstream
>> device's data sheet. ?Using the method described above it is easy for
>> a person with both data sheets to see how the devices are wired up
>> since all of the clock names are represented by nodes in the clock
>> tree. ?In short, the final outcome would looking something like:
>>
>> dpll (device a's driver registered this clock)
>> ? |
>> clkin (one of device b's possible parents)
>> ? | ? ?(it is a dummy clock from DT since it is board-level topology)
>> ? |
>> leaf (device b's driver registered this clock)
>>
>> clkin would have a single parent named "dpll" in this case, and again,
>> it would have no meaningful clk_ops.
>>
>> A caveat to the above scenario is that parent_names shouldn't have
>> holes in it, but a null pointer check is reasonable anyways.
>>
>> What do you think? ?Even if we allow for muxes to have holes in
>> parent_names we'll still have to solve these sort of device
>> integration issues and DT will likely play a roll here. ?I'll roll in
>> the null pointer check regardless.
>>
>> Also, do you forsee needing hole in parent_names for any reason other
>> than described above?
>
> I need it only for the case where a some values in the mux are marked as
> reserved in the datasheet or we simply do not have the corresponding
> clock in our tree (yet). We could also say that NULL pointers are not
> allowed in parent arrays, but instead "orphan" or "dummy" should be
> used. Then __clk_init should check for NULL pointers to make this clear.

I've added a WARN in __clk_init if any entries in .parent_names are
NULL.  I think it best to populate it with "dummy", or maybe a
platform-specific name if it helps you during development.

Regards,
Mike

>
> Sascha
>
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |


From thierry.reding at avionic-design.de  Wed Mar 14 16:49:35 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 21:49:35 +0100
Subject: [PATCH v4 02/10] pwm: Allow chips to support multiple PWMs.
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F0020695DB57DC@AUSP01VMBX24.collaborationhost.net>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-3-git-send-email-thierry.reding@avionic-design.de>
 <ADE657CA350FB648AAC2C43247A983F0020695DB57DC@AUSP01VMBX24.collaborationhost.net>
Message-ID: <20120314204935.GB12334@avionic-0098.mockup.avionic-design.de>

* H Hartley Sweeten wrote:
> On Wednesday, March 14, 2012 8:56 AM, Thierry Reding wrote:
[...]
> > +#ifdef CONFIG_DEBUG_FS
> > +	void			(*dbg_show)(struct pwm_chip *chip,
> > +					    struct seq_file *s);
> > +#endif
> 
> This doesn't compile...
> 
> include/linux/pwm.h:87: warning: 'struct seq_file' declared inside parameter list
> include/linux/pwm.h:87: warning: its scope is only this definition or declaration, which is probably not what you want

Okay, pwm.h probably needs a seq_file.h include. Thanks for noticing.

Thierry
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From khilman at ti.com  Wed Mar 14 16:50:36 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 14 Mar 2012 13:50:36 -0700
Subject: [PATCH 00/12] mfd: twl: Fix for irqdomain/next + SPARSE_IRQ + MMC
 card detect
In-Reply-To: <1330707024-23730-1-git-send-email-b-cousson@ti.com> (Benoit
 Cousson's message of "Fri, 2 Mar 2012 17:50:12 +0100")
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
Message-ID: <87399ahppf.fsf@ti.com>

Hi Benoit,

Benoit Cousson <b-cousson at ti.com> writes:

[...]

> This is not for pull-request, becasue it is based on irqdomain + OMAP
> IRQ DT series + OMAP twl DT series yet to be pushed.

What's the status of this series?

At least 'gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ
support' is needed in mainline (linux-next) now since without it, non-DT
boots will dump a big fat warning trace[2].  

Also FYI, I needed the patch below[1] in order to build this series.

Kevin

[1]
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index b8c74c7..8db1d64 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -15,6 +15,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
+#include <linux/i2c/twl.h>
 
 #include <mach/hardware.h>
 #include <asm/hardware/gic.h>


[2]
[    0.495117] twl4030: PIH (irq 7) chaining IRQs 368..401
[    0.501190] twl4030: power (irq 373) chaining IRQs 402..409
[    0.509429] twl4030: gpio (irq 368) chaining IRQs 410..427
[    0.515319] ------------[ cut here ]------------
[    0.520202] WARNING: at /work/kernel/omap/pm/drivers/gpio/gpio-twl4030.c:410 gpio_twl4030_probe+0x44/0x214()
[    0.530395] Modules linked in:
[    0.533691] [<c0014248>] (unwind_backtrace+0x0/0xf0) from [<c0039054>] (warn_slowpath_common+0x4c/0x64)
[    0.543640] [<c0039054>] (warn_slowpath_common+0x4c/0x64) from [<c0039088>] (warn_slowpath_null+0x1c/0x24)
[    0.553680] [<c0039088>] (warn_slowpath_null+0x1c/0x24) from [<c04196f4>] (gpio_twl4030_probe+0x44/0x214)
[    0.563629] [<c04196f4>] (gpio_twl4030_probe+0x44/0x214) from [<c028832c>] (platform_drv_probe+0x18/0x1c)
[    0.573577] [<c028832c>] (platform_drv_probe+0x18/0x1c) from [<c0286fd4>] (really_probe+0x60/0x15c)
[    0.583007] [<c0286fd4>] (really_probe+0x60/0x15c) from [<c0287214>] (driver_probe_device+0x48/0x60)
[    0.592498] [<c0287214>] (driver_probe_device+0x48/0x60) from [<c0285af8>] (bus_for_each_drv+0x5c/0x88)
[    0.602264] [<c0285af8>] (bus_for_each_drv+0x5c/0x88) from [<c028718c>] (device_attach+0x98/0xbc)
[    0.611480] [<c028718c>] (device_attach+0x98/0xbc) from [<c0286844>] (bus_probe_device+0x88/0xac)
[    0.620727] [<c0286844>] (bus_probe_device+0x88/0xac) from [<c0285160>] (device_add+0x278/0x358)
[    0.629882] [<c0285160>] (device_add+0x278/0x358) from [<c02887a8>] (platform_device_add+0xf8/0x1a4)
[    0.639373] [<c02887a8>] (platform_device_add+0xf8/0x1a4) from [<c042e4a0>] (add_numbered_child.constprop.0+0xb8/0xfc)
[    0.650451] [<c042e4a0>] (add_numbered_child.constprop.0+0xb8/0xfc) from [<c042e5a4>] (add_children+0x44/0x6d0)
[    0.660949] [<c042e5a4>] (add_children+0x44/0x6d0) from [<c041a8b8>] (twl_probe+0x354/0x3bc)
[    0.669738] [<c041a8b8>] (twl_probe+0x354/0x3bc) from [<c0326cb0>] (i2c_device_probe+0xc0/0x100)
[    0.678863] [<c0326cb0>] (i2c_device_probe+0xc0/0x100) from [<c0286fd4>] (really_probe+0x60/0x15c)
[    0.688171] [<c0286fd4>] (really_probe+0x60/0x15c) from [<c0287214>] (driver_probe_device+0x48/0x60)
[    0.697692] [<c0287214>] (driver_probe_device+0x48/0x60) from [<c0285af8>] (bus_for_each_drv+0x5c/0x88)
[    0.707458] [<c0285af8>] (bus_for_each_drv+0x5c/0x88) from [<c028718c>] (device_attach+0x98/0xbc)
[    0.716674] [<c028718c>] (device_attach+0x98/0xbc) from [<c0286844>] (bus_probe_device+0x88/0xac)
[    0.725921] [<c0286844>] (bus_probe_device+0x88/0xac) from [<c0285160>] (device_add+0x278/0x358)
[    0.735076] [<c0285160>] (device_add+0x278/0x358) from [<c0327410>] (i2c_new_device+0xec/0x160)
[    0.744354] [<c0327410>] (i2c_new_device+0xec/0x160) from [<c032781c>] (i2c_register_adapter+0x168/0x220)
[    0.754302] [<c032781c>] (i2c_register_adapter+0x168/0x220) from [<c0327a40>] (i2c_add_numbered_adapter+0xd4/0xf0)
[    0.765045] [<c0327a40>] (i2c_add_numbered_adapter+0xd4/0xf0) from [<c041f4c8>] (omap_i2c_probe+0x334/0x424)
[    0.775268] [<c041f4c8>] (omap_i2c_probe+0x334/0x424) from [<c028832c>] (platform_drv_probe+0x18/0x1c)
[    0.784942] [<c028832c>] (platform_drv_probe+0x18/0x1c) from [<c0286fd4>] (really_probe+0x60/0x15c)
[    0.794342] [<c0286fd4>] (really_probe+0x60/0x15c) from [<c0287214>] (driver_probe_device+0x48/0x60)
[    0.803863] [<c0287214>] (driver_probe_device+0x48/0x60) from [<c02872c0>] (__driver_attach+0x94/0x98)
[    0.813537] [<c02872c0>] (__driver_attach+0x94/0x98) from [<c0285b74>] (bus_for_each_dev+0x50/0x7c)
[    0.822937] [<c0285b74>] (bus_for_each_dev+0x50/0x7c) from [<c0286ad4>] (bus_add_driver+0x184/0x248)
[    0.832427] [<c0286ad4>] (bus_add_driver+0x184/0x248) from [<c0287798>] (driver_register+0x78/0x12c)
[    0.841949] [<c0287798>] (driver_register+0x78/0x12c) from [<c0008800>] (do_one_initcall+0x34/0x178)
[    0.851440] [<c0008800>] (do_one_initcall+0x34/0x178) from [<c06068ac>] (kernel_init+0x8c/0x130)
[    0.860565] [<c06068ac>] (kernel_init+0x8c/0x130) from [<c000e850>] (kernel_thread_exit+0x0/0x8)
[    0.870117] ---[ end trace 1b75b31a2719ed1c ]---


From lars at metafoo.de  Wed Mar 14 16:52:39 2012
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Wed, 14 Mar 2012 21:52:39 +0100
Subject: [PATCH v4 01/10] PWM: add pwm framework support
In-Reply-To: <1331740593-10807-2-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-2-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F610517.7090006@metafoo.de>

On 03/14/2012 04:56 PM, Thierry Reding wrote:
> [...]
> +struct pwm_chip {
> +	int			pwm_id;
> +	const char		*label;
> +	struct pwm_ops		*ops;

Nothing major, but if you are going for another round it would be good to see
ops made const.

> +};



From thierry.reding at avionic-design.de  Wed Mar 14 16:57:34 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 14 Mar 2012 21:57:34 +0100
Subject: [PATCH v4 01/10] PWM: add pwm framework support
In-Reply-To: <4F610517.7090006@metafoo.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-2-git-send-email-thierry.reding@avionic-design.de>
 <4F610517.7090006@metafoo.de>
Message-ID: <20120314205734.GA16020@avionic-0098.mockup.avionic-design.de>

* Lars-Peter Clausen wrote:
> On 03/14/2012 04:56 PM, Thierry Reding wrote:
> > [...]
> > +struct pwm_chip {
> > +	int			pwm_id;
> > +	const char		*label;
> > +	struct pwm_ops		*ops;
> 
> Nothing major, but if you are going for another round it would be good to see
> ops made const.

I'll go for another round because I just noticed that I still have two open
TODO items that I forgot to fix from last round's review.

I'll take a note to make it const.

Thierry
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From khilman at ti.com  Wed Mar 14 16:59:51 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 14 Mar 2012 13:59:51 -0700
Subject: [PATCH 01/12] mfd: twl-core: don't depend on pdata->irq_base/end
In-Reply-To: <1330707024-23730-2-git-send-email-b-cousson@ti.com> (Benoit
 Cousson's message of "Fri, 2 Mar 2012 17:50:13 +0100")
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-2-git-send-email-b-cousson@ti.com>
Message-ID: <87pqcegapk.fsf@ti.com>

Benoit Cousson <b-cousson at ti.com> writes:

> From: Felipe Balbi <balbi at ti.com>
>
> With sparse IRQs the driver shouldn't depend at all on
> any IRQ values coming from board-file.
>
> Remove every occurences of pdata->irq_base/end.

Well, not quite *every*. :)

If the driver isn't going to use those fields anymore, they should also
be removed from the pdata struct too[1].  Also, the remaining board/init
code that is initializing those fields should be removed as well[2], since
it obviously has no effect.

The first patch below should probably be folded into this one, and then
the 2nd patch removes all the users.

Kevin

[1]
>From 70a1833ca20142ef5b6b96dbc92a63c7f8ef9a04 Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman at ti.com>
Date: Wed, 14 Mar 2012 13:55:31 -0700
Subject: [PATCH 1/2] mfd: twl-core: remove pdata->irq_base/end

Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 include/linux/i2c/twl.h |    1 -
 1 file changed, 1 deletion(-)

diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 2463b61..fa76006 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -697,7 +697,6 @@ struct twl4030_audio_data {
 };
 
 struct twl4030_platform_data {
-	unsigned				irq_base, irq_end;
 	struct twl4030_clock_init_data		*clock;
 	struct twl4030_bci_platform_data	*bci;
 	struct twl4030_gpio_platform_data	*gpio;
-- 
1.7.9.2


[2]
>From d2b7b518b4c66beb99fccfcb898001c11a2f6dc9 Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman at ti.com>
Date: Wed, 14 Mar 2012 13:56:01 -0700
Subject: [PATCH 2/2] ARM: OMAP2+: TWL: remove usage of pdata->irq_base/_end

The driver has been converted to use SPARSE_IRQ and no longer needs to
be passed IRQ base/end.  The driver no longer uses these fields, so
remove them from the reamaining users.

Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/board-2430sdp.c    |    3 ---
 arch/arm/mach-omap2/board-omap3logic.c |    3 ---
 arch/arm/mach-omap2/twl-common.c       |    9 ---------
 3 files changed, 15 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index c8bda62..b8b3700 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -218,9 +218,6 @@ static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
 };
 
 static struct twl4030_platform_data sdp2430_twldata = {
-	.irq_base	= TWL4030_IRQ_BASE,
-	.irq_end	= TWL4030_IRQ_END,
-
 	/* platform_data for children goes here */
 	.gpio		= &sdp2430_gpio_data,
 	.vmmc1		= &sdp2430_vmmc1,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 4a7d8c8..f145935 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -85,9 +85,6 @@ static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
 };
 
 static struct twl4030_platform_data omap3logic_twldata = {
-	.irq_base	= TWL4030_IRQ_BASE,
-	.irq_end	= TWL4030_IRQ_END,
-
 	/* platform_data for children goes here */
 	.gpio		= &omap3logic_gpio_data,
 	.vmmc1		= &omap3logic_vmmc1,
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 1cddcb2..5c9aa3f 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -184,10 +184,6 @@ static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
 void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 				  u32 pdata_flags, u32 regulators_flags)
 {
-	if (!pmic_data->irq_base)
-		pmic_data->irq_base = TWL4030_IRQ_BASE;
-	if (!pmic_data->irq_end)
-		pmic_data->irq_end = TWL4030_IRQ_END;
 	if (!pmic_data->vdd1) {
 		omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
 		omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
@@ -415,11 +411,6 @@ static struct twl_regulator_driver_data omap4_vdd3_drvdata = {
 void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
 				  u32 pdata_flags, u32 regulators_flags)
 {
-	if (!pmic_data->irq_base)
-		pmic_data->irq_base = TWL6030_IRQ_BASE;
-	if (!pmic_data->irq_end)
-		pmic_data->irq_end = TWL6030_IRQ_END;
-
 	if (!pmic_data->vdd1) {
 		omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
 		omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
-- 
1.7.9.2



From b-cousson at ti.com  Wed Mar 14 17:01:31 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Wed, 14 Mar 2012 22:01:31 +0100
Subject: [PATCH 00/12] mfd: twl: Fix for irqdomain/next + SPARSE_IRQ +
 MMC card detect
In-Reply-To: <87399ahppf.fsf@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <87399ahppf.fsf@ti.com>
Message-ID: <4F61072B.9030606@ti.com>

Hi Kevin,

On 3/14/2012 9:50 PM, Kevin Hilman wrote:
> Hi Benoit,
>
> Benoit Cousson<b-cousson at ti.com>  writes:
>
> [...]
>
>> This is not for pull-request, becasue it is based on irqdomain + OMAP
>> IRQ DT series + OMAP twl DT series yet to be pushed.
>
> What's the status of this series?

I sent earlier today the pull request to Samuel.

Here is the branch for information: for_3.4/twl_irq_gpio_mmc_fix

> At least 'gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ
> support' is needed in mainline (linux-next) now since without it, non-DT
> boots will dump a big fat warning trace[2].

Yeah, I know :-(

> Also FYI, I needed the patch below[1] in order to build this series.

That's weird, this include was added by the following commit 
a7cbb9b15d55dff0488b1a6d93929c2386d8632b at 3.2 time frame.

What branch are you using?

Regards,
Benoit

>
> Kevin
>
> [1]
> diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
> index b8c74c7..8db1d64 100644
> --- a/arch/arm/mach-omap2/board-generic.c
> +++ b/arch/arm/mach-omap2/board-generic.c
> @@ -15,6 +15,7 @@
>   #include<linux/of_irq.h>
>   #include<linux/of_platform.h>
>   #include<linux/irqdomain.h>
> +#include<linux/i2c/twl.h>
>
>   #include<mach/hardware.h>
>   #include<asm/hardware/gic.h>
>
>
> [2]
> [    0.495117] twl4030: PIH (irq 7) chaining IRQs 368..401
> [    0.501190] twl4030: power (irq 373) chaining IRQs 402..409
> [    0.509429] twl4030: gpio (irq 368) chaining IRQs 410..427
> [    0.515319] ------------[ cut here ]------------
> [    0.520202] WARNING: at /work/kernel/omap/pm/drivers/gpio/gpio-twl4030.c:410 gpio_twl4030_probe+0x44/0x214()
> [    0.530395] Modules linked in:
> [    0.533691] [<c0014248>] (unwind_backtrace+0x0/0xf0) from [<c0039054>] (warn_slowpath_common+0x4c/0x64)
> [    0.543640] [<c0039054>] (warn_slowpath_common+0x4c/0x64) from [<c0039088>] (warn_slowpath_null+0x1c/0x24)
> [    0.553680] [<c0039088>] (warn_slowpath_null+0x1c/0x24) from [<c04196f4>] (gpio_twl4030_probe+0x44/0x214)
> [    0.563629] [<c04196f4>] (gpio_twl4030_probe+0x44/0x214) from [<c028832c>] (platform_drv_probe+0x18/0x1c)
> [    0.573577] [<c028832c>] (platform_drv_probe+0x18/0x1c) from [<c0286fd4>] (really_probe+0x60/0x15c)
> [    0.583007] [<c0286fd4>] (really_probe+0x60/0x15c) from [<c0287214>] (driver_probe_device+0x48/0x60)
> [    0.592498] [<c0287214>] (driver_probe_device+0x48/0x60) from [<c0285af8>] (bus_for_each_drv+0x5c/0x88)
> [    0.602264] [<c0285af8>] (bus_for_each_drv+0x5c/0x88) from [<c028718c>] (device_attach+0x98/0xbc)
> [    0.611480] [<c028718c>] (device_attach+0x98/0xbc) from [<c0286844>] (bus_probe_device+0x88/0xac)
> [    0.620727] [<c0286844>] (bus_probe_device+0x88/0xac) from [<c0285160>] (device_add+0x278/0x358)
> [    0.629882] [<c0285160>] (device_add+0x278/0x358) from [<c02887a8>] (platform_device_add+0xf8/0x1a4)
> [    0.639373] [<c02887a8>] (platform_device_add+0xf8/0x1a4) from [<c042e4a0>] (add_numbered_child.constprop.0+0xb8/0xfc)
> [    0.650451] [<c042e4a0>] (add_numbered_child.constprop.0+0xb8/0xfc) from [<c042e5a4>] (add_children+0x44/0x6d0)
> [    0.660949] [<c042e5a4>] (add_children+0x44/0x6d0) from [<c041a8b8>] (twl_probe+0x354/0x3bc)
> [    0.669738] [<c041a8b8>] (twl_probe+0x354/0x3bc) from [<c0326cb0>] (i2c_device_probe+0xc0/0x100)
> [    0.678863] [<c0326cb0>] (i2c_device_probe+0xc0/0x100) from [<c0286fd4>] (really_probe+0x60/0x15c)
> [    0.688171] [<c0286fd4>] (really_probe+0x60/0x15c) from [<c0287214>] (driver_probe_device+0x48/0x60)
> [    0.697692] [<c0287214>] (driver_probe_device+0x48/0x60) from [<c0285af8>] (bus_for_each_drv+0x5c/0x88)
> [    0.707458] [<c0285af8>] (bus_for_each_drv+0x5c/0x88) from [<c028718c>] (device_attach+0x98/0xbc)
> [    0.716674] [<c028718c>] (device_attach+0x98/0xbc) from [<c0286844>] (bus_probe_device+0x88/0xac)
> [    0.725921] [<c0286844>] (bus_probe_device+0x88/0xac) from [<c0285160>] (device_add+0x278/0x358)
> [    0.735076] [<c0285160>] (device_add+0x278/0x358) from [<c0327410>] (i2c_new_device+0xec/0x160)
> [    0.744354] [<c0327410>] (i2c_new_device+0xec/0x160) from [<c032781c>] (i2c_register_adapter+0x168/0x220)
> [    0.754302] [<c032781c>] (i2c_register_adapter+0x168/0x220) from [<c0327a40>] (i2c_add_numbered_adapter+0xd4/0xf0)
> [    0.765045] [<c0327a40>] (i2c_add_numbered_adapter+0xd4/0xf0) from [<c041f4c8>] (omap_i2c_probe+0x334/0x424)
> [    0.775268] [<c041f4c8>] (omap_i2c_probe+0x334/0x424) from [<c028832c>] (platform_drv_probe+0x18/0x1c)
> [    0.784942] [<c028832c>] (platform_drv_probe+0x18/0x1c) from [<c0286fd4>] (really_probe+0x60/0x15c)
> [    0.794342] [<c0286fd4>] (really_probe+0x60/0x15c) from [<c0287214>] (driver_probe_device+0x48/0x60)
> [    0.803863] [<c0287214>] (driver_probe_device+0x48/0x60) from [<c02872c0>] (__driver_attach+0x94/0x98)
> [    0.813537] [<c02872c0>] (__driver_attach+0x94/0x98) from [<c0285b74>] (bus_for_each_dev+0x50/0x7c)
> [    0.822937] [<c0285b74>] (bus_for_each_dev+0x50/0x7c) from [<c0286ad4>] (bus_add_driver+0x184/0x248)
> [    0.832427] [<c0286ad4>] (bus_add_driver+0x184/0x248) from [<c0287798>] (driver_register+0x78/0x12c)
> [    0.841949] [<c0287798>] (driver_register+0x78/0x12c) from [<c0008800>] (do_one_initcall+0x34/0x178)
> [    0.851440] [<c0008800>] (do_one_initcall+0x34/0x178) from [<c06068ac>] (kernel_init+0x8c/0x130)
> [    0.860565] [<c06068ac>] (kernel_init+0x8c/0x130) from [<c000e850>] (kernel_thread_exit+0x0/0x8)
> [    0.870117] ---[ end trace 1b75b31a2719ed1c ]---



From b-cousson at ti.com  Wed Mar 14 17:08:17 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Wed, 14 Mar 2012 22:08:17 +0100
Subject: [PATCH 01/12] mfd: twl-core: don't depend on pdata->irq_base/end
In-Reply-To: <87pqcegapk.fsf@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-2-git-send-email-b-cousson@ti.com> <87pqcegapk.fsf@ti.com>
Message-ID: <4F6108C1.2060004@ti.com>

On 3/14/2012 9:59 PM, Kevin Hilman wrote:
> Benoit Cousson<b-cousson at ti.com>  writes:
>
>> From: Felipe Balbi<balbi at ti.com>
>>
>> With sparse IRQs the driver shouldn't depend at all on
>> any IRQ values coming from board-file.
>>
>> Remove every occurences of pdata->irq_base/end.
>
> Well, not quite *every*. :)

Hehe, good catch, thanks.

> If the driver isn't going to use those fields anymore, they should also
> be removed from the pdata struct too[1].  Also, the remaining board/init
> code that is initializing those fields should be removed as well[2], since
> it obviously has no effect.
>
> The first patch below should probably be folded into this one, and then
> the 2nd patch removes all the users.

We should probably remove all the users before removing the attribute? 
It looks like your patches are ordered in the opposite way.

I'll add that in the series and repost the pull request.

Regards,
Benoit

>
> Kevin
>
> [1]
>  From 70a1833ca20142ef5b6b96dbc92a63c7f8ef9a04 Mon Sep 17 00:00:00 2001
> From: Kevin Hilman<khilman at ti.com>
> Date: Wed, 14 Mar 2012 13:55:31 -0700
> Subject: [PATCH 1/2] mfd: twl-core: remove pdata->irq_base/end
>
> Signed-off-by: Kevin Hilman<khilman at ti.com>
> ---
>   include/linux/i2c/twl.h |    1 -
>   1 file changed, 1 deletion(-)
>
> diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
> index 2463b61..fa76006 100644
> --- a/include/linux/i2c/twl.h
> +++ b/include/linux/i2c/twl.h
> @@ -697,7 +697,6 @@ struct twl4030_audio_data {
>   };
>
>   struct twl4030_platform_data {
> -	unsigned				irq_base, irq_end;
>   	struct twl4030_clock_init_data		*clock;
>   	struct twl4030_bci_platform_data	*bci;
>   	struct twl4030_gpio_platform_data	*gpio;



From khilman at ti.com  Wed Mar 14 17:15:56 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 14 Mar 2012 14:15:56 -0700
Subject: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting to
 add IVA OPP
In-Reply-To: <1331746695-24372-1-git-send-email-mvs@tigris.de> (Maximilian
 Schwerin's message of "Wed, 14 Mar 2012 18:38:15 +0100")
References: <1331746695-24372-1-git-send-email-mvs@tigris.de>
Message-ID: <874ntqg9yr.fsf@ti.com>

Maximilian Schwerin <mvs at tigris.de> writes:

> From: Steve Sakoman <steve at sakoman.com>
>
> Don't try to add IVA OPPs for OMAP3 versions not containing an IVA
> subsystem, as this would make omap_init_opp_table fail.
>
> Signed-off-by: Steve Sakoman <steve at sakoman.com>
> Signed-off-by: Maximilian Schwerin <mvs at tigris.de>

Minor: patch subjects for arch/arm/* core code need to have the ARM:
prefix also.

Also, please run scripts/checkpatch.pl on your patch and fix the
warnings.

> ---
>  arch/arm/mach-omap2/opp.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
> index 9262a6b..414f2ec 100644
> --- a/arch/arm/mach-omap2/opp.c
> +++ b/arch/arm/mach-omap2/opp.c
> @@ -62,6 +62,10 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
>  				__func__, i);
>  			return -EINVAL;
>  		}
> +
> +		if ((strcmp(opp_def->hwmod_name,"iva") == 0) && !omap3_has_iva())
> +			continue;
> +
>  		oh = omap_hwmod_lookup(opp_def->hwmod_name);
>  		if (!oh || !oh->od) {
>  			pr_warn("%s: no hwmod or odev for %s, [%d] "

Wouldn't the one-liner below do the same thing?

Actually, your patch makes it less noisy at boot time, avoiding the
pr_warn(), so is probably better.

Kevin

diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index 9262a6b..d3d4fa2 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -67,7 +67,7 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
 			pr_warn("%s: no hwmod or odev for %s, [%d] "
 				"cannot add OPPs.\n", __func__,
 				opp_def->hwmod_name, i);
-			return -EINVAL;
+			continue;
 		}
 		dev = &oh->od->pdev->dev;


From khilman at ti.com  Wed Mar 14 17:17:54 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 14 Mar 2012 14:17:54 -0700
Subject: [PATCH 01/12] mfd: twl-core: don't depend on pdata->irq_base/end
In-Reply-To: <4F6108C1.2060004@ti.com> (Benoit Cousson's message of "Wed, 14
 Mar 2012 22:08:17 +0100")
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-2-git-send-email-b-cousson@ti.com>
 <87pqcegapk.fsf@ti.com> <4F6108C1.2060004@ti.com>
Message-ID: <87y5r2evb1.fsf@ti.com>

"Cousson, Benoit" <b-cousson at ti.com> writes:

> On 3/14/2012 9:59 PM, Kevin Hilman wrote:
>> Benoit Cousson<b-cousson at ti.com>  writes:
>>
>>> From: Felipe Balbi<balbi at ti.com>
>>>
>>> With sparse IRQs the driver shouldn't depend at all on
>>> any IRQ values coming from board-file.
>>>
>>> Remove every occurences of pdata->irq_base/end.
>>
>> Well, not quite *every*. :)
>
> Hehe, good catch, thanks.
>
>> If the driver isn't going to use those fields anymore, they should also
>> be removed from the pdata struct too[1].  Also, the remaining board/init
>> code that is initializing those fields should be removed as well[2], since
>> it obviously has no effect.
>>
>> The first patch below should probably be folded into this one, and then
>> the 2nd patch removes all the users.
>
> We should probably remove all the users before removing the attribute?
> It looks like your patches are ordered in the opposite way.

Agreed.

> I'll add that in the series and repost the pull request.

Great, thanks.

Kevin


From nico at fluxnic.net  Wed Mar 14 17:19:53 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 14 Mar 2012 17:19:53 -0400 (EDT)
Subject: [PATCH v3 1/5] ARM: protect usage of cr_alignment by #ifdef
 CONFIG_CPU_CP15
In-Reply-To: <20120314195120.GA2391@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
 <1331720483-10075-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <alpine.LFD.2.02.1203141103080.24151@xanadu.home>
 <20120314195120.GA2391@pengutronix.de>
Message-ID: <alpine.LFD.2.02.1203141710210.24151@xanadu.home>

On Wed, 14 Mar 2012, Uwe Kleine-K?nig wrote:

> On Wed, Mar 14, 2012 at 11:24:36AM -0400, Nicolas Pitre wrote:
> > Again, you could just leave the original display, with cr=00000000 which 
> > is a fairly good representation of reality.
> Maybe having
> 
> 	#define cr_alignment 0
> 
> for the !CONFIG_CPU_CP15 case would be a nice alternative. This way all
> places that want to modify cr_alignment fail to compile, but reading
> gives a "fairly good representation of reality".

Even better, yes.

> Having said that I'm not sure about "fairly good". v7m also supports
> unaligned accesses. But it's not configured in a cp15 register
> (obviously) but in a system register.

Hence having a "control register" displaying as zero is still fairly 
good.

> Quoting ARMARM-v7m:
> 
> 	Configuration and Control Register, CCR
> 	[...]
> 	Bit [3] UNALIGN_TRP	Controls the trapping of unaligned word or
> 				halfword accesses:
> 				0 = Trapping disabled.
> 				1 = Trapping enabled.
> 				Unaligned load-store multiples and word
> 				or halfword exclusive accesses always
> 				fault.
> 
> So we need a more general abstraction to have correct and clean code?

In the context of the alignment trap code, yes.  Maybe on v7m there is 
no point having the alignment trap disabled at all.  It's been almost 
forever that gcc is not relying on the side effect of misaligned 
accesses anymore.

> > >  	flush_cache_all();
> > > +#ifdef CONFIG_CPU_CP15
> > >  	set_cr(cr_alignment);
> > > +#endif
> > 
> > However it might be best to provide a dummy set_cr() instead of 
> > #ifdef'ing it out everywhere.
> What should the dummy set_cr do? Print a runtime warning if called with
> != 0?

Maybe not.  In fact if that code path is used, then something might be 
wrong at a higher level.


Nicolas

From khilman at ti.com  Wed Mar 14 17:24:50 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 14 Mar 2012 14:24:50 -0700
Subject: [PATCH 00/12] mfd: twl: Fix for irqdomain/next + SPARSE_IRQ + MMC
 card detect
In-Reply-To: <4F61072B.9030606@ti.com> (Benoit Cousson's message of "Wed, 14
 Mar 2012 22:01:31 +0100")
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <87399ahppf.fsf@ti.com> <4F61072B.9030606@ti.com>
Message-ID: <87ty1qeuzh.fsf@ti.com>

"Cousson, Benoit" <b-cousson at ti.com> writes:

> Hi Kevin,
>
> On 3/14/2012 9:50 PM, Kevin Hilman wrote:
>> Hi Benoit,
>>
>> Benoit Cousson<b-cousson at ti.com>  writes:
>>
>> [...]
>>
>>> This is not for pull-request, becasue it is based on irqdomain + OMAP
>>> IRQ DT series + OMAP twl DT series yet to be pushed.
>>
>> What's the status of this series?
>
> I sent earlier today the pull request to Samuel.
>
> Here is the branch for information: for_3.4/twl_irq_gpio_mmc_fix
>
>> At least 'gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ
>> support' is needed in mainline (linux-next) now since without it, non-DT
>> boots will dump a big fat warning trace[2].
>
> Yeah, I know :-(
>
>> Also FYI, I needed the patch below[1] in order to build this series.
>
> That's weird, this include was added by the following commit
> a7cbb9b15d55dff0488b1a6d93929c2386d8632b at 3.2 time frame.

OK.

> What branch are you using?

I was using your for_3.4/twl_irq_gpio_cleanup, but had some merge
conflicts.  Maybe I mis-merged something and dropped that include.

Kevin


From tglx at linutronix.de  Wed Mar 14 17:28:15 2012
From: tglx at linutronix.de (Thomas Gleixner)
Date: Wed, 14 Mar 2012 22:28:15 +0100 (CET)
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zMsCuZgmp1Hm0dq=EVoX6Zj62XQVqR=6GzDntSD5HnHzg@mail.gmail.com>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120313112447.GA29317@pengutronix.de>
 <CAJOA=zMTY+4dU9VUa-TkEbdE-WJd7V4tCG-af6vgq0CPN6rWpg@mail.gmail.com>
 <20120314084857.GL3852@pengutronix.de>
 <CAJOA=zMsCuZgmp1Hm0dq=EVoX6Zj62XQVqR=6GzDntSD5HnHzg@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1203142218320.2466@ionos>

On Wed, 14 Mar 2012, Turquette, Mike wrote:

Could you folks please trim your replies? It's annoying to page down a
gazillion of lines to find the gist.

> On Wed, Mar 14, 2012 at 1:48 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> >> Also, do you forsee needing hole in parent_names for any reason other
> >> than described above?
> >
> > I need it only for the case where a some values in the mux are marked as
> > reserved in the datasheet or we simply do not have the corresponding
> > clock in our tree (yet). We could also say that NULL pointers are not
> > allowed in parent arrays, but instead "orphan" or "dummy" should be
> > used. Then __clk_init should check for NULL pointers to make this clear.
> 
> I've added a WARN in __clk_init if any entries in .parent_names are
> NULL.  I think it best to populate it with "dummy", or maybe a
> platform-specific name if it helps you during development.

There is no guarantee that the selection of a parent can be mapped
linear to register values.

So the right way to deal with it is to have an array of valid names
with no holes and NULL pointers allowed and have a mapping from the
array index to the register value.

That makes the core code robust and allows to handle all corner cases
including reserved bits, not implemented clocks and weird register
layouts.

Thanks,

	tglx


From nm at ti.com  Wed Mar 14 17:35:17 2012
From: nm at ti.com (Menon, Nishanth)
Date: Wed, 14 Mar 2012 16:35:17 -0500
Subject: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting to
 add IVA OPP
In-Reply-To: <874ntqg9yr.fsf@ti.com>
References: <1331746695-24372-1-git-send-email-mvs@tigris.de>
 <874ntqg9yr.fsf@ti.com>
Message-ID: <CAOMWX4eYQvwHfpci1AgLO8kk1yxzB-zruMQQvLXeLnxbfUHFgw@mail.gmail.com>

On Wed, Mar 14, 2012 at 16:15, Kevin Hilman <khilman at ti.com> wrote:
> Maximilian Schwerin <mvs at tigris.de> writes:
>
>> From: Steve Sakoman <steve at sakoman.com>
>>
>> Don't try to add IVA OPPs for OMAP3 versions not containing an IVA
>> subsystem, as this would make omap_init_opp_table fail.
>>
>> Signed-off-by: Steve Sakoman <steve at sakoman.com>
>> Signed-off-by: Maximilian Schwerin <mvs at tigris.de>
>
> Minor: patch subjects for arch/arm/* core code need to have the ARM:
> prefix also.
>
> Also, please run scripts/checkpatch.pl on your patch and fix the
> warnings.
>
>> ---
>> ?arch/arm/mach-omap2/opp.c | ? ?4 ++++
>> ?1 files changed, 4 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
>> index 9262a6b..414f2ec 100644
>> --- a/arch/arm/mach-omap2/opp.c
>> +++ b/arch/arm/mach-omap2/opp.c
>> @@ -62,6 +62,10 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __func__, i);
>> ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;
>> ? ? ? ? ? ? ? }
>> +
>> + ? ? ? ? ? ? if ((strcmp(opp_def->hwmod_name,"iva") == 0) && !omap3_has_iva())
>> + ? ? ? ? ? ? ? ? ? ? continue;
>> +
>> ? ? ? ? ? ? ? oh = omap_hwmod_lookup(opp_def->hwmod_name);
>> ? ? ? ? ? ? ? if (!oh || !oh->od) {
>> ? ? ? ? ? ? ? ? ? ? ? pr_warn("%s: no hwmod or odev for %s, [%d] "
>
> Wouldn't the one-liner below do the same thing?
>
> Actually, your patch makes it less noisy at boot time, avoiding the
> pr_warn(), so is probably better.

The only issue i have with current patch is that it focusses to solve
a specific device IVA.
we could have similar variances if we had SGX/AESS device etc
registered in the common
table. a generic solution might be preferable - could we reduce the
severity of pr_warn to pr_debug and do a continue instead?

>
> Kevin
>
> diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
> index 9262a6b..d3d4fa2 100644
> --- a/arch/arm/mach-omap2/opp.c
> +++ b/arch/arm/mach-omap2/opp.c
> @@ -67,7 +67,7 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
> ? ? ? ? ? ? ? ? ? ? ? ?pr_warn("%s: no hwmod or odev for %s, [%d] "
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"cannot add OPPs.\n", __func__,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?opp_def->hwmod_name, i);
> - ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? ? ? ? ? ? ? ? ? continue;
> ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ?dev = &oh->od->pdev->dev;


Regards,
Nishanth Menon


From marc at cpdesign.com.au  Wed Mar 14 16:43:04 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Thu, 15 Mar 2012 07:43:04 +1100
Subject: mc13xxx: add I2C support (now with regmap), V3
Message-ID: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>

Hi,

This series (against mfd-2.6/for-next) changes the mc13xxx driver to use 
regmap and adds I2C support. It generally goes about this the same way as 
the previous 2 versions, but now uses regmap.

I am unable to test SPI functionality, but the I2C stuff works. It would be
great if someone could test the SPI side again.

The first 2 patches add required support to regmap for the mc13xxx register
format(s), I've included them here for convenience.
@Mark B: I also have some versions of these that apply against regmap/for-next.

Cheers,
Marc




From marc at cpdesign.com.au  Wed Mar 14 16:43:05 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Thu, 15 Mar 2012 07:43:05 +1100
Subject: [PATCH v3 1/6] regmap: add support for 7_25 format
In-Reply-To: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
References: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1331757790-10583-2-git-send-email-marc@cpdesign.com.au>

This adds support for devices with 7 address bits and 25 data bits.
The initial intended user for this are the mc13xxx mfds in spi mode.
(The 25th data bit is actually a dummy bit)

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/base/regmap/regmap.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index be10a4f..62ef0df 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -100,6 +100,14 @@ static void regmap_format_10_14_write(struct regmap *map,
 	out[0] = reg >> 2;
 }
 
+static void regmap_format_7_25_write(struct regmap *map,
+				    unsigned int reg, unsigned int val)
+{
+	__be32 *out = map->work_buf;
+
+	*out = (reg << 25) | val;
+}
+
 static void regmap_format_8(void *buf, unsigned int val)
 {
 	u8 *b = buf;
@@ -193,6 +201,9 @@ struct regmap *regmap_init(struct device *dev,
 		case 9:
 			map->format.format_write = regmap_format_7_9_write;
 			break;
+		case 25:
+			map->format.format_write = regmap_format_7_25_write;
+			break;
 		default:
 			goto err_map;
 		}
-- 
1.7.3.4



From marc at cpdesign.com.au  Wed Mar 14 16:43:06 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Thu, 15 Mar 2012 07:43:06 +1100
Subject: [PATCH v3 2/6] regmap: Add support for device with 24 data bits.
In-Reply-To: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
References: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1331757790-10583-3-git-send-email-marc@cpdesign.com.au>

Add support for devices with 24 data bits.

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/base/regmap/regmap.c |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index 62ef0df..880e3a0 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -122,6 +122,15 @@ static void regmap_format_16(void *buf, unsigned int val)
 	b[0] = cpu_to_be16(val);
 }
 
+static void regmap_format_24(void *buf, unsigned int val)
+{
+	u8 *b = buf;
+
+	b[0] = val >> 16;
+	b[1] = val >> 8;
+	b[2] = val;
+}
+
 static unsigned int regmap_parse_8(void *buf)
 {
 	u8 *b = buf;
@@ -138,6 +147,16 @@ static unsigned int regmap_parse_16(void *buf)
 	return b[0];
 }
 
+static unsigned int regmap_parse_24(void *buf)
+{
+	u8 *b = buf;
+	unsigned int ret = b[2];
+	ret |= ((unsigned int)b[1]) << 8;
+	ret |= ((unsigned int)b[0]) << 16;
+
+	return ret;
+}
+
 /**
  * regmap_init(): Initialise register map
  *
@@ -240,6 +259,10 @@ struct regmap *regmap_init(struct device *dev,
 		map->format.format_val = regmap_format_16;
 		map->format.parse_val = regmap_parse_16;
 		break;
+	case 24:
+		map->format.format_val = regmap_format_24;
+		map->format.parse_val = regmap_parse_24;
+		break;
 	}
 
 	if (!map->format.format_write &&
-- 
1.7.3.4



From marc at cpdesign.com.au  Wed Mar 14 16:43:07 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Thu, 15 Mar 2012 07:43:07 +1100
Subject: [PATCH v3 3/6] mfd: mc13xxx-core: Prepare for separate spi and i2c
 backends.
In-Reply-To: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
References: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1331757790-10583-4-git-send-email-marc@cpdesign.com.au>

This patch abstracts the bus specific operations from the driver core.
Generic init and cleanup is consolidated into mc13xxx_common_*.
spi specific functions are renamed to reflect such.
(The irq member of the mc13xxx struct is no longer redundant, it's used
to store the irq for cleanup time).

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/mfd/mc13xxx-core.c |  187 ++++++++++++++++++++++++++------------------
 1 files changed, 112 insertions(+), 75 deletions(-)

diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index 7122386..0753402 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -22,8 +22,18 @@
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
 
+enum mc13xxx_id {
+	MC13XXX_ID_MC13783,
+	MC13XXX_ID_MC13892,
+	MC13XXX_ID_INVALID,
+};
+
 struct mc13xxx {
 	struct spi_device *spidev;
+
+	struct device *dev;
+	enum mc13xxx_id ictype;
+
 	struct mutex lock;
 	int irq;
 	int flags;
@@ -144,36 +154,32 @@ struct mc13xxx {
 void mc13xxx_lock(struct mc13xxx *mc13xxx)
 {
 	if (!mutex_trylock(&mc13xxx->lock)) {
-		dev_dbg(&mc13xxx->spidev->dev, "wait for %s from %pf\n",
+		dev_dbg(mc13xxx->dev, "wait for %s from %pf\n",
 				__func__, __builtin_return_address(0));
 
 		mutex_lock(&mc13xxx->lock);
 	}
-	dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
+	dev_dbg(mc13xxx->dev, "%s from %pf\n",
 			__func__, __builtin_return_address(0));
 }
 EXPORT_SYMBOL(mc13xxx_lock);
 
 void mc13xxx_unlock(struct mc13xxx *mc13xxx)
 {
-	dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
+	dev_dbg(mc13xxx->dev, "%s from %pf\n",
 			__func__, __builtin_return_address(0));
 	mutex_unlock(&mc13xxx->lock);
 }
 EXPORT_SYMBOL(mc13xxx_unlock);
 
 #define MC13XXX_REGOFFSET_SHIFT 25
-int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
+static int mc13xxx_spi_reg_read(struct mc13xxx *mc13xxx,
+				unsigned int offset, u32 *val)
 {
 	struct spi_transfer t;
 	struct spi_message m;
 	int ret;
 
-	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
-
-	if (offset > MC13XXX_NUMREGS)
-		return -EINVAL;
-
 	*val = offset << MC13XXX_REGOFFSET_SHIFT;
 
 	memset(&t, 0, sizeof(t));
@@ -195,26 +201,17 @@ int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 
 	*val &= 0xffffff;
 
-	dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
-
 	return 0;
 }
-EXPORT_SYMBOL(mc13xxx_reg_read);
 
-int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
+static int mc13xxx_spi_reg_write(struct mc13xxx *mc13xxx, unsigned int offset,
+		u32 val)
 {
 	u32 buf;
 	struct spi_transfer t;
 	struct spi_message m;
 	int ret;
 
-	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
-
-	dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
-
-	if (offset > MC13XXX_NUMREGS || val > 0xffffff)
-		return -EINVAL;
-
 	buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
 
 	memset(&t, 0, sizeof(t));
@@ -235,6 +232,34 @@ int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
 
 	return 0;
 }
+
+int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
+{
+	int ret;
+
+	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
+
+	if (offset > MC13XXX_NUMREGS)
+		return -EINVAL;
+
+	ret = mc13xxx_spi_reg_read(mc13xxx, offset, val);
+	dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
+
+	return ret;
+}
+EXPORT_SYMBOL(mc13xxx_reg_read);
+
+int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
+{
+	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
+
+	dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
+
+	if (offset > MC13XXX_NUMREGS || val > 0xffffff)
+		return -EINVAL;
+
+	return mc13xxx_spi_reg_write(mc13xxx, offset, val);
+}
 EXPORT_SYMBOL(mc13xxx_reg_write);
 
 int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
@@ -439,7 +464,7 @@ static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
 			if (handled == IRQ_HANDLED)
 				num_handled++;
 		} else {
-			dev_err(&mc13xxx->spidev->dev,
+			dev_err(mc13xxx->dev,
 					"BUG: irq %u but no handler\n",
 					baseirq + irq);
 
@@ -475,25 +500,23 @@ static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
 	return IRQ_RETVAL(handled);
 }
 
-enum mc13xxx_id {
-	MC13XXX_ID_MC13783,
-	MC13XXX_ID_MC13892,
-	MC13XXX_ID_INVALID,
-};
-
 static const char *mc13xxx_chipname[] = {
 	[MC13XXX_ID_MC13783] = "mc13783",
 	[MC13XXX_ID_MC13892] = "mc13892",
 };
 
 #define maskval(reg, mask)	(((reg) & (mask)) >> __ffs(mask))
-static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
+static int mc13xxx_identify(struct mc13xxx *mc13xxx)
 {
 	u32 icid;
 	u32 revision;
-	const char *name;
 	int ret;
 
+	/*
+	 * Get the generation ID from register 46, as apparently some older
+	 * IC revisions only have this info at this location. Newer ICs seem to
+	 * have both.
+	 */
 	ret = mc13xxx_reg_read(mc13xxx, 46, &icid);
 	if (ret)
 		return ret;
@@ -502,26 +525,23 @@ static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
 
 	switch (icid) {
 	case 2:
-		*id = MC13XXX_ID_MC13783;
-		name = "mc13783";
+		mc13xxx->ictype = MC13XXX_ID_MC13783;
 		break;
 	case 7:
-		*id = MC13XXX_ID_MC13892;
-		name = "mc13892";
+		mc13xxx->ictype = MC13XXX_ID_MC13892;
 		break;
 	default:
-		*id = MC13XXX_ID_INVALID;
+		mc13xxx->ictype = MC13XXX_ID_INVALID;
 		break;
 	}
 
-	if (*id == MC13XXX_ID_MC13783 || *id == MC13XXX_ID_MC13892) {
+	if (mc13xxx->ictype == MC13XXX_ID_MC13783 ||
+			mc13xxx->ictype == MC13XXX_ID_MC13892) {
 		ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
-		if (ret)
-			return ret;
 
-		dev_info(&mc13xxx->spidev->dev, "%s: rev: %d.%d, "
+		dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
 				"fin: %d, fab: %d, icid: %d/%d\n",
-				mc13xxx_chipname[*id],
+				mc13xxx_chipname[mc13xxx->ictype],
 				maskval(revision, MC13XXX_REVISION_REVFULL),
 				maskval(revision, MC13XXX_REVISION_REVMETAL),
 				maskval(revision, MC13XXX_REVISION_FIN),
@@ -530,26 +550,12 @@ static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
 				maskval(revision, MC13XXX_REVISION_ICIDCODE));
 	}
 
-	if (*id != MC13XXX_ID_INVALID) {
-		const struct spi_device_id *devid =
-			spi_get_device_id(mc13xxx->spidev);
-		if (!devid || devid->driver_data != *id)
-			dev_warn(&mc13xxx->spidev->dev, "device id doesn't "
-					"match auto detection!\n");
-	}
-
-	return 0;
+	return (mc13xxx->ictype == MC13XXX_ID_INVALID) ? -ENODEV : 0;
 }
 
 static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
 {
-	const struct spi_device_id *devid =
-		spi_get_device_id(mc13xxx->spidev);
-
-	if (!devid)
-		return NULL;
-
-	return mc13xxx_chipname[devid->driver_data];
+	return mc13xxx_chipname[mc13xxx->ictype];
 }
 
 int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
@@ -589,7 +595,7 @@ int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
 	};
 	init_completion(&adcdone_data.done);
 
-	dev_dbg(&mc13xxx->spidev->dev, "%s\n", __func__);
+	dev_dbg(mc13xxx->dev, "%s\n", __func__);
 
 	mc13xxx_lock(mc13xxx);
 
@@ -631,7 +637,7 @@ int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
 		return -EINVAL;
 	}
 
-	dev_dbg(&mc13xxx->spidev->dev, "%s: request irq\n", __func__);
+	dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
 	mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
 			mc13xxx_handler_adcdone, __func__, &adcdone_data);
 	mc13xxx_irq_ack(mc13xxx, MC13XXX_IRQ_ADCDONE);
@@ -689,7 +695,7 @@ static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
 	if (!cell.name)
 		return -ENOMEM;
 
-	return mfd_add_devices(&mc13xxx->spidev->dev, -1, &cell, 1, NULL, 0);
+	return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0);
 }
 
 static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
@@ -700,7 +706,7 @@ static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
 #ifdef CONFIG_OF
 static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 {
-	struct device_node *np = mc13xxx->spidev->dev.of_node;
+	struct device_node *np = mc13xxx->dev.of_node;
 
 	if (!np)
 		return -ENODEV;
@@ -746,13 +752,17 @@ static const struct of_device_id mc13xxx_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
 
-static int mc13xxx_probe(struct spi_device *spi)
+static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+		struct mc13xxx_platform_data *pdata, int irq);
+
+static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx);
+
+static int mc13xxx_spi_probe(struct spi_device *spi)
 {
 	const struct of_device_id *of_id;
 	struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
 	struct mc13xxx *mc13xxx;
 	struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
-	enum mc13xxx_id id;
 	int ret;
 
 	of_id = of_match_device(mc13xxx_dt_ids, &spi->dev);
@@ -768,13 +778,34 @@ static int mc13xxx_probe(struct spi_device *spi)
 	spi->bits_per_word = 32;
 	spi_setup(spi);
 
+	mc13xxx->dev = &spi->dev;
 	mc13xxx->spidev = spi;
 
+	ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
+
+	if (ret) {
+		dev_set_drvdata(&spi->dev, NULL);
+	} else {
+		const struct spi_device_id *devid =
+			spi_get_device_id(mc13xxx->spidev);
+		if (!devid || devid->driver_data != mc13xxx->ictype)
+			dev_warn(mc13xxx->dev,
+				"device id doesn't match auto detection!\n");
+	}
+
+	return ret;
+}
+
+static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+		struct mc13xxx_platform_data *pdata, int irq)
+{
+	int ret;
+
 	mutex_init(&mc13xxx->lock);
 	mc13xxx_lock(mc13xxx);
 
-	ret = mc13xxx_identify(mc13xxx, &id);
-	if (ret || id == MC13XXX_ID_INVALID)
+	ret = mc13xxx_identify(mc13xxx);
+	if (ret)
 		goto err_revision;
 
 	/* mask all irqs */
@@ -786,18 +817,19 @@ static int mc13xxx_probe(struct spi_device *spi)
 	if (ret)
 		goto err_mask;
 
-	ret = request_threaded_irq(spi->irq, NULL, mc13xxx_irq_thread,
+	ret = request_threaded_irq(irq, NULL, mc13xxx_irq_thread,
 			IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
 
 	if (ret) {
 err_mask:
 err_revision:
 		mc13xxx_unlock(mc13xxx);
-		dev_set_drvdata(&spi->dev, NULL);
 		kfree(mc13xxx);
 		return ret;
 	}
 
+	mc13xxx->irq = irq;
+
 	mc13xxx_unlock(mc13xxx);
 
 	if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
@@ -831,39 +863,44 @@ err_revision:
 	return 0;
 }
 
-static int __devexit mc13xxx_remove(struct spi_device *spi)
+static int __devexit mc13xxx_spi_remove(struct spi_device *spi)
 {
 	struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
 
-	free_irq(mc13xxx->spidev->irq, mc13xxx);
+	mc13xxx_common_cleanup(mc13xxx);
 
-	mfd_remove_devices(&spi->dev);
+	return 0;
+}
 
-	kfree(mc13xxx);
+static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
+{
+	free_irq(mc13xxx->irq, mc13xxx);
 
-	return 0;
+	mfd_remove_devices(mc13xxx->dev);
+
+	kfree(mc13xxx);
 }
 
-static struct spi_driver mc13xxx_driver = {
+static struct spi_driver mc13xxx_spi_driver = {
 	.id_table = mc13xxx_device_id,
 	.driver = {
 		.name = "mc13xxx",
 		.owner = THIS_MODULE,
 		.of_match_table = mc13xxx_dt_ids,
 	},
-	.probe = mc13xxx_probe,
-	.remove = __devexit_p(mc13xxx_remove),
+	.probe = mc13xxx_spi_probe,
+	.remove = __devexit_p(mc13xxx_spi_remove),
 };
 
 static int __init mc13xxx_init(void)
 {
-	return spi_register_driver(&mc13xxx_driver);
+	return spi_register_driver(&mc13xxx_spi_driver);
 }
 subsys_initcall(mc13xxx_init);
 
 static void __exit mc13xxx_exit(void)
 {
-	spi_unregister_driver(&mc13xxx_driver);
+	spi_unregister_driver(&mc13xxx_spi_driver);
 }
 module_exit(mc13xxx_exit);
 
-- 
1.7.3.4



From marc at cpdesign.com.au  Wed Mar 14 16:43:08 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Thu, 15 Mar 2012 07:43:08 +1100
Subject: [PATCH v3 4/6] mfd: mc13xxx-core: use regmap for register access
In-Reply-To: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
References: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1331757790-10583-5-git-send-email-marc@cpdesign.com.au>

This change converts the mc13xxx core to use regmap rather than direct
spi r/w.
The spidev member of mc13xxx struct becomes redundant and is removed.
Extra debugging aids are added to mc13xxx_reg_rmw.
Mutex init is moved to before regmap init.

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/mfd/mc13xxx-core.c |  109 ++++++++++++-------------------------------
 1 files changed, 31 insertions(+), 78 deletions(-)

diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index 0753402..9804572 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -21,6 +21,8 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
+#include <linux/regmap.h>
+#include <linux/err.h>
 
 enum mc13xxx_id {
 	MC13XXX_ID_MC13783,
@@ -29,7 +31,7 @@ enum mc13xxx_id {
 };
 
 struct mc13xxx {
-	struct spi_device *spidev;
+	struct regmap *regmap;
 
 	struct device *dev;
 	enum mc13xxx_id ictype;
@@ -172,67 +174,6 @@ void mc13xxx_unlock(struct mc13xxx *mc13xxx)
 }
 EXPORT_SYMBOL(mc13xxx_unlock);
 
-#define MC13XXX_REGOFFSET_SHIFT 25
-static int mc13xxx_spi_reg_read(struct mc13xxx *mc13xxx,
-				unsigned int offset, u32 *val)
-{
-	struct spi_transfer t;
-	struct spi_message m;
-	int ret;
-
-	*val = offset << MC13XXX_REGOFFSET_SHIFT;
-
-	memset(&t, 0, sizeof(t));
-
-	t.tx_buf = val;
-	t.rx_buf = val;
-	t.len = sizeof(u32);
-
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	ret = spi_sync(mc13xxx->spidev, &m);
-
-	/* error in message.status implies error return from spi_sync */
-	BUG_ON(!ret && m.status);
-
-	if (ret)
-		return ret;
-
-	*val &= 0xffffff;
-
-	return 0;
-}
-
-static int mc13xxx_spi_reg_write(struct mc13xxx *mc13xxx, unsigned int offset,
-		u32 val)
-{
-	u32 buf;
-	struct spi_transfer t;
-	struct spi_message m;
-	int ret;
-
-	buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
-
-	memset(&t, 0, sizeof(t));
-
-	t.tx_buf = &buf;
-	t.rx_buf = &buf;
-	t.len = sizeof(u32);
-
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	ret = spi_sync(mc13xxx->spidev, &m);
-
-	BUG_ON(!ret && m.status);
-
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
 int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 {
 	int ret;
@@ -242,7 +183,7 @@ int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 	if (offset > MC13XXX_NUMREGS)
 		return -EINVAL;
 
-	ret = mc13xxx_spi_reg_read(mc13xxx, offset, val);
+	ret = regmap_read(mc13xxx->regmap, offset, val);
 	dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
 
 	return ret;
@@ -258,25 +199,19 @@ int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
 	if (offset > MC13XXX_NUMREGS || val > 0xffffff)
 		return -EINVAL;
 
-	return mc13xxx_spi_reg_write(mc13xxx, offset, val);
+	return regmap_write(mc13xxx->regmap, offset, val);
 }
 EXPORT_SYMBOL(mc13xxx_reg_write);
 
 int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
 		u32 mask, u32 val)
 {
-	int ret;
-	u32 valread;
-
+	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 	BUG_ON(val & ~mask);
+	dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
+			offset, val, mask);
 
-	ret = mc13xxx_reg_read(mc13xxx, offset, &valread);
-	if (ret)
-		return ret;
-
-	valread = (valread & ~mask) | val;
-
-	return mc13xxx_reg_write(mc13xxx, offset, valread);
+	return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
 }
 EXPORT_SYMBOL(mc13xxx_reg_rmw);
 
@@ -752,6 +687,15 @@ static const struct of_device_id mc13xxx_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
 
+static struct regmap_config mc13xxx_regmap_spi_config = {
+	.reg_bits = 7,
+	.val_bits = 25,
+
+	.max_register = MC13XXX_NUMREGS,
+
+	.cache_type = REGCACHE_NONE,
+};
+
 static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
 		struct mc13xxx_platform_data *pdata, int irq);
 
@@ -776,10 +720,18 @@ static int mc13xxx_spi_probe(struct spi_device *spi)
 	dev_set_drvdata(&spi->dev, mc13xxx);
 	spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
 	spi->bits_per_word = 32;
-	spi_setup(spi);
 
 	mc13xxx->dev = &spi->dev;
-	mc13xxx->spidev = spi;
+	mutex_init(&mc13xxx->lock);
+
+	mc13xxx->regmap = regmap_init_spi(spi, &mc13xxx_regmap_spi_config);
+	if (IS_ERR(mc13xxx->regmap)) {
+		ret = PTR_ERR(mc13xxx->regmap);
+		dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
+				ret);
+		dev_set_drvdata(&spi->dev, NULL);
+		return ret;
+	}
 
 	ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
 
@@ -787,7 +739,7 @@ static int mc13xxx_spi_probe(struct spi_device *spi)
 		dev_set_drvdata(&spi->dev, NULL);
 	} else {
 		const struct spi_device_id *devid =
-			spi_get_device_id(mc13xxx->spidev);
+			spi_get_device_id(spi);
 		if (!devid || devid->driver_data != mc13xxx->ictype)
 			dev_warn(mc13xxx->dev,
 				"device id doesn't match auto detection!\n");
@@ -801,7 +753,6 @@ static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
 {
 	int ret;
 
-	mutex_init(&mc13xxx->lock);
 	mc13xxx_lock(mc13xxx);
 
 	ret = mc13xxx_identify(mc13xxx);
@@ -878,6 +829,8 @@ static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
 
 	mfd_remove_devices(mc13xxx->dev);
 
+	regmap_exit(mc13xxx->regmap);
+
 	kfree(mc13xxx);
 }
 
-- 
1.7.3.4



From marc at cpdesign.com.au  Wed Mar 14 16:43:09 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Thu, 15 Mar 2012 07:43:09 +1100
Subject: [PATCH v3 5/6] mfd: mc13xxx-core: Move spi specific code into
 separate module.
In-Reply-To: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
References: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1331757790-10583-6-git-send-email-marc@cpdesign.com.au>

All spi specific code is moved into a new module. The mc13xxx struct
moves to a new local include file by necessity.

A new config choice selects the SPI bus type support and by default is
value of SPI_MASTER to remain compatible with existing configs.

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/mfd/Kconfig        |   15 ++++-
 drivers/mfd/Makefile       |    1 +
 drivers/mfd/mc13xxx-core.c |  146 ++------------------------------------------
 drivers/mfd/mc13xxx-spi.c  |  138 +++++++++++++++++++++++++++++++++++++++++
 drivers/mfd/mc13xxx.h      |   45 ++++++++++++++
 5 files changed, 201 insertions(+), 144 deletions(-)
 create mode 100644 drivers/mfd/mc13xxx-spi.c
 create mode 100644 drivers/mfd/mc13xxx.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index cd13e9f..501fee5 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -577,12 +577,21 @@ config MFD_MC13XXX
 	select MFD_CORE
 	select MFD_MC13783
 	help
-	  Support for the Freescale (Atlas) PMIC and audio CODECs
-	  MC13783 and MC13892.
-	  This driver provides common support for accessing  the device,
+	  Enable support for the Freescale MC13783 and MC13892 PMICs.
+	  This driver provides common support for accessing the device,
 	  additional drivers must be enabled in order to use the
 	  functionality of the device.
 
+if MFD_MC13XXX
+
+config MFD_MC13XXX_SPI
+	tristate "MC13xxx SPI interface" if SPI_MASTER
+	default SPI_MASTER
+	help
+	  Select this if your MC13xxx is connected via an SPI bus.
+
+endif
+
 config ABX500_CORE
 	bool "ST-Ericsson ABX500 Mixed Signal Circuit register functions"
 	default y if ARCH_U300 || ARCH_U8500
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b953bab..2dc66ed 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_TWL6030_PWM)	+= twl6030-pwm.o
 obj-$(CONFIG_TWL6040_CORE)	+= twl6040-core.o twl6040-irq.o
 
 obj-$(CONFIG_MFD_MC13XXX)	+= mc13xxx-core.o
+obj-$(CONFIG_MFD_MC13XXX_SPI)	+= mc13xxx-spi.o
 
 obj-$(CONFIG_MFD_CORE)		+= mfd-core.o
 
diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index 9804572..31dbf91 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -15,36 +15,13 @@
 #include <linux/platform_device.h>
 #include <linux/mutex.h>
 #include <linux/interrupt.h>
-#include <linux/spi/spi.h>
 #include <linux/mfd/core.h>
 #include <linux/mfd/mc13xxx.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
-#include <linux/regmap.h>
-#include <linux/err.h>
 
-enum mc13xxx_id {
-	MC13XXX_ID_MC13783,
-	MC13XXX_ID_MC13892,
-	MC13XXX_ID_INVALID,
-};
-
-struct mc13xxx {
-	struct regmap *regmap;
-
-	struct device *dev;
-	enum mc13xxx_id ictype;
-
-	struct mutex lock;
-	int irq;
-	int flags;
-
-	irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
-	void *irqdata[MC13XXX_NUM_IRQ];
-
-	int adcflags;
-};
+#include "mc13xxx.h"
 
 #define MC13XXX_IRQSTAT0	0
 #define MC13XXX_IRQSTAT0_ADCDONEI	(1 << 0)
@@ -151,8 +128,6 @@ struct mc13xxx {
 
 #define MC13XXX_ADC2		45
 
-#define MC13XXX_NUMREGS 0x3f
-
 void mc13xxx_lock(struct mc13xxx *mc13xxx)
 {
 	if (!mutex_trylock(&mc13xxx->lock)) {
@@ -667,88 +642,7 @@ static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 }
 #endif
 
-static const struct spi_device_id mc13xxx_device_id[] = {
-	{
-		.name = "mc13783",
-		.driver_data = MC13XXX_ID_MC13783,
-	}, {
-		.name = "mc13892",
-		.driver_data = MC13XXX_ID_MC13892,
-	}, {
-		/* sentinel */
-	}
-};
-MODULE_DEVICE_TABLE(spi, mc13xxx_device_id);
-
-static const struct of_device_id mc13xxx_dt_ids[] = {
-	{ .compatible = "fsl,mc13783", .data = (void *) MC13XXX_ID_MC13783, },
-	{ .compatible = "fsl,mc13892", .data = (void *) MC13XXX_ID_MC13892, },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
-
-static struct regmap_config mc13xxx_regmap_spi_config = {
-	.reg_bits = 7,
-	.val_bits = 25,
-
-	.max_register = MC13XXX_NUMREGS,
-
-	.cache_type = REGCACHE_NONE,
-};
-
-static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
-		struct mc13xxx_platform_data *pdata, int irq);
-
-static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx);
-
-static int mc13xxx_spi_probe(struct spi_device *spi)
-{
-	const struct of_device_id *of_id;
-	struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
-	struct mc13xxx *mc13xxx;
-	struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
-	int ret;
-
-	of_id = of_match_device(mc13xxx_dt_ids, &spi->dev);
-	if (of_id)
-		sdrv->id_table = &mc13xxx_device_id[(enum mc13xxx_id) of_id->data];
-
-	mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
-	if (!mc13xxx)
-		return -ENOMEM;
-
-	dev_set_drvdata(&spi->dev, mc13xxx);
-	spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
-	spi->bits_per_word = 32;
-
-	mc13xxx->dev = &spi->dev;
-	mutex_init(&mc13xxx->lock);
-
-	mc13xxx->regmap = regmap_init_spi(spi, &mc13xxx_regmap_spi_config);
-	if (IS_ERR(mc13xxx->regmap)) {
-		ret = PTR_ERR(mc13xxx->regmap);
-		dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
-				ret);
-		dev_set_drvdata(&spi->dev, NULL);
-		return ret;
-	}
-
-	ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
-
-	if (ret) {
-		dev_set_drvdata(&spi->dev, NULL);
-	} else {
-		const struct spi_device_id *devid =
-			spi_get_device_id(spi);
-		if (!devid || devid->driver_data != mc13xxx->ictype)
-			dev_warn(mc13xxx->dev,
-				"device id doesn't match auto detection!\n");
-	}
-
-	return ret;
-}
-
-static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+int mc13xxx_common_init(struct mc13xxx *mc13xxx,
 		struct mc13xxx_platform_data *pdata, int irq)
 {
 	int ret;
@@ -813,17 +707,9 @@ err_revision:
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(mc13xxx_common_init);
 
-static int __devexit mc13xxx_spi_remove(struct spi_device *spi)
-{
-	struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
-
-	mc13xxx_common_cleanup(mc13xxx);
-
-	return 0;
-}
-
-static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
+void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
 {
 	free_irq(mc13xxx->irq, mc13xxx);
 
@@ -833,29 +719,7 @@ static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
 
 	kfree(mc13xxx);
 }
-
-static struct spi_driver mc13xxx_spi_driver = {
-	.id_table = mc13xxx_device_id,
-	.driver = {
-		.name = "mc13xxx",
-		.owner = THIS_MODULE,
-		.of_match_table = mc13xxx_dt_ids,
-	},
-	.probe = mc13xxx_spi_probe,
-	.remove = __devexit_p(mc13xxx_spi_remove),
-};
-
-static int __init mc13xxx_init(void)
-{
-	return spi_register_driver(&mc13xxx_spi_driver);
-}
-subsys_initcall(mc13xxx_init);
-
-static void __exit mc13xxx_exit(void)
-{
-	spi_unregister_driver(&mc13xxx_spi_driver);
-}
-module_exit(mc13xxx_exit);
+EXPORT_SYMBOL_GPL(mc13xxx_common_cleanup);
 
 MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>");
diff --git a/drivers/mfd/mc13xxx-spi.c b/drivers/mfd/mc13xxx-spi.c
new file mode 100644
index 0000000..3e71df4
--- /dev/null
+++ b/drivers/mfd/mc13xxx-spi.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * loosely based on an earlier driver that has
+ * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/mc13xxx.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/err.h>
+#include <linux/spi/spi.h>
+
+#include "mc13xxx.h"
+
+static const struct spi_device_id mc13xxx_device_id[] = {
+	{
+		.name = "mc13783",
+		.driver_data = MC13XXX_ID_MC13783,
+	}, {
+		.name = "mc13892",
+		.driver_data = MC13XXX_ID_MC13892,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(spi, mc13xxx_device_id);
+
+static const struct of_device_id mc13xxx_dt_ids[] = {
+	{ .compatible = "fsl,mc13783", .data = (void *) MC13XXX_ID_MC13783, },
+	{ .compatible = "fsl,mc13892", .data = (void *) MC13XXX_ID_MC13892, },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
+
+static struct regmap_config mc13xxx_regmap_spi_config = {
+	.reg_bits = 7,
+	.val_bits = 25,
+
+	.max_register = MC13XXX_NUMREGS,
+
+	.cache_type = REGCACHE_NONE,
+};
+
+static int mc13xxx_spi_probe(struct spi_device *spi)
+{
+	const struct of_device_id *of_id;
+	struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
+	struct mc13xxx *mc13xxx;
+	struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
+	int ret;
+
+	of_id = of_match_device(mc13xxx_dt_ids, &spi->dev);
+	if (of_id)
+		sdrv->id_table = &mc13xxx_device_id[(enum mc13xxx_id) of_id->data];
+
+	mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
+	if (!mc13xxx)
+		return -ENOMEM;
+
+	dev_set_drvdata(&spi->dev, mc13xxx);
+	spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
+	spi->bits_per_word = 32;
+
+	mc13xxx->dev = &spi->dev;
+	mutex_init(&mc13xxx->lock);
+
+	mc13xxx->regmap = regmap_init_spi(spi, &mc13xxx_regmap_spi_config);
+	if (IS_ERR(mc13xxx->regmap)) {
+		ret = PTR_ERR(mc13xxx->regmap);
+		dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
+				ret);
+		dev_set_drvdata(&spi->dev, NULL);
+		return ret;
+	}
+
+	ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
+
+	if (ret) {
+		dev_set_drvdata(&spi->dev, NULL);
+	} else {
+		const struct spi_device_id *devid =
+			spi_get_device_id(spi);
+		if (!devid || devid->driver_data != mc13xxx->ictype)
+			dev_warn(mc13xxx->dev,
+				"device id doesn't match auto detection!\n");
+	}
+
+	return ret;
+}
+
+static int __devexit mc13xxx_spi_remove(struct spi_device *spi)
+{
+	struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
+
+	mc13xxx_common_cleanup(mc13xxx);
+
+	return 0;
+}
+
+static struct spi_driver mc13xxx_spi_driver = {
+	.id_table = mc13xxx_device_id,
+	.driver = {
+		.name = "mc13xxx",
+		.owner = THIS_MODULE,
+		.of_match_table = mc13xxx_dt_ids,
+	},
+	.probe = mc13xxx_spi_probe,
+	.remove = __devexit_p(mc13xxx_spi_remove),
+};
+
+static int __init mc13xxx_init(void)
+{
+	return spi_register_driver(&mc13xxx_spi_driver);
+}
+subsys_initcall(mc13xxx_init);
+
+static void __exit mc13xxx_exit(void)
+{
+	spi_unregister_driver(&mc13xxx_spi_driver);
+}
+module_exit(mc13xxx_exit);
+
+MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
+MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/mc13xxx.h b/drivers/mfd/mc13xxx.h
new file mode 100644
index 0000000..bbba06f
--- /dev/null
+++ b/drivers/mfd/mc13xxx.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2012 Creative Product Design
+ * Marc Reilly <marc at cpdesign.com.au>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#ifndef __DRIVERS_MFD_MC13XXX_H
+#define __DRIVERS_MFD_MC13XXX_H
+
+#include <linux/mutex.h>
+#include <linux/regmap.h>
+#include <linux/mfd/mc13xxx.h>
+
+enum mc13xxx_id {
+	MC13XXX_ID_MC13783,
+	MC13XXX_ID_MC13892,
+	MC13XXX_ID_INVALID,
+};
+
+#define MC13XXX_NUMREGS 0x3f
+
+struct mc13xxx {
+	struct regmap *regmap;
+
+	struct device *dev;
+	enum mc13xxx_id ictype;
+
+	struct mutex lock;
+	int irq;
+	int flags;
+
+	irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
+	void *irqdata[MC13XXX_NUM_IRQ];
+
+	int adcflags;
+};
+
+int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+		struct mc13xxx_platform_data *pdata, int irq);
+
+void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx);
+
+#endif /* __DRIVERS_MFD_MC13XXX_H */
-- 
1.7.3.4



From marc at cpdesign.com.au  Wed Mar 14 16:43:10 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Thu, 15 Mar 2012 07:43:10 +1100
Subject: [PATCH v3 6/6] mfd: mc13xxx: Add i2c driver
In-Reply-To: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
References: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1331757790-10583-7-git-send-email-marc@cpdesign.com.au>

Adds support for mc13xxx family ICs connected via i2c.

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/mfd/Kconfig       |    8 +++-
 drivers/mfd/Makefile      |    1 +
 drivers/mfd/mc13xxx-i2c.c |  128 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 136 insertions(+), 1 deletions(-)
 create mode 100644 drivers/mfd/mc13xxx-i2c.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 501fee5..3a039ff 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -573,7 +573,7 @@ config MFD_MC13783
 
 config MFD_MC13XXX
 	tristate "Support Freescale MC13783 and MC13892"
-	depends on SPI_MASTER
+	depends on SPI_MASTER || I2C
 	select MFD_CORE
 	select MFD_MC13783
 	help
@@ -590,6 +590,12 @@ config MFD_MC13XXX_SPI
 	help
 	  Select this if your MC13xxx is connected via an SPI bus.
 
+config MFD_MC13XXX_I2C
+	tristate "MC13xxx I2C interface" if I2C
+	default I2C
+	help
+	  Select this if your MC13xxx is connected via an I2C bus.
+
 endif
 
 config ABX500_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 2dc66ed..6d4566f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_TWL6040_CORE)	+= twl6040-core.o twl6040-irq.o
 
 obj-$(CONFIG_MFD_MC13XXX)	+= mc13xxx-core.o
 obj-$(CONFIG_MFD_MC13XXX_SPI)	+= mc13xxx-spi.o
+obj-$(CONFIG_MFD_MC13XXX_I2C)	+= mc13xxx-i2c.o
 
 obj-$(CONFIG_MFD_CORE)		+= mfd-core.o
 
diff --git a/drivers/mfd/mc13xxx-i2c.c b/drivers/mfd/mc13xxx-i2c.c
new file mode 100644
index 0000000..1fb89af
--- /dev/null
+++ b/drivers/mfd/mc13xxx-i2c.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2009-2010 Creative Product Design
+ * Marc Reilly marc at cpdesign.com.au
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/mc13xxx.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/i2c.h>
+#include <linux/err.h>
+
+#include "mc13xxx.h"
+
+static const struct i2c_device_id mc13xxx_i2c_device_id[] = {
+	{
+		.name = "mc13783",
+		.driver_data = MC13XXX_ID_MC13783
+	}, {
+		.name = "mc13892",
+		.driver_data = MC13XXX_ID_MC13892,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(i2c, mc13xxx_i2c_device_id);
+
+static const struct of_device_id mc13xxx_dt_ids[] = {
+	{ .compatible = "fsl,mc13783", .data = (void *) MC13XXX_ID_MC13783, },
+	{ .compatible = "fsl,mc13892", .data = (void *) MC13XXX_ID_MC13892, },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
+
+static struct regmap_config mc13xxx_regmap_i2c_config = {
+	.reg_bits = 8,
+	.val_bits = 24,
+
+	.max_register = MC13XXX_NUMREGS,
+
+	.cache_type = REGCACHE_NONE,
+};
+
+static int mc13xxx_i2c_probe(struct i2c_client *client,
+		const struct i2c_device_id *id)
+{
+	const struct of_device_id *of_id;
+	struct i2c_driver *idrv = to_i2c_driver(client->dev.driver);
+	struct mc13xxx *mc13xxx;
+	struct mc13xxx_platform_data *pdata = dev_get_platdata(&client->dev);
+	int ret;
+
+	of_id = of_match_device(mc13xxx_dt_ids, &client->dev);
+	if (of_id)
+		idrv->id_table =
+			&mc13xxx_i2c_device_id[(enum mc13xxx_id) of_id->data];
+
+	mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
+	if (!mc13xxx)
+		return -ENOMEM;
+
+	dev_set_drvdata(&client->dev, mc13xxx);
+
+	mc13xxx->dev = &client->dev;
+	mutex_init(&mc13xxx->lock);
+
+	mc13xxx->regmap = regmap_init_i2c(client, &mc13xxx_regmap_i2c_config);
+	if (IS_ERR(mc13xxx->regmap)) {
+		ret = PTR_ERR(mc13xxx->regmap);
+		dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
+				ret);
+		dev_set_drvdata(&client->dev, NULL);
+		return ret;
+	}
+
+	ret = mc13xxx_common_init(mc13xxx, pdata, client->irq);
+
+	if (ret == 0 && (id->driver_data != mc13xxx->ictype))
+		dev_warn(mc13xxx->dev,
+				"device id doesn't match auto detection!\n");
+
+	return ret;
+}
+
+static int __devexit mc13xxx_i2c_remove(struct i2c_client *client)
+{
+	struct mc13xxx *mc13xxx = dev_get_drvdata(&client->dev);
+
+	mc13xxx_common_cleanup(mc13xxx);
+
+	return 0;
+}
+
+static struct i2c_driver mc13xxx_i2c_driver = {
+	.id_table = mc13xxx_i2c_device_id,
+	.driver = {
+		.owner = THIS_MODULE,
+		.name = "mc13xxx",
+		.of_match_table = mc13xxx_dt_ids,
+	},
+	.probe = mc13xxx_i2c_probe,
+	.remove = __devexit_p(mc13xxx_i2c_remove),
+};
+
+static int __init mc13xxx_i2c_init(void)
+{
+	return i2c_add_driver(&mc13xxx_i2c_driver);
+}
+subsys_initcall(mc13xxx_i2c_init);
+
+static void __exit mc13xxx_i2c_exit(void)
+{
+	i2c_del_driver(&mc13xxx_i2c_driver);
+}
+module_exit(mc13xxx_i2c_exit);
+
+MODULE_DESCRIPTION("i2c driver for Freescale MC13XXX PMIC");
+MODULE_AUTHOR("Marc Reilly <marc at cpdesign.com.au");
+MODULE_LICENSE("GPL v2");
-- 
1.7.3.4



From arnd at arndb.de  Wed Mar 14 17:40:54 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 14 Mar 2012 21:40:54 +0000
Subject: [PATCH v3 2/5] ARM: Add a printk loglevel modifier
In-Reply-To: <20120314200630.GB2391@pengutronix.de>
References: <20120314101928.GA29474@pengutronix.de>
 <201203141312.51547.arnd@arndb.de> <20120314200630.GB2391@pengutronix.de>
Message-ID: <201203142140.55052.arnd@arndb.de>

On Wednesday 14 March 2012, Uwe Kleine-K?nig wrote:
> I don't get your reasoning here.
> 
> An (independant) printk (that is expected to start at a new line) must
> start with KERN_SOMETHING iff the previous printk always ends in \n?
> Probably not. 
> 
> Independently of the correctness of the first patch that splits the
> printk I'm just taking it as an example:
> 
> In this case the two printks in question are:
> 
>                 printk("CPU: %s [%08x] revision %d (ARMv%s)", ...);
>         #ifdef CONFIG_CPU_CP15
>                 printk(KERN_CONT ", cr=%08lx\n", cr_alignment);
>         #endif
> 
> and
> 
>                 printk("CPU: %s data cache, %s instruction cache\n", ...)
> 
> In this case it's correct to add KERN_INFO to the last printk, isn't it?
> When would you consider it to be wrong?

I forgot about KERN_CONT, which did not exist until a few years ago
and is still not all that common. Initially, KERN_CONT was just an
empty string that was used to make it clear when a printk was
intentionally used as a continuation of the previous line, rather
than having no KERN_* at all.

In the example above, the first and the second line should get a KERN_INFO
or one of the others.

> If you want to have the first group of printks to always end in \n, I'd
> have to do:
> 
>                 printk("CPU: %s [%08x] revision %d (ARMv%s)", ...);
>         #ifdef CONFIG_CPU_CP15
>                 printk(KERN_CONT ", cr=%08lx", cr_alignment);
>         #endif
>                 printk(KERN_CONT "\n");
> 
> but ISTR Linus (Torvalds) telling me that KERN_CONT "\n" is wrong and
> should just be skipped.

Ok, didn't know that.

	Arnd


From khilman at ti.com  Wed Mar 14 17:53:45 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 14 Mar 2012 14:53:45 -0700
Subject: [PATCH 01/12] mfd: twl-core: don't depend on pdata->irq_base/end
In-Reply-To: <87pqcegapk.fsf@ti.com> (Kevin Hilman's message of "Wed, 14 Mar
 2012 13:59:51 -0700")
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-2-git-send-email-b-cousson@ti.com>
 <87pqcegapk.fsf@ti.com>
Message-ID: <87k42metna.fsf@ti.com>

Kevin Hilman <khilman at ti.com> writes:

> Benoit Cousson <b-cousson at ti.com> writes:
>
>> From: Felipe Balbi <balbi at ti.com>
>>
>> With sparse IRQs the driver shouldn't depend at all on
>> any IRQ values coming from board-file.
>>
>> Remove every occurences of pdata->irq_base/end.
>
> Well, not quite *every*. :)
>
> If the driver isn't going to use those fields anymore, they should also
> be removed from the pdata struct too[1].  Also, the remaining board/init
> code that is initializing those fields should be removed as well[2], since
> it obviously has no effect.
>
> The first patch below should probably be folded into this one, and then
> the 2nd patch removes all the users.

Below is a correct version of the 2nd patch which removes all the users.

The previous version wouldn't apply cleanly because I generated it on
top of a local branch that also included some other changes to
twl-common.c from the SMPS regulator series (which seems to have missed
the window for v3.4.)

This one applies cleanly on your for_3.4/twl_irq_gpio_mmc_fix branch.

Kevin

>From b59a4754fb66f6f729ebbd0563c4cd2bd2cda56e Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman at ti.com>
Date: Wed, 14 Mar 2012 13:56:01 -0700
Subject: [PATCH] ARM: OMAP2+: TWL: remove usage of pdata->irq_base/_end

The driver has been converted to use SPARSE_IRQ and no longer needs to
be passed IRQ base/end.  The driver no longer uses these fields, so
remove them from the reamaining users.

Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/board-2430sdp.c    |    3 ---
 arch/arm/mach-omap2/board-omap3logic.c |    3 ---
 arch/arm/mach-omap2/twl-common.c       |   10 ----------
 3 files changed, 16 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 7370983..7dfcb96 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -218,9 +218,6 @@ static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
 };
 
 static struct twl4030_platform_data sdp2430_twldata = {
-	.irq_base	= TWL4030_IRQ_BASE,
-	.irq_end	= TWL4030_IRQ_END,
-
 	/* platform_data for children goes here */
 	.gpio		= &sdp2430_gpio_data,
 	.vmmc1		= &sdp2430_vmmc1,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 4198dd0..0b053b4 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -85,9 +85,6 @@ static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
 };
 
 static struct twl4030_platform_data omap3logic_twldata = {
-	.irq_base	= TWL4030_IRQ_BASE,
-	.irq_end	= TWL4030_IRQ_END,
-
 	/* platform_data for children goes here */
 	.gpio		= &omap3logic_gpio_data,
 	.vmmc1		= &omap3logic_vmmc1,
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 10b20c6..ce349ac 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -129,11 +129,6 @@ static struct regulator_init_data omap3_vpll2_idata = {
 void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
 				  u32 pdata_flags, u32 regulators_flags)
 {
-	if (!pmic_data->irq_base)
-		pmic_data->irq_base = TWL4030_IRQ_BASE;
-	if (!pmic_data->irq_end)
-		pmic_data->irq_end = TWL4030_IRQ_END;
-
 	/* Common platform data configurations */
 	if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
 		pmic_data->usb = &omap3_usb_pdata;
@@ -287,11 +282,6 @@ static struct regulator_init_data omap4_clk32kg_idata = {
 void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
 				  u32 pdata_flags, u32 regulators_flags)
 {
-	if (!pmic_data->irq_base)
-		pmic_data->irq_base = TWL6030_IRQ_BASE;
-	if (!pmic_data->irq_end)
-		pmic_data->irq_end = TWL6030_IRQ_END;
-
 	/* Common platform data configurations */
 	if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
 		pmic_data->usb = &omap4_usb_pdata;
-- 
1.7.9.2



From u.kleine-koenig at pengutronix.de  Wed Mar 14 17:53:44 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 14 Mar 2012 22:53:44 +0100
Subject: [PATCH v3 1/5] ARM: protect usage of cr_alignment by #ifdef
 CONFIG_CPU_CP15
In-Reply-To: <alpine.LFD.2.02.1203141710210.24151@xanadu.home>
References: <20120314101928.GA29474@pengutronix.de>
 <1331720483-10075-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <alpine.LFD.2.02.1203141103080.24151@xanadu.home>
 <20120314195120.GA2391@pengutronix.de>
 <alpine.LFD.2.02.1203141710210.24151@xanadu.home>
Message-ID: <20120314215344.GD2391@pengutronix.de>

Hello Nicolas,

On Wed, Mar 14, 2012 at 05:19:53PM -0400, Nicolas Pitre wrote:
> On Wed, 14 Mar 2012, Uwe Kleine-K?nig wrote:
> > On Wed, Mar 14, 2012 at 11:24:36AM -0400, Nicolas Pitre wrote:
> > > >  	flush_cache_all();
> > > > +#ifdef CONFIG_CPU_CP15
> > > >  	set_cr(cr_alignment);
> > > > +#endif
> > > 
> > > However it might be best to provide a dummy set_cr() instead of 
> > > #ifdef'ing it out everywhere.
> > What should the dummy set_cr do? Print a runtime warning if called with
> > != 0?
> 
> Maybe not.  In fact if that code path is used, then something might be 
> wrong at a higher level.
And that's why I choosed not to implement a dummy set_cr ...

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From khilman at ti.com  Wed Mar 14 18:06:37 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 14 Mar 2012 15:06:37 -0700
Subject: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting to
 add IVA OPP
In-Reply-To: <CAOMWX4eYQvwHfpci1AgLO8kk1yxzB-zruMQQvLXeLnxbfUHFgw@mail.gmail.com>
 (Nishanth Menon's message of "Wed, 14 Mar 2012 16:35:17 -0500")
References: <1331746695-24372-1-git-send-email-mvs@tigris.de>
 <874ntqg9yr.fsf@ti.com>
 <CAOMWX4eYQvwHfpci1AgLO8kk1yxzB-zruMQQvLXeLnxbfUHFgw@mail.gmail.com>
Message-ID: <8762e6et1u.fsf@ti.com>

"Menon, Nishanth" <nm at ti.com> writes:

> On Wed, Mar 14, 2012 at 16:15, Kevin Hilman <khilman at ti.com> wrote:
>> Maximilian Schwerin <mvs at tigris.de> writes:
>>
>>> From: Steve Sakoman <steve at sakoman.com>
>>>
>>> Don't try to add IVA OPPs for OMAP3 versions not containing an IVA
>>> subsystem, as this would make omap_init_opp_table fail.
>>>
>>> Signed-off-by: Steve Sakoman <steve at sakoman.com>
>>> Signed-off-by: Maximilian Schwerin <mvs at tigris.de>
>>
>> Minor: patch subjects for arch/arm/* core code need to have the ARM:
>> prefix also.
>>
>> Also, please run scripts/checkpatch.pl on your patch and fix the
>> warnings.
>>
>>> ---
>>> ?arch/arm/mach-omap2/opp.c | ? ?4 ++++
>>> ?1 files changed, 4 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
>>> index 9262a6b..414f2ec 100644
>>> --- a/arch/arm/mach-omap2/opp.c
>>> +++ b/arch/arm/mach-omap2/opp.c
>>> @@ -62,6 +62,10 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __func__, i);
>>> ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;
>>> ? ? ? ? ? ? ? }
>>> +
>>> + ? ? ? ? ? ? if ((strcmp(opp_def->hwmod_name,"iva") == 0) && !omap3_has_iva())
>>> + ? ? ? ? ? ? ? ? ? ? continue;
>>> +
>>> ? ? ? ? ? ? ? oh = omap_hwmod_lookup(opp_def->hwmod_name);
>>> ? ? ? ? ? ? ? if (!oh || !oh->od) {
>>> ? ? ? ? ? ? ? ? ? ? ? pr_warn("%s: no hwmod or odev for %s, [%d] "
>>
>> Wouldn't the one-liner below do the same thing?
>>
>> Actually, your patch makes it less noisy at boot time, avoiding the
>> pr_warn(), so is probably better.
>
> The only issue i have with current patch is that it focusses to solve
> a specific device IVA.
> we could have similar variances if we had SGX/AESS device etc
> registered in the common
> table. a generic solution might be preferable - could we reduce the
> severity of pr_warn to pr_debug and do a continue instead?

I agree, that would be a better generic solution.

Kevin


From mturquette at ti.com  Wed Mar 14 18:13:28 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 14 Mar 2012 15:13:28 -0700
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <alpine.LFD.2.02.1203142218320.2466@ionos>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120313112447.GA29317@pengutronix.de>
 <CAJOA=zMTY+4dU9VUa-TkEbdE-WJd7V4tCG-af6vgq0CPN6rWpg@mail.gmail.com>
 <20120314084857.GL3852@pengutronix.de>
 <CAJOA=zMsCuZgmp1Hm0dq=EVoX6Zj62XQVqR=6GzDntSD5HnHzg@mail.gmail.com>
 <alpine.LFD.2.02.1203142218320.2466@ionos>
Message-ID: <CAJOA=zNj8eC+h-S9KqwuAEiGFZMAn2h0TNTR6nund4qM7Z97ug@mail.gmail.com>

On Wed, Mar 14, 2012 at 2:28 PM, Thomas Gleixner <tglx at linutronix.de> wrote:
> On Wed, 14 Mar 2012, Turquette, Mike wrote:
>
> Could you folks please trim your replies? It's annoying to page down a
> gazillion of lines to find the gist.

Sure.  My mailer does this for me so I forget to do it sometimes...

>> On Wed, Mar 14, 2012 at 1:48 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>> >> Also, do you forsee needing hole in parent_names for any reason other
>> >> than described above?
>> >
>> > I need it only for the case where a some values in the mux are marked as
>> > reserved in the datasheet or we simply do not have the corresponding
>> > clock in our tree (yet). We could also say that NULL pointers are not
>> > allowed in parent arrays, but instead "orphan" or "dummy" should be
>> > used. Then __clk_init should check for NULL pointers to make this clear.
>>
>> I've added a WARN in __clk_init if any entries in .parent_names are
>> NULL. ?I think it best to populate it with "dummy", or maybe a
>> platform-specific name if it helps you during development.
>
> There is no guarantee that the selection of a parent can be mapped
> linear to register values.

Agreed.  I have always viewed .parent_names as only a list of the
names of all possible parents, nothing more.  And of course its array
indexing should line up with struct clk **parents.

> So the right way to deal with it is to have an array of valid names
> with no holes and NULL pointers allowed and have a mapping from the
> array index to the register value.

This is essentially what the .set_rate callback does.  It takes as
input "u8 index" and peforms the hardware specific magic to select the
correct parent clock.  This might be a register write using that exact
same index, or it might be a single-bit register write using that
index as the shift value, or it might translate that index into the
data sent to an i2c device (where the address would be stored in
struct clk_foo), etc etc.

We both agree that .parent_names must contain valid names and should
not have holes.  What I don't understand is if you are saying that we
should allow NULL ptrs as names; that seems contradictory but I want
to make sure I'm reading you correctly.

Thanks,
Mike

> That makes the core code robust and allows to handle all corner cases
> including reserved bits, not implemented clocks and weird register
> layouts.
>
> Thanks,
>
> ? ? ? ?tglx


From tony at atomide.com  Wed Mar 14 18:14:54 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 14 Mar 2012 15:14:54 -0700
Subject: [PATCH 01/12] mfd: twl-core: don't depend on pdata->irq_base/end
In-Reply-To: <87pqcegapk.fsf@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-2-git-send-email-b-cousson@ti.com>
 <87pqcegapk.fsf@ti.com>
Message-ID: <20120314221454.GS12083@atomide.com>

* Kevin Hilman <khilman at ti.com> [120314 14:02]:
> From: Kevin Hilman <khilman at ti.com>
> Date: Wed, 14 Mar 2012 13:56:01 -0700
> Subject: [PATCH 2/2] ARM: OMAP2+: TWL: remove usage of pdata->irq_base/_end
> 
> The driver has been converted to use SPARSE_IRQ and no longer needs to
> be passed IRQ base/end.  The driver no longer uses these fields, so
> remove them from the reamaining users.
> 
> Signed-off-by: Kevin Hilman <khilman at ti.com>
> ---
>  arch/arm/mach-omap2/board-2430sdp.c    |    3 ---
>  arch/arm/mach-omap2/board-omap3logic.c |    3 ---
>  arch/arm/mach-omap2/twl-common.c       |    9 ---------
>  3 files changed, 15 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
> index c8bda62..b8b3700 100644
> --- a/arch/arm/mach-omap2/board-2430sdp.c
> +++ b/arch/arm/mach-omap2/board-2430sdp.c
> @@ -218,9 +218,6 @@ static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
>  };
>  
>  static struct twl4030_platform_data sdp2430_twldata = {
> -	.irq_base	= TWL4030_IRQ_BASE,
> -	.irq_end	= TWL4030_IRQ_END,
> -
>  	/* platform_data for children goes here */
>  	.gpio		= &sdp2430_gpio_data,
>  	.vmmc1		= &sdp2430_vmmc1,
> diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
> index 4a7d8c8..f145935 100644
> --- a/arch/arm/mach-omap2/board-omap3logic.c
> +++ b/arch/arm/mach-omap2/board-omap3logic.c
> @@ -85,9 +85,6 @@ static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
>  };
>  
>  static struct twl4030_platform_data omap3logic_twldata = {
> -	.irq_base	= TWL4030_IRQ_BASE,
> -	.irq_end	= TWL4030_IRQ_END,
> -
>  	/* platform_data for children goes here */
>  	.gpio		= &omap3logic_gpio_data,
>  	.vmmc1		= &omap3logic_vmmc1,
> diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
> index 1cddcb2..5c9aa3f 100644
> --- a/arch/arm/mach-omap2/twl-common.c
> +++ b/arch/arm/mach-omap2/twl-common.c
> @@ -184,10 +184,6 @@ static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
>  void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
>  				  u32 pdata_flags, u32 regulators_flags)
>  {
> -	if (!pmic_data->irq_base)
> -		pmic_data->irq_base = TWL4030_IRQ_BASE;
> -	if (!pmic_data->irq_end)
> -		pmic_data->irq_end = TWL4030_IRQ_END;
>  	if (!pmic_data->vdd1) {
>  		omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
>  		omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
> @@ -415,11 +411,6 @@ static struct twl_regulator_driver_data omap4_vdd3_drvdata = {
>  void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
>  				  u32 pdata_flags, u32 regulators_flags)
>  {
> -	if (!pmic_data->irq_base)
> -		pmic_data->irq_base = TWL6030_IRQ_BASE;
> -	if (!pmic_data->irq_end)
> -		pmic_data->irq_end = TWL6030_IRQ_END;
> -
>  	if (!pmic_data->vdd1) {
>  		omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
>  		omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
> -- 

Looks right to me:

Acked-by: Tony Lindgren <tony at atomide.com>


From festevam at gmail.com  Wed Mar 14 18:15:01 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 14 Mar 2012 19:15:01 -0300
Subject: [PATCH v3 6/6] mfd: mc13xxx: Add i2c driver
In-Reply-To: <1331757790-10583-7-git-send-email-marc@cpdesign.com.au>
References: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
 <1331757790-10583-7-git-send-email-marc@cpdesign.com.au>
Message-ID: <CAOMZO5BVObpszMd4_dDr3NHw9-oXh9wY_T48UA2vMWozdUyukw@mail.gmail.com>

Hi Marc,

On Wed, Mar 14, 2012 at 5:43 PM, Marc Reilly <marc at cpdesign.com.au> wrote:

> +
> +static const struct i2c_device_id mc13xxx_i2c_device_id[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .name = "mc13783",
> + ? ? ? ? ? ? ? .driver_data = MC13XXX_ID_MC13783

mc13783 does not have i2c interface.


From tglx at linutronix.de  Wed Mar 14 18:18:44 2012
From: tglx at linutronix.de (Thomas Gleixner)
Date: Wed, 14 Mar 2012 23:18:44 +0100 (CET)
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zNj8eC+h-S9KqwuAEiGFZMAn2h0TNTR6nund4qM7Z97ug@mail.gmail.com>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120313112447.GA29317@pengutronix.de>
 <CAJOA=zMTY+4dU9VUa-TkEbdE-WJd7V4tCG-af6vgq0CPN6rWpg@mail.gmail.com>
 <20120314084857.GL3852@pengutronix.de>
 <CAJOA=zMsCuZgmp1Hm0dq=EVoX6Zj62XQVqR=6GzDntSD5HnHzg@mail.gmail.com>
 <alpine.LFD.2.02.1203142218320.2466@ionos>
 <CAJOA=zNj8eC+h-S9KqwuAEiGFZMAn2h0TNTR6nund4qM7Z97ug@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1203142317280.2466@ionos>

On Wed, 14 Mar 2012, Turquette, Mike wrote:
> On Wed, Mar 14, 2012 at 2:28 PM, Thomas Gleixner <tglx at linutronix.de> wrote:
> > So the right way to deal with it is to have an array of valid names
> > with no holes and NULL pointers allowed and have a mapping from the
> > array index to the register value.
> 
> This is essentially what the .set_rate callback does.  It takes as
> input "u8 index" and peforms the hardware specific magic to select the
> correct parent clock.  This might be a register write using that exact
> same index, or it might be a single-bit register write using that
> index as the shift value, or it might translate that index into the
> data sent to an i2c device (where the address would be stored in
> struct clk_foo), etc etc.
> 
> We both agree that .parent_names must contain valid names and should
> not have holes.  What I don't understand is if you are saying that we
> should allow NULL ptrs as names; that seems contradictory but I want
> to make sure I'm reading you correctly.

I should have said: no holes and no NULL pointers, just an array of
valid names.

Thanks,

	tglx


From olof at lixom.net  Wed Mar 14 18:37:15 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 14 Mar 2012 15:37:15 -0700
Subject: [PATCH v4 11/12] ARM: EXYNOS: add support device tree enabled
 board file for EXYNOS5
In-Reply-To: <1331736138-28964-12-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
 <1331736138-28964-12-git-send-email-kgene.kim@samsung.com>
Message-ID: <20120314223715.GA13872@quad.lixom.net>

On Wed, Mar 14, 2012 at 07:42:17AM -0700, Kukjin Kim wrote:
> This patch adds a new EXYNOS5 compatible device tree enabled board
> When using this, a corresponding device tree blob which describes the
> board's properties should be supplied at boot time to the kernel.

Hi,

Sorry, missed this last time around:

> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index a2ed05c..ac24386 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -362,7 +362,18 @@ config MACH_SMDK4412
>  	  Machine support for Samsung SMDK4412
>  endif
>  
> -comment "Flattened Device Tree based board for Exynos4 based SoC"
> +if ARCH_EXYNOS5
> +
> +comment "EXYNOS5250 Boards"
> +
> +config MACH_SMDK5250
> +	bool "SMDK5250"
> +	select SOC_EXYNOS5250
> +	help
> +	  Machine support for Samsung SMDK5250
> +endif


There's no board file for SMDK5250 in this series (and there shouldn't be since
it should all be covered by MACH_EXYNOS5_DT. So the above config option can go
away.


-Olof


From olof at lixom.net  Wed Mar 14 18:40:01 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 14 Mar 2012 15:40:01 -0700
Subject: [PATCH v4 00/12] ARM: EXYNOS: add support new EXYNOS5250
In-Reply-To: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <20120314224001.GB13872@quad.lixom.net>

On Wed, Mar 14, 2012 at 07:42:06AM -0700, Kukjin Kim wrote:
> This patch adds support EXYNOS5250 SoC which has two A15 cores
> can be used on mobile and tablet devices.

Looks good. I've switched back with Arnd so he does pulls right now,
but I'd be OK with this going in as it is now (see one nit to fixup when you
build the branch -- no need to repost with it I think).


So, I'll leave it up to Arnd to pull but it looks good enough for me at this
time.


-Olof



From b-cousson at ti.com  Wed Mar 14 18:50:13 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Wed, 14 Mar 2012 23:50:13 +0100
Subject: [GIT PULL] ARM: OMAP: i2c, gpio, spi and regulator DTS updates
In-Reply-To: <4F5E89B4.4010505@ti.com>
References: <4F5E89B4.4010505@ti.com>
Message-ID: <4F6120A5.6050407@ti.com>

Hi Tony,

It looks like Chris Ball just queued  the HSMMC DT stuff from Rajendra, 
so I can add as well the MMC DTS for OMAP3 and OMAP4 as well.

It is fine for an update?

Than I can add as Kevin's patch for twl irq_base removal.

Thanks,
Benoit

On 3/13/2012 12:41 AM, Cousson, Benoit wrote:
> Hi Tony,
>
> Here are the remaining DTS patches for 3.4.
>
> Ideally all the driver DT adaptation should have been merged before that one.
>
> This series is based on your lo/dt-part2 branch.
>
> Thanks,
> Benoit
>
>
> The following changes since commit 328ae2cb50af2f96b6061eb462aa92966a462bbc:
>    Ilya Yanok (1):
>          arm/dts: mt_ventoux: very basic support for TeeJet Mt.Ventoux board
>
> are available in the git repository at:
>
>    git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/dts/all
>
> Benoit Cousson (11):
>        arm/dts: twl6030: Add DTS file for twl6030 PMIC
>        arm/dts: twl4030: Add DTS file for twl4030 PM + Audio IC
>        arm/dts: omap4-panda: Add twl6030 and i2c EEPROM
>        arm/dts: omap4-sdp: Add twl6030, i2c3 and i2c4 devices
>        arm/dts: omap3-beagle: Add twl4030 and i2c EEPROM
>        ARM: OMAP2+: board-generic: Remove i2c static init
>        arm/dts: OMAP4: Add gpio nodes
>        arm/dts: OMAP3: Add gpio nodes
>        arm/dts: OMAP4: Add SPI controller nodes
>        arm/dts: OMAP3: Add SPI controller nodes
>        arm/dts: omap4-sdp: Add ks8851 ethernet SPI device
>
> Rajendra Nayak (1):
>        arm/dts: twl: Pass regulator data from dt
>
>   arch/arm/boot/dts/omap3-beagle.dts  |   35 ++++++++++++++
>   arch/arm/boot/dts/omap3.dtsi        |   86 +++++++++++++++++++++++++++++++++++
>   arch/arm/boot/dts/omap4-panda.dts   |   34 ++++++++++++++
>   arch/arm/boot/dts/omap4-sdp.dts     |   73 +++++++++++++++++++++++++++++
>   arch/arm/boot/dts/omap4.dtsi        |   86 +++++++++++++++++++++++++++++++++++
>   arch/arm/boot/dts/twl4030.dtsi      |   39 ++++++++++++++++
>   arch/arm/boot/dts/twl6030.dtsi      |   86 +++++++++++++++++++++++++++++++++++
>   arch/arm/mach-omap2/board-generic.c |   37 +--------------
>   arch/arm/mach-omap2/devices.c       |    4 +-
>   arch/arm/mach-omap2/gpio.c          |    8 +++-
>   10 files changed, 450 insertions(+), 38 deletions(-)
>   create mode 100644 arch/arm/boot/dts/twl4030.dtsi
>   create mode 100644 arch/arm/boot/dts/twl6030.dtsi
>



From tony at atomide.com  Wed Mar 14 18:57:43 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 14 Mar 2012 15:57:43 -0700
Subject: [GIT PULL] ARM: OMAP: i2c, gpio, spi and regulator DTS updates
In-Reply-To: <4F6120A5.6050407@ti.com>
References: <4F5E89B4.4010505@ti.com>
 <4F6120A5.6050407@ti.com>
Message-ID: <20120314225743.GT12083@atomide.com>

* Cousson, Benoit <b-cousson at ti.com> [120314 15:52]:
> Hi Tony,
> 
> It looks like Chris Ball just queued  the HSMMC DT stuff from
> Rajendra, so I can add as well the MMC DTS for OMAP3 and OMAP4 as
> well.
> 
> It is fine for an update?

Sure, I'm not planning to pull this until after the merge
window.
 
> Than I can add as Kevin's patch for twl irq_base removal.

Hmm I don't follow. That's needed first as a fix for the
merge window?

Regards,

Tony 


From b04825 at freescale.com  Wed Mar 14 19:00:41 2012
From: b04825 at freescale.com (Timur Tabi)
Date: Wed, 14 Mar 2012 18:00:41 -0500
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120314122723.GC3133@opensource.wolfsonmicro.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
Message-ID: <4F612319.50302@freescale.com>

Mark Brown wrote:

> All of which is exactly the same as for any other device and essentially
> irrelevant to how we define the bindings for the cards.

So using imx-audio-sgtl5000.txt as an example, you're saying that if I
have two SSIs, I should do this in my device tree:

sound1 {
	compatible = "fsl,imx51-babbage-sgtl5000",
		     "fsl,imx-audio-sgtl5000";
	model = "imx51-babbage-sgtl5000";
	ssi-controller = <&ssi1>;
	audio-codec = <&sgtl5000_1>;
	mux-int-port = <1>;
	mux-ext-port = <3>;
};

sound2 {
	compatible = "fsl,imx51-babbage-sgtl5000",
		     "fsl,imx-audio-sgtl5000";
	model = "imx51-babbage-sgtl5000";
	ssi-controller = <&ssi2>;
	audio-codec = <&sgtl5000_2>;
	mux-int-port = <1>;
	mux-ext-port = <3>;
};

>>> The biggest improvement is that the SoC binding knows nothing about the
>>> card binding at all, cards are completely separate and are free to
>>> define any binding they choose using any number of on-SoC and off-SoC
>>> devices.
> 
>> Ok, I don't understand that at all.
> 
> Do you have some questions about the above?  What is it that you find
> unclear?   

What's the difference between an "SoC binding" and a "card binding"?

> We've been through this *repeatedly*, including in the message you're
> replying to, and we're still going back to square one every time you
> decide to start talking about device tree again.  This is frustrating
> in the extreme.

I'm sorry you're frustrated, but so am I.  I still don't understand why
the binding that I invented for the SSI driver isn't good enough for i.MX.
 The binding and the code was documented and approved a long time ago.
Why can't we keep the same binding on i.MX, to keep the code simpler?

-- 
Timur Tabi
Linux kernel developer at Freescale



From timur at freescale.com  Wed Mar 14 19:02:44 2012
From: timur at freescale.com (Timur Tabi)
Date: Wed, 14 Mar 2012 18:02:44 -0500
Subject: [PATCH v4] ASoC: add imx-sgtl5000 machine driver working with
 fsl_ssi
In-Reply-To: <20120314090115.GN3852@pengutronix.de>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
 <20120314090115.GN3852@pengutronix.de>
Message-ID: <4F612394.4060703@freescale.com>

Sascha Hauer wrote:
> What are the next steps here? Now we have fsl_ssi.c and imx-ssi.c, one
> for dt bindings and the other one for platform bindings and also AC97
> support. They should probably get merged some day which might be a bit
> difficult since currently I don't see the platform users moving over
> to devicetree and the seem to be no AC97 users in powerpc.

I don't have any problem with adding AC97 support to fsl_ssi.c, assuming
it's not a huge mess.  I don't know enough about AC97 to know how easy
that is, though.

-- 
Timur Tabi
Linux kernel developer at Freescale



From b-cousson at ti.com  Wed Mar 14 19:04:04 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Thu, 15 Mar 2012 00:04:04 +0100
Subject: [GIT PULL] ARM: OMAP: i2c, gpio, spi and regulator DTS updates
In-Reply-To: <20120314225743.GT12083@atomide.com>
References: <4F5E89B4.4010505@ti.com> <4F6120A5.6050407@ti.com>
 <20120314225743.GT12083@atomide.com>
Message-ID: <4F6123E4.5090808@ti.com>

On 3/14/2012 11:57 PM, Tony Lindgren wrote:
> * Cousson, Benoit<b-cousson at ti.com>  [120314 15:52]:
>> Hi Tony,
>>
>> It looks like Chris Ball just queued  the HSMMC DT stuff from
>> Rajendra, so I can add as well the MMC DTS for OMAP3 and OMAP4 as
>> well.
>>
>> It is fine for an update?
>
> Sure, I'm not planning to pull this until after the merge
> window.

OK, so we will not have the DTS support for the new drivers for 3.4 :-(

Well, if you pull that in a lo branch, that will be enough to base the 
further work on it.

>> Than I can add as Kevin's patch for twl irq_base removal.
>
> Hmm I don't follow. That's needed first as a fix for the
> merge window?

No, not that one. It is just some more cleanup on top of the one Felipe 
already did in the twl series I've just sent to Samuel.
But if you do not plan to pull that series for 3.4, that does not really 
matter.

Regards,
Benoit


From kgene.kim at samsung.com  Wed Mar 14 19:18:57 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 16:18:57 -0700
Subject: [PATCH v4 11/12] ARM: EXYNOS: add support device tree enabled
 board file for EXYNOS5
In-Reply-To: <20120314223715.GA13872@quad.lixom.net>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
 <1331736138-28964-12-git-send-email-kgene.kim@samsung.com>
 <20120314223715.GA13872@quad.lixom.net>
Message-ID: <4F612761.6050903@samsung.com>

Olof Johansson wrote:
> On Wed, Mar 14, 2012 at 07:42:17AM -0700, Kukjin Kim wrote:
>> This patch adds a new EXYNOS5 compatible device tree enabled board
>> When using this, a corresponding device tree blob which describes the
>> board's properties should be supplied at boot time to the kernel.
>
> Hi,
>
Hi Olof,

> Sorry, missed this last time around:
>
No problem and thanks.

>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index a2ed05c..ac24386 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -362,7 +362,18 @@ config MACH_SMDK4412
>>   	  Machine support for Samsung SMDK4412
>>   endif
>>
>> -comment "Flattened Device Tree based board for Exynos4 based SoC"
>> +if ARCH_EXYNOS5
>> +
>> +comment "EXYNOS5250 Boards"
>> +
>> +config MACH_SMDK5250
>> +	bool "SMDK5250"
>> +	select SOC_EXYNOS5250
>> +	help
>> +	  Machine support for Samsung SMDK5250
>> +endif
>
>
> There's no board file for SMDK5250 in this series (and there shouldn't be since
> it should all be covered by MACH_EXYNOS5_DT. So the above config option can go
> away.
>
Yeah, you're right. I think, it seem that remained after just testing 
anyway, it will be fixed before sending pull request.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From hartleys at visionengravers.com  Wed Mar 14 19:19:50 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 14 Mar 2012 18:19:50 -0500
Subject: [PATCH v4 00/10] Add PWM framework and device tree support.
In-Reply-To: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020695DB5858@AUSP01VMBX24.collaborationhost.net>

On Wednesday, March 14, 2012 8:56 AM, Thierry Reding wrote:
> 
> This patch series adds very rudimentary device-tree support for PWM
> devices. With all of these patches applied (plus one board-specific
> patch that is not included), I'm able to control the backlight on the
> device I'm working on using the sysfs interface provided by the pwm-bl
> driver and the backlight class.

Hello Thierry,

Are you planning on adding a sysfs interface for generic userspace access
to the PWM devices?

I have tested your patches (with a couple fixes already mentioned) on a
ep93xx board and have converted the drivers/misc/ep93xx_pwm.c driver
to use the framework.  Everything "seems" to work but my use for the
PWM is from userspace so I can't really test anything.

I have hacked in the sysfs interface from the ep93xx_pwm driver but it
is a hack... It's not really using the framework to control the PWM since
all the sysfs knobs are directly accessing the pwm registers.

Anyway, I would be happy to convert the current driver to the new framework
and get it out of drivers/misc and into a proper location. But, before I can do
that, I need to be able to control the PWM from userspace somehow.

Maybe an interface similar to the one gpiolib provides with CONFIG_GPIO_SYSFS?

Regards,
Hartley



From kgene.kim at samsung.com  Wed Mar 14 19:20:27 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 14 Mar 2012 16:20:27 -0700
Subject: [PATCH v4 00/12] ARM: EXYNOS: add support new EXYNOS5250
In-Reply-To: <20120314224001.GB13872@quad.lixom.net>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
 <20120314224001.GB13872@quad.lixom.net>
Message-ID: <4F6127BB.1070406@samsung.com>

Olof Johansson wrote:
> On Wed, Mar 14, 2012 at 07:42:06AM -0700, Kukjin Kim wrote:
>> This patch adds support EXYNOS5250 SoC which has two A15 cores
>> can be used on mobile and tablet devices.
>
> Looks good. I've switched back with Arnd so he does pulls right now,
> but I'd be OK with this going in as it is now (see one nit to fixup when you
> build the branch -- no need to repost with it I think).
>
OK, let me do it.

> So, I'll leave it up to Arnd to pull but it looks good enough for me at this
> time.
>
OK, I see.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From tony at atomide.com  Wed Mar 14 19:21:47 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 14 Mar 2012 16:21:47 -0700
Subject: [GIT PULL] ARM: OMAP: i2c, gpio, spi and regulator DTS updates
In-Reply-To: <4F6123E4.5090808@ti.com>
References: <4F5E89B4.4010505@ti.com> <4F6120A5.6050407@ti.com>
 <20120314225743.GT12083@atomide.com> <4F6123E4.5090808@ti.com>
Message-ID: <20120314232147.GU12083@atomide.com>

* Cousson, Benoit <b-cousson at ti.com> [120314 16:06]:
> On 3/14/2012 11:57 PM, Tony Lindgren wrote:
> >* Cousson, Benoit<b-cousson at ti.com>  [120314 15:52]:
> >>Hi Tony,
> >>
> >>It looks like Chris Ball just queued  the HSMMC DT stuff from
> >>Rajendra, so I can add as well the MMC DTS for OMAP3 and OMAP4 as
> >>well.
> >>
> >>It is fine for an update?
> >
> >Sure, I'm not planning to pull this until after the merge
> >window.
> 
> OK, so we will not have the DTS support for the new drivers for 3.4 :-(

Well you said this one has driver dependencies :)

> Well, if you pull that in a lo branch, that will be enough to base
> the further work on it.

Right we got something like seven branches ready to go for
early merging after the merge window.. We should have patches
sitting in linux-next for at least a week before the merge
window opens.

> >>Than I can add as Kevin's patch for twl irq_base removal.
> >
> >Hmm I don't follow. That's needed first as a fix for the
> >merge window?
> 
> No, not that one. It is just some more cleanup on top of the one
> Felipe already did in the twl series I've just sent to Samuel.
> But if you do not plan to pull that series for 3.4, that does not
> really matter.

Ah OK. In that case feel free to update. Also check if some
of these can be sent as fixes during the -rc cycle?

Regards,

Tony


From b-cousson at ti.com  Wed Mar 14 19:38:13 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Thu, 15 Mar 2012 00:38:13 +0100
Subject: [GIT PULL] ARM: OMAP: i2c, gpio, spi and regulator DTS updates
In-Reply-To: <20120314232147.GU12083@atomide.com>
References: <4F5E89B4.4010505@ti.com> <4F6120A5.6050407@ti.com>
 <20120314225743.GT12083@atomide.com> <4F6123E4.5090808@ti.com>
 <20120314232147.GU12083@atomide.com>
Message-ID: <4F612BE5.5000603@ti.com>

On 3/15/2012 12:21 AM, Tony Lindgren wrote:
> * Cousson, Benoit<b-cousson at ti.com>  [120314 16:06]:
>> On 3/14/2012 11:57 PM, Tony Lindgren wrote:
>>> * Cousson, Benoit<b-cousson at ti.com>   [120314 15:52]:
>>>> Hi Tony,
>>>>
>>>> It looks like Chris Ball just queued  the HSMMC DT stuff from
>>>> Rajendra, so I can add as well the MMC DTS for OMAP3 and OMAP4 as
>>>> well.
>>>>
>>>> It is fine for an update?
>>>
>>> Sure, I'm not planning to pull this until after the merge
>>> window.
>>
>> OK, so we will not have the DTS support for the new drivers for 3.4 :-(
>
> Well you said this one has driver dependencies :)

Well, this is not a strong dependency, but it is still better to have 
the driver adapted to use the DTS node.

What is really unfair is that I did remove the DTS from the driver 
series to avoid conflict during merge of the various driver series. So 
next time, I guess I'd rather let the DTS along with the driver, but 
this is really a pity.

>> Well, if you pull that in a lo branch, that will be enough to base
>> the further work on it.
>
> Right we got something like seven branches ready to go for
> early merging after the merge window.. We should have patches
> sitting in linux-next for at least a week before the merge
> window opens.

I know that, but since it is just a bunch of DTS, none of them will 
break anything in linux-next anyway...

>>>> Than I can add as Kevin's patch for twl irq_base removal.
>>>
>>> Hmm I don't follow. That's needed first as a fix for the
>>> merge window?
>>
>> No, not that one. It is just some more cleanup on top of the one
>> Felipe already did in the twl series I've just sent to Samuel.
>> But if you do not plan to pull that series for 3.4, that does not
>> really matter.
>
> Ah OK. In that case feel free to update. Also check if some
> of these can be sent as fixes during the -rc cycle?

No, that should be fine, this one can wait 3.5.

Regards,
Benoit


From b-cousson at ti.com  Wed Mar 14 19:39:21 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Thu, 15 Mar 2012 00:39:21 +0100
Subject: [GIT PULL] ARM: OMAP: i2c, gpio, spi, regulator and mmc DTS updates
Message-ID: <4F612C29.40608@ti.com>

Hi Tony,

Here are the remaining DTS patches for 3.4.

On top of the previous pull request, I just added the MMC DTS since the driver adaptation just got queued.

It will be still be good to have that for 3.4 if possible, otherwise we will have a bunch of drivers DT adapted but no DTS file to use them :-(

This series is based on your lo/dt-part2 branch.

Thanks,
Benoit


The following changes since commit 328ae2cb50af2f96b6061eb462aa92966a462bbc:
  Ilya Yanok (1):
        arm/dts: mt_ventoux: very basic support for TeeJet Mt.Ventoux board

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/dts/all

Benoit Cousson (11):
      arm/dts: twl6030: Add DTS file for twl6030 PMIC
      arm/dts: twl4030: Add DTS file for twl4030 PM + Audio IC
      arm/dts: omap4-panda: Add twl6030 and i2c EEPROM
      arm/dts: omap4-sdp: Add twl6030, i2c3 and i2c4 devices
      arm/dts: omap3-beagle: Add twl4030 and i2c EEPROM
      ARM: OMAP2+: board-generic: Remove i2c static init
      arm/dts: OMAP4: Add gpio nodes
      arm/dts: OMAP3: Add gpio nodes
      arm/dts: OMAP4: Add SPI controller nodes
      arm/dts: OMAP3: Add SPI controller nodes
      arm/dts: omap4-sdp: Add ks8851 ethernet SPI device

Rajendra Nayak (3):
      arm/dts: twl: Pass regulator data from dt
      arm/dts: OMAP4: Add mmc controller nodes and board data
      arm/dts: OMAP3: Add mmc controller nodes and board data

 arch/arm/boot/dts/omap3-beagle.dts  |   49 +++++++++++++++
 arch/arm/boot/dts/omap3.dtsi        |  102 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap4-panda.dts   |   56 +++++++++++++++++
 arch/arm/boot/dts/omap4-sdp.dts     |   97 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap4.dtsi        |  117 +++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/twl4030.dtsi      |   39 ++++++++++++
 arch/arm/boot/dts/twl6030.dtsi      |   86 +++++++++++++++++++++++++
 arch/arm/mach-omap2/board-generic.c |   37 +----------
 arch/arm/mach-omap2/devices.c       |    4 +-
 arch/arm/mach-omap2/gpio.c          |    8 ++-
 10 files changed, 557 insertions(+), 38 deletions(-)
 create mode 100644 arch/arm/boot/dts/twl4030.dtsi
 create mode 100644 arch/arm/boot/dts/twl6030.dtsi



From sfr at canb.auug.org.au  Wed Mar 14 19:59:01 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 15 Mar 2012 10:59:01 +1100
Subject: linux-next: build failure after merge of the final tree (arm-soc
 tree related)
Message-ID: <20120315105901.7b10c9f4de9374a613436988@canb.auug.org.au>

Hi all,

After merging the final tree, today's linux-next build (powerpc
allmodconfig) failed like this:

drivers/ata/sata_mv.c:4185:1: error: '__mod_of_device_table' aliased to undefined symbol 'mvsdio_dt_ids'

Caused by commit f1e1e148c5cb ("ARM: kirkwood: sata_mv: add device tree
binding").
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From rmallon at gmail.com  Wed Mar 14 20:13:46 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Thu, 15 Mar 2012 11:13:46 +1100
Subject: [PATCH v4 09/10] pwm: Add PXA support
In-Reply-To: <1331740593-10807-10-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-10-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F61343A.80103@gmail.com>

On 15/03/12 02:56, Thierry Reding wrote:

> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> ---
> Changes in v3:
>   - update PWM ops for changes in patch 2

Couple of quick notes, mostly for future work.

> +	/* NOTE: the clock to PWM has to be enabled first
> +	 * before writing to the registers
> +	 */
> +	clk_enable(pc->clk);


Should be fixed to also call clk_prepare (and clk_unprepare after
clk_disable). Could be done in a follow up patch.

> +	__raw_writel(prescale, pc->mmio_base + offset + PWMCR);
> +	__raw_writel(dc, pc->mmio_base + offset + PWMDCR);
> +	__raw_writel(pv, pc->mmio_base + offset + PWMPCR);


Should we fix this driver to use readl/writel instead of the __raw
variants? The memory is properly ioremaped, and to my understanding the
__raw memory accessors should be avoided outside of core code. This
could be done in a follow up patch if you want to keep this patch as
mostly just a move of the code.

~Ryan


From jason at lakedaemon.net  Wed Mar 14 20:20:20 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 14 Mar 2012 20:20:20 -0400
Subject: linux-next: build failure after merge of the final tree
 (arm-soc tree related)
In-Reply-To: <20120315105901.7b10c9f4de9374a613436988@canb.auug.org.au>
References: <20120315105901.7b10c9f4de9374a613436988@canb.auug.org.au>
Message-ID: <20120315002020.GA16189@titan.lakedaemon.net>

On Thu, Mar 15, 2012 at 10:59:01AM +1100, Stephen Rothwell wrote:
> Hi all,
> 
> After merging the final tree, today's linux-next build (powerpc
> allmodconfig) failed like this:
> 
> drivers/ata/sata_mv.c:4185:1: error: '__mod_of_device_table' aliased to undefined symbol 'mvsdio_dt_ids'
> 
> Caused by commit f1e1e148c5cb ("ARM: kirkwood: sata_mv: add device tree
> binding").

Stephen,

That's my mistake.  I did a pull request for the wrong branch.  Olof,
could you please drop the offending branch and I'll submit a new pull
request once I have a chance to test Arnd's irq patch?

thx,

Jason.


From jg1.han at samsung.com  Wed Mar 14 20:20:26 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Thu, 15 Mar 2012 09:20:26 +0900
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <4F60E5C8.3040804@gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com> <4F60E5C8.3040804@gmail.com>
Message-ID: <001501cd0241$6bb53560$431fa020$%han@samsung.com>

> -----Original Message-----
> From: Darius Augulis [mailto:augulis.darius at gmail.com]
> Sent: Thursday, March 15, 2012 3:39 AM
> To: Jingoo Han
> Cc: 'Thomas Abraham'; linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-
> kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; kgene.kim at samsung.com; ben-
> linux at fluff.org; patches at linaro.org; 'Kyungmin Park'; 'JeongHyeon Kim'; 'Heiko Stuebner'; 'Kwangwoo Lee';
> 'Mark Brown'; 'Peter Korsgaard'; 'Maurus Cuelenaere'
> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> 
> On 03/14/2012 03:51 AM, Jingoo Han wrote:
> >> -----Original Message-----
> >> From: Thomas Abraham [mailto:thomas.abraham at linaro.org]
> >> Sent: Tuesday, March 13, 2012 7:11 PM
> >> To: Jingoo Han
> >> Cc: linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-kernel at lists.infradead.org;
> linux-
> >> samsung-soc at vger.kernel.org; kgene.kim at samsung.com; ben-linux at fluff.org; patches at linaro.org; Kyungmin
> >> Park; JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter Korsgaard; Darius Augulis;
> Maurus
> >> Cuelenaere
> >> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> >>
> >> On 13 March 2012 15:17, Jingoo Han<jg1.han at samsung.com>  wrote:
> >>>> -----Original Message-----
> >>>> From: Thomas Abraham [mailto:thomas.abraham at linaro.org]
> >>>> Sent: Tuesday, March 13, 2012 6:00 AM
> >>>> To: linux-fbdev at vger.kernel.org
> >>>> Cc: FlorianSchandinat at gmx.de; linux-arm-kernel at lists.infradead.org; linux-samsung-
> soc at vger.kernel.org;
> >>>> kgene.kim at samsung.com; jg1.han at samsung.com; ben-linux at fluff.org; patches at linaro.org; Kyungmin Park;
> >>>> JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter Korsgaard; Darius Augulis; Maurus
> >>>> Cuelenaere
> >>>> Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> >>>>
> >>>> For all the Samsung SoC based boards which have the platform data for
> >>>> s3c-fb driver, the 'default_win' element in the platform data is removed
> >>>> and the lcd panel video timing values are moved out of individual window
> >>>> configuration data.
> >>>>
> >>>> Cc: Jingoo Han<jg1.han at samsung.com>
> >>>> Cc: Kyungmin Park<kyungmin.park at samsung.com>
> >>>> Cc: JeongHyeon Kim<jhkim at insignal.co.kr>
> >>>> Cc: Kukjin Kim<kgene.kim at samsung.com>
> >>>> Cc: Heiko Stuebner<heiko at sntech.de>
> >>>> Cc: Ben Dooks<ben-linux at fluff.org>
> >>>> Cc: Kwangwoo Lee<kwangwoo.lee at gmail.com>
> >>>> Cc: Mark Brown<broonie at opensource.wolfsonmicro.com>
> >>>> Cc: Peter Korsgaard<jacmet at sunsite.dk>
> >>>> Cc: Darius Augulis<augulis.darius at gmail.com>
> >>>> Cc: Maurus Cuelenaere<mcuelenaere at gmail.com>
> >>>> Signed-off-by: Thomas Abraham<thomas.abraham at linaro.org>
> >>>> ---
> >>>>   arch/arm/mach-exynos/mach-nuri.c           |   26 ++++++++++-------
> >>>>   arch/arm/mach-exynos/mach-origen.c         |   24 ++++++++++-------
> >>>>   arch/arm/mach-exynos/mach-smdkv310.c       |   28 +++++++++++--------
> >>>>   arch/arm/mach-exynos/mach-universal_c210.c |   26 ++++++++++-------
> >>>>   arch/arm/mach-s3c24xx/mach-smdk2416.c      |   27 ++++++++++--------
> >>>>   arch/arm/mach-s3c64xx/mach-anw6410.c       |   25 ++++++++++-------
> >>>>   arch/arm/mach-s3c64xx/mach-crag6410.c      |   25 ++++++++++-------
> >>>>   arch/arm/mach-s3c64xx/mach-hmt.c           |   24 ++++++++++-------
> >>>>   arch/arm/mach-s3c64xx/mach-mini6410.c      |   40 ++++++++++++---------------
> >>>>   arch/arm/mach-s3c64xx/mach-real6410.c      |   40 ++++++++++++---------------
> >>>>   arch/arm/mach-s3c64xx/mach-smartq5.c       |   26 ++++++++++-------
> >>>>   arch/arm/mach-s3c64xx/mach-smartq7.c       |   26 ++++++++++-------
> >>>>   arch/arm/mach-s3c64xx/mach-smdk6410.c      |   25 ++++++++++-------
> >>>>   arch/arm/mach-s5p64x0/mach-smdk6440.c      |   24 ++++++++++-------
> >>>>   arch/arm/mach-s5p64x0/mach-smdk6450.c      |   24 ++++++++++-------
> >>>>   arch/arm/mach-s5pc100/mach-smdkc100.c      |   27 ++++++++++--------
> >>>>   arch/arm/mach-s5pv210/mach-aquila.c        |   36 +++++++++++--------------
> >>>>   arch/arm/mach-s5pv210/mach-goni.c          |   26 ++++++++++-------
> >>>>   arch/arm/mach-s5pv210/mach-smdkv210.c      |   24 ++++++++++-------
> >>>>   19 files changed, 285 insertions(+), 238 deletions(-)
> >>>>
> >>> [.....]
> >>>
> >>>> diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
> >>>> index c34c2ab..24dcdc9 100644
> >>>> --- a/arch/arm/mach-s3c64xx/mach-mini6410.c
> >>>> +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
> >>>> @@ -153,36 +153,32 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
> >>>>
> >>>>   static struct s3c_fb_pd_win mini6410_fb_win[] = {
> >>>>        {
> >>>> -             .win_mode       = {     /* 4.3" 480x272 */
> >>>> -                     .left_margin    = 3,
> >>>> -                     .right_margin   = 2,
> >>>> -                     .upper_margin   = 1,
> >>>> -                     .lower_margin   = 1,
> >>>> -                     .hsync_len      = 40,
> >>>> -                     .vsync_len      = 1,
> >>>> -                     .xres           = 480,
> >>>> -                     .yres           = 272,
> >>>> -             },
> >>>>                .max_bpp        = 32,
> >>>>                .default_bpp    = 16,
> >>>> +             .xres           = 480,
> >>>> +             .yres           = 272,
> >>>>        }, {
> >>>> -             .win_mode       = {     /* 7.0" 800x480 */
> >>>> -                     .left_margin    = 8,
> >>>> -                     .right_margin   = 13,
> >>>> -                     .upper_margin   = 7,
> >>>> -                     .lower_margin   = 5,
> >>>> -                     .hsync_len      = 3,
> >>>> -                     .vsync_len      = 1,
> >>>> -                     .xres           = 800,
> >>>> -                     .yres           = 480,
> >>>> -             },
> >>>>                .max_bpp        = 32,
> >>>>                .default_bpp    = 16,
> >>>> +             .xres           = 800,
> >>>> +             .yres           = 480,
> >>>>        },
> >>>>   };
> >>>>
> >>>> +static struct fb_videomode mini6410_lcd_timing = {
> >>>> +     .left_margin    = 8,
> >>>> +     .right_margin   = 13,
> >>>> +     .upper_margin   = 7,
> >>>> +     .lower_margin   = 5,
> >>>> +     .hsync_len      = 3,
> >>>> +     .vsync_len      = 1,
> >>>> +     .xres           = 800,
> >>>> +     .yres           = 480,
> >>>> +};
> >>>> +
> >>>>   static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
> >>>>        .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
> >>>> +     .vtiming        =&mini6410_lcd_timing,
> >>>>        .win[0]         =&mini6410_fb_win[0],
> >>>>        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> >>>>        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> >>>> @@ -310,8 +306,8 @@ static void __init mini6410_machine_init(void)
> >>>>        mini6410_lcd_pdata.win[0] =&mini6410_fb_win[features.lcd_index];
> >>>>
> >>>>        printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
> >>>> -             mini6410_lcd_pdata.win[0]->win_mode.xres,
> >>>> -             mini6410_lcd_pdata.win[0]->win_mode.yres);
> >>>> +             mini6410_lcd_pdata.win[0]->xres,
> >>>> +             mini6410_lcd_pdata.win[0]->yres);
> >>>>
> >>>>        s3c_nand_set_platdata(&mini6410_nand_info);
> >>>>        s3c_fb_set_platdata(&mini6410_lcd_pdata);
> >>>> diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
> >>>> index be2a9a2..41e4f74 100644
> >>>> --- a/arch/arm/mach-s3c64xx/mach-real6410.c
> >>>> +++ b/arch/arm/mach-s3c64xx/mach-real6410.c
> >>>> @@ -119,36 +119,32 @@ static struct platform_device real6410_device_eth = {
> >>>>
> >>>>   static struct s3c_fb_pd_win real6410_fb_win[] = {
> >>>>        {
> >>>> -             .win_mode       = {     /* 4.3" 480x272 */
> >>>> -                     .left_margin    = 3,
> >>>> -                     .right_margin   = 2,
> >>>> -                     .upper_margin   = 1,
> >>>> -                     .lower_margin   = 1,
> >>>> -                     .hsync_len      = 40,
> >>>> -                     .vsync_len      = 1,
> >>>> -                     .xres           = 480,
> >>>> -                     .yres           = 272,
> >>>> -             },
> >>>>                .max_bpp        = 32,
> >>>>                .default_bpp    = 16,
> >>>> +             .xres           = 480,
> >>>> +             .yres           = 272,
> >>>>        }, {
> >>>> -             .win_mode       = {     /* 7.0" 800x480 */
> >>>> -                     .left_margin    = 8,
> >>>> -                     .right_margin   = 13,
> >>>> -                     .upper_margin   = 7,
> >>>> -                     .lower_margin   = 5,
> >>>> -                     .hsync_len      = 3,
> >>>> -                     .vsync_len      = 1,
> >>>> -                     .xres           = 800,
> >>>> -                     .yres           = 480,
> >>>> -             },
> >>>>                .max_bpp        = 32,
> >>>>                .default_bpp    = 16,
> >>>> +             .xres           = 800,
> >>>> +             .yres           = 480,
> >>>>        },
> >>>>   };
> >>>>
> >>>> +static struct fb_videomode real6410_lcd_timing = {
> >>>> +     .left_margin    = 3,
> >>>> +     .right_margin   = 2,
> >>>> +     .upper_margin   = 1,
> >>>> +     .lower_margin   = 1,
> >>>> +     .hsync_len      = 40,
> >>>> +     .vsync_len      = 1,
> >>>> +     .xres           = 800,
> >>>> +     .yres           = 480,
> >>>> +};
> >>>
> >>> What is the difference between mini6410_lcd_timing and real6410_lcd_timing?
> >>> In my opinion, it would be good as follows:
> >>>
> >>> +static struct fb_videomode real6410_lcd_timing = {
> >>> +       .left_margin    = 8,
> >>> +       .right_margin   = 13,
> >>> +       .upper_margin   = 7,
> >>> +       .lower_margin   = 5,
> >>> +       .hsync_len      = 3,
> >>> +       .vsync_len      = 1,
> >>> +       .xres           = 800,
> >>> +       .yres           = 480,
> >>> +};
> >>>
> >>>
> >> Before this patch series, both real6410 and mini6410 had 'default_win'
> >> = 0 in the platform data. And, the s3c-fb driver selected the video
> >> timing from the window selected by the default_win parameter in s3c-fb
> >> platform data, i.e window 0 for both mini6440 and real6410. So, in
> >> this patch, while moving the timing values out of window data, the
> >> timing values for window 0 was selected.
> >>
> >> The timing value for window 1 was never used on mini6410 and real6410.
> >> So I would suggest to use timing value of window 0 in this patch.
> > OK, I see.
> > Then, as you mentioned above, the timing value of mini6410 and real6410 should be same.
> > Also, the mini6410 should use the timing value for window 0 as below.
> >
> > Also, this timing value is used for 4.3" 480x272 LCD.
> > So, xres and yres would be 480 and 272, respectively, instead of 800 and 480.
> >
> > The mini6410 seems to use 4.3" 480x272 LCD as default LCD.
> > Please refer to 'http://www.friendlyarm.net/products/mini6410'.
> >
> > Also, real6410 seems to use 4.3" 480x272 LCD as default LCD.
> > http://s3c6410kits.googlecode.com/files/overview_Real6410.pdf
> >
> > Therefore, given this, the timing value of mini6410 and real6410 would be as follows.
> >
> > +static struct fb_videomode mini6410_lcd_timing = {
> > +	.left_margin	= 8,
> > +	.right_margin	= 13,
> > +	.upper_margin	= 7,
> > +	.lower_margin	= 5,
> > +	.hsync_len	= 3,
> > +	.vsync_len	= 1,
> > +	.xres		= 480,
> > +	.yres		= 272,
> > +};
> >
> > +static struct fb_videomode real6410_lcd_timing = {
> > +	.left_margin	= 8,
> > +	.right_margin	= 13,
> > +	.upper_margin	= 7,
> > +	.lower_margin	= 5,
> > +	.hsync_len	= 3,
> > +	.vsync_len	= 1,
> > +	.xres		= 480,
> > +	.yres		= 272,
> > +};
> >
> > Darius Augulis, can you confirm it?
> > (Darius Augulis is a maintainer for real6410 and mini6410 boards.)
> 
> Are you going to leave only single LCD resolution for every of two
> boards? If so, then my answer is no.

Yes, only single LCD resolution will be left.

> I have mini6410 with both 4.3" and 7" LCDs and real6410 with 7" LCD. Now
> we have possibility to choose LCD size dynamically - leave it there.
> What you mean "default" 4.3" size LCD? The 7" size LCD is also provided
> by board sellers - I've bought it.

OK, I see.
Both mini6410 and real6410 provide both 4.3" and 7" LCDs,
so you needs to select both LCDs.

Um, usually, single LCD is provided on the single board.
Also, the daughter board with another kind LCD can be connected to the board.

However, .win_mode is used not for LCD, but for windows of FIMD IP.
Actually, our current framework does not support to choose multi LCD,
so, I understand that you use .win_mode[1] as second LCD.
However, that's not accurate way to select multi LCD.

Thomas, can you consider Augulis's opinion?
I think that the method to select multi LCDs is necessary.

Ideal process is such as:
  1. add the patch to support to select multi LCDs
  2. apply above patch to make the mini6410 and real6410 to select multi LCDs.
  3. apply Thomas's patchset to remove timing value from .win_mode variable.

Best regards,
Jingoo Han

> 
> regards,
> Darius Augulis
> 
> >
> > Best regards,
> > Jingoo Han
> >
> >> Thanks for your comments.
> >>
> >> Regards,
> >> Thomas.
> >



From omar.ramirez at ti.com  Wed Mar 14 20:31:19 2012
From: omar.ramirez at ti.com (Ramirez Luna, Omar)
Date: Wed, 14 Mar 2012 19:31:19 -0500
Subject: [PATCH v2 5/8] ARM: OMAP2+: hwmod: ensure that SYSCONFIG bits are
 reprogrammed after a reset
In-Reply-To: <20120228053657.16278.76132.stgit@dusk>
References: <20120228053524.16278.59430.stgit@dusk>
 <20120228053657.16278.76132.stgit@dusk>
Message-ID: <CAB-zwWhAa3PprwDLzWLkBFUHPeJO3HN3M9mAZF=ohGTvP43jYA@mail.gmail.com>

Hi Paul,

2012/2/27 Paul Walmsley <paul at pwsan.com>:
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index db4ad41..aeb6f4c 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -1490,13 +1490,22 @@ static int _reset(struct omap_hwmod *oh)
> ? ? ? ?pr_debug("omap_hwmod: %s: resetting\n", oh->name);
>
> ? ? ? ?if (oh->class->reset)
> - ? ? ? ? ? ? ? return oh->class->reset(oh);
> -
> - ? ? ? if (!oh->rst_lines_cnt)
> - ? ? ? ? ? ? ? return _ocp_softreset(oh);
> + ? ? ? ? ? ? ? oh->class->reset(oh);
> + ? ? ? else if (!oh->rst_lines_cnt)
> + ? ? ? ? ? ? ? _ocp_softreset(oh);
> + ? ? ? else
> + ? ? ? ? ? ? ? for (i = 0; i < oh->rst_lines_cnt; i++)
> + ? ? ? ? ? ? ? ? ? ? ? _assert_hardreset(oh, oh->rst_lines[i].name);

If we reached here the reset lines will be asserted, and then the code
below touches sysc registers on a module under reset.

This would crash on _setup->_setup_reset->_reset.

Adding a 'return 0' I believe fixes the behavior, boots the board and
leaves the hwmod under reset.

-	else
+	} else {
 		for (i = 0; i < oh->rst_lines_cnt; i++)
 			_assert_hardreset(oh, oh->rst_lines[i].name);
+		return 0;
+	}

>
> - ? ? ? for (i = 0; i < oh->rst_lines_cnt; i++)
> - ? ? ? ? ? ? ? _assert_hardreset(oh, oh->rst_lines[i].name);
> + ? ? ? /*
> + ? ? ? ?* OCP_SYSCONFIG bits need to be reprogrammed after a
> + ? ? ? ?* softreset. ?The _enable() function should be split to avoid
> + ? ? ? ?* the rewrite of the OCP_SYSCONFIG register.
> + ? ? ? ?*/
> + ? ? ? if (oh->class->sysc) {
> + ? ? ? ? ? ? ? _update_sysc_cache(oh);
> + ? ? ? ? ? ? ? _enable_sysc(oh);
> + ? ? ? }

Best Regards,

Omar


From hartleys at visionengravers.com  Wed Mar 14 20:42:31 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 14 Mar 2012 19:42:31 -0500
Subject: [PATCH v4 02/10] pwm: Allow chips to support multiple PWMs.
In-Reply-To: <20120314204935.GB12334@avionic-0098.mockup.avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-3-git-send-email-thierry.reding@avionic-design.de>
 <ADE657CA350FB648AAC2C43247A983F0020695DB57DC@AUSP01VMBX24.collaborationhost.net>
 <20120314204935.GB12334@avionic-0098.mockup.avionic-design.de>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020695DB587C@AUSP01VMBX24.collaborationhost.net>

On Wednesday, March 14, 2012 1:50 PM, Thierry Reding wrote:
> * H Hartley Sweeten wrote:
>> On Wednesday, March 14, 2012 8:56 AM, Thierry Reding wrote:
> [...]
>>> +#ifdef CONFIG_DEBUG_FS
>>> +	void			(*dbg_show)(struct pwm_chip *chip,
>>> +					    struct seq_file *s);
>>> +#endif
>> 
>> This doesn't compile...
>> 
>> include/linux/pwm.h:87: warning: 'struct seq_file' declared inside parameter list
>> include/linux/pwm.h:87: warning: its scope is only this definition or declaration, which is probably not what you want
>
> Okay, pwm.h probably needs a seq_file.h include. Thanks for noticing.

Or just a:

struct seq_file;

Regards,
Hartley


From tony at atomide.com  Wed Mar 14 20:46:38 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 14 Mar 2012 17:46:38 -0700
Subject: [GIT PULL] ARM: OMAP: i2c, gpio, spi, regulator and mmc DTS
 updates
In-Reply-To: <4F612C29.40608@ti.com>
References: <4F612C29.40608@ti.com>
Message-ID: <20120315004638.GW12083@atomide.com>

Hi,

* Cousson, Benoit <b-cousson at ti.com> [120314 16:41]:
> Hi Tony,
> 
> Here are the remaining DTS patches for 3.4.
> 
> On top of the previous pull request, I just added the MMC DTS since the driver adaptation just got queued.
> 
> It will be still be good to have that for 3.4 if possible, otherwise we will have a bunch of drivers DT adapted but no DTS file to use them :-(

This might be doable as a follow-up patch series at the end
of the merge window or at -rc1 when the related driver changes
have been merged.

Arnd and Olof, what do you guys think?

Regards,

Tony

 
> This series is based on your lo/dt-part2 branch.
> 
> Thanks,
> Benoit
> 
> 
> The following changes since commit 328ae2cb50af2f96b6061eb462aa92966a462bbc:
>   Ilya Yanok (1):
>         arm/dts: mt_ventoux: very basic support for TeeJet Mt.Ventoux board
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/dts/all
> 
> Benoit Cousson (11):
>       arm/dts: twl6030: Add DTS file for twl6030 PMIC
>       arm/dts: twl4030: Add DTS file for twl4030 PM + Audio IC
>       arm/dts: omap4-panda: Add twl6030 and i2c EEPROM
>       arm/dts: omap4-sdp: Add twl6030, i2c3 and i2c4 devices
>       arm/dts: omap3-beagle: Add twl4030 and i2c EEPROM
>       ARM: OMAP2+: board-generic: Remove i2c static init
>       arm/dts: OMAP4: Add gpio nodes
>       arm/dts: OMAP3: Add gpio nodes
>       arm/dts: OMAP4: Add SPI controller nodes
>       arm/dts: OMAP3: Add SPI controller nodes
>       arm/dts: omap4-sdp: Add ks8851 ethernet SPI device
> 
> Rajendra Nayak (3):
>       arm/dts: twl: Pass regulator data from dt
>       arm/dts: OMAP4: Add mmc controller nodes and board data
>       arm/dts: OMAP3: Add mmc controller nodes and board data
> 
>  arch/arm/boot/dts/omap3-beagle.dts  |   49 +++++++++++++++
>  arch/arm/boot/dts/omap3.dtsi        |  102 ++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/omap4-panda.dts   |   56 +++++++++++++++++
>  arch/arm/boot/dts/omap4-sdp.dts     |   97 +++++++++++++++++++++++++++++
>  arch/arm/boot/dts/omap4.dtsi        |  117 +++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/twl4030.dtsi      |   39 ++++++++++++
>  arch/arm/boot/dts/twl6030.dtsi      |   86 +++++++++++++++++++++++++
>  arch/arm/mach-omap2/board-generic.c |   37 +----------
>  arch/arm/mach-omap2/devices.c       |    4 +-
>  arch/arm/mach-omap2/gpio.c          |    8 ++-
>  10 files changed, 557 insertions(+), 38 deletions(-)
>  create mode 100644 arch/arm/boot/dts/twl4030.dtsi
>  create mode 100644 arch/arm/boot/dts/twl6030.dtsi
> 


From mturquette at ti.com  Wed Mar 14 20:51:48 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 14 Mar 2012 17:51:48 -0700
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <20120313120507.GS3852@pengutronix.de>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
 <20120311113414.GM3852@pengutronix.de>
 <CAJOA=zMdkLB-DCPOk=kz5mn6BK6A_swocyCHJHeGE6H7FxBbmQ@mail.gmail.com>
 <20120312115117.GN3852@pengutronix.de>
 <CAJOA=zPx0ARsoO4ueSTMe_z2Gs4xG4P2qn1=-vHFf7_k=+K6hQ@mail.gmail.com>
 <20120313120507.GS3852@pengutronix.de>
Message-ID: <CAJOA=zMT4vK7WPF7iEH9kN6GHHAv-LChHoadzieqV-Wd3Qj=WQ@mail.gmail.com>

On Tue, Mar 13, 2012 at 5:05 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Mon, Mar 12, 2012 at 08:16:36PM -0700, Turquette, Mike wrote:
>> On Mon, Mar 12, 2012 at 4:51 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>> > I tried another
>> > approach on the weekend which basically does not try to do all in a
>> > single recursion but instead sets the rate in multiple steps:
>> >
>> > 1) call a function which calculates all new rates of affected clocks
>> > ? in a rate change and safes the value in a clk->new_rate field. This
>> > ? function returns the topmost clock which has to be changed.
>> > 2) starting from the topmost clock notify all clients. This walks the
>> > ? whole subtree even if a notfifier refuses the change. If necessary
>> > ? we can walk the whole subtree again to abort the change.
>> > 3) actually change rates starting from the topmost clocks and notify
>> > ? all clients on the way. I changed the set_rate callback to void.
>> > ? Instead of failing (what is failing in case of set_rate? The clock
>> > ? will still have some rate) I check for the result with
>> > ? clk_ops->recalc_rate.
>
> The way described above works for me now, see this branch:
>
> git://git.pengutronix.de/git/imx/linux-2.6.git v3.3-rc6-clkv6-fixup
>
> You may not necessarily like it as it changes quite a lot in the rate
> changing code.

I tried that code and I really like it!  It is much more readable and
feels less "fragile" than the previous recursive __clk_set_rate.  I
did quite a bit of testing with this code today.  One of the tests
looks like this:

    pll         (adjustable to anything)
     |
clk_divider     (5 bits wide)
     |
   dummy        (no clk_ops)

The new code did a fine job arbitrating rates for the PLL and the
intermediate divider even if I put weird constraints on the PLL.  For
instance if I artificially limited it to a minimum of 600MHz and then
ran clk_set_rate(dummy, 300MHz) it would lock at 600MHz and set
clk_divider to divide-by-2.  Setting to 600MHz or more set the divider
back to 1 and relocked the PLL appropriately.  Pretty cool.

I also tested the notifiers with this code and they seem to function
properly.  I'll take this code in for v7.  Thanks a lot for this
helpful contribution.

I did find that MULT_ROUND_UP caused trouble for my PLL's round_rate
implementation.  Maybe my PLL code is fragile but a quick fix was to
make sure that we send the exact value we want to the round_rate code.
 I also feel this is more correct.  Let me know what you think:

8<---------------------------------------------------------------

commit 189fecedb175d0366759246c4192f45b0bc39a50
Author: Mike Turquette <mturquette at linaro.org>
Date:   Wed Mar 14 17:29:51 2012 -0700

    clk-divider.c: round the actual rate we care about

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 86ca9cd..06ef4a0 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -47,12 +47,6 @@ static unsigned long clk_divider_recalc_rate(struct
clk_hw *hw,
 }
 EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);

-/*
- * The reverse of DIV_ROUND_UP: The maximum number which
- * divided by m is r
- */
-#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
-
 static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
 		unsigned long *best_parent_rate)
 {
@@ -84,9 +78,9 @@ static int clk_divider_bestdiv(struct clk_hw *hw,
unsigned long rate,

 	for (i = 1; i <= maxdiv; i++) {
 		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
-				MULT_ROUND_UP(rate, i));
+				(rate * i));
 		now = parent_rate / i;
-		if (now <= rate && now >= best) {
+		if (now <= rate && now > best) {
 			bestdiv = i;
 			best = now;
 			*best_parent_rate = parent_rate;


From paul.gortmaker at windriver.com  Wed Mar 14 21:53:39 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Wed, 14 Mar 2012 21:53:39 -0400
Subject: linux-next: build failure after merge of the final tree (arm-soc
 tree related)
In-Reply-To: <20120315105901.7b10c9f4de9374a613436988@canb.auug.org.au>
References: <20120315105901.7b10c9f4de9374a613436988@canb.auug.org.au>
Message-ID: <CAP=VYLosYNbhGeUYyLr=0xa1UgK=fL-GOafySixFyQjy4GrdgA@mail.gmail.com>

On Wed, Mar 14, 2012 at 7:59 PM, Stephen Rothwell <sfr at canb.auug.org.au> wrote:
> Hi all,
>
> After merging the final tree, today's linux-next build (powerpc
> allmodconfig) failed like this:
>
> drivers/ata/sata_mv.c:4185:1: error: '__mod_of_device_table' aliased to undefined symbol 'mvsdio_dt_ids'
>
> Caused by commit f1e1e148c5cb ("ARM: kirkwood: sata_mv: add device tree
> binding").

Looks like the same thing I reported in yesterday's triage that was
screwing sparc:

http://www.spinics.net/lists/sparclinux/msg09199.html

Odd that it only started screwing powerpc today though.

Paul.
--

> --
> Cheers,
> Stephen Rothwell ? ? ? ? ? ? ? ? ? ?sfr at canb.auug.org.au


From sfr at canb.auug.org.au  Wed Mar 14 22:05:41 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 15 Mar 2012 13:05:41 +1100
Subject: linux-next: build failure after merge of the final tree
 (arm-soc tree related)
In-Reply-To: <CAP=VYLosYNbhGeUYyLr=0xa1UgK=fL-GOafySixFyQjy4GrdgA@mail.gmail.com>
References: <20120315105901.7b10c9f4de9374a613436988@canb.auug.org.au>
 <CAP=VYLosYNbhGeUYyLr=0xa1UgK=fL-GOafySixFyQjy4GrdgA@mail.gmail.com>
Message-ID: <20120315130541.d0d8c98d132a32dfe369ee19@canb.auug.org.au>

Hi Paul,

On Wed, 14 Mar 2012 21:53:39 -0400 Paul Gortmaker <paul.gortmaker at windriver.com> wrote:
>
> On Wed, Mar 14, 2012 at 7:59 PM, Stephen Rothwell <sfr at canb.auug.org.au> wrote:
> >
> > After merging the final tree, today's linux-next build (powerpc
> > allmodconfig) failed like this:
> >
> > drivers/ata/sata_mv.c:4185:1: error: '__mod_of_device_table' aliased to undefined symbol 'mvsdio_dt_ids'
> >
> > Caused by commit f1e1e148c5cb ("ARM: kirkwood: sata_mv: add device tree
> > binding").
> 
> Looks like the same thing I reported in yesterday's triage that was
> screwing sparc:
> 
> http://www.spinics.net/lists/sparclinux/msg09199.html
> 
> Odd that it only started screwing powerpc today though.

It started affecting PowerPC with next-20120309, but I don't read the
build logs every day :-(

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From sfr at canb.auug.org.au  Wed Mar 14 22:08:49 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 15 Mar 2012 13:08:49 +1100
Subject: linux-next: build failure after merge of the final tree
 (arm-soc tree related)
In-Reply-To: <20120315002020.GA16189@titan.lakedaemon.net>
References: <20120315105901.7b10c9f4de9374a613436988@canb.auug.org.au>
 <20120315002020.GA16189@titan.lakedaemon.net>
Message-ID: <20120315130849.9274a279aed2b10eb90d5c2f@canb.auug.org.au>

Hi all,

On Wed, 14 Mar 2012 20:20:20 -0400 Jason Cooper <jason at lakedaemon.net> wrote:
>
> On Thu, Mar 15, 2012 at 10:59:01AM +1100, Stephen Rothwell wrote:
> > 
> > After merging the final tree, today's linux-next build (powerpc
> > allmodconfig) failed like this:
> > 
> > drivers/ata/sata_mv.c:4185:1: error: '__mod_of_device_table' aliased to undefined symbol 'mvsdio_dt_ids'
> > 
> > Caused by commit f1e1e148c5cb ("ARM: kirkwood: sata_mv: add device tree
> > binding").
> 
> That's my mistake.  I did a pull request for the wrong branch.  Olof,
> could you please drop the offending branch and I'll submit a new pull
> request once I have a chance to test Arnd's irq patch?

I will revert that commit today.

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From aisheng.dong at freescale.com  Wed Mar 14 22:57:09 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Thu, 15 Mar 2012 10:57:09 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <4F60979E.3060704@gmail.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <4F5F5B3F.2000303@gmail.com>
 <20120314062354.GA8494@shlinux2.ap.freescale.net>
 <4F60979E.3060704@gmail.com>
Message-ID: <20120315025707.GA13022@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 09:05:34PM +0800, Rob Herring wrote:
> On 03/14/2012 01:23 AM, Dong Aisheng wrote:
> > On Tue, Mar 13, 2012 at 09:35:43AM -0500, Rob Herring wrote:
> >> On 03/13/2012 03:47 AM, Dong Aisheng wrote:
> >>> From: Dong Aisheng <dong.aisheng at linaro.org>
> >>>
> >>> This patch includes basic dt support which can boot via nfs rootfs.
> >>>
> >>> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> >>> ---
> >>>  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
> >>>  arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
> >>>  arch/arm/boot/dts/imx28.dtsi                  |   88 +++++++++++++++++++++++++
> >>>  arch/arm/mach-mxs/Kconfig                     |    9 +++
> >>>  arch/arm/mach-mxs/Makefile                    |    1 +
> >>>  arch/arm/mach-mxs/imx28-dt.c                  |   67 +++++++++++++++++++
> >>>  6 files changed, 200 insertions(+), 0 deletions(-)
> > ....
> >>> +				interrupts = <47>;
> >>> +			};
> >>> +		};
> >>> +	};
> >>> +
> >>> +	ahb at 80080000 {
> >>> +		compatible = "simple-bus";
> >>> +		#address-cells = <1>;
> >>> +		#size-cells = <1>;
> >>> +		reg = <0x80080000 0x80000>;
> >>> +		ranges;
> >>> +
> >>> +		fec at 800f0000 {
> >>> +			compatible = "fsl,imx28-fec";
> >>> +			reg = <0x800f0000 0x4000>;
> >>
> >> This too IIRC.
> >>
> > The size is 16KB/0x4000 in iMX28 spec. :)
> 
> Yes, but the module only uses <4KB. You waste virtual memory space by
> mapping all the unused area. It's not really an issue when you have
> <512MB of RAM, but does become an issue.
> 
Yes, it seems an issue of spec.
And all other places are using the same size.
The simplest way now may be just keep align with spec first.

> >>> +			interrupts = <101>;
> >>> +			status = "disabled";
> >>> +		};
> >>> +
> >>> +		fec at 800f4000 {
> >>> +			compatible = "fsl,imx28-fec";
> >>> +			reg = <0x800f4000 0x4000>;
> >>> +			interrupts = <102>;
> >>> +			status = "disabled";
> >>> +		};
> >>> +
> >>> +	};
> >>> +};
> >>> diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
> >>> index c57f996..6ab66af 100644
> >>> --- a/arch/arm/mach-mxs/Kconfig
> >>> +++ b/arch/arm/mach-mxs/Kconfig
> >>> @@ -17,6 +17,15 @@ config SOC_IMX28
> >>>  
> >>>  comment "MXS platforms:"
> >>>  
> >>> +config MACH_IMX28_DT
> >>
> >> Perhaps this should be more generic like MACH_MXS_DT to eventually
> >> support MX23 as well?
> >>
> > I just did like the imx ways.
> > But yes if we see the need when do imx23 dt support.
> > 
> >>> +	bool "Support i.MX28 platforms from device tree"
> >>> +	select SOC_IMX28
> >>> +	select USE_OF
> >>> +	select MACH_MX28EVK
> >>
> >> This should not be selected here.
> >>
> > Like other imx soc dt board files, the imx28-dt.c may need to use some bits
> > like pinmux in mx28evk.c board file.
> > 
> > Yes, currently i can remove it since it is using uboot pinmux setting.
> > But when add other devices support which is not covered in u-boot like flexcan,
> > i may need to use non-dt board's pinmux setting.
> > So maybe we can keep it first and remove it when totally not dependent
> > on non-dt files.
> 
> Okay either way, but my vote would be add it as needed.
> 
Your vote is ok to me.

> >>> + * The code contained herein is licensed under the GNU General Public
> >>> + * License. You may obtain a copy of the GNU General Public License
> >>> + * Version 2 or later at the following locations:
> >>> + *
> >>> + * http://www.opensource.org/licenses/gpl-license.html
> >>> + * http://www.gnu.org/copyleft/gpl.html
> >>> + */
> >>> +
> >>> +#include <linux/init.h>
> >>> +#include <linux/irqdomain.h>
> >>> +#include <linux/of_irq.h>
> >>> +#include <linux/of_platform.h>
> >>> +#include <asm/mach/arch.h>
> >>> +#include <asm/mach/time.h>
> >>> +#include <mach/common.h>
> >>> +#include <mach/mx28.h>
> >>> +
> >>> +static const struct of_dev_auxdata imx28_auxdata_lookup[] __initconst = {
> >>> +	OF_DEV_AUXDATA("arm,pl011", MX28_DUART_BASE_ADDR, "duart", NULL),
> >>> +	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC0_BASE_ADDR, "imx28-fec.0", NULL),
> >>> +	OF_DEV_AUXDATA("fsl,imx28-fec", MX28_ENET_MAC1_BASE_ADDR, "imx28-fec.1", NULL),
> >>
> >> Why do you need the old names?
> >>
> > To keep align with the old clocks.
> > See arch/arm/mach-mxs/clock-mx28.c:
> > _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
> > _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
> > Is there any better way to avoid this?
> 
> Yes, you can add more clock look-ups with the DT name.
> 
Got it.

Regards
Dong Aisheng



From aisheng.dong at freescale.com  Wed Mar 14 23:02:07 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Thu, 15 Mar 2012 11:02:07 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120314141643.GP3852@pengutronix.de>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
Message-ID: <20120315030206.GB13022@shlinux2.ap.freescale.net>

On Wed, Mar 14, 2012 at 10:16:43PM +0800, s.hauer at pengutronix.de wrote:
> On Wed, Mar 14, 2012 at 08:45:23PM +0800, Dong Aisheng wrote:
> > On Wed, Mar 14, 2012 at 01:23:51AM +0800, Grant Likely wrote:
> > > On Tue, 13 Mar 2012 16:47:04 +0800, Dong Aisheng <b29396 at freescale.com> wrote:
> > > > From: Dong Aisheng <dong.aisheng at linaro.org>
> > > > 
> > > > This patch includes basic dt support which can boot via nfs rootfs.
> > > > 
> > > > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > > > ---
> > > >  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
> > > >  arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
> > > >  arch/arm/boot/dts/imx28.dtsi                  |   88 +++++++++++++++++++++++++
> > > >  arch/arm/mach-mxs/Kconfig                     |    9 +++
> > > >  arch/arm/mach-mxs/Makefile                    |    1 +
> > > >  arch/arm/mach-mxs/imx28-dt.c                  |   67 +++++++++++++++++++
> > > >  6 files changed, 200 insertions(+), 0 deletions(-)
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> > > > index 54bddda..9f21faf 100644
> > > > --- a/Documentation/devicetree/bindings/arm/fsl.txt
> > > > +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> > > > @@ -1,6 +1,10 @@
> > > >  Freescale i.MX Platforms Device Tree Bindings
> > > >  -----------------------------------------------
> > > >  
> > > > +i.MX28 Evaluation Kit
> > > > +Required root node properties:
> > > > +    - compatible = "fsl,imx28-evk", "fsl,imx28";
> > > > +
> > > >  i.MX51 Babbage Board
> > > >  Required root node properties:
> > > >      - compatible = "fsl,imx51-babbage", "fsl,imx51";
> > > > diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
> > > > new file mode 100644
> > > > index 0000000..9758dc4
> > > > --- /dev/null
> > > > +++ b/arch/arm/boot/dts/imx28-evk.dts
> > > > @@ -0,0 +1,31 @@
> > > > +/*
> > > > + * Copyright 2012 Freescale Semiconductor, Inc.
> > > > + *
> > > > + * The code contained herein is licensed under the GNU General Public
> > > > + * License. You may obtain a copy of the GNU General Public License
> > > > + * Version 2 or later at the following locations:
> > > > + *
> > > > + * http://www.opensource.org/licenses/gpl-license.html
> > > > + * http://www.gnu.org/copyleft/gpl.html
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +/include/ "imx28.dtsi"
> > > > +
> > > > +/ {
> > > > +	model = "Freescale i.MX28 Evaluation Kit";
> > > > +	compatible = "fsl,imx28-evk", "fsl,imx28";
> > > > +
> > > > +	memory {
> > > > +		device_type = "memory";
> > > > +		reg = <0x40000000 0x08000000>;
> > > > +	};
> > > > +
> > > > +	ahb at 80080000 {
> > > > +		fec at 800f0000 {
> > > > +			phy-mode = "rmii";
> > > > +			local-mac-address = [00 04 9F 01 7D 5B];
> > > 
> > > Generally a bad idea to put a specific mac address into the device tree.
> > > Better to fill it with zeros.  Otherwise all the dev boards will end up using
> > > the same value.
> > > 
> > Yes, this issue also exists on other platfroms like mx6q.
> > One way is to dynamically get mac address by reading otp register as non-dt does
> > like:
> > static int __init mx28evk_fec_get_mac(void)
> > {
> >         int i;
> >         u32 val;
> >         const u32 *ocotp = mxs_get_ocotp();
> > 
> >         if (!ocotp)
> >                 return -ETIMEDOUT;
> > 
> >         /*
> >          * OCOTP only stores the last 4 octets for each mac address,
> >          * so hard-code Freescale OUI (00:04:9f) here.
> >          */
> >         for (i = 0; i < 2; i++) {
> >                 val = ocotp[i];
> >                 mx28_fec_pdata[i].mac[0] = 0x00;
> >                 mx28_fec_pdata[i].mac[1] = 0x04;
> >                 mx28_fec_pdata[i].mac[2] = 0x9f;
> >                 mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
> >                 mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
> >                 mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
> >         }
> > 
> >         return 0;
> > }
> > 
> > But it seems this needs pass mac address to fec driver via platforom data which is
> > not friendly to dt.
> > 
> > Another way may be changing fec driver to get the fixed part of mac address(first
> > two bytes) from device tree and read the left dynamical part from otp which i'm not
> > sure is better enough.
> > 
> > BTW, filling with zeros seems not work since it's invalid mac address.
> 
> Yes, that's the idea of using this value...
> 
But comparing to use an invalid value, why not just do not define that
local-mac-address property?

Regards
Dong Aisheng



From aisheng.dong at freescale.com  Wed Mar 14 23:05:09 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Thu, 15 Mar 2012 11:05:09 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120314194123.GR26642@pengutronix.de>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120314194123.GR26642@pengutronix.de>
Message-ID: <20120315030508.GC13022@shlinux2.ap.freescale.net>

On Thu, Mar 15, 2012 at 03:41:23AM +0800, Sascha Hauer wrote:
> On Tue, Mar 13, 2012 at 04:47:04PM +0800, Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > This patch includes basic dt support which can boot via nfs rootfs.
> > 
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > ---
> >  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
> >  arch/arm/boot/dts/imx28-evk.dts               |   31 +++++++++
> >  arch/arm/boot/dts/imx28.dtsi                  |   88 +++++++++++++++++++++++++
> >  arch/arm/mach-mxs/Kconfig                     |    9 +++
> >  arch/arm/mach-mxs/Makefile                    |    1 +
> >  arch/arm/mach-mxs/imx28-dt.c                  |   67 +++++++++++++++++++
> >  6 files changed, 200 insertions(+), 0 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> > index 54bddda..9f21faf 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.txt
> > +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> > @@ -1,6 +1,10 @@
> 
> > +
> > +static const char *imx28_dt_compat[] __initdata = {
> > +	"fsl,imx28-evk",
> > +	NULL,
> > +};
> > +
> 
> I suggest to add a generic "fsl,imx28" entry here. It helps people to
> start an unpatched kernel on their boards.
> 
Good point.
Thanks for reminder.

Regards
Dong Aisheng



From bryan.wu at canonical.com  Thu Mar 15 01:08:49 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Thu, 15 Mar 2012 13:08:49 +0800
Subject: [PATCH 3/3] led-triggers: create a trigger for CPU activity
In-Reply-To: <20120313161138.cbeb594d.akpm@linux-foundation.org>
References: <1331197863-25564-1-git-send-email-bryan.wu@canonical.com>
 <1331197863-25564-3-git-send-email-bryan.wu@canonical.com>
 <20120313161138.cbeb594d.akpm@linux-foundation.org>
Message-ID: <CAK5ve-+MuYbjnFmff8z5axQ-vrJn6ZbCOE_ZYyoWmkJwwAbhig@mail.gmail.com>

On Wed, Mar 14, 2012 at 7:11 AM, Andrew Morton
<akpm at linux-foundation.org> wrote:
> On Thu, ?8 Mar 2012 17:11:03 +0800
> Bryan Wu <bryan.wu at canonical.com> wrote:
>
>> Attempting to consolidate the ARM LED code, this removes the
>> custom RealView LED trigger code to turn LEDs on and off in
>> response to CPU activity and replace it with a standard trigger.
>>
>> (bryan.wu at canonical.com:
>> It moves arch/arm/kernel/leds.c syscore stubs into this trigger.
>> It also provides ledtrig_cpu trigger event stub in <linux/leds.h>.
>> Although it was inspired by ARM work, it can be used in other arch.)
>
> The patch doesn't "remove" or "move" anything. ?It wholly consists of
> additions. ?Confused.
>

I'm working on rebase my previous ARM leds consolidation patches to
the linux-next. So this patch will come with those patches soon.
Thanks for pointing out this.

>> Cc: Richard Purdie <rpurdie at rpsys.net>
>> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
>> Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
>>
>> Reviewed-by: Jamie Iles <jamie at jamieiles.com>
>> Tested-by: Jochen Friedrich <jochen at scram.de>
>
> The authorship is a bit unclear. ?You're the primary author, yes?
>

My work is based on Linus Walleij's patch, so I keep his signed off
here. Basically I rewrote most of things.

>> --- /dev/null
>> +++ b/drivers/leds/ledtrig-cpu.c
>> @@ -0,0 +1,119 @@
>> +/*
>> + * ledtrig-cpu.c - LED trigger based on CPU activity
>> + *
>> + * Copyright 2011 Linus Walleij <linus.walleij at linaro.org>
>> + * Copyright 2011 Bryan Wu <bryan.wu at canonical.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/kernel.h>
>> +#include <linux/init.h>
>> +#include <linux/slab.h>
>> +#include <linux/percpu.h>
>> +#include <linux/syscore_ops.h>
>> +#include "leds.h"
>> +
>> +static DEFINE_PER_CPU(struct led_trigger *, cpu_trig);
>> +static DEFINE_PER_CPU(char [8], trig_name);
>> +
>> +void ledtrig_cpu(enum cpu_led_event ledevt)
>> +{
>> + ? ? struct led_trigger *trig = __get_cpu_var(cpu_trig);
>> +
>> + ? ? if (!trig)
>> + ? ? ? ? ? ? return;
>> +
>> + ? ? /* Locate the correct CPU LED */
>> + ? ? switch (ledevt) {
>> + ? ? case CPU_LED_IDLE_END:
>> + ? ? case CPU_LED_START:
>> + ? ? ? ? ? ? /* Will turn the LED on, max brightness */
>> + ? ? ? ? ? ? led_trigger_event(trig, LED_FULL);
>> + ? ? ? ? ? ? break;
>> +
>> + ? ? case CPU_LED_IDLE_START:
>> + ? ? case CPU_LED_STOP:
>> + ? ? case CPU_LED_HALTED:
>> + ? ? ? ? ? ? /* Will turn the LED off */
>> + ? ? ? ? ? ? led_trigger_event(trig, LED_OFF);
>> + ? ? ? ? ? ? break;
>> +
>> + ? ? default:
>> + ? ? ? ? ? ? /* Will leave the LED as it is */
>> + ? ? ? ? ? ? break;
>> + ? ? }
>> +}
>> +EXPORT_SYMBOL(ledtrig_cpu);
>
> This is a global, exported-to-modules API function. ?It should be
> documented.
>
> It should especially be documented if it has tricky unobvious calling
> conditions, as this function does. ?AFAICT it must be called by code
> which is running on the target CPU and which is pinned to that CPU via
> either preempt_disable() or set_cpus_allowed().
>
> Or something else - I don't have a clue, and the author didn't tell me :(
>

OK, I will sort out the documents about this API.

>> +static int ledtrig_cpu_syscore_suspend(void)
>> +{
>> + ? ? ledtrig_cpu(CPU_LED_STOP);
>> + ? ? return 0;
>> +}
>> +
>> +static void ledtrig_cpu_syscore_resume(void)
>> +{
>> + ? ? ledtrig_cpu(CPU_LED_START);
>> +}
>> +
>> +static void ledtrig_cpu_syscore_shutdown(void)
>> +{
>> + ? ? ledtrig_cpu(CPU_LED_HALTED);
>> +}
>> +
>> +static struct syscore_ops ledtrig_cpu_syscore_ops = {
>> + ? ? .shutdown ? ? ? = ledtrig_cpu_syscore_shutdown,
>> + ? ? .suspend ? ? ? ?= ledtrig_cpu_syscore_suspend,
>> + ? ? .resume ? ? ? ? = ledtrig_cpu_syscore_resume,
>> +};
>> +
>> +static void __init ledtrig_cpu_register(void *info)
>> +{
>> + ? ? int cpuid = smp_processor_id();
>> + ? ? struct led_trigger *trig;
>> + ? ? char *name = __get_cpu_var(trig_name);
>> +
>> + ? ? snprintf(name, 8, "cpu%d", cpuid);
>
> This explodes at 10,000 CPUS ;)
>

I think it's enough for a while -:). or need I use snprintf(name,
4+NR_CPUS, "cpu%d", cpuid);

>> + ? ? led_trigger_register_simple(name, &trig);
>> +
>> + ? ? pr_info("LED trigger %s indicate activity on CPU %d\n",
>> + ? ? ? ? ? ? trig->name, cpuid);
>> +
>> + ? ? __get_cpu_var(cpu_trig) = trig;
>> +}
>> +
>> +static void __exit ledtrig_cpu_unregister(void *info)
>> +{
>> + ? ? struct led_trigger *trig = __get_cpu_var(cpu_trig);
>> + ? ? char *name = __get_cpu_var(trig_name);
>> +
>> + ? ? led_trigger_unregister_simple(trig);
>> + ? ? __get_cpu_var(cpu_trig) = NULL;
>> + ? ? memset(name, 0, 8);
>> +}
>> +
>> +static int __init ledtrig_cpu_init(void)
>> +{
>> + ? ? on_each_cpu(ledtrig_cpu_register, NULL, 1);
>
> on_each_cpu() only calls the function on presently-onlined CPUs. ?How
> does this code interact with CPU hotplug?
>
> And as you've already noted, led_trigger_register_simple() is totally
> not callable from interrupt context. ?And we're not just talking about
> under local_irq_disable() here: on_each_cpu() will raise cross-cpu hard
> interrupts to call the function on remote CPUs. ?We end up trying to do
> down_write() and who knows what else from within a hard interrupt
> handler.
>

Right, I will change that to for_each_cpu() and resubmmit the patch.

>> --- a/include/linux/leds.h
>> +++ b/include/linux/leds.h
>> @@ -210,4 +210,19 @@ struct gpio_led_platform_data {
>> ?struct platform_device *gpio_led_register_device(
>> ? ? ? ? ? ? ? int id, const struct gpio_led_platform_data *pdata);
>>
>> +#if defined(CONFIG_LEDS_TRIGGER_CPU) || defined(CONFIG_LEDS_TRIGGER_CPU_MODULE)
>> +enum cpu_led_event {
>> + ? ? CPU_LED_IDLE_START, ? ? /* CPU enters idle */
>> + ? ? CPU_LED_IDLE_END, ? ? ? /* CPU idle ends */
>> + ? ? CPU_LED_START, ? ? ? ? ?/* Machine starts, especially resume */
>> + ? ? CPU_LED_STOP, ? ? ? ? ? /* Machine stops, especially suspend */
>> + ? ? CPU_LED_HALTED, ? ? ? ? /* Machine shutdown */
>> +};
>> +
>> +/* Use this routine to handle LEDs */
>> +extern void ledtrig_cpu(enum cpu_led_event evt);
>> +#else
>> +#define ledtrig_cpu(evt) do {} while (0)
>> +#endif
>
> a) the stub function should be written in C, not CPP please
>

Actually, I'm only familiar with C and forget to write CPP for a
while. is this looks like CPP?

> b) it makes no sense to provide the stub function when the
> ? definition of its argument type (enum cpu_led_event) is not
> ? also available.
>

OK, l will move out the enum cpu_led_event out of this ifdef.

Thanks,
-- 
Bryan Wu <bryan.wu at canonical.com>
Kernel Developer ? ?+86.138-1617-6545 Mobile
Canonical Ltd. ? ? ?www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com


From paul at pwsan.com  Thu Mar 15 02:25:58 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 15 Mar 2012 00:25:58 -0600 (MDT)
Subject: [PATCH v2 5/8] ARM: OMAP2+: hwmod: ensure that SYSCONFIG bits
 are reprogrammed after a reset
In-Reply-To: <CAB-zwWhAa3PprwDLzWLkBFUHPeJO3HN3M9mAZF=ohGTvP43jYA@mail.gmail.com>
References: <20120228053524.16278.59430.stgit@dusk>
 <20120228053657.16278.76132.stgit@dusk>
 <CAB-zwWhAa3PprwDLzWLkBFUHPeJO3HN3M9mAZF=ohGTvP43jYA@mail.gmail.com>
Message-ID: <alpine.DEB.2.00.1203150024260.7269@utopia.booyaka.com>

Hola Omar,

On Wed, 14 Mar 2012, Ramirez Luna, Omar wrote:

> If we reached here the reset lines will be asserted, and then the code
> below touches sysc registers on a module under reset.

Do you know of any case where this would be a problem?  Seems like it 
would only affect IP blocks that have both hard reset lines and SYSCONFIG 
registers, and as far as I know, we don't have any of those defined?


- Paul


From thierry.reding at avionic-design.de  Thu Mar 15 02:41:24 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 15 Mar 2012 07:41:24 +0100
Subject: [PATCH v4 00/10] Add PWM framework and device tree support.
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F0020695DB5858@AUSP01VMBX24.collaborationhost.net>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <ADE657CA350FB648AAC2C43247A983F0020695DB5858@AUSP01VMBX24.collaborationhost.net>
Message-ID: <20120315064124.GA20502@avionic-0098.mockup.avionic-design.de>

* H Hartley Sweeten wrote:
> Are you planning on adding a sysfs interface for generic userspace access
> to the PWM devices?

I wasn't planning to, but really only because I have no need for it. You
could of course add one yourself.

> Anyway, I would be happy to convert the current driver to the new framework
> and get it out of drivers/misc and into a proper location. But, before I can do
> that, I need to be able to control the PWM from userspace somehow.

You should probably coordinate with Sascha Hauer who I think already has most
(if not all) of the PWM drivers converted to his first version of the
framework and said he was going to rebase them on top of this series.

> Maybe an interface similar to the one gpiolib provides with CONFIG_GPIO_SYSFS?

I think the most challenging part will be figuring out how to export PWM
devices via sysfs on a per-chip basis. Since the goal of the series is to
eventually get rid of the global namespace, using an export file like gpiolib
won't work in the long run. Perhaps something like the following would:

	/sys/class/pwm/
		pwmchipX/
			export
			unexport
			pwmY/
				label
				duty
				period

That way you get a reference to the device associated with a PWM chip and you
can use the new pwm_request_from_device() function to request and export the
PWM device.

Again, I have no direct use for this and you probably know the requirements
better than me so it's probably better if you add the interface. I'm happy to
review patches, though.

Thierry
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From sfr at canb.auug.org.au  Thu Mar 15 02:50:00 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 15 Mar 2012 17:50:00 +1100
Subject: linux-next: manual merge of the arm-soc tree with Linus' tree
Message-ID: <20120315175000.897f1172c296d4a687be0537@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-shmobile/board-mackerel.c between commit 1740d3448012
("ARM: mach-shmobile: mackerel: Reserve DMA memory for the frame buffer")
from Linus' tree and commit 5d7220ec000f ("ARM: mach-shmobile: sh7372
map_io and init_early update") from the arm-soc tree.

The latter moved the code to another file
arch/arm/mach-shmobile/setup-sh7372.c and I have no idea how to fix this
up, so I just removed the change done by the former.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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From sfr at canb.auug.org.au  Thu Mar 15 02:56:28 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 15 Mar 2012 17:56:28 +1100
Subject: linux-next: manual merge of the arm-soc tree with the arm tree
Message-ID: <20120315175628.ca8afd4482712e1043212416@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-shmobile/setup-r8a7740.c between commit 250a27237e0e ("ARM:
shmobile: remove NR_IRQS") from the arm tree and commit d3ab7221489f
("ARM: mach-shmobile: r8a7740 map_io and init_early update") from the
arm-soc tree.

Just context changes.  I fixed it up (see below) and can carry the fix as
necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-shmobile/setup-r8a7740.c
index fa15d81,74e5234..0000000
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@@ -25,9 -25,41 +25,42 @@@
  #include <linux/serial_sci.h>
  #include <linux/sh_timer.h>
  #include <mach/r8a7740.h>
 +#include <mach/irqs.h>
+ #include <mach/common.h>
  #include <asm/mach-types.h>
+ #include <asm/mach/map.h>
  #include <asm/mach/arch.h>
+ #include <asm/mach/time.h>
+ 
+ static struct map_desc r8a7740_io_desc[] __initdata = {
+ 	 /*
+ 	  * for CPGA/INTC/PFC
+ 	  * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
+ 	  */
+ 	{
+ 		.virtual	= 0xe6000000,
+ 		.pfn		= __phys_to_pfn(0xe6000000),
+ 		.length		= 160 << 20,
+ 		.type		= MT_DEVICE_NONSHARED
+ 	},
+ #ifdef CONFIG_CACHE_L2X0
+ 	/*
+ 	 * for l2x0_init()
+ 	 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
+ 	 */
+ 	{
+ 		.virtual	= 0xf0002000,
+ 		.pfn		= __phys_to_pfn(0xf0100000),
+ 		.length		= PAGE_SIZE,
+ 		.type		= MT_DEVICE_NONSHARED
+ 	},
+ #endif
+ };
+ 
+ void __init r8a7740_map_io(void)
+ {
+ 	iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
+ }
  
  /* SCIFA0 */
  static struct plat_sci_port scif0_platform_data = {
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From thierry.reding at avionic-design.de  Thu Mar 15 02:56:31 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 15 Mar 2012 07:56:31 +0100
Subject: [PATCH v4 09/10] pwm: Add PXA support
In-Reply-To: <4F61343A.80103@gmail.com>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-10-git-send-email-thierry.reding@avionic-design.de>
 <4F61343A.80103@gmail.com>
Message-ID: <20120315065631.GB20502@avionic-0098.mockup.avionic-design.de>

* Ryan Mallon wrote:
> On 15/03/12 02:56, Thierry Reding wrote:
> 
> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> > ---
> > Changes in v3:
> >   - update PWM ops for changes in patch 2
> 
> Couple of quick notes, mostly for future work.
> 
> > +	/* NOTE: the clock to PWM has to be enabled first
> > +	 * before writing to the registers
> > +	 */
> > +	clk_enable(pc->clk);
> 
> 
> Should be fixed to also call clk_prepare (and clk_unprepare after
> clk_disable). Could be done in a follow up patch.
> 
> > +	__raw_writel(prescale, pc->mmio_base + offset + PWMCR);
> > +	__raw_writel(dc, pc->mmio_base + offset + PWMDCR);
> > +	__raw_writel(pv, pc->mmio_base + offset + PWMPCR);
> 
> 
> Should we fix this driver to use readl/writel instead of the __raw
> variants? The memory is properly ioremaped, and to my understanding the
> __raw memory accessors should be avoided outside of core code. This
> could be done in a follow up patch if you want to keep this patch as
> mostly just a move of the code.

Actually I wasn't planning on keeping this patch at all. Sascha already has
the existing PWM providers converted to his original framework and offered to
rebase them onto this series once the dust settles. I only used them as
testbed to see how the driver interface works out for different hardware. But
I also think that if Sascha hasn't cleaned the driver up yet it should either
be done in his conversion patches or as follow ups.

Sascha: how do you plan on going forward with this? It seems like the driver
interface is pretty much done now and I expect the next round to be the last,
unless I forget to properly work through the TODO list again. If you are busy
with other stuff I can probably find some time to help with porting your
converted drivers.

I'm also wondering which tree this will go in through. Does it make sense to
have an extra tree just for the PWM framework or can it go in via some other
general purpose tree? Who do I need to prod?

Thierry
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From LW at KARO-electronics.de  Thu Mar 15 02:53:29 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Thu, 15 Mar 2012 07:53:29 +0100
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120315030206.GB13022@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
Message-ID: <20321.37353.63115.664975@ipc1.ka-ro>

Hi,

Dong Aisheng writes:
> On Wed, Mar 14, 2012 at 10:16:43PM +0800, s.hauer at pengutronix.de wrote:
> > On Wed, Mar 14, 2012 at 08:45:23PM +0800, Dong Aisheng wrote:
> > > On Wed, Mar 14, 2012 at 01:23:51AM +0800, Grant Likely wrote:
[...]
> > > But it seems this needs pass mac address to fec driver via platforom data which is
> > > not friendly to dt.
> > > 
> > > Another way may be changing fec driver to get the fixed part of mac address(first
> > > two bytes) from device tree and read the left dynamical part from otp which i'm not
> > > sure is better enough.
> > > 
> > > BTW, filling with zeros seems not work since it's invalid mac address.
> > 
> > Yes, that's the idea of using this value...
> > 
> But comparing to use an invalid value, why not just do not define that
> local-mac-address property?
> 
Because a MAC address is by definition a GLOBALLY UNIQUE IDENTIFIER
which is contrary to coding a "valid" default value for it somewhere!
The owner of a certain MAC address range (OUI) is responsible for
ensuring the uniqueness. Thus only they may assign a specific MAC
address to a specific device.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From sfr at canb.auug.org.au  Thu Mar 15 03:06:23 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 15 Mar 2012 18:06:23 +1100
Subject: linux-next: manual merge of the arm-soc tree with the arm tree
Message-ID: <20120315180623.ba48c5a9765ac8e4a0a17c41@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-shmobile/setup-sh7367.c between commit 250a27237e0e ("ARM:
shmobile: remove NR_IRQS") from the arm tree and commit 237caf9e6b0c
("ARM: mach-shmobile: sh7367 map_io and init_early update") from the
arm-soc tree.

Just context changes.  I fixed it up (see below) and can carry the fix as
necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-shmobile/setup-sh7367.c
index 8e848198,a51e1a1..0000000
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@@ -29,9 -29,28 +29,29 @@@
  #include <linux/serial_sci.h>
  #include <linux/sh_timer.h>
  #include <mach/hardware.h>
 +#include <mach/irqs.h>
+ #include <mach/common.h>
  #include <asm/mach-types.h>
  #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+ #include <asm/mach/time.h>
+ 
+ static struct map_desc sh7367_io_desc[] __initdata = {
+ 	/* create a 1:1 entity map for 0xe6xxxxxx
+ 	 * used by CPGA, INTC and PFC.
+ 	 */
+ 	{
+ 		.virtual	= 0xe6000000,
+ 		.pfn		= __phys_to_pfn(0xe6000000),
+ 		.length		= 256 << 20,
+ 		.type		= MT_DEVICE_NONSHARED
+ 	},
+ };
+ 
+ void __init sh7367_map_io(void)
+ {
+ 	iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
+ }
  
  /* SCIFA0 */
  static struct plat_sci_port scif0_platform_data = {
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From sfr at canb.auug.org.au  Thu Mar 15 03:06:30 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 15 Mar 2012 18:06:30 +1100
Subject: linux-next: manual merge of the arm-soc tree with the arm tree
Message-ID: <20120315180630.61dab9c2b41da3b823c9ac94@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-shmobile/setup-sh7377.c between commit 250a27237e0e ("ARM:
shmobile: remove NR_IRQS") from the arm tree and commit bfc46f3ef838
("ARM: mach-shmobile: sh7377 map_io and init_early update") from the
arm-soc tree.

Just context changes.  I fixed it up (see below) and can carry the fix as
necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-shmobile/setup-sh7377.c
index 747ed8e,9f14609..0000000
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@@ -30,9 -30,28 +30,29 @@@
  #include <linux/sh_intc.h>
  #include <linux/sh_timer.h>
  #include <mach/hardware.h>
 +#include <mach/irqs.h>
+ #include <mach/common.h>
+ #include <asm/mach/map.h>
  #include <asm/mach-types.h>
  #include <asm/mach/arch.h>
+ #include <asm/mach/time.h>
+ 
+ static struct map_desc sh7377_io_desc[] __initdata = {
+ 	/* create a 1:1 entity map for 0xe6xxxxxx
+ 	 * used by CPGA, INTC and PFC.
+ 	 */
+ 	{
+ 		.virtual	= 0xe6000000,
+ 		.pfn		= __phys_to_pfn(0xe6000000),
+ 		.length		= 256 << 20,
+ 		.type		= MT_DEVICE_NONSHARED
+ 	},
+ };
+ 
+ void __init sh7377_map_io(void)
+ {
+ 	iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc));
+ }
  
  /* SCIFA0 */
  static struct plat_sci_port scif0_platform_data = {
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From sfr at canb.auug.org.au  Thu Mar 15 03:17:18 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 15 Mar 2012 18:17:18 +1100
Subject: Conflict between Versatile Express DT conversion and local
 timer updates
In-Reply-To: <4F605A3B.5030800@arm.com>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <201203131155.16454.arnd@arndb.de> <4F5F52A2.3050005@arm.com>
 <201203131433.07214.arnd@arndb.de>
 <CAOesGMjo=JT3TKwne+m5XUpkBMQFKQLZrr1T60m+Wx7YgqMiOA@mail.gmail.com>
 <4F605A3B.5030800@arm.com>
Message-ID: <20120315181718.d80071db25428a7b5113ef9a@canb.auug.org.au>

Hi all,

On Wed, 14 Mar 2012 08:43:39 +0000 Marc Zyngier <marc.zyngier at arm.com> wrote:
>
> On 14/03/12 00:52, Olof Johansson wrote:
> > On Tue, Mar 13, 2012 at 7:33 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> >> On Tuesday 13 March 2012, Marc Zyngier wrote:
> >>> On 13/03/12 11:55, Arnd Bergmann wrote:
> >>>> On Tuesday 13 March 2012, Marc Zyngier wrote:
> >>>>> On 13/03/12 10:15, Russell King - ARM Linux wrote:
> >>
> >>>> d) create a new next/timer branch in arm-soc that has Pawel's
> >>>>    98ed4ceb "ARM: vexpress: Get rid of MMIO_P2V" (the first patch from
> >>>>    vexpress/dt, your patches and the ux500/timer series. Also put
> >>>>    98ed4ceb into the next/cleanup branch.
> >>>>
> >>>> Any of those will work for us, my preference would be on #4. I have
> >>>> created the next/timer branch in the arm-soc tree, so you can use
> >>>> that and either rebase your patches on top or merge your tree into
> >>>> it and fix up the merge conflicts.
> >>>
> >>> Thanks for doing that Arnd.
> >>>
> >>> I've thus created a new branch:
> >>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> >>> local_timers-for-arm-soc
> >>>
> >>> which contains the arm-soc next/timers branch as well as my local timers
> >>> series. I'd greatly appreciate if you could pull it for 3.4.
> >>>
> >>
> >> I've updated the next/timer branch with your changes now, but did not
> >> put it into the for-next branch because Olof is currently handling that.
> >>
> >> Olof, can you add it to for-next please? The timer branch should have
> >> no dependencies other than rmk/for-armsoc, so it can be fairly close to
> >> the start.
> > 
> > 
> > Thanks. I merged into for-next, but since there's already a history in
> > there and I didn't rebuild it, it's on top of everything else.
> > 
> > I got two trivial merge conflicts (and a few that git sorted out
> > automatically): one with the tegra makefile, the other with shmobile's
> > timer init.
> > 
> > Marc, please take a look at the next/timers merge in the arm-soc
> > for-next branch and let me know if they're OK. I'm pretty sure they
> > are though.
> 
> Had a brief look, and it seems alright to me.
> 
> Thanks Olof!

ok, it looks like Marc's series is now in both the arm and arm-soc trees
(and causing some conflicts due to other changes to the files involved
and some resolved conflicts).

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From mgherzan at gmail.com  Thu Mar 15 03:23:43 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Thu, 15 Mar 2012 08:23:43 +0100
Subject: [PATCH v7] ARM: net: JIT compiler for packet filters
In-Reply-To: <20120213160248.GA25655@n2100.arm.linux.org.uk>
References: <1325937154-2656-1-git-send-email-mgherzan@gmail.com>
 <4F392DFD.4070600@gmail.com> <20120213160248.GA25655@n2100.arm.linux.org.uk>
Message-ID: <4F6198FF.90801@gmail.com>

Am 13.02.2012 17:02, schrieb Russell King - ARM Linux:
> On Mon, Feb 13, 2012 at 04:36:29PM +0100, Mircea Gherzan wrote:
>> Gentle ping. This patch has been in the tracking system for over a
>> month. Is there any reason not to apply it in arm/for-next?
> 
> Yes.  It needs quite a review to make sure that there's absolutely no
> possibility for userspace to be able to generate malicious ARM code
> and then have it executed.  Or put it another way: security paranoia.

Are there any specific security aspects you're thinking of? Leaks to
userspace, divisions by zero and invalid packet offsets are already
taken care of.

> I'm afraid that I've not been able to look at it at all yet, and I
> haven't seen anyone looking at the code from that aspect.

Thanks,
Mircea


From augulis.darius at gmail.com  Thu Mar 15 03:42:03 2012
From: augulis.darius at gmail.com (Darius Augulis)
Date: Thu, 15 Mar 2012 09:42:03 +0200
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <001501cd0241$6bb53560$431fa020$%han@samsung.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com>
 <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
Message-ID: <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>

Hi,

>
> Yes, only single LCD resolution will be left.
>
>> I have mini6410 with both 4.3" and 7" LCDs and real6410 with 7" LCD. Now
>> we have possibility to choose LCD size dynamically - leave it there.
>> What you mean "default" 4.3" size LCD? The 7" size LCD is also provided
>> by board sellers - I've bought it.
>
> OK, I see.
> Both mini6410 and real6410 provide both 4.3" and 7" LCDs,
> so you needs to select both LCDs.
>
> Um, usually, single LCD is provided on the single board.
> Also, the daughter board with another kind LCD can be connected to the board.

There is single board - mini6410 (or real6410) and it's name doesn't
depend on connected LCD size.
We know, that this board is available with different sizes of LCD and
currently we have in kernel support for both sizes.
It might be so, that it's implemented not in perfect way, but it was
accepted and at least it's working.
If you want to rework s3c-fb platform data and driver framework, you
should not drop any functionality created by other people.

>
> However, .win_mode is used not for LCD, but for windows of FIMD IP.
> Actually, our current framework does not support to choose multi LCD,
> so, I understand that you use .win_mode[1] as second LCD.
> However, that's not accurate way to select multi LCD.
>
> Thomas, can you consider Augulis's opinion?
> I think that the method to select multi LCDs is necessary.
>
> Ideal process is such as:
> ?1. add the patch to support to select multi LCDs
> ?2. apply above patch to make the mini6410 and real6410 to select multi LCDs.
> ?3. apply Thomas's patchset to remove timing value from .win_mode variable.

Yes, this would be the right way to go.

regards,
Darius A.


From paul.liu at linaro.org  Thu Mar 15 03:43:41 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Thu, 15 Mar 2012 15:43:41 +0800
Subject: [PATCH v9] mfd: Add anatop mfd driver
Message-ID: <1331797421-23731-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
Anatop provides regulators and thermal.
This driver handles the address space and the operation of the mfd device.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Venu Byravarasu <vbyravarasu at nvidia.com>
Cc: Peter Korsgaard <jacmet at sunsite.dk>
---
 drivers/mfd/Kconfig        |    8 +++
 drivers/mfd/Makefile       |    1 +
 drivers/mfd/anatop-mfd.c   |  142 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/anatop.h |   40 ++++++++++++
 4 files changed, 191 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mfd/anatop-mfd.c
 create mode 100644 include/linux/mfd/anatop.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 82da448..c3a9f31 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -846,6 +846,14 @@ config MFD_INTEL_MSIC
 	  Passage) chip. This chip embeds audio, battery, GPIO, etc.
 	  devices used in Intel Medfield platforms.
 
+config MFD_ANATOP
+	bool "Support for Freescale i.MX on-chip ANATOP controller"
+	depends on SOC_IMX6Q
+	help
+	  Select this option to enable Freescale i.MX on-chip ANATOP
+	  MFD controller. This controller embeds regulator and
+	  thermal devices for Freescale i.MX platforms.
+
 endmenu
 endif
 
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 27430d3..42c8bf6 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -113,3 +113,4 @@ obj-$(CONFIG_TPS65911_COMPARATOR)	+= tps65911-comparator.o
 obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
 obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
 obj-$(CONFIG_MFD_S5M_CORE)	+= s5m-core.o s5m-irq.o
+obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
new file mode 100644
index 0000000..4272e60
--- /dev/null
+++ b/drivers/mfd/anatop-mfd.c
@@ -0,0 +1,142 @@
+/*
+ * Anatop MFD driver
+ *
+ * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ * Copyright (C) 2012 Linaro
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+
+u32 anatop_get_bits(struct anatop *adata, u32 addr, int bit_shift,
+		    int bit_width)
+{
+	u32 val, mask;
+
+	if (bit_width == 32)
+		mask = ~0;
+	else
+		mask = (1 << bit_width) - 1;
+
+	val = readl(adata->ioreg + addr);
+	val = (val >> bit_shift) & mask;
+
+	return val;
+}
+EXPORT_SYMBOL(anatop_get_bits);
+
+void anatop_set_bits(struct anatop *adata, u32 addr, int bit_shift,
+		     int bit_width, u32 data)
+{
+	u32 val, mask;
+
+	if (bit_width == 32)
+		mask = ~0;
+	else
+		mask = (1 << bit_width) - 1;
+
+	spin_lock(&adata->reglock);
+	val = readl(adata->ioreg + addr) & ~(mask << bit_shift);
+	writel((data << bit_shift) | val, adata->ioreg + addr);
+	spin_unlock(&adata->reglock);
+}
+EXPORT_SYMBOL(anatop_set_bits);
+
+static const struct of_device_id of_anatop_subdevice_match[] = {
+	{ .compatible = "fsl,anatop-regulator", },
+	{ .compatible = "fsl,anatop-thermal", },
+	{ },
+};
+
+static int __devinit of_anatop_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	void *ioreg;
+	struct anatop *drvdata;
+
+	ioreg = of_iomap(np, 0);
+	if (!ioreg)
+		return -EADDRNOTAVAIL;
+	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+	if (!drvdata)
+		return -ENOMEM;
+	drvdata->ioreg = ioreg;
+	spin_lock_init(&drvdata->reglock);
+	platform_set_drvdata(pdev, drvdata);
+	of_platform_bus_probe(np, of_anatop_subdevice_match, dev);
+
+	return 0;
+}
+
+static int __devexit of_anatop_remove(struct platform_device *pdev)
+{
+	struct anatop *drvdata;
+	drvdata = platform_get_drvdata(pdev);
+	iounmap(drvdata->ioreg);
+	return 0;
+}
+
+static const struct of_device_id of_anatop_match[] = {
+	{ .compatible = "fsl,imx6q-anatop", },
+	{ },
+};
+
+static struct platform_driver anatop_of_driver = {
+	.driver = {
+		.name = "anatop-mfd",
+		.owner = THIS_MODULE,
+		.of_match_table = of_anatop_match,
+	},
+	.probe		= of_anatop_probe,
+	.remove		= of_anatop_remove,
+};
+
+static int __init anatop_init(void)
+{
+	return platform_driver_register(&anatop_of_driver);
+}
+postcore_initcall(anatop_init);
+
+static void __exit anatop_exit(void)
+{
+	platform_driver_unregister(&anatop_of_driver);
+}
+module_exit(anatop_exit);
+
+MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP MFD driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
new file mode 100644
index 0000000..22c1007
--- /dev/null
+++ b/include/linux/mfd/anatop.h
@@ -0,0 +1,40 @@
+/*
+ * anatop.h - Anatop MFD driver
+ *
+ *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ *  Copyright (C) 2012 Linaro
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_MFD_ANATOP_H
+#define __LINUX_MFD_ANATOP_H
+
+#include <linux/spinlock.h>
+
+/**
+ * anatop - MFD data
+ * @ioreg: ioremap register
+ * @reglock: spinlock for register read/write
+ */
+struct anatop {
+	void *ioreg;
+	spinlock_t reglock;
+};
+
+extern u32 anatop_get_bits(struct anatop *, u32, int, int);
+extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
+
+#endif /*  __LINUX_MFD_ANATOP_H */
-- 
1.7.9.1



From b39297 at freescale.com  Thu Mar 15 04:02:36 2012
From: b39297 at freescale.com (Wu Guoxing)
Date: Thu, 15 Mar 2012 16:02:36 +0800
Subject: [PATCH v8] ARM : mx35: 3ds-board: add framebuffer device
In-Reply-To: <20120314050238.GA15933@sapphire.tkos.co.il>
References: <1331691054-6442-1-git-send-email-b39297@freescale.com>
 <20120314050238.GA15933@sapphire.tkos.co.il>
Message-ID: <20120315080235.GA2837@wgx-VirtualBox>

Hi Baruch:

On Wed, Mar 14, 2012 at 07:02:38AM +0200, Baruch Siach wrote:
> Hi Wu,
> 
> On Wed, Mar 14, 2012 at 10:10:54AM +0800, Wu Guoxing wrote:
> > From: wu guoxing <b39297 at freescale.com>
> > 
> > This patch adds framebuffer support for freescale mx35 3ds board
> > 
> > Signed-off-by: Wu Guoxing <b39297 at freescale.com>
> > ---
> 
> [snip]
> 
> > +static int lcd_power_gpio = -ENXIO;
> 
> Since this is only used in mx35_3ds_lcd_set_power() below, can't it be local 
> to that routine?
> 
when I search the whole kernel code, I didn't find much using of function local static
variable, and even if the static variable is used only by that one function.

and we need this variable to be global, to avoid search the gpiochip every time.
> > +
> > +static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
> > +						     void *data)
> > +{
> > +	return !strcmp(chip->label, data);
> > +}
> > +
> > +static void mx35_3ds_lcd_set_power(
> > +				struct plat_lcd_data *pd, unsigned int power)
> > +{
> > +	struct gpio_chip *chip;
> > +
> > +	if (!gpio_is_valid(lcd_power_gpio)) {
> > +		chip = gpiochip_find(
> > +				"mc9s08dz60", mc9s08dz60_gpiochip_match);
> > +		if (chip) {
> > +			lcd_power_gpio =
> > +				chip->base + GPIO_MC9S08DZ60_LCD_ENABLE;
> > +			if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
> > +				pr_err("error: gpio already requested!\n");
> > +				lcd_power_gpio = -ENXIO;
> > +			}
> > +		} else {
> > +			pr_err("error: didn't find mc9s08dz60 gpio chip\n");
> > +		}
> > +	}
> > +
> > +	if (gpio_is_valid(lcd_power_gpio))
> > +		gpio_set_value_cansleep(lcd_power_gpio, power);
> > +}
> 
> baruch
> 
> -- 
>      http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
> =}------------------------------------------------ooO--U--Ooo------------{=
>    - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
> 



From jg1.han at samsung.com  Thu Mar 15 04:10:45 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Thu, 15 Mar 2012 17:10:45 +0900
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com> <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
Message-ID: <002a01cd0283$1f61b200$5e251600$%han@samsung.com>



> -----Original Message-----
> From: Darius Augulis [mailto:augulis.darius at gmail.com]
> Sent: Thursday, March 15, 2012 4:42 PM
> To: Jingoo Han
> Cc: Thomas Abraham; linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-
> kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; kgene.kim at samsung.com; ben-
> linux at fluff.org; patches at linaro.org; Kyungmin Park; JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark
> Brown; Peter Korsgaard; Maurus Cuelenaere
> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> 
> Hi,
> 
> >
> > Yes, only single LCD resolution will be left.
> >
> >> I have mini6410 with both 4.3" and 7" LCDs and real6410 with 7" LCD. Now
> >> we have possibility to choose LCD size dynamically - leave it there.
> >> What you mean "default" 4.3" size LCD? The 7" size LCD is also provided
> >> by board sellers - I've bought it.
> >
> > OK, I see.
> > Both mini6410 and real6410 provide both 4.3" and 7" LCDs,
> > so you needs to select both LCDs.
> >
> > Um, usually, single LCD is provided on the single board.
> > Also, the daughter board with another kind LCD can be connected to the board.
> 
> There is single board - mini6410 (or real6410) and it's name doesn't
> depend on connected LCD size.
> We know, that this board is available with different sizes of LCD and
> currently we have in kernel support for both sizes.
> It might be so, that it's implemented not in perfect way, but it was
> accepted and at least it's working.


I don't think so.
You argues that the wrong code should not be removed because it was accepted and at least it's working.
It is just wrong usage, which can just work.
Moreover, your code will make the problem, when 2~5 windows of FIMD IP are used.
So, your code can be removed.


> If you want to rework s3c-fb platform data and driver framework, you
> should not drop any functionality created by other people.

Augulis, Thomas Abraham wants to rework s3c-fb platform data and driver framework, not me. :)
I am just reviewing the Thomas's patchset.

> 
> >
> > However, .win_mode is used not for LCD, but for windows of FIMD IP.
> > Actually, our current framework does not support to choose multi LCD,
> > so, I understand that you use .win_mode[1] as second LCD.
> > However, that's not accurate way to select multi LCD.
> >
> > Thomas, can you consider Augulis's opinion?
> > I think that the method to select multi LCDs is necessary.
> >
> > Ideal process is such as:
> > ?1. add the patch to support to select multi LCDs
> > ?2. apply above patch to make the mini6410 and real6410 to select multi LCDs.
> > ?3. apply Thomas's patchset to remove timing value from .win_mode variable.
> 
> Yes, this would be the right way to go.

However, skipping step 1 & 2 is also available, because your code is wrong.
As I'm mentioned above, your code will make the problem when 2~5 windows of FIMD IP are used.


> 
> regards,
> Darius A.



From viresh.kumar at st.com  Thu Mar 15 04:19:54 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 15 Mar 2012 13:49:54 +0530
Subject: [PATCH v2] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <1331737232-25477-1-git-send-email-sr@denx.de>
References: <1331737232-25477-1-git-send-email-sr@denx.de>
Message-ID: <4F61A62A.3040501@st.com>


Hi Stefan,

Thanks for your patch. :)

I have looked carefully at the patch, regarding addresses and irq numbers,
and they look fine. Just few minor comments below:

On 3/14/2012 8:30 PM, Stefan Roese wrote:

> diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi

> +       soc {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "simple-bus";
> +               ranges;
> +

> +
> +               gmac0: ethernet at e0800000 {

There is no gmac1, so can name it gmac only.

> +                       compatible = "st,spear600-gmac";
> +                       reg = <0xe0800000 0x8000>;
> +                       interrupt-parent = <&vic1>;
> +                       interrupts = <24 23>;
> +                       interrupt-names = "macirq", "eth_wake_irq";
> +                       mac-address = [000000000000]; /* Filled in by U-Boot */
> +               };
> +

> +               fsmc0: flash at d1800000 {

same.

> +                       status = "disabled";
> +                       compatible = "st,spear600-fsmc-nand";
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       reg = <0xd1800000 0x1000        /* FSMC Register */
> +                              0xd2000000 0x4000>;      /* NAND Base */
> +                       reg-names = "fsmc_regs", "nand_data";
> +               };
> +
> +               smi0: flash at fc000000 {

same

> +                       status = "disabled";
> +                       compatible = "st,spear600-smi";
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       reg = <0xfc000000 0x1000>;
> +                       interrupt-parent = <&vic1>;
> +                       interrupts = <12>;
> +               };
> +

> diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
> index c6e4254..c4949aa 100644
> --- a/arch/arm/mach-spear6xx/spear600_evb.c
> +++ b/arch/arm/mach-spear6xx/spear600_evb.c
> @@ -32,9 +32,6 @@ static void __init spear600_evb_init(void)
>  {
>         unsigned int i;
> 

Why don't we remove the devices from arrays above, which are now
supported by DT?

> -       /* call spear600 machine init function */
> -       spear600_init();
> -
>         /* Add Platform Devices */
>         platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
> 
> diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c

> +static const struct of_device_id vic_of_match[] __initconst = {
> +       { .compatible = "arm,pl190-vic", .data = vic_of_init, },
> +       { /* Sentinel */ }
> +};
> +
> +static void __init spear6xx_dt_init_irq(void)
> +{
> +       of_irq_init(vic_of_match);
> +}
> +

Did you checked this out?

-- 
viresh


From augulis.darius at gmail.com  Thu Mar 15 04:26:50 2012
From: augulis.darius at gmail.com (Darius Augulis)
Date: Thu, 15 Mar 2012 10:26:50 +0200
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com>
 <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
Message-ID: <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>

On Thu, Mar 15, 2012 at 10:10 AM, Jingoo Han <jg1.han at samsung.com> wrote:

>> There is single board - mini6410 (or real6410) and it's name doesn't
>> depend on connected LCD size.
>> We know, that this board is available with different sizes of LCD and
>> currently we have in kernel support for both sizes.
>> It might be so, that it's implemented not in perfect way, but it was
>> accepted and at least it's working.
>
>
> I don't think so.
> You argues that the wrong code should not be removed because it was accepted and at least it's working.
> It is just wrong usage, which can just work.
> Moreover, your code will make the problem, when 2~5 windows of FIMD IP are used.

Could please explain that? How does LCD feature selection for mini6410
and real6410 break that?
Timing for different sizes of LCD is located in two statically
allocated structures which are used at board init time depending on
kernel param line.
Data from one of these structures is copied to s3c-fb platform data
dynamically by board init code. Why it's a problem? What changes if
platform data isn't rewritten dynamically?

> So, your code can be removed.

I don't think so. It does not break anything yet. One who make
changes, should ensure backwards compatibility, at least talking about
functionality and hardware (LCD) support, which was added few months
ago. Remember, we talk about kernel parameters line - now it lets
bootloader to select correct LCD size. After your changes, board with
7" LCD wont show anything.

Darius A.


From pullip.cho at samsung.com  Thu Mar 15 04:32:36 2012
From: pullip.cho at samsung.com (Cho KyongHo)
Date: Thu, 15 Mar 2012 17:32:36 +0900
Subject: [PATCH v12 0/3] iommu/exynos: Add IOMMU/System MMU driver for Samsung
 Exynos
Message-ID: <000001cd0286$2cf947e0$86ebd7a0$%cho@samsung.com>

These patches are successfully compiled in
linux-samsung.git/for-next branch
You can find the git repo in
http://git.kernel.org/?p=linux/kernel/git/kgene/linux-samsung.git

Changes since v11:
- Removed struct iommu_client and merged it
   with struct sysmmu_drvdata
- Fix kfree() invalid address in exynos_iommu_destroy_domain().

Changes since v10:
- Prevent race condition between iommu_attach_device() and
   iommu_detach_device().
- Added declaration of platform device for System MMU-FIMCs
   in mach/sysmmu.h.
- Some changes on macros and type names:
   * enum EXYNOS_SYSMMU_INTERRUPT_TYPE
      -> enum exynos_sysmmu_inttype
   * Changed macro definitions for register offsets
      to look uniform.

Changes since v9:
- Split the first patch into 2 patches.
   One removes System MMU driver from arch/arm/plat- tree and
   the other modifies and adds platform device definitions in
   arch/arm/mach tree
- Some bug fixes
- Change "gsc" for Exynos4 to "fimc"

Changes since v8:
- exynos_iommu_map/unmap() just works for the page sizes
   that System MMU supports. (Joerg's comment)
- 1 platform device for 1 H/W though a multimedia accelerator
   with several System MMUs attached.
   This make controlling System MMU simpler.
- Information between System MMU and the accelerators:
   Shifted to accelerator's device structure from System MMU's

Changes since v7:
- Rebased with the recent commits of the following git branches
  * git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git/next
  * git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git/for-next
- Changed magic numbers into macros
- Setting owner of a System MMU in 'iommu' field of dev_archdata
- Verbose message in the default fault handler
- Some bug fixes.

Changes since v6:
- Totally rewrite exynos_iommu_map() and exynos_iommu_unmap() according
  to the change in iommu_map() and iommu_unmap().
- Change special slab for Lv2 page table to kmalloc().

Changes since v5:
- Relation between device and a domain become n:1 (Joerg's comment)
- Implements iommu_commit(). --> Removed

Changes since v4:
- exynos_iommu_unmap()returns unmapped size in page order
  (Ohad Ben-Cohen's comment)
- Fixed typo error of resource names
- Fixed missing #include<mach/sysmmu.h>
  in arch/arm/mach-exynos4/mach-armlex4210.c

Changes since v3:
- Used DEFINE_RES_MEM and DEFINE_RES_IRQ macros
  to define resources of System MMU (Russell King's comment)
- Fixed removal of CONFIG_S5P_SLEEP definition  (Sylwester Nawrocki's comment)

Changes since v2:
- Add lock for System MMU private data.
  And fixes the following problems pointed by Joerg Rodel:
- Fix wrong argument to kmalloc() and get_free_pages()
- Merged patches into 2 due to bisectability

Changes since v1:
Fixes of the following problems pointed by Russell King.:
 - Missing unlocking a spinlock in exynos_iommu_attach_dev().
 - atomic_t -> int in sysmmu_drvdata.activations
 - sysmmu_platdata -> sysmmu_drvdata
 - Change in error messages in irq handler
 - Removed casting in format of error message
 - omap_iommu_ops -> exynos_iommu_ops in the last patch

Patch Summary:
[PATCH v12 1/3] S5P: SYSMMU: Remove System MMU device driver
[PATCH v12 2/3] ARM: EXYNOS: Change System MMU platform device definitions
[PATCH v12 3/3] iommu/exynos: Add iommu driver for Exynos Platforms

The first patch removes the existing System MMU device driver which does not conform to IOMMU API set prepared in the kernel.
 
The second patch enhances System MMU platform device definition:
 - Removed System MMU for MDMA0 in TOP block because it is not
   used. Use MDMA2 in LCD block.
 - Removed System MMU ID. Instead, a System MMU is bound to a device
   that the System MMU is dedicated during machine initialization.
   If a device driver wants to handle System MMU, it must bind its
   device with System MMU with sysmmu_set_owner().
 - clkdev
 - Added support for Exynos5

The last patch implements IOMMU API:
- New System MMU device driver that fully implements IOMMU API.

Thanks to Kyungmin Park and Marek Szyprowski for kind review.

Diffstats:
 arch/arm/mach-exynos/Kconfig                    |   10 +-
 arch/arm/mach-exynos/Makefile                   |    2 +-
 arch/arm/mach-exynos/clock-exynos4.c            |   79 +-
 arch/arm/mach-exynos/clock-exynos4.h            |    2 +
 arch/arm/mach-exynos/clock-exynos4210.c         |   11 +
 arch/arm/mach-exynos/clock-exynos4212.c         |   28 +-
 arch/arm/mach-exynos/clock-exynos5.c            |   90 ++
 arch/arm/mach-exynos/dev-sysmmu.c               |  457 ++++++-----
 arch/arm/mach-exynos/include/mach/irqs.h        |   25 +-
 arch/arm/mach-exynos/include/mach/map.h         |   38 +
 arch/arm/mach-exynos/include/mach/regs-clock.h  |    5 +
 arch/arm/mach-exynos/include/mach/regs-sysmmu.h |   28 -
 arch/arm/mach-exynos/include/mach/sysmmu.h      |   88 ++-
 arch/arm/mach-exynos/mach-armlex4210.c          |    1 -
 arch/arm/mach-exynos/mach-smdkv310.c            |    1 -
 arch/arm/plat-s5p/Kconfig                       |    8 -
 arch/arm/plat-s5p/Makefile                      |    1 -
 arch/arm/plat-s5p/sysmmu.c                      |  313 -------
 arch/arm/plat-samsung/include/plat/devs.h       |    1 -
 arch/arm/plat-samsung/include/plat/sysmmu.h     |   95 --
 drivers/iommu/Kconfig                           |   21 +
 drivers/iommu/Makefile                          |    1 +
 drivers/iommu/exynos-iommu.c                    | 1057 +++++++++++++++++++++++
 23 files changed, 1608 insertions(+), 754 deletions(-)



From pullip.cho at samsung.com  Thu Mar 15 04:32:37 2012
From: pullip.cho at samsung.com (Cho KyongHo)
Date: Thu, 15 Mar 2012 17:32:37 +0900
Subject: [PATCH v12 1/3] S5P: SYSMMU: Remove System MMU device driver
Message-ID: <000101cd0286$2db544e0$891fcea0$%cho@samsung.com>

This patch removes System MMU device driver from arm/plat-s5p tree
for transition to implement IOMMU driver.
Although controlling System MMU in this removing driver
is similar to the new IOMMU driver in the following patch,
the new one is almost rewrite of this driver and there is no
benefit to moving the driver file from arch/arm/ to drivers/iommu.

Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
---
 arch/arm/plat-s5p/Kconfig                   |    8 -
 arch/arm/plat-s5p/Makefile                  |    1 -
 arch/arm/plat-s5p/sysmmu.c                  |  313 ---------------------------
 arch/arm/plat-samsung/include/plat/devs.h   |    1 -
 arch/arm/plat-samsung/include/plat/sysmmu.h |   95 --------
 5 files changed, 0 insertions(+), 418 deletions(-)
 delete mode 100644 arch/arm/plat-s5p/sysmmu.c
 delete mode 100644 arch/arm/plat-samsung/include/plat/sysmmu.h

diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 96bea32..2c1193c 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -50,14 +50,6 @@ config S5P_PM
 	  Common code for power management support on S5P and newer SoCs
 	  Note: Do not select this for S5P6440 and S5P6450.
 
-comment "System MMU"
-
-config S5P_SYSTEM_MMU
-	bool "S5P SYSTEM MMU"
-	depends on ARCH_EXYNOS4
-	help
-	  Say Y here if you want to enable System MMU
-
 config S5P_SLEEP
 	bool
 	help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 4bd8241..4953d50 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -16,7 +16,6 @@ obj-y				+= clock.o
 obj-y				+= irq.o
 obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
 obj-$(CONFIG_S5P_GPIO_INT)	+= irq-gpioint.o
-obj-$(CONFIG_S5P_SYSTEM_MMU)	+= sysmmu.o
 obj-$(CONFIG_S5P_PM)		+= pm.o irq-pm.o
 obj-$(CONFIG_S5P_SLEEP)		+= sleep.o
 obj-$(CONFIG_S5P_HRT) 		+= s5p-time.o
diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c
deleted file mode 100644
index c8bec9c..0000000
--- a/arch/arm/plat-s5p/sysmmu.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/* linux/arch/arm/plat-s5p/sysmmu.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/export.h>
-
-#include <asm/pgtable.h>
-
-#include <mach/map.h>
-#include <mach/regs-sysmmu.h>
-#include <plat/sysmmu.h>
-
-#define CTRL_ENABLE	0x5
-#define CTRL_BLOCK	0x7
-#define CTRL_DISABLE	0x0
-
-static struct device *dev;
-
-static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
-	S5P_PAGE_FAULT_ADDR,
-	S5P_AR_FAULT_ADDR,
-	S5P_AW_FAULT_ADDR,
-	S5P_DEFAULT_SLAVE_ADDR,
-	S5P_AR_FAULT_ADDR,
-	S5P_AR_FAULT_ADDR,
-	S5P_AW_FAULT_ADDR,
-	S5P_AW_FAULT_ADDR
-};
-
-static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
-	"PAGE FAULT",
-	"AR MULTI-HIT FAULT",
-	"AW MULTI-HIT FAULT",
-	"BUS ERROR",
-	"AR SECURITY PROTECTION FAULT",
-	"AR ACCESS PROTECTION FAULT",
-	"AW SECURITY PROTECTION FAULT",
-	"AW ACCESS PROTECTION FAULT"
-};
-
-static int (*fault_handlers[S5P_SYSMMU_TOTAL_IPNUM])(
-		enum S5P_SYSMMU_INTERRUPT_TYPE itype,
-		unsigned long pgtable_base,
-		unsigned long fault_addr);
-
-/*
- * If adjacent 2 bits are true, the system MMU is enabled.
- * The system MMU is disabled, otherwise.
- */
-static unsigned long sysmmu_states;
-
-static inline void set_sysmmu_active(sysmmu_ips ips)
-{
-	sysmmu_states |= 3 << (ips * 2);
-}
-
-static inline void set_sysmmu_inactive(sysmmu_ips ips)
-{
-	sysmmu_states &= ~(3 << (ips * 2));
-}
-
-static inline int is_sysmmu_active(sysmmu_ips ips)
-{
-	return sysmmu_states & (3 << (ips * 2));
-}
-
-static void __iomem *sysmmusfrs[S5P_SYSMMU_TOTAL_IPNUM];
-
-static inline void sysmmu_block(sysmmu_ips ips)
-{
-	__raw_writel(CTRL_BLOCK, sysmmusfrs[ips] + S5P_MMU_CTRL);
-	dev_dbg(dev, "%s is blocked.\n", sysmmu_ips_name[ips]);
-}
-
-static inline void sysmmu_unblock(sysmmu_ips ips)
-{
-	__raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
-	dev_dbg(dev, "%s is unblocked.\n", sysmmu_ips_name[ips]);
-}
-
-static inline void __sysmmu_tlb_invalidate(sysmmu_ips ips)
-{
-	__raw_writel(0x1, sysmmusfrs[ips] + S5P_MMU_FLUSH);
-	dev_dbg(dev, "TLB of %s is invalidated.\n", sysmmu_ips_name[ips]);
-}
-
-static inline void __sysmmu_set_ptbase(sysmmu_ips ips, unsigned long pgd)
-{
-	if (unlikely(pgd == 0)) {
-		pgd = (unsigned long)ZERO_PAGE(0);
-		__raw_writel(0x20, sysmmusfrs[ips] + S5P_MMU_CFG); /* 4KB LV1 */
-	} else {
-		__raw_writel(0x0, sysmmusfrs[ips] + S5P_MMU_CFG); /* 16KB LV1 */
-	}
-
-	__raw_writel(pgd, sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
-
-	dev_dbg(dev, "Page table base of %s is initialized with 0x%08lX.\n",
-						sysmmu_ips_name[ips], pgd);
-	__sysmmu_tlb_invalidate(ips);
-}
-
-void sysmmu_set_fault_handler(sysmmu_ips ips,
-			int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
-					unsigned long pgtable_base,
-					unsigned long fault_addr))
-{
-	BUG_ON(!((ips >= SYSMMU_MDMA) && (ips < S5P_SYSMMU_TOTAL_IPNUM)));
-	fault_handlers[ips] = handler;
-}
-
-static irqreturn_t s5p_sysmmu_irq(int irq, void *dev_id)
-{
-	/* SYSMMU is in blocked when interrupt occurred. */
-	unsigned long base = 0;
-	sysmmu_ips ips = (sysmmu_ips)dev_id;
-	enum S5P_SYSMMU_INTERRUPT_TYPE itype;
-
-	itype = (enum S5P_SYSMMU_INTERRUPT_TYPE)
-		__ffs(__raw_readl(sysmmusfrs[ips] + S5P_INT_STATUS));
-
-	BUG_ON(!((itype >= 0) && (itype < 8)));
-
-	dev_alert(dev, "%s occurred by %s.\n", sysmmu_fault_name[itype],
-							sysmmu_ips_name[ips]);
-
-	if (fault_handlers[ips]) {
-		unsigned long addr;
-
-		base = __raw_readl(sysmmusfrs[ips] + S5P_PT_BASE_ADDR);
-		addr = __raw_readl(sysmmusfrs[ips] + fault_reg_offset[itype]);
-
-		if (fault_handlers[ips](itype, base, addr)) {
-			__raw_writel(1 << itype,
-					sysmmusfrs[ips] + S5P_INT_CLEAR);
-			dev_notice(dev, "%s from %s is resolved."
-					" Retrying translation.\n",
-				sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
-		} else {
-			base = 0;
-		}
-	}
-
-	sysmmu_unblock(ips);
-
-	if (!base)
-		dev_notice(dev, "%s from %s is not handled.\n",
-			sysmmu_fault_name[itype], sysmmu_ips_name[ips]);
-
-	return IRQ_HANDLED;
-}
-
-void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd)
-{
-	if (is_sysmmu_active(ips)) {
-		sysmmu_block(ips);
-		__sysmmu_set_ptbase(ips, pgd);
-		sysmmu_unblock(ips);
-	} else {
-		dev_dbg(dev, "%s is disabled. "
-			"Skipping initializing page table base.\n",
-						sysmmu_ips_name[ips]);
-	}
-}
-
-void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd)
-{
-	if (!is_sysmmu_active(ips)) {
-		sysmmu_clk_enable(ips);
-
-		__sysmmu_set_ptbase(ips, pgd);
-
-		__raw_writel(CTRL_ENABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
-
-		set_sysmmu_active(ips);
-		dev_dbg(dev, "%s is enabled.\n", sysmmu_ips_name[ips]);
-	} else {
-		dev_dbg(dev, "%s is already enabled.\n", sysmmu_ips_name[ips]);
-	}
-}
-
-void s5p_sysmmu_disable(sysmmu_ips ips)
-{
-	if (is_sysmmu_active(ips)) {
-		__raw_writel(CTRL_DISABLE, sysmmusfrs[ips] + S5P_MMU_CTRL);
-		set_sysmmu_inactive(ips);
-		sysmmu_clk_disable(ips);
-		dev_dbg(dev, "%s is disabled.\n", sysmmu_ips_name[ips]);
-	} else {
-		dev_dbg(dev, "%s is already disabled.\n", sysmmu_ips_name[ips]);
-	}
-}
-
-void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips)
-{
-	if (is_sysmmu_active(ips)) {
-		sysmmu_block(ips);
-		__sysmmu_tlb_invalidate(ips);
-		sysmmu_unblock(ips);
-	} else {
-		dev_dbg(dev, "%s is disabled. "
-			"Skipping invalidating TLB.\n", sysmmu_ips_name[ips]);
-	}
-}
-
-static int s5p_sysmmu_probe(struct platform_device *pdev)
-{
-	int i, ret;
-	struct resource *res, *mem;
-
-	dev = &pdev->dev;
-
-	for (i = 0; i < S5P_SYSMMU_TOTAL_IPNUM; i++) {
-		int irq;
-
-		sysmmu_clk_init(dev, i);
-		sysmmu_clk_disable(i);
-
-		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-		if (!res) {
-			dev_err(dev, "Failed to get the resource of %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENODEV;
-			goto err_res;
-		}
-
-		mem = request_mem_region(res->start, resource_size(res),
-					 pdev->name);
-		if (!mem) {
-			dev_err(dev, "Failed to request the memory region of %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -EBUSY;
-			goto err_res;
-		}
-
-		sysmmusfrs[i] = ioremap(res->start, resource_size(res));
-		if (!sysmmusfrs[i]) {
-			dev_err(dev, "Failed to ioremap() for %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENXIO;
-			goto err_reg;
-		}
-
-		irq = platform_get_irq(pdev, i);
-		if (irq <= 0) {
-			dev_err(dev, "Failed to get the IRQ resource of %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENOENT;
-			goto err_map;
-		}
-
-		if (request_irq(irq, s5p_sysmmu_irq, IRQF_DISABLED,
-						pdev->name, (void *)i)) {
-			dev_err(dev, "Failed to request IRQ for %s.\n",
-							sysmmu_ips_name[i]);
-			ret = -ENOENT;
-			goto err_map;
-		}
-	}
-
-	return 0;
-
-err_map:
-	iounmap(sysmmusfrs[i]);
-err_reg:
-	release_mem_region(mem->start, resource_size(mem));
-err_res:
-	return ret;
-}
-
-static int s5p_sysmmu_remove(struct platform_device *pdev)
-{
-	return 0;
-}
-int s5p_sysmmu_runtime_suspend(struct device *dev)
-{
-	return 0;
-}
-
-int s5p_sysmmu_runtime_resume(struct device *dev)
-{
-	return 0;
-}
-
-const struct dev_pm_ops s5p_sysmmu_pm_ops = {
-	.runtime_suspend	= s5p_sysmmu_runtime_suspend,
-	.runtime_resume		= s5p_sysmmu_runtime_resume,
-};
-
-static struct platform_driver s5p_sysmmu_driver = {
-	.probe		= s5p_sysmmu_probe,
-	.remove		= s5p_sysmmu_remove,
-	.driver		= {
-		.owner		= THIS_MODULE,
-		.name		= "s5p-sysmmu",
-		.pm		= &s5p_sysmmu_pm_ops,
-	}
-};
-
-static int __init s5p_sysmmu_init(void)
-{
-	return platform_driver_register(&s5p_sysmmu_driver);
-}
-arch_initcall(s5p_sysmmu_init);
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 2155d4a..4067d1d 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -133,7 +133,6 @@ extern struct platform_device exynos4_device_pcm1;
 extern struct platform_device exynos4_device_pcm2;
 extern struct platform_device exynos4_device_pd[];
 extern struct platform_device exynos4_device_spdif;
-extern struct platform_device exynos4_device_sysmmu;
 
 extern struct platform_device samsung_asoc_dma;
 extern struct platform_device samsung_asoc_idma;
diff --git a/arch/arm/plat-samsung/include/plat/sysmmu.h b/arch/arm/plat-samsung/include/plat/sysmmu.h
deleted file mode 100644
index 5fe8ee0..0000000
--- a/arch/arm/plat-samsung/include/plat/sysmmu.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * Samsung System MMU driver for S5P platform
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __PLAT_SAMSUNG_SYSMMU_H
-#define __PLAT_SAMSUNG_SYSMMU_H __FILE__
-
-enum S5P_SYSMMU_INTERRUPT_TYPE {
-	SYSMMU_PAGEFAULT,
-	SYSMMU_AR_MULTIHIT,
-	SYSMMU_AW_MULTIHIT,
-	SYSMMU_BUSERROR,
-	SYSMMU_AR_SECURITY,
-	SYSMMU_AR_ACCESS,
-	SYSMMU_AW_SECURITY,
-	SYSMMU_AW_PROTECTION, /* 7 */
-	SYSMMU_FAULTS_NUM
-};
-
-#ifdef CONFIG_S5P_SYSTEM_MMU
-
-#include <mach/sysmmu.h>
-
-/**
- * s5p_sysmmu_enable() - enable system mmu of ip
- * @ips: The ip connected system mmu.
- * #pgd: Base physical address of the 1st level page table
- *
- * This function enable system mmu to transfer address
- * from virtual address to physical address
- */
-void s5p_sysmmu_enable(sysmmu_ips ips, unsigned long pgd);
-
-/**
- * s5p_sysmmu_disable() - disable sysmmu mmu of ip
- * @ips: The ip connected system mmu.
- *
- * This function disable system mmu to transfer address
- * from virtual address to physical address
- */
-void s5p_sysmmu_disable(sysmmu_ips ips);
-
-/**
- * s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
- * @ips: The ip connected system mmu.
- * @pgd: The page table base address.
- *
- * This function set page table base address
- * When system mmu transfer address from virtaul address to physical address,
- * system mmu refer address information from page table
- */
-void s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
-
-/**
- * s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
- * @ips: The ip connected system mmu.
- *
- * This function flush all TLB entry in system mmu
- */
-void s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
-
-/** s5p_sysmmu_set_fault_handler() - Fault handler for System MMUs
- * @itype: type of fault.
- * @pgtable_base: the physical address of page table base. This is 0 if @ips is
- *               SYSMMU_BUSERROR.
- * @fault_addr: the device (virtual) address that the System MMU tried to
- *             translated. This is 0 if @ips is SYSMMU_BUSERROR.
- * Called when interrupt occurred by the System MMUs
- * The device drivers of peripheral devices that has a System MMU can implement
- * a fault handler to resolve address translation fault by System MMU.
- * The meanings of return value and parameters are described below.
-
- * return value: non-zero if the fault is correctly resolved.
- *         zero if the fault is not handled.
- */
-void s5p_sysmmu_set_fault_handler(sysmmu_ips ips,
-			int (*handler)(enum S5P_SYSMMU_INTERRUPT_TYPE itype,
-					unsigned long pgtable_base,
-					unsigned long fault_addr));
-#else
-#define s5p_sysmmu_enable(ips, pgd) do { } while (0)
-#define s5p_sysmmu_disable(ips) do { } while (0)
-#define s5p_sysmmu_set_tablebase_pgd(ips, pgd) do { } while (0)
-#define s5p_sysmmu_tlb_invalidate(ips) do { } while (0)
-#define s5p_sysmmu_set_fault_handler(ips, handler) do { } while (0)
-#endif
-#endif /* __ASM_PLAT_SYSMMU_H */
-- 
1.7.1



From pullip.cho at samsung.com  Thu Mar 15 04:32:40 2012
From: pullip.cho at samsung.com (Cho KyongHo)
Date: Thu, 15 Mar 2012 17:32:40 +0900
Subject: [PATCH v12 3/3] iommu/exynos: Add iommu driver for Exynos Platforms
Message-ID: <000301cd0286$2f4310d0$8dc93270$%cho@samsung.com>

This is the System MMU driver and IOMMU API implementation for
Exynos SOC platforms. Exynos platforms has more than 10 System
MMUs dedicated for each multimedia accelerators.

The System MMU driver is already in arc/arm/plat-s5p but it is
moved to drivers/iommu due to Ohad Ben-Cohen gathered IOMMU drivers
there

Any device driver in Exynos platforms that needs to control its
System MMU must call platform_set_sysmmu() to inform System MMU
driver who will control it.
platform_set_sysmmu() is defined in <mach/sysmmu.h>

Cc: Joerg Roedel <joerg.roedel at amd.com>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
---
 drivers/iommu/Kconfig        |   21 +
 drivers/iommu/Makefile       |    1 +
 drivers/iommu/exynos-iommu.c | 1057 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1079 insertions(+), 0 deletions(-)
 create mode 100644 drivers/iommu/exynos-iommu.c

diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 6bea696..25d3eed 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -142,4 +142,25 @@ config OMAP_IOMMU_DEBUG
 
          Say N unless you know you need this.
 
+config EXYNOS_IOMMU
+	bool "Exynos IOMMU Support"
+	depends on EXYNOS_DEV_SYSMMU
+	select IOMMU_API
+	help
+	  Support for the IOMMU(System MMU) of Samsung Exynos application
+	  processor family. This enables H/W multimedia accellerators to see
+	  non-linear physical memory chunks as a linear memory in their
+	  address spaces
+
+	  If unsure, say N here.
+
+config EXYNOS_IOMMU_DEBUG
+	bool "Debugging log for Exynos IOMMU"
+	depends on EXYNOS_IOMMU
+	help
+	  Select this to see the detailed log message that shows what
+	  happens in the IOMMU driver
+
+	  Say N unless you need kernel log message for IOMMU debugging
+
 endif # IOMMU_SUPPORT
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 0e36b49..5a8fd97 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_IRQ_REMAP) += intr_remapping.o
 obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
 obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o
 obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
+obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
new file mode 100644
index 0000000..b8daf7c
--- /dev/null
+++ b/drivers/iommu/exynos-iommu.c
@@ -0,0 +1,1057 @@
+/* linux/drivers/iommu/exynos_iommu.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifdef CONFIG_EXYNOS_IOMMU_DEBUG
+#define DEBUG
+#endif
+
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mm.h>
+#include <linux/iommu.h>
+#include <linux/errno.h>
+#include <linux/list.h>
+#include <linux/memblock.h>
+#include <linux/export.h>
+
+#include <asm/cacheflush.h>
+#include <asm/pgtable.h>
+
+#include <mach/sysmmu.h>
+
+/* We does not consider super section mapping (16MB) */
+#define SECT_ORDER 20
+#define LPAGE_ORDER 16
+#define SPAGE_ORDER 12
+
+#define SECT_SIZE (1 << SECT_ORDER)
+#define LPAGE_SIZE (1 << LPAGE_ORDER)
+#define SPAGE_SIZE (1 << SPAGE_ORDER)
+
+#define SECT_MASK (~(SECT_SIZE - 1))
+#define LPAGE_MASK (~(LPAGE_SIZE - 1))
+#define SPAGE_MASK (~(SPAGE_SIZE - 1))
+
+#define lv1ent_fault(sent) (((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
+#define lv1ent_page(sent) ((*(sent) & 3) == 1)
+#define lv1ent_section(sent) ((*(sent) & 3) == 2)
+
+#define lv2ent_fault(pent) ((*(pent) & 3) == 0)
+#define lv2ent_small(pent) ((*(pent) & 2) == 2)
+#define lv2ent_large(pent) ((*(pent) & 3) == 1)
+
+#define section_phys(sent) (*(sent) & SECT_MASK)
+#define section_offs(iova) ((iova) & 0xFFFFF)
+#define lpage_phys(pent) (*(pent) & LPAGE_MASK)
+#define lpage_offs(iova) ((iova) & 0xFFFF)
+#define spage_phys(pent) (*(pent) & SPAGE_MASK)
+#define spage_offs(iova) ((iova) & 0xFFF)
+
+#define lv1ent_offset(iova) ((iova) >> SECT_ORDER)
+#define lv2ent_offset(iova) (((iova) & 0xFF000) >> SPAGE_ORDER)
+
+#define NUM_LV1ENTRIES 4096
+#define NUM_LV2ENTRIES 256
+
+#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(long))
+
+#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
+
+#define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
+
+#define mk_lv1ent_sect(pa) ((pa) | 2)
+#define mk_lv1ent_page(pa) ((pa) | 1)
+#define mk_lv2ent_lpage(pa) ((pa) | 1)
+#define mk_lv2ent_spage(pa) ((pa) | 2)
+
+#define CTRL_ENABLE	0x5
+#define CTRL_BLOCK	0x7
+#define CTRL_DISABLE	0x0
+
+#define REG_MMU_CTRL		0x000
+#define REG_MMU_CFG		0x004
+#define REG_MMU_STATUS		0x008
+#define REG_MMU_FLUSH		0x00C
+#define REG_MMU_FLUSH_ENTRY	0x010
+#define REG_PT_BASE_ADDR	0x014
+#define REG_INT_STATUS		0x018
+#define REG_INT_CLEAR		0x01C
+
+#define REG_PAGE_FAULT_ADDR	0x024
+#define REG_AW_FAULT_ADDR	0x028
+#define REG_AR_FAULT_ADDR	0x02C
+#define REG_DEFAULT_SLAVE_ADDR	0x030
+
+#define REG_MMU_VERSION		0x034
+
+#define REG_PB0_SADDR		0x04C
+#define REG_PB0_EADDR		0x050
+#define REG_PB1_SADDR		0x054
+#define REG_PB1_EADDR		0x058
+
+static unsigned long *section_entry(unsigned long *pgtable, unsigned long iova)
+{
+	return pgtable + lv1ent_offset(iova);
+}
+
+static unsigned long *page_entry(unsigned long *sent, unsigned long iova)
+{
+	return (unsigned long *)__va(lv2table_base(sent)) + lv2ent_offset(iova);
+}
+
+enum exynos_sysmmu_inttype {
+	SYSMMU_PAGEFAULT,
+	SYSMMU_AR_MULTIHIT,
+	SYSMMU_AW_MULTIHIT,
+	SYSMMU_BUSERROR,
+	SYSMMU_AR_SECURITY,
+	SYSMMU_AR_ACCESS,
+	SYSMMU_AW_SECURITY,
+	SYSMMU_AW_PROTECTION, /* 7 */
+	SYSMMU_FAULT_UNKNOWN,
+	SYSMMU_FAULTS_NUM
+};
+
+typedef int (*sysmmu_fault_handler_t)(enum exynos_sysmmu_inttype itype,
+			unsigned long pgtable_base, unsigned long fault_addr);
+
+static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
+	REG_PAGE_FAULT_ADDR,
+	REG_AR_FAULT_ADDR,
+	REG_AW_FAULT_ADDR,
+	REG_DEFAULT_SLAVE_ADDR,
+	REG_AR_FAULT_ADDR,
+	REG_AR_FAULT_ADDR,
+	REG_AW_FAULT_ADDR,
+	REG_AW_FAULT_ADDR
+};
+
+static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
+	"PAGE FAULT",
+	"AR MULTI-HIT FAULT",
+	"AW MULTI-HIT FAULT",
+	"BUS ERROR",
+	"AR SECURITY PROTECTION FAULT",
+	"AR ACCESS PROTECTION FAULT",
+	"AW SECURITY PROTECTION FAULT",
+	"AW ACCESS PROTECTION FAULT",
+	"UNKNOWN FAULT"
+};
+
+struct exynos_iommu_domain {
+	struct list_head clients; /* list of sysmmu_drvdata.node */
+	unsigned long *pgtable; /* lv1 page table, 16KB */
+	short *lv2entcnt; /* free lv2 entry counter for each section */
+	spinlock_t lock; /* lock for this structure */
+	spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
+};
+
+struct sysmmu_drvdata {
+	struct list_head node; /* entry of exynos_iommu_domain.clients */
+	struct device *sysmmu;	/* System MMU's device descriptor */
+	struct device *dev;	/* Owner of system MMU */
+	char *dbgname;
+	int nsfrs;
+	void __iomem **sfrbases;
+	struct clk *clk[2];
+	int activations;
+	rwlock_t lock;
+	struct iommu_domain *domain;
+	sysmmu_fault_handler_t fault_handler;
+	unsigned long pgtable;
+};
+
+static bool set_sysmmu_active(struct sysmmu_drvdata *data)
+{
+	/* return true if the System MMU was not active previously
+	   and it needs to be initialized */
+	return ++data->activations == 1;
+}
+
+static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
+{
+	/* return true if the System MMU is needed to be disabled */
+	BUG_ON(data->activations < 1);
+	return --data->activations == 0;
+}
+
+static bool is_sysmmu_active(struct sysmmu_drvdata *data)
+{
+	return data->activations > 0;
+}
+
+static void sysmmu_block(void __iomem *sfrbase)
+{
+	__raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
+}
+
+static void sysmmu_unblock(void __iomem *sfrbase)
+{
+	__raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
+}
+
+static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
+{
+	__raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
+}
+
+static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
+						unsigned long iova)
+{
+	__raw_writel((iova & SPAGE_MASK) | 1, sfrbase + REG_MMU_FLUSH_ENTRY);
+}
+
+static void __sysmmu_set_ptbase(void __iomem *sfrbase,
+				       unsigned long pgd)
+{
+	__raw_writel(0x1, sfrbase + REG_MMU_CFG); /* 16KB LV1, LRU */
+	__raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
+
+	__sysmmu_tlb_invalidate(sfrbase);
+}
+
+static void __sysmmu_set_prefbuf(void __iomem *sfrbase, unsigned long base,
+						unsigned long size, int idx)
+{
+	__raw_writel(base, sfrbase + REG_PB0_SADDR + idx * 8);
+	__raw_writel(size - 1 + base,  sfrbase + REG_PB0_EADDR + idx * 8);
+}
+
+void exynos_sysmmu_set_prefbuf(struct device *dev,
+				unsigned long base0, unsigned long size0,
+				unsigned long base1, unsigned long size1)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	unsigned long flags;
+	int i;
+
+	BUG_ON((base0 + size0) <= base0);
+	BUG_ON((size1 > 0) && ((base1 + size1) <= base1));
+
+	read_lock_irqsave(&data->lock, flags);
+	if (!is_sysmmu_active(data))
+		goto finish;
+
+	for (i = 0; i < data->nsfrs; i++) {
+		if ((readl(data->sfrbases[i] + REG_MMU_VERSION) >> 28) == 3) {
+			sysmmu_block(data->sfrbases[i]);
+
+			if (size1 == 0) {
+				if (size0 <= SZ_128K) {
+					base1 = base0;
+					size1 = size0;
+				} else {
+					size1 = size0 -
+						ALIGN(size0 / 2, SZ_64K);
+					size0 = size0 - size1;
+					base1 = base0 + size0;
+				}
+			}
+
+			__sysmmu_set_prefbuf(
+					data->sfrbases[i], base0, size0, 0);
+			__sysmmu_set_prefbuf(
+					data->sfrbases[i], base1, size1, 1);
+
+			sysmmu_unblock(data->sfrbases[i]);
+		}
+	}
+finish:
+	read_unlock_irqrestore(&data->lock, flags);
+}
+
+static void __set_fault_handler(struct sysmmu_drvdata *data,
+					sysmmu_fault_handler_t handler)
+{
+	unsigned long flags;
+
+	write_lock_irqsave(&data->lock, flags);
+	data->fault_handler = handler;
+	write_unlock_irqrestore(&data->lock, flags);
+}
+
+void exynos_sysmmu_set_fault_handler(struct device *dev,
+					sysmmu_fault_handler_t handler)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+
+	__set_fault_handler(data, handler);
+}
+
+static int default_fault_handler(enum exynos_sysmmu_inttype itype,
+		     unsigned long pgtable_base, unsigned long fault_addr)
+{
+	unsigned long *ent;
+
+	if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
+		itype = SYSMMU_FAULT_UNKNOWN;
+
+	pr_err("%s occured at 0x%lx(Page table base: 0x%lx)\n",
+			sysmmu_fault_name[itype], fault_addr, pgtable_base);
+
+	ent = section_entry(__va(pgtable_base), fault_addr);
+	pr_err("\tLv1 entry: 0x%lx\n", *ent);
+
+	if (lv1ent_page(ent)) {
+		ent = page_entry(ent, fault_addr);
+		pr_err("\t Lv2 entry: 0x%lx\n", *ent);
+	}
+
+	pr_err("Generating Kernel OOPS... because it is unrecoverable.\n");
+
+	BUG();
+
+	return 0;
+}
+
+static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
+{
+	/* SYSMMU is in blocked when interrupt occurred. */
+	struct sysmmu_drvdata *data = dev_id;
+	struct resource *irqres;
+	struct platform_device *pdev;
+	enum exynos_sysmmu_inttype itype;
+	unsigned long addr = -1;
+
+	int i, ret = -ENOSYS;
+
+	read_lock(&data->lock);
+
+	WARN_ON(!is_sysmmu_active(data));
+
+	pdev = to_platform_device(data->sysmmu);
+	for (i = 0; i < pdev->num_resources; i++) {
+		irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+		if (irqres && ((int)irqres->start == irq))
+			break;
+	}
+
+	if (i == pdev->num_resources) {
+		itype = SYSMMU_FAULT_UNKNOWN;
+	} else {
+		i /= 2;
+
+		itype = (enum exynos_sysmmu_inttype)
+			__ffs(__raw_readl(data->sfrbases[i] + REG_INT_STATUS));
+		if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
+			itype = SYSMMU_FAULT_UNKNOWN;
+		else
+			addr = __raw_readl(
+				data->sfrbases[i] + fault_reg_offset[itype]);
+	}
+
+	if (data->domain)
+		ret = report_iommu_fault(data->domain, data->dev,
+				addr, itype);
+
+	if ((ret == -ENOSYS) && data->fault_handler) {
+		unsigned long base = data->pgtable;
+		if (itype != SYSMMU_FAULT_UNKNOWN)
+			base = __raw_readl(
+					data->sfrbases[i] + REG_PT_BASE_ADDR);
+		ret = data->fault_handler(itype, base, addr);
+	}
+
+	if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
+		__raw_writel(1 << itype, data->sfrbases[i] + REG_INT_CLEAR);
+	else
+		dev_dbg(data->sysmmu, "(%s) %s is not handled.\n",
+				data->dbgname, sysmmu_fault_name[itype]);
+
+	if (itype != SYSMMU_FAULT_UNKNOWN)
+		sysmmu_unblock(data->sfrbases[i]);
+
+	read_unlock(&data->lock);
+
+	return IRQ_HANDLED;
+}
+
+static bool __exynos_sysmmu_disable(struct sysmmu_drvdata *data)
+{
+	unsigned long flags;
+	bool disabled = false;
+	int i;
+
+	write_lock_irqsave(&data->lock, flags);
+
+	if (!set_sysmmu_inactive(data))
+		goto finish;
+
+	for (i = 0; i < data->nsfrs; i++)
+		__raw_writel(CTRL_DISABLE, data->sfrbases[i] + REG_MMU_CTRL);
+
+	if (data->clk[1])
+		clk_disable(data->clk[1]);
+	if (data->clk[0])
+		clk_disable(data->clk[0]);
+
+	disabled = true;
+	data->pgtable = 0;
+	data->domain = NULL;
+finish:
+	write_unlock_irqrestore(&data->lock, flags);
+
+	if (disabled)
+		dev_dbg(data->sysmmu, "(%s) Disabled\n", data->dbgname);
+	else
+		dev_dbg(data->sysmmu, "(%s) %d times left to be disabled\n",
+					data->dbgname, data->activations);
+
+	return disabled;
+}
+
+/* __exynos_sysmmu_enable: Enables System MMU
+ *
+ * returns -error if an error occurred and System MMU is not enabled,
+ * 0 if the System MMU has been just enabled and 1 if System MMU was already
+ * enabled before.
+ */
+static int __exynos_sysmmu_enable(struct sysmmu_drvdata *data,
+			unsigned long pgtable, struct iommu_domain *domain)
+{
+	int i, ret;
+	unsigned long flags;
+
+	write_lock_irqsave(&data->lock, flags);
+
+	if (!set_sysmmu_active(data)) {
+		if (WARN_ON(pgtable != data->pgtable)) {
+			ret = -EBUSY;
+			set_sysmmu_inactive(data);
+		} else {
+			ret = 1;
+		}
+
+		dev_dbg(data->sysmmu, "(%s) Already enabled\n", data->dbgname);
+		goto finish;
+	}
+
+	ret = 0;
+
+	if (data->clk[0])
+		clk_enable(data->clk[0]);
+	if (data->clk[1])
+		clk_enable(data->clk[1]);
+
+	data->pgtable = pgtable;
+
+	for (i = 0; i < data->nsfrs; i++) {
+		__sysmmu_set_ptbase(data->sfrbases[i], pgtable);
+
+		if ((readl(data->sfrbases[i] + REG_MMU_VERSION) >> 28) == 3) {
+			/* System MMU version is 3.x */
+			__raw_writel((1 << 12) | (2 << 28),
+					data->sfrbases[i] + REG_MMU_CFG);
+			__sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 0);
+			__sysmmu_set_prefbuf(data->sfrbases[i], 0, -1, 1);
+		}
+
+		__raw_writel(CTRL_ENABLE, data->sfrbases[i] + REG_MMU_CTRL);
+	}
+
+	data->domain = domain;
+
+	dev_dbg(data->sysmmu, "(%s) Enabled\n", data->dbgname);
+finish:
+	write_unlock_irqrestore(&data->lock, flags);
+
+	if ((ret < 0) && (ret != -EBUSY)) {
+		__exynos_sysmmu_disable(data);
+		dev_dbg(data->sysmmu, "(%s) Failed to enable\n", data->dbgname);
+	}
+
+	return ret;
+}
+
+int exynos_sysmmu_enable(struct device *dev, unsigned long pgtable)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	int ret;
+
+	BUG_ON(!memblock_is_memory(pgtable));
+
+	ret = pm_runtime_get_sync(data->sysmmu);
+	if (ret < 0)
+		return ret;
+
+	ret = __exynos_sysmmu_enable(data, pgtable, NULL);
+	if (ret < 0)
+		pm_runtime_put(data->sysmmu);
+	else
+		data->dev = dev;
+
+	return ret;
+}
+
+bool exynos_sysmmu_disable(struct device *dev)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	bool disabled;
+
+	disabled = __exynos_sysmmu_disable(data);
+	pm_runtime_put(data->sysmmu);
+
+	return disabled;
+}
+
+static void sysmmu_tlb_invalidate_entry(struct device *dev, unsigned long iova)
+{
+	unsigned long flags;
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+
+	read_lock_irqsave(&data->lock, flags);
+
+	if (is_sysmmu_active(data)) {
+		int i;
+		for (i = 0; i < data->nsfrs; i++) {
+			sysmmu_block(data->sfrbases[i]);
+			__sysmmu_tlb_invalidate_entry(data->sfrbases[i], iova);
+			sysmmu_unblock(data->sfrbases[i]);
+		}
+	} else {
+		dev_dbg(data->sysmmu,
+			"(%s) Disabled. Skipping invalidating TLB.\n",
+			data->dbgname);
+	}
+
+	read_unlock_irqrestore(&data->lock, flags);
+}
+
+void exynos_sysmmu_tlb_invalidate(struct device *dev)
+{
+	unsigned long flags;
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+
+	read_lock_irqsave(&data->lock, flags);
+
+	if (is_sysmmu_active(data)) {
+		int i;
+		for (i = 0; i < data->nsfrs; i++) {
+			sysmmu_block(data->sfrbases[i]);
+			__sysmmu_tlb_invalidate(data->sfrbases[i]);
+			sysmmu_unblock(data->sfrbases[i]);
+		}
+	} else {
+		dev_dbg(data->sysmmu,
+			"(%s) Disabled. Skipping invalidating TLB.\n",
+			data->dbgname);
+	}
+
+	read_unlock_irqrestore(&data->lock, flags);
+}
+
+static int exynos_sysmmu_probe(struct platform_device *pdev)
+{
+	int i, ret;
+	struct device *dev;
+	struct sysmmu_drvdata *data;
+
+	dev = &pdev->dev;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (!data) {
+		dev_dbg(dev, "Not enough memory\n");
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+
+	ret = dev_set_drvdata(dev, data);
+	if (ret) {
+		dev_dbg(dev, "Unabled to initialize driver data\n");
+		goto err_init;
+	}
+
+	data->nsfrs = pdev->num_resources / 2;
+	data->sfrbases = kmalloc(sizeof(*data->sfrbases) * data->nsfrs,
+								GFP_KERNEL);
+	if (data->sfrbases == NULL) {
+		dev_dbg(dev, "Not enough memory\n");
+		ret = -ENOMEM;
+		goto err_init;
+	}
+
+	for (i = 0; i < data->nsfrs; i++) {
+		struct resource *res;
+		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+		if (!res) {
+			dev_dbg(dev, "Unable to find IOMEM region\n");
+			ret = -ENOENT;
+			goto err_res;
+		}
+
+		data->sfrbases[i] = ioremap(res->start, resource_size(res));
+		if (!data->sfrbases[i]) {
+			dev_dbg(dev, "Unable to map IOMEM @ PA:%#x\n",
+							res->start);
+			ret = -ENOENT;
+			goto err_res;
+		}
+	}
+
+	for (i = 0; i < data->nsfrs; i++) {
+		ret = platform_get_irq(pdev, i);
+		if (ret <= 0) {
+			dev_dbg(dev, "Unable to find IRQ resource\n");
+			goto err_irq;
+		}
+
+		ret = request_irq(ret, exynos_sysmmu_irq, 0,
+					dev_name(dev), data);
+		if (ret) {
+			dev_dbg(dev, "Unabled to register interrupt handler\n");
+			goto err_irq;
+		}
+	}
+
+	if (dev_get_platdata(dev)) {
+		char *deli, *beg;
+		struct sysmmu_platform_data *platdata = dev_get_platdata(dev);
+
+		beg = platdata->clockname;
+
+		for (deli = beg; (*deli != '\0') && (*deli != ','); deli++)
+			/* NOTHING */;
+
+		if (*deli == '\0')
+			deli = NULL;
+		else
+			*deli = '\0';
+
+		data->clk[0] = clk_get(dev, beg);
+		if (IS_ERR(data->clk[0])) {
+			data->clk[0] = NULL;
+			dev_dbg(dev, "No clock descriptor registered\n");
+		}
+
+		if (data->clk[0] && deli) {
+			*deli = ',';
+			data->clk[1] = clk_get(dev, deli + 1);
+			if (IS_ERR(data->clk[1]))
+				data->clk[1] = NULL;
+		}
+
+		data->dbgname = platdata->dbgname;
+	}
+
+	data->sysmmu = dev;
+	rwlock_init(&data->lock);
+	INIT_LIST_HEAD(&data->node);
+
+	__set_fault_handler(data, &default_fault_handler);
+
+	if (dev->parent)
+		pm_runtime_enable(dev);
+
+	dev_dbg(dev, "(%s) Initialized\n", data->dbgname);
+	return 0;
+err_irq:
+	while (i-- > 0) {
+		int irq;
+
+		irq = platform_get_irq(pdev, i);
+		free_irq(irq, data);
+	}
+err_res:
+	while (data->nsfrs-- > 0)
+		iounmap(data->sfrbases[data->nsfrs]);
+	kfree(data->sfrbases);
+err_init:
+	kfree(data);
+err_alloc:
+	dev_err(dev, "Failed to initialize\n");
+	return ret;
+}
+
+static struct platform_driver exynos_sysmmu_driver = {
+	.probe		= exynos_sysmmu_probe,
+	.driver		= {
+		.owner		= THIS_MODULE,
+		.name		= "exynos-sysmmu",
+	}
+};
+
+static inline void pgtable_flush(void *vastart, void *vaend)
+{
+	dmac_flush_range(vastart, vaend);
+	outer_flush_range(virt_to_phys(vastart),
+				virt_to_phys(vaend));
+}
+
+static int exynos_iommu_domain_init(struct iommu_domain *domain)
+{
+	struct exynos_iommu_domain *priv;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->pgtable = (unsigned long *)__get_free_pages(
+						GFP_KERNEL | __GFP_ZERO, 2);
+	if (!priv->pgtable)
+		goto err_pgtable;
+
+	priv->lv2entcnt = (short *)__get_free_pages(
+						GFP_KERNEL | __GFP_ZERO, 1);
+	if (!priv->lv2entcnt)
+		goto err_counter;
+
+	pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
+
+	spin_lock_init(&priv->lock);
+	spin_lock_init(&priv->pgtablelock);
+	INIT_LIST_HEAD(&priv->clients);
+
+	domain->priv = priv;
+	return 0;
+
+err_counter:
+	free_pages((unsigned long)priv->pgtable, 2);
+err_pgtable:
+	kfree(priv);
+	return -ENOMEM;
+}
+
+static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	struct sysmmu_drvdata *data;
+	unsigned long flags;
+	int i;
+
+	WARN_ON(!list_empty(&priv->clients));
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	list_for_each_entry(data, &priv->clients, node) {
+		while (!exynos_sysmmu_disable(data->dev))
+			; /* until System MMU is actually disabled */
+	}
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	for (i = 0; i < NUM_LV1ENTRIES; i++)
+		if (lv1ent_page(priv->pgtable + i))
+			kfree(__va(lv2table_base(priv->pgtable + i)));
+
+	free_pages((unsigned long)priv->pgtable, 2);
+	free_pages((unsigned long)priv->lv2entcnt, 1);
+	kfree(domain->priv);
+	domain->priv = NULL;
+}
+
+static int exynos_iommu_attach_device(struct iommu_domain *domain,
+				   struct device *dev)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	struct exynos_iommu_domain *priv = domain->priv;
+	unsigned long flags;
+	int ret;
+
+	ret = pm_runtime_get_sync(data->sysmmu);
+	if (ret < 0)
+		return ret;
+
+	ret = 0;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	ret = __exynos_sysmmu_enable(data, __pa(priv->pgtable), domain);
+
+	if (ret == 0) {
+		/* 'data->node' must not appear in priv->clients */
+		BUG_ON(!list_empty(&data->node));
+		data->dev = dev;
+		list_add_tail(&data->node, &priv->clients);
+	}
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	if (ret < 0) {
+		dev_err(dev, "%s: Failed to attach IOMMU with pgtable %#lx\n",
+				__func__, __pa(priv->pgtable));
+		pm_runtime_put(data->sysmmu);
+	} else if (ret > 0) {
+		dev_dbg(dev, "%s: IOMMU with pgtable 0x%lx already attached\n",
+					__func__, __pa(priv->pgtable));
+	} else {
+		dev_dbg(dev, "%s: Attached new IOMMU with pgtable 0x%lx\n",
+					__func__, __pa(priv->pgtable));
+	}
+
+	return ret;
+}
+
+static void exynos_iommu_detach_device(struct iommu_domain *domain,
+				    struct device *dev)
+{
+	struct sysmmu_drvdata *data = dev_get_drvdata(dev->archdata.iommu);
+	struct exynos_iommu_domain *priv = domain->priv;
+	struct list_head *pos;
+	unsigned long flags;
+	bool found = false;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	list_for_each(pos, &priv->clients) {
+		if (list_entry(pos, struct sysmmu_drvdata, node) == data) {
+			found = true;
+			break;
+		}
+	}
+
+	if (!found)
+		goto finish;
+
+	if (__exynos_sysmmu_disable(data)) {
+		dev_dbg(dev, "%s: Detached IOMMU with pgtable %#lx\n",
+					__func__, __pa(priv->pgtable));
+		list_del(&data->node);
+		INIT_LIST_HEAD(&data->node);
+
+	} else {
+		dev_dbg(dev, "%s: Detaching IOMMU with pgtable %#lx delayed",
+					__func__, __pa(priv->pgtable));
+	}
+
+finish:
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	if (found)
+		pm_runtime_put(data->sysmmu);
+}
+
+static unsigned long *alloc_lv2entry(unsigned long *sent, unsigned long iova,
+					short *pgcounter)
+{
+	if (lv1ent_fault(sent)) {
+		unsigned long *pent;
+
+		pent = kzalloc(LV2TABLE_SIZE, GFP_ATOMIC);
+		BUG_ON((unsigned long)pent & (LV2TABLE_SIZE - 1));
+		if (!pent)
+			return NULL;
+
+		*sent = mk_lv1ent_page(__pa(pent));
+		*pgcounter = NUM_LV2ENTRIES;
+		pgtable_flush(pent, pent + NUM_LV2ENTRIES);
+		pgtable_flush(sent, sent + 1);
+	}
+
+	return page_entry(sent, iova);
+}
+
+static int lv1set_section(unsigned long *sent, phys_addr_t paddr, short *pgcnt)
+{
+	if (lv1ent_section(sent))
+		return -EADDRINUSE;
+
+	if (lv1ent_page(sent)) {
+		if (*pgcnt != NUM_LV2ENTRIES)
+			return -EADDRINUSE;
+
+		kfree(page_entry(sent, 0));
+
+		*pgcnt = 0;
+	}
+
+	*sent = mk_lv1ent_sect(paddr);
+
+	pgtable_flush(sent, sent + 1);
+
+	return 0;
+}
+
+static int lv2set_page(unsigned long *pent, phys_addr_t paddr, size_t size,
+								short *pgcnt)
+{
+	if (size == SPAGE_SIZE) {
+		if (!lv2ent_fault(pent))
+			return -EADDRINUSE;
+
+		*pent = mk_lv2ent_spage(paddr);
+		pgtable_flush(pent, pent + 1);
+		*pgcnt -= 1;
+	} else { /* size == LPAGE_SIZE */
+		int i;
+		for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
+			if (!lv2ent_fault(pent)) {
+				memset(pent, 0, sizeof(*pent) * i);
+				return -EADDRINUSE;
+			}
+
+			*pent = mk_lv2ent_lpage(paddr);
+		}
+		pgtable_flush(pent - SPAGES_PER_LPAGE, pent);
+		*pgcnt -= SPAGES_PER_LPAGE;
+	}
+
+	return 0;
+}
+
+static int exynos_iommu_map(struct iommu_domain *domain, unsigned long iova,
+			 phys_addr_t paddr, size_t size, int prot)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	unsigned long *entry;
+	unsigned long flags;
+	int ret = -ENOMEM;
+
+	BUG_ON(priv->pgtable == NULL);
+
+	spin_lock_irqsave(&priv->pgtablelock, flags);
+
+	entry = section_entry(priv->pgtable, iova);
+
+	if (size == SECT_SIZE) {
+		ret = lv1set_section(entry, paddr,
+					&priv->lv2entcnt[lv1ent_offset(iova)]);
+	} else {
+		unsigned long *pent;
+
+		pent = alloc_lv2entry(entry, iova,
+					&priv->lv2entcnt[lv1ent_offset(iova)]);
+
+		if (!pent)
+			ret = -ENOMEM;
+		else
+			ret = lv2set_page(pent, paddr, size,
+					&priv->lv2entcnt[lv1ent_offset(iova)]);
+	}
+
+	if (ret) {
+		pr_debug("%s: Failed to map iova 0x%lx/0x%x bytes\n",
+							__func__, iova, size);
+	}
+
+	spin_unlock_irqrestore(&priv->pgtablelock, flags);
+
+	return ret;
+}
+
+static size_t exynos_iommu_unmap(struct iommu_domain *domain,
+					       unsigned long iova, size_t size)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	struct sysmmu_drvdata *data;
+	unsigned long flags;
+	unsigned long *ent;
+
+	BUG_ON(priv->pgtable == NULL);
+
+	spin_lock_irqsave(&priv->pgtablelock, flags);
+
+	ent = section_entry(priv->pgtable, iova);
+
+	if (lv1ent_section(ent)) {
+		BUG_ON(size < SECT_SIZE);
+
+		*ent = 0;
+		pgtable_flush(ent, ent + 1);
+		size = SECT_SIZE;
+		goto done;
+	}
+
+	if (unlikely(lv1ent_fault(ent))) {
+		if (size > SECT_SIZE)
+			size = SECT_SIZE;
+		goto done;
+	}
+
+	/* lv1ent_page(sent) == true here */
+
+	ent = page_entry(ent, iova);
+
+	if (unlikely(lv2ent_fault(ent))) {
+		size = SPAGE_SIZE;
+		goto done;
+	}
+
+	if (lv2ent_small(ent)) {
+		*ent = 0;
+		size = SPAGE_SIZE;
+		priv->lv2entcnt[lv1ent_offset(iova)] += 1;
+		goto done;
+	}
+
+	/* lv1ent_large(ent) == true here */
+	BUG_ON(size < LPAGE_SIZE);
+
+	memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
+
+	size = LPAGE_SIZE;
+	priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
+done:
+	spin_unlock_irqrestore(&priv->pgtablelock, flags);
+
+	spin_lock_irqsave(&priv->lock, flags);
+	list_for_each_entry(data, &priv->clients, node)
+		sysmmu_tlb_invalidate_entry(data->dev, iova);
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+
+	return size;
+}
+
+static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
+					  unsigned long iova)
+{
+	struct exynos_iommu_domain *priv = domain->priv;
+	unsigned long *entry;
+	unsigned long flags;
+	phys_addr_t phys = 0;
+
+	spin_lock_irqsave(&priv->pgtablelock, flags);
+
+	entry = section_entry(priv->pgtable, iova);
+
+	if (lv1ent_section(entry)) {
+		phys = section_phys(entry) + section_offs(iova);
+	} else if (lv1ent_page(entry)) {
+		entry = page_entry(entry, iova);
+
+		if (lv2ent_large(entry))
+			phys = lpage_phys(entry) + lpage_offs(iova);
+		else if (lv2ent_small(entry))
+			phys = spage_phys(entry) + spage_offs(iova);
+	}
+
+	spin_unlock_irqrestore(&priv->pgtablelock, flags);
+
+	return phys;
+}
+
+static struct iommu_ops exynos_iommu_ops = {
+	.domain_init = &exynos_iommu_domain_init,
+	.domain_destroy = &exynos_iommu_domain_destroy,
+	.attach_dev = &exynos_iommu_attach_device,
+	.detach_dev = &exynos_iommu_detach_device,
+	.map = &exynos_iommu_map,
+	.unmap = &exynos_iommu_unmap,
+	.iova_to_phys = &exynos_iommu_iova_to_phys,
+	.pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
+};
+
+static int __init exynos_iommu_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&exynos_sysmmu_driver);
+
+	if (ret == 0)
+		bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
+
+	return ret;
+}
+arch_initcall(exynos_iommu_init);
-- 
1.7.1



From pullip.cho at samsung.com  Thu Mar 15 04:32:39 2012
From: pullip.cho at samsung.com (Cho KyongHo)
Date: Thu, 15 Mar 2012 17:32:39 +0900
Subject: [PATCH v12 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
Message-ID: <000201cd0286$2e6fbb40$8b4f31c0$%cho@samsung.com>

Handling System MMUs with an identifier is not flexible to manage
System MMU platform devices because of the following reasons:
1. A device driver which needs to handle System MMU must know the ID.
2. A System MMU may not present in some implementations of Exynos family.
3. Handling System MMU with IOMMU API does not require an ID.

This patch is the result of removing ID of System MMUs.
Instead, a device driver that needs to handle its System MMU must
use IOMMU API while its descriptor of platform device is given.

This patch also includes the following enhancements:
- A System MMU device becomes a child if its power domain device.
- clkdev

Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
---
 arch/arm/mach-exynos/Kconfig                    |   10 +-
 arch/arm/mach-exynos/Makefile                   |    2 +-
 arch/arm/mach-exynos/clock-exynos4.c            |   79 ++--
 arch/arm/mach-exynos/clock-exynos4.h            |    2 +
 arch/arm/mach-exynos/clock-exynos4210.c         |   11 +
 arch/arm/mach-exynos/clock-exynos4212.c         |   28 ++-
 arch/arm/mach-exynos/clock-exynos5.c            |   90 +++++
 arch/arm/mach-exynos/dev-sysmmu.c               |  457 ++++++++++++----------
 arch/arm/mach-exynos/include/mach/irqs.h        |   25 +-
 arch/arm/mach-exynos/include/mach/map.h         |   38 ++
 arch/arm/mach-exynos/include/mach/regs-clock.h  |    5 +
 arch/arm/mach-exynos/include/mach/regs-sysmmu.h |   28 --
 arch/arm/mach-exynos/include/mach/sysmmu.h      |   88 +++--
 arch/arm/mach-exynos/mach-armlex4210.c          |    1 -
 arch/arm/mach-exynos/mach-smdkv310.c            |    1 -
 15 files changed, 529 insertions(+), 336 deletions(-)
 delete mode 100644 arch/arm/mach-exynos/include/mach/regs-sysmmu.h

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 0491cee..801c738 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -85,10 +85,10 @@ config EXYNOS4_SETUP_FIMD0
 	help
 	  Common setup code for FIMD0.
 
-config EXYNOS4_DEV_SYSMMU
+config EXYNOS_DEV_SYSMMU
 	bool
 	help
-	  Common setup code for SYSTEM MMU in EXYNOS4
+	  Common setup code for SYSTEM MMU in EXYNOS platforms
 
 config EXYNOS4_DEV_DWMCI
 	bool
@@ -200,12 +200,12 @@ config MACH_SMDKV310
 	select S3C_DEV_HSMMC2
 	select S3C_DEV_HSMMC3
 	select SAMSUNG_DEV_BACKLIGHT
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_DEV_AHCI
 	select SAMSUNG_DEV_KEYPAD
 	select EXYNOS4_DEV_DMA
 	select SAMSUNG_DEV_PWM
 	select EXYNOS4_DEV_USB_OHCI
-	select EXYNOS4_DEV_SYSMMU
 	select EXYNOS4_SETUP_FIMD0
 	select EXYNOS4_SETUP_I2C1
 	select EXYNOS4_SETUP_KEYPAD
@@ -224,7 +224,6 @@ config MACH_ARMLEX4210
 	select S3C_DEV_HSMMC3
 	select EXYNOS4_DEV_AHCI
 	select EXYNOS4_DEV_DMA
-	select EXYNOS4_DEV_SYSMMU
 	select EXYNOS4_SETUP_SDHCI
 	help
 	  Machine support for Samsung ARMLEX4210 based on EXYNOS4210
@@ -251,6 +250,7 @@ config MACH_UNIVERSAL_C210
 	select S5P_DEV_MFC
 	select S5P_DEV_ONENAND
 	select S5P_DEV_TV
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_DEV_DMA
 	select EXYNOS4_SETUP_FIMD0
 	select EXYNOS4_SETUP_I2C1
@@ -322,6 +322,7 @@ config MACH_ORIGEN
 	select S5P_DEV_USB_EHCI
 	select SAMSUNG_DEV_BACKLIGHT
 	select SAMSUNG_DEV_PWM
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_DEV_DMA
 	select EXYNOS4_DEV_USB_OHCI
 	select EXYNOS4_SETUP_FIMD0
@@ -345,6 +346,7 @@ config MACH_SMDK4212
 	select SAMSUNG_DEV_BACKLIGHT
 	select SAMSUNG_DEV_KEYPAD
 	select SAMSUNG_DEV_PWM
+	select EXYNOS_DEV_SYSMMU
 	select EXYNOS4_DEV_DMA
 	select EXYNOS4_SETUP_I2C1
 	select EXYNOS4_SETUP_I2C3
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8631840..2726252 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -50,7 +50,7 @@ obj-$(CONFIG_MACH_EXYNOS5_DT)		+= mach-exynos5-dt.o
 obj-y					+= dev-uart.o
 obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
 obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
-obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)	+= dev-sysmmu.o
+obj-$(CONFIG_EXYNOS_DEV_SYSMMU)		+= dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
 obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 523e360..cebdef0 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -168,7 +168,7 @@ static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
 }
 
-static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
 }
@@ -198,6 +198,11 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
 }
 
+int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
+}
+
 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
@@ -678,61 +683,55 @@ static struct clk exynos4_init_clocks_off[] = {
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 14),
 	}, {
-		.name		= "SYSMMU_MDMA",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+		.enable		= exynos4_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+		.enable		= exynos4_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(tv, 2),
+		.enable		= exynos4_clk_ip_tv_ctrl,
+		.ctrlbit	= (1 << 4),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+		.enable		= exynos4_clk_ip_cam_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(rot, 4),
 		.enable		= exynos4_clk_ip_image_ctrl,
-		.ctrlbit	= (1 << 5),
+		.ctrlbit	= (1 << 4),
 	}, {
-		.name		= "SYSMMU_FIMC0",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc0, 5),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 7),
 	}, {
-		.name		= "SYSMMU_FIMC1",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc1, 6),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 8),
 	}, {
-		.name		= "SYSMMU_FIMC2",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc2, 7),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 9),
 	}, {
-		.name		= "SYSMMU_FIMC3",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimc3, 8),
 		.enable		= exynos4_clk_ip_cam_ctrl,
 		.ctrlbit	= (1 << 10),
 	}, {
-		.name		= "SYSMMU_JPEG",
-		.enable		= exynos4_clk_ip_cam_ctrl,
-		.ctrlbit	= (1 << 11),
-	}, {
-		.name		= "SYSMMU_FIMD0",
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimd0, 10),
 		.enable		= exynos4_clk_ip_lcd0_ctrl,
 		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_FIMD1",
-		.enable		= exynos4_clk_ip_lcd1_ctrl,
-		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_PCIe",
-		.enable		= exynos4_clk_ip_fsys_ctrl,
-		.ctrlbit	= (1 << 18),
-	}, {
-		.name		= "SYSMMU_G2D",
-		.enable		= exynos4_clk_ip_image_ctrl,
-		.ctrlbit	= (1 << 3),
-	}, {
-		.name		= "SYSMMU_ROTATOR",
-		.enable		= exynos4_clk_ip_image_ctrl,
-		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_TV",
-		.enable		= exynos4_clk_ip_tv_ctrl,
-		.ctrlbit	= (1 << 4),
-	}, {
-		.name		= "SYSMMU_MFC_L",
-		.enable		= exynos4_clk_ip_mfc_ctrl,
-		.ctrlbit	= (1 << 1),
-	}, {
-		.name		= "SYSMMU_MFC_R",
-		.enable		= exynos4_clk_ip_mfc_ctrl,
-		.ctrlbit	= (1 << 2),
 	}
 };
 
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
index cb71c29..28a1197 100644
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -26,5 +26,7 @@ extern struct clk *exynos4_clkset_group_list[];
 extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
 
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 3b131e4..b8689ff 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -26,6 +26,7 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
 
 #include "common.h"
 #include "clock-exynos4.h"
@@ -94,6 +95,16 @@ static struct clk init_clocks_off[] = {
 		.devname	= "exynos4-fb.1",
 		.enable		= exynos4_clk_ip_lcd1_ctrl,
 		.ctrlbit	= (1 << 0),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
+		.enable		= exynos4_clk_ip_image_ctrl,
+		.ctrlbit	= (1 << 3),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(fimd1, 11),
+		.enable		= exynos4_clk_ip_lcd1_ctrl,
+		.ctrlbit	= (1 << 4),
 	},
 };
 
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 3ecc01e..9882312 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -26,6 +26,7 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
 
 #include "common.h"
 #include "clock-exynos4.h"
@@ -39,6 +40,16 @@ static struct sleep_save exynos4212_clock_save[] = {
 };
 #endif
 
+static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
+}
+
+static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
+}
+
 static struct clk *clk_src_mpll_user_list[] = {
 	[0] = &clk_fin_mpll,
 	[1] = &exynos4_clk_mout_mpll.clk,
@@ -66,7 +77,22 @@ static struct clksrc_clk clksrcs[] = {
 };
 
 static struct clk init_clocks_off[] = {
-	/* nothing here yet */
+	{
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
+		.enable		= exynos4_clk_ip_dmc_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= exynos4212_clk_ip_isp0_ctrl,
+		.ctrlbit	= (7 << 8),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME2,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= exynos4212_clk_ip_isp1_ctrl,
+		.ctrlbit	= (1 << 4),
+	}
 };
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index d013982..3320ad1 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -82,6 +82,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
 }
 
+static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
+}
+
 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
 {
 	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
@@ -127,6 +132,21 @@ static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
 }
 
+static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
+}
+
+static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
+}
+
+static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
+}
+
 /* Core list of CMU_CPU side */
 
 static struct clksrc_clk exynos5_clk_mout_apll = {
@@ -630,6 +650,76 @@ static struct clk exynos5_init_clocks_off[] = {
 		.parent		= &exynos5_clk_aclk_66.clk,
 		.enable		= exynos5_clk_ip_peric_ctrl,
 		.ctrlbit	= (1 << 14),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
+		.enable		= &exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 1),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
+		.enable		= &exynos5_clk_ip_mfc_ctrl,
+		.ctrlbit	= (1 << 2),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(tv, 2),
+		.enable		= &exynos5_clk_ip_disp1_ctrl,
+		.ctrlbit	= (1 << 9)
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(jpeg, 3),
+		.enable		= &exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(rot, 4),
+		.enable		= &exynos5_clk_ip_gen_ctrl,
+		.ctrlbit	= (1 << 6)
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc0, 5),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 7),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc1, 6),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 8),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc2, 7),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(gsc3, 8),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= &exynos5_clk_ip_isp0_ctrl,
+		.ctrlbit	= (0x3F << 8),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME2,
+		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
+		.enable		= &exynos5_clk_ip_isp1_ctrl,
+		.ctrlbit	= (0xF << 4),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(camif0, 12),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(camif1, 13),
+		.enable		= &exynos5_clk_ip_gscl_ctrl,
+		.ctrlbit	= (1 << 12),
+	}, {
+		.name		= SYSMMU_CLOCK_NAME,
+		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
+		.enable		= &exynos5_clk_ip_acp_ctrl,
+		.ctrlbit	= (1 << 7)
 	}
 };
 
diff --git a/arch/arm/mach-exynos/dev-sysmmu.c b/arch/arm/mach-exynos/dev-sysmmu.c
index 781563f..c5b1ea3 100644
--- a/arch/arm/mach-exynos/dev-sysmmu.c
+++ b/arch/arm/mach-exynos/dev-sysmmu.c
@@ -1,9 +1,9 @@
-/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
+/* linux/arch/arm/mach-exynos/dev-sysmmu.c
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * EXYNOS4 - System MMU support
+ * EXYNOS - System MMU support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,222 +12,263 @@
 
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
-#include <linux/export.h>
+
+#include <plat/cpu.h>
 
 #include <mach/map.h>
 #include <mach/irqs.h>
 #include <mach/sysmmu.h>
-#include <plat/s5p-clock.h>
-
-/* These names must be equal to the clock names in mach-exynos4/clock.c */
-const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
-	"SYSMMU_MDMA"	,
-	"SYSMMU_SSS"	,
-	"SYSMMU_FIMC0"	,
-	"SYSMMU_FIMC1"	,
-	"SYSMMU_FIMC2"	,
-	"SYSMMU_FIMC3"	,
-	"SYSMMU_JPEG"	,
-	"SYSMMU_FIMD0"	,
-	"SYSMMU_FIMD1"	,
-	"SYSMMU_PCIe"	,
-	"SYSMMU_G2D"	,
-	"SYSMMU_ROTATOR",
-	"SYSMMU_MDMA2"	,
-	"SYSMMU_TV"	,
-	"SYSMMU_MFC_L"	,
-	"SYSMMU_MFC_R"	,
-};
 
-static struct resource exynos4_sysmmu_resource[] = {
-	[0] = {
-		.start	= EXYNOS4_PA_SYSMMU_MDMA,
-		.end	= EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_SYSMMU_MDMA0_0,
-		.end	= IRQ_SYSMMU_MDMA0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[2] = {
-		.start	= EXYNOS4_PA_SYSMMU_SSS,
-		.end	= EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[3] = {
-		.start	= IRQ_SYSMMU_SSS_0,
-		.end	= IRQ_SYSMMU_SSS_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[4] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC0,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[5] = {
-		.start	= IRQ_SYSMMU_FIMC0_0,
-		.end	= IRQ_SYSMMU_FIMC0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[6] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC1,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[7] = {
-		.start	= IRQ_SYSMMU_FIMC1_0,
-		.end	= IRQ_SYSMMU_FIMC1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[8] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC2,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[9] = {
-		.start	= IRQ_SYSMMU_FIMC2_0,
-		.end	= IRQ_SYSMMU_FIMC2_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[10] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMC3,
-		.end	= EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[11] = {
-		.start	= IRQ_SYSMMU_FIMC3_0,
-		.end	= IRQ_SYSMMU_FIMC3_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[12] = {
-		.start	= EXYNOS4_PA_SYSMMU_JPEG,
-		.end	= EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[13] = {
-		.start	= IRQ_SYSMMU_JPEG_0,
-		.end	= IRQ_SYSMMU_JPEG_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[14] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMD0,
-		.end	= EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[15] = {
-		.start	= IRQ_SYSMMU_LCD0_M0_0,
-		.end	= IRQ_SYSMMU_LCD0_M0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[16] = {
-		.start	= EXYNOS4_PA_SYSMMU_FIMD1,
-		.end	= EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[17] = {
-		.start	= IRQ_SYSMMU_LCD1_M1_0,
-		.end	= IRQ_SYSMMU_LCD1_M1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[18] = {
-		.start	= EXYNOS4_PA_SYSMMU_PCIe,
-		.end	= EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[19] = {
-		.start	= IRQ_SYSMMU_PCIE_0,
-		.end	= IRQ_SYSMMU_PCIE_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[20] = {
-		.start	= EXYNOS4_PA_SYSMMU_G2D,
-		.end	= EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[21] = {
-		.start	= IRQ_SYSMMU_2D_0,
-		.end	= IRQ_SYSMMU_2D_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[22] = {
-		.start	= EXYNOS4_PA_SYSMMU_ROTATOR,
-		.end	= EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[23] = {
-		.start	= IRQ_SYSMMU_ROTATOR_0,
-		.end	= IRQ_SYSMMU_ROTATOR_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[24] = {
-		.start	= EXYNOS4_PA_SYSMMU_MDMA2,
-		.end	= EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[25] = {
-		.start	= IRQ_SYSMMU_MDMA1_0,
-		.end	= IRQ_SYSMMU_MDMA1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[26] = {
-		.start	= EXYNOS4_PA_SYSMMU_TV,
-		.end	= EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[27] = {
-		.start	= IRQ_SYSMMU_TV_M0_0,
-		.end	= IRQ_SYSMMU_TV_M0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[28] = {
-		.start	= EXYNOS4_PA_SYSMMU_MFC_L,
-		.end	= EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[29] = {
-		.start	= IRQ_SYSMMU_MFC_M0_0,
-		.end	= IRQ_SYSMMU_MFC_M0_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-	[30] = {
-		.start	= EXYNOS4_PA_SYSMMU_MFC_R,
-		.end	= EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[31] = {
-		.start	= IRQ_SYSMMU_MFC_M1_0,
-		.end	= IRQ_SYSMMU_MFC_M1_0,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
+static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
+
+#define SYSMMU_PLATFORM_DEVICE(ipname, devid)				\
+static struct sysmmu_platform_data platdata_##ipname = {		\
+	.dbgname = #ipname,						\
+};									\
+struct platform_device SYSMMU_PLATDEV(ipname) =				\
+{									\
+	.name		= SYSMMU_DEVNAME_BASE,				\
+	.id		= devid,					\
+	.dev		= {						\
+		.dma_mask		= &exynos_sysmmu_dma_mask,	\
+		.coherent_dma_mask	= DMA_BIT_MASK(32),		\
+		.platform_data		= &platdata_##ipname,		\
+	},								\
+}
+
+SYSMMU_PLATFORM_DEVICE(mfc_l,	0);
+SYSMMU_PLATFORM_DEVICE(mfc_r,	1);
+SYSMMU_PLATFORM_DEVICE(tv,	2);
+SYSMMU_PLATFORM_DEVICE(jpeg,	3);
+SYSMMU_PLATFORM_DEVICE(rot,	4);
+SYSMMU_PLATFORM_DEVICE(fimc0,	5); /* fimc* and gsc* exist exclusively */
+SYSMMU_PLATFORM_DEVICE(fimc1,	6);
+SYSMMU_PLATFORM_DEVICE(fimc2,	7);
+SYSMMU_PLATFORM_DEVICE(fimc3,	8);
+SYSMMU_PLATFORM_DEVICE(gsc0,	5);
+SYSMMU_PLATFORM_DEVICE(gsc1,	6);
+SYSMMU_PLATFORM_DEVICE(gsc2,	7);
+SYSMMU_PLATFORM_DEVICE(gsc3,	8);
+SYSMMU_PLATFORM_DEVICE(isp,	9);
+SYSMMU_PLATFORM_DEVICE(fimd0,	10);
+SYSMMU_PLATFORM_DEVICE(fimd1,	11);
+SYSMMU_PLATFORM_DEVICE(camif0,	12);
+SYSMMU_PLATFORM_DEVICE(camif1,	13);
+SYSMMU_PLATFORM_DEVICE(2d,	14);
+
+#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
+
+#define SYSMMU_RESOURCE(core, ipname)					\
+	static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
+
+#define DEFINE_SYSMMU_RESOURCE(core, mem, irq)				\
+	DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem),	\
+	DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
+
+#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq)			\
+	SYSMMU_RESOURCE(core, ipname) {					\
+		DEFINE_SYSMMU_RESOURCE(core, mem, irq)			\
+	}
 
-struct platform_device exynos4_device_sysmmu = {
-	.name		= "s5p-sysmmu",
-	.id		= 32,
-	.num_resources	= ARRAY_SIZE(exynos4_sysmmu_resource),
-	.resource	= exynos4_sysmmu_resource,
+struct sysmmu_resource_map {
+	struct platform_device *pdev;
+	struct resource *res;
+	u32 rnum;
+	struct device *pdd;
+	char *clocknames;
 };
-EXPORT_SYMBOL(exynos4_device_sysmmu);
 
-static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
-void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
-{
-	sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
-	if (IS_ERR(sysmmu_clk[ips]))
-		sysmmu_clk[ips] = NULL;
-	else
-		clk_put(sysmmu_clk[ips]);
+#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) {		\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME,				\
 }
 
-void sysmmu_clk_enable(sysmmu_ips ips)
-{
-	if (sysmmu_clk[ips])
-		clk_enable(sysmmu_clk[ips]);
+#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) {	\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,		\
+}
+
+#ifdef CONFIG_EXYNOS_DEV_PD
+#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) {		\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME,				\
+	.pdd = &exynos##core##_device_pd[pd].dev,			\
+}
+
+#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
+	.pdev = &SYSMMU_PLATDEV(ipname),				\
+	.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname),		\
+	.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
+	.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2,		\
+	.pdd = &exynos##core##_device_pd[pd].dev,			\
 }
+#else
+#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd)		\
+		SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
+#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata)	\
+		SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
+
+#endif /* CONFIG_EXYNOS_DEV_PD */
+
+#ifdef CONFIG_ARCH_EXYNOS4
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0,	FIMC0,	FIMC0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1,	FIMC1,	FIMC1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2,	FIMC2,	FIMC2);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3,	FIMC3,	FIMC3);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg,	JPEG,	JPEG);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d,	G2D,	2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv,	TV,	TV_M0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp,	2D_ACP,	2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot,	ROTATOR, ROTATOR);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0,	FIMD0,	LCD0_M0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1,	FIMD1,	LCD1_M1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0,	FIMC_LITE0, FIMC_LITE0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1,	FIMC_LITE1, FIMC_LITE1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r,	MFC_R,	MFC_M0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l,	MFC_L,	MFC_M1);
+SYSMMU_RESOURCE(EXYNOS4, isp) {
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc0,	fimc0,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc1,	fimc1,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc2,	fimc2,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimc3,	fimc3,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, tv,	tv,	PD_TV),
+	SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r,	mfc_r,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l,	mfc_l,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_PD(4, rot,	rot,	PD_LCD0),
+	SYSMMU_RESOURCE_MAPPING_PD(4, jpeg,	jpeg,	PD_CAM),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimd0,	fimd0,	PD_LCD0),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING_PD(4, 2d,	2d,	PD_LCD0),
+	SYSMMU_RESOURCE_MAPPING_PD(4, fimd1,	fimd1,	PD_LCD1),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING(4,	2d,	2d_acp),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	camif0, flite0,	PD_ISP),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	camif1, flite1,	PD_ISP),
+	SYSMMU_RESOURCE_MAPPING_PD(4,	isp,	isp,	PD_ISP),
+};
+#endif /* CONFIG_ARCH_EXYNOS4 */
 
-void sysmmu_clk_disable(sysmmu_ips ips)
+#ifdef CONFIG_ARCH_EXYNOS5
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg,	JPEG,	JPEG);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1,	FIMD1,	FIMD1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d,	2D,	2D);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot,	ROTATOR, ROTATOR);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv,	TV,	TV);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0,	LITE0,	LITE0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1,	LITE1,	LITE1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0,	GSC0,	GSC0);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1,	GSC1,	GSC1);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2,	GSC2,	GSC2);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3,	GSC3,	GSC3);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r,	MFC_R,	MFC_R);
+SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l,	MFC_L,	MFC_L);
+SYSMMU_RESOURCE(EXYNOS5, isp) {
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5,	ODC, ODC),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
+	DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
+};
+
+static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
+	SYSMMU_RESOURCE_MAPPING(5,	jpeg,	jpeg),
+	SYSMMU_RESOURCE_MAPPING(5,	fimd1,	fimd1),
+	SYSMMU_RESOURCE_MAPPING(5,	2d,	2d),
+	SYSMMU_RESOURCE_MAPPING(5,	rot,	rot),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	tv,	tv,	PD_DISP1),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	camif0,	flite0,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	camif1,	flite1,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc0,	gsc0,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc1,	gsc1,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc2,	gsc2,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	gsc3,	gsc3,	PD_GSCL),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	mfc_r,	mfc_r,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_PD(5,	mfc_l,	mfc_l,	PD_MFC),
+	SYSMMU_RESOURCE_MAPPING_MCPD(5,	isp,	isp,	PD_ISP, mc_platdata),
+};
+#endif /* CONFIG_ARCH_EXYNOS5 */
+
+static int __init init_sysmmu_platform_device(void)
 {
-	if (sysmmu_clk[ips])
-		clk_disable(sysmmu_clk[ips]);
+	int i, j;
+	struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
+	int nmap[2] = {0, 0};
+
+#ifdef CONFIG_ARCH_EXYNOS5
+	if (soc_is_exynos5250()) {
+		resmap[0] = sysmmu_resmap5;
+		nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
+		nmap[1] = 0;
+	}
+#endif
+
+#ifdef CONFIG_ARCH_EXYNOS4
+	if (resmap[0] == NULL) {
+		resmap[0] = sysmmu_resmap4;
+		nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
+	}
+
+	if (soc_is_exynos4210()) {
+		resmap[1] = sysmmu_resmap4210;
+		nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
+	}
+
+	if (soc_is_exynos4412() || soc_is_exynos4212()) {
+		resmap[1] = sysmmu_resmap4212;
+		nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
+	}
+#endif
+
+	for (j = 0; j < 2; j++) {
+		for (i = 0; i < nmap[j]; i++) {
+			struct sysmmu_resource_map *map;
+			struct sysmmu_platform_data *platdata;
+
+			map = &resmap[j][i];
+
+			map->pdev->dev.parent = map->pdd;
+
+			platdata = map->pdev->dev.platform_data;
+			platdata->clockname = map->clocknames;
+
+			if (platform_device_add_resources(map->pdev, map->res,
+								map->rnum)) {
+				pr_err("%s: Failed to add device resources for "
+						"%s.%d\n", __func__,
+						map->pdev->name, map->pdev->id);
+				continue;
+			}
+
+			if (platform_device_register(map->pdev)) {
+				pr_err("%s: Failed to register %s.%d\n",
+					__func__, map->pdev->name,
+						map->pdev->id);
+			}
+		}
+	}
+
+	return 0;
 }
+arch_initcall(init_sysmmu_platform_device);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 9bee853..f140e1a 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -154,6 +154,13 @@
 #define EXYNOS4_IRQ_SYSMMU_MFC_M1_0	COMBINER_IRQ(5, 6)
 #define EXYNOS4_IRQ_SYSMMU_PCIE_0	COMBINER_IRQ(5, 7)
 
+#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0	COMBINER_IRQ(16, 0)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0	COMBINER_IRQ(16, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0	COMBINER_IRQ(16, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0	COMBINER_IRQ(16, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0	COMBINER_IRQ(16, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0	COMBINER_IRQ(16, 5)
+
 #define EXYNOS4_IRQ_FIMD0_FIFO		COMBINER_IRQ(11, 0)
 #define EXYNOS4_IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
 #define EXYNOS4_IRQ_FIMD0_SYSTEM	COMBINER_IRQ(11, 2)
@@ -218,24 +225,6 @@
 #define IRQ_KEYPAD			EXYNOS4_IRQ_KEYPAD
 #define IRQ_PMU				EXYNOS4_IRQ_PMU
 
-#define IRQ_SYSMMU_MDMA0_0		EXYNOS4_IRQ_SYSMMU_MDMA0_0
-#define IRQ_SYSMMU_SSS_0                EXYNOS4_IRQ_SYSMMU_SSS_0
-#define IRQ_SYSMMU_FIMC0_0              EXYNOS4_IRQ_SYSMMU_FIMC0_0
-#define IRQ_SYSMMU_FIMC1_0              EXYNOS4_IRQ_SYSMMU_FIMC1_0
-#define IRQ_SYSMMU_FIMC2_0              EXYNOS4_IRQ_SYSMMU_FIMC2_0
-#define IRQ_SYSMMU_FIMC3_0              EXYNOS4_IRQ_SYSMMU_FIMC3_0
-#define IRQ_SYSMMU_JPEG_0               EXYNOS4_IRQ_SYSMMU_JPEG_0
-#define IRQ_SYSMMU_2D_0                 EXYNOS4_IRQ_SYSMMU_2D_0
-
-#define IRQ_SYSMMU_ROTATOR_0            EXYNOS4_IRQ_SYSMMU_ROTATOR_0
-#define IRQ_SYSMMU_MDMA1_0              EXYNOS4_IRQ_SYSMMU_MDMA1_0
-#define IRQ_SYSMMU_LCD0_M0_0            EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
-#define IRQ_SYSMMU_LCD1_M1_0            EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
-#define IRQ_SYSMMU_TV_M0_0              EXYNOS4_IRQ_SYSMMU_TV_M0_0
-#define IRQ_SYSMMU_MFC_M0_0             EXYNOS4_IRQ_SYSMMU_MFC_M0_0
-#define IRQ_SYSMMU_MFC_M1_0             EXYNOS4_IRQ_SYSMMU_MFC_M1_0
-#define IRQ_SYSMMU_PCIE_0               EXYNOS4_IRQ_SYSMMU_PCIE_0
-
 #define IRQ_FIMD0_FIFO			EXYNOS4_IRQ_FIMD0_FIFO
 #define IRQ_FIMD0_VSYNC			EXYNOS4_IRQ_FIMD0_VSYNC
 #define IRQ_FIMD0_SYSTEM		EXYNOS4_IRQ_FIMD0_SYSTEM
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 024d38f..69f2ea6 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -91,6 +91,7 @@
 #define EXYNOS4_PA_PDMA1		0x12690000
 
 #define EXYNOS4_PA_SYSMMU_MDMA		0x10A40000
+#define EXYNOS4_PA_SYSMMU_2D_ACP	0x10A40000
 #define EXYNOS4_PA_SYSMMU_SSS		0x10A50000
 #define EXYNOS4_PA_SYSMMU_FIMC0		0x11A20000
 #define EXYNOS4_PA_SYSMMU_FIMC1		0x11A30000
@@ -99,6 +100,12 @@
 #define EXYNOS4_PA_SYSMMU_JPEG		0x11A60000
 #define EXYNOS4_PA_SYSMMU_FIMD0		0x11E20000
 #define EXYNOS4_PA_SYSMMU_FIMD1		0x12220000
+#define EXYNOS4_PA_SYSMMU_FIMC_ISP	0x12260000
+#define EXYNOS4_PA_SYSMMU_FIMC_DRC	0x12270000
+#define EXYNOS4_PA_SYSMMU_FIMC_FD	0x122A0000
+#define EXYNOS4_PA_SYSMMU_ISPCPU	0x122B0000
+#define EXYNOS4_PA_SYSMMU_FIMC_LITE0	0x123B0000
+#define EXYNOS4_PA_SYSMMU_FIMC_LITE1	0x123C0000
 #define EXYNOS4_PA_SYSMMU_PCIe		0x12620000
 #define EXYNOS4_PA_SYSMMU_G2D		0x12A20000
 #define EXYNOS4_PA_SYSMMU_ROTATOR	0x12A30000
@@ -106,6 +113,37 @@
 #define EXYNOS4_PA_SYSMMU_TV		0x12E20000
 #define EXYNOS4_PA_SYSMMU_MFC_L		0x13620000
 #define EXYNOS4_PA_SYSMMU_MFC_R		0x13630000
+
+#define EXYNOS5_PA_SYSMMU_MDMA1		0x10A40000
+#define EXYNOS5_PA_SYSMMU_SSS		0x10A50000
+#define EXYNOS5_PA_SYSMMU_2D		0x10A60000
+#define EXYNOS5_PA_SYSMMU_MFC_L		0x11200000
+#define EXYNOS5_PA_SYSMMU_MFC_R		0x11210000
+#define EXYNOS5_PA_SYSMMU_ROTATOR	0x11D40000
+#define EXYNOS5_PA_SYSMMU_MDMA2		0x11D50000
+#define EXYNOS5_PA_SYSMMU_JPEG		0x11F20000
+#define EXYNOS5_PA_SYSMMU_IOP		0x12360000
+#define EXYNOS5_PA_SYSMMU_RTIC		0x12370000
+#define EXYNOS5_PA_SYSMMU_GPS		0x12630000
+#define EXYNOS5_PA_SYSMMU_ISP		0x13260000
+#define EXYNOS5_PA_SYSMMU_DRC		0x12370000
+#define EXYNOS5_PA_SYSMMU_SCALERC	0x13280000
+#define EXYNOS5_PA_SYSMMU_SCALERP	0x13290000
+#define EXYNOS5_PA_SYSMMU_FD		0x132A0000
+#define EXYNOS5_PA_SYSMMU_ISPCPU	0x132B0000
+#define EXYNOS5_PA_SYSMMU_ODC		0x132C0000
+#define EXYNOS5_PA_SYSMMU_DIS0		0x132D0000
+#define EXYNOS5_PA_SYSMMU_DIS1		0x132E0000
+#define EXYNOS5_PA_SYSMMU_3DNR		0x132F0000
+#define EXYNOS5_PA_SYSMMU_LITE0		0x13C40000
+#define EXYNOS5_PA_SYSMMU_LITE1		0x13C50000
+#define EXYNOS5_PA_SYSMMU_GSC0		0x13E80000
+#define EXYNOS5_PA_SYSMMU_GSC1		0x13E90000
+#define EXYNOS5_PA_SYSMMU_GSC2		0x13EA0000
+#define EXYNOS5_PA_SYSMMU_GSC3		0x13EB0000
+#define EXYNOS5_PA_SYSMMU_FIMD1		0x14640000
+#define EXYNOS5_PA_SYSMMU_TV		0x14650000
+
 #define EXYNOS4_PA_SPI0			0x13920000
 #define EXYNOS4_PA_SPI1			0x13930000
 #define EXYNOS4_PA_SPI2			0x13940000
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index e141c1f..7395236 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -135,6 +135,9 @@
 #define EXYNOS4_CLKGATE_SCLKCPU			EXYNOS_CLKREG(0x14800)
 #define EXYNOS4_CLKGATE_IP_CPU			EXYNOS_CLKREG(0x14900)
 
+#define EXYNOS4_CLKGATE_IP_ISP0			EXYNOS_CLKREG(0x18800)
+#define EXYNOS4_CLKGATE_IP_ISP1			EXYNOS_CLKREG(0x18804)
+
 #define EXYNOS4_APLL_LOCKTIME			(0x1C20)	/* 300us */
 
 #define EXYNOS4_APLLCON0_ENABLE_SHIFT		(31)
@@ -297,6 +300,8 @@
 #define EXYNOS5_CLKDIV_PERIC0			EXYNOS_CLKREG(0x10558)
 
 #define EXYNOS5_CLKGATE_IP_ACP			EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_ISP0			EXYNOS_CLKREG(0x0C800)
+#define EXYNOS5_CLKGATE_IP_ISP1			EXYNOS_CLKREG(0x0C804)
 #define EXYNOS5_CLKGATE_IP_GSCL			EXYNOS_CLKREG(0x10920)
 #define EXYNOS5_CLKGATE_IP_DISP1		EXYNOS_CLKREG(0x10928)
 #define EXYNOS5_CLKGATE_IP_MFC			EXYNOS_CLKREG(0x1092C)
diff --git a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
deleted file mode 100644
index 68ff6ad..0000000
--- a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
- *
- * EXYNOS4 - System MMU register
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_SYSMMU_H
-#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
-
-#define S5P_MMU_CTRL			0x000
-#define S5P_MMU_CFG			0x004
-#define S5P_MMU_STATUS			0x008
-#define S5P_MMU_FLUSH			0x00C
-#define S5P_PT_BASE_ADDR		0x014
-#define S5P_INT_STATUS			0x018
-#define S5P_INT_CLEAR			0x01C
-#define S5P_PAGE_FAULT_ADDR		0x024
-#define S5P_AW_FAULT_ADDR		0x028
-#define S5P_AR_FAULT_ADDR		0x02C
-#define S5P_DEFAULT_SLAVE_ADDR		0x030
-
-#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
index 6a5fbb5..998daf2 100644
--- a/arch/arm/mach-exynos/include/mach/sysmmu.h
+++ b/arch/arm/mach-exynos/include/mach/sysmmu.h
@@ -1,46 +1,66 @@
-/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *		http://www.samsung.com
  *
- * Samsung sysmmu driver for EXYNOS4
+ * EXYNOS - System MMU support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_ARCH_SYSMMU_H
-#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
-
-enum exynos4_sysmmu_ips {
-	SYSMMU_MDMA,
-	SYSMMU_SSS,
-	SYSMMU_FIMC0,
-	SYSMMU_FIMC1,
-	SYSMMU_FIMC2,
-	SYSMMU_FIMC3,
-	SYSMMU_JPEG,
-	SYSMMU_FIMD0,
-	SYSMMU_FIMD1,
-	SYSMMU_PCIe,
-	SYSMMU_G2D,
-	SYSMMU_ROTATOR,
-	SYSMMU_MDMA2,
-	SYSMMU_TV,
-	SYSMMU_MFC_L,
-	SYSMMU_MFC_R,
-	EXYNOS4_SYSMMU_TOTAL_IPNUM,
+ */
+
+#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
+#define _ARM_MACH_EXYNOS_SYSMMU_H_
+
+struct sysmmu_platform_data {
+	char *dbgname;
+	/* comma(,) separated list of clock names for clock gating */
+	char *clockname;
 };
 
-#define S5P_SYSMMU_TOTAL_IPNUM		EXYNOS4_SYSMMU_TOTAL_IPNUM
+#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
+
+#define SYSMMU_CLOCK_NAME "sysmmu"
+#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
+
+#ifdef CONFIG_EXYNOS_DEV_SYSMMU
+#include <linux/device.h>
+struct platform_device;
+
+#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
+
+extern struct platform_device SYSMMU_PLATDEV(mfc_l);
+extern struct platform_device SYSMMU_PLATDEV(mfc_r);
+extern struct platform_device SYSMMU_PLATDEV(tv);
+extern struct platform_device SYSMMU_PLATDEV(jpeg);
+extern struct platform_device SYSMMU_PLATDEV(rot);
+extern struct platform_device SYSMMU_PLATDEV(fimc0);
+extern struct platform_device SYSMMU_PLATDEV(fimc1);
+extern struct platform_device SYSMMU_PLATDEV(fimc2);
+extern struct platform_device SYSMMU_PLATDEV(fimc3);
+extern struct platform_device SYSMMU_PLATDEV(gsc0);
+extern struct platform_device SYSMMU_PLATDEV(gsc1);
+extern struct platform_device SYSMMU_PLATDEV(gsc2);
+extern struct platform_device SYSMMU_PLATDEV(gsc3);
+extern struct platform_device SYSMMU_PLATDEV(isp);
+extern struct platform_device SYSMMU_PLATDEV(fimd0);
+extern struct platform_device SYSMMU_PLATDEV(fimd1);
+extern struct platform_device SYSMMU_PLATDEV(camif0);
+extern struct platform_device SYSMMU_PLATDEV(camif1);
+extern struct platform_device SYSMMU_PLATDEV(2d);
 
-extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
+#ifdef CONFIG_IOMMU_API
+static inline void platform_set_sysmmu(
+				struct device *sysmmu, struct device *dev)
+{
+	dev->archdata.iommu = sysmmu;
+}
+#endif
 
-typedef enum exynos4_sysmmu_ips sysmmu_ips;
+#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
+#define platform_set_sysmmu(dev, sysmmu) do { } while (0)
+#endif
 
-void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
-void sysmmu_clk_enable(sysmmu_ips ips);
-void sysmmu_clk_disable(sysmmu_ips ips);
+#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
 
-#endif /* __ASM_ARM_ARCH_SYSMMU_H */
+#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index a1e7007..6ab171c 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -154,7 +154,6 @@ static struct platform_device *armlex4210_devices[] __initdata = {
 	&s3c_device_hsmmc3,
 	&s3c_device_rtc,
 	&s3c_device_wdt,
-	&exynos4_device_sysmmu,
 	&samsung_asoc_dma,
 	&armlex4210_smsc911x,
 	&exynos4_device_ahci,
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index f08529f..f7b6e12 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -277,7 +277,6 @@ static struct platform_device *smdkv310_devices[] __initdata = {
 	&s5p_device_mfc_l,
 	&s5p_device_mfc_r,
 	&exynos4_device_spdif,
-	&exynos4_device_sysmmu,
 	&samsung_asoc_dma,
 	&samsung_asoc_idma,
 	&s5p_device_fimd0,
-- 
1.7.1



From nicolas.ferre at atmel.com  Thu Mar 15 04:38:10 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 09:38:10 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <4F22DEF2.5000807@ti.com>
References: <4F22DEF2.5000807@ti.com>
Message-ID: <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>

Add some basic helpers to retrieve a DMA controller device_node and the
DMA request specifications. By making DMA controllers register a generic
translation function, we allow the management of any type of DMA requests
specification.
The void * output of an of_dma_xlate() function that will be implemented
by the DMA controller can carry any type of "dma-request" argument.

The DMA client will search its associated DMA controller in the list and
call the registered of_dam_xlate() function to retrieve the request values.

One simple xlate function is provided for the "single number" type of
request binding.

This implementation is independent from dmaengine so it can also be used
by legacy drivers.

For legacy reason another API will export the DMA request number into a
Linux resource of type IORESOURCE_DMA.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Cc: Stephen Warren <swarren at nvidia.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Rob Herring <rob.herring at calxeda.com>
---
 Documentation/devicetree/bindings/dma/dma.txt |   45 +++++
 drivers/of/Kconfig                            |    5 +
 drivers/of/Makefile                           |    1 +
 drivers/of/dma.c                              |  260 +++++++++++++++++++++++++
 include/linux/of_dma.h                        |   67 +++++++
 5 files changed, 378 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/dma.txt
 create mode 100644 drivers/of/dma.c
 create mode 100644 include/linux/of_dma.h

diff --git a/Documentation/devicetree/bindings/dma/dma.txt b/Documentation/devicetree/bindings/dma/dma.txt
new file mode 100644
index 0000000..c49e98d
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/dma.txt
@@ -0,0 +1,45 @@
+* Generic DMA Controller and DMA request bindings
+
+Generic binding to provide a way for a driver to retrieve the
+DMA request line that goes from an IP to a DMA controller.
+
+
+* DMA controller
+
+Required property:
+    - #dma-cells: Number of cells for each DMA line.
+
+
+Example:
+
+	sdma: dma-controller at 48000000 {
+		compatible = "ti,sdma-omap4"
+		reg = <0x48000000 0x1000>;
+		interrupts = <12>;
+		#dma-cells = <1>;
+	};
+
+
+
+* DMA client
+
+Client drivers should specify the DMA request property using a phandle to
+the controller. If needed, the DMA request identity on that controller is then
+added followed by optional request specifications.
+
+Required property:
+    - dma-request: List of phandle + dma-request + request specifications,
+      one group per request "line".
+Optional property:
+    - dma-request-names: list of strings in the same order as the dma-request
+      in the dma-request property.
+
+
+Example:
+
+	i2c1: i2c at 1 {
+		...
+		dma-request = <&sdma 2 &sdma 3>;
+		dma-request-names = "tx", "rx";
+		...
+	};
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index 268163d..7d1f06b 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -90,4 +90,9 @@ config OF_PCI_IRQ
 	help
 	  OpenFirmware PCI IRQ routing helpers
 
+config OF_DMA
+	def_bool y
+	help
+	  Device Tree DMA routing helpers
+
 endmenu # OF
diff --git a/drivers/of/Makefile b/drivers/of/Makefile
index a73f5a5..6eb50c6 100644
--- a/drivers/of/Makefile
+++ b/drivers/of/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_OF_SELFTEST) += selftest.o
 obj-$(CONFIG_OF_MDIO)	+= of_mdio.o
 obj-$(CONFIG_OF_PCI)	+= of_pci.o
 obj-$(CONFIG_OF_PCI_IRQ)  += of_pci_irq.o
+obj-$(CONFIG_OF_DMA)	+= dma.o
diff --git a/drivers/of/dma.c b/drivers/of/dma.c
new file mode 100644
index 0000000..3315844
--- /dev/null
+++ b/drivers/of/dma.c
@@ -0,0 +1,260 @@
+/*
+ * Device tree helpers for DMA request / controller
+ *
+ * Based on of_gpio.c
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/rculist.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+
+static LIST_HEAD(of_dma_list);
+
+struct of_dma {
+	struct list_head of_dma_controllers;
+	struct device_node *of_node;
+	int of_dma_n_cells;
+	int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
+};
+
+/**
+ * of_dma_find_controller() - Find a DMA controller in DT DMA helpers list
+ * @np:		device node of DMA controller
+ */
+static struct of_dma *of_dma_find_controller(struct device_node *np)
+{
+	struct of_dma	*ofdma;
+
+	list_for_each_entry_rcu(ofdma, &of_dma_list, of_dma_controllers) {
+		if (ofdma->of_node == np)
+			return ofdma;
+	}
+
+	return NULL;
+}
+
+/**
+ * of_dma_controller_register() - Register a DMA controller to DT DMA helpers
+ * @np:			device node of DMA controller
+ * @of_dma_xlate:	generic translation function which converts a phandle
+ *			arguments list into a generic output value
+ *
+ * Returns 0 on success or appropriate errno value on error.
+ *
+ * If #dma-cells is not specified in DMA controller device tree node, we assume
+ * that the DMA controller phandle will come without argument.
+ *
+ * Allocated memory should be freed with appropriate of_dma_controller_free()
+ * call.
+ */
+int of_dma_controller_register(struct device_node *np,
+			int (*of_dma_xlate)(struct of_phandle_args *, void *))
+{
+	struct of_dma	*ofdma;
+	const __be32	*nbcells;
+
+	if (!np || !of_dma_xlate) {
+		pr_err("%s: not enough information provided\n", __func__);
+		return -EINVAL;
+	}
+
+	ofdma = kzalloc(sizeof(*ofdma), GFP_KERNEL);
+	if (!ofdma)
+		return -ENOMEM;
+
+	nbcells = of_get_property(np, "#dma-cells", NULL);
+	if (!nbcells)
+		/*
+		 * no #dma-cells properties: assume no argument to
+		 * dma-request property on slave side
+		 */
+		ofdma->of_dma_n_cells = 0;
+	else
+		ofdma->of_dma_n_cells = be32_to_cpup(nbcells);
+
+	ofdma->of_node = np;
+	ofdma->of_dma_xlate = of_dma_xlate;
+
+	/* Now queue of_dma controller structure in list */
+	list_add_tail_rcu(&ofdma->of_dma_controllers, &of_dma_list);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(of_dma_controller_register);
+
+/**
+ * of_dma_controller_free() - Remove a DMA controller from DT DMA helpers list
+ * @np:		device node of DMA controller
+ *
+ * Memory allocated by of_dma_controller_register() is freed here.
+ */
+void of_dma_controller_free(struct device_node *np)
+{
+	struct of_dma	*ofdma;
+
+	ofdma = of_dma_find_controller(np);
+	if (ofdma) {
+		list_del_rcu(&ofdma->of_dma_controllers);
+		kfree(ofdma);
+	}
+}
+EXPORT_SYMBOL_GPL(of_dma_controller_free);
+
+/**
+ * of_get_dma_request() - Get the associated DMA request data
+ * @np:		device node to get DMA request from
+ * @index:	index of the DMA request
+ * @out_data:	a output that can be filled in by the of_dma_xlate() function
+ *
+ * Returns return value of of_dma_xlate() and fills out_data (if provided).
+ * On error returns the appropriate errno value.
+ */
+int of_get_dma_request(struct device_node *np, int index,
+		       void *out_data)
+{
+	struct of_phandle_args	dma_spec;
+	struct of_dma		*ofdma;
+	int			ret;
+
+	ret = of_parse_phandle_with_args(np, "dma-request", "#dma-cells",
+					 index, &dma_spec);
+	if (ret) {
+		pr_err("%s: can't parse dma property\n", np->full_name);
+		goto err0;
+	}
+
+	if (list_empty(&of_dma_list)) {
+		pr_debug("%s: empty DMA controller list\n",
+			 np->full_name);
+		ret = -ENOENT;
+		goto err1;
+	}
+
+	ofdma = of_dma_find_controller(dma_spec.np);
+	if (!ofdma) {
+		pr_debug("%s: DMA controller %s isn't registered\n",
+			 np->full_name, dma_spec.np->full_name);
+		ret = -ENODEV;
+		goto err1;
+	}
+
+	if (dma_spec.args_count != ofdma->of_dma_n_cells) {
+		pr_debug("%s: wrong #dma-cells for %s\n",
+			 np->full_name, dma_spec.np->full_name);
+		ret = -EINVAL;
+		goto err1;
+	}
+
+	ret = ofdma->of_dma_xlate(&dma_spec, out_data);
+
+err1:
+	of_node_put(dma_spec.np);
+err0:
+	pr_debug("%s exited with status %d\n", __func__, ret);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(of_get_dma_request);
+
+/**
+ * of_dma_xlate_onenumbercell() - Generic DMA xlate for direct one cell bindings
+ *
+ * Device Tree DMA translation function which works with one cell bindings
+ * where the cell values map directly to the hardware request number understood
+ * by the DMA controller.
+ */
+int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec, void *dma_req)
+{
+	if (!dma_spec)
+		return -EINVAL;
+	if (WARN_ON(dma_spec->args_count != 1))
+		return -EINVAL;
+	*(int *)dma_req = dma_spec->args[0];
+	return 0;
+}
+EXPORT_SYMBOL_GPL(of_dma_xlate_onenumbercell);
+
+/**
+ * of_dma_count - Count DMA requests for a device
+ * @np:		device node to count DMAs for
+ *
+ * The function returns the count of DMA requests specified for a node.
+ *
+ * Note that the empty DMA specifiers counts too. For example,
+ *
+ * dma-request = <0
+ *                &sdma 1
+ *                0
+ *                &sdma 3>;
+ *
+ * defines four DMAs (so this function will return 4), two of which
+ * are not specified.
+ */
+unsigned int of_dma_count(struct device_node *np)
+{
+	unsigned int cnt = 0;
+
+	do {
+		int ret;
+
+		ret = of_parse_phandle_with_args(np, "dma-request",
+						 "#dma-cells", cnt, NULL);
+		/* A hole in the dma-request = <> counts anyway. */
+		if (ret < 0 && ret != -EEXIST)
+			break;
+	} while (++cnt);
+
+	return cnt;
+}
+EXPORT_SYMBOL_GPL(of_dma_count);
+
+/**
+ * of_dma_to_resource - Decode a node's DMA and return it as a resource
+ * @dev: pointer to device tree node
+ * @index: zero-based index of the DMA request
+ * @r: pointer to resource structure to return result into.
+ *
+ * Using a resource to export a DMA request number to a driver should
+ * be used only for legacy purpose and on system when only one DMA controller
+ * is present.
+ * The proper and only scalable way is to use the native of_get_dma_request API
+ * in order retrieve both the DMA controller device node and the DMA request
+ * line for that controller.
+ */
+int of_dma_to_resource(struct device_node *dev, int index, struct resource *r)
+{
+	const char *name = NULL;
+	int dma;
+	int ret;
+
+	if (!r)
+		return -EINVAL;
+
+	ret = of_get_dma_request(dev, index, &dma);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * Get optional "dma-request-names" property to add a name
+	 * to the resource.
+	 */
+	of_property_read_string_index(dev, "dma-request-names", index,
+				      &name);
+
+	r->start = dma;
+	r->end = dma;
+	r->flags = IORESOURCE_DMA;
+	r->name = name ? name : dev->full_name;
+
+	return dma;
+}
+EXPORT_SYMBOL_GPL(of_dma_to_resource);
diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
new file mode 100644
index 0000000..c6147bb
--- /dev/null
+++ b/include/linux/of_dma.h
@@ -0,0 +1,67 @@
+/*
+ * OF helpers for DMA request / controller
+ *
+ * Based on of_gpio.h
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_OF_DMA_H
+#define __LINUX_OF_DMA_H
+
+#include <linux/of.h>
+
+struct device_node;
+
+#ifdef CONFIG_OF_DMA
+
+extern int of_dma_controller_register(struct device_node *np,
+			int (*of_dma_xlate)(struct of_phandle_args *, void *));
+extern void of_dma_controller_free(struct device_node *np);
+extern int of_get_dma_request(struct device_node *np, int index,
+			      void *out_data);
+extern unsigned int of_dma_count(struct device_node *np);
+extern int of_dma_to_resource(struct device_node *dev, int index,
+			      struct resource *r);
+
+extern int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
+				      void *dma_req);
+#else /* CONFIG_OF_DMA */
+
+static int of_dma_controller_register(struct device_node *np,
+			int (*of_dma_xlate)(struct of_phandle_args *, void *))
+{
+	return -ENOSYS;
+}
+
+static void of_dma_controller_free(struct device_node *np) {}
+
+extern int of_get_dma_request(struct device_node *np, int index,
+			      void *out_data)
+{
+	return -ENOSYS;
+}
+
+static inline unsigned int of_dma_count(struct device_node *np)
+{
+	return 0;
+}
+
+static int of_dma_to_resource(struct device_node *dev, int index,
+			      struct resource *r);
+{
+	return -ENOSYS;
+}
+
+static int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
+				      void *dma_req)
+{
+	return -ENOSYS;
+}
+#endif /* CONFIG_OF_DMA */
+
+#endif /* __LINUX_OF_DMA_H */
-- 
1.7.9



From jg1.han at samsung.com  Thu Mar 15 04:39:58 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Thu, 15 Mar 2012 17:39:58 +0900
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com> <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
Message-ID: <000001cd0287$34ae4890$9e0ad9b0$%han@samsung.com>



> -----Original Message-----
> From: Darius Augulis [mailto:augulis.darius at gmail.com]
> Sent: Thursday, March 15, 2012 5:27 PM
> To: Jingoo Han
> Cc: Thomas Abraham; linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-
> kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; kgene.kim at samsung.com; ben-
> linux at fluff.org; patches at linaro.org; Kyungmin Park; JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark
> Brown; Peter Korsgaard; Maurus Cuelenaere
> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> 
> On Thu, Mar 15, 2012 at 10:10 AM, Jingoo Han <jg1.han at samsung.com> wrote:
> 
> >> There is single board - mini6410 (or real6410) and it's name doesn't
> >> depend on connected LCD size.
> >> We know, that this board is available with different sizes of LCD and
> >> currently we have in kernel support for both sizes.
> >> It might be so, that it's implemented not in perfect way, but it was
> >> accepted and at least it's working.
> >
> >
> > I don't think so.
> > You argues that the wrong code should not be removed because it was accepted and at least it's working.
> > It is just wrong usage, which can just work.
> > Moreover, your code will make the problem, when 2~5 windows of FIMD IP are used.
> 
> Could please explain that? How does LCD feature selection for mini6410
> and real6410 break that?
> Timing for different sizes of LCD is located in two statically
> allocated structures which are used at board init time depending on
> kernel param line.
> Data from one of these structures is copied to s3c-fb platform data
> dynamically by board init code. Why it's a problem? What changes if
> platform data isn't rewritten dynamically?
> 
> > So, your code can be removed.
> 
> I don't think so. It does not break anything yet. One who make
> changes, should ensure backwards compatibility, at least talking about
> functionality and hardware (LCD) support, which was added few months
> ago. Remember, we talk about kernel parameters line - now it lets
> bootloader to select correct LCD size. After your changes, board with
> 7" LCD wont show anything.

OK, your code work, although the usage is wrong.

Thomas, can you keep backwards compatibility?


> 
> Darius A.



From arnd at arndb.de  Thu Mar 15 04:01:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 08:01:12 +0000
Subject: [GIT PULL] ARM: OMAP: i2c, gpio, spi,
 regulator and mmc DTS updates
In-Reply-To: <20120315004638.GW12083@atomide.com>
References: <4F612C29.40608@ti.com> <20120315004638.GW12083@atomide.com>
Message-ID: <201203150801.13183.arnd@arndb.de>

On Thursday 15 March 2012, Tony Lindgren wrote:
> * Cousson, Benoit <b-cousson at ti.com> [120314 16:41]:
> > Hi Tony,
> > 
> > Here are the remaining DTS patches for 3.4.
> > 
> > On top of the previous pull request, I just added the MMC DTS since the driver adaptation just got queued.
> > 
> > It will be still be good to have that for 3.4 if possible, otherwise we will
> > have a bunch of drivers DT adapted but no DTS file to use them :-(
> 
> This might be doable as a follow-up patch series at the end
> of the merge window or at -rc1 when the related driver changes
> have been merged.
> 
> Arnd and Olof, what do you guys think?

I'll have to look at the patches more closely, but from the diffstat it definitely
looks ok for a later merge once the driver is in. If you can rebase the branch on
top of the mmc tree (or the merge of that tree with whatever else is needed), it
should give us a bisectable history and I can stick it into a late/* branch right
away.

	Arnd



From arnd at arndb.de  Thu Mar 15 04:40:42 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 08:40:42 +0000
Subject: [PATCH v4 03/10] pwm: Add device tree support
In-Reply-To: <1331740593-10807-4-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-4-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <201203150840.42659.arnd@arndb.de>

On Wednesday 14 March 2012, Thierry Reding wrote:
> This patch adds helpers to support device tree bindings for the generic
> PWM API. Device tree binding documentation for PWM controllers is also
> provided.
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> ---
> Changes in v4:
>   - add OF-specific code removed from patch 2
>   - make of_node_to_pwmchip() and of_pwm_simple_xlate() static
>   - rename of_get_named_pwm() to of_pwm_request(), return a struct
>     pwm_device, get rid of the now unused spec parameter and use the
>     device_node.name field as the PWM's name
>   - return a requested struct pwm_device from pwm_chip.of_xlate and
>     drop the now unused spec parameter
>   - move OF support code into drivers/pwm/core.c
>   - used deferred probing if a PWM chip is not available yet
> 
> Changes in v2:
>   - add device tree binding documentation
>   - add of_xlate to parse controller-specific PWM-specifier

Looks very cool now, and much simpler!

> diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
> index 6ea51dc..d47b8ee 100644
> --- a/drivers/of/Kconfig
> +++ b/drivers/of/Kconfig
> @@ -57,6 +57,12 @@ config OF_GPIO
>  	help
>  	  OpenFirmware GPIO accessors
>  
> +config OF_PWM
> +	def_bool y
> +	depends on PWM
> +	help
> +	  OpenFirmware PWM accessors
> +
>  config OF_I2C
>  	def_tristate I2C
>  	depends on I2C && !SPARC

You might want to remove this one now and just use CONFIG_OF in the driver,
unless there is  a reason to keep it here.

> +#ifdef CONFIG_OF_PWM
> +static struct pwm_chip *of_node_to_pwmchip(struct device_node *np)
> +{
> +	struct pwm_chip *chip;
> +
> +	mutex_lock(&pwm_lock);
> +
> +	list_for_each_entry(chip, &pwm_chips, list)
> +		if (chip->dev && chip->dev->of_node == np) {
> +			mutex_unlock(&pwm_lock);
> +			return chip;
> +		}
> +
> +	mutex_unlock(&pwm_lock);
> +
> +	return ERR_PTR(-EPROBE_DEFER);
> +}

EPROBE_DEFER doesn't exist yet in my kernel, and I wonder if it's actually
safe to be used this way, because it can result in arbitrary drivers using
this to be put on the defered probe list. It certainly sounds like the
right thing to do in the long run though.

> +#else
> +static inline void of_pwmchip_add(struct pwm_chip *pc)
> +{
> +}
> +
> +static inline void of_pwmchip_remove(struct pwm_chip *pc)
> +{
> +}
> +#endif /* CONFIG_OF_PWM */
> +
>  /**
>   * pwm_set_chip_data - set private chip data for a PWM
>   * @pwm: PWM device
> @@ -184,6 +254,7 @@ int pwmchip_add(struct pwm_chip *chip)
>  
>  	INIT_LIST_HEAD(&chip->list);
>  	list_add(&chip->list, &pwm_chips);
> +	of_pwmchip_add(chip);
>  
>  out:
>  	mutex_unlock(&pwm_lock);

You could express the same thing using 

	if (IS_ENABLED(CONFIG_OF_PWM))
		of_pwmchip_add(chip);

The advantage of this is that you always get compile coverage for the
entire file, but the function is automatically discarded by the
compiler when the condition is false at compile time. That obviously
doesn't work for exported functions.

> +#ifdef CONFIG_OF
> +/**
> + * of_pwm_request() - request a PWM via the PWM framework
> + * @np: device node to get the PWM from
> + * @propname: property name containing PWM specifier(s)
> + * @index: index of the PWM
> + *
> + * Returns the PWM device parsed from the phandle specified in the given
> + * property of a device tree node or NULL on failure. Values parsed from
> + * the device tree are stored in the returned PWM device object.
> + */
> +struct pwm_device *of_pwm_request(struct device_node *np,
> +				  const char *propname, int index)
> +{
> +	struct pwm_device *pwm = NULL;
> +	struct of_phandle_args args;
> +	struct pwm_chip *pc;
> +	int err;
> +
> +	err = of_parse_phandle_with_args(np, propname, "#pwm-cells", index,
> +					 &args);

Wow, I just looked up what of_parse_phandle_with_args() does and that is
extremely helpful indeed.

>  /*
> @@ -102,6 +104,12 @@ struct pwm_chip {
>  	unsigned int		npwm;
>  
>  	struct pwm_device	*pwms;
> +
> +#ifdef CONFIG_OF_PWM
> +	struct pwm_device *	(*of_xlate)(struct pwm_chip *pc,
> +					    const struct of_phandle_args *args);
> +	unsigned int		of_pwm_n_cells;
> +#endif
>  };
>  
>  int pwm_set_chip_data(struct pwm_device *pwm, void *data);

If you use IS_ENABLED() as I suggested above, this #ifdef will have to go
away, too, which is a very small size overhead.

	Arnd


From sr at denx.de  Thu Mar 15 04:41:02 2012
From: sr at denx.de (Stefan Roese)
Date: Thu, 15 Mar 2012 09:41:02 +0100
Subject: [PATCH v2] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <4F61A62A.3040501@st.com>
References: <1331737232-25477-1-git-send-email-sr@denx.de>
 <4F61A62A.3040501@st.com>
Message-ID: <201203150941.02822.sr@denx.de>

Hi Viresh,

On Thursday 15 March 2012 09:19:54 Viresh Kumar wrote:
> Hi Stefan,
> 
> Thanks for your patch. :)

You are welcome. :)
 
> I have looked carefully at the patch, regarding addresses and irq numbers,
> and they look fine. Just few minor comments below:
> 
> On 3/14/2012 8:30 PM, Stefan Roese wrote:
> > diff --git a/arch/arm/boot/dts/spear600.dtsi
> > b/arch/arm/boot/dts/spear600.dtsi
> > 
> > +       soc {
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +               compatible = "simple-bus";
> > +               ranges;
> > +
> > 
> > +
> > +               gmac0: ethernet at e0800000 {
> 
> There is no gmac1, so can name it gmac only.

I have no strong preference here. Not sure, what the common practice is. But I 
can remove the numbers on those single instance devices.
 
> > +                       compatible = "st,spear600-gmac";
> > +                       reg = <0xe0800000 0x8000>;
> > +                       interrupt-parent = <&vic1>;
> > +                       interrupts = <24 23>;
> > +                       interrupt-names = "macirq", "eth_wake_irq";
> > +                       mac-address = [000000000000]; /* Filled in by
> > U-Boot */ +               };
> > +
> > 
> > +               fsmc0: flash at d1800000 {
> 
> same.
> 
> > +                       status = "disabled";
> > +                       compatible = "st,spear600-fsmc-nand";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +                       reg = <0xd1800000 0x1000        /* FSMC Register
> > */ +                              0xd2000000 0x4000>;      /* NAND Base
> > */ +                       reg-names = "fsmc_regs", "nand_data";
> > +               };
> > +
> > +               smi0: flash at fc000000 {
> 
> same
> 
> > +                       status = "disabled";
> > +                       compatible = "st,spear600-smi";
> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +                       reg = <0xfc000000 0x1000>;
> > +                       interrupt-parent = <&vic1>;
> > +                       interrupts = <12>;
> > +               };
> > +
> > 
> > diff --git a/arch/arm/mach-spear6xx/spear600_evb.c
> > b/arch/arm/mach-spear6xx/spear600_evb.c index c6e4254..c4949aa 100644
> > --- a/arch/arm/mach-spear6xx/spear600_evb.c
> > +++ b/arch/arm/mach-spear6xx/spear600_evb.c
> > @@ -32,9 +32,6 @@ static void __init spear600_evb_init(void)
> > 
> >  {
> >  
> >         unsigned int i;
> 
> Why don't we remove the devices from arrays above, which are now
> supported by DT?

This is the non-DT file (spear600_evb.c). I wanted to preserve it, so that it 
still can be built. But thinking a bit more about it, the current mainline 
SPEAr600 port only supports UART and GPIO as peripheral devices. And this 
SPEAr600 DT patch also supports those and even more devices.

So why don't we make an even bigger "cut", and remove the non-DT SPEAr600 
files/data completely now? If you give me your ACK on this, I'll squash this 
into my patch as well, resulting in a nice diffstat. ;)
 
> > -       /* call spear600 machine init function */
> > -       spear600_init();
> > -
> > 
> >         /* Add Platform Devices */
> >         platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
> > 
> > diff --git a/arch/arm/mach-spear6xx/spear6xx.c
> > b/arch/arm/mach-spear6xx/spear6xx.c
> > 
> > +static const struct of_device_id vic_of_match[] __initconst = {
> > +       { .compatible = "arm,pl190-vic", .data = vic_of_init, },
> > +       { /* Sentinel */ }
> > +};
> > +
> > +static void __init spear6xx_dt_init_irq(void)
> > +{
> > +       of_irq_init(vic_of_match);
> > +}
> > +
> 
> Did you checked this out?

Not yet. Sorry, I missed it. Will check now...

Thanks,
Stefan


From viresh.kumar at st.com  Thu Mar 15 04:42:46 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 15 Mar 2012 14:12:46 +0530
Subject: [PATCH v2] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <201203150941.02822.sr@denx.de>
References: <1331737232-25477-1-git-send-email-sr@denx.de>
 <4F61A62A.3040501@st.com> <201203150941.02822.sr@denx.de>
Message-ID: <4F61AB86.5010204@st.com>

On 3/15/2012 2:11 PM, Stefan Roese wrote:
> So why don't we make an even bigger "cut", and remove the non-DT SPEAr600 
> files/data completely now? If you give me your ACK on this, I'll squash this 
> into my patch as well, resulting in a nice diffstat. 

My ack is already with you :)
Just go ahead, float the new version and i will ack it.

-- 
viresh


From peppe.cavallaro at st.com  Thu Mar 15 04:45:31 2012
From: peppe.cavallaro at st.com (Giuseppe CAVALLARO)
Date: Thu, 15 Mar 2012 09:45:31 +0100
Subject: [PATCH] stmmac: Add device-tree support
In-Reply-To: <20120314162628.GO18320@game.jcrosoft.org>
References: <1331561157-3820-1-git-send-email-sr@denx.de>
 <20120312143825.GB13869@game.jcrosoft.org> <4F60832E.6060100@st.com>
 <20120314162628.GO18320@game.jcrosoft.org>
Message-ID: <4F61AC2B.30609@st.com>

On 3/14/2012 5:26 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 12:38 Wed 14 Mar     , Giuseppe CAVALLARO wrote:
>> On 3/12/2012 3:38 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> On 15:05 Mon 12 Mar     , Stefan Roese wrote:
>>>> This patch adds support to configure the STMMAC ethernet driver via
>>>> device-tree instead of platform_data.
>>>>
>>>> Currently, only the properties needed on SPEAr600 are provided. All
>>>> other properties should be added once needed on other platforms.
>>>>
>>>> Signed-off-by: Stefan Roese <sr at denx.de>
>>>> Cc: Giuseppe Cavallaro <peppe.cavallaro at st.com>
>>>> Cc: Viresh Kumar <viresh.kumar at st.com>
>>>> ---
>>>>  Documentation/devicetree/bindings/net/stmmac.txt   |   38 +++++++++++
>>>>  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   66 +++++++++++++++++++-
>>>>  2 files changed, 103 insertions(+), 1 deletion(-)
>>>>  create mode 100644 Documentation/devicetree/bindings/net/stmmac.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
>>>> new file mode 100644
>>>> index 0000000..386a47f
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/net/stmmac.txt
>>>> @@ -0,0 +1,38 @@
>>>> +* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
>>>> +
>>>> +Required properties:
>>>> +- compatible: Should be "stm,gmac"
>>
>>> this IP have 2 version at least the GMAC for the second generation and mac for
>>> the first generation
>>
>> yes you are right. STMMAC supports two device generations I named:
>> dwma10/100 and dwmac1000 (gmac).
>>
>> Concerning the latter, we support several different versions of the
>> synopsys GMAC cores ... from 3.30 to 3.61a.
>>
>> For example, stx7108 and Stx7109 have the same GMAC core (also SPEAr600
>> IIRC).
> no PM the PM was only since 7108 IIRC

Sorry! you are right :-)

7109 has the mac10/100 (databook 1.91) and 7105/8 have the gmac databook
3.30.

peppe

> 
> 7109 use mac not gmac IIRC it's 7105 that start to use the GMAC with 300Mbps
> max
>> SPEAr13xx has 3.50a
>> New ST SoC Stxh415 has the 3.60a. etc.
>>
>>>> +- reg: Address and length of the register set for the device
>>>> +- interrupt-parent: Should be the phandle for the interrupt controller
>>>> +  that services interrupts for this device
>>>> +- interrupts: Should contain the STMMAC interrupts
>>>> +- interrupt-names: Should contain the interrupt names "macirq"
>>>> +  "eth_wake_irq" if this interrupt is supported in the "interrupts"
>>>> +  property
>>> optionnal
>>
>> yes
>>
>> note that there will be a new field for lpi IRQ as well
>>
>>>> +- phy-mode: String, operation mode of the PHY interface.
>>>> +  Supported values are: "mii", "rmii", "gmii", "rgmii".
>>>> +- phy-addr: MDIO address of the PHY
>>>> +
>>>> +Optional properties:
>>>> +- stm,prog-burst-len: Specify the burst length
>>>> +- stm,has-gmac: Indicates that the controller supports 1000Mbps
>>> this IP support more mode 10/100/300/1000
>>
>> has_gmac was used to understand on devices w/o the HW cap registers if
>> the core is a gmac... another useful parameter could be : enh_desc
> this need to manage via compatible
> 
> Best Regards,
> J.
> 



From sr at denx.de  Thu Mar 15 04:48:27 2012
From: sr at denx.de (Stefan Roese)
Date: Thu, 15 Mar 2012 09:48:27 +0100
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <4F604321.9000204@st.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <4F604321.9000204@st.com>
Message-ID: <201203150948.27918.sr@denx.de>

Viresh,

On Wednesday 14 March 2012 08:05:05 Viresh Kumar wrote:
> > +static const char *spear600_dt_board_compat[] = {
> > +	"st,spear600-evb",
> > +	NULL
> > +};
> > +
> > +static const struct of_device_id vic_of_match[] __initconst = {
> > +	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
> > +	{ /* Sentinel */ }
> > +};
> > +
> > +static void __init spear6xx_dt_init_irq(void)
> > +{
> > +	of_irq_init(vic_of_match);
> > +}
> > +
> 
> What about adding this routine in vic.c file, which can then be used
> by all platforms, instead of replicating this code.

We can't move vic_of_match to the vic.c, since there are differences between 
the boards using it. And only moving spear6xx_dt_init_irq() (renamed of 
course) doesn't seem worth it.

Thanks,
Stefan


From arnd at arndb.de  Thu Mar 15 04:48:32 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 08:48:32 +0000
Subject: [PATCH v4 10/10] pwm-backlight: Add rudimentary device tree
 support
In-Reply-To: <1331740593-10807-11-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-11-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <201203150848.32500.arnd@arndb.de>

On Wednesday 14 March 2012, Thierry Reding wrote:
> +
> +       pwm = of_pwm_request(node, "pwm", 0);
> +       if (IS_ERR(pwm))
> +               return PTR_ERR(pwm);

It's interesting that the (so far) only user of of_pwm_request() doesn't
actually give a meaningful argument as the name of the pwm property.

Maybe rename that function to of_pwm_request_named() and provide a helper
that just does this:?

static inline struct pwm_device *of_pwm_request(struct device_node *np, int index)
{
	return of_pwm_request_named(np, "pwm", index);
}

Any device that just has needs one pwm or uses more than one but has no
reason to name them can just use this helper then and use the default pwm
property name.

	Arnd


From s.hauer at pengutronix.de  Thu Mar 15 05:04:34 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 15 Mar 2012 10:04:34 +0100
Subject: [PATCH] move pwm drivers to new framework
Message-ID: <1331802277-12477-1-git-send-email-s.hauer@pengutronix.de>

This series is based on Thierrys pwm-v4 patches. It moves the existing
i.MX, samsung and vt8500 drivers over to the new framework. This is only
compile tested, no runtime tests at all. I can test the i.MX driver myself,
but it would be good to have some testers for samsung and vt8500.

Sascha

The following changes since commit 07e34a1f9a21c9f72e86a4e1ec64cc2150c89389:

  pwm: temporary fixup (2012-03-15 09:44:52 +0100)

are available in the git repository at:

  git://git.pengutronix.de/git/imx/linux-2.6.git pwm-v4

for you to fetch changes up to dc7c38dab4355ff3a43e5b9356d180e72a923ed3:

  ARM vt8500: Move vt8500 pwm driver to pwm framework (2012-03-15 09:45:49 +0100)

----------------------------------------------------------------
Sascha Hauer (3):
      ARM i.MX: Move i.MX pwm driver to pwm framework
      ARM Samsung: Move s3c pwm driver to pwm framework
      ARM vt8500: Move vt8500 pwm driver to pwm framework

 arch/arm/mach-vt8500/Makefile                      |    2 -
 arch/arm/plat-mxc/Kconfig                          |    6 -
 arch/arm/plat-mxc/Makefile                         |    1 -
 arch/arm/plat-samsung/Makefile                     |    4 -
 drivers/pwm/Kconfig                                |   27 +++
 drivers/pwm/Makefile                               |    5 +
 arch/arm/plat-mxc/pwm.c => drivers/pwm/pwm-imx.c   |  155 ++++++---------
 .../pwm.c => drivers/pwm/pwm-samsung.c             |  215 ++++++++------------
 .../mach-vt8500/pwm.c => drivers/pwm/pwm-vt8500.c  |  124 ++++--------
 9 files changed, 216 insertions(+), 323 deletions(-)
 rename arch/arm/plat-mxc/pwm.c => drivers/pwm/pwm-imx.c (66%)
 rename arch/arm/plat-samsung/pwm.c => drivers/pwm/pwm-samsung.c (61%)
 rename arch/arm/mach-vt8500/pwm.c => drivers/pwm/pwm-vt8500.c (64%)


From s.hauer at pengutronix.de  Thu Mar 15 05:04:37 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 15 Mar 2012 10:04:37 +0100
Subject: [PATCH 3/3] ARM vt8500: Move vt8500 pwm driver to pwm framework
In-Reply-To: <1331802277-12477-1-git-send-email-s.hauer@pengutronix.de>
References: <1331802277-12477-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1331802277-12477-4-git-send-email-s.hauer@pengutronix.de>

Move the driver to drivers/pwm/ and convert it to use the framework.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Alexey Charkov <alchark at gmail.com>
---
 arch/arm/mach-vt8500/Makefile                      |    2 -
 drivers/pwm/Kconfig                                |    9 ++
 drivers/pwm/Makefile                               |    3 +
 .../mach-vt8500/pwm.c => drivers/pwm/pwm-vt8500.c  |  124 +++++++-------------
 4 files changed, 56 insertions(+), 82 deletions(-)
 rename arch/arm/mach-vt8500/pwm.c => drivers/pwm/pwm-vt8500.c (64%)

diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 81aedb7..8df9e4a 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -5,5 +5,3 @@ obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o
 
 obj-$(CONFIG_MACH_BV07) += bv07.o
 obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o
-
-obj-$(CONFIG_HAVE_PWM) += pwm.o
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 0d9aa92..a93feff 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -55,4 +55,13 @@ config PWM_TEGRA
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-tegra.
 
+config PWM_VT8500
+	tristate "vt8500 pwm support"
+	depends on ARCH_VT8500
+	help
+	  Generic PWM framework driver for vt8500.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-vt8500.
+
 endif
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 2d613e0..fe745b0 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -4,3 +4,6 @@ obj-$(CONFIG_PWM_IMX)		+= imx-pwm.o
 obj-$(CONFIG_PWM_PXA)		+= pwm-pxa.o
 obj-$(CONFIG_PWM_SAMSUNG)	+= samsung-pwm.o
 obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
+obj-$(CONFIG_PWM_IMX)		+= pwm-imx.o
+obj-$(CONFIG_PWM_SAMSUNG)	+= pwm-samsung.o
+obj-$(CONFIG_PWM_VT8500)	+= pwm-vt8500.o
diff --git a/arch/arm/mach-vt8500/pwm.c b/drivers/pwm/pwm-vt8500.c
similarity index 64%
rename from arch/arm/mach-vt8500/pwm.c
rename to drivers/pwm/pwm-vt8500.c
index 8ad825e..6ebea33 100644
--- a/arch/arm/mach-vt8500/pwm.c
+++ b/drivers/pwm/pwm-vt8500.c
@@ -26,10 +26,7 @@
 
 #define VT8500_NR_PWMS 4
 
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
-
-struct pwm_device {
+struct vt8500_pwm_device {
 	struct list_head	node;
 	struct platform_device	*pdev;
 
@@ -39,8 +36,11 @@ struct pwm_device {
 
 	unsigned int	use_count;
 	unsigned int	pwm_id;
+	struct pwm_chip	chip;
 };
 
+#define to_vt8500_pwm_device(chip)	container_of(chip, struct vt8500_pwm_device, chip)
+
 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 static inline void pwm_busy_wait(void __iomem *reg, u8 bitmask)
 {
@@ -53,12 +53,14 @@ static inline void pwm_busy_wait(void __iomem *reg, u8 bitmask)
 			   bitmask);
 }
 
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+		int duty_ns, int period_ns)
 {
+	struct vt8500_pwm_device *vt8500_pwm = to_vt8500_pwm_device(chip);
 	unsigned long long c;
 	unsigned long period_cycles, prescale, pv, dc;
 
-	if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
+	if (vt8500_pwm == NULL || period_ns == 0 || duty_ns > period_ns)
 		return -EINVAL;
 
 	c = 25000000/2; /* wild guess --- need to implement clocks */
@@ -80,94 +82,50 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 	do_div(c, period_ns);
 	dc = c;
 
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 1));
-	writel(prescale, pwm->regbase + 0x4 + (pwm->pwm_id << 4));
+	pwm_busy_wait(vt8500_pwm->regbase + 0x40 + vt8500_pwm->pwm_id, (1 << 1));
+	writel(prescale, vt8500_pwm->regbase + 0x4 + (vt8500_pwm->pwm_id << 4));
 
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 2));
-	writel(pv, pwm->regbase + 0x8 + (pwm->pwm_id << 4));
+	pwm_busy_wait(vt8500_pwm->regbase + 0x40 + vt8500_pwm->pwm_id, (1 << 2));
+	writel(pv, vt8500_pwm->regbase + 0x8 + (vt8500_pwm->pwm_id << 4));
 
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 3));
-	writel(dc, pwm->regbase + 0xc + (pwm->pwm_id << 4));
+	pwm_busy_wait(vt8500_pwm->regbase + 0x40 + vt8500_pwm->pwm_id, (1 << 3));
+	writel(dc, vt8500_pwm->regbase + 0xc + (vt8500_pwm->pwm_id << 4));
 
 	return 0;
 }
-EXPORT_SYMBOL(pwm_config);
 
-int pwm_enable(struct pwm_device *pwm)
+static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 0));
-	writel(5, pwm->regbase + (pwm->pwm_id << 4));
-	return 0;
-}
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 0));
-	writel(0, pwm->regbase + (pwm->pwm_id << 4));
-}
-EXPORT_SYMBOL(pwm_disable);
+	struct vt8500_pwm_device *vt8500_pwm = to_vt8500_pwm_device(chip);
 
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-	struct pwm_device *pwm;
-	int found = 0;
-
-	mutex_lock(&pwm_lock);
-
-	list_for_each_entry(pwm, &pwm_list, node) {
-		if (pwm->pwm_id == pwm_id) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (found) {
-		if (pwm->use_count == 0) {
-			pwm->use_count++;
-			pwm->label = label;
-		} else {
-			pwm = ERR_PTR(-EBUSY);
-		}
-	} else {
-		pwm = ERR_PTR(-ENOENT);
-	}
-
-	mutex_unlock(&pwm_lock);
-	return pwm;
+	pwm_busy_wait(vt8500_pwm->regbase + 0x40 + vt8500_pwm->pwm_id, (1 << 0));
+	writel(5, vt8500_pwm->regbase + (vt8500_pwm->pwm_id << 4));
+	return 0;
 }
-EXPORT_SYMBOL(pwm_request);
 
-void pwm_free(struct pwm_device *pwm)
+static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
-	mutex_lock(&pwm_lock);
-
-	if (pwm->use_count) {
-		pwm->use_count--;
-		pwm->label = NULL;
-	} else {
-		pr_warning("PWM device already freed\n");
-	}
+	struct vt8500_pwm_device *vt8500_pwm = to_vt8500_pwm_device(chip);
 
-	mutex_unlock(&pwm_lock);
+	pwm_busy_wait(vt8500_pwm->regbase + 0x40 + vt8500_pwm->pwm_id, (1 << 0));
+	writel(0, vt8500_pwm->regbase + (vt8500_pwm->pwm_id << 4));
 }
-EXPORT_SYMBOL(pwm_free);
 
-static inline void __add_pwm(struct pwm_device *pwm)
-{
-	mutex_lock(&pwm_lock);
-	list_add_tail(&pwm->node, &pwm_list);
-	mutex_unlock(&pwm_lock);
-}
+static struct pwm_ops vt8500_pwm_ops = {
+	.enable = vt8500_pwm_enable,
+	.disable = vt8500_pwm_disable,
+	.config = vt8500_pwm_config,
+	.owner = THIS_MODULE,
+};
 
 static int __devinit pwm_probe(struct platform_device *pdev)
 {
-	struct pwm_device *pwms;
+	struct vt8500_pwm_device *pwms;
 	struct resource *r;
 	int ret = 0;
 	int i;
 
-	pwms = kzalloc(sizeof(struct pwm_device) * VT8500_NR_PWMS, GFP_KERNEL);
+	pwms = kzalloc(sizeof(*pwms) * VT8500_NR_PWMS, GFP_KERNEL);
 	if (pwms == NULL) {
 		dev_err(&pdev->dev, "failed to allocate memory\n");
 		return -ENOMEM;
@@ -177,6 +135,7 @@ static int __devinit pwm_probe(struct platform_device *pdev)
 		pwms[i].use_count = 0;
 		pwms[i].pwm_id = i;
 		pwms[i].pdev = pdev;
+		pwms[i].chip.ops = &vt8500_pwm_ops;
 	}
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -203,12 +162,20 @@ static int __devinit pwm_probe(struct platform_device *pdev)
 	for (i = 1; i < VT8500_NR_PWMS; i++)
 		pwms[i].regbase = pwms[0].regbase;
 
-	for (i = 0; i < VT8500_NR_PWMS; i++)
-		__add_pwm(&pwms[i]);
+	for (i = 0; i < VT8500_NR_PWMS; i++) {
+		ret = pwmchip_add(&pwms[i].chip);
+		if (ret)
+			goto err_unregister;
+	}
 
 	platform_set_drvdata(pdev, pwms);
 	return 0;
 
+err_unregister:
+	while (i) {
+		i--;
+		pwmchip_remove(&pwms[i].chip);
+	}
 err_free_mem:
 	release_mem_region(r->start, resource_size(r));
 err_free:
@@ -218,7 +185,7 @@ err_free:
 
 static int __devexit pwm_remove(struct platform_device *pdev)
 {
-	struct pwm_device *pwms;
+	struct vt8500_pwm_device *pwms;
 	struct resource *r;
 	int i;
 
@@ -226,11 +193,8 @@ static int __devexit pwm_remove(struct platform_device *pdev)
 	if (pwms == NULL)
 		return -ENODEV;
 
-	mutex_lock(&pwm_lock);
-
 	for (i = 0; i < VT8500_NR_PWMS; i++)
-		list_del(&pwms[i].node);
-	mutex_unlock(&pwm_lock);
+		pwmchip_remove(&pwms[i].chip);
 
 	iounmap(pwms[0].regbase);
 
-- 
1.7.9.1



From s.hauer at pengutronix.de  Thu Mar 15 05:04:35 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 15 Mar 2012 10:04:35 +0100
Subject: [PATCH 1/3] ARM i.MX: Move i.MX pwm driver to pwm framework
In-Reply-To: <1331802277-12477-1-git-send-email-s.hauer@pengutronix.de>
References: <1331802277-12477-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1331802277-12477-2-git-send-email-s.hauer@pengutronix.de>

Move the driver to drivers/pwm/ and convert it to use the framework.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/plat-mxc/Kconfig                        |    6 -
 arch/arm/plat-mxc/Makefile                       |    1 -
 drivers/pwm/Kconfig                              |    9 ++
 drivers/pwm/Makefile                             |    1 +
 arch/arm/plat-mxc/pwm.c => drivers/pwm/pwm-imx.c |  155 ++++++++-------------
 5 files changed, 69 insertions(+), 103 deletions(-)
 rename arch/arm/plat-mxc/pwm.c => drivers/pwm/pwm-imx.c (66%)

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index dcebb12..ee09395 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -47,12 +47,6 @@ config MXC_TZIC
 config MXC_AVIC
 	bool
 
-config MXC_PWM
-	tristate "Enable PWM driver"
-	select HAVE_PWM
-	help
-	  Enable support for the i.MX PWM controller(s).
-
 config MXC_DEBUG_BOARD
 	bool "Enable MXC debug board(for 3-stack)"
 	help
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 076db84f..d75ab5a 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -11,7 +11,6 @@ obj-$(CONFIG_MXC_AVIC) += avic.o
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
-obj-$(CONFIG_MXC_PWM)  += pwm.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 0ef4f30..a9a9715 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -18,6 +18,15 @@ config PWM_BFIN
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-bfin.
 
+config PWM_IMX
+	tristate "i.MX pwm support"
+	depends on ARCH_MXC
+	help
+	  Generic PWM framework driver for i.MX.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-imx.
+
 config PWM_PXA
 	tristate "PXA PWM support"
 	depends on ARCH_PXA
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index e859c51..fc7571e 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_PWM)		+= core.o
 obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
+obj-$(CONFIG_PWM_IMX)		+= imx-pwm.o
 obj-$(CONFIG_PWM_PXA)		+= pwm-pxa.o
 obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
diff --git a/arch/arm/plat-mxc/pwm.c b/drivers/pwm/pwm-imx.c
similarity index 66%
rename from arch/arm/plat-mxc/pwm.c
rename to drivers/pwm/pwm-imx.c
index e032717..cdb02b0 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/drivers/pwm/pwm-imx.c
@@ -39,24 +39,24 @@
 #define MX3_PWMCR_CLKSRC_IPG      (1 << 16)
 #define MX3_PWMCR_EN              (1 << 0)
 
-
-
-struct pwm_device {
+struct imx_pwm_device {
 	struct list_head	node;
-	struct platform_device *pdev;
 
-	const char	*label;
 	struct clk	*clk;
 
 	int		clk_enabled;
 	void __iomem	*mmio_base;
 
-	unsigned int	use_count;
-	unsigned int	pwm_id;
+	struct pwm_chip chip;
 };
 
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+#define to_imx_pwm_device(chip)	container_of(chip, struct imx_pwm_device, chip)
+
+static int imx_pwm_config(struct pwm_chip *chip,
+		struct pwm_device *pwm, int duty_ns, int period_ns)
 {
+	struct imx_pwm_device *imxpwm = to_imx_pwm_device(chip);
+
 	if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
 		return -EINVAL;
 
@@ -65,7 +65,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 		unsigned long period_cycles, duty_cycles, prescale;
 		u32 cr;
 
-		c = clk_get_rate(pwm->clk);
+		c = clk_get_rate(imxpwm->clk);
 		c = c * period_ns;
 		do_div(c, 1000000000);
 		period_cycles = c;
@@ -86,8 +86,8 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 		else
 			period_cycles = 0;
 
-		writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);
-		writel(period_cycles, pwm->mmio_base + MX3_PWMPR);
+		writel(duty_cycles, imxpwm->mmio_base + MX3_PWMSAR);
+		writel(period_cycles, imxpwm->mmio_base + MX3_PWMPR);
 
 		cr = MX3_PWMCR_PRESCALER(prescale) |
 			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
@@ -98,7 +98,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 		else
 			cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
 
-		writel(cr, pwm->mmio_base + MX3_PWMCR);
+		writel(cr, imxpwm->mmio_base + MX3_PWMCR);
 	} else if (cpu_is_mx1() || cpu_is_mx21()) {
 		/* The PWM subsystem allows for exact frequencies. However,
 		 * I cannot connect a scope on my device to the PWM line and
@@ -116,110 +116,70 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 		 * both the prescaler (/1 .. /128) and then by CLKSEL
 		 * (/2 .. /16).
 		 */
-		u32 max = readl(pwm->mmio_base + MX1_PWMP);
+		u32 max = readl(imxpwm->mmio_base + MX1_PWMP);
 		u32 p = max * duty_ns / period_ns;
-		writel(max - p, pwm->mmio_base + MX1_PWMS);
+		writel(max - p, imxpwm->mmio_base + MX1_PWMS);
 	} else {
 		BUG();
 	}
 
 	return 0;
 }
-EXPORT_SYMBOL(pwm_config);
 
-int pwm_enable(struct pwm_device *pwm)
+static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
+	struct imx_pwm_device *imxpwm = to_imx_pwm_device(chip);
 	int rc = 0;
 
-	if (!pwm->clk_enabled) {
-		rc = clk_enable(pwm->clk);
+	if (!imxpwm->clk_enabled) {
+		rc = clk_enable(imxpwm->clk);
 		if (!rc)
-			pwm->clk_enabled = 1;
+			imxpwm->clk_enabled = 1;
 	}
 	return rc;
 }
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-	writel(0, pwm->mmio_base + MX3_PWMCR);
-
-	if (pwm->clk_enabled) {
-		clk_disable(pwm->clk);
-		pwm->clk_enabled = 0;
-	}
-}
-EXPORT_SYMBOL(pwm_disable);
-
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
 
-struct pwm_device *pwm_request(int pwm_id, const char *label)
+static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
-	struct pwm_device *pwm;
-	int found = 0;
+	struct imx_pwm_device *imxpwm = to_imx_pwm_device(chip);
 
-	mutex_lock(&pwm_lock);
+	writel(0, imxpwm->mmio_base + MX3_PWMCR);
 
-	list_for_each_entry(pwm, &pwm_list, node) {
-		if (pwm->pwm_id == pwm_id) {
-			found = 1;
-			break;
-		}
+	if (imxpwm->clk_enabled) {
+		clk_disable(imxpwm->clk);
+		imxpwm->clk_enabled = 0;
 	}
-
-	if (found) {
-		if (pwm->use_count == 0) {
-			pwm->use_count++;
-			pwm->label = label;
-		} else
-			pwm = ERR_PTR(-EBUSY);
-	} else
-		pwm = ERR_PTR(-ENOENT);
-
-	mutex_unlock(&pwm_lock);
-	return pwm;
 }
-EXPORT_SYMBOL(pwm_request);
-
-void pwm_free(struct pwm_device *pwm)
-{
-	mutex_lock(&pwm_lock);
-
-	if (pwm->use_count) {
-		pwm->use_count--;
-		pwm->label = NULL;
-	} else
-		pr_warning("PWM device already freed\n");
 
-	mutex_unlock(&pwm_lock);
-}
-EXPORT_SYMBOL(pwm_free);
+static struct pwm_ops imx_pwm_ops = {
+	.enable = imx_pwm_enable,
+	.disable = imx_pwm_disable,
+	.config = imx_pwm_config,
+	.owner = THIS_MODULE,
+};
 
 static int __devinit mxc_pwm_probe(struct platform_device *pdev)
 {
-	struct pwm_device *pwm;
+	struct imx_pwm_device *imxpwm;
 	struct resource *r;
 	int ret = 0;
 
-	pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
-	if (pwm == NULL) {
+	imxpwm = kzalloc(sizeof(*imxpwm), GFP_KERNEL);
+	if (imxpwm == NULL) {
 		dev_err(&pdev->dev, "failed to allocate memory\n");
 		return -ENOMEM;
 	}
 
-	pwm->clk = clk_get(&pdev->dev, "pwm");
+	imxpwm->clk = clk_get(&pdev->dev, "pwm");
 
-	if (IS_ERR(pwm->clk)) {
-		ret = PTR_ERR(pwm->clk);
+	if (IS_ERR(imxpwm->clk)) {
+		ret = PTR_ERR(imxpwm->clk);
 		goto err_free;
 	}
 
-	pwm->clk_enabled = 0;
+	imxpwm->chip.ops = &imx_pwm_ops;
 
-	pwm->use_count = 0;
-	pwm->pwm_id = pdev->id;
-	pwm->pdev = pdev;
+	imxpwm->clk_enabled = 0;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
@@ -235,50 +195,53 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev)
 		goto err_free_clk;
 	}
 
-	pwm->mmio_base = ioremap(r->start, resource_size(r));
-	if (pwm->mmio_base == NULL) {
+	imxpwm->mmio_base = ioremap(r->start, resource_size(r));
+	if (imxpwm->mmio_base == NULL) {
 		dev_err(&pdev->dev, "failed to ioremap() registers\n");
 		ret = -ENODEV;
 		goto err_free_mem;
 	}
 
-	mutex_lock(&pwm_lock);
-	list_add_tail(&pwm->node, &pwm_list);
-	mutex_unlock(&pwm_lock);
+	ret = pwmchip_add(&imxpwm->chip);
+	if (ret)
+		goto err_iounmap;
 
-	platform_set_drvdata(pdev, pwm);
+	platform_set_drvdata(pdev, imxpwm);
 	return 0;
 
+err_iounmap:
+	iounmap(imxpwm->mmio_base);
 err_free_mem:
 	release_mem_region(r->start, resource_size(r));
 err_free_clk:
-	clk_put(pwm->clk);
+	clk_put(imxpwm->clk);
 err_free:
-	kfree(pwm);
+	kfree(imxpwm);
 	return ret;
 }
 
 static int __devexit mxc_pwm_remove(struct platform_device *pdev)
 {
-	struct pwm_device *pwm;
+	struct imx_pwm_device *imxpwm;
 	struct resource *r;
+	int ret;
 
-	pwm = platform_get_drvdata(pdev);
-	if (pwm == NULL)
+	imxpwm = platform_get_drvdata(pdev);
+	if (imxpwm == NULL)
 		return -ENODEV;
 
-	mutex_lock(&pwm_lock);
-	list_del(&pwm->node);
-	mutex_unlock(&pwm_lock);
+	ret = pwmchip_remove(&imxpwm->chip);
+	if (ret)
+		return ret;
 
-	iounmap(pwm->mmio_base);
+	iounmap(imxpwm->mmio_base);
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	release_mem_region(r->start, resource_size(r));
 
-	clk_put(pwm->clk);
+	clk_put(imxpwm->clk);
 
-	kfree(pwm);
+	kfree(imxpwm);
 	return 0;
 }
 
-- 
1.7.9.1



From s.hauer at pengutronix.de  Thu Mar 15 05:04:36 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 15 Mar 2012 10:04:36 +0100
Subject: [PATCH 2/3] ARM Samsung: Move s3c pwm driver to pwm framework
In-Reply-To: <1331802277-12477-1-git-send-email-s.hauer@pengutronix.de>
References: <1331802277-12477-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1331802277-12477-3-git-send-email-s.hauer@pengutronix.de>

Move the driver to drivers/pwm/ and convert it to use the framework.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/plat-samsung/Makefile                     |    4 -
 drivers/pwm/Kconfig                                |    9 +
 drivers/pwm/Makefile                               |    1 +
 .../pwm.c => drivers/pwm/pwm-samsung.c             |  215 ++++++++------------
 4 files changed, 91 insertions(+), 138 deletions(-)
 rename arch/arm/plat-samsung/pwm.c => drivers/pwm/pwm-samsung.c (61%)

diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 6012366..f09a7cf 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -50,7 +50,3 @@ obj-$(CONFIG_SAMSUNG_WAKEMASK)	+= wakeup-mask.o
 # PD support
 
 obj-$(CONFIG_SAMSUNG_PD)	+= pd.o
-
-# PWM support
-
-obj-$(CONFIG_HAVE_PWM)		+= pwm.o
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index a9a9715..0d9aa92 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -36,6 +36,15 @@ config PWM_PXA
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-pxa.
 
+config PWM_SAMSUNG
+	tristate "Samsung pwm support"
+	depends on PLAT_SAMSUNG
+	help
+	  Generic PWM framework driver for Samsung.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-samsung.
+
 config PWM_TEGRA
 	tristate "NVIDIA Tegra PWM support"
 	depends on ARCH_TEGRA
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index fc7571e..2d613e0 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -2,4 +2,5 @@ obj-$(CONFIG_PWM)		+= core.o
 obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
 obj-$(CONFIG_PWM_IMX)		+= imx-pwm.o
 obj-$(CONFIG_PWM_PXA)		+= pwm-pxa.o
+obj-$(CONFIG_PWM_SAMSUNG)	+= samsung-pwm.o
 obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
diff --git a/arch/arm/plat-samsung/pwm.c b/drivers/pwm/pwm-samsung.c
similarity index 61%
rename from arch/arm/plat-samsung/pwm.c
rename to drivers/pwm/pwm-samsung.c
index c559d84..5640ba3 100644
--- a/arch/arm/plat-samsung/pwm.c
+++ b/drivers/pwm/pwm-samsung.c
@@ -24,7 +24,7 @@
 
 #include <plat/regs-timer.h>
 
-struct pwm_device {
+struct s3c_pwm_device {
 	struct list_head	 list;
 	struct platform_device	*pdev;
 
@@ -37,110 +37,62 @@ struct pwm_device {
 
 	unsigned char		 tcon_base;
 	unsigned char		 running;
-	unsigned char		 use_count;
 	unsigned char		 pwm_id;
+	struct pwm_chip chip;
 };
 
+#define to_s3c_pwm_device(chip)	container_of(chip, struct s3c_pwm_device, chip)
+
 #define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg)
 
 static struct clk *clk_scaler[2];
 
-static inline int pwm_is_tdiv(struct pwm_device *pwm)
+static inline int pwm_is_tdiv(struct s3c_pwm_device *pwm)
 {
 	return clk_get_parent(pwm->clk) == pwm->clk_div;
 }
 
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-	struct pwm_device *pwm;
-	int found = 0;
-
-	mutex_lock(&pwm_lock);
-
-	list_for_each_entry(pwm, &pwm_list, list) {
-		if (pwm->pwm_id == pwm_id) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (found) {
-		if (pwm->use_count == 0) {
-			pwm->use_count = 1;
-			pwm->label = label;
-		} else
-			pwm = ERR_PTR(-EBUSY);
-	} else
-		pwm = ERR_PTR(-ENOENT);
-
-	mutex_unlock(&pwm_lock);
-	return pwm;
-}
-
-EXPORT_SYMBOL(pwm_request);
-
-
-void pwm_free(struct pwm_device *pwm)
-{
-	mutex_lock(&pwm_lock);
-
-	if (pwm->use_count) {
-		pwm->use_count--;
-		pwm->label = NULL;
-	} else
-		printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id);
-
-	mutex_unlock(&pwm_lock);
-}
-
-EXPORT_SYMBOL(pwm_free);
-
 #define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0))
 #define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2))
 #define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3))
 #define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1))
 
-int pwm_enable(struct pwm_device *pwm)
+static int s3c_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
+	struct s3c_pwm_device *s3c_pwm = to_s3c_pwm_device(chip);
 	unsigned long flags;
 	unsigned long tcon;
 
 	local_irq_save(flags);
 
 	tcon = __raw_readl(S3C2410_TCON);
-	tcon |= pwm_tcon_start(pwm);
+	tcon |= pwm_tcon_start(s3c_pwm);
 	__raw_writel(tcon, S3C2410_TCON);
 
 	local_irq_restore(flags);
 
-	pwm->running = 1;
+	s3c_pwm->running = 1;
 	return 0;
 }
 
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
+static void s3c_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
+	struct s3c_pwm_device *s3c_pwm = to_s3c_pwm_device(chip);
 	unsigned long flags;
 	unsigned long tcon;
 
 	local_irq_save(flags);
 
 	tcon = __raw_readl(S3C2410_TCON);
-	tcon &= ~pwm_tcon_start(pwm);
+	tcon &= ~pwm_tcon_start(s3c_pwm);
 	__raw_writel(tcon, S3C2410_TCON);
 
 	local_irq_restore(flags);
 
-	pwm->running = 0;
+	s3c_pwm->running = 0;
 }
 
-EXPORT_SYMBOL(pwm_disable);
-
-static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
+static unsigned long pwm_calc_tin(struct s3c_pwm_device *pwm, unsigned long freq)
 {
 	unsigned long tin_parent_rate;
 	unsigned int div;
@@ -158,8 +110,10 @@ static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
 
 #define NS_IN_HZ (1000000000UL)
 
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+static int s3c_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+		int duty_ns, int period_ns)
 {
+	struct s3c_pwm_device *s3c_pwm = to_s3c_pwm_device(chip);
 	unsigned long tin_rate;
 	unsigned long tin_ns;
 	unsigned long period;
@@ -178,38 +132,38 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 	if (duty_ns > period_ns)
 		return -EINVAL;
 
-	if (period_ns == pwm->period_ns &&
-	    duty_ns == pwm->duty_ns)
+	if (period_ns == s3c_pwm->period_ns &&
+	    duty_ns == s3c_pwm->duty_ns)
 		return 0;
 
 	/* The TCMP and TCNT can be read without a lock, they're not
 	 * shared between the timers. */
 
-	tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id));
-	tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id));
+	tcmp = __raw_readl(S3C2410_TCMPB(s3c_pwm->pwm_id));
+	tcnt = __raw_readl(S3C2410_TCNTB(s3c_pwm->pwm_id));
 
 	period = NS_IN_HZ / period_ns;
 
-	pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n",
+	pwm_dbg(s3c_pwm, "duty_ns=%d, period_ns=%d (%lu)\n",
 		duty_ns, period_ns, period);
 
 	/* Check to see if we are changing the clock rate of the PWM */
 
-	if (pwm->period_ns != period_ns) {
-		if (pwm_is_tdiv(pwm)) {
-			tin_rate = pwm_calc_tin(pwm, period);
-			clk_set_rate(pwm->clk_div, tin_rate);
+	if (s3c_pwm->period_ns != period_ns) {
+		if (pwm_is_tdiv(s3c_pwm)) {
+			tin_rate = pwm_calc_tin(s3c_pwm, period);
+			clk_set_rate(s3c_pwm->clk_div, tin_rate);
 		} else
-			tin_rate = clk_get_rate(pwm->clk);
+			tin_rate = clk_get_rate(s3c_pwm->clk);
 
-		pwm->period_ns = period_ns;
+		s3c_pwm->period_ns = period_ns;
 
-		pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate);
+		pwm_dbg(s3c_pwm, "tin_rate=%lu\n", tin_rate);
 
 		tin_ns = NS_IN_HZ / tin_rate;
 		tcnt = period_ns / tin_ns;
 	} else
-		tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk);
+		tin_ns = NS_IN_HZ / clk_get_rate(s3c_pwm->clk);
 
 	/* Note, counters count down */
 
@@ -220,7 +174,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 	if (tcmp == tcnt)
 		tcmp--;
 
-	pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
+	pwm_dbg(s3c_pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
 
 	if (tcmp < 0)
 		tcmp = 0;
@@ -229,15 +183,15 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 
 	local_irq_save(flags);
 
-	__raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id));
-	__raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id));
+	__raw_writel(tcmp, S3C2410_TCMPB(s3c_pwm->pwm_id));
+	__raw_writel(tcnt, S3C2410_TCNTB(s3c_pwm->pwm_id));
 
 	tcon = __raw_readl(S3C2410_TCON);
-	tcon |= pwm_tcon_manulupdate(pwm);
-	tcon |= pwm_tcon_autoreload(pwm);
+	tcon |= pwm_tcon_manulupdate(s3c_pwm);
+	tcon |= pwm_tcon_autoreload(s3c_pwm);
 	__raw_writel(tcon, S3C2410_TCON);
 
-	tcon &= ~pwm_tcon_manulupdate(pwm);
+	tcon &= ~pwm_tcon_manulupdate(s3c_pwm);
 	__raw_writel(tcon, S3C2410_TCON);
 
 	local_irq_restore(flags);
@@ -245,24 +199,17 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 	return 0;
 }
 
-EXPORT_SYMBOL(pwm_config);
-
-static int pwm_register(struct pwm_device *pwm)
-{
-	pwm->duty_ns = -1;
-	pwm->period_ns = -1;
-
-	mutex_lock(&pwm_lock);
-	list_add_tail(&pwm->list, &pwm_list);
-	mutex_unlock(&pwm_lock);
-
-	return 0;
-}
+static struct pwm_ops s3c_pwm_ops = {
+	.enable = s3c_pwm_enable,
+	.disable = s3c_pwm_disable,
+	.config = s3c_pwm_config,
+	.owner = THIS_MODULE,
+};
 
 static int s3c_pwm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
-	struct pwm_device *pwm;
+	struct s3c_pwm_device *s3c_pwm;
 	unsigned long flags;
 	unsigned long tcon;
 	unsigned int id = pdev->id;
@@ -273,83 +220,83 @@ static int s3c_pwm_probe(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
-	pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
-	if (pwm == NULL) {
+	s3c_pwm = kzalloc(sizeof(*s3c_pwm), GFP_KERNEL);
+	if (s3c_pwm == NULL) {
 		dev_err(dev, "failed to allocate pwm_device\n");
 		return -ENOMEM;
 	}
 
-	pwm->pdev = pdev;
-	pwm->pwm_id = id;
-
 	/* calculate base of control bits in TCON */
-	pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4;
+	s3c_pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4;
+	s3c_pwm->chip.ops = &s3c_pwm_ops;
 
-	pwm->clk = clk_get(dev, "pwm-tin");
-	if (IS_ERR(pwm->clk)) {
+	s3c_pwm->clk = clk_get(dev, "pwm-tin");
+	if (IS_ERR(s3c_pwm->clk)) {
 		dev_err(dev, "failed to get pwm tin clk\n");
-		ret = PTR_ERR(pwm->clk);
+		ret = PTR_ERR(s3c_pwm->clk);
 		goto err_alloc;
 	}
 
-	pwm->clk_div = clk_get(dev, "pwm-tdiv");
-	if (IS_ERR(pwm->clk_div)) {
+	s3c_pwm->clk_div = clk_get(dev, "pwm-tdiv");
+	if (IS_ERR(s3c_pwm->clk_div)) {
 		dev_err(dev, "failed to get pwm tdiv clk\n");
-		ret = PTR_ERR(pwm->clk_div);
+		ret = PTR_ERR(s3c_pwm->clk_div);
 		goto err_clk_tin;
 	}
 
-	clk_enable(pwm->clk);
-	clk_enable(pwm->clk_div);
+	clk_enable(s3c_pwm->clk);
+	clk_enable(s3c_pwm->clk_div);
 
 	local_irq_save(flags);
 
 	tcon = __raw_readl(S3C2410_TCON);
-	tcon |= pwm_tcon_invert(pwm);
+	tcon |= pwm_tcon_invert(s3c_pwm);
 	__raw_writel(tcon, S3C2410_TCON);
 
 	local_irq_restore(flags);
 
 
-	ret = pwm_register(pwm);
+	ret = pwmchip_add(&s3c_pwm->chip);
 	if (ret) {
 		dev_err(dev, "failed to register pwm\n");
 		goto err_clk_tdiv;
 	}
 
-	pwm_dbg(pwm, "config bits %02x\n",
-		(__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f);
+	pwm_dbg(s3c_pwm, "config bits %02x\n",
+		(__raw_readl(S3C2410_TCON) >> s3c_pwm->tcon_base) & 0x0f);
 
 	dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n",
-		 clk_get_rate(pwm->clk),
-		 clk_get_rate(pwm->clk_div),
-		 pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base);
+		 clk_get_rate(s3c_pwm->clk),
+		 clk_get_rate(s3c_pwm->clk_div),
+		 pwm_is_tdiv(s3c_pwm) ? "div" : "ext", s3c_pwm->tcon_base);
 
-	platform_set_drvdata(pdev, pwm);
+	platform_set_drvdata(pdev, s3c_pwm);
 	return 0;
 
  err_clk_tdiv:
-	clk_disable(pwm->clk_div);
-	clk_disable(pwm->clk);
-	clk_put(pwm->clk_div);
+	clk_disable(s3c_pwm->clk_div);
+	clk_disable(s3c_pwm->clk);
+	clk_put(s3c_pwm->clk_div);
 
  err_clk_tin:
-	clk_put(pwm->clk);
+	clk_put(s3c_pwm->clk);
 
  err_alloc:
-	kfree(pwm);
+	kfree(s3c_pwm);
 	return ret;
 }
 
 static int __devexit s3c_pwm_remove(struct platform_device *pdev)
 {
-	struct pwm_device *pwm = platform_get_drvdata(pdev);
+	struct s3c_pwm_device *s3c_pwm = platform_get_drvdata(pdev);
+
+	pwmchip_remove(&s3c_pwm->chip);
 
-	clk_disable(pwm->clk_div);
-	clk_disable(pwm->clk);
-	clk_put(pwm->clk_div);
-	clk_put(pwm->clk);
-	kfree(pwm);
+	clk_disable(s3c_pwm->clk_div);
+	clk_disable(s3c_pwm->clk);
+	clk_put(s3c_pwm->clk_div);
+	clk_put(s3c_pwm->clk);
+	kfree(s3c_pwm);
 
 	return 0;
 }
@@ -357,26 +304,26 @@ static int __devexit s3c_pwm_remove(struct platform_device *pdev)
 #ifdef CONFIG_PM
 static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state)
 {
-	struct pwm_device *pwm = platform_get_drvdata(pdev);
+	struct s3c_pwm_device *s3c_pwm = platform_get_drvdata(pdev);
 
 	/* No one preserve these values during suspend so reset them
 	 * Otherwise driver leaves PWM unconfigured if same values
 	 * passed to pwm_config
 	 */
-	pwm->period_ns = 0;
-	pwm->duty_ns = 0;
+	s3c_pwm->period_ns = 0;
+	s3c_pwm->duty_ns = 0;
 
 	return 0;
 }
 
 static int s3c_pwm_resume(struct platform_device *pdev)
 {
-	struct pwm_device *pwm = platform_get_drvdata(pdev);
+	struct s3c_pwm_device *s3c_pwmwm = platform_get_drvdata(pdev);
 	unsigned long tcon;
 
 	/* Restore invertion */
 	tcon = __raw_readl(S3C2410_TCON);
-	tcon |= pwm_tcon_invert(pwm);
+	tcon |= pwm_tcon_invert(s3c_pwmwm);
 	__raw_writel(tcon, S3C2410_TCON);
 
 	return 0;
-- 
1.7.9.1



From s.hauer at pengutronix.de  Thu Mar 15 05:05:40 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 15 Mar 2012 10:05:40 +0100
Subject: [PATCH v4 09/10] pwm: Add PXA support
In-Reply-To: <20120315065631.GB20502@avionic-0098.mockup.avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-10-git-send-email-thierry.reding@avionic-design.de>
 <4F61343A.80103@gmail.com>
 <20120315065631.GB20502@avionic-0098.mockup.avionic-design.de>
Message-ID: <20120315090540.GW3852@pengutronix.de>

On Thu, Mar 15, 2012 at 07:56:31AM +0100, Thierry Reding wrote:
> * Ryan Mallon wrote:
> > On 15/03/12 02:56, Thierry Reding wrote:
> > 
> > > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> > > ---
> > > Changes in v3:
> > >   - update PWM ops for changes in patch 2
> > 
> > Couple of quick notes, mostly for future work.
> > 
> > > +	/* NOTE: the clock to PWM has to be enabled first
> > > +	 * before writing to the registers
> > > +	 */
> > > +	clk_enable(pc->clk);
> > 
> > 
> > Should be fixed to also call clk_prepare (and clk_unprepare after
> > clk_disable). Could be done in a follow up patch.
> > 
> > > +	__raw_writel(prescale, pc->mmio_base + offset + PWMCR);
> > > +	__raw_writel(dc, pc->mmio_base + offset + PWMDCR);
> > > +	__raw_writel(pv, pc->mmio_base + offset + PWMPCR);
> > 
> > 
> > Should we fix this driver to use readl/writel instead of the __raw
> > variants? The memory is properly ioremaped, and to my understanding the
> > __raw memory accessors should be avoided outside of core code. This
> > could be done in a follow up patch if you want to keep this patch as
> > mostly just a move of the code.
> 
> Actually I wasn't planning on keeping this patch at all. Sascha already has
> the existing PWM providers converted to his original framework and offered to
> rebase them onto this series once the dust settles. I only used them as
> testbed to see how the driver interface works out for different hardware. But
> I also think that if Sascha hasn't cleaned the driver up yet it should either
> be done in his conversion patches or as follow ups.

All I have is a simple conversion to the new framework, nothing more.  I
rebased my patches yesterday onto this series (unfortunately due to the
additional argument pwm_device the patches do not look like just moving
the drivers anymore). I also skipped the PXA patch since I saw that you
already have this one. I just posted the patches to the list.

> 
> Sascha: how do you plan on going forward with this? It seems like the driver
> interface is pretty much done now and I expect the next round to be the last,
> unless I forget to properly work through the TODO list again. If you are busy
> with other stuff I can probably find some time to help with porting your
> converted drivers.

I haven't done drivers/mfd/twl6030-pwm.c. This one needs a bit more work
as it currently does not register itself as a subdriver to the twl6030
but just uses a globally available twl_i2c_write_u8() function. So if
you have some time to spare it would be great if you could do this.

> 
> I'm also wondering which tree this will go in through. Does it make sense to
> have an extra tree just for the PWM framework or can it go in via some other
> general purpose tree? Who do I need to prod?

Good question, I don't know.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Thu Mar 15 05:07:29 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 09:07:29 +0000
Subject: [PATCH v9] mfd: Add anatop mfd driver
In-Reply-To: <1331797421-23731-1-git-send-email-paul.liu@linaro.org>
References: <1331797421-23731-1-git-send-email-paul.liu@linaro.org>
Message-ID: <201203150907.29895.arnd@arndb.de>

On Thursday 15 March 2012, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
> Anatop provides regulators and thermal.
> This driver handles the address space and the operation of the mfd device.

Hi Paul,

This looks like a very nice and clean driver, good work!

Very broadly speaking, I wonder whether we could use the regmap
infrastructure for these things in the future, but I would first
need to understand whether that is actually in the scope of regmap.

It seems that you just need a subset of what regmap provides,
so it could work, but it might not actually be better than what
you have now.

Mark, can you comment on that?

> +u32 anatop_get_bits(struct anatop *adata, u32 addr, int bit_shift,
> +		    int bit_width)
> +{
> +	u32 val, mask;
> +
> +	if (bit_width == 32)
> +		mask = ~0;
> +	else
> +		mask = (1 << bit_width) - 1;
> +
> +	val = readl(adata->ioreg + addr);
> +	val = (val >> bit_shift) & mask;
> +
> +	return val;
> +}
> +EXPORT_SYMBOL(anatop_get_bits);

I think the exports here should be EXPORT_SYMBOL_GPL. There is no reason
why an out of tree driver would ever use these.

> +static const struct of_device_id of_anatop_subdevice_match[] = {
> +	{ .compatible = "fsl,anatop-regulator", },
> +	{ .compatible = "fsl,anatop-thermal", },
> +	{ },
> +};
> +
> +static int __devinit of_anatop_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	void *ioreg;
> +	struct anatop *drvdata;
> +
> +	ioreg = of_iomap(np, 0);
> +	if (!ioreg)
> +		return -EADDRNOTAVAIL;
> +	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> +	if (!drvdata)
> +		return -ENOMEM;
> +	drvdata->ioreg = ioreg;
> +	spin_lock_init(&drvdata->reglock);
> +	platform_set_drvdata(pdev, drvdata);
> +	of_platform_bus_probe(np, of_anatop_subdevice_match, dev);
> +
> +	return 0;
> +}

Why do you list the subdevices in of_anatop_subdevice_match()? I think you
should just use 

	of_platform_bus_probe(np, of_anatop_match, dev);

here, using the same match table that you have in the platform_driver.
That will automatically create platform devices for any children of this
device, so you don't have to update the list above when you get new
child drivers.

	Arnd


From thierry.reding at avionic-design.de  Thu Mar 15 05:21:34 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 15 Mar 2012 10:21:34 +0100
Subject: [PATCH v4 09/10] pwm: Add PXA support
In-Reply-To: <20120315090540.GW3852@pengutronix.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-10-git-send-email-thierry.reding@avionic-design.de>
 <4F61343A.80103@gmail.com>
 <20120315065631.GB20502@avionic-0098.mockup.avionic-design.de>
 <20120315090540.GW3852@pengutronix.de>
Message-ID: <20120315092134.GA29841@avionic-0098.adnet.avionic-design.de>

* Sascha Hauer wrote:
> On Thu, Mar 15, 2012 at 07:56:31AM +0100, Thierry Reding wrote:
> > Actually I wasn't planning on keeping this patch at all. Sascha already has
> > the existing PWM providers converted to his original framework and offered to
> > rebase them onto this series once the dust settles. I only used them as
> > testbed to see how the driver interface works out for different hardware. But
> > I also think that if Sascha hasn't cleaned the driver up yet it should either
> > be done in his conversion patches or as follow ups.
> 
> All I have is a simple conversion to the new framework, nothing more.  I
> rebased my patches yesterday onto this series (unfortunately due to the
> additional argument pwm_device the patches do not look like just moving
> the drivers anymore). I also skipped the PXA patch since I saw that you
> already have this one. I just posted the patches to the list.

Okay, I'll keep my Blackfin and PXA converted drivers then and will fix the
issues with the PXA driver brought up by Ryan. Would you be okay if I took
your conversion patches and added them to my series? I was trying to avoid
the additional work but I think it might make things easier if they are part
of the same series.

> > Sascha: how do you plan on going forward with this? It seems like the driver
> > interface is pretty much done now and I expect the next round to be the last,
> > unless I forget to properly work through the TODO list again. If you are busy
> > with other stuff I can probably find some time to help with porting your
> > converted drivers.
> 
> I haven't done drivers/mfd/twl6030-pwm.c. This one needs a bit more work
> as it currently does not register itself as a subdriver to the twl6030
> but just uses a globally available twl_i2c_write_u8() function. So if
> you have some time to spare it would be great if you could do this.

Okay, I'll have a look. I guess the next round won't be the last after all.
:-)

> > I'm also wondering which tree this will go in through. Does it make sense to
> > have an extra tree just for the PWM framework or can it go in via some other
> > general purpose tree? Who do I need to prod?
> 
> Good question, I don't know.

Okay, maybe Arnd can comment on it.

Thierry
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From arnd at arndb.de  Thu Mar 15 05:22:06 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 09:22:06 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <201203150922.06379.arnd@arndb.de>

On Thursday 15 March 2012, Nicolas Ferre wrote:
> Add some basic helpers to retrieve a DMA controller device_node and the
> DMA request specifications. By making DMA controllers register a generic
> translation function, we allow the management of any type of DMA requests
> specification.
> The void * output of an of_dma_xlate() function that will be implemented
> by the DMA controller can carry any type of "dma-request" argument.
> 
> The DMA client will search its associated DMA controller in the list and
> call the registered of_dam_xlate() function to retrieve the request values.
> 
> One simple xlate function is provided for the "single number" type of
> request binding.
> 
> This implementation is independent from dmaengine so it can also be used
> by legacy drivers.
> 
> For legacy reason another API will export the DMA request number into a
> Linux resource of type IORESOURCE_DMA.

This looks very good. I missed the first version of this patch, but was
thinking of very similar bindings.

> +Client drivers should specify the DMA request property using a phandle to
> +the controller. If needed, the DMA request identity on that controller is then
> +added followed by optional request specifications.
> +
> +Required property:
> +    - dma-request: List of phandle + dma-request + request specifications,
> +      one group per request "line".
> +Optional property:
> +    - dma-request-names: list of strings in the same order as the dma-request
> +      in the dma-request property.
> +
> +
> +Example:
> +
> +	i2c1: i2c at 1 {
> +		...
> +		dma-request = <&sdma 2 &sdma 3>;
> +		dma-request-names = "tx", "rx";
> +		...
> +	};

This is slightly different from how the proposed pwm binding works that
Thierry is working on, which uses an arbitrary property name instead of
requiring the use of a specific property but then allowing to give names
in another property.

I don't care much which way it's done, but please try to agree on one
approach that is used for both.

The one you have here is already used by reg and irq, while the other
one is used in gpio.

> +/**
> + * of_get_dma_request() - Get the associated DMA request data
> + * @np:		device node to get DMA request from
> + * @index:	index of the DMA request
> + * @out_data:	a output that can be filled in by the of_dma_xlate() function
> + *
> + * Returns return value of of_dma_xlate() and fills out_data (if provided).
> + * On error returns the appropriate errno value.
> + */

I would suggest provinding a helper function around this one that directly
calls __dma_request_channel(). AFAICT, you should be able to let the dma
controller provide a generic filter function in struct of_dma that the
driver can use by default.

	Arnd


From linux at arm.linux.org.uk  Thu Mar 15 05:21:40 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 09:21:40 +0000
Subject: Conflict between Versatile Express DT conversion and local
 timer updates
In-Reply-To: <20120315181718.d80071db25428a7b5113ef9a@canb.auug.org.au>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <201203131155.16454.arnd@arndb.de> <4F5F52A2.3050005@arm.com>
 <201203131433.07214.arnd@arndb.de>
 <CAOesGMjo=JT3TKwne+m5XUpkBMQFKQLZrr1T60m+Wx7YgqMiOA@mail.gmail.com>
 <4F605A3B.5030800@arm.com>
 <20120315181718.d80071db25428a7b5113ef9a@canb.auug.org.au>
Message-ID: <20120315092140.GA15988@n2100.arm.linux.org.uk>

On Thu, Mar 15, 2012 at 06:17:18PM +1100, Stephen Rothwell wrote:
> Hi all,
> 
> On Wed, 14 Mar 2012 08:43:39 +0000 Marc Zyngier <marc.zyngier at arm.com> wrote:
> >
> > On 14/03/12 00:52, Olof Johansson wrote:
> > > On Tue, Mar 13, 2012 at 7:33 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> > >> On Tuesday 13 March 2012, Marc Zyngier wrote:
> > >>> On 13/03/12 11:55, Arnd Bergmann wrote:
> > >>>> On Tuesday 13 March 2012, Marc Zyngier wrote:
> > >>>>> On 13/03/12 10:15, Russell King - ARM Linux wrote:
> > >>
> > >>>> d) create a new next/timer branch in arm-soc that has Pawel's
> > >>>>    98ed4ceb "ARM: vexpress: Get rid of MMIO_P2V" (the first patch from
> > >>>>    vexpress/dt, your patches and the ux500/timer series. Also put
> > >>>>    98ed4ceb into the next/cleanup branch.
> > >>>>
> > >>>> Any of those will work for us, my preference would be on #4. I have
> > >>>> created the next/timer branch in the arm-soc tree, so you can use
> > >>>> that and either rebase your patches on top or merge your tree into
> > >>>> it and fix up the merge conflicts.
> > >>>
> > >>> Thanks for doing that Arnd.
> > >>>
> > >>> I've thus created a new branch:
> > >>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> > >>> local_timers-for-arm-soc
> > >>>
> > >>> which contains the arm-soc next/timers branch as well as my local timers
> > >>> series. I'd greatly appreciate if you could pull it for 3.4.
> > >>>
> > >>
> > >> I've updated the next/timer branch with your changes now, but did not
> > >> put it into the for-next branch because Olof is currently handling that.
> > >>
> > >> Olof, can you add it to for-next please? The timer branch should have
> > >> no dependencies other than rmk/for-armsoc, so it can be fairly close to
> > >> the start.
> > > 
> > > 
> > > Thanks. I merged into for-next, but since there's already a history in
> > > there and I didn't rebuild it, it's on top of everything else.
> > > 
> > > I got two trivial merge conflicts (and a few that git sorted out
> > > automatically): one with the tegra makefile, the other with shmobile's
> > > timer init.
> > > 
> > > Marc, please take a look at the next/timers merge in the arm-soc
> > > for-next branch and let me know if they're OK. I'm pretty sure they
> > > are though.
> > 
> > Had a brief look, and it seems alright to me.
> > 
> > Thanks Olof!
> 
> ok, it looks like Marc's series is now in both the arm and arm-soc trees
> (and causing some conflicts due to other changes to the files involved
> and some resolved conflicts).

It shouldn't be in my tree anymore - I removed it a couple of days ago
and pushed that out.


From linux at arm.linux.org.uk  Thu Mar 15 05:26:52 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 09:26:52 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203150922.06379.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <201203150922.06379.arnd@arndb.de>
Message-ID: <20120315092652.GA16389@n2100.arm.linux.org.uk>

On Thu, Mar 15, 2012 at 09:22:06AM +0000, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Nicolas Ferre wrote:
> > Add some basic helpers to retrieve a DMA controller device_node and the
> > DMA request specifications. By making DMA controllers register a generic
> > translation function, we allow the management of any type of DMA requests
> > specification.
> > The void * output of an of_dma_xlate() function that will be implemented
> > by the DMA controller can carry any type of "dma-request" argument.
> > 
> > The DMA client will search its associated DMA controller in the list and
> > call the registered of_dam_xlate() function to retrieve the request values.
> > 
> > One simple xlate function is provided for the "single number" type of
> > request binding.
> > 
> > This implementation is independent from dmaengine so it can also be used
> > by legacy drivers.
> > 
> > For legacy reason another API will export the DMA request number into a
> > Linux resource of type IORESOURCE_DMA.
> 
> This looks very good. I missed the first version of this patch, but was
> thinking of very similar bindings.

There's one issue which is concerning me - when we switch OMAP to use
DMA engine, it won't use numeric stuff anymore but the DMA engine way
of requesting a channel (match function + data).

How does that fit into this scheme?


From viresh.kumar at st.com  Thu Mar 15 05:00:27 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 15 Mar 2012 14:30:27 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203150948.27918.sr@denx.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <4F604321.9000204@st.com> <201203150948.27918.sr@denx.de>
Message-ID: <4F61AFAB.6080301@st.com>

On 3/15/2012 2:18 PM, Stefan Roese wrote:
>>> > > +static const struct of_device_id vic_of_match[] __initconst = {
>>> > > +	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
>>> > > +	{ /* Sentinel */ }
>>> > > +};
>>> > > +
>>> > > +static void __init spear6xx_dt_init_irq(void)
>>> > > +{
>>> > > +	of_irq_init(vic_of_match);
>>> > > +}
>>> > > +
>> > 
>> > What about adding this routine in vic.c file, which can then be used
>> > by all platforms, instead of replicating this code.
> We can't move vic_of_match to the vic.c, since there are differences between 
> the boards using it. And only moving spear6xx_dt_init_irq() (renamed of 
> course) doesn't seem worth it.

I knew this. Actually my thought was, we have two compatible strings for vic:
pl190 and pl192.

So, create two vic_of_match* arrays and two vic*_dt_init_irq() routines.
That will solve the issue i believe.

-- 
viresh


From linux at arm.linux.org.uk  Thu Mar 15 05:36:15 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 09:36:15 +0000
Subject: Conflict between Versatile Express DT conversion and local
 timer updates
In-Reply-To: <20120315092140.GA15988@n2100.arm.linux.org.uk>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <201203131155.16454.arnd@arndb.de> <4F5F52A2.3050005@arm.com>
 <201203131433.07214.arnd@arndb.de>
 <CAOesGMjo=JT3TKwne+m5XUpkBMQFKQLZrr1T60m+Wx7YgqMiOA@mail.gmail.com>
 <4F605A3B.5030800@arm.com>
 <20120315181718.d80071db25428a7b5113ef9a@canb.auug.org.au>
 <20120315092140.GA15988@n2100.arm.linux.org.uk>
Message-ID: <20120315093615.GB15988@n2100.arm.linux.org.uk>

On Thu, Mar 15, 2012 at 09:21:40AM +0000, Russell King - ARM Linux wrote:
> It shouldn't be in my tree anymore - I removed it a couple of days ago
> and pushed that out.

Sorry, it didn't get pushed out (the last push was 10 mins before I
removed it.  So yes, you're right.  Should be gone in your next pull.


From prakash.pm at ti.com  Thu Mar 15 05:42:20 2012
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Thu, 15 Mar 2012 09:42:20 +0000
Subject: [PATCH] arm:da850: register musb device
In-Reply-To: <4F6081C3.4070905@mvista.com>
References: <1331651015-32586-1-git-send-email-prakash.pm@ti.com>
 <4F5F7F91.8010301@mvista.com>
 <A73F36158E33644199EB82C5EC81C7BC3178406C@DBDE01.ent.ti.com>
 <4F6081C3.4070905@mvista.com>
Message-ID: <A73F36158E33644199EB82C5EC81C7BC31784B33@DBDE01.ent.ti.com>

Hi Sergei,

On Wed, Mar 14, 2012 at 17:02:19, Sergei Shtylyov wrote:
> Hello.
> 
> On 14-03-2012 10:16, Manjunathappa, Prakash wrote:
> 
> >>> Properly set up the OTG mode thru the CFGCHIP2 register, enable the
> >>> USB0_DRVVBUS pin,
> 
> >>      I don't see where you are enabling it.
> 
> > Yes, I will correct the message.
> 
> >>> and finally register the MUSB platform device.
> 
>     Also, you're registering the MUSB device for DA850/OMAP-L138 EVM board, 
> not the whole DA850/OMAP-L138 SoC, so that should be reflected in the subject.
> 

True, I will fix the subject.

Thanks,
Prakash

> >>> Signed-off-by: Ajay Kumar Gupta<ajay.gupta at ti.com>
> >>> Signed-off-by: Manjunathappa, Prakash<prakash.pm at ti.com>
> 
> WBR, Sergei
> 



From s.hauer at pengutronix.de  Thu Mar 15 05:43:57 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 15 Mar 2012 10:43:57 +0100
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zMT4vK7WPF7iEH9kN6GHHAv-LChHoadzieqV-Wd3Qj=WQ@mail.gmail.com>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
 <20120311113414.GM3852@pengutronix.de>
 <CAJOA=zMdkLB-DCPOk=kz5mn6BK6A_swocyCHJHeGE6H7FxBbmQ@mail.gmail.com>
 <20120312115117.GN3852@pengutronix.de>
 <CAJOA=zPx0ARsoO4ueSTMe_z2Gs4xG4P2qn1=-vHFf7_k=+K6hQ@mail.gmail.com>
 <20120313120507.GS3852@pengutronix.de>
 <CAJOA=zMT4vK7WPF7iEH9kN6GHHAv-LChHoadzieqV-Wd3Qj=WQ@mail.gmail.com>
Message-ID: <20120315094357.GX3852@pengutronix.de>

On Wed, Mar 14, 2012 at 05:51:48PM -0700, Turquette, Mike wrote:
> On Tue, Mar 13, 2012 at 5:05 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > On Mon, Mar 12, 2012 at 08:16:36PM -0700, Turquette, Mike wrote:
> >> On Mon, Mar 12, 2012 at 4:51 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> >> > I tried another
> >> > approach on the weekend which basically does not try to do all in a
> >> > single recursion but instead sets the rate in multiple steps:
> >> >
> >> > 1) call a function which calculates all new rates of affected clocks
> >> > ? in a rate change and safes the value in a clk->new_rate field. This
> >> > ? function returns the topmost clock which has to be changed.
> >> > 2) starting from the topmost clock notify all clients. This walks the
> >> > ? whole subtree even if a notfifier refuses the change. If necessary
> >> > ? we can walk the whole subtree again to abort the change.
> >> > 3) actually change rates starting from the topmost clocks and notify
> >> > ? all clients on the way. I changed the set_rate callback to void.
> >> > ? Instead of failing (what is failing in case of set_rate? The clock
> >> > ? will still have some rate) I check for the result with
> >> > ? clk_ops->recalc_rate.
> >
> > The way described above works for me now, see this branch:
> >
> > git://git.pengutronix.de/git/imx/linux-2.6.git v3.3-rc6-clkv6-fixup
> >
> > You may not necessarily like it as it changes quite a lot in the rate
> > changing code.
> 
> I tried that code and I really like it!  It is much more readable and
> feels less "fragile" than the previous recursive __clk_set_rate.  I
> did quite a bit of testing with this code today.  One of the tests
> looks like this:
> 
>     pll         (adjustable to anything)
>      |
> clk_divider     (5 bits wide)
>      |
>    dummy        (no clk_ops)
> 
> The new code did a fine job arbitrating rates for the PLL and the
> intermediate divider even if I put weird constraints on the PLL.  For
> instance if I artificially limited it to a minimum of 600MHz and then
> ran clk_set_rate(dummy, 300MHz) it would lock at 600MHz and set
> clk_divider to divide-by-2.  Setting to 600MHz or more set the divider
> back to 1 and relocked the PLL appropriately.  Pretty cool.
> 
> I also tested the notifiers with this code and they seem to function
> properly.  I'll take this code in for v7.  Thanks a lot for this
> helpful contribution.
> 
> I did find that MULT_ROUND_UP caused trouble for my PLL's round_rate
> implementation.  Maybe my PLL code is fragile but a quick fix was to
> make sure that we send the exact value we want to the round_rate code.
>  I also feel this is more correct.  Let me know what you think:
> 
> 8<---------------------------------------------------------------
> 
> commit 189fecedb175d0366759246c4192f45b0bc39a50
> Author: Mike Turquette <mturquette at linaro.org>
> Date:   Wed Mar 14 17:29:51 2012 -0700
> 
>     clk-divider.c: round the actual rate we care about
> 
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 86ca9cd..06ef4a0 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -47,12 +47,6 @@ static unsigned long clk_divider_recalc_rate(struct
> clk_hw *hw,
>  }
>  EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
> 
> -/*
> - * The reverse of DIV_ROUND_UP: The maximum number which
> - * divided by m is r
> - */
> -#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
> -
>  static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
>  		unsigned long *best_parent_rate)
>  {
> @@ -84,9 +78,9 @@ static int clk_divider_bestdiv(struct clk_hw *hw,
> unsigned long rate,
> 
>  	for (i = 1; i <= maxdiv; i++) {
>  		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
> -				MULT_ROUND_UP(rate, i));
> +				(rate * i));

I think MULT_ROUND_UP is the right thing to use here (not sure if this
is a good name though)
Consider we want to have an output rate of 33Hz. Now acceptable input
rates for a divider value of 3 would be 99, 100 and 101Hz, so we have
to call round_rate for the parent with 101Hz which includes 100 and
99Hz.

If you have problems with your PLL than most likely because it does
something different on clk_round_rate than it does in clk_set_rate,
for example clk_round_rate(10000) returns 10000, but clk_set_rate then
sets the rate 9999 due to some rounding error. Being consistent between
round_rate and set_rate is very important for this mechanism to work
properly. It did cost me some nerves to get it right for the divider
(and even more nerves to figure out why it is correct the way it works)

>  		now = parent_rate / i;
> -		if (now <= rate && now >= best) {
> +		if (now <= rate && now > best) {

This change is an optimization, but should be unrelated to your PLL
problem, right?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From sfr at canb.auug.org.au  Thu Mar 15 05:44:08 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 15 Mar 2012 20:44:08 +1100
Subject: Conflict between Versatile Express DT conversion and local
 timer updates
In-Reply-To: <20120315093615.GB15988@n2100.arm.linux.org.uk>
References: <20120312231016.GC10830@n2100.arm.linux.org.uk>
 <201203131155.16454.arnd@arndb.de> <4F5F52A2.3050005@arm.com>
 <201203131433.07214.arnd@arndb.de>
 <CAOesGMjo=JT3TKwne+m5XUpkBMQFKQLZrr1T60m+Wx7YgqMiOA@mail.gmail.com>
 <4F605A3B.5030800@arm.com>
 <20120315181718.d80071db25428a7b5113ef9a@canb.auug.org.au>
 <20120315092140.GA15988@n2100.arm.linux.org.uk>
 <20120315093615.GB15988@n2100.arm.linux.org.uk>
Message-ID: <20120315204408.457caee20a959d8172e6ba97@canb.auug.org.au>

Hi Russell,

On Thu, 15 Mar 2012 09:36:15 +0000 Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
>
> On Thu, Mar 15, 2012 at 09:21:40AM +0000, Russell King - ARM Linux wrote:
> > It shouldn't be in my tree anymore - I removed it a couple of days ago
> > and pushed that out.
> 
> Sorry, it didn't get pushed out (the last push was 10 mins before I
> removed it.  So yes, you're right.  Should be gone in your next pull.

Thanks for that.

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From s.hauer at pengutronix.de  Thu Mar 15 05:45:27 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 15 Mar 2012 10:45:27 +0100
Subject: [PATCH v4 09/10] pwm: Add PXA support
In-Reply-To: <20120315092134.GA29841@avionic-0098.adnet.avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-10-git-send-email-thierry.reding@avionic-design.de>
 <4F61343A.80103@gmail.com>
 <20120315065631.GB20502@avionic-0098.mockup.avionic-design.de>
 <20120315090540.GW3852@pengutronix.de>
 <20120315092134.GA29841@avionic-0098.adnet.avionic-design.de>
Message-ID: <20120315094527.GY3852@pengutronix.de>

On Thu, Mar 15, 2012 at 10:21:34AM +0100, Thierry Reding wrote:
> * Sascha Hauer wrote:
> > On Thu, Mar 15, 2012 at 07:56:31AM +0100, Thierry Reding wrote:
> > > Actually I wasn't planning on keeping this patch at all. Sascha already has
> > > the existing PWM providers converted to his original framework and offered to
> > > rebase them onto this series once the dust settles. I only used them as
> > > testbed to see how the driver interface works out for different hardware. But
> > > I also think that if Sascha hasn't cleaned the driver up yet it should either
> > > be done in his conversion patches or as follow ups.
> > 
> > All I have is a simple conversion to the new framework, nothing more.  I
> > rebased my patches yesterday onto this series (unfortunately due to the
> > additional argument pwm_device the patches do not look like just moving
> > the drivers anymore). I also skipped the PXA patch since I saw that you
> > already have this one. I just posted the patches to the list.
> 
> Okay, I'll keep my Blackfin and PXA converted drivers then and will fix the
> issues with the PXA driver brought up by Ryan. Would you be okay if I took
> your conversion patches and added them to my series?

Sure, go ahead.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From laurent.pinchart at ideasonboard.com  Thu Mar 15 05:51:06 2012
From: laurent.pinchart at ideasonboard.com (Laurent Pinchart)
Date: Thu, 15 Mar 2012 10:51:06 +0100
Subject: linux-next: manual merge of the arm-soc tree with Linus' tree
In-Reply-To: <20120315175000.897f1172c296d4a687be0537@canb.auug.org.au>
References: <20120315175000.897f1172c296d4a687be0537@canb.auug.org.au>
Message-ID: <1362815.uO65s14ojU@avalon>

Hi Stephen,

On Thursday 15 March 2012 17:50:00 Stephen Rothwell wrote:
> Hi all,
> 
> Today's linux-next merge of the arm-soc tree got a conflict in
> arch/arm/mach-shmobile/board-mackerel.c between commit 1740d3448012
> ("ARM: mach-shmobile: mackerel: Reserve DMA memory for the frame buffer")
> from Linus' tree and commit 5d7220ec000f ("ARM: mach-shmobile: sh7372
> map_io and init_early update") from the arm-soc tree.
> 
> The latter moved the code to another file
> arch/arm/mach-shmobile/setup-sh7372.c and I have no idea how to fix this
> up, so I just removed the change done by the former.

The following patch (5d7220ec000f rebased on top of 1740d3448012) shows the
correct conflict resolution in my opinion.

>From f040ba69632a54c86767974768d68b308901061c Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm at opensource.se>
Date: Wed, 29 Feb 2012 12:37:19 +0900
Subject: [PATCH] ARM: mach-shmobile: sh7372 map_io and init_early update

ARM: mach-shmobile: sh7372 map_io and init_early update

Update the sh7372 SoC and the AP4EVB and Mackerel boards to make use
of the functions sh7372_map_io() and sh7372_add_early_devices().

Signed-off-by: Magnus Damm <damm at opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw at sisk.pl>
Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
---
 arch/arm/mach-shmobile/board-ap4evb.c        |   25 ++-----------------------
 arch/arm/mach-shmobile/board-mackerel.c      |   21 +++------------------
 arch/arm/mach-shmobile/include/mach/common.h |    1 +
 arch/arm/mach-shmobile/setup-sh7372.c        |   22 ++++++++++++++++++++++
 4 files changed, 28 insertions(+), 41 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index eeb4d96..c57ded1 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -61,7 +61,6 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/setup.h>
 
@@ -1190,27 +1189,6 @@ static struct i2c_board_info i2c1_devices[] = {
 	},
 };
 
-static struct map_desc ap4evb_io_desc[] __initdata = {
-	/* create a 1:1 entity map for 0xe6xxxxxx
-	 * used by CPGA, INTC and PFC.
-	 */
-	{
-		.virtual	= 0xe6000000,
-		.pfn		= __phys_to_pfn(0xe6000000),
-		.length		= 256 << 20,
-		.type		= MT_DEVICE_NONSHARED
-	},
-};
-
-static void __init ap4evb_map_io(void)
-{
-	iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
-
-	/* setup early devices and console here as well */
-	sh7372_add_early_devices();
-	shmobile_setup_console();
-}
-
 #define GPIO_PORT9CR	0xE6051009
 #define GPIO_PORT10CR	0xE605100A
 #define USCCR1		0xE6058144
@@ -1469,7 +1447,8 @@ static struct sys_timer ap4evb_timer = {
 };
 
 MACHINE_START(AP4EVB, "ap4evb")
-	.map_io		= ap4evb_map_io,
+	.map_io		= sh7372_map_io,
+	.init_early	= sh7372_add_early_devices,
 	.init_irq	= sh7372_init_irq,
 	.handle_irq	= shmobile_handle_irq_intc,
 	.init_machine	= ap4evb_init,
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 7b53cda..b5bbab7 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -58,7 +58,6 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <asm/mach/map.h>
 #include <asm/mach-types.h>
 
 /*
@@ -1337,29 +1336,14 @@ static struct i2c_board_info i2c1_devices[] = {
 	},
 };
 
-static struct map_desc mackerel_io_desc[] __initdata = {
-	/* create a 1:1 entity map for 0xe6xxxxxx
-	 * used by CPGA, INTC and PFC.
-	 */
-	{
-		.virtual	= 0xe6000000,
-		.pfn		= __phys_to_pfn(0xe6000000),
-		.length		= 256 << 20,
-		.type		= MT_DEVICE_NONSHARED
-	},
-};
-
 static void __init mackerel_map_io(void)
 {
-	iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
+	sh7372_map_io();
+
 	/* DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
 	 * enough to allocate the frame buffer memory.
 	 */
 	init_consistent_dma_size(12 << 20);
-
-	/* setup early devices and console here as well */
-	sh7372_add_early_devices();
-	shmobile_setup_console();
 }
 
 #define GPIO_PORT9CR	0xE6051009
@@ -1592,6 +1576,7 @@ static struct sys_timer mackerel_timer = {
 
 MACHINE_START(MACKEREL, "mackerel")
 	.map_io		= mackerel_map_io,
+	.init_early	= sh7372_add_early_devices,
 	.init_irq	= sh7372_init_irq,
 	.handle_irq	= shmobile_handle_irq_intc,
 	.init_machine	= mackerel_init,
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index e4b945e..b327402 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -30,6 +30,7 @@ extern struct clk sh7377_extalc1_clk;
 extern struct clk sh7377_extal2_clk;
 
 extern void sh7372_init_irq(void);
+extern void sh7372_map_io(void);
 extern void sh7372_add_early_devices(void);
 extern void sh7372_add_standard_devices(void);
 extern void sh7372_clock_init(void);
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index a83cf51..12b4378 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -33,9 +33,28 @@
 #include <linux/pm_domain.h>
 #include <mach/hardware.h>
 #include <mach/sh7372.h>
+#include <mach/common.h>
+#include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+static struct map_desc sh7372_io_desc[] __initdata = {
+	/* create a 1:1 entity map for 0xe6xxxxxx
+	 * used by CPGA, INTC and PFC.
+	 */
+	{
+		.virtual	= 0xe6000000,
+		.pfn		= __phys_to_pfn(0xe6000000),
+		.length		= 256 << 20,
+		.type		= MT_DEVICE_NONSHARED
+	},
+};
+
+void __init sh7372_map_io(void)
+{
+	iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
+}
+
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
 	.mapbase	= 0xe6c40000,
@@ -1049,4 +1068,7 @@ void __init sh7372_add_early_devices(void)
 {
 	early_platform_add_devices(sh7372_early_devices,
 				   ARRAY_SIZE(sh7372_early_devices));
+
+	/* setup early console here as well */
+	shmobile_setup_console();
 }

-- 
Regards,

Laurent Pinchart



From s.hauer at pengutronix.de  Thu Mar 15 05:52:31 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 15 Mar 2012 10:52:31 +0100
Subject: [alsa-devel] [PATCH v4] ASoC: add imx-sgtl5000 machine driver
 working with fsl_ssi
In-Reply-To: <4F612394.4060703@freescale.com>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
 <20120314090115.GN3852@pengutronix.de>
 <4F612394.4060703@freescale.com>
Message-ID: <20120315095230.GZ3852@pengutronix.de>

On Wed, Mar 14, 2012 at 06:02:44PM -0500, Timur Tabi wrote:
> Sascha Hauer wrote:
> > What are the next steps here? Now we have fsl_ssi.c and imx-ssi.c, one
> > for dt bindings and the other one for platform bindings and also AC97
> > support. They should probably get merged some day which might be a bit
> > difficult since currently I don't see the platform users moving over
> > to devicetree and the seem to be no AC97 users in powerpc.
> 
> I don't have any problem with adding AC97 support to fsl_ssi.c, assuming
> it's not a huge mess.  I don't know enough about AC97 to know how easy
> that is, though.

>From the hardware side it's basically calling setup_channel_to_ac97()
and providing AC97 register read/write functions. One ugly detail is
that we need a bus reset function. This basically means putting the
pins in gpio mode and issuing the reset manually. The SSI unit does
not provide a way to reset the bus.
I don't know how this AC97 stuff integrates into the devicetree. Anyway,
that's a topic for future discussions and shouldn't block the current
patches. I just want to make sure that the original imx-ssi driver is
not removed as long as the fsl_ssi driver does not have AC97 support.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Thu Mar 15 06:09:23 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 10:09:23 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120315092652.GA16389@n2100.arm.linux.org.uk>
References: <4F22DEF2.5000807@ti.com> <201203150922.06379.arnd@arndb.de>
 <20120315092652.GA16389@n2100.arm.linux.org.uk>
Message-ID: <201203151009.24161.arnd@arndb.de>

On Thursday 15 March 2012, Russell King - ARM Linux wrote:
> On Thu, Mar 15, 2012 at 09:22:06AM +0000, Arnd Bergmann wrote:
> > On Thursday 15 March 2012, Nicolas Ferre wrote:
> > > Add some basic helpers to retrieve a DMA controller device_node and the
> > > DMA request specifications. By making DMA controllers register a generic
> > > translation function, we allow the management of any type of DMA requests
> > > specification.
> > > The void * output of an of_dma_xlate() function that will be implemented
> > > by the DMA controller can carry any type of "dma-request" argument.
> > > 
> > > The DMA client will search its associated DMA controller in the list and
> > > call the registered of_dam_xlate() function to retrieve the request values.
> > > 
> > > One simple xlate function is provided for the "single number" type of
> > > request binding.
> > > 
> > > This implementation is independent from dmaengine so it can also be used
> > > by legacy drivers.
> > > 
> > > For legacy reason another API will export the DMA request number into a
> > > Linux resource of type IORESOURCE_DMA.
> > 
> > This looks very good. I missed the first version of this patch, but was
> > thinking of very similar bindings.
> 
> There's one issue which is concerning me - when we switch OMAP to use
> DMA engine, it won't use numeric stuff anymore but the DMA engine way
> of requesting a channel (match function + data).
> 
> How does that fit into this scheme?

I haven't looked at the omap dma driver much, but if it just uses a
channel number, then I'd assume the data would be a single u32 cell
with that number, and the match function would be trivial.

Is that what you are asking about or am I missing the point?

	Arnd


From broonie at opensource.wolfsonmicro.com  Thu Mar 15 06:18:37 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 15 Mar 2012 10:18:37 +0000
Subject: [alsa-devel] [PATCH v4] ASoC: add imx-sgtl5000 machine driver
 working with fsl_ssi
In-Reply-To: <20120315095230.GZ3852@pengutronix.de>
References: <1331553537-19789-1-git-send-email-shawn.guo@linaro.org>
 <20120314090115.GN3852@pengutronix.de>
 <4F612394.4060703@freescale.com>
 <20120315095230.GZ3852@pengutronix.de>
Message-ID: <20120315101836.GA3138@opensource.wolfsonmicro.com>

On Thu, Mar 15, 2012 at 10:52:31AM +0100, Sascha Hauer wrote:

> I don't know how this AC97 stuff integrates into the devicetree. Anyway,
> that's a topic for future discussions and shouldn't block the current
> patches. I just want to make sure that the original imx-ssi driver is
> not removed as long as the fsl_ssi driver does not have AC97 support.

AC'97 should be hotpluggable once you know the controller is there.
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From thierry.reding at avionic-design.de  Thu Mar 15 06:27:36 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Thu, 15 Mar 2012 11:27:36 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203150922.06379.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <201203150922.06379.arnd@arndb.de>
Message-ID: <20120315102736.GA25371@avionic-0098.adnet.avionic-design.de>

* Arnd Bergmann wrote:
> On Thursday 15 March 2012, Nicolas Ferre wrote:
[...]
> > +	i2c1: i2c at 1 {
> > +		...
> > +		dma-request = <&sdma 2 &sdma 3>;
> > +		dma-request-names = "tx", "rx";
> > +		...
> > +	};
> 
> This is slightly different from how the proposed pwm binding works that
> Thierry is working on, which uses an arbitrary property name instead of
> requiring the use of a specific property but then allowing to give names
> in another property.
> 
> I don't care much which way it's done, but please try to agree on one
> approach that is used for both.
> 
> The one you have here is already used by reg and irq, while the other
> one is used in gpio.

I think we can just use pwm as the fixed property name. Or alternatively do
something along the lines of the regulator bindings, where we use "-pwm" as
the suffix for specifying PWM devices. For instance if a named PWM is
requested, the OF support code would look for a <name>-pwm property, while
requesting an unnamed PWM would simply look at the pwm property.

When it comes to the labelling of PWM devices, I don't think both variants
are exclusive. Currently the PWM framework uses name of the user OF device
node for the PWM label. That is, if I have the following in the DTS:

	pwm {
		...
	};

	backlight {
		compatible = "pwm-backlight";
		pwm = <&pwm 0 5000000>;
		...
	};

Then the PWM will be labelled "backlight":

	$ cat cat /sys/kernel/debug/pwm
	platform/tegra-pwm, 4 PWM devices
	pwm-0   (backlight           ): requested enabled
	pwm-1   ((null)              ):
	pwm-2   ((null)              ):
	pwm-3   ((null)              ):

So if we decide to explicitly allow specifying names, then we can always add
a pwm-names property (or <name>-pwm-names respectively) to use as label and
fallback to the user OF device node name if that property is not present.

Thierry
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From linux at arm.linux.org.uk  Thu Mar 15 06:28:45 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 10:28:45 +0000
Subject: Lost fixes?
Message-ID: <20120315102845.GB16389@n2100.arm.linux.org.uk>

These fixes are a collection from other people which resolve various
issues found with the new kautobuilder.  They're now a month old, and
as far as I can see, have not been merged into Linus' tree.

What's the status of them, and when are they going to be merged?

Thanks.

 arch/arm/mach-omap2/Makefile                 |    5 +----
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c |    2 +-
 arch/arm/mach-omap2/clock.c                  |    2 +-
 arch/arm/mach-omap2/clock.h                  |    2 +-
 arch/arm/mach-omap2/smartreflex.c            |    2 +-
 arch/arm/plat-omap/clock.c                   |    2 +-
 arch/arm/plat-omap/dma.c                     |    2 +-
 arch/arm/plat-omap/include/plat/clock.h      |    4 ++--
 drivers/cpufreq/Kconfig.arm                  |    6 ++++++
 drivers/cpufreq/Makefile                     |    2 +-
 drivers/mfd/da9052-spi.c                     |    4 ++--
 kernel/irq/chip.c                            |    3 +--
 12 files changed, 19 insertions(+), 17 deletions(-)



From broonie at opensource.wolfsonmicro.com  Thu Mar 15 06:29:45 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 15 Mar 2012 10:29:45 +0000
Subject: [PATCH v4 03/10] pwm: Add device tree support
In-Reply-To: <201203150840.42659.arnd@arndb.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-4-git-send-email-thierry.reding@avionic-design.de>
 <201203150840.42659.arnd@arndb.de>
Message-ID: <20120315102944.GB3138@opensource.wolfsonmicro.com>

On Thu, Mar 15, 2012 at 08:40:42AM +0000, Arnd Bergmann wrote:
> On Wednesday 14 March 2012, Thierry Reding wrote:

> > +static struct pwm_chip *of_node_to_pwmchip(struct device_node *np)
> > +{

> > +	return ERR_PTR(-EPROBE_DEFER);
> > +}

> EPROBE_DEFER doesn't exist yet in my kernel, and I wonder if it's actually
> safe to be used this way, because it can result in arbitrary drivers using
> this to be put on the defered probe list. It certainly sounds like the
> right thing to do in the long run though.

Similar code is going in for regulators in 3.4 along with the core
-EPROBE_DEFER change (though not OF specific) and I sent a similar patch
for GPIOs too, hopefully Grant will ack it in time for it to make it in.

My theory is that since you need to explicitly know that the thing
you're requesting is there in order to request it (eg, have a PWM number
or DT link) the overwhemlingly common case for a failure to request will
be that the provider didn't register yet which is exactly the case where
deferral is desired.  It therefore seems sensible to have the framework
default the drivers to retrying rather than have almost every individual
driver look at the failure, figure out if it was a missing provider, and
then retry.  Drivers that have a good reason to fail can always check
for -EPROBE_DEFER and override it.

The result should be that we can take advantage of probe deferral over
large areas of the kernel without having to go and explicitly modify so
many drivers - if the frameworks like GPIO, clk and regulator can do
this that ought to cover 90% of the cases where probe deferral will be
needed without having to do anything more than have good error handling
paths on probe which is a good idea anyway.
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From rmk+kernel at arm.linux.org.uk  Thu Mar 15 06:30:19 2012
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 15 Mar 2012 10:30:19 +0000
Subject: [PATCH 4/6] ARM: OMAP: fix missing __devexit_p() annotations
In-Reply-To: <20120315102845.GB16389@n2100.arm.linux.org.uk>
References: <20120315102845.GB16389@n2100.arm.linux.org.uk>
Message-ID: <E1S87wp-0000Mz-V8@rmk-PC.arm.linux.org.uk>

Missing __devexit_p() annotations in driver structures for remove functions
marked with __devexit is waiting for build errors to happen, such as:

`omap_system_dma_remove' referenced in section `.data' of arch/arm/plat-omap/bui
lt-in.o: defined in discarded section `.devexit.text' of arch/arm/plat-omap/buil
t-in.o

Add the necessary annotation, and as a result of audit, fix others which
are also missing in arch/arm/*omap*.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/smartreflex.c |    2 +-
 arch/arm/plat-omap/dma.c          |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 7e755bb..47c77a1 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -1012,7 +1012,7 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
 }
 
 static struct platform_driver smartreflex_driver = {
-	.remove         = omap_sr_remove,
+	.remove         = __devexit_p(omap_sr_remove),
 	.driver		= {
 		.name	= "smartreflex",
 	},
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 002fb4d..cb856fe 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2125,7 +2125,7 @@ static int __devexit omap_system_dma_remove(struct platform_device *pdev)
 
 static struct platform_driver omap_system_dma_driver = {
 	.probe		= omap_system_dma_probe,
-	.remove		= omap_system_dma_remove,
+	.remove		= __devexit_p(omap_system_dma_remove),
 	.driver		= {
 		.name	= "omap_dma_system"
 	},
-- 
1.7.4.4



From paul at pwsan.com  Thu Mar 15 06:30:40 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 15 Mar 2012 10:30:40 +0000
Subject: [PATCH 5/6] ARM: OMAP2+: I2C: always compile I2C reset code, even if
 I2C driver is not built
In-Reply-To: <20120315102845.GB16389@n2100.arm.linux.org.uk>
References: <20120315102845.GB16389@n2100.arm.linux.org.uk>
Message-ID: <E1S87xA-0000N4-2z@rmk-PC.arm.linux.org.uk>

During kernel init, we reset all IP blocks on the OMAP that we can,
even if there is no driver compiled for that IP block.  Unlike most IP
blocks, the I2C block requires some extra programming for this to
work.  This reset code is incorrectly omitted when the I2C driver is
deselected.  In this circumstance, the build breaks.  Fix by compiling
the I2C reset code unconditionally.

Problem reported by Russell King <linux at arm.linux.org.uk>.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/mach-omap2/Makefile |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index bd76394..56a6e98 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-	 common.o gpio.o dma.o wd_timer.o display.o
+	 common.o gpio.o dma.o wd_timer.o display.o i2c.o
 
 omap-2-3-common				= irq.o sdrc.o
 hwmod-common				= omap_hwmod.o \
@@ -182,9 +182,6 @@ obj-$(CONFIG_OMAP_IOMMU)		+= iommu2.o
 iommu-$(CONFIG_OMAP_IOMMU)		:= omap-iommu.o
 obj-y					+= $(iommu-m) $(iommu-y)
 
-i2c-omap-$(CONFIG_I2C_OMAP)		:= i2c.o
-obj-y					+= $(i2c-omap-m) $(i2c-omap-y)
-
 ifneq ($(CONFIG_TIDSPBRIDGE),)
 obj-y					+= dsp.o
 endif
-- 
1.7.4.4



From rmk+kernel at arm.linux.org.uk  Thu Mar 15 06:31:00 2012
From: rmk+kernel at arm.linux.org.uk (Russell King)
Date: Thu, 15 Mar 2012 10:31:00 +0000
Subject: [PATCH 6/6] ARM: OMAP: fix cpufreq build
In-Reply-To: <20120315102845.GB16389@n2100.arm.linux.org.uk>
References: <20120315102845.GB16389@n2100.arm.linux.org.uk>
Message-ID: <E1S87xU-0000N8-6u@rmk-PC.arm.linux.org.uk>

OMAPs cpufreq requires the frequency table support, but nothing ensures
that this is selected.  This can result in configurations which fail to
build:

drivers/built-in.o:(.data+0x5238): undefined reference to `cpufreq_freq_attr_scaling_available_freqs'
drivers/cpufreq/omap-cpufreq.c:88: undefined reference to `cpufreq_frequency_table_target'
drivers/cpufreq/omap-cpufreq.c:60: undefined reference to `cpufreq_frequency_table_verify'
drivers/cpufreq/omap-cpufreq.c:186: undefined reference to `cpufreq_frequency_table_cpuinfo'
drivers/cpufreq/omap-cpufreq.c:190: undefined reference to `cpufreq_frequency_table_get_attr'

Fix this by introducing a new configuration variable and having that
select CPU_FREQ_TABLE.

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c |    2 +-
 arch/arm/mach-omap2/clock.c                  |    2 +-
 arch/arm/mach-omap2/clock.h                  |    2 +-
 arch/arm/plat-omap/clock.c                   |    2 +-
 arch/arm/plat-omap/include/plat/clock.h      |    4 ++--
 drivers/cpufreq/Kconfig.arm                  |    5 +++++
 drivers/cpufreq/Makefile                     |    2 +-
 7 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 39f9d5a..4705b50 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -165,7 +165,7 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 	return 0;
 }
 
-#ifdef CONFIG_CPU_FREQ
+#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
 /*
  * Walk PRCM rate table and fillout cpufreq freq_table
  * XXX This should be replaced by an OPP layer in the near future
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index f57ed5b..450feb0 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -536,7 +536,7 @@ struct clk_functions omap2_clk_functions = {
 	.clk_set_rate		= omap2_clk_set_rate,
 	.clk_set_parent		= omap2_clk_set_parent,
 	.clk_disable_unused	= omap2_clk_disable_unused,
-#ifdef CONFIG_CPU_FREQ
+#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
 	/* These will be removed when the OPP code is integrated */
 	.clk_init_cpufreq_table	= omap2_clk_init_cpufreq_table,
 	.clk_exit_cpufreq_table	= omap2_clk_exit_cpufreq_table,
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b8c2a68..f331cfc 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -146,7 +146,7 @@ extern const struct clksel_rate gpt_sys_rates[];
 extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 
-#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
+#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_ARM_OMAP2PLUS_CPUFREQ)
 extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #else
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 567e4b5..2e2efb6 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -399,7 +399,7 @@ struct clk dummy_ck = {
 	.ops	= &clkops_null,
 };
 
-#ifdef CONFIG_CPU_FREQ
+#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
 void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 {
 	unsigned long flags;
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 240a7b9..879ba27 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -283,7 +283,7 @@ struct clk_functions {
 	void		(*clk_allow_idle)(struct clk *clk);
 	void		(*clk_deny_idle)(struct clk *clk);
 	void		(*clk_disable_unused)(struct clk *clk);
-#ifdef CONFIG_CPU_FREQ
+#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
 	void		(*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
 	void		(*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
 #endif
@@ -301,7 +301,7 @@ extern void recalculate_root_clocks(void);
 extern unsigned long followparent_recalc(struct clk *clk);
 extern void clk_enable_init_clocks(void);
 unsigned long omap_fixed_divisor_recalc(struct clk *clk);
-#ifdef CONFIG_CPU_FREQ
+#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index c8bde43..74e8b55 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -2,6 +2,11 @@
 # ARM CPU Frequency scaling drivers
 #
 
+config ARM_OMAP2PLUS_CPUFREQ
+	bool
+	depends on ARCH_OMAP2PLUS
+	select CPU_FREQ_TABLE
+
 config ARM_S3C64XX_CPUFREQ
 	bool "Samsung S3C64XX"
 	depends on CPU_S3C6410
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index ac000fa..fda94c7 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -44,7 +44,7 @@ obj-$(CONFIG_ARM_S3C64XX_CPUFREQ)	+= s3c64xx-cpufreq.o
 obj-$(CONFIG_ARM_S5PV210_CPUFREQ)	+= s5pv210-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
-obj-$(CONFIG_ARCH_OMAP2PLUS)            += omap-cpufreq.o
+obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)     += omap-cpufreq.o
 
 ##################################################################################
 # PowerPC platform drivers
-- 
1.7.4.4



From sameo at linux.intel.com  Thu Mar 15 06:44:50 2012
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Thu, 15 Mar 2012 11:44:50 +0100
Subject: Lost fixes?
In-Reply-To: <20120315102845.GB16389@n2100.arm.linux.org.uk>
References: <20120315102845.GB16389@n2100.arm.linux.org.uk>
Message-ID: <20120315104450.GA20705@sortiz-mobl>

On Thu, Mar 15, 2012 at 10:28:45AM +0000, Russell King - ARM Linux wrote:
> These fixes are a collection from other people which resolve various
> issues found with the new kautobuilder.  They're now a month old, and
> as far as I can see, have not been merged into Linus' tree.
> 
> What's the status of them, and when are they going to be merged?
For the drivers/mfd/da9052-spi.c part: A patch from Axel Lin has been living
in my for-next branch for a while now. It's a section mismatch warning fix, so
not something I consider worth sending to Linus after the merge window is
closed. So it's queued for the next one.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From sr at denx.de  Thu Mar 15 06:38:51 2012
From: sr at denx.de (Stefan Roese)
Date: Thu, 15 Mar 2012 11:38:51 +0100
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <4F61AFAB.6080301@st.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203150948.27918.sr@denx.de> <4F61AFAB.6080301@st.com>
Message-ID: <201203151138.51508.sr@denx.de>

On Thursday 15 March 2012 10:00:27 Viresh Kumar wrote:
> On 3/15/2012 2:18 PM, Stefan Roese wrote:
> >>> > > +static const struct of_device_id vic_of_match[] __initconst = {
> >>> > > +	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
> >>> > > +	{ /* Sentinel */ }
> >>> > > +};
> >>> > > +
> >>> > > +static void __init spear6xx_dt_init_irq(void)
> >>> > > +{
> >>> > > +	of_irq_init(vic_of_match);
> >>> > > +}
> >>> > > +
> >> > 
> >> > What about adding this routine in vic.c file, which can then be used
> >> > by all platforms, instead of replicating this code.
> > 
> > We can't move vic_of_match to the vic.c, since there are differences
> > between the boards using it. And only moving spear6xx_dt_init_irq()
> > (renamed of course) doesn't seem worth it.
> 
> I knew this. Actually my thought was, we have two compatible strings for
> vic: pl190 and pl192.
> 
> So, create two vic_of_match* arrays and two vic*_dt_init_irq() routines.
> That will solve the issue i believe.

I still don't think its worth it. But please feel free to send an add-on 
patch, to "clean this up".

Thanks,
Stefan


From viresh.kumar at st.com  Thu Mar 15 06:40:27 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 15 Mar 2012 16:10:27 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203151138.51508.sr@denx.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203150948.27918.sr@denx.de> <4F61AFAB.6080301@st.com>
 <201203151138.51508.sr@denx.de>
Message-ID: <4F61C71B.2000106@st.com>

On 3/15/2012 4:08 PM, Stefan Roese wrote:
> I still don't think its worth it. But please feel free to send an add-on 
> patch, to "clean this up".

Ok. I will do it.

-- 
viresh


From broonie at opensource.wolfsonmicro.com  Thu Mar 15 06:44:44 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 15 Mar 2012 10:44:44 +0000
Subject: [PATCH v3 1/6] regmap: add support for 7_25 format
In-Reply-To: <1331757790-10583-2-git-send-email-marc@cpdesign.com.au>
References: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
 <1331757790-10583-2-git-send-email-marc@cpdesign.com.au>
Message-ID: <20120315104443.GC3138@opensource.wolfsonmicro.com>

On Thu, Mar 15, 2012 at 07:43:05AM +1100, Marc Reilly wrote:
> This adds support for devices with 7 address bits and 25 data bits.
> The initial intended user for this are the mc13xxx mfds in spi mode.
> (The 25th data bit is actually a dummy bit)
> 
> Signed-off-by: Marc Reilly <marc at cpdesign.com.au>

It looks like this should be using the pad_bits parameter, though
currently we only actually support pad bytes and integer sized register
values.  Ugh.  We also have some entertainment because this device
contains a touchscreen so I imagine you want readback but devices using
odd register sizes don't do readback right now.

What I think we want to do here is use pad_bits then internally to the
API notice that reg_bits + pad_bits is a byte and therefore set up for 8
bit registers and set a new value reg_shift in the map which shifts the
register address left, either teaching the register format functions
about it or just making a new one.  This should work better from a
framework point of view.
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From broonie at opensource.wolfsonmicro.com  Thu Mar 15 06:46:18 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 15 Mar 2012 10:46:18 +0000
Subject: [PATCH v3 2/6] regmap: Add support for device with 24 data bits.
In-Reply-To: <1331757790-10583-3-git-send-email-marc@cpdesign.com.au>
References: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
 <1331757790-10583-3-git-send-email-marc@cpdesign.com.au>
Message-ID: <20120315104617.GD3138@opensource.wolfsonmicro.com>

On Thu, Mar 15, 2012 at 07:43:06AM +1100, Marc Reilly wrote:
> Add support for devices with 24 data bits.

Not sure what you generated this patch against but it doesn't apply to
my topic/core or against -next.  Please regenerate it against
topic/core, it looks good.
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From sr at denx.de  Thu Mar 15 06:50:32 2012
From: sr at denx.de (Stefan Roese)
Date: Thu, 15 Mar 2012 11:50:32 +0100
Subject: [PATCH v3] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
Message-ID: <1331808632-22585-1-git-send-email-sr@denx.de>

This patch adds a generic target for SPEAr600 board that can be
configured via the device-tree. Currently the following devices
are supported via the devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
follow in later patches.

Only the spear600-evb is currently supported. Other SPEAr600
based boards will follow later.

Since the current mainline SPEAr600 code only supports the SPEAr600
evaluation board, with nearly zero peripheral devices (only UART
and GPIO), it makes sense to switch over to DT based configuration
completely now. So this patch also removes all non-DT stuff, mainly
platform device data. The files spear600.c and spear600_evb.c are
removed completely.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Viresh Kumar <viresh.kumar at st.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
Arnd, I didn't add your reviewed-by, since this patch version
has changed quite a bit. Please review again. Thanks.

v3:
- Removed non-DT SPEAr600 board support completely
- Removed OF_DEV_AUXDATA and changed clkdev instead, since we
  don't support non-DT targets any more
- Changed gmac0 -> gmac etc for single instance devices in the
  dts
- Added max memory size to memory node (instead of 0)
- Dropped mac-address property
- Removed some headers from spear6xx.c

v2:
- Added DT support to spear6xx.c instead of creating board-dt.c
- Removed UART (PL011) and GPIO (PL061) platform data for
  devicetree board port. This works now via DT probing
- Added OF_DEV_AUXDATA for clock device name matching for some
  device drivers
- Removed sper600.c file completely
- Added DW I2C and ethernet nodes to the dts files
- Added other DT nodes (SMI, FSMC, ECHI, OHCI), currently disabled
  since the corresponding device drivers don't support DT probing
- Removed Linaro/FSL copyright notice from SPEAr DT files (copy-paste cruft)
- Many smaller modification to the dts/dtsi files
- Changed Documentation/devicetree/bindings/arm/spear.txt to match
  the changed bindings

 Documentation/devicetree/bindings/arm/spear.txt |    8 ++
 arch/arm/boot/dts/spear600-evb.dts              |   30 +++++
 arch/arm/boot/dts/spear600.dtsi                 |  161 +++++++++++++++++++++++
 arch/arm/mach-spear6xx/Kconfig                  |    7 +-
 arch/arm/mach-spear6xx/Makefile                 |    6 -
 arch/arm/mach-spear6xx/clock.c                  |   14 +-
 arch/arm/mach-spear6xx/spear600.c               |   25 ----
 arch/arm/mach-spear6xx/spear600_evb.c           |   54 --------
 arch/arm/mach-spear6xx/spear6xx.c               |  132 +++++--------------
 9 files changed, 246 insertions(+), 191 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
 create mode 100644 arch/arm/boot/dts/spear600-evb.dts
 create mode 100644 arch/arm/boot/dts/spear600.dtsi
 delete mode 100644 arch/arm/mach-spear6xx/spear600.c
 delete mode 100644 arch/arm/mach-spear6xx/spear600_evb.c

diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
new file mode 100644
index 0000000..f8e54f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -0,0 +1,8 @@
+ST SPEAr Platforms Device Tree Bindings
+---------------------------------------
+
+Boards with the ST SPEAr600 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear600";
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
new file mode 100644
index 0000000..cc594ed
--- /dev/null
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear600.dtsi"
+
+/ {
+	model = "ST SPEAr600 Evaluation Board";
+	compatible = "st,spear600-evb", "st,spear600";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	ahb {
+		gmac: ethernet at e0800000 {
+			phy-mode = "gmii";
+		};
+
+		i2c at d0200000 {
+			clock-frequency = <400000>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
new file mode 100644
index 0000000..187e0eb
--- /dev/null
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "st,spear600";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>; /* Real value updated by U-Boot */
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vic0: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		vic1: interrupt-controller at f1000000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		serial at d0000000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xd0000000 0x1000>;
+			interrupt-parent = <&vic0>;
+			interrupts = <24>;
+		};
+
+		serial at d0080000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xd0080000 0x1000>;
+			interrupt-parent = <&vic0>;
+			interrupts = <25>;
+		};
+
+		/* local/cpu GPIO */
+		gpio0: gpio at f0100000 {
+			#gpio-cells = <2>;
+			compatible = "arm,pl061", "arm,primecell";
+			gpio-controller;
+			reg = <0xf0100000 0x1000>;
+			interrupt-parent = <&vic0>;
+			interrupts = <18>;
+		};
+
+		/* basic GPIO */
+		gpio1: gpio at fc980000 {
+			#gpio-cells = <2>;
+			compatible = "arm,pl061", "arm,primecell";
+			gpio-controller;
+			reg = <0xfc980000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <19>;
+		};
+
+		/* appl GPIO */
+		gpio2: gpio at d8100000 {
+			#gpio-cells = <2>;
+			compatible = "arm,pl061", "arm,primecell";
+			gpio-controller;
+			reg = <0xd8100000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <4>;
+		};
+
+		gmac: ethernet at e0800000 {
+			compatible = "st,spear600-gmac";
+			reg = <0xe0800000 0x8000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <24 23>;
+			interrupt-names = "macirq", "eth_wake_irq";
+		};
+
+		i2c at d0200000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0xd0200000 0x1000>;
+			interrupt-parent = <&vic0>;
+			interrupts = <28>;
+		};
+
+		fsmc: flash at d1800000 {
+			status = "disabled";
+			compatible = "st,fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd1800000 0x1000	/* FSMC Register */
+			       0xd2000000 0x4000>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+		};
+
+		smi: flash at fc000000 {
+			status = "disabled";
+			compatible = "st,spear-smi";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xfc000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <12>;
+		};
+
+		ehci at e1800000 {
+			status = "disabled";
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe1800000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <27>;
+		};
+
+		ehci at e2000000 {
+			status = "disabled";
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe2000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <29>;
+		};
+
+		ohci at e1900000 {
+			status = "disabled";
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe1900000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <26>;
+		};
+
+		ohci at e2100000 {
+			status = "disabled";
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe2100000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <28>;
+		};
+	};
+};
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
index ff4ae5b..fbe298b 100644
--- a/arch/arm/mach-spear6xx/Kconfig
+++ b/arch/arm/mach-spear6xx/Kconfig
@@ -5,11 +5,12 @@
 if ARCH_SPEAR6XX
 
 menu "SPEAr6xx Implementations"
-config BOARD_SPEAR600_EVB
-	bool "SPEAr600 Evaluation Board"
+config BOARD_SPEAR600_DT
+	bool "SPEAr600 generic board configured via device-tree"
 	select MACH_SPEAR600
+	select USE_OF
 	help
-	  Supports ST SPEAr600 Evaluation Board
+	  Supports ST SPEAr600 boards configured via the device-tree
 
 endmenu
 
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index cc1a4d8..76e5750 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -4,9 +4,3 @@
 
 # common files
 obj-y	+= clock.o spear6xx.o
-
-# spear600 specific files
-obj-$(CONFIG_MACH_SPEAR600) += spear600.o
-
-# spear600 boards files
-obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index ac70e0d..358f280 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -641,8 +641,8 @@ static struct clk_lookup spear_clk_lookups[] = {
 	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
 	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
 	{ .con_id = "gpt3_synth_clk",	.clk = &gpt3_synth_clk},
-	{ .dev_id = "uart0",		.clk = &uart0_clk},
-	{ .dev_id = "uart1",		.clk = &uart1_clk},
+	{ .dev_id = "d0000000.serial",	.clk = &uart0_clk},
+	{ .dev_id = "d0080000.serial",	.clk = &uart1_clk},
 	{ .dev_id = "firda",		.clk = &firda_clk},
 	{ .dev_id = "clcd",		.clk = &clcd_clk},
 	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
@@ -655,20 +655,20 @@ static struct clk_lookup spear_clk_lookups[] = {
 	{ .con_id = "usbh.1_clk",	.clk = &usbh1_clk},
 	/* clock derived from ahb clk */
 	{ .con_id = "apb_clk",		.clk = &apb_clk},
-	{ .dev_id = "i2c_designware.0",	.clk = &i2c_clk},
+	{ .dev_id = "d0200000.i2c",	.clk = &i2c_clk},
 	{ .dev_id = "dma",		.clk = &dma_clk},
 	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
 	{ .dev_id = "gmac",		.clk = &gmac_clk},
 	{ .dev_id = "smi",		.clk = &smi_clk},
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
+	{ .dev_id = "fsmc-nand",	.clk = &fsmc_clk},
 	/* clock derived from apb clk */
 	{ .dev_id = "adc",		.clk = &adc_clk},
 	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
 	{ .dev_id = "ssp-pl022.1",	.clk = &ssp1_clk},
 	{ .dev_id = "ssp-pl022.2",	.clk = &ssp2_clk},
-	{ .dev_id = "gpio0",		.clk = &gpio0_clk},
-	{ .dev_id = "gpio1",		.clk = &gpio1_clk},
-	{ .dev_id = "gpio2",		.clk = &gpio2_clk},
+	{ .dev_id = "f0100000.gpio",	.clk = &gpio0_clk},
+	{ .dev_id = "fc980000.gpio",	.clk = &gpio1_clk},
+	{ .dev_id = "d8100000.gpio",	.clk = &gpio2_clk},
 };
 
 void __init spear6xx_clk_init(void)
diff --git a/arch/arm/mach-spear6xx/spear600.c b/arch/arm/mach-spear6xx/spear600.c
deleted file mode 100644
index d0e6eea..0000000
--- a/arch/arm/mach-spear6xx/spear600.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/spear600.c
- *
- * SPEAr600 machine source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/ptrace.h>
-#include <asm/irq.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* Add spear600 specific devices here */
-
-void __init spear600_init(void)
-{
-	/* call spear6xx family common init function */
-	spear6xx_init();
-}
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
deleted file mode 100644
index c6e4254..0000000
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/spear600_evb.c
- *
- * SPEAr600 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-static struct amba_device *amba_devs[] __initdata = {
-	&gpio_device[0],
-	&gpio_device[1],
-	&gpio_device[2],
-	&uart_device[0],
-	&uart_device[1],
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-};
-
-static void __init spear600_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear600 machine init function */
-	spear600_init();
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear6xx_map_io,
-	.init_irq	=	spear6xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear6xx_timer,
-	.init_machine	=	spear600_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index e0f6628..2ed8b14 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -6,111 +6,21 @@
  * Copyright (C) 2009 ST Microelectronics
  * Rajeev Kumar<rajeev-dlh.kumar at st.com>
  *
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
-#include <mach/irqs.h>
-
-/* Add spear6xx machines common devices here */
-/* uart device registration */
-struct amba_device uart_device[] = {
-	{
-		.dev = {
-			.init_name = "uart0",
-		},
-		.res = {
-			.start = SPEAR6XX_ICM1_UART0_BASE,
-			.end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_UART_0, NO_IRQ},
-	}, {
-		.dev = {
-			.init_name = "uart1",
-		},
-		.res = {
-			.start = SPEAR6XX_ICM1_UART1_BASE,
-			.end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_UART_1, NO_IRQ},
-	}
-};
-
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data[] = {
-	{
-		.gpio_base	= 0,
-		.irq_base	= SPEAR_GPIO0_INT_BASE,
-	}, {
-		.gpio_base	= 8,
-		.irq_base	= SPEAR_GPIO1_INT_BASE,
-	}, {
-		.gpio_base	= 16,
-		.irq_base	= SPEAR_GPIO2_INT_BASE,
-	},
-};
-
-struct amba_device gpio_device[] = {
-	{
-		.dev = {
-			.init_name = "gpio0",
-			.platform_data = &gpio_plat_data[0],
-		},
-		.res = {
-			.start = SPEAR6XX_CPU_GPIO_BASE,
-			.end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_LOCAL_GPIO, NO_IRQ},
-	}, {
-		.dev = {
-			.init_name = "gpio1",
-			.platform_data = &gpio_plat_data[1],
-		},
-		.res = {
-			.start = SPEAR6XX_ICM3_GPIO_BASE,
-			.end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_BASIC_GPIO, NO_IRQ},
-	}, {
-		.dev = {
-			.init_name = "gpio2",
-			.platform_data = &gpio_plat_data[2],
-		},
-		.res = {
-			.start = SPEAR6XX_ICM2_GPIO_BASE,
-			.end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_APPL_GPIO, NO_IRQ},
-	}
-};
-
-/* This will add devices, and do machine specific tasks */
-void __init spear6xx_init(void)
-{
-	/* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear6xx_init_irq(void)
-{
-	vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_PRI_BASE, 0, ~0, 0);
-	vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0, 0);
-}
 
 /* Following will create static virtual/physical mappings */
 static struct map_desc spear6xx_io_desc[] __initdata = {
@@ -181,3 +91,33 @@ static void __init spear6xx_timer_init(void)
 struct sys_timer spear6xx_timer = {
 	.init = spear6xx_timer_init,
 };
+
+static void __init spear600_dt_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *spear600_dt_board_compat[] = {
+	"st,spear600",
+	NULL
+};
+
+static const struct of_device_id vic_of_match[] __initconst = {
+	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ /* Sentinel */ }
+};
+
+static void __init spear6xx_dt_init_irq(void)
+{
+	of_irq_init(vic_of_match);
+}
+
+DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
+	.map_io		=	spear6xx_map_io,
+	.init_irq	=	spear6xx_dt_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear6xx_timer,
+	.init_machine	=	spear600_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear600_dt_board_compat,
+MACHINE_END
-- 
1.7.9.2



From aisheng.dong at freescale.com  Thu Mar 15 06:59:28 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Thu, 15 Mar 2012 18:59:28 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20321.37353.63115.664975@ipc1.ka-ro>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
Message-ID: <20120315105927.GE13022@shlinux2.ap.freescale.net>

On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa?mann wrote:
> Hi,
> 
> Dong Aisheng writes:
> > On Wed, Mar 14, 2012 at 10:16:43PM +0800, s.hauer at pengutronix.de wrote:
> > > On Wed, Mar 14, 2012 at 08:45:23PM +0800, Dong Aisheng wrote:
> > > > On Wed, Mar 14, 2012 at 01:23:51AM +0800, Grant Likely wrote:
> [...]
> > > > But it seems this needs pass mac address to fec driver via platforom data which is
> > > > not friendly to dt.
> > > > 
> > > > Another way may be changing fec driver to get the fixed part of mac address(first
> > > > two bytes) from device tree and read the left dynamical part from otp which i'm not
> > > > sure is better enough.
> > > > 
> > > > BTW, filling with zeros seems not work since it's invalid mac address.
> > > 
> > > Yes, that's the idea of using this value...
> > > 
> > But comparing to use an invalid value, why not just do not define that
> > local-mac-address property?
> > 
> Because a MAC address is by definition a GLOBALLY UNIQUE IDENTIFIER
> which is contrary to coding a "valid" default value for it somewhere!
> The owner of a certain MAC address range (OUI) is responsible for
> ensuring the uniqueness. Thus only they may assign a specific MAC
> address to a specific device.
> 
Yes, you're correct.
So i propose to read the MAC address from MX28 OTP in fec driver instead of
define it in device tree in my last mail.
http://www.spinics.net/lists/arm-kernel/msg165040.html
Do you have any comment on that way?

Regards
Dong Aisheng



From viresh.kumar at st.com  Thu Mar 15 07:03:29 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 15 Mar 2012 16:33:29 +0530
Subject: [PATCH v3] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <1331808632-22585-1-git-send-email-sr@denx.de>
References: <1331808632-22585-1-git-send-email-sr@denx.de>
Message-ID: <4F61CC81.1020902@st.com>

On 3/15/2012 4:20 PM, Stefan Roese wrote:

> diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi

> +/ {
> +       compatible = "st,spear600";
> +
> +       cpus {
> +               cpu at 0 {
> +                       compatible = "arm,arm926ejs";
> +               };
> +       };
> +
> +       memory {
> +               device_type = "memory";
> +               reg = <0 0x40000000>; /* Real value updated by U-Boot */
> +       };
> +
> +       ahb {

What is the significance of this name? As i see gpio/spi etc in this list,
which are on apb bus.

> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "simple-bus";
> +               ranges;
> +

> +               /* local/cpu GPIO */
> +               gpio0: gpio at f0100000 {
> +                       #gpio-cells = <2>;
> +                       compatible = "arm,pl061", "arm,primecell";
> +                       gpio-controller;
> +                       reg = <0xf0100000 0x1000>;
> +                       interrupt-parent = <&vic0>;
> +                       interrupts = <18>;
> +               };
> +
> +               /* basic GPIO */
> +               gpio1: gpio at fc980000 {
> +                       #gpio-cells = <2>;
> +                       compatible = "arm,pl061", "arm,primecell";
> +                       gpio-controller;
> +                       reg = <0xfc980000 0x1000>;
> +                       interrupt-parent = <&vic1>;
> +                       interrupts = <19>;
> +               };
> +
> +               /* appl GPIO */
> +               gpio2: gpio at d8100000 {
> +                       #gpio-cells = <2>;
> +                       compatible = "arm,pl061", "arm,primecell";
> +                       gpio-controller;
> +                       reg = <0xd8100000 0x1000>;
> +                       interrupt-parent = <&vic1>;
> +                       interrupts = <4>;
> +               };
> +

> +};

> diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
> index ac70e0d..358f280 100644
> --- a/arch/arm/mach-spear6xx/clock.c
> +++ b/arch/arm/mach-spear6xx/clock.c
> @@ -641,8 +641,8 @@ static struct clk_lookup spear_clk_lookups[] = {
>         { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
>         { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
>         { .con_id = "gpt3_synth_clk",   .clk = &gpt3_synth_clk},
> -       { .dev_id = "uart0",            .clk = &uart0_clk},
> -       { .dev_id = "uart1",            .clk = &uart1_clk},
> +       { .dev_id = "d0000000.serial",  .clk = &uart0_clk},
> +       { .dev_id = "d0080000.serial",  .clk = &uart1_clk},

I didn't got Jean's comment at that time, but now it is ultra clear.

Acked-by: Viresh Kumar <viresh.kumar at st.com>

-- 
viresh


From jean.pihet at newoldbits.com  Thu Mar 15 07:06:44 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Thu, 15 Mar 2012 12:06:44 +0100
Subject: [PATCH 4/6] ARM: OMAP: fix missing __devexit_p() annotations
In-Reply-To: <E1S87wp-0000Mz-V8@rmk-PC.arm.linux.org.uk>
References: <20120315102845.GB16389@n2100.arm.linux.org.uk>
 <E1S87wp-0000Mz-V8@rmk-PC.arm.linux.org.uk>
Message-ID: <CAORVsuUVC4hpotK=eybA=Eqtfg0+PivjwRUENjCwcLG2dp1Ucg@mail.gmail.com>

Russell,

On Thu, Mar 15, 2012 at 11:30 AM, Russell King
<rmk+kernel at arm.linux.org.uk> wrote:
> Missing __devexit_p() annotations in driver structures for remove functions
> marked with __devexit is waiting for build errors to happen, such as:
>
> `omap_system_dma_remove' referenced in section `.data' of arch/arm/plat-omap/bui
> lt-in.o: defined in discarded section `.devexit.text' of arch/arm/plat-omap/buil
> t-in.o
>
> Add the necessary annotation, and as a result of audit, fix others which
> are also missing in arch/arm/*omap*.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> Acked-by: Tony Lindgren <tony at atomide.com>
> ---
> ?arch/arm/mach-omap2/smartreflex.c | ? ?2 +-
> ?arch/arm/plat-omap/dma.c ? ? ? ? ?| ? ?2 +-
> ?2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
> index 7e755bb..47c77a1 100644
> --- a/arch/arm/mach-omap2/smartreflex.c
> +++ b/arch/arm/mach-omap2/smartreflex.c
> @@ -1012,7 +1012,7 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
> ?}
>
> ?static struct platform_driver smartreflex_driver = {
> - ? ? ? .remove ? ? ? ? = omap_sr_remove,
> + ? ? ? .remove ? ? ? ? = __devexit_p(omap_sr_remove),
> ? ? ? ?.driver ? ? ? ? = {
> ? ? ? ? ? ? ? ?.name ? = "smartreflex",
> ? ? ? ?},
Tony already has this change in his master branch, commit
149f1d5c8d2fd6879cdf93ca70f1cb745e698a1e ('ARM: OMAP2+: Fix devexit
for smartreflex when CONFIG_HOTPLUG is not set').

Jean


From joerg.roedel at amd.com  Thu Mar 15 07:12:27 2012
From: joerg.roedel at amd.com (Joerg Roedel)
Date: Thu, 15 Mar 2012 12:12:27 +0100
Subject: [PATCH v12 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
In-Reply-To: <000201cd0286$2e6fbb40$8b4f31c0$%cho@samsung.com>
References: <000201cd0286$2e6fbb40$8b4f31c0$%cho@samsung.com>
Message-ID: <20120315111227.GA2384@amd.com>

On Thu, Mar 15, 2012 at 05:32:39PM +0900, Cho KyongHo wrote:
> Handling System MMUs with an identifier is not flexible to manage
> System MMU platform devices because of the following reasons:
> 1. A device driver which needs to handle System MMU must know the ID.
> 2. A System MMU may not present in some implementations of Exynos family.
> 3. Handling System MMU with IOMMU API does not require an ID.
> 
> This patch is the result of removing ID of System MMUs.
> Instead, a device driver that needs to handle its System MMU must
> use IOMMU API while its descriptor of platform device is given.
> 
> This patch also includes the following enhancements:
> - A System MMU device becomes a child if its power domain device.
> - clkdev
> 
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
> ---
>  arch/arm/mach-exynos/Kconfig                    |   10 +-
>  arch/arm/mach-exynos/Makefile                   |    2 +-
>  arch/arm/mach-exynos/clock-exynos4.c            |   79 ++--
>  arch/arm/mach-exynos/clock-exynos4.h            |    2 +
>  arch/arm/mach-exynos/clock-exynos4210.c         |   11 +
>  arch/arm/mach-exynos/clock-exynos4212.c         |   28 ++-
>  arch/arm/mach-exynos/clock-exynos5.c            |   90 +++++
>  arch/arm/mach-exynos/dev-sysmmu.c               |  457 ++++++++++++----------
>  arch/arm/mach-exynos/include/mach/irqs.h        |   25 +-
>  arch/arm/mach-exynos/include/mach/map.h         |   38 ++
>  arch/arm/mach-exynos/include/mach/regs-clock.h  |    5 +
>  arch/arm/mach-exynos/include/mach/regs-sysmmu.h |   28 --
>  arch/arm/mach-exynos/include/mach/sysmmu.h      |   88 +++--
>  arch/arm/mach-exynos/mach-armlex4210.c          |    1 -
>  arch/arm/mach-exynos/mach-smdkv310.c            |    1 -
>  15 files changed, 529 insertions(+), 336 deletions(-)
>  delete mode 100644 arch/arm/mach-exynos/include/mach/regs-sysmmu.h

This patch doesn't apply cleanly against upstream Linux (v3.3-rcX).
Please rebase to upstream and resend. The other 2 patches apply fine.


	Joerg

-- 
AMD Operating System Research Center

Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach
General Managers: Alberto Bozzo
Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632



From hvaibhav at ti.com  Thu Mar 15 07:06:24 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Thu, 15 Mar 2012 16:36:24 +0530
Subject: [PATCH-V3 1/3] ARM: OMAP3/4: omap_hwmod: Add rstst_off field to
 struct omap_hwmod_omap4_prcm
In-Reply-To: <1331809586-24652-1-git-send-email-hvaibhav@ti.com>
References: <1331809586-24652-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1331809586-24652-2-git-send-email-hvaibhav@ti.com>

In case of AM33XX device, XXX_RSTST register offset is not
consistent across PRM modules/instances,

PRM_XXX            RSTST
=========================
PRM_PER_MOD:       0x04
PRM_WKUP_MOD:      0x0C
PRM_MPU_MOD:       NA
PRM_DEVICE_MOD:    0x08

This means, we need to pass on XXX_RSTST register offset
information through omap_hwmod data, similar to XXX_RSTCTRL.

Currently, this field is only applicable and used for AM33XX devices.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index ce75c30..1cfa008 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -377,11 +377,13 @@ struct omap_hwmod_omap2_prcm {
  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
  * @clkctrl_reg: PRCM address of the clock control register
  * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
+ * @rstst_reg: (AM33XX Only) address of the XXX_RSTST register located in the PRM
  * @submodule_wkdep_bit: bit shift of the WKDEP range
  */
 struct omap_hwmod_omap4_prcm {
 	u16		clkctrl_offs;
 	u16		rstctrl_offs;
+	u16		rstst_offs;
 	u16		context_offs;
 	u8		submodule_wkdep_bit;
 	u8		modulemode;
--
1.7.0.4



From hvaibhav at ti.com  Thu Mar 15 07:06:25 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Thu, 15 Mar 2012 16:36:25 +0530
Subject: [PATCH-V3 2/3] ARM: OMAP2+: powerdomain: Add offset & mask fields to
 struct powerdomain
In-Reply-To: <1331809586-24652-1-git-send-email-hvaibhav@ti.com>
References: <1331809586-24652-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1331809586-24652-3-git-send-email-hvaibhav@ti.com>

In case of AM33xx device, there is no consistency between
PWRSTCTRL & PWRSTST register offsets in PRM space, for example -

PRM_XXX           PWRSTCTRL     PWRSTST
=======================================
PRM_PER_MOD:      0x0C,         0x08
PRM_WKUP_MOD:     0x04,         0x08
PRM_MPU_MOD:      0x00,         0x04
PRM_DEVICE_MOD:   NA,           NA

And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -

PRM_XXX           LOGICRET  MEMON  MEMRET
=========================================
GFX_PWRCTRL:      2,        17,    6
PER_PWRCTRL:      3,        25,    29
MPU_PWRCTRL:      2,        18,    22
WKUP_PWRCTRL:     3,        NA,    NA

This means, we need to maintain and pass on all this information
through powerdomain handle; so adding fields for,
   - PWRSTCTRL/ST register offset
   - Logic retention state mask
   - mem_on/ret/pwrst/retst mask

Currently, this fields is only applicable and used for AM33XX devices.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/powerdomain.h |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 0d72a8a..8fc50b2 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -92,6 +92,15 @@ struct powerdomain;
  * @pwrdm_clkdms: Clockdomains in this powerdomain
  * @node: list_head linking all powerdomains
  * @voltdm_node: list_head linking all powerdomains in a voltagedomain
+ * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
+ * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
+ * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
+ *	in @pwrstctrl_offs
+ * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
+ * @mem_ret_mask: (AM33XX only) mask for mem retention bitfield in @pwrstctrl_offs
+ * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
+ * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
+ *	in @pwrstctrl_offs
  * @state:
  * @state_counter:
  * @timer:
@@ -121,6 +130,14 @@ struct powerdomain {
 	unsigned ret_logic_off_counter;
 	unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];

+	const u8 pwrstctrl_offs;
+	const u8 pwrstst_offs;
+	const u32 logicretstate_mask;
+	const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
+	const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
+	const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
+	const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
+
 #ifdef CONFIG_PM_DEBUG
 	s64 timer;
 	s64 state_timer[PWRDM_MAX_PWRSTS];
--
1.7.0.4



From hvaibhav at ti.com  Thu Mar 15 07:06:23 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Thu, 15 Mar 2012 16:36:23 +0530
Subject: [PATCH-V3 0/3] ARM: OMAP2+: Add powerdomain & PRM support for AM33XX
 device
Message-ID: <1331809586-24652-1-git-send-email-hvaibhav@ti.com>

After going round-n-round on how to add support for AM33XX family
of device into kernel, especially for PRM and CM support, we have
decided to handle it separately; as AM33XX-PRCM module is different
than OMAP3 and OMAP4 architecture.

The difference becomes very interesting/weird when it comes to
the consistency for register offsets in PRM address space and
bit-field offsets inside PRM registers,
So along with Powerdomain data and PRM api's required for AM33XX
device, this patch series adds,

 - XXX_RSTST register offset to "struct omap_hwmod_omap4_prcm"
 - PWRSTCTRL & PWRSTST register offsets to "struct powerdomain"
 - Logicretstate and mem_on/ret/pwrst/retst mask to "struct powerdomain"


Testing: This patch series has been boot tested on AM37xEVM and AM335x
         based BeagleBone community board.

THANKS TO PAUL HERE...for helping and concluding on this, soon I will
have similar patch for CM support, then clock-tree and hwmod will follow...

Changes from V1 & V2:
	- Rolled back to my original approach, where AM33xx device was
	  handled separately (RFC version).
	- As per Paul's comments, added Register offsets & bit-fields
	  masks.

Vaibhav Hiremath (3):
  ARM: OMAP3/4: omap_hwmod: Add rstst_off field to struct
    omap_hwmod_omap4_prcm
  ARM: OMAP2+: powerdomain: Add offset & mask fields to struct
    powerdomain
  ARM: OMAP3+: am33xx: Add power domain data

 arch/arm/mach-omap2/Makefile                 |    4 +
 arch/arm/mach-omap2/io.c                     |    1 +
 arch/arm/mach-omap2/omap_hwmod.c             |   32 ++-
 arch/arm/mach-omap2/powerdomain.h            |   23 ++-
 arch/arm/mach-omap2/powerdomain33xx.c        |  230 +++++++++++++++++
 arch/arm/mach-omap2/powerdomains33xx_data.c  |  185 +++++++++++++
 arch/arm/mach-omap2/prm-regbits-33xx.h       |  357 ++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm33xx.c                |  134 ++++++++++
 arch/arm/mach-omap2/prm33xx.h                |  129 +++++++++
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    2 +
 10 files changed, 1092 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-omap2/powerdomain33xx.c
 create mode 100644 arch/arm/mach-omap2/powerdomains33xx_data.c
 create mode 100644 arch/arm/mach-omap2/prm-regbits-33xx.h
 create mode 100644 arch/arm/mach-omap2/prm33xx.c
 create mode 100644 arch/arm/mach-omap2/prm33xx.h



From hvaibhav at ti.com  Thu Mar 15 07:06:26 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Thu, 15 Mar 2012 16:36:26 +0530
Subject: [PATCH-V3 3/3] ARM: OMAP3+: am33xx: Add powerdomain & PRM support
In-Reply-To: <1331809586-24652-1-git-send-email-hvaibhav@ti.com>
References: <1331809586-24652-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1331809586-24652-4-git-send-email-hvaibhav@ti.com>

As far as PRM/CM/PRCM modules are concerned, AM33XX device is
different than OMAP3 and OMAP4 architectures; so we need to
handle it separately.
This patch adds support for, Powerdomain, Powerdomain data,
PRM api's required for AM33XX device.

And also, hooks up AM33XX powerdomain to existing OMAP framework.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Signed-off-by: Afzal Mohammed <afzal at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/Makefile                |    4 +
 arch/arm/mach-omap2/io.c                    |    1 +
 arch/arm/mach-omap2/omap_hwmod.c            |   32 +++-
 arch/arm/mach-omap2/powerdomain.h           |    6 +-
 arch/arm/mach-omap2/powerdomain33xx.c       |  230 +++++++++++++++++
 arch/arm/mach-omap2/powerdomains33xx_data.c |  185 ++++++++++++++
 arch/arm/mach-omap2/prm-regbits-33xx.h      |  357 +++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm33xx.c               |  134 ++++++++++
 arch/arm/mach-omap2/prm33xx.h               |  129 ++++++++++
 9 files changed, 1073 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-omap2/powerdomain33xx.c
 create mode 100644 arch/arm/mach-omap2/powerdomains33xx_data.c
 create mode 100644 arch/arm/mach-omap2/prm-regbits-33xx.h
 create mode 100644 arch/arm/mach-omap2/prm33xx.c
 create mode 100644 arch/arm/mach-omap2/prm33xx.h

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b4ac21e..fd130e5 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -114,6 +114,10 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(powerdomain-common) \
 					   powerdomain2xxx_3xxx.o \
 					   powerdomains3xxx_data.o \
 					   powerdomains2xxx_3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX)		+= $(powerdomain-common) \
+					   prm33xx.o \
+					   powerdomain33xx.o \
+					   powerdomains33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common) \
 					   powerdomain44xx.o \
 					   powerdomains44xx_data.o
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 11d53df..b594918 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -473,6 +473,7 @@ void __init am33xx_init_early(void)
 	omap2_set_globals_am33xx();
 	omap_common_init_early();
 	am33xx_voltagedomains_init();
+	am33xx_powerdomains_init();
 	omap3xxx_clk_init();
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 26928c6..d698010 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -151,6 +151,7 @@
 #include "cminst44xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
+#include "prm33xx.h"
 #include "prminst44xx.h"
 #include "mux.h"

@@ -1418,7 +1419,15 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
 	if (IS_ERR_VALUE(ret))
 		return ret;

-	if (cpu_is_omap24xx() || cpu_is_omap34xx())
+	/*
+	 * cpu_is_omap34xx() is true for am33xx device as well, so
+	 * fist check for cpu_is_am33xx().
+	 */
+	if (cpu_is_am33xx())
+		return am33xx_prm_assert_hardreset(ohri.rst_shift,
+				oh->clkdm->pwrdm.ptr->prcm_offs,
+				oh->prcm.omap4.rstctrl_offs);
+	else if (cpu_is_omap24xx() || cpu_is_omap34xx())
 		return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
 						  ohri.rst_shift);
 	else if (cpu_is_omap44xx())
@@ -1452,7 +1461,16 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 	if (IS_ERR_VALUE(ret))
 		return ret;

-	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+	/*
+	 * cpu_is_omap34xx() is true for am33xx device as well, so
+	 * fist check for cpu_is_am33xx().
+	 */
+	if (cpu_is_am33xx()) {
+		return am33xx_prm_deassert_hardreset(ohri.rst_shift,
+				oh->clkdm->pwrdm.ptr->prcm_offs,
+				oh->prcm.omap4.rstctrl_offs,
+				oh->prcm.omap4.rstst_offs);
+	} else if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
 		ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
 						   ohri.rst_shift,
 						   ohri.st_shift);
@@ -1494,7 +1512,15 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 	if (IS_ERR_VALUE(ret))
 		return ret;

-	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+	/*
+	 * cpu_is_omap34xx() is true for am33xx device as well, so
+	 * fist check for cpu_is_am33xx().
+	 */
+	if (cpu_is_am33xx()) {
+		return am33xx_prm_is_hardreset_asserted(ohri.rst_shift,
+				oh->clkdm->pwrdm.ptr->prcm_offs,
+				oh->prcm.omap4.rstctrl_offs);
+	} else if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
 		return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
 						       ohri.st_shift);
 	} else if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 8fc50b2..53e42a9 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -67,9 +67,9 @@

 /*
  * Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain on OMAP4 is the worst case
+ * PER powerdomain on AM33XX is the worst case
  */
-#define PWRDM_MAX_CLKDMS	9
+#define PWRDM_MAX_CLKDMS	11

 /* XXX A completely arbitrary number. What is reasonable here? */
 #define PWRDM_TRANSITION_BAILOUT 100000
@@ -240,10 +240,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
 extern void omap242x_powerdomains_init(void);
 extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
+extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);

 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
+extern struct pwrdm_ops am33xx_pwrdm_operations;
 extern struct pwrdm_ops omap4_pwrdm_operations;

 /* Common Internal functions used across OMAP rev's */
diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c
new file mode 100644
index 0000000..c53f8d8
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain33xx.c
@@ -0,0 +1,230 @@
+/*
+ * AM33XX Powerdomain control
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
+ * <rnayak at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include <plat/prcm.h>
+
+#include "powerdomain.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+
+static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+	am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
+			(pwrst << OMAP_POWERSTATE_SHIFT),
+			pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+	return 0;
+}
+
+static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs,  pwrdm->pwrstctrl_offs);
+	v &= OMAP_POWERSTATE_MASK;
+	v >>= OMAP_POWERSTATE_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+	v &= OMAP_POWERSTATEST_MASK;
+	v >>= OMAP_POWERSTATEST_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+	v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
+	v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+	am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
+			(1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
+			pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+	return 0;
+}
+
+static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+	am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
+			AM33XX_LASTPOWERSTATEENTERED_MASK,
+			pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+	return 0;
+}
+
+static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+	u32 m;
+
+	m = pwrdm->logicretstate_mask;
+	if (!m)
+		return -EINVAL;
+
+	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+			pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+	return 0;
+}
+
+static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+	v &= AM33XX_LOGICSTATEST_MASK;
+	v >>= AM33XX_LOGICSTATEST_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+	u32 v, m;
+
+	m = pwrdm->logicretstate_mask;
+	if (!m)
+		return -EINVAL;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+	v &= m;
+	v >>= __ffs(m);
+
+	return v;
+}
+
+static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+		u8 pwrst)
+{
+	u32 m;
+
+	m = pwrdm->mem_on_mask[bank];
+	if (!m)
+		return -EINVAL;
+
+	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+			pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+	return 0;
+}
+
+static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+					u8 pwrst)
+{
+	u32 m;
+
+	m = pwrdm->mem_ret_mask[bank];
+	if (!m)
+		return -EINVAL;
+
+	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+			pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+	return 0;
+}
+
+static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+	u32 m, v;
+
+	m = pwrdm->mem_pwrst_mask[bank];
+	if (!m)
+		return -EINVAL;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+	v &= m;
+	v >>= __ffs(m);
+
+	return v;
+}
+
+static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+	u32 m, v;
+
+	m = pwrdm->mem_retst_mask[bank];
+	if (!m)
+		return -EINVAL;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+	v &= m;
+	v >>= __ffs(m);
+
+	return v;
+}
+
+static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+	u32 c = 0;
+
+	/*
+	 * REVISIT: pwrdm_wait_transition() may be better implemented
+	 * via a callback and a periodic timer check -- how long do we expect
+	 * powerdomain transitions to take?
+	 */
+
+	/* XXX Is this udelay() value meaningful? */
+	while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
+			& OMAP_INTRANSITION_MASK) &&
+			(c++ < PWRDM_TRANSITION_BAILOUT))
+		udelay(1);
+
+	if (c > PWRDM_TRANSITION_BAILOUT) {
+		printk(KERN_ERR "powerdomain: waited too long for "
+				"powerdomain %s to complete transition\n",
+				pwrdm->name);
+		return -EAGAIN;
+	}
+
+	pr_debug("powerdomain: completed transition in %d loops\n", c);
+
+	return 0;
+}
+
+struct pwrdm_ops am33xx_pwrdm_operations = {
+	.pwrdm_set_next_pwrst		= am33xx_pwrdm_set_next_pwrst,
+	.pwrdm_read_next_pwrst		= am33xx_pwrdm_read_next_pwrst,
+	.pwrdm_read_pwrst		= am33xx_pwrdm_read_pwrst,
+	.pwrdm_read_prev_pwrst		= am33xx_pwrdm_read_prev_pwrst,
+	.pwrdm_set_logic_retst		= am33xx_pwrdm_set_logic_retst,
+	.pwrdm_read_logic_pwrst		= am33xx_pwrdm_read_logic_pwrst,
+	.pwrdm_read_logic_retst		= am33xx_pwrdm_read_logic_retst,
+	.pwrdm_clear_all_prev_pwrst	= am33xx_pwrdm_clear_all_prev_pwrst,
+	.pwrdm_set_lowpwrstchange	= am33xx_pwrdm_set_lowpwrstchange,
+	.pwrdm_read_mem_pwrst		= am33xx_pwrdm_read_mem_pwrst,
+	.pwrdm_read_mem_retst		= am33xx_pwrdm_read_mem_retst,
+	.pwrdm_set_mem_onst		= am33xx_pwrdm_set_mem_onst,
+	.pwrdm_set_mem_retst		= am33xx_pwrdm_set_mem_retst,
+	.pwrdm_wait_transition		= am33xx_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
new file mode 100644
index 0000000..869adb8
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -0,0 +1,185 @@
+/*
+ * AM33XX Power domain data
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+#include "prcm-common.h"
+#include "prm-regbits-33xx.h"
+#include "prm33xx.h"
+
+static struct powerdomain gfx_33xx_pwrdm = {
+	.name			= "gfx_pwrdm",
+	.voltdm			= { .name = "core" },
+	.prcm_offs		= AM33XX_PRM_GFX_MOD,
+	.pwrstctrl_offs		= AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
+	.pwrstst_offs		= AM33XX_PM_GFX_PWRSTST_OFFSET,
+	.pwrsts			= PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+	.banks			= 1,
+	.logicretstate_mask	= AM33XX_LOGICRETSTATE_MASK,
+	.mem_on_mask		= {
+		[0]		= AM33XX_GFX_MEM_ONSTATE_MASK,	/* gfx_mem */
+	},
+	.mem_ret_mask		= {
+		[0]		= AM33XX_GFX_MEM_RETSTATE_MASK,	/* gfx_mem */
+	},
+	.mem_pwrst_mask		= {
+		[0]		= AM33XX_GFX_MEM_STATEST_MASK,	/* gfx_mem */
+	},
+	.mem_retst_mask		= {
+		[0]		= AM33XX_GFX_MEM_RETSTATE_MASK,	/* gfx_mem */
+	},
+	.pwrsts_mem_ret		= {
+		[0]		= PWRSTS_OFF_RET,	/* gfx_mem */
+	},
+	.pwrsts_mem_on		= {
+		[0]		= PWRSTS_ON,		/* gfx_mem */
+	},
+};
+
+static struct powerdomain rtc_33xx_pwrdm = {
+	.name			= "rtc_pwrdm",
+	.voltdm			= { .name = "rtc" },
+	.prcm_offs		= AM33XX_PRM_RTC_MOD,
+	.pwrstctrl_offs		= AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
+	.pwrstst_offs		= AM33XX_PM_RTC_PWRSTST_OFFSET,
+	.pwrsts			= PWRSTS_ON,
+	.logicretstate_mask	= AM33XX_LOGICRETSTATE_MASK,
+};
+
+static struct powerdomain wkup_33xx_pwrdm = {
+	.name			= "wkup_pwrdm",
+	.voltdm			= { .name = "core" },
+	.prcm_offs		= AM33XX_PRM_WKUP_MOD,
+	.pwrstctrl_offs		= AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
+	.pwrstst_offs		= AM33XX_PM_WKUP_PWRSTST_OFFSET,
+	.pwrsts			= PWRSTS_ON,
+	.logicretstate_mask	= AM33XX_LOGICRETSTATE_3_3_MASK,
+};
+
+static struct powerdomain per_33xx_pwrdm = {
+	.name			= "per_pwrdm",
+	.voltdm			= { .name = "core" },
+	.prcm_offs		= AM33XX_PRM_PER_MOD,
+	.pwrstctrl_offs		= AM33XX_PM_PER_PWRSTCTRL_OFFSET,
+	.pwrstst_offs		= AM33XX_PM_PER_PWRSTST_OFFSET,
+	.pwrsts			= PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+	.banks			= 3,
+	.logicretstate_mask	= AM33XX_LOGICRETSTATE_3_3_MASK,
+	.mem_on_mask		= {
+		[0]		= AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
+		[1]		= AM33XX_PER_MEM_ONSTATE_MASK,	/* per_mem */
+		[2]		= AM33XX_RAM_MEM_ONSTATE_MASK,	/* ram_mem */
+	},
+	.mem_ret_mask		= {
+		[0]		= AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
+		[1]		= AM33XX_PER_MEM_RETSTATE_MASK,	/* per_mem */
+		[2]		= AM33XX_RAM_MEM_RETSTATE_MASK,	/* ram_mem */
+	},
+	.mem_pwrst_mask		= {
+		[0]		= AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
+		[1]		= AM33XX_PER_MEM_STATEST_MASK,	/* per_mem */
+		[2]		= AM33XX_RAM_MEM_STATEST_MASK,	/* ram_mem */
+	},
+	.mem_retst_mask		= {
+		[0]		= AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
+		[1]		= AM33XX_PER_MEM_RETSTATE_MASK,	/* per_mem */
+		[2]		= AM33XX_RAM_MEM_RETSTATE_MASK,	/* ram_mem */
+	},
+	.pwrsts_mem_ret		= {
+		[0]		= PWRSTS_OFF_RET,	/* pruss_mem */
+		[1]		= PWRSTS_OFF_RET,	/* per_mem */
+		[2]		= PWRSTS_OFF_RET,	/* ram_mem */
+	},
+	.pwrsts_mem_on		= {
+		[0]		= PWRSTS_ON,		/* pruss_mem */
+		[1]		= PWRSTS_ON,		/* per_mem */
+		[2]		= PWRSTS_ON,		/* ram_mem */
+	},
+};
+
+static struct powerdomain mpu_33xx_pwrdm = {
+	.name			= "mpu_pwrdm",
+	.voltdm			= { .name = "mpu" },
+	.prcm_offs		= AM33XX_PRM_MPU_MOD,
+	.pwrstctrl_offs		= AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
+	.pwrstst_offs		= AM33XX_PM_MPU_PWRSTST_OFFSET,
+	.pwrsts			= PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+	.banks			= 3,
+	.logicretstate_mask	= AM33XX_LOGICRETSTATE_MASK,
+	.mem_on_mask		= {
+		[0]		= AM33XX_MPU_L1_ONSTATE_MASK,	/* mpu_l1 */
+		[1]		= AM33XX_MPU_L2_ONSTATE_MASK,	/* mpu_l2 */
+		[2]		= AM33XX_MPU_RAM_ONSTATE_MASK,	/* mpu_ram */
+	},
+	.mem_ret_mask		= {
+		[0]		= AM33XX_MPU_L1_RETSTATE_MASK,	/* mpu_l1 */
+		[1]		= AM33XX_MPU_L2_RETSTATE_MASK,	/* mpu_l2 */
+		[2]		= AM33XX_MPU_RAM_RETSTATE_MASK,	/* mpu_ram */
+	},
+	.mem_pwrst_mask		= {
+		[0]		= AM33XX_MPU_L1_STATEST_MASK,	/* mpu_l1 */
+		[1]		= AM33XX_MPU_L2_STATEST_MASK,	/* mpu_l2 */
+		[2]		= AM33XX_MPU_RAM_STATEST_MASK,	/* mpu_ram */
+	},
+	.mem_retst_mask		= {
+		[0]		= AM33XX_MPU_L1_RETSTATE_MASK,	/* mpu_l1 */
+		[1]		= AM33XX_MPU_L2_RETSTATE_MASK,	/* mpu_l2 */
+		[2]		= AM33XX_MPU_RAM_RETSTATE_MASK,	/* mpu_ram */
+	},
+	.pwrsts_mem_ret		= {
+		[0]		= PWRSTS_OFF_RET,	/* mpu_l1 */
+		[1]		= PWRSTS_OFF_RET,	/* mpu_l2 */
+		[2]		= PWRSTS_OFF_RET,	/* mpu_ram */
+	},
+	.pwrsts_mem_on		= {
+		[0]		= PWRSTS_ON,		/* mpu_l1 */
+		[1]		= PWRSTS_ON,		/* mpu_l2 */
+		[2]		= PWRSTS_ON,		/* mpu_ram */
+	},
+};
+
+static struct powerdomain cefuse_33xx_pwrdm = {
+	.name		= "cefuse_pwrdm",
+	.voltdm		= { .name = "core" },
+	.prcm_offs	= AM33XX_PRM_CEFUSE_MOD,
+	.pwrstctrl_offs	= AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
+	.pwrstst_offs	= AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
+	.pwrsts		= PWRSTS_OFF_ON,
+};
+
+static struct powerdomain *powerdomains_am33xx[] __initdata = {
+	&gfx_33xx_pwrdm,
+	&rtc_33xx_pwrdm,
+	&wkup_33xx_pwrdm,
+	&per_33xx_pwrdm,
+	&mpu_33xx_pwrdm,
+	&cefuse_33xx_pwrdm,
+	NULL,
+};
+
+void __init am33xx_powerdomains_init(void)
+{
+	pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
+	pwrdm_register_pwrdms(powerdomains_am33xx);
+	pwrdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
new file mode 100644
index 0000000..0221b5c
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -0,0 +1,357 @@
+/*
+ * AM33XX PRM_XXX register bits
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+
+#include "prm.h"
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT			1
+#define AM33XX_ABBOFF_ACT_EXPORT_MASK			(1 << 1)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT		2
+#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK			(1 << 2)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_AIPOFF_SHIFT				8
+#define AM33XX_AIPOFF_MASK				(1 << 8)
+
+/* Used by PM_WKUP_PWRSTST */
+#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT		17
+#define AM33XX_DEBUGSS_MEM_STATEST_MASK			(0x3 << 17)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_DISABLE_RTA_EXPORT_SHIFT			0
+#define AM33XX_DISABLE_RTA_EXPORT_MASK			(1 << 0)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT			12
+#define AM33XX_DPLL_CORE_RECAL_EN_MASK			(1 << 12)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT			12
+#define AM33XX_DPLL_CORE_RECAL_ST_MASK			(1 << 12)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT			14
+#define AM33XX_DPLL_DDR_RECAL_EN_MASK			(1 << 14)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT			14
+#define AM33XX_DPLL_DDR_RECAL_ST_MASK			(1 << 14)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT			15
+#define AM33XX_DPLL_DISP_RECAL_EN_MASK			(1 << 15)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT			13
+#define AM33XX_DPLL_DISP_RECAL_ST_MASK			(1 << 13)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT			11
+#define AM33XX_DPLL_MPU_RECAL_EN_MASK			(1 << 11)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT			11
+#define AM33XX_DPLL_MPU_RECAL_ST_MASK			(1 << 11)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_PER_RECAL_EN_SHIFT			13
+#define AM33XX_DPLL_PER_RECAL_EN_MASK			(1 << 13)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_PER_RECAL_ST_SHIFT			15
+#define AM33XX_DPLL_PER_RECAL_ST_MASK			(1 << 15)
+
+/* Used by RM_WKUP_RSTST */
+#define AM33XX_EMULATION_M3_RST_SHIFT			6
+#define AM33XX_EMULATION_M3_RST_MASK			(1 << 6)
+
+/* Used by RM_MPU_RSTST */
+#define AM33XX_EMULATION_MPU_RST_SHIFT			5
+#define AM33XX_EMULATION_MPU_RST_MASK			(1 << 5)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC1_EXPORT_SHIFT			3
+#define AM33XX_ENFUNC1_EXPORT_MASK			(1 << 3)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC3_EXPORT_SHIFT			5
+#define AM33XX_ENFUNC3_EXPORT_MASK			(1 << 5)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC4_SHIFT				6
+#define AM33XX_ENFUNC4_MASK				(1 << 6)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC5_SHIFT				7
+#define AM33XX_ENFUNC5_MASK				(1 << 7)
+
+/* Used by PRM_RSTST */
+#define AM33XX_EXTERNAL_WARM_RST_SHIFT			5
+#define AM33XX_EXTERNAL_WARM_RST_MASK			(1 << 5)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_FORCEWKUP_EN_SHIFT			10
+#define AM33XX_FORCEWKUP_EN_MASK			(1 << 10)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_FORCEWKUP_ST_SHIFT			10
+#define AM33XX_FORCEWKUP_ST_MASK			(1 << 10)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define AM33XX_GFX_MEM_ONSTATE_SHIFT			17
+#define AM33XX_GFX_MEM_ONSTATE_MASK			(0x3 << 17)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define AM33XX_GFX_MEM_RETSTATE_SHIFT			6
+#define AM33XX_GFX_MEM_RETSTATE_MASK			(1 << 6)
+
+/* Used by PM_GFX_PWRSTST */
+#define AM33XX_GFX_MEM_STATEST_SHIFT			4
+#define AM33XX_GFX_MEM_STATEST_MASK			(0x3 << 4)
+
+/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
+#define AM33XX_GFX_RST_SHIFT				0
+#define AM33XX_GFX_RST_MASK				(1 << 0)
+
+/* Used by PRM_RSTST */
+#define AM33XX_GLOBAL_COLD_RST_SHIFT			0
+#define AM33XX_GLOBAL_COLD_RST_MASK			(1 << 0)
+
+/* Used by PRM_RSTST */
+#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT			1
+#define AM33XX_GLOBAL_WARM_SW_RST_MASK			(1 << 1)
+
+/* Used by RM_WKUP_RSTST */
+#define AM33XX_ICECRUSHER_M3_RST_SHIFT			7
+#define AM33XX_ICECRUSHER_M3_RST_MASK			(1 << 7)
+
+/* Used by RM_MPU_RSTST */
+#define AM33XX_ICECRUSHER_MPU_RST_SHIFT			6
+#define AM33XX_ICECRUSHER_MPU_RST_MASK			(1 << 6)
+
+/* Used by PRM_RSTST */
+#define AM33XX_ICEPICK_RST_SHIFT			9
+#define AM33XX_ICEPICK_RST_MASK				(1 << 9)
+
+/* Used by RM_PER_RSTCTRL */
+#define AM33XX_PRUSS_LRST_SHIFT				1
+#define AM33XX_PRUSS_LRST_MASK				(1 << 1)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT			5
+#define AM33XX_PRUSS_MEM_ONSTATE_MASK			(0x3 << 5)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT			7
+#define AM33XX_PRUSS_MEM_RETSTATE_MASK			(1 << 7)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_PRUSS_MEM_STATEST_SHIFT			23
+#define AM33XX_PRUSS_MEM_STATEST_MASK			(0x3 << 23)
+
+/*
+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ */
+#define AM33XX_INTRANSITION_SHIFT			20
+#define AM33XX_INTRANSITION_MASK			(1 << 20)
+
+/* Used by PM_CEFUSE_PWRSTST */
+#define AM33XX_LASTPOWERSTATEENTERED_SHIFT		24
+#define AM33XX_LASTPOWERSTATEENTERED_MASK		(0x3 << 24)
+
+/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
+#define AM33XX_LOGICRETSTATE_SHIFT			2
+#define AM33XX_LOGICRETSTATE_MASK			(1 << 2)
+
+/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
+#define AM33XX_LOGICRETSTATE_3_3_SHIFT			3
+#define AM33XX_LOGICRETSTATE_3_3_MASK			(1 << 3)
+
+/*
+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ */
+#define AM33XX_LOGICSTATEST_SHIFT			2
+#define AM33XX_LOGICSTATEST_MASK			(1 << 2)
+
+/*
+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
+ */
+#define AM33XX_LOWPOWERSTATECHANGE_SHIFT		4
+#define AM33XX_LOWPOWERSTATECHANGE_MASK			(1 << 4)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L1_ONSTATE_SHIFT			18
+#define AM33XX_MPU_L1_ONSTATE_MASK			(0x3 << 18)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L1_RETSTATE_SHIFT			22
+#define AM33XX_MPU_L1_RETSTATE_MASK			(1 << 22)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_L1_STATEST_SHIFT			6
+#define AM33XX_MPU_L1_STATEST_MASK			(0x3 << 6)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L2_ONSTATE_SHIFT			20
+#define AM33XX_MPU_L2_ONSTATE_MASK			(0x3 << 20)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L2_RETSTATE_SHIFT			23
+#define AM33XX_MPU_L2_RETSTATE_MASK			(1 << 23)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_L2_STATEST_SHIFT			8
+#define AM33XX_MPU_L2_STATEST_MASK			(0x3 << 8)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_RAM_ONSTATE_SHIFT			16
+#define AM33XX_MPU_RAM_ONSTATE_MASK			(0x3 << 16)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_RAM_RETSTATE_SHIFT			24
+#define AM33XX_MPU_RAM_RETSTATE_MASK			(1 << 24)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_RAM_STATEST_SHIFT			4
+#define AM33XX_MPU_RAM_STATEST_MASK			(0x3 << 4)
+
+/* Used by PRM_RSTST */
+#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT		2
+#define AM33XX_MPU_SECURITY_VIOL_RST_MASK		(1 << 2)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_PCHARGECNT_VALUE_SHIFT			0
+#define AM33XX_PCHARGECNT_VALUE_MASK			(0x3f << 0)
+
+/* Used by RM_PER_RSTCTRL */
+#define AM33XX_PCI_LRST_SHIFT				0
+#define AM33XX_PCI_LRST_MASK				(1 << 0)
+
+/* Renamed from PCI_LRST Used by RM_PER_RSTST */
+#define AM33XX_PCI_LRST_5_5_SHIFT			5
+#define AM33XX_PCI_LRST_5_5_MASK			(1 << 5)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PER_MEM_ONSTATE_SHIFT			25
+#define AM33XX_PER_MEM_ONSTATE_MASK			(0x3 << 25)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PER_MEM_RETSTATE_SHIFT			29
+#define AM33XX_PER_MEM_RETSTATE_MASK			(1 << 29)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_PER_MEM_STATEST_SHIFT			17
+#define AM33XX_PER_MEM_STATEST_MASK			(0x3 << 17)
+
+/*
+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL
+ */
+#define AM33XX_POWERSTATE_SHIFT				0
+#define AM33XX_POWERSTATE_MASK				(0x3 << 0)
+
+/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
+#define AM33XX_POWERSTATEST_SHIFT			0
+#define AM33XX_POWERSTATEST_MASK			(0x3 << 0)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_RAM_MEM_ONSTATE_SHIFT			30
+#define AM33XX_RAM_MEM_ONSTATE_MASK			(0x3 << 30)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_RAM_MEM_RETSTATE_SHIFT			27
+#define AM33XX_RAM_MEM_RETSTATE_MASK			(1 << 27)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_RAM_MEM_STATEST_SHIFT			21
+#define AM33XX_RAM_MEM_STATEST_MASK			(0x3 << 21)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_RETMODE_ENABLE_SHIFT			0
+#define AM33XX_RETMODE_ENABLE_MASK			(1 << 0)
+
+/* Used by REVISION_PRM */
+#define AM33XX_REV_SHIFT				0
+#define AM33XX_REV_MASK					(0xff << 0)
+
+/* Used by PRM_RSTTIME */
+#define AM33XX_RSTTIME1_SHIFT				0
+#define AM33XX_RSTTIME1_MASK				(0xff << 0)
+
+/* Used by PRM_RSTTIME */
+#define AM33XX_RSTTIME2_SHIFT				8
+#define AM33XX_RSTTIME2_MASK				(0x1f << 8)
+
+/* Used by PRM_RSTCTRL */
+#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT			1
+#define AM33XX_RST_GLOBAL_COLD_SW_MASK			(1 << 1)
+
+/* Used by PRM_RSTCTRL */
+#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT			0
+#define AM33XX_RST_GLOBAL_WARM_SW_MASK			(1 << 0)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_SLPCNT_VALUE_SHIFT			16
+#define AM33XX_SLPCNT_VALUE_MASK			(0xff << 16)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_SRAMLDO_STATUS_SHIFT			8
+#define AM33XX_SRAMLDO_STATUS_MASK			(1 << 8)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_SRAM_IN_TRANSITION_SHIFT			9
+#define AM33XX_SRAM_IN_TRANSITION_MASK			(1 << 9)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_STARTUP_COUNT_SHIFT			24
+#define AM33XX_STARTUP_COUNT_MASK			(0xff << 24)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_TRANSITION_EN_SHIFT			8
+#define AM33XX_TRANSITION_EN_MASK			(1 << 8)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_TRANSITION_ST_SHIFT			8
+#define AM33XX_TRANSITION_ST_MASK			(1 << 8)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_VSETUPCNT_VALUE_SHIFT			8
+#define AM33XX_VSETUPCNT_VALUE_MASK			(0xff << 8)
+
+/* Used by PRM_RSTST */
+#define AM33XX_WDT0_RST_SHIFT				3
+#define AM33XX_WDT0_RST_MASK				(1 << 3)
+
+/* Used by PRM_RSTST */
+#define AM33XX_WDT1_RST_SHIFT				4
+#define AM33XX_WDT1_RST_MASK				(1 << 4)
+
+/* Used by RM_WKUP_RSTCTRL */
+#define AM33XX_WKUP_M3_LRST_SHIFT			3
+#define AM33XX_WKUP_M3_LRST_MASK			(1 << 3)
+
+/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
+#define AM33XX_WKUP_M3_LRST_5_5_SHIFT			5
+#define AM33XX_WKUP_M3_LRST_5_5_MASK			(1 << 5)
+
+#endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
new file mode 100644
index 0000000..7444855
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -0,0 +1,134 @@
+/*
+ * AM33XX PRM functions
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "common.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+/* Read a register in a PRM instance */
+u32 am33xx_prm_read_reg(s16 inst, u16 idx)
+{
+	return __raw_readl(prm_base + inst + idx);
+}
+
+/* Write into a register in a PRM instance */
+void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
+{
+	__raw_writel(val, prm_base + inst + idx);
+}
+
+/* Read-modify-write a register in PRM. Caller must lock */
+u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(inst, idx);
+	v &= ~mask;
+	v |= bits;
+	am33xx_prm_write_reg(v, inst, idx);
+
+	return v;
+}
+
+/**
+ * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @shift: register bit shift corresponding to the reset line to check
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_offs: RM_RSTCTRL register address offset for this module
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL upon parameter error.
+ */
+int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(inst, rstctrl_offs);
+	v &= 1 << shift;
+	v >>= shift;
+
+	return v;
+}
+
+/**
+ * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
+ * @shift: register bit shift corresponding to the reset line to assert
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
+{
+	u32 mask = 1 << shift;
+
+	am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
+
+	return 0;
+}
+
+/**
+ * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
+ * wait
+ * @shift: register bit shift corresponding to the reset line to deassert
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @rstst_reg: RM_RSTST register address for this module
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+		u16 rstctrl_offs, u16 rstst_offs)
+{
+	int c;
+	u32 mask = 1 << shift;
+
+	/* Check the current status to avoid  de-asserting the line twice */
+	if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
+		return -EEXIST;
+
+	/* Clear the reset status by writing 1 to the status bit */
+	am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
+	/* de-assert the reset control line */
+	am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
+	/* wait the status to be set */
+
+	omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
+				rstst_offs), MAX_MODULE_HARDRESET_WAIT, c);
+
+	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
new file mode 100644
index 0000000..3f25c56
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -0,0 +1,129 @@
+/*
+ * AM33XX PRM instance offset macros
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+
+#define AM33XX_PRM_BASE               0x44E00000
+
+#define AM33XX_PRM_REGADDR(inst, reg)                         \
+	AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define AM33XX_PRM_OCP_SOCKET_MOD	0x0B00
+#define AM33XX_PRM_PER_MOD		0x0C00
+#define AM33XX_PRM_WKUP_MOD		0x0D00
+#define AM33XX_PRM_MPU_MOD		0x0E00
+#define AM33XX_PRM_DEVICE_MOD		0x0F00
+#define AM33XX_PRM_RTC_MOD		0x1000
+#define AM33XX_PRM_GFX_MOD		0x1100
+#define AM33XX_PRM_CEFUSE_MOD		0x1200
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define AM33XX_REVISION_PRM_OFFSET		0x0000
+#define AM33XX_REVISION_PRM			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
+#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET		0x0004
+#define AM33XX_PRM_IRQSTATUS_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
+#define AM33XX_PRM_IRQENABLE_MPU_OFFSET		0x0008
+#define AM33XX_PRM_IRQENABLE_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
+#define AM33XX_PRM_IRQSTATUS_M3_OFFSET		0x000c
+#define AM33XX_PRM_IRQSTATUS_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
+#define AM33XX_PRM_IRQENABLE_M3_OFFSET		0x0010
+#define AM33XX_PRM_IRQENABLE_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
+
+/* PRM.PER_PRM register offsets */
+#define AM33XX_RM_PER_RSTCTRL_OFFSET		0x0000
+#define AM33XX_RM_PER_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
+#define AM33XX_RM_PER_RSTST_OFFSET		0x0004
+#define AM33XX_RM_PER_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
+#define AM33XX_PM_PER_PWRSTST_OFFSET		0x0008
+#define AM33XX_PM_PER_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
+#define AM33XX_PM_PER_PWRSTCTRL_OFFSET		0x000c
+#define AM33XX_PM_PER_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
+
+/* PRM.WKUP_PRM register offsets */
+#define AM33XX_RM_WKUP_RSTCTRL_OFFSET		0x0000
+#define AM33XX_RM_WKUP_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
+#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET		0x0004
+#define AM33XX_PM_WKUP_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
+#define AM33XX_PM_WKUP_PWRSTST_OFFSET		0x0008
+#define AM33XX_PM_WKUP_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
+#define AM33XX_RM_WKUP_RSTST_OFFSET		0x000c
+#define AM33XX_RM_WKUP_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
+
+/* PRM.MPU_PRM register offsets */
+#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET		0x0000
+#define AM33XX_PM_MPU_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
+#define AM33XX_PM_MPU_PWRSTST_OFFSET		0x0004
+#define AM33XX_PM_MPU_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
+#define AM33XX_RM_MPU_RSTST_OFFSET		0x0008
+#define AM33XX_RM_MPU_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
+
+/* PRM.DEVICE_PRM register offsets */
+#define AM33XX_PRM_RSTCTRL_OFFSET		0x0000
+#define AM33XX_PRM_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
+#define AM33XX_PRM_RSTTIME_OFFSET		0x0004
+#define AM33XX_PRM_RSTTIME			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
+#define AM33XX_PRM_RSTST_OFFSET			0x0008
+#define AM33XX_PRM_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
+#define AM33XX_PRM_SRAM_COUNT_OFFSET		0x000c
+#define AM33XX_PRM_SRAM_COUNT			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET	0x0010
+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET	0x0014
+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET	0x0018
+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET	0x001c
+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
+
+/* PRM.RTC_PRM register offsets */
+#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET		0x0000
+#define AM33XX_PM_RTC_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
+#define AM33XX_PM_RTC_PWRSTST_OFFSET		0x0004
+#define AM33XX_PM_RTC_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
+
+/* PRM.GFX_PRM register offsets */
+#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET		0x0000
+#define AM33XX_PM_GFX_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
+#define AM33XX_RM_GFX_RSTCTRL_OFFSET		0x0004
+#define AM33XX_RM_GFX_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
+#define AM33XX_PM_GFX_PWRSTST_OFFSET		0x0010
+#define AM33XX_PM_GFX_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
+#define AM33XX_RM_GFX_RSTST_OFFSET		0x0014
+#define AM33XX_RM_GFX_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
+
+/* PRM.CEFUSE_PRM register offsets */
+#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET	0x0000
+#define AM33XX_PM_CEFUSE_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
+#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET		0x0004
+#define AM33XX_PM_CEFUSE_PWRSTST		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
+
+extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
+extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
+extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+extern void am33xx_prm_global_warm_sw_reset(void);
+extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
+		u16 rstctrl_offs);
+extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
+extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+		u16 rstctrl_offs, u16 rstst_offs);
+#endif
--
1.7.0.4



From LW at KARO-electronics.de  Thu Mar 15 07:22:04 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Thu, 15 Mar 2012 12:22:04 +0100
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120315105927.GE13022@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
Message-ID: <20321.53468.310199.875966@ipc1.ka-ro>

Hi,

Dong Aisheng writes:
> On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa?mann wrote:
> > Hi,
> > 
> > Dong Aisheng writes:
> > > On Wed, Mar 14, 2012 at 10:16:43PM +0800, s.hauer at pengutronix.de wrote:
> > > > On Wed, Mar 14, 2012 at 08:45:23PM +0800, Dong Aisheng wrote:
> > > > > On Wed, Mar 14, 2012 at 01:23:51AM +0800, Grant Likely wrote:
> > [...]
> > > > > But it seems this needs pass mac address to fec driver via platforom data which is
> > > > > not friendly to dt.
> > > > > 
> > > > > Another way may be changing fec driver to get the fixed part of mac address(first
> > > > > two bytes) from device tree and read the left dynamical part from otp which i'm not
> > > > > sure is better enough.
> > > > > 
> > > > > BTW, filling with zeros seems not work since it's invalid mac address.
> > > > 
> > > > Yes, that's the idea of using this value...
> > > > 
> > > But comparing to use an invalid value, why not just do not define that
> > > local-mac-address property?
> > > 
> > Because a MAC address is by definition a GLOBALLY UNIQUE IDENTIFIER
> > which is contrary to coding a "valid" default value for it somewhere!
> > The owner of a certain MAC address range (OUI) is responsible for
> > ensuring the uniqueness. Thus only they may assign a specific MAC
> > address to a specific device.
> > 
> Yes, you're correct.
> So i propose to read the MAC address from MX28 OTP in fec driver instead of
> define it in device tree in my last mail.
> http://www.spinics.net/lists/arm-kernel/msg165040.html
> Do you have any comment on that way?
> 
That patch sets the OUI to the Freescale owned MAC range. Thus only
Freescale products may be able to use the driver.

Anyway there is no definite spec how the MAC address(es) are stored
in the fuse map. Thus reading the MAC from there is more or less
platform specific.

Currently I'm setting up the MAC address for our TX28 from the fuses
in the platform code passed via platform_data, but that will obviously
not work with DT.

The correct way would probably be to pass the MAC from the bootloader
via a DT blob. But that would require all bootloaders to be updated
first to support DTS. :(

An intermediate solution could be using OF_DEV_AUXDATA to pass a
platform_data struct that may contain a MAC address set up by the
platform code.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From s.hauer at pengutronix.de  Thu Mar 15 07:24:19 2012
From: s.hauer at pengutronix.de (s.hauer at pengutronix.de)
Date: Thu, 15 Mar 2012 12:24:19 +0100
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120315105927.GE13022@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
Message-ID: <20120315112419.GA3852@pengutronix.de>

On Thu, Mar 15, 2012 at 06:59:28PM +0800, Dong Aisheng wrote:
> On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa?mann wrote:
> > Hi,
> > 
> > Dong Aisheng writes:
> > > On Wed, Mar 14, 2012 at 10:16:43PM +0800, s.hauer at pengutronix.de wrote:
> > > > On Wed, Mar 14, 2012 at 08:45:23PM +0800, Dong Aisheng wrote:
> > > > > On Wed, Mar 14, 2012 at 01:23:51AM +0800, Grant Likely wrote:
> > [...]
> > > > > But it seems this needs pass mac address to fec driver via platforom data which is
> > > > > not friendly to dt.
> > > > > 
> > > > > Another way may be changing fec driver to get the fixed part of mac address(first
> > > > > two bytes) from device tree and read the left dynamical part from otp which i'm not
> > > > > sure is better enough.
> > > > > 
> > > > > BTW, filling with zeros seems not work since it's invalid mac address.
> > > > 
> > > > Yes, that's the idea of using this value...
> > > > 
> > > But comparing to use an invalid value, why not just do not define that
> > > local-mac-address property?
> > > 
> > Because a MAC address is by definition a GLOBALLY UNIQUE IDENTIFIER
> > which is contrary to coding a "valid" default value for it somewhere!
> > The owner of a certain MAC address range (OUI) is responsible for
> > ensuring the uniqueness. Thus only they may assign a specific MAC
> > address to a specific device.
> > 
> Yes, you're correct.
> So i propose to read the MAC address from MX28 OTP in fec driver instead of
> define it in device tree in my last mail.
> http://www.spinics.net/lists/arm-kernel/msg165040.html
> Do you have any comment on that way?

Yes, you could do that. Otherwise it's perfectly fine to pass the MAC
address in the device tree, it's just not ok to put specific values
into the kernel source. You could leave the values blank and let the
bootloader fill them in. Or you could fill in valid values before you
compile the devicetree, but be prepared for surprises once you have
two boards in your network and use the devicetree for both.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Thu Mar 15 07:40:27 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 11:40:27 +0000
Subject: [PATCH v3] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <4F61CC81.1020902@st.com>
References: <1331808632-22585-1-git-send-email-sr@denx.de>
 <4F61CC81.1020902@st.com>
Message-ID: <201203151140.27453.arnd@arndb.de>

On Thursday 15 March 2012, Viresh Kumar wrote:
> On 3/15/2012 4:20 PM, Stefan Roese wrote:
> 
> > diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
> 
> > +/ {
> > +       compatible = "st,spear600";
> > +
> > +       cpus {
> > +               cpu at 0 {
> > +                       compatible = "arm,arm926ejs";
> > +               };
> > +       };
> > +
> > +       memory {
> > +               device_type = "memory";
> > +               reg = <0 0x40000000>; /* Real value updated by U-Boot */
> > +       };
> > +
> > +       ahb {
> 
> What is the significance of this name? As i see gpio/spi etc in this list,
> which are on apb bus.

That sounds like it should be corrected, the device tree should reflect
the physical hierarchy where possible, e.g.

	ahb0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0xe0000000 0xe0000000 0x10000000>;

		ethernet at e0800000 {
			...
		};

		...
	};

	ahb1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0xd0000000 0xd0000000 0x10000000>;
		ranges = <0xf0000000 0xf0000000 0x10000000>;

		apb {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x0 0xf0000000 0x10000000>;
	
			gpio at f0100000 {
				/* note: reg relative to local ranges property */
				reg = <0x100000 0x1000>;
				...
			};
			...
		};
		...


               i2c at d0200000 {
                        reg = <0xd0200000 0x1000>;
			...
               };

	};

I don't have the data sheet, so the bus hierarchy above is completely made up,
but I guess you get the idea. If each bus has its own local register range, it
may be helpful to use the ranges property to remap the reg properties in the
way that I did in the apb example above.

	Arnd


From linux at arm.linux.org.uk  Thu Mar 15 07:41:51 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 11:41:51 +0000
Subject: [PATCH v7] ARM: net: JIT compiler for packet filters
In-Reply-To: <1325937154-2656-1-git-send-email-mgherzan@gmail.com>
References: <1325937154-2656-1-git-send-email-mgherzan@gmail.com>
Message-ID: <20120315114151.GC15988@n2100.arm.linux.org.uk>

I'm unconvinced that this is safe.

On Sat, Jan 07, 2012 at 12:52:34PM +0100, Mircea Gherzan wrote:
> +static int build_body(struct jit_ctx *ctx)
> +{
> +	void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
> +	const struct sk_filter *prog = ctx->skf;
> +	const struct sock_filter *inst;
> +	unsigned i, load_order, off, condt;
> +	int imm12;
> +	u32 k;
> +
> +	for (i = 0; i < prog->len; i++) {
> +		inst = &(prog->insns[i]);
> +		/* K as an immediate value operand */
> +		k = inst->k;
> +
> +		/* compute offsets only in the fake pass */
> +		if (ctx->target == NULL)
> +			ctx->offsets[i] = ctx->idx * 4;
> +
> +		switch (inst->code) {
> +		case BPF_S_LD_IMM:
> +			emit_mov_i(r_A, k, ctx);
> +			break;
> +		case BPF_S_LD_W_LEN:
> +			ctx->seen |= SEEN_SKB;
> +			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
> +			emit(ARM_LDR_I(r_A, r_skb,
> +				       offsetof(struct sk_buff, len)), ctx);
> +			break;
> +		case BPF_S_LD_MEM:
> +			/* A = scratch[k] */
> +			ctx->seen |= SEEN_MEM_WORD(k);
> +			emit(ARM_LDR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
> +			break;
> +		case BPF_S_LD_W_ABS:
> +			load_order = 2;
> +			goto load;
> +		case BPF_S_LD_H_ABS:
> +			load_order = 1;
> +			goto load;
> +		case BPF_S_LD_B_ABS:
> +			load_order = 0;
> +load:
> +			/* the interpreter will deal with the negative K */
> +			if (k < 0)
> +				return -1;

k is a u32, so won't this will always be false - negative numbers will
appear as huge positive numbers instead.

> +			emit_mov_i(r_off, k, ctx);
> +load_common:
> +			ctx->seen |= SEEN_DATA | SEEN_CALL;
> +
> +			if (load_order > 0) {
> +				emit(ARM_SUB_I(r_scratch, r_skb_hl,
> +					       1 << load_order), ctx);
> +				emit(ARM_CMP_R(r_scratch, r_off), ctx);
> +				condt = ARM_COND_HS;
> +			} else {
> +				emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
> +				condt = ARM_COND_HI;
> +			}
> +
> +			_emit(condt, ARM_ADD_R(r_scratch, r_off, r_skb_data),
> +			      ctx);
> +
> +			if (load_order == 0)
> +				_emit(condt, ARM_LDRB_I(r_A, r_scratch, 0),
> +				      ctx);
> +			else if (load_order == 1)
> +				emit_load_be16(condt, r_A, r_scratch, ctx);
> +			else if (load_order == 2)
> +				emit_load_be32(condt, r_A, r_scratch, ctx);

I think this is creating code to do something like this:

	sub r_scratch, r_skb_hl, #1 << load_order
	cmp r_scratch, k
	ldrhs dest, [r_skb_data, k]

Isn't this going to perform the loads for any k greater than the header
length?  What stops k being larger than the packet?  And is this correct
in the first place?

> +
> +			_emit(condt, ARM_B(b_imm(i + 1, ctx)), ctx);
> +
> +			/* the slowpath */
> +			emit_mov_i(ARM_R3, (u32)load_func[load_order], ctx);
> +			emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
> +			/* the offset is already in R1 */
> +			emit_blx_r(ARM_R3, ctx);
> +			/* check the result of skb_copy_bits */
> +			emit(ARM_CMP_I(ARM_R1, 0), ctx);
> +			emit_err_ret(ARM_COND_NE, ctx);
> +			emit(ARM_MOV_R(r_A, ARM_R0), ctx);
> +			break;
> +		case BPF_S_LD_W_IND:
> +			load_order = 2;
> +			goto load_ind;
> +		case BPF_S_LD_H_IND:
> +			load_order = 1;
> +			goto load_ind;
> +		case BPF_S_LD_B_IND:
> +			load_order = 0;
> +load_ind:
> +			OP_IMM3(ARM_ADD, r_off, r_X, k, ctx);
> +			goto load_common;
> +		case BPF_S_LDX_IMM:
> +			ctx->seen |= SEEN_X;
> +			emit_mov_i(r_X, k, ctx);
> +			break;
> +		case BPF_S_LDX_W_LEN:
> +			ctx->seen |= SEEN_X | SEEN_SKB;
> +			emit(ARM_LDR_I(r_X, r_skb,
> +				       offsetof(struct sk_buff, len)), ctx);
> +			break;
> +		case BPF_S_LDX_MEM:
> +			ctx->seen |= SEEN_X | SEEN_MEM_WORD(k);
> +			emit(ARM_LDR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);

What about this - SCRATCH_OFF() is just a simple:
	+#define SCRATCH_OFF(k)         (SCRATCH_SP_OFFSET + (k))

So what if 'k' is a carefully chosen 32-bit number outside of the range
of the stack?  Shouldn't there be a check for k < BPF_MEMWORDS to fail
the translation where-ever SEEN_MEM_WORD(k) or SCRATCH_OFF(k) is used?

> +			break;
> +		case BPF_S_LDX_B_MSH:
> +			/* x = ((*(frame + k)) & 0xf) << 2; */

So, k is passed in from userspace.  What stops k being out of the bounds
of 'frame' and referring to other kernel space data via carefully crafted
bpf code?

> +			ctx->seen |= SEEN_X | SEEN_DATA | SEEN_CALL;
> +			/* the interpreter should deal with the negative K */
> +			if (k < 0)
> +				return -1;
> +			/* offset in r1: we might have to take the slow path */
> +			emit_mov_i(r_off, k, ctx);
> +			emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
> +
> +			/* load in r0: common with the slowpath */
> +			_emit(ARM_COND_HI, ARM_LDRB_R(ARM_R0, r_skb_data,
> +						      ARM_R1), ctx);
> +			/*
> +			 * emit_mov_i() might generate one or two instructions,
> +			 * the same holds for emit_blx_r()
> +			 */
> +			_emit(ARM_COND_HI, ARM_B(b_imm(i + 1, ctx) - 2), ctx);
> +
> +			emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
> +			/* r_off is r1 */
> +			emit_mov_i(ARM_R3, (u32)jit_get_skb_b, ctx);
> +			emit_blx_r(ARM_R3, ctx);
> +
> +			emit(ARM_AND_I(r_X, ARM_R0, 0x00f), ctx);
> +			emit(ARM_LSL_I(r_X, r_X, 2), ctx);
> +			break;
> +		case BPF_S_ST:
> +			ctx->seen |= SEEN_MEM_WORD(k);
> +			emit(ARM_STR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
> +			break;
> +		case BPF_S_STX:
> +			update_on_xread(ctx);
> +			ctx->seen |= SEEN_MEM_WORD(k);
> +			emit(ARM_STR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
> +			break;
> +		case BPF_S_ALU_ADD_K:
> +			/* A += K */
> +			OP_IMM3(ARM_ADD, r_A, r_A, k, ctx);
> +			break;
> +		case BPF_S_ALU_ADD_X:
> +			update_on_xread(ctx);
> +			emit(ARM_ADD_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_SUB_K:
> +			/* A -= K */
> +			OP_IMM3(ARM_SUB, r_A, r_A, k, ctx);
> +			break;
> +		case BPF_S_ALU_SUB_X:
> +			update_on_xread(ctx);
> +			emit(ARM_SUB_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_MUL_K:
> +			/* A *= K */
> +			emit_mov_i(r_scratch, k, ctx);
> +			emit(ARM_MUL(r_A, r_A, r_scratch), ctx);
> +			break;
> +		case BPF_S_ALU_MUL_X:
> +			update_on_xread(ctx);
> +			emit(ARM_MUL(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_DIV_K:
> +			/* current k == reciprocal_value(userspace k) */
> +			emit_mov_i(r_scratch, k, ctx);
> +			/* A = top 32 bits of the product */
> +			emit(ARM_UMULL(r_scratch, r_A, r_A, r_scratch), ctx);
> +			break;
> +		case BPF_S_ALU_DIV_X:
> +			update_on_xread(ctx);
> +			emit(ARM_CMP_I(r_X, 0), ctx);
> +			emit_err_ret(ARM_COND_EQ, ctx);
> +			emit_udiv(r_A, r_A, r_X, ctx);
> +			break;
> +		case BPF_S_ALU_OR_K:
> +			/* A |= K */
> +			OP_IMM3(ARM_ORR, r_A, r_A, k, ctx);
> +			break;
> +		case BPF_S_ALU_OR_X:
> +			update_on_xread(ctx);
> +			emit(ARM_ORR_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_AND_K:
> +			/* A &= K */
> +			OP_IMM3(ARM_AND, r_A, r_A, k, ctx);
> +			break;
> +		case BPF_S_ALU_AND_X:
> +			update_on_xread(ctx);
> +			emit(ARM_AND_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_LSH_K:
> +			if (unlikely(k > 31))
> +				return -1;
> +			emit(ARM_LSL_I(r_A, r_A, k), ctx);
> +			break;
> +		case BPF_S_ALU_LSH_X:
> +			update_on_xread(ctx);
> +			emit(ARM_LSL_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_RSH_K:
> +			if (unlikely(k > 31))
> +				return -1;
> +			emit(ARM_LSR_I(r_A, r_A, k), ctx);
> +			break;
> +		case BPF_S_ALU_RSH_X:
> +			update_on_xread(ctx);
> +			emit(ARM_LSR_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_NEG:
> +			/* A = -A */
> +			emit(ARM_RSB_I(r_A, r_A, 0), ctx);
> +			break;
> +		case BPF_S_JMP_JA:
> +			/* pc += K */
> +			emit(ARM_B(b_imm(i + k + 1, ctx)), ctx);

This seems to allow the offset[] array to be indexed by an out of bounds
32-bit offset (k).  What stops that, therefore what prevents reading a
target jump address from a random location in kernel space?

I think b_imm() should check that it's not going to overflow its array
of offsets.


From marc.zyngier at arm.com  Thu Mar 15 07:47:22 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu, 15 Mar 2012 11:47:22 +0000
Subject: [PATCH v4 09/15] ARM: ux500: convert to twd_local_timer_register()
 interface
In-Reply-To: <4F60D7DD.50705@linaro.org>
References: <1327061042-14857-1-git-send-email-marc.zyngier@arm.com>
 <1327061042-14857-10-git-send-email-marc.zyngier@arm.com>
 <CANmRt2gjhg-nznAOxQHA1g7EX+F4uEjp1nW5iT3Rtw4s8y5uGg@mail.gmail.com>
 <4F60D7DD.50705@linaro.org>
Message-ID: <4F61D6CA.8060002@arm.com>

On 14/03/12 17:39, Lee Jones wrote:

> NAK: Won't build. :(

Thanks for noticing this.

I've just pushed a fix to local_timers-for-arm-soc, and the patch should
be on the ML shortly.

	M.
-- 
Jazz is not dead. It just smells funny...



From marc.zyngier at arm.com  Thu Mar 15 07:47:26 2012
From: marc.zyngier at arm.com (Marc Zyngier)
Date: Thu, 15 Mar 2012 11:47:26 +0000
Subject: [PATCH -next] ARM: ux500: fix compilation after local timer rework
Message-ID: <1331812046-21062-1-git-send-email-marc.zyngier@arm.com>

mach-ux500/timer.c lacked the inclusion of mach/irqs.h, and thus
failed to compile. Fix it and also remove an unused variable.

Test compiled only.

Reported-by: Lee Jones <lee.jones at linaro.org>
Cc: Arnd Bergman <arnd at arndb.de>
Cc: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
---
Arnd,

I've pushed this patch to my local_timers-for-arm-soc. If you can pull
it one more time, that would be great.

Thanks,

	M.

 arch/arm/mach-ux500/timer.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index fbeed7e..e9d5807 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -14,6 +14,7 @@
 
 #include <mach/setup.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 
 #ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer,
@@ -41,7 +42,6 @@ static void __init ux500_timer_init(void)
 {
 	void __iomem *mtu_timer_base;
 	void __iomem *prcmu_timer_base;
-	int err;
 
 	if (cpu_is_u5500()) {
 		mtu_timer_base = __io_address(U5500_MTU0_BASE);
-- 
1.7.7.1




From broonie at opensource.wolfsonmicro.com  Thu Mar 15 08:09:48 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 15 Mar 2012 12:09:48 +0000
Subject: [PATCH v9] mfd: Add anatop mfd driver
In-Reply-To: <201203150907.29895.arnd@arndb.de>
References: <1331797421-23731-1-git-send-email-paul.liu@linaro.org>
 <201203150907.29895.arnd@arndb.de>
Message-ID: <20120315120948.GG3138@opensource.wolfsonmicro.com>

On Thu, Mar 15, 2012 at 09:07:29AM +0000, Arnd Bergmann wrote:

> Very broadly speaking, I wonder whether we could use the regmap
> infrastructure for these things in the future, but I would first
> need to understand whether that is actually in the scope of regmap.

> It seems that you just need a subset of what regmap provides,
> so it could work, but it might not actually be better than what
> you have now.

> Mark, can you comment on that?

There were some other mutterings about using regmap for memory mapped
devices, mostly from the point of view of building framework features
like this on top of it.  regmap currently makes some assumptions that
the I/O is going to be slow so approximately any amount of CPU time can
usefully be spent on avoiding I/O but we can probably do something about
that.  It also uses mutexes to lock I/O which might not be the most
sensible thing for memory mapped devices, but again that's solveable.
Right now there's no memory mapping support but there's no reason that
can't be added.

In short, it does seem sensible to want to have some support for this
for devices that use appropriate idioms.
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From festevam at gmail.com  Thu Mar 15 08:19:55 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 15 Mar 2012 09:19:55 -0300
Subject: [GIT PULL] i.MX35 3ds updates
In-Reply-To: <20120314192249.GR3852@pengutronix.de>
References: <20120314192249.GR3852@pengutronix.de>
Message-ID: <CAOMZO5C5dTpqWunYTMv2WJ5Neertd-mrfM6R2+fu3X2B+W_X7g@mail.gmail.com>

Hi Sascha,

On Wed, Mar 14, 2012 at 4:22 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:

> ----------------------------------------------------------------
> Alex Gershgorin (1):
> ? ? ?i.MX35-PDK: Add Camera support

For the camera to be registered correctly it needs this patch:
http://patchwork.ozlabs.org/patch/144942/

Would be nice if it could be part of this pull request.

Thanks,

Fabio Estevam


From arnd at arndb.de  Thu Mar 15 08:44:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 12:44:37 +0000
Subject: [PATCH v4 03/10] pwm: Add device tree support
In-Reply-To: <20120315102944.GB3138@opensource.wolfsonmicro.com>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <201203150840.42659.arnd@arndb.de>
 <20120315102944.GB3138@opensource.wolfsonmicro.com>
Message-ID: <201203151244.37483.arnd@arndb.de>

On Thursday 15 March 2012, Mark Brown wrote:
> Similar code is going in for regulators in 3.4 along with the core
> -EPROBE_DEFER change (though not OF specific) and I sent a similar patch
> for GPIOs too, hopefully Grant will ack it in time for it to make it in.
> 
> My theory is that since you need to explicitly know that the thing
> you're requesting is there in order to request it (eg, have a PWM number
> or DT link) the overwhemlingly common case for a failure to request will
> be that the provider didn't register yet which is exactly the case where
> deferral is desired.  It therefore seems sensible to have the framework
> default the drivers to retrying rather than have almost every individual
> driver look at the failure, figure out if it was a missing provider, and
> then retry.  Drivers that have a good reason to fail can always check
> for -EPROBE_DEFER and override it.
> 
> The result should be that we can take advantage of probe deferral over
> large areas of the kernel without having to go and explicitly modify so
> many drivers - if the frameworks like GPIO, clk and regulator can do
> this that ought to cover 90% of the cases where probe deferral will be
> needed without having to do anything more than have good error handling
> paths on probe which is a good idea anyway.

Ok, makes sense.

Thanks,
	
	Arnd


From nicolas.ferre at atmel.com  Thu Mar 15 09:00:09 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 14:00:09 +0100
Subject: [PATCH 1/6] ARM: at91: change AT91 Kconfig entry comment
Message-ID: <feb3f4c639fae3f01636ba2017968fac1078ddca.1331816340.git.nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/Kconfig |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cabd8f5..e7043c8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -324,8 +324,8 @@ config ARCH_AT91
 	select CLKDEV_LOOKUP
 	select IRQ_DOMAIN
 	help
-	  This enables support for systems based on the Atmel AT91RM9200,
-	  AT91SAM9 processors.
+	  This enables support for systems based on Atmel
+	  AT91RM9200 and AT91SAM9* processors.
 
 config ARCH_BCMRING
 	bool "Broadcom BCMRING"
-- 
1.7.9



From nicolas.ferre at atmel.com  Thu Mar 15 09:00:13 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 14:00:13 +0100
Subject: [PATCH 5/6] ARM: at91/Kconfig: add AT91SAM9x5 family to
 AT91_EARLY_DBGU0 entry
In-Reply-To: <feb3f4c639fae3f01636ba2017968fac1078ddca.1331816340.git.nicolas.ferre@atmel.com>
References: <feb3f4c639fae3f01636ba2017968fac1078ddca.1331816340.git.nicolas.ferre@atmel.com>
Message-ID: <5cf97bff4110a92ed592b5e0cfe33ac35df2c591.1331816340.git.nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6e02b58..24da4cc 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -535,7 +535,7 @@ choice
 	prompt "Select a UART for early kernel messages"
 
 config AT91_EARLY_DBGU0
-	bool "DBGU on rm9200, 9260/9g20, 9261/9g10 and 9rl"
+	bool "DBGU on rm9200, 9260/9g20, 9261/9g10, 9rl and 9x5"
 	depends on HAVE_AT91_DBGU0
 
 config AT91_EARLY_DBGU1
-- 
1.7.9



From nicolas.ferre at atmel.com  Thu Mar 15 09:00:11 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 14:00:11 +0100
Subject: [PATCH 3/6] ARM: at91/Kconfig: add comment to at91sam9x5 family entry
In-Reply-To: <feb3f4c639fae3f01636ba2017968fac1078ddca.1331816340.git.nicolas.ferre@atmel.com>
References: <feb3f4c639fae3f01636ba2017968fac1078ddca.1331816340.git.nicolas.ferre@atmel.com>
Message-ID: <ab6ff7bf84cdf0b77dd5402a4988aa9810fe1ecc.1331816340.git.nicolas.ferre@atmel.com>

Add comment to make it clear that several SoC are supported by
this generic entry.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/Kconfig |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 5f0fe11..4a896c6 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -113,6 +113,12 @@ config ARCH_AT91SAM9X5
 	select HAVE_NET_MACB
 	select HAVE_AT91_DBGU0
 	select AT91_SAM9G45_RESET
+	help
+	  Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
+	  This means that your SAM9 name finishes with a '5' (except if it is
+	  AT91SAM9G45!).
+	  This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35
+	  and AT91SAM9X35.
 
 config ARCH_AT91X40
 	bool "AT91x40"
-- 
1.7.9



From nicolas.ferre at atmel.com  Thu Mar 15 09:00:10 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 14:00:10 +0100
Subject: [PATCH 2/6] ARM: at91/Kconfig: change at91sam9g45 entry
In-Reply-To: <feb3f4c639fae3f01636ba2017968fac1078ddca.1331816340.git.nicolas.ferre@atmel.com>
References: <feb3f4c639fae3f01636ba2017968fac1078ddca.1331816340.git.nicolas.ferre@atmel.com>
Message-ID: <363ddfb6d06a14366d523c70d4f890f974e7cb80.1331816340.git.nicolas.ferre@atmel.com>

The AT91SAM9G45 entry covers the whole family so we also add the AT91SAM9M10
name and the "families" qualifier. Then, add a comment to explain which SoCs
are supported by this entry: AT91SAM9G45, AT91SAM9G46 but also
AT91SAM9M10 and AT91SAM9M11.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/Kconfig |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index e55cdcb..5f0fe11 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -93,7 +93,7 @@ config ARCH_AT91SAM9G20
 	select AT91_SAM9_ALT_RESET
 
 config ARCH_AT91SAM9G45
-	bool "AT91SAM9G45"
+	bool "AT91SAM9G45 or AT91SAM9M10 families"
 	select CPU_ARM926T
 	select GENERIC_CLOCKEVENTS
 	select HAVE_AT91_USART3
@@ -101,6 +101,9 @@ config ARCH_AT91SAM9G45
 	select HAVE_NET_MACB
 	select HAVE_AT91_DBGU1
 	select AT91_SAM9G45_RESET
+	help
+	  Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
+	  This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
 
 config ARCH_AT91SAM9X5
 	bool "AT91SAM9x5 family"
-- 
1.7.9



From nicolas.ferre at atmel.com  Thu Mar 15 09:00:12 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 14:00:12 +0100
Subject: [PATCH 4/6] ARM: at91/Kconfig: add clarifications to
 AT91SAM9M10G45-EK entry
In-Reply-To: <feb3f4c639fae3f01636ba2017968fac1078ddca.1331816340.git.nicolas.ferre@atmel.com>
References: <feb3f4c639fae3f01636ba2017968fac1078ddca.1331816340.git.nicolas.ferre@atmel.com>
Message-ID: <b32b4c16c5997f0df32300e5eb1762caf9c40e88.1331816340.git.nicolas.ferre@atmel.com>

Add clarifications about the SoCs that can be found on an AT91SAM9M10G45-EK
board. Add also the web link to this board on Atmel's website.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/Kconfig |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 4a896c6..6e02b58 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -448,9 +448,10 @@ comment "AT91SAM9G45 Board Type"
 config MACH_AT91SAM9M10G45EK
 	bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
 	help
-	  Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
-	  "ES" at the end of the name means that this board is an
-	  Engineering Sample.
+	  Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
+	  Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
+	  families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
+	  <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
 
 endif
 
-- 
1.7.9



From nicolas.ferre at atmel.com  Thu Mar 15 09:00:14 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 14:00:14 +0100
Subject: [PATCH 6/6] ARM: at91/Kconfig: website link for AT91SAM9G20-EK
In-Reply-To: <feb3f4c639fae3f01636ba2017968fac1078ddca.1331816340.git.nicolas.ferre@atmel.com>
References: <feb3f4c639fae3f01636ba2017968fac1078ddca.1331816340.git.nicolas.ferre@atmel.com>
Message-ID: <02d9058446476af7961360b126768339ba4f6b7f.1331816340.git.nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 24da4cc..79e69bf 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -379,6 +379,7 @@ config MACH_AT91SAM9G20EK_2MMC
 	  Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
 	  with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
 	  onwards.
+	  <http://www.atmel.com/tools/SAM9G20-EK.aspx>
 
 config MACH_CPU9G20
 	bool "Eukrea CPU9G20 board"
-- 
1.7.9



From shawn.guo at linaro.org  Thu Mar 15 09:02:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 15 Mar 2012 21:02:58 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F612319.50302@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
Message-ID: <20120315130253.GA6065@S2101-09.ap.freescale.net>

On Wed, Mar 14, 2012 at 06:00:41PM -0500, Timur Tabi wrote:
> Mark Brown wrote:
> 
> > All of which is exactly the same as for any other device and essentially
> > irrelevant to how we define the bindings for the cards.
> 
> So using imx-audio-sgtl5000.txt as an example, you're saying that if I
> have two SSIs, I should do this in my device tree:
> 
> sound1 {
> 	compatible = "fsl,imx51-babbage-sgtl5000",
> 		     "fsl,imx-audio-sgtl5000";
> 	model = "imx51-babbage-sgtl5000";
> 	ssi-controller = <&ssi1>;
> 	audio-codec = <&sgtl5000_1>;
> 	mux-int-port = <1>;
> 	mux-ext-port = <3>;
> };
> 
> sound2 {
> 	compatible = "fsl,imx51-babbage-sgtl5000",
> 		     "fsl,imx-audio-sgtl5000";
> 	model = "imx51-babbage-sgtl5000";
> 	ssi-controller = <&ssi2>;
> 	audio-codec = <&sgtl5000_2>;
> 	mux-int-port = <1>;
> 	mux-ext-port = <3>;
> };
> 
Are you putting an example that has two sgtl5000 codecs connected to
SSI1 and SSI2 on a particular board?

I have never seen a real case for such setup.  Have you actually seen?
I do not even see the need to use two SSI controllers for all imx
platforms I have seen.

The real case I have seen is imx28 saif driver, which has to use two
saif controllers connected to one sgtl5000 to support full-duplex.
I would expect something like below for that machine driver.

sound2 {
	compatible = "fsl,imx28-evk-sgtl5000",
		     "fsl,mxs-audio-sgtl5000";
	model = "imx28-evk-sgtl5000";
	saif-controller = <&saif1, &saif2>;
};

We can have that controller property be a phandle array in the binding.

> >>> The biggest improvement is that the SoC binding knows nothing about the
> >>> card binding at all, cards are completely separate and are free to
> >>> define any binding they choose using any number of on-SoC and off-SoC
> >>> devices.
> > 
> >> Ok, I don't understand that at all.
> > 
> > Do you have some questions about the above?  What is it that you find
> > unclear?   
> 
> What's the difference between an "SoC binding" and a "card binding"?
> 
I guess "SoC binding" means the binding for fsl_ssi while "card
binding" means the binding for imx-sgtl5000 in this particular case.

> > We've been through this *repeatedly*, including in the message you're
> > replying to, and we're still going back to square one every time you
> > decide to start talking about device tree again.  This is frustrating
> > in the extreme.
> 
> I'm sorry you're frustrated, but so am I.

And, so am I :(

I thought you have agreed that we can go for new binding for imx
machine drivers per the discussion you and Mark had on the first
version of the series.  That's why I changed to use the new binding
in v2, and you even had given your ack tag on v2.  Now you are
suddenly against that so strongly.  I really do not understand why.
Can you share your concern regarding to that?  What's the problem
with imx using new binding exactly?

> I still don't understand why
> the binding that I invented for the SSI driver isn't good enough for i.MX.

I guess Mark had made it clear that having "codec-handle" encoded in
ssi node is not as good as what new binding does, having it encoded
in "audio complex" node.

>  The binding and the code was documented and approved a long time ago.
> Why can't we keep the same binding on i.MX,
> to keep the code simpler?

I hardly agree with that.  The PowerPC binding will require:

1. fsl_ssi's probe function needs to trigger machine driver's probe
2. machine driver needs to find ssi's node to access codec-handle

which actually makes it complexer than the new binding.

Anyway, either way works, and I have tried both.  But unfortunately
I still have not made everyone happy.  Are we going to make the series
miss the v3.4 merge window just because of this argument, which does
not make much point to me at all.

-- 
Regards,
Shawn


From B04825 at freescale.com  Thu Mar 15 09:37:06 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Thu, 15 Mar 2012 13:37:06 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120315130253.GA6065@S2101-09.ap.freescale.net>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315130253.GA6065@S2101-09.ap.freescale.net>
Message-ID: <4F61F080.4090800@freescale.com>

Shawn Guo wrote:

> Are you putting an example that has two sgtl5000 codecs connected to
> SSI1 and SSI2 on a particular board?

No, this is just a theoretical example.

> I have never seen a real case for such setup.  Have you actually seen?
> I do not even see the need to use two SSI controllers for all imx
> platforms I have seen.

The PowerPC MPC8610 has two SSIs, and I have a hacked up board that has 
both connected to two CS4270s.  This is how I tested multiple SSI support 
in my driver.

Since my driver supports any number of SSIs, I expect any changes to it to 
continue that support.

> The real case I have seen is imx28 saif driver, which has to use two
> saif controllers connected to one sgtl5000 to support full-duplex.
> I would expect something like below for that machine driver.
>
> sound2 {
> 	compatible = "fsl,imx28-evk-sgtl5000",
> 		     "fsl,mxs-audio-sgtl5000";
> 	model = "imx28-evk-sgtl5000";
> 	saif-controller =<&saif1,&saif2>;
> };
>
> We can have that controller property be a phandle array in the binding.

I can see how this style of binding would make it easier to support an 
N-to-M mapping of controllers to codecs.  However, this is not a concern 
for the SSI driver.

> I thought you have agreed that we can go for new binding for imx
> machine drivers per the discussion you and Mark had on the first
> version of the series.  That's why I changed to use the new binding
> in v2, and you even had given your ack tag on v2.  Now you are
> suddenly against that so strongly.  I really do not understand why.
> Can you share your concern regarding to that?  What's the problem
> with imx using new binding exactly?

I admit I may have been too hasty in giving that ACK, because I did not 
take the time to study the binding.  I figured that the new binding was 
superior to what I came up with years ago.

Now that I've studied the binding, I no longer believe that.  I don't 
understand what's so wonderful about the new binding that my driver has to 
support it *and* the old binding.  I think it would be easier if i.MX uses 
the original binding.

>> I still don't understand why
>> the binding that I invented for the SSI driver isn't good enough for i.MX.
>
> I guess Mark had made it clear that having "codec-handle" encoded in
> ssi node is not as good as what new binding does, having it encoded
> in "audio complex" node.

Even if the new binding is "better", I do not see how it's SOOOOO much 
better that my driver has to support it.  The drawback in supporting both 
is the added complexity.

>> Why can't we keep the same binding on i.MX,
>> to keep the code simpler?
>
> I hardly agree with that.  The PowerPC binding will require:
>
> 1. fsl_ssi's probe function needs to trigger machine driver's probe
> 2. machine driver needs to find ssi's node to access codec-handle
>
> which actually makes it complexer than the new binding.

But the driver already does this!  No one's asking you to add the code to 
perform these tasks.  Just use the existing code.

> Anyway, either way works, and I have tried both.  But unfortunately
> I still have not made everyone happy.  Are we going to make the series
> miss the v3.4 merge window just because of this argument, which does
> not make much point to me at all.

I can respect that concern, but at the same time, I still have to push for 
what I believe makes the most sense.

-- 
Timur Tabi
Linux kernel developer at Freescale


From arnd at arndb.de  Thu Mar 15 09:39:36 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 13:39:36 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203151138.51508.sr@denx.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <4F61AFAB.6080301@st.com> <201203151138.51508.sr@denx.de>
Message-ID: <201203151339.36173.arnd@arndb.de>

On Thursday 15 March 2012, Stefan Roese wrote:
> On Thursday 15 March 2012 10:00:27 Viresh Kumar wrote:
> > On 3/15/2012 2:18 PM, Stefan Roese wrote:
> > >>> > > +static const struct of_device_id vic_of_match[] __initconst = {
> > >>> > > +     { .compatible = "arm,pl190-vic", .data = vic_of_init, },
> > >>> > > +     { /* Sentinel */ }
> > >>> > > +};
> > >>> > > +
> > >>> > > +static void __init spear6xx_dt_init_irq(void)
> > >>> > > +{
> > >>> > > +     of_irq_init(vic_of_match);
> > >>> > > +}
> > >>> > > +
> > >> > 
> > >> > What about adding this routine in vic.c file, which can then be used
> > >> > by all platforms, instead of replicating this code.
> > > 
> > > We can't move vic_of_match to the vic.c, since there are differences
> > > between the boards using it. And only moving spear6xx_dt_init_irq()
> > > (renamed of course) doesn't seem worth it.
> > 
> > I knew this. Actually my thought was, we have two compatible strings for
> > vic: pl190 and pl192.
> > 
> > So, create two vic_of_match* arrays and two vic*_dt_init_irq() routines.
> > That will solve the issue i believe.
> 
> I still don't think its worth it. But please feel free to send an add-on 
> patch, to "clean this up".

What's wrong with one vic_dt_init_irq() function and an array with two entries?

	Arnd


From omaplinuxkernel at gmail.com  Thu Mar 15 09:40:42 2012
From: omaplinuxkernel at gmail.com (Shubhrajyoti Datta)
Date: Thu, 15 Mar 2012 19:10:42 +0530
Subject: [PATCH v3 6/6] mfd: mc13xxx: Add i2c driver
In-Reply-To: <1331757790-10583-7-git-send-email-marc@cpdesign.com.au>
References: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
 <1331757790-10583-7-git-send-email-marc@cpdesign.com.au>
Message-ID: <CAM=Q2cssNF2TSWHjcbG4wsABBXhquYoKq_scC6bDcq8kdoosyQ@mail.gmail.com>

Hi Marc,

On Thu, Mar 15, 2012 at 2:13 AM, Marc Reilly <marc at cpdesign.com.au> wrote:
> Adds support for mc13xxx family ICs connected via i2c.
>
> Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
> ---
<snip>

> +static int mc13xxx_i2c_probe(struct i2c_client *client,
> + ? ? ? ? ? ? ? const struct i2c_device_id *id)
> +{
> + ? ? ? const struct of_device_id *of_id;
> + ? ? ? struct i2c_driver *idrv = to_i2c_driver(client->dev.driver);
> + ? ? ? struct mc13xxx *mc13xxx;
> + ? ? ? struct mc13xxx_platform_data *pdata = dev_get_platdata(&client->dev);
> + ? ? ? int ret;
> +
> + ? ? ? of_id = of_match_device(mc13xxx_dt_ids, &client->dev);
> + ? ? ? if (of_id)
> + ? ? ? ? ? ? ? idrv->id_table =
> + ? ? ? ? ? ? ? ? ? ? ? &mc13xxx_i2c_device_id[(enum mc13xxx_id) of_id->data];
> +
> + ? ? ? mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
> + ? ? ? if (!mc13xxx)
> + ? ? ? ? ? ? ? return -ENOMEM;
> +
> + ? ? ? dev_set_drvdata(&client->dev, mc13xxx);
> +
> + ? ? ? mc13xxx->dev = &client->dev;
> + ? ? ? mutex_init(&mc13xxx->lock);
> +
> + ? ? ? mc13xxx->regmap = regmap_init_i2c(client, &mc13xxx_regmap_i2c_config);
> + ? ? ? if (IS_ERR(mc13xxx->regmap)) {
> + ? ? ? ? ? ? ? ret = PTR_ERR(mc13xxx->regmap);
> + ? ? ? ? ? ? ? dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ret);
> + ? ? ? ? ? ? ? dev_set_drvdata(&client->dev, NULL);
Are we  leaking mc13xxx here
May be you can consider using devm* functions ?

>  + ? ? ? ? ? ? ? return ret;
> + ? ? ? }
> +


From arnd at arndb.de  Thu Mar 15 09:47:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 13:47:11 +0000
Subject: [PATCH -next] ARM: ux500: fix compilation after local timer rework
In-Reply-To: <1331812046-21062-1-git-send-email-marc.zyngier@arm.com>
References: <1331812046-21062-1-git-send-email-marc.zyngier@arm.com>
Message-ID: <201203151347.11511.arnd@arndb.de>

On Thursday 15 March 2012, Marc Zyngier wrote:
> mach-ux500/timer.c lacked the inclusion of mach/irqs.h, and thus
> failed to compile. Fix it and also remove an unused variable.
> 
> Test compiled only.
> 
> Reported-by: Lee Jones <lee.jones at linaro.org>
> Cc: Arnd Bergman <arnd at arndb.de>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Signed-off-by: Marc Zyngier <marc.zyngier at arm.com>
> ---
> Arnd,
> 
> I've pushed this patch to my local_timers-for-arm-soc. If you can pull
> it one more time, that would be great.

Thanks for the quick update, pulled into next/timers now.

	Arnd


From arnd at arndb.de  Thu Mar 15 09:50:59 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 13:50:59 +0000
Subject: [GIT PULL] i.MX25 iomux fix
In-Reply-To: <20120313133610.GH3852@pengutronix.de>
References: <20120313133610.GH3852@pengutronix.de>
Message-ID: <201203151350.59689.arnd@arndb.de>

On Tuesday 13 March 2012, Sascha Hauer wrote:
> Hi Arnd, Olof,
> 
> Please pull the following (non urgent, for next) fix for the i.MX25
> iomux.
> 

Pulled into fixes-non-critical, thanks!

	Arnd


From kgene.kim at samsung.com  Thu Mar 15 10:17:49 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 15 Mar 2012 07:17:49 -0700
Subject: [GIT PULL] Samsung SoC EXYNOS5250 arch for v3.4
Message-ID: <4F61FA0D.1050007@samsung.com>

Hi Arnd, Olof,

Thank you for kindly review for EXYNOS5 and addressed comments.

Here are 'pull request' for supporting EXYNOS5250.

Please pull from:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/soc-exynos5250-arch

It is based on next/devel-samsung-dma which has been pulled into arm-soc 
to avoid merge conflicts, because they touches same files.
And it is including additional two commits, one commit for fix 
exynos4-dt build error which is caused by this series and one for 
supporting lcd clkdev.

If any problems, please kindly let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit efd9960b0e1bdfe48490504a8166ffdbcc466dba:

   ARM: EXYNOS: add support DMA for EXYNOS4X12 SoC (2012-03-10 22:51:20 
-0800)

are available in the git repository at:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/soc-exynos5250-arch

Eunki Kim (1):
       ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5

Kukjin Kim (11):
       ARM: EXYNOS: to declare static for mach-exynos/common.c
       ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts()
       ARM: EXYNOS: add clock part for EXYNOS5250 SoC
       ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
       ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
       ARM: EXYNOS: add support for EXYNOS5250 SoC
       ARM: EXYNOS: add interrupt definitions for EXYNOS5250
       ARM: EXYNOS: add support get_core_count() for EXYNOS5250
       ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5 SoCs
       ARM: EXYNOS: add support device tree enabled board file for EXYNOS5
       ARM: dts: add initial dts file for EXYNOS5250, SMDK5250

Tushar Behera (2):
       ARM: EXYNOS: Add clkdev lookup entry for lcd clock
       ARM: EXYNOS: Fix compilation error with mach-exynos4-dt board

  arch/arm/Makefile                               |    1 +
  arch/arm/boot/dts/exynos5250-smdk5250.dts       |   26 +
  arch/arm/boot/dts/exynos5250.dtsi               |  413 ++++++++
  arch/arm/mach-exynos/Kconfig                    |   29 +-
  arch/arm/mach-exynos/Makefile                   |    5 +-
  arch/arm/mach-exynos/clock-exynos4.c            |   14 +-
  arch/arm/mach-exynos/clock-exynos5.c            | 1247 
+++++++++++++++++++++++
  arch/arm/mach-exynos/common.c                   |  449 +++++++--
  arch/arm/mach-exynos/common.h                   |   37 +-
  arch/arm/mach-exynos/dev-ahci.c                 |    4 +-
  arch/arm/mach-exynos/dev-audio.c                |    4 +-
  arch/arm/mach-exynos/dev-uart.c                 |   78 ++
  arch/arm/mach-exynos/dma.c                      |    6 +-
  arch/arm/mach-exynos/include/mach/debug-macro.S |    9 +-
  arch/arm/mach-exynos/include/mach/irqs.h        |  597 ++++++++---
  arch/arm/mach-exynos/include/mach/map.h         |   41 +-
  arch/arm/mach-exynos/include/mach/regs-clock.h  |   62 ++
  arch/arm/mach-exynos/include/mach/regs-gpio.h   |   20 +-
  arch/arm/mach-exynos/include/mach/regs-pmu.h    |    1 +
  arch/arm/mach-exynos/include/mach/uncompress.h  |   17 +-
  arch/arm/mach-exynos/mach-exynos4-dt.c          |    8 +-
  arch/arm/mach-exynos/mach-exynos5-dt.c          |   78 ++
  arch/arm/mach-exynos/mct.c                      |   23 +-
  arch/arm/mach-exynos/platsmp.c                  |    9 +-
  arch/arm/mach-exynos/setup-i2c0.c               |    9 +-
  arch/arm/plat-s5p/Kconfig                       |    8 +-
  arch/arm/plat-s5p/Makefile                      |    3 +-
  arch/arm/plat-s5p/clock.c                       |   36 +
  arch/arm/plat-s5p/irq-pm.c                      |   25 +-
  arch/arm/plat-samsung/include/plat/cpu.h        |   10 +
  arch/arm/plat-samsung/include/plat/devs.h       |    2 +
  arch/arm/plat-samsung/include/plat/s5p-clock.h  |    6 +
  arch/arm/plat-samsung/include/plat/uncompress.h |    2 +
  arch/arm/plat-samsung/irq-vic-timer.c           |   16 +
  34 files changed, 2954 insertions(+), 341 deletions(-)
  create mode 100644 arch/arm/boot/dts/exynos5250-smdk5250.dts
  create mode 100644 arch/arm/boot/dts/exynos5250.dtsi
  create mode 100644 arch/arm/mach-exynos/clock-exynos5.c
  create mode 100644 arch/arm/mach-exynos/dev-uart.c
  create mode 100644 arch/arm/mach-exynos/mach-exynos5-dt.c


From shawn.guo at linaro.org  Thu Mar 15 10:21:18 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 15 Mar 2012 22:21:18 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F61F080.4090800@freescale.com>
References: <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315130253.GA6065@S2101-09.ap.freescale.net>
 <4F61F080.4090800@freescale.com>
Message-ID: <20120315142115.GB6065@S2101-09.ap.freescale.net>

On Thu, Mar 15, 2012 at 01:37:06PM +0000, Tabi Timur-B04825 wrote:
...
> The PowerPC MPC8610 has two SSIs, and I have a hacked up board that has 
> both connected to two CS4270s.  This is how I tested multiple SSI support 
> in my driver.
> 
> Since my driver supports any number of SSIs, I expect any changes to it to 
> continue that support.
> 
I think it can still easily get supported with the binding like below.

sound {
      compatible = "fsl,imx51-babbage-sgtl5000",
                   "fsl,imx-audio-sgtl5000";
      model = "imx51-babbage-sgtl5000";
      ssi-controller = <&ssi1, &ssi2>;
      audio-codec = <&sgtl5000_1, &sgtl5000_2>;
      mux-int-port = <1>;
      mux-ext-port = <3>;
};

The only difference will be both ssi-controller and audio-codec become
an array of phandles.

...
> I admit I may have been too hasty in giving that ACK, because I did not 
> take the time to study the binding.  I figured that the new binding was 
> superior to what I came up with years ago.
> 
> Now that I've studied the binding, I no longer believe that.  I don't 
> understand what's so wonderful about the new binding that my driver has to 
> support it *and* the old binding.  I think it would be easier if i.MX uses 
> the original binding.
> 
I do not think it would be easier for imx.  Looking at the imx-sgtl5000
binding, you will find we have audmux port configuration encoded there.
How would you suggest to get that fit into the PowerPC binding?

...
> Even if the new binding is "better", I do not see how it's SOOOOO much 
> better that my driver has to support it.  The drawback in supporting both 
> is the added complexity.

If you insist on that the driver should only support single binding,
I would rather change mpc8610_hpcd and p1022_ds to use the new binding.

...
> But the driver already does this!  No one's asking you to add the code to 
> perform these tasks.  Just use the existing code.

Again, what's your suggestion to support audmux configuration with the
existing binding?

-- 
Regards,
Shawn


From grant.likely at secretlab.ca  Thu Mar 15 05:54:54 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 15 Mar 2012 03:54:54 -0600
Subject: [PATCH v4] of: introduce helper to manage boolean
In-Reply-To: <1331660903-10193-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331660903-10193-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <20120315095454.9294E3E08CB@localhost>

On Tue, 13 Mar 2012 18:48:23 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> of_property_read_bool
> 
> Search for a property in a device node.
> Returns true if the property exist false otherwise.
> 
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Acked-by: Rob Herring <rob.herring at calxeda.com>
> Acked-by: Arnd Bergmann <arnd at arndb.de>

One comment below; but otherwise:

Acked-by: Grant Likely <grant.likely at secretlab.ca>

Feel free to merge via whatever tree needs it.

g.

> Cc: Grant Likely <grant.likely at secretlab.ca>
> ---
> v4:
> 
> 	send the right version
> 
> 	include Grant comment
> 
> 	Grant can I get the go please?
> 
> Best Regards,
> J.
>  include/linux/of.h |   16 ++++++++++++++++
>  1 files changed, 16 insertions(+), 0 deletions(-)
> 
> diff --git a/include/linux/of.h b/include/linux/of.h
> index a75a831..a992cdf 100644
> --- a/include/linux/of.h
> +++ b/include/linux/of.h
> @@ -342,6 +342,22 @@ static inline int of_machine_is_compatible(const char *compat)
>  #define of_match_node(_matches, _node)	NULL
>  #endif /* CONFIG_OF */
>  
> +/**
> + * of_property_read_bool - Findfrom a property
> + * @np:		device node from which the property value is to be read.
> + * @propname:	name of the property to be searched.
> + *
> + * Search for a property in a device node.
> + * Returns true if the property exist false otherwise.
> + */
> +static inline bool of_property_read_bool(const struct device_node *np,
> +					 const char *propname)
> +{
> +	struct property *prop = of_find_property(np, propname, NULL);
> +
> +	return prop ? true : false;
> +}

Could simply be:
{
	return of_find_property(...) != NULL;
}


> +
>  static inline int of_property_read_u32(const struct device_node *np,
>  				       const char *propname,
>  				       u32 *out_value)
> -- 
> 1.7.7
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From kgene.kim at samsung.com  Thu Mar 15 10:25:20 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 15 Mar 2012 07:25:20 -0700
Subject: [GIT PULL] Samsung EXYNOS5250 GPIO for v3.4
Message-ID: <4F61FBD0.4040904@samsung.com>

Hi Arnd, Olof,

Please pull EXYNOS5250 gpio for v3.4.

   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/soc-exynos5250-gpio

It is including add support GPIOlib for EXYNOS5250 and Grant Likely 
already agreed to send this via arm-soc for v3.4. Actually, this is 
needed for compilation of EXYNOS5250 arch. As a note, this has no 
dependency with others for merging.

If any problems, please let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:

   Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)

are available in the git repository at:
   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
next/soc-exynos5250-gpio

Sangsu Park (3):
       ARM: EXYNOS: add support GPIO for EXYNOS5250
       gpio/samsung: add support GPIOlib for EXYNOS5250
       gpio/samsung: use ioremap() for EXYNOS4 GPIOlib

  arch/arm/mach-exynos/common.c            |   15 -
  arch/arm/mach-exynos/include/mach/gpio.h |  239 ++++++++++++---
  arch/arm/mach-exynos/include/mach/map.h  |    4 +
  drivers/gpio/gpio-samsung.c              |  487 
+++++++++++++++++++++++++++---
  4 files changed, 637 insertions(+), 108 deletions(-)


From khilman at ti.com  Thu Mar 15 10:25:43 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 15 Mar 2012 07:25:43 -0700
Subject: [GIT PULL] cpufreq: OMAP updates for v3.4
In-Reply-To: <CANOLnON+hHtnjo9samAqvXp_nVJMjQ7CnxMCe7ggO4UwYaz4rw@mail.gmail.com>
 (Grazvydas Ignotas's message of "Wed, 14 Mar 2012 19:38:38 +0200")
References: <87y5rci2na.fsf@ti.com>
 <CANOLnON91vXWb2L-FXjz3sqq-9j5SaEodtpt_yvFiN33D4Q3Ow@mail.gmail.com>
 <87wr6ngkrl.fsf@ti.com>
 <CANOLnON+hHtnjo9samAqvXp_nVJMjQ7CnxMCe7ggO4UwYaz4rw@mail.gmail.com>
Message-ID: <87obryc55k.fsf@ti.com>

Grazvydas Ignotas <notasas at gmail.com> writes:

> On Wed, Mar 14, 2012 at 7:22 PM, Kevin Hilman <khilman at ti.com> wrote:
>> Grazvydas Ignotas <notasas at gmail.com> writes:
>>
>> [...]
>>
>>>> Russell King (1):
>>>> ? ? ?cpufreq: OMAP driver depends CPUfreq tables
>>>
>>> It seems this one got messed up, it says "default ARCH_OMAP2PLUS"
>>> instead of depends.
>>
>> That was intentional. ?What do you think is messed up about it?
>>
>> It's the same as saying:
>>
>> ? ? depends on ARCH_OMAP2PLUS
>> ? ? default y
>
> Hm, somehow I've never encountered this syntax, but it more looks like
> it means "default y if ARCH_OMAP2PLUS" instead of that.
>
> Checked this with menuconfig now:
>   default ARCH_OMAP2PLUS
> resolves to:
>   ARCH_HAS_CPUFREQ [=y] && CPU_FREQ [=y] && ARM [=y]
>
> ..which might cause build break when OMAP is not selected, and
>
>   depends on ARCH_OMAP2PLUS
>   default y
> resolves to:
>   ARCH_HAS_CPUFREQ [=y] && CPU_FREQ [=y] && ARM [=y] && ARCH_OMAP2PLUS [=y]
>
> ..which should be randconfig friendly.

Yeah, you're right.  Feel free to send a patch using your comments above
to describe that the current form is not randconfig friendly.

Kevin


From broonie at opensource.wolfsonmicro.com  Thu Mar 15 10:27:03 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 15 Mar 2012 14:27:03 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F612319.50302@freescale.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
Message-ID: <20120315142702.GL3138@opensource.wolfsonmicro.com>

On Wed, Mar 14, 2012 at 06:00:41PM -0500, Timur Tabi wrote:
> Mark Brown wrote:

> So using imx-audio-sgtl5000.txt as an example, you're saying that if I
> have two SSIs, I should do this in my device tree:

> sound1 {
> };

> sound2 {
> };

That's a totally sensible option if you've got two unrelated audio
subsystems on your board for some reason.  If you've got a system where
that's not applicable and the two devices are related in some way then
you'd define a new sound card binding that reflects that.

> >>> The biggest improvement is that the SoC binding knows nothing about the
> >>> card binding at all, cards are completely separate and are free to
> >>> define any binding they choose using any number of on-SoC and off-SoC
> >>> devices.

> >> Ok, I don't understand that at all.

> > Do you have some questions about the above?  What is it that you find
> > unclear?   

> What's the difference between an "SoC binding" and a "card binding"?

The SoC is the bit of silicon with the CPU and other devices on it like
the DMA controller and SSI or whatever ports.  The card is the PCB this
has been soldered down onto.

> > We've been through this *repeatedly*, including in the message you're
> > replying to, and we're still going back to square one every time you
> > decide to start talking about device tree again.  This is frustrating
> > in the extreme.

> I'm sorry you're frustrated, but so am I.  I still don't understand why
> the binding that I invented for the SSI driver isn't good enough for i.MX.
>  The binding and the code was documented and approved a long time ago.
> Why can't we keep the same binding on i.MX, to keep the code simpler?

The problem with your binding has always been, and continues to be, that
it's based on the idea that there's one CODEC per SSI and that the CODEC
is a simple appendage of that SSI.  There's no real real binding for the
machine driver, it's just silently created by a single SSI port.  Really
there's nothing new with this issue, there's always been this absence of
a representation for the machine distinct from the individual devices it
is built up from.

This means that when you get systems which have auxiliary devices (like
most of the Wolfson reference boards which have a power amplifier for
the sub speaker not connected to an SSI port) or that need to set up
things like complex accessory detection mechanisms there's no real place
in your binding to support those systems.  Things like the configuration
of the input and output connections which the nVidia WM8903 drivers are
able to do over multiple boards are another example.
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From plagnioj at jcrosoft.com  Thu Mar 15 10:18:43 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 15 Mar 2012 15:18:43 +0100
Subject: [PATCH v4] of: introduce helper to manage boolean
In-Reply-To: <20120315095454.9294E3E08CB@localhost>
References: <1331660903-10193-1-git-send-email-plagnioj@jcrosoft.com>
 <20120315095454.9294E3E08CB@localhost>
Message-ID: <20120315141843.GQ18320@game.jcrosoft.org>

On 03:54 Thu 15 Mar     , Grant Likely wrote:
> On Tue, 13 Mar 2012 18:48:23 +0100, Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com> wrote:
> > of_property_read_bool
> > 
> > Search for a property in a device node.
> > Returns true if the property exist false otherwise.
> > 
> > Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > Acked-by: Rob Herring <rob.herring at calxeda.com>
> > Acked-by: Arnd Bergmann <arnd at arndb.de>
> 
> One comment below; but otherwise:
> 
> Acked-by: Grant Likely <grant.likely at secretlab.ca>
> 
> Feel free to merge via whatever tree needs it.
> 
> g.
> 
> > Cc: Grant Likely <grant.likely at secretlab.ca>
> > ---
> > v4:
> > 
> > 	send the right version
> > 
> > 	include Grant comment
> > 
> > 	Grant can I get the go please?
> > 
> > Best Regards,
> > J.
> >  include/linux/of.h |   16 ++++++++++++++++
> >  1 files changed, 16 insertions(+), 0 deletions(-)
> > 
> > diff --git a/include/linux/of.h b/include/linux/of.h
> > index a75a831..a992cdf 100644
> > --- a/include/linux/of.h
> > +++ b/include/linux/of.h
> > @@ -342,6 +342,22 @@ static inline int of_machine_is_compatible(const char *compat)
> >  #define of_match_node(_matches, _node)	NULL
> >  #endif /* CONFIG_OF */
> >  
> > +/**
> > + * of_property_read_bool - Findfrom a property
> > + * @np:		device node from which the property value is to be read.
> > + * @propname:	name of the property to be searched.
> > + *
> > + * Search for a property in a device node.
> > + * Returns true if the property exist false otherwise.
> > + */
> > +static inline bool of_property_read_bool(const struct device_node *np,
> > +					 const char *propname)
> > +{
> > +	struct property *prop = of_find_property(np, propname, NULL);
> > +
> > +	return prop ? true : false;
> > +}
> 
> Could simply be:
> {
> 	return of_find_property(...) != NULL;
ok fine no preference sned the pull to Arnd with the reset of the DT for at91

please check the USB too I gusee they can go too  but maybe  for the atmel
high-speed device you will have some comment

Best Regards,
J.


From lee.jones at linaro.org  Thu Mar 15 10:31:35 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 15 Mar 2012 14:31:35 +0000
Subject: [PATCH v4 09/15] ARM: ux500: convert to twd_local_timer_register()
 interface
In-Reply-To: <4F61D6CA.8060002@arm.com>
References: <1327061042-14857-1-git-send-email-marc.zyngier@arm.com>
 <1327061042-14857-10-git-send-email-marc.zyngier@arm.com>
 <CANmRt2gjhg-nznAOxQHA1g7EX+F4uEjp1nW5iT3Rtw4s8y5uGg@mail.gmail.com>
 <4F60D7DD.50705@linaro.org> <4F61D6CA.8060002@arm.com>
Message-ID: <4F61FD47.4030603@linaro.org>

On 15/03/12 11:47, Marc Zyngier wrote:
> On 14/03/12 17:39, Lee Jones wrote:
> 
>> NAK: Won't build. :(
> 
> Thanks for noticing this.
> 
> I've just pushed a fix to local_timers-for-arm-soc, and the patch should
> be on the ML shortly.

I have tested it. Works okay.

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From shawn.guo at linaro.org  Thu Mar 15 10:34:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 15 Mar 2012 22:34:49 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120315142702.GL3138@opensource.wolfsonmicro.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
Message-ID: <20120315143446.GC6065@S2101-09.ap.freescale.net>

On Thu, Mar 15, 2012 at 02:27:03PM +0000, Mark Brown wrote:
> On Wed, Mar 14, 2012 at 06:00:41PM -0500, Timur Tabi wrote:
...
> > I'm sorry you're frustrated, but so am I.  I still don't understand why
> > the binding that I invented for the SSI driver isn't good enough for i.MX.
> >  The binding and the code was documented and approved a long time ago.
> > Why can't we keep the same binding on i.MX, to keep the code simpler?
> 
> The problem with your binding has always been, and continues to be, that
> it's based on the idea that there's one CODEC per SSI and that the CODEC
> is a simple appendage of that SSI.  There's no real real binding for the
> machine driver, it's just silently created by a single SSI port.  Really
> there's nothing new with this issue, there's always been this absence of
> a representation for the machine distinct from the individual devices it
> is built up from.
> 
> This means that when you get systems which have auxiliary devices (like
> most of the Wolfson reference boards which have a power amplifier for
> the sub speaker not connected to an SSI port) or that need to set up
> things like complex accessory detection mechanisms there's no real place
> in your binding to support those systems.  Things like the configuration
> of the input and output connections which the nVidia WM8903 drivers are
> able to do over multiple boards are another example.

Yes, we will have the exactly same thing for imx-sgtl5000 to be added
later.  The current imx-sgtl5000 driver just an initial support.

-- 
Regards,
Shawn


From linus.walleij at linaro.org  Thu Mar 15 10:38:19 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 15 Mar 2012 15:38:19 +0100
Subject: [PATCH 01/10] ARM: ux500: CONFIG: Enable Device Tree support for
 future endeavours
In-Reply-To: <1331730306-11461-2-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-2-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdas8K3Xeau90OskwjD2NwUdxCO3Ft4xKMaSCzpcEF52eQ@mail.gmail.com>

On Wed, Mar 14, 2012 at 2:04 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Thu Mar 15 10:39:02 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 15 Mar 2012 15:39:02 +0100
Subject: [PATCH 02/10] ARM: ux500: Initial Device Tree support for Snowball
In-Reply-To: <201203141456.40135.arnd@arndb.de>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <201203141358.03541.arnd@arndb.de> <4F60AD39.6020009@linaro.org>
 <201203141456.40135.arnd@arndb.de>
Message-ID: <CACRpkdZj0BGuhJ8W5mNusEbqbJSk-4XB+Rqz-JjXq_iqQBaqMA@mail.gmail.com>

On Wed, Mar 14, 2012 at 3:56 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> On Wednesday 14 March 2012, Lee Jones wrote:
>> Sorry I missed that.
>>
>> Just for my clarification, how important is that?
>>
>> Is it re-spin a patch-set important?
>>
> No need to send the patches out by email for this, but
> please fix it up for the pull request.

Add this:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From kgene.kim at samsung.com  Thu Mar 15 10:39:25 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 15 Mar 2012 07:39:25 -0700
Subject: [PATCH v12 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
In-Reply-To: <20120315111227.GA2384@amd.com>
References: <000201cd0286$2e6fbb40$8b4f31c0$%cho@samsung.com>
 <20120315111227.GA2384@amd.com>
Message-ID: <4F61FF1D.5000502@samsung.com>

On 03/15/12 04:12, Joerg Roedel wrote:
> On Thu, Mar 15, 2012 at 05:32:39PM +0900, Cho KyongHo wrote:

KyongHo, I looked at 'Cho KyongHo <pullip.cho ...>' and 'KyongHo Cho 
<pullip.cho ...>' in this series, which one do you want to use?

>> Handling System MMUs with an identifier is not flexible to manage
>> System MMU platform devices because of the following reasons:
>> 1. A device driver which needs to handle System MMU must know the ID.
>> 2. A System MMU may not present in some implementations of Exynos family.
>> 3. Handling System MMU with IOMMU API does not require an ID.
>>
>> This patch is the result of removing ID of System MMUs.
>> Instead, a device driver that needs to handle its System MMU must
>> use IOMMU API while its descriptor of platform device is given.
>>
>> This patch also includes the following enhancements:
>> - A System MMU device becomes a child if its power domain device.
>> - clkdev
>>
>> Cc: Kukjin Kim<kgene.kim at samsung.com>
>> Signed-off-by: KyongHo Cho<pullip.cho at samsung.com>
>> ---
>>   arch/arm/mach-exynos/Kconfig                    |   10 +-
>>   arch/arm/mach-exynos/Makefile                   |    2 +-
>>   arch/arm/mach-exynos/clock-exynos4.c            |   79 ++--
>>   arch/arm/mach-exynos/clock-exynos4.h            |    2 +
>>   arch/arm/mach-exynos/clock-exynos4210.c         |   11 +
>>   arch/arm/mach-exynos/clock-exynos4212.c         |   28 ++-
>>   arch/arm/mach-exynos/clock-exynos5.c            |   90 +++++
>>   arch/arm/mach-exynos/dev-sysmmu.c               |  457 ++++++++++++----------
>>   arch/arm/mach-exynos/include/mach/irqs.h        |   25 +-
>>   arch/arm/mach-exynos/include/mach/map.h         |   38 ++
>>   arch/arm/mach-exynos/include/mach/regs-clock.h  |    5 +
>>   arch/arm/mach-exynos/include/mach/regs-sysmmu.h |   28 --
>>   arch/arm/mach-exynos/include/mach/sysmmu.h      |   88 +++--
>>   arch/arm/mach-exynos/mach-armlex4210.c          |    1 -
>>   arch/arm/mach-exynos/mach-smdkv310.c            |    1 -
>>   15 files changed, 529 insertions(+), 336 deletions(-)
>>   delete mode 100644 arch/arm/mach-exynos/include/mach/regs-sysmmu.h
>
> This patch doesn't apply cleanly against upstream Linux (v3.3-rcX).
> Please rebase to upstream and resend. The other 2 patches apply fine.
>

Yes, as KyoungHo said, this has been created on top of Samsung tree 
for-next because this touches many exynos stuff which has been changed 
from Samsung tree for upcoming merge window. So if you're ok on this, 
1st patch and this should be sent to upstream via samsung tree even 
though I can't find any topic branch for this yet. And if you want topic 
branch for your tree, let me know, I can provide it.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From linus.walleij at linaro.org  Thu Mar 15 10:39:38 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 15 Mar 2012 15:39:38 +0100
Subject: [PATCH 03/10] ARM: ux500: combine the board init functions for DT
 boot
In-Reply-To: <1331730306-11461-4-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-4-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZUWQ9W4YUjqrowKoYo=HhGXg-arHacRDUD1s17Fucv1g@mail.gmail.com>

On Wed, Mar 14, 2012 at 2:04 PM, Lee Jones <lee.jones at linaro.org> wrote:

> From: Arnd Bergmann <arnd at arndb.de>
>
> This lets us move over evertything to device tree one by one.
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Clever!
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From richard.zhao at linaro.org  Thu Mar 15 10:46:04 2012
From: richard.zhao at linaro.org (Richard Zhao)
Date: Thu, 15 Mar 2012 22:46:04 +0800
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <20120314085228.GM3852@pengutronix.de>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
 <20120314085228.GM3852@pengutronix.de>
Message-ID: <20120315144601.GA5701@richard-laptop>

On Wed, Mar 14, 2012 at 09:52:28AM +0100, Sascha Hauer wrote:
> On Wed, Mar 14, 2012 at 04:22:58PM +0800, Richard Zhao wrote:
> > Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> > ---
> >  arch/arm/mach-imx/clock-imx6q.c |   85 +++++++++++++++++++++++++++++++++-----
> >  1 files changed, 73 insertions(+), 12 deletions(-)
> > 
> > diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
> > index e4e4f5e..3d5dc56 100644
> > --- a/arch/arm/mach-imx/clock-imx6q.c
> > +++ b/arch/arm/mach-imx/clock-imx6q.c
> > @@ -519,6 +519,18 @@ static int pll1_sys_set_rate(struct clk *clk, unsigned long rate)
> >  	return 0;
> >  }
> >  
> > +static unsigned long pll1_sys_round_rate(struct clk *clk, unsigned long rate)
> > +{
> > +	u32 div;
> > +	unsigned long parent_rate = clk_get_rate(clk->parent);
> > +
> > +	rate = rate < FREQ_650M ? FREQ_650M : rate;
> > +	rate = rate > FREQ_1300M ? FREQ_1300M : rate;
> > +
> > +	div = rate * 2 / parent_rate;
> > +	return parent_rate * div / 2;
> > +}
> > +
> >  static unsigned long pll8_enet_get_rate(struct clk *clk)
> >  {
> >  	u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >>
> > @@ -567,6 +579,20 @@ static int pll8_enet_set_rate(struct clk *clk, unsigned long rate)
> >  	return 0;
> >  }
> >  
> > +static unsigned long pll8_enet_round_rate(struct clk *clk, unsigned long rate)
> > +{
> > +	if (rate >= 125000000)
> > +		rate = 125000000;
> > +	else if (rate >= 100000000)
> > +		rate = 100000000;
> > +	else if (rate >= 50000000)
> > +		rate = 50000000;
> > +	else
> > +		rate = 25000000;
> > +	return rate;
> > +}
> > +
> > +
> >  static unsigned long pll_av_get_rate(struct clk *clk)
> >  {
> >  	void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
> > @@ -606,6 +632,25 @@ static int pll_av_set_rate(struct clk *clk, unsigned long rate)
> >  	return 0;
> >  }
> >  
> > +static unsigned long pll_av_round_rate(struct clk *clk, unsigned long rate)
> > +{
> > +	unsigned long parent_rate = clk_get_rate(clk->parent);
> > +	u32 div;
> > +	u32 mfn, mfd = 1000000;
> > +	s64 temp64;
> > +
> > +	rate = rate < FREQ_650M ? FREQ_650M : rate;
> > +	rate = rate > FREQ_1300M ? FREQ_1300M : rate;
> > +
> > +	div = rate / parent_rate;
> > +	temp64 = (u64) (parent_rate - (div * parent_rate));
> > +        temp64 *= mfd;
> > +        do_div(temp64, parent_rate);
> > +        mfn = temp64;
> > +
> > +        return (parent_rate * div) + ((parent_rate / mfd) * mfn);
> > +}
> > +
> >  static void __iomem *pll_get_div_reg_bit(struct clk *clk, u32 *bp, u32 *bm)
> >  {
> >  	void __iomem *reg;
> > @@ -662,18 +707,33 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
> >  	return 0;
> >  }
> >  
> > -#define pll2_bus_get_rate	pll_get_rate
> > -#define pll2_bus_set_rate	pll_set_rate
> > -#define pll3_usb_otg_get_rate	pll_get_rate
> > -#define pll3_usb_otg_set_rate	pll_set_rate
> > -#define pll7_usb_host_get_rate	pll_get_rate
> > -#define pll7_usb_host_set_rate	pll_set_rate
> > -#define pll4_audio_get_rate	pll_av_get_rate
> > -#define pll4_audio_set_rate	pll_av_set_rate
> > -#define pll5_video_get_rate	pll_av_get_rate
> > -#define pll5_video_set_rate	pll_av_set_rate
> > -#define pll6_mlb_get_rate	NULL
> > -#define pll6_mlb_set_rate	NULL
> > +static unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
> > +{
> > +	if (rate >= FREQ_528M)
> > +		rate = FREQ_528M;
> > +	else
> > +		rate = FREQ_480M;
> > +	return rate;
> > +}
> > +
> > +#define pll2_bus_get_rate		pll_get_rate
> > +#define pll2_bus_set_rate		pll_set_rate
> > +#define pll2_bus_round_rate		pll_round_rate
> > +#define pll3_usb_otg_get_rate		pll_get_rate
> > +#define pll3_usb_otg_set_rate		pll_set_rate
> > +#define pll3_usb_otg_round_rate		pll_round_rate
> > +#define pll7_usb_host_get_rate		pll_get_rate
> > +#define pll7_usb_host_set_rate		pll_set_rate
> > +#define pll7_usb_host_round_rate	pll_round_rate
> > +#define pll4_audio_get_rate		pll_av_get_rate
> > +#define pll4_audio_set_rate		pll_av_set_rate
> > +#define pll4_audio_round_rate		pll_av_round_rate
> > +#define pll5_video_get_rate		pll_av_get_rate
> > +#define pll5_video_set_rate		pll_av_set_rate
> > +#define pll5_video_round_rate		pll_av_round_rate
> > +#define pll6_mlb_get_rate		NULL
> > +#define pll6_mlb_set_rate		NULL
> > +#define pll6_mlb_round_rate		NULL
> >  
> >  #define DEF_PLL(name)					\
> >  	static struct clk name = {			\
> > @@ -681,6 +741,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
> >  		.disable	= pll_disable,		\
> >  		.get_rate	= name##_get_rate,	\
> >  		.set_rate	= name##_set_rate,	\
> > +		.round_rate	= name##_round_rate,	\
> 
> I hope this ## stuff is gone soon with the generic clock framework. It
> is so ugly and inefficient.
I hope this doesn't prevent this two patches go in.

Thanks
Richard
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From pintu_agarwal at yahoo.com  Thu Mar 15 10:53:23 2012
From: pintu_agarwal at yahoo.com (PINTU KUMAR)
Date: Thu, 15 Mar 2012 07:53:23 -0700 (PDT)
Subject: [INFO] : Hibernation and Resume between 2 similar devices
In-Reply-To: <10238.1331746385@turing-police.cc.vt.edu>
References: <28119509.96581331614425960.JavaMail.weblogic@epml27>
 <201203132136.56353.rjw@sisk.pl>
 <1331720518.14716.YahooMailNeo@web162005.mail.bf1.yahoo.com>
 <10238.1331746385@turing-police.cc.vt.edu>
Message-ID: <1331823203.99847.YahooMailNeo@web162001.mail.bf1.yahoo.com>



----- Original Message -----
> From: "Valdis.Kletnieks at vt.edu" <Valdis.Kletnieks at vt.edu>
> To: PINTU KUMAR <pintu_agarwal at yahoo.com>
> Cc: Rafael J. Wysocki <rjw at sisk.pl>; "linux-kernel at vger.kernel.org" <linux-kernel at vger.kernel.org>; "linux-arm-kernel at lists.infradead.org" <linux-arm-kernel at lists.infradead.org>
> Sent: Wednesday, 14 March 2012 11:03 PM
> Subject: Re: [INFO] : Hibernation and Resume between 2 similar devices
> 
> On Wed, 14 Mar 2012 03:21:58 PDT, PINTU KUMAR said:
>> > From: Rafael J. Wysocki <rjw at sisk.pl>
>> > Not out of the box (you'd need to hack the kernel for that to work 
> I think,
>> > at least on x86) and the devices would need to be _exactly_ identical.
>> > Moreover, if there is read-write mass storage in them, the filesystems 
> on
>> > both would have to be exactly identical as well (including metadata 
> and data
>> > layout etc.).
> 
>> Suppose in "Device 1" during hibernation, I have a file say 
> "file1.txt" opened whose inode number is say "123456".
>> This opened state of file1.txt will be captured in hibernation image.
>> Now assume that same "file1.txt" is also present (not opened) in 
> "Device2" but whose inode number is say "567890".
>> Now if I reboot "Device 2" and try to resume from hibernated 
> image of "Device 1", what would happen to "file1.txt" ??
> 
> Rafael was quite clear - the mass storage has to be *identical*.? You reboot
> with the image of "Device 1", that had file1.txt open, what will 
> happen when
> you close (or write, or sync) the file is this:
> 
> 1) You'll write data out to disk into whatever blocks were owned by inode
> 12345, no matter who actually owns them on Device2's storage.
> 
> 2) You'll write out inode 12345 to disk, no matter what used to be there.
> 
> Note that you'll do this same thing for *every single* file that was open 
> when
> you hibernated, which means you'll corrupt every file that was opened *and*
> every file that was closed but was using the same blocks on the new disk as the
> open file was using on the original disk.
> 
> In short, you just completely corrupted the file system. 

Yes, consider that 2 devices are identical in all respect.
ok lets discard the file (write, save) scenario after the resume. My doubt was, will I get the snapshot of file in RAM after I resume ?
Ok leave the file case.

Consider the case of?few application (which is already present in both the devices)?, 
lets say : In Device 1 we opened : Browser, calculator, a photo (already existing).
Then I captured the hibernated image in a swap file.
My I want to restore/resume this hibernated image from another _similar_ device.
After I resume, will I able to restore the same applications in Device 2 ????

Ok, if something cannot be resumed, we can throw it away.
I mean, during hibernation, if we opened 10 apps, and during resume we get only 5, that should be ok.
We can discard which ever is not relevant for Device 2.
?

> 


From s.hauer at pengutronix.de  Thu Mar 15 11:00:48 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 15 Mar 2012 16:00:48 +0100
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <20120315144601.GA5701@richard-laptop>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
 <20120314085228.GM3852@pengutronix.de>
 <20120315144601.GA5701@richard-laptop>
Message-ID: <20120315150048.GC3852@pengutronix.de>

On Thu, Mar 15, 2012 at 10:46:04PM +0800, Richard Zhao wrote:
> On Wed, Mar 14, 2012 at 09:52:28AM +0100, Sascha Hauer wrote:
> > On Wed, Mar 14, 2012 at 04:22:58PM +0800, Richard Zhao wrote:
> > > Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> > > ---
> > >  
> > >  #define DEF_PLL(name)					\
> > >  	static struct clk name = {			\
> > > @@ -681,6 +741,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
> > >  		.disable	= pll_disable,		\
> > >  		.get_rate	= name##_get_rate,	\
> > >  		.set_rate	= name##_set_rate,	\
> > > +		.round_rate	= name##_round_rate,	\
> > 
> > I hope this ## stuff is gone soon with the generic clock framework. It
> > is so ugly and inefficient.
> I hope this doesn't prevent this two patches go in.

Given that we are short from getting a generic clock framework (and I
think this time it's for real) and that you are not mention in any words
what these patches fix I don't see a reason for merging them.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From per.forlin at stericsson.com  Thu Mar 15 11:06:40 2012
From: per.forlin at stericsson.com (Per Forlin)
Date: Thu, 15 Mar 2012 16:06:40 +0100
Subject: [PATCH 0/5] MMC: mmci: Provide bindings for Device Tree
In-Reply-To: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CAFEEs1kz+QT_4Yc6byS4se0EMZvqA5hp5CvLvvtNgC++AJboxA@mail.gmail.com>

Hi,

I would like to see what the minimal required change is to support DT
for mmci without factorization.
1. Minimal change in mmci.
2. Add mmci_dt.c which contains the DT-populate code.

The factorization could be done as step 2 I think.

What do you say?

BR
Per

On Wed, Mar 14, 2012 at 3:19 PM, Lee Jones <lee.jones at linaro.org> wrote:
> This patch-set splits out ux500 and ARM specific variants from mmci
> core code, applies generic bindings for use by all variants, then
> enables the ux500 variant for use with Device Tree.
>
> ?Documentation/devicetree/bindings/mmc/mmci.txt | ? 27 +++
> ?arch/arm/boot/dts/db8500.dtsi ? ? ? ? ? ? ? ? ?| ? ?6 +-
> ?arch/arm/boot/dts/snowball.dts ? ? ? ? ? ? ? ? | ? 30 +++-
> ?arch/arm/mach-ux500/board-mop500.c ? ? ? ? ? ? | ? ?3 +-
> ?drivers/mmc/host/Makefile ? ? ? ? ? ? ? ? ? ? ?| ? ?2 +-
> ?drivers/mmc/host/mmci-arm.c ? ? ? ? ? ? ? ? ? ?| ? 65 ++++++
> ?drivers/mmc/host/mmci-ux500.c ? ? ? ? ? ? ? ? ?| ?260 ++++++++++++++++++++++++
> ?drivers/mmc/host/mmci.c ? ? ? ? ? ? ? ? ? ? ? ?| ?194 +++++-------------
> ?drivers/mmc/host/mmci.h ? ? ? ? ? ? ? ? ? ? ? ?| ? 37 ++++
> ?9 files changed, 473 insertions(+), 151 deletions(-)
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html


From shawn.guo at linaro.org  Thu Mar 15 11:07:04 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 15 Mar 2012 23:07:04 +0800
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <20120315150048.GC3852@pengutronix.de>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
 <20120314085228.GM3852@pengutronix.de>
 <20120315144601.GA5701@richard-laptop>
 <20120315150048.GC3852@pengutronix.de>
Message-ID: <CAAQ0ZWRfgaj2W8m6RvHwtwExSF=hT5ysyxmw9vQriFm5es6Mhg@mail.gmail.com>

On 15 March 2012 23:00, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Thu, Mar 15, 2012 at 10:46:04PM +0800, Richard Zhao wrote:
>> On Wed, Mar 14, 2012 at 09:52:28AM +0100, Sascha Hauer wrote:
>> > On Wed, Mar 14, 2012 at 04:22:58PM +0800, Richard Zhao wrote:
>> > > Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
>> > > ---
>> > >
>> > > ?#define DEF_PLL(name) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> > > ? static struct clk name = { ? ? ? ? ? ? ? ? ? ? ?\
>> > > @@ -681,6 +741,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
>> > > ? ? ? ? ? .disable ? ? ? ?= pll_disable, ? ? ? ? ?\
>> > > ? ? ? ? ? .get_rate ? ? ? = name##_get_rate, ? ? ?\
>> > > ? ? ? ? ? .set_rate ? ? ? = name##_set_rate, ? ? ?\
>> > > + ? ? ? ? .round_rate ? ? = name##_round_rate, ? ?\
>> >
>> > I hope this ## stuff is gone soon with the generic clock framework. It
>> > is so ugly and inefficient.
>> I hope this doesn't prevent this two patches go in.
>
> Given that we are short from getting a generic clock framework (and I
> think this time it's for real) and that you are not mention in any words
> what these patches fix I don't see a reason for merging them.
>
And I agree with Sascha.  Since I'm resuming my imx6 common clk
migration, you can keep an eye on the patches to ensure the changes
you are proposing here get rolled in.

Regards,
Shawn


From per.forlin at stericsson.com  Thu Mar 15 11:12:21 2012
From: per.forlin at stericsson.com (Per Forlin)
Date: Thu, 15 Mar 2012 16:12:21 +0100
Subject: [PATCH 3/5] MMC: mmci: Add generic Device Tree bindings to mmci
 core code
In-Reply-To: <1331734803-17954-4-git-send-email-lee.jones@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <1331734803-17954-4-git-send-email-lee.jones@linaro.org>
Message-ID: <CAFEEs1mQr4hDC6RuvchfWe7HNq67Eh2bPtwyWN-tukw32-V0rg@mail.gmail.com>

On Wed, Mar 14, 2012 at 3:20 PM, Lee Jones <lee.jones at linaro.org> wrote:
> This adds the necessary bindings for collection of shared
> attributes used in the mmci driver.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
> ?drivers/mmc/host/mmci.c | ? 43 +++++++++++++++++++++++++++++++++++++++++++
> ?1 files changed, 43 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> index 23b41a5..9132ca8 100644
> --- a/drivers/mmc/host/mmci.c
> +++ b/drivers/mmc/host/mmci.c
> @@ -30,6 +30,7 @@
> ?#include <linux/dma-mapping.h>
> ?#include <linux/amba/mmci.h>
> ?#include <linux/pm_runtime.h>
> +#include <linux/of_gpio.h>
>
> ?#include <asm/div64.h>
> ?#include <asm/io.h>
> @@ -1056,11 +1057,47 @@ static const struct mmc_host_ops mmci_ops = {
> ? ? ? ?.get_cd ? ? ? ? = mmci_get_cd,
> ?};
>
> +#ifdef CONFIG_OF
> +static void mmci_dt_populate_generic_pdata(struct device_node *np,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct mmci_platform_data *pdata)
> +{
> + ? ? ? const void *prop;
> + ? ? ? int len;
> +
> + ? ? ? of_property_read_u32(np, "wp-gpios", &pdata->gpio_wp);
> + ? ? ? if (!pdata->gpio_wp)
> + ? ? ? ? ? ? ? pdata->gpio_wp = -1;
> +
> + ? ? ? of_property_read_u32(np, "cd-gpios", &pdata->gpio_cd);
> + ? ? ? if (!pdata->gpio_cd)
> + ? ? ? ? ? ? ? pdata->gpio_cd = -1;
> +
> + ? ? ? if (of_get_property(np, "cd-invert", NULL))
> + ? ? ? ? ? ? ? pdata->cd_invert = true;
> + ? ? ? else
> + ? ? ? ? ? ? ? pdata->cd_invert = false;
> +
> + ? ? ? of_property_read_u32(np, "clock_frequency", &pdata->f_max);
> + ? ? ? if (!pdata->f_max)
> + ? ? ? ? ? ? ? pr_warning("%s has no 'clock_frequency' property\n", np->full_name);
> +
> + ? ? ? if (of_get_property(np, "mmc_cap_4_bit_data", NULL))
I have no previous experience with DT. Could you please bring some
light on this.
Is it really necessary to represent each bit in the CAP with a string?
To add CAP_ERASE for instance I need to change the code here and
update the DT, right?

BR
Per


From arnd at arndb.de  Thu Mar 15 11:12:20 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 15:12:20 +0000
Subject: [GIT PULL] LPC32xx: Ethernet support
In-Reply-To: <4F5FC86A.70501@antcom.de>
References: <4F5FC86A.70501@antcom.de>
Message-ID: <201203151512.21185.arnd@arndb.de>

On Tuesday 13 March 2012, Roland Stigge wrote:
> Hi Arnd and Olof,
> 
> now that David Miller has accepted the LPC32xx Ethernet patches into
> net-next, I'm providing the respective LPC32xx platform code as described
> below.
> 
> It's on top of v3.3-rc5, the already existing LPC32xx patches in arm-soc
> and the USB support patch. So please first pull the USB patch.
> 
> Thanks in advance,

Pulled both usb and eth into the lpc32xx/drivers branch in arm-soc.

Thanks,

	Arnd


From richard.zhao at linaro.org  Thu Mar 15 11:15:23 2012
From: richard.zhao at linaro.org (Richard Zhao)
Date: Thu, 15 Mar 2012 23:15:23 +0800
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <20120315150048.GC3852@pengutronix.de>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
 <20120314085228.GM3852@pengutronix.de>
 <20120315144601.GA5701@richard-laptop>
 <20120315150048.GC3852@pengutronix.de>
Message-ID: <20120315151521.GB5701@richard-laptop>

On Thu, Mar 15, 2012 at 04:00:48PM +0100, Sascha Hauer wrote:
> On Thu, Mar 15, 2012 at 10:46:04PM +0800, Richard Zhao wrote:
> > On Wed, Mar 14, 2012 at 09:52:28AM +0100, Sascha Hauer wrote:
> > > On Wed, Mar 14, 2012 at 04:22:58PM +0800, Richard Zhao wrote:
> > > > Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> > > > ---
> > > >  
> > > >  #define DEF_PLL(name)					\
> > > >  	static struct clk name = {			\
> > > > @@ -681,6 +741,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
> > > >  		.disable	= pll_disable,		\
> > > >  		.get_rate	= name##_get_rate,	\
> > > >  		.set_rate	= name##_set_rate,	\
> > > > +		.round_rate	= name##_round_rate,	\
> > > 
> > > I hope this ## stuff is gone soon with the generic clock framework. It
> > > is so ugly and inefficient.
> > I hope this doesn't prevent this two patches go in.
> 
> Given that we are short from getting a generic clock framework (and I
> think this time it's for real) and that you are not mention in any words
> what these patches fix I don't see a reason for merging them.
I think the cpu clock is a great challenge for generic clock framework.
When it set_rate, it includes reparent, and change parent's parent's rate.
I don't see any upstream code like that till now. and it's really what
we need.

And it also block cpufreq from upstreaming.


Thanks
Richard
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Thu Mar 15 11:21:16 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 15:21:16 +0000
Subject: [GIT PULL] ep93xx for v3.4
In-Reply-To: <4F6034D6.1030208@gmail.com>
References: <4F6034D6.1030208@gmail.com>
Message-ID: <201203151521.16239.arnd@arndb.de>

On Wednesday 14 March 2012, Ryan Mallon wrote:
> This my first attempt at doing at git pull request, so hopefully I
> haven't messed it up :-).

Looks all good to me.

> The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
>   Linus Torvalds (1):
>         Linux 3.3-rc7
> 
> are available in the git repository at:
> 
>   git://github.com/RyanMallon/linux-2.6.git ep93xx-for-arm-soc
> 

Applied to next/cleanup branch,

I got a small conflict between 3.3-rc7 and the cleanup branch, but that
had nothing to do with you.

Thanks!

	ARnd


From omar.ramirez at ti.com  Thu Mar 15 11:21:29 2012
From: omar.ramirez at ti.com (Ramirez Luna, Omar)
Date: Thu, 15 Mar 2012 10:21:29 -0500
Subject: [PATCH v2 5/8] ARM: OMAP2+: hwmod: ensure that SYSCONFIG bits are
 reprogrammed after a reset
In-Reply-To: <alpine.DEB.2.00.1203150024260.7269@utopia.booyaka.com>
References: <20120228053524.16278.59430.stgit@dusk>
 <20120228053657.16278.76132.stgit@dusk>
 <CAB-zwWhAa3PprwDLzWLkBFUHPeJO3HN3M9mAZF=ohGTvP43jYA@mail.gmail.com>
 <alpine.DEB.2.00.1203150024260.7269@utopia.booyaka.com>
Message-ID: <CAB-zwWh3tcz5xUkzthH_AAsmeXfMieUW-SCQnAaXyfSg8khqvg@mail.gmail.com>

On Thu, Mar 15, 2012 at 1:25 AM, Paul Walmsley <paul at pwsan.com> wrote:
> Hola Omar,

Hola :)

> On Wed, 14 Mar 2012, Ramirez Luna, Omar wrote:
>
>> If we reached here the reset lines will be asserted, and then the code
>> below touches sysc registers on a module under reset.
>
> Do you know of any case where this would be a problem? ?Seems like it
> would only affect IP blocks that have both hard reset lines and SYSCONFIG
> registers, and as far as I know, we don't have any of those defined?

MMU (not yet mainlined) has both, a reset line and a sysconfig.

I have been holding the hwmod for some time, but now that
rpmsg/remoteproc is going to mainline it could make use of it along
with omap3isp, however now I need to define functions to handle the
reset lines (although I was fine with hwmod handling it).

AFAIKnew, hwmod handling the reset line was fine (IMHO), the only 2 things were:
- For the drivers to somehow make use of shutdown/enable if they
needed they hwmod under reset and out.
- The annoying: hwmod XX failed to hardreset because of the wrong
reset sequence but causing no functional issues.

Regards,

Omar


From lee.jones at linaro.org  Thu Mar 15 11:25:05 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 15 Mar 2012 15:25:05 +0000
Subject: [PATCH 3/5] MMC: mmci: Add generic Device Tree bindings to mmci
 core code
In-Reply-To: <CAFEEs1mQr4hDC6RuvchfWe7HNq67Eh2bPtwyWN-tukw32-V0rg@mail.gmail.com>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <1331734803-17954-4-git-send-email-lee.jones@linaro.org>
 <CAFEEs1mQr4hDC6RuvchfWe7HNq67Eh2bPtwyWN-tukw32-V0rg@mail.gmail.com>
Message-ID: <4F6209D1.9070805@linaro.org>

On 15/03/12 15:12, Per Forlin wrote:
> On Wed, Mar 14, 2012 at 3:20 PM, Lee Jones <lee.jones at linaro.org> wrote:
>> This adds the necessary bindings for collection of shared
>> attributes used in the mmci driver.
>>
>> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>> ---
>>  drivers/mmc/host/mmci.c |   43 +++++++++++++++++++++++++++++++++++++++++++
>>  1 files changed, 43 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
>> index 23b41a5..9132ca8 100644
>> --- a/drivers/mmc/host/mmci.c
>> +++ b/drivers/mmc/host/mmci.c
>> @@ -30,6 +30,7 @@
>>  #include <linux/dma-mapping.h>
>>  #include <linux/amba/mmci.h>
>>  #include <linux/pm_runtime.h>
>> +#include <linux/of_gpio.h>
>>
>>  #include <asm/div64.h>
>>  #include <asm/io.h>
>> @@ -1056,11 +1057,47 @@ static const struct mmc_host_ops mmci_ops = {
>>        .get_cd         = mmci_get_cd,
>>  };
>>
>> +#ifdef CONFIG_OF
>> +static void mmci_dt_populate_generic_pdata(struct device_node *np,
>> +                                       struct mmci_platform_data *pdata)
>> +{
>> +       const void *prop;
>> +       int len;
>> +
>> +       of_property_read_u32(np, "wp-gpios", &pdata->gpio_wp);
>> +       if (!pdata->gpio_wp)
>> +               pdata->gpio_wp = -1;
>> +
>> +       of_property_read_u32(np, "cd-gpios", &pdata->gpio_cd);
>> +       if (!pdata->gpio_cd)
>> +               pdata->gpio_cd = -1;
>> +
>> +       if (of_get_property(np, "cd-invert", NULL))
>> +               pdata->cd_invert = true;
>> +       else
>> +               pdata->cd_invert = false;
>> +
>> +       of_property_read_u32(np, "clock_frequency", &pdata->f_max);
>> +       if (!pdata->f_max)
>> +               pr_warning("%s has no 'clock_frequency' property\n", np->full_name);
>> +
>> +       if (of_get_property(np, "mmc_cap_4_bit_data", NULL))
> I have no previous experience with DT. Could you please bring some
> light on this.
> Is it really necessary to represent each bit in the CAP with a string?

No, you can use a straight integer in the DT blob, but this makes it
much easier to read.

> To add CAP_ERASE for instance I need to change the code here and
> update the DT, right?

That's right, but no MMCI user makes use of it, so it would just be
unnecessary/unused code clogging up the core driver.

Kind regards,
Lee

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Thu Mar 15 11:25:14 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 15 Mar 2012 15:25:14 +0000
Subject: [PATCH 0/5] MMC: mmci: Provide bindings for Device Tree
In-Reply-To: <CAFEEs1kz+QT_4Yc6byS4se0EMZvqA5hp5CvLvvtNgC++AJboxA@mail.gmail.com>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <CAFEEs1kz+QT_4Yc6byS4se0EMZvqA5hp5CvLvvtNgC++AJboxA@mail.gmail.com>
Message-ID: <4F6209DA.1080809@linaro.org>

Hi Per,

> I would like to see what the minimal required change is to support DT
> for mmci without factorization.
> 1. Minimal change in mmci.
> 2. Add mmci_dt.c which contains the DT-populate code.
> 
> The factorization could be done as step 2 I think.
> 
> What do you say?

I'm wondering what the difference is as the work has already been done.

It was Arnd's suggestion to separate out the two types of variants, and
I'm quite fond of the new (fully featured) layout.

Kind regards,
Lee

> On Wed, Mar 14, 2012 at 3:19 PM, Lee Jones <lee.jones at linaro.org> wrote:
>> This patch-set splits out ux500 and ARM specific variants from mmci
>> core code, applies generic bindings for use by all variants, then
>> enables the ux500 variant for use with Device Tree.
>>
>>  Documentation/devicetree/bindings/mmc/mmci.txt |   27 +++
>>  arch/arm/boot/dts/db8500.dtsi                  |    6 +-
>>  arch/arm/boot/dts/snowball.dts                 |   30 +++-
>>  arch/arm/mach-ux500/board-mop500.c             |    3 +-
>>  drivers/mmc/host/Makefile                      |    2 +-
>>  drivers/mmc/host/mmci-arm.c                    |   65 ++++++
>>  drivers/mmc/host/mmci-ux500.c                  |  260 ++++++++++++++++++++++++
>>  drivers/mmc/host/mmci.c                        |  194 +++++-------------
>>  drivers/mmc/host/mmci.h                        |   37 ++++
>>  9 files changed, 473 insertions(+), 151 deletions(-)
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html


-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From arnd at arndb.de  Thu Mar 15 11:32:44 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 15:32:44 +0000
Subject: [PATCH 0/5] MMC: mmci: Provide bindings for Device Tree
In-Reply-To: <4F6209DA.1080809@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <CAFEEs1kz+QT_4Yc6byS4se0EMZvqA5hp5CvLvvtNgC++AJboxA@mail.gmail.com>
 <4F6209DA.1080809@linaro.org>
Message-ID: <201203151532.44363.arnd@arndb.de>

On Thursday 15 March 2012, Lee Jones wrote:
> > I would like to see what the minimal required change is to support DT
> > for mmci without factorization.
> > 1. Minimal change in mmci.
> > 2. Add mmci_dt.c which contains the DT-populate code.
> > 
> > The factorization could be done as step 2 I think.
> > 
> > What do you say?
> 
> I'm wondering what the difference is as the work has already been done.
> 
> It was Arnd's suggestion to separate out the two types of variants, and
> I'm quite fond of the new (fully featured) layout.

Right, I usually prefer cleanups or other refactoring to be done first, and
then features added on top.

You could in theory add have just patches 3/4/5 all applied without
the refactoring, but that I would be worried that this causes dependencies
between the mmci driver and ux500 specific functionality like the
stedma40_filter function.

	Arnd


From tpiepho at gmail.com  Thu Mar 15 11:39:46 2012
From: tpiepho at gmail.com (Trent Piepho)
Date: Thu, 15 Mar 2012 11:39:46 -0400
Subject: [alsa-devel] [PATCH v3 09/11] ASoC: fsl: remove the fatal error
 checking on codec-handle
In-Reply-To: <20120315142115.GB6065@S2101-09.ap.freescale.net>
References: <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315130253.GA6065@S2101-09.ap.freescale.net>
 <4F61F080.4090800@freescale.com>
 <20120315142115.GB6065@S2101-09.ap.freescale.net>
Message-ID: <CA+7tXig6=gz8utcnV8qUs6=JnwEz8+tqc-57v-xNcYcK_AAHXw@mail.gmail.com>

On Thu, Mar 15, 2012 at 10:21 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Thu, Mar 15, 2012 at 01:37:06PM +0000, Tabi Timur-B04825 wrote:
> ...
> > The PowerPC MPC8610 has two SSIs, and I have a hacked up board that has
> > both connected to two CS4270s. ?This is how I tested multiple SSI support
> > in my driver.
> >
> > Since my driver supports any number of SSIs, I expect any changes to it to
> > continue that support.
> >
> I think it can still easily get supported with the binding like below.
>
> sound {
> ? ? ?compatible = "fsl,imx51-babbage-sgtl5000",
> ? ? ? ? ? ? ? ? ? "fsl,imx-audio-sgtl5000";
> ? ? ?model = "imx51-babbage-sgtl5000";
> ? ? ?ssi-controller = <&ssi1, &ssi2>;
> ? ? ?audio-codec = <&sgtl5000_1, &sgtl5000_2>;
> ? ? ?mux-int-port = <1>;
> ? ? ?mux-ext-port = <3>;
> };

How would you support binding the imx51 ESAI controller?

>
> The only difference will be both ssi-controller and audio-codec become
> an array of phandles.
>
> ...
> > I admit I may have been too hasty in giving that ACK, because I did not
> > take the time to study the binding. ?I figured that the new binding was
> > superior to what I came up with years ago.
> >
> > Now that I've studied the binding, I no longer believe that. ?I don't
> > understand what's so wonderful about the new binding that my driver has to
> > support it *and* the old binding. ?I think it would be easier if i.MX uses
> > the original binding.
> >
> I do not think it would be easier for imx. ?Looking at the imx-sgtl5000
> binding, you will find we have audmux port configuration encoded there.
> How would you suggest to get that fit into the PowerPC binding?
>
> ...
> > Even if the new binding is "better", I do not see how it's SOOOOO much
> > better that my driver has to support it. ?The drawback in supporting both
> > is the added complexity.
>
> If you insist on that the driver should only support single binding,
> I would rather change mpc8610_hpcd and p1022_ds to use the new binding.
>
> ...
> > But the driver already does this! ?No one's asking you to add the code to
> > perform these tasks. ?Just use the existing code.
>
> Again, what's your suggestion to support audmux configuration with the
> existing binding?
>
> --
> Regards,
> Shawn
> _______________________________________________
> Alsa-devel mailing list
> Alsa-devel at alsa-project.org
> http://mailman.alsa-project.org/mailman/listinfo/alsa-devel


From plagnioj at jcrosoft.com  Thu Mar 15 11:32:31 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 15 Mar 2012 16:32:31 +0100
Subject: [PATCH v2] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <201203142001.58762.sr@denx.de>
References: <1331737232-25477-1-git-send-email-sr@denx.de>
 <201203141749.05899.sr@denx.de>
 <20120314172435.GP18320@game.jcrosoft.org>
 <201203142001.58762.sr@denx.de>
Message-ID: <20120315153231.GA7757@game.jcrosoft.org>

On 20:01 Wed 14 Mar     , Stefan Roese wrote:
> On Wednesday 14 March 2012 18:24:35 Jean-Christophe PLAGNIOL-VILLARD wrote:
> > > > > diff --git a/arch/arm/boot/dts/spear600-evb.dts
> > > > > b/arch/arm/boot/dts/spear600-evb.dts new file mode 100644
> > > > > index 0000000..cbfda8d
> > > > > --- /dev/null
> > > > > +++ b/arch/arm/boot/dts/spear600-evb.dts
> > > > > @@ -0,0 +1,30 @@
> > > > > +/*
> > > > > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > > > > + *
> > > > > + * The code contained herein is licensed under the GNU General
> > > > > Public + * License. You may obtain a copy of the GNU General Public
> > > > > License + * Version 2 or later at the following locations:
> > > > > + *
> > > > > + * http://www.opensource.org/licenses/gpl-license.html
> > > > > + * http://www.gnu.org/copyleft/gpl.html
> > > > > + */
> > > > > +
> > > > > +/dts-v1/;
> > > > > +/include/ "spear600.dtsi"
> > > > > +
> > > > > +/ {
> > > > > +	model = "ST SPEAr600 Evaluation Board";
> > > > > +	compatible = "st,spear600-evb", "st,spear600";
> > > > > +	#address-cells = <1>;
> > > > > +	#size-cells = <1>;
> > > > 
> > > > please put the mem size here
> > > 
> > > Might I ask why? Other *.dtsi files don't have it either.
> > 
> > do not expect the bootloader to put it. I t's not mandatory
> 
> But the memory node it is already present in spear600.dtsi (see below). Do we 
> really need to duplicate this in the board specific dts file?
no if the mem is the same size please drop the commentabout bootloader update
it's a common knowlegde on DT for ARM
>  
> > > > > +
> > > > > +	soc {
> > > > > +		gmac0: ethernet at e0800000 {
> > > > > +			phy-mode = "gmii";
> > > > > +		};
> > > > > +
> > > > > +		i2c at d0200000 {
> > > > > +			clock-frequency = <400000>;
> > > > > +		};
> > > > > +	};
> > > > > +};
> > > > > diff --git a/arch/arm/boot/dts/spear600.dtsi
> > > > > b/arch/arm/boot/dts/spear600.dtsi new file mode 100644
> > > > > index 0000000..e45e58f
> > > > > --- /dev/null
> > > > > +++ b/arch/arm/boot/dts/spear600.dtsi
> > > > > @@ -0,0 +1,162 @@
> > > > > +/*
> > > > > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > > > > + *
> > > > > + * The code contained herein is licensed under the GNU General
> > > > > Public + * License. You may obtain a copy of the GNU General Public
> > > > > License + * Version 2 or later at the following locations:
> > > > > + *
> > > > > + * http://www.opensource.org/licenses/gpl-license.html
> > > > > + * http://www.gnu.org/copyleft/gpl.html
> > > > > + */
> > > > > +
> > > > > +/include/ "skeleton.dtsi"
> > > > > +
> > > > > +/ {
> > > > > +	compatible = "st,spear600";
> > > > > +
> > > > > +	cpus {
> > > > > +		cpu at 0 {
> > > > > +			compatible = "arm,arm926ejs";
> > > > > +		};
> > > > > +	};
> > > > > +
> > > > > +	memory {
> > > > > +		device_type = "memory";
> > > > > +		reg = <0 0>; /* Filled by U-Boot */
> > > > 
> > > > please put the max mem of the SoC here
> > > 
> > > Why? It's always updated by the bootloader. And a max. mem size (when not
> > > updated to the correct mem size by the bootloader) would crash the board
> > > if it is equipped with less memory.
> > 
> > yes but we descripbe the soc here and on the dts you reduce it
> > Never expect the bootloader to update it.
> 
> Without update to real size we're doomed.
yes but the board dts is supposed to udpate it

you put the max in the soc dtsi

and the real mem size in board dts

Best Regards,
J.


From lee.jones at linaro.org  Thu Mar 15 11:44:21 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 15 Mar 2012 15:44:21 +0000
Subject: [PATCH 0/5] MMC: mmci: Provide bindings for Device Tree
In-Reply-To: <201203151532.44363.arnd@arndb.de>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <CAFEEs1kz+QT_4Yc6byS4se0EMZvqA5hp5CvLvvtNgC++AJboxA@mail.gmail.com>
 <4F6209DA.1080809@linaro.org> <201203151532.44363.arnd@arndb.de>
Message-ID: <4F620E55.4000701@linaro.org>

On 15/03/12 15:32, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Lee Jones wrote:
>>> I would like to see what the minimal required change is to support DT
>>> for mmci without factorization.
>>> 1. Minimal change in mmci.
>>> 2. Add mmci_dt.c which contains the DT-populate code.
>>>
>>> The factorization could be done as step 2 I think.
>>>
>>> What do you say?
>>
>> I'm wondering what the difference is as the work has already been done.
>>
>> It was Arnd's suggestion to separate out the two types of variants, and
>> I'm quite fond of the new (fully featured) layout.
> 
> Right, I usually prefer cleanups or other refactoring to be done first, and
> then features added on top.
> 
> You could in theory add have just patches 3/4/5 all applied without
> the refactoring, but that I would be worried that this causes dependencies
> between the mmci driver and ux500 specific functionality like the
> stedma40_filter function.

It's a possibility that we may have run into that even with this new
layout. Remember you suggested that the u300 variant may be better off
going into the ARM variant's file, but I wasn't quite sure, as it was an
ST product. Well the afore mentioned function may still cause us some
trouble. I am in the mists of some regression testing now. I'll report
back when I know more.

Kind regards,
Lee


-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From arnd at arndb.de  Thu Mar 15 11:52:09 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 15:52:09 +0000
Subject: [GIT PULL] DaVinci fixes for v3.3
In-Reply-To: <DF0F476B391FA8409C78302C7BA518B6317F5E48@DBDE01.ent.ti.com>
References: <DF0F476B391FA8409C78302C7BA518B6317F5E48@DBDE01.ent.ti.com>
Message-ID: <201203151552.09922.arnd@arndb.de>

On Wednesday 14 March 2012, Nori, Sekhar wrote:
> Hi Arnd, Olof,
> 
> Can you please pull the following DaVinci fixes for v3.3.
> They fix a build and section mismatch warning.
> 
> Thanks,
> Sekhar
> 
> The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
>   Linus Torvalds (1):
>         Linux 3.3-rc7
> 
> are available in the git repository at:
> 
>   git://gitorious.org/linux-davinci/linux-davinci.git fixes
> 
> Uwe Kleine-K??????nig (2):
>       ARM: davinci: cpufreq: fix compiler warning
>       ARM: davinci: DA850: move da850_register_pm to .init.text
> 
>  arch/arm/mach-davinci/cpufreq.c |    2 +-
>  arch/arm/mach-davinci/da850.c   |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-
> 

Hi Sekhar,

I've applied these two to the next/fixes-non-critical branch for v3.4,
not the fixes branch for v3.3 because they both look like they have
no impact on production systems other than the build warnings.

If I missed something and one or both patches are indeed required for 3.3,
please let me know.

	Arnd


From arnd at arndb.de  Thu Mar 15 11:52:54 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 15:52:54 +0000
Subject: [PATCH v9] mfd: Add anatop mfd driver
In-Reply-To: <20120315120948.GG3138@opensource.wolfsonmicro.com>
References: <1331797421-23731-1-git-send-email-paul.liu@linaro.org>
 <201203150907.29895.arnd@arndb.de>
 <20120315120948.GG3138@opensource.wolfsonmicro.com>
Message-ID: <201203151552.54617.arnd@arndb.de>

On Thursday 15 March 2012, Mark Brown wrote:
> There were some other mutterings about using regmap for memory mapped
> devices, mostly from the point of view of building framework features
> like this on top of it.  regmap currently makes some assumptions that
> the I/O is going to be slow so approximately any amount of CPU time can
> usefully be spent on avoiding I/O but we can probably do something about
> that.  It also uses mutexes to lock I/O which might not be the most
> sensible thing for memory mapped devices, but again that's solveable.
> Right now there's no memory mapping support but there's no reason that
> can't be added.
> 
> In short, it does seem sensible to want to have some support for this
> for devices that use appropriate idioms.

Ok, I see. 

I guess there is no reason to change anything in Paul's patch now, but
we can keep this in mind if we see a lot of similar drivers in the future.

Thanks,

	Arnd


From linus.walleij at linaro.org  Thu Mar 15 11:56:52 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 15 Mar 2012 16:56:52 +0100
Subject: [PATCH 04/10] ARM: ux500: split dts file for snowball into
 generic part
In-Reply-To: <1331730306-11461-5-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-5-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbtR29w9ObEwnQ6zKboQdjFf6kWcGea8KTCYiWqefoYaA@mail.gmail.com>

On Wed, Mar 14, 2012 at 2:05 PM, Lee Jones <lee.jones at linaro.org> wrote:

> From: Arnd Bergmann <arnd at arndb.de>
>
> db8500.dtsi can be used by all systems with a db8500 or
> db9500 SoC, while snowball.dts is board specific.
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Thanks,
Linus Walleij


From tpiepho at gmail.com  Thu Mar 15 11:57:52 2012
From: tpiepho at gmail.com (Trent Piepho)
Date: Thu, 15 Mar 2012 11:57:52 -0400
Subject: [alsa-devel] [PATCH v3 09/11] ASoC: fsl: remove the fatal error
 checking on codec-handle
In-Reply-To: <CA+7tXig6=gz8utcnV8qUs6=JnwEz8+tqc-57v-xNcYcK_AAHXw@mail.gmail.com>
References: <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315130253.GA6065@S2101-09.ap.freescale.net>
 <4F61F080.4090800@freescale.com>
 <20120315142115.GB6065@S2101-09.ap.freescale.net>
 <CA+7tXig6=gz8utcnV8qUs6=JnwEz8+tqc-57v-xNcYcK_AAHXw@mail.gmail.com>
Message-ID: <CA+7tXiiJyLAm1ytyqQYgbJ_roUtXwxqhFWKEBk+4jY_HV5V8Zg@mail.gmail.com>

On Thu, Mar 15, 2012 at 11:39 AM, Trent Piepho <tpiepho at gmail.com> wrote:
> On Thu, Mar 15, 2012 at 10:21 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
>> On Thu, Mar 15, 2012 at 01:37:06PM +0000, Tabi Timur-B04825 wrote:
>> ...
>> > The PowerPC MPC8610 has two SSIs, and I have a hacked up board that has
>> > both connected to two CS4270s. ?This is how I tested multiple SSI support
>> > in my driver.
>> >
>> > Since my driver supports any number of SSIs, I expect any changes to it to
>> > continue that support.
>> >
>> I think it can still easily get supported with the binding like below.
>>
>> sound {
>> ? ? ?compatible = "fsl,imx51-babbage-sgtl5000",
>> ? ? ? ? ? ? ? ? ? "fsl,imx-audio-sgtl5000";
>> ? ? ?model = "imx51-babbage-sgtl5000";
>> ? ? ?ssi-controller = <&ssi1, &ssi2>;
>> ? ? ?audio-codec = <&sgtl5000_1, &sgtl5000_2>;
>> ? ? ?mux-int-port = <1>;
>> ? ? ?mux-ext-port = <3>;
>> };
>
> How would you support binding the imx51 ESAI controller?

Sorry about previous email, laptop touchpad emitted a spurious click,
which caused text window in gmail to become deselected, which caused a
subsequent enter to send the email rather than creating a new line.

For esai, would you add something like:
    esai-controller = <&esai1>;
    esai-audio-codec = <&sgtl5000_3>;

That seems rather ugly to me.

It seems to me in most device bindings where one piece of hardware is
attached to another, than the one upstream has in its binding a
phandle to the one downstream.  But here we have a third binding with
two lists of devices and an implied link between devices in
corresponding positions in the lists.  Does any other device binding
work like that?


From nicolas.ferre at atmel.com  Thu Mar 15 11:57:20 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 16:57:20 +0100
Subject: [PATCH 4/6] rtc: Kconfig: remove dependency for AT91 rtc driver
In-Reply-To: <cover.1331826095.git.nicolas.ferre@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
Message-ID: <7dce7bba2113315bf484570e3e0ad234c68c610b.1331826095.git.nicolas.ferre@atmel.com>

This will allow to select this driver for newer SoCs.
Keep dependency on AT91 because of the use of an header
file located in include/mach directory.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/rtc/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 3a125b8..918736e 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -831,7 +831,7 @@ config RTC_DRV_AT32AP700X
 
 config RTC_DRV_AT91RM9200
 	tristate "AT91RM9200 or some AT91SAM9 RTC"
-	depends on ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
+	depends on ARCH_AT91
 	help
 	  Driver for the internal RTC (Realtime Clock) module found on
 	  Atmel AT91RM9200's and some  AT91SAM9 chips. On AT91SAM9 chips
-- 
1.7.9



From nicolas.ferre at atmel.com  Thu Mar 15 11:57:18 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 16:57:18 +0100
Subject: [PATCH 2/6] mmc: Kconfig: remove choice between at91_mci and atmel-mci
In-Reply-To: <cover.1331826095.git.nicolas.ferre@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
Message-ID: <d86c9743d2434e2c6a2a34cefe6c989e0efa9652.1331826095.git.nicolas.ferre@atmel.com>

This choice is not so important now that atmel-mci supports every
Atmel AT91 SoC except AT91RM9200. As this newer driver is better
maintained choose this one to avoid confusion.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/mmc/host/Kconfig |   13 ++-----------
 1 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 00fcbed..455a414 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -270,16 +270,9 @@ config MMC_AU1X
 
 	  If unsure, say N.
 
-choice
-	prompt "Atmel SD/MMC Driver"
-	depends on AVR32 || ARCH_AT91
-	default MMC_ATMELMCI if AVR32
-	help
-	  Choose which driver to use for the Atmel MCI Silicon
-
 config MMC_AT91
 	tristate "AT91 SD/MMC Card Interface support"
-	depends on ARCH_AT91
+	depends on ARCH_AT91RM9200
 	help
 	  This selects the AT91 MCI controller.
 
@@ -287,7 +280,7 @@ config MMC_AT91
 
 config MMC_ATMELMCI
 	tristate "Atmel Multimedia Card Interface support"
-	depends on AVR32 || ARCH_AT91
+	depends on AVR32 || (ARCH_AT91 && !ARCH_AT91RM9200)
 	help
 	  This selects the Atmel Multimedia Card Interface driver. If
 	  you have an AT32 (AVR32) or AT91 platform with a Multimedia
@@ -295,8 +288,6 @@ config MMC_ATMELMCI
 
 	  If unsure, say N.
 
-endchoice
-
 config MMC_ATMELMCI_DMA
 	bool "Atmel MCI DMA support"
 	depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE
-- 
1.7.9



From nicolas.ferre at atmel.com  Thu Mar 15 11:57:16 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 16:57:16 +0100
Subject: [PATCH 0/6] AT91 drivers Kconfig cleanup
Message-ID: <cover.1331826095.git.nicolas.ferre@atmel.com>

This is a series which deals with AT91 drivers Kconfig entries. Its goal is
to remove too restrictive dependencies on SoC names.
This will allow to add support for newer SoC seamlessly.

One question remains: should I submit those patches through dedicated
sub-maintainer's git trees or can I queue the whole series in arm-soc?

Nicolas Ferre (6):
  dmaengine: Kconfig: fix Atmel at_hdmac entry
  mmc: Kconfig: remove choice between at91_mci and atmel-mci
  mmc: atmel-mci: remove the need for CONFIG_MMC_ATMELMCI_DMA
  rtc: Kconfig: remove dependency for AT91 rtc driver
  Input: Kconfig: remove dependency for atmel_tsadcc driver
  hwrng: Kconfig: remove dependency for atmel-rng driver

 drivers/char/hw_random/Kconfig    |    2 +-
 drivers/dma/Kconfig               |    5 ++---
 drivers/input/touchscreen/Kconfig |    4 ++--
 drivers/mmc/host/Kconfig          |   23 ++---------------------
 drivers/mmc/host/atmel-mci.c      |    2 --
 drivers/rtc/Kconfig               |    2 +-
 6 files changed, 8 insertions(+), 30 deletions(-)

Best regards,
-- 
1.7.9



From nicolas.ferre at atmel.com  Thu Mar 15 11:57:22 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 16:57:22 +0100
Subject: [PATCH 6/6] hwrng: Kconfig: remove dependency for atmel-rng driver
In-Reply-To: <cover.1331826095.git.nicolas.ferre@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
Message-ID: <c3455cec019bedacc6ff58cf8cd2ae25cdeb212f.1331826095.git.nicolas.ferre@atmel.com>

This will allow to select this driver for newer SoCs. Make sure to
keep dependency on HAVE_CLK to avoid breaking other machines.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/char/hw_random/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 0689bf6..b2402eb 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -62,7 +62,7 @@ config HW_RANDOM_AMD
 
 config HW_RANDOM_ATMEL
 	tristate "Atmel Random Number Generator support"
-	depends on HW_RANDOM && ARCH_AT91SAM9G45
+	depends on HW_RANDOM && HAVE_CLK
 	default HW_RANDOM
 	---help---
 	  This driver provides kernel-side support for the Random Number
-- 
1.7.9



From nicolas.ferre at atmel.com  Thu Mar 15 11:57:17 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 16:57:17 +0100
Subject: [PATCH 1/6] dmaengine: Kconfig: fix Atmel at_hdmac entry
In-Reply-To: <cover.1331826095.git.nicolas.ferre@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
Message-ID: <7cdf1e94a17a7d872cb1eeaef812aab25b3caf40.1331826095.git.nicolas.ferre@atmel.com>

Remove SoC dependency and make it generic for every Atmel ARM AT91. That will
allow to select this driver for newer chips. Keep dependency on AT91 because of
the use of an header file located in include/mach directory.
Modify the comment to reflect this.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/dma/Kconfig |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f1a2749..6d50f35 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -91,11 +91,10 @@ config DW_DMAC
 
 config AT_HDMAC
 	tristate "Atmel AHB DMA support"
-	depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
+	depends on ARCH_AT91
 	select DMA_ENGINE
 	help
-	  Support the Atmel AHB DMA controller.  This can be integrated in
-	  chips such as the Atmel AT91SAM9RL.
+	  Support the Atmel AHB DMA controller.
 
 config FSL_DMA
 	tristate "Freescale Elo and Elo Plus DMA support"
-- 
1.7.9



From nicolas.ferre at atmel.com  Thu Mar 15 11:57:21 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 16:57:21 +0100
Subject: [PATCH 5/6] Input: Kconfig: remove dependency for atmel_tsadcc driver
In-Reply-To: <cover.1331826095.git.nicolas.ferre@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
Message-ID: <531cf3ace390f3673a73792f15f9c7cd6aeb273d.1331826095.git.nicolas.ferre@atmel.com>

This will allow to select this driver for newer SoCs.
Keep dependency on AT91 because of the use of an header
file located in include/mach directory.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/input/touchscreen/Kconfig |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 4af2a18..3900c64 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -432,10 +432,10 @@ config TOUCHSCREEN_TOUCHWIN
 
 config TOUCHSCREEN_ATMEL_TSADCC
 	tristate "Atmel Touchscreen Interface"
-	depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
+	depends on ARCH_AT91
 	help
 	  Say Y here if you have a 4-wire touchscreen connected to the
-          ADC Controller on your Atmel SoC (such as the AT91SAM9RL).
+          ADC Controller on your Atmel SoC.
 
 	  If unsure, say N.
 
-- 
1.7.9



From arnd at arndb.de  Thu Mar 15 12:04:58 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 16:04:58 +0000
Subject: [GIT PULL][for v3.4] pull request from board-specific branch in
 arch-pxa
In-Reply-To: <CAN1soZyWmrzQzr0VHtrixdr2myv4ggJ1YBcS8OnuLJLOn2uVEQ@mail.gmail.com>
References: <CAN1soZyWmrzQzr0VHtrixdr2myv4ggJ1YBcS8OnuLJLOn2uVEQ@mail.gmail.com>
Message-ID: <201203151604.58969.arnd@arndb.de>

On Wednesday 14 March 2012, Haojian Zhuang wrote:
> First, please help to revert one commit 43de6a7dda6e9a7345e2 on
> arnd/pxa/board branch of arm-soc.git first. Since this commit is
> duplicated, and it's already merged into v3.3-rc7. I'm sorry on
> inconvenience.
> 
> commit 43de6a7dda6e9a7345e218e688f2092f991126f0
> Author: Haojian Zhuang <haojian.zhuang at marvell.com>
> Date:   Tue Feb 28 10:57:48 2012 +0800
> 
>     ARM: pxa: add dummy clock for pxa25x and pxa27x
> 

I need clarification on this:

I can see the clock was added in 389eda15e "ARM: pxa: add clk support in
gpio driver" as well as 7557c175f6 "ARM: pxa: add dummy clock for sa1100-rtc",
but removed in a55b5ada "Revert "ARM: pxa: add dummy clock for sa1100-rtc""
and then added again in bbdc818b2 "ARM: pxa: add dummy clock for pxa25x
and pxa27x". I want to make sure I'm not making the mess any bigger than
it already is. So you want the dummy clocks for pxa25x and pxa27x removed
again, never to come back, right?

	Arnd


From nicolas.ferre at atmel.com  Thu Mar 15 11:57:19 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 15 Mar 2012 16:57:19 +0100
Subject: [PATCH 3/6] mmc: atmel-mci: remove the need for
 CONFIG_MMC_ATMELMCI_DMA
In-Reply-To: <cover.1331826095.git.nicolas.ferre@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
Message-ID: <c7df6b7863557d95bb8457f5c2b4002ea44c86ff.1331826095.git.nicolas.ferre@atmel.com>

This Kconfig option is not needed anymore, so remove it.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 drivers/mmc/host/Kconfig     |   10 ----------
 drivers/mmc/host/atmel-mci.c |    2 --
 2 files changed, 0 insertions(+), 12 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 455a414..a6fc44a 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -288,16 +288,6 @@ config MMC_ATMELMCI
 
 	  If unsure, say N.
 
-config MMC_ATMELMCI_DMA
-	bool "Atmel MCI DMA support"
-	depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE
-	help
-	  Say Y here to have the Atmel MCI driver use a DMA engine to
-	  do data transfers and thus increase the throughput and
-	  reduce the CPU utilization.
-
-	  If unsure, say N.
-
 config MMC_IMX
 	tristate "Motorola i.MX Multimedia Card Interface support"
 	depends on ARCH_MX1
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index e4449a5..b5693fd 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -2164,10 +2164,8 @@ static int __exit atmci_remove(struct platform_device *pdev)
 	atmci_readl(host, ATMCI_SR);
 	clk_disable(host->mck);
 
-#ifdef CONFIG_MMC_ATMELMCI_DMA
 	if (host->dma.chan)
 		dma_release_channel(host->dma.chan);
-#endif
 
 	free_irq(platform_get_irq(pdev, 0), host);
 	iounmap(host->regs);
-- 
1.7.9



From linus.walleij at linaro.org  Thu Mar 15 12:05:44 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 15 Mar 2012 17:05:44 +0100
Subject: [PATCH 05/10] ARM: ux500: db8500: list most devices in the
 snowball device tree
In-Reply-To: <201203141359.46109.arnd@arndb.de>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-6-git-send-email-lee.jones@linaro.org>
 <201203141359.46109.arnd@arndb.de>
Message-ID: <CACRpkdanB7A55DV5TkADdWDmaySC4ZjZMgP74tF8WdN7gNQ7EA@mail.gmail.com>

On Wed, Mar 14, 2012 at 2:59 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 14 March 2012, Lee Jones wrote:
>> + ? ? ? ? ? ? ? pmu {
>> + ? ? ? ? ? ? ? ? ? ? ? compatible = "arm,cortex-a9-pmu";
>> + ? ? ? ? ? ? ? ? ? ? ? interrupts = <7>;
>> + ? ? ? ? ? ? ? };
>> +
>> + ? ? ? ? ? ? ? rtc at 80154000 {
>> + ? ? ? ? ? ? ? ? ? ? ? compatible = "stericsson,db8500-rtc";
>> + ? ? ? ? ? ? ? ? ? ? ? reg = <0x80154000 0x1000>;
>> + ? ? ? ? ? ? ? ? ? ? ? interrupts = <18>;
>> + ? ? ? ? ? ? ? };
>> +
>> + ? ? ? ? ? ? ? gpio0: gpio at 8012e000 {
>> + ? ? ? ? ? ? ? ? ? ? ? compatible = "stericsson,db8500-gpio",
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "stmicroelectronics,nomadik-gpio";
>> + ? ? ? ? ? ? ? ? ? ? ? reg = ?<0x8012e000 0x80>;
>> + ? ? ? ? ? ? ? ? ? ? ? interrupts = <119>;
>> + ? ? ? ? ? ? ? ? ? ? ? supports-sleepmode;
>> + ? ? ? ? ? ? ? ? ? ? ? gpio-controller;
>> + ? ? ? ? ? ? ? };
>
> Reading through it one more time, I realized that all the interrupt
> numbers are incorrect here and you fix them up one by one in the
> later patches. I think it would be more logical if you could just
> fix correct them here and then later just add the additional properties
> and enable the device.

Lee, fix up the IRQs and it's
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Thanks,
Linus Walleij


From plagnioj at jcrosoft.com  Thu Mar 15 11:54:47 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 15 Mar 2012 16:54:47 +0100
Subject: [PULL 01/02] AT91 DT2 pull request
Message-ID: <20120315155443.GB7757@game.jcrosoft.org>

Hi Arnd,

	please find a pull with DT update for AT91
	based on cleanup2 + DT previously pull

	with :

	 - OF: boolean
	 - NAND (with generic bining and at91 fixed)
	 - RAAM Controller
	 - i2c/gpio (binding + soc)
	 - PMC
	 - Reset Controller
	 - Shutdown Controller

The following changes since commit f75622f4679479d352d2fa83e0d84c6c13cfcb5f:

  ARM: at91: at91sam9x5cm/dt: add leds support (2012-03-01 22:34:22 +0800)

are available in the git repository at:
  git://github.com/at91linux/linux-at91.git at91-3.4-cleanup2-DT2

Jean-Christophe PLAGNIOL-VILLARD (19):
      ATMEL: fix nand ecc support
      mtd/atmel_nand: add on_flash_bbt to enable the use of On Flash BBT
      ARM: at91: enable on flash bbt for Atmel Reference and DT boards
      of: introduce helper to manage boolean
      of/mtd/nand: add generic bindings and helpers
      atmel/nand: add DT support
      ARM: at91: sam9x5 add nand support
      i2c/gpio: add DT support
      ARM: at91: sam9g20 add i2c DT support
      ARM: at91: usb_a9g20 add DT i2c support
      ARM: at91: sam9g45 add i2c DT support
      ARM: at91: sam9x5 add i2c DT support
      ARM: at91/dt: add Calao DAB-MMX daugther board support for USB-A9G20
      ARM: at91/dt: add specific DT soc init
      ARM: at91: add pmc DT support
      ARM: at91: always enable sam9 restart
      ARM: at91: add RSTC (Reset Controller) dt support
      ARM: at91: add ram controller DT support
      ARM: at91: add Shutdown Controller (SHDWC) DT support

 .../devicetree/bindings/arm/atmel-at91.txt         |   60 ++++++++
 .../devicetree/bindings/arm/atmel-pmc.txt          |   11 ++
 .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 ++++
 .../devicetree/bindings/mtd/atmel-nand.txt         |   41 +++++
 Documentation/devicetree/bindings/mtd/nand.txt     |    7 +
 arch/arm/boot/dts/at91sam9g20.dtsi                 |   49 ++++++
 arch/arm/boot/dts/at91sam9g25ek.dts                |    2 +-
 arch/arm/boot/dts/at91sam9g45.dtsi                 |   50 ++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts             |   36 +++++-
 arch/arm/boot/dts/at91sam9x5.dtsi                  |   74 +++++++++
 arch/arm/boot/dts/at91sam9x5cm.dtsi                |   45 ++++++
 arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi           |   96 ++++++++++++
 arch/arm/boot/dts/usb_a9g20.dts                    |   64 ++++++++-
 arch/arm/configs/at91sam9g20_defconfig             |    3 +
 arch/arm/mach-at91/Kconfig                         |   10 +-
 arch/arm/mach-at91/at91sam9x5.c                    |   12 --
 arch/arm/mach-at91/board-afeb-9260v1.c             |    1 +
 arch/arm/mach-at91/board-cam60.c                   |    1 +
 arch/arm/mach-at91/board-cpu9krea.c                |    1 +
 arch/arm/mach-at91/board-dt.c                      |   57 +-------
 arch/arm/mach-at91/board-kb9202.c                  |    1 +
 arch/arm/mach-at91/board-neocore926.c              |    1 +
 arch/arm/mach-at91/board-qil-a9260.c               |    2 +
 arch/arm/mach-at91/board-rm9200dk.c                |    2 +
 arch/arm/mach-at91/board-sam9-l9260.c              |    1 +
 arch/arm/mach-at91/board-sam9260ek.c               |    2 +
 arch/arm/mach-at91/board-sam9261ek.c               |    2 +
 arch/arm/mach-at91/board-sam9263ek.c               |    2 +
 arch/arm/mach-at91/board-sam9g20ek.c               |    2 +
 arch/arm/mach-at91/board-sam9m10g45ek.c            |    2 +
 arch/arm/mach-at91/board-sam9rlek.c                |    2 +
 arch/arm/mach-at91/board-snapper9260.c             |    1 +
 arch/arm/mach-at91/board-stamp9g20.c               |    1 +
 arch/arm/mach-at91/board-usb-a926x.c               |    2 +
 arch/arm/mach-at91/board-yl-9200.c                 |    1 +
 arch/arm/mach-at91/clock.c                         |   56 +++++++-
 arch/arm/mach-at91/generic.h                       |    2 +
 arch/arm/mach-at91/include/mach/at91_shdwc.h       |    4 +-
 arch/arm/mach-at91/include/mach/at91sam9x5.h       |    5 -
 arch/arm/mach-at91/include/mach/board.h            |   15 +--
 arch/arm/mach-at91/pm.c                            |   13 --
 arch/arm/mach-at91/setup.c                         |  158 ++++++++++++++++++++
 arch/avr32/boards/atngw100/setup.c                 |    1 +
 arch/avr32/boards/atstk1000/atstk1002.c            |    1 +
 arch/avr32/mach-at32ap/include/mach/board.h        |   13 +--
 drivers/i2c/busses/i2c-gpio.c                      |   94 +++++++++---
 drivers/mtd/nand/atmel_nand.c                      |  136 ++++++++++++-----
 drivers/of/Kconfig                                 |    4 +
 drivers/of/Makefile                                |    1 +
 drivers/of/of_mtd.c                                |   85 +++++++++++
 include/linux/of.h                                 |   16 ++
 include/linux/of_mtd.h                             |   19 +++
 include/linux/platform_data/atmel.h                |   27 ++++
 53 files changed, 1139 insertions(+), 187 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-pmc.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/atmel-nand.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/nand.txt
 create mode 100644 arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
 create mode 100644 drivers/of/of_mtd.c
 create mode 100644 include/linux/of_mtd.h
 create mode 100644 include/linux/platform_data/atmel.h

Best Regards,
J.


From linus.walleij at linaro.org  Thu Mar 15 12:06:59 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 15 Mar 2012 17:06:59 +0100
Subject: [PATCH 06/10] ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt
 Controller) in Device Tree
In-Reply-To: <1331730306-11461-7-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-7-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdabqkfJSe4ef27ZrRYtoczLEO5bdqEKLYVOcUcQmrUcWg@mail.gmail.com>

On Wed, Mar 14, 2012 at 2:05 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This enables the embedded GIC on all u8500 based hardware using DT.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From plagnioj at jcrosoft.com  Thu Mar 15 11:56:12 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 15 Mar 2012 16:56:12 +0100
Subject: [PATCH 1/5 v5] i2c/gpio: add DT support
In-Reply-To: <1331642024-19869-1-git-send-email-plagnioj@jcrosoft.com>
References: <1331642024-19869-1-git-send-email-plagnioj@jcrosoft.com>
Message-ID: <1331826972-14386-1-git-send-email-plagnioj@jcrosoft.com>

To achieve DT support, we need to populate a custom platform_data in a
private struct from DT information. To simplify code, the adapter and
algorithm are also put into the private struct.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Acked-by: Wolfram Sang <w.sang at pengutronix.de>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 +++++++
 drivers/i2c/busses/i2c-gpio.c                      |   94 +++++++++++++++----
 2 files changed, 106 insertions(+), 20 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt

diff --git a/Documentation/devicetree/bindings/gpio/gpio_i2c.txt b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
new file mode 100644
index 0000000..4f8ec94
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio_i2c.txt
@@ -0,0 +1,32 @@
+Device-Tree bindings for i2c gpio driver
+
+Required properties:
+	- compatible = "i2c-gpio";
+	- gpios: sda and scl gpio
+
+
+Optional properties:
+	- i2c-gpio,sda-open-drain: sda as open drain
+	- i2c-gpio,scl-open-drain: scl as open drain
+	- i2c-gpio,scl-output-only: scl as output only
+	- i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform)
+	- i2c-gpio,timeout-ms: timeout to get data
+
+Example nodes:
+
+i2c at 0 {
+	compatible = "i2c-gpio";
+	gpios = <&pioA 23 0 /* sda */
+		 &pioA 24 0 /* scl */
+		>;
+	i2c-gpio,sda-open-drain;
+	i2c-gpio,scl-open-drain;
+	i2c-gpio,delay-us = <2>;	/* ~100 kHz */
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	rv3029c2 at 56 {
+		compatible = "rv3029c2";
+		reg = <0x56>;
+	};
+};
diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
index a651779..c0330a4 100644
--- a/drivers/i2c/busses/i2c-gpio.c
+++ b/drivers/i2c/busses/i2c-gpio.c
@@ -14,8 +14,15 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/of_i2c.h>
 
-#include <asm/gpio.h>
+struct i2c_gpio_private_data {
+	struct i2c_adapter adap;
+	struct i2c_algo_bit_data bit_data;
+	struct i2c_gpio_platform_data pdata;
+};
 
 /* Toggle SDA by changing the direction of the pin */
 static void i2c_gpio_setsda_dir(void *data, int state)
@@ -78,24 +85,62 @@ static int i2c_gpio_getscl(void *data)
 	return gpio_get_value(pdata->scl_pin);
 }
 
+static int __devinit of_i2c_gpio_probe(struct device_node *np,
+			     struct i2c_gpio_platform_data *pdata)
+{
+	u32 reg;
+
+	if (of_gpio_count(np) < 2)
+		return -ENODEV;
+
+	pdata->sda_pin = of_get_gpio(np, 0);
+	pdata->scl_pin = of_get_gpio(np, 1);
+
+	if (!gpio_is_valid(pdata->sda_pin) || !gpio_is_valid(pdata->scl_pin)) {
+		pr_err("%s: invalid GPIO pins, sda=%d/scl=%d\n",
+		       np->full_name, pdata->sda_pin, pdata->scl_pin);
+		return -ENODEV;
+	}
+
+	of_property_read_u32(np, "i2c-gpio,delay-us", &pdata->udelay);
+
+	if (!of_property_read_u32(np, "i2c-gpio,timeout-ms", &reg))
+		pdata->timeout = msecs_to_jiffies(reg);
+
+	pdata->sda_is_open_drain =
+		of_property_read_bool(np, "i2c-gpio,sda-open-drain");
+	pdata->scl_is_open_drain =
+		of_property_read_bool(np, "i2c-gpio,scl-open-drain");
+	pdata->scl_is_output_only =
+		of_property_read_bool(np, "i2c-gpio,scl-output-only");
+
+	return 0;
+}
+
 static int __devinit i2c_gpio_probe(struct platform_device *pdev)
 {
+	struct i2c_gpio_private_data *priv;
 	struct i2c_gpio_platform_data *pdata;
 	struct i2c_algo_bit_data *bit_data;
 	struct i2c_adapter *adap;
 	int ret;
 
-	pdata = pdev->dev.platform_data;
-	if (!pdata)
-		return -ENXIO;
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	adap = &priv->adap;
+	bit_data = &priv->bit_data;
+	pdata = &priv->pdata;
 
-	ret = -ENOMEM;
-	adap = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
-	if (!adap)
-		goto err_alloc_adap;
-	bit_data = kzalloc(sizeof(struct i2c_algo_bit_data), GFP_KERNEL);
-	if (!bit_data)
-		goto err_alloc_bit_data;
+	if (pdev->dev.of_node) {
+		ret = of_i2c_gpio_probe(pdev->dev.of_node, pdata);
+		if (ret)
+			return ret;
+	} else {
+		if (!pdev->dev.platform_data)
+			return -ENXIO;
+		memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
+	}
 
 	ret = gpio_request(pdata->sda_pin, "sda");
 	if (ret)
@@ -143,6 +188,7 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
 	adap->algo_data = bit_data;
 	adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 	adap->dev.parent = &pdev->dev;
+	adap->dev.of_node = pdev->dev.of_node;
 
 	/*
 	 * If "dev->id" is negative we consider it as zero.
@@ -154,7 +200,9 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_add_bus;
 
-	platform_set_drvdata(pdev, adap);
+	of_i2c_register_devices(adap);
+
+	platform_set_drvdata(pdev, priv);
 
 	dev_info(&pdev->dev, "using pins %u (SDA) and %u (SCL%s)\n",
 		 pdata->sda_pin, pdata->scl_pin,
@@ -168,34 +216,40 @@ err_add_bus:
 err_request_scl:
 	gpio_free(pdata->sda_pin);
 err_request_sda:
-	kfree(bit_data);
-err_alloc_bit_data:
-	kfree(adap);
-err_alloc_adap:
 	return ret;
 }
 
 static int __devexit i2c_gpio_remove(struct platform_device *pdev)
 {
+	struct i2c_gpio_private_data *priv;
 	struct i2c_gpio_platform_data *pdata;
 	struct i2c_adapter *adap;
 
-	adap = platform_get_drvdata(pdev);
-	pdata = pdev->dev.platform_data;
+	priv = platform_get_drvdata(pdev);
+	adap = &priv->adap;
+	pdata = &priv->pdata;
 
 	i2c_del_adapter(adap);
 	gpio_free(pdata->scl_pin);
 	gpio_free(pdata->sda_pin);
-	kfree(adap->algo_data);
-	kfree(adap);
 
 	return 0;
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id i2c_gpio_dt_ids[] = {
+	{ .compatible = "i2c-gpio", },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, i2c_gpio_dt_ids);
+#endif
+
 static struct platform_driver i2c_gpio_driver = {
 	.driver		= {
 		.name	= "i2c-gpio",
 		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(i2c_gpio_dt_ids),
 	},
 	.probe		= i2c_gpio_probe,
 	.remove		= __devexit_p(i2c_gpio_remove),
-- 
1.7.7



From linus.walleij at linaro.org  Thu Mar 15 12:08:42 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 15 Mar 2012 17:08:42 +0100
Subject: [PATCH 08/10] ARM: ux500: Enable PL011 AMBA UART Controller for
 Device Tree
In-Reply-To: <1331730306-11461-9-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-9-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZt0zKy+m+e+MoFnmn6TLxi6DtX9HsQ1CSiwz3BnbRLuA@mail.gmail.com>

On Wed, Mar 14, 2012 at 2:05 PM, Lee Jones <lee.jones at linaro.org> wrote:

> Enables the 3 UARTs found on a u8500 using DT.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Auxdata and all in place, perfect.
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From linus.walleij at linaro.org  Thu Mar 15 12:09:29 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 15 Mar 2012 17:09:29 +0100
Subject: [PATCH 09/10] ARM: ux500: Enable PL310 Level 2 Cache Controller
 in Device Tree
In-Reply-To: <1331730306-11461-10-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-10-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdZ1pnXyYUc5sZifCx7oMZCmOesvYNOKAiWf8P7Jwvv-Xg@mail.gmail.com>

On Wed, Mar 14, 2012 at 2:05 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This provides PL310 Level 2 Cache Controller Device Tree
> support for all u8500 based devices.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From arnd at arndb.de  Thu Mar 15 12:10:44 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 16:10:44 +0000
Subject: [GIT PULL][for v3.4] pull request from board-specific branch in
 arch-pxa
In-Reply-To: <CAN1soZyWmrzQzr0VHtrixdr2myv4ggJ1YBcS8OnuLJLOn2uVEQ@mail.gmail.com>
References: <CAN1soZyWmrzQzr0VHtrixdr2myv4ggJ1YBcS8OnuLJLOn2uVEQ@mail.gmail.com>
Message-ID: <201203151610.44491.arnd@arndb.de>

On Wednesday 14 March 2012, Haojian Zhuang wrote:
> Second, please help to pull these commits from arch-pxa git tree.
> 
> The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
> 
>   Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)
> 
> are available in the git repository at:
>   git://github.com/hzhuang1/linux.git board-specific
> 
> Paul Parsons (3):
>       ARM: pxa/hx4700: Remove unwanted request for GPIO105
>       ARM: pxa/hx4700: Reduce sleep mode battery discharge by 35%
>       pxa/hx4700: Remove pcmcia platform_device structure
> 
>  arch/arm/mach-pxa/hx4700.c                  |   17 ++---------------
>  arch/arm/mach-pxa/include/mach/mfp-pxa27x.h |    2 ++
>  2 files changed, 4 insertions(+), 15 deletions(-)
> 

Pulled into next/boards,

Thanks!

	ARnd


From linus.walleij at linaro.org  Thu Mar 15 12:11:45 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 15 Mar 2012 17:11:45 +0100
Subject: [PATCH 10/10] ARM: ux500: Enable PL022 SSP Controller in Device
 Tree
In-Reply-To: <1331730306-11461-11-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-11-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdaYDjyYDo9HCkHSyQrQuQP3Hp7TUZKTCXOseeoLxXh6Lg@mail.gmail.com>

On Wed, Mar 14, 2012 at 2:05 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This SSP Controller supports a number of serial communication methods.
>
> Namely:
>
> /**
> ?* enum ssp_interface - interfaces allowed for this SSP Controller
> ?* @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
> ?* @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
> ?* interface
> ?* @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
> ?* interface
> ?* @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
> ?* &STn8815 only)
> ?*/
>
> ... and as such cannot be registered using of_register_spi_devices.
> Instead it can be registered simply as a primecell device.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Why is the commit message all about what the patch cannot do rather
than on what it does, anyway, begin with stating what you do and
its:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From arnd at arndb.de  Thu Mar 15 12:13:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 16:13:04 +0000
Subject: [GIT PULL][for 3.4] pull request from fixes-non-critical branch
 in arch-pxa git
In-Reply-To: <CAN1soZy5LR2vFF4BNgiuUcWubCdt1+a+nEwVM24WavOR8oJRkA@mail.gmail.com>
References: <CAN1soZy5LR2vFF4BNgiuUcWubCdt1+a+nEwVM24WavOR8oJRkA@mail.gmail.com>
Message-ID: <201203151613.04323.arnd@arndb.de>

On Wednesday 14 March 2012, Haojian Zhuang wrote:
> Please help to pull commits from fixes-non-critical branch in arch-pxa git tree.
> 
> The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
> 
>   Linux 3.3-rc7 (2012-03-10 13:49:52 -0800)
> 
> are available in the git repository at:
>   git://github.com/hzhuang1/linux.git fixes-non-critical
> 

Pulled into next/maintainers branch. This one will be sent right after the
next/fixes-non-critical branch.

Thanks,

	Arnd


From linus.walleij at linaro.org  Thu Mar 15 12:13:45 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 15 Mar 2012 17:13:45 +0100
Subject: [PATCH 10/10] ARM: ux500: Enable PL022 SSP Controller in Device
 Tree
In-Reply-To: <201203141405.50005.arnd@arndb.de>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-11-git-send-email-lee.jones@linaro.org>
 <201203141405.50005.arnd@arndb.de>
Message-ID: <CACRpkdYwwavBCk_P2oqfQOYNTGkucdHfZjNgWgwygx-f86==1A@mail.gmail.com>

On Wed, Mar 14, 2012 at 3:05 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> For this to be functional, I think you also need a way for the SPI
> controller to find the child devices from the device tree, but I
> don't see how ux500 currently does it, or how it should be done.

It will be functional as long as you use the onholy hybrid of supplying
the SPI devices (like the I2C devices!) from the board files instead.

But both drivers/spi/spi-pl022.c and drivers/i2c/busses/i2c-nomadik.c
needs patches to register child devices from DT.

Yours,
Linus Walleij


From broonie at opensource.wolfsonmicro.com  Thu Mar 15 12:24:13 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 15 Mar 2012 16:24:13 +0000
Subject: [alsa-devel] [PATCH v3 09/11] ASoC: fsl: remove the fatal error
 checking on codec-handle
In-Reply-To: <CA+7tXiiJyLAm1ytyqQYgbJ_roUtXwxqhFWKEBk+4jY_HV5V8Zg@mail.gmail.com>
References: <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315130253.GA6065@S2101-09.ap.freescale.net>
 <4F61F080.4090800@freescale.com>
 <20120315142115.GB6065@S2101-09.ap.freescale.net>
 <CA+7tXig6=gz8utcnV8qUs6=JnwEz8+tqc-57v-xNcYcK_AAHXw@mail.gmail.com>
 <CA+7tXiiJyLAm1ytyqQYgbJ_roUtXwxqhFWKEBk+4jY_HV5V8Zg@mail.gmail.com>
Message-ID: <20120315162413.GO3138@opensource.wolfsonmicro.com>

On Thu, Mar 15, 2012 at 11:57:52AM -0400, Trent Piepho wrote:

> which caused text window in gmail to become deselected, which caused a
> subsequent enter to send the email rather than creating a new line.

> For esai, would you add something like:
>     esai-controller = <&esai1>;
>     esai-audio-codec = <&sgtl5000_3>;

> That seems rather ugly to me.

None of these examples seem particularly to reflect realistic audio
hardware; they're more describing a board with multiple distinct audio
subsystems on it than a single card.  Remember that nothing at all is
fixed about how the card binding works internally, the card driver is
free to pick any binding that makes sense for the systems it supports.
Shoehorning every possible card into the same binding is definitely a
really bad idea.

> It seems to me in most device bindings where one piece of hardware is
> attached to another, than the one upstream has in its binding a
> phandle to the one downstream.  But here we have a third binding with
> two lists of devices and an implied link between devices in
> corresponding positions in the lists.  Does any other device binding
> work like that?

There's no upstream and downstream here, really.  But like I say none of
this looks like realistic hardware anyway.

*Please* go and read the previous discussions of audio bindings for
SoCs, while it's more understandable with people who haven't been
involved before its still tiresome to have to go back to square one.
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From b-cousson at ti.com  Thu Mar 15 12:30:49 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Thu, 15 Mar 2012 17:30:49 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203150922.06379.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <201203150922.06379.arnd@arndb.de>
Message-ID: <4F621939.9040906@ti.com>

On 3/15/2012 10:22 AM, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Nicolas Ferre wrote:
>> Add some basic helpers to retrieve a DMA controller device_node and the
>> DMA request specifications. By making DMA controllers register a generic
>> translation function, we allow the management of any type of DMA requests
>> specification.
>> The void * output of an of_dma_xlate() function that will be implemented
>> by the DMA controller can carry any type of "dma-request" argument.
>>
>> The DMA client will search its associated DMA controller in the list and
>> call the registered of_dam_xlate() function to retrieve the request values.
>>
>> One simple xlate function is provided for the "single number" type of
>> request binding.
>>
>> This implementation is independent from dmaengine so it can also be used
>> by legacy drivers.
>>
>> For legacy reason another API will export the DMA request number into a
>> Linux resource of type IORESOURCE_DMA.
>
> This looks very good. I missed the first version of this patch, but was
> thinking of very similar bindings.
>
>> +Client drivers should specify the DMA request property using a phandle to
>> +the controller. If needed, the DMA request identity on that controller is then
>> +added followed by optional request specifications.
>> +
>> +Required property:
>> +    - dma-request: List of phandle + dma-request + request specifications,
>> +      one group per request "line".
>> +Optional property:
>> +    - dma-request-names: list of strings in the same order as the dma-request
>> +      in the dma-request property.
>> +
>> +
>> +Example:
>> +
>> +	i2c1: i2c at 1 {
>> +		...
>> +		dma-request =<&sdma 2&sdma 3>;
>> +		dma-request-names = "tx", "rx";
>> +		...
>> +	};
>
> This is slightly different from how the proposed pwm binding works that
> Thierry is working on, which uses an arbitrary property name instead of
> requiring the use of a specific property but then allowing to give names
> in another property.
>
> I don't care much which way it's done, but please try to agree on one
> approach that is used for both.
>
> The one you have here is already used by reg and irq, while the other
> one is used in gpio.

This was done like IRQ on purpose, because an Interrupt ReQuest line and 
a DMA Request line are really similar for the HW point of view at IP level.
I'm not sure what Thierry have done for pwm, but I thing that having the 
same scheme for reg, irq and dma was what we agreed with Grant during 
Plumbers.

GPIO scheme will be probably good enough as well, but the idea was to be 
consistent in the binding for similar information.

Regards,
Benoit


From dave.martin at linaro.org  Thu Mar 15 12:32:08 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 15 Mar 2012 16:32:08 +0000
Subject: [PATCH 0/4] ARM: opcodes: Facilitate custom opcode injection
Message-ID: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>

Since my "uniform assembler" series had some problems and did not
meet with widespread agreement, this can't be used as a basis for a
mechanism to safely inject custom instruction opcodes (which was my
immediate reason for writing those patchse).

This series follows a more conventional approach to achieve the
goal for safe opcode injection across all kernel endianness and
instruction set configurations.

I have made best efforts to verify that these patches do the right
thing for big-endian configurations, but review/testing from people
who are actively working with big-endian targets would be
appreciated.  There's no code in the kernel using these macros yet,
but you can experiment with the __HVC() macro added by the final
patch.  If this disassembles correctly in vmlinux (see below), then
the macros should be safe for your configuration.


Note that for BE8 targets, you _will_ get weird-looking instruction
data in your .o files:  because the ".inst" family of assembler
directives is relatively new I use data directives instead.  This
means that the data for those directives has to be pre-swapped by
the opcode injection macros, whereas _instruction_ data should get
byteswapped by the linker in the final link (with ld --be8).  Using
data directives brings some complexity, but it is the only way to
ensure compatibility with older assembler versions.

To check correctness, you should therefore review the final linker
output (vmlinux) if you want to be certain what the final
instruction stream looks like.  You may need to strip data mapping
symbols (strip -N'$d') from vmlinux in order for the injected
instructions to be disassembled properly -- note that this has no
effect on the run-time meaning of the image.

For BE32 the situation is simpler again, because like LE, BE32 uses
the same endianness for data and instructions.

Dave Martin (4):
  ARM: opcodes: Don't define the thumb32 byteswapping macros for BE32
  ARM: opcodes: Make opcode byteswapping macros assembly-compatible
  ARM: opcodes: Add helpers for emitting custom opcodes
  ARM: opcodes: Opcode definitions for the Virtualization Extensions

 arch/arm/include/asm/opcodes-virt.h |   29 ++++++
 arch/arm/include/asm/opcodes.h      |  181 ++++++++++++++++++++++++++++++++---
 2 files changed, 195 insertions(+), 15 deletions(-)
 create mode 100644 arch/arm/include/asm/opcodes-virt.h

-- 
1.7.4.1



From dave.martin at linaro.org  Thu Mar 15 12:32:09 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 15 Mar 2012 16:32:09 +0000
Subject: [PATCH 1/4] ARM: opcodes: Don't define the thumb32 byteswapping
 macros for BE32
In-Reply-To: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
References: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1331829132-9762-2-git-send-email-dave.martin@linaro.org>

The existing __mem_to_opcode_thumb32() is incorrect for BE32
platforms.  However, these don't support Thumb-2 kernels, so this
option is not so relevant for those platforms anyway.

This operation is complicated by the lack of unaligned memory
access support prior to ARMv6.

Rather than provide a "working" macro which will probably won't get
used (or worse, will get misused), this patch removes the macro for
BE32 kernels.  People manipulating Thumb opcodes prior to ARMv6
should almost certainly be splitting these operations into
halfwords anyway, using __opcode_thumb32_{first,second,compose}()
and the 16-bit opcode transformations.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
---
 arch/arm/include/asm/opcodes.h |   15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 19c48de..cf877c8 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -49,18 +49,31 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 #include <linux/swab.h>
 
 #ifdef CONFIG_CPU_ENDIAN_BE8
+
 #define __opcode_to_mem_arm(x) swab32(x)
 #define __opcode_to_mem_thumb16(x) swab16(x)
 #define __opcode_to_mem_thumb32(x) swahb32(x)
-#else
+
+#else /* ! CONFIG_CPU_ENDIAN_BE8 */
+
 #define __opcode_to_mem_arm(x) ((u32)(x))
 #define __opcode_to_mem_thumb16(x) ((u16)(x))
+#ifndef CONFIG_CPU_ENDIAN_BE32
+/*
+ * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
+ * work in all cases, due to alignment constraints.  For now, a correct
+ * version is not proivided for BE32.
+ */
 #define __opcode_to_mem_thumb32(x) swahw32(x)
 #endif
 
+#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
+
 #define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
 #define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
 #define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
+#endif
 
 /* Operations specific to Thumb opcodes */
 
-- 
1.7.4.1



From dave.martin at linaro.org  Thu Mar 15 12:32:10 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 15 Mar 2012 16:32:10 +0000
Subject: [PATCH 2/4] ARM: opcodes: Make opcode byteswapping macros
 assembly-compatible
In-Reply-To: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
References: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1331829132-9762-3-git-send-email-dave.martin@linaro.org>

Most of the existing macros don't work with assembler, due to the
use of type casts and C functions from <linux/swab.h>.

This patch abstracts out those operations and provides simple
explicit versions for use in assembly code.

__opcode_is_thumb32() and __opcode_is_thumb16() are also converted
to do bitmask-based testing to avoid confusion if these are used in
assembly code (the assembler typically treats all arithmetic values
as signed).

Signed-off-by: Dave Martin <dave.martin at linaro.org>
---
 arch/arm/include/asm/opcodes.h |   97 +++++++++++++++++++++++++++++++++------
 1 files changed, 82 insertions(+), 15 deletions(-)

diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index cf877c8..32730a8 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -19,6 +19,33 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 
 
 /*
+ * Assembler opcode byteswap helpers.
+ * These are only intended for use by this header: don't use them directly,
+ * because they will be suboptimal in most cases.
+ */
+#define ___asm_opcode_swab32(x) (	\
+	  (((x) << 24) & 0xFF000000)	\
+	| (((x) <<  8) & 0x00FF0000)	\
+	| (((x) >>  8) & 0x0000FF00)	\
+	| (((x) >> 24) & 0x000000FF)	\
+)
+#define ___asm_opcode_swab16(x) (	\
+	  (((x) << 8) & 0xFF00)		\
+	| (((x) >> 8) & 0x00FF)		\
+)
+#define ___asm_opcode_swahb32(x) (	\
+	  (((x) << 8) & 0xFF00FF00)	\
+	| (((x) >> 8) & 0x00FF00FF)	\
+)
+#define ___asm_opcode_swahw32(x) (	\
+	  (((x) << 16) & 0xFFFF0000)	\
+	| (((x) >> 16) & 0x0000FFFF)	\
+)
+#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
+#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
+
+
+/*
  * Opcode byteswap helpers
  *
  * These macros help with converting instructions between a canonical integer
@@ -41,30 +68,58 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
  * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
  * represent any valid Thumb-2 instruction.  For this range,
  * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
+ *
+ * The ___asm variants are intended only for use by this header, in situations
+ * involving inline assembler.  For .S files, the normal __opcode_*() macros
+ * should do the right thing.
  */
+#ifdef __ASSEMBLY__
 
-#ifndef __ASSEMBLY__
+#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
+#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
+#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
+#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
+#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
+#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
+
+#else /* ! __ASSEMBLY__ */
 
 #include <linux/types.h>
 #include <linux/swab.h>
 
+#define ___opcode_swab32(x) swab32(x)
+#define ___opcode_swab16(x) swab16(x)
+#define ___opcode_swahb32(x) swahb32(x)
+#define ___opcode_swahw32(x) swahw32(x)
+#define ___opcode_identity32(x) ((u32)(x))
+#define ___opcode_identity16(x) ((u16)(x))
+
+#endif /* ! __ASSEMBLY__ */
+
+
 #ifdef CONFIG_CPU_ENDIAN_BE8
 
-#define __opcode_to_mem_arm(x) swab32(x)
-#define __opcode_to_mem_thumb16(x) swab16(x)
-#define __opcode_to_mem_thumb32(x) swahb32(x)
+#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
+#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
 
 #else /* ! CONFIG_CPU_ENDIAN_BE8 */
 
-#define __opcode_to_mem_arm(x) ((u32)(x))
-#define __opcode_to_mem_thumb16(x) ((u16)(x))
+#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
 #ifndef CONFIG_CPU_ENDIAN_BE32
 /*
  * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
  * work in all cases, due to alignment constraints.  For now, a correct
  * version is not proivided for BE32.
  */
-#define __opcode_to_mem_thumb32(x) swahw32(x)
+#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
 #endif
 
 #endif /* ! CONFIG_CPU_ENDIAN_BE8 */
@@ -78,15 +133,27 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 /* Operations specific to Thumb opcodes */
 
 /* Instruction size checks: */
-#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL)
-#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL)
+#define __opcode_is_thumb32(x) (		\
+	   ((x) & 0xF8000000) == 0xE8000000	\
+	|| ((x) & 0xF0000000) == 0xF0000000	\
+)
+#define __opcode_is_thumb16(x) (					\
+	   ((x) & 0xFFFF0000) == 0					\
+	&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)	\
+)
 
 /* Operations to construct or split 32-bit Thumb instructions: */
-#define __opcode_thumb32_first(x) ((u16)((x) >> 16))
-#define __opcode_thumb32_second(x) ((u16)(x))
-#define __opcode_thumb32_compose(first, second) \
-	(((u32)(u16)(first) << 16) | (u32)(u16)(second))
-
-#endif /* __ASSEMBLY__ */
+#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
+#define __opcode_thumb32_second(x) (___opcode_identity16(x))
+#define __opcode_thumb32_compose(first, second) (			\
+	  (___opcode_identity32(___opcode_identity16(first)) << 16)	\
+	| ___opcode_identity32(___opcode_identity16(second))		\
+)
+#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
+#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
+#define ___asm_opcode_thumb32_compose(first, second) (			    \
+	  (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
+	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
+)
 
 #endif /* __ASM_ARM_OPCODES_H */
-- 
1.7.4.1



From dave.martin at linaro.org  Thu Mar 15 12:32:11 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 15 Mar 2012 16:32:11 +0000
Subject: [PATCH 3/4] ARM: opcodes: Add helpers for emitting custom opcodes
In-Reply-To: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
References: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1331829132-9762-4-git-send-email-dave.martin@linaro.org>

This patch adds some __inst_() macros for injecting custom opcodes
in assembler (both inline and in .S files).  They should make it
easier and cleaner to get things right in little-/big-
endian/ARM/Thumb-2 kernels without a lot of #ifdefs.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
---
 arch/arm/include/asm/opcodes.h |   69 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 69 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 32730a8..50ef0be 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -156,4 +156,73 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
 )
 
+/*
+ * Opcode injection helpers
+ *
+ * In rare cases it is necessary to assemble an opcode which the
+ * assembler does not support directly, or which would normally be
+ * rejected because of the CFLAGS or AFLAGS used to build the affected
+ * file.
+ *
+ * Before using these macros, consider carefully whether it is feasible
+ * instead to change the build flags for your file, or whether it really
+ * makes sense to support old assembler versions when building that
+ * particular kernel feature.
+ *
+ * The macros defined here should only be used where there is no viable
+ * alternative.
+ *
+ *
+ * __inst_arm(x): emit the specified ARM opcode
+ * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
+ * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
+ *
+ * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
+ *	16-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
+ *	32-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ *
+ * Note that using these macros directly is poor practice.  Instead, you
+ * should use them to define human-readable wrapper macros to encode the
+ * instructions that you care about.  In code which might run on ARMv7 or
+ * above, you can usually use the __inst_arm_thumb{16,32} macros to
+ * specify the ARM and Thumb alternatives at the same time.  This ensures
+ * that the correct opcode gets emitted depending on the instruction set
+ * used for the kernel build.
+ */
+#include <linux/stringify.h>
+
+#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
+#define __inst_thumb32(x) ___inst_thumb32(				\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),	\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))	\
+)
+#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
+
+#ifdef CONFIG_THUMB2_KERNEL
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
+	__inst_thumb16(thumb_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
+	__inst_thumb32(thumb_opcode)
+#else
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#endif
+
+/* Helpers for the helpers.  Don't use these directly. */
+#ifdef __ASSEMBLY__
+#define ___inst_arm(x) .long x
+#define ___inst_thumb16(x) .short x
+#define ___inst_thumb32(first, second) .short first, second
+#else
+#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
+#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
+#define ___inst_thumb32(first, second) \
+	".short " __stringify(first) ", " __stringify(second) "\n\t"
+#endif
+
 #endif /* __ASM_ARM_OPCODES_H */
-- 
1.7.4.1



From dave.martin at linaro.org  Thu Mar 15 12:32:12 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Thu, 15 Mar 2012 16:32:12 +0000
Subject: [PATCH 4/4] ARM: opcodes: Opcode definitions for the Virtualization
 Extensions
In-Reply-To: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
References: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1331829132-9762-5-git-send-email-dave.martin@linaro.org>

For now, this patch just adds a definition for the HVC instruction.
More can be added here later, as needed.

Now that we have a real example of how to use the opcode injection
macros properly, this patch also adds a cross-reference from the
explanation in opcodes.h (since without an example, figuring out
how to use the macros is not that easy).

Signed-off-by: Dave Martin <dave.martin at linaro.org>
---
 arch/arm/include/asm/opcodes-virt.h |   29 +++++++++++++++++++++++++++++
 arch/arm/include/asm/opcodes.h      |    2 ++
 2 files changed, 31 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/opcodes-virt.h

diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
new file mode 100644
index 0000000..b85665a
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-virt.h
@@ -0,0 +1,29 @@
+/*
+ * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
+ * Copyright (C) 2012  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARM_OPCODES_VIRT_H
+#define __ASM_ARM_OPCODES_VIRT_H
+
+#include <asm/opcodes.h>
+
+#define __HVC(imm16) __inst_arm_thumb32(				\
+	0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),	\
+	0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)	\
+)
+
+#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 50ef0be..89ff5b9 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -193,6 +193,8 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
  * specify the ARM and Thumb alternatives at the same time.  This ensures
  * that the correct opcode gets emitted depending on the instruction set
  * used for the kernel build.
+ *
+ * Look at opcodes-virt.h for an example of how to use these macros.
  */
 #include <linux/stringify.h>
 
-- 
1.7.4.1



From arnd at arndb.de  Thu Mar 15 12:39:38 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 16:39:38 +0000
Subject: linux-next: build failure after merge of the final tree (arm-soc
 tree related)
In-Reply-To: <20120315002020.GA16189@titan.lakedaemon.net>
References: <20120315105901.7b10c9f4de9374a613436988@canb.auug.org.au>
 <20120315002020.GA16189@titan.lakedaemon.net>
Message-ID: <201203151639.38223.arnd@arndb.de>

On Thursday 15 March 2012, Jason Cooper wrote:
> That's my mistake.  I did a pull request for the wrong branch.  Olof,
> could you please drop the offending branch and I'll submit a new pull
> request once I have a chance to test Arnd's irq patch?

I reverted this in the for-next branch for now. The two initial patches
from the kirkwood/board branch are still present.

	Arnd


From jean.pihet at newoldbits.com  Thu Mar 15 12:43:55 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Thu, 15 Mar 2012 17:43:55 +0100
Subject: [PATCH 00/10] PM: Create the AVS class of drivers
Message-ID: <1331829845-9526-1-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

AVS is a power management technique which controls the operating
voltage of a device in order to optimize (i.e. reduce) its power
consumption. The voltage is adapted depending on static factors
(chip manufacturing process) and dynamic factors (temperature
depending performance).
AVS is also called SmartReflex on OMAP devices.

To that end, create the AVS framework in drivers/power/avs and
move the OMAP SmartReflex code to the new directory.

In preparation to the move of the OMAP code the following changes have been
made:
- split the include files into generic and platform specific code,
- fill in platform data from the device initialization code and pass
  it to the driver,
- create CONFIG_AVS* config options accordingly.

The platform integration data for SmartReflex is passed from hwmod
and the voltage layer to the driver using pdata.


Tested on OMAP3 Beagleboard using omap2plus_defconfig with the
CONFIG_POWER_AVS* options set.
Based on master branch of the l-o git tree (3.3.0-rc6) [1], commit
85244e0edd240da2004bb2ab7cbcbc67a336f20d.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git


Jean Pihet (10):
  ARM: OMAP3+: voltage: export functions to plat/voltage.h
  ARM: OMAP2+: SmartReflex: move the platform specific macros in
    plat-omap
  ARM: OMAP3+: SmartReflex: class drivers should use struct omap_sr *
  ARM: OMAP2+: smartreflex: Use the names from hwmod data instead of
    voltage domains.
  ARM: OMAP3: hwmod: rename the smartreflex entries
  ARM: OMAP2+: SmartReflex: use the platform header file for voltage
    functions
  ARM: OMAP2+: SmartReflex: introduce a busy loop condition test macro
  ARM: OMAP2+: SmartReflex: Use per-OPP data structure
  ARM: OMAP2+: SmartReflex: add POWER_AVS Kconfig options
  ARM: OMAP: SmartReflex: Move smartreflex driver to drivers/

 arch/arm/mach-omap2/Makefile                  |    4 +-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c    |   11 +-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c    |    3 +-
 arch/arm/mach-omap2/pm.h                      |    2 +-
 arch/arm/mach-omap2/smartreflex-class3.c      |   60 --
 arch/arm/mach-omap2/smartreflex.c             | 1165 -------------------------
 arch/arm/mach-omap2/smartreflex.h             |  256 ------
 arch/arm/mach-omap2/sr_device.c               |   38 +-
 arch/arm/mach-omap2/voltage.h                 |    1 -
 arch/arm/mach-omap2/vp.h                      |    2 -
 arch/arm/plat-omap/Kconfig                    |   31 -
 arch/arm/plat-omap/include/plat/smartreflex.h |   95 ++
 arch/arm/plat-omap/include/plat/voltage.h     |    3 +
 drivers/power/Kconfig                         |    2 +
 drivers/power/Makefile                        |    2 +
 drivers/power/avs/Kconfig                     |   45 +
 drivers/power/avs/Makefile                    |    2 +
 drivers/power/avs/smartreflex-class3.c        |   60 ++
 drivers/power/avs/smartreflex.c               | 1117 ++++++++++++++++++++++++
 drivers/power/avs/smartreflex.h               |  238 +++++
 20 files changed, 1604 insertions(+), 1533 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/smartreflex-class3.c
 delete mode 100644 arch/arm/mach-omap2/smartreflex.c
 delete mode 100644 arch/arm/mach-omap2/smartreflex.h
 create mode 100644 arch/arm/plat-omap/include/plat/smartreflex.h
 create mode 100644 drivers/power/avs/Kconfig
 create mode 100644 drivers/power/avs/Makefile
 create mode 100644 drivers/power/avs/smartreflex-class3.c
 create mode 100644 drivers/power/avs/smartreflex.c
 create mode 100644 drivers/power/avs/smartreflex.h

-- 
1.7.5.4



From jean.pihet at newoldbits.com  Thu Mar 15 12:43:56 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Thu, 15 Mar 2012 17:43:56 +0100
Subject: [PATCH 01/10] ARM: OMAP3+: voltage: export functions to plat/voltage.h
In-Reply-To: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331829845-9526-2-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Move some functions from mach-omap2/ dir to the plat/ dir.
The SmartReflex class driver is a user of the basic voltage domains
functions (enable, disable, reset).

Signed-off-by: Jean Pihet <j-pihet at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/voltage.h             |    1 -
 arch/arm/mach-omap2/vp.h                  |    2 --
 arch/arm/plat-omap/include/plat/voltage.h |    3 +++
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 16a1b09..a81dea8 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -167,6 +167,5 @@ int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
 			  int (*fn)(struct voltagedomain *voltdm,
 				    struct powerdomain *pwrdm));
 int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
-void voltdm_reset(struct voltagedomain *voltdm);
 unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
 #endif
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
index 7c155d2..837cb8d 100644
--- a/arch/arm/mach-omap2/vp.h
+++ b/arch/arm/mach-omap2/vp.h
@@ -118,8 +118,6 @@ extern struct omap_vp_instance omap4_vp_iva;
 extern struct omap_vp_instance omap4_vp_core;
 
 void omap_vp_init(struct voltagedomain *voltdm);
-void omap_vp_enable(struct voltagedomain *voltdm);
-void omap_vp_disable(struct voltagedomain *voltdm);
 int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
 			      unsigned long target_volt);
 int omap_vp_update_errorgain(struct voltagedomain *voltdm,
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
index 0a6a482..1842709 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -16,5 +16,8 @@ struct voltagedomain;
 struct voltagedomain *voltdm_lookup(const char *name);
 int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
 unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
+void voltdm_reset(struct voltagedomain *voltdm);
 
+void omap_vp_enable(struct voltagedomain *voltdm);
+void omap_vp_disable(struct voltagedomain *voltdm);
 #endif
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Thu Mar 15 12:43:57 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Thu, 15 Mar 2012 17:43:57 +0100
Subject: [PATCH 02/10] ARM: OMAP2+: SmartReflex: move the platform specific
 macros in plat-omap
In-Reply-To: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331829845-9526-3-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Move the platform specific macros from the smartreflex header file
(arch/arm/mach-omap2/smartreflex.h) in a new header file in plat-omap
(arch/arm/plat-omap/include/plat/smartreflex.h).

This change makes the SmartReflex implementation ready for the move
to drivers/.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c    |    3 +-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c    |    3 +-
 arch/arm/mach-omap2/smartreflex.h             |   42 ----------------
 arch/arm/mach-omap2/sr_device.c               |    2 +-
 arch/arm/plat-omap/include/plat/smartreflex.h |   65 +++++++++++++++++++++++++
 5 files changed, 68 insertions(+), 47 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/smartreflex.h

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 0cc6a40..1f681e8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -26,10 +26,9 @@
 #include <plat/mcbsp.h>
 #include <plat/mcspi.h>
 #include <plat/dmtimer.h>
+#include <plat/smartreflex.h>
 
 #include "omap_hwmod_common_data.h"
-
-#include "smartreflex.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
 #include "wd_timer.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 48e5834..a1e359f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -30,10 +30,9 @@
 #include <plat/mmc.h>
 #include <plat/dmtimer.h>
 #include <plat/common.h>
+#include <plat/smartreflex.h>
 
 #include "omap_hwmod_common_data.h"
-
-#include "smartreflex.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 #include "prm44xx.h"
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 5809141..cb8d98a 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -152,14 +152,6 @@ struct omap_sr_pmic_data {
 	void (*sr_pmic_init) (void);
 };
 
-/**
- * struct omap_smartreflex_dev_attr - Smartreflex Device attribute.
- *
- * @sensor_voltdm_name:       Name of voltdomain of SR instance
- */
-struct omap_smartreflex_dev_attr {
-	const char      *sensor_voltdm_name;
-};
 
 #ifdef CONFIG_OMAP_SMARTREFLEX
 /*
@@ -194,40 +186,6 @@ struct omap_sr_class_data {
 	u8 class_type;
 };
 
-/**
- * struct omap_sr_nvalue_table	- Smartreflex n-target value info
- *
- * @efuse_offs:	The offset of the efuse where n-target values are stored.
- * @nvalue:	The n-target value.
- */
-struct omap_sr_nvalue_table {
-	u32 efuse_offs;
-	u32 nvalue;
-};
-
-/**
- * struct omap_sr_data - Smartreflex platform data.
- *
- * @ip_type:		Smartreflex IP type.
- * @senp_mod:		SENPENABLE value for the sr
- * @senn_mod:		SENNENABLE value for sr
- * @nvalue_count:	Number of distinct nvalues in the nvalue table
- * @enable_on_init:	whether this sr module needs to enabled at
- *			boot up or not.
- * @nvalue_table:	table containing the  efuse offsets and nvalues
- *			corresponding to them.
- * @voltdm:		Pointer to the voltage domain associated with the SR
- */
-struct omap_sr_data {
-	int				ip_type;
-	u32				senp_mod;
-	u32				senn_mod;
-	int				nvalue_count;
-	bool				enable_on_init;
-	struct omap_sr_nvalue_table	*nvalue_table;
-	struct voltagedomain		*voltdm;
-};
-
 /* Smartreflex module enable/disable interface */
 void omap_sr_enable(struct voltagedomain *voltdm);
 void omap_sr_disable(struct voltagedomain *voltdm);
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index a503e1e..dad1473 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -23,8 +23,8 @@
 #include <linux/io.h>
 
 #include <plat/omap_device.h>
+#include <plat/smartreflex.h>
 
-#include "smartreflex.h"
 #include "voltage.h"
 #include "control.h"
 #include "pm.h"
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
new file mode 100644
index 0000000..baa296f
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -0,0 +1,65 @@
+/*
+ * OMAP Platform Smartreflex Defines and Routines
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Jean Pihet <j-pihet at ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970 at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_PLATOMAP_SMARTREFLEX_H
+#define __ASM_ARM_PLATOMAP_SMARTREFLEX_H
+
+#include "voltage.h"
+
+/**
+ * struct omap_sr_nvalue_table	- Smartreflex n-target value info
+ *
+ * @efuse_offs:	The offset of the efuse where n-target values are stored.
+ * @nvalue:	The n-target value.
+ */
+struct omap_sr_nvalue_table {
+	u32 efuse_offs;
+	u32 nvalue;
+};
+
+/**
+ * struct omap_sr_data - Smartreflex platform data.
+ *
+ * @ip_type:		Smartreflex IP type.
+ * @senp_mod:		SENPENABLE value for the sr
+ * @senn_mod:		SENNENABLE value for sr
+ * @nvalue_count:	Number of distinct nvalues in the nvalue table
+ * @enable_on_init:	whether this sr module needs to enabled at
+ *			boot up or not.
+ * @nvalue_table:	table containing the  efuse offsets and nvalues
+ *			corresponding to them.
+ * @voltdm:		Pointer to the voltage domain associated with the SR
+ */
+struct omap_sr_data {
+	int				ip_type;
+	u32				senp_mod;
+	u32				senn_mod;
+	int				nvalue_count;
+	bool				enable_on_init;
+	struct omap_sr_nvalue_table	*nvalue_table;
+	struct voltagedomain		*voltdm;
+};
+
+/**
+ * struct omap_smartreflex_dev_attr - Smartreflex Device attribute.
+ *
+ * @sensor_voltdm_name:       Name of voltdomain of SR instance
+ */
+struct omap_smartreflex_dev_attr {
+	const char      *sensor_voltdm_name;
+};
+
+#endif
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Thu Mar 15 12:43:58 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Thu, 15 Mar 2012 17:43:58 +0100
Subject: [PATCH 03/10] ARM: OMAP3+: SmartReflex: class drivers should use
 struct omap_sr *
In-Reply-To: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331829845-9526-4-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Convert SmartReflex "class" functions to take a struct omap_sr *, rather than
a struct voltagedomain *.  SmartReflex code should be driver code and not
tightly coupled to OMAP subarchitecture-specific structures.

Based on Paul's original code for the SmartReflex driver conversion.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Thara Gopinath <thara at ti.com>
Cc: Nishanth Menon <nm at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/smartreflex-class3.c      |   24 ++++++++--------
 arch/arm/mach-omap2/smartreflex.c             |   37 +++++--------------------
 arch/arm/mach-omap2/smartreflex.h             |    8 +++---
 arch/arm/plat-omap/include/plat/smartreflex.h |   23 +++++++++++++++
 4 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 955566e..a105077 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -13,34 +13,34 @@
 
 #include "smartreflex.h"
 
-static int sr_class3_enable(struct voltagedomain *voltdm)
+static int sr_class3_enable(struct omap_sr *sr)
 {
-	unsigned long volt = voltdm_get_voltage(voltdm);
+	unsigned long volt = voltdm_get_voltage(sr->voltdm);
 
 	if (!volt) {
 		pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
-				__func__, voltdm->name);
+				__func__, sr->voltdm->name);
 		return -ENODATA;
 	}
 
-	omap_vp_enable(voltdm);
-	return sr_enable(voltdm, volt);
+	omap_vp_enable(sr->voltdm);
+	return sr_enable(sr->voltdm, volt);
 }
 
-static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
+static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
 {
-	sr_disable_errgen(voltdm);
-	omap_vp_disable(voltdm);
-	sr_disable(voltdm);
+	sr_disable_errgen(sr->voltdm);
+	omap_vp_disable(sr->voltdm);
+	sr_disable(sr->voltdm);
 	if (is_volt_reset)
-		voltdm_reset(voltdm);
+		voltdm_reset(sr->voltdm);
 
 	return 0;
 }
 
-static int sr_class3_configure(struct voltagedomain *voltdm)
+static int sr_class3_configure(struct omap_sr *sr)
 {
-	return sr_configure_errgen(voltdm);
+	return sr_configure_errgen(sr->voltdm);
 }
 
 /* SR class3 structure */
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 008fbd7..57a484d 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -35,29 +35,6 @@
 #define NVALUE_NAME_LEN		40
 #define SR_DISABLE_TIMEOUT	200
 
-struct omap_sr {
-	struct list_head		node;
-	struct platform_device		*pdev;
-	struct omap_sr_nvalue_table	*nvalue_table;
-	struct voltagedomain		*voltdm;
-	struct dentry			*dbg_dir;
-	unsigned int			irq;
-	int				srid;
-	int				ip_type;
-	int				nvalue_count;
-	bool				autocomp_active;
-	u32				clk_length;
-	u32				err_weight;
-	u32				err_minlimit;
-	u32				err_maxlimit;
-	u32				accum_data;
-	u32				senn_avgweight;
-	u32				senp_avgweight;
-	u32				senp_mod;
-	u32				senn_mod;
-	void __iomem			*base;
-};
-
 /* sr_list contains all the instances of smartreflex module */
 static LIST_HEAD(sr_list);
 
@@ -148,7 +125,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
 	}
 
 	if (sr_class->notify)
-		sr_class->notify(sr_info->voltdm, status);
+		sr_class->notify(sr_info, status);
 
 	return IRQ_HANDLED;
 }
@@ -226,7 +203,7 @@ static void sr_start_vddautocomp(struct omap_sr *sr)
 		return;
 	}
 
-	if (!sr_class->enable(sr->voltdm))
+	if (!sr_class->enable(sr))
 		sr->autocomp_active = true;
 }
 
@@ -240,7 +217,7 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
 	}
 
 	if (sr->autocomp_active) {
-		sr_class->disable(sr->voltdm, 1);
+		sr_class->disable(sr, 1);
 		sr->autocomp_active = false;
 	}
 }
@@ -655,7 +632,7 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 		return 0;
 
 	/* Configure SR */
-	ret = sr_class->configure(voltdm);
+	ret = sr_class->configure(sr);
 	if (ret)
 		return ret;
 
@@ -773,7 +750,7 @@ void omap_sr_enable(struct voltagedomain *voltdm)
 		return;
 	}
 
-	sr_class->enable(voltdm);
+	sr_class->enable(sr);
 }
 
 /**
@@ -806,7 +783,7 @@ void omap_sr_disable(struct voltagedomain *voltdm)
 		return;
 	}
 
-	sr_class->disable(voltdm, 0);
+	sr_class->disable(sr, 0);
 }
 
 /**
@@ -839,7 +816,7 @@ void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
 		return;
 	}
 
-	sr_class->disable(voltdm, 1);
+	sr_class->disable(sr, 1);
 }
 
 /**
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index cb8d98a..f12ebde 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -178,10 +178,10 @@ struct omap_sr_pmic_data {
  *			based decisions.
  */
 struct omap_sr_class_data {
-	int (*enable)(struct voltagedomain *voltdm);
-	int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
-	int (*configure)(struct voltagedomain *voltdm);
-	int (*notify)(struct voltagedomain *voltdm, u32 status);
+	int (*enable)(struct omap_sr *sr);
+	int (*disable)(struct omap_sr *sr, int is_volt_reset);
+	int (*configure)(struct omap_sr *sr);
+	int (*notify)(struct omap_sr *sr, u32 status);
 	u8 notify_flags;
 	u8 class_type;
 };
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
index baa296f..3f46706 100644
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -19,6 +19,29 @@
 
 #include "voltage.h"
 
+struct omap_sr {
+	struct list_head		node;
+	struct platform_device		*pdev;
+	struct omap_sr_nvalue_table	*nvalue_table;
+	struct voltagedomain		*voltdm;
+	struct dentry			*dbg_dir;
+	unsigned int			irq;
+	int				srid;
+	int				ip_type;
+	int				nvalue_count;
+	bool				autocomp_active;
+	u32				clk_length;
+	u32				err_weight;
+	u32				err_minlimit;
+	u32				err_maxlimit;
+	u32				accum_data;
+	u32				senn_avgweight;
+	u32				senp_avgweight;
+	u32				senp_mod;
+	u32				senn_mod;
+	void __iomem			*base;
+};
+
 /**
  * struct omap_sr_nvalue_table	- Smartreflex n-target value info
  *
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Thu Mar 15 12:44:01 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Thu, 15 Mar 2012 17:44:01 +0100
Subject: [PATCH 06/10] ARM: OMAP2+: SmartReflex: use the platform header file
 for voltage functions
In-Reply-To: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331829845-9526-7-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/smartreflex.h |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index f12ebde..8d3e3c2 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -22,7 +22,8 @@
 
 #include <linux/platform_device.h>
 
-#include "voltage.h"
+#include <plat/smartreflex.h>
+#include <plat/voltage.h>
 
 /*
  * Different Smartreflex IPs version. The v1 is the 65nm version used in
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Thu Mar 15 12:44:00 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Thu, 15 Mar 2012 17:44:00 +0100
Subject: [PATCH 05/10] ARM: OMAP3: hwmod: rename the smartreflex entries
In-Reply-To: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331829845-9526-6-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Change the name field value to better reflect the smartreflex
integration in the system

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |    8 ++++----
 arch/arm/mach-omap2/smartreflex.c          |    2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 1f681e8..728740d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2750,7 +2750,7 @@ static struct omap_hwmod_ocp_if *omap34xx_sr1_slaves[] = {
 };
 
 static struct omap_hwmod omap34xx_sr1_hwmod = {
-	.name		= "sr1",
+	.name		= "mpu_iva",
 	.class		= &omap34xx_smartreflex_hwmod_class,
 	.main_clk	= "sr1_fck",
 	.prcm		= {
@@ -2774,7 +2774,7 @@ static struct omap_hwmod_ocp_if *omap36xx_sr1_slaves[] = {
 };
 
 static struct omap_hwmod omap36xx_sr1_hwmod = {
-	.name		= "sr1",
+	.name		= "mpu_iva",
 	.class		= &omap36xx_smartreflex_hwmod_class,
 	.main_clk	= "sr1_fck",
 	.prcm		= {
@@ -2802,7 +2802,7 @@ static struct omap_hwmod_ocp_if *omap34xx_sr2_slaves[] = {
 };
 
 static struct omap_hwmod omap34xx_sr2_hwmod = {
-	.name		= "sr2",
+	.name		= "core",
 	.class		= &omap34xx_smartreflex_hwmod_class,
 	.main_clk	= "sr2_fck",
 	.prcm		= {
@@ -2826,7 +2826,7 @@ static struct omap_hwmod_ocp_if *omap36xx_sr2_slaves[] = {
 };
 
 static struct omap_hwmod omap36xx_sr2_hwmod = {
-	.name		= "sr2",
+	.name		= "core",
 	.class		= &omap36xx_smartreflex_hwmod_class,
 	.main_clk	= "sr2_fck",
 	.prcm		= {
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 8e3ef66..dd80fde 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -184,7 +184,7 @@ static void sr_set_regfields(struct omap_sr *sr)
 		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
 		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
 		sr->accum_data = OMAP3430_SR_ACCUMDATA;
-		if (!(strcmp(sr->name, "sr1"))) {
+		if (!(strcmp(sr->name, "sr_mpu_iva"))) {
 			sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
 			sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
 		} else {
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Thu Mar 15 12:44:02 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Thu, 15 Mar 2012 17:44:02 +0100
Subject: [PATCH 07/10] ARM: OMAP2+: SmartReflex: introduce a busy loop
 condition test macro
In-Reply-To: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331829845-9526-8-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Now that omap_test_timeout is only accessible from mach-omap2/,
introduce a similar function for SR.

This change makes the SmartReflex implementation ready for the move
to drivers/.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |   12 ++++++------
 arch/arm/mach-omap2/smartreflex.h |   23 +++++++++++++++++++++++
 2 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index dd80fde..ceb50b5 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -290,9 +290,9 @@ static void sr_v1_disable(struct omap_sr *sr)
 	 * Wait for SR to be disabled.
 	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
 	 */
-	omap_test_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
-			ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
-			timeout);
+	sr_test_cond_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
+			     ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
+			     timeout);
 
 	if (timeout >= SR_DISABLE_TIMEOUT)
 		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
@@ -335,9 +335,9 @@ static void sr_v2_disable(struct omap_sr *sr)
 	 * Wait for SR to be disabled.
 	 * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
 	 */
-	omap_test_timeout((sr_read_reg(sr, IRQSTATUS) &
-			IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
-			timeout);
+	sr_test_cond_timeout((sr_read_reg(sr, IRQSTATUS) &
+			     IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
+			     timeout);
 
 	if (timeout >= SR_DISABLE_TIMEOUT)
 		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 8d3e3c2..3bd4fee 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -21,6 +21,7 @@
 #define __ASM_ARM_OMAP_SMARTREFLEX_H
 
 #include <linux/platform_device.h>
+#include <linux/delay.h>
 
 #include <plat/smartreflex.h>
 #include <plat/voltage.h>
@@ -144,6 +145,28 @@
 #define OMAP3430_SR_ERRMAXLIMIT		0x02
 
 /**
+ * test_cond_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ *
+ * Copied from omap_test_timeout
+ */
+#define sr_test_cond_timeout(cond, timeout, index)		\
+({								\
+	for (index = 0; index < timeout; index++) {		\
+		if (cond)					\
+			break;					\
+		udelay(1);					\
+	}							\
+})
+
+/**
  * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
  *				pmic specific info to smartreflex driver
  *
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Thu Mar 15 12:43:59 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Thu, 15 Mar 2012 17:43:59 +0100
Subject: [PATCH 04/10] ARM: OMAP2+: smartreflex: Use the names from hwmod data
 instead of voltage domains.
In-Reply-To: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331829845-9526-5-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Associate a name with each SmartReflex instance from the hwmod data,
rather than attempting to reuse the name of a voltage domain. The name
from hwmod better reflects the smartreflex integration in the system.

Also have the name passed to the drivers using pdata, which helps to remove
any dependencies on SoC-specific structures.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/smartreflex-class3.c      |    4 +-
 arch/arm/mach-omap2/smartreflex.c             |   65 ++++++++++---------------
 arch/arm/mach-omap2/sr_device.c               |    1 +
 arch/arm/plat-omap/include/plat/smartreflex.h |    3 +
 4 files changed, 32 insertions(+), 41 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index a105077..9a19ce7 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -18,8 +18,8 @@ static int sr_class3_enable(struct omap_sr *sr)
 	unsigned long volt = voltdm_get_voltage(sr->voltdm);
 
 	if (!volt) {
-		pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
-				__func__, sr->voltdm->name);
+		pr_warning("%s: Curr voltage unknown. Cannot enable %s\n",
+				__func__, sr->name);
 		return -ENODATA;
 	}
 
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 57a484d..8e3ef66 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -184,7 +184,7 @@ static void sr_set_regfields(struct omap_sr *sr)
 		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
 		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
 		sr->accum_data = OMAP3430_SR_ACCUMDATA;
-		if (!(strcmp(sr->voltdm->name, "mpu"))) {
+		if (!(strcmp(sr->name, "sr1"))) {
 			sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
 			sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
 		} else {
@@ -235,19 +235,13 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
  */
 static int sr_late_init(struct omap_sr *sr_info)
 {
-	char *name;
 	struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
 	struct resource *mem;
 	int ret = 0;
 
 	if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
-		name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
-		if (name == NULL) {
-			ret = -ENOMEM;
-			goto error;
-		}
 		ret = request_irq(sr_info->irq, sr_interrupt,
-				0, name, sr_info);
+				  0, sr_info->name, sr_info);
 		if (ret)
 			goto error;
 		disable_irq(sr_info->irq);
@@ -266,7 +260,6 @@ error:
 	dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
 		"interrupt handler. Smartreflex will"
 		"not function as desired\n", __func__);
-	kfree(name);
 	kfree(sr_info);
 
 	return ret;
@@ -396,8 +389,7 @@ int sr_configure_errgen(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return PTR_ERR(sr);
 	}
 
@@ -464,8 +456,7 @@ int sr_disable_errgen(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return PTR_ERR(sr);
 	}
 
@@ -515,8 +506,7 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return PTR_ERR(sr);
 	}
 
@@ -601,8 +591,7 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 	int ret;
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return PTR_ERR(sr);
 	}
 
@@ -655,8 +644,7 @@ void sr_disable(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return;
 	}
 
@@ -736,8 +724,7 @@ void omap_sr_enable(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return;
 	}
 
@@ -769,8 +756,7 @@ void omap_sr_disable(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return;
 	}
 
@@ -802,8 +788,7 @@ void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return;
 	}
 
@@ -890,7 +875,6 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 	struct dentry *nvalue_dir;
 	struct omap_volt_data *volt_data;
 	int i, ret = 0;
-	char *name;
 
 	sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
 	if (!sr_info) {
@@ -927,6 +911,14 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_irq_safe(&pdev->dev);
 
+	sr_info->name = kasprintf(GFP_KERNEL, "sr_%s", pdata->name);
+	if (!sr_info->name) {
+		dev_err(&pdev->dev, "%s: Unable to alloc SR instance name\n",
+			__func__);
+		ret = -ENOMEM;
+		goto err_release_region;
+	}
+
 	sr_info->pdev = pdev;
 	sr_info->srid = pdev->id;
 	sr_info->voltdm = pdata->voltdm;
@@ -974,20 +966,12 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 		}
 	}
 
-	name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
-	if (!name) {
-		dev_err(&pdev->dev, "%s: Unable to alloc debugfs name\n",
-			__func__);
-		ret = -ENOMEM;
-		goto err_iounmap;
-	}
-	sr_info->dbg_dir = debugfs_create_dir(name, sr_dbg_dir);
-	kfree(name);
+	sr_info->dbg_dir = debugfs_create_dir(sr_info->name, sr_dbg_dir);
 	if (IS_ERR_OR_NULL(sr_info->dbg_dir)) {
 		dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
 			__func__);
 		ret = PTR_ERR(sr_info->dbg_dir);
-		goto err_iounmap;
+		goto err_free_name;
 	}
 
 	(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
@@ -1009,10 +993,10 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 
 	omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
 	if (!volt_data) {
-		dev_warn(&pdev->dev, "%s: No Voltage table for the"
-			" corresponding vdd vdd_%s. Cannot create debugfs"
+		dev_warn(&pdev->dev, "%s: %s: No Voltage table for the"
+			" corresponding vdd. Cannot create debugfs"
 			"entries for n-values\n",
-			__func__, sr_info->voltdm->name);
+			__func__, sr_info->name);
 		ret = -ENODATA;
 		goto err_debugfs;
 	}
@@ -1030,6 +1014,8 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 
 err_debugfs:
 	debugfs_remove_recursive(sr_info->dbg_dir);
+err_free_name:
+	kfree(sr_info->name);
 err_iounmap:
 	list_del(&sr_info->node);
 	iounmap(sr_info->base);
@@ -1066,6 +1052,7 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
 
 	list_del(&sr_info->node);
 	iounmap(sr_info->base);
+	kfree(sr_info->name);
 	kfree(sr_info);
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	release_mem_region(mem->start, resource_size(mem));
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index dad1473..2c74ebc 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -93,6 +93,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 		goto exit;
 	}
 
+	sr_data->name = oh->name;
 	sr_data->ip_type = oh->class->rev;
 	sr_data->senn_mod = 0x1;
 	sr_data->senp_mod = 0x1;
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
index 3f46706..7bfc91a 100644
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -20,6 +20,7 @@
 #include "voltage.h"
 
 struct omap_sr {
+	char				*name;
 	struct list_head		node;
 	struct platform_device		*pdev;
 	struct omap_sr_nvalue_table	*nvalue_table;
@@ -56,6 +57,7 @@ struct omap_sr_nvalue_table {
 /**
  * struct omap_sr_data - Smartreflex platform data.
  *
+ * @name:		instance name
  * @ip_type:		Smartreflex IP type.
  * @senp_mod:		SENPENABLE value for the sr
  * @senn_mod:		SENNENABLE value for sr
@@ -67,6 +69,7 @@ struct omap_sr_nvalue_table {
  * @voltdm:		Pointer to the voltage domain associated with the SR
  */
 struct omap_sr_data {
+	const char			*name;
 	int				ip_type;
 	u32				senp_mod;
 	u32				senn_mod;
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Thu Mar 15 12:44:04 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Thu, 15 Mar 2012 17:44:04 +0100
Subject: [PATCH 09/10] ARM: OMAP2+: SmartReflex: add POWER_AVS Kconfig options
In-Reply-To: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331829845-9526-10-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Add a Kconfig menu (POWER_AVS) and rename the Kconfig options
for the OMAP SmartReflex implementation:
 CONFIG_OMAP_SMARTREFLEX renames to CONFIG_POWER_AVS_OMAP
 CONFIG_OMAP_SMARTREFLEX_CLASS3 renames to CONFIG_POWER_AVS_OMAP_CLASS3

This change makes the SmartReflex implementation ready for the move
to drivers/.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/Makefile      |    5 ++-
 arch/arm/mach-omap2/pm.h          |    2 +-
 arch/arm/mach-omap2/smartreflex.h |    6 ++--
 arch/arm/plat-omap/Kconfig        |   45 ++++++++++++++++++++++++------------
 4 files changed, 37 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9746529..30666fd 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -68,8 +68,9 @@ obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o \
 obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o omap-mpuss-lowpower.o \
 					   cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
-obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
-obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-class3.o
+
+obj-$(CONFIG_POWER_AVS_OMAP)		+= sr_device.o smartreflex.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)	+= smartreflex-class3.o
 
 AFLAGS_sleep24xx.o			:=-Wa,-march=armv6
 AFLAGS_sleep34xx.o			:=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index a051431..1a2d483 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -110,7 +110,7 @@ extern void enable_omap3630_toggle_l2_on_restore(void);
 static inline void enable_omap3630_toggle_l2_on_restore(void) { }
 #endif		/* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
 
-#ifdef CONFIG_OMAP_SMARTREFLEX
+#ifdef CONFIG_POWER_AVS_OMAP
 extern int omap_devinit_smartreflex(void);
 extern void omap_enable_smartreflex_on_init(void);
 #else
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 3bd4fee..dbfb554 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -17,8 +17,8 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
-#define __ASM_ARM_OMAP_SMARTREFLEX_H
+#ifndef __DRIVERS_POWER_AVS_SMARTREFLEX_H
+#define __DRIVERS_POWER_AVS_SMARTREFLEX_H
 
 #include <linux/platform_device.h>
 #include <linux/delay.h>
@@ -177,7 +177,7 @@ struct omap_sr_pmic_data {
 };
 
 
-#ifdef CONFIG_OMAP_SMARTREFLEX
+#ifdef CONFIG_POWER_AVS_OMAP
 /*
  * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
  * The smartreflex class driver should pass the class type.
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index f419a08..6ec9237 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -44,37 +44,52 @@ config OMAP_DEBUG_LEDS
 	depends on OMAP_DEBUG_DEVICES
 	default y if LEDS_CLASS
 
-config OMAP_SMARTREFLEX
-	bool "SmartReflex support"
-	depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
+menuconfig POWER_AVS
+	tristate "Adaptive Voltage Scaling class support"
 	help
-	  Say Y if you want to enable SmartReflex.
+	  AVS is a power management technique which finely controls the
+	  operating voltage of a device in order to optimize (i.e. reduce)
+	  its power consumption.
+	  At a given operating point the voltage is adapted depending on
+	  static factors (chip manufacturing process) and dynamic factors
+	  (temperature depending performance).
+	  AVS is also called SmartReflex on OMAP devices.
+
+	  Say Y here to enable Adaptive Voltage Scaling class support.
+
+if POWER_AVS
 
-	  SmartReflex can perform continuous dynamic voltage
-	  scaling around the nominal operating point voltage
-	  according to silicon characteristics and operating
-	  conditions. Enabling SmartReflex reduces power
-	  consumption.
+config POWER_AVS_OMAP
+	bool "AVS support for the OMAP IP versions 1&2"
+	depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
+	help
+	  Say Y to enable AVS support on OMAP containing the version 1 or
+	  version 2 of the SmartReflex IP.
+	  V1 is the 65nm version used in OMAP3430.
+	  V2 is the update for the 45nm version of the IP used in OMAP3630
+	  and OMAP4430
 
 	  Please note, that by default SmartReflex is only
-	  initialized. To enable the automatic voltage
-	  compensation for vdd mpu  and vdd core from user space,
+	  initialized and not enabled. To enable the automatic voltage
+	  compensation for vdd mpu and vdd core from user space,
 	  user must write 1 to
-		/debug/voltage/vdd_<X>/smartreflex/autocomp,
-	  where X is mpu or core for OMAP3.
+		/debug/smartreflex/sr_<X>/autocomp,
+	  where X is mpu_iva or core for OMAP3.
 	  Optionally autocompensation can be enabled in the kernel
 	  by default during system init via the enable_on_init flag
 	  which an be passed as platform data to the smartreflex driver.
 
-config OMAP_SMARTREFLEX_CLASS3
+config POWER_AVS_OMAP_CLASS3
 	bool "Class 3 mode of Smartreflex Implementation"
-	depends on OMAP_SMARTREFLEX && TWL4030_CORE
+	depends on POWER_AVS_OMAP && TWL4030_CORE
 	help
 	  Say Y to enable Class 3 implementation of Smartreflex
 
 	  Class 3 implementation of Smartreflex employs continuous hardware
 	  voltage calibration.
 
+endif # POWER_AVS
+
 config OMAP_RESET_CLOCKS
 	bool "Reset unused clocks during boot"
 	depends on ARCH_OMAP
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Thu Mar 15 12:44:03 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Thu, 15 Mar 2012 17:44:03 +0100
Subject: [PATCH 08/10] ARM: OMAP2+: SmartReflex: Use per-OPP data structure
In-Reply-To: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331829845-9526-9-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

The SmartReflex driver incorrectly treats some per-OPP data as data
common to all OPPs (e.g., ERRMINLIMIT).  Move this data into a per-OPP
data structure.
The SmartReflex driver should not be dependent on whether the host SoC
uses eFuses to store SmartReflex parameters or not.  (Even SoCs that
do store SR data in eFuses often need to override that data with
software-defined values.)  So, convert sr_retrieve_nvalue() to look up
per-OPP data by the OPP's nominal voltage, rather than by the eFuse
offset.

While at it:
 . tidy up the code wrt default values in the data tables,
 . remove the global errminlimit debugfs entry and create per-voltage
   entries from the data tables.

Furthermore, in order to make the SmartReflex implementation ready for
the move to drivers/, remove the dependency from the SR driver code
to the voltage layer by querying the data tables only from the SR device
init code.

Based on Paul's original code for the SmartReflex driver conversion.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Thara Gopinath <thara at ti.com>
Cc: Nishanth Menon <nm at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/smartreflex.c             |   57 ++++++++++--------------
 arch/arm/mach-omap2/sr_device.c               |   35 +++++++++++++---
 arch/arm/plat-omap/include/plat/smartreflex.h |    8 +++-
 3 files changed, 59 insertions(+), 41 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index ceb50b5..52950a1 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -348,22 +348,24 @@ static void sr_v2_disable(struct omap_sr *sr)
 	sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
 }
 
-static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
+static struct omap_sr_nvalue_table *sr_retrieve_nvalue_row(
+				struct omap_sr *sr,
+				unsigned long volt_nominal)
 {
 	int i;
 
 	if (!sr->nvalue_table) {
 		dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
 			__func__);
-		return 0;
+		return NULL;
 	}
 
 	for (i = 0; i < sr->nvalue_count; i++) {
-		if (sr->nvalue_table[i].efuse_offs == efuse_offs)
-			return sr->nvalue_table[i].nvalue;
+		if (sr->nvalue_table[i].volt_nominal == volt_nominal)
+			return &sr->nvalue_table[i];
 	}
 
-	return 0;
+	return NULL;
 }
 
 /* Public Functions */
@@ -585,9 +587,8 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
  */
 int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 {
-	struct omap_volt_data *volt_data;
 	struct omap_sr *sr = _sr_lookup(voltdm);
-	u32 nvalue_reciprocal;
+	struct omap_sr_nvalue_table *nvalue_row;
 	int ret;
 
 	if (IS_ERR(sr)) {
@@ -595,24 +596,16 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 		return PTR_ERR(sr);
 	}
 
-	volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
-
-	if (IS_ERR(volt_data)) {
-		dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table"
-			"for nominal voltage %ld\n", __func__, volt);
-		return PTR_ERR(volt_data);
-	}
-
-	nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs);
-
-	if (!nvalue_reciprocal) {
-		dev_warn(&sr->pdev->dev, "%s: NVALUE = 0 at voltage %ld\n",
-			__func__, volt);
+	nvalue_row = sr_retrieve_nvalue_row(sr, volt);
+	if (!nvalue_row) {
+		dev_warn(&sr->pdev->dev, "%s: failure getting SR data for this voltage %ld\n",
+			 __func__, volt);
 		return -ENODATA;
 	}
 
+
 	/* errminlimit is opp dependent and hence linked to voltage */
-	sr->err_minlimit = volt_data->sr_errminlimit;
+	sr->err_minlimit = nvalue_row->errminlimit;
 
 	pm_runtime_get_sync(&sr->pdev->dev);
 
@@ -625,7 +618,7 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 	if (ret)
 		return ret;
 
-	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
+	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_row->nvalue);
 
 	/* SRCONFIG - enable SR */
 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
@@ -873,7 +866,6 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 	struct omap_sr_data *pdata = pdev->dev.platform_data;
 	struct resource *mem, *irq;
 	struct dentry *nvalue_dir;
-	struct omap_volt_data *volt_data;
 	int i, ret = 0;
 
 	sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
@@ -980,8 +972,6 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 			&sr_info->err_weight);
 	(void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
 			&sr_info->err_maxlimit);
-	(void) debugfs_create_x32("errminlimit", S_IRUGO, sr_info->dbg_dir,
-			&sr_info->err_minlimit);
 
 	nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
 	if (IS_ERR_OR_NULL(nvalue_dir)) {
@@ -991,12 +981,9 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 		goto err_debugfs;
 	}
 
-	omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
-	if (!volt_data) {
-		dev_warn(&pdev->dev, "%s: %s: No Voltage table for the"
-			" corresponding vdd. Cannot create debugfs"
-			"entries for n-values\n",
-			__func__, sr_info->name);
+	if (sr_info->nvalue_count == 0 || !sr_info->nvalue_table) {
+		dev_warn(&pdev->dev, "%s: %s: No Voltage table for the corresponding vdd. Cannot create debugfs entries for n-values\n",
+			 __func__, sr_info->name);
 		ret = -ENODATA;
 		goto err_debugfs;
 	}
@@ -1004,10 +991,14 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 	for (i = 0; i < sr_info->nvalue_count; i++) {
 		char name[NVALUE_NAME_LEN + 1];
 
-		snprintf(name, sizeof(name), "volt_%d",
-			 volt_data[i].volt_nominal);
+		snprintf(name, sizeof(name), "volt_%lu",
+			 sr_info->nvalue_table[i].volt_nominal);
 		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
 				&(sr_info->nvalue_table[i].nvalue));
+		snprintf(name, sizeof(name), "errminlimit_%lu",
+			 sr_info->nvalue_table[i].volt_nominal);
+		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
+				&(sr_info->nvalue_table[i].errminlimit));
 	}
 
 	return ret;
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 2c74ebc..e1382a6 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -36,7 +36,10 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
 				struct omap_sr_data *sr_data)
 {
 	struct omap_sr_nvalue_table *nvalue_table;
-	int i, count = 0;
+	int i, j, count = 0;
+
+	sr_data->nvalue_count = 0;
+	sr_data->nvalue_table = NULL;
 
 	while (volt_data[count].volt_nominal)
 		count++;
@@ -44,8 +47,14 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
 	nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count,
 			GFP_KERNEL);
 
-	for (i = 0; i < count; i++) {
+	if (!nvalue_table) {
+		pr_err("OMAP: SmartReflex: cannot allocate memory for n-value table\n");
+		return;
+	}
+
+	for (i = 0, j = 0; i < count; i++) {
 		u32 v;
+
 		/*
 		 * In OMAP4 the efuse registers are 24 bit aligned.
 		 * A __raw_readl will fail for non-32 bit aligned address
@@ -58,15 +67,29 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
 				omap_ctrl_readb(offset + 1) << 8 |
 				omap_ctrl_readb(offset + 2) << 16;
 		} else {
-			 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+			v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
 		}
 
-		nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs;
-		nvalue_table[i].nvalue = v;
+		/*
+		 * Many OMAP SoCs don't have the eFuse values set.
+		 * For example, pretty much all OMAP3xxx before
+		 * ES3.something.
+		 *
+		 * XXX There needs to be some way for board files or
+		 * userspace to add these in.
+		 */
+		if (v == 0)
+			continue;
+
+		nvalue_table[j].nvalue = v;
+		nvalue_table[j].errminlimit = volt_data[i].sr_errminlimit;
+		nvalue_table[j].volt_nominal = volt_data[i].volt_nominal;
+
+		j++;
 	}
 
 	sr_data->nvalue_table = nvalue_table;
-	sr_data->nvalue_count = count;
+	sr_data->nvalue_count = j;
 }
 
 static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
index 7bfc91a..017d36f 100644
--- a/arch/arm/plat-omap/include/plat/smartreflex.h
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -46,12 +46,16 @@ struct omap_sr {
 /**
  * struct omap_sr_nvalue_table	- Smartreflex n-target value info
  *
- * @efuse_offs:	The offset of the efuse where n-target values are stored.
- * @nvalue:	The n-target value.
+ * @efuse_offs:	  The offset of the efuse where n-target values are stored.
+ * @nvalue:	  The n-target value.
+ * @errminlimit:  The value of the ERRMINLIMIT bitfield for this n-target
+ * @volt_nominal: microvolts DC that the VDD is initially programmed to
  */
 struct omap_sr_nvalue_table {
 	u32 efuse_offs;
 	u32 nvalue;
+	u32 errminlimit;
+	unsigned long volt_nominal;
 };
 
 /**
-- 
1.7.5.4



From b04825 at freescale.com  Thu Mar 15 12:44:16 2012
From: b04825 at freescale.com (Timur Tabi)
Date: Thu, 15 Mar 2012 11:44:16 -0500
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120315142702.GL3138@opensource.wolfsonmicro.com>
References: <1331225990-27308-1-git-send-email-shawn.guo@linaro.org>
 <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
Message-ID: <4F621C60.5090700@freescale.com>

Mark Brown wrote:
> On Wed, Mar 14, 2012 at 06:00:41PM -0500, Timur Tabi wrote:
>> Mark Brown wrote:
> 
>> So using imx-audio-sgtl5000.txt as an example, you're saying that if I
>> have two SSIs, I should do this in my device tree:
> 
>> sound1 {
>> };
> 
>> sound2 {
>> };
> 
> That's a totally sensible option if you've got two unrelated audio
> subsystems on your board for some reason.  If you've got a system where
> that's not applicable and the two devices are related in some way then
> you'd define a new sound card binding that reflects that.

Well, the two SSIs are related only in that they're the same kind of
device.  But SSI1 connected to CS4270_1 is completely independent from
SSI2 connected to CS4270_2.

So I guess that means that we'd have two soundX {} top-level nodes.

> The SoC is the bit of silicon with the CPU and other devices on it like
> the DMA controller and SSI or whatever ports.  The card is the PCB this
> has been soldered down onto.

Well, I asked about the difference between the soc BINDING and the card
BINDING.  On PowerPC, at least, there's no distinct binding for either.
For example, I2C devices are on the PCB, but they're listed as child nodes
of the I2C controller, which is on the SoC.

> The problem with your binding has always been, and continues to be, that
> it's based on the idea that there's one CODEC per SSI and that the CODEC
> is a simple appendage of that SSI.  There's no real real binding for the
> machine driver, it's just silently created by a single SSI port.  Really
> there's nothing new with this issue, there's always been this absence of
> a representation for the machine distinct from the individual devices it
> is built up from.
> 
> This means that when you get systems which have auxiliary devices (like
> most of the Wolfson reference boards which have a power amplifier for
> the sub speaker not connected to an SSI port) or that need to set up
> things like complex accessory detection mechanisms there's no real place
> in your binding to support those systems.  Things like the configuration
> of the input and output connections which the nVidia WM8903 drivers are
> able to do over multiple boards are another example.

Ok, fair enough.  I understand that my binding has no way of specifying
board-specific properties, or anything that isn't directly related to the
SSI, codec, or DMA controller.

However, I don't like the way this is being represented as a PowerPC vs.
ARM issue, because that's just not correct.  It's an "old binding" vs "new
binding" issue.  For example:

+	/*
+	 * In case of imx, the machine driver uses new binding which does
+	 * not require SSI driver to trigger machine driver's probe, but
+	 * the pcm device needs to be registered here.
+	 */
+	if (ssi_private->ssi_on_imx) {
+		ssi_private->imx_pcm_pdev =
+			platform_device_register_simple("imx-pcm-audio",

This prohibits me from using the new binding on any future PowerPC parts,
because it clearly says "iMX" on everything.
-- 
Timur Tabi
Linux kernel developer at Freescale



From jean.pihet at newoldbits.com  Thu Mar 15 12:44:05 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Thu, 15 Mar 2012 17:44:05 +0100
Subject: [PATCH 10/10] ARM: OMAP: SmartReflex: Move smartreflex driver to
 drivers/
In-Reply-To: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
Message-ID: <1331829845-9526-11-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

After a clean-up of the interfaces the OMAP IP driver and class
support code is now a generic driver.
Move it to drivers/power/avs/.

The build is controlled by the following Kconfig options:
 . CONFIG_POWER_AVS: general knob for Adaptive Voltage Scaling support,
 . CONFIG_POWER_AVS_OMAP: AVS support on OMAP containing the version 1
    or version 2 of the SmartReflex IP,
 . CONFIG_POWER_AVS_OMAP_CLASS3: Class 3 implementation of Smartreflex.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/Makefile             |    3 +-
 arch/arm/mach-omap2/smartreflex-class3.c |   60 --
 arch/arm/mach-omap2/smartreflex.c        | 1120 ------------------------------
 arch/arm/mach-omap2/smartreflex.h        |  238 -------
 arch/arm/plat-omap/Kconfig               |   46 --
 drivers/power/Kconfig                    |    2 +
 drivers/power/Makefile                   |    2 +
 drivers/power/avs/Kconfig                |   45 ++
 drivers/power/avs/Makefile               |    2 +
 drivers/power/avs/smartreflex-class3.c   |   60 ++
 drivers/power/avs/smartreflex.c          | 1117 +++++++++++++++++++++++++++++
 drivers/power/avs/smartreflex.h          |  238 +++++++
 12 files changed, 1467 insertions(+), 1466 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/smartreflex-class3.c
 delete mode 100644 arch/arm/mach-omap2/smartreflex.c
 delete mode 100644 arch/arm/mach-omap2/smartreflex.h
 create mode 100644 drivers/power/avs/Kconfig
 create mode 100644 drivers/power/avs/Makefile
 create mode 100644 drivers/power/avs/smartreflex-class3.c
 create mode 100644 drivers/power/avs/smartreflex.c
 create mode 100644 drivers/power/avs/smartreflex.h

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 30666fd..bb23056 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -69,8 +69,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o omap-mpuss-lowpower.o \
 					   cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 
-obj-$(CONFIG_POWER_AVS_OMAP)		+= sr_device.o smartreflex.o
-obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)	+= smartreflex-class3.o
+obj-$(CONFIG_POWER_AVS_OMAP)		+= sr_device.o
 
 AFLAGS_sleep24xx.o			:=-Wa,-march=armv6
 AFLAGS_sleep34xx.o			:=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
deleted file mode 100644
index 9a19ce7..0000000
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Smart reflex Class 3 specific implementations
- *
- * Author: Thara Gopinath       <thara at ti.com>
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- * Thara Gopinath <thara at ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include "smartreflex.h"
-
-static int sr_class3_enable(struct omap_sr *sr)
-{
-	unsigned long volt = voltdm_get_voltage(sr->voltdm);
-
-	if (!volt) {
-		pr_warning("%s: Curr voltage unknown. Cannot enable %s\n",
-				__func__, sr->name);
-		return -ENODATA;
-	}
-
-	omap_vp_enable(sr->voltdm);
-	return sr_enable(sr->voltdm, volt);
-}
-
-static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
-{
-	sr_disable_errgen(sr->voltdm);
-	omap_vp_disable(sr->voltdm);
-	sr_disable(sr->voltdm);
-	if (is_volt_reset)
-		voltdm_reset(sr->voltdm);
-
-	return 0;
-}
-
-static int sr_class3_configure(struct omap_sr *sr)
-{
-	return sr_configure_errgen(sr->voltdm);
-}
-
-/* SR class3 structure */
-static struct omap_sr_class_data class3_data = {
-	.enable = sr_class3_enable,
-	.disable = sr_class3_disable,
-	.configure = sr_class3_configure,
-	.class_type = SR_CLASS3,
-};
-
-/* Smartreflex Class3 init API to be called from board file */
-static int __init sr_class3_init(void)
-{
-	pr_info("SmartReflex Class3 initialized\n");
-	return sr_register_class(&class3_data);
-}
-late_initcall(sr_class3_init);
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
deleted file mode 100644
index 52950a1..0000000
--- a/arch/arm/mach-omap2/smartreflex.c
+++ /dev/null
@@ -1,1120 +0,0 @@
-/*
- * OMAP SmartReflex Voltage Control
- *
- * Author: Thara Gopinath	<thara at ti.com>
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- * Thara Gopinath <thara at ti.com>
- *
- * Copyright (C) 2008 Nokia Corporation
- * Kalle Jokiniemi
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Lesly A M <x0080970 at ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/pm_runtime.h>
-
-#include "common.h"
-
-#include "pm.h"
-#include "smartreflex.h"
-
-#define SMARTREFLEX_NAME_LEN	16
-#define NVALUE_NAME_LEN		40
-#define SR_DISABLE_TIMEOUT	200
-
-/* sr_list contains all the instances of smartreflex module */
-static LIST_HEAD(sr_list);
-
-static struct omap_sr_class_data *sr_class;
-static struct omap_sr_pmic_data *sr_pmic_data;
-static struct dentry		*sr_dbg_dir;
-
-static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
-{
-	__raw_writel(value, (sr->base + offset));
-}
-
-static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
-					u32 value)
-{
-	u32 reg_val;
-
-	/*
-	 * Smartreflex error config register is special as it contains
-	 * certain status bits which if written a 1 into means a clear
-	 * of those bits. So in order to make sure no accidental write of
-	 * 1 happens to those status bits, do a clear of them in the read
-	 * value. This mean this API doesn't rewrite values in these bits
-	 * if they are currently set, but does allow the caller to write
-	 * those bits.
-	 */
-	if (sr->ip_type == SR_TYPE_V1 && offset == ERRCONFIG_V1)
-		mask |= ERRCONFIG_STATUS_V1_MASK;
-	else if (sr->ip_type == SR_TYPE_V2 && offset == ERRCONFIG_V2)
-		mask |= ERRCONFIG_VPBOUNDINTST_V2;
-
-	reg_val = __raw_readl(sr->base + offset);
-	reg_val &= ~mask;
-
-	value &= mask;
-
-	reg_val |= value;
-
-	__raw_writel(reg_val, (sr->base + offset));
-}
-
-static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
-{
-	return __raw_readl(sr->base + offset);
-}
-
-static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
-{
-	struct omap_sr *sr_info;
-
-	if (!voltdm) {
-		pr_err("%s: Null voltage domain passed!\n", __func__);
-		return ERR_PTR(-EINVAL);
-	}
-
-	list_for_each_entry(sr_info, &sr_list, node) {
-		if (voltdm == sr_info->voltdm)
-			return sr_info;
-	}
-
-	return ERR_PTR(-ENODATA);
-}
-
-static irqreturn_t sr_interrupt(int irq, void *data)
-{
-	struct omap_sr *sr_info = data;
-	u32 status = 0;
-
-	switch (sr_info->ip_type) {
-	case SR_TYPE_V1:
-		/* Read the status bits */
-		status = sr_read_reg(sr_info, ERRCONFIG_V1);
-
-		/* Clear them by writing back */
-		sr_write_reg(sr_info, ERRCONFIG_V1, status);
-		break;
-	case SR_TYPE_V2:
-		/* Read the status bits */
-		status = sr_read_reg(sr_info, IRQSTATUS);
-
-		/* Clear them by writing back */
-		sr_write_reg(sr_info, IRQSTATUS, status);
-		break;
-	default:
-		dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n",
-			sr_info->ip_type);
-		return IRQ_NONE;
-	}
-
-	if (sr_class->notify)
-		sr_class->notify(sr_info, status);
-
-	return IRQ_HANDLED;
-}
-
-static void sr_set_clk_length(struct omap_sr *sr)
-{
-	struct clk *sys_ck;
-	u32 sys_clk_speed;
-
-	if (cpu_is_omap34xx())
-		sys_ck = clk_get(NULL, "sys_ck");
-	else
-		sys_ck = clk_get(NULL, "sys_clkin_ck");
-
-	if (IS_ERR(sys_ck)) {
-		dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
-			__func__);
-		return;
-	}
-
-	sys_clk_speed = clk_get_rate(sys_ck);
-	clk_put(sys_ck);
-
-	switch (sys_clk_speed) {
-	case 12000000:
-		sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
-		break;
-	case 13000000:
-		sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
-		break;
-	case 19200000:
-		sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
-		break;
-	case 26000000:
-		sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
-		break;
-	case 38400000:
-		sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
-		break;
-	default:
-		dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n",
-			__func__, sys_clk_speed);
-		break;
-	}
-}
-
-static void sr_set_regfields(struct omap_sr *sr)
-{
-	/*
-	 * For time being these values are defined in smartreflex.h
-	 * and populated during init. May be they can be moved to board
-	 * file or pmic specific data structure. In that case these structure
-	 * fields will have to be populated using the pdata or pmic structure.
-	 */
-	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
-		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
-		sr->accum_data = OMAP3430_SR_ACCUMDATA;
-		if (!(strcmp(sr->name, "sr_mpu_iva"))) {
-			sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
-			sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
-		} else {
-			sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
-			sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
-		}
-	}
-}
-
-static void sr_start_vddautocomp(struct omap_sr *sr)
-{
-	if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
-		dev_warn(&sr->pdev->dev,
-			"%s: smartreflex class driver not registered\n",
-			__func__);
-		return;
-	}
-
-	if (!sr_class->enable(sr))
-		sr->autocomp_active = true;
-}
-
-static void sr_stop_vddautocomp(struct omap_sr *sr)
-{
-	if (!sr_class || !(sr_class->disable)) {
-		dev_warn(&sr->pdev->dev,
-			"%s: smartreflex class driver not registered\n",
-			__func__);
-		return;
-	}
-
-	if (sr->autocomp_active) {
-		sr_class->disable(sr, 1);
-		sr->autocomp_active = false;
-	}
-}
-
-/*
- * This function handles the intializations which have to be done
- * only when both sr device and class driver regiter has
- * completed. This will be attempted to be called from both sr class
- * driver register and sr device intializtion API's. Only one call
- * will ultimately succeed.
- *
- * Currently this function registers interrupt handler for a particular SR
- * if smartreflex class driver is already registered and has
- * requested for interrupts and the SR interrupt line in present.
- */
-static int sr_late_init(struct omap_sr *sr_info)
-{
-	struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
-	struct resource *mem;
-	int ret = 0;
-
-	if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
-		ret = request_irq(sr_info->irq, sr_interrupt,
-				  0, sr_info->name, sr_info);
-		if (ret)
-			goto error;
-		disable_irq(sr_info->irq);
-	}
-
-	if (pdata && pdata->enable_on_init)
-		sr_start_vddautocomp(sr_info);
-
-	return ret;
-
-error:
-	iounmap(sr_info->base);
-	mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
-	release_mem_region(mem->start, resource_size(mem));
-	list_del(&sr_info->node);
-	dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
-		"interrupt handler. Smartreflex will"
-		"not function as desired\n", __func__);
-	kfree(sr_info);
-
-	return ret;
-}
-
-static void sr_v1_disable(struct omap_sr *sr)
-{
-	int timeout = 0;
-	int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
-			ERRCONFIG_MCUBOUNDINTST;
-
-	/* Enable MCUDisableAcknowledge interrupt */
-	sr_modify_reg(sr, ERRCONFIG_V1,
-			ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
-
-	/* SRCONFIG - disable SR */
-	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
-
-	/* Disable all other SR interrupts and clear the status as needed */
-	if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1)
-		errconf_val |= ERRCONFIG_VPBOUNDINTST_V1;
-	sr_modify_reg(sr, ERRCONFIG_V1,
-			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
-			ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
-			errconf_val);
-
-	/*
-	 * Wait for SR to be disabled.
-	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
-	 */
-	sr_test_cond_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
-			     ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
-			     timeout);
-
-	if (timeout >= SR_DISABLE_TIMEOUT)
-		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
-			__func__);
-
-	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
-	sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
-			ERRCONFIG_MCUDISACKINTST);
-}
-
-static void sr_v2_disable(struct omap_sr *sr)
-{
-	int timeout = 0;
-
-	/* Enable MCUDisableAcknowledge interrupt */
-	sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
-
-	/* SRCONFIG - disable SR */
-	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
-
-	/*
-	 * Disable all other SR interrupts and clear the status
-	 * write to status register ONLY on need basis - only if status
-	 * is set.
-	 */
-	if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2)
-		sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
-			ERRCONFIG_VPBOUNDINTST_V2);
-	else
-		sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
-				0x0);
-	sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
-			IRQENABLE_MCUVALIDINT |
-			IRQENABLE_MCUBOUNDSINT));
-	sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
-			IRQSTATUS_MCVALIDINT |
-			IRQSTATUS_MCBOUNDSINT));
-
-	/*
-	 * Wait for SR to be disabled.
-	 * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
-	 */
-	sr_test_cond_timeout((sr_read_reg(sr, IRQSTATUS) &
-			     IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
-			     timeout);
-
-	if (timeout >= SR_DISABLE_TIMEOUT)
-		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
-			__func__);
-
-	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
-	sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
-	sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
-}
-
-static struct omap_sr_nvalue_table *sr_retrieve_nvalue_row(
-				struct omap_sr *sr,
-				unsigned long volt_nominal)
-{
-	int i;
-
-	if (!sr->nvalue_table) {
-		dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
-			__func__);
-		return NULL;
-	}
-
-	for (i = 0; i < sr->nvalue_count; i++) {
-		if (sr->nvalue_table[i].volt_nominal == volt_nominal)
-			return &sr->nvalue_table[i];
-	}
-
-	return NULL;
-}
-
-/* Public Functions */
-
-/**
- * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the
- *			 error generator module.
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * configure the error generator module inside the smartreflex module.
- * SR settings if using the ERROR module inside Smartreflex.
- * SR CLASS 3 by default uses only the ERROR module where as
- * SR CLASS 2 can choose between ERROR module and MINMAXAVG
- * module. Returns 0 on success and error value in case of failure.
- */
-int sr_configure_errgen(struct voltagedomain *voltdm)
-{
-	u32 sr_config, sr_errconfig, errconfig_offs;
-	u32 vpboundint_en, vpboundint_st;
-	u32 senp_en = 0, senn_en = 0;
-	u8 senp_shift, senn_shift;
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return PTR_ERR(sr);
-	}
-
-	if (!sr->clk_length)
-		sr_set_clk_length(sr);
-
-	senp_en = sr->senp_mod;
-	senn_en = sr->senn_mod;
-
-	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-		SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
-
-	switch (sr->ip_type) {
-	case SR_TYPE_V1:
-		sr_config |= SRCONFIG_DELAYCTRL;
-		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
-		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
-		errconfig_offs = ERRCONFIG_V1;
-		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
-		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
-		break;
-	case SR_TYPE_V2:
-		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
-		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
-		errconfig_offs = ERRCONFIG_V2;
-		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
-		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
-		break;
-	default:
-		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-			"module without specifying the ip\n", __func__);
-		return -EINVAL;
-	}
-
-	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
-	sr_write_reg(sr, SRCONFIG, sr_config);
-	sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
-		(sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
-		(sr->err_minlimit <<  ERRCONFIG_ERRMINLIMIT_SHIFT);
-	sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
-		SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
-		sr_errconfig);
-
-	/* Enabling the interrupts if the ERROR module is used */
-	sr_modify_reg(sr, errconfig_offs, (vpboundint_en | vpboundint_st),
-		      vpboundint_en);
-
-	return 0;
-}
-
-/**
- * sr_disable_errgen() - Disables SmartReflex AVS module's errgen component
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * disable the error generator module inside the smartreflex module.
- *
- * Returns 0 on success and error value in case of failure.
- */
-int sr_disable_errgen(struct voltagedomain *voltdm)
-{
-	u32 errconfig_offs;
-	u32 vpboundint_en, vpboundint_st;
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return PTR_ERR(sr);
-	}
-
-	switch (sr->ip_type) {
-	case SR_TYPE_V1:
-		errconfig_offs = ERRCONFIG_V1;
-		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
-		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
-		break;
-	case SR_TYPE_V2:
-		errconfig_offs = ERRCONFIG_V2;
-		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
-		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
-		break;
-	default:
-		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-			"module without specifying the ip\n", __func__);
-		return -EINVAL;
-	}
-
-	/* Disable the interrupts of ERROR module */
-	sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
-
-	/* Disable the Sensor and errorgen */
-	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0);
-
-	return 0;
-}
-
-/**
- * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the
- *			 minmaxavg module.
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * configure the minmaxavg module inside the smartreflex module.
- * SR settings if using the ERROR module inside Smartreflex.
- * SR CLASS 3 by default uses only the ERROR module where as
- * SR CLASS 2 can choose between ERROR module and MINMAXAVG
- * module. Returns 0 on success and error value in case of failure.
- */
-int sr_configure_minmax(struct voltagedomain *voltdm)
-{
-	u32 sr_config, sr_avgwt;
-	u32 senp_en = 0, senn_en = 0;
-	u8 senp_shift, senn_shift;
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return PTR_ERR(sr);
-	}
-
-	if (!sr->clk_length)
-		sr_set_clk_length(sr);
-
-	senp_en = sr->senp_mod;
-	senn_en = sr->senn_mod;
-
-	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-		SRCONFIG_SENENABLE |
-		(sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
-
-	switch (sr->ip_type) {
-	case SR_TYPE_V1:
-		sr_config |= SRCONFIG_DELAYCTRL;
-		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
-		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
-		break;
-	case SR_TYPE_V2:
-		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
-		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
-		break;
-	default:
-		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-			"module without specifying the ip\n", __func__);
-		return -EINVAL;
-	}
-
-	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
-	sr_write_reg(sr, SRCONFIG, sr_config);
-	sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
-		(sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
-	sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
-
-	/*
-	 * Enabling the interrupts if MINMAXAVG module is used.
-	 * TODO: check if all the interrupts are mandatory
-	 */
-	switch (sr->ip_type) {
-	case SR_TYPE_V1:
-		sr_modify_reg(sr, ERRCONFIG_V1,
-			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
-			ERRCONFIG_MCUBOUNDINTEN),
-			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
-			 ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
-			 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
-		break;
-	case SR_TYPE_V2:
-		sr_write_reg(sr, IRQSTATUS,
-			IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
-			IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
-		sr_write_reg(sr, IRQENABLE_SET,
-			IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
-			IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
-		break;
-	default:
-		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-			"module without specifying the ip\n", __func__);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-/**
- * sr_enable() - Enables the smartreflex module.
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- * @volt:	The voltage at which the Voltage domain associated with
- *		the smartreflex module is operating at.
- *		This is required only to program the correct Ntarget value.
- *
- * This API is to be called from the smartreflex class driver to
- * enable a smartreflex module. Returns 0 on success. Returns error
- * value if the voltage passed is wrong or if ntarget value is wrong.
- */
-int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
-{
-	struct omap_sr *sr = _sr_lookup(voltdm);
-	struct omap_sr_nvalue_table *nvalue_row;
-	int ret;
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return PTR_ERR(sr);
-	}
-
-	nvalue_row = sr_retrieve_nvalue_row(sr, volt);
-	if (!nvalue_row) {
-		dev_warn(&sr->pdev->dev, "%s: failure getting SR data for this voltage %ld\n",
-			 __func__, volt);
-		return -ENODATA;
-	}
-
-
-	/* errminlimit is opp dependent and hence linked to voltage */
-	sr->err_minlimit = nvalue_row->errminlimit;
-
-	pm_runtime_get_sync(&sr->pdev->dev);
-
-	/* Check if SR is already enabled. If yes do nothing */
-	if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
-		return 0;
-
-	/* Configure SR */
-	ret = sr_class->configure(sr);
-	if (ret)
-		return ret;
-
-	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_row->nvalue);
-
-	/* SRCONFIG - enable SR */
-	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
-	return 0;
-}
-
-/**
- * sr_disable() - Disables the smartreflex module.
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * disable a smartreflex module.
- */
-void sr_disable(struct voltagedomain *voltdm)
-{
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return;
-	}
-
-	/* Check if SR clocks are already disabled. If yes do nothing */
-	if (pm_runtime_suspended(&sr->pdev->dev))
-		return;
-
-	/*
-	 * Disable SR if only it is indeed enabled. Else just
-	 * disable the clocks.
-	 */
-	if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
-		switch (sr->ip_type) {
-		case SR_TYPE_V1:
-			sr_v1_disable(sr);
-			break;
-		case SR_TYPE_V2:
-			sr_v2_disable(sr);
-			break;
-		default:
-			dev_err(&sr->pdev->dev, "UNKNOWN IP type %d\n",
-				sr->ip_type);
-		}
-	}
-
-	pm_runtime_put_sync_suspend(&sr->pdev->dev);
-}
-
-/**
- * sr_register_class() - API to register a smartreflex class parameters.
- * @class_data:	The structure containing various sr class specific data.
- *
- * This API is to be called by the smartreflex class driver to register itself
- * with the smartreflex driver during init. Returns 0 on success else the
- * error value.
- */
-int sr_register_class(struct omap_sr_class_data *class_data)
-{
-	struct omap_sr *sr_info;
-
-	if (!class_data) {
-		pr_warning("%s:, Smartreflex class data passed is NULL\n",
-			__func__);
-		return -EINVAL;
-	}
-
-	if (sr_class) {
-		pr_warning("%s: Smartreflex class driver already registered\n",
-			__func__);
-		return -EBUSY;
-	}
-
-	sr_class = class_data;
-
-	/*
-	 * Call into late init to do intializations that require
-	 * both sr driver and sr class driver to be initiallized.
-	 */
-	list_for_each_entry(sr_info, &sr_list, node)
-		sr_late_init(sr_info);
-
-	return 0;
-}
-
-/**
- * omap_sr_enable() -  API to enable SR clocks and to call into the
- *			registered smartreflex class enable API.
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to enable
- * a particular smartreflex module. This API will do the initial
- * configurations to turn on the smartreflex module and in turn call
- * into the registered smartreflex class enable API.
- */
-void omap_sr_enable(struct voltagedomain *voltdm)
-{
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return;
-	}
-
-	if (!sr->autocomp_active)
-		return;
-
-	if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
-		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
-			"registered\n", __func__);
-		return;
-	}
-
-	sr_class->enable(sr);
-}
-
-/**
- * omap_sr_disable() - API to disable SR without resetting the voltage
- *			processor voltage
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to disable
- * a particular smartreflex module. This API will in turn call
- * into the registered smartreflex class disable API. This API will tell
- * the smartreflex class disable not to reset the VP voltage after
- * disabling smartreflex.
- */
-void omap_sr_disable(struct voltagedomain *voltdm)
-{
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return;
-	}
-
-	if (!sr->autocomp_active)
-		return;
-
-	if (!sr_class || !(sr_class->disable)) {
-		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
-			"registered\n", __func__);
-		return;
-	}
-
-	sr_class->disable(sr, 0);
-}
-
-/**
- * omap_sr_disable_reset_volt() - API to disable SR and reset the
- *				voltage processor voltage
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to disable
- * a particular smartreflex module. This API will in turn call
- * into the registered smartreflex class disable API. This API will tell
- * the smartreflex class disable to reset the VP voltage after
- * disabling smartreflex.
- */
-void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
-{
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return;
-	}
-
-	if (!sr->autocomp_active)
-		return;
-
-	if (!sr_class || !(sr_class->disable)) {
-		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
-			"registered\n", __func__);
-		return;
-	}
-
-	sr_class->disable(sr, 1);
-}
-
-/**
- * omap_sr_register_pmic() - API to register pmic specific info.
- * @pmic_data:	The structure containing pmic specific data.
- *
- * This API is to be called from the PMIC specific code to register with
- * smartreflex driver pmic specific info. Currently the only info required
- * is the smartreflex init on the PMIC side.
- */
-void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data)
-{
-	if (!pmic_data) {
-		pr_warning("%s: Trying to register NULL PMIC data structure"
-			"with smartreflex\n", __func__);
-		return;
-	}
-
-	sr_pmic_data = pmic_data;
-}
-
-/* PM Debug FS entries to enable and disable smartreflex. */
-static int omap_sr_autocomp_show(void *data, u64 *val)
-{
-	struct omap_sr *sr_info = data;
-
-	if (!sr_info) {
-		pr_warning("%s: omap_sr struct not found\n", __func__);
-		return -EINVAL;
-	}
-
-	*val = sr_info->autocomp_active;
-
-	return 0;
-}
-
-static int omap_sr_autocomp_store(void *data, u64 val)
-{
-	struct omap_sr *sr_info = data;
-
-	if (!sr_info) {
-		pr_warning("%s: omap_sr struct not found\n", __func__);
-		return -EINVAL;
-	}
-
-	/* Sanity check */
-	if (val > 1) {
-		pr_warning("%s: Invalid argument %lld\n", __func__, val);
-		return -EINVAL;
-	}
-
-	/* control enable/disable only if there is a delta in value */
-	if (sr_info->autocomp_active != val) {
-		if (!val)
-			sr_stop_vddautocomp(sr_info);
-		else
-			sr_start_vddautocomp(sr_info);
-	}
-
-	return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
-			omap_sr_autocomp_store, "%llu\n");
-
-static int __init omap_sr_probe(struct platform_device *pdev)
-{
-	struct omap_sr *sr_info;
-	struct omap_sr_data *pdata = pdev->dev.platform_data;
-	struct resource *mem, *irq;
-	struct dentry *nvalue_dir;
-	int i, ret = 0;
-
-	sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
-	if (!sr_info) {
-		dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
-			__func__);
-		return -ENOMEM;
-	}
-
-	platform_set_drvdata(pdev, sr_info);
-
-	if (!pdata) {
-		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
-		ret = -EINVAL;
-		goto err_free_devinfo;
-	}
-
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!mem) {
-		dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
-		ret = -ENODEV;
-		goto err_free_devinfo;
-	}
-
-	mem = request_mem_region(mem->start, resource_size(mem),
-					dev_name(&pdev->dev));
-	if (!mem) {
-		dev_err(&pdev->dev, "%s: no mem region\n", __func__);
-		ret = -EBUSY;
-		goto err_free_devinfo;
-	}
-
-	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-
-	pm_runtime_enable(&pdev->dev);
-	pm_runtime_irq_safe(&pdev->dev);
-
-	sr_info->name = kasprintf(GFP_KERNEL, "sr_%s", pdata->name);
-	if (!sr_info->name) {
-		dev_err(&pdev->dev, "%s: Unable to alloc SR instance name\n",
-			__func__);
-		ret = -ENOMEM;
-		goto err_release_region;
-	}
-
-	sr_info->pdev = pdev;
-	sr_info->srid = pdev->id;
-	sr_info->voltdm = pdata->voltdm;
-	sr_info->nvalue_table = pdata->nvalue_table;
-	sr_info->nvalue_count = pdata->nvalue_count;
-	sr_info->senn_mod = pdata->senn_mod;
-	sr_info->senp_mod = pdata->senp_mod;
-	sr_info->autocomp_active = false;
-	sr_info->ip_type = pdata->ip_type;
-	sr_info->base = ioremap(mem->start, resource_size(mem));
-	if (!sr_info->base) {
-		dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
-		ret = -ENOMEM;
-		goto err_release_region;
-	}
-
-	if (irq)
-		sr_info->irq = irq->start;
-
-	sr_set_clk_length(sr_info);
-	sr_set_regfields(sr_info);
-
-	list_add(&sr_info->node, &sr_list);
-
-	/*
-	 * Call into late init to do intializations that require
-	 * both sr driver and sr class driver to be initiallized.
-	 */
-	if (sr_class) {
-		ret = sr_late_init(sr_info);
-		if (ret) {
-			pr_warning("%s: Error in SR late init\n", __func__);
-			goto err_iounmap;
-		}
-	}
-
-	dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
-	if (!sr_dbg_dir) {
-		sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
-		if (IS_ERR_OR_NULL(sr_dbg_dir)) {
-			ret = PTR_ERR(sr_dbg_dir);
-			pr_err("%s:sr debugfs dir creation failed(%d)\n",
-				__func__, ret);
-			goto err_iounmap;
-		}
-	}
-
-	sr_info->dbg_dir = debugfs_create_dir(sr_info->name, sr_dbg_dir);
-	if (IS_ERR_OR_NULL(sr_info->dbg_dir)) {
-		dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
-			__func__);
-		ret = PTR_ERR(sr_info->dbg_dir);
-		goto err_free_name;
-	}
-
-	(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
-			sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops);
-	(void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
-			&sr_info->err_weight);
-	(void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
-			&sr_info->err_maxlimit);
-
-	nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
-	if (IS_ERR_OR_NULL(nvalue_dir)) {
-		dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
-			"for n-values\n", __func__);
-		ret = PTR_ERR(nvalue_dir);
-		goto err_debugfs;
-	}
-
-	if (sr_info->nvalue_count == 0 || !sr_info->nvalue_table) {
-		dev_warn(&pdev->dev, "%s: %s: No Voltage table for the corresponding vdd. Cannot create debugfs entries for n-values\n",
-			 __func__, sr_info->name);
-		ret = -ENODATA;
-		goto err_debugfs;
-	}
-
-	for (i = 0; i < sr_info->nvalue_count; i++) {
-		char name[NVALUE_NAME_LEN + 1];
-
-		snprintf(name, sizeof(name), "volt_%lu",
-			 sr_info->nvalue_table[i].volt_nominal);
-		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
-				&(sr_info->nvalue_table[i].nvalue));
-		snprintf(name, sizeof(name), "errminlimit_%lu",
-			 sr_info->nvalue_table[i].volt_nominal);
-		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
-				&(sr_info->nvalue_table[i].errminlimit));
-	}
-
-	return ret;
-
-err_debugfs:
-	debugfs_remove_recursive(sr_info->dbg_dir);
-err_free_name:
-	kfree(sr_info->name);
-err_iounmap:
-	list_del(&sr_info->node);
-	iounmap(sr_info->base);
-err_release_region:
-	release_mem_region(mem->start, resource_size(mem));
-err_free_devinfo:
-	kfree(sr_info);
-
-	return ret;
-}
-
-static int __devexit omap_sr_remove(struct platform_device *pdev)
-{
-	struct omap_sr_data *pdata = pdev->dev.platform_data;
-	struct omap_sr *sr_info;
-	struct resource *mem;
-
-	if (!pdata) {
-		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
-		return -EINVAL;
-	}
-
-	sr_info = _sr_lookup(pdata->voltdm);
-	if (IS_ERR(sr_info)) {
-		dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
-			__func__);
-		return PTR_ERR(sr_info);
-	}
-
-	if (sr_info->autocomp_active)
-		sr_stop_vddautocomp(sr_info);
-	if (sr_info->dbg_dir)
-		debugfs_remove_recursive(sr_info->dbg_dir);
-
-	list_del(&sr_info->node);
-	iounmap(sr_info->base);
-	kfree(sr_info->name);
-	kfree(sr_info);
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	release_mem_region(mem->start, resource_size(mem));
-
-	return 0;
-}
-
-static void __devexit omap_sr_shutdown(struct platform_device *pdev)
-{
-	struct omap_sr_data *pdata = pdev->dev.platform_data;
-	struct omap_sr *sr_info;
-
-	if (!pdata) {
-		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
-		return;
-	}
-
-	sr_info = _sr_lookup(pdata->voltdm);
-	if (IS_ERR(sr_info)) {
-		dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
-			__func__);
-		return;
-	}
-
-	if (sr_info->autocomp_active)
-		sr_stop_vddautocomp(sr_info);
-
-	return;
-}
-
-static struct platform_driver smartreflex_driver = {
-	.remove         = __devexit_p(omap_sr_remove),
-	.shutdown	= __devexit_p(omap_sr_shutdown),
-	.driver		= {
-		.name	= "smartreflex",
-	},
-};
-
-static int __init sr_init(void)
-{
-	int ret = 0;
-
-	/*
-	 * sr_init is a late init. If by then a pmic specific API is not
-	 * registered either there is no need for anything to be done on
-	 * the PMIC side or somebody has forgotten to register a PMIC
-	 * handler. Warn for the second condition.
-	 */
-	if (sr_pmic_data && sr_pmic_data->sr_pmic_init)
-		sr_pmic_data->sr_pmic_init();
-	else
-		pr_warning("%s: No PMIC hook to init smartreflex\n", __func__);
-
-	ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe);
-	if (ret) {
-		pr_err("%s: platform driver register failed for SR\n",
-			__func__);
-		return ret;
-	}
-
-	return 0;
-}
-late_initcall(sr_init);
-
-static void __exit sr_exit(void)
-{
-	platform_driver_unregister(&smartreflex_driver);
-}
-module_exit(sr_exit);
-
-MODULE_DESCRIPTION("OMAP Smartreflex Driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" DRIVER_NAME);
-MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
deleted file mode 100644
index dbfb554..0000000
--- a/arch/arm/mach-omap2/smartreflex.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * OMAP Smartreflex Defines and Routines
- *
- * Author: Thara Gopinath	<thara at ti.com>
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- * Thara Gopinath <thara at ti.com>
- *
- * Copyright (C) 2008 Nokia Corporation
- * Kalle Jokiniemi
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Lesly A M <x0080970 at ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __DRIVERS_POWER_AVS_SMARTREFLEX_H
-#define __DRIVERS_POWER_AVS_SMARTREFLEX_H
-
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-
-#include <plat/smartreflex.h>
-#include <plat/voltage.h>
-
-/*
- * Different Smartreflex IPs version. The v1 is the 65nm version used in
- * OMAP3430. The v2 is the update for the 45nm version of the IP
- * used in OMAP3630 and OMAP4430
- */
-#define SR_TYPE_V1	1
-#define SR_TYPE_V2	2
-
-/* SMART REFLEX REG ADDRESS OFFSET */
-#define SRCONFIG		0x00
-#define SRSTATUS		0x04
-#define SENVAL			0x08
-#define SENMIN			0x0C
-#define SENMAX			0x10
-#define SENAVG			0x14
-#define AVGWEIGHT		0x18
-#define NVALUERECIPROCAL	0x1c
-#define SENERROR_V1		0x20
-#define ERRCONFIG_V1		0x24
-#define IRQ_EOI			0x20
-#define IRQSTATUS_RAW		0x24
-#define IRQSTATUS		0x28
-#define IRQENABLE_SET		0x2C
-#define IRQENABLE_CLR		0x30
-#define SENERROR_V2		0x34
-#define ERRCONFIG_V2		0x38
-
-/* Bit/Shift Positions */
-
-/* SRCONFIG */
-#define SRCONFIG_ACCUMDATA_SHIFT	22
-#define SRCONFIG_SRCLKLENGTH_SHIFT	12
-#define SRCONFIG_SENNENABLE_V1_SHIFT	5
-#define SRCONFIG_SENPENABLE_V1_SHIFT	3
-#define SRCONFIG_SENNENABLE_V2_SHIFT	1
-#define SRCONFIG_SENPENABLE_V2_SHIFT	0
-#define SRCONFIG_CLKCTRL_SHIFT		0
-
-#define SRCONFIG_ACCUMDATA_MASK		(0x3ff << 22)
-
-#define SRCONFIG_SRENABLE		BIT(11)
-#define SRCONFIG_SENENABLE		BIT(10)
-#define SRCONFIG_ERRGEN_EN		BIT(9)
-#define SRCONFIG_MINMAXAVG_EN		BIT(8)
-#define SRCONFIG_DELAYCTRL		BIT(2)
-
-/* AVGWEIGHT */
-#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT	2
-#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT	0
-
-/* NVALUERECIPROCAL */
-#define NVALUERECIPROCAL_SENPGAIN_SHIFT	20
-#define NVALUERECIPROCAL_SENNGAIN_SHIFT	16
-#define NVALUERECIPROCAL_RNSENP_SHIFT	8
-#define NVALUERECIPROCAL_RNSENN_SHIFT	0
-
-/* ERRCONFIG */
-#define ERRCONFIG_ERRWEIGHT_SHIFT	16
-#define ERRCONFIG_ERRMAXLIMIT_SHIFT	8
-#define ERRCONFIG_ERRMINLIMIT_SHIFT	0
-
-#define SR_ERRWEIGHT_MASK		(0x07 << 16)
-#define SR_ERRMAXLIMIT_MASK		(0xff << 8)
-#define SR_ERRMINLIMIT_MASK		(0xff << 0)
-
-#define ERRCONFIG_VPBOUNDINTEN_V1	BIT(31)
-#define ERRCONFIG_VPBOUNDINTST_V1	BIT(30)
-#define	ERRCONFIG_MCUACCUMINTEN		BIT(29)
-#define ERRCONFIG_MCUACCUMINTST		BIT(28)
-#define	ERRCONFIG_MCUVALIDINTEN		BIT(27)
-#define ERRCONFIG_MCUVALIDINTST		BIT(26)
-#define ERRCONFIG_MCUBOUNDINTEN		BIT(25)
-#define	ERRCONFIG_MCUBOUNDINTST		BIT(24)
-#define	ERRCONFIG_MCUDISACKINTEN	BIT(23)
-#define ERRCONFIG_VPBOUNDINTST_V2	BIT(23)
-#define ERRCONFIG_MCUDISACKINTST	BIT(22)
-#define ERRCONFIG_VPBOUNDINTEN_V2	BIT(22)
-
-#define ERRCONFIG_STATUS_V1_MASK	(ERRCONFIG_VPBOUNDINTST_V1 | \
-					ERRCONFIG_MCUACCUMINTST | \
-					ERRCONFIG_MCUVALIDINTST | \
-					ERRCONFIG_MCUBOUNDINTST | \
-					ERRCONFIG_MCUDISACKINTST)
-/* IRQSTATUS */
-#define IRQSTATUS_MCUACCUMINT		BIT(3)
-#define IRQSTATUS_MCVALIDINT		BIT(2)
-#define IRQSTATUS_MCBOUNDSINT		BIT(1)
-#define IRQSTATUS_MCUDISABLEACKINT	BIT(0)
-
-/* IRQENABLE_SET and IRQENABLE_CLEAR */
-#define IRQENABLE_MCUACCUMINT		BIT(3)
-#define IRQENABLE_MCUVALIDINT		BIT(2)
-#define IRQENABLE_MCUBOUNDSINT		BIT(1)
-#define IRQENABLE_MCUDISABLEACKINT	BIT(0)
-
-/* Common Bit values */
-
-#define SRCLKLENGTH_12MHZ_SYSCLK	0x3c
-#define SRCLKLENGTH_13MHZ_SYSCLK	0x41
-#define SRCLKLENGTH_19MHZ_SYSCLK	0x60
-#define SRCLKLENGTH_26MHZ_SYSCLK	0x82
-#define SRCLKLENGTH_38MHZ_SYSCLK	0xC0
-
-/*
- * 3430 specific values. Maybe these should be passed from board file or
- * pmic structures.
- */
-#define OMAP3430_SR_ACCUMDATA		0x1f4
-
-#define OMAP3430_SR1_SENPAVGWEIGHT	0x03
-#define OMAP3430_SR1_SENNAVGWEIGHT	0x03
-
-#define OMAP3430_SR2_SENPAVGWEIGHT	0x01
-#define OMAP3430_SR2_SENNAVGWEIGHT	0x01
-
-#define OMAP3430_SR_ERRWEIGHT		0x04
-#define OMAP3430_SR_ERRMAXLIMIT		0x02
-
-/**
- * test_cond_timeout - busy-loop, testing a condition
- * @cond: condition to test until it evaluates to true
- * @timeout: maximum number of microseconds in the timeout
- * @index: loop index (integer)
- *
- * Loop waiting for @cond to become true or until at least @timeout
- * microseconds have passed.  To use, define some integer @index in the
- * calling code.  After running, if @index == @timeout, then the loop has
- * timed out.
- *
- * Copied from omap_test_timeout
- */
-#define sr_test_cond_timeout(cond, timeout, index)		\
-({								\
-	for (index = 0; index < timeout; index++) {		\
-		if (cond)					\
-			break;					\
-		udelay(1);					\
-	}							\
-})
-
-/**
- * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
- *				pmic specific info to smartreflex driver
- *
- * @sr_pmic_init:	API to initialize smartreflex on the PMIC side.
- */
-struct omap_sr_pmic_data {
-	void (*sr_pmic_init) (void);
-};
-
-
-#ifdef CONFIG_POWER_AVS_OMAP
-/*
- * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
- * The smartreflex class driver should pass the class type.
- * Should be used to populate the class_type field of the
- * omap_smartreflex_class_data structure.
- */
-#define SR_CLASS1	0x1
-#define SR_CLASS2	0x2
-#define SR_CLASS3	0x3
-
-/**
- * struct omap_sr_class_data - Smartreflex class driver info
- *
- * @enable:		API to enable a particular class smaartreflex.
- * @disable:		API to disable a particular class smartreflex.
- * @configure:		API to configure a particular class smartreflex.
- * @notify:		API to notify the class driver about an event in SR.
- *			Not needed for class3.
- * @notify_flags:	specify the events to be notified to the class driver
- * @class_type:		specify which smartreflex class.
- *			Can be used by the SR driver to take any class
- *			based decisions.
- */
-struct omap_sr_class_data {
-	int (*enable)(struct omap_sr *sr);
-	int (*disable)(struct omap_sr *sr, int is_volt_reset);
-	int (*configure)(struct omap_sr *sr);
-	int (*notify)(struct omap_sr *sr, u32 status);
-	u8 notify_flags;
-	u8 class_type;
-};
-
-/* Smartreflex module enable/disable interface */
-void omap_sr_enable(struct voltagedomain *voltdm);
-void omap_sr_disable(struct voltagedomain *voltdm);
-void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
-
-/* API to register the pmic specific data with the smartreflex driver. */
-void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
-
-/* Smartreflex driver hooks to be called from Smartreflex class driver */
-int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
-void sr_disable(struct voltagedomain *voltdm);
-int sr_configure_errgen(struct voltagedomain *voltdm);
-int sr_disable_errgen(struct voltagedomain *voltdm);
-int sr_configure_minmax(struct voltagedomain *voltdm);
-
-/* API to register the smartreflex class driver with the smartreflex driver */
-int sr_register_class(struct omap_sr_class_data *class_data);
-#else
-static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
-static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
-static inline void omap_sr_disable_reset_volt(
-		struct voltagedomain *voltdm) {}
-static inline void omap_sr_register_pmic(
-		struct omap_sr_pmic_data *pmic_data) {}
-#endif
-#endif
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 6ec9237..80dfb22 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -44,52 +44,6 @@ config OMAP_DEBUG_LEDS
 	depends on OMAP_DEBUG_DEVICES
 	default y if LEDS_CLASS
 
-menuconfig POWER_AVS
-	tristate "Adaptive Voltage Scaling class support"
-	help
-	  AVS is a power management technique which finely controls the
-	  operating voltage of a device in order to optimize (i.e. reduce)
-	  its power consumption.
-	  At a given operating point the voltage is adapted depending on
-	  static factors (chip manufacturing process) and dynamic factors
-	  (temperature depending performance).
-	  AVS is also called SmartReflex on OMAP devices.
-
-	  Say Y here to enable Adaptive Voltage Scaling class support.
-
-if POWER_AVS
-
-config POWER_AVS_OMAP
-	bool "AVS support for the OMAP IP versions 1&2"
-	depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
-	help
-	  Say Y to enable AVS support on OMAP containing the version 1 or
-	  version 2 of the SmartReflex IP.
-	  V1 is the 65nm version used in OMAP3430.
-	  V2 is the update for the 45nm version of the IP used in OMAP3630
-	  and OMAP4430
-
-	  Please note, that by default SmartReflex is only
-	  initialized and not enabled. To enable the automatic voltage
-	  compensation for vdd mpu and vdd core from user space,
-	  user must write 1 to
-		/debug/smartreflex/sr_<X>/autocomp,
-	  where X is mpu_iva or core for OMAP3.
-	  Optionally autocompensation can be enabled in the kernel
-	  by default during system init via the enable_on_init flag
-	  which an be passed as platform data to the smartreflex driver.
-
-config POWER_AVS_OMAP_CLASS3
-	bool "Class 3 mode of Smartreflex Implementation"
-	depends on POWER_AVS_OMAP && TWL4030_CORE
-	help
-	  Say Y to enable Class 3 implementation of Smartreflex
-
-	  Class 3 implementation of Smartreflex employs continuous hardware
-	  voltage calibration.
-
-endif # POWER_AVS
-
 config OMAP_RESET_CLOCKS
 	bool "Reset unused clocks during boot"
 	depends on ARCH_OMAP
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 3a8daf8..06f991e 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -275,3 +275,5 @@ config CHARGER_MAX8998
 	  platform data of MAX8998/LP3974 PMICs.
 
 endif # POWER_SUPPLY
+
+source "drivers/power/avs/Kconfig"
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index e429008..e4a8fd2 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -41,3 +41,5 @@ obj-$(CONFIG_CHARGER_GPIO)	+= gpio-charger.o
 obj-$(CONFIG_CHARGER_MANAGER)	+= charger-manager.o
 obj-$(CONFIG_CHARGER_MAX8997)	+= max8997_charger.o
 obj-$(CONFIG_CHARGER_MAX8998)	+= max8998_charger.o
+
+obj-$(CONFIG_POWER_AVS)		+= avs/
diff --git a/drivers/power/avs/Kconfig b/drivers/power/avs/Kconfig
new file mode 100644
index 0000000..35b21c4
--- /dev/null
+++ b/drivers/power/avs/Kconfig
@@ -0,0 +1,45 @@
+menuconfig POWER_AVS
+	tristate "Adaptive Voltage Scaling class support"
+	help
+	  AVS is a power management technique which finely controls the
+	  operating voltage of a device in order to optimize (i.e. reduce)
+	  its power consumption.
+	  At a given operating point the voltage is adapted depending on
+	  static factors (chip manufacturing process) and dynamic factors
+	  (temperature depending performance).
+	  AVS is also called SmartReflex on OMAP devices.
+
+	  Say Y here to enable Adaptive Voltage Scaling class support.
+
+if POWER_AVS
+
+config POWER_AVS_OMAP
+	bool "AVS support for the OMAP IP versions 1&2"
+	depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
+	help
+	  Say Y to enable AVS support on OMAP containing the version 1 or
+	  version 2 of the SmartReflex IP.
+	  V1 is the 65nm version used in OMAP3430.
+	  V2 is the update for the 45nm version of the IP used in OMAP3630
+	  and OMAP4430
+
+	  Please note, that by default SmartReflex is only
+	  initialized and not enabled. To enable the automatic voltage
+	  compensation for vdd mpu and vdd core from user space,
+	  user must write 1 to
+		/debug/smartreflex/sr_<X>/autocomp,
+	  where X is mpu_iva or core for OMAP3.
+	  Optionally autocompensation can be enabled in the kernel
+	  by default during system init via the enable_on_init flag
+	  which an be passed as platform data to the smartreflex driver.
+
+config POWER_AVS_OMAP_CLASS3
+	bool "Class 3 mode of Smartreflex Implementation"
+	depends on POWER_AVS_OMAP && TWL4030_CORE
+	help
+	  Say Y to enable Class 3 implementation of Smartreflex
+
+	  Class 3 implementation of Smartreflex employs continuous hardware
+	  voltage calibration.
+
+endif # POWER_AVS
diff --git a/drivers/power/avs/Makefile b/drivers/power/avs/Makefile
new file mode 100644
index 0000000..ac72ec5
--- /dev/null
+++ b/drivers/power/avs/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_POWER_AVS_OMAP)		+= smartreflex.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)	+= smartreflex-class3.o
diff --git a/drivers/power/avs/smartreflex-class3.c b/drivers/power/avs/smartreflex-class3.c
new file mode 100644
index 0000000..9a19ce7
--- /dev/null
+++ b/drivers/power/avs/smartreflex-class3.c
@@ -0,0 +1,60 @@
+/*
+ * Smart reflex Class 3 specific implementations
+ *
+ * Author: Thara Gopinath       <thara at ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "smartreflex.h"
+
+static int sr_class3_enable(struct omap_sr *sr)
+{
+	unsigned long volt = voltdm_get_voltage(sr->voltdm);
+
+	if (!volt) {
+		pr_warning("%s: Curr voltage unknown. Cannot enable %s\n",
+				__func__, sr->name);
+		return -ENODATA;
+	}
+
+	omap_vp_enable(sr->voltdm);
+	return sr_enable(sr->voltdm, volt);
+}
+
+static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
+{
+	sr_disable_errgen(sr->voltdm);
+	omap_vp_disable(sr->voltdm);
+	sr_disable(sr->voltdm);
+	if (is_volt_reset)
+		voltdm_reset(sr->voltdm);
+
+	return 0;
+}
+
+static int sr_class3_configure(struct omap_sr *sr)
+{
+	return sr_configure_errgen(sr->voltdm);
+}
+
+/* SR class3 structure */
+static struct omap_sr_class_data class3_data = {
+	.enable = sr_class3_enable,
+	.disable = sr_class3_disable,
+	.configure = sr_class3_configure,
+	.class_type = SR_CLASS3,
+};
+
+/* Smartreflex Class3 init API to be called from board file */
+static int __init sr_class3_init(void)
+{
+	pr_info("SmartReflex Class3 initialized\n");
+	return sr_register_class(&class3_data);
+}
+late_initcall(sr_class3_init);
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
new file mode 100644
index 0000000..cd751ef
--- /dev/null
+++ b/drivers/power/avs/smartreflex.c
@@ -0,0 +1,1117 @@
+/*
+ * OMAP SmartReflex Voltage Control
+ *
+ * Author: Thara Gopinath	<thara at ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara at ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970 at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+
+#include "smartreflex.h"
+
+#define SMARTREFLEX_NAME_LEN	16
+#define NVALUE_NAME_LEN		40
+#define SR_DISABLE_TIMEOUT	200
+
+/* sr_list contains all the instances of smartreflex module */
+static LIST_HEAD(sr_list);
+
+static struct omap_sr_class_data *sr_class;
+static struct omap_sr_pmic_data *sr_pmic_data;
+static struct dentry		*sr_dbg_dir;
+
+static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
+{
+	__raw_writel(value, (sr->base + offset));
+}
+
+static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
+					u32 value)
+{
+	u32 reg_val;
+
+	/*
+	 * Smartreflex error config register is special as it contains
+	 * certain status bits which if written a 1 into means a clear
+	 * of those bits. So in order to make sure no accidental write of
+	 * 1 happens to those status bits, do a clear of them in the read
+	 * value. This mean this API doesn't rewrite values in these bits
+	 * if they are currently set, but does allow the caller to write
+	 * those bits.
+	 */
+	if (sr->ip_type == SR_TYPE_V1 && offset == ERRCONFIG_V1)
+		mask |= ERRCONFIG_STATUS_V1_MASK;
+	else if (sr->ip_type == SR_TYPE_V2 && offset == ERRCONFIG_V2)
+		mask |= ERRCONFIG_VPBOUNDINTST_V2;
+
+	reg_val = __raw_readl(sr->base + offset);
+	reg_val &= ~mask;
+
+	value &= mask;
+
+	reg_val |= value;
+
+	__raw_writel(reg_val, (sr->base + offset));
+}
+
+static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
+{
+	return __raw_readl(sr->base + offset);
+}
+
+static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
+{
+	struct omap_sr *sr_info;
+
+	if (!voltdm) {
+		pr_err("%s: Null voltage domain passed!\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	list_for_each_entry(sr_info, &sr_list, node) {
+		if (voltdm == sr_info->voltdm)
+			return sr_info;
+	}
+
+	return ERR_PTR(-ENODATA);
+}
+
+static irqreturn_t sr_interrupt(int irq, void *data)
+{
+	struct omap_sr *sr_info = data;
+	u32 status = 0;
+
+	switch (sr_info->ip_type) {
+	case SR_TYPE_V1:
+		/* Read the status bits */
+		status = sr_read_reg(sr_info, ERRCONFIG_V1);
+
+		/* Clear them by writing back */
+		sr_write_reg(sr_info, ERRCONFIG_V1, status);
+		break;
+	case SR_TYPE_V2:
+		/* Read the status bits */
+		status = sr_read_reg(sr_info, IRQSTATUS);
+
+		/* Clear them by writing back */
+		sr_write_reg(sr_info, IRQSTATUS, status);
+		break;
+	default:
+		dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n",
+			sr_info->ip_type);
+		return IRQ_NONE;
+	}
+
+	if (sr_class->notify)
+		sr_class->notify(sr_info, status);
+
+	return IRQ_HANDLED;
+}
+
+static void sr_set_clk_length(struct omap_sr *sr)
+{
+	struct clk *sys_ck;
+	u32 sys_clk_speed;
+
+	if (cpu_is_omap34xx())
+		sys_ck = clk_get(NULL, "sys_ck");
+	else
+		sys_ck = clk_get(NULL, "sys_clkin_ck");
+
+	if (IS_ERR(sys_ck)) {
+		dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
+			__func__);
+		return;
+	}
+
+	sys_clk_speed = clk_get_rate(sys_ck);
+	clk_put(sys_ck);
+
+	switch (sys_clk_speed) {
+	case 12000000:
+		sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+		break;
+	case 13000000:
+		sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+		break;
+	case 19200000:
+		sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+		break;
+	case 26000000:
+		sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+		break;
+	case 38400000:
+		sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+		break;
+	default:
+		dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n",
+			__func__, sys_clk_speed);
+		break;
+	}
+}
+
+static void sr_set_regfields(struct omap_sr *sr)
+{
+	/*
+	 * For time being these values are defined in smartreflex.h
+	 * and populated during init. May be they can be moved to board
+	 * file or pmic specific data structure. In that case these structure
+	 * fields will have to be populated using the pdata or pmic structure.
+	 */
+	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
+		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+		sr->accum_data = OMAP3430_SR_ACCUMDATA;
+		if (!(strcmp(sr->name, "sr_mpu_iva"))) {
+			sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+			sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+		} else {
+			sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+			sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+		}
+	}
+}
+
+static void sr_start_vddautocomp(struct omap_sr *sr)
+{
+	if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+		dev_warn(&sr->pdev->dev,
+			"%s: smartreflex class driver not registered\n",
+			__func__);
+		return;
+	}
+
+	if (!sr_class->enable(sr))
+		sr->autocomp_active = true;
+}
+
+static void sr_stop_vddautocomp(struct omap_sr *sr)
+{
+	if (!sr_class || !(sr_class->disable)) {
+		dev_warn(&sr->pdev->dev,
+			"%s: smartreflex class driver not registered\n",
+			__func__);
+		return;
+	}
+
+	if (sr->autocomp_active) {
+		sr_class->disable(sr, 1);
+		sr->autocomp_active = false;
+	}
+}
+
+/*
+ * This function handles the intializations which have to be done
+ * only when both sr device and class driver regiter has
+ * completed. This will be attempted to be called from both sr class
+ * driver register and sr device intializtion API's. Only one call
+ * will ultimately succeed.
+ *
+ * Currently this function registers interrupt handler for a particular SR
+ * if smartreflex class driver is already registered and has
+ * requested for interrupts and the SR interrupt line in present.
+ */
+static int sr_late_init(struct omap_sr *sr_info)
+{
+	struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
+	struct resource *mem;
+	int ret = 0;
+
+	if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
+		ret = request_irq(sr_info->irq, sr_interrupt,
+				  0, sr_info->name, sr_info);
+		if (ret)
+			goto error;
+		disable_irq(sr_info->irq);
+	}
+
+	if (pdata && pdata->enable_on_init)
+		sr_start_vddautocomp(sr_info);
+
+	return ret;
+
+error:
+	iounmap(sr_info->base);
+	mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
+	release_mem_region(mem->start, resource_size(mem));
+	list_del(&sr_info->node);
+	dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
+		"interrupt handler. Smartreflex will"
+		"not function as desired\n", __func__);
+	kfree(sr_info);
+
+	return ret;
+}
+
+static void sr_v1_disable(struct omap_sr *sr)
+{
+	int timeout = 0;
+	int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
+			ERRCONFIG_MCUBOUNDINTST;
+
+	/* Enable MCUDisableAcknowledge interrupt */
+	sr_modify_reg(sr, ERRCONFIG_V1,
+			ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
+
+	/* SRCONFIG - disable SR */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+	/* Disable all other SR interrupts and clear the status as needed */
+	if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1)
+		errconf_val |= ERRCONFIG_VPBOUNDINTST_V1;
+	sr_modify_reg(sr, ERRCONFIG_V1,
+			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+			ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
+			errconf_val);
+
+	/*
+	 * Wait for SR to be disabled.
+	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
+	 */
+	sr_test_cond_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
+			     ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
+			     timeout);
+
+	if (timeout >= SR_DISABLE_TIMEOUT)
+		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+			__func__);
+
+	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+	sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
+			ERRCONFIG_MCUDISACKINTST);
+}
+
+static void sr_v2_disable(struct omap_sr *sr)
+{
+	int timeout = 0;
+
+	/* Enable MCUDisableAcknowledge interrupt */
+	sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
+
+	/* SRCONFIG - disable SR */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+	/*
+	 * Disable all other SR interrupts and clear the status
+	 * write to status register ONLY on need basis - only if status
+	 * is set.
+	 */
+	if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2)
+		sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+			ERRCONFIG_VPBOUNDINTST_V2);
+	else
+		sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+				0x0);
+	sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
+			IRQENABLE_MCUVALIDINT |
+			IRQENABLE_MCUBOUNDSINT));
+	sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
+			IRQSTATUS_MCVALIDINT |
+			IRQSTATUS_MCBOUNDSINT));
+
+	/*
+	 * Wait for SR to be disabled.
+	 * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
+	 */
+	sr_test_cond_timeout((sr_read_reg(sr, IRQSTATUS) &
+			     IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
+			     timeout);
+
+	if (timeout >= SR_DISABLE_TIMEOUT)
+		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+			__func__);
+
+	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+	sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
+	sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
+}
+
+static struct omap_sr_nvalue_table *sr_retrieve_nvalue_row(
+				struct omap_sr *sr,
+				unsigned long volt_nominal)
+{
+	int i;
+
+	if (!sr->nvalue_table) {
+		dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
+			__func__);
+		return NULL;
+	}
+
+	for (i = 0; i < sr->nvalue_count; i++) {
+		if (sr->nvalue_table[i].volt_nominal == volt_nominal)
+			return &sr->nvalue_table[i];
+	}
+
+	return NULL;
+}
+
+/* Public Functions */
+
+/**
+ * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the
+ *			 error generator module.
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the error generator module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_errgen(struct voltagedomain *voltdm)
+{
+	u32 sr_config, sr_errconfig, errconfig_offs;
+	u32 vpboundint_en, vpboundint_st;
+	u32 senp_en = 0, senn_en = 0;
+	u8 senp_shift, senn_shift;
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return PTR_ERR(sr);
+	}
+
+	if (!sr->clk_length)
+		sr_set_clk_length(sr);
+
+	senp_en = sr->senp_mod;
+	senn_en = sr->senn_mod;
+
+	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+		SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
+
+	switch (sr->ip_type) {
+	case SR_TYPE_V1:
+		sr_config |= SRCONFIG_DELAYCTRL;
+		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+		errconfig_offs = ERRCONFIG_V1;
+		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+		break;
+	case SR_TYPE_V2:
+		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+		errconfig_offs = ERRCONFIG_V2;
+		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+		break;
+	default:
+		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+			"module without specifying the ip\n", __func__);
+		return -EINVAL;
+	}
+
+	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+	sr_write_reg(sr, SRCONFIG, sr_config);
+	sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
+		(sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
+		(sr->err_minlimit <<  ERRCONFIG_ERRMINLIMIT_SHIFT);
+	sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
+		SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+		sr_errconfig);
+
+	/* Enabling the interrupts if the ERROR module is used */
+	sr_modify_reg(sr, errconfig_offs, (vpboundint_en | vpboundint_st),
+		      vpboundint_en);
+
+	return 0;
+}
+
+/**
+ * sr_disable_errgen() - Disables SmartReflex AVS module's errgen component
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * disable the error generator module inside the smartreflex module.
+ *
+ * Returns 0 on success and error value in case of failure.
+ */
+int sr_disable_errgen(struct voltagedomain *voltdm)
+{
+	u32 errconfig_offs;
+	u32 vpboundint_en, vpboundint_st;
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return PTR_ERR(sr);
+	}
+
+	switch (sr->ip_type) {
+	case SR_TYPE_V1:
+		errconfig_offs = ERRCONFIG_V1;
+		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+		break;
+	case SR_TYPE_V2:
+		errconfig_offs = ERRCONFIG_V2;
+		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+		break;
+	default:
+		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+			"module without specifying the ip\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Disable the interrupts of ERROR module */
+	sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
+
+	/* Disable the Sensor and errorgen */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0);
+
+	return 0;
+}
+
+/**
+ * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the
+ *			 minmaxavg module.
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the minmaxavg module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_minmax(struct voltagedomain *voltdm)
+{
+	u32 sr_config, sr_avgwt;
+	u32 senp_en = 0, senn_en = 0;
+	u8 senp_shift, senn_shift;
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return PTR_ERR(sr);
+	}
+
+	if (!sr->clk_length)
+		sr_set_clk_length(sr);
+
+	senp_en = sr->senp_mod;
+	senn_en = sr->senn_mod;
+
+	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+		SRCONFIG_SENENABLE |
+		(sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
+
+	switch (sr->ip_type) {
+	case SR_TYPE_V1:
+		sr_config |= SRCONFIG_DELAYCTRL;
+		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+		break;
+	case SR_TYPE_V2:
+		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+		break;
+	default:
+		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+			"module without specifying the ip\n", __func__);
+		return -EINVAL;
+	}
+
+	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+	sr_write_reg(sr, SRCONFIG, sr_config);
+	sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
+		(sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
+	sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
+
+	/*
+	 * Enabling the interrupts if MINMAXAVG module is used.
+	 * TODO: check if all the interrupts are mandatory
+	 */
+	switch (sr->ip_type) {
+	case SR_TYPE_V1:
+		sr_modify_reg(sr, ERRCONFIG_V1,
+			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+			ERRCONFIG_MCUBOUNDINTEN),
+			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
+			 ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
+			 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
+		break;
+	case SR_TYPE_V2:
+		sr_write_reg(sr, IRQSTATUS,
+			IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
+			IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
+		sr_write_reg(sr, IRQENABLE_SET,
+			IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
+			IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
+		break;
+	default:
+		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+			"module without specifying the ip\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ * sr_enable() - Enables the smartreflex module.
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ * @volt:	The voltage at which the Voltage domain associated with
+ *		the smartreflex module is operating at.
+ *		This is required only to program the correct Ntarget value.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * enable a smartreflex module. Returns 0 on success. Returns error
+ * value if the voltage passed is wrong or if ntarget value is wrong.
+ */
+int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
+{
+	struct omap_sr *sr = _sr_lookup(voltdm);
+	struct omap_sr_nvalue_table *nvalue_row;
+	int ret;
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return PTR_ERR(sr);
+	}
+
+	nvalue_row = sr_retrieve_nvalue_row(sr, volt);
+	if (!nvalue_row) {
+		dev_warn(&sr->pdev->dev, "%s: failure getting SR data for this voltage %ld\n",
+			 __func__, volt);
+		return -ENODATA;
+	}
+
+
+	/* errminlimit is opp dependent and hence linked to voltage */
+	sr->err_minlimit = nvalue_row->errminlimit;
+
+	pm_runtime_get_sync(&sr->pdev->dev);
+
+	/* Check if SR is already enabled. If yes do nothing */
+	if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
+		return 0;
+
+	/* Configure SR */
+	ret = sr_class->configure(sr);
+	if (ret)
+		return ret;
+
+	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_row->nvalue);
+
+	/* SRCONFIG - enable SR */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
+	return 0;
+}
+
+/**
+ * sr_disable() - Disables the smartreflex module.
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * disable a smartreflex module.
+ */
+void sr_disable(struct voltagedomain *voltdm)
+{
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return;
+	}
+
+	/* Check if SR clocks are already disabled. If yes do nothing */
+	if (pm_runtime_suspended(&sr->pdev->dev))
+		return;
+
+	/*
+	 * Disable SR if only it is indeed enabled. Else just
+	 * disable the clocks.
+	 */
+	if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
+		switch (sr->ip_type) {
+		case SR_TYPE_V1:
+			sr_v1_disable(sr);
+			break;
+		case SR_TYPE_V2:
+			sr_v2_disable(sr);
+			break;
+		default:
+			dev_err(&sr->pdev->dev, "UNKNOWN IP type %d\n",
+				sr->ip_type);
+		}
+	}
+
+	pm_runtime_put_sync_suspend(&sr->pdev->dev);
+}
+
+/**
+ * sr_register_class() - API to register a smartreflex class parameters.
+ * @class_data:	The structure containing various sr class specific data.
+ *
+ * This API is to be called by the smartreflex class driver to register itself
+ * with the smartreflex driver during init. Returns 0 on success else the
+ * error value.
+ */
+int sr_register_class(struct omap_sr_class_data *class_data)
+{
+	struct omap_sr *sr_info;
+
+	if (!class_data) {
+		pr_warning("%s:, Smartreflex class data passed is NULL\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	if (sr_class) {
+		pr_warning("%s: Smartreflex class driver already registered\n",
+			__func__);
+		return -EBUSY;
+	}
+
+	sr_class = class_data;
+
+	/*
+	 * Call into late init to do intializations that require
+	 * both sr driver and sr class driver to be initiallized.
+	 */
+	list_for_each_entry(sr_info, &sr_list, node)
+		sr_late_init(sr_info);
+
+	return 0;
+}
+
+/**
+ * omap_sr_enable() -  API to enable SR clocks and to call into the
+ *			registered smartreflex class enable API.
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to enable
+ * a particular smartreflex module. This API will do the initial
+ * configurations to turn on the smartreflex module and in turn call
+ * into the registered smartreflex class enable API.
+ */
+void omap_sr_enable(struct voltagedomain *voltdm)
+{
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return;
+	}
+
+	if (!sr->autocomp_active)
+		return;
+
+	if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+			"registered\n", __func__);
+		return;
+	}
+
+	sr_class->enable(sr);
+}
+
+/**
+ * omap_sr_disable() - API to disable SR without resetting the voltage
+ *			processor voltage
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable not to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable(struct voltagedomain *voltdm)
+{
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return;
+	}
+
+	if (!sr->autocomp_active)
+		return;
+
+	if (!sr_class || !(sr_class->disable)) {
+		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+			"registered\n", __func__);
+		return;
+	}
+
+	sr_class->disable(sr, 0);
+}
+
+/**
+ * omap_sr_disable_reset_volt() - API to disable SR and reset the
+ *				voltage processor voltage
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
+{
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return;
+	}
+
+	if (!sr->autocomp_active)
+		return;
+
+	if (!sr_class || !(sr_class->disable)) {
+		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+			"registered\n", __func__);
+		return;
+	}
+
+	sr_class->disable(sr, 1);
+}
+
+/**
+ * omap_sr_register_pmic() - API to register pmic specific info.
+ * @pmic_data:	The structure containing pmic specific data.
+ *
+ * This API is to be called from the PMIC specific code to register with
+ * smartreflex driver pmic specific info. Currently the only info required
+ * is the smartreflex init on the PMIC side.
+ */
+void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data)
+{
+	if (!pmic_data) {
+		pr_warning("%s: Trying to register NULL PMIC data structure"
+			"with smartreflex\n", __func__);
+		return;
+	}
+
+	sr_pmic_data = pmic_data;
+}
+
+/* PM Debug FS entries to enable and disable smartreflex. */
+static int omap_sr_autocomp_show(void *data, u64 *val)
+{
+	struct omap_sr *sr_info = data;
+
+	if (!sr_info) {
+		pr_warning("%s: omap_sr struct not found\n", __func__);
+		return -EINVAL;
+	}
+
+	*val = sr_info->autocomp_active;
+
+	return 0;
+}
+
+static int omap_sr_autocomp_store(void *data, u64 val)
+{
+	struct omap_sr *sr_info = data;
+
+	if (!sr_info) {
+		pr_warning("%s: omap_sr struct not found\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Sanity check */
+	if (val > 1) {
+		pr_warning("%s: Invalid argument %lld\n", __func__, val);
+		return -EINVAL;
+	}
+
+	/* control enable/disable only if there is a delta in value */
+	if (sr_info->autocomp_active != val) {
+		if (!val)
+			sr_stop_vddautocomp(sr_info);
+		else
+			sr_start_vddautocomp(sr_info);
+	}
+
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
+			omap_sr_autocomp_store, "%llu\n");
+
+static int __init omap_sr_probe(struct platform_device *pdev)
+{
+	struct omap_sr *sr_info;
+	struct omap_sr_data *pdata = pdev->dev.platform_data;
+	struct resource *mem, *irq;
+	struct dentry *nvalue_dir;
+	int i, ret = 0;
+
+	sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
+	if (!sr_info) {
+		dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
+			__func__);
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, sr_info);
+
+	if (!pdata) {
+		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+		ret = -EINVAL;
+		goto err_free_devinfo;
+	}
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem) {
+		dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
+		ret = -ENODEV;
+		goto err_free_devinfo;
+	}
+
+	mem = request_mem_region(mem->start, resource_size(mem),
+					dev_name(&pdev->dev));
+	if (!mem) {
+		dev_err(&pdev->dev, "%s: no mem region\n", __func__);
+		ret = -EBUSY;
+		goto err_free_devinfo;
+	}
+
+	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+	pm_runtime_enable(&pdev->dev);
+	pm_runtime_irq_safe(&pdev->dev);
+
+	sr_info->name = kasprintf(GFP_KERNEL, "sr_%s", pdata->name);
+	if (!sr_info->name) {
+		dev_err(&pdev->dev, "%s: Unable to alloc SR instance name\n",
+			__func__);
+		ret = -ENOMEM;
+		goto err_release_region;
+	}
+
+	sr_info->pdev = pdev;
+	sr_info->srid = pdev->id;
+	sr_info->voltdm = pdata->voltdm;
+	sr_info->nvalue_table = pdata->nvalue_table;
+	sr_info->nvalue_count = pdata->nvalue_count;
+	sr_info->senn_mod = pdata->senn_mod;
+	sr_info->senp_mod = pdata->senp_mod;
+	sr_info->autocomp_active = false;
+	sr_info->ip_type = pdata->ip_type;
+	sr_info->base = ioremap(mem->start, resource_size(mem));
+	if (!sr_info->base) {
+		dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
+		ret = -ENOMEM;
+		goto err_release_region;
+	}
+
+	if (irq)
+		sr_info->irq = irq->start;
+
+	sr_set_clk_length(sr_info);
+	sr_set_regfields(sr_info);
+
+	list_add(&sr_info->node, &sr_list);
+
+	/*
+	 * Call into late init to do intializations that require
+	 * both sr driver and sr class driver to be initiallized.
+	 */
+	if (sr_class) {
+		ret = sr_late_init(sr_info);
+		if (ret) {
+			pr_warning("%s: Error in SR late init\n", __func__);
+			goto err_iounmap;
+		}
+	}
+
+	dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
+	if (!sr_dbg_dir) {
+		sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
+		if (IS_ERR_OR_NULL(sr_dbg_dir)) {
+			ret = PTR_ERR(sr_dbg_dir);
+			pr_err("%s:sr debugfs dir creation failed(%d)\n",
+				__func__, ret);
+			goto err_iounmap;
+		}
+	}
+
+	sr_info->dbg_dir = debugfs_create_dir(sr_info->name, sr_dbg_dir);
+	if (IS_ERR_OR_NULL(sr_info->dbg_dir)) {
+		dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
+			__func__);
+		ret = PTR_ERR(sr_info->dbg_dir);
+		goto err_free_name;
+	}
+
+	(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
+			sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops);
+	(void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
+			&sr_info->err_weight);
+	(void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
+			&sr_info->err_maxlimit);
+
+	nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
+	if (IS_ERR_OR_NULL(nvalue_dir)) {
+		dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
+			"for n-values\n", __func__);
+		ret = PTR_ERR(nvalue_dir);
+		goto err_debugfs;
+	}
+
+	if (sr_info->nvalue_count == 0 || !sr_info->nvalue_table) {
+		dev_warn(&pdev->dev, "%s: %s: No Voltage table for the corresponding vdd. Cannot create debugfs entries for n-values\n",
+			 __func__, sr_info->name);
+		ret = -ENODATA;
+		goto err_debugfs;
+	}
+
+	for (i = 0; i < sr_info->nvalue_count; i++) {
+		char name[NVALUE_NAME_LEN + 1];
+
+		snprintf(name, sizeof(name), "volt_%lu",
+			 sr_info->nvalue_table[i].volt_nominal);
+		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
+				&(sr_info->nvalue_table[i].nvalue));
+		snprintf(name, sizeof(name), "errminlimit_%lu",
+			 sr_info->nvalue_table[i].volt_nominal);
+		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
+				&(sr_info->nvalue_table[i].errminlimit));
+	}
+
+	return ret;
+
+err_debugfs:
+	debugfs_remove_recursive(sr_info->dbg_dir);
+err_free_name:
+	kfree(sr_info->name);
+err_iounmap:
+	list_del(&sr_info->node);
+	iounmap(sr_info->base);
+err_release_region:
+	release_mem_region(mem->start, resource_size(mem));
+err_free_devinfo:
+	kfree(sr_info);
+
+	return ret;
+}
+
+static int __devexit omap_sr_remove(struct platform_device *pdev)
+{
+	struct omap_sr_data *pdata = pdev->dev.platform_data;
+	struct omap_sr *sr_info;
+	struct resource *mem;
+
+	if (!pdata) {
+		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+		return -EINVAL;
+	}
+
+	sr_info = _sr_lookup(pdata->voltdm);
+	if (IS_ERR(sr_info)) {
+		dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
+			__func__);
+		return PTR_ERR(sr_info);
+	}
+
+	if (sr_info->autocomp_active)
+		sr_stop_vddautocomp(sr_info);
+	if (sr_info->dbg_dir)
+		debugfs_remove_recursive(sr_info->dbg_dir);
+
+	list_del(&sr_info->node);
+	iounmap(sr_info->base);
+	kfree(sr_info->name);
+	kfree(sr_info);
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(mem->start, resource_size(mem));
+
+	return 0;
+}
+
+static void __devexit omap_sr_shutdown(struct platform_device *pdev)
+{
+	struct omap_sr_data *pdata = pdev->dev.platform_data;
+	struct omap_sr *sr_info;
+
+	if (!pdata) {
+		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+		return;
+	}
+
+	sr_info = _sr_lookup(pdata->voltdm);
+	if (IS_ERR(sr_info)) {
+		dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
+			__func__);
+		return;
+	}
+
+	if (sr_info->autocomp_active)
+		sr_stop_vddautocomp(sr_info);
+
+	return;
+}
+
+static struct platform_driver smartreflex_driver = {
+	.remove         = __devexit_p(omap_sr_remove),
+	.shutdown	= __devexit_p(omap_sr_shutdown),
+	.driver		= {
+		.name	= "smartreflex",
+	},
+};
+
+static int __init sr_init(void)
+{
+	int ret = 0;
+
+	/*
+	 * sr_init is a late init. If by then a pmic specific API is not
+	 * registered either there is no need for anything to be done on
+	 * the PMIC side or somebody has forgotten to register a PMIC
+	 * handler. Warn for the second condition.
+	 */
+	if (sr_pmic_data && sr_pmic_data->sr_pmic_init)
+		sr_pmic_data->sr_pmic_init();
+	else
+		pr_warning("%s: No PMIC hook to init smartreflex\n", __func__);
+
+	ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe);
+	if (ret) {
+		pr_err("%s: platform driver register failed for SR\n",
+			__func__);
+		return ret;
+	}
+
+	return 0;
+}
+late_initcall(sr_init);
+
+static void __exit sr_exit(void)
+{
+	platform_driver_unregister(&smartreflex_driver);
+}
+module_exit(sr_exit);
+
+MODULE_DESCRIPTION("OMAP Smartreflex Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/drivers/power/avs/smartreflex.h b/drivers/power/avs/smartreflex.h
new file mode 100644
index 0000000..dbfb554
--- /dev/null
+++ b/drivers/power/avs/smartreflex.h
@@ -0,0 +1,238 @@
+/*
+ * OMAP Smartreflex Defines and Routines
+ *
+ * Author: Thara Gopinath	<thara at ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara at ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970 at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DRIVERS_POWER_AVS_SMARTREFLEX_H
+#define __DRIVERS_POWER_AVS_SMARTREFLEX_H
+
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+
+#include <plat/smartreflex.h>
+#include <plat/voltage.h>
+
+/*
+ * Different Smartreflex IPs version. The v1 is the 65nm version used in
+ * OMAP3430. The v2 is the update for the 45nm version of the IP
+ * used in OMAP3630 and OMAP4430
+ */
+#define SR_TYPE_V1	1
+#define SR_TYPE_V2	2
+
+/* SMART REFLEX REG ADDRESS OFFSET */
+#define SRCONFIG		0x00
+#define SRSTATUS		0x04
+#define SENVAL			0x08
+#define SENMIN			0x0C
+#define SENMAX			0x10
+#define SENAVG			0x14
+#define AVGWEIGHT		0x18
+#define NVALUERECIPROCAL	0x1c
+#define SENERROR_V1		0x20
+#define ERRCONFIG_V1		0x24
+#define IRQ_EOI			0x20
+#define IRQSTATUS_RAW		0x24
+#define IRQSTATUS		0x28
+#define IRQENABLE_SET		0x2C
+#define IRQENABLE_CLR		0x30
+#define SENERROR_V2		0x34
+#define ERRCONFIG_V2		0x38
+
+/* Bit/Shift Positions */
+
+/* SRCONFIG */
+#define SRCONFIG_ACCUMDATA_SHIFT	22
+#define SRCONFIG_SRCLKLENGTH_SHIFT	12
+#define SRCONFIG_SENNENABLE_V1_SHIFT	5
+#define SRCONFIG_SENPENABLE_V1_SHIFT	3
+#define SRCONFIG_SENNENABLE_V2_SHIFT	1
+#define SRCONFIG_SENPENABLE_V2_SHIFT	0
+#define SRCONFIG_CLKCTRL_SHIFT		0
+
+#define SRCONFIG_ACCUMDATA_MASK		(0x3ff << 22)
+
+#define SRCONFIG_SRENABLE		BIT(11)
+#define SRCONFIG_SENENABLE		BIT(10)
+#define SRCONFIG_ERRGEN_EN		BIT(9)
+#define SRCONFIG_MINMAXAVG_EN		BIT(8)
+#define SRCONFIG_DELAYCTRL		BIT(2)
+
+/* AVGWEIGHT */
+#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT	2
+#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT	0
+
+/* NVALUERECIPROCAL */
+#define NVALUERECIPROCAL_SENPGAIN_SHIFT	20
+#define NVALUERECIPROCAL_SENNGAIN_SHIFT	16
+#define NVALUERECIPROCAL_RNSENP_SHIFT	8
+#define NVALUERECIPROCAL_RNSENN_SHIFT	0
+
+/* ERRCONFIG */
+#define ERRCONFIG_ERRWEIGHT_SHIFT	16
+#define ERRCONFIG_ERRMAXLIMIT_SHIFT	8
+#define ERRCONFIG_ERRMINLIMIT_SHIFT	0
+
+#define SR_ERRWEIGHT_MASK		(0x07 << 16)
+#define SR_ERRMAXLIMIT_MASK		(0xff << 8)
+#define SR_ERRMINLIMIT_MASK		(0xff << 0)
+
+#define ERRCONFIG_VPBOUNDINTEN_V1	BIT(31)
+#define ERRCONFIG_VPBOUNDINTST_V1	BIT(30)
+#define	ERRCONFIG_MCUACCUMINTEN		BIT(29)
+#define ERRCONFIG_MCUACCUMINTST		BIT(28)
+#define	ERRCONFIG_MCUVALIDINTEN		BIT(27)
+#define ERRCONFIG_MCUVALIDINTST		BIT(26)
+#define ERRCONFIG_MCUBOUNDINTEN		BIT(25)
+#define	ERRCONFIG_MCUBOUNDINTST		BIT(24)
+#define	ERRCONFIG_MCUDISACKINTEN	BIT(23)
+#define ERRCONFIG_VPBOUNDINTST_V2	BIT(23)
+#define ERRCONFIG_MCUDISACKINTST	BIT(22)
+#define ERRCONFIG_VPBOUNDINTEN_V2	BIT(22)
+
+#define ERRCONFIG_STATUS_V1_MASK	(ERRCONFIG_VPBOUNDINTST_V1 | \
+					ERRCONFIG_MCUACCUMINTST | \
+					ERRCONFIG_MCUVALIDINTST | \
+					ERRCONFIG_MCUBOUNDINTST | \
+					ERRCONFIG_MCUDISACKINTST)
+/* IRQSTATUS */
+#define IRQSTATUS_MCUACCUMINT		BIT(3)
+#define IRQSTATUS_MCVALIDINT		BIT(2)
+#define IRQSTATUS_MCBOUNDSINT		BIT(1)
+#define IRQSTATUS_MCUDISABLEACKINT	BIT(0)
+
+/* IRQENABLE_SET and IRQENABLE_CLEAR */
+#define IRQENABLE_MCUACCUMINT		BIT(3)
+#define IRQENABLE_MCUVALIDINT		BIT(2)
+#define IRQENABLE_MCUBOUNDSINT		BIT(1)
+#define IRQENABLE_MCUDISABLEACKINT	BIT(0)
+
+/* Common Bit values */
+
+#define SRCLKLENGTH_12MHZ_SYSCLK	0x3c
+#define SRCLKLENGTH_13MHZ_SYSCLK	0x41
+#define SRCLKLENGTH_19MHZ_SYSCLK	0x60
+#define SRCLKLENGTH_26MHZ_SYSCLK	0x82
+#define SRCLKLENGTH_38MHZ_SYSCLK	0xC0
+
+/*
+ * 3430 specific values. Maybe these should be passed from board file or
+ * pmic structures.
+ */
+#define OMAP3430_SR_ACCUMDATA		0x1f4
+
+#define OMAP3430_SR1_SENPAVGWEIGHT	0x03
+#define OMAP3430_SR1_SENNAVGWEIGHT	0x03
+
+#define OMAP3430_SR2_SENPAVGWEIGHT	0x01
+#define OMAP3430_SR2_SENNAVGWEIGHT	0x01
+
+#define OMAP3430_SR_ERRWEIGHT		0x04
+#define OMAP3430_SR_ERRMAXLIMIT		0x02
+
+/**
+ * test_cond_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ *
+ * Copied from omap_test_timeout
+ */
+#define sr_test_cond_timeout(cond, timeout, index)		\
+({								\
+	for (index = 0; index < timeout; index++) {		\
+		if (cond)					\
+			break;					\
+		udelay(1);					\
+	}							\
+})
+
+/**
+ * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
+ *				pmic specific info to smartreflex driver
+ *
+ * @sr_pmic_init:	API to initialize smartreflex on the PMIC side.
+ */
+struct omap_sr_pmic_data {
+	void (*sr_pmic_init) (void);
+};
+
+
+#ifdef CONFIG_POWER_AVS_OMAP
+/*
+ * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
+ * The smartreflex class driver should pass the class type.
+ * Should be used to populate the class_type field of the
+ * omap_smartreflex_class_data structure.
+ */
+#define SR_CLASS1	0x1
+#define SR_CLASS2	0x2
+#define SR_CLASS3	0x3
+
+/**
+ * struct omap_sr_class_data - Smartreflex class driver info
+ *
+ * @enable:		API to enable a particular class smaartreflex.
+ * @disable:		API to disable a particular class smartreflex.
+ * @configure:		API to configure a particular class smartreflex.
+ * @notify:		API to notify the class driver about an event in SR.
+ *			Not needed for class3.
+ * @notify_flags:	specify the events to be notified to the class driver
+ * @class_type:		specify which smartreflex class.
+ *			Can be used by the SR driver to take any class
+ *			based decisions.
+ */
+struct omap_sr_class_data {
+	int (*enable)(struct omap_sr *sr);
+	int (*disable)(struct omap_sr *sr, int is_volt_reset);
+	int (*configure)(struct omap_sr *sr);
+	int (*notify)(struct omap_sr *sr, u32 status);
+	u8 notify_flags;
+	u8 class_type;
+};
+
+/* Smartreflex module enable/disable interface */
+void omap_sr_enable(struct voltagedomain *voltdm);
+void omap_sr_disable(struct voltagedomain *voltdm);
+void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
+
+/* API to register the pmic specific data with the smartreflex driver. */
+void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
+
+/* Smartreflex driver hooks to be called from Smartreflex class driver */
+int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
+void sr_disable(struct voltagedomain *voltdm);
+int sr_configure_errgen(struct voltagedomain *voltdm);
+int sr_disable_errgen(struct voltagedomain *voltdm);
+int sr_configure_minmax(struct voltagedomain *voltdm);
+
+/* API to register the smartreflex class driver with the smartreflex driver */
+int sr_register_class(struct omap_sr_class_data *class_data);
+#else
+static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
+static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+static inline void omap_sr_disable_reset_volt(
+		struct voltagedomain *voltdm) {}
+static inline void omap_sr_register_pmic(
+		struct omap_sr_pmic_data *pmic_data) {}
+#endif
+#endif
-- 
1.7.5.4



From plagnioj at jcrosoft.com  Thu Mar 15 12:34:11 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 15 Mar 2012 17:34:11 +0100
Subject: [PULL 01/02 v2] AT91 DT2 pull request
Message-ID: <20120315163411.GC7757@game.jcrosoft.org>

Hi Arnd,

	please find a pull with DT update for AT91
	based on cleanup2 + DT previously pull

	with :

	 - OF: boolean
	 - NAND (with generic bining and at91 fixed)
	 - RAAM Controller
	 - i2c/gpio (binding + soc)
	 - PMC
	 - Reset Controller
	 - Shutdown Controller
	 - USB ECHI & OHCI

	v2 add missing USB host (Acked)

The following changes since commit f75622f4679479d352d2fa83e0d84c6c13cfcb5f:

  ARM: at91: at91sam9x5cm/dt: add leds support (2012-03-01 22:34:22 +0800)

are available in the git repository at:
  git://github.com/at91linux/linux-at91.git at91-3.4-cleanup2-DT2

Jean-Christophe PLAGNIOL-VILLARD (23):
      ATMEL: fix nand ecc support
      mtd/atmel_nand: add on_flash_bbt to enable the use of On Flash BBT
      ARM: at91: enable on flash bbt for Atmel Reference and DT boards
      of: introduce helper to manage boolean
      of/mtd/nand: add generic bindings and helpers
      atmel/nand: add DT support
      ARM: at91: sam9x5 add nand support
      i2c/gpio: add DT support
      ARM: at91: sam9g20 add i2c DT support
      ARM: at91: usb_a9g20 add DT i2c support
      ARM: at91: sam9g45 add i2c DT support
      ARM: at91: sam9x5 add i2c DT support
      ARM: at91/dt: add Calao DAB-MMX daugther board support for USB-A9G20
      ARM: at91/dt: add specific DT soc init
      ARM: at91: add pmc DT support
      ARM: at91: always enable sam9 restart
      ARM: at91: add RSTC (Reset Controller) dt support
      ARM: at91: add ram controller DT support
      ARM: at91: add Shutdown Controller (SHDWC) DT support
      ARM: at91: usb ohci add dt support
      ARM: at91: dt: enable usb ohci for sam9g20, sam9g45 amd sam9x5
      ARM: at91: usb ehci add dt support
      ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5

 .../devicetree/bindings/arm/atmel-at91.txt         |   60 ++++++++
 .../devicetree/bindings/arm/atmel-pmc.txt          |   11 ++
 .../devicetree/bindings/gpio/gpio_i2c.txt          |   32 ++++
 .../devicetree/bindings/mtd/atmel-nand.txt         |   41 +++++
 Documentation/devicetree/bindings/mtd/nand.txt     |    7 +
 .../devicetree/bindings/usb/atmel-usb.txt          |   31 ++++
 arch/arm/boot/dts/at91sam9g20.dtsi                 |   56 +++++++
 arch/arm/boot/dts/at91sam9g25ek.dts                |   14 ++-
 arch/arm/boot/dts/at91sam9g45.dtsi                 |   64 ++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts             |   46 ++++++-
 arch/arm/boot/dts/at91sam9x5.dtsi                  |   88 +++++++++++
 arch/arm/boot/dts/at91sam9x5cm.dtsi                |   45 ++++++
 arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi           |   96 ++++++++++++
 arch/arm/boot/dts/usb_a9g20.dts                    |   69 +++++++++-
 arch/arm/configs/at91sam9g20_defconfig             |    3 +
 arch/arm/mach-at91/Kconfig                         |   10 +-
 arch/arm/mach-at91/at91sam9260.c                   |    1 +
 arch/arm/mach-at91/at91sam9g45.c                   |    2 +
 arch/arm/mach-at91/at91sam9x5.c                    |   17 +--
 arch/arm/mach-at91/board-afeb-9260v1.c             |    1 +
 arch/arm/mach-at91/board-cam60.c                   |    1 +
 arch/arm/mach-at91/board-cpu9krea.c                |    1 +
 arch/arm/mach-at91/board-dt.c                      |   57 +-------
 arch/arm/mach-at91/board-kb9202.c                  |    1 +
 arch/arm/mach-at91/board-neocore926.c              |    1 +
 arch/arm/mach-at91/board-qil-a9260.c               |    2 +
 arch/arm/mach-at91/board-rm9200dk.c                |    2 +
 arch/arm/mach-at91/board-sam9-l9260.c              |    1 +
 arch/arm/mach-at91/board-sam9260ek.c               |    2 +
 arch/arm/mach-at91/board-sam9261ek.c               |    2 +
 arch/arm/mach-at91/board-sam9263ek.c               |    2 +
 arch/arm/mach-at91/board-sam9g20ek.c               |    2 +
 arch/arm/mach-at91/board-sam9m10g45ek.c            |    2 +
 arch/arm/mach-at91/board-sam9rlek.c                |    2 +
 arch/arm/mach-at91/board-snapper9260.c             |    1 +
 arch/arm/mach-at91/board-stamp9g20.c               |    1 +
 arch/arm/mach-at91/board-usb-a926x.c               |    2 +
 arch/arm/mach-at91/board-yl-9200.c                 |    1 +
 arch/arm/mach-at91/clock.c                         |   56 +++++++-
 arch/arm/mach-at91/generic.h                       |    2 +
 arch/arm/mach-at91/include/mach/at91_shdwc.h       |    4 +-
 arch/arm/mach-at91/include/mach/at91sam9x5.h       |    5 -
 arch/arm/mach-at91/include/mach/board.h            |   15 +--
 arch/arm/mach-at91/pm.c                            |   13 --
 arch/arm/mach-at91/setup.c                         |  158 ++++++++++++++++++++
 arch/avr32/boards/atngw100/setup.c                 |    1 +
 arch/avr32/boards/atstk1000/atstk1002.c            |    1 +
 arch/avr32/mach-at32ap/include/mach/board.h        |   13 +--
 drivers/i2c/busses/i2c-gpio.c                      |   94 +++++++++---
 drivers/mtd/nand/atmel_nand.c                      |  136 ++++++++++++-----
 drivers/of/Kconfig                                 |    4 +
 drivers/of/Makefile                                |    1 +
 drivers/of/of_mtd.c                                |   85 +++++++++++
 drivers/usb/Kconfig                                |    2 +-
 drivers/usb/host/ehci-atmel.c                      |   24 +++-
 drivers/usb/host/ohci-at91.c                       |  101 ++++++++++++-
 include/linux/of.h                                 |   16 ++
 include/linux/of_mtd.h                             |   19 +++
 include/linux/platform_data/atmel.h                |   27 ++++
 59 files changed, 1363 insertions(+), 191 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel-pmc.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio_i2c.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/atmel-nand.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/nand.txt
 create mode 100644 Documentation/devicetree/bindings/usb/atmel-usb.txt
 create mode 100644 arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
 create mode 100644 drivers/of/of_mtd.c
 create mode 100644 include/linux/of_mtd.h
 create mode 100644 include/linux/platform_data/atmel.h

Best Regards,
J.


From b04825 at freescale.com  Thu Mar 15 12:47:05 2012
From: b04825 at freescale.com (Timur Tabi)
Date: Thu, 15 Mar 2012 11:47:05 -0500
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120315142115.GB6065@S2101-09.ap.freescale.net>
References: <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315130253.GA6065@S2101-09.ap.freescale.net>
 <4F61F080.4090800@freescale.com>
 <20120315142115.GB6065@S2101-09.ap.freescale.net>
Message-ID: <4F621D09.2080806@freescale.com>

Shawn Guo wrote:
> sound {
>       compatible = "fsl,imx51-babbage-sgtl5000",
>                    "fsl,imx-audio-sgtl5000";
>       model = "imx51-babbage-sgtl5000";
>       ssi-controller = <&ssi1, &ssi2>;
>       audio-codec = <&sgtl5000_1, &sgtl5000_2>;
>       mux-int-port = <1>;
>       mux-ext-port = <3>;
> };

Based on Mark's other email, I would rather see this:

sound1 {
      compatible = "fsl,imx51-babbage-sgtl5000",
                   "fsl,imx-audio-sgtl5000";
      model = "imx51-babbage-sgtl5000";
      ssi-controller = <&ssi1>;
      audio-codec = <&sgtl5000_1>;
      mux-int-port = <1>;
      mux-ext-port = <3>;
};

sound2 {
      compatible = "fsl,imx51-babbage-sgtl5000",
                   "fsl,imx-audio-sgtl5000";
      model = "imx51-babbage-sgtl5000";
      ssi-controller = <&ssi2>;
      audio-codec = <&sgtl5000_2>;
      mux-int-port = <1>;
      mux-ext-port = <3>;
};

(ignoring for the moment that I have no idea what the mux-xxx-port values
in sound2 should be)

This makes it clear that ssi1 connects only to sgtl5000_1.

If you're okay with this, then please update the documentation accordingly.

-- 
Timur Tabi
Linux kernel developer at Freescale



From dmitry.torokhov at gmail.com  Thu Mar 15 12:50:31 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Thu, 15 Mar 2012 09:50:31 -0700
Subject: [PATCH 0/6] AT91 drivers Kconfig cleanup
In-Reply-To: <cover.1331826095.git.nicolas.ferre@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
Message-ID: <7104123.IANagkT9hm@dtor-d630.eng.vmware.com>

On Thursday, March 15, 2012 04:57:16 PM Nicolas Ferre wrote:
> This is a series which deals with AT91 drivers Kconfig entries. Its goal is
> to remove too restrictive dependencies on SoC names.
> This will allow to add support for newer SoC seamlessly.
> 
> One question remains: should I submit those patches through dedicated
> sub-maintainer's git trees or can I queue the whole series in arm-soc?

I'm fine if you queue input piece through arm-soc.

Thanks.

-- 
Dmitry


From lost.distance at yahoo.com  Thu Mar 15 12:55:26 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Thu, 15 Mar 2012 16:55:26 +0000 (GMT)
Subject: [GIT PULL][for v3.4] pull request from board-specific branch in
 arch-pxa
In-Reply-To: <201203151604.58969.arnd@arndb.de>
Message-ID: <1331830526.23927.YahooMailClassic@web29014.mail.ird.yahoo.com>

--- On Thu, 15/3/12, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 14 March 2012, Haojian
> Zhuang wrote:
> > First, please help to revert one commit
> 43de6a7dda6e9a7345e2 on
> > arnd/pxa/board branch of arm-soc.git first. Since this
> commit is
> > duplicated, and it's already merged into v3.3-rc7. I'm
> sorry on
> > inconvenience.
> > 
> > commit 43de6a7dda6e9a7345e218e688f2092f991126f0
> > Author: Haojian Zhuang <haojian.zhuang at marvell.com>
> > Date:???Tue Feb 28 10:57:48 2012 +0800
> > 
> >? ???ARM: pxa: add dummy clock for
> pxa25x and pxa27x
> > 
> 
> I need clarification on this:
> 
> I can see the clock was added in 389eda15e "ARM: pxa: add
> clk support in
> gpio driver" as well as 7557c175f6 "ARM: pxa: add dummy
> clock for sa1100-rtc",
> but removed in a55b5ada "Revert "ARM: pxa: add dummy clock
> for sa1100-rtc""
> and then added again in bbdc818b2 "ARM: pxa: add dummy clock
> for pxa25x
> and pxa27x". I want to make sure I'm not making the mess any
> bigger than
> it already is. So you want the dummy clocks for pxa25x and
> pxa27x removed
> again, never to come back, right?

The dummy clocks for pxa25x and pxa27x need to be present. If the dummy
clock for pxa27x is not present, my hx4700 hangs on boot.

Consequently linux-3.3-rc7 is correct.

Paul


From tony at atomide.com  Thu Mar 15 12:56:27 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 15 Mar 2012 09:56:27 -0700
Subject: [PATCH 5/6] ARM: OMAP2+: I2C: always compile I2C reset code,
 even if I2C driver is not built
In-Reply-To: <E1S87xA-0000N4-2z@rmk-PC.arm.linux.org.uk>
References: <20120315102845.GB16389@n2100.arm.linux.org.uk>
 <E1S87xA-0000N4-2z@rmk-PC.arm.linux.org.uk>
Message-ID: <20120315165626.GX12083@atomide.com>

* Paul Walmsley <paul at pwsan.com> [120315 03:33]:
> During kernel init, we reset all IP blocks on the OMAP that we can,
> even if there is no driver compiled for that IP block.  Unlike most IP
> blocks, the I2C block requires some extra programming for this to
> work.  This reset code is incorrectly omitted when the I2C driver is
> deselected.  In this circumstance, the build breaks.  Fix by compiling
> the I2C reset code unconditionally.

This one is commit ed8dfd22ea2533a1b169881c3de94be8daa0e297 in
arm-soc/for-next.

Regards,

Tony


From tony at atomide.com  Thu Mar 15 12:59:33 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 15 Mar 2012 09:59:33 -0700
Subject: [PATCH 4/6] ARM: OMAP: fix missing __devexit_p() annotations
In-Reply-To: <CAORVsuUVC4hpotK=eybA=Eqtfg0+PivjwRUENjCwcLG2dp1Ucg@mail.gmail.com>
References: <20120315102845.GB16389@n2100.arm.linux.org.uk>
 <E1S87wp-0000Mz-V8@rmk-PC.arm.linux.org.uk>
 <CAORVsuUVC4hpotK=eybA=Eqtfg0+PivjwRUENjCwcLG2dp1Ucg@mail.gmail.com>
Message-ID: <20120315165932.GY12083@atomide.com>

* Jean Pihet <jean.pihet at newoldbits.com> [120315 04:09]:
> Russell,
> 
> On Thu, Mar 15, 2012 at 11:30 AM, Russell King
> <rmk+kernel at arm.linux.org.uk> wrote:
> > Missing __devexit_p() annotations in driver structures for remove functions
> > marked with __devexit is waiting for build errors to happen, such as:
> >
> > `omap_system_dma_remove' referenced in section `.data' of arch/arm/plat-omap/bui
> > lt-in.o: defined in discarded section `.devexit.text' of arch/arm/plat-omap/buil
> > t-in.o
> >
> > Add the necessary annotation, and as a result of audit, fix others which
> > are also missing in arch/arm/*omap*.
> >
> > Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> > Acked-by: Tony Lindgren <tony at atomide.com>
> > ---
> > ?arch/arm/mach-omap2/smartreflex.c | ? ?2 +-
> > ?arch/arm/plat-omap/dma.c ? ? ? ? ?| ? ?2 +-
> > ?2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
> > index 7e755bb..47c77a1 100644
> > --- a/arch/arm/mach-omap2/smartreflex.c
> > +++ b/arch/arm/mach-omap2/smartreflex.c
> > @@ -1012,7 +1012,7 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
> > ?}
> >
> > ?static struct platform_driver smartreflex_driver = {
> > - ? ? ? .remove ? ? ? ? = omap_sr_remove,
> > + ? ? ? .remove ? ? ? ? = __devexit_p(omap_sr_remove),
> > ? ? ? ?.driver ? ? ? ? = {
> > ? ? ? ? ? ? ? ?.name ? = "smartreflex",
> > ? ? ? ?},
> Tony already has this change in his master branch, commit
> 149f1d5c8d2fd6879cdf93ca70f1cb745e698a1e ('ARM: OMAP2+: Fix devexit
> for smartreflex when CONFIG_HOTPLUG is not set').

Also same commit in arm-soc/for-next.

Regards,

Tony


From khilman at ti.com  Thu Mar 15 13:00:35 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 15 Mar 2012 10:00:35 -0700
Subject: [GIT PULL] cpufreq: OMAP updates for v3.4
In-Reply-To: <20120307203031.GA7672@redhat.com>
References: <87y5rci2na.fsf@ti.com> <20120307203031.GA7672@redhat.com>
Message-ID: <4F622033.6030403@ti.com>

Hi Dave,

On 03/07/2012 12:30 PM, Dave Jones wrote:
> On Wed, Mar 07, 2012 at 12:20:41PM -0800, Kevin Hilman wrote:
>   >  Dave,
>   >
>   >  Please pull the following OMAP CPUfreq driver changes for v3.4.
>
> pulled, thanks.

Looks like these got pulled into your fixes branch, but I don't see them 
in linux-next?  Are these on their way upstream?

Kevin


From lee.jones at linaro.org  Thu Mar 15 13:08:29 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 15 Mar 2012 17:08:29 +0000
Subject: [GIT PULL] [for v3.4] Pull request containing ux500 DT enablement
Message-ID: <4F62220D.1090106@linaro.org>

The following changes since commit fff9a13341312c8d0f06e04c1345e855528b03da:

  ARM: ux500: CONFIG: Enable Device Tree support for future endeavours (2012-03-15 16:33:54 +0000)

are available in the git repository at:
  git://git.linaro.org/people/ljones/linux-3.0-ux500.git device-tree-snowball-ux500

Arnd Bergmann (3):
      ARM: ux500: Initial Device Tree support for Snowball
      ARM: ux500: combine the board init functions for DT boot
      ARM: ux500: split dts file for snowball into generic part

Lee Jones (5):
      ARM: ux500: db8500: list most devices in the snowball device tree
      ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt Controller) in Device Tree
      ARM: ux500: Enable PL011 AMBA UART Controller for Device Tree
      ARM: ux500: Enable PL310 Level 2 Cache Controller in Device Tree
      ARM: ux500: Enable PL022 SSP Controller in Device Tree

 arch/arm/boot/dts/db8500.dtsi      |  269 ++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/snowball.dts     |  139 +++++++++++++++++++
 arch/arm/mach-ux500/Makefile.boot  |    1 +
 arch/arm/mach-ux500/board-mop500.c |   99 +++++++++++++-
 arch/arm/mach-ux500/cache-l2x0.c   |    7 +-
 arch/arm/mach-ux500/cpu.c          |   12 ++-
 6 files changed, 523 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/boot/dts/db8500.dtsi
 create mode 100644 arch/arm/boot/dts/snowball.dts


-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515 
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From khilman at ti.com  Thu Mar 15 13:10:19 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 15 Mar 2012 10:10:19 -0700
Subject: [PATCH 6/6] ARM: OMAP: fix cpufreq build
In-Reply-To: <E1S87xU-0000N8-6u@rmk-PC.arm.linux.org.uk> (Russell King's
 message of "Thu, 15 Mar 2012 10:31:00 +0000")
References: <20120315102845.GB16389@n2100.arm.linux.org.uk>
 <E1S87xU-0000N8-6u@rmk-PC.arm.linux.org.uk>
Message-ID: <87aa3hdc3o.fsf@ti.com>

Russell King <rmk+kernel at arm.linux.org.uk> writes:

> OMAPs cpufreq requires the frequency table support, but nothing ensures
> that this is selected.  This can result in configurations which fail to
> build:
>
> drivers/built-in.o:(.data+0x5238): undefined reference to `cpufreq_freq_attr_scaling_available_freqs'
> drivers/cpufreq/omap-cpufreq.c:88: undefined reference to `cpufreq_frequency_table_target'
> drivers/cpufreq/omap-cpufreq.c:60: undefined reference to `cpufreq_frequency_table_verify'
> drivers/cpufreq/omap-cpufreq.c:186: undefined reference to `cpufreq_frequency_table_cpuinfo'
> drivers/cpufreq/omap-cpufreq.c:190: undefined reference to `cpufreq_frequency_table_get_attr'
>
> Fix this by introducing a new configuration variable and having that
> select CPU_FREQ_TABLE.
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---
>  arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c |    2 +-
>  arch/arm/mach-omap2/clock.c                  |    2 +-
>  arch/arm/mach-omap2/clock.h                  |    2 +-
>  arch/arm/plat-omap/clock.c                   |    2 +-
>  arch/arm/plat-omap/include/plat/clock.h      |    4 ++--

The arch/arm/* stuff is all code that has been removed, but the pull
request didn't make it in time for v3.4:

   http://www.spinics.net/lists/arm-kernel/msg164545.html

Initially, this was intended as a cleanup because it was just dead code
removal, but since we missed v3.4, maybe we should pull out 
"ARM: OMAP: clock: cleanup CPUfreq leftovers" and submit for 3.4-rc.

>  drivers/cpufreq/Kconfig.arm                  |    5 +++++
>  drivers/cpufreq/Makefile                     |    2 +-

This change was included in my CPUfreq pull request to Dave Jones.  He
has pulled it into his fixes branch[1], but I don't see it upstream.
I've just sent a mail to Dave asking about it.

Kevin

[1] git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq.git fixes



From broonie at opensource.wolfsonmicro.com  Thu Mar 15 13:11:13 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 15 Mar 2012 17:11:13 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F621C60.5090700@freescale.com>
References: <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
Message-ID: <20120315171112.GP3138@opensource.wolfsonmicro.com>

On Thu, Mar 15, 2012 at 11:44:16AM -0500, Timur Tabi wrote:
> Mark Brown wrote:

> > The SoC is the bit of silicon with the CPU and other devices on it like
> > the DMA controller and SSI or whatever ports.  The card is the PCB this
> > has been soldered down onto.

> Well, I asked about the difference between the soc BINDING and the card
> BINDING.  On PowerPC, at least, there's no distinct binding for either.
> For example, I2C devices are on the PCB, but they're listed as child nodes
> of the I2C controller, which is on the SoC.

Right, but this is the problem in a nutshell - there's nowhere to put
the board binding so the SoC code has to know about and do it.

> However, I don't like the way this is being represented as a PowerPC vs.
> ARM issue, because that's just not correct.  It's an "old binding" vs "new
> binding" issue.  For example:

I think that's just creeping in because the old binding is the existing
practice on PowerPC.

> +	/*
> +	 * In case of imx, the machine driver uses new binding which does
> +	 * not require SSI driver to trigger machine driver's probe, but
> +	 * the pcm device needs to be registered here.
> +	 */
> +	if (ssi_private->ssi_on_imx) {
> +		ssi_private->imx_pcm_pdev =
> +			platform_device_register_simple("imx-pcm-audio",

> This prohibits me from using the new binding on any future PowerPC parts,
> because it clearly says "iMX" on everything.

So long as it's internal to the code (which the above is) I don't think
it really matters, the code can be changed later.  We need to do
something about DMA controllers in general, and there was some recent
discussion on the DT list about a generic binding for them, so leaving
the code as-is with nothing in the DT itself seems like a good place to
leave things initially.
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From tony at atomide.com  Thu Mar 15 13:14:00 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 15 Mar 2012 10:14:00 -0700
Subject: [PATCH 02/10] ARM: OMAP2+: SmartReflex: move the platform
 specific macros in plat-omap
In-Reply-To: <1331829845-9526-3-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
 <1331829845-9526-3-git-send-email-j-pihet@ti.com>
Message-ID: <20120315171359.GA7276@atomide.com>

* jean.pihet at newoldbits.com <jean.pihet at newoldbits.com> [120315 09:47]:
> From: Jean Pihet <j-pihet at ti.com>
> 
> Move the platform specific macros from the smartreflex header file
> (arch/arm/mach-omap2/smartreflex.h) in a new header file in plat-omap
> (arch/arm/plat-omap/include/plat/smartreflex.h).
> 
> This change makes the SmartReflex implementation ready for the move
> to drivers/.

Glad to see this happening!

This would be better located in linux/power/smartreflex.h rather than
plat/smartreflex.h.

Regards,

Tony


From arnd at arndb.de  Thu Mar 15 13:32:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 17:32:12 +0000
Subject: linux-next: build failure after merge of the final tree (arm-soc
 tree related)
In-Reply-To: <20120315172213.GC20243@titan.lakedaemon.net>
References: <20120315105901.7b10c9f4de9374a613436988@canb.auug.org.au>
 <201203151639.38223.arnd@arndb.de>
 <20120315172213.GC20243@titan.lakedaemon.net>
Message-ID: <201203151732.12852.arnd@arndb.de>

On Thursday 15 March 2012, Jason Cooper wrote:
> On Thu, Mar 15, 2012 at 04:39:38PM +0000, Arnd Bergmann wrote:
> > On Thursday 15 March 2012, Jason Cooper wrote:
> > > That's my mistake.  I did a pull request for the wrong branch.  Olof,
> > > could you please drop the offending branch and I'll submit a new pull
> > > request once I have a chance to test Arnd's irq patch?
> > 
> > I reverted this in the for-next branch for now. The two initial patches
> > from the kirkwood/board branch are still present.
> 
> Okay, thanks.  I've rebased onto next/boards and merged the
> depends/irqdomain branch.  I'm making progress, but not finished yet.

Ok. I hope we can still make it for v3.4, but I think it won't be
much of a problem if not -- it will get merged into linux-next
just after v3.4-rc1 in case we don't make it, and then you have
plenty of time to improve it further.

> How is a pull-request done in the above scenario?  is my merge commit
> included in the series?  what is the pull-request based on?
> next/boards, or depends/irqdomain?

You should base it on depends/irqdomain.

	Arnd


From paul at pwsan.com  Thu Mar 15 13:32:30 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 15 Mar 2012 11:32:30 -0600 (MDT)
Subject: [PATCH 1/2] ARM: OMAP: powerdomain: Wait for powerdomain
 transition in pwrdm_state_switch()
In-Reply-To: <1331562873-29535-2-git-send-email-santosh.shilimkar@ti.com>
References: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
 <1331562873-29535-2-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <alpine.DEB.2.00.1203151129160.26218@utopia.booyaka.com>

On Mon, 12 Mar 2012, Santosh Shilimkar wrote:

> Commit b1cbdb00d{OMAP: clockdomain: Wait for powerdomain to be ON
> when using clockdomain force wakeup} was assuming that pwrdm_state_switch()
> does wait for the powerdomain transition which is not the case.
> 
> Fix this API by adding the pwrdm_wait_transition().
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> CC: Rajendra Nayak <rnayak at ti.com>
> CC: Paul Walmsley <paul at pwsan.com>

Acked-by: Paul Walmsley <paul at pwsan.com>

Sounds like this fixes a major kernel oops bug for Tony so this should go 
in ASAP to v3.3-rc series.


- Paul


From linux at arm.linux.org.uk  Thu Mar 15 13:32:56 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 17:32:56 +0000
Subject: [PATCH 2/5] MMC: mmci: Seperate ARM variants from generic code
In-Reply-To: <1331734803-17954-3-git-send-email-lee.jones@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <1331734803-17954-3-git-send-email-lee.jones@linaro.org>
Message-ID: <20120315173256.GD15988@n2100.arm.linux.org.uk>

On Wed, Mar 14, 2012 at 02:20:00PM +0000, Lee Jones wrote:
> This is a step in the right direction for future Device
> Tree support. It will allow variant specific attributes
> to be collected from a Device Tree without overloading
> the MMCI core. It will also provide additional future
> variants a cleaner way to add support.

NAK.  You can't have two driver structures with the same name.  The names
are sysfs object names.


From linux at arm.linux.org.uk  Thu Mar 15 13:35:08 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 17:35:08 +0000
Subject: [PATCH 5/5] MMC: mmci: Add required documentation for Device
 Tree bindings
In-Reply-To: <1331734803-17954-6-git-send-email-lee.jones@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <1331734803-17954-6-git-send-email-lee.jones@linaro.org>
Message-ID: <20120315173508.GE15988@n2100.arm.linux.org.uk>

On Wed, Mar 14, 2012 at 02:20:03PM +0000, Lee Jones wrote:
> +ux500 variant specific properties:
> +- gpio-en                : contains the level-shifter enable gpio
> +- gpio-vsel              : contains the level-shifter voltage select gpio
> +- tx_dst_dev_type        : contains the tx destination device (DMA) 
> +- rx_src_dev_type        : contains the rx source device (DMA)

So what about the DMA support being proposed elsewhere?

This sounds like we're inventing one DMA solution for one bit of the tree
and another DMA solution for another bit.  This is madness.

Note that ARM boards like Versatile also have DMA support, even though
most of those platforms are diabolically crippled to the point of it being
useless.  I believe it works on a few select boards...


From lee.jones at linaro.org  Thu Mar 15 13:36:04 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 15 Mar 2012 17:36:04 +0000
Subject: [PATCH 2/5] MMC: mmci: Seperate ARM variants from generic code
In-Reply-To: <20120315173256.GD15988@n2100.arm.linux.org.uk>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <1331734803-17954-3-git-send-email-lee.jones@linaro.org>
 <20120315173256.GD15988@n2100.arm.linux.org.uk>
Message-ID: <4F622884.6060807@linaro.org>

On 15/03/12 17:32, Russell King - ARM Linux wrote:
> On Wed, Mar 14, 2012 at 02:20:00PM +0000, Lee Jones wrote:
>> This is a step in the right direction for future Device
>> Tree support. It will allow variant specific attributes
>> to be collected from a Device Tree without overloading
>> the MMCI core. It will also provide additional future
>> variants a cleaner way to add support.
> 
> NAK.  You can't have two driver structures with the same name.  The names
> are sysfs object names.

Well spotted.

I've already changed this in v2. :)

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From linux at arm.linux.org.uk  Thu Mar 15 13:37:14 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 17:37:14 +0000
Subject: [PATCH 2/5] MMC: mmci: Seperate ARM variants from generic code
In-Reply-To: <4F622884.6060807@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <1331734803-17954-3-git-send-email-lee.jones@linaro.org>
 <20120315173256.GD15988@n2100.arm.linux.org.uk> <4F622884.6060807@linaro.org>
Message-ID: <20120315173714.GF15988@n2100.arm.linux.org.uk>

On Thu, Mar 15, 2012 at 05:36:04PM +0000, Lee Jones wrote:
> On 15/03/12 17:32, Russell King - ARM Linux wrote:
> > On Wed, Mar 14, 2012 at 02:20:00PM +0000, Lee Jones wrote:
> >> This is a step in the right direction for future Device
> >> Tree support. It will allow variant specific attributes
> >> to be collected from a Device Tree without overloading
> >> the MMCI core. It will also provide additional future
> >> variants a cleaner way to add support.
> > 
> > NAK.  You can't have two driver structures with the same name.  The names
> > are sysfs object names.
> 
> Well spotted.
> 
> I've already changed this in v2. :)

I'm not in favour of splitting the two variants either btw.


From lee.jones at linaro.org  Thu Mar 15 13:38:12 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Thu, 15 Mar 2012 17:38:12 +0000
Subject: [PATCH 2/5] MMC: mmci: Seperate ARM variants from generic code
In-Reply-To: <4F622884.6060807@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <1331734803-17954-3-git-send-email-lee.jones@linaro.org>
 <20120315173256.GD15988@n2100.arm.linux.org.uk> <4F622884.6060807@linaro.org>
Message-ID: <4F622904.4000705@linaro.org>

On 15/03/12 17:36, Lee Jones wrote:
> On 15/03/12 17:32, Russell King - ARM Linux wrote:
>> On Wed, Mar 14, 2012 at 02:20:00PM +0000, Lee Jones wrote:
>>> This is a step in the right direction for future Device
>>> Tree support. It will allow variant specific attributes
>>> to be collected from a Device Tree without overloading
>>> the MMCI core. It will also provide additional future
>>> variants a cleaner way to add support.
>>
>> NAK.  You can't have two driver structures with the same name.  The names
>> are sysfs object names.
> 
> Well spotted.
> 
> I've already changed this in v2. :)

In case you were interested, see:

http://git.linaro.org/gitweb?p=people/ljones/linux-3.0-ux500.git;a=shortlog;h=refs/heads/device-tree-snowball-mmci

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From nicolas.pitre at linaro.org  Thu Mar 15 13:40:35 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 15 Mar 2012 13:40:35 -0400 (EDT)
Subject: [PATCH 1/4] ARM: opcodes: Don't define the thumb32 byteswapping
 macros for BE32
In-Reply-To: <1331829132-9762-2-git-send-email-dave.martin@linaro.org>
References: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
 <1331829132-9762-2-git-send-email-dave.martin@linaro.org>
Message-ID: <alpine.LFD.2.02.1203151337150.24151@xanadu.home>

On Thu, 15 Mar 2012, Dave Martin wrote:

> The existing __mem_to_opcode_thumb32() is incorrect for BE32
> platforms.  However, these don't support Thumb-2 kernels, so this
> option is not so relevant for those platforms anyway.
> 
> This operation is complicated by the lack of unaligned memory
> access support prior to ARMv6.
> 
> Rather than provide a "working" macro which will probably won't get
> used (or worse, will get misused), this patch removes the macro for
> BE32 kernels.  People manipulating Thumb opcodes prior to ARMv6
> should almost certainly be splitting these operations into
> halfwords anyway, using __opcode_thumb32_{first,second,compose}()
> and the 16-bit opcode transformations.
> 
> Signed-off-by: Dave Martin <dave.martin at linaro.org>

Acked-by: Nicolas Pitre <nico at linaro.org>


> +/*
> + * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
> + * work in all cases, due to alignment constraints.  For now, a correct
> + * version is not proivided for BE32.

s/proivided/provided/


Nicolas


From broonie at opensource.wolfsonmicro.com  Thu Mar 15 13:43:44 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 15 Mar 2012 17:43:44 +0000
Subject: [PATCH v3 4/6] mfd: mc13xxx-core: use regmap for register access
In-Reply-To: <1331757790-10583-5-git-send-email-marc@cpdesign.com.au>
References: <1331757790-10583-1-git-send-email-marc@cpdesign.com.au>
 <1331757790-10583-5-git-send-email-marc@cpdesign.com.au>
Message-ID: <20120315174343.GQ3138@opensource.wolfsonmicro.com>

On Thu, Mar 15, 2012 at 07:43:08AM +1100, Marc Reilly wrote:
> This change converts the mc13xxx core to use regmap rather than direct
> spi r/w.
> The spidev member of mc13xxx struct becomes redundant and is removed.
> Extra debugging aids are added to mc13xxx_reg_rmw.
> Mutex init is moved to before regmap init.

Reviwed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

For rmw please push the trace down into regmap as a new tracepoint if
you find it useful; one of the wins from regmap is intended to be the
trace and diagnostic infrastructure you get for free with it.  At the
minute only the underlying reads and writes have trace.
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From arnd at arndb.de  Thu Mar 15 13:46:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 17:46:56 +0000
Subject: [PATCH 2/5] MMC: mmci: Seperate ARM variants from generic code
In-Reply-To: <20120315173714.GF15988@n2100.arm.linux.org.uk>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <4F622884.6060807@linaro.org> <20120315173714.GF15988@n2100.arm.linux.org.uk>
Message-ID: <201203151746.56678.arnd@arndb.de>

On Thursday 15 March 2012, Russell King - ARM Linux wrote:
> On Thu, Mar 15, 2012 at 05:36:04PM +0000, Lee Jones wrote:
> > On 15/03/12 17:32, Russell King - ARM Linux wrote:
> > > On Wed, Mar 14, 2012 at 02:20:00PM +0000, Lee Jones wrote:
> > >> This is a step in the right direction for future Device
> > >> Tree support. It will allow variant specific attributes
> > >> to be collected from a Device Tree without overloading
> > >> the MMCI core. It will also provide additional future
> > >> variants a cleaner way to add support.
> > > 
> > > NAK.  You can't have two driver structures with the same name.  The names
> > > are sysfs object names.
> > 
> > Well spotted.
> > 
> > I've already changed this in v2. :)
> 
> I'm not in favour of splitting the two variants either btw.

Can you elaborate? I suggested the split in order to keep the ux500
specific parts local to one file. With the device tree conversion,
we really want to have them out of the platform code, but sticking them
into the main driver seems wrong, too.

I don't mind leaving the ARM and u300 specific bits in the main driver,
but I think having the ux500 parts separate does indeed help.

	Arnd


From linus.walleij at linaro.org  Thu Mar 15 13:47:24 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 15 Mar 2012 18:47:24 +0100
Subject: [PATCH 07/10] ARM: ux500: Provide local timer support for Device
 Tree
In-Reply-To: <1331730306-11461-8-git-send-email-lee.jones@linaro.org>
References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org>
 <1331730306-11461-8-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdYVZhFjMyj8Xo-RK8h4d=kKZ0g6Owbur2GKFanT3hda9A@mail.gmail.com>

On Wed, Mar 14, 2012 at 2:05 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This enables local timer (AKA: private timer) support for
> all u8500 based hardware using DT.
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

Yours,
Linus Walleij


From arnd at arndb.de  Thu Mar 15 13:49:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 17:49:07 +0000
Subject: [PATCH 5/5] MMC: mmci: Add required documentation for Device Tree
 bindings
In-Reply-To: <20120315173508.GE15988@n2100.arm.linux.org.uk>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <1331734803-17954-6-git-send-email-lee.jones@linaro.org>
 <20120315173508.GE15988@n2100.arm.linux.org.uk>
Message-ID: <201203151749.07673.arnd@arndb.de>

On Thursday 15 March 2012, Russell King - ARM Linux wrote:
> 
> On Wed, Mar 14, 2012 at 02:20:03PM +0000, Lee Jones wrote:
> > +ux500 variant specific properties:
> > +- gpio-en                : contains the level-shifter enable gpio
> > +- gpio-vsel              : contains the level-shifter voltage select gpio
> > +- tx_dst_dev_type        : contains the tx destination device (DMA) 
> > +- rx_src_dev_type        : contains the rx source device (DMA)
> 
> So what about the DMA support being proposed elsewhere?
> 
> This sounds like we're inventing one DMA solution for one bit of the tree
> and another DMA solution for another bit.  This is madness.

Agreed. I originally made a similar comment for an early version but had not
noticed that it made it into this one. This should be using the proper DMA
bindings, or just auxdata while we're not entirely there yet.

	Arnd


From tony at atomide.com  Thu Mar 15 13:51:22 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 15 Mar 2012 10:51:22 -0700
Subject: [PATCH 1/2] ARM: OMAP: powerdomain: Wait for powerdomain
 transition in pwrdm_state_switch()
In-Reply-To: <alpine.DEB.2.00.1203151129160.26218@utopia.booyaka.com>
References: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
 <1331562873-29535-2-git-send-email-santosh.shilimkar@ti.com>
 <alpine.DEB.2.00.1203151129160.26218@utopia.booyaka.com>
Message-ID: <20120315175122.GB7276@atomide.com>

* Paul Walmsley <paul at pwsan.com> [120315 10:35]:
> On Mon, 12 Mar 2012, Santosh Shilimkar wrote:
> 
> > Commit b1cbdb00d{OMAP: clockdomain: Wait for powerdomain to be ON
> > when using clockdomain force wakeup} was assuming that pwrdm_state_switch()
> > does wait for the powerdomain transition which is not the case.
> > 
> > Fix this API by adding the pwrdm_wait_transition().
> > 
> > Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> > CC: Rajendra Nayak <rnayak at ti.com>
> > CC: Paul Walmsley <paul at pwsan.com>
> 
> Acked-by: Paul Walmsley <paul at pwsan.com>
> 
> Sounds like this fixes a major kernel oops bug for Tony so this should go 
> in ASAP to v3.3-rc series.

Got a random oops with this one applied still, just happened
to take longer this time :(

Regards,

Tony


From jason at lakedaemon.net  Thu Mar 15 13:22:13 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Thu, 15 Mar 2012 13:22:13 -0400
Subject: linux-next: build failure after merge of the final tree
 (arm-soc tree related)
In-Reply-To: <201203151639.38223.arnd@arndb.de>
References: <20120315105901.7b10c9f4de9374a613436988@canb.auug.org.au>
 <20120315002020.GA16189@titan.lakedaemon.net>
 <201203151639.38223.arnd@arndb.de>
Message-ID: <20120315172213.GC20243@titan.lakedaemon.net>

On Thu, Mar 15, 2012 at 04:39:38PM +0000, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Jason Cooper wrote:
> > That's my mistake.  I did a pull request for the wrong branch.  Olof,
> > could you please drop the offending branch and I'll submit a new pull
> > request once I have a chance to test Arnd's irq patch?
> 
> I reverted this in the for-next branch for now. The two initial patches
> from the kirkwood/board branch are still present.

Okay, thanks.  I've rebased onto next/boards and merged the
depends/irqdomain branch.  I'm making progress, but not finished yet.

How is a pull-request done in the above scenario?  is my merge commit
included in the series?  what is the pull-request based on?
next/boards, or depends/irqdomain?

thx,

Jason.


From nicolas.pitre at linaro.org  Thu Mar 15 13:53:20 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 15 Mar 2012 13:53:20 -0400 (EDT)
Subject: [PATCH 2/4] ARM: opcodes: Make opcode byteswapping macros
 assembly-compatible
In-Reply-To: <1331829132-9762-3-git-send-email-dave.martin@linaro.org>
References: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
 <1331829132-9762-3-git-send-email-dave.martin@linaro.org>
Message-ID: <alpine.LFD.2.02.1203151351180.24151@xanadu.home>

On Thu, 15 Mar 2012, Dave Martin wrote:

> Most of the existing macros don't work with assembler, due to the
> use of type casts and C functions from <linux/swab.h>.
> 
> This patch abstracts out those operations and provides simple
> explicit versions for use in assembly code.
> 
> __opcode_is_thumb32() and __opcode_is_thumb16() are also converted
> to do bitmask-based testing to avoid confusion if these are used in
> assembly code (the assembler typically treats all arithmetic values
> as signed).
> 
> Signed-off-by: Dave Martin <dave.martin at linaro.org>

OK.  One really has to read through the whole series to see the point of 
this.

Acked-by: Nicolas Pitre <nico at linaro.org>



> ---
>  arch/arm/include/asm/opcodes.h |   97 +++++++++++++++++++++++++++++++++------
>  1 files changed, 82 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
> index cf877c8..32730a8 100644
> --- a/arch/arm/include/asm/opcodes.h
> +++ b/arch/arm/include/asm/opcodes.h
> @@ -19,6 +19,33 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
>  
>  
>  /*
> + * Assembler opcode byteswap helpers.
> + * These are only intended for use by this header: don't use them directly,
> + * because they will be suboptimal in most cases.
> + */
> +#define ___asm_opcode_swab32(x) (	\
> +	  (((x) << 24) & 0xFF000000)	\
> +	| (((x) <<  8) & 0x00FF0000)	\
> +	| (((x) >>  8) & 0x0000FF00)	\
> +	| (((x) >> 24) & 0x000000FF)	\
> +)
> +#define ___asm_opcode_swab16(x) (	\
> +	  (((x) << 8) & 0xFF00)		\
> +	| (((x) >> 8) & 0x00FF)		\
> +)
> +#define ___asm_opcode_swahb32(x) (	\
> +	  (((x) << 8) & 0xFF00FF00)	\
> +	| (((x) >> 8) & 0x00FF00FF)	\
> +)
> +#define ___asm_opcode_swahw32(x) (	\
> +	  (((x) << 16) & 0xFFFF0000)	\
> +	| (((x) >> 16) & 0x0000FFFF)	\
> +)
> +#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
> +#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
> +
> +
> +/*
>   * Opcode byteswap helpers
>   *
>   * These macros help with converting instructions between a canonical integer
> @@ -41,30 +68,58 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
>   * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
>   * represent any valid Thumb-2 instruction.  For this range,
>   * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
> + *
> + * The ___asm variants are intended only for use by this header, in situations
> + * involving inline assembler.  For .S files, the normal __opcode_*() macros
> + * should do the right thing.
>   */
> +#ifdef __ASSEMBLY__
>  
> -#ifndef __ASSEMBLY__
> +#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
> +#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
> +#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
> +#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
> +#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
> +#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
> +
> +#else /* ! __ASSEMBLY__ */
>  
>  #include <linux/types.h>
>  #include <linux/swab.h>
>  
> +#define ___opcode_swab32(x) swab32(x)
> +#define ___opcode_swab16(x) swab16(x)
> +#define ___opcode_swahb32(x) swahb32(x)
> +#define ___opcode_swahw32(x) swahw32(x)
> +#define ___opcode_identity32(x) ((u32)(x))
> +#define ___opcode_identity16(x) ((u16)(x))
> +
> +#endif /* ! __ASSEMBLY__ */
> +
> +
>  #ifdef CONFIG_CPU_ENDIAN_BE8
>  
> -#define __opcode_to_mem_arm(x) swab32(x)
> -#define __opcode_to_mem_thumb16(x) swab16(x)
> -#define __opcode_to_mem_thumb32(x) swahb32(x)
> +#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
> +#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
> +#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
> +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
> +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
> +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
>  
>  #else /* ! CONFIG_CPU_ENDIAN_BE8 */
>  
> -#define __opcode_to_mem_arm(x) ((u32)(x))
> -#define __opcode_to_mem_thumb16(x) ((u16)(x))
> +#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
> +#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
> +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
> +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
>  #ifndef CONFIG_CPU_ENDIAN_BE32
>  /*
>   * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
>   * work in all cases, due to alignment constraints.  For now, a correct
>   * version is not proivided for BE32.
>   */
> -#define __opcode_to_mem_thumb32(x) swahw32(x)
> +#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
> +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
>  #endif
>  
>  #endif /* ! CONFIG_CPU_ENDIAN_BE8 */
> @@ -78,15 +133,27 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
>  /* Operations specific to Thumb opcodes */
>  
>  /* Instruction size checks: */
> -#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL)
> -#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL)
> +#define __opcode_is_thumb32(x) (		\
> +	   ((x) & 0xF8000000) == 0xE8000000	\
> +	|| ((x) & 0xF0000000) == 0xF0000000	\
> +)
> +#define __opcode_is_thumb16(x) (					\
> +	   ((x) & 0xFFFF0000) == 0					\
> +	&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)	\
> +)
>  
>  /* Operations to construct or split 32-bit Thumb instructions: */
> -#define __opcode_thumb32_first(x) ((u16)((x) >> 16))
> -#define __opcode_thumb32_second(x) ((u16)(x))
> -#define __opcode_thumb32_compose(first, second) \
> -	(((u32)(u16)(first) << 16) | (u32)(u16)(second))
> -
> -#endif /* __ASSEMBLY__ */
> +#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
> +#define __opcode_thumb32_second(x) (___opcode_identity16(x))
> +#define __opcode_thumb32_compose(first, second) (			\
> +	  (___opcode_identity32(___opcode_identity16(first)) << 16)	\
> +	| ___opcode_identity32(___opcode_identity16(second))		\
> +)
> +#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
> +#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
> +#define ___asm_opcode_thumb32_compose(first, second) (			    \
> +	  (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
> +	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
> +)
>  
>  #endif /* __ASM_ARM_OPCODES_H */
> -- 
> 1.7.4.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


From arnd at arndb.de  Thu Mar 15 13:53:25 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 17:53:25 +0000
Subject: [PATCH 5/5] MMC: mmci: Add required documentation for Device Tree
 bindings
In-Reply-To: <1331734803-17954-6-git-send-email-lee.jones@linaro.org>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <1331734803-17954-6-git-send-email-lee.jones@linaro.org>
Message-ID: <201203151753.25774.arnd@arndb.de>

On Wednesday 14 March 2012, Lee Jones wrote:

Some more comments about the individual properties

> +Required properties:
> +- compatible             : contains "arm,pl18x", "arm,primecell".

Better use the exact number for 'x' here.

> +- reg                    : contains pl18x registers and length.
> +- interrupts             : contains the device IRQ(s).

You should document what the first and second interrupts are,
respectively, if there is more than one.

> +- arm,primecell-periphid : contains the PrimeCell Peripheral ID.

This one should be optional.

> +
> +Optional properties:
> +- ocr_mask               : contains the regulator oscillator mask

Not sure about this one. If it's for the regulators, we should be
using the regulator bindings.

> +- wp-gpios               : contains any write protect (ro) gpios
> +- cd-gpios               : contains any card detection gpios
> +- cd-invert              : indicates whether the cd gpio is inverted 
> +- clock_frequency        : contains the maximum operating frequency

The name should be 'clock-frequency', not 'clock_frequency'.

> +- mmc_cap_4_bit_data     : indicates whether device is 4 bit capable
> +- mmc_cap_8_bit_data     : indicates whether device is 8 bit capable
> +- mmc_cap_mmc_highspeed  : indicates whether MMC is high speed capable
> +- mmc_cap_sd_highspeed   : indicates whether SD is high speed capable

I would strongly recommend using the same naming as sdhci here. I think
tegra has set a precedent.

> +ux500 variant specific properties:
> +- gpio-en                : contains the level-shifter enable gpio
> +- gpio-vsel              : contains the level-shifter voltage select gpio

I think these need to be 'en-gpios' and 'vsel-gpios', in order for the
gpio binding to work.

> +- tx_dst_dev_type        : contains the tx destination device (DMA) 
> +- rx_src_dev_type        : contains the rx source device (DMA)

As Russell commented already, these should not be here.

	Arnd


From nicolas.pitre at linaro.org  Thu Mar 15 13:54:22 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 15 Mar 2012 13:54:22 -0400 (EDT)
Subject: [PATCH 3/4] ARM: opcodes: Add helpers for emitting custom opcodes
In-Reply-To: <1331829132-9762-4-git-send-email-dave.martin@linaro.org>
References: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
 <1331829132-9762-4-git-send-email-dave.martin@linaro.org>
Message-ID: <alpine.LFD.2.02.1203151354040.24151@xanadu.home>

On Thu, 15 Mar 2012, Dave Martin wrote:

> This patch adds some __inst_() macros for injecting custom opcodes
> in assembler (both inline and in .S files).  They should make it
> easier and cleaner to get things right in little-/big-
> endian/ARM/Thumb-2 kernels without a lot of #ifdefs.
> 
> Signed-off-by: Dave Martin <dave.martin at linaro.org>

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
>  arch/arm/include/asm/opcodes.h |   69 ++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 69 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
> index 32730a8..50ef0be 100644
> --- a/arch/arm/include/asm/opcodes.h
> +++ b/arch/arm/include/asm/opcodes.h
> @@ -156,4 +156,73 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
>  	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
>  )
>  
> +/*
> + * Opcode injection helpers
> + *
> + * In rare cases it is necessary to assemble an opcode which the
> + * assembler does not support directly, or which would normally be
> + * rejected because of the CFLAGS or AFLAGS used to build the affected
> + * file.
> + *
> + * Before using these macros, consider carefully whether it is feasible
> + * instead to change the build flags for your file, or whether it really
> + * makes sense to support old assembler versions when building that
> + * particular kernel feature.
> + *
> + * The macros defined here should only be used where there is no viable
> + * alternative.
> + *
> + *
> + * __inst_arm(x): emit the specified ARM opcode
> + * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
> + * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
> + *
> + * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
> + *	16-bit Thumb opcode, depending on whether an ARM or Thumb-2
> + *	kernel is being built
> + *
> + * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
> + *	32-bit Thumb opcode, depending on whether an ARM or Thumb-2
> + *	kernel is being built
> + *
> + *
> + * Note that using these macros directly is poor practice.  Instead, you
> + * should use them to define human-readable wrapper macros to encode the
> + * instructions that you care about.  In code which might run on ARMv7 or
> + * above, you can usually use the __inst_arm_thumb{16,32} macros to
> + * specify the ARM and Thumb alternatives at the same time.  This ensures
> + * that the correct opcode gets emitted depending on the instruction set
> + * used for the kernel build.
> + */
> +#include <linux/stringify.h>
> +
> +#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
> +#define __inst_thumb32(x) ___inst_thumb32(				\
> +	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),	\
> +	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))	\
> +)
> +#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
> +
> +#ifdef CONFIG_THUMB2_KERNEL
> +#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
> +	__inst_thumb16(thumb_opcode)
> +#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
> +	__inst_thumb32(thumb_opcode)
> +#else
> +#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
> +#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
> +#endif
> +
> +/* Helpers for the helpers.  Don't use these directly. */
> +#ifdef __ASSEMBLY__
> +#define ___inst_arm(x) .long x
> +#define ___inst_thumb16(x) .short x
> +#define ___inst_thumb32(first, second) .short first, second
> +#else
> +#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
> +#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
> +#define ___inst_thumb32(first, second) \
> +	".short " __stringify(first) ", " __stringify(second) "\n\t"
> +#endif
> +
>  #endif /* __ASM_ARM_OPCODES_H */
> -- 
> 1.7.4.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


From linux at arm.linux.org.uk  Thu Mar 15 13:54:43 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 17:54:43 +0000
Subject: [PATCH 2/5] MMC: mmci: Seperate ARM variants from generic code
In-Reply-To: <201203151746.56678.arnd@arndb.de>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <4F622884.6060807@linaro.org> <20120315173714.GF15988@n2100.arm.linux.org.uk>
 <201203151746.56678.arnd@arndb.de>
Message-ID: <20120315175443.GG15988@n2100.arm.linux.org.uk>

On Thu, Mar 15, 2012 at 05:46:56PM +0000, Arnd Bergmann wrote:
> Can you elaborate? I suggested the split in order to keep the ux500
> specific parts local to one file. With the device tree conversion,
> we really want to have them out of the platform code, but sticking them
> into the main driver seems wrong, too.

You're talking about the data structures which describe what quirks to
apply for the ux500 parts, rather than the actual quirks themselves.
That's not a particularly clever thing to do because it separates out
the selection of the works from the rest of the driver, which means
simply searching for the flags to find out what's applied for what has
to span several files.


From kumarrav at codeaurora.org  Thu Mar 15 13:57:51 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Thu, 15 Mar 2012 23:27:51 +0530
Subject: [PATCH v3 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 DMA APIs
In-Reply-To: <CAPDArRLs23VDJSWpX8xJsXfn+_SV2FcyzLYBF9UAxf=Rv9svGQ@mail.gmail.com>
References: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>
 <20120312201421.GA3459@fifo99.com>
 <CAPDArRLs23VDJSWpX8xJsXfn+_SV2FcyzLYBF9UAxf=Rv9svGQ@mail.gmail.com>
Message-ID: <4F622D9F.1070101@codeaurora.org>

On 3/13/2012 4:27 PM, Shantanu Gupta wrote:
> Any info available(publicly) on so as to what all chipsets have this
> capability ?

This is DMA engine driver for "Application Data Mover(ADM)" which in one 
type of DMA device in most of the Qualcomm processors like snapdragon.

>
> On Tue, Mar 13, 2012 at 1:44 AM, Daniel Walker <dwalker at fifo99.com
> <mailto:dwalker at fifo99.com>> wrote:
>
>     On Mon, Mar 12, 2012 at 04:02:44PM +0530, Ravi Kumar V wrote:
>      > Add DMAEngine based driver using the old MSM DMA APIs internally.s
>
>     What do you mean by this?
>
>      > The benefit of this approach is that not all the drivers
>      > have to get converted to DMAEngine APIs simultaneosly while
>      > both the drivers can stay enabled in the kernel. The client
>      > drivers using the old MSM APIs directly can now convert to
>      > DMAEngine one by one.
>
>     Which drivers?
>
>     Daniel
>     --
>     To unsubscribe from this list: send the line "unsubscribe
>     linux-arm-msm" in
>     the body of a message to majordomo at vger.kernel.org
>     <mailto:majordomo at vger.kernel.org>
>     More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>


-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From linux at arm.linux.org.uk  Thu Mar 15 13:58:16 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 17:58:16 +0000
Subject: [PATCH 5/5] MMC: mmci: Add required documentation for Device
 Tree bindings
In-Reply-To: <201203151749.07673.arnd@arndb.de>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <1331734803-17954-6-git-send-email-lee.jones@linaro.org>
 <20120315173508.GE15988@n2100.arm.linux.org.uk>
 <201203151749.07673.arnd@arndb.de>
Message-ID: <20120315175816.GH15988@n2100.arm.linux.org.uk>

On Thu, Mar 15, 2012 at 05:49:07PM +0000, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Russell King - ARM Linux wrote:
> > 
> > On Wed, Mar 14, 2012 at 02:20:03PM +0000, Lee Jones wrote:
> > > +ux500 variant specific properties:
> > > +- gpio-en                : contains the level-shifter enable gpio
> > > +- gpio-vsel              : contains the level-shifter voltage select gpio
> > > +- tx_dst_dev_type        : contains the tx destination device (DMA) 
> > > +- rx_src_dev_type        : contains the rx source device (DMA)
> > 
> > So what about the DMA support being proposed elsewhere?
> > 
> > This sounds like we're inventing one DMA solution for one bit of the tree
> > and another DMA solution for another bit.  This is madness.
> 
> Agreed. I originally made a similar comment for an early version but had not
> noticed that it made it into this one. This should be using the proper DMA
> bindings, or just auxdata while we're not entirely there yet.

It's something that I'm also concerned with the main OF DMA patches.  It's
not at all clear what we want from DMA bindings yet because we've hardly
started converting from platform specific DMA APIs to the DMA engine based
APIs.

The way DMA channels are selected by DMA APIs is significantly different
from the DMA engine based API, and I remain worried that we're locking in
to a platform specific DMA API method.

I think the DMA parts should be left alone until there has been much more
of an effort to convert to DMA engine based APIs for the various platforms.

Note: OMAP DMA is something I've been asked to take over, and is something
I've been looking at over the last couple of weeks so far.


From nicolas.pitre at linaro.org  Thu Mar 15 13:58:28 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Thu, 15 Mar 2012 13:58:28 -0400 (EDT)
Subject: [PATCH 4/4] ARM: opcodes: Opcode definitions for the
 Virtualization Extensions
In-Reply-To: <1331829132-9762-5-git-send-email-dave.martin@linaro.org>
References: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
 <1331829132-9762-5-git-send-email-dave.martin@linaro.org>
Message-ID: <alpine.LFD.2.02.1203151355570.24151@xanadu.home>

On Thu, 15 Mar 2012, Dave Martin wrote:

> For now, this patch just adds a definition for the HVC instruction.
> More can be added here later, as needed.
> 
> Now that we have a real example of how to use the opcode injection
> macros properly, this patch also adds a cross-reference from the
> explanation in opcodes.h (since without an example, figuring out
> how to use the macros is not that easy).
> 
> Signed-off-by: Dave Martin <dave.martin at linaro.org>

Acked-by: Nicolas Pitre <nico at linaro.org>

Maybe this would be a good idea to document in one of the patch logs why 
you didn't go with the assembler macro route like it is done in 
unified.h for the various it instructions.

> ---
>  arch/arm/include/asm/opcodes-virt.h |   29 +++++++++++++++++++++++++++++
>  arch/arm/include/asm/opcodes.h      |    2 ++
>  2 files changed, 31 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/include/asm/opcodes-virt.h
> 
> diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
> new file mode 100644
> index 0000000..b85665a
> --- /dev/null
> +++ b/arch/arm/include/asm/opcodes-virt.h
> @@ -0,0 +1,29 @@
> +/*
> + * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
> + * Copyright (C) 2012  Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + */
> +#ifndef __ASM_ARM_OPCODES_VIRT_H
> +#define __ASM_ARM_OPCODES_VIRT_H
> +
> +#include <asm/opcodes.h>
> +
> +#define __HVC(imm16) __inst_arm_thumb32(				\
> +	0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),	\
> +	0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)	\
> +)
> +
> +#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
> diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
> index 50ef0be..89ff5b9 100644
> --- a/arch/arm/include/asm/opcodes.h
> +++ b/arch/arm/include/asm/opcodes.h
> @@ -193,6 +193,8 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
>   * specify the ARM and Thumb alternatives at the same time.  This ensures
>   * that the correct opcode gets emitted depending on the instruction set
>   * used for the kernel build.
> + *
> + * Look at opcodes-virt.h for an example of how to use these macros.
>   */
>  #include <linux/stringify.h>
>  
> -- 
> 1.7.4.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


From linux at arm.linux.org.uk  Thu Mar 15 13:59:19 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 17:59:19 +0000
Subject: [PATCH 5/5] MMC: mmci: Add required documentation for Device
 Tree bindings
In-Reply-To: <201203151753.25774.arnd@arndb.de>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <1331734803-17954-6-git-send-email-lee.jones@linaro.org>
 <201203151753.25774.arnd@arndb.de>
Message-ID: <20120315175919.GI15988@n2100.arm.linux.org.uk>

On Thu, Mar 15, 2012 at 05:53:25PM +0000, Arnd Bergmann wrote:
> On Wednesday 14 March 2012, Lee Jones wrote:
> > +
> > +Optional properties:
> > +- ocr_mask               : contains the regulator oscillator mask
> 
> Not sure about this one. If it's for the regulators, we should be
> using the regulator bindings.

It's also nothing to do with oscillators.


From nsekhar at ti.com  Thu Mar 15 14:01:48 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Thu, 15 Mar 2012 18:01:48 +0000
Subject: [GIT PULL] DaVinci fixes for v3.3
In-Reply-To: <201203151552.09922.arnd@arndb.de>
References: <DF0F476B391FA8409C78302C7BA518B6317F5E48@DBDE01.ent.ti.com>
 <201203151552.09922.arnd@arndb.de>
Message-ID: <DF0F476B391FA8409C78302C7BA518B6317F9B4C@DBDE01.ent.ti.com>

Hi Arnd,

On Thu, Mar 15, 2012 at 21:22:09, Arnd Bergmann wrote:
> On Wednesday 14 March 2012, Nori, Sekhar wrote:
> > Hi Arnd, Olof,
> > 
> > Can you please pull the following DaVinci fixes for v3.3.
> > They fix a build and section mismatch warning.
> > 
> > Thanks,
> > Sekhar
> > 
> > The following changes since commit fde7d9049e55ab85a390be7f415d74c9f62dd0f9:
> >   Linus Torvalds (1):
> >         Linux 3.3-rc7
> > 
> > are available in the git repository at:
> > 
> >   git://gitorious.org/linux-davinci/linux-davinci.git fixes
> > 
> > Uwe Kleine-K??????nig (2):
> >       ARM: davinci: cpufreq: fix compiler warning
> >       ARM: davinci: DA850: move da850_register_pm to .init.text
> > 
> >  arch/arm/mach-davinci/cpufreq.c |    2 +-
> >  arch/arm/mach-davinci/da850.c   |    2 +-
> >  2 files changed, 2 insertions(+), 2 deletions(-
> > 
> 
> Hi Sekhar,
> 
> I've applied these two to the next/fixes-non-critical branch for v3.4,
> not the fixes branch for v3.3 because they both look like they have
> no impact on production systems other than the build warnings.
> 
> If I missed something and one or both patches are indeed required for 3.3,
> please let me know.

That's right, they will not have impact on production systems and are
not v3.3 regressions either. Queuing for v3.4 is the right choice.

Thanks,
Sekhar


From nsekhar at ti.com  Thu Mar 15 14:06:20 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Thu, 15 Mar 2012 18:06:20 +0000
Subject: [GIT PULL v2] DaVinci DM644x video display support
In-Reply-To: <DF0F476B391FA8409C78302C7BA518B6317F13DB@DBDE01.ent.ti.com>
References: <DF0F476B391FA8409C78302C7BA518B6317F13DB@DBDE01.ent.ti.com>
Message-ID: <DF0F476B391FA8409C78302C7BA518B6317F9BA1@DBDE01.ent.ti.com>

Hi Arnd, Olof,

On Sun, Mar 11, 2012 at 13:06:55, Nori, Sekhar wrote:
> Hi Arnd, Olof,
> 
> Can you please pull these two patches adding support
> for DaVinci DM644x V4L2 display support for v3.4.
> 
> These patches heavily depend on the clean-up series sent
> earlier. I have re-generated the pull request against
> v3.4/cleanup branch of my tree (already pulled earlier
> and unchanged since) as suggested by Olof.
> 
> Let me know if this works for you.

If there is no further feedback, can you please pull
these patches?

Thanks,
Sekhar


From don.morris at hp.com  Thu Mar 15 14:07:30 2012
From: don.morris at hp.com (Don Morris)
Date: Thu, 15 Mar 2012 11:07:30 -0700
Subject: [PATCH V2] iop-adma: Corrected array overflow in RAID6 Xscale(R) test.
Message-ID: <1331834850-27409-1-git-send-email-don.morris@hp.com>

Bug: cppcheck reported overflow in array assignment (for loop walks
0 to IOP_ADMA_NUM_SRC_TEST+2, array size is IOP_ADMA_NUM_SRC_TEST).

Reported as: https://bugzilla.kernel.org/show_bug.cgi?id=42677

Test code pq_src array was grown by two elements to correspond with actual
usage (IOP_ADMA_NUM_SRC_TEST+2), stack consumption was kept constant by
modifying the pq_dest two element array which is only used when pq_src
is referenced up to IOP_ADMA_NUM_SRC_TEST elements into the address
of the new last two elements of the pq_src array. This is presumed to
be the original intent but would be reliant on compilers always having
pq_dest contiguous with the final element of pq_src.

Note: This is a re-send of a request for review from two weeks ago.
Looking for review (or shootdown), adding LKML to list for a wider
audience. Thanks.

Updated per review comments of Sergei Shtylyov <sshtylyov at mvista.com>

Signed-off-by: Don Morris <don.morris at hp.com>
---
 drivers/dma/iop-adma.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c
index 04be90b..9b1951d 100644
--- a/drivers/dma/iop-adma.c
+++ b/drivers/dma/iop-adma.c
@@ -1271,8 +1271,8 @@ iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device)
 	struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2];
 	/* address conversion buffers (dma_map / page_address) */
 	void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2];
-	dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST];
-	dma_addr_t pq_dest[2];
+	dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST+2];
+	dma_addr_t *pq_dest = &pq_src[IOP_ADMA_NUM_SRC_TEST];
 
 	int i;
 	struct dma_async_tx_descriptor *tx;
-- 
1.7.9.111.gf3fb0



From kumarrav at codeaurora.org  Thu Mar 15 14:12:23 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Thu, 15 Mar 2012 23:42:23 +0530
Subject: [PATCH v3 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 DMA APIs
In-Reply-To: <20120314201929.GA17259@codeaurora.org>
References: <1331548364-27845-1-git-send-email-kumarrav@codeaurora.org>
 <20120312201421.GA3459@fifo99.com> <4F5F41AF.1090907@codeaurora.org>
 <20120314150533.GA8757@fifo99.com> <20120314201929.GA17259@codeaurora.org>
Message-ID: <4F623107.2040108@codeaurora.org>

On 3/15/2012 1:49 AM, David Brown wrote:
> On Wed, Mar 14, 2012 at 08:05:53AM -0700, Daniel Walker wrote:
>> On Tue, Mar 13, 2012 at 06:16:39PM +0530, Ravi Kumar V wrote:
>>> On 3/13/2012 1:44 AM, Daniel Walker wrote:
>>>> On Mon, Mar 12, 2012 at 04:02:44PM +0530, Ravi Kumar V wrote:
>>>>> Add DMAEngine based driver using the old MSM DMA APIs internally.
>>>>
>>>> What do you mean by this?
>>>>
>>> There is a MSM DMA driver in arch/arm/mach-msm/ which is not in
>>> dmaengine framework standards, but that driver is been used by
>>> client drivers nand, eMMC and serial drivers. Now if we implement
>>> the whole dma driver using dmaengine framework then nand, eMMC like
>>> drivers will be failed as they are using old dma driver API's, so
>>> instead of implementing new driver from scratch we are keeping the
>>> old dma API's as it is and using those API's in new dmaengine
>>> framework.So that we can convert clients drivers to use dma engine
>>> framework.
>>
>> Did you investigate converting the drivers (nand, eMMC, serialied ) ? It
>> seems like there would be a 1:1 mapping between the API's , so it might
>> only be a find->replace operation.
>
> Only at a very superficial level--they both do DMA.  The ADM driver
> wants its scatterlists constructed manually by the caller (in DMA-able
> memory) and just the pointer handed over.  The drivers will have to be
> converted to use the abstracted scatterlists that dmaengine wants.
> Drivers like msm_sdcc are currently fairly intimitely tied to flow
> that is specific to ADM.  The msm_sdcc driver also needs use of the
> ADM's "box" mode, which has to be made to work with DMAEngine as well.
>
> Providing both APIs is really the only practical way to get this in
> without having to rewrite several other drivers.
>
> The nand driver (which doesn't seem to have made it in yet,
> https://lkml.org/lkml/2011/2/28/570) is much worse.  About half of the
> code is constructing ADM specific command blocks.  I'm not even sure
> it will be practical to even migrate that driver to DMAEngine, since
> the nand controller hardware is so intimately tied to the functioning
> of the ADM.
>
> David
>

Yes i have tried to convert these drivers, but mostly we need to add 
DMAEngine stuff like requesting channel, creating the descriptors, 
passing these descriptors to channel etc which are different from old 
implementation.So we have choose this path not to disturb the existing 
drivers while converting a driver.

Thanks
Ravi Kumar V
-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From aneesh at ti.com  Thu Mar 15 14:17:30 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu, 15 Mar 2012 23:47:30 +0530
Subject: [PATCH v2 0/7] Add TI EMIF SDRAM controller driver
Message-ID: <1331835457-5390-1-git-send-email-aneesh@ti.com>

Add a driver for the EMIF SDRAM controller used in TI SoCs

EMIF is an SDRAM controller that supports, based on its revision,
one or more of LPDDR2/DDR2/DDR3 protocols.This driver adds support
for LPDDR2.

The driver supports the following features:
- Calculates the DDR AC timing parameters to be set in EMIF
  registers using data from the device data-sheets and based
  on the DDR frequency. If data from data-sheets is not available
  default timing values from the JEDEC spec are used. These
  will be safe, but not necessarily optimal
- API for changing timings during DVFS or at boot-up
- Temperature alert configuration and handling of temperature
  alerts, if any for LPDDR2 devices
  * temperature alert is based on periodic polling of MR4 mode
    register in DDR devices automatically performed by hardware
  * timings are de-rated and brought back to nominal when
    temperature raises and falls respectively
- Cache of calculated register values to avoid re-calculating
  them

The driver will need some minor updates when it is eventually
integrated with Dynamic Voltage and Frequency Scaling (DVFS).
This can not be done now as DVFS support is not available in
the mainline yet.

Discussions with Santosh Shilimkar <santosh.shilimkar at ti.com>
were immensely helpful in shaping up the interfaces. Vibhore Vardhan
<vvardhan at gmail.com> did the initial code snippet for thermal
handling.

Testing: 
- The driver is tested on OMAP4430 SDP.
- The driver in a slightly adapted form is also tested on OMAP5.
- Since mainline kernel doesn't have DVFS support yet,
  testing was done using a test module.
- Temperature alert handling was tested with simulated interrupts
  and faked temperature values as testing all cases in real-life
  scenarios is difficult.
- Tested the driver as a module

Cc: Greg KH <greg at kroah.com>

v2:
- Fixed a bug found in the implementation of errata i728
  workaround
- Fixed the value of frequency printed in debugfs
- Dropped the hwmod patch as Paul has already posted a
  a hwmod series [1] that adds hwmod for EMIF
- Converted instances of __init to __init_or_module

[1] http://thread.gmane.org/gmane.linux.ports.arm.omap/72855

Aneesh V (7):
  misc: ddr: add LPDDR2 data from JESD209-2
  misc: emif: add register definitions for EMIF
  misc: emif: add basic infrastructure for EMIF driver
  misc: emif: handle frequency and voltage change events
  misc: emif: add interrupt and temperature handling
  misc: emif: add one-time settings
  misc: emif: add debugfs entries for emif

 Documentation/misc-devices/ti-emif.txt  |   58 ++
 drivers/misc/Kconfig                    |   12 +
 drivers/misc/Makefile                   |    1 +
 drivers/misc/emif.c                     | 1670 +++++++++++++++++++++++++++++++
 drivers/misc/emif.h                     |  589 +++++++++++
 include/linux/platform_data/emif_plat.h |  128 +++
 include/misc/jedec_ddr.h                |  177 ++++
 lib/Kconfig                             |    8 +
 lib/Makefile                            |    3 +
 lib/jedec_ddr_data.c                    |  135 +++
 10 files changed, 2781 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/misc-devices/ti-emif.txt
 create mode 100644 drivers/misc/emif.c
 create mode 100644 drivers/misc/emif.h
 create mode 100644 include/linux/platform_data/emif_plat.h
 create mode 100644 include/misc/jedec_ddr.h
 create mode 100644 lib/jedec_ddr_data.c



From aneesh at ti.com  Thu Mar 15 14:17:32 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu, 15 Mar 2012 23:47:32 +0530
Subject: [PATCH v2 2/7] misc: emif: add register definitions for EMIF
In-Reply-To: <1331835457-5390-1-git-send-email-aneesh@ti.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
Message-ID: <1331835457-5390-3-git-send-email-aneesh@ti.com>

Add register offsets and bit field definitions
for EMIF module in TI SoCs

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v1:
- Improved commit log
- Corrected copyright year
- Changed file name in order to add other defines
  needed by the driver in the same file in subsequent
  patches
---
 drivers/misc/emif.h |  454 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 454 insertions(+), 0 deletions(-)
 create mode 100644 drivers/misc/emif.h

diff --git a/drivers/misc/emif.h b/drivers/misc/emif.h
new file mode 100644
index 0000000..44b97df
--- /dev/null
+++ b/drivers/misc/emif.h
@@ -0,0 +1,454 @@
+/*
+ * Defines for the EMIF driver
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __EMIF_H
+#define __EMIF_H
+
+/* Registers offset */
+#define EMIF_MODULE_ID_AND_REVISION			0x0000
+#define EMIF_STATUS					0x0004
+#define EMIF_SDRAM_CONFIG				0x0008
+#define EMIF_SDRAM_CONFIG_2				0x000c
+#define EMIF_SDRAM_REFRESH_CONTROL			0x0010
+#define EMIF_SDRAM_REFRESH_CTRL_SHDW			0x0014
+#define EMIF_SDRAM_TIMING_1				0x0018
+#define EMIF_SDRAM_TIMING_1_SHDW			0x001c
+#define EMIF_SDRAM_TIMING_2				0x0020
+#define EMIF_SDRAM_TIMING_2_SHDW			0x0024
+#define EMIF_SDRAM_TIMING_3				0x0028
+#define EMIF_SDRAM_TIMING_3_SHDW			0x002c
+#define EMIF_LPDDR2_NVM_TIMING				0x0030
+#define EMIF_LPDDR2_NVM_TIMING_SHDW			0x0034
+#define EMIF_POWER_MANAGEMENT_CONTROL			0x0038
+#define EMIF_POWER_MANAGEMENT_CTRL_SHDW			0x003c
+#define EMIF_LPDDR2_MODE_REG_DATA			0x0040
+#define EMIF_LPDDR2_MODE_REG_CONFIG			0x0050
+#define EMIF_OCP_CONFIG					0x0054
+#define EMIF_OCP_CONFIG_VALUE_1				0x0058
+#define EMIF_OCP_CONFIG_VALUE_2				0x005c
+#define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL		0x0060
+#define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT		0x0064
+#define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT	0x0068
+#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1	0x006c
+#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2	0x0070
+#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3	0x0074
+#define EMIF_PERFORMANCE_COUNTER_1			0x0080
+#define EMIF_PERFORMANCE_COUNTER_2			0x0084
+#define EMIF_PERFORMANCE_COUNTER_CONFIG			0x0088
+#define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT	0x008c
+#define EMIF_PERFORMANCE_COUNTER_TIME			0x0090
+#define EMIF_MISC_REG					0x0094
+#define EMIF_DLL_CALIB_CTRL				0x0098
+#define EMIF_DLL_CALIB_CTRL_SHDW			0x009c
+#define EMIF_END_OF_INTERRUPT				0x00a0
+#define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS		0x00a4
+#define EMIF_LL_OCP_INTERRUPT_RAW_STATUS		0x00a8
+#define EMIF_SYSTEM_OCP_INTERRUPT_STATUS		0x00ac
+#define EMIF_LL_OCP_INTERRUPT_STATUS			0x00b0
+#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET		0x00b4
+#define EMIF_LL_OCP_INTERRUPT_ENABLE_SET		0x00b8
+#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR		0x00bc
+#define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR		0x00c0
+#define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG	0x00c8
+#define EMIF_TEMPERATURE_ALERT_CONFIG			0x00cc
+#define EMIF_OCP_ERROR_LOG				0x00d0
+#define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW		0x00d4
+#define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL		0x00d8
+#define EMIF_READ_WRITE_LEVELING_CONTROL		0x00dc
+#define EMIF_DDR_PHY_CTRL_1				0x00e4
+#define EMIF_DDR_PHY_CTRL_1_SHDW			0x00e8
+#define EMIF_DDR_PHY_CTRL_2				0x00ec
+#define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING	0x0100
+#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104
+#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108
+#define EMIF_READ_WRITE_EXECUTION_THRESHOLD		0x0120
+#define EMIF_COS_CONFIG					0x0124
+#define EMIF_PHY_STATUS_1				0x0140
+#define EMIF_PHY_STATUS_2				0x0144
+#define EMIF_PHY_STATUS_3				0x0148
+#define EMIF_PHY_STATUS_4				0x014c
+#define EMIF_PHY_STATUS_5				0x0150
+#define EMIF_PHY_STATUS_6				0x0154
+#define EMIF_PHY_STATUS_7				0x0158
+#define EMIF_PHY_STATUS_8				0x015c
+#define EMIF_PHY_STATUS_9				0x0160
+#define EMIF_PHY_STATUS_10				0x0164
+#define EMIF_PHY_STATUS_11				0x0168
+#define EMIF_PHY_STATUS_12				0x016c
+#define EMIF_PHY_STATUS_13				0x0170
+#define EMIF_PHY_STATUS_14				0x0174
+#define EMIF_PHY_STATUS_15				0x0178
+#define EMIF_PHY_STATUS_16				0x017c
+#define EMIF_PHY_STATUS_17				0x0180
+#define EMIF_PHY_STATUS_18				0x0184
+#define EMIF_PHY_STATUS_19				0x0188
+#define EMIF_PHY_STATUS_20				0x018c
+#define EMIF_PHY_STATUS_21				0x0190
+#define EMIF_EXT_PHY_CTRL_1				0x0200
+#define EMIF_EXT_PHY_CTRL_1_SHDW			0x0204
+#define EMIF_EXT_PHY_CTRL_2				0x0208
+#define EMIF_EXT_PHY_CTRL_2_SHDW			0x020c
+#define EMIF_EXT_PHY_CTRL_3				0x0210
+#define EMIF_EXT_PHY_CTRL_3_SHDW			0x0214
+#define EMIF_EXT_PHY_CTRL_4				0x0218
+#define EMIF_EXT_PHY_CTRL_4_SHDW			0x021c
+#define EMIF_EXT_PHY_CTRL_5				0x0220
+#define EMIF_EXT_PHY_CTRL_5_SHDW			0x0224
+#define EMIF_EXT_PHY_CTRL_6				0x0228
+#define EMIF_EXT_PHY_CTRL_6_SHDW			0x022c
+#define EMIF_EXT_PHY_CTRL_7				0x0230
+#define EMIF_EXT_PHY_CTRL_7_SHDW			0x0234
+#define EMIF_EXT_PHY_CTRL_8				0x0238
+#define EMIF_EXT_PHY_CTRL_8_SHDW			0x023c
+#define EMIF_EXT_PHY_CTRL_9				0x0240
+#define EMIF_EXT_PHY_CTRL_9_SHDW			0x0244
+#define EMIF_EXT_PHY_CTRL_10				0x0248
+#define EMIF_EXT_PHY_CTRL_10_SHDW			0x024c
+#define EMIF_EXT_PHY_CTRL_11				0x0250
+#define EMIF_EXT_PHY_CTRL_11_SHDW			0x0254
+#define EMIF_EXT_PHY_CTRL_12				0x0258
+#define EMIF_EXT_PHY_CTRL_12_SHDW			0x025c
+#define EMIF_EXT_PHY_CTRL_13				0x0260
+#define EMIF_EXT_PHY_CTRL_13_SHDW			0x0264
+#define EMIF_EXT_PHY_CTRL_14				0x0268
+#define EMIF_EXT_PHY_CTRL_14_SHDW			0x026c
+#define EMIF_EXT_PHY_CTRL_15				0x0270
+#define EMIF_EXT_PHY_CTRL_15_SHDW			0x0274
+#define EMIF_EXT_PHY_CTRL_16				0x0278
+#define EMIF_EXT_PHY_CTRL_16_SHDW			0x027c
+#define EMIF_EXT_PHY_CTRL_17				0x0280
+#define EMIF_EXT_PHY_CTRL_17_SHDW			0x0284
+#define EMIF_EXT_PHY_CTRL_18				0x0288
+#define EMIF_EXT_PHY_CTRL_18_SHDW			0x028c
+#define EMIF_EXT_PHY_CTRL_19				0x0290
+#define EMIF_EXT_PHY_CTRL_19_SHDW			0x0294
+#define EMIF_EXT_PHY_CTRL_20				0x0298
+#define EMIF_EXT_PHY_CTRL_20_SHDW			0x029c
+#define EMIF_EXT_PHY_CTRL_21				0x02a0
+#define EMIF_EXT_PHY_CTRL_21_SHDW			0x02a4
+#define EMIF_EXT_PHY_CTRL_22				0x02a8
+#define EMIF_EXT_PHY_CTRL_22_SHDW			0x02ac
+#define EMIF_EXT_PHY_CTRL_23				0x02b0
+#define EMIF_EXT_PHY_CTRL_23_SHDW			0x02b4
+#define EMIF_EXT_PHY_CTRL_24				0x02b8
+#define EMIF_EXT_PHY_CTRL_24_SHDW			0x02bc
+#define EMIF_EXT_PHY_CTRL_25				0x02c0
+#define EMIF_EXT_PHY_CTRL_25_SHDW			0x02c4
+#define EMIF_EXT_PHY_CTRL_26				0x02c8
+#define EMIF_EXT_PHY_CTRL_26_SHDW			0x02cc
+#define EMIF_EXT_PHY_CTRL_27				0x02d0
+#define EMIF_EXT_PHY_CTRL_27_SHDW			0x02d4
+#define EMIF_EXT_PHY_CTRL_28				0x02d8
+#define EMIF_EXT_PHY_CTRL_28_SHDW			0x02dc
+#define EMIF_EXT_PHY_CTRL_29				0x02e0
+#define EMIF_EXT_PHY_CTRL_29_SHDW			0x02e4
+#define EMIF_EXT_PHY_CTRL_30				0x02e8
+#define EMIF_EXT_PHY_CTRL_30_SHDW			0x02ec
+
+/* Registers shifts and masks */
+
+/* EMIF_MODULE_ID_AND_REVISION */
+#define SCHEME_SHIFT					30
+#define SCHEME_MASK					(0x3 << 30)
+#define MODULE_ID_SHIFT					16
+#define MODULE_ID_MASK					(0xfff << 16)
+#define RTL_VERSION_SHIFT				11
+#define RTL_VERSION_MASK				(0x1f << 11)
+#define MAJOR_REVISION_SHIFT				8
+#define MAJOR_REVISION_MASK				(0x7 << 8)
+#define MINOR_REVISION_SHIFT				0
+#define MINOR_REVISION_MASK				(0x3f << 0)
+
+/* STATUS */
+#define BE_SHIFT					31
+#define BE_MASK						(1 << 31)
+#define DUAL_CLK_MODE_SHIFT				30
+#define DUAL_CLK_MODE_MASK				(1 << 30)
+#define FAST_INIT_SHIFT					29
+#define FAST_INIT_MASK					(1 << 29)
+#define RDLVLGATETO_SHIFT				6
+#define RDLVLGATETO_MASK				(1 << 6)
+#define RDLVLTO_SHIFT					5
+#define RDLVLTO_MASK					(1 << 5)
+#define WRLVLTO_SHIFT					4
+#define WRLVLTO_MASK					(1 << 4)
+#define PHY_DLL_READY_SHIFT				2
+#define PHY_DLL_READY_MASK				(1 << 2)
+
+/* SDRAM_CONFIG */
+#define SDRAM_TYPE_SHIFT				29
+#define SDRAM_TYPE_MASK					(0x7 << 29)
+#define IBANK_POS_SHIFT					27
+#define IBANK_POS_MASK					(0x3 << 27)
+#define DDR_TERM_SHIFT					24
+#define DDR_TERM_MASK					(0x7 << 24)
+#define DDR2_DDQS_SHIFT					23
+#define DDR2_DDQS_MASK					(1 << 23)
+#define DYN_ODT_SHIFT					21
+#define DYN_ODT_MASK					(0x3 << 21)
+#define DDR_DISABLE_DLL_SHIFT				20
+#define DDR_DISABLE_DLL_MASK				(1 << 20)
+#define SDRAM_DRIVE_SHIFT				18
+#define SDRAM_DRIVE_MASK				(0x3 << 18)
+#define CWL_SHIFT					16
+#define CWL_MASK					(0x3 << 16)
+#define NARROW_MODE_SHIFT				14
+#define NARROW_MODE_MASK				(0x3 << 14)
+#define CL_SHIFT					10
+#define CL_MASK						(0xf << 10)
+#define ROWSIZE_SHIFT					7
+#define ROWSIZE_MASK					(0x7 << 7)
+#define IBANK_SHIFT					4
+#define IBANK_MASK					(0x7 << 4)
+#define EBANK_SHIFT					3
+#define EBANK_MASK					(1 << 3)
+#define PAGESIZE_SHIFT					0
+#define PAGESIZE_MASK					(0x7 << 0)
+
+/* SDRAM_CONFIG_2 */
+#define CS1NVMEN_SHIFT					30
+#define CS1NVMEN_MASK					(1 << 30)
+#define EBANK_POS_SHIFT					27
+#define EBANK_POS_MASK					(1 << 27)
+#define RDBNUM_SHIFT					4
+#define RDBNUM_MASK					(0x3 << 4)
+#define RDBSIZE_SHIFT					0
+#define RDBSIZE_MASK					(0x7 << 0)
+
+/* SDRAM_REFRESH_CONTROL */
+#define INITREF_DIS_SHIFT				31
+#define INITREF_DIS_MASK				(1 << 31)
+#define SRT_SHIFT					29
+#define SRT_MASK					(1 << 29)
+#define ASR_SHIFT					28
+#define ASR_MASK					(1 << 28)
+#define PASR_SHIFT					24
+#define PASR_MASK					(0x7 << 24)
+#define REFRESH_RATE_SHIFT				0
+#define REFRESH_RATE_MASK				(0xffff << 0)
+
+/* SDRAM_TIMING_1 */
+#define T_RTW_SHIFT					29
+#define T_RTW_MASK					(0x7 << 29)
+#define T_RP_SHIFT					25
+#define T_RP_MASK					(0xf << 25)
+#define T_RCD_SHIFT					21
+#define T_RCD_MASK					(0xf << 21)
+#define T_WR_SHIFT					17
+#define T_WR_MASK					(0xf << 17)
+#define T_RAS_SHIFT					12
+#define T_RAS_MASK					(0x1f << 12)
+#define T_RC_SHIFT					6
+#define T_RC_MASK					(0x3f << 6)
+#define T_RRD_SHIFT					3
+#define T_RRD_MASK					(0x7 << 3)
+#define T_WTR_SHIFT					0
+#define T_WTR_MASK					(0x7 << 0)
+
+/* SDRAM_TIMING_2 */
+#define T_XP_SHIFT					28
+#define T_XP_MASK					(0x7 << 28)
+#define T_ODT_SHIFT					25
+#define T_ODT_MASK					(0x7 << 25)
+#define T_XSNR_SHIFT					16
+#define T_XSNR_MASK					(0x1ff << 16)
+#define T_XSRD_SHIFT					6
+#define T_XSRD_MASK					(0x3ff << 6)
+#define T_RTP_SHIFT					3
+#define T_RTP_MASK					(0x7 << 3)
+#define T_CKE_SHIFT					0
+#define T_CKE_MASK					(0x7 << 0)
+
+/* SDRAM_TIMING_3 */
+#define T_PDLL_UL_SHIFT					28
+#define T_PDLL_UL_MASK					(0xf << 28)
+#define T_CSTA_SHIFT					24
+#define T_CSTA_MASK					(0xf << 24)
+#define T_CKESR_SHIFT					21
+#define T_CKESR_MASK					(0x7 << 21)
+#define ZQ_ZQCS_SHIFT					15
+#define ZQ_ZQCS_MASK					(0x3f << 15)
+#define T_TDQSCKMAX_SHIFT				13
+#define T_TDQSCKMAX_MASK				(0x3 << 13)
+#define T_RFC_SHIFT					4
+#define T_RFC_MASK					(0x1ff << 4)
+#define T_RAS_MAX_SHIFT					0
+#define T_RAS_MAX_MASK					(0xf << 0)
+
+/* POWER_MANAGEMENT_CONTROL */
+#define PD_TIM_SHIFT					12
+#define PD_TIM_MASK					(0xf << 12)
+#define DPD_EN_SHIFT					11
+#define DPD_EN_MASK					(1 << 11)
+#define LP_MODE_SHIFT					8
+#define LP_MODE_MASK					(0x7 << 8)
+#define SR_TIM_SHIFT					4
+#define SR_TIM_MASK					(0xf << 4)
+#define CS_TIM_SHIFT					0
+#define CS_TIM_MASK					(0xf << 0)
+
+/* LPDDR2_MODE_REG_DATA */
+#define VALUE_0_SHIFT					0
+#define VALUE_0_MASK					(0x7f << 0)
+
+/* LPDDR2_MODE_REG_CONFIG */
+#define CS_SHIFT					31
+#define CS_MASK						(1 << 31)
+#define REFRESH_EN_SHIFT				30
+#define REFRESH_EN_MASK					(1 << 30)
+#define ADDRESS_SHIFT					0
+#define ADDRESS_MASK					(0xff << 0)
+
+/* OCP_CONFIG */
+#define SYS_THRESH_MAX_SHIFT				24
+#define SYS_THRESH_MAX_MASK				(0xf << 24)
+#define MPU_THRESH_MAX_SHIFT				20
+#define MPU_THRESH_MAX_MASK				(0xf << 20)
+#define LL_THRESH_MAX_SHIFT				16
+#define LL_THRESH_MAX_MASK				(0xf << 16)
+
+/* PERFORMANCE_COUNTER_1 */
+#define COUNTER1_SHIFT					0
+#define COUNTER1_MASK					(0xffffffff << 0)
+
+/* PERFORMANCE_COUNTER_2 */
+#define COUNTER2_SHIFT					0
+#define COUNTER2_MASK					(0xffffffff << 0)
+
+/* PERFORMANCE_COUNTER_CONFIG */
+#define CNTR2_MCONNID_EN_SHIFT				31
+#define CNTR2_MCONNID_EN_MASK				(1 << 31)
+#define CNTR2_REGION_EN_SHIFT				30
+#define CNTR2_REGION_EN_MASK				(1 << 30)
+#define CNTR2_CFG_SHIFT					16
+#define CNTR2_CFG_MASK					(0xf << 16)
+#define CNTR1_MCONNID_EN_SHIFT				15
+#define CNTR1_MCONNID_EN_MASK				(1 << 15)
+#define CNTR1_REGION_EN_SHIFT				14
+#define CNTR1_REGION_EN_MASK				(1 << 14)
+#define CNTR1_CFG_SHIFT					0
+#define CNTR1_CFG_MASK					(0xf << 0)
+
+/* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */
+#define MCONNID2_SHIFT					24
+#define MCONNID2_MASK					(0xff << 24)
+#define REGION_SEL2_SHIFT				16
+#define REGION_SEL2_MASK				(0x3 << 16)
+#define MCONNID1_SHIFT					8
+#define MCONNID1_MASK					(0xff << 8)
+#define REGION_SEL1_SHIFT				0
+#define REGION_SEL1_MASK				(0x3 << 0)
+
+/* PERFORMANCE_COUNTER_TIME */
+#define TOTAL_TIME_SHIFT				0
+#define TOTAL_TIME_MASK					(0xffffffff << 0)
+
+/* DLL_CALIB_CTRL */
+#define ACK_WAIT_SHIFT					16
+#define ACK_WAIT_MASK					(0xf << 16)
+#define DLL_CALIB_INTERVAL_SHIFT			0
+#define DLL_CALIB_INTERVAL_MASK				(0x1ff << 0)
+
+/* END_OF_INTERRUPT */
+#define EOI_SHIFT					0
+#define EOI_MASK					(1 << 0)
+
+/* SYSTEM_OCP_INTERRUPT_RAW_STATUS */
+#define DNV_SYS_SHIFT					2
+#define DNV_SYS_MASK					(1 << 2)
+#define TA_SYS_SHIFT					1
+#define TA_SYS_MASK					(1 << 1)
+#define ERR_SYS_SHIFT					0
+#define ERR_SYS_MASK					(1 << 0)
+
+/* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */
+#define DNV_LL_SHIFT					2
+#define DNV_LL_MASK					(1 << 2)
+#define TA_LL_SHIFT					1
+#define TA_LL_MASK					(1 << 1)
+#define ERR_LL_SHIFT					0
+#define ERR_LL_MASK					(1 << 0)
+
+/* SYSTEM_OCP_INTERRUPT_ENABLE_SET */
+#define EN_DNV_SYS_SHIFT				2
+#define EN_DNV_SYS_MASK					(1 << 2)
+#define EN_TA_SYS_SHIFT					1
+#define EN_TA_SYS_MASK					(1 << 1)
+#define EN_ERR_SYS_SHIFT					0
+#define EN_ERR_SYS_MASK					(1 << 0)
+
+/* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */
+#define EN_DNV_LL_SHIFT					2
+#define EN_DNV_LL_MASK					(1 << 2)
+#define EN_TA_LL_SHIFT					1
+#define EN_TA_LL_MASK					(1 << 1)
+#define EN_ERR_LL_SHIFT					0
+#define EN_ERR_LL_MASK					(1 << 0)
+
+/* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */
+#define ZQ_CS1EN_SHIFT					31
+#define ZQ_CS1EN_MASK					(1 << 31)
+#define ZQ_CS0EN_SHIFT					30
+#define ZQ_CS0EN_MASK					(1 << 30)
+#define ZQ_DUALCALEN_SHIFT				29
+#define ZQ_DUALCALEN_MASK				(1 << 29)
+#define ZQ_SFEXITEN_SHIFT				28
+#define ZQ_SFEXITEN_MASK				(1 << 28)
+#define ZQ_ZQINIT_MULT_SHIFT				18
+#define ZQ_ZQINIT_MULT_MASK				(0x3 << 18)
+#define ZQ_ZQCL_MULT_SHIFT				16
+#define ZQ_ZQCL_MULT_MASK				(0x3 << 16)
+#define ZQ_REFINTERVAL_SHIFT				0
+#define ZQ_REFINTERVAL_MASK				(0xffff << 0)
+
+/* TEMPERATURE_ALERT_CONFIG */
+#define TA_CS1EN_SHIFT					31
+#define TA_CS1EN_MASK					(1 << 31)
+#define TA_CS0EN_SHIFT					30
+#define TA_CS0EN_MASK					(1 << 30)
+#define TA_SFEXITEN_SHIFT				28
+#define TA_SFEXITEN_MASK				(1 << 28)
+#define TA_DEVWDT_SHIFT					26
+#define TA_DEVWDT_MASK					(0x3 << 26)
+#define TA_DEVCNT_SHIFT					24
+#define TA_DEVCNT_MASK					(0x3 << 24)
+#define TA_REFINTERVAL_SHIFT				0
+#define TA_REFINTERVAL_MASK				(0x3fffff << 0)
+
+/* OCP_ERROR_LOG */
+#define MADDRSPACE_SHIFT				14
+#define MADDRSPACE_MASK					(0x3 << 14)
+#define MBURSTSEQ_SHIFT					11
+#define MBURSTSEQ_MASK					(0x7 << 11)
+#define MCMD_SHIFT					8
+#define MCMD_MASK					(0x7 << 8)
+#define MCONNID_SHIFT					0
+#define MCONNID_MASK					(0xff << 0)
+
+/* DDR_PHY_CTRL_1 - EMIF4D */
+#define DLL_SLAVE_DLY_CTRL_SHIFT_4D			4
+#define DLL_SLAVE_DLY_CTRL_MASK_4D			(0xFF << 4)
+#define READ_LATENCY_SHIFT_4D				0
+#define READ_LATENCY_MASK_4D				(0xf << 0)
+
+/* DDR_PHY_CTRL_1 - EMIF4D5 */
+#define DLL_HALF_DELAY_SHIFT_4D5			21
+#define DLL_HALF_DELAY_MASK_4D5				(1 << 21)
+#define READ_LATENCY_SHIFT_4D5				0
+#define READ_LATENCY_MASK_4D5				(0x1f << 0)
+
+/* DDR_PHY_CTRL_1_SHDW */
+#define DDR_PHY_CTRL_1_SHDW_SHIFT			5
+#define DDR_PHY_CTRL_1_SHDW_MASK			(0x7ffffff << 5)
+#define READ_LATENCY_SHDW_SHIFT				0
+#define READ_LATENCY_SHDW_MASK				(0x1f << 0)
+
+#endif
-- 
1.7.1



From aneesh at ti.com  Thu Mar 15 14:17:33 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu, 15 Mar 2012 23:47:33 +0530
Subject: [PATCH v2 3/7] misc: emif: add basic infrastructure for EMIF driver
In-Reply-To: <1331835457-5390-1-git-send-email-aneesh@ti.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
Message-ID: <1331835457-5390-4-git-send-email-aneesh@ti.com>

EMIF is an SDRAM controller used in various Texas Instruments
SoCs. EMIF supports, based on its revision, one or more of
LPDDR2/DDR2/DDR3 protocols.

Add the basic infrastructure for EMIF driver that includes
driver registration, probe, parsing of platform data etc.

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v2:
- replaced __init with __init_or_module

v1:
- Removed emif_cleanup() function and instead used
  devm_* variant of APIs for resource allocations
- Split include/linux/emif.h into two parts. The first
  part now becomes include/linux/platform_data/emif_plat.h
  and the other part is now merged in drivers/misc/emif.h
- Made error messages more verbose
- Corrected copyright year
- Fixed other coding style comments
- Minor adjustments to patch organization. Moved
  some definitions to a subsequent patch that uses
  them
- Added a list a of devices. This is needed for errata
  i728 workaround and for the new locking scheme
- Added documentation for driver
---
 Documentation/misc-devices/ti-emif.txt  |   58 ++++++
 drivers/misc/Kconfig                    |   12 ++
 drivers/misc/Makefile                   |    1 +
 drivers/misc/emif.c                     |  289 +++++++++++++++++++++++++++++++
 drivers/misc/emif.h                     |    7 +
 include/linux/platform_data/emif_plat.h |  128 ++++++++++++++
 6 files changed, 495 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/misc-devices/ti-emif.txt
 create mode 100644 drivers/misc/emif.c
 create mode 100644 include/linux/platform_data/emif_plat.h

diff --git a/Documentation/misc-devices/ti-emif.txt b/Documentation/misc-devices/ti-emif.txt
new file mode 100644
index 0000000..a9238c1
--- /dev/null
+++ b/Documentation/misc-devices/ti-emif.txt
@@ -0,0 +1,58 @@
+TI EMIF SDRAM Controller Driver:
+
+Author
+========
+Aneesh V <aneesh at ti.com>
+
+Location
+============
+driver/misc/emif.c
+
+Supported SoCs:
+===================
+TI OMAP44xx
+TI OMAP54xx
+
+Menuconfig option:
+==========================
+Device Drivers
+	Misc devices
+		Texas Instruments EMIF driver
+
+Description
+===========
+This driver is for the EMIF module available in Texas Instruments
+SoCs. EMIF is an SDRAM controller that, based on its revision,
+supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
+This driver takes care of only LPDDR2 memories presently. The
+functions of the driver includes re-configuring AC timing
+parameters and other settings during frequency, voltage and
+temperature changes
+
+Platform Data (see include/linux/platform_data/emif_plat.h):
+=====================================================================
+DDR device details and other board dependent and SoC dependent
+information can be passed through platform data (struct emif_platform_data)
+- DDR device details: 'struct ddr_device_info'
+- Device AC timings: 'struct lpddr2_timings' and 'struct lpddr2_min_tck'
+- Custom configurations: customizable policy options through
+  'struct emif_custom_configs'
+- IP revision
+- PHY type
+
+Interface to the external world:
+================================
+EMIF driver registers notifiers for voltage and frequency changes
+affecting EMIF and takes appropriate actions when these are invoked.
+- freq_pre_notify_handling()
+- freq_post_notify_handling()
+- volt_notify_handling()
+
+Debugfs
+========
+The driver creates two debugfs entries per device.
+- regcache_dump : dump of register values calculated and saved for all
+  frequencies used so far.
+- mr4 : last polled value of MR4 register in the LPDDR2 device. MR4
+  indicates the current temperature level of the device.
+
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index c779509..847a936 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -441,6 +441,18 @@ config VMWARE_BALLOON
 	  To compile this driver as a module, choose M here: the
 	  module will be called vmw_balloon.
 
+config TI_EMIF
+	tristate "Texas Instruments EMIF driver"
+	select DDR
+	help
+	  This driver is for the EMIF module available in Texas Instruments
+	  SoCs. EMIF is an SDRAM controller that, based on its revision,
+	  supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
+	  This driver takes care of only LPDDR2 memories presently. The
+	  functions of the driver includes re-configuring AC timing
+	  parameters and other settings during frequency, voltage and
+	  temperature changes
+
 config ARM_CHARLCD
 	bool "ARM Ltd. Character LCD Driver"
 	depends on PLAT_VERSATILE
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3e1d801..75ab920 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_TI_DAC7512)	+= ti_dac7512.o
 obj-$(CONFIG_C2PORT)		+= c2port/
 obj-$(CONFIG_IWMC3200TOP)      += iwmc3200top/
 obj-$(CONFIG_HMC6352)		+= hmc6352.o
+obj-$(CONFIG_TI_EMIF)		+= emif.o
 obj-y				+= eeprom/
 obj-y				+= cb710/
 obj-$(CONFIG_SPEAR13XX_PCIE_GADGET)	+= spear13xx_pcie_gadget.o
diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
new file mode 100644
index 0000000..f864640
--- /dev/null
+++ b/drivers/misc/emif.c
@@ -0,0 +1,289 @@
+/*
+ * EMIF driver
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ * Santosh Shilimkar <santosh.shilimkar at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/platform_data/emif_plat.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/seq_file.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <misc/jedec_ddr.h>
+#include "emif.h"
+
+/**
+ * struct emif_data - Per device static data for driver's use
+ * @duplicate:			Whether the DDR devices attached to this EMIF
+ *				instance are exactly same as that on EMIF1. In
+ *				this case we can save some memory and processing
+ * @temperature_level:		Maximum temperature of LPDDR2 devices attached
+ *				to this EMIF - read from MR4 register. If there
+ *				are two devices attached to this EMIF, this
+ *				value is the maximum of the two temperature
+ *				levels.
+ * @node:			node in the device list
+ * @base:			base address of memory-mapped IO registers.
+ * @dev:			device pointer.
+ * @plat_data:			Pointer to saved platform data.
+ */
+struct emif_data {
+	u8				duplicate;
+	u8				temperature_level;
+	struct list_head		node;
+	void __iomem			*base;
+	struct device			*dev;
+	struct emif_platform_data	*plat_data;
+};
+
+static struct emif_data *emif1;
+static LIST_HEAD(device_list);
+
+static void get_default_timings(struct emif_data *emif)
+{
+	struct emif_platform_data *pd = emif->plat_data;
+
+	pd->timings		= lpddr2_jedec_timings;
+	pd->timings_arr_size	= ARRAY_SIZE(lpddr2_jedec_timings);
+
+	dev_warn(emif->dev, "%s: using default timings\n", __func__);
+}
+
+static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
+		u32 ip_rev, struct device *dev)
+{
+	int valid;
+
+	valid = (type == DDR_TYPE_LPDDR2_S4 ||
+			type == DDR_TYPE_LPDDR2_S2)
+		&& (density >= DDR_DENSITY_64Mb
+			&& density <= DDR_DENSITY_8Gb)
+		&& (io_width >= DDR_IO_WIDTH_8
+			&& io_width <= DDR_IO_WIDTH_32);
+
+	/* Combinations of EMIF and PHY revisions that we support today */
+	switch (ip_rev) {
+	case EMIF_4D:
+		valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
+		break;
+	case EMIF_4D5:
+		valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
+		break;
+	default:
+		valid = 0;
+	}
+
+	if (!valid)
+		dev_err(dev, "%s: invalid DDR details\n", __func__);
+	return valid;
+}
+
+static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
+		struct device *dev)
+{
+	int valid = 1;
+
+	if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
+		(cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
+		valid = cust_cfgs->lpmode_freq_threshold &&
+			cust_cfgs->lpmode_timeout_performance &&
+			cust_cfgs->lpmode_timeout_power;
+
+	if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
+		valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
+
+	if (!valid)
+		dev_warn(dev, "%s: invalid custom configs\n", __func__);
+
+	return valid;
+}
+
+static struct emif_data *__init_or_module get_device_details(
+		struct platform_device *pdev)
+{
+	u32				size;
+	struct emif_data		*emif = NULL;
+	struct ddr_device_info		*dev_info;
+	struct emif_custom_configs	*cust_cfgs;
+	struct emif_platform_data	*pd;
+	struct device			*dev;
+	void				*temp;
+
+	pd = pdev->dev.platform_data;
+	dev = &pdev->dev;
+
+	if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
+			pd->device_info->density, pd->device_info->io_width,
+			pd->phy_type, pd->ip_rev, dev))) {
+		dev_err(dev, "%s: invalid device data\n", __func__);
+		goto error;
+	}
+
+	emif	= devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
+	temp	= devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+	dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
+
+	if (!emif || !pd || !dev_info) {
+		dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__);
+		goto error;
+	}
+
+	memcpy(temp, pd, sizeof(*pd));
+	pd = temp;
+	memcpy(dev_info, pd->device_info, sizeof(*dev_info));
+
+	pd->device_info		= dev_info;
+	emif->plat_data		= pd;
+	emif->dev		= dev;
+	emif->temperature_level	= SDRAM_TEMP_NOMINAL;
+
+	/*
+	 * For EMIF instances other than EMIF1 see if the devices connected
+	 * are exactly same as on EMIF1(which is typically the case). If so,
+	 * mark it as a duplicate of EMIF1 and skip copying timings data.
+	 * This will save some memory and some computation later.
+	 */
+	emif->duplicate = emif1 && (memcmp(dev_info,
+		emif1->plat_data->device_info,
+		sizeof(struct ddr_device_info)) == 0);
+
+	if (emif->duplicate) {
+		pd->timings = NULL;
+		pd->min_tck = NULL;
+		goto out;
+	} else if (emif1) {
+		dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
+			__func__);
+	}
+
+	/*
+	 * Copy custom configs - ignore allocation error, if any, as
+	 * custom_configs is not very critical
+	 */
+	cust_cfgs = pd->custom_configs;
+	if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
+		temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
+		if (temp)
+			memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
+		else
+			dev_warn(dev, "%s:%d: allocation error\n", __func__,
+				__LINE__);
+		pd->custom_configs = temp;
+	}
+
+	/*
+	 * Copy timings and min-tck values from platform data. If it is not
+	 * available or if memory allocation fails, use JEDEC defaults
+	 */
+	size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
+	if (pd->timings) {
+		temp = devm_kzalloc(dev, size, GFP_KERNEL);
+		if (temp) {
+			memcpy(temp, pd->timings, sizeof(*pd->timings));
+			pd->timings = temp;
+		} else {
+			dev_warn(dev, "%s:%d: allocation error\n", __func__,
+				__LINE__);
+			get_default_timings(emif);
+		}
+	} else {
+		get_default_timings(emif);
+	}
+
+	if (pd->min_tck) {
+		temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
+		if (temp) {
+			memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
+			pd->min_tck = temp;
+		} else {
+			dev_warn(dev, "%s:%d: allocation error\n", __func__,
+				__LINE__);
+			pd->min_tck = &lpddr2_jedec_min_tck;
+		}
+	} else {
+		pd->min_tck = &lpddr2_jedec_min_tck;
+	}
+
+out:
+	return emif;
+
+error:
+	return NULL;
+}
+
+static int __init_or_module emif_probe(struct platform_device *pdev)
+{
+	struct emif_data	*emif;
+	struct resource		*res;
+
+	emif = get_device_details(pdev);
+	if (!emif) {
+		pr_err("%s: error getting device data\n", __func__);
+		goto error;
+	}
+
+	if (!emif1)
+		emif1 = emif;
+
+	list_add(&emif->node, &device_list);
+
+	/* Save pointers to each other in emif and device structures */
+	emif->dev = &pdev->dev;
+	platform_set_drvdata(pdev, emif);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(emif->dev, "%s: error getting memory resource\n",
+			__func__);
+		goto error;
+	}
+
+	emif->base = devm_request_and_ioremap(emif->dev, res);
+	if (!emif->base) {
+		dev_err(emif->dev, "%s: devm_request_and_ioremap() failed\n",
+			__func__);
+		goto error;
+	}
+
+	dev_info(&pdev->dev, "%s: device configured with addr = %p\n",
+		__func__, emif->base);
+
+	return 0;
+error:
+	return -ENODEV;
+}
+
+static struct platform_driver emif_driver = {
+	.driver = {
+		.name = "emif",
+	},
+};
+
+static int __init_or_module emif_register(void)
+{
+	return platform_driver_probe(&emif_driver, emif_probe);
+}
+
+static void __exit emif_unregister(void)
+{
+	platform_driver_unregister(&emif_driver);
+}
+
+module_init(emif_register);
+module_exit(emif_unregister);
+MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:emif");
+MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/drivers/misc/emif.h b/drivers/misc/emif.h
index 44b97df..692b2a8 100644
--- a/drivers/misc/emif.h
+++ b/drivers/misc/emif.h
@@ -12,6 +12,13 @@
 #ifndef __EMIF_H
 #define __EMIF_H
 
+/*
+ * Maximum number of different frequencies supported by EMIF driver
+ * Determines the number of entries in the pointer array for register
+ * cache
+ */
+#define EMIF_MAX_NUM_FREQUENCIES			6
+
 /* Registers offset */
 #define EMIF_MODULE_ID_AND_REVISION			0x0000
 #define EMIF_STATUS					0x0004
diff --git a/include/linux/platform_data/emif_plat.h b/include/linux/platform_data/emif_plat.h
new file mode 100644
index 0000000..03378ca
--- /dev/null
+++ b/include/linux/platform_data/emif_plat.h
@@ -0,0 +1,128 @@
+/*
+ * Definitions for TI EMIF device platform data
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __EMIF_PLAT_H
+#define __EMIF_PLAT_H
+
+/* Low power modes - EMIF_PWR_MGMT_CTRL */
+#define EMIF_LP_MODE_DISABLE				0
+#define EMIF_LP_MODE_CLOCK_STOP				1
+#define EMIF_LP_MODE_SELF_REFRESH			2
+#define EMIF_LP_MODE_PWR_DN				4
+
+/* Hardware capabilities */
+#define	EMIF_HW_CAPS_LL_INTERFACE			0x00000001
+
+/*
+ * EMIF IP Revisions
+ *	EMIF4D  - Used in OMAP4
+ *	EMIF4D5 - Used in OMAP5
+ */
+#define	EMIF_4D						1
+#define	EMIF_4D5					2
+
+/*
+ * PHY types
+ *	ATTILAPHY  - Used in OMAP4
+ *	INTELLIPHY - Used in OMAP5
+ */
+#define	EMIF_PHY_TYPE_ATTILAPHY				1
+#define	EMIF_PHY_TYPE_INTELLIPHY			2
+
+/* Custom config requests */
+#define EMIF_CUSTOM_CONFIG_LPMODE			0x00000001
+#define EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL	0x00000002
+
+#ifndef __ASSEMBLY__
+/**
+ * struct ddr_device_info - All information about the DDR device except AC
+ *		timing parameters
+ * @type:	Device type (LPDDR2-S4, LPDDR2-S2 etc)
+ * @density:	Device density
+ * @io_width:	Bus width
+ * @cs1_used:	Whether there is a DDR device attached to the second
+ *		chip-select(CS1) of this EMIF instance
+ * @cal_resistors_per_cs: Whether there is one calibration resistor per
+ *		chip-select or whether it's a single one for both
+ * @manufacturer: Manufacturer name string
+ */
+struct ddr_device_info {
+	u32	type;
+	u32	density;
+	u32	io_width;
+	u32	cs1_used;
+	u32	cal_resistors_per_cs;
+	char	manufacturer[10];
+};
+
+/**
+ * struct emif_custom_configs - Custom configuration parameters/policies
+ *		passed from the platform layer
+ * @mask:	Mask to indicate which configs are requested
+ * @lpmode:	LPMODE to be used in PWR_MGMT_CTRL register
+ * @lpmode_timeout_performance: Timeout before LPMODE entry when higher
+ *		performance is desired at the cost of power (typically
+ *		at higher OPPs)
+ * @lpmode_timeout_power: Timeout before LPMODE entry when better power
+ *		savings is desired and performance is not important
+ *		(typically at lower loads indicated by lower OPPs)
+ * @lpmode_freq_threshold: The DDR frequency threshold to identify between
+ *		the above two cases:
+ *		timeout = (freq >= lpmode_freq_threshold) ?
+ *			lpmode_timeout_performance :
+ *			lpmode_timeout_power;
+ * @temp_alert_poll_interval_ms: LPDDR2 MR4 polling interval at nominal
+ *		temperature(in milliseconds). When temperature is high
+ *		polling is done 4 times as frequently.
+ */
+struct emif_custom_configs {
+	u32 mask;
+	u32 lpmode;
+	u32 lpmode_timeout_performance;
+	u32 lpmode_timeout_power;
+	u32 lpmode_freq_threshold;
+	u32 temp_alert_poll_interval_ms;
+};
+
+/**
+ * struct emif_platform_data - Platform data passed on EMIF platform
+ *				device creation. Used by the driver.
+ * @hw_caps:		Hw capabilities of the EMIF IP in the respective SoC
+ * @device_info:	Device info structure containing information such
+ *			as type, bus width, density etc
+ * @timings:		Timings information from device datasheet passed
+ *			as an array of 'struct lpddr2_timings'. Can be NULL
+ *			if if default timings are ok
+ * @timings_arr_size:	Size of the timings array. Depends on the number
+ *			of different frequencies for which timings data
+ *			is provided
+ * @min_tck:		Minimum value of some timing parameters in terms
+ *			of number of cycles. Can be NULL if default values
+ *			are ok
+ * @custom_configs:	Custom configurations requested by SoC or board
+ *			code and the data for them. Can be NULL if default
+ *			configurations done by the driver are ok. See
+ *			documentation for 'struct emif_custom_configs' for
+ *			more details
+ */
+struct emif_platform_data {
+	u32 hw_caps;
+	struct ddr_device_info *device_info;
+	const struct lpddr2_timings *timings;
+	u32 timings_arr_size;
+	const struct lpddr2_min_tck *min_tck;
+	struct emif_custom_configs *custom_configs;
+	u32 ip_rev;
+	u32 phy_type;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif /* __LINUX_EMIF_H */
-- 
1.7.1



From aneesh at ti.com  Thu Mar 15 14:17:35 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu, 15 Mar 2012 23:47:35 +0530
Subject: [PATCH v2 5/7] misc: emif: add interrupt and temperature handling
In-Reply-To: <1331835457-5390-1-git-send-email-aneesh@ti.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
Message-ID: <1331835457-5390-6-git-send-email-aneesh@ti.com>

Add an ISR for EMIF that:
	1. reports details of access errors
	2. takes action on thermal events

Also clear all interrupts on shut-down. Pending IRQs
may casue problems during warm-reset.

Temperature handling:
EMIF can be configured to poll the temperature level
of an LPDDR2 device from the MR4 mode register in the
device. EMIF generates an interrupt whenever it identifies
a temperature level change between two consecutive pollings.

Some of the timing parameters need to be de-rated at high
temperatures. The interrupt handler takes care of doing
this and also takes care of going back to nominal settings
when temperature falls back to nominal levels.

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---

v2:
- replaced __init with __init_or_module

v1:
- Improved commit log
- Improved synchronization with thread context
---
 drivers/misc/emif.c |  211 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 209 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index 1ca8165..52048f4 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
@@ -545,6 +545,42 @@ static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
 }
 
 /*
+ * Get the temperature level of the EMIF instance:
+ * Reads the MR4 register of attached SDRAM parts to find out the temperature
+ * level. If there are two parts attached(one on each CS), then the temperature
+ * level for the EMIF instance is the higher of the two temperatures.
+ */
+static void get_temperature_level(struct emif_data *emif)
+{
+	u32		temp, temperature_level;
+	void __iomem	*base;
+
+	base = emif->base;
+
+	/* Read mode register 4 */
+	writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
+	temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
+	temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
+				MR4_SDRAM_REF_RATE_SHIFT;
+
+	if (emif->plat_data->device_info->cs1_used) {
+		writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
+		temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
+		temp = (temp & MR4_SDRAM_REF_RATE_MASK)
+				>> MR4_SDRAM_REF_RATE_SHIFT;
+		temperature_level = max(temp, temperature_level);
+	}
+
+	/* treat everything less than nominal(3) in MR4 as nominal */
+	if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
+		temperature_level = SDRAM_TEMP_NOMINAL;
+
+	/* if we get reserved value in MR4 persist with the existing value */
+	if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
+		emif->temperature_level = temperature_level;
+}
+
+/*
  * Program EMIF shadow registers that are not dependent on temperature
  * or voltage
  */
@@ -627,6 +663,158 @@ out:
 	writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
 }
 
+static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
+{
+	u32		old_temp_level;
+	irqreturn_t	ret = IRQ_HANDLED;
+
+	spin_lock_irqsave(&emif_lock, irq_state);
+	old_temp_level = emif->temperature_level;
+	get_temperature_level(emif);
+
+	if (unlikely(emif->temperature_level == old_temp_level)) {
+		goto out;
+	} else if (!emif->curr_regs) {
+		dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
+		goto out;
+	}
+
+	if (emif->temperature_level < old_temp_level ||
+		emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
+		/*
+		 * Temperature coming down - defer handling to thread OR
+		 * Temperature far too high - do kernel_power_off() from
+		 * thread context
+		 */
+		ret = IRQ_WAKE_THREAD;
+	} else {
+		/* Temperature is going up - handle immediately */
+		setup_temperature_sensitive_regs(emif, emif->curr_regs);
+		do_freq_update();
+	}
+
+out:
+	spin_unlock_irqrestore(&emif_lock, irq_state);
+	return ret;
+}
+
+static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
+{
+	u32			interrupts;
+	struct emif_data	*emif = dev_id;
+	void __iomem		*base = emif->base;
+	struct device		*dev = emif->dev;
+	irqreturn_t		ret = IRQ_HANDLED;
+
+	/* Save the status and clear it */
+	interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
+	writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
+
+	/*
+	 * Handle temperature alert
+	 * Temperature alert should be same for all ports
+	 * So, it's enough to process it only for one of the ports
+	 */
+	if (interrupts & TA_SYS_MASK)
+		ret = handle_temp_alert(base, emif);
+
+	if (interrupts & ERR_SYS_MASK)
+		dev_err(dev, "Access error from SYS port - %x\n", interrupts);
+
+	if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
+		/* Save the status and clear it */
+		interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
+		writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
+
+		if (interrupts & ERR_LL_MASK)
+			dev_err(dev, "Access error from LL port - %x\n",
+				interrupts);
+	}
+
+	return ret;
+}
+
+static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
+{
+	struct emif_data	*emif = dev_id;
+
+	if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
+		dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
+		kernel_power_off();
+		return IRQ_HANDLED;
+	}
+
+	spin_lock_irqsave(&emif_lock, irq_state);
+
+	if (emif->curr_regs) {
+		setup_temperature_sensitive_regs(emif, emif->curr_regs);
+		do_freq_update();
+	} else {
+		dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
+	}
+
+	spin_unlock_irqrestore(&emif_lock, irq_state);
+
+	return IRQ_HANDLED;
+}
+
+static void clear_all_interrupts(struct emif_data *emif)
+{
+	void __iomem	*base = emif->base;
+
+	writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
+		base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
+	if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
+		writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
+			base + EMIF_LL_OCP_INTERRUPT_STATUS);
+}
+
+static void disable_and_clear_all_interrupts(struct emif_data *emif)
+{
+	void __iomem		*base = emif->base;
+
+	/* Disable all interrupts */
+	writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
+		base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
+	if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
+		writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
+			base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
+
+	/* Clear all interrupts */
+	clear_all_interrupts(emif);
+}
+
+static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
+{
+	u32		interrupts, type;
+	void __iomem	*base = emif->base;
+
+	type = emif->plat_data->device_info->type;
+
+	clear_all_interrupts(emif);
+
+	/* Enable interrupts for SYS interface */
+	interrupts = EN_ERR_SYS_MASK;
+	if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
+		interrupts |= EN_TA_SYS_MASK;
+	writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
+
+	/* Enable interrupts for LL interface */
+	if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
+		/* TA need not be enabled for LL */
+		interrupts = EN_ERR_LL_MASK;
+		writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
+	}
+
+	/* setup IRQ handlers */
+	return devm_request_threaded_irq(emif->dev, irq,
+				    emif_interrupt_handler,
+				    emif_threaded_isr,
+				    0, dev_name(emif->dev),
+				    emif);
+
+}
+
 static void get_default_timings(struct emif_data *emif)
 {
 	struct emif_platform_data *pd = emif->plat_data;
@@ -803,6 +991,7 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 {
 	struct emif_data	*emif;
 	struct resource		*res;
+	int			irq;
 
 	emif = get_device_details(pdev);
 	if (!emif) {
@@ -831,6 +1020,16 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 		goto error;
 	}
 
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(emif->dev, "%s: error getting IRQ resource - %d\n",
+			__func__, irq);
+		goto error;
+	}
+
+	disable_and_clear_all_interrupts(emif);
+	setup_interrupts(emif, irq);
+
 	/* One-time actions taken on probing the first device */
 	if (!emif1) {
 		emif1 = emif;
@@ -843,14 +1042,21 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 		 */
 	}
 
-	dev_info(&pdev->dev, "%s: device configured with addr = %p\n",
-		__func__, emif->base);
+	dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
+		__func__, emif->base, irq);
 
 	return 0;
 error:
 	return -ENODEV;
 }
 
+static void emif_shutdown(struct platform_device *pdev)
+{
+	struct emif_data	*emif = platform_get_drvdata(pdev);
+
+	disable_and_clear_all_interrupts(emif);
+}
+
 static int get_emif_reg_values(struct emif_data *emif, u32 freq,
 		struct emif_regs *regs)
 {
@@ -1154,6 +1360,7 @@ static void __attribute__((unused)) freq_post_notify_handling(void)
 }
 
 static struct platform_driver emif_driver = {
+	.shutdown	= emif_shutdown,
 	.driver = {
 		.name = "emif",
 	},
-- 
1.7.1



From aneesh at ti.com  Thu Mar 15 14:17:36 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu, 15 Mar 2012 23:47:36 +0530
Subject: [PATCH v2 6/7] misc: emif: add one-time settings
In-Reply-To: <1331835457-5390-1-git-send-email-aneesh@ti.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
Message-ID: <1331835457-5390-7-git-send-email-aneesh@ti.com>

Add settings that are not dependent on frequency
or any other transient parameters. This includes
- power managment control init
- impedence calibration control
- frequency independent phy configuration registers
- initialization of temperature polling

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v2:
- replaced __init with __init_or_module
- fixed bug in the implementation of i728 errata workaround

v1:
- Improved commit log
- Changes for errata i728 workaround
---
 drivers/misc/emif.c |  148 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 148 insertions(+), 0 deletions(-)

diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index 52048f4..270a0e4 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
@@ -78,6 +78,24 @@ static void set_ddr_clk_period(u32 freq)
 }
 
 /*
+ * Get bus width used by EMIF. Note that this may be different from the
+ * bus width of the DDR devices used. For instance two 16-bit DDR devices
+ * may be connected to a given CS of EMIF. In this case bus width as far
+ * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
+ */
+static u32 get_emif_bus_width(struct emif_data *emif)
+{
+	u32		width;
+	void __iomem	*base = emif->base;
+
+	width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
+			>> NARROW_MODE_SHIFT;
+	width = width == 0 ? 32 : 16;
+
+	return width;
+}
+
+/*
  * Get the CL from SDRAM_CONFIG register
  */
 static u32 get_cl(struct emif_data *emif)
@@ -372,6 +390,70 @@ static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
 	return tim3;
 }
 
+static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
+		bool cs1_used, bool cal_resistors_per_cs)
+{
+	u32 zq = 0, val = 0;
+
+	val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
+	zq |= val << ZQ_REFINTERVAL_SHIFT;
+
+	val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
+	zq |= val << ZQ_ZQCL_MULT_SHIFT;
+
+	val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
+	zq |= val << ZQ_ZQINIT_MULT_SHIFT;
+
+	zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
+
+	if (cal_resistors_per_cs)
+		zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
+	else
+		zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
+
+	zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
+
+	val = cs1_used ? 1 : 0;
+	zq |= val << ZQ_CS1EN_SHIFT;
+
+	return zq;
+}
+
+static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
+		const struct emif_custom_configs *custom_configs, bool cs1_used,
+		u32 sdram_io_width, u32 emif_bus_width)
+{
+	u32 alert = 0, interval, devcnt;
+
+	if (custom_configs && (custom_configs->mask &
+				EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
+		interval = custom_configs->temp_alert_poll_interval_ms;
+	else
+		interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
+
+	interval *= 1000000;			/* Convert to ns */
+	interval /= addressing->tREFI_ns;	/* Convert to refresh cycles */
+	alert |= (interval << TA_REFINTERVAL_SHIFT);
+
+	/*
+	 * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
+	 * also to this form and subtract to get TA_DEVCNT, which is
+	 * in log2(x) form.
+	 */
+	emif_bus_width = __fls(emif_bus_width) - 1;
+	devcnt = emif_bus_width - sdram_io_width;
+	alert |= devcnt << TA_DEVCNT_SHIFT;
+
+	/* DEVWDT is in 'log2(x) - 3' form */
+	alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
+
+	alert |= 1 << TA_SFEXITEN_SHIFT;
+	alert |= 1 << TA_CS0EN_SHIFT;
+	alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
+
+	return alert;
+}
+
 static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
 {
 	u32 idle = 0, val = 0;
@@ -815,6 +897,71 @@ static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
 
 }
 
+static void __init_or_module emif_onetime_settings(struct emif_data *emif)
+{
+	u32				pwr_mgmt_ctrl, zq, temp_alert_cfg;
+	void __iomem			*base = emif->base;
+	const struct lpddr2_addressing	*addressing;
+	const struct ddr_device_info	*device_info;
+
+	device_info = emif->plat_data->device_info;
+	addressing = get_addressing_table(device_info);
+
+	/*
+	 * Init power management settings
+	 * We don't know the frequency yet. Use a high frequency
+	 * value for a conservative timeout setting
+	 */
+	pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
+			emif->plat_data->ip_rev);
+	emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
+	writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
+
+	/* Init ZQ calibration settings */
+	zq = get_zq_config_reg(addressing, device_info->cs1_used,
+		device_info->cal_resistors_per_cs);
+	writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
+
+	/* Check temperature level temperature level*/
+	get_temperature_level(emif);
+	if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
+		dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
+
+	/* Init temperature polling */
+	temp_alert_cfg = get_temp_alert_config(addressing,
+		emif->plat_data->custom_configs, device_info->cs1_used,
+		device_info->io_width, get_emif_bus_width(emif));
+	writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
+
+	/*
+	 * Program external PHY control registers that are not frequency
+	 * dependent
+	 */
+	if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
+		return;
+	writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
+}
+
 static void get_default_timings(struct emif_data *emif)
 {
 	struct emif_platform_data *pd = emif->plat_data;
@@ -1027,6 +1174,7 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 		goto error;
 	}
 
+	emif_onetime_settings(emif);
 	disable_and_clear_all_interrupts(emif);
 	setup_interrupts(emif, irq);
 
-- 
1.7.1



From aneesh at ti.com  Thu Mar 15 14:17:37 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu, 15 Mar 2012 23:47:37 +0530
Subject: [PATCH v2 7/7] misc: emif: add debugfs entries for emif
In-Reply-To: <1331835457-5390-1-git-send-email-aneesh@ti.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
Message-ID: <1331835457-5390-8-git-send-email-aneesh@ti.com>

Add debug entries for:
	1. calculated registers per frequency
	2. last polled value of MR4(temperature level
	   of LPDDR2 memory)

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v2:
- Corrected the frequency value shown in
  register cache dump
- replaced __init with __init_or_module
---
 drivers/misc/emif.c |  138 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 138 insertions(+), 0 deletions(-)

diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index 270a0e4..6d2f776 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
+#include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/module.h>
 #include <linux/list.h>
@@ -47,6 +48,7 @@
  *				frequency change (i.e. corresponding to the
  *				frequency in effect at the moment)
  * @plat_data:			Pointer to saved platform data.
+ * @debugfs_root:		dentry to the root folder for EMIF in debugfs
  */
 struct emif_data {
 	u8				duplicate;
@@ -60,6 +62,7 @@ struct emif_data {
 	struct emif_regs		*regs_cache[EMIF_MAX_NUM_FREQUENCIES];
 	struct emif_regs		*curr_regs;
 	struct emif_platform_data	*plat_data;
+	struct dentry			*debugfs_root;
 };
 
 static struct emif_data *emif1;
@@ -68,6 +71,130 @@ static unsigned long	irq_state;
 static u32		t_ck; /* DDR clock period in ps */
 static LIST_HEAD(device_list);
 
+static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
+	struct emif_regs *regs)
+{
+	u32 type = emif->plat_data->device_info->type;
+	u32 ip_rev = emif->plat_data->ip_rev;
+
+	seq_printf(s, "EMIF register cache dump for %dMHz\n",
+		regs->freq/1000000);
+
+	seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
+	seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
+	seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
+	seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
+
+	if (ip_rev == EMIF_4D) {
+		seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
+			regs->read_idle_ctrl_shdw_normal);
+		seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
+			regs->read_idle_ctrl_shdw_volt_ramp);
+	} else if (ip_rev == EMIF_4D5) {
+		seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
+			regs->dll_calib_ctrl_shdw_normal);
+		seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
+			regs->dll_calib_ctrl_shdw_volt_ramp);
+	}
+
+	if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
+		seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
+			regs->ref_ctrl_shdw_derated);
+		seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
+			regs->sdram_tim1_shdw_derated);
+		seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
+			regs->sdram_tim3_shdw_derated);
+	}
+}
+
+static int emif_regdump_show(struct seq_file *s, void *unused)
+{
+	struct emif_data	*emif	= s->private;
+	struct emif_regs	**regs_cache;
+	int			i;
+
+	if (emif->duplicate)
+		regs_cache = emif1->regs_cache;
+	else
+		regs_cache = emif->regs_cache;
+
+	for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
+		do_emif_regdump_show(s, emif, regs_cache[i]);
+		seq_printf(s, "\n");
+	}
+
+	return 0;
+}
+
+static int emif_regdump_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, emif_regdump_show, inode->i_private);
+}
+
+static const struct file_operations emif_regdump_fops = {
+	.open			= emif_regdump_open,
+	.read			= seq_read,
+	.release		= single_release,
+};
+
+static int emif_mr4_show(struct seq_file *s, void *unused)
+{
+	struct emif_data *emif = s->private;
+
+	seq_printf(s, "MR4=%d\n", emif->temperature_level);
+	return 0;
+}
+
+static int emif_mr4_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, emif_mr4_show, inode->i_private);
+}
+
+static const struct file_operations emif_mr4_fops = {
+	.open			= emif_mr4_open,
+	.read			= seq_read,
+	.release		= single_release,
+};
+
+static int __init_or_module emif_debugfs_init(struct emif_data *emif)
+{
+	struct dentry	*dentry;
+	int		ret;
+
+	dentry = debugfs_create_dir(dev_name(emif->dev), NULL);
+	if (IS_ERR(dentry)) {
+		ret = PTR_ERR(dentry);
+		goto err0;
+	}
+	emif->debugfs_root = dentry;
+
+	dentry = debugfs_create_file("regcache_dump", S_IRUGO,
+			emif->debugfs_root, emif, &emif_regdump_fops);
+	if (IS_ERR(dentry)) {
+		ret = PTR_ERR(dentry);
+		goto err1;
+	}
+
+	dentry = debugfs_create_file("mr4", S_IRUGO,
+			emif->debugfs_root, emif, &emif_mr4_fops);
+	if (IS_ERR(dentry)) {
+		ret = PTR_ERR(dentry);
+		goto err1;
+	}
+
+	return 0;
+err1:
+	debugfs_remove_recursive(emif->debugfs_root);
+err0:
+	return ret;
+}
+
+static void __exit emif_debugfs_exit(struct emif_data *emif)
+{
+	debugfs_remove_recursive(emif->debugfs_root);
+	emif->debugfs_root = NULL;
+}
+
 /*
  * Calculate the period of DDR clock from frequency value
  */
@@ -1175,6 +1302,7 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 	}
 
 	emif_onetime_settings(emif);
+	emif_debugfs_init(emif);
 	disable_and_clear_all_interrupts(emif);
 	setup_interrupts(emif, irq);
 
@@ -1198,6 +1326,15 @@ error:
 	return -ENODEV;
 }
 
+static int __exit emif_remove(struct platform_device *pdev)
+{
+	struct emif_data *emif = platform_get_drvdata(pdev);
+
+	emif_debugfs_exit(emif);
+
+	return 0;
+}
+
 static void emif_shutdown(struct platform_device *pdev)
 {
 	struct emif_data	*emif = platform_get_drvdata(pdev);
@@ -1508,6 +1645,7 @@ static void __attribute__((unused)) freq_post_notify_handling(void)
 }
 
 static struct platform_driver emif_driver = {
+	.remove		= __exit_p(emif_remove),
 	.shutdown	= emif_shutdown,
 	.driver = {
 		.name = "emif",
-- 
1.7.1



From nm at ti.com  Thu Mar 15 14:24:31 2012
From: nm at ti.com (Nishanth Menon)
Date: Thu, 15 Mar 2012 13:24:31 -0500
Subject: [PATCH] OMAP: clock: fix race in disable all clocks
Message-ID: <1331835871-13328-1-git-send-email-nm@ti.com>

clk_disable_unused is invoked when CONFIG_OMAP_RESET_CLOCKS=y.
Since clk_disable_unused is called as lateinitcall, there can
be more than a few workqueues executing off secondary CPU(s).
The current code does the following:
a) checks if clk is unused
b) holds lock
c) disables clk
d) unlocks

Between (a) and (b) being executed on CPU0, It is possible to
have a driver executing on CPU1 which could do a get_sync->clk_get
(and increase the use_count) of the clock which was just about
to be disabled by clk_disable_unused.

We ensure instead that the entire list traversal is protected by
the lock allowing for parent child clock traversal which could be
potentially be done by runtime operations to be safe as well.

Reported-by: Todd Poynor <toddpoynor at google.com>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
To confirm this in reality happens, I setup a trap as follows:
  @@ -450,6 +450,8 @@ static int __init clk_disable_unused(void)
  			continue;
  
  		spin_lock_irqsave(&clockfw_lock, flags);
 +		WARN(ck->usecount, "XXXX->RACECONDITION FOR CLOCK %s\n",
 +			ck->name);
  		arch_clock->clk_disable_unused(ck);
  		spin_unlock_irqrestore(&clockfw_lock, flags);
  	}
Resultant log: http://pastebin.pandaboard.org/index.php/view/66400792

 arch/arm/plat-omap/clock.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 567e4b5..8030cc1 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -442,6 +442,8 @@ static int __init clk_disable_unused(void)
 		return 0;
 
 	pr_info("clock: disabling unused clocks to save power\n");
+
+	spin_lock_irqsave(&clockfw_lock, flags);
 	list_for_each_entry(ck, &clocks, node) {
 		if (ck->ops == &clkops_null)
 			continue;
@@ -449,10 +451,9 @@ static int __init clk_disable_unused(void)
 		if (ck->usecount > 0 || !ck->enable_reg)
 			continue;
 
-		spin_lock_irqsave(&clockfw_lock, flags);
 		arch_clock->clk_disable_unused(ck);
-		spin_unlock_irqrestore(&clockfw_lock, flags);
 	}
+	spin_unlock_irqrestore(&clockfw_lock, flags);
 
 	return 0;
 }
-- 
1.7.0.4



From aneesh at ti.com  Thu Mar 15 14:17:31 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu, 15 Mar 2012 23:47:31 +0530
Subject: [PATCH v2 1/7] misc: ddr: add LPDDR2 data from JESD209-2
In-Reply-To: <1331835457-5390-1-git-send-email-aneesh@ti.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
Message-ID: <1331835457-5390-2-git-send-email-aneesh@ti.com>

add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:

1. Addressing information for LPDDR2 memories of different
   densities and types(S2/S4)
2. AC timing data.

This data will useful for memory controller device drivers

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v1:
- Moved to /lib from /drivers/misc
- Corrected Copyright year
---
 include/misc/jedec_ddr.h |  177 ++++++++++++++++++++++++++++++++++++++++++++++
 lib/Kconfig              |    8 ++
 lib/Makefile             |    3 +
 lib/jedec_ddr_data.c     |  135 +++++++++++++++++++++++++++++++++++
 4 files changed, 323 insertions(+), 0 deletions(-)
 create mode 100644 include/misc/jedec_ddr.h
 create mode 100644 lib/jedec_ddr_data.c

diff --git a/include/misc/jedec_ddr.h b/include/misc/jedec_ddr.h
new file mode 100644
index 0000000..93ffd4a
--- /dev/null
+++ b/include/misc/jedec_ddr.h
@@ -0,0 +1,177 @@
+/*
+ * Definitions for DDR memories based on JEDEC specs
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_JEDEC_DDR_H
+#define __LINUX_JEDEC_DDR_H
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
+/* DDR Densities */
+#define DDR_DENSITY_64Mb	1
+#define DDR_DENSITY_128Mb	2
+#define DDR_DENSITY_256Mb	3
+#define DDR_DENSITY_512Mb	4
+#define DDR_DENSITY_1Gb		5
+#define DDR_DENSITY_2Gb		6
+#define DDR_DENSITY_4Gb		7
+#define DDR_DENSITY_8Gb		8
+#define DDR_DENSITY_16Gb	9
+#define DDR_DENSITY_32Gb	10
+
+/* DDR type */
+#define DDR_TYPE_DDR2		1
+#define DDR_TYPE_DDR3		2
+#define DDR_TYPE_LPDDR2_S4	3
+#define DDR_TYPE_LPDDR2_S2	4
+#define DDR_TYPE_LPDDR2_NVM	5
+
+/* DDR IO width */
+#define DDR_IO_WIDTH_4		1
+#define DDR_IO_WIDTH_8		2
+#define DDR_IO_WIDTH_16		3
+#define DDR_IO_WIDTH_32		4
+
+/* Number of Row bits */
+#define R9			9
+#define R10			10
+#define R11			11
+#define R12			12
+#define R13			13
+#define R14			14
+#define R15			15
+#define R16			16
+
+/* Number of Column bits */
+#define C7			7
+#define C8			8
+#define C9			9
+#define C10			10
+#define C11			11
+#define C12			12
+
+/* Number of Banks */
+#define B1			0
+#define B2			1
+#define B4			2
+#define B8			3
+
+/* Refresh rate in nano-seconds */
+#define T_REFI_15_6		15600
+#define T_REFI_7_8		7800
+#define T_REFI_3_9		3900
+
+/* tRFC values */
+#define T_RFC_90		90000
+#define T_RFC_110		110000
+#define T_RFC_130		130000
+#define T_RFC_160		160000
+#define T_RFC_210		210000
+#define T_RFC_300		300000
+#define T_RFC_350		350000
+
+/* Mode register numbers */
+#define DDR_MR0			0
+#define DDR_MR1			1
+#define DDR_MR2			2
+#define DDR_MR3			3
+#define DDR_MR4			4
+#define DDR_MR5			5
+#define DDR_MR6			6
+#define DDR_MR7			7
+#define DDR_MR8			8
+#define DDR_MR9			9
+#define DDR_MR10		10
+#define DDR_MR11		11
+#define DDR_MR16		16
+#define DDR_MR17		17
+#define DDR_MR18		18
+
+/*
+ * LPDDR2 related defines
+ */
+
+/* MR4 register fields */
+#define MR4_SDRAM_REF_RATE_SHIFT			0
+#define MR4_SDRAM_REF_RATE_MASK				7
+#define MR4_TUF_SHIFT					7
+#define MR4_TUF_MASK					(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define NUM_DDR_ADDR_TABLE_ENTRIES			11
+#define NUM_DDR_TIMING_TABLE_ENTRIES			4
+
+/* Structure for DDR addressing info from the JEDEC spec */
+struct lpddr2_addressing {
+	u32 num_banks;
+	u32 tREFI_ns;
+	u32 tRFCab_ps;
+};
+
+/*
+ * Structure for timings from the LPDDR2 datasheet
+ * All parameters are in pico seconds(ps) unless explicitly indicated
+ * with a suffix like tRAS_max_ns below
+ */
+struct lpddr2_timings {
+	u32 max_freq;
+	u32 min_freq;
+	u32 tRPab;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_min;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u32 tCKESR;
+	u32 tDQSCK_max;
+	u32 tDQSCK_max_derated;
+	u32 tFAW;
+	u32 tZQCS;
+	u32 tZQCL;
+	u32 tZQinit;
+	u32 tRAS_max_ns;
+};
+
+/*
+ * Min value for some parameters in terms of number of tCK cycles(nCK)
+ * Please set to zero parameters that are not valid for a given memory
+ * type
+ */
+struct lpddr2_min_tck {
+	u32 tRPab;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRASmin;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u32 tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+extern const struct lpddr2_addressing
+	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES];
+extern const struct lpddr2_timings
+	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
+extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
+#endif /* __ASSEMBLY__ */
+
+#endif /* __LINUX_JEDEC_DDR_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index 028aba9..c5d4f1f 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -291,6 +291,14 @@ config CORDIC
 	  This option provides an implementation of the CORDIC algorithm;
 	  calculations are in fixed point. Module will be called cordic.
 
+config DDR
+	bool "JEDEC DDR data"
+	help
+	  Data from JEDEC specs for DDR SDRAM memories,
+	  particularly the AC timing parameters and addressing
+	  information. This data is useful for drivers handling
+	  DDR SDRAM controllers.
+
 config MPILIB
 	tristate
 	select CLZ_TAB
diff --git a/lib/Makefile b/lib/Makefile
index 18515f0..066d700 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -123,6 +123,9 @@ obj-$(CONFIG_SIGNATURE) += digsig.o
 
 obj-$(CONFIG_CLZ_TAB) += clz_tab.o
 
+obj-$(CONFIG_DDR) += jedec_ddr_data.o
+
+
 hostprogs-y	:= gen_crc32table
 clean-files	:= crc32table.h
 
diff --git a/lib/jedec_ddr_data.c b/lib/jedec_ddr_data.c
new file mode 100644
index 0000000..fc223d6
--- /dev/null
+++ b/lib/jedec_ddr_data.c
@@ -0,0 +1,135 @@
+/*
+ * DDR addressing details and AC timing parameters from JEDEC specs
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <misc/jedec_ddr.h>
+#include <linux/module.h>
+
+/* LPDDR2 addressing details from JESD209-2 section 2.4 */
+const struct lpddr2_addressing
+	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
+	{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
+	{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
+	{B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
+	{B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
+	{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
+	{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
+	{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
+	{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
+	{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
+	{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
+};
+EXPORT_SYMBOL(lpddr2_jedec_addressing_table);
+
+/* LPDDR2 AC timing parameters from JESD209-2 section 12 */
+const struct lpddr2_timings
+	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
+	/* Speed bin 400(200 MHz) */
+	[0] = {
+		.max_freq	= 200000000,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 10000,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 533(266 MHz) */
+	[1] = {
+		.max_freq	= 266666666,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 800(400 MHz) */
+	[2] = {
+		.max_freq	= 400000000,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 1066(533 MHz) */
+	[3] = {
+		.max_freq	= 533333333,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 5620,
+	},
+};
+EXPORT_SYMBOL(lpddr2_jedec_timings);
+
+const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
+	.tRPab		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRASmin	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+EXPORT_SYMBOL(lpddr2_jedec_min_tck);
-- 
1.7.1



From aneesh at ti.com  Thu Mar 15 14:17:34 2012
From: aneesh at ti.com (Aneesh V)
Date: Thu, 15 Mar 2012 23:47:34 +0530
Subject: [PATCH v2 4/7] misc: emif: handle frequency and voltage change events
In-Reply-To: <1331835457-5390-1-git-send-email-aneesh@ti.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
Message-ID: <1331835457-5390-5-git-send-email-aneesh@ti.com>

Change SDRAM timings and other settings as necessary
on voltage and frequency changes. We calculate these
register settings based on data from the device data
sheet and inputs such a frequency, voltage state(stable
or ramping), temperature level etc.

TODO: frequency and voltage change handling needs to
be integrated with clock framework and regulator
framework respectively. This is not done today
due to missing pieces in the kernel.

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v1:
- Added comment in commit log as well as code about
  missing integration part that needs to be done in
  future
- Removed some settings that were relevant only for
  DDR3
- Correction in temperature derated value of tim3
- Added errata i735 and i728  workarounds. As part of
  this we need to now maintain a list of all devices
  in the driver and iterate through them in some cases
- Improved synchronization. Added protection for newly
  identified cases of potential race conditions.
- Minor changes in patch organization. struct members
  needed by this patch now defined here.
---
 drivers/misc/emif.c |  894 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 drivers/misc/emif.h |  130 ++++++++-
 2 files changed, 1020 insertions(+), 4 deletions(-)

diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index f864640..1ca8165 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
@@ -21,6 +21,7 @@
 #include <linux/seq_file.h>
 #include <linux/module.h>
 #include <linux/list.h>
+#include <linux/spinlock.h>
 #include <misc/jedec_ddr.h>
 #include "emif.h"
 
@@ -37,20 +38,595 @@
  * @node:			node in the device list
  * @base:			base address of memory-mapped IO registers.
  * @dev:			device pointer.
+ * @addressing			table with addressing information from the spec
+ * @regs_cache:			An array of 'struct emif_regs' that stores
+ *				calculated register values for different
+ *				frequencies, to avoid re-calculating them on
+ *				each DVFS transition.
+ * @curr_regs:			The set of register values used in the last
+ *				frequency change (i.e. corresponding to the
+ *				frequency in effect at the moment)
  * @plat_data:			Pointer to saved platform data.
  */
 struct emif_data {
 	u8				duplicate;
 	u8				temperature_level;
+	u8				lpmode;
 	struct list_head		node;
+	unsigned long			irq_state;
 	void __iomem			*base;
 	struct device			*dev;
+	const struct lpddr2_addressing	*addressing;
+	struct emif_regs		*regs_cache[EMIF_MAX_NUM_FREQUENCIES];
+	struct emif_regs		*curr_regs;
 	struct emif_platform_data	*plat_data;
 };
 
 static struct emif_data *emif1;
+static spinlock_t	emif_lock;
+static unsigned long	irq_state;
+static u32		t_ck; /* DDR clock period in ps */
 static LIST_HEAD(device_list);
 
+/*
+ * Calculate the period of DDR clock from frequency value
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+	/* Divide 10^12 by frequency to get period in ps */
+	t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
+}
+
+/*
+ * Get the CL from SDRAM_CONFIG register
+ */
+static u32 get_cl(struct emif_data *emif)
+{
+	u32		cl;
+	void __iomem	*base = emif->base;
+
+	cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
+
+	return cl;
+}
+
+static void set_lpmode(struct emif_data *emif, u8 lpmode)
+{
+	u32 temp;
+	void __iomem *base = emif->base;
+
+	temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
+	temp &= ~LP_MODE_MASK;
+	temp |= (lpmode << LP_MODE_SHIFT);
+	writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
+}
+
+static void do_freq_update(void)
+{
+	struct emif_data *emif;
+
+	/*
+	 * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
+	 *
+	 * i728 DESCRIPTION:
+	 * The EMIF automatically puts the SDRAM into self-refresh mode
+	 * after the EMIF has not performed accesses during
+	 * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
+	 * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
+	 * to 0x2. If during a small window the following three events
+	 * occur:
+	 * - The SR_TIMING counter expires
+	 * - And frequency change is requested
+	 * - And OCP access is requested
+	 * Then it causes instable clock on the DDR interface.
+	 *
+	 * WORKAROUND
+	 * To avoid the occurrence of the three events, the workaround
+	 * is to disable the self-refresh when requesting a frequency
+	 * change. Before requesting a frequency change the software must
+	 * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
+	 * frequency change has been done, the software can reprogram
+	 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
+	 */
+	list_for_each_entry(emif, &device_list, node) {
+		if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
+			set_lpmode(emif, EMIF_LP_MODE_DISABLE);
+	}
+
+	/*
+	 * TODO: Do FREQ_UPDATE here when an API
+	 * is available for this as part of the new
+	 * clock framework
+	 */
+
+	list_for_each_entry(emif, &device_list, node) {
+		if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
+			set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
+	}
+}
+
+/* Find addressing table entry based on the device's type and density */
+static const struct lpddr2_addressing *get_addressing_table(
+	const struct ddr_device_info *device_info)
+{
+	u32		index, type, density;
+
+	type = device_info->type;
+	density = device_info->density;
+
+	switch (type) {
+	case DDR_TYPE_LPDDR2_S4:
+		index = density - 1;
+		break;
+	case DDR_TYPE_LPDDR2_S2:
+		switch (density) {
+		case DDR_DENSITY_1Gb:
+		case DDR_DENSITY_2Gb:
+			index = density + 3;
+			break;
+		default:
+			index = density - 1;
+		}
+		break;
+	default:
+		return NULL;
+	}
+
+	return &lpddr2_jedec_addressing_table[index];
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
+		u32 freq)
+{
+	u32				i, min, max, freq_nearest;
+	const struct lpddr2_timings	*timings = NULL;
+	const struct lpddr2_timings	*timings_arr = emif->plat_data->timings;
+	struct				device *dev = emif->dev;
+
+	/* Start with a very high frequency - 1GHz */
+	freq_nearest = 1000000000;
+
+	/*
+	 * Find the timings table such that:
+	 *  1. the frequency range covers the required frequency(safe) AND
+	 *  2. the max_freq is closest to the required frequency(optimal)
+	 */
+	for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
+		max = timings_arr[i].max_freq;
+		min = timings_arr[i].min_freq;
+		if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
+			freq_nearest = max;
+			timings = &timings_arr[i];
+		}
+	}
+
+	if (!timings)
+		dev_err(dev, "%s: couldn't find timings for - %dHz\n",
+			__func__, freq);
+
+	dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
+		__func__, freq, freq_nearest);
+
+	return timings;
+}
+
+static u32 get_sdram_ref_ctrl_shdw(u32 freq,
+		const struct lpddr2_addressing *addressing)
+{
+	u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
+
+	/* Scale down frequency and t_refi to avoid overflow */
+	freq_khz = freq / 1000;
+	t_refi = addressing->tREFI_ns / 100;
+
+	/*
+	 * refresh rate to be set is 'tREFI(in us) * freq in MHz
+	 * division by 10000 to account for change in units
+	 */
+	val = t_refi * freq_khz / 10000;
+	ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
+
+	return ref_ctrl_shdw;
+}
+
+static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,
+		const struct lpddr2_min_tck *min_tck,
+		const struct lpddr2_addressing *addressing)
+{
+	u32 tim1 = 0, val = 0;
+
+	val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
+	tim1 |= val << T_WTR_SHIFT;
+
+	if (addressing->num_banks == B8)
+		val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
+	else
+		val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
+	tim1 |= (val - 1) << T_RRD_SHIFT;
+
+	val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
+	tim1 |= val << T_RC_SHIFT;
+
+	val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
+	tim1 |= (val - 1) << T_RAS_SHIFT;
+
+	val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
+	tim1 |= val << T_WR_SHIFT;
+
+	val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
+	tim1 |= val << T_RCD_SHIFT;
+
+	val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
+	tim1 |= val << T_RP_SHIFT;
+
+	return tim1;
+}
+
+static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,
+		const struct lpddr2_min_tck *min_tck,
+		const struct lpddr2_addressing *addressing)
+{
+	u32 tim1 = 0, val = 0;
+
+	val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
+	tim1 = val << T_WTR_SHIFT;
+
+	/*
+	 * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
+	 * to tFAW for de-rating
+	 */
+	if (addressing->num_banks == B8) {
+		val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
+	} else {
+		val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
+		val = max(min_tck->tRRD, val) - 1;
+	}
+	tim1 |= val << T_RRD_SHIFT;
+
+	val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
+	tim1 |= (val - 1) << T_RC_SHIFT;
+
+	val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
+	val = max(min_tck->tRASmin, val) - 1;
+	tim1 |= val << T_RAS_SHIFT;
+
+	val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
+	tim1 |= val << T_WR_SHIFT;
+
+	val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
+	tim1 |= (val - 1) << T_RCD_SHIFT;
+
+	val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
+	tim1 |= (val - 1) << T_RP_SHIFT;
+
+	return tim1;
+}
+
+static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings,
+		const struct lpddr2_min_tck *min_tck,
+		const struct lpddr2_addressing *addressing,
+		u32 type)
+{
+	u32 tim2 = 0, val = 0;
+
+	val = min_tck->tCKE - 1;
+	tim2 |= val << T_CKE_SHIFT;
+
+	val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
+	tim2 |= val << T_RTP_SHIFT;
+
+	/* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
+	val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
+	tim2 |= val << T_XSNR_SHIFT;
+
+	/* XSRD same as XSNR for LPDDR2 */
+	tim2 |= val << T_XSRD_SHIFT;
+
+	val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
+	tim2 |= val << T_XP_SHIFT;
+
+	return tim2;
+}
+
+static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
+		const struct lpddr2_min_tck *min_tck,
+		const struct lpddr2_addressing *addressing,
+		u32 type, u32 ip_rev, u32 derated)
+{
+	u32 tim3 = 0, val = 0, t_dqsck;
+
+	val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
+	val = val > 0xF ? 0xF : val;
+	tim3 |= val << T_RAS_MAX_SHIFT;
+
+	val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
+	tim3 |= val << T_RFC_SHIFT;
+
+	t_dqsck = (derated == EMIF_DERATED_TIMINGS) ?
+		timings->tDQSCK_max_derated : timings->tDQSCK_max;
+	if (ip_rev == EMIF_4D5)
+		val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
+	else
+		val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
+
+	tim3 |= val << T_TDQSCKMAX_SHIFT;
+
+	val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
+	tim3 |= val << ZQ_ZQCS_SHIFT;
+
+	val = DIV_ROUND_UP(timings->tCKESR, t_ck);
+	val = max(min_tck->tCKESR, val) - 1;
+	tim3 |= val << T_CKESR_SHIFT;
+
+	if (ip_rev == EMIF_4D5) {
+		tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
+
+		val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
+		tim3 |= val << T_PDLL_UL_SHIFT;
+	}
+
+	return tim3;
+}
+
+static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
+{
+	u32 idle = 0, val = 0;
+
+	/*
+	 * Maximum value in normal conditions and increased frequency
+	 * when voltage is ramping
+	 */
+	if (volt_ramp)
+		val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
+	else
+		val = 0x1FF;
+
+	/*
+	 * READ_IDLE_CTRL register in EMIF4D has same offset and fields
+	 * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
+	 */
+	idle |= val << DLL_CALIB_INTERVAL_SHIFT;
+	idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT;
+
+	return idle;
+}
+
+static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp)
+{
+	u32 calib = 0, val = 0;
+
+	if (volt_ramp == DDR_VOLTAGE_RAMPING)
+		val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
+	else
+		val = 0; /* Disabled when voltage is stable */
+
+	calib |= val << DLL_CALIB_INTERVAL_SHIFT;
+	calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT;
+
+	return calib;
+}
+
+static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings,
+	u32 freq, u8 RL)
+{
+	u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
+
+	val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
+	phy |= val << READ_LATENCY_SHIFT_4D;
+
+	if (freq <= 100000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
+	else if (freq <= 200000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
+	else
+		val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
+
+	phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;
+
+	return phy;
+}
+
+static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl)
+{
+	u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay;
+
+	/*
+	 * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
+	 * half-delay is not needed else set half-delay
+	 */
+	if (freq >= 265000000 && freq < 267000000)
+		half_delay = 0;
+	else
+		half_delay = 1;
+
+	phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5;
+	phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS,
+			t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
+
+	return phy;
+}
+
+static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void)
+{
+	u32 fifo_we_slave_ratio;
+
+	fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
+		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
+
+	return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 |
+		fifo_we_slave_ratio << 22;
+}
+
+static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void)
+{
+	u32 fifo_we_slave_ratio;
+
+	fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
+		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
+
+	return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 |
+		fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23;
+}
+
+static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void)
+{
+	u32 fifo_we_slave_ratio;
+
+	fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
+		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
+
+	return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 |
+		fifo_we_slave_ratio << 13;
+}
+
+static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
+{
+	u32 pwr_mgmt_ctrl	= 0, timeout;
+	u32 lpmode		= EMIF_LP_MODE_SELF_REFRESH;
+	u32 timeout_perf	= EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
+	u32 timeout_pwr		= EMIF_LP_MODE_TIMEOUT_POWER;
+	u32 freq_threshold	= EMIF_LP_MODE_FREQ_THRESHOLD;
+
+	struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
+
+	if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
+		lpmode		= cust_cfgs->lpmode;
+		timeout_perf	= cust_cfgs->lpmode_timeout_performance;
+		timeout_pwr	= cust_cfgs->lpmode_timeout_power;
+		freq_threshold  = cust_cfgs->lpmode_freq_threshold;
+	}
+
+	/* Timeout based on DDR frequency */
+	timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
+
+	/* The value to be set in register is "log2(timeout) - 3" */
+	if (timeout < 16) {
+		timeout = 0;
+	} else {
+		timeout = __fls(timeout) - 3;
+		if (timeout & (timeout - 1))
+			timeout++;
+	}
+
+	switch (lpmode) {
+	case EMIF_LP_MODE_CLOCK_STOP:
+		pwr_mgmt_ctrl = (timeout << CS_TIM_SHIFT) |
+					SR_TIM_MASK | PD_TIM_MASK;
+		break;
+	case EMIF_LP_MODE_SELF_REFRESH:
+		/* Workaround for errata i735 */
+		if (timeout < 6)
+			timeout = 6;
+
+		pwr_mgmt_ctrl = (timeout << SR_TIM_SHIFT) |
+					CS_TIM_MASK | PD_TIM_MASK;
+		break;
+	case EMIF_LP_MODE_PWR_DN:
+		pwr_mgmt_ctrl = (timeout << PD_TIM_SHIFT) |
+					CS_TIM_MASK | SR_TIM_MASK;
+		break;
+	case EMIF_LP_MODE_DISABLE:
+	default:
+		pwr_mgmt_ctrl = CS_TIM_MASK |
+					PD_TIM_MASK | SR_TIM_MASK;
+	}
+
+	/* No CS_TIM in EMIF_4D5 */
+	if (ip_rev == EMIF_4D5)
+		pwr_mgmt_ctrl &= ~CS_TIM_MASK;
+
+	pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
+
+	return pwr_mgmt_ctrl;
+}
+
+/*
+ * Program EMIF shadow registers that are not dependent on temperature
+ * or voltage
+ */
+static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
+{
+	void __iomem	*base = emif->base;
+
+	writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
+	writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
+
+	/* Settings specific for EMIF4D5 */
+	if (emif->plat_data->ip_rev != EMIF_4D5)
+		return;
+	writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
+	writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
+	writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
+}
+
+/*
+ * When voltage ramps dll calibration and forced read idle should
+ * happen more often
+ */
+static void setup_volt_sensitive_regs(struct emif_data *emif,
+		struct emif_regs *regs, u32 volt_state)
+{
+	u32		calib_ctrl;
+	void __iomem	*base = emif->base;
+
+	/*
+	 * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
+	 * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
+	 * is an alias of the respective read_idle_ctrl_shdw_* (members of
+	 * a union). So, the below code takes care of both cases
+	 */
+	if (volt_state == DDR_VOLTAGE_RAMPING)
+		calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp;
+	else
+		calib_ctrl = regs->dll_calib_ctrl_shdw_normal;
+
+	writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
+}
+
+/*
+ * setup_temperature_sensitive_regs() - set the timings for temperature
+ * sensitive registers. This happens once at initialisation time based
+ * on the temperature at boot time and subsequently based on the temperature
+ * alert interrupt. Temperature alert can happen when the temperature
+ * increases or drops. So this function can have the effect of either
+ * derating the timings or going back to nominal values.
+ */
+static void setup_temperature_sensitive_regs(struct emif_data *emif,
+		struct emif_regs *regs)
+{
+	u32		tim1, tim3, ref_ctrl, type;
+	void __iomem	*base = emif->base;
+	u32		temperature;
+
+	type = emif->plat_data->device_info->type;
+
+	tim1 = regs->sdram_tim1_shdw;
+	tim3 = regs->sdram_tim3_shdw;
+	ref_ctrl = regs->ref_ctrl_shdw;
+
+	/* No de-rating for non-lpddr2 devices */
+	if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
+		goto out;
+
+	temperature = emif->temperature_level;
+	if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
+		ref_ctrl = regs->ref_ctrl_shdw_derated;
+	} else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
+		tim1 = regs->sdram_tim1_shdw_derated;
+		tim3 = regs->sdram_tim3_shdw_derated;
+		ref_ctrl = regs->ref_ctrl_shdw_derated;
+	}
+
+out:
+	writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
+	writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
+	writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
+}
+
 static void get_default_timings(struct emif_data *emif)
 {
 	struct emif_platform_data *pd = emif->plat_data;
@@ -234,10 +810,8 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 		goto error;
 	}
 
-	if (!emif1)
-		emif1 = emif;
-
 	list_add(&emif->node, &device_list);
+	emif->addressing = get_addressing_table(emif->plat_data->device_info);
 
 	/* Save pointers to each other in emif and device structures */
 	emif->dev = &pdev->dev;
@@ -257,6 +831,18 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 		goto error;
 	}
 
+	/* One-time actions taken on probing the first device */
+	if (!emif1) {
+		emif1 = emif;
+		spin_lock_init(&emif_lock);
+
+		/*
+		 * TODO: register notifiers for frequency and voltage
+		 * change here once the respective frameworks are
+		 * available
+		 */
+	}
+
 	dev_info(&pdev->dev, "%s: device configured with addr = %p\n",
 		__func__, emif->base);
 
@@ -265,6 +851,308 @@ error:
 	return -ENODEV;
 }
 
+static int get_emif_reg_values(struct emif_data *emif, u32 freq,
+		struct emif_regs *regs)
+{
+	u32				cs1_used, ip_rev, phy_type;
+	u32				cl, type;
+	const struct lpddr2_timings	*timings;
+	const struct lpddr2_min_tck	*min_tck;
+	const struct ddr_device_info	*device_info;
+	const struct lpddr2_addressing	*addressing;
+	struct emif_data		*emif_for_calc;
+	struct device			*dev;
+	const struct emif_custom_configs *custom_configs;
+
+	dev = emif->dev;
+	/*
+	 * If the devices on this EMIF instance is duplicate of EMIF1,
+	 * use EMIF1 details for the calculation
+	 */
+	emif_for_calc	= emif->duplicate ? emif1 : emif;
+	timings		= get_timings_table(emif_for_calc, freq);
+	addressing	= emif_for_calc->addressing;
+	if (!timings || !addressing) {
+		dev_err(dev, "%s: not enough data available for %dHz",
+			__func__, freq);
+		return -1;
+	}
+
+	device_info	= emif_for_calc->plat_data->device_info;
+	type		= device_info->type;
+	cs1_used	= device_info->cs1_used;
+	ip_rev		= emif_for_calc->plat_data->ip_rev;
+	phy_type	= emif_for_calc->plat_data->phy_type;
+
+	min_tck		= emif_for_calc->plat_data->min_tck;
+	custom_configs	= emif_for_calc->plat_data->custom_configs;
+
+	set_ddr_clk_period(freq);
+
+	regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing);
+	regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck,
+			addressing);
+	regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck,
+			addressing, type);
+	regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck,
+		addressing, type, ip_rev, EMIF_NORMAL_TIMINGS);
+
+	cl = get_cl(emif);
+
+	if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) {
+		regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
+			timings, freq, cl);
+	} else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) {
+		regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
+		regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5();
+		regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5();
+		regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5();
+	} else {
+		return -1;
+	}
+
+	/* Only timeout values in pwr_mgmt_ctrl_shdw register */
+	regs->pwr_mgmt_ctrl_shdw =
+		get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) &
+		(CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK);
+
+	if (ip_rev & EMIF_4D) {
+		regs->read_idle_ctrl_shdw_normal =
+			get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE);
+
+		regs->read_idle_ctrl_shdw_volt_ramp =
+			get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING);
+	} else if (ip_rev & EMIF_4D5) {
+		regs->dll_calib_ctrl_shdw_normal =
+			get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE);
+
+		regs->dll_calib_ctrl_shdw_volt_ramp =
+			get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING);
+	}
+
+	if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
+		regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4,
+			addressing);
+
+		regs->sdram_tim1_shdw_derated =
+			get_sdram_tim_1_shdw_derated(timings, min_tck,
+				addressing);
+
+		regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings,
+			min_tck, addressing, type, ip_rev,
+			EMIF_DERATED_TIMINGS);
+	}
+
+	regs->freq = freq;
+
+	return 0;
+}
+
+/*
+ * get_regs() - gets the cached emif_regs structure for a given EMIF instance
+ * given frequency(freq):
+ *
+ * As an optimisation, every EMIF instance other than EMIF1 shares the
+ * register cache with EMIF1 if the devices connected on this instance
+ * are same as that on EMIF1(indicated by the duplicate flag)
+ *
+ * If we do not have an entry corresponding to the frequency given, we
+ * allocate a new entry and calculate the values
+ *
+ * Upon finding the right reg dump, save it in curr_regs. It can be
+ * directly used for thermal de-rating and voltage ramping changes.
+ */
+static struct emif_regs *get_regs(struct emif_data *emif, u32 freq)
+{
+	int			i;
+	struct emif_regs	**regs_cache;
+	struct emif_regs	*regs = NULL;
+	struct device		*dev;
+
+	dev = emif->dev;
+	if (emif->curr_regs && emif->curr_regs->freq == freq) {
+		dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq);
+		return emif->curr_regs;
+	}
+
+	if (emif->duplicate)
+		regs_cache = emif1->regs_cache;
+	else
+		regs_cache = emif->regs_cache;
+
+	for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
+		if (regs_cache[i]->freq == freq) {
+			regs = regs_cache[i];
+			dev_dbg(dev,
+				"%s: reg dump found in reg cache for %u Hz\n",
+				__func__, freq);
+			break;
+		}
+	}
+
+	/*
+	 * If we don't have an entry for this frequency in the cache create one
+	 * and calculate the values
+	 */
+	if (!regs) {
+		regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC);
+		if (!regs)
+			return NULL;
+
+		if (get_emif_reg_values(emif, freq, regs)) {
+			devm_kfree(emif->dev, regs);
+			return NULL;
+		}
+
+		/*
+		 * Now look for an un-used entry in the cache and save the
+		 * newly created struct. If there are no free entries
+		 * over-write the last entry
+		 */
+		for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++)
+			;
+
+		if (i >= EMIF_MAX_NUM_FREQUENCIES) {
+			dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n",
+				__func__);
+			i = EMIF_MAX_NUM_FREQUENCIES - 1;
+			devm_kfree(emif->dev, regs_cache[i]);
+		}
+		regs_cache[i] = regs;
+	}
+
+	return regs;
+}
+
+static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state)
+{
+	dev_dbg(emif->dev, "%s: voltage notification : %d", __func__,
+		volt_state);
+
+	if (!emif->curr_regs) {
+		dev_err(emif->dev,
+			"%s: volt-notify before registers are ready: %d\n",
+			__func__, volt_state);
+		return;
+	}
+
+	setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state);
+}
+
+/*
+ * TODO: voltage notify handling should be hooked up to
+ * regulator framework as soon as the necessary support
+ * is available in mainline kernel. This function is un-used
+ * right now.
+ */
+static void __attribute__((unused)) volt_notify_handling(u32 volt_state)
+{
+	struct emif_data *emif;
+
+	spin_lock_irqsave(&emif_lock, irq_state);
+
+	list_for_each_entry(emif, &device_list, node)
+		do_volt_notify_handling(emif, volt_state);
+	do_freq_update();
+
+	spin_unlock_irqrestore(&emif_lock, irq_state);
+}
+
+static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq)
+{
+	struct emif_regs *regs;
+
+	regs = get_regs(emif, new_freq);
+	if (!regs)
+		return;
+
+	emif->curr_regs = regs;
+
+	/*
+	 * Update the shadow registers:
+	 * Temperature and voltage-ramp sensitive settings are also configured
+	 * in terms of DDR cycles. So, we need to update them too when there
+	 * is a freq change
+	 */
+	dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz",
+		__func__, new_freq);
+	setup_registers(emif, regs);
+	setup_temperature_sensitive_regs(emif, regs);
+	setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE);
+
+	/*
+	 * Part of workaround for errata i728. See do_freq_update()
+	 * for more details
+	 */
+	if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
+		set_lpmode(emif, EMIF_LP_MODE_DISABLE);
+}
+
+/*
+ * TODO: frequency notify handling should be hooked up to
+ * clock framework as soon as the necessary support is
+ * available in mainline kernel. This function is un-used
+ * right now.
+ */
+static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq)
+{
+	struct emif_data *emif;
+
+	/*
+	 * NOTE: we are taking the spin-lock here and releases it
+	 * only in post-notifier. This doesn't look good and
+	 * Sparse complains about it, but this seems to be
+	 * un-avoidable. We need to lock a sequence of events
+	 * that is split between EMIF and clock framework.
+	 *
+	 * 1. EMIF driver updates EMIF timings in shadow registers in the
+	 *    frequency pre-notify callback from clock framework
+	 * 2. clock framework sets up the registers for the new frequency
+	 * 3. clock framework initiates a hw-sequence that updates
+	 *    the frequency EMIF timings synchronously.
+	 *
+	 * All these 3 steps should be performed as an atomic operation
+	 * vis-a-vis similar sequence in the EMIF interrupt handler
+	 * for temperature events. Otherwise, there could be race
+	 * conditions that could result in incorrect EMIF timings for
+	 * a given frequency
+	 */
+	spin_lock_irqsave(&emif_lock, irq_state);
+
+	list_for_each_entry(emif, &device_list, node)
+		do_freq_pre_notify_handling(emif, new_freq);
+}
+
+static void do_freq_post_notify_handling(struct emif_data *emif)
+{
+	/*
+	 * Part of workaround for errata i728. See do_freq_update()
+	 * for more details
+	 */
+	if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
+		set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
+}
+
+/*
+ * TODO: frequency notify handling should be hooked up to
+ * clock framework as soon as the necessary support is
+ * available in mainline kernel. This function is un-used
+ * right now.
+ */
+static void __attribute__((unused)) freq_post_notify_handling(void)
+{
+	struct emif_data *emif;
+
+	list_for_each_entry(emif, &device_list, node)
+		do_freq_post_notify_handling(emif);
+
+	/*
+	 * Lock is done in pre-notify handler. See freq_pre_notify_handling()
+	 * for more details
+	 */
+	spin_unlock_irqrestore(&emif_lock, irq_state);
+}
+
 static struct platform_driver emif_driver = {
 	.driver = {
 		.name = "emif",
diff --git a/drivers/misc/emif.h b/drivers/misc/emif.h
index 692b2a8..bfe08ba 100644
--- a/drivers/misc/emif.h
+++ b/drivers/misc/emif.h
@@ -19,6 +19,103 @@
  */
 #define EMIF_MAX_NUM_FREQUENCIES			6
 
+/* State of the core voltage */
+#define DDR_VOLTAGE_STABLE				0
+#define DDR_VOLTAGE_RAMPING				1
+
+/* Defines for timing De-rating */
+#define EMIF_NORMAL_TIMINGS				0
+#define EMIF_DERATED_TIMINGS				1
+
+/* Length of the forced read idle period in terms of cycles */
+#define EMIF_READ_IDLE_LEN_VAL				5
+
+/*
+ * forced read idle interval to be used when voltage
+ * is changed as part of DVFS/DPS - 1ms
+ */
+#define READ_IDLE_INTERVAL_DVFS				(1*1000000)
+
+/*
+ * Forced read idle interval to be used when voltage is stable
+ * 50us - or maximum value will do
+ */
+#define READ_IDLE_INTERVAL_NORMAL			(50*1000000)
+
+/* DLL calibration interval when voltage is NOT stable - 1us */
+#define DLL_CALIB_INTERVAL_DVFS				(1*1000000)
+
+#define DLL_CALIB_ACK_WAIT_VAL				5
+
+/* Interval between ZQCS commands - hw team recommended value */
+#define EMIF_ZQCS_INTERVAL_US				(50*1000)
+/* Enable ZQ Calibration on exiting Self-refresh */
+#define ZQ_SFEXITEN_ENABLE				1
+/*
+ * ZQ Calibration simultaneously on both chip-selects:
+ * Needs one calibration resistor per CS
+ */
+#define	ZQ_DUALCALEN_DISABLE				0
+#define	ZQ_DUALCALEN_ENABLE				1
+
+#define T_ZQCS_DEFAULT_NS				90
+#define T_ZQCL_DEFAULT_NS				360
+#define T_ZQINIT_DEFAULT_NS				1000
+
+/* DPD_EN */
+#define DPD_DISABLE					0
+#define DPD_ENABLE					1
+
+/*
+ * Default values for the low-power entry to be used if not provided by user.
+ * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512
+ * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz
+ */
+#define EMIF_LP_MODE_TIMEOUT_PERFORMANCE		2048
+#define EMIF_LP_MODE_TIMEOUT_POWER			512
+#define EMIF_LP_MODE_FREQ_THRESHOLD			400000000
+
+/* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY		0x049FF000
+#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY	0x41
+#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY	0x80
+#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF
+
+/* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY		0x0E084200
+#define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS	10000
+
+/* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */
+#define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS		360
+
+#define EMIF_T_CSTA					3
+#define EMIF_T_PDLL_UL					128
+
+/* External PHY control registers magic values */
+#define EMIF_EXT_PHY_CTRL_1_VAL				0x04020080
+#define EMIF_EXT_PHY_CTRL_5_VAL				0x04010040
+#define EMIF_EXT_PHY_CTRL_6_VAL				0x01004010
+#define EMIF_EXT_PHY_CTRL_7_VAL				0x00001004
+#define EMIF_EXT_PHY_CTRL_8_VAL				0x04010040
+#define EMIF_EXT_PHY_CTRL_9_VAL				0x01004010
+#define EMIF_EXT_PHY_CTRL_10_VAL			0x00001004
+#define EMIF_EXT_PHY_CTRL_11_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_12_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_13_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_14_VAL			0x80080080
+#define EMIF_EXT_PHY_CTRL_15_VAL			0x00800800
+#define EMIF_EXT_PHY_CTRL_16_VAL			0x08102040
+#define EMIF_EXT_PHY_CTRL_17_VAL			0x00000001
+#define EMIF_EXT_PHY_CTRL_18_VAL			0x540A8150
+#define EMIF_EXT_PHY_CTRL_19_VAL			0xA81502A0
+#define EMIF_EXT_PHY_CTRL_20_VAL			0x002A0540
+#define EMIF_EXT_PHY_CTRL_21_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_22_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_23_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_24_VAL			0x00000077
+
+#define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS	1200
+
 /* Registers offset */
 #define EMIF_MODULE_ID_AND_REVISION			0x0000
 #define EMIF_STATUS					0x0004
@@ -458,4 +555,35 @@
 #define READ_LATENCY_SHDW_SHIFT				0
 #define READ_LATENCY_SHDW_MASK				(0x1f << 0)
 
-#endif
+#ifndef __ASSEMBLY__
+/*
+ * Structure containing shadow of important registers in EMIF
+ * The calculation function fills in this structure to be later used for
+ * initialisation and DVFS
+ */
+struct emif_regs {
+	u32 freq;
+	u32 ref_ctrl_shdw;
+	u32 ref_ctrl_shdw_derated;
+	u32 sdram_tim1_shdw;
+	u32 sdram_tim1_shdw_derated;
+	u32 sdram_tim2_shdw;
+	u32 sdram_tim3_shdw;
+	u32 sdram_tim3_shdw_derated;
+	u32 pwr_mgmt_ctrl_shdw;
+	union {
+		u32 read_idle_ctrl_shdw_normal;
+		u32 dll_calib_ctrl_shdw_normal;
+	};
+	union {
+		u32 read_idle_ctrl_shdw_volt_ramp;
+		u32 dll_calib_ctrl_shdw_volt_ramp;
+	};
+
+	u32 phy_ctrl_1_shdw;
+	u32 ext_phy_ctrl_2_shdw;
+	u32 ext_phy_ctrl_3_shdw;
+	u32 ext_phy_ctrl_4_shdw;
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __EMIF_H */
-- 
1.7.1



From aneesh at ti.com  Thu Mar 15 14:34:03 2012
From: aneesh at ti.com (Aneesh V)
Date: Fri, 16 Mar 2012 00:04:03 +0530
Subject: [PATCH v2 0/4] dt: device tree support for TI EMIF driver
Message-ID: <1331836447-7584-1-git-send-email-aneesh@ti.com>

This series adds device tree support for TI EMIF SDRAM controller
driver. For this, a binding has been added for representing AC timing
parameters and other details of LPDDR2 memories.

This series depends v2 of my series for adding EMIF driver [1]

[1] http://marc.info/?l=linux-omap&m=133183554007498&w=2

Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Grant Likely <grant.likely at secretlab.ca>

Aneesh V (4):
  dt: device tree bindings for LPDDR2 memories
  dt: emif: device tree bindings for TI's EMIF sdram controller
  arm: dts: EMIF and LPDDR2 device tree data for OMAP4 boards
  misc: emif: add device tree support to emif driver

 .../devicetree/bindings/lpddr2/lpddr2-timings.txt  |   52 ++++
 .../devicetree/bindings/lpddr2/lpddr2.txt          |  102 +++++++
 .../bindings/memory-controllers/ti/emif.txt        |   55 ++++
 arch/arm/boot/dts/elpida_ecb240abacn.dtsi          |   67 +++++
 arch/arm/boot/dts/omap4-panda.dts                  |   13 +
 arch/arm/boot/dts/omap4-sdp.dts                    |   13 +
 arch/arm/boot/dts/omap4.dtsi                       |   18 ++
 drivers/misc/emif.c                                |  285 +++++++++++++++++++-
 8 files changed, 604 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
 create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
 create mode 100644 arch/arm/boot/dts/elpida_ecb240abacn.dtsi



From aneesh at ti.com  Thu Mar 15 14:34:04 2012
From: aneesh at ti.com (Aneesh V)
Date: Fri, 16 Mar 2012 00:04:04 +0530
Subject: [PATCH v2 1/4] dt: device tree bindings for LPDDR2 memories
In-Reply-To: <1331836447-7584-1-git-send-email-aneesh@ti.com>
References: <1331836447-7584-1-git-send-email-aneesh@ti.com>
Message-ID: <1331836447-7584-2-git-send-email-aneesh@ti.com>

device tree bindings for LPDDR2 SDRAM memories compliant
to JESD209-2 standard.

The 'lpddr2' binding in-turn uses another binding 'lpddr2-timings'
for specifying the AC timing parameters of the memory device at
different speed-bins.

Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v1:
- Removed two DDR3 only timing parameters that were
  inadvertently added in the binding
---
 .../devicetree/bindings/lpddr2/lpddr2-timings.txt  |   52 ++++++++++
 .../devicetree/bindings/lpddr2/lpddr2.txt          |  102 ++++++++++++++++++++
 2 files changed, 154 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
 create mode 100644 Documentation/devicetree/bindings/lpddr2/lpddr2.txt

diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
new file mode 100644
index 0000000..a48f698
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
@@ -0,0 +1,52 @@
+* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
+
+Required properties:
+- compatible : Should be "jedec,lpddr2-timings"
+- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
+- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
+
+Optional properties:
+
+The following properties represent AC timing parameters from the memory
+data-sheet of the device for a given speed-bin. All these properties are
+of type <u32> and the default unit is ps (pico seconds). Parameters with
+a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
+- tRCD
+- tWR
+- tRAS-min
+- tRRD
+- tWTR
+- tXP
+- tRTP
+- tDQSCK-max
+- tFAW
+- tZQCS
+- tZQinit
+- tRPab
+- tZQCL
+- tCKESR
+- tRAS-max-ns
+- tDQSCK-max-derated
+
+Example:
+
+timings_elpida_ECB240ABACN_400mhz: lpddr2-timings at 0 {
+	compatible 	= "jedec,lpddr2-timings";
+	min-freq	= <10000000>;
+	max-freq	= <400000000>;
+	tRPab		= <21000>;
+	tRCD		= <18000>;
+	tWR		= <15000>;
+	tRAS-min	= <42000>;
+	tRRD		= <10000>;
+	tWTR		= <7500>;
+	tXP		= <7500>;
+	tRTP		= <7500>;
+	tCKESR		= <15000>;
+	tDQSCK-max 	= <5500>;
+	tFAW		= <50000>;
+	tZQCS		= <90000>;
+	tZQCL		= <360000>;
+	tZQinit		= <1000000>;
+	tRAS-max-ns	= <70000>;
+};
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
new file mode 100644
index 0000000..a2ab203
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
@@ -0,0 +1,102 @@
+* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
+
+Required properties:
+- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
+  "jedec,lpddr2-s4"
+
+  "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
+
+  "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
+
+  "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
+
+- density  : <u32> representing density in Mb (Mega bits)
+
+- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
+
+Optional properties:
+
+The following optional properties represent the minimum value of some AC
+timing parameters of the DDR device in terms of number of clock cycles.
+These values shall be obtained from the device data-sheet.
+- tRRD-min-tck
+- tWTR-min-tck
+- tXP-min-tck
+- tRTP-min-tck
+- tCKE-min-tck
+- tRPab-min-tck
+- tRCD-min-tck
+- tWR-min-tck
+- tRASmin-min-tck
+- tCKESR-min-tck
+- tFAW-min-tck
+
+Child nodes:
+- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
+  "lpddr2-timings" provides AC timing parameters of the device for
+  a given speed-bin. The user may provide the timings for as many
+  speed-bins as is required. Please see Documentation/devicetree/
+  bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
+
+Example:
+
+elpida_ECB240ABACN : lpddr2 {
+	compatible 	= "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+	density		= <2048>;
+	io-width	= <32>;
+
+	tRPab-min-tck	= <3>;
+	tRCD-min-tck	= <3>;
+	tWR-min-tck	= <3>;
+	tRASmin-min-tck	= <3>;
+	tRRD-min-tck	= <2>;
+	tWTR-min-tck	= <2>;
+	tXP-min-tck	= <2>;
+	tRTP-min-tck	= <2>;
+	tCKE-min-tck	= <3>;
+	tCKESR-min-tck	= <3>;
+	tFAW-min-tck	= <8>;
+
+	timings_elpida_ECB240ABACN_400mhz: lpddr2-timings at 0 {
+		compatible 	= "jedec,lpddr2-timings";
+		min-freq	= <10000000>;
+		max-freq	= <400000000>;
+		tRPab		= <21000>;
+		tRCD		= <18000>;
+		tWR		= <15000>;
+		tRAS-min	= <42000>;
+		tRRD		= <10000>;
+		tWTR		= <7500>;
+		tXP		= <7500>;
+		tRTP		= <7500>;
+		tCKESR		= <15000>;
+		tDQSCK-max 	= <5500>;
+		tFAW		= <50000>;
+		tZQCS		= <90000>;
+		tZQCL		= <360000>;
+		tZQinit		= <1000000>;
+		tRAS-max-ns	= <70000>;
+	};
+
+	timings_elpida_ECB240ABACN_200mhz: lpddr2-timings at 1 {
+		compatible 	= "jedec,lpddr2-timings";
+		min-freq	= <10000000>;
+		max-freq	= <200000000>;
+		tRPab		= <21000>;
+		tRCD		= <18000>;
+		tWR		= <15000>;
+		tRAS-min	= <42000>;
+		tRRD		= <10000>;
+		tWTR		= <10000>;
+		tXP		= <7500>;
+		tRTP		= <7500>;
+		tCKESR		= <15000>;
+		tDQSCK-max 	= <5500>;
+		tFAW		= <50000>;
+		tZQCS		= <90000>;
+		tZQCL		= <360000>;
+		tZQinit		= <1000000>;
+		tRAS-max-ns	= <70000>;
+	};
+
+}
-- 
1.7.1



From aneesh at ti.com  Thu Mar 15 14:34:05 2012
From: aneesh at ti.com (Aneesh V)
Date: Fri, 16 Mar 2012 00:04:05 +0530
Subject: [PATCH v2 2/4] dt: emif: device tree bindings for TI's EMIF sdram
 controller
In-Reply-To: <1331836447-7584-1-git-send-email-aneesh@ti.com>
References: <1331836447-7584-1-git-send-email-aneesh@ti.com>
Message-ID: <1331836447-7584-3-git-send-email-aneesh@ti.com>

EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
of the EMIF IP and memory parts attached to it.

Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
---
 .../bindings/memory-controllers/ti/emif.txt        |   55 ++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/emif.txt

diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
new file mode 100644
index 0000000..938f8e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -0,0 +1,55 @@
+* EMIF family of TI SDRAM controllers
+
+EMIF - External Memory Interface - is an SDRAM controller used in
+TI SoCs. EMIF supports, based on the IP revision, one or more of
+DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
+of the EMIF IP and memory parts attached to it.
+
+Required properties:
+- compatible	: Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
+  is the IP revision of the specific EMIF instance.
+
+- phy-type	: <u32> indicating the DDR phy type. Following are the
+  allowed values
+  <1>	: Attila PHY
+  <2>	: Intelli PHY
+
+- device-handle	: phandle to a "lpddr2" node representing the memory part
+
+- ti,hwmods	: For TI hwmods processing and omap device creation
+  the value shall be "emif<n>" where <n> is the number of the EMIF
+  instance with base 1.
+
+Optional properties:
+- cs1-used		: Have this property if CS1 of this EMIF
+  instance has a memory part attached to it. If there is a memory
+  part attached to CS1, it should be the same type as the one on CS0,
+  so there is no need to give the details of this memory part.
+
+- cal-resistor-per-cs	: Have this property if the board has one
+  calibration resistor per chip-select.
+
+- hw-caps-read-idle-ctrl: Have this property if the controller
+  supports read idle window programming
+
+- hw-caps-dll-calib-ctrl: Have this property if the controller
+  supports dll calibration control
+
+- hw-caps-ll-interface	: Have this property if the controller
+  has a low latency interface and corresponding interrupt events
+
+- hw-caps-temp-alert	: Have this property if the controller
+  has capability for generating SDRAM temperature alerts
+
+Example:
+
+emif1: emif at 0x4c000000 {
+	compatible	= "ti,emif-4d";
+	ti,hwmods	= "emif2";
+	phy-type	= <1>;
+	device-handle	= <&elpida_ECB240ABACN>;
+	cs1-used;
+	hw-caps-read-idle-ctrl;
+	hw-caps-ll-interface;
+	hw-caps-temp-alert;
+};
-- 
1.7.1



From aneesh at ti.com  Thu Mar 15 14:34:06 2012
From: aneesh at ti.com (Aneesh V)
Date: Fri, 16 Mar 2012 00:04:06 +0530
Subject: [PATCH v2 3/4] arm: dts: EMIF and LPDDR2 device tree data for OMAP4
 boards
In-Reply-To: <1331836447-7584-1-git-send-email-aneesh@ti.com>
References: <1331836447-7584-1-git-send-email-aneesh@ti.com>
Message-ID: <1331836447-7584-4-git-send-email-aneesh@ti.com>

Device tree data for the EMIF sdram controllers in OMAP4
and LPDDR2 memory devices attached to OMAP4 boards.

Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v1:
- Removed DDR3 only parameters from
  elpida_ecb240abacn.dtsi
---
 arch/arm/boot/dts/elpida_ecb240abacn.dtsi |   67 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/omap4-panda.dts         |   13 ++++++
 arch/arm/boot/dts/omap4-sdp.dts           |   13 ++++++
 arch/arm/boot/dts/omap4.dtsi              |   18 ++++++++
 4 files changed, 111 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/elpida_ecb240abacn.dtsi

diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
new file mode 100644
index 0000000..34b9f72
--- /dev/null
+++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Common devices used in different OMAP boards
+ */
+
+/ {
+	elpida_ECB240ABACN: lpddr2 {
+		compatible 	= "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+		density		= <2048>;
+		io-width	= <32>;
+
+		tRPab-min-tck	= <3>;
+		tRCD-min-tck	= <3>;
+		tWR-min-tck	= <3>;
+		tRASmin-min-tck	= <3>;
+		tRRD-min-tck	= <2>;
+		tWTR-min-tck	= <2>;
+		tXP-min-tck	= <2>;
+		tRTP-min-tck	= <2>;
+		tCKE-min-tck	= <3>;
+		tCKESR-min-tck	= <3>;
+		tFAW-min-tck	= <8>;
+
+		timings_elpida_ECB240ABACN_400mhz: lpddr2-timings at 0 {
+			compatible	= "jedec,lpddr2-timings";
+			min-freq	= <10000000>;
+			max-freq	= <400000000>;
+			tRPab		= <21000>;
+			tRCD		= <18000>;
+			tWR		= <15000>;
+			tRAS-min	= <42000>;
+			tRRD		= <10000>;
+			tWTR		= <7500>;
+			tXP		= <7500>;
+			tRTP		= <7500>;
+			tCKESR		= <15000>;
+			tDQSCK-max 	= <5500>;
+			tFAW		= <50000>;
+			tZQCS		= <90000>;
+			tZQCL		= <360000>;
+			tZQinit		= <1000000>;
+			tRAS-max-ns	= <70000>;
+			tDQSCK-max-derated = <6000>;
+		};
+
+		timings_elpida_ECB240ABACN_200mhz: lpddr2-timings at 1 {
+			compatible	= "jedec,lpddr2-timings";
+			min-freq	= <10000000>;
+			max-freq	= <200000000>;
+			tRPab		= <21000>;
+			tRCD		= <18000>;
+			tWR		= <15000>;
+			tRAS-min	= <42000>;
+			tRRD		= <10000>;
+			tWTR		= <10000>;
+			tXP		= <7500>;
+			tRTP		= <7500>;
+			tCKESR		= <15000>;
+			tDQSCK-max 	= <5500>;
+			tFAW		= <50000>;
+			tZQCS		= <90000>;
+			tZQCL		= <360000>;
+			tZQinit		= <1000000>;
+			tRAS-max-ns	= <70000>;
+			tDQSCK-max-derated = <6000>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9755ad5..f548523 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 /include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 PandaBoard";
@@ -17,4 +18,16 @@
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
+
+	ocp {
+		emif1: emif at 0x4c000000 {
+			cs1-used;
+			device-handle = <&elpida_ECB240ABACN>;
+		};
+
+		emif2: emif at 0x4d000000 {
+			cs1-used;
+			device-handle = <&elpida_ECB240ABACN>;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 63c6b2b..6dc08bc 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 /include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
 
 / {
 	model = "TI OMAP4 SDP board";
@@ -17,4 +18,16 @@
 		device_type = "memory";
 		reg = <0x80000000 0x40000000>; /* 1 GB */
 	};
+
+	ocp {
+		emif1: emif at 0x4c000000 {
+			cs1-used;
+			device-handle = <&elpida_ECB240ABACN>;
+		};
+
+		emif2: emif at 0x4d000000 {
+			cs1-used;
+			device-handle = <&elpida_ECB240ABACN>;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 70a44f6..fe3664a 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -127,5 +127,23 @@
 			ti,hwmods = "uart4";
 			clock-frequency = <48000000>;
 		};
+
+		emif1: emif at 0x4c000000 {
+			compatible	= "ti,emif-4d";
+			ti,hwmods	= "emif1";
+			phy-type	= <1>;
+			hw-caps-read-idle-ctrl;
+			hw-caps-ll-interface;
+			hw-caps-temp-alert;
+		};
+
+		emif2: emif at 0x4d000000 {
+			compatible	= "ti,emif-4d";
+			ti,hwmods	= "emif2";
+			phy-type	= <1>;
+			hw-caps-read-idle-ctrl;
+			hw-caps-ll-interface;
+			hw-caps-temp-alert;
+		};
 	};
 };
-- 
1.7.1



From aneesh at ti.com  Thu Mar 15 14:34:07 2012
From: aneesh at ti.com (Aneesh V)
Date: Fri, 16 Mar 2012 00:04:07 +0530
Subject: [PATCH v2 4/4] misc: emif: add device tree support to emif driver
In-Reply-To: <1331836447-7584-1-git-send-email-aneesh@ti.com>
References: <1331836447-7584-1-git-send-email-aneesh@ti.com>
Message-ID: <1331836447-7584-5-git-send-email-aneesh@ti.com>

Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v2:
- Addressed comments from Grant Likely:
  Converted occurences of __init to __init_or_module
  Removed un-necessary instances of #ifdef CONFIG_OF
- Rebased to v2 of EMIF driver series

v1:
- Rebased to the latest version of EMIF series
- Replace kzalloc()/kfree() with devm_* variants
---
 drivers/misc/emif.c |  285 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 284 insertions(+), 1 deletions(-)

diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index 6d2f776..75f21d2 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/module.h>
@@ -49,6 +50,7 @@
  *				frequency in effect at the moment)
  * @plat_data:			Pointer to saved platform data.
  * @debugfs_root:		dentry to the root folder for EMIF in debugfs
+ * @np_ddr:			Pointer to ddr device tree node
  */
 struct emif_data {
 	u8				duplicate;
@@ -63,6 +65,7 @@ struct emif_data {
 	struct emif_regs		*curr_regs;
 	struct emif_platform_data	*plat_data;
 	struct dentry			*debugfs_root;
+	struct device_node		*np_ddr;
 };
 
 static struct emif_data *emif1;
@@ -1148,6 +1151,270 @@ static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
 	return valid;
 }
 
+#if defined(CONFIG_OF)
+static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
+		struct emif_data *emif)
+{
+	struct emif_custom_configs	*cust_cfgs = NULL;
+	int				len;
+	const int			*lpmode, *poll_intvl;
+
+	lpmode = of_get_property(np_emif, "low-power-mode", &len);
+	poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
+
+	if (lpmode || poll_intvl)
+		cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
+			GFP_KERNEL);
+
+	if (!cust_cfgs)
+		return;
+
+	if (lpmode) {
+		cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
+		cust_cfgs->lpmode = *lpmode;
+		of_property_read_u32(np_emif,
+				"low-power-mode-timeout-performance",
+				&cust_cfgs->lpmode_timeout_performance);
+		of_property_read_u32(np_emif,
+				"low-power-mode-timeout-power",
+				&cust_cfgs->lpmode_timeout_power);
+		of_property_read_u32(np_emif,
+				"low-power-mode-freq-threshold",
+				&cust_cfgs->lpmode_freq_threshold);
+	}
+
+	if (poll_intvl) {
+		cust_cfgs->mask |=
+				EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
+		cust_cfgs->temp_alert_poll_interval_ms = *poll_intvl;
+	}
+
+	if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
+		devm_kfree(emif->dev, cust_cfgs);
+		return;
+	}
+
+	emif->plat_data->custom_configs = cust_cfgs;
+}
+
+static void __init_or_module of_get_min_tck(struct device_node *np,
+		struct emif_data *emif)
+{
+	int			ret = 0;
+	struct lpddr2_min_tck	*min;
+
+	min = devm_kzalloc(emif->dev, sizeof(*min), GFP_KERNEL);
+	if (!min)
+		goto default_min_tck;
+
+	ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab);
+	ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD);
+	ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR);
+	ret |= of_property_read_u32(np, "tRASmin-min-tck", &min->tRASmin);
+	ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD);
+	ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR);
+	ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP);
+	ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP);
+	ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE);
+	ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR);
+	ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW);
+
+	if (ret) {
+		devm_kfree(emif->dev, min);
+		goto default_min_tck;
+	}
+
+	emif->plat_data->min_tck = min;
+	return;
+
+default_min_tck:
+	dev_warn(emif->dev, "%s: using default min-tck values\n", __func__);
+	emif->plat_data->min_tck = &lpddr2_jedec_min_tck;
+}
+
+static int __init_or_module of_do_get_timings(struct device_node *np,
+		struct lpddr2_timings *tim)
+{
+	int ret;
+
+	ret = of_property_read_u32(np, "max-freq", &tim->max_freq);
+	ret |= of_property_read_u32(np, "min-freq", &tim->min_freq);
+	ret |= of_property_read_u32(np, "tRPab", &tim->tRPab);
+	ret |= of_property_read_u32(np, "tRCD", &tim->tRCD);
+	ret |= of_property_read_u32(np, "tWR", &tim->tWR);
+	ret |= of_property_read_u32(np, "tRAS-min", &tim->tRAS_min);
+	ret |= of_property_read_u32(np, "tRRD", &tim->tRRD);
+	ret |= of_property_read_u32(np, "tWTR", &tim->tWTR);
+	ret |= of_property_read_u32(np, "tXP", &tim->tXP);
+	ret |= of_property_read_u32(np, "tRTP", &tim->tRTP);
+	ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR);
+	ret |= of_property_read_u32(np, "tDQSCK-max", &tim->tDQSCK_max);
+	ret |= of_property_read_u32(np, "tFAW", &tim->tFAW);
+	ret |= of_property_read_u32(np, "tZQCS", &tim->tZQCS);
+	ret |= of_property_read_u32(np, "tZQCL", &tim->tZQCL);
+	ret |= of_property_read_u32(np, "tZQinit", &tim->tZQinit);
+	ret |= of_property_read_u32(np, "tRAS-max-ns", &tim->tRAS_max_ns);
+	ret |= of_property_read_u32(np, "tDQSCK-max-derated",
+		&tim->tDQSCK_max_derated);
+
+	return ret;
+}
+
+static void __init_or_module of_get_ddr_timings(struct device_node *np_ddr,
+		struct emif_data *emif)
+{
+	struct lpddr2_timings	*timings = NULL;
+	u32			arr_sz = 0, i = 0;
+	struct device_node	*np_tim;
+	char			*tim_compat;
+
+	switch (emif->plat_data->device_info->type) {
+	case DDR_TYPE_LPDDR2_S2:
+	case DDR_TYPE_LPDDR2_S4:
+		tim_compat = "jedec,lpddr2-timings";
+		break;
+	default:
+		dev_warn(emif->dev, "%s: un-supported memory type\n", __func__);
+	}
+
+	for_each_child_of_node(np_ddr, np_tim)
+		if (of_device_is_compatible(np_tim, tim_compat))
+			arr_sz++;
+
+	if (arr_sz)
+		timings = devm_kzalloc(emif->dev, sizeof(*timings) * arr_sz,
+			GFP_KERNEL);
+
+	if (!timings)
+		goto default_timings;
+
+	for_each_child_of_node(np_ddr, np_tim) {
+		if (of_device_is_compatible(np_tim, tim_compat)) {
+			if (of_do_get_timings(np_tim, &timings[i])) {
+				devm_kfree(emif->dev, timings);
+				goto default_timings;
+			}
+			i++;
+		}
+	}
+
+	emif->plat_data->timings = timings;
+	emif->plat_data->timings_arr_size = arr_sz;
+
+	return;
+
+default_timings:
+	get_default_timings(emif);
+
+	return;
+}
+
+static void __init_or_module of_get_ddr_info(struct device_node *np_emif,
+		struct device_node *np_ddr,
+		struct ddr_device_info *dev_info)
+{
+	u32 density = 0, io_width = 0;
+	int len;
+
+	if (of_find_property(np_emif, "cs1-used", &len))
+		dev_info->cs1_used = true;
+
+	if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
+		dev_info->cal_resistors_per_cs = true;
+
+	if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s4"))
+		dev_info->type = DDR_TYPE_LPDDR2_S4;
+	else if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s2"))
+		dev_info->type = DDR_TYPE_LPDDR2_S2;
+
+	of_property_read_u32(np_ddr, "density", &density);
+	of_property_read_u32(np_ddr, "io-width", &io_width);
+
+	/* Convert from density in Mb to the density encoding in jedc_ddr.h */
+	if (density & (density - 1))
+		dev_info->density = 0;
+	else
+		dev_info->density = __fls(density) - 5;
+
+	/* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
+	if (io_width & (io_width - 1))
+		dev_info->io_width = 0;
+	else
+		dev_info->io_width = __fls(io_width) - 1;
+}
+
+static struct emif_data * __init_or_module of_get_device_details(
+		struct device_node *np_emif, struct device *dev)
+{
+	struct emif_data		*emif = NULL;
+	struct ddr_device_info		*dev_info = NULL;
+	struct emif_platform_data	*pd = NULL;
+	struct device_node		*np_ddr;
+	int				len;
+
+	np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
+	if (!np_ddr)
+		goto error;
+	emif	= devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
+	pd	= devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+	dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
+
+	if (!emif || !pd || !dev_info) {
+		dev_err(dev, "%s: of_get_device_details() failure!!\n",
+			__func__);
+		goto error;
+	}
+
+	emif->plat_data		= pd;
+	pd->device_info		= dev_info;
+	emif->dev		= dev;
+	emif->np_ddr		= np_ddr;
+	emif->temperature_level	= SDRAM_TEMP_NOMINAL;
+
+	if (of_device_is_compatible(np_emif, "ti,emif-4d"))
+		emif->plat_data->ip_rev = EMIF_4D;
+	else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
+		emif->plat_data->ip_rev = EMIF_4D5;
+
+	of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
+
+	if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
+		pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
+
+	of_get_ddr_info(np_emif, np_ddr, dev_info);
+	if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
+			pd->device_info->io_width, pd->phy_type, pd->ip_rev,
+			emif->dev)) {
+		dev_err(dev, "%s: invalid device data!!\n", __func__);
+		goto error;
+	}
+	/*
+	 * For EMIF instances other than EMIF1 see if the devices connected
+	 * are exactly same as on EMIF1(which is typically the case). If so,
+	 * mark it as a duplicate of EMIF1. This will save some memory and
+	 * computation.
+	 */
+	if (emif1 && emif1->np_ddr == np_ddr) {
+		emif->duplicate = true;
+		goto out;
+	} else if (emif1) {
+		dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
+			__func__);
+	}
+
+
+	of_get_custom_configs(np_emif, emif);
+	of_get_ddr_timings(np_ddr, emif);
+	of_get_min_tck(np_ddr, emif);
+	goto out;
+
+error:
+	return NULL;
+out:
+	return emif;
+}
+#endif
+
 static struct emif_data *__init_or_module get_device_details(
 		struct platform_device *pdev)
 {
@@ -1267,7 +1534,13 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 	struct resource		*res;
 	int			irq;
 
-	emif = get_device_details(pdev);
+#if defined(CONFIG_OF)
+	if (pdev->dev.of_node)
+		emif = of_get_device_details(pdev->dev.of_node, &pdev->dev);
+	else
+#endif
+		emif = get_device_details(pdev);
+
 	if (!emif) {
 		pr_err("%s: error getting device data\n", __func__);
 		goto error;
@@ -1644,11 +1917,21 @@ static void __attribute__((unused)) freq_post_notify_handling(void)
 	spin_unlock_irqrestore(&emif_lock, irq_state);
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id emif_of_match[] = {
+		{ .compatible = "ti,emif-4d" },
+		{ .compatible = "ti,emif-4d5" },
+		{},
+};
+MODULE_DEVICE_TABLE(of, emif_of_match);
+#endif
+
 static struct platform_driver emif_driver = {
 	.remove		= __exit_p(emif_remove),
 	.shutdown	= emif_shutdown,
 	.driver = {
 		.name = "emif",
+		.of_match_table = of_match_ptr(emif_of_match),
 	},
 };
 
-- 
1.7.1



From paul at pwsan.com  Thu Mar 15 14:39:08 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 15 Mar 2012 12:39:08 -0600 (MDT)
Subject: [PATCH] OMAP: clock: fix race in disable all clocks
In-Reply-To: <1331835871-13328-1-git-send-email-nm@ti.com>
References: <1331835871-13328-1-git-send-email-nm@ti.com>
Message-ID: <alpine.DEB.2.00.1203151236560.7108@utopia.booyaka.com>

Hi

adding Todd to cc

On Thu, 15 Mar 2012, Nishanth Menon wrote:

> clk_disable_unused is invoked when CONFIG_OMAP_RESET_CLOCKS=y.
> Since clk_disable_unused is called as lateinitcall, there can
> be more than a few workqueues executing off secondary CPU(s).
> The current code does the following:
> a) checks if clk is unused
> b) holds lock
> c) disables clk
> d) unlocks
> 
> Between (a) and (b) being executed on CPU0, It is possible to
> have a driver executing on CPU1 which could do a get_sync->clk_get
> (and increase the use_count) of the clock which was just about
> to be disabled by clk_disable_unused.
> 
> We ensure instead that the entire list traversal is protected by
> the lock allowing for parent child clock traversal which could be
> potentially be done by runtime operations to be safe as well.
> 
> Reported-by: Todd Poynor <toddpoynor at google.com>
> Signed-off-by: Nishanth Menon <nm at ti.com>

Thanks, I'll queue this for v3.4-rc1.

In the medium term, we should get rid of CONFIG_OMAP_RESET_CLOCKS, at 
least for the OMAP2+ chips, and just do this by default.  But this will 
need to wait until all of the OMAP2+ devices and drivers have been 
converted to use hwmod.  Patches to that end are also gladly accepted :-)
In 3.5 we should be in pretty good shape for OMAP4, but OMAP2/3 will still 
need some work.



- Paul


From philipp.zabel at gmail.com  Thu Mar 15 14:43:20 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Thu, 15 Mar 2012 19:43:20 +0100
Subject: [PATCH] pxa: Remove INIT_CLKREG macro, replace it with the
 equivalent CLKDEV_INIT
Message-ID: <1331837000.14662.23.camel@flow>

Only the struct clk pointer parameter had to be moved to the end.
The CLKDEV_INIT macro was added in 196a57c2749119be4732cc2b2adb8aafcb4fcb14
(ARM: 7131/1: clkdev: Add Common Macro for clk_lookup) for this purpose.

Signed-off-by: Philipp Zabel <philipp.zabel at gmail.com>
---
 arch/arm/mach-pxa/clock.h   |    7 -----
 arch/arm/mach-pxa/eseries.c |    2 +-
 arch/arm/mach-pxa/pxa25x.c  |   42 ++++++++++++++++----------------
 arch/arm/mach-pxa/pxa27x.c  |   56 +++++++++++++++++++++---------------------
 arch/arm/mach-pxa/pxa300.c  |    6 ++--
 arch/arm/mach-pxa/pxa320.c  |    4 +-
 arch/arm/mach-pxa/pxa3xx.c  |   48 ++++++++++++++++++------------------
 arch/arm/mach-pxa/pxa95x.c  |   32 ++++++++++++------------
 8 files changed, 95 insertions(+), 102 deletions(-)

diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 3a258b1..2946fa2 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -22,13 +22,6 @@ void clk_dummy_disable(struct clk *);
 extern const struct clkops clk_dummy_ops;
 extern struct clk clk_dummy;
 
-#define INIT_CLKREG(_clk,_devname,_conname)		\
-	{						\
-		.clk		= _clk,			\
-		.dev_id		= _devname,		\
-		.con_id		= _conname,		\
-	}
-
 #define DEFINE_CK(_name, _cken, _ops)			\
 struct clk clk_##_name = {				\
 		.ops	= _ops,				\
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 4cb2391..3c29343 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -141,7 +141,7 @@ static struct clk tmio_dummy_clk = {
 };
 
 static struct clk_lookup eseries_clkregs[] = {
-	INIT_CLKREG(&tmio_dummy_clk, NULL, "CLK_CK32K"),
+	CLKDEV_INIT(NULL, "CLK_CK32K", &tmio_dummy_clk),
 };
 
 static void __init eseries_register_clks(void)
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 3352b37..99dd55e 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -189,30 +189,30 @@ static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
 static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
 
 static struct clk_lookup pxa25x_clkregs[] = {
-	INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
-	INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
-	INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
-	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
-	INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
-	INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
-	INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
-	INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
-	INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
-	INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
-	INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
-	INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
-	INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
-	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
-	INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
-	INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
-	INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
-	INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
-	INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
-	INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+	CLKDEV_INIT("pxa2xx-fb", NULL, &clk_pxa25x_lcd),
+	CLKDEV_INIT("pxa2xx-uart.0", NULL, &clk_pxa25x_ffuart),
+	CLKDEV_INIT("pxa2xx-uart.1", NULL, &clk_pxa25x_btuart),
+	CLKDEV_INIT("pxa2xx-uart.2", NULL, &clk_pxa25x_stuart),
+	CLKDEV_INIT("pxa25x-udc", NULL, &clk_pxa25x_usb),
+	CLKDEV_INIT("pxa2xx-mci.0", NULL, &clk_pxa25x_mmc),
+	CLKDEV_INIT("pxa2xx-i2c.0", NULL, &clk_pxa25x_i2c),
+	CLKDEV_INIT("pxa25x-ssp.0", NULL, &clk_pxa25x_ssp),
+	CLKDEV_INIT("pxa25x-nssp.1", NULL, &clk_pxa25x_nssp),
+	CLKDEV_INIT("pxa25x-nssp.2", NULL, &clk_pxa25x_assp),
+	CLKDEV_INIT("pxa25x-pwm.0", NULL, &clk_pxa25x_pwm0),
+	CLKDEV_INIT("pxa25x-pwm.1", NULL, &clk_pxa25x_pwm1),
+	CLKDEV_INIT("pxa2xx-i2s", NULL, &clk_pxa25x_i2s),
+	CLKDEV_INIT("pxa2xx-ir", "UARTCLK", &clk_pxa25x_stuart),
+	CLKDEV_INIT("pxa2xx-ir", "FICPCLK", &clk_pxa25x_ficp),
+	CLKDEV_INIT(NULL, "AC97CLK", &clk_pxa25x_ac97),
+	CLKDEV_INIT(NULL, "GPIO11_CLK", &clk_pxa25x_gpio11),
+	CLKDEV_INIT(NULL, "GPIO12_CLK", &clk_pxa25x_gpio12),
+	CLKDEV_INIT("pxa2xx-pcmcia", NULL, &clk_pxa25x_mem),
+	CLKDEV_INIT("pxa-gpio", NULL, &clk_dummy),
 };
 
 static struct clk_lookup pxa25x_hwuart_clkreg =
-	INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
+	CLKDEV_INIT("pxa2xx-uart.3", NULL, &clk_pxa25x_hwuart);
 
 #ifdef CONFIG_PM
 
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 6bce78e..2ece3e2 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -202,34 +202,34 @@ static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
 static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
 
 static struct clk_lookup pxa27x_clkregs[] = {
-	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
-	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
-	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
-	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
-	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
-	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
-	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
-	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
-	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
-	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
-	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
-	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
-	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
-	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
-	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
-	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
-	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
-	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
-	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
-	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
-	INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
-	INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+	CLKDEV_INIT("pxa2xx-fb", NULL, &clk_pxa27x_lcd),
+	CLKDEV_INIT("pxa27x-camera.0", NULL, &clk_pxa27x_camera),
+	CLKDEV_INIT("pxa2xx-uart.0", NULL, &clk_pxa27x_ffuart),
+	CLKDEV_INIT("pxa2xx-uart.1", NULL, &clk_pxa27x_btuart),
+	CLKDEV_INIT("pxa2xx-uart.2", NULL, &clk_pxa27x_stuart),
+	CLKDEV_INIT("pxa2xx-i2s", NULL, &clk_pxa27x_i2s),
+	CLKDEV_INIT("pxa2xx-i2c.0", NULL, &clk_pxa27x_i2c),
+	CLKDEV_INIT("pxa27x-udc", NULL, &clk_pxa27x_usb),
+	CLKDEV_INIT("pxa2xx-mci.0", NULL, &clk_pxa27x_mmc),
+	CLKDEV_INIT("pxa2xx-ir", "UARTCLK", &clk_pxa27x_stuart),
+	CLKDEV_INIT("pxa2xx-ir", "FICPCLK", &clk_pxa27x_ficp),
+	CLKDEV_INIT("pxa27x-ohci", NULL, &clk_pxa27x_usbhost),
+	CLKDEV_INIT("pxa2xx-i2c.1", NULL, &clk_pxa27x_pwri2c),
+	CLKDEV_INIT("pxa27x-keypad", NULL, &clk_pxa27x_keypad),
+	CLKDEV_INIT("pxa27x-ssp.0", NULL, &clk_pxa27x_ssp1),
+	CLKDEV_INIT("pxa27x-ssp.1", NULL, &clk_pxa27x_ssp2),
+	CLKDEV_INIT("pxa27x-ssp.2", NULL, &clk_pxa27x_ssp3),
+	CLKDEV_INIT("pxa27x-pwm.0", NULL, &clk_pxa27x_pwm0),
+	CLKDEV_INIT("pxa27x-pwm.1", NULL, &clk_pxa27x_pwm1),
+	CLKDEV_INIT(NULL, "AC97CLK", &clk_pxa27x_ac97),
+	CLKDEV_INIT(NULL, "AC97CONFCLK", &clk_pxa27x_ac97conf),
+	CLKDEV_INIT(NULL, "MSLCLK", &clk_pxa27x_msl),
+	CLKDEV_INIT(NULL, "USIMCLK", &clk_pxa27x_usim),
+	CLKDEV_INIT(NULL, "MSTKCLK", &clk_pxa27x_memstk),
+	CLKDEV_INIT(NULL, "IMCLK", &clk_pxa27x_im),
+	CLKDEV_INIT(NULL, "MEMCLK", &clk_pxa27x_memc),
+	CLKDEV_INIT("pxa2xx-pcmcia", NULL, &clk_pxa27x_mem),
+	CLKDEV_INIT("pxa-gpio", NULL, &clk_dummy),
 };
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 40bb165..0cdab8c 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -87,14 +87,14 @@ static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0);
 static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0);
 
 static struct clk_lookup common_clkregs[] = {
-	INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
-	INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
+	CLKDEV_INIT("pxa3xx-nand", NULL, &clk_common_nand),
+	CLKDEV_INIT("pxa3xx-gcu", NULL, &clk_gcu),
 };
 
 static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
 
 static struct clk_lookup pxa310_clkregs[] = {
-	INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", NULL),
+	CLKDEV_INIT("pxa2xx-mci.2", NULL, &clk_pxa310_mmc3),
 };
 
 static int __init pxa300_init(void)
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index 8d614ec..994e991 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -81,8 +81,8 @@ static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0);
 static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0);
 
 static struct clk_lookup pxa320_clkregs[] = {
-	INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
-	INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
+	CLKDEV_INIT("pxa3xx-nand", NULL, &clk_pxa320_nand),
+	CLKDEV_INIT("pxa3xx-gcu", NULL, &clk_gcu),
 };
 
 static int __init pxa320_init(void)
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 3918a67..25a093e 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -64,31 +64,31 @@ static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
 
 static struct clk_lookup pxa3xx_clkregs[] = {
-	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
+	CLKDEV_INIT(NULL, "CLK_POUT", &clk_pxa3xx_pout),
 	/* Power I2C clock is always on */
-	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
-	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
-	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
-	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
-	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
-	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
-	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
-	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
-	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
-	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
-	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
-	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
-	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
-	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
-	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
-	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
-	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
-	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
-	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
-	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
-	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
-	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
-	INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
+	CLKDEV_INIT("pxa3xx-pwri2c.1", NULL, &clk_dummy),
+	CLKDEV_INIT("pxa2xx-fb", NULL, &clk_pxa3xx_lcd),
+	CLKDEV_INIT(NULL, "CAMCLK", &clk_pxa3xx_camera),
+	CLKDEV_INIT(NULL, "AC97CLK", &clk_pxa3xx_ac97),
+	CLKDEV_INIT("pxa2xx-uart.0", NULL, &clk_pxa3xx_ffuart),
+	CLKDEV_INIT("pxa2xx-uart.1", NULL, &clk_pxa3xx_btuart),
+	CLKDEV_INIT("pxa2xx-uart.2", NULL, &clk_pxa3xx_stuart),
+	CLKDEV_INIT("pxa2xx-ir", "UARTCLK", &clk_pxa3xx_stuart),
+	CLKDEV_INIT("pxa2xx-i2c.0", NULL, &clk_pxa3xx_i2c),
+	CLKDEV_INIT("pxa27x-udc", NULL, &clk_pxa3xx_udc),
+	CLKDEV_INIT("pxa27x-ohci", NULL, &clk_pxa3xx_usbh),
+	CLKDEV_INIT("pxa3xx-u2d", NULL, &clk_pxa3xx_u2d),
+	CLKDEV_INIT("pxa27x-keypad", NULL, &clk_pxa3xx_keypad),
+	CLKDEV_INIT("pxa27x-ssp.0", NULL, &clk_pxa3xx_ssp1),
+	CLKDEV_INIT("pxa27x-ssp.1", NULL, &clk_pxa3xx_ssp2),
+	CLKDEV_INIT("pxa27x-ssp.2", NULL, &clk_pxa3xx_ssp3),
+	CLKDEV_INIT("pxa27x-ssp.3", NULL, &clk_pxa3xx_ssp4),
+	CLKDEV_INIT("pxa27x-pwm.0", NULL, &clk_pxa3xx_pwm0),
+	CLKDEV_INIT("pxa27x-pwm.1", NULL, &clk_pxa3xx_pwm1),
+	CLKDEV_INIT("pxa2xx-mci.0", NULL, &clk_pxa3xx_mmc1),
+	CLKDEV_INIT("pxa2xx-mci.1", NULL, &clk_pxa3xx_mmc2),
+	CLKDEV_INIT("pxa2xx-pcmcia", NULL, &clk_pxa3xx_smemc),
+	CLKDEV_INIT("pxa-gpio", NULL, &clk_pxa3xx_gpio),
 };
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
index 5ce434b..2b29a45 100644
--- a/arch/arm/mach-pxa/pxa95x.c
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -214,23 +214,23 @@ static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa95x_gpio, GPIO, 13000000, 0);
 
 static struct clk_lookup pxa95x_clkregs[] = {
-	INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
+	CLKDEV_INIT(NULL, "CLK_POUT", &clk_pxa95x_pout),
 	/* Power I2C clock is always on */
-	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
-	INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
-	INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
-	INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
-	INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-uart.2", NULL),
-	INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-ir", "UARTCLK"),
-	INIT_CLKREG(&clk_pxa95x_i2c, "pxa2xx-i2c.0", NULL),
-	INIT_CLKREG(&clk_pxa95x_keypad, "pxa27x-keypad", NULL),
-	INIT_CLKREG(&clk_pxa95x_ssp1, "pxa27x-ssp.0", NULL),
-	INIT_CLKREG(&clk_pxa95x_ssp2, "pxa27x-ssp.1", NULL),
-	INIT_CLKREG(&clk_pxa95x_ssp3, "pxa27x-ssp.2", NULL),
-	INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL),
-	INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL),
-	INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
-	INIT_CLKREG(&clk_pxa95x_gpio, "pxa-gpio", NULL),
+	CLKDEV_INIT("pxa3xx-pwri2c.1", NULL, &clk_dummy),
+	CLKDEV_INIT("pxa2xx-fb", NULL, &clk_pxa95x_lcd),
+	CLKDEV_INIT("pxa2xx-uart.0", NULL, &clk_pxa95x_ffuart),
+	CLKDEV_INIT("pxa2xx-uart.1", NULL, &clk_pxa95x_btuart),
+	CLKDEV_INIT("pxa2xx-uart.2", NULL, &clk_pxa95x_stuart),
+	CLKDEV_INIT("pxa2xx-ir", "UARTCLK", &clk_pxa95x_stuart),
+	CLKDEV_INIT("pxa2xx-i2c.0", NULL, &clk_pxa95x_i2c),
+	CLKDEV_INIT("pxa27x-keypad", NULL, &clk_pxa95x_keypad),
+	CLKDEV_INIT("pxa27x-ssp.0", NULL, &clk_pxa95x_ssp1),
+	CLKDEV_INIT("pxa27x-ssp.1", NULL, &clk_pxa95x_ssp2),
+	CLKDEV_INIT("pxa27x-ssp.2", NULL, &clk_pxa95x_ssp3),
+	CLKDEV_INIT("pxa27x-ssp.3", NULL, &clk_pxa95x_ssp4),
+	CLKDEV_INIT("pxa27x-pwm.0", NULL, &clk_pxa95x_pwm0),
+	CLKDEV_INIT("pxa27x-pwm.1", NULL, &clk_pxa95x_pwm1),
+	CLKDEV_INIT("pxa-gpio", NULL, &clk_pxa95x_gpio),
 };
 
 void __init pxa95x_init_irq(void)
-- 
1.7.9.1




From paul at pwsan.com  Thu Mar 15 14:47:43 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 15 Mar 2012 12:47:43 -0600 (MDT)
Subject: [PATCH 6/6] ARM: OMAP: fix cpufreq build
In-Reply-To: <87aa3hdc3o.fsf@ti.com>
References: <20120315102845.GB16389@n2100.arm.linux.org.uk>
 <E1S87xU-0000N8-6u@rmk-PC.arm.linux.org.uk> <87aa3hdc3o.fsf@ti.com>
Message-ID: <alpine.DEB.2.00.1203151247220.7108@utopia.booyaka.com>

On Thu, 15 Mar 2012, Kevin Hilman wrote:

> Initially, this was intended as a cleanup because it was just dead code
> removal, but since we missed v3.4, maybe we should pull out 
> "ARM: OMAP: clock: cleanup CPUfreq leftovers" and submit for 3.4-rc.

If it doesn't go upstream for the 3.4 merge window, I'll submit it for 
3.4-rc.


- Paul


From kumarrav at codeaurora.org  Thu Mar 15 14:49:20 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Fri, 16 Mar 2012 00:19:20 +0530
Subject: [PATCH v3 1/2] dmaengine: Add support for per xfer specific
 privatedata
In-Reply-To: <4F606270.1020709@codeaurora.org>
References: <1331548336-27802-1-git-send-email-kumarrav@codeaurora.org>
 <1331569796.1727.9.camel@vkoul-udesk3> <4F606270.1020709@codeaurora.org>
Message-ID: <4F6239B0.6040507@codeaurora.org>

On 3/14/2012 2:48 PM, Ravi Kumar V wrote:
> On 3/12/2012 9:59 PM, Vinod Koul wrote:
>> On Mon, 2012-03-12 at 16:02 +0530, Ravi Kumar V wrote:
>>> Add new argument to DMA SG and Interleave mode for passing
>>> per transfer specific private data, using this it enables the
>>> dma devices which needs to pass the parameters which changes per
>>> each transfer.
>>>
>>> Signed-off-by: Ravi Kumar V<kumarrav at codeaurora.org>
>>> ---
>>> include/linux/dmaengine.h | 4 ++--
>>> 1 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
>>> index 679b349..b8f0495 100644
>>> --- a/include/linux/dmaengine.h
>>> +++ b/include/linux/dmaengine.h
>>> @@ -570,7 +570,7 @@ struct dma_device {
>>> struct dma_chan *chan,
>>> struct scatterlist *dst_sg, unsigned int dst_nents,
>>> struct scatterlist *src_sg, unsigned int src_nents,
>>> - unsigned long flags);
>>> + unsigned long flags, void *context);
>> Please follow the related discussion we had. Alexandre had already
>> posted updated and this needs to follow.
>> Also this way you break the existing drivers which use this API, not
>> sure why you posted without fixing them?
>>
I have gone through the discussion in
https://lkml.org/lkml/2012/2/6/300
As per my understanding
1.we need to add new transaction types DMA_SG_EXT & DMA_INTERLEAVE_EXT.
2.Add context parameter to existing API's.
3.Typecast the context parameter with architecture specific structure
there by restricting client drivers to pass only arch specific parameter.
4.Add inline functions as suggested by Russell
and then
5.Fix existing code and client drivers for using new API.

Hi Vinod,

I am ready to follow above steps and also suggested by Russell and 
submit new patch.
Please can you confirm me so that i will start work.

My suggestion is instead of adding context parameter in existing API's,
how it would be if we can add a new API for each DMA transaction types
available in dmaengine for passing transaction specific parameter?
so that existing clients and dma drivers will not be disturbed.

Thanks
Ravi Kumar
-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From s.hauer at pengutronix.de  Thu Mar 15 14:50:04 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 15 Mar 2012 19:50:04 +0100
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <20120315151521.GB5701@richard-laptop>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
 <20120314085228.GM3852@pengutronix.de>
 <20120315144601.GA5701@richard-laptop>
 <20120315150048.GC3852@pengutronix.de>
 <20120315151521.GB5701@richard-laptop>
Message-ID: <20120315185004.GD3852@pengutronix.de>

On Thu, Mar 15, 2012 at 11:15:23PM +0800, Richard Zhao wrote:
> On Thu, Mar 15, 2012 at 04:00:48PM +0100, Sascha Hauer wrote:
> > On Thu, Mar 15, 2012 at 10:46:04PM +0800, Richard Zhao wrote:
> > > On Wed, Mar 14, 2012 at 09:52:28AM +0100, Sascha Hauer wrote:
> > > > On Wed, Mar 14, 2012 at 04:22:58PM +0800, Richard Zhao wrote:
> > > > > Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> > > > > ---
> > > > >  
> > > > >  #define DEF_PLL(name)					\
> > > > >  	static struct clk name = {			\
> > > > > @@ -681,6 +741,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
> > > > >  		.disable	= pll_disable,		\
> > > > >  		.get_rate	= name##_get_rate,	\
> > > > >  		.set_rate	= name##_set_rate,	\
> > > > > +		.round_rate	= name##_round_rate,	\
> > > > 
> > > > I hope this ## stuff is gone soon with the generic clock framework. It
> > > > is so ugly and inefficient.
> > > I hope this doesn't prevent this two patches go in.
> > 
> > Given that we are short from getting a generic clock framework (and I
> > think this time it's for real) and that you are not mention in any words
> > what these patches fix I don't see a reason for merging them.
> I think the cpu clock is a great challenge for generic clock framework.
> When it set_rate, it includes reparent, and change parent's parent's rate.
> I don't see any upstream code like that till now. and it's really what
> we need.

Then do a clk_set_parent, clk_set_rate and a clk_set_parent again
in your cpufreq driver. The notifying mechanism even allows you to
block any concurrent change in between these three steps if necessary.
Noone says that these three steps have to be encapsulated in a single
clk_set_rate call like you did in your patch.

> 
> And it also block cpufreq from upstreaming.

Yes, and that's a good way to tell your management why you have to
invest some time into porting i.MX6 to the generic clock framework ;)

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From greg at kroah.com  Thu Mar 15 15:02:38 2012
From: greg at kroah.com (Greg KH)
Date: Thu, 15 Mar 2012 12:02:38 -0700
Subject: [PATCH v2 1/7] misc: ddr: add LPDDR2 data from JESD209-2
In-Reply-To: <1331835457-5390-2-git-send-email-aneesh@ti.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
 <1331835457-5390-2-git-send-email-aneesh@ti.com>
Message-ID: <20120315190238.GD11142@kroah.com>

On Thu, Mar 15, 2012 at 11:47:31PM +0530, Aneesh V wrote:
> add LPDDR2 data from the JEDEC spec JESD209-2. The data
> includes:
> 
> 1. Addressing information for LPDDR2 memories of different
>    densities and types(S2/S4)
> 2. AC timing data.
> 
> This data will useful for memory controller device drivers

Right now, only one driver, right?

> +#ifndef __ASSEMBLY__

Why is this needed?

> +/* Structure for DDR addressing info from the JEDEC spec */
> +struct lpddr2_addressing {
> +	u32 num_banks;
> +	u32 tREFI_ns;
> +	u32 tRFCab_ps;
> +};

Do these structures cross the user/kernel boundry somehow?  If so,
please use the proper kernel types for this.

> --- a/lib/Makefile
> +++ b/lib/Makefile
> @@ -123,6 +123,9 @@ obj-$(CONFIG_SIGNATURE) += digsig.o
>  
>  obj-$(CONFIG_CLZ_TAB) += clz_tab.o
>  
> +obj-$(CONFIG_DDR) += jedec_ddr_data.o
> +
> +

Why the extra line?

>  hostprogs-y	:= gen_crc32table
>  clean-files	:= crc32table.h
>  
> diff --git a/lib/jedec_ddr_data.c b/lib/jedec_ddr_data.c
> new file mode 100644
> index 0000000..fc223d6
> --- /dev/null
> +++ b/lib/jedec_ddr_data.c
> @@ -0,0 +1,135 @@
> +/*
> + * DDR addressing details and AC timing parameters from JEDEC specs
> + *
> + * Copyright (C) 2012 Texas Instruments, Inc.
> + *
> + * Aneesh V <aneesh at ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <misc/jedec_ddr.h>
> +#include <linux/module.h>
> +
> +/* LPDDR2 addressing details from JESD209-2 section 2.4 */
> +const struct lpddr2_addressing
> +	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
> +	{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
> +	{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
> +	{B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
> +	{B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
> +	{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
> +	{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
> +	{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
> +	{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
> +	{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
> +	{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
> +};
> +EXPORT_SYMBOL(lpddr2_jedec_addressing_table);

EXPORT_SYMBOL_GPL for these and the others?

thanks,

greg k-h


From greg at kroah.com  Thu Mar 15 15:04:44 2012
From: greg at kroah.com (Greg KH)
Date: Thu, 15 Mar 2012 12:04:44 -0700
Subject: [PATCH v2 0/7] Add TI EMIF SDRAM controller driver
In-Reply-To: <1331835457-5390-1-git-send-email-aneesh@ti.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
Message-ID: <20120315190444.GE11142@kroah.com>

On Thu, Mar 15, 2012 at 11:47:30PM +0530, Aneesh V wrote:
> Add a driver for the EMIF SDRAM controller used in TI SoCs
> 
> EMIF is an SDRAM controller that supports, based on its revision,
> one or more of LPDDR2/DDR2/DDR3 protocols.This driver adds support
> for LPDDR2.
> 
> The driver supports the following features:
> - Calculates the DDR AC timing parameters to be set in EMIF
>   registers using data from the device data-sheets and based
>   on the DDR frequency. If data from data-sheets is not available
>   default timing values from the JEDEC spec are used. These
>   will be safe, but not necessarily optimal
> - API for changing timings during DVFS or at boot-up

Is this a kernel/user API, or just an in-kernel API?

thanks,

greg k-h


From per.forlin at stericsson.com  Thu Mar 15 15:12:49 2012
From: per.forlin at stericsson.com (Per Forlin)
Date: Thu, 15 Mar 2012 20:12:49 +0100
Subject: [PATCH 0/5] MMC: mmci: Provide bindings for Device Tree
In-Reply-To: <201203151532.44363.arnd@arndb.de>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <CAFEEs1kz+QT_4Yc6byS4se0EMZvqA5hp5CvLvvtNgC++AJboxA@mail.gmail.com>
 <4F6209DA.1080809@linaro.org> <201203151532.44363.arnd@arndb.de>
Message-ID: <CAFEEs1=TJaCYmaWd7zd28NsV8ubZBpBn7p=Mi7vGtmV_vpfh1w@mail.gmail.com>

On Thu, Mar 15, 2012 at 4:32 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Thursday 15 March 2012, Lee Jones wrote:
>> > I would like to see what the minimal required change is to support DT
>> > for mmci without factorization.
>> > 1. Minimal change in mmci.
>> > 2. Add mmci_dt.c which contains the DT-populate code.
>> >
>> > The factorization could be done as step 2 I think.
>> >
>> > What do you say?
>>
>> I'm wondering what the difference is as the work has already been done.
>>
>> It was Arnd's suggestion to separate out the two types of variants, and
>> I'm quite fond of the new (fully featured) layout.
>
> Right, I usually prefer cleanups or other refactoring to be done first, and
> then features added on top.
>
> You could in theory add have just patches 3/4/5 all applied without
> the refactoring, but that I would be worried that this causes dependencies
> between the mmci driver and ux500 specific functionality like the
> stedma40_filter function.
>
About DT
I think I need to catch up on the DT-design a bit. I will try to catch
up on the DT-implementation and maybe then the refactorization will
make sense to me :)

Board specific data in mmci-driver
The stedma40 filter function is not really specific for ux500. ux500
use stedma40 but it should be possible to replace this DMA.IP with
some other DMA-controller. This is board specific configuration. You
should not need to change the mmci-driver just because the dma-driver
has changed, right?
Or will the board-configuration now be placed in mmci-ux500?

Common DT populate code for all mmc host drivers
Some parts of the DT-population is common for all the host driver, for
instance setting the CAP and CAP2. This code should be moved to a
common place to be used by other host drivers as well.

About refactoring
There are numbers of patches stashed up for MMCI waiting for verdict
here http://git.kernel.org/?p=linux/kernel/git/linusw/linux-stericsson.git;a=shortlog;h=refs/heads/mmci.
If doing a refactorization please rebase it on top of these patches.
This needs to be done carefully, there may be more to considerations
than just DT. Maybe the timing is better to do this for 4.5, just
after 4.4 is closed. Then we can make sure that all new patches are
made on top of the refactorized base.

BR
Per


From aneesh at ti.com  Thu Mar 15 15:56:47 2012
From: aneesh at ti.com (Aneesh V)
Date: Fri, 16 Mar 2012 01:26:47 +0530
Subject: [PATCH v2 1/7] misc: ddr: add LPDDR2 data from JESD209-2
In-Reply-To: <20120315190238.GD11142@kroah.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
 <1331835457-5390-2-git-send-email-aneesh@ti.com>
 <20120315190238.GD11142@kroah.com>
Message-ID: <4F62497F.1020907@ti.com>

On Friday 16 March 2012 12:32 AM, Greg KH wrote:
> On Thu, Mar 15, 2012 at 11:47:31PM +0530, Aneesh V wrote:
>> add LPDDR2 data from the JEDEC spec JESD209-2. The data
>> includes:
>>
>> 1. Addressing information for LPDDR2 memories of different
>>     densities and types(S2/S4)
>> 2. AC timing data.
>>
>> This data will useful for memory controller device drivers
>
> Right now, only one driver, right?

Yes, should that be documented?

>
>> +#ifndef __ASSEMBLY__
>
> Why is this needed?

IIRC, this header file was getting included in an omap specific header
file that was in turn included from an assembly file. I will check if
this is still the case. If not, I will remove it.

>
>> +/* Structure for DDR addressing info from the JEDEC spec */
>> +struct lpddr2_addressing {
>> +	u32 num_banks;
>> +	u32 tREFI_ns;
>> +	u32 tRFCab_ps;
>> +};
>
> Do these structures cross the user/kernel boundry somehow?  If so,
> please use the proper kernel types for this.

No. These structures are meant for use by device drivers.

>
>> --- a/lib/Makefile
>> +++ b/lib/Makefile
>> @@ -123,6 +123,9 @@ obj-$(CONFIG_SIGNATURE) += digsig.o
>>
>>   obj-$(CONFIG_CLZ_TAB) += clz_tab.o
>>
>> +obj-$(CONFIG_DDR) += jedec_ddr_data.o
>> +
>> +
>
> Why the extra line?

Un-intentional. Will remove.

>
>>   hostprogs-y	:= gen_crc32table
>>   clean-files	:= crc32table.h
>>
>> diff --git a/lib/jedec_ddr_data.c b/lib/jedec_ddr_data.c
>> new file mode 100644
>> index 0000000..fc223d6
>> --- /dev/null
>> +++ b/lib/jedec_ddr_data.c
>> @@ -0,0 +1,135 @@
>> +/*
>> + * DDR addressing details and AC timing parameters from JEDEC specs
>> + *
>> + * Copyright (C) 2012 Texas Instruments, Inc.
>> + *
>> + * Aneesh V<aneesh at ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include<misc/jedec_ddr.h>
>> +#include<linux/module.h>
>> +
>> +/* LPDDR2 addressing details from JESD209-2 section 2.4 */
>> +const struct lpddr2_addressing
>> +	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
>> +	{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
>> +	{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
>> +	{B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
>> +	{B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
>> +	{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
>> +	{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
>> +	{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
>> +	{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
>> +	{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
>> +	{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
>> +};
>> +EXPORT_SYMBOL(lpddr2_jedec_addressing_table);
>
> EXPORT_SYMBOL_GPL for these and the others?

Will fix all.

Thanks,
Aneesh


From linux at arm.linux.org.uk  Thu Mar 15 15:57:53 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 19:57:53 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <4F621939.9040906@ti.com>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <201203150922.06379.arnd@arndb.de> <4F621939.9040906@ti.com>
Message-ID: <20120315195753.GA2842@n2100.arm.linux.org.uk>

On Thu, Mar 15, 2012 at 05:30:49PM +0100, Cousson, Benoit wrote:
> This was done like IRQ on purpose, because an Interrupt ReQuest line and  
> a DMA Request line are really similar for the HW point of view at IP 
> level.

I'm not sure about that at all levels.  Sure, at hardware level they're
the same, but I think the flat numeric namespace for IRQs has been
proven to be a problem when there's multiple IRQ controllers in the
system.

> I'm not sure what Thierry have done for pwm, but I thing that having the  
> same scheme for reg, irq and dma was what we agreed with Grant during  
> Plumbers.

I really don't like these behind-the-scenes discussions which never then
get followed up in public, and people then start quoting what was "agreed"
as that's the way things must be done.

It's a bit like folk at the recent Linaro Connect apparantly discussing
my machine registry and deciding that it should be shut down.  No one
has yet talked to me about that or even done the curtesy of asking me
what my view is.

As far as I'm concerned for DMA stuff, there is currently no real solution
for a DT representation; TI have asked me to take over the conversion of
OMAP DMA support to the DMA engine API, and I'm not yet convinced that
the existing numbering system is the right solution - especially as
there's several overlapping numberspaces for OMAP DMA numbers which
are SoC specific.


From arnd at arndb.de  Thu Mar 15 16:01:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 20:01:12 +0000
Subject: linux-next: manual merge of the arm-soc tree with Linus' tree
In-Reply-To: <1362815.uO65s14ojU@avalon>
References: <20120315175000.897f1172c296d4a687be0537@canb.auug.org.au>
 <1362815.uO65s14ojU@avalon>
Message-ID: <201203152001.12353.arnd@arndb.de>

On Thursday 15 March 2012, Laurent Pinchart wrote:
> The following patch (5d7220ec000f rebased on top of 1740d3448012) shows the
> correct conflict resolution in my opinion.
> 
> From f040ba69632a54c86767974768d68b308901061c Mon Sep 17 00:00:00 2001
> From: Magnus Damm <damm at opensource.se>
> Date: Wed, 29 Feb 2012 12:37:19 +0900
> Subject: [PATCH] ARM: mach-shmobile: sh7372 map_io and init_early update
> 
> ARM: mach-shmobile: sh7372 map_io and init_early update
> 
> Update the sh7372 SoC and the AP4EVB and Mackerel boards to make use
> of the functions sh7372_map_io() and sh7372_add_early_devices().
> 
> Signed-off-by: Magnus Damm <damm at opensource.se>
> Signed-off-by: Rafael J. Wysocki <rjw at sisk.pl>
> Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>

Hi Laurent,

I've merged Paul's branch into my renesas/soc branch, because I don't
rebase the branches once they are merged into arm-soc. Thanks a lot
for the resolution you suggested, I used the same resulting code
in the merge commit.

I'm not particularly happy about how we got here. Obviously, the bug
fixes that Paul sent should have gone through the arm-soc tree to
avoid this situation, and they should have been based on a -rc release
rather than some random commit after -rc6. It's not a big issue
because the next/soc branch already contains -rc7 though.

	Arnd


From aneesh at ti.com  Thu Mar 15 16:01:15 2012
From: aneesh at ti.com (Aneesh V)
Date: Fri, 16 Mar 2012 01:31:15 +0530
Subject: [PATCH v2 0/7] Add TI EMIF SDRAM controller driver
In-Reply-To: <20120315190444.GE11142@kroah.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
 <20120315190444.GE11142@kroah.com>
Message-ID: <4F624A8B.7040407@ti.com>

On Friday 16 March 2012 12:34 AM, Greg KH wrote:
> On Thu, Mar 15, 2012 at 11:47:30PM +0530, Aneesh V wrote:
>> Add a driver for the EMIF SDRAM controller used in TI SoCs
>>
>> EMIF is an SDRAM controller that supports, based on its revision,
>> one or more of LPDDR2/DDR2/DDR3 protocols.This driver adds support
>> for LPDDR2.
>>
>> The driver supports the following features:
>> - Calculates the DDR AC timing parameters to be set in EMIF
>>    registers using data from the device data-sheets and based
>>    on the DDR frequency. If data from data-sheets is not available
>>    default timing values from the JEDEC spec are used. These
>>    will be safe, but not necessarily optimal
>> - API for changing timings during DVFS or at boot-up
>
> Is this a kernel/user API, or just an in-kernel API?

That's just an in-kernel API or more precisely callbacks to be
registered for DDR frequency change events.

thanks,
Aneesh


From arnd at arndb.de  Thu Mar 15 14:23:32 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 18:23:32 +0000
Subject: [PATCH 2/5] MMC: mmci: Seperate ARM variants from generic code
In-Reply-To: <20120315175443.GG15988@n2100.arm.linux.org.uk>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <201203151746.56678.arnd@arndb.de>
 <20120315175443.GG15988@n2100.arm.linux.org.uk>
Message-ID: <201203151823.32882.arnd@arndb.de>

On Thursday 15 March 2012, Russell King - ARM Linux wrote:
> On Thu, Mar 15, 2012 at 05:46:56PM +0000, Arnd Bergmann wrote:
> > Can you elaborate? I suggested the split in order to keep the ux500
> > specific parts local to one file. With the device tree conversion,
> > we really want to have them out of the platform code, but sticking them
> > into the main driver seems wrong, too.
> 
> You're talking about the data structures which describe what quirks to
> apply for the ux500 parts, rather than the actual quirks themselves.
> That's not a particularly clever thing to do because it separates out
> the selection of the works from the rest of the driver, which means
> simply searching for the flags to find out what's applied for what has
> to span several files.

Right, that is a disadvantage, but it's also how a lot of other
drivers work, in particular sdhci.

My reasoning is roughly this:

* we want to get rid of arch/arm/mach-ux500/board-mop500-sdi.c
* the sdi0_configure() and mop500_sdi0_vdd_handler() functions
  need to be moved somewhere in order to do that, so they should
  be with the driver.
* we don't want them in mmci.c, so we create a new file for these.
* in order to call do the setup from sdi0_configure right, it needs
  to be done in the probe() function
* if we want to have a separate probe function, we also need to
  have a separate amba_driver structure
* the variant_data in mmci.c belongs with the amba_id, so that
  also gets moved to the ux500 file.

If you have a better solution for one or more of these, I'm
all ears.

The alternatives that I can see are:
a) keep using auxdata to supply a platform_data pointer and
   do everything in the main driver. Problem: we want to
   avoid auxdata if possible
b) move the code from patch 4 into mmci.c using #ifdef.
   Problem: it's ugly code that has nothing to do with mmci
   in general.
c) use the regulator framework to do the voltage selection
   here, and have only generic code in mmci.c. This may
   be the best solution, but I have no idea if this is
   actually possible, or how to do it.

	arnd



From u.kleine-koenig at pengutronix.de  Thu Mar 15 16:18:23 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 15 Mar 2012 21:18:23 +0100
Subject: [PATCH] ARM: davinci: implement DEBUG_LL port choice
Message-ID: <1331842703-4248-1-git-send-email-u.kleine-koenig@pengutronix.de>

Apart from the necessity to do this change for multi-platform kernels
the previous logic depended on the zImage decompressor to write the
physical and virtual address to a magic memory location.
If the decompressor is unused or not correctly configured for the
current machid, the addruart macro was an infinite loop. Moreover
debugging the early zImage code was not possible either.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/Kconfig.debug                           |   16 ++++++
 arch/arm/mach-davinci/include/mach/debug-macro.S |   58 ++++++++--------------
 arch/arm/mach-davinci/include/mach/hardware.h    |    2 +-
 arch/arm/mach-davinci/include/mach/serial.h      |   10 ----
 arch/arm/mach-davinci/include/mach/uncompress.h  |   25 +++-------
 5 files changed, 44 insertions(+), 67 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e0d236d..57019be 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -108,6 +108,22 @@ choice
 		bool "Kernel low-level debugging on 9263, 9g45 and cap9"
 		depends on HAVE_AT91_DBGU1
 
+	config DEBUG_DAVINCI_UART0
+		bool "Kernel low-level debugging on Davinci using uart0
+		depends on ARCH_DAVINCI_DM644x
+
+	config DEBUG_DA8XX_UART1
+		bool "Kernel low-level debugging on DA8xx using uart1"
+		depends on ARCH_DAVINCI_DA8XX
+
+	config DEBUG_DA8XX_UART2
+		bool "Kernel low-level debugging on DA8xx using uart2"
+		depends on ARCH_DAVINCI_DA8XX
+
+	config DEBUG_TNETV107X_UART1
+		bool "Kernel low-level debugging on TNETV107x using uart1
+		depends on ARCH_DAVINCI_TNETV107X
+
 	config DEBUG_FOOTBRIDGE_COM1
 		bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
 		depends on FOOTBRIDGE
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index cf94552..9c08295 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -22,46 +22,28 @@
 
 #define UART_SHIFT	2
 
-		.pushsection .data
-davinci_uart_phys:	.word	0
-davinci_uart_virt:	.word	0
-		.popsection
-
-		.macro addruart, rp, rv, tmp
-
-		/* Use davinci_uart_phys/virt if already configured */
-10:		adr	\rp, 99f		@ get effective addr of 99f
-		ldr	\rv, [\rp]		@ get absolute addr of 99f
-		sub	\rv, \rv, \rp		@ offset between the two
-		ldr	\rp, [\rp, #4]		@ abs addr of omap_uart_phys
-		sub	\tmp, \rp, \rv		@ make it effective
-		ldr	\rp, [\tmp, #0]		@ davinci_uart_phys
-		ldr	\rv, [\tmp, #4]		@ davinci_uart_virt
-		cmp	\rp, #0			@ is port configured?
-		cmpne	\rv, #0
-		bne	100f			@ already configured
-
-		/* Check the debug UART address set in uncompress.h */
-		and	\rp, pc, #0xff000000
-		ldr	\rv, =DAVINCI_UART_INFO_OFS
-		add	\rp, \rp, \rv
-
-		/* Copy uart phys address from decompressor uart info */
-		ldr	\rv, [\rp, #0]
-		str	\rv, [\tmp, #0]
-
-		/* Copy uart virt address from decompressor uart info */
-		ldr	\rv, [\rp, #4]
-		str	\rv, [\tmp, #4]
-
-		b	10b
+#if defined(CONFIG_DEBUG_DAVINCI_UART0)
+#define UART_BASE	DAVINCI_UART0_BASE
+#elif defined(CONFIG_DEBUG_DA8XX_UART0)
+#define UART_BASE	DA8XX_UART0_BASE
+#elif defined(CONFIG_DEBUG_DA8XX_UART1)
+#define UART_BASE	DA8XX_UART1_BASE
+#elif defined(CONFIG_DEBUG_DA8XX_UART2)
+#define UART_BASE	DA8XX_UART2_BASE
+#elif defined(CONFIG_DEBUG_TNETV107X_UART1)
+#define UART_BASE	TNETV107X_UART2_BASE
+#define UART_VIRTBASE	TNETV107X_UART2_VIRT
+#else
+#error "Select a specifc port for DEBUG_LL"
+#endif
 
-		.align
-99:		.word	.
-		.word	davinci_uart_phys
-		.ltorg
+#ifndef UART_VIRTBASE
+#define UART_VIRTBASE IO_ADDRESS(UART_BASE)
+#endif
 
-100:
+		.macro addruart, rp, rv, tmp
+		ldr     \rp, =UART_BASE
+		ldr     \rv, =UART_VIRTBASE
 		.endm
 
 		.macro	senduart,rd,rx
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 414e0b9..649ddc2 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -24,7 +24,7 @@
 /*
  * I/O mapping
  */
-#define IO_PHYS				0x01c00000UL
+#define IO_PHYS				UL(0x01c00000)
 #define IO_OFFSET			0xfd000000 /* Virtual IO = 0xfec00000 */
 #define IO_SIZE				0x00400000
 #define IO_VIRT				(IO_PHYS + IO_OFFSET)
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index e347d88..46b3cd1 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -15,16 +15,6 @@
 
 #include <mach/hardware.h>
 
-/*
- * Stolen area that contains debug uart physical and virtual addresses.  These
- * addresses are filled in by the uncompress.h code, and are used by the debug
- * macros in debug-macro.S.
- *
- * This area sits just below the page tables (see arch/arm/kernel/head.S).
- * We define it as a relative offset from start of usable RAM.
- */
-#define DAVINCI_UART_INFO_OFS	0x3ff8
-
 #define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 9dc7cf9..25cf227 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -41,37 +41,25 @@ static inline void flush(void)
 		barrier();
 }
 
-static inline void set_uart_info(u32 phys, void * __iomem virt)
+static inline void set_uart_info(u32 phys)
 {
-	/*
-	 * Get address of some.bss variable and round it down
-	 * a la CONFIG_AUTO_ZRELADDR.
-	 */
-	u32 ram_start = (u32)&uart & 0xf8000000;
-	u32 *uart_info = (u32 *)(ram_start + DAVINCI_UART_INFO_OFS);
-
 	uart = (u32 *)phys;
-	uart_info[0] = phys;
-	uart_info[1] = (u32)virt;
 }
 
-#define _DEBUG_LL_ENTRY(machine, phys, virt)			\
+#define _DEBUG_LL_ENTRY(machine, phys)				\
 	if (machine_is_##machine()) {				\
-		set_uart_info(phys, virt);			\
+		set_uart_info(phys);				\
 		break;						\
 	}
 
 #define DEBUG_LL_DAVINCI(machine, port)				\
-	_DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE,	\
-			IO_ADDRESS(DAVINCI_UART##port##_BASE))
+	_DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE)
 
 #define DEBUG_LL_DA8XX(machine, port)				\
-	_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE,	\
-			IO_ADDRESS(DA8XX_UART##port##_BASE))
+	_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
 
 #define DEBUG_LL_TNETV107X(machine, port)			\
-	_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE,	\
-			TNETV107X_UART##port##_VIRT)
+	_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE)
 
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
@@ -96,6 +84,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 		DEBUG_LL_DA8XX(davinci_da850_evm,	2);
 		DEBUG_LL_DA8XX(mityomapl138,		1);
 		DEBUG_LL_DA8XX(omapl138_hawkboard,	2);
+		DEBUG_LL_DA8XX(bje_display3_5,		0);
 
 		/* TNETV107x boards */
 		DEBUG_LL_TNETV107X(tnetv107x,		1);
-- 
1.7.9.1



From linux at arm.linux.org.uk  Thu Mar 15 16:30:37 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 20:30:37 +0000
Subject: [PATCH 2/5] MMC: mmci: Seperate ARM variants from generic code
In-Reply-To: <201203151823.32882.arnd@arndb.de>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <201203151746.56678.arnd@arndb.de>
 <20120315175443.GG15988@n2100.arm.linux.org.uk>
 <201203151823.32882.arnd@arndb.de>
Message-ID: <20120315203037.GA2311@n2100.arm.linux.org.uk>

On Thu, Mar 15, 2012 at 06:23:32PM +0000, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Russell King - ARM Linux wrote:
> > On Thu, Mar 15, 2012 at 05:46:56PM +0000, Arnd Bergmann wrote:
> > > Can you elaborate? I suggested the split in order to keep the ux500
> > > specific parts local to one file. With the device tree conversion,
> > > we really want to have them out of the platform code, but sticking them
> > > into the main driver seems wrong, too.
> > 
> > You're talking about the data structures which describe what quirks to
> > apply for the ux500 parts, rather than the actual quirks themselves.
> > That's not a particularly clever thing to do because it separates out
> > the selection of the works from the rest of the driver, which means
> > simply searching for the flags to find out what's applied for what has
> > to span several files.
> 
> Right, that is a disadvantage, but it's also how a lot of other
> drivers work, in particular sdhci.
> 
> My reasoning is roughly this:
> 
> * we want to get rid of arch/arm/mach-ux500/board-mop500-sdi.c
> * the sdi0_configure() and mop500_sdi0_vdd_handler() functions
>   need to be moved somewhere in order to do that, so they should
>   be with the driver.

I don't believe they should.  MMCI _is_ the peripheral itself.  All the
stuff that's in board-mop500-sdi.c seems to be doing is configuration
type stuff for the SoC that its been integrated into.  Are you seriously
advocating having multiple drivers for essentially the same hardware?

> * we don't want them in mmci.c, so we create a new file for these.
> * in order to call do the setup from sdi0_configure right, it needs
>   to be done in the probe() function

I've always disagreed with this whole approach of "drivers should callback
into generic code to claim their GPIOs".  If the GPIO is dedicated by a
platform to a function, then that function is there independent of whether
the driver is present or not.  In many cases, it is totally _wrong_ to
leave a signal which should be driven unconfigured - if the board design
is such that its intended to be an output and there's no pull-up, it
could end up floating at half-supply which will eat power.

I have always been of the opinion that resources like GPIOs which are
under platform control should be requested and configured by the platform
and not by their respective drivers.

Have you noticed how much of the configuration is tweaked depending on
which init function is called?

> * if we want to have a separate probe function, we also need to
>   have a separate amba_driver structure
> * the variant_data in mmci.c belongs with the amba_id, so that
>   also gets moved to the ux500 file.
> 
> If you have a better solution for one or more of these, I'm
> all ears.

Are you really advocating having mmci_foo.c where foo is an ever
increasing number of SoCs with the MMCI integrated because you want
to integrate SoC specific details into the MMCI peripheral driver?

> The alternatives that I can see are:
> a) keep using auxdata to supply a platform_data pointer and
>    do everything in the main driver. Problem: we want to
>    avoid auxdata if possible
> b) move the code from patch 4 into mmci.c using #ifdef.
>    Problem: it's ugly code that has nothing to do with mmci
>    in general.
> c) use the regulator framework to do the voltage selection
>    here, and have only generic code in mmci.c. This may
>    be the best solution, but I have no idea if this is
>    actually possible, or how to do it.

Let's ignore the DMA stuff for the time being - that's a separate problem
which needs to be addressed once we work out how to deal with how DMA
engine stuff gets resolved with DT based systems.

The remainder of it (mmci_platform_data) looks like it can be easily
represented as DT properties, the exception to that is the ios_handler.
I think the right solution for that is to move to the regulator framework,
but allow the driver to continue having the ios callback if there is
no attached regulator.  It needs that because of the four integrated
regulator control bits (which are entirely undefined.)

We _do_ need a solution for GPIO-controlled voltage regulators, as these
are actually quite common - see the various soc-common using PCMCIA
drivers.

So I think actually a bit more thought is required here, and there's a
need to use some of the facilities such as regulator which are now present
that weren't when the driver was originally written some 9 years ago.


From arnd at arndb.de  Thu Mar 15 16:36:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 20:36:35 +0000
Subject: [GIT PULL v2] DaVinci DM644x video display support
In-Reply-To: <DF0F476B391FA8409C78302C7BA518B6317F13DB@DBDE01.ent.ti.com>
References: <DF0F476B391FA8409C78302C7BA518B6317F13DB@DBDE01.ent.ti.com>
Message-ID: <201203152036.36133.arnd@arndb.de>

On Sunday 11 March 2012, Nori, Sekhar wrote:
> Hi Arnd, Olof,
> 
> Can you please pull these two patches adding support
> for DaVinci DM644x V4L2 display support for v3.4.
> 
> These patches heavily depend on the clean-up series sent
> earlier. I have re-generated the pull request against
> v3.4/cleanup branch of my tree (already pulled earlier
> and unchanged since) as suggested by Olof.
> 
> Let me know if this works for you.

Looks good, applied to the next/drivers branch now.
Sorry for missing the pull request earlier, that was my fault
and I should have pulled it already.

I got a small merge conflict, see the resolution below.

	Arnd

commit e594a97c8c74533ec105b2ac9194217e918f172f
Merge: f66f9bd d5be5f5
Author: Arnd Bergmann <arnd at arndb.de>
Date:   Thu Mar 15 20:33:47 2012 +0000

    Merge branch 'v3.4/features' of git://gitorious.org/linux-davinci/linux-davinci into next/drivers
    
    * 'v3.4/features' of git://gitorious.org/linux-davinci/linux-davinci:
      ARM: davinci: dm644x evm: add support for VPBE display
      ARM: davinci: dm644x: add support for v4l2 video display
    
    * included from the davinci/cleanup branch:
      ARM: davinci: dm644x: don't force vpfe registeration on all boards
      ARM: davinci: dm644x: fix inconsistent variable naming
      ARM: davinci: dm644x: improve readability using macro
      ARM: davinci: streamline sysmod access
      ARM: davinci: create new common platform header for davinci
      ARM: davinci: dm646x: move private definitions to C file
      ARM: davinci: dm365: move private definitions to C file
      ARM: davinci: dm644x: move private definitions to C file
    
    Conflicts:
    	arch/arm/mach-davinci/board-dm644x-evm.c
    	arch/arm/mach-davinci/board-neuros-osd2.c
    	arch/arm/mach-davinci/board-sffsdr.c
    
    Signed-off-by: Arnd Bergmann <arnd at arndb.de>

diff --cc arch/arm/mach-davinci/board-dm644x-evm.c
index 1247ecd,3854235..3683306
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@@ -40,7 -39,9 +39,9 @@@
  #include <mach/usb.h>
  #include <mach/aemif.h>
  
+ #include "davinci.h"
+ 
 -#define DM644X_EVM_PHY_ID		"0:01"
 +#define DM644X_EVM_PHY_ID		"davinci_mdio-0:01"
  #define LXT971_PHY_ID	(0x001378e2)
  #define LXT971_PHY_MASK	(0xfffffff0)
  
diff --cc arch/arm/mach-davinci/board-neuros-osd2.c
index 8d34f51,3d12a3a..a772bb4
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@@ -39,7 -38,9 +38,9 @@@
  #include <mach/mmc.h>
  #include <mach/usb.h>
  
+ #include "davinci.h"
+ 
 -#define NEUROS_OSD2_PHY_ID		"0:01"
 +#define NEUROS_OSD2_PHY_ID		"davinci_mdio-0:01"
  #define LXT971_PHY_ID			0x001378e2
  #define LXT971_PHY_MASK			0xfffffff0
  
diff --cc arch/arm/mach-davinci/board-sffsdr.c
index 31da3c5,897cec5..76e67509
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@@ -42,7 -41,9 +41,9 @@@
  #include <mach/mux.h>
  #include <mach/usb.h>
  
+ #include "davinci.h"
+ 
 -#define SFFSDR_PHY_ID		"0:01"
 +#define SFFSDR_PHY_ID		"davinci_mdio-0:01"
  static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
  	/* U-Boot Environment: Block 0
  	 * UBL:                Block 1


From linux at arm.linux.org.uk  Thu Mar 15 16:36:27 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 20:36:27 +0000
Subject: [PATCH 0/5] MMC: mmci: Provide bindings for Device Tree
In-Reply-To: <CAFEEs1=TJaCYmaWd7zd28NsV8ubZBpBn7p=Mi7vGtmV_vpfh1w@mail.gmail.com>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <CAFEEs1kz+QT_4Yc6byS4se0EMZvqA5hp5CvLvvtNgC++AJboxA@mail.gmail.com>
 <4F6209DA.1080809@linaro.org> <201203151532.44363.arnd@arndb.de>
 <CAFEEs1=TJaCYmaWd7zd28NsV8ubZBpBn7p=Mi7vGtmV_vpfh1w@mail.gmail.com>
Message-ID: <20120315203627.GB2311@n2100.arm.linux.org.uk>

On Thu, Mar 15, 2012 at 08:12:49PM +0100, Per Forlin wrote:
> About refactoring
> There are numbers of patches stashed up for MMCI waiting for verdict
> here http://git.kernel.org/?p=linux/kernel/git/linusw/linux-stericsson.git;a=shortlog;h=refs/heads/mmci.
> If doing a refactorization please rebase it on top of these patches.

Quite a number of these are in linux-next via my tree:

http://ftp.arm.linux.org.uk/git/?p=linux-next.git;a=shortlog;h=7437cfa532842ce75189826742bddf1ba137f58e

There's 10 there, out of the 17 in Linus' tree.  See my previous replies
on why that's the case.


From arnd at arndb.de  Thu Mar 15 16:41:53 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 20:41:53 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120315195753.GA2842@n2100.arm.linux.org.uk>
References: <4F22DEF2.5000807@ti.com> <4F621939.9040906@ti.com>
 <20120315195753.GA2842@n2100.arm.linux.org.uk>
Message-ID: <201203152041.53754.arnd@arndb.de>

On Thursday 15 March 2012, Russell King - ARM Linux wrote:
> On Thu, Mar 15, 2012 at 05:30:49PM +0100, Cousson, Benoit wrote:
> > This was done like IRQ on purpose, because an Interrupt ReQuest line and  
> > a DMA Request line are really similar for the HW point of view at IP 
> > level.
> 
> I'm not sure about that at all levels.  Sure, at hardware level they're
> the same, but I think the flat numeric namespace for IRQs has been
> proven to be a problem when there's multiple IRQ controllers in the
> system.

In the DT bindings, both IRQ and the suggested DMA are not flat number
spaces, but instead can be of arbitrarly length defined by the controller.

> As far as I'm concerned for DMA stuff, there is currently no real solution
> for a DT representation; TI have asked me to take over the conversion of
> OMAP DMA support to the DMA engine API, and I'm not yet convinced that
> the existing numbering system is the right solution - especially as
> there's several overlapping numberspaces for OMAP DMA numbers which
> are SoC specific.

The numbers definitely need to become local to each of the controllers, but
that is the case pretty much automatically using the proposed binding,
because each dma request identifier starts with the phandle of the
controller.

	Arnd


From arnd at arndb.de  Thu Mar 15 16:54:50 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 20:54:50 +0000
Subject: [GIT PULL] Samsung EXYNOS5250 GPIO for v3.4
In-Reply-To: <4F61FBD0.4040904@samsung.com>
References: <4F61FBD0.4040904@samsung.com>
Message-ID: <201203152054.50953.arnd@arndb.de>

On Thursday 15 March 2012, Kukjin Kim wrote:
> Hi Arnd, Olof,
> 
> Please pull EXYNOS5250 gpio for v3.4.
> 
>    git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
> next/soc-exynos5250-gpio
> 
> It is including add support GPIOlib for EXYNOS5250 and Grant Likely 
> already agreed to send this via arm-soc for v3.4. Actually, this is 
> needed for compilation of EXYNOS5250 arch. As a note, this has no 
> dependency with others for merging.
> 
> If any problems, please let me know.
> 

Pulled into next/drivers.

Thanks,

	Arnd


From dhowells at redhat.com  Thu Mar 15 16:56:03 2012
From: dhowells at redhat.com (David Howells)
Date: Thu, 15 Mar 2012 20:56:03 +0000
Subject: [PATCH 05/38] Disintegrate asm/system.h for ARM [ver #3]
In-Reply-To: <20120315205514.28759.58969.stgit@warthog.procyon.org.uk>
References: <20120315205514.28759.58969.stgit@warthog.procyon.org.uk>
Message-ID: <20120315205603.28759.91855.stgit@warthog.procyon.org.uk>

Signed-off-by: David Howells <dhowells at redhat.com>
cc: linux-arm-kernel at lists.infradead.org
---

 arch/arm/common/via82c505.c                  |    1 
 arch/arm/include/asm/atomic.h                |    4 
 arch/arm/include/asm/barrier.h               |   70 ++++
 arch/arm/include/asm/bitops.h                |    2 
 arch/arm/include/asm/bug.h                   |   30 ++
 arch/arm/include/asm/cmpxchg.h               |  295 ++++++++++++++++
 arch/arm/include/asm/compiler.h              |   15 +
 arch/arm/include/asm/div64.h                 |    2 
 arch/arm/include/asm/dma.h                   |    1 
 arch/arm/include/asm/domain.h                |    4 
 arch/arm/include/asm/exec.h                  |    6 
 arch/arm/include/asm/io.h                    |    2 
 arch/arm/include/asm/mmu.h                   |    7 
 arch/arm/include/asm/processor.h             |    1 
 arch/arm/include/asm/switch_to.h             |   18 +
 arch/arm/include/asm/system.h                |  474 --------------------------
 arch/arm/include/asm/system_info.h           |   27 +
 arch/arm/include/asm/system_misc.h           |   30 ++
 arch/arm/include/asm/uaccess.h               |    2 
 arch/arm/kernel/armksyms.c                   |    1 
 arch/arm/kernel/elf.c                        |    1 
 arch/arm/kernel/entry-armv.S                 |    2 
 arch/arm/kernel/hw_breakpoint.c              |    1 
 arch/arm/kernel/irq.c                        |    1 
 arch/arm/kernel/kprobes-common.c             |    1 
 arch/arm/kernel/machine_kexec.c              |    2 
 arch/arm/kernel/process.c                    |    1 
 arch/arm/kernel/ptrace.c                     |    1 
 arch/arm/kernel/setup.c                      |    2 
 arch/arm/kernel/sleep.S                      |    1 
 arch/arm/kernel/tcm.c                        |    1 
 arch/arm/kernel/thumbee.c                    |    1 
 arch/arm/kernel/traps.c                      |    2 
 arch/arm/mach-at91/at91cap9.c                |    2 
 arch/arm/mach-at91/at91rm9200.c              |    1 
 arch/arm/mach-at91/at91sam9260.c             |    1 
 arch/arm/mach-at91/at91sam9261.c             |    1 
 arch/arm/mach-at91/at91sam9263.c             |    1 
 arch/arm/mach-at91/at91sam9g45.c             |    1 
 arch/arm/mach-at91/at91sam9rl.c              |    1 
 arch/arm/mach-at91/include/mach/system_rev.h |    2 
 arch/arm/mach-clps711x/common.c              |    1 
 arch/arm/mach-clps711x/p720t-leds.c          |    1 
 arch/arm/mach-davinci/board-da850-evm.c      |    1 
 arch/arm/mach-ebsa110/core.c                 |    2 
 arch/arm/mach-ebsa110/leds.c                 |    1 
 arch/arm/mach-footbridge/common.c            |    1 
 arch/arm/mach-footbridge/dc21285-timer.c     |    1 
 arch/arm/mach-footbridge/dc21285.c           |    1 
 arch/arm/mach-footbridge/ebsa285-leds.c      |    1 
 arch/arm/mach-footbridge/netwinder-hw.c      |    1 
 arch/arm/mach-footbridge/netwinder-leds.c    |    1 
 arch/arm/mach-imx/dma-v1.c                   |    1 
 arch/arm/mach-imx/mach-imx6q.c               |    1 
 arch/arm/mach-imx/mach-mx51_efikamx.c        |    1 
 arch/arm/mach-imx/mach-mx51_efikasb.c        |    1 
 arch/arm/mach-integrator/core.c              |    1 
 arch/arm/mach-integrator/leds.c              |    1 
 arch/arm/mach-integrator/pci.c               |    1 
 arch/arm/mach-integrator/pci_v3.c            |    1 
 arch/arm/mach-iop33x/uart.c                  |    1 
 arch/arm/mach-ixp2000/core.c                 |    1 
 arch/arm/mach-ixp2000/enp2611.c              |    1 
 arch/arm/mach-ixp2000/ixdp2400.c             |    1 
 arch/arm/mach-ixp2000/ixdp2800.c             |    1 
 arch/arm/mach-ixp2000/ixdp2x00.c             |    1 
 arch/arm/mach-ixp2000/ixdp2x01.c             |    1 
 arch/arm/mach-ixp2000/pci.c                  |    1 
 arch/arm/mach-ixp23xx/core.c                 |    1 
 arch/arm/mach-ixp23xx/espresso.c             |    1 
 arch/arm/mach-ixp23xx/ixdp2351.c             |    1 
 arch/arm/mach-ixp23xx/pci.c                  |    1 
 arch/arm/mach-ixp23xx/roadrunner.c           |    1 
 arch/arm/mach-ixp4xx/common-pci.c            |    1 
 arch/arm/mach-ixp4xx/goramo_mlr.c            |    1 
 arch/arm/mach-ks8695/time.c                  |    1 
 arch/arm/mach-mmp/common.c                   |    1 
 arch/arm/mach-mmp/pxa168.c                   |    1 
 arch/arm/mach-msm/board-sapphire.c           |    1 
 arch/arm/mach-mxs/system.c                   |    2 
 arch/arm/mach-omap1/id.c                     |    1 
 arch/arm/mach-omap1/leds-h2p2-debug.c        |    1 
 arch/arm/mach-omap1/leds-innovator.c         |    1 
 arch/arm/mach-omap1/leds-osk.c               |    1 
 arch/arm/mach-omap1/mux.c                    |    1 
 arch/arm/mach-omap1/time.c                   |    1 
 arch/arm/mach-omap1/timer32k.c               |    1 
 arch/arm/mach-omap2/board-omap3touchbook.c   |    1 
 arch/arm/mach-omap2/board-rx51-peripherals.c |    1 
 arch/arm/mach-omap2/mux.c                    |    1 
 arch/arm/mach-omap2/omap-mpuss-lowpower.c    |    1 
 arch/arm/mach-omap2/pm24xx.c                 |    1 
 arch/arm/mach-omap2/pm34xx.c                 |    1 
 arch/arm/mach-omap2/pm44xx.c                 |    1 
 arch/arm/mach-omap2/sleep44xx.S              |    1 
 arch/arm/mach-orion5x/common.c               |    1 
 arch/arm/mach-orion5x/dns323-setup.c         |    1 
 arch/arm/mach-orion5x/ls-chl-setup.c         |    1 
 arch/arm/mach-orion5x/ls_hgl-setup.c         |    1 
 arch/arm/mach-orion5x/lsmini-setup.c         |    1 
 arch/arm/mach-pnx4008/core.c                 |    2 
 arch/arm/mach-pnx4008/dma.c                  |    1 
 arch/arm/mach-pnx4008/irq.c                  |    1 
 arch/arm/mach-pnx4008/time.c                 |    1 
 arch/arm/mach-pxa/cm-x300.c                  |    1 
 arch/arm/mach-pxa/colibri-pxa3xx.c           |    1 
 arch/arm/mach-pxa/corgi.c                    |    1 
 arch/arm/mach-pxa/generic.c                  |    1 
 arch/arm/mach-pxa/leds-idp.c                 |    1 
 arch/arm/mach-pxa/leds-lubbock.c             |    1 
 arch/arm/mach-pxa/leds-mainstone.c           |    1 
 arch/arm/mach-pxa/magician.c                 |    1 
 arch/arm/mach-pxa/poodle.c                   |    1 
 arch/arm/mach-pxa/reset.c                    |    1 
 arch/arm/mach-pxa/viper.c                    |    1 
 arch/arm/mach-pxa/zeus.c                     |    1 
 arch/arm/mach-realview/core.c                |    1 
 arch/arm/mach-rpc/riscpc.c                   |    1 
 arch/arm/mach-s3c2410/s3c2410.c              |    1 
 arch/arm/mach-s3c2412/s3c2412.c              |    1 
 arch/arm/mach-s3c2416/s3c2416.c              |    1 
 arch/arm/mach-s3c2440/s3c244x.c              |    1 
 arch/arm/mach-s3c2443/s3c2443.c              |    1 
 arch/arm/mach-s3c64xx/common.c               |    1 
 arch/arm/mach-s5p64x0/common.c               |    1 
 arch/arm/mach-s5pc100/common.c               |    1 
 arch/arm/mach-sa1100/dma.c                   |    1 
 arch/arm/mach-sa1100/generic.c               |    2 
 arch/arm/mach-sa1100/leds-assabet.c          |    1 
 arch/arm/mach-sa1100/leds-badge4.c           |    1 
 arch/arm/mach-sa1100/leds-cerf.c             |    1 
 arch/arm/mach-sa1100/leds-hackkit.c          |    1 
 arch/arm/mach-sa1100/leds-lart.c             |    1 
 arch/arm/mach-sa1100/pm.c                    |    1 
 arch/arm/mach-shark/leds.c                   |    1 
 arch/arm/mach-shmobile/cpuidle.c             |    1 
 arch/arm/mach-shmobile/include/mach/system.h |    2 
 arch/arm/mach-shmobile/pm-r8a7779.c          |    1 
 arch/arm/mach-shmobile/pm-sh7372.c           |    1 
 arch/arm/mach-shmobile/suspend.c             |    2 
 arch/arm/mach-tegra/cpu-tegra.c              |    1 
 arch/arm/mach-versatile/core.c               |    1 
 arch/arm/mach-versatile/pci.c                |    1 
 arch/arm/mach-w90x900/cpu.c                  |    1 
 arch/arm/mm/alignment.c                      |    1 
 arch/arm/mm/fault.c                          |    3 
 arch/arm/mm/flush.c                          |    1 
 arch/arm/mm/idmap.c                          |    1 
 arch/arm/mm/ioremap.c                        |    1 
 arch/arm/mm/mmu.c                            |    1 
 arch/arm/mm/proc-fa526.S                     |    1 
 arch/arm/nwfpe/fpa11.c                       |    1 
 arch/arm/plat-iop/i2c.c                      |    1 
 arch/arm/plat-iop/pci.c                      |    1 
 arch/arm/plat-iop/restart.c                  |    1 
 arch/arm/plat-mxc/system.c                   |    2 
 arch/arm/plat-omap/debug-leds.c              |    1 
 arch/arm/plat-omap/dma.c                     |    1 
 arch/arm/plat-omap/mux.c                     |    1 
 arch/arm/plat-pxa/dma.c                      |    1 
 arch/arm/plat-s3c24xx/cpu.c                  |    1 
 arch/arm/plat-s3c24xx/dma.c                  |    1 
 arch/arm/plat-samsung/cpu.c                  |    1 
 arch/arm/plat-samsung/time.c                 |    1 
 arch/arm/plat-spear/restart.c                |    1 
 arch/arm/vfp/vfpmodule.c                     |    1 
 drivers/cpuidle/cpuidle.c                    |    1 
 drivers/net/ethernet/8390/etherh.c           |    1 
 drivers/tty/serial/21285.c                   |    1 
 drivers/watchdog/wdt285.c                    |    1 
 include/linux/mtd/map.h                      |    2 
 171 files changed, 594 insertions(+), 565 deletions(-)
 create mode 100644 arch/arm/include/asm/barrier.h
 create mode 100644 arch/arm/include/asm/cmpxchg.h
 create mode 100644 arch/arm/include/asm/compiler.h
 create mode 100644 arch/arm/include/asm/exec.h
 create mode 100644 arch/arm/include/asm/switch_to.h
 create mode 100644 arch/arm/include/asm/system_info.h
 create mode 100644 arch/arm/include/asm/system_misc.h

diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c
index 67dd2af..1171a50 100644
--- a/arch/arm/common/via82c505.c
+++ b/arch/arm/common/via82c505.c
@@ -6,7 +6,6 @@
 #include <linux/ioport.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 
 #include <asm/mach/pci.h>
 
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 86976d0..68374ba 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -13,7 +13,9 @@
 
 #include <linux/compiler.h>
 #include <linux/types.h>
-#include <asm/system.h>
+#include <linux/irqflags.h>
+#include <asm/barrier.h>
+#include <asm/cmpxchg.h>
 
 #define ATOMIC_INIT(i)	{ (i) }
 
diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
new file mode 100644
index 0000000..408e392
--- /dev/null
+++ b/arch/arm/include/asm/barrier.h
@@ -0,0 +1,70 @@
+#ifndef __ASM_BARRIER_H
+#define __ASM_BARRIER_H
+
+#ifdef __ASSEMBLY__
+#error do not include asm/barrier.h from assembly
+#endif
+
+#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
+
+#if __LINUX_ARM_ARCH__ >= 7 ||		\
+	(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
+#define sev()	__asm__ __volatile__ ("sev" : : : "memory")
+#define wfe()	__asm__ __volatile__ ("wfe" : : : "memory")
+#define wfi()	__asm__ __volatile__ ("wfi" : : : "memory")
+#endif
+
+#if __LINUX_ARM_ARCH__ >= 7
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+				    : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+				    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
+				    : : "r" (0) : "memory")
+#elif defined(CONFIG_CPU_FA526)
+#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
+				    : : "r" (0) : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+				    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#else
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
+				    : : "r" (0) : "memory")
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#endif
+
+#ifdef CONFIG_ARCH_HAS_BARRIERS
+#include <mach/barriers.h>
+#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
+#include <asm/outercache.h>
+#define mb()		do { dsb(); outer_sync(); } while (0)
+#define rmb()		dsb()
+#define wmb()		mb()
+#else
+#include <asm/memory.h>
+#define mb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
+#define rmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
+#define wmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
+#endif
+
+#ifndef CONFIG_SMP
+#define smp_mb()	barrier()
+#define smp_rmb()	barrier()
+#define smp_wmb()	barrier()
+#else
+#define smp_mb()	dmb()
+#define smp_rmb()	dmb()
+#define smp_wmb()	dmb()
+#endif
+
+#define read_barrier_depends()		do { } while(0)
+#define smp_read_barrier_depends()	do { } while(0)
+
+#define set_mb(var, value)	do { var = value; smp_mb(); } while (0)
+
+#endif /* __ASM_BARRIER_H */
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index f7419ef..e691ec9 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -24,7 +24,7 @@
 #endif
 
 #include <linux/compiler.h>
-#include <asm/system.h>
+#include <linux/irqflags.h>
 
 #define smp_mb__before_clear_bit()	smp_mb()
 #define smp_mb__after_clear_bit()	smp_mb()
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index fac79dc..7af5c6c 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -1,6 +1,7 @@
 #ifndef _ASMARM_BUG_H
 #define _ASMARM_BUG_H
 
+#include <linux/linkage.h>
 
 #ifdef CONFIG_BUG
 
@@ -57,4 +58,33 @@ do {								\
 
 #include <asm-generic/bug.h>
 
+struct pt_regs;
+void die(const char *msg, struct pt_regs *regs, int err);
+
+struct siginfo;
+void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
+		unsigned long err, unsigned long trap);
+
+#ifdef CONFIG_ARM_LPAE
+#define FAULT_CODE_ALIGNMENT	33
+#define FAULT_CODE_DEBUG	34
+#else
+#define FAULT_CODE_ALIGNMENT	1
+#define FAULT_CODE_DEBUG	2
+#endif
+
+void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
+				       struct pt_regs *),
+		     int sig, int code, const char *name);
+
+void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
+				       struct pt_regs *),
+		     int sig, int code, const char *name);
+
+extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
+
+struct mm_struct;
+extern void show_pte(struct mm_struct *mm, unsigned long addr);
+extern void __show_regs(struct pt_regs *);
+
 #endif
diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
new file mode 100644
index 0000000..d41d7cb
--- /dev/null
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -0,0 +1,295 @@
+#ifndef __ASM_ARM_CMPXCHG_H
+#define __ASM_ARM_CMPXCHG_H
+
+#include <linux/irqflags.h>
+#include <asm/barrier.h>
+
+#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
+/*
+ * On the StrongARM, "swp" is terminally broken since it bypasses the
+ * cache totally.  This means that the cache becomes inconsistent, and,
+ * since we use normal loads/stores as well, this is really bad.
+ * Typically, this causes oopsen in filp_close, but could have other,
+ * more disastrous effects.  There are two work-arounds:
+ *  1. Disable interrupts and emulate the atomic swap
+ *  2. Clean the cache, perform atomic swap, flush the cache
+ *
+ * We choose (1) since its the "easiest" to achieve here and is not
+ * dependent on the processor type.
+ *
+ * NOTE that this solution won't work on an SMP system, so explcitly
+ * forbid it here.
+ */
+#define swp_is_buggy
+#endif
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+{
+	extern void __bad_xchg(volatile void *, int);
+	unsigned long ret;
+#ifdef swp_is_buggy
+	unsigned long flags;
+#endif
+#if __LINUX_ARM_ARCH__ >= 6
+	unsigned int tmp;
+#endif
+
+	smp_mb();
+
+	switch (size) {
+#if __LINUX_ARM_ARCH__ >= 6
+	case 1:
+		asm volatile("@	__xchg1\n"
+		"1:	ldrexb	%0, [%3]\n"
+		"	strexb	%1, %2, [%3]\n"
+		"	teq	%1, #0\n"
+		"	bne	1b"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+	case 4:
+		asm volatile("@	__xchg4\n"
+		"1:	ldrex	%0, [%3]\n"
+		"	strex	%1, %2, [%3]\n"
+		"	teq	%1, #0\n"
+		"	bne	1b"
+			: "=&r" (ret), "=&r" (tmp)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+#elif defined(swp_is_buggy)
+#ifdef CONFIG_SMP
+#error SMP is not supported on this platform
+#endif
+	case 1:
+		raw_local_irq_save(flags);
+		ret = *(volatile unsigned char *)ptr;
+		*(volatile unsigned char *)ptr = x;
+		raw_local_irq_restore(flags);
+		break;
+
+	case 4:
+		raw_local_irq_save(flags);
+		ret = *(volatile unsigned long *)ptr;
+		*(volatile unsigned long *)ptr = x;
+		raw_local_irq_restore(flags);
+		break;
+#else
+	case 1:
+		asm volatile("@	__xchg1\n"
+		"	swpb	%0, %1, [%2]"
+			: "=&r" (ret)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+	case 4:
+		asm volatile("@	__xchg4\n"
+		"	swp	%0, %1, [%2]"
+			: "=&r" (ret)
+			: "r" (x), "r" (ptr)
+			: "memory", "cc");
+		break;
+#endif
+	default:
+		__bad_xchg(ptr, size), ret = 0;
+		break;
+	}
+	smp_mb();
+
+	return ret;
+}
+
+#define xchg(ptr,x) \
+	((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+#include <asm-generic/cmpxchg-local.h>
+
+#if __LINUX_ARM_ARCH__ < 6
+/* min ARCH < ARMv6 */
+
+#ifdef CONFIG_SMP
+#error "SMP is not supported on this platform"
+#endif
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+#define cmpxchg_local(ptr, o, n)				  	       \
+	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
+			(unsigned long)(n), sizeof(*(ptr))))
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+#ifndef CONFIG_SMP
+#include <asm-generic/cmpxchg.h>
+#endif
+
+#else	/* min ARCH >= ARMv6 */
+
+extern void __bad_cmpxchg(volatile void *ptr, int size);
+
+/*
+ * cmpxchg only support 32-bits operands on ARMv6.
+ */
+
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+				      unsigned long new, int size)
+{
+	unsigned long oldval, res;
+
+	switch (size) {
+#ifndef CONFIG_CPU_V6	/* min ARCH >= ARMv6K */
+	case 1:
+		do {
+			asm volatile("@ __cmpxchg1\n"
+			"	ldrexb	%1, [%2]\n"
+			"	mov	%0, #0\n"
+			"	teq	%1, %3\n"
+			"	strexbeq %0, %4, [%2]\n"
+				: "=&r" (res), "=&r" (oldval)
+				: "r" (ptr), "Ir" (old), "r" (new)
+				: "memory", "cc");
+		} while (res);
+		break;
+	case 2:
+		do {
+			asm volatile("@ __cmpxchg1\n"
+			"	ldrexh	%1, [%2]\n"
+			"	mov	%0, #0\n"
+			"	teq	%1, %3\n"
+			"	strexheq %0, %4, [%2]\n"
+				: "=&r" (res), "=&r" (oldval)
+				: "r" (ptr), "Ir" (old), "r" (new)
+				: "memory", "cc");
+		} while (res);
+		break;
+#endif
+	case 4:
+		do {
+			asm volatile("@ __cmpxchg4\n"
+			"	ldrex	%1, [%2]\n"
+			"	mov	%0, #0\n"
+			"	teq	%1, %3\n"
+			"	strexeq %0, %4, [%2]\n"
+				: "=&r" (res), "=&r" (oldval)
+				: "r" (ptr), "Ir" (old), "r" (new)
+				: "memory", "cc");
+		} while (res);
+		break;
+	default:
+		__bad_cmpxchg(ptr, size);
+		oldval = 0;
+	}
+
+	return oldval;
+}
+
+static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
+					 unsigned long new, int size)
+{
+	unsigned long ret;
+
+	smp_mb();
+	ret = __cmpxchg(ptr, old, new, size);
+	smp_mb();
+
+	return ret;
+}
+
+#define cmpxchg(ptr,o,n)						\
+	((__typeof__(*(ptr)))__cmpxchg_mb((ptr),			\
+					  (unsigned long)(o),		\
+					  (unsigned long)(n),		\
+					  sizeof(*(ptr))))
+
+static inline unsigned long __cmpxchg_local(volatile void *ptr,
+					    unsigned long old,
+					    unsigned long new, int size)
+{
+	unsigned long ret;
+
+	switch (size) {
+#ifdef CONFIG_CPU_V6	/* min ARCH == ARMv6 */
+	case 1:
+	case 2:
+		ret = __cmpxchg_local_generic(ptr, old, new, size);
+		break;
+#endif
+	default:
+		ret = __cmpxchg(ptr, old, new, size);
+	}
+
+	return ret;
+}
+
+#define cmpxchg_local(ptr,o,n)						\
+	((__typeof__(*(ptr)))__cmpxchg_local((ptr),			\
+				       (unsigned long)(o),		\
+				       (unsigned long)(n),		\
+				       sizeof(*(ptr))))
+
+#ifndef CONFIG_CPU_V6	/* min ARCH >= ARMv6K */
+
+/*
+ * Note : ARMv7-M (currently unsupported by Linux) does not support
+ * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
+ * not be allowed to use __cmpxchg64.
+ */
+static inline unsigned long long __cmpxchg64(volatile void *ptr,
+					     unsigned long long old,
+					     unsigned long long new)
+{
+	register unsigned long long oldval asm("r0");
+	register unsigned long long __old asm("r2") = old;
+	register unsigned long long __new asm("r4") = new;
+	unsigned long res;
+
+	do {
+		asm volatile(
+		"	@ __cmpxchg8\n"
+		"	ldrexd	%1, %H1, [%2]\n"
+		"	mov	%0, #0\n"
+		"	teq	%1, %3\n"
+		"	teqeq	%H1, %H3\n"
+		"	strexdeq %0, %4, %H4, [%2]\n"
+			: "=&r" (res), "=&r" (oldval)
+			: "r" (ptr), "Ir" (__old), "r" (__new)
+			: "memory", "cc");
+	} while (res);
+
+	return oldval;
+}
+
+static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
+						unsigned long long old,
+						unsigned long long new)
+{
+	unsigned long long ret;
+
+	smp_mb();
+	ret = __cmpxchg64(ptr, old, new);
+	smp_mb();
+
+	return ret;
+}
+
+#define cmpxchg64(ptr,o,n)						\
+	((__typeof__(*(ptr)))__cmpxchg64_mb((ptr),			\
+					    (unsigned long long)(o),	\
+					    (unsigned long long)(n)))
+
+#define cmpxchg64_local(ptr,o,n)					\
+	((__typeof__(*(ptr)))__cmpxchg64((ptr),				\
+					 (unsigned long long)(o),	\
+					 (unsigned long long)(n)))
+
+#else /* min ARCH = ARMv6 */
+
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+#endif
+
+#endif	/* __LINUX_ARM_ARCH__ >= 6 */
+
+#endif /* __ASM_ARM_CMPXCHG_H */
diff --git a/arch/arm/include/asm/compiler.h b/arch/arm/include/asm/compiler.h
new file mode 100644
index 0000000..8155db2
--- /dev/null
+++ b/arch/arm/include/asm/compiler.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_ARM_COMPILER_H
+#define __ASM_ARM_COMPILER_H
+
+/*
+ * This is used to ensure the compiler did actually allocate the register we
+ * asked it for some inline assembly sequences.  Apparently we can't trust
+ * the compiler from one version to another so a bit of paranoia won't hurt.
+ * This string is meant to be concatenated with the inline asm string and
+ * will cause compilation to stop on mismatch.
+ * (for details, see gcc PR 15089)
+ */
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+
+#endif /* __ASM_ARM_COMPILER_H */
diff --git a/arch/arm/include/asm/div64.h b/arch/arm/include/asm/div64.h
index d3f0a9e..fe92ccf 100644
--- a/arch/arm/include/asm/div64.h
+++ b/arch/arm/include/asm/div64.h
@@ -1,8 +1,8 @@
 #ifndef __ASM_ARM_DIV64
 #define __ASM_ARM_DIV64
 
-#include <asm/system.h>
 #include <linux/types.h>
+#include <asm/compiler.h>
 
 /*
  * The semantics of do_div() are:
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 69a5b0b..5694a0d 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -19,7 +19,6 @@
  * It should not be re-used except for that purpose.
  */
 #include <linux/spinlock.h>
-#include <asm/system.h>
 #include <asm/scatterlist.h>
 
 #include <mach/isa-dma.h>
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index b5dc173..3d22204 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -10,6 +10,10 @@
 #ifndef __ASM_PROC_DOMAIN_H
 #define __ASM_PROC_DOMAIN_H
 
+#ifndef __ASSEMBLY__
+#include <asm/barrier.h>
+#endif
+
 /*
  * Domain numbers
  *
diff --git a/arch/arm/include/asm/exec.h b/arch/arm/include/asm/exec.h
new file mode 100644
index 0000000..7c4fbef
--- /dev/null
+++ b/arch/arm/include/asm/exec.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARM_EXEC_H
+#define __ASM_ARM_EXEC_H
+
+#define arch_align_stack(x) (x)
+
+#endif /* __ASM_ARM_EXEC_H */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 9275828..bae7eb6 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -26,7 +26,6 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 #include <asm/memory.h>
-#include <asm/system.h>
 #include <asm-generic/pci_iomap.h>
 
 /*
@@ -99,6 +98,7 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 
 /* IO barriers */
 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
+#include <asm/barrier.h>
 #define __iormb()		rmb()
 #define __iowmb()		wmb()
 #else
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 1496565..b8e580a 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -34,4 +34,11 @@ typedef struct {
 
 #endif
 
+/*
+ * switch_mm() may do a full cache flush over the context switch,
+ * so enable interrupts over the context switch to avoid high
+ * latency.
+ */
+#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
+
 #endif
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index cb8d638..ce280b8 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -22,7 +22,6 @@
 #include <asm/hw_breakpoint.h>
 #include <asm/ptrace.h>
 #include <asm/types.h>
-#include <asm/system.h>
 
 #ifdef __KERNEL__
 #define STACK_TOP	((current->personality & ADDR_LIMIT_32BIT) ? \
diff --git a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h
new file mode 100644
index 0000000..fa09e6b
--- /dev/null
+++ b/arch/arm/include/asm/switch_to.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_ARM_SWITCH_TO_H
+#define __ASM_ARM_SWITCH_TO_H
+
+#include <linux/thread_info.h>
+
+/*
+ * switch_to(prev, next) should switch from task `prev' to `next'
+ * `prev' will never be the same as `next'.  schedule() itself
+ * contains the memory barrier to tell GCC not to cache `current'.
+ */
+extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
+
+#define switch_to(prev,next,last)					\
+do {									\
+	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
+} while (0)
+
+#endif /* __ASM_ARM_SWITCH_TO_H */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 774c41e..74542c5 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -1,466 +1,8 @@
-#ifndef __ASM_ARM_SYSTEM_H
-#define __ASM_ARM_SYSTEM_H
-
-#ifdef __KERNEL__
-
-#define CPU_ARCH_UNKNOWN	0
-#define CPU_ARCH_ARMv3		1
-#define CPU_ARCH_ARMv4		2
-#define CPU_ARCH_ARMv4T		3
-#define CPU_ARCH_ARMv5		4
-#define CPU_ARCH_ARMv5T		5
-#define CPU_ARCH_ARMv5TE	6
-#define CPU_ARCH_ARMv5TEJ	7
-#define CPU_ARCH_ARMv6		8
-#define CPU_ARCH_ARMv7		9
-
-/*
- * This is used to ensure the compiler did actually allocate the register we
- * asked it for some inline assembly sequences.  Apparently we can't trust
- * the compiler from one version to another so a bit of paranoia won't hurt.
- * This string is meant to be concatenated with the inline asm string and
- * will cause compilation to stop on mismatch.
- * (for details, see gcc PR 15089)
- */
-#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
-
-#ifndef __ASSEMBLY__
-
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-#include <linux/irqflags.h>
-
-#include <asm/outercache.h>
-
-struct thread_info;
-struct task_struct;
-
-/* information about the system we're running on */
-extern unsigned int system_rev;
-extern unsigned int system_serial_low;
-extern unsigned int system_serial_high;
-extern unsigned int mem_fclk_21285;
-
-struct pt_regs;
-
-void die(const char *msg, struct pt_regs *regs, int err);
-
-struct siginfo;
-void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
-		unsigned long err, unsigned long trap);
-
-#ifdef CONFIG_ARM_LPAE
-#define FAULT_CODE_ALIGNMENT	33
-#define FAULT_CODE_DEBUG	34
-#else
-#define FAULT_CODE_ALIGNMENT	1
-#define FAULT_CODE_DEBUG	2
-#endif
-
-void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
-				       struct pt_regs *),
-		     int sig, int code, const char *name);
-
-void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
-				       struct pt_regs *),
-		     int sig, int code, const char *name);
-
-#define xchg(ptr,x) \
-	((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
-
-struct mm_struct;
-extern void show_pte(struct mm_struct *mm, unsigned long addr);
-extern void __show_regs(struct pt_regs *);
-
-extern int __pure cpu_architecture(void);
-extern void cpu_init(void);
-
-void soft_restart(unsigned long);
-extern void (*arm_pm_restart)(char str, const char *cmd);
-
-#define UDBG_UNDEFINED	(1 << 0)
-#define UDBG_SYSCALL	(1 << 1)
-#define UDBG_BADABORT	(1 << 2)
-#define UDBG_SEGV	(1 << 3)
-#define UDBG_BUS	(1 << 4)
-
-extern unsigned int user_debug;
-
-#if __LINUX_ARM_ARCH__ >= 7 ||		\
-	(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
-#define sev()	__asm__ __volatile__ ("sev" : : : "memory")
-#define wfe()	__asm__ __volatile__ ("wfe" : : : "memory")
-#define wfi()	__asm__ __volatile__ ("wfi" : : : "memory")
-#endif
-
-#if __LINUX_ARM_ARCH__ >= 7
-#define isb() __asm__ __volatile__ ("isb" : : : "memory")
-#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
-#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
-#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
-#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
-				    : : "r" (0) : "memory")
-#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
-				    : : "r" (0) : "memory")
-#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
-				    : : "r" (0) : "memory")
-#elif defined(CONFIG_CPU_FA526)
-#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
-				    : : "r" (0) : "memory")
-#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
-				    : : "r" (0) : "memory")
-#define dmb() __asm__ __volatile__ ("" : : : "memory")
-#else
-#define isb() __asm__ __volatile__ ("" : : : "memory")
-#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
-				    : : "r" (0) : "memory")
-#define dmb() __asm__ __volatile__ ("" : : : "memory")
-#endif
-
-#ifdef CONFIG_ARCH_HAS_BARRIERS
-#include <mach/barriers.h>
-#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
-#define mb()		do { dsb(); outer_sync(); } while (0)
-#define rmb()		dsb()
-#define wmb()		mb()
-#else
-#include <asm/memory.h>
-#define mb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
-#define rmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
-#define wmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
-#endif
-
-#ifndef CONFIG_SMP
-#define smp_mb()	barrier()
-#define smp_rmb()	barrier()
-#define smp_wmb()	barrier()
-#else
-#define smp_mb()	dmb()
-#define smp_rmb()	dmb()
-#define smp_wmb()	dmb()
-#endif
-
-#define read_barrier_depends()		do { } while(0)
-#define smp_read_barrier_depends()	do { } while(0)
-
-#define set_mb(var, value)	do { var = value; smp_mb(); } while (0)
-#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
-
-/*
- * switch_mm() may do a full cache flush over the context switch,
- * so enable interrupts over the context switch to avoid high
- * latency.
- */
-#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
-
-/*
- * switch_to(prev, next) should switch from task `prev' to `next'
- * `prev' will never be the same as `next'.  schedule() itself
- * contains the memory barrier to tell GCC not to cache `current'.
- */
-extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
-
-#define switch_to(prev,next,last)					\
-do {									\
-	last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));	\
-} while (0)
-
-#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
-/*
- * On the StrongARM, "swp" is terminally broken since it bypasses the
- * cache totally.  This means that the cache becomes inconsistent, and,
- * since we use normal loads/stores as well, this is really bad.
- * Typically, this causes oopsen in filp_close, but could have other,
- * more disastrous effects.  There are two work-arounds:
- *  1. Disable interrupts and emulate the atomic swap
- *  2. Clean the cache, perform atomic swap, flush the cache
- *
- * We choose (1) since its the "easiest" to achieve here and is not
- * dependent on the processor type.
- *
- * NOTE that this solution won't work on an SMP system, so explcitly
- * forbid it here.
- */
-#define swp_is_buggy
-#endif
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
-{
-	extern void __bad_xchg(volatile void *, int);
-	unsigned long ret;
-#ifdef swp_is_buggy
-	unsigned long flags;
-#endif
-#if __LINUX_ARM_ARCH__ >= 6
-	unsigned int tmp;
-#endif
-
-	smp_mb();
-
-	switch (size) {
-#if __LINUX_ARM_ARCH__ >= 6
-	case 1:
-		asm volatile("@	__xchg1\n"
-		"1:	ldrexb	%0, [%3]\n"
-		"	strexb	%1, %2, [%3]\n"
-		"	teq	%1, #0\n"
-		"	bne	1b"
-			: "=&r" (ret), "=&r" (tmp)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
-		break;
-	case 4:
-		asm volatile("@	__xchg4\n"
-		"1:	ldrex	%0, [%3]\n"
-		"	strex	%1, %2, [%3]\n"
-		"	teq	%1, #0\n"
-		"	bne	1b"
-			: "=&r" (ret), "=&r" (tmp)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
-		break;
-#elif defined(swp_is_buggy)
-#ifdef CONFIG_SMP
-#error SMP is not supported on this platform
-#endif
-	case 1:
-		raw_local_irq_save(flags);
-		ret = *(volatile unsigned char *)ptr;
-		*(volatile unsigned char *)ptr = x;
-		raw_local_irq_restore(flags);
-		break;
-
-	case 4:
-		raw_local_irq_save(flags);
-		ret = *(volatile unsigned long *)ptr;
-		*(volatile unsigned long *)ptr = x;
-		raw_local_irq_restore(flags);
-		break;
-#else
-	case 1:
-		asm volatile("@	__xchg1\n"
-		"	swpb	%0, %1, [%2]"
-			: "=&r" (ret)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
-		break;
-	case 4:
-		asm volatile("@	__xchg4\n"
-		"	swp	%0, %1, [%2]"
-			: "=&r" (ret)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
-		break;
-#endif
-	default:
-		__bad_xchg(ptr, size), ret = 0;
-		break;
-	}
-	smp_mb();
-
-	return ret;
-}
-
-extern void disable_hlt(void);
-extern void enable_hlt(void);
-
-void cpu_idle_wait(void);
-
-#include <asm-generic/cmpxchg-local.h>
-
-#if __LINUX_ARM_ARCH__ < 6
-/* min ARCH < ARMv6 */
-
-#ifdef CONFIG_SMP
-#error "SMP is not supported on this platform"
-#endif
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n)				  	       \
-	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
-			(unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#ifndef CONFIG_SMP
-#include <asm-generic/cmpxchg.h>
-#endif
-
-#else	/* min ARCH >= ARMv6 */
-
-extern void __bad_cmpxchg(volatile void *ptr, int size);
-
-/*
- * cmpxchg only support 32-bits operands on ARMv6.
- */
-
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
-				      unsigned long new, int size)
-{
-	unsigned long oldval, res;
-
-	switch (size) {
-#ifndef CONFIG_CPU_V6	/* min ARCH >= ARMv6K */
-	case 1:
-		do {
-			asm volatile("@ __cmpxchg1\n"
-			"	ldrexb	%1, [%2]\n"
-			"	mov	%0, #0\n"
-			"	teq	%1, %3\n"
-			"	strexbeq %0, %4, [%2]\n"
-				: "=&r" (res), "=&r" (oldval)
-				: "r" (ptr), "Ir" (old), "r" (new)
-				: "memory", "cc");
-		} while (res);
-		break;
-	case 2:
-		do {
-			asm volatile("@ __cmpxchg1\n"
-			"	ldrexh	%1, [%2]\n"
-			"	mov	%0, #0\n"
-			"	teq	%1, %3\n"
-			"	strexheq %0, %4, [%2]\n"
-				: "=&r" (res), "=&r" (oldval)
-				: "r" (ptr), "Ir" (old), "r" (new)
-				: "memory", "cc");
-		} while (res);
-		break;
-#endif
-	case 4:
-		do {
-			asm volatile("@ __cmpxchg4\n"
-			"	ldrex	%1, [%2]\n"
-			"	mov	%0, #0\n"
-			"	teq	%1, %3\n"
-			"	strexeq %0, %4, [%2]\n"
-				: "=&r" (res), "=&r" (oldval)
-				: "r" (ptr), "Ir" (old), "r" (new)
-				: "memory", "cc");
-		} while (res);
-		break;
-	default:
-		__bad_cmpxchg(ptr, size);
-		oldval = 0;
-	}
-
-	return oldval;
-}
-
-static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
-					 unsigned long new, int size)
-{
-	unsigned long ret;
-
-	smp_mb();
-	ret = __cmpxchg(ptr, old, new, size);
-	smp_mb();
-
-	return ret;
-}
-
-#define cmpxchg(ptr,o,n)						\
-	((__typeof__(*(ptr)))__cmpxchg_mb((ptr),			\
-					  (unsigned long)(o),		\
-					  (unsigned long)(n),		\
-					  sizeof(*(ptr))))
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
-					    unsigned long old,
-					    unsigned long new, int size)
-{
-	unsigned long ret;
-
-	switch (size) {
-#ifdef CONFIG_CPU_V6	/* min ARCH == ARMv6 */
-	case 1:
-	case 2:
-		ret = __cmpxchg_local_generic(ptr, old, new, size);
-		break;
-#endif
-	default:
-		ret = __cmpxchg(ptr, old, new, size);
-	}
-
-	return ret;
-}
-
-#define cmpxchg_local(ptr,o,n)						\
-	((__typeof__(*(ptr)))__cmpxchg_local((ptr),			\
-				       (unsigned long)(o),		\
-				       (unsigned long)(n),		\
-				       sizeof(*(ptr))))
-
-#ifndef CONFIG_CPU_V6	/* min ARCH >= ARMv6K */
-
-/*
- * Note : ARMv7-M (currently unsupported by Linux) does not support
- * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
- * not be allowed to use __cmpxchg64.
- */
-static inline unsigned long long __cmpxchg64(volatile void *ptr,
-					     unsigned long long old,
-					     unsigned long long new)
-{
-	register unsigned long long oldval asm("r0");
-	register unsigned long long __old asm("r2") = old;
-	register unsigned long long __new asm("r4") = new;
-	unsigned long res;
-
-	do {
-		asm volatile(
-		"	@ __cmpxchg8\n"
-		"	ldrexd	%1, %H1, [%2]\n"
-		"	mov	%0, #0\n"
-		"	teq	%1, %3\n"
-		"	teqeq	%H1, %H3\n"
-		"	strexdeq %0, %4, %H4, [%2]\n"
-			: "=&r" (res), "=&r" (oldval)
-			: "r" (ptr), "Ir" (__old), "r" (__new)
-			: "memory", "cc");
-	} while (res);
-
-	return oldval;
-}
-
-static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
-						unsigned long long old,
-						unsigned long long new)
-{
-	unsigned long long ret;
-
-	smp_mb();
-	ret = __cmpxchg64(ptr, old, new);
-	smp_mb();
-
-	return ret;
-}
-
-#define cmpxchg64(ptr,o,n)						\
-	((__typeof__(*(ptr)))__cmpxchg64_mb((ptr),			\
-					    (unsigned long long)(o),	\
-					    (unsigned long long)(n)))
-
-#define cmpxchg64_local(ptr,o,n)					\
-	((__typeof__(*(ptr)))__cmpxchg64((ptr),				\
-					 (unsigned long long)(o),	\
-					 (unsigned long long)(n)))
-
-#else /* min ARCH = ARMv6 */
-
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#endif
-
-#endif	/* __LINUX_ARM_ARCH__ >= 6 */
-
-#endif /* __ASSEMBLY__ */
-
-#define arch_align_stack(x) (x)
-
-#endif /* __KERNEL__ */
-
-#endif
+/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
+#include <asm/barrier.h>
+#include <asm/compiler.h>
+#include <asm/cmpxchg.h>
+#include <asm/exec.h>
+#include <asm/switch_to.h>
+#include <asm/system_info.h>
+#include <asm/system_misc.h>
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
new file mode 100644
index 0000000..dfd386d
--- /dev/null
+++ b/arch/arm/include/asm/system_info.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_ARM_SYSTEM_INFO_H
+#define __ASM_ARM_SYSTEM_INFO_H
+
+#define CPU_ARCH_UNKNOWN	0
+#define CPU_ARCH_ARMv3		1
+#define CPU_ARCH_ARMv4		2
+#define CPU_ARCH_ARMv4T		3
+#define CPU_ARCH_ARMv5		4
+#define CPU_ARCH_ARMv5T		5
+#define CPU_ARCH_ARMv5TE	6
+#define CPU_ARCH_ARMv5TEJ	7
+#define CPU_ARCH_ARMv6		8
+#define CPU_ARCH_ARMv7		9
+
+#ifndef __ASSEMBLY__
+
+/* information about the system we're running on */
+extern unsigned int system_rev;
+extern unsigned int system_serial_low;
+extern unsigned int system_serial_high;
+extern unsigned int mem_fclk_21285;
+
+extern int __pure cpu_architecture(void);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_ARM_SYSTEM_INFO_H */
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
new file mode 100644
index 0000000..ccda6c2
--- /dev/null
+++ b/arch/arm/include/asm/system_misc.h
@@ -0,0 +1,30 @@
+#ifndef __ASM_ARM_SYSTEM_MISC_H
+#define __ASM_ARM_SYSTEM_MISC_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/irqflags.h>
+
+extern void cpu_init(void);
+
+void soft_restart(unsigned long);
+extern void (*arm_pm_restart)(char str, const char *cmd);
+
+#define UDBG_UNDEFINED	(1 << 0)
+#define UDBG_SYSCALL	(1 << 1)
+#define UDBG_BADABORT	(1 << 2)
+#define UDBG_SEGV	(1 << 3)
+#define UDBG_BUS	(1 << 4)
+
+extern unsigned int user_debug;
+
+extern void disable_hlt(void);
+extern void enable_hlt(void);
+
+void cpu_idle_wait(void);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_ARM_SYSTEM_MISC_H */
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 2958976..71f6536 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -16,8 +16,8 @@
 #include <asm/errno.h>
 #include <asm/memory.h>
 #include <asm/domain.h>
-#include <asm/system.h>
 #include <asm/unified.h>
+#include <asm/compiler.h>
 
 #define VERIFY_READ 0
 #define VERIFY_WRITE 1
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 5b0bce6..b57c75e 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -18,7 +18,6 @@
 #include <linux/io.h>
 
 #include <asm/checksum.h>
-#include <asm/system.h>
 #include <asm/ftrace.h>
 
 /*
diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c
index ddba41d..d0d1e83 100644
--- a/arch/arm/kernel/elf.c
+++ b/arch/arm/kernel/elf.c
@@ -3,6 +3,7 @@
 #include <linux/personality.h>
 #include <linux/binfmts.h>
 #include <linux/elf.h>
+#include <asm/system_info.h>
 
 int elf_check_arch(const struct elf32_hdr *x)
 {
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index be16a48..093a415 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -24,7 +24,7 @@
 #include <asm/unwind.h>
 #include <asm/unistd.h>
 #include <asm/tls.h>
-#include <asm/system.h>
+#include <asm/system_info.h>
 
 #include "entry-header.S"
 #include <asm/entry-macro-multi.S>
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index d6a95ef..ba386bd 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -34,7 +34,6 @@
 #include <asm/current.h>
 #include <asm/hw_breakpoint.h>
 #include <asm/kdebug.h>
-#include <asm/system.h>
 #include <asm/traps.h>
 
 /* Breakpoint currently in use for each BRP. */
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 3efd82c..6a6a097 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -36,7 +36,6 @@
 #include <linux/proc_fs.h>
 
 #include <asm/exception.h>
-#include <asm/system.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/kernel/kprobes-common.c b/arch/arm/kernel/kprobes-common.c
index a5394fb4..18a7628 100644
--- a/arch/arm/kernel/kprobes-common.c
+++ b/arch/arm/kernel/kprobes-common.c
@@ -13,6 +13,7 @@
 
 #include <linux/kernel.h>
 #include <linux/kprobes.h>
+#include <asm/system_info.h>
 
 #include "kprobes.h"
 
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 764bd45..5699598 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -12,7 +12,7 @@
 #include <asm/mmu_context.h>
 #include <asm/cacheflush.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
+#include <asm/system_misc.h>
 
 extern const unsigned char relocate_new_kernel[];
 extern const unsigned int relocate_new_kernel_size;
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 971d65c..784222c 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -35,7 +35,6 @@
 #include <asm/cacheflush.h>
 #include <asm/leds.h>
 #include <asm/processor.h>
-#include <asm/system.h>
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index ede6443..45956c9 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -26,7 +26,6 @@
 #include <linux/audit.h>
 
 #include <asm/pgtable.h>
-#include <asm/system.h>
 #include <asm/traps.h>
 
 #define REG_PC	15
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 615e992..9b19972 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -53,6 +53,8 @@
 #include <asm/traps.h>
 #include <asm/unwind.h>
 #include <asm/memblock.h>
+#include <asm/system_info.h>
+#include <asm/system_misc.h>
 
 #if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 #include "compat.h"
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 1f268bd..987dcf3 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -4,7 +4,6 @@
 #include <asm/assembler.h>
 #include <asm/glue-cache.h>
 #include <asm/glue-proc.h>
-#include <asm/system.h>
 	.text
 
 /*
diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
index 01ec453..30ae6bb 100644
--- a/arch/arm/kernel/tcm.c
+++ b/arch/arm/kernel/tcm.c
@@ -16,6 +16,7 @@
 #include <asm/cputype.h>
 #include <asm/mach/map.h>
 #include <asm/memory.h>
+#include <asm/system_info.h>
 #include "tcm.h"
 
 static struct gen_pool *tcm_pool;
diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c
index 9cb7aac..37bc322 100644
--- a/arch/arm/kernel/thumbee.c
+++ b/arch/arm/kernel/thumbee.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 
 #include <asm/thread_notify.h>
+#include <asm/system_info.h>
 
 /*
  * Access to the ThumbEE Handler Base register
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index f84dfe6..cd77743 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -29,11 +29,11 @@
 #include <linux/atomic.h>
 #include <asm/cacheflush.h>
 #include <asm/exception.h>
-#include <asm/system.h>
 #include <asm/unistd.h>
 #include <asm/traps.h>
 #include <asm/unwind.h>
 #include <asm/tls.h>
+#include <asm/system_misc.h>
 
 #include "signal.h"
 
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index a42edc2..fc460e9 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -17,6 +17,8 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
+#include <asm/system_misc.h>
 
 #include <mach/cpu.h>
 #include <mach/at91cap9.h>
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 99c3174..413c027 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/at91rm9200.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_st.h>
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index d4036ba..79f5718 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9260.h>
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 023c2ff..62818b9 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91_pmc.h>
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 75e876c..722ee08 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/at91sam9263.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 1cb6a96..47e8fdb 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -16,6 +16,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index d2c91a8..7ae4993 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -14,6 +14,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9rl.h>
diff --git a/arch/arm/mach-at91/include/mach/system_rev.h b/arch/arm/mach-at91/include/mach/system_rev.h
index ec164a4..ef79a9a 100644
--- a/arch/arm/mach-at91/include/mach/system_rev.h
+++ b/arch/arm/mach-at91/include/mach/system_rev.h
@@ -7,6 +7,8 @@
 #ifndef __ARCH_SYSTEM_REV_H__
 #define __ARCH_SYSTEM_REV_H__
 
+#include <asm/system_info.h>
+
 /*
  * board revision encoding
  * mach specific
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index ab1711b..ac84f92 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -37,6 +37,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/clps7111.h>
+#include <asm/system_misc.h>
 
 /*
  * This maps the generic CLPS711x registers
diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c
index 1512144..dd9a6cd 100644
--- a/arch/arm/mach-clps711x/p720t-leds.c
+++ b/arch/arm/mach-clps711x/p720t-leds.c
@@ -25,7 +25,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 
 #include <asm/hardware/clps7111.h>
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index d508890..5d9afd8 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -34,6 +34,7 @@
 #include <linux/delay.h>
 #include <linux/wl12xx.h>
 
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 294aad0..0c40e59 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -22,7 +22,7 @@
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-ebsa110/leds.c b/arch/arm/mach-ebsa110/leds.c
index 6a6ea57..101a320 100644
--- a/arch/arm/mach-ebsa110/leds.c
+++ b/arch/arm/mach-ebsa110/leds.c
@@ -17,7 +17,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 
 static spinlock_t leds_lock;
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 41978ee..3e6aaa6 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -21,6 +21,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/dec21285.h>
 
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index 121ad1d..3b54196 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -14,6 +14,7 @@
 
 #include <asm/hardware/dec21285.h>
 #include <asm/mach/time.h>
+#include <asm/system_info.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index f685650..94a7087 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -21,7 +21,6 @@
 #include <video/vga.h>
 
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 #include <asm/hardware/dec21285.h>
 
diff --git a/arch/arm/mach-footbridge/ebsa285-leds.c b/arch/arm/mach-footbridge/ebsa285-leds.c
index 4e10090..5bd2667 100644
--- a/arch/arm/mach-footbridge/ebsa285-leds.c
+++ b/arch/arm/mach-footbridge/ebsa285-leds.c
@@ -24,7 +24,6 @@
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
 
 #define LED_STATE_ENABLED	1
 #define LED_STATE_CLAIMED	2
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 80a1c5c..cac9f67 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -17,6 +17,7 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-footbridge/netwinder-leds.c b/arch/arm/mach-footbridge/netwinder-leds.c
index e57102e..5a2bd89 100644
--- a/arch/arm/mach-footbridge/netwinder-leds.c
+++ b/arch/arm/mach-footbridge/netwinder-leds.c
@@ -24,7 +24,6 @@
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
 
 #define LED_STATE_ENABLED	1
 #define LED_STATE_CLAIMED	2
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index 42afc29..3189a60 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -32,7 +32,6 @@
 #include <linux/scatterlist.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <mach/dma-v1.h>
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index c257281..527b697 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -21,6 +21,7 @@
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
index 3a5ed2d..586e9f8 100644
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ b/arch/arm/mach-imx/mach-mx51_efikamx.c
@@ -33,6 +33,7 @@
 #include <mach/iomux-mx51.h>
 
 #include <asm/setup.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
index ea5f65b..24aded9 100644
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ b/arch/arm/mach-imx/mach-mx51_efikasb.c
@@ -36,6 +36,7 @@
 #include <mach/iomux-mx51.h>
 
 #include <asm/setup.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 019f0ab..d2fd9f3 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -27,7 +27,6 @@
 #include <mach/platform.h>
 #include <asm/irq.h>
 #include <mach/cm.h>
-#include <asm/system.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index 28be186..466defa 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -29,7 +29,6 @@
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 #include <mach/cm.h>
 
diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c
index 520b6bf..36068f4 100644
--- a/arch/arm/mach-integrator/pci.c
+++ b/arch/arm/mach-integrator/pci.c
@@ -27,7 +27,6 @@
 #include <linux/init.h>
 
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 3c82566..9d47b4c 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -32,7 +32,6 @@
 #include <mach/platform.h>
 #include <asm/irq.h>
 #include <asm/signal.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 #include <asm/irq_regs.h>
 
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
index cdae24e..bbf54d7 100644
--- a/arch/arm/mach-iop33x/uart.c
+++ b/arch/arm/mach-iop33x/uart.c
@@ -22,7 +22,6 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
-#include <asm/system.h>
 #include <asm/memory.h>
 #include <mach/hardware.h>
 #include <asm/hardware/iop3xx.h>
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 81c4537..f214cdf 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -32,7 +32,6 @@
 #include <asm/memory.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
 
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index e872d23..4867f40 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -36,7 +36,6 @@
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index f53e911..558f5f8 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -29,7 +29,6 @@
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index a2e7c39..33c6d5f 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -29,7 +29,6 @@
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 634b6c8..910426a 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -30,7 +30,6 @@
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 7632bea..5196c39 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -34,7 +34,6 @@
 #include <asm/irq.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 626fda4..7e9a1f3 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -26,7 +26,6 @@
 #include <linux/io.h>
 
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index 0923bb9..ccdec42 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -34,7 +34,6 @@
 #include <asm/memory.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
 
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
index 8f2487e..d142d45 100644
--- a/arch/arm/mach-ixp23xx/espresso.c
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -32,7 +32,6 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
 
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index 5d5dd3e..b0e07db 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -36,7 +36,6 @@
 #include <asm/memory.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
 
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 25b5c46..bdf2866 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -28,7 +28,6 @@
 
 #include <asm/irq.h>
 #include <asm/sizes.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
index 377283f..eaaa3fa 100644
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -36,7 +36,6 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
 
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 5eff15f..0f445d3 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -32,7 +32,6 @@
 #include <asm/cputype.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 #include <mach/hardware.h>
 
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index c0e3d69..78ae12c 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -12,7 +12,6 @@
 #include <linux/pci.h>
 #include <linux/serial_8250.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 37dfcd5..ec783a3 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -27,6 +27,7 @@
 #include <linux/io.h>
 
 #include <asm/mach/time.h>
+#include <asm/system_misc.h>
 
 #include <mach/regs-timer.h>
 #include <mach/regs-irq.h>
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 062b5b9..c868a6c 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 
 #include <asm/page.h>
+#include <asm/system_misc.h>
 #include <asm/mach/map.h>
 #include <mach/addr-map.h>
 #include <mach/cputype.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index ada1213..d5c9a2e 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/platform_device.h>
 
+#include <asm/system_misc.h>
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/cputype.h>
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 97b8191..4a8ea0d 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -27,7 +27,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
-#include <asm/system.h>
 #include <mach/system.h>
 #include <mach/vreg.h>
 #include <mach/board.h>
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 54f91ad..30042e2 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -25,7 +25,7 @@
 #include <linux/module.h>
 
 #include <asm/proc-fns.h>
-#include <asm/system.h>
+#include <asm/system_misc.h>
 
 #include <mach/mxs.h>
 #include <mach/common.h>
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index a0e3560..b3f3363 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <asm/system_info.h>
 #include <plat/cpu.h>
 
 #define OMAP_DIE_ID_0		0xfffe1800
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
index 4b818eb..f6b14a1 100644
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ b/arch/arm/mach-omap1/leds-h2p2-debug.c
@@ -17,7 +17,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 
 #include <plat/fpga.h>
diff --git a/arch/arm/mach-omap1/leds-innovator.c b/arch/arm/mach-omap1/leds-innovator.c
index 9b99c28..3a066ee 100644
--- a/arch/arm/mach-omap1/leds-innovator.c
+++ b/arch/arm/mach-omap1/leds-innovator.c
@@ -5,7 +5,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
index da09f43..936ed42 100644
--- a/arch/arm/mach-omap1/leds-osk.c
+++ b/arch/arm/mach-omap1/leds-osk.c
@@ -8,7 +8,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 5fdef7a..087dba0 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -27,7 +27,6 @@
 #include <linux/io.h>
 #include <linux/spinlock.h>
 
-#include <asm/system.h>
 
 #include <plat/mux.h>
 
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index b8faffa..7595e0a 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -44,7 +44,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 9a54ef4..10bcd13 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -46,7 +46,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index a0b851a..c524c9d 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -38,6 +38,7 @@
 #include <linux/i2c/twl.h>
 
 #include <mach/hardware.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index acb4e77..2bf84fd 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -25,6 +25,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/mmc/host.h>
 #include <linux/power/isp1704_charger.h>
+#include <asm/system_info.h>
 
 #include <plat/mcspi.h>
 #include <plat/board.h>
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 611a0e3..e974d33 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -35,7 +35,6 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 
-#include <asm/system.h>
 
 #include <plat/omap_hwmod.h>
 
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 1d5d010..069f8fc 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -46,7 +46,6 @@
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
 #include <asm/smp_scu.h>
-#include <asm/system.h>
 #include <asm/pgalloc.h>
 #include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 23de98d..730bb00 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -34,6 +34,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 #include <asm/mach-types.h>
+#include <asm/system_misc.h>
 
 #include <mach/irqs.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc69875..64d95e6 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -31,6 +31,7 @@
 #include <trace/events/power.h>
 
 #include <asm/suspend.h>
+#include <asm/system_misc.h>
 
 #include <plat/sram.h>
 #include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index c264ef7..a73e325 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -16,6 +16,7 @@
 #include <linux/list.h>
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <asm/system_misc.h>
 
 #include "common.h"
 #include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index abd2834..9f6b83d 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -10,7 +10,6 @@
  */
 
 #include <linux/linkage.h>
-#include <asm/system.h>
 #include <asm/smp_scu.h>
 #include <asm/memory.h>
 #include <asm/hardware/cache-l2x0.h>
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 5dad38e..2448166 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -21,6 +21,7 @@
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 #include <asm/timex.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 91b0f47..f4f6ad2d 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -29,6 +29,7 @@
 #include <linux/ata_platform.h>
 #include <linux/phy.h>
 #include <linux/marvell_phy.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 5272131..0c9e413 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -22,7 +22,6 @@
 #include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/system.h>
 #include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 9a8697b..c1b5d8a 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -21,7 +21,6 @@
 #include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/system.h>
 #include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 09c7365..949eaa8 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -21,7 +21,6 @@
 #include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/system.h>
 #include <mach/orion5x.h>
 #include "common.h"
 #include "mpp.h"
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index 4cfb40b..be4c928 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -32,7 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
index 7fa4bf2..a4739e9 100644
--- a/arch/arm/mach-pnx4008/dma.c
+++ b/arch/arm/mach-pnx4008/dma.c
@@ -24,7 +24,6 @@
 #include <linux/io.h>
 #include <linux/gfp.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <mach/dma.h>
 #include <asm/dma-mapping.h>
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 7608c7a..41e4201 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -28,7 +28,6 @@
 #include <asm/setup.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
-#include <asm/system.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
index 0c8aad4..0cfe8af 100644
--- a/arch/arm/mach-pnx4008/time.c
+++ b/arch/arm/mach-pnx4008/time.c
@@ -24,7 +24,6 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 4b981b8..125ae08 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -55,6 +55,7 @@
 #include <mach/pxa3xx-u2d.h>
 
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
index 2b8ca0d..2075a69 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -20,6 +20,7 @@
 #include <asm/sizes.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
+#include <asm/system_info.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/mfp-pxa300.h>
 #include <mach/colibri.h>
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 11f1e73..de9d45e 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -40,7 +40,6 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 5432ecb..4225417 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -22,7 +22,6 @@
 #include <linux/init.h>
 
 #include <mach/hardware.h>
-#include <asm/system.h>
 #include <asm/mach/map.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/mach-pxa/leds-idp.c b/arch/arm/mach-pxa/leds-idp.c
index 8b9c171..06b0600 100644
--- a/arch/arm/mach-pxa/leds-idp.c
+++ b/arch/arm/mach-pxa/leds-idp.c
@@ -16,7 +16,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include <mach/pxa25x.h>
 #include <mach/idp.h>
diff --git a/arch/arm/mach-pxa/leds-lubbock.c b/arch/arm/mach-pxa/leds-lubbock.c
index e26d5ef..0bd85c8 100644
--- a/arch/arm/mach-pxa/leds-lubbock.c
+++ b/arch/arm/mach-pxa/leds-lubbock.c
@@ -15,7 +15,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <mach/pxa25x.h>
 #include <mach/lubbock.h>
 
diff --git a/arch/arm/mach-pxa/leds-mainstone.c b/arch/arm/mach-pxa/leds-mainstone.c
index db4af5e..4058ab3 100644
--- a/arch/arm/mach-pxa/leds-mainstone.c
+++ b/arch/arm/mach-pxa/leds-mainstone.c
@@ -14,7 +14,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include <mach/pxa27x.h>
 #include <mach/mainstone.h>
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 3d6baf9..264cd89 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -31,6 +31,7 @@
 #include <linux/i2c/pxa-i2c.h>
 
 #include <mach/hardware.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 744baee..89d98c8 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -34,7 +34,6 @@
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
-#include <asm/system.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index c8497b0..b452889 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -9,6 +9,7 @@
 #include <linux/gpio.h>
 #include <linux/io.h>
 #include <asm/proc-fns.h>
+#include <asm/system_misc.h>
 
 #include <mach/regs-ost.h>
 #include <mach/reset.h>
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 023d6ca..7a3d342 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -57,6 +57,7 @@
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
+#include <asm/system_info.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index a4dd1c3..4c5ae58 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -34,6 +34,7 @@
 #include <asm/suspend.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
 
 #include <mach/pxa27x.h>
 #include <mach/regs-uart.h>
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index acd329a..45868bb 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -33,7 +33,6 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index 3d44a59..e958597 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -28,6 +28,7 @@
 #include <asm/page.h>
 #include <asm/domain.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 061b6bb..a3c5cb0 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -30,6 +30,7 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <plat/cpu-freq.h>
 
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index aff6e85..100ef1c 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -31,6 +31,7 @@
 #include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/idle.h>
 
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 5287d28..ed67ec9 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -43,6 +43,7 @@
 #include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/idle.h>
 #include <mach/regs-s3c2443-clock.h>
diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c
index d15852f..6f74118 100644
--- a/arch/arm/mach-s3c2440/s3c244x.c
+++ b/arch/arm/mach-s3c2440/s3c244x.c
@@ -23,6 +23,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
+#include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index b9deaeb..9318847 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -29,6 +29,7 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/regs-s3c2443-clock.h>
 
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index bee7dcd..b313380 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -29,6 +29,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/vic.h>
+#include <asm/system_misc.h>
 
 #include <mach/map.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 52b89a3..a9d1ad4 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -30,6 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/map.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index c909573..dff11c3 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -30,6 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/map.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c
index ad66035..56e1333 100644
--- a/arch/arm/mach-sa1100/dma.c
+++ b/arch/arm/mach-sa1100/dma.c
@@ -16,7 +16,6 @@
 #include <linux/spinlock.h>
 #include <linux/errno.h>
 
-#include <asm/system.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <mach/dma.h>
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index bb10ee2..9ad9469 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -21,10 +21,10 @@
 
 #include <asm/div64.h>
 #include <mach/hardware.h>
-#include <asm/system.h>
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-sa1100/leds-assabet.c b/arch/arm/mach-sa1100/leds-assabet.c
index 64e9b4b..3699176 100644
--- a/arch/arm/mach-sa1100/leds-assabet.c
+++ b/arch/arm/mach-sa1100/leds-assabet.c
@@ -13,7 +13,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <mach/assabet.h>
 
 #include "leds.h"
diff --git a/arch/arm/mach-sa1100/leds-badge4.c b/arch/arm/mach-sa1100/leds-badge4.c
index cf1e384..f99fac3 100644
--- a/arch/arm/mach-sa1100/leds-badge4.c
+++ b/arch/arm/mach-sa1100/leds-badge4.c
@@ -14,7 +14,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-sa1100/leds-cerf.c b/arch/arm/mach-sa1100/leds-cerf.c
index 259b48e..040540f 100644
--- a/arch/arm/mach-sa1100/leds-cerf.c
+++ b/arch/arm/mach-sa1100/leds-cerf.c
@@ -7,7 +7,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-sa1100/leds-hackkit.c b/arch/arm/mach-sa1100/leds-hackkit.c
index 2bce137..6a23524 100644
--- a/arch/arm/mach-sa1100/leds-hackkit.c
+++ b/arch/arm/mach-sa1100/leds-hackkit.c
@@ -13,7 +13,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-sa1100/leds-lart.c b/arch/arm/mach-sa1100/leds-lart.c
index 0505a1f..a51830c 100644
--- a/arch/arm/mach-sa1100/leds-lart.c
+++ b/arch/arm/mach-sa1100/leds-lart.c
@@ -13,7 +13,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #include "leds.h"
 
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index bf85b8b..2fa499e 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -30,7 +30,6 @@
 #include <mach/hardware.h>
 #include <asm/memory.h>
 #include <asm/suspend.h>
-#include <asm/system.h>
 #include <asm/mach/time.h>
 
 extern int sa1100_finish_suspend(unsigned long);
diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c
index ccd4918..2560907 100644
--- a/arch/arm/mach-shark/leds.c
+++ b/arch/arm/mach-shark/leds.c
@@ -23,7 +23,6 @@
 #include <linux/io.h>
 
 #include <asm/leds.h>
-#include <asm/system.h>
 
 #define LED_STATE_ENABLED	1
 #define LED_STATE_CLAIMED	2
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
index 1b23342..21b09b6 100644
--- a/arch/arm/mach-shmobile/cpuidle.c
+++ b/arch/arm/mach-shmobile/cpuidle.c
@@ -13,7 +13,6 @@
 #include <linux/suspend.h>
 #include <linux/module.h>
 #include <linux/err.h>
-#include <asm/system.h>
 #include <asm/io.h>
 
 static void shmobile_enter_wfi(void)
diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
index 956ac18..9204270 100644
--- a/arch/arm/mach-shmobile/include/mach/system.h
+++ b/arch/arm/mach-shmobile/include/mach/system.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
+#include <asm/system_misc.h>
+
 static inline void arch_idle(void)
 {
 	cpu_do_idle();
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index c38ba7b..a18a4ae 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -18,7 +18,6 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/console.h>
-#include <asm/system.h>
 #include <asm/io.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index fcf8b17..a3bdb12 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -21,7 +21,6 @@
 #include <linux/irq.h>
 #include <linux/bitrev.h>
 #include <linux/console.h>
-#include <asm/system.h>
 #include <asm/io.h>
 #include <asm/tlbflush.h>
 #include <asm/suspend.h>
diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
index c1febe1..4d1b86a 100644
--- a/arch/arm/mach-shmobile/suspend.c
+++ b/arch/arm/mach-shmobile/suspend.c
@@ -12,8 +12,8 @@
 #include <linux/suspend.h>
 #include <linux/module.h>
 #include <linux/err.h>
-#include <asm/system.h>
 #include <asm/io.h>
+#include <asm/system_misc.h>
 
 static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
 {
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index bb5ce39..7a065f0 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -30,7 +30,6 @@
 #include <linux/io.h>
 #include <linux/suspend.h>
 
-#include <asm/system.h>
 
 #include <mach/clk.h>
 
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 02b7b93..f0932b5 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -36,7 +36,6 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
 
-#include <asm/system.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
 #include <asm/hardware/arm_timer.h>
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 90069bc..787cf5f 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -24,7 +24,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/system.h>
 #include <asm/mach/pci.h>
 
 /*
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 9a06619..9e4dd8b 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -28,6 +28,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-serial.h>
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 78459b8..72c751a 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -24,6 +24,7 @@
 
 #include <asm/cp15.h>
 #include <asm/unaligned.h>
+#include <asm/system_info.h>
 
 #include "fault.h"
 
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index bb7eac3..2da5df7 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -21,9 +21,10 @@
 #include <linux/perf_event.h>
 
 #include <asm/exception.h>
-#include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
+#include <asm/system_misc.h>
+#include <asm/system_info.h>
 
 #include "fault.h"
 
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 1a8d4aa..062d61a 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -16,7 +16,6 @@
 #include <asm/cachetype.h>
 #include <asm/highmem.h>
 #include <asm/smp_plat.h>
-#include <asm/system.h>
 #include <asm/tlbflush.h>
 
 #include "mm.h"
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index feacf4c..ab88ed4 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -5,6 +5,7 @@
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
 #include <asm/sections.h>
+#include <asm/system_info.h>
 
 pgd_t *idmap_pgd;
 
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 66daf17..6780b49 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -33,6 +33,7 @@
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
 #include <asm/sizes.h>
+#include <asm/system_info.h>
 
 #include <asm/mach/map.h>
 #include "mm.h"
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 163a69a..8aa1add 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -27,6 +27,7 @@
 #include <asm/tlb.h>
 #include <asm/highmem.h>
 #include <asm/traps.h>
+#include <asm/system_info.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 272558a..d217e97 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -22,7 +22,6 @@
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
-#include <asm/system.h>
 
 #include "proc-macros.S"
 
diff --git a/arch/arm/nwfpe/fpa11.c b/arch/arm/nwfpe/fpa11.c
index cc60acd..2782ebc 100644
--- a/arch/arm/nwfpe/fpa11.c
+++ b/arch/arm/nwfpe/fpa11.c
@@ -28,7 +28,6 @@
 
 #include <linux/compiler.h>
 #include <linux/string.h>
-#include <asm/system.h>
 
 /* Reset the FPA11 chip.  Called to initialize and reset the emulator. */
 static void resetFPA11(void)
diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c
index 4efe392..88215ad 100644
--- a/arch/arm/plat-iop/i2c.c
+++ b/arch/arm/plat-iop/i2c.c
@@ -23,7 +23,6 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
-#include <asm/system.h>
 #include <asm/memory.h>
 #include <mach/hardware.h>
 #include <asm/hardware/iop3xx.h>
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index f4d40a2..bb26981 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -20,7 +20,6 @@
 #include <linux/io.h>
 #include <asm/irq.h>
 #include <asm/signal.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/mach/pci.h>
 #include <asm/hardware/iop3xx.h>
diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
index 6a85a0c..33fa699 100644
--- a/arch/arm/plat-iop/restart.c
+++ b/arch/arm/plat-iop/restart.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <asm/hardware/iop3xx.h>
+#include <asm/system_misc.h>
 #include <mach/hardware.h>
 
 void iop3xx_restart(char mode, const char *cmd)
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 3599bf2..c195d6d 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -25,8 +25,8 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
+#include <asm/system_misc.h>
 #include <asm/proc-fns.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 
 void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 61a1ec2..39407cb 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -15,7 +15,6 @@
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
-#include <asm/system.h>
 #include <asm/mach-types.h>
 
 #include <plat/fpga.h>
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 002fb4d..dbb1049 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,7 +36,6 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <plat/dma.h>
 
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 0d4aa0d..976fc80 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -26,7 +26,6 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/system.h>
 #include <linux/spinlock.h>
 #include <plat/mux.h>
 
diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c
index 2d3c19d..79ef102 100644
--- a/arch/arm/plat-pxa/dma.c
+++ b/arch/arm/plat-pxa/dma.c
@@ -20,7 +20,6 @@
 #include <linux/errno.h>
 #include <linux/dma-mapping.h>
 
-#include <asm/system.h>
 #include <asm/irq.h>
 #include <asm/memory.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 21f1fda..ded6431 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -34,6 +34,7 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/cacheflush.h>
+#include <asm/system_info.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 2bab4c9..28f898f 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -27,7 +27,6 @@
 #include <linux/errno.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <mach/dma.h>
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
index 81c06d4..46b426e 100644
--- a/arch/arm/plat-samsung/cpu.c
+++ b/arch/arm/plat-samsung/cpu.c
@@ -15,7 +15,6 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
-#include <asm/system.h>
 
 #include <mach/map.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index e3bb806..4dcb11c 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -28,7 +28,6 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 
-#include <asm/system.h>
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 2b4e3d8..16f203e 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -11,6 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 #include <linux/io.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/sp810.h>
 #include <mach/hardware.h>
 #include <mach/generic.h>
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index d89068f..9f50997 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -22,6 +22,7 @@
 #include <asm/cputype.h>
 #include <asm/thread_notify.h>
 #include <asm/vfp.h>
+#include <asm/system_info.h>
 
 #include "vfpinstr.h"
 #include "vfp.h"
diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index 59f4261..654076e 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -19,6 +19,7 @@
 #include <linux/hrtimer.h>
 #include <linux/module.h>
 #include <trace/events/power.h>
+#include <asm/system_misc.h>
 
 #include "cpuidle.h"
 
diff --git a/drivers/net/ethernet/8390/etherh.c b/drivers/net/ethernet/8390/etherh.c
index 48c4948..a45b0d8 100644
--- a/drivers/net/ethernet/8390/etherh.c
+++ b/drivers/net/ethernet/8390/etherh.c
@@ -48,6 +48,7 @@
 #include <asm/system.h>
 #include <asm/ecard.h>
 #include <asm/io.h>
+#include <asm/system_info.h>
 
 #define EI_SHIFT(x)	(ei_local->reg_offset[x])
 
diff --git a/drivers/tty/serial/21285.c b/drivers/tty/serial/21285.c
index 1b37626..6d0ddbc 100644
--- a/drivers/tty/serial/21285.c
+++ b/drivers/tty/serial/21285.c
@@ -16,6 +16,7 @@
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
+#include <asm/system_info.h>
 #include <asm/hardware/dec21285.h>
 #include <mach/hardware.h>
 
diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c
index f551356..658a36d 100644
--- a/drivers/watchdog/wdt285.c
+++ b/drivers/watchdog/wdt285.c
@@ -32,6 +32,7 @@
 #include <mach/hardware.h>
 
 #include <asm/mach-types.h>
+#include <asm/system_info.h>
 #include <asm/hardware/dec21285.h>
 
 /*
diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h
index 94e924e..d9072d9 100644
--- a/include/linux/mtd/map.h
+++ b/include/linux/mtd/map.h
@@ -1,4 +1,4 @@
-/*
+ r/*
  * Copyright ? 2000-2010 David Woodhouse <dwmw2 at infradead.org> et al.
  *
  * This program is free software; you can redistribute it and/or modify



From arnd at arndb.de  Thu Mar 15 16:58:30 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 15 Mar 2012 20:58:30 +0000
Subject: [PATCH 0/5] MMC: mmci: Provide bindings for Device Tree
In-Reply-To: <CAFEEs1=TJaCYmaWd7zd28NsV8ubZBpBn7p=Mi7vGtmV_vpfh1w@mail.gmail.com>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <201203151532.44363.arnd@arndb.de>
 <CAFEEs1=TJaCYmaWd7zd28NsV8ubZBpBn7p=Mi7vGtmV_vpfh1w@mail.gmail.com>
Message-ID: <201203152058.31398.arnd@arndb.de>

On Thursday 15 March 2012, Per Forlin wrote:
> On Thu, Mar 15, 2012 at 4:32 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Thursday 15 March 2012, Lee Jones wrote:
> >> > I would like to see what the minimal required change is to support DT
> >> > for mmci without factorization.
> >> > 1. Minimal change in mmci.
> >> > 2. Add mmci_dt.c which contains the DT-populate code.
> >> >
> >> > The factorization could be done as step 2 I think.
> >> >
> >> > What do you say?
> >>
> >> I'm wondering what the difference is as the work has already been done.
> >>
> >> It was Arnd's suggestion to separate out the two types of variants, and
> >> I'm quite fond of the new (fully featured) layout.
> >
> > Right, I usually prefer cleanups or other refactoring to be done first, and
> > then features added on top.
> >
> > You could in theory add have just patches 3/4/5 all applied without
> > the refactoring, but that I would be worried that this causes dependencies
> > between the mmci driver and ux500 specific functionality like the
> > stedma40_filter function.
> >
> About DT
> I think I need to catch up on the DT-design a bit. I will try to catch
> up on the DT-implementation and maybe then the refactorization will
> make sense to me :)
> 
> Board specific data in mmci-driver
> The stedma40 filter function is not really specific for ux500. ux500
> use stedma40 but it should be possible to replace this DMA.IP with
> some other DMA-controller. This is board specific configuration. You
> should not need to change the mmci-driver just because the dma-driver
> has changed, right?
> Or will the board-configuration now be placed in mmci-ux500?

Right, the DMA configuration does not really belong in there, but
the voltage setup might (unless we convert that to the regulator
setup).

> Common DT populate code for all mmc host drivers
> Some parts of the DT-population is common for all the host driver, for
> instance setting the CAP and CAP2. This code should be moved to a
> common place to be used by other host drivers as well.

Good idea, yes. We should also have a generic mmc binding document
that describes how to set flags like 8-bit mode. We already have
two conflicting variants in .dts files and we should make sure
we bring everybody back together here.

> About refactoring
> There are numbers of patches stashed up for MMCI waiting for verdict
> here http://git.kernel.org/?p=linux/kernel/git/linusw/linux-stericsson.git;a=shortlog;h=refs/heads/mmci.
> If doing a refactorization please rebase it on top of these patches.
> This needs to be done carefully, there may be more to considerations
> than just DT. Maybe the timing is better to do this for 4.5, just
> after 4.4 is closed. Then we can make sure that all new patches are
> made on top of the refactorized base.

Yes, thanks for the info. Doing this for 3.4 is definitely out of the
question then, and hopefully we can use the new dma bindings when it's
done for 3.5

	Arnd


From rjw at sisk.pl  Thu Mar 15 17:19:22 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Thu, 15 Mar 2012 22:19:22 +0100
Subject: [PATCH 10/10] ARM: OMAP: SmartReflex: Move smartreflex driver to
 drivers/
In-Reply-To: <1331829845-9526-11-git-send-email-j-pihet@ti.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
 <1331829845-9526-11-git-send-email-j-pihet@ti.com>
Message-ID: <201203152219.22985.rjw@sisk.pl>

On Thursday, March 15, 2012, jean.pihet at newoldbits.com wrote:
> From: Jean Pihet <j-pihet at ti.com>
> 
> After a clean-up of the interfaces the OMAP IP driver and class
> support code is now a generic driver.
> Move it to drivers/power/avs/.
> 
> The build is controlled by the following Kconfig options:
>  . CONFIG_POWER_AVS: general knob for Adaptive Voltage Scaling support,
>  . CONFIG_POWER_AVS_OMAP: AVS support on OMAP containing the version 1
>     or version 2 of the SmartReflex IP,
>  . CONFIG_POWER_AVS_OMAP_CLASS3: Class 3 implementation of Smartreflex.
> 
> Signed-off-by: Jean Pihet <j-pihet at ti.com>
> ---
[...]
> diff --git a/drivers/power/Makefile b/drivers/power/Makefile
> index e429008..e4a8fd2 100644
> --- a/drivers/power/Makefile
> +++ b/drivers/power/Makefile
> @@ -41,3 +41,5 @@ obj-$(CONFIG_CHARGER_GPIO)	+= gpio-charger.o
>  obj-$(CONFIG_CHARGER_MANAGER)	+= charger-manager.o
>  obj-$(CONFIG_CHARGER_MAX8997)	+= max8997_charger.o
>  obj-$(CONFIG_CHARGER_MAX8998)	+= max8998_charger.o
> +
> +obj-$(CONFIG_POWER_AVS)		+= avs/
> diff --git a/drivers/power/avs/Kconfig b/drivers/power/avs/Kconfig
> new file mode 100644
> index 0000000..35b21c4
> --- /dev/null
> +++ b/drivers/power/avs/Kconfig
> @@ -0,0 +1,45 @@
> +menuconfig POWER_AVS
> +	tristate "Adaptive Voltage Scaling class support"
> +	help
> +	  AVS is a power management technique which finely controls the
> +	  operating voltage of a device in order to optimize (i.e. reduce)
> +	  its power consumption.
> +	  At a given operating point the voltage is adapted depending on
> +	  static factors (chip manufacturing process) and dynamic factors
> +	  (temperature depending performance).
> +	  AVS is also called SmartReflex on OMAP devices.
> +
> +	  Say Y here to enable Adaptive Voltage Scaling class support.
> +
> +if POWER_AVS
> +
> +config POWER_AVS_OMAP

I think it would be better to keep this and the next one in the OMAP
arch Kconfig.

> +	bool "AVS support for the OMAP IP versions 1&2"
> +	depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
> +	help
> +	  Say Y to enable AVS support on OMAP containing the version 1 or
> +	  version 2 of the SmartReflex IP.
> +	  V1 is the 65nm version used in OMAP3430.
> +	  V2 is the update for the 45nm version of the IP used in OMAP3630
> +	  and OMAP4430
> +
> +	  Please note, that by default SmartReflex is only
> +	  initialized and not enabled. To enable the automatic voltage
> +	  compensation for vdd mpu and vdd core from user space,
> +	  user must write 1 to
> +		/debug/smartreflex/sr_<X>/autocomp,
> +	  where X is mpu_iva or core for OMAP3.
> +	  Optionally autocompensation can be enabled in the kernel
> +	  by default during system init via the enable_on_init flag
> +	  which an be passed as platform data to the smartreflex driver.
> +
> +config POWER_AVS_OMAP_CLASS3
> +	bool "Class 3 mode of Smartreflex Implementation"
> +	depends on POWER_AVS_OMAP && TWL4030_CORE
> +	help
> +	  Say Y to enable Class 3 implementation of Smartreflex
> +
> +	  Class 3 implementation of Smartreflex employs continuous hardware
> +	  voltage calibration.
> +
> +endif # POWER_AVS

Thanks,
Rafael


From dhowells at redhat.com  Thu Mar 15 17:26:19 2012
From: dhowells at redhat.com (David Howells)
Date: Thu, 15 Mar 2012 21:26:19 +0000
Subject: [PATCH] Fixes after disintegration of asm/system.h for ARM
Message-ID: <20120315212619.31098.94700.stgit@warthog.procyon.org.uk>

Signed-off-by: David Howells <dhowells at redhat.com>
cc: Russell King <linux at arm.linux.org.uk>
cc: linux-arm-kernel at lists.infradead.org
---

 arch/arm/include/asm/barrier.h               |    6 ++++++
 arch/arm/include/asm/domain.h                |    2 ++
 arch/arm/include/asm/io.h                    |    1 +
 arch/arm/include/asm/processor.h             |    1 -
 arch/arm/include/asm/system_misc.h           |    5 -----
 arch/arm/kernel/kprobes-common.c             |    1 +
 arch/arm/kernel/machine_kexec.c              |    1 +
 arch/arm/kernel/tcm.c                        |    1 +
 arch/arm/kernel/thumbee.c                    |    1 +
 arch/arm/mach-at91/at91cap9.c                |    2 ++
 arch/arm/mach-at91/at91rm9200.c              |    1 +
 arch/arm/mach-at91/at91sam9260.c             |    1 +
 arch/arm/mach-at91/at91sam9261.c             |    1 +
 arch/arm/mach-at91/at91sam9263.c             |    1 +
 arch/arm/mach-at91/at91sam9g45.c             |    1 +
 arch/arm/mach-at91/at91sam9rl.c              |    1 +
 arch/arm/mach-at91/include/mach/system_rev.h |    2 ++
 arch/arm/mach-clps711x/common.c              |    1 +
 arch/arm/mach-davinci/board-da850-evm.c      |    1 +
 arch/arm/mach-ebsa110/core.c                 |    1 +
 arch/arm/mach-footbridge/common.c            |    1 +
 arch/arm/mach-footbridge/dc21285-timer.c     |    1 +
 arch/arm/mach-footbridge/netwinder-hw.c      |    1 +
 arch/arm/mach-imx/mach-imx6q.c               |    1 +
 arch/arm/mach-imx/mach-mx51_efikamx.c        |    1 +
 arch/arm/mach-imx/mach-mx51_efikasb.c        |    1 +
 arch/arm/mach-ks8695/time.c                  |    1 +
 arch/arm/mach-mmp/common.c                   |    1 +
 arch/arm/mach-mmp/pxa168.c                   |    1 +
 arch/arm/mach-mxs/system.c                   |    1 +
 arch/arm/mach-omap1/id.c                     |    1 +
 arch/arm/mach-omap2/board-omap3touchbook.c   |    1 +
 arch/arm/mach-omap2/board-rx51-peripherals.c |    1 +
 arch/arm/mach-omap2/pm24xx.c                 |    1 +
 arch/arm/mach-omap2/pm34xx.c                 |    1 +
 arch/arm/mach-omap2/pm44xx.c                 |    1 +
 arch/arm/mach-orion5x/common.c               |    1 +
 arch/arm/mach-orion5x/dns323-setup.c         |    1 +
 arch/arm/mach-pnx4008/core.c                 |    1 +
 arch/arm/mach-pxa/cm-x300.c                  |    1 +
 arch/arm/mach-pxa/colibri-pxa3xx.c           |    1 +
 arch/arm/mach-pxa/magician.c                 |    1 +
 arch/arm/mach-pxa/reset.c                    |    1 +
 arch/arm/mach-pxa/viper.c                    |    1 +
 arch/arm/mach-pxa/zeus.c                     |    1 +
 arch/arm/mach-rpc/riscpc.c                   |    1 +
 arch/arm/mach-s3c2410/s3c2410.c              |    1 +
 arch/arm/mach-s3c2412/s3c2412.c              |    1 +
 arch/arm/mach-s3c2416/s3c2416.c              |    1 +
 arch/arm/mach-s3c2440/s3c244x.c              |    1 +
 arch/arm/mach-s3c2443/s3c2443.c              |    1 +
 arch/arm/mach-s3c64xx/common.c               |    1 +
 arch/arm/mach-s5p64x0/common.c               |    1 +
 arch/arm/mach-s5pc100/common.c               |    1 +
 arch/arm/mach-sa1100/generic.c               |    1 +
 arch/arm/mach-shmobile/include/mach/system.h |    2 ++
 arch/arm/mach-shmobile/suspend.c             |    1 +
 arch/arm/mach-w90x900/cpu.c                  |    1 +
 arch/arm/mm/alignment.c                      |    1 +
 arch/arm/mm/fault.c                          |    2 ++
 arch/arm/mm/mmu.c                            |    1 +
 arch/arm/plat-iop/restart.c                  |    1 +
 arch/arm/plat-mxc/system.c                   |    1 +
 arch/arm/plat-s3c24xx/cpu.c                  |    1 +
 arch/arm/plat-spear/restart.c                |    1 +
 arch/arm/vfp/vfpmodule.c                     |    1 +
 drivers/cpuidle/cpuidle.c                    |    1 +
 drivers/net/ethernet/8390/etherh.c           |    1 +
 drivers/tty/serial/21285.c                   |    1 +
 drivers/watchdog/wdt285.c                    |    1 +
 include/linux/mtd/map.h                      |    2 +-
 71 files changed, 79 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 81b24b6..408e392 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -1,6 +1,11 @@
 #ifndef __ASM_BARRIER_H
 #define __ASM_BARRIER_H
 
+#ifdef __ASSEMBLY__
+#error do not include asm/barrier.h from assembly
+#endif
+
+#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
 #if __LINUX_ARM_ARCH__ >= 7 ||		\
 	(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
@@ -36,6 +41,7 @@
 #ifdef CONFIG_ARCH_HAS_BARRIERS
 #include <mach/barriers.h>
 #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
+#include <asm/outercache.h>
 #define mb()		do { dsb(); outer_sync(); } while (0)
 #define rmb()		dsb()
 #define wmb()		mb()
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index 489f160..3d22204 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -10,7 +10,9 @@
 #ifndef __ASM_PROC_DOMAIN_H
 #define __ASM_PROC_DOMAIN_H
 
+#ifndef __ASSEMBLY__
 #include <asm/barrier.h>
+#endif
 
 /*
  * Domain numbers
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 0a34bf7..bae7eb6 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -98,6 +98,7 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 
 /* IO barriers */
 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
+#include <asm/barrier.h>
 #define __iormb()		rmb()
 #define __iowmb()		wmb()
 #else
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index cb8d638..ce280b8 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -22,7 +22,6 @@
 #include <asm/hw_breakpoint.h>
 #include <asm/ptrace.h>
 #include <asm/types.h>
-#include <asm/system.h>
 
 #ifdef __KERNEL__
 #define STACK_TOP	((current->personality & ADDR_LIMIT_32BIT) ? \
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index f5cf1e8..ccda6c2 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -7,9 +7,6 @@
 #include <linux/linkage.h>
 #include <linux/irqflags.h>
 
-#include <asm/outercache.h>
-
-extern int __pure cpu_architecture(void);
 extern void cpu_init(void);
 
 void soft_restart(unsigned long);
@@ -23,8 +20,6 @@ extern void (*arm_pm_restart)(char str, const char *cmd);
 
 extern unsigned int user_debug;
 
-#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
-
 extern void disable_hlt(void);
 extern void enable_hlt(void);
 
diff --git a/arch/arm/kernel/kprobes-common.c b/arch/arm/kernel/kprobes-common.c
index a5394fb4..18a7628 100644
--- a/arch/arm/kernel/kprobes-common.c
+++ b/arch/arm/kernel/kprobes-common.c
@@ -13,6 +13,7 @@
 
 #include <linux/kernel.h>
 #include <linux/kprobes.h>
+#include <asm/system_info.h>
 
 #include "kprobes.h"
 
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index e097865..5699598 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -12,6 +12,7 @@
 #include <asm/mmu_context.h>
 #include <asm/cacheflush.h>
 #include <asm/mach-types.h>
+#include <asm/system_misc.h>
 
 extern const unsigned char relocate_new_kernel[];
 extern const unsigned int relocate_new_kernel_size;
diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
index 01ec453..30ae6bb 100644
--- a/arch/arm/kernel/tcm.c
+++ b/arch/arm/kernel/tcm.c
@@ -16,6 +16,7 @@
 #include <asm/cputype.h>
 #include <asm/mach/map.h>
 #include <asm/memory.h>
+#include <asm/system_info.h>
 #include "tcm.h"
 
 static struct gen_pool *tcm_pool;
diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c
index 9cb7aac..37bc322 100644
--- a/arch/arm/kernel/thumbee.c
+++ b/arch/arm/kernel/thumbee.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 
 #include <asm/thread_notify.h>
+#include <asm/system_info.h>
 
 /*
  * Access to the ThumbEE Handler Base register
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index a42edc2..fc460e9 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -17,6 +17,8 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
+#include <asm/system_misc.h>
 
 #include <mach/cpu.h>
 #include <mach/at91cap9.h>
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 99c3174..413c027 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/at91rm9200.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_st.h>
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index d4036ba..79f5718 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9260.h>
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 023c2ff..62818b9 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91_pmc.h>
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 75e876c..722ee08 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/at91sam9263.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 1cb6a96..47e8fdb 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -16,6 +16,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index d2c91a8..7ae4993 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -14,6 +14,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9rl.h>
diff --git a/arch/arm/mach-at91/include/mach/system_rev.h b/arch/arm/mach-at91/include/mach/system_rev.h
index ec164a4..ef79a9a 100644
--- a/arch/arm/mach-at91/include/mach/system_rev.h
+++ b/arch/arm/mach-at91/include/mach/system_rev.h
@@ -7,6 +7,8 @@
 #ifndef __ARCH_SYSTEM_REV_H__
 #define __ARCH_SYSTEM_REV_H__
 
+#include <asm/system_info.h>
+
 /*
  * board revision encoding
  * mach specific
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index ab1711b..ac84f92 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -37,6 +37,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/clps7111.h>
+#include <asm/system_misc.h>
 
 /*
  * This maps the generic CLPS711x registers
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index d508890..5d9afd8 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -34,6 +34,7 @@
 #include <linux/delay.h>
 #include <linux/wl12xx.h>
 
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index e43dcc0..0c40e59 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -22,6 +22,7 @@
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 41978ee..3e6aaa6 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -21,6 +21,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/dec21285.h>
 
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index 121ad1d..3b54196 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -14,6 +14,7 @@
 
 #include <asm/hardware/dec21285.h>
 #include <asm/mach/time.h>
+#include <asm/system_info.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 80a1c5c..cac9f67 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -17,6 +17,7 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index c257281..527b697 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -21,6 +21,7 @@
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
index 3a5ed2d..586e9f8 100644
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ b/arch/arm/mach-imx/mach-mx51_efikamx.c
@@ -33,6 +33,7 @@
 #include <mach/iomux-mx51.h>
 
 #include <asm/setup.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
index ea5f65b..24aded9 100644
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ b/arch/arm/mach-imx/mach-mx51_efikasb.c
@@ -36,6 +36,7 @@
 #include <mach/iomux-mx51.h>
 
 #include <asm/setup.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 37dfcd5..ec783a3 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -27,6 +27,7 @@
 #include <linux/io.h>
 
 #include <asm/mach/time.h>
+#include <asm/system_misc.h>
 
 #include <mach/regs-timer.h>
 #include <mach/regs-irq.h>
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 062b5b9..c868a6c 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 
 #include <asm/page.h>
+#include <asm/system_misc.h>
 #include <asm/mach/map.h>
 #include <mach/addr-map.h>
 #include <mach/cputype.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index ada1213..d5c9a2e 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/platform_device.h>
 
+#include <asm/system_misc.h>
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/cputype.h>
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 32fe638..30042e2 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -25,6 +25,7 @@
 #include <linux/module.h>
 
 #include <asm/proc-fns.h>
+#include <asm/system_misc.h>
 
 #include <mach/mxs.h>
 #include <mach/common.h>
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index a0e3560..b3f3363 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <asm/system_info.h>
 #include <plat/cpu.h>
 
 #define OMAP_DIE_ID_0		0xfffe1800
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index a0b851a..c524c9d 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -38,6 +38,7 @@
 #include <linux/i2c/twl.h>
 
 #include <mach/hardware.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index acb4e77..2bf84fd 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -25,6 +25,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/mmc/host.h>
 #include <linux/power/isp1704_charger.h>
+#include <asm/system_info.h>
 
 #include <plat/mcspi.h>
 #include <plat/board.h>
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 23de98d..730bb00 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -34,6 +34,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 #include <asm/mach-types.h>
+#include <asm/system_misc.h>
 
 #include <mach/irqs.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc69875..64d95e6 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -31,6 +31,7 @@
 #include <trace/events/power.h>
 
 #include <asm/suspend.h>
+#include <asm/system_misc.h>
 
 #include <plat/sram.h>
 #include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index c264ef7..a73e325 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -16,6 +16,7 @@
 #include <linux/list.h>
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <asm/system_misc.h>
 
 #include "common.h"
 #include "clockdomain.h"
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 5dad38e..2448166 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -21,6 +21,7 @@
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 #include <asm/timex.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 91b0f47..f4f6ad2d 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -29,6 +29,7 @@
 #include <linux/ata_platform.h>
 #include <linux/phy.h>
 #include <linux/marvell_phy.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index 977538f..be4c928 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -32,6 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 4b981b8..125ae08 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -55,6 +55,7 @@
 #include <mach/pxa3xx-u2d.h>
 
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
index 2b8ca0d..2075a69 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -20,6 +20,7 @@
 #include <asm/sizes.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
+#include <asm/system_info.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/mfp-pxa300.h>
 #include <mach/colibri.h>
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 3d6baf9..264cd89 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -31,6 +31,7 @@
 #include <linux/i2c/pxa-i2c.h>
 
 #include <mach/hardware.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index c8497b0..b452889 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -9,6 +9,7 @@
 #include <linux/gpio.h>
 #include <linux/io.h>
 #include <asm/proc-fns.h>
+#include <asm/system_misc.h>
 
 #include <mach/regs-ost.h>
 #include <mach/reset.h>
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 023d6ca..7a3d342 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -57,6 +57,7 @@
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
+#include <asm/system_info.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index a4dd1c3..4c5ae58 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -34,6 +34,7 @@
 #include <asm/suspend.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
 
 #include <mach/pxa27x.h>
 #include <mach/regs-uart.h>
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index 3d44a59..e958597 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -28,6 +28,7 @@
 #include <asm/page.h>
 #include <asm/domain.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 061b6bb..a3c5cb0 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -30,6 +30,7 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <plat/cpu-freq.h>
 
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index aff6e85..100ef1c 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -31,6 +31,7 @@
 #include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/idle.h>
 
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 5287d28..ed67ec9 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -43,6 +43,7 @@
 #include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/idle.h>
 #include <mach/regs-s3c2443-clock.h>
diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c
index d15852f..6f74118 100644
--- a/arch/arm/mach-s3c2440/s3c244x.c
+++ b/arch/arm/mach-s3c2440/s3c244x.c
@@ -23,6 +23,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
+#include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index b9deaeb..9318847 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -29,6 +29,7 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/regs-s3c2443-clock.h>
 
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index bee7dcd..b313380 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -29,6 +29,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/vic.h>
+#include <asm/system_misc.h>
 
 #include <mach/map.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 52b89a3..a9d1ad4 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -30,6 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/map.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index c909573..dff11c3 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -30,6 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/map.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 17caece..9ad9469 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -24,6 +24,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
index 956ac18..9204270 100644
--- a/arch/arm/mach-shmobile/include/mach/system.h
+++ b/arch/arm/mach-shmobile/include/mach/system.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
+#include <asm/system_misc.h>
+
 static inline void arch_idle(void)
 {
 	cpu_do_idle();
diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
index 12d760c..4d1b86a 100644
--- a/arch/arm/mach-shmobile/suspend.c
+++ b/arch/arm/mach-shmobile/suspend.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 #include <linux/err.h>
 #include <asm/io.h>
+#include <asm/system_misc.h>
 
 static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
 {
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 9a06619..9e4dd8b 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -28,6 +28,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-serial.h>
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 9107231..8b05694 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -25,6 +25,7 @@
 #include <asm/cp15.h>
 #include <asm/system_info.h>
 #include <asm/unaligned.h>
+#include <asm/system_info.h>
 
 #include "fault.h"
 
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 5bdff5c..5a0a0b7 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -25,6 +25,8 @@
 #include <asm/system_misc.h>
 #include <asm/system_info.h>
 #include <asm/tlbflush.h>
+#include <asm/system_misc.h>
+#include <asm/system_info.h>
 
 #include "fault.h"
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index cd439c1..a27555a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -28,6 +28,7 @@
 #include <asm/highmem.h>
 #include <asm/system_info.h>
 #include <asm/traps.h>
+#include <asm/system_info.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
index 6a85a0c..33fa699 100644
--- a/arch/arm/plat-iop/restart.c
+++ b/arch/arm/plat-iop/restart.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <asm/hardware/iop3xx.h>
+#include <asm/system_misc.h>
 #include <mach/hardware.h>
 
 void iop3xx_restart(char mode, const char *cmd)
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 8f12074..c195d6d 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -25,6 +25,7 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
+#include <asm/system_misc.h>
 #include <asm/proc-fns.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 21f1fda..ded6431 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -34,6 +34,7 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/cacheflush.h>
+#include <asm/system_info.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 2b4e3d8..16f203e 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -11,6 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 #include <linux/io.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/sp810.h>
 #include <mach/hardware.h>
 #include <mach/generic.h>
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index d89068f..9f50997 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -22,6 +22,7 @@
 #include <asm/cputype.h>
 #include <asm/thread_notify.h>
 #include <asm/vfp.h>
+#include <asm/system_info.h>
 
 #include "vfpinstr.h"
 #include "vfp.h"
diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index 59f4261..654076e 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -19,6 +19,7 @@
 #include <linux/hrtimer.h>
 #include <linux/module.h>
 #include <trace/events/power.h>
+#include <asm/system_misc.h>
 
 #include "cpuidle.h"
 
diff --git a/drivers/net/ethernet/8390/etherh.c b/drivers/net/ethernet/8390/etherh.c
index 48c4948..a45b0d8 100644
--- a/drivers/net/ethernet/8390/etherh.c
+++ b/drivers/net/ethernet/8390/etherh.c
@@ -48,6 +48,7 @@
 #include <asm/system.h>
 #include <asm/ecard.h>
 #include <asm/io.h>
+#include <asm/system_info.h>
 
 #define EI_SHIFT(x)	(ei_local->reg_offset[x])
 
diff --git a/drivers/tty/serial/21285.c b/drivers/tty/serial/21285.c
index 1b37626..6d0ddbc 100644
--- a/drivers/tty/serial/21285.c
+++ b/drivers/tty/serial/21285.c
@@ -16,6 +16,7 @@
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
+#include <asm/system_info.h>
 #include <asm/hardware/dec21285.h>
 #include <mach/hardware.h>
 
diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c
index f551356..658a36d 100644
--- a/drivers/watchdog/wdt285.c
+++ b/drivers/watchdog/wdt285.c
@@ -32,6 +32,7 @@
 #include <mach/hardware.h>
 
 #include <asm/mach-types.h>
+#include <asm/system_info.h>
 #include <asm/hardware/dec21285.h>
 
 /*
diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h
index 94e924e..d9072d9 100644
--- a/include/linux/mtd/map.h
+++ b/include/linux/mtd/map.h
@@ -1,4 +1,4 @@
-/*
+ r/*
  * Copyright ? 2000-2010 David Woodhouse <dwmw2 at infradead.org> et al.
  *
  * This program is free software; you can redistribute it and/or modify



From rjw at sisk.pl  Thu Mar 15 17:36:27 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Thu, 15 Mar 2012 22:36:27 +0100
Subject: linux-next: manual merge of the arm-soc tree with Linus' tree
In-Reply-To: <201203152001.12353.arnd@arndb.de>
References: <20120315175000.897f1172c296d4a687be0537@canb.auug.org.au>
 <1362815.uO65s14ojU@avalon> <201203152001.12353.arnd@arndb.de>
Message-ID: <201203152236.27977.rjw@sisk.pl>

On Thursday, March 15, 2012, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Laurent Pinchart wrote:
> > The following patch (5d7220ec000f rebased on top of 1740d3448012) shows the
> > correct conflict resolution in my opinion.
> > 
> > From f040ba69632a54c86767974768d68b308901061c Mon Sep 17 00:00:00 2001
> > From: Magnus Damm <damm at opensource.se>
> > Date: Wed, 29 Feb 2012 12:37:19 +0900
> > Subject: [PATCH] ARM: mach-shmobile: sh7372 map_io and init_early update
> > 
> > ARM: mach-shmobile: sh7372 map_io and init_early update
> > 
> > Update the sh7372 SoC and the AP4EVB and Mackerel boards to make use
> > of the functions sh7372_map_io() and sh7372_add_early_devices().
> > 
> > Signed-off-by: Magnus Damm <damm at opensource.se>
> > Signed-off-by: Rafael J. Wysocki <rjw at sisk.pl>
> > Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> 
> Hi Laurent,
> 
> I've merged Paul's branch into my renesas/soc branch, because I don't
> rebase the branches once they are merged into arm-soc. Thanks a lot
> for the resolution you suggested, I used the same resulting code
> in the merge commit.
> 
> I'm not particularly happy about how we got here. Obviously, the bug
> fixes that Paul sent should have gone through the arm-soc tree to
> avoid this situation, and they should have been based on a -rc release
> rather than some random commit after -rc6. It's not a big issue
> because the next/soc branch already contains -rc7 though.

This is a consequece of our decision that Paul would handle v3.3 fixes
and push them directly to Linus, while I would take new material for v3.4,
sorry about that.

It should be a temporary problem only, though, because once v3.3 has been
released, all arm/mach-shmobile fixes will go through the arm-soc tree.

Thanks,
Rafael


From dhowells at redhat.com  Thu Mar 15 17:33:45 2012
From: dhowells at redhat.com (David Howells)
Date: Thu, 15 Mar 2012 21:33:45 +0000
Subject: [PATCH] Fixes after disintegration of asm/system.h for ARM [ver #2]
Message-ID: <20120315213345.31434.26037.stgit@warthog.procyon.org.uk>

Signed-off-by: David Howells <dhowells at redhat.com>
cc: Russell King <linux at arm.linux.org.uk>
cc: linux-arm-kernel at lists.infradead.org
---

 arch/arm/include/asm/barrier.h               |    6 ++++++
 arch/arm/include/asm/domain.h                |    2 ++
 arch/arm/include/asm/io.h                    |    1 +
 arch/arm/include/asm/processor.h             |    1 -
 arch/arm/include/asm/system_misc.h           |    5 -----
 arch/arm/kernel/kprobes-common.c             |    1 +
 arch/arm/kernel/machine_kexec.c              |    1 +
 arch/arm/kernel/tcm.c                        |    1 +
 arch/arm/kernel/thumbee.c                    |    1 +
 arch/arm/mach-at91/at91cap9.c                |    2 ++
 arch/arm/mach-at91/at91rm9200.c              |    1 +
 arch/arm/mach-at91/at91sam9260.c             |    1 +
 arch/arm/mach-at91/at91sam9261.c             |    1 +
 arch/arm/mach-at91/at91sam9263.c             |    1 +
 arch/arm/mach-at91/at91sam9g45.c             |    1 +
 arch/arm/mach-at91/at91sam9rl.c              |    1 +
 arch/arm/mach-at91/include/mach/system_rev.h |    2 ++
 arch/arm/mach-clps711x/common.c              |    1 +
 arch/arm/mach-davinci/board-da850-evm.c      |    1 +
 arch/arm/mach-ebsa110/core.c                 |    1 +
 arch/arm/mach-footbridge/common.c            |    1 +
 arch/arm/mach-footbridge/dc21285-timer.c     |    1 +
 arch/arm/mach-footbridge/netwinder-hw.c      |    1 +
 arch/arm/mach-imx/mach-imx6q.c               |    1 +
 arch/arm/mach-imx/mach-mx51_efikamx.c        |    1 +
 arch/arm/mach-imx/mach-mx51_efikasb.c        |    1 +
 arch/arm/mach-ks8695/time.c                  |    1 +
 arch/arm/mach-mmp/common.c                   |    1 +
 arch/arm/mach-mmp/pxa168.c                   |    1 +
 arch/arm/mach-mxs/system.c                   |    1 +
 arch/arm/mach-omap1/id.c                     |    1 +
 arch/arm/mach-omap2/board-omap3touchbook.c   |    1 +
 arch/arm/mach-omap2/board-rx51-peripherals.c |    1 +
 arch/arm/mach-omap2/pm24xx.c                 |    1 +
 arch/arm/mach-omap2/pm34xx.c                 |    1 +
 arch/arm/mach-omap2/pm44xx.c                 |    1 +
 arch/arm/mach-orion5x/common.c               |    1 +
 arch/arm/mach-orion5x/dns323-setup.c         |    1 +
 arch/arm/mach-pnx4008/core.c                 |    1 +
 arch/arm/mach-pxa/cm-x300.c                  |    1 +
 arch/arm/mach-pxa/colibri-pxa3xx.c           |    1 +
 arch/arm/mach-pxa/magician.c                 |    1 +
 arch/arm/mach-pxa/reset.c                    |    1 +
 arch/arm/mach-pxa/viper.c                    |    1 +
 arch/arm/mach-pxa/zeus.c                     |    1 +
 arch/arm/mach-rpc/riscpc.c                   |    1 +
 arch/arm/mach-s3c2410/s3c2410.c              |    1 +
 arch/arm/mach-s3c2412/s3c2412.c              |    1 +
 arch/arm/mach-s3c2416/s3c2416.c              |    1 +
 arch/arm/mach-s3c2440/s3c244x.c              |    1 +
 arch/arm/mach-s3c2443/s3c2443.c              |    1 +
 arch/arm/mach-s3c64xx/common.c               |    1 +
 arch/arm/mach-s5p64x0/common.c               |    1 +
 arch/arm/mach-s5pc100/common.c               |    1 +
 arch/arm/mach-sa1100/generic.c               |    1 +
 arch/arm/mach-shmobile/include/mach/system.h |    2 ++
 arch/arm/mach-shmobile/suspend.c             |    1 +
 arch/arm/mach-w90x900/cpu.c                  |    1 +
 arch/arm/mm/alignment.c                      |    1 +
 arch/arm/mm/fault.c                          |    2 ++
 arch/arm/mm/mmu.c                            |    1 +
 arch/arm/plat-iop/restart.c                  |    1 +
 arch/arm/plat-mxc/system.c                   |    1 +
 arch/arm/plat-s3c24xx/cpu.c                  |    1 +
 arch/arm/plat-spear/restart.c                |    1 +
 arch/arm/vfp/vfpmodule.c                     |    1 +
 drivers/cpuidle/cpuidle.c                    |    1 +
 drivers/net/ethernet/8390/etherh.c           |    1 +
 drivers/tty/serial/21285.c                   |    1 +
 drivers/watchdog/wdt285.c                    |    1 +
 70 files changed, 78 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 81b24b6..408e392 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -1,6 +1,11 @@
 #ifndef __ASM_BARRIER_H
 #define __ASM_BARRIER_H
 
+#ifdef __ASSEMBLY__
+#error do not include asm/barrier.h from assembly
+#endif
+
+#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
 #if __LINUX_ARM_ARCH__ >= 7 ||		\
 	(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
@@ -36,6 +41,7 @@
 #ifdef CONFIG_ARCH_HAS_BARRIERS
 #include <mach/barriers.h>
 #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
+#include <asm/outercache.h>
 #define mb()		do { dsb(); outer_sync(); } while (0)
 #define rmb()		dsb()
 #define wmb()		mb()
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index 489f160..3d22204 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -10,7 +10,9 @@
 #ifndef __ASM_PROC_DOMAIN_H
 #define __ASM_PROC_DOMAIN_H
 
+#ifndef __ASSEMBLY__
 #include <asm/barrier.h>
+#endif
 
 /*
  * Domain numbers
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 0a34bf7..bae7eb6 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -98,6 +98,7 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 
 /* IO barriers */
 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
+#include <asm/barrier.h>
 #define __iormb()		rmb()
 #define __iowmb()		wmb()
 #else
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index cb8d638..ce280b8 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -22,7 +22,6 @@
 #include <asm/hw_breakpoint.h>
 #include <asm/ptrace.h>
 #include <asm/types.h>
-#include <asm/system.h>
 
 #ifdef __KERNEL__
 #define STACK_TOP	((current->personality & ADDR_LIMIT_32BIT) ? \
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index f5cf1e8..ccda6c2 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -7,9 +7,6 @@
 #include <linux/linkage.h>
 #include <linux/irqflags.h>
 
-#include <asm/outercache.h>
-
-extern int __pure cpu_architecture(void);
 extern void cpu_init(void);
 
 void soft_restart(unsigned long);
@@ -23,8 +20,6 @@ extern void (*arm_pm_restart)(char str, const char *cmd);
 
 extern unsigned int user_debug;
 
-#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
-
 extern void disable_hlt(void);
 extern void enable_hlt(void);
 
diff --git a/arch/arm/kernel/kprobes-common.c b/arch/arm/kernel/kprobes-common.c
index a5394fb4..18a7628 100644
--- a/arch/arm/kernel/kprobes-common.c
+++ b/arch/arm/kernel/kprobes-common.c
@@ -13,6 +13,7 @@
 
 #include <linux/kernel.h>
 #include <linux/kprobes.h>
+#include <asm/system_info.h>
 
 #include "kprobes.h"
 
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index e097865..5699598 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -12,6 +12,7 @@
 #include <asm/mmu_context.h>
 #include <asm/cacheflush.h>
 #include <asm/mach-types.h>
+#include <asm/system_misc.h>
 
 extern const unsigned char relocate_new_kernel[];
 extern const unsigned int relocate_new_kernel_size;
diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
index 01ec453..30ae6bb 100644
--- a/arch/arm/kernel/tcm.c
+++ b/arch/arm/kernel/tcm.c
@@ -16,6 +16,7 @@
 #include <asm/cputype.h>
 #include <asm/mach/map.h>
 #include <asm/memory.h>
+#include <asm/system_info.h>
 #include "tcm.h"
 
 static struct gen_pool *tcm_pool;
diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c
index 9cb7aac..37bc322 100644
--- a/arch/arm/kernel/thumbee.c
+++ b/arch/arm/kernel/thumbee.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 
 #include <asm/thread_notify.h>
+#include <asm/system_info.h>
 
 /*
  * Access to the ThumbEE Handler Base register
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index a42edc2..fc460e9 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -17,6 +17,8 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
+#include <asm/system_misc.h>
 
 #include <mach/cpu.h>
 #include <mach/at91cap9.h>
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 99c3174..413c027 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/at91rm9200.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_st.h>
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index d4036ba..79f5718 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9260.h>
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 023c2ff..62818b9 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91_pmc.h>
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 75e876c..722ee08 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -15,6 +15,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/at91sam9263.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 1cb6a96..47e8fdb 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -16,6 +16,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index d2c91a8..7ae4993 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -14,6 +14,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9rl.h>
diff --git a/arch/arm/mach-at91/include/mach/system_rev.h b/arch/arm/mach-at91/include/mach/system_rev.h
index ec164a4..ef79a9a 100644
--- a/arch/arm/mach-at91/include/mach/system_rev.h
+++ b/arch/arm/mach-at91/include/mach/system_rev.h
@@ -7,6 +7,8 @@
 #ifndef __ARCH_SYSTEM_REV_H__
 #define __ARCH_SYSTEM_REV_H__
 
+#include <asm/system_info.h>
+
 /*
  * board revision encoding
  * mach specific
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index ab1711b..ac84f92 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -37,6 +37,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/clps7111.h>
+#include <asm/system_misc.h>
 
 /*
  * This maps the generic CLPS711x registers
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index d508890..5d9afd8 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -34,6 +34,7 @@
 #include <linux/delay.h>
 #include <linux/wl12xx.h>
 
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index e43dcc0..0c40e59 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -22,6 +22,7 @@
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 41978ee..3e6aaa6 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -21,6 +21,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/dec21285.h>
 
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index 121ad1d..3b54196 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -14,6 +14,7 @@
 
 #include <asm/hardware/dec21285.h>
 #include <asm/mach/time.h>
+#include <asm/system_info.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 80a1c5c..cac9f67 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -17,6 +17,7 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index c257281..527b697 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -21,6 +21,7 @@
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
index 3a5ed2d..586e9f8 100644
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ b/arch/arm/mach-imx/mach-mx51_efikamx.c
@@ -33,6 +33,7 @@
 #include <mach/iomux-mx51.h>
 
 #include <asm/setup.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
index ea5f65b..24aded9 100644
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ b/arch/arm/mach-imx/mach-mx51_efikasb.c
@@ -36,6 +36,7 @@
 #include <mach/iomux-mx51.h>
 
 #include <asm/setup.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 37dfcd5..ec783a3 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -27,6 +27,7 @@
 #include <linux/io.h>
 
 #include <asm/mach/time.h>
+#include <asm/system_misc.h>
 
 #include <mach/regs-timer.h>
 #include <mach/regs-irq.h>
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 062b5b9..c868a6c 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 
 #include <asm/page.h>
+#include <asm/system_misc.h>
 #include <asm/mach/map.h>
 #include <mach/addr-map.h>
 #include <mach/cputype.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index ada1213..d5c9a2e 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -15,6 +15,7 @@
 #include <linux/clk.h>
 #include <linux/platform_device.h>
 
+#include <asm/system_misc.h>
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/cputype.h>
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 32fe638..30042e2 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -25,6 +25,7 @@
 #include <linux/module.h>
 
 #include <asm/proc-fns.h>
+#include <asm/system_misc.h>
 
 #include <mach/mxs.h>
 #include <mach/common.h>
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index a0e3560..b3f3363 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <asm/system_info.h>
 #include <plat/cpu.h>
 
 #define OMAP_DIE_ID_0		0xfffe1800
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index a0b851a..c524c9d 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -38,6 +38,7 @@
 #include <linux/i2c/twl.h>
 
 #include <mach/hardware.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index acb4e77..2bf84fd 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -25,6 +25,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/mmc/host.h>
 #include <linux/power/isp1704_charger.h>
+#include <asm/system_info.h>
 
 #include <plat/mcspi.h>
 #include <plat/board.h>
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 23de98d..730bb00 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -34,6 +34,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 #include <asm/mach-types.h>
+#include <asm/system_misc.h>
 
 #include <mach/irqs.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc69875..64d95e6 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -31,6 +31,7 @@
 #include <trace/events/power.h>
 
 #include <asm/suspend.h>
+#include <asm/system_misc.h>
 
 #include <plat/sram.h>
 #include "clockdomain.h"
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index c264ef7..a73e325 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -16,6 +16,7 @@
 #include <linux/list.h>
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <asm/system_misc.h>
 
 #include "common.h"
 #include "clockdomain.h"
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 5dad38e..2448166 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -21,6 +21,7 @@
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 #include <asm/timex.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 91b0f47..f4f6ad2d 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -29,6 +29,7 @@
 #include <linux/ata_platform.h>
 #include <linux/phy.h>
 #include <linux/marvell_phy.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index 977538f..be4c928 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -32,6 +32,7 @@
 #include <asm/mach-types.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 4b981b8..125ae08 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -55,6 +55,7 @@
 #include <mach/pxa3xx-u2d.h>
 
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
 
 #include "generic.h"
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
index 2b8ca0d..2075a69 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -20,6 +20,7 @@
 #include <asm/sizes.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
+#include <asm/system_info.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/mfp-pxa300.h>
 #include <mach/colibri.h>
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 3d6baf9..264cd89 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -31,6 +31,7 @@
 #include <linux/i2c/pxa-i2c.h>
 
 #include <mach/hardware.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index c8497b0..b452889 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -9,6 +9,7 @@
 #include <linux/gpio.h>
 #include <linux/io.h>
 #include <asm/proc-fns.h>
+#include <asm/system_misc.h>
 
 #include <mach/regs-ost.h>
 #include <mach/reset.h>
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 023d6ca..7a3d342 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -57,6 +57,7 @@
 #include <asm/mach-types.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
+#include <asm/system_info.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index a4dd1c3..4c5ae58 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -34,6 +34,7 @@
 #include <asm/suspend.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
 
 #include <mach/pxa27x.h>
 #include <mach/regs-uart.h>
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index 3d44a59..e958597 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -28,6 +28,7 @@
 #include <asm/page.h>
 #include <asm/domain.h>
 #include <asm/setup.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 061b6bb..a3c5cb0 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -30,6 +30,7 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <plat/cpu-freq.h>
 
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index aff6e85..100ef1c 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -31,6 +31,7 @@
 #include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/idle.h>
 
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 5287d28..ed67ec9 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -43,6 +43,7 @@
 #include <mach/hardware.h>
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/idle.h>
 #include <mach/regs-s3c2443-clock.h>
diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c
index d15852f..6f74118 100644
--- a/arch/arm/mach-s3c2440/s3c244x.c
+++ b/arch/arm/mach-s3c2440/s3c244x.c
@@ -23,6 +23,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
+#include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index b9deaeb..9318847 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -29,6 +29,7 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/regs-s3c2443-clock.h>
 
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index bee7dcd..b313380 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -29,6 +29,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/vic.h>
+#include <asm/system_misc.h>
 
 #include <mach/map.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 52b89a3..a9d1ad4 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -30,6 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/map.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index c909573..dff11c3 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -30,6 +30,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/map.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 17caece..9ad9469 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -24,6 +24,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
index 956ac18..9204270 100644
--- a/arch/arm/mach-shmobile/include/mach/system.h
+++ b/arch/arm/mach-shmobile/include/mach/system.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
+#include <asm/system_misc.h>
+
 static inline void arch_idle(void)
 {
 	cpu_do_idle();
diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
index 12d760c..4d1b86a 100644
--- a/arch/arm/mach-shmobile/suspend.c
+++ b/arch/arm/mach-shmobile/suspend.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 #include <linux/err.h>
 #include <asm/io.h>
+#include <asm/system_misc.h>
 
 static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
 {
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 9a06619..9e4dd8b 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -28,6 +28,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-serial.h>
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 9107231..8b05694 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -25,6 +25,7 @@
 #include <asm/cp15.h>
 #include <asm/system_info.h>
 #include <asm/unaligned.h>
+#include <asm/system_info.h>
 
 #include "fault.h"
 
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 5bdff5c..5a0a0b7 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -25,6 +25,8 @@
 #include <asm/system_misc.h>
 #include <asm/system_info.h>
 #include <asm/tlbflush.h>
+#include <asm/system_misc.h>
+#include <asm/system_info.h>
 
 #include "fault.h"
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index cd439c1..a27555a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -28,6 +28,7 @@
 #include <asm/highmem.h>
 #include <asm/system_info.h>
 #include <asm/traps.h>
+#include <asm/system_info.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
index 6a85a0c..33fa699 100644
--- a/arch/arm/plat-iop/restart.c
+++ b/arch/arm/plat-iop/restart.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 #include <asm/hardware/iop3xx.h>
+#include <asm/system_misc.h>
 #include <mach/hardware.h>
 
 void iop3xx_restart(char mode, const char *cmd)
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 8f12074..c195d6d 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -25,6 +25,7 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
+#include <asm/system_misc.h>
 #include <asm/proc-fns.h>
 #include <asm/mach-types.h>
 
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 21f1fda..ded6431 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -34,6 +34,7 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/cacheflush.h>
+#include <asm/system_info.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 2b4e3d8..16f203e 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -11,6 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 #include <linux/io.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/sp810.h>
 #include <mach/hardware.h>
 #include <mach/generic.h>
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index d89068f..9f50997 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -22,6 +22,7 @@
 #include <asm/cputype.h>
 #include <asm/thread_notify.h>
 #include <asm/vfp.h>
+#include <asm/system_info.h>
 
 #include "vfpinstr.h"
 #include "vfp.h"
diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index 59f4261..654076e 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -19,6 +19,7 @@
 #include <linux/hrtimer.h>
 #include <linux/module.h>
 #include <trace/events/power.h>
+#include <asm/system_misc.h>
 
 #include "cpuidle.h"
 
diff --git a/drivers/net/ethernet/8390/etherh.c b/drivers/net/ethernet/8390/etherh.c
index 48c4948..a45b0d8 100644
--- a/drivers/net/ethernet/8390/etherh.c
+++ b/drivers/net/ethernet/8390/etherh.c
@@ -48,6 +48,7 @@
 #include <asm/system.h>
 #include <asm/ecard.h>
 #include <asm/io.h>
+#include <asm/system_info.h>
 
 #define EI_SHIFT(x)	(ei_local->reg_offset[x])
 
diff --git a/drivers/tty/serial/21285.c b/drivers/tty/serial/21285.c
index 1b37626..6d0ddbc 100644
--- a/drivers/tty/serial/21285.c
+++ b/drivers/tty/serial/21285.c
@@ -16,6 +16,7 @@
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
+#include <asm/system_info.h>
 #include <asm/hardware/dec21285.h>
 #include <mach/hardware.h>
 
diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c
index f551356..658a36d 100644
--- a/drivers/watchdog/wdt285.c
+++ b/drivers/watchdog/wdt285.c
@@ -32,6 +32,7 @@
 #include <mach/hardware.h>
 
 #include <asm/mach-types.h>
+#include <asm/system_info.h>
 #include <asm/hardware/dec21285.h>
 
 /*



From b-cousson at ti.com  Thu Mar 15 17:39:12 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Thu, 15 Mar 2012 22:39:12 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203152041.53754.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com> <4F621939.9040906@ti.com>
 <20120315195753.GA2842@n2100.arm.linux.org.uk>
 <201203152041.53754.arnd@arndb.de>
Message-ID: <4F626180.2010902@ti.com>

On 3/15/2012 9:41 PM, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Russell King - ARM Linux wrote:
>> On Thu, Mar 15, 2012 at 05:30:49PM +0100, Cousson, Benoit wrote:
>>> This was done like IRQ on purpose, because an Interrupt ReQuest line and
>>> a DMA Request line are really similar for the HW point of view at IP
>>> level.
>>
>> I'm not sure about that at all levels.  Sure, at hardware level they're
>> the same, but I think the flat numeric namespace for IRQs has been
>> proven to be a problem when there's multiple IRQ controllers in the
>> system.
>
> In the DT bindings, both IRQ and the suggested DMA are not flat number
> spaces, but instead can be of arbitrarly length defined by the controller.
>
>> As far as I'm concerned for DMA stuff, there is currently no real solution
>> for a DT representation; TI have asked me to take over the conversion of
>> OMAP DMA support to the DMA engine API, and I'm not yet convinced that
>> the existing numbering system is the right solution - especially as
>> there's several overlapping numberspaces for OMAP DMA numbers which
>> are SoC specific.
>
> The numbers definitely need to become local to each of the controllers, but
> that is the case pretty much automatically using the proposed binding,
> because each dma request identifier starts with the phandle of the
> controller.

Indeed, and in the case of the OMAP SDMA controller, it can handle up to 
127 DMA request lines numbered from 0 to 126... So a local number seems 
to be a good representation... especially for a number. I'm not sure to 
understand the issue with this binding.

And AFAIK, there is the only one general purpose DMA controller in OMAP 
so far. The other ones are private to some IPs like MMC or USB, so they 
do not need necessarily need any DT representation.
But anyway, since the controller phandle is mandatory, it will be able 
to handle even several instances of this DMA controller without any issue.

Regards
Benoit


From linux at arm.linux.org.uk  Thu Mar 15 17:55:37 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 15 Mar 2012 21:55:37 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <4F626180.2010902@ti.com>
References: <4F22DEF2.5000807@ti.com> <4F621939.9040906@ti.com>
 <20120315195753.GA2842@n2100.arm.linux.org.uk>
 <201203152041.53754.arnd@arndb.de> <4F626180.2010902@ti.com>
Message-ID: <20120315215537.GB2842@n2100.arm.linux.org.uk>

On Thu, Mar 15, 2012 at 10:39:12PM +0100, Cousson, Benoit wrote:
> On 3/15/2012 9:41 PM, Arnd Bergmann wrote:
>> On Thursday 15 March 2012, Russell King - ARM Linux wrote:
>>> On Thu, Mar 15, 2012 at 05:30:49PM +0100, Cousson, Benoit wrote:
>>>> This was done like IRQ on purpose, because an Interrupt ReQuest line and
>>>> a DMA Request line are really similar for the HW point of view at IP
>>>> level.
>>>
>>> I'm not sure about that at all levels.  Sure, at hardware level they're
>>> the same, but I think the flat numeric namespace for IRQs has been
>>> proven to be a problem when there's multiple IRQ controllers in the
>>> system.
>>
>> In the DT bindings, both IRQ and the suggested DMA are not flat number
>> spaces, but instead can be of arbitrarly length defined by the controller.
>>
>>> As far as I'm concerned for DMA stuff, there is currently no real solution
>>> for a DT representation; TI have asked me to take over the conversion of
>>> OMAP DMA support to the DMA engine API, and I'm not yet convinced that
>>> the existing numbering system is the right solution - especially as
>>> there's several overlapping numberspaces for OMAP DMA numbers which
>>> are SoC specific.
>>
>> The numbers definitely need to become local to each of the controllers, but
>> that is the case pretty much automatically using the proposed binding,
>> because each dma request identifier starts with the phandle of the
>> controller.
>
> Indeed, and in the case of the OMAP SDMA controller, it can handle up to  
> 127 DMA request lines numbered from 0 to 126... So a local number seems  
> to be a good representation... especially for a number. I'm not sure to  
> understand the issue with this binding.
>
> And AFAIK, there is the only one general purpose DMA controller in OMAP  
> so far. The other ones are private to some IPs like MMC or USB, so they  
> do not need necessarily need any DT representation.
> But anyway, since the controller phandle is mandatory, it will be able  
> to handle even several instances of this DMA controller without any 
> issue.

Thank you both for missing my point.

#define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */

#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */

#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */

#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */

#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */

Notice the overlap between the different SoCs for the same number on the
same DMA controller.

This shouldn't cause problems when all users are within the SoC specific
file, but those EXT ones would probably be platform specific, and so you
immediately have a dependence between the platform and the SoC there.

That dependence can be completely eliminated by other matching schemes
which are supportable via the DMA engine API.


From kgene.kim at samsung.com  Thu Mar 15 18:19:43 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 15 Mar 2012 15:19:43 -0700
Subject: [PATCH] Fixes after disintegration of asm/system.h for ARM
In-Reply-To: <20120315212619.31098.94700.stgit@warthog.procyon.org.uk>
References: <20120315212619.31098.94700.stgit@warthog.procyon.org.uk>
Message-ID: <4F626AFF.1060501@samsung.com>

David Howells:
> Signed-off-by: David Howells<dhowells at redhat.com>
> cc: Russell King<linux at arm.linux.org.uk>
> cc: linux-arm-kernel at lists.infradead.org
> ---

[...]

>   arch/arm/mach-s3c2410/s3c2410.c              |    1 +
>   arch/arm/mach-s3c2412/s3c2412.c              |    1 +
>   arch/arm/mach-s3c2416/s3c2416.c              |    1 +
>   arch/arm/mach-s3c2440/s3c244x.c              |    1 +
>   arch/arm/mach-s3c2443/s3c2443.c              |    1 +

Just note, above files have been moved into mach-s3c24xx/

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From dhowells at redhat.com  Thu Mar 15 18:25:15 2012
From: dhowells at redhat.com (David Howells)
Date: Thu, 15 Mar 2012 22:25:15 +0000
Subject: [PATCH] Fixes after disintegration of asm/system.h for ARM
In-Reply-To: <4F626AFF.1060501@samsung.com>
References: <4F626AFF.1060501@samsung.com>
 <20120315212619.31098.94700.stgit@warthog.procyon.org.uk>
Message-ID: <463.1331850315@redhat.com>

Kukjin Kim <kgene.kim at samsung.com> wrote:

> >   arch/arm/mach-s3c2410/s3c2410.c              |    1 +
> >   arch/arm/mach-s3c2412/s3c2412.c              |    1 +
> >   arch/arm/mach-s3c2416/s3c2416.c              |    1 +
> >   arch/arm/mach-s3c2440/s3c244x.c              |    1 +
> >   arch/arm/mach-s3c2443/s3c2443.c              |    1 +
> 
> Just note, above files have been moved into mach-s3c24xx/

Thanks.  Hopefully GIT should handle that.

David


From paul at pwsan.com  Thu Mar 15 19:01:45 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 15 Mar 2012 17:01:45 -0600 (MDT)
Subject: [PATCH 1/2] ARM: OMAP: powerdomain: Wait for powerdomain
 transition in pwrdm_state_switch()
In-Reply-To: <20120315175122.GB7276@atomide.com>
References: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
 <1331562873-29535-2-git-send-email-santosh.shilimkar@ti.com>
 <alpine.DEB.2.00.1203151129160.26218@utopia.booyaka.com>
 <20120315175122.GB7276@atomide.com>
Message-ID: <alpine.DEB.2.00.1203151701290.2133@utopia.booyaka.com>

On Thu, 15 Mar 2012, Tony Lindgren wrote:

> * Paul Walmsley <paul at pwsan.com> [120315 10:35]:
> > On Mon, 12 Mar 2012, Santosh Shilimkar wrote:
> > 
> > > Commit b1cbdb00d{OMAP: clockdomain: Wait for powerdomain to be ON
> > > when using clockdomain force wakeup} was assuming that pwrdm_state_switch()
> > > does wait for the powerdomain transition which is not the case.
> > > 
> > > Fix this API by adding the pwrdm_wait_transition().
> > > 
> > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> > > CC: Rajendra Nayak <rnayak at ti.com>
> > > CC: Paul Walmsley <paul at pwsan.com>
> > 
> > Acked-by: Paul Walmsley <paul at pwsan.com>
> > 
> > Sounds like this fixes a major kernel oops bug for Tony so this should go 
> > in ASAP to v3.3-rc series.
> 
> Got a random oops with this one applied still, just happened
> to take longer this time :(

Oh well.  Will queue it for v3.4-rc1 then...


- Paul


From mgreer at animalcreek.com  Thu Mar 15 19:07:11 2012
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Thu, 15 Mar 2012 16:07:11 -0700
Subject: arm: omap3: pm34xx.c: Some minor fixups
Message-ID: <1331852833-4357-1-git-send-email-mgreer@animalcreek.com>

I found some minor issues when looking through pm34xx.c recently
so these patches try to address them.  My apologies if they are
already fixed in another branch somewhere.  Based on latest k.o.
master branch.

Mark
--


From mgreer at animalcreek.com  Thu Mar 15 19:07:12 2012
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Thu, 15 Mar 2012 16:07:12 -0700
Subject: [PATCH 1/2] arm: omap3: pm34xx.c: Fix omap3_pm_init() error out paths
In-Reply-To: <1331852833-4357-1-git-send-email-mgreer@animalcreek.com>
References: <1331852833-4357-1-git-send-email-mgreer@animalcreek.com>
Message-ID: <1331852833-4357-2-git-send-email-mgreer@animalcreek.com>

From: "Mark A. Greer" <mgreer at animalcreek.com>

It appears that the error paths were overlooked when the
omap3_pm_init() routine had the prcm chain handler code
added.  Fix this by adding a goto target and reordering
the error handling code.  Also fix how the irq argument
for free_irq() is determined.

CC: Tero Kristo <t-kristo at ti.com>
Signed-off-by: Mark A. Greer <mgreer at animalcreek.com>
---
 arch/arm/mach-omap2/pm34xx.c |   16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 27fc7a2..af8d741 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -817,13 +817,13 @@ static int __init omap3_pm_init(void)
 
 	if (ret) {
 		pr_err("pm: Failed to request pm_io irq\n");
-		goto err1;
+		goto err2;
 	}
 
 	ret = pwrdm_for_each(pwrdms_setup, NULL);
 	if (ret) {
 		printk(KERN_ERR "Failed to setup powerdomains\n");
-		goto err2;
+		goto err3;
 	}
 
 	(void) clkdm_for_each(clkdms_setup, NULL);
@@ -831,7 +831,8 @@ static int __init omap3_pm_init(void)
 	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 	if (mpu_pwrdm == NULL) {
 		printk(KERN_ERR "Failed to get mpu_pwrdm\n");
-		goto err2;
+		ret = -EINVAL;
+		goto err3;
 	}
 
 	neon_pwrdm = pwrdm_lookup("neon_pwrdm");
@@ -879,14 +880,17 @@ static int __init omap3_pm_init(void)
 	}
 
 	omap3_save_scratchpad_contents();
-err1:
 	return ret;
-err2:
-	free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
+
+err3:
 	list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 		list_del(&pwrst->node);
 		kfree(pwrst);
 	}
+	free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
+err2:
+	free_irq(omap_prcm_event_to_irq("wkup"), NULL);
+err1:
 	return ret;
 }
 
-- 
1.7.9.4



From mgreer at animalcreek.com  Thu Mar 15 19:07:13 2012
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Thu, 15 Mar 2012 16:07:13 -0700
Subject: [PATCH 2/2] arm: omap3: pm34xx.c: Replace printk() with appropriate
 pr_*()
In-Reply-To: <1331852833-4357-1-git-send-email-mgreer@animalcreek.com>
References: <1331852833-4357-1-git-send-email-mgreer@animalcreek.com>
Message-ID: <1331852833-4357-3-git-send-email-mgreer@animalcreek.com>

From: "Mark A. Greer" <mgreer at animalcreek.com>

Currently, pm34xx.c has a mix of printk() and pr_*() statements
so replace the printk() statements with the equivalent pr_*()
statements.

Signed-off-by: Mark A. Greer <mgreer at animalcreek.com>
---
 arch/arm/mach-omap2/pm34xx.c |   17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index af8d741..495e509 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -166,8 +166,7 @@ static void omap3_save_secure_ram_context(void)
 		pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 		/* Following is for error tracking, it should not happen */
 		if (ret) {
-			printk(KERN_ERR "save_secure_sram() returns %08x\n",
-				ret);
+			pr_err("save_secure_sram() returns %08x\n", ret);
 			while (1)
 				;
 		}
@@ -307,7 +306,7 @@ void omap_sram_idle(void)
 		break;
 	default:
 		/* Invalid state */
-		printk(KERN_ERR "Invalid mpu state in sram_idle\n");
+		pr_err("Invalid mpu state in sram_idle\n");
 		return;
 	}
 
@@ -463,7 +462,7 @@ restore:
 	list_for_each_entry(pwrst, &pwrst_list, node) {
 		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 		if (state > pwrst->next_state) {
-			printk(KERN_INFO "Powerdomain (%s) didn't enter "
+			pr_info("Powerdomain (%s) didn't enter "
 			       "target state %d\n",
 			       pwrst->pwrdm->name, pwrst->next_state);
 			ret = -1;
@@ -471,9 +470,9 @@ restore:
 		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 	}
 	if (ret)
-		printk(KERN_ERR "Could not enter target state in pm_suspend\n");
+		pr_err("Could not enter target state in pm_suspend\n");
 	else
-		printk(KERN_INFO "Successfully put all powerdomains "
+		pr_info("Successfully put all powerdomains "
 		       "to target state\n");
 
 	return ret;
@@ -822,7 +821,7 @@ static int __init omap3_pm_init(void)
 
 	ret = pwrdm_for_each(pwrdms_setup, NULL);
 	if (ret) {
-		printk(KERN_ERR "Failed to setup powerdomains\n");
+		pr_err("Failed to setup powerdomains\n");
 		goto err3;
 	}
 
@@ -830,7 +829,7 @@ static int __init omap3_pm_init(void)
 
 	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 	if (mpu_pwrdm == NULL) {
-		printk(KERN_ERR "Failed to get mpu_pwrdm\n");
+		pr_err("Failed to get mpu_pwrdm\n");
 		ret = -EINVAL;
 		goto err3;
 	}
@@ -865,7 +864,7 @@ static int __init omap3_pm_init(void)
 		omap3_secure_ram_storage =
 			kmalloc(0x803F, GFP_KERNEL);
 		if (!omap3_secure_ram_storage)
-			printk(KERN_ERR "Memory allocation failed when"
+			pr_err("Memory allocation failed when"
 					"allocating for secure sram context\n");
 
 		local_irq_disable();
-- 
1.7.9.4



From tony at atomide.com  Thu Mar 15 19:22:57 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 15 Mar 2012 16:22:57 -0700
Subject: [PATCH 1/2] ARM: OMAP: powerdomain: Wait for powerdomain
 transition in pwrdm_state_switch()
In-Reply-To: <alpine.DEB.2.00.1203151701290.2133@utopia.booyaka.com>
References: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
 <1331562873-29535-2-git-send-email-santosh.shilimkar@ti.com>
 <alpine.DEB.2.00.1203151129160.26218@utopia.booyaka.com>
 <20120315175122.GB7276@atomide.com>
 <alpine.DEB.2.00.1203151701290.2133@utopia.booyaka.com>
Message-ID: <20120315232256.GC7276@atomide.com>

* Paul Walmsley <paul at pwsan.com> [120315 16:04]:
> On Thu, 15 Mar 2012, Tony Lindgren wrote:
> 
> > * Paul Walmsley <paul at pwsan.com> [120315 10:35]:
> > > On Mon, 12 Mar 2012, Santosh Shilimkar wrote:
> > > 
> > > > Commit b1cbdb00d{OMAP: clockdomain: Wait for powerdomain to be ON
> > > > when using clockdomain force wakeup} was assuming that pwrdm_state_switch()
> > > > does wait for the powerdomain transition which is not the case.
> > > > 
> > > > Fix this API by adding the pwrdm_wait_transition().
> > > > 
> > > > Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> > > > CC: Rajendra Nayak <rnayak at ti.com>
> > > > CC: Paul Walmsley <paul at pwsan.com>
> > > 
> > > Acked-by: Paul Walmsley <paul at pwsan.com>
> > > 
> > > Sounds like this fixes a major kernel oops bug for Tony so this should go 
> > > in ASAP to v3.3-rc series.
> > 
> > Got a random oops with this one applied still, just happened
> > to take longer this time :(
> 
> Oh well.  Will queue it for v3.4-rc1 then...

It seems that I need this patch plus need to undo the wrong
serial muxing in commit 7496ba30 (ARM: OMAP2+: UART: Add default mux
for all uarts) to make my zoom3 boot reliably.

Regards,

Tony


From paul at pwsan.com  Thu Mar 15 19:34:04 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 15 Mar 2012 17:34:04 -0600 (MDT)
Subject: [PATCH 1/2] ARM: OMAP: powerdomain: Wait for powerdomain
 transition in pwrdm_state_switch()
In-Reply-To: <20120315232256.GC7276@atomide.com>
References: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
 <1331562873-29535-2-git-send-email-santosh.shilimkar@ti.com>
 <alpine.DEB.2.00.1203151129160.26218@utopia.booyaka.com>
 <20120315175122.GB7276@atomide.com>
 <alpine.DEB.2.00.1203151701290.2133@utopia.booyaka.com>
 <20120315232256.GC7276@atomide.com>
Message-ID: <alpine.DEB.2.00.1203151733360.5007@utopia.booyaka.com>

On Thu, 15 Mar 2012, Tony Lindgren wrote:

> It seems that I need this patch plus need to undo the wrong
> serial muxing in commit 7496ba30 (ARM: OMAP2+: UART: Add default mux
> for all uarts) to make my zoom3 boot reliably.

Okay.  Well want to take the powerdomain patch for the v3.3-rc series 
then?

- Paul


From ccross at android.com  Thu Mar 15 19:37:19 2012
From: ccross at android.com (Colin Cross)
Date: Thu, 15 Mar 2012 16:37:19 -0700
Subject: [PATCHv2 0/5] coupled cpuidle state support
In-Reply-To: <1331749794-8056-1-git-send-email-ccross@android.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
Message-ID: <CAMbhsRQAw2+as13NVvWkh7ojyRs+jNpFist2gmiiEY52U=o84A@mail.gmail.com>

On Wed, Mar 14, 2012 at 11:29 AM, Colin Cross <ccross at android.com> wrote:
> On some ARM SMP SoCs (OMAP4460, Tegra 2, and probably more), the
> cpus cannot be independently powered down, either due to
> sequencing restrictions (on Tegra 2, cpu 0 must be the last to
> power down), or due to HW bugs (on OMAP4460, a cpu powering up
> will corrupt the gic state unless the other cpu runs a work
> around). ?Each cpu has a power state that it can enter without
> coordinating with the other cpu (usually Wait For Interrupt, or
> WFI), and one or more "coupled" power states that affect blocks
> shared between the cpus (L2 cache, interrupt controller, and
> sometimes the whole SoC). ?Entering a coupled power state must
> be tightly controlled on both cpus.
>
> The easiest solution to implementing coupled cpu power states is
> to hotplug all but one cpu whenever possible, usually using a
> cpufreq governor that looks at cpu load to determine when to
> enable the secondary cpus. ?This causes problems, as hotplug is an
> expensive operation, so the number of hotplug transitions must be
> minimized, leading to very slow response to loads, often on the
> order of seconds.
>
> This patch series implements an alternative solution, where each
> cpu will wait in the WFI state until all cpus are ready to enter
> a coupled state, at which point the coupled state function will
> be called on all cpus at approximately the same time.
>
> Once all cpus are ready to enter idle, they are woken by an smp
> cross call. ?At this point, there is a chance that one of the
> cpus will find work to do, and choose not to enter suspend. ?A
> final pass is needed to guarantee that all cpus will call the
> power state enter function at the same time. ?During this pass,
> each cpu will increment the ready counter, and continue once the
> ready counter matches the number of online coupled cpus. ?If any
> cpu exits idle, the other cpus will decrement their counter and
> retry.
>
> To use coupled cpuidle states, a cpuidle driver must:
>
> ? Set struct cpuidle_device.coupled_cpus to the mask of all
> ? coupled cpus, usually the same as cpu_possible_mask if all cpus
> ? are part of the same cluster. ?The coupled_cpus mask must be
> ? set in the struct cpuidle_device for each cpu.
>
> ? Set struct cpuidle_device.safe_state to a state that is not a
> ? coupled state. ?This is usually WFI.
>
> ? Set CPUIDLE_FLAG_COUPLED in struct cpuidle_state.flags for each
> ? state that affects multiple cpus.
>
> ? Provide a struct cpuidle_state.enter function for each state
> ? that affects multiple cpus. ?This function is guaranteed to be
> ? called on all cpus at approximately the same time. ?The driver
> ? should ensure that the cpus all abort together if any cpu tries
> ? to abort once the function is called.
>
> This series has been tested by implementing a test cpuidle state
> that uses the parallel barrier helper function to verify that
> all cpus call the function at the same time.
>
> This patch set has a few disadvantages over the hotplug governor,
> but I think they are all fairly minor:
> ? * Worst-case interrupt latency can be increased. ?If one cpu
> ? ? receives an interrupt while the other is spinning in the
> ? ? ready_count loop, the second cpu will be stuck with
> ? ? interrupts off until the first cpu finished processing
> ? ? its interrupt and exits idle. ?This will increase the worst
> ? ? case interrupt latency by the worst-case interrupt processing
> ? ? time, but should be very rare.
> ? * Interrupts are processed while still inside pm_idle.
> ? ? Normally, interrupts are only processed at the very end of
> ? ? pm_idle, just before it returns to the idle loop. ?Coupled
> ? ? states requires processing interrupts inside
> ? ? cpuidle_enter_state_coupled in order to distinguish between
> ? ? the smp_cross_call from another cpu that is now idle and an
> ? ? interrupt that should cause idle to exit.
> ? ? I don't see a way to fix this without either being able to
> ? ? read the next pending irq from the interrupt chip, or
> ? ? querying the irq core for which interrupts were processed.
> ? * Since interrupts are processed inside cpuidle, the next
> ? ? timer event could change. ?The new timer event will be
> ? ? handled correctly, but the idle state decision made by
> ? ? the governor will be out of date, and will not be revisited.
> ? ? The governor select function could be called again every time,
> ? ? but this could lead to a lot of work being done by an idle
> ? ? cpu if the other cpu was mostly busy.
>
> v2:
> ? * removed the coupled lock, replacing it with atomic counters
> ? * added a check for outstanding pokes before beginning the
> ? ? final transition to avoid extra wakeups
> ? * made the cpuidle_coupled struct completely private
> ? * fixed kerneldoc comment formatting
> ? * added a patch with a helper function for resynchronizing
> ? ? cpus after aborting idle
> ? * added a patch (not for merging) to add trace events for
> ? ? verification and performance testing

I forgot to mention, this patch series is on v3.3-rc7, and will
conflict with the cpuidle timekeeping patches.  If those go in first
(which is likely), I will rework this series on top of it.  I left it
on v3.3-rc7 now to make testing easier.


From tony at atomide.com  Thu Mar 15 19:40:05 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 15 Mar 2012 16:40:05 -0700
Subject: [PATCH 1/2] ARM: OMAP: powerdomain: Wait for powerdomain
 transition in pwrdm_state_switch()
In-Reply-To: <alpine.DEB.2.00.1203151733360.5007@utopia.booyaka.com>
References: <1331562873-29535-1-git-send-email-santosh.shilimkar@ti.com>
 <1331562873-29535-2-git-send-email-santosh.shilimkar@ti.com>
 <alpine.DEB.2.00.1203151129160.26218@utopia.booyaka.com>
 <20120315175122.GB7276@atomide.com>
 <alpine.DEB.2.00.1203151701290.2133@utopia.booyaka.com>
 <20120315232256.GC7276@atomide.com>
 <alpine.DEB.2.00.1203151733360.5007@utopia.booyaka.com>
Message-ID: <20120315234004.GD7276@atomide.com>

* Paul Walmsley <paul at pwsan.com> [120315 16:36]:
> On Thu, 15 Mar 2012, Tony Lindgren wrote:
> 
> > It seems that I need this patch plus need to undo the wrong
> > serial muxing in commit 7496ba30 (ARM: OMAP2+: UART: Add default mux
> > for all uarts) to make my zoom3 boot reliably.
> 
> Okay.  Well want to take the powerdomain patch for the v3.3-rc series 
> then?

Uhh now got a random issue of "BUG: bad unlock balance detected"..
Random oopses seem less common now, but still not booting reliably.

Regards,

Tony


From nico at fluxnic.net  Thu Mar 15 19:45:09 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 15 Mar 2012 19:45:09 -0400 (EDT)
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120315195753.GA2842@n2100.arm.linux.org.uk>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <201203150922.06379.arnd@arndb.de> <4F621939.9040906@ti.com>
 <20120315195753.GA2842@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.02.1203151934560.24151@xanadu.home>

On Thu, 15 Mar 2012, Russell King - ARM Linux wrote:

> I really don't like these behind-the-scenes discussions which never then
> get followed up in public, and people then start quoting what was "agreed"
> as that's the way things must be done.
> 
> It's a bit like folk at the recent Linaro Connect apparantly discussing
> my machine registry and deciding that it should be shut down.  No one
> has yet talked to me about that or even done the curtesy of asking me
> what my view is.

Let me catch the ball in flight here as the responsible folk was me.

For the transition to DT to be effective for new boards on ARM, I 
suggested that the machine registry would need to be closed at this 
point i.e. no new additions to it.  As far as I remember, Vincent 
volunteered to talk to you about it, which he apparently did within the 
same hour.  That's all there was to it.


Nicolas


From herbert at gondor.apana.org.au  Thu Mar 15 19:54:06 2012
From: herbert at gondor.apana.org.au (Herbert Xu)
Date: Fri, 16 Mar 2012 10:54:06 +1100
Subject: [PATCH 6/6] hwrng: Kconfig: remove dependency for atmel-rng driver
In-Reply-To: <c3455cec019bedacc6ff58cf8cd2ae25cdeb212f.1331826095.git.nicolas.ferre@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
 <c3455cec019bedacc6ff58cf8cd2ae25cdeb212f.1331826095.git.nicolas.ferre@atmel.com>
Message-ID: <20120315235406.GB18496@gondor.apana.org.au>

On Thu, Mar 15, 2012 at 04:57:22PM +0100, Nicolas Ferre wrote:
> This will allow to select this driver for newer SoCs. Make sure to
> keep dependency on HAVE_CLK to avoid breaking other machines.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Acked-by: Herbert Xu <herbert at gondor.apana.org.au>
-- 
Email: Herbert Xu <herbert at gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt


From khilman at ti.com  Thu Mar 15 20:04:43 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 15 Mar 2012 17:04:43 -0700
Subject: [PATCHv2 3/5] cpuidle: add support for states that affect
 multiple cpus
In-Reply-To: <1331749794-8056-4-git-send-email-ccross@android.com> (Colin
 Cross's message of "Wed, 14 Mar 2012 11:29:52 -0700")
References: <1331749794-8056-1-git-send-email-ccross@android.com>
 <1331749794-8056-4-git-send-email-ccross@android.com>
Message-ID: <87lin18l7o.fsf@ti.com>

Colin Cross <ccross at android.com> writes:

> +/**
> + * cpuidle_coupled_cpu_set_alive - adjust alive_count during hotplug transitions
> + * @cpu: target cpu number
> + * @alive: whether the target cpu is going up or down
> + *
> + * Run on the cpu that is bringing up the target cpu, before the target cpu
> + * has been booted, or after the target cpu is completely dead.
> + */
> +static void cpuidle_coupled_cpu_set_alive(int cpu, bool alive)
> +{
> +	struct cpuidle_device *dev;
> +	struct cpuidle_coupled *coupled;
> +
> +	mutex_lock(&cpuidle_lock);
> +
> +	dev = per_cpu(cpuidle_devices, cpu);
> +	if (!dev->coupled)
> +		goto out;
> +
> +	coupled = dev->coupled;
> +
> +	/*
> +	 * waiting_count must be at least 1 less than alive_count, because
> +	 * this cpu is not waiting.  Spin until all cpus have noticed this cpu
> +	 * is not idle and exited the ready loop before changing alive_count.
> +	 */
> +	while (atomic_read(&coupled->ready_count))
> +		cpu_relax();
> +
> +	smp_mb__before_atomic_inc();
> +	atomic_inc(&coupled->alive_count);

This doesn't look quite right.  alive_count is incrmented whether the
CPU is going up or down?

Maybe I misunderstood something, but I don't see anywhere where
alive_count is decrmemented after a CPU is removed.

Kevin

> +	smp_mb__after_atomic_inc();
> +
> +	if (alive)
> +		coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_NOT_IDLE;
> +	else
> +		coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_DEAD;
> +
> +out:
> +	mutex_unlock(&cpuidle_lock);
> +}
> +


From ccross at android.com  Thu Mar 15 20:20:08 2012
From: ccross at android.com (Colin Cross)
Date: Thu, 15 Mar 2012 17:20:08 -0700
Subject: [PATCHv2 3/5] cpuidle: add support for states that affect
 multiple cpus
In-Reply-To: <87lin18l7o.fsf@ti.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
 <1331749794-8056-4-git-send-email-ccross@android.com>
 <87lin18l7o.fsf@ti.com>
Message-ID: <CAMbhsRS3J2vruru8i4r1-cB9aJLYW9y1bP0vv7=L3q1JP77ttg@mail.gmail.com>

On Thu, Mar 15, 2012 at 5:04 PM, Kevin Hilman <khilman at ti.com> wrote:
> Colin Cross <ccross at android.com> writes:
>
>> +/**
>> + * cpuidle_coupled_cpu_set_alive - adjust alive_count during hotplug transitions
>> + * @cpu: target cpu number
>> + * @alive: whether the target cpu is going up or down
>> + *
>> + * Run on the cpu that is bringing up the target cpu, before the target cpu
>> + * has been booted, or after the target cpu is completely dead.
>> + */
>> +static void cpuidle_coupled_cpu_set_alive(int cpu, bool alive)
>> +{
>> + ? ? struct cpuidle_device *dev;
>> + ? ? struct cpuidle_coupled *coupled;
>> +
>> + ? ? mutex_lock(&cpuidle_lock);
>> +
>> + ? ? dev = per_cpu(cpuidle_devices, cpu);
>> + ? ? if (!dev->coupled)
>> + ? ? ? ? ? ? goto out;
>> +
>> + ? ? coupled = dev->coupled;
>> +
>> + ? ? /*
>> + ? ? ?* waiting_count must be at least 1 less than alive_count, because
>> + ? ? ?* this cpu is not waiting. ?Spin until all cpus have noticed this cpu
>> + ? ? ?* is not idle and exited the ready loop before changing alive_count.
>> + ? ? ?*/
>> + ? ? while (atomic_read(&coupled->ready_count))
>> + ? ? ? ? ? ? cpu_relax();
>> +
>> + ? ? smp_mb__before_atomic_inc();
>> + ? ? atomic_inc(&coupled->alive_count);
>
> This doesn't look quite right. ?alive_count is incrmented whether the
> CPU is going up or down?
>
> Maybe I misunderstood something, but I don't see anywhere where
> alive_count is decrmemented after a CPU is removed.

Oops, dropped the atomic_dec when I merged from two separate functions
for up and down to a single function that takes a bool.

>> + ? ? smp_mb__after_atomic_inc();
>> +
>> + ? ? if (alive)
>> + ? ? ? ? ? ? coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_NOT_IDLE;
>> + ? ? else
>> + ? ? ? ? ? ? coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_DEAD;
>> +
>> +out:
>> + ? ? mutex_unlock(&cpuidle_lock);
>> +}
>> +


From richard.zhao at freescale.com  Thu Mar 15 21:10:07 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Fri, 16 Mar 2012 09:10:07 +0800
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <20120315185004.GD3852@pengutronix.de>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
 <20120314085228.GM3852@pengutronix.de>
 <20120315144601.GA5701@richard-laptop>
 <20120315150048.GC3852@pengutronix.de>
 <20120315151521.GB5701@richard-laptop>
 <20120315185004.GD3852@pengutronix.de>
Message-ID: <20120316011006.GA17459@b20223-02.ap.freescale.net>

Hi Sascha,

On Thu, Mar 15, 2012 at 07:50:04PM +0100, Sascha Hauer wrote:
> On Thu, Mar 15, 2012 at 11:15:23PM +0800, Richard Zhao wrote:
> > On Thu, Mar 15, 2012 at 04:00:48PM +0100, Sascha Hauer wrote:
> > > On Thu, Mar 15, 2012 at 10:46:04PM +0800, Richard Zhao wrote:
> > > > On Wed, Mar 14, 2012 at 09:52:28AM +0100, Sascha Hauer wrote:
> > > > > On Wed, Mar 14, 2012 at 04:22:58PM +0800, Richard Zhao wrote:
> > > > > > Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> > > > > > ---
> > > > > >  
> > > > > >  #define DEF_PLL(name)					\
> > > > > >  	static struct clk name = {			\
> > > > > > @@ -681,6 +741,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
> > > > > >  		.disable	= pll_disable,		\
> > > > > >  		.get_rate	= name##_get_rate,	\
> > > > > >  		.set_rate	= name##_set_rate,	\
> > > > > > +		.round_rate	= name##_round_rate,	\
> > > > > 
> > > > > I hope this ## stuff is gone soon with the generic clock framework. It
> > > > > is so ugly and inefficient.
> > > > I hope this doesn't prevent this two patches go in.
> > > 
> > > Given that we are short from getting a generic clock framework (and I
> > > think this time it's for real) and that you are not mention in any words
> > > what these patches fix I don't see a reason for merging them.
> > I think the cpu clock is a great challenge for generic clock framework.
> > When it set_rate, it includes reparent, and change parent's parent's rate.
> > I don't see any upstream code like that till now. and it's really what
> > we need.
> 
> Then do a clk_set_parent, clk_set_rate and a clk_set_parent again
> in your cpufreq driver.
No, it's platform code, and supposed to be in arch/arm. What the cpufre
driver know is to get cpu clk, rather not how cpu clk change its rate.
And cpu clk/arm_clk is a real clock wires in SoC.
> The notifying mechanism even allows you to
> block any concurrent change in between these three steps if necessary.
> Noone says that these three steps have to be encapsulated in a single
> clk_set_rate call like you did in your patch.
If you're reviwing the patch, why not take a step advance? :)
> 
> > 
> > And it also block cpufreq from upstreaming.
> 
> Yes, and that's a good way to tell your management why you have to
> invest some time into porting i.MX6 to the generic clock framework ;)
It's Shawn doing the work. So I think it's better get the patches in
and let everyone notice the tricky things.

In my opinion, it might not be good to close the window for summiting
patch of basic modules, which is used nearly by every driver. There
might be more things pending thant you thought.

Thanks
Richard
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From shawn.guo at linaro.org  Thu Mar 15 21:27:13 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 09:27:13 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F621D09.2080806@freescale.com>
References: <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315130253.GA6065@S2101-09.ap.freescale.net>
 <4F61F080.4090800@freescale.com>
 <20120315142115.GB6065@S2101-09.ap.freescale.net>
 <4F621D09.2080806@freescale.com>
Message-ID: <20120316012711.GD6065@S2101-09.ap.freescale.net>

On Thu, Mar 15, 2012 at 11:47:05AM -0500, Timur Tabi wrote:
> Shawn Guo wrote:
> > sound {
> >       compatible = "fsl,imx51-babbage-sgtl5000",
> >                    "fsl,imx-audio-sgtl5000";
> >       model = "imx51-babbage-sgtl5000";
> >       ssi-controller = <&ssi1, &ssi2>;
> >       audio-codec = <&sgtl5000_1, &sgtl5000_2>;
> >       mux-int-port = <1>;
> >       mux-ext-port = <3>;
> > };
> 
> Based on Mark's other email, I would rather see this:
> 
> sound1 {
>       compatible = "fsl,imx51-babbage-sgtl5000",
>                    "fsl,imx-audio-sgtl5000";
>       model = "imx51-babbage-sgtl5000";
>       ssi-controller = <&ssi1>;
>       audio-codec = <&sgtl5000_1>;
>       mux-int-port = <1>;
>       mux-ext-port = <3>;
> };
> 
> sound2 {
>       compatible = "fsl,imx51-babbage-sgtl5000",
>                    "fsl,imx-audio-sgtl5000";
>       model = "imx51-babbage-sgtl5000";
>       ssi-controller = <&ssi2>;
>       audio-codec = <&sgtl5000_2>;
>       mux-int-port = <1>;
>       mux-ext-port = <3>;
> };
> 
> (ignoring for the moment that I have no idea what the mux-xxx-port values
> in sound2 should be)
> 
> This makes it clear that ssi1 connects only to sgtl5000_1.
> 
> If you're okay with this, then please update the documentation accordingly.
> 
Hmm, Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
is the binding document specifically for imx-sgtl5000 driver rather
than for all fsl_ssi based machine drivers.  Since I have never seen
and doubt will ever see the setup that two SSIs connect to two
sgtl5000 codecs on any imx board, I do not see much point to update
the documentation for that.

If this is indeed a practical setup for PowerPC, it can be documented
in the binding for PowerPC machine driver when there is future PowerPC
machine drivers adopting the new binding.

-- 
Regards,
Shawn


From jg1.han at samsung.com  Thu Mar 15 21:39:06 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Fri, 16 Mar 2012 10:39:06 +0900
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com> <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
Message-ID: <001d01cd0315$935cc720$ba165560$%han@samsung.com>



> -----Original Message-----
> From: Darius Augulis [mailto:augulis.darius at gmail.com]
> Sent: Thursday, March 15, 2012 5:27 PM
> To: Jingoo Han
> Cc: Thomas Abraham; linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-
> kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; kgene.kim at samsung.com; ben-
> linux at fluff.org; patches at linaro.org; Kyungmin Park; JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark
> Brown; Peter Korsgaard; Maurus Cuelenaere
> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> 
> On Thu, Mar 15, 2012 at 10:10 AM, Jingoo Han <jg1.han at samsung.com> wrote:
> 
> >> There is single board - mini6410 (or real6410) and it's name doesn't
> >> depend on connected LCD size.
> >> We know, that this board is available with different sizes of LCD and
> >> currently we have in kernel support for both sizes.
> >> It might be so, that it's implemented not in perfect way, but it was
> >> accepted and at least it's working.
> >
> >
> > I don't think so.
> > You argues that the wrong code should not be removed because it was accepted and at least it's working.
> > It is just wrong usage, which can just work.
> > Moreover, your code will make the problem, when 2~5 windows of FIMD IP are used.
> 
> Could please explain that? How does LCD feature selection for mini6410
> and real6410 break that?
> Timing for different sizes of LCD is located in two statically
> allocated structures which are used at board init time depending on
> kernel param line.
> Data from one of these structures is copied to s3c-fb platform data
> dynamically by board init code. Why it's a problem? What changes if
> platform data isn't rewritten dynamically?
> 
> > So, your code can be removed.
> 
> I don't think so. It does not break anything yet. One who make
> changes, should ensure backwards compatibility, at least talking about
> functionality and hardware (LCD) support, which was added few months
> ago. Remember, we talk about kernel parameters line - now it lets
> bootloader to select correct LCD size. After your changes, board with
> 7" LCD wont show anything.

[CC'ed Tushar Behera]

Yes, your code is working. However, your code is bug.
'struct s3c_fb_pd_win' is used not for LCD, but for windows of FIMD IP. So, 'struct s3c_fb_pd_win' should not be used to select LCD.
The mach-aquila.c uses two 'struct s3c_fb_pd_win' like you, however 'struct s3c_fb_pd_win' don't make problem with Thomas's
patchset. It is because mach-aquila.c use 'struct s3c_fb_pd_win' for only windows of FIMD IP.
We don't have to responsibility to keep wrong code. If you have kept the rule, Thomas's patch would not make the compatibility
problem with your code. Why we should keep aberration such as your code? If you want to select two LCDs, please find other way.


> 
> Darius A.



From arjan at linux.intel.com  Thu Mar 15 21:52:05 2012
From: arjan at linux.intel.com (Arjan van de Ven)
Date: Thu, 15 Mar 2012 18:52:05 -0700
Subject: [PATCHv2 3/5] cpuidle: add support for states that affect multiple
 cpus
In-Reply-To: <CAMbhsRS3J2vruru8i4r1-cB9aJLYW9y1bP0vv7=L3q1JP77ttg@mail.gmail.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
 <1331749794-8056-4-git-send-email-ccross@android.com> <87lin18l7o.fsf@ti.com>
 <CAMbhsRS3J2vruru8i4r1-cB9aJLYW9y1bP0vv7=L3q1JP77ttg@mail.gmail.com>
Message-ID: <4F629CC5.60402@linux.intel.com>

On 3/15/2012 5:20 PM, Colin Cross wrote:
> Oops, dropped the atomic_dec when I merged from two separate functions
> for up and down to a single function that takes a bool.

generally in Linux we tend to not like "multiplexer" common functions
like this.

my suggestion: make your current function a __ prefixed one, then
provide 2 small inlines that call the __ one...



From B04825 at freescale.com  Thu Mar 15 21:55:01 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Fri, 16 Mar 2012 01:55:01 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120316012711.GD6065@S2101-09.ap.freescale.net>
References: <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315130253.GA6065@S2101-09.ap.freescale.net>
 <4F61F080.4090800@freescale.com>
 <20120315142115.GB6065@S2101-09.ap.freescale.net>
 <4F621D09.2080806@freescale.com>
 <20120316012711.GD6065@S2101-09.ap.freescale.net>
Message-ID: <4F629D71.3050102@freescale.com>

Shawn Guo wrote:
> Hmm, Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
> is the binding document specifically for imx-sgtl5000 driver rather
> than for all fsl_ssi based machine drivers.  Since I have never seen
> and doubt will ever see the setup that two SSIs connect to two
> sgtl5000 codecs on any imx board, I do not see much point to update
> the documentation for that.
>
> If this is indeed a practical setup for PowerPC, it can be documented
> in the binding for PowerPC machine driver when there is future PowerPC
> machine drivers adopting the new binding.

Ok.  I was going to say that I'd like to see a template that applies to 
all SOCs with an SSI, but I guess that won't be that useful.

I'm just concerned that if there's no standard way to create bindings for 
machine drivers, we're going to end up with some kind of mess down the road.

-- 
Timur Tabi
Linux kernel developer at Freescale


From shawn.guo at linaro.org  Thu Mar 15 22:01:14 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 10:01:14 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F621C60.5090700@freescale.com>
References: <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
Message-ID: <20120316020111.GE6065@S2101-09.ap.freescale.net>

On Thu, Mar 15, 2012 at 11:44:16AM -0500, Timur Tabi wrote:
...
> Ok, fair enough.  I understand that my binding has no way of specifying
> board-specific properties, or anything that isn't directly related to the
> SSI, codec, or DMA controller.
> 
> However, I don't like the way this is being represented as a PowerPC vs.
> ARM issue, because that's just not correct.  It's an "old binding" vs "new
> binding" issue.  For example:
> 
> +	/*
> +	 * In case of imx, the machine driver uses new binding which does
> +	 * not require SSI driver to trigger machine driver's probe, but
> +	 * the pcm device needs to be registered here.
> +	 */
> +	if (ssi_private->ssi_on_imx) {

This could probably change to check whether property codec-handle is
present under SSI node to decide if it runs with "old binding" or
"new binding".

> +		ssi_private->imx_pcm_pdev =
> +			platform_device_register_simple("imx-pcm-audio",
> 
This is still IMX vs. PowerPC thing rather than "old binding" vs. "new
binding" one.

> This prohibits me from using the new binding on any future PowerPC parts,
> because it clearly says "iMX" on everything.

I think we can change it later when the future PowerPC parts come to
use the new binding.  In any case, I do not see this is an issue that
should block the whole series.

-- 
Regards,
Shawn


From B04825 at freescale.com  Thu Mar 15 22:07:42 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Fri, 16 Mar 2012 02:07:42 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120316020111.GE6065@S2101-09.ap.freescale.net>
References: <1331225990-27308-10-git-send-email-shawn.guo@linaro.org>
 <4F591B8D.8090705@freescale.com>
 <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
 <20120316020111.GE6065@S2101-09.ap.freescale.net>
Message-ID: <4F62A06C.5000304@freescale.com>

Shawn Guo wrote:

> This could probably change to check whether property codec-handle is
> present under SSI node to decide if it runs with "old binding" or
> "new binding".

I guess that's how we need to do it.  The SSI driver should not be looking 
for /sound node, but that's the most reliable way to know if we have a new 
or old binding.

>> +		ssi_private->imx_pcm_pdev =
>> +			platform_device_register_simple("imx-pcm-audio",
>>
> This is still IMX vs. PowerPC thing rather than "old binding" vs. "new
> binding" one.

What is "imx-pcm-audio"?

>> This prohibits me from using the new binding on any future PowerPC parts,
>> because it clearly says "iMX" on everything.
>
> I think we can change it later when the future PowerPC parts come to
> use the new binding.  In any case, I do not see this is an issue that
> should block the whole series.

At least get rid of any unnecessary references to "imx".

-- 
Timur Tabi
Linux kernel developer at Freescale


From shawn.guo at linaro.org  Thu Mar 15 22:23:47 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 10:23:47 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F62A06C.5000304@freescale.com>
References: <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
 <20120316020111.GE6065@S2101-09.ap.freescale.net>
 <4F62A06C.5000304@freescale.com>
Message-ID: <20120316022345.GA7632@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 02:07:42AM +0000, Tabi Timur-B04825 wrote:
...
> >> +		ssi_private->imx_pcm_pdev =
> >> +			platform_device_register_simple("imx-pcm-audio",
> >>
> > This is still IMX vs. PowerPC thing rather than "old binding" vs. "new
> > binding" one.
> 
> What is "imx-pcm-audio"?
> 
Something like "fsl-pcm-audio", but different from "fsl-pcm-audio"
will be instantiated as a hardware block by device tree,
"imx-pcm-audio" is pretty much like a ASoC wrapper for calling
dmaengine driver.  So there is no hardware block presenting this
"device" in device tree, and we need to instantiate it from cpu DAI
driver as Mark suggested.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Thu Mar 15 22:52:21 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 10:52:21 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F62A06C.5000304@freescale.com>
References: <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
 <20120316020111.GE6065@S2101-09.ap.freescale.net>
 <4F62A06C.5000304@freescale.com>
Message-ID: <20120316025219.GB7632@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 02:07:42AM +0000, Tabi Timur-B04825 wrote:
> Shawn Guo wrote:
> 
> > This could probably change to check whether property codec-handle is
> > present under SSI node to decide if it runs with "old binding" or
> > "new binding".
> 
> I guess that's how we need to do it.  The SSI driver should not be looking 
> for /sound node, but that's the most reliable way to know if we have a new 
> or old binding.
> 
...
> >> This prohibits me from using the new binding on any future PowerPC parts,
> >> because it clearly says "iMX" on everything.
> >
> > I think we can change it later when the future PowerPC parts come to
> > use the new binding.  In any case, I do not see this is an issue that
> > should block the whole series.
> 
> At least get rid of any unnecessary references to "imx".
> 
So something like this?

        /*
         * If codec-handle property is missing from SSI node, we assume
         * that the machine driver uses new binding which does not require
         * SSI driver to trigger machine driver's probe.
         */
        if (!of_get_property(np, "codec-handle", NULL)) {
                if (ssi_private->ssi_on_imx) {
                        ssi_private->imx_pcm_pdev =
                                platform_device_register_simple("imx-pcm-audio",
                                                                -1, NULL, 0);
                        if (IS_ERR(ssi_private->imx_pcm_pdev)) {
                                ret = PTR_ERR(ssi_private->imx_pcm_pdev);
                                goto error_dev;
                        }
                }
                /* success for new binding case */
                return 0;
        }

It does not reduce any reference to "imx" actually.  If you think it's
worth another iteration of the series, I will post v5 for it.

-- 
Regards,
Shawn


From aisheng.dong at freescale.com  Thu Mar 15 23:01:35 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Fri, 16 Mar 2012 11:01:35 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20321.53468.310199.875966@ipc1.ka-ro>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
Message-ID: <20120316030134.GA5161@shlinux2.ap.freescale.net>

On Thu, Mar 15, 2012 at 07:22:04PM +0800, Lothar Wa?mann wrote:
> Hi,
> 
> Dong Aisheng writes:
> > On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa?mann wrote:
> > > Hi,
> > > 
> > > Dong Aisheng writes:
> > > > On Wed, Mar 14, 2012 at 10:16:43PM +0800, s.hauer at pengutronix.de wrote:
> > > > > On Wed, Mar 14, 2012 at 08:45:23PM +0800, Dong Aisheng wrote:
> > > > > > On Wed, Mar 14, 2012 at 01:23:51AM +0800, Grant Likely wrote:
> > > [...]
> > > > > > But it seems this needs pass mac address to fec driver via platforom data which is
> > > > > > not friendly to dt.
> > > > > > 
> > > > > > Another way may be changing fec driver to get the fixed part of mac address(first
> > > > > > two bytes) from device tree and read the left dynamical part from otp which i'm not
> > > > > > sure is better enough.
> > > > > > 
> > > > > > BTW, filling with zeros seems not work since it's invalid mac address.
> > > > > 
> > > > > Yes, that's the idea of using this value...
> > > > > 
> > > > But comparing to use an invalid value, why not just do not define that
> > > > local-mac-address property?
> > > > 
> > > Because a MAC address is by definition a GLOBALLY UNIQUE IDENTIFIER
> > > which is contrary to coding a "valid" default value for it somewhere!
> > > The owner of a certain MAC address range (OUI) is responsible for
> > > ensuring the uniqueness. Thus only they may assign a specific MAC
> > > address to a specific device.
> > > 
> > Yes, you're correct.
> > So i propose to read the MAC address from MX28 OTP in fec driver instead of
> > define it in device tree in my last mail.
> > http://www.spinics.net/lists/arm-kernel/msg165040.html
> > Do you have any comment on that way?
> > 
> That patch sets the OUI to the Freescale owned MAC range. Thus only
> Freescale products may be able to use the driver.
> 
No.
My proposal is only set the fixed part(first two octets) in board dts file,
each board knows it's value, and read the left 4 octets from OCOTP dynamically.
Obviously the freeescale board dts file is only for FSL platforms.
Other platforms can define their fix part of MAC address in their dts file.

> Anyway there is no definite spec how the MAC address(es) are stored
> in the fuse map. Thus reading the MAC from there is more or less
> platform specific.
> 
It's just provide one more option since there are customers storing the MAC
in the fuse map.

> Currently I'm setting up the MAC address for our TX28 from the fuses
> in the platform code passed via platform_data, but that will obviously
> not work with DT.
> 
Non-dt can also use my proposal, then you only need to pass the fixed part of
MAC via platfrom data, the left will be read by fec driver.

> The correct way would probably be to pass the MAC from the bootloader
> via a DT blob. But that would require all bootloaders to be updated
> first to support DTS. :(
> 
But uboot will face the same problem that can not define a valid MAC
in dts, did i undertand correctly?

> An intermediate solution could be using OF_DEV_AUXDATA to pass a
> platform_data struct that may contain a MAC address set up by the
> platform code.
> 
Yes, it's a way but i'm afraid will not get accepted by dt people.

Regards
Dong Aisheng



From aisheng.dong at freescale.com  Thu Mar 15 23:05:21 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Fri, 16 Mar 2012 11:05:21 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120315112419.GA3852@pengutronix.de>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20120315112419.GA3852@pengutronix.de>
Message-ID: <20120316030521.GB5161@shlinux2.ap.freescale.net>

On Thu, Mar 15, 2012 at 07:24:19PM +0800, s.hauer at pengutronix.de wrote:
> On Thu, Mar 15, 2012 at 06:59:28PM +0800, Dong Aisheng wrote:
> > On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa?mann wrote:
> > > Hi,
> > > 
> > > Dong Aisheng writes:
> > > > On Wed, Mar 14, 2012 at 10:16:43PM +0800, s.hauer at pengutronix.de wrote:
> > > > > On Wed, Mar 14, 2012 at 08:45:23PM +0800, Dong Aisheng wrote:
> > > > > > On Wed, Mar 14, 2012 at 01:23:51AM +0800, Grant Likely wrote:
> > > [...]
> > > > > > But it seems this needs pass mac address to fec driver via platforom data which is
> > > > > > not friendly to dt.
> > > > > > 
> > > > > > Another way may be changing fec driver to get the fixed part of mac address(first
> > > > > > two bytes) from device tree and read the left dynamical part from otp which i'm not
> > > > > > sure is better enough.
> > > > > > 
> > > > > > BTW, filling with zeros seems not work since it's invalid mac address.
> > > > > 
> > > > > Yes, that's the idea of using this value...
> > > > > 
> > > > But comparing to use an invalid value, why not just do not define that
> > > > local-mac-address property?
> > > > 
> > > Because a MAC address is by definition a GLOBALLY UNIQUE IDENTIFIER
> > > which is contrary to coding a "valid" default value for it somewhere!
> > > The owner of a certain MAC address range (OUI) is responsible for
> > > ensuring the uniqueness. Thus only they may assign a specific MAC
> > > address to a specific device.
> > > 
> > Yes, you're correct.
> > So i propose to read the MAC address from MX28 OTP in fec driver instead of
> > define it in device tree in my last mail.
> > http://www.spinics.net/lists/arm-kernel/msg165040.html
> > Do you have any comment on that way?
> 
> Yes, you could do that. Otherwise it's perfectly fine to pass the MAC
> address in the device tree, it's just not ok to put specific values
> into the kernel source. You could leave the values blank and let the
Yes, correct.

> bootloader fill them in. Or you could fill in valid values before you
> compile the devicetree, but be prepared for surprises once you have
> two boards in your network and use the devicetree for both.
> 

Thanks for the info.
I will submit that patch for discussion.

Regards
Dong Aisheng



From vinod.koul at intel.com  Thu Mar 15 23:13:57 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Fri, 16 Mar 2012 08:43:57 +0530
Subject: [PATCH 1/6] dmaengine: Kconfig: fix Atmel at_hdmac entry
In-Reply-To: <7cdf1e94a17a7d872cb1eeaef812aab25b3caf40.1331826095.git.nicolas.ferre@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
 <7cdf1e94a17a7d872cb1eeaef812aab25b3caf40.1331826095.git.nicolas.ferre@atmel.com>
Message-ID: <1331867637.1727.29.camel@vkoul-udesk3>

On Thu, 2012-03-15 at 16:57 +0100, Nicolas Ferre wrote:
> Remove SoC dependency and make it generic for every Atmel ARM AT91. That will
> allow to select this driver for newer chips. Keep dependency on AT91 because of
> the use of an header file located in include/mach directory.
> Modify the comment to reflect this.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Vinod Koul <vinod.koul at linux.intel.com>
> ---
>  drivers/dma/Kconfig |    5 ++---
>  1 files changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index f1a2749..6d50f35 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -91,11 +91,10 @@ config DW_DMAC
>  
>  config AT_HDMAC
>  	tristate "Atmel AHB DMA support"
> -	depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
> +	depends on ARCH_AT91
>  	select DMA_ENGINE
>  	help
> -	  Support the Atmel AHB DMA controller.  This can be integrated in
> -	  chips such as the Atmel AT91SAM9RL.
> +	  Support the Atmel AHB DMA controller.
>  
>  config FSL_DMA
>  	tristate "Freescale Elo and Elo Plus DMA support"


-- 
~Vinod



From B04825 at freescale.com  Thu Mar 15 23:44:43 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Fri, 16 Mar 2012 03:44:43 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120316022345.GA7632@S2101-09.ap.freescale.net>
References: <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
 <20120316020111.GE6065@S2101-09.ap.freescale.net>
 <4F62A06C.5000304@freescale.com>
 <20120316022345.GA7632@S2101-09.ap.freescale.net>
Message-ID: <4F62B729.2090902@freescale.com>

Shawn Guo wrote:
>> >
> Something like "fsl-pcm-audio", but different from "fsl-pcm-audio"
> will be instantiated as a hardware block by device tree,
> "imx-pcm-audio" is pretty much like a ASoC wrapper for calling
> dmaengine driver.  So there is no hardware block presenting this
> "device" in device tree, and we need to instantiate it from cpu DAI
> driver as Mark suggested.

Wait, is this the DMA controller?  Because on PowerPC, we have device tree 
nodes for the DMA controller.  Why don't you have one on i.MX?

-- 
Timur Tabi
Linux kernel developer at Freescale


From viresh.kumar at st.com  Thu Mar 15 23:47:16 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 16 Mar 2012 09:17:16 +0530
Subject: [PATCH] watchdog/coh901327: convert to use watchdog core
In-Reply-To: <20120315212705.GH10698@spo001.leaseweb.com>
References: <1331131929-22383-1-git-send-email-linus.walleij@stericsson.com>
 <20120307164240.GA1130@pengutronix.de>
 <CACRpkdaE5HASdF27db7EfnSoaUF8mA5bWoKUhaAzSegdBKsKFQ@mail.gmail.com>
 <20120315212705.GH10698@spo001.leaseweb.com>
Message-ID: <4F62B7C4.7020702@st.com>

On 3/16/2012 2:57 AM, Wim Van Sebroeck wrote:
> Hi Linus,
> 
>> On Wed, Mar 7, 2012 at 5:42 PM, Wolfram Sang <w.sang at pengutronix.de> wrote:
>>
>>>>       case WDIOC_GETTIMELEFT:
>>>>               clk_enable(clk);
>>>>               /* Read repeatedly until the value is stable! */
>>>
>>> I was wondering if it pays to put this IOCTL to watchdog_dev and add another
>>> callback to watchdog_ops? I'd think so. Wim, Linus, what do you think?
>>
>> OK with me, shall I hack a patch?
> 
> I think Viresh did something allready.

You can find it here:

http://www.spinics.net/lists/arm-kernel/msg164285.html

-- 
viresh


From shawn.guo at linaro.org  Thu Mar 15 23:53:05 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 11:53:05 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F62B729.2090902@freescale.com>
References: <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
 <20120316020111.GE6065@S2101-09.ap.freescale.net>
 <4F62A06C.5000304@freescale.com>
 <20120316022345.GA7632@S2101-09.ap.freescale.net>
 <4F62B729.2090902@freescale.com>
Message-ID: <20120316035254.GF6065@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 03:44:43AM +0000, Tabi Timur-B04825 wrote:
> Shawn Guo wrote:
> >> >
> > Something like "fsl-pcm-audio", but different from "fsl-pcm-audio"
> > will be instantiated as a hardware block by device tree,
> > "imx-pcm-audio" is pretty much like a ASoC wrapper for calling
> > dmaengine driver.  So there is no hardware block presenting this
> > "device" in device tree, and we need to instantiate it from cpu DAI
> > driver as Mark suggested.
> 
> Wait, is this the DMA controller?  Because on PowerPC, we have device tree 
> nodes for the DMA controller.  Why don't you have one on i.MX?
> 
We do have a DMA controller node for IMX.

	sdma at 83fb0000 {
		compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
		reg = <0x83fb0000 0x4000>;
		interrupts = <6>;
	};

But it's instantiated as a dmaengine device backed by dmaengine driver
drivers/dma/imx-dma.c.  "imx-pcm-audio" will just be an ASoC dmaengine
client using dmaengine API.

-- 
Regards,
Shawn


From B04825 at freescale.com  Thu Mar 15 23:53:39 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Fri, 16 Mar 2012 03:53:39 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120316025219.GB7632@S2101-09.ap.freescale.net>
References: <20120309013216.GH2499@S2101-09.ap.freescale.net>
 <4F5FD706.8040209@freescale.com>
 <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
 <20120316020111.GE6065@S2101-09.ap.freescale.net>
 <4F62A06C.5000304@freescale.com>
 <20120316025219.GB7632@S2101-09.ap.freescale.net>
Message-ID: <4F62B941.5010306@freescale.com>

Shawn Guo wrote:
> So something like this?
>
>          /*
>           * If codec-handle property is missing from SSI node, we assume
>           * that the machine driver uses new binding which does not require
>           * SSI driver to trigger machine driver's probe.
>           */
>          if (!of_get_property(np, "codec-handle", NULL)) {
>                  if (ssi_private->ssi_on_imx) {
>                          ssi_private->imx_pcm_pdev =
>                                  platform_device_register_simple("imx-pcm-audio",
>                                                                  -1, NULL, 0);
>                          if (IS_ERR(ssi_private->imx_pcm_pdev)) {
>                                  ret = PTR_ERR(ssi_private->imx_pcm_pdev);
>                                  goto error_dev;
>                          }
>                  }
>                  /* success for new binding case */
>                  return 0;
>          }
>
> It does not reduce any reference to "imx" actually.  If you think it's
> worth another iteration of the series, I will post v5 for it.

I had something more like this in mind:

         /*
          * If codec-handle property is missing from SSI node, we assume
          * that the machine driver uses new binding which does not require
          * SSI driver to trigger machine driver's probe.
          */
         if (!of_get_property(np, "codec-handle", NULL))
		ssi_private->new_binding = true;


	if (ssi_private->ssi_on_imx) {
                 ssi_private->imx_pcm_pdev =
                 	platform_device_register_simple("imx-pcm-audio",
                                                                 -1, NULL, 0);
                         if (IS_ERR(ssi_private->imx_pcm_pdev)) {
                                 ret = PTR_ERR(ssi_private->imx_pcm_pdev);
                                 goto error_dev;
                         }
                 }
                 /* success for new binding case */
                 return 0;
         }

Well, it's not perfect, but the idea is that we keep track of new vs. old 
binding separately from imx vs. powerpc.  Although I'm thinking there 
might be a way to general the call to platform_device_register_simple. 
Maybe we could put "imx-pcm-audio" in the device tree?

-- 
Timur Tabi
Linux kernel developer at Freescale


From viresh.kumar at st.com  Fri Mar 16 00:02:18 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 16 Mar 2012 09:32:18 +0530
Subject: [PATCH v3] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <201203151140.27453.arnd@arndb.de>
References: <1331808632-22585-1-git-send-email-sr@denx.de>
 <4F61CC81.1020902@st.com> <201203151140.27453.arnd@arndb.de>
Message-ID: <4F62BB4A.9090708@st.com>

On 3/15/2012 5:10 PM, Arnd Bergmann wrote:
> I don't have the data sheet, so the bus hierarchy above is completely made up,
> but I guess you get the idea. If each bus has its own local register range, it
> may be helpful to use the ranges property to remap the reg properties in the
> way that I did in the apb example above.

Got your point.

@Stefan: You can get this information from clock.c to see which clocks have ahb as parent
and which have apb as parent.

Over that i have kept them in groups/order in the lookup array too. So that would also be
very helpful.

-- 
viresh


From shawn.guo at linaro.org  Fri Mar 16 00:05:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 12:05:11 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F62B941.5010306@freescale.com>
References: <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
 <20120316020111.GE6065@S2101-09.ap.freescale.net>
 <4F62A06C.5000304@freescale.com>
 <20120316025219.GB7632@S2101-09.ap.freescale.net>
 <4F62B941.5010306@freescale.com>
Message-ID: <20120316040509.GA7758@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 03:53:39AM +0000, Tabi Timur-B04825 wrote:
> Shawn Guo wrote:
> > So something like this?
> >
> >          /*
> >           * If codec-handle property is missing from SSI node, we assume
> >           * that the machine driver uses new binding which does not require
> >           * SSI driver to trigger machine driver's probe.
> >           */
> >          if (!of_get_property(np, "codec-handle", NULL)) {
> >                  if (ssi_private->ssi_on_imx) {
> >                          ssi_private->imx_pcm_pdev =
> >                                  platform_device_register_simple("imx-pcm-audio",
> >                                                                  -1, NULL, 0);
> >                          if (IS_ERR(ssi_private->imx_pcm_pdev)) {
> >                                  ret = PTR_ERR(ssi_private->imx_pcm_pdev);
> >                                  goto error_dev;
> >                          }
> >                  }
> >                  /* success for new binding case */
> >                  return 0;
> >          }
> >
> > It does not reduce any reference to "imx" actually.  If you think it's
> > worth another iteration of the series, I will post v5 for it.
> 
> I had something more like this in mind:
> 
>          /*
>           * If codec-handle property is missing from SSI node, we assume
>           * that the machine driver uses new binding which does not require
>           * SSI driver to trigger machine driver's probe.
>           */
>          if (!of_get_property(np, "codec-handle", NULL))
> 		ssi_private->new_binding = true;
> 
> 
> 	if (ssi_private->ssi_on_imx) {
>                  ssi_private->imx_pcm_pdev =
>                  	platform_device_register_simple("imx-pcm-audio",
>                                                                  -1, NULL, 0);
>                          if (IS_ERR(ssi_private->imx_pcm_pdev)) {
>                                  ret = PTR_ERR(ssi_private->imx_pcm_pdev);
>                                  goto error_dev;
>                          }
>                  }
>                  /* success for new binding case */
>                  return 0;
>          }
> 
> Well, it's not perfect, but the idea is that we keep track of new vs. old 
> binding separately from imx vs. powerpc.

Fine with me.

> Although I'm thinking there 
> might be a way to general the call to platform_device_register_simple. 
> Maybe we could put "imx-pcm-audio" in the device tree?
> 
It seems a little bit abuse of device tree to me.  My first choice was
to do that in imx-sgtl5000 machine driver.  But Mark disagrees.

-- 
Regards,
Shawn


From B04825 at freescale.com  Fri Mar 16 00:08:32 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Fri, 16 Mar 2012 04:08:32 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120316035254.GF6065@S2101-09.ap.freescale.net>
References: <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
 <20120316020111.GE6065@S2101-09.ap.freescale.net>
 <4F62A06C.5000304@freescale.com>
 <20120316022345.GA7632@S2101-09.ap.freescale.net>
 <4F62B729.2090902@freescale.com>
 <20120316035254.GF6065@S2101-09.ap.freescale.net>
Message-ID: <4F62BCBE.7030806@freescale.com>

Shawn Guo wrote:
> But it's instantiated as a dmaengine device backed by dmaengine driver
> drivers/dma/imx-dma.c.  "imx-pcm-audio" will just be an ASoC dmaengine
> client using dmaengine API.

So you don't have the equivalent of sound/soc/fsl_dma.c?  Don't you need 
to program the DMA controller specifically for audio?  There's no way I 
could use drivers/dma/fsldma.c for audio.

-- 
Timur Tabi
Linux kernel developer at Freescale


From shawn.guo at linaro.org  Fri Mar 16 00:14:33 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 12:14:33 +0800
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F62BCBE.7030806@freescale.com>
References: <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
 <20120316020111.GE6065@S2101-09.ap.freescale.net>
 <4F62A06C.5000304@freescale.com>
 <20120316022345.GA7632@S2101-09.ap.freescale.net>
 <4F62B729.2090902@freescale.com>
 <20120316035254.GF6065@S2101-09.ap.freescale.net>
 <4F62BCBE.7030806@freescale.com>
Message-ID: <20120316041428.GA7772@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 04:08:32AM +0000, Tabi Timur-B04825 wrote:
> Shawn Guo wrote:
> > But it's instantiated as a dmaengine device backed by dmaengine driver
> > drivers/dma/imx-dma.c.  "imx-pcm-audio" will just be an ASoC dmaengine
> > client using dmaengine API.
> 
> So you don't have the equivalent of sound/soc/fsl_dma.c?  Don't you need 
> to program the DMA controller specifically for audio?  There's no way I 
> could use drivers/dma/fsldma.c for audio.
> 
I need to program the DMA controller for audio.  But that's done through
generic dmaengine API with audio specific parameters passed in.  That's
pretty much what all snd_imx_pcm_hw_params (sound/soc/fsl/imx-pcm-dma.c)
does there.

-- 
Regards,
Shawn


From B04825 at freescale.com  Fri Mar 16 00:17:02 2012
From: B04825 at freescale.com (Tabi Timur-B04825)
Date: Fri, 16 Mar 2012 04:17:02 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <20120316041428.GA7772@S2101-09.ap.freescale.net>
References: <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
 <20120316020111.GE6065@S2101-09.ap.freescale.net>
 <4F62A06C.5000304@freescale.com>
 <20120316022345.GA7632@S2101-09.ap.freescale.net>
 <4F62B729.2090902@freescale.com>
 <20120316035254.GF6065@S2101-09.ap.freescale.net>
 <4F62BCBE.7030806@freescale.com>
 <20120316041428.GA7772@S2101-09.ap.freescale.net>
Message-ID: <4F62BEBC.9040203@freescale.com>

Shawn Guo wrote:
> I need to program the DMA controller for audio.  But that's done through
> generic dmaengine API with audio specific parameters passed in.  That's
> pretty much what all snd_imx_pcm_hw_params (sound/soc/fsl/imx-pcm-dma.c)
> does there.

Interesting.  I'll have to check that out.

-- 
Timur Tabi
Linux kernel developer at Freescale


From jason at lakedaemon.net  Fri Mar 16 00:21:21 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 04:21:21 +0000
Subject: [PATCH 1/9] ARM: orion: spi: remove enable_clock_fix which is not used
In-Reply-To: <cover.1331868507.git.jason@lakedaemon.net>
References: <cover.1331868507.git.jason@lakedaemon.net>
Message-ID: <eefe66c948eeb87f67f28ff162ad905de273a650.1331868507.git.jason@lakedaemon.net>

From: Andrew Lunn <andrew at lunn.ch>

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
---
 drivers/spi/spi-orion.c       |    5 -----
 include/linux/spi/orion_spi.h |    1 -
 2 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index 13448c8..e496f79 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -359,11 +359,6 @@ static int orion_spi_setup(struct spi_device *spi)
 
 	orion_spi = spi_master_get_devdata(spi->master);
 
-	/* Fix ac timing if required.   */
-	if (orion_spi->spi_info->enable_clock_fix)
-		orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
-				  (1 << 14));
-
 	if ((spi->max_speed_hz == 0)
 			|| (spi->max_speed_hz > orion_spi->max_speed))
 		spi->max_speed_hz = orion_spi->max_speed;
diff --git a/include/linux/spi/orion_spi.h b/include/linux/spi/orion_spi.h
index decf6d8..b4d9fa6 100644
--- a/include/linux/spi/orion_spi.h
+++ b/include/linux/spi/orion_spi.h
@@ -11,7 +11,6 @@
 
 struct orion_spi_info {
 	u32	tclk;		/* no <linux/clk.h> support yet */
-	u32	enable_clock_fix;
 };
 
 
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar 16 00:21:20 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 04:21:20 +0000
Subject: [PATCH 0/9 v5] ARM: kirkwood: fdt: convert kirkwood to fdt
In-Reply-To: <cover.1330625877.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
Message-ID: <cover.1331868507.git.jason@lakedaemon.net>

This series continues the process of converting all of the drivers initialized
from kirkwood_init() to devicetree.

The first three patches are code cleanup from Andrew Lunn and myself.

The next three patches are cleanup and prep to facilitate adding new boards
during the transition to devicetree.

The next patch moves the uarts into the bus for all kirkwood boards and leaves
enabling them and specifying clock-frequency up to the board file.

The rest of the series is the initial conversion of rtc-mv to devicetree since
it  doesn't use tclk or pinmux.  These should be safe to merge as they won't
interfere with the clk/clkdev work Andrew Lunn is working on.

Overall changes since v4:

	- rebased off of arm-soc/next/boards
	- protected dreamplug_init() in common.h
	- corrected authorship of orion-wdt resource patch to me.

Overall changes since v3:

	- squashed several fixup patches into the series (use mrvl, use
	  inclusive address sizes)
	- applied Arnd's suggestion for serial ports in kirkwood.dtsi, added my
	  idea of defining serial clock in dts.
	- moved dreamplug_init() out of board-dt.c (into board-dreamplug.c) to
	  facilitate the orderly arrival of new boards with fdt support (Jamie
	  Lentin's boards)
	- moved all non-fdt cleanups to the beginning of the series.
	- removed mv_cesa, mv_sata, and orion-ehci from this series as they
	  depend on intc/dma/clock to work properly
	- removed Ack's and Reviewed-By's on patches with significant changes
		- Grant's Ack remains on the "wdt: use resource" patch as it is
		  a reduced scope version (no fdt bindings), otherwise,
		  identical to code originally Acked.  Please let me know if
		  that's not appropriate.

Overall changes since v2:

	- added Andrew Lunn's cleanup patches
	- reshuffled to more logical order
	- wrapped all struct of_device_id[]'s in #ifdef CONFIG_OF
	- s/marvell,/mrvl,/g
	- added orion-ehci
	- added mv_sata
	- prevent clocks from gating when booting from devicetree

Drivers yet to be converted are:

	mv_cesa:    needs intc in fdt (next on list)
	mv_sata:    needs dma, intc
	orion-ehci: needs dma, intc
	orion-spi:  uses tclk
	orion-wdt:  uses tclk
	mvsdio:     uses tclk
	i2c:        uses freq_m/freq_n, not sure if that should use clk/clkdev
	mv_xor:     haven't figured out howto do shared resources/dma in fdt
	ge0/ge1:    haven't looked at it yet
	nand:       not needed for dreamplug, Jamie Lentin is working on it

Please be aware that this is a complete reshuffle of the whole series and is
based purely against arm-soc/next/boards.

Interested folks can pull from:

git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_for_3.4_v3

Andrew Lunn (2):
  ARM: orion: spi: remove enable_clock_fix which is not used
  ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data.

Jason Cooper (7):
  ARM: orion: wdt: use resource vice direct access
  ARM: kirkwood: fdt: use mrvl ticker symbol
  ARM: kirkwood: fdt: absorb kirkwood_init()
  ARM: kirkwood: fdt: facilitate new boards during fdt migration
  ARM: kirkwood: fdt: define uart[01] as disabled, enable uart0
  ARM: kirkwood: rtc-mv devicetree bindings
  ARM: kirkwood: use devicetree for rtc-mv

 arch/arm/boot/dts/kirkwood-dreamplug.dts |   13 +--
 arch/arm/boot/dts/kirkwood.dtsi          |   34 ++++++-
 arch/arm/mach-kirkwood/Makefile          |    1 +
 arch/arm/mach-kirkwood/board-dreamplug.c |  152 ++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c        |  151 +++++-------------------------
 arch/arm/mach-kirkwood/common.c          |   11 +-
 arch/arm/mach-kirkwood/common.h          |   15 +++
 arch/arm/plat-orion/common.c             |    7 +-
 arch/arm/plat-orion/include/plat/audio.h |    1 -
 drivers/rtc/rtc-mv.c                     |    9 ++
 drivers/spi/spi-orion.c                  |    5 -
 drivers/watchdog/orion_wdt.c             |   24 +++--
 include/linux/spi/orion_spi.h            |    1 -
 13 files changed, 264 insertions(+), 160 deletions(-)
 create mode 100644 arch/arm/mach-kirkwood/board-dreamplug.c

-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar 16 00:21:22 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 04:21:22 +0000
Subject: [PATCH 2/9] ARM: Kirkwood: Remove tclk from
 kirkwood_asoc_platform_data.
In-Reply-To: <cover.1331868507.git.jason@lakedaemon.net>
References: <cover.1331868507.git.jason@lakedaemon.net>
Message-ID: <720cc8b963308aed15d80bd9ccd479bb0d91185f.1331868507.git.jason@lakedaemon.net>

From: Andrew Lunn <andrew at lunn.ch>

It is not used anywhere in the sound driver.

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/mach-kirkwood/common.c          |    1 -
 arch/arm/plat-orion/include/plat/audio.h |    1 -
 2 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 77d4852..79a9fe7 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -450,7 +450,6 @@ void __init kirkwood_init(void)
 {
 	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
 		kirkwood_id(), kirkwood_tclk);
-	kirkwood_i2s_data.tclk = kirkwood_tclk;
 
 	/*
 	 * Disable propagation of mbus errors to the CPU local bus,
diff --git a/arch/arm/plat-orion/include/plat/audio.h b/arch/arm/plat-orion/include/plat/audio.h
index 885f8ab..d6a55bd 100644
--- a/arch/arm/plat-orion/include/plat/audio.h
+++ b/arch/arm/plat-orion/include/plat/audio.h
@@ -2,7 +2,6 @@
 #define __PLAT_AUDIO_H
 
 struct kirkwood_asoc_platform_data {
-	u32 tclk;
 	int burst;
 };
 #endif
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar 16 00:21:27 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 04:21:27 +0000
Subject: [PATCH 7/9] ARM: kirkwood: fdt: define uart[01] as disabled,
 enable uart0
In-Reply-To: <cover.1331868507.git.jason@lakedaemon.net>
References: <cover.1331868507.git.jason@lakedaemon.net>
Message-ID: <df6c6160b649e0f4bbf032be5428691378eda244.1331868507.git.jason@lakedaemon.net>

Define both uarts in kirkwood.dtsi as they are common to all kirkwood
SoCs.  Each board may enable all or none of them, so they are disabled
by default.  uart0 is enabled for the dreamplug.

tclk can vary for each board, so we leave it undefined in the kirkwood
dtsi.  Each board can then set it as appropriate when enabling the uart.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/boot/dts/kirkwood-dreamplug.dts |   11 +++++------
 arch/arm/boot/dts/kirkwood.dtsi          |   26 +++++++++++++++++++++++++-
 2 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 333f11b..a5376b8 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -15,11 +15,10 @@
 		bootargs = "console=ttyS0,115200n8 earlyprintk";
 	};
 
-	serial at f1012000 {
-		compatible = "ns16550a";
-		reg = <0xf1012000 0x100>;
-		reg-shift = <2>;
-		interrupts = <33>;
-		clock-frequency = <200000000>;
+	ocp at f1000000 {
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 702b955..825310b 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -2,5 +2,29 @@
 
 / {
 	compatible = "mrvl,kirkwood";
-};
 
+	ocp at f1000000 {
+		compatible = "simple-bus";
+		ranges = <0 0xf1000000 0x1000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		serial at 12000 {
+			compatible = "ns16550a";
+			reg = <0x12000 0x100>;
+			reg-shift = <2>;
+			interrupts = <33>;
+			/* set clock-frequency in board dts */
+			status = "disabled";
+		};
+
+		serial at 12100 {
+			compatible = "ns16550a";
+			reg = <0x12100 0x100>;
+			reg-shift = <2>;
+			interrupts = <34>;
+			/* set clock-frequency in board dts */
+			status = "disabled";
+		};
+	};
+};
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar 16 00:21:28 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 04:21:28 +0000
Subject: [PATCH 8/9 v2] ARM: kirkwood: rtc-mv devicetree bindings
In-Reply-To: <cover.1331868507.git.jason@lakedaemon.net>
References: <cover.1331868507.git.jason@lakedaemon.net>
Message-ID: <45356e7e743479397bb661225beb68df5dd0947d.1331868507.git.jason@lakedaemon.net>

Trivial conversion to devicetree.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes from v1:

    - added 'trivial conversion' patch description.

 drivers/rtc/rtc-mv.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c
index 768e2ed..0dd8421 100644
--- a/drivers/rtc/rtc-mv.c
+++ b/drivers/rtc/rtc-mv.c
@@ -12,6 +12,7 @@
 #include <linux/bcd.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/delay.h>
 #include <linux/gfp.h>
 #include <linux/module.h>
@@ -294,11 +295,19 @@ static int __exit mv_rtc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id rtc_mv_of_match_table[] = {
+	{ .compatible = "mrvl,orion-rtc", },
+	{}
+};
+#endif
+
 static struct platform_driver mv_rtc_driver = {
 	.remove		= __exit_p(mv_rtc_remove),
 	.driver		= {
 		.name	= "rtc-mv",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(rtc_mv_of_match_table),
 	},
 };
 
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar 16 00:21:29 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 04:21:29 +0000
Subject: [PATCH 9/9] ARM: kirkwood: use devicetree for rtc-mv
In-Reply-To: <cover.1331868507.git.jason@lakedaemon.net>
References: <cover.1331868507.git.jason@lakedaemon.net>
Message-ID: <ed16b33e93ffe131e6cfd1d2baab6168a0b6bdbd.1331868507.git.jason@lakedaemon.net>

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
Acked-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/boot/dts/kirkwood.dtsi   |    6 ++++++
 arch/arm/mach-kirkwood/board-dt.c |    1 -
 arch/arm/mach-kirkwood/common.c   |    2 +-
 arch/arm/mach-kirkwood/common.h   |    1 -
 4 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 825310b..3474ef8 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -26,5 +26,11 @@
 			/* set clock-frequency in board dts */
 			status = "disabled";
 		};
+
+		rtc at 10300 {
+			compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc";
+			reg = <0x10300 0x20>;
+			interrupts = <53>;
+		};
 	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 975ad01..1c672d9 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -43,7 +43,6 @@ static void __init kirkwood_dt_init(void)
 #endif
 
 	/* internal devices that every board has */
-	kirkwood_rtc_init();
 	kirkwood_wdt_init();
 	kirkwood_xor0_init();
 	kirkwood_xor1_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 04a7eb9..a02cae8 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -163,7 +163,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-void __init kirkwood_rtc_init(void)
+static void __init kirkwood_rtc_init(void)
 {
 	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 4737578..fa8e768 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -61,7 +61,6 @@ static inline void dreamplug_init(void) {};
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-void kirkwood_rtc_init(void);
 void kirkwood_wdt_init(void);
 void kirkwood_xor0_init(void);
 void kirkwood_xor1_init(void);
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar 16 00:21:25 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 04:21:25 +0000
Subject: [PATCH 5/9] ARM: kirkwood: fdt: absorb kirkwood_init()
In-Reply-To: <cover.1331868507.git.jason@lakedaemon.net>
References: <cover.1331868507.git.jason@lakedaemon.net>
Message-ID: <3e7f2d60b6c828d98de65c996c66728d5838f7e4.1331868507.git.jason@lakedaemon.net>

We need to absorb kirkwood_init() into kirkwood_dt_init() so that as we
convert drivers, we can remove the platform call, eg
kirkwood_rtc_init().  This maintains compatibility with non-fdt
configurations because they still call kirkwood_init() in common.c.

As drivers are converted, we will reinstate the 'static' qualifier in
common.c.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/mach-kirkwood/board-dt.c |   29 ++++++++++++++++++++++++++++-
 arch/arm/mach-kirkwood/common.c   |   12 ++++++------
 arch/arm/mach-kirkwood/common.h   |    8 ++++++++
 3 files changed, 42 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index fbe6405..9bd35ac 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -29,7 +29,9 @@
 #include <linux/spi/orion_spi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 #include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
 #include <plat/mvsdio.h>
 #include "common.h"
 #include "mpp.h"
@@ -155,7 +157,32 @@ static void __init dreamplug_init(void)
 
 static void __init kirkwood_dt_init(void)
 {
-	kirkwood_init();
+	pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
+
+	/*
+	 * Disable propagation of mbus errors to the CPU local bus,
+	 * as this causes mbus errors (which can occur for example
+	 * for PCI aborts) to throw CPU aborts, which we're not set
+	 * up to deal with.
+	 */
+	writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
+
+	kirkwood_setup_cpu_mbus();
+
+#ifdef CONFIG_CACHE_FEROCEON_L2
+	kirkwood_l2_init();
+#endif
+
+	/* internal devices that every board has */
+	kirkwood_rtc_init();
+	kirkwood_wdt_init();
+	kirkwood_xor0_init();
+	kirkwood_xor1_init();
+	kirkwood_crypto_init();
+
+#ifdef CONFIG_KEXEC
+	kexec_reinit = kirkwood_enable_pcie;
+#endif
 
 	if (of_machine_is_compatible("globalscale,dreamplug"))
 		dreamplug_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 79a9fe7..04a7eb9 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -163,7 +163,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-static void __init kirkwood_rtc_init(void)
+void __init kirkwood_rtc_init(void)
 {
 	orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
@@ -279,7 +279,7 @@ void __init kirkwood_crypto_init(void)
 /*****************************************************************************
  * XOR0
  ****************************************************************************/
-static void __init kirkwood_xor0_init(void)
+void __init kirkwood_xor0_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_XOR0;
 
@@ -291,7 +291,7 @@ static void __init kirkwood_xor0_init(void)
 /*****************************************************************************
  * XOR1
  ****************************************************************************/
-static void __init kirkwood_xor1_init(void)
+void __init kirkwood_xor1_init(void)
 {
 	kirkwood_clk_ctrl |= CGC_XOR1;
 
@@ -303,7 +303,7 @@ static void __init kirkwood_xor1_init(void)
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-static void __init kirkwood_wdt_init(void)
+void __init kirkwood_wdt_init(void)
 {
 	orion_wdt_init(kirkwood_tclk);
 }
@@ -392,7 +392,7 @@ void __init kirkwood_audio_init(void)
 /*
  * Identify device ID and revision.
  */
-static char * __init kirkwood_id(void)
+char * __init kirkwood_id(void)
 {
 	u32 dev, rev;
 
@@ -435,7 +435,7 @@ static char * __init kirkwood_id(void)
 	}
 }
 
-static void __init kirkwood_l2_init(void)
+void __init kirkwood_l2_init(void)
 {
 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
 	writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 9071a39..c382447 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -51,6 +51,14 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev
 void kirkwood_audio_init(void);
 void kirkwood_restart(char, const char *);
 
+char *kirkwood_id(void);
+void kirkwood_l2_init(void);
+void kirkwood_rtc_init(void);
+void kirkwood_wdt_init(void);
+void kirkwood_xor0_init(void);
+void kirkwood_xor1_init(void);
+void kirkwood_crypto_init(void);
+
 extern int kirkwood_tclk;
 extern struct sys_timer kirkwood_timer;
 
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar 16 00:21:23 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 04:21:23 +0000
Subject: [PATCH 3/9 v3] ARM: orion: wdt: use resource vice direct access
In-Reply-To: <cover.1331868507.git.jason@lakedaemon.net>
References: <cover.1331868507.git.jason@lakedaemon.net>
Message-ID: <04a5c4c305df36619b1cf12a3e2bb21de9378b15.1331868507.git.jason@lakedaemon.net>

Signed-off-by: Andrew Lunn <andrew at lunn.ch>
Signed-off-by: Jason Cooper <jason at lakedaemon.net>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
Acked-by: Arnd Bergmann <arnd at arndb.de>
---

Changes from v2:

    - Corrected authorship to myself.  The author was inadvertently changed to
      Andrew Lunn with a wayward 'commit --amend' during a 'rebase -i' to split
      the wdt patch.  Andrew brought it to my attention.  Thanks, Andrew!

Notes from v2:
Note: This code is the exact same as that originally Acked by Grant.  I've
simply removed the fdt bindings, as I need to hold off until common clock is
added.  If it's not appropriate to retain his Ack here, please let me know.

 arch/arm/plat-orion/common.c |    7 ++++++-
 drivers/watchdog/orion_wdt.c |   24 +++++++++++++++---------
 2 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 089899a..74daf5e 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -21,6 +21,7 @@
 #include <plat/orion_wdt.h>
 #include <plat/mv_xor.h>
 #include <plat/ehci-orion.h>
+#include <mach/bridge-regs.h>
 
 /* Fill in the resources structure and link it into the platform
    device structure. There is always a memory region, and nearly
@@ -568,13 +569,17 @@ void __init orion_spi_1_init(unsigned long mapbase,
  ****************************************************************************/
 static struct orion_wdt_platform_data orion_wdt_data;
 
+static struct resource orion_wdt_resource =
+		DEFINE_RES_MEM(TIMER_VIRT_BASE, 0x28);
+
 static struct platform_device orion_wdt_device = {
 	.name		= "orion_wdt",
 	.id		= -1,
 	.dev		= {
 		.platform_data	= &orion_wdt_data,
 	},
-	.num_resources	= 0,
+	.resource	= &orion_wdt_resource,
+	.num_resources	= 1,
 };
 
 void __init orion_wdt_init(unsigned long tclk)
diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
index 4ad78f8..1368e4c 100644
--- a/drivers/watchdog/orion_wdt.c
+++ b/drivers/watchdog/orion_wdt.c
@@ -28,9 +28,9 @@
 /*
  * Watchdog timer block registers.
  */
-#define TIMER_CTRL		(TIMER_VIRT_BASE + 0x0000)
+#define TIMER_CTRL		0x0000
 #define  WDT_EN			0x0010
-#define WDT_VAL			(TIMER_VIRT_BASE + 0x0024)
+#define WDT_VAL			0x0024
 
 #define WDT_MAX_CYCLE_COUNT	0xffffffff
 #define WDT_IN_USE		0
@@ -40,6 +40,7 @@ static int nowayout = WATCHDOG_NOWAYOUT;
 static int heartbeat = -1;		/* module parameter (seconds) */
 static unsigned int wdt_max_duration;	/* (seconds) */
 static unsigned int wdt_tclk;
+static void __iomem *wdt_reg;
 static unsigned long wdt_status;
 static DEFINE_SPINLOCK(wdt_lock);
 
@@ -48,7 +49,7 @@ static void orion_wdt_ping(void)
 	spin_lock(&wdt_lock);
 
 	/* Reload watchdog duration */
-	writel(wdt_tclk * heartbeat, WDT_VAL);
+	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
 
 	spin_unlock(&wdt_lock);
 }
@@ -60,7 +61,7 @@ static void orion_wdt_enable(void)
 	spin_lock(&wdt_lock);
 
 	/* Set watchdog duration */
-	writel(wdt_tclk * heartbeat, WDT_VAL);
+	writel(wdt_tclk * heartbeat, wdt_reg + WDT_VAL);
 
 	/* Clear watchdog timer interrupt */
 	reg = readl(BRIDGE_CAUSE);
@@ -68,9 +69,9 @@ static void orion_wdt_enable(void)
 	writel(reg, BRIDGE_CAUSE);
 
 	/* Enable watchdog timer */
-	reg = readl(TIMER_CTRL);
+	reg = readl(wdt_reg + TIMER_CTRL);
 	reg |= WDT_EN;
-	writel(reg, TIMER_CTRL);
+	writel(reg, wdt_reg + TIMER_CTRL);
 
 	/* Enable reset on watchdog */
 	reg = readl(RSTOUTn_MASK);
@@ -92,9 +93,9 @@ static void orion_wdt_disable(void)
 	writel(reg, RSTOUTn_MASK);
 
 	/* Disable watchdog timer */
-	reg = readl(TIMER_CTRL);
+	reg = readl(wdt_reg + TIMER_CTRL);
 	reg &= ~WDT_EN;
-	writel(reg, TIMER_CTRL);
+	writel(reg, wdt_reg + TIMER_CTRL);
 
 	spin_unlock(&wdt_lock);
 }
@@ -102,7 +103,7 @@ static void orion_wdt_disable(void)
 static int orion_wdt_get_timeleft(int *time_left)
 {
 	spin_lock(&wdt_lock);
-	*time_left = readl(WDT_VAL) / wdt_tclk;
+	*time_left = readl(wdt_reg + WDT_VAL) / wdt_tclk;
 	spin_unlock(&wdt_lock);
 	return 0;
 }
@@ -236,6 +237,7 @@ static struct miscdevice orion_wdt_miscdev = {
 static int __devinit orion_wdt_probe(struct platform_device *pdev)
 {
 	struct orion_wdt_platform_data *pdata = pdev->dev.platform_data;
+	struct resource *res;
 	int ret;
 
 	if (pdata) {
@@ -245,6 +247,10 @@ static int __devinit orion_wdt_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	wdt_reg = ioremap(res->start, resource_size(res));
+
 	if (orion_wdt_miscdev.parent)
 		return -EBUSY;
 	orion_wdt_miscdev.parent = &pdev->dev;
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar 16 00:21:24 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 04:21:24 +0000
Subject: [PATCH 4/9] ARM: kirkwood: fdt: use mrvl ticker symbol
In-Reply-To: <cover.1331868507.git.jason@lakedaemon.net>
References: <cover.1331868507.git.jason@lakedaemon.net>
Message-ID: <12bc9d34d737beecb2c7a0703bd779b025e94721.1331868507.git.jason@lakedaemon.net>

Also, use inclusive register size for uart0.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 arch/arm/boot/dts/kirkwood-dreamplug.dts |    4 ++--
 arch/arm/boot/dts/kirkwood.dtsi          |    2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 8a5dff8..333f11b 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -4,7 +4,7 @@
 
 / {
 	model = "Globalscale Technologies Dreamplug";
-	compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+	compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
 
 	memory {
 		device_type = "memory";
@@ -17,7 +17,7 @@
 
 	serial at f1012000 {
 		compatible = "ns16550a";
-		reg = <0xf1012000 0xff>;
+		reg = <0xf1012000 0x100>;
 		reg-shift = <2>;
 		interrupts = <33>;
 		clock-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 771c6bb..702b955 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -1,6 +1,6 @@
 /include/ "skeleton.dtsi"
 
 / {
-	compatible = "marvell,kirkwood";
+	compatible = "mrvl,kirkwood";
 };
 
-- 
1.7.3.4



From jason at lakedaemon.net  Fri Mar 16 00:21:26 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 04:21:26 +0000
Subject: [PATCH 6/9 v2] ARM: kirkwood: fdt: facilitate new boards during fdt
 migration
In-Reply-To: <cover.1331868507.git.jason@lakedaemon.net>
References: <cover.1331868507.git.jason@lakedaemon.net>
Message-ID: <232cbb0b517d8497ff1e5ad22d48ef2713b473e6.1331868507.git.jason@lakedaemon.net>

Move all dreamplug-specific code out of board-dt.c and into
board-dreamplug.c.  This way new boards that are added during the
conversion to fdt don't clutter up board-dt.c.

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---

Changes from v1:

    - This code was broken out into a separate patch so that it could apply
      cleanly to code already in arm-soc/next/boards
    - protected the declaration of dreamplug_init() in common.h with #ifdef on
      CONFIG_MACH_DREAMPLUG_DT

 arch/arm/mach-kirkwood/Makefile          |    1 +
 arch/arm/mach-kirkwood/board-dreamplug.c |  152 ++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c        |  133 +--------------------------
 arch/arm/mach-kirkwood/common.h          |    8 ++
 4 files changed, 162 insertions(+), 132 deletions(-)
 create mode 100644 arch/arm/mach-kirkwood/board-dreamplug.c

diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index acbc5e1..e299a95 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_T5325)		+= t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)		+= board-dt.o
+obj-$(CONFIG_MACH_DREAMPLUG_DT)		+= board-dreamplug.o
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
new file mode 100644
index 0000000..9854539
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2012 (C), Jason Cooper <jason at lakedaemon.net>
+ *
+ * arch/arm/mach-kirkwood/board-dreamplug.c
+ *
+ * Marvell DreamPlug Reference Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+struct mtd_partition dreamplug_partitions[] = {
+	{
+		.name	= "u-boot",
+		.size	= SZ_512K,
+		.offset = 0,
+	},
+	{
+		.name	= "u-boot env",
+		.size	= SZ_64K,
+		.offset = SZ_512K + SZ_512K,
+	},
+	{
+		.name	= "dtb",
+		.size	= SZ_64K,
+		.offset = SZ_512K + SZ_512K + SZ_512K,
+	},
+};
+
+static const struct flash_platform_data dreamplug_spi_slave_data = {
+	.type		= "mx25l1606e",
+	.name		= "spi_flash",
+	.parts		= dreamplug_partitions,
+	.nr_parts	= ARRAY_SIZE(dreamplug_partitions),
+};
+
+static struct spi_board_info __initdata dreamplug_spi_slave_info[] = {
+	{
+		.modalias	= "m25p80",
+		.platform_data	= &dreamplug_spi_slave_data,
+		.irq		= -1,
+		.max_speed_hz	= 50000000,
+		.bus_num	= 0,
+		.chip_select	= 0,
+	},
+};
+
+static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
+};
+
+static struct mv_sata_platform_data dreamplug_sata_data = {
+	.n_ports	= 1,
+};
+
+static struct mvsdio_platform_data dreamplug_mvsdio_data = {
+	/* unfortunately the CD signal has not been connected */
+};
+
+static struct gpio_led dreamplug_led_pins[] = {
+	{
+		.name			= "dreamplug:blue:bluetooth",
+		.gpio			= 47,
+		.active_low		= 1,
+	},
+	{
+		.name			= "dreamplug:green:wifi",
+		.gpio			= 48,
+		.active_low		= 1,
+	},
+	{
+		.name			= "dreamplug:green:wifi_ap",
+		.gpio			= 49,
+		.active_low		= 1,
+	},
+};
+
+static struct gpio_led_platform_data dreamplug_led_data = {
+	.leds		= dreamplug_led_pins,
+	.num_leds	= ARRAY_SIZE(dreamplug_led_pins),
+};
+
+static struct platform_device dreamplug_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &dreamplug_led_data,
+	}
+};
+
+static unsigned int dreamplug_mpp_config[] __initdata = {
+	MPP0_SPI_SCn,
+	MPP1_SPI_MOSI,
+	MPP2_SPI_SCK,
+	MPP3_SPI_MISO,
+	MPP47_GPIO,	/* Bluetooth LED */
+	MPP48_GPIO,	/* Wifi LED */
+	MPP49_GPIO,	/* Wifi AP LED */
+	0
+};
+
+void __init dreamplug_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_mpp_conf(dreamplug_mpp_config);
+
+	spi_register_board_info(dreamplug_spi_slave_info,
+				ARRAY_SIZE(dreamplug_spi_slave_info));
+	kirkwood_spi_init();
+
+	kirkwood_ehci_init();
+	kirkwood_ge00_init(&dreamplug_ge00_data);
+	kirkwood_ge01_init(&dreamplug_ge01_data);
+	kirkwood_sata_init(&dreamplug_sata_data);
+	kirkwood_sdio_init(&dreamplug_mvsdio_data);
+
+	platform_device_register(&dreamplug_leds);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 9bd35ac..975ad01 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -3,7 +3,7 @@
  *
  * arch/arm/mach-kirkwood/board-dt.c
  *
- * Marvell DreamPlug Reference Board Setup
+ * Flattened Device Tree board initialization
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
@@ -12,149 +12,18 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/orion_spi.h>
-#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
-#include <plat/mvsdio.h>
 #include "common.h"
-#include "mpp.h"
 
 static struct of_device_id kirkwood_dt_match_table[] __initdata = {
 	{ .compatible = "simple-bus", },
 	{ }
 };
 
-struct mtd_partition dreamplug_partitions[] = {
-	{
-		.name	= "u-boot",
-		.size	= SZ_512K,
-		.offset = 0,
-	},
-	{
-		.name	= "u-boot env",
-		.size	= SZ_64K,
-		.offset = SZ_512K + SZ_512K,
-	},
-	{
-		.name	= "dtb",
-		.size	= SZ_64K,
-		.offset = SZ_512K + SZ_512K + SZ_512K,
-	},
-};
-
-static const struct flash_platform_data dreamplug_spi_slave_data = {
-	.type		= "mx25l1606e",
-	.name		= "spi_flash",
-	.parts		= dreamplug_partitions,
-	.nr_parts	= ARRAY_SIZE(dreamplug_partitions),
-};
-
-static struct spi_board_info __initdata dreamplug_spi_slave_info[] = {
-	{
-		.modalias	= "m25p80",
-		.platform_data	= &dreamplug_spi_slave_data,
-		.irq		= -1,
-		.max_speed_hz	= 50000000,
-		.bus_num	= 0,
-		.chip_select	= 0,
-	},
-};
-
-static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
-};
-
-static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
-	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
-};
-
-static struct mv_sata_platform_data dreamplug_sata_data = {
-	.n_ports	= 1,
-};
-
-static struct mvsdio_platform_data dreamplug_mvsdio_data = {
-	/* unfortunately the CD signal has not been connected */
-};
-
-static struct gpio_led dreamplug_led_pins[] = {
-	{
-		.name			= "dreamplug:blue:bluetooth",
-		.gpio			= 47,
-		.active_low		= 1,
-	},
-	{
-		.name			= "dreamplug:green:wifi",
-		.gpio			= 48,
-		.active_low		= 1,
-	},
-	{
-		.name			= "dreamplug:green:wifi_ap",
-		.gpio			= 49,
-		.active_low		= 1,
-	},
-};
-
-static struct gpio_led_platform_data dreamplug_led_data = {
-	.leds		= dreamplug_led_pins,
-	.num_leds	= ARRAY_SIZE(dreamplug_led_pins),
-};
-
-static struct platform_device dreamplug_leds = {
-	.name	= "leds-gpio",
-	.id	= -1,
-	.dev	= {
-		.platform_data	= &dreamplug_led_data,
-	}
-};
-
-static unsigned int dreamplug_mpp_config[] __initdata = {
-	MPP0_SPI_SCn,
-	MPP1_SPI_MOSI,
-	MPP2_SPI_SCK,
-	MPP3_SPI_MISO,
-	MPP47_GPIO,	/* Bluetooth LED */
-	MPP48_GPIO,	/* Wifi LED */
-	MPP49_GPIO,	/* Wifi AP LED */
-	0
-};
-
-static void __init dreamplug_init(void)
-{
-	/*
-	 * Basic setup. Needs to be called early.
-	 */
-	kirkwood_mpp_conf(dreamplug_mpp_config);
-
-	spi_register_board_info(dreamplug_spi_slave_info,
-				ARRAY_SIZE(dreamplug_spi_slave_info));
-	kirkwood_spi_init();
-
-	kirkwood_ehci_init();
-	kirkwood_ge00_init(&dreamplug_ge00_data);
-	kirkwood_ge01_init(&dreamplug_ge01_data);
-	kirkwood_sata_init(&dreamplug_sata_data);
-	kirkwood_sdio_init(&dreamplug_mvsdio_data);
-
-	platform_device_register(&dreamplug_leds);
-}
-
 static void __init kirkwood_dt_init(void)
 {
 	pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index c382447..4737578 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -51,6 +51,14 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev
 void kirkwood_audio_init(void);
 void kirkwood_restart(char, const char *);
 
+/* board init functions for boards not fully converted to fdt */
+#ifdef CONFIG_MACH_DREAMPLUG_DT
+void dreamplug_init(void);
+#else
+static inline void dreamplug_init(void) {};
+#endif
+
+/* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
 void kirkwood_rtc_init(void);
-- 
1.7.3.4



From nico at fluxnic.net  Fri Mar 16 01:44:26 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 16 Mar 2012 01:44:26 -0400
Subject: [PATCH 0/2] improve debugability of early boot of the kernel
Message-ID: <1331876668-32492-1-git-send-email-nico@fluxnic.net>

Especially with the recent rework of static mappings, some people are
stuck with non booting kernels and very little to help them debug it
by themselves.  Turns out that this can be remedied with a patch I posted
a couple months ago, however this version is much improved.

This depends on commit 94e5a85b3be0 "ARM: earlier initialization of vectors
page" that can be found in Russell's tree.

[PATCH 1/2] DEBUG_LL: limit early mapping to the minimum
[PATCH 2/2] remove the debugging restrictions in devicemaps_init()


Nicolas


From nico at fluxnic.net  Fri Mar 16 01:44:27 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 16 Mar 2012 01:44:27 -0400
Subject: [PATCH 1/2] DEBUG_LL: limit early mapping to the minimum
In-Reply-To: <1331876668-32492-1-git-send-email-nico@fluxnic.net>
References: <1331876668-32492-1-git-send-email-nico@fluxnic.net>
Message-ID: <1331876668-32492-2-git-send-email-nico@fluxnic.net>

There is just no point mapping up to 512MB for a serial port.
Using a single 1MB entry is way sufficient for all users.

Signed-off-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/kernel/head.S |    9 +--------
 1 files changed, 1 insertions(+), 8 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 3bf0c7f8b0..835898e7d7 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -277,10 +277,6 @@ __create_page_tables:
 	mov	r3, r3, lsl #PMD_ORDER
 
 	add	r0, r4, r3
-	rsb	r3, r3, #0x4000			@ PTRS_PER_PGD*sizeof(long)
-	cmp	r3, #0x0800			@ limit to 512MB
-	movhi	r3, #0x0800
-	add	r6, r0, r3
 	mov	r3, r7, lsr #SECTION_SHIFT
 	ldr	r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
 	orr	r3, r7, r3, lsl #SECTION_SHIFT
@@ -289,13 +285,10 @@ __create_page_tables:
 #else
 	orr	r3, r3, #PMD_SECT_XN
 #endif
-1:	str	r3, [r0], #4
+	str	r3, [r0], #4
 #ifdef CONFIG_ARM_LPAE
 	str	r7, [r0], #4
 #endif
-	add	r3, r3, #1 << SECTION_SHIFT
-	cmp	r0, r6
-	blo	1b
 
 #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
 	/* we don't need any serial debugging mappings */
-- 
1.7.9.rc2



From nico at fluxnic.net  Fri Mar 16 01:44:28 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 16 Mar 2012 01:44:28 -0400
Subject: [PATCH 2/2] remove the debugging restrictions in devicemaps_init()
In-Reply-To: <1331876668-32492-1-git-send-email-nico@fluxnic.net>
References: <1331876668-32492-1-git-send-email-nico@fluxnic.net>
Message-ID: <1331876668-32492-3-git-send-email-nico@fluxnic.net>

More code is getting involved through devicemaps_init() these days,
including calls to printk() or BUG().  Not being able to access any
device to print out debugging information and only being presented with
a silent kernel crash in that case has become a major inconvenience
lately.

By having the active page table separate from the one being initialized,
it is possible to preserve the initial debug mapping that was set in
head.S until the final page table is ready.  Because there exists some
code that installs a partial mapping in order to probe the hardware
before installing additional mappings, it is necessary to set up the
vector mapping early which enables the fault handler to copy some of
the newly created mappings into our page table copy as needed.

This patch implements such a temporary page table copy only for
non LPAE configurations at the moment.

Signed-off-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/mm/mmu.c |   95 +++++++++++++++++++++++++++++++++++++++-------------
 1 files changed, 71 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index f77f1dbbdf..80e3a5410f 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -987,16 +987,47 @@ void __init arm_mm_memblock_reserve(void)
 #endif
 }
 
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_ARM_LPAE)
+
+/*
+ * The debug mappings will be cleared from the initial page table by
+ * devicemaps_init(), and eventually recreated via mdesc->map_io().
+ * To allow for debug devices to always remain accessible, we switch to
+ * a temporary copy of the current page table while the final one is being
+ * manipulated, and switch back once the final mappings are in place.
+ */
+static pgd_t * __init install_temp_mm(void)
+{
+	pgd_t *temp_pgd = early_alloc(PTRS_PER_PGD * sizeof(pgd_t));
+	pgd_t *init_pgd = pgd_offset_k(0);
+
+	/* copy vector and kernel space mappings */
+	pgd_val(temp_pgd[0]) = pgd_val(init_pgd[0]);
+	memcpy(temp_pgd + USER_PTRS_PER_PGD, init_pgd + USER_PTRS_PER_PGD,
+	       (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+	clean_dcache_area(temp_pgd, PTRS_PER_PGD * sizeof(pgd_t));
+	cpu_switch_mm(temp_pgd, &init_mm);
+	return temp_pgd;
+}
+
+static void __init remove_temp_mm(pgd_t *temp_pgd)
+{
+	cpu_switch_mm(init_mm.pgd, &init_mm);
+	memblock_free(__pa(temp_pgd), PTRS_PER_PGD * sizeof(pgd_t));
+}
+
+#else
+#define install_temp_mm()	(NULL)
+#define remove_temp_mm(mm)	do { (void)(mm); } while (0)
+#endif
+
 /*
- * Set up the device mappings.  Since we clear out the page tables for all
- * mappings above VMALLOC_START, we will remove any debug device mappings.
- * This means you have to be careful how you debug this function, or any
- * called function.  This means you can't use any function or debugging
- * method which may touch any device, otherwise the kernel _will_ crash.
+ * Set up the device mappings.
  */
 static void __init devicemaps_init(struct machine_desc *mdesc)
 {
 	struct map_desc map;
+	pgd_t *temp_pgd;
 	unsigned long addr;
 	void *vectors;
 
@@ -1004,10 +1035,41 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 	 * Allocate the vector page early.
 	 */
 	vectors = early_alloc(PAGE_SIZE);
-
 	early_trap_init(vectors);
 
-	for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
+	/*
+	 * Create a mapping for the machine vectors at the high-vectors
+	 * location (0xffff0000).  If we aren't using high-vectors, also
+	 * create a mapping at the low-vectors virtual address.
+	 */
+	pmd_clear(pmd_off_k(0xffff0000));
+	map.pfn = __phys_to_pfn(virt_to_phys(vectors));
+	map.virtual = 0xffff0000;
+	map.length = PAGE_SIZE;
+	map.type = MT_HIGH_VECTORS;
+	create_mapping(&map);
+
+	if (!vectors_high()) {
+		map.virtual = 0;
+		map.type = MT_LOW_VECTORS;
+		create_mapping(&map);
+	}
+
+	/*
+	 * After this point, any missing entry in our temp mm will be
+	 * populated via do_translation_fault().  This may happen if
+	 * some platform code needs to install a partial mapping to
+	 * probe the hardware in order to install more mappings.
+	 */
+	temp_pgd = install_temp_mm();
+
+	/*
+	 * Clear out the page tables for all mappings above VMALLOC_START
+	 * while preserving the high vector mapping.
+	 */
+	for (addr = VMALLOC_START; 
+	     addr < (0xffff0000UL & PMD_MASK);
+	     addr += PMD_SIZE)
 		pmd_clear(pmd_off_k(addr));
 
 	/*
@@ -1041,28 +1103,13 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 #endif
 
 	/*
-	 * Create a mapping for the machine vectors at the high-vectors
-	 * location (0xffff0000).  If we aren't using high-vectors, also
-	 * create a mapping at the low-vectors virtual address.
-	 */
-	map.pfn = __phys_to_pfn(virt_to_phys(vectors));
-	map.virtual = 0xffff0000;
-	map.length = PAGE_SIZE;
-	map.type = MT_HIGH_VECTORS;
-	create_mapping(&map);
-
-	if (!vectors_high()) {
-		map.virtual = 0;
-		map.type = MT_LOW_VECTORS;
-		create_mapping(&map);
-	}
-
-	/*
 	 * Ask the machine support to map in the statically mapped devices.
 	 */
 	if (mdesc->map_io)
 		mdesc->map_io();
 
+	remove_temp_mm(temp_pgd);
+
 	/*
 	 * Finally flush the caches and tlb to ensure that we're in a
 	 * consistent state wrt the writebuffer.  This also ensures that
-- 
1.7.9.rc2



From mturquette at linaro.org  Fri Mar 16 02:11:17 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 15 Mar 2012 23:11:17 -0700
Subject: [PATCH v7 0/3] common clk framework
Message-ID: <1331878280-2758-1-git-send-email-mturquette@linaro.org>

The common clock framework defines a common struct clk as well as an
implementation of the clk api that unifies clock operations on various
platforms and devices.

The net result is consolidation of many different struct clk definitions
and platform-specific clock framework implementations.

This series is the feature freeze for the common clock framework.
Unless any major bugs are reported this should be the final version of
this patchset.  Now is the time to add any acked-by's, reviewed-by's or
tested-by's.  I've carried over the *-by's from v6; I hope everyone is
OK with that.

Big thanks to Sascha Hauer for his changes to clk_set_rate in this
version.

Major changes since v6:
 * clk_set_rate rewritten to set clock rates from top-to-bottom
   * should also reduce pre-rate change notifier noise (thanks Sascha)
 * fixed up clk_divider's .round_rate logic (thanks Sascha)
 * removed useless locking around basic clock types
 * fixed return types for __clk_get_(enable|prepare)_count
 * some NULL pointer fixes for handling .parent_names and .parents
 * removed unnecessary checks for recursive calls in a few helpers
 * made __clk_round_rate more sane and aligned with clk_round_rate
   * parent rates are returned if .round_rate is not implemented
 * fixed CONFIG_COMMON_CLK_DEBUGFS to select DEBUG_FS
 * rebased onto Linus' v3.3-rc7 tag

Major changes since v5:
 * removed redundant HAVE_CLK_PREPARE in Kconfig
 * new CONFIG_COMMON_CLK_DISABLE_UNUSED feature
   * results in a new clk_op callback, .is_enabled
 * standardized the hw-specific locking in the basic clock types
 * export the individual ops for each basic clock type
 * improve registration for single-parent basic clocks (thanks Sascha)
 * fixed bugs in gate clock's static initializers (thanks Andrew)
 * overall improvements to Documentation/clk.txt
 * rebased onto Linus' v3.3-rc6 tag

Major changes since v4:
 * rolled in TGLX's comments on overall design.  We now have,
   * proper handling of root clocks and orphan clocks
   * multi-parent clocks are handled in the core
   * struct clk is shielded from struct clk_foo and vice versa
     * this is a return to the previous struct clk_hw design
 * split basic clock types out into separate files
 * split headers up by purpose
   * clk.h remains the driver-level interface
     * declarations for rate change notifiers are the only additions
   * clk-provider.h is primary header for implementing clock operations
   * clk-private.h allows for static initialization of clock data
 * validation and bug fixes
 * rebased onto Linus' v3.3-rc5 tag

Patches can be pulled from:
git://git.linaro.org/people/mturquette/linux.git v3.3-rc7-clkv7

v6 can be found at,
http://article.gmane.org/gmane.linux.kernel/1265022

v5 can be found at,
http://article.gmane.org/gmane.linux.kernel/1261472

v4 can be found at,
http://article.gmane.org/gmane.linux.linaro.devel/8896/

v3 can be found at,
http://article.gmane.org/gmane.linux.kernel/1218622

Mike Turquette (3):
  Documentation: common clk API
  clk: introduce the common clock framework
  clk: basic clock hardware types

 Documentation/clk.txt        |  233 +++++++
 drivers/clk/Kconfig          |   40 ++
 drivers/clk/Makefile         |    2 +
 drivers/clk/clk-divider.c    |  200 ++++++
 drivers/clk/clk-fixed-rate.c |   82 +++
 drivers/clk/clk-gate.c       |  150 +++++
 drivers/clk/clk-mux.c        |  116 ++++
 drivers/clk/clk.c            | 1461 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-private.h  |  196 ++++++
 include/linux/clk-provider.h |  300 +++++++++
 include/linux/clk.h          |   68 ++-
 11 files changed, 2843 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/clk.txt
 create mode 100644 drivers/clk/clk-divider.c
 create mode 100644 drivers/clk/clk-fixed-rate.c
 create mode 100644 drivers/clk/clk-gate.c
 create mode 100644 drivers/clk/clk-mux.c
 create mode 100644 drivers/clk/clk.c
 create mode 100644 include/linux/clk-private.h
 create mode 100644 include/linux/clk-provider.h

-- 
1.7.5.4



From mturquette at linaro.org  Fri Mar 16 02:11:18 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 15 Mar 2012 23:11:18 -0700
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
Message-ID: <1331878280-2758-2-git-send-email-mturquette@linaro.org>

Provide documentation for the common clk structures and APIs.  This code
can be found in drivers/clk/ and include/linux/clk*.h.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Mike Turquette <mturquette at ti.com>
Reviewed-by: Andrew Lunn <andrew at lunn.ch>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
---
No changes since v6

Changes since v5:
 * __clk_init must be called for statically initialized clocks
 * added "clk_ops matrix" to better clarify which ops are mandatory

 Documentation/clk.txt |  233 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 233 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/clk.txt

diff --git a/Documentation/clk.txt b/Documentation/clk.txt
new file mode 100644
index 0000000..1943fae
--- /dev/null
+++ b/Documentation/clk.txt
@@ -0,0 +1,233 @@
+		The Common Clk Framework
+		Mike Turquette <mturquette at ti.com>
+
+This document endeavours to explain the common clk framework details,
+and how to port a platform over to this framework.  It is not yet a
+detailed explanation of the clock api in include/linux/clk.h, but
+perhaps someday it will include that information.
+
+	Part 1 - introduction and interface split
+
+The common clk framework is an interface to control the clock nodes
+available on various devices today.  This may come in the form of clock
+gating, rate adjustment, muxing or other operations.  This framework is
+enabled with the CONFIG_COMMON_CLK option.
+
+The interface itself is divided into two halves, each shielded from the
+details of its counterpart.  First is the common definition of struct
+clk which unifies the framework-level accounting and infrastructure that
+has traditionally been duplicated across a variety of platforms.  Second
+is a common implementation of the clk.h api, defined in
+drivers/clk/clk.c.  Finally there is struct clk_ops, whose operations
+are invoked by the clk api implementation.
+
+The second half of the interface is comprised of the hardware-specific
+callbacks registered with struct clk_ops and the corresponding
+hardware-specific structures needed to model a particular clock.  For
+the remainder of this document any reference to a callback in struct
+clk_ops, such as .enable or .set_rate, implies the hardware-specific
+implementation of that code.  Likewise, references to struct clk_foo
+serve as a convenient shorthand for the implementation of the
+hardware-specific bits for the hypothetical "foo" hardware.
+
+Tying the two halves of this interface together is struct clk_hw, which
+is defined in struct clk_foo and pointed to within struct clk.  This
+allows easy for navigation between the two discrete halves of the common
+clock interface.
+
+	Part 2 - common data structures and api
+
+Below is the common struct clk definition from
+include/linux/clk-private.h, modified for brevity:
+
+	struct clk {
+		const char		*name;
+		const struct clk_ops	*ops;
+		struct clk_hw		*hw;
+		char			**parent_names;
+		struct clk		**parents;
+		struct clk		*parent;
+		struct hlist_head	children;
+		struct hlist_node	child_node;
+		...
+	};
+
+The members above make up the core of the clk tree topology.  The clk
+api itself defines several driver-facing functions which operate on
+struct clk.  That api is documented in include/linux/clk.h.
+
+Platforms and devices utilizing the common struct clk use the struct
+clk_ops pointer in struct clk to perform the hardware-specific parts of
+the operations defined in clk.h:
+
+	struct clk_ops {
+		int		(*prepare)(struct clk_hw *hw);
+		void		(*unprepare)(struct clk_hw *hw);
+		int		(*enable)(struct clk_hw *hw);
+		void		(*disable)(struct clk_hw *hw);
+		int		(*is_enabled)(struct clk_hw *hw);
+		unsigned long	(*recalc_rate)(struct clk_hw *hw,
+						unsigned long parent_rate);
+		long		(*round_rate)(struct clk_hw *hw, unsigned long,
+						unsigned long *);
+		int		(*set_parent)(struct clk_hw *hw, u8 index);
+		u8		(*get_parent)(struct clk_hw *hw);
+		int		(*set_rate)(struct clk_hw *hw, unsigned long);
+		void		(*init)(struct clk_hw *hw);
+	};
+
+	Part 3 - hardware clk implementations
+
+The strength of the common struct clk comes from its .ops and .hw pointers
+which abstract the details of struct clk from the hardware-specific bits, and
+vice versa.  To illustrate consider the simple gateable clk implementation in
+drivers/clk/clk-gate.c:
+
+struct clk_gate {
+	struct clk_hw	hw;
+	void __iomem    *reg;
+	u8              bit_idx;
+	...
+};
+
+struct clk_gate contains struct clk_hw hw as well as hardware-specific
+knowledge about which register and bit controls this clk's gating.
+Nothing about clock topology or accounting, such as enable_count or
+notifier_count, is needed here.  That is all handled by the common
+framework code and struct clk.
+
+Let's walk through enabling this clk from driver code:
+
+	struct clk *clk;
+	clk = clk_get(NULL, "my_gateable_clk");
+
+	clk_prepare(clk);
+	clk_enable(clk);
+
+The call graph for clk_enable is very simple:
+
+clk_enable(clk);
+	clk->ops->enable(clk->hw);
+	[resolves to...]
+		clk_gate_enable(hw);
+		[resolves struct clk gate with to_clk_gate(hw)]
+			clk_gate_set_bit(gate);
+
+And the definition of clk_gate_set_bit:
+
+static void clk_gate_set_bit(struct clk_gate *gate)
+{
+	u32 reg;
+
+	reg = __raw_readl(gate->reg);
+	reg |= BIT(gate->bit_idx);
+	writel(reg, gate->reg);
+}
+
+Note that to_clk_gate is defined as:
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, clk)
+
+This pattern of abstraction is used for every clock hardware
+representation.
+
+	Part 4 - supporting your own clk hardware
+
+When implementing support for a new type of clock it only necessary to
+include the following header:
+
+#include <linux/clk-provider.h>
+
+include/linux/clk.h is included within that header and clk-private.h
+must never be included from the code which implements the operations for
+a clock.  More on that below in Part 5.
+
+To construct a clk hardware structure for your platform you must define
+the following:
+
+struct clk_foo {
+	struct clk_hw hw;
+	... hardware specific data goes here ...
+};
+
+To take advantage of your data you'll need to support valid operations
+for your clk:
+
+struct clk_ops clk_foo_ops {
+	.enable		= &clk_foo_enable;
+	.disable	= &clk_foo_disable;
+};
+
+Implement the above functions using container_of:
+
+#define to_clk_foo(_hw) container_of(_hw, struct clk_foo, hw)
+
+int clk_foo_enable(struct clk_hw *hw)
+{
+	struct clk_foo *foo;
+
+	foo = to_clk_foo(hw);
+
+	... perform magic on foo ...
+
+	return 0;
+};
+
+Below is a matrix detailing which clk_ops are mandatory based upon the
+hardware capbilities of that clock.  A cell marked as "y" means
+mandatory, a cell marked as "n" implies that either including that
+callback is invalid or otherwise uneccesary.  Empty cells are either
+optional or must be evaluated on a case-by-case basis.
+
+                           clock hardware characteristics
+	     -----------------------------------------------------------
+             | gate | change rate | single parent | multiplexer | root |
+             |------|-------------|---------------|-------------|------|
+.prepare     |      |             |               |             |      |
+.unprepare   |      |             |               |             |      |
+             |      |             |               |             |      |
+.enable      | y    |             |               |             |      |
+.disable     | y    |             |               |             |      |
+.is_enabled  | y    |             |               |             |      |
+             |      |             |               |             |      |
+.recalc_rate |      | y           |               |             |      |
+.round_rate  |      | y           |               |             |      |
+.set_rate    |      | y           |               |             |      |
+             |      |             |               |             |      |
+.set_parent  |      |             | n             | y           | n    |
+.get_parent  |      |             | n             | y           | n    |
+             |      |             |               |             |      |
+.init        |      |             |               |             |      |
+	     -----------------------------------------------------------
+
+Finally, register your clock at run-time with a hardware-specific
+registration function.  This function simply populates struct clk_foo's
+data and then passes the common struct clk parameters to the framework
+with a call to:
+
+clk_register(...)
+
+See the basic clock types in drivers/clk/clk-*.c for examples.
+
+	Part 5 - static initialization of clock data
+
+For platforms with many clocks (often numbering into the hundreds) it
+may be desirable to statically initialize some clock data.  This
+presents a problem since the definition of struct clk should be hidden
+from everyone except for the clock core in drivers/clk/clk.c.
+
+To get around this problem struct clk's definition is exposed in
+include/linux/clk-private.h along with some macros for more easily
+initializing instances of the basic clock types.  These clocks must
+still be initialized with the common clock framework via a call to
+__clk_init.
+
+clk-private.h must NEVER be included by code which implements struct
+clk_ops callbacks, nor must it be included by any logic which pokes
+around inside of struct clk at run-time.  To do so is a layering
+violation.
+
+To better enforce this policy, always follow this simple rule: any
+statically initialized clock data MUST be defined in a separate file
+from the logic that implements its ops.  Basically separate the logic
+from the data and all is well.
-- 
1.7.5.4



From mturquette at linaro.org  Fri Mar 16 02:11:20 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 15 Mar 2012 23:11:20 -0700
Subject: [PATCH v7 3/3] clk: basic clock hardware types
In-Reply-To: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
Message-ID: <1331878280-2758-4-git-send-email-mturquette@linaro.org>

Many platforms support simple gateable clocks, fixed-rate clocks,
adjustable divider clocks and multi-parent multiplexer clocks.

This patch introduces basic clock types for the above-mentioned hardware
which share some common characteristics.

Based on original work by Jeremy Kerr and contribution by Jamie Iles.
Dividers and multiplexor clocks originally contributed by Richard Zhao &
Sascha Hauer.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Mike Turquette <mturquette at ti.com>
Reviewed-by: Andrew Lunn <andrew at lunn.ch>
Tested-by: Andrew Lunn <andrew at lunn.ch>
Reviewed-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Jamie Iles <jamie at jamieiles.com>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
---
Changes since v6:
 * fixed up clk_divider's .round_rate logic (thanks Sascha)
 * removed useless locking around basic clock types

Changes since v5:
 * standardized the hw-specific locking in the basic clock types
 * export the individual ops for each basic clock type
 * improve registration for single-parent basic clocks (thanks Sascha)
 * fixed bugs in gate clock's static initializers (thanks Andrew)

 drivers/clk/Makefile         |    3 +-
 drivers/clk/clk-divider.c    |  200 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/clk-fixed-rate.c |   82 +++++++++++++++++
 drivers/clk/clk-gate.c       |  150 +++++++++++++++++++++++++++++++
 drivers/clk/clk-mux.c        |  116 ++++++++++++++++++++++++
 include/linux/clk-private.h  |  124 ++++++++++++++++++++++++++
 include/linux/clk-provider.h |  127 ++++++++++++++++++++++++++
 7 files changed, 801 insertions(+), 1 deletions(-)
 create mode 100644 drivers/clk/clk-divider.c
 create mode 100644 drivers/clk/clk-fixed-rate.c
 create mode 100644 drivers/clk/clk-gate.c
 create mode 100644 drivers/clk/clk-mux.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ff362c4..1f736bc 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,3 +1,4 @@
 
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
-obj-$(CONFIG_COMMON_CLK)	+= clk.o
+obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
+				   clk-mux.o clk-divider.o
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
new file mode 100644
index 0000000..d5ac6a7
--- /dev/null
+++ b/drivers/clk/clk-divider.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Adjustable divider clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+/*
+ * DOC: basic adjustable divider clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is adjustable.  clk->rate = parent->rate / divisor
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
+
+#define div_mask(d)	((1 << (d->width)) - 1)
+
+static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	unsigned int div;
+
+	div = readl(divider->reg) >> divider->shift;
+	div &= div_mask(divider);
+
+	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
+		div++;
+
+	return parent_rate / div;
+}
+EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
+
+/*
+ * The reverse of DIV_ROUND_UP: The maximum number which
+ * divided by m is r
+ */
+#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
+
+static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+		unsigned long *best_parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	int i, bestdiv = 0;
+	unsigned long parent_rate, best = 0, now, maxdiv;
+
+	if (!rate)
+		rate = 1;
+
+	maxdiv = (1 << divider->width);
+
+	if (divider->flags & CLK_DIVIDER_ONE_BASED)
+		maxdiv--;
+
+	if (!best_parent_rate) {
+		parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
+		bestdiv = DIV_ROUND_UP(parent_rate, rate);
+		bestdiv = bestdiv == 0 ? 1 : bestdiv;
+		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+		return bestdiv;
+	}
+
+	/*
+	 * The maximum divider we can use without overflowing
+	 * unsigned long in rate * i below
+	 */
+	maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+	for (i = 1; i <= maxdiv; i++) {
+		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
+				MULT_ROUND_UP(rate, i));
+		now = parent_rate / i;
+		if (now <= rate && now > best) {
+			bestdiv = i;
+			best = now;
+			*best_parent_rate = parent_rate;
+		}
+	}
+
+	if (!bestdiv) {
+		bestdiv = (1 << divider->width);
+		if (divider->flags & CLK_DIVIDER_ONE_BASED)
+			bestdiv--;
+		*best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
+	}
+
+	return bestdiv;
+}
+
+static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	int div;
+	div = clk_divider_bestdiv(hw, rate, prate);
+
+	if (prate)
+		return *prate / div;
+	else {
+		unsigned long r;
+		r = __clk_get_rate(__clk_get_parent(hw->clk));
+		return r / div;
+	}
+}
+EXPORT_SYMBOL_GPL(clk_divider_round_rate);
+
+static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	unsigned int div;
+	unsigned long flags = 0;
+	u32 val;
+
+	div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate;
+
+	if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
+		div--;
+
+	if (div > div_mask(divider))
+		div = div_mask(divider);
+
+	if (divider->lock)
+		spin_lock_irqsave(divider->lock, flags);
+
+	val = readl(divider->reg);
+	val &= ~(div_mask(divider) << divider->shift);
+	val |= div << divider->shift;
+	writel(val, divider->reg);
+
+	if (divider->lock)
+		spin_unlock_irqrestore(divider->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(clk_divider_set_rate);
+
+struct clk_ops clk_divider_ops = {
+	.recalc_rate = clk_divider_recalc_rate,
+	.round_rate = clk_divider_round_rate,
+	.set_rate = clk_divider_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_divider_ops);
+
+struct clk *clk_register_divider(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_divider_flags, spinlock_t *lock)
+{
+	struct clk_divider *div;
+	struct clk *clk;
+
+	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
+
+	if (!div) {
+		pr_err("%s: could not allocate divider clk\n", __func__);
+		return NULL;
+	}
+
+	/* struct clk_divider assignments */
+	div->reg = reg;
+	div->shift = shift;
+	div->width = width;
+	div->flags = clk_divider_flags;
+	div->lock = lock;
+
+	if (parent_name) {
+		div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
+		if (!div->parent[0])
+			goto out;
+	}
+
+	clk = clk_register(dev, name,
+			&clk_divider_ops, &div->hw,
+			div->parent,
+			(parent_name ? 1 : 0),
+			flags);
+	if (clk)
+		return clk;
+
+out:
+	kfree(div->parent[0]);
+	kfree(div);
+
+	return NULL;
+}
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
new file mode 100644
index 0000000..90c79fb
--- /dev/null
+++ b/drivers/clk/clk-fixed-rate.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Fixed rate clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+/*
+ * DOC: basic fixed-rate clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parents are prepared
+ * enable - clk_enable only ensures parents are enabled
+ * rate - rate is always a fixed value.  No clk_set_rate support
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
+
+static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	return to_clk_fixed_rate(hw)->fixed_rate;
+}
+EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate);
+
+struct clk_ops clk_fixed_rate_ops = {
+	.recalc_rate = clk_fixed_rate_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
+
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		unsigned long fixed_rate)
+{
+	struct clk_fixed_rate *fixed;
+	char **parent_names = NULL;
+	u8 len;
+
+	fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
+
+	if (!fixed) {
+		pr_err("%s: could not allocate fixed clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_fixed_rate assignments */
+	fixed->fixed_rate = fixed_rate;
+
+	if (parent_name) {
+		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
+
+		if (! parent_names)
+			goto out;
+
+		len = sizeof(char) * strlen(parent_name);
+
+		parent_names[0] = kmalloc(len, GFP_KERNEL);
+
+		if (!parent_names[0])
+			goto out;
+
+		strncpy(parent_names[0], parent_name, len);
+	}
+
+out:
+	return clk_register(dev, name,
+			&clk_fixed_rate_ops, &fixed->hw,
+			parent_names,
+			(parent_name ? 1 : 0),
+			flags);
+}
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
new file mode 100644
index 0000000..b5902e2
--- /dev/null
+++ b/drivers/clk/clk-gate.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Gated clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+/**
+ * DOC: basic gatable clock which can gate and ungate it's ouput
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional & control gating
+ * rate - inherits rate from parent.  No clk_set_rate support
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+
+static void clk_gate_set_bit(struct clk_gate *gate)
+{
+	u32 reg;
+	unsigned long flags = 0;
+
+	if (gate->lock)
+		spin_lock_irqsave(gate->lock, flags);
+
+	reg = readl(gate->reg);
+	reg |= BIT(gate->bit_idx);
+	writel(reg, gate->reg);
+
+	if (gate->lock)
+		spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static void clk_gate_clear_bit(struct clk_gate *gate)
+{
+	u32 reg;
+	unsigned long flags = 0;
+
+	if (gate->lock)
+		spin_lock_irqsave(gate->lock, flags);
+
+	reg = readl(gate->reg);
+	reg &= ~BIT(gate->bit_idx);
+	writel(reg, gate->reg);
+
+	if (gate->lock)
+		spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int clk_gate_enable(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+
+	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+		clk_gate_clear_bit(gate);
+	else
+		clk_gate_set_bit(gate);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(clk_gate_enable);
+
+static void clk_gate_disable(struct clk_hw *hw)
+{
+	struct clk_gate *gate = to_clk_gate(hw);
+
+	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+		clk_gate_set_bit(gate);
+	else
+		clk_gate_clear_bit(gate);
+}
+EXPORT_SYMBOL_GPL(clk_gate_disable);
+
+static int clk_gate_is_enabled(struct clk_hw *hw)
+{
+	u32 reg;
+	struct clk_gate *gate = to_clk_gate(hw);
+
+	reg = readl(gate->reg);
+
+	/* if a set bit disables this clk, flip it before masking */
+	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+		reg ^= BIT(gate->bit_idx);
+
+	reg &= BIT(gate->bit_idx);
+
+	return reg ? 1 : 0;
+}
+EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
+
+struct clk_ops clk_gate_ops = {
+	.enable = clk_gate_enable,
+	.disable = clk_gate_disable,
+	.is_enabled = clk_gate_is_enabled,
+};
+EXPORT_SYMBOL_GPL(clk_gate_ops);
+
+struct clk *clk_register_gate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 bit_idx,
+		u8 clk_gate_flags, spinlock_t *lock)
+{
+	struct clk_gate *gate;
+	struct clk *clk;
+
+	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+
+	if (!gate) {
+		pr_err("%s: could not allocate gated clk\n", __func__);
+		return NULL;
+	}
+
+	/* struct clk_gate assignments */
+	gate->reg = reg;
+	gate->bit_idx = bit_idx;
+	gate->flags = clk_gate_flags;
+	gate->lock = lock;
+
+	if (parent_name) {
+		gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
+		if (!gate->parent[0])
+			goto out;
+	}
+
+	clk = clk_register(dev, name,
+			&clk_gate_ops, &gate->hw,
+			gate->parent,
+			(parent_name ? 1 : 0),
+			flags);
+	if (clk)
+		return clk;
+out:
+	kfree(gate->parent[0]);
+	kfree(gate);
+
+	return NULL;
+}
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
new file mode 100644
index 0000000..c71ad1f
--- /dev/null
+++ b/drivers/clk/clk-mux.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
+ * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao at linaro.org>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Simple multiplexer clock implementation
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+/*
+ * DOC: basic adjustable multiplexer clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is only affected by parent switching.  No clk_set_rate support
+ * parent - parent is adjustable through clk_set_parent
+ */
+
+#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
+
+static u8 clk_mux_get_parent(struct clk_hw *hw)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	u32 val;
+
+	/*
+	 * FIXME need a mux-specific flag to determine if val is bitwise or numeric
+	 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
+	 * to 0x7 (index starts at one)
+	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
+	 * val = 0x4 really means "bit 2, index starts at bit 0"
+	 */
+	val = readl(mux->reg) >> mux->shift;
+	val &= (1 << mux->width) - 1;
+
+	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
+		val = ffs(val) - 1;
+
+	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
+		val--;
+
+	if (val >= __clk_get_num_parents(hw->clk))
+		return -EINVAL;
+
+	return val;
+}
+EXPORT_SYMBOL_GPL(clk_mux_get_parent);
+
+static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct clk_mux *mux = to_clk_mux(hw);
+	u32 val;
+	unsigned long flags = 0;
+
+	if (mux->flags & CLK_MUX_INDEX_BIT)
+		index = (1 << ffs(index));
+
+	if (mux->flags & CLK_MUX_INDEX_ONE)
+		index++;
+
+	if (mux->lock)
+		spin_lock_irqsave(mux->lock, flags);
+
+	val = readl(mux->reg);
+	val &= ~(((1 << mux->width) - 1) << mux->shift);
+	val |= index << mux->shift;
+	writel(val, mux->reg);
+
+	if (mux->lock)
+		spin_unlock_irqrestore(mux->lock, flags);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(clk_mux_set_parent);
+
+struct clk_ops clk_mux_ops = {
+	.get_parent = clk_mux_get_parent,
+	.set_parent = clk_mux_set_parent,
+};
+EXPORT_SYMBOL_GPL(clk_mux_ops);
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+		char **parent_names, u8 num_parents, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_mux_flags, spinlock_t *lock)
+{
+	struct clk_mux *mux;
+
+	mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL);
+
+	if (!mux) {
+		pr_err("%s: could not allocate mux clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_mux assignments */
+	mux->reg = reg;
+	mux->shift = shift;
+	mux->width = width;
+	mux->flags = clk_mux_flags;
+	mux->lock = lock;
+
+	return clk_register(dev, name, &clk_mux_ops, &mux->hw,
+			parent_names, num_parents, flags);
+}
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index e2cce6f..5e4312b 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -46,6 +46,130 @@ struct clk {
 #endif
 };
 
+/*
+ * DOC: Basic clock implementations common to many platforms
+ *
+ * Each basic clock hardware type is comprised of a structure describing the
+ * clock hardware, implementations of the relevant callbacks in struct clk_ops,
+ * unique flags for that hardware type, a registration function and an
+ * alternative macro for static initialization
+ */
+
+extern struct clk_ops clk_fixed_rate_ops;
+
+#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate,		\
+				_fixed_rate_flags)		\
+	static struct clk _name;				\
+	static char *_name##_parent_names[] = {};		\
+	static struct clk_fixed_rate _name##_hw = {		\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.fixed_rate = _rate,				\
+		.flags = _fixed_rate_flags,			\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_fixed_rate_ops,			\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _name##_parent_names,		\
+		.num_parents =					\
+			ARRAY_SIZE(_name##_parent_names),	\
+		.flags = _flags,				\
+	};
+
+extern struct clk_ops clk_gate_ops;
+
+#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,	\
+				_flags, _reg, _bit_idx,		\
+				_gate_flags, _lock)		\
+	static struct clk _name;				\
+	static char *_name##_parent_names[] = {			\
+		_parent_name,					\
+	};							\
+	static struct clk *_name##_parents[] = {		\
+		_parent_ptr,					\
+	};							\
+	static struct clk_gate _name##_hw = {			\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.reg = _reg,					\
+		.bit_idx = _bit_idx,				\
+		.flags = _gate_flags,				\
+		.lock = _lock,					\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_gate_ops,				\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _name##_parent_names,		\
+		.num_parents =					\
+			ARRAY_SIZE(_name##_parent_names),	\
+		.parents = _name##_parents,			\
+		.flags = _flags,				\
+	};
+
+extern struct clk_ops clk_divider_ops;
+
+#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
+				_flags, _reg, _shift, _width,	\
+				_divider_flags, _lock)		\
+	static struct clk _name;				\
+	static char *_name##_parent_names[] = {			\
+		_parent_name,					\
+	};							\
+	static struct clk *_name##_parents[] = {		\
+		_parent_ptr,					\
+	};							\
+	static struct clk_divider _name##_hw = {		\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.reg = _reg,					\
+		.shift = _shift,				\
+		.width = _width,				\
+		.flags = _divider_flags,			\
+		.lock = _lock,					\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_divider_ops,			\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _name##_parent_names,		\
+		.num_parents =					\
+			ARRAY_SIZE(_name##_parent_names),	\
+		.parents = _name##_parents,			\
+		.flags = _flags,				\
+	};
+
+extern struct clk_ops clk_mux_ops;
+
+#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags,	\
+				_reg, _shift, _width,		\
+				_mux_flags, _lock)		\
+	static struct clk _name;				\
+	static struct clk_mux _name##_hw = {			\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.reg = _reg,					\
+		.shift = _shift,				\
+		.width = _width,				\
+		.flags = _mux_flags,				\
+		.lock = _lock,					\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_mux_ops,				\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _parent_names,			\
+		.num_parents =					\
+			ARRAY_SIZE(_parent_names),		\
+		.parents = _parents,				\
+		.flags = _flags,				\
+	};
+
 /**
  * __clk_init - initialize the data structures in a struct clk
  * @dev:	device initializing this clk, placeholder for now
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index b18b0e7..5508897 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -129,6 +129,133 @@ struct clk_ops {
 	void		(*init)(struct clk_hw *hw);
 };
 
+/*
+ * DOC: Basic clock implementations common to many platforms
+ *
+ * Each basic clock hardware type is comprised of a structure describing the
+ * clock hardware, implementations of the relevant callbacks in struct clk_ops,
+ * unique flags for that hardware type, a registration function and an
+ * alternative macro for static initialization
+ */
+
+/**
+ * struct clk_fixed_rate - fixed-rate clock
+ * @hw:		handle between common and hardware-specific interfaces
+ * @fixed_rate:	constant frequency of clock
+ */
+struct clk_fixed_rate {
+	struct		clk_hw hw;
+	unsigned long	fixed_rate;
+	u8		flags;
+};
+
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		unsigned long fixed_rate);
+
+/**
+ * struct clk_gate - gating clock
+ *
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register controlling gate
+ * @bit_idx:	single bit controlling gate
+ * @flags:	hardware-specific flags
+ * @lock:	register lock
+ *
+ * Clock which can gate its output.  Implements .enable & .disable
+ *
+ * Flags:
+ * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
+ * 	enable the clock.  Setting this flag does the opposite: setting the bit
+ * 	disable the clock and clearing it enables the clock
+ */
+struct clk_gate {
+	struct clk_hw hw;
+	void __iomem	*reg;
+	u8		bit_idx;
+	u8		flags;
+	spinlock_t	*lock;
+	char		*parent[1];
+};
+
+#define CLK_GATE_SET_TO_DISABLE		BIT(0)
+
+struct clk *clk_register_gate(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 bit_idx,
+		u8 clk_gate_flags, spinlock_t *lock);
+
+/**
+ * struct clk_divider - adjustable divider clock
+ *
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register containing the divider
+ * @shift:	shift to the divider bit field
+ * @width:	width of the divider bit field
+ * @lock:	register lock
+ *
+ * Clock with an adjustable divider affecting its output frequency.  Implements
+ * .recalc_rate, .set_rate and .round_rate
+ *
+ * Flags:
+ * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
+ * 	register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
+ * 	the raw value read from the register, with the value of zero considered
+ * 	invalid
+ * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
+ * 	the hardware register
+ */
+struct clk_divider {
+	struct clk_hw	hw;
+	void __iomem	*reg;
+	u8		shift;
+	u8		width;
+	u8		flags;
+	spinlock_t	*lock;
+	char		*parent[1];
+};
+
+#define CLK_DIVIDER_ONE_BASED		BIT(0)
+#define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
+
+struct clk *clk_register_divider(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_divider_flags, spinlock_t *lock);
+
+/**
+ * struct clk_mux - multiplexer clock
+ *
+ * @hw:		handle between common and hardware-specific interfaces
+ * @reg:	register controlling multiplexer
+ * @shift:	shift to multiplexer bit field
+ * @width:	width of mutliplexer bit field
+ * @num_clks:	number of parent clocks
+ * @lock:	register lock
+ *
+ * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
+ * and .recalc_rate
+ *
+ * Flags:
+ * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
+ * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two)
+ */
+struct clk_mux {
+	struct clk_hw	hw;
+	void __iomem	*reg;
+	u8		shift;
+	u8		width;
+	u8		flags;
+	spinlock_t	*lock;
+};
+
+#define CLK_MUX_INDEX_ONE		BIT(0)
+#define CLK_MUX_INDEX_BIT		BIT(1)
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+		char **parent_names, u8 num_parents, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_mux_flags, spinlock_t *lock);
 
 /**
  * clk_register - allocate a new clock, register it and return an opaque cookie
-- 
1.7.5.4



From mturquette at linaro.org  Fri Mar 16 02:11:19 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Thu, 15 Mar 2012 23:11:19 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
Message-ID: <1331878280-2758-3-git-send-email-mturquette@linaro.org>

The common clock framework defines a common struct clk useful across
most platforms as well as an implementation of the clk api that drivers
can use safely for managing clocks.

The net result is consolidation of many different struct clk definitions
and platform-specific clock framework implementations.

This patch introduces the common struct clk, struct clk_ops and an
implementation of the well-known clock api in include/clk/clk.h.
Platforms may define their own hardware-specific clock structure and
their own clock operation callbacks, so long as it wraps an instance of
struct clk_hw.

See Documentation/clk.txt for more details.

This patch is based on the work of Jeremy Kerr, which in turn was based
on the work of Ben Herrenschmidt.

Signed-off-by: Mike Turquette <mturquette at linaro.org>
Signed-off-by: Mike Turquette <mturquette at ti.com>
Reviewed-by: Thomas Gleixner <tglx at linutronix.de>
Tested-by: Andrew Lunn <andrew at lunn.ch>
Reviewed-by: Rob Herring <rob.herring <at> calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
---
Changes since v6:
 * clk_set_rate rewritten to set clock rates from top-to-bottom
   * should also reduce pre-rate change notifier noise (thanks Sascha)
 * fixed return types for __clk_get_(enable|prepare)_count
 * some NULL pointer fixes for handling .parent_names and .parents
 * removed unnecessary checks for recursive calls in a few helpers
 * made __clk_round_rate more sane and aligned with clk_round_rate
   * parent rates are returned if .round_rate is not implemented
 * fixed CONFIG_COMMON_CLK_DEBUGFS to select DEBUG_FS

Changes since v5:
 * new CONFIG_COMMON_CLK_DISABLE_UNUSED feature
   * results in a new clk_op callback, .is_enabled
 * new helpers
   * __clk_get_prepare_count
   * __clk_get_enable_count
   * __clk_is_enabled
 * fix bug in __clk_get_rate for orphan clocks

 drivers/clk/Kconfig          |   40 ++
 drivers/clk/Makefile         |    1 +
 drivers/clk/clk.c            | 1461 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-private.h  |   72 ++
 include/linux/clk-provider.h |  173 +++++
 include/linux/clk.h          |   68 ++-
 6 files changed, 1810 insertions(+), 5 deletions(-)
 create mode 100644 drivers/clk/clk.c
 create mode 100644 include/linux/clk-private.h
 create mode 100644 include/linux/clk-provider.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9b3cd08..2eaf17e 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -8,3 +8,43 @@ config HAVE_CLK_PREPARE
 
 config HAVE_MACH_CLKDEV
 	bool
+
+menuconfig COMMON_CLK
+	bool "Common Clock Framework"
+	select HAVE_CLK_PREPARE
+	---help---
+	  The common clock framework is a single definition of struct
+	  clk, useful across many platforms, as well as an
+	  implementation of the clock API in include/linux/clk.h.
+	  Architectures utilizing the common struct clk should select
+	  this automatically, but it may be necessary to manually select
+	  this option for loadable modules requiring the common clock
+	  framework.
+
+	  If in doubt, say "N".
+
+if COMMON_CLK
+
+config COMMON_CLK_DISABLE_UNUSED
+	bool "Disabled unused clocks at boot"
+	depends on COMMON_CLK
+	---help---
+	  Traverses the entire clock tree and disables any clocks that are
+	  enabled in hardware but have not been enabled by any device drivers.
+	  This saves power and keeps the software model of the clock in line
+	  with reality.
+
+	  If in doubt, say "N".
+
+config COMMON_CLK_DEBUG
+	bool "DebugFS representation of clock tree"
+	depends on COMMON_CLK
+	select DEBUG_FS
+	---help---
+	  Creates a directory hierchy in debugfs for visualizing the clk
+	  tree structure.  Each directory contains read-only members
+	  that export information specific to that clk node: clk_rate,
+	  clk_flags, clk_prepare_count, clk_enable_count &
+	  clk_notifier_count.
+
+endif
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 07613fa..ff362c4 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,2 +1,3 @@
 
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
+obj-$(CONFIG_COMMON_CLK)	+= clk.o
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
new file mode 100644
index 0000000..9cf6f59
--- /dev/null
+++ b/drivers/clk/clk.c
@@ -0,0 +1,1461 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr at canonical.com>
+ * Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Standard functionality for the common clock API.  See Documentation/clk.txt
+ */
+
+#include <linux/clk-private.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/slab.h>
+
+static DEFINE_SPINLOCK(enable_lock);
+static DEFINE_MUTEX(prepare_lock);
+
+static HLIST_HEAD(clk_root_list);
+static HLIST_HEAD(clk_orphan_list);
+static LIST_HEAD(clk_notifier_list);
+
+/***        debugfs support        ***/
+
+#ifdef CONFIG_COMMON_CLK_DEBUG
+#include <linux/debugfs.h>
+
+static struct dentry *rootdir;
+static struct dentry *orphandir;
+static int inited = 0;
+
+/* caller must hold prepare_lock */
+static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
+{
+	struct dentry *d;
+	int ret = -ENOMEM;
+
+	if (!clk || !pdentry) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	d = debugfs_create_dir(clk->name, pdentry);
+	if (!d)
+		goto out;
+
+	clk->dentry = d;
+
+	d = debugfs_create_u32("clk_rate", S_IRUGO, clk->dentry,
+			(u32 *)&clk->rate);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
+			(u32 *)&clk->flags);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_u32("clk_prepare_count", S_IRUGO, clk->dentry,
+			(u32 *)&clk->prepare_count);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_u32("clk_enable_count", S_IRUGO, clk->dentry,
+			(u32 *)&clk->enable_count);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_u32("clk_notifier_count", S_IRUGO, clk->dentry,
+			(u32 *)&clk->notifier_count);
+	if (!d)
+		goto err_out;
+
+	ret = 0;
+	goto out;
+
+err_out:
+	debugfs_remove(clk->dentry);
+out:
+	return ret;
+}
+
+/* caller must hold prepare_lock */
+static int clk_debug_create_subtree(struct clk *clk, struct dentry *pdentry)
+{
+	struct clk *child;
+	struct hlist_node *tmp;
+	int ret = -EINVAL;;
+
+	if (!clk || !pdentry)
+		goto out;
+
+	ret = clk_debug_create_one(clk, pdentry);
+
+	if (ret)
+		goto out;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node)
+		clk_debug_create_subtree(child, clk->dentry);
+
+	ret = 0;
+out:
+	return ret;
+}
+
+/**
+ * clk_debug_register - add a clk node to the debugfs clk tree
+ * @clk: the clk being added to the debugfs clk tree
+ *
+ * Dynamically adds a clk to the debugfs clk tree if debugfs has been
+ * initialized.  Otherwise it bails out early since the debugfs clk tree
+ * will be created lazily by clk_debug_init as part of a late_initcall.
+ *
+ * Caller must hold prepare_lock.  Only clk_init calls this function (so
+ * far) so this is taken care.
+ */
+static int clk_debug_register(struct clk *clk)
+{
+	struct clk *parent;
+	struct dentry *pdentry;
+	int ret = 0;
+
+	if (!inited)
+		goto out;
+
+	parent = clk->parent;
+
+	/*
+	 * Check to see if a clk is a root clk.  Also check that it is
+	 * safe to add this clk to debugfs
+	 */
+	if (!parent)
+		if (clk->flags & CLK_IS_ROOT)
+			pdentry = rootdir;
+		else
+			pdentry = orphandir;
+	else
+		if (parent->dentry)
+			pdentry = parent->dentry;
+		else
+			goto out;
+
+	ret = clk_debug_create_subtree(clk, pdentry);
+
+out:
+	return ret;
+}
+
+/**
+ * clk_debug_init - lazily create the debugfs clk tree visualization
+ *
+ * clks are often initialized very early during boot before memory can
+ * be dynamically allocated and well before debugfs is setup.
+ * clk_debug_init walks the clk tree hierarchy while holding
+ * prepare_lock and creates the topology as part of a late_initcall,
+ * thus insuring that clks initialized very early will still be
+ * represented in the debugfs clk tree.  This function should only be
+ * called once at boot-time, and all other clks added dynamically will
+ * be done so with clk_debug_register.
+ */
+static int __init clk_debug_init(void)
+{
+	struct clk *clk;
+	struct hlist_node *tmp;
+
+	rootdir = debugfs_create_dir("clk", NULL);
+
+	if (!rootdir)
+		return -ENOMEM;
+
+	orphandir = debugfs_create_dir("orphans", rootdir);
+
+	if (!orphandir)
+		return -ENOMEM;
+
+	mutex_lock(&prepare_lock);
+
+	hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
+		clk_debug_create_subtree(clk, rootdir);
+
+	hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
+		clk_debug_create_subtree(clk, orphandir);
+
+	inited = 1;
+
+	mutex_unlock(&prepare_lock);
+
+	return 0;
+}
+late_initcall(clk_debug_init);
+#else
+static inline int clk_debug_register(struct clk *clk) { return 0; }
+#endif /* CONFIG_COMMON_CLK_DEBUG */
+
+#ifdef CONFIG_COMMON_CLK_DISABLE_UNUSED
+/* caller must hold prepare_lock */
+static void clk_disable_unused_subtree(struct clk *clk)
+{
+	struct clk *child;
+	struct hlist_node *tmp;
+	unsigned long flags;
+
+	if (!clk)
+		goto out;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node)
+		clk_disable_unused_subtree(child);
+
+	spin_lock_irqsave(&enable_lock, flags);
+
+	if (clk->enable_count)
+		goto unlock_out;
+
+	if (clk->flags & CLK_IGNORE_UNUSED)
+		goto unlock_out;
+
+	if (__clk_is_enabled(clk) && clk->ops->disable)
+		clk->ops->disable(clk->hw);
+
+unlock_out:
+	spin_unlock_irqrestore(&enable_lock, flags);
+
+out:
+	return;
+}
+
+static int clk_disable_unused(void)
+{
+	struct clk *clk;
+	struct hlist_node *tmp;
+
+	mutex_lock(&prepare_lock);
+
+	hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
+		clk_disable_unused_subtree(clk);
+
+	hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
+		clk_disable_unused_subtree(clk);
+
+	mutex_unlock(&prepare_lock);
+
+	return 0;
+}
+late_initcall(clk_disable_unused);
+#else
+static inline int clk_disable_unused(struct clk *clk) { return 0; }
+#endif /* CONFIG_COMMON_CLK_DISABLE_UNUSED */
+
+/***    helper functions   ***/
+
+inline const char *__clk_get_name(struct clk *clk)
+{
+	return !clk ? NULL : clk->name;
+}
+
+inline struct clk_hw *__clk_get_hw(struct clk *clk)
+{
+	return !clk ? NULL : clk->hw;
+}
+
+inline u8 __clk_get_num_parents(struct clk *clk)
+{
+	return !clk ? -EINVAL : clk->num_parents;
+}
+
+inline struct clk *__clk_get_parent(struct clk *clk)
+{
+	return !clk ? NULL : clk->parent;
+}
+
+inline int __clk_get_enable_count(struct clk *clk)
+{
+	return !clk ? -EINVAL : clk->enable_count;
+}
+
+inline int __clk_get_prepare_count(struct clk *clk)
+{
+	return !clk ? -EINVAL : clk->prepare_count;
+}
+
+unsigned long __clk_get_rate(struct clk *clk)
+{
+	unsigned long ret;
+
+	if (!clk) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = clk->rate;
+
+	if (clk->flags & CLK_IS_ROOT)
+		goto out;
+
+	if (!clk->parent)
+		ret = -ENODEV;
+
+out:
+	return ret;
+}
+
+inline unsigned long __clk_get_flags(struct clk *clk)
+{
+	return !clk ? -EINVAL : clk->flags;
+}
+
+int __clk_is_enabled(struct clk *clk)
+{
+	int ret;
+
+	if (!clk)
+		return -EINVAL;
+
+	/*
+	 * .is_enabled is only mandatory for clocks that gate
+	 * fall back to software usage counter if .is_enabled is missing
+	 */
+	if (!clk->ops->is_enabled) {
+		ret = clk->enable_count ? 1 : 0;
+		goto out;
+	}
+
+	ret = clk->ops->is_enabled(clk->hw);
+out:
+	return ret;
+}
+
+static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
+{
+	struct clk *child;
+	struct clk *ret;
+	struct hlist_node *tmp;
+
+	if (!strcmp(clk->name, name))
+		return clk;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		ret = __clk_lookup_subtree(name, child);
+		if (ret)
+			return ret;
+	}
+
+	return NULL;
+}
+
+struct clk *__clk_lookup(const char *name)
+{
+	struct clk *root_clk;
+	struct clk *ret;
+	struct hlist_node *tmp;
+
+	if (!name)
+		return NULL;
+
+	/* search the 'proper' clk tree first */
+	hlist_for_each_entry(root_clk, tmp, &clk_root_list, child_node) {
+		ret = __clk_lookup_subtree(name, root_clk);
+		if (ret)
+			return ret;
+	}
+
+	/* if not found, then search the orphan tree */
+	hlist_for_each_entry(root_clk, tmp, &clk_orphan_list, child_node) {
+		ret = __clk_lookup_subtree(name, root_clk);
+		if (ret)
+			return ret;
+	}
+
+	return NULL;
+}
+
+/***        clk api        ***/
+
+void __clk_unprepare(struct clk *clk)
+{
+	if (!clk)
+		return;
+
+	if (WARN_ON(clk->prepare_count == 0))
+		return;
+
+	if (--clk->prepare_count > 0)
+		return;
+
+	WARN_ON(clk->enable_count > 0);
+
+	if (clk->ops->unprepare)
+		clk->ops->unprepare(clk->hw);
+
+	__clk_unprepare(clk->parent);
+}
+
+/**
+ * clk_unprepare - undo preparation of a clock source
+ * @clk: the clk being unprepare
+ *
+ * clk_unprepare may sleep, which differentiates it from clk_disable.  In a
+ * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
+ * if the operation may sleep.  One example is a clk which is accessed over
+ * I2c.  In the complex case a clk gate operation may require a fast and a slow
+ * part.  It is this reason that clk_unprepare and clk_disable are not mutually
+ * exclusive.  In fact clk_disable must be called before clk_unprepare.
+ */
+void clk_unprepare(struct clk *clk)
+{
+	mutex_lock(&prepare_lock);
+	__clk_unprepare(clk);
+	mutex_unlock(&prepare_lock);
+}
+EXPORT_SYMBOL_GPL(clk_unprepare);
+
+int __clk_prepare(struct clk *clk)
+{
+	int ret = 0;
+
+	if (!clk)
+		return 0;
+
+	if (clk->prepare_count == 0) {
+		ret = __clk_prepare(clk->parent);
+		if (ret)
+			return ret;
+
+		if (clk->ops->prepare) {
+			ret = clk->ops->prepare(clk->hw);
+			if (ret) {
+				__clk_unprepare(clk->parent);
+				return ret;
+			}
+		}
+	}
+
+	clk->prepare_count++;
+
+	return 0;
+}
+
+/**
+ * clk_prepare - prepare a clock source
+ * @clk: the clk being prepared
+ *
+ * clk_prepare may sleep, which differentiates it from clk_enable.  In a simple
+ * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
+ * operation may sleep.  One example is a clk which is accessed over I2c.  In
+ * the complex case a clk ungate operation may require a fast and a slow part.
+ * It is this reason that clk_prepare and clk_enable are not mutually
+ * exclusive.  In fact clk_prepare must be called before clk_enable.
+ * Returns 0 on success, -EERROR otherwise.
+ */
+int clk_prepare(struct clk *clk)
+{
+	int ret;
+
+	mutex_lock(&prepare_lock);
+	ret = __clk_prepare(clk);
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_prepare);
+
+static void __clk_disable(struct clk *clk)
+{
+	if (!clk)
+		return;
+
+	if (WARN_ON(clk->enable_count == 0))
+		return;
+
+	if (--clk->enable_count > 0)
+		return;
+
+	if (clk->ops->disable)
+		clk->ops->disable(clk->hw);
+
+	__clk_disable(clk->parent);
+}
+
+/**
+ * clk_disable - gate a clock
+ * @clk: the clk being gated
+ *
+ * clk_disable must not sleep, which differentiates it from clk_unprepare.  In
+ * a simple case, clk_disable can be used instead of clk_unprepare to gate a
+ * clk if the operation is fast and will never sleep.  One example is a
+ * SoC-internal clk which is controlled via simple register writes.  In the
+ * complex case a clk gate operation may require a fast and a slow part.  It is
+ * this reason that clk_unprepare and clk_disable are not mutually exclusive.
+ * In fact clk_disable must be called before clk_unprepare.
+ */
+void clk_disable(struct clk *clk)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&enable_lock, flags);
+	__clk_disable(clk);
+	spin_unlock_irqrestore(&enable_lock, flags);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+static int __clk_enable(struct clk *clk)
+{
+	int ret = 0;
+
+	if (!clk)
+		return 0;
+
+	if (WARN_ON(clk->prepare_count == 0))
+		return -ESHUTDOWN;
+
+	if (clk->enable_count == 0) {
+		ret = __clk_enable(clk->parent);
+
+		if (ret)
+			return ret;
+
+		if (clk->ops->enable) {
+			ret = clk->ops->enable(clk->hw);
+			if (ret) {
+				__clk_disable(clk->parent);
+				return ret;
+			}
+		}
+	}
+
+	clk->enable_count++;
+	return 0;
+}
+
+/**
+ * clk_enable - ungate a clock
+ * @clk: the clk being ungated
+ *
+ * clk_enable must not sleep, which differentiates it from clk_prepare.  In a
+ * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
+ * if the operation will never sleep.  One example is a SoC-internal clk which
+ * is controlled via simple register writes.  In the complex case a clk ungate
+ * operation may require a fast and a slow part.  It is this reason that
+ * clk_enable and clk_prepare are not mutually exclusive.  In fact clk_prepare
+ * must be called before clk_enable.  Returns 0 on success, -EERROR
+ * otherwise.
+ */
+int clk_enable(struct clk *clk)
+{
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&enable_lock, flags);
+	ret = __clk_enable(clk);
+	spin_unlock_irqrestore(&enable_lock, flags);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+/**
+ * clk_get_rate - return the rate of clk
+ * @clk: the clk whose rate is being returned
+ *
+ * Simply returns the cached rate of the clk.  Does not query the hardware.  If
+ * clk is NULL then returns -EINVAL.
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+	unsigned long rate;
+
+	mutex_lock(&prepare_lock);
+	rate = __clk_get_rate(clk);
+	mutex_unlock(&prepare_lock);
+
+	return rate;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+/**
+ * __clk_round_rate - round the given rate for a clk
+ * @clk: round the rate of this clock
+ *
+ * Caller must hold prepare_lock.  Useful for clk_ops such as .set_rate
+ */
+unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long unused;
+
+	if (!clk)
+		return -EINVAL;
+
+	if (!clk->ops->round_rate)
+		return clk->rate;
+
+	if (clk->flags & CLK_SET_RATE_PARENT)
+		return clk->ops->round_rate(clk->hw, rate, &unused);
+	else
+		return clk->ops->round_rate(clk->hw, rate, NULL);
+}
+
+/**
+ * clk_round_rate - round the given rate for a clk
+ * @clk: the clk for which we are rounding a rate
+ * @rate: the rate which is to be rounded
+ *
+ * Takes in a rate as input and rounds it to a rate that the clk can actually
+ * use which is then returned.  If clk doesn't support round_rate operation
+ * then the parent rate is returned.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long ret;
+
+	mutex_lock(&prepare_lock);
+	ret = __clk_round_rate(clk, rate);
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+/**
+ * __clk_notify - call clk notifier chain
+ * @clk: struct clk * that is changing rate
+ * @msg: clk notifier type (see include/linux/clk.h)
+ * @old_rate: old clk rate
+ * @new_rate: new clk rate
+ *
+ * Triggers a notifier call chain on the clk rate-change notification
+ * for 'clk'.  Passes a pointer to the struct clk and the previous
+ * and current rates to the notifier callback.  Intended to be called by
+ * internal clock code only.  Returns NOTIFY_DONE from the last driver
+ * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
+ * a driver returns that.
+ */
+static int __clk_notify(struct clk *clk, unsigned long msg,
+		unsigned long old_rate, unsigned long new_rate)
+{
+	struct clk_notifier *cn;
+	struct clk_notifier_data cnd;
+	int ret = NOTIFY_DONE;
+
+	cnd.clk = clk;
+	cnd.old_rate = old_rate;
+	cnd.new_rate = new_rate;
+
+	list_for_each_entry(cn, &clk_notifier_list, node) {
+		if (cn->clk == clk) {
+			ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
+					&cnd);
+			break;
+		}
+	}
+
+	return ret;
+}
+
+/**
+ * __clk_recalc_rates
+ * @clk: first clk in the subtree
+ * @msg: notification type (see include/linux/clk.h)
+ *
+ * Walks the subtree of clks starting with clk and recalculates rates as it
+ * goes.  Note that if a clk does not implement the .recalc_rate callback then
+ * it is assumed that the clock will take on the rate of it's parent.
+ *
+ * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
+ * if necessary.
+ *
+ * Caller must hold prepare_lock.
+ */
+static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
+{
+	unsigned long old_rate;
+	unsigned long parent_rate = 0;
+	struct hlist_node *tmp;
+	struct clk *child;
+
+	old_rate = clk->rate;
+
+	if (clk->parent)
+		parent_rate = clk->parent->rate;
+
+	if (clk->ops->recalc_rate)
+		clk->rate = clk->ops->recalc_rate(clk->hw, parent_rate);
+	else
+		clk->rate = parent_rate;
+
+	/*
+	 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
+	 * & ABORT_RATE_CHANGE notifiers
+	 */
+	if (clk->notifier_count && msg)
+		__clk_notify(clk, msg, old_rate, clk->rate);
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node)
+		__clk_recalc_rates(child, msg);
+}
+
+/**
+ * __clk_speculate_rates
+ * @clk: first clk in the subtree
+ * @parent_rate: the "future" rate of clk's parent
+ *
+ * Walks the subtree of clks starting with clk, speculating rates as it
+ * goes and firing off PRE_RATE_CHANGE notifications as necessary.
+ *
+ * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
+ * pre-rate change notifications and returns early if no clks in the
+ * subtree have subscribed to the notifications.  Note that if a clk does not
+ * implement the .recalc_rate callback then it is assumed that the clock will
+ * take on the rate of it's parent.
+ *
+ * Caller must hold prepare_lock.
+ */
+static int __clk_speculate_rates(struct clk *clk, unsigned long parent_rate)
+{
+	struct hlist_node *tmp;
+	struct clk *child;
+	unsigned long new_rate;
+	int ret = NOTIFY_DONE;
+
+	if (clk->ops->recalc_rate)
+		new_rate = clk->ops->recalc_rate(clk->hw, parent_rate);
+	else
+		new_rate = parent_rate;
+
+	/* abort the rate change if a driver returns NOTIFY_BAD */
+	if (clk->notifier_count)
+		ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
+
+	if (ret == NOTIFY_BAD)
+		goto out;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		ret = __clk_speculate_rates(child, new_rate);
+		if (ret == NOTIFY_BAD)
+			break;
+	}
+
+out:
+	return ret;
+}
+
+static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
+{
+	struct clk *child;
+	struct hlist_node *tmp;
+
+	clk->new_rate = new_rate;
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		if (child->ops->recalc_rate)
+			child->new_rate = child->ops->recalc_rate(child->hw, new_rate);
+		else
+			child->new_rate = new_rate;
+		clk_calc_subtree(child, child->new_rate);
+	}
+}
+
+/*
+ * calculate the new rates returning the topmost clock that has to be
+ * changed.
+ */
+static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
+{
+	struct clk *top = clk;
+	unsigned long best_parent_rate = clk->parent->rate;
+	unsigned long new_rate;
+
+	if (!clk->ops->round_rate && !(clk->flags & CLK_SET_RATE_PARENT)) {
+		clk->new_rate = clk->rate;
+		return NULL;
+	}
+
+	if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) {
+		top = clk_calc_new_rates(clk->parent, rate);
+		new_rate = clk->new_rate = clk->parent->new_rate;
+
+		goto out;
+	}
+
+	if (clk->flags & CLK_SET_RATE_PARENT)
+		new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
+	else
+		new_rate = clk->ops->round_rate(clk->hw, rate, NULL);
+
+	if (best_parent_rate != clk->parent->rate) {
+		top = clk_calc_new_rates(clk->parent, best_parent_rate);
+
+		goto out;
+	}
+
+out:
+	clk_calc_subtree(clk, new_rate);
+
+	return top;
+}
+
+/*
+ * Notify about rate changes in a subtree. Always walk down the whole tree
+ * so that in case of an error we can walk down the whole tree again and
+ * abort the change.
+ */
+static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long event)
+{
+	struct hlist_node *tmp;
+	struct clk *child, *fail_clk = NULL;
+	int ret = NOTIFY_DONE;
+
+	if (clk->rate == clk->new_rate)
+		return 0;
+
+	if (clk->notifier_count) {
+		ret = __clk_notify(clk, event, clk->rate, clk->new_rate);
+		if (ret == NOTIFY_BAD)
+			fail_clk = clk;
+	}
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
+		clk = clk_propagate_rate_change(child, event);
+		if (clk)
+			fail_clk = clk;
+	}
+
+	return fail_clk;
+}
+
+/*
+ * walk down a subtree and set the new rates notifying the rate
+ * change on the way
+ */
+static void clk_change_rate(struct clk *clk)
+{
+	struct clk *child;
+	unsigned long old_rate;
+	struct hlist_node *tmp;
+
+	old_rate = clk->rate;
+
+	if (clk->ops->set_rate)
+		clk->ops->set_rate(clk->hw, clk->new_rate);
+
+	if (clk->ops->recalc_rate)
+		clk->rate = clk->ops->recalc_rate(clk->hw,
+				clk->parent->rate);
+	else
+		clk->rate = clk->parent->rate;
+
+	if (clk->notifier_count && old_rate != clk->rate)
+		__clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);
+
+	hlist_for_each_entry(child, tmp, &clk->children, child_node)
+		clk_change_rate(child);
+}
+
+/**
+ * clk_set_rate - specify a new rate for clk
+ * @clk: the clk whose rate is being changed
+ * @rate: the new rate for clk
+ *
+ * In the simplest case clk_set_rate will only change the rate of clk.
+ *
+ * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call
+ * will fail; only when the clk is disabled will it be able to change
+ * its rate.
+ *
+ * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to
+ * recursively propagate up to clk's parent; whether or not this happens
+ * depends on the outcome of clk's .round_rate implementation.  If
+ * *parent_rate is 0 after calling .round_rate then upstream parent
+ * propagation is ignored.  If *parent_rate comes back with a new rate
+ * for clk's parent then we propagate up to clk's parent and set it's
+ * rate.  Upward propagation will continue until either a clk does not
+ * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting
+ * changes to clk's parent_rate.  If there is a failure during upstream
+ * propagation then clk_set_rate will unwind and restore each clk's rate
+ * that had been successfully changed.  Afterwards a rate change abort
+ * notification will be propagated downstream, starting from the clk
+ * that failed.
+ *
+ * At the end of all of the rate setting, clk_set_rate internally calls
+ * __clk_recalc_rates and propagates the rate changes downstream,
+ * starting from the highest clk whose rate was changed.  This has the
+ * added benefit of propagating post-rate change notifiers.
+ *
+ * Note that while post-rate change and rate change abort notifications
+ * are guaranteed to be sent to a clk only once per call to
+ * clk_set_rate, pre-change notifications will be sent for every clk
+ * whose rate is changed.  Stacking pre-change notifications is noisy
+ * for the drivers subscribed to them, but this allows drivers to react
+ * to intermediate clk rate changes up until the point where the final
+ * rate is achieved at the end of upstream propagation.
+ *
+ * Returns 0 on success, -EERROR otherwise.
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk *top, *fail_clk;
+	int ret = 0;
+
+	/* prevent racing with updates to the clock topology */
+	mutex_lock(&prepare_lock);
+
+	/* bail early if nothing to do */
+	if (rate == clk->rate)
+		goto out;
+
+	/* calculate new rates and get the topmost changed clock */
+	top = clk_calc_new_rates(clk, rate);
+	if (!top) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* notify that we are about to change rates */
+	fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
+	if (fail_clk) {
+		pr_warn("%s: failed to set %s rate\n", __func__,
+				fail_clk->name);
+		clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
+		ret = -EBUSY;
+		goto out;
+	}
+
+	/* change the rates */
+	clk_change_rate(top);
+
+	mutex_unlock(&prepare_lock);
+
+	return 0;
+out:
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+/**
+ * clk_get_parent - return the parent of a clk
+ * @clk: the clk whose parent gets returned
+ *
+ * Simply returns clk->parent.  Returns NULL if clk is NULL.
+ */
+struct clk *clk_get_parent(struct clk *clk)
+{
+	struct clk *parent;
+
+	mutex_lock(&prepare_lock);
+	parent = __clk_get_parent(clk);
+	mutex_unlock(&prepare_lock);
+
+	return parent;
+}
+EXPORT_SYMBOL_GPL(clk_get_parent);
+
+/*
+ * .get_parent is mandatory for clocks with multiple possible parents.  It is
+ * optional for single-parent clocks.  Always call .get_parent if it is
+ * available and WARN if it is missing for multi-parent clocks.
+ *
+ * For single-parent clocks without .get_parent, first check to see if the
+ * .parents array exists, and if so use it to avoid an expensive tree
+ * traversal.  If .parents does not exist then walk the tree with __clk_lookup.
+ */
+static struct clk *__clk_init_parent(struct clk *clk)
+{
+	struct clk *ret = NULL;
+	u8 index;
+
+	/* handle the trivial cases */
+
+	if (!clk->num_parents)
+		goto out;
+
+	if (clk->num_parents == 1) {
+		if (IS_ERR_OR_NULL(clk->parent))
+			ret = clk->parent = __clk_lookup(clk->parent_names[0]);
+		ret = clk->parent;
+		goto out;
+	}
+
+	if (!clk->ops->get_parent) {
+		WARN(!clk->ops->get_parent,
+			"%s: multi-parent clocks must implement .get_parent\n",
+			__func__);
+		goto out;
+	};
+
+	/*
+	 * Do our best to cache parent clocks in clk->parents.  This prevents
+	 * unnecessary and expensive calls to __clk_lookup.  We don't set
+	 * clk->parent here; that is done by the calling function
+	 */
+
+	index = clk->ops->get_parent(clk->hw);
+
+	if (!clk->parents)
+		clk->parents =
+			kmalloc((sizeof(struct clk*) * clk->num_parents),
+					GFP_KERNEL);
+
+	if (!clk->parents)
+		ret = __clk_lookup(clk->parent_names[index]);
+	else if (!clk->parents[index])
+		ret = clk->parents[index] =
+			__clk_lookup(clk->parent_names[index]);
+	else
+		ret = clk->parents[index];
+
+out:
+	return ret;
+}
+
+void __clk_reparent(struct clk *clk, struct clk *new_parent)
+{
+#ifdef CONFIG_COMMON_CLK_DEBUG
+	struct dentry *d;
+	struct dentry *new_parent_d;
+#endif
+
+	if (!clk || !new_parent)
+		return;
+
+	hlist_del(&clk->child_node);
+
+	if (new_parent)
+		hlist_add_head(&clk->child_node, &new_parent->children);
+	else
+		hlist_add_head(&clk->child_node, &clk_orphan_list);
+
+#ifdef CONFIG_COMMON_CLK_DEBUG
+	if (!inited)
+		goto out;
+
+	if (new_parent)
+		new_parent_d = new_parent->dentry;
+	else
+		new_parent_d = orphandir;
+
+	d = debugfs_rename(clk->dentry->d_parent, clk->dentry,
+			new_parent_d, clk->name);
+	if (d)
+		clk->dentry = d;
+	else
+		pr_debug("%s: failed to rename debugfs entry for %s\n",
+				__func__, clk->name);
+out:
+#endif
+
+	clk->parent = new_parent;
+
+	__clk_recalc_rates(clk, POST_RATE_CHANGE);
+}
+
+static int __clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct clk *old_parent;
+	unsigned long flags;
+	int ret = -EINVAL;
+	u8 i;
+
+	old_parent = clk->parent;
+
+	/* find index of new parent clock using cached parent ptrs */
+	for (i = 0; i < clk->num_parents; i++)
+		if (clk->parents[i] == parent)
+			break;
+
+	/*
+	 * find index of new parent clock using string name comparison
+	 * also try to cache the parent to avoid future calls to __clk_lookup
+	 */
+	if (i == clk->num_parents)
+		for (i = 0; i < clk->num_parents; i++)
+			if (!strcmp(clk->parent_names[i], parent->name)) {
+				clk->parents[i] = __clk_lookup(parent->name);
+				break;
+			}
+
+	if (i == clk->num_parents) {
+		pr_debug("%s: clock %s is not a possible parent of clock %s\n",
+				__func__, parent->name, clk->name);
+		goto out;
+	}
+
+	/* migrate prepare and enable */
+	if (clk->prepare_count)
+		__clk_prepare(parent);
+
+	/* FIXME replace with clk_is_enabled(clk) someday */
+	spin_lock_irqsave(&enable_lock, flags);
+	if (clk->enable_count)
+		__clk_enable(parent);
+	spin_unlock_irqrestore(&enable_lock, flags);
+
+	/* change clock input source */
+	ret = clk->ops->set_parent(clk->hw, i);
+
+	/* clean up old prepare and enable */
+	spin_lock_irqsave(&enable_lock, flags);
+	if (clk->enable_count)
+		__clk_disable(old_parent);
+	spin_unlock_irqrestore(&enable_lock, flags);
+
+	if (clk->prepare_count)
+		__clk_unprepare(old_parent);
+
+out:
+	return ret;
+}
+
+/**
+ * clk_set_parent - switch the parent of a mux clk
+ * @clk: the mux clk whose input we are switching
+ * @parent: the new input to clk
+ *
+ * Re-parent clk to use parent as it's new input source.  If clk has the
+ * CLK_SET_PARENT_GATE flag set then clk must be gated for this
+ * operation to succeed.  After successfully changing clk's parent
+ * clk_set_parent will update the clk topology, sysfs topology and
+ * propagate rate recalculation via __clk_recalc_rates.  Returns 0 on
+ * success, -EERROR otherwise.
+ */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	int ret = 0;
+
+	if (!clk || !clk->ops)
+		return -EINVAL;
+
+	if (!clk->ops->set_parent)
+		return -ENOSYS;
+
+	/* prevent racing with updates to the clock topology */
+	mutex_lock(&prepare_lock);
+
+	if (clk->parent == parent)
+		goto out;
+
+	/* propagate PRE_RATE_CHANGE notifications */
+	if (clk->notifier_count)
+		ret = __clk_speculate_rates(clk, parent->rate);
+
+	/* abort if a driver objects */
+	if (ret == NOTIFY_STOP)
+		goto out;
+
+	/* only re-parent if the clock is not in use */
+	if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count)
+		ret = -EBUSY;
+	else
+		ret = __clk_set_parent(clk, parent);
+
+	/* propagate ABORT_RATE_CHANGE if .set_parent failed */
+	if (ret) {
+		__clk_recalc_rates(clk, ABORT_RATE_CHANGE);
+		goto out;
+	}
+
+	/* propagate rate recalculation downstream */
+	__clk_reparent(clk, parent);
+
+out:
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+/**
+ * __clk_init - initialize the data structures in a struct clk
+ * @dev:	device initializing this clk, placeholder for now
+ * @clk:	clk being initialized
+ *
+ * Initializes the lists in struct clk, queries the hardware for the
+ * parent and rate and sets them both.
+ *
+ * Any struct clk passed into __clk_init must have the following members
+ * populated:
+ * 	.name
+ * 	.ops
+ * 	.hw
+ * 	.parent_names
+ * 	.num_parents
+ * 	.flags
+ *
+ * Essentially, everything that would normally be passed into clk_register is
+ * assumed to be initialized already in __clk_init.  The other members may be
+ * populated, but are optional.
+ *
+ * __clk_init is only exposed via clk-private.h and is intended for use with
+ * very large numbers of clocks that need to be statically initialized.  It is
+ * a layering violation to include clk-private.h from any code which implements
+ * a clock's .ops; as such any statically initialized clock data MUST be in a
+ * separate C file from the logic that implements it's operations.
+ */
+void __clk_init(struct device *dev, struct clk *clk)
+{
+	int i;
+	struct clk *orphan;
+	struct hlist_node *tmp, *tmp2;
+
+	if (!clk)
+		return;
+
+	mutex_lock(&prepare_lock);
+
+	/* check to see if a clock with this name is already registered */
+	if (__clk_lookup(clk->name))
+		goto out;
+
+	/* throw a WARN if any entries in parent_names are NULL */
+	for (i = 0; i < clk->num_parents; i++)
+		WARN(!clk->parent_names[i],
+				"%s: invalid NULL in %s's .parent_names\n",
+				__func__, clk->name);
+
+	/*
+	 * Allocate an array of struct clk *'s to avoid unnecessary string
+	 * look-ups of clk's possible parents.  This can fail for clocks passed
+	 * in to clk_init during early boot; thus any access to clk->parents[]
+	 * must always check for a NULL pointer and try to populate it if
+	 * necessary.
+	 *
+	 * If clk->parents is not NULL we skip this entire block.  This allows
+	 * for clock drivers to statically initialize clk->parents.
+	 */
+	if (clk->num_parents && !clk->parents) {
+		clk->parents = kmalloc((sizeof(struct clk*) * clk->num_parents),
+				GFP_KERNEL);
+		/*
+		 * __clk_lookup returns NULL for parents that have not been
+		 * clk_init'd; thus any access to clk->parents[] must check
+		 * for a NULL pointer.  We can always perform lazy lookups for
+		 * missing parents later on.
+		 */
+		if (clk->parents)
+			for (i = 0; i < clk->num_parents; i++)
+				clk->parents[i] =
+					__clk_lookup(clk->parent_names[i]);
+	}
+
+	clk->parent = __clk_init_parent(clk);
+
+	/*
+	 * Populate clk->parent if parent has already been __clk_init'd.  If
+	 * parent has not yet been __clk_init'd then place clk in the orphan
+	 * list.  If clk has set the CLK_IS_ROOT flag then place it in the root
+	 * clk list.
+	 *
+	 * Every time a new clk is clk_init'd then we walk the list of orphan
+	 * clocks and re-parent any that are children of the clock currently
+	 * being clk_init'd.
+	 */
+	if (clk->parent)
+		hlist_add_head(&clk->child_node,
+				&clk->parent->children);
+	else if (clk->flags & CLK_IS_ROOT)
+		hlist_add_head(&clk->child_node, &clk_root_list);
+	else
+		hlist_add_head(&clk->child_node, &clk_orphan_list);
+
+	/*
+	 * Set clk's rate.  The preferred method is to use .recalc_rate.  For
+	 * simple clocks and lazy developers the default fallback is to use the
+	 * parent's rate.  If a clock doesn't have a parent (or is orphaned)
+	 * then rate is set to zero.
+	 */
+	if (clk->ops->recalc_rate)
+		clk->rate = clk->ops->recalc_rate(clk->hw,
+				__clk_get_rate(clk->parent));
+	else if (clk->parent)
+		clk->rate = clk->parent->rate;
+	else
+		clk->rate = 0;
+
+	/*
+	 * walk the list of orphan clocks and reparent any that are children of
+	 * this clock
+	 */
+	hlist_for_each_entry_safe(orphan, tmp, tmp2, &clk_orphan_list, child_node)
+		for (i = 0; i < orphan->num_parents; i++)
+			if (!strcmp(clk->name, orphan->parent_names[i])) {
+				__clk_reparent(orphan, clk);
+				break;
+			}
+
+	/*
+	 * optional platform-specific magic
+	 *
+	 * The .init callback is not used by any of the basic clock types, but
+	 * exists for weird hardware that must perform initialization magic.
+	 * Please consider other ways of solving initialization problems before
+	 * using this callback, as it's use is discouraged.
+	 */
+	if (clk->ops->init)
+		clk->ops->init(clk->hw);
+
+	clk_debug_register(clk);
+
+out:
+	mutex_unlock(&prepare_lock);
+
+	return;
+}
+
+/**
+ * clk_register - allocate a new clock, register it and return an opaque cookie
+ * @dev: device that is registering this clock
+ * @name: clock name
+ * @ops: operations this clock supports
+ * @hw: link to hardware-specific clock data
+ * @parent_names: array of string names for all possible parents
+ * @num_parents: number of possible parents
+ * @flags: framework-level hints and quirks
+ *
+ * clk_register is the primary interface for populating the clock tree with new
+ * clock nodes.  It returns a pointer to the newly allocated struct clk which
+ * cannot be dereferenced by driver code but may be used in conjuction with the
+ * rest of the clock API.
+ */
+struct clk *clk_register(struct device *dev, const char *name,
+		const struct clk_ops *ops, struct clk_hw *hw,
+		char **parent_names, u8 num_parents, unsigned long flags)
+{
+	struct clk *clk;
+
+	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+	if (!clk)
+		return NULL;
+
+	clk->name = name;
+	clk->ops = ops;
+	clk->hw = hw;
+	clk->flags = flags;
+	clk->parent_names = parent_names;
+	clk->num_parents = num_parents;
+	hw->clk = clk;
+
+	__clk_init(dev, clk);
+
+	return clk;
+}
+EXPORT_SYMBOL_GPL(clk_register);
+
+/***        clk rate change notifiers        ***/
+
+/**
+ * clk_notifier_register - add a clk rate change notifier
+ * @clk: struct clk * to watch
+ * @nb: struct notifier_block * with callback info
+ *
+ * Request notification when clk's rate changes.  This uses an SRCU
+ * notifier because we want it to block and notifier unregistrations are
+ * uncommon.  The callbacks associated with the notifier must not
+ * re-enter into the clk framework by calling any top-level clk APIs;
+ * this will cause a nested prepare_lock mutex.
+ *
+ * Pre-change notifier callbacks will be passed the current, pre-change
+ * rate of the clk via struct clk_notifier_data.old_rate.  The new,
+ * post-change rate of the clk is passed via struct
+ * clk_notifier_data.new_rate.
+ *
+ * Post-change notifiers will pass the now-current, post-change rate of
+ * the clk in both struct clk_notifier_data.old_rate and struct
+ * clk_notifier_data.new_rate.
+ *
+ * Abort-change notifiers are effectively the opposite of pre-change
+ * notifiers: the original pre-change clk rate is passed in via struct
+ * clk_notifier_data.new_rate and the failed post-change rate is passed
+ * in via struct clk_notifier_data.old_rate.
+ *
+ * clk_notifier_register() must be called from non-atomic context.
+ * Returns -EINVAL if called with null arguments, -ENOMEM upon
+ * allocation failure; otherwise, passes along the return value of
+ * srcu_notifier_chain_register().
+ */
+int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
+{
+	struct clk_notifier *cn;
+	int ret = -ENOMEM;
+
+	if (!clk || !nb)
+		return -EINVAL;
+
+	mutex_lock(&prepare_lock);
+
+	/* search the list of notifiers for this clk */
+	list_for_each_entry(cn, &clk_notifier_list, node)
+		if (cn->clk == clk)
+			break;
+
+	/* if clk wasn't in the notifier list, allocate new clk_notifier */
+	if (cn->clk != clk) {
+		cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
+		if (!cn)
+			goto out;
+
+		cn->clk = clk;
+		srcu_init_notifier_head(&cn->notifier_head);
+
+		list_add(&cn->node, &clk_notifier_list);
+	}
+
+	ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
+
+	clk->notifier_count++;
+
+out:
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_notifier_register);
+
+/**
+ * clk_notifier_unregister - remove a clk rate change notifier
+ * @clk: struct clk *
+ * @nb: struct notifier_block * with callback info
+ *
+ * Request no further notification for changes to 'clk' and frees memory
+ * allocated in clk_notifier_register.
+ *
+ * Returns -EINVAL if called with null arguments; otherwise, passes
+ * along the return value of srcu_notifier_chain_unregister().
+ */
+int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
+{
+	struct clk_notifier *cn = NULL;
+	int ret = -EINVAL;
+
+	if (!clk || !nb)
+		return -EINVAL;
+
+	mutex_lock(&prepare_lock);
+
+	list_for_each_entry(cn, &clk_notifier_list, node)
+		if (cn->clk == clk)
+			break;
+
+	if (cn->clk == clk) {
+		ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
+
+		clk->notifier_count--;
+
+		/* XXX the notifier code should handle this better */
+		if (!cn->notifier_head.head) {
+			srcu_cleanup_notifier_head(&cn->notifier_head);
+			kfree(cn);
+		}
+
+	} else {
+		ret = -ENOENT;
+	}
+
+	mutex_unlock(&prepare_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_notifier_unregister);
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
new file mode 100644
index 0000000..e2cce6f
--- /dev/null
+++ b/include/linux/clk-private.h
@@ -0,0 +1,72 @@
+/*
+ *  linux/include/linux/clk-private.h
+ *
+ *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr at canonical.com>
+ *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_CLK_PRIVATE_H
+#define __LINUX_CLK_PRIVATE_H
+
+#include <linux/clk-provider.h>
+#include <linux/list.h>
+
+/*
+ * WARNING: Do not include clk-private.h from any file that implements struct
+ * clk_ops.  Doing so is a layering violation!
+ *
+ * This header exists only to allow for statically initialized clock data.  Any
+ * static clock data must be defined in a separate file from the logic that
+ * implements the clock operations for that same data.
+ */
+
+#ifdef CONFIG_COMMON_CLK
+
+struct clk {
+	const char		*name;
+	const struct clk_ops	*ops;
+	struct clk_hw		*hw;
+	struct clk		*parent;
+	char			**parent_names;
+	struct clk		**parents;
+	u8			num_parents;
+	unsigned long		rate;
+	unsigned long		new_rate;
+	unsigned long		flags;
+	unsigned int		enable_count;
+	unsigned int		prepare_count;
+	struct hlist_head	children;
+	struct hlist_node	child_node;
+	unsigned int		notifier_count;
+#ifdef CONFIG_COMMON_CLK_DEBUG
+	struct dentry		*dentry;
+#endif
+};
+
+/**
+ * __clk_init - initialize the data structures in a struct clk
+ * @dev:	device initializing this clk, placeholder for now
+ * @clk:	clk being initialized
+ *
+ * Initializes the lists in struct clk, queries the hardware for the
+ * parent and rate and sets them both.
+ *
+ * Any struct clk passed into __clk_init must have the following members
+ * populated:
+ * 	.name
+ * 	.ops
+ * 	.hw
+ * 	.parent_names
+ * 	.num_parents
+ * 	.flags
+ *
+ * It is not necessary to call clk_register if __clk_init is used directly with
+ * statically initialized clock data.
+ */
+void __clk_init(struct device *dev, struct clk *clk);
+
+#endif /* CONFIG_COMMON_CLK */
+#endif /* CLK_PRIVATE_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
new file mode 100644
index 0000000..b18b0e7
--- /dev/null
+++ b/include/linux/clk-provider.h
@@ -0,0 +1,173 @@
+/*
+ *  linux/include/linux/clk-provider.h
+ *
+ *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr at canonical.com>
+ *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_CLK_PROVIDER_H
+#define __LINUX_CLK_PROVIDER_H
+
+#include <linux/clk.h>
+
+#ifdef CONFIG_COMMON_CLK
+
+/**
+ * struct clk_hw - handle for traversing from a struct clk to its corresponding
+ * hardware-specific structure.  struct clk_hw should be declared within struct
+ * clk_foo and then referenced by the struct clk instance that uses struct
+ * clk_foo's clk_ops
+ *
+ * clk: pointer to the struct clk instance that points back to this struct
+ * clk_hw instance
+ */
+struct clk_hw {
+	struct clk *clk;
+};
+
+/*
+ * flags used across common struct clk.  these flags should only affect the
+ * top-level framework.  custom flags for dealing with hardware specifics
+ * belong in struct clk_foo
+ */
+#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
+#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
+#define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
+#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
+#define CLK_IS_ROOT		BIT(4) /* root clk, has no parent */
+
+/**
+ * struct clk_ops -  Callback operations for hardware clocks; these are to
+ * be provided by the clock implementation, and will be called by drivers
+ * through the clk_* api.
+ *
+ * @prepare:	Prepare the clock for enabling. This must not return until
+ * 		the clock is fully prepared, and it's safe to call clk_enable.
+ * 		This callback is intended to allow clock implementations to
+ * 		do any initialisation that may sleep. Called with
+ * 		prepare_lock held.
+ *
+ * @unprepare:	Release the clock from its prepared state. This will typically
+ * 		undo any work done in the @prepare callback. Called with
+ * 		prepare_lock held.
+ *
+ * @enable:	Enable the clock atomically. This must not return until the
+ * 		clock is generating a valid clock signal, usable by consumer
+ * 		devices. Called with enable_lock held. This function must not
+ * 		sleep.
+ *
+ * @disable:	Disable the clock atomically. Called with enable_lock held.
+ * 		This function must not sleep.
+ *
+ * @recalc_rate	Recalculate the rate of this clock, by quering hardware.  The
+ * 		parent rate is an input parameter.  It is up to the caller to
+ * 		insure that the prepare_mutex is held across this call.
+ * 		Returns the calculated rate.  Optional, but recommended - if
+ * 		this op is not set then clock rate will be initialized to 0.
+ *
+ * @round_rate:	Given a target rate as input, returns the closest rate actually
+ * 		supported by the clock.
+ *
+ * @get_parent:	Queries the hardware to determine the parent of a clock.  The
+ * 		return value is a u8 which specifies the index corresponding to
+ * 		the parent clock.  This index can be applied to either the
+ * 		.parent_names or .parents arrays.  In short, this function
+ * 		translates the parent value read from hardware into an array
+ * 		index.  Currently only called when the clock is initialized by
+ * 		__clk_init.  This callback is mandatory for clocks with
+ * 		multiple parents.  It is optional (and unnecessary) for clocks
+ * 		with 0 or 1 parents.
+ *
+ * @set_parent:	Change the input source of this clock; for clocks with multiple
+ * 		possible parents specify a new parent by passing in the index
+ * 		as a u8 corresponding to the parent in either the .parent_names
+ * 		or .parents arrays.  This function in affect translates an
+ * 		array index into the value programmed into the hardware.
+ * 		Returns 0 on success, -EERROR otherwise.
+ *
+ * @set_rate:	Change the rate of this clock. If this callback returns
+ * 		CLK_SET_RATE_PARENT, the rate change will be propagated to the
+ * 		parent clock (which may propagate again if the parent clock
+ * 		also sets this flag). The requested rate of the parent is
+ * 		passed back from the callback in the second 'unsigned long *'
+ * 		argument.  Note that it is up to the hardware clock's set_rate
+ * 		implementation to insure that clocks do not run out of spec
+ * 		when propgating the call to set_rate up to the parent.  One way
+ * 		to do this is to gate the clock (via clk_disable and/or
+ * 		clk_unprepare) before calling clk_set_rate, then ungating it
+ * 		afterward.  If your clock also has the CLK_GATE_SET_RATE flag
+ * 		set then this will insure safety.  Returns 0 on success,
+ * 		-EERROR otherwise.
+ *
+ * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
+ * implementations to split any work between atomic (enable) and sleepable
+ * (prepare) contexts.  If enabling a clock requires code that might sleep,
+ * this must be done in clk_prepare.  Clock enable code that will never be
+ * called in a sleepable context may be implement in clk_enable.
+ *
+ * Typically, drivers will call clk_prepare when a clock may be needed later
+ * (eg. when a device is opened), and clk_enable when the clock is actually
+ * required (eg. from an interrupt). Note that clk_prepare MUST have been
+ * called before clk_enable.
+ */
+struct clk_ops {
+	int		(*prepare)(struct clk_hw *hw);
+	void		(*unprepare)(struct clk_hw *hw);
+	int		(*enable)(struct clk_hw *hw);
+	void		(*disable)(struct clk_hw *hw);
+	int		(*is_enabled)(struct clk_hw *hw);
+	unsigned long	(*recalc_rate)(struct clk_hw *hw,
+					unsigned long parent_rate);
+	long		(*round_rate)(struct clk_hw *hw, unsigned long,
+					unsigned long *);
+	int		(*set_parent)(struct clk_hw *hw, u8 index);
+	u8		(*get_parent)(struct clk_hw *hw);
+	int		(*set_rate)(struct clk_hw *hw, unsigned long);
+	void		(*init)(struct clk_hw *hw);
+};
+
+
+/**
+ * clk_register - allocate a new clock, register it and return an opaque cookie
+ * @dev: device that is registering this clock
+ * @name: clock name
+ * @ops: operations this clock supports
+ * @hw: link to hardware-specific clock data
+ * @parent_names: array of string names for all possible parents
+ * @num_parents: number of possible parents
+ * @flags: framework-level hints and quirks
+ *
+ * clk_register is the primary interface for populating the clock tree with new
+ * clock nodes.  It returns a pointer to the newly allocated struct clk which
+ * cannot be dereferenced by driver code but may be used in conjuction with the
+ * rest of the clock API.
+ */
+struct clk *clk_register(struct device *dev, const char *name,
+		const struct clk_ops *ops, struct clk_hw *hw,
+		char **parent_names, u8 num_parents, unsigned long flags);
+
+/* helper functions */
+const char *__clk_get_name(struct clk *clk);
+struct clk_hw *__clk_get_hw(struct clk *clk);
+u8 __clk_get_num_parents(struct clk *clk);
+struct clk *__clk_get_parent(struct clk *clk);
+inline int __clk_get_enable_count(struct clk *clk);
+inline int __clk_get_prepare_count(struct clk *clk);
+unsigned long __clk_get_rate(struct clk *clk);
+unsigned long __clk_get_flags(struct clk *clk);
+int __clk_is_enabled(struct clk *clk);
+struct clk *__clk_lookup(const char *name);
+
+/*
+ * FIXME clock api without lock protection
+ */
+int __clk_prepare(struct clk *clk);
+void __clk_unprepare(struct clk *clk);
+void __clk_reparent(struct clk *clk, struct clk *new_parent);
+unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
+
+#endif /* CONFIG_COMMON_CLK */
+#endif /* CLK_PROVIDER_H */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index b9d46fa..b025272 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -3,6 +3,7 @@
  *
  *  Copyright (C) 2004 ARM Limited.
  *  Written by Deep Blue Solutions Limited.
+ *  Copyright (C) 2011-2012 Linaro Ltd <mturquette at linaro.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,18 +13,75 @@
 #define __LINUX_CLK_H
 
 #include <linux/kernel.h>
+#include <linux/notifier.h>
 
 struct device;
 
-/*
- * The base API.
+struct clk;
+
+#ifdef CONFIG_COMMON_CLK
+
+/**
+ * DOC: clk notifier callback types
+ *
+ * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
+ *     to indicate that the rate change will proceed.  Drivers must
+ *     immediately terminate any operations that will be affected by the
+ *     rate change.  Callbacks may either return NOTIFY_DONE or
+ *     NOTIFY_STOP.
+ *
+ * ABORT_RATE_CHANGE: called if the rate change failed for some reason
+ *     after PRE_RATE_CHANGE.  In this case, all registered notifiers on
+ *     the clk will be called with ABORT_RATE_CHANGE. Callbacks must
+ *     always return NOTIFY_DONE.
+ *
+ * POST_RATE_CHANGE - called after the clk rate change has successfully
+ *     completed.  Callbacks must always return NOTIFY_DONE.
+ *
  */
+#define PRE_RATE_CHANGE			BIT(0)
+#define POST_RATE_CHANGE		BIT(1)
+#define ABORT_RATE_CHANGE		BIT(2)
 
+/**
+ * struct clk_notifier - associate a clk with a notifier
+ * @clk: struct clk * to associate the notifier with
+ * @notifier_head: a blocking_notifier_head for this clk
+ * @node: linked list pointers
+ *
+ * A list of struct clk_notifier is maintained by the notifier code.
+ * An entry is created whenever code registers the first notifier on a
+ * particular @clk.  Future notifiers on that @clk are added to the
+ * @notifier_head.
+ */
+struct clk_notifier {
+	struct clk			*clk;
+	struct srcu_notifier_head	notifier_head;
+	struct list_head		node;
+};
 
-/*
- * struct clk - an machine class defined object / cookie.
+/**
+ * struct clk_notifier_data - rate data to pass to the notifier callback
+ * @clk: struct clk * being changed
+ * @old_rate: previous rate of this clk
+ * @new_rate: new rate of this clk
+ *
+ * For a pre-notifier, old_rate is the clk's rate before this rate
+ * change, and new_rate is what the rate will be in the future.  For a
+ * post-notifier, old_rate and new_rate are both set to the clk's
+ * current rate (this was done to optimize the implementation).
  */
-struct clk;
+struct clk_notifier_data {
+	struct clk		*clk;
+	unsigned long		old_rate;
+	unsigned long		new_rate;
+};
+
+int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
+
+int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
+
+#endif /* !CONFIG_COMMON_CLK */
 
 /**
  * clk_get - lookup and obtain a reference to a clock producer.
-- 
1.7.5.4



From mturquette at ti.com  Fri Mar 16 02:22:00 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Thu, 15 Mar 2012 23:22:00 -0700
Subject: [PATCH v6 2/3] clk: introduce the common clock framework
In-Reply-To: <20120315094357.GX3852@pengutronix.de>
References: <1331366064-1273-1-git-send-email-mturquette@linaro.org>
 <1331366064-1273-3-git-send-email-mturquette@linaro.org>
 <20120311113414.GM3852@pengutronix.de>
 <CAJOA=zMdkLB-DCPOk=kz5mn6BK6A_swocyCHJHeGE6H7FxBbmQ@mail.gmail.com>
 <20120312115117.GN3852@pengutronix.de>
 <CAJOA=zPx0ARsoO4ueSTMe_z2Gs4xG4P2qn1=-vHFf7_k=+K6hQ@mail.gmail.com>
 <20120313120507.GS3852@pengutronix.de>
 <CAJOA=zMT4vK7WPF7iEH9kN6GHHAv-LChHoadzieqV-Wd3Qj=WQ@mail.gmail.com>
 <20120315094357.GX3852@pengutronix.de>
Message-ID: <CAJOA=zOLaFJ3xoaL2EtX=rkA1XM2gEzyns6meiiGLrbX8HFujQ@mail.gmail.com>

On Thu, Mar 15, 2012 at 2:43 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Wed, Mar 14, 2012 at 05:51:48PM -0700, Turquette, Mike wrote:
>> @@ -84,9 +78,9 @@ static int clk_divider_bestdiv(struct clk_hw *hw,
>> unsigned long rate,
>>
>> ? ? ? for (i = 1; i <= maxdiv; i++) {
>> ? ? ? ? ? ? ? parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? MULT_ROUND_UP(rate, i));
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? (rate * i));
>
> I think MULT_ROUND_UP is the right thing to use here (not sure if this
> is a good name though)
> Consider we want to have an output rate of 33Hz. Now acceptable input
> rates for a divider value of 3 would be 99, 100 and 101Hz, so we have
> to call round_rate for the parent with 101Hz which includes 100 and
> 99Hz.

We're back to the point Rob brought up about .round_rate rounding up
or down.  We really need a least-upper-bounds or greatest-lower-bounds
flag, similar to how CPUfreq selects target frequencies today.  I'm
freezing features for this patchset now, so I'll keep your
MULT_ROUND_UP approach and some day I'll fix .round_rate for good.

> If you have problems with your PLL than most likely because it does
> something different on clk_round_rate than it does in clk_set_rate,
> for example clk_round_rate(10000) returns 10000, but clk_set_rate then
> sets the rate 9999 due to some rounding error. Being consistent between
> round_rate and set_rate is very important for this mechanism to work
> properly. It did cost me some nerves to get it right for the divider
> (and even more nerves to figure out why it is correct the way it works)

What I'd like to do is request the *exact* frequency I want when
passing in a rate to my PLLs .round_rate.  Due to the way that my MN
dividers are calculated, and due to some jitter avoidance code, it is
bad for me to request 600000001 Hz when I really want 600MHz exactly.
Anyways I fixed this up on my end enough to work with MULT_ROUND_UP,
so that can stay for the immediate future.

>
>> ? ? ? ? ? ? ? now = parent_rate / i;
>> - ? ? ? ? ? ? if (now <= rate && now >= best) {
>> + ? ? ? ? ? ? if (now <= rate && now > best) {
>
> This change is an optimization, but should be unrelated to your PLL
> problem, right?

MULT_ROUND_UP yields multiples of 'rate' plus an incrementing value (m
- 1).  Without that incrementing value added to the rate passed into
__clk_round_rate the for loop above will always max out the divider.
To illustrate:

The rate we want is 300MHz.  Without MULT_ROUND_UP the for loop will
start yielding these combinations:

__clk_round_rate(parent, 300MHz), divide-by-1
__clk_round_rate(parent, 600MHz), divide-by-2
__clk_round_rate(parent, 900MHz), divide-by-3
__clk_round_rate(parent, 1200MHz), divide-by-4
...etc...

These all yield the desired 300MHz for our divider so it just keeps
going until you max out the divider and requests some crazy rate for
the parent.  On most hardware that I am aware of it is desirable to
keep the divider as low as possible so the change to the conditional
prevents us from overwriting best every single time while keeping the
divider low.  So yes, it is an optimization, but it is also quite
necessary without MULT_ROUND_UP.

Anyways I've kept MULT_ROUND_UP exactly as-is with the exception that
I've added that small optimization to keep dividers low.  I hope there
are no objections to that.

Regards,
Mike

>
> Sascha
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ? ? ? ? ? ? ? ? ? ? ? ? ? |
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 ? ?|
> Amtsgericht Hildesheim, HRA 2686 ? ? ? ? ? | Fax: ? +49-5121-206917-5555 |


From sfr at canb.auug.org.au  Fri Mar 16 02:45:46 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 16 Mar 2012 17:45:46 +1100
Subject: linux-next: manual merge of the arm-soc tree with the s5p tree
Message-ID: <20120316174546.5121be30a86c2937579bd3f5@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-exynos/common.c between commit 1d7233ac478a ("Merge branch
'next/soc-exynos5250-arch-gpio' into for-next") from the s5p tree and
commit 853a0231e057 ("Merge branch 'samsung/soc' into next/soc2") from
the arm-soc tree.

These merge commits both looks suspect, but I fixed it up as best I could
(see below).
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-exynos/common.c
index 4e1d0b7,e6cc50e..0000000
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@@ -593,6 -586,14 +593,13 @@@ static int __init exynos4_l2x0_cache_in
  	if (soc_is_exynos5250())
  		return 0;
  
 -	int ret;
+ 	ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
+ 	if (!ret) {
+ 		l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
+ 		clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
+ 		return 0;
+ 	}
+ 
  	if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
  		l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
  		/* TAG, Data Latency Control: 2 cycles */
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From sfr at canb.auug.org.au  Fri Mar 16 02:49:41 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 16 Mar 2012 17:49:41 +1100
Subject: linux-next: manual merge of the arm-soc tree with the arm tree
Message-ID: <20120316174941.40421ba160741a0f6aab6611@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
arch/arm/mach-msm/timer.c between commit f8e56c42e4e3 ("msm: timer:
Support sched_clock()") from the arm tree and commit 5ca709c16d0f ("ARM:
local timers: convert MSM to runtime registration interface") from the
arm-soc tree.

I fixed it up (see below) and can carry the fax as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au

diff --cc arch/arm/mach-msm/timer.c
index 61983da,75f4be4..0000000
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@@ -128,11 -127,45 +128,50 @@@ static struct clocksource msm_clocksour
  	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
  };
  
 +static notrace u32 msm_sched_clock_read(void)
 +{
 +	return msm_clocksource.read(&msm_clocksource);
 +}
 +
+ #ifdef CONFIG_LOCAL_TIMERS
+ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
+ {
+ 	/* Use existing clock_event for cpu 0 */
+ 	if (!smp_processor_id())
+ 		return 0;
+ 
+ 	writel_relaxed(0, event_base + TIMER_ENABLE);
+ 	writel_relaxed(0, event_base + TIMER_CLEAR);
+ 	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
+ 	evt->irq = msm_clockevent.irq;
+ 	evt->name = "local_timer";
+ 	evt->features = msm_clockevent.features;
+ 	evt->rating = msm_clockevent.rating;
+ 	evt->set_mode = msm_timer_set_mode;
+ 	evt->set_next_event = msm_timer_set_next_event;
+ 	evt->shift = msm_clockevent.shift;
+ 	evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
+ 	evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
+ 	evt->min_delta_ns = clockevent_delta2ns(4, evt);
+ 
+ 	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
+ 	clockevents_register_device(evt);
+ 	enable_percpu_irq(evt->irq, 0);
+ 	return 0;
+ }
+ 
+ static void msm_local_timer_stop(struct clock_event_device *evt)
+ {
+ 	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
+ 	disable_percpu_irq(evt->irq);
+ }
+ 
+ static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
+ 	.setup	= msm_local_timer_setup,
+ 	.stop	= msm_local_timer_stop,
+ };
+ #endif /* CONFIG_LOCAL_TIMERS */
+ 
  static void __init msm_timer_init(void)
  {
  	struct clock_event_device *ce = &msm_clockevent;
@@@ -195,44 -232,8 +238,10 @@@ err
  	res = clocksource_register_hz(cs, dgt_hz);
  	if (res)
  		pr_err("clocksource_register failed\n");
 +	setup_sched_clock(msm_sched_clock_read,
 +			cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz);
  }
  
- #ifdef CONFIG_LOCAL_TIMERS
- int __cpuinit local_timer_setup(struct clock_event_device *evt)
- {
- 	/* Use existing clock_event for cpu 0 */
- 	if (!smp_processor_id())
- 		return 0;
- 
- 	writel_relaxed(0, event_base + TIMER_ENABLE);
- 	writel_relaxed(0, event_base + TIMER_CLEAR);
- 	writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
- 	evt->irq = msm_clockevent.irq;
- 	evt->name = "local_timer";
- 	evt->features = msm_clockevent.features;
- 	evt->rating = msm_clockevent.rating;
- 	evt->set_mode = msm_timer_set_mode;
- 	evt->set_next_event = msm_timer_set_next_event;
- 	evt->shift = msm_clockevent.shift;
- 	evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
- 	evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
- 	evt->min_delta_ns = clockevent_delta2ns(4, evt);
- 
- 	*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
- 	clockevents_register_device(evt);
- 	enable_percpu_irq(evt->irq, 0);
- 	return 0;
- }
- 
- void local_timer_stop(struct clock_event_device *evt)
- {
- 	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
- 	disable_percpu_irq(evt->irq);
- }
- #endif /* CONFIG_LOCAL_TIMERS */
- 
  struct sys_timer msm_timer = {
  	.init = msm_timer_init
  };
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From shawn.guo at linaro.org  Fri Mar 16 03:19:54 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 15:19:54 +0800
Subject: [PATCH v4 01/10] PWM: add pwm framework support
In-Reply-To: <1331740593-10807-2-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-2-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120316071951.GB7758@S2101-09.ap.freescale.net>

On Wed, Mar 14, 2012 at 04:56:24PM +0100, Thierry Reding wrote:
...
> +PPWM core

s/PPWM/PWM?

> +M:	Sascha Hauer <s.hauer at pengutronix.de>
> +L:	linux-kernel at vger.kernel.org
> +S:	Maintained
> +F:	drivers/pwm/
> +

-- 
Regards,
Shawn


From thierry.reding at avionic-design.de  Fri Mar 16 03:28:14 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 16 Mar 2012 08:28:14 +0100
Subject: [PATCH v4 01/10] PWM: add pwm framework support
In-Reply-To: <20120316071951.GB7758@S2101-09.ap.freescale.net>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-2-git-send-email-thierry.reding@avionic-design.de>
 <20120316071951.GB7758@S2101-09.ap.freescale.net>
Message-ID: <20120316072814.GB8226@avionic-0098.mockup.avionic-design.de>

* Shawn Guo wrote:
> On Wed, Mar 14, 2012 at 04:56:24PM +0100, Thierry Reding wrote:
> ...
> > +PPWM core
> 
> s/PPWM/PWM?

Yes, I noticed that as well just yesterday.

Thanks,
Thierry
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From augulis.darius at gmail.com  Fri Mar 16 03:47:27 2012
From: augulis.darius at gmail.com (Darius Augulis)
Date: Fri, 16 Mar 2012 09:47:27 +0200
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <001d01cd0315$935cc720$ba165560$%han@samsung.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com>
 <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
 <001d01cd0315$935cc720$ba165560$%han@samsung.com>
Message-ID: <CAEYLNCrGCmb5EJjURLY=EGfM=4N54MirNkCCyQRxqKEN3Eka8Q@mail.gmail.com>

On Fri, Mar 16, 2012 at 3:39 AM, Jingoo Han <jg1.han at samsung.com> wrote:

>> > So, your code can be removed.
>>
>> I don't think so. It does not break anything yet. One who make
>> changes, should ensure backwards compatibility, at least talking about
>> functionality and hardware (LCD) support, which was added few months
>> ago. Remember, we talk about kernel parameters line - now it lets
>> bootloader to select correct LCD size. After your changes, board with
>> 7" LCD wont show anything.
>
> [CC'ed Tushar Behera]
>
> Yes, your code is working. However, your code is bug.

it's not a bug, because it's working like it was intended to. it was
reviewed and accepted by maintainers before merging to main line.
you do not have rights to drop it because you don't like it.
You are doing changes - please do it correctly and do not break
existing functionality.
btw, you still not answered my question: why these two s3c_fb_pd_win
structures in mach-mini6410.c is a problem? They are declared on the
stack, but platform data uses only single one. mini6410 rewrites its
s3c-fb platform data with data from one of these two structures
dynamically. Why it's a bug? You want to remove this dynamic selection
which could be leaved there with reworked framework too.

> 'struct s3c_fb_pd_win' is used not for LCD, but for windows of FIMD IP. So, 'struct s3c_fb_pd_win' should not be used to select LCD.
> The mach-aquila.c uses two 'struct s3c_fb_pd_win' like you, however 'struct s3c_fb_pd_win' don't make problem with Thomas's
> patchset. It is because mach-aquila.c use 'struct s3c_fb_pd_win' for only windows of FIMD IP.
> We don't have to responsibility to keep wrong code. If you have kept the rule, Thomas's patch would not make the compatibility
> problem with your code. Why we should keep aberration such as your code? If you want to select two LCDs, please find other way.
>
>
>>
>> Darius A.
>


From shawn.guo at linaro.org  Fri Mar 16 03:49:05 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 15:49:05 +0800
Subject: [PATCH 1/3] ARM i.MX: Move i.MX pwm driver to pwm framework
In-Reply-To: <1331802277-12477-2-git-send-email-s.hauer@pengutronix.de>
References: <1331802277-12477-1-git-send-email-s.hauer@pengutronix.de>
 <1331802277-12477-2-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120316074902.GC7758@S2101-09.ap.freescale.net>

On Thu, Mar 15, 2012 at 10:04:35AM +0100, Sascha Hauer wrote:
> Move the driver to drivers/pwm/ and convert it to use the framework.
> 
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  arch/arm/plat-mxc/Kconfig                        |    6 -
>  arch/arm/plat-mxc/Makefile                       |    1 -
>  drivers/pwm/Kconfig                              |    9 ++
>  drivers/pwm/Makefile                             |    1 +
>  arch/arm/plat-mxc/pwm.c => drivers/pwm/pwm-imx.c |  155 ++++++++-------------
>  5 files changed, 69 insertions(+), 103 deletions(-)
>  rename arch/arm/plat-mxc/pwm.c => drivers/pwm/pwm-imx.c (66%)
> 
> diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
> index dcebb12..ee09395 100644
> --- a/arch/arm/plat-mxc/Kconfig
> +++ b/arch/arm/plat-mxc/Kconfig
> @@ -47,12 +47,6 @@ config MXC_TZIC
>  config MXC_AVIC
>  	bool
>  
> -config MXC_PWM
> -	tristate "Enable PWM driver"
> -	select HAVE_PWM
> -	help
> -	  Enable support for the i.MX PWM controller(s).
> -
>  config MXC_DEBUG_BOARD
>  	bool "Enable MXC debug board(for 3-stack)"
>  	help
> diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
> index 076db84f..d75ab5a 100644
> --- a/arch/arm/plat-mxc/Makefile
> +++ b/arch/arm/plat-mxc/Makefile
> @@ -11,7 +11,6 @@ obj-$(CONFIG_MXC_AVIC) += avic.o
>  obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
>  obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
>  obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
> -obj-$(CONFIG_MXC_PWM)  += pwm.o
>  obj-$(CONFIG_MXC_ULPI) += ulpi.o
>  obj-$(CONFIG_MXC_USE_EPIT) += epit.o
>  obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 0ef4f30..a9a9715 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -18,6 +18,15 @@ config PWM_BFIN
>  	  To compile this driver as a module, choose M here: the module
>  	  will be called pwm-bfin.
>  
> +config PWM_IMX
> +	tristate "i.MX pwm support"
> +	depends on ARCH_MXC
> +	help
> +	  Generic PWM framework driver for i.MX.
> +
> +	  To compile this driver as a module, choose M here: the module
> +	  will be called pwm-imx.
> +
>  config PWM_PXA
>  	tristate "PXA PWM support"
>  	depends on ARCH_PXA
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index e859c51..fc7571e 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -1,4 +1,5 @@
>  obj-$(CONFIG_PWM)		+= core.o
>  obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
> +obj-$(CONFIG_PWM_IMX)		+= imx-pwm.o

s/imx-pwm.o/pwm-imx.o

>  obj-$(CONFIG_PWM_PXA)		+= pwm-pxa.o
>  obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
> diff --git a/arch/arm/plat-mxc/pwm.c b/drivers/pwm/pwm-imx.c
> similarity index 66%
> rename from arch/arm/plat-mxc/pwm.c
> rename to drivers/pwm/pwm-imx.c
> index e032717..cdb02b0 100644
> --- a/arch/arm/plat-mxc/pwm.c
> +++ b/drivers/pwm/pwm-imx.c
> @@ -39,24 +39,24 @@
>  #define MX3_PWMCR_CLKSRC_IPG      (1 << 16)
>  #define MX3_PWMCR_EN              (1 << 0)
>  
> -
> -
> -struct pwm_device {
> +struct imx_pwm_device {
>  	struct list_head	node;
> -	struct platform_device *pdev;
>  
> -	const char	*label;
>  	struct clk	*clk;
>  
>  	int		clk_enabled;
>  	void __iomem	*mmio_base;
>  
> -	unsigned int	use_count;
> -	unsigned int	pwm_id;
> +	struct pwm_chip chip;
>  };
>  
> -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
> +#define to_imx_pwm_device(chip)	container_of(chip, struct imx_pwm_device, chip)
> +
> +static int imx_pwm_config(struct pwm_chip *chip,
> +		struct pwm_device *pwm, int duty_ns, int period_ns)
>  {
> +	struct imx_pwm_device *imxpwm = to_imx_pwm_device(chip);
> +
>  	if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
>  		return -EINVAL;
>  
> @@ -65,7 +65,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
>  		unsigned long period_cycles, duty_cycles, prescale;
>  		u32 cr;
>  
> -		c = clk_get_rate(pwm->clk);
> +		c = clk_get_rate(imxpwm->clk);
>  		c = c * period_ns;
>  		do_div(c, 1000000000);
>  		period_cycles = c;
> @@ -86,8 +86,8 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
>  		else
>  			period_cycles = 0;
>  
> -		writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);
> -		writel(period_cycles, pwm->mmio_base + MX3_PWMPR);
> +		writel(duty_cycles, imxpwm->mmio_base + MX3_PWMSAR);
> +		writel(period_cycles, imxpwm->mmio_base + MX3_PWMPR);
>  
>  		cr = MX3_PWMCR_PRESCALER(prescale) |
>  			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
> @@ -98,7 +98,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
>  		else
>  			cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
>  
> -		writel(cr, pwm->mmio_base + MX3_PWMCR);
> +		writel(cr, imxpwm->mmio_base + MX3_PWMCR);
>  	} else if (cpu_is_mx1() || cpu_is_mx21()) {

Since we are here, can we move one step further to get rid of these
cpu_is_xxx()?  Then, we can remove <mach/hardware.h> inclusion from
the driver.

>  		/* The PWM subsystem allows for exact frequencies. However,
>  		 * I cannot connect a scope on my device to the PWM line and
> @@ -116,110 +116,70 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
>  		 * both the prescaler (/1 .. /128) and then by CLKSEL
>  		 * (/2 .. /16).
>  		 */
> -		u32 max = readl(pwm->mmio_base + MX1_PWMP);
> +		u32 max = readl(imxpwm->mmio_base + MX1_PWMP);
>  		u32 p = max * duty_ns / period_ns;
> -		writel(max - p, pwm->mmio_base + MX1_PWMS);
> +		writel(max - p, imxpwm->mmio_base + MX1_PWMS);
>  	} else {
>  		BUG();
>  	}
>  
>  	return 0;
>  }
> -EXPORT_SYMBOL(pwm_config);
>  
> -int pwm_enable(struct pwm_device *pwm)
> +static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>  {
> +	struct imx_pwm_device *imxpwm = to_imx_pwm_device(chip);
>  	int rc = 0;
>  
> -	if (!pwm->clk_enabled) {
> -		rc = clk_enable(pwm->clk);
> +	if (!imxpwm->clk_enabled) {
> +		rc = clk_enable(imxpwm->clk);
>  		if (!rc)
> -			pwm->clk_enabled = 1;
> +			imxpwm->clk_enabled = 1;
>  	}
>  	return rc;
>  }
> -EXPORT_SYMBOL(pwm_enable);
> -
> -void pwm_disable(struct pwm_device *pwm)
> -{
> -	writel(0, pwm->mmio_base + MX3_PWMCR);
> -
> -	if (pwm->clk_enabled) {
> -		clk_disable(pwm->clk);
> -		pwm->clk_enabled = 0;
> -	}
> -}
> -EXPORT_SYMBOL(pwm_disable);
> -
> -static DEFINE_MUTEX(pwm_lock);
> -static LIST_HEAD(pwm_list);
>  
> -struct pwm_device *pwm_request(int pwm_id, const char *label)
> +static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
>  {
> -	struct pwm_device *pwm;
> -	int found = 0;
> +	struct imx_pwm_device *imxpwm = to_imx_pwm_device(chip);
>  
> -	mutex_lock(&pwm_lock);
> +	writel(0, imxpwm->mmio_base + MX3_PWMCR);
>  
> -	list_for_each_entry(pwm, &pwm_list, node) {
> -		if (pwm->pwm_id == pwm_id) {
> -			found = 1;
> -			break;
> -		}
> +	if (imxpwm->clk_enabled) {
> +		clk_disable(imxpwm->clk);
> +		imxpwm->clk_enabled = 0;
>  	}
> -
> -	if (found) {
> -		if (pwm->use_count == 0) {
> -			pwm->use_count++;
> -			pwm->label = label;
> -		} else
> -			pwm = ERR_PTR(-EBUSY);
> -	} else
> -		pwm = ERR_PTR(-ENOENT);
> -
> -	mutex_unlock(&pwm_lock);
> -	return pwm;
>  }
> -EXPORT_SYMBOL(pwm_request);
> -
> -void pwm_free(struct pwm_device *pwm)
> -{
> -	mutex_lock(&pwm_lock);
> -
> -	if (pwm->use_count) {
> -		pwm->use_count--;
> -		pwm->label = NULL;
> -	} else
> -		pr_warning("PWM device already freed\n");
>  
> -	mutex_unlock(&pwm_lock);
> -}
> -EXPORT_SYMBOL(pwm_free);
> +static struct pwm_ops imx_pwm_ops = {
> +	.enable = imx_pwm_enable,
> +	.disable = imx_pwm_disable,
> +	.config = imx_pwm_config,
> +	.owner = THIS_MODULE,
> +};
>  
>  static int __devinit mxc_pwm_probe(struct platform_device *pdev)

Should we take this opportunity to rename the driver from mxc_pwm to
imx_pwm?

Also, does mxc_pwm_init need necessarily to be an arch_initcall?
Otherwise, we can have the following change.

-static int __init mxc_pwm_init(void)
-{
-       return platform_driver_register(&mxc_pwm_driver);
-}
-arch_initcall(mxc_pwm_init);
-
-static void __exit mxc_pwm_exit(void)
-{
-       platform_driver_unregister(&mxc_pwm_driver);
-}
-module_exit(mxc_pwm_exit);
+module_platform_driver(imx_pwm_driver);

Regards,
Shawn

>  {
> -	struct pwm_device *pwm;
> +	struct imx_pwm_device *imxpwm;
>  	struct resource *r;
>  	int ret = 0;
>  
> -	pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
> -	if (pwm == NULL) {
> +	imxpwm = kzalloc(sizeof(*imxpwm), GFP_KERNEL);
> +	if (imxpwm == NULL) {
>  		dev_err(&pdev->dev, "failed to allocate memory\n");
>  		return -ENOMEM;
>  	}
>  
> -	pwm->clk = clk_get(&pdev->dev, "pwm");
> +	imxpwm->clk = clk_get(&pdev->dev, "pwm");
>  
> -	if (IS_ERR(pwm->clk)) {
> -		ret = PTR_ERR(pwm->clk);
> +	if (IS_ERR(imxpwm->clk)) {
> +		ret = PTR_ERR(imxpwm->clk);
>  		goto err_free;
>  	}
>  
> -	pwm->clk_enabled = 0;
> +	imxpwm->chip.ops = &imx_pwm_ops;
>  
> -	pwm->use_count = 0;
> -	pwm->pwm_id = pdev->id;
> -	pwm->pdev = pdev;
> +	imxpwm->clk_enabled = 0;
>  
>  	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	if (r == NULL) {
> @@ -235,50 +195,53 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev)
>  		goto err_free_clk;
>  	}
>  
> -	pwm->mmio_base = ioremap(r->start, resource_size(r));
> -	if (pwm->mmio_base == NULL) {
> +	imxpwm->mmio_base = ioremap(r->start, resource_size(r));
> +	if (imxpwm->mmio_base == NULL) {
>  		dev_err(&pdev->dev, "failed to ioremap() registers\n");
>  		ret = -ENODEV;
>  		goto err_free_mem;
>  	}
>  
> -	mutex_lock(&pwm_lock);
> -	list_add_tail(&pwm->node, &pwm_list);
> -	mutex_unlock(&pwm_lock);
> +	ret = pwmchip_add(&imxpwm->chip);
> +	if (ret)
> +		goto err_iounmap;
>  
> -	platform_set_drvdata(pdev, pwm);
> +	platform_set_drvdata(pdev, imxpwm);
>  	return 0;
>  
> +err_iounmap:
> +	iounmap(imxpwm->mmio_base);
>  err_free_mem:
>  	release_mem_region(r->start, resource_size(r));
>  err_free_clk:
> -	clk_put(pwm->clk);
> +	clk_put(imxpwm->clk);
>  err_free:
> -	kfree(pwm);
> +	kfree(imxpwm);
>  	return ret;
>  }
>  
>  static int __devexit mxc_pwm_remove(struct platform_device *pdev)
>  {
> -	struct pwm_device *pwm;
> +	struct imx_pwm_device *imxpwm;
>  	struct resource *r;
> +	int ret;
>  
> -	pwm = platform_get_drvdata(pdev);
> -	if (pwm == NULL)
> +	imxpwm = platform_get_drvdata(pdev);
> +	if (imxpwm == NULL)
>  		return -ENODEV;
>  
> -	mutex_lock(&pwm_lock);
> -	list_del(&pwm->node);
> -	mutex_unlock(&pwm_lock);
> +	ret = pwmchip_remove(&imxpwm->chip);
> +	if (ret)
> +		return ret;
>  
> -	iounmap(pwm->mmio_base);
> +	iounmap(imxpwm->mmio_base);
>  
>  	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	release_mem_region(r->start, resource_size(r));
>  
> -	clk_put(pwm->clk);
> +	clk_put(imxpwm->clk);
>  
> -	kfree(pwm);
> +	kfree(imxpwm);
>  	return 0;
>  }
>  
> -- 
> 1.7.9.1
> 


From LW at KARO-electronics.de  Fri Mar 16 03:48:13 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Fri, 16 Mar 2012 08:48:13 +0100
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120316030134.GA5161@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
 <20120316030134.GA5161@shlinux2.ap.freescale.net>
Message-ID: <20322.61501.432329.124466@ipc1.ka-ro>

Hi,

Dong Aisheng writes:
> On Thu, Mar 15, 2012 at 07:22:04PM +0800, Lothar Wa?mann wrote:
[...]
> My proposal is only set the fixed part(first two octets) in board dts file,
> each board knows it's value, and read the left 4 octets from OCOTP dynamically.
>
The OUI part is three bytes, not two! But anyway, since there is no
definition on how the MAC has to be stored in OCOTP there is no way
for the driver to know how to interpret the data it may read from
there.

> > Anyway there is no definite spec how the MAC address(es) are stored
> > in the fuse map. Thus reading the MAC from there is more or less
> > platform specific.
> > 
> It's just provide one more option since there are customers storing the MAC
> in the fuse map.
> 
How would the driver know, whether and how the customer has stored the
MAC address in OCOTP? E.g. on our TX28 modules the FULL MAC is stored
in the CUSTOM registers in OCOTP.

> > Currently I'm setting up the MAC address for our TX28 from the fuses
> > in the platform code passed via platform_data, but that will obviously
> > not work with DT.
> > 
> Non-dt can also use my proposal, then you only need to pass the fixed part of
> MAC via platfrom data, the left will be read by fec driver.
> 
Reading the MAC from fuses is platform sepcific. The driver cannot
know how the MAC is stored there and needs to rely on platform
specific code to do this.

> > The correct way would probably be to pass the MAC from the bootloader
> > via a DT blob. But that would require all bootloaders to be updated
> > first to support DTS. :(
> > 
> But uboot will face the same problem that can not define a valid MAC
> in dts, did i undertand correctly?
> 
That's why I said "would require all bootloaders to be updated first
to support DTS".


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From mgherzan at gmail.com  Fri Mar 16 03:53:40 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Fri, 16 Mar 2012 08:53:40 +0100
Subject: [PATCH v7] ARM: net: JIT compiler for packet filters
In-Reply-To: <20120315114151.GC15988@n2100.arm.linux.org.uk>
References: <1325937154-2656-1-git-send-email-mgherzan@gmail.com>
 <20120315114151.GC15988@n2100.arm.linux.org.uk>
Message-ID: <4F62F184.5010603@gmail.com>

Am 15.03.2012 12:41, schrieb Russell King - ARM Linux:
> I'm unconvinced that this is safe.
> 
> On Sat, Jan 07, 2012 at 12:52:34PM +0100, Mircea Gherzan wrote:
>> +static int build_body(struct jit_ctx *ctx)
>> +{
>> +	void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
>> +	const struct sk_filter *prog = ctx->skf;
>> +	const struct sock_filter *inst;
>> +	unsigned i, load_order, off, condt;
>> +	int imm12;
>> +	u32 k;
>> +
>> +	for (i = 0; i < prog->len; i++) {
>> +		inst = &(prog->insns[i]);
>> +		/* K as an immediate value operand */
>> +		k = inst->k;
>> +
>> +		/* compute offsets only in the fake pass */
>> +		if (ctx->target == NULL)
>> +			ctx->offsets[i] = ctx->idx * 4;
>> +
>> +		switch (inst->code) {
>> +		case BPF_S_LD_IMM:
>> +			emit_mov_i(r_A, k, ctx);
>> +			break;
>> +		case BPF_S_LD_W_LEN:
>> +			ctx->seen |= SEEN_SKB;
>> +			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
>> +			emit(ARM_LDR_I(r_A, r_skb,
>> +				       offsetof(struct sk_buff, len)), ctx);
>> +			break;
>> +		case BPF_S_LD_MEM:
>> +			/* A = scratch[k] */
>> +			ctx->seen |= SEEN_MEM_WORD(k);
>> +			emit(ARM_LDR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
>> +			break;
>> +		case BPF_S_LD_W_ABS:
>> +			load_order = 2;
>> +			goto load;
>> +		case BPF_S_LD_H_ABS:
>> +			load_order = 1;
>> +			goto load;
>> +		case BPF_S_LD_B_ABS:
>> +			load_order = 0;
>> +load:
>> +			/* the interpreter will deal with the negative K */
>> +			if (k < 0)
>> +				return -1;
> 
> k is a u32, so won't this will always be false - negative numbers will
> appear as huge positive numbers instead.

Good catch, thanks.

>> +			emit_mov_i(r_off, k, ctx);
>> +load_common:
>> +			ctx->seen |= SEEN_DATA | SEEN_CALL;
>> +
>> +			if (load_order > 0) {
>> +				emit(ARM_SUB_I(r_scratch, r_skb_hl,
>> +					       1 << load_order), ctx);
>> +				emit(ARM_CMP_R(r_scratch, r_off), ctx);
>> +				condt = ARM_COND_HS;
>> +			} else {
>> +				emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
>> +				condt = ARM_COND_HI;
>> +			}
>> +
>> +			_emit(condt, ARM_ADD_R(r_scratch, r_off, r_skb_data),
>> +			      ctx);
>> +
>> +			if (load_order == 0)
>> +				_emit(condt, ARM_LDRB_I(r_A, r_scratch, 0),
>> +				      ctx);
>> +			else if (load_order == 1)
>> +				emit_load_be16(condt, r_A, r_scratch, ctx);
>> +			else if (load_order == 2)
>> +				emit_load_be32(condt, r_A, r_scratch, ctx);
> 
> I think this is creating code to do something like this:
> 
> 	sub r_scratch, r_skb_hl, #1 << load_order
> 	cmp r_scratch, k
> 	ldrhs dest, [r_skb_data, k]
> 
> Isn't this going to perform the loads for any k greater than the header
> length?  What stops k being larger than the packet?  And is this correct
> in the first place?

If K is an offset within the header (scratch "higher or same") then use
a direct load, otherwise land on the slowpath of skb_copy_bits(). If K
is larger than the packet then the skb_copy_bits() will return an error.

I don't see anything wrong with this.

>> +
>> +			_emit(condt, ARM_B(b_imm(i + 1, ctx)), ctx);
>> +
>> +			/* the slowpath */
>> +			emit_mov_i(ARM_R3, (u32)load_func[load_order], ctx);
>> +			emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
>> +			/* the offset is already in R1 */
>> +			emit_blx_r(ARM_R3, ctx);
>> +			/* check the result of skb_copy_bits */
>> +			emit(ARM_CMP_I(ARM_R1, 0), ctx);
>> +			emit_err_ret(ARM_COND_NE, ctx);
>> +			emit(ARM_MOV_R(r_A, ARM_R0), ctx);
>> +			break;
>> +		case BPF_S_LD_W_IND:
>> +			load_order = 2;
>> +			goto load_ind;
>> +		case BPF_S_LD_H_IND:
>> +			load_order = 1;
>> +			goto load_ind;
>> +		case BPF_S_LD_B_IND:
>> +			load_order = 0;
>> +load_ind:
>> +			OP_IMM3(ARM_ADD, r_off, r_X, k, ctx);
>> +			goto load_common;
>> +		case BPF_S_LDX_IMM:
>> +			ctx->seen |= SEEN_X;
>> +			emit_mov_i(r_X, k, ctx);
>> +			break;
>> +		case BPF_S_LDX_W_LEN:
>> +			ctx->seen |= SEEN_X | SEEN_SKB;
>> +			emit(ARM_LDR_I(r_X, r_skb,
>> +				       offsetof(struct sk_buff, len)), ctx);
>> +			break;
>> +		case BPF_S_LDX_MEM:
>> +			ctx->seen |= SEEN_X | SEEN_MEM_WORD(k);
>> +			emit(ARM_LDR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
> 
> What about this - SCRATCH_OFF() is just a simple:
> 	+#define SCRATCH_OFF(k)         (SCRATCH_SP_OFFSET + (k))
> 
> So what if 'k' is a carefully chosen 32-bit number outside of the range
> of the stack?  Shouldn't there be a check for k < BPF_MEMWORDS to fail
> the translation where-ever SEEN_MEM_WORD(k) or SCRATCH_OFF(k) is used?

The "scratch memory" accesses are checked in the the sk_chk_filter(), so
there's no need to do anything here.

>> +			break;
>> +		case BPF_S_LDX_B_MSH:
>> +			/* x = ((*(frame + k)) & 0xf) << 2; */
> 
> So, k is passed in from userspace.  What stops k being out of the bounds
> of 'frame' and referring to other kernel space data via carefully crafted
> bpf code?

If k is out of bounds then we land once again on the skb_copy_bits()
slowpath.

> 
>> +			ctx->seen |= SEEN_X | SEEN_DATA | SEEN_CALL;
>> +			/* the interpreter should deal with the negative K */
>> +			if (k < 0)
>> +				return -1;
>> +			/* offset in r1: we might have to take the slow path */
>> +			emit_mov_i(r_off, k, ctx);
>> +			emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
>> +
>> +			/* load in r0: common with the slowpath */
>> +			_emit(ARM_COND_HI, ARM_LDRB_R(ARM_R0, r_skb_data,
>> +						      ARM_R1), ctx);
>> +			/*
>> +			 * emit_mov_i() might generate one or two instructions,
>> +			 * the same holds for emit_blx_r()
>> +			 */
>> +			_emit(ARM_COND_HI, ARM_B(b_imm(i + 1, ctx) - 2), ctx);
>> +
>> +			emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
>> +			/* r_off is r1 */
>> +			emit_mov_i(ARM_R3, (u32)jit_get_skb_b, ctx);
>> +			emit_blx_r(ARM_R3, ctx);
>> +
>> +			emit(ARM_AND_I(r_X, ARM_R0, 0x00f), ctx);
>> +			emit(ARM_LSL_I(r_X, r_X, 2), ctx);
>> +			break;
>> +		case BPF_S_ST:
>> +			ctx->seen |= SEEN_MEM_WORD(k);
>> +			emit(ARM_STR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
>> +			break;
>> +		case BPF_S_STX:
>> +			update_on_xread(ctx);
>> +			ctx->seen |= SEEN_MEM_WORD(k);
>> +			emit(ARM_STR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
>> +			break;
>> +		case BPF_S_ALU_ADD_K:
>> +			/* A += K */
>> +			OP_IMM3(ARM_ADD, r_A, r_A, k, ctx);
>> +			break;
>> +		case BPF_S_ALU_ADD_X:
>> +			update_on_xread(ctx);
>> +			emit(ARM_ADD_R(r_A, r_A, r_X), ctx);
>> +			break;
>> +		case BPF_S_ALU_SUB_K:
>> +			/* A -= K */
>> +			OP_IMM3(ARM_SUB, r_A, r_A, k, ctx);
>> +			break;
>> +		case BPF_S_ALU_SUB_X:
>> +			update_on_xread(ctx);
>> +			emit(ARM_SUB_R(r_A, r_A, r_X), ctx);
>> +			break;
>> +		case BPF_S_ALU_MUL_K:
>> +			/* A *= K */
>> +			emit_mov_i(r_scratch, k, ctx);
>> +			emit(ARM_MUL(r_A, r_A, r_scratch), ctx);
>> +			break;
>> +		case BPF_S_ALU_MUL_X:
>> +			update_on_xread(ctx);
>> +			emit(ARM_MUL(r_A, r_A, r_X), ctx);
>> +			break;
>> +		case BPF_S_ALU_DIV_K:
>> +			/* current k == reciprocal_value(userspace k) */
>> +			emit_mov_i(r_scratch, k, ctx);
>> +			/* A = top 32 bits of the product */
>> +			emit(ARM_UMULL(r_scratch, r_A, r_A, r_scratch), ctx);
>> +			break;
>> +		case BPF_S_ALU_DIV_X:
>> +			update_on_xread(ctx);
>> +			emit(ARM_CMP_I(r_X, 0), ctx);
>> +			emit_err_ret(ARM_COND_EQ, ctx);
>> +			emit_udiv(r_A, r_A, r_X, ctx);
>> +			break;
>> +		case BPF_S_ALU_OR_K:
>> +			/* A |= K */
>> +			OP_IMM3(ARM_ORR, r_A, r_A, k, ctx);
>> +			break;
>> +		case BPF_S_ALU_OR_X:
>> +			update_on_xread(ctx);
>> +			emit(ARM_ORR_R(r_A, r_A, r_X), ctx);
>> +			break;
>> +		case BPF_S_ALU_AND_K:
>> +			/* A &= K */
>> +			OP_IMM3(ARM_AND, r_A, r_A, k, ctx);
>> +			break;
>> +		case BPF_S_ALU_AND_X:
>> +			update_on_xread(ctx);
>> +			emit(ARM_AND_R(r_A, r_A, r_X), ctx);
>> +			break;
>> +		case BPF_S_ALU_LSH_K:
>> +			if (unlikely(k > 31))
>> +				return -1;
>> +			emit(ARM_LSL_I(r_A, r_A, k), ctx);
>> +			break;
>> +		case BPF_S_ALU_LSH_X:
>> +			update_on_xread(ctx);
>> +			emit(ARM_LSL_R(r_A, r_A, r_X), ctx);
>> +			break;
>> +		case BPF_S_ALU_RSH_K:
>> +			if (unlikely(k > 31))
>> +				return -1;
>> +			emit(ARM_LSR_I(r_A, r_A, k), ctx);
>> +			break;
>> +		case BPF_S_ALU_RSH_X:
>> +			update_on_xread(ctx);
>> +			emit(ARM_LSR_R(r_A, r_A, r_X), ctx);
>> +			break;
>> +		case BPF_S_ALU_NEG:
>> +			/* A = -A */
>> +			emit(ARM_RSB_I(r_A, r_A, 0), ctx);
>> +			break;
>> +		case BPF_S_JMP_JA:
>> +			/* pc += K */
>> +			emit(ARM_B(b_imm(i + k + 1, ctx)), ctx);
> 
> This seems to allow the offset[] array to be indexed by an out of bounds
> 32-bit offset (k).  What stops that, therefore what prevents reading a
> target jump address from a random location in kernel space?

The offset of the jump target is checked in sk_chk_filter(), so no need
to worry about anything here.

> I think b_imm() should check that it's not going to overflow its array
> of offsets.

Thanks,
Mircea


From shawn.guo at linaro.org  Fri Mar 16 04:00:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:00:27 +0800
Subject: [PATCH v4 06/10] pwm: Add NVIDIA Tegra SoC support
In-Reply-To: <1331740593-10807-7-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-7-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120316080025.GD7758@S2101-09.ap.freescale.net>

On Wed, Mar 14, 2012 at 04:56:29PM +0100, Thierry Reding wrote:
> This commit adds a generic PWM framework driver for the PWFM controller
> found on NVIDIA Tegra SoCs. The driver is based on code from the
> Chromium kernel tree and was originally written by Gary King (NVIDIA)
> and later modified by Simon Que (Chromium).
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> ---
> Changes in v4:
>   - merge patch from ChromiumOS kernel to fix a rounding issue
>   - move DT code to patch 7
> 
> Changes in v3:
>   - use pwm_device.hwpwm instead of recomputing it
>   - update pwm_ops for changes in patch 2
> 
> Changes in v2:
>   - set pwm_chip.dev field
>   - rename clk_enb to enable
>   - introduce NUM_PWM macro instead of hard-coding the number of PWM
>     devices
>   - update comment in tegra_pwm_config
>   - fix coding-style for multi-line comments
>   - use module_platform_driver
>   - change license to GPL
> 
>  drivers/pwm/Kconfig     |   10 ++
>  drivers/pwm/Makefile    |    1 +
>  drivers/pwm/pwm-tegra.c |  256 +++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 267 insertions(+)
>  create mode 100644 drivers/pwm/pwm-tegra.c
> 
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 93c1052..bda6f23 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -9,4 +9,14 @@ menuconfig PWM
>  
>  if PWM
>  
> +config PWM_TEGRA
> +	tristate "NVIDIA Tegra PWM support"
> +	depends on ARCH_TEGRA
> +	help
> +	  Generic PWM framework driver for the PWFM controller found on NVIDIA
> +	  Tegra SoCs.
> +
> +	  To compile this driver as a module, choose M here: the module
> +	  will be called pwm-tegra.
> +
>  endif
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index 3469c3d..12300f5 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -1 +1,2 @@
>  obj-$(CONFIG_PWM)		+= core.o
> +obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> new file mode 100644
> index 0000000..19540fc
> --- /dev/null
> +++ b/drivers/pwm/pwm-tegra.c
> @@ -0,0 +1,256 @@
> +/*
> + * drivers/pwm/pwm-tegra.c
> + *
> + * Tegra pulse-width-modulation controller driver
> + *
> + * Copyright (c) 2010, NVIDIA Corporation.
> + * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer at pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pwm.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#define PWM_ENABLE	(1 << 31)
> +#define PWM_DUTY_WIDTH	8
> +#define PWM_DUTY_SHIFT	16
> +#define PWM_SCALE_WIDTH	13
> +#define PWM_SCALE_SHIFT	0
> +
> +#define NUM_PWM 4
> +
> +struct tegra_pwm_chip {
> +	struct pwm_chip		chip;
> +	struct device		*dev;
> +
> +	struct clk		*clk;
> +
> +	int			enable[NUM_PWM];
> +	void __iomem		*mmio_base;
> +};
> +
> +static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
> +{
> +	return container_of(chip, struct tegra_pwm_chip, chip);
> +}
> +
> +static inline int pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
> +		unsigned long val)
> +{
> +	unsigned long offset = num << 4;
> +	int rc;
> +
> +	rc = clk_enable(chip->clk);
> +	if (WARN_ON(rc))
> +		return rc;
> +
> +	writel(val, chip->mmio_base + offset);
> +	clk_disable(chip->clk);
> +
> +	return 0;
> +}
> +
> +static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> +		int duty_ns, int period_ns)
> +{
> +	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
> +	unsigned long long c;
> +	unsigned long rate, hz;
> +	u32 val = 0;
> +

Every pwm driver I have been looking at has some validation on
parameters here, something like:

	if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
		return -EINVAL;

It's not needed for tegra, or the check on those platforms is
unnecessary?

> +	/*
> +	 * Convert from duty_ns / period_ns to a fixed number of duty ticks
> +	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
> +	 * nearest integer during division.
> +	 */
> +	c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
> +	do_div(c, period_ns);
> +
> +	val = (u32)c << PWM_DUTY_SHIFT;
> +
> +	/*
> +	 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
> +	 * cycles at the PWM clock rate will take period_ns nanoseconds.
> +	 */
> +	rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
> +	hz = 1000000000ul / period_ns;
> +
> +	rate = (rate + (hz / 2)) / hz;
> +
> +	/*
> +	 * Since the actual PWM divider is the register's frequency divider
> +	 * field minus 1, we need to decrement to get the correct value to
> +	 * write to the register.
> +	 */
> +	if (rate > 0)
> +		rate--;
> +
> +	/*
> +	 * Make sure that the rate will fit in the register's frequency
> +	 * divider field.
> +	 */
> +	if (rate >> PWM_SCALE_WIDTH)
> +		return -EINVAL;
> +
> +	val |= (rate << PWM_SCALE_SHIFT);
> +
> +	/* If the PWM channel is enabled, keep it enabled */
> +	if (pc->enable[pwm->hwpwm])
> +		val |= PWM_ENABLE;
> +
> +	return pwm_writel(pc, pwm->hwpwm, val);
> +}
> +
> +static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
> +{
> +	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
> +	int rc = 0;
> +
> +	if (!pc->enable[pwm->hwpwm]) {
> +		rc = clk_enable(pc->clk);
> +		if (!rc) {
> +			unsigned long offset = pwm->hwpwm << 4;
> +			u32 val;
> +
> +			val = readl(pc->mmio_base + offset);
> +			val |= PWM_ENABLE;
> +			writel(val, pc->mmio_base + offset);
> +
> +			pc->enable[pwm->hwpwm] = 1;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
> +{
> +	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
> +
> +	if (pc->enable[pwm->hwpwm]) {
> +		unsigned long offset = pwm->hwpwm << 4;
> +		u32 val;
> +
> +		val = readl(pc->mmio_base + offset);
> +		val &= ~PWM_ENABLE;
> +		writel(val, pc->mmio_base + offset);
> +
> +		clk_disable(pc->clk);
> +		pc->enable[pwm->hwpwm] = 0;
> +	}
> +}
> +
> +static struct pwm_ops tegra_pwm_ops = {
> +	.config = tegra_pwm_config,
> +	.enable = tegra_pwm_enable,
> +	.disable = tegra_pwm_disable,
> +	.owner = THIS_MODULE,
> +};
> +
> +static int tegra_pwm_probe(struct platform_device *pdev)
> +{
> +	struct tegra_pwm_chip *pwm;
> +	struct resource *r;
> +	int ret;
> +
> +	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
> +	if (!pwm) {
> +		dev_err(&pdev->dev, "failed to allocate memory\n");
> +		return -ENOMEM;
> +	}
> +
> +	pwm->dev = &pdev->dev;
> +
> +	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!r) {
> +		dev_err(&pdev->dev, "no memory resources defined\n");
> +		return -ENODEV;
> +	}
> +
> +	r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
> +			pdev->name);
> +	if (!r) {
> +		dev_err(&pdev->dev, "failed to request memory\n");
> +		return -EBUSY;
> +	}
> +
> +	pwm->mmio_base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
> +	if (!pwm->mmio_base) {
> +		dev_err(&pdev->dev, "failed to ioremap() region\n");
> +		return -ENODEV;
> +	}
> +

The helper devm_request_and_ioremap() can help here?

> +	platform_set_drvdata(pdev, pwm);
> +
> +	pwm->clk = clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(pwm->clk))
> +		return PTR_ERR(pwm->clk);
> +
> +	pwm->chip.dev = &pdev->dev;
> +	pwm->chip.ops = &tegra_pwm_ops;
> +	pwm->chip.base = -1;
> +	pwm->chip.npwm = NUM_PWM;
> +
> +	ret = pwmchip_add(&pwm->chip);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
> +		clk_put(pwm->clk);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int __devexit tegra_pwm_remove(struct platform_device *pdev)
> +{
> +	struct tegra_pwm_chip *pwm = platform_get_drvdata(pdev);
> +	int i;
> +
> +	if (WARN_ON(!pwm))
> +		return -ENODEV;
> +
> +	pwmchip_remove(&pwm->chip);
> +
> +	for (i = 0; i < NUM_PWM; i++) {
> +		pwm_writel(pwm, i, 0);
> +
> +		if (pwm->enable[i])
> +			clk_disable(pwm->clk);
> +	}
> +
> +	clk_put(pwm->clk);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver tegra_pwm_driver = {
> +	.driver = {
> +		.name = "tegra-pwm",
> +	},
> +	.probe = tegra_pwm_probe,
> +	.remove = __devexit_p(tegra_pwm_remove),
> +};
> +
I would remove this blank line.

> +module_platform_driver(tegra_pwm_driver);

Regards,
Shawn

> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("NVIDIA Corporation");
> -- 
> 1.7.9.4
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss


From jg1.han at samsung.com  Fri Mar 16 04:07:03 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Fri, 16 Mar 2012 17:07:03 +0900
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <CAEYLNCrGCmb5EJjURLY=EGfM=4N54MirNkCCyQRxqKEN3Eka8Q@mail.gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com> <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
 <001d01cd0315$935cc720$ba165560$%han@samsung.com>
 <CAEYLNCrGCmb5EJjURLY=EGfM=4N54MirNkCCyQRxqKEN3Eka8Q@mail.gmail.com>
Message-ID: <002d01cd034b$c56f2b00$504d8100$%han@samsung.com>



> -----Original Message-----
> From: Darius Augulis [mailto:augulis.darius at gmail.com]
> Sent: Friday, March 16, 2012 4:47 PM
> To: Jingoo Han
> Cc: Thomas Abraham; linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-
> kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; ben-linux at fluff.org; patches at linaro.org;
> kgene.kim at samsung.com; Kyungmin Park; JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter
> Korsgaard; Maurus Cuelenaere; Tushar Behera
> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> 
> On Fri, Mar 16, 2012 at 3:39 AM, Jingoo Han <jg1.han at samsung.com> wrote:
> 
> >> > So, your code can be removed.
> >>
> >> I don't think so. It does not break anything yet. One who make
> >> changes, should ensure backwards compatibility, at least talking about
> >> functionality and hardware (LCD) support, which was added few months
> >> ago. Remember, we talk about kernel parameters line - now it lets
> >> bootloader to select correct LCD size. After your changes, board with
> >> 7" LCD wont show anything.
> >
> > [CC'ed Tushar Behera]
> >
> > Yes, your code is working. However, your code is bug.
> 
> it's not a bug, because it's working like it was intended to. it was
> reviewed and accepted by maintainers before merging to main line.
> you do not have rights to drop it because you don't like it.
> You are doing changes - please do it correctly and do not break
> existing functionality.
> btw, you still not answered my question: why these two s3c_fb_pd_win
> structures in mach-mini6410.c is a problem? They are declared on the
> stack, but platform data uses only single one. mini6410 rewrites its
> s3c-fb platform data with data from one of these two structures
> dynamically. Why it's a bug? You want to remove this dynamic selection
> which could be leaved there with reworked framework too.


It's just bug.

struct s3c_fb_pd_win should be used for windows of FIMD IP.
It should not be used for selecting multi-LCDs.

struct s3c_fb_pd_win should include information of windows of FIMD IP, s3c_fb_pd_win[0], s3c_fb_pd_win[1] represents window 0,
window 1 of FIMD IP. However, your code includes information of LCD, it means that struct s3c_fb_pd_win represents 4.3" LCD, 7.0"
LCD. It is wrong usage.


> 
> > 'struct s3c_fb_pd_win' is used not for LCD, but for windows of FIMD IP. So, 'struct s3c_fb_pd_win'
> should not be used to select LCD.
> > The mach-aquila.c uses two 'struct s3c_fb_pd_win' like you, however 'struct s3c_fb_pd_win' don't make
> problem with Thomas's
> > patchset. It is because mach-aquila.c use 'struct s3c_fb_pd_win' for only windows of FIMD IP.
> > We don't have to responsibility to keep wrong code. If you have kept the rule, Thomas's patch would
> not make the compatibility
> > problem with your code. Why we should keep aberration such as your code? If you want to select two
> LCDs, please find other way.
> >
> >
> >>
> >> Darius A.
> >



From thierry.reding at avionic-design.de  Fri Mar 16 04:08:32 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 16 Mar 2012 09:08:32 +0100
Subject: [PATCH 1/3] ARM i.MX: Move i.MX pwm driver to pwm framework
In-Reply-To: <20120316074902.GC7758@S2101-09.ap.freescale.net>
References: <1331802277-12477-1-git-send-email-s.hauer@pengutronix.de>
 <1331802277-12477-2-git-send-email-s.hauer@pengutronix.de>
 <20120316074902.GC7758@S2101-09.ap.freescale.net>
Message-ID: <20120316080832.GA6458@avionic-0098.mockup.avionic-design.de>

* Shawn Guo wrote:
> On Thu, Mar 15, 2012 at 10:04:35AM +0100, Sascha Hauer wrote:
> > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> > index e859c51..fc7571e 100644
> > --- a/drivers/pwm/Makefile
> > +++ b/drivers/pwm/Makefile
> > @@ -1,4 +1,5 @@
> >  obj-$(CONFIG_PWM)		+= core.o
> >  obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
> > +obj-$(CONFIG_PWM_IMX)		+= imx-pwm.o
> 
> s/imx-pwm.o/pwm-imx.o

Yes, I'll make that change when I integrate the patch in my series.

> > @@ -98,7 +98,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
> >  		else
> >  			cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
> >  
> > -		writel(cr, pwm->mmio_base + MX3_PWMCR);
> > +		writel(cr, imxpwm->mmio_base + MX3_PWMCR);
> >  	} else if (cpu_is_mx1() || cpu_is_mx21()) {
> 
> Since we are here, can we move one step further to get rid of these
> cpu_is_xxx()?  Then, we can remove <mach/hardware.h> inclusion from
> the driver.

I guess this could be handled by using several names for the driver and
handling the differences using a table of platform_device_id:s. Perhaps
you had something different in mind?

> >  static int __devinit mxc_pwm_probe(struct platform_device *pdev)
> 
> Should we take this opportunity to rename the driver from mxc_pwm to
> imx_pwm?

If we decide to rename maybe it should be done in two steps. First it can be
renamed internally and in the second step the name could be changed along
with all users. I just want to avoid too much churn in this series, which is
already growing way larger than I had hoped.

> Also, does mxc_pwm_init need necessarily to be an arch_initcall?
> Otherwise, we can have the following change.
> 
> -static int __init mxc_pwm_init(void)
> -{
> -       return platform_driver_register(&mxc_pwm_driver);
> -}
> -arch_initcall(mxc_pwm_init);
> -
> -static void __exit mxc_pwm_exit(void)
> -{
> -       platform_driver_unregister(&mxc_pwm_driver);
> -}
> -module_exit(mxc_pwm_exit);
> +module_platform_driver(imx_pwm_driver);

I assume that some platforms may require it to be initialized early because
other drivers may depend on the PWMs being present. However this can probably
be solved in a much better way by using deferred driver probing, which should
be available in 3.4.

Thierry
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From shawn.guo at linaro.org  Fri Mar 16 04:12:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:12:26 +0800
Subject: [PATCH v4 09/10] pwm: Add PXA support
In-Reply-To: <1331740593-10807-10-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-10-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120316081222.GE7758@S2101-09.ap.freescale.net>

On Wed, Mar 14, 2012 at 04:56:32PM +0100, Thierry Reding wrote:
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> ---
> Changes in v3:
>   - update PWM ops for changes in patch 2
> 
>  arch/arm/plat-pxa/Makefile |    1 -
>  arch/arm/plat-pxa/pwm.c    |  304 --------------------------------------------
>  drivers/pwm/Kconfig        |    9 ++
>  drivers/pwm/Makefile       |    1 +
>  drivers/pwm/pwm-pxa.c      |  244 +++++++++++++++++++++++++++++++++++
>  5 files changed, 254 insertions(+), 305 deletions(-)
>  delete mode 100644 arch/arm/plat-pxa/pwm.c
>  create mode 100644 drivers/pwm/pwm-pxa.c
> 
The patch should be generated with "git format-patch -M", so that we
can see the diff like below. 

--- a/arch/arm/plat-pxa/pwm.c
+++ b/drivers/pwm/pwm-pxa.c

-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+                         int duty_ns, int period_ns)
 {
+       struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
        unsigned long long c;
        unsigned long period_cycles, prescale, pv, dc;
+       unsigned long offset;

-       if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
+       if (period_ns == 0 || duty_ns > period_ns)
                return -EINVAL;

Then I will have a question why "pwm == NULL" check is removed?

Regards,
Shawn


From linus.walleij at stericsson.com  Fri Mar 16 04:14:00 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 16 Mar 2012 09:14:00 +0100
Subject: [PATCH 1/2] watchdog: Add support for WDIOC_GETTIMELEFT IOCTL in
 watchdog core
Message-ID: <1331885640-21661-1-git-send-email-linus.walleij@stericsson.com>

From: Viresh Kumar <viresh.kumar at st.com>

This patch adds support for WDIOC_GETTIMELEFT IOCTL in watchdog core. So, there
is another function pointer added to struct watchdog_ops, which can be passed by
drivers to support this IOCTL.

Related documentation is updated too.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 .../watchdog/convert_drivers_to_kernel_api.txt     |    4 ++++
 Documentation/watchdog/watchdog-kernel-api.txt     |    2 ++
 drivers/watchdog/watchdog_dev.c                    |    5 +++++
 include/linux/watchdog.h                           |    2 ++
 4 files changed, 13 insertions(+)

diff --git a/Documentation/watchdog/convert_drivers_to_kernel_api.txt b/Documentation/watchdog/convert_drivers_to_kernel_api.txt
index be8119b..271b885 100644
--- a/Documentation/watchdog/convert_drivers_to_kernel_api.txt
+++ b/Documentation/watchdog/convert_drivers_to_kernel_api.txt
@@ -59,6 +59,10 @@ Here is a overview of the functions and probably needed actions:
 	WDIOC_GETTIMEOUT:
 		No preparations needed
 
+	WDIOC_GETTIMELEFT:
+		It needs get_timeleft() callback to be defined. Otherwise it
+		will return EOPNOTSUPP
+
   Other IOCTLs can be served using the ioctl-callback. Note that this is mainly
   intended for porting old drivers; new drivers should not invent private IOCTLs.
   Private IOCTLs are processed first. When the callback returns with
diff --git a/Documentation/watchdog/watchdog-kernel-api.txt b/Documentation/watchdog/watchdog-kernel-api.txt
index 4b93c28..e4c4d1c 100644
--- a/Documentation/watchdog/watchdog-kernel-api.txt
+++ b/Documentation/watchdog/watchdog-kernel-api.txt
@@ -77,6 +77,7 @@ struct watchdog_ops {
 	int (*ping)(struct watchdog_device *);
 	unsigned int (*status)(struct watchdog_device *);
 	int (*set_timeout)(struct watchdog_device *, unsigned int);
+	unsigned int (*get_timeleft)(struct watchdog_device *);
 	long (*ioctl)(struct watchdog_device *, unsigned int, unsigned long);
 };
 
@@ -122,6 +123,7 @@ they are supported. These optional routines/operations are:
   to re-program the watchdog timer device.
   (Note: the WDIOF_SETTIMEOUT needs to be set in the options field of the
   watchdog's info structure).
+* get_timeleft: this routines returns the time left for reset.
 * ioctl: if this routine is present then it will be called first before we do
   our own internal ioctl call handling. This routine should return -ENOIOCTLCMD
   if a command is not supported. The parameters that are passed to the ioctl
diff --git a/drivers/watchdog/watchdog_dev.c b/drivers/watchdog/watchdog_dev.c
index 1199da0..fa64fb8 100644
--- a/drivers/watchdog/watchdog_dev.c
+++ b/drivers/watchdog/watchdog_dev.c
@@ -237,6 +237,11 @@ static long watchdog_ioctl(struct file *file, unsigned int cmd,
 		if (wdd->timeout == 0)
 			return -EOPNOTSUPP;
 		return put_user(wdd->timeout, p);
+	case WDIOC_GETTIMELEFT:
+		if (!wdd->ops->get_timeleft)
+			return -EOPNOTSUPP;
+
+		return put_user(wdd->ops->get_timeleft(wdd), p);
 	default:
 		return -ENOTTY;
 	}
diff --git a/include/linux/watchdog.h b/include/linux/watchdog.h
index 43ba5b3..58bc9a1 100644
--- a/include/linux/watchdog.h
+++ b/include/linux/watchdog.h
@@ -66,6 +66,7 @@ struct watchdog_device;
  * @ping:	The routine that sends a keepalive ping to the watchdog device.
  * @status:	The routine that shows the status of the watchdog device.
  * @set_timeout:The routine for setting the watchdog devices timeout value.
+ * @get_timeleft:The routine for getting the watchdog device's timeleft value.
  * @ioctl:	The routines that handles extra ioctl calls.
  *
  * The watchdog_ops structure contains a list of low-level operations
@@ -82,6 +83,7 @@ struct watchdog_ops {
 	int (*ping)(struct watchdog_device *);
 	unsigned int (*status)(struct watchdog_device *);
 	int (*set_timeout)(struct watchdog_device *, unsigned int);
+	unsigned int (*get_timeleft)(struct watchdog_device *);
 	long (*ioctl)(struct watchdog_device *, unsigned int, unsigned long);
 };
 
-- 
1.7.9.2



From linus.walleij at stericsson.com  Fri Mar 16 04:14:12 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 16 Mar 2012 09:14:12 +0100
Subject: [PATCH 2/2 v2] watchdog/coh901327: convert to use watchdog core
Message-ID: <1331885652-21750-1-git-send-email-linus.walleij@stericsson.com>

From: Linus Walleij <linus.walleij at linaro.org>

This converts the COH901327 watchdog to use the watchdog core.
I followed Wolframs document, looked at some other drivers and
tested it on the U300.

Cc: Wolfram Sang <w.sang at pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Rebased on top of Viresh's GETTIMELEFT patch and consequently
  dropped the ioctl() call.
---
 drivers/watchdog/Kconfig         |    1 +
 drivers/watchdog/coh901327_wdt.c |  192 +++++++++++---------------------------
 2 files changed, 56 insertions(+), 137 deletions(-)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index df9e8f0..2a4c640 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -283,6 +283,7 @@ config COH901327_WATCHDOG
 	bool "ST-Ericsson COH 901 327 watchdog"
 	depends on ARCH_U300
 	default y if MACH_U300
+	select WATCHDOG_CORE
 	help
 	  Say Y here to include Watchdog timer support for the
 	  watchdog embedded into the ST-Ericsson U300 series platforms.
diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c
index 5b89f7d..7f0cbeb 100644
--- a/drivers/watchdog/coh901327_wdt.c
+++ b/drivers/watchdog/coh901327_wdt.c
@@ -8,17 +8,15 @@
  */
 #include <linux/module.h>
 #include <linux/types.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
 #include <linux/watchdog.h>
 #include <linux/interrupt.h>
 #include <linux/pm.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
-#include <linux/uaccess.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/err.h>
 
 #define DRV_NAME "WDOG COH 901 327"
 
@@ -74,8 +72,6 @@ static resource_size_t phybase;
 static resource_size_t physize;
 static int irq;
 static void __iomem *virtbase;
-static unsigned long coh901327_users;
-static unsigned long boot_status;
 static struct device *parent;
 
 /*
@@ -155,30 +151,31 @@ static void coh901327_disable(void)
 			__func__, val);
 }
 
-static void coh901327_start(void)
+static int coh901327_start(struct watchdog_device *wdt_dev)
 {
 	coh901327_enable(margin * 100);
+	return 0;
+}
+
+static int coh901327_stop(struct watchdog_device *wdt_dev)
+{
+	coh901327_disable();
+	return 0;
 }
 
-static void coh901327_keepalive(void)
+static int coh901327_ping(struct watchdog_device *wdd)
 {
 	clk_enable(clk);
 	/* Feed the watchdog */
 	writew(U300_WDOG_FR_FEED_RESTART_TIMER,
 	       virtbase + U300_WDOG_FR);
 	clk_disable(clk);
+	return 0;
 }
 
-static int coh901327_settimeout(int time)
+static int coh901327_settimeout(struct watchdog_device *wdt_dev,
+				unsigned int time)
 {
-	/*
-	 * Max margin is 327 since the 10ms
-	 * timeout register is max
-	 * 0x7FFF = 327670ms ~= 327s.
-	 */
-	if (time <= 0 || time > 327)
-		return -EINVAL;
-
 	margin = time;
 	clk_enable(clk);
 	/* Set new timeout value */
@@ -190,6 +187,23 @@ static int coh901327_settimeout(int time)
 	return 0;
 }
 
+static unsigned int coh901327_gettimeleft(struct watchdog_device *wdt_dev)
+{
+	u16 val;
+
+	clk_enable(clk);
+	/* Read repeatedly until the value is stable! */
+	val = readw(virtbase + U300_WDOG_CR);
+	while (val & U300_WDOG_CR_VALID_IND)
+		val = readw(virtbase + U300_WDOG_CR);
+	val &= U300_WDOG_CR_COUNT_VALUE_MASK;
+	clk_disable(clk);
+	if (val != 0)
+		val /= 100;
+
+	return val;
+}
+
 /*
  * This interrupt occurs 10 ms before the watchdog WILL bark.
  */
@@ -218,130 +232,35 @@ static irqreturn_t coh901327_interrupt(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
-/*
- * Allow only one user (daemon) to open the watchdog
- */
-static int coh901327_open(struct inode *inode, struct file *file)
-{
-	if (test_and_set_bit(1, &coh901327_users))
-		return -EBUSY;
-	coh901327_start();
-	return nonseekable_open(inode, file);
-}
-
-static int coh901327_release(struct inode *inode, struct file *file)
-{
-	clear_bit(1, &coh901327_users);
-	coh901327_disable();
-	return 0;
-}
-
-static ssize_t coh901327_write(struct file *file, const char __user *data,
-			       size_t len, loff_t *ppos)
-{
-	if (len)
-		coh901327_keepalive();
-	return len;
-}
-
-static long coh901327_ioctl(struct file *file, unsigned int cmd,
-			    unsigned long arg)
-{
-	int ret = -ENOTTY;
-	u16 val;
-	int time;
-	int new_options;
-	union {
-		struct watchdog_info __user *ident;
-		int __user *i;
-	} uarg;
-	static const struct watchdog_info ident = {
-		.options		= WDIOF_CARDRESET |
-					  WDIOF_SETTIMEOUT |
-					  WDIOF_KEEPALIVEPING,
-		.identity		= "COH 901 327 Watchdog",
-		.firmware_version	= 1,
-	};
-	uarg.i = (int __user *)arg;
-
-	switch (cmd) {
-	case WDIOC_GETSUPPORT:
-		ret = copy_to_user(uarg.ident, &ident,
-				   sizeof(ident)) ? -EFAULT : 0;
-		break;
-
-	case WDIOC_GETSTATUS:
-		ret = put_user(0, uarg.i);
-		break;
-
-	case WDIOC_GETBOOTSTATUS:
-		ret = put_user(boot_status, uarg.i);
-		break;
-
-	case WDIOC_SETOPTIONS:
-		ret = get_user(new_options, uarg.i);
-		if (ret)
-			break;
-		if (new_options & WDIOS_DISABLECARD)
-			coh901327_disable();
-		if (new_options & WDIOS_ENABLECARD)
-			coh901327_start();
-		ret = 0;
-		break;
-
-	case WDIOC_KEEPALIVE:
-		coh901327_keepalive();
-		ret = 0;
-		break;
-
-	case WDIOC_SETTIMEOUT:
-		ret = get_user(time, uarg.i);
-		if (ret)
-			break;
-
-		ret = coh901327_settimeout(time);
-		if (ret)
-			break;
-		/* Then fall through to return set value */
-
-	case WDIOC_GETTIMEOUT:
-		ret = put_user(margin, uarg.i);
-		break;
-
-	case WDIOC_GETTIMELEFT:
-		clk_enable(clk);
-		/* Read repeatedly until the value is stable! */
-		val = readw(virtbase + U300_WDOG_CR);
-		while (val & U300_WDOG_CR_VALID_IND)
-			val = readw(virtbase + U300_WDOG_CR);
-		val &= U300_WDOG_CR_COUNT_VALUE_MASK;
-		clk_disable(clk);
-		if (val != 0)
-			val /= 100;
-		ret = put_user(val, uarg.i);
-		break;
-	}
-	return ret;
-}
+static const struct watchdog_info coh901327_ident = {
+	.options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
+	.identity = DRV_NAME,
+};
 
-static const struct file_operations coh901327_fops = {
-	.owner		= THIS_MODULE,
-	.llseek		= no_llseek,
-	.write		= coh901327_write,
-	.unlocked_ioctl	= coh901327_ioctl,
-	.open		= coh901327_open,
-	.release	= coh901327_release,
+static struct watchdog_ops coh901327_ops = {
+	.owner = THIS_MODULE,
+	.start = coh901327_start,
+	.stop = coh901327_stop,
+	.ping = coh901327_ping,
+	.set_timeout = coh901327_settimeout,
+	.get_timeleft = coh901327_gettimeleft,
 };
 
-static struct miscdevice coh901327_miscdev = {
-	.minor		= WATCHDOG_MINOR,
-	.name		= "watchdog",
-	.fops		= &coh901327_fops,
+static struct watchdog_device coh901327_wdt = {
+	.info = &coh901327_ident,
+	.ops = &coh901327_ops,
+	/*
+	 * Max margin is 327 since the 10ms
+	 * timeout register is max
+	 * 0x7FFF = 327670ms ~= 327s.
+	 */
+	.min_timeout = 0,
+	.max_timeout = 327,
 };
 
 static int __exit coh901327_remove(struct platform_device *pdev)
 {
-	misc_deregister(&coh901327_miscdev);
+	watchdog_unregister_device(&coh901327_wdt);
 	coh901327_disable();
 	free_irq(irq, pdev);
 	clk_put(clk);
@@ -350,7 +269,6 @@ static int __exit coh901327_remove(struct platform_device *pdev)
 	return 0;
 }
 
-
 static int __init coh901327_probe(struct platform_device *pdev)
 {
 	int ret;
@@ -393,7 +311,7 @@ static int __init coh901327_probe(struct platform_device *pdev)
 	case U300_WDOG_SR_STATUS_TIMED_OUT:
 		dev_info(&pdev->dev,
 			"watchdog timed out since last chip reset!\n");
-		boot_status = WDIOF_CARDRESET;
+		coh901327_wdt.bootstatus |= WDIOF_CARDRESET;
 		/* Status will be cleared below */
 		break;
 	case U300_WDOG_SR_STATUS_NORMAL:
@@ -435,7 +353,7 @@ static int __init coh901327_probe(struct platform_device *pdev)
 
 	clk_disable(clk);
 
-	ret = misc_register(&coh901327_miscdev);
+	ret = watchdog_register_device(&coh901327_wdt);
 	if (ret == 0)
 		dev_info(&pdev->dev,
 			 "initialized. timer margin=%d sec\n", margin);
@@ -547,4 +465,4 @@ module_param(margin, int, 0);
 MODULE_PARM_DESC(margin, "Watchdog margin in seconds (default 60s)");
 
 MODULE_LICENSE("GPL");
-MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
+MODULE_ALIAS("platform:coh901327-watchdog");
-- 
1.7.9.2



From linus.walleij at linaro.org  Fri Mar 16 04:15:35 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 16 Mar 2012 09:15:35 +0100
Subject: [PATCH] watchdog/coh901327: convert to use watchdog core
In-Reply-To: <20120315212705.GH10698@spo001.leaseweb.com>
References: <1331131929-22383-1-git-send-email-linus.walleij@stericsson.com>
 <20120307164240.GA1130@pengutronix.de>
 <CACRpkdaE5HASdF27db7EfnSoaUF8mA5bWoKUhaAzSegdBKsKFQ@mail.gmail.com>
 <20120315212705.GH10698@spo001.leaseweb.com>
Message-ID: <CACRpkdZ9tD8XQ3tOwTHMa3jOhivkwW7YZO0WZgG7r5BYDNktCQ@mail.gmail.com>

On Thu, Mar 15, 2012 at 10:27 PM, Wim Van Sebroeck <wim at iguana.be> wrote:
> Hi Linus,
>
>> On Wed, Mar 7, 2012 at 5:42 PM, Wolfram Sang <w.sang at pengutronix.de> wrote:
>>
>> >> ? ? ? case WDIOC_GETTIMELEFT:
>> >> ? ? ? ? ? ? ? clk_enable(clk);
>> >> ? ? ? ? ? ? ? /* Read repeatedly until the value is stable! */
>> >
>> > I was wondering if it pays to put this IOCTL to watchdog_dev and add another
>> > callback to watchdog_ops? I'd think so. Wim, Linus, what do you think?
>>
>> OK with me, shall I hack a patch?
>
> I think Viresh did something allready.

OK I rebased on top of Viresh's patch and sent them both out since
I don't know the status of his patch.

If you already have Viresh's patch in your tree just applying 2/2
should work as fine.

Yours,
Linus Walleij


From shawn.guo at linaro.org  Fri Mar 16 04:17:51 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:17:51 +0800
Subject: [PATCH 1/3] ARM i.MX: Move i.MX pwm driver to pwm framework
In-Reply-To: <20120316080832.GA6458@avionic-0098.mockup.avionic-design.de>
References: <1331802277-12477-1-git-send-email-s.hauer@pengutronix.de>
 <1331802277-12477-2-git-send-email-s.hauer@pengutronix.de>
 <20120316074902.GC7758@S2101-09.ap.freescale.net>
 <20120316080832.GA6458@avionic-0098.mockup.avionic-design.de>
Message-ID: <20120316081748.GF7758@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 09:08:32AM +0100, Thierry Reding wrote:
> * Shawn Guo wrote:
> > On Thu, Mar 15, 2012 at 10:04:35AM +0100, Sascha Hauer wrote:
> > > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> > > index e859c51..fc7571e 100644
> > > --- a/drivers/pwm/Makefile
> > > +++ b/drivers/pwm/Makefile
> > > @@ -1,4 +1,5 @@
> > >  obj-$(CONFIG_PWM)		+= core.o
> > >  obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
> > > +obj-$(CONFIG_PWM_IMX)		+= imx-pwm.o
> > 
> > s/imx-pwm.o/pwm-imx.o
> 
> Yes, I'll make that change when I integrate the patch in my series.
> 
Thanks for taking this on.

> > > @@ -98,7 +98,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
> > >  		else
> > >  			cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
> > >  
> > > -		writel(cr, pwm->mmio_base + MX3_PWMCR);
> > > +		writel(cr, imxpwm->mmio_base + MX3_PWMCR);
> > >  	} else if (cpu_is_mx1() || cpu_is_mx21()) {
> > 
> > Since we are here, can we move one step further to get rid of these
> > cpu_is_xxx()?  Then, we can remove <mach/hardware.h> inclusion from
> > the driver.
> 
> I guess this could be handled by using several names for the driver and
> handling the differences using a table of platform_device_id:s. Perhaps
> you had something different in mind?
> 
Same thing on my mind.

> > >  static int __devinit mxc_pwm_probe(struct platform_device *pdev)
> > 
> > Should we take this opportunity to rename the driver from mxc_pwm to
> > imx_pwm?
> 
> If we decide to rename maybe it should be done in two steps. First it can be
> renamed internally and in the second step the name could be changed along
> with all users. I just want to avoid too much churn in this series, which is
> already growing way larger than I had hoped.
> 
It seems I'm asking too much.  Okay, we can do that after it gets moved.

> > Also, does mxc_pwm_init need necessarily to be an arch_initcall?
> > Otherwise, we can have the following change.
> > 
> > -static int __init mxc_pwm_init(void)
> > -{
> > -       return platform_driver_register(&mxc_pwm_driver);
> > -}
> > -arch_initcall(mxc_pwm_init);
> > -
> > -static void __exit mxc_pwm_exit(void)
> > -{
> > -       platform_driver_unregister(&mxc_pwm_driver);
> > -}
> > -module_exit(mxc_pwm_exit);
> > +module_platform_driver(imx_pwm_driver);
> 
> I assume that some platforms may require it to be initialized early because
> other drivers may depend on the PWMs being present. However this can probably
> be solved in a much better way by using deferred driver probing, which should
> be available in 3.4.
> 
Ditto.

-- 
Regards,
Shawn


From paul.liu at linaro.org  Fri Mar 16 04:16:56 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Fri, 16 Mar 2012 16:16:56 +0800
Subject: [PATCH v10] mfd: Add anatop mfd driver
Message-ID: <1331885816-26902-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
Anatop provides regulators and thermal.
This driver handles the address space and the operation of the mfd device.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
Cc: Samuel Ortiz <sameo at linux.intel.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Venu Byravarasu <vbyravarasu at nvidia.com>
Cc: Peter Korsgaard <jacmet at sunsite.dk>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Rob Lee <rob.lee at linaro.org>
---
 drivers/mfd/Kconfig        |    8 +++
 drivers/mfd/Makefile       |    1 +
 drivers/mfd/anatop-mfd.c   |  137 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/anatop.h |   40 +++++++++++++
 4 files changed, 186 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mfd/anatop-mfd.c
 create mode 100644 include/linux/mfd/anatop.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 82da448..c3a9f31 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -846,6 +846,14 @@ config MFD_INTEL_MSIC
 	  Passage) chip. This chip embeds audio, battery, GPIO, etc.
 	  devices used in Intel Medfield platforms.
 
+config MFD_ANATOP
+	bool "Support for Freescale i.MX on-chip ANATOP controller"
+	depends on SOC_IMX6Q
+	help
+	  Select this option to enable Freescale i.MX on-chip ANATOP
+	  MFD controller. This controller embeds regulator and
+	  thermal devices for Freescale i.MX platforms.
+
 endmenu
 endif
 
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 27430d3..42c8bf6 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -113,3 +113,4 @@ obj-$(CONFIG_TPS65911_COMPARATOR)	+= tps65911-comparator.o
 obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
 obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
 obj-$(CONFIG_MFD_S5M_CORE)	+= s5m-core.o s5m-irq.o
+obj-$(CONFIG_MFD_ANATOP)	+= anatop-mfd.o
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
new file mode 100644
index 0000000..2af4248
--- /dev/null
+++ b/drivers/mfd/anatop-mfd.c
@@ -0,0 +1,137 @@
+/*
+ * Anatop MFD driver
+ *
+ * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ * Copyright (C) 2012 Linaro
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/mfd/anatop.h>
+
+u32 anatop_get_bits(struct anatop *adata, u32 addr, int bit_shift,
+		    int bit_width)
+{
+	u32 val, mask;
+
+	if (bit_width == 32)
+		mask = ~0;
+	else
+		mask = (1 << bit_width) - 1;
+
+	val = readl(adata->ioreg + addr);
+	val = (val >> bit_shift) & mask;
+
+	return val;
+}
+EXPORT_SYMBOL_GPL(anatop_get_bits);
+
+void anatop_set_bits(struct anatop *adata, u32 addr, int bit_shift,
+		     int bit_width, u32 data)
+{
+	u32 val, mask;
+
+	if (bit_width == 32)
+		mask = ~0;
+	else
+		mask = (1 << bit_width) - 1;
+
+	spin_lock(&adata->reglock);
+	val = readl(adata->ioreg + addr) & ~(mask << bit_shift);
+	writel((data << bit_shift) | val, adata->ioreg + addr);
+	spin_unlock(&adata->reglock);
+}
+EXPORT_SYMBOL_GPL(anatop_set_bits);
+
+static const struct of_device_id of_anatop_match[] = {
+	{ .compatible = "fsl,imx6q-anatop", },
+	{ },
+};
+
+static int __devinit of_anatop_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	void *ioreg;
+	struct anatop *drvdata;
+
+	ioreg = of_iomap(np, 0);
+	if (!ioreg)
+		return -EADDRNOTAVAIL;
+	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+	if (!drvdata)
+		return -ENOMEM;
+	drvdata->ioreg = ioreg;
+	spin_lock_init(&drvdata->reglock);
+	platform_set_drvdata(pdev, drvdata);
+	of_platform_populate(np, of_anatop_match, NULL, dev);
+
+	return 0;
+}
+
+static int __devexit of_anatop_remove(struct platform_device *pdev)
+{
+	struct anatop *drvdata;
+	drvdata = platform_get_drvdata(pdev);
+	iounmap(drvdata->ioreg);
+
+	return 0;
+}
+
+static struct platform_driver anatop_of_driver = {
+	.driver = {
+		.name = "anatop-mfd",
+		.owner = THIS_MODULE,
+		.of_match_table = of_anatop_match,
+	},
+	.probe		= of_anatop_probe,
+	.remove		= of_anatop_remove,
+};
+
+static int __init anatop_init(void)
+{
+	return platform_driver_register(&anatop_of_driver);
+}
+postcore_initcall(anatop_init);
+
+static void __exit anatop_exit(void)
+{
+	platform_driver_unregister(&anatop_of_driver);
+}
+module_exit(anatop_exit);
+
+MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("ANATOP MFD driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
new file mode 100644
index 0000000..22c1007
--- /dev/null
+++ b/include/linux/mfd/anatop.h
@@ -0,0 +1,40 @@
+/*
+ * anatop.h - Anatop MFD driver
+ *
+ *  Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
+ *  Copyright (C) 2012 Linaro
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_MFD_ANATOP_H
+#define __LINUX_MFD_ANATOP_H
+
+#include <linux/spinlock.h>
+
+/**
+ * anatop - MFD data
+ * @ioreg: ioremap register
+ * @reglock: spinlock for register read/write
+ */
+struct anatop {
+	void *ioreg;
+	spinlock_t reglock;
+};
+
+extern u32 anatop_get_bits(struct anatop *, u32, int, int);
+extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
+
+#endif /*  __LINUX_MFD_ANATOP_H */
-- 
1.7.9.1



From mgherzan at gmail.com  Fri Mar 16 04:17:24 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Fri, 16 Mar 2012 09:17:24 +0100
Subject: [PATCH v8] ARM: net: JIT compiler for packet filters
Message-ID: <1331885844-30575-1-git-send-email-mgherzan@gmail.com>

Based of Matt Evans's PPC64 implementation.

The compiler generates ARM instructions but interworking is
supported for Thumb2 kernels.

Supports both little and big endian. Unaligned loads are emitted
for ARMv6+. Not all the BPF opcodes that deal with ancillary data
are supported. The scratch memory of the filter lives on the stack.
Hardware integer division is used if it is available.

Enabled in the same way as for x86-64 and PPC64:

	echo 1 > /proc/sys/net/core/bpf_jit_enable

A value greater than 1 enables opcode output.

Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
---

Changes in v8:
 * skb_copy_bits() return value check in LDX_MSH
 * immediate value as signed integer for absolute loads

Changes in v7:
 * fix the intruction generation for LDX_MSH, OR_X, LSH_K,
   RSH_K and JMP_JA
 * fix the condition for saving the A register
 * use fls() instead of the compiler builtin
 * punt to the interpreter on absolute loads with K < 0
 * check for invalid data references
 * support the NEG opcode
 * clear X in the prologue based on a context flag
 * simplify the conditional jumps

Changes in v6:
 * fix the code generation for the ANC_CPU opcode

Changes in v5:
 * replace SEEN_LEN with SEEN_SKB
 * set ctx->seen when handling some ancillary data opcodes

Changes in v4:
 * first check if the JIT compiler is enabled
 * fix the code generation for the LDX_MSH opcode

Changes in v3:
 * no longer depend on EABI and !Thumb2
 * add BLX "emulation" for ARMv4 without Thumb
 * use the integer divide instruction on Cortex-A15
 * fix the handling of the DIV_K opcode
 * use a C wrapper for __aeabi_uidiv
 * fix the generation of the epilogue (non-FP case)

Changes in v2:
 * enable the compiler only for ARMv5+ because of the BLX instruction
 * use the same comparison for the ARM version checks
 * use misaligned accesses on ARMv6
 * fix the SEEN_MEM
 * fix the mem_words_used()

 arch/arm/Kconfig          |    1 +
 arch/arm/Makefile         |    1 +
 arch/arm/net/Makefile     |    3 +
 arch/arm/net/bpf_jit_32.c |  916 +++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/net/bpf_jit_32.h |  190 ++++++++++
 5 files changed, 1111 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/net/Makefile
 create mode 100644 arch/arm/net/bpf_jit_32.c
 create mode 100644 arch/arm/net/bpf_jit_32.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dfb0312..ade6274 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -32,6 +32,7 @@ config ARM
 	select GENERIC_IRQ_SHOW
 	select CPU_PM if (SUSPEND || CPU_IDLE)
 	select GENERIC_PCI_IOMAP
+	select HAVE_BPF_JIT
 	help
 	  The ARM series is a line of low-power-consumption RISC chip designs
 	  licensed by ARM Ltd and targeted at embedded applications and
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1683bfb..03b0039 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -252,6 +252,7 @@ core-$(CONFIG_VFP)		+= arch/arm/vfp/
 
 # If we have a machine-specific directory, then include it in the build.
 core-y				+= arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
+core-y				+= arch/arm/net/
 core-y				+= $(machdirs) $(platdirs)
 
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
diff --git a/arch/arm/net/Makefile b/arch/arm/net/Makefile
new file mode 100644
index 0000000..c2c1084
--- /dev/null
+++ b/arch/arm/net/Makefile
@@ -0,0 +1,3 @@
+# ARM-specific networking code
+
+obj-$(CONFIG_BPF_JIT) += bpf_jit_32.o
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
new file mode 100644
index 0000000..2ee157a
--- /dev/null
+++ b/arch/arm/net/bpf_jit_32.c
@@ -0,0 +1,916 @@
+/*
+ * Just-In-Time compiler for BPF filters on 32bit ARM
+ *
+ * Copyright (c) 2011 Mircea Gherzan <mgherzan at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/bitops.h>
+#include <linux/compiler.h>
+#include <linux/errno.h>
+#include <linux/filter.h>
+#include <linux/moduleloader.h>
+#include <linux/netdevice.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <asm/cacheflush.h>
+#include <asm/hwcap.h>
+
+#include "bpf_jit_32.h"
+
+/*
+ * ABI:
+ *
+ * r0	scratch register
+ * r4	BPF register A
+ * r5	BPF register X
+ * r6	pointer to the skb
+ * r7	skb->data
+ * r8	skb_headlen(skb)
+ */
+
+#define r_scratch	ARM_R0
+/* r1-r3 are (also) used for the unaligned loads on the non-ARMv7 slowpath */
+#define r_off		ARM_R1
+#define r_A		ARM_R4
+#define r_X		ARM_R5
+#define r_skb		ARM_R6
+#define r_skb_data	ARM_R7
+#define r_skb_hl	ARM_R8
+
+#define SCRATCH_SP_OFFSET	0
+#define SCRATCH_OFF(k)		(SCRATCH_SP_OFFSET + (k))
+
+#define SEEN_MEM		((1 << BPF_MEMWORDS) - 1)
+#define SEEN_MEM_WORD(k)	(1 << (k))
+#define SEEN_X			(1 << BPF_MEMWORDS)
+#define SEEN_CALL		(1 << (BPF_MEMWORDS + 1))
+#define SEEN_SKB		(1 << (BPF_MEMWORDS + 2))
+#define SEEN_DATA		(1 << (BPF_MEMWORDS + 3))
+
+#define FLAG_NEED_X_RESET	(1 << 0)
+
+struct jit_ctx {
+	const struct sk_filter *skf;
+	unsigned idx;
+	unsigned prologue_bytes;
+	int ret0_fp_idx;
+	u32 seen;
+	u32 flags;
+	u32 *offsets;
+	u32 *target;
+#if __LINUX_ARM_ARCH__ < 7
+	u16 epilogue_bytes;
+	u16 imm_count;
+	u32 *imms;
+#endif
+};
+
+int bpf_jit_enable __read_mostly;
+
+static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset)
+{
+	u8 ret;
+	int err;
+
+	err = skb_copy_bits(skb, offset, &ret, 1);
+
+	return (u64)err << 32 | ret;
+}
+
+static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset)
+{
+	u16 ret;
+	int err;
+
+	err = skb_copy_bits(skb, offset, &ret, 2);
+
+	return (u64)err << 32 | ntohs(ret);
+}
+
+static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset)
+{
+	u32 ret;
+	int err;
+
+	err = skb_copy_bits(skb, offset, &ret, 4);
+
+	return (u64)err << 32 | ntohl(ret);
+}
+
+/*
+ * Wrapper that handles both OABI and EABI and assures Thumb2 interworking
+ * (where the assembly routines like __aeabi_uidiv could cause problems).
+ */
+static u32 jit_udiv(u32 dividend, u32 divisor)
+{
+	return dividend / divisor;
+}
+
+static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx)
+{
+	if (ctx->target != NULL)
+		ctx->target[ctx->idx] = inst | (cond << 28);
+
+	ctx->idx++;
+}
+
+/*
+ * Emit an instruction that will be executed unconditionally.
+ */
+static inline void emit(u32 inst, struct jit_ctx *ctx)
+{
+	_emit(ARM_COND_AL, inst, ctx);
+}
+
+static u16 saved_regs(struct jit_ctx *ctx)
+{
+	u16 ret = 0;
+
+	if ((ctx->skf->len > 1) ||
+	    (ctx->skf->insns[0].code == BPF_S_RET_A))
+		ret |= 1 << r_A;
+
+#ifdef CONFIG_FRAME_POINTER
+	ret |= (1 << ARM_FP) | (1 << ARM_IP) | (1 << ARM_LR) | (1 << ARM_PC);
+#else
+	if (ctx->seen & SEEN_CALL)
+		ret |= 1 << ARM_LR;
+#endif
+	if (ctx->seen & (SEEN_DATA | SEEN_SKB))
+		ret |= 1 << r_skb;
+	if (ctx->seen & SEEN_DATA)
+		ret |= (1 << r_skb_data) | (1 << r_skb_hl);
+	if (ctx->seen & SEEN_X)
+		ret |= 1 << r_X;
+
+	return ret;
+}
+
+static inline int mem_words_used(struct jit_ctx *ctx)
+{
+	/* yes, we do waste some stack space IF there are "holes" in the set" */
+	return fls(ctx->seen & SEEN_MEM);
+}
+
+static inline bool is_load_to_a(u16 inst)
+{
+	switch (inst) {
+	case BPF_S_LD_W_LEN:
+	case BPF_S_LD_W_ABS:
+	case BPF_S_LD_H_ABS:
+	case BPF_S_LD_B_ABS:
+	case BPF_S_ANC_CPU:
+	case BPF_S_ANC_IFINDEX:
+	case BPF_S_ANC_MARK:
+	case BPF_S_ANC_PROTOCOL:
+	case BPF_S_ANC_RXHASH:
+	case BPF_S_ANC_QUEUE:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static void build_prologue(struct jit_ctx *ctx)
+{
+	u16 reg_set = saved_regs(ctx);
+	u16 first_inst = ctx->skf->insns[0].code;
+	u16 off;
+
+#ifdef CONFIG_FRAME_POINTER
+	emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx);
+	emit(ARM_PUSH(reg_set), ctx);
+	emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx);
+#else
+	if (reg_set)
+		emit(ARM_PUSH(reg_set), ctx);
+#endif
+
+	if (ctx->seen & (SEEN_DATA | SEEN_SKB))
+		emit(ARM_MOV_R(r_skb, ARM_R0), ctx);
+
+	if (ctx->seen & SEEN_DATA) {
+		off = offsetof(struct sk_buff, data);
+		emit(ARM_LDR_I(r_skb_data, r_skb, off), ctx);
+		/* headlen = len - data_len */
+		off = offsetof(struct sk_buff, len);
+		emit(ARM_LDR_I(r_skb_hl, r_skb, off), ctx);
+		off = offsetof(struct sk_buff, data_len);
+		emit(ARM_LDR_I(r_scratch, r_skb, off), ctx);
+		emit(ARM_SUB_R(r_skb_hl, r_skb_hl, r_scratch), ctx);
+	}
+
+	if (ctx->flags & FLAG_NEED_X_RESET)
+		emit(ARM_MOV_I(r_X, 0), ctx);
+
+	/* do not leak kernel data to userspace */
+	if ((first_inst != BPF_S_RET_K) && !(is_load_to_a(first_inst)))
+		emit(ARM_MOV_I(r_A, 0), ctx);
+
+	/* stack space for the BPF_MEM words */
+	if (ctx->seen & SEEN_MEM)
+		emit(ARM_SUB_I(ARM_SP, ARM_SP, mem_words_used(ctx) * 4), ctx);
+}
+
+static void build_epilogue(struct jit_ctx *ctx)
+{
+	u16 reg_set = saved_regs(ctx);
+
+	if (ctx->seen & SEEN_MEM)
+		emit(ARM_ADD_I(ARM_SP, ARM_SP, mem_words_used(ctx) * 4), ctx);
+
+	reg_set &= ~(1 << ARM_LR);
+
+#ifdef CONFIG_FRAME_POINTER
+	/* the first instruction of the prologue was: mov ip, sp */
+	reg_set &= ~(1 << ARM_IP);
+	reg_set |= (1 << ARM_SP);
+	emit(ARM_LDM(ARM_SP, reg_set), ctx);
+#else
+	if (reg_set) {
+		if (ctx->seen & SEEN_CALL)
+			reg_set |= 1 << ARM_PC;
+		emit(ARM_POP(reg_set), ctx);
+	}
+
+	if (!(ctx->seen & SEEN_CALL))
+		emit(ARM_BX(ARM_LR), ctx);
+#endif
+}
+
+static int16_t imm8m(u32 x)
+{
+	u32 rot;
+
+	for (rot = 0; rot < 16; rot++)
+		if ((x & ~ror32(0xff, 2 * rot)) == 0)
+			return rol32(x, 2 * rot) | (rot << 8);
+
+	return -1;
+}
+
+#if __LINUX_ARM_ARCH__ < 7
+
+static u16 imm_offset(u32 k, struct jit_ctx *ctx)
+{
+	unsigned i = 0, offset;
+	u16 imm;
+
+	/* on the "fake" run we just count them (duplicates included) */
+	if (ctx->target == NULL) {
+		ctx->imm_count++;
+		return 0;
+	}
+
+	while ((i < ctx->imm_count) && ctx->imms[i]) {
+		if (ctx->imms[i] == k)
+			break;
+		i++;
+	}
+
+	if (ctx->imms[i] == 0)
+		ctx->imms[i] = k;
+
+	/* constants go just after the epilogue */
+	offset =  ctx->offsets[ctx->skf->len];
+	offset += ctx->prologue_bytes;
+	offset += ctx->epilogue_bytes;
+	offset += i * 4;
+
+	ctx->target[offset / 4] = k;
+
+	/* PC in ARM mode == address of the instruction + 8 */
+	imm = offset - (8 + ctx->idx * 4);
+
+	return imm;
+}
+
+#endif /* __LINUX_ARM_ARCH__ */
+
+/*
+ * Move an immediate that's not an imm8m to a core register.
+ */
+static inline void emit_mov_i_no8m(int rd, u32 val, struct jit_ctx *ctx)
+{
+#if __LINUX_ARM_ARCH__ < 7
+	emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx);
+#else
+	emit(ARM_MOVW(rd, val & 0xffff), ctx);
+	if (val > 0xffff)
+		emit(ARM_MOVT(rd, val >> 16), ctx);
+#endif
+}
+
+static inline void emit_mov_i(int rd, u32 val, struct jit_ctx *ctx)
+{
+	int imm12 = imm8m(val);
+
+	if (imm12 >= 0)
+		emit(ARM_MOV_I(rd, imm12), ctx);
+	else
+		emit_mov_i_no8m(rd, val, ctx);
+}
+
+#if __LINUX_ARM_ARCH__ < 6
+
+static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
+{
+	_emit(cond, ARM_LDRB_I(ARM_R3, r_addr, 1), ctx);
+	_emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx);
+	_emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 3), ctx);
+	_emit(cond, ARM_LSL_I(ARM_R3, ARM_R3, 16), ctx);
+	_emit(cond, ARM_LDRB_I(ARM_R0, r_addr, 2), ctx);
+	_emit(cond, ARM_ORR_S(ARM_R3, ARM_R3, ARM_R1, SRTYPE_LSL, 24), ctx);
+	_emit(cond, ARM_ORR_R(ARM_R3, ARM_R3, ARM_R2), ctx);
+	_emit(cond, ARM_ORR_S(r_res, ARM_R3, ARM_R0, SRTYPE_LSL, 8), ctx);
+}
+
+static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
+{
+	_emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx);
+	_emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 1), ctx);
+	_emit(cond, ARM_ORR_S(r_res, ARM_R2, ARM_R1, SRTYPE_LSL, 8), ctx);
+}
+
+static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx)
+{
+	emit(ARM_LSL_R(ARM_R1, r_src, 8), ctx);
+	emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSL, 8), ctx);
+	emit(ARM_LSL_I(r_dst, r_dst, 8), ctx);
+	emit(ARM_LSL_R(r_dst, r_dst, 8), ctx);
+}
+
+#else  /* ARMv6+ */
+
+static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
+{
+	_emit(cond, ARM_LDR_I(r_res, r_addr, 0), ctx);
+#ifdef __LITTLE_ENDIAN
+	_emit(cond, ARM_REV(r_res, r_res), ctx);
+#endif
+}
+
+static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
+{
+	_emit(cond, ARM_LDRH_I(r_res, r_addr, 0), ctx);
+#ifdef __LITTLE_ENDIAN
+	_emit(cond, ARM_REV16(r_res, r_res), ctx);
+#endif
+}
+
+static inline void emit_swap16(u8 r_dst __maybe_unused,
+			       u8 r_src __maybe_unused,
+			       struct jit_ctx *ctx __maybe_unused)
+{
+#ifdef __LITTLE_ENDIAN
+	emit(ARM_REV16(r_dst, r_src), ctx);
+#endif
+}
+
+#endif /* __LINUX_ARM_ARCH__ < 6 */
+
+
+/* Compute the immediate value for a PC-relative branch. */
+static inline u32 b_imm(unsigned tgt, struct jit_ctx *ctx)
+{
+	u32 imm;
+
+	if (ctx->target == NULL)
+		return 0;
+	/*
+	 * BPF allows only forward jumps and the offset of the target is
+	 * still the one computed during the first pass.
+	 */
+	imm  = ctx->offsets[tgt] + ctx->prologue_bytes - (ctx->idx * 4 + 8);
+
+	return imm >> 2;
+}
+
+#define OP_IMM3(op, r1, r2, imm_val, ctx)				\
+	do {								\
+		imm12 = imm8m(imm_val);					\
+		if (imm12 < 0) {					\
+			emit_mov_i_no8m(r_scratch, imm_val, ctx);	\
+			emit(op ## _R((r1), (r2), r_scratch), ctx);	\
+		} else {						\
+			emit(op ## _I((r1), (r2), imm12), ctx);		\
+		}							\
+	} while (0)
+
+static inline void emit_err_ret(u8 cond, struct jit_ctx *ctx)
+{
+	if (ctx->ret0_fp_idx >= 0) {
+		_emit(cond, ARM_B(b_imm(ctx->ret0_fp_idx, ctx)), ctx);
+		/* NOP to keep the size constant between passes */
+		emit(ARM_MOV_R(ARM_R0, ARM_R0), ctx);
+	} else {
+		_emit(cond, ARM_MOV_I(ARM_R0, 0), ctx);
+		_emit(cond, ARM_B(b_imm(ctx->skf->len, ctx)), ctx);
+	}
+}
+
+static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
+{
+#if __LINUX_ARM_ARCH__ < 5
+	emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
+
+	if (elf_hwcap & HWCAP_THUMB)
+		emit(ARM_BX(tgt_reg), ctx);
+	else
+		emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx);
+#else
+	emit(ARM_BLX_R(tgt_reg), ctx);
+#endif
+}
+
+static inline void emit_udiv(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx)
+{
+#if __LINUX_ARM_ARCH__ == 7
+	if (elf_hwcap & HWCAP_IDIVA) {
+		emit(ARM_UDIV(rd, rm, rn), ctx);
+		return;
+	}
+#endif
+	if (rm != ARM_R0)
+		emit(ARM_MOV_R(ARM_R0, rm), ctx);
+	if (rn != ARM_R1)
+		emit(ARM_MOV_R(ARM_R1, rn), ctx);
+
+	ctx->seen |= SEEN_CALL;
+	emit_mov_i(ARM_R3, (u32)jit_udiv, ctx);
+	emit_blx_r(ARM_R3, ctx);
+
+	if (rd != ARM_R0)
+		emit(ARM_MOV_R(rd, ARM_R0), ctx);
+}
+
+static inline void update_on_xread(struct jit_ctx *ctx)
+{
+	if (!(ctx->seen & SEEN_X))
+		ctx->flags |= FLAG_NEED_X_RESET;
+
+	ctx->seen |= SEEN_X;
+}
+
+static int build_body(struct jit_ctx *ctx)
+{
+	void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
+	const struct sk_filter *prog = ctx->skf;
+	const struct sock_filter *inst;
+	unsigned i, load_order, off, condt;
+	int imm12;
+	u32 k;
+
+	for (i = 0; i < prog->len; i++) {
+		inst = &(prog->insns[i]);
+		/* K as an immediate value operand */
+		k = inst->k;
+
+		/* compute offsets only in the fake pass */
+		if (ctx->target == NULL)
+			ctx->offsets[i] = ctx->idx * 4;
+
+		switch (inst->code) {
+		case BPF_S_LD_IMM:
+			emit_mov_i(r_A, k, ctx);
+			break;
+		case BPF_S_LD_W_LEN:
+			ctx->seen |= SEEN_SKB;
+			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
+			emit(ARM_LDR_I(r_A, r_skb,
+				       offsetof(struct sk_buff, len)), ctx);
+			break;
+		case BPF_S_LD_MEM:
+			/* A = scratch[k] */
+			ctx->seen |= SEEN_MEM_WORD(k);
+			emit(ARM_LDR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
+			break;
+		case BPF_S_LD_W_ABS:
+			load_order = 2;
+			goto load;
+		case BPF_S_LD_H_ABS:
+			load_order = 1;
+			goto load;
+		case BPF_S_LD_B_ABS:
+			load_order = 0;
+load:
+			/* the interpreter will deal with the negative K */
+			if ((int)k < 0)
+				return -ENOTSUPP;
+			emit_mov_i(r_off, k, ctx);
+load_common:
+			ctx->seen |= SEEN_DATA | SEEN_CALL;
+
+			if (load_order > 0) {
+				emit(ARM_SUB_I(r_scratch, r_skb_hl,
+					       1 << load_order), ctx);
+				emit(ARM_CMP_R(r_scratch, r_off), ctx);
+				condt = ARM_COND_HS;
+			} else {
+				emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
+				condt = ARM_COND_HI;
+			}
+
+			_emit(condt, ARM_ADD_R(r_scratch, r_off, r_skb_data),
+			      ctx);
+
+			if (load_order == 0)
+				_emit(condt, ARM_LDRB_I(r_A, r_scratch, 0),
+				      ctx);
+			else if (load_order == 1)
+				emit_load_be16(condt, r_A, r_scratch, ctx);
+			else if (load_order == 2)
+				emit_load_be32(condt, r_A, r_scratch, ctx);
+
+			_emit(condt, ARM_B(b_imm(i + 1, ctx)), ctx);
+
+			/* the slowpath */
+			emit_mov_i(ARM_R3, (u32)load_func[load_order], ctx);
+			emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
+			/* the offset is already in R1 */
+			emit_blx_r(ARM_R3, ctx);
+			/* check the result of skb_copy_bits */
+			emit(ARM_CMP_I(ARM_R1, 0), ctx);
+			emit_err_ret(ARM_COND_NE, ctx);
+			emit(ARM_MOV_R(r_A, ARM_R0), ctx);
+			break;
+		case BPF_S_LD_W_IND:
+			load_order = 2;
+			goto load_ind;
+		case BPF_S_LD_H_IND:
+			load_order = 1;
+			goto load_ind;
+		case BPF_S_LD_B_IND:
+			load_order = 0;
+load_ind:
+			OP_IMM3(ARM_ADD, r_off, r_X, k, ctx);
+			goto load_common;
+		case BPF_S_LDX_IMM:
+			ctx->seen |= SEEN_X;
+			emit_mov_i(r_X, k, ctx);
+			break;
+		case BPF_S_LDX_W_LEN:
+			ctx->seen |= SEEN_X | SEEN_SKB;
+			emit(ARM_LDR_I(r_X, r_skb,
+				       offsetof(struct sk_buff, len)), ctx);
+			break;
+		case BPF_S_LDX_MEM:
+			ctx->seen |= SEEN_X | SEEN_MEM_WORD(k);
+			emit(ARM_LDR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
+			break;
+		case BPF_S_LDX_B_MSH:
+			/* x = ((*(frame + k)) & 0xf) << 2; */
+			ctx->seen |= SEEN_X | SEEN_DATA | SEEN_CALL;
+			/* the interpreter should deal with the negative K */
+			if (k < 0)
+				return -1;
+			/* offset in r1: we might have to take the slow path */
+			emit_mov_i(r_off, k, ctx);
+			emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
+
+			/* load in r0: common with the slowpath */
+			_emit(ARM_COND_HI, ARM_LDRB_R(ARM_R0, r_skb_data,
+						      ARM_R1), ctx);
+			/*
+			 * emit_mov_i() might generate one or two instructions,
+			 * the same holds for emit_blx_r()
+			 */
+			_emit(ARM_COND_HI, ARM_B(b_imm(i + 1, ctx) - 2), ctx);
+
+			emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
+			/* r_off is r1 */
+			emit_mov_i(ARM_R3, (u32)jit_get_skb_b, ctx);
+			emit_blx_r(ARM_R3, ctx);
+			/* check the return value of skb_copy_bits */
+			emit(ARM_CMP_I(ARM_R1, 0), ctx);
+			emit_err_ret(ARM_COND_NE, ctx);
+
+			emit(ARM_AND_I(r_X, ARM_R0, 0x00f), ctx);
+			emit(ARM_LSL_I(r_X, r_X, 2), ctx);
+			break;
+		case BPF_S_ST:
+			ctx->seen |= SEEN_MEM_WORD(k);
+			emit(ARM_STR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
+			break;
+		case BPF_S_STX:
+			update_on_xread(ctx);
+			ctx->seen |= SEEN_MEM_WORD(k);
+			emit(ARM_STR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
+			break;
+		case BPF_S_ALU_ADD_K:
+			/* A += K */
+			OP_IMM3(ARM_ADD, r_A, r_A, k, ctx);
+			break;
+		case BPF_S_ALU_ADD_X:
+			update_on_xread(ctx);
+			emit(ARM_ADD_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_SUB_K:
+			/* A -= K */
+			OP_IMM3(ARM_SUB, r_A, r_A, k, ctx);
+			break;
+		case BPF_S_ALU_SUB_X:
+			update_on_xread(ctx);
+			emit(ARM_SUB_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_MUL_K:
+			/* A *= K */
+			emit_mov_i(r_scratch, k, ctx);
+			emit(ARM_MUL(r_A, r_A, r_scratch), ctx);
+			break;
+		case BPF_S_ALU_MUL_X:
+			update_on_xread(ctx);
+			emit(ARM_MUL(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_DIV_K:
+			/* current k == reciprocal_value(userspace k) */
+			emit_mov_i(r_scratch, k, ctx);
+			/* A = top 32 bits of the product */
+			emit(ARM_UMULL(r_scratch, r_A, r_A, r_scratch), ctx);
+			break;
+		case BPF_S_ALU_DIV_X:
+			update_on_xread(ctx);
+			emit(ARM_CMP_I(r_X, 0), ctx);
+			emit_err_ret(ARM_COND_EQ, ctx);
+			emit_udiv(r_A, r_A, r_X, ctx);
+			break;
+		case BPF_S_ALU_OR_K:
+			/* A |= K */
+			OP_IMM3(ARM_ORR, r_A, r_A, k, ctx);
+			break;
+		case BPF_S_ALU_OR_X:
+			update_on_xread(ctx);
+			emit(ARM_ORR_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_AND_K:
+			/* A &= K */
+			OP_IMM3(ARM_AND, r_A, r_A, k, ctx);
+			break;
+		case BPF_S_ALU_AND_X:
+			update_on_xread(ctx);
+			emit(ARM_AND_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_LSH_K:
+			if (unlikely(k > 31))
+				return -1;
+			emit(ARM_LSL_I(r_A, r_A, k), ctx);
+			break;
+		case BPF_S_ALU_LSH_X:
+			update_on_xread(ctx);
+			emit(ARM_LSL_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_RSH_K:
+			if (unlikely(k > 31))
+				return -1;
+			emit(ARM_LSR_I(r_A, r_A, k), ctx);
+			break;
+		case BPF_S_ALU_RSH_X:
+			update_on_xread(ctx);
+			emit(ARM_LSR_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_NEG:
+			/* A = -A */
+			emit(ARM_RSB_I(r_A, r_A, 0), ctx);
+			break;
+		case BPF_S_JMP_JA:
+			/* pc += K */
+			emit(ARM_B(b_imm(i + k + 1, ctx)), ctx);
+			break;
+		case BPF_S_JMP_JEQ_K:
+			/* pc += (A == K) ? pc->jt : pc->jf */
+			condt  = ARM_COND_EQ;
+			goto cmp_imm;
+		case BPF_S_JMP_JGT_K:
+			/* pc += (A > K) ? pc->jt : pc->jf */
+			condt  = ARM_COND_HI;
+			goto cmp_imm;
+		case BPF_S_JMP_JGE_K:
+			/* pc += (A >= K) ? pc->jt : pc->jf */
+			condt  = ARM_COND_HS;
+cmp_imm:
+			imm12 = imm8m(k);
+			if (imm12 < 0) {
+				emit_mov_i_no8m(r_scratch, k, ctx);
+				emit(ARM_CMP_R(r_A, r_scratch), ctx);
+			} else {
+				emit(ARM_CMP_I(r_A, imm12), ctx);
+			}
+cond_jump:
+			if (inst->jt)
+				_emit(condt, ARM_B(b_imm(i + inst->jt + 1,
+						   ctx)), ctx);
+			if (inst->jf)
+				_emit(condt ^ 1, ARM_B(b_imm(i + inst->jf + 1,
+							     ctx)), ctx);
+			break;
+		case BPF_S_JMP_JEQ_X:
+			/* pc += (A == X) ? pc->jt : pc->jf */
+			condt   = ARM_COND_EQ;
+			goto cmp_x;
+		case BPF_S_JMP_JGT_X:
+			/* pc += (A > X) ? pc->jt : pc->jf */
+			condt   = ARM_COND_HI;
+			goto cmp_x;
+		case BPF_S_JMP_JGE_X:
+			/* pc += (A >= X) ? pc->jt : pc->jf */
+			condt   = ARM_COND_CS;
+cmp_x:
+			update_on_xread(ctx);
+			emit(ARM_CMP_R(r_A, r_X), ctx);
+			goto cond_jump;
+		case BPF_S_JMP_JSET_K:
+			/* pc += (A & K) ? pc->jt : pc->jf */
+			condt  = ARM_COND_NE;
+			/* not set iff all zeroes iff Z==1 iff EQ */
+
+			imm12 = imm8m(k);
+			if (imm12 < 0) {
+				emit_mov_i_no8m(r_scratch, k, ctx);
+				emit(ARM_TST_R(r_A, r_scratch), ctx);
+			} else {
+				emit(ARM_TST_I(r_A, imm12), ctx);
+			}
+			goto cond_jump;
+		case BPF_S_JMP_JSET_X:
+			/* pc += (A & X) ? pc->jt : pc->jf */
+			update_on_xread(ctx);
+			condt  = ARM_COND_NE;
+			emit(ARM_TST_R(r_A, r_X), ctx);
+			goto cond_jump;
+		case BPF_S_RET_A:
+			emit(ARM_MOV_R(ARM_R0, r_A), ctx);
+			goto b_epilogue;
+		case BPF_S_RET_K:
+			if ((k == 0) && (ctx->ret0_fp_idx < 0))
+				ctx->ret0_fp_idx = i;
+			emit_mov_i(ARM_R0, k, ctx);
+b_epilogue:
+			if (i != ctx->skf->len - 1)
+				emit(ARM_B(b_imm(prog->len, ctx)), ctx);
+			break;
+		case BPF_S_MISC_TAX:
+			/* X = A */
+			ctx->seen |= SEEN_X;
+			emit(ARM_MOV_R(r_X, r_A), ctx);
+			break;
+		case BPF_S_MISC_TXA:
+			/* A = X */
+			update_on_xread(ctx);
+			emit(ARM_MOV_R(r_A, r_X), ctx);
+			break;
+		case BPF_S_ANC_PROTOCOL:
+			/* A = ntohs(skb->protocol) */
+			ctx->seen |= SEEN_SKB;
+			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
+						  protocol) != 2);
+			off = offsetof(struct sk_buff, protocol);
+			emit(ARM_LDRH_I(r_scratch, r_skb, off), ctx);
+			emit_swap16(r_A, r_scratch, ctx);
+			break;
+		case BPF_S_ANC_CPU:
+			/* r_scratch = current_thread_info() */
+			OP_IMM3(ARM_BIC, r_scratch, ARM_SP, THREAD_SIZE - 1, ctx);
+			/* A = current_thread_info()->cpu */
+			BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info, cpu) != 4);
+			off = offsetof(struct thread_info, cpu);
+			emit(ARM_LDR_I(r_A, r_scratch, off), ctx);
+			break;
+		case BPF_S_ANC_IFINDEX:
+			/* A = skb->dev->ifindex */
+			ctx->seen |= SEEN_SKB;
+			off = offsetof(struct sk_buff, dev);
+			emit(ARM_LDR_I(r_scratch, r_skb, off), ctx);
+
+			emit(ARM_CMP_I(r_scratch, 0), ctx);
+			emit_err_ret(ARM_COND_EQ, ctx);
+
+			BUILD_BUG_ON(FIELD_SIZEOF(struct net_device,
+						  ifindex) != 4);
+			off = offsetof(struct net_device, ifindex);
+			emit(ARM_LDR_I(r_A, r_scratch, off), ctx);
+			break;
+		case BPF_S_ANC_MARK:
+			ctx->seen |= SEEN_SKB;
+			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
+			off = offsetof(struct sk_buff, mark);
+			emit(ARM_LDR_I(r_A, r_skb, off), ctx);
+			break;
+		case BPF_S_ANC_RXHASH:
+			ctx->seen |= SEEN_SKB;
+			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, rxhash) != 4);
+			off = offsetof(struct sk_buff, rxhash);
+			emit(ARM_LDR_I(r_A, r_skb, off), ctx);
+			break;
+		case BPF_S_ANC_QUEUE:
+			ctx->seen |= SEEN_SKB;
+			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
+						  queue_mapping) != 2);
+			BUILD_BUG_ON(offsetof(struct sk_buff,
+					      queue_mapping) > 0xff);
+			off = offsetof(struct sk_buff, queue_mapping);
+			emit(ARM_LDRH_I(r_A, r_skb, off), ctx);
+			break;
+		default:
+			return -1;
+		}
+	}
+
+	/* compute offsets only during the first pass */
+	if (ctx->target == NULL)
+		ctx->offsets[i] = ctx->idx * 4;
+
+	return 0;
+}
+
+
+void bpf_jit_compile(struct sk_filter *fp)
+{
+	struct jit_ctx ctx;
+	unsigned tmp_idx;
+	unsigned alloc_size;
+
+	if (!bpf_jit_enable)
+		return;
+
+	memset(&ctx, 0, sizeof(ctx));
+	ctx.skf		= fp;
+	ctx.ret0_fp_idx = -1;
+
+	ctx.offsets = kzalloc(GFP_KERNEL, 4 * (ctx.skf->len + 1));
+	if (ctx.offsets == NULL)
+		return;
+
+	/* fake pass to fill in the ctx->seen */
+	if (unlikely(build_body(&ctx)))
+		goto out;
+
+	tmp_idx = ctx.idx;
+	build_prologue(&ctx);
+	ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
+
+#if __LINUX_ARM_ARCH__ < 7
+	tmp_idx = ctx.idx;
+	build_epilogue(&ctx);
+	ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4;
+
+	ctx.idx += ctx.imm_count;
+	if (ctx.imm_count) {
+		ctx.imms = kzalloc(GFP_KERNEL, 4 * ctx.imm_count);
+		if (ctx.imms == NULL)
+			goto out;
+	}
+#else
+	/* there's nothing after the epilogue on ARMv7 */
+	build_epilogue(&ctx);
+#endif
+
+	alloc_size = 4 * ctx.idx;
+	ctx.target = module_alloc(max(sizeof(struct work_struct),
+				      alloc_size));
+	if (unlikely(ctx.target == NULL))
+		goto out;
+
+	ctx.idx = 0;
+	build_prologue(&ctx);
+	build_body(&ctx);
+	build_epilogue(&ctx);
+
+	flush_icache_range((u32)ctx.target, (u32)(ctx.target + ctx.idx));
+
+#if __LINUX_ARM_ARCH__ < 7
+	if (ctx.imm_count)
+		kfree(ctx.imms);
+#endif
+
+	if (bpf_jit_enable > 1)
+		print_hex_dump(KERN_INFO, "BPF JIT code: ",
+			       DUMP_PREFIX_ADDRESS, 16, 4, ctx.target,
+			       alloc_size, false);
+
+	fp->bpf_func = (void *)ctx.target;
+out:
+	kfree(ctx.offsets);
+	return;
+}
+
+static void bpf_jit_free_worker(struct work_struct *work)
+{
+	module_free(NULL, work);
+}
+
+void bpf_jit_free(struct sk_filter *fp)
+{
+	struct work_struct *work;
+
+	if (fp->bpf_func != sk_run_filter) {
+		work = (struct work_struct *)fp->bpf_func;
+
+		INIT_WORK(work, bpf_jit_free_worker);
+		schedule_work(work);
+	}
+}
+
diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
new file mode 100644
index 0000000..99ae5e3
--- /dev/null
+++ b/arch/arm/net/bpf_jit_32.h
@@ -0,0 +1,190 @@
+/*
+ * Just-In-Time compiler for BPF filters on 32bit ARM
+ *
+ * Copyright (c) 2011 Mircea Gherzan <mgherzan at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ */
+
+#ifndef PFILTER_OPCODES_ARM_H
+#define PFILTER_OPCODES_ARM_H
+
+#define ARM_R0	0
+#define ARM_R1	1
+#define ARM_R2	2
+#define ARM_R3	3
+#define ARM_R4	4
+#define ARM_R5	5
+#define ARM_R6	6
+#define ARM_R7	7
+#define ARM_R8	8
+#define ARM_R9	9
+#define ARM_R10	10
+#define ARM_FP	11
+#define ARM_IP	12
+#define ARM_SP	13
+#define ARM_LR	14
+#define ARM_PC	15
+
+#define ARM_COND_EQ		0x0
+#define ARM_COND_NE		0x1
+#define ARM_COND_CS		0x2
+#define ARM_COND_HS		ARM_COND_CS
+#define ARM_COND_CC		0x3
+#define ARM_COND_LO		ARM_COND_CC
+#define ARM_COND_MI		0x4
+#define ARM_COND_PL		0x5
+#define ARM_COND_VS		0x6
+#define ARM_COND_VC		0x7
+#define ARM_COND_HI		0x8
+#define ARM_COND_LS		0x9
+#define ARM_COND_GE		0xa
+#define ARM_COND_LT		0xb
+#define ARM_COND_GT		0xc
+#define ARM_COND_LE		0xd
+#define ARM_COND_AL		0xe
+
+/* register shift types */
+#define SRTYPE_LSL		0
+#define SRTYPE_LSR		1
+#define SRTYPE_ASR		2
+#define SRTYPE_ROR		3
+
+#define ARM_INST_ADD_R		0x00800000
+#define ARM_INST_ADD_I		0x02800000
+
+#define ARM_INST_AND_R		0x00000000
+#define ARM_INST_AND_I		0x02000000
+
+#define ARM_INST_BIC_R		0x01c00000
+#define ARM_INST_BIC_I		0x03c00000
+
+#define ARM_INST_B		0x0a000000
+#define ARM_INST_BX		0x012FFF10
+#define ARM_INST_BLX_R		0x012fff30
+
+#define ARM_INST_CMP_R		0x01500000
+#define ARM_INST_CMP_I		0x03500000
+
+#define ARM_INST_LDRB_I		0x05d00000
+#define ARM_INST_LDRB_R		0x07d00000
+#define ARM_INST_LDRH_I		0x01d000b0
+#define ARM_INST_LDR_I		0x05900000
+
+#define ARM_INST_LDM		0x08900000
+
+#define ARM_INST_LSL_I		0x01a00000
+#define ARM_INST_LSL_R		0x01a00010
+
+#define ARM_INST_LSR_I		0x01a00020
+#define ARM_INST_LSR_R		0x01a00030
+
+#define ARM_INST_MOV_R		0x01a00000
+#define ARM_INST_MOV_I		0x03a00000
+#define ARM_INST_MOVW		0x03000000
+#define ARM_INST_MOVT		0x03400000
+
+#define ARM_INST_MUL		0x00000090
+
+#define ARM_INST_POP		0x08bd0000
+#define ARM_INST_PUSH		0x092d0000
+
+#define ARM_INST_ORR_R		0x01800000
+#define ARM_INST_ORR_I		0x03800000
+
+#define ARM_INST_REV		0x06bf0f30
+#define ARM_INST_REV16		0x06bf0fb0
+
+#define ARM_INST_RSB_I		0x02600000
+
+#define ARM_INST_SUB_R		0x00400000
+#define ARM_INST_SUB_I		0x02400000
+
+#define ARM_INST_STR_I		0x05800000
+
+#define ARM_INST_TST_R		0x01100000
+#define ARM_INST_TST_I		0x03100000
+
+#define ARM_INST_UDIV		0x0730f010
+
+#define ARM_INST_UMULL		0x00800090
+
+/* register */
+#define _AL3_R(op, rd, rn, rm)	((op ## _R) | (rd) << 12 | (rn) << 16 | (rm))
+/* immediate */
+#define _AL3_I(op, rd, rn, imm)	((op ## _I) | (rd) << 12 | (rn) << 16 | (imm))
+
+#define ARM_ADD_R(rd, rn, rm)	_AL3_R(ARM_INST_ADD, rd, rn, rm)
+#define ARM_ADD_I(rd, rn, imm)	_AL3_I(ARM_INST_ADD, rd, rn, imm)
+
+#define ARM_AND_R(rd, rn, rm)	_AL3_R(ARM_INST_AND, rd, rn, rm)
+#define ARM_AND_I(rd, rn, imm)	_AL3_I(ARM_INST_AND, rd, rn, imm)
+
+#define ARM_BIC_R(rd, rn, rm)	_AL3_R(ARM_INST_BIC, rd, rn, rm)
+#define ARM_BIC_I(rd, rn, imm)	_AL3_I(ARM_INST_BIC, rd, rn, imm)
+
+#define ARM_B(imm24)		(ARM_INST_B | ((imm24) & 0xffffff))
+#define ARM_BX(rm)		(ARM_INST_BX | (rm))
+#define ARM_BLX_R(rm)		(ARM_INST_BLX_R | (rm))
+
+#define ARM_CMP_R(rn, rm)	_AL3_R(ARM_INST_CMP, 0, rn, rm)
+#define ARM_CMP_I(rn, imm)	_AL3_I(ARM_INST_CMP, 0, rn, imm)
+
+#define ARM_LDR_I(rt, rn, off)	(ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \
+				 | (off))
+#define ARM_LDRB_I(rt, rn, off)	(ARM_INST_LDRB_I | (rt) << 12 | (rn) << 16 \
+				 | (off))
+#define ARM_LDRB_R(rt, rn, rm)	(ARM_INST_LDRB_R | (rt) << 12 | (rn) << 16 \
+				 | (rm))
+#define ARM_LDRH_I(rt, rn, off)	(ARM_INST_LDRH_I | (rt) << 12 | (rn) << 16 \
+				 | (((off) & 0xf0) << 4) | ((off) & 0xf))
+
+#define ARM_LDM(rn, regs)	(ARM_INST_LDM | (rn) << 16 | (regs))
+
+#define ARM_LSL_R(rd, rn, rm)	(_AL3_R(ARM_INST_LSL, rd, 0, rn) | (rm) << 8)
+#define ARM_LSL_I(rd, rn, imm)	(_AL3_I(ARM_INST_LSL, rd, 0, rn) | (imm) << 7)
+
+#define ARM_LSR_R(rd, rn, rm)	(_AL3_R(ARM_INST_LSR, rd, 0, rn) | (rm) << 8)
+#define ARM_LSR_I(rd, rn, imm)	(_AL3_I(ARM_INST_LSR, rd, 0, rn) | (imm) << 7)
+
+#define ARM_MOV_R(rd, rm)	_AL3_R(ARM_INST_MOV, rd, 0, rm)
+#define ARM_MOV_I(rd, imm)	_AL3_I(ARM_INST_MOV, rd, 0, imm)
+
+#define ARM_MOVW(rd, imm)	\
+	(ARM_INST_MOVW | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
+
+#define ARM_MOVT(rd, imm)	\
+	(ARM_INST_MOVT | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
+
+#define ARM_MUL(rd, rm, rn)	(ARM_INST_MUL | (rd) << 16 | (rm) << 8 | (rn))
+
+#define ARM_POP(regs)		(ARM_INST_POP | (regs))
+#define ARM_PUSH(regs)		(ARM_INST_PUSH | (regs))
+
+#define ARM_ORR_R(rd, rn, rm)	_AL3_R(ARM_INST_ORR, rd, rn, rm)
+#define ARM_ORR_I(rd, rn, imm)	_AL3_I(ARM_INST_ORR, rd, rn, imm)
+#define ARM_ORR_S(rd, rn, rm, type, rs)	\
+	(ARM_ORR_R(rd, rn, rm) | (type) << 5 | (rs) << 7)
+
+#define ARM_REV(rd, rm)		(ARM_INST_REV | (rd) << 12 | (rm))
+#define ARM_REV16(rd, rm)	(ARM_INST_REV16 | (rd) << 12 | (rm))
+
+#define ARM_RSB_I(rd, rn, imm)	_AL3_I(ARM_INST_RSB, rd, rn, imm)
+
+#define ARM_SUB_R(rd, rn, rm)	_AL3_R(ARM_INST_SUB, rd, rn, rm)
+#define ARM_SUB_I(rd, rn, imm)	_AL3_I(ARM_INST_SUB, rd, rn, imm)
+
+#define ARM_STR_I(rt, rn, off)	(ARM_INST_STR_I | (rt) << 12 | (rn) << 16 \
+				 | (off))
+
+#define ARM_TST_R(rn, rm)	_AL3_R(ARM_INST_TST, 0, rn, rm)
+#define ARM_TST_I(rn, imm)	_AL3_I(ARM_INST_TST, 0, rn, imm)
+
+#define ARM_UDIV(rd, rn, rm)	(ARM_INST_UDIV | (rd) << 16 | (rn) | (rm) << 8)
+
+#define ARM_UMULL(rd_lo, rd_hi, rn, rm)	(ARM_INST_UMULL | (rd_hi) << 16 \
+					 | (rd_lo) << 12 | (rm) << 8 | rn)
+
+#endif /* PFILTER_OPCODES_ARM_H */
-- 
1.7.9.1



From aisheng.dong at freescale.com  Fri Mar 16 04:22:44 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Fri, 16 Mar 2012 16:22:44 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20322.61501.432329.124466@ipc1.ka-ro>
References: <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
 <20120316030134.GA5161@shlinux2.ap.freescale.net>
 <20322.61501.432329.124466@ipc1.ka-ro>
Message-ID: <20120316082243.GA13065@shlinux2.ap.freescale.net>

On Fri, Mar 16, 2012 at 03:48:13PM +0800, Lothar Wa?mann wrote:
> Hi,
> 
> Dong Aisheng writes:
> > On Thu, Mar 15, 2012 at 07:22:04PM +0800, Lothar Wa?mann wrote:
> [...]
> > My proposal is only set the fixed part(first two octets) in board dts file,
> > each board knows it's value, and read the left 4 octets from OCOTP dynamically.
> >
> The OUI part is three bytes, not two! But anyway, since there is no
> definition on how the MAC has to be stored in OCOTP there is no way
> for the driver to know how to interpret the data it may read from
> there.
> 
I may miss this, i will double check it.
Thanks for the info. :-)

> > > Anyway there is no definite spec how the MAC address(es) are stored
> > > in the fuse map. Thus reading the MAC from there is more or less
> > > platform specific.
> > > 
> > It's just provide one more option since there are customers storing the MAC
> > in the fuse map.
> > 
> How would the driver know, whether and how the customer has stored the
> MAC address in OCOTP? E.g. on our TX28 modules the FULL MAC is stored
> in the CUSTOM registers in OCOTP.
> 
> > > Currently I'm setting up the MAC address for our TX28 from the fuses
> > > in the platform code passed via platform_data, but that will obviously
> > > not work with DT.
> > > 
> > Non-dt can also use my proposal, then you only need to pass the fixed part of
> > MAC via platfrom data, the left will be read by fec driver.
> > 
> Reading the MAC from fuses is platform sepcific. The driver cannot
> know how the MAC is stored there and needs to rely on platform
> specific code to do this.
> 
> > > The correct way would probably be to pass the MAC from the bootloader
> > > via a DT blob. But that would require all bootloaders to be updated
> > > first to support DTS. :(
> > > 
> > But uboot will face the same problem that can not define a valid MAC
> > in dts, did i undertand correctly?
> > 
> That's why I said "would require all bootloaders to be updated first
> to support DTS".

Regards
Dong Aisheng



From thierry.reding at avionic-design.de  Fri Mar 16 04:21:31 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 16 Mar 2012 09:21:31 +0100
Subject: [PATCH v4 06/10] pwm: Add NVIDIA Tegra SoC support
In-Reply-To: <20120316080025.GD7758@S2101-09.ap.freescale.net>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-7-git-send-email-thierry.reding@avionic-design.de>
 <20120316080025.GD7758@S2101-09.ap.freescale.net>
Message-ID: <20120316082131.GB6458@avionic-0098.mockup.avionic-design.de>

* Shawn Guo wrote:
> On Wed, Mar 14, 2012 at 04:56:29PM +0100, Thierry Reding wrote:
> > This commit adds a generic PWM framework driver for the PWFM controller
> > found on NVIDIA Tegra SoCs. The driver is based on code from the
> > Chromium kernel tree and was originally written by Gary King (NVIDIA)
> > and later modified by Simon Que (Chromium).
> > 
> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> > ---
> > Changes in v4:
> >   - merge patch from ChromiumOS kernel to fix a rounding issue
> >   - move DT code to patch 7
> > 
> > Changes in v3:
> >   - use pwm_device.hwpwm instead of recomputing it
> >   - update pwm_ops for changes in patch 2
> > 
> > Changes in v2:
> >   - set pwm_chip.dev field
> >   - rename clk_enb to enable
> >   - introduce NUM_PWM macro instead of hard-coding the number of PWM
> >     devices
> >   - update comment in tegra_pwm_config
> >   - fix coding-style for multi-line comments
> >   - use module_platform_driver
> >   - change license to GPL
> > 
> >  drivers/pwm/Kconfig     |   10 ++
> >  drivers/pwm/Makefile    |    1 +
> >  drivers/pwm/pwm-tegra.c |  256 +++++++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 267 insertions(+)
> >  create mode 100644 drivers/pwm/pwm-tegra.c
> > 
> > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> > index 93c1052..bda6f23 100644
> > --- a/drivers/pwm/Kconfig
> > +++ b/drivers/pwm/Kconfig
> > @@ -9,4 +9,14 @@ menuconfig PWM
> >  
> >  if PWM
> >  
> > +config PWM_TEGRA
> > +	tristate "NVIDIA Tegra PWM support"
> > +	depends on ARCH_TEGRA
> > +	help
> > +	  Generic PWM framework driver for the PWFM controller found on NVIDIA
> > +	  Tegra SoCs.
> > +
> > +	  To compile this driver as a module, choose M here: the module
> > +	  will be called pwm-tegra.
> > +
> >  endif
> > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> > index 3469c3d..12300f5 100644
> > --- a/drivers/pwm/Makefile
> > +++ b/drivers/pwm/Makefile
> > @@ -1 +1,2 @@
> >  obj-$(CONFIG_PWM)		+= core.o
> > +obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
> > diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> > new file mode 100644
> > index 0000000..19540fc
> > --- /dev/null
> > +++ b/drivers/pwm/pwm-tegra.c
> > @@ -0,0 +1,256 @@
> > +/*
> > + * drivers/pwm/pwm-tegra.c
> > + *
> > + * Tegra pulse-width-modulation controller driver
> > + *
> > + * Copyright (c) 2010, NVIDIA Corporation.
> > + * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer at pengutronix.de>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful, but WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along
> > + * with this program; if not, write to the Free Software Foundation, Inc.,
> > + * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/pwm.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#define PWM_ENABLE	(1 << 31)
> > +#define PWM_DUTY_WIDTH	8
> > +#define PWM_DUTY_SHIFT	16
> > +#define PWM_SCALE_WIDTH	13
> > +#define PWM_SCALE_SHIFT	0
> > +
> > +#define NUM_PWM 4
> > +
> > +struct tegra_pwm_chip {
> > +	struct pwm_chip		chip;
> > +	struct device		*dev;
> > +
> > +	struct clk		*clk;
> > +
> > +	int			enable[NUM_PWM];
> > +	void __iomem		*mmio_base;
> > +};
> > +
> > +static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
> > +{
> > +	return container_of(chip, struct tegra_pwm_chip, chip);
> > +}
> > +
> > +static inline int pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
> > +		unsigned long val)
> > +{
> > +	unsigned long offset = num << 4;
> > +	int rc;
> > +
> > +	rc = clk_enable(chip->clk);
> > +	if (WARN_ON(rc))
> > +		return rc;
> > +
> > +	writel(val, chip->mmio_base + offset);
> > +	clk_disable(chip->clk);
> > +
> > +	return 0;
> > +}
> > +
> > +static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> > +		int duty_ns, int period_ns)
> > +{
> > +	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
> > +	unsigned long long c;
> > +	unsigned long rate, hz;
> > +	u32 val = 0;
> > +
> 
> Every pwm driver I have been looking at has some validation on
> parameters here, something like:
> 
> 	if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
> 		return -EINVAL;
> 
> It's not needed for tegra, or the check on those platforms is
> unnecessary?

Yes, I should add similar checks for the Tegra driver. On the other hand
maybe the checks should be pushed into the core. At least those checks that
are truly general sanity checks. Off the top of my head, I can think of the
following general preconditions:

	pwm != NULL
	period_ns > 0
	duty_ns >= 0
	duty_ns <= period_ns

Of course duty_ns >= 0 could be done away with by just making the duty_ns and
period_ns parameters unsigned. But such changes were actually supposed to be
added incrementally once the framework had been merged.

> > +	r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
> > +			pdev->name);
> > +	if (!r) {
> > +		dev_err(&pdev->dev, "failed to request memory\n");
> > +		return -EBUSY;
> > +	}
> > +
> > +	pwm->mmio_base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
> > +	if (!pwm->mmio_base) {
> > +		dev_err(&pdev->dev, "failed to ioremap() region\n");
> > +		return -ENODEV;
> > +	}
> > +
> 
> The helper devm_request_and_ioremap() can help here?

Yes, absolutely.

> > +static struct platform_driver tegra_pwm_driver = {
> > +	.driver = {
> > +		.name = "tegra-pwm",
> > +	},
> > +	.probe = tegra_pwm_probe,
> > +	.remove = __devexit_p(tegra_pwm_remove),
> > +};
> > +
> I would remove this blank line.
> 
> > +module_platform_driver(tegra_pwm_driver);

I don't know; I think it makes the code cluttered.

Thierry
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From arnd at arndb.de  Fri Mar 16 04:24:05 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 08:24:05 +0000
Subject: [PATCH v10] mfd: Add anatop mfd driver
In-Reply-To: <1331885816-26902-1-git-send-email-paul.liu@linaro.org>
References: <1331885816-26902-1-git-send-email-paul.liu@linaro.org>
Message-ID: <201203160824.05384.arnd@arndb.de>

On Friday 16 March 2012, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
> Anatop provides regulators and thermal.
> This driver handles the address space and the operation of the mfd device.
> 
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Acked-by: Shawn Guo <shawn.guo at linaro.org>

Reviewed-by: Arnd Bergmann <arnd at arndb.de>


From linus.walleij at linaro.org  Fri Mar 16 04:25:12 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 16 Mar 2012 09:25:12 +0100
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <1331878280-2758-2-git-send-email-mturquette@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-2-git-send-email-mturquette@linaro.org>
Message-ID: <CACRpkdbXq7zX_XrvAOJc7U6=T0Aaoq+U9_GmZS4fVmVd_arC7A@mail.gmail.com>

On Fri, Mar 16, 2012 at 7:11 AM, Mike Turquette <mturquette at linaro.org> wrote:

> Provide documentation for the common clk structures and APIs. ?This code
> can be found in drivers/clk/ and include/linux/clk*.h.

Acked-by: Linus Wallej <linus.walleij at linaro.org>
For this three-piece v7 patchset.

It already does magnitudes more advanced stuff than what I need
so I'm pretty pleased, any remaining details can surely be ironed out
in-tree.

Thanks,
Linus Walleij


From arnd at arndb.de  Fri Mar 16 04:26:36 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 08:26:36 +0000
Subject: linux-next: manual merge of the arm-soc tree with the s5p tree
In-Reply-To: <20120316174546.5121be30a86c2937579bd3f5@canb.auug.org.au>
References: <20120316174546.5121be30a86c2937579bd3f5@canb.auug.org.au>
Message-ID: <201203160826.36287.arnd@arndb.de>

On Friday 16 March 2012, Stephen Rothwell wrote:
> Today's linux-next merge of the arm-soc tree got a conflict in
> arch/arm/mach-exynos/common.c between commit 1d7233ac478a ("Merge branch
> 'next/soc-exynos5250-arch-gpio' into for-next") from the s5p tree and
> commit 853a0231e057 ("Merge branch 'samsung/soc' into next/soc2") from
> the arm-soc tree.
> 
> These merge commits both looks suspect, but I fixed it up as best I could
> (see below).

Right, both the arm-soc and the s5p tree merge the same commits and
come to different results. Kgene, please have a look and let me know
which of the three solutions is correct.

	Arnd

> Cheers,
> Stephen Rothwell                    sfr at canb.auug.org.au
> 
> diff --cc arch/arm/mach-exynos/common.c
> index 4e1d0b7,e6cc50e..0000000
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@@ -593,6 -586,14 +593,13 @@@ static int __init exynos4_l2x0_cache_in
>         if (soc_is_exynos5250())
>                 return 0;
>   
>  -      int ret;
> +       ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
> +       if (!ret) {
> +               l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
> +               clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
> +               return 0;
> +       }
> + 
>         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
>                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
>                 /* TAG, Data Latency Control: 2 cycles */



From thierry.reding at avionic-design.de  Fri Mar 16 04:29:34 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 16 Mar 2012 09:29:34 +0100
Subject: [PATCH v4 09/10] pwm: Add PXA support
In-Reply-To: <20120316081222.GE7758@S2101-09.ap.freescale.net>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-10-git-send-email-thierry.reding@avionic-design.de>
 <20120316081222.GE7758@S2101-09.ap.freescale.net>
Message-ID: <20120316082934.GC6458@avionic-0098.mockup.avionic-design.de>

* Shawn Guo wrote:
> On Wed, Mar 14, 2012 at 04:56:32PM +0100, Thierry Reding wrote:
> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> > ---
> > Changes in v3:
> >   - update PWM ops for changes in patch 2
> > 
> >  arch/arm/plat-pxa/Makefile |    1 -
> >  arch/arm/plat-pxa/pwm.c    |  304 --------------------------------------------
> >  drivers/pwm/Kconfig        |    9 ++
> >  drivers/pwm/Makefile       |    1 +
> >  drivers/pwm/pwm-pxa.c      |  244 +++++++++++++++++++++++++++++++++++
> >  5 files changed, 254 insertions(+), 305 deletions(-)
> >  delete mode 100644 arch/arm/plat-pxa/pwm.c
> >  create mode 100644 drivers/pwm/pwm-pxa.c
> > 
> The patch should be generated with "git format-patch -M", so that we
> can see the diff like below. 
> 
> --- a/arch/arm/plat-pxa/pwm.c
> +++ b/drivers/pwm/pwm-pxa.c

Yes, Arnd already mentioned that in the last round but I forgot. It usually
takes me a couple of weeks to prepare the next version and I try to keep a
list of TODOs but that doesn't seem to be efficient enough yet.

> -int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
> +static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
> +                         int duty_ns, int period_ns)
>  {
> +       struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
>         unsigned long long c;
>         unsigned long period_cycles, prescale, pv, dc;
> +       unsigned long offset;
> 
> -       if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
> +       if (period_ns == 0 || duty_ns > period_ns)
>                 return -EINVAL;
> 
> Then I will have a question why "pwm == NULL" check is removed?

Actually, as I mentioned in another mail the idea was to put these kinds of
checks into the core. They are still missing from the core, though.

Thierry
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From nicolas.ferre at atmel.com  Fri Mar 16 04:30:17 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 16 Mar 2012 09:30:17 +0100
Subject: [PATCH] Fixes after disintegration of asm/system.h for ARM
In-Reply-To: <20120315212619.31098.94700.stgit@warthog.procyon.org.uk>
References: <20120315212619.31098.94700.stgit@warthog.procyon.org.uk>
Message-ID: <4F62FA19.3030907@atmel.com>

On 03/15/2012 10:26 PM, David Howells :
> Signed-off-by: David Howells <dhowells at redhat.com>
> cc: Russell King <linux at arm.linux.org.uk>
> cc: linux-arm-kernel at lists.infradead.org
> ---
> 
>  arch/arm/include/asm/barrier.h               |    6 ++++++
>  arch/arm/include/asm/domain.h                |    2 ++
>  arch/arm/include/asm/io.h                    |    1 +
>  arch/arm/include/asm/processor.h             |    1 -
>  arch/arm/include/asm/system_misc.h           |    5 -----
>  arch/arm/kernel/kprobes-common.c             |    1 +
>  arch/arm/kernel/machine_kexec.c              |    1 +
>  arch/arm/kernel/tcm.c                        |    1 +
>  arch/arm/kernel/thumbee.c                    |    1 +
>  arch/arm/mach-at91/at91cap9.c                |    2 ++

This file is not existing anymore in 3.4.


>  arch/arm/mach-at91/at91rm9200.c              |    1 +
>  arch/arm/mach-at91/at91sam9260.c             |    1 +
>  arch/arm/mach-at91/at91sam9261.c             |    1 +
>  arch/arm/mach-at91/at91sam9263.c             |    1 +
>  arch/arm/mach-at91/at91sam9g45.c             |    1 +
>  arch/arm/mach-at91/at91sam9rl.c              |    1 +
>  arch/arm/mach-at91/include/mach/system_rev.h |    2 ++
>  arch/arm/mach-clps711x/common.c              |    1 +
>  arch/arm/mach-davinci/board-da850-evm.c      |    1 +
>  arch/arm/mach-ebsa110/core.c                 |    1 +
>  arch/arm/mach-footbridge/common.c            |    1 +
>  arch/arm/mach-footbridge/dc21285-timer.c     |    1 +
>  arch/arm/mach-footbridge/netwinder-hw.c      |    1 +
>  arch/arm/mach-imx/mach-imx6q.c               |    1 +
>  arch/arm/mach-imx/mach-mx51_efikamx.c        |    1 +
>  arch/arm/mach-imx/mach-mx51_efikasb.c        |    1 +
>  arch/arm/mach-ks8695/time.c                  |    1 +
>  arch/arm/mach-mmp/common.c                   |    1 +
>  arch/arm/mach-mmp/pxa168.c                   |    1 +
>  arch/arm/mach-mxs/system.c                   |    1 +
>  arch/arm/mach-omap1/id.c                     |    1 +
>  arch/arm/mach-omap2/board-omap3touchbook.c   |    1 +
>  arch/arm/mach-omap2/board-rx51-peripherals.c |    1 +
>  arch/arm/mach-omap2/pm24xx.c                 |    1 +
>  arch/arm/mach-omap2/pm34xx.c                 |    1 +
>  arch/arm/mach-omap2/pm44xx.c                 |    1 +
>  arch/arm/mach-orion5x/common.c               |    1 +
>  arch/arm/mach-orion5x/dns323-setup.c         |    1 +
>  arch/arm/mach-pnx4008/core.c                 |    1 +
>  arch/arm/mach-pxa/cm-x300.c                  |    1 +
>  arch/arm/mach-pxa/colibri-pxa3xx.c           |    1 +
>  arch/arm/mach-pxa/magician.c                 |    1 +
>  arch/arm/mach-pxa/reset.c                    |    1 +
>  arch/arm/mach-pxa/viper.c                    |    1 +
>  arch/arm/mach-pxa/zeus.c                     |    1 +
>  arch/arm/mach-rpc/riscpc.c                   |    1 +
>  arch/arm/mach-s3c2410/s3c2410.c              |    1 +
>  arch/arm/mach-s3c2412/s3c2412.c              |    1 +
>  arch/arm/mach-s3c2416/s3c2416.c              |    1 +
>  arch/arm/mach-s3c2440/s3c244x.c              |    1 +
>  arch/arm/mach-s3c2443/s3c2443.c              |    1 +
>  arch/arm/mach-s3c64xx/common.c               |    1 +
>  arch/arm/mach-s5p64x0/common.c               |    1 +
>  arch/arm/mach-s5pc100/common.c               |    1 +
>  arch/arm/mach-sa1100/generic.c               |    1 +
>  arch/arm/mach-shmobile/include/mach/system.h |    2 ++
>  arch/arm/mach-shmobile/suspend.c             |    1 +
>  arch/arm/mach-w90x900/cpu.c                  |    1 +
>  arch/arm/mm/alignment.c                      |    1 +
>  arch/arm/mm/fault.c                          |    2 ++
>  arch/arm/mm/mmu.c                            |    1 +
>  arch/arm/plat-iop/restart.c                  |    1 +
>  arch/arm/plat-mxc/system.c                   |    1 +
>  arch/arm/plat-s3c24xx/cpu.c                  |    1 +
>  arch/arm/plat-spear/restart.c                |    1 +
>  arch/arm/vfp/vfpmodule.c                     |    1 +
>  drivers/cpuidle/cpuidle.c                    |    1 +
>  drivers/net/ethernet/8390/etherh.c           |    1 +
>  drivers/tty/serial/21285.c                   |    1 +
>  drivers/watchdog/wdt285.c                    |    1 +
>  include/linux/mtd/map.h                      |    2 +-
>  71 files changed, 79 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
> index 81b24b6..408e392 100644
> --- a/arch/arm/include/asm/barrier.h
> +++ b/arch/arm/include/asm/barrier.h
> @@ -1,6 +1,11 @@
>  #ifndef __ASM_BARRIER_H
>  #define __ASM_BARRIER_H
>  
> +#ifdef __ASSEMBLY__
> +#error do not include asm/barrier.h from assembly
> +#endif
> +
> +#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
>  
>  #if __LINUX_ARM_ARCH__ >= 7 ||		\
>  	(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
> @@ -36,6 +41,7 @@
>  #ifdef CONFIG_ARCH_HAS_BARRIERS
>  #include <mach/barriers.h>
>  #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
> +#include <asm/outercache.h>
>  #define mb()		do { dsb(); outer_sync(); } while (0)
>  #define rmb()		dsb()
>  #define wmb()		mb()
> diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
> index 489f160..3d22204 100644
> --- a/arch/arm/include/asm/domain.h
> +++ b/arch/arm/include/asm/domain.h
> @@ -10,7 +10,9 @@
>  #ifndef __ASM_PROC_DOMAIN_H
>  #define __ASM_PROC_DOMAIN_H
>  
> +#ifndef __ASSEMBLY__
>  #include <asm/barrier.h>
> +#endif
>  
>  /*
>   * Domain numbers
> diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
> index 0a34bf7..bae7eb6 100644
> --- a/arch/arm/include/asm/io.h
> +++ b/arch/arm/include/asm/io.h
> @@ -98,6 +98,7 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
>  
>  /* IO barriers */
>  #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
> +#include <asm/barrier.h>
>  #define __iormb()		rmb()
>  #define __iowmb()		wmb()
>  #else
> diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
> index cb8d638..ce280b8 100644
> --- a/arch/arm/include/asm/processor.h
> +++ b/arch/arm/include/asm/processor.h
> @@ -22,7 +22,6 @@
>  #include <asm/hw_breakpoint.h>
>  #include <asm/ptrace.h>
>  #include <asm/types.h>
> -#include <asm/system.h>
>  
>  #ifdef __KERNEL__
>  #define STACK_TOP	((current->personality & ADDR_LIMIT_32BIT) ? \
> diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
> index f5cf1e8..ccda6c2 100644
> --- a/arch/arm/include/asm/system_misc.h
> +++ b/arch/arm/include/asm/system_misc.h
> @@ -7,9 +7,6 @@
>  #include <linux/linkage.h>
>  #include <linux/irqflags.h>
>  
> -#include <asm/outercache.h>
> -
> -extern int __pure cpu_architecture(void);
>  extern void cpu_init(void);
>  
>  void soft_restart(unsigned long);
> @@ -23,8 +20,6 @@ extern void (*arm_pm_restart)(char str, const char *cmd);
>  
>  extern unsigned int user_debug;
>  
> -#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
> -
>  extern void disable_hlt(void);
>  extern void enable_hlt(void);
>  
> diff --git a/arch/arm/kernel/kprobes-common.c b/arch/arm/kernel/kprobes-common.c
> index a5394fb4..18a7628 100644
> --- a/arch/arm/kernel/kprobes-common.c
> +++ b/arch/arm/kernel/kprobes-common.c
> @@ -13,6 +13,7 @@
>  
>  #include <linux/kernel.h>
>  #include <linux/kprobes.h>
> +#include <asm/system_info.h>
>  
>  #include "kprobes.h"
>  
> diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
> index e097865..5699598 100644
> --- a/arch/arm/kernel/machine_kexec.c
> +++ b/arch/arm/kernel/machine_kexec.c
> @@ -12,6 +12,7 @@
>  #include <asm/mmu_context.h>
>  #include <asm/cacheflush.h>
>  #include <asm/mach-types.h>
> +#include <asm/system_misc.h>
>  
>  extern const unsigned char relocate_new_kernel[];
>  extern const unsigned int relocate_new_kernel_size;
> diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
> index 01ec453..30ae6bb 100644
> --- a/arch/arm/kernel/tcm.c
> +++ b/arch/arm/kernel/tcm.c
> @@ -16,6 +16,7 @@
>  #include <asm/cputype.h>
>  #include <asm/mach/map.h>
>  #include <asm/memory.h>
> +#include <asm/system_info.h>
>  #include "tcm.h"
>  
>  static struct gen_pool *tcm_pool;
> diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c
> index 9cb7aac..37bc322 100644
> --- a/arch/arm/kernel/thumbee.c
> +++ b/arch/arm/kernel/thumbee.c
> @@ -21,6 +21,7 @@
>  #include <linux/init.h>
>  
>  #include <asm/thread_notify.h>
> +#include <asm/system_info.h>
>  
>  /*
>   * Access to the ThumbEE Handler Base register
> diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
> index a42edc2..fc460e9 100644
> --- a/arch/arm/mach-at91/at91cap9.c
> +++ b/arch/arm/mach-at91/at91cap9.c
> @@ -17,6 +17,8 @@
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> +#include <asm/system_info.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/cpu.h>
>  #include <mach/at91cap9.h>
> diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
> index 99c3174..413c027 100644
> --- a/arch/arm/mach-at91/at91rm9200.c
> +++ b/arch/arm/mach-at91/at91rm9200.c
> @@ -15,6 +15,7 @@
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> +#include <asm/system_misc.h>
>  #include <mach/at91rm9200.h>
>  #include <mach/at91_pmc.h>
>  #include <mach/at91_st.h>
> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
> index d4036ba..79f5718 100644
> --- a/arch/arm/mach-at91/at91sam9260.c
> +++ b/arch/arm/mach-at91/at91sam9260.c
> @@ -15,6 +15,7 @@
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> +#include <asm/system_misc.h>
>  #include <mach/cpu.h>
>  #include <mach/at91_dbgu.h>
>  #include <mach/at91sam9260.h>
> diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
> index 023c2ff..62818b9 100644
> --- a/arch/arm/mach-at91/at91sam9261.c
> +++ b/arch/arm/mach-at91/at91sam9261.c
> @@ -15,6 +15,7 @@
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> +#include <asm/system_misc.h>
>  #include <mach/cpu.h>
>  #include <mach/at91sam9261.h>
>  #include <mach/at91_pmc.h>
> diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
> index 75e876c..722ee08 100644
> --- a/arch/arm/mach-at91/at91sam9263.c
> +++ b/arch/arm/mach-at91/at91sam9263.c
> @@ -15,6 +15,7 @@
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> +#include <asm/system_misc.h>
>  #include <mach/at91sam9263.h>
>  #include <mach/at91_pmc.h>
>  #include <mach/at91_rstc.h>
> diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
> index 1cb6a96..47e8fdb 100644
> --- a/arch/arm/mach-at91/at91sam9g45.c
> +++ b/arch/arm/mach-at91/at91sam9g45.c
> @@ -16,6 +16,7 @@
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> +#include <asm/system_misc.h>
>  #include <mach/at91sam9g45.h>
>  #include <mach/at91_pmc.h>
>  #include <mach/cpu.h>
> diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
> index d2c91a8..7ae4993 100644
> --- a/arch/arm/mach-at91/at91sam9rl.c
> +++ b/arch/arm/mach-at91/at91sam9rl.c
> @@ -14,6 +14,7 @@
>  #include <asm/irq.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> +#include <asm/system_misc.h>
>  #include <mach/cpu.h>
>  #include <mach/at91_dbgu.h>
>  #include <mach/at91sam9rl.h>
> diff --git a/arch/arm/mach-at91/include/mach/system_rev.h b/arch/arm/mach-at91/include/mach/system_rev.h
> index ec164a4..ef79a9a 100644
> --- a/arch/arm/mach-at91/include/mach/system_rev.h
> +++ b/arch/arm/mach-at91/include/mach/system_rev.h
> @@ -7,6 +7,8 @@
>  #ifndef __ARCH_SYSTEM_REV_H__
>  #define __ARCH_SYSTEM_REV_H__
>  
> +#include <asm/system_info.h>
> +
>  /*
>   * board revision encoding
>   * mach specific
> diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
> index ab1711b..ac84f92 100644
> --- a/arch/arm/mach-clps711x/common.c
> +++ b/arch/arm/mach-clps711x/common.c
> @@ -37,6 +37,7 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/time.h>
>  #include <asm/hardware/clps7111.h>
> +#include <asm/system_misc.h>
>  
>  /*
>   * This maps the generic CLPS711x registers
> diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
> index d508890..5d9afd8 100644
> --- a/arch/arm/mach-davinci/board-da850-evm.c
> +++ b/arch/arm/mach-davinci/board-da850-evm.c
> @@ -34,6 +34,7 @@
>  #include <linux/delay.h>
>  #include <linux/wl12xx.h>
>  
> +#include <asm/system_info.h>
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  
> diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
> index e43dcc0..0c40e59 100644
> --- a/arch/arm/mach-ebsa110/core.c
> +++ b/arch/arm/mach-ebsa110/core.c
> @@ -22,6 +22,7 @@
>  #include <asm/mach-types.h>
>  #include <asm/pgtable.h>
>  #include <asm/page.h>
> +#include <asm/system_misc.h>
>  
>  #include <asm/mach/arch.h>
>  #include <asm/mach/irq.h>
> diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
> index 41978ee..3e6aaa6 100644
> --- a/arch/arm/mach-footbridge/common.c
> +++ b/arch/arm/mach-footbridge/common.c
> @@ -21,6 +21,7 @@
>  #include <asm/irq.h>
>  #include <asm/mach-types.h>
>  #include <asm/setup.h>
> +#include <asm/system_misc.h>
>  #include <asm/hardware/dec21285.h>
>  
>  #include <asm/mach/irq.h>
> diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
> index 121ad1d..3b54196 100644
> --- a/arch/arm/mach-footbridge/dc21285-timer.c
> +++ b/arch/arm/mach-footbridge/dc21285-timer.c
> @@ -14,6 +14,7 @@
>  
>  #include <asm/hardware/dec21285.h>
>  #include <asm/mach/time.h>
> +#include <asm/system_info.h>
>  
>  #include "common.h"
>  
> diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
> index 80a1c5c..cac9f67 100644
> --- a/arch/arm/mach-footbridge/netwinder-hw.c
> +++ b/arch/arm/mach-footbridge/netwinder-hw.c
> @@ -17,6 +17,7 @@
>  #include <asm/leds.h>
>  #include <asm/mach-types.h>
>  #include <asm/setup.h>
> +#include <asm/system_misc.h>
>  
>  #include <asm/mach/arch.h>
>  
> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
> index c257281..527b697 100644
> --- a/arch/arm/mach-imx/mach-imx6q.c
> +++ b/arch/arm/mach-imx/mach-imx6q.c
> @@ -21,6 +21,7 @@
>  #include <linux/of_platform.h>
>  #include <linux/phy.h>
>  #include <linux/micrel_phy.h>
> +#include <asm/system_misc.h>
>  #include <asm/hardware/cache-l2x0.h>
>  #include <asm/hardware/gic.h>
>  #include <asm/mach/arch.h>
> diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
> index 3a5ed2d..586e9f8 100644
> --- a/arch/arm/mach-imx/mach-mx51_efikamx.c
> +++ b/arch/arm/mach-imx/mach-mx51_efikamx.c
> @@ -33,6 +33,7 @@
>  #include <mach/iomux-mx51.h>
>  
>  #include <asm/setup.h>
> +#include <asm/system_info.h>
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/time.h>
> diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
> index ea5f65b..24aded9 100644
> --- a/arch/arm/mach-imx/mach-mx51_efikasb.c
> +++ b/arch/arm/mach-imx/mach-mx51_efikasb.c
> @@ -36,6 +36,7 @@
>  #include <mach/iomux-mx51.h>
>  
>  #include <asm/setup.h>
> +#include <asm/system_info.h>
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/time.h>
> diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
> index 37dfcd5..ec783a3 100644
> --- a/arch/arm/mach-ks8695/time.c
> +++ b/arch/arm/mach-ks8695/time.c
> @@ -27,6 +27,7 @@
>  #include <linux/io.h>
>  
>  #include <asm/mach/time.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/regs-timer.h>
>  #include <mach/regs-irq.h>
> diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
> index 062b5b9..c868a6c 100644
> --- a/arch/arm/mach-mmp/common.c
> +++ b/arch/arm/mach-mmp/common.c
> @@ -13,6 +13,7 @@
>  #include <linux/module.h>
>  
>  #include <asm/page.h>
> +#include <asm/system_misc.h>
>  #include <asm/mach/map.h>
>  #include <mach/addr-map.h>
>  #include <mach/cputype.h>
> diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
> index ada1213..d5c9a2e 100644
> --- a/arch/arm/mach-mmp/pxa168.c
> +++ b/arch/arm/mach-mmp/pxa168.c
> @@ -15,6 +15,7 @@
>  #include <linux/clk.h>
>  #include <linux/platform_device.h>
>  
> +#include <asm/system_misc.h>
>  #include <asm/mach/time.h>
>  #include <mach/addr-map.h>
>  #include <mach/cputype.h>
> diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
> index 32fe638..30042e2 100644
> --- a/arch/arm/mach-mxs/system.c
> +++ b/arch/arm/mach-mxs/system.c
> @@ -25,6 +25,7 @@
>  #include <linux/module.h>
>  
>  #include <asm/proc-fns.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/mxs.h>
>  #include <mach/common.h>
> diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
> index a0e3560..b3f3363 100644
> --- a/arch/arm/mach-omap1/id.c
> +++ b/arch/arm/mach-omap1/id.c
> @@ -15,6 +15,7 @@
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/io.h>
> +#include <asm/system_info.h>
>  #include <plat/cpu.h>
>  
>  #define OMAP_DIE_ID_0		0xfffe1800
> diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
> index a0b851a..c524c9d 100644
> --- a/arch/arm/mach-omap2/board-omap3touchbook.c
> +++ b/arch/arm/mach-omap2/board-omap3touchbook.c
> @@ -38,6 +38,7 @@
>  #include <linux/i2c/twl.h>
>  
>  #include <mach/hardware.h>
> +#include <asm/system_info.h>
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
> index acb4e77..2bf84fd 100644
> --- a/arch/arm/mach-omap2/board-rx51-peripherals.c
> +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
> @@ -25,6 +25,7 @@
>  #include <linux/gpio_keys.h>
>  #include <linux/mmc/host.h>
>  #include <linux/power/isp1704_charger.h>
> +#include <asm/system_info.h>
>  
>  #include <plat/mcspi.h>
>  #include <plat/board.h>
> diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
> index 23de98d..730bb00 100644
> --- a/arch/arm/mach-omap2/pm24xx.c
> +++ b/arch/arm/mach-omap2/pm24xx.c
> @@ -34,6 +34,7 @@
>  #include <asm/mach/time.h>
>  #include <asm/mach/irq.h>
>  #include <asm/mach-types.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/irqs.h>
>  #include <plat/clock.h>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index fc69875..64d95e6 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -31,6 +31,7 @@
>  #include <trace/events/power.h>
>  
>  #include <asm/suspend.h>
> +#include <asm/system_misc.h>
>  
>  #include <plat/sram.h>
>  #include "clockdomain.h"
> diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
> index c264ef7..a73e325 100644
> --- a/arch/arm/mach-omap2/pm44xx.c
> +++ b/arch/arm/mach-omap2/pm44xx.c
> @@ -16,6 +16,7 @@
>  #include <linux/list.h>
>  #include <linux/err.h>
>  #include <linux/slab.h>
> +#include <asm/system_misc.h>
>  
>  #include "common.h"
>  #include "clockdomain.h"
> diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
> index 5dad38e..2448166 100644
> --- a/arch/arm/mach-orion5x/common.c
> +++ b/arch/arm/mach-orion5x/common.c
> @@ -21,6 +21,7 @@
>  #include <net/dsa.h>
>  #include <asm/page.h>
>  #include <asm/setup.h>
> +#include <asm/system_misc.h>
>  #include <asm/timex.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
> index 91b0f47..f4f6ad2d 100644
> --- a/arch/arm/mach-orion5x/dns323-setup.c
> +++ b/arch/arm/mach-orion5x/dns323-setup.c
> @@ -29,6 +29,7 @@
>  #include <linux/ata_platform.h>
>  #include <linux/phy.h>
>  #include <linux/marvell_phy.h>
> +#include <asm/system_info.h>
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/pci.h>
> diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
> index 977538f..be4c928 100644
> --- a/arch/arm/mach-pnx4008/core.c
> +++ b/arch/arm/mach-pnx4008/core.c
> @@ -32,6 +32,7 @@
>  #include <asm/mach-types.h>
>  #include <asm/pgtable.h>
>  #include <asm/page.h>
> +#include <asm/system_misc.h>
>  
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
> index 4b981b8..125ae08 100644
> --- a/arch/arm/mach-pxa/cm-x300.c
> +++ b/arch/arm/mach-pxa/cm-x300.c
> @@ -55,6 +55,7 @@
>  #include <mach/pxa3xx-u2d.h>
>  
>  #include <asm/mach/map.h>
> +#include <asm/system_info.h>
>  
>  #include "generic.h"
>  #include "devices.h"
> diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
> index 2b8ca0d..2075a69 100644
> --- a/arch/arm/mach-pxa/colibri-pxa3xx.c
> +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
> @@ -20,6 +20,7 @@
>  #include <asm/sizes.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/irq.h>
> +#include <asm/system_info.h>
>  #include <mach/pxa3xx-regs.h>
>  #include <mach/mfp-pxa300.h>
>  #include <mach/colibri.h>
> diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
> index 3d6baf9..264cd89 100644
> --- a/arch/arm/mach-pxa/magician.c
> +++ b/arch/arm/mach-pxa/magician.c
> @@ -31,6 +31,7 @@
>  #include <linux/i2c/pxa-i2c.h>
>  
>  #include <mach/hardware.h>
> +#include <asm/system_info.h>
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  
> diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
> index c8497b0..b452889 100644
> --- a/arch/arm/mach-pxa/reset.c
> +++ b/arch/arm/mach-pxa/reset.c
> @@ -9,6 +9,7 @@
>  #include <linux/gpio.h>
>  #include <linux/io.h>
>  #include <asm/proc-fns.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/regs-ost.h>
>  #include <mach/reset.h>
> diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
> index 023d6ca..7a3d342 100644
> --- a/arch/arm/mach-pxa/viper.c
> +++ b/arch/arm/mach-pxa/viper.c
> @@ -57,6 +57,7 @@
>  #include <asm/mach-types.h>
>  #include <asm/irq.h>
>  #include <asm/sizes.h>
> +#include <asm/system_info.h>
>  
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
> index a4dd1c3..4c5ae58 100644
> --- a/arch/arm/mach-pxa/zeus.c
> +++ b/arch/arm/mach-pxa/zeus.c
> @@ -34,6 +34,7 @@
>  #include <asm/suspend.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> +#include <asm/system_info.h>
>  
>  #include <mach/pxa27x.h>
>  #include <mach/regs-uart.h>
> diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
> index 3d44a59..e958597 100644
> --- a/arch/arm/mach-rpc/riscpc.c
> +++ b/arch/arm/mach-rpc/riscpc.c
> @@ -28,6 +28,7 @@
>  #include <asm/page.h>
>  #include <asm/domain.h>
>  #include <asm/setup.h>
> +#include <asm/system_misc.h>
>  
>  #include <asm/mach/map.h>
>  #include <asm/mach/arch.h>
> diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
> index 061b6bb..a3c5cb0 100644
> --- a/arch/arm/mach-s3c2410/s3c2410.c
> +++ b/arch/arm/mach-s3c2410/s3c2410.c
> @@ -30,6 +30,7 @@
>  
>  #include <mach/hardware.h>
>  #include <asm/irq.h>
> +#include <asm/system_misc.h>
>  
>  #include <plat/cpu-freq.h>
>  
> diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
> index aff6e85..100ef1c 100644
> --- a/arch/arm/mach-s3c2412/s3c2412.c
> +++ b/arch/arm/mach-s3c2412/s3c2412.c
> @@ -31,6 +31,7 @@
>  #include <mach/hardware.h>
>  #include <asm/proc-fns.h>
>  #include <asm/irq.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/idle.h>
>  
> diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
> index 5287d28..ed67ec9 100644
> --- a/arch/arm/mach-s3c2416/s3c2416.c
> +++ b/arch/arm/mach-s3c2416/s3c2416.c
> @@ -43,6 +43,7 @@
>  #include <mach/hardware.h>
>  #include <asm/proc-fns.h>
>  #include <asm/irq.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/idle.h>
>  #include <mach/regs-s3c2443-clock.h>
> diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c
> index d15852f..6f74118 100644
> --- a/arch/arm/mach-s3c2440/s3c244x.c
> +++ b/arch/arm/mach-s3c2440/s3c244x.c
> @@ -23,6 +23,7 @@
>  #include <linux/clk.h>
>  #include <linux/io.h>
>  
> +#include <asm/system_misc.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
> diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
> index b9deaeb..9318847 100644
> --- a/arch/arm/mach-s3c2443/s3c2443.c
> +++ b/arch/arm/mach-s3c2443/s3c2443.c
> @@ -29,6 +29,7 @@
>  
>  #include <mach/hardware.h>
>  #include <asm/irq.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/regs-s3c2443-clock.h>
>  
> diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
> index bee7dcd..b313380 100644
> --- a/arch/arm/mach-s3c64xx/common.c
> +++ b/arch/arm/mach-s3c64xx/common.c
> @@ -29,6 +29,7 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  #include <asm/hardware/vic.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/map.h>
>  #include <mach/hardware.h>
> diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
> index 52b89a3..a9d1ad4 100644
> --- a/arch/arm/mach-s5p64x0/common.c
> +++ b/arch/arm/mach-s5p64x0/common.c
> @@ -30,6 +30,7 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/map.h>
>  #include <mach/hardware.h>
> diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
> index c909573..dff11c3 100644
> --- a/arch/arm/mach-s5pc100/common.c
> +++ b/arch/arm/mach-s5pc100/common.c
> @@ -30,6 +30,7 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/map.h>
>  #include <mach/hardware.h>
> diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
> index 17caece..9ad9469 100644
> --- a/arch/arm/mach-sa1100/generic.c
> +++ b/arch/arm/mach-sa1100/generic.c
> @@ -24,6 +24,7 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/flash.h>
>  #include <asm/irq.h>
> +#include <asm/system_misc.h>
>  
>  #include "generic.h"
>  
> diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
> index 956ac18..9204270 100644
> --- a/arch/arm/mach-shmobile/include/mach/system.h
> +++ b/arch/arm/mach-shmobile/include/mach/system.h
> @@ -1,6 +1,8 @@
>  #ifndef __ASM_ARCH_SYSTEM_H
>  #define __ASM_ARCH_SYSTEM_H
>  
> +#include <asm/system_misc.h>
> +
>  static inline void arch_idle(void)
>  {
>  	cpu_do_idle();
> diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
> index 12d760c..4d1b86a 100644
> --- a/arch/arm/mach-shmobile/suspend.c
> +++ b/arch/arm/mach-shmobile/suspend.c
> @@ -13,6 +13,7 @@
>  #include <linux/module.h>
>  #include <linux/err.h>
>  #include <asm/io.h>
> +#include <asm/system_misc.h>
>  
>  static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
>  {
> diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
> index 9a06619..9e4dd8b 100644
> --- a/arch/arm/mach-w90x900/cpu.c
> +++ b/arch/arm/mach-w90x900/cpu.c
> @@ -28,6 +28,7 @@
>  #include <asm/mach/map.h>
>  #include <asm/mach/irq.h>
>  #include <asm/irq.h>
> +#include <asm/system_misc.h>
>  
>  #include <mach/hardware.h>
>  #include <mach/regs-serial.h>
> diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
> index 9107231..8b05694 100644
> --- a/arch/arm/mm/alignment.c
> +++ b/arch/arm/mm/alignment.c
> @@ -25,6 +25,7 @@
>  #include <asm/cp15.h>
>  #include <asm/system_info.h>
>  #include <asm/unaligned.h>
> +#include <asm/system_info.h>
>  
>  #include "fault.h"
>  
> diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> index 5bdff5c..5a0a0b7 100644
> --- a/arch/arm/mm/fault.c
> +++ b/arch/arm/mm/fault.c
> @@ -25,6 +25,8 @@
>  #include <asm/system_misc.h>
>  #include <asm/system_info.h>
>  #include <asm/tlbflush.h>
> +#include <asm/system_misc.h>
> +#include <asm/system_info.h>
>  
>  #include "fault.h"
>  
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index cd439c1..a27555a 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -28,6 +28,7 @@
>  #include <asm/highmem.h>
>  #include <asm/system_info.h>
>  #include <asm/traps.h>
> +#include <asm/system_info.h>
>  
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
> index 6a85a0c..33fa699 100644
> --- a/arch/arm/plat-iop/restart.c
> +++ b/arch/arm/plat-iop/restart.c
> @@ -8,6 +8,7 @@
>   * published by the Free Software Foundation.
>   */
>  #include <asm/hardware/iop3xx.h>
> +#include <asm/system_misc.h>
>  #include <mach/hardware.h>
>  
>  void iop3xx_restart(char mode, const char *cmd)
> diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
> index 8f12074..c195d6d 100644
> --- a/arch/arm/plat-mxc/system.c
> +++ b/arch/arm/plat-mxc/system.c
> @@ -25,6 +25,7 @@
>  
>  #include <mach/hardware.h>
>  #include <mach/common.h>
> +#include <asm/system_misc.h>
>  #include <asm/proc-fns.h>
>  #include <asm/mach-types.h>
>  
> diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
> index 21f1fda..ded6431 100644
> --- a/arch/arm/plat-s3c24xx/cpu.c
> +++ b/arch/arm/plat-s3c24xx/cpu.c
> @@ -34,6 +34,7 @@
>  #include <mach/hardware.h>
>  #include <asm/irq.h>
>  #include <asm/cacheflush.h>
> +#include <asm/system_info.h>
>  
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
> index 2b4e3d8..16f203e 100644
> --- a/arch/arm/plat-spear/restart.c
> +++ b/arch/arm/plat-spear/restart.c
> @@ -11,6 +11,7 @@
>   * warranty of any kind, whether express or implied.
>   */
>  #include <linux/io.h>
> +#include <asm/system_misc.h>
>  #include <asm/hardware/sp810.h>
>  #include <mach/hardware.h>
>  #include <mach/generic.h>
> diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
> index d89068f..9f50997 100644
> --- a/arch/arm/vfp/vfpmodule.c
> +++ b/arch/arm/vfp/vfpmodule.c
> @@ -22,6 +22,7 @@
>  #include <asm/cputype.h>
>  #include <asm/thread_notify.h>
>  #include <asm/vfp.h>
> +#include <asm/system_info.h>
>  
>  #include "vfpinstr.h"
>  #include "vfp.h"
> diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
> index 59f4261..654076e 100644
> --- a/drivers/cpuidle/cpuidle.c
> +++ b/drivers/cpuidle/cpuidle.c
> @@ -19,6 +19,7 @@
>  #include <linux/hrtimer.h>
>  #include <linux/module.h>
>  #include <trace/events/power.h>
> +#include <asm/system_misc.h>
>  
>  #include "cpuidle.h"
>  
> diff --git a/drivers/net/ethernet/8390/etherh.c b/drivers/net/ethernet/8390/etherh.c
> index 48c4948..a45b0d8 100644
> --- a/drivers/net/ethernet/8390/etherh.c
> +++ b/drivers/net/ethernet/8390/etherh.c
> @@ -48,6 +48,7 @@
>  #include <asm/system.h>
>  #include <asm/ecard.h>
>  #include <asm/io.h>
> +#include <asm/system_info.h>
>  
>  #define EI_SHIFT(x)	(ei_local->reg_offset[x])
>  
> diff --git a/drivers/tty/serial/21285.c b/drivers/tty/serial/21285.c
> index 1b37626..6d0ddbc 100644
> --- a/drivers/tty/serial/21285.c
> +++ b/drivers/tty/serial/21285.c
> @@ -16,6 +16,7 @@
>  
>  #include <asm/irq.h>
>  #include <asm/mach-types.h>
> +#include <asm/system_info.h>
>  #include <asm/hardware/dec21285.h>
>  #include <mach/hardware.h>
>  
> diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c
> index f551356..658a36d 100644
> --- a/drivers/watchdog/wdt285.c
> +++ b/drivers/watchdog/wdt285.c
> @@ -32,6 +32,7 @@
>  #include <mach/hardware.h>
>  
>  #include <asm/mach-types.h>
> +#include <asm/system_info.h>
>  #include <asm/hardware/dec21285.h>
>  
>  /*
> diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h
> index 94e924e..d9072d9 100644
> --- a/include/linux/mtd/map.h
> +++ b/include/linux/mtd/map.h
> @@ -1,4 +1,4 @@
> -/*
> + r/*
>   * Copyright ? 2000-2010 David Woodhouse <dwmw2 at infradead.org> et al.
>   *
>   * This program is free software; you can redistribute it and/or modify
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


-- 
Nicolas Ferre


From arnd at arndb.de  Fri Mar 16 04:31:06 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 08:31:06 +0000
Subject: linux-next: manual merge of the arm-soc tree with the arm tree
In-Reply-To: <20120316174941.40421ba160741a0f6aab6611@canb.auug.org.au>
References: <20120316174941.40421ba160741a0f6aab6611@canb.auug.org.au>
Message-ID: <201203160831.07305.arnd@arndb.de>

On Friday 16 March 2012, Stephen Rothwell wrote:
> Today's linux-next merge of the arm-soc tree got a conflict in
> arch/arm/mach-msm/timer.c between commit f8e56c42e4e3 ("msm: timer:
> Support sched_clock()") from the arm tree and commit 5ca709c16d0f ("ARM:
> local timers: convert MSM to runtime registration interface") from the
> arm-soc tree.

We've had a few conflicts with localtimer patches already and the
solution might be very different and nonobvious. Stephen B, please
check if linux-next still works for you with localtimer enabled.

The fix does look correct to me though.

> I fixed it up (see below) and can carry the fax as necessary.

The fax? I think email will do fine ;-)

Thanks Stephen R,

	Arnd


From nicolas.ferre at atmel.com  Fri Mar 16 04:35:10 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 16 Mar 2012 09:35:10 +0100
Subject: [PATCH] dmaengine: at_hdmac: add slave config operation
In-Reply-To: <1331725303-26298-1-git-send-email-nicolas.ferre@atmel.com>
References: <1331725303-26298-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <4F62FB3E.2000903@atmel.com>

On 03/14/2012 12:41 PM, Nicolas Ferre :
> This patch introduces DMA_SLAVE_CONFIG to at_hdmac Atmel DMA driver.
> 
> It is needed to fix a regression in the use of atmel-mci.c driver on Atmel
> AT91 platforms brouth by e2b35f3:
> "dmaengine/dw_dmac: Fix dw_dmac user drivers to adapt to slave_config changes"

Hi Vinod,

Can we queue this patch for 3.4 quickly as the current linux-next is
broken as far as at91 + sd/mmc is concerned.

I have written it on top of Russell's patch series about cookies
management. Please tell me if it applies nicely on your 3.4 queue...

Thanks a lot, best regards,


> We remove some parts of the private structure "at_dma_slave" and use the
> information provided by "struct dma_slave_config": source/destination
> peripheral registers and access width.
> 
> AT_DMA_SLAVE_WIDTH_* values used previously are not needed anymore as we
> now use the standard ones. Although some conversion functions are needed to
> match register expected values.
> 
> Some AT91 sub-architecture specific files are slightly touched by this patch
> but it cannot be split because it can break compilation.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> ---
>  arch/arm/mach-at91/at91sam9g45_devices.c   |    1 -
>  arch/arm/mach-at91/include/mach/at_hdmac.h |   15 -------
>  drivers/dma/at_hdmac.c                     |   56 +++++++++++++++++++++------
>  drivers/dma/at_hdmac_regs.h                |   32 ++++++++++++++++
>  4 files changed, 75 insertions(+), 29 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
> index 96e2adc..28d3401 100644
> --- a/arch/arm/mach-at91/at91sam9g45_devices.c
> +++ b/arch/arm/mach-at91/at91sam9g45_devices.c
> @@ -432,7 +432,6 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
>  
>  	/* DMA slave channel configuration */
>  	atslave->dma_dev = &at_hdmac_device.dev;
> -	atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
>  	atslave->cfg = ATC_FIFOCFG_HALFFIFO
>  			| ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
>  	atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
> diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h
> index 187cb58..fff48d1 100644
> --- a/arch/arm/mach-at91/include/mach/at_hdmac.h
> +++ b/arch/arm/mach-at91/include/mach/at_hdmac.h
> @@ -24,18 +24,6 @@ struct at_dma_platform_data {
>  };
>  
>  /**
> - * enum at_dma_slave_width - DMA slave register access width.
> - * @AT_DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
> - * @AT_DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
> - * @AT_DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
> - */
> -enum at_dma_slave_width {
> -	AT_DMA_SLAVE_WIDTH_8BIT = 0,
> -	AT_DMA_SLAVE_WIDTH_16BIT,
> -	AT_DMA_SLAVE_WIDTH_32BIT,
> -};
> -
> -/**
>   * struct at_dma_slave - Controller-specific information about a slave
>   * @dma_dev: required DMA master device
>   * @tx_reg: physical address of data register used for
> @@ -48,9 +36,6 @@ enum at_dma_slave_width {
>   */
>  struct at_dma_slave {
>  	struct device		*dma_dev;
> -	dma_addr_t		tx_reg;
> -	dma_addr_t		rx_reg;
> -	enum at_dma_slave_width	reg_width;
>  	u32			cfg;
>  	u32			ctrla;
>  };
> diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
> index 5d225dd..b015a5c 100644
> --- a/drivers/dma/at_hdmac.c
> +++ b/drivers/dma/at_hdmac.c
> @@ -647,6 +647,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
>  {
>  	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
>  	struct at_dma_slave	*atslave = chan->private;
> +	struct dma_slave_config	*sconfig = &atchan->dma_sconfig;
>  	struct at_desc		*first = NULL;
>  	struct at_desc		*prev = NULL;
>  	u32			ctrla;
> @@ -668,19 +669,18 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
>  		return NULL;
>  	}
>  
> -	reg_width = atslave->reg_width;
> -
>  	ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla;
>  	ctrlb = ATC_IEN;
>  
>  	switch (direction) {
>  	case DMA_MEM_TO_DEV:
> +		reg_width = convert_buswidth(sconfig->dst_addr_width);
>  		ctrla |=  ATC_DST_WIDTH(reg_width);
>  		ctrlb |=  ATC_DST_ADDR_MODE_FIXED
>  			| ATC_SRC_ADDR_MODE_INCR
>  			| ATC_FC_MEM2PER
>  			| ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF);
> -		reg = atslave->tx_reg;
> +		reg = sconfig->dst_addr;
>  		for_each_sg(sgl, sg, sg_len, i) {
>  			struct at_desc	*desc;
>  			u32		len;
> @@ -708,13 +708,14 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
>  		}
>  		break;
>  	case DMA_DEV_TO_MEM:
> +		reg_width = convert_buswidth(sconfig->src_addr_width);
>  		ctrla |=  ATC_SRC_WIDTH(reg_width);
>  		ctrlb |=  ATC_DST_ADDR_MODE_INCR
>  			| ATC_SRC_ADDR_MODE_FIXED
>  			| ATC_FC_PER2MEM
>  			| ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF);
>  
> -		reg = atslave->rx_reg;
> +		reg = sconfig->src_addr;
>  		for_each_sg(sgl, sg, sg_len, i) {
>  			struct at_desc	*desc;
>  			u32		len;
> @@ -790,12 +791,15 @@ err_out:
>   * atc_dma_cyclic_fill_desc - Fill one period decriptor
>   */
>  static int
> -atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
> +atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
>  		unsigned int period_index, dma_addr_t buf_addr,
> -		size_t period_len, enum dma_transfer_direction direction)
> +		unsigned int reg_width, size_t period_len,
> +		enum dma_transfer_direction direction)
>  {
> -	u32		ctrla;
> -	unsigned int	reg_width = atslave->reg_width;
> +	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
> +	struct at_dma_slave	*atslave = chan->private;
> +	struct dma_slave_config	*sconfig = &atchan->dma_sconfig;
> +	u32			ctrla;
>  
>  	/* prepare common CRTLA value */
>  	ctrla =   ATC_DEFAULT_CTRLA | atslave->ctrla
> @@ -806,7 +810,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
>  	switch (direction) {
>  	case DMA_MEM_TO_DEV:
>  		desc->lli.saddr = buf_addr + (period_len * period_index);
> -		desc->lli.daddr = atslave->tx_reg;
> +		desc->lli.daddr = sconfig->dst_addr;
>  		desc->lli.ctrla = ctrla;
>  		desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED
>  				| ATC_SRC_ADDR_MODE_INCR
> @@ -816,7 +820,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
>  		break;
>  
>  	case DMA_DEV_TO_MEM:
> -		desc->lli.saddr = atslave->rx_reg;
> +		desc->lli.saddr = sconfig->src_addr;
>  		desc->lli.daddr = buf_addr + (period_len * period_index);
>  		desc->lli.ctrla = ctrla;
>  		desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR
> @@ -847,9 +851,11 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
>  {
>  	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
>  	struct at_dma_slave	*atslave = chan->private;
> +	struct dma_slave_config	*sconfig = &atchan->dma_sconfig;
>  	struct at_desc		*first = NULL;
>  	struct at_desc		*prev = NULL;
>  	unsigned long		was_cyclic;
> +	unsigned int		reg_width;
>  	unsigned int		periods = buf_len / period_len;
>  	unsigned int		i;
>  
> @@ -869,8 +875,13 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
>  		return NULL;
>  	}
>  
> +	if (sconfig->direction == DMA_MEM_TO_DEV)
> +		reg_width = convert_buswidth(sconfig->dst_addr_width);
> +	else
> +		reg_width = convert_buswidth(sconfig->src_addr_width);
> +
>  	/* Check for too big/unaligned periods and unaligned DMA buffer */
> -	if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr,
> +	if (atc_dma_cyclic_check_values(reg_width, buf_addr,
>  					period_len, direction))
>  		goto err_out;
>  
> @@ -882,8 +893,8 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
>  		if (!desc)
>  			goto err_desc_get;
>  
> -		if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr,
> -						period_len, direction))
> +		if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr,
> +					     reg_width, period_len, direction))
>  			goto err_desc_get;
>  
>  		atc_desc_chain(&first, &prev, desc);
> @@ -906,6 +917,23 @@ err_out:
>  	return NULL;
>  }
>  
> +static int set_runtime_config(struct dma_chan *chan,
> +			      struct dma_slave_config *sconfig)
> +{
> +	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
> +
> +	/* Check if it is chan is configured for slave transfers */
> +	if (!chan->private)
> +		return -EINVAL;
> +
> +	memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig));
> +
> +	convert_burst(&atchan->dma_sconfig.src_maxburst);
> +	convert_burst(&atchan->dma_sconfig.dst_maxburst);
> +
> +	return 0;
> +}
> +
>  
>  static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
>  		       unsigned long arg)
> @@ -966,6 +994,8 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
>  		clear_bit(ATC_IS_CYCLIC, &atchan->status);
>  
>  		spin_unlock_irqrestore(&atchan->lock, flags);
> +	} else if (cmd == DMA_SLAVE_CONFIG) {
> +		return set_runtime_config(chan, (struct dma_slave_config *)arg);
>  	} else {
>  		return -ENXIO;
>  	}
> diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
> index 08fd8a0..897a8bc 100644
> --- a/drivers/dma/at_hdmac_regs.h
> +++ b/drivers/dma/at_hdmac_regs.h
> @@ -207,6 +207,7 @@ enum atc_status {
>   * @save_cfg: configuration register that is saved on suspend/resume cycle
>   * @save_dscr: for cyclic operations, preserve next descriptor address in
>   *             the cyclic list on suspend/resume cycle
> + * @dma_sconfig: configuration for slave transfers, passed via DMA_SLAVE_CONFIG
>   * @lock: serializes enqueue/dequeue operations to descriptors lists
>   * @active_list: list of descriptors dmaengine is being running on
>   * @queue: list of descriptors ready to be submitted to engine
> @@ -222,6 +223,7 @@ struct at_dma_chan {
>  	struct tasklet_struct	tasklet;
>  	u32			save_cfg;
>  	u32			save_dscr;
> +	struct dma_slave_config dma_sconfig;
>  
>  	spinlock_t		lock;
>  
> @@ -243,6 +245,36 @@ static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
>  	return container_of(dchan, struct at_dma_chan, chan_common);
>  }
>  
> +/*
> + * Fix sconfig's burst size according to at_hdmac. We need to convert them as:
> + * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
> + *
> + * This can be done by finding most significant bit set.
> + */
> +static inline void convert_burst(u32 *maxburst)
> +{
> +	if (*maxburst > 1)
> +		*maxburst = fls(*maxburst) - 2;
> +	else
> +		*maxburst = 0;
> +}
> +
> +/*
> + * Fix sconfig's bus width according to at_hdmac.
> + * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
> + */
> +static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
> +{
> +	switch (addr_width) {
> +	case DMA_SLAVE_BUSWIDTH_2_BYTES:
> +		return 1;
> +	case DMA_SLAVE_BUSWIDTH_4_BYTES:
> +		return 2;
> +	default:
> +		/* For 1 byte width or fallback */
> +		return 0;
> +	}
> +}
>  
>  /*--  Controller  ------------------------------------------------------*/
>  


-- 
Nicolas Ferre


From shawn.guo at linaro.org  Fri Mar 16 04:49:54 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:49:54 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20321.53468.310199.875966@ipc1.ka-ro>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
Message-ID: <20120316084952.GG7758@S2101-09.ap.freescale.net>

On Thu, Mar 15, 2012 at 12:22:04PM +0100, Lothar Wa?mann wrote:
...
> An intermediate solution could be using OF_DEV_AUXDATA to pass a
> platform_data struct that may contain a MAC address set up by the
> platform code.
> 
+1

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Fri Mar 16 04:56:36 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:56:36 +0800
Subject: [PATCH v5] ASoC: add imx-sgtl5000 machine driver working with fsl_ssi
Message-ID: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>

Changes since v4:
 * Add new_binding flag for fsl_ssi driver to support both
   "old binding" and "new binding"

---
Shawn Guo (8):
      ASoC: fsl: separate SSI and DMA Kconfig options
      ASoC: imx: merge sound/soc/imx into sound/soc/fsl
      ASoC: fsl: rename imx-pcm Kconfig options and filename
      ASoC: fsl: create fsl_utils to accommodate the common functions
      ASoC: fsl: remove helper fsl_asoc_get_codec_dev_name
      ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
      ASoC: fsl: let fsl_ssi work with imx pcm and machine drivers
      ASoC: fsl: add imx-sgtl5000 machine driver

 .../bindings/sound/imx-audio-sgtl5000.txt          |   24 +++
 arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig   |    1 +
 arch/powerpc/configs/mpc85xx_defconfig             |    1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig         |    1 +
 sound/soc/Kconfig                                  |    1 -
 sound/soc/Makefile                                 |    1 -
 sound/soc/fsl/Kconfig                              |  124 +++++++++++++-
 sound/soc/fsl/Makefile                             |   29 +++-
 sound/soc/{imx => fsl}/eukrea-tlv320.c             |    2 +-
 sound/soc/fsl/fsl_ssi.c                            |  141 ++++++++++++----
 sound/soc/fsl/fsl_utils.c                          |   91 ++++++++++
 sound/soc/fsl/fsl_utils.h                          |   26 +++
 sound/soc/{imx => fsl}/imx-audmux.c                |    0
 sound/soc/{imx => fsl}/imx-audmux.h                |    0
 .../{imx/imx-pcm-dma-mx2.c => fsl/imx-pcm-dma.c}   |    0
 sound/soc/{imx => fsl}/imx-pcm-fiq.c               |    0
 sound/soc/{imx => fsl}/imx-pcm.c                   |    0
 sound/soc/{imx => fsl}/imx-pcm.h                   |    0
 sound/soc/fsl/imx-sgtl5000.c                       |  177 ++++++++++++++++++++
 sound/soc/{imx => fsl}/imx-ssi.c                   |    2 +-
 sound/soc/{imx => fsl}/imx-ssi.h                   |    0
 sound/soc/fsl/mpc8610_hpcd.c                       |  166 ++-----------------
 sound/soc/{imx => fsl}/mx27vis-aic32x4.c           |    0
 sound/soc/fsl/p1022_ds.c                           |  158 +----------------
 sound/soc/{imx => fsl}/phycore-ac97.c              |    0
 sound/soc/{imx => fsl}/wm1133-ev1.c                |    0
 sound/soc/imx/Kconfig                              |   79 ---------
 sound/soc/imx/Makefile                             |   22 ---
 28 files changed, 601 insertions(+), 445 deletions(-)


From shawn.guo at linaro.org  Fri Mar 16 04:56:37 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:56:37 +0800
Subject: [PATCH v5 1/8] ASoC: fsl: separate SSI and DMA Kconfig options
In-Reply-To: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331888204-27058-2-git-send-email-shawn.guo@linaro.org>

The fsl_ssi driver will possibly be shared between Freescale PowerPC
and ARM/IMX families, so give it a separate Kconfig option.  Then
fsl_ssi driver can possibly be selected independently from selecting
PowerPC DMA based PCM driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 sound/soc/fsl/Kconfig  |   15 +++++++++------
 sound/soc/fsl/Makefile |    3 ++-
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index d754d34..ca693b2 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,10 +1,11 @@
 config SND_MPC52xx_DMA
 	tristate
 
-# ASoC platform support for the Freescale PowerPC SOCs that have an SSI and
-# an Elo DMA controller, such as the MPC8610 and P1022.  You will still need to
-# select a platform driver and a codec driver.
-config SND_SOC_POWERPC_SSI
+config SND_SOC_FSL_SSI
+	tristate
+	depends on FSL_SOC
+
+config SND_SOC_POWERPC_DMA
 	tristate
 	depends on FSL_SOC
 
@@ -12,7 +13,8 @@ config SND_SOC_MPC8610_HPCD
 	tristate "ALSA SoC support for the Freescale MPC8610 HPCD board"
 	# I2C is necessary for the CS4270 driver
 	depends on MPC8610_HPCD && I2C
-	select SND_SOC_POWERPC_SSI
+	select SND_SOC_FSL_SSI
+	select SND_SOC_POWERPC_DMA
 	select SND_SOC_CS4270
 	select SND_SOC_CS4270_VD33_ERRATA
 	default y if MPC8610_HPCD
@@ -23,7 +25,8 @@ config SND_SOC_P1022_DS
 	tristate "ALSA SoC support for the Freescale P1022 DS board"
 	# I2C is necessary for the WM8776 driver
 	depends on P1022_DS && I2C
-	select SND_SOC_POWERPC_SSI
+	select SND_SOC_FSL_SSI
+	select SND_SOC_POWERPC_DMA
 	select SND_SOC_WM8776
 	default y if P1022_DS
 	help
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index b4a38c0..95d483f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -9,7 +9,8 @@ obj-$(CONFIG_SND_SOC_P1022_DS) += snd-soc-p1022-ds.o
 # Freescale PowerPC SSI/DMA Platform Support
 snd-soc-fsl-ssi-objs := fsl_ssi.o
 snd-soc-fsl-dma-objs := fsl_dma.o
-obj-$(CONFIG_SND_SOC_POWERPC_SSI) += snd-soc-fsl-ssi.o snd-soc-fsl-dma.o
+obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 
 # MPC5200 Platform Support
 obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
-- 
1.7.5.4



From shawn.guo at linaro.org  Fri Mar 16 04:56:38 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:56:38 +0800
Subject: [PATCH v5 2/8] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331888204-27058-3-git-send-email-shawn.guo@linaro.org>

Freescale PowerPC and ARM/IMX families share the same SSI IP block.
The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
code sharing and consolidation can happen.

This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
IMX platform.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig |    1 +
 arch/powerpc/configs/mpc85xx_defconfig           |    1 +
 arch/powerpc/configs/mpc85xx_smp_defconfig       |    1 +
 sound/soc/Kconfig                                |    1 -
 sound/soc/Makefile                               |    1 -
 sound/soc/fsl/Kconfig                            |   92 ++++++++++++++++++++++
 sound/soc/fsl/Makefile                           |   22 +++++
 sound/soc/{imx => fsl}/eukrea-tlv320.c           |    2 +-
 sound/soc/{imx => fsl}/imx-audmux.c              |    0
 sound/soc/{imx => fsl}/imx-audmux.h              |    0
 sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c         |    0
 sound/soc/{imx => fsl}/imx-pcm-fiq.c             |    0
 sound/soc/{imx => fsl}/imx-pcm.c                 |    0
 sound/soc/{imx => fsl}/imx-pcm.h                 |    0
 sound/soc/{imx => fsl}/imx-ssi.c                 |    2 +-
 sound/soc/{imx => fsl}/imx-ssi.h                 |    0
 sound/soc/{imx => fsl}/mx27vis-aic32x4.c         |    0
 sound/soc/{imx => fsl}/phycore-ac97.c            |    0
 sound/soc/{imx => fsl}/wm1133-ev1.c              |    0
 sound/soc/imx/Kconfig                            |   79 -------------------
 sound/soc/imx/Makefile                           |   22 -----
 21 files changed, 119 insertions(+), 105 deletions(-)
 rename sound/soc/{imx => fsl}/eukrea-tlv320.c (99%)
 rename sound/soc/{imx => fsl}/imx-audmux.c (100%)
 rename sound/soc/{imx => fsl}/imx-audmux.h (100%)
 rename sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm-fiq.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm.c (100%)
 rename sound/soc/{imx => fsl}/imx-pcm.h (100%)
 rename sound/soc/{imx => fsl}/imx-ssi.c (99%)
 rename sound/soc/{imx => fsl}/imx-ssi.h (100%)
 rename sound/soc/{imx => fsl}/mx27vis-aic32x4.c (100%)
 rename sound/soc/{imx => fsl}/phycore-ac97.c (100%)
 rename sound/soc/{imx => fsl}/wm1133-ev1.c (100%)
 delete mode 100644 sound/soc/imx/Kconfig
 delete mode 100644 sound/soc/imx/Makefile

diff --git a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
index 0db9ba0..c09598b 100644
--- a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
+++ b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
@@ -100,6 +100,7 @@ CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
 CONFIG_SND_SOC=y
+CONFIG_SND_POWERPC_SOC=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_CMOS=y
 CONFIG_EXT2_FS=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index f37a2ab..44605f8 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -139,6 +139,7 @@ CONFIG_SND_INTEL8X0=y
 # CONFIG_SND_PPC is not set
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=y
+CONFIG_SND_POWERPC_SOC=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index abdcd31..98e227e 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -141,6 +141,7 @@ CONFIG_SND_INTEL8X0=y
 # CONFIG_SND_PPC is not set
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=y
+CONFIG_SND_POWERPC_SOC=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 91c9855..0f85f6d 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -35,7 +35,6 @@ source "sound/soc/blackfin/Kconfig"
 source "sound/soc/davinci/Kconfig"
 source "sound/soc/ep93xx/Kconfig"
 source "sound/soc/fsl/Kconfig"
-source "sound/soc/imx/Kconfig"
 source "sound/soc/jz4740/Kconfig"
 source "sound/soc/nuc900/Kconfig"
 source "sound/soc/omap/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 2feaf37..363dfd6 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -12,7 +12,6 @@ obj-$(CONFIG_SND_SOC)	+= blackfin/
 obj-$(CONFIG_SND_SOC)	+= davinci/
 obj-$(CONFIG_SND_SOC)	+= ep93xx/
 obj-$(CONFIG_SND_SOC)	+= fsl/
-obj-$(CONFIG_SND_SOC)   += imx/
 obj-$(CONFIG_SND_SOC)	+= jz4740/
 obj-$(CONFIG_SND_SOC)	+= mid-x86/
 obj-$(CONFIG_SND_SOC)	+= mxs/
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index ca693b2..19856a0 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,3 +1,15 @@
+config SND_SOC_FSL_SSI
+	tristate
+
+menuconfig SND_POWERPC_SOC
+	tristate "SoC Audio for Freescale PowerPC CPUs"
+	depends on FSL_SOC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the PowerPC CPUs.
+
+if SND_POWERPC_SOC
+
 config SND_MPC52xx_DMA
 	tristate
 
@@ -68,3 +80,83 @@ config SND_MPC52xx_SOC_EFIKA
 	help
 	  Say Y if you want to add support for sound on the Efika.
 
+endif # SND_POWERPC_SOC
+
+menuconfig SND_IMX_SOC
+	tristate "SoC Audio for Freescale i.MX CPUs"
+	depends on ARCH_MXC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the i.MX CPUs.
+
+if SND_IMX_SOC
+
+config SND_SOC_IMX_SSI
+	tristate
+
+config SND_SOC_IMX_PCM
+	tristate
+
+config SND_MXC_SOC_FIQ
+	tristate
+	select FIQ
+	select SND_SOC_IMX_PCM
+
+config SND_MXC_SOC_MX2
+	tristate
+	select SND_SOC_DMAENGINE_PCM
+	select SND_SOC_IMX_PCM
+
+config SND_SOC_IMX_AUDMUX
+	tristate
+
+config SND_MXC_SOC_WM1133_EV1
+	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
+	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
+	select SND_SOC_WM8350
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
+	  PMIC board with WM8835x fitted.
+
+config SND_SOC_MX27VIS_AIC32X4
+	tristate "SoC audio support for Visstrim M10 boards"
+	depends on MACH_IMX27_VISSTRIM_M10 && I2C
+	select SND_SOC_TLV320AIC32X4
+	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Say Y if you want to add support for SoC audio on Visstrim SM10
+	  board with TLV320AIC32X4 codec.
+
+config SND_SOC_PHYCORE_AC97
+	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
+	depends on MACH_PCM043 || MACH_PCA100
+	select SND_SOC_AC97_BUS
+	select SND_SOC_WM9712
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Say Y if you want to add support for SoC audio on Phytec phyCORE
+	  and phyCARD boards in AC97 mode
+
+config SND_SOC_EUKREA_TLV320
+	tristate "Eukrea TLV320"
+	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
+		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
+	depends on I2C
+	select SND_SOC_TLV320AIC23
+	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_IMX_SSI
+	help
+	  Enable I2S based access to the TLV320AIC23B codec attached
+	  to the SSI interface
+
+endif # SND_IMX_SOC
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 95d483f..36c257f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -21,3 +21,25 @@ obj-$(CONFIG_SND_SOC_MPC5200_AC97) += mpc5200_psc_ac97.o
 obj-$(CONFIG_SND_MPC52xx_SOC_PCM030) += pcm030-audio-fabric.o
 obj-$(CONFIG_SND_MPC52xx_SOC_EFIKA) += efika-audio-fabric.o
 
+# i.MX Platform Support
+snd-soc-imx-ssi-objs := imx-ssi.o
+snd-soc-imx-audmux-objs := imx-audmux.o
+
+obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
+obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
+
+obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
+snd-soc-imx-pcm-y := imx-pcm.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
+snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
+
+# i.MX Machine Support
+snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
+snd-soc-phycore-ac97-objs := phycore-ac97.o
+snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
+snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+
+obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
+obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
+obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
+obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/fsl/eukrea-tlv320.c
similarity index 99%
rename from sound/soc/imx/eukrea-tlv320.c
rename to sound/soc/fsl/eukrea-tlv320.c
index 7d4475c..efb9ede 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/fsl/eukrea-tlv320.c
@@ -7,7 +7,7 @@
  * which is Copyright 2009 Simtec Electronics
  * and on sound/soc/imx/phycore-ac97.c which is
  * Copyright 2009 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
- * 
+ *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
  *  Free Software Foundation;  either version 2 of the  License, or (at your
diff --git a/sound/soc/imx/imx-audmux.c b/sound/soc/fsl/imx-audmux.c
similarity index 100%
rename from sound/soc/imx/imx-audmux.c
rename to sound/soc/fsl/imx-audmux.c
diff --git a/sound/soc/imx/imx-audmux.h b/sound/soc/fsl/imx-audmux.h
similarity index 100%
rename from sound/soc/imx/imx-audmux.h
rename to sound/soc/fsl/imx-audmux.h
diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/fsl/imx-pcm-dma-mx2.c
similarity index 100%
rename from sound/soc/imx/imx-pcm-dma-mx2.c
rename to sound/soc/fsl/imx-pcm-dma-mx2.c
diff --git a/sound/soc/imx/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
similarity index 100%
rename from sound/soc/imx/imx-pcm-fiq.c
rename to sound/soc/fsl/imx-pcm-fiq.c
diff --git a/sound/soc/imx/imx-pcm.c b/sound/soc/fsl/imx-pcm.c
similarity index 100%
rename from sound/soc/imx/imx-pcm.c
rename to sound/soc/fsl/imx-pcm.c
diff --git a/sound/soc/imx/imx-pcm.h b/sound/soc/fsl/imx-pcm.h
similarity index 100%
rename from sound/soc/imx/imx-pcm.h
rename to sound/soc/fsl/imx-pcm.h
diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
similarity index 99%
rename from sound/soc/imx/imx-ssi.c
rename to sound/soc/fsl/imx-ssi.c
index 9203cdd..3e0dac5a 100644
--- a/sound/soc/imx/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -28,7 +28,7 @@
  * value. When we read the same register two times (and the register still
  * contains the same value) these status bits are not set. We work
  * around this by not polling these bits but only wait a fixed delay.
- * 
+ *
  */
 
 #include <linux/clk.h>
diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/fsl/imx-ssi.h
similarity index 100%
rename from sound/soc/imx/imx-ssi.h
rename to sound/soc/fsl/imx-ssi.h
diff --git a/sound/soc/imx/mx27vis-aic32x4.c b/sound/soc/fsl/mx27vis-aic32x4.c
similarity index 100%
rename from sound/soc/imx/mx27vis-aic32x4.c
rename to sound/soc/fsl/mx27vis-aic32x4.c
diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/fsl/phycore-ac97.c
similarity index 100%
rename from sound/soc/imx/phycore-ac97.c
rename to sound/soc/fsl/phycore-ac97.c
diff --git a/sound/soc/imx/wm1133-ev1.c b/sound/soc/fsl/wm1133-ev1.c
similarity index 100%
rename from sound/soc/imx/wm1133-ev1.c
rename to sound/soc/fsl/wm1133-ev1.c
diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
deleted file mode 100644
index 810acaa..0000000
--- a/sound/soc/imx/Kconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-menuconfig SND_IMX_SOC
-	tristate "SoC Audio for Freescale i.MX CPUs"
-	depends on ARCH_MXC
-	help
-	  Say Y or M if you want to add support for codecs attached to
-	  the i.MX SSI interface.
-
-
-if SND_IMX_SOC
-
-config SND_SOC_IMX_SSI
-	tristate
-
-config SND_SOC_IMX_PCM
-	tristate
-
-config SND_MXC_SOC_FIQ
-	tristate
-	select FIQ
-	select SND_SOC_IMX_PCM
-
-config SND_MXC_SOC_MX2
-	select SND_SOC_DMAENGINE_PCM
-	tristate
-	select SND_SOC_IMX_PCM
-
-config SND_SOC_IMX_AUDMUX
-	tristate
-
-config SND_MXC_SOC_WM1133_EV1
-	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
-	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
-	select SND_SOC_WM8350
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
-	  PMIC board with WM8835x fitted.
-
-config SND_SOC_MX27VIS_AIC32X4
-	tristate "SoC audio support for Visstrim M10 boards"
-	depends on MACH_IMX27_VISSTRIM_M10 && I2C
-	select SND_SOC_TLV320AIC32X4
-	select SND_MXC_SOC_MX2
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Say Y if you want to add support for SoC audio on Visstrim SM10
-	  board with TLV320AIC32X4 codec.
-
-config SND_SOC_PHYCORE_AC97
-	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
-	depends on MACH_PCM043 || MACH_PCA100
-	select SND_SOC_AC97_BUS
-	select SND_SOC_WM9712
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Say Y if you want to add support for SoC audio on Phytec phyCORE
-	  and phyCARD boards in AC97 mode
-
-config SND_SOC_EUKREA_TLV320
-	tristate "Eukrea TLV320"
-	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
-		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
-	depends on I2C
-	select SND_SOC_TLV320AIC23
-	select SND_MXC_SOC_FIQ
-	select SND_SOC_IMX_AUDMUX
-	select SND_SOC_IMX_SSI
-	help
-	  Enable I2S based access to the TLV320AIC23B codec attached
-	  to the SSI interface
-
-endif	# SND_IMX_SOC
diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
deleted file mode 100644
index f5db3e9..0000000
--- a/sound/soc/imx/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-# i.MX Platform Support
-snd-soc-imx-ssi-objs := imx-ssi.o
-snd-soc-imx-audmux-objs := imx-audmux.o
-
-obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
-obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
-
-obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
-snd-soc-imx-pcm-y := imx-pcm.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
-
-# i.MX Machine Support
-snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
-snd-soc-phycore-ac97-objs := phycore-ac97.o
-snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
-snd-soc-wm1133-ev1-objs := wm1133-ev1.o
-
-obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
-obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
-obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
-obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
-- 
1.7.5.4



From shawn.guo at linaro.org  Fri Mar 16 04:56:39 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:56:39 +0800
Subject: [PATCH v5 3/8] ASoC: fsl: rename imx-pcm Kconfig options and filename
In-Reply-To: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331888204-27058-4-git-send-email-shawn.guo@linaro.org>

Rename a couple of imx-pcm Kconfig options and filename to get them
well named and less confusing.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 sound/soc/fsl/Kconfig                              |   12 ++++++------
 sound/soc/fsl/Makefile                             |    4 ++--
 sound/soc/fsl/{imx-pcm-dma-mx2.c => imx-pcm-dma.c} |    0
 3 files changed, 8 insertions(+), 8 deletions(-)
 rename sound/soc/fsl/{imx-pcm-dma-mx2.c => imx-pcm-dma.c} (100%)

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 19856a0..e3f7509 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -97,12 +97,12 @@ config SND_SOC_IMX_SSI
 config SND_SOC_IMX_PCM
 	tristate
 
-config SND_MXC_SOC_FIQ
+config SND_SOC_IMX_PCM_FIQ
 	tristate
 	select FIQ
 	select SND_SOC_IMX_PCM
 
-config SND_MXC_SOC_MX2
+config SND_SOC_IMX_PCM_DMA
 	tristate
 	select SND_SOC_DMAENGINE_PCM
 	select SND_SOC_IMX_PCM
@@ -114,7 +114,7 @@ config SND_MXC_SOC_WM1133_EV1
 	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
 	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
 	select SND_SOC_WM8350
-	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_PCM_FIQ
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
@@ -125,7 +125,7 @@ config SND_SOC_MX27VIS_AIC32X4
 	tristate "SoC audio support for Visstrim M10 boards"
 	depends on MACH_IMX27_VISSTRIM_M10 && I2C
 	select SND_SOC_TLV320AIC32X4
-	select SND_MXC_SOC_MX2
+	select SND_SOC_IMX_PCM_DMA
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
@@ -137,7 +137,7 @@ config SND_SOC_PHYCORE_AC97
 	depends on MACH_PCM043 || MACH_PCA100
 	select SND_SOC_AC97_BUS
 	select SND_SOC_WM9712
-	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_PCM_FIQ
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
@@ -152,7 +152,7 @@ config SND_SOC_EUKREA_TLV320
 		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
 	depends on I2C
 	select SND_SOC_TLV320AIC23
-	select SND_MXC_SOC_FIQ
+	select SND_SOC_IMX_PCM_FIQ
 	select SND_SOC_IMX_AUDMUX
 	select SND_SOC_IMX_SSI
 	help
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 36c257f..f031409 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -30,8 +30,8 @@ obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
 
 obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
 snd-soc-imx-pcm-y := imx-pcm.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
-snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
+snd-soc-imx-pcm-$(CONFIG_SND_SOC_IMX_PCM_FIQ) += imx-pcm-fiq.o
+snd-soc-imx-pcm-$(CONFIG_SND_SOC_IMX_PCM_DMA) += imx-pcm-dma.o
 
 # i.MX Machine Support
 snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
diff --git a/sound/soc/fsl/imx-pcm-dma-mx2.c b/sound/soc/fsl/imx-pcm-dma.c
similarity index 100%
rename from sound/soc/fsl/imx-pcm-dma-mx2.c
rename to sound/soc/fsl/imx-pcm-dma.c
-- 
1.7.5.4



From shawn.guo at linaro.org  Fri Mar 16 04:56:40 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:56:40 +0800
Subject: [PATCH v5 4/8] ASoC: fsl: create fsl_utils to accommodate the common
 functions
In-Reply-To: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331888204-27058-5-git-send-email-shawn.guo@linaro.org>

There is some amount of code duplication between mpc8610_hpcd and
p1022_ds machine drivers, and the same code will be duplicated again
when another new machine driver is added.  The patch creates fsl_utils
to accommodate the common functions to stop the code duplication.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 sound/soc/fsl/Kconfig        |    5 ++
 sound/soc/fsl/Makefile       |    2 +
 sound/soc/fsl/fsl_utils.c    |  135 ++++++++++++++++++++++++++++++++++++
 sound/soc/fsl/fsl_utils.h    |   27 +++++++
 sound/soc/fsl/mpc8610_hpcd.c |  157 +++---------------------------------------
 sound/soc/fsl/p1022_ds.c     |  149 +++-------------------------------------
 6 files changed, 189 insertions(+), 286 deletions(-)
 create mode 100644 sound/soc/fsl/fsl_utils.c
 create mode 100644 sound/soc/fsl/fsl_utils.h

diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index e3f7509..535ee73 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -1,6 +1,9 @@
 config SND_SOC_FSL_SSI
 	tristate
 
+config SND_SOC_FSL_UTILS
+	tristate
+
 menuconfig SND_POWERPC_SOC
 	tristate "SoC Audio for Freescale PowerPC CPUs"
 	depends on FSL_SOC
@@ -26,6 +29,7 @@ config SND_SOC_MPC8610_HPCD
 	# I2C is necessary for the CS4270 driver
 	depends on MPC8610_HPCD && I2C
 	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
 	select SND_SOC_POWERPC_DMA
 	select SND_SOC_CS4270
 	select SND_SOC_CS4270_VD33_ERRATA
@@ -38,6 +42,7 @@ config SND_SOC_P1022_DS
 	# I2C is necessary for the WM8776 driver
 	depends on P1022_DS && I2C
 	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
 	select SND_SOC_POWERPC_DMA
 	select SND_SOC_WM8776
 	default y if P1022_DS
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index f031409..fbdbed0 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -8,8 +8,10 @@ obj-$(CONFIG_SND_SOC_P1022_DS) += snd-soc-p1022-ds.o
 
 # Freescale PowerPC SSI/DMA Platform Support
 snd-soc-fsl-ssi-objs := fsl_ssi.o
+snd-soc-fsl-utils-objs := fsl_utils.o
 snd-soc-fsl-dma-objs := fsl_dma.o
 obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
 obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
 
 # MPC5200 Platform Support
diff --git a/sound/soc/fsl/fsl_utils.c b/sound/soc/fsl/fsl_utils.c
new file mode 100644
index 0000000..4370c28
--- /dev/null
+++ b/sound/soc/fsl/fsl_utils.c
@@ -0,0 +1,135 @@
+/**
+ * Freescale ALSA SoC Machine driver utility
+ *
+ * Author: Timur Tabi <timur at freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_i2c.h>
+#include <sound/soc.h>
+
+#include "fsl_utils.h"
+
+/**
+ * fsl_asoc_get_codec_dev_name - determine the dev_name for a codec node
+ *
+ * @np: pointer to the I2C device tree node
+ * @buf: buffer to be filled with the dev_name of the I2C device
+ * @len: the length of the buffer
+ *
+ * This function determines the dev_name for an I2C node.  This is the name
+ * that would be returned by dev_name() if this device_node were part of a
+ * 'struct device'  It's ugly and hackish, but it works.
+ *
+ * The dev_name for such devices include the bus number and I2C address. For
+ * example, "cs4270.0-004f".
+ */
+int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len)
+{
+	const u32 *iprop;
+	u32 addr;
+	char temp[DAI_NAME_SIZE];
+	struct i2c_client *i2c;
+
+	of_modalias_node(np, temp, DAI_NAME_SIZE);
+
+	iprop = of_get_property(np, "reg", NULL);
+	if (!iprop)
+		return -EINVAL;
+
+	addr = be32_to_cpup(iprop);
+
+	/* We need the adapter number */
+	i2c = of_find_i2c_device_by_node(np);
+	if (!i2c) {
+		put_device(&i2c->dev);
+		return -ENODEV;
+	}
+
+	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
+	put_device(&i2c->dev);
+
+	return 0;
+}
+EXPORT_SYMBOL(fsl_asoc_get_codec_dev_name);
+
+/**
+ * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
+ *
+ * @ssi_np: pointer to the SSI device tree node
+ * @name: name of the phandle pointing to the dma channel
+ * @dai: ASoC DAI link pointer to be filled with platform_name
+ * @dma_channel_id: dma channel id to be returned
+ * @dma_id: dma id to be returned
+ *
+ * This function determines the dma and channel id for given SSI node.  It
+ * also discovers the platform_name for the ASoC DAI link.
+ */
+int fsl_asoc_get_dma_channel(struct device_node *ssi_np,
+			     const char *name,
+			     struct snd_soc_dai_link *dai,
+			     unsigned int *dma_channel_id,
+			     unsigned int *dma_id)
+{
+	struct resource res;
+	struct device_node *dma_channel_np, *dma_np;
+	const u32 *iprop;
+	int ret;
+
+	dma_channel_np = of_parse_phandle(ssi_np, name, 0);
+	if (!dma_channel_np)
+		return -EINVAL;
+
+	if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) {
+		of_node_put(dma_channel_np);
+		return -EINVAL;
+	}
+
+	/* Determine the dev_name for the device_node.  This code mimics the
+	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
+	 * the dev_name() of the device to match the platform (DMA) device with
+	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
+	 * now).
+	 *
+	 * dai->platform name should already point to an allocated buffer.
+	 */
+	ret = of_address_to_resource(dma_channel_np, 0, &res);
+	if (ret) {
+		of_node_put(dma_channel_np);
+		return ret;
+	}
+	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
+		 (unsigned long long) res.start, dma_channel_np->name);
+
+	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
+	if (!iprop) {
+		of_node_put(dma_channel_np);
+		return -EINVAL;
+	}
+	*dma_channel_id = be32_to_cpup(iprop);
+
+	dma_np = of_get_parent(dma_channel_np);
+	iprop = of_get_property(dma_np, "cell-index", NULL);
+	if (!iprop) {
+		of_node_put(dma_np);
+		return -EINVAL;
+	}
+	*dma_id = be32_to_cpup(iprop);
+
+	of_node_put(dma_np);
+	of_node_put(dma_channel_np);
+
+	return 0;
+}
+EXPORT_SYMBOL(fsl_asoc_get_dma_channel);
+
+MODULE_AUTHOR("Timur Tabi <timur at freescale.com>");
+MODULE_DESCRIPTION("Freescale ASoC utility code");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/fsl/fsl_utils.h b/sound/soc/fsl/fsl_utils.h
new file mode 100644
index 0000000..44d1436
--- /dev/null
+++ b/sound/soc/fsl/fsl_utils.h
@@ -0,0 +1,27 @@
+/**
+ * Freescale ALSA SoC Machine driver utility
+ *
+ * Author: Timur Tabi <timur at freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef _FSL_UTILS_H
+#define _FSL_UTILS_H
+
+#define DAI_NAME_SIZE	32
+
+struct snd_soc_dai_link;
+struct device_node;
+
+int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len);
+int fsl_asoc_get_dma_channel(struct device_node *ssi_np, const char *name,
+			     struct snd_soc_dai_link *dai,
+			     unsigned int *dma_channel_id,
+			     unsigned int *dma_id);
+
+#endif /* _FSL_UTILS_H */
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index afbabf4..4195182 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -14,18 +14,16 @@
 #include <linux/interrupt.h>
 #include <linux/of_device.h>
 #include <linux/slab.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 #include <asm/fsl_guts.h>
 
 #include "fsl_dma.h"
 #include "fsl_ssi.h"
+#include "fsl_utils.h"
 
 /* There's only one global utilities register */
 static phys_addr_t guts_phys;
 
-#define DAI_NAME_SIZE	32
-
 /**
  * mpc8610_hpcd_data: machine-specific ASoC device data
  *
@@ -181,141 +179,6 @@ static struct snd_soc_ops mpc8610_hpcd_ops = {
 };
 
 /**
- * get_node_by_phandle_name - get a node by its phandle name
- *
- * This function takes a node, the name of a property in that node, and a
- * compatible string.  Assuming the property is a phandle to another node,
- * it returns that node, (optionally) if that node is compatible.
- *
- * If the property is not a phandle, or the node it points to is not compatible
- * with the specific string, then NULL is returned.
- */
-static struct device_node *get_node_by_phandle_name(struct device_node *np,
-					       const char *name,
-					       const char *compatible)
-{
-	const phandle *ph;
-	int len;
-
-	ph = of_get_property(np, name, &len);
-	if (!ph || (len != sizeof(phandle)))
-		return NULL;
-
-	np = of_find_node_by_phandle(*ph);
-	if (!np)
-		return NULL;
-
-	if (compatible && !of_device_is_compatible(np, compatible)) {
-		of_node_put(np);
-		return NULL;
-	}
-
-	return np;
-}
-
-/**
- * get_parent_cell_index -- return the cell-index of the parent of a node
- *
- * Return the value of the cell-index property of the parent of the given
- * node.  This is used for DMA channel nodes that need to know the DMA ID
- * of the controller they are on.
- */
-static int get_parent_cell_index(struct device_node *np)
-{
-	struct device_node *parent = of_get_parent(np);
-	const u32 *iprop;
-
-	if (!parent)
-		return -1;
-
-	iprop = of_get_property(parent, "cell-index", NULL);
-	of_node_put(parent);
-
-	if (!iprop)
-		return -1;
-
-	return be32_to_cpup(iprop);
-}
-
-/**
- * codec_node_dev_name - determine the dev_name for a codec node
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270.0-004f".
- */
-static int codec_node_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	int addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c)
-		return -ENODEV;
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-
-	return 0;
-}
-
-static int get_dma_channel(struct device_node *ssi_np,
-			   const char *name,
-			   struct snd_soc_dai_link *dai,
-			   unsigned int *dma_channel_id,
-			   unsigned int *dma_id)
-{
-	struct resource res;
-	struct device_node *dma_channel_np;
-	const u32 *iprop;
-	int ret;
-
-	dma_channel_np = get_node_by_phandle_name(ssi_np, name,
-						  "fsl,ssi-dma-channel");
-	if (!dma_channel_np)
-		return -EINVAL;
-
-	/* Determine the dev_name for the device_node.  This code mimics the
-	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
-	 * the dev_name() of the device to match the platform (DMA) device with
-	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
-	 * now).
-	 *
-	 * dai->platform name should already point to an allocated buffer.
-	 */
-	ret = of_address_to_resource(dma_channel_np, 0, &res);
-	if (ret)
-		return ret;
-	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
-		 (unsigned long long) res.start, dma_channel_np->name);
-
-	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
-	if (!iprop) {
-		of_node_put(dma_channel_np);
-		return -EINVAL;
-	}
-
-	*dma_channel_id = be32_to_cpup(iprop);
-	*dma_id = get_parent_cell_index(dma_channel_np);
-	of_node_put(dma_channel_np);
-
-	return 0;
-}
-
-/**
  * mpc8610_hpcd_probe: platform probe function for the machine driver
  *
  * Although this is a machine driver, the SSI node is the "master" node with
@@ -353,8 +216,8 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 	machine_data->dai[0].ops = &mpc8610_hpcd_ops;
 
 	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = codec_node_dev_name(codec_np, machine_data->codec_name,
-				  DAI_NAME_SIZE);
+	ret = fsl_asoc_get_codec_dev_name(codec_np, machine_data->codec_name,
+					  DAI_NAME_SIZE);
 	if (ret) {
 		dev_err(&pdev->dev, "invalid codec node %s\n",
 			codec_np->full_name);
@@ -458,9 +321,10 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 
 	/* Find the playback DMA channel to use. */
 	machine_data->dai[0].platform_name = machine_data->platform_name[0];
-	ret = get_dma_channel(np, "fsl,playback-dma", &machine_data->dai[0],
-			      &machine_data->dma_channel_id[0],
-			      &machine_data->dma_id[0]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma",
+				       &machine_data->dai[0],
+				       &machine_data->dma_channel_id[0],
+				       &machine_data->dma_id[0]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
 		goto error;
@@ -468,9 +332,10 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 
 	/* Find the capture DMA channel to use. */
 	machine_data->dai[1].platform_name = machine_data->platform_name[1];
-	ret = get_dma_channel(np, "fsl,capture-dma", &machine_data->dai[1],
-			      &machine_data->dma_channel_id[1],
-			      &machine_data->dma_id[1]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma",
+				       &machine_data->dai[1],
+				       &machine_data->dma_channel_id[1],
+				       &machine_data->dma_id[1]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
 		goto error;
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index b889870..e3680ce 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -14,12 +14,12 @@
 #include <linux/interrupt.h>
 #include <linux/of_device.h>
 #include <linux/slab.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 #include <asm/fsl_guts.h>
 
 #include "fsl_dma.h"
 #include "fsl_ssi.h"
+#include "fsl_utils.h"
 
 /* P1022-specific PMUXCR and DMUXCR bit definitions */
 
@@ -57,8 +57,6 @@ static inline void guts_set_dmuxcr(struct ccsr_guts_85xx __iomem *guts,
 /* There's only one global utilities register */
 static phys_addr_t guts_phys;
 
-#define DAI_NAME_SIZE	32
-
 /**
  * machine_data: machine-specific ASoC device data
  *
@@ -191,136 +189,6 @@ static struct snd_soc_ops p1022_ds_ops = {
 };
 
 /**
- * get_node_by_phandle_name - get a node by its phandle name
- *
- * This function takes a node, the name of a property in that node, and a
- * compatible string.  Assuming the property is a phandle to another node,
- * it returns that node, (optionally) if that node is compatible.
- *
- * If the property is not a phandle, or the node it points to is not compatible
- * with the specific string, then NULL is returned.
- */
-static struct device_node *get_node_by_phandle_name(struct device_node *np,
-	const char *name, const char *compatible)
-{
-	np = of_parse_phandle(np, name, 0);
-	if (!np)
-		return NULL;
-
-	if (!of_device_is_compatible(np, compatible)) {
-		of_node_put(np);
-		return NULL;
-	}
-
-	return np;
-}
-
-/**
- * get_parent_cell_index -- return the cell-index of the parent of a node
- *
- * Return the value of the cell-index property of the parent of the given
- * node.  This is used for DMA channel nodes that need to know the DMA ID
- * of the controller they are on.
- */
-static int get_parent_cell_index(struct device_node *np)
-{
-	struct device_node *parent = of_get_parent(np);
-	const u32 *iprop;
-	int ret = -1;
-
-	if (!parent)
-		return -1;
-
-	iprop = of_get_property(parent, "cell-index", NULL);
-	if (iprop)
-		ret = be32_to_cpup(iprop);
-
-	of_node_put(parent);
-
-	return ret;
-}
-
-/**
- * codec_node_dev_name - determine the dev_name for a codec node
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270-codec.0-004f".
- */
-static int codec_node_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	int addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c)
-		return -ENODEV;
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-
-	return 0;
-}
-
-static int get_dma_channel(struct device_node *ssi_np,
-			   const char *name,
-			   struct snd_soc_dai_link *dai,
-			   unsigned int *dma_channel_id,
-			   unsigned int *dma_id)
-{
-	struct resource res;
-	struct device_node *dma_channel_np;
-	const u32 *iprop;
-	int ret;
-
-	dma_channel_np = get_node_by_phandle_name(ssi_np, name,
-						  "fsl,ssi-dma-channel");
-	if (!dma_channel_np)
-		return -EINVAL;
-
-	/* Determine the dev_name for the device_node.  This code mimics the
-	 * behavior of of_device_make_bus_id(). We need this because ASoC uses
-	 * the dev_name() of the device to match the platform (DMA) device with
-	 * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
-	 * now).
-	 *
-	 * dai->platform name should already point to an allocated buffer.
-	 */
-	ret = of_address_to_resource(dma_channel_np, 0, &res);
-	if (ret) {
-		of_node_put(dma_channel_np);
-		return ret;
-	}
-	snprintf((char *)dai->platform_name, DAI_NAME_SIZE, "%llx.%s",
-		 (unsigned long long) res.start, dma_channel_np->name);
-
-	iprop = of_get_property(dma_channel_np, "cell-index", NULL);
-	if (!iprop) {
-		of_node_put(dma_channel_np);
-		return -EINVAL;
-	}
-
-	*dma_channel_id = be32_to_cpup(iprop);
-	*dma_id = get_parent_cell_index(dma_channel_np);
-	of_node_put(dma_channel_np);
-
-	return 0;
-}
-
-/**
  * p1022_ds_probe: platform probe function for the machine driver
  *
  * Although this is a machine driver, the SSI node is the "master" node with
@@ -358,7 +226,8 @@ static int p1022_ds_probe(struct platform_device *pdev)
 	mdata->dai[0].ops = &p1022_ds_ops;
 
 	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = codec_node_dev_name(codec_np, mdata->codec_name, DAI_NAME_SIZE);
+	ret = fsl_asoc_get_codec_dev_name(codec_np, mdata->codec_name,
+					  DAI_NAME_SIZE);
 	if (ret) {
 		dev_err(&pdev->dev, "invalid codec node %s\n",
 			codec_np->full_name);
@@ -454,9 +323,9 @@ static int p1022_ds_probe(struct platform_device *pdev)
 
 	/* Find the playback DMA channel to use. */
 	mdata->dai[0].platform_name = mdata->platform_name[0];
-	ret = get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
-			      &mdata->dma_channel_id[0],
-			      &mdata->dma_id[0]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,playback-dma", &mdata->dai[0],
+				       &mdata->dma_channel_id[0],
+				       &mdata->dma_id[0]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid playback DMA phandle\n");
 		goto error;
@@ -464,9 +333,9 @@ static int p1022_ds_probe(struct platform_device *pdev)
 
 	/* Find the capture DMA channel to use. */
 	mdata->dai[1].platform_name = mdata->platform_name[1];
-	ret = get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
-			      &mdata->dma_channel_id[1],
-			      &mdata->dma_id[1]);
+	ret = fsl_asoc_get_dma_channel(np, "fsl,capture-dma", &mdata->dai[1],
+				       &mdata->dma_channel_id[1],
+				       &mdata->dma_id[1]);
 	if (ret) {
 		dev_err(&pdev->dev, "missing/invalid capture DMA phandle\n");
 		goto error;
-- 
1.7.5.4



From shawn.guo at linaro.org  Fri Mar 16 04:56:41 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:56:41 +0800
Subject: [PATCH v5 5/8] ASoC: fsl: remove helper fsl_asoc_get_codec_dev_name
In-Reply-To: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331888204-27058-6-git-send-email-shawn.guo@linaro.org>

The ASoC core now can support matching codec with device node besides
name, so we can save helper function fsl_asoc_get_codec_dev_name.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 sound/soc/fsl/fsl_utils.c    |   44 ------------------------------------------
 sound/soc/fsl/fsl_utils.h    |    1 -
 sound/soc/fsl/mpc8610_hpcd.c |   13 +----------
 sound/soc/fsl/p1022_ds.c     |   13 +----------
 4 files changed, 4 insertions(+), 67 deletions(-)

diff --git a/sound/soc/fsl/fsl_utils.c b/sound/soc/fsl/fsl_utils.c
index 4370c28..b9e42b5 100644
--- a/sound/soc/fsl/fsl_utils.c
+++ b/sound/soc/fsl/fsl_utils.c
@@ -12,55 +12,11 @@
 
 #include <linux/module.h>
 #include <linux/of_address.h>
-#include <linux/of_i2c.h>
 #include <sound/soc.h>
 
 #include "fsl_utils.h"
 
 /**
- * fsl_asoc_get_codec_dev_name - determine the dev_name for a codec node
- *
- * @np: pointer to the I2C device tree node
- * @buf: buffer to be filled with the dev_name of the I2C device
- * @len: the length of the buffer
- *
- * This function determines the dev_name for an I2C node.  This is the name
- * that would be returned by dev_name() if this device_node were part of a
- * 'struct device'  It's ugly and hackish, but it works.
- *
- * The dev_name for such devices include the bus number and I2C address. For
- * example, "cs4270.0-004f".
- */
-int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len)
-{
-	const u32 *iprop;
-	u32 addr;
-	char temp[DAI_NAME_SIZE];
-	struct i2c_client *i2c;
-
-	of_modalias_node(np, temp, DAI_NAME_SIZE);
-
-	iprop = of_get_property(np, "reg", NULL);
-	if (!iprop)
-		return -EINVAL;
-
-	addr = be32_to_cpup(iprop);
-
-	/* We need the adapter number */
-	i2c = of_find_i2c_device_by_node(np);
-	if (!i2c) {
-		put_device(&i2c->dev);
-		return -ENODEV;
-	}
-
-	snprintf(buf, len, "%s.%u-%04x", temp, i2c->adapter->nr, addr);
-	put_device(&i2c->dev);
-
-	return 0;
-}
-EXPORT_SYMBOL(fsl_asoc_get_codec_dev_name);
-
-/**
  * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
  *
  * @ssi_np: pointer to the SSI device tree node
diff --git a/sound/soc/fsl/fsl_utils.h b/sound/soc/fsl/fsl_utils.h
index 44d1436..b295112 100644
--- a/sound/soc/fsl/fsl_utils.h
+++ b/sound/soc/fsl/fsl_utils.h
@@ -18,7 +18,6 @@
 struct snd_soc_dai_link;
 struct device_node;
 
-int fsl_asoc_get_codec_dev_name(struct device_node *np, char *buf, size_t len);
 int fsl_asoc_get_dma_channel(struct device_node *ssi_np, const char *name,
 			     struct snd_soc_dai_link *dai,
 			     unsigned int *dma_channel_id,
diff --git a/sound/soc/fsl/mpc8610_hpcd.c b/sound/soc/fsl/mpc8610_hpcd.c
index 4195182..8fdc430 100644
--- a/sound/soc/fsl/mpc8610_hpcd.c
+++ b/sound/soc/fsl/mpc8610_hpcd.c
@@ -41,7 +41,6 @@ struct mpc8610_hpcd_data {
 	unsigned int dma_id[2];		/* 0 = DMA1, 1 = DMA2, etc */
 	unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
 	char codec_dai_name[DAI_NAME_SIZE];
-	char codec_name[DAI_NAME_SIZE];
 	char platform_name[2][DAI_NAME_SIZE]; /* One for each DMA channel */
 };
 
@@ -215,16 +214,8 @@ static int mpc8610_hpcd_probe(struct platform_device *pdev)
 	machine_data->dai[0].cpu_dai_name = dev_name(&ssi_pdev->dev);
 	machine_data->dai[0].ops = &mpc8610_hpcd_ops;
 
-	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = fsl_asoc_get_codec_dev_name(codec_np, machine_data->codec_name,
-					  DAI_NAME_SIZE);
-	if (ret) {
-		dev_err(&pdev->dev, "invalid codec node %s\n",
-			codec_np->full_name);
-		ret = -EINVAL;
-		goto error;
-	}
-	machine_data->dai[0].codec_name = machine_data->codec_name;
+	/* ASoC core can match codec with device node */
+	machine_data->dai[0].codec_of_node = codec_np;
 
 	/* The DAI name from the codec (snd_soc_dai_driver.name) */
 	machine_data->dai[0].codec_dai_name = "cs4270-hifi";
diff --git a/sound/soc/fsl/p1022_ds.c b/sound/soc/fsl/p1022_ds.c
index e3680ce..0f42f31 100644
--- a/sound/soc/fsl/p1022_ds.c
+++ b/sound/soc/fsl/p1022_ds.c
@@ -73,7 +73,6 @@ struct machine_data {
 	unsigned int ssi_id;		/* 0 = SSI1, 1 = SSI2, etc */
 	unsigned int dma_id[2];		/* 0 = DMA1, 1 = DMA2, etc */
 	unsigned int dma_channel_id[2]; /* 0 = ch 0, 1 = ch 1, etc*/
-	char codec_name[DAI_NAME_SIZE];
 	char platform_name[2][DAI_NAME_SIZE]; /* One for each DMA channel */
 };
 
@@ -225,16 +224,8 @@ static int p1022_ds_probe(struct platform_device *pdev)
 	mdata->dai[0].cpu_dai_name = dev_name(&ssi_pdev->dev);
 	mdata->dai[0].ops = &p1022_ds_ops;
 
-	/* Determine the codec name, it will be used as the codec DAI name */
-	ret = fsl_asoc_get_codec_dev_name(codec_np, mdata->codec_name,
-					  DAI_NAME_SIZE);
-	if (ret) {
-		dev_err(&pdev->dev, "invalid codec node %s\n",
-			codec_np->full_name);
-		ret = -EINVAL;
-		goto error;
-	}
-	mdata->dai[0].codec_name = mdata->codec_name;
+	/* ASoC core can match codec with device node */
+	mdata->dai[0].codec_of_node = codec_np;
 
 	/* We register two DAIs per SSI, one for playback and the other for
 	 * capture.  We support codecs that have separate DAIs for both playback
-- 
1.7.5.4



From shawn.guo at linaro.org  Fri Mar 16 04:56:42 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:56:42 +0800
Subject: [PATCH v5 6/8] ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
In-Reply-To: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331888204-27058-7-git-send-email-shawn.guo@linaro.org>

Provide different pair of accessors for accessing SSI registers on
PowerPC and ARM/IMX, so that fsl_ssi driver can be built on both
architectures.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 sound/soc/fsl/fsl_ssi.c |   64 ++++++++++++++++++++++++++++++----------------
 1 files changed, 42 insertions(+), 22 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 2eb407f..db9a734 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -11,11 +11,14 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 
 #include <sound/core.h>
@@ -26,6 +29,25 @@
 
 #include "fsl_ssi.h"
 
+#ifdef PPC
+#define read_ssi(addr)			 in_be32(addr)
+#define write_ssi(val, addr)		 out_be32(addr, val)
+#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
+#elif defined ARM
+#define read_ssi(addr)			 readl(addr)
+#define write_ssi(val, addr)		 writel(val, addr)
+/*
+ * FIXME: Proper locking should be added at write_ssi_mask caller level
+ * to ensure this register read/modify/write sequence is race free.
+ */
+static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
+{
+	u32 val = readl(addr);
+	val = (val & ~clear) | set;
+	writel(val, addr);
+}
+#endif
+
 /**
  * FSLSSI_I2S_RATES: sample rates supported by the I2S
  *
@@ -145,7 +167,7 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 	   were interrupted for.  We mask it with the Interrupt Enable register
 	   so that we only check for events that we're interested in.
 	 */
-	sisr = in_be32(&ssi->sisr) & SIER_FLAGS;
+	sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
 
 	if (sisr & CCSR_SSI_SISR_RFRC) {
 		ssi_private->stats.rfrc++;
@@ -260,7 +282,7 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
 
 	/* Clear the bits that we set */
 	if (sisr2)
-		out_be32(&ssi->sisr, sisr2);
+		write_ssi(sisr2, &ssi->sisr);
 
 	return ret;
 }
@@ -295,7 +317,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 * SSI needs to be disabled before updating the registers we set
 		 * here.
 		 */
-		clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
+		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
 
 		/*
 		 * Program the SSI into I2S Slave Non-Network Synchronous mode.
@@ -303,20 +325,18 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 *
 		 * FIXME: Little-endian samples require a different shift dir
 		 */
-		clrsetbits_be32(&ssi->scr,
+		write_ssi_mask(&ssi->scr,
 			CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
 			CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE
 			| (synchronous ? CCSR_SSI_SCR_SYN : 0));
 
-		out_be32(&ssi->stcr,
-			 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
+		write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
 			 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
-			 CCSR_SSI_STCR_TSCKP);
+			 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
 
-		out_be32(&ssi->srcr,
-			 CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
+		write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
 			 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
-			 CCSR_SSI_SRCR_RSCKP);
+			 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
 
 		/*
 		 * The DC and PM bits are only used if the SSI is the clock
@@ -324,7 +344,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 */
 
 		/* Enable the interrupts and DMA requests */
-		out_be32(&ssi->sier, SIER_FLAGS);
+		write_ssi(SIER_FLAGS, &ssi->sier);
 
 		/*
 		 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
@@ -339,9 +359,9 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		 * make this value larger (and maybe we should), but this way
 		 * data will be written to memory as soon as it's available.
 		 */
-		out_be32(&ssi->sfcsr,
-			CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
-			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2));
+		write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
+			CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2),
+			&ssi->sfcsr);
 
 		/*
 		 * We keep the SSI disabled because if we enable it, then the
@@ -417,7 +437,7 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 	unsigned int sample_size =
 		snd_pcm_format_width(params_format(hw_params));
 	u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
-	int enabled = in_be32(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
+	int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
 
 	/*
 	 * If we're in synchronous mode, and the SSI is already enabled,
@@ -439,9 +459,9 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
 	/* In synchronous mode, the SSI uses STCCR for capture */
 	if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
 	    ssi_private->cpu_dai_drv.symmetric_rates)
-		clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+		write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
 	else
-		clrsetbits_be32(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+		write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
 
 	return 0;
 }
@@ -466,19 +486,19 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-			setbits32(&ssi->scr,
+			write_ssi_mask(&ssi->scr, 0,
 				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
 		else
-			setbits32(&ssi->scr,
+			write_ssi_mask(&ssi->scr, 0,
 				CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
 		break;
 
 	case SNDRV_PCM_TRIGGER_STOP:
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-			clrbits32(&ssi->scr, CCSR_SSI_SCR_TE);
+			write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
 		else
-			clrbits32(&ssi->scr, CCSR_SSI_SCR_RE);
+			write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
 		break;
 
 	default:
@@ -510,7 +530,7 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
 	if (!ssi_private->first_stream) {
 		struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
 
-		clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN);
+		write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
 	}
 }
 
-- 
1.7.5.4



From shawn.guo at linaro.org  Fri Mar 16 04:56:43 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:56:43 +0800
Subject: [PATCH v5 7/8] ASoC: fsl: let fsl_ssi work with imx pcm and machine
 drivers
In-Reply-To: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331888204-27058-8-git-send-email-shawn.guo@linaro.org>

Makes necessary changes on fsl_ssi to let it work with imx pcm and
machine drivers.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 sound/soc/fsl/fsl_ssi.c |   77 ++++++++++++++++++++++++++++++++++++++++++----
 1 files changed, 70 insertions(+), 7 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index db9a734..30ff605 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -28,6 +28,7 @@
 #include <sound/soc.h>
 
 #include "fsl_ssi.h"
+#include "imx-pcm.h"
 
 #ifdef PPC
 #define read_ssi(addr)			 in_be32(addr)
@@ -116,6 +117,12 @@ struct fsl_ssi_private {
 	struct device_attribute dev_attr;
 	struct platform_device *pdev;
 
+	bool new_binding;
+	bool ssi_on_imx;
+	struct platform_device *imx_pcm_pdev;
+	struct imx_pcm_dma_params dma_params_tx;
+	struct imx_pcm_dma_params dma_params_rx;
+
 	struct {
 		unsigned int rfrc;
 		unsigned int tfrc;
@@ -413,6 +420,12 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
 		ssi_private->second_stream = substream;
 	}
 
+	if (ssi_private->ssi_on_imx)
+		snd_soc_dai_set_dma_data(dai, substream,
+			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+				&ssi_private->dma_params_tx :
+				&ssi_private->dma_params_rx);
+
 	return 0;
 }
 
@@ -642,12 +655,6 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 	if (!of_device_is_available(np))
 		return -ENODEV;
 
-	/* Check for a codec-handle property. */
-	if (!of_get_property(np, "codec-handle", NULL)) {
-		dev_err(&pdev->dev, "missing codec-handle property\n");
-		return -ENODEV;
-	}
-
 	/* We only support the SSI in "I2S Slave" mode */
 	sprop = of_get_property(np, "fsl,mode", NULL);
 	if (!sprop || strcmp(sprop, "i2s-slave")) {
@@ -712,6 +719,35 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
                 /* Older 8610 DTs didn't have the fifo-depth property */
 		ssi_private->fifo_depth = 8;
 
+	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
+		u32 dma_events[2];
+		ssi_private->ssi_on_imx = true;
+		/*
+		 * We have burstsize be "fifo_depth - 2" to match the SSI
+		 * watermark setting in fsl_ssi_startup().
+		 */
+		ssi_private->dma_params_tx.burstsize =
+			ssi_private->fifo_depth - 2;
+		ssi_private->dma_params_rx.burstsize =
+			ssi_private->fifo_depth - 2;
+		ssi_private->dma_params_tx.dma_addr =
+			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
+		ssi_private->dma_params_rx.dma_addr =
+			ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
+		/*
+		 * TODO: This is a temporary solution and should be changed
+		 * to use generic DMA binding later when the helplers get in.
+		 */
+		ret = of_property_read_u32_array(pdev->dev.of_node,
+					"fsl,ssi-dma-events", dma_events, 2);
+		if (ret) {
+			dev_err(&pdev->dev, "could not get dma events\n");
+			goto error_irq;
+		}
+		ssi_private->dma_params_tx.dma = dma_events[0];
+		ssi_private->dma_params_rx.dma = dma_events[1];
+	}
+
 	/* Initialize the the device_attribute structure */
 	dev_attr = &ssi_private->dev_attr;
 	sysfs_attr_init(&dev_attr->attr);
@@ -735,6 +771,26 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 		goto error_dev;
 	}
 
+	if (ssi_private->ssi_on_imx) {
+		ssi_private->imx_pcm_pdev =
+			platform_device_register_simple("imx-pcm-audio",
+							-1, NULL, 0);
+		if (IS_ERR(ssi_private->imx_pcm_pdev)) {
+			ret = PTR_ERR(ssi_private->imx_pcm_pdev);
+			goto error_dev;
+		}
+	}
+
+	/*
+	 * If codec-handle property is missing from SSI node, we assume
+	 * that the machine driver uses new binding which does not require
+	 * SSI driver to trigger machine driver's probe.
+	 */
+	if (!of_get_property(np, "codec-handle", NULL)) {
+		ssi_private->new_binding = true;
+		goto done;
+	}
+
 	/* Trigger the machine driver's probe function.  The platform driver
 	 * name of the machine driver is taken from /compatible property of the
 	 * device tree.  We also pass the address of the CPU DAI driver
@@ -756,9 +812,12 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 		goto error_dai;
 	}
 
+done:
 	return 0;
 
 error_dai:
+	if (ssi_private->ssi_on_imx)
+		platform_device_unregister(ssi_private->imx_pcm_pdev);
 	snd_soc_unregister_dai(&pdev->dev);
 
 error_dev:
@@ -784,7 +843,10 @@ static int fsl_ssi_remove(struct platform_device *pdev)
 {
 	struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
 
-	platform_device_unregister(ssi_private->pdev);
+	if (!ssi_private->new_binding)
+		platform_device_unregister(ssi_private->pdev);
+	if (ssi_private->ssi_on_imx)
+		platform_device_unregister(ssi_private->imx_pcm_pdev);
 	snd_soc_unregister_dai(&pdev->dev);
 	device_remove_file(&pdev->dev, &ssi_private->dev_attr);
 
@@ -799,6 +861,7 @@ static int fsl_ssi_remove(struct platform_device *pdev)
 
 static const struct of_device_id fsl_ssi_ids[] = {
 	{ .compatible = "fsl,mpc8610-ssi", },
+	{ .compatible = "fsl,imx21-ssi", },
 	{}
 };
 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
-- 
1.7.5.4



From shawn.guo at linaro.org  Fri Mar 16 04:56:44 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 16:56:44 +0800
Subject: [PATCH v5 8/8] ASoC: fsl: add imx-sgtl5000 machine driver
In-Reply-To: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1331888204-27058-9-git-send-email-shawn.guo@linaro.org>

This is the initial imx-sgtl5000 machine driver support with only
playback dai link implemented.  More features can be added on top
of it later.

It's a device tree only machine driver working with fsl_ssi driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 .../bindings/sound/imx-audio-sgtl5000.txt          |   24 +++
 sound/soc/fsl/Kconfig                              |   12 ++
 sound/soc/fsl/Makefile                             |    2 +
 sound/soc/fsl/imx-sgtl5000.c                       |  177 ++++++++++++++++++++
 4 files changed, 215 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
 create mode 100644 sound/soc/fsl/imx-sgtl5000.c

diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
new file mode 100644
index 0000000..421a374
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
@@ -0,0 +1,24 @@
+Freescale i.MX audio complex with SGTL5000 codec
+
+Required properties:
+- compatible : "fsl,imx-audio-sgtl5000"
+- model : The user-visible name of this sound complex
+- ssi-controller : The phandle of the i.MX SSI controller
+- audio-codec : The phandle of the SGTL5000 audio codec
+- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
+- mux-ext-port : The external port of the i.MX audio muxer
+
+Note: The AUDMUX port numbering should start at 1, which is consistent with
+hardware manual.
+
+Example:
+
+sound {
+	compatible = "fsl,imx51-babbage-sgtl5000",
+		     "fsl,imx-audio-sgtl5000";
+	model = "imx51-babbage-sgtl5000";
+	ssi-controller = <&ssi1>;
+	audio-codec = <&sgtl5000>;
+	mux-int-port = <1>;
+	mux-ext-port = <3>;
+};
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 535ee73..aa14fc9 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -164,4 +164,16 @@ config SND_SOC_EUKREA_TLV320
 	  Enable I2S based access to the TLV320AIC23B codec attached
 	  to the SSI interface
 
+config SND_SOC_IMX_SGTL5000
+	tristate "SoC Audio support for i.MX boards with sgtl5000"
+	depends on OF && I2C
+	select SND_SOC_SGTL5000
+	select SND_SOC_IMX_PCM_DMA
+	select SND_SOC_IMX_AUDMUX
+	select SND_SOC_FSL_SSI
+	select SND_SOC_FSL_UTILS
+	help
+	  Say Y if you want to add support for SoC audio on an i.MX board with
+	  a sgtl5000 codec.
+
 endif # SND_IMX_SOC
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index fbdbed0..638d385 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -40,8 +40,10 @@ snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
 snd-soc-phycore-ac97-objs := phycore-ac97.o
 snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
 snd-soc-wm1133-ev1-objs := wm1133-ev1.o
+snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
 
 obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
 obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
 obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
 obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
+obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
diff --git a/sound/soc/fsl/imx-sgtl5000.c b/sound/soc/fsl/imx-sgtl5000.c
new file mode 100644
index 0000000..3786b61
--- /dev/null
+++ b/sound/soc/fsl/imx-sgtl5000.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <sound/soc.h>
+
+#include "../codecs/sgtl5000.h"
+#include "imx-audmux.h"
+
+#define DAI_NAME_SIZE	32
+
+struct imx_sgtl5000_data {
+	struct snd_soc_dai_link dai;
+	struct snd_soc_card card;
+	char codec_dai_name[DAI_NAME_SIZE];
+	char platform_name[DAI_NAME_SIZE];
+	unsigned int clk_frequency;
+};
+
+static int imx_sgtl5000_dai_init(struct snd_soc_pcm_runtime *rtd)
+{
+	struct imx_sgtl5000_data *data = container_of(rtd->card,
+					struct imx_sgtl5000_data, card);
+	struct device *dev = rtd->card->dev;
+	int ret;
+
+	ret = snd_soc_dai_set_sysclk(rtd->codec_dai, SGTL5000_SYSCLK,
+				     data->clk_frequency, SND_SOC_CLOCK_IN);
+	if (ret) {
+		dev_err(dev, "could not set codec driver clock params\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __devinit imx_sgtl5000_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *ssi_np, *codec_np;
+	struct platform_device *ssi_pdev;
+	struct imx_sgtl5000_data *data;
+	int int_port, ext_port;
+	int ret;
+
+	ret = of_property_read_u32(np, "mux-int-port", &int_port);
+	if (ret) {
+		dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
+		return ret;
+	}
+	ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
+	if (ret) {
+		dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
+		return ret;
+	}
+
+	/*
+	 * The port numbering in the hardware manual starts at 1, while
+	 * the audmux API expects it starts at 0.
+	 */
+	int_port--;
+	ext_port--;
+	ret = imx_audmux_v2_configure_port(int_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
+			IMX_AUDMUX_V2_PTCR_TFSDIR |
+			IMX_AUDMUX_V2_PTCR_TCLKDIR,
+			IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
+	if (ret) {
+		dev_err(&pdev->dev, "audmux internal port setup failed\n");
+		return ret;
+	}
+	imx_audmux_v2_configure_port(ext_port,
+			IMX_AUDMUX_V2_PTCR_SYN |
+			IMX_AUDMUX_V2_PTCR_TCSEL(int_port),
+			IMX_AUDMUX_V2_PDCR_RXDSEL(int_port));
+	if (ret) {
+		dev_err(&pdev->dev, "audmux external port setup failed\n");
+		return ret;
+	}
+
+	ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
+	codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
+	if (!ssi_np || !codec_np) {
+		dev_err(&pdev->dev, "phandle missing or invalid\n");
+		return -EINVAL;
+	}
+
+	ssi_pdev = of_find_device_by_node(ssi_np);
+	if (!ssi_pdev) {
+		dev_err(&pdev->dev, "failed to find SSI platform device\n");
+		return -EINVAL;
+	}
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	ret = of_property_read_u32(codec_np, "clock-frequency",
+				   &data->clk_frequency);
+	if (ret) {
+		dev_err(&pdev->dev, "clock-frequency missing or invalid\n");
+		return ret;
+	}
+
+	data->dai.name = "HiFi";
+	data->dai.stream_name = "HiFi";
+	data->dai.codec_dai_name = "sgtl5000";
+	data->dai.codec_of_node = codec_np;
+	data->dai.cpu_dai_name = dev_name(&ssi_pdev->dev);
+	data->dai.platform_name = "imx-pcm-audio";
+	data->dai.init = &imx_sgtl5000_dai_init;
+	data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+			    SND_SOC_DAIFMT_CBM_CFM;
+
+	data->card.dev = &pdev->dev;
+	ret = snd_soc_of_parse_card_name(&data->card, "model");
+	if (ret)
+		return ret;
+	data->card.num_links = 1;
+	data->card.dai_link = &data->dai;
+
+	ret = snd_soc_register_card(&data->card);
+	if (ret) {
+		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, data);
+	of_node_put(ssi_np);
+	of_node_put(codec_np);
+
+	return 0;
+}
+
+static int __devexit imx_sgtl5000_remove(struct platform_device *pdev)
+{
+	struct imx_sgtl5000_data *data = platform_get_drvdata(pdev);
+
+	snd_soc_unregister_card(&data->card);
+
+	return 0;
+}
+
+static const struct of_device_id imx_sgtl5000_dt_ids[] = {
+	{ .compatible = "fsl,imx-audio-sgtl5000", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_sgtl5000_dt_ids);
+
+static struct platform_driver imx_sgtl5000_driver = {
+	.driver = {
+		.name = "imx-sgtl5000",
+		.owner = THIS_MODULE,
+		.of_match_table = imx_sgtl5000_dt_ids,
+	},
+	.probe = imx_sgtl5000_probe,
+	.remove = __devexit_p(imx_sgtl5000_remove),
+};
+module_platform_driver(imx_sgtl5000_driver);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo at linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX SGTL5000 ASoC machine driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx-sgtl5000");
-- 
1.7.5.4



From linus.walleij at linaro.org  Fri Mar 16 05:01:34 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 16 Mar 2012 10:01:34 +0100
Subject: [PATCH 0/5] MMC: mmci: Provide bindings for Device Tree
In-Reply-To: <201203152058.31398.arnd@arndb.de>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <201203151532.44363.arnd@arndb.de>
 <CAFEEs1=TJaCYmaWd7zd28NsV8ubZBpBn7p=Mi7vGtmV_vpfh1w@mail.gmail.com>
 <201203152058.31398.arnd@arndb.de>
Message-ID: <CACRpkdbyVXA+GxRtVL+JGPorp0ULJmeUEUZPxVxOT8W1-WmeMw@mail.gmail.com>

On Thu, Mar 15, 2012 at 9:58 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> [Per]
>> The stedma40 filter function is not really specific for ux500. ux500
>> use stedma40 but it should be possible to replace this DMA.IP with
>> some other DMA-controller. This is board specific configuration. You
>> should not need to change the mmci-driver just because the dma-driver
>> has changed, right?
>> Or will the board-configuration now be placed in mmci-ux500?
>
> Right, the DMA configuration does not really belong in there, but
> the voltage setup might (unless we convert that to the regulator
> setup).

The voltage to power the card is already using the regulator
framework with the MMC-specific helpers in the MMCI driver.

But I guess you're after modelling the levelshifter as a regulator?

Basically the level shifter is a separate device has two voltage
inputs A and B (from other regulators) that is controlled by a
simple GPIO to select voltage A or B to drive the signals to
the card.

That could probably be modelled as a regulator with two
volategs for sure, but then we should maybe create a more
generic "struct level_shifter_regulator" (or whatever) for the
concept as a whole.

Let's page Mark about what to do with levelshifters and whether
they are regulators of sorts in his book.

Yours,
Linus Walleij


From augulis.darius at gmail.com  Fri Mar 16 05:15:46 2012
From: augulis.darius at gmail.com (Darius Augulis)
Date: Fri, 16 Mar 2012 11:15:46 +0200
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <002d01cd034b$c56f2b00$504d8100$%han@samsung.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com>
 <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
 <001d01cd0315$935cc720$ba165560$%han@samsung.com>
 <CAEYLNCrGCmb5EJjURLY=EGfM=4N54MirNkCCyQRxqKEN3Eka8Q@mail.gmail.com>
 <002d01cd034b$c56f2b00$504d8100$%han@samsung.com>
Message-ID: <CAEYLNCpfQ0cYb4efw6PZNnKjQ2rF25rj5Ed=i884LJXHAwigBw@mail.gmail.com>

On Fri, Mar 16, 2012 at 10:07 AM, Jingoo Han <jg1.han at samsung.com> wrote:
>
>
>> -----Original Message-----
>> From: Darius Augulis [mailto:augulis.darius at gmail.com]
>> Sent: Friday, March 16, 2012 4:47 PM
>> To: Jingoo Han
>> Cc: Thomas Abraham; linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-
>> kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; ben-linux at fluff.org; patches at linaro.org;
>> kgene.kim at samsung.com; Kyungmin Park; JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter
>> Korsgaard; Maurus Cuelenaere; Tushar Behera
>> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
>>
>> On Fri, Mar 16, 2012 at 3:39 AM, Jingoo Han <jg1.han at samsung.com> wrote:
>>
>> it's not a bug, because it's working like it was intended to. it was
>> reviewed and accepted by maintainers before merging to main line.
>> you do not have rights to drop it because you don't like it.
>> You are doing changes - please do it correctly and do not break
>> existing functionality.
>> btw, you still not answered my question: why these two s3c_fb_pd_win
>> structures in mach-mini6410.c is a problem? They are declared on the
>> stack, but platform data uses only single one. mini6410 rewrites its
>> s3c-fb platform data with data from one of these two structures
>> dynamically. Why it's a bug? You want to remove this dynamic selection
>> which could be leaved there with reworked framework too.
>
>
> It's just bug.
>
> struct s3c_fb_pd_win should be used for windows of FIMD IP.
> It should not be used for selecting multi-LCDs.

why not? s3c_fb_pd_win contains timing values which depend directly on
LCD size and resolution.
Please look into the code again - mini6410 doesn't use platform data
so select different LCD sizes.
It has only single window in platform data - exactly what you want.
Now tell my, why you are arguing, that this platform data cannot be
rewritten dynamically by board setup routines at kernel startup time?
Many ARM architectures are doing the same - takes kernel command line
argument to select LCD and passes necessary data for its fb drivers
via platform data structures. It not a bug, it's correct approach to
support different sizes of LCD display for the same board.
You are simply lazy to deal with little bit different code of mini6410
and real6410 because they have support for multiple LCDs and other
s3c-fb boards doesn't.
This is a reason why you want to drop it and not because it's a bug.
Hope other maintainers and code reviewers understand this situation correctly.

>
> struct s3c_fb_pd_win should include information of windows of FIMD IP, s3c_fb_pd_win[0], s3c_fb_pd_win[1] represents window 0,
> window 1 of FIMD IP. However, your code includes information of LCD, it means that struct s3c_fb_pd_win represents 4.3" LCD, 7.0"
> LCD. It is wrong usage.
>
>
>>
>> > 'struct s3c_fb_pd_win' is used not for LCD, but for windows of FIMD IP. So, 'struct s3c_fb_pd_win'
>> should not be used to select LCD.
>> > The mach-aquila.c uses two 'struct s3c_fb_pd_win' like you, however 'struct s3c_fb_pd_win' don't make
>> problem with Thomas's
>> > patchset. It is because mach-aquila.c use 'struct s3c_fb_pd_win' for only windows of FIMD IP.
>> > We don't have to responsibility to keep wrong code. If you have kept the rule, Thomas's patch would
>> not make the compatibility
>> > problem with your code. Why we should keep aberration such as your code? If you want to select two
>> LCDs, please find other way.
>> >
>> >
>> >>
>> >> Darius A.
>> >
>


From Maximilian.Schwerin at tigris.de  Fri Mar 16 05:26:49 2012
From: Maximilian.Schwerin at tigris.de (Maximilian Schwerin)
Date: Fri, 16 Mar 2012 10:26:49 +0100
Subject: AW: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting to
 add IVA OPP
In-Reply-To: <8762e6et1u.fsf@ti.com>
Message-ID: <5448984682E7954C9BFF27F747A9C6CA56D6A8@dolphin.TIGRIS.local>

> Von: Kevin Hilman [mailto:khilman at ti.com] 
> 
> "Menon, Nishanth" <nm at ti.com> writes:
> 
> > On Wed, Mar 14, 2012 at 16:15, Kevin Hilman <khilman at ti.com> wrote:
> >> Maximilian Schwerin <mvs at tigris.de> writes:
> >>
> >>> From: Steve Sakoman <steve at sakoman.com>
> >>>
> >>> Don't try to add IVA OPPs for OMAP3 versions not containing an IVA
> >>> subsystem, as this would make omap_init_opp_table fail.
> >>>
> >>> Signed-off-by: Steve Sakoman <steve at sakoman.com>
> >>> Signed-off-by: Maximilian Schwerin <mvs at tigris.de>
> >>
> >> Minor: patch subjects for arch/arm/* core code need to 
> have the ARM:
> >> prefix also.
> >>
> >> Also, please run scripts/checkpatch.pl on your patch and fix the
> >> warnings.
> >>
> >>> ---
> >>> ?arch/arm/mach-omap2/opp.c | ? ?4 ++++
> >>> ?1 files changed, 4 insertions(+), 0 deletions(-)
> >>>
> >>> diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
> >>> index 9262a6b..414f2ec 100644
> >>> --- a/arch/arm/mach-omap2/opp.c
> >>> +++ b/arch/arm/mach-omap2/opp.c
> >>> @@ -62,6 +62,10 @@ int __init omap_init_opp_table(struct 
> omap_opp_def *opp_def,
> >>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __func__, i);
> >>> ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;
> >>> ? ? ? ? ? ? ? }
> >>> +
> >>> + ? ? ? ? ? ? if ((strcmp(opp_def->hwmod_name,"iva") == 
> 0) && !omap3_has_iva())
> >>> + ? ? ? ? ? ? ? ? ? ? continue;
> >>> +
> >>> ? ? ? ? ? ? ? oh = omap_hwmod_lookup(opp_def->hwmod_name);
> >>> ? ? ? ? ? ? ? if (!oh || !oh->od) {
> >>> ? ? ? ? ? ? ? ? ? ? ? pr_warn("%s: no hwmod or odev for %s, [%d] "
> >>
> >> Wouldn't the one-liner below do the same thing?
> >>
> >> Actually, your patch makes it less noisy at boot time, avoiding the
> >> pr_warn(), so is probably better.
> >
> > The only issue i have with current patch is that it 
> focusses to solve
> > a specific device IVA.
> > we could have similar variances if we had SGX/AESS device etc
> > registered in the common
> > table. a generic solution might be preferable - could we reduce the
> > severity of pr_warn to pr_debug and do a continue instead?
> 
> I agree, that would be a better generic solution.
> 
> Kevin
>

This is a pragmatic and simple solution for a well understood problem with no side effects. Why not fix the problem now and do the generic solution later on? 

I'm not a fulltime kernel dev. I have about two weeks to get my new board out to my customer... Every time I set up a new board, I have to fix problems using known patches that are sometimes years old. Every patch I have to find costs me hours of time I really don't have. 

Just my two cents (euro cents of course :-), Maximilian
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From s.hauer at pengutronix.de  Fri Mar 16 05:27:39 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2012 10:27:39 +0100
Subject: [PATCH 1/3] ARM i.MX: Move i.MX pwm driver to pwm framework
In-Reply-To: <20120316081748.GF7758@S2101-09.ap.freescale.net>
References: <1331802277-12477-1-git-send-email-s.hauer@pengutronix.de>
 <1331802277-12477-2-git-send-email-s.hauer@pengutronix.de>
 <20120316074902.GC7758@S2101-09.ap.freescale.net>
 <20120316080832.GA6458@avionic-0098.mockup.avionic-design.de>
 <20120316081748.GF7758@S2101-09.ap.freescale.net>
Message-ID: <20120316092739.GH3852@pengutronix.de>

On Fri, Mar 16, 2012 at 04:17:51PM +0800, Shawn Guo wrote:
> On Fri, Mar 16, 2012 at 09:08:32AM +0100, Thierry Reding wrote:
> > * Shawn Guo wrote:
> > > On Thu, Mar 15, 2012 at 10:04:35AM +0100, Sascha Hauer wrote:
> > > > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> > > > index e859c51..fc7571e 100644
> > > > --- a/drivers/pwm/Makefile
> > > > +++ b/drivers/pwm/Makefile
> > > > @@ -1,4 +1,5 @@
> > > >  obj-$(CONFIG_PWM)		+= core.o
> > > >  obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
> > > > +obj-$(CONFIG_PWM_IMX)		+= imx-pwm.o
> > > 
> > > s/imx-pwm.o/pwm-imx.o
> > 
> > Yes, I'll make that change when I integrate the patch in my series.
> > 
> Thanks for taking this on.
> 
> > > > @@ -98,7 +98,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
> > > >  		else
> > > >  			cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
> > > >  
> > > > -		writel(cr, pwm->mmio_base + MX3_PWMCR);
> > > > +		writel(cr, imxpwm->mmio_base + MX3_PWMCR);
> > > >  	} else if (cpu_is_mx1() || cpu_is_mx21()) {
> > > 
> > > Since we are here, can we move one step further to get rid of these
> > > cpu_is_xxx()?  Then, we can remove <mach/hardware.h> inclusion from
> > > the driver.
> > 
> > I guess this could be handled by using several names for the driver and
> > handling the differences using a table of platform_device_id:s. Perhaps
> > you had something different in mind?
> > 
> Same thing on my mind.
> 
> > > >  static int __devinit mxc_pwm_probe(struct platform_device *pdev)
> > > 
> > > Should we take this opportunity to rename the driver from mxc_pwm to
> > > imx_pwm?
> > 
> > If we decide to rename maybe it should be done in two steps. First it can be
> > renamed internally and in the second step the name could be changed along
> > with all users. I just want to avoid too much churn in this series, which is
> > already growing way larger than I had hoped.
> > 
> It seems I'm asking too much.  Okay, we can do that after it gets moved.

Indeed. The pwm driver became a horrible piece of code over time, it's
time to refactor it. I just wanted to make the move first, then look for
further cleanups.

Sascha

-- 
Pengutronix e.K.                           |                             |
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From subash.ramaswamy at linaro.org  Fri Mar 16 05:30:41 2012
From: subash.ramaswamy at linaro.org (Subash Patel)
Date: Fri, 16 Mar 2012 15:00:41 +0530
Subject: [PATCH v12 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
In-Reply-To: <4F61FF1D.5000502@samsung.com>
References: <000201cd0286$2e6fbb40$8b4f31c0$%cho@samsung.com>
 <20120315111227.GA2384@amd.com> <4F61FF1D.5000502@samsung.com>
Message-ID: <4F630841.2070307@linaro.org>

Hi KyongHo, Kukjin,

On 03/15/2012 08:09 PM, Kukjin Kim wrote:
> On 03/15/12 04:12, Joerg Roedel wrote:
>> On Thu, Mar 15, 2012 at 05:32:39PM +0900, Cho KyongHo wrote:
>
> KyongHo, I looked at 'Cho KyongHo <pullip.cho ...>' and 'KyongHo Cho 
> <pullip.cho ...>' in this series, which one do you want to use?
>
>>> Handling System MMUs with an identifier is not flexible to manage
>>> System MMU platform devices because of the following reasons:
>>> 1. A device driver which needs to handle System MMU must know the ID.
>>> 2. A System MMU may not present in some implementations of Exynos 
>>> family.
>>> 3. Handling System MMU with IOMMU API does not require an ID.
>>>
>>> This patch is the result of removing ID of System MMUs.
>>> Instead, a device driver that needs to handle its System MMU must
>>> use IOMMU API while its descriptor of platform device is given.
>>>
>>> This patch also includes the following enhancements:
>>> - A System MMU device becomes a child if its power domain device.
>>> - clkdev
>>>
>>> Cc: Kukjin Kim<kgene.kim at samsung.com>
>>> Signed-off-by: KyongHo Cho<pullip.cho at samsung.com>
>>> ---
>>>   arch/arm/mach-exynos/Kconfig                    |   10 +-
>>>   arch/arm/mach-exynos/Makefile                   |    2 +-
>>>   arch/arm/mach-exynos/clock-exynos4.c            |   79 ++--
>>>   arch/arm/mach-exynos/clock-exynos4.h            |    2 +
>>>   arch/arm/mach-exynos/clock-exynos4210.c         |   11 +
>>>   arch/arm/mach-exynos/clock-exynos4212.c         |   28 ++-
>>>   arch/arm/mach-exynos/clock-exynos5.c            |   90 +++++
>>>   arch/arm/mach-exynos/dev-sysmmu.c               |  457 
>>> ++++++++++++----------
>>>   arch/arm/mach-exynos/include/mach/irqs.h        |   25 +-
>>>   arch/arm/mach-exynos/include/mach/map.h         |   38 ++
>>>   arch/arm/mach-exynos/include/mach/regs-clock.h  |    5 +
>>>   arch/arm/mach-exynos/include/mach/regs-sysmmu.h |   28 --
>>>   arch/arm/mach-exynos/include/mach/sysmmu.h      |   88 +++--
>>>   arch/arm/mach-exynos/mach-armlex4210.c          |    1 -
>>>   arch/arm/mach-exynos/mach-smdkv310.c            |    1 -
>>>   15 files changed, 529 insertions(+), 336 deletions(-)
>>>   delete mode 100644 arch/arm/mach-exynos/include/mach/regs-sysmmu.h
>>
>> This patch doesn't apply cleanly against upstream Linux (v3.3-rcX).
>> Please rebase to upstream and resend. The other 2 patches apply fine.
>>
>
> Yes, as KyoungHo said, this has been created on top of Samsung tree 
> for-next because this touches many exynos stuff which has been changed 
> from Samsung tree for upcoming merge window. So if you're ok on this, 
> 1st patch and this should be sent to upstream via samsung tree even 
> though I can't find any topic branch for this yet. And if you want 
> topic branch for your tree, let me know, I can provide it.
>
> Thanks.
Wouldn't it be good to send exynos4 SYSMMU patches now, and send only 
the exynos5 delta when your for-next(exynos5) changes
get merged to mainline? Manually editing the patches is really pain-some 
and sometimes error-some :( Can this patch in particular
be split?
>
> Best regards,
> Kgene.
> -- 
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
Regards,
Subash


From sr at denx.de  Fri Mar 16 05:30:16 2012
From: sr at denx.de (Stefan Roese)
Date: Fri, 16 Mar 2012 10:30:16 +0100
Subject: [PATCH v4] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
Message-ID: <1331890216-8361-1-git-send-email-sr@denx.de>

This patch adds a generic target for SPEAr600 board that can be
configured via the device-tree. Currently the following devices
are supported via the devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
follow in later patches.

Only the spear600-evb is currently supported. Other SPEAr600
based boards will follow later.

Since the current mainline SPEAr600 code only supports the SPEAr600
evaluation board, with nearly zero peripheral devices (only UART
and GPIO), it makes sense to switch over to DT based configuration
completely now. So this patch also removes all non-DT stuff, mainly
platform device data. The files spear600.c and spear600_evb.c are
removed completely.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Viresh Kumar <viresh.kumar at st.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
v4:
- Added memory node to all dts/dtsi files
- Reorganizes bus topology in the dtsi file, to match the
  real SoC layout

v3:
- Removed non-DT SPEAr600 board support completely
- Removed OF_DEV_AUXDATA and changed clkdev instead, since we
  don't support non-DT targets any more
- Changed gmac0 -> gmac etc for single instance devices in the
  dts
- Added max memory size to memory node (instead of 0)
- Dropped mac-address property
- Removed some headers from spear6xx.c

v2:
- Added DT support to spear6xx.c instead of creating board-dt.c
- Removed UART (PL011) and GPIO (PL061) platform data for
  devicetree board port. This works now via DT probing
- Added OF_DEV_AUXDATA for clock device name matching for some
  device drivers
- Removed sper600.c file completely
- Added DW I2C and ethernet nodes to the dts files
- Added other DT nodes (SMI, FSMC, ECHI, OHCI), currently disabled
  since the corresponding device drivers don't support DT probing
- Removed Linaro/FSL copyright notice from SPEAr DT files (copy-paste cruft)
- Many smaller modification to the dts/dtsi files
- Changed Documentation/devicetree/bindings/arm/spear.txt to match
  the changed bindings

 Documentation/devicetree/bindings/arm/spear.txt |    8 ++
 arch/arm/boot/dts/spear600-evb.dts              |   37 +++++
 arch/arm/boot/dts/spear600.dtsi                 |  170 +++++++++++++++++++++++
 arch/arm/mach-spear6xx/Kconfig                  |    7 +-
 arch/arm/mach-spear6xx/Makefile                 |    6 -
 arch/arm/mach-spear6xx/clock.c                  |   14 +-
 arch/arm/mach-spear6xx/spear600.c               |   25 ----
 arch/arm/mach-spear6xx/spear600_evb.c           |   54 -------
 arch/arm/mach-spear6xx/spear6xx.c               |  132 +++++-------------
 9 files changed, 262 insertions(+), 191 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
 create mode 100644 arch/arm/boot/dts/spear600-evb.dts
 create mode 100644 arch/arm/boot/dts/spear600.dtsi
 delete mode 100644 arch/arm/mach-spear6xx/spear600.c
 delete mode 100644 arch/arm/mach-spear6xx/spear600_evb.c

diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
new file mode 100644
index 0000000..f8e54f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -0,0 +1,8 @@
+ST SPEAr Platforms Device Tree Bindings
+---------------------------------------
+
+Boards with the ST SPEAr600 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear600";
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
new file mode 100644
index 0000000..bf706b2
--- /dev/null
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear600.dtsi"
+
+/ {
+	model = "ST SPEAr600 Evaluation Board";
+	compatible = "st,spear600-evb", "st,spear600";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x10000000>;
+	};
+
+	ahb {
+		gmac: ethernet at e0800000 {
+			phy-mode = "gmii";
+		};
+
+		apb {
+			i2c at d0200000 {
+				clock-frequency = <400000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
new file mode 100644
index 0000000..cf14762
--- /dev/null
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "st,spear600";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vic0: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		vic1: interrupt-controller at f1000000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		gmac: ethernet at e0800000 {
+			compatible = "st,spear600-gmac";
+			reg = <0xe0800000 0x8000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <24 23>;
+			interrupt-names = "macirq", "eth_wake_irq";
+		};
+
+		fsmc: flash at d1800000 {
+			status = "disabled";
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd1800000 0x1000	/* FSMC Register */
+			       0xd2000000 0x4000>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x20000>;
+			st,cle-off = <0x10000>;
+		};
+
+		smi: flash at fc000000 {
+			status = "disabled";
+			compatible = "st,spear600-smi";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xfc000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <12>;
+		};
+
+		ehci at e1800000 {
+			status = "disabled";
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe1800000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <27>;
+		};
+
+		ehci at e2000000 {
+			status = "disabled";
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe2000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <29>;
+		};
+
+		ohci at e1900000 {
+			status = "disabled";
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe1900000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <26>;
+		};
+
+		ohci at e2100000 {
+			status = "disabled";
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe2100000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <28>;
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges;
+
+			serial at d0000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0000000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <24>;
+			};
+
+			serial at d0080000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0080000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <25>;
+			};
+
+			/* local/cpu GPIO */
+			gpio0: gpio at f0100000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xf0100000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <18>;
+			};
+
+			/* basic GPIO */
+			gpio1: gpio at fc980000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xfc980000 0x1000>;
+				interrupt-parent = <&vic1>;
+				interrupts = <19>;
+			};
+
+			/* appl GPIO */
+			gpio2: gpio at d8100000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xd8100000 0x1000>;
+				interrupt-parent = <&vic1>;
+				interrupts = <4>;
+			};
+
+			i2c at d0200000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,designware-i2c";
+				reg = <0xd0200000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <28>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
index ff4ae5b..fbe298b 100644
--- a/arch/arm/mach-spear6xx/Kconfig
+++ b/arch/arm/mach-spear6xx/Kconfig
@@ -5,11 +5,12 @@
 if ARCH_SPEAR6XX
 
 menu "SPEAr6xx Implementations"
-config BOARD_SPEAR600_EVB
-	bool "SPEAr600 Evaluation Board"
+config BOARD_SPEAR600_DT
+	bool "SPEAr600 generic board configured via device-tree"
 	select MACH_SPEAR600
+	select USE_OF
 	help
-	  Supports ST SPEAr600 Evaluation Board
+	  Supports ST SPEAr600 boards configured via the device-tree
 
 endmenu
 
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index cc1a4d8..76e5750 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -4,9 +4,3 @@
 
 # common files
 obj-y	+= clock.o spear6xx.o
-
-# spear600 specific files
-obj-$(CONFIG_MACH_SPEAR600) += spear600.o
-
-# spear600 boards files
-obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index ac70e0d..358f280 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -641,8 +641,8 @@ static struct clk_lookup spear_clk_lookups[] = {
 	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
 	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
 	{ .con_id = "gpt3_synth_clk",	.clk = &gpt3_synth_clk},
-	{ .dev_id = "uart0",		.clk = &uart0_clk},
-	{ .dev_id = "uart1",		.clk = &uart1_clk},
+	{ .dev_id = "d0000000.serial",	.clk = &uart0_clk},
+	{ .dev_id = "d0080000.serial",	.clk = &uart1_clk},
 	{ .dev_id = "firda",		.clk = &firda_clk},
 	{ .dev_id = "clcd",		.clk = &clcd_clk},
 	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
@@ -655,20 +655,20 @@ static struct clk_lookup spear_clk_lookups[] = {
 	{ .con_id = "usbh.1_clk",	.clk = &usbh1_clk},
 	/* clock derived from ahb clk */
 	{ .con_id = "apb_clk",		.clk = &apb_clk},
-	{ .dev_id = "i2c_designware.0",	.clk = &i2c_clk},
+	{ .dev_id = "d0200000.i2c",	.clk = &i2c_clk},
 	{ .dev_id = "dma",		.clk = &dma_clk},
 	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
 	{ .dev_id = "gmac",		.clk = &gmac_clk},
 	{ .dev_id = "smi",		.clk = &smi_clk},
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
+	{ .dev_id = "fsmc-nand",	.clk = &fsmc_clk},
 	/* clock derived from apb clk */
 	{ .dev_id = "adc",		.clk = &adc_clk},
 	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
 	{ .dev_id = "ssp-pl022.1",	.clk = &ssp1_clk},
 	{ .dev_id = "ssp-pl022.2",	.clk = &ssp2_clk},
-	{ .dev_id = "gpio0",		.clk = &gpio0_clk},
-	{ .dev_id = "gpio1",		.clk = &gpio1_clk},
-	{ .dev_id = "gpio2",		.clk = &gpio2_clk},
+	{ .dev_id = "f0100000.gpio",	.clk = &gpio0_clk},
+	{ .dev_id = "fc980000.gpio",	.clk = &gpio1_clk},
+	{ .dev_id = "d8100000.gpio",	.clk = &gpio2_clk},
 };
 
 void __init spear6xx_clk_init(void)
diff --git a/arch/arm/mach-spear6xx/spear600.c b/arch/arm/mach-spear6xx/spear600.c
deleted file mode 100644
index d0e6eea..0000000
--- a/arch/arm/mach-spear6xx/spear600.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/spear600.c
- *
- * SPEAr600 machine source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/ptrace.h>
-#include <asm/irq.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* Add spear600 specific devices here */
-
-void __init spear600_init(void)
-{
-	/* call spear6xx family common init function */
-	spear6xx_init();
-}
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
deleted file mode 100644
index c6e4254..0000000
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/spear600_evb.c
- *
- * SPEAr600 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-static struct amba_device *amba_devs[] __initdata = {
-	&gpio_device[0],
-	&gpio_device[1],
-	&gpio_device[2],
-	&uart_device[0],
-	&uart_device[1],
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-};
-
-static void __init spear600_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear600 machine init function */
-	spear600_init();
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear6xx_map_io,
-	.init_irq	=	spear6xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear6xx_timer,
-	.init_machine	=	spear600_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index e0f6628..2ed8b14 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -6,111 +6,21 @@
  * Copyright (C) 2009 ST Microelectronics
  * Rajeev Kumar<rajeev-dlh.kumar at st.com>
  *
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
-#include <mach/irqs.h>
-
-/* Add spear6xx machines common devices here */
-/* uart device registration */
-struct amba_device uart_device[] = {
-	{
-		.dev = {
-			.init_name = "uart0",
-		},
-		.res = {
-			.start = SPEAR6XX_ICM1_UART0_BASE,
-			.end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_UART_0, NO_IRQ},
-	}, {
-		.dev = {
-			.init_name = "uart1",
-		},
-		.res = {
-			.start = SPEAR6XX_ICM1_UART1_BASE,
-			.end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_UART_1, NO_IRQ},
-	}
-};
-
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data[] = {
-	{
-		.gpio_base	= 0,
-		.irq_base	= SPEAR_GPIO0_INT_BASE,
-	}, {
-		.gpio_base	= 8,
-		.irq_base	= SPEAR_GPIO1_INT_BASE,
-	}, {
-		.gpio_base	= 16,
-		.irq_base	= SPEAR_GPIO2_INT_BASE,
-	},
-};
-
-struct amba_device gpio_device[] = {
-	{
-		.dev = {
-			.init_name = "gpio0",
-			.platform_data = &gpio_plat_data[0],
-		},
-		.res = {
-			.start = SPEAR6XX_CPU_GPIO_BASE,
-			.end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_LOCAL_GPIO, NO_IRQ},
-	}, {
-		.dev = {
-			.init_name = "gpio1",
-			.platform_data = &gpio_plat_data[1],
-		},
-		.res = {
-			.start = SPEAR6XX_ICM3_GPIO_BASE,
-			.end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_BASIC_GPIO, NO_IRQ},
-	}, {
-		.dev = {
-			.init_name = "gpio2",
-			.platform_data = &gpio_plat_data[2],
-		},
-		.res = {
-			.start = SPEAR6XX_ICM2_GPIO_BASE,
-			.end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_APPL_GPIO, NO_IRQ},
-	}
-};
-
-/* This will add devices, and do machine specific tasks */
-void __init spear6xx_init(void)
-{
-	/* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear6xx_init_irq(void)
-{
-	vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_PRI_BASE, 0, ~0, 0);
-	vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0, 0);
-}
 
 /* Following will create static virtual/physical mappings */
 static struct map_desc spear6xx_io_desc[] __initdata = {
@@ -181,3 +91,33 @@ static void __init spear6xx_timer_init(void)
 struct sys_timer spear6xx_timer = {
 	.init = spear6xx_timer_init,
 };
+
+static void __init spear600_dt_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *spear600_dt_board_compat[] = {
+	"st,spear600",
+	NULL
+};
+
+static const struct of_device_id vic_of_match[] __initconst = {
+	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ /* Sentinel */ }
+};
+
+static void __init spear6xx_dt_init_irq(void)
+{
+	of_irq_init(vic_of_match);
+}
+
+DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
+	.map_io		=	spear6xx_map_io,
+	.init_irq	=	spear6xx_dt_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear6xx_timer,
+	.init_machine	=	spear600_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear600_dt_board_compat,
+MACHINE_END
-- 
1.7.9.2



From jg1.han at samsung.com  Fri Mar 16 05:48:19 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Fri, 16 Mar 2012 18:48:19 +0900
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <CAEYLNCpfQ0cYb4efw6PZNnKjQ2rF25rj5Ed=i884LJXHAwigBw@mail.gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com> <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
 <001d01cd0315$935cc720$ba165560$%han@samsung.com>
 <CAEYLNCrGCmb5EJjURLY=EGfM=4N54MirNkCCyQRxqKEN3Eka8Q@mail.gmail.com>
 <002d01cd034b$c56f2b00$504d8100$%han@samsung.com>
 <CAEYLNCpfQ0cYb4efw6PZNnKjQ2rF25rj5Ed=i884LJXHAwigBw@mail.gmail.com>
Message-ID: <002f01cd0359$eb718330$c2548990$%han@samsung.com>


> -----Original Message-----
> From: Darius Augulis [mailto:augulis.darius at gmail.com]
> Sent: Friday, March 16, 2012 6:16 PM
> To: Jingoo Han
> Cc: Thomas Abraham; linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-
> kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; ben-linux at fluff.org; patches at linaro.org;
> kgene.kim at samsung.com; Kyungmin Park; JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter
> Korsgaard; Maurus Cuelenaere; Tushar Behera
> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> 
> On Fri, Mar 16, 2012 at 10:07 AM, Jingoo Han <jg1.han at samsung.com> wrote:
> >
> >
> >> -----Original Message-----
> >> From: Darius Augulis [mailto:augulis.darius at gmail.com]
> >> Sent: Friday, March 16, 2012 4:47 PM
> >> To: Jingoo Han
> >> Cc: Thomas Abraham; linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-
> >> kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; ben-linux at fluff.org;
> patches at linaro.org;
> >> kgene.kim at samsung.com; Kyungmin Park; JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter
> >> Korsgaard; Maurus Cuelenaere; Tushar Behera
> >> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> >>
> >> On Fri, Mar 16, 2012 at 3:39 AM, Jingoo Han <jg1.han at samsung.com> wrote:
> >>
> >> it's not a bug, because it's working like it was intended to. it was
> >> reviewed and accepted by maintainers before merging to main line.
> >> you do not have rights to drop it because you don't like it.
> >> You are doing changes - please do it correctly and do not break
> >> existing functionality.
> >> btw, you still not answered my question: why these two s3c_fb_pd_win
> >> structures in mach-mini6410.c is a problem? They are declared on the
> >> stack, but platform data uses only single one. mini6410 rewrites its
> >> s3c-fb platform data with data from one of these two structures
> >> dynamically. Why it's a bug? You want to remove this dynamic selection
> >> which could be leaved there with reworked framework too.
> >
> >
> > It's just bug.
> >
> > struct s3c_fb_pd_win should be used for windows of FIMD IP.
> > It should not be used for selecting multi-LCDs.
> 
> why not? s3c_fb_pd_win contains timing values which depend directly on
> LCD size and resolution.
> Please look into the code again - mini6410 doesn't use platform data
> so select different LCD sizes.
> It has only single window in platform data - exactly what you want.
> Now tell my, why you are arguing, that this platform data cannot be
> rewritten dynamically by board setup routines at kernel startup time?
> Many ARM architectures are doing the same - takes kernel command line
> argument to select LCD and passes necessary data for its fb drivers
> via platform data structures. It not a bug, it's correct approach to
> support different sizes of LCD display for the same board.


Hey, it is not my point.
To take kernel command line is not problem to support multiple LCDs.

My point is that s3c_fb_pd_win should not include variable LCD option.
So, if you want to support multiple LCDs, you should use another variable,
instead of using s3c_fb_pd_win[0] and s3c_fb_pd_win[1] as 4.3" LCD, 7.0" LCD.

You use s3c_fb_pd_win[0], s3c_fb_pd_win[1] as 4.3" LCD, 7.0" LCD.
However, s3c_fb_pd_win[0], s3c_fb_pd_win[1] means the windows of FIMD IP.


> You are simply lazy to deal with little bit different code of mini6410
> and real6410 because they have support for multiple LCDs and other
> s3c-fb boards doesn't.
> This is a reason why you want to drop it and not because it's a bug.
> Hope other maintainers and code reviewers understand this situation correctly.
> 
> >
> > struct s3c_fb_pd_win should include information of windows of FIMD IP, s3c_fb_pd_win[0],
> s3c_fb_pd_win[1] represents window 0,
> > window 1 of FIMD IP. However, your code includes information of LCD, it means that struct
> s3c_fb_pd_win represents 4.3" LCD, 7.0"
> > LCD. It is wrong usage.
> >
> >
> >>
> >> > 'struct s3c_fb_pd_win' is used not for LCD, but for windows of FIMD IP. So, 'struct s3c_fb_pd_win'
> >> should not be used to select LCD.
> >> > The mach-aquila.c uses two 'struct s3c_fb_pd_win' like you, however 'struct s3c_fb_pd_win' don't
> make
> >> problem with Thomas's
> >> > patchset. It is because mach-aquila.c use 'struct s3c_fb_pd_win' for only windows of FIMD IP.
> >> > We don't have to responsibility to keep wrong code. If you have kept the rule, Thomas's patch would
> >> not make the compatibility
> >> > problem with your code. Why we should keep aberration such as your code? If you want to select two
> >> LCDs, please find other way.
> >> >
> >> >
> >> >>
> >> >> Darius A.
> >> >
> >



From viresh.kumar at st.com  Fri Mar 16 05:51:53 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 16 Mar 2012 15:21:53 +0530
Subject: [PATCH v4] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <1331890216-8361-1-git-send-email-sr@denx.de>
References: <1331890216-8361-1-git-send-email-sr@denx.de>
Message-ID: <4F630D39.2090905@st.com>

On 3/16/2012 3:00 PM, Stefan Roese wrote:
> This patch adds a generic target for SPEAr600 board that can be
> configured via the device-tree. Currently the following devices
> are supported via the devicetree:
> 
> - VIC interrupts
> - PL011 UART
> - PL061 GPIO
> - Synopsys DW I2C
> - Synopsys DW ethernet
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Acked-by: Viresh Kumar <viresh.kumar at st.com>

I have one query (as part of my learning of DT) to all DT experts:

> 
> +                       /* local/cpu GPIO */
> +                       gpio0: gpio at f0100000 {
> +                               #gpio-cells = <2>;
> +                               compatible = "arm,pl061", "arm,primecell";
> +                               gpio-controller;
> +                               reg = <0xf0100000 0x1000>;
> +                               interrupt-parent = <&vic0>;
> +                               interrupts = <18>;
> +                       };
> +
> 

Can we add name property here:
				name = "gpio0"

So that we don't need to do below stuff.

> diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
> @@ -641,8 +641,8 @@ static struct clk_lookup spear_clk_lookups[] = {
> -       { .dev_id = "gpio0",            .clk = &gpio0_clk},
> -       { .dev_id = "gpio1",            .clk = &gpio1_clk},
> -       { .dev_id = "gpio2",            .clk = &gpio2_clk},
> +       { .dev_id = "f0100000.gpio",    .clk = &gpio0_clk},
> +       { .dev_id = "fc980000.gpio",    .clk = &gpio1_clk},

I can't find much dts files using this approach. Even i don't know
if setting name will be sufficient?

-- 
viresh


From arnd at arndb.de  Fri Mar 16 05:56:59 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 09:56:59 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120315215537.GB2842@n2100.arm.linux.org.uk>
References: <4F22DEF2.5000807@ti.com> <4F626180.2010902@ti.com>
 <20120315215537.GB2842@n2100.arm.linux.org.uk>
Message-ID: <201203160956.59674.arnd@arndb.de>

On Thursday 15 March 2012, Russell King - ARM Linux wrote:
> Thank you both for missing my point.
> 
> #define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
> #define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
> 
> #define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
> #define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
> 
> #define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
> #define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
> 
> #define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
> #define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
> 
> #define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
> #define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
> #define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
> 
> Notice the overlap between the different SoCs for the same number on the
> same DMA controller.
> 
> This shouldn't cause problems when all users are within the SoC specific
> file, but those EXT ones would probably be platform specific, and so you
> immediately have a dependence between the platform and the SoC there.
> 
> That dependence can be completely eliminated by other matching schemes
> which are supportable via the DMA engine API.

Ok, so I guess you are worried about the case where you have one .dtsi
include file for the soc and another .dtsi file for the platform, and
you want to generically encode e.g. DMA_EXT_DMAREQ3 in the platform file
so you don't need to write a new .dts file for each combination of that
platform wiht a different soc. Does that describe where you see the
issue?

If so, I would recommend not using a flat numbering scheme for omap,
but have something slightly more complex like a lot of the other
dmagenine drivers do. This binding does not make any assumption about
the meaning of the values, so you can do e.g. three cells for
each channel with a definition like this:

Cell 1: channel class
 Possible values are:
 0 -- raw channel number
 1 -- external channel
 2 -- spi
 3 -- i2c
 4 -- mmc
 to be extended when necessary

Cell 2: instance of this channel
 When Cell 1 is zero, this is just the channel number local to the controller,
 for other values it defines the instance, e.g. ext0, ext1, ext2, ...

Cell 3: DMA direction
 The following values are defined:
 0 -- invalid
 1 -- read
 2 -- write
 3 -- read/write

This specific binding for the omap dma would let you put either a simple channel
into the device tree, or have a high-level description in there. On an OMAP243X,
these two would have the same meaning and a user could put either one in there:

	dma-request = <&dmaengine 0 14 1     /* physical channels 14 (read) */
			&dmaengine 0 15 2>;  /*   and 15 (write)  */

	dma-request = <&dmaengine 1 3 1	     /* external DMA 3 (read) and 4 (write) */
			&dmaengine 1 4 2>;


The cell layout above is just a made-up example, you can basically put everything 
in there that you would put into the arguments to the dma match function. I believe
this is not limited to numbers but can also include phandles and strings. The mapping
from dma classes to physical channels could either be hardcoded in the source for
the dmaengine driver, or get passed in properties of the dmaengine's device_node.

A completely different way to get around the same problem is to define a tree
of virtual dmaengine device nodes, still within the same binding:


	dmaengine-phys: dmaengine {
		compatible = "ti,omap2430-dmaengine", "ti,omap2-dmaengine";
		reg = <0x4a056000 0x1000>;
		#address-cells = <1>; /* physical dma channel number space */		
		#size-cells = <0>;
		#dma-cells = 1;

		dmaengine-ext: dmaengine at 2 {
			ranges = <0 2>, <1 3>, <2 7>, <3 14>, <4 25>,
				<5 25> <6 64>;
			#dma-cells = 1;
		};
	};

This way, a device driver could either refer to the physical dmaengine device
and pass
a physical number like

	dma-requests = <&dmaengine-phys 14>;

or to the same effect refer to a child of node of that engine passing a
local number like

	dma-requests = <&dmaengine-ext 3>;

The dmaengine driver in this case can simply use of_translate_address() to
get from channel 3 to 14 using the ranges in the child dmaengine device node.

	Arnd


From kgene.kim at samsung.com  Fri Mar 16 06:00:09 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 16 Mar 2012 03:00:09 -0700
Subject: linux-next: manual merge of the arm-soc tree with the s5p tree
In-Reply-To: <201203160826.36287.arnd@arndb.de>
References: <20120316174546.5121be30a86c2937579bd3f5@canb.auug.org.au>
 <201203160826.36287.arnd@arndb.de>
Message-ID: <4F630F29.6020101@samsung.com>

On 03/16/12 01:26, Arnd Bergmann wrote:
> On Friday 16 March 2012, Stephen Rothwell wrote:
>> Today's linux-next merge of the arm-soc tree got a conflict in
>> arch/arm/mach-exynos/common.c between commit 1d7233ac478a ("Merge branch
>> 'next/soc-exynos5250-arch-gpio' into for-next") from the s5p tree and
>> commit 853a0231e057 ("Merge branch 'samsung/soc' into next/soc2") from
>> the arm-soc tree.
>>
>> These merge commits both looks suspect, but I fixed it up as best I could
>> (see below).
>
Thank you, Stehpen.

> Right, both the arm-soc and the s5p tree merge the same commits and
> come to different results. Kgene, please have a look and let me know
> which of the three solutions is correct.
>

Yeah, my resolution is missing and both looks OK to me, actually it's 
just different the position of declaration for 'int ret' and I'm not 
sure which one is better even though I fixed with Arnd's resolution.

Arnd, Stephen, thanks :)

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From arnd at arndb.de  Fri Mar 16 06:03:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 10:03:01 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <201203161003.02163.arnd@arndb.de>

On Thursday 15 March 2012, Nicolas Ferre wrote:
> For legacy reason another API will export the DMA request number into a
> Linux resource of type IORESOURCE_DMA.

Can you explain which legacy scenarios you think this is going to help with?

> +/**
> + * of_dma_to_resource - Decode a node's DMA and return it as a resource
> + * @dev: pointer to device tree node
> + * @index: zero-based index of the DMA request
> + * @r: pointer to resource structure to return result into.
> + *
> + * Using a resource to export a DMA request number to a driver should
> + * be used only for legacy purpose and on system when only one DMA controller
> + * is present.
> + * The proper and only scalable way is to use the native of_get_dma_request API
> + * in order retrieve both the DMA controller device node and the DMA request
> + * line for that controller.
> + */
> +int of_dma_to_resource(struct device_node *dev, int index, struct resource *r)
> +{

I think a better way to discourage the use of IORESOURCE_DMA is to not provide
this function at all, especially given that it's not really well-defined what
it will do when you have more than one cell for the dma channel identifier or
when you have multiple DMA engines, so any driver relying on it is inherently
nonportable.

	Arnd


From tpiepho at gmail.com  Fri Mar 16 06:16:13 2012
From: tpiepho at gmail.com (Trent Piepho)
Date: Fri, 16 Mar 2012 06:16:13 -0400
Subject: [alsa-devel] [PATCH v5 8/8] ASoC: fsl: add imx-sgtl5000 machine
 driver
In-Reply-To: <1331888204-27058-9-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-9-git-send-email-shawn.guo@linaro.org>
Message-ID: <CA+7tXihmfBQCgvuY0rx5v4w-bcwYK+7kP9v29w36N-Rc9KSQ+A@mail.gmail.com>

On Fri, Mar 16, 2012 at 4:56 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> +Required properties:
> +- compatible : "fsl,imx-audio-sgtl5000"
> +- model : The user-visible name of this sound complex
> +- ssi-controller : The phandle of the i.MX SSI controller
> +- audio-codec : The phandle of the SGTL5000 audio codec
> +- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
> +- mux-ext-port : The external port of the i.MX audio muxer
> +
> +Note: The AUDMUX port numbering should start at 1, which is consistent with
> +hardware manual.
> +
> +Example:
> +
> +sound {
> + ? ? ? compatible = "fsl,imx51-babbage-sgtl5000",
> + ? ? ? ? ? ? ? ? ? ?"fsl,imx-audio-sgtl5000";
> + ? ? ? model = "imx51-babbage-sgtl5000";
> + ? ? ? ssi-controller = <&ssi1>;
> + ? ? ? audio-codec = <&sgtl5000>;
> + ? ? ? mux-int-port = <1>;
> + ? ? ? mux-ext-port = <3>;
> +};

What would the device node look like for the ESAI controller?  I've
got a board here based on an iMX53 with two of three SSI controllers
and the ESAI controller in use.  It used the nullcodec codec driver
for SSI and ESAI.  The ESAI driver was since replaced with an entirely
new custom driver that doesn't use ASoC at all.  But ignoring that
detail, what would the sound node(s) look like for some hardware that
isn't so simple?  It seems like there would be three sound nodes, but
what would compatible and model be set to?  I'm having a hard time
seeing how "fsl,imx-audio-sgtl5000" would be changed into something
for either SSI or ESAI.


From augulis.darius at gmail.com  Fri Mar 16 06:18:30 2012
From: augulis.darius at gmail.com (Darius Augulis)
Date: Fri, 16 Mar 2012 12:18:30 +0200
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <002f01cd0359$eb718330$c2548990$%han@samsung.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com>
 <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
 <001d01cd0315$935cc720$ba165560$%han@samsung.com>
 <CAEYLNCrGCmb5EJjURLY=EGfM=4N54MirNkCCyQRxqKEN3Eka8Q@mail.gmail.com>
 <002d01cd034b$c56f2b00$504d8100$%han@samsung.com>
 <CAEYLNCpfQ0cYb4efw6PZNnKjQ2rF25rj5Ed=i884LJXHAwigBw@mail.gmail.com>
 <002f01cd0359$eb718330$c2548990$%han@samsung.com>
Message-ID: <CAEYLNCpJU_5uVa-jo5HUNY8Av6eYaiow1gEZtHCiQZ5oKkGoMQ@mail.gmail.com>

On Fri, Mar 16, 2012 at 11:48 AM, Jingoo Han <jg1.han at samsung.com> wrote:
>> > It's just bug.
>> >
>> > struct s3c_fb_pd_win should be used for windows of FIMD IP.
>> > It should not be used for selecting multi-LCDs.
>>
>> why not? s3c_fb_pd_win contains timing values which depend directly on
>> LCD size and resolution.
>> Please look into the code again - mini6410 doesn't use platform data
>> so select different LCD sizes.
>> It has only single window in platform data - exactly what you want.
>> Now tell my, why you are arguing, that this platform data cannot be
>> rewritten dynamically by board setup routines at kernel startup time?
>> Many ARM architectures are doing the same - takes kernel command line
>> argument to select LCD and passes necessary data for its fb drivers
>> via platform data structures. It not a bug, it's correct approach to
>> support different sizes of LCD display for the same board.
>
>
> Hey, it is not my point.
> To take kernel command line is not problem to support multiple LCDs.
>
> My point is that s3c_fb_pd_win should not include variable LCD option.
> So, if you want to support multiple LCDs, you should use another variable,
> instead of using s3c_fb_pd_win[0] and s3c_fb_pd_win[1] as 4.3" LCD, 7.0" LCD.

But I use s3c_fb_pd_win only as container to hold timing values in
board setup code.
s3c-fb platform data has only single window and does not perform any
LCD selection.
What is wrong here? You suggest to declare some custom structure to
hold these timing values? What's the point?

>
> You use s3c_fb_pd_win[0], s3c_fb_pd_win[1] as 4.3" LCD, 7.0" LCD.
> However, s3c_fb_pd_win[0], s3c_fb_pd_win[1] means the windows of FIMD IP.

There is no multiple windows in platform data! driver sees only single
window. And this wont change in any way if you drop LCD selection from
board setup code.
Driver will see the same single window. So - your are arguing, that
board setup code sets platform data in bad way. I don't accept your
opinion, because tens of boards are doing the same and nobody call it
bug.

>


From tglx at linutronix.de  Fri Mar 16 06:29:49 2012
From: tglx at linutronix.de (Thomas Gleixner)
Date: Fri, 16 Mar 2012 11:29:49 +0100 (CET)
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <CACRpkdbXq7zX_XrvAOJc7U6=T0Aaoq+U9_GmZS4fVmVd_arC7A@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-2-git-send-email-mturquette@linaro.org>
 <CACRpkdbXq7zX_XrvAOJc7U6=T0Aaoq+U9_GmZS4fVmVd_arC7A@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1203161129010.2466@ionos>

On Fri, 16 Mar 2012, Linus Walleij wrote:

> On Fri, Mar 16, 2012 at 7:11 AM, Mike Turquette <mturquette at linaro.org> wrote:
> 
> > Provide documentation for the common clk structures and APIs. ?This code
> > can be found in drivers/clk/ and include/linux/clk*.h.
> 
> Acked-by: Linus Wallej <linus.walleij at linaro.org>
> For this three-piece v7 patchset.
> 
> It already does magnitudes more advanced stuff than what I need
> so I'm pretty pleased, any remaining details can surely be ironed out
> in-tree.

Ack. We really need to get that in now and sort out the details in
tree otherwise we will never finish that thing.

Thanks,

	tglx

From s.hauer at pengutronix.de  Fri Mar 16 06:57:09 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 16 Mar 2012 11:57:09 +0100
Subject: [PATCH v7 0/3] common clk framework
In-Reply-To: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
Message-ID: <20120316105709.GC29317@pengutronix.de>

On Thu, Mar 15, 2012 at 11:11:17PM -0700, Mike Turquette wrote:
> The common clock framework defines a common struct clk as well as an
> implementation of the clk api that unifies clock operations on various
> platforms and devices.
> 
> The net result is consolidation of many different struct clk definitions
> and platform-specific clock framework implementations.
> 
> This series is the feature freeze for the common clock framework.
> Unless any major bugs are reported this should be the final version of
> this patchset.  Now is the time to add any acked-by's, reviewed-by's or
> tested-by's.  I've carried over the *-by's from v6; I hope everyone is
> OK with that.

Nice work, thanks again Mike. I gave it a test on various i.MX SoCs and
I can give you my:

Tested-by: Sascha Hauer <s.hauer at pengutronix.de>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From dave.martin at linaro.org  Fri Mar 16 06:59:41 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Fri, 16 Mar 2012 10:59:41 +0000
Subject: [PATCH 2/4] ARM: opcodes: Make opcode byteswapping macros
 assembly-compatible
In-Reply-To: <alpine.LFD.2.02.1203151351180.24151@xanadu.home>
References: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
 <1331829132-9762-3-git-send-email-dave.martin@linaro.org>
 <alpine.LFD.2.02.1203151351180.24151@xanadu.home>
Message-ID: <20120316105928.GA2017@linaro.org>

On Thu, Mar 15, 2012 at 01:53:20PM -0400, Nicolas Pitre wrote:
> On Thu, 15 Mar 2012, Dave Martin wrote:
> 
> > Most of the existing macros don't work with assembler, due to the
> > use of type casts and C functions from <linux/swab.h>.
> > 
> > This patch abstracts out those operations and provides simple
> > explicit versions for use in assembly code.
> > 
> > __opcode_is_thumb32() and __opcode_is_thumb16() are also converted
> > to do bitmask-based testing to avoid confusion if these are used in
> > assembly code (the assembler typically treats all arithmetic values
> > as signed).
> > 
> > Signed-off-by: Dave Martin <dave.martin at linaro.org>
> 
> OK.  One really has to read through the whole series to see the point of 
> this.

That's a fair comment -- I'll try to add a bit more clarification with
reference to the other patches.

The real reason for this is that the C preprocessor doesn't resolve
arithmetic expressions, so if we stringify them into inline asm, the
whole expressions just get dumped out to the assembler without getting
evaluated first.  Which means that we need the expressions in a form
which the assembler can evaluate too.

I see you understood that -- but as you say, it's non-obvious.
 
(This can be avoided by using an "i" constraint to pass those numbers
to the inline asm.  I had a local series which did things that way, but
it makes the macros very awkward to use, since you need some macros
to show where in the inline asm to insert the instructions, and different
macros to pass the correct constraints.)

> Acked-by: Nicolas Pitre <nico at linaro.org>

Thanks
---Dave

> 
> 
> 
> > ---
> >  arch/arm/include/asm/opcodes.h |   97 +++++++++++++++++++++++++++++++++------
> >  1 files changed, 82 insertions(+), 15 deletions(-)
> > 
> > diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
> > index cf877c8..32730a8 100644
> > --- a/arch/arm/include/asm/opcodes.h
> > +++ b/arch/arm/include/asm/opcodes.h
> > @@ -19,6 +19,33 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
> >  
> >  
> >  /*
> > + * Assembler opcode byteswap helpers.
> > + * These are only intended for use by this header: don't use them directly,
> > + * because they will be suboptimal in most cases.
> > + */
> > +#define ___asm_opcode_swab32(x) (	\
> > +	  (((x) << 24) & 0xFF000000)	\
> > +	| (((x) <<  8) & 0x00FF0000)	\
> > +	| (((x) >>  8) & 0x0000FF00)	\
> > +	| (((x) >> 24) & 0x000000FF)	\
> > +)
> > +#define ___asm_opcode_swab16(x) (	\
> > +	  (((x) << 8) & 0xFF00)		\
> > +	| (((x) >> 8) & 0x00FF)		\
> > +)
> > +#define ___asm_opcode_swahb32(x) (	\
> > +	  (((x) << 8) & 0xFF00FF00)	\
> > +	| (((x) >> 8) & 0x00FF00FF)	\
> > +)
> > +#define ___asm_opcode_swahw32(x) (	\
> > +	  (((x) << 16) & 0xFFFF0000)	\
> > +	| (((x) >> 16) & 0x0000FFFF)	\
> > +)
> > +#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
> > +#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
> > +
> > +
> > +/*
> >   * Opcode byteswap helpers
> >   *
> >   * These macros help with converting instructions between a canonical integer
> > @@ -41,30 +68,58 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
> >   * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
> >   * represent any valid Thumb-2 instruction.  For this range,
> >   * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
> > + *
> > + * The ___asm variants are intended only for use by this header, in situations
> > + * involving inline assembler.  For .S files, the normal __opcode_*() macros
> > + * should do the right thing.
> >   */
> > +#ifdef __ASSEMBLY__
> >  
> > -#ifndef __ASSEMBLY__
> > +#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
> > +#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
> > +#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
> > +#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
> > +#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
> > +#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
> > +
> > +#else /* ! __ASSEMBLY__ */
> >  
> >  #include <linux/types.h>
> >  #include <linux/swab.h>
> >  
> > +#define ___opcode_swab32(x) swab32(x)
> > +#define ___opcode_swab16(x) swab16(x)
> > +#define ___opcode_swahb32(x) swahb32(x)
> > +#define ___opcode_swahw32(x) swahw32(x)
> > +#define ___opcode_identity32(x) ((u32)(x))
> > +#define ___opcode_identity16(x) ((u16)(x))
> > +
> > +#endif /* ! __ASSEMBLY__ */
> > +
> > +
> >  #ifdef CONFIG_CPU_ENDIAN_BE8
> >  
> > -#define __opcode_to_mem_arm(x) swab32(x)
> > -#define __opcode_to_mem_thumb16(x) swab16(x)
> > -#define __opcode_to_mem_thumb32(x) swahb32(x)
> > +#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
> > +#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
> > +#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
> > +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
> > +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
> > +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
> >  
> >  #else /* ! CONFIG_CPU_ENDIAN_BE8 */
> >  
> > -#define __opcode_to_mem_arm(x) ((u32)(x))
> > -#define __opcode_to_mem_thumb16(x) ((u16)(x))
> > +#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
> > +#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
> > +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
> > +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
> >  #ifndef CONFIG_CPU_ENDIAN_BE32
> >  /*
> >   * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
> >   * work in all cases, due to alignment constraints.  For now, a correct
> >   * version is not proivided for BE32.
> >   */
> > -#define __opcode_to_mem_thumb32(x) swahw32(x)
> > +#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
> > +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
> >  #endif
> >  
> >  #endif /* ! CONFIG_CPU_ENDIAN_BE8 */
> > @@ -78,15 +133,27 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
> >  /* Operations specific to Thumb opcodes */
> >  
> >  /* Instruction size checks: */
> > -#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL)
> > -#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL)
> > +#define __opcode_is_thumb32(x) (		\
> > +	   ((x) & 0xF8000000) == 0xE8000000	\
> > +	|| ((x) & 0xF0000000) == 0xF0000000	\
> > +)
> > +#define __opcode_is_thumb16(x) (					\
> > +	   ((x) & 0xFFFF0000) == 0					\
> > +	&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)	\
> > +)
> >  
> >  /* Operations to construct or split 32-bit Thumb instructions: */
> > -#define __opcode_thumb32_first(x) ((u16)((x) >> 16))
> > -#define __opcode_thumb32_second(x) ((u16)(x))
> > -#define __opcode_thumb32_compose(first, second) \
> > -	(((u32)(u16)(first) << 16) | (u32)(u16)(second))
> > -
> > -#endif /* __ASSEMBLY__ */
> > +#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
> > +#define __opcode_thumb32_second(x) (___opcode_identity16(x))
> > +#define __opcode_thumb32_compose(first, second) (			\
> > +	  (___opcode_identity32(___opcode_identity16(first)) << 16)	\
> > +	| ___opcode_identity32(___opcode_identity16(second))		\
> > +)
> > +#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
> > +#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
> > +#define ___asm_opcode_thumb32_compose(first, second) (			    \
> > +	  (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
> > +	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
> > +)
> >  
> >  #endif /* __ASM_ARM_OPCODES_H */
> > -- 
> > 1.7.4.1
> > 
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > 


From dave.martin at linaro.org  Fri Mar 16 07:04:23 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Fri, 16 Mar 2012 11:04:23 +0000
Subject: [PATCH 4/4] ARM: opcodes: Opcode definitions for the
 Virtualization Extensions
In-Reply-To: <alpine.LFD.2.02.1203151355570.24151@xanadu.home>
References: <1331829132-9762-1-git-send-email-dave.martin@linaro.org>
 <1331829132-9762-5-git-send-email-dave.martin@linaro.org>
 <alpine.LFD.2.02.1203151355570.24151@xanadu.home>
Message-ID: <20120316110423.GB2017@linaro.org>

On Thu, Mar 15, 2012 at 01:58:28PM -0400, Nicolas Pitre wrote:
> On Thu, 15 Mar 2012, Dave Martin wrote:
> 
> > For now, this patch just adds a definition for the HVC instruction.
> > More can be added here later, as needed.
> > 
> > Now that we have a real example of how to use the opcode injection
> > macros properly, this patch also adds a cross-reference from the
> > explanation in opcodes.h (since without an example, figuring out
> > how to use the macros is not that easy).
> > 
> > Signed-off-by: Dave Martin <dave.martin at linaro.org>
> 
> Acked-by: Nicolas Pitre <nico at linaro.org>
> 
> Maybe this would be a good idea to document in one of the patch logs why 
> you didn't go with the assembler macro route like it is done in 
> unified.h for the various it instructions.

Yes, that's a good idea.  I'll add a brief note somewhere -- probably on
the previous patch.

Cheers
---Dave

> 
> > ---
> >  arch/arm/include/asm/opcodes-virt.h |   29 +++++++++++++++++++++++++++++
> >  arch/arm/include/asm/opcodes.h      |    2 ++
> >  2 files changed, 31 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/include/asm/opcodes-virt.h
> > 
> > diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
> > new file mode 100644
> > index 0000000..b85665a
> > --- /dev/null
> > +++ b/arch/arm/include/asm/opcodes-virt.h
> > @@ -0,0 +1,29 @@
> > +/*
> > + * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
> > + * Copyright (C) 2012  Linaro Limited
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along
> > + * with this program; if not, write to the Free Software Foundation, Inc.,
> > + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> > + */
> > +#ifndef __ASM_ARM_OPCODES_VIRT_H
> > +#define __ASM_ARM_OPCODES_VIRT_H
> > +
> > +#include <asm/opcodes.h>
> > +
> > +#define __HVC(imm16) __inst_arm_thumb32(				\
> > +	0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),	\
> > +	0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)	\
> > +)
> > +
> > +#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
> > diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
> > index 50ef0be..89ff5b9 100644
> > --- a/arch/arm/include/asm/opcodes.h
> > +++ b/arch/arm/include/asm/opcodes.h
> > @@ -193,6 +193,8 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
> >   * specify the ARM and Thumb alternatives at the same time.  This ensures
> >   * that the correct opcode gets emitted depending on the instruction set
> >   * used for the kernel build.
> > + *
> > + * Look at opcodes-virt.h for an example of how to use these macros.
> >   */
> >  #include <linux/stringify.h>
> >  
> > -- 
> > 1.7.4.1
> > 
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> > 


From amit.kucheria at linaro.org  Fri Mar 16 07:14:20 2012
From: amit.kucheria at linaro.org (Amit Kucheria)
Date: Fri, 16 Mar 2012 13:14:20 +0200
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <alpine.LFD.2.02.1203161129010.2466@ionos>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-2-git-send-email-mturquette@linaro.org>
 <CACRpkdbXq7zX_XrvAOJc7U6=T0Aaoq+U9_GmZS4fVmVd_arC7A@mail.gmail.com>
 <alpine.LFD.2.02.1203161129010.2466@ionos>
Message-ID: <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>

On Fri, Mar 16, 2012 at 12:29 PM, Thomas Gleixner <tglx at linutronix.de> wrote:
> On Fri, 16 Mar 2012, Linus Walleij wrote:
>
>> On Fri, Mar 16, 2012 at 7:11 AM, Mike Turquette <mturquette at linaro.org> wrote:
>>
>> > Provide documentation for the common clk structures and APIs. ?This code
>> > can be found in drivers/clk/ and include/linux/clk*.h.
>>
>> Acked-by: Linus Wallej <linus.walleij at linaro.org>
>> For this three-piece v7 patchset.
>>
>> It already does magnitudes more advanced stuff than what I need
>> so I'm pretty pleased, any remaining details can surely be ironed out
>> in-tree.
>
> Ack. We really need to get that in now and sort out the details in
> tree otherwise we will never finish that thing.
>

Thomas, Russell, Arnd,

Can we shoe-horn this thing into 3.4 (it is a bit late, i know) so
that platform ports can gather speed? Several people are waiting for a
somewhat stable version before starting their ports.

And what is the path into mainline - will Russell carry it or Arnd
(with Russell's blessing)?

Regards,
Amit


From shawn.guo at linaro.org  Fri Mar 16 07:18:18 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 19:18:18 +0800
Subject: [alsa-devel] [PATCH v5 8/8] ASoC: fsl: add imx-sgtl5000 machine
 driver
In-Reply-To: <CA+7tXihmfBQCgvuY0rx5v4w-bcwYK+7kP9v29w36N-Rc9KSQ+A@mail.gmail.com>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-9-git-send-email-shawn.guo@linaro.org>
 <CA+7tXihmfBQCgvuY0rx5v4w-bcwYK+7kP9v29w36N-Rc9KSQ+A@mail.gmail.com>
Message-ID: <20120316111814.GA7860@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 06:16:13AM -0400, Trent Piepho wrote:
> On Fri, Mar 16, 2012 at 4:56 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> > +Required properties:
> > +- compatible : "fsl,imx-audio-sgtl5000"
> > +- model : The user-visible name of this sound complex
> > +- ssi-controller : The phandle of the i.MX SSI controller
> > +- audio-codec : The phandle of the SGTL5000 audio codec
> > +- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
> > +- mux-ext-port : The external port of the i.MX audio muxer
> > +
> > +Note: The AUDMUX port numbering should start at 1, which is consistent with
> > +hardware manual.
> > +
> > +Example:
> > +
> > +sound {
> > + ? ? ? compatible = "fsl,imx51-babbage-sgtl5000",
> > + ? ? ? ? ? ? ? ? ? ?"fsl,imx-audio-sgtl5000";
> > + ? ? ? model = "imx51-babbage-sgtl5000";
> > + ? ? ? ssi-controller = <&ssi1>;
> > + ? ? ? audio-codec = <&sgtl5000>;
> > + ? ? ? mux-int-port = <1>;
> > + ? ? ? mux-ext-port = <3>;
> > +};
> 
> What would the device node look like for the ESAI controller?  I've
> got a board here based on an iMX53 with two of three SSI controllers
> and the ESAI controller in use.  It used the nullcodec codec driver
> for SSI and ESAI.  The ESAI driver was since replaced with an entirely
> new custom driver that doesn't use ASoC at all.  But ignoring that
> detail, what would the sound node(s) look like for some hardware that
> isn't so simple?  It seems like there would be three sound nodes, but
> what would compatible and model be set to?  I'm having a hard time
> seeing how "fsl,imx-audio-sgtl5000" would be changed into something
> for either SSI or ESAI.

Maybe having "fsl,imx-audio-xxx" for machine drivers backed by SSI,
and "fsl,imx-esai-audio-xxx" for the ones backed by ESAI?

-- 
Regards,
Shawn


From b-cousson at ti.com  Fri Mar 16 07:19:55 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Fri, 16 Mar 2012 12:19:55 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203161003.02163.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <201203161003.02163.arnd@arndb.de>
Message-ID: <4F6321DB.50600@ti.com>

On 3/16/2012 11:03 AM, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Nicolas Ferre wrote:
>> For legacy reason another API will export the DMA request number into a
>> Linux resource of type IORESOURCE_DMA.
>
> Can you explain which legacy scenarios you think this is going to help with?

We do have a bunch of drivers that are using IORESOURCE_DMA today to 
retrieve the DMA request. Since we do have an unique DMA controller it 
was easy and convenient.
And it seems that other ARM SoCs are using it for the same purpose. 
There are at least 230+ IORESOURCE_DMA instances in the kernel today.

>> +/**
>> + * of_dma_to_resource - Decode a node's DMA and return it as a resource
>> + * @dev: pointer to device tree node
>> + * @index: zero-based index of the DMA request
>> + * @r: pointer to resource structure to return result into.
>> + *
>> + * Using a resource to export a DMA request number to a driver should
>> + * be used only for legacy purpose and on system when only one DMA controller
>> + * is present.
>> + * The proper and only scalable way is to use the native of_get_dma_request API
>> + * in order retrieve both the DMA controller device node and the DMA request
>> + * line for that controller.
>> + */
>> +int of_dma_to_resource(struct device_node *dev, int index, struct resource *r)
>> +{
>
> I think a better way to discourage the use of IORESOURCE_DMA is to not provide
> this function at all, especially given that it's not really well-defined what
> it will do when you have more than one cell for the dma channel identifier or
> when you have multiple DMA engines, so any driver relying on it is inherently
> nonportable.

For the moment it is still used in a lot of places, and without any 
other better API yet, it is still useful. As written it is there only 
for simple single DMA controller case.

By maintaining that IORESOURCE_DMA for the moment we can adapt some 
driver to DT without having to change the way they are retrieving 
information. By using IORESOURCE_IRQ and IORESOURCE_MEM, we had the same 
advantage.

Otherwise how are we supposed to get the DMA channel for non-DT boot 
until we have migrated everything to DT? A bunch of ARM SoC are using 
IORESOURCE_DMA for the same purpose.

The goal here is really to maintain that during the transition phase 
only. As soon as the full DT support is there, we can switch to the of_ API.

Ideally, we should define and use a generic API non dependent of DT. 
AFAIK, that does not exist so far.
And since most drivers are not using dmaengine, we do not even have a 
common DMA fmwk to define an API on top.

I fully agree that this IORESOURCE_DMA is not scalable for multiple 
controller, ugly, and must be avoided like the plague.
But what other options do we have during the transition?

Regards,
Benoit


From ts.srikanth at samsung.com  Fri Mar 16 07:41:22 2012
From: ts.srikanth at samsung.com (Srikanth TS)
Date: Fri, 16 Mar 2012 20:41:22 +0900
Subject: Link for the latest patches of AHCI
Message-ID: <005f01cd0369$b636b360$22a41a20$%srikanth@samsung.com>

Hi All,

I am using AHCI for testing my SATA device.

I tried to clone from below link as mentioned in the MAINTAINERS file for drivers/ata/.
http://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev.git

But This link does not exist.

Can someone please tell me where can I find the latest merged patches, which are still not in official kernel version?

Regards,
Srikanth.



From rui.p.m.sousa at gmail.com  Fri Mar 16 07:44:22 2012
From: rui.p.m.sousa at gmail.com (Rui Sousa)
Date: Fri, 16 Mar 2012 12:44:22 +0100
Subject: spinlock_t and tagged memory block size
Message-ID: <CABcrWnUQ_4-nrZkt_zw5VC=cYJBfmaPsU7ktjMf2=xk7+=PArQ@mail.gmail.com>

Hi,

Cortex-A9 architecture defines the minimum size of tagged memory block
(used on load/store exclusives) to be 2^3 = 8bytes (Cortex A9 r2p2,
Technical Reference Manual, page 4-8).
However, the spinlock_t structure size (if preemption and spinlock
debug options are all disabled) is only 4bytes.
AFAICS, this will break spinlocks if two spinlocks are linked next to
each other. Am I right, or did I miss something?

Br,
Rui


From plagnioj at jcrosoft.com  Fri Mar 16 07:50:22 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 16 Mar 2012 12:50:22 +0100
Subject: [PATCH v4] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <1331890216-8361-1-git-send-email-sr@denx.de>
References: <1331890216-8361-1-git-send-email-sr@denx.de>
Message-ID: <20120316115022.GF7757@game.jcrosoft.org>

On 10:30 Fri 16 Mar     , Stefan Roese wrote:
> This patch adds a generic target for SPEAr600 board that can be
> configured via the device-tree. Currently the following devices
> are supported via the devicetree:
> 
> - VIC interrupts
> - PL011 UART
> - PL061 GPIO
> - Synopsys DW I2C
> - Synopsys DW ethernet
> 
> Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
> follow in later patches.
so drop USB, nand & co from the dtsi

this will be add later when the binding will documentated and Acked

> 
> Only the spear600-evb is currently supported. Other SPEAr600
> based boards will follow later.
> 
> Since the current mainline SPEAr600 code only supports the SPEAr600
> evaluation board, with nearly zero peripheral devices (only UART
> and GPIO), it makes sense to switch over to DT based configuration
> completely now. So this patch also removes all non-DT stuff, mainly
> platform device data. The files spear600.c and spear600_evb.c are
> removed completely.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
> v4:
> - Added memory node to all dts/dtsi files
> - Reorganizes bus topology in the dtsi file, to match the
>   real SoC layout
> 
> v3:
> - Removed non-DT SPEAr600 board support completely
> - Removed OF_DEV_AUXDATA and changed clkdev instead, since we
>   don't support non-DT targets any more
> - Changed gmac0 -> gmac etc for single instance devices in the
>   dts
> - Added max memory size to memory node (instead of 0)
> - Dropped mac-address property
> - Removed some headers from spear6xx.c
> 
> v2:
> - Added DT support to spear6xx.c instead of creating board-dt.c
> - Removed UART (PL011) and GPIO (PL061) platform data for
>   devicetree board port. This works now via DT probing
> - Added OF_DEV_AUXDATA for clock device name matching for some
>   device drivers
> - Removed sper600.c file completely
> - Added DW I2C and ethernet nodes to the dts files
> - Added other DT nodes (SMI, FSMC, ECHI, OHCI), currently disabled
>   since the corresponding device drivers don't support DT probing
> - Removed Linaro/FSL copyright notice from SPEAr DT files (copy-paste cruft)
> - Many smaller modification to the dts/dtsi files
> - Changed Documentation/devicetree/bindings/arm/spear.txt to match
>   the changed bindings
> 
>  Documentation/devicetree/bindings/arm/spear.txt |    8 ++
>  arch/arm/boot/dts/spear600-evb.dts              |   37 +++++
>  arch/arm/boot/dts/spear600.dtsi                 |  170 +++++++++++++++++++++++
>  arch/arm/mach-spear6xx/Kconfig                  |    7 +-
>  arch/arm/mach-spear6xx/Makefile                 |    6 -
>  arch/arm/mach-spear6xx/clock.c                  |   14 +-
>  arch/arm/mach-spear6xx/spear600.c               |   25 ----
>  arch/arm/mach-spear6xx/spear600_evb.c           |   54 -------
>  arch/arm/mach-spear6xx/spear6xx.c               |  132 +++++-------------
>  9 files changed, 262 insertions(+), 191 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
>  create mode 100644 arch/arm/boot/dts/spear600-evb.dts
>  create mode 100644 arch/arm/boot/dts/spear600.dtsi
>  delete mode 100644 arch/arm/mach-spear6xx/spear600.c
>  delete mode 100644 arch/arm/mach-spear6xx/spear600_evb.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
> new file mode 100644
> index 0000000..f8e54f0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/spear.txt
> @@ -0,0 +1,8 @@
> +ST SPEAr Platforms Device Tree Bindings
> +---------------------------------------
> +
> +Boards with the ST SPEAr600 SoC shall have the following properties:
> +
> +Required root node property:
> +
> +compatible = "st,spear600";
> diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
> new file mode 100644
> index 0000000..bf706b2
> --- /dev/null
> +++ b/arch/arm/boot/dts/spear600-evb.dts
> @@ -0,0 +1,37 @@
> +/*
> + * Copyright 2012 Stefan Roese <sr at denx.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "spear600.dtsi"
> +
> +/ {
> +	model = "ST SPEAr600 Evaluation Board";
> +	compatible = "st,spear600-evb", "st,spear600";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0 0x10000000>;
> +	};
> +
> +	ahb {
> +		gmac: ethernet at e0800000 {
> +			phy-mode = "gmii";
> +		};
> +
> +		apb {
> +			i2c at d0200000 {
> +				clock-frequency = <400000>;

disable everything not core is good in the dtsi
so board enable what they need and do not get surprised whe updating the dtsi

but you need to consistant


> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
> new file mode 100644
> index 0000000..cf14762
> --- /dev/null
> +++ b/arch/arm/boot/dts/spear600.dtsi
> @@ -0,0 +1,170 @@
> +/*
> + * Copyright 2012 Stefan Roese <sr at denx.de>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	compatible = "st,spear600";
> +
> +	cpus {
> +		cpu at 0 {
> +			compatible = "arm,arm926ejs";
> +		};
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0 0x40000000>;
> +	};
> +
> +	ahb {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		vic0: interrupt-controller at f1100000 {
> +			compatible = "arm,pl190-vic";
> +			interrupt-controller;
> +			reg = <0xf1100000 0x1000>;
> +			#interrupt-cells = <1>;
> +		};
> +
> +		vic1: interrupt-controller at f1000000 {
> +			compatible = "arm,pl190-vic";
> +			interrupt-controller;
> +			reg = <0xf1000000 0x1000>;
> +			#interrupt-cells = <1>;
> +		};
> +
> +		gmac: ethernet at e0800000 {
> +			compatible = "st,spear600-gmac";
> +			reg = <0xe0800000 0x8000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <24 23>;
> +			interrupt-names = "macirq", "eth_wake_irq";
> +		};
> +
> +		fsmc: flash at d1800000 {
> +			status = "disabled";
> +			compatible = "st,spear600-fsmc-nand";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0xd1800000 0x1000	/* FSMC Register */
> +			       0xd2000000 0x4000>;	/* NAND Base */
> +			reg-names = "fsmc_regs", "nand_data";
> +			st,ale-off = <0x20000>;
> +			st,cle-off = <0x10000>;
> +		};
> +
> +		smi: flash at fc000000 {
> +			status = "disabled";
> +			compatible = "st,spear600-smi";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0xfc000000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <12>;
> +		};
> +
> +		ehci at e1800000 {
> +			status = "disabled";
> +			compatible = "st,spear600-ehci", "usb-ehci";
> +			reg = <0xe1800000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <27>;
> +		};
> +
> +		ehci at e2000000 {
> +			status = "disabled";
> +			compatible = "st,spear600-ehci", "usb-ehci";
> +			reg = <0xe2000000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <29>;
> +		};
> +
> +		ohci at e1900000 {
> +			status = "disabled";
> +			compatible = "st,spear600-ohci", "usb-ohci";
> +			reg = <0xe1900000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <26>;
> +		};
> +
> +		ohci at e2100000 {
> +			status = "disabled";
> +			compatible = "st,spear600-ohci", "usb-ohci";
> +			reg = <0xe2100000 0x1000>;
> +			interrupt-parent = <&vic1>;
> +			interrupts = <28>;
> +		};
> +
> +		apb {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "simple-bus";
> +			ranges;
> +
> +			serial at d0000000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0xd0000000 0x1000>;
> +				interrupt-parent = <&vic0>;
> +				interrupts = <24>;
> +			};
> +
> +			serial at d0080000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0xd0080000 0x1000>;
> +				interrupt-parent = <&vic0>;
> +				interrupts = <25>;
> +			};
> +
> +			/* local/cpu GPIO */
> +			gpio0: gpio at f0100000 {
> +				#gpio-cells = <2>;
> +				compatible = "arm,pl061", "arm,primecell";
> +				gpio-controller;
> +				reg = <0xf0100000 0x1000>;
> +				interrupt-parent = <&vic0>;
> +				interrupts = <18>;
> +			};
> +
> +			/* basic GPIO */
> +			gpio1: gpio at fc980000 {
on ST SoC the gpio are usally called pio so pio0
> +				#gpio-cells = <2>;
> +				compatible = "arm,pl061", "arm,primecell";
> +				gpio-controller;
> +				reg = <0xfc980000 0x1000>;
> +				interrupt-parent = <&vic1>;
> +				interrupts = <19>;
> +			};
> +
> +			/* appl GPIO */
> +			gpio2: gpio at d8100000 {
> +				#gpio-cells = <2>;
> +				compatible = "arm,pl061", "arm,primecell";
> +				gpio-controller;
> +				reg = <0xd8100000 0x1000>;
> +				interrupt-parent = <&vic1>;
> +				interrupts = <4>;
> +			};
> +
> +			i2c at d0200000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "snps,designware-i2c";
> +				reg = <0xd0200000 0x1000>;
> +				interrupt-parent = <&vic0>;
> +				interrupts = <28>;
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
> index ff4ae5b..fbe298b 100644
> --- a/arch/arm/mach-spear6xx/Kconfig
> +++ b/arch/arm/mach-spear6xx/Kconfig
> @@ -5,11 +5,12 @@
>  if ARCH_SPEAR6XX
>  
>  menu "SPEAr6xx Implementations"
> -config BOARD_SPEAR600_EVB
> -	bool "SPEAr600 Evaluation Board"
> +config BOARD_SPEAR600_DT
> +	bool "SPEAr600 generic board configured via device-tree"
>  	select MACH_SPEAR600
> +	select USE_OF
>  	help
> -	  Supports ST SPEAr600 Evaluation Board
> +	  Supports ST SPEAr600 boards configured via the device-tree
>  
>  endmenu
>  
> diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
> index cc1a4d8..76e5750 100644
> --- a/arch/arm/mach-spear6xx/Makefile
> +++ b/arch/arm/mach-spear6xx/Makefile
> @@ -4,9 +4,3 @@
>  
>  # common files
>  obj-y	+= clock.o spear6xx.o
> -
> -# spear600 specific files
> -obj-$(CONFIG_MACH_SPEAR600) += spear600.o
> -
> -# spear600 boards files
> -obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
> diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
> index ac70e0d..358f280 100644
> --- a/arch/arm/mach-spear6xx/clock.c
> +++ b/arch/arm/mach-spear6xx/clock.c
> @@ -641,8 +641,8 @@ static struct clk_lookup spear_clk_lookups[] = {
>  	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
>  	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
>  	{ .con_id = "gpt3_synth_clk",	.clk = &gpt3_synth_clk},
> -	{ .dev_id = "uart0",		.clk = &uart0_clk},
> -	{ .dev_id = "uart1",		.clk = &uart1_clk},
> +	{ .dev_id = "d0000000.serial",	.clk = &uart0_clk},
> +	{ .dev_id = "d0080000.serial",	.clk = &uart1_clk},
switch to the macro CLK_.. will be good but can be done later


otherwise look good

Best Regards,
J.


From plagnioj at jcrosoft.com  Fri Mar 16 07:51:56 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 16 Mar 2012 12:51:56 +0100
Subject: [PATCH v4] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <4F630D39.2090905@st.com>
References: <1331890216-8361-1-git-send-email-sr@denx.de>
 <4F630D39.2090905@st.com>
Message-ID: <20120316115156.GG7757@game.jcrosoft.org>

On 15:21 Fri 16 Mar     , Viresh Kumar wrote:
> On 3/16/2012 3:00 PM, Stefan Roese wrote:
> > This patch adds a generic target for SPEAr600 board that can be
> > configured via the device-tree. Currently the following devices
> > are supported via the devicetree:
> > 
> > - VIC interrupts
> > - PL011 UART
> > - PL061 GPIO
> > - Synopsys DW I2C
> > - Synopsys DW ethernet
> > 
> > Signed-off-by: Stefan Roese <sr at denx.de>
> > Cc: Viresh Kumar <viresh.kumar at st.com>
> > Cc: Arnd Bergmann <arnd at arndb.de>
> > Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> 
> Acked-by: Viresh Kumar <viresh.kumar at st.com>
> 
> I have one query (as part of my learning of DT) to all DT experts:
> 
> > 
> > +                       /* local/cpu GPIO */
> > +                       gpio0: gpio at f0100000 {
> > +                               #gpio-cells = <2>;
> > +                               compatible = "arm,pl061", "arm,primecell";
> > +                               gpio-controller;
> > +                               reg = <0xf0100000 0x1000>;
> > +                               interrupt-parent = <&vic0>;
> > +                               interrupts = <18>;
> > +                       };
> > +
> > 
> 
> Can we add name property here:
> 				name = "gpio0"
> 
> So that we don't need to do below stuff.
no the nae of the device is f0100000.gpio"

so what do stefan is right

Best Regards,
J.


From arnd at arndb.de  Fri Mar 16 08:04:19 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 12:04:19 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <4F6321DB.50600@ti.com>
References: <4F22DEF2.5000807@ti.com> <201203161003.02163.arnd@arndb.de>
 <4F6321DB.50600@ti.com>
Message-ID: <201203161204.19800.arnd@arndb.de>

On Friday 16 March 2012, Cousson, Benoit wrote:
> And it seems that other ARM SoCs are using it for the same purpose. 
> There are at least 230+ IORESOURCE_DMA instances in the kernel today.

These tend to be the ones that don't use dmaengine but either the
ISA dma api or a platform specific variant of that, right?

Also, I think that most of those definitions are for the same few
devices. The number that I see is much lower:

$ git grep -l IORESOURCE_DMA drivers/ sound/ | wc -l
     51

Out of those, a quite number are mips or blackfin or xtensa based, or are
for legacy ISA devices, which leaves 29 drivers for ARM. 

> For the moment it is still used in a lot of places, and without any 
> other better API yet, it is still useful. As written it is there only 
> for simple single DMA controller case.
> 
> By maintaining that IORESOURCE_DMA for the moment we can adapt some 
> driver to DT without having to change the way they are retrieving 
> information. By using IORESOURCE_IRQ and IORESOURCE_MEM, we had the same 
> advantage.

The main difference to IORESOURCE_IRQ and IORESOURCE_MEM that I see
is that those are going to start for any forseeable time and are actually
helpful in a lot of ways. We are not going to remove the single number
space for interrupts in the next few years. For DMA, the dmaengine API
has already moved away from the flat number space of the ISA API.

> Otherwise how are we supposed to get the DMA channel for non-DT boot 
> until we have migrated everything to DT? A bunch of ARM SoC are using 
> IORESOURCE_DMA for the same purpose.
> 
> The goal here is really to maintain that during the transition phase 
> only. As soon as the full DT support is there, we can switch to the of_ API.
> 
> Ideally, we should define and use a generic API non dependent of DT. 
> AFAIK, that does not exist so far.
> And since most drivers are not using dmaengine, we do not even have a 
> common DMA fmwk to define an API on top.
> 
> I fully agree that this IORESOURCE_DMA is not scalable for multiple 
> controller, ugly, and must be avoided like the plague.
> But what other options do we have during the transition?

We could use the same binding for the nonstandard controllers, but
keep the dma channel number lookup separate for those, and let them
call of_get_dma_request directly.

Since there are not too many drivers using those controllers with
dma resources today, it's fairly easy to go through those as we write
the driver bindings and just do

	err = of_get_dma_request(pdev->dev.of_node, 0, &dma);
	if (err) {
		struct resource *r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
		if (r)
			dma = r->start;
	}

For the drivers that we convert to DT before we convert them to dmaengine,
and not do anything if we convert them to dmaengine first.

	Arnd


From arnd at arndb.de  Fri Mar 16 08:09:18 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 12:09:18 +0000
Subject: [PATCH v4] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <20120316115022.GF7757@game.jcrosoft.org>
References: <1331890216-8361-1-git-send-email-sr@denx.de>
 <20120316115022.GF7757@game.jcrosoft.org>
Message-ID: <201203161209.18292.arnd@arndb.de>

On Friday 16 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> On 10:30 Fri 16 Mar     , Stefan Roese wrote:
> > This patch adds a generic target for SPEAr600 board that can be
> > configured via the device-tree. Currently the following devices
> > are supported via the devicetree:
> > 
> > - VIC interrupts
> > - PL011 UART
> > - PL061 GPIO
> > - Synopsys DW I2C
> > - Synopsys DW ethernet
> > 
> > Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
> > follow in later patches.
> so drop USB, nand & co from the dtsi
> 
> this will be add later when the binding will documentated and Acked
> 

I actually like to see the devices in there, and it already helped
figure out that there are two buses instead of just one. Maybe we
can agree on putting them in the file but commenting them out using
/* */ with an added notice that they will get enabled once we have
bindings?

	Arnd


From arnd at arndb.de  Fri Mar 16 08:14:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 12:14:35 +0000
Subject: [PATCH v4] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <1331890216-8361-1-git-send-email-sr@denx.de>
References: <1331890216-8361-1-git-send-email-sr@denx.de>
Message-ID: <201203161214.35929.arnd@arndb.de>

On Friday 16 March 2012, Stefan Roese wrote:

> v4:
> - Added memory node to all dts/dtsi files
> - Reorganizes bus topology in the dtsi file, to match the
>   real SoC layout

Looks good.

> +
> +	ahb {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		vic0: interrupt-controller at f1100000 {
> +			compatible = "arm,pl190-vic";
> +			interrupt-controller;
> +			reg = <0xf1100000 0x1000>;
> +			#interrupt-cells = <1>;
> +		};
> +
> ...
> +		apb {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "simple-bus";
> +			ranges;
> +
> +			serial at d0000000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0xd0000000 0x1000>;
> +				interrupt-parent = <&vic0>;
> +				interrupts = <24>;
> +			};
> ...
> +		};
> +	};
> +};

I would prefer to see non-empty ranges properties here. I expected the
buses to be contiguous address ranges per bus, but apparently that
is not the case -- you have 0xd... and 0xf... on both of them.

The simplest ranges property would be to have in the ahb node:

	ranges = <0xd0000000 0xd0000000 0x30000000>;

Which just means that the bus is limited to those addresses (if that is
indeed the case -- I don't know much about ahb and apb).

	Arnd


From arnd.bergmann at linaro.org  Fri Mar 16 08:18:05 2012
From: arnd.bergmann at linaro.org (Arnd Bergmann)
Date: Fri, 16 Mar 2012 12:18:05 +0000
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <alpine.LFD.2.02.1203161129010.2466@ionos>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
Message-ID: <201203161218.05125.arnd.bergmann@linaro.org>

On Friday 16 March 2012, Amit Kucheria wrote:
> On Fri, Mar 16, 2012 at 12:29 PM, Thomas Gleixner <tglx at linutronix.de> wrote:
> > On Fri, 16 Mar 2012, Linus Walleij wrote:
> >
> >> On Fri, Mar 16, 2012 at 7:11 AM, Mike Turquette <mturquette at linaro.org> wrote:
> >>
> >> > Provide documentation for the common clk structures and APIs.  This code
> >> > can be found in drivers/clk/ and include/linux/clk*.h.
> >>
> >> Acked-by: Linus Wallej <linus.walleij at linaro.org>
> >> For this three-piece v7 patchset.
> >>
> >> It already does magnitudes more advanced stuff than what I need
> >> so I'm pretty pleased, any remaining details can surely be ironed out
> >> in-tree.
> >
> > Ack. We really need to get that in now and sort out the details in
> > tree otherwise we will never finish that thing.
> >
> 
> Thomas, Russell, Arnd,
> 
> Can we shoe-horn this thing into 3.4 (it is a bit late, i know) so
> that platform ports can gather speed? Several people are waiting for a
> somewhat stable version before starting their ports.
> 
> And what is the path into mainline - will Russell carry it or Arnd
> (with Russell's blessing)?

I would suggest putting it into a late/* branch of arm-soc so it finally
gets some linux-next exposure, and then sending it in the second week of the
merge window.

Russell, please let me know if you want to carry it instead or if you
have found any last-minute show stoppers in the code.

	Arnd


From sr at denx.de  Fri Mar 16 08:20:25 2012
From: sr at denx.de (Stefan Roese)
Date: Fri, 16 Mar 2012 13:20:25 +0100
Subject: [PATCH v4] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <20120316115022.GF7757@game.jcrosoft.org>
References: <1331890216-8361-1-git-send-email-sr@denx.de>
 <20120316115022.GF7757@game.jcrosoft.org>
Message-ID: <201203161320.25873.sr@denx.de>

On Friday 16 March 2012 12:50:22 Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 10:30 Fri 16 Mar     , Stefan Roese wrote:
> > This patch adds a generic target for SPEAr600 board that can be
> > configured via the device-tree. Currently the following devices
> > are supported via the devicetree:
> > 
> > - VIC interrupts
> > - PL011 UART
> > - PL061 GPIO
> > - Synopsys DW I2C
> > - Synopsys DW ethernet
> > 
> > Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
> > follow in later patches.
> 
> so drop USB, nand & co from the dtsi
> 
> this will be add later when the binding will documentated and Acked

Okay. As I described in an earlier mail, I included those devices upon Arnd's 
request. But I'll drop them for now in a new patch version.
 
> > Only the spear600-evb is currently supported. Other SPEAr600
> > based boards will follow later.
> > 
> > Since the current mainline SPEAr600 code only supports the SPEAr600
> > evaluation board, with nearly zero peripheral devices (only UART
> > and GPIO), it makes sense to switch over to DT based configuration
> > completely now. So this patch also removes all non-DT stuff, mainly
> > platform device data. The files spear600.c and spear600_evb.c are
> > removed completely.
> > 
> > Signed-off-by: Stefan Roese <sr at denx.de>
> > Cc: Viresh Kumar <viresh.kumar at st.com>
> > Cc: Arnd Bergmann <arnd at arndb.de>
> > Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> > ---
> > v4:
> > - Added memory node to all dts/dtsi files
> > - Reorganizes bus topology in the dtsi file, to match the
> > 
> >   real SoC layout
> > 
> > v3:
> > - Removed non-DT SPEAr600 board support completely
> > - Removed OF_DEV_AUXDATA and changed clkdev instead, since we
> > 
> >   don't support non-DT targets any more
> > 
> > - Changed gmac0 -> gmac etc for single instance devices in the
> > 
> >   dts
> > 
> > - Added max memory size to memory node (instead of 0)
> > - Dropped mac-address property
> > - Removed some headers from spear6xx.c
> > 
> > v2:
> > - Added DT support to spear6xx.c instead of creating board-dt.c
> > - Removed UART (PL011) and GPIO (PL061) platform data for
> > 
> >   devicetree board port. This works now via DT probing
> > 
> > - Added OF_DEV_AUXDATA for clock device name matching for some
> > 
> >   device drivers
> > 
> > - Removed sper600.c file completely
> > - Added DW I2C and ethernet nodes to the dts files
> > - Added other DT nodes (SMI, FSMC, ECHI, OHCI), currently disabled
> > 
> >   since the corresponding device drivers don't support DT probing
> > 
> > - Removed Linaro/FSL copyright notice from SPEAr DT files (copy-paste
> > cruft) - Many smaller modification to the dts/dtsi files
> > - Changed Documentation/devicetree/bindings/arm/spear.txt to match
> > 
> >   the changed bindings
> >  
> >  Documentation/devicetree/bindings/arm/spear.txt |    8 ++
> >  arch/arm/boot/dts/spear600-evb.dts              |   37 +++++
> >  arch/arm/boot/dts/spear600.dtsi                 |  170
> >  +++++++++++++++++++++++ arch/arm/mach-spear6xx/Kconfig                 
> >  |    7 +-
> >  arch/arm/mach-spear6xx/Makefile                 |    6 -
> >  arch/arm/mach-spear6xx/clock.c                  |   14 +-
> >  arch/arm/mach-spear6xx/spear600.c               |   25 ----
> >  arch/arm/mach-spear6xx/spear600_evb.c           |   54 -------
> >  arch/arm/mach-spear6xx/spear6xx.c               |  132
> >  +++++------------- 9 files changed, 262 insertions(+), 191 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
> >  create mode 100644 arch/arm/boot/dts/spear600-evb.dts
> >  create mode 100644 arch/arm/boot/dts/spear600.dtsi
> >  delete mode 100644 arch/arm/mach-spear6xx/spear600.c
> >  delete mode 100644 arch/arm/mach-spear6xx/spear600_evb.c
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/spear.txt
> > b/Documentation/devicetree/bindings/arm/spear.txt new file mode 100644
> > index 0000000..f8e54f0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/spear.txt
> > @@ -0,0 +1,8 @@
> > +ST SPEAr Platforms Device Tree Bindings
> > +---------------------------------------
> > +
> > +Boards with the ST SPEAr600 SoC shall have the following properties:
> > +
> > +Required root node property:
> > +
> > +compatible = "st,spear600";
> > diff --git a/arch/arm/boot/dts/spear600-evb.dts
> > b/arch/arm/boot/dts/spear600-evb.dts new file mode 100644
> > index 0000000..bf706b2
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/spear600-evb.dts
> > @@ -0,0 +1,37 @@
> > +/*
> > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/dts-v1/;
> > +/include/ "spear600.dtsi"
> > +
> > +/ {
> > +	model = "ST SPEAr600 Evaluation Board";
> > +	compatible = "st,spear600-evb", "st,spear600";
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	memory {
> > +		device_type = "memory";
> > +		reg = <0 0x10000000>;
> > +	};
> > +
> > +	ahb {
> > +		gmac: ethernet at e0800000 {
> > +			phy-mode = "gmii";
> > +		};
> > +
> > +		apb {
> > +			i2c at d0200000 {
> > +				clock-frequency = <400000>;
> 
> disable everything not core is good in the dtsi
> so board enable what they need and do not get surprised whe updating the
> dtsi
> 
> but you need to consistant

Let me check, if I understand you correctly. I should disable all peripheral 
devices in the *.dtsi file?  All devices? Also interrupt controller? Is this 
common practice? I don't see it in other dtsi file (e.g. omap4/tegra).

> > +			};
> > +		};
> > +	};
> > +};
> > diff --git a/arch/arm/boot/dts/spear600.dtsi
> > b/arch/arm/boot/dts/spear600.dtsi new file mode 100644
> > index 0000000..cf14762
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/spear600.dtsi
> > @@ -0,0 +1,170 @@
> > +/*
> > + * Copyright 2012 Stefan Roese <sr at denx.de>
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/include/ "skeleton.dtsi"
> > +
> > +/ {
> > +	compatible = "st,spear600";
> > +
> > +	cpus {
> > +		cpu at 0 {
> > +			compatible = "arm,arm926ejs";
> > +		};
> > +	};
> > +
> > +	memory {
> > +		device_type = "memory";
> > +		reg = <0 0x40000000>;
> > +	};
> > +
> > +	ahb {
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		compatible = "simple-bus";
> > +		ranges;
> > +
> > +		vic0: interrupt-controller at f1100000 {
> > +			compatible = "arm,pl190-vic";
> > +			interrupt-controller;
> > +			reg = <0xf1100000 0x1000>;
> > +			#interrupt-cells = <1>;
> > +		};
> > +
> > +		vic1: interrupt-controller at f1000000 {
> > +			compatible = "arm,pl190-vic";
> > +			interrupt-controller;
> > +			reg = <0xf1000000 0x1000>;
> > +			#interrupt-cells = <1>;
> > +		};
> > +
> > +		gmac: ethernet at e0800000 {
> > +			compatible = "st,spear600-gmac";
> > +			reg = <0xe0800000 0x8000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <24 23>;
> > +			interrupt-names = "macirq", "eth_wake_irq";
> > +		};
> > +
> > +		fsmc: flash at d1800000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-fsmc-nand";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			reg = <0xd1800000 0x1000	/* FSMC Register */
> > +			       0xd2000000 0x4000>;	/* NAND Base */
> > +			reg-names = "fsmc_regs", "nand_data";
> > +			st,ale-off = <0x20000>;
> > +			st,cle-off = <0x10000>;
> > +		};
> > +
> > +		smi: flash at fc000000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-smi";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			reg = <0xfc000000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <12>;
> > +		};
> > +
> > +		ehci at e1800000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-ehci", "usb-ehci";
> > +			reg = <0xe1800000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <27>;
> > +		};
> > +
> > +		ehci at e2000000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-ehci", "usb-ehci";
> > +			reg = <0xe2000000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <29>;
> > +		};
> > +
> > +		ohci at e1900000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-ohci", "usb-ohci";
> > +			reg = <0xe1900000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <26>;
> > +		};
> > +
> > +		ohci at e2100000 {
> > +			status = "disabled";
> > +			compatible = "st,spear600-ohci", "usb-ohci";
> > +			reg = <0xe2100000 0x1000>;
> > +			interrupt-parent = <&vic1>;
> > +			interrupts = <28>;
> > +		};
> > +
> > +		apb {
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			compatible = "simple-bus";
> > +			ranges;
> > +
> > +			serial at d0000000 {
> > +				compatible = "arm,pl011", "arm,primecell";
> > +				reg = <0xd0000000 0x1000>;
> > +				interrupt-parent = <&vic0>;
> > +				interrupts = <24>;
> > +			};
> > +
> > +			serial at d0080000 {
> > +				compatible = "arm,pl011", "arm,primecell";
> > +				reg = <0xd0080000 0x1000>;
> > +				interrupt-parent = <&vic0>;
> > +				interrupts = <25>;
> > +			};
> > +
> > +			/* local/cpu GPIO */
> > +			gpio0: gpio at f0100000 {
> > +				#gpio-cells = <2>;
> > +				compatible = "arm,pl061", "arm,primecell";
> > +				gpio-controller;
> > +				reg = <0xf0100000 0x1000>;
> > +				interrupt-parent = <&vic0>;
> > +				interrupts = <18>;
> > +			};
> > +
> > +			/* basic GPIO */
> > +			gpio1: gpio at fc980000 {
> 
> on ST SoC the gpio are usally called pio so pio0

Not on SPEAr600 as far as I can tell.
 
> > +				#gpio-cells = <2>;
> > +				compatible = "arm,pl061", "arm,primecell";
> > +				gpio-controller;
> > +				reg = <0xfc980000 0x1000>;
> > +				interrupt-parent = <&vic1>;
> > +				interrupts = <19>;
> > +			};
> > +
> > +			/* appl GPIO */
> > +			gpio2: gpio at d8100000 {
> > +				#gpio-cells = <2>;
> > +				compatible = "arm,pl061", "arm,primecell";
> > +				gpio-controller;
> > +				reg = <0xd8100000 0x1000>;
> > +				interrupt-parent = <&vic1>;
> > +				interrupts = <4>;
> > +			};
> > +
> > +			i2c at d0200000 {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				compatible = "snps,designware-i2c";
> > +				reg = <0xd0200000 0x1000>;
> > +				interrupt-parent = <&vic0>;
> > +				interrupts = <28>;
> > +			};
> > +		};
> > +	};
> > +};
> > diff --git a/arch/arm/mach-spear6xx/Kconfig
> > b/arch/arm/mach-spear6xx/Kconfig index ff4ae5b..fbe298b 100644
> > --- a/arch/arm/mach-spear6xx/Kconfig
> > +++ b/arch/arm/mach-spear6xx/Kconfig
> > @@ -5,11 +5,12 @@
> > 
> >  if ARCH_SPEAR6XX
> >  
> >  menu "SPEAr6xx Implementations"
> > 
> > -config BOARD_SPEAR600_EVB
> > -	bool "SPEAr600 Evaluation Board"
> > +config BOARD_SPEAR600_DT
> > +	bool "SPEAr600 generic board configured via device-tree"
> > 
> >  	select MACH_SPEAR600
> > 
> > +	select USE_OF
> > 
> >  	help
> > 
> > -	  Supports ST SPEAr600 Evaluation Board
> > +	  Supports ST SPEAr600 boards configured via the device-tree
> > 
> >  endmenu
> > 
> > diff --git a/arch/arm/mach-spear6xx/Makefile
> > b/arch/arm/mach-spear6xx/Makefile index cc1a4d8..76e5750 100644
> > --- a/arch/arm/mach-spear6xx/Makefile
> > +++ b/arch/arm/mach-spear6xx/Makefile
> > @@ -4,9 +4,3 @@
> > 
> >  # common files
> >  obj-y	+= clock.o spear6xx.o
> > 
> > -
> > -# spear600 specific files
> > -obj-$(CONFIG_MACH_SPEAR600) += spear600.o
> > -
> > -# spear600 boards files
> > -obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
> > diff --git a/arch/arm/mach-spear6xx/clock.c
> > b/arch/arm/mach-spear6xx/clock.c index ac70e0d..358f280 100644
> > --- a/arch/arm/mach-spear6xx/clock.c
> > +++ b/arch/arm/mach-spear6xx/clock.c
> > @@ -641,8 +641,8 @@ static struct clk_lookup spear_clk_lookups[] = {
> > 
> >  	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
> >  	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
> >  	{ .con_id = "gpt3_synth_clk",	.clk = &gpt3_synth_clk},
> > 
> > -	{ .dev_id = "uart0",		.clk = &uart0_clk},
> > -	{ .dev_id = "uart1",		.clk = &uart1_clk},
> > +	{ .dev_id = "d0000000.serial",	.clk = &uart0_clk},
> > +	{ .dev_id = "d0080000.serial",	.clk = &uart1_clk},
> 
> switch to the macro CLK_.. will be good but can be done later

Sure. Still a lot to do... 
 
> otherwise look good

Ufff. Good.

Thanks,
Stefan


From shawn.guo at linaro.org  Fri Mar 16 08:22:46 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 16 Mar 2012 20:22:46 +0800
Subject: [GIT PULL] imx irq_domain migration
In-Reply-To: <CACxGe6tsHWj+bHcg1uEV8x-KE7B8p1Lj-_DL9mysYn1z+Bex3g@mail.gmail.com>
References: <20120216154941.GB11758@r65073-Latitude-D630>
 <4F3D41D2.5090203@gmail.com>
 <20120314050837.GB21337@S2101-09.ap.freescale.net>
 <4F6098C6.7050503@gmail.com>
 <CACxGe6tsHWj+bHcg1uEV8x-KE7B8p1Lj-_DL9mysYn1z+Bex3g@mail.gmail.com>
Message-ID: <20120316122243.GH7758@S2101-09.ap.freescale.net>

On Wed, Mar 14, 2012 at 09:44:26AM -0600, Grant Likely wrote:
> On Wed, Mar 14, 2012 at 7:10 AM, Rob Herring <robherring2 at gmail.com> wrote:
> > On 03/14/2012 12:08 AM, Shawn Guo wrote:
> >> On Thu, Feb 16, 2012 at 11:50:10AM -0600, Rob Herring wrote:
> >>> Shawn,
> >>>
> >>> On 02/16/2012 09:49 AM, Shawn Guo wrote:
> >>>> Hi Rob,
> >>>>
> >>>> Please pull imx irq_domain support below. It's based on Grant's
> >>>> irqdomain/next today with your generic-chip series applied on top
> >>>> of it.
> >>>
> >>> You're asking me to pull changes on top of a branch that I don't even
> >>> have as you've rebased my changes. While it would work I don't think
> >>> this is the right flow. Plus there is not really any reason for iMX
> >>> changes to go thru me.
> >>>
> >>> Either Grant needs to stabilize his branch so you and I can send him
> >>> pull requests or he can pull in our changes and rebase them as he
> >>> rebases. I already asked him to do just that with my 1 patch others are
> >>> dependent on.
> >>>
> >> Hi Grant,
> >>
> >> Would you consider to take this request after you take Rob's
> >> generic_irq one?
> >
> > You'll need rebase your branch as I did since Grant did.
> 
> Also, the imx changes should go via the arm-soc tree, not the
> irqdomain/next branch.  irqdomain/next is stable now, so you can use
> it as your base.  Rebase your changes on top of it and ask Arnd or
> Olof to pull the result into an arm-soc branch.
> 
Okay.  Since imx change has a dependency on Rob's change, I have to
wait until Rob's change shows up on irqdomain/next.

-- 
Regards,
Shawn


From tarun.kanti at ti.com  Fri Mar 16 08:24:05 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 17:54:05 +0530
Subject: [PATCH 0/2] omap: board file changes to support dynamic irq alloc
Message-ID: <1331900647-3508-1-git-send-email-tarun.kanti@ti.com>

These two patches incorporate changes to OMAP1 and OMAP2 platforms
board files whereby older references to OMAP_GPIO_IRQ macro are
now replaced with gpio_to_irq(), thereby getting rid of static
irq references.

Reference: git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git omap/dt
Commit: 9a0cee711448335ec43eae83272495e9334c0098

Test info:
OMAP1 Platforms:
Boot test on OMAP1710 H3.

OMAP2PLUS Platforms:
OMAP2430SDP, OMAP3430SDP, OMAP3630-ZOOM3, OMAP4430-SDP,
OMAP4430-PANDA, OMAP4430-BLAZE

I have also done gpio functional testing after merging Grant's:
git://git.secretlab.ca/git/linux-2.6.git gpio/next
on top of these patches.

I would request someone help me testing on other platforms.

Tarun Kanti DebBarma (2):
  omap1/board-files: fix OMAP_GPIO_IRQ usage with gpio_to_irq()
  omap2plus/board-files: fix OMAP_GPIO_IRQ usage with gpio_to_irq()

 arch/arm/mach-omap1/board-h2.c               |    8 ++++----
 arch/arm/mach-omap1/board-h3.c               |    8 ++++----
 arch/arm/mach-omap1/board-htcherald.c        |    6 +++---
 arch/arm/mach-omap1/board-innovator.c        |    4 ++--
 arch/arm/mach-omap1/board-nokia770.c         |    1 +
 arch/arm/mach-omap1/board-osk.c              |   12 ++++++------
 arch/arm/mach-omap1/board-palmte.c           |    2 +-
 arch/arm/mach-omap1/board-palmtt.c           |    2 +-
 arch/arm/mach-omap1/board-palmz71.c          |    2 +-
 arch/arm/mach-omap1/board-voiceblue.c        |   16 +++++++---------
 arch/arm/mach-omap2/board-2430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-4430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-apollon.c          |    6 ++++--
 arch/arm/mach-omap2/board-devkit8000.c       |    3 ++-
 arch/arm/mach-omap2/board-h4.c               |    2 +-
 arch/arm/mach-omap2/board-omap3evm.c         |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c       |    2 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c |    3 ++-
 arch/arm/mach-omap2/board-zoom-debugboard.c  |    3 ++-
 arch/arm/mach-omap2/board-zoom-peripherals.c |    6 ++++--
 arch/arm/mach-omap2/common-board-devices.c   |    2 +-
 21 files changed, 50 insertions(+), 44 deletions(-)



From tarun.kanti at ti.com  Fri Mar 16 08:24:06 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 17:54:06 +0530
Subject: [PATCH 1/2] omap1/board-files: fix OMAP_GPIO_IRQ usage with
 gpio_to_irq()
In-Reply-To: <1331900647-3508-1-git-send-email-tarun.kanti@ti.com>
References: <1331900647-3508-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331900647-3508-2-git-send-email-tarun.kanti@ti.com>

With dynamic allocation of IRQ the usage of OMAP_GPIO_IRQ
is no longer valid. We should be using gpio_to_irq() instead.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 arch/arm/mach-omap1/board-h2.c        |    8 ++++----
 arch/arm/mach-omap1/board-h3.c        |    8 ++++----
 arch/arm/mach-omap1/board-htcherald.c |    6 +++---
 arch/arm/mach-omap1/board-innovator.c |    4 ++--
 arch/arm/mach-omap1/board-nokia770.c  |    1 +
 arch/arm/mach-omap1/board-osk.c       |   12 ++++++------
 arch/arm/mach-omap1/board-palmte.c    |    2 +-
 arch/arm/mach-omap1/board-palmtt.c    |    2 +-
 arch/arm/mach-omap1/board-palmz71.c   |    2 +-
 arch/arm/mach-omap1/board-voiceblue.c |   16 +++++++---------
 10 files changed, 30 insertions(+), 31 deletions(-)

diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 00ad6b2..ad0eece 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -244,8 +244,6 @@ static struct resource h2_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -364,11 +362,9 @@ static struct tps65010_board tps_board = {
 static struct i2c_board_info __initdata h2_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("tps65010", 0x48),
-		.irq            = OMAP_GPIO_IRQ(58),
 		.platform_data	= &tps_board,
 	}, {
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(2),
 	},
 };
 
@@ -437,10 +433,14 @@ static void __init h2_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	h2_devices[2]->resource[1].start = gpio_to_irq(0);
+	h2_devices[2]->resource[1].end = gpio_to_irq(0);
 	platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
 	omap_board_config = h2_config;
 	omap_board_config_size = ARRAY_SIZE(h2_config);
 	omap_serial_init();
+	h2_i2c_board_info[0].irq = gpio_to_irq(58);
+	h2_i2c_board_info[1].irq = gpio_to_irq(2);
 	omap_register_i2c_bus(1, 100, h2_i2c_board_info,
 			      ARRAY_SIZE(h2_i2c_board_info));
 	omap1_usb_init(&h2_usb_config);
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 4a7f251..692b16d 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -246,8 +246,6 @@ static struct resource smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(40),
-		.end	= OMAP_GPIO_IRQ(40),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -337,7 +335,6 @@ static struct spi_board_info h3_spi_board_info[] __initdata = {
 		.modalias	= "tsc2101",
 		.bus_num	= 2,
 		.chip_select	= 0,
-		.irq		= OMAP_GPIO_IRQ(H3_TS_GPIO),
 		.max_speed_hz	= 16000000,
 		/* .platform_data	= &tsc_platform_data, */
 	},
@@ -381,7 +378,6 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = {
        },
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(14),
 	},
 };
 
@@ -423,12 +419,16 @@ static void __init h3_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	devices[2]->resource[1].start = gpio_to_irq(40);
+	devices[2]->resource[1].end = gpio_to_irq(40);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
+	h3_spi_board_info[0].irq = gpio_to_irq(H3_TS_GPIO);
 	spi_register_board_info(h3_spi_board_info,
 				ARRAY_SIZE(h3_spi_board_info));
 	omap_board_config = h3_config;
 	omap_board_config_size = ARRAY_SIZE(h3_config);
 	omap_serial_init();
+	h3_i2c_board_info[1].irq = gpio_to_irq(14);
 	omap_register_i2c_bus(1, 100, h3_i2c_board_info,
 			      ARRAY_SIZE(h3_i2c_board_info));
 	omap1_usb_init(&h3_usb_config);
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 731cc3d..766b1e3 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -324,8 +324,6 @@ static struct platform_device gpio_leds_device = {
 
 static struct resource htcpld_resources[] = {
 	[0] = {
-		.start  = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
-		.end    = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
 		.flags  = IORESOURCE_IRQ,
 	},
 };
@@ -454,7 +452,6 @@ static struct spi_board_info __initdata htcherald_spi_board_info[] = {
 	{
 		.modalias		= "ads7846",
 		.platform_data		= &htcherald_ts_platform_data,
-		.irq			= OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS),
 		.max_speed_hz		= 2500000,
 		.bus_num		= 2,
 		.chip_select		= 1,
@@ -582,6 +579,8 @@ static void __init htcherald_init(void)
 	/* Do board initialization before we register all the devices */
 	omap_board_config = htcherald_config;
 	omap_board_config_size = ARRAY_SIZE(htcherald_config);
+	devices[2]->resource[0].start = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
+	devices[2]->resource[0].end = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	htcherald_disable_watchdog();
@@ -589,6 +588,7 @@ static void __init htcherald_init(void)
 	htcherald_usb_enable();
 	omap1_usb_init(&htcherald_usb_config);
 
+	htcherald_spi_board_info[0].irq = gpio_to_irq(HTCHERALD_GPIO_TS);
 	spi_register_board_info(htcherald_spi_board_info,
 		ARRAY_SIZE(htcherald_spi_board_info));
 
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index be2002f..965f3d7 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -244,8 +244,6 @@ static struct resource innovator1610_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -409,6 +407,8 @@ static void __init innovator_init(void)
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
 	if (!cpu_is_omap1510()) {
+		innovator1610_devices[1]->resource[1].start = gpio_to_irq(0);
+		innovator1610_devices[1]->resource[1].end = gpio_to_irq(0);
 		platform_add_devices(innovator1610_devices, ARRAY_SIZE(innovator1610_devices));
 	}
 #endif
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index f9efc03..c0b3ce7 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -240,6 +240,7 @@ static void __init omap_nokia770_init(void)
 	omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
 
 	platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
+	nokia770_spi_board_info[1].irq = gpio_to_irq(15);
 	spi_register_board_info(nokia770_spi_board_info,
 				ARRAY_SIZE(nokia770_spi_board_info));
 	omap_serial_init();
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 675de06..6791887 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -129,8 +129,6 @@ static struct resource osk5912_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -147,8 +145,6 @@ static struct platform_device osk5912_smc91x_device = {
 
 static struct resource osk5912_cf_resources[] = {
 	[0] = {
-		.start	= OMAP_GPIO_IRQ(62),
-		.end	= OMAP_GPIO_IRQ(62),
 		.flags	= IORESOURCE_IRQ,
 	},
 };
@@ -240,7 +236,6 @@ static struct tps65010_board tps_board = {
 static struct i2c_board_info __initdata osk_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("tps65010", 0x48),
-		.irq		= OMAP_GPIO_IRQ(OMAP_MPUIO(1)),
 		.platform_data	= &tps_board,
 
 	},
@@ -414,7 +409,6 @@ static struct spi_board_info __initdata mistral_boardinfo[] = { {
 	/* MicroWire (bus 2) CS0 has an ads7846e */
 	.modalias		= "ads7846",
 	.platform_data		= &mistral_ts_info,
-	.irq			= OMAP_GPIO_IRQ(4),
 	.max_speed_hz		= 120000 /* max sample rate at 3V */
 					* 26 /* command + data + overhead */,
 	.bus_num		= 2,
@@ -477,6 +471,7 @@ static void __init osk_mistral_init(void)
 	gpio_direction_input(4);
 	irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
 
+	mistral_boardinfo[0].irq = gpio_to_irq(4);
 	spi_register_board_info(mistral_boardinfo,
 			ARRAY_SIZE(mistral_boardinfo));
 
@@ -548,6 +543,10 @@ static void __init osk_init(void)
 
 	osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
 	osk_flash_resource.end += SZ_32M - 1;
+	osk5912_devices[1]->resource[1].start = gpio_to_irq(0);
+	osk5912_devices[1]->resource[1].end = gpio_to_irq(0);
+	osk5912_devices[2]->resource[0].start = gpio_to_irq(62);
+	osk5912_devices[2]->resource[0].end = gpio_to_irq(62);
 	platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
 	omap_board_config = osk_config;
 	omap_board_config_size = ARRAY_SIZE(osk_config);
@@ -564,6 +563,7 @@ static void __init osk_init(void)
 		gpio_direction_input(OMAP_MPUIO(1));
 
 	omap_serial_init();
+	osk_i2c_board_info[0].irq = gpio_to_irq(OMAP_MPUIO(1));
 	omap_register_i2c_bus(1, 400, osk_i2c_board_info,
 			      ARRAY_SIZE(osk_i2c_board_info));
 	osk_mistral_init();
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 81fa27f..108c7d1 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -218,7 +218,6 @@ static struct spi_board_info palmte_spi_info[] __initdata = {
 		.modalias	= "tsc2102",
 		.bus_num	= 2,	/* uWire (officially) */
 		.chip_select	= 0,	/* As opposed to 3 */
-		.irq		= OMAP_GPIO_IRQ(PALMTE_PINTDAV_GPIO),
 		.max_speed_hz	= 8000000,
 	},
 };
@@ -255,6 +254,7 @@ static void __init omap_palmte_init(void)
 
 	platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices));
 
+	palmte_spi_info[0].irq = gpio_to_irq(PALMTE_PINTDAV_GPIO);
 	spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
 	palmte_misc_gpio_setup();
 	omap_serial_init();
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 81cb821..b87a92f 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -255,7 +255,6 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
 		/* MicroWire (bus 2) CS0 has an ads7846e */
 		.modalias	= "ads7846",
 		.platform_data	= &palmtt_ts_info,
-		.irq		= OMAP_GPIO_IRQ(6),
 		.max_speed_hz	= 120000	/* max sample rate at 3V */
 					* 26	/* command + data + overhead */,
 		.bus_num	= 2,
@@ -303,6 +302,7 @@ static void __init omap_palmtt_init(void)
 
 	platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices));
 
+	palmtt_boardinfo[0].irq = gpio_to_irq(6);
 	spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
 	omap_serial_init();
 	omap1_usb_init(&palmtt_usb_config);
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index e881945..0ff25fa 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -222,7 +222,6 @@ static struct spi_board_info __initdata palmz71_boardinfo[] = { {
 	/* MicroWire (bus 2) CS0 has an ads7846e */
 	.modalias	= "ads7846",
 	.platform_data	= &palmz71_ts_info,
-	.irq		= OMAP_GPIO_IRQ(PALMZ71_PENIRQ_GPIO),
 	.max_speed_hz	= 120000	/* max sample rate at 3V */
 				* 26	/* command + data + overhead */,
 	.bus_num	= 2,
@@ -318,6 +317,7 @@ omap_palmz71_init(void)
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
+	palmz71_boardinfo[0].irq = gpio_to_irq(PALMZ71_PENIRQ_GPIO);
 	spi_register_board_info(palmz71_boardinfo,
 				ARRAY_SIZE(palmz71_boardinfo));
 	omap1_usb_init(&palmz71_usb_config);
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index f83a502..63732fe 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -42,7 +42,6 @@
 static struct plat_serial8250_port voiceblue_ports[] = {
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x40000),
-		.irq		= OMAP_GPIO_IRQ(12),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -50,7 +49,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x50000),
-		.irq		= OMAP_GPIO_IRQ(13),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -58,7 +56,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x60000),
-		.irq		= OMAP_GPIO_IRQ(14),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -66,7 +63,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x70000),
-		.irq		= OMAP_GPIO_IRQ(15),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -78,9 +74,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 static struct platform_device serial_device = {
 	.name			= "serial8250",
 	.id			= PLAT8250_DEV_PLATFORM1,
-	.dev			= {
-		.platform_data	= voiceblue_ports,
-	},
 };
 
 static int __init ext_uart_init(void)
@@ -88,6 +81,11 @@ static int __init ext_uart_init(void)
 	if (!machine_is_voiceblue())
 		return -ENODEV;
 
+	voiceblue_ports[0].irq = gpio_to_irq(12);
+	voiceblue_ports[1].irq = gpio_to_irq(13);
+	voiceblue_ports[2].irq = gpio_to_irq(14);
+	voiceblue_ports[3].irq = gpio_to_irq(15);
+	serial_device.dev.platform_data = voiceblue_ports;
 	return platform_device_register(&serial_device);
 }
 arch_initcall(ext_uart_init);
@@ -126,8 +124,6 @@ static struct resource voiceblue_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(8),
-		.end	= OMAP_GPIO_IRQ(8),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -273,6 +269,8 @@ static void __init voiceblue_init(void)
 	irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
 	irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
 
+	voiceblue_devices[1]->resource[1].start = gpio_to_irq(8);
+	voiceblue_devices[1]->resource[1].end = gpio_to_irq(8);
 	platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
 	omap_board_config = voiceblue_config;
 	omap_board_config_size = ARRAY_SIZE(voiceblue_config);
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 08:24:07 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 17:54:07 +0530
Subject: [PATCH 2/2] omap2plus/board-files: fix OMAP_GPIO_IRQ usage with
 gpio_to_irq()
In-Reply-To: <1331900647-3508-1-git-send-email-tarun.kanti@ti.com>
References: <1331900647-3508-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331900647-3508-3-git-send-email-tarun.kanti@ti.com>

With dynamic allocation of IRQ the usage of OMAP_GPIO_IRQi
is no longer valid. We should be using gpio_to_irq() instead.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 arch/arm/mach-omap2/board-2430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-4430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-apollon.c          |    6 ++++--
 arch/arm/mach-omap2/board-devkit8000.c       |    3 ++-
 arch/arm/mach-omap2/board-h4.c               |    2 +-
 arch/arm/mach-omap2/board-omap3evm.c         |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c       |    2 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c |    3 ++-
 arch/arm/mach-omap2/board-zoom-debugboard.c  |    3 ++-
 arch/arm/mach-omap2/board-zoom-peripherals.c |    6 ++++--
 arch/arm/mach-omap2/common-board-devices.c   |    2 +-
 11 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 7370983..5a1b6af 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -230,12 +230,12 @@ static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = {
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2D),
 		.flags = I2C_CLIENT_WAKE,
-		.irq = OMAP_GPIO_IRQ(78),
 	},
 };
 
 static int __init omap2430_i2c_init(void)
 {
+	sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
 	omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
 			ARRAY_SIZE(sdp2430_i2c1_boardinfo));
 	omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 4e90715..a09c699 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -873,7 +873,6 @@ static void __init omap4_sdp4430_wifi_mux_init(void)
 }
 
 static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
 	.board_ref_clock = WL12XX_REFCLOCK_26,
 	.board_tcxo_clock = WL12XX_TCXOCLOCK_26,
 };
@@ -883,6 +882,7 @@ static void __init omap4_sdp4430_wifi_init(void)
 	int ret;
 
 	omap4_sdp4430_wifi_mux_init();
+	omap4_sdp4430_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
 	ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
 	if (ret)
 		pr_err("Error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index ac77382..7dd9d4d 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -136,8 +136,6 @@ static struct resource apollon_smc91x_resources[] = {
 		.flags  = IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
-		.end	= OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -341,6 +339,10 @@ static void __init omap_apollon_init(void)
 	 * You have to mux them off in device drivers later on
 	 * if not needed.
 	 */
+	apollon_devices[1]->resource[1].start =
+					gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
+	apollon_devices[1]->resource[1].end =
+					gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
 	platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index e873063..e947dc7 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -410,7 +410,6 @@ static struct resource omap_dm9000_resources[] = {
 		.flags		= IORESOURCE_MEM,
 	},
 	[2] = {
-		.start		= OMAP_GPIO_IRQ(OMAP_DM9000_GPIO_IRQ),
 		.flags		= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
 	},
 };
@@ -637,6 +636,8 @@ static void __init devkit8000_init(void)
 	omap_dm9000_init();
 
 	devkit8000_i2c_init();
+	devkit8000_devices[2]->resource[2].start =
+					gpio_to_irq(OMAP_DM9000_GPIO_IRQ);
 	platform_add_devices(devkit8000_devices,
 			ARRAY_SIZE(devkit8000_devices));
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 54af800..0bbbabe 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -348,7 +348,6 @@ static struct at24_platform_data m24c01 = {
 static struct i2c_board_info __initdata h4_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(125),
 	},
 	{	/* EEPROM on mainboard */
 		I2C_BOARD_INFO("24c01", 0x52),
@@ -377,6 +376,7 @@ static void __init omap_h4_init(void)
 	 */
 
 	board_mkp_init();
+	h4_i2c_board_info[0].irq = gpio_to_irq(125);
 	i2c_register_board_info(1, h4_i2c_board_info,
 			ARRAY_SIZE(h4_i2c_board_info));
 
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c877236..eed88a4 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -487,7 +487,6 @@ static struct platform_device omap3evm_wlan_regulator = {
 };
 
 struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
 	.board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
 };
 #endif
@@ -623,6 +622,7 @@ static void __init omap3_evm_wl12xx_init(void)
 	int ret;
 
 	/* WL12xx WLAN Init */
+	omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
 	ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 28fc271..4496007 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -199,7 +199,6 @@ static struct platform_device omap_vwlan_device = {
 };
 
 struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
-	.irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
 	/* PANDA ref clock is 38.4 MHz */
 	.board_ref_clock = 2,
 };
@@ -494,6 +493,7 @@ static void __init omap4_panda_init(void)
 		package = OMAP_PACKAGE_CBL;
 	omap4_mux_init(board_mux, NULL, package);
 
+	omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
 	ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index acb4e77..1cec076 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -172,7 +172,6 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
 		.modalias		= "tsc2005",
 		.bus_num		= 1,
 		.chip_select		= 0,
-		.irq			= OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
 		.max_speed_hz		= 6000000,
 		.controller_data	= &tsc2005_mcspi_config,
 		.platform_data		= &tsc2005_pdata,
@@ -1124,6 +1123,8 @@ static void __init rx51_init_tsc2005(void)
 		"tsc2005 reset");
 	if (r >= 0) {
 		tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
+		rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq =
+					gpio_to_irq(RX51_TSC2005_IRQ_GPIO);
 	} else {
 		printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
 		tsc2005_pdata.esd_timeout_ms = 0;
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 369c2eb..1e8540e 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -43,7 +43,6 @@ static inline void __init zoom_init_smsc911x(void)
 static struct plat_serial8250_port serial_platform_data[] = {
 	{
 		.mapbase	= ZOOM_UART_BASE,
-		.irq		= OMAP_GPIO_IRQ(102),
 		.flags		= UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ,
 		.irqflags	= IRQF_SHARED | IRQF_TRIGGER_RISING,
 		.iotype		= UPIO_MEM,
@@ -89,6 +88,8 @@ static inline void __init zoom_init_quaduart(void)
 	if (gpio_request_one(quart_gpio, GPIOF_IN, "TL16CP754C GPIO") < 0)
 		printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n",
 								quart_gpio);
+
+	serial_platform_data[0].irq = gpio_to_irq(102);
 }
 
 static inline int omap_zoom_debugboard_detect(void)
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index c126461..a489f82 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -193,7 +193,6 @@ static struct platform_device omap_vwlan_device = {
 };
 
 static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO),
 	/* ZOOM ref clock is 26 MHz */
 	.board_ref_clock = 1,
 };
@@ -296,7 +295,10 @@ static void enable_board_wakeup_source(void)
 
 void __init zoom_peripherals_init(void)
 {
-	int ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
+	int ret;
+
+	omap_zoom_wlan_data.irq = gpio_to_irq(OMAP_ZOOM_WLAN_IRQ_GPIO);
+	ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
 
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index bcb0c58..4cb17b4 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -79,7 +79,7 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 	ads7846_config.gpio_pendown = gpio_pendown;
 
 	spi_bi->bus_num	= bus_num;
-	spi_bi->irq	= OMAP_GPIO_IRQ(gpio_pendown);
+	spi_bi->irq	= gpio_to_irq(gpio_pendown);
 
 	if (board_pdata)
 		spi_bi->platform_data = board_pdata;
-- 
1.7.0.4



From richard.zhao at linaro.org  Fri Mar 16 08:25:45 2012
From: richard.zhao at linaro.org (Richard Zhao)
Date: Fri, 16 Mar 2012 20:25:45 +0800
Subject: [PATCH v7 3/3] clk: basic clock hardware types
In-Reply-To: <1331878280-2758-4-git-send-email-mturquette@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-4-git-send-email-mturquette@linaro.org>
Message-ID: <20120316122542.GA1774@richard-laptop>

[...]
> +static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
> +		unsigned long *best_parent_rate)
> +{
> +	struct clk_divider *divider = to_clk_divider(hw);
> +	int i, bestdiv = 0;
> +	unsigned long parent_rate, best = 0, now, maxdiv;
> +
> +	if (!rate)
> +		rate = 1;
> +
> +	maxdiv = (1 << divider->width);
> +
> +	if (divider->flags & CLK_DIVIDER_ONE_BASED)
> +		maxdiv--;
> +
> +	if (!best_parent_rate) {
> +		parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
> +		bestdiv = DIV_ROUND_UP(parent_rate, rate);
> +		bestdiv = bestdiv == 0 ? 1 : bestdiv;
> +		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
> +		return bestdiv;
> +	}
> +
> +	/*
> +	 * The maximum divider we can use without overflowing
> +	 * unsigned long in rate * i below
> +	 */
> +	maxdiv = min(ULONG_MAX / rate, maxdiv);
> +
> +	for (i = 1; i <= maxdiv; i++) {
> +		parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
> +				MULT_ROUND_UP(rate, i));
> +		now = parent_rate / i;
> +		if (now <= rate && now > best) {
> +			bestdiv = i;
> +			best = now;
> +			*best_parent_rate = parent_rate;
Better add		if (now == rate)
				break;
There may be more than one hit for (now == rate). We'd better select
smallest div, thus smallest parent_rate.

It's the same comment for v6, but not show stopper.

Thanks
Richard
> +		}
> +	}
> +
> +	if (!bestdiv) {
> +		bestdiv = (1 << divider->width);
> +		if (divider->flags & CLK_DIVIDER_ONE_BASED)
> +			bestdiv--;
> +		*best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
> +	}
> +
> +	return bestdiv;
> +}
 


From sr at denx.de  Fri Mar 16 08:33:22 2012
From: sr at denx.de (Stefan Roese)
Date: Fri, 16 Mar 2012 13:33:22 +0100
Subject: [PATCH v4] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <201203161209.18292.arnd@arndb.de>
References: <1331890216-8361-1-git-send-email-sr@denx.de>
 <20120316115022.GF7757@game.jcrosoft.org> <201203161209.18292.arnd@arndb.de>
Message-ID: <201203161333.22524.sr@denx.de>

On Friday 16 March 2012 13:09:18 Arnd Bergmann wrote:
> On Friday 16 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 10:30 Fri 16 Mar     , Stefan Roese wrote:
> > > This patch adds a generic target for SPEAr600 board that can be
> > > configured via the device-tree. Currently the following devices
> > > are supported via the devicetree:
> > > 
> > > - VIC interrupts
> > > - PL011 UART
> > > - PL061 GPIO
> > > - Synopsys DW I2C
> > > - Synopsys DW ethernet
> > > 
> > > Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
> > > follow in later patches.
> > 
> > so drop USB, nand & co from the dtsi
> > 
> > this will be add later when the binding will documentated and Acked
> 
> I actually like to see the devices in there, and it already helped
> figure out that there are two buses instead of just one. Maybe we
> can agree on putting them in the file but commenting them out using
> /* */ with an added notice that they will get enabled once we have
> bindings?

It would be great to have a decision on this. I'm leaving for a short vacation 
in a few hours and would like to have the new (hopefully final) patch out 
before that.

Thanks for all your comments,
Stefan


From sr at denx.de  Fri Mar 16 08:34:11 2012
From: sr at denx.de (Stefan Roese)
Date: Fri, 16 Mar 2012 13:34:11 +0100
Subject: [PATCH v4] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <201203161214.35929.arnd@arndb.de>
References: <1331890216-8361-1-git-send-email-sr@denx.de>
 <201203161214.35929.arnd@arndb.de>
Message-ID: <201203161334.11377.sr@denx.de>

On Friday 16 March 2012 13:14:35 Arnd Bergmann wrote:
> On Friday 16 March 2012, Stefan Roese wrote:
> > v4:
> > - Added memory node to all dts/dtsi files
> > - Reorganizes bus topology in the dtsi file, to match the
> > 
> >   real SoC layout
> 
> Looks good.
> 
> > +
> > +	ahb {
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		compatible = "simple-bus";
> > +		ranges;
> > +
> > +		vic0: interrupt-controller at f1100000 {
> > +			compatible = "arm,pl190-vic";
> > +			interrupt-controller;
> > +			reg = <0xf1100000 0x1000>;
> > +			#interrupt-cells = <1>;
> > +		};
> > +
> > ...
> > +		apb {
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			compatible = "simple-bus";
> > +			ranges;
> > +
> > +			serial at d0000000 {
> > +				compatible = "arm,pl011", "arm,primecell";
> > +				reg = <0xd0000000 0x1000>;
> > +				interrupt-parent = <&vic0>;
> > +				interrupts = <24>;
> > +			};
> > ...
> > +		};
> > +	};
> > +};
> 
> I would prefer to see non-empty ranges properties here. I expected the
> buses to be contiguous address ranges per bus, but apparently that
> is not the case -- you have 0xd... and 0xf... on both of them.

Yes, Its quite ugly.
 
> The simplest ranges property would be to have in the ahb node:
> 
> 	ranges = <0xd0000000 0xd0000000 0x30000000>;
> 
> Which just means that the bus is limited to those addresses (if that is
> indeed the case -- I don't know much about ahb and apb).

Okay, I'll add those ranges. Even though I personally don't find it more 
descriptive this way.

Thanks,
Stefan


From arnd at arndb.de  Fri Mar 16 08:36:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 12:36:35 +0000
Subject: [PATCH 0/5] MMC: mmci: Provide bindings for Device Tree
In-Reply-To: <CACRpkdbyVXA+GxRtVL+JGPorp0ULJmeUEUZPxVxOT8W1-WmeMw@mail.gmail.com>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <201203152058.31398.arnd@arndb.de>
 <CACRpkdbyVXA+GxRtVL+JGPorp0ULJmeUEUZPxVxOT8W1-WmeMw@mail.gmail.com>
Message-ID: <201203161236.36088.arnd@arndb.de>

On Friday 16 March 2012, Linus Walleij wrote:
> On Thu, Mar 15, 2012 at 9:58 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > [Per]
> >> The stedma40 filter function is not really specific for ux500. ux500
> >> use stedma40 but it should be possible to replace this DMA.IP with
> >> some other DMA-controller. This is board specific configuration. You
> >> should not need to change the mmci-driver just because the dma-driver
> >> has changed, right?
> >> Or will the board-configuration now be placed in mmci-ux500?
> >
> > Right, the DMA configuration does not really belong in there, but
> > the voltage setup might (unless we convert that to the regulator
> > setup).
> 
> The voltage to power the card is already using the regulator
> framework with the MMC-specific helpers in the MMCI driver.
> 
> But I guess you're after modelling the levelshifter as a regulator?
> 
> Basically the level shifter is a separate device has two voltage
> inputs A and B (from other regulators) that is controlled by a
> simple GPIO to select voltage A or B to drive the signals to
> the card.
> 
> That could probably be modelled as a regulator with two
> volategs for sure, but then we should maybe create a more
> generic "struct level_shifter_regulator" (or whatever) for the
> concept as a whole.

Ok, thanks for the explanation.

> Let's page Mark about what to do with levelshifters and whether
> they are regulators of sorts in his book.

It does sound appealing, especially because this one could be
done completely generically by defining a regulator that has
a bunch of other regulators as well as a set of gpio lines as
inputs and one output that can be used in other devices. We
would probably only use this one together with device tree then.

	Arnd


From sshtylyov at ru.mvista.com  Fri Mar 16 08:42:16 2012
From: sshtylyov at ru.mvista.com (Sergei Shtylyov)
Date: Fri, 16 Mar 2012 16:42:16 +0400
Subject: [PATCH 2/2] arm: omap3: pm34xx.c: Replace printk() with
 appropriate pr_*()
In-Reply-To: <1331852833-4357-3-git-send-email-mgreer@animalcreek.com>
References: <1331852833-4357-1-git-send-email-mgreer@animalcreek.com>
 <1331852833-4357-3-git-send-email-mgreer@animalcreek.com>
Message-ID: <4F633528.1040305@ru.mvista.com>

Hello.

On 16-03-2012 3:07, Mark A. Greer wrote:

> From: "Mark A. Greer" <mgreer at animalcreek.com>

> Currently, pm34xx.c has a mix of printk() and pr_*() statements
> so replace the printk() statements with the equivalent pr_*()
> statements.

> Signed-off-by: Mark A. Greer <mgreer at animalcreek.com>
> ---
>   arch/arm/mach-omap2/pm34xx.c |   17 ++++++++---------
>   1 file changed, 8 insertions(+), 9 deletions(-)

> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index af8d741..495e509 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
[...]
> @@ -463,7 +462,7 @@ restore:
>   	list_for_each_entry(pwrst,&pwrst_list, node) {
>   		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
>   		if (state>  pwrst->next_state) {
> -			printk(KERN_INFO "Powerdomain (%s) didn't enter "
> +			pr_info("Powerdomain (%s) didn't enter "
>   			       "target state %d\n",

    Last line should have been realigned I think.

>   			       pwrst->pwrdm->name, pwrst->next_state);
>   			ret = -1;
> @@ -471,9 +470,9 @@ restore:
>   		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
>   	}
>   	if (ret)
> -		printk(KERN_ERR "Could not enter target state in pm_suspend\n");
> +		pr_err("Could not enter target state in pm_suspend\n");
>   	else
> -		printk(KERN_INFO "Successfully put all powerdomains "
> +		pr_info("Successfully put all powerdomains "
>   		       "to target state\n");

    Last line should have been realigned I think.

>
>   	return ret;
> @@ -865,7 +864,7 @@ static int __init omap3_pm_init(void)
>   		omap3_secure_ram_storage =
>   			kmalloc(0x803F, GFP_KERNEL);
>   		if (!omap3_secure_ram_storage)
> -			printk(KERN_ERR "Memory allocation failed when"
> +			pr_err("Memory allocation failed when"

    BTW, space after "when" is missing here.

>   					"allocating for secure sram context\n");

    Should have been realigned I think.

WBR, Sergei


From arnd at arndb.de  Fri Mar 16 08:48:15 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 12:48:15 +0000
Subject: [PATCH 2/5] MMC: mmci: Seperate ARM variants from generic code
In-Reply-To: <20120315203037.GA2311@n2100.arm.linux.org.uk>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <201203151823.32882.arnd@arndb.de>
 <20120315203037.GA2311@n2100.arm.linux.org.uk>
Message-ID: <201203161248.15490.arnd@arndb.de>

On Thursday 15 March 2012, Russell King - ARM Linux wrote:
> On Thu, Mar 15, 2012 at 06:23:32PM +0000, Arnd Bergmann wrote:
> > 
> > * we want to get rid of arch/arm/mach-ux500/board-mop500-sdi.c
> > * the sdi0_configure() and mop500_sdi0_vdd_handler() functions
> >   need to be moved somewhere in order to do that, so they should
> >   be with the driver.
> 
> I don't believe they should.  MMCI _is_ the peripheral itself.  All the
> stuff that's in board-mop500-sdi.c seems to be doing is configuration
> type stuff for the SoC that its been integrated into.  Are you seriously
> advocating having multiple drivers for essentially the same hardware?

It's basically the same we have for sdhci or ohci, or even the various
8250 versions. There is usually an identical core used in a number of
chips with slight variantions. In some cases it's better to describe
them as quirks of one driver, in other cases it's better abstract
them as separate driver files. The debate is just over which of these
two cases mmci fits into.

> > * if we want to have a separate probe function, we also need to
> >   have a separate amba_driver structure
> > * the variant_data in mmci.c belongs with the amba_id, so that
> >   also gets moved to the ux500 file.
> > 
> > If you have a better solution for one or more of these, I'm
> > all ears.
> 
> Are you really advocating having mmci_foo.c where foo is an ever
> increasing number of SoCs with the MMCI integrated because you want
> to integrate SoC specific details into the MMCI peripheral driver?

Only when they are significantly different from the common one.
According to your arguments above, the ux500 one might not be
different enough, but if something comes along that needs something
wildly different while still sharing a lot of the other code,
I would certainly use the same model.

> > The alternatives that I can see are:
> > a) keep using auxdata to supply a platform_data pointer and
> >    do everything in the main driver. Problem: we want to
> >    avoid auxdata if possible
> > b) move the code from patch 4 into mmci.c using #ifdef.
> >    Problem: it's ugly code that has nothing to do with mmci
> >    in general.
> > c) use the regulator framework to do the voltage selection
> >    here, and have only generic code in mmci.c. This may
> >    be the best solution, but I have no idea if this is
> >    actually possible, or how to do it.
> 
> Let's ignore the DMA stuff for the time being - that's a separate problem
> which needs to be addressed once we work out how to deal with how DMA
> engine stuff gets resolved with DT based systems.

Agreed.

> The remainder of it (mmci_platform_data) looks like it can be easily
> represented as DT properties, the exception to that is the ios_handler.
> I think the right solution for that is to move to the regulator framework,
> but allow the driver to continue having the ios callback if there is
> no attached regulator.  It needs that because of the four integrated
> regulator control bits (which are entirely undefined.)

Yes, that's what I was not sure about whether it's worth it. If we do this,
I absolutely agree that there is no need to split mmci.c.

> We _do_ need a solution for GPIO-controlled voltage regulators, as these
> are actually quite common - see the various soc-common using PCMCIA
> drivers.
> 
> So I think actually a bit more thought is required here, and there's a
> need to use some of the facilities such as regulator which are now present
> that weren't when the driver was originally written some 9 years ago.

Ok. Let's see what Mark has to say about this.

	Arnd


From notasas at gmail.com  Fri Mar 16 08:49:54 2012
From: notasas at gmail.com (Grazvydas Ignotas)
Date: Fri, 16 Mar 2012 14:49:54 +0200
Subject: [PATCH] OMAP: HSMMC: avoid erratum workaround when transceiver is
 attached
Message-ID: <1331902194-4679-1-git-send-email-notasas@gmail.com>

If transceiver is attached to a MMC host of ES2.1 OMAP, it seems
2.1.1.128 erratum doesn't apply and there is no data corruption,
probably because of different signal timing. The workaround for this
erratum disables multiblock reads, which causes dramatic loss of
performance (over 75% slower), so avoid it when transceiver is present.

Cc: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Grazvydas Ignotas <notasas at gmail.com>
---
 arch/arm/mach-omap2/hsmmc.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 100db62..b0268ea 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -506,6 +506,13 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
 	if (oh->dev_attr != NULL) {
 		mmc_dev_attr = oh->dev_attr;
 		mmc_data->controller_flags = mmc_dev_attr->flags;
+		/*
+		 * erratum 2.1.1.128 doesn't apply if board has
+		 * a transceiver is attached
+		 */
+		if (hsmmcinfo->transceiver)
+			mmc_data->controller_flags &=
+				~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
 	}
 
 	pdev = platform_device_alloc(name, ctrl_nr - 1);
-- 
1.7.0.4



From arnd at arndb.de  Fri Mar 16 08:50:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 12:50:11 +0000
Subject: [GIT PULL] Samsung SoC EXYNOS5250 arch for v3.4
In-Reply-To: <4F61FA0D.1050007@samsung.com>
References: <4F61FA0D.1050007@samsung.com>
Message-ID: <201203161250.11353.arnd@arndb.de>

On Thursday 15 March 2012, Kukjin Kim wrote:
> Hi Arnd, Olof,
> 
> Thank you for kindly review for EXYNOS5 and addressed comments.
> 
> Here are 'pull request' for supporting EXYNOS5250.
> 
> Please pull from:
>    git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
> next/soc-exynos5250-arch
> 
> It is based on next/devel-samsung-dma which has been pulled into arm-soc 
> to avoid merge conflicts, because they touches same files.
> And it is including additional two commits, one commit for fix 
> exynos4-dt build error which is caused by this series and one for 
> supporting lcd clkdev.
> 
> If any problems, please kindly let me know.

As you may have noticed from Stephen's notification about the merge
conflict, I have put this into the next/soc2 branch now.

I'm not too happy with the resolution of my comments, but in the
end I think it's better to have it in the tree than not have it.
While you did reply with explanations for why some of the patches
were necessary, you did not actually put the explanations into 
the changeset descriptions but only sent a reply to my emails.

I don't think that the merge conflict is problematic, especially
since Linus won't see the same thing that Stephen did, but as I
wrote in the other mail, please check that my resolution was correct.

	Arnd


From arnd at arndb.de  Fri Mar 16 08:52:54 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 12:52:54 +0000
Subject: [PATCH v4] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <201203161333.22524.sr@denx.de>
References: <1331890216-8361-1-git-send-email-sr@denx.de>
 <201203161209.18292.arnd@arndb.de> <201203161333.22524.sr@denx.de>
Message-ID: <201203161252.54953.arnd@arndb.de>

On Friday 16 March 2012, Stefan Roese wrote:
> > I actually like to see the devices in there, and it already helped
> > figure out that there are two buses instead of just one. Maybe we
> > can agree on putting them in the file but commenting them out using
> > /* */ with an added notice that they will get enabled once we have
> > bindings?
> 
> It would be great to have a decision on this. I'm leaving for a short vacation 
> in a few hours and would like to have the new (hopefully final) patch out 
> before that.

It's not a show-stopper for me either way, your patches look great.

	Arnd


From sr at denx.de  Fri Mar 16 08:57:05 2012
From: sr at denx.de (Stefan Roese)
Date: Fri, 16 Mar 2012 13:57:05 +0100
Subject: [PATCH v4] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <201203161252.54953.arnd@arndb.de>
References: <1331890216-8361-1-git-send-email-sr@denx.de>
 <201203161333.22524.sr@denx.de> <201203161252.54953.arnd@arndb.de>
Message-ID: <201203161357.06146.sr@denx.de>

On Friday 16 March 2012 13:52:54 Arnd Bergmann wrote:
> On Friday 16 March 2012, Stefan Roese wrote:
> > > I actually like to see the devices in there, and it already helped
> > > figure out that there are two buses instead of just one. Maybe we
> > > can agree on putting them in the file but commenting them out using
> > > /* */ with an added notice that they will get enabled once we have
> > > bindings?
> > 
> > It would be great to have a decision on this. I'm leaving for a short
> > vacation in a few hours and would like to have the new (hopefully final)
> > patch out before that.
> 
> It's not a show-stopper for me either way, your patches look great.

Thanks Arnd.

I'll leave the devices included then, and still disabled. Stay tuned...

Thanks,
Stefan


From sr at denx.de  Fri Mar 16 09:03:23 2012
From: sr at denx.de (Stefan Roese)
Date: Fri, 16 Mar 2012 14:03:23 +0100
Subject: [PATCH v5] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
Message-ID: <1331903003-14045-1-git-send-email-sr@denx.de>

This patch adds a generic target for SPEAr600 board that can be
configured via the device-tree. Currently the following devices
are supported via the devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
follow in later patches.

Only the spear600-evb is currently supported. Other SPEAr600
based boards will follow later.

Since the current mainline SPEAr600 code only supports the SPEAr600
evaluation board, with nearly zero peripheral devices (only UART
and GPIO), it makes sense to switch over to DT based configuration
completely now. So this patch also removes all non-DT stuff, mainly
platform device data. The files spear600.c and spear600_evb.c are
removed completely.

Signed-off-by: Stefan Roese <sr at denx.de>
Acked-by: Viresh Kumar <viresh.kumar at st.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
v5:
- Disabled all non-core devices in spear600.dtsi
- Enabled used devices in spear600-evb.dts
- Added values to ranges property for busses

v4:
- Added memory node to all dts/dtsi files
- Reorganizes bus topology in the dtsi file, to match the
  real SoC layout

v3:
- Removed non-DT SPEAr600 board support completely
- Removed OF_DEV_AUXDATA and changed clkdev instead, since we
  don't support non-DT targets any more
- Changed gmac0 -> gmac etc for single instance devices in the
  dts
- Added max memory size to memory node (instead of 0)
- Dropped mac-address property
- Removed some headers from spear6xx.c

v2:
- Added DT support to spear6xx.c instead of creating board-dt.c
- Removed UART (PL011) and GPIO (PL061) platform data for
  devicetree board port. This works now via DT probing
- Added OF_DEV_AUXDATA for clock device name matching for some
  device drivers
- Removed sper600.c file completely
- Added DW I2C and ethernet nodes to the dts files
- Added other DT nodes (SMI, FSMC, ECHI, OHCI), currently disabled
  since the corresponding device drivers don't support DT probing
- Removed Linaro/FSL copyright notice from SPEAr DT files (copy-paste cruft)
- Many smaller modification to the dts/dtsi files
- Changed Documentation/devicetree/bindings/arm/spear.txt to match
  the changed bindings


 Documentation/devicetree/bindings/arm/spear.txt |    8 ++
 arch/arm/boot/dts/spear600-evb.dts              |   47 ++++++
 arch/arm/boot/dts/spear600.dtsi                 |  174 +++++++++++++++++++++++
 arch/arm/mach-spear6xx/Kconfig                  |    7 +-
 arch/arm/mach-spear6xx/Makefile                 |    6 -
 arch/arm/mach-spear6xx/clock.c                  |   14 +-
 arch/arm/mach-spear6xx/spear600.c               |   25 ----
 arch/arm/mach-spear6xx/spear600_evb.c           |   54 -------
 arch/arm/mach-spear6xx/spear6xx.c               |  132 +++++------------
 9 files changed, 276 insertions(+), 191 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
 create mode 100644 arch/arm/boot/dts/spear600-evb.dts
 create mode 100644 arch/arm/boot/dts/spear600.dtsi
 delete mode 100644 arch/arm/mach-spear6xx/spear600.c
 delete mode 100644 arch/arm/mach-spear6xx/spear600_evb.c

diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
new file mode 100644
index 0000000..f8e54f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -0,0 +1,8 @@
+ST SPEAr Platforms Device Tree Bindings
+---------------------------------------
+
+Boards with the ST SPEAr600 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear600";
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
new file mode 100644
index 0000000..636292e
--- /dev/null
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear600.dtsi"
+
+/ {
+	model = "ST SPEAr600 Evaluation Board";
+	compatible = "st,spear600-evb", "st,spear600";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x10000000>;
+	};
+
+	ahb {
+		gmac: ethernet at e0800000 {
+			phy-mode = "gmii";
+			status = "okay";
+		};
+
+		apb {
+			serial at d0000000 {
+				status = "okay";
+			};
+
+			serial at d0080000 {
+				status = "okay";
+			};
+
+			i2c at d0200000 {
+				clock-frequency = <400000>;
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
new file mode 100644
index 0000000..ebe0885
--- /dev/null
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "st,spear600";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+		vic0: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		vic1: interrupt-controller at f1000000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		gmac: ethernet at e0800000 {
+			compatible = "st,spear600-gmac";
+			reg = <0xe0800000 0x8000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <24 23>;
+			interrupt-names = "macirq", "eth_wake_irq";
+			status = "disabled";
+		};
+
+		fsmc: flash at d1800000 {
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd1800000 0x1000	/* FSMC Register */
+			       0xd2000000 0x4000>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x20000>;
+			st,cle-off = <0x10000>;
+			status = "disabled";
+		};
+
+		smi: flash at fc000000 {
+			compatible = "st,spear600-smi";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xfc000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <12>;
+			status = "disabled";
+		};
+
+		ehci at e1800000 {
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe1800000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <27>;
+			status = "disabled";
+		};
+
+		ehci at e2000000 {
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe2000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <29>;
+			status = "disabled";
+		};
+
+		ohci at e1900000 {
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe1900000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <26>;
+			status = "disabled";
+		};
+
+		ohci at e2100000 {
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe2100000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <28>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+			serial at d0000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0000000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <24>;
+				status = "disabled";
+			};
+
+			serial at d0080000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0080000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <25>;
+				status = "disabled";
+			};
+
+			/* local/cpu GPIO */
+			gpio0: gpio at f0100000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xf0100000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <18>;
+			};
+
+			/* basic GPIO */
+			gpio1: gpio at fc980000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xfc980000 0x1000>;
+				interrupt-parent = <&vic1>;
+				interrupts = <19>;
+			};
+
+			/* appl GPIO */
+			gpio2: gpio at d8100000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xd8100000 0x1000>;
+				interrupt-parent = <&vic1>;
+				interrupts = <4>;
+			};
+
+			i2c at d0200000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,designware-i2c";
+				reg = <0xd0200000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <28>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
index ff4ae5b..fbe298b 100644
--- a/arch/arm/mach-spear6xx/Kconfig
+++ b/arch/arm/mach-spear6xx/Kconfig
@@ -5,11 +5,12 @@
 if ARCH_SPEAR6XX
 
 menu "SPEAr6xx Implementations"
-config BOARD_SPEAR600_EVB
-	bool "SPEAr600 Evaluation Board"
+config BOARD_SPEAR600_DT
+	bool "SPEAr600 generic board configured via device-tree"
 	select MACH_SPEAR600
+	select USE_OF
 	help
-	  Supports ST SPEAr600 Evaluation Board
+	  Supports ST SPEAr600 boards configured via the device-tree
 
 endmenu
 
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index cc1a4d8..76e5750 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -4,9 +4,3 @@
 
 # common files
 obj-y	+= clock.o spear6xx.o
-
-# spear600 specific files
-obj-$(CONFIG_MACH_SPEAR600) += spear600.o
-
-# spear600 boards files
-obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index ac70e0d..358f280 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -641,8 +641,8 @@ static struct clk_lookup spear_clk_lookups[] = {
 	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
 	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
 	{ .con_id = "gpt3_synth_clk",	.clk = &gpt3_synth_clk},
-	{ .dev_id = "uart0",		.clk = &uart0_clk},
-	{ .dev_id = "uart1",		.clk = &uart1_clk},
+	{ .dev_id = "d0000000.serial",	.clk = &uart0_clk},
+	{ .dev_id = "d0080000.serial",	.clk = &uart1_clk},
 	{ .dev_id = "firda",		.clk = &firda_clk},
 	{ .dev_id = "clcd",		.clk = &clcd_clk},
 	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
@@ -655,20 +655,20 @@ static struct clk_lookup spear_clk_lookups[] = {
 	{ .con_id = "usbh.1_clk",	.clk = &usbh1_clk},
 	/* clock derived from ahb clk */
 	{ .con_id = "apb_clk",		.clk = &apb_clk},
-	{ .dev_id = "i2c_designware.0",	.clk = &i2c_clk},
+	{ .dev_id = "d0200000.i2c",	.clk = &i2c_clk},
 	{ .dev_id = "dma",		.clk = &dma_clk},
 	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
 	{ .dev_id = "gmac",		.clk = &gmac_clk},
 	{ .dev_id = "smi",		.clk = &smi_clk},
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
+	{ .dev_id = "fsmc-nand",	.clk = &fsmc_clk},
 	/* clock derived from apb clk */
 	{ .dev_id = "adc",		.clk = &adc_clk},
 	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
 	{ .dev_id = "ssp-pl022.1",	.clk = &ssp1_clk},
 	{ .dev_id = "ssp-pl022.2",	.clk = &ssp2_clk},
-	{ .dev_id = "gpio0",		.clk = &gpio0_clk},
-	{ .dev_id = "gpio1",		.clk = &gpio1_clk},
-	{ .dev_id = "gpio2",		.clk = &gpio2_clk},
+	{ .dev_id = "f0100000.gpio",	.clk = &gpio0_clk},
+	{ .dev_id = "fc980000.gpio",	.clk = &gpio1_clk},
+	{ .dev_id = "d8100000.gpio",	.clk = &gpio2_clk},
 };
 
 void __init spear6xx_clk_init(void)
diff --git a/arch/arm/mach-spear6xx/spear600.c b/arch/arm/mach-spear6xx/spear600.c
deleted file mode 100644
index d0e6eea..0000000
--- a/arch/arm/mach-spear6xx/spear600.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/spear600.c
- *
- * SPEAr600 machine source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/ptrace.h>
-#include <asm/irq.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* Add spear600 specific devices here */
-
-void __init spear600_init(void)
-{
-	/* call spear6xx family common init function */
-	spear6xx_init();
-}
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
deleted file mode 100644
index c6e4254..0000000
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/spear600_evb.c
- *
- * SPEAr600 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-static struct amba_device *amba_devs[] __initdata = {
-	&gpio_device[0],
-	&gpio_device[1],
-	&gpio_device[2],
-	&uart_device[0],
-	&uart_device[1],
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-};
-
-static void __init spear600_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear600 machine init function */
-	spear600_init();
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear6xx_map_io,
-	.init_irq	=	spear6xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear6xx_timer,
-	.init_machine	=	spear600_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index e0f6628..2ed8b14 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -6,111 +6,21 @@
  * Copyright (C) 2009 ST Microelectronics
  * Rajeev Kumar<rajeev-dlh.kumar at st.com>
  *
+ * Copyright 2012 Stefan Roese <sr at denx.de>
+ *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
-#include <mach/irqs.h>
-
-/* Add spear6xx machines common devices here */
-/* uart device registration */
-struct amba_device uart_device[] = {
-	{
-		.dev = {
-			.init_name = "uart0",
-		},
-		.res = {
-			.start = SPEAR6XX_ICM1_UART0_BASE,
-			.end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_UART_0, NO_IRQ},
-	}, {
-		.dev = {
-			.init_name = "uart1",
-		},
-		.res = {
-			.start = SPEAR6XX_ICM1_UART1_BASE,
-			.end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_UART_1, NO_IRQ},
-	}
-};
-
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data[] = {
-	{
-		.gpio_base	= 0,
-		.irq_base	= SPEAR_GPIO0_INT_BASE,
-	}, {
-		.gpio_base	= 8,
-		.irq_base	= SPEAR_GPIO1_INT_BASE,
-	}, {
-		.gpio_base	= 16,
-		.irq_base	= SPEAR_GPIO2_INT_BASE,
-	},
-};
-
-struct amba_device gpio_device[] = {
-	{
-		.dev = {
-			.init_name = "gpio0",
-			.platform_data = &gpio_plat_data[0],
-		},
-		.res = {
-			.start = SPEAR6XX_CPU_GPIO_BASE,
-			.end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_LOCAL_GPIO, NO_IRQ},
-	}, {
-		.dev = {
-			.init_name = "gpio1",
-			.platform_data = &gpio_plat_data[1],
-		},
-		.res = {
-			.start = SPEAR6XX_ICM3_GPIO_BASE,
-			.end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_BASIC_GPIO, NO_IRQ},
-	}, {
-		.dev = {
-			.init_name = "gpio2",
-			.platform_data = &gpio_plat_data[2],
-		},
-		.res = {
-			.start = SPEAR6XX_ICM2_GPIO_BASE,
-			.end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1,
-			.flags = IORESOURCE_MEM,
-		},
-		.irq = {IRQ_APPL_GPIO, NO_IRQ},
-	}
-};
-
-/* This will add devices, and do machine specific tasks */
-void __init spear6xx_init(void)
-{
-	/* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear6xx_init_irq(void)
-{
-	vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_PRI_BASE, 0, ~0, 0);
-	vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0, 0);
-}
 
 /* Following will create static virtual/physical mappings */
 static struct map_desc spear6xx_io_desc[] __initdata = {
@@ -181,3 +91,33 @@ static void __init spear6xx_timer_init(void)
 struct sys_timer spear6xx_timer = {
 	.init = spear6xx_timer_init,
 };
+
+static void __init spear600_dt_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *spear600_dt_board_compat[] = {
+	"st,spear600",
+	NULL
+};
+
+static const struct of_device_id vic_of_match[] __initconst = {
+	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ /* Sentinel */ }
+};
+
+static void __init spear6xx_dt_init_irq(void)
+{
+	of_irq_init(vic_of_match);
+}
+
+DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
+	.map_io		=	spear6xx_map_io,
+	.init_irq	=	spear6xx_dt_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear6xx_timer,
+	.init_machine	=	spear600_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear600_dt_board_compat,
+MACHINE_END
-- 
1.7.9.2



From sshtylyov at mvista.com  Fri Mar 16 09:03:14 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 16 Mar 2012 17:03:14 +0400
Subject: Link for the latest patches of AHCI
In-Reply-To: <005f01cd0369$b636b360$22a41a20$%srikanth@samsung.com>
References: <005f01cd0369$b636b360$22a41a20$%srikanth@samsung.com>
Message-ID: <4F633A12.6080901@mvista.com>

Hello.

On 16-03-2012 15:41, Srikanth TS wrote:

> I tried to clone from below link as mentioned in the MAINTAINERS file for drivers/ata/.
> http://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev.git

> But This link does not exist.

> Can someone please tell me where can I find the latest merged patches, which are still not in official kernel version?

    git://github.com/jgarzik/libata-dev.git

> Regards,
> Srikanth.

WBR, Sergei

PS: Jeff, maybe it's time to update MAINTAINERS or are you still going to 
restore access to your tree at kernel.org?


From arnd at arndb.de  Fri Mar 16 09:12:47 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 13:12:47 +0000
Subject: [PULL 01/02 v2] AT91 DT2 pull request
In-Reply-To: <20120315164129.GD7757@game.jcrosoft.org>
References: <20120315155443.GB7757@game.jcrosoft.org>
 <20120315164129.GD7757@game.jcrosoft.org>
Message-ID: <201203161312.47925.arnd@arndb.de>

On Thursday 15 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
>         please find a pull with DT update for AT91
>         based on cleanup2 + DT previously pull
> 
>         with :
> 
>          - OF: boolean
>          - NAND (with generic bining and at91 fixed)
>          - RAM Controller
>          - i2c/gpio (binding + soc)
>          - PMC
>          - Reset Controller
>          - Shutdown Controller
>          - USB OHCI & ECHO (Acked)
> 
>          v2: missing usb host

Pulled both 01 and 02 into the next/dt branch now, this is all
very good stuff!

Thanks,

	Arnd


From plagnioj at jcrosoft.com  Fri Mar 16 09:11:29 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 16 Mar 2012 14:11:29 +0100
Subject: [PATCH v5] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <1331903003-14045-1-git-send-email-sr@denx.de>
References: <1331903003-14045-1-git-send-email-sr@denx.de>
Message-ID: <20120316131129.GH7757@game.jcrosoft.org>

On 14:03 Fri 16 Mar     , Stefan Roese wrote:
> This patch adds a generic target for SPEAr600 board that can be
> configured via the device-tree. Currently the following devices
> are supported via the devicetree:
> 
> - VIC interrupts
> - PL011 UART
> - PL061 GPIO
> - Synopsys DW I2C
> - Synopsys DW ethernet
> 
> Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
> follow in later patches.
> 
> Only the spear600-evb is currently supported. Other SPEAr600
> based boards will follow later.
> 
> Since the current mainline SPEAr600 code only supports the SPEAr600
> evaluation board, with nearly zero peripheral devices (only UART
> and GPIO), it makes sense to switch over to DT based configuration
> completely now. So this patch also removes all non-DT stuff, mainly
> platform device data. The files spear600.c and spear600_evb.c are
> removed completely.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>
> Acked-by: Viresh Kumar <viresh.kumar at st.com>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>


I'm not a fan to have non Documented DT binding butthey are basic so ok

Best Regards,
J.


From b-cousson at ti.com  Fri Mar 16 09:28:32 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Fri, 16 Mar 2012 14:28:32 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203161204.19800.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com> <201203161003.02163.arnd@arndb.de>
 <4F6321DB.50600@ti.com> <201203161204.19800.arnd@arndb.de>
Message-ID: <4F634000.8010408@ti.com>

On 3/16/2012 1:04 PM, Arnd Bergmann wrote:
> On Friday 16 March 2012, Cousson, Benoit wrote:
>> And it seems that other ARM SoCs are using it for the same purpose.
>> There are at least 230+ IORESOURCE_DMA instances in the kernel today.
>
> These tend to be the ones that don't use dmaengine but either the
> ISA dma api or a platform specific variant of that, right?
>
> Also, I think that most of those definitions are for the same few
> devices. The number that I see is much lower:
>
> $ git grep -l IORESOURCE_DMA drivers/ sound/ | wc -l
>       51

Gosh, good point... I've just done a dumb grep, but most of them are in 
the device creation inside arch code:-(

Assuming OMAP driver does contains omap in the name, the result is 
indeed way smaller.

git grep -l IORESOURCE_DMA drivers/ sound/ | grep omap

drivers/crypto/omap-aes.c
drivers/crypto/omap-sham.c
drivers/spi/spi-omap2-mcspi.c
drivers/tty/serial/omap-serial.c
sound/soc/omap/omap-dmic.c
sound/soc/omap/omap-hdmi.c

We do have 127 DMA requests and only 6 drivers are using them, that's a 
pity...

> Out of those, a quite number are mips or blackfin or xtensa based, or are
> for legacy ISA devices, which leaves 29 drivers for ARM.
>
>> For the moment it is still used in a lot of places, and without any
>> other better API yet, it is still useful. As written it is there only
>> for simple single DMA controller case.
>>
>> By maintaining that IORESOURCE_DMA for the moment we can adapt some
>> driver to DT without having to change the way they are retrieving
>> information. By using IORESOURCE_IRQ and IORESOURCE_MEM, we had the same
>> advantage.
>
> The main difference to IORESOURCE_IRQ and IORESOURCE_MEM that I see
> is that those are going to start for any forseeable time and are actually
> helpful in a lot of ways. We are not going to remove the single number
> space for interrupts in the next few years. For DMA, the dmaengine API
> has already moved away from the flat number space of the ISA API.
>
>> Otherwise how are we supposed to get the DMA channel for non-DT boot
>> until we have migrated everything to DT? A bunch of ARM SoC are using
>> IORESOURCE_DMA for the same purpose.
>>
>> The goal here is really to maintain that during the transition phase
>> only. As soon as the full DT support is there, we can switch to the of_ API.
>>
>> Ideally, we should define and use a generic API non dependent of DT.
>> AFAIK, that does not exist so far.
>> And since most drivers are not using dmaengine, we do not even have a
>> common DMA fmwk to define an API on top.
>>
>> I fully agree that this IORESOURCE_DMA is not scalable for multiple
>> controller, ugly, and must be avoided like the plague.
>> But what other options do we have during the transition?
>
> We could use the same binding for the nonstandard controllers, but
> keep the dma channel number lookup separate for those, and let them
> call of_get_dma_request directly.
>
> Since there are not too many drivers using those controllers with
> dma resources today, it's fairly easy to go through those as we write
> the driver bindings and just do
>
> 	err = of_get_dma_request(pdev->dev.of_node, 0,&dma);
> 	if (err) {
> 		struct resource *r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
> 		if (r)
> 			dma = r->start;
> 	}
>
> For the drivers that we convert to DT before we convert them to dmaengine,
> and not do anything if we convert them to dmaengine first.

Considering the small amount of OMAP drivers really using 
IORESOURCE_DMA, I guess this is fair enough.

Bottom-line, I do not have any more issue removing this of_dma_to_resource.


Nico,
Is that OK for you to repost the patch without this function?

Thanks,
Benoit


From nicolas.ferre at atmel.com  Fri Mar 16 09:36:05 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 16 Mar 2012 14:36:05 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <4F634000.8010408@ti.com>
References: <4F22DEF2.5000807@ti.com> <201203161003.02163.arnd@arndb.de>
 <4F6321DB.50600@ti.com> <201203161204.19800.arnd@arndb.de>
 <4F634000.8010408@ti.com>
Message-ID: <4F6341C5.4060009@atmel.com>

On 03/16/2012 02:28 PM, Cousson, Benoit :
> On 3/16/2012 1:04 PM, Arnd Bergmann wrote:
>> On Friday 16 March 2012, Cousson, Benoit wrote:
>>> And it seems that other ARM SoCs are using it for the same purpose.
>>> There are at least 230+ IORESOURCE_DMA instances in the kernel today.
>>
>> These tend to be the ones that don't use dmaengine but either the
>> ISA dma api or a platform specific variant of that, right?
>>
>> Also, I think that most of those definitions are for the same few
>> devices. The number that I see is much lower:
>>
>> $ git grep -l IORESOURCE_DMA drivers/ sound/ | wc -l
>>       51
> 
> Gosh, good point... I've just done a dumb grep, but most of them are in
> the device creation inside arch code:-(
> 
> Assuming OMAP driver does contains omap in the name, the result is
> indeed way smaller.
> 
> git grep -l IORESOURCE_DMA drivers/ sound/ | grep omap
> 
> drivers/crypto/omap-aes.c
> drivers/crypto/omap-sham.c
> drivers/spi/spi-omap2-mcspi.c
> drivers/tty/serial/omap-serial.c
> sound/soc/omap/omap-dmic.c
> sound/soc/omap/omap-hdmi.c
> 
> We do have 127 DMA requests and only 6 drivers are using them, that's a
> pity...
> 
>> Out of those, a quite number are mips or blackfin or xtensa based, or are
>> for legacy ISA devices, which leaves 29 drivers for ARM.
>>
>>> For the moment it is still used in a lot of places, and without any
>>> other better API yet, it is still useful. As written it is there only
>>> for simple single DMA controller case.
>>>
>>> By maintaining that IORESOURCE_DMA for the moment we can adapt some
>>> driver to DT without having to change the way they are retrieving
>>> information. By using IORESOURCE_IRQ and IORESOURCE_MEM, we had the same
>>> advantage.
>>
>> The main difference to IORESOURCE_IRQ and IORESOURCE_MEM that I see
>> is that those are going to start for any forseeable time and are actually
>> helpful in a lot of ways. We are not going to remove the single number
>> space for interrupts in the next few years. For DMA, the dmaengine API
>> has already moved away from the flat number space of the ISA API.
>>
>>> Otherwise how are we supposed to get the DMA channel for non-DT boot
>>> until we have migrated everything to DT? A bunch of ARM SoC are using
>>> IORESOURCE_DMA for the same purpose.
>>>
>>> The goal here is really to maintain that during the transition phase
>>> only. As soon as the full DT support is there, we can switch to the
>>> of_ API.
>>>
>>> Ideally, we should define and use a generic API non dependent of DT.
>>> AFAIK, that does not exist so far.
>>> And since most drivers are not using dmaengine, we do not even have a
>>> common DMA fmwk to define an API on top.
>>>
>>> I fully agree that this IORESOURCE_DMA is not scalable for multiple
>>> controller, ugly, and must be avoided like the plague.
>>> But what other options do we have during the transition?
>>
>> We could use the same binding for the nonstandard controllers, but
>> keep the dma channel number lookup separate for those, and let them
>> call of_get_dma_request directly.
>>
>> Since there are not too many drivers using those controllers with
>> dma resources today, it's fairly easy to go through those as we write
>> the driver bindings and just do
>>
>>     err = of_get_dma_request(pdev->dev.of_node, 0,&dma);
>>     if (err) {
>>         struct resource *r = platform_get_resource(pdev,
>> IORESOURCE_DMA, 0);
>>         if (r)
>>             dma = r->start;
>>     }
>>
>> For the drivers that we convert to DT before we convert them to
>> dmaengine,
>> and not do anything if we convert them to dmaengine first.
> 
> Considering the small amount of OMAP drivers really using
> IORESOURCE_DMA, I guess this is fair enough.
> 
> Bottom-line, I do not have any more issue removing this of_dma_to_resource.
> 
> 
> Nico,
> Is that OK for you to repost the patch without this function?

Yes sure, I will repost a V2 soon.

I also try to have an integration in DT selftest.c:
- that will show some possibilities of the API
- that will give some examples of usage (1 or 2 xlate() functions)
- that made me review my code and find a weakness
- that will allow to monitor non-regression (obviously)
=> WIP...

Bye,
-- 
Nicolas Ferre


From sourav.poddar at ti.com  Fri Mar 16 09:39:17 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 16 Mar 2012 19:09:17 +0530
Subject: [PATCH 0/2] Omap keypad cleanup and omap5 support
Message-ID: <1331905159-11255-1-git-send-email-sourav.poddar@ti.com>

The series consists of two patches.
Patch1 of the series makes omap4 keypad independent of the
architecture by moving platform_data to <linux/platform_data>

Patch2 add support for omap5 onchip keypad.

Tested on omap4430sdp using 3.3-rc6.
Tested on omap5 board using 3.1 custom kernel. 

Felipe Balbi (1):
  input: keypad: move platform_data to <linux/platform_data>

G, Manjunath Kondaiah (1):
  Input: omap-keypad: dynamically handle register offsets

 arch/arm/mach-omap2/board-4430sdp.c            |    1 +
 arch/arm/mach-omap2/devices.c                  |    1 +
 arch/arm/plat-omap/include/plat/omap4-keypad.h |    9 --
 drivers/input/keyboard/Kconfig                 |    7 +-
 drivers/input/keyboard/omap4-keypad.c          |  124 +++++++++++++++++++-----
 include/linux/platform_data/omap4-keypad.h     |   13 +++
 6 files changed, 118 insertions(+), 37 deletions(-)
 create mode 100644 include/linux/platform_data/omap4-keypad.h



From sourav.poddar at ti.com  Fri Mar 16 09:39:18 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 16 Mar 2012 19:09:18 +0530
Subject: [PATCH 1/2] input: keypad: move platform_data to <linux/platform_data>
In-Reply-To: <1331905159-11255-1-git-send-email-sourav.poddar@ti.com>
References: <1331905159-11255-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1331905159-11255-2-git-send-email-sourav.poddar@ti.com>

From: Felipe Balbi <balbi at ti.com>

This patch allows us to drop the OMAP depencendy
from the OMAP4 keypad driver.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/mach-omap2/board-4430sdp.c            |    1 +
 arch/arm/mach-omap2/devices.c                  |    1 +
 arch/arm/plat-omap/include/plat/omap4-keypad.h |    9 ---------
 drivers/input/keyboard/Kconfig                 |    1 -
 drivers/input/keyboard/omap4-keypad.c          |    2 +-
 include/linux/platform_data/omap4-keypad.h     |   13 +++++++++++++
 6 files changed, 16 insertions(+), 11 deletions(-)
 create mode 100644 include/linux/platform_data/omap4-keypad.h

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 4e90715..d16902c 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -25,6 +25,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/leds.h>
 #include <linux/leds_pwm.h>
+#include <linux/platform_data/omap4-keypad.h>
 
 #include <mach/hardware.h>
 #include <asm/hardware/gic.h>
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 283d11e..58e1d20 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -17,6 +17,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/of.h>
+#include <linux/platform_data/omap4-keypad.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
index 9fe6c87..8ad0a37 100644
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -1,15 +1,6 @@
 #ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
 #define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
 
-#include <linux/input/matrix_keypad.h>
-
-struct omap4_keypad_platform_data {
-	const struct matrix_keymap_data *keymap_data;
-
-	u8 rows;
-	u8 cols;
-};
-
 extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
 				struct omap_board_data *);
 #endif
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index cdc385b..1379daa 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -512,7 +512,6 @@ config KEYBOARD_OMAP
 
 config KEYBOARD_OMAP4
 	tristate "TI OMAP4 keypad support"
-	depends on ARCH_OMAP4
 	help
 	  Say Y here if you want to use the OMAP4 keypad.
 
diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c
index d5c5d77..e809ac0 100644
--- a/drivers/input/keyboard/omap4-keypad.c
+++ b/drivers/input/keyboard/omap4-keypad.c
@@ -31,7 +31,7 @@
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
 
-#include <plat/omap4-keypad.h>
+#include <linux/platform_data/omap4-keypad.h>
 
 /* OMAP4 registers */
 #define OMAP4_KBD_REVISION		0x00
diff --git a/include/linux/platform_data/omap4-keypad.h b/include/linux/platform_data/omap4-keypad.h
new file mode 100644
index 0000000..4eef5fb
--- /dev/null
+++ b/include/linux/platform_data/omap4-keypad.h
@@ -0,0 +1,13 @@
+#ifndef __LINUX_INPUT_OMAP4_KEYPAD_H
+#define __LINUX_INPUT_OMAP4_KEYPAD_H
+
+#include <linux/input/matrix_keypad.h>
+
+struct omap4_keypad_platform_data {
+	const struct matrix_keymap_data *keymap_data;
+
+	u8 rows;
+	u8 cols;
+};
+
+#endif /* __LINUX_INPUT_OMAP4_KEYPAD_H */
-- 
1.7.1



From sourav.poddar at ti.com  Fri Mar 16 09:39:19 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 16 Mar 2012 19:09:19 +0530
Subject: [PATCH 2/2] Input: omap-keypad: dynamically handle register offsets
In-Reply-To: <1331905159-11255-1-git-send-email-sourav.poddar@ti.com>
References: <1331905159-11255-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1331905159-11255-3-git-send-email-sourav.poddar@ti.com>

From: G, Manjunath Kondaiah <manjugk at ti.com>

Keypad controller register offsets are different for omap4
and omap5. Handle these offsets through static mapping and
assign these mappings during run time.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: G, Manjunath Kondaiah <manjugk at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 drivers/input/keyboard/Kconfig        |    6 +-
 drivers/input/keyboard/omap4-keypad.c |  122 ++++++++++++++++++++++++++------
 2 files changed, 102 insertions(+), 26 deletions(-)

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index 1379daa..09d7d0b 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -510,10 +510,10 @@ config KEYBOARD_OMAP
 	  To compile this driver as a module, choose M here: the
 	  module will be called omap-keypad.
 
-config KEYBOARD_OMAP4
-	tristate "TI OMAP4 keypad support"
+config KEYBOARD_OMAP4+
+	tristate "TI OMAP4+ keypad support"
 	help
-	  Say Y here if you want to use the OMAP4 keypad.
+	  Say Y here if you want to use the OMAP4+ keypad.
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called omap4-keypad.
diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c
index e809ac0..6872495 100644
--- a/drivers/input/keyboard/omap4-keypad.c
+++ b/drivers/input/keyboard/omap4-keypad.c
@@ -68,6 +68,11 @@
 
 #define OMAP4_MASK_IRQSTATUSDISABLE	0xFFFF
 
+enum {
+	KBD_REVISION_OMAP4 = 0,
+	KBD_REVISION_OMAP5,
+};
+
 struct omap4_keypad {
 	struct input_dev *input;
 
@@ -76,11 +81,79 @@ struct omap4_keypad {
 
 	unsigned int rows;
 	unsigned int cols;
+	unsigned int revision;
 	unsigned int row_shift;
 	unsigned char key_state[8];
 	unsigned short keymap[];
 };
 
+static int kbd_read_irqstatus(struct omap4_keypad *keypad_data, u32 offset)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		return __raw_readl(keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		return __raw_readl(keypad_data->base + offset + 0x0c);
+
+	return -ENODEV;
+}
+
+static int kbd_write_irqstatus(struct omap4_keypad *keypad_data,
+						u32 offset, u32 value)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		return __raw_writel(value, keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		return __raw_writel(value, keypad_data->base + offset + 0x0c);
+
+	return -ENODEV;
+}
+
+static int kbd_write_irqenable(struct omap4_keypad *keypad_data,
+						u32 offset, u32 value)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		return __raw_writel(value, keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		return __raw_writel(value, keypad_data->base + offset + 0x0c);
+
+	return -ENODEV;
+}
+
+static int kbd_readl(struct omap4_keypad *keypad_data, u32 offset)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		return __raw_readl(keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		return __raw_readl(keypad_data->base + offset + 0x10);
+
+	return -ENODEV;
+}
+
+static void kbd_writel(struct omap4_keypad *keypad_data, u32 offset, u32 value)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		__raw_writel(value, keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		__raw_writel(value, keypad_data->base + offset + 0x10);
+}
+
+static int kbd_read_revision(struct omap4_keypad *keypad_data, u32 offset)
+{
+	int reg;
+	reg = __raw_readl(keypad_data->base + offset);
+	reg &= 0x03 << 30;
+	reg >>= 30;
+
+	switch (reg) {
+	case 1:
+		return KBD_REVISION_OMAP5;
+	case 0:
+		return KBD_REVISION_OMAP4;
+	default:
+		return -ENODEV;
+	}
+}
+
 /* Interrupt handler */
 static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
 {
@@ -91,12 +164,11 @@ static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
 	u32 *new_state = (u32 *) key_state;
 
 	/* Disable interrupts */
-	__raw_writel(OMAP4_VAL_IRQDISABLE,
-		     keypad_data->base + OMAP4_KBD_IRQENABLE);
+	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
+						OMAP4_VAL_IRQDISABLE);
 
-	*new_state = __raw_readl(keypad_data->base + OMAP4_KBD_FULLCODE31_0);
-	*(new_state + 1) = __raw_readl(keypad_data->base
-						+ OMAP4_KBD_FULLCODE63_32);
+	*new_state = kbd_readl(keypad_data, OMAP4_KBD_FULLCODE31_0);
+	*(new_state + 1) = kbd_readl(keypad_data, OMAP4_KBD_FULLCODE63_32);
 
 	for (row = 0; row < keypad_data->rows; row++) {
 		changed = key_state[row] ^ keypad_data->key_state[row];
@@ -121,12 +193,13 @@ static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
 		sizeof(keypad_data->key_state));
 
 	/* clear pending interrupts */
-	__raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS),
-			keypad_data->base + OMAP4_KBD_IRQSTATUS);
+	kbd_write_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS,
+			kbd_read_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS));
 
 	/* enable interrupts */
-	__raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN | OMAP4_DEF_IRQENABLE_LONGKEY,
-			keypad_data->base + OMAP4_KBD_IRQENABLE);
+	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
+			OMAP4_DEF_IRQENABLE_EVENTEN |
+				OMAP4_DEF_IRQENABLE_LONGKEY);
 
 	return IRQ_HANDLED;
 }
@@ -139,16 +212,19 @@ static int omap4_keypad_open(struct input_dev *input)
 
 	disable_irq(keypad_data->irq);
 
-	__raw_writel(OMAP4_VAL_FUNCTIONALCFG,
-			keypad_data->base + OMAP4_KBD_CTRL);
-	__raw_writel(OMAP4_VAL_DEBOUNCINGTIME,
-			keypad_data->base + OMAP4_KBD_DEBOUNCINGTIME);
-	__raw_writel(OMAP4_VAL_IRQDISABLE,
-			keypad_data->base + OMAP4_KBD_IRQSTATUS);
-	__raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN | OMAP4_DEF_IRQENABLE_LONGKEY,
-			keypad_data->base + OMAP4_KBD_IRQENABLE);
-	__raw_writel(OMAP4_DEF_WUP_EVENT_ENA | OMAP4_DEF_WUP_LONG_KEY_ENA,
-			keypad_data->base + OMAP4_KBD_WAKEUPENABLE);
+	keypad_data->revision = kbd_read_revision(keypad_data,
+			OMAP4_KBD_REVISION);
+	kbd_writel(keypad_data, OMAP4_KBD_CTRL,
+			OMAP4_VAL_FUNCTIONALCFG);
+	kbd_writel(keypad_data, OMAP4_KBD_DEBOUNCINGTIME,
+			OMAP4_VAL_DEBOUNCINGTIME);
+	kbd_write_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS,
+			OMAP4_VAL_IRQDISABLE);
+	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
+			OMAP4_DEF_IRQENABLE_EVENTEN |
+				OMAP4_DEF_IRQENABLE_LONGKEY);
+	kbd_writel(keypad_data, OMAP4_KBD_WAKEUPENABLE,
+			OMAP4_DEF_WUP_EVENT_ENA | OMAP4_DEF_WUP_LONG_KEY_ENA);
 
 	enable_irq(keypad_data->irq);
 
@@ -162,12 +238,12 @@ static void omap4_keypad_close(struct input_dev *input)
 	disable_irq(keypad_data->irq);
 
 	/* Disable interrupts */
-	__raw_writel(OMAP4_VAL_IRQDISABLE,
-		     keypad_data->base + OMAP4_KBD_IRQENABLE);
+	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
+			OMAP4_VAL_IRQDISABLE);
 
 	/* clear pending interrupts */
-	__raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS),
-			keypad_data->base + OMAP4_KBD_IRQSTATUS);
+	kbd_write_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS,
+			kbd_read_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS));
 
 	enable_irq(keypad_data->irq);
 
-- 
1.7.1



From philipp.zabel at gmail.com  Fri Mar 16 09:40:13 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Fri, 16 Mar 2012 14:40:13 +0100
Subject: [PATCH] pxa/hx4700: fix the LCD initialization
Message-ID: <1331905213.29979.1.camel@flow>

Common sense and the SDG bootldr code reference dictate that
N2.7V/7.3V be disabled here, and not LVDD, which already was
disabled 10 ms earlier.
This should only have an effect if the LCD was enabled in the
bootloader.

Signed-off-by: Philipp Zabel <philipp.zabel at gmail.com>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: Paul Parsons <lost.distance at yahoo.com>
---
 arch/arm/mach-pxa/hx4700.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 61bb967..31c6dd1 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -399,7 +399,7 @@ static void sony_lcd_init(void)
 	gpio_set_value(GPIO62_HX4700_LCD_nRESET, 0);
 	mdelay(10);
 	gpio_set_value(GPIO59_HX4700_LCD_PC1, 0);
-	gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
+	gpio_set_value(GPIO112_HX4700_LCD_N2V7_7V3_ON, 0);
 	mdelay(20);
 
 	gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 1);
-- 
1.7.9.1




From b-cousson at ti.com  Fri Mar 16 09:46:28 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Fri, 16 Mar 2012 14:46:28 +0100
Subject: [PATCH 0/2] omap: board file changes to support dynamic irq alloc
In-Reply-To: <1331900647-3508-1-git-send-email-tarun.kanti@ti.com>
References: <1331900647-3508-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <4F634434.3080707@ti.com>

Hi Tarun,

On 3/16/2012 1:24 PM, Tarun Kanti DebBarma wrote:
> These two patches incorporate changes to OMAP1 and OMAP2 platforms
> board files whereby older references to OMAP_GPIO_IRQ macro are
> now replaced with gpio_to_irq(), thereby getting rid of static
> irq references.

Thanks for the board fix / cleanup.

...

>   arch/arm/mach-omap1/board-h2.c               |    8 ++++----
>   arch/arm/mach-omap1/board-h3.c               |    8 ++++----
>   arch/arm/mach-omap1/board-htcherald.c        |    6 +++---
>   arch/arm/mach-omap1/board-innovator.c        |    4 ++--
>   arch/arm/mach-omap1/board-nokia770.c         |    1 +
>   arch/arm/mach-omap1/board-osk.c              |   12 ++++++------
>   arch/arm/mach-omap1/board-palmte.c           |    2 +-
>   arch/arm/mach-omap1/board-palmtt.c           |    2 +-
>   arch/arm/mach-omap1/board-palmz71.c          |    2 +-
>   arch/arm/mach-omap1/board-voiceblue.c        |   16 +++++++---------
>   arch/arm/mach-omap2/board-2430sdp.c          |    2 +-
>   arch/arm/mach-omap2/board-4430sdp.c          |    2 +-
>   arch/arm/mach-omap2/board-apollon.c          |    6 ++++--
>   arch/arm/mach-omap2/board-devkit8000.c       |    3 ++-
>   arch/arm/mach-omap2/board-h4.c               |    2 +-
>   arch/arm/mach-omap2/board-omap3evm.c         |    2 +-
>   arch/arm/mach-omap2/board-omap4panda.c       |    2 +-
>   arch/arm/mach-omap2/board-rx51-peripherals.c |    3 ++-
>   arch/arm/mach-omap2/board-zoom-debugboard.c  |    3 ++-
>   arch/arm/mach-omap2/board-zoom-peripherals.c |    6 ++++--
>   arch/arm/mach-omap2/common-board-devices.c   |    2 +-

I guess, you should be able to remove even the MACRO definition? 

diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 9e86ee0..d4df414 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -158,10 +158,6 @@
 #define OMAP_MPUIO(nr)         (OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
 
-#define OMAP_GPIO_IRQ(nr)      (OMAP_GPIO_IS_MPUIO(nr) ? \
-                                IH_MPUIO_BASE + ((nr) & 0x0f) : \
-                                IH_GPIO_BASE + (nr))
-
 #define METHOD_MPUIO           0
 #define METHOD_GPIO_1510       1
 #define METHOD_GPIO_1610       2


It will avoid that people use it going forward.

Regards,
Benoit



From tarun.kanti at ti.com  Fri Mar 16 09:52:08 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Fri, 16 Mar 2012 19:22:08 +0530
Subject: [PATCH 0/2] omap: board file changes to support dynamic irq alloc
In-Reply-To: <4F634434.3080707@ti.com>
References: <1331900647-3508-1-git-send-email-tarun.kanti@ti.com>
 <4F634434.3080707@ti.com>
Message-ID: <CAC83Zv+zEn-VejJ1TVkFqDC4NaLybi2Ur7SmyC55YMMVWZ7T4Q@mail.gmail.com>

On Fri, Mar 16, 2012 at 7:16 PM, Cousson, Benoit <b-cousson at ti.com> wrote:
> Hi Tarun,
>
> On 3/16/2012 1:24 PM, Tarun Kanti DebBarma wrote:
>> These two patches incorporate changes to OMAP1 and OMAP2 platforms
>> board files whereby older references to OMAP_GPIO_IRQ macro are
>> now replaced with gpio_to_irq(), thereby getting rid of static
>> irq references.
>
> Thanks for the board fix / cleanup.
>
> ...
>
>> ? arch/arm/mach-omap1/board-h2.c ? ? ? ? ? ? ? | ? ?8 ++++----
>> ? arch/arm/mach-omap1/board-h3.c ? ? ? ? ? ? ? | ? ?8 ++++----
>> ? arch/arm/mach-omap1/board-htcherald.c ? ? ? ?| ? ?6 +++---
>> ? arch/arm/mach-omap1/board-innovator.c ? ? ? ?| ? ?4 ++--
>> ? arch/arm/mach-omap1/board-nokia770.c ? ? ? ? | ? ?1 +
>> ? arch/arm/mach-omap1/board-osk.c ? ? ? ? ? ? ?| ? 12 ++++++------
>> ? arch/arm/mach-omap1/board-palmte.c ? ? ? ? ? | ? ?2 +-
>> ? arch/arm/mach-omap1/board-palmtt.c ? ? ? ? ? | ? ?2 +-
>> ? arch/arm/mach-omap1/board-palmz71.c ? ? ? ? ?| ? ?2 +-
>> ? arch/arm/mach-omap1/board-voiceblue.c ? ? ? ?| ? 16 +++++++---------
>> ? arch/arm/mach-omap2/board-2430sdp.c ? ? ? ? ?| ? ?2 +-
>> ? arch/arm/mach-omap2/board-4430sdp.c ? ? ? ? ?| ? ?2 +-
>> ? arch/arm/mach-omap2/board-apollon.c ? ? ? ? ?| ? ?6 ++++--
>> ? arch/arm/mach-omap2/board-devkit8000.c ? ? ? | ? ?3 ++-
>> ? arch/arm/mach-omap2/board-h4.c ? ? ? ? ? ? ? | ? ?2 +-
>> ? arch/arm/mach-omap2/board-omap3evm.c ? ? ? ? | ? ?2 +-
>> ? arch/arm/mach-omap2/board-omap4panda.c ? ? ? | ? ?2 +-
>> ? arch/arm/mach-omap2/board-rx51-peripherals.c | ? ?3 ++-
>> ? arch/arm/mach-omap2/board-zoom-debugboard.c ?| ? ?3 ++-
>> ? arch/arm/mach-omap2/board-zoom-peripherals.c | ? ?6 ++++--
>> ? arch/arm/mach-omap2/common-board-devices.c ? | ? ?2 +-
>
> I guess, you should be able to remove even the MACRO definition?
Yes, there is another file referring to this macro.
I will check and update before removing the macro.

>
> diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
> index 9e86ee0..d4df414 100644
> --- a/arch/arm/plat-omap/include/plat/gpio.h
> +++ b/arch/arm/plat-omap/include/plat/gpio.h
> @@ -158,10 +158,6 @@
> ?#define OMAP_MPUIO(nr) ? ? ? ? (OMAP_MAX_GPIO_LINES + (nr))
> ?#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
>
> -#define OMAP_GPIO_IRQ(nr) ? ? ?(OMAP_GPIO_IS_MPUIO(nr) ? \
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?IH_MPUIO_BASE + ((nr) & 0x0f) : \
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?IH_GPIO_BASE + (nr))
> -
> ?#define METHOD_MPUIO ? ? ? ? ? 0
> ?#define METHOD_GPIO_1510 ? ? ? 1
> ?#define METHOD_GPIO_1610 ? ? ? 2
>
>
> It will avoid that people use it going forward.
Right. Thanks.
--
Tarun
>
> Regards,
> Benoit
>


From tarun.kanti at ti.com  Fri Mar 16 10:05:48 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:48 +0530
Subject: [PATCH v4 00/12] gpio/omap: Some more driver cleanup and fixes
Message-ID: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>

The cleanup is mostly getting rid of redundant fields in struct gpio_bank{}
as we already have them as part of bank->context now. Also, remove un-used
variable from gpio_irq_handler. Also, the suspend/resume callbacks are
removed bacause they are not needed any more.

The fixes include correction of _set_gpio_irqenable() implementation,
missing wakeup_en register update in set_gpio_wakeup(), type mismatch
of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
register update in set_gpio_dataout_() and few corrections in context
save logic.

It is baselined on top of:
git://git.secretlab.ca/git/linux-2.6.git gpio/next
Commit: 81b279d80a63628e580c71a31d30a8c3b3047ad4

Series is available here for reference:
git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_more_cleanup_fixes

Power Test: 
Off-mode and Retention on OMAP3430 (Suspend and Idle paths).
Also confirmed that dataout register content preserved over
off-mode.
            
Functional Test:
OMAP2430, OMAP3430SDP, ZOOM3, OMAP4430, OMAP4-BLAZE, PANDA 

v4:
a) Implemented all comments on v3 which are mostly related to
avoiding unnecessary register read while updating the context.

b) Folded:
gpio/omap: fix dataout register overwrite in _set_gpio_dataout
into:
gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg

v3:
- Added 4 more additional patches to the previous series
 which are all bug fixes.

v2:
- Added a new patch to update wakeup_en register in _set_gpio_wakeup()
 in addition to updating bank->context.wake_en.

- Added a new patch to remove redundant decoding of gpio offset in
 gpio_get(), _get_gpio_datain() and _get_gpio_dataout().

- Added a new patch to remove suspend/resume callbacks because the
 operations performed with the callbacks are redundant.

Tarun Kanti DebBarma (12):
  gpio/omap: remove saved_fallingdetect, saved_risingdetect fields
  gpio/omap: fix wakeup_en register update in _set_gpio_wakeup()
  gpio/omap: remove suspend_wakeup field from struct gpio_bank
  gpio/omap: remove saved_wakeup field from struct gpio_bank
  gpio/omap: get rid of retrigger variable in gpio_irq_handler
  gpio/omap: fix trigger type to unsigned
  gpio/omap: fix _set_gpio_irqenable implementation
  gpio/omap: remove redundant decoding of gpio offset
  gpio/omap: remove suspend/resume callbacks
  gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg
  gpio/omap: fix incorrect context restore logic in omap_gpio_runtime_*
  gpio/omap: fix incorrect update to context.irqenable1

 drivers/gpio/gpio-omap.c |  131 +++++++++++++---------------------------------
 1 files changed, 37 insertions(+), 94 deletions(-)



From tarun.kanti at ti.com  Fri Mar 16 10:05:52 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:52 +0530
Subject: [PATCH v4 04/12] gpio/omap: remove saved_wakeup field from struct
 gpio_bank
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-5-git-send-email-tarun.kanti@ti.com>

There is no more need to have saved_wakeup because bank->context.wake_en
already holds that value. So getting rid of read/write operation associated
with this field.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |   12 +++---------
 1 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 3a4f151..3b91ade 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -57,7 +57,6 @@ struct gpio_bank {
 	u16 irq;
 	int irq_base;
 	struct irq_domain *domain;
-	u32 saved_wakeup;
 	u32 non_wakeup_gpios;
 	u32 enabled_non_wakeup_gpios;
 	struct gpio_regs context;
@@ -777,7 +776,6 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
 	unsigned long		flags;
 
 	spin_lock_irqsave(&bank->lock, flags);
-	bank->saved_wakeup = __raw_readl(mask_reg);
 	__raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
@@ -793,7 +791,7 @@ static int omap_mpuio_resume_noirq(struct device *dev)
 	unsigned long		flags;
 
 	spin_lock_irqsave(&bank->lock, flags);
-	__raw_writel(bank->saved_wakeup, mask_reg);
+	__raw_writel(bank->context.wake_en, mask_reg);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
@@ -1153,7 +1151,6 @@ static int omap_gpio_suspend(struct device *dev)
 	struct platform_device *pdev = to_platform_device(dev);
 	struct gpio_bank *bank = platform_get_drvdata(pdev);
 	void __iomem *base = bank->base;
-	void __iomem *wakeup_enable;
 	unsigned long flags;
 
 	if (!bank->mod_usage || !bank->loses_context)
@@ -1162,10 +1159,7 @@ static int omap_gpio_suspend(struct device *dev)
 	if (!bank->regs->wkup_en || !bank->context.wake_en)
 		return 0;
 
-	wakeup_enable = bank->base + bank->regs->wkup_en;
-
 	spin_lock_irqsave(&bank->lock, flags);
-	bank->saved_wakeup = __raw_readl(wakeup_enable);
 	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
 	_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
 	spin_unlock_irqrestore(&bank->lock, flags);
@@ -1183,12 +1177,12 @@ static int omap_gpio_resume(struct device *dev)
 	if (!bank->mod_usage || !bank->loses_context)
 		return 0;
 
-	if (!bank->regs->wkup_en || !bank->saved_wakeup)
+	if (!bank->regs->wkup_en || !bank->context.wake_en)
 		return 0;
 
 	spin_lock_irqsave(&bank->lock, flags);
 	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
-	_gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
+	_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 10:05:55 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:55 +0530
Subject: [PATCH v4 07/12] gpio/omap: fix _set_gpio_irqenable implementation
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-8-git-send-email-tarun.kanti@ti.com>

This function should be capable of both enabling and disabling interrupts
based upon the *enable* parameter. Right now the function only enables
the interrupt and *enable* is not used at all. So add the interrupt
disable capability also using the parameter.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 4d23da1..8b453dd 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -480,7 +480,10 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 
 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
 {
-	_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
+	if (enable)
+		_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
+	else
+		_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
 }
 
 /*
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 10:05:56 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:56 +0530
Subject: [PATCH v4 08/12] gpio/omap: remove redundant decoding of gpio offset
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-9-git-send-email-tarun.kanti@ti.com>

In gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of
un-necessary operation to compute gpio mask. The gpio offset passed
to gpio_get() is sufficient to do that.

Here is Russell's original comment:
Can someone explain to me this:
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))

static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
       void __iomem *reg = bank->base + bank->regs->datain;

       return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
}

static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
       struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
       void __iomem *reg = bank->base;
       int gpio = chip->base + offset;
       u32 mask = GPIO_BIT(bank, gpio);

       if (gpio_is_input(bank, mask))
               return _get_gpio_datain(bank, gpio);
       else
               return _get_gpio_dataout(bank, gpio);
}

Given that bank->width on OMAP is either 32 or 16, and GPIO numbers for
any GPIO chip are always aligned to 32 or 16, why does this code bother
adding the chips base gpio number and then modulo the width?

Surely this means if - for argument sake - you registered a GPIO chip
with 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0
bit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be
chip 1 bit 0..7.

However, if you registered a GPIO chip with 16 lines first, it would
mean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be
chip 1 bit 0..15.

Surely this kind of behaviour is not intended?

Is there a reason why the bitmask can't just be (1 << offset) where
offset is passed into these functions as GPIO number - chip->base ?

Reported-by: Russell King - ARM Linux <linux at arm.linux.org.uk>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 drivers/gpio/gpio-omap.c |   18 +++++++-----------
 1 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 8b453dd..cce2c73 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -140,18 +140,18 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
 	bank->context.dataout = l;
 }
 
-static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
+static int _get_gpio_datain(struct gpio_bank *bank, int offset)
 {
 	void __iomem *reg = bank->base + bank->regs->datain;
 
-	return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
+	return (__raw_readl(reg) & (1 << offset)) != 0;
 }
 
-static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
+static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
 {
 	void __iomem *reg = bank->base + bank->regs->dataout;
 
-	return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
+	return (__raw_readl(reg) & (1 << offset)) != 0;
 }
 
 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
@@ -852,19 +852,15 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
 static int gpio_get(struct gpio_chip *chip, unsigned offset)
 {
 	struct gpio_bank *bank;
-	void __iomem *reg;
-	int gpio;
 	u32 mask;
 
-	gpio = chip->base + offset;
 	bank = container_of(chip, struct gpio_bank, chip);
-	reg = bank->base;
-	mask = GPIO_BIT(bank, gpio);
+	mask = (1 << offset);
 
 	if (gpio_is_input(bank, mask))
-		return _get_gpio_datain(bank, gpio);
+		return _get_gpio_datain(bank, offset);
 	else
-		return _get_gpio_dataout(bank, gpio);
+		return _get_gpio_dataout(bank, offset);
 }
 
 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 10:06:00 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:36:00 +0530
Subject: [PATCH v4 12/12] gpio/omap: fix incorrect update to context.irqenable1
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-13-git-send-email-tarun.kanti@ti.com>

In _enable_gpio_irqbank() when bank->regs->set_irqenable is valid,
gpio_mask can be directly set by writing to set_irqenable register
without overwriting current value. In order to ensure the same is
stored in context.irqenable1, we must read from regs->irqenable
instead of overwriting it with gpio_mask.
The overwriting makes sense only in the second case where irqenable
is explicitly read and updated with new gpio_mask before writing it
back. However, for consistency reading regs->irqenable into the
bank->context.irqenable1 takes care of both the scenarios.

        if (bank->regs->set_irqenable) {
                reg += bank->regs->set_irqenable;
                l = gpio_mask;
        } else {
                reg += bank->regs->irqenable;
                l = __raw_readl(reg);
                if (bank->regs->irqenable_inv)
                        l &= ~gpio_mask;
                else
                        l |= gpio_mask;
        }

Make the same change for _disable_gpio_irqbank().

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 drivers/gpio/gpio-omap.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index c5aff7c..ae62c62 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -447,6 +447,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 	if (bank->regs->set_irqenable) {
 		reg += bank->regs->set_irqenable;
 		l = gpio_mask;
+		bank->context.irqenable1 |= gpio_mask;
 	} else {
 		reg += bank->regs->irqenable;
 		l = __raw_readl(reg);
@@ -454,10 +455,10 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 			l &= ~gpio_mask;
 		else
 			l |= gpio_mask;
+		bank->context.irqenable1 = l;
 	}
 
 	__raw_writel(l, reg);
-	bank->context.irqenable1 = l;
 }
 
 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
@@ -468,6 +469,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 	if (bank->regs->clr_irqenable) {
 		reg += bank->regs->clr_irqenable;
 		l = gpio_mask;
+		bank->context.irqenable1 &= ~gpio_mask;
 	} else {
 		reg += bank->regs->irqenable;
 		l = __raw_readl(reg);
@@ -475,10 +477,10 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 			l |= gpio_mask;
 		else
 			l &= ~gpio_mask;
+		bank->context.irqenable1 = l;
 	}
 
 	__raw_writel(l, reg);
-	bank->context.irqenable1 = l;
 }
 
 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 10:05:53 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:53 +0530
Subject: [PATCH v4 05/12] gpio/omap: get rid of retrigger variable in
 gpio_irq_handler
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-6-git-send-email-tarun.kanti@ti.com>

commit 672e302e3c (ARM: OMAP: use edge/level handlers from generic IRQ
framework) removed retrigger support in favor of using generic IRQ
framework.  This patch cleans up some unused remnants of that removal.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 3b91ade..47143b7 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -627,7 +627,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 	u32 isr;
 	unsigned int gpio_irq, gpio_index;
 	struct gpio_bank *bank;
-	u32 retrigger = 0;
 	int unmasked = 0;
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 
@@ -664,8 +663,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 			chained_irq_exit(chip, desc);
 		}
 
-		isr |= retrigger;
-		retrigger = 0;
 		if (!isr)
 			break;
 
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 10:05:50 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:50 +0530
Subject: [PATCH v4 02/12] gpio/omap: fix wakeup_en register update in
 _set_gpio_wakeup()
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-3-git-send-email-tarun.kanti@ti.com>

There are two ways through which wakeup_en register can be programmed
using gpiolib APIs as shown below. It is seen that in the second case
in _set_gpio_wakeup(), even though bank->suspend_wakeup is updated
correctly, its value is not programmed in wakeup_en register. Fix this.

chip.irq_set_type()->gpio_irq_type()->_set_gpio_triggering()->set_gpio_trigger()
chip.irq_set_wake()->gpio_wake_enable()->_set_gpio_wakeup()

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 drivers/gpio/gpio-omap.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 0c1c529..171f951 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -509,6 +509,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
 	else
 		bank->suspend_wakeup &= ~gpio_bit;
 
+	__raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 10:05:58 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:58 +0530
Subject: [PATCH v4 10/12] gpio/omap: fix missing dataout context save in
 _set_gpio_dataout_reg
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-11-git-send-email-tarun.kanti@ti.com>

There are two functions, _set_gpio_dataout_reg() and _set_gpio_dataout_mask()
which writes to dataout register and the dataout context must be saved.
It is missing in the first function, _set_gpio_dataout_reg(). Fix this.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 drivers/gpio/gpio-omap.c |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index dba69b8..072a841 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -116,10 +116,13 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
 	void __iomem *reg = bank->base;
 	u32 l = GPIO_BIT(bank, gpio);
 
-	if (enable)
+	if (enable) {
 		reg += bank->regs->set_dataout;
-	else
+		bank->context.dataout |= l;
+	} else {
 		reg += bank->regs->clr_dataout;
+		bank->context.dataout &= ~l;
+	}
 
 	__raw_writel(l, reg);
 }
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 10:05:54 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:54 +0530
Subject: [PATCH v4 06/12] gpio/omap: fix trigger type to unsigned
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-7-git-send-email-tarun.kanti@ti.com>

The GPIO trigger parameter is of type unsigned.
enum {
        IRQ_TYPE_NONE           = 0x00000000,
        IRQ_TYPE_EDGE_RISING    = 0x00000001,
        IRQ_TYPE_EDGE_FALLING   = 0x00000002,
        IRQ_TYPE_EDGE_BOTH      = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
        IRQ_TYPE_LEVEL_HIGH     = 0x00000004,
        IRQ_TYPE_LEVEL_LOW      = 0x00000008,
        IRQ_TYPE_LEVEL_MASK     = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
        IRQ_TYPE_SENSE_MASK     = 0x0000000f,

        IRQ_TYPE_PROBE          = 0x00000010,
...
};
Even though gpio_irq_type(struct irq_data *d, unsigned type) has the right type
of parameter, the subsequent called functions set_gpio_triggering() and
set_gpio_trigger() wrongly makes it signed integer. Fix this.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 47143b7..4d23da1 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -241,7 +241,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
 }
 
 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
-						int trigger)
+						unsigned trigger)
 {
 	void __iomem *base = bank->base;
 	u32 gpio_bit = 1 << gpio;
@@ -323,7 +323,8 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 #endif
 
-static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
+static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
+							unsigned trigger)
 {
 	void __iomem *reg = bank->base;
 	void __iomem *base = bank->base;
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 10:05:59 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:59 +0530
Subject: [PATCH v4 11/12] gpio/omap: fix incorrect context restore logic in
 omap_gpio_runtime_*
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-12-git-send-email-tarun.kanti@ti.com>

In omap_gpio_runtime_suspend/resume() the context save/restore should
be independent of bank->enabled_non_wakeup_gpios. This was preventing
context restore of GPIO lines which are not wakeup enabled.

Reported-by: Govindraj Raja <govindraj.raja at ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 drivers/gpio/gpio-omap.c |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 072a841..c5aff7c 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1187,9 +1187,6 @@ static int omap_gpio_runtime_suspend(struct device *dev)
 	 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
 	 * generated.  See OMAP2420 Errata item 1.101.
 	 */
-	if (!(bank->enabled_non_wakeup_gpios))
-		goto update_gpio_context_count;
-
 	bank->saved_datain = __raw_readl(bank->base +
 						bank->regs->datain);
 	l1 = bank->context.fallingdetect;
@@ -1236,7 +1233,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
 	__raw_writel(bank->context.risingdetect,
 		     bank->base + bank->regs->risingdetect);
 
-	if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
+	if (!bank->workaround_enabled) {
 		spin_unlock_irqrestore(&bank->lock, flags);
 		return 0;
 	}
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 10:05:49 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:49 +0530
Subject: [PATCH v4 01/12] gpio/omap: remove saved_fallingdetect,
 saved_risingdetect fields
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-2-git-send-email-tarun.kanti@ti.com>

Since we already have context.fallingdetect and context.risingdetect
there is no more need to have these additional fields. Also, getting
rid of extra reads associated with them.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |   19 ++++++++-----------
 1 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 7cbad85..0c1c529 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -63,8 +63,6 @@ struct gpio_bank {
 	u32 enabled_non_wakeup_gpios;
 	struct gpio_regs context;
 	u32 saved_datain;
-	u32 saved_fallingdetect;
-	u32 saved_risingdetect;
 	u32 level_mask;
 	u32 toggle_mask;
 	spinlock_t lock;
@@ -1244,11 +1242,9 @@ static int omap_gpio_runtime_suspend(struct device *dev)
 
 	bank->saved_datain = __raw_readl(bank->base +
 						bank->regs->datain);
-	l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
-	l2 = __raw_readl(bank->base + bank->regs->risingdetect);
+	l1 = bank->context.fallingdetect;
+	l2 = bank->context.risingdetect;
 
-	bank->saved_fallingdetect = l1;
-	bank->saved_risingdetect = l2;
 	l1 &= ~bank->enabled_non_wakeup_gpios;
 	l2 &= ~bank->enabled_non_wakeup_gpios;
 
@@ -1307,9 +1303,9 @@ static int omap_gpio_runtime_resume(struct device *dev)
 		}
 	}
 
-	__raw_writel(bank->saved_fallingdetect,
+	__raw_writel(bank->context.fallingdetect,
 			bank->base + bank->regs->fallingdetect);
-	__raw_writel(bank->saved_risingdetect,
+	__raw_writel(bank->context.risingdetect,
 			bank->base + bank->regs->risingdetect);
 	l = __raw_readl(bank->base + bank->regs->datain);
 
@@ -1326,14 +1322,15 @@ static int omap_gpio_runtime_resume(struct device *dev)
 	 * No need to generate IRQs for the rising edge for gpio IRQs
 	 * configured with falling edge only; and vice versa.
 	 */
-	gen0 = l & bank->saved_fallingdetect;
+	gen0 = l & bank->context.fallingdetect;
 	gen0 &= bank->saved_datain;
 
-	gen1 = l & bank->saved_risingdetect;
+	gen1 = l & bank->context.risingdetect;
 	gen1 &= ~(bank->saved_datain);
 
 	/* FIXME: Consider GPIO IRQs with level detections properly! */
-	gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect));
+	gen = l & (~(bank->context.fallingdetect) &
+					 ~(bank->context.risingdetect));
 	/* Consider all GPIO IRQs needed to be updated */
 	gen |= gen0 | gen1;
 
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 10:05:51 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:51 +0530
Subject: [PATCH v4 03/12] gpio/omap: remove suspend_wakeup field from struct
 gpio_bank
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-4-git-send-email-tarun.kanti@ti.com>

Since we already have bank->context.wake_en to keep track
of gpios which are wakeup enabled, there is no need to have
this field any more.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |   13 ++++++-------
 1 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 171f951..3a4f151 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -57,7 +57,6 @@ struct gpio_bank {
 	u16 irq;
 	int irq_base;
 	struct irq_domain *domain;
-	u32 suspend_wakeup;
 	u32 saved_wakeup;
 	u32 non_wakeup_gpios;
 	u32 enabled_non_wakeup_gpios;
@@ -505,11 +504,11 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
 
 	spin_lock_irqsave(&bank->lock, flags);
 	if (enable)
-		bank->suspend_wakeup |= gpio_bit;
+		bank->context.wake_en |= gpio_bit;
 	else
-		bank->suspend_wakeup &= ~gpio_bit;
+		bank->context.wake_en &= ~gpio_bit;
 
-	__raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en);
+	__raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
@@ -779,7 +778,7 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
 
 	spin_lock_irqsave(&bank->lock, flags);
 	bank->saved_wakeup = __raw_readl(mask_reg);
-	__raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
+	__raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
@@ -1160,7 +1159,7 @@ static int omap_gpio_suspend(struct device *dev)
 	if (!bank->mod_usage || !bank->loses_context)
 		return 0;
 
-	if (!bank->regs->wkup_en || !bank->suspend_wakeup)
+	if (!bank->regs->wkup_en || !bank->context.wake_en)
 		return 0;
 
 	wakeup_enable = bank->base + bank->regs->wkup_en;
@@ -1168,7 +1167,7 @@ static int omap_gpio_suspend(struct device *dev)
 	spin_lock_irqsave(&bank->lock, flags);
 	bank->saved_wakeup = __raw_readl(wakeup_enable);
 	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
-	_gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
+	_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
-- 
1.7.0.4



From tarun.kanti at ti.com  Fri Mar 16 10:05:57 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Fri, 16 Mar 2012 19:35:57 +0530
Subject: [PATCH v4 09/12] gpio/omap: remove suspend/resume callbacks
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1331906760-5259-10-git-send-email-tarun.kanti@ti.com>

Both omap_gpio_suspend() and omap_gpio_resume() does programming
of wakeup_en register.
_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);

This is redundant in omap_gpio_suspend() because wakeup_en
register automatically gets initialized in _set_gpio_wakeup()
and set_gpio_trigger() while being called either from
chip.irq_set_wake() or chip.irq_set_type().

This is also redundant in omap_gpio_resume() because wakeup_en
register is programmed in omap_gpio_restore_context() called
which is called from runtime resume callback.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 drivers/gpio/gpio-omap.c |   47 ----------------------------------------------
 1 files changed, 0 insertions(+), 47 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index cce2c73..dba69b8 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1142,50 +1142,6 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
 
-#if defined(CONFIG_PM_SLEEP)
-static int omap_gpio_suspend(struct device *dev)
-{
-	struct platform_device *pdev = to_platform_device(dev);
-	struct gpio_bank *bank = platform_get_drvdata(pdev);
-	void __iomem *base = bank->base;
-	unsigned long flags;
-
-	if (!bank->mod_usage || !bank->loses_context)
-		return 0;
-
-	if (!bank->regs->wkup_en || !bank->context.wake_en)
-		return 0;
-
-	spin_lock_irqsave(&bank->lock, flags);
-	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
-	_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
-	spin_unlock_irqrestore(&bank->lock, flags);
-
-	return 0;
-}
-
-static int omap_gpio_resume(struct device *dev)
-{
-	struct platform_device *pdev = to_platform_device(dev);
-	struct gpio_bank *bank = platform_get_drvdata(pdev);
-	void __iomem *base = bank->base;
-	unsigned long flags;
-
-	if (!bank->mod_usage || !bank->loses_context)
-		return 0;
-
-	if (!bank->regs->wkup_en || !bank->context.wake_en)
-		return 0;
-
-	spin_lock_irqsave(&bank->lock, flags);
-	_gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
-	_gpio_rmw(base, bank->regs->wkup_en, bank->context.wake_en, 1);
-	spin_unlock_irqrestore(&bank->lock, flags);
-
-	return 0;
-}
-#endif /* CONFIG_PM_SLEEP */
-
 #if defined(CONFIG_PM_RUNTIME)
 static void omap_gpio_restore_context(struct gpio_bank *bank);
 
@@ -1417,14 +1373,11 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)
 }
 #endif /* CONFIG_PM_RUNTIME */
 #else
-#define omap_gpio_suspend NULL
-#define omap_gpio_resume NULL
 #define omap_gpio_runtime_suspend NULL
 #define omap_gpio_runtime_resume NULL
 #endif
 
 static const struct dev_pm_ops gpio_pm_ops = {
-	SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
 	SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
 									NULL)
 };
-- 
1.7.0.4



From nm at ti.com  Fri Mar 16 10:20:35 2012
From: nm at ti.com (Nishanth Menon)
Date: Fri, 16 Mar 2012 09:20:35 -0500
Subject: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting
 to add IVA OPP
In-Reply-To: <5448984682E7954C9BFF27F747A9C6CA56D6A8@dolphin.TIGRIS.local>
References: <8762e6et1u.fsf@ti.com>
 <5448984682E7954C9BFF27F747A9C6CA56D6A8@dolphin.TIGRIS.local>
Message-ID: <20120316142034.GA22234@senorita.am.dhcp.ti.com>

On 10:26-20120316, Maximilian Schwerin wrote:
[...]
> > >>> +
> > >>> + ? ? ? ? ? ? if ((strcmp(opp_def->hwmod_name,"iva") == 
> > 0) && !omap3_has_iva())
> > >>> + ? ? ? ? ? ? ? ? ? ? continue;
> > >>> +
> > >>> ? ? ? ? ? ? ? oh = omap_hwmod_lookup(opp_def->hwmod_name);
> > >>> ? ? ? ? ? ? ? if (!oh || !oh->od) {
> > >>> ? ? ? ? ? ? ? ? ? ? ? pr_warn("%s: no hwmod or odev for %s, [%d] "
> > >>
> > >> Wouldn't the one-liner below do the same thing?
> > >>
> > >> Actually, your patch makes it less noisy at boot time, avoiding the
> > >> pr_warn(), so is probably better.
> > >
> > > The only issue i have with current patch is that it 
> > focusses to solve
> > > a specific device IVA.
> > > we could have similar variances if we had SGX/AESS device etc
> > > registered in the common
> > > table. a generic solution might be preferable - could we reduce the
> > > severity of pr_warn to pr_debug and do a continue instead?
> > 
> > I agree, that would be a better generic solution.
> > 
> > Kevin
> >
> 
> This is a pragmatic and simple solution for a well understood problem with no side effects. Why not fix the problem now and do the generic solution later on? 
> 
> I'm not a fulltime kernel dev. I have about two weeks to get my new board out to my customer... Every time I set up a new board, I have to fix problems using known patches that are sometimes years old. Every patch I have to find costs me hours of time I really don't have. 
> 
> Just my two cents (euro cents of course :-), Maximilian
ok, so lets fix it generically - here is the patch for it. Let us know
if this works for you


>From 5275d09c9f1a16c8f0814745e1c313c6cca049f6 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm at ti.com>
Date: Fri, 16 Mar 2012 09:13:24 -0500
Subject: [PATCH] OMAP2+: OPP: allow OPP enumeration to continue if device is not present

On platforms such as OMAP3, certain variants may not have IVA, SGX
or some specific component. We currently have a check to aid fixing
wrong population of OPP entries for issues such as typos. This however
causes a conflict with valid requirement where the SoC variant does
not actually have the module present.

So, reduce the severity of the print to a debug statement and skip
registering that specific OPP, but continue down the list.

Reported-by: Steve Sakoman <steve at sakoman.com>
Reported-by: Maximilian Schwerin <mvs at tigris.de>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
 arch/arm/mach-omap2/opp.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index 9262a6b..de6d464 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -64,10 +64,10 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
 		}
 		oh = omap_hwmod_lookup(opp_def->hwmod_name);
 		if (!oh || !oh->od) {
-			pr_warn("%s: no hwmod or odev for %s, [%d] "
+			pr_debug("%s: no hwmod or odev for %s, [%d] "
 				"cannot add OPPs.\n", __func__,
 				opp_def->hwmod_name, i);
-			return -EINVAL;
+			continue;
 		}
 		dev = &oh->od->pdev->dev;
 
-- 
1.7.0.4


-- 
Regards,
Nishanth Menon


From sourav.poddar at ti.com  Fri Mar 16 10:26:27 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 16 Mar 2012 19:56:27 +0530
Subject: [PATCH 0/2] Omap keypad cleanup and omap5 support
Message-ID: <1331907989-11891-1-git-send-email-sourav.poddar@ti.com>

The series consists of two patches.
Patch1 of the series makes omap4 keypad independent of the
architecture by moving platform_data to <linux/platform_data>

Patch2 add support for omap5 onchip keypad.

Tested on omap4430sdp using 3.3-rc6.
Tested on omap5 board using 3.1 custom kernel. 

Felipe Balbi (1):
  input: keypad: move platform_data to <linux/platform_data>

G, Manjunath Kondaiah (1):
  Input: omap-keypad: dynamically handle register offsets

 arch/arm/mach-omap2/board-4430sdp.c            |    1 +
 arch/arm/mach-omap2/devices.c                  |    1 +
 arch/arm/plat-omap/include/plat/omap4-keypad.h |    9 --
 drivers/input/keyboard/Kconfig                 |    7 +-
 drivers/input/keyboard/omap4-keypad.c          |  124 +++++++++++++++++++-----
 include/linux/platform_data/omap4-keypad.h     |   13 +++
 6 files changed, 118 insertions(+), 37 deletions(-)
 create mode 100644 include/linux/platform_data/omap4-keypad.h



From sourav.poddar at ti.com  Fri Mar 16 10:26:28 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 16 Mar 2012 19:56:28 +0530
Subject: [PATCH 1/2] input: keypad: move platform_data to <linux/platform_data>
In-Reply-To: <1331907989-11891-1-git-send-email-sourav.poddar@ti.com>
References: <1331907989-11891-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1331907989-11891-2-git-send-email-sourav.poddar@ti.com>

From: Felipe Balbi <balbi at ti.com>

This patch allows us to drop the OMAP depencendy
from the OMAP4 keypad driver.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 arch/arm/mach-omap2/board-4430sdp.c            |    1 +
 arch/arm/mach-omap2/devices.c                  |    1 +
 arch/arm/plat-omap/include/plat/omap4-keypad.h |    9 ---------
 drivers/input/keyboard/Kconfig                 |    1 -
 drivers/input/keyboard/omap4-keypad.c          |    2 +-
 include/linux/platform_data/omap4-keypad.h     |   13 +++++++++++++
 6 files changed, 16 insertions(+), 11 deletions(-)
 create mode 100644 include/linux/platform_data/omap4-keypad.h

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 4e90715..d16902c 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -25,6 +25,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/leds.h>
 #include <linux/leds_pwm.h>
+#include <linux/platform_data/omap4-keypad.h>
 
 #include <mach/hardware.h>
 #include <asm/hardware/gic.h>
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 283d11e..58e1d20 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -17,6 +17,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/of.h>
+#include <linux/platform_data/omap4-keypad.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
index 9fe6c87..8ad0a37 100644
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -1,15 +1,6 @@
 #ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
 #define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
 
-#include <linux/input/matrix_keypad.h>
-
-struct omap4_keypad_platform_data {
-	const struct matrix_keymap_data *keymap_data;
-
-	u8 rows;
-	u8 cols;
-};
-
 extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
 				struct omap_board_data *);
 #endif
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index cdc385b..1379daa 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -512,7 +512,6 @@ config KEYBOARD_OMAP
 
 config KEYBOARD_OMAP4
 	tristate "TI OMAP4 keypad support"
-	depends on ARCH_OMAP4
 	help
 	  Say Y here if you want to use the OMAP4 keypad.
 
diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c
index d5c5d77..e809ac0 100644
--- a/drivers/input/keyboard/omap4-keypad.c
+++ b/drivers/input/keyboard/omap4-keypad.c
@@ -31,7 +31,7 @@
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
 
-#include <plat/omap4-keypad.h>
+#include <linux/platform_data/omap4-keypad.h>
 
 /* OMAP4 registers */
 #define OMAP4_KBD_REVISION		0x00
diff --git a/include/linux/platform_data/omap4-keypad.h b/include/linux/platform_data/omap4-keypad.h
new file mode 100644
index 0000000..4eef5fb
--- /dev/null
+++ b/include/linux/platform_data/omap4-keypad.h
@@ -0,0 +1,13 @@
+#ifndef __LINUX_INPUT_OMAP4_KEYPAD_H
+#define __LINUX_INPUT_OMAP4_KEYPAD_H
+
+#include <linux/input/matrix_keypad.h>
+
+struct omap4_keypad_platform_data {
+	const struct matrix_keymap_data *keymap_data;
+
+	u8 rows;
+	u8 cols;
+};
+
+#endif /* __LINUX_INPUT_OMAP4_KEYPAD_H */
-- 
1.7.1



From sourav.poddar at ti.com  Fri Mar 16 10:26:29 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Fri, 16 Mar 2012 19:56:29 +0530
Subject: [PATCH 2/2] Input: omap-keypad: dynamically handle register offsets
In-Reply-To: <1331907989-11891-1-git-send-email-sourav.poddar@ti.com>
References: <1331907989-11891-1-git-send-email-sourav.poddar@ti.com>
Message-ID: <1331907989-11891-3-git-send-email-sourav.poddar@ti.com>

From: G, Manjunath Kondaiah <manjugk at ti.com>

Keypad controller register offsets are different for omap4
and omap5. Handle these offsets through static mapping and
assign these mappings during run time.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: G, Manjunath Kondaiah <manjugk at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
 drivers/input/keyboard/Kconfig        |    6 +-
 drivers/input/keyboard/omap4-keypad.c |  122 ++++++++++++++++++++++++++------
 2 files changed, 102 insertions(+), 26 deletions(-)

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index 1379daa..09d7d0b 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -510,10 +510,10 @@ config KEYBOARD_OMAP
 	  To compile this driver as a module, choose M here: the
 	  module will be called omap-keypad.
 
-config KEYBOARD_OMAP4
-	tristate "TI OMAP4 keypad support"
+config KEYBOARD_OMAP4+
+	tristate "TI OMAP4+ keypad support"
 	help
-	  Say Y here if you want to use the OMAP4 keypad.
+	  Say Y here if you want to use the OMAP4+ keypad.
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called omap4-keypad.
diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c
index e809ac0..6872495 100644
--- a/drivers/input/keyboard/omap4-keypad.c
+++ b/drivers/input/keyboard/omap4-keypad.c
@@ -68,6 +68,11 @@
 
 #define OMAP4_MASK_IRQSTATUSDISABLE	0xFFFF
 
+enum {
+	KBD_REVISION_OMAP4 = 0,
+	KBD_REVISION_OMAP5,
+};
+
 struct omap4_keypad {
 	struct input_dev *input;
 
@@ -76,11 +81,79 @@ struct omap4_keypad {
 
 	unsigned int rows;
 	unsigned int cols;
+	unsigned int revision;
 	unsigned int row_shift;
 	unsigned char key_state[8];
 	unsigned short keymap[];
 };
 
+static int kbd_read_irqstatus(struct omap4_keypad *keypad_data, u32 offset)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		return __raw_readl(keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		return __raw_readl(keypad_data->base + offset + 0x0c);
+
+	return -ENODEV;
+}
+
+static int kbd_write_irqstatus(struct omap4_keypad *keypad_data,
+						u32 offset, u32 value)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		return __raw_writel(value, keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		return __raw_writel(value, keypad_data->base + offset + 0x0c);
+
+	return -ENODEV;
+}
+
+static int kbd_write_irqenable(struct omap4_keypad *keypad_data,
+						u32 offset, u32 value)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		return __raw_writel(value, keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		return __raw_writel(value, keypad_data->base + offset + 0x0c);
+
+	return -ENODEV;
+}
+
+static int kbd_readl(struct omap4_keypad *keypad_data, u32 offset)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		return __raw_readl(keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		return __raw_readl(keypad_data->base + offset + 0x10);
+
+	return -ENODEV;
+}
+
+static void kbd_writel(struct omap4_keypad *keypad_data, u32 offset, u32 value)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		__raw_writel(value, keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		__raw_writel(value, keypad_data->base + offset + 0x10);
+}
+
+static int kbd_read_revision(struct omap4_keypad *keypad_data, u32 offset)
+{
+	int reg;
+	reg = __raw_readl(keypad_data->base + offset);
+	reg &= 0x03 << 30;
+	reg >>= 30;
+
+	switch (reg) {
+	case 1:
+		return KBD_REVISION_OMAP5;
+	case 0:
+		return KBD_REVISION_OMAP4;
+	default:
+		return -ENODEV;
+	}
+}
+
 /* Interrupt handler */
 static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
 {
@@ -91,12 +164,11 @@ static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
 	u32 *new_state = (u32 *) key_state;
 
 	/* Disable interrupts */
-	__raw_writel(OMAP4_VAL_IRQDISABLE,
-		     keypad_data->base + OMAP4_KBD_IRQENABLE);
+	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
+						OMAP4_VAL_IRQDISABLE);
 
-	*new_state = __raw_readl(keypad_data->base + OMAP4_KBD_FULLCODE31_0);
-	*(new_state + 1) = __raw_readl(keypad_data->base
-						+ OMAP4_KBD_FULLCODE63_32);
+	*new_state = kbd_readl(keypad_data, OMAP4_KBD_FULLCODE31_0);
+	*(new_state + 1) = kbd_readl(keypad_data, OMAP4_KBD_FULLCODE63_32);
 
 	for (row = 0; row < keypad_data->rows; row++) {
 		changed = key_state[row] ^ keypad_data->key_state[row];
@@ -121,12 +193,13 @@ static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
 		sizeof(keypad_data->key_state));
 
 	/* clear pending interrupts */
-	__raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS),
-			keypad_data->base + OMAP4_KBD_IRQSTATUS);
+	kbd_write_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS,
+			kbd_read_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS));
 
 	/* enable interrupts */
-	__raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN | OMAP4_DEF_IRQENABLE_LONGKEY,
-			keypad_data->base + OMAP4_KBD_IRQENABLE);
+	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
+			OMAP4_DEF_IRQENABLE_EVENTEN |
+				OMAP4_DEF_IRQENABLE_LONGKEY);
 
 	return IRQ_HANDLED;
 }
@@ -139,16 +212,19 @@ static int omap4_keypad_open(struct input_dev *input)
 
 	disable_irq(keypad_data->irq);
 
-	__raw_writel(OMAP4_VAL_FUNCTIONALCFG,
-			keypad_data->base + OMAP4_KBD_CTRL);
-	__raw_writel(OMAP4_VAL_DEBOUNCINGTIME,
-			keypad_data->base + OMAP4_KBD_DEBOUNCINGTIME);
-	__raw_writel(OMAP4_VAL_IRQDISABLE,
-			keypad_data->base + OMAP4_KBD_IRQSTATUS);
-	__raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN | OMAP4_DEF_IRQENABLE_LONGKEY,
-			keypad_data->base + OMAP4_KBD_IRQENABLE);
-	__raw_writel(OMAP4_DEF_WUP_EVENT_ENA | OMAP4_DEF_WUP_LONG_KEY_ENA,
-			keypad_data->base + OMAP4_KBD_WAKEUPENABLE);
+	keypad_data->revision = kbd_read_revision(keypad_data,
+			OMAP4_KBD_REVISION);
+	kbd_writel(keypad_data, OMAP4_KBD_CTRL,
+			OMAP4_VAL_FUNCTIONALCFG);
+	kbd_writel(keypad_data, OMAP4_KBD_DEBOUNCINGTIME,
+			OMAP4_VAL_DEBOUNCINGTIME);
+	kbd_write_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS,
+			OMAP4_VAL_IRQDISABLE);
+	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
+			OMAP4_DEF_IRQENABLE_EVENTEN |
+				OMAP4_DEF_IRQENABLE_LONGKEY);
+	kbd_writel(keypad_data, OMAP4_KBD_WAKEUPENABLE,
+			OMAP4_DEF_WUP_EVENT_ENA | OMAP4_DEF_WUP_LONG_KEY_ENA);
 
 	enable_irq(keypad_data->irq);
 
@@ -162,12 +238,12 @@ static void omap4_keypad_close(struct input_dev *input)
 	disable_irq(keypad_data->irq);
 
 	/* Disable interrupts */
-	__raw_writel(OMAP4_VAL_IRQDISABLE,
-		     keypad_data->base + OMAP4_KBD_IRQENABLE);
+	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
+			OMAP4_VAL_IRQDISABLE);
 
 	/* clear pending interrupts */
-	__raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS),
-			keypad_data->base + OMAP4_KBD_IRQSTATUS);
+	kbd_write_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS,
+			kbd_read_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS));
 
 	enable_irq(keypad_data->irq);
 
-- 
1.7.1



From msalter at redhat.com  Fri Mar 16 10:40:06 2012
From: msalter at redhat.com (Mark Salter)
Date: Fri, 16 Mar 2012 10:40:06 -0400
Subject: [PATCH 05/38] Disintegrate asm/system.h for ARM [ver #3]
In-Reply-To: <20120315205603.28759.91855.stgit@warthog.procyon.org.uk>
References: <20120315205514.28759.58969.stgit@warthog.procyon.org.uk>
 <20120315205603.28759.91855.stgit@warthog.procyon.org.uk>
Message-ID: <1331908808.12353.2.camel@deneb.redhat.com>

On Thu, 2012-03-15 at 20:56 +0000, David Howells wrote:
> Signed-off-by: David Howells <dhowells at redhat.com>
> cc: linux-arm-kernel at lists.infradead.org
> ---

<snip>

> diff --git a/include/linux/mtd/map.h b/include/linux/mtd/map.h
> index 94e924e..d9072d9 100644
> --- a/include/linux/mtd/map.h
> +++ b/include/linux/mtd/map.h
> @@ -1,4 +1,4 @@
> -/*
> + r/*
>   * Copyright ? 2000-2010 David Woodhouse <dwmw2 at infradead.org> et al.
>   *
>   * This program is free software; you can redistribute it and/or modify
> 

Looks like this hunk was unintended. It is causing a build failure for
me.

--Mark




From catalin.marinas at arm.com  Fri Mar 16 10:40:01 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 16 Mar 2012 14:40:01 +0000
Subject: spinlock_t and tagged memory block size
In-Reply-To: <CABcrWnUQ_4-nrZkt_zw5VC=cYJBfmaPsU7ktjMf2=xk7+=PArQ@mail.gmail.com>
References: <CABcrWnUQ_4-nrZkt_zw5VC=cYJBfmaPsU7ktjMf2=xk7+=PArQ@mail.gmail.com>
Message-ID: <CAHkRjk4mu-LCEscGN_mN0R1J7LHsTUFNx519qnjt1tNuL4dnfw@mail.gmail.com>

On 16 March 2012 11:44, Rui Sousa <rui.p.m.sousa at gmail.com> wrote:
> Cortex-A9 architecture defines the minimum size of tagged memory block
> (used on load/store exclusives) to be 2^3 = 8bytes (Cortex A9 r2p2,
> Technical Reference Manual, page 4-8).
> However, the spinlock_t structure size (if preemption and spinlock
> debug options are all disabled) is only 4bytes.
> AFAICS, this will break spinlocks if two spinlocks are linked next to
> each other. Am I right, or did I miss something?

It won't break, only that if two CPUs try to acquire the different
locks at the same time, only one will succeed the first time, the
other will need to go through the LDREX/STREX loop once more.

-- 
Catalin


From monstr at monstr.eu  Fri Mar 16 10:57:40 2012
From: monstr at monstr.eu (Michal Simek)
Date: Fri, 16 Mar 2012 15:57:40 +0100
Subject: [PATCH 1/7] remoteproc: resource table overhaul
In-Reply-To: <1330589497-4139-2-git-send-email-ohad@wizery.com>
References: <1330589497-4139-1-git-send-email-ohad@wizery.com>
 <1330589497-4139-2-git-send-email-ohad@wizery.com>
Message-ID: <4F6354E4.8030704@monstr.eu>

Hi Ohad,

Ohad Ben-Cohen wrote:
> The resource table is an array of 'struct fw_resource' members, where
> each resource entry is expressed as a single member of that array.
> 
> This approach got us this far, but it has a few drawbacks:
> 
> 1. Different resource entries end up overloading the same members of 'struct
>    fw_resource' with different meanings. The resulting code is error prone
>    and hard to read and maintain.
> 
> 2. It's impossible to extend 'struct fw_resource' without breaking the
>    existing firmware images (and we already want to: we can't introduce the
>    new virito device resource entry with the current scheme).
> 
> 3. It doesn't scale: 'struct fw_resource' must be as big as the largest
>    resource entry type. As a result, smaller resource entries end up
>    utilizing only small part of it.
> 
> This is fixed by defining a dedicated structure for every resource type,
> and then converting the resource table to a list of type-value members.
> Instead of a rigid array of homogeneous structs, the resource table
> is turned into a collection of heterogeneous structures.
> 
> This way:
> 1. Resource entries consume exactly the amount of bytes they need.
> 2. It's easy to extend: just create a new resource entry structure, and assign
>    it a new type.
> 3. The code is easier to read and maintain: the structures' members names are
>    meaningful.
> 
> While we're at it, this patch has several other resource table changes:
> 1. The resource table gains a simple header which contains the
>    number of entries in the table and their offsets within the table. This
>    makes the parsing code simpler and easier to read.
> 2. A version member is added to the resource table. Should we change the
>    format again, we'll bump up this version to prevent breakage with
>    existing firmware images.
> 3. The VRING and VIRTIO_DEV resource entries are combined to a single
>    VDEV entry. This paves the way to supporting multiple VDEV entries.
> 4. Since we don't really support 64-bit rprocs yet, convert two stray u64
>    members to u32.

I don't want to look for in this patch but there is one change which completely
break my remoteproc for dual core ARM.

I am using ohad-github/rpmsg_3.3_rc6_TLV branch and I have also changed resource
table to get it work.

Here is the part of log where you can see what happen.

rproc_handle_virtio_rsc: rsc type 0
rproc_handle_virtio_rsc: rsc type 3
vdev rsc: id 7, dfeatures 1, cfg len 0, 2 vrings
vdev rsc: vring0: da 100000, qsz 256, align 4096
vring0: va e1000000 dma 0 size 3000 idr 0
vdev rsc: vring1: da 104000, qsz 256, align 4096
vring1: va e1004000 dma 4000 size 3000 idr 1
zynq-rproc zynq-rproc.1: powering up cpu1_freertos
zynq-rproc zynq-rproc.1: Booting fw image test, size 211118
iommu not found
rsc: type 0
carveout rsc: da 0, pa 0, len 100000, flags 0
carveout va e1100000, dma 100000, len 0x100000
rsc: type 3
rsc: type 2
trace0 added: va e1140000, da 0x40000, len 0x8000
phdr: type 1 da 0x0 memsz 0x1ae60 filesz 0x14014

The problem which I have is that vdev entry and vrings are handled first
and in __rproc_handle_vring calls dma_alloc_coherent first which caused
that virtaddr points to memory start (remapped to virt addr 0xe1000000)
which should be used by code.

In previous version I had carverout first which means that code was copyied
to physical address 0x0 and then vrigns were allocated. Current code allocate
vring first and then RTOS is not able to run from zero address.

Thanks,
Michal




-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian


From jean.pihet at newoldbits.com  Fri Mar 16 11:19:31 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Fri, 16 Mar 2012 16:19:31 +0100
Subject: [PATCH 02/10] ARM: OMAP2+: SmartReflex: move the platform
 specific macros in plat-omap
In-Reply-To: <20120315171359.GA7276@atomide.com>
References: <1331829845-9526-1-git-send-email-j-pihet@ti.com>
 <1331829845-9526-3-git-send-email-j-pihet@ti.com>
 <20120315171359.GA7276@atomide.com>
Message-ID: <CAORVsuUp9VBX1XbkQkcq91XsbRSut1RC6KCNPFHrX+RfWv7hQA@mail.gmail.com>

Hi Tony,

On Thu, Mar 15, 2012 at 6:14 PM, Tony Lindgren <tony at atomide.com> wrote:
> * jean.pihet at newoldbits.com <jean.pihet at newoldbits.com> [120315 09:47]:
>> From: Jean Pihet <j-pihet at ti.com>
>>
>> Move the platform specific macros from the smartreflex header file
>> (arch/arm/mach-omap2/smartreflex.h) in a new header file in plat-omap
>> (arch/arm/plat-omap/include/plat/smartreflex.h).
>>
>> This change makes the SmartReflex implementation ready for the move
>> to drivers/.
>
> Glad to see this happening!
>
> This would be better located in linux/power/smartreflex.h rather than
> plat/smartreflex.h.
Ok. Is the file name still Ok in that case? Should it mention OMAP?

Thanks,
Jean

>
> Regards,
>
> Tony


From lost.distance at yahoo.com  Fri Mar 16 11:24:35 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 16 Mar 2012 15:24:35 +0000 (GMT)
Subject: [PATCH] pxa/hx4700: Add standard UART to hx4700_pin_config[]
Message-ID: <1331911475.54244.YahooMailClassic@web29012.mail.ird.yahoo.com>

Add the two standard UART signals (GPIO46_STUART_RXD, GPIO47_STUART_TXD) to the
initial mfp config table hx4700_pin_config[] passed to pxa2xx_mfp_config().
Although pxa2xx_transceiver_mode() can subsequently set these two signals via
its own call to pxa2xx_mfp_config(), pxa2xx_transceiver_mode() is only present
when CONFIG_PXA_FICP=y. Hence this patch provides a default mfp config.

Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
---

--- a/arch/arm/mach-pxa/hx4700.c	2012-03-16 15:18:29.636709575 +0000
+++ b/arch/arm/mach-pxa/hx4700.c	2012-03-16 15:19:35.401070040 +0000
@@ -101,6 +101,10 @@ static unsigned long hx4700_pin_config[]
 	GPIO44_BTUART_CTS,
 	GPIO45_BTUART_RTS_LPM_LOW,
 
+	/* STUART (IRDA) */
+	GPIO46_STUART_RXD,
+	GPIO47_STUART_TXD,
+
 	/* PWM 1 (Backlight) */
 	GPIO17_PWM1_OUT,
 



From Maximilian.Schwerin at tigris.de  Fri Mar 16 11:47:15 2012
From: Maximilian.Schwerin at tigris.de (Maximilian Schwerin)
Date: Fri, 16 Mar 2012 16:47:15 +0100
Subject: AW: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting to
 add IVA OPP
In-Reply-To: <20120316142034.GA22234@senorita.am.dhcp.ti.com>
Message-ID: <5448984682E7954C9BFF27F747A9C6CA56D6BE@dolphin.TIGRIS.local>

> -----Urspr?ngliche Nachricht-----
> Von: Nishanth Menon [mailto:nm at ti.com] 
> Gesendet: Freitag, 16. M?rz 2012 15:21
> An: Maximilian Schwerin
> Cc: Kevin Hilman; linux-omap at vger.kernel.org; 
> linux-arm-kernel at lists.infradead.org; Steve Sakoman
> Betreff: Re: [PATCH] OMAP3: OPP: Test for IVA subsystem 
> before attempting to add IVA OPP
> 
> On 10:26-20120316, Maximilian Schwerin wrote:
> [...]
> > > >>> +
> > > >>> + ? ? ? ? ? ? if ((strcmp(opp_def->hwmod_name,"iva") == 
> > > 0) && !omap3_has_iva())
> > > >>> + ? ? ? ? ? ? ? ? ? ? continue;
> > > >>> +
> > > >>> ? ? ? ? ? ? ? oh = omap_hwmod_lookup(opp_def->hwmod_name);
> > > >>> ? ? ? ? ? ? ? if (!oh || !oh->od) {
> > > >>> ? ? ? ? ? ? ? ? ? ? ? pr_warn("%s: no hwmod or odev 
> for %s, [%d] "
> > > >>
> > > >> Wouldn't the one-liner below do the same thing?
> > > >>
> > > >> Actually, your patch makes it less noisy at boot time, 
> avoiding the
> > > >> pr_warn(), so is probably better.
> > > >
> > > > The only issue i have with current patch is that it 
> > > focusses to solve
> > > > a specific device IVA.
> > > > we could have similar variances if we had SGX/AESS device etc
> > > > registered in the common
> > > > table. a generic solution might be preferable - could 
> we reduce the
> > > > severity of pr_warn to pr_debug and do a continue instead?
> > > 
> > > I agree, that would be a better generic solution.
> > > 
> > > Kevin
> > >
> > 
> > This is a pragmatic and simple solution for a well 
> understood problem with no side effects. Why not fix the 
> problem now and do the generic solution later on? 
> > 
> > I'm not a fulltime kernel dev. I have about two weeks to 
> get my new board out to my customer... Every time I set up a 
> new board, I have to fix problems using known patches that 
> are sometimes years old. Every patch I have to find costs me 
> hours of time I really don't have. 
> > 
> > Just my two cents (euro cents of course :-), Maximilian
> ok, so lets fix it generically - here is the patch for it. Let us know
> if this works for you
> 
> 
> From 5275d09c9f1a16c8f0814745e1c313c6cca049f6 Mon Sep 17 00:00:00 2001
> From: Nishanth Menon <nm at ti.com>
> Date: Fri, 16 Mar 2012 09:13:24 -0500
> Subject: [PATCH] OMAP2+: OPP: allow OPP enumeration to 
> continue if device is not present
> 
> On platforms such as OMAP3, certain variants may not have IVA, SGX
> or some specific component. We currently have a check to aid fixing
> wrong population of OPP entries for issues such as typos. This however
> causes a conflict with valid requirement where the SoC variant does
> not actually have the module present.
> 
> So, reduce the severity of the print to a debug statement and skip
> registering that specific OPP, but continue down the list.
> 
> Reported-by: Steve Sakoman <steve at sakoman.com>
> Reported-by: Maximilian Schwerin <mvs at tigris.de>
> Signed-off-by: Nishanth Menon <nm at ti.com>
> ---
>  arch/arm/mach-omap2/opp.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
> index 9262a6b..de6d464 100644
> --- a/arch/arm/mach-omap2/opp.c
> +++ b/arch/arm/mach-omap2/opp.c
> @@ -64,10 +64,10 @@ int __init omap_init_opp_table(struct 
> omap_opp_def *opp_def,
>  		}
>  		oh = omap_hwmod_lookup(opp_def->hwmod_name);
>  		if (!oh || !oh->od) {
> -			pr_warn("%s: no hwmod or odev for %s, [%d] "
> +			pr_debug("%s: no hwmod or odev for %s, [%d] "
>  				"cannot add OPPs.\n", __func__,
>  				opp_def->hwmod_name, i);
> -			return -EINVAL;
> +			continue;
>  		}
>  		dev = &oh->od->pdev->dev;
>  
> -- 
> 1.7.0.4
> 
> 
> -- 
> Regards,
> Nishanth Menon

Hi,

sorry my fault! This was not what I was thinking of as generic. Works as expected!

Thanks, m.
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From nm at ti.com  Fri Mar 16 11:57:35 2012
From: nm at ti.com (Menon, Nishanth)
Date: Fri, 16 Mar 2012 10:57:35 -0500
Subject: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting to
 add IVA OPP
In-Reply-To: <5448984682E7954C9BFF27F747A9C6CA56D6BE@dolphin.TIGRIS.local>
References: <20120316142034.GA22234@senorita.am.dhcp.ti.com>
 <5448984682E7954C9BFF27F747A9C6CA56D6BE@dolphin.TIGRIS.local>
Message-ID: <CAOMWX4ckGQWXd7yogT61pSCAKoHU3vFM7PubFkDKhog3OhJryw@mail.gmail.com>

On Fri, Mar 16, 2012 at 10:47, Maximilian Schwerin
<Maximilian.Schwerin at tigris.de> wrote:
>
> sorry my fault! This was not what I was thinking of as generic. Works as
> expected!
Can i take it as an acked-by?

Regards,
Nishanth Menon


From steve at sakoman.com  Fri Mar 16 12:04:28 2012
From: steve at sakoman.com (Steve Sakoman)
Date: Fri, 16 Mar 2012 09:04:28 -0700
Subject: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting to
 add IVA OPP
In-Reply-To: <20120316142034.GA22234@senorita.am.dhcp.ti.com>
References: <8762e6et1u.fsf@ti.com>
 <5448984682E7954C9BFF27F747A9C6CA56D6A8@dolphin.TIGRIS.local>
 <20120316142034.GA22234@senorita.am.dhcp.ti.com>
Message-ID: <CAOSpxdaTcMnp5tvNFO1AcvZJPXZ+X0GkVv6NBt59LmzuFGVdUA@mail.gmail.com>

On Fri, Mar 16, 2012 at 7:20 AM, Nishanth Menon <nm at ti.com> wrote:
> From 5275d09c9f1a16c8f0814745e1c313c6cca049f6 Mon Sep 17 00:00:00 2001
> From: Nishanth Menon <nm at ti.com>
> Date: Fri, 16 Mar 2012 09:13:24 -0500
> Subject: [PATCH] OMAP2+: OPP: allow OPP enumeration to continue if device is not present
>
> On platforms such as OMAP3, certain variants may not have IVA, SGX
> or some specific component. We currently have a check to aid fixing
> wrong population of OPP entries for issues such as typos. This however
> causes a conflict with valid requirement where the SoC variant does
> not actually have the module present.
>
> So, reduce the severity of the print to a debug statement and skip
> registering that specific OPP, but continue down the list.
>
> Reported-by: Steve Sakoman <steve at sakoman.com>
> Reported-by: Maximilian Schwerin <mvs at tigris.de>
> Signed-off-by: Nishanth Menon <nm at ti.com>
> ---
> ?arch/arm/mach-omap2/opp.c | ? ?4 ++--
> ?1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
> index 9262a6b..de6d464 100644
> --- a/arch/arm/mach-omap2/opp.c
> +++ b/arch/arm/mach-omap2/opp.c
> @@ -64,10 +64,10 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
> ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ?oh = omap_hwmod_lookup(opp_def->hwmod_name);
> ? ? ? ? ? ? ? ?if (!oh || !oh->od) {
> - ? ? ? ? ? ? ? ? ? ? ? pr_warn("%s: no hwmod or odev for %s, [%d] "
> + ? ? ? ? ? ? ? ? ? ? ? pr_debug("%s: no hwmod or odev for %s, [%d] "
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"cannot add OPPs.\n", __func__,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?opp_def->hwmod_name, i);
> - ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? ? ? ? ? ? ? ? ? continue;
> ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ?dev = &oh->od->pdev->dev;
>
> --
> 1.7.0.4

Acked-by: Steve Sakoman <steve at sakoman.com>


From nm at ti.com  Fri Mar 16 12:19:09 2012
From: nm at ti.com (Nishanth Menon)
Date: Fri, 16 Mar 2012 11:19:09 -0500
Subject: [PATCH] OMAP2+: OPP: allow OPP enumeration to continue if device is
 not present
Message-ID: <1331914749-23171-1-git-send-email-nm@ti.com>

On platforms such as OMAP3, certain variants may not have IVA, SGX
or some specific component. We currently have a check to aid fixing
wrong population of OPP entries for issues such as typos. This however
causes a conflict with valid requirement where the SoC variant does
not actually have the module present.

So, reduce the severity of the print to a debug statement and skip
registering that specific OPP, but continue down the list.

Reported-by: Steve Sakoman <steve at sakoman.com>
Reported-by: Maximilian Schwerin <mvs at tigris.de>
Acked-by: Steve Sakoman <steve at sakoman.com>
Tested-by: Maximilian Schwerin <mvs at tigris.de>
Signed-off-by: Nishanth Menon <nm at ti.com>
---
Discussion: http://marc.info/?t=133174689300002&r=1&w=2
 arch/arm/mach-omap2/opp.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index 9262a6b..de6d464 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -64,10 +64,10 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
 		}
 		oh = omap_hwmod_lookup(opp_def->hwmod_name);
 		if (!oh || !oh->od) {
-			pr_warn("%s: no hwmod or odev for %s, [%d] "
+			pr_debug("%s: no hwmod or odev for %s, [%d] "
 				"cannot add OPPs.\n", __func__,
 				opp_def->hwmod_name, i);
-			return -EINVAL;
+			continue;
 		}
 		dev = &oh->od->pdev->dev;
 
-- 
1.7.0.4



From dmitry.torokhov at gmail.com  Fri Mar 16 12:36:19 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Fri, 16 Mar 2012 09:36:19 -0700
Subject: [PATCH 1/2] input: keypad: move platform_data to
 <linux/platform_data>
In-Reply-To: <1331907989-11891-2-git-send-email-sourav.poddar@ti.com>
References: <1331907989-11891-1-git-send-email-sourav.poddar@ti.com>
 <1331907989-11891-2-git-send-email-sourav.poddar@ti.com>
Message-ID: <1357514.ox9yZWgqO9@dtor-d630.eng.vmware.com>

On Friday, March 16, 2012 07:56:28 PM Sourav Poddar wrote:
> From: Felipe Balbi <balbi at ti.com>
> 
> This patch allows us to drop the OMAP depencendy
> from the OMAP4 keypad driver.
> 
> Signed-off-by: Felipe Balbi <balbi at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
>  arch/arm/mach-omap2/board-4430sdp.c            |    1 +
>  arch/arm/mach-omap2/devices.c                  |    1 +
>  arch/arm/plat-omap/include/plat/omap4-keypad.h |    9 ---------
>  drivers/input/keyboard/Kconfig                 |    1 -
>  drivers/input/keyboard/omap4-keypad.c          |    2 +-
>  include/linux/platform_data/omap4-keypad.h     |   13 +++++++++++++

Instead of creating platform_data directory why not move to
include/linux/input/omap4-keypad.h?

Thanks.

-- 
Dmitry


From mturquette at ti.com  Fri Mar 16 12:51:19 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 16 Mar 2012 09:51:19 -0700
Subject: [PATCH v7 3/3] clk: basic clock hardware types
In-Reply-To: <20120316122542.GA1774@richard-laptop>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-4-git-send-email-mturquette@linaro.org>
 <20120316122542.GA1774@richard-laptop>
Message-ID: <CAJOA=zPvukWMdEmvtpPEvjmTv3X2Ar72ULzHf=Tb-O8CY-sRMw@mail.gmail.com>

On Fri, Mar 16, 2012 at 5:25 AM, Richard Zhao <richard.zhao at linaro.org> wrote:
> [...]
>> +static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
>> + ? ? ? ? ? ? unsigned long *best_parent_rate)
>> +{
>> + ? ? struct clk_divider *divider = to_clk_divider(hw);
>> + ? ? int i, bestdiv = 0;
>> + ? ? unsigned long parent_rate, best = 0, now, maxdiv;
>> +
>> + ? ? if (!rate)
>> + ? ? ? ? ? ? rate = 1;
>> +
>> + ? ? maxdiv = (1 << divider->width);
>> +
>> + ? ? if (divider->flags & CLK_DIVIDER_ONE_BASED)
>> + ? ? ? ? ? ? maxdiv--;
>> +
>> + ? ? if (!best_parent_rate) {
>> + ? ? ? ? ? ? parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
>> + ? ? ? ? ? ? bestdiv = DIV_ROUND_UP(parent_rate, rate);
>> + ? ? ? ? ? ? bestdiv = bestdiv == 0 ? 1 : bestdiv;
>> + ? ? ? ? ? ? bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
>> + ? ? ? ? ? ? return bestdiv;
>> + ? ? }
>> +
>> + ? ? /*
>> + ? ? ?* The maximum divider we can use without overflowing
>> + ? ? ?* unsigned long in rate * i below
>> + ? ? ?*/
>> + ? ? maxdiv = min(ULONG_MAX / rate, maxdiv);
>> +
>> + ? ? for (i = 1; i <= maxdiv; i++) {
>> + ? ? ? ? ? ? parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? MULT_ROUND_UP(rate, i));
>> + ? ? ? ? ? ? now = parent_rate / i;
>> + ? ? ? ? ? ? if (now <= rate && now > best) {
>> + ? ? ? ? ? ? ? ? ? ? bestdiv = i;
>> + ? ? ? ? ? ? ? ? ? ? best = now;
>> + ? ? ? ? ? ? ? ? ? ? *best_parent_rate = parent_rate;
> Better add ? ? ? ? ? ? ?if (now == rate)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?break;
> There may be more than one hit for (now == rate). We'd better select
> smallest div, thus smallest parent_rate.

Hmm I forgot to take this in.  Notice that the conditional above has changed:

if (now <= rate && now > best) {

So the smallest divider _will_ be selected, but adding in your check
for now == rate is nice since it will prevent unnecessary looping if
we've managed to hit the exact rate that we want.  I'll ninja this one
into the merge request.

Thanks,
Mike

>
> It's the same comment for v6, but not show stopper.
>
> Thanks
> Richard
>> + ? ? ? ? ? ? }
>> + ? ? }
>> +
>> + ? ? if (!bestdiv) {
>> + ? ? ? ? ? ? bestdiv = (1 << divider->width);
>> + ? ? ? ? ? ? if (divider->flags & CLK_DIVIDER_ONE_BASED)
>> + ? ? ? ? ? ? ? ? ? ? bestdiv--;
>> + ? ? ? ? ? ? *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
>> + ? ? }
>> +
>> + ? ? return bestdiv;
>> +}
>


From nsekhar at ti.com  Fri Mar 16 12:59:56 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Fri, 16 Mar 2012 16:59:56 +0000
Subject: [GIT PULL v2] DaVinci DM644x video display support
In-Reply-To: <201203152036.36133.arnd@arndb.de>
References: <DF0F476B391FA8409C78302C7BA518B6317F13DB@DBDE01.ent.ti.com>
 <201203152036.36133.arnd@arndb.de>
Message-ID: <DF0F476B391FA8409C78302C7BA518B6317FB3D7@DBDE01.ent.ti.com>

Hi Arnd,

On Fri, Mar 16, 2012 at 02:06:35, Arnd Bergmann wrote:
> On Sunday 11 March 2012, Nori, Sekhar wrote:
> > Hi Arnd, Olof,
> > 
> > Can you please pull these two patches adding support
> > for DaVinci DM644x V4L2 display support for v3.4.
> > 
> > These patches heavily depend on the clean-up series sent
> > earlier. I have re-generated the pull request against
> > v3.4/cleanup branch of my tree (already pulled earlier
> > and unchanged since) as suggested by Olof.
> > 
> > Let me know if this works for you.
> 
> Looks good, applied to the next/drivers branch now.
> Sorry for missing the pull request earlier, that was my fault
> and I should have pulled it already.
> 
> I got a small merge conflict, see the resolution below.

Thanks for pulling this. The merge conflict resolution
was correct.

Regards,
Sekhar



From sameo at linux.intel.com  Fri Mar 16 13:14:46 2012
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Fri, 16 Mar 2012 18:14:46 +0100
Subject: [PATCH] mfd: pcap: depend on arch-pxa
In-Reply-To: <1331011808-28307-1-git-send-email-haojian.zhuang@gmail.com>
References: <1331011808-28307-1-git-send-email-haojian.zhuang@gmail.com>
Message-ID: <20120316171446.GF20524@sortiz-mobl>

Hi Haojian,

On Tue, Mar 06, 2012 at 01:30:08PM +0800, Haojian Zhuang wrote:
> drivers/mfd/ezx-pcap.c: In function ?pcap_isr_work?:
> drivers/mfd/ezx-pcap.c:206:2: error: implicit declaration of function
> ?pxa_irq_to_gpio?
> make[2]: *** [drivers/mfd/ezx-pcap.o] Error 1
You get that error once you replace irq_to_gpio() with pxa_irq_to_gpio().


> PCAP driver invokes irq_to_gpio() directly. This function isn't common
> function in most silicons. PCAP driver is enabled for EZX machine with
> arch-pxa. Now use pxa_irq_to_gpio() instead.
> 
> It's only a workaround for this issue. Acutally the best solution is
> using thread irq to fix this issue.
How would that fix the problem ? Defining irq_to_gpio for the PXA arch sounds
like a better option. I don't particularily like this patch as it restricts
the pcap driver quite a lot.
Would you be able to look at fixing the PXA gpio.h instead ?

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From lauraa at codeaurora.org  Fri Mar 16 13:21:02 2012
From: lauraa at codeaurora.org (Laura Abbott)
Date: Fri, 16 Mar 2012 10:21:02 -0700
Subject: [PATCH] arm: Add unwinding support for memset and memzero.
In-Reply-To: <20120314111504.GA2033@linaro.org>
References: <1331574027-28542-1-git-send-email-lauraa@codeaurora.org>
 <20120314111504.GA2033@linaro.org>
Message-ID: <4F63767E.3020706@codeaurora.org>

On 3/14/2012 4:15 AM, Dave Martin wrote:
>
> For functions like this, the unwinding requirements are different
> depending on where we are in the function.  But the unwinder annotations
> don't remember exact instruction locations; only the extent of the
> whole unwind block is recorded, along with the sequence (but not
> location) of unwinder directives.
>
> As is, the unwinding may be wrong depending on which part of the function
> is executing when the fault occurs.
>

Hmmmm, I thought I could get away with only one annotation based on the 
structure of memset/memzero but looking again you are right, it really 
requires multiple annotations to be correct.

> It may be possible to split the function into multiple unwind blocks,
> e.g.:
>
> ENTRY(somefunc)
> UNWIND(.fnstart)
>
> UNWIND(.save {r4,lr})
> 	stfmd	sp!, {r4,lr}
>
> 	/* check something */
>
> 	blt	_the_other_way
> 	/* maybe carry out our job this way */
>
> 	ldmfd	sp!, {r4,lr}
> UNWIND(.fnend)
>
> _the_other_way:
> UNWIND(.fnstart)
> UNWIND(.save {r4,lr})
> UNWIND(.save {r5-r8})
> 	stmfd	sp!, {r5-r8}	/* !! */
>
> 	/* carry out our job the other way */
>
> 	ldmfd	sp!, {r5-r8}
> 	ldmfd	sp!, {r4,pc}	/* !! */
> UNWIND(.fnend)
>
>
> This is still not exactly right (it's hard to be exactly right,
> since the unwind tables are not meant for handling asynchronous
> unwinding), but unwinding should be correct for the main bits of code
> where most time is spent and/or faults are most likely (the "carry out
> our job" comments).
>

Would a compiler be able to generate code such as this and still 
generate correct completely unwinding annotations? Or if the compiler 
knows unwinding is necessary, is the only option to generate code in 
'unwindable blocks'? (alternatively, no compiler is smart/stupid enough 
to generate this code?)

> You'd have to experiment to see whether the backtracer does something
> sensible with unwind tables like this.  It might need tweaking to
> find the correct function symbol if a fault occurs in the second
> unwind block for example ... that perhaps it will already do the
> right thing.
>

Yes, I'll look into this. memcpy is missing annotations as well but that 
code is significantly more convoluted.

> Cheers
> ---Dave
>

Thanks,
Laura

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From sameo at linux.intel.com  Fri Mar 16 13:29:08 2012
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Fri, 16 Mar 2012 18:29:08 +0100
Subject: [PATCH v5 2/3] arm:davinci: move emif driver to mfd framework
In-Reply-To: <A73F36158E33644199EB82C5EC81C7BC317702E9@DBDE01.ent.ti.com>
References: <y> <1330005504-25321-3-git-send-email-prakash.pm@ti.com>
 <20120227142638.GN27687@sortiz-mobl>
 <A73F36158E33644199EB82C5EC81C7BC3176D103@DBDE01.ent.ti.com>
 <20120301112329.GI9008@sortiz-mobl>
 <A73F36158E33644199EB82C5EC81C7BC317702E9@DBDE01.ent.ti.com>
Message-ID: <20120316172908.GG20524@sortiz-mobl>

Hi Prakash,

On Tue, Mar 06, 2012 at 01:12:25PM +0000, Manjunathappa, Prakash wrote:
> Hi Samuel,
> 
> May be I did not do a good job giving complete information on this earlier.
> So I have replied on top of my mail with below information (seems you missed it)
> 
I did get it, sorry for not being able to reply earlier.


> Taking above points into consideration Arnd Bergmann suggested to move AEMIF driver to
> MFD framework [1], relevant portion of his mail as follows,
> 
> " If you want it to provide endpoint devices that are handled by
> distinct subsystems in Linux, I would make it an mfd multifunction
> device and make the common... "
You're missing that part of the quote:

"...code a driver that scans the connected memories in order to register
its child devices for each of the subsystems."

If you can do that, then I'd take that patch to the MFD subsystem. Otherwise,
the only incentive for me to take it would be to be able to share the 2
functions currently in this driver between several archs. But MFD would just
be a placeholder for this driver right now.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From philipp.zabel at gmail.com  Fri Mar 16 13:35:43 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Fri, 16 Mar 2012 18:35:43 +0100
Subject: [RFC/PATCH 0/4] pxa: attempt at switch to common clock framework
Message-ID: <1331919343.31118.19.camel@flow>

Hi,

I have made an attempt at an initial conversion of PXA clocks to the
common clock framework (http://lkml.org/lkml/2012/3/16/25), and I'd
like to know if somebody is already working on this, or if I am
heading in the general right direction.

Unfortunately, this set still hangs during boot on hx4700 (pxa270),
unless I also disable the calls to __clk_lookup in drivers/clk/clk.c
completely (or apply the patch below). I'll investigate once I get
access to my serial cable and hx4700 charger, but I'd be grateful if
somebody could spot any embarassingly obvious errors.
For pxa25x and pxa3xx, it's compile-tested only.

regards
Philipp

---
 drivers/clk/clk.c |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index c7c3bc5..79b46af 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -336,14 +336,15 @@ static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
 	struct hlist_node *tmp;
 
 	if (!strcmp(clk->name, name))
-		return clk;
+		return NULL;
 
+#if 0
 	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
 		ret = __clk_lookup_subtree(name, child);
 		if (ret)
 			return ret;
 	}
-
+#endif
 	return NULL;
 }
 
-- 
1.7.9.1




From philipp.zabel at gmail.com  Fri Mar 16 13:36:13 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Fri, 16 Mar 2012 18:36:13 +0100
Subject: [RFC/PATCH 1/4] pxa: Remove INIT_CLKREG macro, replace it with the
 equivalent CLKDEV_INIT
Message-ID: <1331919373.31118.20.camel@flow>

The CLKDEV_INIT macro was added in 196a57c2749119be4732cc2b2adb8aafcb4fcb14
(ARM: 7131/1: clkdev: Add Common Macro for clk_lookup) for this purpose.

Signed-off-by: Philipp Zabel <philipp.zabel at gmail.com>
---
 arch/arm/mach-pxa/clock.h   |    7 -----
 arch/arm/mach-pxa/eseries.c |    2 +-
 arch/arm/mach-pxa/pxa25x.c  |   42 ++++++++++++++++----------------
 arch/arm/mach-pxa/pxa27x.c  |   56 +++++++++++++++++++++---------------------
 arch/arm/mach-pxa/pxa300.c  |    6 ++--
 arch/arm/mach-pxa/pxa320.c  |    4 +-
 arch/arm/mach-pxa/pxa3xx.c  |   48 ++++++++++++++++++------------------
 arch/arm/mach-pxa/pxa95x.c  |   32 ++++++++++++------------
 8 files changed, 95 insertions(+), 102 deletions(-)

diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 3a258b1..2946fa2 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -22,13 +22,6 @@ void clk_dummy_disable(struct clk *);
 extern const struct clkops clk_dummy_ops;
 extern struct clk clk_dummy;
 
-#define INIT_CLKREG(_clk,_devname,_conname)		\
-	{						\
-		.clk		= _clk,			\
-		.dev_id		= _devname,		\
-		.con_id		= _conname,		\
-	}
-
 #define DEFINE_CK(_name, _cken, _ops)			\
 struct clk clk_##_name = {				\
 		.ops	= _ops,				\
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 4cb2391..3c29343 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -141,7 +141,7 @@ static struct clk tmio_dummy_clk = {
 };
 
 static struct clk_lookup eseries_clkregs[] = {
-	INIT_CLKREG(&tmio_dummy_clk, NULL, "CLK_CK32K"),
+	CLKDEV_INIT(NULL, "CLK_CK32K", &tmio_dummy_clk),
 };
 
 static void __init eseries_register_clks(void)
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 3352b37..99dd55e 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -189,30 +189,30 @@ static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
 static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
 
 static struct clk_lookup pxa25x_clkregs[] = {
-	INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
-	INIT_CLKREG(&clk_pxa25x_ffuart, "pxa2xx-uart.0", NULL),
-	INIT_CLKREG(&clk_pxa25x_btuart, "pxa2xx-uart.1", NULL),
-	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-uart.2", NULL),
-	INIT_CLKREG(&clk_pxa25x_usb, "pxa25x-udc", NULL),
-	INIT_CLKREG(&clk_pxa25x_mmc, "pxa2xx-mci.0", NULL),
-	INIT_CLKREG(&clk_pxa25x_i2c, "pxa2xx-i2c.0", NULL),
-	INIT_CLKREG(&clk_pxa25x_ssp, "pxa25x-ssp.0", NULL),
-	INIT_CLKREG(&clk_pxa25x_nssp, "pxa25x-nssp.1", NULL),
-	INIT_CLKREG(&clk_pxa25x_assp, "pxa25x-nssp.2", NULL),
-	INIT_CLKREG(&clk_pxa25x_pwm0, "pxa25x-pwm.0", NULL),
-	INIT_CLKREG(&clk_pxa25x_pwm1, "pxa25x-pwm.1", NULL),
-	INIT_CLKREG(&clk_pxa25x_i2s, "pxa2xx-i2s", NULL),
-	INIT_CLKREG(&clk_pxa25x_stuart, "pxa2xx-ir", "UARTCLK"),
-	INIT_CLKREG(&clk_pxa25x_ficp, "pxa2xx-ir", "FICPCLK"),
-	INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
-	INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
-	INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
-	INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
-	INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+	CLKDEV_INIT("pxa2xx-fb", NULL, &clk_pxa25x_lcd),
+	CLKDEV_INIT("pxa2xx-uart.0", NULL, &clk_pxa25x_ffuart),
+	CLKDEV_INIT("pxa2xx-uart.1", NULL, &clk_pxa25x_btuart),
+	CLKDEV_INIT("pxa2xx-uart.2", NULL, &clk_pxa25x_stuart),
+	CLKDEV_INIT("pxa25x-udc", NULL, &clk_pxa25x_usb),
+	CLKDEV_INIT("pxa2xx-mci.0", NULL, &clk_pxa25x_mmc),
+	CLKDEV_INIT("pxa2xx-i2c.0", NULL, &clk_pxa25x_i2c),
+	CLKDEV_INIT("pxa25x-ssp.0", NULL, &clk_pxa25x_ssp),
+	CLKDEV_INIT("pxa25x-nssp.1", NULL, &clk_pxa25x_nssp),
+	CLKDEV_INIT("pxa25x-nssp.2", NULL, &clk_pxa25x_assp),
+	CLKDEV_INIT("pxa25x-pwm.0", NULL, &clk_pxa25x_pwm0),
+	CLKDEV_INIT("pxa25x-pwm.1", NULL, &clk_pxa25x_pwm1),
+	CLKDEV_INIT("pxa2xx-i2s", NULL, &clk_pxa25x_i2s),
+	CLKDEV_INIT("pxa2xx-ir", "UARTCLK", &clk_pxa25x_stuart),
+	CLKDEV_INIT("pxa2xx-ir", "FICPCLK", &clk_pxa25x_ficp),
+	CLKDEV_INIT(NULL, "AC97CLK", &clk_pxa25x_ac97),
+	CLKDEV_INIT(NULL, "GPIO11_CLK", &clk_pxa25x_gpio11),
+	CLKDEV_INIT(NULL, "GPIO12_CLK", &clk_pxa25x_gpio12),
+	CLKDEV_INIT("pxa2xx-pcmcia", NULL, &clk_pxa25x_mem),
+	CLKDEV_INIT("pxa-gpio", NULL, &clk_dummy),
 };
 
 static struct clk_lookup pxa25x_hwuart_clkreg =
-	INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
+	CLKDEV_INIT("pxa2xx-uart.3", NULL, &clk_pxa25x_hwuart);
 
 #ifdef CONFIG_PM
 
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 6bce78e..2ece3e2 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -202,34 +202,34 @@ static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
 static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
 
 static struct clk_lookup pxa27x_clkregs[] = {
-	INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
-	INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
-	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
-	INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
-	INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
-	INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
-	INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
-	INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
-	INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
-	INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
-	INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
-	INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
-	INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
-	INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
-	INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
-	INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
-	INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
-	INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
-	INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
-	INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
-	INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
-	INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
-	INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+	CLKDEV_INIT("pxa2xx-fb", NULL, &clk_pxa27x_lcd),
+	CLKDEV_INIT("pxa27x-camera.0", NULL, &clk_pxa27x_camera),
+	CLKDEV_INIT("pxa2xx-uart.0", NULL, &clk_pxa27x_ffuart),
+	CLKDEV_INIT("pxa2xx-uart.1", NULL, &clk_pxa27x_btuart),
+	CLKDEV_INIT("pxa2xx-uart.2", NULL, &clk_pxa27x_stuart),
+	CLKDEV_INIT("pxa2xx-i2s", NULL, &clk_pxa27x_i2s),
+	CLKDEV_INIT("pxa2xx-i2c.0", NULL, &clk_pxa27x_i2c),
+	CLKDEV_INIT("pxa27x-udc", NULL, &clk_pxa27x_usb),
+	CLKDEV_INIT("pxa2xx-mci.0", NULL, &clk_pxa27x_mmc),
+	CLKDEV_INIT("pxa2xx-ir", "UARTCLK", &clk_pxa27x_stuart),
+	CLKDEV_INIT("pxa2xx-ir", "FICPCLK", &clk_pxa27x_ficp),
+	CLKDEV_INIT("pxa27x-ohci", NULL, &clk_pxa27x_usbhost),
+	CLKDEV_INIT("pxa2xx-i2c.1", NULL, &clk_pxa27x_pwri2c),
+	CLKDEV_INIT("pxa27x-keypad", NULL, &clk_pxa27x_keypad),
+	CLKDEV_INIT("pxa27x-ssp.0", NULL, &clk_pxa27x_ssp1),
+	CLKDEV_INIT("pxa27x-ssp.1", NULL, &clk_pxa27x_ssp2),
+	CLKDEV_INIT("pxa27x-ssp.2", NULL, &clk_pxa27x_ssp3),
+	CLKDEV_INIT("pxa27x-pwm.0", NULL, &clk_pxa27x_pwm0),
+	CLKDEV_INIT("pxa27x-pwm.1", NULL, &clk_pxa27x_pwm1),
+	CLKDEV_INIT(NULL, "AC97CLK", &clk_pxa27x_ac97),
+	CLKDEV_INIT(NULL, "AC97CONFCLK", &clk_pxa27x_ac97conf),
+	CLKDEV_INIT(NULL, "MSLCLK", &clk_pxa27x_msl),
+	CLKDEV_INIT(NULL, "USIMCLK", &clk_pxa27x_usim),
+	CLKDEV_INIT(NULL, "MSTKCLK", &clk_pxa27x_memstk),
+	CLKDEV_INIT(NULL, "IMCLK", &clk_pxa27x_im),
+	CLKDEV_INIT(NULL, "MEMCLK", &clk_pxa27x_memc),
+	CLKDEV_INIT("pxa2xx-pcmcia", NULL, &clk_pxa27x_mem),
+	CLKDEV_INIT("pxa-gpio", NULL, &clk_dummy),
 };
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 40bb165..0cdab8c 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -87,14 +87,14 @@ static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0);
 static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0);
 
 static struct clk_lookup common_clkregs[] = {
-	INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
-	INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
+	CLKDEV_INIT("pxa3xx-nand", NULL, &clk_common_nand),
+	CLKDEV_INIT("pxa3xx-gcu", NULL, &clk_gcu),
 };
 
 static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
 
 static struct clk_lookup pxa310_clkregs[] = {
-	INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", NULL),
+	CLKDEV_INIT("pxa2xx-mci.2", NULL, &clk_pxa310_mmc3),
 };
 
 static int __init pxa300_init(void)
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index 8d614ec..994e991 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -81,8 +81,8 @@ static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0);
 static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0);
 
 static struct clk_lookup pxa320_clkregs[] = {
-	INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
-	INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
+	CLKDEV_INIT("pxa3xx-nand", NULL, &clk_pxa320_nand),
+	CLKDEV_INIT("pxa3xx-gcu", NULL, &clk_gcu),
 };
 
 static int __init pxa320_init(void)
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 3918a67..25a093e 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -64,31 +64,31 @@ static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
 
 static struct clk_lookup pxa3xx_clkregs[] = {
-	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
+	CLKDEV_INIT(NULL, "CLK_POUT", &clk_pxa3xx_pout),
 	/* Power I2C clock is always on */
-	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
-	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
-	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
-	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
-	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
-	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
-	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
-	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
-	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
-	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
-	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
-	INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
-	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
-	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
-	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
-	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
-	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
-	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
-	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
-	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
-	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
-	INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
-	INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
+	CLKDEV_INIT("pxa3xx-pwri2c.1", NULL, &clk_dummy),
+	CLKDEV_INIT("pxa2xx-fb", NULL, &clk_pxa3xx_lcd),
+	CLKDEV_INIT(NULL, "CAMCLK", &clk_pxa3xx_camera),
+	CLKDEV_INIT(NULL, "AC97CLK", &clk_pxa3xx_ac97),
+	CLKDEV_INIT("pxa2xx-uart.0", NULL, &clk_pxa3xx_ffuart),
+	CLKDEV_INIT("pxa2xx-uart.1", NULL, &clk_pxa3xx_btuart),
+	CLKDEV_INIT("pxa2xx-uart.2", NULL, &clk_pxa3xx_stuart),
+	CLKDEV_INIT("pxa2xx-ir", "UARTCLK", &clk_pxa3xx_stuart),
+	CLKDEV_INIT("pxa2xx-i2c.0", NULL, &clk_pxa3xx_i2c),
+	CLKDEV_INIT("pxa27x-udc", NULL, &clk_pxa3xx_udc),
+	CLKDEV_INIT("pxa27x-ohci", NULL, &clk_pxa3xx_usbh),
+	CLKDEV_INIT("pxa3xx-u2d", NULL, &clk_pxa3xx_u2d),
+	CLKDEV_INIT("pxa27x-keypad", NULL, &clk_pxa3xx_keypad),
+	CLKDEV_INIT("pxa27x-ssp.0", NULL, &clk_pxa3xx_ssp1),
+	CLKDEV_INIT("pxa27x-ssp.1", NULL, &clk_pxa3xx_ssp2),
+	CLKDEV_INIT("pxa27x-ssp.2", NULL, &clk_pxa3xx_ssp3),
+	CLKDEV_INIT("pxa27x-ssp.3", NULL, &clk_pxa3xx_ssp4),
+	CLKDEV_INIT("pxa27x-pwm.0", NULL, &clk_pxa3xx_pwm0),
+	CLKDEV_INIT("pxa27x-pwm.1", NULL, &clk_pxa3xx_pwm1),
+	CLKDEV_INIT("pxa2xx-mci.0", NULL, &clk_pxa3xx_mmc1),
+	CLKDEV_INIT("pxa2xx-mci.1", NULL, &clk_pxa3xx_mmc2),
+	CLKDEV_INIT("pxa2xx-pcmcia", NULL, &clk_pxa3xx_smemc),
+	CLKDEV_INIT("pxa-gpio", NULL, &clk_pxa3xx_gpio),
 };
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
index 5ce434b..2b29a45 100644
--- a/arch/arm/mach-pxa/pxa95x.c
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -214,23 +214,23 @@ static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa95x_gpio, GPIO, 13000000, 0);
 
 static struct clk_lookup pxa95x_clkregs[] = {
-	INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
+	CLKDEV_INIT(NULL, "CLK_POUT", &clk_pxa95x_pout),
 	/* Power I2C clock is always on */
-	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
-	INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
-	INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
-	INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
-	INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-uart.2", NULL),
-	INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-ir", "UARTCLK"),
-	INIT_CLKREG(&clk_pxa95x_i2c, "pxa2xx-i2c.0", NULL),
-	INIT_CLKREG(&clk_pxa95x_keypad, "pxa27x-keypad", NULL),
-	INIT_CLKREG(&clk_pxa95x_ssp1, "pxa27x-ssp.0", NULL),
-	INIT_CLKREG(&clk_pxa95x_ssp2, "pxa27x-ssp.1", NULL),
-	INIT_CLKREG(&clk_pxa95x_ssp3, "pxa27x-ssp.2", NULL),
-	INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL),
-	INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL),
-	INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
-	INIT_CLKREG(&clk_pxa95x_gpio, "pxa-gpio", NULL),
+	CLKDEV_INIT("pxa3xx-pwri2c.1", NULL, &clk_dummy),
+	CLKDEV_INIT("pxa2xx-fb", NULL, &clk_pxa95x_lcd),
+	CLKDEV_INIT("pxa2xx-uart.0", NULL, &clk_pxa95x_ffuart),
+	CLKDEV_INIT("pxa2xx-uart.1", NULL, &clk_pxa95x_btuart),
+	CLKDEV_INIT("pxa2xx-uart.2", NULL, &clk_pxa95x_stuart),
+	CLKDEV_INIT("pxa2xx-ir", "UARTCLK", &clk_pxa95x_stuart),
+	CLKDEV_INIT("pxa2xx-i2c.0", NULL, &clk_pxa95x_i2c),
+	CLKDEV_INIT("pxa27x-keypad", NULL, &clk_pxa95x_keypad),
+	CLKDEV_INIT("pxa27x-ssp.0", NULL, &clk_pxa95x_ssp1),
+	CLKDEV_INIT("pxa27x-ssp.1", NULL, &clk_pxa95x_ssp2),
+	CLKDEV_INIT("pxa27x-ssp.2", NULL, &clk_pxa95x_ssp3),
+	CLKDEV_INIT("pxa27x-ssp.3", NULL, &clk_pxa95x_ssp4),
+	CLKDEV_INIT("pxa27x-pwm.0", NULL, &clk_pxa95x_pwm0),
+	CLKDEV_INIT("pxa27x-pwm.1", NULL, &clk_pxa95x_pwm1),
+	CLKDEV_INIT("pxa-gpio", NULL, &clk_pxa95x_gpio),
 };
 
 void __init pxa95x_init_irq(void)
-- 
1.7.9.1




From philipp.zabel at gmail.com  Fri Mar 16 13:36:54 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Fri, 16 Mar 2012 18:36:54 +0100
Subject: [RFC/PATCH 2/4] pxa2xx: move clkops definitions into a separate
 object file
Message-ID: <1331919414.31118.21.camel@flow>

This avoids the layering violation discussed in Documentation/clk.txt:
static clock definitions and clk_ops implementations have to reside
in separate files.

An alternative would be to move the static clock definitions out of
pxa*.c, but given that there are already clock-pxa2xx.c and clock-pxa3xx.c,
this seems like the more logical choice.

Signed-off-by: Philipp Zabel <philipp.zabel at gmail.com>
---
 arch/arm/mach-pxa/Makefile       |    4 +-
 arch/arm/mach-pxa/clock-pxa25x.c |  133 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-pxa/clock-pxa27x.c |  123 +++++++++++++++++++++++++++++++++++
 arch/arm/mach-pxa/clock.h        |    8 ++
 arch/arm/mach-pxa/pxa25x.c       |  118 ---------------------------------
 arch/arm/mach-pxa/pxa27x.c       |  108 ------------------------------
 6 files changed, 266 insertions(+), 228 deletions(-)
 create mode 100644 arch/arm/mach-pxa/clock-pxa25x.c
 create mode 100644 arch/arm/mach-pxa/clock-pxa27x.c

diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index be0f7df..0a1fc28 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -16,8 +16,8 @@ endif
 # Generic drivers that other drivers may depend upon
 
 # SoC-specific code
-obj-$(CONFIG_PXA25x)		+= mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
-obj-$(CONFIG_PXA27x)		+= mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
+obj-$(CONFIG_PXA25x)		+= mfp-pxa2xx.o clock-pxa2xx.o clock-pxa25x.o pxa2xx.o pxa25x.o
+obj-$(CONFIG_PXA27x)		+= mfp-pxa2xx.o clock-pxa2xx.o clock-pxa27x.o pxa2xx.o pxa27x.o
 obj-$(CONFIG_PXA3xx)		+= mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
 obj-$(CONFIG_PXA95x)		+= mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o pxa95x.o smemc.o
 obj-$(CONFIG_CPU_PXA300)	+= pxa300.o
diff --git a/arch/arm/mach-pxa/clock-pxa25x.c b/arch/arm/mach-pxa/clock-pxa25x.c
new file mode 100644
index 0000000..d6f525c
--- /dev/null
+++ b/arch/arm/mach-pxa/clock-pxa25x.c
@@ -0,0 +1,133 @@
+/*
+ * linux/arch/arm/mach-pxa/clock-pxa25x.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+
+#include <mach/pxa2xx-regs.h>
+
+#include "clock.h"
+
+/*
+ * Various clock factors driven by the CCCR register.
+ */
+
+/* Crystal Frequency to Memory Frequency Multiplier (L) */
+static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
+
+/* Memory Frequency to Run Mode Frequency Multiplier (M) */
+static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
+
+/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
+/* Note: we store the value N * 2 here. */
+static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
+
+/* Crystal clock */
+#define BASE_CLK	3686400
+
+/*
+ * Get the clock frequency as reflected by CCCR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
+ */
+unsigned int pxa25x_get_clk_frequency_khz(int info)
+{
+	unsigned long cccr, turbo;
+	unsigned int l, L, m, M, n2, N;
+
+	cccr = CCCR;
+	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
+
+	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
+	m  =  M_clk_mult[(cccr >> 5) & 0x03];
+	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
+
+	L = l * BASE_CLK;
+	M = m * L;
+	N = n2 * M / 2;
+
+	if(info)
+	{
+		L += 5000;
+		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
+			L / 1000000, (L % 1000000) / 10000, l );
+		M += 5000;
+		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
+			M / 1000000, (M % 1000000) / 10000, m );
+		N += 5000;
+		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
+			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
+			(turbo & 1) ? "" : "in" );
+	}
+
+	return (turbo & 1) ? (N/1000) : (M/1000);
+}
+
+static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
+{
+	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
+}
+
+const struct clkops clk_pxa25x_mem_ops = {
+	.enable		= clk_dummy_enable,
+	.disable	= clk_dummy_disable,
+	.getrate	= clk_pxa25x_mem_getrate,
+};
+
+const struct clkops clk_pxa25x_lcd_ops = {
+	.enable		= clk_pxa2xx_cken_enable,
+	.disable	= clk_pxa2xx_cken_disable,
+	.getrate	= clk_pxa25x_mem_getrate,
+};
+
+static unsigned long gpio12_config_32k[] = {
+	GPIO12_32KHz,
+};
+
+static unsigned long gpio12_config_gpio[] = {
+	GPIO12_GPIO,
+};
+
+static void clk_gpio12_enable(struct clk *clk)
+{
+	pxa2xx_mfp_config(gpio12_config_32k, 1);
+}
+
+static void clk_gpio12_disable(struct clk *clk)
+{
+	pxa2xx_mfp_config(gpio12_config_gpio, 1);
+}
+
+const struct clkops clk_pxa25x_gpio12_ops = {
+	.enable         = clk_gpio12_enable,
+	.disable        = clk_gpio12_disable,
+};
+
+static unsigned long gpio11_config_3m6[] = {
+	GPIO11_3_6MHz,
+};
+
+static unsigned long gpio11_config_gpio[] = {
+	GPIO11_GPIO,
+};
+
+static void clk_gpio11_enable(struct clk *clk)
+{
+	pxa2xx_mfp_config(gpio11_config_3m6, 1);
+}
+
+static void clk_gpio11_disable(struct clk *clk)
+{
+	pxa2xx_mfp_config(gpio11_config_gpio, 1);
+}
+
+const struct clkops clk_pxa25x_gpio11_ops = {
+	.enable         = clk_gpio11_enable,
+	.disable        = clk_gpio11_disable,
+};
+
diff --git a/arch/arm/mach-pxa/clock-pxa27x.c b/arch/arm/mach-pxa/clock-pxa27x.c
new file mode 100644
index 0000000..dd97c6d
--- /dev/null
+++ b/arch/arm/mach-pxa/clock-pxa27x.c
@@ -0,0 +1,123 @@
+/*
+ * linux/arch/arm/mach-pxa/clock-pxa27x.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+
+#include <mach/pxa2xx-regs.h>
+
+#include "clock.h"
+
+/* Crystal clock: 13MHz */
+#define BASE_CLK	13000000
+
+/*
+ * Get the clock frequency as reflected by CCSR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
+ */
+unsigned int pxa27x_get_clk_frequency_khz(int info)
+{
+	unsigned long ccsr, clkcfg;
+	unsigned int l, L, m, M, n2, N, S;
+	int cccr_a, t, ht, b;
+
+	ccsr = CCSR;
+	cccr_a = CCCR & (1 << 25);
+
+	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
+	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
+	t  = clkcfg & (1 << 0);
+	ht = clkcfg & (1 << 2);
+	b  = clkcfg & (1 << 3);
+
+	l  = ccsr & 0x1f;
+	n2 = (ccsr>>7) & 0xf;
+	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
+
+	L  = l * BASE_CLK;
+	N  = (L * n2) / 2;
+	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
+	S  = (b) ? L : (L/2);
+
+	if (info) {
+		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
+			L / 1000000, (L % 1000000) / 10000, l );
+		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
+			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
+			(t) ? "" : "in" );
+		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
+			M / 1000000, (M % 1000000) / 10000, m );
+		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
+			S / 1000000, (S % 1000000) / 10000 );
+	}
+
+	return (t) ? (N/1000) : (L/1000);
+}
+
+/*
+ * Return the current mem clock frequency as reflected by CCCR[A], B, and L
+ */
+static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
+{
+	unsigned long ccsr, clkcfg;
+	unsigned int l, L, m, M;
+	int cccr_a, b;
+
+	ccsr = CCSR;
+	cccr_a = CCCR & (1 << 25);
+
+	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
+	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
+	b = clkcfg & (1 << 3);
+
+	l = ccsr & 0x1f;
+	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
+
+	L = l * BASE_CLK;
+	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
+
+	return M;
+}
+
+const struct clkops clk_pxa27x_mem_ops = {
+	.enable		= clk_dummy_enable,
+	.disable	= clk_dummy_disable,
+	.getrate	= clk_pxa27x_mem_getrate,
+};
+
+/*
+ * Return the current LCD clock frequency in units of 10kHz as
+ */
+static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
+{
+	unsigned long ccsr;
+	unsigned int l, L, k, K;
+
+	ccsr = CCSR;
+
+	l = ccsr & 0x1f;
+	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
+
+	L = l * BASE_CLK;
+	K = L / k;
+
+	return (K / 10000);
+}
+
+static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
+{
+	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
+}
+
+const struct clkops clk_pxa27x_lcd_ops = {
+	.enable		= clk_pxa2xx_cken_enable,
+	.disable	= clk_pxa2xx_cken_disable,
+	.getrate	= clk_pxa27x_lcd_getrate,
+};
+
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 2946fa2..a3585a2 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -45,6 +45,14 @@ struct clk clk_##_name = {				\
 
 extern const struct clkops clk_pxa2xx_cken_ops;
 
+extern const struct clkops clk_pxa25x_mem_ops;
+extern const struct clkops clk_pxa25x_lcd_ops;
+extern const struct clkops clk_pxa25x_gpio12_ops;
+extern const struct clkops clk_pxa25x_gpio11_ops;
+
+extern const struct clkops clk_pxa27x_mem_ops;
+extern const struct clkops clk_pxa27x_lcd_ops;
+
 void clk_pxa2xx_cken_enable(struct clk *clk);
 void clk_pxa2xx_cken_disable(struct clk *clk);
 
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 99dd55e..2c2eb41 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -41,124 +41,6 @@
 #include "clock.h"
 
 /*
- * Various clock factors driven by the CCCR register.
- */
-
-/* Crystal Frequency to Memory Frequency Multiplier (L) */
-static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
-
-/* Memory Frequency to Run Mode Frequency Multiplier (M) */
-static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
-
-/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
-/* Note: we store the value N * 2 here. */
-static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
-
-/* Crystal clock */
-#define BASE_CLK	3686400
-
-/*
- * Get the clock frequency as reflected by CCCR and the turbo flag.
- * We assume these values have been applied via a fcs.
- * If info is not 0 we also display the current settings.
- */
-unsigned int pxa25x_get_clk_frequency_khz(int info)
-{
-	unsigned long cccr, turbo;
-	unsigned int l, L, m, M, n2, N;
-
-	cccr = CCCR;
-	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
-
-	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
-	m  =  M_clk_mult[(cccr >> 5) & 0x03];
-	n2 = N2_clk_mult[(cccr >> 7) & 0x07];
-
-	L = l * BASE_CLK;
-	M = m * L;
-	N = n2 * M / 2;
-
-	if(info)
-	{
-		L += 5000;
-		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
-			L / 1000000, (L % 1000000) / 10000, l );
-		M += 5000;
-		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
-			M / 1000000, (M % 1000000) / 10000, m );
-		N += 5000;
-		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
-			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
-			(turbo & 1) ? "" : "in" );
-	}
-
-	return (turbo & 1) ? (N/1000) : (M/1000);
-}
-
-static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
-{
-	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
-}
-
-static const struct clkops clk_pxa25x_mem_ops = {
-	.enable		= clk_dummy_enable,
-	.disable	= clk_dummy_disable,
-	.getrate	= clk_pxa25x_mem_getrate,
-};
-
-static const struct clkops clk_pxa25x_lcd_ops = {
-	.enable		= clk_pxa2xx_cken_enable,
-	.disable	= clk_pxa2xx_cken_disable,
-	.getrate	= clk_pxa25x_mem_getrate,
-};
-
-static unsigned long gpio12_config_32k[] = {
-	GPIO12_32KHz,
-};
-
-static unsigned long gpio12_config_gpio[] = {
-	GPIO12_GPIO,
-};
-
-static void clk_gpio12_enable(struct clk *clk)
-{
-	pxa2xx_mfp_config(gpio12_config_32k, 1);
-}
-
-static void clk_gpio12_disable(struct clk *clk)
-{
-	pxa2xx_mfp_config(gpio12_config_gpio, 1);
-}
-
-static const struct clkops clk_pxa25x_gpio12_ops = {
-	.enable         = clk_gpio12_enable,
-	.disable        = clk_gpio12_disable,
-};
-
-static unsigned long gpio11_config_3m6[] = {
-	GPIO11_3_6MHz,
-};
-
-static unsigned long gpio11_config_gpio[] = {
-	GPIO11_GPIO,
-};
-
-static void clk_gpio11_enable(struct clk *clk)
-{
-	pxa2xx_mfp_config(gpio11_config_3m6, 1);
-}
-
-static void clk_gpio11_disable(struct clk *clk)
-{
-	pxa2xx_mfp_config(gpio11_config_gpio, 1);
-}
-
-static const struct clkops clk_pxa25x_gpio11_ops = {
-	.enable         = clk_gpio11_enable,
-	.disable        = clk_gpio11_disable,
-};
-
-/*
  * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
  * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
  * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 2ece3e2..b9dc6ac 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -65,114 +65,6 @@ void pxa27x_assert_ac97reset(int reset_gpio, int on)
 }
 EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
 
-/* Crystal clock: 13MHz */
-#define BASE_CLK	13000000
-
-/*
- * Get the clock frequency as reflected by CCSR and the turbo flag.
- * We assume these values have been applied via a fcs.
- * If info is not 0 we also display the current settings.
- */
-unsigned int pxa27x_get_clk_frequency_khz(int info)
-{
-	unsigned long ccsr, clkcfg;
-	unsigned int l, L, m, M, n2, N, S;
-       	int cccr_a, t, ht, b;
-
-	ccsr = CCSR;
-	cccr_a = CCCR & (1 << 25);
-
-	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
-	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
-	t  = clkcfg & (1 << 0);
-	ht = clkcfg & (1 << 2);
-	b  = clkcfg & (1 << 3);
-
-	l  = ccsr & 0x1f;
-	n2 = (ccsr>>7) & 0xf;
-	m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
-
-	L  = l * BASE_CLK;
-	N  = (L * n2) / 2;
-	M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
-	S  = (b) ? L : (L/2);
-
-	if (info) {
-		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
-			L / 1000000, (L % 1000000) / 10000, l );
-		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
-			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
-			(t) ? "" : "in" );
-		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
-			M / 1000000, (M % 1000000) / 10000, m );
-		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
-			S / 1000000, (S % 1000000) / 10000 );
-	}
-
-	return (t) ? (N/1000) : (L/1000);
-}
-
-/*
- * Return the current mem clock frequency as reflected by CCCR[A], B, and L
- */
-static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
-{
-	unsigned long ccsr, clkcfg;
-	unsigned int l, L, m, M;
-       	int cccr_a, b;
-
-	ccsr = CCSR;
-	cccr_a = CCCR & (1 << 25);
-
-	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
-	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
-	b = clkcfg & (1 << 3);
-
-	l = ccsr & 0x1f;
-	m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
-
-	L = l * BASE_CLK;
-	M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
-
-	return M;
-}
-
-static const struct clkops clk_pxa27x_mem_ops = {
-	.enable		= clk_dummy_enable,
-	.disable	= clk_dummy_disable,
-	.getrate	= clk_pxa27x_mem_getrate,
-};
-
-/*
- * Return the current LCD clock frequency in units of 10kHz as
- */
-static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
-{
-	unsigned long ccsr;
-	unsigned int l, L, k, K;
-
-	ccsr = CCSR;
-
-	l = ccsr & 0x1f;
-	k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
-
-	L = l * BASE_CLK;
-	K = L / k;
-
-	return (K / 10000);
-}
-
-static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
-{
-	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
-}
-
-static const struct clkops clk_pxa27x_lcd_ops = {
-	.enable		= clk_pxa2xx_cken_enable,
-	.disable	= clk_pxa2xx_cken_disable,
-	.getrate	= clk_pxa27x_lcd_getrate,
-};
-
 static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
 static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
 static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
-- 
1.7.9.1




From philipp.zabel at gmail.com  Fri Mar 16 13:37:23 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Fri, 16 Mar 2012 18:37:23 +0100
Subject: [RFC/PATCH 3/4] pxa2xx: checkpatch fixes for clock-pxa25x.c and
 clock-pxa27x.c
Message-ID: <1331919443.31118.22.camel@flow>

checkpatch.pl loudly complains about the previous patch. So we could use
the opportunity and squash this patch into it to address style issues.

Signed-off-by: Philipp Zabel <philipp.zabel at gmail.com>
---
 arch/arm/mach-pxa/clock-pxa25x.c |   19 +++++++++----------
 arch/arm/mach-pxa/clock-pxa27x.c |   24 ++++++++++++------------
 2 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-pxa/clock-pxa25x.c b/arch/arm/mach-pxa/clock-pxa25x.c
index d6f525c..53fd568 100644
--- a/arch/arm/mach-pxa/clock-pxa25x.c
+++ b/arch/arm/mach-pxa/clock-pxa25x.c
@@ -41,7 +41,7 @@ unsigned int pxa25x_get_clk_frequency_khz(int info)
 	unsigned int l, L, m, M, n2, N;
 
 	cccr = CCCR;
-	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
+	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo));
 
 	l  =  L_clk_mult[(cccr >> 0) & 0x1f];
 	m  =  M_clk_mult[(cccr >> 5) & 0x03];
@@ -51,18 +51,17 @@ unsigned int pxa25x_get_clk_frequency_khz(int info)
 	M = m * L;
 	N = n2 * M / 2;
 
-	if(info)
-	{
+	if (info) {
 		L += 5000;
-		printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
-			L / 1000000, (L % 1000000) / 10000, l );
+		pr_info("Memory clock: %d.%02dMHz (*%d)\n",
+			L / 1000000, (L % 1000000) / 10000, l);
 		M += 5000;
-		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
-			M / 1000000, (M % 1000000) / 10000, m );
+		pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
+			M / 1000000, (M % 1000000) / 10000, m);
 		N += 5000;
-		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
-			N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
-			(turbo & 1) ? "" : "in" );
+		pr_info("Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
+			N / 1000000, (N % 1000000) / 10000, n2 / 2,
+			(n2 % 2) * 5, (turbo & 1) ? "" : "in");
 	}
 
 	return (turbo & 1) ? (N/1000) : (M/1000);
diff --git a/arch/arm/mach-pxa/clock-pxa27x.c b/arch/arm/mach-pxa/clock-pxa27x.c
index dd97c6d..734864d 100644
--- a/arch/arm/mach-pxa/clock-pxa27x.c
+++ b/arch/arm/mach-pxa/clock-pxa27x.c
@@ -31,7 +31,7 @@ unsigned int pxa27x_get_clk_frequency_khz(int info)
 	cccr_a = CCCR & (1 << 25);
 
 	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
-	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
+	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
 	t  = clkcfg & (1 << 0);
 	ht = clkcfg & (1 << 2);
 	b  = clkcfg & (1 << 3);
@@ -46,15 +46,15 @@ unsigned int pxa27x_get_clk_frequency_khz(int info)
 	S  = (b) ? L : (L/2);
 
 	if (info) {
-		printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
-			L / 1000000, (L % 1000000) / 10000, l );
-		printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
-			N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
-			(t) ? "" : "in" );
-		printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
-			M / 1000000, (M % 1000000) / 10000, m );
-		printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
-			S / 1000000, (S % 1000000) / 10000 );
+		pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
+			L / 1000000, (L % 1000000) / 10000, l);
+		pr_info("Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
+			N / 1000000, (N % 1000000) / 10000, n2 / 2,
+			(n2 % 2) * 5, (t) ? "" : "in");
+		pr_info("Memory clock: %d.%02dMHz (/%d)\n",
+			M / 1000000, (M % 1000000) / 10000, m);
+		pr_info("System bus clock: %d.%02dMHz\n",
+			S / 1000000, (S % 1000000) / 10000);
 	}
 
 	return (t) ? (N/1000) : (L/1000);
@@ -73,7 +73,7 @@ static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
 	cccr_a = CCCR & (1 << 25);
 
 	/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
-	asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
+	asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
 	b = clkcfg & (1 << 3);
 
 	l = ccsr & 0x1f;
@@ -107,7 +107,7 @@ static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
 	L = l * BASE_CLK;
 	K = L / k;
 
-	return (K / 10000);
+	return K / 10000;
 }
 
 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
-- 
1.7.9.1




From philipp.zabel at gmail.com  Fri Mar 16 13:38:03 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Fri, 16 Mar 2012 18:38:03 +0100
Subject: [RFC/PATCH 4/4] pxa: convert to common clock framework
Message-ID: <1331919483.31118.23.camel@flow>

This patch:
* moves the PXA-specific delay out of clk_enable into callbacks,
* removes the custom clk API functions which are now provided
  by the common clk framework,
* converts from struct clkops to struct clk_ops,
* removes the dummy clock enable/disable functions,
* changes clock definition macros to define the cross-linked
  struct clk / struct clk_pxa pair, and
* initializes the statically defined clocks with __clk_init

Signed-off-by: Philipp Zabel <philipp.zabel at gmail.com>
---
 arch/arm/Kconfig                 |    1 +
 arch/arm/mach-pxa/clock-pxa25x.c |   30 ++++++-----
 arch/arm/mach-pxa/clock-pxa27x.c |   16 +++---
 arch/arm/mach-pxa/clock-pxa2xx.c |   26 ++++++++-
 arch/arm/mach-pxa/clock-pxa3xx.c |   49 ++++++++++++-----
 arch/arm/mach-pxa/clock.c        |   76 +-------------------------
 arch/arm/mach-pxa/clock.h        |  108 +++++++++++++++++++++++--------------
 arch/arm/mach-pxa/eseries.c      |   11 +----
 arch/arm/mach-pxa/pxa25x.c       |   22 ++++++++
 arch/arm/mach-pxa/pxa27x.c       |   30 +++++++++++
 arch/arm/mach-pxa/pxa3xx.c       |   26 +++++++++
 11 files changed, 232 insertions(+), 163 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3cc5897..ab46c97 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -684,6 +684,7 @@ config ARCH_PXA
 	select ARCH_HAS_CPUFREQ
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
+	select COMMON_CLK
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select GPIO_PXA
diff --git a/arch/arm/mach-pxa/clock-pxa25x.c b/arch/arm/mach-pxa/clock-pxa25x.c
index 53fd568..de2a2e7 100644
--- a/arch/arm/mach-pxa/clock-pxa25x.c
+++ b/arch/arm/mach-pxa/clock-pxa25x.c
@@ -9,6 +9,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 
+#include <mach/mfp-pxa25x.h>
 #include <mach/pxa2xx-regs.h>
 
 #include "clock.h"
@@ -67,21 +68,20 @@ unsigned int pxa25x_get_clk_frequency_khz(int info)
 	return (turbo & 1) ? (N/1000) : (M/1000);
 }
 
-static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
+static unsigned long clk_pxa25x_mem_recalc_rate(struct clk_hw *hw,
+						unsigned long parent_rate)
 {
 	return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
 }
 
-const struct clkops clk_pxa25x_mem_ops = {
-	.enable		= clk_dummy_enable,
-	.disable	= clk_dummy_disable,
-	.getrate	= clk_pxa25x_mem_getrate,
+const struct clk_ops clk_pxa25x_mem_ops = {
+	.recalc_rate	= clk_pxa25x_mem_recalc_rate,
 };
 
-const struct clkops clk_pxa25x_lcd_ops = {
+const struct clk_ops clk_pxa25x_lcd_ops = {
 	.enable		= clk_pxa2xx_cken_enable,
 	.disable	= clk_pxa2xx_cken_disable,
-	.getrate	= clk_pxa25x_mem_getrate,
+	.recalc_rate	= clk_pxa25x_mem_recalc_rate,
 };
 
 static unsigned long gpio12_config_32k[] = {
@@ -92,17 +92,19 @@ static unsigned long gpio12_config_gpio[] = {
 	GPIO12_GPIO,
 };
 
-static void clk_gpio12_enable(struct clk *clk)
+static int clk_gpio12_enable(struct clk_hw *hw)
 {
 	pxa2xx_mfp_config(gpio12_config_32k, 1);
+
+	return 0;
 }
 
-static void clk_gpio12_disable(struct clk *clk)
+static void clk_gpio12_disable(struct clk_hw *hw)
 {
 	pxa2xx_mfp_config(gpio12_config_gpio, 1);
 }
 
-const struct clkops clk_pxa25x_gpio12_ops = {
+const struct clk_ops clk_pxa25x_gpio12_ops = {
 	.enable         = clk_gpio12_enable,
 	.disable        = clk_gpio12_disable,
 };
@@ -115,17 +117,19 @@ static unsigned long gpio11_config_gpio[] = {
 	GPIO11_GPIO,
 };
 
-static void clk_gpio11_enable(struct clk *clk)
+static int clk_gpio11_enable(struct clk_hw *hw)
 {
 	pxa2xx_mfp_config(gpio11_config_3m6, 1);
+
+	return 0;
 }
 
-static void clk_gpio11_disable(struct clk *clk)
+static void clk_gpio11_disable(struct clk_hw *hw)
 {
 	pxa2xx_mfp_config(gpio11_config_gpio, 1);
 }
 
-const struct clkops clk_pxa25x_gpio11_ops = {
+const struct clk_ops clk_pxa25x_gpio11_ops = {
 	.enable         = clk_gpio11_enable,
 	.disable        = clk_gpio11_disable,
 };
diff --git a/arch/arm/mach-pxa/clock-pxa27x.c b/arch/arm/mach-pxa/clock-pxa27x.c
index 734864d..6b5ebba 100644
--- a/arch/arm/mach-pxa/clock-pxa27x.c
+++ b/arch/arm/mach-pxa/clock-pxa27x.c
@@ -63,7 +63,8 @@ unsigned int pxa27x_get_clk_frequency_khz(int info)
 /*
  * Return the current mem clock frequency as reflected by CCCR[A], B, and L
  */
-static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
+static unsigned long clk_pxa27x_mem_recalc_rate(struct clk_hw *hw,
+						unsigned long parent_rate)
 {
 	unsigned long ccsr, clkcfg;
 	unsigned int l, L, m, M;
@@ -85,10 +86,8 @@ static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
 	return M;
 }
 
-const struct clkops clk_pxa27x_mem_ops = {
-	.enable		= clk_dummy_enable,
-	.disable	= clk_dummy_disable,
-	.getrate	= clk_pxa27x_mem_getrate,
+const struct clk_ops clk_pxa27x_mem_ops = {
+	.recalc_rate	= clk_pxa27x_mem_recalc_rate,
 };
 
 /*
@@ -110,14 +109,15 @@ static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
 	return K / 10000;
 }
 
-static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
+static unsigned long clk_pxa27x_lcd_recalc_rate(struct clk_hw *hw,
+						unsigned long parent_rate)
 {
 	return pxa27x_get_lcdclk_frequency_10khz() * 10000;
 }
 
-const struct clkops clk_pxa27x_lcd_ops = {
+const struct clk_ops clk_pxa27x_lcd_ops = {
 	.enable		= clk_pxa2xx_cken_enable,
 	.disable	= clk_pxa2xx_cken_disable,
-	.getrate	= clk_pxa27x_lcd_getrate,
+	.recalc_rate	= clk_pxa27x_lcd_recalc_rate,
 };
 
diff --git a/arch/arm/mach-pxa/clock-pxa2xx.c b/arch/arm/mach-pxa/clock-pxa2xx.c
index 1d5859d..5ab5cb6 100644
--- a/arch/arm/mach-pxa/clock-pxa2xx.c
+++ b/arch/arm/mach-pxa/clock-pxa2xx.c
@@ -6,6 +6,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -15,19 +17,37 @@
 
 #include "clock.h"
 
-void clk_pxa2xx_cken_enable(struct clk *clk)
+int clk_pxa2xx_cken_enable(struct clk_hw *hw)
 {
+	struct clk_pxa *clk = to_clk_pxa(hw);
+
 	CKEN |= 1 << clk->cken;
+
+	if (clk->delay)
+		udelay(clk->delay);
+
+	return 0;
 }
 
-void clk_pxa2xx_cken_disable(struct clk *clk)
+void clk_pxa2xx_cken_disable(struct clk_hw *hw)
 {
+	struct clk_pxa *clk = to_clk_pxa(hw);
+
 	CKEN &= ~(1 << clk->cken);
 }
 
-const struct clkops clk_pxa2xx_cken_ops = {
+static unsigned long clk_pxa2xx_cken_recalc_rate(struct clk_hw *hw,
+						unsigned long parent_rate)
+{
+	struct clk_pxa *clk = to_clk_pxa(hw);
+
+	return clk->rate;
+}
+
+const struct clk_ops clk_pxa2xx_cken_ops = {
 	.enable		= clk_pxa2xx_cken_enable,
 	.disable	= clk_pxa2xx_cken_disable,
+	.recalc_rate	= clk_pxa2xx_cken_recalc_rate,
 };
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c
index 2a37a9a..93064b4 100644
--- a/arch/arm/mach-pxa/clock-pxa3xx.c
+++ b/arch/arm/mach-pxa/clock-pxa3xx.c
@@ -6,6 +6,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -76,7 +78,8 @@ unsigned int pxa3xx_get_clk_frequency_khz(int info)
 /*
  * Return the current AC97 clock frequency.
  */
-static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
+static unsigned long clk_pxa3xx_ac97_recalc_rate(struct clk_hw *hw,
+						unsigned long parent_rate)
 {
 	unsigned long rate = 312000000;
 	unsigned long ac97_div;
@@ -95,7 +98,8 @@ static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
 /*
  * Return the current HSIO bus clock frequency
  */
-static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
+static unsigned long clk_pxa3xx_hsio_recalc_rate(struct clk_hw *hw,
+						unsigned long parent_rate)
 {
 	unsigned long acsr;
 	unsigned int hss, hsio_clk;
@@ -112,7 +116,8 @@ static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
 static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
 static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
 
-static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
+static unsigned long clk_pxa3xx_smemc_recalc_rate(struct clk_hw *hw,
+						unsigned long parent_rate)
 {
 	unsigned long acsr = ACSR;
 	unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
@@ -121,18 +126,25 @@ static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
 			df_clkdiv[(memclkcfg >> 16) & 0x3];
 }
 
-void clk_pxa3xx_cken_enable(struct clk *clk)
+int clk_pxa3xx_cken_enable(struct clk_hw *hw)
 {
+	struct clk_pxa *clk = to_clk_pxa(hw);
 	unsigned long mask = 1ul << (clk->cken & 0x1f);
 
 	if (clk->cken < 32)
 		CKENA |= mask;
 	else
 		CKENB |= mask;
+
+	if (clk->delay)
+		udelay(clk->delay);
+
+	return 0;
 }
 
-void clk_pxa3xx_cken_disable(struct clk *clk)
+void clk_pxa3xx_cken_disable(struct clk_hw *hw)
 {
+	struct clk_pxa *clk = to_clk_pxa(hw);
 	unsigned long mask = 1ul << (clk->cken & 0x1f);
 
 	if (clk->cken < 32)
@@ -141,40 +153,47 @@ void clk_pxa3xx_cken_disable(struct clk *clk)
 		CKENB &= ~mask;
 }
 
-const struct clkops clk_pxa3xx_cken_ops = {
+const struct clk_ops clk_pxa3xx_cken_ops = {
 	.enable		= clk_pxa3xx_cken_enable,
 	.disable	= clk_pxa3xx_cken_disable,
 };
 
-const struct clkops clk_pxa3xx_hsio_ops = {
+const struct clk_ops clk_pxa3xx_hsio_ops = {
 	.enable		= clk_pxa3xx_cken_enable,
 	.disable	= clk_pxa3xx_cken_disable,
-	.getrate	= clk_pxa3xx_hsio_getrate,
+	.recalc_rate	= clk_pxa3xx_hsio_recalc_rate,
 };
 
-const struct clkops clk_pxa3xx_ac97_ops = {
+const struct clk_ops clk_pxa3xx_ac97_ops = {
 	.enable		= clk_pxa3xx_cken_enable,
 	.disable	= clk_pxa3xx_cken_disable,
-	.getrate	= clk_pxa3xx_ac97_getrate,
+	.recalc_rate	= clk_pxa3xx_ac97_recalc_rate,
 };
 
-const struct clkops clk_pxa3xx_smemc_ops = {
+const struct clk_ops clk_pxa3xx_smemc_ops = {
 	.enable		= clk_pxa3xx_cken_enable,
 	.disable	= clk_pxa3xx_cken_disable,
-	.getrate	= clk_pxa3xx_smemc_getrate,
+	.recalc_rate	= clk_pxa3xx_smemc_recalc_rate,
 };
 
-static void clk_pout_enable(struct clk *clk)
+static int clk_pout_enable(struct clk_hw *hw)
 {
+	struct clk_pxa *clk = to_clk_pxa(hw);
+
 	OSCC |= OSCC_PEN;
+
+	if (clk->delay)
+		udelay(clk->delay);
+
+	return 0;
 }
 
-static void clk_pout_disable(struct clk *clk)
+static void clk_pout_disable(struct clk_hw *hw)
 {
 	OSCC &= ~OSCC_PEN;
 }
 
-const struct clkops clk_pxa3xx_pout_ops = {
+const struct clk_ops clk_pxa3xx_pout_ops = {
 	.enable		= clk_pout_enable,
 	.disable	= clk_pout_disable,
 };
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index 4d46610..d5d5876 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -3,82 +3,12 @@
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/clk-private.h>
 
 #include "clock.h"
 
-static DEFINE_SPINLOCK(clocks_lock);
-
-int clk_enable(struct clk *clk)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&clocks_lock, flags);
-	if (clk->enabled++ == 0)
-		clk->ops->enable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
-
-	if (clk->delay)
-		udelay(clk->delay);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-	unsigned long flags;
-
-	WARN_ON(clk->enabled == 0);
-
-	spin_lock_irqsave(&clocks_lock, flags);
-	if (--clk->enabled == 0)
-		clk->ops->disable(clk);
-	spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	unsigned long rate;
-
-	rate = clk->rate;
-	if (clk->ops->getrate)
-		rate = clk->ops->getrate(clk);
-
-	return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned long flags;
-	int ret = -EINVAL;
-
-	if (clk->ops->setrate) {
-		spin_lock_irqsave(&clocks_lock, flags);
-		ret = clk->ops->setrate(clk, rate);
-		spin_unlock_irqrestore(&clocks_lock, flags);
-	}
-
-	return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-void clk_dummy_enable(struct clk *clk)
-{
-}
-
-void clk_dummy_disable(struct clk *clk)
-{
-}
-
-const struct clkops clk_dummy_ops = {
-	.enable		= clk_dummy_enable,
-	.disable	= clk_dummy_disable,
+const struct clk_ops clk_dummy_ops = {
 };
 
 struct clk clk_dummy = {
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index a3585a2..7c04f9b 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -1,80 +1,106 @@
 #include <linux/clkdev.h>
+#include <linux/clk-private.h>
+#include <linux/clk-provider.h>
 #include <linux/syscore_ops.h>
 
-struct clkops {
-	void			(*enable)(struct clk *);
-	void			(*disable)(struct clk *);
-	unsigned long		(*getrate)(struct clk *);
-	int			(*setrate)(struct clk *, unsigned long);
-};
+#define to_clk_pxa(_hw) container_of(_hw, struct clk_pxa, hw)
 
-struct clk {
-	const struct clkops	*ops;
-	unsigned long		rate;
+struct clk_pxa {
+	struct clk_hw		hw;
 	unsigned int		cken;
 	unsigned int		delay;
-	unsigned int		enabled;
+	unsigned long		rate;
 };
 
-void clk_dummy_enable(struct clk *);
-void clk_dummy_disable(struct clk *);
-
-extern const struct clkops clk_dummy_ops;
+extern const struct clk_ops clk_dummy_ops;
 extern struct clk clk_dummy;
 
 #define DEFINE_CK(_name, _cken, _ops)			\
-struct clk clk_##_name = {				\
-		.ops	= _ops,				\
+	struct clk clk_##_name;				\
+	static struct clk_pxa clk_pxa_##_name = {	\
+		.hw = {					\
+			.clk = &clk_##_name,		\
+		},					\
 		.cken	= CKEN_##_cken,			\
+	};						\
+	static struct clk clk_##_name = {		\
+		.name   = #_name,			\
+		.ops	= _ops,				\
+		.hw	= &clk_pxa_##_name.hw,		\
 	}
 
 #define DEFINE_CLK(_name, _ops, _rate, _delay)		\
-struct clk clk_##_name = {				\
-		.ops	= _ops, 			\
-		.rate	= _rate,			\
+	struct clk clk_##_name;				\
+	static struct clk_pxa clk_pxa_##_name = {	\
+		.hw = {					\
+			.clk = &clk_##_name,		\
+		},					\
 		.delay	= _delay,			\
+		.rate	= _rate,			\
+	};						\
+	static struct clk clk_##_name = {		\
+		.name   = #_name,			\
+		.ops	= _ops,				\
+		.hw	= &clk_pxa_##_name.hw,		\
 	}
 
 #define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay)	\
-struct clk clk_##_name = {				\
-		.ops	= &clk_pxa2xx_cken_ops,		\
-		.rate	= _rate,			\
+	struct clk clk_##_name;				\
+	static struct clk_pxa clk_pxa_##_name = {	\
+		.hw = {					\
+			.clk = &clk_##_name,		\
+		},					\
 		.cken	= CKEN_##_cken,			\
 		.delay	= _delay,			\
+		.rate	= _rate,			\
+	};						\
+	static struct clk clk_##_name = {		\
+		.name   = #_name,			\
+		.ops	= &clk_pxa2xx_cken_ops,		\
+		.hw	= &clk_pxa_##_name.hw,		\
 	}
 
-extern const struct clkops clk_pxa2xx_cken_ops;
+extern const struct clk_ops clk_pxa2xx_cken_ops;
+
+extern const struct clk_ops clk_pxa25x_mem_ops;
+extern const struct clk_ops clk_pxa25x_lcd_ops;
+extern const struct clk_ops clk_pxa25x_gpio12_ops;
+extern const struct clk_ops clk_pxa25x_gpio11_ops;
 
-extern const struct clkops clk_pxa25x_mem_ops;
-extern const struct clkops clk_pxa25x_lcd_ops;
-extern const struct clkops clk_pxa25x_gpio12_ops;
-extern const struct clkops clk_pxa25x_gpio11_ops;
+extern const struct clk_ops clk_pxa27x_mem_ops;
+extern const struct clk_ops clk_pxa27x_lcd_ops;
 
-extern const struct clkops clk_pxa27x_mem_ops;
-extern const struct clkops clk_pxa27x_lcd_ops;
+int clk_pxa2xx_cken_enable(struct clk_hw *hw);
+void clk_pxa2xx_cken_disable(struct clk_hw *hw);
 
-void clk_pxa2xx_cken_enable(struct clk *clk);
-void clk_pxa2xx_cken_disable(struct clk *clk);
 
 extern struct syscore_ops pxa2xx_clock_syscore_ops;
 
 #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
 #define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay)	\
-struct clk clk_##_name = {				\
-		.ops	= &clk_pxa3xx_cken_ops,		\
-		.rate	= _rate,			\
+	struct clk clk_##_name;				\
+	static struct clk_pxa clk_pxa_##_name = {	\
+		.hw = {					\
+			.clk = &clk_##_name,		\
+		},					\
 		.cken	= CKEN_##_cken,			\
 		.delay	= _delay,			\
+		.rate	= _rate,			\
+	};						\
+	static struct clk clk_##_name = {		\
+		.name   = #_name,			\
+		.ops	= &clk_pxa3xx_cken_ops,		\
+		.hw	= &clk_pxa_##_name.hw,		\
 	}
 
-extern const struct clkops clk_pxa3xx_cken_ops;
-extern const struct clkops clk_pxa3xx_hsio_ops;
-extern const struct clkops clk_pxa3xx_ac97_ops;
-extern const struct clkops clk_pxa3xx_pout_ops;
-extern const struct clkops clk_pxa3xx_smemc_ops;
+extern const struct clk_ops clk_pxa3xx_cken_ops;
+extern const struct clk_ops clk_pxa3xx_hsio_ops;
+extern const struct clk_ops clk_pxa3xx_ac97_ops;
+extern const struct clk_ops clk_pxa3xx_pout_ops;
+extern const struct clk_ops clk_pxa3xx_smemc_ops;
 
-extern void clk_pxa3xx_cken_enable(struct clk *);
-extern void clk_pxa3xx_cken_disable(struct clk *);
+extern int clk_pxa3xx_cken_enable(struct clk_hw *);
+extern void clk_pxa3xx_cken_disable(struct clk_hw *);
 
 extern struct syscore_ops pxa3xx_clock_syscore_ops;
 
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 3c29343..9214e03 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -126,17 +126,8 @@ struct resource eseries_tmio_resources[] = {
 };
 
 /* Some e-series hardware cannot control the 32K clock */
-static void clk_32k_dummy(struct clk *clk)
-{
-}
-
-static const struct clkops clk_32k_dummy_ops = {
-	.enable         = clk_32k_dummy,
-	.disable        = clk_32k_dummy,
-};
-
 static struct clk tmio_dummy_clk = {
-	.ops	= &clk_32k_dummy_ops,
+	.ops	= &clk_dummy_ops,
 	.rate	= 32768,
 };
 
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 2c2eb41..a5a42bc 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -16,6 +16,7 @@
  * initialization stuff for PXA machines which can be overridden later if
  * need be.
  */
+#include <linux/clk-private.h>
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
 #include <linux/module.h>
@@ -241,6 +242,27 @@ static int __init pxa25x_init(void)
 
 		reset_status = RCSR;
 
+		__clk_init(NULL, &clk_pxa25x_hwuart);
+		__clk_init(NULL, &clk_pxa25x_ffuart);
+		__clk_init(NULL, &clk_pxa25x_btuart);
+		__clk_init(NULL, &clk_pxa25x_stuart);
+		__clk_init(NULL, &clk_pxa25x_usb);
+		__clk_init(NULL, &clk_pxa25x_mmc);
+		__clk_init(NULL, &clk_pxa25x_i2c);
+		__clk_init(NULL, &clk_pxa25x_ssp);
+		__clk_init(NULL, &clk_pxa25x_nssp);
+		__clk_init(NULL, &clk_pxa25x_assp);
+		__clk_init(NULL, &clk_pxa25x_pwm0);
+		__clk_init(NULL, &clk_pxa25x_pwm1);
+		__clk_init(NULL, &clk_pxa25x_ac97);
+		__clk_init(NULL, &clk_pxa25x_i2s);
+		__clk_init(NULL, &clk_pxa25x_ficp);
+
+		__clk_init(NULL, &clk_pxa25x_lcd);
+		__clk_init(NULL, &clk_pxa25x_gpio11);
+		__clk_init(NULL, &clk_pxa25x_gpio12);
+		__clk_init(NULL, &clk_pxa25x_mem);
+
 		clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
 
 		if ((ret = pxa_init_dma(IRQ_DMA, 16)))
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index b9dc6ac..8f98413 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -11,6 +11,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/clk-private.h>
 #include <linux/gpio.h>
 #include <linux/gpio-pxa.h>
 #include <linux/module.h>
@@ -339,6 +340,35 @@ static int __init pxa27x_init(void)
 
 		reset_status = RCSR;
 
+		__clk_init(NULL, &clk_pxa27x_ffuart);
+		__clk_init(NULL, &clk_pxa27x_btuart);
+		__clk_init(NULL, &clk_pxa27x_stuart);
+		__clk_init(NULL, &clk_pxa27x_i2s);
+		__clk_init(NULL, &clk_pxa27x_i2c);
+		__clk_init(NULL, &clk_pxa27x_usb);
+		__clk_init(NULL, &clk_pxa27x_mmc);
+		__clk_init(NULL, &clk_pxa27x_ficp);
+		__clk_init(NULL, &clk_pxa27x_usbhost);
+		__clk_init(NULL, &clk_pxa27x_pwri2c);
+		__clk_init(NULL, &clk_pxa27x_keypad);
+		__clk_init(NULL, &clk_pxa27x_ssp1);
+		__clk_init(NULL, &clk_pxa27x_ssp2);
+		__clk_init(NULL, &clk_pxa27x_ssp3);
+		__clk_init(NULL, &clk_pxa27x_pwm0);
+		__clk_init(NULL, &clk_pxa27x_pwm1);
+		__clk_init(NULL, &clk_pxa27x_ac97);
+		__clk_init(NULL, &clk_pxa27x_ac97conf);
+		__clk_init(NULL, &clk_pxa27x_msl);
+		__clk_init(NULL, &clk_pxa27x_usim);
+		__clk_init(NULL, &clk_pxa27x_memstk);
+		__clk_init(NULL, &clk_pxa27x_im);
+		__clk_init(NULL, &clk_pxa27x_memc);
+
+		__clk_init(NULL, &clk_pxa27x_lcd);
+		__clk_init(NULL, &clk_pxa27x_camera);
+		__clk_init(NULL, &clk_pxa27x_mem);
+		__clk_init(NULL, &clk_dummy);
+
 		clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
 
 		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 25a093e..de6c85c 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -12,6 +12,8 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/clkdev.h>
+#include <linux/clk-private.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -453,6 +455,30 @@ static int __init pxa3xx_init(void)
 		 */
 		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
 
+		__clk_init(NULL, &clk_pxa3xx_pout);
+		__clk_init(NULL, &clk_dummy);
+		__clk_init(NULL, &clk_pxa3xx_lcd);
+		__clk_init(NULL, &clk_pxa3xx_camera);
+		__clk_init(NULL, &clk_pxa3xx_ac97);
+		__clk_init(NULL, &clk_pxa3xx_ffuart);
+		__clk_init(NULL, &clk_pxa3xx_btuart);
+		__clk_init(NULL, &clk_pxa3xx_stuart);
+		__clk_init(NULL, &clk_pxa3xx_i2c);
+		__clk_init(NULL, &clk_pxa3xx_udc);
+		__clk_init(NULL, &clk_pxa3xx_usbh);
+		__clk_init(NULL, &clk_pxa3xx_u2d);
+		__clk_init(NULL, &clk_pxa3xx_keypad);
+		__clk_init(NULL, &clk_pxa3xx_ssp1);
+		__clk_init(NULL, &clk_pxa3xx_ssp2);
+		__clk_init(NULL, &clk_pxa3xx_ssp3);
+		__clk_init(NULL, &clk_pxa3xx_ssp4);
+		__clk_init(NULL, &clk_pxa3xx_pwm0);
+		__clk_init(NULL, &clk_pxa3xx_pwm1);
+		__clk_init(NULL, &clk_pxa3xx_mmc1);
+		__clk_init(NULL, &clk_pxa3xx_mmc2);
+		__clk_init(NULL, &clk_pxa3xx_smemc);
+		__clk_init(NULL, &clk_pxa3xx_gpio);
+
 		clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
 
 		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
-- 
1.7.9.1




From mgreer at animalcreek.com  Fri Mar 16 14:02:28 2012
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Fri, 16 Mar 2012 11:02:28 -0700
Subject: [PATCH 2/2] arm: omap3: pm34xx.c: Replace printk() with
 appropriate pr_*()
In-Reply-To: <4F633528.1040305@ru.mvista.com>
References: <1331852833-4357-1-git-send-email-mgreer@animalcreek.com>
 <1331852833-4357-3-git-send-email-mgreer@animalcreek.com>
 <4F633528.1040305@ru.mvista.com>
Message-ID: <20120316180228.GA1894@animalcreek.com>

On Fri, Mar 16, 2012 at 04:42:16PM +0400, Sergei Shtylyov wrote:
> Hello.
> 
> On 16-03-2012 3:07, Mark A. Greer wrote:
> 
> >From: "Mark A. Greer" <mgreer at animalcreek.com>

> >@@ -463,7 +462,7 @@ restore:
> >  	list_for_each_entry(pwrst,&pwrst_list, node) {
> >  		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
> >  		if (state>  pwrst->next_state) {
> >-			printk(KERN_INFO "Powerdomain (%s) didn't enter "
> >+			pr_info("Powerdomain (%s) didn't enter "
> >  			       "target state %d\n",
> 
>    Last line should have been realigned I think.

Okay, I'll fix this and the others in a bit.

Mark
--


From broonie at opensource.wolfsonmicro.com  Fri Mar 16 14:45:12 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 16 Mar 2012 18:45:12 +0000
Subject: [PATCH v10] mfd: Add anatop mfd driver
In-Reply-To: <1331885816-26902-1-git-send-email-paul.liu@linaro.org>
References: <1331885816-26902-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120316184511.GA3158@opensource.wolfsonmicro.com>

On Fri, Mar 16, 2012 at 04:16:56PM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
> Anatop provides regulators and thermal.
> This driver handles the address space and the operation of the mfd device.

Reviwed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
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From broonie at opensource.wolfsonmicro.com  Fri Mar 16 15:18:12 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 16 Mar 2012 19:18:12 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F62B941.5010306@freescale.com>
References: <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315142702.GL3138@opensource.wolfsonmicro.com>
 <4F621C60.5090700@freescale.com>
 <20120316020111.GE6065@S2101-09.ap.freescale.net>
 <4F62A06C.5000304@freescale.com>
 <20120316025219.GB7632@S2101-09.ap.freescale.net>
 <4F62B941.5010306@freescale.com>
Message-ID: <20120316191809.GG3158@opensource.wolfsonmicro.com>

On Fri, Mar 16, 2012 at 03:53:39AM +0000, Tabi Timur-B04825 wrote:

> might be a way to general the call to platform_device_register_simple. 
> Maybe we could put "imx-pcm-audio" in the device tree?

We might end up doing that but as this adaption of the DMA controller to
the audio stack isn't really hardware so much as an implementation
detail of the audio stack it'd be nice to come up with some neater way
of doing it, ideally not involving the platform device at all.

I'm starting to think we should have a framework thing that lets DAI
drivers say they're a combined DMA/DAI driver for cases like this where
there is a generic DMA device that's being shared by lots of different
subsystems.  It's a common situation and it makes the device registration
clearer.  Adding Stephen Warren as he was thinking about this stuff in
the context of the nVidia drivers.
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From broonie at opensource.wolfsonmicro.com  Fri Mar 16 15:21:12 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 16 Mar 2012 19:21:12 +0000
Subject: [alsa-devel] [PATCH v5 8/8] ASoC: fsl: add imx-sgtl5000 machine
 driver
In-Reply-To: <20120316111814.GA7860@S2101-09.ap.freescale.net>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-9-git-send-email-shawn.guo@linaro.org>
 <CA+7tXihmfBQCgvuY0rx5v4w-bcwYK+7kP9v29w36N-Rc9KSQ+A@mail.gmail.com>
 <20120316111814.GA7860@S2101-09.ap.freescale.net>
Message-ID: <20120316192110.GH3158@opensource.wolfsonmicro.com>

On Fri, Mar 16, 2012 at 07:18:18PM +0800, Shawn Guo wrote:

> Maybe having "fsl,imx-audio-xxx" for machine drivers backed by SSI,
> and "fsl,imx-esai-audio-xxx" for the ones backed by ESAI?

Alternatively if the SSI and ESAI devices are compatible enough at the
ASoC API level (or can be identified by the driver just by looking at
the DAI that's referenced without too much pain) the CPU DAI could just
be linked to either type of DAI (probably with a more generic name for
the property).

But either way works fine, and obviously you're going to end up with
more complex systems which use a completely custom binding anyway.
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From mgherzan at gmail.com  Fri Mar 16 15:41:59 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Fri, 16 Mar 2012 20:41:59 +0100
Subject: [PATCH v8] ARM: net: JIT compiler for packet filters
In-Reply-To: <1331885844-30575-1-git-send-email-mgherzan@gmail.com>
References: <1331885844-30575-1-git-send-email-mgherzan@gmail.com>
Message-ID: <4F639787.7070801@gmail.com>

Am 16.03.2012 09:17, schrieb Mircea Gherzan:
> Based of Matt Evans's PPC64 implementation.
> 
> The compiler generates ARM instructions but interworking is
> supported for Thumb2 kernels.
> 
> Supports both little and big endian. Unaligned loads are emitted
> for ARMv6+. Not all the BPF opcodes that deal with ancillary data
> are supported. The scratch memory of the filter lives on the stack.
> Hardware integer division is used if it is available.
> 
> Enabled in the same way as for x86-64 and PPC64:
> 
> 	echo 1 > /proc/sys/net/core/bpf_jit_enable
> 
> A value greater than 1 enables opcode output.
> 
> Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
> ---
> 
> Changes in v8:
>  * skb_copy_bits() return value check in LDX_MSH
>  * immediate value as signed integer for absolute loads
> 
> Changes in v7:
>  * fix the intruction generation for LDX_MSH, OR_X, LSH_K,
>    RSH_K and JMP_JA
>  * fix the condition for saving the A register
>  * use fls() instead of the compiler builtin
>  * punt to the interpreter on absolute loads with K < 0
>  * check for invalid data references
>  * support the NEG opcode
>  * clear X in the prologue based on a context flag
>  * simplify the conditional jumps
> 
> Changes in v6:
>  * fix the code generation for the ANC_CPU opcode
> 
> Changes in v5:
>  * replace SEEN_LEN with SEEN_SKB
>  * set ctx->seen when handling some ancillary data opcodes
> 
> Changes in v4:
>  * first check if the JIT compiler is enabled
>  * fix the code generation for the LDX_MSH opcode
> 
> Changes in v3:
>  * no longer depend on EABI and !Thumb2
>  * add BLX "emulation" for ARMv4 without Thumb
>  * use the integer divide instruction on Cortex-A15
>  * fix the handling of the DIV_K opcode
>  * use a C wrapper for __aeabi_uidiv
>  * fix the generation of the epilogue (non-FP case)
> 
> Changes in v2:
>  * enable the compiler only for ARMv5+ because of the BLX instruction
>  * use the same comparison for the ARM version checks
>  * use misaligned accesses on ARMv6
>  * fix the SEEN_MEM
>  * fix the mem_words_used()
> 
>  arch/arm/Kconfig          |    1 +
>  arch/arm/Makefile         |    1 +
>  arch/arm/net/Makefile     |    3 +
>  arch/arm/net/bpf_jit_32.c |  916 +++++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/net/bpf_jit_32.h |  190 ++++++++++
>  5 files changed, 1111 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/net/Makefile
>  create mode 100644 arch/arm/net/bpf_jit_32.c
>  create mode 100644 arch/arm/net/bpf_jit_32.h
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index dfb0312..ade6274 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -32,6 +32,7 @@ config ARM
>  	select GENERIC_IRQ_SHOW
>  	select CPU_PM if (SUSPEND || CPU_IDLE)
>  	select GENERIC_PCI_IOMAP
> +	select HAVE_BPF_JIT
>  	help
>  	  The ARM series is a line of low-power-consumption RISC chip designs
>  	  licensed by ARM Ltd and targeted at embedded applications and
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 1683bfb..03b0039 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -252,6 +252,7 @@ core-$(CONFIG_VFP)		+= arch/arm/vfp/
>  
>  # If we have a machine-specific directory, then include it in the build.
>  core-y				+= arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
> +core-y				+= arch/arm/net/
>  core-y				+= $(machdirs) $(platdirs)
>  
>  drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
> diff --git a/arch/arm/net/Makefile b/arch/arm/net/Makefile
> new file mode 100644
> index 0000000..c2c1084
> --- /dev/null
> +++ b/arch/arm/net/Makefile
> @@ -0,0 +1,3 @@
> +# ARM-specific networking code
> +
> +obj-$(CONFIG_BPF_JIT) += bpf_jit_32.o
> diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
> new file mode 100644
> index 0000000..2ee157a
> --- /dev/null
> +++ b/arch/arm/net/bpf_jit_32.c
> @@ -0,0 +1,916 @@
> +/*
> + * Just-In-Time compiler for BPF filters on 32bit ARM
> + *
> + * Copyright (c) 2011 Mircea Gherzan <mgherzan at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; version 2 of the License.
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/compiler.h>
> +#include <linux/errno.h>
> +#include <linux/filter.h>
> +#include <linux/moduleloader.h>
> +#include <linux/netdevice.h>
> +#include <linux/string.h>
> +#include <linux/slab.h>
> +#include <asm/cacheflush.h>
> +#include <asm/hwcap.h>
> +
> +#include "bpf_jit_32.h"
> +
> +/*
> + * ABI:
> + *
> + * r0	scratch register
> + * r4	BPF register A
> + * r5	BPF register X
> + * r6	pointer to the skb
> + * r7	skb->data
> + * r8	skb_headlen(skb)
> + */
> +
> +#define r_scratch	ARM_R0
> +/* r1-r3 are (also) used for the unaligned loads on the non-ARMv7 slowpath */
> +#define r_off		ARM_R1
> +#define r_A		ARM_R4
> +#define r_X		ARM_R5
> +#define r_skb		ARM_R6
> +#define r_skb_data	ARM_R7
> +#define r_skb_hl	ARM_R8
> +
> +#define SCRATCH_SP_OFFSET	0
> +#define SCRATCH_OFF(k)		(SCRATCH_SP_OFFSET + (k))
> +
> +#define SEEN_MEM		((1 << BPF_MEMWORDS) - 1)
> +#define SEEN_MEM_WORD(k)	(1 << (k))
> +#define SEEN_X			(1 << BPF_MEMWORDS)
> +#define SEEN_CALL		(1 << (BPF_MEMWORDS + 1))
> +#define SEEN_SKB		(1 << (BPF_MEMWORDS + 2))
> +#define SEEN_DATA		(1 << (BPF_MEMWORDS + 3))
> +
> +#define FLAG_NEED_X_RESET	(1 << 0)
> +
> +struct jit_ctx {
> +	const struct sk_filter *skf;
> +	unsigned idx;
> +	unsigned prologue_bytes;
> +	int ret0_fp_idx;
> +	u32 seen;
> +	u32 flags;
> +	u32 *offsets;
> +	u32 *target;
> +#if __LINUX_ARM_ARCH__ < 7
> +	u16 epilogue_bytes;
> +	u16 imm_count;
> +	u32 *imms;
> +#endif
> +};
> +
> +int bpf_jit_enable __read_mostly;
> +
> +static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset)
> +{
> +	u8 ret;
> +	int err;
> +
> +	err = skb_copy_bits(skb, offset, &ret, 1);
> +
> +	return (u64)err << 32 | ret;
> +}
> +
> +static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset)
> +{
> +	u16 ret;
> +	int err;
> +
> +	err = skb_copy_bits(skb, offset, &ret, 2);
> +
> +	return (u64)err << 32 | ntohs(ret);
> +}
> +
> +static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset)
> +{
> +	u32 ret;
> +	int err;
> +
> +	err = skb_copy_bits(skb, offset, &ret, 4);
> +
> +	return (u64)err << 32 | ntohl(ret);
> +}
> +
> +/*
> + * Wrapper that handles both OABI and EABI and assures Thumb2 interworking
> + * (where the assembly routines like __aeabi_uidiv could cause problems).
> + */
> +static u32 jit_udiv(u32 dividend, u32 divisor)
> +{
> +	return dividend / divisor;
> +}
> +
> +static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx)
> +{
> +	if (ctx->target != NULL)
> +		ctx->target[ctx->idx] = inst | (cond << 28);
> +
> +	ctx->idx++;
> +}
> +
> +/*
> + * Emit an instruction that will be executed unconditionally.
> + */
> +static inline void emit(u32 inst, struct jit_ctx *ctx)
> +{
> +	_emit(ARM_COND_AL, inst, ctx);
> +}
> +
> +static u16 saved_regs(struct jit_ctx *ctx)
> +{
> +	u16 ret = 0;
> +
> +	if ((ctx->skf->len > 1) ||
> +	    (ctx->skf->insns[0].code == BPF_S_RET_A))
> +		ret |= 1 << r_A;
> +
> +#ifdef CONFIG_FRAME_POINTER
> +	ret |= (1 << ARM_FP) | (1 << ARM_IP) | (1 << ARM_LR) | (1 << ARM_PC);
> +#else
> +	if (ctx->seen & SEEN_CALL)
> +		ret |= 1 << ARM_LR;
> +#endif
> +	if (ctx->seen & (SEEN_DATA | SEEN_SKB))
> +		ret |= 1 << r_skb;
> +	if (ctx->seen & SEEN_DATA)
> +		ret |= (1 << r_skb_data) | (1 << r_skb_hl);
> +	if (ctx->seen & SEEN_X)
> +		ret |= 1 << r_X;
> +
> +	return ret;
> +}
> +
> +static inline int mem_words_used(struct jit_ctx *ctx)
> +{
> +	/* yes, we do waste some stack space IF there are "holes" in the set" */
> +	return fls(ctx->seen & SEEN_MEM);
> +}
> +
> +static inline bool is_load_to_a(u16 inst)
> +{
> +	switch (inst) {
> +	case BPF_S_LD_W_LEN:
> +	case BPF_S_LD_W_ABS:
> +	case BPF_S_LD_H_ABS:
> +	case BPF_S_LD_B_ABS:
> +	case BPF_S_ANC_CPU:
> +	case BPF_S_ANC_IFINDEX:
> +	case BPF_S_ANC_MARK:
> +	case BPF_S_ANC_PROTOCOL:
> +	case BPF_S_ANC_RXHASH:
> +	case BPF_S_ANC_QUEUE:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static void build_prologue(struct jit_ctx *ctx)
> +{
> +	u16 reg_set = saved_regs(ctx);
> +	u16 first_inst = ctx->skf->insns[0].code;
> +	u16 off;
> +
> +#ifdef CONFIG_FRAME_POINTER
> +	emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx);
> +	emit(ARM_PUSH(reg_set), ctx);
> +	emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx);
> +#else
> +	if (reg_set)
> +		emit(ARM_PUSH(reg_set), ctx);
> +#endif
> +
> +	if (ctx->seen & (SEEN_DATA | SEEN_SKB))
> +		emit(ARM_MOV_R(r_skb, ARM_R0), ctx);
> +
> +	if (ctx->seen & SEEN_DATA) {
> +		off = offsetof(struct sk_buff, data);
> +		emit(ARM_LDR_I(r_skb_data, r_skb, off), ctx);
> +		/* headlen = len - data_len */
> +		off = offsetof(struct sk_buff, len);
> +		emit(ARM_LDR_I(r_skb_hl, r_skb, off), ctx);
> +		off = offsetof(struct sk_buff, data_len);
> +		emit(ARM_LDR_I(r_scratch, r_skb, off), ctx);
> +		emit(ARM_SUB_R(r_skb_hl, r_skb_hl, r_scratch), ctx);
> +	}
> +
> +	if (ctx->flags & FLAG_NEED_X_RESET)
> +		emit(ARM_MOV_I(r_X, 0), ctx);
> +
> +	/* do not leak kernel data to userspace */
> +	if ((first_inst != BPF_S_RET_K) && !(is_load_to_a(first_inst)))
> +		emit(ARM_MOV_I(r_A, 0), ctx);
> +
> +	/* stack space for the BPF_MEM words */
> +	if (ctx->seen & SEEN_MEM)
> +		emit(ARM_SUB_I(ARM_SP, ARM_SP, mem_words_used(ctx) * 4), ctx);
> +}
> +
> +static void build_epilogue(struct jit_ctx *ctx)
> +{
> +	u16 reg_set = saved_regs(ctx);
> +
> +	if (ctx->seen & SEEN_MEM)
> +		emit(ARM_ADD_I(ARM_SP, ARM_SP, mem_words_used(ctx) * 4), ctx);
> +
> +	reg_set &= ~(1 << ARM_LR);
> +
> +#ifdef CONFIG_FRAME_POINTER
> +	/* the first instruction of the prologue was: mov ip, sp */
> +	reg_set &= ~(1 << ARM_IP);
> +	reg_set |= (1 << ARM_SP);
> +	emit(ARM_LDM(ARM_SP, reg_set), ctx);
> +#else
> +	if (reg_set) {
> +		if (ctx->seen & SEEN_CALL)
> +			reg_set |= 1 << ARM_PC;
> +		emit(ARM_POP(reg_set), ctx);
> +	}
> +
> +	if (!(ctx->seen & SEEN_CALL))
> +		emit(ARM_BX(ARM_LR), ctx);
> +#endif
> +}
> +
> +static int16_t imm8m(u32 x)
> +{
> +	u32 rot;
> +
> +	for (rot = 0; rot < 16; rot++)
> +		if ((x & ~ror32(0xff, 2 * rot)) == 0)
> +			return rol32(x, 2 * rot) | (rot << 8);
> +
> +	return -1;
> +}
> +
> +#if __LINUX_ARM_ARCH__ < 7
> +
> +static u16 imm_offset(u32 k, struct jit_ctx *ctx)
> +{
> +	unsigned i = 0, offset;
> +	u16 imm;
> +
> +	/* on the "fake" run we just count them (duplicates included) */
> +	if (ctx->target == NULL) {
> +		ctx->imm_count++;
> +		return 0;
> +	}
> +
> +	while ((i < ctx->imm_count) && ctx->imms[i]) {
> +		if (ctx->imms[i] == k)
> +			break;
> +		i++;
> +	}
> +
> +	if (ctx->imms[i] == 0)
> +		ctx->imms[i] = k;
> +
> +	/* constants go just after the epilogue */
> +	offset =  ctx->offsets[ctx->skf->len];
> +	offset += ctx->prologue_bytes;
> +	offset += ctx->epilogue_bytes;
> +	offset += i * 4;
> +
> +	ctx->target[offset / 4] = k;
> +
> +	/* PC in ARM mode == address of the instruction + 8 */
> +	imm = offset - (8 + ctx->idx * 4);
> +
> +	return imm;
> +}
> +
> +#endif /* __LINUX_ARM_ARCH__ */
> +
> +/*
> + * Move an immediate that's not an imm8m to a core register.
> + */
> +static inline void emit_mov_i_no8m(int rd, u32 val, struct jit_ctx *ctx)
> +{
> +#if __LINUX_ARM_ARCH__ < 7
> +	emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx);
> +#else
> +	emit(ARM_MOVW(rd, val & 0xffff), ctx);
> +	if (val > 0xffff)
> +		emit(ARM_MOVT(rd, val >> 16), ctx);
> +#endif
> +}
> +
> +static inline void emit_mov_i(int rd, u32 val, struct jit_ctx *ctx)
> +{
> +	int imm12 = imm8m(val);
> +
> +	if (imm12 >= 0)
> +		emit(ARM_MOV_I(rd, imm12), ctx);
> +	else
> +		emit_mov_i_no8m(rd, val, ctx);
> +}
> +
> +#if __LINUX_ARM_ARCH__ < 6
> +
> +static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
> +{
> +	_emit(cond, ARM_LDRB_I(ARM_R3, r_addr, 1), ctx);
> +	_emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx);
> +	_emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 3), ctx);
> +	_emit(cond, ARM_LSL_I(ARM_R3, ARM_R3, 16), ctx);
> +	_emit(cond, ARM_LDRB_I(ARM_R0, r_addr, 2), ctx);
> +	_emit(cond, ARM_ORR_S(ARM_R3, ARM_R3, ARM_R1, SRTYPE_LSL, 24), ctx);
> +	_emit(cond, ARM_ORR_R(ARM_R3, ARM_R3, ARM_R2), ctx);
> +	_emit(cond, ARM_ORR_S(r_res, ARM_R3, ARM_R0, SRTYPE_LSL, 8), ctx);
> +}
> +
> +static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
> +{
> +	_emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx);
> +	_emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 1), ctx);
> +	_emit(cond, ARM_ORR_S(r_res, ARM_R2, ARM_R1, SRTYPE_LSL, 8), ctx);
> +}
> +
> +static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx)
> +{
> +	emit(ARM_LSL_R(ARM_R1, r_src, 8), ctx);
> +	emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSL, 8), ctx);
> +	emit(ARM_LSL_I(r_dst, r_dst, 8), ctx);
> +	emit(ARM_LSL_R(r_dst, r_dst, 8), ctx);
> +}
> +
> +#else  /* ARMv6+ */
> +
> +static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
> +{
> +	_emit(cond, ARM_LDR_I(r_res, r_addr, 0), ctx);
> +#ifdef __LITTLE_ENDIAN
> +	_emit(cond, ARM_REV(r_res, r_res), ctx);
> +#endif
> +}
> +
> +static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
> +{
> +	_emit(cond, ARM_LDRH_I(r_res, r_addr, 0), ctx);
> +#ifdef __LITTLE_ENDIAN
> +	_emit(cond, ARM_REV16(r_res, r_res), ctx);
> +#endif
> +}
> +
> +static inline void emit_swap16(u8 r_dst __maybe_unused,
> +			       u8 r_src __maybe_unused,
> +			       struct jit_ctx *ctx __maybe_unused)
> +{
> +#ifdef __LITTLE_ENDIAN
> +	emit(ARM_REV16(r_dst, r_src), ctx);
> +#endif
> +}
> +
> +#endif /* __LINUX_ARM_ARCH__ < 6 */
> +
> +
> +/* Compute the immediate value for a PC-relative branch. */
> +static inline u32 b_imm(unsigned tgt, struct jit_ctx *ctx)
> +{
> +	u32 imm;
> +
> +	if (ctx->target == NULL)
> +		return 0;
> +	/*
> +	 * BPF allows only forward jumps and the offset of the target is
> +	 * still the one computed during the first pass.
> +	 */
> +	imm  = ctx->offsets[tgt] + ctx->prologue_bytes - (ctx->idx * 4 + 8);
> +
> +	return imm >> 2;
> +}
> +
> +#define OP_IMM3(op, r1, r2, imm_val, ctx)				\
> +	do {								\
> +		imm12 = imm8m(imm_val);					\
> +		if (imm12 < 0) {					\
> +			emit_mov_i_no8m(r_scratch, imm_val, ctx);	\
> +			emit(op ## _R((r1), (r2), r_scratch), ctx);	\
> +		} else {						\
> +			emit(op ## _I((r1), (r2), imm12), ctx);		\
> +		}							\
> +	} while (0)
> +
> +static inline void emit_err_ret(u8 cond, struct jit_ctx *ctx)
> +{
> +	if (ctx->ret0_fp_idx >= 0) {
> +		_emit(cond, ARM_B(b_imm(ctx->ret0_fp_idx, ctx)), ctx);
> +		/* NOP to keep the size constant between passes */
> +		emit(ARM_MOV_R(ARM_R0, ARM_R0), ctx);
> +	} else {
> +		_emit(cond, ARM_MOV_I(ARM_R0, 0), ctx);
> +		_emit(cond, ARM_B(b_imm(ctx->skf->len, ctx)), ctx);
> +	}
> +}
> +
> +static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
> +{
> +#if __LINUX_ARM_ARCH__ < 5
> +	emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
> +
> +	if (elf_hwcap & HWCAP_THUMB)
> +		emit(ARM_BX(tgt_reg), ctx);
> +	else
> +		emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx);
> +#else
> +	emit(ARM_BLX_R(tgt_reg), ctx);
> +#endif
> +}
> +
> +static inline void emit_udiv(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx)
> +{
> +#if __LINUX_ARM_ARCH__ == 7
> +	if (elf_hwcap & HWCAP_IDIVA) {
> +		emit(ARM_UDIV(rd, rm, rn), ctx);
> +		return;
> +	}
> +#endif
> +	if (rm != ARM_R0)
> +		emit(ARM_MOV_R(ARM_R0, rm), ctx);
> +	if (rn != ARM_R1)
> +		emit(ARM_MOV_R(ARM_R1, rn), ctx);
> +
> +	ctx->seen |= SEEN_CALL;
> +	emit_mov_i(ARM_R3, (u32)jit_udiv, ctx);
> +	emit_blx_r(ARM_R3, ctx);
> +
> +	if (rd != ARM_R0)
> +		emit(ARM_MOV_R(rd, ARM_R0), ctx);
> +}
> +
> +static inline void update_on_xread(struct jit_ctx *ctx)
> +{
> +	if (!(ctx->seen & SEEN_X))
> +		ctx->flags |= FLAG_NEED_X_RESET;
> +
> +	ctx->seen |= SEEN_X;
> +}
> +
> +static int build_body(struct jit_ctx *ctx)
> +{
> +	void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
> +	const struct sk_filter *prog = ctx->skf;
> +	const struct sock_filter *inst;
> +	unsigned i, load_order, off, condt;
> +	int imm12;
> +	u32 k;
> +
> +	for (i = 0; i < prog->len; i++) {
> +		inst = &(prog->insns[i]);
> +		/* K as an immediate value operand */
> +		k = inst->k;
> +
> +		/* compute offsets only in the fake pass */
> +		if (ctx->target == NULL)
> +			ctx->offsets[i] = ctx->idx * 4;
> +
> +		switch (inst->code) {
> +		case BPF_S_LD_IMM:
> +			emit_mov_i(r_A, k, ctx);
> +			break;
> +		case BPF_S_LD_W_LEN:
> +			ctx->seen |= SEEN_SKB;
> +			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
> +			emit(ARM_LDR_I(r_A, r_skb,
> +				       offsetof(struct sk_buff, len)), ctx);
> +			break;
> +		case BPF_S_LD_MEM:
> +			/* A = scratch[k] */
> +			ctx->seen |= SEEN_MEM_WORD(k);
> +			emit(ARM_LDR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
> +			break;
> +		case BPF_S_LD_W_ABS:
> +			load_order = 2;
> +			goto load;
> +		case BPF_S_LD_H_ABS:
> +			load_order = 1;
> +			goto load;
> +		case BPF_S_LD_B_ABS:
> +			load_order = 0;
> +load:
> +			/* the interpreter will deal with the negative K */
> +			if ((int)k < 0)
> +				return -ENOTSUPP;
> +			emit_mov_i(r_off, k, ctx);
> +load_common:
> +			ctx->seen |= SEEN_DATA | SEEN_CALL;
> +
> +			if (load_order > 0) {
> +				emit(ARM_SUB_I(r_scratch, r_skb_hl,
> +					       1 << load_order), ctx);
> +				emit(ARM_CMP_R(r_scratch, r_off), ctx);
> +				condt = ARM_COND_HS;
> +			} else {
> +				emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
> +				condt = ARM_COND_HI;
> +			}
> +
> +			_emit(condt, ARM_ADD_R(r_scratch, r_off, r_skb_data),
> +			      ctx);
> +
> +			if (load_order == 0)
> +				_emit(condt, ARM_LDRB_I(r_A, r_scratch, 0),
> +				      ctx);
> +			else if (load_order == 1)
> +				emit_load_be16(condt, r_A, r_scratch, ctx);
> +			else if (load_order == 2)
> +				emit_load_be32(condt, r_A, r_scratch, ctx);
> +
> +			_emit(condt, ARM_B(b_imm(i + 1, ctx)), ctx);
> +
> +			/* the slowpath */
> +			emit_mov_i(ARM_R3, (u32)load_func[load_order], ctx);
> +			emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
> +			/* the offset is already in R1 */
> +			emit_blx_r(ARM_R3, ctx);
> +			/* check the result of skb_copy_bits */
> +			emit(ARM_CMP_I(ARM_R1, 0), ctx);
> +			emit_err_ret(ARM_COND_NE, ctx);
> +			emit(ARM_MOV_R(r_A, ARM_R0), ctx);
> +			break;
> +		case BPF_S_LD_W_IND:
> +			load_order = 2;
> +			goto load_ind;
> +		case BPF_S_LD_H_IND:
> +			load_order = 1;
> +			goto load_ind;
> +		case BPF_S_LD_B_IND:
> +			load_order = 0;
> +load_ind:
> +			OP_IMM3(ARM_ADD, r_off, r_X, k, ctx);
> +			goto load_common;
> +		case BPF_S_LDX_IMM:
> +			ctx->seen |= SEEN_X;
> +			emit_mov_i(r_X, k, ctx);
> +			break;
> +		case BPF_S_LDX_W_LEN:
> +			ctx->seen |= SEEN_X | SEEN_SKB;
> +			emit(ARM_LDR_I(r_X, r_skb,
> +				       offsetof(struct sk_buff, len)), ctx);
> +			break;
> +		case BPF_S_LDX_MEM:
> +			ctx->seen |= SEEN_X | SEEN_MEM_WORD(k);
> +			emit(ARM_LDR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
> +			break;
> +		case BPF_S_LDX_B_MSH:
> +			/* x = ((*(frame + k)) & 0xf) << 2; */
> +			ctx->seen |= SEEN_X | SEEN_DATA | SEEN_CALL;
> +			/* the interpreter should deal with the negative K */
> +			if (k < 0)
> +				return -1;
> +			/* offset in r1: we might have to take the slow path */
> +			emit_mov_i(r_off, k, ctx);
> +			emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
> +
> +			/* load in r0: common with the slowpath */
> +			_emit(ARM_COND_HI, ARM_LDRB_R(ARM_R0, r_skb_data,
> +						      ARM_R1), ctx);
> +			/*
> +			 * emit_mov_i() might generate one or two instructions,
> +			 * the same holds for emit_blx_r()
> +			 */
> +			_emit(ARM_COND_HI, ARM_B(b_imm(i + 1, ctx) - 2), ctx);
> +
> +			emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
> +			/* r_off is r1 */
> +			emit_mov_i(ARM_R3, (u32)jit_get_skb_b, ctx);
> +			emit_blx_r(ARM_R3, ctx);
> +			/* check the return value of skb_copy_bits */
> +			emit(ARM_CMP_I(ARM_R1, 0), ctx);
> +			emit_err_ret(ARM_COND_NE, ctx);
> +
> +			emit(ARM_AND_I(r_X, ARM_R0, 0x00f), ctx);
> +			emit(ARM_LSL_I(r_X, r_X, 2), ctx);
> +			break;
> +		case BPF_S_ST:
> +			ctx->seen |= SEEN_MEM_WORD(k);
> +			emit(ARM_STR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
> +			break;
> +		case BPF_S_STX:
> +			update_on_xread(ctx);
> +			ctx->seen |= SEEN_MEM_WORD(k);
> +			emit(ARM_STR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
> +			break;
> +		case BPF_S_ALU_ADD_K:
> +			/* A += K */
> +			OP_IMM3(ARM_ADD, r_A, r_A, k, ctx);
> +			break;
> +		case BPF_S_ALU_ADD_X:
> +			update_on_xread(ctx);
> +			emit(ARM_ADD_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_SUB_K:
> +			/* A -= K */
> +			OP_IMM3(ARM_SUB, r_A, r_A, k, ctx);
> +			break;
> +		case BPF_S_ALU_SUB_X:
> +			update_on_xread(ctx);
> +			emit(ARM_SUB_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_MUL_K:
> +			/* A *= K */
> +			emit_mov_i(r_scratch, k, ctx);
> +			emit(ARM_MUL(r_A, r_A, r_scratch), ctx);
> +			break;
> +		case BPF_S_ALU_MUL_X:
> +			update_on_xread(ctx);
> +			emit(ARM_MUL(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_DIV_K:
> +			/* current k == reciprocal_value(userspace k) */
> +			emit_mov_i(r_scratch, k, ctx);
> +			/* A = top 32 bits of the product */
> +			emit(ARM_UMULL(r_scratch, r_A, r_A, r_scratch), ctx);
> +			break;
> +		case BPF_S_ALU_DIV_X:
> +			update_on_xread(ctx);
> +			emit(ARM_CMP_I(r_X, 0), ctx);
> +			emit_err_ret(ARM_COND_EQ, ctx);
> +			emit_udiv(r_A, r_A, r_X, ctx);
> +			break;
> +		case BPF_S_ALU_OR_K:
> +			/* A |= K */
> +			OP_IMM3(ARM_ORR, r_A, r_A, k, ctx);
> +			break;
> +		case BPF_S_ALU_OR_X:
> +			update_on_xread(ctx);
> +			emit(ARM_ORR_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_AND_K:
> +			/* A &= K */
> +			OP_IMM3(ARM_AND, r_A, r_A, k, ctx);
> +			break;
> +		case BPF_S_ALU_AND_X:
> +			update_on_xread(ctx);
> +			emit(ARM_AND_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_LSH_K:
> +			if (unlikely(k > 31))
> +				return -1;
> +			emit(ARM_LSL_I(r_A, r_A, k), ctx);
> +			break;
> +		case BPF_S_ALU_LSH_X:
> +			update_on_xread(ctx);
> +			emit(ARM_LSL_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_RSH_K:
> +			if (unlikely(k > 31))
> +				return -1;
> +			emit(ARM_LSR_I(r_A, r_A, k), ctx);
> +			break;
> +		case BPF_S_ALU_RSH_X:
> +			update_on_xread(ctx);
> +			emit(ARM_LSR_R(r_A, r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ALU_NEG:
> +			/* A = -A */
> +			emit(ARM_RSB_I(r_A, r_A, 0), ctx);
> +			break;
> +		case BPF_S_JMP_JA:
> +			/* pc += K */
> +			emit(ARM_B(b_imm(i + k + 1, ctx)), ctx);
> +			break;
> +		case BPF_S_JMP_JEQ_K:
> +			/* pc += (A == K) ? pc->jt : pc->jf */
> +			condt  = ARM_COND_EQ;
> +			goto cmp_imm;
> +		case BPF_S_JMP_JGT_K:
> +			/* pc += (A > K) ? pc->jt : pc->jf */
> +			condt  = ARM_COND_HI;
> +			goto cmp_imm;
> +		case BPF_S_JMP_JGE_K:
> +			/* pc += (A >= K) ? pc->jt : pc->jf */
> +			condt  = ARM_COND_HS;
> +cmp_imm:
> +			imm12 = imm8m(k);
> +			if (imm12 < 0) {
> +				emit_mov_i_no8m(r_scratch, k, ctx);
> +				emit(ARM_CMP_R(r_A, r_scratch), ctx);
> +			} else {
> +				emit(ARM_CMP_I(r_A, imm12), ctx);
> +			}
> +cond_jump:
> +			if (inst->jt)
> +				_emit(condt, ARM_B(b_imm(i + inst->jt + 1,
> +						   ctx)), ctx);
> +			if (inst->jf)
> +				_emit(condt ^ 1, ARM_B(b_imm(i + inst->jf + 1,
> +							     ctx)), ctx);
> +			break;
> +		case BPF_S_JMP_JEQ_X:
> +			/* pc += (A == X) ? pc->jt : pc->jf */
> +			condt   = ARM_COND_EQ;
> +			goto cmp_x;
> +		case BPF_S_JMP_JGT_X:
> +			/* pc += (A > X) ? pc->jt : pc->jf */
> +			condt   = ARM_COND_HI;
> +			goto cmp_x;
> +		case BPF_S_JMP_JGE_X:
> +			/* pc += (A >= X) ? pc->jt : pc->jf */
> +			condt   = ARM_COND_CS;
> +cmp_x:
> +			update_on_xread(ctx);
> +			emit(ARM_CMP_R(r_A, r_X), ctx);
> +			goto cond_jump;
> +		case BPF_S_JMP_JSET_K:
> +			/* pc += (A & K) ? pc->jt : pc->jf */
> +			condt  = ARM_COND_NE;
> +			/* not set iff all zeroes iff Z==1 iff EQ */
> +
> +			imm12 = imm8m(k);
> +			if (imm12 < 0) {
> +				emit_mov_i_no8m(r_scratch, k, ctx);
> +				emit(ARM_TST_R(r_A, r_scratch), ctx);
> +			} else {
> +				emit(ARM_TST_I(r_A, imm12), ctx);
> +			}
> +			goto cond_jump;
> +		case BPF_S_JMP_JSET_X:
> +			/* pc += (A & X) ? pc->jt : pc->jf */
> +			update_on_xread(ctx);
> +			condt  = ARM_COND_NE;
> +			emit(ARM_TST_R(r_A, r_X), ctx);
> +			goto cond_jump;
> +		case BPF_S_RET_A:
> +			emit(ARM_MOV_R(ARM_R0, r_A), ctx);
> +			goto b_epilogue;
> +		case BPF_S_RET_K:
> +			if ((k == 0) && (ctx->ret0_fp_idx < 0))
> +				ctx->ret0_fp_idx = i;
> +			emit_mov_i(ARM_R0, k, ctx);
> +b_epilogue:
> +			if (i != ctx->skf->len - 1)
> +				emit(ARM_B(b_imm(prog->len, ctx)), ctx);
> +			break;
> +		case BPF_S_MISC_TAX:
> +			/* X = A */
> +			ctx->seen |= SEEN_X;
> +			emit(ARM_MOV_R(r_X, r_A), ctx);
> +			break;
> +		case BPF_S_MISC_TXA:
> +			/* A = X */
> +			update_on_xread(ctx);
> +			emit(ARM_MOV_R(r_A, r_X), ctx);
> +			break;
> +		case BPF_S_ANC_PROTOCOL:
> +			/* A = ntohs(skb->protocol) */
> +			ctx->seen |= SEEN_SKB;
> +			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
> +						  protocol) != 2);
> +			off = offsetof(struct sk_buff, protocol);
> +			emit(ARM_LDRH_I(r_scratch, r_skb, off), ctx);
> +			emit_swap16(r_A, r_scratch, ctx);
> +			break;
> +		case BPF_S_ANC_CPU:
> +			/* r_scratch = current_thread_info() */
> +			OP_IMM3(ARM_BIC, r_scratch, ARM_SP, THREAD_SIZE - 1, ctx);
> +			/* A = current_thread_info()->cpu */
> +			BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info, cpu) != 4);
> +			off = offsetof(struct thread_info, cpu);
> +			emit(ARM_LDR_I(r_A, r_scratch, off), ctx);
> +			break;
> +		case BPF_S_ANC_IFINDEX:
> +			/* A = skb->dev->ifindex */
> +			ctx->seen |= SEEN_SKB;
> +			off = offsetof(struct sk_buff, dev);
> +			emit(ARM_LDR_I(r_scratch, r_skb, off), ctx);
> +
> +			emit(ARM_CMP_I(r_scratch, 0), ctx);
> +			emit_err_ret(ARM_COND_EQ, ctx);
> +
> +			BUILD_BUG_ON(FIELD_SIZEOF(struct net_device,
> +						  ifindex) != 4);
> +			off = offsetof(struct net_device, ifindex);
> +			emit(ARM_LDR_I(r_A, r_scratch, off), ctx);
> +			break;
> +		case BPF_S_ANC_MARK:
> +			ctx->seen |= SEEN_SKB;
> +			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
> +			off = offsetof(struct sk_buff, mark);
> +			emit(ARM_LDR_I(r_A, r_skb, off), ctx);
> +			break;
> +		case BPF_S_ANC_RXHASH:
> +			ctx->seen |= SEEN_SKB;
> +			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, rxhash) != 4);
> +			off = offsetof(struct sk_buff, rxhash);
> +			emit(ARM_LDR_I(r_A, r_skb, off), ctx);
> +			break;
> +		case BPF_S_ANC_QUEUE:
> +			ctx->seen |= SEEN_SKB;
> +			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
> +						  queue_mapping) != 2);
> +			BUILD_BUG_ON(offsetof(struct sk_buff,
> +					      queue_mapping) > 0xff);
> +			off = offsetof(struct sk_buff, queue_mapping);
> +			emit(ARM_LDRH_I(r_A, r_skb, off), ctx);
> +			break;
> +		default:
> +			return -1;
> +		}
> +	}
> +
> +	/* compute offsets only during the first pass */
> +	if (ctx->target == NULL)
> +		ctx->offsets[i] = ctx->idx * 4;
> +
> +	return 0;
> +}
> +
> +
> +void bpf_jit_compile(struct sk_filter *fp)
> +{
> +	struct jit_ctx ctx;
> +	unsigned tmp_idx;
> +	unsigned alloc_size;
> +
> +	if (!bpf_jit_enable)
> +		return;
> +
> +	memset(&ctx, 0, sizeof(ctx));
> +	ctx.skf		= fp;
> +	ctx.ret0_fp_idx = -1;
> +
> +	ctx.offsets = kzalloc(GFP_KERNEL, 4 * (ctx.skf->len + 1));
> +	if (ctx.offsets == NULL)
> +		return;
> +
> +	/* fake pass to fill in the ctx->seen */
> +	if (unlikely(build_body(&ctx)))
> +		goto out;
> +
> +	tmp_idx = ctx.idx;
> +	build_prologue(&ctx);
> +	ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
> +
> +#if __LINUX_ARM_ARCH__ < 7
> +	tmp_idx = ctx.idx;
> +	build_epilogue(&ctx);
> +	ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4;
> +
> +	ctx.idx += ctx.imm_count;
> +	if (ctx.imm_count) {
> +		ctx.imms = kzalloc(GFP_KERNEL, 4 * ctx.imm_count);
> +		if (ctx.imms == NULL)
> +			goto out;
> +	}
> +#else
> +	/* there's nothing after the epilogue on ARMv7 */
> +	build_epilogue(&ctx);
> +#endif
> +
> +	alloc_size = 4 * ctx.idx;
> +	ctx.target = module_alloc(max(sizeof(struct work_struct),
> +				      alloc_size));
> +	if (unlikely(ctx.target == NULL))
> +		goto out;
> +
> +	ctx.idx = 0;
> +	build_prologue(&ctx);
> +	build_body(&ctx);
> +	build_epilogue(&ctx);
> +
> +	flush_icache_range((u32)ctx.target, (u32)(ctx.target + ctx.idx));
> +
> +#if __LINUX_ARM_ARCH__ < 7
> +	if (ctx.imm_count)
> +		kfree(ctx.imms);
> +#endif
> +
> +	if (bpf_jit_enable > 1)
> +		print_hex_dump(KERN_INFO, "BPF JIT code: ",
> +			       DUMP_PREFIX_ADDRESS, 16, 4, ctx.target,
> +			       alloc_size, false);
> +
> +	fp->bpf_func = (void *)ctx.target;
> +out:
> +	kfree(ctx.offsets);
> +	return;
> +}
> +
> +static void bpf_jit_free_worker(struct work_struct *work)
> +{
> +	module_free(NULL, work);
> +}
> +
> +void bpf_jit_free(struct sk_filter *fp)
> +{
> +	struct work_struct *work;
> +
> +	if (fp->bpf_func != sk_run_filter) {
> +		work = (struct work_struct *)fp->bpf_func;
> +
> +		INIT_WORK(work, bpf_jit_free_worker);
> +		schedule_work(work);
> +	}
> +}
> +
> diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
> new file mode 100644
> index 0000000..99ae5e3
> --- /dev/null
> +++ b/arch/arm/net/bpf_jit_32.h
> @@ -0,0 +1,190 @@
> +/*
> + * Just-In-Time compiler for BPF filters on 32bit ARM
> + *
> + * Copyright (c) 2011 Mircea Gherzan <mgherzan at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; version 2 of the License.
> + */
> +
> +#ifndef PFILTER_OPCODES_ARM_H
> +#define PFILTER_OPCODES_ARM_H
> +
> +#define ARM_R0	0
> +#define ARM_R1	1
> +#define ARM_R2	2
> +#define ARM_R3	3
> +#define ARM_R4	4
> +#define ARM_R5	5
> +#define ARM_R6	6
> +#define ARM_R7	7
> +#define ARM_R8	8
> +#define ARM_R9	9
> +#define ARM_R10	10
> +#define ARM_FP	11
> +#define ARM_IP	12
> +#define ARM_SP	13
> +#define ARM_LR	14
> +#define ARM_PC	15
> +
> +#define ARM_COND_EQ		0x0
> +#define ARM_COND_NE		0x1
> +#define ARM_COND_CS		0x2
> +#define ARM_COND_HS		ARM_COND_CS
> +#define ARM_COND_CC		0x3
> +#define ARM_COND_LO		ARM_COND_CC
> +#define ARM_COND_MI		0x4
> +#define ARM_COND_PL		0x5
> +#define ARM_COND_VS		0x6
> +#define ARM_COND_VC		0x7
> +#define ARM_COND_HI		0x8
> +#define ARM_COND_LS		0x9
> +#define ARM_COND_GE		0xa
> +#define ARM_COND_LT		0xb
> +#define ARM_COND_GT		0xc
> +#define ARM_COND_LE		0xd
> +#define ARM_COND_AL		0xe
> +
> +/* register shift types */
> +#define SRTYPE_LSL		0
> +#define SRTYPE_LSR		1
> +#define SRTYPE_ASR		2
> +#define SRTYPE_ROR		3
> +
> +#define ARM_INST_ADD_R		0x00800000
> +#define ARM_INST_ADD_I		0x02800000
> +
> +#define ARM_INST_AND_R		0x00000000
> +#define ARM_INST_AND_I		0x02000000
> +
> +#define ARM_INST_BIC_R		0x01c00000
> +#define ARM_INST_BIC_I		0x03c00000
> +
> +#define ARM_INST_B		0x0a000000
> +#define ARM_INST_BX		0x012FFF10
> +#define ARM_INST_BLX_R		0x012fff30
> +
> +#define ARM_INST_CMP_R		0x01500000
> +#define ARM_INST_CMP_I		0x03500000
> +
> +#define ARM_INST_LDRB_I		0x05d00000
> +#define ARM_INST_LDRB_R		0x07d00000
> +#define ARM_INST_LDRH_I		0x01d000b0
> +#define ARM_INST_LDR_I		0x05900000
> +
> +#define ARM_INST_LDM		0x08900000
> +
> +#define ARM_INST_LSL_I		0x01a00000
> +#define ARM_INST_LSL_R		0x01a00010
> +
> +#define ARM_INST_LSR_I		0x01a00020
> +#define ARM_INST_LSR_R		0x01a00030
> +
> +#define ARM_INST_MOV_R		0x01a00000
> +#define ARM_INST_MOV_I		0x03a00000
> +#define ARM_INST_MOVW		0x03000000
> +#define ARM_INST_MOVT		0x03400000
> +
> +#define ARM_INST_MUL		0x00000090
> +
> +#define ARM_INST_POP		0x08bd0000
> +#define ARM_INST_PUSH		0x092d0000
> +
> +#define ARM_INST_ORR_R		0x01800000
> +#define ARM_INST_ORR_I		0x03800000
> +
> +#define ARM_INST_REV		0x06bf0f30
> +#define ARM_INST_REV16		0x06bf0fb0
> +
> +#define ARM_INST_RSB_I		0x02600000
> +
> +#define ARM_INST_SUB_R		0x00400000
> +#define ARM_INST_SUB_I		0x02400000
> +
> +#define ARM_INST_STR_I		0x05800000
> +
> +#define ARM_INST_TST_R		0x01100000
> +#define ARM_INST_TST_I		0x03100000
> +
> +#define ARM_INST_UDIV		0x0730f010
> +
> +#define ARM_INST_UMULL		0x00800090
> +
> +/* register */
> +#define _AL3_R(op, rd, rn, rm)	((op ## _R) | (rd) << 12 | (rn) << 16 | (rm))
> +/* immediate */
> +#define _AL3_I(op, rd, rn, imm)	((op ## _I) | (rd) << 12 | (rn) << 16 | (imm))
> +
> +#define ARM_ADD_R(rd, rn, rm)	_AL3_R(ARM_INST_ADD, rd, rn, rm)
> +#define ARM_ADD_I(rd, rn, imm)	_AL3_I(ARM_INST_ADD, rd, rn, imm)
> +
> +#define ARM_AND_R(rd, rn, rm)	_AL3_R(ARM_INST_AND, rd, rn, rm)
> +#define ARM_AND_I(rd, rn, imm)	_AL3_I(ARM_INST_AND, rd, rn, imm)
> +
> +#define ARM_BIC_R(rd, rn, rm)	_AL3_R(ARM_INST_BIC, rd, rn, rm)
> +#define ARM_BIC_I(rd, rn, imm)	_AL3_I(ARM_INST_BIC, rd, rn, imm)
> +
> +#define ARM_B(imm24)		(ARM_INST_B | ((imm24) & 0xffffff))
> +#define ARM_BX(rm)		(ARM_INST_BX | (rm))
> +#define ARM_BLX_R(rm)		(ARM_INST_BLX_R | (rm))
> +
> +#define ARM_CMP_R(rn, rm)	_AL3_R(ARM_INST_CMP, 0, rn, rm)
> +#define ARM_CMP_I(rn, imm)	_AL3_I(ARM_INST_CMP, 0, rn, imm)
> +
> +#define ARM_LDR_I(rt, rn, off)	(ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \
> +				 | (off))
> +#define ARM_LDRB_I(rt, rn, off)	(ARM_INST_LDRB_I | (rt) << 12 | (rn) << 16 \
> +				 | (off))
> +#define ARM_LDRB_R(rt, rn, rm)	(ARM_INST_LDRB_R | (rt) << 12 | (rn) << 16 \
> +				 | (rm))
> +#define ARM_LDRH_I(rt, rn, off)	(ARM_INST_LDRH_I | (rt) << 12 | (rn) << 16 \
> +				 | (((off) & 0xf0) << 4) | ((off) & 0xf))
> +
> +#define ARM_LDM(rn, regs)	(ARM_INST_LDM | (rn) << 16 | (regs))
> +
> +#define ARM_LSL_R(rd, rn, rm)	(_AL3_R(ARM_INST_LSL, rd, 0, rn) | (rm) << 8)
> +#define ARM_LSL_I(rd, rn, imm)	(_AL3_I(ARM_INST_LSL, rd, 0, rn) | (imm) << 7)
> +
> +#define ARM_LSR_R(rd, rn, rm)	(_AL3_R(ARM_INST_LSR, rd, 0, rn) | (rm) << 8)
> +#define ARM_LSR_I(rd, rn, imm)	(_AL3_I(ARM_INST_LSR, rd, 0, rn) | (imm) << 7)
> +
> +#define ARM_MOV_R(rd, rm)	_AL3_R(ARM_INST_MOV, rd, 0, rm)
> +#define ARM_MOV_I(rd, imm)	_AL3_I(ARM_INST_MOV, rd, 0, imm)
> +
> +#define ARM_MOVW(rd, imm)	\
> +	(ARM_INST_MOVW | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
> +
> +#define ARM_MOVT(rd, imm)	\
> +	(ARM_INST_MOVT | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
> +
> +#define ARM_MUL(rd, rm, rn)	(ARM_INST_MUL | (rd) << 16 | (rm) << 8 | (rn))
> +
> +#define ARM_POP(regs)		(ARM_INST_POP | (regs))
> +#define ARM_PUSH(regs)		(ARM_INST_PUSH | (regs))
> +
> +#define ARM_ORR_R(rd, rn, rm)	_AL3_R(ARM_INST_ORR, rd, rn, rm)
> +#define ARM_ORR_I(rd, rn, imm)	_AL3_I(ARM_INST_ORR, rd, rn, imm)
> +#define ARM_ORR_S(rd, rn, rm, type, rs)	\
> +	(ARM_ORR_R(rd, rn, rm) | (type) << 5 | (rs) << 7)
> +
> +#define ARM_REV(rd, rm)		(ARM_INST_REV | (rd) << 12 | (rm))
> +#define ARM_REV16(rd, rm)	(ARM_INST_REV16 | (rd) << 12 | (rm))
> +
> +#define ARM_RSB_I(rd, rn, imm)	_AL3_I(ARM_INST_RSB, rd, rn, imm)
> +
> +#define ARM_SUB_R(rd, rn, rm)	_AL3_R(ARM_INST_SUB, rd, rn, rm)
> +#define ARM_SUB_I(rd, rn, imm)	_AL3_I(ARM_INST_SUB, rd, rn, imm)
> +
> +#define ARM_STR_I(rt, rn, off)	(ARM_INST_STR_I | (rt) << 12 | (rn) << 16 \
> +				 | (off))
> +
> +#define ARM_TST_R(rn, rm)	_AL3_R(ARM_INST_TST, 0, rn, rm)
> +#define ARM_TST_I(rn, imm)	_AL3_I(ARM_INST_TST, 0, rn, imm)
> +
> +#define ARM_UDIV(rd, rn, rm)	(ARM_INST_UDIV | (rd) << 16 | (rn) | (rm) << 8)
> +
> +#define ARM_UMULL(rd_lo, rd_hi, rn, rm)	(ARM_INST_UMULL | (rd_hi) << 16 \
> +					 | (rd_lo) << 12 | (rm) << 8 | rn)
> +
> +#endif /* PFILTER_OPCODES_ARM_H */

Updated in the patch tracking system as 7259/3. Hopefully it's not too
late for the inclusion in 3.4.

Thanks,
Mircea


From sameo at linux.intel.com  Fri Mar 16 16:14:45 2012
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Fri, 16 Mar 2012 21:14:45 +0100
Subject: [PATCH v10] mfd: Add anatop mfd driver
In-Reply-To: <1331885816-26902-1-git-send-email-paul.liu@linaro.org>
References: <1331885816-26902-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120316201445.GV20524@sortiz-mobl>

Hi,

On Fri, Mar 16, 2012 at 04:16:56PM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is a mfd chip embedded in Freescale i.MX6Q SoC.
> Anatop provides regulators and thermal.
> This driver handles the address space and the operation of the mfd device.
I applied this one, thanks.

Cheers,
Samuel.

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From arnd at arndb.de  Fri Mar 16 16:09:47 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 20:09:47 +0000
Subject: [GIT PULL] [for v3.4] Pull request containing ux500 DT enablement
In-Reply-To: <4F62220D.1090106@linaro.org>
References: <4F62220D.1090106@linaro.org>
Message-ID: <201203162009.48239.arnd@arndb.de>

On Thursday 15 March 2012, Lee Jones wrote:
> The following changes since commit fff9a13341312c8d0f06e04c1345e855528b03da:
> 
>   ARM: ux500: CONFIG: Enable Device Tree support for future endeavours (2012-03-15 16:33:54 +0000)
> 
> are available in the git repository at:
>   git://git.linaro.org/people/ljones/linux-3.0-ux500.git device-tree-snowball-ux500
> 
> Arnd Bergmann (3):
>       ARM: ux500: Initial Device Tree support for Snowball
>       ARM: ux500: combine the board init functions for DT boot
>       ARM: ux500: split dts file for snowball into generic part
> 
> Lee Jones (5):
>       ARM: ux500: db8500: list most devices in the snowball device tree
>       ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt Controller) in Device Tree
>       ARM: ux500: Enable PL011 AMBA UART Controller for Device Tree
>       ARM: ux500: Enable PL310 Level 2 Cache Controller in Device Tree
>       ARM: ux500: Enable PL022 SSP Controller in Device Tree

I've pulled this into next/dt2, not next/dt for now. I had to rebase the patches
as we discussed and then did some build tests to make sure nothing broke. I found
one bug with your patches and CONFIG_OF disabled, which I fixed in the patch itself,
and found some build warnings that you should take a look at in the for-next
branch. Also the patch "CONFIG: Enable Device Tree support for future endeavours"
seems essential for the entire series, so I applied it as well, along with 
your localtime patch.

I still think we can make it for v3.4, but I'll let this sit in linux-next for a
few days longer than the other pull requests and if we find more problems it's out
and gets postponed till v3.5.

	Arnd


From eric.dumazet at gmail.com  Fri Mar 16 16:17:42 2012
From: eric.dumazet at gmail.com (Eric Dumazet)
Date: Fri, 16 Mar 2012 13:17:42 -0700
Subject: [PATCH v8] ARM: net: JIT compiler for packet filters
In-Reply-To: <4F639787.7070801@gmail.com>
References: <1331885844-30575-1-git-send-email-mgherzan@gmail.com>
 <4F639787.7070801@gmail.com>
Message-ID: <1331929062.19406.21.camel@edumazet-glaptop>

On Fri, 2012-03-16 at 20:41 +0100, Mircea Gherzan wrote:

> Updated in the patch tracking system as 7259/3. Hopefully it's not too
> late for the inclusion in 3.4.

What was the point of copy/pasting the whole mail ?




From arnd at arndb.de  Fri Mar 16 16:18:27 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 20:18:27 +0000
Subject: [PATCH 0/9 v5] ARM: kirkwood: fdt: convert kirkwood to fdt
In-Reply-To: <cover.1331868507.git.jason@lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <cover.1331868507.git.jason@lakedaemon.net>
Message-ID: <201203162018.27957.arnd@arndb.de>

On Friday 16 March 2012, Jason Cooper wrote:
> 
> This series continues the process of converting all of the drivers initialized
> from kirkwood_init() to devicetree.
> 
> The first three patches are code cleanup from Andrew Lunn and myself.
> 
> The next three patches are cleanup and prep to facilitate adding new boards
> during the transition to devicetree.
> 
> The next patch moves the uarts into the bus for all kirkwood boards and leaves
> enabling them and specifying clock-frequency up to the board file.
> 
> The rest of the series is the initial conversion of rtc-mv to devicetree since
> it  doesn't use tclk or pinmux.  These should be safe to merge as they won't
> interfere with the clk/clkdev work Andrew Lunn is working on.
> 
>
> Please be aware that this is a complete reshuffle of the whole series and is
> based purely against arm-soc/next/boards.

Is this a pull request for v3.4 or not? I'm willing to take it and have put
it into next/dt2 for now so it makes it into linux-next. I'm not taking
a newer version for v3.4 any more, so if anyone has concerns over some of
your patches in the series, it all gets removed again and we will have to
postpone them until v3.5.

Note that it would have been better to base your series on top of just
the kirkwood/board branch rather than all of next/boards, but it's not
a big deal.

	Arnd


From aneesh at ti.com  Fri Mar 16 16:19:37 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 01:49:37 +0530
Subject: [PATCH v3] misc: ddr: add LPDDR2 data from JESD209-2
In-Reply-To: <20120315190238.GD11142@kroah.com>
References: <20120315190238.GD11142@kroah.com>
Message-ID: <1331929177-11694-1-git-send-email-aneesh@ti.com>

add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:

1. Addressing information for LPDDR2 memories of different
   densities and types(S2/S4)
2. AC timing data.

This data will useful for memory controller device drivers

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v3:
- Converted EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
- Removed un-necessary newline

v1:
- Moved to /lib from /drivers/misc
- Corrected Copyright year
---
 include/misc/jedec_ddr.h |  177 ++++++++++++++++++++++++++++++++++++++++++++++
 lib/Kconfig              |    8 ++
 lib/Makefile             |    2 +
 lib/jedec_ddr_data.c     |  135 +++++++++++++++++++++++++++++++++++
 4 files changed, 322 insertions(+), 0 deletions(-)
 create mode 100644 include/misc/jedec_ddr.h
 create mode 100644 lib/jedec_ddr_data.c

diff --git a/include/misc/jedec_ddr.h b/include/misc/jedec_ddr.h
new file mode 100644
index 0000000..93ffd4a
--- /dev/null
+++ b/include/misc/jedec_ddr.h
@@ -0,0 +1,177 @@
+/*
+ * Definitions for DDR memories based on JEDEC specs
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_JEDEC_DDR_H
+#define __LINUX_JEDEC_DDR_H
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
+/* DDR Densities */
+#define DDR_DENSITY_64Mb	1
+#define DDR_DENSITY_128Mb	2
+#define DDR_DENSITY_256Mb	3
+#define DDR_DENSITY_512Mb	4
+#define DDR_DENSITY_1Gb		5
+#define DDR_DENSITY_2Gb		6
+#define DDR_DENSITY_4Gb		7
+#define DDR_DENSITY_8Gb		8
+#define DDR_DENSITY_16Gb	9
+#define DDR_DENSITY_32Gb	10
+
+/* DDR type */
+#define DDR_TYPE_DDR2		1
+#define DDR_TYPE_DDR3		2
+#define DDR_TYPE_LPDDR2_S4	3
+#define DDR_TYPE_LPDDR2_S2	4
+#define DDR_TYPE_LPDDR2_NVM	5
+
+/* DDR IO width */
+#define DDR_IO_WIDTH_4		1
+#define DDR_IO_WIDTH_8		2
+#define DDR_IO_WIDTH_16		3
+#define DDR_IO_WIDTH_32		4
+
+/* Number of Row bits */
+#define R9			9
+#define R10			10
+#define R11			11
+#define R12			12
+#define R13			13
+#define R14			14
+#define R15			15
+#define R16			16
+
+/* Number of Column bits */
+#define C7			7
+#define C8			8
+#define C9			9
+#define C10			10
+#define C11			11
+#define C12			12
+
+/* Number of Banks */
+#define B1			0
+#define B2			1
+#define B4			2
+#define B8			3
+
+/* Refresh rate in nano-seconds */
+#define T_REFI_15_6		15600
+#define T_REFI_7_8		7800
+#define T_REFI_3_9		3900
+
+/* tRFC values */
+#define T_RFC_90		90000
+#define T_RFC_110		110000
+#define T_RFC_130		130000
+#define T_RFC_160		160000
+#define T_RFC_210		210000
+#define T_RFC_300		300000
+#define T_RFC_350		350000
+
+/* Mode register numbers */
+#define DDR_MR0			0
+#define DDR_MR1			1
+#define DDR_MR2			2
+#define DDR_MR3			3
+#define DDR_MR4			4
+#define DDR_MR5			5
+#define DDR_MR6			6
+#define DDR_MR7			7
+#define DDR_MR8			8
+#define DDR_MR9			9
+#define DDR_MR10		10
+#define DDR_MR11		11
+#define DDR_MR16		16
+#define DDR_MR17		17
+#define DDR_MR18		18
+
+/*
+ * LPDDR2 related defines
+ */
+
+/* MR4 register fields */
+#define MR4_SDRAM_REF_RATE_SHIFT			0
+#define MR4_SDRAM_REF_RATE_MASK				7
+#define MR4_TUF_SHIFT					7
+#define MR4_TUF_MASK					(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define NUM_DDR_ADDR_TABLE_ENTRIES			11
+#define NUM_DDR_TIMING_TABLE_ENTRIES			4
+
+/* Structure for DDR addressing info from the JEDEC spec */
+struct lpddr2_addressing {
+	u32 num_banks;
+	u32 tREFI_ns;
+	u32 tRFCab_ps;
+};
+
+/*
+ * Structure for timings from the LPDDR2 datasheet
+ * All parameters are in pico seconds(ps) unless explicitly indicated
+ * with a suffix like tRAS_max_ns below
+ */
+struct lpddr2_timings {
+	u32 max_freq;
+	u32 min_freq;
+	u32 tRPab;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_min;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u32 tCKESR;
+	u32 tDQSCK_max;
+	u32 tDQSCK_max_derated;
+	u32 tFAW;
+	u32 tZQCS;
+	u32 tZQCL;
+	u32 tZQinit;
+	u32 tRAS_max_ns;
+};
+
+/*
+ * Min value for some parameters in terms of number of tCK cycles(nCK)
+ * Please set to zero parameters that are not valid for a given memory
+ * type
+ */
+struct lpddr2_min_tck {
+	u32 tRPab;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRASmin;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u32 tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+extern const struct lpddr2_addressing
+	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES];
+extern const struct lpddr2_timings
+	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
+extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
+#endif /* __ASSEMBLY__ */
+
+#endif /* __LINUX_JEDEC_DDR_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index 028aba9..c5d4f1f 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -291,6 +291,14 @@ config CORDIC
 	  This option provides an implementation of the CORDIC algorithm;
 	  calculations are in fixed point. Module will be called cordic.
 
+config DDR
+	bool "JEDEC DDR data"
+	help
+	  Data from JEDEC specs for DDR SDRAM memories,
+	  particularly the AC timing parameters and addressing
+	  information. This data is useful for drivers handling
+	  DDR SDRAM controllers.
+
 config MPILIB
 	tristate
 	select CLZ_TAB
diff --git a/lib/Makefile b/lib/Makefile
index 18515f0..74290c9 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -123,6 +123,8 @@ obj-$(CONFIG_SIGNATURE) += digsig.o
 
 obj-$(CONFIG_CLZ_TAB) += clz_tab.o
 
+obj-$(CONFIG_DDR) += jedec_ddr_data.o
+
 hostprogs-y	:= gen_crc32table
 clean-files	:= crc32table.h
 
diff --git a/lib/jedec_ddr_data.c b/lib/jedec_ddr_data.c
new file mode 100644
index 0000000..498c78f
--- /dev/null
+++ b/lib/jedec_ddr_data.c
@@ -0,0 +1,135 @@
+/*
+ * DDR addressing details and AC timing parameters from JEDEC specs
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <misc/jedec_ddr.h>
+#include <linux/module.h>
+
+/* LPDDR2 addressing details from JESD209-2 section 2.4 */
+const struct lpddr2_addressing
+	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
+	{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
+	{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
+	{B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
+	{B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
+	{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
+	{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
+	{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
+	{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
+	{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
+	{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
+};
+EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
+
+/* LPDDR2 AC timing parameters from JESD209-2 section 12 */
+const struct lpddr2_timings
+	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
+	/* Speed bin 400(200 MHz) */
+	[0] = {
+		.max_freq	= 200000000,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 10000,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 533(266 MHz) */
+	[1] = {
+		.max_freq	= 266666666,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 800(400 MHz) */
+	[2] = {
+		.max_freq	= 400000000,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 1066(533 MHz) */
+	[3] = {
+		.max_freq	= 533333333,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 5620,
+	},
+};
+EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
+
+const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
+	.tRPab		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRASmin	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
-- 
1.7.1



From mgherzan at gmail.com  Fri Mar 16 16:22:30 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Fri, 16 Mar 2012 21:22:30 +0100
Subject: [PATCH v8] ARM: net: JIT compiler for packet filters
In-Reply-To: <1331929062.19406.21.camel@edumazet-glaptop>
References: <1331885844-30575-1-git-send-email-mgherzan@gmail.com>
 <4F639787.7070801@gmail.com> <1331929062.19406.21.camel@edumazet-glaptop>
Message-ID: <4F63A106.9060603@gmail.com>

Am 16.03.2012 21:17, schrieb Eric Dumazet:
> On Fri, 2012-03-16 at 20:41 +0100, Mircea Gherzan wrote:
> 
>> Updated in the patch tracking system as 7259/3. Hopefully it's not too
>> late for the inclusion in 3.4.
> 
> What was the point of copy/pasting the whole mail ?

I forgot to cc netdev in the first mail. Sorry.

Mircea


From jason at lakedaemon.net  Fri Mar 16 16:28:15 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 16:28:15 -0400
Subject: [PATCH 0/9 v5] ARM: kirkwood: fdt: convert kirkwood to fdt
In-Reply-To: <201203162018.27957.arnd@arndb.de>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <cover.1331868507.git.jason@lakedaemon.net>
 <201203162018.27957.arnd@arndb.de>
Message-ID: <20120316202815.GI20243@titan.lakedaemon.net>

On Fri, Mar 16, 2012 at 08:18:27PM +0000, Arnd Bergmann wrote:
> On Friday 16 March 2012, Jason Cooper wrote:
> > 
> > This series continues the process of converting all of the drivers initialized
> > from kirkwood_init() to devicetree.
> > 
> > The first three patches are code cleanup from Andrew Lunn and myself.
> > 
> > The next three patches are cleanup and prep to facilitate adding new boards
> > during the transition to devicetree.
> > 
> > The next patch moves the uarts into the bus for all kirkwood boards and leaves
> > enabling them and specifying clock-frequency up to the board file.
> > 
> > The rest of the series is the initial conversion of rtc-mv to devicetree since
> > it  doesn't use tclk or pinmux.  These should be safe to merge as they won't
> > interfere with the clk/clkdev work Andrew Lunn is working on.
> > 
> >
> > Please be aware that this is a complete reshuffle of the whole series and is
> > based purely against arm-soc/next/boards.
> 
> Is this a pull request for v3.4 or not?

I was going to give it a day or two more, and if no one brought up
anything earth-shattering, I was going to submit the pull-request for
this series on Sunday.  I can do it now if you think it's ok.

> I'm willing to take it and have put it into next/dt2 for now so it
> makes it into linux-next. I'm not taking a newer version for v3.4 any
> more, so if anyone has concerns over some of your patches in the
> series, it all gets removed again and we will have to postpone them
> until v3.5.

The problematic patch (sata_mv) has been removed.  So, there should be
no issue.

> Note that it would have been better to base your series on top of just
> the kirkwood/board branch rather than all of next/boards, but it's not
> a big deal.

Ok.

thx,

Jason.


From kgene.kim at samsung.com  Fri Mar 16 16:30:22 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 16 Mar 2012 13:30:22 -0700
Subject: [GIT PULL] Samsung SoC EXYNOS5250 arch for v3.4
In-Reply-To: <201203161250.11353.arnd@arndb.de>
References: <4F61FA0D.1050007@samsung.com> <201203161250.11353.arnd@arndb.de>
Message-ID: <4F63A2DE.7070705@samsung.com>

Arnd Bergmann wrote:

[...]

>
> As you may have noticed from Stephen's notification about the merge
> conflict, I have put this into the next/soc2 branch now.
>
Yes, thanks.

> I'm not too happy with the resolution of my comments, but in the

Hmm, sorry about that.

> end I think it's better to have it in the tree than not have it.
> While you did reply with explanations for why some of the patches
> were necessary, you did not actually put the explanations into
> the changeset descriptions but only sent a reply to my emails.

Oh, I see. If similar case will happen next time, let me expand its 
descritpions.

>
> I don't think that the merge conflict is problematic, especially
> since Linus won't see the same thing that Stephen did, but as I
> wrote in the other mail, please check that my resolution was correct.
>
Yes, as I replied, I think your resolution and Stehpehn's one, both are 
correct to me and just different postion of 'int ret'. As a note, I just 
fixed it up with yours.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From arnd at arndb.de  Fri Mar 16 16:31:55 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 20:31:55 +0000
Subject: [PATCH v5] ARM: SPEAr600: Add device-tree support to SPEAr600
 boards
In-Reply-To: <20120316131129.GH7757@game.jcrosoft.org>
References: <1331903003-14045-1-git-send-email-sr@denx.de>
 <20120316131129.GH7757@game.jcrosoft.org>
Message-ID: <201203162031.56051.arnd@arndb.de>

On Friday 16 March 2012, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > 
> > Signed-off-by: Stefan Roese <sr at denx.de>
> > Acked-by: Viresh Kumar <viresh.kumar at st.com>
> > Cc: Arnd Bergmann <arnd at arndb.de>
> > Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> 
> 
> I'm not a fan to have non Documented DT binding butthey are basic so ok
> 

I've applied the patch to the next/dt2 branch now, which means it
will get sent later than the first batch of dt conversions and
we have some time to let this get tested in linux-next, but the
plan is still to have it in v3.4.

With this, it seems that SPEAr600 will be the surprise winner in the
race to have the first platform that removes all of its board files
and replaces them with DT probing ;-)

Thanks everyone!

	Arnd


From arnd at arndb.de  Fri Mar 16 16:41:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 20:41:12 +0000
Subject: [PATCH 0/9 v5] ARM: kirkwood: fdt: convert kirkwood to fdt
In-Reply-To: <20120316202815.GI20243@titan.lakedaemon.net>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203162018.27957.arnd@arndb.de>
 <20120316202815.GI20243@titan.lakedaemon.net>
Message-ID: <201203162041.12831.arnd@arndb.de>

On Friday 16 March 2012, Jason Cooper wrote:
> I was going to give it a day or two more, and if no one brought up
> anything earth-shattering, I was going to submit the pull-request for
> this series on Sunday.  I can do it now if you think it's ok.

I've already pulled it now, and I'm not going to take any new patches
for v3.4 any more. I expect Linus to open up the merge window
any time now, and he does not like to see patches sent to him
that have not been in linux-next before the merge window opened.

So the deal is that anything that is in now stays in unless someone
reports a serious problem and in that case it gets removed.
Any simple bugs can be fixed by sending follow-up patches of
course.

> > I'm willing to take it and have put it into next/dt2 for now so it
> > makes it into linux-next. I'm not taking a newer version for v3.4 any
> > more, so if anyone has concerns over some of your patches in the
> > series, it all gets removed again and we will have to postpone them
> > until v3.5.
> 
> The problematic patch (sata_mv) has been removed.  So, there should be
> no issue.

Ok, thanks for the confirmation.

	Arnd


From kgene.kim at samsung.com  Fri Mar 16 16:47:50 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 16 Mar 2012 13:47:50 -0700
Subject: [PATCH v12 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
In-Reply-To: <4F630841.2070307@linaro.org>
References: <000201cd0286$2e6fbb40$8b4f31c0$%cho@samsung.com>
 <20120315111227.GA2384@amd.com> <4F61FF1D.5000502@samsung.com>
 <4F630841.2070307@linaro.org>
Message-ID: <4F63A6F6.9050506@samsung.com>

Subash Patel wrote:
> Hi KyongHo, Kukjin,
>
> On 03/15/2012 08:09 PM, Kukjin Kim wrote:
>> On 03/15/12 04:12, Joerg Roedel wrote:
>>> On Thu, Mar 15, 2012 at 05:32:39PM +0900, Cho KyongHo wrote:
>>
>> KyongHo, I looked at 'Cho KyongHo <pullip.cho ...>' and 'KyongHo Cho
>> <pullip.cho ...>' in this series, which one do you want to use?
>>
>>>> Handling System MMUs with an identifier is not flexible to manage
>>>> System MMU platform devices because of the following reasons:
>>>> 1. A device driver which needs to handle System MMU must know the ID.
>>>> 2. A System MMU may not present in some implementations of Exynos
>>>> family.
>>>> 3. Handling System MMU with IOMMU API does not require an ID.
>>>>
>>>> This patch is the result of removing ID of System MMUs.
>>>> Instead, a device driver that needs to handle its System MMU must
>>>> use IOMMU API while its descriptor of platform device is given.
>>>>
>>>> This patch also includes the following enhancements:
>>>> - A System MMU device becomes a child if its power domain device.
>>>> - clkdev
>>>>
>>>> Cc: Kukjin Kim<kgene.kim at samsung.com>
>>>> Signed-off-by: KyongHo Cho<pullip.cho at samsung.com>
>>>> ---
>>>> arch/arm/mach-exynos/Kconfig | 10 +-
>>>> arch/arm/mach-exynos/Makefile | 2 +-
>>>> arch/arm/mach-exynos/clock-exynos4.c | 79 ++--
>>>> arch/arm/mach-exynos/clock-exynos4.h | 2 +
>>>> arch/arm/mach-exynos/clock-exynos4210.c | 11 +
>>>> arch/arm/mach-exynos/clock-exynos4212.c | 28 ++-
>>>> arch/arm/mach-exynos/clock-exynos5.c | 90 +++++
>>>> arch/arm/mach-exynos/dev-sysmmu.c | 457 ++++++++++++----------
>>>> arch/arm/mach-exynos/include/mach/irqs.h | 25 +-
>>>> arch/arm/mach-exynos/include/mach/map.h | 38 ++
>>>> arch/arm/mach-exynos/include/mach/regs-clock.h | 5 +
>>>> arch/arm/mach-exynos/include/mach/regs-sysmmu.h | 28 --
>>>> arch/arm/mach-exynos/include/mach/sysmmu.h | 88 +++--
>>>> arch/arm/mach-exynos/mach-armlex4210.c | 1 -
>>>> arch/arm/mach-exynos/mach-smdkv310.c | 1 -
>>>> 15 files changed, 529 insertions(+), 336 deletions(-)
>>>> delete mode 100644 arch/arm/mach-exynos/include/mach/regs-sysmmu.h
>>>
>>> This patch doesn't apply cleanly against upstream Linux (v3.3-rcX).
>>> Please rebase to upstream and resend. The other 2 patches apply fine.
>>>
>>
>> Yes, as KyoungHo said, this has been created on top of Samsung tree
>> for-next because this touches many exynos stuff which has been changed
>> from Samsung tree for upcoming merge window. So if you're ok on this,
>> 1st patch and this should be sent to upstream via samsung tree even
>> though I can't find any topic branch for this yet. And if you want
>> topic branch for your tree, let me know, I can provide it.
>>
>> Thanks.
> Wouldn't it be good to send exynos4 SYSMMU patches now, and send only
> the exynos5 delta when your for-next(exynos5) changes

Hmm, it can be a solution for this, but I'm not sure exynos4 and exynos5 
can be splitted.

> get merged to mainline? Manually editing the patches is really pain-some

YES, absolutely. Nobody like it.

> and sometimes error-some :( Can this patch in particular
> be split?

Hmm...

Now we don't have much time for upcoming merge window, and this should 
be in linux-next before open merge window.

Anyway Joerg, how do you want to handle this? Do you want to pick up 
1/2/3 all of them in your tree? If so, 2nd patch should be on top of 
some samsung topic stuff.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From aneesh at ti.com  Fri Mar 16 16:50:07 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 02:20:07 +0530
Subject: [PATCH v4] misc: ddr: add LPDDR2 data from JESD209-2
In-Reply-To: <1331929177-11694-1-git-send-email-aneesh@ti.com>
References: <1331929177-11694-1-git-send-email-aneesh@ti.com>
Message-ID: <1331931007-584-1-git-send-email-aneesh@ti.com>

add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:

1. Addressing information for LPDDR2 memories of different
   densities and types(S2/S4)
2. AC timing data.

This data will useful for memory controller device drivers.
Right now this is used by the TI EMIF SDRAM controller
driver.

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v4:
- Removed 'ifndef __ASSEMBLY__' from jedec_ddr.h
- Updated commit log to be more specific on where
  this patch is used currently

v3:
- Converted EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
- Removed un-necessary newline

v1:
- Moved to /lib from /drivers/misc
- Corrected Copyright year
---
 include/misc/jedec_ddr.h |  175 ++++++++++++++++++++++++++++++++++++++++++++++
 lib/Kconfig              |    8 ++
 lib/Makefile             |    2 +
 lib/jedec_ddr_data.c     |  135 +++++++++++++++++++++++++++++++++++
 4 files changed, 320 insertions(+), 0 deletions(-)
 create mode 100644 include/misc/jedec_ddr.h
 create mode 100644 lib/jedec_ddr_data.c

diff --git a/include/misc/jedec_ddr.h b/include/misc/jedec_ddr.h
new file mode 100644
index 0000000..ddad0f8
--- /dev/null
+++ b/include/misc/jedec_ddr.h
@@ -0,0 +1,175 @@
+/*
+ * Definitions for DDR memories based on JEDEC specs
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_JEDEC_DDR_H
+#define __LINUX_JEDEC_DDR_H
+
+#include <linux/types.h>
+
+/* DDR Densities */
+#define DDR_DENSITY_64Mb	1
+#define DDR_DENSITY_128Mb	2
+#define DDR_DENSITY_256Mb	3
+#define DDR_DENSITY_512Mb	4
+#define DDR_DENSITY_1Gb		5
+#define DDR_DENSITY_2Gb		6
+#define DDR_DENSITY_4Gb		7
+#define DDR_DENSITY_8Gb		8
+#define DDR_DENSITY_16Gb	9
+#define DDR_DENSITY_32Gb	10
+
+/* DDR type */
+#define DDR_TYPE_DDR2		1
+#define DDR_TYPE_DDR3		2
+#define DDR_TYPE_LPDDR2_S4	3
+#define DDR_TYPE_LPDDR2_S2	4
+#define DDR_TYPE_LPDDR2_NVM	5
+
+/* DDR IO width */
+#define DDR_IO_WIDTH_4		1
+#define DDR_IO_WIDTH_8		2
+#define DDR_IO_WIDTH_16		3
+#define DDR_IO_WIDTH_32		4
+
+/* Number of Row bits */
+#define R9			9
+#define R10			10
+#define R11			11
+#define R12			12
+#define R13			13
+#define R14			14
+#define R15			15
+#define R16			16
+
+/* Number of Column bits */
+#define C7			7
+#define C8			8
+#define C9			9
+#define C10			10
+#define C11			11
+#define C12			12
+
+/* Number of Banks */
+#define B1			0
+#define B2			1
+#define B4			2
+#define B8			3
+
+/* Refresh rate in nano-seconds */
+#define T_REFI_15_6		15600
+#define T_REFI_7_8		7800
+#define T_REFI_3_9		3900
+
+/* tRFC values */
+#define T_RFC_90		90000
+#define T_RFC_110		110000
+#define T_RFC_130		130000
+#define T_RFC_160		160000
+#define T_RFC_210		210000
+#define T_RFC_300		300000
+#define T_RFC_350		350000
+
+/* Mode register numbers */
+#define DDR_MR0			0
+#define DDR_MR1			1
+#define DDR_MR2			2
+#define DDR_MR3			3
+#define DDR_MR4			4
+#define DDR_MR5			5
+#define DDR_MR6			6
+#define DDR_MR7			7
+#define DDR_MR8			8
+#define DDR_MR9			9
+#define DDR_MR10		10
+#define DDR_MR11		11
+#define DDR_MR16		16
+#define DDR_MR17		17
+#define DDR_MR18		18
+
+/*
+ * LPDDR2 related defines
+ */
+
+/* MR4 register fields */
+#define MR4_SDRAM_REF_RATE_SHIFT			0
+#define MR4_SDRAM_REF_RATE_MASK				7
+#define MR4_TUF_SHIFT					7
+#define MR4_TUF_MASK					(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define NUM_DDR_ADDR_TABLE_ENTRIES			11
+#define NUM_DDR_TIMING_TABLE_ENTRIES			4
+
+/* Structure for DDR addressing info from the JEDEC spec */
+struct lpddr2_addressing {
+	u32 num_banks;
+	u32 tREFI_ns;
+	u32 tRFCab_ps;
+};
+
+/*
+ * Structure for timings from the LPDDR2 datasheet
+ * All parameters are in pico seconds(ps) unless explicitly indicated
+ * with a suffix like tRAS_max_ns below
+ */
+struct lpddr2_timings {
+	u32 max_freq;
+	u32 min_freq;
+	u32 tRPab;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_min;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u32 tCKESR;
+	u32 tDQSCK_max;
+	u32 tDQSCK_max_derated;
+	u32 tFAW;
+	u32 tZQCS;
+	u32 tZQCL;
+	u32 tZQinit;
+	u32 tRAS_max_ns;
+};
+
+/*
+ * Min value for some parameters in terms of number of tCK cycles(nCK)
+ * Please set to zero parameters that are not valid for a given memory
+ * type
+ */
+struct lpddr2_min_tck {
+	u32 tRPab;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRASmin;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u32 tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+extern const struct lpddr2_addressing
+	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES];
+extern const struct lpddr2_timings
+	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
+extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
+
+#endif /* __LINUX_JEDEC_DDR_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index 028aba9..c5d4f1f 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -291,6 +291,14 @@ config CORDIC
 	  This option provides an implementation of the CORDIC algorithm;
 	  calculations are in fixed point. Module will be called cordic.
 
+config DDR
+	bool "JEDEC DDR data"
+	help
+	  Data from JEDEC specs for DDR SDRAM memories,
+	  particularly the AC timing parameters and addressing
+	  information. This data is useful for drivers handling
+	  DDR SDRAM controllers.
+
 config MPILIB
 	tristate
 	select CLZ_TAB
diff --git a/lib/Makefile b/lib/Makefile
index 18515f0..74290c9 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -123,6 +123,8 @@ obj-$(CONFIG_SIGNATURE) += digsig.o
 
 obj-$(CONFIG_CLZ_TAB) += clz_tab.o
 
+obj-$(CONFIG_DDR) += jedec_ddr_data.o
+
 hostprogs-y	:= gen_crc32table
 clean-files	:= crc32table.h
 
diff --git a/lib/jedec_ddr_data.c b/lib/jedec_ddr_data.c
new file mode 100644
index 0000000..498c78f
--- /dev/null
+++ b/lib/jedec_ddr_data.c
@@ -0,0 +1,135 @@
+/*
+ * DDR addressing details and AC timing parameters from JEDEC specs
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <misc/jedec_ddr.h>
+#include <linux/module.h>
+
+/* LPDDR2 addressing details from JESD209-2 section 2.4 */
+const struct lpddr2_addressing
+	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
+	{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
+	{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
+	{B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
+	{B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
+	{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
+	{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
+	{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
+	{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
+	{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
+	{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
+};
+EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
+
+/* LPDDR2 AC timing parameters from JESD209-2 section 12 */
+const struct lpddr2_timings
+	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
+	/* Speed bin 400(200 MHz) */
+	[0] = {
+		.max_freq	= 200000000,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 10000,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 533(266 MHz) */
+	[1] = {
+		.max_freq	= 266666666,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 800(400 MHz) */
+	[2] = {
+		.max_freq	= 400000000,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 1066(533 MHz) */
+	[3] = {
+		.max_freq	= 533333333,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 5620,
+	},
+};
+EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
+
+const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
+	.tRPab		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRASmin	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
-- 
1.7.1



From davem at davemloft.net  Fri Mar 16 16:54:03 2012
From: davem at davemloft.net (David Miller)
Date: Fri, 16 Mar 2012 13:54:03 -0700 (PDT)
Subject: [PATCH v8] ARM: net: JIT compiler for packet filters
In-Reply-To: <4F63A106.9060603@gmail.com>
References: <4F639787.7070801@gmail.com>
 <1331929062.19406.21.camel@edumazet-glaptop>
 <4F63A106.9060603@gmail.com>
Message-ID: <20120316.135403.1245702993058109595.davem@davemloft.net>

From: Mircea Gherzan <mgherzan at gmail.com>
Date: Fri, 16 Mar 2012 21:22:30 +0100

> Am 16.03.2012 21:17, schrieb Eric Dumazet:
>> On Fri, 2012-03-16 at 20:41 +0100, Mircea Gherzan wrote:
>> 
>>> Updated in the patch tracking system as 7259/3. Hopefully it's not too
>>> late for the inclusion in 3.4.
>> 
>> What was the point of copy/pasting the whole mail ?
> 
> I forgot to cc netdev in the first mail. Sorry.

That doesn't work, if you just quote the patch then it doesn't
get picked up by patchwork at all.

You have to make a real, fresh, patch postings for it to get
logged correctly.


From arnd at arndb.de  Fri Mar 16 16:57:58 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 16 Mar 2012 20:57:58 +0000
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <201203161218.05125.arnd.bergmann@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
Message-ID: <201203162057.58706.arnd@arndb.de>

On Friday 16 March 2012, Arnd Bergmann wrote:
> > 
> > Can we shoe-horn this thing into 3.4 (it is a bit late, i know) so
> > that platform ports can gather speed? Several people are waiting for a
> > somewhat stable version before starting their ports.
> > 
> > And what is the path into mainline - will Russell carry it or Arnd
> > (with Russell's blessing)?
> 
> I would suggest putting it into a late/* branch of arm-soc so it finally
> gets some linux-next exposure, and then sending it in the second week of the
> merge window.
> 
> Russell, please let me know if you want to carry it instead or if you
> have found any last-minute show stoppers in the code.

FWIW, it's in arm-soc now, and it's the last thing I  put in there
for v3.4. From now on until v3.4-rc1, feature patches can only get
removed from arm-soc, not added.

	Arnd


From aneesh at ti.com  Fri Mar 16 16:58:47 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 02:28:47 +0530
Subject: [PATCH v2 1/7] misc: ddr: add LPDDR2 data from JESD209-2
In-Reply-To: <20120315190238.GD11142@kroah.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
 <1331835457-5390-2-git-send-email-aneesh@ti.com>
 <20120315190238.GD11142@kroah.com>
Message-ID: <4F63A987.3@ti.com>

Hi Greg,

On Friday 16 March 2012 12:32 AM, Greg KH wrote:
> On Thu, Mar 15, 2012 at 11:47:31PM +0530, Aneesh V wrote:
>> add LPDDR2 data from the JEDEC spec JESD209-2. The data
>> includes:
>>
>> 1. Addressing information for LPDDR2 memories of different
>>     densities and types(S2/S4)
>> 2. AC timing data.
>>
>> This data will useful for memory controller device drivers
>
> Right now, only one driver, right?
>
>> +#ifndef __ASSEMBLY__
>
> Why is this needed?
>
>> +/* Structure for DDR addressing info from the JEDEC spec */
>> +struct lpddr2_addressing {
>> +	u32 num_banks;
>> +	u32 tREFI_ns;
>> +	u32 tRFCab_ps;
>> +};
>
> Do these structures cross the user/kernel boundry somehow?  If so,
> please use the proper kernel types for this.
>
>> --- a/lib/Makefile
>> +++ b/lib/Makefile
>> @@ -123,6 +123,9 @@ obj-$(CONFIG_SIGNATURE) += digsig.o
>>
>>   obj-$(CONFIG_CLZ_TAB) += clz_tab.o
>>
>> +obj-$(CONFIG_DDR) += jedec_ddr_data.o
>> +
>> +
>
> Why the extra line?
>
>>   hostprogs-y	:= gen_crc32table
>>   clean-files	:= crc32table.h
>>
>> diff --git a/lib/jedec_ddr_data.c b/lib/jedec_ddr_data.c
>> new file mode 100644
>> index 0000000..fc223d6
>> --- /dev/null
>> +++ b/lib/jedec_ddr_data.c
>> @@ -0,0 +1,135 @@
>> +/*
>> + * DDR addressing details and AC timing parameters from JEDEC specs
>> + *
>> + * Copyright (C) 2012 Texas Instruments, Inc.
>> + *
>> + * Aneesh V<aneesh at ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include<misc/jedec_ddr.h>
>> +#include<linux/module.h>
>> +
>> +/* LPDDR2 addressing details from JESD209-2 section 2.4 */
>> +const struct lpddr2_addressing
>> +	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
>> +	{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
>> +	{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
>> +	{B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
>> +	{B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
>> +	{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
>> +	{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
>> +	{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
>> +	{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
>> +	{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
>> +	{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
>> +};
>> +EXPORT_SYMBOL(lpddr2_jedec_addressing_table);
>
> EXPORT_SYMBOL_GPL for these and the others?

I have fixed these comments and pushed my latest patches at:
git://github.com/aneeshv/linux.git
branch: emif-upstream-v4

thanks,
Aneesh



From jason at lakedaemon.net  Fri Mar 16 17:02:29 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 16 Mar 2012 17:02:29 -0400
Subject: [PATCH 0/9 v5] ARM: kirkwood: fdt: convert kirkwood to fdt
In-Reply-To: <201203162041.12831.arnd@arndb.de>
References: <cover.1330625877.git.jason@lakedaemon.net>
 <201203162018.27957.arnd@arndb.de>
 <20120316202815.GI20243@titan.lakedaemon.net>
 <201203162041.12831.arnd@arndb.de>
Message-ID: <20120316210229.GJ20243@titan.lakedaemon.net>

On Fri, Mar 16, 2012 at 08:41:12PM +0000, Arnd Bergmann wrote:
> On Friday 16 March 2012, Jason Cooper wrote:
> > I was going to give it a day or two more, and if no one brought up
> > anything earth-shattering, I was going to submit the pull-request for
> > this series on Sunday.  I can do it now if you think it's ok.
> 
> I've already pulled it now, and I'm not going to take any new patches
> for v3.4 any more. I expect Linus to open up the merge window
> any time now, and he does not like to see patches sent to him
> that have not been in linux-next before the merge window opened.

Ahhh  That explains some things.

Thanks,

Jason.


From swarren at wwwdotorg.org  Fri Mar 16 17:03:55 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 16 Mar 2012 15:03:55 -0600
Subject: [PATCH] Kbuild: centralize MKIMAGE and cmd_uimage definitions
Message-ID: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>

All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
to avoid duplication.

All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
parameterized version in Makefile.lib to avoid duplication.

Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
---
v2:
* Fix blackfin's UIMAGE_LOADADDR in the ROMKERNEL case.
* Fix missing ) on a variable reference in avr32 and sparc.
* Only set those UIMAGE_* variables that the arch-specific Makefile hasn't
  already set.
* The patch series is now just this single patch which removes duplication;
  I've dropped the Kconfig feature to allow use of -T kernel_noload for
  now, since it looks like U-Boot is gaining direct zImage support.

 arch/arm/boot/Makefile          |   23 +++++++++--------------
 arch/avr32/boot/images/Makefile |    9 +++------
 arch/blackfin/boot/Makefile     |   19 ++++++++-----------
 arch/microblaze/boot/Makefile   |   10 +++-------
 arch/sh/boot/Makefile           |    8 ++------
 arch/sparc/boot/Makefile        |    9 +++------
 arch/unicore32/boot/Makefile    |   12 ++----------
 scripts/Makefile.lib            |   24 ++++++++++++++++++++++++
 8 files changed, 54 insertions(+), 60 deletions(-)

diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index fc871e7..c877087 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -11,8 +11,6 @@
 # Copyright (C) 1995-2002 Russell King
 #
 
-MKIMAGE         := $(srctree)/scripts/mkuboot.sh
-
 ifneq ($(MACHINE),)
 include $(srctree)/$(MACHINE)/Makefile.boot
 endif
@@ -69,22 +67,19 @@ $(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
 
 clean-files := *.dtb
 
-quiet_cmd_uimage = UIMAGE  $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
-		   -C none -a $(LOADADDR) -e $(STARTADDR) \
-		   -n 'Linux-$(KERNELRELEASE)' -d $< $@
-
-ifeq ($(CONFIG_ZBOOT_ROM),y)
-$(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
+ifneq ($(LOADADDR),)
+  UIMAGE_LOADADDR=$(LOADADDR)
 else
-$(obj)/uImage: LOADADDR=$(ZRELADDR)
+  ifeq ($(CONFIG_ZBOOT_ROM),y)
+    UIMAGE_LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
+  else
+    UIMAGE_LOADADDR=$(ZRELADDR)
+  endif
 endif
 
-$(obj)/uImage: STARTADDR=$(LOADADDR)
-
 check_for_multiple_loadaddr = \
-if [ $(words $(LOADADDR)) -gt 1 ]; then \
-	echo 'multiple load addresses: $(LOADADDR)'; \
+if [ $(words $(UIMAGE_LOADADDR)) -gt 1 ]; then \
+	echo 'multiple load addresses: $(UIMAGE_LOADADDR)'; \
 	echo 'This is incompatible with uImages'; \
 	echo 'Specify LOADADDR on the commandline to build an uImage'; \
 	false; \
diff --git a/arch/avr32/boot/images/Makefile b/arch/avr32/boot/images/Makefile
index 1848bf0..2a3b539 100644
--- a/arch/avr32/boot/images/Makefile
+++ b/arch/avr32/boot/images/Makefile
@@ -6,8 +6,6 @@
 # for more details.
 #
 
-MKIMAGE		:= $(srctree)/scripts/mkuboot.sh
-
 extra-y		:= vmlinux.bin vmlinux.gz
 
 OBJCOPYFLAGS_vmlinux.bin := -O binary -R .note.gnu.build-id
@@ -17,10 +15,9 @@ $(obj)/vmlinux.bin: vmlinux FORCE
 $(obj)/vmlinux.gz: $(obj)/vmlinux.bin FORCE
 	$(call if_changed,gzip)
 
-quiet_cmd_uimage = UIMAGE $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A avr32 -O linux -T kernel	\
-		-C gzip -a $(CONFIG_LOAD_ADDRESS) -e $(CONFIG_ENTRY_ADDRESS)	\
-		-n 'Linux-$(KERNELRELEASE)' -d $< $@
+UIMAGE_LOADADDR = $(CONFIG_LOAD_ADDRESS)
+UIMAGE_ENTRYADDR = $(CONFIG_ENTRY_ADDRESS)
+UIMAGE_COMPRESSION = gzip
 
 targets += uImage uImage.srec
 $(obj)/uImage: $(obj)/vmlinux.gz
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index 0a49279..f7d27d5 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -6,20 +6,17 @@
 # for more details.
 #
 
-MKIMAGE := $(srctree)/scripts/mkuboot.sh
-
 targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip
 extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
 
-UIMAGE_OPTS-y :=
-UIMAGE_OPTS-$(CONFIG_RAMKERNEL) += -a $(CONFIG_BOOT_LOAD)
-UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -a $(CONFIG_ROM_BASE) -x
-
-quiet_cmd_uimage = UIMAGE  $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
-                   -C $(2) -n '$(CPU_REV)-$(KERNELRELEASE)' \
-                   -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
-                   $(UIMAGE_OPTS-y) -d $< $@
+ifeq ($(CONFIG_RAMKERNEL),y)
+UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
+else # CONFIG_ROMKERNEL must be set
+UIMAGE_LOADADDR = $(CONFIG_ROM_BASE)
+endif
+UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}')
+UIMAGE_NAME = '$(CPU_REV)-$(KERNELRELEASE)'
+UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -x
 
 $(obj)/vmlinux.bin: vmlinux FORCE
 	$(call if_changed,objcopy)
diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile
index 0c796cf..ca76ecd 100644
--- a/arch/microblaze/boot/Makefile
+++ b/arch/microblaze/boot/Makefile
@@ -2,8 +2,6 @@
 # arch/microblaze/boot/Makefile
 #
 
-MKIMAGE := $(srctree)/scripts/mkuboot.sh
-
 obj-y += linked_dtb.o
 
 targets := linux.bin linux.bin.gz simpleImage.%
@@ -35,11 +33,9 @@ quiet_cmd_strip = STRIP   $@
 	cmd_strip = $(STRIP) -K microblaze_start -K _end -K __log_buf \
 				-K _fdt_start vmlinux -o $@
 
-quiet_cmd_uimage = UIMAGE  $@.ub
-	cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A microblaze -O linux -T kernel \
-		-C none -n 'Linux-$(KERNELRELEASE)' \
-		-a $(CONFIG_KERNEL_BASE_ADDR) -e $(CONFIG_KERNEL_BASE_ADDR) \
-		-d $@ $@.ub
+UIMAGE_IN = $@
+UIMAGE_OUT = $@.ub
+UIMAGE_LOADADDR = $(CONFIG_KERNEL_BASE_ADDR)
 
 $(obj)/simpleImage.%: vmlinux FORCE
 	$(call if_changed,cp,.unstrip)
diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
index e4ea31a..58592df 100644
--- a/arch/sh/boot/Makefile
+++ b/arch/sh/boot/Makefile
@@ -8,8 +8,6 @@
 # Copyright (C) 1999 Stuart Menefy
 #
 
-MKIMAGE := $(srctree)/scripts/mkuboot.sh
-
 #
 # Assign safe dummy values if these variables are not defined,
 # in order to suppress error message.
@@ -61,10 +59,8 @@ KERNEL_ENTRY	:= $(shell /bin/bash -c 'printf "0x%08x" \
 			$(KERNEL_MEMORY) + \
 			$(CONFIG_ZERO_PAGE_OFFSET) + $(CONFIG_ENTRY_OFFSET)]')
 
-quiet_cmd_uimage = UIMAGE  $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sh -O linux -T kernel \
-		   -C $(2) -a $(KERNEL_LOAD) -e $(KERNEL_ENTRY) \
-		   -n 'Linux-$(KERNELRELEASE)' -d $< $@
+UIMAGE_LOADADDR = $(KERNEL_LOAD)
+UIMAGE_ENTRYADDR = $(KERNEL_ENTRY)
 
 $(obj)/vmlinux.bin: vmlinux FORCE
 	$(call if_changed,objcopy)
diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile
index 9205416..d56d199 100644
--- a/arch/sparc/boot/Makefile
+++ b/arch/sparc/boot/Makefile
@@ -5,7 +5,6 @@
 
 ROOT_IMG	:= /usr/src/root.img
 ELFTOAOUT	:= elftoaout
-MKIMAGE 	:= $(srctree)/scripts/mkuboot.sh
 
 hostprogs-y	:= piggyback btfixupprep
 targets		:= tftpboot.img btfix.o btfix.S image zImage vmlinux.aout
@@ -92,11 +91,9 @@ $(obj)/image.bin: $(obj)/image FORCE
 $(obj)/image.gz: $(obj)/image.bin
 	$(call if_changed,gzip)
 
-quiet_cmd_uimage = UIMAGE  $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sparc -O linux -T kernel \
-               -C gzip -a $(CONFIG_UBOOT_LOAD_ADDR) \
-	       -e $(CONFIG_UBOOT_ENTRY_ADDR) -n 'Linux-$(KERNELRELEASE)' \
-               -d $< $@
+UIMAGE_LOADADDR = $(CONFIG_UBOOT_LOAD_ADDR)
+UIMAGE_ENTRYADDR = $(CONFIG_UBOOT_ENTRY_ADDR)
+UIMAGE_COMPRESSION = gzip
 
 quiet_cmd_uimage.o = UIMAGE.O $@
       cmd_uimage.o = $(LD) -Tdata $(CONFIG_UBOOT_FLASH_ADDR) \
diff --git a/arch/unicore32/boot/Makefile b/arch/unicore32/boot/Makefile
index 79e5f88..ec7fb70 100644
--- a/arch/unicore32/boot/Makefile
+++ b/arch/unicore32/boot/Makefile
@@ -11,8 +11,6 @@
 # Copyright (C) 2001~2010 GUAN Xue-tao
 #
 
-MKIMAGE := $(srctree)/scripts/mkuboot.sh
-
 targets := Image zImage uImage
 
 $(obj)/Image: vmlinux FORCE
@@ -26,14 +24,8 @@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE
 	$(call if_changed,objcopy)
 	@echo '  Kernel: $@ is ready'
 
-quiet_cmd_uimage = UIMAGE  $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A unicore -O linux -T kernel \
-		   -C none -a $(LOADADDR) -e $(STARTADDR) \
-		   -n 'Linux-$(KERNELRELEASE)' -d $< $@
-
-$(obj)/uImage: LOADADDR=0x0
-
-$(obj)/uImage: STARTADDR=$(LOADADDR)
+UIMAGE_ARCH = unicore
+UIMAGE_LOADADDR = 0x0
 
 $(obj)/uImage: $(obj)/zImage FORCE
 	$(call if_changed,uimage)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 00c368c..0be6f11 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -304,6 +304,30 @@ cmd_lzo = (cat $(filter-out FORCE,$^) | \
 	lzop -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
 	(rm -f $@ ; false)
 
+# U-Boot mkimage
+# ---------------------------------------------------------------------------
+
+MKIMAGE := $(srctree)/scripts/mkuboot.sh
+
+# SRCARCH just happens to match slightly more than ARCH (on sparc), so reduces
+# the number of overrides in arch makefiles
+UIMAGE_ARCH ?= $(SRCARCH)
+UIMAGE_COMPRESSION ?= $(if $(2),$(2),none)
+UIMAGE_OPTS-y ?=
+UIMAGE_TYPE ?= kernel
+UIMAGE_LOADADDR ?= arch_must_set_this
+UIMAGE_ENTRYADDR ?= $(UIMAGE_LOADADDR)
+UIMAGE_NAME ?= 'Linux-$(KERNELRELEASE)'
+UIMAGE_IN ?= $<
+UIMAGE_OUT ?= $@
+
+quiet_cmd_uimage = UIMAGE  $(UIMAGE_OUT)
+      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(UIMAGE_ARCH) -O linux \
+			-C $(UIMAGE_COMPRESSION) $(UIMAGE_OPTS-y) \
+			-T $(UIMAGE_TYPE) \
+			-a $(UIMAGE_LOADADDR) -e $(UIMAGE_ENTRYADDR) \
+			-n $(UIMAGE_NAME) -d $(UIMAGE_IN) $(UIMAGE_OUT)
+
 # XZ
 # ---------------------------------------------------------------------------
 # Use xzkern to compress the kernel image and xzmisc to compress other things.
-- 
1.7.0.4



From balbi at ti.com  Fri Mar 16 17:08:43 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 16 Mar 2012 23:08:43 +0200
Subject: [PATCH 1/2] input: keypad: move platform_data to
 <linux/platform_data>
In-Reply-To: <1357514.ox9yZWgqO9@dtor-d630.eng.vmware.com>
References: <1331907989-11891-1-git-send-email-sourav.poddar@ti.com>
 <1331907989-11891-2-git-send-email-sourav.poddar@ti.com>
 <1357514.ox9yZWgqO9@dtor-d630.eng.vmware.com>
Message-ID: <20120316210841.GA19797@arwen.pp.htv.fi>

Hi,

On Fri, Mar 16, 2012 at 09:36:19AM -0700, Dmitry Torokhov wrote:
> On Friday, March 16, 2012 07:56:28 PM Sourav Poddar wrote:
> > From: Felipe Balbi <balbi at ti.com>
> > 
> > This patch allows us to drop the OMAP depencendy
> > from the OMAP4 keypad driver.
> > 
> > Signed-off-by: Felipe Balbi <balbi at ti.com>
> > Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> > ---
> >  arch/arm/mach-omap2/board-4430sdp.c            |    1 +
> >  arch/arm/mach-omap2/devices.c                  |    1 +
> >  arch/arm/plat-omap/include/plat/omap4-keypad.h |    9 ---------
> >  drivers/input/keyboard/Kconfig                 |    1 -
> >  drivers/input/keyboard/omap4-keypad.c          |    2 +-
> >  include/linux/platform_data/omap4-keypad.h     |   13 +++++++++++++
> 
> Instead of creating platform_data directory why not move to
> include/linux/input/omap4-keypad.h?

look closer, that directory already exists. But if you prefer placing
that header on <linux/input> that's doable too.

-- 
balbi
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From paul.gortmaker at windriver.com  Fri Mar 16 17:18:00 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Fri, 16 Mar 2012 17:18:00 -0400
Subject: ARM: fix build failure on ux500 in linux-next
Message-ID: <20120316211759.GA18829@windriver.com>

When I 1st saw this build failure, I thought it was me, because of the
BUG() stuff.  But git bisect claims it comes from the arm-soc tree?

In any case, the fix is trivial and self evident, regardless of where
it came from.  I can carry it in my bug-3.4 cleanup tree if need be.
Let me know if you want me to do that.

Thanks,
Paul.
---

git bisect start
# good: [fde7d9049e55ab85a390be7f415d74c9f62dd0f9] Linux 3.3-rc7
git bisect good fde7d9049e55ab85a390be7f415d74c9f62dd0f9
# bad: [e9ae4cb7dce90c006b25783f431100c1aebe8249] Add linux-next specific files for 20120316
git bisect bad e9ae4cb7dce90c006b25783f431100c1aebe8249
# good: [04e2934e35128af6772c6e7582a2a70e9bfa6e39] Merge remote-tracking branch 'sound/for-next'
git bisect good 04e2934e35128af6772c6e7582a2a70e9bfa6e39
# good: [83e256edcb2f8886786b1bba59992c90391e162a] Merge remote-tracking branch 'tip/auto-latest'
git bisect good 83e256edcb2f8886786b1bba59992c90391e162a
# good: [e047bb4623cb69a162fe3b6dffb6b6719e5ed36b] Merge remote-tracking branch 'tmem/linux-next'
git bisect good e047bb4623cb69a162fe3b6dffb6b6719e5ed36b
# good: [4d879eaf577c4f1a84a9cad4445e388f3fa3751b] Merge branch 'next/timer' into for-next
git bisect good 4d879eaf577c4f1a84a9cad4445e388f3fa3751b
# bad: [11f98c49d6bbedf80ebd3b477cf9283c6a3e9b1a] xtensa: use set_current_blocked() and block_sigmask()
git bisect bad 11f98c49d6bbedf80ebd3b477cf9283c6a3e9b1a
# good: [50cfadc1b7ae56c5062401018df8fe16114de29a] Merge remote-tracking branch 'gpio/gpio/next'
git bisect good 50cfadc1b7ae56c5062401018df8fe16114de29a
# bad: [befe1aab92393bd4106d78f5610958dc37dce074] Merge remote-tracking branch 'dma-mapping/dma-mapping-next'
git bisect bad befe1aab92393bd4106d78f5610958dc37dce074
# good: [7ae1cd4e9625311fbada74513a69044f66b5eff9] Merge branch 'next/boards' into for-next
git bisect good 7ae1cd4e9625311fbada74513a69044f66b5eff9
# good: [268b190b02965250cb5080beb755f25a2631cceb] Merge branch 'next/drivers' into for-next
git bisect good 268b190b02965250cb5080beb755f25a2631cceb
# good: [b908eddffb98f4106068e132b6a05888cea59fd0] Hexagon: adapt for dma_map_ops changes
git bisect good b908eddffb98f4106068e132b6a05888cea59fd0
# good: [62d02641854bc02534c32e2c20f0d403cde32f24] Merge branch 'next/soc2' into for-next
git bisect good 62d02641854bc02534c32e2c20f0d403cde32f24
# good: [c4715f1e814e05beb5f99ec18ddb0e2e934a8b3d] common: DMA-mapping: add WRITE_COMBINE attribute
git bisect good c4715f1e814e05beb5f99ec18ddb0e2e934a8b3d
# good: [6cc2bf1ab405a7085c92fefbad610b35ec60d3e0] common: DMA-mapping: add NON-CONSISTENT attribute
git bisect good 6cc2bf1ab405a7085c92fefbad610b35ec60d3e0
# bad: [c4aa47a2a1665e8d5ea62dcbfba9a54a86003190] Merge remote-tracking branch 'arm-soc/for-next'
git bisect bad c4aa47a2a1665e8d5ea62dcbfba9a54a86003190

---

>From 79a97eb612706ee3428ae7909503079c6fd3cf68 Mon Sep 17 00:00:00 2001
From: Paul Gortmaker <paul.gortmaker at windriver.com>
Date: Fri, 16 Mar 2012 16:45:32 -0400
Subject: [PATCH] ARM: fix trivial build failures on ux500

Seen in linux-next builds:

arch/arm/mach-ux500/timer.c: In function 'ux500_twd_init':
arch/arm/mach-ux500/timer.c:35: error: implicit declaration of function 'pr_err'
arch/arm/mach-ux500/timer.c: In function 'ux500_timer_init':
arch/arm/mach-ux500/timer.c:53: error: implicit declaration of function 'BUG'

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>

diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index e9d5807..90cf3f0 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -5,6 +5,8 @@
  * Author: Mattias Wallin <mattias.wallin at stericsson.com> for ST-Ericsson
  */
 #include <linux/io.h>
+#include <linux/bug.h>
+#include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 
-- 
1.7.9.1






From timur at freescale.com  Fri Mar 16 17:21:43 2012
From: timur at freescale.com (Timur Tabi)
Date: Fri, 16 Mar 2012 16:21:43 -0500
Subject: [PATCH v5 2/8] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <1331888204-27058-3-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-3-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F63AEE7.4030505@freescale.com>

Shawn Guo wrote:
> Freescale PowerPC and ARM/IMX families share the same SSI IP block.
> The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
> code sharing and consolidation can happen.
> 
> This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
> in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
> IMX platform.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---

I'm okay with this patch, but you will need an Ack from Kumar Gala to
carry the defconfig portions through the ASoC tree.  Or, he might want you
to split the patch up.

>  arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig |    1 +
>  arch/powerpc/configs/mpc85xx_defconfig           |    1 +
>  arch/powerpc/configs/mpc85xx_smp_defconfig       |    1 +
>  sound/soc/Kconfig                                |    1 -
>  sound/soc/Makefile                               |    1 -
>  sound/soc/fsl/Kconfig                            |   92 ++++++++++++++++++++++
>  sound/soc/fsl/Makefile                           |   22 +++++
>  sound/soc/{imx => fsl}/eukrea-tlv320.c           |    2 +-
>  sound/soc/{imx => fsl}/imx-audmux.c              |    0
>  sound/soc/{imx => fsl}/imx-audmux.h              |    0
>  sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c         |    0
>  sound/soc/{imx => fsl}/imx-pcm-fiq.c             |    0
>  sound/soc/{imx => fsl}/imx-pcm.c                 |    0
>  sound/soc/{imx => fsl}/imx-pcm.h                 |    0
>  sound/soc/{imx => fsl}/imx-ssi.c                 |    2 +-
>  sound/soc/{imx => fsl}/imx-ssi.h                 |    0
>  sound/soc/{imx => fsl}/mx27vis-aic32x4.c         |    0
>  sound/soc/{imx => fsl}/phycore-ac97.c            |    0
>  sound/soc/{imx => fsl}/wm1133-ev1.c              |    0
>  sound/soc/imx/Kconfig                            |   79 -------------------
>  sound/soc/imx/Makefile                           |   22 -----
>  21 files changed, 119 insertions(+), 105 deletions(-)
>  rename sound/soc/{imx => fsl}/eukrea-tlv320.c (99%)
>  rename sound/soc/{imx => fsl}/imx-audmux.c (100%)
>  rename sound/soc/{imx => fsl}/imx-audmux.h (100%)
>  rename sound/soc/{imx => fsl}/imx-pcm-dma-mx2.c (100%)
>  rename sound/soc/{imx => fsl}/imx-pcm-fiq.c (100%)
>  rename sound/soc/{imx => fsl}/imx-pcm.c (100%)
>  rename sound/soc/{imx => fsl}/imx-pcm.h (100%)
>  rename sound/soc/{imx => fsl}/imx-ssi.c (99%)
>  rename sound/soc/{imx => fsl}/imx-ssi.h (100%)
>  rename sound/soc/{imx => fsl}/mx27vis-aic32x4.c (100%)
>  rename sound/soc/{imx => fsl}/phycore-ac97.c (100%)
>  rename sound/soc/{imx => fsl}/wm1133-ev1.c (100%)
>  delete mode 100644 sound/soc/imx/Kconfig
>  delete mode 100644 sound/soc/imx/Makefile
> 
> diff --git a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
> index 0db9ba0..c09598b 100644
> --- a/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
> +++ b/arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig
> @@ -100,6 +100,7 @@ CONFIG_SND_MIXER_OSS=y
>  CONFIG_SND_PCM_OSS=y
>  # CONFIG_SND_SUPPORT_OLD_API is not set
>  CONFIG_SND_SOC=y
> +CONFIG_SND_POWERPC_SOC=y
>  CONFIG_RTC_CLASS=y
>  CONFIG_RTC_DRV_CMOS=y
>  CONFIG_EXT2_FS=y
> diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
> index f37a2ab..44605f8 100644
> --- a/arch/powerpc/configs/mpc85xx_defconfig
> +++ b/arch/powerpc/configs/mpc85xx_defconfig
> @@ -139,6 +139,7 @@ CONFIG_SND_INTEL8X0=y
>  # CONFIG_SND_PPC is not set
>  # CONFIG_SND_USB is not set
>  CONFIG_SND_SOC=y
> +CONFIG_SND_POWERPC_SOC=y
>  CONFIG_HID_A4TECH=y
>  CONFIG_HID_APPLE=y
>  CONFIG_HID_BELKIN=y
> diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
> index abdcd31..98e227e 100644
> --- a/arch/powerpc/configs/mpc85xx_smp_defconfig
> +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
> @@ -141,6 +141,7 @@ CONFIG_SND_INTEL8X0=y
>  # CONFIG_SND_PPC is not set
>  # CONFIG_SND_USB is not set
>  CONFIG_SND_SOC=y
> +CONFIG_SND_POWERPC_SOC=y
>  CONFIG_HID_A4TECH=y
>  CONFIG_HID_APPLE=y
>  CONFIG_HID_BELKIN=y
> diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
> index 91c9855..0f85f6d 100644
> --- a/sound/soc/Kconfig
> +++ b/sound/soc/Kconfig
> @@ -35,7 +35,6 @@ source "sound/soc/blackfin/Kconfig"
>  source "sound/soc/davinci/Kconfig"
>  source "sound/soc/ep93xx/Kconfig"
>  source "sound/soc/fsl/Kconfig"
> -source "sound/soc/imx/Kconfig"
>  source "sound/soc/jz4740/Kconfig"
>  source "sound/soc/nuc900/Kconfig"
>  source "sound/soc/omap/Kconfig"
> diff --git a/sound/soc/Makefile b/sound/soc/Makefile
> index 2feaf37..363dfd6 100644
> --- a/sound/soc/Makefile
> +++ b/sound/soc/Makefile
> @@ -12,7 +12,6 @@ obj-$(CONFIG_SND_SOC)	+= blackfin/
>  obj-$(CONFIG_SND_SOC)	+= davinci/
>  obj-$(CONFIG_SND_SOC)	+= ep93xx/
>  obj-$(CONFIG_SND_SOC)	+= fsl/
> -obj-$(CONFIG_SND_SOC)   += imx/
>  obj-$(CONFIG_SND_SOC)	+= jz4740/
>  obj-$(CONFIG_SND_SOC)	+= mid-x86/
>  obj-$(CONFIG_SND_SOC)	+= mxs/
> diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
> index ca693b2..19856a0 100644
> --- a/sound/soc/fsl/Kconfig
> +++ b/sound/soc/fsl/Kconfig
> @@ -1,3 +1,15 @@
> +config SND_SOC_FSL_SSI
> +	tristate
> +
> +menuconfig SND_POWERPC_SOC
> +	tristate "SoC Audio for Freescale PowerPC CPUs"
> +	depends on FSL_SOC
> +	help
> +	  Say Y or M if you want to add support for codecs attached to
> +	  the PowerPC CPUs.
> +
> +if SND_POWERPC_SOC
> +
>  config SND_MPC52xx_DMA
>  	tristate
>  
> @@ -68,3 +80,83 @@ config SND_MPC52xx_SOC_EFIKA
>  	help
>  	  Say Y if you want to add support for sound on the Efika.
>  
> +endif # SND_POWERPC_SOC
> +
> +menuconfig SND_IMX_SOC
> +	tristate "SoC Audio for Freescale i.MX CPUs"
> +	depends on ARCH_MXC
> +	help
> +	  Say Y or M if you want to add support for codecs attached to
> +	  the i.MX CPUs.
> +
> +if SND_IMX_SOC
> +
> +config SND_SOC_IMX_SSI
> +	tristate
> +
> +config SND_SOC_IMX_PCM
> +	tristate
> +
> +config SND_MXC_SOC_FIQ
> +	tristate
> +	select FIQ
> +	select SND_SOC_IMX_PCM
> +
> +config SND_MXC_SOC_MX2
> +	tristate
> +	select SND_SOC_DMAENGINE_PCM
> +	select SND_SOC_IMX_PCM
> +
> +config SND_SOC_IMX_AUDMUX
> +	tristate
> +
> +config SND_MXC_SOC_WM1133_EV1
> +	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
> +	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
> +	select SND_SOC_WM8350
> +	select SND_MXC_SOC_FIQ
> +	select SND_SOC_IMX_AUDMUX
> +	select SND_SOC_IMX_SSI
> +	help
> +	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
> +	  PMIC board with WM8835x fitted.
> +
> +config SND_SOC_MX27VIS_AIC32X4
> +	tristate "SoC audio support for Visstrim M10 boards"
> +	depends on MACH_IMX27_VISSTRIM_M10 && I2C
> +	select SND_SOC_TLV320AIC32X4
> +	select SND_MXC_SOC_MX2
> +	select SND_SOC_IMX_AUDMUX
> +	select SND_SOC_IMX_SSI
> +	help
> +	  Say Y if you want to add support for SoC audio on Visstrim SM10
> +	  board with TLV320AIC32X4 codec.
> +
> +config SND_SOC_PHYCORE_AC97
> +	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
> +	depends on MACH_PCM043 || MACH_PCA100
> +	select SND_SOC_AC97_BUS
> +	select SND_SOC_WM9712
> +	select SND_MXC_SOC_FIQ
> +	select SND_SOC_IMX_AUDMUX
> +	select SND_SOC_IMX_SSI
> +	help
> +	  Say Y if you want to add support for SoC audio on Phytec phyCORE
> +	  and phyCARD boards in AC97 mode
> +
> +config SND_SOC_EUKREA_TLV320
> +	tristate "Eukrea TLV320"
> +	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
> +		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
> +		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
> +		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
> +	depends on I2C
> +	select SND_SOC_TLV320AIC23
> +	select SND_MXC_SOC_FIQ
> +	select SND_SOC_IMX_AUDMUX
> +	select SND_SOC_IMX_SSI
> +	help
> +	  Enable I2S based access to the TLV320AIC23B codec attached
> +	  to the SSI interface
> +
> +endif # SND_IMX_SOC
> diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
> index 95d483f..36c257f 100644
> --- a/sound/soc/fsl/Makefile
> +++ b/sound/soc/fsl/Makefile
> @@ -21,3 +21,25 @@ obj-$(CONFIG_SND_SOC_MPC5200_AC97) += mpc5200_psc_ac97.o
>  obj-$(CONFIG_SND_MPC52xx_SOC_PCM030) += pcm030-audio-fabric.o
>  obj-$(CONFIG_SND_MPC52xx_SOC_EFIKA) += efika-audio-fabric.o
>  
> +# i.MX Platform Support
> +snd-soc-imx-ssi-objs := imx-ssi.o
> +snd-soc-imx-audmux-objs := imx-audmux.o
> +
> +obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
> +obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
> +
> +obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
> +snd-soc-imx-pcm-y := imx-pcm.o
> +snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
> +snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
> +
> +# i.MX Machine Support
> +snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
> +snd-soc-phycore-ac97-objs := phycore-ac97.o
> +snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
> +snd-soc-wm1133-ev1-objs := wm1133-ev1.o
> +
> +obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
> +obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
> +obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
> +obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
> diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/fsl/eukrea-tlv320.c
> similarity index 99%
> rename from sound/soc/imx/eukrea-tlv320.c
> rename to sound/soc/fsl/eukrea-tlv320.c
> index 7d4475c..efb9ede 100644
> --- a/sound/soc/imx/eukrea-tlv320.c
> +++ b/sound/soc/fsl/eukrea-tlv320.c
> @@ -7,7 +7,7 @@
>   * which is Copyright 2009 Simtec Electronics
>   * and on sound/soc/imx/phycore-ac97.c which is
>   * Copyright 2009 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
> - * 
> + *
>   *  This program is free software; you can redistribute  it and/or modify it
>   *  under  the terms of  the GNU General  Public License as published by the
>   *  Free Software Foundation;  either version 2 of the  License, or (at your
> diff --git a/sound/soc/imx/imx-audmux.c b/sound/soc/fsl/imx-audmux.c
> similarity index 100%
> rename from sound/soc/imx/imx-audmux.c
> rename to sound/soc/fsl/imx-audmux.c
> diff --git a/sound/soc/imx/imx-audmux.h b/sound/soc/fsl/imx-audmux.h
> similarity index 100%
> rename from sound/soc/imx/imx-audmux.h
> rename to sound/soc/fsl/imx-audmux.h
> diff --git a/sound/soc/imx/imx-pcm-dma-mx2.c b/sound/soc/fsl/imx-pcm-dma-mx2.c
> similarity index 100%
> rename from sound/soc/imx/imx-pcm-dma-mx2.c
> rename to sound/soc/fsl/imx-pcm-dma-mx2.c
> diff --git a/sound/soc/imx/imx-pcm-fiq.c b/sound/soc/fsl/imx-pcm-fiq.c
> similarity index 100%
> rename from sound/soc/imx/imx-pcm-fiq.c
> rename to sound/soc/fsl/imx-pcm-fiq.c
> diff --git a/sound/soc/imx/imx-pcm.c b/sound/soc/fsl/imx-pcm.c
> similarity index 100%
> rename from sound/soc/imx/imx-pcm.c
> rename to sound/soc/fsl/imx-pcm.c
> diff --git a/sound/soc/imx/imx-pcm.h b/sound/soc/fsl/imx-pcm.h
> similarity index 100%
> rename from sound/soc/imx/imx-pcm.h
> rename to sound/soc/fsl/imx-pcm.h
> diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
> similarity index 99%
> rename from sound/soc/imx/imx-ssi.c
> rename to sound/soc/fsl/imx-ssi.c
> index 9203cdd..3e0dac5a 100644
> --- a/sound/soc/imx/imx-ssi.c
> +++ b/sound/soc/fsl/imx-ssi.c
> @@ -28,7 +28,7 @@
>   * value. When we read the same register two times (and the register still
>   * contains the same value) these status bits are not set. We work
>   * around this by not polling these bits but only wait a fixed delay.
> - * 
> + *
>   */
>  
>  #include <linux/clk.h>
> diff --git a/sound/soc/imx/imx-ssi.h b/sound/soc/fsl/imx-ssi.h
> similarity index 100%
> rename from sound/soc/imx/imx-ssi.h
> rename to sound/soc/fsl/imx-ssi.h
> diff --git a/sound/soc/imx/mx27vis-aic32x4.c b/sound/soc/fsl/mx27vis-aic32x4.c
> similarity index 100%
> rename from sound/soc/imx/mx27vis-aic32x4.c
> rename to sound/soc/fsl/mx27vis-aic32x4.c
> diff --git a/sound/soc/imx/phycore-ac97.c b/sound/soc/fsl/phycore-ac97.c
> similarity index 100%
> rename from sound/soc/imx/phycore-ac97.c
> rename to sound/soc/fsl/phycore-ac97.c
> diff --git a/sound/soc/imx/wm1133-ev1.c b/sound/soc/fsl/wm1133-ev1.c
> similarity index 100%
> rename from sound/soc/imx/wm1133-ev1.c
> rename to sound/soc/fsl/wm1133-ev1.c
> diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
> deleted file mode 100644
> index 810acaa..0000000
> --- a/sound/soc/imx/Kconfig
> +++ /dev/null
> @@ -1,79 +0,0 @@
> -menuconfig SND_IMX_SOC
> -	tristate "SoC Audio for Freescale i.MX CPUs"
> -	depends on ARCH_MXC
> -	help
> -	  Say Y or M if you want to add support for codecs attached to
> -	  the i.MX SSI interface.
> -
> -
> -if SND_IMX_SOC
> -
> -config SND_SOC_IMX_SSI
> -	tristate
> -
> -config SND_SOC_IMX_PCM
> -	tristate
> -
> -config SND_MXC_SOC_FIQ
> -	tristate
> -	select FIQ
> -	select SND_SOC_IMX_PCM
> -
> -config SND_MXC_SOC_MX2
> -	select SND_SOC_DMAENGINE_PCM
> -	tristate
> -	select SND_SOC_IMX_PCM
> -
> -config SND_SOC_IMX_AUDMUX
> -	tristate
> -
> -config SND_MXC_SOC_WM1133_EV1
> -	tristate "Audio on the the i.MX31ADS with WM1133-EV1 fitted"
> -	depends on MACH_MX31ADS_WM1133_EV1 && EXPERIMENTAL
> -	select SND_SOC_WM8350
> -	select SND_MXC_SOC_FIQ
> -	select SND_SOC_IMX_AUDMUX
> -	select SND_SOC_IMX_SSI
> -	help
> -	  Enable support for audio on the i.MX31ADS with the WM1133-EV1
> -	  PMIC board with WM8835x fitted.
> -
> -config SND_SOC_MX27VIS_AIC32X4
> -	tristate "SoC audio support for Visstrim M10 boards"
> -	depends on MACH_IMX27_VISSTRIM_M10 && I2C
> -	select SND_SOC_TLV320AIC32X4
> -	select SND_MXC_SOC_MX2
> -	select SND_SOC_IMX_AUDMUX
> -	select SND_SOC_IMX_SSI
> -	help
> -	  Say Y if you want to add support for SoC audio on Visstrim SM10
> -	  board with TLV320AIC32X4 codec.
> -
> -config SND_SOC_PHYCORE_AC97
> -	tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
> -	depends on MACH_PCM043 || MACH_PCA100
> -	select SND_SOC_AC97_BUS
> -	select SND_SOC_WM9712
> -	select SND_MXC_SOC_FIQ
> -	select SND_SOC_IMX_AUDMUX
> -	select SND_SOC_IMX_SSI
> -	help
> -	  Say Y if you want to add support for SoC audio on Phytec phyCORE
> -	  and phyCARD boards in AC97 mode
> -
> -config SND_SOC_EUKREA_TLV320
> -	tristate "Eukrea TLV320"
> -	depends on MACH_EUKREA_MBIMX27_BASEBOARD \
> -		|| MACH_EUKREA_MBIMXSD25_BASEBOARD \
> -		|| MACH_EUKREA_MBIMXSD35_BASEBOARD \
> -		|| MACH_EUKREA_MBIMXSD51_BASEBOARD
> -	depends on I2C
> -	select SND_SOC_TLV320AIC23
> -	select SND_MXC_SOC_FIQ
> -	select SND_SOC_IMX_AUDMUX
> -	select SND_SOC_IMX_SSI
> -	help
> -	  Enable I2S based access to the TLV320AIC23B codec attached
> -	  to the SSI interface
> -
> -endif	# SND_IMX_SOC
> diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile
> deleted file mode 100644
> index f5db3e9..0000000
> --- a/sound/soc/imx/Makefile
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -# i.MX Platform Support
> -snd-soc-imx-ssi-objs := imx-ssi.o
> -snd-soc-imx-audmux-objs := imx-audmux.o
> -
> -obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
> -obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
> -
> -obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
> -snd-soc-imx-pcm-y := imx-pcm.o
> -snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_FIQ) += imx-pcm-fiq.o
> -snd-soc-imx-pcm-$(CONFIG_SND_MXC_SOC_MX2) += imx-pcm-dma-mx2.o
> -
> -# i.MX Machine Support
> -snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
> -snd-soc-phycore-ac97-objs := phycore-ac97.o
> -snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
> -snd-soc-wm1133-ev1-objs := wm1133-ev1.o
> -
> -obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
> -obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
> -obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
> -obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o


-- 
Timur Tabi
Linux kernel developer at Freescale



From timur at freescale.com  Fri Mar 16 17:25:09 2012
From: timur at freescale.com (Timur Tabi)
Date: Fri, 16 Mar 2012 16:25:09 -0500
Subject: [PATCH v5] ASoC: add imx-sgtl5000 machine driver working with
 fsl_ssi
In-Reply-To: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <4F63AFB5.8000408@freescale.com>

Shawn Guo wrote:
> Changes since v4:
>  * Add new_binding flag for fsl_ssi driver to support both
>    "old binding" and "new binding"
> 
> ---
> Shawn Guo (8):
>       ASoC: fsl: separate SSI and DMA Kconfig options
>       ASoC: imx: merge sound/soc/imx into sound/soc/fsl
>       ASoC: fsl: rename imx-pcm Kconfig options and filename
>       ASoC: fsl: create fsl_utils to accommodate the common functions
>       ASoC: fsl: remove helper fsl_asoc_get_codec_dev_name
>       ASoC: fsl: make fsl_ssi driver compilable on ARM/IMX
>       ASoC: fsl: let fsl_ssi work with imx pcm and machine drivers
>       ASoC: fsl: add imx-sgtl5000 machine driver

Entire patchset:

Acked-by: Timur Tabi <timur at freescale.com>

-- 
Timur Tabi
Linux kernel developer at Freescale



From mgherzan at gmail.com  Fri Mar 16 17:28:36 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Fri, 16 Mar 2012 22:28:36 +0100
Subject: [PATCH v8 RESEND] ARM: net: JIT compiler for packet filters
Message-ID: <1331933316-10197-1-git-send-email-mgherzan@gmail.com>

Based of Matt Evans's PPC64 implementation.

The compiler generates ARM instructions but interworking is
supported for Thumb2 kernels.

Supports both little and big endian. Unaligned loads are emitted
for ARMv6+. Not all the BPF opcodes that deal with ancillary data
are supported. The scratch memory of the filter lives on the stack.
Hardware integer division is used if it is available.

Enabled in the same way as for x86-64 and PPC64:

	echo 1 > /proc/sys/net/core/bpf_jit_enable

A value greater than 1 enables opcode output.

Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
---

Changes in v8:
 * skb_copy_bits() return value check in LDX_MSH
 * immediate value as signed integer for absolute loads

Changes in v7:
 * fix the intruction generation for LDX_MSH, OR_X, LSH_K,
   RSH_K and JMP_JA
 * fix the condition for saving the A register
 * use fls() instead of the compiler builtin
 * punt to the interpreter on absolute loads with K < 0
 * check for invalid data references
 * support the NEG opcode
 * clear X in the prologue based on a context flag
 * simplify the conditional jumps

Changes in v6:
 * fix the code generation for the ANC_CPU opcode

Changes in v5:
 * replace SEEN_LEN with SEEN_SKB
 * set ctx->seen when handling some ancillary data opcodes

Changes in v4:
 * first check if the JIT compiler is enabled
 * fix the code generation for the LDX_MSH opcode

Changes in v3:
 * no longer depend on EABI and !Thumb2
 * add BLX "emulation" for ARMv4 without Thumb
 * use the integer divide instruction on Cortex-A15
 * fix the handling of the DIV_K opcode
 * use a C wrapper for __aeabi_uidiv
 * fix the generation of the epilogue (non-FP case)

Changes in v2:
 * enable the compiler only for ARMv5+ because of the BLX instruction
 * use the same comparison for the ARM version checks
 * use misaligned accesses on ARMv6
 * fix the SEEN_MEM
 * fix the mem_words_used()

 arch/arm/Kconfig          |    1 +
 arch/arm/Makefile         |    1 +
 arch/arm/net/Makefile     |    3 +
 arch/arm/net/bpf_jit_32.c |  916 +++++++++++++++++++++++++++++++++++++++++++++
 arch/arm/net/bpf_jit_32.h |  190 ++++++++++
 5 files changed, 1111 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/net/Makefile
 create mode 100644 arch/arm/net/bpf_jit_32.c
 create mode 100644 arch/arm/net/bpf_jit_32.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dfb0312..ade6274 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -32,6 +32,7 @@ config ARM
 	select GENERIC_IRQ_SHOW
 	select CPU_PM if (SUSPEND || CPU_IDLE)
 	select GENERIC_PCI_IOMAP
+	select HAVE_BPF_JIT
 	help
 	  The ARM series is a line of low-power-consumption RISC chip designs
 	  licensed by ARM Ltd and targeted at embedded applications and
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1683bfb..03b0039 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -252,6 +252,7 @@ core-$(CONFIG_VFP)		+= arch/arm/vfp/
 
 # If we have a machine-specific directory, then include it in the build.
 core-y				+= arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
+core-y				+= arch/arm/net/
 core-y				+= $(machdirs) $(platdirs)
 
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
diff --git a/arch/arm/net/Makefile b/arch/arm/net/Makefile
new file mode 100644
index 0000000..c2c1084
--- /dev/null
+++ b/arch/arm/net/Makefile
@@ -0,0 +1,3 @@
+# ARM-specific networking code
+
+obj-$(CONFIG_BPF_JIT) += bpf_jit_32.o
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
new file mode 100644
index 0000000..2ee157a
--- /dev/null
+++ b/arch/arm/net/bpf_jit_32.c
@@ -0,0 +1,916 @@
+/*
+ * Just-In-Time compiler for BPF filters on 32bit ARM
+ *
+ * Copyright (c) 2011 Mircea Gherzan <mgherzan at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/bitops.h>
+#include <linux/compiler.h>
+#include <linux/errno.h>
+#include <linux/filter.h>
+#include <linux/moduleloader.h>
+#include <linux/netdevice.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <asm/cacheflush.h>
+#include <asm/hwcap.h>
+
+#include "bpf_jit_32.h"
+
+/*
+ * ABI:
+ *
+ * r0	scratch register
+ * r4	BPF register A
+ * r5	BPF register X
+ * r6	pointer to the skb
+ * r7	skb->data
+ * r8	skb_headlen(skb)
+ */
+
+#define r_scratch	ARM_R0
+/* r1-r3 are (also) used for the unaligned loads on the non-ARMv7 slowpath */
+#define r_off		ARM_R1
+#define r_A		ARM_R4
+#define r_X		ARM_R5
+#define r_skb		ARM_R6
+#define r_skb_data	ARM_R7
+#define r_skb_hl	ARM_R8
+
+#define SCRATCH_SP_OFFSET	0
+#define SCRATCH_OFF(k)		(SCRATCH_SP_OFFSET + (k))
+
+#define SEEN_MEM		((1 << BPF_MEMWORDS) - 1)
+#define SEEN_MEM_WORD(k)	(1 << (k))
+#define SEEN_X			(1 << BPF_MEMWORDS)
+#define SEEN_CALL		(1 << (BPF_MEMWORDS + 1))
+#define SEEN_SKB		(1 << (BPF_MEMWORDS + 2))
+#define SEEN_DATA		(1 << (BPF_MEMWORDS + 3))
+
+#define FLAG_NEED_X_RESET	(1 << 0)
+
+struct jit_ctx {
+	const struct sk_filter *skf;
+	unsigned idx;
+	unsigned prologue_bytes;
+	int ret0_fp_idx;
+	u32 seen;
+	u32 flags;
+	u32 *offsets;
+	u32 *target;
+#if __LINUX_ARM_ARCH__ < 7
+	u16 epilogue_bytes;
+	u16 imm_count;
+	u32 *imms;
+#endif
+};
+
+int bpf_jit_enable __read_mostly;
+
+static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset)
+{
+	u8 ret;
+	int err;
+
+	err = skb_copy_bits(skb, offset, &ret, 1);
+
+	return (u64)err << 32 | ret;
+}
+
+static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset)
+{
+	u16 ret;
+	int err;
+
+	err = skb_copy_bits(skb, offset, &ret, 2);
+
+	return (u64)err << 32 | ntohs(ret);
+}
+
+static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset)
+{
+	u32 ret;
+	int err;
+
+	err = skb_copy_bits(skb, offset, &ret, 4);
+
+	return (u64)err << 32 | ntohl(ret);
+}
+
+/*
+ * Wrapper that handles both OABI and EABI and assures Thumb2 interworking
+ * (where the assembly routines like __aeabi_uidiv could cause problems).
+ */
+static u32 jit_udiv(u32 dividend, u32 divisor)
+{
+	return dividend / divisor;
+}
+
+static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx)
+{
+	if (ctx->target != NULL)
+		ctx->target[ctx->idx] = inst | (cond << 28);
+
+	ctx->idx++;
+}
+
+/*
+ * Emit an instruction that will be executed unconditionally.
+ */
+static inline void emit(u32 inst, struct jit_ctx *ctx)
+{
+	_emit(ARM_COND_AL, inst, ctx);
+}
+
+static u16 saved_regs(struct jit_ctx *ctx)
+{
+	u16 ret = 0;
+
+	if ((ctx->skf->len > 1) ||
+	    (ctx->skf->insns[0].code == BPF_S_RET_A))
+		ret |= 1 << r_A;
+
+#ifdef CONFIG_FRAME_POINTER
+	ret |= (1 << ARM_FP) | (1 << ARM_IP) | (1 << ARM_LR) | (1 << ARM_PC);
+#else
+	if (ctx->seen & SEEN_CALL)
+		ret |= 1 << ARM_LR;
+#endif
+	if (ctx->seen & (SEEN_DATA | SEEN_SKB))
+		ret |= 1 << r_skb;
+	if (ctx->seen & SEEN_DATA)
+		ret |= (1 << r_skb_data) | (1 << r_skb_hl);
+	if (ctx->seen & SEEN_X)
+		ret |= 1 << r_X;
+
+	return ret;
+}
+
+static inline int mem_words_used(struct jit_ctx *ctx)
+{
+	/* yes, we do waste some stack space IF there are "holes" in the set" */
+	return fls(ctx->seen & SEEN_MEM);
+}
+
+static inline bool is_load_to_a(u16 inst)
+{
+	switch (inst) {
+	case BPF_S_LD_W_LEN:
+	case BPF_S_LD_W_ABS:
+	case BPF_S_LD_H_ABS:
+	case BPF_S_LD_B_ABS:
+	case BPF_S_ANC_CPU:
+	case BPF_S_ANC_IFINDEX:
+	case BPF_S_ANC_MARK:
+	case BPF_S_ANC_PROTOCOL:
+	case BPF_S_ANC_RXHASH:
+	case BPF_S_ANC_QUEUE:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static void build_prologue(struct jit_ctx *ctx)
+{
+	u16 reg_set = saved_regs(ctx);
+	u16 first_inst = ctx->skf->insns[0].code;
+	u16 off;
+
+#ifdef CONFIG_FRAME_POINTER
+	emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx);
+	emit(ARM_PUSH(reg_set), ctx);
+	emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx);
+#else
+	if (reg_set)
+		emit(ARM_PUSH(reg_set), ctx);
+#endif
+
+	if (ctx->seen & (SEEN_DATA | SEEN_SKB))
+		emit(ARM_MOV_R(r_skb, ARM_R0), ctx);
+
+	if (ctx->seen & SEEN_DATA) {
+		off = offsetof(struct sk_buff, data);
+		emit(ARM_LDR_I(r_skb_data, r_skb, off), ctx);
+		/* headlen = len - data_len */
+		off = offsetof(struct sk_buff, len);
+		emit(ARM_LDR_I(r_skb_hl, r_skb, off), ctx);
+		off = offsetof(struct sk_buff, data_len);
+		emit(ARM_LDR_I(r_scratch, r_skb, off), ctx);
+		emit(ARM_SUB_R(r_skb_hl, r_skb_hl, r_scratch), ctx);
+	}
+
+	if (ctx->flags & FLAG_NEED_X_RESET)
+		emit(ARM_MOV_I(r_X, 0), ctx);
+
+	/* do not leak kernel data to userspace */
+	if ((first_inst != BPF_S_RET_K) && !(is_load_to_a(first_inst)))
+		emit(ARM_MOV_I(r_A, 0), ctx);
+
+	/* stack space for the BPF_MEM words */
+	if (ctx->seen & SEEN_MEM)
+		emit(ARM_SUB_I(ARM_SP, ARM_SP, mem_words_used(ctx) * 4), ctx);
+}
+
+static void build_epilogue(struct jit_ctx *ctx)
+{
+	u16 reg_set = saved_regs(ctx);
+
+	if (ctx->seen & SEEN_MEM)
+		emit(ARM_ADD_I(ARM_SP, ARM_SP, mem_words_used(ctx) * 4), ctx);
+
+	reg_set &= ~(1 << ARM_LR);
+
+#ifdef CONFIG_FRAME_POINTER
+	/* the first instruction of the prologue was: mov ip, sp */
+	reg_set &= ~(1 << ARM_IP);
+	reg_set |= (1 << ARM_SP);
+	emit(ARM_LDM(ARM_SP, reg_set), ctx);
+#else
+	if (reg_set) {
+		if (ctx->seen & SEEN_CALL)
+			reg_set |= 1 << ARM_PC;
+		emit(ARM_POP(reg_set), ctx);
+	}
+
+	if (!(ctx->seen & SEEN_CALL))
+		emit(ARM_BX(ARM_LR), ctx);
+#endif
+}
+
+static int16_t imm8m(u32 x)
+{
+	u32 rot;
+
+	for (rot = 0; rot < 16; rot++)
+		if ((x & ~ror32(0xff, 2 * rot)) == 0)
+			return rol32(x, 2 * rot) | (rot << 8);
+
+	return -1;
+}
+
+#if __LINUX_ARM_ARCH__ < 7
+
+static u16 imm_offset(u32 k, struct jit_ctx *ctx)
+{
+	unsigned i = 0, offset;
+	u16 imm;
+
+	/* on the "fake" run we just count them (duplicates included) */
+	if (ctx->target == NULL) {
+		ctx->imm_count++;
+		return 0;
+	}
+
+	while ((i < ctx->imm_count) && ctx->imms[i]) {
+		if (ctx->imms[i] == k)
+			break;
+		i++;
+	}
+
+	if (ctx->imms[i] == 0)
+		ctx->imms[i] = k;
+
+	/* constants go just after the epilogue */
+	offset =  ctx->offsets[ctx->skf->len];
+	offset += ctx->prologue_bytes;
+	offset += ctx->epilogue_bytes;
+	offset += i * 4;
+
+	ctx->target[offset / 4] = k;
+
+	/* PC in ARM mode == address of the instruction + 8 */
+	imm = offset - (8 + ctx->idx * 4);
+
+	return imm;
+}
+
+#endif /* __LINUX_ARM_ARCH__ */
+
+/*
+ * Move an immediate that's not an imm8m to a core register.
+ */
+static inline void emit_mov_i_no8m(int rd, u32 val, struct jit_ctx *ctx)
+{
+#if __LINUX_ARM_ARCH__ < 7
+	emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx);
+#else
+	emit(ARM_MOVW(rd, val & 0xffff), ctx);
+	if (val > 0xffff)
+		emit(ARM_MOVT(rd, val >> 16), ctx);
+#endif
+}
+
+static inline void emit_mov_i(int rd, u32 val, struct jit_ctx *ctx)
+{
+	int imm12 = imm8m(val);
+
+	if (imm12 >= 0)
+		emit(ARM_MOV_I(rd, imm12), ctx);
+	else
+		emit_mov_i_no8m(rd, val, ctx);
+}
+
+#if __LINUX_ARM_ARCH__ < 6
+
+static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
+{
+	_emit(cond, ARM_LDRB_I(ARM_R3, r_addr, 1), ctx);
+	_emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx);
+	_emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 3), ctx);
+	_emit(cond, ARM_LSL_I(ARM_R3, ARM_R3, 16), ctx);
+	_emit(cond, ARM_LDRB_I(ARM_R0, r_addr, 2), ctx);
+	_emit(cond, ARM_ORR_S(ARM_R3, ARM_R3, ARM_R1, SRTYPE_LSL, 24), ctx);
+	_emit(cond, ARM_ORR_R(ARM_R3, ARM_R3, ARM_R2), ctx);
+	_emit(cond, ARM_ORR_S(r_res, ARM_R3, ARM_R0, SRTYPE_LSL, 8), ctx);
+}
+
+static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
+{
+	_emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx);
+	_emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 1), ctx);
+	_emit(cond, ARM_ORR_S(r_res, ARM_R2, ARM_R1, SRTYPE_LSL, 8), ctx);
+}
+
+static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx)
+{
+	emit(ARM_LSL_R(ARM_R1, r_src, 8), ctx);
+	emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSL, 8), ctx);
+	emit(ARM_LSL_I(r_dst, r_dst, 8), ctx);
+	emit(ARM_LSL_R(r_dst, r_dst, 8), ctx);
+}
+
+#else  /* ARMv6+ */
+
+static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
+{
+	_emit(cond, ARM_LDR_I(r_res, r_addr, 0), ctx);
+#ifdef __LITTLE_ENDIAN
+	_emit(cond, ARM_REV(r_res, r_res), ctx);
+#endif
+}
+
+static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
+{
+	_emit(cond, ARM_LDRH_I(r_res, r_addr, 0), ctx);
+#ifdef __LITTLE_ENDIAN
+	_emit(cond, ARM_REV16(r_res, r_res), ctx);
+#endif
+}
+
+static inline void emit_swap16(u8 r_dst __maybe_unused,
+			       u8 r_src __maybe_unused,
+			       struct jit_ctx *ctx __maybe_unused)
+{
+#ifdef __LITTLE_ENDIAN
+	emit(ARM_REV16(r_dst, r_src), ctx);
+#endif
+}
+
+#endif /* __LINUX_ARM_ARCH__ < 6 */
+
+
+/* Compute the immediate value for a PC-relative branch. */
+static inline u32 b_imm(unsigned tgt, struct jit_ctx *ctx)
+{
+	u32 imm;
+
+	if (ctx->target == NULL)
+		return 0;
+	/*
+	 * BPF allows only forward jumps and the offset of the target is
+	 * still the one computed during the first pass.
+	 */
+	imm  = ctx->offsets[tgt] + ctx->prologue_bytes - (ctx->idx * 4 + 8);
+
+	return imm >> 2;
+}
+
+#define OP_IMM3(op, r1, r2, imm_val, ctx)				\
+	do {								\
+		imm12 = imm8m(imm_val);					\
+		if (imm12 < 0) {					\
+			emit_mov_i_no8m(r_scratch, imm_val, ctx);	\
+			emit(op ## _R((r1), (r2), r_scratch), ctx);	\
+		} else {						\
+			emit(op ## _I((r1), (r2), imm12), ctx);		\
+		}							\
+	} while (0)
+
+static inline void emit_err_ret(u8 cond, struct jit_ctx *ctx)
+{
+	if (ctx->ret0_fp_idx >= 0) {
+		_emit(cond, ARM_B(b_imm(ctx->ret0_fp_idx, ctx)), ctx);
+		/* NOP to keep the size constant between passes */
+		emit(ARM_MOV_R(ARM_R0, ARM_R0), ctx);
+	} else {
+		_emit(cond, ARM_MOV_I(ARM_R0, 0), ctx);
+		_emit(cond, ARM_B(b_imm(ctx->skf->len, ctx)), ctx);
+	}
+}
+
+static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
+{
+#if __LINUX_ARM_ARCH__ < 5
+	emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
+
+	if (elf_hwcap & HWCAP_THUMB)
+		emit(ARM_BX(tgt_reg), ctx);
+	else
+		emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx);
+#else
+	emit(ARM_BLX_R(tgt_reg), ctx);
+#endif
+}
+
+static inline void emit_udiv(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx)
+{
+#if __LINUX_ARM_ARCH__ == 7
+	if (elf_hwcap & HWCAP_IDIVA) {
+		emit(ARM_UDIV(rd, rm, rn), ctx);
+		return;
+	}
+#endif
+	if (rm != ARM_R0)
+		emit(ARM_MOV_R(ARM_R0, rm), ctx);
+	if (rn != ARM_R1)
+		emit(ARM_MOV_R(ARM_R1, rn), ctx);
+
+	ctx->seen |= SEEN_CALL;
+	emit_mov_i(ARM_R3, (u32)jit_udiv, ctx);
+	emit_blx_r(ARM_R3, ctx);
+
+	if (rd != ARM_R0)
+		emit(ARM_MOV_R(rd, ARM_R0), ctx);
+}
+
+static inline void update_on_xread(struct jit_ctx *ctx)
+{
+	if (!(ctx->seen & SEEN_X))
+		ctx->flags |= FLAG_NEED_X_RESET;
+
+	ctx->seen |= SEEN_X;
+}
+
+static int build_body(struct jit_ctx *ctx)
+{
+	void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
+	const struct sk_filter *prog = ctx->skf;
+	const struct sock_filter *inst;
+	unsigned i, load_order, off, condt;
+	int imm12;
+	u32 k;
+
+	for (i = 0; i < prog->len; i++) {
+		inst = &(prog->insns[i]);
+		/* K as an immediate value operand */
+		k = inst->k;
+
+		/* compute offsets only in the fake pass */
+		if (ctx->target == NULL)
+			ctx->offsets[i] = ctx->idx * 4;
+
+		switch (inst->code) {
+		case BPF_S_LD_IMM:
+			emit_mov_i(r_A, k, ctx);
+			break;
+		case BPF_S_LD_W_LEN:
+			ctx->seen |= SEEN_SKB;
+			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
+			emit(ARM_LDR_I(r_A, r_skb,
+				       offsetof(struct sk_buff, len)), ctx);
+			break;
+		case BPF_S_LD_MEM:
+			/* A = scratch[k] */
+			ctx->seen |= SEEN_MEM_WORD(k);
+			emit(ARM_LDR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
+			break;
+		case BPF_S_LD_W_ABS:
+			load_order = 2;
+			goto load;
+		case BPF_S_LD_H_ABS:
+			load_order = 1;
+			goto load;
+		case BPF_S_LD_B_ABS:
+			load_order = 0;
+load:
+			/* the interpreter will deal with the negative K */
+			if ((int)k < 0)
+				return -ENOTSUPP;
+			emit_mov_i(r_off, k, ctx);
+load_common:
+			ctx->seen |= SEEN_DATA | SEEN_CALL;
+
+			if (load_order > 0) {
+				emit(ARM_SUB_I(r_scratch, r_skb_hl,
+					       1 << load_order), ctx);
+				emit(ARM_CMP_R(r_scratch, r_off), ctx);
+				condt = ARM_COND_HS;
+			} else {
+				emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
+				condt = ARM_COND_HI;
+			}
+
+			_emit(condt, ARM_ADD_R(r_scratch, r_off, r_skb_data),
+			      ctx);
+
+			if (load_order == 0)
+				_emit(condt, ARM_LDRB_I(r_A, r_scratch, 0),
+				      ctx);
+			else if (load_order == 1)
+				emit_load_be16(condt, r_A, r_scratch, ctx);
+			else if (load_order == 2)
+				emit_load_be32(condt, r_A, r_scratch, ctx);
+
+			_emit(condt, ARM_B(b_imm(i + 1, ctx)), ctx);
+
+			/* the slowpath */
+			emit_mov_i(ARM_R3, (u32)load_func[load_order], ctx);
+			emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
+			/* the offset is already in R1 */
+			emit_blx_r(ARM_R3, ctx);
+			/* check the result of skb_copy_bits */
+			emit(ARM_CMP_I(ARM_R1, 0), ctx);
+			emit_err_ret(ARM_COND_NE, ctx);
+			emit(ARM_MOV_R(r_A, ARM_R0), ctx);
+			break;
+		case BPF_S_LD_W_IND:
+			load_order = 2;
+			goto load_ind;
+		case BPF_S_LD_H_IND:
+			load_order = 1;
+			goto load_ind;
+		case BPF_S_LD_B_IND:
+			load_order = 0;
+load_ind:
+			OP_IMM3(ARM_ADD, r_off, r_X, k, ctx);
+			goto load_common;
+		case BPF_S_LDX_IMM:
+			ctx->seen |= SEEN_X;
+			emit_mov_i(r_X, k, ctx);
+			break;
+		case BPF_S_LDX_W_LEN:
+			ctx->seen |= SEEN_X | SEEN_SKB;
+			emit(ARM_LDR_I(r_X, r_skb,
+				       offsetof(struct sk_buff, len)), ctx);
+			break;
+		case BPF_S_LDX_MEM:
+			ctx->seen |= SEEN_X | SEEN_MEM_WORD(k);
+			emit(ARM_LDR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
+			break;
+		case BPF_S_LDX_B_MSH:
+			/* x = ((*(frame + k)) & 0xf) << 2; */
+			ctx->seen |= SEEN_X | SEEN_DATA | SEEN_CALL;
+			/* the interpreter should deal with the negative K */
+			if (k < 0)
+				return -1;
+			/* offset in r1: we might have to take the slow path */
+			emit_mov_i(r_off, k, ctx);
+			emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
+
+			/* load in r0: common with the slowpath */
+			_emit(ARM_COND_HI, ARM_LDRB_R(ARM_R0, r_skb_data,
+						      ARM_R1), ctx);
+			/*
+			 * emit_mov_i() might generate one or two instructions,
+			 * the same holds for emit_blx_r()
+			 */
+			_emit(ARM_COND_HI, ARM_B(b_imm(i + 1, ctx) - 2), ctx);
+
+			emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
+			/* r_off is r1 */
+			emit_mov_i(ARM_R3, (u32)jit_get_skb_b, ctx);
+			emit_blx_r(ARM_R3, ctx);
+			/* check the return value of skb_copy_bits */
+			emit(ARM_CMP_I(ARM_R1, 0), ctx);
+			emit_err_ret(ARM_COND_NE, ctx);
+
+			emit(ARM_AND_I(r_X, ARM_R0, 0x00f), ctx);
+			emit(ARM_LSL_I(r_X, r_X, 2), ctx);
+			break;
+		case BPF_S_ST:
+			ctx->seen |= SEEN_MEM_WORD(k);
+			emit(ARM_STR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
+			break;
+		case BPF_S_STX:
+			update_on_xread(ctx);
+			ctx->seen |= SEEN_MEM_WORD(k);
+			emit(ARM_STR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
+			break;
+		case BPF_S_ALU_ADD_K:
+			/* A += K */
+			OP_IMM3(ARM_ADD, r_A, r_A, k, ctx);
+			break;
+		case BPF_S_ALU_ADD_X:
+			update_on_xread(ctx);
+			emit(ARM_ADD_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_SUB_K:
+			/* A -= K */
+			OP_IMM3(ARM_SUB, r_A, r_A, k, ctx);
+			break;
+		case BPF_S_ALU_SUB_X:
+			update_on_xread(ctx);
+			emit(ARM_SUB_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_MUL_K:
+			/* A *= K */
+			emit_mov_i(r_scratch, k, ctx);
+			emit(ARM_MUL(r_A, r_A, r_scratch), ctx);
+			break;
+		case BPF_S_ALU_MUL_X:
+			update_on_xread(ctx);
+			emit(ARM_MUL(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_DIV_K:
+			/* current k == reciprocal_value(userspace k) */
+			emit_mov_i(r_scratch, k, ctx);
+			/* A = top 32 bits of the product */
+			emit(ARM_UMULL(r_scratch, r_A, r_A, r_scratch), ctx);
+			break;
+		case BPF_S_ALU_DIV_X:
+			update_on_xread(ctx);
+			emit(ARM_CMP_I(r_X, 0), ctx);
+			emit_err_ret(ARM_COND_EQ, ctx);
+			emit_udiv(r_A, r_A, r_X, ctx);
+			break;
+		case BPF_S_ALU_OR_K:
+			/* A |= K */
+			OP_IMM3(ARM_ORR, r_A, r_A, k, ctx);
+			break;
+		case BPF_S_ALU_OR_X:
+			update_on_xread(ctx);
+			emit(ARM_ORR_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_AND_K:
+			/* A &= K */
+			OP_IMM3(ARM_AND, r_A, r_A, k, ctx);
+			break;
+		case BPF_S_ALU_AND_X:
+			update_on_xread(ctx);
+			emit(ARM_AND_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_LSH_K:
+			if (unlikely(k > 31))
+				return -1;
+			emit(ARM_LSL_I(r_A, r_A, k), ctx);
+			break;
+		case BPF_S_ALU_LSH_X:
+			update_on_xread(ctx);
+			emit(ARM_LSL_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_RSH_K:
+			if (unlikely(k > 31))
+				return -1;
+			emit(ARM_LSR_I(r_A, r_A, k), ctx);
+			break;
+		case BPF_S_ALU_RSH_X:
+			update_on_xread(ctx);
+			emit(ARM_LSR_R(r_A, r_A, r_X), ctx);
+			break;
+		case BPF_S_ALU_NEG:
+			/* A = -A */
+			emit(ARM_RSB_I(r_A, r_A, 0), ctx);
+			break;
+		case BPF_S_JMP_JA:
+			/* pc += K */
+			emit(ARM_B(b_imm(i + k + 1, ctx)), ctx);
+			break;
+		case BPF_S_JMP_JEQ_K:
+			/* pc += (A == K) ? pc->jt : pc->jf */
+			condt  = ARM_COND_EQ;
+			goto cmp_imm;
+		case BPF_S_JMP_JGT_K:
+			/* pc += (A > K) ? pc->jt : pc->jf */
+			condt  = ARM_COND_HI;
+			goto cmp_imm;
+		case BPF_S_JMP_JGE_K:
+			/* pc += (A >= K) ? pc->jt : pc->jf */
+			condt  = ARM_COND_HS;
+cmp_imm:
+			imm12 = imm8m(k);
+			if (imm12 < 0) {
+				emit_mov_i_no8m(r_scratch, k, ctx);
+				emit(ARM_CMP_R(r_A, r_scratch), ctx);
+			} else {
+				emit(ARM_CMP_I(r_A, imm12), ctx);
+			}
+cond_jump:
+			if (inst->jt)
+				_emit(condt, ARM_B(b_imm(i + inst->jt + 1,
+						   ctx)), ctx);
+			if (inst->jf)
+				_emit(condt ^ 1, ARM_B(b_imm(i + inst->jf + 1,
+							     ctx)), ctx);
+			break;
+		case BPF_S_JMP_JEQ_X:
+			/* pc += (A == X) ? pc->jt : pc->jf */
+			condt   = ARM_COND_EQ;
+			goto cmp_x;
+		case BPF_S_JMP_JGT_X:
+			/* pc += (A > X) ? pc->jt : pc->jf */
+			condt   = ARM_COND_HI;
+			goto cmp_x;
+		case BPF_S_JMP_JGE_X:
+			/* pc += (A >= X) ? pc->jt : pc->jf */
+			condt   = ARM_COND_CS;
+cmp_x:
+			update_on_xread(ctx);
+			emit(ARM_CMP_R(r_A, r_X), ctx);
+			goto cond_jump;
+		case BPF_S_JMP_JSET_K:
+			/* pc += (A & K) ? pc->jt : pc->jf */
+			condt  = ARM_COND_NE;
+			/* not set iff all zeroes iff Z==1 iff EQ */
+
+			imm12 = imm8m(k);
+			if (imm12 < 0) {
+				emit_mov_i_no8m(r_scratch, k, ctx);
+				emit(ARM_TST_R(r_A, r_scratch), ctx);
+			} else {
+				emit(ARM_TST_I(r_A, imm12), ctx);
+			}
+			goto cond_jump;
+		case BPF_S_JMP_JSET_X:
+			/* pc += (A & X) ? pc->jt : pc->jf */
+			update_on_xread(ctx);
+			condt  = ARM_COND_NE;
+			emit(ARM_TST_R(r_A, r_X), ctx);
+			goto cond_jump;
+		case BPF_S_RET_A:
+			emit(ARM_MOV_R(ARM_R0, r_A), ctx);
+			goto b_epilogue;
+		case BPF_S_RET_K:
+			if ((k == 0) && (ctx->ret0_fp_idx < 0))
+				ctx->ret0_fp_idx = i;
+			emit_mov_i(ARM_R0, k, ctx);
+b_epilogue:
+			if (i != ctx->skf->len - 1)
+				emit(ARM_B(b_imm(prog->len, ctx)), ctx);
+			break;
+		case BPF_S_MISC_TAX:
+			/* X = A */
+			ctx->seen |= SEEN_X;
+			emit(ARM_MOV_R(r_X, r_A), ctx);
+			break;
+		case BPF_S_MISC_TXA:
+			/* A = X */
+			update_on_xread(ctx);
+			emit(ARM_MOV_R(r_A, r_X), ctx);
+			break;
+		case BPF_S_ANC_PROTOCOL:
+			/* A = ntohs(skb->protocol) */
+			ctx->seen |= SEEN_SKB;
+			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
+						  protocol) != 2);
+			off = offsetof(struct sk_buff, protocol);
+			emit(ARM_LDRH_I(r_scratch, r_skb, off), ctx);
+			emit_swap16(r_A, r_scratch, ctx);
+			break;
+		case BPF_S_ANC_CPU:
+			/* r_scratch = current_thread_info() */
+			OP_IMM3(ARM_BIC, r_scratch, ARM_SP, THREAD_SIZE - 1, ctx);
+			/* A = current_thread_info()->cpu */
+			BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info, cpu) != 4);
+			off = offsetof(struct thread_info, cpu);
+			emit(ARM_LDR_I(r_A, r_scratch, off), ctx);
+			break;
+		case BPF_S_ANC_IFINDEX:
+			/* A = skb->dev->ifindex */
+			ctx->seen |= SEEN_SKB;
+			off = offsetof(struct sk_buff, dev);
+			emit(ARM_LDR_I(r_scratch, r_skb, off), ctx);
+
+			emit(ARM_CMP_I(r_scratch, 0), ctx);
+			emit_err_ret(ARM_COND_EQ, ctx);
+
+			BUILD_BUG_ON(FIELD_SIZEOF(struct net_device,
+						  ifindex) != 4);
+			off = offsetof(struct net_device, ifindex);
+			emit(ARM_LDR_I(r_A, r_scratch, off), ctx);
+			break;
+		case BPF_S_ANC_MARK:
+			ctx->seen |= SEEN_SKB;
+			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
+			off = offsetof(struct sk_buff, mark);
+			emit(ARM_LDR_I(r_A, r_skb, off), ctx);
+			break;
+		case BPF_S_ANC_RXHASH:
+			ctx->seen |= SEEN_SKB;
+			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, rxhash) != 4);
+			off = offsetof(struct sk_buff, rxhash);
+			emit(ARM_LDR_I(r_A, r_skb, off), ctx);
+			break;
+		case BPF_S_ANC_QUEUE:
+			ctx->seen |= SEEN_SKB;
+			BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
+						  queue_mapping) != 2);
+			BUILD_BUG_ON(offsetof(struct sk_buff,
+					      queue_mapping) > 0xff);
+			off = offsetof(struct sk_buff, queue_mapping);
+			emit(ARM_LDRH_I(r_A, r_skb, off), ctx);
+			break;
+		default:
+			return -1;
+		}
+	}
+
+	/* compute offsets only during the first pass */
+	if (ctx->target == NULL)
+		ctx->offsets[i] = ctx->idx * 4;
+
+	return 0;
+}
+
+
+void bpf_jit_compile(struct sk_filter *fp)
+{
+	struct jit_ctx ctx;
+	unsigned tmp_idx;
+	unsigned alloc_size;
+
+	if (!bpf_jit_enable)
+		return;
+
+	memset(&ctx, 0, sizeof(ctx));
+	ctx.skf		= fp;
+	ctx.ret0_fp_idx = -1;
+
+	ctx.offsets = kzalloc(GFP_KERNEL, 4 * (ctx.skf->len + 1));
+	if (ctx.offsets == NULL)
+		return;
+
+	/* fake pass to fill in the ctx->seen */
+	if (unlikely(build_body(&ctx)))
+		goto out;
+
+	tmp_idx = ctx.idx;
+	build_prologue(&ctx);
+	ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
+
+#if __LINUX_ARM_ARCH__ < 7
+	tmp_idx = ctx.idx;
+	build_epilogue(&ctx);
+	ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4;
+
+	ctx.idx += ctx.imm_count;
+	if (ctx.imm_count) {
+		ctx.imms = kzalloc(GFP_KERNEL, 4 * ctx.imm_count);
+		if (ctx.imms == NULL)
+			goto out;
+	}
+#else
+	/* there's nothing after the epilogue on ARMv7 */
+	build_epilogue(&ctx);
+#endif
+
+	alloc_size = 4 * ctx.idx;
+	ctx.target = module_alloc(max(sizeof(struct work_struct),
+				      alloc_size));
+	if (unlikely(ctx.target == NULL))
+		goto out;
+
+	ctx.idx = 0;
+	build_prologue(&ctx);
+	build_body(&ctx);
+	build_epilogue(&ctx);
+
+	flush_icache_range((u32)ctx.target, (u32)(ctx.target + ctx.idx));
+
+#if __LINUX_ARM_ARCH__ < 7
+	if (ctx.imm_count)
+		kfree(ctx.imms);
+#endif
+
+	if (bpf_jit_enable > 1)
+		print_hex_dump(KERN_INFO, "BPF JIT code: ",
+			       DUMP_PREFIX_ADDRESS, 16, 4, ctx.target,
+			       alloc_size, false);
+
+	fp->bpf_func = (void *)ctx.target;
+out:
+	kfree(ctx.offsets);
+	return;
+}
+
+static void bpf_jit_free_worker(struct work_struct *work)
+{
+	module_free(NULL, work);
+}
+
+void bpf_jit_free(struct sk_filter *fp)
+{
+	struct work_struct *work;
+
+	if (fp->bpf_func != sk_run_filter) {
+		work = (struct work_struct *)fp->bpf_func;
+
+		INIT_WORK(work, bpf_jit_free_worker);
+		schedule_work(work);
+	}
+}
+
diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
new file mode 100644
index 0000000..99ae5e3
--- /dev/null
+++ b/arch/arm/net/bpf_jit_32.h
@@ -0,0 +1,190 @@
+/*
+ * Just-In-Time compiler for BPF filters on 32bit ARM
+ *
+ * Copyright (c) 2011 Mircea Gherzan <mgherzan at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; version 2 of the License.
+ */
+
+#ifndef PFILTER_OPCODES_ARM_H
+#define PFILTER_OPCODES_ARM_H
+
+#define ARM_R0	0
+#define ARM_R1	1
+#define ARM_R2	2
+#define ARM_R3	3
+#define ARM_R4	4
+#define ARM_R5	5
+#define ARM_R6	6
+#define ARM_R7	7
+#define ARM_R8	8
+#define ARM_R9	9
+#define ARM_R10	10
+#define ARM_FP	11
+#define ARM_IP	12
+#define ARM_SP	13
+#define ARM_LR	14
+#define ARM_PC	15
+
+#define ARM_COND_EQ		0x0
+#define ARM_COND_NE		0x1
+#define ARM_COND_CS		0x2
+#define ARM_COND_HS		ARM_COND_CS
+#define ARM_COND_CC		0x3
+#define ARM_COND_LO		ARM_COND_CC
+#define ARM_COND_MI		0x4
+#define ARM_COND_PL		0x5
+#define ARM_COND_VS		0x6
+#define ARM_COND_VC		0x7
+#define ARM_COND_HI		0x8
+#define ARM_COND_LS		0x9
+#define ARM_COND_GE		0xa
+#define ARM_COND_LT		0xb
+#define ARM_COND_GT		0xc
+#define ARM_COND_LE		0xd
+#define ARM_COND_AL		0xe
+
+/* register shift types */
+#define SRTYPE_LSL		0
+#define SRTYPE_LSR		1
+#define SRTYPE_ASR		2
+#define SRTYPE_ROR		3
+
+#define ARM_INST_ADD_R		0x00800000
+#define ARM_INST_ADD_I		0x02800000
+
+#define ARM_INST_AND_R		0x00000000
+#define ARM_INST_AND_I		0x02000000
+
+#define ARM_INST_BIC_R		0x01c00000
+#define ARM_INST_BIC_I		0x03c00000
+
+#define ARM_INST_B		0x0a000000
+#define ARM_INST_BX		0x012FFF10
+#define ARM_INST_BLX_R		0x012fff30
+
+#define ARM_INST_CMP_R		0x01500000
+#define ARM_INST_CMP_I		0x03500000
+
+#define ARM_INST_LDRB_I		0x05d00000
+#define ARM_INST_LDRB_R		0x07d00000
+#define ARM_INST_LDRH_I		0x01d000b0
+#define ARM_INST_LDR_I		0x05900000
+
+#define ARM_INST_LDM		0x08900000
+
+#define ARM_INST_LSL_I		0x01a00000
+#define ARM_INST_LSL_R		0x01a00010
+
+#define ARM_INST_LSR_I		0x01a00020
+#define ARM_INST_LSR_R		0x01a00030
+
+#define ARM_INST_MOV_R		0x01a00000
+#define ARM_INST_MOV_I		0x03a00000
+#define ARM_INST_MOVW		0x03000000
+#define ARM_INST_MOVT		0x03400000
+
+#define ARM_INST_MUL		0x00000090
+
+#define ARM_INST_POP		0x08bd0000
+#define ARM_INST_PUSH		0x092d0000
+
+#define ARM_INST_ORR_R		0x01800000
+#define ARM_INST_ORR_I		0x03800000
+
+#define ARM_INST_REV		0x06bf0f30
+#define ARM_INST_REV16		0x06bf0fb0
+
+#define ARM_INST_RSB_I		0x02600000
+
+#define ARM_INST_SUB_R		0x00400000
+#define ARM_INST_SUB_I		0x02400000
+
+#define ARM_INST_STR_I		0x05800000
+
+#define ARM_INST_TST_R		0x01100000
+#define ARM_INST_TST_I		0x03100000
+
+#define ARM_INST_UDIV		0x0730f010
+
+#define ARM_INST_UMULL		0x00800090
+
+/* register */
+#define _AL3_R(op, rd, rn, rm)	((op ## _R) | (rd) << 12 | (rn) << 16 | (rm))
+/* immediate */
+#define _AL3_I(op, rd, rn, imm)	((op ## _I) | (rd) << 12 | (rn) << 16 | (imm))
+
+#define ARM_ADD_R(rd, rn, rm)	_AL3_R(ARM_INST_ADD, rd, rn, rm)
+#define ARM_ADD_I(rd, rn, imm)	_AL3_I(ARM_INST_ADD, rd, rn, imm)
+
+#define ARM_AND_R(rd, rn, rm)	_AL3_R(ARM_INST_AND, rd, rn, rm)
+#define ARM_AND_I(rd, rn, imm)	_AL3_I(ARM_INST_AND, rd, rn, imm)
+
+#define ARM_BIC_R(rd, rn, rm)	_AL3_R(ARM_INST_BIC, rd, rn, rm)
+#define ARM_BIC_I(rd, rn, imm)	_AL3_I(ARM_INST_BIC, rd, rn, imm)
+
+#define ARM_B(imm24)		(ARM_INST_B | ((imm24) & 0xffffff))
+#define ARM_BX(rm)		(ARM_INST_BX | (rm))
+#define ARM_BLX_R(rm)		(ARM_INST_BLX_R | (rm))
+
+#define ARM_CMP_R(rn, rm)	_AL3_R(ARM_INST_CMP, 0, rn, rm)
+#define ARM_CMP_I(rn, imm)	_AL3_I(ARM_INST_CMP, 0, rn, imm)
+
+#define ARM_LDR_I(rt, rn, off)	(ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \
+				 | (off))
+#define ARM_LDRB_I(rt, rn, off)	(ARM_INST_LDRB_I | (rt) << 12 | (rn) << 16 \
+				 | (off))
+#define ARM_LDRB_R(rt, rn, rm)	(ARM_INST_LDRB_R | (rt) << 12 | (rn) << 16 \
+				 | (rm))
+#define ARM_LDRH_I(rt, rn, off)	(ARM_INST_LDRH_I | (rt) << 12 | (rn) << 16 \
+				 | (((off) & 0xf0) << 4) | ((off) & 0xf))
+
+#define ARM_LDM(rn, regs)	(ARM_INST_LDM | (rn) << 16 | (regs))
+
+#define ARM_LSL_R(rd, rn, rm)	(_AL3_R(ARM_INST_LSL, rd, 0, rn) | (rm) << 8)
+#define ARM_LSL_I(rd, rn, imm)	(_AL3_I(ARM_INST_LSL, rd, 0, rn) | (imm) << 7)
+
+#define ARM_LSR_R(rd, rn, rm)	(_AL3_R(ARM_INST_LSR, rd, 0, rn) | (rm) << 8)
+#define ARM_LSR_I(rd, rn, imm)	(_AL3_I(ARM_INST_LSR, rd, 0, rn) | (imm) << 7)
+
+#define ARM_MOV_R(rd, rm)	_AL3_R(ARM_INST_MOV, rd, 0, rm)
+#define ARM_MOV_I(rd, imm)	_AL3_I(ARM_INST_MOV, rd, 0, imm)
+
+#define ARM_MOVW(rd, imm)	\
+	(ARM_INST_MOVW | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
+
+#define ARM_MOVT(rd, imm)	\
+	(ARM_INST_MOVT | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
+
+#define ARM_MUL(rd, rm, rn)	(ARM_INST_MUL | (rd) << 16 | (rm) << 8 | (rn))
+
+#define ARM_POP(regs)		(ARM_INST_POP | (regs))
+#define ARM_PUSH(regs)		(ARM_INST_PUSH | (regs))
+
+#define ARM_ORR_R(rd, rn, rm)	_AL3_R(ARM_INST_ORR, rd, rn, rm)
+#define ARM_ORR_I(rd, rn, imm)	_AL3_I(ARM_INST_ORR, rd, rn, imm)
+#define ARM_ORR_S(rd, rn, rm, type, rs)	\
+	(ARM_ORR_R(rd, rn, rm) | (type) << 5 | (rs) << 7)
+
+#define ARM_REV(rd, rm)		(ARM_INST_REV | (rd) << 12 | (rm))
+#define ARM_REV16(rd, rm)	(ARM_INST_REV16 | (rd) << 12 | (rm))
+
+#define ARM_RSB_I(rd, rn, imm)	_AL3_I(ARM_INST_RSB, rd, rn, imm)
+
+#define ARM_SUB_R(rd, rn, rm)	_AL3_R(ARM_INST_SUB, rd, rn, rm)
+#define ARM_SUB_I(rd, rn, imm)	_AL3_I(ARM_INST_SUB, rd, rn, imm)
+
+#define ARM_STR_I(rt, rn, off)	(ARM_INST_STR_I | (rt) << 12 | (rn) << 16 \
+				 | (off))
+
+#define ARM_TST_R(rn, rm)	_AL3_R(ARM_INST_TST, 0, rn, rm)
+#define ARM_TST_I(rn, imm)	_AL3_I(ARM_INST_TST, 0, rn, imm)
+
+#define ARM_UDIV(rd, rn, rm)	(ARM_INST_UDIV | (rd) << 16 | (rn) | (rm) << 8)
+
+#define ARM_UMULL(rd_lo, rd_hi, rn, rm)	(ARM_INST_UMULL | (rd_hi) << 16 \
+					 | (rd_lo) << 12 | (rm) << 8 | rn)
+
+#endif /* PFILTER_OPCODES_ARM_H */
-- 
1.7.9.1



From tpiepho at gmail.com  Fri Mar 16 17:28:54 2012
From: tpiepho at gmail.com (Trent Piepho)
Date: Fri, 16 Mar 2012 17:28:54 -0400
Subject: [alsa-devel] [PATCH v5 8/8] ASoC: fsl: add imx-sgtl5000 machine
 driver
In-Reply-To: <20120316192110.GH3158@opensource.wolfsonmicro.com>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-9-git-send-email-shawn.guo@linaro.org>
 <CA+7tXihmfBQCgvuY0rx5v4w-bcwYK+7kP9v29w36N-Rc9KSQ+A@mail.gmail.com>
 <20120316111814.GA7860@S2101-09.ap.freescale.net>
 <20120316192110.GH3158@opensource.wolfsonmicro.com>
Message-ID: <CA+7tXih-omxaDq6dSKBeOaZ7YRWDVSQnMY=eJZ0-YumOBG=oCA@mail.gmail.com>

On Fri, Mar 16, 2012 at 3:21 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Fri, Mar 16, 2012 at 07:18:18PM +0800, Shawn Guo wrote:
>
>> Maybe having "fsl,imx-audio-xxx" for machine drivers backed by SSI,
>> and "fsl,imx-esai-audio-xxx" for the ones backed by ESAI?

It seems non-orthogonal to me that ESAI has esai in the name but SSI
does not have ssi.

> Alternatively if the SSI and ESAI devices are compatible enough at the
> ASoC API level (or can be identified by the driver just by looking at
> the DAI that's referenced without too much pain) the CPU DAI could just
> be linked to either type of DAI (probably with a more generic name for
> the property).
>
> But either way works fine, and obviously you're going to end up with
> more complex systems which use a completely custom binding anyway.

The ESAI and SSI hardware are totally different.  SSI gives you a
playback and a record stream in an I2S, or I2S like, interface.  A
stream is mono or stereo. ESAI has IIRC up to six output and four
inputs streams.  Each stream is in parallel on the same clock, and can
have one or more channels.  So it's sort of like six SSI devices
combined into one.  Except all the streams share a single FIFO and DMA
channel, so you can not independently turn the streams on and off in
ALSA like you could with six distinct SSI devices.  The hardware does
have the ability to turn streams on and off on the fly, but ALSA
models the device as something like a 12 channel PCM stream and
doesn't provide a way to change the hw_params on the fly between
periods.  Hence why we have a custom driver that does ugly things so
we can do this.


From timur at freescale.com  Fri Mar 16 17:31:20 2012
From: timur at freescale.com (Timur Tabi)
Date: Fri, 16 Mar 2012 16:31:20 -0500
Subject: [alsa-devel] [PATCH v5 8/8] ASoC: fsl: add imx-sgtl5000 machine
 driver
In-Reply-To: <CA+7tXih-omxaDq6dSKBeOaZ7YRWDVSQnMY=eJZ0-YumOBG=oCA@mail.gmail.com>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-9-git-send-email-shawn.guo@linaro.org>
 <CA+7tXihmfBQCgvuY0rx5v4w-bcwYK+7kP9v29w36N-Rc9KSQ+A@mail.gmail.com>
 <20120316111814.GA7860@S2101-09.ap.freescale.net>
 <20120316192110.GH3158@opensource.wolfsonmicro.com>
 <CA+7tXih-omxaDq6dSKBeOaZ7YRWDVSQnMY=eJZ0-YumOBG=oCA@mail.gmail.com>
Message-ID: <4F63B128.7040705@freescale.com>

Trent Piepho wrote:
> The ESAI and SSI hardware are totally different.  SSI gives you a
> playback and a record stream in an I2S, or I2S like, interface.  A
> stream is mono or stereo. ESAI has IIRC up to six output and four
> inputs streams.  Each stream is in parallel on the same clock, and can
> have one or more channels. 

Are these channels on the same wire in a time-division multiplexing, or on
six different wires?  If it's a TDM, then the SSI can actually do this
using "network mode", but I don't enable that in the driver, since it's
not really I2S compliant.

Well, this point is not really relevant to the discussion.

-- 
Timur Tabi
Linux kernel developer at Freescale



From greg at kroah.com  Fri Mar 16 17:33:17 2012
From: greg at kroah.com (Greg KH)
Date: Fri, 16 Mar 2012 14:33:17 -0700
Subject: [PATCH v2 1/7] misc: ddr: add LPDDR2 data from JESD209-2
In-Reply-To: <4F63A987.3@ti.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
 <1331835457-5390-2-git-send-email-aneesh@ti.com>
 <20120315190238.GD11142@kroah.com> <4F63A987.3@ti.com>
Message-ID: <20120316213316.GC24556@kroah.com>

On Sat, Mar 17, 2012 at 02:28:47AM +0530, Aneesh V wrote:
> Hi Greg,
> 
> On Friday 16 March 2012 12:32 AM, Greg KH wrote:
> >On Thu, Mar 15, 2012 at 11:47:31PM +0530, Aneesh V wrote:
> >>add LPDDR2 data from the JEDEC spec JESD209-2. The data
> >>includes:
> >>
> >>1. Addressing information for LPDDR2 memories of different
> >>    densities and types(S2/S4)
> >>2. AC timing data.
> >>
> >>This data will useful for memory controller device drivers
> >
> >Right now, only one driver, right?
> >
> >>+#ifndef __ASSEMBLY__
> >
> >Why is this needed?
> >
> >>+/* Structure for DDR addressing info from the JEDEC spec */
> >>+struct lpddr2_addressing {
> >>+	u32 num_banks;
> >>+	u32 tREFI_ns;
> >>+	u32 tRFCab_ps;
> >>+};
> >
> >Do these structures cross the user/kernel boundry somehow?  If so,
> >please use the proper kernel types for this.
> >
> >>--- a/lib/Makefile
> >>+++ b/lib/Makefile
> >>@@ -123,6 +123,9 @@ obj-$(CONFIG_SIGNATURE) += digsig.o
> >>
> >>  obj-$(CONFIG_CLZ_TAB) += clz_tab.o
> >>
> >>+obj-$(CONFIG_DDR) += jedec_ddr_data.o
> >>+
> >>+
> >
> >Why the extra line?
> >
> >>  hostprogs-y	:= gen_crc32table
> >>  clean-files	:= crc32table.h
> >>
> >>diff --git a/lib/jedec_ddr_data.c b/lib/jedec_ddr_data.c
> >>new file mode 100644
> >>index 0000000..fc223d6
> >>--- /dev/null
> >>+++ b/lib/jedec_ddr_data.c
> >>@@ -0,0 +1,135 @@
> >>+/*
> >>+ * DDR addressing details and AC timing parameters from JEDEC specs
> >>+ *
> >>+ * Copyright (C) 2012 Texas Instruments, Inc.
> >>+ *
> >>+ * Aneesh V<aneesh at ti.com>
> >>+ *
> >>+ * This program is free software; you can redistribute it and/or modify
> >>+ * it under the terms of the GNU General Public License version 2 as
> >>+ * published by the Free Software Foundation.
> >>+ */
> >>+
> >>+#include<misc/jedec_ddr.h>
> >>+#include<linux/module.h>
> >>+
> >>+/* LPDDR2 addressing details from JESD209-2 section 2.4 */
> >>+const struct lpddr2_addressing
> >>+	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
> >>+	{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
> >>+	{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
> >>+	{B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
> >>+	{B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
> >>+	{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
> >>+	{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
> >>+	{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
> >>+	{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
> >>+	{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
> >>+	{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
> >>+};
> >>+EXPORT_SYMBOL(lpddr2_jedec_addressing_table);
> >
> >EXPORT_SYMBOL_GPL for these and the others?
> 
> I have fixed these comments and pushed my latest patches at:
> git://github.com/aneeshv/linux.git
> branch: emif-upstream-v4

Sorry, but I don't take git pulls for stuff like this, please send all
of the patches in email so it can be reviewed properly.

thanks,

greg k-h


From mturquette at ti.com  Fri Mar 16 17:40:11 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 16 Mar 2012 14:40:11 -0700
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <201203162057.58706.arnd@arndb.de>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
Message-ID: <CAJOA=zNL2WeMzrEBRw_2OeYRfwHjxUjSJLgHzrWzFXR9Yvsvug@mail.gmail.com>

On Fri, Mar 16, 2012 at 1:57 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 16 March 2012, Arnd Bergmann wrote:
>> >
>> > Can we shoe-horn this thing into 3.4 (it is a bit late, i know) so
>> > that platform ports can gather speed? Several people are waiting for a
>> > somewhat stable version before starting their ports.
>> >
>> > And what is the path into mainline - will Russell carry it or Arnd
>> > (with Russell's blessing)?
>>
>> I would suggest putting it into a late/* branch of arm-soc so it finally
>> gets some linux-next exposure, and then sending it in the second week of the
>> merge window.
>>
>> Russell, please let me know if you want to carry it instead or if you
>> have found any last-minute show stoppers in the code.
>
> FWIW, it's in arm-soc now, and it's the last thing I ?put in there
> for v3.4. From now on until v3.4-rc1, feature patches can only get
> removed from arm-soc, not added.

Thanks Arnd.

Regards,
Mike

>
> ? ? ? ?Arnd


From greg at kroah.com  Fri Mar 16 17:43:34 2012
From: greg at kroah.com (Greg KH)
Date: Fri, 16 Mar 2012 14:43:34 -0700
Subject: [PATCH v4] misc: ddr: add LPDDR2 data from JESD209-2
In-Reply-To: <1331931007-584-1-git-send-email-aneesh@ti.com>
References: <1331929177-11694-1-git-send-email-aneesh@ti.com>
 <1331931007-584-1-git-send-email-aneesh@ti.com>
Message-ID: <20120316214334.GA24925@kroah.com>

On Sat, Mar 17, 2012 at 02:20:07AM +0530, Aneesh V wrote:
> add LPDDR2 data from the JEDEC spec JESD209-2. The data
> includes:
> 
> 1. Addressing information for LPDDR2 memories of different
>    densities and types(S2/S4)
> 2. AC timing data.
> 
> This data will useful for memory controller device drivers.
> Right now this is used by the TI EMIF SDRAM controller
> driver.
> 
> Cc: Greg KH <greg at kroah.com>
> Signed-off-by: Aneesh V <aneesh at ti.com>

What happened to the other patches that depended on this one?

greg k-h


From tpiepho at gmail.com  Fri Mar 16 17:45:09 2012
From: tpiepho at gmail.com (Trent Piepho)
Date: Fri, 16 Mar 2012 17:45:09 -0400
Subject: [alsa-devel] [PATCH v5 8/8] ASoC: fsl: add imx-sgtl5000 machine
 driver
In-Reply-To: <4F63B128.7040705@freescale.com>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-9-git-send-email-shawn.guo@linaro.org>
 <CA+7tXihmfBQCgvuY0rx5v4w-bcwYK+7kP9v29w36N-Rc9KSQ+A@mail.gmail.com>
 <20120316111814.GA7860@S2101-09.ap.freescale.net>
 <20120316192110.GH3158@opensource.wolfsonmicro.com>
 <CA+7tXih-omxaDq6dSKBeOaZ7YRWDVSQnMY=eJZ0-YumOBG=oCA@mail.gmail.com>
 <4F63B128.7040705@freescale.com>
Message-ID: <CA+7tXijxUpnoBfrjOEyBeLPF9T9qhBiy6B+8LPVnyNc99mYVQw@mail.gmail.com>

On Fri, Mar 16, 2012 at 5:31 PM, Timur Tabi <timur at freescale.com> wrote:
> Trent Piepho wrote:
>> The ESAI and SSI hardware are totally different. ?SSI gives you a
>> playback and a record stream in an I2S, or I2S like, interface. ?A
>> stream is mono or stereo. ESAI has IIRC up to six output and four
>> inputs streams. ?Each stream is in parallel on the same clock, and can
>> have one or more channels.
>
> Are these channels on the same wire in a time-division multiplexing, or on
> six different wires? ?If it's a TDM, then the SSI can actually do this
> using "network mode", but I don't enable that in the driver, since it's
> not really I2S compliant.

Six different wires.  Each wire can have multiple channels, or
"slots", to do mono, stereo, 5.1, etc.  Each wire needs the same
number of slots, since there is only one frame sync.  And only one bit
clock too.  RX and TX can be synchronous or async.  I know it has
network mode too, but our hardware is I2S so I never bothered to look
into exactly what network mode is.


From nico at fluxnic.net  Fri Mar 16 17:47:56 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 16 Mar 2012 17:47:56 -0400 (EDT)
Subject: [PATCH] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
References: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <alpine.LFD.2.02.1203161746250.24151@xanadu.home>

On Fri, 16 Mar 2012, Stephen Warren wrote:

> All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
> to avoid duplication.
> 
> All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
> parameterized version in Makefile.lib to avoid duplication.
> 
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>

Acked-by: Nicolas Pitre <nico at linaro.org>


> ---
> v2:
> * Fix blackfin's UIMAGE_LOADADDR in the ROMKERNEL case.
> * Fix missing ) on a variable reference in avr32 and sparc.
> * Only set those UIMAGE_* variables that the arch-specific Makefile hasn't
>   already set.
> * The patch series is now just this single patch which removes duplication;
>   I've dropped the Kconfig feature to allow use of -T kernel_noload for
>   now, since it looks like U-Boot is gaining direct zImage support.
> 
>  arch/arm/boot/Makefile          |   23 +++++++++--------------
>  arch/avr32/boot/images/Makefile |    9 +++------
>  arch/blackfin/boot/Makefile     |   19 ++++++++-----------
>  arch/microblaze/boot/Makefile   |   10 +++-------
>  arch/sh/boot/Makefile           |    8 ++------
>  arch/sparc/boot/Makefile        |    9 +++------
>  arch/unicore32/boot/Makefile    |   12 ++----------
>  scripts/Makefile.lib            |   24 ++++++++++++++++++++++++
>  8 files changed, 54 insertions(+), 60 deletions(-)
> 
> diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
> index fc871e7..c877087 100644
> --- a/arch/arm/boot/Makefile
> +++ b/arch/arm/boot/Makefile
> @@ -11,8 +11,6 @@
>  # Copyright (C) 1995-2002 Russell King
>  #
>  
> -MKIMAGE         := $(srctree)/scripts/mkuboot.sh
> -
>  ifneq ($(MACHINE),)
>  include $(srctree)/$(MACHINE)/Makefile.boot
>  endif
> @@ -69,22 +67,19 @@ $(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
>  
>  clean-files := *.dtb
>  
> -quiet_cmd_uimage = UIMAGE  $@
> -      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
> -		   -C none -a $(LOADADDR) -e $(STARTADDR) \
> -		   -n 'Linux-$(KERNELRELEASE)' -d $< $@
> -
> -ifeq ($(CONFIG_ZBOOT_ROM),y)
> -$(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
> +ifneq ($(LOADADDR),)
> +  UIMAGE_LOADADDR=$(LOADADDR)
>  else
> -$(obj)/uImage: LOADADDR=$(ZRELADDR)
> +  ifeq ($(CONFIG_ZBOOT_ROM),y)
> +    UIMAGE_LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
> +  else
> +    UIMAGE_LOADADDR=$(ZRELADDR)
> +  endif
>  endif
>  
> -$(obj)/uImage: STARTADDR=$(LOADADDR)
> -
>  check_for_multiple_loadaddr = \
> -if [ $(words $(LOADADDR)) -gt 1 ]; then \
> -	echo 'multiple load addresses: $(LOADADDR)'; \
> +if [ $(words $(UIMAGE_LOADADDR)) -gt 1 ]; then \
> +	echo 'multiple load addresses: $(UIMAGE_LOADADDR)'; \
>  	echo 'This is incompatible with uImages'; \
>  	echo 'Specify LOADADDR on the commandline to build an uImage'; \
>  	false; \
> diff --git a/arch/avr32/boot/images/Makefile b/arch/avr32/boot/images/Makefile
> index 1848bf0..2a3b539 100644
> --- a/arch/avr32/boot/images/Makefile
> +++ b/arch/avr32/boot/images/Makefile
> @@ -6,8 +6,6 @@
>  # for more details.
>  #
>  
> -MKIMAGE		:= $(srctree)/scripts/mkuboot.sh
> -
>  extra-y		:= vmlinux.bin vmlinux.gz
>  
>  OBJCOPYFLAGS_vmlinux.bin := -O binary -R .note.gnu.build-id
> @@ -17,10 +15,9 @@ $(obj)/vmlinux.bin: vmlinux FORCE
>  $(obj)/vmlinux.gz: $(obj)/vmlinux.bin FORCE
>  	$(call if_changed,gzip)
>  
> -quiet_cmd_uimage = UIMAGE $@
> -      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A avr32 -O linux -T kernel	\
> -		-C gzip -a $(CONFIG_LOAD_ADDRESS) -e $(CONFIG_ENTRY_ADDRESS)	\
> -		-n 'Linux-$(KERNELRELEASE)' -d $< $@
> +UIMAGE_LOADADDR = $(CONFIG_LOAD_ADDRESS)
> +UIMAGE_ENTRYADDR = $(CONFIG_ENTRY_ADDRESS)
> +UIMAGE_COMPRESSION = gzip
>  
>  targets += uImage uImage.srec
>  $(obj)/uImage: $(obj)/vmlinux.gz
> diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
> index 0a49279..f7d27d5 100644
> --- a/arch/blackfin/boot/Makefile
> +++ b/arch/blackfin/boot/Makefile
> @@ -6,20 +6,17 @@
>  # for more details.
>  #
>  
> -MKIMAGE := $(srctree)/scripts/mkuboot.sh
> -
>  targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip
>  extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
>  
> -UIMAGE_OPTS-y :=
> -UIMAGE_OPTS-$(CONFIG_RAMKERNEL) += -a $(CONFIG_BOOT_LOAD)
> -UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -a $(CONFIG_ROM_BASE) -x
> -
> -quiet_cmd_uimage = UIMAGE  $@
> -      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
> -                   -C $(2) -n '$(CPU_REV)-$(KERNELRELEASE)' \
> -                   -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
> -                   $(UIMAGE_OPTS-y) -d $< $@
> +ifeq ($(CONFIG_RAMKERNEL),y)
> +UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
> +else # CONFIG_ROMKERNEL must be set
> +UIMAGE_LOADADDR = $(CONFIG_ROM_BASE)
> +endif
> +UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}')
> +UIMAGE_NAME = '$(CPU_REV)-$(KERNELRELEASE)'
> +UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -x
>  
>  $(obj)/vmlinux.bin: vmlinux FORCE
>  	$(call if_changed,objcopy)
> diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile
> index 0c796cf..ca76ecd 100644
> --- a/arch/microblaze/boot/Makefile
> +++ b/arch/microblaze/boot/Makefile
> @@ -2,8 +2,6 @@
>  # arch/microblaze/boot/Makefile
>  #
>  
> -MKIMAGE := $(srctree)/scripts/mkuboot.sh
> -
>  obj-y += linked_dtb.o
>  
>  targets := linux.bin linux.bin.gz simpleImage.%
> @@ -35,11 +33,9 @@ quiet_cmd_strip = STRIP   $@
>  	cmd_strip = $(STRIP) -K microblaze_start -K _end -K __log_buf \
>  				-K _fdt_start vmlinux -o $@
>  
> -quiet_cmd_uimage = UIMAGE  $@.ub
> -	cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A microblaze -O linux -T kernel \
> -		-C none -n 'Linux-$(KERNELRELEASE)' \
> -		-a $(CONFIG_KERNEL_BASE_ADDR) -e $(CONFIG_KERNEL_BASE_ADDR) \
> -		-d $@ $@.ub
> +UIMAGE_IN = $@
> +UIMAGE_OUT = $@.ub
> +UIMAGE_LOADADDR = $(CONFIG_KERNEL_BASE_ADDR)
>  
>  $(obj)/simpleImage.%: vmlinux FORCE
>  	$(call if_changed,cp,.unstrip)
> diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
> index e4ea31a..58592df 100644
> --- a/arch/sh/boot/Makefile
> +++ b/arch/sh/boot/Makefile
> @@ -8,8 +8,6 @@
>  # Copyright (C) 1999 Stuart Menefy
>  #
>  
> -MKIMAGE := $(srctree)/scripts/mkuboot.sh
> -
>  #
>  # Assign safe dummy values if these variables are not defined,
>  # in order to suppress error message.
> @@ -61,10 +59,8 @@ KERNEL_ENTRY	:= $(shell /bin/bash -c 'printf "0x%08x" \
>  			$(KERNEL_MEMORY) + \
>  			$(CONFIG_ZERO_PAGE_OFFSET) + $(CONFIG_ENTRY_OFFSET)]')
>  
> -quiet_cmd_uimage = UIMAGE  $@
> -      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sh -O linux -T kernel \
> -		   -C $(2) -a $(KERNEL_LOAD) -e $(KERNEL_ENTRY) \
> -		   -n 'Linux-$(KERNELRELEASE)' -d $< $@
> +UIMAGE_LOADADDR = $(KERNEL_LOAD)
> +UIMAGE_ENTRYADDR = $(KERNEL_ENTRY)
>  
>  $(obj)/vmlinux.bin: vmlinux FORCE
>  	$(call if_changed,objcopy)
> diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile
> index 9205416..d56d199 100644
> --- a/arch/sparc/boot/Makefile
> +++ b/arch/sparc/boot/Makefile
> @@ -5,7 +5,6 @@
>  
>  ROOT_IMG	:= /usr/src/root.img
>  ELFTOAOUT	:= elftoaout
> -MKIMAGE 	:= $(srctree)/scripts/mkuboot.sh
>  
>  hostprogs-y	:= piggyback btfixupprep
>  targets		:= tftpboot.img btfix.o btfix.S image zImage vmlinux.aout
> @@ -92,11 +91,9 @@ $(obj)/image.bin: $(obj)/image FORCE
>  $(obj)/image.gz: $(obj)/image.bin
>  	$(call if_changed,gzip)
>  
> -quiet_cmd_uimage = UIMAGE  $@
> -      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sparc -O linux -T kernel \
> -               -C gzip -a $(CONFIG_UBOOT_LOAD_ADDR) \
> -	       -e $(CONFIG_UBOOT_ENTRY_ADDR) -n 'Linux-$(KERNELRELEASE)' \
> -               -d $< $@
> +UIMAGE_LOADADDR = $(CONFIG_UBOOT_LOAD_ADDR)
> +UIMAGE_ENTRYADDR = $(CONFIG_UBOOT_ENTRY_ADDR)
> +UIMAGE_COMPRESSION = gzip
>  
>  quiet_cmd_uimage.o = UIMAGE.O $@
>        cmd_uimage.o = $(LD) -Tdata $(CONFIG_UBOOT_FLASH_ADDR) \
> diff --git a/arch/unicore32/boot/Makefile b/arch/unicore32/boot/Makefile
> index 79e5f88..ec7fb70 100644
> --- a/arch/unicore32/boot/Makefile
> +++ b/arch/unicore32/boot/Makefile
> @@ -11,8 +11,6 @@
>  # Copyright (C) 2001~2010 GUAN Xue-tao
>  #
>  
> -MKIMAGE := $(srctree)/scripts/mkuboot.sh
> -
>  targets := Image zImage uImage
>  
>  $(obj)/Image: vmlinux FORCE
> @@ -26,14 +24,8 @@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE
>  	$(call if_changed,objcopy)
>  	@echo '  Kernel: $@ is ready'
>  
> -quiet_cmd_uimage = UIMAGE  $@
> -      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A unicore -O linux -T kernel \
> -		   -C none -a $(LOADADDR) -e $(STARTADDR) \
> -		   -n 'Linux-$(KERNELRELEASE)' -d $< $@
> -
> -$(obj)/uImage: LOADADDR=0x0
> -
> -$(obj)/uImage: STARTADDR=$(LOADADDR)
> +UIMAGE_ARCH = unicore
> +UIMAGE_LOADADDR = 0x0
>  
>  $(obj)/uImage: $(obj)/zImage FORCE
>  	$(call if_changed,uimage)
> diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
> index 00c368c..0be6f11 100644
> --- a/scripts/Makefile.lib
> +++ b/scripts/Makefile.lib
> @@ -304,6 +304,30 @@ cmd_lzo = (cat $(filter-out FORCE,$^) | \
>  	lzop -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \
>  	(rm -f $@ ; false)
>  
> +# U-Boot mkimage
> +# ---------------------------------------------------------------------------
> +
> +MKIMAGE := $(srctree)/scripts/mkuboot.sh
> +
> +# SRCARCH just happens to match slightly more than ARCH (on sparc), so reduces
> +# the number of overrides in arch makefiles
> +UIMAGE_ARCH ?= $(SRCARCH)
> +UIMAGE_COMPRESSION ?= $(if $(2),$(2),none)
> +UIMAGE_OPTS-y ?=
> +UIMAGE_TYPE ?= kernel
> +UIMAGE_LOADADDR ?= arch_must_set_this
> +UIMAGE_ENTRYADDR ?= $(UIMAGE_LOADADDR)
> +UIMAGE_NAME ?= 'Linux-$(KERNELRELEASE)'
> +UIMAGE_IN ?= $<
> +UIMAGE_OUT ?= $@
> +
> +quiet_cmd_uimage = UIMAGE  $(UIMAGE_OUT)
> +      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(UIMAGE_ARCH) -O linux \
> +			-C $(UIMAGE_COMPRESSION) $(UIMAGE_OPTS-y) \
> +			-T $(UIMAGE_TYPE) \
> +			-a $(UIMAGE_LOADADDR) -e $(UIMAGE_ENTRYADDR) \
> +			-n $(UIMAGE_NAME) -d $(UIMAGE_IN) $(UIMAGE_OUT)
> +
>  # XZ
>  # ---------------------------------------------------------------------------
>  # Use xzkern to compress the kernel image and xzmisc to compress other things.
> -- 
> 1.7.0.4
> 


From nicolas.pitre at linaro.org  Fri Mar 16 17:50:41 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 16 Mar 2012 17:50:41 -0400 (EDT)
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <201203162057.58706.arnd@arndb.de>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
Message-ID: <alpine.LFD.2.02.1203161748280.24151@xanadu.home>

On Fri, 16 Mar 2012, Arnd Bergmann wrote:

> FWIW, it's in arm-soc now, and it's the last thing I  put in there
> for v3.4.

Amen!


Nicolas


From aneesh at ti.com  Fri Mar 16 17:50:36 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 03:20:36 +0530
Subject: [PATCH v4] misc: ddr: add LPDDR2 data from JESD209-2
In-Reply-To: <20120316214334.GA24925@kroah.com>
References: <1331929177-11694-1-git-send-email-aneesh@ti.com>
 <1331931007-584-1-git-send-email-aneesh@ti.com>
 <20120316214334.GA24925@kroah.com>
Message-ID: <4F63B5AC.5080808@ti.com>

On Saturday 17 March 2012 03:13 AM, Greg KH wrote:
> On Sat, Mar 17, 2012 at 02:20:07AM +0530, Aneesh V wrote:
>> add LPDDR2 data from the JEDEC spec JESD209-2. The data
>> includes:
>>
>> 1. Addressing information for LPDDR2 memories of different
>>     densities and types(S2/S4)
>> 2. AC timing data.
>>
>> This data will useful for memory controller device drivers.
>> Right now this is used by the TI EMIF SDRAM controller
>> driver.
>>
>> Cc: Greg KH<greg at kroah.com>
>> Signed-off-by: Aneesh V<aneesh at ti.com>
>
> What happened to the other patches that depended on this one?

I was not sure what was the convention regarding re-submitting just one
patch in a series. I realize that you prefer having the whole series
again. I will send it shortly.

thanks,
Aneesh


From aneesh at ti.com  Fri Mar 16 17:51:40 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 03:21:40 +0530
Subject: [PATCH v4 0/7] Add TI EMIF SDRAM controller driver
Message-ID: <1331934707-29487-1-git-send-email-aneesh@ti.com>

Add a driver for the EMIF SDRAM controller used in TI SoCs

EMIF is an SDRAM controller that supports, based on its revision,
one or more of LPDDR2/DDR2/DDR3 protocols.This driver adds support
for LPDDR2.

The driver supports the following features:
- Calculates the DDR AC timing parameters to be set in EMIF
  registers using data from the device data-sheets and based
  on the DDR frequency. If data from data-sheets is not available
  default timing values from the JEDEC spec are used. These
  will be safe, but not necessarily optimal
- API for changing timings during DVFS or at boot-up
- Temperature alert configuration and handling of temperature
  alerts, if any for LPDDR2 devices
  * temperature alert is based on periodic polling of MR4 mode
    register in DDR devices automatically performed by hardware
  * timings are de-rated and brought back to nominal when
    temperature raises and falls respectively
- Cache of calculated register values to avoid re-calculating
  them

The driver will need some minor updates when it is eventually
integrated with Dynamic Voltage and Frequency Scaling (DVFS).
This can not be done now as DVFS support is not available in
the mainline yet.

Discussions with Santosh Shilimkar <santosh.shilimkar at ti.com>
were immensely helpful in shaping up the interfaces. Vibhore Vardhan
<vvardhan at gmail.com> did the initial code snippet for thermal
handling.

Testing: 
- The driver is tested on OMAP4430 SDP.
- The driver in a slightly adapted form is also tested on OMAP5.
- Since mainline kernel doesn't have DVFS support yet,
  testing was done using a test module.
- Temperature alert handling was tested with simulated interrupts
  and faked temperature values as testing all cases in real-life
  scenarios is difficult.
- Tested the driver as a module

Cc: Greg KH <greg at kroah.com>

v4:
- Converted instances of EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
- Removed un-necessary "#ifndef __ASSEMBLY__'
- Minor formatting fix

v2:
- Fixed a bug found in the implementation of errata i728
  workaround
- Fixed the value of frequency printed in debugfs
- Dropped the hwmod patch as Paul has already posted a
  a hwmod series [1] that adds hwmod for EMIF
- Converted instances of __init to __init_or_module

[1] http://thread.gmane.org/gmane.linux.ports.arm.omap/72855

Aneesh V (7):
  misc: ddr: add LPDDR2 data from JESD209-2
  misc: emif: add register definitions for EMIF
  misc: emif: add basic infrastructure for EMIF driver
  misc: emif: handle frequency and voltage change events
  misc: emif: add interrupt and temperature handling
  misc: emif: add one-time settings
  misc: emif: add debugfs entries for emif

 Documentation/misc-devices/ti-emif.txt  |   58 ++
 drivers/misc/Kconfig                    |   12 +
 drivers/misc/Makefile                   |    1 +
 drivers/misc/emif.c                     | 1670 +++++++++++++++++++++++++++++++
 drivers/misc/emif.h                     |  589 +++++++++++
 include/linux/platform_data/emif_plat.h |  128 +++
 include/misc/jedec_ddr.h                |  175 ++++
 lib/Kconfig                             |    8 +
 lib/Makefile                            |    2 +
 lib/jedec_ddr_data.c                    |  135 +++
 10 files changed, 2778 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/misc-devices/ti-emif.txt
 create mode 100644 drivers/misc/emif.c
 create mode 100644 drivers/misc/emif.h
 create mode 100644 include/linux/platform_data/emif_plat.h
 create mode 100644 include/misc/jedec_ddr.h
 create mode 100644 lib/jedec_ddr_data.c



From aneesh at ti.com  Fri Mar 16 17:51:41 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 03:21:41 +0530
Subject: [PATCH v4 1/7] misc: ddr: add LPDDR2 data from JESD209-2
In-Reply-To: <1331934707-29487-1-git-send-email-aneesh@ti.com>
References: <1331934707-29487-1-git-send-email-aneesh@ti.com>
Message-ID: <1331934707-29487-2-git-send-email-aneesh@ti.com>

add LPDDR2 data from the JEDEC spec JESD209-2. The data
includes:

1. Addressing information for LPDDR2 memories of different
   densities and types(S2/S4)
2. AC timing data.

This data will useful for memory controller device drivers.
Right now this is used by the TI EMIF SDRAM controller
driver.

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---

v4:
- Removed 'ifndef __ASSEMBLY__' from jedec_ddr.h
- Updated commit log to be more specific on where
  this patch is used currently
- Converted EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
- Removed un-necessary newline

v1:
- Moved to /lib from /drivers/misc
- Corrected Copyright year
---
 include/misc/jedec_ddr.h |  175 ++++++++++++++++++++++++++++++++++++++++++++++
 lib/Kconfig              |    8 ++
 lib/Makefile             |    2 +
 lib/jedec_ddr_data.c     |  135 +++++++++++++++++++++++++++++++++++
 4 files changed, 320 insertions(+), 0 deletions(-)
 create mode 100644 include/misc/jedec_ddr.h
 create mode 100644 lib/jedec_ddr_data.c

diff --git a/include/misc/jedec_ddr.h b/include/misc/jedec_ddr.h
new file mode 100644
index 0000000..ddad0f8
--- /dev/null
+++ b/include/misc/jedec_ddr.h
@@ -0,0 +1,175 @@
+/*
+ * Definitions for DDR memories based on JEDEC specs
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_JEDEC_DDR_H
+#define __LINUX_JEDEC_DDR_H
+
+#include <linux/types.h>
+
+/* DDR Densities */
+#define DDR_DENSITY_64Mb	1
+#define DDR_DENSITY_128Mb	2
+#define DDR_DENSITY_256Mb	3
+#define DDR_DENSITY_512Mb	4
+#define DDR_DENSITY_1Gb		5
+#define DDR_DENSITY_2Gb		6
+#define DDR_DENSITY_4Gb		7
+#define DDR_DENSITY_8Gb		8
+#define DDR_DENSITY_16Gb	9
+#define DDR_DENSITY_32Gb	10
+
+/* DDR type */
+#define DDR_TYPE_DDR2		1
+#define DDR_TYPE_DDR3		2
+#define DDR_TYPE_LPDDR2_S4	3
+#define DDR_TYPE_LPDDR2_S2	4
+#define DDR_TYPE_LPDDR2_NVM	5
+
+/* DDR IO width */
+#define DDR_IO_WIDTH_4		1
+#define DDR_IO_WIDTH_8		2
+#define DDR_IO_WIDTH_16		3
+#define DDR_IO_WIDTH_32		4
+
+/* Number of Row bits */
+#define R9			9
+#define R10			10
+#define R11			11
+#define R12			12
+#define R13			13
+#define R14			14
+#define R15			15
+#define R16			16
+
+/* Number of Column bits */
+#define C7			7
+#define C8			8
+#define C9			9
+#define C10			10
+#define C11			11
+#define C12			12
+
+/* Number of Banks */
+#define B1			0
+#define B2			1
+#define B4			2
+#define B8			3
+
+/* Refresh rate in nano-seconds */
+#define T_REFI_15_6		15600
+#define T_REFI_7_8		7800
+#define T_REFI_3_9		3900
+
+/* tRFC values */
+#define T_RFC_90		90000
+#define T_RFC_110		110000
+#define T_RFC_130		130000
+#define T_RFC_160		160000
+#define T_RFC_210		210000
+#define T_RFC_300		300000
+#define T_RFC_350		350000
+
+/* Mode register numbers */
+#define DDR_MR0			0
+#define DDR_MR1			1
+#define DDR_MR2			2
+#define DDR_MR3			3
+#define DDR_MR4			4
+#define DDR_MR5			5
+#define DDR_MR6			6
+#define DDR_MR7			7
+#define DDR_MR8			8
+#define DDR_MR9			9
+#define DDR_MR10		10
+#define DDR_MR11		11
+#define DDR_MR16		16
+#define DDR_MR17		17
+#define DDR_MR18		18
+
+/*
+ * LPDDR2 related defines
+ */
+
+/* MR4 register fields */
+#define MR4_SDRAM_REF_RATE_SHIFT			0
+#define MR4_SDRAM_REF_RATE_MASK				7
+#define MR4_TUF_SHIFT					7
+#define MR4_TUF_MASK					(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define NUM_DDR_ADDR_TABLE_ENTRIES			11
+#define NUM_DDR_TIMING_TABLE_ENTRIES			4
+
+/* Structure for DDR addressing info from the JEDEC spec */
+struct lpddr2_addressing {
+	u32 num_banks;
+	u32 tREFI_ns;
+	u32 tRFCab_ps;
+};
+
+/*
+ * Structure for timings from the LPDDR2 datasheet
+ * All parameters are in pico seconds(ps) unless explicitly indicated
+ * with a suffix like tRAS_max_ns below
+ */
+struct lpddr2_timings {
+	u32 max_freq;
+	u32 min_freq;
+	u32 tRPab;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_min;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u32 tCKESR;
+	u32 tDQSCK_max;
+	u32 tDQSCK_max_derated;
+	u32 tFAW;
+	u32 tZQCS;
+	u32 tZQCL;
+	u32 tZQinit;
+	u32 tRAS_max_ns;
+};
+
+/*
+ * Min value for some parameters in terms of number of tCK cycles(nCK)
+ * Please set to zero parameters that are not valid for a given memory
+ * type
+ */
+struct lpddr2_min_tck {
+	u32 tRPab;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRASmin;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u32 tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+extern const struct lpddr2_addressing
+	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES];
+extern const struct lpddr2_timings
+	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
+extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
+
+#endif /* __LINUX_JEDEC_DDR_H */
diff --git a/lib/Kconfig b/lib/Kconfig
index 028aba9..c5d4f1f 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -291,6 +291,14 @@ config CORDIC
 	  This option provides an implementation of the CORDIC algorithm;
 	  calculations are in fixed point. Module will be called cordic.
 
+config DDR
+	bool "JEDEC DDR data"
+	help
+	  Data from JEDEC specs for DDR SDRAM memories,
+	  particularly the AC timing parameters and addressing
+	  information. This data is useful for drivers handling
+	  DDR SDRAM controllers.
+
 config MPILIB
 	tristate
 	select CLZ_TAB
diff --git a/lib/Makefile b/lib/Makefile
index 18515f0..74290c9 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -123,6 +123,8 @@ obj-$(CONFIG_SIGNATURE) += digsig.o
 
 obj-$(CONFIG_CLZ_TAB) += clz_tab.o
 
+obj-$(CONFIG_DDR) += jedec_ddr_data.o
+
 hostprogs-y	:= gen_crc32table
 clean-files	:= crc32table.h
 
diff --git a/lib/jedec_ddr_data.c b/lib/jedec_ddr_data.c
new file mode 100644
index 0000000..498c78f
--- /dev/null
+++ b/lib/jedec_ddr_data.c
@@ -0,0 +1,135 @@
+/*
+ * DDR addressing details and AC timing parameters from JEDEC specs
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <misc/jedec_ddr.h>
+#include <linux/module.h>
+
+/* LPDDR2 addressing details from JESD209-2 section 2.4 */
+const struct lpddr2_addressing
+	lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
+	{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
+	{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
+	{B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
+	{B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
+	{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
+	{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
+	{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
+	{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
+	{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
+	{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
+};
+EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
+
+/* LPDDR2 AC timing parameters from JESD209-2 section 12 */
+const struct lpddr2_timings
+	lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
+	/* Speed bin 400(200 MHz) */
+	[0] = {
+		.max_freq	= 200000000,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 10000,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 533(266 MHz) */
+	[1] = {
+		.max_freq	= 266666666,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 800(400 MHz) */
+	[2] = {
+		.max_freq	= 400000000,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 6000,
+	},
+	/* Speed bin 1066(533 MHz) */
+	[3] = {
+		.max_freq	= 533333333,
+		.min_freq	= 10000000,
+		.tRPab		= 21000,
+		.tRCD		= 18000,
+		.tWR		= 15000,
+		.tRAS_min	= 42000,
+		.tRRD		= 10000,
+		.tWTR		= 7500,
+		.tXP		= 7500,
+		.tRTP		= 7500,
+		.tCKESR		= 15000,
+		.tDQSCK_max	= 5500,
+		.tFAW		= 50000,
+		.tZQCS		= 90000,
+		.tZQCL		= 360000,
+		.tZQinit	= 1000000,
+		.tRAS_max_ns	= 70000,
+		.tDQSCK_max_derated = 5620,
+	},
+};
+EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
+
+const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
+	.tRPab		= 3,
+	.tRCD		= 3,
+	.tWR		= 3,
+	.tRASmin	= 3,
+	.tRRD		= 2,
+	.tWTR		= 2,
+	.tXP		= 2,
+	.tRTP		= 2,
+	.tCKE		= 3,
+	.tCKESR		= 3,
+	.tFAW		= 8
+};
+EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
-- 
1.7.1



From aneesh at ti.com  Fri Mar 16 17:51:42 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 03:21:42 +0530
Subject: [PATCH v4 2/7] misc: emif: add register definitions for EMIF
In-Reply-To: <1331934707-29487-1-git-send-email-aneesh@ti.com>
References: <1331934707-29487-1-git-send-email-aneesh@ti.com>
Message-ID: <1331934707-29487-3-git-send-email-aneesh@ti.com>

Add register offsets and bit field definitions
for EMIF module in TI SoCs

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v1:
- Improved commit log
- Corrected copyright year
- Changed file name in order to add other defines
  needed by the driver in the same file in subsequent
  patches
---
 drivers/misc/emif.h |  454 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 454 insertions(+), 0 deletions(-)
 create mode 100644 drivers/misc/emif.h

diff --git a/drivers/misc/emif.h b/drivers/misc/emif.h
new file mode 100644
index 0000000..44b97df
--- /dev/null
+++ b/drivers/misc/emif.h
@@ -0,0 +1,454 @@
+/*
+ * Defines for the EMIF driver
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson at ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __EMIF_H
+#define __EMIF_H
+
+/* Registers offset */
+#define EMIF_MODULE_ID_AND_REVISION			0x0000
+#define EMIF_STATUS					0x0004
+#define EMIF_SDRAM_CONFIG				0x0008
+#define EMIF_SDRAM_CONFIG_2				0x000c
+#define EMIF_SDRAM_REFRESH_CONTROL			0x0010
+#define EMIF_SDRAM_REFRESH_CTRL_SHDW			0x0014
+#define EMIF_SDRAM_TIMING_1				0x0018
+#define EMIF_SDRAM_TIMING_1_SHDW			0x001c
+#define EMIF_SDRAM_TIMING_2				0x0020
+#define EMIF_SDRAM_TIMING_2_SHDW			0x0024
+#define EMIF_SDRAM_TIMING_3				0x0028
+#define EMIF_SDRAM_TIMING_3_SHDW			0x002c
+#define EMIF_LPDDR2_NVM_TIMING				0x0030
+#define EMIF_LPDDR2_NVM_TIMING_SHDW			0x0034
+#define EMIF_POWER_MANAGEMENT_CONTROL			0x0038
+#define EMIF_POWER_MANAGEMENT_CTRL_SHDW			0x003c
+#define EMIF_LPDDR2_MODE_REG_DATA			0x0040
+#define EMIF_LPDDR2_MODE_REG_CONFIG			0x0050
+#define EMIF_OCP_CONFIG					0x0054
+#define EMIF_OCP_CONFIG_VALUE_1				0x0058
+#define EMIF_OCP_CONFIG_VALUE_2				0x005c
+#define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL		0x0060
+#define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT		0x0064
+#define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT	0x0068
+#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1	0x006c
+#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2	0x0070
+#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3	0x0074
+#define EMIF_PERFORMANCE_COUNTER_1			0x0080
+#define EMIF_PERFORMANCE_COUNTER_2			0x0084
+#define EMIF_PERFORMANCE_COUNTER_CONFIG			0x0088
+#define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT	0x008c
+#define EMIF_PERFORMANCE_COUNTER_TIME			0x0090
+#define EMIF_MISC_REG					0x0094
+#define EMIF_DLL_CALIB_CTRL				0x0098
+#define EMIF_DLL_CALIB_CTRL_SHDW			0x009c
+#define EMIF_END_OF_INTERRUPT				0x00a0
+#define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS		0x00a4
+#define EMIF_LL_OCP_INTERRUPT_RAW_STATUS		0x00a8
+#define EMIF_SYSTEM_OCP_INTERRUPT_STATUS		0x00ac
+#define EMIF_LL_OCP_INTERRUPT_STATUS			0x00b0
+#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET		0x00b4
+#define EMIF_LL_OCP_INTERRUPT_ENABLE_SET		0x00b8
+#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR		0x00bc
+#define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR		0x00c0
+#define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG	0x00c8
+#define EMIF_TEMPERATURE_ALERT_CONFIG			0x00cc
+#define EMIF_OCP_ERROR_LOG				0x00d0
+#define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW		0x00d4
+#define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL		0x00d8
+#define EMIF_READ_WRITE_LEVELING_CONTROL		0x00dc
+#define EMIF_DDR_PHY_CTRL_1				0x00e4
+#define EMIF_DDR_PHY_CTRL_1_SHDW			0x00e8
+#define EMIF_DDR_PHY_CTRL_2				0x00ec
+#define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING	0x0100
+#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104
+#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108
+#define EMIF_READ_WRITE_EXECUTION_THRESHOLD		0x0120
+#define EMIF_COS_CONFIG					0x0124
+#define EMIF_PHY_STATUS_1				0x0140
+#define EMIF_PHY_STATUS_2				0x0144
+#define EMIF_PHY_STATUS_3				0x0148
+#define EMIF_PHY_STATUS_4				0x014c
+#define EMIF_PHY_STATUS_5				0x0150
+#define EMIF_PHY_STATUS_6				0x0154
+#define EMIF_PHY_STATUS_7				0x0158
+#define EMIF_PHY_STATUS_8				0x015c
+#define EMIF_PHY_STATUS_9				0x0160
+#define EMIF_PHY_STATUS_10				0x0164
+#define EMIF_PHY_STATUS_11				0x0168
+#define EMIF_PHY_STATUS_12				0x016c
+#define EMIF_PHY_STATUS_13				0x0170
+#define EMIF_PHY_STATUS_14				0x0174
+#define EMIF_PHY_STATUS_15				0x0178
+#define EMIF_PHY_STATUS_16				0x017c
+#define EMIF_PHY_STATUS_17				0x0180
+#define EMIF_PHY_STATUS_18				0x0184
+#define EMIF_PHY_STATUS_19				0x0188
+#define EMIF_PHY_STATUS_20				0x018c
+#define EMIF_PHY_STATUS_21				0x0190
+#define EMIF_EXT_PHY_CTRL_1				0x0200
+#define EMIF_EXT_PHY_CTRL_1_SHDW			0x0204
+#define EMIF_EXT_PHY_CTRL_2				0x0208
+#define EMIF_EXT_PHY_CTRL_2_SHDW			0x020c
+#define EMIF_EXT_PHY_CTRL_3				0x0210
+#define EMIF_EXT_PHY_CTRL_3_SHDW			0x0214
+#define EMIF_EXT_PHY_CTRL_4				0x0218
+#define EMIF_EXT_PHY_CTRL_4_SHDW			0x021c
+#define EMIF_EXT_PHY_CTRL_5				0x0220
+#define EMIF_EXT_PHY_CTRL_5_SHDW			0x0224
+#define EMIF_EXT_PHY_CTRL_6				0x0228
+#define EMIF_EXT_PHY_CTRL_6_SHDW			0x022c
+#define EMIF_EXT_PHY_CTRL_7				0x0230
+#define EMIF_EXT_PHY_CTRL_7_SHDW			0x0234
+#define EMIF_EXT_PHY_CTRL_8				0x0238
+#define EMIF_EXT_PHY_CTRL_8_SHDW			0x023c
+#define EMIF_EXT_PHY_CTRL_9				0x0240
+#define EMIF_EXT_PHY_CTRL_9_SHDW			0x0244
+#define EMIF_EXT_PHY_CTRL_10				0x0248
+#define EMIF_EXT_PHY_CTRL_10_SHDW			0x024c
+#define EMIF_EXT_PHY_CTRL_11				0x0250
+#define EMIF_EXT_PHY_CTRL_11_SHDW			0x0254
+#define EMIF_EXT_PHY_CTRL_12				0x0258
+#define EMIF_EXT_PHY_CTRL_12_SHDW			0x025c
+#define EMIF_EXT_PHY_CTRL_13				0x0260
+#define EMIF_EXT_PHY_CTRL_13_SHDW			0x0264
+#define EMIF_EXT_PHY_CTRL_14				0x0268
+#define EMIF_EXT_PHY_CTRL_14_SHDW			0x026c
+#define EMIF_EXT_PHY_CTRL_15				0x0270
+#define EMIF_EXT_PHY_CTRL_15_SHDW			0x0274
+#define EMIF_EXT_PHY_CTRL_16				0x0278
+#define EMIF_EXT_PHY_CTRL_16_SHDW			0x027c
+#define EMIF_EXT_PHY_CTRL_17				0x0280
+#define EMIF_EXT_PHY_CTRL_17_SHDW			0x0284
+#define EMIF_EXT_PHY_CTRL_18				0x0288
+#define EMIF_EXT_PHY_CTRL_18_SHDW			0x028c
+#define EMIF_EXT_PHY_CTRL_19				0x0290
+#define EMIF_EXT_PHY_CTRL_19_SHDW			0x0294
+#define EMIF_EXT_PHY_CTRL_20				0x0298
+#define EMIF_EXT_PHY_CTRL_20_SHDW			0x029c
+#define EMIF_EXT_PHY_CTRL_21				0x02a0
+#define EMIF_EXT_PHY_CTRL_21_SHDW			0x02a4
+#define EMIF_EXT_PHY_CTRL_22				0x02a8
+#define EMIF_EXT_PHY_CTRL_22_SHDW			0x02ac
+#define EMIF_EXT_PHY_CTRL_23				0x02b0
+#define EMIF_EXT_PHY_CTRL_23_SHDW			0x02b4
+#define EMIF_EXT_PHY_CTRL_24				0x02b8
+#define EMIF_EXT_PHY_CTRL_24_SHDW			0x02bc
+#define EMIF_EXT_PHY_CTRL_25				0x02c0
+#define EMIF_EXT_PHY_CTRL_25_SHDW			0x02c4
+#define EMIF_EXT_PHY_CTRL_26				0x02c8
+#define EMIF_EXT_PHY_CTRL_26_SHDW			0x02cc
+#define EMIF_EXT_PHY_CTRL_27				0x02d0
+#define EMIF_EXT_PHY_CTRL_27_SHDW			0x02d4
+#define EMIF_EXT_PHY_CTRL_28				0x02d8
+#define EMIF_EXT_PHY_CTRL_28_SHDW			0x02dc
+#define EMIF_EXT_PHY_CTRL_29				0x02e0
+#define EMIF_EXT_PHY_CTRL_29_SHDW			0x02e4
+#define EMIF_EXT_PHY_CTRL_30				0x02e8
+#define EMIF_EXT_PHY_CTRL_30_SHDW			0x02ec
+
+/* Registers shifts and masks */
+
+/* EMIF_MODULE_ID_AND_REVISION */
+#define SCHEME_SHIFT					30
+#define SCHEME_MASK					(0x3 << 30)
+#define MODULE_ID_SHIFT					16
+#define MODULE_ID_MASK					(0xfff << 16)
+#define RTL_VERSION_SHIFT				11
+#define RTL_VERSION_MASK				(0x1f << 11)
+#define MAJOR_REVISION_SHIFT				8
+#define MAJOR_REVISION_MASK				(0x7 << 8)
+#define MINOR_REVISION_SHIFT				0
+#define MINOR_REVISION_MASK				(0x3f << 0)
+
+/* STATUS */
+#define BE_SHIFT					31
+#define BE_MASK						(1 << 31)
+#define DUAL_CLK_MODE_SHIFT				30
+#define DUAL_CLK_MODE_MASK				(1 << 30)
+#define FAST_INIT_SHIFT					29
+#define FAST_INIT_MASK					(1 << 29)
+#define RDLVLGATETO_SHIFT				6
+#define RDLVLGATETO_MASK				(1 << 6)
+#define RDLVLTO_SHIFT					5
+#define RDLVLTO_MASK					(1 << 5)
+#define WRLVLTO_SHIFT					4
+#define WRLVLTO_MASK					(1 << 4)
+#define PHY_DLL_READY_SHIFT				2
+#define PHY_DLL_READY_MASK				(1 << 2)
+
+/* SDRAM_CONFIG */
+#define SDRAM_TYPE_SHIFT				29
+#define SDRAM_TYPE_MASK					(0x7 << 29)
+#define IBANK_POS_SHIFT					27
+#define IBANK_POS_MASK					(0x3 << 27)
+#define DDR_TERM_SHIFT					24
+#define DDR_TERM_MASK					(0x7 << 24)
+#define DDR2_DDQS_SHIFT					23
+#define DDR2_DDQS_MASK					(1 << 23)
+#define DYN_ODT_SHIFT					21
+#define DYN_ODT_MASK					(0x3 << 21)
+#define DDR_DISABLE_DLL_SHIFT				20
+#define DDR_DISABLE_DLL_MASK				(1 << 20)
+#define SDRAM_DRIVE_SHIFT				18
+#define SDRAM_DRIVE_MASK				(0x3 << 18)
+#define CWL_SHIFT					16
+#define CWL_MASK					(0x3 << 16)
+#define NARROW_MODE_SHIFT				14
+#define NARROW_MODE_MASK				(0x3 << 14)
+#define CL_SHIFT					10
+#define CL_MASK						(0xf << 10)
+#define ROWSIZE_SHIFT					7
+#define ROWSIZE_MASK					(0x7 << 7)
+#define IBANK_SHIFT					4
+#define IBANK_MASK					(0x7 << 4)
+#define EBANK_SHIFT					3
+#define EBANK_MASK					(1 << 3)
+#define PAGESIZE_SHIFT					0
+#define PAGESIZE_MASK					(0x7 << 0)
+
+/* SDRAM_CONFIG_2 */
+#define CS1NVMEN_SHIFT					30
+#define CS1NVMEN_MASK					(1 << 30)
+#define EBANK_POS_SHIFT					27
+#define EBANK_POS_MASK					(1 << 27)
+#define RDBNUM_SHIFT					4
+#define RDBNUM_MASK					(0x3 << 4)
+#define RDBSIZE_SHIFT					0
+#define RDBSIZE_MASK					(0x7 << 0)
+
+/* SDRAM_REFRESH_CONTROL */
+#define INITREF_DIS_SHIFT				31
+#define INITREF_DIS_MASK				(1 << 31)
+#define SRT_SHIFT					29
+#define SRT_MASK					(1 << 29)
+#define ASR_SHIFT					28
+#define ASR_MASK					(1 << 28)
+#define PASR_SHIFT					24
+#define PASR_MASK					(0x7 << 24)
+#define REFRESH_RATE_SHIFT				0
+#define REFRESH_RATE_MASK				(0xffff << 0)
+
+/* SDRAM_TIMING_1 */
+#define T_RTW_SHIFT					29
+#define T_RTW_MASK					(0x7 << 29)
+#define T_RP_SHIFT					25
+#define T_RP_MASK					(0xf << 25)
+#define T_RCD_SHIFT					21
+#define T_RCD_MASK					(0xf << 21)
+#define T_WR_SHIFT					17
+#define T_WR_MASK					(0xf << 17)
+#define T_RAS_SHIFT					12
+#define T_RAS_MASK					(0x1f << 12)
+#define T_RC_SHIFT					6
+#define T_RC_MASK					(0x3f << 6)
+#define T_RRD_SHIFT					3
+#define T_RRD_MASK					(0x7 << 3)
+#define T_WTR_SHIFT					0
+#define T_WTR_MASK					(0x7 << 0)
+
+/* SDRAM_TIMING_2 */
+#define T_XP_SHIFT					28
+#define T_XP_MASK					(0x7 << 28)
+#define T_ODT_SHIFT					25
+#define T_ODT_MASK					(0x7 << 25)
+#define T_XSNR_SHIFT					16
+#define T_XSNR_MASK					(0x1ff << 16)
+#define T_XSRD_SHIFT					6
+#define T_XSRD_MASK					(0x3ff << 6)
+#define T_RTP_SHIFT					3
+#define T_RTP_MASK					(0x7 << 3)
+#define T_CKE_SHIFT					0
+#define T_CKE_MASK					(0x7 << 0)
+
+/* SDRAM_TIMING_3 */
+#define T_PDLL_UL_SHIFT					28
+#define T_PDLL_UL_MASK					(0xf << 28)
+#define T_CSTA_SHIFT					24
+#define T_CSTA_MASK					(0xf << 24)
+#define T_CKESR_SHIFT					21
+#define T_CKESR_MASK					(0x7 << 21)
+#define ZQ_ZQCS_SHIFT					15
+#define ZQ_ZQCS_MASK					(0x3f << 15)
+#define T_TDQSCKMAX_SHIFT				13
+#define T_TDQSCKMAX_MASK				(0x3 << 13)
+#define T_RFC_SHIFT					4
+#define T_RFC_MASK					(0x1ff << 4)
+#define T_RAS_MAX_SHIFT					0
+#define T_RAS_MAX_MASK					(0xf << 0)
+
+/* POWER_MANAGEMENT_CONTROL */
+#define PD_TIM_SHIFT					12
+#define PD_TIM_MASK					(0xf << 12)
+#define DPD_EN_SHIFT					11
+#define DPD_EN_MASK					(1 << 11)
+#define LP_MODE_SHIFT					8
+#define LP_MODE_MASK					(0x7 << 8)
+#define SR_TIM_SHIFT					4
+#define SR_TIM_MASK					(0xf << 4)
+#define CS_TIM_SHIFT					0
+#define CS_TIM_MASK					(0xf << 0)
+
+/* LPDDR2_MODE_REG_DATA */
+#define VALUE_0_SHIFT					0
+#define VALUE_0_MASK					(0x7f << 0)
+
+/* LPDDR2_MODE_REG_CONFIG */
+#define CS_SHIFT					31
+#define CS_MASK						(1 << 31)
+#define REFRESH_EN_SHIFT				30
+#define REFRESH_EN_MASK					(1 << 30)
+#define ADDRESS_SHIFT					0
+#define ADDRESS_MASK					(0xff << 0)
+
+/* OCP_CONFIG */
+#define SYS_THRESH_MAX_SHIFT				24
+#define SYS_THRESH_MAX_MASK				(0xf << 24)
+#define MPU_THRESH_MAX_SHIFT				20
+#define MPU_THRESH_MAX_MASK				(0xf << 20)
+#define LL_THRESH_MAX_SHIFT				16
+#define LL_THRESH_MAX_MASK				(0xf << 16)
+
+/* PERFORMANCE_COUNTER_1 */
+#define COUNTER1_SHIFT					0
+#define COUNTER1_MASK					(0xffffffff << 0)
+
+/* PERFORMANCE_COUNTER_2 */
+#define COUNTER2_SHIFT					0
+#define COUNTER2_MASK					(0xffffffff << 0)
+
+/* PERFORMANCE_COUNTER_CONFIG */
+#define CNTR2_MCONNID_EN_SHIFT				31
+#define CNTR2_MCONNID_EN_MASK				(1 << 31)
+#define CNTR2_REGION_EN_SHIFT				30
+#define CNTR2_REGION_EN_MASK				(1 << 30)
+#define CNTR2_CFG_SHIFT					16
+#define CNTR2_CFG_MASK					(0xf << 16)
+#define CNTR1_MCONNID_EN_SHIFT				15
+#define CNTR1_MCONNID_EN_MASK				(1 << 15)
+#define CNTR1_REGION_EN_SHIFT				14
+#define CNTR1_REGION_EN_MASK				(1 << 14)
+#define CNTR1_CFG_SHIFT					0
+#define CNTR1_CFG_MASK					(0xf << 0)
+
+/* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */
+#define MCONNID2_SHIFT					24
+#define MCONNID2_MASK					(0xff << 24)
+#define REGION_SEL2_SHIFT				16
+#define REGION_SEL2_MASK				(0x3 << 16)
+#define MCONNID1_SHIFT					8
+#define MCONNID1_MASK					(0xff << 8)
+#define REGION_SEL1_SHIFT				0
+#define REGION_SEL1_MASK				(0x3 << 0)
+
+/* PERFORMANCE_COUNTER_TIME */
+#define TOTAL_TIME_SHIFT				0
+#define TOTAL_TIME_MASK					(0xffffffff << 0)
+
+/* DLL_CALIB_CTRL */
+#define ACK_WAIT_SHIFT					16
+#define ACK_WAIT_MASK					(0xf << 16)
+#define DLL_CALIB_INTERVAL_SHIFT			0
+#define DLL_CALIB_INTERVAL_MASK				(0x1ff << 0)
+
+/* END_OF_INTERRUPT */
+#define EOI_SHIFT					0
+#define EOI_MASK					(1 << 0)
+
+/* SYSTEM_OCP_INTERRUPT_RAW_STATUS */
+#define DNV_SYS_SHIFT					2
+#define DNV_SYS_MASK					(1 << 2)
+#define TA_SYS_SHIFT					1
+#define TA_SYS_MASK					(1 << 1)
+#define ERR_SYS_SHIFT					0
+#define ERR_SYS_MASK					(1 << 0)
+
+/* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */
+#define DNV_LL_SHIFT					2
+#define DNV_LL_MASK					(1 << 2)
+#define TA_LL_SHIFT					1
+#define TA_LL_MASK					(1 << 1)
+#define ERR_LL_SHIFT					0
+#define ERR_LL_MASK					(1 << 0)
+
+/* SYSTEM_OCP_INTERRUPT_ENABLE_SET */
+#define EN_DNV_SYS_SHIFT				2
+#define EN_DNV_SYS_MASK					(1 << 2)
+#define EN_TA_SYS_SHIFT					1
+#define EN_TA_SYS_MASK					(1 << 1)
+#define EN_ERR_SYS_SHIFT					0
+#define EN_ERR_SYS_MASK					(1 << 0)
+
+/* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */
+#define EN_DNV_LL_SHIFT					2
+#define EN_DNV_LL_MASK					(1 << 2)
+#define EN_TA_LL_SHIFT					1
+#define EN_TA_LL_MASK					(1 << 1)
+#define EN_ERR_LL_SHIFT					0
+#define EN_ERR_LL_MASK					(1 << 0)
+
+/* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */
+#define ZQ_CS1EN_SHIFT					31
+#define ZQ_CS1EN_MASK					(1 << 31)
+#define ZQ_CS0EN_SHIFT					30
+#define ZQ_CS0EN_MASK					(1 << 30)
+#define ZQ_DUALCALEN_SHIFT				29
+#define ZQ_DUALCALEN_MASK				(1 << 29)
+#define ZQ_SFEXITEN_SHIFT				28
+#define ZQ_SFEXITEN_MASK				(1 << 28)
+#define ZQ_ZQINIT_MULT_SHIFT				18
+#define ZQ_ZQINIT_MULT_MASK				(0x3 << 18)
+#define ZQ_ZQCL_MULT_SHIFT				16
+#define ZQ_ZQCL_MULT_MASK				(0x3 << 16)
+#define ZQ_REFINTERVAL_SHIFT				0
+#define ZQ_REFINTERVAL_MASK				(0xffff << 0)
+
+/* TEMPERATURE_ALERT_CONFIG */
+#define TA_CS1EN_SHIFT					31
+#define TA_CS1EN_MASK					(1 << 31)
+#define TA_CS0EN_SHIFT					30
+#define TA_CS0EN_MASK					(1 << 30)
+#define TA_SFEXITEN_SHIFT				28
+#define TA_SFEXITEN_MASK				(1 << 28)
+#define TA_DEVWDT_SHIFT					26
+#define TA_DEVWDT_MASK					(0x3 << 26)
+#define TA_DEVCNT_SHIFT					24
+#define TA_DEVCNT_MASK					(0x3 << 24)
+#define TA_REFINTERVAL_SHIFT				0
+#define TA_REFINTERVAL_MASK				(0x3fffff << 0)
+
+/* OCP_ERROR_LOG */
+#define MADDRSPACE_SHIFT				14
+#define MADDRSPACE_MASK					(0x3 << 14)
+#define MBURSTSEQ_SHIFT					11
+#define MBURSTSEQ_MASK					(0x7 << 11)
+#define MCMD_SHIFT					8
+#define MCMD_MASK					(0x7 << 8)
+#define MCONNID_SHIFT					0
+#define MCONNID_MASK					(0xff << 0)
+
+/* DDR_PHY_CTRL_1 - EMIF4D */
+#define DLL_SLAVE_DLY_CTRL_SHIFT_4D			4
+#define DLL_SLAVE_DLY_CTRL_MASK_4D			(0xFF << 4)
+#define READ_LATENCY_SHIFT_4D				0
+#define READ_LATENCY_MASK_4D				(0xf << 0)
+
+/* DDR_PHY_CTRL_1 - EMIF4D5 */
+#define DLL_HALF_DELAY_SHIFT_4D5			21
+#define DLL_HALF_DELAY_MASK_4D5				(1 << 21)
+#define READ_LATENCY_SHIFT_4D5				0
+#define READ_LATENCY_MASK_4D5				(0x1f << 0)
+
+/* DDR_PHY_CTRL_1_SHDW */
+#define DDR_PHY_CTRL_1_SHDW_SHIFT			5
+#define DDR_PHY_CTRL_1_SHDW_MASK			(0x7ffffff << 5)
+#define READ_LATENCY_SHDW_SHIFT				0
+#define READ_LATENCY_SHDW_MASK				(0x1f << 0)
+
+#endif
-- 
1.7.1



From aneesh at ti.com  Fri Mar 16 17:51:43 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 03:21:43 +0530
Subject: [PATCH v4 3/7] misc: emif: add basic infrastructure for EMIF driver
In-Reply-To: <1331934707-29487-1-git-send-email-aneesh@ti.com>
References: <1331934707-29487-1-git-send-email-aneesh@ti.com>
Message-ID: <1331934707-29487-4-git-send-email-aneesh@ti.com>

EMIF is an SDRAM controller used in various Texas Instruments
SoCs. EMIF supports, based on its revision, one or more of
LPDDR2/DDR2/DDR3 protocols.

Add the basic infrastructure for EMIF driver that includes
driver registration, probe, parsing of platform data etc.

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v2:
- replaced __init with __init_or_module

v1:
- Removed emif_cleanup() function and instead used
  devm_* variant of APIs for resource allocations
- Split include/linux/emif.h into two parts. The first
  part now becomes include/linux/platform_data/emif_plat.h
  and the other part is now merged in drivers/misc/emif.h
- Made error messages more verbose
- Corrected copyright year
- Fixed other coding style comments
- Minor adjustments to patch organization. Moved
  some definitions to a subsequent patch that uses
  them
- Added a list a of devices. This is needed for errata
  i728 workaround and for the new locking scheme
- Added documentation for driver
---
 Documentation/misc-devices/ti-emif.txt  |   58 ++++++
 drivers/misc/Kconfig                    |   12 ++
 drivers/misc/Makefile                   |    1 +
 drivers/misc/emif.c                     |  289 +++++++++++++++++++++++++++++++
 drivers/misc/emif.h                     |    7 +
 include/linux/platform_data/emif_plat.h |  128 ++++++++++++++
 6 files changed, 495 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/misc-devices/ti-emif.txt
 create mode 100644 drivers/misc/emif.c
 create mode 100644 include/linux/platform_data/emif_plat.h

diff --git a/Documentation/misc-devices/ti-emif.txt b/Documentation/misc-devices/ti-emif.txt
new file mode 100644
index 0000000..a9238c1
--- /dev/null
+++ b/Documentation/misc-devices/ti-emif.txt
@@ -0,0 +1,58 @@
+TI EMIF SDRAM Controller Driver:
+
+Author
+========
+Aneesh V <aneesh at ti.com>
+
+Location
+============
+driver/misc/emif.c
+
+Supported SoCs:
+===================
+TI OMAP44xx
+TI OMAP54xx
+
+Menuconfig option:
+==========================
+Device Drivers
+	Misc devices
+		Texas Instruments EMIF driver
+
+Description
+===========
+This driver is for the EMIF module available in Texas Instruments
+SoCs. EMIF is an SDRAM controller that, based on its revision,
+supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
+This driver takes care of only LPDDR2 memories presently. The
+functions of the driver includes re-configuring AC timing
+parameters and other settings during frequency, voltage and
+temperature changes
+
+Platform Data (see include/linux/platform_data/emif_plat.h):
+=====================================================================
+DDR device details and other board dependent and SoC dependent
+information can be passed through platform data (struct emif_platform_data)
+- DDR device details: 'struct ddr_device_info'
+- Device AC timings: 'struct lpddr2_timings' and 'struct lpddr2_min_tck'
+- Custom configurations: customizable policy options through
+  'struct emif_custom_configs'
+- IP revision
+- PHY type
+
+Interface to the external world:
+================================
+EMIF driver registers notifiers for voltage and frequency changes
+affecting EMIF and takes appropriate actions when these are invoked.
+- freq_pre_notify_handling()
+- freq_post_notify_handling()
+- volt_notify_handling()
+
+Debugfs
+========
+The driver creates two debugfs entries per device.
+- regcache_dump : dump of register values calculated and saved for all
+  frequencies used so far.
+- mr4 : last polled value of MR4 register in the LPDDR2 device. MR4
+  indicates the current temperature level of the device.
+
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index c779509..847a936 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -441,6 +441,18 @@ config VMWARE_BALLOON
 	  To compile this driver as a module, choose M here: the
 	  module will be called vmw_balloon.
 
+config TI_EMIF
+	tristate "Texas Instruments EMIF driver"
+	select DDR
+	help
+	  This driver is for the EMIF module available in Texas Instruments
+	  SoCs. EMIF is an SDRAM controller that, based on its revision,
+	  supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
+	  This driver takes care of only LPDDR2 memories presently. The
+	  functions of the driver includes re-configuring AC timing
+	  parameters and other settings during frequency, voltage and
+	  temperature changes
+
 config ARM_CHARLCD
 	bool "ARM Ltd. Character LCD Driver"
 	depends on PLAT_VERSATILE
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3e1d801..75ab920 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_TI_DAC7512)	+= ti_dac7512.o
 obj-$(CONFIG_C2PORT)		+= c2port/
 obj-$(CONFIG_IWMC3200TOP)      += iwmc3200top/
 obj-$(CONFIG_HMC6352)		+= hmc6352.o
+obj-$(CONFIG_TI_EMIF)		+= emif.o
 obj-y				+= eeprom/
 obj-y				+= cb710/
 obj-$(CONFIG_SPEAR13XX_PCIE_GADGET)	+= spear13xx_pcie_gadget.o
diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
new file mode 100644
index 0000000..f864640
--- /dev/null
+++ b/drivers/misc/emif.c
@@ -0,0 +1,289 @@
+/*
+ * EMIF driver
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ * Santosh Shilimkar <santosh.shilimkar at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/platform_data/emif_plat.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/seq_file.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <misc/jedec_ddr.h>
+#include "emif.h"
+
+/**
+ * struct emif_data - Per device static data for driver's use
+ * @duplicate:			Whether the DDR devices attached to this EMIF
+ *				instance are exactly same as that on EMIF1. In
+ *				this case we can save some memory and processing
+ * @temperature_level:		Maximum temperature of LPDDR2 devices attached
+ *				to this EMIF - read from MR4 register. If there
+ *				are two devices attached to this EMIF, this
+ *				value is the maximum of the two temperature
+ *				levels.
+ * @node:			node in the device list
+ * @base:			base address of memory-mapped IO registers.
+ * @dev:			device pointer.
+ * @plat_data:			Pointer to saved platform data.
+ */
+struct emif_data {
+	u8				duplicate;
+	u8				temperature_level;
+	struct list_head		node;
+	void __iomem			*base;
+	struct device			*dev;
+	struct emif_platform_data	*plat_data;
+};
+
+static struct emif_data *emif1;
+static LIST_HEAD(device_list);
+
+static void get_default_timings(struct emif_data *emif)
+{
+	struct emif_platform_data *pd = emif->plat_data;
+
+	pd->timings		= lpddr2_jedec_timings;
+	pd->timings_arr_size	= ARRAY_SIZE(lpddr2_jedec_timings);
+
+	dev_warn(emif->dev, "%s: using default timings\n", __func__);
+}
+
+static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
+		u32 ip_rev, struct device *dev)
+{
+	int valid;
+
+	valid = (type == DDR_TYPE_LPDDR2_S4 ||
+			type == DDR_TYPE_LPDDR2_S2)
+		&& (density >= DDR_DENSITY_64Mb
+			&& density <= DDR_DENSITY_8Gb)
+		&& (io_width >= DDR_IO_WIDTH_8
+			&& io_width <= DDR_IO_WIDTH_32);
+
+	/* Combinations of EMIF and PHY revisions that we support today */
+	switch (ip_rev) {
+	case EMIF_4D:
+		valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
+		break;
+	case EMIF_4D5:
+		valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
+		break;
+	default:
+		valid = 0;
+	}
+
+	if (!valid)
+		dev_err(dev, "%s: invalid DDR details\n", __func__);
+	return valid;
+}
+
+static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
+		struct device *dev)
+{
+	int valid = 1;
+
+	if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
+		(cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
+		valid = cust_cfgs->lpmode_freq_threshold &&
+			cust_cfgs->lpmode_timeout_performance &&
+			cust_cfgs->lpmode_timeout_power;
+
+	if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
+		valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
+
+	if (!valid)
+		dev_warn(dev, "%s: invalid custom configs\n", __func__);
+
+	return valid;
+}
+
+static struct emif_data *__init_or_module get_device_details(
+		struct platform_device *pdev)
+{
+	u32				size;
+	struct emif_data		*emif = NULL;
+	struct ddr_device_info		*dev_info;
+	struct emif_custom_configs	*cust_cfgs;
+	struct emif_platform_data	*pd;
+	struct device			*dev;
+	void				*temp;
+
+	pd = pdev->dev.platform_data;
+	dev = &pdev->dev;
+
+	if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
+			pd->device_info->density, pd->device_info->io_width,
+			pd->phy_type, pd->ip_rev, dev))) {
+		dev_err(dev, "%s: invalid device data\n", __func__);
+		goto error;
+	}
+
+	emif	= devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
+	temp	= devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+	dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
+
+	if (!emif || !pd || !dev_info) {
+		dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__);
+		goto error;
+	}
+
+	memcpy(temp, pd, sizeof(*pd));
+	pd = temp;
+	memcpy(dev_info, pd->device_info, sizeof(*dev_info));
+
+	pd->device_info		= dev_info;
+	emif->plat_data		= pd;
+	emif->dev		= dev;
+	emif->temperature_level	= SDRAM_TEMP_NOMINAL;
+
+	/*
+	 * For EMIF instances other than EMIF1 see if the devices connected
+	 * are exactly same as on EMIF1(which is typically the case). If so,
+	 * mark it as a duplicate of EMIF1 and skip copying timings data.
+	 * This will save some memory and some computation later.
+	 */
+	emif->duplicate = emif1 && (memcmp(dev_info,
+		emif1->plat_data->device_info,
+		sizeof(struct ddr_device_info)) == 0);
+
+	if (emif->duplicate) {
+		pd->timings = NULL;
+		pd->min_tck = NULL;
+		goto out;
+	} else if (emif1) {
+		dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
+			__func__);
+	}
+
+	/*
+	 * Copy custom configs - ignore allocation error, if any, as
+	 * custom_configs is not very critical
+	 */
+	cust_cfgs = pd->custom_configs;
+	if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
+		temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
+		if (temp)
+			memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
+		else
+			dev_warn(dev, "%s:%d: allocation error\n", __func__,
+				__LINE__);
+		pd->custom_configs = temp;
+	}
+
+	/*
+	 * Copy timings and min-tck values from platform data. If it is not
+	 * available or if memory allocation fails, use JEDEC defaults
+	 */
+	size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
+	if (pd->timings) {
+		temp = devm_kzalloc(dev, size, GFP_KERNEL);
+		if (temp) {
+			memcpy(temp, pd->timings, sizeof(*pd->timings));
+			pd->timings = temp;
+		} else {
+			dev_warn(dev, "%s:%d: allocation error\n", __func__,
+				__LINE__);
+			get_default_timings(emif);
+		}
+	} else {
+		get_default_timings(emif);
+	}
+
+	if (pd->min_tck) {
+		temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
+		if (temp) {
+			memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
+			pd->min_tck = temp;
+		} else {
+			dev_warn(dev, "%s:%d: allocation error\n", __func__,
+				__LINE__);
+			pd->min_tck = &lpddr2_jedec_min_tck;
+		}
+	} else {
+		pd->min_tck = &lpddr2_jedec_min_tck;
+	}
+
+out:
+	return emif;
+
+error:
+	return NULL;
+}
+
+static int __init_or_module emif_probe(struct platform_device *pdev)
+{
+	struct emif_data	*emif;
+	struct resource		*res;
+
+	emif = get_device_details(pdev);
+	if (!emif) {
+		pr_err("%s: error getting device data\n", __func__);
+		goto error;
+	}
+
+	if (!emif1)
+		emif1 = emif;
+
+	list_add(&emif->node, &device_list);
+
+	/* Save pointers to each other in emif and device structures */
+	emif->dev = &pdev->dev;
+	platform_set_drvdata(pdev, emif);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(emif->dev, "%s: error getting memory resource\n",
+			__func__);
+		goto error;
+	}
+
+	emif->base = devm_request_and_ioremap(emif->dev, res);
+	if (!emif->base) {
+		dev_err(emif->dev, "%s: devm_request_and_ioremap() failed\n",
+			__func__);
+		goto error;
+	}
+
+	dev_info(&pdev->dev, "%s: device configured with addr = %p\n",
+		__func__, emif->base);
+
+	return 0;
+error:
+	return -ENODEV;
+}
+
+static struct platform_driver emif_driver = {
+	.driver = {
+		.name = "emif",
+	},
+};
+
+static int __init_or_module emif_register(void)
+{
+	return platform_driver_probe(&emif_driver, emif_probe);
+}
+
+static void __exit emif_unregister(void)
+{
+	platform_driver_unregister(&emif_driver);
+}
+
+module_init(emif_register);
+module_exit(emif_unregister);
+MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:emif");
+MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/drivers/misc/emif.h b/drivers/misc/emif.h
index 44b97df..692b2a8 100644
--- a/drivers/misc/emif.h
+++ b/drivers/misc/emif.h
@@ -12,6 +12,13 @@
 #ifndef __EMIF_H
 #define __EMIF_H
 
+/*
+ * Maximum number of different frequencies supported by EMIF driver
+ * Determines the number of entries in the pointer array for register
+ * cache
+ */
+#define EMIF_MAX_NUM_FREQUENCIES			6
+
 /* Registers offset */
 #define EMIF_MODULE_ID_AND_REVISION			0x0000
 #define EMIF_STATUS					0x0004
diff --git a/include/linux/platform_data/emif_plat.h b/include/linux/platform_data/emif_plat.h
new file mode 100644
index 0000000..03378ca
--- /dev/null
+++ b/include/linux/platform_data/emif_plat.h
@@ -0,0 +1,128 @@
+/*
+ * Definitions for TI EMIF device platform data
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __EMIF_PLAT_H
+#define __EMIF_PLAT_H
+
+/* Low power modes - EMIF_PWR_MGMT_CTRL */
+#define EMIF_LP_MODE_DISABLE				0
+#define EMIF_LP_MODE_CLOCK_STOP				1
+#define EMIF_LP_MODE_SELF_REFRESH			2
+#define EMIF_LP_MODE_PWR_DN				4
+
+/* Hardware capabilities */
+#define	EMIF_HW_CAPS_LL_INTERFACE			0x00000001
+
+/*
+ * EMIF IP Revisions
+ *	EMIF4D  - Used in OMAP4
+ *	EMIF4D5 - Used in OMAP5
+ */
+#define	EMIF_4D						1
+#define	EMIF_4D5					2
+
+/*
+ * PHY types
+ *	ATTILAPHY  - Used in OMAP4
+ *	INTELLIPHY - Used in OMAP5
+ */
+#define	EMIF_PHY_TYPE_ATTILAPHY				1
+#define	EMIF_PHY_TYPE_INTELLIPHY			2
+
+/* Custom config requests */
+#define EMIF_CUSTOM_CONFIG_LPMODE			0x00000001
+#define EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL	0x00000002
+
+#ifndef __ASSEMBLY__
+/**
+ * struct ddr_device_info - All information about the DDR device except AC
+ *		timing parameters
+ * @type:	Device type (LPDDR2-S4, LPDDR2-S2 etc)
+ * @density:	Device density
+ * @io_width:	Bus width
+ * @cs1_used:	Whether there is a DDR device attached to the second
+ *		chip-select(CS1) of this EMIF instance
+ * @cal_resistors_per_cs: Whether there is one calibration resistor per
+ *		chip-select or whether it's a single one for both
+ * @manufacturer: Manufacturer name string
+ */
+struct ddr_device_info {
+	u32	type;
+	u32	density;
+	u32	io_width;
+	u32	cs1_used;
+	u32	cal_resistors_per_cs;
+	char	manufacturer[10];
+};
+
+/**
+ * struct emif_custom_configs - Custom configuration parameters/policies
+ *		passed from the platform layer
+ * @mask:	Mask to indicate which configs are requested
+ * @lpmode:	LPMODE to be used in PWR_MGMT_CTRL register
+ * @lpmode_timeout_performance: Timeout before LPMODE entry when higher
+ *		performance is desired at the cost of power (typically
+ *		at higher OPPs)
+ * @lpmode_timeout_power: Timeout before LPMODE entry when better power
+ *		savings is desired and performance is not important
+ *		(typically at lower loads indicated by lower OPPs)
+ * @lpmode_freq_threshold: The DDR frequency threshold to identify between
+ *		the above two cases:
+ *		timeout = (freq >= lpmode_freq_threshold) ?
+ *			lpmode_timeout_performance :
+ *			lpmode_timeout_power;
+ * @temp_alert_poll_interval_ms: LPDDR2 MR4 polling interval at nominal
+ *		temperature(in milliseconds). When temperature is high
+ *		polling is done 4 times as frequently.
+ */
+struct emif_custom_configs {
+	u32 mask;
+	u32 lpmode;
+	u32 lpmode_timeout_performance;
+	u32 lpmode_timeout_power;
+	u32 lpmode_freq_threshold;
+	u32 temp_alert_poll_interval_ms;
+};
+
+/**
+ * struct emif_platform_data - Platform data passed on EMIF platform
+ *				device creation. Used by the driver.
+ * @hw_caps:		Hw capabilities of the EMIF IP in the respective SoC
+ * @device_info:	Device info structure containing information such
+ *			as type, bus width, density etc
+ * @timings:		Timings information from device datasheet passed
+ *			as an array of 'struct lpddr2_timings'. Can be NULL
+ *			if if default timings are ok
+ * @timings_arr_size:	Size of the timings array. Depends on the number
+ *			of different frequencies for which timings data
+ *			is provided
+ * @min_tck:		Minimum value of some timing parameters in terms
+ *			of number of cycles. Can be NULL if default values
+ *			are ok
+ * @custom_configs:	Custom configurations requested by SoC or board
+ *			code and the data for them. Can be NULL if default
+ *			configurations done by the driver are ok. See
+ *			documentation for 'struct emif_custom_configs' for
+ *			more details
+ */
+struct emif_platform_data {
+	u32 hw_caps;
+	struct ddr_device_info *device_info;
+	const struct lpddr2_timings *timings;
+	u32 timings_arr_size;
+	const struct lpddr2_min_tck *min_tck;
+	struct emif_custom_configs *custom_configs;
+	u32 ip_rev;
+	u32 phy_type;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif /* __LINUX_EMIF_H */
-- 
1.7.1



From aneesh at ti.com  Fri Mar 16 17:51:44 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 03:21:44 +0530
Subject: [PATCH v4 4/7] misc: emif: handle frequency and voltage change events
In-Reply-To: <1331934707-29487-1-git-send-email-aneesh@ti.com>
References: <1331934707-29487-1-git-send-email-aneesh@ti.com>
Message-ID: <1331934707-29487-5-git-send-email-aneesh@ti.com>

Change SDRAM timings and other settings as necessary
on voltage and frequency changes. We calculate these
register settings based on data from the device data
sheet and inputs such a frequency, voltage state(stable
or ramping), temperature level etc.

TODO: frequency and voltage change handling needs to
be integrated with clock framework and regulator
framework respectively. This is not done today
due to missing pieces in the kernel.

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v1:
- Added comment in commit log as well as code about
  missing integration part that needs to be done in
  future
- Removed some settings that were relevant only for
  DDR3
- Correction in temperature derated value of tim3
- Added errata i735 and i728  workarounds. As part of
  this we need to now maintain a list of all devices
  in the driver and iterate through them in some cases
- Improved synchronization. Added protection for newly
  identified cases of potential race conditions.
- Minor changes in patch organization. struct members
  needed by this patch now defined here.
---
 drivers/misc/emif.c |  894 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 drivers/misc/emif.h |  130 ++++++++-
 2 files changed, 1020 insertions(+), 4 deletions(-)

diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index f864640..1ca8165 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
@@ -21,6 +21,7 @@
 #include <linux/seq_file.h>
 #include <linux/module.h>
 #include <linux/list.h>
+#include <linux/spinlock.h>
 #include <misc/jedec_ddr.h>
 #include "emif.h"
 
@@ -37,20 +38,595 @@
  * @node:			node in the device list
  * @base:			base address of memory-mapped IO registers.
  * @dev:			device pointer.
+ * @addressing			table with addressing information from the spec
+ * @regs_cache:			An array of 'struct emif_regs' that stores
+ *				calculated register values for different
+ *				frequencies, to avoid re-calculating them on
+ *				each DVFS transition.
+ * @curr_regs:			The set of register values used in the last
+ *				frequency change (i.e. corresponding to the
+ *				frequency in effect at the moment)
  * @plat_data:			Pointer to saved platform data.
  */
 struct emif_data {
 	u8				duplicate;
 	u8				temperature_level;
+	u8				lpmode;
 	struct list_head		node;
+	unsigned long			irq_state;
 	void __iomem			*base;
 	struct device			*dev;
+	const struct lpddr2_addressing	*addressing;
+	struct emif_regs		*regs_cache[EMIF_MAX_NUM_FREQUENCIES];
+	struct emif_regs		*curr_regs;
 	struct emif_platform_data	*plat_data;
 };
 
 static struct emif_data *emif1;
+static spinlock_t	emif_lock;
+static unsigned long	irq_state;
+static u32		t_ck; /* DDR clock period in ps */
 static LIST_HEAD(device_list);
 
+/*
+ * Calculate the period of DDR clock from frequency value
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+	/* Divide 10^12 by frequency to get period in ps */
+	t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
+}
+
+/*
+ * Get the CL from SDRAM_CONFIG register
+ */
+static u32 get_cl(struct emif_data *emif)
+{
+	u32		cl;
+	void __iomem	*base = emif->base;
+
+	cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
+
+	return cl;
+}
+
+static void set_lpmode(struct emif_data *emif, u8 lpmode)
+{
+	u32 temp;
+	void __iomem *base = emif->base;
+
+	temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
+	temp &= ~LP_MODE_MASK;
+	temp |= (lpmode << LP_MODE_SHIFT);
+	writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
+}
+
+static void do_freq_update(void)
+{
+	struct emif_data *emif;
+
+	/*
+	 * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
+	 *
+	 * i728 DESCRIPTION:
+	 * The EMIF automatically puts the SDRAM into self-refresh mode
+	 * after the EMIF has not performed accesses during
+	 * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
+	 * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
+	 * to 0x2. If during a small window the following three events
+	 * occur:
+	 * - The SR_TIMING counter expires
+	 * - And frequency change is requested
+	 * - And OCP access is requested
+	 * Then it causes instable clock on the DDR interface.
+	 *
+	 * WORKAROUND
+	 * To avoid the occurrence of the three events, the workaround
+	 * is to disable the self-refresh when requesting a frequency
+	 * change. Before requesting a frequency change the software must
+	 * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
+	 * frequency change has been done, the software can reprogram
+	 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
+	 */
+	list_for_each_entry(emif, &device_list, node) {
+		if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
+			set_lpmode(emif, EMIF_LP_MODE_DISABLE);
+	}
+
+	/*
+	 * TODO: Do FREQ_UPDATE here when an API
+	 * is available for this as part of the new
+	 * clock framework
+	 */
+
+	list_for_each_entry(emif, &device_list, node) {
+		if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
+			set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
+	}
+}
+
+/* Find addressing table entry based on the device's type and density */
+static const struct lpddr2_addressing *get_addressing_table(
+	const struct ddr_device_info *device_info)
+{
+	u32		index, type, density;
+
+	type = device_info->type;
+	density = device_info->density;
+
+	switch (type) {
+	case DDR_TYPE_LPDDR2_S4:
+		index = density - 1;
+		break;
+	case DDR_TYPE_LPDDR2_S2:
+		switch (density) {
+		case DDR_DENSITY_1Gb:
+		case DDR_DENSITY_2Gb:
+			index = density + 3;
+			break;
+		default:
+			index = density - 1;
+		}
+		break;
+	default:
+		return NULL;
+	}
+
+	return &lpddr2_jedec_addressing_table[index];
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
+		u32 freq)
+{
+	u32				i, min, max, freq_nearest;
+	const struct lpddr2_timings	*timings = NULL;
+	const struct lpddr2_timings	*timings_arr = emif->plat_data->timings;
+	struct				device *dev = emif->dev;
+
+	/* Start with a very high frequency - 1GHz */
+	freq_nearest = 1000000000;
+
+	/*
+	 * Find the timings table such that:
+	 *  1. the frequency range covers the required frequency(safe) AND
+	 *  2. the max_freq is closest to the required frequency(optimal)
+	 */
+	for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
+		max = timings_arr[i].max_freq;
+		min = timings_arr[i].min_freq;
+		if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
+			freq_nearest = max;
+			timings = &timings_arr[i];
+		}
+	}
+
+	if (!timings)
+		dev_err(dev, "%s: couldn't find timings for - %dHz\n",
+			__func__, freq);
+
+	dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
+		__func__, freq, freq_nearest);
+
+	return timings;
+}
+
+static u32 get_sdram_ref_ctrl_shdw(u32 freq,
+		const struct lpddr2_addressing *addressing)
+{
+	u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
+
+	/* Scale down frequency and t_refi to avoid overflow */
+	freq_khz = freq / 1000;
+	t_refi = addressing->tREFI_ns / 100;
+
+	/*
+	 * refresh rate to be set is 'tREFI(in us) * freq in MHz
+	 * division by 10000 to account for change in units
+	 */
+	val = t_refi * freq_khz / 10000;
+	ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
+
+	return ref_ctrl_shdw;
+}
+
+static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,
+		const struct lpddr2_min_tck *min_tck,
+		const struct lpddr2_addressing *addressing)
+{
+	u32 tim1 = 0, val = 0;
+
+	val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
+	tim1 |= val << T_WTR_SHIFT;
+
+	if (addressing->num_banks == B8)
+		val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
+	else
+		val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
+	tim1 |= (val - 1) << T_RRD_SHIFT;
+
+	val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
+	tim1 |= val << T_RC_SHIFT;
+
+	val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
+	tim1 |= (val - 1) << T_RAS_SHIFT;
+
+	val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
+	tim1 |= val << T_WR_SHIFT;
+
+	val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
+	tim1 |= val << T_RCD_SHIFT;
+
+	val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
+	tim1 |= val << T_RP_SHIFT;
+
+	return tim1;
+}
+
+static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,
+		const struct lpddr2_min_tck *min_tck,
+		const struct lpddr2_addressing *addressing)
+{
+	u32 tim1 = 0, val = 0;
+
+	val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
+	tim1 = val << T_WTR_SHIFT;
+
+	/*
+	 * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
+	 * to tFAW for de-rating
+	 */
+	if (addressing->num_banks == B8) {
+		val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
+	} else {
+		val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
+		val = max(min_tck->tRRD, val) - 1;
+	}
+	tim1 |= val << T_RRD_SHIFT;
+
+	val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
+	tim1 |= (val - 1) << T_RC_SHIFT;
+
+	val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
+	val = max(min_tck->tRASmin, val) - 1;
+	tim1 |= val << T_RAS_SHIFT;
+
+	val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
+	tim1 |= val << T_WR_SHIFT;
+
+	val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
+	tim1 |= (val - 1) << T_RCD_SHIFT;
+
+	val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
+	tim1 |= (val - 1) << T_RP_SHIFT;
+
+	return tim1;
+}
+
+static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings,
+		const struct lpddr2_min_tck *min_tck,
+		const struct lpddr2_addressing *addressing,
+		u32 type)
+{
+	u32 tim2 = 0, val = 0;
+
+	val = min_tck->tCKE - 1;
+	tim2 |= val << T_CKE_SHIFT;
+
+	val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
+	tim2 |= val << T_RTP_SHIFT;
+
+	/* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
+	val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
+	tim2 |= val << T_XSNR_SHIFT;
+
+	/* XSRD same as XSNR for LPDDR2 */
+	tim2 |= val << T_XSRD_SHIFT;
+
+	val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
+	tim2 |= val << T_XP_SHIFT;
+
+	return tim2;
+}
+
+static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
+		const struct lpddr2_min_tck *min_tck,
+		const struct lpddr2_addressing *addressing,
+		u32 type, u32 ip_rev, u32 derated)
+{
+	u32 tim3 = 0, val = 0, t_dqsck;
+
+	val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
+	val = val > 0xF ? 0xF : val;
+	tim3 |= val << T_RAS_MAX_SHIFT;
+
+	val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
+	tim3 |= val << T_RFC_SHIFT;
+
+	t_dqsck = (derated == EMIF_DERATED_TIMINGS) ?
+		timings->tDQSCK_max_derated : timings->tDQSCK_max;
+	if (ip_rev == EMIF_4D5)
+		val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
+	else
+		val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
+
+	tim3 |= val << T_TDQSCKMAX_SHIFT;
+
+	val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
+	tim3 |= val << ZQ_ZQCS_SHIFT;
+
+	val = DIV_ROUND_UP(timings->tCKESR, t_ck);
+	val = max(min_tck->tCKESR, val) - 1;
+	tim3 |= val << T_CKESR_SHIFT;
+
+	if (ip_rev == EMIF_4D5) {
+		tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
+
+		val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
+		tim3 |= val << T_PDLL_UL_SHIFT;
+	}
+
+	return tim3;
+}
+
+static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
+{
+	u32 idle = 0, val = 0;
+
+	/*
+	 * Maximum value in normal conditions and increased frequency
+	 * when voltage is ramping
+	 */
+	if (volt_ramp)
+		val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
+	else
+		val = 0x1FF;
+
+	/*
+	 * READ_IDLE_CTRL register in EMIF4D has same offset and fields
+	 * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
+	 */
+	idle |= val << DLL_CALIB_INTERVAL_SHIFT;
+	idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT;
+
+	return idle;
+}
+
+static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp)
+{
+	u32 calib = 0, val = 0;
+
+	if (volt_ramp == DDR_VOLTAGE_RAMPING)
+		val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
+	else
+		val = 0; /* Disabled when voltage is stable */
+
+	calib |= val << DLL_CALIB_INTERVAL_SHIFT;
+	calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT;
+
+	return calib;
+}
+
+static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings,
+	u32 freq, u8 RL)
+{
+	u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
+
+	val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
+	phy |= val << READ_LATENCY_SHIFT_4D;
+
+	if (freq <= 100000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
+	else if (freq <= 200000000)
+		val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
+	else
+		val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
+
+	phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;
+
+	return phy;
+}
+
+static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl)
+{
+	u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay;
+
+	/*
+	 * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
+	 * half-delay is not needed else set half-delay
+	 */
+	if (freq >= 265000000 && freq < 267000000)
+		half_delay = 0;
+	else
+		half_delay = 1;
+
+	phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5;
+	phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS,
+			t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
+
+	return phy;
+}
+
+static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void)
+{
+	u32 fifo_we_slave_ratio;
+
+	fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
+		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
+
+	return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 |
+		fifo_we_slave_ratio << 22;
+}
+
+static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void)
+{
+	u32 fifo_we_slave_ratio;
+
+	fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
+		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
+
+	return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 |
+		fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23;
+}
+
+static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void)
+{
+	u32 fifo_we_slave_ratio;
+
+	fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
+		EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
+
+	return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 |
+		fifo_we_slave_ratio << 13;
+}
+
+static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
+{
+	u32 pwr_mgmt_ctrl	= 0, timeout;
+	u32 lpmode		= EMIF_LP_MODE_SELF_REFRESH;
+	u32 timeout_perf	= EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
+	u32 timeout_pwr		= EMIF_LP_MODE_TIMEOUT_POWER;
+	u32 freq_threshold	= EMIF_LP_MODE_FREQ_THRESHOLD;
+
+	struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
+
+	if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
+		lpmode		= cust_cfgs->lpmode;
+		timeout_perf	= cust_cfgs->lpmode_timeout_performance;
+		timeout_pwr	= cust_cfgs->lpmode_timeout_power;
+		freq_threshold  = cust_cfgs->lpmode_freq_threshold;
+	}
+
+	/* Timeout based on DDR frequency */
+	timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
+
+	/* The value to be set in register is "log2(timeout) - 3" */
+	if (timeout < 16) {
+		timeout = 0;
+	} else {
+		timeout = __fls(timeout) - 3;
+		if (timeout & (timeout - 1))
+			timeout++;
+	}
+
+	switch (lpmode) {
+	case EMIF_LP_MODE_CLOCK_STOP:
+		pwr_mgmt_ctrl = (timeout << CS_TIM_SHIFT) |
+					SR_TIM_MASK | PD_TIM_MASK;
+		break;
+	case EMIF_LP_MODE_SELF_REFRESH:
+		/* Workaround for errata i735 */
+		if (timeout < 6)
+			timeout = 6;
+
+		pwr_mgmt_ctrl = (timeout << SR_TIM_SHIFT) |
+					CS_TIM_MASK | PD_TIM_MASK;
+		break;
+	case EMIF_LP_MODE_PWR_DN:
+		pwr_mgmt_ctrl = (timeout << PD_TIM_SHIFT) |
+					CS_TIM_MASK | SR_TIM_MASK;
+		break;
+	case EMIF_LP_MODE_DISABLE:
+	default:
+		pwr_mgmt_ctrl = CS_TIM_MASK |
+					PD_TIM_MASK | SR_TIM_MASK;
+	}
+
+	/* No CS_TIM in EMIF_4D5 */
+	if (ip_rev == EMIF_4D5)
+		pwr_mgmt_ctrl &= ~CS_TIM_MASK;
+
+	pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
+
+	return pwr_mgmt_ctrl;
+}
+
+/*
+ * Program EMIF shadow registers that are not dependent on temperature
+ * or voltage
+ */
+static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
+{
+	void __iomem	*base = emif->base;
+
+	writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
+	writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
+
+	/* Settings specific for EMIF4D5 */
+	if (emif->plat_data->ip_rev != EMIF_4D5)
+		return;
+	writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
+	writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
+	writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
+}
+
+/*
+ * When voltage ramps dll calibration and forced read idle should
+ * happen more often
+ */
+static void setup_volt_sensitive_regs(struct emif_data *emif,
+		struct emif_regs *regs, u32 volt_state)
+{
+	u32		calib_ctrl;
+	void __iomem	*base = emif->base;
+
+	/*
+	 * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
+	 * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
+	 * is an alias of the respective read_idle_ctrl_shdw_* (members of
+	 * a union). So, the below code takes care of both cases
+	 */
+	if (volt_state == DDR_VOLTAGE_RAMPING)
+		calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp;
+	else
+		calib_ctrl = regs->dll_calib_ctrl_shdw_normal;
+
+	writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
+}
+
+/*
+ * setup_temperature_sensitive_regs() - set the timings for temperature
+ * sensitive registers. This happens once at initialisation time based
+ * on the temperature at boot time and subsequently based on the temperature
+ * alert interrupt. Temperature alert can happen when the temperature
+ * increases or drops. So this function can have the effect of either
+ * derating the timings or going back to nominal values.
+ */
+static void setup_temperature_sensitive_regs(struct emif_data *emif,
+		struct emif_regs *regs)
+{
+	u32		tim1, tim3, ref_ctrl, type;
+	void __iomem	*base = emif->base;
+	u32		temperature;
+
+	type = emif->plat_data->device_info->type;
+
+	tim1 = regs->sdram_tim1_shdw;
+	tim3 = regs->sdram_tim3_shdw;
+	ref_ctrl = regs->ref_ctrl_shdw;
+
+	/* No de-rating for non-lpddr2 devices */
+	if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
+		goto out;
+
+	temperature = emif->temperature_level;
+	if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
+		ref_ctrl = regs->ref_ctrl_shdw_derated;
+	} else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
+		tim1 = regs->sdram_tim1_shdw_derated;
+		tim3 = regs->sdram_tim3_shdw_derated;
+		ref_ctrl = regs->ref_ctrl_shdw_derated;
+	}
+
+out:
+	writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
+	writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
+	writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
+}
+
 static void get_default_timings(struct emif_data *emif)
 {
 	struct emif_platform_data *pd = emif->plat_data;
@@ -234,10 +810,8 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 		goto error;
 	}
 
-	if (!emif1)
-		emif1 = emif;
-
 	list_add(&emif->node, &device_list);
+	emif->addressing = get_addressing_table(emif->plat_data->device_info);
 
 	/* Save pointers to each other in emif and device structures */
 	emif->dev = &pdev->dev;
@@ -257,6 +831,18 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 		goto error;
 	}
 
+	/* One-time actions taken on probing the first device */
+	if (!emif1) {
+		emif1 = emif;
+		spin_lock_init(&emif_lock);
+
+		/*
+		 * TODO: register notifiers for frequency and voltage
+		 * change here once the respective frameworks are
+		 * available
+		 */
+	}
+
 	dev_info(&pdev->dev, "%s: device configured with addr = %p\n",
 		__func__, emif->base);
 
@@ -265,6 +851,308 @@ error:
 	return -ENODEV;
 }
 
+static int get_emif_reg_values(struct emif_data *emif, u32 freq,
+		struct emif_regs *regs)
+{
+	u32				cs1_used, ip_rev, phy_type;
+	u32				cl, type;
+	const struct lpddr2_timings	*timings;
+	const struct lpddr2_min_tck	*min_tck;
+	const struct ddr_device_info	*device_info;
+	const struct lpddr2_addressing	*addressing;
+	struct emif_data		*emif_for_calc;
+	struct device			*dev;
+	const struct emif_custom_configs *custom_configs;
+
+	dev = emif->dev;
+	/*
+	 * If the devices on this EMIF instance is duplicate of EMIF1,
+	 * use EMIF1 details for the calculation
+	 */
+	emif_for_calc	= emif->duplicate ? emif1 : emif;
+	timings		= get_timings_table(emif_for_calc, freq);
+	addressing	= emif_for_calc->addressing;
+	if (!timings || !addressing) {
+		dev_err(dev, "%s: not enough data available for %dHz",
+			__func__, freq);
+		return -1;
+	}
+
+	device_info	= emif_for_calc->plat_data->device_info;
+	type		= device_info->type;
+	cs1_used	= device_info->cs1_used;
+	ip_rev		= emif_for_calc->plat_data->ip_rev;
+	phy_type	= emif_for_calc->plat_data->phy_type;
+
+	min_tck		= emif_for_calc->plat_data->min_tck;
+	custom_configs	= emif_for_calc->plat_data->custom_configs;
+
+	set_ddr_clk_period(freq);
+
+	regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing);
+	regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck,
+			addressing);
+	regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck,
+			addressing, type);
+	regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck,
+		addressing, type, ip_rev, EMIF_NORMAL_TIMINGS);
+
+	cl = get_cl(emif);
+
+	if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) {
+		regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
+			timings, freq, cl);
+	} else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) {
+		regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
+		regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5();
+		regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5();
+		regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5();
+	} else {
+		return -1;
+	}
+
+	/* Only timeout values in pwr_mgmt_ctrl_shdw register */
+	regs->pwr_mgmt_ctrl_shdw =
+		get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) &
+		(CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK);
+
+	if (ip_rev & EMIF_4D) {
+		regs->read_idle_ctrl_shdw_normal =
+			get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE);
+
+		regs->read_idle_ctrl_shdw_volt_ramp =
+			get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING);
+	} else if (ip_rev & EMIF_4D5) {
+		regs->dll_calib_ctrl_shdw_normal =
+			get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE);
+
+		regs->dll_calib_ctrl_shdw_volt_ramp =
+			get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING);
+	}
+
+	if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
+		regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4,
+			addressing);
+
+		regs->sdram_tim1_shdw_derated =
+			get_sdram_tim_1_shdw_derated(timings, min_tck,
+				addressing);
+
+		regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings,
+			min_tck, addressing, type, ip_rev,
+			EMIF_DERATED_TIMINGS);
+	}
+
+	regs->freq = freq;
+
+	return 0;
+}
+
+/*
+ * get_regs() - gets the cached emif_regs structure for a given EMIF instance
+ * given frequency(freq):
+ *
+ * As an optimisation, every EMIF instance other than EMIF1 shares the
+ * register cache with EMIF1 if the devices connected on this instance
+ * are same as that on EMIF1(indicated by the duplicate flag)
+ *
+ * If we do not have an entry corresponding to the frequency given, we
+ * allocate a new entry and calculate the values
+ *
+ * Upon finding the right reg dump, save it in curr_regs. It can be
+ * directly used for thermal de-rating and voltage ramping changes.
+ */
+static struct emif_regs *get_regs(struct emif_data *emif, u32 freq)
+{
+	int			i;
+	struct emif_regs	**regs_cache;
+	struct emif_regs	*regs = NULL;
+	struct device		*dev;
+
+	dev = emif->dev;
+	if (emif->curr_regs && emif->curr_regs->freq == freq) {
+		dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq);
+		return emif->curr_regs;
+	}
+
+	if (emif->duplicate)
+		regs_cache = emif1->regs_cache;
+	else
+		regs_cache = emif->regs_cache;
+
+	for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
+		if (regs_cache[i]->freq == freq) {
+			regs = regs_cache[i];
+			dev_dbg(dev,
+				"%s: reg dump found in reg cache for %u Hz\n",
+				__func__, freq);
+			break;
+		}
+	}
+
+	/*
+	 * If we don't have an entry for this frequency in the cache create one
+	 * and calculate the values
+	 */
+	if (!regs) {
+		regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC);
+		if (!regs)
+			return NULL;
+
+		if (get_emif_reg_values(emif, freq, regs)) {
+			devm_kfree(emif->dev, regs);
+			return NULL;
+		}
+
+		/*
+		 * Now look for an un-used entry in the cache and save the
+		 * newly created struct. If there are no free entries
+		 * over-write the last entry
+		 */
+		for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++)
+			;
+
+		if (i >= EMIF_MAX_NUM_FREQUENCIES) {
+			dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n",
+				__func__);
+			i = EMIF_MAX_NUM_FREQUENCIES - 1;
+			devm_kfree(emif->dev, regs_cache[i]);
+		}
+		regs_cache[i] = regs;
+	}
+
+	return regs;
+}
+
+static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state)
+{
+	dev_dbg(emif->dev, "%s: voltage notification : %d", __func__,
+		volt_state);
+
+	if (!emif->curr_regs) {
+		dev_err(emif->dev,
+			"%s: volt-notify before registers are ready: %d\n",
+			__func__, volt_state);
+		return;
+	}
+
+	setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state);
+}
+
+/*
+ * TODO: voltage notify handling should be hooked up to
+ * regulator framework as soon as the necessary support
+ * is available in mainline kernel. This function is un-used
+ * right now.
+ */
+static void __attribute__((unused)) volt_notify_handling(u32 volt_state)
+{
+	struct emif_data *emif;
+
+	spin_lock_irqsave(&emif_lock, irq_state);
+
+	list_for_each_entry(emif, &device_list, node)
+		do_volt_notify_handling(emif, volt_state);
+	do_freq_update();
+
+	spin_unlock_irqrestore(&emif_lock, irq_state);
+}
+
+static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq)
+{
+	struct emif_regs *regs;
+
+	regs = get_regs(emif, new_freq);
+	if (!regs)
+		return;
+
+	emif->curr_regs = regs;
+
+	/*
+	 * Update the shadow registers:
+	 * Temperature and voltage-ramp sensitive settings are also configured
+	 * in terms of DDR cycles. So, we need to update them too when there
+	 * is a freq change
+	 */
+	dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz",
+		__func__, new_freq);
+	setup_registers(emif, regs);
+	setup_temperature_sensitive_regs(emif, regs);
+	setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE);
+
+	/*
+	 * Part of workaround for errata i728. See do_freq_update()
+	 * for more details
+	 */
+	if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
+		set_lpmode(emif, EMIF_LP_MODE_DISABLE);
+}
+
+/*
+ * TODO: frequency notify handling should be hooked up to
+ * clock framework as soon as the necessary support is
+ * available in mainline kernel. This function is un-used
+ * right now.
+ */
+static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq)
+{
+	struct emif_data *emif;
+
+	/*
+	 * NOTE: we are taking the spin-lock here and releases it
+	 * only in post-notifier. This doesn't look good and
+	 * Sparse complains about it, but this seems to be
+	 * un-avoidable. We need to lock a sequence of events
+	 * that is split between EMIF and clock framework.
+	 *
+	 * 1. EMIF driver updates EMIF timings in shadow registers in the
+	 *    frequency pre-notify callback from clock framework
+	 * 2. clock framework sets up the registers for the new frequency
+	 * 3. clock framework initiates a hw-sequence that updates
+	 *    the frequency EMIF timings synchronously.
+	 *
+	 * All these 3 steps should be performed as an atomic operation
+	 * vis-a-vis similar sequence in the EMIF interrupt handler
+	 * for temperature events. Otherwise, there could be race
+	 * conditions that could result in incorrect EMIF timings for
+	 * a given frequency
+	 */
+	spin_lock_irqsave(&emif_lock, irq_state);
+
+	list_for_each_entry(emif, &device_list, node)
+		do_freq_pre_notify_handling(emif, new_freq);
+}
+
+static void do_freq_post_notify_handling(struct emif_data *emif)
+{
+	/*
+	 * Part of workaround for errata i728. See do_freq_update()
+	 * for more details
+	 */
+	if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
+		set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
+}
+
+/*
+ * TODO: frequency notify handling should be hooked up to
+ * clock framework as soon as the necessary support is
+ * available in mainline kernel. This function is un-used
+ * right now.
+ */
+static void __attribute__((unused)) freq_post_notify_handling(void)
+{
+	struct emif_data *emif;
+
+	list_for_each_entry(emif, &device_list, node)
+		do_freq_post_notify_handling(emif);
+
+	/*
+	 * Lock is done in pre-notify handler. See freq_pre_notify_handling()
+	 * for more details
+	 */
+	spin_unlock_irqrestore(&emif_lock, irq_state);
+}
+
 static struct platform_driver emif_driver = {
 	.driver = {
 		.name = "emif",
diff --git a/drivers/misc/emif.h b/drivers/misc/emif.h
index 692b2a8..bfe08ba 100644
--- a/drivers/misc/emif.h
+++ b/drivers/misc/emif.h
@@ -19,6 +19,103 @@
  */
 #define EMIF_MAX_NUM_FREQUENCIES			6
 
+/* State of the core voltage */
+#define DDR_VOLTAGE_STABLE				0
+#define DDR_VOLTAGE_RAMPING				1
+
+/* Defines for timing De-rating */
+#define EMIF_NORMAL_TIMINGS				0
+#define EMIF_DERATED_TIMINGS				1
+
+/* Length of the forced read idle period in terms of cycles */
+#define EMIF_READ_IDLE_LEN_VAL				5
+
+/*
+ * forced read idle interval to be used when voltage
+ * is changed as part of DVFS/DPS - 1ms
+ */
+#define READ_IDLE_INTERVAL_DVFS				(1*1000000)
+
+/*
+ * Forced read idle interval to be used when voltage is stable
+ * 50us - or maximum value will do
+ */
+#define READ_IDLE_INTERVAL_NORMAL			(50*1000000)
+
+/* DLL calibration interval when voltage is NOT stable - 1us */
+#define DLL_CALIB_INTERVAL_DVFS				(1*1000000)
+
+#define DLL_CALIB_ACK_WAIT_VAL				5
+
+/* Interval between ZQCS commands - hw team recommended value */
+#define EMIF_ZQCS_INTERVAL_US				(50*1000)
+/* Enable ZQ Calibration on exiting Self-refresh */
+#define ZQ_SFEXITEN_ENABLE				1
+/*
+ * ZQ Calibration simultaneously on both chip-selects:
+ * Needs one calibration resistor per CS
+ */
+#define	ZQ_DUALCALEN_DISABLE				0
+#define	ZQ_DUALCALEN_ENABLE				1
+
+#define T_ZQCS_DEFAULT_NS				90
+#define T_ZQCL_DEFAULT_NS				360
+#define T_ZQINIT_DEFAULT_NS				1000
+
+/* DPD_EN */
+#define DPD_DISABLE					0
+#define DPD_ENABLE					1
+
+/*
+ * Default values for the low-power entry to be used if not provided by user.
+ * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512
+ * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz
+ */
+#define EMIF_LP_MODE_TIMEOUT_PERFORMANCE		2048
+#define EMIF_LP_MODE_TIMEOUT_POWER			512
+#define EMIF_LP_MODE_FREQ_THRESHOLD			400000000
+
+/* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY		0x049FF000
+#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY	0x41
+#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY	0x80
+#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF
+
+/* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY		0x0E084200
+#define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS	10000
+
+/* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */
+#define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS		360
+
+#define EMIF_T_CSTA					3
+#define EMIF_T_PDLL_UL					128
+
+/* External PHY control registers magic values */
+#define EMIF_EXT_PHY_CTRL_1_VAL				0x04020080
+#define EMIF_EXT_PHY_CTRL_5_VAL				0x04010040
+#define EMIF_EXT_PHY_CTRL_6_VAL				0x01004010
+#define EMIF_EXT_PHY_CTRL_7_VAL				0x00001004
+#define EMIF_EXT_PHY_CTRL_8_VAL				0x04010040
+#define EMIF_EXT_PHY_CTRL_9_VAL				0x01004010
+#define EMIF_EXT_PHY_CTRL_10_VAL			0x00001004
+#define EMIF_EXT_PHY_CTRL_11_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_12_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_13_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_14_VAL			0x80080080
+#define EMIF_EXT_PHY_CTRL_15_VAL			0x00800800
+#define EMIF_EXT_PHY_CTRL_16_VAL			0x08102040
+#define EMIF_EXT_PHY_CTRL_17_VAL			0x00000001
+#define EMIF_EXT_PHY_CTRL_18_VAL			0x540A8150
+#define EMIF_EXT_PHY_CTRL_19_VAL			0xA81502A0
+#define EMIF_EXT_PHY_CTRL_20_VAL			0x002A0540
+#define EMIF_EXT_PHY_CTRL_21_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_22_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_23_VAL			0x00000000
+#define EMIF_EXT_PHY_CTRL_24_VAL			0x00000077
+
+#define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS	1200
+
 /* Registers offset */
 #define EMIF_MODULE_ID_AND_REVISION			0x0000
 #define EMIF_STATUS					0x0004
@@ -458,4 +555,35 @@
 #define READ_LATENCY_SHDW_SHIFT				0
 #define READ_LATENCY_SHDW_MASK				(0x1f << 0)
 
-#endif
+#ifndef __ASSEMBLY__
+/*
+ * Structure containing shadow of important registers in EMIF
+ * The calculation function fills in this structure to be later used for
+ * initialisation and DVFS
+ */
+struct emif_regs {
+	u32 freq;
+	u32 ref_ctrl_shdw;
+	u32 ref_ctrl_shdw_derated;
+	u32 sdram_tim1_shdw;
+	u32 sdram_tim1_shdw_derated;
+	u32 sdram_tim2_shdw;
+	u32 sdram_tim3_shdw;
+	u32 sdram_tim3_shdw_derated;
+	u32 pwr_mgmt_ctrl_shdw;
+	union {
+		u32 read_idle_ctrl_shdw_normal;
+		u32 dll_calib_ctrl_shdw_normal;
+	};
+	union {
+		u32 read_idle_ctrl_shdw_volt_ramp;
+		u32 dll_calib_ctrl_shdw_volt_ramp;
+	};
+
+	u32 phy_ctrl_1_shdw;
+	u32 ext_phy_ctrl_2_shdw;
+	u32 ext_phy_ctrl_3_shdw;
+	u32 ext_phy_ctrl_4_shdw;
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __EMIF_H */
-- 
1.7.1



From aneesh at ti.com  Fri Mar 16 17:51:45 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 03:21:45 +0530
Subject: [PATCH v4 5/7] misc: emif: add interrupt and temperature handling
In-Reply-To: <1331934707-29487-1-git-send-email-aneesh@ti.com>
References: <1331934707-29487-1-git-send-email-aneesh@ti.com>
Message-ID: <1331934707-29487-6-git-send-email-aneesh@ti.com>

Add an ISR for EMIF that:
	1. reports details of access errors
	2. takes action on thermal events

Also clear all interrupts on shut-down. Pending IRQs
may casue problems during warm-reset.

Temperature handling:
EMIF can be configured to poll the temperature level
of an LPDDR2 device from the MR4 mode register in the
device. EMIF generates an interrupt whenever it identifies
a temperature level change between two consecutive pollings.

Some of the timing parameters need to be de-rated at high
temperatures. The interrupt handler takes care of doing
this and also takes care of going back to nominal settings
when temperature falls back to nominal levels.

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---

v2:
- replaced __init with __init_or_module

v1:
- Improved commit log
- Improved synchronization with thread context
---
 drivers/misc/emif.c |  211 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 209 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index 1ca8165..52048f4 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
@@ -545,6 +545,42 @@ static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
 }
 
 /*
+ * Get the temperature level of the EMIF instance:
+ * Reads the MR4 register of attached SDRAM parts to find out the temperature
+ * level. If there are two parts attached(one on each CS), then the temperature
+ * level for the EMIF instance is the higher of the two temperatures.
+ */
+static void get_temperature_level(struct emif_data *emif)
+{
+	u32		temp, temperature_level;
+	void __iomem	*base;
+
+	base = emif->base;
+
+	/* Read mode register 4 */
+	writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
+	temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
+	temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
+				MR4_SDRAM_REF_RATE_SHIFT;
+
+	if (emif->plat_data->device_info->cs1_used) {
+		writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
+		temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
+		temp = (temp & MR4_SDRAM_REF_RATE_MASK)
+				>> MR4_SDRAM_REF_RATE_SHIFT;
+		temperature_level = max(temp, temperature_level);
+	}
+
+	/* treat everything less than nominal(3) in MR4 as nominal */
+	if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
+		temperature_level = SDRAM_TEMP_NOMINAL;
+
+	/* if we get reserved value in MR4 persist with the existing value */
+	if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
+		emif->temperature_level = temperature_level;
+}
+
+/*
  * Program EMIF shadow registers that are not dependent on temperature
  * or voltage
  */
@@ -627,6 +663,158 @@ out:
 	writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
 }
 
+static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
+{
+	u32		old_temp_level;
+	irqreturn_t	ret = IRQ_HANDLED;
+
+	spin_lock_irqsave(&emif_lock, irq_state);
+	old_temp_level = emif->temperature_level;
+	get_temperature_level(emif);
+
+	if (unlikely(emif->temperature_level == old_temp_level)) {
+		goto out;
+	} else if (!emif->curr_regs) {
+		dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
+		goto out;
+	}
+
+	if (emif->temperature_level < old_temp_level ||
+		emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
+		/*
+		 * Temperature coming down - defer handling to thread OR
+		 * Temperature far too high - do kernel_power_off() from
+		 * thread context
+		 */
+		ret = IRQ_WAKE_THREAD;
+	} else {
+		/* Temperature is going up - handle immediately */
+		setup_temperature_sensitive_regs(emif, emif->curr_regs);
+		do_freq_update();
+	}
+
+out:
+	spin_unlock_irqrestore(&emif_lock, irq_state);
+	return ret;
+}
+
+static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
+{
+	u32			interrupts;
+	struct emif_data	*emif = dev_id;
+	void __iomem		*base = emif->base;
+	struct device		*dev = emif->dev;
+	irqreturn_t		ret = IRQ_HANDLED;
+
+	/* Save the status and clear it */
+	interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
+	writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
+
+	/*
+	 * Handle temperature alert
+	 * Temperature alert should be same for all ports
+	 * So, it's enough to process it only for one of the ports
+	 */
+	if (interrupts & TA_SYS_MASK)
+		ret = handle_temp_alert(base, emif);
+
+	if (interrupts & ERR_SYS_MASK)
+		dev_err(dev, "Access error from SYS port - %x\n", interrupts);
+
+	if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
+		/* Save the status and clear it */
+		interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
+		writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
+
+		if (interrupts & ERR_LL_MASK)
+			dev_err(dev, "Access error from LL port - %x\n",
+				interrupts);
+	}
+
+	return ret;
+}
+
+static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
+{
+	struct emif_data	*emif = dev_id;
+
+	if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
+		dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
+		kernel_power_off();
+		return IRQ_HANDLED;
+	}
+
+	spin_lock_irqsave(&emif_lock, irq_state);
+
+	if (emif->curr_regs) {
+		setup_temperature_sensitive_regs(emif, emif->curr_regs);
+		do_freq_update();
+	} else {
+		dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
+	}
+
+	spin_unlock_irqrestore(&emif_lock, irq_state);
+
+	return IRQ_HANDLED;
+}
+
+static void clear_all_interrupts(struct emif_data *emif)
+{
+	void __iomem	*base = emif->base;
+
+	writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
+		base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
+	if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
+		writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
+			base + EMIF_LL_OCP_INTERRUPT_STATUS);
+}
+
+static void disable_and_clear_all_interrupts(struct emif_data *emif)
+{
+	void __iomem		*base = emif->base;
+
+	/* Disable all interrupts */
+	writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
+		base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
+	if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
+		writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
+			base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
+
+	/* Clear all interrupts */
+	clear_all_interrupts(emif);
+}
+
+static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
+{
+	u32		interrupts, type;
+	void __iomem	*base = emif->base;
+
+	type = emif->plat_data->device_info->type;
+
+	clear_all_interrupts(emif);
+
+	/* Enable interrupts for SYS interface */
+	interrupts = EN_ERR_SYS_MASK;
+	if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
+		interrupts |= EN_TA_SYS_MASK;
+	writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
+
+	/* Enable interrupts for LL interface */
+	if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
+		/* TA need not be enabled for LL */
+		interrupts = EN_ERR_LL_MASK;
+		writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
+	}
+
+	/* setup IRQ handlers */
+	return devm_request_threaded_irq(emif->dev, irq,
+				    emif_interrupt_handler,
+				    emif_threaded_isr,
+				    0, dev_name(emif->dev),
+				    emif);
+
+}
+
 static void get_default_timings(struct emif_data *emif)
 {
 	struct emif_platform_data *pd = emif->plat_data;
@@ -803,6 +991,7 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 {
 	struct emif_data	*emif;
 	struct resource		*res;
+	int			irq;
 
 	emif = get_device_details(pdev);
 	if (!emif) {
@@ -831,6 +1020,16 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 		goto error;
 	}
 
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(emif->dev, "%s: error getting IRQ resource - %d\n",
+			__func__, irq);
+		goto error;
+	}
+
+	disable_and_clear_all_interrupts(emif);
+	setup_interrupts(emif, irq);
+
 	/* One-time actions taken on probing the first device */
 	if (!emif1) {
 		emif1 = emif;
@@ -843,14 +1042,21 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 		 */
 	}
 
-	dev_info(&pdev->dev, "%s: device configured with addr = %p\n",
-		__func__, emif->base);
+	dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
+		__func__, emif->base, irq);
 
 	return 0;
 error:
 	return -ENODEV;
 }
 
+static void emif_shutdown(struct platform_device *pdev)
+{
+	struct emif_data	*emif = platform_get_drvdata(pdev);
+
+	disable_and_clear_all_interrupts(emif);
+}
+
 static int get_emif_reg_values(struct emif_data *emif, u32 freq,
 		struct emif_regs *regs)
 {
@@ -1154,6 +1360,7 @@ static void __attribute__((unused)) freq_post_notify_handling(void)
 }
 
 static struct platform_driver emif_driver = {
+	.shutdown	= emif_shutdown,
 	.driver = {
 		.name = "emif",
 	},
-- 
1.7.1



From aneesh at ti.com  Fri Mar 16 17:51:46 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 03:21:46 +0530
Subject: [PATCH v4 6/7] misc: emif: add one-time settings
In-Reply-To: <1331934707-29487-1-git-send-email-aneesh@ti.com>
References: <1331934707-29487-1-git-send-email-aneesh@ti.com>
Message-ID: <1331934707-29487-7-git-send-email-aneesh@ti.com>

Add settings that are not dependent on frequency
or any other transient parameters. This includes
- power managment control init
- impedence calibration control
- frequency independent phy configuration registers
- initialization of temperature polling

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v2:
- replaced __init with __init_or_module
- fixed bug in the implementation of i728 errata workaround

v1:
- Improved commit log
- Changes for errata i728 workaround
---
 drivers/misc/emif.c |  148 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 148 insertions(+), 0 deletions(-)

diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index 52048f4..270a0e4 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
@@ -78,6 +78,24 @@ static void set_ddr_clk_period(u32 freq)
 }
 
 /*
+ * Get bus width used by EMIF. Note that this may be different from the
+ * bus width of the DDR devices used. For instance two 16-bit DDR devices
+ * may be connected to a given CS of EMIF. In this case bus width as far
+ * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
+ */
+static u32 get_emif_bus_width(struct emif_data *emif)
+{
+	u32		width;
+	void __iomem	*base = emif->base;
+
+	width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
+			>> NARROW_MODE_SHIFT;
+	width = width == 0 ? 32 : 16;
+
+	return width;
+}
+
+/*
  * Get the CL from SDRAM_CONFIG register
  */
 static u32 get_cl(struct emif_data *emif)
@@ -372,6 +390,70 @@ static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
 	return tim3;
 }
 
+static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
+		bool cs1_used, bool cal_resistors_per_cs)
+{
+	u32 zq = 0, val = 0;
+
+	val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
+	zq |= val << ZQ_REFINTERVAL_SHIFT;
+
+	val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
+	zq |= val << ZQ_ZQCL_MULT_SHIFT;
+
+	val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
+	zq |= val << ZQ_ZQINIT_MULT_SHIFT;
+
+	zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
+
+	if (cal_resistors_per_cs)
+		zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
+	else
+		zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
+
+	zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
+
+	val = cs1_used ? 1 : 0;
+	zq |= val << ZQ_CS1EN_SHIFT;
+
+	return zq;
+}
+
+static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
+		const struct emif_custom_configs *custom_configs, bool cs1_used,
+		u32 sdram_io_width, u32 emif_bus_width)
+{
+	u32 alert = 0, interval, devcnt;
+
+	if (custom_configs && (custom_configs->mask &
+				EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
+		interval = custom_configs->temp_alert_poll_interval_ms;
+	else
+		interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
+
+	interval *= 1000000;			/* Convert to ns */
+	interval /= addressing->tREFI_ns;	/* Convert to refresh cycles */
+	alert |= (interval << TA_REFINTERVAL_SHIFT);
+
+	/*
+	 * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
+	 * also to this form and subtract to get TA_DEVCNT, which is
+	 * in log2(x) form.
+	 */
+	emif_bus_width = __fls(emif_bus_width) - 1;
+	devcnt = emif_bus_width - sdram_io_width;
+	alert |= devcnt << TA_DEVCNT_SHIFT;
+
+	/* DEVWDT is in 'log2(x) - 3' form */
+	alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
+
+	alert |= 1 << TA_SFEXITEN_SHIFT;
+	alert |= 1 << TA_CS0EN_SHIFT;
+	alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
+
+	return alert;
+}
+
 static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
 {
 	u32 idle = 0, val = 0;
@@ -815,6 +897,71 @@ static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
 
 }
 
+static void __init_or_module emif_onetime_settings(struct emif_data *emif)
+{
+	u32				pwr_mgmt_ctrl, zq, temp_alert_cfg;
+	void __iomem			*base = emif->base;
+	const struct lpddr2_addressing	*addressing;
+	const struct ddr_device_info	*device_info;
+
+	device_info = emif->plat_data->device_info;
+	addressing = get_addressing_table(device_info);
+
+	/*
+	 * Init power management settings
+	 * We don't know the frequency yet. Use a high frequency
+	 * value for a conservative timeout setting
+	 */
+	pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
+			emif->plat_data->ip_rev);
+	emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
+	writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
+
+	/* Init ZQ calibration settings */
+	zq = get_zq_config_reg(addressing, device_info->cs1_used,
+		device_info->cal_resistors_per_cs);
+	writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
+
+	/* Check temperature level temperature level*/
+	get_temperature_level(emif);
+	if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
+		dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
+
+	/* Init temperature polling */
+	temp_alert_cfg = get_temp_alert_config(addressing,
+		emif->plat_data->custom_configs, device_info->cs1_used,
+		device_info->io_width, get_emif_bus_width(emif));
+	writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
+
+	/*
+	 * Program external PHY control registers that are not frequency
+	 * dependent
+	 */
+	if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
+		return;
+	writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
+	writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
+}
+
 static void get_default_timings(struct emif_data *emif)
 {
 	struct emif_platform_data *pd = emif->plat_data;
@@ -1027,6 +1174,7 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 		goto error;
 	}
 
+	emif_onetime_settings(emif);
 	disable_and_clear_all_interrupts(emif);
 	setup_interrupts(emif, irq);
 
-- 
1.7.1



From aneesh at ti.com  Fri Mar 16 17:51:47 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 03:21:47 +0530
Subject: [PATCH v4 7/7] misc: emif: add debugfs entries for emif
In-Reply-To: <1331934707-29487-1-git-send-email-aneesh@ti.com>
References: <1331934707-29487-1-git-send-email-aneesh@ti.com>
Message-ID: <1331934707-29487-8-git-send-email-aneesh@ti.com>

Add debug entries for:
	1. calculated registers per frequency
	2. last polled value of MR4(temperature level
	   of LPDDR2 memory)

Cc: Greg KH <greg at kroah.com>
Signed-off-by: Aneesh V <aneesh at ti.com>
---
v2:
- Corrected the frequency value shown in
  register cache dump
- replaced __init with __init_or_module
---
 drivers/misc/emif.c |  138 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 138 insertions(+), 0 deletions(-)

diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
index 270a0e4..6d2f776 100644
--- a/drivers/misc/emif.c
+++ b/drivers/misc/emif.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
+#include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/module.h>
 #include <linux/list.h>
@@ -47,6 +48,7 @@
  *				frequency change (i.e. corresponding to the
  *				frequency in effect at the moment)
  * @plat_data:			Pointer to saved platform data.
+ * @debugfs_root:		dentry to the root folder for EMIF in debugfs
  */
 struct emif_data {
 	u8				duplicate;
@@ -60,6 +62,7 @@ struct emif_data {
 	struct emif_regs		*regs_cache[EMIF_MAX_NUM_FREQUENCIES];
 	struct emif_regs		*curr_regs;
 	struct emif_platform_data	*plat_data;
+	struct dentry			*debugfs_root;
 };
 
 static struct emif_data *emif1;
@@ -68,6 +71,130 @@ static unsigned long	irq_state;
 static u32		t_ck; /* DDR clock period in ps */
 static LIST_HEAD(device_list);
 
+static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
+	struct emif_regs *regs)
+{
+	u32 type = emif->plat_data->device_info->type;
+	u32 ip_rev = emif->plat_data->ip_rev;
+
+	seq_printf(s, "EMIF register cache dump for %dMHz\n",
+		regs->freq/1000000);
+
+	seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
+	seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
+	seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
+	seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
+
+	if (ip_rev == EMIF_4D) {
+		seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
+			regs->read_idle_ctrl_shdw_normal);
+		seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
+			regs->read_idle_ctrl_shdw_volt_ramp);
+	} else if (ip_rev == EMIF_4D5) {
+		seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
+			regs->dll_calib_ctrl_shdw_normal);
+		seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
+			regs->dll_calib_ctrl_shdw_volt_ramp);
+	}
+
+	if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
+		seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
+			regs->ref_ctrl_shdw_derated);
+		seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
+			regs->sdram_tim1_shdw_derated);
+		seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
+			regs->sdram_tim3_shdw_derated);
+	}
+}
+
+static int emif_regdump_show(struct seq_file *s, void *unused)
+{
+	struct emif_data	*emif	= s->private;
+	struct emif_regs	**regs_cache;
+	int			i;
+
+	if (emif->duplicate)
+		regs_cache = emif1->regs_cache;
+	else
+		regs_cache = emif->regs_cache;
+
+	for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
+		do_emif_regdump_show(s, emif, regs_cache[i]);
+		seq_printf(s, "\n");
+	}
+
+	return 0;
+}
+
+static int emif_regdump_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, emif_regdump_show, inode->i_private);
+}
+
+static const struct file_operations emif_regdump_fops = {
+	.open			= emif_regdump_open,
+	.read			= seq_read,
+	.release		= single_release,
+};
+
+static int emif_mr4_show(struct seq_file *s, void *unused)
+{
+	struct emif_data *emif = s->private;
+
+	seq_printf(s, "MR4=%d\n", emif->temperature_level);
+	return 0;
+}
+
+static int emif_mr4_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, emif_mr4_show, inode->i_private);
+}
+
+static const struct file_operations emif_mr4_fops = {
+	.open			= emif_mr4_open,
+	.read			= seq_read,
+	.release		= single_release,
+};
+
+static int __init_or_module emif_debugfs_init(struct emif_data *emif)
+{
+	struct dentry	*dentry;
+	int		ret;
+
+	dentry = debugfs_create_dir(dev_name(emif->dev), NULL);
+	if (IS_ERR(dentry)) {
+		ret = PTR_ERR(dentry);
+		goto err0;
+	}
+	emif->debugfs_root = dentry;
+
+	dentry = debugfs_create_file("regcache_dump", S_IRUGO,
+			emif->debugfs_root, emif, &emif_regdump_fops);
+	if (IS_ERR(dentry)) {
+		ret = PTR_ERR(dentry);
+		goto err1;
+	}
+
+	dentry = debugfs_create_file("mr4", S_IRUGO,
+			emif->debugfs_root, emif, &emif_mr4_fops);
+	if (IS_ERR(dentry)) {
+		ret = PTR_ERR(dentry);
+		goto err1;
+	}
+
+	return 0;
+err1:
+	debugfs_remove_recursive(emif->debugfs_root);
+err0:
+	return ret;
+}
+
+static void __exit emif_debugfs_exit(struct emif_data *emif)
+{
+	debugfs_remove_recursive(emif->debugfs_root);
+	emif->debugfs_root = NULL;
+}
+
 /*
  * Calculate the period of DDR clock from frequency value
  */
@@ -1175,6 +1302,7 @@ static int __init_or_module emif_probe(struct platform_device *pdev)
 	}
 
 	emif_onetime_settings(emif);
+	emif_debugfs_init(emif);
 	disable_and_clear_all_interrupts(emif);
 	setup_interrupts(emif, irq);
 
@@ -1198,6 +1326,15 @@ error:
 	return -ENODEV;
 }
 
+static int __exit emif_remove(struct platform_device *pdev)
+{
+	struct emif_data *emif = platform_get_drvdata(pdev);
+
+	emif_debugfs_exit(emif);
+
+	return 0;
+}
+
 static void emif_shutdown(struct platform_device *pdev)
 {
 	struct emif_data	*emif = platform_get_drvdata(pdev);
@@ -1508,6 +1645,7 @@ static void __attribute__((unused)) freq_post_notify_handling(void)
 }
 
 static struct platform_driver emif_driver = {
+	.remove		= __exit_p(emif_remove),
 	.shutdown	= emif_shutdown,
 	.driver = {
 		.name = "emif",
-- 
1.7.1



From aneesh at ti.com  Fri Mar 16 17:53:50 2012
From: aneesh at ti.com (Aneesh V)
Date: Sat, 17 Mar 2012 03:23:50 +0530
Subject: [PATCH v2 1/7] misc: ddr: add LPDDR2 data from JESD209-2
In-Reply-To: <20120316213316.GC24556@kroah.com>
References: <1331835457-5390-1-git-send-email-aneesh@ti.com>
 <1331835457-5390-2-git-send-email-aneesh@ti.com>
 <20120315190238.GD11142@kroah.com> <4F63A987.3@ti.com>
 <20120316213316.GC24556@kroah.com>
Message-ID: <4F63B66E.3000200@ti.com>

On Saturday 17 March 2012 03:03 AM, Greg KH wrote:
> On Sat, Mar 17, 2012 at 02:28:47AM +0530, Aneesh V wrote:
>> Hi Greg,

[...]

>> I have fixed these comments and pushed my latest patches at:
>> git://github.com/aneeshv/linux.git
>> branch: emif-upstream-v4
>
> Sorry, but I don't take git pulls for stuff like this, please send all
> of the patches in email so it can be reviewed properly.
>

I had sent the updated version of the affected patch. Anyway, I will
send the whole series again.

thanks,
Aneesh


From mturquette at ti.com  Fri Mar 16 18:03:54 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 16 Mar 2012 15:03:54 -0700
Subject: [RFC/PATCH 4/4] pxa: convert to common clock framework
In-Reply-To: <1331919483.31118.23.camel@flow>
References: <1331919483.31118.23.camel@flow>
Message-ID: <CAJOA=zN2dxgjQ8EZYAwE=OLO1GLdArqy1Xf18F82en9QvFi4cw@mail.gmail.com>

On Fri, Mar 16, 2012 at 10:38 AM, Philipp Zabel <philipp.zabel at gmail.com> wrote:
> ?#define DEFINE_CK(_name, _cken, _ops) ? ? ? ? ? ? ? ? ?\
> -struct clk clk_##_name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .ops ? ?= _ops, ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? struct clk clk_##_name; ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? static struct clk_pxa clk_pxa_##_name = { ? ? ? \
> + ? ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? .clk = &clk_##_name, ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?.cken ? = CKEN_##_cken, ? ? ? ? ? ? ? ? \
> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk clk_##_name = { ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .name ? = #_name, ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .ops ? ?= _ops, ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .hw ? ? = &clk_pxa_##_name.hw, ? ? ? ? ?\
> ? ? ? ?}

Hi Philipp,

It looks like your macros do not initialize the .parent_names,
.num_parents or .flags members of struct clk.  __clk_init expects
those to be initialized before being called.  The kerneldoc for
__clk_init states this:
http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=e2cce6fa604686ea3bca0496998322bacaed854d;hb=c5836d8acd9846ec1675b269d994d96a8ee44df4#l49

You can use the macros for the basic clocks types as templates.  The
gate and mux macros are good to look at since those show how to handle
a single-parent and multi-parent clock, respectively:
http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=5e4312b6f5ccb1072273ce94e235874c74dd852d;hb=2508b44cd5c134691dc5d679f728bbf82af2abe0#l83
and
http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=5e4312b6f5ccb1072273ce94e235874c74dd852d;hb=2508b44cd5c134691dc5d679f728bbf82af2abe0#l148

>
> ?#define DEFINE_CLK(_name, _ops, _rate, _delay) ? ? ? ? \
> -struct clk clk_##_name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .ops ? ?= _ops, ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .rate ? = _rate, ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? struct clk clk_##_name; ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? static struct clk_pxa clk_pxa_##_name = { ? ? ? \
> + ? ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? .clk = &clk_##_name, ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?.delay ?= _delay, ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .rate ? = _rate, ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk clk_##_name = { ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .name ? = #_name, ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .ops ? ?= _ops, ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .hw ? ? = &clk_pxa_##_name.hw, ? ? ? ? ?\
> ? ? ? ?}

ditto

>
> ?#define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay) ?\
> -struct clk clk_##_name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? .ops ? ?= &clk_pxa2xx_cken_ops, ? ? ? ? \
> - ? ? ? ? ? ? ? .rate ? = _rate, ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? struct clk clk_##_name; ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? static struct clk_pxa clk_pxa_##_name = { ? ? ? \
> + ? ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? ? ? ? ? .clk = &clk_##_name, ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?.cken ? = CKEN_##_cken, ? ? ? ? ? ? ? ? \
> ? ? ? ? ? ? ? ?.delay ?= _delay, ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .rate ? = _rate, ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? static struct clk clk_##_name = { ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .name ? = #_name, ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? .ops ? ?= &clk_pxa2xx_cken_ops, ? ? ? ? \
> + ? ? ? ? ? ? ? .hw ? ? = &clk_pxa_##_name.hw, ? ? ? ? ?\
> ? ? ? ?}

ditto

Regards,
Mike

From mturquette at ti.com  Fri Mar 16 18:07:44 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 16 Mar 2012 15:07:44 -0700
Subject: [RFC/PATCH 0/4] pxa: attempt at switch to common clock framework
In-Reply-To: <1331919343.31118.19.camel@flow>
References: <1331919343.31118.19.camel@flow>
Message-ID: <CAJOA=zPkTy=MqiGkuLsdGE_bLMVEipRh291EaP3BV-yHWbxFRA@mail.gmail.com>

On Fri, Mar 16, 2012 at 10:35 AM, Philipp Zabel <philipp.zabel at gmail.com> wrote:
> Hi,
>
> I have made an attempt at an initial conversion of PXA clocks to the
> common clock framework (http://lkml.org/lkml/2012/3/16/25), and I'd
> like to know if somebody is already working on this, or if I am
> heading in the general right direction.
>
> Unfortunately, this set still hangs during boot on hx4700 (pxa270),
> unless I also disable the calls to __clk_lookup in drivers/clk/clk.c
> completely (or apply the patch below). I'll investigate once I get
> access to my serial cable and hx4700 charger, but I'd be grateful if
> somebody could spot any embarassingly obvious errors.

I responded with details for your patch #4.  Looks like the macros are
missing a bit of initialization data.  Definitely not an embarrassing
error!  Those macros are not small.  It does show yet one more reason
why it would be good to get rid of the static initialization code at
some point in the future.

Regards,
Mike

> For pxa25x and pxa3xx, it's compile-tested only.
>
> regards
> Philipp
>
> ---
> ?drivers/clk/clk.c | ? ?8 +++++---
> ?1 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index c7c3bc5..79b46af 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -336,14 +336,15 @@ static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
> ? ? ? ?struct hlist_node *tmp;
>
> ? ? ? ?if (!strcmp(clk->name, name))
> - ? ? ? ? ? ? ? return clk;
> + ? ? ? ? ? ? ? return NULL;
>
> +#if 0
> ? ? ? ?hlist_for_each_entry(child, tmp, &clk->children, child_node) {
> ? ? ? ? ? ? ? ?ret = __clk_lookup_subtree(name, child);
> ? ? ? ? ? ? ? ?if (ret)
> ? ? ? ? ? ? ? ? ? ? ? ?return ret;
> ? ? ? ?}
> -
> +#endif
> ? ? ? ?return NULL;
> ?}
>
> --
> 1.7.9.1
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From paul at pwsan.com  Fri Mar 16 18:21:17 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Fri, 16 Mar 2012 16:21:17 -0600 (MDT)
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <201203162057.58706.arnd@arndb.de>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
Message-ID: <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>

Hi

On Fri, 16 Mar 2012, Arnd Bergmann wrote:

> On Friday 16 March 2012, Arnd Bergmann wrote:
> > > 
> > > Can we shoe-horn this thing into 3.4 (it is a bit late, i know) so
> > > that platform ports can gather speed? Several people are waiting for a
> > > somewhat stable version before starting their ports.
> > > 
> > > And what is the path into mainline - will Russell carry it or Arnd
> > > (with Russell's blessing)?
> > 
> > I would suggest putting it into a late/* branch of arm-soc so it finally
> > gets some linux-next exposure, and then sending it in the second week of the
> > merge window.
> > 
> > Russell, please let me know if you want to carry it instead or if you
> > have found any last-minute show stoppers in the code.
> 
> FWIW, it's in arm-soc now [...]

If the common clock code is to go upstream now, it should be marked as 
experimental.  This is because we know the API is not well-defined, and 
that both the API and the underlying mechanics will almost certainly need 
to change for non-trivial uses of the rate changing code (e.g., DVFS with 
external I/O devices).

While I understand and accept the motivation to get the common clk code 
upstream now, if platforms start to use it, they need to be aware that the 
behavior of the code can change significantly.  These platforms may need 
to revalidate their implementations or change the way that many of their 
drivers use the clock functions.

It also seems important to recognize that significant changes are still 
coming into the common clk code (e.g., the clk_set_rate() changes that 
came in just a few days ago).

So, the following is a patch to mark it as experimental.  It applies on 
the current head of arm-soc/next/clk 
(9d9f78ed9af0e465d2fd15550471956e7f559b9f).  This should be a good 
compromise: it allows simple platforms or platforms with maintainers with 
lots of time to start converting over to the common clk code, while still 
clearly indicating that the API and underlying code is likely to change in 
significant ways.

Once at least two major SoC ports have DVFS with external I/O devices 
safely up and running on their mainline kernels with the common clk code, 
I'd suggest removing the experimental designation.

...

None of this is meant to reflect on Mike, by the way, who is doing a good 
job in a difficult situation.

 
- Paul

From: Paul Walmsley <paul at pwsan.com>
Date: Fri, 16 Mar 2012 16:06:30 -0600
Subject: [PATCH] clk: mark the common clk code as EXPERIMENTAL for now

Mark the common clk code as depending on CONFIG_EXPERIMENTAL.  The API
is not well-defined and both it and the underlying mechanics are likely
to need significant changes to support non-trivial uses of the rate
changing code, such as DVFS with external I/O devices.  So any platforms
that switch their implementation over to this may need to revise much
of their driver code and revalidate their implementations until the
behavior of the code is better-defined.

A good time for removing this EXPERIMENTAL designation would be after at
least two platforms that do DVFS on groups of external I/O devices have
ported their clock implementations over to the common clk code.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Mike Turquette <mturquette at ti.com>
---
 drivers/clk/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 2eaf17e..a0a83de 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -12,6 +12,7 @@ config HAVE_MACH_CLKDEV
 menuconfig COMMON_CLK
 	bool "Common Clock Framework"
 	select HAVE_CLK_PREPARE
+	depends on EXPERIMENTAL
 	---help---
 	  The common clock framework is a single definition of struct
 	  clk, useful across many platforms, as well as an
-- 
1.7.9.1



From mturquette at ti.com  Fri Mar 16 18:33:04 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 16 Mar 2012 15:33:04 -0700
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
Message-ID: <CAJOA=zPmy7Dwzw8EOCW_+cvy2Dv=w0TPUq7Zg_s=Y0rs+v+u2w@mail.gmail.com>

On Fri, Mar 16, 2012 at 3:21 PM, Paul Walmsley <paul at pwsan.com> wrote:
> From: Paul Walmsley <paul at pwsan.com>
> Date: Fri, 16 Mar 2012 16:06:30 -0600
> Subject: [PATCH] clk: mark the common clk code as EXPERIMENTAL for now
>
> Mark the common clk code as depending on CONFIG_EXPERIMENTAL. ?The API
> is not well-defined and both it and the underlying mechanics are likely
> to need significant changes to support non-trivial uses of the rate
> changing code, such as DVFS with external I/O devices. ?So any platforms
> that switch their implementation over to this may need to revise much
> of their driver code and revalidate their implementations until the
> behavior of the code is better-defined.
>
> A good time for removing this EXPERIMENTAL designation would be after at
> least two platforms that do DVFS on groups of external I/O devices have
> ported their clock implementations over to the common clk code.
>
> Signed-off-by: Paul Walmsley <paul at pwsan.com>
> Cc: Mike Turquette <mturquette at ti.com>

ACK.  This will set some reasonable expectations while things are in flux.

Arnd are you willing to take this in?

Thanks,
Mike

> ---
> ?drivers/clk/Kconfig | ? ?1 +
> ?1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 2eaf17e..a0a83de 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -12,6 +12,7 @@ config HAVE_MACH_CLKDEV
> ?menuconfig COMMON_CLK
> ? ? ? ?bool "Common Clock Framework"
> ? ? ? ?select HAVE_CLK_PREPARE
> + ? ? ? depends on EXPERIMENTAL
> ? ? ? ?---help---
> ? ? ? ? ?The common clock framework is a single definition of struct
> ? ? ? ? ?clk, useful across many platforms, as well as an
> --
> 1.7.9.1
>


From festevam at gmail.com  Fri Mar 16 19:13:13 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 16 Mar 2012 20:13:13 -0300
Subject: Want to Get Suggestion for MX28 USB Submisson
In-Reply-To: <F281D0F91ED19E4D8E63A7504E8A6498093839@039-SN2MPN1-021.039d.mgd.msft.net>
References: <35AB98346D25394A9354ED89C4D76587225CFF@039-SN1MPN1-002.039d.mgd.msft.net>
 <201202041117.48190.marek.vasut@gmail.com>
 <F281D0F91ED19E4D8E63A7504E8A6498033336@039-SN2MPN1-021.039d.mgd.msft.net>
 <201202100447.14248.marek.vasut@gmail.com>
 <CAOMZO5C3Y3kP5k_CKkCVMVdDem2T82g6F3uL=8GCVfNKHpdymA@mail.gmail.com>
 <F281D0F91ED19E4D8E63A7504E8A6498093839@039-SN2MPN1-021.039d.mgd.msft.net>
Message-ID: <CAOMZO5A1D8SLp=UpFK0dfjaaeJK+R4yUjXbRm=xhOjfEPdzEtA@mail.gmail.com>

Hi Peter,

On Wed, Mar 14, 2012 at 12:30 AM, Chen Peter-B29397
<B29397 at freescale.com> wrote:

> According to sascha's suggestion, it is better to re-submit after we have
> a generic USB PHY Layer in mainline.
>
> Currently, Heikki's split PHY from OTG structure patches have mainlined,
> next step is to submit a generic USB PHY driver.

Just for my understanding: is there someone working on this generic
USB PHY driver?


From s.hauer at pengutronix.de  Fri Mar 16 19:47:06 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat, 17 Mar 2012 00:47:06 +0100
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
Message-ID: <20120316234706.GJ3852@pengutronix.de>

Hi Paul,

On Fri, Mar 16, 2012 at 04:21:17PM -0600, Paul Walmsley wrote:
> Hi
> 
> On Fri, 16 Mar 2012, Arnd Bergmann wrote:
> 
> 
> If the common clock code is to go upstream now, it should be marked as 
> experimental.

No, please don't do this. This effectively marks the architectures using
the generic clock framework experimental. We can mark drivers as 'you
have been warned', but marking an architecture as experimental is the
wrong sign for both its users and people willing to adopt the framework.
Also we get this:

warning: (ARCH_MX1 && MACH_MX21 && ARCH_MX25 && MACH_MX27) selects COMMON_CLK which has unmet direct dependencies (EXPERIMENTAL)

(and no, I don't want to support to clock frameworks in parallel)

> This is because we know the API is not well-defined, and 
> that both the API and the underlying mechanics will almost certainly need 
> to change for non-trivial uses of the rate changing code (e.g., DVFS with 
> external I/O devices).

Please leave DVFS out of the game. DVFS will use the clock framework for
the F part and the regulator framework for the V part, but the clock
framework should not get extended with DVFS features. The notifiers we
currently have in the clock framework should give enough information
for DVFS implementations. Even if they don't and we have to change
something here this will have no influence on the architectures
implementing their clock tree with the common clock framework.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From bhelgaas at google.com  Fri Mar 16 19:48:04 2012
From: bhelgaas at google.com (Bjorn Helgaas)
Date: Fri, 16 Mar 2012 17:48:04 -0600
Subject: [PATCH v2 2/7] arm/PCI: don't export pci_flags
In-Reply-To: <20120316234653.6649.59492.stgit@bhelgaas.mtv.corp.google.com>
References: <20120316234653.6649.59492.stgit@bhelgaas.mtv.corp.google.com>
Message-ID: <20120316234804.6649.3554.stgit@bhelgaas.mtv.corp.google.com>

There's no need to export pci_flags; it's not exported by any other
architecture, and no modules reference it.

CC: Rob Herring <rob.herring at calxeda.com>
CC: Russell King <linux at arm.linux.org.uk>
CC: linux-arm-kernel at lists.infradead.org
Signed-off-by: Bjorn Helgaas <bhelgaas at google.com>
---
 arch/arm/kernel/bios32.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index be5d3b2..632df9a 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -498,7 +498,6 @@ void __init pci_common_init(struct hw_pci *hw)
 		pci_bus_add_devices(bus);
 	}
 }
-EXPORT_SYMBOL(pci_flags);
 
 #ifndef CONFIG_PCI_HOST_ITE8152
 void pcibios_set_master(struct pci_dev *dev)



From shawn.guo at linaro.org  Fri Mar 16 20:07:59 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 17 Mar 2012 08:07:59 +0800
Subject: [alsa-devel] [PATCH v5 8/8] ASoC: fsl: add imx-sgtl5000 machine
 driver
In-Reply-To: <CA+7tXih-omxaDq6dSKBeOaZ7YRWDVSQnMY=eJZ0-YumOBG=oCA@mail.gmail.com>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-9-git-send-email-shawn.guo@linaro.org>
 <CA+7tXihmfBQCgvuY0rx5v4w-bcwYK+7kP9v29w36N-Rc9KSQ+A@mail.gmail.com>
 <20120316111814.GA7860@S2101-09.ap.freescale.net>
 <20120316192110.GH3158@opensource.wolfsonmicro.com>
 <CA+7tXih-omxaDq6dSKBeOaZ7YRWDVSQnMY=eJZ0-YumOBG=oCA@mail.gmail.com>
Message-ID: <20120317000757.GB7860@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 05:28:54PM -0400, Trent Piepho wrote:
> On Fri, Mar 16, 2012 at 3:21 PM, Mark Brown
> <broonie at opensource.wolfsonmicro.com> wrote:
> > On Fri, Mar 16, 2012 at 07:18:18PM +0800, Shawn Guo wrote:
> >
> >> Maybe having "fsl,imx-audio-xxx" for machine drivers backed by SSI,
> >> and "fsl,imx-esai-audio-xxx" for the ones backed by ESAI?
> 
> It seems non-orthogonal to me that ESAI has esai in the name but SSI
> does not have ssi.
> 
SSI comes first and so takes the "default and shorter" name :)

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Fri Mar 16 20:18:14 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 17 Mar 2012 08:18:14 +0800
Subject: [GIT PULL] imx irq_domain migration
In-Reply-To: <20120316122243.GH7758@S2101-09.ap.freescale.net>
References: <20120216154941.GB11758@r65073-Latitude-D630>
 <4F3D41D2.5090203@gmail.com>
 <20120314050837.GB21337@S2101-09.ap.freescale.net>
 <4F6098C6.7050503@gmail.com>
 <CACxGe6tsHWj+bHcg1uEV8x-KE7B8p1Lj-_DL9mysYn1z+Bex3g@mail.gmail.com>
 <20120316122243.GH7758@S2101-09.ap.freescale.net>
Message-ID: <20120317001812.GI7758@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 08:22:46PM +0800, Shawn Guo wrote:
...
> Okay.  Since imx change has a dependency on Rob's change, I have to
> wait until Rob's change shows up on irqdomain/next.

It does not matter now.  Arnd announced that arm-soc tree has closed
for the coming merge window.  I will wait for v3.4-rc1 then.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Fri Mar 16 20:21:30 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 17 Mar 2012 08:21:30 +0800
Subject: [PATCH v5 2/8] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <4F63AEE7.4030505@freescale.com>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-3-git-send-email-shawn.guo@linaro.org>
 <4F63AEE7.4030505@freescale.com>
Message-ID: <20120317002128.GC7860@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 04:21:43PM -0500, Timur Tabi wrote:
> Shawn Guo wrote:
> > Freescale PowerPC and ARM/IMX families share the same SSI IP block.
> > The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
> > code sharing and consolidation can happen.
> > 
> > This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
> > in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
> > IMX platform.
> > 
> > Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> > Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> > ---
> 
> I'm okay with this patch, but you will need an Ack from Kumar Gala to
> carry the defconfig portions through the ASoC tree.  Or, he might want you
> to split the patch up.
> 
Splitting the patch up will introduce a dependency between PowerPC tree
and sound tree.  Since the change is trivial enough (one line change),
even if there is a merge conflict (very unlikely, just tried linux-next
and did not see), Linus will be able to handle it.  So I'd rather not
split.  What'd you say, Kumar?

> >  arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig |    1 +
> >  arch/powerpc/configs/mpc85xx_defconfig           |    1 +
> >  arch/powerpc/configs/mpc85xx_smp_defconfig       |    1 +

-- 
Regards,
Shawn


From robherring2 at gmail.com  Fri Mar 16 20:54:43 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 16 Mar 2012 19:54:43 -0500
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <20120316234706.GJ3852@pengutronix.de>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <20120316234706.GJ3852@pengutronix.de>
Message-ID: <4F63E0D3.3060106@gmail.com>

On 03/16/2012 06:47 PM, Sascha Hauer wrote:
> Hi Paul,
> 
> On Fri, Mar 16, 2012 at 04:21:17PM -0600, Paul Walmsley wrote:
>> Hi
>>
>> On Fri, 16 Mar 2012, Arnd Bergmann wrote:
>>
>>
>> If the common clock code is to go upstream now, it should be marked as 
>> experimental.
> 
> No, please don't do this. This effectively marks the architectures using
> the generic clock framework experimental. We can mark drivers as 'you
> have been warned', but marking an architecture as experimental is the
> wrong sign for both its users and people willing to adopt the framework.
> Also we get this:
> 
> warning: (ARCH_MX1 && MACH_MX21 && ARCH_MX25 && MACH_MX27) selects COMMON_CLK which has unmet direct dependencies (EXPERIMENTAL)
> 
> (and no, I don't want to support to clock frameworks in parallel)
> 

+1

For simple users at least, the api is perfectly adequate and it is not
experimental (unless new means experimental).

Rob

>> This is because we know the API is not well-defined, and 
>> that both the API and the underlying mechanics will almost certainly need 
>> to change for non-trivial uses of the rate changing code (e.g., DVFS with 
>> external I/O devices).
> 
> Please leave DVFS out of the game. DVFS will use the clock framework for
> the F part and the regulator framework for the V part, but the clock
> framework should not get extended with DVFS features. The notifiers we
> currently have in the clock framework should give enough information
> for DVFS implementations. Even if they don't and we have to change
> something here this will have no influence on the architectures
> implementing their clock tree with the common clock framework.
> 
> Sascha
> 



From skannan at codeaurora.org  Fri Mar 16 23:23:57 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Fri, 16 Mar 2012 20:23:57 -0700
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
References: <1330763341-3437-1-git-send-email-mturquette@linaro.org>
 <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
 <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
Message-ID: <4F6403CD.8020509@codeaurora.org>

On 03/07/2012 01:20 PM, Turquette, Mike wrote:
> On Tue, Mar 6, 2012 at 11:00 AM, Sascha Hauer<s.hauer at pengutronix.de>  wrote:
>> On Mon, Mar 05, 2012 at 12:03:15PM -0800, Turquette, Mike wrote:
>>> On Sun, Mar 4, 2012 at 11:38 PM, Sascha Hauer<s.hauer at pengutronix.de>  wrote:
>>>> On Sun, Mar 04, 2012 at 04:12:21PM -0800, Turquette, Mike wrote:
>>>>>>>
>>>>>>> I believe this patch already does what you suggest, but I might be
>>>>>>> missing your point.
>>>>>>
>>>>>> In include/linux/clk-private.h you expose struct clk outside the core.
>>>>>> This has to be done to make static initializers possible. There is a big
>>>>>> warning in this file that it must not be included from files implementing
>>>>>> struct clk_ops. You can simply avoid this warning by declaring struct clk
>>>>>> with only a single member:
>>>>>>
>>>>>> include/linux/clk.h:
>>>>>>
>>>>>> struct clk {
>>>>>>         struct clk_internal *internal;
>>>>>> };
>>>>>>
>>>>>> This way everybody knows struct clk (thus can embed it in their static
>>>>>> initializers), but doesn't know anything about the internal members. Now
>>>>>> in drivers/clk/clk.c you declare struct clk_internal exactly like struct
>>>>>> clk was declared before:
>>>>>>
>>>>>> struct clk_internal {
>>>>>>         const char              *name;
>>>>>>         const struct clk_ops    *ops;
>>>>>>         struct clk_hw           *hw;
>>>>>>         struct clk              *parent;
>>>>>>         char                    **parent_names;
>>>>>>         struct clk              **parents;
>>>>>>         u8                      num_parents;
>>>>>>         unsigned long           rate;
>>>>>>         unsigned long           flags;
>>>>>>         unsigned int            enable_count;
>>>>>>         unsigned int            prepare_count;
>>>>>>         struct hlist_head       children;
>>>>>>         struct hlist_node       child_node;
>>>>>>         unsigned int            notifier_count;
>>>>>> #ifdef CONFIG_COMMON_CLK_DEBUG
>>>>>>         struct dentry           *dentry;
>>>>>> #endif
>>>>>> };
>>>>>>
>>>>>> An instance of struct clk_internal will be allocated in
>>>>>> __clk_init/clk_register. Now the private data stays completely inside
>>>>>> the core and noone can abuse it.
>>>>>
>>>>> Hi Sascha,
>>>>>
>>>>> I see the disconnect here.  For OMAP (and possibly other platforms) at
>>>>> least some clock data is necessary during early boot, before the
>>>>> regular allocation methods are available (timers for instance).
>>>>
>>>> We had this problem on i.MX aswell. It turned out that the timer clock
>>>> is the only clock that is needed so early. We solved this by moving the
>>>> clock init to the system timer init function.
>>>
>>> When you say "mov[ed] the clock init to the system timer init
>>> function" do you mean that you statically allocated struct clk and
>>> used the clk framework api, or instead you just did some direct
>>> register writes to initialize things properly?
>>
>> I meant that on i.MX we do the clock tree initialization when kmalloc is
>> available, see the attached patch for omap4 based on your branch which
>> does the same for Omap. The first clock you need is the one for the
>> timer, so you can initialize the clocktree at the beginning of
>> time_init() and don't need statically initialized clocks anymore.
>>
>>>>
>>>> Well, the file is work in progress, you probably fix this before sending
>>>> it out, but I bet people will include clk-private.h and nobody else
>>>> notices it.
>>>
>>> clock44xx_data.c does not violate that rule.  None of the logic that
>>> implements ops for those clocks is present clock44xx_data.c.
>>
>> Indeed, I missed that. It only has the ops but not the individual
>> functions.
>>
>>> All of
>>> the code in that file is simply initialization and registration of
>>> OMAP4 clocks.  Many of the clocks are basic clock types (divider,
>>> multiplexer and fixed-rate are used in that file) with protected code
>>> drivers/clk/clk-*.c and the remaining clocks are of the struct
>>> clk_hw_omap variety, which has code spread across several files:
>>>
>>> arch/arm/mach-omap2/clock.c
>>> arch/arm/mach-omap2/clock.h
>>> arch/arm/mach-omap2/clkt_dpll.c
>>> arch/arm/mach-omap2/clkt_clksel.c
>>> arch/arm/mach-omap2/dpll3xxx.c
>>> arch/arm/mach-omap2/dpll4xxx.c
>>>
>>> All of the above files include linux/clk-provider.h, not
>>> linux/clk-private.h.  That code makes heavy use of the
>>> __clk_get_whatever helpers and shows how a platform might honor the
>>> layer of separation between struct clk and stuct clk_ops/struct
>>> clk_foo.  You are correct that the code is a work-in-progress, but
>>> there are no layering violations that I can see.
>>>
>>> I also think we are talking past each other to some degree.  One point
>>> I would like to make (and maybe you already know this from code
>>> review) is that it is unnecessary to have pointers to your parent
>>> struct clk*'s when either initializing or registering your clocks.  In
>>> fact the existing clk_register_foo functions don't even allow you to
>>> pass in parent pointers and rely wholly on string name matching.  I
>>> just wanted to point that out in case it went unnoticed, as it is a
>>> new way of doing things from the previous series and was born out of
>>> Thomas' review of V4 and multi-parent handling.  This also keeps
>>> device-tree in mind where we might not know the struct clk *pointer at
>>> compile time for "connecting" discrete devices.
>>
>> Yes, I've seen this and I really like it. Also the change that
>> multiplexers return an index to an array instead of the parent
>> clock is very nice.
>>
>> Sascha
>>
>>
>> 8<-----------------------------------------------------
>>
>> ARM omap4: move clocktree init to timer init time so we don't need static clocks
>>
>> Signed-off-by: Sascha Hauer<s.hauer at pengutronix.de>
>

Hi Mike,

I already took a quick look at the v7 series, but I thought this thread 
has more relevant context for my response. So, responding here.

I'm with Sascha on creating a clk_internal/clk_initializer and removing 
clk_hw. You had asked about the benefits of his suggestion in one of the 
earlier threads. I'm sure I have told some of these reasons I don't like 
clk_hw, but repeating my points here for others to chime in.

I used to be a huge proponent for using macros for clocks in our 
internal tree. All the clocks were constructed using macros (you will 
see it in the history of tree we publish in CAF). They quickly became 
unreadable when you have several hundreds of clocks. The biggest problem 
is that you can't quickly look at a clock's macro and figure out what 
the register offset or bit mask or shift value is. Our eyes/brains 
aren't meant for quickly parsing the commas and finding the n-th field 
or even remembering what the n-th field of each macro corresponds to. If 
it's actually broken out as fields in a struct, it's much easier to 
read. So, long story short, I think the well-intentioned helper macros 
will make code quite unreadable.

I also don't want to maintain such helper macros for the platform 
specific clock types that I will have to create for MSM if I were to go 
with macros.

If I choose not to use the helper macros, then I need to define three 
separate declarations for each clock. That looks messy when you have 
100s of clocks.

With clk_initializer, we also don't have to keep changing the 
clk_init/clk_register APIs whenever we add any other optional fields in 
the future. You just add it to clk_initializer and if people care for 
those fields, they can add it to the static/dynamic clocks.

Whether we use a macro or not, the current approach also adds twice the 
the no. of symbols in the debug info and increases the size of the 
kernel. When we go for a single ARM kernel, this is going to be 
noticeable. I agree that the point about debuginfo size increase might 
not matter to most.

> Hi Sascha,
>
> Thanks for the example code.  This is in fact something I had
> considered doing before, but it is a bit complicated for my platform.
>
> We set up all of the OMAP clocks with __clk_init because this is a
> dependency of OMAP's hwmod code which models and interacts with
> specific resources for hardware modules, such as clocks.  There are
> other dependencies such as our clockdomain code, which needs the
> clocks to be fully initialized.  Some aspects of these layers get
> init'd before we can allocate memory.

I know there is a version of OMAP hwmod in upstream, but is this 
dependency of fully initialized clock struct a requirement for the 
upstream version of hwmod or an internal OMAP tree? I will explain the 
reason for this question further down.

> Admittedly I think that the OMAP code could migrate some of these bits
> to a lazy-registration model, specifically the hwmod object instances,
> but that requires an awful lot of refactoring for a fairly large stack
> of platform code.  This might be something to achieve in the future
> but for now we *need* initialisation to be fully static.

When we work on moving clocks to device tree, wouldn't you face the same 
problem? You will have to dynamically create most of the clocks in that 
case too.

> Assuming that some day OMAP code can be refactored to allow for lazy
> (or at least initcall-based) registration of clocks then perhaps your
> suggestion can take root.  Which leads me to this question: are there
> any other platforms out there that require the level of expose to
> struct clk present in this patchset?  OMAP does, for now, but if that
> changes then I need to know if others require this as well.

MSM platform doesn't need exposure to clk_internal or the corresponding 
fields in clk. We too have the timer issue, but I would rather deal with 
the timer separately (using register writes from the timer code) than 
ugly up the 200+ clocks we have on each SoC.

Getting to suggesting a solution, how about we go with something similar 
to Sasha's suggestion:
* Put clk_inititalizer in clk-provider.h
* clk-provider.h has a forward declaration to clk (struct clk;)
* Put struct clk and struct clk_internal in a clk-private.h or whatever.
* Add a struct *clk field to struct clk_initializer (this is temporary).


For platforms that don't have the static init limitations you mention, 
they can do something like this:

#include <linux/clk-provider.h>

struct clk_complex {
	struct clk_initializer i;
	u32 foo;
	u32 bar;
	u8 baz;
};

struct clk_complex mmc1_clk {
	foo = 5,
	bar = 10,
	baz = 3,
	. i = {
		.name = mmc,
		.ops = &complex_ops,
	}
};

clk_register(NULL, &mmc1_clk.i);

But platforms that have the limitations you mention can do something like:

#include <clk-provider.h>
#include <clk-private.h>

struct clk __mmc1_clk;

struct clk_complex mmc1_clk {
	foo = 5,
	bar = 10,
	baz = 3,
	. i = {
		.name = mmc,
		.ops = &complex_ops,
		.clk = &__mmc1_clk;
	}
};

clk_init(NULL, &mmc1_clk.i);

I guess another way to look at this is: move all the inputs params in 
clk_register() to clk_hw and rename clk_hw to clk_initializer.

With the above solutions, those that don't have the OMAP-like 
limitations can have their code look much cleaner, and OMAP can still 
continue to work. After the initial conversion of all platform to the 
common clock framework, we don't allow anyone to ever include 
clk-private.h. We could even add it to check_patch.pl. Then once 
everyone fixes their static initialization limitations, we can delete 
the clk field from clk_initializer and move struct clk to clk.c.

Thoughts?

Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From skannan at codeaurora.org  Fri Mar 16 23:28:02 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Fri, 16 Mar 2012 20:28:02 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <1331878280-2758-3-git-send-email-mturquette@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
Message-ID: <4F6404C2.7000506@codeaurora.org>

On 03/15/2012 11:11 PM, Mike Turquette wrote:
> The common clock framework defines a common struct clk useful across
> most platforms as well as an implementation of the clk api that drivers
> can use safely for managing clocks.
>
> The net result is consolidation of many different struct clk definitions
> and platform-specific clock framework implementations.
>
> This patch introduces the common struct clk, struct clk_ops and an
> implementation of the well-known clock api in include/clk/clk.h.
> Platforms may define their own hardware-specific clock structure and
> their own clock operation callbacks, so long as it wraps an instance of
> struct clk_hw.
>
> See Documentation/clk.txt for more details.
>
> This patch is based on the work of Jeremy Kerr, which in turn was based
> on the work of Ben Herrenschmidt.
>
> Signed-off-by: Mike Turquette<mturquette at linaro.org>
> Signed-off-by: Mike Turquette<mturquette at ti.com>
> Reviewed-by: Thomas Gleixner<tglx at linutronix.de>
> Tested-by: Andrew Lunn<andrew at lunn.ch>
> Reviewed-by: Rob Herring<rob.herring<at>  calxeda.com>
> Cc: Russell King<linux at arm.linux.org.uk>
> Cc: Jeremy Kerr<jeremy.kerr at canonical.com>
> Cc: Arnd Bergman<arnd.bergmann at linaro.org>
> Cc: Paul Walmsley<paul at pwsan.com>
> Cc: Shawn Guo<shawn.guo at freescale.com>
> Cc: Sascha Hauer<s.hauer at pengutronix.de>
> Cc: Richard Zhao<richard.zhao at linaro.org>
> Cc: Saravana Kannan<skannan at codeaurora.org>
> Cc: Magnus Damm<magnus.damm at gmail.com>
> Cc: Mark Brown<broonie at opensource.wolfsonmicro.com>
> Cc: Linus Walleij<linus.walleij at stericsson.com>
> Cc: Stephen Boyd<sboyd at codeaurora.org>
> Cc: Amit Kucheria<amit.kucheria at linaro.org>
> Cc: Deepak Saxena<dsaxena at linaro.org>
> Cc: Grant Likely<grant.likely at secretlab.ca>
> ---

Mike,

Thanks for the patches! Glad to see that it's finally getting in! I sent 
a request for a minor change as a reply to the v5 series (since it had 
more context). Can you please take a look at that and let me know if you 
can send out a v8 or a patch on top of this to do that?

Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From skannan at codeaurora.org  Fri Mar 16 23:38:54 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Fri, 16 Mar 2012 20:38:54 -0700
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <4F63E0D3.3060106@gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <20120316234706.GJ3852@pengutronix.de> <4F63E0D3.3060106@gmail.com>
Message-ID: <4F64074E.2070903@codeaurora.org>

On 03/16/2012 05:54 PM, Rob Herring wrote:
> On 03/16/2012 06:47 PM, Sascha Hauer wrote:
>> Hi Paul,
>>
>> On Fri, Mar 16, 2012 at 04:21:17PM -0600, Paul Walmsley wrote:
>>> Hi
>>>
>>> On Fri, 16 Mar 2012, Arnd Bergmann wrote:
>>>
>>>
>>> If the common clock code is to go upstream now, it should be marked as
>>> experimental.
>>
>> No, please don't do this. This effectively marks the architectures using
>> the generic clock framework experimental. We can mark drivers as 'you
>> have been warned', but marking an architecture as experimental is the
>> wrong sign for both its users and people willing to adopt the framework.
>> Also we get this:
>>
>> warning: (ARCH_MX1&&  MACH_MX21&&  ARCH_MX25&&  MACH_MX27) selects COMMON_CLK which has unmet direct dependencies (EXPERIMENTAL)
>>
>> (and no, I don't want to support to clock frameworks in parallel)
>>
>
> +1
>
> For simple users at least, the api is perfectly adequate and it is not
> experimental (unless new means experimental).
>

+1 - not experimental please.

While I agree with Mike and Paul that there is room for a lot of 
improvements to the clock APIs, I think the existing APIs in this patch 
series can become macro wrappers around any new APIs improvements we add 
in the future.

We should have really done that for the 
clk_prepare_enable/unprepare_disable(), but it should certainly be 
doable for future API additions now that we have the atomic/non-atomic 
differentiation out of the way.

Thanks,
Saravana


-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From dmitry.torokhov at gmail.com  Sat Mar 17 01:36:19 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Fri, 16 Mar 2012 22:36:19 -0700
Subject: [PATCH 1/2] input: keypad: move platform_data to
 <linux/platform_data>
In-Reply-To: <20120316210841.GA19797@arwen.pp.htv.fi>
References: <1331907989-11891-1-git-send-email-sourav.poddar@ti.com>
 <1331907989-11891-2-git-send-email-sourav.poddar@ti.com>
 <1357514.ox9yZWgqO9@dtor-d630.eng.vmware.com>
 <20120316210841.GA19797@arwen.pp.htv.fi>
Message-ID: <20120317053619.GA20049@core.coreip.homeip.net>

On Fri, Mar 16, 2012 at 11:08:43PM +0200, Felipe Balbi wrote:
> Hi,
> 
> On Fri, Mar 16, 2012 at 09:36:19AM -0700, Dmitry Torokhov wrote:
> > On Friday, March 16, 2012 07:56:28 PM Sourav Poddar wrote:
> > > From: Felipe Balbi <balbi at ti.com>
> > > 
> > > This patch allows us to drop the OMAP depencendy
> > > from the OMAP4 keypad driver.
> > > 
> > > Signed-off-by: Felipe Balbi <balbi at ti.com>
> > > Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> > > ---
> > >  arch/arm/mach-omap2/board-4430sdp.c            |    1 +
> > >  arch/arm/mach-omap2/devices.c                  |    1 +
> > >  arch/arm/plat-omap/include/plat/omap4-keypad.h |    9 ---------
> > >  drivers/input/keyboard/Kconfig                 |    1 -
> > >  drivers/input/keyboard/omap4-keypad.c          |    2 +-
> > >  include/linux/platform_data/omap4-keypad.h     |   13 +++++++++++++
> > 
> > Instead of creating platform_data directory why not move to
> > include/linux/input/omap4-keypad.h?
> 
> look closer, that directory already exists. But if you prefer placing
> that header on <linux/input> that's doable too.

OK, fair enough, applied.

-- 
Dmitry


From dmitry.torokhov at gmail.com  Sat Mar 17 01:47:15 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Fri, 16 Mar 2012 22:47:15 -0700
Subject: [PATCH 2/2] Input: omap-keypad: dynamically handle register
 offsets
In-Reply-To: <1331907989-11891-3-git-send-email-sourav.poddar@ti.com>
References: <1331907989-11891-1-git-send-email-sourav.poddar@ti.com>
 <1331907989-11891-3-git-send-email-sourav.poddar@ti.com>
Message-ID: <20120317054715.GB20049@core.coreip.homeip.net>

Hi Sourav,

On Fri, Mar 16, 2012 at 07:56:29PM +0530, Sourav Poddar wrote:
> From: G, Manjunath Kondaiah <manjugk at ti.com>
> 
> Keypad controller register offsets are different for omap4
> and omap5. Handle these offsets through static mapping and
> assign these mappings during run time.
> 
> Signed-off-by: Felipe Balbi <balbi at ti.com>
> Signed-off-by: G, Manjunath Kondaiah <manjugk at ti.com>
> Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
> ---
>  drivers/input/keyboard/Kconfig        |    6 +-
>  drivers/input/keyboard/omap4-keypad.c |  122 ++++++++++++++++++++++++++------
>  2 files changed, 102 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
> index 1379daa..09d7d0b 100644
> --- a/drivers/input/keyboard/Kconfig
> +++ b/drivers/input/keyboard/Kconfig
> @@ -510,10 +510,10 @@ config KEYBOARD_OMAP
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called omap-keypad.
>  
> -config KEYBOARD_OMAP4
> -	tristate "TI OMAP4 keypad support"
> +config KEYBOARD_OMAP4+
> +	tristate "TI OMAP4+ keypad support"
>  	help
> -	  Say Y here if you want to use the OMAP4 keypad.
> +	  Say Y here if you want to use the OMAP4+ keypad.
>  
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called omap4-keypad.
> diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c
> index e809ac0..6872495 100644
> --- a/drivers/input/keyboard/omap4-keypad.c
> +++ b/drivers/input/keyboard/omap4-keypad.c
> @@ -68,6 +68,11 @@
>  
>  #define OMAP4_MASK_IRQSTATUSDISABLE	0xFFFF
>  
> +enum {
> +	KBD_REVISION_OMAP4 = 0,
> +	KBD_REVISION_OMAP5,
> +};
> +
>  struct omap4_keypad {
>  	struct input_dev *input;
>  
> @@ -76,11 +81,79 @@ struct omap4_keypad {
>  
>  	unsigned int rows;
>  	unsigned int cols;
> +	unsigned int revision;
>  	unsigned int row_shift;
>  	unsigned char key_state[8];
>  	unsigned short keymap[];
>  };
>  
> +static int kbd_read_irqstatus(struct omap4_keypad *keypad_data, u32 offset)
> +{
> +	if (keypad_data->revision == KBD_REVISION_OMAP4)
> +		return __raw_readl(keypad_data->base + offset);
> +	else if (keypad_data->revision == KBD_REVISION_OMAP5)
> +		return __raw_readl(keypad_data->base + offset + 0x0c);
> +

This is called from ISR and doing comparisons seems quite wasteful. Why
don't you stuff register numbers for IRQ manipulations into struct
omap4_keypad at probe time and your function would just do:

	return __raw_readl(keypad_data->base + keypad_data->irqstatus_reg);

And do the same for irqstatus. FOr the rest of the register store the
common offset (seems to be 0x10).

> +	return -ENODEV;
> +}
> +
> +static int kbd_write_irqstatus(struct omap4_keypad *keypad_data,
> +						u32 offset, u32 value)
> +{
> +	if (keypad_data->revision == KBD_REVISION_OMAP4)
> +		return __raw_writel(value, keypad_data->base + offset);
> +	else if (keypad_data->revision == KBD_REVISION_OMAP5)
> +		return __raw_writel(value, keypad_data->base + offset + 0x0c);
> +
> +	return -ENODEV;
> +}
> +
> +static int kbd_write_irqenable(struct omap4_keypad *keypad_data,
> +						u32 offset, u32 value)
> +{
> +	if (keypad_data->revision == KBD_REVISION_OMAP4)
> +		return __raw_writel(value, keypad_data->base + offset);
> +	else if (keypad_data->revision == KBD_REVISION_OMAP5)
> +		return __raw_writel(value, keypad_data->base + offset + 0x0c);
> +
> +	return -ENODEV;
> +}
> +
> +static int kbd_readl(struct omap4_keypad *keypad_data, u32 offset)
> +{
> +	if (keypad_data->revision == KBD_REVISION_OMAP4)
> +		return __raw_readl(keypad_data->base + offset);
> +	else if (keypad_data->revision == KBD_REVISION_OMAP5)
> +		return __raw_readl(keypad_data->base + offset + 0x10);
> +
> +	return -ENODEV;
> +}
> +
> +static void kbd_writel(struct omap4_keypad *keypad_data, u32 offset, u32 value)
> +{
> +	if (keypad_data->revision == KBD_REVISION_OMAP4)
> +		__raw_writel(value, keypad_data->base + offset);
> +	else if (keypad_data->revision == KBD_REVISION_OMAP5)
> +		__raw_writel(value, keypad_data->base + offset + 0x10);
> +}
> +
> +static int kbd_read_revision(struct omap4_keypad *keypad_data, u32 offset)
> +{
> +	int reg;
> +	reg = __raw_readl(keypad_data->base + offset);
> +	reg &= 0x03 << 30;
> +	reg >>= 30;
> +
> +	switch (reg) {
> +	case 1:
> +		return KBD_REVISION_OMAP5;
> +	case 0:
> +		return KBD_REVISION_OMAP4;
> +	default:
> +		return -ENODEV;
> +	}
> +}
> +
>  /* Interrupt handler */
>  static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
>  {
> @@ -91,12 +164,11 @@ static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
>  	u32 *new_state = (u32 *) key_state;
>  
>  	/* Disable interrupts */
> -	__raw_writel(OMAP4_VAL_IRQDISABLE,
> -		     keypad_data->base + OMAP4_KBD_IRQENABLE);
> +	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
> +						OMAP4_VAL_IRQDISABLE);
>  
> -	*new_state = __raw_readl(keypad_data->base + OMAP4_KBD_FULLCODE31_0);
> -	*(new_state + 1) = __raw_readl(keypad_data->base
> -						+ OMAP4_KBD_FULLCODE63_32);
> +	*new_state = kbd_readl(keypad_data, OMAP4_KBD_FULLCODE31_0);
> +	*(new_state + 1) = kbd_readl(keypad_data, OMAP4_KBD_FULLCODE63_32);
>  
>  	for (row = 0; row < keypad_data->rows; row++) {
>  		changed = key_state[row] ^ keypad_data->key_state[row];
> @@ -121,12 +193,13 @@ static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
>  		sizeof(keypad_data->key_state));
>  
>  	/* clear pending interrupts */
> -	__raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS),
> -			keypad_data->base + OMAP4_KBD_IRQSTATUS);
> +	kbd_write_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS,
> +			kbd_read_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS));
>  
>  	/* enable interrupts */
> -	__raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN | OMAP4_DEF_IRQENABLE_LONGKEY,
> -			keypad_data->base + OMAP4_KBD_IRQENABLE);
> +	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
> +			OMAP4_DEF_IRQENABLE_EVENTEN |
> +				OMAP4_DEF_IRQENABLE_LONGKEY);
>  
>  	return IRQ_HANDLED;
>  }
> @@ -139,16 +212,19 @@ static int omap4_keypad_open(struct input_dev *input)
>  
>  	disable_irq(keypad_data->irq);
>  
> -	__raw_writel(OMAP4_VAL_FUNCTIONALCFG,
> -			keypad_data->base + OMAP4_KBD_CTRL);
> -	__raw_writel(OMAP4_VAL_DEBOUNCINGTIME,
> -			keypad_data->base + OMAP4_KBD_DEBOUNCINGTIME);
> -	__raw_writel(OMAP4_VAL_IRQDISABLE,
> -			keypad_data->base + OMAP4_KBD_IRQSTATUS);
> -	__raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN | OMAP4_DEF_IRQENABLE_LONGKEY,
> -			keypad_data->base + OMAP4_KBD_IRQENABLE);
> -	__raw_writel(OMAP4_DEF_WUP_EVENT_ENA | OMAP4_DEF_WUP_LONG_KEY_ENA,
> -			keypad_data->base + OMAP4_KBD_WAKEUPENABLE);
> +	keypad_data->revision = kbd_read_revision(keypad_data,
> +			OMAP4_KBD_REVISION);

You want to bail out of kbd_read_revision() returns error here.

> +	kbd_writel(keypad_data, OMAP4_KBD_CTRL,
> +			OMAP4_VAL_FUNCTIONALCFG);
> +	kbd_writel(keypad_data, OMAP4_KBD_DEBOUNCINGTIME,
> +			OMAP4_VAL_DEBOUNCINGTIME);
> +	kbd_write_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS,
> +			OMAP4_VAL_IRQDISABLE);
> +	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
> +			OMAP4_DEF_IRQENABLE_EVENTEN |
> +				OMAP4_DEF_IRQENABLE_LONGKEY);
> +	kbd_writel(keypad_data, OMAP4_KBD_WAKEUPENABLE,
> +			OMAP4_DEF_WUP_EVENT_ENA | OMAP4_DEF_WUP_LONG_KEY_ENA);
>  
>  	enable_irq(keypad_data->irq);
>  
> @@ -162,12 +238,12 @@ static void omap4_keypad_close(struct input_dev *input)
>  	disable_irq(keypad_data->irq);
>  
>  	/* Disable interrupts */
> -	__raw_writel(OMAP4_VAL_IRQDISABLE,
> -		     keypad_data->base + OMAP4_KBD_IRQENABLE);
> +	kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
> +			OMAP4_VAL_IRQDISABLE);
>  
>  	/* clear pending interrupts */
> -	__raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS),
> -			keypad_data->base + OMAP4_KBD_IRQSTATUS);
> +	kbd_write_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS,
> +			kbd_read_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS));
>  
>  	enable_irq(keypad_data->irq);
>  
> -- 
> 1.7.1
> 

Thanks.

-- 
Dmitry


From kmpark at infradead.org  Sat Mar 17 02:10:58 2012
From: kmpark at infradead.org (Kyungmin Park)
Date: Sat, 17 Mar 2012 15:10:58 +0900
Subject: [PATCH v4 0/7] Add TI EMIF SDRAM controller driver
In-Reply-To: <1331934707-29487-1-git-send-email-aneesh@ti.com>
References: <1331934707-29487-1-git-send-email-aneesh@ti.com>
Message-ID: <CAH9JG2XB86id0qTMUV9j6x6hJVaP=iJaEOtM_7c05QTovr4sig@mail.gmail.com>

Hi,

On 3/17/12, Aneesh V <aneesh at ti.com> wrote:
> Add a driver for the EMIF SDRAM controller used in TI SoCs
>
> EMIF is an SDRAM controller that supports, based on its revision,
> one or more of LPDDR2/DDR2/DDR3 protocols.This driver adds support
> for LPDDR2.
>
> The driver supports the following features:
> - Calculates the DDR AC timing parameters to be set in EMIF
>   registers using data from the device data-sheets and based
>   on the DDR frequency. If data from data-sheets is not available
>   default timing values from the JEDEC spec are used. These
>   will be safe, but not necessarily optimal
> - API for changing timings during DVFS or at boot-up
> - Temperature alert configuration and handling of temperature
>   alerts, if any for LPDDR2 devices
>   * temperature alert is based on periodic polling of MR4 mode
>     register in DDR devices automatically performed by hardware
>   * timings are de-rated and brought back to nominal when
>     temperature raises and falls respectively
> - Cache of calculated register values to avoid re-calculating
>   them
>
> The driver will need some minor updates when it is eventually
> integrated with Dynamic Voltage and Frequency Scaling (DVFS).
> This can not be done now as DVFS support is not available in
> the mainline yet.
Do you see the devfreq? it's designed for non-cpu device frequency.
It's role is similar with cpufreq.

Now samsung exynos uses devfreq for DRAM bus frequency.

Thank you,
Kyungmin Park
>
> Discussions with Santosh Shilimkar <santosh.shilimkar at ti.com>
> were immensely helpful in shaping up the interfaces. Vibhore Vardhan
> <vvardhan at gmail.com> did the initial code snippet for thermal
> handling.
>
> Testing:
> - The driver is tested on OMAP4430 SDP.
> - The driver in a slightly adapted form is also tested on OMAP5.
> - Since mainline kernel doesn't have DVFS support yet,
>   testing was done using a test module.
> - Temperature alert handling was tested with simulated interrupts
>   and faked temperature values as testing all cases in real-life
>   scenarios is difficult.
> - Tested the driver as a module
>
> Cc: Greg KH <greg at kroah.com>
>
> v4:
> - Converted instances of EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
> - Removed un-necessary "#ifndef __ASSEMBLY__'
> - Minor formatting fix
>
> v2:
> - Fixed a bug found in the implementation of errata i728
>   workaround
> - Fixed the value of frequency printed in debugfs
> - Dropped the hwmod patch as Paul has already posted a
>   a hwmod series [1] that adds hwmod for EMIF
> - Converted instances of __init to __init_or_module
>
> [1] http://thread.gmane.org/gmane.linux.ports.arm.omap/72855
>
> Aneesh V (7):
>   misc: ddr: add LPDDR2 data from JESD209-2
>   misc: emif: add register definitions for EMIF
>   misc: emif: add basic infrastructure for EMIF driver
>   misc: emif: handle frequency and voltage change events
>   misc: emif: add interrupt and temperature handling
>   misc: emif: add one-time settings
>   misc: emif: add debugfs entries for emif
>
>  Documentation/misc-devices/ti-emif.txt  |   58 ++
>  drivers/misc/Kconfig                    |   12 +
>  drivers/misc/Makefile                   |    1 +
>  drivers/misc/emif.c                     | 1670
> +++++++++++++++++++++++++++++++
>  drivers/misc/emif.h                     |  589 +++++++++++
>  include/linux/platform_data/emif_plat.h |  128 +++
>  include/misc/jedec_ddr.h                |  175 ++++
>  lib/Kconfig                             |    8 +
>  lib/Makefile                            |    2 +
>  lib/jedec_ddr_data.c                    |  135 +++
>  10 files changed, 2778 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/misc-devices/ti-emif.txt
>  create mode 100644 drivers/misc/emif.c
>  create mode 100644 drivers/misc/emif.h
>  create mode 100644 include/linux/platform_data/emif_plat.h
>  create mode 100644 include/misc/jedec_ddr.h
>  create mode 100644 lib/jedec_ddr_data.c
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From ohad at wizery.com  Sat Mar 17 02:39:08 2012
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Sat, 17 Mar 2012 08:39:08 +0200
Subject: [PATCH 1/7] remoteproc: resource table overhaul
In-Reply-To: <4F6354E4.8030704@monstr.eu>
References: <1330589497-4139-1-git-send-email-ohad@wizery.com>
 <1330589497-4139-2-git-send-email-ohad@wizery.com>
 <4F6354E4.8030704@monstr.eu>
Message-ID: <CAK=Wgbbbi4GnuHedSh6cR1LhkZr8c9q6i=_TLSL252LpPB8Xsw@mail.gmail.com>

Hi Michal,

On Fri, Mar 16, 2012 at 4:57 PM, Michal Simek <monstr at monstr.eu> wrote:
> In previous version I had carverout first which means that code was copyied
> to physical address 0x0 and then vrigns were allocated. Current code
> allocate vring first and then RTOS is not able to run from zero address.

In general, depending on specific allocation ordering is error prone
and you shouldn't do it.

For a given device, we treat memory allocated with
dma_alloc_coherent() as homogeneous. We care about its utilization and
alignments of allocations rather than their specific location in the
total region.

If that's not the case, and there's special memory you want assigned
with a specific purpose, than it's recommended to let the code make
sure it happens explicitly, and not rely on implicit order of
allocation.

Today there's no way to assign several memory regions with a specific
device, but a reasonable workaround that's being used is creating
several sub-devices with the special memory, and then looking them up
with stuff like device_for_each_child() or device_find_child().

About your specific issue: the current allocation scheme was chosen
for simplicity, but I do plan to change it back by postponing the
vring dma allocation until a remote processor is really powered on.
It's not a lot of memory, but this way we'd only allocate it when
really needed (so if it's CMA, others could use it).

IOW: you can probably just wait a bit until this patch is ready and
take it into your tree. It will most likely bring back the behavior you
need :)

Ohad.


From lee.jones at linaro.org  Sat Mar 17 04:49:58 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Sat, 17 Mar 2012 08:49:58 +0000
Subject: [GIT PULL] [for v3.4] Pull request containing ux500 DT enablement
In-Reply-To: <201203162009.48239.arnd@arndb.de>
References: <4F62220D.1090106@linaro.org> <201203162009.48239.arnd@arndb.de>
Message-ID: <4F645036.2030900@linaro.org>

On 16/03/12 20:09, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Lee Jones wrote:
>> The following changes since commit fff9a13341312c8d0f06e04c1345e855528b03da:
>>
>>   ARM: ux500: CONFIG: Enable Device Tree support for future endeavours (2012-03-15 16:33:54 +0000)
>>
>> are available in the git repository at:
>>   git://git.linaro.org/people/ljones/linux-3.0-ux500.git device-tree-snowball-ux500
>>
>> Arnd Bergmann (3):
>>       ARM: ux500: Initial Device Tree support for Snowball
>>       ARM: ux500: combine the board init functions for DT boot
>>       ARM: ux500: split dts file for snowball into generic part
>>
>> Lee Jones (5):
>>       ARM: ux500: db8500: list most devices in the snowball device tree
>>       ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt Controller) in Device Tree
>>       ARM: ux500: Enable PL011 AMBA UART Controller for Device Tree
>>       ARM: ux500: Enable PL310 Level 2 Cache Controller in Device Tree
>>       ARM: ux500: Enable PL022 SSP Controller in Device Tree
> 
> I've pulled this into next/dt2, not next/dt for now. I had to rebase the patches
> as we discussed and then did some build tests to make sure nothing broke. I found
> one bug with your patches and CONFIG_OF disabled, which I fixed in the patch itself,

I did test the patch-set with CONFIG_OF disabled, but it looks like I
wasn't diligent enough to deselect CONFIG_MACH_UX500_DT, which selects
USE_OF.

Thanks for fixing though.

> and found some build warnings that you should take a look at in the for-next
> branch. 

Okay, that patch is actually going in via the drivers/base tree. I have
a patch to fix the compile errors. It's only a single character change.
Can you apply it through your tree? I'll send it up to the ML and CC
Greg and yourself.

> Also the patch "CONFIG: Enable Device Tree support for future endeavours"
> seems essential for the entire series, so I applied it as well, along with 
> your localtime patch.

Yes it is. It should have been part of the pull-request. That's my error
for rushing, sorry.

> I still think we can make it for v3.4, but I'll let this sit in linux-next for a
> few days longer than the other pull requests and if we find more problems it's out
> and gets postponed till v3.5.

I'm sure it will be fine now. :)

Kind regards,
Lee

-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Sat Mar 17 05:01:10 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Sat, 17 Mar 2012 09:01:10 +0000
Subject: [PATCH] drivers/base: fix compiler warning in SoC export driver -
 idr should be ida
Message-ID: <4F6452D6.30307@linaro.org>

Reported-by: Arnd Bergman <arnd at arndb.de>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/base/soc.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/base/soc.c b/drivers/base/soc.c
index 05f1503..e57aec1 100644
--- a/drivers/base/soc.c
+++ b/drivers/base/soc.c
@@ -15,7 +15,7 @@
 #include <linux/sys_soc.h>
 #include <linux/err.h>
 
-static DEFINE_IDR(soc_ida);
+static DEFINE_IDA(soc_ida);
 static DEFINE_SPINLOCK(soc_lock);
 
 static ssize_t soc_info_get(struct device *dev,
-- 
1.7.5.4


From linux at arm.linux.org.uk  Sat Mar 17 05:04:24 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 17 Mar 2012 09:04:24 +0000
Subject: [PATCH] drivers/base: fix compiler warning in SoC export
 driver - idr should be ida
In-Reply-To: <4F6452D6.30307@linaro.org>
References: <4F6452D6.30307@linaro.org>
Message-ID: <20120317090424.GK15988@n2100.arm.linux.org.uk>

On Sat, Mar 17, 2012 at 09:01:10AM +0000, Lee Jones wrote:

If you're fixing a warning, please always include the warning in the
commit description.

> Reported-by: Arnd Bergman <arnd at arndb.de>
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
> ---
>  drivers/base/soc.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/base/soc.c b/drivers/base/soc.c
> index 05f1503..e57aec1 100644
> --- a/drivers/base/soc.c
> +++ b/drivers/base/soc.c
> @@ -15,7 +15,7 @@
>  #include <linux/sys_soc.h>
>  #include <linux/err.h>
>  
> -static DEFINE_IDR(soc_ida);
> +static DEFINE_IDA(soc_ida);
>  static DEFINE_SPINLOCK(soc_lock);
>  
>  static ssize_t soc_info_get(struct device *dev,
> -- 
> 1.7.5.4
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From arnd at arndb.de  Sat Mar 17 05:05:32 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 17 Mar 2012 09:05:32 +0000
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <CAJOA=zPmy7Dwzw8EOCW_+cvy2Dv=w0TPUq7Zg_s=Y0rs+v+u2w@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <CAJOA=zPmy7Dwzw8EOCW_+cvy2Dv=w0TPUq7Zg_s=Y0rs+v+u2w@mail.gmail.com>
Message-ID: <201203170905.33191.arnd@arndb.de>

On Friday 16 March 2012, Turquette, Mike wrote:
> On Fri, Mar 16, 2012 at 3:21 PM, Paul Walmsley <paul at pwsan.com> wrote:
> > From: Paul Walmsley <paul at pwsan.com>
> > Date: Fri, 16 Mar 2012 16:06:30 -0600
> > Subject: [PATCH] clk: mark the common clk code as EXPERIMENTAL for now
> >
> > Mark the common clk code as depending on CONFIG_EXPERIMENTAL.  The API
> > is not well-defined and both it and the underlying mechanics are likely
> > to need significant changes to support non-trivial uses of the rate
> > changing code, such as DVFS with external I/O devices.  So any platforms
> > that switch their implementation over to this may need to revise much
> > of their driver code and revalidate their implementations until the
> > behavior of the code is better-defined.
> >
> > A good time for removing this EXPERIMENTAL designation would be after at
> > least two platforms that do DVFS on groups of external I/O devices have
> > ported their clock implementations over to the common clk code.
> >
> > Signed-off-by: Paul Walmsley <paul at pwsan.com>
> > Cc: Mike Turquette <mturquette at ti.com>
> 
> ACK.  This will set some reasonable expectations while things are in flux.
> 
> Arnd are you willing to take this in?

I think it's rather pointless, because the option is not going to
be user selectable but will get selected by the platform unless I'm
mistaken. The platform maintainers that care already know the state
of the framework. Also, there are no user space interfaces that we
have to warn users about not being stable, because the framework
is internal to the kernel.

However, I wonder whether we need the patch below to prevent
users from accidentally enabling COMMON_CLK on platforms that
already provide their own implementation.

	Arnd

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 2eaf17e..a0a83de 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -12,7 +12,7 @@ config HAVE_MACH_CLKDEV

 menuconfig COMMON_CLK
-       bool "Common Clock Framework"
+	bool
        select HAVE_CLK_PREPARE
        ---help---
          The common clock framework is a single definition of struct
          clk, useful across many platforms, as well as an


From lee.jones at linaro.org  Sat Mar 17 05:12:11 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Sat, 17 Mar 2012 09:12:11 +0000
Subject: [PATCH] drivers/base: fix compiler warning in SoC export driver
 - idr should be ida
In-Reply-To: <20120317090424.GK15988@n2100.arm.linux.org.uk>
References: <4F6452D6.30307@linaro.org>
 <20120317090424.GK15988@n2100.arm.linux.org.uk>
Message-ID: <4F64556B.3010505@linaro.org>

On 17/03/12 09:04, Russell King - ARM Linux wrote:
> On Sat, Mar 17, 2012 at 09:01:10AM +0000, Lee Jones wrote:
> 
> If you're fixing a warning, please always include the warning in the
> commit description.

No problem, thanks.

>> Reported-by: Arnd Bergman <arnd at arndb.de>
>> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
>> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>> ---
>>  drivers/base/soc.c |    2 +-
>>  1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/base/soc.c b/drivers/base/soc.c
>> index 05f1503..e57aec1 100644
>> --- a/drivers/base/soc.c
>> +++ b/drivers/base/soc.c
>> @@ -15,7 +15,7 @@
>>  #include <linux/sys_soc.h>
>>  #include <linux/err.h>
>>  
>> -static DEFINE_IDR(soc_ida);
>> +static DEFINE_IDA(soc_ida);
>>  static DEFINE_SPINLOCK(soc_lock);
>>  
>>  static ssize_t soc_info_get(struct device *dev,
>> -- 
>> 1.7.5.4
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


-- 
Lee Jones
Linaro ST-Ericsson Landing Team Lead
M: +44 77 88 633 515
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog


From lee.jones at linaro.org  Sat Mar 17 05:17:49 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Sat, 17 Mar 2012 09:17:49 +0000
Subject: [PATCH] drivers/base: fix compiler warning in SoC export driver -
 idr should be ida
Message-ID: <4F6456BD.9080205@linaro.org>

This fixes:
  note: expected ?struct ida *? but argument is of type ?struct idr *?
  warning: passing argument 1 of ?ida_pre_get? from incompatible pointer type

Reported-by: Arnd Bergman <arnd at arndb.de>
Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 drivers/base/soc.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/base/soc.c b/drivers/base/soc.c
index 05f1503..e57aec1 100644
--- a/drivers/base/soc.c
+++ b/drivers/base/soc.c
@@ -15,7 +15,7 @@
 #include <linux/sys_soc.h>
 #include <linux/err.h>
 
-static DEFINE_IDR(soc_ida);
+static DEFINE_IDA(soc_ida);
 static DEFINE_SPINLOCK(soc_lock);
 
 static ssize_t soc_info_get(struct device *dev,
-- 
1.7.5.4


From philipp.zabel at gmail.com  Sat Mar 17 06:24:25 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Sat, 17 Mar 2012 11:24:25 +0100
Subject: [RFC/PATCH 4/4] pxa: convert to common clock framework
In-Reply-To: <CAJOA=zN2dxgjQ8EZYAwE=OLO1GLdArqy1Xf18F82en9QvFi4cw@mail.gmail.com>
References: <1331919483.31118.23.camel@flow>
 <CAJOA=zN2dxgjQ8EZYAwE=OLO1GLdArqy1Xf18F82en9QvFi4cw@mail.gmail.com>
Message-ID: <CA+gwMcdzHpGhLXXh5QTYid+rBtj8cGqFS9Te4QB3rpR9B8hXUw@mail.gmail.com>

Hi Mike,

On Fri, Mar 16, 2012 at 11:03 PM, Turquette, Mike <mturquette at ti.com> wrote:
> On Fri, Mar 16, 2012 at 10:38 AM, Philipp Zabel <philipp.zabel at gmail.com> wrote:
>> ?#define DEFINE_CK(_name, _cken, _ops) ? ? ? ? ? ? ? ? ?\
>> -struct clk clk_##_name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> - ? ? ? ? ? ? ? .ops ? ?= _ops, ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? struct clk clk_##_name; ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? static struct clk_pxa clk_pxa_##_name = { ? ? ? \
>> + ? ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? ? ? ? ? ? .clk = &clk_##_name, ? ? ? ? ? ?\
>> + ? ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> ? ? ? ? ? ? ? ?.cken ? = CKEN_##_cken, ? ? ? ? ? ? ? ? \
>> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> + ? ? ? static struct clk clk_##_name = { ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? ? .name ? = #_name, ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? ? .ops ? ?= _ops, ? ? ? ? ? ? ? ? ? ? ? ? \
>> + ? ? ? ? ? ? ? .hw ? ? = &clk_pxa_##_name.hw, ? ? ? ? ?\
>> ? ? ? ?}
>
> Hi Philipp,
>
> It looks like your macros do not initialize the .parent_names,
> .num_parents or .flags members of struct clk. ?__clk_init expects
> those to be initialized before being called. ?The kerneldoc for
> __clk_init states this:
> http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=e2cce6fa604686ea3bca0496998322bacaed854d;hb=c5836d8acd9846ec1675b269d994d96a8ee44df4#l49

Yes, thank you! That was the problem.

> You can use the macros for the basic clocks types as templates. ?The
> gate and mux macros are good to look at since those show how to handle
> a single-parent and multi-parent clock, respectively:
> http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=5e4312b6f5ccb1072273ce94e235874c74dd852d;hb=2508b44cd5c134691dc5d679f728bbf82af2abe0#l83
> and
> http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=5e4312b6f5ccb1072273ce94e235874c74dd852d;hb=2508b44cd5c134691dc5d679f728bbf82af2abe0#l148

If there was a fixed fractional divider clk element, a lot of the
peripheral clocks could be derived from a fixed clk representing the
312 MHz PPLL on PXA27x (fixed -> divider -> gate), using just the
basic clock templates.

regards
Philipp


From s.hauer at pengutronix.de  Sat Mar 17 08:28:31 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat, 17 Mar 2012 13:28:31 +0100
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <20120316011006.GA17459@b20223-02.ap.freescale.net>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
 <20120314085228.GM3852@pengutronix.de>
 <20120315144601.GA5701@richard-laptop>
 <20120315150048.GC3852@pengutronix.de>
 <20120315151521.GB5701@richard-laptop>
 <20120315185004.GD3852@pengutronix.de>
 <20120316011006.GA17459@b20223-02.ap.freescale.net>
Message-ID: <20120317122831.GD29317@pengutronix.de>

On Fri, Mar 16, 2012 at 09:10:07AM +0800, Richard Zhao wrote:
> Hi Sascha,
> 
> On Thu, Mar 15, 2012 at 07:50:04PM +0100, Sascha Hauer wrote:
> > On Thu, Mar 15, 2012 at 11:15:23PM +0800, Richard Zhao wrote:
> > > On Thu, Mar 15, 2012 at 04:00:48PM +0100, Sascha Hauer wrote:
> > > > On Thu, Mar 15, 2012 at 10:46:04PM +0800, Richard Zhao wrote:
> > > > > On Wed, Mar 14, 2012 at 09:52:28AM +0100, Sascha Hauer wrote:
> > > > > > On Wed, Mar 14, 2012 at 04:22:58PM +0800, Richard Zhao wrote:
> > > > > > > Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> > > > > > > ---
> > > > > > >  
> > > > > > >  #define DEF_PLL(name)					\
> > > > > > >  	static struct clk name = {			\
> > > > > > > @@ -681,6 +741,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
> > > > > > >  		.disable	= pll_disable,		\
> > > > > > >  		.get_rate	= name##_get_rate,	\
> > > > > > >  		.set_rate	= name##_set_rate,	\
> > > > > > > +		.round_rate	= name##_round_rate,	\
> > > > > > 
> > > > > > I hope this ## stuff is gone soon with the generic clock framework. It
> > > > > > is so ugly and inefficient.
> > > > > I hope this doesn't prevent this two patches go in.
> > > > 
> > > > Given that we are short from getting a generic clock framework (and I
> > > > think this time it's for real) and that you are not mention in any words
> > > > what these patches fix I don't see a reason for merging them.
> > > I think the cpu clock is a great challenge for generic clock framework.
> > > When it set_rate, it includes reparent, and change parent's parent's rate.
> > > I don't see any upstream code like that till now. and it's really what
> > > we need.
> > 
> > Then do a clk_set_parent, clk_set_rate and a clk_set_parent again
> > in your cpufreq driver.
> No, it's platform code, and supposed to be in arch/arm. What the cpufre
> driver know is to get cpu clk, rather not how cpu clk change its rate.
> And cpu clk/arm_clk is a real clock wires in SoC.

The job of the clock framework is to give a consistent view on the
clocks and to handle parent/rate changes properly. It even the
CLK_SET_RATE_GATE for ensuring that your PLL can only change its rate
when it's gated. It's not the job of the clock framework to dynamically
reorganize the clock tree on a rate change.

Besides, do you really want to reprogram the PLL with a cpufreq change?
You have a divider behind that PLL which you apparently can change
without having to reparent the PLL. Doesn't this give you enough choices
for the cpu frequency?

> > The notifying mechanism even allows you to
> > block any concurrent change in between these three steps if necessary.
> > Noone says that these three steps have to be encapsulated in a single
> > clk_set_rate call like you did in your patch.
> If you're reviwing the patch, why not take a step advance? :)

I have prepared the patches for converting i.MX1/21/25/27 and I have
(older) patches for the i.MX31/51/53 which I want to rebase on the
current clock framework. That gives me enough to do until the next merge
window. Additionally I'm not yet very familiar with the i.MX6.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From santosh.shilimkar at ti.com  Sat Mar 17 08:29:46 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Sat, 17 Mar 2012 17:59:46 +0530
Subject: [PATCHv2 3/5] cpuidle: add support for states that affect multiple
 cpus
In-Reply-To: <1331749794-8056-4-git-send-email-ccross@android.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
 <1331749794-8056-4-git-send-email-ccross@android.com>
Message-ID: <4F6483BA.8050103@ti.com>

Colin,

On Wednesday 14 March 2012 11:59 PM, Colin Cross wrote:
> On some ARM SMP SoCs (OMAP4460, Tegra 2, and probably more), the
> cpus cannot be independently powered down, either due to
> sequencing restrictions (on Tegra 2, cpu 0 must be the last to
> power down), or due to HW bugs (on OMAP4460, a cpu powering up
> will corrupt the gic state unless the other cpu runs a work
> around).  Each cpu has a power state that it can enter without
> coordinating with the other cpu (usually Wait For Interrupt, or
> WFI), and one or more "coupled" power states that affect blocks
> shared between the cpus (L2 cache, interrupt controller, and
> sometimes the whole SoC).  Entering a coupled power state must
> be tightly controlled on both cpus.
> 
> The easiest solution to implementing coupled cpu power states is
> to hotplug all but one cpu whenever possible, usually using a
> cpufreq governor that looks at cpu load to determine when to
> enable the secondary cpus.  This causes problems, as hotplug is an
> expensive operation, so the number of hotplug transitions must be
> minimized, leading to very slow response to loads, often on the
> order of seconds.
> 
> This file implements an alternative solution, where each cpu will
> wait in the WFI state until all cpus are ready to enter a coupled
> state, at which point the coupled state function will be called
> on all cpus at approximately the same time.
> 
> Once all cpus are ready to enter idle, they are woken by an smp
> cross call.  At this point, there is a chance that one of the
> cpus will find work to do, and choose not to enter idle.  A
> final pass is needed to guarantee that all cpus will call the
> power state enter function at the same time.  During this pass,
> each cpu will increment the ready counter, and continue once the
> ready counter matches the number of online coupled cpus.  If any
> cpu exits idle, the other cpus will decrement their counter and
> retry.
> 
> To use coupled cpuidle states, a cpuidle driver must:
> 
>    Set struct cpuidle_device.coupled_cpus to the mask of all
>    coupled cpus, usually the same as cpu_possible_mask if all cpus
>    are part of the same cluster.  The coupled_cpus mask must be
>    set in the struct cpuidle_device for each cpu.
> 
>    Set struct cpuidle_device.safe_state to a state that is not a
>    coupled state.  This is usually WFI.
> 
>    Set CPUIDLE_FLAG_COUPLED in struct cpuidle_state.flags for each
>    state that affects multiple cpus.
> 
>    Provide a struct cpuidle_state.enter function for each state
>    that affects multiple cpus.  This function is guaranteed to be
>    called on all cpus at approximately the same time.  The driver
>    should ensure that the cpus all abort together if any cpu tries
>    to abort once the function is called.
> 
> Signed-off-by: Colin Cross <ccross at android.com>
> Cc: Len Brown <len.brown at intel.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Cc: Amit Kucheria <amit.kucheria at linaro.org>
> Cc: Arjan van de Ven <arjan at linux.intel.com>
> Cc: Trinabh Gupta <g.trinabh at gmail.com>
> Cc: Deepthi Dharwar <deepthi at linux.vnet.ibm.com>
> ---

[..]

> diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
> new file mode 100644
> index 0000000..046fccb
> --- /dev/null
> +++ b/drivers/cpuidle/coupled.c
> @@ -0,0 +1,568 @@
> +/*
> + * coupled.c - helper functions to enter the same idle state on multiple cpus
> + *
> + * Copyright (c) 2011 Google, Inc.
> + *
> + * Author: Colin Cross <ccross at android.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + */

[...]

> +/**
> + * cpuidle_coupled_cpu_set_alive - adjust alive_count during hotplug transitions
> + * @cpu: target cpu number
> + * @alive: whether the target cpu is going up or down
> + *
> + * Run on the cpu that is bringing up the target cpu, before the target cpu
> + * has been booted, or after the target cpu is completely dead.
> + */
> +static void cpuidle_coupled_cpu_set_alive(int cpu, bool alive)
> +{
> +	struct cpuidle_device *dev;
> +	struct cpuidle_coupled *coupled;
> +
> +	mutex_lock(&cpuidle_lock);
> +
> +	dev = per_cpu(cpuidle_devices, cpu);
> +	if (!dev->coupled)
> +		goto out;
> +
> +	coupled = dev->coupled;
> +
> +	/*
> +	 * waiting_count must be at least 1 less than alive_count, because
> +	 * this cpu is not waiting.  Spin until all cpus have noticed this cpu
> +	 * is not idle and exited the ready loop before changing alive_count.
> +	 */
> +	while (atomic_read(&coupled->ready_count))
> +		cpu_relax();
> +
> +	smp_mb__before_atomic_inc();
> +	atomic_inc(&coupled->alive_count);
> +	smp_mb__after_atomic_inc();
> +
> +	if (alive)
> +		coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_NOT_IDLE;
> +	else
> +		coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_DEAD;
> +

While playing around with this version, I noticed that the
'alive_count' is ever incrementing which will lead to
coupled idle state not being attempted after one CPU offline
attempt.

Fix in end of the email for the same. With it, coupled states
continue to work with CPU online/offline transitions.

Feel free to fold it into original patch. Attached
the same in case mailer eat tabs.

Regards
Santosh

>>
cpuidle: coupled: Fix the alive_count based on CPU online/offline.

Currently the alive_count is ever incrementing which will lead to
coupled idle state not being attempted after one CPU offline
attempt.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 drivers/cpuidle/coupled.c |   14 +++++++++-----
 1 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c
index 3bc8a02..708bcfe 100644
--- a/drivers/cpuidle/coupled.c
+++ b/drivers/cpuidle/coupled.c
@@ -595,14 +595,18 @@ static void cpuidle_coupled_cpu_set_alive(int cpu,
bool alive)
        while (atomic_read(&coupled->ready_count))
                cpu_relax();

-       smp_mb__before_atomic_inc();
-       atomic_inc(&coupled->alive_count);
-       smp_mb__after_atomic_inc();

-       if (alive)
+       if (alive) {
+               smp_mb__before_atomic_inc();
+               atomic_inc(&coupled->alive_count);
+               smp_mb__after_atomic_inc();
                coupled->requested_state[dev->cpu] =
CPUIDLE_COUPLED_NOT_IDLE;
-       else
+       } else {
+               smp_mb__before_atomic_inc();
+               atomic_dec(&coupled->alive_count);
+               smp_mb__after_atomic_inc();
                coupled->requested_state[dev->cpu] = CPUIDLE_COUPLED_DEAD;
+       }

<upled-Fix-the-alive_count-based-on-CPU-onl.patch" 45L, 1387C 1,1
    Top




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From mgherzan at gmail.com  Sat Mar 17 08:57:31 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Sat, 17 Mar 2012 13:57:31 +0100
Subject: [PATCH v2] ARM: OMAP: WiLink platform data for the PandaBoard
In-Reply-To: <1331074504-22683-1-git-send-email-mgherzan@gmail.com>
References: <1331074504-22683-1-git-send-email-mgherzan@gmail.com>
Message-ID: <4F648A3B.7020003@gmail.com>

Hi Tony,

Am 06.03.2012 23:55, schrieb Mircea Gherzan:
> The "uim" deamon requires sysfs entries that are filled in using
> this platform data.
> 
> Signed-off-by: Mircea Gherzan <mgherzan at gmail.com>
> ---
>  arch/arm/mach-omap2/board-omap4panda.c |   14 ++++++++++++--
>  include/linux/ti_wilink_st.h           |    2 ++
>  2 files changed, 14 insertions(+), 2 deletions(-)

Gentle ping.

Thanks,
Mircea


From lost.distance at yahoo.com  Sat Mar 17 10:48:37 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Sat, 17 Mar 2012 14:48:37 +0000 (GMT)
Subject: [PATCH] pxa/hx4700: fix the LCD initialization
In-Reply-To: <1331905213.29979.1.camel@flow>
Message-ID: <1331995717.82481.YahooMailClassic@web29016.mail.ird.yahoo.com>

Hello Philipp

--- On Fri, 16/3/12, Philipp Zabel <philipp.zabel at gmail.com> wrote:
> Common sense and the SDG bootldr code
> reference dictate that
> N2.7V/7.3V be disabled here, and not LVDD, which already
> was
> disabled 10 ms earlier.
> This should only have an effect if the LCD was enabled in
> the
> bootloader.
> 
> Signed-off-by: Philipp Zabel <philipp.zabel at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Paul Parsons <lost.distance at yahoo.com>
> ---
>  arch/arm/mach-pxa/hx4700.c |? ? 2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-pxa/hx4700.c
> b/arch/arm/mach-pxa/hx4700.c
> index 61bb967..31c6dd1 100644
> --- a/arch/arm/mach-pxa/hx4700.c
> +++ b/arch/arm/mach-pxa/hx4700.c
> @@ -399,7 +399,7 @@ static void sony_lcd_init(void)
>  ??? gpio_set_value(GPIO62_HX4700_LCD_nRESET,
> 0);
>  ??? mdelay(10);
>  ??? gpio_set_value(GPIO59_HX4700_LCD_PC1,
> 0);
> -???
> gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
> +???
> gpio_set_value(GPIO112_HX4700_LCD_N2V7_7V3_ON, 0);
>  ??? mdelay(20);
>  
>  ???
> gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 1);
> -- 

After some experimenting it seems that neither GPIO110 "LCD_LVDD_3V3_ON"
nor GPIO112 "LCD_N2V7_7V3_ON" have any effect on the hx4700 LCD.
After the hx4700 boots I can turn either one off, or both off together,
and the LCD and touchscreen will continue to work normally.

Is there an authoritative description of the 7 "LCD" GPIOs (GPIO59,
GPIO62, GPIO70, GPIO84, GPIO110, GPIO111, GPIO112) that are used by
the kernel, or the 2 "LCD" GPIOs (GPIO22, GPIO73) that are not used?
The SDG code provides no enlightenment.

Paul


From grant.likely at secretlab.ca  Sat Mar 17 06:47:51 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sat, 17 Mar 2012 10:47:51 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120315102736.GA25371@avionic-0098.adnet.avionic-design.de>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <201203150922.06379.arnd@arndb.de>
 <20120315102736.GA25371@avionic-0098.adnet.avionic-design.de>
Message-ID: <20120317104751.4F00E3E0910@localhost>

On Thu, 15 Mar 2012 11:27:36 +0100, Thierry Reding <thierry.reding at avionic-design.de> wrote:
> * Arnd Bergmann wrote:
> > On Thursday 15 March 2012, Nicolas Ferre wrote:
> [...]
> > > +	i2c1: i2c at 1 {
> > > +		...
> > > +		dma-request = <&sdma 2 &sdma 3>;
> > > +		dma-request-names = "tx", "rx";
> > > +		...
> > > +	};
> > 
> > This is slightly different from how the proposed pwm binding works that
> > Thierry is working on, which uses an arbitrary property name instead of
> > requiring the use of a specific property but then allowing to give names
> > in another property.
> > 
> > I don't care much which way it's done, but please try to agree on one
> > approach that is used for both.
> > 
> > The one you have here is already used by reg and irq, while the other
> > one is used in gpio.
> 
> I think we can just use pwm as the fixed property name. Or alternatively do
> something along the lines of the regulator bindings, where we use "-pwm" as
> the suffix for specifying PWM devices. For instance if a named PWM is
> requested, the OF support code would look for a <name>-pwm property, while
> requesting an unnamed PWM would simply look at the pwm property.
> 
> When it comes to the labelling of PWM devices, I don't think both variants
> are exclusive. Currently the PWM framework uses name of the user OF device
> node for the PWM label. That is, if I have the following in the DTS:
> 
> 	pwm {
> 		..
> 	};
> 
> 	backlight {
> 		compatible = "pwm-backlight";
> 		pwm = <&pwm 0 5000000>;
> 		...
> 	};
> 
> Then the PWM will be labelled "backlight":
> 
> 	$ cat cat /sys/kernel/debug/pwm
> 	platform/tegra-pwm, 4 PWM devices
> 	pwm-0   (backlight           ): requested enabled
> 	pwm-1   ((null)              ):
> 	pwm-2   ((null)              ):
> 	pwm-3   ((null)              ):
> 
> So if we decide to explicitly allow specifying names, then we can always add
> a pwm-names property (or <name>-pwm-names respectively) to use as label and
> fallback to the user OF device node name if that property is not present.

After implementing both schemes (ie. interrupts+interrupt-names && [*-]gpios)
I definitely prefer the fixed property name plus a separate names property.
It is easier to use common code with that scheme, and easier to statically
check for correctness.

g.


From grant.likely at secretlab.ca  Sat Mar 17 05:40:59 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sat, 17 Mar 2012 09:40:59 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <20120317094059.7C2333E08E2@localhost>

On Thu, 15 Mar 2012 09:38:10 +0100, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
> Add some basic helpers to retrieve a DMA controller device_node and the
> DMA request specifications. By making DMA controllers register a generic
> translation function, we allow the management of any type of DMA requests
> specification.
> The void * output of an of_dma_xlate() function that will be implemented
> by the DMA controller can carry any type of "dma-request" argument.
> 
> The DMA client will search its associated DMA controller in the list and
> call the registered of_dam_xlate() function to retrieve the request values.
> 
> One simple xlate function is provided for the "single number" type of
> request binding.
> 
> This implementation is independent from dmaengine so it can also be used
> by legacy drivers.
> 
> For legacy reason another API will export the DMA request number into a
> Linux resource of type IORESOURCE_DMA.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Benoit Cousson <b-cousson at ti.com>

Hi Nicolas,

Comments below.

> Cc: Stephen Warren <swarren at nvidia.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Rob Herring <rob.herring at calxeda.com>
> ---
>  Documentation/devicetree/bindings/dma/dma.txt |   45 +++++
>  drivers/of/Kconfig                            |    5 +
>  drivers/of/Makefile                           |    1 +
>  drivers/of/dma.c                              |  260 +++++++++++++++++++++++++
>  include/linux/of_dma.h                        |   67 +++++++
>  5 files changed, 378 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/dma/dma.txt
>  create mode 100644 drivers/of/dma.c
>  create mode 100644 include/linux/of_dma.h
> 
> diff --git a/Documentation/devicetree/bindings/dma/dma.txt b/Documentation/devicetree/bindings/dma/dma.txt
> new file mode 100644
> index 0000000..c49e98d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/dma.txt
> @@ -0,0 +1,45 @@
> +* Generic DMA Controller and DMA request bindings
> +
> +Generic binding to provide a way for a driver to retrieve the
> +DMA request line that goes from an IP to a DMA controller.
> +
> +
> +* DMA controller
> +
> +Required property:
> +    - #dma-cells: Number of cells for each DMA line.
> +
> +
> +Example:
> +
> +	sdma: dma-controller at 48000000 {
> +		compatible = "ti,sdma-omap4"
> +		reg = <0x48000000 0x1000>;
> +		interrupts = <12>;
> +		#dma-cells = <1>;
> +	};
> +
> +
> +
> +* DMA client
> +
> +Client drivers should specify the DMA request property using a phandle to
> +the controller. If needed, the DMA request identity on that controller is then
> +added followed by optional request specifications.
> +
> +Required property:
> +    - dma-request: List of phandle + dma-request + request specifications,
> +      one group per request "line".
> +Optional property:
> +    - dma-request-names: list of strings in the same order as the dma-request
> +      in the dma-request property.
> +
> +
> +Example:
> +
> +	i2c1: i2c at 1 {
> +		...
> +		dma-request = <&sdma 2 &sdma 3>;
> +		dma-request-names = "tx", "rx";
> +		...
> +	};
> diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
> index 268163d..7d1f06b 100644
> --- a/drivers/of/Kconfig
> +++ b/drivers/of/Kconfig
> @@ -90,4 +90,9 @@ config OF_PCI_IRQ
>  	help
>  	  OpenFirmware PCI IRQ routing helpers
>  
> +config OF_DMA
> +	def_bool y
> +	help
> +	  Device Tree DMA routing helpers

Not really any point in having this config symbol at all if it is
always enabled.

> +
>  endmenu # OF
> diff --git a/drivers/of/Makefile b/drivers/of/Makefile
> index a73f5a5..6eb50c6 100644
> --- a/drivers/of/Makefile
> +++ b/drivers/of/Makefile
> @@ -12,3 +12,4 @@ obj-$(CONFIG_OF_SELFTEST) += selftest.o
>  obj-$(CONFIG_OF_MDIO)	+= of_mdio.o
>  obj-$(CONFIG_OF_PCI)	+= of_pci.o
>  obj-$(CONFIG_OF_PCI_IRQ)  += of_pci_irq.o
> +obj-$(CONFIG_OF_DMA)	+= dma.o
> diff --git a/drivers/of/dma.c b/drivers/of/dma.c
> new file mode 100644
> index 0000000..3315844
> --- /dev/null
> +++ b/drivers/of/dma.c
> @@ -0,0 +1,260 @@
> +/*
> + * Device tree helpers for DMA request / controller
> + *
> + * Based on of_gpio.c
> + *
> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/module.h>
> +#include <linux/rculist.h>
> +#include <linux/slab.h>
> +#include <linux/of.h>
> +#include <linux/of_dma.h>
> +
> +static LIST_HEAD(of_dma_list);
> +
> +struct of_dma {
> +	struct list_head of_dma_controllers;
> +	struct device_node *of_node;
> +	int of_dma_n_cells;
> +	int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
> +};

This _xlate is nearly useless as a generic API.  It solves the problem for
the specific case where the driver is hard-coded to know which DMA engine
to talk to, but since the returned data doesn't provide any context, it
isn't useful if there are multiple DMA controllers to choose from.

The void *data pointer must be replaced with a typed structure so that
context can be returned.

> +
> +/**
> + * of_dma_find_controller() - Find a DMA controller in DT DMA helpers list
> + * @np:		device node of DMA controller
> + */
> +static struct of_dma *of_dma_find_controller(struct device_node *np)
> +{
> +	struct of_dma	*ofdma;
> +
> +	list_for_each_entry_rcu(ofdma, &of_dma_list, of_dma_controllers) {
> +		if (ofdma->of_node == np)
> +			return ofdma;
> +	}
> +
> +	return NULL;
> +}
> +
> +/**
> + * of_dma_controller_register() - Register a DMA controller to DT DMA helpers
> + * @np:			device node of DMA controller
> + * @of_dma_xlate:	generic translation function which converts a phandle
> + *			arguments list into a generic output value
> + *
> + * Returns 0 on success or appropriate errno value on error.
> + *
> + * If #dma-cells is not specified in DMA controller device tree node, we assume
> + * that the DMA controller phandle will come without argument.
> + *
> + * Allocated memory should be freed with appropriate of_dma_controller_free()
> + * call.
> + */
> +int of_dma_controller_register(struct device_node *np,
> +			int (*of_dma_xlate)(struct of_phandle_args *, void *))
> +{
> +	struct of_dma	*ofdma;
> +	const __be32	*nbcells;
> +
> +	if (!np || !of_dma_xlate) {
> +		pr_err("%s: not enough information provided\n", __func__);
> +		return -EINVAL;
> +	}
> +
> +	ofdma = kzalloc(sizeof(*ofdma), GFP_KERNEL);
> +	if (!ofdma)
> +		return -ENOMEM;
> +
> +	nbcells = of_get_property(np, "#dma-cells", NULL);
> +	if (!nbcells)
> +		/*
> +		 * no #dma-cells properties: assume no argument to
> +		 * dma-request property on slave side
> +		 */
> +		ofdma->of_dma_n_cells = 0;
> +	else
> +		ofdma->of_dma_n_cells = be32_to_cpup(nbcells);

Make #dma-cells a required property

> +
> +	ofdma->of_node = np;
> +	ofdma->of_dma_xlate = of_dma_xlate;
> +
> +	/* Now queue of_dma controller structure in list */
> +	list_add_tail_rcu(&ofdma->of_dma_controllers, &of_dma_list);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(of_dma_controller_register);
> +
> +/**
> + * of_dma_controller_free() - Remove a DMA controller from DT DMA helpers list
> + * @np:		device node of DMA controller
> + *
> + * Memory allocated by of_dma_controller_register() is freed here.
> + */
> +void of_dma_controller_free(struct device_node *np)
> +{
> +	struct of_dma	*ofdma;
> +
> +	ofdma = of_dma_find_controller(np);
> +	if (ofdma) {
> +		list_del_rcu(&ofdma->of_dma_controllers);
> +		kfree(ofdma);
> +	}
> +}
> +EXPORT_SYMBOL_GPL(of_dma_controller_free);
> +
> +/**
> + * of_get_dma_request() - Get the associated DMA request data
> + * @np:		device node to get DMA request from
> + * @index:	index of the DMA request
> + * @out_data:	a output that can be filled in by the of_dma_xlate() function
> + *
> + * Returns return value of of_dma_xlate() and fills out_data (if provided).
> + * On error returns the appropriate errno value.
> + */
> +int of_get_dma_request(struct device_node *np, int index,
> +		       void *out_data)
> +{
> +	struct of_phandle_args	dma_spec;
> +	struct of_dma		*ofdma;
> +	int			ret;
> +
> +	ret = of_parse_phandle_with_args(np, "dma-request", "#dma-cells",
> +					 index, &dma_spec);
> +	if (ret) {
> +		pr_err("%s: can't parse dma property\n", np->full_name);
> +		goto err0;
> +	}
> +
> +	if (list_empty(&of_dma_list)) {
> +		pr_debug("%s: empty DMA controller list\n",
> +			 np->full_name);
> +		ret = -ENOENT;
> +		goto err1;
> +	}
> +
> +	ofdma = of_dma_find_controller(dma_spec.np);
> +	if (!ofdma) {
> +		pr_debug("%s: DMA controller %s isn't registered\n",
> +			 np->full_name, dma_spec.np->full_name);
> +		ret = -ENODEV;
> +		goto err1;
> +	}
> +
> +	if (dma_spec.args_count != ofdma->of_dma_n_cells) {
> +		pr_debug("%s: wrong #dma-cells for %s\n",
> +			 np->full_name, dma_spec.np->full_name);
> +		ret = -EINVAL;
> +		goto err1;
> +	}
> +
> +	ret = ofdma->of_dma_xlate(&dma_spec, out_data);
> +
> +err1:
> +	of_node_put(dma_spec.np);
> +err0:
> +	pr_debug("%s exited with status %d\n", __func__, ret);
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(of_get_dma_request);
> +
> +/**
> + * of_dma_xlate_onenumbercell() - Generic DMA xlate for direct one cell bindings
> + *
> + * Device Tree DMA translation function which works with one cell bindings
> + * where the cell values map directly to the hardware request number understood
> + * by the DMA controller.
> + */
> +int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec, void *dma_req)
> +{
> +	if (!dma_spec)
> +		return -EINVAL;
> +	if (WARN_ON(dma_spec->args_count != 1))
> +		return -EINVAL;
> +	*(int *)dma_req = dma_spec->args[0];

Following on from comment above; the void *dma_req parameter is dangerous.  How
does this function know that it has been passed an int* pointer?

> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(of_dma_xlate_onenumbercell);
> +
> +/**
> + * of_dma_count - Count DMA requests for a device
> + * @np:		device node to count DMAs for
> + *
> + * The function returns the count of DMA requests specified for a node.
> + *
> + * Note that the empty DMA specifiers counts too. For example,
> + *
> + * dma-request = <0
> + *                &sdma 1
> + *                0
> + *                &sdma 3>;
> + *
> + * defines four DMAs (so this function will return 4), two of which
> + * are not specified.
> + */
> +unsigned int of_dma_count(struct device_node *np)
> +{
> +	unsigned int cnt = 0;
> +
> +	do {
> +		int ret;
> +
> +		ret = of_parse_phandle_with_args(np, "dma-request",
> +						 "#dma-cells", cnt, NULL);
> +		/* A hole in the dma-request = <> counts anyway. */
> +		if (ret < 0 && ret != -EEXIST)
> +			break;
> +	} while (++cnt);
> +
> +	return cnt;
> +}
> +EXPORT_SYMBOL_GPL(of_dma_count);
> +
> +/**
> + * of_dma_to_resource - Decode a node's DMA and return it as a resource
> + * @dev: pointer to device tree node
> + * @index: zero-based index of the DMA request
> + * @r: pointer to resource structure to return result into.
> + *
> + * Using a resource to export a DMA request number to a driver should
> + * be used only for legacy purpose and on system when only one DMA controller
> + * is present.
> + * The proper and only scalable way is to use the native of_get_dma_request API
> + * in order retrieve both the DMA controller device node and the DMA request
> + * line for that controller.
> + */
> +int of_dma_to_resource(struct device_node *dev, int index, struct resource *r)
> +{
> +	const char *name = NULL;
> +	int dma;
> +	int ret;
> +
> +	if (!r)
> +		return -EINVAL;
> +
> +	ret = of_get_dma_request(dev, index, &dma);
> +	if (ret < 0)
> +		return ret;
> +
> +	/*
> +	 * Get optional "dma-request-names" property to add a name
> +	 * to the resource.
> +	 */
> +	of_property_read_string_index(dev, "dma-request-names", index,
> +				      &name);
> +
> +	r->start = dma;
> +	r->end = dma;
> +	r->flags = IORESOURCE_DMA;
> +	r->name = name ? name : dev->full_name;

I'll reiterate my concern here.  The dual meaning of r->name depending
on the presence of a dma-request-names property is a real problem.  I know
this patch set hasn't introduced the problem since it already exists for
register regions and irqs, but it is expanding it.

> +
> +	return dma;
> +}
> +EXPORT_SYMBOL_GPL(of_dma_to_resource);
> diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
> new file mode 100644
> index 0000000..c6147bb
> --- /dev/null
> +++ b/include/linux/of_dma.h
> @@ -0,0 +1,67 @@
> +/*
> + * OF helpers for DMA request / controller
> + *
> + * Based on of_gpio.h
> + *
> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __LINUX_OF_DMA_H
> +#define __LINUX_OF_DMA_H
> +
> +#include <linux/of.h>
> +
> +struct device_node;
> +
> +#ifdef CONFIG_OF_DMA
> +
> +extern int of_dma_controller_register(struct device_node *np,
> +			int (*of_dma_xlate)(struct of_phandle_args *, void *));
> +extern void of_dma_controller_free(struct device_node *np);
> +extern int of_get_dma_request(struct device_node *np, int index,
> +			      void *out_data);
> +extern unsigned int of_dma_count(struct device_node *np);
> +extern int of_dma_to_resource(struct device_node *dev, int index,
> +			      struct resource *r);
> +
> +extern int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
> +				      void *dma_req);
> +#else /* CONFIG_OF_DMA */
> +
> +static int of_dma_controller_register(struct device_node *np,
> +			int (*of_dma_xlate)(struct of_phandle_args *, void *))
> +{
> +	return -ENOSYS;
> +}
> +
> +static void of_dma_controller_free(struct device_node *np) {}
> +
> +extern int of_get_dma_request(struct device_node *np, int index,
> +			      void *out_data)
> +{
> +	return -ENOSYS;
> +}
> +
> +static inline unsigned int of_dma_count(struct device_node *np)
> +{
> +	return 0;
> +}
> +
> +static int of_dma_to_resource(struct device_node *dev, int index,
> +			      struct resource *r);
> +{
> +	return -ENOSYS;
> +}
> +
> +static int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
> +				      void *dma_req)
> +{
> +	return -ENOSYS;
> +}
> +#endif /* CONFIG_OF_DMA */
> +
> +#endif /* __LINUX_OF_DMA_H */
> -- 
> 1.7.9
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From grant.likely at secretlab.ca  Sat Mar 17 05:42:17 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sat, 17 Mar 2012 09:42:17 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120315092652.GA16389@n2100.arm.linux.org.uk>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <201203150922.06379.arnd@arndb.de>
 <20120315092652.GA16389@n2100.arm.linux.org.uk>
Message-ID: <20120317094217.6BA143E0908@localhost>

On Thu, 15 Mar 2012 09:26:52 +0000, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> On Thu, Mar 15, 2012 at 09:22:06AM +0000, Arnd Bergmann wrote:
> > On Thursday 15 March 2012, Nicolas Ferre wrote:
> > > Add some basic helpers to retrieve a DMA controller device_node and the
> > > DMA request specifications. By making DMA controllers register a generic
> > > translation function, we allow the management of any type of DMA requests
> > > specification.
> > > The void * output of an of_dma_xlate() function that will be implemented
> > > by the DMA controller can carry any type of "dma-request" argument.
> > > 
> > > The DMA client will search its associated DMA controller in the list and
> > > call the registered of_dam_xlate() function to retrieve the request values.
> > > 
> > > One simple xlate function is provided for the "single number" type of
> > > request binding.
> > > 
> > > This implementation is independent from dmaengine so it can also be used
> > > by legacy drivers.
> > > 
> > > For legacy reason another API will export the DMA request number into a
> > > Linux resource of type IORESOURCE_DMA.
> > 
> > This looks very good. I missed the first version of this patch, but was
> > thinking of very similar bindings.
> 
> There's one issue which is concerning me - when we switch OMAP to use
> DMA engine, it won't use numeric stuff anymore but the DMA engine way
> of requesting a channel (match function + data).
> 
> How does that fit into this scheme?

Not well as the current patch set stands.  The xlate function doesn't return
any context for the dma channel number that it returns, so the driver cannot
figure out which DMA controller to use if there are multiple.

g.



From thomas.petazzoni at free-electrons.com  Sat Mar 17 11:43:45 2012
From: thomas.petazzoni at free-electrons.com (Thomas Petazzoni)
Date: Sat, 17 Mar 2012 16:43:45 +0100
Subject: Atmel at91x40 ("EB01" eval board) resurected
In-Reply-To: <CALz2mmXcAk9ZOsAzKMbKVVJ2+Et02+Gxj_z6xSgukC5LjgJTLg@mail.gmail.com>
References: <CALz2mmXcAk9ZOsAzKMbKVVJ2+Et02+Gxj_z6xSgukC5LjgJTLg@mail.gmail.com>
Message-ID: <20120317164345.4f20beef@skate>

Hello Phil,

Le Thu, 22 Dec 2011 22:18:53 -0500,
Phil Budne <phil at ultimate.com> a ?crit :

> I decided to see if I could bring up current kernel sources under
> skyeye  (at91x40 simulation).

Very interesting, thanks. Your patches indeed allow the AT91x40 kernel
to boot under SkyEye, while the unpatched Linux kernel does not,
apparently.

Greg, it seems you are saying that the mainline kernel, unchanged,
boots under SkyEye. Could you share your kernel configuration and
SkyEye configuration?

> Runs on locally modified skyeye
>  based on skyeye-v1.2_Rel.tar (had trouble building latest release)
>  adds interrupt driven UART output
>  tweaked for programmed I/O UART input
>  fix for loading XIP data section (load at physical, not virtual address)

Would you mind publishing your changes to SkyEye? So far, I'm blocked
because of the lack of interrupt driver UART output.

Do you plan on further pushing those AT91x40 changes?

Thanks for your work,

Thomas Petazzoni
-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com


From arnd at arndb.de  Sat Mar 17 12:03:02 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 17 Mar 2012 16:03:02 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120317094217.6BA143E0908@localhost>
References: <4F22DEF2.5000807@ti.com>
 <20120315092652.GA16389@n2100.arm.linux.org.uk>
 <20120317094217.6BA143E0908@localhost>
Message-ID: <201203171603.02230.arnd@arndb.de>

On Saturday 17 March 2012, Grant Likely wrote:
> On Thu, 15 Mar 2012 09:26:52 +0000, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> > On Thu, Mar 15, 2012 at 09:22:06AM +0000, Arnd Bergmann wrote:
> > > On Thursday 15 March 2012, Nicolas Ferre wrote:
> > > > Add some basic helpers to retrieve a DMA controller device_node and the
> > > > DMA request specifications. By making DMA controllers register a generic
> > > > translation function, we allow the management of any type of DMA requests
> > > > specification.
> > > > The void * output of an of_dma_xlate() function that will be implemented
> > > > by the DMA controller can carry any type of "dma-request" argument.
> > > > 
> > > > The DMA client will search its associated DMA controller in the list and
> > > > call the registered of_dam_xlate() function to retrieve the request values.
> > > > 
> > > > One simple xlate function is provided for the "single number" type of
> > > > request binding.
> > > > 
> > > > This implementation is independent from dmaengine so it can also be used
> > > > by legacy drivers.
> > > > 
> > > > For legacy reason another API will export the DMA request number into a
> > > > Linux resource of type IORESOURCE_DMA.
> > > 
> > > This looks very good. I missed the first version of this patch, but was
> > > thinking of very similar bindings.
> > 
> > There's one issue which is concerning me - when we switch OMAP to use
> > DMA engine, it won't use numeric stuff anymore but the DMA engine way
> > of requesting a channel (match function + data).
> > 
> > How does that fit into this scheme?
> 
> Not well as the current patch set stands.  The xlate function doesn't return
> any context for the dma channel number that it returns, so the driver cannot
> figure out which DMA controller to use if there are multiple.

Shouldn't that be part of the data returned by xlate? I was under the impression
that this would be the data that you would pass into dma_request_channel, together
with a filter function that find the instance from the data.

That's why I suggested adding another helper function that would provide a
generic filter function for the dt binding doing just that.

	Arnd


From s.hauer at pengutronix.de  Sat Mar 17 12:07:44 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat, 17 Mar 2012 17:07:44 +0100
Subject: [RFC/PATCH 4/4] pxa: convert to common clock framework
In-Reply-To: <CA+gwMcdzHpGhLXXh5QTYid+rBtj8cGqFS9Te4QB3rpR9B8hXUw@mail.gmail.com>
References: <1331919483.31118.23.camel@flow>
 <CAJOA=zN2dxgjQ8EZYAwE=OLO1GLdArqy1Xf18F82en9QvFi4cw@mail.gmail.com>
 <CA+gwMcdzHpGhLXXh5QTYid+rBtj8cGqFS9Te4QB3rpR9B8hXUw@mail.gmail.com>
Message-ID: <20120317160744.GE29317@pengutronix.de>

On Sat, Mar 17, 2012 at 11:24:25AM +0100, Philipp Zabel wrote:
> Hi Mike,
> 
> On Fri, Mar 16, 2012 at 11:03 PM, Turquette, Mike <mturquette at ti.com> wrote:
> > On Fri, Mar 16, 2012 at 10:38 AM, Philipp Zabel <philipp.zabel at gmail.com> wrote:
> >> ?#define DEFINE_CK(_name, _cken, _ops) ? ? ? ? ? ? ? ? ?\
> >> -struct clk clk_##_name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> >> - ? ? ? ? ? ? ? .ops ? ?= _ops, ? ? ? ? ? ? ? ? ? ? ? ? \
> >> + ? ? ? struct clk clk_##_name; ? ? ? ? ? ? ? ? ? ? ? ? \
> >> + ? ? ? static struct clk_pxa clk_pxa_##_name = { ? ? ? \
> >> + ? ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> >> + ? ? ? ? ? ? ? ? ? ? ? .clk = &clk_##_name, ? ? ? ? ? ?\
> >> + ? ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> >> ? ? ? ? ? ? ? ?.cken ? = CKEN_##_cken, ? ? ? ? ? ? ? ? \
> >> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> >> + ? ? ? static struct clk clk_##_name = { ? ? ? ? ? ? ? \
> >> + ? ? ? ? ? ? ? .name ? = #_name, ? ? ? ? ? ? ? ? ? ? ? \
> >> + ? ? ? ? ? ? ? .ops ? ?= _ops, ? ? ? ? ? ? ? ? ? ? ? ? \
> >> + ? ? ? ? ? ? ? .hw ? ? = &clk_pxa_##_name.hw, ? ? ? ? ?\
> >> ? ? ? ?}
> >
> > Hi Philipp,
> >
> > It looks like your macros do not initialize the .parent_names,
> > .num_parents or .flags members of struct clk. ?__clk_init expects
> > those to be initialized before being called. ?The kerneldoc for
> > __clk_init states this:
> > http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=e2cce6fa604686ea3bca0496998322bacaed854d;hb=c5836d8acd9846ec1675b269d994d96a8ee44df4#l49
> 
> Yes, thank you! That was the problem.
> 
> > You can use the macros for the basic clocks types as templates. ?The
> > gate and mux macros are good to look at since those show how to handle
> > a single-parent and multi-parent clock, respectively:
> > http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=5e4312b6f5ccb1072273ce94e235874c74dd852d;hb=2508b44cd5c134691dc5d679f728bbf82af2abe0#l83
> > and
> > http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=5e4312b6f5ccb1072273ce94e235874c74dd852d;hb=2508b44cd5c134691dc5d679f728bbf82af2abe0#l148
> 
> If there was a fixed fractional divider clk element, a lot of the
> peripheral clocks could be derived from a fixed clk representing the
> 312 MHz PPLL on PXA27x (fixed -> divider -> gate), using just the
> basic clock templates.

You could try the following. It is not thoroughly tested but may be a
starting point. I need this aswell for i.MX so I will continue to work
on it soon.

Sascha

8<-------------------------------------------------------

clk: add a fixed factor clock

Having fixed factors/dividers in hardware is a common pattern, so
add a clock doing this. Currently no rate propagation is supported.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/Makefile           |    2 +-
 drivers/clk/clk-fixed-factor.c |   97 ++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-provider.h   |    4 ++
 3 files changed, 102 insertions(+), 1 deletions(-)
 create mode 100644 drivers/clk/clk-fixed-factor.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ba9a779..54f6f5b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,4 +1,4 @@
 
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
-				   clk-mux.o clk-divider.o clk-test.o
+				   clk-mux.o clk-divider.o clk-fixed-factor.o clk-test.o
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
new file mode 100644
index 0000000..7c5e1fc
--- /dev/null
+++ b/drivers/clk/clk-fixed-factor.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Standard functionality for the common clock API.
+ */
+#include <linux/module.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+struct clk_fixed_factor {
+	struct clk_hw	hw;
+	unsigned int	mult;
+	unsigned int	div;
+	char		*parent[1];
+};
+
+#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
+
+static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
+
+	return (parent_rate / fix->div) * fix->mult;
+}
+
+static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
+
+	if (prate) {
+		unsigned long best_parent;
+		best_parent = (rate / fix->mult) * fix->div;
+		*prate = __clk_round_rate(__clk_get_parent(hw->clk),
+				best_parent);
+		return (*prate / fix->div) * fix->mult;
+	} else {
+		return (__clk_get_rate(__clk_get_parent(hw->clk)) / fix->div) * fix->mult;
+	}
+}
+
+static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate)
+{
+	return 0;
+}
+
+struct clk_ops clk_fixed_factor_ops = {
+	.round_rate = clk_factor_round_rate,
+	.set_rate = clk_factor_set_rate,
+	.recalc_rate = clk_factor_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
+
+struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		unsigned int mult, unsigned int div)
+{
+	struct clk_fixed_factor *fix;
+	struct clk *clk;
+
+	fix = kmalloc(sizeof(struct clk_gate), GFP_KERNEL);
+
+	if (!fix) {
+		pr_err("%s: could not allocate gated clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_gate assignments */
+	fix->mult = mult;
+	fix->div = div;
+
+	if (parent_name) {
+		fix->parent[0] = kstrdup(parent_name, GFP_KERNEL);
+		if (!fix->parent[0])
+			goto out;
+	}
+
+	clk = clk_register(dev, name,
+			&clk_fixed_factor_ops, &fix->hw,
+			fix->parent,
+			(parent_name ? 1 : 0),
+			flags);
+	if (clk)
+		return clk;
+
+out:
+	kfree(fix->parent[0]);
+	kfree(fix);
+
+	return NULL;
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5508897..21ca2f8 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -257,6 +257,10 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_mux_flags, spinlock_t *lock);
 
+struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		unsigned int mult, unsigned int div);
+
 /**
  * clk_register - allocate a new clock, register it and return an opaque cookie
  * @dev: device that is registering this clock
-- 
1.7.9.1

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From mturquette at ti.com  Sat Mar 17 14:02:11 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Sat, 17 Mar 2012 11:02:11 -0700
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <201203170905.33191.arnd@arndb.de>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <CAJOA=zPmy7Dwzw8EOCW_+cvy2Dv=w0TPUq7Zg_s=Y0rs+v+u2w@mail.gmail.com>
 <201203170905.33191.arnd@arndb.de>
Message-ID: <CAJOA=zNVSWR6xZEfx4hioB-Q7M6PsrP9gdvJc1t+YN=QVE=83w@mail.gmail.com>

On Sat, Mar 17, 2012 at 2:05 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 16 March 2012, Turquette, Mike wrote:
>> On Fri, Mar 16, 2012 at 3:21 PM, Paul Walmsley <paul at pwsan.com> wrote:
>> > From: Paul Walmsley <paul at pwsan.com>
>> > Date: Fri, 16 Mar 2012 16:06:30 -0600
>> > Subject: [PATCH] clk: mark the common clk code as EXPERIMENTAL for now
>> >
>> > Mark the common clk code as depending on CONFIG_EXPERIMENTAL. ?The API
>> > is not well-defined and both it and the underlying mechanics are likely
>> > to need significant changes to support non-trivial uses of the rate
>> > changing code, such as DVFS with external I/O devices. ?So any platforms
>> > that switch their implementation over to this may need to revise much
>> > of their driver code and revalidate their implementations until the
>> > behavior of the code is better-defined.
>> >
>> > A good time for removing this EXPERIMENTAL designation would be after at
>> > least two platforms that do DVFS on groups of external I/O devices have
>> > ported their clock implementations over to the common clk code.
>> >
>> > Signed-off-by: Paul Walmsley <paul at pwsan.com>
>> > Cc: Mike Turquette <mturquette at ti.com>
>>
>> ACK. ?This will set some reasonable expectations while things are in flux.
>>
>> Arnd are you willing to take this in?
>
> I think it's rather pointless, because the option is not going to
> be user selectable but will get selected by the platform unless I'm
> mistaken. The platform maintainers that care already know the state
> of the framework. Also, there are no user space interfaces that we
> have to warn users about not being stable, because the framework
> is internal to the kernel.

The consensus seems to be to not set experimental.

> However, I wonder whether we need the patch below to prevent
> users from accidentally enabling COMMON_CLK on platforms that
> already provide their own implementation.
>
> ? ? ? ?Arnd
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 2eaf17e..a0a83de 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -12,7 +12,7 @@ config HAVE_MACH_CLKDEV
>
> ?menuconfig COMMON_CLK
> - ? ? ? bool "Common Clock Framework"
> + ? ? ? bool
> ? ? ? ?select HAVE_CLK_PREPARE
> ? ? ? ?---help---
> ? ? ? ? ?The common clock framework is a single definition of struct
> ? ? ? ? ?clk, useful across many platforms, as well as an

Much like experimental I'm not sure how needed this change is.  The
help section does say to leave it disabled by default, if unsure.  If
you merge it I won't object but this might be fixing an imaginary
problem.

Regards,
Mike


From mturquette at ti.com  Sat Mar 17 14:06:15 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Sat, 17 Mar 2012 11:06:15 -0700
Subject: [RFC/PATCH 4/4] pxa: convert to common clock framework
In-Reply-To: <CA+gwMcdzHpGhLXXh5QTYid+rBtj8cGqFS9Te4QB3rpR9B8hXUw@mail.gmail.com>
References: <1331919483.31118.23.camel@flow>
 <CAJOA=zN2dxgjQ8EZYAwE=OLO1GLdArqy1Xf18F82en9QvFi4cw@mail.gmail.com>
 <CA+gwMcdzHpGhLXXh5QTYid+rBtj8cGqFS9Te4QB3rpR9B8hXUw@mail.gmail.com>
Message-ID: <CAJOA=zOQ5x-idULPvM9acGNBL2onnT_+aZL9r1xUZ0MZ6jZo9A@mail.gmail.com>

On Sat, Mar 17, 2012 at 3:24 AM, Philipp Zabel <philipp.zabel at gmail.com> wrote:
> Hi Mike,
>
> On Fri, Mar 16, 2012 at 11:03 PM, Turquette, Mike <mturquette at ti.com> wrote:
>> On Fri, Mar 16, 2012 at 10:38 AM, Philipp Zabel <philipp.zabel at gmail.com> wrote:
>>> ?#define DEFINE_CK(_name, _cken, _ops) ? ? ? ? ? ? ? ? ?\
>>> -struct clk clk_##_name = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>>> - ? ? ? ? ? ? ? .ops ? ?= _ops, ? ? ? ? ? ? ? ? ? ? ? ? \
>>> + ? ? ? struct clk clk_##_name; ? ? ? ? ? ? ? ? ? ? ? ? \
>>> + ? ? ? static struct clk_pxa clk_pxa_##_name = { ? ? ? \
>>> + ? ? ? ? ? ? ? .hw = { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>>> + ? ? ? ? ? ? ? ? ? ? ? .clk = &clk_##_name, ? ? ? ? ? ?\
>>> + ? ? ? ? ? ? ? }, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>>> ? ? ? ? ? ? ? ?.cken ? = CKEN_##_cken, ? ? ? ? ? ? ? ? \
>>> + ? ? ? }; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>>> + ? ? ? static struct clk clk_##_name = { ? ? ? ? ? ? ? \
>>> + ? ? ? ? ? ? ? .name ? = #_name, ? ? ? ? ? ? ? ? ? ? ? \
>>> + ? ? ? ? ? ? ? .ops ? ?= _ops, ? ? ? ? ? ? ? ? ? ? ? ? \
>>> + ? ? ? ? ? ? ? .hw ? ? = &clk_pxa_##_name.hw, ? ? ? ? ?\
>>> ? ? ? ?}
>>
>> Hi Philipp,
>>
>> It looks like your macros do not initialize the .parent_names,
>> .num_parents or .flags members of struct clk. ?__clk_init expects
>> those to be initialized before being called. ?The kerneldoc for
>> __clk_init states this:
>> http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=e2cce6fa604686ea3bca0496998322bacaed854d;hb=c5836d8acd9846ec1675b269d994d96a8ee44df4#l49
>
> Yes, thank you! That was the problem.

Awesome!  Glad that it's working for you now without the hacks.

>> You can use the macros for the basic clocks types as templates. ?The
>> gate and mux macros are good to look at since those show how to handle
>> a single-parent and multi-parent clock, respectively:
>> http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=5e4312b6f5ccb1072273ce94e235874c74dd852d;hb=2508b44cd5c134691dc5d679f728bbf82af2abe0#l83
>> and
>> http://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=blob;f=include/linux/clk-private.h;h=5e4312b6f5ccb1072273ce94e235874c74dd852d;hb=2508b44cd5c134691dc5d679f728bbf82af2abe0#l148
>
> If there was a fixed fractional divider clk element, a lot of the
> peripheral clocks could be derived from a fixed clk representing the
> 312 MHz PPLL on PXA27x (fixed -> divider -> gate), using just the
> basic clock templates.

We need more common clock types, no question.  I have code for
fixed-dividers and a standard "dummy" clock which I think will be
critical for DT clock bindings when wiring up discrete devices.
Sascha probably has what you need in his tree already.

All of these changes are welcome additions to the framework, but I
didn't want to slow down the merge process with feature creep.  Happy
to take any patches from you in the future.

Regards,
Mike


From arnd at arndb.de  Sat Mar 17 14:33:26 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 17 Mar 2012 18:33:26 +0000
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <CAJOA=zNVSWR6xZEfx4hioB-Q7M6PsrP9gdvJc1t+YN=QVE=83w@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <201203170905.33191.arnd@arndb.de>
 <CAJOA=zNVSWR6xZEfx4hioB-Q7M6PsrP9gdvJc1t+YN=QVE=83w@mail.gmail.com>
Message-ID: <201203171833.27068.arnd@arndb.de>

On Saturday 17 March 2012, Turquette, Mike wrote:
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 2eaf17e..a0a83de 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -12,7 +12,7 @@ config HAVE_MACH_CLKDEV
> >
> >  menuconfig COMMON_CLK
> > -       bool "Common Clock Framework"
> > +       bool
> >        select HAVE_CLK_PREPARE
> >        ---help---
> >          The common clock framework is a single definition of struct
> >          clk, useful across many platforms, as well as an
> 
> Much like experimental I'm not sure how needed this change is.  The
> help section does say to leave it disabled by default, if unsure.  If
> you merge it I won't object but this might be fixing an imaginary
> problem.

Well, it doesn't have any consequences for real users, but it I think it
does for randconfig builds, which we are trying to repair currently.

	Arnd


From ccross at android.com  Sat Mar 17 15:21:34 2012
From: ccross at android.com (Colin Cross)
Date: Sat, 17 Mar 2012 12:21:34 -0700
Subject: [PATCHv2 3/5] cpuidle: add support for states that affect
 multiple cpus
In-Reply-To: <4F6483BA.8050103@ti.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
 <1331749794-8056-4-git-send-email-ccross@android.com>
 <4F6483BA.8050103@ti.com>
Message-ID: <CAMbhsRQDdXcKVp-_RNe-0i7YYLr4vKDDXqVw_eP4VsmfbFNtYg@mail.gmail.com>

On Sat, Mar 17, 2012 at 5:29 AM, Santosh Shilimkar
<santosh.shilimkar at ti.com> wrote:

<snip>

> While playing around with this version, I noticed that the
> 'alive_count' is ever incrementing which will lead to
> coupled idle state not being attempted after one CPU offline
> attempt.
>
> Fix in end of the email for the same. With it, coupled states
> continue to work with CPU online/offline transitions.
>
> Feel free to fold it into original patch. Attached
> the same in case mailer eat tabs.

<snip>

Thanks, Kevin reported this issue and I'll fix it in the next version.


From s.hauer at pengutronix.de  Sat Mar 17 16:29:31 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Sat, 17 Mar 2012 21:29:31 +0100
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <CAJOA=zNVSWR6xZEfx4hioB-Q7M6PsrP9gdvJc1t+YN=QVE=83w@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <CAJOA=zPmy7Dwzw8EOCW_+cvy2Dv=w0TPUq7Zg_s=Y0rs+v+u2w@mail.gmail.com>
 <201203170905.33191.arnd@arndb.de>
 <CAJOA=zNVSWR6xZEfx4hioB-Q7M6PsrP9gdvJc1t+YN=QVE=83w@mail.gmail.com>
Message-ID: <20120317202931.GN3852@pengutronix.de>

On Sat, Mar 17, 2012 at 11:02:11AM -0700, Turquette, Mike wrote:
> On Sat, Mar 17, 2012 at 2:05 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Friday 16 March 2012, Turquette, Mike wrote:
> >> On Fri, Mar 16, 2012 at 3:21 PM, Paul Walmsley <paul at pwsan.com> wrote:
> >> > From: Paul Walmsley <paul at pwsan.com>
> >> > Date: Fri, 16 Mar 2012 16:06:30 -0600
> >> > Subject: [PATCH] clk: mark the common clk code as EXPERIMENTAL for now
> >> >
> >> > Mark the common clk code as depending on CONFIG_EXPERIMENTAL. ?The API
> >> > is not well-defined and both it and the underlying mechanics are likely
> >> > to need significant changes to support non-trivial uses of the rate
> >> > changing code, such as DVFS with external I/O devices. ?So any platforms
> >> > that switch their implementation over to this may need to revise much
> >> > of their driver code and revalidate their implementations until the
> >> > behavior of the code is better-defined.
> >> >
> >> > A good time for removing this EXPERIMENTAL designation would be after at
> >> > least two platforms that do DVFS on groups of external I/O devices have
> >> > ported their clock implementations over to the common clk code.
> >> >
> >> > Signed-off-by: Paul Walmsley <paul at pwsan.com>
> >> > Cc: Mike Turquette <mturquette at ti.com>
> >>
> >> ACK. ?This will set some reasonable expectations while things are in flux.
> >>
> >> Arnd are you willing to take this in?
> >
> > I think it's rather pointless, because the option is not going to
> > be user selectable but will get selected by the platform unless I'm
> > mistaken. The platform maintainers that care already know the state
> > of the framework. Also, there are no user space interfaces that we
> > have to warn users about not being stable, because the framework
> > is internal to the kernel.
> 
> The consensus seems to be to not set experimental.
> 
> > However, I wonder whether we need the patch below to prevent
> > users from accidentally enabling COMMON_CLK on platforms that
> > already provide their own implementation.
> >
> > ? ? ? ?Arnd
> >
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 2eaf17e..a0a83de 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -12,7 +12,7 @@ config HAVE_MACH_CLKDEV
> >
> > ?menuconfig COMMON_CLK
> > - ? ? ? bool "Common Clock Framework"
> > + ? ? ? bool
> > ? ? ? ?select HAVE_CLK_PREPARE
> > ? ? ? ?---help---
> > ? ? ? ? ?The common clock framework is a single definition of struct
> > ? ? ? ? ?clk, useful across many platforms, as well as an
> 
> Much like experimental I'm not sure how needed this change is.  The
> help section does say to leave it disabled by default, if unsure.  If
> you merge it I won't object but this might be fixing an imaginary
> problem.

Architectures without common clock support won't build with this option
enabled (multiple definition of clk_enable etc), so I think this should
not be user visible.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From arnd at arndb.de  Sat Mar 17 17:13:30 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 17 Mar 2012 21:13:30 +0000
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <20120317202931.GN3852@pengutronix.de>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAJOA=zNVSWR6xZEfx4hioB-Q7M6PsrP9gdvJc1t+YN=QVE=83w@mail.gmail.com>
 <20120317202931.GN3852@pengutronix.de>
Message-ID: <201203172113.31122.arnd@arndb.de>

On Saturday 17 March 2012, Sascha Hauer wrote:
> On Sat, Mar 17, 2012 at 11:02:11AM -0700, Turquette, Mike wrote:
> >
> > Much like experimental I'm not sure how needed this change is.  The
> > help section does say to leave it disabled by default, if unsure.  If
> > you merge it I won't object but this might be fixing an imaginary
> > problem.
> 
> Architectures without common clock support won't build with this option
> enabled (multiple definition of clk_enable etc), so I think this should
> not be user visible.

I've applied this patch now.

	Arnd

commit c173033d154e9792b1b5059783b802f82536d48f
Author: Arnd Bergmann <arnd at arndb.de>
Date:   Sat Mar 17 21:10:51 2012 +0000

    clk: make CONFIG_COMMON_CLK invisible
    
    All platforms that use the common clk infrastructure should select
    COMMON_CLK from platform code, and on all other platforms, it must
    not be enabled, so there is no point making the option visible to
    users, and when it is visible, we break randconfig builds.
    
    Signed-off-by: Arnd Bergmann <arnd at arndb.de>

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 2eaf17e..82bcfbd 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -10,18 +10,14 @@ config HAVE_MACH_CLKDEV
 	bool
 
 menuconfig COMMON_CLK
-	bool "Common Clock Framework"
+	bool
 	select HAVE_CLK_PREPARE
 	---help---
 	  The common clock framework is a single definition of struct
 	  clk, useful across many platforms, as well as an
 	  implementation of the clock API in include/linux/clk.h.
 	  Architectures utilizing the common struct clk should select
-	  this automatically, but it may be necessary to manually select
-	  this option for loadable modules requiring the common clock
-	  framework.
-
-	  If in doubt, say "N".
+	  this option.
 
 if COMMON_CLK
 



From arnd at arndb.de  Sat Mar 17 17:16:30 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 17 Mar 2012 21:16:30 +0000
Subject: [PATCH] drivers/base: fix compiler warning in SoC export driver -
 idr should be ida
In-Reply-To: <4F6456BD.9080205@linaro.org>
References: <4F6456BD.9080205@linaro.org>
Message-ID: <201203172116.30154.arnd@arndb.de>

On Saturday 17 March 2012, Lee Jones wrote:
> 
> This fixes:
>   note: expected ?struct ida *? but argument is of type ?struct idr *?
>   warning: passing argument 1 of ?ida_pre_get? from incompatible pointer type
> 
> Reported-by: Arnd Bergman <arnd at arndb.de>
> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>
>
>  drivers/base/soc.c |    2 +-

Acked-by: Arnd Bergmann <arnd at arndb.de>

Greg, are you taking this through your tree?

	Arnd


From broonie at opensource.wolfsonmicro.com  Sat Mar 17 17:26:53 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 17 Mar 2012 21:26:53 +0000
Subject: [PATCH 0/5] MMC: mmci: Provide bindings for Device Tree
In-Reply-To: <201203161236.36088.arnd@arndb.de>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <201203152058.31398.arnd@arndb.de>
 <CACRpkdbyVXA+GxRtVL+JGPorp0ULJmeUEUZPxVxOT8W1-WmeMw@mail.gmail.com>
 <201203161236.36088.arnd@arndb.de>
Message-ID: <20120317212652.GD3315@opensource.wolfsonmicro.com>

On Fri, Mar 16, 2012 at 12:36:35PM +0000, Arnd Bergmann wrote:
> On Friday 16 March 2012, Linus Walleij wrote:
> > On Thu, Mar 15, 2012 at 9:58 PM, Arnd Bergmann <arnd at arndb.de> wrote:

> > But I guess you're after modelling the levelshifter as a regulator?

> > Basically the level shifter is a separate device has two voltage
> > inputs A and B (from other regulators) that is controlled by a
> > simple GPIO to select voltage A or B to drive the signals to
> > the card.

> > That could probably be modelled as a regulator with two
> > volategs for sure, but then we should maybe create a more
> > generic "struct level_shifter_regulator" (or whatever) for the
> > concept as a whole.

> Ok, thanks for the explanation.

I'm not sure I'd bother defining a special regulator type for this if it
is done using regulators - given that it's likely to just be a GPIO
rather than a specific driver I'm not sure it's worth worrying about how
exactly the hardware is implemented.

> > Let's page Mark about what to do with levelshifters and whether
> > they are regulators of sorts in his book.

> It does sound appealing, especially because this one could be
> done completely generically by defining a regulator that has
> a bunch of other regulators as well as a set of gpio lines as
> inputs and one output that can be used in other devices. We
> would probably only use this one together with device tree then.

It seems sensible to me - probably the existing gpio-regulator driver
can do the job, though it's not unreasonable to expect that we'll want
to support switching between variable voltage supplies at some point.
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From broonie at opensource.wolfsonmicro.com  Sat Mar 17 17:30:23 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 17 Mar 2012 21:30:23 +0000
Subject: [PATCH 2/5] MMC: mmci: Seperate ARM variants from generic code
In-Reply-To: <201203161248.15490.arnd@arndb.de>
References: <1331734803-17954-1-git-send-email-lee.jones@linaro.org>
 <201203151823.32882.arnd@arndb.de>
 <20120315203037.GA2311@n2100.arm.linux.org.uk>
 <201203161248.15490.arnd@arndb.de>
Message-ID: <20120317213022.GE3315@opensource.wolfsonmicro.com>

On Fri, Mar 16, 2012 at 12:48:15PM +0000, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Russell King - ARM Linux wrote:

> > We _do_ need a solution for GPIO-controlled voltage regulators, as these
> > are actually quite common - see the various soc-common using PCMCIA
> > drivers.

> > So I think actually a bit more thought is required here, and there's a
> > need to use some of the facilities such as regulator which are now present
> > that weren't when the driver was originally written some 9 years ago.

> Ok. Let's see what Mark has to say about this.

There's the gpio-regulator driver in mainline which should be able to
support a fairly wide range of these simple regulators, and also the
fixed voltage regulator for extremely simple cases.
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From broonie at opensource.wolfsonmicro.com  Sat Mar 17 17:42:52 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 17 Mar 2012 21:42:52 +0000
Subject: [PATCH v3 09/11] ASoC: fsl: remove the fatal error checking on
 codec-handle
In-Reply-To: <4F629D71.3050102@freescale.com>
References: <20120313234638.GY3177@opensource.wolfsonmicro.com>
 <4F6008FA.3040805@freescale.com>
 <20120314122723.GC3133@opensource.wolfsonmicro.com>
 <4F612319.50302@freescale.com>
 <20120315130253.GA6065@S2101-09.ap.freescale.net>
 <4F61F080.4090800@freescale.com>
 <20120315142115.GB6065@S2101-09.ap.freescale.net>
 <4F621D09.2080806@freescale.com>
 <20120316012711.GD6065@S2101-09.ap.freescale.net>
 <4F629D71.3050102@freescale.com>
Message-ID: <20120317214252.GF3315@opensource.wolfsonmicro.com>

On Fri, Mar 16, 2012 at 01:55:01AM +0000, Tabi Timur-B04825 wrote:

> I'm just concerned that if there's no standard way to create bindings for 
> machine drivers, we're going to end up with some kind of mess down the road.

I think that we'll be able to deal with that by adding helpers for
common cases (as has already started to happen with some of the nVidia
inspired changes like the auto_nc_pins() stuff) - approach the problem
by extracting the good practice and putting it into helpers to encourage
use.  Fortunately machine drivers are by their nature system specific so
so if they are messed up they impact a limited subset of systems.
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From mgreer at animalcreek.com  Sat Mar 17 21:22:46 2012
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Sat, 17 Mar 2012 18:22:46 -0700
Subject: [PATCH v3 0/2] arm: omap3: pm34xx.c: Some minor fixups
Message-ID: <1332033768-21986-1-git-send-email-mgreer@animalcreek.com>

I found some minor issues when looking through pm34xx.c recently
so these patches try to address them.  My apologies if they are
already fixed in another branch somewhere.  Based on latest k.o.
master branch.

Mark


From mgreer at animalcreek.com  Sat Mar 17 21:22:47 2012
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Sat, 17 Mar 2012 18:22:47 -0700
Subject: [PATCH v3 1/2] arm: omap3: pm34xx.c: Fix omap3_pm_init() error out
 paths
In-Reply-To: <1332033768-21986-1-git-send-email-mgreer@animalcreek.com>
References: <1332033768-21986-1-git-send-email-mgreer@animalcreek.com>
Message-ID: <1332033768-21986-2-git-send-email-mgreer@animalcreek.com>

From: "Mark A. Greer" <mgreer at animalcreek.com>

It appears that the error paths were overlooked when the
omap3_pm_init() routine had the prcm chain handler code
added.  Fix this by adding a goto target and reordering
the error handling code.  Also fix how the irq argument
for free_irq() is determined.

CC: Tero Kristo <t-kristo at ti.com>
Signed-off-by: Mark A. Greer <mgreer at animalcreek.com>
---
 arch/arm/mach-omap2/pm34xx.c |   16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 27fc7a2..af8d741 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -817,13 +817,13 @@ static int __init omap3_pm_init(void)
 
 	if (ret) {
 		pr_err("pm: Failed to request pm_io irq\n");
-		goto err1;
+		goto err2;
 	}
 
 	ret = pwrdm_for_each(pwrdms_setup, NULL);
 	if (ret) {
 		printk(KERN_ERR "Failed to setup powerdomains\n");
-		goto err2;
+		goto err3;
 	}
 
 	(void) clkdm_for_each(clkdms_setup, NULL);
@@ -831,7 +831,8 @@ static int __init omap3_pm_init(void)
 	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 	if (mpu_pwrdm == NULL) {
 		printk(KERN_ERR "Failed to get mpu_pwrdm\n");
-		goto err2;
+		ret = -EINVAL;
+		goto err3;
 	}
 
 	neon_pwrdm = pwrdm_lookup("neon_pwrdm");
@@ -879,14 +880,17 @@ static int __init omap3_pm_init(void)
 	}
 
 	omap3_save_scratchpad_contents();
-err1:
 	return ret;
-err2:
-	free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
+
+err3:
 	list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 		list_del(&pwrst->node);
 		kfree(pwrst);
 	}
+	free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
+err2:
+	free_irq(omap_prcm_event_to_irq("wkup"), NULL);
+err1:
 	return ret;
 }
 
-- 
1.7.9.4



From mgreer at animalcreek.com  Sat Mar 17 21:22:48 2012
From: mgreer at animalcreek.com (Mark A. Greer)
Date: Sat, 17 Mar 2012 18:22:48 -0700
Subject: [PATCH v3 2/2] arm: omap3: pm34xx.c: Replace printk() with
 appropriate pr_*()
In-Reply-To: <1332033768-21986-1-git-send-email-mgreer@animalcreek.com>
References: <1332033768-21986-1-git-send-email-mgreer@animalcreek.com>
Message-ID: <1332033768-21986-3-git-send-email-mgreer@animalcreek.com>

From: "Mark A. Greer" <mgreer at animalcreek.com>

Currently, pm34xx.c has a mix of printk() and pr_*() statements
so replace the printk() statements with the equivalent pr_*()
statements.

Signed-off-by: Mark A. Greer <mgreer at animalcreek.com>
---
 arch/arm/mach-omap2/pm34xx.c |   22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index af8d741..abc2ee0 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -166,8 +166,7 @@ static void omap3_save_secure_ram_context(void)
 		pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 		/* Following is for error tracking, it should not happen */
 		if (ret) {
-			printk(KERN_ERR "save_secure_sram() returns %08x\n",
-				ret);
+			pr_err("save_secure_sram() returns %08x\n", ret);
 			while (1)
 				;
 		}
@@ -307,7 +306,7 @@ void omap_sram_idle(void)
 		break;
 	default:
 		/* Invalid state */
-		printk(KERN_ERR "Invalid mpu state in sram_idle\n");
+		pr_err("Invalid mpu state in sram_idle\n");
 		return;
 	}
 
@@ -463,18 +462,17 @@ restore:
 	list_for_each_entry(pwrst, &pwrst_list, node) {
 		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 		if (state > pwrst->next_state) {
-			printk(KERN_INFO "Powerdomain (%s) didn't enter "
-			       "target state %d\n",
+			pr_info("Powerdomain (%s) didn't enter "
+				"target state %d\n",
 			       pwrst->pwrdm->name, pwrst->next_state);
 			ret = -1;
 		}
 		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 	}
 	if (ret)
-		printk(KERN_ERR "Could not enter target state in pm_suspend\n");
+		pr_err("Could not enter target state in pm_suspend\n");
 	else
-		printk(KERN_INFO "Successfully put all powerdomains "
-		       "to target state\n");
+		pr_info("Successfully put all powerdomains to target state\n");
 
 	return ret;
 }
@@ -822,7 +820,7 @@ static int __init omap3_pm_init(void)
 
 	ret = pwrdm_for_each(pwrdms_setup, NULL);
 	if (ret) {
-		printk(KERN_ERR "Failed to setup powerdomains\n");
+		pr_err("Failed to setup powerdomains\n");
 		goto err3;
 	}
 
@@ -830,7 +828,7 @@ static int __init omap3_pm_init(void)
 
 	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 	if (mpu_pwrdm == NULL) {
-		printk(KERN_ERR "Failed to get mpu_pwrdm\n");
+		pr_err("Failed to get mpu_pwrdm\n");
 		ret = -EINVAL;
 		goto err3;
 	}
@@ -865,8 +863,8 @@ static int __init omap3_pm_init(void)
 		omap3_secure_ram_storage =
 			kmalloc(0x803F, GFP_KERNEL);
 		if (!omap3_secure_ram_storage)
-			printk(KERN_ERR "Memory allocation failed when"
-					"allocating for secure sram context\n");
+			pr_err("Memory allocation failed when "
+			       "allocating for secure sram context\n");
 
 		local_irq_disable();
 		local_fiq_disable();
-- 
1.7.9.4



From javier at dowhile0.org  Sat Mar 17 22:43:14 2012
From: javier at dowhile0.org (Javier Martinez Canillas)
Date: Sun, 18 Mar 2012 03:43:14 +0100
Subject: [PATCH 1/2] omap3: nand: Make board_onenand_init() visible to board
 code
Message-ID: <1332038595-15810-1-git-send-email-javier@dowhile0.org>

board_onenand_init() and board_nand_init() initialization functions are
used to initialize OneNAND and NAND memories respectively. But only
board_nand_init() was visible to be used from board code. This patch makes
possible to initialize a OneNAND flash memory within platform code.

Signed-off-by: Javier Martinez Canillas <javier at dowhile0.org>
---
 arch/arm/mach-omap2/board-flash.c |    4 ++--
 arch/arm/mach-omap2/board-flash.h |   11 +++++++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 0349fd2..70a81f9 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -87,7 +87,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
 	.dma_channel	= -1,   /* disable DMA in OMAP OneNAND driver */
 };
 
-static void
+void
 __init board_onenand_init(struct mtd_partition *onenand_parts,
 				u8 nr_parts, u8 cs)
 {
@@ -98,7 +98,7 @@ __init board_onenand_init(struct mtd_partition *onenand_parts,
 	gpmc_onenand_init(&board_onenand_data);
 }
 #else
-static void
+void
 __init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
 {
 }
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index d25503a..c44b70d 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -47,3 +47,14 @@ static inline void board_nand_init(struct mtd_partition *nand_parts,
 {
 }
 #endif
+
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+		defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+extern void board_onenand_init(struct mtd_partition *nand_parts,
+					u8 nr_parts, u8 cs);
+#else
+static inline void board_onenand_init(struct mtd_partition *nand_parts,
+					u8 nr_parts, u8 cs)
+{
+}
+#endif
-- 
1.7.7.6



From javier at dowhile0.org  Sat Mar 17 22:43:15 2012
From: javier at dowhile0.org (Javier Martinez Canillas)
Date: Sun, 18 Mar 2012 03:43:15 +0100
Subject: [PATCH 2/2] OMAP3: igep0020: Add support for Micron NAND Flash
 storage memory
In-Reply-To: <1332038595-15810-1-git-send-email-javier@dowhile0.org>
References: <1332038595-15810-1-git-send-email-javier@dowhile0.org>
Message-ID: <1332038595-15810-2-git-send-email-javier@dowhile0.org>

IGEP-based boards can have two different flash memories, a OneNAND or
a NAND device. The boot configuration pins (sys_boot) are used to
specify which memory is available.

Also, this patch removes unnecesary code for registering the OneNAND.

Signed-off-by: Javier Martinez Canillas <javier at dowhile0.org>
---
 arch/arm/mach-omap2/board-igep0020.c |   81 +++++++++++++++------------------
 1 files changed, 37 insertions(+), 44 deletions(-)

diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index e558800..59b0164 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -24,6 +24,8 @@
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
 
+#include <linux/mtd/nand.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
@@ -39,6 +41,8 @@
 #include "hsmmc.h"
 #include "sdram-numonyx-m65kxxxxam.h"
 #include "common-board-devices.h"
+#include "board-flash.h"
+#include "control.h"
 
 #define IGEP2_SMSC911X_CS       5
 #define IGEP2_SMSC911X_GPIO     176
@@ -60,6 +64,10 @@
 #define IGEP3_GPIO_LED1_RED	16
 #define IGEP3_GPIO_USBH_NRESET  183
 
+#define IGEP_SYSBOOT_MASK           0x1f
+#define IGEP_SYSBOOT_NAND           0x0f
+#define IGEP_SYSBOOT_ONENAND        0x10
+
 /*
  * IGEP2 Hardware Revision Table
  *
@@ -110,8 +118,10 @@ static void __init igep2_get_revision(void)
 	gpio_free(IGEP2_GPIO_LED1_RED);
 }
 
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
-	defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+#if defined(CONFIG_MTD_ONENAND_OMAP2) ||		\
+	defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) ||	\
+	defined(CONFIG_MTD_NAND_OMAP2) ||		\
+	defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 
 #define ONENAND_MAP             0x20000000
 
@@ -123,7 +133,7 @@ static void __init igep2_get_revision(void)
  * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
  */
 
-static struct mtd_partition igep_onenand_partitions[] = {
+static struct mtd_partition igep_flash_partitions[] = {
 	{
 		.name           = "X-Loader",
 		.offset         = 0,
@@ -151,50 +161,33 @@ static struct mtd_partition igep_onenand_partitions[] = {
 	},
 };
 
-static struct omap_onenand_platform_data igep_onenand_data = {
-	.parts = igep_onenand_partitions,
-	.nr_parts = ARRAY_SIZE(igep_onenand_partitions),
-	.dma_channel	= -1,	/* disable DMA in OMAP OneNAND driver */
-};
-
-static struct platform_device igep_onenand_device = {
-	.name		= "omap2-onenand",
-	.id		= -1,
-	.dev = {
-		.platform_data = &igep_onenand_data,
-	},
-};
+static inline u32 igep_get_sysboot_value(void)
+{
+	return omap_ctrl_readl(OMAP343X_CONTROL_STATUS) & IGEP_SYSBOOT_MASK;
+}
 
 static void __init igep_flash_init(void)
 {
-	u8 cs = 0;
-	u8 onenandcs = GPMC_CS_NUM + 1;
-
-	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-		u32 ret;
-		ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-		/* Check if NAND/oneNAND is configured */
-		if ((ret & 0xC00) == 0x800)
-			/* NAND found */
-			pr_err("IGEP: Unsupported NAND found\n");
-		else {
-			ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
-			if ((ret & 0x3F) == (ONENAND_MAP >> 24))
-				/* ONENAND found */
-				onenandcs = cs;
-		}
-	}
-
-	if (onenandcs > GPMC_CS_NUM) {
-		pr_err("IGEP: Unable to find configuration in GPMC\n");
-		return;
-	}
-
-	igep_onenand_data.cs = onenandcs;
-
-	if (platform_device_register(&igep_onenand_device) < 0)
-		pr_err("IGEP: Unable to register OneNAND device\n");
+	u32 mux;
+	mux = igep_get_sysboot_value();
+
+	if (mux == IGEP_SYSBOOT_NAND) {
+#if defined(CONFIG_MTD_NAND_OMAP2) || \
+	defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+		pr_info("IGEP: initializing NAND memory device\n");
+		board_nand_init(igep_flash_partitions,
+				ARRAY_SIZE(igep_flash_partitions),
+				0, NAND_BUSWIDTH_16);
+#endif
+	} else if (mux == IGEP_SYSBOOT_ONENAND) {
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+	defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+		pr_info("IGEP: initializing OneNAND memory device\n");
+		board_onenand_init(igep_flash_partitions,
+				   ARRAY_SIZE(igep_flash_partitions), 0);
+#endif
+	} else
+		pr_err("IGEP: Flash: unsupported sysboot sequence found\n");
 }
 
 #else
-- 
1.7.7.6



From javier at dowhile0.org  Sat Mar 17 23:30:29 2012
From: javier at dowhile0.org (Javier Martinez Canillas)
Date: Sun, 18 Mar 2012 04:30:29 +0100
Subject: [PATCH v2 2/2] OMAP3: igep0020: Add support for Micron NAND Flash
 storage memory
Message-ID: <1332041429-23978-1-git-send-email-javier@dowhile0.org>

IGEP-based boards can have two different flash memories, a OneNAND or
a NAND device. The boot configuration pins (sys_boot) are used to
specify which memory is available.

Also, this patch removes unnecesary code for registering the OneNAND.

Signed-off-by: Javier Martinez Canillas <javier at dowhile0.org>
---

v2: It's not necessary to guard board_nand_init() and board_onenand_init()
    with #ifdef since they are defined as empty functions in board-flash.c

 arch/arm/mach-omap2/board-igep0020.c |   75 ++++++++++++++--------------------
 1 files changed, 31 insertions(+), 44 deletions(-)

diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index e558800..dbd13b2 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -24,6 +24,8 @@
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
 
+#include <linux/mtd/nand.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
@@ -39,6 +41,8 @@
 #include "hsmmc.h"
 #include "sdram-numonyx-m65kxxxxam.h"
 #include "common-board-devices.h"
+#include "board-flash.h"
+#include "control.h"
 
 #define IGEP2_SMSC911X_CS       5
 #define IGEP2_SMSC911X_GPIO     176
@@ -60,6 +64,10 @@
 #define IGEP3_GPIO_LED1_RED	16
 #define IGEP3_GPIO_USBH_NRESET  183
 
+#define IGEP_SYSBOOT_MASK           0x1f
+#define IGEP_SYSBOOT_NAND           0x0f
+#define IGEP_SYSBOOT_ONENAND        0x10
+
 /*
  * IGEP2 Hardware Revision Table
  *
@@ -110,8 +118,10 @@ static void __init igep2_get_revision(void)
 	gpio_free(IGEP2_GPIO_LED1_RED);
 }
 
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
-	defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+#if defined(CONFIG_MTD_ONENAND_OMAP2) ||		\
+	defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) ||	\
+	defined(CONFIG_MTD_NAND_OMAP2) ||		\
+	defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 
 #define ONENAND_MAP             0x20000000
 
@@ -123,7 +133,7 @@ static void __init igep2_get_revision(void)
  * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
  */
 
-static struct mtd_partition igep_onenand_partitions[] = {
+static struct mtd_partition igep_flash_partitions[] = {
 	{
 		.name           = "X-Loader",
 		.offset         = 0,
@@ -151,50 +161,27 @@ static struct mtd_partition igep_onenand_partitions[] = {
 	},
 };
 
-static struct omap_onenand_platform_data igep_onenand_data = {
-	.parts = igep_onenand_partitions,
-	.nr_parts = ARRAY_SIZE(igep_onenand_partitions),
-	.dma_channel	= -1,	/* disable DMA in OMAP OneNAND driver */
-};
-
-static struct platform_device igep_onenand_device = {
-	.name		= "omap2-onenand",
-	.id		= -1,
-	.dev = {
-		.platform_data = &igep_onenand_data,
-	},
-};
+static inline u32 igep_get_sysboot_value(void)
+{
+	return omap_ctrl_readl(OMAP343X_CONTROL_STATUS) & IGEP_SYSBOOT_MASK;
+}
 
 static void __init igep_flash_init(void)
 {
-	u8 cs = 0;
-	u8 onenandcs = GPMC_CS_NUM + 1;
-
-	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-		u32 ret;
-		ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-		/* Check if NAND/oneNAND is configured */
-		if ((ret & 0xC00) == 0x800)
-			/* NAND found */
-			pr_err("IGEP: Unsupported NAND found\n");
-		else {
-			ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
-			if ((ret & 0x3F) == (ONENAND_MAP >> 24))
-				/* ONENAND found */
-				onenandcs = cs;
-		}
-	}
-
-	if (onenandcs > GPMC_CS_NUM) {
-		pr_err("IGEP: Unable to find configuration in GPMC\n");
-		return;
-	}
-
-	igep_onenand_data.cs = onenandcs;
-
-	if (platform_device_register(&igep_onenand_device) < 0)
-		pr_err("IGEP: Unable to register OneNAND device\n");
+	u32 mux;
+	mux = igep_get_sysboot_value();
+
+	if (mux == IGEP_SYSBOOT_NAND) {
+		pr_info("IGEP: initializing NAND memory device\n");
+		board_nand_init(igep_flash_partitions,
+				ARRAY_SIZE(igep_flash_partitions),
+				0, NAND_BUSWIDTH_16);
+	} else if (mux == IGEP_SYSBOOT_ONENAND) {
+		pr_info("IGEP: initializing OneNAND memory device\n");
+		board_onenand_init(igep_flash_partitions,
+				   ARRAY_SIZE(igep_flash_partitions), 0);
+	} else
+		pr_err("IGEP: Flash: unsupported sysboot sequence found\n");
 }
 
 #else
-- 
1.7.7.6



From shawn.guo at linaro.org  Sun Mar 18 01:43:32 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 18 Mar 2012 13:43:32 +0800
Subject: [RFC/PATCH 4/4] pxa: convert to common clock framework
In-Reply-To: <1331919483.31118.23.camel@flow>
References: <1331919483.31118.23.camel@flow>
Message-ID: <20120318054329.GA29638@S2101-09.ap.freescale.net>

Your patch #2 is trying to avoid the layering violation by separating
static clock definitions and from clk_ops implementations into
different files.  But ...

On Fri, Mar 16, 2012 at 06:38:03PM +0100, Philipp Zabel wrote:
...
> diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
> index a3585a2..7c04f9b 100644
> --- a/arch/arm/mach-pxa/clock.h
> +++ b/arch/arm/mach-pxa/clock.h
> @@ -1,80 +1,106 @@
>  #include <linux/clkdev.h>
> +#include <linux/clk-private.h>

... This is what I read from clk-private.h.

/*
 * WARNING: Do not include clk-private.h from any file that implements struct
 * clk_ops.  Doing so is a layering violation!
 *
 * ...
 */

And you include it in arch/arm/mach-pxa/clock.h which in turn is being
included by the pxa clock files implementing clk_ops.

> +#include <linux/clk-provider.h>
>  #include <linux/syscore_ops.h>

Regards,
Shawn


From santosh.shilimkar at ti.com  Sun Mar 18 03:18:22 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Sun, 18 Mar 2012 12:48:22 +0530
Subject: [PATCHv2 3/5] cpuidle: add support for states that affect
 multiple cpus
In-Reply-To: <CAMbhsRQDdXcKVp-_RNe-0i7YYLr4vKDDXqVw_eP4VsmfbFNtYg@mail.gmail.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
 <1331749794-8056-4-git-send-email-ccross@android.com>
 <4F6483BA.8050103@ti.com>
 <CAMbhsRQDdXcKVp-_RNe-0i7YYLr4vKDDXqVw_eP4VsmfbFNtYg@mail.gmail.com>
Message-ID: <CAMQu2gz11nwDy2nzFDTL7XaLcf4ULqUDWVOEzAQLD9JJ8Y=JYA@mail.gmail.com>

On Sun, Mar 18, 2012 at 12:51 AM, Colin Cross <ccross at android.com> wrote:
> On Sat, Mar 17, 2012 at 5:29 AM, Santosh Shilimkar
> <santosh.shilimkar at ti.com> wrote:
>
> <snip>
>
>> While playing around with this version, I noticed that the
>> 'alive_count' is ever incrementing which will lead to
>> coupled idle state not being attempted after one CPU offline
>> attempt.
>>
>> Fix in end of the email for the same. With it, coupled states
>> continue to work with CPU online/offline transitions.
>>
>> Feel free to fold it into original patch. Attached
>> the same in case mailer eat tabs.
>
> <snip>
>
> Thanks, Kevin reported this issue and I'll fix it in the next version.
 Ahh... I see comments from Kevin now. Some how I missed it
otherwise would have saved me few minutes of debug.

Regards
Santosh


From grant.likely at secretlab.ca  Sun Mar 18 05:08:41 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 18 Mar 2012 09:08:41 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203171603.02230.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com>
 <20120315092652.GA16389@n2100.arm.linux.org.uk>
 <20120317094217.6BA143E0908@localhost> <201203171603.02230.arnd@arndb.de>
Message-ID: <20120318090841.DC4973E060A@localhost>

On Sat, 17 Mar 2012 16:03:02 +0000, Arnd Bergmann <arnd at arndb.de> wrote:
> On Saturday 17 March 2012, Grant Likely wrote:
> > On Thu, 15 Mar 2012 09:26:52 +0000, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> > > On Thu, Mar 15, 2012 at 09:22:06AM +0000, Arnd Bergmann wrote:
> > > > On Thursday 15 March 2012, Nicolas Ferre wrote:
> > > > > Add some basic helpers to retrieve a DMA controller device_node and the
> > > > > DMA request specifications. By making DMA controllers register a generic
> > > > > translation function, we allow the management of any type of DMA requests
> > > > > specification.
> > > > > The void * output of an of_dma_xlate() function that will be implemented
> > > > > by the DMA controller can carry any type of "dma-request" argument.
> > > > > 
> > > > > The DMA client will search its associated DMA controller in the list and
> > > > > call the registered of_dam_xlate() function to retrieve the request values.
> > > > > 
> > > > > One simple xlate function is provided for the "single number" type of
> > > > > request binding.
> > > > > 
> > > > > This implementation is independent from dmaengine so it can also be used
> > > > > by legacy drivers.
> > > > > 
> > > > > For legacy reason another API will export the DMA request number into a
> > > > > Linux resource of type IORESOURCE_DMA.
> > > > 
> > > > This looks very good. I missed the first version of this patch, but was
> > > > thinking of very similar bindings.
> > > 
> > > There's one issue which is concerning me - when we switch OMAP to use
> > > DMA engine, it won't use numeric stuff anymore but the DMA engine way
> > > of requesting a channel (match function + data).
> > > 
> > > How does that fit into this scheme?
> > 
> > Not well as the current patch set stands.  The xlate function doesn't return
> > any context for the dma channel number that it returns, so the driver cannot
> > figure out which DMA controller to use if there are multiple.
> 
> Shouldn't that be part of the data returned by xlate? I was under the impression
> that this would be the data that you would pass into dma_request_channel, together
> with a filter function that find the instance from the data.

Yes, that's my point.  The patch as it is currently written doesn't do
what it needs to.

g.



From thierry.reding at avionic-design.de  Sun Mar 18 05:22:41 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Sun, 18 Mar 2012 10:22:41 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120317104751.4F00E3E0910@localhost>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <201203150922.06379.arnd@arndb.de>
 <20120315102736.GA25371@avionic-0098.adnet.avionic-design.de>
 <20120317104751.4F00E3E0910@localhost>
Message-ID: <20120318092241.GA23839@avionic-0098.mockup.avionic-design.de>

* Grant Likely wrote:
> On Thu, 15 Mar 2012 11:27:36 +0100, Thierry Reding <thierry.reding at avionic-design.de> wrote:
> > So if we decide to explicitly allow specifying names, then we can always add
> > a pwm-names property (or <name>-pwm-names respectively) to use as label and
> > fallback to the user OF device node name if that property is not present.
> 
> After implementing both schemes (ie. interrupts+interrupt-names && [*-]gpios)
> I definitely prefer the fixed property name plus a separate names property.
> It is easier to use common code with that scheme, and easier to statically
> check for correctness.

Okay. Would everyone be happy with "pwms" and "pwm-names"?

Thierry
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From B29397 at freescale.com  Sun Mar 18 08:06:37 2012
From: B29397 at freescale.com (Chen Peter-B29397)
Date: Sun, 18 Mar 2012 12:06:37 +0000
Subject: Want to Get Suggestion for MX28 USB Submisson
In-Reply-To: <CAOMZO5A1D8SLp=UpFK0dfjaaeJK+R4yUjXbRm=xhOjfEPdzEtA@mail.gmail.com>
References: <35AB98346D25394A9354ED89C4D76587225CFF@039-SN1MPN1-002.039d.mgd.msft.net>
 <201202041117.48190.marek.vasut@gmail.com>
 <F281D0F91ED19E4D8E63A7504E8A6498033336@039-SN2MPN1-021.039d.mgd.msft.net>
 <201202100447.14248.marek.vasut@gmail.com>
 <CAOMZO5C3Y3kP5k_CKkCVMVdDem2T82g6F3uL=8GCVfNKHpdymA@mail.gmail.com>
 <F281D0F91ED19E4D8E63A7504E8A6498093839@039-SN2MPN1-021.039d.mgd.msft.net>
 <CAOMZO5A1D8SLp=UpFK0dfjaaeJK+R4yUjXbRm=xhOjfEPdzEtA@mail.gmail.com>
Message-ID: <F281D0F91ED19E4D8E63A7504E8A6498096381@039-SN2MPN1-021.039d.mgd.msft.net>

 
> On Wed, Mar 14, 2012 at 12:30 AM, Chen Peter-B29397
> <B29397 at freescale.com> wrote:
> 
> > According to sascha's suggestion, it is better to re-submit after we
> have
> > a generic USB PHY Layer in mainline.
> >
> > Currently, Heikki's split PHY from OTG structure patches have mainlined,
> > next step is to submit a generic USB PHY driver.
> 
> Just for my understanding: is there someone working on this generic
> USB PHY driver?

Add related people.

I have much internal stuff on hands now, and have not bandwidth to do it right now. 

From joro at 8bytes.org  Sun Mar 18 09:27:46 2012
From: joro at 8bytes.org (Joerg Roedel)
Date: Sun, 18 Mar 2012 14:27:46 +0100
Subject: [PATCH v12 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
In-Reply-To: <4F63A6F6.9050506@samsung.com>
References: <000201cd0286$2e6fbb40$8b4f31c0$%cho@samsung.com>
 <20120315111227.GA2384@amd.com> <4F61FF1D.5000502@samsung.com>
 <4F630841.2070307@linaro.org> <4F63A6F6.9050506@samsung.com>
Message-ID: <20120318132746.GL26973@8bytes.org>

On Fri, Mar 16, 2012 at 01:47:50PM -0700, Kukjin Kim wrote:
> Anyway Joerg, how do you want to handle this? Do you want to pick up  
> 1/2/3 all of them in your tree? If so, 2nd patch should be on top of  
> some samsung topic stuff.

Since patch 2 only applies to the Samsung tree, it is best to carry
this in your tree for merging. Feel free to add my Acked-by to patch 3.
But any further patches for the Exynos IOMMU drivers should go through
my tree after it is merged.


Thanks,

	Joerg



From shawn.guo at linaro.org  Sun Mar 18 09:46:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 18 Mar 2012 21:46:26 +0800
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <1331878280-2758-3-git-send-email-mturquette@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
Message-ID: <20120318134623.GB29638@S2101-09.ap.freescale.net>

Reading the documentation of function clk_set_rate(), I'm not sure
it exactly matches what the code does.

If there is mismatch, it might be worth sending an incremental patch
to update the documentation and avoid the confusion?

On Thu, Mar 15, 2012 at 11:11:19PM -0700, Mike Turquette wrote:
> +/**
> + * clk_set_rate - specify a new rate for clk
> + * @clk: the clk whose rate is being changed
> + * @rate: the new rate for clk
> + *
> + * In the simplest case clk_set_rate will only change the rate of clk.
> + *
> + * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call
> + * will fail; only when the clk is disabled will it be able to change
> + * its rate.
> + *
> + * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to
> + * recursively propagate up to clk's parent; whether or not this happens
> + * depends on the outcome of clk's .round_rate implementation.  If
> + * *parent_rate is 0 after calling .round_rate then upstream parent

Might "*parent_rate is not changed" be more accurate?

> + * propagation is ignored.  If *parent_rate comes back with a new rate
> + * for clk's parent then we propagate up to clk's parent and set it's
> + * rate.  Upward propagation will continue until either a clk does not
> + * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting
> + * changes to clk's parent_rate.

> + * If there is a failure during upstream
> + * propagation then clk_set_rate will unwind and restore each clk's rate
> + * that had been successfully changed.  Afterwards a rate change abort
> + * notification will be propagated downstream, starting from the clk
> + * that failed.

I'm not sure this part still matches the code.

> + *
> + * At the end of all of the rate setting, clk_set_rate internally calls
> + * __clk_recalc_rates and propagates the rate changes downstream,

I do not see __clk_recalc_rates is called by clk_set_rate in any way.

Regards,
Shawn

> + * starting from the highest clk whose rate was changed.  This has the
> + * added benefit of propagating post-rate change notifiers.
> + *
> + * Note that while post-rate change and rate change abort notifications
> + * are guaranteed to be sent to a clk only once per call to
> + * clk_set_rate, pre-change notifications will be sent for every clk
> + * whose rate is changed.  Stacking pre-change notifications is noisy
> + * for the drivers subscribed to them, but this allows drivers to react
> + * to intermediate clk rate changes up until the point where the final
> + * rate is achieved at the end of upstream propagation.
> + *
> + * Returns 0 on success, -EERROR otherwise.
> + */


From shawn.guo at linaro.org  Sun Mar 18 10:07:10 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 18 Mar 2012 22:07:10 +0800
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <1331878280-2758-3-git-send-email-mturquette@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
Message-ID: <20120318140707.GC29638@S2101-09.ap.freescale.net>

Another trivial comment.  But if there is an incremental patch, maybe
consider to include it.

On Thu, Mar 15, 2012 at 11:11:19PM -0700, Mike Turquette wrote:
...
> +#ifdef CONFIG_COMMON_CLK_DISABLE_UNUSED
> +static int clk_disable_unused(void)
> +{
> +	struct clk *clk;
> +	struct hlist_node *tmp;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
> +		clk_disable_unused_subtree(clk);
> +
> +	hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
> +		clk_disable_unused_subtree(clk);
> +
> +	mutex_unlock(&prepare_lock);
> +
> +	return 0;
> +}
> +late_initcall(clk_disable_unused);
> +#else
> +static inline int clk_disable_unused(struct clk *clk) { return 0; }

This #else block seems completely unnecessary to me.

> +#endif /* CONFIG_COMMON_CLK_DISABLE_UNUSED */

-- 
Regards,
Shawn


From arnd at arndb.de  Sun Mar 18 11:10:14 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 18 Mar 2012 15:10:14 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120318092241.GA23839@avionic-0098.mockup.avionic-design.de>
References: <4F22DEF2.5000807@ti.com> <20120317104751.4F00E3E0910@localhost>
 <20120318092241.GA23839@avionic-0098.mockup.avionic-design.de>
Message-ID: <201203181510.14428.arnd@arndb.de>

On Sunday 18 March 2012, Thierry Reding wrote:
> Not enough information to check signature validity.  Show Details
>   * Grant Likely wrote:
> > On Thu, 15 Mar 2012 11:27:36 +0100, Thierry Reding <thierry.reding at avionic-design.de> wrote:
> > > So if we decide to explicitly allow specifying names, then we can always add
> > > a pwm-names property (or <name>-pwm-names respectively) to use as label and
> > > fallback to the user OF device node name if that property is not present.
> > 
> > After implementing both schemes (ie. interrupts+interrupt-names && [*-]gpios)
> > I definitely prefer the fixed property name plus a separate names property.
> > It is easier to use common code with that scheme, and easier to statically
> > check for correctness.
> 
> Okay. Would everyone be happy with "pwms" and "pwm-names"?

Sounds good. I would have suggested "pwm", but the plural also works since
that is used for "interrupts", too.

	Arnd


From olof at lixom.net  Sun Mar 18 13:27:10 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 18 Mar 2012 10:27:10 -0700
Subject: [PATCH] arm/tegra: pcie: fix return value of function
In-Reply-To: <4F5FA1BB.5050002@wwwdotorg.org>
References: <CAOesGMi0aqCjLsJ5wWXwFVQL2T8wtUuE14rFZ9h7NKHXcWAoqQ@mail.gmail.com>
 <1331617587-10714-1-git-send-email-mad_soft@inbox.ru>
 <4F5FA1BB.5050002@wwwdotorg.org>
Message-ID: <20120318172710.GA24110@quad.lixom.net>

On Tue, Mar 13, 2012 at 01:36:27PM -0600, Stephen Warren wrote:
> On 03/12/2012 11:46 PM, Dmitry Artamonow wrote:
> > In previous patch (arm/tegra: add timeout to PCIe PLL lock detection loop)
> > tegra_pcie_enable_controller() function type has been changed from
> > void to int, but the last return statement wasn't converted, so
> > function returns undefined value. Fix it.
> > 
> > Also while at it, address couple of minor concerns raised by reviewers:
> > use usleep_range for delay, and lower the value of timeout to 300ms
> > to be consistent with Nvidia Vibrante kernel.
> > 
> > Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>
> 
> Acked-by: Stephen Warren <swarren at wwwdotorg.org>

Thanks, applied to for-3.4/cleanups-and-fixes


-Olof


From olof at lixom.net  Sun Mar 18 13:31:59 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 18 Mar 2012 10:31:59 -0700
Subject: [PATCH 00/11] ARM: tegra: Add PCIe device tree support
In-Reply-To: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120318173159.GB24110@quad.lixom.net>

On Thu, Mar 08, 2012 at 03:51:20PM +0100, Thierry Reding wrote:
> This patch series adds support for device tree based probing of the PCIe
> controller found on Tegra SoCs.
> 
> Patches 1 and 2 have already been posted by Grant and Mark respectively
> but I've included them here for reference. Both patches are dependencies
> for the subsequent patches.
> 
> Patches 3, 4 and 5 add support for obtaining the regulators required to
> power the PCIe controller from the device tree. Patches 6 and 7 are
> required to make some common PCI functions available after the init
> phase because the deferred probing will postpone the probing of the PCIe
> controller driver until that point.
> 
> Patches 8 and 9 make the PCIe controller code available as a driver and
> add the corresponding platform devices to the boards that enable PCIe
> (Harmony and TrimSlice). Patch 10 adds MSI support and patch 11 finally
> adds a device tree binding with documentation.
> 
> The code in patch 10 (MSI support) is based on the Vibrante kernel and I
> wasn't able to get a proper Signed-off-by or even copyright information.
> Perhaps somebody at NVIDIA can find out?

Hi,

This patch series looks good to me, but I'm out of time to stage it for
3.4. Stephen is taking over lead maintainership for 3.5 and forward,
so I'll let him pick it up for that release.


-Olof



From olof at lixom.net  Sun Mar 18 13:36:06 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 18 Mar 2012 10:36:06 -0700
Subject: [PATCH v3 4/5] ARM: tegra: select USB_ULPI if USB is selected
In-Reply-To: <1330727160-11242-1-git-send-email-alan@signal11.us>
References: <1330727075-10974-1-git-send-email-alan@signal11.us>
 <1330727160-11242-1-git-send-email-alan@signal11.us>
Message-ID: <20120318173606.GA24327@quad.lixom.net>

On Fri, Mar 02, 2012 at 05:26:00PM -0500, Alan Ott wrote:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> Automatically select USB_ULPI if USB is enabled on Tegra.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Alan Ott <alan at signal11.us>

Thanks, applied. I think this was the last outstanding patch that I had not yet
applied. Since there had been some slight confusion with v2 vs v3, please check
the contents of the tegra for-next branch and make sure it contains what you
would expect it to.

Thanks!


-Olof


From olof at lixom.net  Sun Mar 18 13:44:11 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 18 Mar 2012 10:44:11 -0700
Subject: [PATCH] ARM: tegra: update main repo and add patchwork
Message-ID: <1332092651-25346-1-git-send-email-olof@lixom.net>

Stephen is taking over the main tegra repo, so change the entry to point at his tree on kernel.org

Also, document the patchwork URL.

Signed-off-by: Olof Johansson <olof at lixom.net>
---


Arnd, I applied the previous Tegra maintainer patch to next/maintainers
directly, so this should just go on top of there.


Thanks!


-Olof


 MAINTAINERS |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 187d855..a23a635 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6515,7 +6515,8 @@ M:	Colin Cross <ccross at android.com>
 M:	Olof Johansson <olof at lixom.net>
 M:	Stephen Warren <swarren at wwwdotorg.org>
 L:	linux-tegra at vger.kernel.org
-T:	git git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
+Q:	http://patchwork.ozlabs.org/project/linux-tegra/list/
+T:	git git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git
 S:	Supported
 F:	arch/arm/mach-tegra
 
-- 
1.7.10.rc1



From olof at lixom.net  Sun Mar 18 13:50:20 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 18 Mar 2012 10:50:20 -0700
Subject: [GIT PULL] Refresh of board branch for tegra
Message-ID: <CAOesGMh9hp12fwNQ4QwStg3yc-DXnixj4wHNOjO1rHeX8hJnxQ@mail.gmail.com>

Hi Arnd,

One more patch has been added to the board branch, just a defconfig
update to mostly include some of the new drivers that have been added
lately, etc.


The following changes since commit c5444f39620b2b7801eb1997c41befdc8bcf78ea:

  ARM: tegra: match SoC name not board name in DT board files
(2012-03-04 10:41:19 -0800)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git for-3.4/boards

for you to fetch changes up to 0a25893597dfbad08aff833bdefac2fe5b31aabd:

  ARM: tegra: update defconfig (2012-03-07 14:38:49 -0800)

----------------------------------------------------------------
Stephen Warren (1):
      ARM: tegra: update defconfig

 arch/arm/configs/tegra_defconfig |   33 ++++++++++++++++++++++-----------
 1 file changed, 22 insertions(+), 11 deletions(-)


From olof at lixom.net  Sun Mar 18 13:51:42 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 18 Mar 2012 10:51:42 -0700
Subject: [GIT PULL] A few more non-critical fixes for tegra
Message-ID: <CAOesGMhELxtTnVMzADM01RhsPcGt7ciqLh-h0+xNwUg8MGCo1Q@mail.gmail.com>

Hi Arnd,

A few more patches have been added to the cleanup-and-fixes branch for
tegra, see below. Please pull on top of current tegra/cleanups
contents!


Thanks,

-Olof


The following changes since commit f6a1ba67362fe78a1ec81c355ee638c70689b5d7:

  ARM: tegra: Enable CPUIdle on Tegra20 (2012-03-04 11:17:17 -0800)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git
for-3.4/cleanup-and-fixes

for you to fetch changes up to 279b658525abd06645938fb607860de42c4cf31e:

  ARM: tegra: select USB_ULPI if USB is selected (2012-03-18 10:34:32 -0700)

----------------------------------------------------------------
Arnd Bergmann (1):
      ARM: tegra: select USB_ULPI if USB is selected

Dmitry Artamonow (3):
      arm/tegra: fix harmony pinmux for PCIe
      arm/tegra: add timeout to PCIe PLL lock detection loop
      arm/tegra: pcie: fix return value of function

 arch/arm/mach-tegra/Kconfig                |    4 ++--
 arch/arm/mach-tegra/board-harmony-pinmux.c |    6 +++---
 arch/arm/mach-tegra/pcie.c                 |   16 ++++++++++++----
 3 files changed, 17 insertions(+), 9 deletions(-)


From olof at lixom.net  Sun Mar 18 13:54:15 2012
From: olof at lixom.net (Olof Johansson)
Date: Sun, 18 Mar 2012 10:54:15 -0700
Subject: [GIT PULL] A few more dt patches for tegra
Message-ID: <CAOesGMgrx3VK0Om8KoSMh8=7+EmW-P-ZqmXKLNDO6mw4g3yrFg@mail.gmail.com>

Hi Arnd,

I have a few more patches on top of the branch already pulled into
tegra/dt in arm-soc. Please pull these ones on top of the existing
contents.

Thanks!


-Olof

The following changes since commit 96d6714ca27acab087dcc8d75a7ec815abe3dde7:

  ASoC: DT: Add digital microphone binding to PAZ00 board. (2012-03-04
10:42:16 -0800)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git for-3.4/dt

for you to fetch changes up to 0a428036dfb28be3e5f0d671e3457509d1f4ea29:

  arm: tegra: dts: Mark USB1 as an OTG port on Seaboard (2012-03-07
14:36:56 -0800)

----------------------------------------------------------------
Simon Glass (3):
      arm: tegra: dts: Support host/device selection and legacy mode
      arm: tegra: dts: Add legacy mode support to Tegra2x USB1 port
      arm: tegra: dts: Mark USB1 as an OTG port on Seaboard

 Documentation/devicetree/bindings/usb/tegra-usb.txt |   13 +++++++++++++
 arch/arm/boot/dts/tegra-seaboard.dts                |    1 +
 arch/arm/boot/dts/tegra20.dtsi                      |    1 +
 3 files changed, 15 insertions(+)


From grant.likely at secretlab.ca  Sun Mar 18 14:22:38 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 18 Mar 2012 18:22:38 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120318092241.GA23839@avionic-0098.mockup.avionic-design.de>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <201203150922.06379.arnd@arndb.de>
 <20120315102736.GA25371@avionic-0098.adnet.avionic-design.de>
 <20120317104751.4F00E3E0910@localhost>
 <20120318092241.GA23839@avionic-0098.mockup.avionic-design.de>
Message-ID: <20120318182238.3A7D43E07BF@localhost>

On Sun, 18 Mar 2012 10:22:41 +0100, Thierry Reding <thierry.reding at avionic-design.de> wrote:
> * Grant Likely wrote:
> > On Thu, 15 Mar 2012 11:27:36 +0100, Thierry Reding <thierry.reding at avionic-design.de> wrote:
> > > So if we decide to explicitly allow specifying names, then we can always add
> > > a pwm-names property (or <name>-pwm-names respectively) to use as label and
> > > fallback to the user OF device node name if that property is not present.
> > 
> > After implementing both schemes (ie. interrupts+interrupt-names && [*-]gpios)
> > I definitely prefer the fixed property name plus a separate names property.
> > It is easier to use common code with that scheme, and easier to statically
> > check for correctness.
> 
> Okay. Would everyone be happy with "pwms" and "pwm-names"?

okay.

g.



From grant.likely at secretlab.ca  Sun Mar 18 14:47:49 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 18 Mar 2012 18:47:49 +0000
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120316030134.GA5161@shlinux2.ap.freescale.net>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
 <20120316030134.GA5161@shlinux2.ap.freescale.net>
Message-ID: <20120318184749.BB15D3E07BF@localhost>

On Fri, 16 Mar 2012 11:01:35 +0800, Dong Aisheng <aisheng.dong at freescale.com> wrote:
> On Thu, Mar 15, 2012 at 07:22:04PM +0800, Lothar Wa??mann wrote:
> > Hi,
> > 
> > Dong Aisheng writes:
> > > On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa??mann wrote:
> > > > Hi,
> > > > 
> > > > Dong Aisheng writes:
> > > > > On Wed, Mar 14, 2012 at 10:16:43PM +0800, s.hauer at pengutronix.de wrote:
> > > > > > On Wed, Mar 14, 2012 at 08:45:23PM +0800, Dong Aisheng wrote:
> > > > > > > On Wed, Mar 14, 2012 at 01:23:51AM +0800, Grant Likely wrote:
> > > > [...]
> > > > > > > But it seems this needs pass mac address to fec driver via platforom data which is
> > > > > > > not friendly to dt.
> > > > > > > 
> > > > > > > Another way may be changing fec driver to get the fixed part of mac address(first
> > > > > > > two bytes) from device tree and read the left dynamical part from otp which i'm not
> > > > > > > sure is better enough.
> > > > > > > 
> > > > > > > BTW, filling with zeros seems not work since it's invalid mac address.
> > > > > > 
> > > > > > Yes, that's the idea of using this value...
> > > > > > 
> > > > > But comparing to use an invalid value, why not just do not define that
> > > > > local-mac-address property?
> > > > > 
> > > > Because a MAC address is by definition a GLOBALLY UNIQUE IDENTIFIER
> > > > which is contrary to coding a "valid" default value for it somewhere!
> > > > The owner of a certain MAC address range (OUI) is responsible for
> > > > ensuring the uniqueness. Thus only they may assign a specific MAC
> > > > address to a specific device.
> > > > 
> > > Yes, you're correct.
> > > So i propose to read the MAC address from MX28 OTP in fec driver instead of
> > > define it in device tree in my last mail.
> > > http://www.spinics.net/lists/arm-kernel/msg165040.html
> > > Do you have any comment on that way?
> > > 
> > That patch sets the OUI to the Freescale owned MAC range. Thus only
> > Freescale products may be able to use the driver.
> > 
> No.
> My proposal is only set the fixed part(first two octets) in board dts file,
> each board knows it's value, and read the left 4 octets from OCOTP dynamically.
> Obviously the freeescale board dts file is only for FSL platforms.
> Other platforms can define their fix part of MAC address in their dts file.
> 
> > Anyway there is no definite spec how the MAC address(es) are stored
> > in the fuse map. Thus reading the MAC from there is more or less
> > platform specific.
> > 
> It's just provide one more option since there are customers storing the MAC
> in the fuse map.

That should be straight forward to support; have a property that
specifies the method used for fetching/calculating the MAC.

> > Currently I'm setting up the MAC address for our TX28 from the fuses
> > in the platform code passed via platform_data, but that will obviously
> > not work with DT.
> > 
> Non-dt can also use my proposal, then you only need to pass the fixed part of
> MAC via platfrom data, the left will be read by fec driver.
> 
> > The correct way would probably be to pass the MAC from the bootloader
> > via a DT blob. But that would require all bootloaders to be updated
> > first to support DTS. :(
> > 
> But uboot will face the same problem that can not define a valid MAC
> in dts, did i undertand correctly?
> 
> > An intermediate solution could be using OF_DEV_AUXDATA to pass a
> > platform_data struct that may contain a MAC address set up by the
> > platform code.
> > 
> Yes, it's a way but i'm afraid will not get accepted by dt people.

The problem remains; where does the platform code get the MAC address
from?  The kernel has to devise it from *somewhere* and the best place
for that should be in the MAC driver itself.

I've got no problem with the idea of only specifying the OUI in the DT
and the driver extracting the remaining 3 bytes from the hardware.

In principle, that's the design intent for DT systems anyway; it
describes things which cannot be probed from the hardware, or tells
the OS how the data is encoded in the hardware.

g.

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From arnd at arndb.de  Sun Mar 18 16:13:22 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 18 Mar 2012 20:13:22 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120317094059.7C2333E08E2@localhost>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <20120317094059.7C2333E08E2@localhost>
Message-ID: <201203182013.22790.arnd@arndb.de>

On Saturday 17 March 2012, Grant Likely wrote:
> > +static LIST_HEAD(of_dma_list);
> > +
> > +struct of_dma {
> > +     struct list_head of_dma_controllers;
> > +     struct device_node *of_node;
> > +     int of_dma_n_cells;
> > +     int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
> > +};
> 
> This _xlate is nearly useless as a generic API.  It solves the problem for
> the specific case where the driver is hard-coded to know which DMA engine
> to talk to, but since the returned data doesn't provide any context, it
> isn't useful if there are multiple DMA controllers to choose from.
> 
> The void *data pointer must be replaced with a typed structure so that
> context can be returned.

I've read up a bit more on how the existing drivers use the filter
functions, it seems there are multiple classes of them, the classes
that I've encountered are:

1. matches on chan->device pointer and/or chan_id
   (8 drivers)
2. will match anything
   (6 drivers)
3. requires specific dma engine driver, then behaves like 1 or 2
   (8 drivers, almost all freescale)
4. one of a kind, matches resource name string or device->dev_id
   (two drivers)
5. filter function and data both provided by platform code,
   platform picks dmaengine driver.
   (4 amba pl* drivers, used on ARM, ux500, ...)

The last category is interesting because here, the dmaengine
driver (pl330, coh901318, sirf-dma, ste_dma40) provides the filter
function while in the other cases that is provided by the device
driver! Out of these, the ste_dma40 is special because it's the
only one where the data is a complex data structure describing the
constraints on the driver, while all others just find the right
channel.

Some drivers also pass assign driver specific data to chan->private.

I would hope that we can all make them use something like
     struct dma_channel *of_dma_request_channel(struct of_node*,
					int index, void *driver_data);
with an appropriate common definition behind it. In the cases
where the driver can just match anything, I'd assume that all
channels are equal, so #dma-cells would be 0. For the ste_dma40,
#dma-cells needs to cover all of stedma40_chan_cfg. In most
other cases, #dma-cells can be 1 and just enumerate the channels,
unless we want to simplify the cases that Russell mentioned where
we want to keep a two stage mapping channel identifiers and physical
channel numbers.

How about an implementation like this:?

typedef bool dma_filter_simple(struct dma_chan *chan, void *filter_param)
{
	/* zero #dma-cells, accept anything */
	return true;
}

struct dma_channel *of_dma_request_channel(struct of_node*, int index,
					dma_cap_mask_t *mask,
					void *driver_data)
{
	struct of_phandle_args dma_spec;
	struct dma_device *device;
	struct dma_chan *chan = NULL;
	dma_filter_fn *filter;

	ret = of_parse_phandle_with_args(np, "dma-request", "#dma-cells",
					 index, &dma_spec);

	device = dma_find_device(dma_spec->np);
	if (!device)
		goto out;

	if (dma_spec->args_count == 0)
		filter = dma_filter_simple;
	else
		filter = device->dma_dt_filter; /* new member */

	chan = private_candidate(mask, device, filter, dma_spec->args);

	if (chan && !chan->private)
		chan->private = driver_data;
out:
	return chan;
}

	Arnd


From grant.likely at secretlab.ca  Sun Mar 18 16:44:21 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 18 Mar 2012 20:44:21 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203182013.22790.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <20120317094059.7C2333E08E2@localhost> <201203182013.22790.arnd@arndb.de>
Message-ID: <20120318204421.759F23E07BF@localhost>

On Sun, 18 Mar 2012 20:13:22 +0000, Arnd Bergmann <arnd at arndb.de> wrote:
> On Saturday 17 March 2012, Grant Likely wrote:
> > > +static LIST_HEAD(of_dma_list);
> > > +
> > > +struct of_dma {
> > > +     struct list_head of_dma_controllers;
> > > +     struct device_node *of_node;
> > > +     int of_dma_n_cells;
> > > +     int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
> > > +};
> > 
> > This _xlate is nearly useless as a generic API.  It solves the problem for
> > the specific case where the driver is hard-coded to know which DMA engine
> > to talk to, but since the returned data doesn't provide any context, it
> > isn't useful if there are multiple DMA controllers to choose from.
> > 
> > The void *data pointer must be replaced with a typed structure so that
> > context can be returned.
> 
> I've read up a bit more on how the existing drivers use the filter
> functions, it seems there are multiple classes of them, the classes
> that I've encountered are:
> 
> 1. matches on chan->device pointer and/or chan_id
>    (8 drivers)
> 2. will match anything
>    (6 drivers)
> 3. requires specific dma engine driver, then behaves like 1 or 2
>    (8 drivers, almost all freescale)
> 4. one of a kind, matches resource name string or device->dev_id
>    (two drivers)
> 5. filter function and data both provided by platform code,
>    platform picks dmaengine driver.
>    (4 amba pl* drivers, used on ARM, ux500, ...)
> 
> The last category is interesting because here, the dmaengine
> driver (pl330, coh901318, sirf-dma, ste_dma40) provides the filter
> function while in the other cases that is provided by the device
> driver! Out of these, the ste_dma40 is special because it's the
> only one where the data is a complex data structure describing the
> constraints on the driver, while all others just find the right
> channel.
> 
> Some drivers also pass assign driver specific data to chan->private.
> 
> I would hope that we can all make them use something like
>      struct dma_channel *of_dma_request_channel(struct of_node*,
> 					int index, void *driver_data);

certainly my hope too!

> with an appropriate common definition behind it. In the cases
> where the driver can just match anything, I'd assume that all
> channels are equal, so #dma-cells would be 0. For the ste_dma40,
> #dma-cells needs to cover all of stedma40_chan_cfg. In most
> other cases, #dma-cells can be 1 and just enumerate the channels,
> unless we want to simplify the cases that Russell mentioned where
> we want to keep a two stage mapping channel identifiers and physical
> channel numbers.
> 
> How about an implementation like this:?
> 
> typedef bool dma_filter_simple(struct dma_chan *chan, void *filter_param)
> {
> 	/* zero #dma-cells, accept anything */
> 	return true;
> }
> 
> struct dma_channel *of_dma_request_channel(struct of_node*, int index,
> 					dma_cap_mask_t *mask,
> 					void *driver_data)
> {
> 	struct of_phandle_args dma_spec;
> 	struct dma_device *device;
> 	struct dma_chan *chan = NULL;
> 	dma_filter_fn *filter;
> 
> 	ret = of_parse_phandle_with_args(np, "dma-request", "#dma-cells",
> 					 index, &dma_spec);
> 
> 	device = dma_find_device(dma_spec->np);

Is dma_find_device() a new function?  How does it look up the dma
device?

> 	if (!device)
> 		goto out;

Just return NULL here.

> 
> 	if (dma_spec->args_count == 0)
> 		filter = dma_filter_simple;
> 	else
> 		filter = device->dma_dt_filter; /* new member */

I'm not thrilled with this if/else hunk; even the case of
#dma-cells=<0> should provide a hook; even it if is the stock simple
filter.  Leaving filter as NULL is the same as accepting everything
anyway.

> 
> 	chan = private_candidate(mask, device, filter, dma_spec->args);
> 
> 	if (chan && !chan->private)
> 		chan->private = driver_data;
> out:
> 	return chan;

I think this looks right, except for the comments above.

g.


From grant.likely at secretlab.ca  Sun Mar 18 16:48:52 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 18 Mar 2012 20:48:52 +0000
Subject: [PATCH v2 4/4] misc: emif: add device tree support to emif driver
In-Reply-To: <1331836447-7584-5-git-send-email-aneesh@ti.com>
References: <1331836447-7584-1-git-send-email-aneesh@ti.com>
 <1331836447-7584-5-git-send-email-aneesh@ti.com>
Message-ID: <20120318204852.664953E07BF@localhost>

On Fri, 16 Mar 2012 00:04:07 +0530, Aneesh V <aneesh at ti.com> wrote:
> Cc: Rajendra Nayak <rnayak at ti.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Signed-off-by: Aneesh V <aneesh at ti.com>

All 4 look okay to me.

Reviewed-by: Grant Likely <grant.likely at secretlab.ca>


From grant.likely at secretlab.ca  Sun Mar 18 17:08:06 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 18 Mar 2012 21:08:06 +0000
Subject: [PATCH 4/4] misc: emif: add device tree support to emif driver
In-Reply-To: <4F59FCAB.5040107@ti.com>
References: <1331224437-4808-1-git-send-email-aneesh@ti.com>
 <1331224437-4808-5-git-send-email-aneesh@ti.com>
 <20120309053704.E40433E0901@localhost> <4F59FCAB.5040107@ti.com>
Message-ID: <20120318210807.057653E07BF@localhost>

On Fri, 09 Mar 2012 18:20:51 +0530, Aneesh V <aneesh at ti.com> wrote:
> Hi Grant,
> 
> On Friday 09 March 2012 11:07 AM, Grant Likely wrote:
> > On Thu,  8 Mar 2012 22:03:57 +0530, Aneesh V<aneesh at ti.com>  wrote:
> >> Cc: Rajendra Nayak<rnayak at ti.com>
> >> Cc: Benoit Cousson<b-cousson at ti.com>
> >> Signed-off-by: Aneesh V<aneesh at ti.com>
> >> ---
> >> Changes since RFC v4:
> >> - Rebased to the latest version of EMIF series
> >> - Replace kzalloc()/kfree() with devm_* variants
> >> ---
> >>   drivers/misc/emif.c |  289 ++++++++++++++++++++++++++++++++++++++++++++++++++-
> >>   1 files changed, 288 insertions(+), 1 deletions(-)
> >>
> >> diff --git a/drivers/misc/emif.c b/drivers/misc/emif.c
> >> index 79fb161..0aaa61e 100644
> >> --- a/drivers/misc/emif.c
> >> +++ b/drivers/misc/emif.c
> >> @@ -18,6 +18,7 @@
> >>   #include<linux/platform_device.h>
> >>   #include<linux/interrupt.h>
> >>   #include<linux/slab.h>
> >> +#include<linux/of.h>
> >>   #include<linux/debugfs.h>
> >>   #include<linux/seq_file.h>
> >>   #include<linux/module.h>
> >> @@ -49,6 +50,7 @@
> >>    *				frequency in effect at the moment)
> >>    * @plat_data:			Pointer to saved platform data.
> >>    * @debugfs_root:		dentry to the root folder for EMIF in debugfs
> >> + * @np_ddr:			Pointer to ddr device tree node
> >>    */
> >>   struct emif_data {
> >>   	u8				duplicate;
> >> @@ -63,6 +65,9 @@ struct emif_data {
> >>   	struct emif_regs		*curr_regs;
> >>   	struct emif_platform_data	*plat_data;
> >>   	struct dentry			*debugfs_root;
> >> +#if defined(CONFIG_OF)
> >> +	struct device_node		*np_ddr;
> >> +#endif
> >
> > Don't bother with the #if/#endif wrapper here.
> 
> Ok.
> 
> >
> >>   };
> >>
> >>   static struct emif_data *emif1;
> >> @@ -1147,6 +1152,270 @@ static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
> >>   	return valid;
> >>   }
> >>
> >> +#if defined(CONFIG_OF)
> >> +static void __init of_get_custom_configs(struct device_node *np_emif,
> >
> > __devinit. Same through the rest of the file.
> 
> I am not sure if we need __devinit. I see that __devinit will not have
> any effect if CONFIG_HOTPLUG is enabled and CONFIG_HOTPLUG is always
> enabled in our configuration. EMIF devices are not hot-pluggable
> devices and are always added at boot-time from the board file. They are
> on-chip IP modules and dynamic discovery and addition doesn't make
> sense for them. So, can't we save some memory by making them __init.
> 
> AFAIU, __init doesn't have any effect in a module. However, I can make
> that more explicit by using '__init_or_module'. Is that ok?
> 
> >
> > [...]
> >> +	return NULL;
> >> +out:
> >> +	return emif;
> >> +}
> >> +#endif
> >> +
> >>   static struct emif_data * __init get_device_details(
> >
> > This function also must be __devinit
> >
> >>   		struct platform_device *pdev)
> >>   {
> >> @@ -1266,7 +1535,13 @@ static int __init emif_probe(struct platform_device *pdev)
> >>   	struct resource		*res;
> >>   	int			irq;
> >>
> >> -	emif = get_device_details(pdev);
> >> +#if defined(CONFIG_OF)
> >> +	if (pdev->dev.of_node)
> >> +		emif = of_get_device_details(pdev->dev.of_node,&pdev->dev);
> >> +	else
> >> +#endif
> >> +		emif = get_device_details(pdev);
> >> +
> >>   	if (!emif) {
> >>   		pr_err("%s: error getting device data\n", __func__);
> >>   		goto error;
> >> @@ -1643,11 +1918,23 @@ static void __attribute__((unused)) freq_post_notify_handling(void)
> >>   	spin_unlock_irqrestore(&emif_lock, irq_state);
> >>   }
> >>
> >> +#if defined(CONFIG_OF)
> >> +static const struct of_device_id emif_of_match[] = {
> >> +		{ .compatible = "ti,emif-4d" },
> >> +		{ .compatible = "ti,emif-4d5" },
> >> +		{},
> >> +};
> >> +MODULE_DEVICE_TABLE(of, emif_of_match);
> >> +#endif
> >> +
> >>   static struct platform_driver emif_driver = {
> >>   	.remove		= __exit_p(emif_remove),
> >
> > Not part of this patch I realize, but this is a bug.  .remove must
> > be in the __devexit section and the __devexit_p() wrapper must
> > be used.  Similarly, emif_probe must be in the __devinit section.
> 
> Again, in our case remove() is not needed unless the driver is built as
> a module because the devices will never be un-registered. When it is
> built as a module the effect is same for both:

It's just outside the pattern expected for device drivers.  I like to
be careful about things like this.  That's why I recommend __devinit
also, but I see now that the probe hook isn't added to the
platform_device so it isn't required.

> 
> #if defined(MODULE) || defined(CONFIG_HOTPLUG)
> #define __devexit_p(x) x
> #else
> #define __devexit_p(x) NULL
> #endif
> 
> #ifdef MODULE
> #define __exit_p(x) x
> #else
> #define __exit_p(x) NULL
> #endif

Don't go with what is written in the code here; go with what the
meaning of the sections are.  The code can be changed, but the drivers
are expected to honor what the sections mean.

__init can be freed after module init
__devinit in reality never gets freed because devices can show up later
__devexit can be freed if hotplug is not enabled
__exit can be freed after module unload

g.



From arnd at arndb.de  Sun Mar 18 17:58:10 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 18 Mar 2012 21:58:10 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120318204421.759F23E07BF@localhost>
References: <4F22DEF2.5000807@ti.com> <201203182013.22790.arnd@arndb.de>
 <20120318204421.759F23E07BF@localhost>
Message-ID: <201203182158.10957.arnd@arndb.de>

On Sunday 18 March 2012, Grant Likely wrote:
> > struct dma_channel *of_dma_request_channel(struct of_node*, int index,
> >                                       dma_cap_mask_t *mask,
> >                                       void *driver_data)
> > {
> >       struct of_phandle_args dma_spec;
> >       struct dma_device *device;
> >       struct dma_chan *chan = NULL;
> >       dma_filter_fn *filter;
> > 
> >       ret = of_parse_phandle_with_args(np, "dma-request", "#dma-cells",
> >                                        index, &dma_spec);
> > 
> >       device = dma_find_device(dma_spec->np);
> 
> Is dma_find_device() a new function?  How does it look up the dma
> device?

Yes, it would be similar to the proposed function in Benoit's patch

> > 
> >       if (dma_spec->args_count == 0)
> >               filter = dma_filter_simple;
> >       else
> >               filter = device->dma_dt_filter; /* new member */
> 
> I'm not thrilled with this if/else hunk; even the case of
> #dma-cells=<0> should provide a hook; even it if is the stock simple
> filter.  Leaving filter as NULL is the same as accepting everything
> anyway.

Right, good point. So a dmaengine driver would either register a trivial
filter if it wants to do anything here, or it would just leave it as a NULL
pointer otherwise.

	Arnd


From arnd at arndb.de  Sun Mar 18 18:12:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 18 Mar 2012 22:12:00 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203182158.10957.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com> <20120318204421.759F23E07BF@localhost>
 <201203182158.10957.arnd@arndb.de>
Message-ID: <201203182212.00769.arnd@arndb.de>

On Sunday 18 March 2012, Arnd Bergmann wrote:
> > 
> > Is dma_find_device() a new function?  How does it look up the dma
> > device?
> 
> Yes, it would be similar to the proposed function in Benoit's patch
> 

Well, actually we would not even need a new list with all the devices,
it can simply become

/* must be called with dma_list_mutex held */
static struct dma_device *dma_find_device(struct of_node *node)
{
	struct dma_device *device;
	
	list_for_each_entry(device, &dma_device_list, global_node) {
		if (device->dev.of_node == node)
			break;
	}
	return device;
}

Given that dma_device_list is most likely be a very short list, this will
be a fast operation.

	Arnd


From linus.walleij at linaro.org  Sun Mar 18 19:19:55 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 19 Mar 2012 00:19:55 +0100
Subject: ARM: fix build failure on ux500 in linux-next
In-Reply-To: <20120316211759.GA18829@windriver.com>
References: <20120316211759.GA18829@windriver.com>
Message-ID: <CACRpkdYzS=wkfUU4gJLTp7djd6J20zVCC_6XhrjwoVpAoSe8iA@mail.gmail.com>

On Fri, Mar 16, 2012 at 10:18 PM, Paul Gortmaker
<paul.gortmaker at windriver.com> wrote:

> When I 1st saw this build failure, I thought it was me, because of the
> BUG() stuff. ?But git bisect claims it comes from the arm-soc tree?

Hm yeah looks like that, but we cannot see which commit
I guess, just that it's the merge from ARM SoC?

> In any case, the fix is trivial and self evident, regardless of where
> it came from. ?I can carry it in my bug-3.4 cleanup tree if need be.
> Let me know if you want me to do that.

Any way that solves the issue is fine with me, maybe Arnd/Olof
wants to apply it to the ARM SoC tree rather? If they don't say
anything, by all means please keep it in cleanup.

Yours,
Linus Walleij


From jg1.han at samsung.com  Sun Mar 18 19:46:25 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Mon, 19 Mar 2012 08:46:25 +0900
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <CAEYLNCpJU_5uVa-jo5HUNY8Av6eYaiow1gEZtHCiQZ5oKkGoMQ@mail.gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com> <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
 <001d01cd0315$935cc720$ba165560$%han@samsung.com>
 <CAEYLNCrGCmb5EJjURLY=EGfM=4N54MirNkCCyQRxqKEN3Eka8Q@mail.gmail.com>
 <002d01cd034b$c56f2b00$504d8100$%han@samsung.com>
 <CAEYLNCpfQ0cYb4efw6PZNnKjQ2rF25rj5Ed=i884LJXHAwigBw@mail.gmail.com>
 <002f01cd0359$eb718330$c2548990$%han@samsung.com>
 <CAEYLNCpJU_5uVa-jo5HUNY8Av6eYaiow1gEZtHCiQZ5oKkGoMQ@mail.gmail.com>
Message-ID: <001501cd0561$57c642b0$0752c810$%han@samsung.com>

> -----Original Message-----
> From: linux-samsung-soc-owner at vger.kernel.org [mailto:linux-samsung-soc-owner at vger.kernel.org] On Behalf
> Of Darius Augulis
> Sent: Friday, March 16, 2012 7:19 PM
> To: Jingoo Han
> Cc: Thomas Abraham; linux-fbdev at vger.kernel.org; FlorianSchandinat at gmx.de; linux-arm-
> kernel at lists.infradead.org; linux-samsung-soc at vger.kernel.org; ben-linux at fluff.org; patches at linaro.org;
> kgene.kim at samsung.com; Kyungmin Park; JeongHyeon Kim; Heiko Stuebner; Kwangwoo Lee; Mark Brown; Peter
> Korsgaard; Maurus Cuelenaere; Tushar Behera
> Subject: Re: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
> 
> On Fri, Mar 16, 2012 at 11:48 AM, Jingoo Han <jg1.han at samsung.com> wrote:
> >> > It's just bug.
> >> >
> >> > struct s3c_fb_pd_win should be used for windows of FIMD IP.
> >> > It should not be used for selecting multi-LCDs.
> >>
> >> why not? s3c_fb_pd_win contains timing values which depend directly on
> >> LCD size and resolution.
> >> Please look into the code again - mini6410 doesn't use platform data
> >> so select different LCD sizes.
> >> It has only single window in platform data - exactly what you want.
> >> Now tell my, why you are arguing, that this platform data cannot be
> >> rewritten dynamically by board setup routines at kernel startup time?
> >> Many ARM architectures are doing the same - takes kernel command line
> >> argument to select LCD and passes necessary data for its fb drivers
> >> via platform data structures. It not a bug, it's correct approach to
> >> support different sizes of LCD display for the same board.
> >
> >
> > Hey, it is not my point.
> > To take kernel command line is not problem to support multiple LCDs.
> >
> > My point is that s3c_fb_pd_win should not include variable LCD option.
> > So, if you want to support multiple LCDs, you should use another variable,
> > instead of using s3c_fb_pd_win[0] and s3c_fb_pd_win[1] as 4.3" LCD, 7.0" LCD.
> 
> But I use s3c_fb_pd_win only as container to hold timing values in
> board setup code.
> s3c-fb platform data has only single window and does not perform any
> LCD selection.
> What is wrong here? You suggest to declare some custom structure to
> hold these timing values? What's the point?
> 
> >
> > You use s3c_fb_pd_win[0], s3c_fb_pd_win[1] as 4.3" LCD, 7.0" LCD.
> > However, s3c_fb_pd_win[0], s3c_fb_pd_win[1] means the windows of FIMD IP.
> 
> There is no multiple windows in platform data! driver sees only single
> window. And this wont change in any way if you drop LCD selection from
> board setup code.
> Driver will see the same single window. So - your are arguing, that
> board setup code sets platform data in bad way. I don't accept your
> opinion, because tens of boards are doing the same and nobody call it
> bug.

Because there are not multiple windows and driver sees only single window as you mentiond, 
Only 'struct s3c_fb_pd_win mini6410_fb_win[0]' should be used and 
'struct s3c_fb_pd_win mini6410_fb_win[1]' should not be used.
s3c_fb_pd_win[0] means window 0 of FIMD IP, s3c_fb_pd_win[1] means window 1 of FIMD IP.

Therefore, if mini6410_fb_win[0] and mini6410_fb_win[1] are included, it means that
2 windows of FIMD IP are used in single LCD.

If you want to support multiple LCDs, you should use struct s3c_fb_platdata[0], struct s3c_fb_platdata[1],
because 'struct s3c_fb_platdata' means LCD panel.

If you understand the purpose of s3c_fb_platdata and s3c_fb_pd_win, you should do, at least, as below.

static struct s3c_fb_pd_win mini6410_fb_lcd0_win[] = {
	{
		.win_mode	= {	/* 4.3" 480x272 */
			.left_margin	= 3,
			.right_margin	= 2,
			.upper_margin	= 1,
			.lower_margin	= 1,
			.hsync_len	= 40,
			.vsync_len	= 1,
			.xres		= 480,
			.yres		= 272,
		},
		.max_bpp	= 32,
		.default_bpp	= 16,
	},
};

static struct s3c_fb_platdata mini6410_lcd_pdata[0] __initdata = {
	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
	.win[0]		= &mini6410_fb_lcd0_win[0],
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};

static struct s3c_fb_pd_win mini6410_fb_lcd1_win[] = {
	{
		.win_mode	= {	/* 7.0" 800x480 */
			.left_margin	= 8,
			.right_margin	= 13,
			.upper_margin	= 7,
			.lower_margin	= 5,
			.hsync_len	= 3,
			.vsync_len	= 1,
			.xres		= 800,
			.yres		= 480,
		},
		.max_bpp	= 32,
		.default_bpp	= 16,
	},
};

static struct s3c_fb_platdata mini6410_lcd_pdata[1] __initdata = {
	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
	.win[0]		= &mini6410_fb_lcd1_win[0],
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};

Each struct means:
  mini6410_lcd_pdata[0]: 4.3" 480x272 LCD
  mini6410_fb_lcd0_win[0]: window 0 used for 4.3" 480x272 LCD

  mini6410_lcd_pdata[1]: 7.0" 800x480 LCD
  mini6410_fb_lcd1_win[0]: window 0 used for 7.0" 800x480 LCD

In this case, 4.3" or 7.0" LCD can be selected using mini6410_lcd_pdata[], instead of selecting mini6410_fb_win[0] or
mini6410_fb_win[1].

My point is that 's3c_fb_platdata and s3c_fb_pd_win should be used exactly'.

> 
> >
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From linus.walleij at linaro.org  Sun Mar 18 19:57:18 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 19 Mar 2012 00:57:18 +0100
Subject: [PATCH 1/2] ARM: dts: versatile-pb/ab fix MMC IRQs
In-Reply-To: <1330682843-21163-1-git-send-email-linus.walleij@linaro.org>
References: <1330682843-21163-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <CACRpkdYu-kSW0SEkMWXiuuu+sy5h2qLSBCYn+vo-NpdohzaM6A@mail.gmail.com>

On Fri, Mar 2, 2012 at 11:07 AM, Linus Walleij <linus.walleij at linaro.org> wrote:

> The MMCI driver will not work without two IRQs since this is not
> flagged as a single-irq variant. Looking through the complex IRQ
> definition for the MMCI on the versatile (including an #if 1
> statement forcing MMCI IRQ0 to the VIC) this appears to the the
> correct IRQ number for both models.
>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> Cc: Niklas Hernaeus <niklas.hernaeus at linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Ping on this and 2/2, could go in as fixes as well.

Yours,
Linus Walleij


From vapier at gentoo.org  Sun Mar 18 20:42:22 2012
From: vapier at gentoo.org (Mike Frysinger)
Date: Sun, 18 Mar 2012 20:42:22 -0400
Subject: [PATCH] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
References: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <201203182042.27555.vapier@gentoo.org>

On Friday 16 March 2012 17:03:55 Stephen Warren wrote:
> All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
> to avoid duplication.
> 
> All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
> parameterized version in Makefile.lib to avoid duplication.

seems to build for Blackfin systems.
Tested-by: Mike Frysinger <vapier at gentoo.org>
-mike
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From haojian.zhuang at gmail.com  Sun Mar 18 21:43:46 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Mon, 19 Mar 2012 09:43:46 +0800
Subject: [PATCH] pxa/hx4700: Add standard UART to hx4700_pin_config[]
In-Reply-To: <1331911475.54244.YahooMailClassic@web29012.mail.ird.yahoo.com>
References: <1331911475.54244.YahooMailClassic@web29012.mail.ird.yahoo.com>
Message-ID: <CAN1soZy0OtAYNrFKRhwOKDtgJaE8fHrWAzwM3xeocvVS75PP=g@mail.gmail.com>

On Fri, Mar 16, 2012 at 11:24 PM, Paul Parsons <lost.distance at yahoo.com> wrote:
> Add the two standard UART signals (GPIO46_STUART_RXD, GPIO47_STUART_TXD) to the
> initial mfp config table hx4700_pin_config[] passed to pxa2xx_mfp_config().
> Although pxa2xx_transceiver_mode() can subsequently set these two signals via
> its own call to pxa2xx_mfp_config(), pxa2xx_transceiver_mode() is only present
> when CONFIG_PXA_FICP=y. Hence this patch provides a default mfp config.
>
> Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
> ---
>
> --- a/arch/arm/mach-pxa/hx4700.c ? ? ? ?2012-03-16 15:18:29.636709575 +0000
> +++ b/arch/arm/mach-pxa/hx4700.c ? ? ? ?2012-03-16 15:19:35.401070040 +0000
> @@ -101,6 +101,10 @@ static unsigned long hx4700_pin_config[]
> ? ? ? ?GPIO44_BTUART_CTS,
> ? ? ? ?GPIO45_BTUART_RTS_LPM_LOW,
>
> + ? ? ? /* STUART (IRDA) */
> + ? ? ? GPIO46_STUART_RXD,
> + ? ? ? GPIO47_STUART_TXD,
> +
> ? ? ? ?/* PWM 1 (Backlight) */
> ? ? ? ?GPIO17_PWM1_OUT,
>
Applied. Thanks


From richard.zhao at freescale.com  Sun Mar 18 21:51:43 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Mon, 19 Mar 2012 09:51:43 +0800
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <20120317122831.GD29317@pengutronix.de>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
 <20120314085228.GM3852@pengutronix.de>
 <20120315144601.GA5701@richard-laptop>
 <20120315150048.GC3852@pengutronix.de>
 <20120315151521.GB5701@richard-laptop>
 <20120315185004.GD3852@pengutronix.de>
 <20120316011006.GA17459@b20223-02.ap.freescale.net>
 <20120317122831.GD29317@pengutronix.de>
Message-ID: <20120319015142.GA2603@b20223-02.ap.freescale.net>

On Sat, Mar 17, 2012 at 01:28:31PM +0100, Sascha Hauer wrote:
> On Fri, Mar 16, 2012 at 09:10:07AM +0800, Richard Zhao wrote:
> > Hi Sascha,
> > 
> > On Thu, Mar 15, 2012 at 07:50:04PM +0100, Sascha Hauer wrote:
> > > On Thu, Mar 15, 2012 at 11:15:23PM +0800, Richard Zhao wrote:
> > > > On Thu, Mar 15, 2012 at 04:00:48PM +0100, Sascha Hauer wrote:
> > > > > On Thu, Mar 15, 2012 at 10:46:04PM +0800, Richard Zhao wrote:
> > > > > > On Wed, Mar 14, 2012 at 09:52:28AM +0100, Sascha Hauer wrote:
> > > > > > > On Wed, Mar 14, 2012 at 04:22:58PM +0800, Richard Zhao wrote:
> > > > > > > > Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> > > > > > > > ---
> > > > > > > >  
> > > > > > > >  #define DEF_PLL(name)					\
> > > > > > > >  	static struct clk name = {			\
> > > > > > > > @@ -681,6 +741,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
> > > > > > > >  		.disable	= pll_disable,		\
> > > > > > > >  		.get_rate	= name##_get_rate,	\
> > > > > > > >  		.set_rate	= name##_set_rate,	\
> > > > > > > > +		.round_rate	= name##_round_rate,	\
> > > > > > > 
> > > > > > > I hope this ## stuff is gone soon with the generic clock framework. It
> > > > > > > is so ugly and inefficient.
> > > > > > I hope this doesn't prevent this two patches go in.
> > > > > 
> > > > > Given that we are short from getting a generic clock framework (and I
> > > > > think this time it's for real) and that you are not mention in any words
> > > > > what these patches fix I don't see a reason for merging them.
> > > > I think the cpu clock is a great challenge for generic clock framework.
> > > > When it set_rate, it includes reparent, and change parent's parent's rate.
> > > > I don't see any upstream code like that till now. and it's really what
> > > > we need.
> > > 
> > > Then do a clk_set_parent, clk_set_rate and a clk_set_parent again
> > > in your cpufreq driver.
> > No, it's platform code, and supposed to be in arch/arm. What the cpufre
> > driver know is to get cpu clk, rather not how cpu clk change its rate.
> > And cpu clk/arm_clk is a real clock wires in SoC.
> 
> The job of the clock framework is to give a consistent view on the
> clocks and to handle parent/rate changes properly. It even the
> CLK_SET_RATE_GATE for ensuring that your PLL can only change its rate
> when it's gated. It's not the job of the clock framework to dynamically
> reorganize the clock tree on a rate change.
The reparent in set_rate is in mutex lock. Looks like, we only need
the unlocked version clk functions.
> 
> Besides, do you really want to reprogram the PLL with a cpufreq change?
> You have a divider behind that PLL which you apparently can change
> without having to reparent the PLL. Doesn't this give you enough choices
> for the cpu frequency?
No. The 3bit cpu divider is not enough. For example, if pll is 1G Hz, the
next lower freq will be 500M, which is a too large step.
> 
> > > The notifying mechanism even allows you to
> > > block any concurrent change in between these three steps if necessary.
> > > Noone says that these three steps have to be encapsulated in a single
> > > clk_set_rate call like you did in your patch.
> > If you're reviwing the patch, why not take a step advance? :)
> 
> I have prepared the patches for converting i.MX1/21/25/27 and I have
> (older) patches for the i.MX31/51/53 which I want to rebase on the
> current clock framework. 
You might notice I ever sent out serveral versions of MX5x clock porting
patches based on your first version. If you want to take it over, it's ok.
> That gives me enough to do until the next merge
> window. Additionally I'm not yet very familiar with the i.MX6.
So, Shawn, would you review it and consider the tricky things when
migrate to new framework?

Thanks
Richard
> 
> Sascha
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
> 



From richard.zhao at freescale.com  Sun Mar 18 21:54:34 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Mon, 19 Mar 2012 09:54:34 +0800
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
Message-ID: <20120319015433.GB2603@b20223-02.ap.freescale.net>

> +static unsigned long pll_av_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	unsigned long parent_rate = clk_get_rate(clk->parent);
> +	u32 div;
> +	u32 mfn, mfd = 1000000;
> +	s64 temp64;
> +
> +	rate = rate < FREQ_650M ? FREQ_650M : rate;
> +	rate = rate > FREQ_1300M ? FREQ_1300M : rate;
> +
> +	div = rate / parent_rate;
> +	temp64 = (u64) (parent_rate - (div * parent_rate));
Be			rate here.
Sorry.
> +        temp64 *= mfd;
> +        do_div(temp64, parent_rate);
> +        mfn = temp64;
> +
> +        return (parent_rate * div) + ((parent_rate / mfd) * mfn);
> +}
> +
 
Thanks
Richard



From shawn.guo at linaro.org  Sun Mar 18 22:48:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 19 Mar 2012 10:48:49 +0800
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <20120319015142.GA2603@b20223-02.ap.freescale.net>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
 <20120314085228.GM3852@pengutronix.de>
 <20120315144601.GA5701@richard-laptop>
 <20120315150048.GC3852@pengutronix.de>
 <20120315151521.GB5701@richard-laptop>
 <20120315185004.GD3852@pengutronix.de>
 <20120316011006.GA17459@b20223-02.ap.freescale.net>
 <20120317122831.GD29317@pengutronix.de>
 <20120319015142.GA2603@b20223-02.ap.freescale.net>
Message-ID: <20120319024847.GA31410@S2101-09.ap.freescale.net>

On Mon, Mar 19, 2012 at 09:51:43AM +0800, Richard Zhao wrote:
...
> So, Shawn, would you review it and consider the tricky things when
> migrate to new framework?
> 
Sure.  I'm working on it.  Just give me some time.

-- 
Regards,
Shawn


From marc at cpdesign.com.au  Mon Mar 19 00:03:54 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Mon, 19 Mar 2012 15:03:54 +1100
Subject: mc13xxx: add I2C support (now with regmap), V4
Message-ID: <1332129838-7080-1-git-send-email-marc@cpdesign.com.au>

Hi,

This series (against mfd-2.6/for-next) changes the mc13xxx driver to use 
regmap and adds I2C support.
It has a compile dependency on regmap/for-next, as the spi driver uses the
recently added pad_bits config field.

Changes since V3:
- spi driver uses padded register format (reads should actually work now!)
- mc13873 removed from I2C driver
- fix memory leak on probe error

Cheers,
Marc

PS. Mark Brown added his "reviwed-by" (sic) for what is now 2/4. I've not 
included it here because 1. it changed (albeit very slightly) so I don't 
know if it's bad ettiquie to include it again, and 2. I'm ignorant of the
correct process/way to include it.



From marc at cpdesign.com.au  Mon Mar 19 00:03:55 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Mon, 19 Mar 2012 15:03:55 +1100
Subject: [PATCH v4 1/4] mfd: mc13xxx-core: Prepare for separate spi and i2c
 backends.
In-Reply-To: <1332129838-7080-1-git-send-email-marc@cpdesign.com.au>
References: <1332129838-7080-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1332129838-7080-2-git-send-email-marc@cpdesign.com.au>

This patch abstracts the bus specific operations from the driver core.
Generic init and cleanup is consolidated into mc13xxx_common_*.
spi specific functions are renamed to reflect such.
(The irq member of the mc13xxx struct is no longer redundant, it's used
to store the irq for cleanup time).

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/mfd/mc13xxx-core.c |  187 ++++++++++++++++++++++++++------------------
 1 files changed, 112 insertions(+), 75 deletions(-)

diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index 7122386..0753402 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -22,8 +22,18 @@
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
 
+enum mc13xxx_id {
+	MC13XXX_ID_MC13783,
+	MC13XXX_ID_MC13892,
+	MC13XXX_ID_INVALID,
+};
+
 struct mc13xxx {
 	struct spi_device *spidev;
+
+	struct device *dev;
+	enum mc13xxx_id ictype;
+
 	struct mutex lock;
 	int irq;
 	int flags;
@@ -144,36 +154,32 @@ struct mc13xxx {
 void mc13xxx_lock(struct mc13xxx *mc13xxx)
 {
 	if (!mutex_trylock(&mc13xxx->lock)) {
-		dev_dbg(&mc13xxx->spidev->dev, "wait for %s from %pf\n",
+		dev_dbg(mc13xxx->dev, "wait for %s from %pf\n",
 				__func__, __builtin_return_address(0));
 
 		mutex_lock(&mc13xxx->lock);
 	}
-	dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
+	dev_dbg(mc13xxx->dev, "%s from %pf\n",
 			__func__, __builtin_return_address(0));
 }
 EXPORT_SYMBOL(mc13xxx_lock);
 
 void mc13xxx_unlock(struct mc13xxx *mc13xxx)
 {
-	dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
+	dev_dbg(mc13xxx->dev, "%s from %pf\n",
 			__func__, __builtin_return_address(0));
 	mutex_unlock(&mc13xxx->lock);
 }
 EXPORT_SYMBOL(mc13xxx_unlock);
 
 #define MC13XXX_REGOFFSET_SHIFT 25
-int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
+static int mc13xxx_spi_reg_read(struct mc13xxx *mc13xxx,
+				unsigned int offset, u32 *val)
 {
 	struct spi_transfer t;
 	struct spi_message m;
 	int ret;
 
-	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
-
-	if (offset > MC13XXX_NUMREGS)
-		return -EINVAL;
-
 	*val = offset << MC13XXX_REGOFFSET_SHIFT;
 
 	memset(&t, 0, sizeof(t));
@@ -195,26 +201,17 @@ int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 
 	*val &= 0xffffff;
 
-	dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
-
 	return 0;
 }
-EXPORT_SYMBOL(mc13xxx_reg_read);
 
-int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
+static int mc13xxx_spi_reg_write(struct mc13xxx *mc13xxx, unsigned int offset,
+		u32 val)
 {
 	u32 buf;
 	struct spi_transfer t;
 	struct spi_message m;
 	int ret;
 
-	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
-
-	dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
-
-	if (offset > MC13XXX_NUMREGS || val > 0xffffff)
-		return -EINVAL;
-
 	buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
 
 	memset(&t, 0, sizeof(t));
@@ -235,6 +232,34 @@ int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
 
 	return 0;
 }
+
+int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
+{
+	int ret;
+
+	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
+
+	if (offset > MC13XXX_NUMREGS)
+		return -EINVAL;
+
+	ret = mc13xxx_spi_reg_read(mc13xxx, offset, val);
+	dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
+
+	return ret;
+}
+EXPORT_SYMBOL(mc13xxx_reg_read);
+
+int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
+{
+	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
+
+	dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
+
+	if (offset > MC13XXX_NUMREGS || val > 0xffffff)
+		return -EINVAL;
+
+	return mc13xxx_spi_reg_write(mc13xxx, offset, val);
+}
 EXPORT_SYMBOL(mc13xxx_reg_write);
 
 int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
@@ -439,7 +464,7 @@ static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
 			if (handled == IRQ_HANDLED)
 				num_handled++;
 		} else {
-			dev_err(&mc13xxx->spidev->dev,
+			dev_err(mc13xxx->dev,
 					"BUG: irq %u but no handler\n",
 					baseirq + irq);
 
@@ -475,25 +500,23 @@ static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
 	return IRQ_RETVAL(handled);
 }
 
-enum mc13xxx_id {
-	MC13XXX_ID_MC13783,
-	MC13XXX_ID_MC13892,
-	MC13XXX_ID_INVALID,
-};
-
 static const char *mc13xxx_chipname[] = {
 	[MC13XXX_ID_MC13783] = "mc13783",
 	[MC13XXX_ID_MC13892] = "mc13892",
 };
 
 #define maskval(reg, mask)	(((reg) & (mask)) >> __ffs(mask))
-static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
+static int mc13xxx_identify(struct mc13xxx *mc13xxx)
 {
 	u32 icid;
 	u32 revision;
-	const char *name;
 	int ret;
 
+	/*
+	 * Get the generation ID from register 46, as apparently some older
+	 * IC revisions only have this info at this location. Newer ICs seem to
+	 * have both.
+	 */
 	ret = mc13xxx_reg_read(mc13xxx, 46, &icid);
 	if (ret)
 		return ret;
@@ -502,26 +525,23 @@ static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
 
 	switch (icid) {
 	case 2:
-		*id = MC13XXX_ID_MC13783;
-		name = "mc13783";
+		mc13xxx->ictype = MC13XXX_ID_MC13783;
 		break;
 	case 7:
-		*id = MC13XXX_ID_MC13892;
-		name = "mc13892";
+		mc13xxx->ictype = MC13XXX_ID_MC13892;
 		break;
 	default:
-		*id = MC13XXX_ID_INVALID;
+		mc13xxx->ictype = MC13XXX_ID_INVALID;
 		break;
 	}
 
-	if (*id == MC13XXX_ID_MC13783 || *id == MC13XXX_ID_MC13892) {
+	if (mc13xxx->ictype == MC13XXX_ID_MC13783 ||
+			mc13xxx->ictype == MC13XXX_ID_MC13892) {
 		ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
-		if (ret)
-			return ret;
 
-		dev_info(&mc13xxx->spidev->dev, "%s: rev: %d.%d, "
+		dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
 				"fin: %d, fab: %d, icid: %d/%d\n",
-				mc13xxx_chipname[*id],
+				mc13xxx_chipname[mc13xxx->ictype],
 				maskval(revision, MC13XXX_REVISION_REVFULL),
 				maskval(revision, MC13XXX_REVISION_REVMETAL),
 				maskval(revision, MC13XXX_REVISION_FIN),
@@ -530,26 +550,12 @@ static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
 				maskval(revision, MC13XXX_REVISION_ICIDCODE));
 	}
 
-	if (*id != MC13XXX_ID_INVALID) {
-		const struct spi_device_id *devid =
-			spi_get_device_id(mc13xxx->spidev);
-		if (!devid || devid->driver_data != *id)
-			dev_warn(&mc13xxx->spidev->dev, "device id doesn't "
-					"match auto detection!\n");
-	}
-
-	return 0;
+	return (mc13xxx->ictype == MC13XXX_ID_INVALID) ? -ENODEV : 0;
 }
 
 static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
 {
-	const struct spi_device_id *devid =
-		spi_get_device_id(mc13xxx->spidev);
-
-	if (!devid)
-		return NULL;
-
-	return mc13xxx_chipname[devid->driver_data];
+	return mc13xxx_chipname[mc13xxx->ictype];
 }
 
 int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
@@ -589,7 +595,7 @@ int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
 	};
 	init_completion(&adcdone_data.done);
 
-	dev_dbg(&mc13xxx->spidev->dev, "%s\n", __func__);
+	dev_dbg(mc13xxx->dev, "%s\n", __func__);
 
 	mc13xxx_lock(mc13xxx);
 
@@ -631,7 +637,7 @@ int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
 		return -EINVAL;
 	}
 
-	dev_dbg(&mc13xxx->spidev->dev, "%s: request irq\n", __func__);
+	dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
 	mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
 			mc13xxx_handler_adcdone, __func__, &adcdone_data);
 	mc13xxx_irq_ack(mc13xxx, MC13XXX_IRQ_ADCDONE);
@@ -689,7 +695,7 @@ static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
 	if (!cell.name)
 		return -ENOMEM;
 
-	return mfd_add_devices(&mc13xxx->spidev->dev, -1, &cell, 1, NULL, 0);
+	return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0);
 }
 
 static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
@@ -700,7 +706,7 @@ static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
 #ifdef CONFIG_OF
 static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 {
-	struct device_node *np = mc13xxx->spidev->dev.of_node;
+	struct device_node *np = mc13xxx->dev.of_node;
 
 	if (!np)
 		return -ENODEV;
@@ -746,13 +752,17 @@ static const struct of_device_id mc13xxx_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
 
-static int mc13xxx_probe(struct spi_device *spi)
+static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+		struct mc13xxx_platform_data *pdata, int irq);
+
+static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx);
+
+static int mc13xxx_spi_probe(struct spi_device *spi)
 {
 	const struct of_device_id *of_id;
 	struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
 	struct mc13xxx *mc13xxx;
 	struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
-	enum mc13xxx_id id;
 	int ret;
 
 	of_id = of_match_device(mc13xxx_dt_ids, &spi->dev);
@@ -768,13 +778,34 @@ static int mc13xxx_probe(struct spi_device *spi)
 	spi->bits_per_word = 32;
 	spi_setup(spi);
 
+	mc13xxx->dev = &spi->dev;
 	mc13xxx->spidev = spi;
 
+	ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
+
+	if (ret) {
+		dev_set_drvdata(&spi->dev, NULL);
+	} else {
+		const struct spi_device_id *devid =
+			spi_get_device_id(mc13xxx->spidev);
+		if (!devid || devid->driver_data != mc13xxx->ictype)
+			dev_warn(mc13xxx->dev,
+				"device id doesn't match auto detection!\n");
+	}
+
+	return ret;
+}
+
+static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+		struct mc13xxx_platform_data *pdata, int irq)
+{
+	int ret;
+
 	mutex_init(&mc13xxx->lock);
 	mc13xxx_lock(mc13xxx);
 
-	ret = mc13xxx_identify(mc13xxx, &id);
-	if (ret || id == MC13XXX_ID_INVALID)
+	ret = mc13xxx_identify(mc13xxx);
+	if (ret)
 		goto err_revision;
 
 	/* mask all irqs */
@@ -786,18 +817,19 @@ static int mc13xxx_probe(struct spi_device *spi)
 	if (ret)
 		goto err_mask;
 
-	ret = request_threaded_irq(spi->irq, NULL, mc13xxx_irq_thread,
+	ret = request_threaded_irq(irq, NULL, mc13xxx_irq_thread,
 			IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
 
 	if (ret) {
 err_mask:
 err_revision:
 		mc13xxx_unlock(mc13xxx);
-		dev_set_drvdata(&spi->dev, NULL);
 		kfree(mc13xxx);
 		return ret;
 	}
 
+	mc13xxx->irq = irq;
+
 	mc13xxx_unlock(mc13xxx);
 
 	if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
@@ -831,39 +863,44 @@ err_revision:
 	return 0;
 }
 
-static int __devexit mc13xxx_remove(struct spi_device *spi)
+static int __devexit mc13xxx_spi_remove(struct spi_device *spi)
 {
 	struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
 
-	free_irq(mc13xxx->spidev->irq, mc13xxx);
+	mc13xxx_common_cleanup(mc13xxx);
 
-	mfd_remove_devices(&spi->dev);
+	return 0;
+}
 
-	kfree(mc13xxx);
+static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
+{
+	free_irq(mc13xxx->irq, mc13xxx);
 
-	return 0;
+	mfd_remove_devices(mc13xxx->dev);
+
+	kfree(mc13xxx);
 }
 
-static struct spi_driver mc13xxx_driver = {
+static struct spi_driver mc13xxx_spi_driver = {
 	.id_table = mc13xxx_device_id,
 	.driver = {
 		.name = "mc13xxx",
 		.owner = THIS_MODULE,
 		.of_match_table = mc13xxx_dt_ids,
 	},
-	.probe = mc13xxx_probe,
-	.remove = __devexit_p(mc13xxx_remove),
+	.probe = mc13xxx_spi_probe,
+	.remove = __devexit_p(mc13xxx_spi_remove),
 };
 
 static int __init mc13xxx_init(void)
 {
-	return spi_register_driver(&mc13xxx_driver);
+	return spi_register_driver(&mc13xxx_spi_driver);
 }
 subsys_initcall(mc13xxx_init);
 
 static void __exit mc13xxx_exit(void)
 {
-	spi_unregister_driver(&mc13xxx_driver);
+	spi_unregister_driver(&mc13xxx_spi_driver);
 }
 module_exit(mc13xxx_exit);
 
-- 
1.7.3.4



From marc at cpdesign.com.au  Mon Mar 19 00:03:56 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Mon, 19 Mar 2012 15:03:56 +1100
Subject: [PATCH v4 2/4] mfd: mc13xxx-core: use regmap for register access
In-Reply-To: <1332129838-7080-1-git-send-email-marc@cpdesign.com.au>
References: <1332129838-7080-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1332129838-7080-3-git-send-email-marc@cpdesign.com.au>

This change converts the mc13xxx core to use regmap rather than direct
spi r/w.
The spidev member of mc13xxx struct becomes redundant and is removed.
Extra debugging aids are added to mc13xxx_reg_rmw.
Mutex init is moved to before regmap init.

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/mfd/mc13xxx-core.c |  111 +++++++++++++-------------------------------
 1 files changed, 33 insertions(+), 78 deletions(-)

diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index 0753402..2c35d6d 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -21,6 +21,8 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
+#include <linux/regmap.h>
+#include <linux/err.h>
 
 enum mc13xxx_id {
 	MC13XXX_ID_MC13783,
@@ -29,7 +31,7 @@ enum mc13xxx_id {
 };
 
 struct mc13xxx {
-	struct spi_device *spidev;
+	struct regmap *regmap;
 
 	struct device *dev;
 	enum mc13xxx_id ictype;
@@ -172,67 +174,6 @@ void mc13xxx_unlock(struct mc13xxx *mc13xxx)
 }
 EXPORT_SYMBOL(mc13xxx_unlock);
 
-#define MC13XXX_REGOFFSET_SHIFT 25
-static int mc13xxx_spi_reg_read(struct mc13xxx *mc13xxx,
-				unsigned int offset, u32 *val)
-{
-	struct spi_transfer t;
-	struct spi_message m;
-	int ret;
-
-	*val = offset << MC13XXX_REGOFFSET_SHIFT;
-
-	memset(&t, 0, sizeof(t));
-
-	t.tx_buf = val;
-	t.rx_buf = val;
-	t.len = sizeof(u32);
-
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	ret = spi_sync(mc13xxx->spidev, &m);
-
-	/* error in message.status implies error return from spi_sync */
-	BUG_ON(!ret && m.status);
-
-	if (ret)
-		return ret;
-
-	*val &= 0xffffff;
-
-	return 0;
-}
-
-static int mc13xxx_spi_reg_write(struct mc13xxx *mc13xxx, unsigned int offset,
-		u32 val)
-{
-	u32 buf;
-	struct spi_transfer t;
-	struct spi_message m;
-	int ret;
-
-	buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
-
-	memset(&t, 0, sizeof(t));
-
-	t.tx_buf = &buf;
-	t.rx_buf = &buf;
-	t.len = sizeof(u32);
-
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	ret = spi_sync(mc13xxx->spidev, &m);
-
-	BUG_ON(!ret && m.status);
-
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
 int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 {
 	int ret;
@@ -242,7 +183,7 @@ int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
 	if (offset > MC13XXX_NUMREGS)
 		return -EINVAL;
 
-	ret = mc13xxx_spi_reg_read(mc13xxx, offset, val);
+	ret = regmap_read(mc13xxx->regmap, offset, val);
 	dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
 
 	return ret;
@@ -258,25 +199,19 @@ int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
 	if (offset > MC13XXX_NUMREGS || val > 0xffffff)
 		return -EINVAL;
 
-	return mc13xxx_spi_reg_write(mc13xxx, offset, val);
+	return regmap_write(mc13xxx->regmap, offset, val);
 }
 EXPORT_SYMBOL(mc13xxx_reg_write);
 
 int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
 		u32 mask, u32 val)
 {
-	int ret;
-	u32 valread;
-
+	BUG_ON(!mutex_is_locked(&mc13xxx->lock));
 	BUG_ON(val & ~mask);
+	dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
+			offset, val, mask);
 
-	ret = mc13xxx_reg_read(mc13xxx, offset, &valread);
-	if (ret)
-		return ret;
-
-	valread = (valread & ~mask) | val;
-
-	return mc13xxx_reg_write(mc13xxx, offset, valread);
+	return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
 }
 EXPORT_SYMBOL(mc13xxx_reg_rmw);
 
@@ -752,6 +687,16 @@ static const struct of_device_id mc13xxx_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
 
+static struct regmap_config mc13xxx_regmap_spi_config = {
+	.reg_bits = 7,
+	.pad_bits = 1,
+	.val_bits = 24,
+
+	.max_register = MC13XXX_NUMREGS,
+
+	.cache_type = REGCACHE_NONE,
+};
+
 static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
 		struct mc13xxx_platform_data *pdata, int irq);
 
@@ -776,10 +721,19 @@ static int mc13xxx_spi_probe(struct spi_device *spi)
 	dev_set_drvdata(&spi->dev, mc13xxx);
 	spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
 	spi->bits_per_word = 32;
-	spi_setup(spi);
 
 	mc13xxx->dev = &spi->dev;
-	mc13xxx->spidev = spi;
+	mutex_init(&mc13xxx->lock);
+
+	mc13xxx->regmap = regmap_init_spi(spi, &mc13xxx_regmap_spi_config);
+	if (IS_ERR(mc13xxx->regmap)) {
+		ret = PTR_ERR(mc13xxx->regmap);
+		dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
+				ret);
+		dev_set_drvdata(&spi->dev, NULL);
+		kfree(mc13xxx);
+		return ret;
+	}
 
 	ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
 
@@ -787,7 +741,7 @@ static int mc13xxx_spi_probe(struct spi_device *spi)
 		dev_set_drvdata(&spi->dev, NULL);
 	} else {
 		const struct spi_device_id *devid =
-			spi_get_device_id(mc13xxx->spidev);
+			spi_get_device_id(spi);
 		if (!devid || devid->driver_data != mc13xxx->ictype)
 			dev_warn(mc13xxx->dev,
 				"device id doesn't match auto detection!\n");
@@ -801,7 +755,6 @@ static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
 {
 	int ret;
 
-	mutex_init(&mc13xxx->lock);
 	mc13xxx_lock(mc13xxx);
 
 	ret = mc13xxx_identify(mc13xxx);
@@ -878,6 +831,8 @@ static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
 
 	mfd_remove_devices(mc13xxx->dev);
 
+	regmap_exit(mc13xxx->regmap);
+
 	kfree(mc13xxx);
 }
 
-- 
1.7.3.4



From marc at cpdesign.com.au  Mon Mar 19 00:03:57 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Mon, 19 Mar 2012 15:03:57 +1100
Subject: [PATCH v4 3/4] mfd: mc13xxx-core: Move spi specific code into
 separate module.
In-Reply-To: <1332129838-7080-1-git-send-email-marc@cpdesign.com.au>
References: <1332129838-7080-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1332129838-7080-4-git-send-email-marc@cpdesign.com.au>

All spi specific code is moved into a new module. The mc13xxx struct
moves to a new local include file by necessity.

A new config choice selects the SPI bus type support and by default is
value of SPI_MASTER to remain compatible with existing configs.

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/mfd/Kconfig        |   15 ++++-
 drivers/mfd/Makefile       |    1 +
 drivers/mfd/mc13xxx-core.c |  148 ++------------------------------------------
 drivers/mfd/mc13xxx-spi.c  |  140 +++++++++++++++++++++++++++++++++++++++++
 drivers/mfd/mc13xxx.h      |   45 +++++++++++++
 5 files changed, 203 insertions(+), 146 deletions(-)
 create mode 100644 drivers/mfd/mc13xxx-spi.c
 create mode 100644 drivers/mfd/mc13xxx.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index cd13e9f..501fee5 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -577,12 +577,21 @@ config MFD_MC13XXX
 	select MFD_CORE
 	select MFD_MC13783
 	help
-	  Support for the Freescale (Atlas) PMIC and audio CODECs
-	  MC13783 and MC13892.
-	  This driver provides common support for accessing  the device,
+	  Enable support for the Freescale MC13783 and MC13892 PMICs.
+	  This driver provides common support for accessing the device,
 	  additional drivers must be enabled in order to use the
 	  functionality of the device.
 
+if MFD_MC13XXX
+
+config MFD_MC13XXX_SPI
+	tristate "MC13xxx SPI interface" if SPI_MASTER
+	default SPI_MASTER
+	help
+	  Select this if your MC13xxx is connected via an SPI bus.
+
+endif
+
 config ABX500_CORE
 	bool "ST-Ericsson ABX500 Mixed Signal Circuit register functions"
 	default y if ARCH_U300 || ARCH_U8500
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index b953bab..2dc66ed 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_TWL6030_PWM)	+= twl6030-pwm.o
 obj-$(CONFIG_TWL6040_CORE)	+= twl6040-core.o twl6040-irq.o
 
 obj-$(CONFIG_MFD_MC13XXX)	+= mc13xxx-core.o
+obj-$(CONFIG_MFD_MC13XXX_SPI)	+= mc13xxx-spi.o
 
 obj-$(CONFIG_MFD_CORE)		+= mfd-core.o
 
diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index 2c35d6d..31dbf91 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -15,36 +15,13 @@
 #include <linux/platform_device.h>
 #include <linux/mutex.h>
 #include <linux/interrupt.h>
-#include <linux/spi/spi.h>
 #include <linux/mfd/core.h>
 #include <linux/mfd/mc13xxx.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
-#include <linux/regmap.h>
-#include <linux/err.h>
 
-enum mc13xxx_id {
-	MC13XXX_ID_MC13783,
-	MC13XXX_ID_MC13892,
-	MC13XXX_ID_INVALID,
-};
-
-struct mc13xxx {
-	struct regmap *regmap;
-
-	struct device *dev;
-	enum mc13xxx_id ictype;
-
-	struct mutex lock;
-	int irq;
-	int flags;
-
-	irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
-	void *irqdata[MC13XXX_NUM_IRQ];
-
-	int adcflags;
-};
+#include "mc13xxx.h"
 
 #define MC13XXX_IRQSTAT0	0
 #define MC13XXX_IRQSTAT0_ADCDONEI	(1 << 0)
@@ -151,8 +128,6 @@ struct mc13xxx {
 
 #define MC13XXX_ADC2		45
 
-#define MC13XXX_NUMREGS 0x3f
-
 void mc13xxx_lock(struct mc13xxx *mc13xxx)
 {
 	if (!mutex_trylock(&mc13xxx->lock)) {
@@ -667,90 +642,7 @@ static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 }
 #endif
 
-static const struct spi_device_id mc13xxx_device_id[] = {
-	{
-		.name = "mc13783",
-		.driver_data = MC13XXX_ID_MC13783,
-	}, {
-		.name = "mc13892",
-		.driver_data = MC13XXX_ID_MC13892,
-	}, {
-		/* sentinel */
-	}
-};
-MODULE_DEVICE_TABLE(spi, mc13xxx_device_id);
-
-static const struct of_device_id mc13xxx_dt_ids[] = {
-	{ .compatible = "fsl,mc13783", .data = (void *) MC13XXX_ID_MC13783, },
-	{ .compatible = "fsl,mc13892", .data = (void *) MC13XXX_ID_MC13892, },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
-
-static struct regmap_config mc13xxx_regmap_spi_config = {
-	.reg_bits = 7,
-	.pad_bits = 1,
-	.val_bits = 24,
-
-	.max_register = MC13XXX_NUMREGS,
-
-	.cache_type = REGCACHE_NONE,
-};
-
-static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
-		struct mc13xxx_platform_data *pdata, int irq);
-
-static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx);
-
-static int mc13xxx_spi_probe(struct spi_device *spi)
-{
-	const struct of_device_id *of_id;
-	struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
-	struct mc13xxx *mc13xxx;
-	struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
-	int ret;
-
-	of_id = of_match_device(mc13xxx_dt_ids, &spi->dev);
-	if (of_id)
-		sdrv->id_table = &mc13xxx_device_id[(enum mc13xxx_id) of_id->data];
-
-	mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
-	if (!mc13xxx)
-		return -ENOMEM;
-
-	dev_set_drvdata(&spi->dev, mc13xxx);
-	spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
-	spi->bits_per_word = 32;
-
-	mc13xxx->dev = &spi->dev;
-	mutex_init(&mc13xxx->lock);
-
-	mc13xxx->regmap = regmap_init_spi(spi, &mc13xxx_regmap_spi_config);
-	if (IS_ERR(mc13xxx->regmap)) {
-		ret = PTR_ERR(mc13xxx->regmap);
-		dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
-				ret);
-		dev_set_drvdata(&spi->dev, NULL);
-		kfree(mc13xxx);
-		return ret;
-	}
-
-	ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
-
-	if (ret) {
-		dev_set_drvdata(&spi->dev, NULL);
-	} else {
-		const struct spi_device_id *devid =
-			spi_get_device_id(spi);
-		if (!devid || devid->driver_data != mc13xxx->ictype)
-			dev_warn(mc13xxx->dev,
-				"device id doesn't match auto detection!\n");
-	}
-
-	return ret;
-}
-
-static int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+int mc13xxx_common_init(struct mc13xxx *mc13xxx,
 		struct mc13xxx_platform_data *pdata, int irq)
 {
 	int ret;
@@ -815,17 +707,9 @@ err_revision:
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(mc13xxx_common_init);
 
-static int __devexit mc13xxx_spi_remove(struct spi_device *spi)
-{
-	struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
-
-	mc13xxx_common_cleanup(mc13xxx);
-
-	return 0;
-}
-
-static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
+void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
 {
 	free_irq(mc13xxx->irq, mc13xxx);
 
@@ -835,29 +719,7 @@ static void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx)
 
 	kfree(mc13xxx);
 }
-
-static struct spi_driver mc13xxx_spi_driver = {
-	.id_table = mc13xxx_device_id,
-	.driver = {
-		.name = "mc13xxx",
-		.owner = THIS_MODULE,
-		.of_match_table = mc13xxx_dt_ids,
-	},
-	.probe = mc13xxx_spi_probe,
-	.remove = __devexit_p(mc13xxx_spi_remove),
-};
-
-static int __init mc13xxx_init(void)
-{
-	return spi_register_driver(&mc13xxx_spi_driver);
-}
-subsys_initcall(mc13xxx_init);
-
-static void __exit mc13xxx_exit(void)
-{
-	spi_unregister_driver(&mc13xxx_spi_driver);
-}
-module_exit(mc13xxx_exit);
+EXPORT_SYMBOL_GPL(mc13xxx_common_cleanup);
 
 MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>");
diff --git a/drivers/mfd/mc13xxx-spi.c b/drivers/mfd/mc13xxx-spi.c
new file mode 100644
index 0000000..3fcdab3
--- /dev/null
+++ b/drivers/mfd/mc13xxx-spi.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * loosely based on an earlier driver that has
+ * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/mc13xxx.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/err.h>
+#include <linux/spi/spi.h>
+
+#include "mc13xxx.h"
+
+static const struct spi_device_id mc13xxx_device_id[] = {
+	{
+		.name = "mc13783",
+		.driver_data = MC13XXX_ID_MC13783,
+	}, {
+		.name = "mc13892",
+		.driver_data = MC13XXX_ID_MC13892,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(spi, mc13xxx_device_id);
+
+static const struct of_device_id mc13xxx_dt_ids[] = {
+	{ .compatible = "fsl,mc13783", .data = (void *) MC13XXX_ID_MC13783, },
+	{ .compatible = "fsl,mc13892", .data = (void *) MC13XXX_ID_MC13892, },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
+
+static struct regmap_config mc13xxx_regmap_spi_config = {
+	.reg_bits = 7,
+	.pad_bits = 1,
+	.val_bits = 24,
+
+	.max_register = MC13XXX_NUMREGS,
+
+	.cache_type = REGCACHE_NONE,
+};
+
+static int mc13xxx_spi_probe(struct spi_device *spi)
+{
+	const struct of_device_id *of_id;
+	struct spi_driver *sdrv = to_spi_driver(spi->dev.driver);
+	struct mc13xxx *mc13xxx;
+	struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
+	int ret;
+
+	of_id = of_match_device(mc13xxx_dt_ids, &spi->dev);
+	if (of_id)
+		sdrv->id_table = &mc13xxx_device_id[(enum mc13xxx_id) of_id->data];
+
+	mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
+	if (!mc13xxx)
+		return -ENOMEM;
+
+	dev_set_drvdata(&spi->dev, mc13xxx);
+	spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
+	spi->bits_per_word = 32;
+
+	mc13xxx->dev = &spi->dev;
+	mutex_init(&mc13xxx->lock);
+
+	mc13xxx->regmap = regmap_init_spi(spi, &mc13xxx_regmap_spi_config);
+	if (IS_ERR(mc13xxx->regmap)) {
+		ret = PTR_ERR(mc13xxx->regmap);
+		dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
+				ret);
+		dev_set_drvdata(&spi->dev, NULL);
+		kfree(mc13xxx);
+		return ret;
+	}
+
+	ret = mc13xxx_common_init(mc13xxx, pdata, spi->irq);
+
+	if (ret) {
+		dev_set_drvdata(&spi->dev, NULL);
+	} else {
+		const struct spi_device_id *devid =
+			spi_get_device_id(spi);
+		if (!devid || devid->driver_data != mc13xxx->ictype)
+			dev_warn(mc13xxx->dev,
+				"device id doesn't match auto detection!\n");
+	}
+
+	return ret;
+}
+
+static int __devexit mc13xxx_spi_remove(struct spi_device *spi)
+{
+	struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
+
+	mc13xxx_common_cleanup(mc13xxx);
+
+	return 0;
+}
+
+static struct spi_driver mc13xxx_spi_driver = {
+	.id_table = mc13xxx_device_id,
+	.driver = {
+		.name = "mc13xxx",
+		.owner = THIS_MODULE,
+		.of_match_table = mc13xxx_dt_ids,
+	},
+	.probe = mc13xxx_spi_probe,
+	.remove = __devexit_p(mc13xxx_spi_remove),
+};
+
+static int __init mc13xxx_init(void)
+{
+	return spi_register_driver(&mc13xxx_spi_driver);
+}
+subsys_initcall(mc13xxx_init);
+
+static void __exit mc13xxx_exit(void)
+{
+	spi_unregister_driver(&mc13xxx_spi_driver);
+}
+module_exit(mc13xxx_exit);
+
+MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
+MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/mc13xxx.h b/drivers/mfd/mc13xxx.h
new file mode 100644
index 0000000..bbba06f
--- /dev/null
+++ b/drivers/mfd/mc13xxx.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2012 Creative Product Design
+ * Marc Reilly <marc at cpdesign.com.au>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#ifndef __DRIVERS_MFD_MC13XXX_H
+#define __DRIVERS_MFD_MC13XXX_H
+
+#include <linux/mutex.h>
+#include <linux/regmap.h>
+#include <linux/mfd/mc13xxx.h>
+
+enum mc13xxx_id {
+	MC13XXX_ID_MC13783,
+	MC13XXX_ID_MC13892,
+	MC13XXX_ID_INVALID,
+};
+
+#define MC13XXX_NUMREGS 0x3f
+
+struct mc13xxx {
+	struct regmap *regmap;
+
+	struct device *dev;
+	enum mc13xxx_id ictype;
+
+	struct mutex lock;
+	int irq;
+	int flags;
+
+	irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
+	void *irqdata[MC13XXX_NUM_IRQ];
+
+	int adcflags;
+};
+
+int mc13xxx_common_init(struct mc13xxx *mc13xxx,
+		struct mc13xxx_platform_data *pdata, int irq);
+
+void mc13xxx_common_cleanup(struct mc13xxx *mc13xxx);
+
+#endif /* __DRIVERS_MFD_MC13XXX_H */
-- 
1.7.3.4



From marc at cpdesign.com.au  Mon Mar 19 00:03:58 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Mon, 19 Mar 2012 15:03:58 +1100
Subject: [PATCH v4 4/4] mfd: mc13xxx: Add i2c driver
In-Reply-To: <1332129838-7080-1-git-send-email-marc@cpdesign.com.au>
References: <1332129838-7080-1-git-send-email-marc@cpdesign.com.au>
Message-ID: <1332129838-7080-5-git-send-email-marc@cpdesign.com.au>

Adds support for mc13xxx family ICs connected via i2c.

Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
---
 drivers/mfd/Kconfig       |    8 +++-
 drivers/mfd/Makefile      |    1 +
 drivers/mfd/mc13xxx-i2c.c |  128 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 136 insertions(+), 1 deletions(-)
 create mode 100644 drivers/mfd/mc13xxx-i2c.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 501fee5..3a039ff 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -573,7 +573,7 @@ config MFD_MC13783
 
 config MFD_MC13XXX
 	tristate "Support Freescale MC13783 and MC13892"
-	depends on SPI_MASTER
+	depends on SPI_MASTER || I2C
 	select MFD_CORE
 	select MFD_MC13783
 	help
@@ -590,6 +590,12 @@ config MFD_MC13XXX_SPI
 	help
 	  Select this if your MC13xxx is connected via an SPI bus.
 
+config MFD_MC13XXX_I2C
+	tristate "MC13xxx I2C interface" if I2C
+	default I2C
+	help
+	  Select this if your MC13xxx is connected via an I2C bus.
+
 endif
 
 config ABX500_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 2dc66ed..6d4566f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_TWL6040_CORE)	+= twl6040-core.o twl6040-irq.o
 
 obj-$(CONFIG_MFD_MC13XXX)	+= mc13xxx-core.o
 obj-$(CONFIG_MFD_MC13XXX_SPI)	+= mc13xxx-spi.o
+obj-$(CONFIG_MFD_MC13XXX_I2C)	+= mc13xxx-i2c.o
 
 obj-$(CONFIG_MFD_CORE)		+= mfd-core.o
 
diff --git a/drivers/mfd/mc13xxx-i2c.c b/drivers/mfd/mc13xxx-i2c.c
new file mode 100644
index 0000000..d22501d
--- /dev/null
+++ b/drivers/mfd/mc13xxx-i2c.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2009-2010 Creative Product Design
+ * Marc Reilly marc at cpdesign.com.au
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/mc13xxx.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/i2c.h>
+#include <linux/err.h>
+
+#include "mc13xxx.h"
+
+static const struct i2c_device_id mc13xxx_i2c_device_id[] = {
+	{
+		.name = "mc13892",
+		.driver_data = MC13XXX_ID_MC13892,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(i2c, mc13xxx_i2c_device_id);
+
+static const struct of_device_id mc13xxx_dt_ids[] = {
+	{
+		.compatible = "fsl,mc13892",
+		.data = (void *) &mc13xxx_i2c_device_id[0],
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(of, mc13xxx_dt_ids);
+
+static struct regmap_config mc13xxx_regmap_i2c_config = {
+	.reg_bits = 8,
+	.val_bits = 24,
+
+	.max_register = MC13XXX_NUMREGS,
+
+	.cache_type = REGCACHE_NONE,
+};
+
+static int mc13xxx_i2c_probe(struct i2c_client *client,
+		const struct i2c_device_id *id)
+{
+	const struct of_device_id *of_id;
+	struct i2c_driver *idrv = to_i2c_driver(client->dev.driver);
+	struct mc13xxx *mc13xxx;
+	struct mc13xxx_platform_data *pdata = dev_get_platdata(&client->dev);
+	int ret;
+
+	of_id = of_match_device(mc13xxx_dt_ids, &client->dev);
+	if (of_id)
+		idrv->id_table = (const struct i2c_device_id*) of_id->data;
+
+	mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
+	if (!mc13xxx)
+		return -ENOMEM;
+
+	dev_set_drvdata(&client->dev, mc13xxx);
+
+	mc13xxx->dev = &client->dev;
+	mutex_init(&mc13xxx->lock);
+
+	mc13xxx->regmap = regmap_init_i2c(client, &mc13xxx_regmap_i2c_config);
+	if (IS_ERR(mc13xxx->regmap)) {
+		ret = PTR_ERR(mc13xxx->regmap);
+		dev_err(mc13xxx->dev, "Failed to initialize register map: %d\n",
+				ret);
+		dev_set_drvdata(&client->dev, NULL);
+		kfree(mc13xxx);
+		return ret;
+	}
+
+	ret = mc13xxx_common_init(mc13xxx, pdata, client->irq);
+
+	if (ret == 0 && (id->driver_data != mc13xxx->ictype))
+		dev_warn(mc13xxx->dev,
+				"device id doesn't match auto detection!\n");
+
+	return ret;
+}
+
+static int __devexit mc13xxx_i2c_remove(struct i2c_client *client)
+{
+	struct mc13xxx *mc13xxx = dev_get_drvdata(&client->dev);
+
+	mc13xxx_common_cleanup(mc13xxx);
+
+	return 0;
+}
+
+static struct i2c_driver mc13xxx_i2c_driver = {
+	.id_table = mc13xxx_i2c_device_id,
+	.driver = {
+		.owner = THIS_MODULE,
+		.name = "mc13xxx",
+		.of_match_table = mc13xxx_dt_ids,
+	},
+	.probe = mc13xxx_i2c_probe,
+	.remove = __devexit_p(mc13xxx_i2c_remove),
+};
+
+static int __init mc13xxx_i2c_init(void)
+{
+	return i2c_add_driver(&mc13xxx_i2c_driver);
+}
+subsys_initcall(mc13xxx_i2c_init);
+
+static void __exit mc13xxx_i2c_exit(void)
+{
+	i2c_del_driver(&mc13xxx_i2c_driver);
+}
+module_exit(mc13xxx_i2c_exit);
+
+MODULE_DESCRIPTION("i2c driver for Freescale MC13XXX PMIC");
+MODULE_AUTHOR("Marc Reilly <marc at cpdesign.com.au");
+MODULE_LICENSE("GPL v2");
-- 
1.7.3.4



From gerg at snapgear.com  Mon Mar 19 01:01:41 2012
From: gerg at snapgear.com (Greg Ungerer)
Date: Mon, 19 Mar 2012 15:01:41 +1000
Subject: Atmel at91x40 ("EB01" eval board) resurected
In-Reply-To: <20120317164345.4f20beef@skate>
References: <CALz2mmXcAk9ZOsAzKMbKVVJ2+Et02+Gxj_z6xSgukC5LjgJTLg@mail.gmail.com>
 <20120317164345.4f20beef@skate>
Message-ID: <4F66BDB5.5020600@snapgear.com>

Hi Thomas,

On 18/03/12 01:43, Thomas Petazzoni wrote:
> Le Thu, 22 Dec 2011 22:18:53 -0500,
> Phil Budne<phil at ultimate.com>  a ??crit :
>
>> I decided to see if I could bring up current kernel sources under
>> skyeye  (at91x40 simulation).
>
> Very interesting, thanks. Your patches indeed allow the AT91x40 kernel
> to boot under SkyEye, while the unpatched Linux kernel does not,
> apparently.
>
> Greg, it seems you are saying that the mainline kernel, unchanged,
> boots under SkyEye.

No, I didn't mean to imply that in my response (
http://lists.infradead.org/pipermail/linux-arm-kernel/2011-December/078670.html).
It has worked in the past, but I haven't run it for a few kernel
versions now.

I was hoping that Phil would respond to the couple of questions I
had about differences, but he never did.


> Could you share your kernel configuration and
> SkyEye configuration?

Yeah, its in mainline. Its one of the defconfigs:

   arch/arm/configs/at91x40_defconfig
   

>> Runs on locally modified skyeye
>>   based on skyeye-v1.2_Rel.tar (had trouble building latest release)
>>   adds interrupt driven UART output
>>   tweaked for programmed I/O UART input
>>   fix for loading XIP data section (load at physical, not virtual address)
>
> Would you mind publishing your changes to SkyEye? So far, I'm blocked
> because of the lack of interrupt driver UART output.
>
> Do you plan on further pushing those AT91x40 changes?

It would be really nice to get Phil's changes in a form that can be
applied to mainline.

Regards
Greg


------------------------------------------------------------------------
Greg Ungerer  --  Principal Engineer        EMAIL:     gerg at snapgear.com
SnapGear Group, McAfee                      PHONE:       +61 7 3435 2888
8 Gardner Close                             FAX:         +61 7 3217 5323
Milton, QLD, 4064, Australia                WEB: http://www.SnapGear.com


From shawn.guo at linaro.org  Mon Mar 19 01:38:04 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 19 Mar 2012 13:38:04 +0800
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <4F6403CD.8020509@codeaurora.org>
References: <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
 <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
 <4F6403CD.8020509@codeaurora.org>
Message-ID: <20120319053801.GB31410@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 08:23:57PM -0700, Saravana Kannan wrote:
...
> Hi Mike,
> 
> I already took a quick look at the v7 series, but I thought this
> thread has more relevant context for my response. So, responding
> here.
> 
> I'm with Sascha on creating a clk_internal/clk_initializer and
> removing clk_hw. You had asked about the benefits of his suggestion
> in one of the earlier threads. I'm sure I have told some of these
> reasons I don't like clk_hw, but repeating my points here for others
> to chime in.
> 
> I used to be a huge proponent for using macros for clocks in our
> internal tree. All the clocks were constructed using macros (you
> will see it in the history of tree we publish in CAF). They quickly
> became unreadable when you have several hundreds of clocks. The
> biggest problem is that you can't quickly look at a clock's macro
> and figure out what the register offset or bit mask or shift value
> is. Our eyes/brains aren't meant for quickly parsing the commas and
> finding the n-th field or even remembering what the n-th field of
> each macro corresponds to. If it's actually broken out as fields in
> a struct, it's much easier to read. So, long story short, I think
> the well-intentioned helper macros will make code quite unreadable.
> 
While I second the idea of clk_initializer, using macros is not really
the thing to complain.  You can save using those macro helpers by
calling APIs clk_register_*().  But that does not solve the problem,
because those APIs also have a long argument list to fill.

-- 
Regards,
Shawn


From monstr at monstr.eu  Mon Mar 19 02:46:10 2012
From: monstr at monstr.eu (Michal Simek)
Date: Mon, 19 Mar 2012 07:46:10 +0100
Subject: [PATCH] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
References: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <4F66D632.5070107@monstr.eu>

Stephen Warren wrote:
> All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
> to avoid duplication.
> 
> All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
> parameterized version in Makefile.lib to avoid duplication.
> 
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> ---
> v2:
> * Fix blackfin's UIMAGE_LOADADDR in the ROMKERNEL case.
> * Fix missing ) on a variable reference in avr32 and sparc.
> * Only set those UIMAGE_* variables that the arch-specific Makefile hasn't
>   already set.
> * The patch series is now just this single patch which removes duplication;
>   I've dropped the Kconfig feature to allow use of -T kernel_noload for
>   now, since it looks like U-Boot is gaining direct zImage support.
> 
>  arch/arm/boot/Makefile          |   23 +++++++++--------------
>  arch/avr32/boot/images/Makefile |    9 +++------
>  arch/blackfin/boot/Makefile     |   19 ++++++++-----------
>  arch/microblaze/boot/Makefile   |   10 +++-------
>  arch/sh/boot/Makefile           |    8 ++------
>  arch/sparc/boot/Makefile        |    9 +++------
>  arch/unicore32/boot/Makefile    |   12 ++----------
>  scripts/Makefile.lib            |   24 ++++++++++++++++++++++++
>  8 files changed, 54 insertions(+), 60 deletions(-)

No problem for Microblaze.

Tested-by: Michal Simek <monstr at monstr.eu>

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian


From sfr at canb.auug.org.au  Mon Mar 19 02:47:43 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Mon, 19 Mar 2012 17:47:43 +1100
Subject: linux-next: manual merge of the arm-soc tree with the l2-mtd tree
Message-ID: <20120319174743.aff001d4f84e82cf4042277a@canb.auug.org.au>

Hi all,

Today's linux-next merge of the arm-soc tree got a conflict in
drivers/mtd/nand/atmel_nand.c between commit 4331c79c6895 ("mtd: do not
use plain 0 as NULL") from the l2-mtd tree and commit d6a016616ba8
("atmel/nand: add DT support") from the arm-soc tree.

The latter superceded the former, so I used that.
-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From LW at KARO-electronics.de  Mon Mar 19 02:54:33 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Mon, 19 Mar 2012 07:54:33 +0100
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120318184749.BB15D3E07BF@localhost>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
 <20120316030134.GA5161@shlinux2.ap.freescale.net>
 <20120318184749.BB15D3E07BF@localhost>
Message-ID: <20326.55337.249575.289067@ipc1.ka-ro>

Hi,

Grant Likely writes:
> On Fri, 16 Mar 2012 11:01:35 +0800, Dong Aisheng <aisheng.dong at freescale.com> wrote:
> > On Thu, Mar 15, 2012 at 07:22:04PM +0800, Lothar Wa?mann wrote:
> > > Hi,
> > > 
> > > Dong Aisheng writes:
> > > > On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa?mann wrote:
> > > > > Hi,
> > > > > 
> > > > > Dong Aisheng writes:
> > > > > > On Wed, Mar 14, 2012 at 10:16:43PM +0800, s.hauer at pengutronix.de wrote:
> > > > > > > On Wed, Mar 14, 2012 at 08:45:23PM +0800, Dong Aisheng wrote:
> > > > > > > > On Wed, Mar 14, 2012 at 01:23:51AM +0800, Grant Likely wrote:
> > > > > [...]
> > > > > > > > But it seems this needs pass mac address to fec driver via platforom data which is
> > > > > > > > not friendly to dt.
> > > > > > > > 
> > > > > > > > Another way may be changing fec driver to get the fixed part of mac address(first
> > > > > > > > two bytes) from device tree and read the left dynamical part from otp which i'm not
> > > > > > > > sure is better enough.
> > > > > > > > 
> > > > > > > > BTW, filling with zeros seems not work since it's invalid mac address.
> > > > > > > 
> > > > > > > Yes, that's the idea of using this value...
> > > > > > > 
> > > > > > But comparing to use an invalid value, why not just do not define that
> > > > > > local-mac-address property?
> > > > > > 
> > > > > Because a MAC address is by definition a GLOBALLY UNIQUE IDENTIFIER
> > > > > which is contrary to coding a "valid" default value for it somewhere!
> > > > > The owner of a certain MAC address range (OUI) is responsible for
> > > > > ensuring the uniqueness. Thus only they may assign a specific MAC
> > > > > address to a specific device.
> > > > > 
> > > > Yes, you're correct.
> > > > So i propose to read the MAC address from MX28 OTP in fec driver instead of
> > > > define it in device tree in my last mail.
> > > > http://www.spinics.net/lists/arm-kernel/msg165040.html
> > > > Do you have any comment on that way?
> > > > 
> > > That patch sets the OUI to the Freescale owned MAC range. Thus only
> > > Freescale products may be able to use the driver.
> > > 
> > No.
> > My proposal is only set the fixed part(first two octets) in board dts file,
> > each board knows it's value, and read the left 4 octets from OCOTP dynamically.
> > Obviously the freeescale board dts file is only for FSL platforms.
> > Other platforms can define their fix part of MAC address in their dts file.
> > 
> > > Anyway there is no definite spec how the MAC address(es) are stored
> > > in the fuse map. Thus reading the MAC from there is more or less
> > > platform specific.
> > > 
> > It's just provide one more option since there are customers storing the MAC
> > in the fuse map.
> 
> That should be straight forward to support; have a property that
> specifies the method used for fetching/calculating the MAC.
> 
Executable code stored inside a DT blob? ;)

> > > Currently I'm setting up the MAC address for our TX28 from the fuses
> > > in the platform code passed via platform_data, but that will obviously
> > > not work with DT.
> > > 
> > Non-dt can also use my proposal, then you only need to pass the fixed part of
> > MAC via platfrom data, the left will be read by fec driver.
> > 
> > > The correct way would probably be to pass the MAC from the bootloader
> > > via a DT blob. But that would require all bootloaders to be updated
> > > first to support DTS. :(
> > > 
> > But uboot will face the same problem that can not define a valid MAC
> > in dts, did i undertand correctly?
> > 
> > > An intermediate solution could be using OF_DEV_AUXDATA to pass a
> > > platform_data struct that may contain a MAC address set up by the
> > > platform code.
> > > 
> > Yes, it's a way but i'm afraid will not get accepted by dt people.
> 
> The problem remains; where does the platform code get the MAC address
> from?  The kernel has to devise it from *somewhere* and the best place
> for that should be in the MAC driver itself.
> 
The platform code knows how and where the MAC is stored on a specific
platform. The driver has no business in knowing platform details like
this. Thus only platform code (or the bootloader) can provide the MAC
to the driver.

> I've got no problem with the idea of only specifying the OUI in the DT
> and the driver extracting the remaining 3 bytes from the hardware.
> 
> In principle, that's the design intent for DT systems anyway; it
> describes things which cannot be probed from the hardware, or tells
> the OS how the data is encoded in the hardware.
> 
If all bootloaders were aware of DT this wouldn't be a problem,
because they could place the correct MAC inside the DT blob right
away.
But in the mean time (AKA forever) we need some other solution.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From shawn.guo at linaro.org  Mon Mar 19 03:01:17 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 19 Mar 2012 15:01:17 +0800
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zPztBfTY_WDwZ5iFEa94eCtHyrzN422RTACMQXs625gRA@mail.gmail.com>
References: <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
 <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
 <20120308062739.GE18513@lunn.ch>
 <20120308232549.GU3852@pengutronix.de>
 <20120309075720.GC16608@lunn.ch>
 <CAJOA=zPztBfTY_WDwZ5iFEa94eCtHyrzN422RTACMQXs625gRA@mail.gmail.com>
Message-ID: <20120319070115.GC31410@S2101-09.ap.freescale.net>

On Fri, Mar 09, 2012 at 10:25:00AM -0800, Turquette, Mike wrote:
...
> However if you have the ability to use the clk_foo_register functions
> please do use them in place of static initialization.  The static init
> stuff is only for folks backed into a corner and forced to use it...
> for now.  I'm looking at ways to allow for kmalloc'ing in early boot,
> as well as reducing the number of clocks that my platform registers
> during early boot drastically.
> 
While I agree using registration functions rather than static
initialization will help make "struct clk" an opaque cookie, I also
see some benefit with using static initialization over registration
functions.  That is we will be able to initialize parents statically
rather than calling expensive __clk_lookup() to find them when using
registration functions.

I'm not sure if this will be a concern with the platforms that have
hundreds of clocks.  Keep it in mind, when we say one clock, there
are generally 3 clks behind it, clk_gate, clk_divider and clk_mux.

-- 
Regards,
Shawn


From boojin.kim at samsung.com  Mon Mar 19 03:02:48 2012
From: boojin.kim at samsung.com (Boojin Kim)
Date: Mon, 19 Mar 2012 16:02:48 +0900
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
Message-ID: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>

This patch uses LDRD/STRD that loads and stores data as DWORD unit
for the copy of 8-words data.
It brings better performance than LDRM/STRM that was used originally.

Signed-off-by: Boojin Kim <boojin.kim at samsung.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/lib/copy_from_user.S |   14 +++++++++-----
 arch/arm/lib/copy_template.S  |   10 ++++++----
 arch/arm/lib/copy_to_user.S   |   13 +++++++++----
 arch/arm/lib/memcpy.S         |   13 +++++++++----
 4 files changed, 33 insertions(+), 17 deletions(-)

diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
index 66a477a..15d1e1c 100644
--- a/arch/arm/lib/copy_from_user.S
+++ b/arch/arm/lib/copy_from_user.S
@@ -51,11 +51,6 @@
 	ldr1w \ptr, \reg4, \abort
 	.endm

-	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
-	ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
-	ldr4w \ptr, \reg5, \reg6, \reg7, \reg8, \abort
-	.endm
-
 	.macro ldr1b ptr reg cond=al abort
 	ldrusr	\reg, \ptr, 1, \cond, abort=\abort
 	.endm
@@ -68,6 +63,15 @@
 	stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
 	.endm

+	.macro cpy8w dst src reg1 reg2 abort
+	.irp offset, #0, #8, #16, #24
+	ldr1w \src, \reg1, \abort
+	ldr1w \src, \reg2, \abort
+	strd \reg1, \reg2, [\dst, \offset]
+	.endr
+	add \dst, \dst, #32
+	.endm
+
 	.macro str1b ptr reg cond=al abort
 	str\cond\()b \reg, [\ptr], #1
 	.endm
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 805e3f8..72640aa 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -28,9 +28,8 @@
  *	'ptr' to the next word. The 'abort' argument is used for fixup tables.
  *
  * ldr4w ptr reg1 reg2 reg3 reg4 abort
- * ldr8w ptr, reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
  *
- *	This loads four or eight words starting from 'ptr', stores them
+ *	This loads eight words starting from 'ptr', stores them
  *	in provided registers and increments 'ptr' past those words.
  *	The'abort' argument is used for fixup tables.
  *
@@ -47,6 +46,10 @@
  *	Same as their ldr* counterparts, but data is stored to 'ptr' location
  *	rather than being loaded.
  *
+ * cpy8w src dst reg1 reg2 abort
+ *	This loads eight words starting from 'src' and stores them to 'dst'.
+ *	The 'abort' argument is used for fixup tables.
+ *
  * enter reg1 reg2
  *
  *	Preserve the provided registers on the stack plus any additional
@@ -97,9 +100,8 @@
 	PLD(	pld	[r1, #92]		)

 3:	PLD(	pld	[r1, #124]		)
-4:		ldr8w	r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+4:		cpy8w   r0, r1, r4, r5, abort=20f
 		subs	r2, r2, #32
-		str8w	r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
 		bge	3b
 	PLD(	cmn	r2, #96			)
 	PLD(	bge	4b			)
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index d066df6..9402a08 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -48,10 +48,6 @@
 	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
 	.endm

-	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
-	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
-	.endm
-
 	.macro ldr1b ptr reg cond=al abort
 	ldr\cond\()b \reg, [\ptr], #1
 	.endm
@@ -71,6 +67,15 @@
 	str1w \ptr, \reg8, \abort
 	.endm

+	.macro cpy8w dst src reg1 reg2 abort
+	.irp offset, #0, #8, #16, #24
+	ldrd \reg1, \reg2, [\src, \offset]
+	str1w \dst, \reg1, \abort
+	str1w \dst, \reg2, \abort
+	.endr
+	add \src, \src, #32
+	.endm
+
 	.macro str1b ptr reg cond=al abort
 	strusr	\reg, \ptr, 1, \cond, abort=\abort
 	.endm
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index a9b9e22..25320c9 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -24,10 +24,6 @@
 	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
 	.endm

-	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
-	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
-	.endm
-
 	.macro ldr1b ptr reg cond=al abort
 	ldr\cond\()b \reg, [\ptr], #1
 	.endm
@@ -40,6 +36,15 @@
 	stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
 	.endm

+	.macro cpy8w dst src reg1 reg2 abort
+	.irp offset, #0, #8, #16, #24
+	ldrd \reg1, \reg2, [\src, \offset]
+	strd \reg1, \reg2, [\dst, \offset]
+	.endr
+	add \src, \src, #32
+	add \dst, \dst, #32
+	.endm
+
 	.macro str1b ptr reg cond=al abort
 	str\cond\()b \reg, [\ptr], #1
 	.endm
--
1.7.1




From monstr at monstr.eu  Mon Mar 19 03:07:41 2012
From: monstr at monstr.eu (Michal Simek)
Date: Mon, 19 Mar 2012 08:07:41 +0100
Subject: [PATCH 1/7] remoteproc: resource table overhaul
In-Reply-To: <CAK=Wgbbbi4GnuHedSh6cR1LhkZr8c9q6i=_TLSL252LpPB8Xsw@mail.gmail.com>
References: <1330589497-4139-1-git-send-email-ohad@wizery.com>
 <1330589497-4139-2-git-send-email-ohad@wizery.com>
 <4F6354E4.8030704@monstr.eu>
 <CAK=Wgbbbi4GnuHedSh6cR1LhkZr8c9q6i=_TLSL252LpPB8Xsw@mail.gmail.com>
Message-ID: <4F66DB3D.4010407@monstr.eu>

Hi Ohad,

> On Fri, Mar 16, 2012 at 4:57 PM, Michal Simek <monstr at monstr.eu> wrote:
>> In previous version I had carverout first which means that code was copyied
>> to physical address 0x0 and then vrigns were allocated. Current code
>> allocate vring first and then RTOS is not able to run from zero address.
> 
> In general, depending on specific allocation ordering is error prone
> and you shouldn't do it.

Yes, I agree with you. It was in v1.


> For a given device, we treat memory allocated with
> dma_alloc_coherent() as homogeneous. We care about its utilization and
> alignments of allocations rather than their specific location in the
> total region.

For zynq platform is very important to use addresses from 0 for rtos.
The main reason why it is so important is ARM reset vectors.


> If that's not the case, and there's special memory you want assigned
> with a specific purpose, than it's recommended to let the code make
> sure it happens explicitly, and not rely on implicit order of
> allocation.

Sure.


> Today there's no way to assign several memory regions with a specific
> device, but a reasonable workaround that's being used is creating
> several sub-devices with the special memory, and then looking them up
> with stuff like device_for_each_child() or device_find_child().
> 
> About your specific issue: the current allocation scheme was chosen
> for simplicity, but I do plan to change it back by postponing the
> vring dma allocation until a remote processor is really powered on.
> It's not a lot of memory, but this way we'd only allocate it when
> really needed (so if it's CMA, others could use it).
> 
> IOW: you can probably just wait a bit until this patch is ready and
> take it into your tree. It will most likely bring back the behavior you
> need :)

OK. I will use v1 where allocation is based on order in resource table.
It is not ideal but it is working.

 From my point of view will be the best to call dma_alloc_coherent only once
which will allocate the whole chunk of memory which is required for "RTOS".

My resource table is easy:
#define TEXT_BASE 0
struct resource_table __resource resources = {
	1, /* we're the first version that implements this */
	3, /* number of entries in the table */
	0, 0, /* reserved, must be zero */
	/* offsets to entries */
	{
			offsetof(struct resource_table, text_cout),
			offsetof(struct resource_table, rpmsg_vdev),
			offsetof(struct resource_table, trace),
	},
	{
		TYPE_CARVEOUT, 0, 0, SZ_1M, 0, 0, "MEM_DATA",
	},
	{
		TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
		RPMSG_IPU_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
		/* no config data */
	},

	/* the two vrings */
	{ TEXT_BASE + SZ_1M, 4096, 256, 1, 0 },
	{ TEXT_BASE + SZ_1M + 0x4000, 4096, 256, 2, 0 },

	{
		TYPE_TRACE, TEXT_BASE + 0x40000, 0x8000, 0, "trace",
	},

};

But as you see I need to keep that offset structure which is
that text/data starts at address 0, vrings0 on 0x100000, vrigns1 on 0x104000
and trace buffer 0x140000.

If dma_alloc_coherent is called just once with size taken from resource table.
(For my case for example 2MB=0x200000) and offset are driven by remoteproc then
it should just work.


Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian


From santosh.shilimkar at ti.com  Mon Mar 19 03:07:41 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Mon, 19 Mar 2012 12:37:41 +0530
Subject: [PATCH v4 0/7] Add TI EMIF SDRAM controller driver
In-Reply-To: <16771402.10791332119314036.JavaMail.weblogic@epv6ml07>
References: <16771402.10791332119314036.JavaMail.weblogic@epv6ml07>
Message-ID: <CAMQu2gy6yzawMAnkK+qmijDNo-5618b5SR7Cr+puMLSRM2znUA@mail.gmail.com>

2012/3/19 ??? <myungjoo.ham at samsung.com>:
>
> Kyungmin Park<kmpark at infradead.org> 2012-03-17 15:10 (GMT+09:00)
>> Hi,
>> On 3/17/12, Aneesh V wrote:
>> > Add a driver for the EMIF SDRAM controller used in TI SoCs
>> >
>> > EMIF is an SDRAM controller that supports, based on its revision,
>> > one or more of LPDDR2/DDR2/DDR3 protocols.This driver adds support
>> > for LPDDR2.
>> >
>> > The driver supports the following features:
>> > - Calculates the DDR AC timing parameters to be set in EMIF
>> >   registers using data from the device data-sheets and based
>> >   on the DDR frequency. If data from data-sheets is not available
>> >   default timing values from the JEDEC spec are used. These
>> >   will be safe, but not necessarily optimal
>> > - API for changing timings during DVFS or at boot-up
>
> This means that you alreeady have callbacks to create a devfreq device driver that supports DVFS on the device. This doesn't need to be a misc device driver then.
>
Nope. The callbacks mentioned above are mainly coming from the clock
framework. Ofcourse the clock node trigger
with voltage ramps would be triggered by some upper laver
governor/framework like CPUFreq/DEVFREQ but as
such this is not necessary. This is an indepdent driver and just like
CPUFREQ notifies it's users for the frequency
change, this driver will be notified to take any action on pre and
post notification. Note that, the driver will
be notified by regulator framework for the voltage ramp up/down cases
too with notifiers.

>> > - Temperature alert configuration and handling of temperature
>> >   alerts, if any for LPDDR2 devices
>> >   * temperature alert is based on periodic polling of MR4 mode
>> >     register in DDR devices automatically performed by hardware
>> >   * timings are de-rated and brought back to nominal when
>> >     temperature raises and falls respectively
>
> This can be a feature overriding "max_freq" inside the Omap EMIF devfreq device driver though it maybe (or not.. I just don't sure) be better to use thermal framework as well.
>
That's absolute abuse and there is no need to link the temperature
handling with DVFS. Reducing frequency can be one
of the cooling techniques but that's not related to the temperature
alert handling. Temperature handling in the EMIF
driver is strictly as per the JDEC specs and that is to de-rate the
timings when temperature threshold is crossed.

The idea is drivers should be independent of all the global policy
governors. Hope this is clear to
you.

Regards
Santosh


From thomas.abraham at linaro.org  Mon Mar 19 03:29:31 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 19 Mar 2012 12:59:31 +0530
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <001501cd0561$57c642b0$0752c810$%han@samsung.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com>
 <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
 <001d01cd0315$935cc720$ba165560$%han@samsung.com>
 <CAEYLNCrGCmb5EJjURLY=EGfM=4N54MirNkCCyQRxqKEN3Eka8Q@mail.gmail.com>
 <002d01cd034b$c56f2b00$504d8100$%han@samsung.com>
 <CAEYLNCpfQ0cYb4efw6PZNnKjQ2rF25rj5Ed=i884LJXHAwigBw@mail.gmail.com>
 <002f01cd0359$eb718330$c2548990$%han@samsung.com>
 <CAEYLNCpJU_5uVa-jo5HUNY8Av6eYaiow1gEZtHCiQZ5oKkGoMQ@mail.gmail.com>
 <001501cd0561$57c642b0$0752c810$%han@samsung.com>
Message-ID: <CAJuYYwQmJvx_uGZKbAJ9uds-ciLs2VDqcifhoqB-P0M5uhO-nA@mail.gmail.com>

Hi Darius,

On 19 March 2012 05:16, Jingoo Han <jg1.han at samsung.com> wrote:
[...]

>
> Because there are not multiple windows and driver sees only single window as you mentiond,
> Only 'struct s3c_fb_pd_win mini6410_fb_win[0]' should be used and
> 'struct s3c_fb_pd_win mini6410_fb_win[1]' should not be used.
> s3c_fb_pd_win[0] means window 0 of FIMD IP, s3c_fb_pd_win[1] means window 1 of FIMD IP.
>
> Therefore, if mini6410_fb_win[0] and mini6410_fb_win[1] are included, it means that
> 2 windows of FIMD IP are used in single LCD.
>
> If you want to support multiple LCDs, you should use struct s3c_fb_platdata[0], struct s3c_fb_platdata[1],
> because 'struct s3c_fb_platdata' means LCD panel.
>
> If you understand the purpose of s3c_fb_platdata and s3c_fb_pd_win, you should do, at least, as below.
>
> static struct s3c_fb_pd_win mini6410_fb_lcd0_win[] = {
> ? ? ? ?{
> ? ? ? ? ? ? ? ?.win_mode ? ? ? = { ? ? /* 4.3" 480x272 */
> ? ? ? ? ? ? ? ? ? ? ? ?.left_margin ? ?= 3,
> ? ? ? ? ? ? ? ? ? ? ? ?.right_margin ? = 2,
> ? ? ? ? ? ? ? ? ? ? ? ?.upper_margin ? = 1,
> ? ? ? ? ? ? ? ? ? ? ? ?.lower_margin ? = 1,
> ? ? ? ? ? ? ? ? ? ? ? ?.hsync_len ? ? ?= 40,
> ? ? ? ? ? ? ? ? ? ? ? ?.vsync_len ? ? ?= 1,
> ? ? ? ? ? ? ? ? ? ? ? ?.xres ? ? ? ? ? = 480,
> ? ? ? ? ? ? ? ? ? ? ? ?.yres ? ? ? ? ? = 272,
> ? ? ? ? ? ? ? ?},
> ? ? ? ? ? ? ? ?.max_bpp ? ? ? ?= 32,
> ? ? ? ? ? ? ? ?.default_bpp ? ?= 16,
> ? ? ? ?},
> };
>
> static struct s3c_fb_platdata mini6410_lcd_pdata[0] __initdata = {
> ? ? ? ?.setup_gpio ? ? = s3c64xx_fb_gpio_setup_24bpp,
> ? ? ? ?.win[0] ? ? ? ? = &mini6410_fb_lcd0_win[0],
> ? ? ? ?.vidcon0 ? ? ? ?= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> ? ? ? ?.vidcon1 ? ? ? ?= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> };
>
> static struct s3c_fb_pd_win mini6410_fb_lcd1_win[] = {
> ? ? ? ?{
> ? ? ? ? ? ? ? ?.win_mode ? ? ? = { ? ? /* 7.0" 800x480 */
> ? ? ? ? ? ? ? ? ? ? ? ?.left_margin ? ?= 8,
> ? ? ? ? ? ? ? ? ? ? ? ?.right_margin ? = 13,
> ? ? ? ? ? ? ? ? ? ? ? ?.upper_margin ? = 7,
> ? ? ? ? ? ? ? ? ? ? ? ?.lower_margin ? = 5,
> ? ? ? ? ? ? ? ? ? ? ? ?.hsync_len ? ? ?= 3,
> ? ? ? ? ? ? ? ? ? ? ? ?.vsync_len ? ? ?= 1,
> ? ? ? ? ? ? ? ? ? ? ? ?.xres ? ? ? ? ? = 800,
> ? ? ? ? ? ? ? ? ? ? ? ?.yres ? ? ? ? ? = 480,
> ? ? ? ? ? ? ? ?},
> ? ? ? ? ? ? ? ?.max_bpp ? ? ? ?= 32,
> ? ? ? ? ? ? ? ?.default_bpp ? ?= 16,
> ? ? ? ?},
> };
>
> static struct s3c_fb_platdata mini6410_lcd_pdata[1] __initdata = {
> ? ? ? ?.setup_gpio ? ? = s3c64xx_fb_gpio_setup_24bpp,
> ? ? ? ?.win[0] ? ? ? ? = &mini6410_fb_lcd1_win[0],
> ? ? ? ?.vidcon0 ? ? ? ?= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> ? ? ? ?.vidcon1 ? ? ? ?= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> };
>
> Each struct means:
> ?mini6410_lcd_pdata[0]: 4.3" 480x272 LCD
> ?mini6410_fb_lcd0_win[0]: window 0 used for 4.3" 480x272 LCD
>
> ?mini6410_lcd_pdata[1]: 7.0" 800x480 LCD
> ?mini6410_fb_lcd1_win[0]: window 0 used for 7.0" 800x480 LCD
>
> In this case, 4.3" or 7.0" LCD can be selected using mini6410_lcd_pdata[], instead of selecting mini6410_fb_win[0] or
> mini6410_fb_win[1].
>
> My point is that 's3c_fb_platdata and s3c_fb_pd_win should be used exactly'.

I agree with solution which Jingoo Han has proposed. Instead of
selecting one instance of s3c_fb_pd_win over the other at runtime, the
features->lcd_index can be used to select one of the instances of
platform data for s3c-fb driver.

s3c_fb_pd_win is used to describe a window supported by the fimd
controller. It is not meant to carry lcd timing information. The lcd
panel timing remains the same irrespective of the window sizes. And
this patchset is a step towards untangling window information and
video timing.

(Apologizes for the delayed reply. I was out of office for last 4 days.)

Thanks,
Thomas.


From sfr at canb.auug.org.au  Mon Mar 19 03:39:11 2012
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Mon, 19 Mar 2012 18:39:11 +1100
Subject: linux-next: build warning after merge of the arm-soc tree
Message-ID: <20120319183911.0cd46df560c714ee71184242@canb.auug.org.au>

Hi all,

After merging the arm-soc tree, today's linux-next build (all)
produced this warning:

drivers/clk/Kconfig:22: warning: menuconfig statement without prompt

Introduced by commit c173033d154e ("clk: make CONFIG_COMMON_CLK invisible").

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
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From augulis.darius at gmail.com  Mon Mar 19 03:40:59 2012
From: augulis.darius at gmail.com (Darius Augulis)
Date: Mon, 19 Mar 2012 09:40:59 +0200
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <CAJuYYwQmJvx_uGZKbAJ9uds-ciLs2VDqcifhoqB-P0M5uhO-nA@mail.gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com>
 <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
 <001d01cd0315$935cc720$ba165560$%han@samsung.com>
 <CAEYLNCrGCmb5EJjURLY=EGfM=4N54MirNkCCyQRxqKEN3Eka8Q@mail.gmail.com>
 <002d01cd034b$c56f2b00$504d8100$%han@samsung.com>
 <CAEYLNCpfQ0cYb4efw6PZNnKjQ2rF25rj5Ed=i884LJXHAwigBw@mail.gmail.com>
 <002f01cd0359$eb718330$c2548990$%han@samsung.com>
 <CAEYLNCpJU_5uVa-jo5HUNY8Av6eYaiow1gEZtHCiQZ5oKkGoMQ@mail.gmail.com>
 <001501cd0561$57c642b0$0752c810$%han@samsung.com>
 <CAJuYYwQmJvx_uGZKbAJ9uds-ciLs2VDqcifhoqB-P0M5uhO-nA@mail.gmail.com>
Message-ID: <CAEYLNCo0zyH9Nsf59UU-J4m=km+mKH1ym5a-9s7WthFpos6D+w@mail.gmail.com>

Hi,

On Mon, Mar 19, 2012 at 9:29 AM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:
> Hi Darius,
>
> On 19 March 2012 05:16, Jingoo Han <jg1.han at samsung.com> wrote:
> [...]
>
>>
>> Because there are not multiple windows and driver sees only single window as you mentiond,
>> Only 'struct s3c_fb_pd_win mini6410_fb_win[0]' should be used and
>> 'struct s3c_fb_pd_win mini6410_fb_win[1]' should not be used.
>> s3c_fb_pd_win[0] means window 0 of FIMD IP, s3c_fb_pd_win[1] means window 1 of FIMD IP.
>>
>> Therefore, if mini6410_fb_win[0] and mini6410_fb_win[1] are included, it means that
>> 2 windows of FIMD IP are used in single LCD.
>>
>> If you want to support multiple LCDs, you should use struct s3c_fb_platdata[0], struct s3c_fb_platdata[1],
>> because 'struct s3c_fb_platdata' means LCD panel.
>>
>> If you understand the purpose of s3c_fb_platdata and s3c_fb_pd_win, you should do, at least, as below.
>>
>> static struct s3c_fb_pd_win mini6410_fb_lcd0_win[] = {
>> ? ? ? ?{
>> ? ? ? ? ? ? ? ?.win_mode ? ? ? = { ? ? /* 4.3" 480x272 */
>> ? ? ? ? ? ? ? ? ? ? ? ?.left_margin ? ?= 3,
>> ? ? ? ? ? ? ? ? ? ? ? ?.right_margin ? = 2,
>> ? ? ? ? ? ? ? ? ? ? ? ?.upper_margin ? = 1,
>> ? ? ? ? ? ? ? ? ? ? ? ?.lower_margin ? = 1,
>> ? ? ? ? ? ? ? ? ? ? ? ?.hsync_len ? ? ?= 40,
>> ? ? ? ? ? ? ? ? ? ? ? ?.vsync_len ? ? ?= 1,
>> ? ? ? ? ? ? ? ? ? ? ? ?.xres ? ? ? ? ? = 480,
>> ? ? ? ? ? ? ? ? ? ? ? ?.yres ? ? ? ? ? = 272,
>> ? ? ? ? ? ? ? ?},
>> ? ? ? ? ? ? ? ?.max_bpp ? ? ? ?= 32,
>> ? ? ? ? ? ? ? ?.default_bpp ? ?= 16,
>> ? ? ? ?},
>> };
>>
>> static struct s3c_fb_platdata mini6410_lcd_pdata[0] __initdata = {
>> ? ? ? ?.setup_gpio ? ? = s3c64xx_fb_gpio_setup_24bpp,
>> ? ? ? ?.win[0] ? ? ? ? = &mini6410_fb_lcd0_win[0],
>> ? ? ? ?.vidcon0 ? ? ? ?= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>> ? ? ? ?.vidcon1 ? ? ? ?= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>> };
>>
>> static struct s3c_fb_pd_win mini6410_fb_lcd1_win[] = {
>> ? ? ? ?{
>> ? ? ? ? ? ? ? ?.win_mode ? ? ? = { ? ? /* 7.0" 800x480 */
>> ? ? ? ? ? ? ? ? ? ? ? ?.left_margin ? ?= 8,
>> ? ? ? ? ? ? ? ? ? ? ? ?.right_margin ? = 13,
>> ? ? ? ? ? ? ? ? ? ? ? ?.upper_margin ? = 7,
>> ? ? ? ? ? ? ? ? ? ? ? ?.lower_margin ? = 5,
>> ? ? ? ? ? ? ? ? ? ? ? ?.hsync_len ? ? ?= 3,
>> ? ? ? ? ? ? ? ? ? ? ? ?.vsync_len ? ? ?= 1,
>> ? ? ? ? ? ? ? ? ? ? ? ?.xres ? ? ? ? ? = 800,
>> ? ? ? ? ? ? ? ? ? ? ? ?.yres ? ? ? ? ? = 480,
>> ? ? ? ? ? ? ? ?},
>> ? ? ? ? ? ? ? ?.max_bpp ? ? ? ?= 32,
>> ? ? ? ? ? ? ? ?.default_bpp ? ?= 16,
>> ? ? ? ?},
>> };
>>
>> static struct s3c_fb_platdata mini6410_lcd_pdata[1] __initdata = {
>> ? ? ? ?.setup_gpio ? ? = s3c64xx_fb_gpio_setup_24bpp,
>> ? ? ? ?.win[0] ? ? ? ? = &mini6410_fb_lcd1_win[0],
>> ? ? ? ?.vidcon0 ? ? ? ?= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>> ? ? ? ?.vidcon1 ? ? ? ?= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>> };
>>
>> Each struct means:
>> ?mini6410_lcd_pdata[0]: 4.3" 480x272 LCD
>> ?mini6410_fb_lcd0_win[0]: window 0 used for 4.3" 480x272 LCD
>>
>> ?mini6410_lcd_pdata[1]: 7.0" 800x480 LCD
>> ?mini6410_fb_lcd1_win[0]: window 0 used for 7.0" 800x480 LCD
>>
>> In this case, 4.3" or 7.0" LCD can be selected using mini6410_lcd_pdata[], instead of selecting mini6410_fb_win[0] or
>> mini6410_fb_win[1].
>>
>> My point is that 's3c_fb_platdata and s3c_fb_pd_win should be used exactly'.
>
> I agree with solution which Jingoo Han has proposed. Instead of
> selecting one instance of s3c_fb_pd_win over the other at runtime, the
> features->lcd_index can be used to select one of the instances of
> platform data for s3c-fb driver.

I agree with it too. Would you make such patch based on your s3c-fb patch set?
Somebody should make it and definitely not to remove multiple LCD
suport for these boards.

>
> s3c_fb_pd_win is used to describe a window supported by the fimd
> controller. It is not meant to carry lcd timing information. The lcd
> panel timing remains the same irrespective of the window sizes. And
> this patchset is a step towards untangling window information and
> video timing.

Right now s3c_fb_pd_win contains exactly LCD timing values.
Your patch will move these timing values to struct fb_videomode.

I could make necessary patch for that too, but I think you will spend
less time doing it by yourself than syncing with me.
What do you think?

regards,
Darius


From shawn.guo at linaro.org  Mon Mar 19 03:42:06 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 19 Mar 2012 15:42:06 +0800
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <4F6403CD.8020509@codeaurora.org>
References: <1330763341-3437-4-git-send-email-mturquette@linaro.org>
 <20120303133158.GA26882@pengutronix.de>
 <CAJOA=zNFNEHxBDhRDdvm7DYR83R0LJjsp_AT3BoG+nL+iN5_tw@mail.gmail.com>
 <20120304115201.GB26882@pengutronix.de>
 <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
 <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
 <4F6403CD.8020509@codeaurora.org>
Message-ID: <20120319074202.GD31410@S2101-09.ap.freescale.net>

On Fri, Mar 16, 2012 at 08:23:57PM -0700, Saravana Kannan wrote:
> On 03/07/2012 01:20 PM, Turquette, Mike wrote:
...
> >Admittedly I think that the OMAP code could migrate some of these bits
> >to a lazy-registration model, specifically the hwmod object instances,
> >but that requires an awful lot of refactoring for a fairly large stack
> >of platform code.  This might be something to achieve in the future
> >but for now we *need* initialisation to be fully static.
> 
> When we work on moving clocks to device tree, wouldn't you face the
> same problem? You will have to dynamically create most of the clocks
> in that case too.
> 
>From what I heard from Mike[1], Omap will not have most of the clocks
encoded in device tree. 

Although my original preference was to have all the clocks represented
in device tree and dynamically registered to clk framework, I've heard
people including Grant incline to only have oscillator and leaf modules
clocks in device tree.  I somehow agree with that now, because having
all the clocks in there will bloat device tree dramatically, considering
there will be 3 clks, clk_gate, clk_divider and clk_mux backing one
clock in general.

Assuming we would agree to have most SoC internal clocks registered
from clock driver rather than device tree, I would like to hear about
how we should have these clock registered from clock driver, static
initialization or using register function?

-- 
Regards,
Shawn

[1] http://article.gmane.org/gmane.linux.linaro.devel/10554


From thomas.abraham at linaro.org  Mon Mar 19 03:49:07 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 19 Mar 2012 13:19:07 +0530
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <CAEYLNCo0zyH9Nsf59UU-J4m=km+mKH1ym5a-9s7WthFpos6D+w@mail.gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com>
 <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
 <001d01cd0315$935cc720$ba165560$%han@samsung.com>
 <CAEYLNCrGCmb5EJjURLY=EGfM=4N54MirNkCCyQRxqKEN3Eka8Q@mail.gmail.com>
 <002d01cd034b$c56f2b00$504d8100$%han@samsung.com>
 <CAEYLNCpfQ0cYb4efw6PZNnKjQ2rF25rj5Ed=i884LJXHAwigBw@mail.gmail.com>
 <002f01cd0359$eb718330$c2548990$%han@samsung.com>
 <CAEYLNCpJU_5uVa-jo5HUNY8Av6eYaiow1gEZtHCiQZ5oKkGoMQ@mail.gmail.com>
 <001501cd0561$57c642b0$0752c810$%han@samsung.com>
 <CAJuYYwQmJvx_uGZKbAJ9uds-ciLs2VDqcifhoqB-P0M5uhO-nA@mail.gmail.com>
 <CAEYLNCo0zyH9Nsf59UU-J4m=km+mKH1ym5a-9s7WthFpos6D+w@mail.gmail.com>
Message-ID: <CAJuYYwQY6C-+NUuYfmDyGoh0ahVa8_x1cai8MCfN_JjWh1k1Gg@mail.gmail.com>

On 19 March 2012 13:10, Darius Augulis <augulis.darius at gmail.com> wrote:
> Hi,
>
> On Mon, Mar 19, 2012 at 9:29 AM, Thomas Abraham
> <thomas.abraham at linaro.org> wrote:
>> Hi Darius,
>>
>> On 19 March 2012 05:16, Jingoo Han <jg1.han at samsung.com> wrote:
>> [...]
>>
>>>
>>> Because there are not multiple windows and driver sees only single window as you mentiond,
>>> Only 'struct s3c_fb_pd_win mini6410_fb_win[0]' should be used and
>>> 'struct s3c_fb_pd_win mini6410_fb_win[1]' should not be used.
>>> s3c_fb_pd_win[0] means window 0 of FIMD IP, s3c_fb_pd_win[1] means window 1 of FIMD IP.
>>>
>>> Therefore, if mini6410_fb_win[0] and mini6410_fb_win[1] are included, it means that
>>> 2 windows of FIMD IP are used in single LCD.
>>>
>>> If you want to support multiple LCDs, you should use struct s3c_fb_platdata[0], struct s3c_fb_platdata[1],
>>> because 'struct s3c_fb_platdata' means LCD panel.
>>>
>>> If you understand the purpose of s3c_fb_platdata and s3c_fb_pd_win, you should do, at least, as below.
>>>
>>> static struct s3c_fb_pd_win mini6410_fb_lcd0_win[] = {
>>> ? ? ? ?{
>>> ? ? ? ? ? ? ? ?.win_mode ? ? ? = { ? ? /* 4.3" 480x272 */
>>> ? ? ? ? ? ? ? ? ? ? ? ?.left_margin ? ?= 3,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.right_margin ? = 2,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.upper_margin ? = 1,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.lower_margin ? = 1,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.hsync_len ? ? ?= 40,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.vsync_len ? ? ?= 1,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.xres ? ? ? ? ? = 480,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.yres ? ? ? ? ? = 272,
>>> ? ? ? ? ? ? ? ?},
>>> ? ? ? ? ? ? ? ?.max_bpp ? ? ? ?= 32,
>>> ? ? ? ? ? ? ? ?.default_bpp ? ?= 16,
>>> ? ? ? ?},
>>> };
>>>
>>> static struct s3c_fb_platdata mini6410_lcd_pdata[0] __initdata = {
>>> ? ? ? ?.setup_gpio ? ? = s3c64xx_fb_gpio_setup_24bpp,
>>> ? ? ? ?.win[0] ? ? ? ? = &mini6410_fb_lcd0_win[0],
>>> ? ? ? ?.vidcon0 ? ? ? ?= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>>> ? ? ? ?.vidcon1 ? ? ? ?= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>>> };
>>>
>>> static struct s3c_fb_pd_win mini6410_fb_lcd1_win[] = {
>>> ? ? ? ?{
>>> ? ? ? ? ? ? ? ?.win_mode ? ? ? = { ? ? /* 7.0" 800x480 */
>>> ? ? ? ? ? ? ? ? ? ? ? ?.left_margin ? ?= 8,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.right_margin ? = 13,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.upper_margin ? = 7,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.lower_margin ? = 5,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.hsync_len ? ? ?= 3,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.vsync_len ? ? ?= 1,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.xres ? ? ? ? ? = 800,
>>> ? ? ? ? ? ? ? ? ? ? ? ?.yres ? ? ? ? ? = 480,
>>> ? ? ? ? ? ? ? ?},
>>> ? ? ? ? ? ? ? ?.max_bpp ? ? ? ?= 32,
>>> ? ? ? ? ? ? ? ?.default_bpp ? ?= 16,
>>> ? ? ? ?},
>>> };
>>>
>>> static struct s3c_fb_platdata mini6410_lcd_pdata[1] __initdata = {
>>> ? ? ? ?.setup_gpio ? ? = s3c64xx_fb_gpio_setup_24bpp,
>>> ? ? ? ?.win[0] ? ? ? ? = &mini6410_fb_lcd1_win[0],
>>> ? ? ? ?.vidcon0 ? ? ? ?= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>>> ? ? ? ?.vidcon1 ? ? ? ?= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>>> };
>>>
>>> Each struct means:
>>> ?mini6410_lcd_pdata[0]: 4.3" 480x272 LCD
>>> ?mini6410_fb_lcd0_win[0]: window 0 used for 4.3" 480x272 LCD
>>>
>>> ?mini6410_lcd_pdata[1]: 7.0" 800x480 LCD
>>> ?mini6410_fb_lcd1_win[0]: window 0 used for 7.0" 800x480 LCD
>>>
>>> In this case, 4.3" or 7.0" LCD can be selected using mini6410_lcd_pdata[], instead of selecting mini6410_fb_win[0] or
>>> mini6410_fb_win[1].
>>>
>>> My point is that 's3c_fb_platdata and s3c_fb_pd_win should be used exactly'.
>>
>> I agree with solution which Jingoo Han has proposed. Instead of
>> selecting one instance of s3c_fb_pd_win over the other at runtime, the
>> features->lcd_index can be used to select one of the instances of
>> platform data for s3c-fb driver.
>
> I agree with it too. Would you make such patch based on your s3c-fb patch set?
> Somebody should make it and definitely not to remove multiple LCD
> suport for these boards.

Sure. I will make a patch for that. I did not notice the way two lcd's
were supported in your code while preparing this patchset. Thanks for
bringing up this point.

>
>>
>> s3c_fb_pd_win is used to describe a window supported by the fimd
>> controller. It is not meant to carry lcd timing information. The lcd
>> panel timing remains the same irrespective of the window sizes. And
>> this patchset is a step towards untangling window information and
>> video timing.
>
> Right now s3c_fb_pd_win contains exactly LCD timing values.
> Your patch will move these timing values to struct fb_videomode.
>
> I could make necessary patch for that too, but I think you will spend
> less time doing it by yourself than syncing with me.
> What do you think?

Yes, I will prepare an additional patch in this series that will
maintain backward compatibility for real6410 and mini6410 with the
approach suggested by Jingoo Han. As I do not have either of these
boards, an ack from you would be very helpful when the next version of
this patchset is posted.

Thanks,
Thomas.


From augulis.darius at gmail.com  Mon Mar 19 03:52:33 2012
From: augulis.darius at gmail.com (Darius Augulis)
Date: Mon, 19 Mar 2012 09:52:33 +0200
Subject: [PATCH v2 3/3] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <CAJuYYwQY6C-+NUuYfmDyGoh0ahVa8_x1cai8MCfN_JjWh1k1Gg@mail.gmail.com>
References: <1331585999-8604-1-git-send-email-thomas.abraham@linaro.org>
 <1331585999-8604-4-git-send-email-thomas.abraham@linaro.org>
 <002f01cd00fe$5df84fa0$19e8eee0$%han@samsung.com>
 <CAJuYYwSUf-gsVesduMggSuues9OLOR6DUDAAMg_tL=e3=3c0tQ@mail.gmail.com>
 <000501cd0184$f088cb20$d19a6160$%han@samsung.com>
 <4F60E5C8.3040804@gmail.com>
 <001501cd0241$6bb53560$431fa020$%han@samsung.com>
 <CAEYLNCp5e=86rpRi2C-5OJptTyEeXAn8JHhbWw_BqGzSaDD9wQ@mail.gmail.com>
 <002a01cd0283$1f61b200$5e251600$%han@samsung.com>
 <CAEYLNCrprPE60ZS=_OWuck0JCJMhCxzVErZwuwGpEDYkQq-hXg@mail.gmail.com>
 <001d01cd0315$935cc720$ba165560$%han@samsung.com>
 <CAEYLNCrGCmb5EJjURLY=EGfM=4N54MirNkCCyQRxqKEN3Eka8Q@mail.gmail.com>
 <002d01cd034b$c56f2b00$504d8100$%han@samsung.com>
 <CAEYLNCpfQ0cYb4efw6PZNnKjQ2rF25rj5Ed=i884LJXHAwigBw@mail.gmail.com>
 <002f01cd0359$eb718330$c2548990$%han@samsung.com>
 <CAEYLNCpJU_5uVa-jo5HUNY8Av6eYaiow1gEZtHCiQZ5oKkGoMQ@mail.gmail.com>
 <001501cd0561$57c642b0$0752c810$%han@samsung.com>
 <CAJuYYwQmJvx_uGZKbAJ9uds-ciLs2VDqcifhoqB-P0M5uhO-nA@mail.gmail.com>
 <CAEYLNCo0zyH9Nsf59UU-J4m=km+mKH1ym5a-9s7WthFpos6D+w@mail.gmail.com>
 <CAJuYYwQY6C-+NUuYfmDyGoh0ahVa8_x1cai8MCfN_JjWh1k1Gg@mail.gmail.com>
Message-ID: <CAEYLNCqzSFW4ugsXgG0ugwQ6p0fSmZaYdgx03J0XVKK4bKH5Lg@mail.gmail.com>

On Mon, Mar 19, 2012 at 9:49 AM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:
> On 19 March 2012 13:10, Darius Augulis <augulis.darius at gmail.com> wrote:

>> Right now s3c_fb_pd_win contains exactly LCD timing values.
>> Your patch will move these timing values to struct fb_videomode.
>>
>> I could make necessary patch for that too, but I think you will spend
>> less time doing it by yourself than syncing with me.
>> What do you think?
>
> Yes, I will prepare an additional patch in this series that will
> maintain backward compatibility for real6410 and mini6410 with the
> approach suggested by Jingoo Han. As I do not have either of these
> boards, an ack from you would be very helpful when the next version of
> this patchset is posted.

It's fine - I will review and probably test it.


From sourav.poddar at ti.com  Mon Mar 19 04:12:46 2012
From: sourav.poddar at ti.com (Sourav Poddar)
Date: Mon, 19 Mar 2012 13:42:46 +0530
Subject: [PATCHv2 2/2] Input: omap-keypad: dynamically handle register offsets
Message-ID: <1332144766-30798-1-git-send-email-sourav.poddar@ti.com>

From: G, Manjunath Kondaiah <manjugk at ti.com>

Keypad controller register offsets are different for omap4
and omap5. Handle these offsets through static mapping and
assign these mappings during run time.

Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: G, Manjunath Kondaiah <manjugk at ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
---
Changes since v1:
Fix Dmitry's comment:
- Configured IRQ manupulation registers at probe time
 drivers/input/keyboard/Kconfig        |    6 +-
 drivers/input/keyboard/omap4-keypad.c |  120 ++++++++++++++++++++++++++------
 2 files changed, 100 insertions(+), 26 deletions(-)

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index 1379daa..09d7d0b 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -510,10 +510,10 @@ config KEYBOARD_OMAP
 	  To compile this driver as a module, choose M here: the
 	  module will be called omap-keypad.
 
-config KEYBOARD_OMAP4
-	tristate "TI OMAP4 keypad support"
+config KEYBOARD_OMAP4+
+	tristate "TI OMAP4+ keypad support"
 	help
-	  Say Y here if you want to use the OMAP4 keypad.
+	  Say Y here if you want to use the OMAP4+ keypad.
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called omap4-keypad.
diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c
index e809ac0..a8b0700 100644
--- a/drivers/input/keyboard/omap4-keypad.c
+++ b/drivers/input/keyboard/omap4-keypad.c
@@ -68,6 +68,11 @@
 
 #define OMAP4_MASK_IRQSTATUSDISABLE	0xFFFF
 
+enum {
+	KBD_REVISION_OMAP4 = 0,
+	KBD_REVISION_OMAP5,
+};
+
 struct omap4_keypad {
 	struct input_dev *input;
 
@@ -76,11 +81,66 @@ struct omap4_keypad {
 
 	unsigned int rows;
 	unsigned int cols;
+	unsigned int revision;
+	u32 irqstatus;
+	u32 irqenable;
 	unsigned int row_shift;
 	unsigned char key_state[8];
 	unsigned short keymap[];
 };
 
+static int kbd_read_irqstatus(struct omap4_keypad *keypad_data, u32 offset)
+{
+	return __raw_readl(keypad_data->base + offset);
+}
+
+static int kbd_write_irqstatus(struct omap4_keypad *keypad_data,
+						u32 offset, u32 value)
+{
+	return __raw_writel(value, keypad_data->base + offset);
+}
+
+static int kbd_write_irqenable(struct omap4_keypad *keypad_data,
+						u32 offset, u32 value)
+{
+	return __raw_writel(value, keypad_data->base + offset);
+}
+
+static int kbd_readl(struct omap4_keypad *keypad_data, u32 offset)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		return __raw_readl(keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		return __raw_readl(keypad_data->base + offset + 0x10);
+
+	return -ENODEV;
+}
+
+static void kbd_writel(struct omap4_keypad *keypad_data, u32 offset, u32 value)
+{
+	if (keypad_data->revision == KBD_REVISION_OMAP4)
+		__raw_writel(value, keypad_data->base + offset);
+	else if (keypad_data->revision == KBD_REVISION_OMAP5)
+		__raw_writel(value, keypad_data->base + offset + 0x10);
+}
+
+static int kbd_read_revision(struct omap4_keypad *keypad_data, u32 offset)
+{
+	int reg;
+	reg = __raw_readl(keypad_data->base + offset);
+	reg &= 0x03 << 30;
+	reg >>= 30;
+
+	switch (reg) {
+	case 1:
+		return KBD_REVISION_OMAP5;
+	case 0:
+		return KBD_REVISION_OMAP4;
+	default:
+		return -ENODEV;
+	}
+}
+
 /* Interrupt handler */
 static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
 {
@@ -91,12 +151,11 @@ static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
 	u32 *new_state = (u32 *) key_state;
 
 	/* Disable interrupts */
-	__raw_writel(OMAP4_VAL_IRQDISABLE,
-		     keypad_data->base + OMAP4_KBD_IRQENABLE);
+	kbd_write_irqenable(keypad_data, keypad_data->irqenable,
+						OMAP4_VAL_IRQDISABLE);
 
-	*new_state = __raw_readl(keypad_data->base + OMAP4_KBD_FULLCODE31_0);
-	*(new_state + 1) = __raw_readl(keypad_data->base
-						+ OMAP4_KBD_FULLCODE63_32);
+	*new_state = kbd_readl(keypad_data, OMAP4_KBD_FULLCODE31_0);
+	*(new_state + 1) = kbd_readl(keypad_data, OMAP4_KBD_FULLCODE63_32);
 
 	for (row = 0; row < keypad_data->rows; row++) {
 		changed = key_state[row] ^ keypad_data->key_state[row];
@@ -121,12 +180,13 @@ static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
 		sizeof(keypad_data->key_state));
 
 	/* clear pending interrupts */
-	__raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS),
-			keypad_data->base + OMAP4_KBD_IRQSTATUS);
+	kbd_write_irqstatus(keypad_data, keypad_data->irqstatus,
+		kbd_read_irqstatus(keypad_data, keypad_data->irqstatus));
 
 	/* enable interrupts */
-	__raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN | OMAP4_DEF_IRQENABLE_LONGKEY,
-			keypad_data->base + OMAP4_KBD_IRQENABLE);
+	kbd_write_irqenable(keypad_data, keypad_data->irqenable,
+		OMAP4_DEF_IRQENABLE_EVENTEN |
+			OMAP4_DEF_IRQENABLE_LONGKEY);
 
 	return IRQ_HANDLED;
 }
@@ -139,16 +199,30 @@ static int omap4_keypad_open(struct input_dev *input)
 
 	disable_irq(keypad_data->irq);
 
-	__raw_writel(OMAP4_VAL_FUNCTIONALCFG,
-			keypad_data->base + OMAP4_KBD_CTRL);
-	__raw_writel(OMAP4_VAL_DEBOUNCINGTIME,
-			keypad_data->base + OMAP4_KBD_DEBOUNCINGTIME);
-	__raw_writel(OMAP4_VAL_IRQDISABLE,
-			keypad_data->base + OMAP4_KBD_IRQSTATUS);
-	__raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN | OMAP4_DEF_IRQENABLE_LONGKEY,
-			keypad_data->base + OMAP4_KBD_IRQENABLE);
-	__raw_writel(OMAP4_DEF_WUP_EVENT_ENA | OMAP4_DEF_WUP_LONG_KEY_ENA,
-			keypad_data->base + OMAP4_KBD_WAKEUPENABLE);
+	keypad_data->revision = kbd_read_revision(keypad_data,
+			OMAP4_KBD_REVISION);
+	if (keypad_data->revision == KBD_REVISION_OMAP4) {
+		keypad_data->irqstatus = OMAP4_KBD_IRQSTATUS;
+		keypad_data->irqenable = OMAP4_KBD_IRQENABLE;
+	} else if (keypad_data->revision == KBD_REVISION_OMAP5) {
+		keypad_data->irqstatus = OMAP4_KBD_IRQSTATUS + 0x0c;
+		keypad_data->irqenable = OMAP4_KBD_IRQENABLE + 0x0c;
+	} else {
+		pr_err("Omap keypad not found\n");
+		return -ENODEV;
+	}
+
+	kbd_writel(keypad_data, OMAP4_KBD_CTRL,
+			OMAP4_VAL_FUNCTIONALCFG);
+	kbd_writel(keypad_data, OMAP4_KBD_DEBOUNCINGTIME,
+			OMAP4_VAL_DEBOUNCINGTIME);
+	kbd_write_irqstatus(keypad_data, keypad_data->irqstatus,
+			OMAP4_VAL_IRQDISABLE);
+	kbd_write_irqenable(keypad_data, keypad_data->irqenable,
+			OMAP4_DEF_IRQENABLE_EVENTEN |
+				OMAP4_DEF_IRQENABLE_LONGKEY);
+	kbd_writel(keypad_data, OMAP4_KBD_WAKEUPENABLE,
+			OMAP4_DEF_WUP_EVENT_ENA | OMAP4_DEF_WUP_LONG_KEY_ENA);
 
 	enable_irq(keypad_data->irq);
 
@@ -162,12 +236,12 @@ static void omap4_keypad_close(struct input_dev *input)
 	disable_irq(keypad_data->irq);
 
 	/* Disable interrupts */
-	__raw_writel(OMAP4_VAL_IRQDISABLE,
-		     keypad_data->base + OMAP4_KBD_IRQENABLE);
+	kbd_write_irqenable(keypad_data, keypad_data->irqenable,
+			OMAP4_VAL_IRQDISABLE);
 
 	/* clear pending interrupts */
-	__raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS),
-			keypad_data->base + OMAP4_KBD_IRQSTATUS);
+	kbd_write_irqstatus(keypad_data, keypad_data->irqstatus,
+		kbd_read_irqstatus(keypad_data, keypad_data->irqstatus));
 
 	enable_irq(keypad_data->irq);
 
-- 
1.7.1



From philipp.zabel at gmail.com  Mon Mar 19 04:31:55 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Mon, 19 Mar 2012 09:31:55 +0100
Subject: [PATCH] pxa/hx4700: fix the LCD initialization
In-Reply-To: <1331995717.82481.YahooMailClassic@web29016.mail.ird.yahoo.com>
References: <1331905213.29979.1.camel@flow>
 <1331995717.82481.YahooMailClassic@web29016.mail.ird.yahoo.com>
Message-ID: <CA+gwMcd14LVxF=pxyewQRDFUfTFxhmnTzHmxSF=_s2kJyxn5EQ@mail.gmail.com>

Hi Paul,

On Sat, Mar 17, 2012 at 3:48 PM, Paul Parsons <lost.distance at yahoo.com> wrote:
> After some experimenting it seems that neither GPIO110 "LCD_LVDD_3V3_ON"
> nor GPIO112 "LCD_N2V7_7V3_ON" have any effect on the hx4700 LCD.
> After the hx4700 boots I can turn either one off, or both off together,
> and the LCD and touchscreen will continue to work normally.
>
> Is there an authoritative description of the 7 "LCD" GPIOs (GPIO59,
> GPIO62, GPIO70, GPIO84, GPIO110, GPIO111, GPIO112) that are used by
> the kernel, or the 2 "LCD" GPIOs (GPIO22, GPIO73) that are not used?
> The SDG code provides no enlightenment.

that is a good question. Not having done any of the reverse
engineering for hx4700 myself, I've always taken the SDG code as
gospel.
Unfortunately I am not aware of any hx4700 hardware schematics or even
a datasheet for the acx523akm lcd panel.

regards
Philipp


From s.hauer at pengutronix.de  Mon Mar 19 04:31:58 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 09:31:58 +0100
Subject: [PATCH 1/2] ARM: imx6q: add pll round_rate support
In-Reply-To: <20120319015142.GA2603@b20223-02.ap.freescale.net>
References: <1331713379-8437-1-git-send-email-richard.zhao@linaro.org>
 <1331713379-8437-2-git-send-email-richard.zhao@linaro.org>
 <20120314085228.GM3852@pengutronix.de>
 <20120315144601.GA5701@richard-laptop>
 <20120315150048.GC3852@pengutronix.de>
 <20120315151521.GB5701@richard-laptop>
 <20120315185004.GD3852@pengutronix.de>
 <20120316011006.GA17459@b20223-02.ap.freescale.net>
 <20120317122831.GD29317@pengutronix.de>
 <20120319015142.GA2603@b20223-02.ap.freescale.net>
Message-ID: <20120319083158.GV3852@pengutronix.de>

On Mon, Mar 19, 2012 at 09:51:43AM +0800, Richard Zhao wrote:
> On Sat, Mar 17, 2012 at 01:28:31PM +0100, Sascha Hauer wrote:
> > On Fri, Mar 16, 2012 at 09:10:07AM +0800, Richard Zhao wrote:
> > > Hi Sascha,
> > > 
> > > On Thu, Mar 15, 2012 at 07:50:04PM +0100, Sascha Hauer wrote:
> > > > On Thu, Mar 15, 2012 at 11:15:23PM +0800, Richard Zhao wrote:
> > > > > On Thu, Mar 15, 2012 at 04:00:48PM +0100, Sascha Hauer wrote:
> > > > > > On Thu, Mar 15, 2012 at 10:46:04PM +0800, Richard Zhao wrote:
> > > > > > > On Wed, Mar 14, 2012 at 09:52:28AM +0100, Sascha Hauer wrote:
> > > > > > > > On Wed, Mar 14, 2012 at 04:22:58PM +0800, Richard Zhao wrote:
> > > > > > > > > Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> > > > > > > > > ---
> > > > > > > > >  
> > > > > > > > >  #define DEF_PLL(name)					\
> > > > > > > > >  	static struct clk name = {			\
> > > > > > > > > @@ -681,6 +741,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate)
> > > > > > > > >  		.disable	= pll_disable,		\
> > > > > > > > >  		.get_rate	= name##_get_rate,	\
> > > > > > > > >  		.set_rate	= name##_set_rate,	\
> > > > > > > > > +		.round_rate	= name##_round_rate,	\
> > > > > > > > 
> > > > > > > > I hope this ## stuff is gone soon with the generic clock framework. It
> > > > > > > > is so ugly and inefficient.
> > > > > > > I hope this doesn't prevent this two patches go in.
> > > > > > 
> > > > > > Given that we are short from getting a generic clock framework (and I
> > > > > > think this time it's for real) and that you are not mention in any words
> > > > > > what these patches fix I don't see a reason for merging them.
> > > > > I think the cpu clock is a great challenge for generic clock framework.
> > > > > When it set_rate, it includes reparent, and change parent's parent's rate.
> > > > > I don't see any upstream code like that till now. and it's really what
> > > > > we need.
> > > > 
> > > > Then do a clk_set_parent, clk_set_rate and a clk_set_parent again
> > > > in your cpufreq driver.
> > > No, it's platform code, and supposed to be in arch/arm. What the cpufre
> > > driver know is to get cpu clk, rather not how cpu clk change its rate.
> > > And cpu clk/arm_clk is a real clock wires in SoC.
> > 
> > The job of the clock framework is to give a consistent view on the
> > clocks and to handle parent/rate changes properly. It even the
> > CLK_SET_RATE_GATE for ensuring that your PLL can only change its rate
> > when it's gated. It's not the job of the clock framework to dynamically
> > reorganize the clock tree on a rate change.
> The reparent in set_rate is in mutex lock. Looks like, we only need
> the unlocked version clk functions.

Again, you don't want to drill holes into the clock framework to
reparent in a set_rate op.

> > 
> > Besides, do you really want to reprogram the PLL with a cpufreq change?
> > You have a divider behind that PLL which you apparently can change
> > without having to reparent the PLL. Doesn't this give you enough choices
> > for the cpu frequency?
> No. The 3bit cpu divider is not enough. For example, if pll is 1G Hz, the
> next lower freq will be 500M, which is a too large step.
> > 
> > > > The notifying mechanism even allows you to
> > > > block any concurrent change in between these three steps if necessary.
> > > > Noone says that these three steps have to be encapsulated in a single
> > > > clk_set_rate call like you did in your patch.
> > > If you're reviwing the patch, why not take a step advance? :)
> > 
> > I have prepared the patches for converting i.MX1/21/25/27 and I have
> > (older) patches for the i.MX31/51/53 which I want to rebase on the
> > current clock framework. 
> You might notice I ever sent out serveral versions of MX5x clock porting
> patches based on your first version. If you want to take it over, it's ok.

No, I don't want to use the static initializers.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From balbi at ti.com  Mon Mar 19 04:33:39 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon, 19 Mar 2012 10:33:39 +0200
Subject: [PATCH 2/2] Input: omap-keypad: dynamically handle register
 offsets
In-Reply-To: <CAKdam54CudK-BoeAfOMrcHk51D9QsUbPhh5=Rqw5_ERCu2BpKA@mail.gmail.com>
References: <1331907989-11891-1-git-send-email-sourav.poddar@ti.com>
 <1331907989-11891-3-git-send-email-sourav.poddar@ti.com>
 <20120317054715.GB20049@core.coreip.homeip.net>
 <CAKdam54CudK-BoeAfOMrcHk51D9QsUbPhh5=Rqw5_ERCu2BpKA@mail.gmail.com>
Message-ID: <20120319083338.GB13774@arwen.pp.htv.fi>

Hi,

On Mon, Mar 19, 2012 at 01:27:50PM +0530, Poddar, Sourav wrote:
> 
> 
> On Sat, Mar 17, 2012 at 11:17 AM, Dmitry Torokhov <dmitry.torokhov at gmail.com>
> wrote:
> 
>     Hi Sourav,
> 
>     On Fri, Mar 16, 2012 at 07:56:29PM +0530, Sourav Poddar wrote:
>     > From: G, Manjunath Kondaiah <manjugk at ti.com>
>     >
>     > Keypad controller register offsets are different for omap4
>     > and omap5. Handle these offsets through static mapping and
>     > assign these mappings during run time.
>     >
>     > Signed-off-by: Felipe Balbi <balbi at ti.com>
>     > Signed-off-by: G, Manjunath Kondaiah <manjugk at ti.com>
>     > Signed-off-by: Sourav Poddar <sourav.poddar at ti.com>
>     > ---
>     >  drivers/input/keyboard/Kconfig        |    6 +-
>     >  drivers/input/keyboard/omap4-keypad.c |  122
>     ++++++++++++++++++++++++++------
>     >  2 files changed, 102 insertions(+), 26 deletions(-)
>     >
>     > diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/
>     Kconfig
>     > index 1379daa..09d7d0b 100644
>     > --- a/drivers/input/keyboard/Kconfig
>     > +++ b/drivers/input/keyboard/Kconfig
>     > @@ -510,10 +510,10 @@ config KEYBOARD_OMAP
>     >         To compile this driver as a module, choose M here: the
>     >         module will be called omap-keypad.
>     >
>     > -config KEYBOARD_OMAP4
>     > -     tristate "TI OMAP4 keypad support"
>     > +config KEYBOARD_OMAP4+
>     > +     tristate "TI OMAP4+ keypad support"
>     >       help
>     > -       Say Y here if you want to use the OMAP4 keypad.
>     > +       Say Y here if you want to use the OMAP4+ keypad.
>     >
>     >         To compile this driver as a module, choose M here: the
>     >         module will be called omap4-keypad.
>     > diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/
>     keyboard/omap4-keypad.c
>     > index e809ac0..6872495 100644
>     > --- a/drivers/input/keyboard/omap4-keypad.c
>     > +++ b/drivers/input/keyboard/omap4-keypad.c
>     > @@ -68,6 +68,11 @@
>     >
>     >  #define OMAP4_MASK_IRQSTATUSDISABLE  0xFFFF
>     >
>     > +enum {
>     > +     KBD_REVISION_OMAP4 = 0,
>     > +     KBD_REVISION_OMAP5,
>     > +};
>     > +
>     >  struct omap4_keypad {
>     >       struct input_dev *input;
>     >
>     > @@ -76,11 +81,79 @@ struct omap4_keypad {
>     >
>     >       unsigned int rows;
>     >       unsigned int cols;
>     > +     unsigned int revision;
>     >       unsigned int row_shift;
>     >       unsigned char key_state[8];
>     >       unsigned short keymap[];
>     >  };
>     >
>     > +static int kbd_read_irqstatus(struct omap4_keypad *keypad_data, u32
>     offset)
>     > +{
>     > +     if (keypad_data->revision == KBD_REVISION_OMAP4)
>     > +             return __raw_readl(keypad_data->base + offset);
>     > +     else if (keypad_data->revision == KBD_REVISION_OMAP5)
>     > +             return __raw_readl(keypad_data->base + offset + 0x0c);
>     > +
> 
>     This is called from ISR and doing comparisons seems quite wasteful. Why
>     don't you stuff register numbers for IRQ manipulations into struct
>     omap4_keypad at probe time and your function would just do:
> 
>            return __raw_readl(keypad_data->base + keypad_data->irqstatus_reg);
> 
> 
> Yes, can do that way . Will make necessary changes and post it again.
> 
>     And do the same for irqstatus. FOr the rest of the register store the
> 
>      I think you mean "irqenable" here.
> 
>     common offset (seems to be 0x10).
> 
>     > +     return -ENODEV;
>     > +}
>     > +
>     > +static int kbd_write_irqstatus(struct omap4_keypad *keypad_data,
>     > +                                             u32 offset, u32 value)
>     > +{
>     > +     if (keypad_data->revision == KBD_REVISION_OMAP4)
>     > +             return __raw_writel(value, keypad_data->base + offset);
>     > +     else if (keypad_data->revision == KBD_REVISION_OMAP5)
>     > +             return __raw_writel(value, keypad_data->base + offset +
>     0x0c);
>     > +
>     > +     return -ENODEV;
>     > +}
>     > +
>     > +static int kbd_write_irqenable(struct omap4_keypad *keypad_data,
>     > +                                             u32 offset, u32 value)
>     > +{
>     > +     if (keypad_data->revision == KBD_REVISION_OMAP4)
>     > +             return __raw_writel(value, keypad_data->base + offset);
>     > +     else if (keypad_data->revision == KBD_REVISION_OMAP5)
>     > +             return __raw_writel(value, keypad_data->base + offset +
>     0x0c);
>     > +
>     > +     return -ENODEV;
>     > +}
>     > +
>     > +static int kbd_readl(struct omap4_keypad *keypad_data, u32 offset)
>     > +{
>     > +     if (keypad_data->revision == KBD_REVISION_OMAP4)
>     > +             return __raw_readl(keypad_data->base + offset);
>     > +     else if (keypad_data->revision == KBD_REVISION_OMAP5)
>     > +             return __raw_readl(keypad_data->base + offset + 0x10);
>     > +
>     > +     return -ENODEV;
>     > +}
>     > +
>     > +static void kbd_writel(struct omap4_keypad *keypad_data, u32 offset, u32
>     value)
>     > +{
>     > +     if (keypad_data->revision == KBD_REVISION_OMAP4)
>     > +             __raw_writel(value, keypad_data->base + offset);
>     > +     else if (keypad_data->revision == KBD_REVISION_OMAP5)
>     > +             __raw_writel(value, keypad_data->base + offset + 0x10);
>     > +}
>     > +
>     > +static int kbd_read_revision(struct omap4_keypad *keypad_data, u32
>     offset)
>     > +{
>     > +     int reg;
>     > +     reg = __raw_readl(keypad_data->base + offset);
>     > +     reg &= 0x03 << 30;
>     > +     reg >>= 30;
>     > +
>     > +     switch (reg) {
>     > +     case 1:
>     > +             return KBD_REVISION_OMAP5;
>     > +     case 0:
>     > +             return KBD_REVISION_OMAP4;
>     > +     default:
>     > +             return -ENODEV;
>     > +     }
>     > +}
>     > +
>     >  /* Interrupt handler */
>     >  static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id)
>     >  {
>     > @@ -91,12 +164,11 @@ static irqreturn_t omap4_keypad_interrupt(int irq,
>     void *dev_id)
>     >       u32 *new_state = (u32 *) key_state;
>     >
>     >       /* Disable interrupts */
>     > -     __raw_writel(OMAP4_VAL_IRQDISABLE,
>     > -                  keypad_data->base + OMAP4_KBD_IRQENABLE);
>     > +     kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
>     > +                                             OMAP4_VAL_IRQDISABLE);
>     >
>     > -     *new_state = __raw_readl(keypad_data->base +
>     OMAP4_KBD_FULLCODE31_0);
>     > -     *(new_state + 1) = __raw_readl(keypad_data->base
>     > -                                             + OMAP4_KBD_FULLCODE63_32);
>     > +     *new_state = kbd_readl(keypad_data, OMAP4_KBD_FULLCODE31_0);
>     > +     *(new_state + 1) = kbd_readl(keypad_data, OMAP4_KBD_FULLCODE63_32);
>     >
>     >       for (row = 0; row < keypad_data->rows; row++) {
>     >               changed = key_state[row] ^ keypad_data->key_state[row];
>     > @@ -121,12 +193,13 @@ static irqreturn_t omap4_keypad_interrupt(int irq,
>     void *dev_id)
>     >               sizeof(keypad_data->key_state));
>     >
>     >       /* clear pending interrupts */
>     > -     __raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS),
>     > -                     keypad_data->base + OMAP4_KBD_IRQSTATUS);
>     > +     kbd_write_irqstatus(keypad_data, OMAP4_KBD_IRQSTATUS,
>     > +                     kbd_read_irqstatus(keypad_data,
>     OMAP4_KBD_IRQSTATUS));
>     >
>     >       /* enable interrupts */
>     > -     __raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN |
>     OMAP4_DEF_IRQENABLE_LONGKEY,
>     > -                     keypad_data->base + OMAP4_KBD_IRQENABLE);
>     > +     kbd_write_irqenable(keypad_data, OMAP4_KBD_IRQENABLE,
>     > +                     OMAP4_DEF_IRQENABLE_EVENTEN |
>     > +                             OMAP4_DEF_IRQENABLE_LONGKEY);
>     >
>     >       return IRQ_HANDLED;
>     >  }
>     > @@ -139,16 +212,19 @@ static int omap4_keypad_open(struct input_dev
>     *input)
>     >
>     >       disable_irq(keypad_data->irq);
>     >
>     > -     __raw_writel(OMAP4_VAL_FUNCTIONALCFG,
>     > -                     keypad_data->base + OMAP4_KBD_CTRL);
>     > -     __raw_writel(OMAP4_VAL_DEBOUNCINGTIME,
>     > -                     keypad_data->base + OMAP4_KBD_DEBOUNCINGTIME);
>     > -     __raw_writel(OMAP4_VAL_IRQDISABLE,
>     > -                     keypad_data->base + OMAP4_KBD_IRQSTATUS);
>     > -     __raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN |
>     OMAP4_DEF_IRQENABLE_LONGKEY,
>     > -                     keypad_data->base + OMAP4_KBD_IRQENABLE);
>     > -     __raw_writel(OMAP4_DEF_WUP_EVENT_ENA | OMAP4_DEF_WUP_LONG_KEY_ENA,
>     > -                     keypad_data->base + OMAP4_KBD_WAKEUPENABLE);
>     > +     keypad_data->revision = kbd_read_revision(keypad_data,
>     > +                     OMAP4_KBD_REVISION);
> 
>     You want to bail out of kbd_read_revision() returns error here.
> 
> 
> Yes, will include a error check.

Please send text/plain emails. You're currently sending multipart:

Content-Type: multipart/alternative;

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balbi
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From philipp.zabel at gmail.com  Mon Mar 19 04:47:19 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Mon, 19 Mar 2012 09:47:19 +0100
Subject: [RFC/PATCH 4/4] pxa: convert to common clock framework
In-Reply-To: <20120317160744.GE29317@pengutronix.de>
References: <1331919483.31118.23.camel@flow>
 <CAJOA=zN2dxgjQ8EZYAwE=OLO1GLdArqy1Xf18F82en9QvFi4cw@mail.gmail.com>
 <CA+gwMcdzHpGhLXXh5QTYid+rBtj8cGqFS9Te4QB3rpR9B8hXUw@mail.gmail.com>
 <20120317160744.GE29317@pengutronix.de>
Message-ID: <CA+gwMceR=iPpt0Ca=nWEDuR3Y3yp=LTVOrRD--qO4QOnUwKUHA@mail.gmail.com>

On Sat, Mar 17, 2012 at 5:07 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Sat, Mar 17, 2012 at 11:24:25AM +0100, Philipp Zabel wrote:
>> If there was a fixed fractional divider clk element, a lot of the
>> peripheral clocks could be derived from a fixed clk representing the
>> 312 MHz PPLL on PXA27x (fixed -> divider -> gate), using just the
>> basic clock templates.
>
> You could try the following. It is not thoroughly tested but may be a
> starting point. I need this aswell for i.MX so I will continue to work
> on it soon.

Thanks, this is exactly what I was looking for.

I'm a bit wary of adding so many clocks that just represent fixed
hardware, especially with the amount of function calls needed.
But describing the clock tree correctly appeals to my sense of order.

What is the take of the PXA maintainers on this?
Are there maybe plans to add device tree support for PXA?

regards
Philipp


From philipp.zabel at gmail.com  Mon Mar 19 04:51:32 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Mon, 19 Mar 2012 09:51:32 +0100
Subject: [RFC/PATCH 4/4] pxa: convert to common clock framework
In-Reply-To: <20120318054329.GA29638@S2101-09.ap.freescale.net>
References: <1331919483.31118.23.camel@flow>
 <20120318054329.GA29638@S2101-09.ap.freescale.net>
Message-ID: <CA+gwMcfcoQEcP4wsnkoy3djoUyih=J+wN-HFKV7ng-zhsaoR9w@mail.gmail.com>

On Sun, Mar 18, 2012 at 6:43 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> Your patch #2 is trying to avoid the layering violation by separating
> static clock definitions and from clk_ops implementations into
> different files. ?But ...
>
> On Fri, Mar 16, 2012 at 06:38:03PM +0100, Philipp Zabel wrote:
> ...
>> diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
>> index a3585a2..7c04f9b 100644
>> --- a/arch/arm/mach-pxa/clock.h
>> +++ b/arch/arm/mach-pxa/clock.h
>> @@ -1,80 +1,106 @@
>> ?#include <linux/clkdev.h>
>> +#include <linux/clk-private.h>
>
> ... This is what I read from clk-private.h.

Thank you.
I could just remove that include line from clock.h, because it is only
needed for the static clock definition macros.
The pxa[23]?x.c, where they are used, already #include <clk-private.h> directly.
Or, to do it properly, clock.h could also be split in two.

regards
Philipp


From linux at arm.linux.org.uk  Mon Mar 19 04:55:03 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 19 Mar 2012 08:55:03 +0000
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
Message-ID: <20120319085503.GL15988@n2100.arm.linux.org.uk>

On Mon, Mar 19, 2012 at 04:02:48PM +0900, Boojin Kim wrote:
> This patch uses LDRD/STRD that loads and stores data as DWORD unit
> for the copy of 8-words data.
> It brings better performance than LDRM/STRM that was used originally.

And what about CPUs that don't have ldrd/strd ?


From arnd at arndb.de  Mon Mar 19 04:57:23 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 08:57:23 +0000
Subject: ARM: fix build failure on ux500 in linux-next
In-Reply-To: <CACRpkdYzS=wkfUU4gJLTp7djd6J20zVCC_6XhrjwoVpAoSe8iA@mail.gmail.com>
References: <20120316211759.GA18829@windriver.com>
 <CACRpkdYzS=wkfUU4gJLTp7djd6J20zVCC_6XhrjwoVpAoSe8iA@mail.gmail.com>
Message-ID: <201203190857.23489.arnd@arndb.de>

On Sunday 18 March 2012, Linus Walleij wrote:
> On Fri, Mar 16, 2012 at 10:18 PM, Paul Gortmaker
> <paul.gortmaker at windriver.com> wrote:
> 
> > When I 1st saw this build failure, I thought it was me, because of the
> > BUG() stuff.  But git bisect claims it comes from the arm-soc tree?
> 
> Hm yeah looks like that, but we cannot see which commit
> I guess, just that it's the merge from ARM SoC?
> 
> > In any case, the fix is trivial and self evident, regardless of where
> > it came from.  I can carry it in my bug-3.4 cleanup tree if need be.
> > Let me know if you want me to do that.
> 
> Any way that solves the issue is fine with me, maybe Arnd/Olof
> wants to apply it to the ARM SoC tree rather? If they don't say
> anything, by all means please keep it in cleanup.

As Lee commented, it should be fixed already with Marc's fixup patch.
Paul, if you still see it in some configuration on the today's linux-next,
please let us know.

	Arnd


From nicolas.ferre at atmel.com  Mon Mar 19 05:00:27 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 19 Mar 2012 10:00:27 +0100
Subject: linux-next: manual merge of the arm-soc tree with the l2-mtd tree
In-Reply-To: <20120319174743.aff001d4f84e82cf4042277a@canb.auug.org.au>
References: <20120319174743.aff001d4f84e82cf4042277a@canb.auug.org.au>
Message-ID: <4F66F5AB.7020600@atmel.com>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 03/19/2012 07:47 AM, Stephen Rothwell :
> Hi all,
> 
> Today's linux-next merge of the arm-soc tree got a conflict in 
> drivers/mtd/nand/atmel_nand.c between commit 4331c79c6895 ("mtd: do
> not use plain 0 as NULL") from the l2-mtd tree and commit
> d6a016616ba8 ("atmel/nand: add DT support") from the arm-soc tree.
> 
> The latter superceded the former, so I used that.

That is definitively the proper fix. Thanks Stephen.

Best regards,
- -- 
Nicolas Ferre
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From gxt at pku.edu.cn  Mon Mar 19 05:05:35 2012
From: gxt at pku.edu.cn (Guan Xueao)
Date: Mon, 19 Mar 2012 17:05:35 +0800
Subject: [PATCH] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
References: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <4F66F6DF.8010609@pku.edu.cn>

On 03/17/2012 05:03 AM, Stephen Warren wrote:
> All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
> to avoid duplication.
>
> All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
> parameterized version in Makefile.lib to avoid duplication.
>
> Signed-off-by: Stephen Warren<swarren at wwwdotorg.org>
> ---
> v2:
> * Fix blackfin's UIMAGE_LOADADDR in the ROMKERNEL case.
> * Fix missing ) on a variable reference in avr32 and sparc.
> * Only set those UIMAGE_* variables that the arch-specific Makefile hasn't
>    already set.
> * The patch series is now just this single patch which removes duplication;
>    I've dropped the Kconfig feature to allow use of -T kernel_noload for
>    now, since it looks like U-Boot is gaining direct zImage support.
>
>
Tested on unicore32.

Tested-by: Guan Xuetao <gxt at mprc.pku.edu.cn>



From tomi.valkeinen at ti.com  Mon Mar 19 05:08:36 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Mon, 19 Mar 2012 11:08:36 +0200
Subject: [PATCH v2 7/7] ARM: OMAP2+: Mark omap_hsmmc_init and omap_mux
 related functions as __init
In-Reply-To: <1329997247-27342-8-git-send-email-rnayak@ti.com>
References: <1329997247-27342-1-git-send-email-rnayak@ti.com>
 <1329997247-27342-8-git-send-email-rnayak@ti.com>
Message-ID: <1332148116.2144.1.camel@deskari>

Hi,

On Thu, 2012-02-23 at 17:10 +0530, Rajendra Nayak wrote:
> From: Tony Lindgren <tony at atomide.com>
> 
> Now that omap hsmmc init is split into two functions, it's safe
> to mark omap_hsmmc_init and omap_mux related functions to __init.
> 
> This basically reverts the following fixes for the case where
> TWL was compiled as a module:
> 
> a98f77b (ARM: omap: fix section mismatch warning for sdp3430_twl_gpio_setup())
> 8930b4e (ARM: omap: fix section mismatch warnings in mux.c caused by hsmmc.c)
> 
> Additionally it fixes up the remaining section warnings for
> all callers of omap_mux functions.

I only now noticed this patch. This breaks DSI, as the DSI muxing
functions are used during runtime and cannot be marked as __init.

Shall I make a new patch for dss tree that fixes this?

 Tomi

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From t-kristo at ti.com  Mon Mar 19 05:48:45 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Mon, 19 Mar 2012 11:48:45 +0200
Subject: [PATCH v3 1/2] arm: omap3: pm34xx.c: Fix omap3_pm_init() error
 out paths
In-Reply-To: <1332033768-21986-2-git-send-email-mgreer@animalcreek.com>
References: <1332033768-21986-1-git-send-email-mgreer@animalcreek.com>
 <1332033768-21986-2-git-send-email-mgreer@animalcreek.com>
Message-ID: <1332150525.2116.334.camel@sokoban>

On Sat, 2012-03-17 at 18:22 -0700, Mark A. Greer wrote:
> From: "Mark A. Greer" <mgreer at animalcreek.com>
> 
> It appears that the error paths were overlooked when the
> omap3_pm_init() routine had the prcm chain handler code
> added.  Fix this by adding a goto target and reordering
> the error handling code.  Also fix how the irq argument
> for free_irq() is determined.

You are right, it looks like the error handling part was accidentally
dropped from version 7 of the prcm patch set.

Acked-by: Tero Kristo <t-kristo at ti.com>

Paul, you going to grab this?

-Tero


> 
> CC: Tero Kristo <t-kristo at ti.com>
> Signed-off-by: Mark A. Greer <mgreer at animalcreek.com>
> ---
>  arch/arm/mach-omap2/pm34xx.c |   16 ++++++++++------
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 27fc7a2..af8d741 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -817,13 +817,13 @@ static int __init omap3_pm_init(void)
>  
>  	if (ret) {
>  		pr_err("pm: Failed to request pm_io irq\n");
> -		goto err1;
> +		goto err2;
>  	}
>  
>  	ret = pwrdm_for_each(pwrdms_setup, NULL);
>  	if (ret) {
>  		printk(KERN_ERR "Failed to setup powerdomains\n");
> -		goto err2;
> +		goto err3;
>  	}
>  
>  	(void) clkdm_for_each(clkdms_setup, NULL);
> @@ -831,7 +831,8 @@ static int __init omap3_pm_init(void)
>  	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
>  	if (mpu_pwrdm == NULL) {
>  		printk(KERN_ERR "Failed to get mpu_pwrdm\n");
> -		goto err2;
> +		ret = -EINVAL;
> +		goto err3;
>  	}
>  
>  	neon_pwrdm = pwrdm_lookup("neon_pwrdm");
> @@ -879,14 +880,17 @@ static int __init omap3_pm_init(void)
>  	}
>  
>  	omap3_save_scratchpad_contents();
> -err1:
>  	return ret;
> -err2:
> -	free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
> +
> +err3:
>  	list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
>  		list_del(&pwrst->node);
>  		kfree(pwrst);
>  	}
> +	free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
> +err2:
> +	free_irq(omap_prcm_event_to_irq("wkup"), NULL);
> +err1:
>  	return ret;
>  }
>  




From arnd at arndb.de  Mon Mar 19 06:00:33 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 10:00:33 +0000
Subject: [RFC/PATCH 4/4] pxa: convert to common clock framework
In-Reply-To: <CA+gwMceR=iPpt0Ca=nWEDuR3Y3yp=LTVOrRD--qO4QOnUwKUHA@mail.gmail.com>
References: <1331919483.31118.23.camel@flow>
 <20120317160744.GE29317@pengutronix.de>
 <CA+gwMceR=iPpt0Ca=nWEDuR3Y3yp=LTVOrRD--qO4QOnUwKUHA@mail.gmail.com>
Message-ID: <201203191000.33905.arnd@arndb.de>

On Monday 19 March 2012, Philipp Zabel wrote:

> Thanks, this is exactly what I was looking for.
> 
> I'm a bit wary of adding so many clocks that just represent fixed
> hardware, especially with the amount of function calls needed.
> But describing the clock tree correctly appeals to my sense of order.
> 
> What is the take of the PXA maintainers on this?
> Are there maybe plans to add device tree support for PXA?
> 

Haojian Zhuang has been busy posting DT patches recently. The patches
ended up being too late for v3.4, but I expect the first set to get
submitted for arm-soc after the merge window has ended.

There is still some infrastructure work required, e.g. in the interrupt
controller, but things will be easier after -rc1 when the irqdomain and
clk support is merged.

	Arnd


From arnd at arndb.de  Mon Mar 19 05:40:01 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 09:40:01 +0000
Subject: linux-next: build warning after merge of the arm-soc tree
In-Reply-To: <20120319183911.0cd46df560c714ee71184242@canb.auug.org.au>
References: <20120319183911.0cd46df560c714ee71184242@canb.auug.org.au>
Message-ID: <201203190940.02329.arnd@arndb.de>

On Monday 19 March 2012, Stephen Rothwell wrote:
> Hi all,
> 
> After merging the arm-soc tree, today's linux-next build (all)
> produced this warning:
> 
> drivers/clk/Kconfig:22: warning: menuconfig statement without prompt
> 
> Introduced by commit c173033d154e ("clk: make CONFIG_COMMON_CLK invisible").

Thanks for the report. This is clearly my fault for not testing the last
minute patch.
I have now replaced it with the one below and tested that it works
as intended.

	Arnd


commit 8fb61e33507e5d76b69467b4f96290338e96b733
Author: Arnd Bergmann <arnd at arndb.de>
Date:   Sat Mar 17 21:10:51 2012 +0000

    clk: make CONFIG_COMMON_CLK invisible
    
    All platforms that use the common clk infrastructure should select
    COMMON_CLK from platform code, and on all other platforms, it must
    not be enabled, so there is no point making the option visible to
    users, and when it is visible, we break randconfig builds.
    
    Signed-off-by: Arnd Bergmann <arnd at arndb.de>

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 2eaf17e..165e1fe 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -9,21 +9,18 @@ config HAVE_CLK_PREPARE
 config HAVE_MACH_CLKDEV
 	bool
 
-menuconfig COMMON_CLK
-	bool "Common Clock Framework"
+config COMMON_CLK
+	bool
 	select HAVE_CLK_PREPARE
 	---help---
 	  The common clock framework is a single definition of struct
 	  clk, useful across many platforms, as well as an
 	  implementation of the clock API in include/linux/clk.h.
 	  Architectures utilizing the common struct clk should select
-	  this automatically, but it may be necessary to manually select
-	  this option for loadable modules requiring the common clock
-	  framework.
-
-	  If in doubt, say "N".
+	  this option.
 
-if COMMON_CLK
+menu "Common Clock Framework"
+	depends on COMMON_CLK
 
 config COMMON_CLK_DISABLE_UNUSED
 	bool "Disabled unused clocks at boot"
@@ -47,4 +44,4 @@ config COMMON_CLK_DEBUG
 	  clk_flags, clk_prepare_count, clk_enable_count &
 	  clk_notifier_count.
 
-endif
+endmenu



From tomi.valkeinen at ti.com  Mon Mar 19 06:20:42 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Mon, 19 Mar 2012 12:20:42 +0200
Subject: [PATCH v2 7/7] ARM: OMAP2+: Mark omap_hsmmc_init and omap_mux
 related functions as __init
In-Reply-To: <1332148116.2144.1.camel@deskari>
References: <1329997247-27342-1-git-send-email-rnayak@ti.com>
 <1329997247-27342-8-git-send-email-rnayak@ti.com>
 <1332148116.2144.1.camel@deskari>
Message-ID: <1332152442.2144.27.camel@deskari>

On Mon, 2012-03-19 at 11:08 +0200, Tomi Valkeinen wrote:
> Hi,
> 
> On Thu, 2012-02-23 at 17:10 +0530, Rajendra Nayak wrote:
> > From: Tony Lindgren <tony at atomide.com>
> > 
> > Now that omap hsmmc init is split into two functions, it's safe
> > to mark omap_hsmmc_init and omap_mux related functions to __init.
> > 
> > This basically reverts the following fixes for the case where
> > TWL was compiled as a module:
> > 
> > a98f77b (ARM: omap: fix section mismatch warning for sdp3430_twl_gpio_setup())
> > 8930b4e (ARM: omap: fix section mismatch warnings in mux.c caused by hsmmc.c)
> > 
> > Additionally it fixes up the remaining section warnings for
> > all callers of omap_mux functions.
> 
> I only now noticed this patch. This breaks DSI, as the DSI muxing
> functions are used during runtime and cannot be marked as __init.
> 
> Shall I make a new patch for dss tree that fixes this?

(too little coffee)

Obviously I can't make a fix in my tree for that, as the problematic
patch is not present there... So here's a patch to fix it, based on
arm-soc/for-next



From b00c2464de51ba6f297371b08bb7745c528fde59 Mon Sep 17 00:00:00 2001
From: Tomi Valkeinen <tomi.valkeinen at ti.com>
Date: Mon, 19 Mar 2012 11:08:54 +0200
Subject: [PATCH] ARM: OMAP2+: Remove __init from DSI mux functions

Commit d1589f0912533e6cb2ac8fd6f1feb3d5989fe8cb (ARM: OMAP2+: Mark
omap_hsmmc_init and omap_mux related functions as __init) changed DSI
muxing functions to __init. This doesn't work, as the muxing functions
are used every time a DSI display is enabled or disabled.

This patch removes the __inits from DSI mux functions.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen at ti.com>
---
 arch/arm/mach-omap2/display.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/display.c
b/arch/arm/mach-omap2/display.c
index 9706c64..400fa37 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -125,7 +125,7 @@ static void omap4_hdmi_mux_pads(enum omap_hdmi_flags
flags)
 	}
 }
 
-static int __init omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
+static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 {
 	u32 enable_mask, enable_shift;
 	u32 pipd_mask, pipd_shift;
@@ -166,7 +166,7 @@ int __init omap_hdmi_init(enum omap_hdmi_flags
flags)
 	return 0;
 }
 
-static int __init omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
+static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 {
 	if (cpu_is_omap44xx())
 		return omap4_dsi_mux_pads(dsi_id, lane_mask);
@@ -174,7 +174,7 @@ static int __init omap_dsi_enable_pads(int dsi_id,
unsigned lane_mask)
 	return 0;
 }
 
-static void __init omap_dsi_disable_pads(int dsi_id, unsigned
lane_mask)
+static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
 {
 	if (cpu_is_omap44xx())
 		omap4_dsi_mux_pads(dsi_id, 0);
-- 
1.7.4.1


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From dhowells at redhat.com  Mon Mar 19 06:45:11 2012
From: dhowells at redhat.com (David Howells)
Date: Mon, 19 Mar 2012 10:45:11 +0000
Subject: [PATCH 05/38] Disintegrate asm/system.h for ARM [ver #3]
In-Reply-To: <1331908808.12353.2.camel@deneb.redhat.com>
References: <1331908808.12353.2.camel@deneb.redhat.com>
 <20120315205514.28759.58969.stgit@warthog.procyon.org.uk>
 <20120315205603.28759.91855.stgit@warthog.procyon.org.uk>
Message-ID: <2349.1332153911@redhat.com>

Mark Salter <msalter at redhat.com> wrote:

> Looks like this hunk was unintended. It is causing a build failure for
> me.

Yep.  Removed that already and reissued the ARM chunk, though only on the ARM
list.

David


From dave.martin at linaro.org  Mon Mar 19 06:53:47 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Mon, 19 Mar 2012 10:53:47 +0000
Subject: [PATCH] arm: Add unwinding support for memset and memzero.
In-Reply-To: <4F63767E.3020706@codeaurora.org>
References: <1331574027-28542-1-git-send-email-lauraa@codeaurora.org>
 <20120314111504.GA2033@linaro.org>
 <4F63767E.3020706@codeaurora.org>
Message-ID: <20120319105346.GA2124@linaro.org>

On Fri, Mar 16, 2012 at 10:21:02AM -0700, Laura Abbott wrote:
> On 3/14/2012 4:15 AM, Dave Martin wrote:
> >
> >For functions like this, the unwinding requirements are different
> >depending on where we are in the function.  But the unwinder annotations
> >don't remember exact instruction locations; only the extent of the
> >whole unwind block is recorded, along with the sequence (but not
> >location) of unwinder directives.
> >
> >As is, the unwinding may be wrong depending on which part of the function
> >is executing when the fault occurs.
> >
> 
> Hmmmm, I thought I could get away with only one annotation based on
> the structure of memset/memzero but looking again you are right, it
> really requires multiple annotations to be correct.
> 
> >It may be possible to split the function into multiple unwind blocks,
> >e.g.:
> >
> >ENTRY(somefunc)
> >UNWIND(.fnstart)
> >
> >UNWIND(.save {r4,lr})
> >	stfmd	sp!, {r4,lr}
> >
> >	/* check something */
> >
> >	blt	_the_other_way
> >	/* maybe carry out our job this way */
> >
> >	ldmfd	sp!, {r4,lr}
> >UNWIND(.fnend)
> >
> >_the_other_way:
> >UNWIND(.fnstart)
> >UNWIND(.save {r4,lr})
> >UNWIND(.save {r5-r8})
> >	stmfd	sp!, {r5-r8}	/* !! */
> >
> >	/* carry out our job the other way */
> >
> >	ldmfd	sp!, {r5-r8}
> >	ldmfd	sp!, {r4,pc}	/* !! */
> >UNWIND(.fnend)
> >
> >
> >This is still not exactly right (it's hard to be exactly right,
> >since the unwind tables are not meant for handling asynchronous
> >unwinding), but unwinding should be correct for the main bits of code
> >where most time is spent and/or faults are most likely (the "carry out
> >our job" comments).
> >
> 
> Would a compiler be able to generate code such as this and still
> generate correct completely unwinding annotations? Or if the
> compiler knows unwinding is necessary, is the only option to
> generate code in 'unwindable blocks'? (alternatively, no compiler is
> smart/stupid enough to generate this code?)

I believe the compiler will typically generate a single unwind block per
function, with single save/restore sequences at the entry and exit
points which save/restore everything the function could possibly
use.  This means that unless a fault occurs in the save/restore
sequences (this would imply a stack overflow etc.) then the resulting
backtrace should be sensible.

In assembly functions, we do sometimes optimise things further, so
that if there is a fast path through the function we don't necessarily
do the full save/restore on that path.  However, deferring state save
like this doesn't fit the "single unwind block per function" model.

The unusual thing about the function being considered here is that
it has two parts where non-stack faults can reasonably occur, with
different save/restore frames in each part.

Cheers
---Dave


From hvaibhav at ti.com  Mon Mar 19 07:11:14 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Mon, 19 Mar 2012 11:11:14 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>	<87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>

On Tue, Mar 13, 2012 at 17:07:16, Ming Lei wrote:
> Hi,
> 
> On Tue, Jan 24, 2012 at 7:38 AM, Kevin Hilman <khilman at ti.com> wrote:
> > Vaibhav Hiremath <hvaibhav at ti.com> writes:
> >
> >> OMAP device has 32k-sync timer which is currently used as a
> >> clocksource in the kernel (omap2plus_defconfig).
> >> The current implementation uses compile time selection between
> >> gp-timer and 32k-sync timer, which breaks multi-omap build for
> >> the devices like AM33xx, where 32k-sync timer is not available.
> >>
> >> So use hwmod database lookup mechanism, through which at run-time
> >> we can identify availability of 32k-sync timer on the device,
> >> else fall back to gp-timer.
> >
> > With the runtime detection & fallback, I suggest also removing the
> > Kconfig choice between the two as well.
> 
> IMO, under some situations, gp timer clocksource has high precision
> and is very useful, so hope the Kconfig choice can be kept, or using
> kernel parameter way,  and the patch need to be changed to support the
> selection.
> 
> 

I think you made very good point here. With the above patch, we are almost missing the capability of registering dmtimer as a clocksource for OMAP.
It will always use 32k-counter, and never fall back to dmtimer.

Then the only options we have here is,

1) Register both the timers, 32k-counter and dmtimer for clocksource; let
   Kernel pick up best rating clocksource out of these two.

   In case of OMAP1/2/3/4, kernel will use dmtimer, since it has better 
   Rating. User can choose the 32k-counter clocksource via bootargs.

   Impact: without bootargs for clocksource selection, kernel will choose 
     dmtimer, impacting loss of time during suspend/resume.


2) Let the current code be as is, means, the clocksource registration will 
   Happened based on "#ifdef CONFIG_OMAP_32K_TIMER" and this option 
   selection will be Controlled by Kconfig rules.


Based on this conclusion, 1st patch of this series needs some changes.
But Irrespective of this, we still need 2 patches from this series,

[PATCH 2/3] ARM: OMAP2+: hwmod data: Add 32k-sync timer data to hwmod database
[PATCH 3/3] ARM: OMAP2/3: Add idle_st bits for ST_32KSYNC timer to prcm-common header


Thanks,
Vaibhav

> thanks,
> -- 
> Ming Lei
> 



From rnayak at ti.com  Mon Mar 19 07:22:05 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Mon, 19 Mar 2012 16:52:05 +0530
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <1331878280-2758-3-git-send-email-mturquette@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
Message-ID: <4F6716DD.5090900@ti.com>

Hi Mike,

On Friday 16 March 2012 11:41 AM, Mike Turquette wrote:
> The common clock framework defines a common struct clk useful across
> most platforms as well as an implementation of the clk api that drivers
> can use safely for managing clocks.
>
> The net result is consolidation of many different struct clk definitions
> and platform-specific clock framework implementations.
>
> This patch introduces the common struct clk, struct clk_ops and an
> implementation of the well-known clock api in include/clk/clk.h.
> Platforms may define their own hardware-specific clock structure and
> their own clock operation callbacks, so long as it wraps an instance of
> struct clk_hw.
>
> See Documentation/clk.txt for more details.
>

> +/*
> + * calculate the new rates returning the topmost clock that has to be
> + * changed.
> + */
> +static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
> +{
> +	struct clk *top = clk;
> +	unsigned long best_parent_rate = clk->parent->rate;

Shouldn't you check for a valid parent before dereferencing it? A
clk_set_rate() on a root clock might throw up some issues otherwise.

> +	unsigned long new_rate;
> +
> +	if (!clk->ops->round_rate&&  !(clk->flags&  CLK_SET_RATE_PARENT)) {
> +		clk->new_rate = clk->rate;
> +		return NULL;

So does this mean a clk_set_rate() fails for a clk which does not have
a valid .round_rate and does not have a CLK_SET_RATE_PARENT flag set?
I was thinking this could do a..
		clk->new_rate = rate;
		top = clk;
		goto out;
..instead.

regards,
Rajendra

> +	}
> +
> +	if (!clk->ops->round_rate&&  (clk->flags&  CLK_SET_RATE_PARENT)) {
> +		top = clk_calc_new_rates(clk->parent, rate);
> +		new_rate = clk->new_rate = clk->parent->new_rate;
> +
> +		goto out;
> +	}
> +
> +	if (clk->flags&  CLK_SET_RATE_PARENT)
> +		new_rate = clk->ops->round_rate(clk->hw, rate,&best_parent_rate);
> +	else
> +		new_rate = clk->ops->round_rate(clk->hw, rate, NULL);
> +
> +	if (best_parent_rate != clk->parent->rate) {
> +		top = clk_calc_new_rates(clk->parent, best_parent_rate);
> +
> +		goto out;
> +	}
> +
> +out:
> +	clk_calc_subtree(clk, new_rate);
> +
> +	return top;
> +}
> +
> +/*
> + * Notify about rate changes in a subtree. Always walk down the whole tree
> + * so that in case of an error we can walk down the whole tree again and
> + * abort the change.
> + */
> +static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long event)
> +{
> +	struct hlist_node *tmp;
> +	struct clk *child, *fail_clk = NULL;
> +	int ret = NOTIFY_DONE;
> +
> +	if (clk->rate == clk->new_rate)
> +		return 0;
> +
> +	if (clk->notifier_count) {
> +		ret = __clk_notify(clk, event, clk->rate, clk->new_rate);
> +		if (ret == NOTIFY_BAD)
> +			fail_clk = clk;
> +	}
> +
> +	hlist_for_each_entry(child, tmp,&clk->children, child_node) {
> +		clk = clk_propagate_rate_change(child, event);
> +		if (clk)
> +			fail_clk = clk;
> +	}
> +
> +	return fail_clk;
> +}
> +
> +/*
> + * walk down a subtree and set the new rates notifying the rate
> + * change on the way
> + */
> +static void clk_change_rate(struct clk *clk)
> +{
> +	struct clk *child;
> +	unsigned long old_rate;
> +	struct hlist_node *tmp;
> +
> +	old_rate = clk->rate;
> +
> +	if (clk->ops->set_rate)
> +		clk->ops->set_rate(clk->hw, clk->new_rate);
> +
> +	if (clk->ops->recalc_rate)
> +		clk->rate = clk->ops->recalc_rate(clk->hw,
> +				clk->parent->rate);
> +	else
> +		clk->rate = clk->parent->rate;
> +
> +	if (clk->notifier_count&&  old_rate != clk->rate)
> +		__clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);
> +
> +	hlist_for_each_entry(child, tmp,&clk->children, child_node)
> +		clk_change_rate(child);
> +}
> +
> +/**
> + * clk_set_rate - specify a new rate for clk
> + * @clk: the clk whose rate is being changed
> + * @rate: the new rate for clk
> + *
> + * In the simplest case clk_set_rate will only change the rate of clk.
> + *
> + * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call
> + * will fail; only when the clk is disabled will it be able to change
> + * its rate.
> + *
> + * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to
> + * recursively propagate up to clk's parent; whether or not this happens
> + * depends on the outcome of clk's .round_rate implementation.  If
> + * *parent_rate is 0 after calling .round_rate then upstream parent
> + * propagation is ignored.  If *parent_rate comes back with a new rate
> + * for clk's parent then we propagate up to clk's parent and set it's
> + * rate.  Upward propagation will continue until either a clk does not
> + * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting
> + * changes to clk's parent_rate.  If there is a failure during upstream
> + * propagation then clk_set_rate will unwind and restore each clk's rate
> + * that had been successfully changed.  Afterwards a rate change abort
> + * notification will be propagated downstream, starting from the clk
> + * that failed.
> + *
> + * At the end of all of the rate setting, clk_set_rate internally calls
> + * __clk_recalc_rates and propagates the rate changes downstream,
> + * starting from the highest clk whose rate was changed.  This has the
> + * added benefit of propagating post-rate change notifiers.
> + *
> + * Note that while post-rate change and rate change abort notifications
> + * are guaranteed to be sent to a clk only once per call to
> + * clk_set_rate, pre-change notifications will be sent for every clk
> + * whose rate is changed.  Stacking pre-change notifications is noisy
> + * for the drivers subscribed to them, but this allows drivers to react
> + * to intermediate clk rate changes up until the point where the final
> + * rate is achieved at the end of upstream propagation.
> + *
> + * Returns 0 on success, -EERROR otherwise.
> + */
> +int clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	struct clk *top, *fail_clk;
> +	int ret = 0;
> +
> +	/* prevent racing with updates to the clock topology */
> +	mutex_lock(&prepare_lock);
> +
> +	/* bail early if nothing to do */
> +	if (rate == clk->rate)
> +		goto out;
> +
> +	/* calculate new rates and get the topmost changed clock */
> +	top = clk_calc_new_rates(clk, rate);
> +	if (!top) {
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	/* notify that we are about to change rates */
> +	fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
> +	if (fail_clk) {
> +		pr_warn("%s: failed to set %s rate\n", __func__,
> +				fail_clk->name);
> +		clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
> +		ret = -EBUSY;
> +		goto out;
> +	}
> +
> +	/* change the rates */
> +	clk_change_rate(top);
> +
> +	mutex_unlock(&prepare_lock);
> +
> +	return 0;
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_set_rate);
> +
> +/**
> + * clk_get_parent - return the parent of a clk
> + * @clk: the clk whose parent gets returned
> + *
> + * Simply returns clk->parent.  Returns NULL if clk is NULL.
> + */
> +struct clk *clk_get_parent(struct clk *clk)
> +{
> +	struct clk *parent;
> +
> +	mutex_lock(&prepare_lock);
> +	parent = __clk_get_parent(clk);
> +	mutex_unlock(&prepare_lock);
> +
> +	return parent;
> +}
> +EXPORT_SYMBOL_GPL(clk_get_parent);
> +
> +/*
> + * .get_parent is mandatory for clocks with multiple possible parents.  It is
> + * optional for single-parent clocks.  Always call .get_parent if it is
> + * available and WARN if it is missing for multi-parent clocks.
> + *
> + * For single-parent clocks without .get_parent, first check to see if the
> + * .parents array exists, and if so use it to avoid an expensive tree
> + * traversal.  If .parents does not exist then walk the tree with __clk_lookup.
> + */
> +static struct clk *__clk_init_parent(struct clk *clk)
> +{
> +	struct clk *ret = NULL;
> +	u8 index;
> +
> +	/* handle the trivial cases */
> +
> +	if (!clk->num_parents)
> +		goto out;
> +
> +	if (clk->num_parents == 1) {
> +		if (IS_ERR_OR_NULL(clk->parent))
> +			ret = clk->parent = __clk_lookup(clk->parent_names[0]);
> +		ret = clk->parent;
> +		goto out;
> +	}
> +
> +	if (!clk->ops->get_parent) {
> +		WARN(!clk->ops->get_parent,
> +			"%s: multi-parent clocks must implement .get_parent\n",
> +			__func__);
> +		goto out;
> +	};
> +
> +	/*
> +	 * Do our best to cache parent clocks in clk->parents.  This prevents
> +	 * unnecessary and expensive calls to __clk_lookup.  We don't set
> +	 * clk->parent here; that is done by the calling function
> +	 */
> +
> +	index = clk->ops->get_parent(clk->hw);
> +
> +	if (!clk->parents)
> +		clk->parents =
> +			kmalloc((sizeof(struct clk*) * clk->num_parents),
> +					GFP_KERNEL);
> +
> +	if (!clk->parents)
> +		ret = __clk_lookup(clk->parent_names[index]);
> +	else if (!clk->parents[index])
> +		ret = clk->parents[index] =
> +			__clk_lookup(clk->parent_names[index]);
> +	else
> +		ret = clk->parents[index];
> +
> +out:
> +	return ret;
> +}
> +
> +void __clk_reparent(struct clk *clk, struct clk *new_parent)
> +{
> +#ifdef CONFIG_COMMON_CLK_DEBUG
> +	struct dentry *d;
> +	struct dentry *new_parent_d;
> +#endif
> +
> +	if (!clk || !new_parent)
> +		return;
> +
> +	hlist_del(&clk->child_node);
> +
> +	if (new_parent)
> +		hlist_add_head(&clk->child_node,&new_parent->children);
> +	else
> +		hlist_add_head(&clk->child_node,&clk_orphan_list);
> +
> +#ifdef CONFIG_COMMON_CLK_DEBUG
> +	if (!inited)
> +		goto out;
> +
> +	if (new_parent)
> +		new_parent_d = new_parent->dentry;
> +	else
> +		new_parent_d = orphandir;
> +
> +	d = debugfs_rename(clk->dentry->d_parent, clk->dentry,
> +			new_parent_d, clk->name);
> +	if (d)
> +		clk->dentry = d;
> +	else
> +		pr_debug("%s: failed to rename debugfs entry for %s\n",
> +				__func__, clk->name);
> +out:
> +#endif
> +
> +	clk->parent = new_parent;
> +
> +	__clk_recalc_rates(clk, POST_RATE_CHANGE);
> +}
> +
> +static int __clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> +	struct clk *old_parent;
> +	unsigned long flags;
> +	int ret = -EINVAL;
> +	u8 i;
> +
> +	old_parent = clk->parent;
> +
> +	/* find index of new parent clock using cached parent ptrs */
> +	for (i = 0; i<  clk->num_parents; i++)
> +		if (clk->parents[i] == parent)
> +			break;
> +
> +	/*
> +	 * find index of new parent clock using string name comparison
> +	 * also try to cache the parent to avoid future calls to __clk_lookup
> +	 */
> +	if (i == clk->num_parents)
> +		for (i = 0; i<  clk->num_parents; i++)
> +			if (!strcmp(clk->parent_names[i], parent->name)) {
> +				clk->parents[i] = __clk_lookup(parent->name);
> +				break;
> +			}
> +
> +	if (i == clk->num_parents) {
> +		pr_debug("%s: clock %s is not a possible parent of clock %s\n",
> +				__func__, parent->name, clk->name);
> +		goto out;
> +	}
> +
> +	/* migrate prepare and enable */
> +	if (clk->prepare_count)
> +		__clk_prepare(parent);
> +
> +	/* FIXME replace with clk_is_enabled(clk) someday */
> +	spin_lock_irqsave(&enable_lock, flags);
> +	if (clk->enable_count)
> +		__clk_enable(parent);
> +	spin_unlock_irqrestore(&enable_lock, flags);
> +
> +	/* change clock input source */
> +	ret = clk->ops->set_parent(clk->hw, i);
> +
> +	/* clean up old prepare and enable */
> +	spin_lock_irqsave(&enable_lock, flags);
> +	if (clk->enable_count)
> +		__clk_disable(old_parent);
> +	spin_unlock_irqrestore(&enable_lock, flags);
> +
> +	if (clk->prepare_count)
> +		__clk_unprepare(old_parent);
> +
> +out:
> +	return ret;
> +}
> +
> +/**
> + * clk_set_parent - switch the parent of a mux clk
> + * @clk: the mux clk whose input we are switching
> + * @parent: the new input to clk
> + *
> + * Re-parent clk to use parent as it's new input source.  If clk has the
> + * CLK_SET_PARENT_GATE flag set then clk must be gated for this
> + * operation to succeed.  After successfully changing clk's parent
> + * clk_set_parent will update the clk topology, sysfs topology and
> + * propagate rate recalculation via __clk_recalc_rates.  Returns 0 on
> + * success, -EERROR otherwise.
> + */
> +int clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> +	int ret = 0;
> +
> +	if (!clk || !clk->ops)
> +		return -EINVAL;
> +
> +	if (!clk->ops->set_parent)
> +		return -ENOSYS;
> +
> +	/* prevent racing with updates to the clock topology */
> +	mutex_lock(&prepare_lock);
> +
> +	if (clk->parent == parent)
> +		goto out;
> +
> +	/* propagate PRE_RATE_CHANGE notifications */
> +	if (clk->notifier_count)
> +		ret = __clk_speculate_rates(clk, parent->rate);
> +
> +	/* abort if a driver objects */
> +	if (ret == NOTIFY_STOP)
> +		goto out;
> +
> +	/* only re-parent if the clock is not in use */
> +	if ((clk->flags&  CLK_SET_PARENT_GATE)&&  clk->prepare_count)
> +		ret = -EBUSY;
> +	else
> +		ret = __clk_set_parent(clk, parent);
> +
> +	/* propagate ABORT_RATE_CHANGE if .set_parent failed */
> +	if (ret) {
> +		__clk_recalc_rates(clk, ABORT_RATE_CHANGE);
> +		goto out;
> +	}
> +
> +	/* propagate rate recalculation downstream */
> +	__clk_reparent(clk, parent);
> +
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_set_parent);
> +
> +/**
> + * __clk_init - initialize the data structures in a struct clk
> + * @dev:	device initializing this clk, placeholder for now
> + * @clk:	clk being initialized
> + *
> + * Initializes the lists in struct clk, queries the hardware for the
> + * parent and rate and sets them both.
> + *
> + * Any struct clk passed into __clk_init must have the following members
> + * populated:
> + * 	.name
> + * 	.ops
> + * 	.hw
> + * 	.parent_names
> + * 	.num_parents
> + * 	.flags
> + *
> + * Essentially, everything that would normally be passed into clk_register is
> + * assumed to be initialized already in __clk_init.  The other members may be
> + * populated, but are optional.
> + *
> + * __clk_init is only exposed via clk-private.h and is intended for use with
> + * very large numbers of clocks that need to be statically initialized.  It is
> + * a layering violation to include clk-private.h from any code which implements
> + * a clock's .ops; as such any statically initialized clock data MUST be in a
> + * separate C file from the logic that implements it's operations.
> + */
> +void __clk_init(struct device *dev, struct clk *clk)
> +{
> +	int i;
> +	struct clk *orphan;
> +	struct hlist_node *tmp, *tmp2;
> +
> +	if (!clk)
> +		return;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	/* check to see if a clock with this name is already registered */
> +	if (__clk_lookup(clk->name))
> +		goto out;
> +
> +	/* throw a WARN if any entries in parent_names are NULL */
> +	for (i = 0; i<  clk->num_parents; i++)
> +		WARN(!clk->parent_names[i],
> +				"%s: invalid NULL in %s's .parent_names\n",
> +				__func__, clk->name);
> +
> +	/*
> +	 * Allocate an array of struct clk *'s to avoid unnecessary string
> +	 * look-ups of clk's possible parents.  This can fail for clocks passed
> +	 * in to clk_init during early boot; thus any access to clk->parents[]
> +	 * must always check for a NULL pointer and try to populate it if
> +	 * necessary.
> +	 *
> +	 * If clk->parents is not NULL we skip this entire block.  This allows
> +	 * for clock drivers to statically initialize clk->parents.
> +	 */
> +	if (clk->num_parents&&  !clk->parents) {
> +		clk->parents = kmalloc((sizeof(struct clk*) * clk->num_parents),
> +				GFP_KERNEL);
> +		/*
> +		 * __clk_lookup returns NULL for parents that have not been
> +		 * clk_init'd; thus any access to clk->parents[] must check
> +		 * for a NULL pointer.  We can always perform lazy lookups for
> +		 * missing parents later on.
> +		 */
> +		if (clk->parents)
> +			for (i = 0; i<  clk->num_parents; i++)
> +				clk->parents[i] =
> +					__clk_lookup(clk->parent_names[i]);
> +	}
> +
> +	clk->parent = __clk_init_parent(clk);
> +
> +	/*
> +	 * Populate clk->parent if parent has already been __clk_init'd.  If
> +	 * parent has not yet been __clk_init'd then place clk in the orphan
> +	 * list.  If clk has set the CLK_IS_ROOT flag then place it in the root
> +	 * clk list.
> +	 *
> +	 * Every time a new clk is clk_init'd then we walk the list of orphan
> +	 * clocks and re-parent any that are children of the clock currently
> +	 * being clk_init'd.
> +	 */
> +	if (clk->parent)
> +		hlist_add_head(&clk->child_node,
> +				&clk->parent->children);
> +	else if (clk->flags&  CLK_IS_ROOT)
> +		hlist_add_head(&clk->child_node,&clk_root_list);
> +	else
> +		hlist_add_head(&clk->child_node,&clk_orphan_list);
> +
> +	/*
> +	 * Set clk's rate.  The preferred method is to use .recalc_rate.  For
> +	 * simple clocks and lazy developers the default fallback is to use the
> +	 * parent's rate.  If a clock doesn't have a parent (or is orphaned)
> +	 * then rate is set to zero.
> +	 */
> +	if (clk->ops->recalc_rate)
> +		clk->rate = clk->ops->recalc_rate(clk->hw,
> +				__clk_get_rate(clk->parent));
> +	else if (clk->parent)
> +		clk->rate = clk->parent->rate;
> +	else
> +		clk->rate = 0;
> +
> +	/*
> +	 * walk the list of orphan clocks and reparent any that are children of
> +	 * this clock
> +	 */
> +	hlist_for_each_entry_safe(orphan, tmp, tmp2,&clk_orphan_list, child_node)
> +		for (i = 0; i<  orphan->num_parents; i++)
> +			if (!strcmp(clk->name, orphan->parent_names[i])) {
> +				__clk_reparent(orphan, clk);
> +				break;
> +			}
> +
> +	/*
> +	 * optional platform-specific magic
> +	 *
> +	 * The .init callback is not used by any of the basic clock types, but
> +	 * exists for weird hardware that must perform initialization magic.
> +	 * Please consider other ways of solving initialization problems before
> +	 * using this callback, as it's use is discouraged.
> +	 */
> +	if (clk->ops->init)
> +		clk->ops->init(clk->hw);
> +
> +	clk_debug_register(clk);
> +
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return;
> +}
> +
> +/**
> + * clk_register - allocate a new clock, register it and return an opaque cookie
> + * @dev: device that is registering this clock
> + * @name: clock name
> + * @ops: operations this clock supports
> + * @hw: link to hardware-specific clock data
> + * @parent_names: array of string names for all possible parents
> + * @num_parents: number of possible parents
> + * @flags: framework-level hints and quirks
> + *
> + * clk_register is the primary interface for populating the clock tree with new
> + * clock nodes.  It returns a pointer to the newly allocated struct clk which
> + * cannot be dereferenced by driver code but may be used in conjuction with the
> + * rest of the clock API.
> + */
> +struct clk *clk_register(struct device *dev, const char *name,
> +		const struct clk_ops *ops, struct clk_hw *hw,
> +		char **parent_names, u8 num_parents, unsigned long flags)
> +{
> +	struct clk *clk;
> +
> +	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
> +	if (!clk)
> +		return NULL;
> +
> +	clk->name = name;
> +	clk->ops = ops;
> +	clk->hw = hw;
> +	clk->flags = flags;
> +	clk->parent_names = parent_names;
> +	clk->num_parents = num_parents;
> +	hw->clk = clk;
> +
> +	__clk_init(dev, clk);
> +
> +	return clk;
> +}
> +EXPORT_SYMBOL_GPL(clk_register);
> +
> +/***        clk rate change notifiers        ***/
> +
> +/**
> + * clk_notifier_register - add a clk rate change notifier
> + * @clk: struct clk * to watch
> + * @nb: struct notifier_block * with callback info
> + *
> + * Request notification when clk's rate changes.  This uses an SRCU
> + * notifier because we want it to block and notifier unregistrations are
> + * uncommon.  The callbacks associated with the notifier must not
> + * re-enter into the clk framework by calling any top-level clk APIs;
> + * this will cause a nested prepare_lock mutex.
> + *
> + * Pre-change notifier callbacks will be passed the current, pre-change
> + * rate of the clk via struct clk_notifier_data.old_rate.  The new,
> + * post-change rate of the clk is passed via struct
> + * clk_notifier_data.new_rate.
> + *
> + * Post-change notifiers will pass the now-current, post-change rate of
> + * the clk in both struct clk_notifier_data.old_rate and struct
> + * clk_notifier_data.new_rate.
> + *
> + * Abort-change notifiers are effectively the opposite of pre-change
> + * notifiers: the original pre-change clk rate is passed in via struct
> + * clk_notifier_data.new_rate and the failed post-change rate is passed
> + * in via struct clk_notifier_data.old_rate.
> + *
> + * clk_notifier_register() must be called from non-atomic context.
> + * Returns -EINVAL if called with null arguments, -ENOMEM upon
> + * allocation failure; otherwise, passes along the return value of
> + * srcu_notifier_chain_register().
> + */
> +int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
> +{
> +	struct clk_notifier *cn;
> +	int ret = -ENOMEM;
> +
> +	if (!clk || !nb)
> +		return -EINVAL;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	/* search the list of notifiers for this clk */
> +	list_for_each_entry(cn,&clk_notifier_list, node)
> +		if (cn->clk == clk)
> +			break;
> +
> +	/* if clk wasn't in the notifier list, allocate new clk_notifier */
> +	if (cn->clk != clk) {
> +		cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
> +		if (!cn)
> +			goto out;
> +
> +		cn->clk = clk;
> +		srcu_init_notifier_head(&cn->notifier_head);
> +
> +		list_add(&cn->node,&clk_notifier_list);
> +	}
> +
> +	ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
> +
> +	clk->notifier_count++;
> +
> +out:
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_notifier_register);
> +
> +/**
> + * clk_notifier_unregister - remove a clk rate change notifier
> + * @clk: struct clk *
> + * @nb: struct notifier_block * with callback info
> + *
> + * Request no further notification for changes to 'clk' and frees memory
> + * allocated in clk_notifier_register.
> + *
> + * Returns -EINVAL if called with null arguments; otherwise, passes
> + * along the return value of srcu_notifier_chain_unregister().
> + */
> +int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
> +{
> +	struct clk_notifier *cn = NULL;
> +	int ret = -EINVAL;
> +
> +	if (!clk || !nb)
> +		return -EINVAL;
> +
> +	mutex_lock(&prepare_lock);
> +
> +	list_for_each_entry(cn,&clk_notifier_list, node)
> +		if (cn->clk == clk)
> +			break;
> +
> +	if (cn->clk == clk) {
> +		ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
> +
> +		clk->notifier_count--;
> +
> +		/* XXX the notifier code should handle this better */
> +		if (!cn->notifier_head.head) {
> +			srcu_cleanup_notifier_head(&cn->notifier_head);
> +			kfree(cn);
> +		}
> +
> +	} else {
> +		ret = -ENOENT;
> +	}
> +
> +	mutex_unlock(&prepare_lock);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(clk_notifier_unregister);
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> new file mode 100644
> index 0000000..e2cce6f
> --- /dev/null
> +++ b/include/linux/clk-private.h
> @@ -0,0 +1,72 @@
> +/*
> + *  linux/include/linux/clk-private.h
> + *
> + *  Copyright (c) 2010-2011 Jeremy Kerr<jeremy.kerr at canonical.com>
> + *  Copyright (C) 2011-2012 Linaro Ltd<mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef __LINUX_CLK_PRIVATE_H
> +#define __LINUX_CLK_PRIVATE_H
> +
> +#include<linux/clk-provider.h>
> +#include<linux/list.h>
> +
> +/*
> + * WARNING: Do not include clk-private.h from any file that implements struct
> + * clk_ops.  Doing so is a layering violation!
> + *
> + * This header exists only to allow for statically initialized clock data.  Any
> + * static clock data must be defined in a separate file from the logic that
> + * implements the clock operations for that same data.
> + */
> +
> +#ifdef CONFIG_COMMON_CLK
> +
> +struct clk {
> +	const char		*name;
> +	const struct clk_ops	*ops;
> +	struct clk_hw		*hw;
> +	struct clk		*parent;
> +	char			**parent_names;
> +	struct clk		**parents;
> +	u8			num_parents;
> +	unsigned long		rate;
> +	unsigned long		new_rate;
> +	unsigned long		flags;
> +	unsigned int		enable_count;
> +	unsigned int		prepare_count;
> +	struct hlist_head	children;
> +	struct hlist_node	child_node;
> +	unsigned int		notifier_count;
> +#ifdef CONFIG_COMMON_CLK_DEBUG
> +	struct dentry		*dentry;
> +#endif
> +};
> +
> +/**
> + * __clk_init - initialize the data structures in a struct clk
> + * @dev:	device initializing this clk, placeholder for now
> + * @clk:	clk being initialized
> + *
> + * Initializes the lists in struct clk, queries the hardware for the
> + * parent and rate and sets them both.
> + *
> + * Any struct clk passed into __clk_init must have the following members
> + * populated:
> + * 	.name
> + * 	.ops
> + * 	.hw
> + * 	.parent_names
> + * 	.num_parents
> + * 	.flags
> + *
> + * It is not necessary to call clk_register if __clk_init is used directly with
> + * statically initialized clock data.
> + */
> +void __clk_init(struct device *dev, struct clk *clk);
> +
> +#endif /* CONFIG_COMMON_CLK */
> +#endif /* CLK_PRIVATE_H */
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> new file mode 100644
> index 0000000..b18b0e7
> --- /dev/null
> +++ b/include/linux/clk-provider.h
> @@ -0,0 +1,173 @@
> +/*
> + *  linux/include/linux/clk-provider.h
> + *
> + *  Copyright (c) 2010-2011 Jeremy Kerr<jeremy.kerr at canonical.com>
> + *  Copyright (C) 2011-2012 Linaro Ltd<mturquette at linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#ifndef __LINUX_CLK_PROVIDER_H
> +#define __LINUX_CLK_PROVIDER_H
> +
> +#include<linux/clk.h>
> +
> +#ifdef CONFIG_COMMON_CLK
> +
> +/**
> + * struct clk_hw - handle for traversing from a struct clk to its corresponding
> + * hardware-specific structure.  struct clk_hw should be declared within struct
> + * clk_foo and then referenced by the struct clk instance that uses struct
> + * clk_foo's clk_ops
> + *
> + * clk: pointer to the struct clk instance that points back to this struct
> + * clk_hw instance
> + */
> +struct clk_hw {
> +	struct clk *clk;
> +};
> +
> +/*
> + * flags used across common struct clk.  these flags should only affect the
> + * top-level framework.  custom flags for dealing with hardware specifics
> + * belong in struct clk_foo
> + */
> +#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
> +#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
> +#define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
> +#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
> +#define CLK_IS_ROOT		BIT(4) /* root clk, has no parent */
> +
> +/**
> + * struct clk_ops -  Callback operations for hardware clocks; these are to
> + * be provided by the clock implementation, and will be called by drivers
> + * through the clk_* api.
> + *
> + * @prepare:	Prepare the clock for enabling. This must not return until
> + * 		the clock is fully prepared, and it's safe to call clk_enable.
> + * 		This callback is intended to allow clock implementations to
> + * 		do any initialisation that may sleep. Called with
> + * 		prepare_lock held.
> + *
> + * @unprepare:	Release the clock from its prepared state. This will typically
> + * 		undo any work done in the @prepare callback. Called with
> + * 		prepare_lock held.
> + *
> + * @enable:	Enable the clock atomically. This must not return until the
> + * 		clock is generating a valid clock signal, usable by consumer
> + * 		devices. Called with enable_lock held. This function must not
> + * 		sleep.
> + *
> + * @disable:	Disable the clock atomically. Called with enable_lock held.
> + * 		This function must not sleep.
> + *
> + * @recalc_rate	Recalculate the rate of this clock, by quering hardware.  The
> + * 		parent rate is an input parameter.  It is up to the caller to
> + * 		insure that the prepare_mutex is held across this call.
> + * 		Returns the calculated rate.  Optional, but recommended - if
> + * 		this op is not set then clock rate will be initialized to 0.
> + *
> + * @round_rate:	Given a target rate as input, returns the closest rate actually
> + * 		supported by the clock.
> + *
> + * @get_parent:	Queries the hardware to determine the parent of a clock.  The
> + * 		return value is a u8 which specifies the index corresponding to
> + * 		the parent clock.  This index can be applied to either the
> + * 		.parent_names or .parents arrays.  In short, this function
> + * 		translates the parent value read from hardware into an array
> + * 		index.  Currently only called when the clock is initialized by
> + * 		__clk_init.  This callback is mandatory for clocks with
> + * 		multiple parents.  It is optional (and unnecessary) for clocks
> + * 		with 0 or 1 parents.
> + *
> + * @set_parent:	Change the input source of this clock; for clocks with multiple
> + * 		possible parents specify a new parent by passing in the index
> + * 		as a u8 corresponding to the parent in either the .parent_names
> + * 		or .parents arrays.  This function in affect translates an
> + * 		array index into the value programmed into the hardware.
> + * 		Returns 0 on success, -EERROR otherwise.
> + *
> + * @set_rate:	Change the rate of this clock. If this callback returns
> + * 		CLK_SET_RATE_PARENT, the rate change will be propagated to the
> + * 		parent clock (which may propagate again if the parent clock
> + * 		also sets this flag). The requested rate of the parent is
> + * 		passed back from the callback in the second 'unsigned long *'
> + * 		argument.  Note that it is up to the hardware clock's set_rate
> + * 		implementation to insure that clocks do not run out of spec
> + * 		when propgating the call to set_rate up to the parent.  One way
> + * 		to do this is to gate the clock (via clk_disable and/or
> + * 		clk_unprepare) before calling clk_set_rate, then ungating it
> + * 		afterward.  If your clock also has the CLK_GATE_SET_RATE flag
> + * 		set then this will insure safety.  Returns 0 on success,
> + * 		-EERROR otherwise.
> + *
> + * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
> + * implementations to split any work between atomic (enable) and sleepable
> + * (prepare) contexts.  If enabling a clock requires code that might sleep,
> + * this must be done in clk_prepare.  Clock enable code that will never be
> + * called in a sleepable context may be implement in clk_enable.
> + *
> + * Typically, drivers will call clk_prepare when a clock may be needed later
> + * (eg. when a device is opened), and clk_enable when the clock is actually
> + * required (eg. from an interrupt). Note that clk_prepare MUST have been
> + * called before clk_enable.
> + */
> +struct clk_ops {
> +	int		(*prepare)(struct clk_hw *hw);
> +	void		(*unprepare)(struct clk_hw *hw);
> +	int		(*enable)(struct clk_hw *hw);
> +	void		(*disable)(struct clk_hw *hw);
> +	int		(*is_enabled)(struct clk_hw *hw);
> +	unsigned long	(*recalc_rate)(struct clk_hw *hw,
> +					unsigned long parent_rate);
> +	long		(*round_rate)(struct clk_hw *hw, unsigned long,
> +					unsigned long *);
> +	int		(*set_parent)(struct clk_hw *hw, u8 index);
> +	u8		(*get_parent)(struct clk_hw *hw);
> +	int		(*set_rate)(struct clk_hw *hw, unsigned long);
> +	void		(*init)(struct clk_hw *hw);
> +};
> +
> +
> +/**
> + * clk_register - allocate a new clock, register it and return an opaque cookie
> + * @dev: device that is registering this clock
> + * @name: clock name
> + * @ops: operations this clock supports
> + * @hw: link to hardware-specific clock data
> + * @parent_names: array of string names for all possible parents
> + * @num_parents: number of possible parents
> + * @flags: framework-level hints and quirks
> + *
> + * clk_register is the primary interface for populating the clock tree with new
> + * clock nodes.  It returns a pointer to the newly allocated struct clk which
> + * cannot be dereferenced by driver code but may be used in conjuction with the
> + * rest of the clock API.
> + */
> +struct clk *clk_register(struct device *dev, const char *name,
> +		const struct clk_ops *ops, struct clk_hw *hw,
> +		char **parent_names, u8 num_parents, unsigned long flags);
> +
> +/* helper functions */
> +const char *__clk_get_name(struct clk *clk);
> +struct clk_hw *__clk_get_hw(struct clk *clk);
> +u8 __clk_get_num_parents(struct clk *clk);
> +struct clk *__clk_get_parent(struct clk *clk);
> +inline int __clk_get_enable_count(struct clk *clk);
> +inline int __clk_get_prepare_count(struct clk *clk);
> +unsigned long __clk_get_rate(struct clk *clk);
> +unsigned long __clk_get_flags(struct clk *clk);
> +int __clk_is_enabled(struct clk *clk);
> +struct clk *__clk_lookup(const char *name);
> +
> +/*
> + * FIXME clock api without lock protection
> + */
> +int __clk_prepare(struct clk *clk);
> +void __clk_unprepare(struct clk *clk);
> +void __clk_reparent(struct clk *clk, struct clk *new_parent);
> +unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
> +
> +#endif /* CONFIG_COMMON_CLK */
> +#endif /* CLK_PROVIDER_H */
> diff --git a/include/linux/clk.h b/include/linux/clk.h
> index b9d46fa..b025272 100644
> --- a/include/linux/clk.h
> +++ b/include/linux/clk.h
> @@ -3,6 +3,7 @@
>    *
>    *  Copyright (C) 2004 ARM Limited.
>    *  Written by Deep Blue Solutions Limited.
> + *  Copyright (C) 2011-2012 Linaro Ltd<mturquette at linaro.org>
>    *
>    * This program is free software; you can redistribute it and/or modify
>    * it under the terms of the GNU General Public License version 2 as
> @@ -12,18 +13,75 @@
>   #define __LINUX_CLK_H
>
>   #include<linux/kernel.h>
> +#include<linux/notifier.h>
>
>   struct device;
>
> -/*
> - * The base API.
> +struct clk;
> +
> +#ifdef CONFIG_COMMON_CLK
> +
> +/**
> + * DOC: clk notifier callback types
> + *
> + * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
> + *     to indicate that the rate change will proceed.  Drivers must
> + *     immediately terminate any operations that will be affected by the
> + *     rate change.  Callbacks may either return NOTIFY_DONE or
> + *     NOTIFY_STOP.
> + *
> + * ABORT_RATE_CHANGE: called if the rate change failed for some reason
> + *     after PRE_RATE_CHANGE.  In this case, all registered notifiers on
> + *     the clk will be called with ABORT_RATE_CHANGE. Callbacks must
> + *     always return NOTIFY_DONE.
> + *
> + * POST_RATE_CHANGE - called after the clk rate change has successfully
> + *     completed.  Callbacks must always return NOTIFY_DONE.
> + *
>    */
> +#define PRE_RATE_CHANGE			BIT(0)
> +#define POST_RATE_CHANGE		BIT(1)
> +#define ABORT_RATE_CHANGE		BIT(2)
>
> +/**
> + * struct clk_notifier - associate a clk with a notifier
> + * @clk: struct clk * to associate the notifier with
> + * @notifier_head: a blocking_notifier_head for this clk
> + * @node: linked list pointers
> + *
> + * A list of struct clk_notifier is maintained by the notifier code.
> + * An entry is created whenever code registers the first notifier on a
> + * particular @clk.  Future notifiers on that @clk are added to the
> + * @notifier_head.
> + */
> +struct clk_notifier {
> +	struct clk			*clk;
> +	struct srcu_notifier_head	notifier_head;
> +	struct list_head		node;
> +};
>
> -/*
> - * struct clk - an machine class defined object / cookie.
> +/**
> + * struct clk_notifier_data - rate data to pass to the notifier callback
> + * @clk: struct clk * being changed
> + * @old_rate: previous rate of this clk
> + * @new_rate: new rate of this clk
> + *
> + * For a pre-notifier, old_rate is the clk's rate before this rate
> + * change, and new_rate is what the rate will be in the future.  For a
> + * post-notifier, old_rate and new_rate are both set to the clk's
> + * current rate (this was done to optimize the implementation).
>    */
> -struct clk;
> +struct clk_notifier_data {
> +	struct clk		*clk;
> +	unsigned long		old_rate;
> +	unsigned long		new_rate;
> +};
> +
> +int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
> +
> +int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
> +
> +#endif /* !CONFIG_COMMON_CLK */
>
>   /**
>    * clk_get - lookup and obtain a reference to a clock producer.



From s.hauer at pengutronix.de  Mon Mar 19 07:22:52 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 12:22:52 +0100
Subject: [PATCH v5 3/4] clk: introduce the common clock framework
In-Reply-To: <20120319070115.GC31410@S2101-09.ap.freescale.net>
References: <CAJOA=zP8d8wm==7=svOzh03Ft-1_LV71q0mA6Pncrh5vQSWGEA@mail.gmail.com>
 <20120305073836.GU3852@pengutronix.de>
 <CAJOA=zMs75ZQ24g5PXpSLV3AJzWEo12g86G8+4+ryQR_cTYpzA@mail.gmail.com>
 <20120306190039.GJ3852@pengutronix.de>
 <CAJOA=zOG_6eSWPEfFL6VKWeTpGKD9y11xeHoOwdS3b59tAZ45A@mail.gmail.com>
 <20120308062739.GE18513@lunn.ch>
 <20120308232549.GU3852@pengutronix.de>
 <20120309075720.GC16608@lunn.ch>
 <CAJOA=zPztBfTY_WDwZ5iFEa94eCtHyrzN422RTACMQXs625gRA@mail.gmail.com>
 <20120319070115.GC31410@S2101-09.ap.freescale.net>
Message-ID: <20120319112252.GW3852@pengutronix.de>

On Mon, Mar 19, 2012 at 03:01:17PM +0800, Shawn Guo wrote:
> On Fri, Mar 09, 2012 at 10:25:00AM -0800, Turquette, Mike wrote:
> ...
> > However if you have the ability to use the clk_foo_register functions
> > please do use them in place of static initialization.  The static init
> > stuff is only for folks backed into a corner and forced to use it...
> > for now.  I'm looking at ways to allow for kmalloc'ing in early boot,
> > as well as reducing the number of clocks that my platform registers
> > during early boot drastically.
> > 
> While I agree using registration functions rather than static
> initialization will help make "struct clk" an opaque cookie, I also
> see some benefit with using static initialization over registration
> functions.  That is we will be able to initialize parents statically
> rather than calling expensive __clk_lookup() to find them when using
> registration functions.
> 
> I'm not sure if this will be a concern with the platforms that have
> hundreds of clocks.  Keep it in mind, when we say one clock, there
> are generally 3 clks behind it, clk_gate, clk_divider and clk_mux.

On an i.MX51 with a fully dynamically allocated clock tree it takes
about 10ms to initialize the tree which I think is acceptable. The
clock tree is not complete, but I would think that about 70% of the
clocks are there.
Normally less performant platforms will have less clocks, so I assume
the times will be comparable.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Mar 19 07:28:58 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 12:28:58 +0100
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <4F6716DD.5090900@ti.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <4F6716DD.5090900@ti.com>
Message-ID: <20120319112858.GX3852@pengutronix.de>

On Mon, Mar 19, 2012 at 04:52:05PM +0530, Rajendra Nayak wrote:
> Hi Mike,
> 
> >+/*
> >+ * calculate the new rates returning the topmost clock that has to be
> >+ * changed.
> >+ */
> >+static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
> >+{
> >+	struct clk *top = clk;
> >+	unsigned long best_parent_rate = clk->parent->rate;
> 
> Shouldn't you check for a valid parent before dereferencing it? A
> clk_set_rate() on a root clock might throw up some issues otherwise.
>

Yes, should be checked.

> >+	unsigned long new_rate;
> >+
> >+	if (!clk->ops->round_rate&&  !(clk->flags&  CLK_SET_RATE_PARENT)) {
> >+		clk->new_rate = clk->rate;
> >+		return NULL;
> 
> So does this mean a clk_set_rate() fails for a clk which does not have
> a valid .round_rate and does not have a CLK_SET_RATE_PARENT flag set?
> I was thinking this could do a..
> 		clk->new_rate = rate;
> 		top = clk;
> 		goto out;
> ..instead.

The core should make sure that either both set_rate and round_rate are
present or none of them.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From tom.leiming at gmail.com  Mon Mar 19 07:44:30 2012
From: tom.leiming at gmail.com (Ming Lei)
Date: Mon, 19 Mar 2012 19:44:30 +0800
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
Message-ID: <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>

On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>
> I think you made very good point here. With the above patch, we are almost missing the capability of registering dmtimer as a clocksource for OMAP.
> It will always use 32k-counter, and never fall back to dmtimer.
>
> Then the only options we have here is,
>
> 1) Register both the timers, 32k-counter and dmtimer for clocksource; let
> ? Kernel pick up best rating clocksource out of these two.
>
> ? In case of OMAP1/2/3/4, kernel will use dmtimer, since it has better
> ? Rating. User can choose the 32k-counter clocksource via bootargs.
>
> ? Impact: without bootargs for clocksource selection, kernel will choose
> ? ? dmtimer, impacting loss of time during suspend/resume.
>
>
> 2) Let the current code be as is, means, the clocksource registration will
> ? Happened based on "#ifdef CONFIG_OMAP_32K_TIMER" and this option
> ? selection will be Controlled by Kconfig rules.

How about the 3rd option?

3), take the way in your patch 1) at default, but will switch to
register dmtimer
directly and bypass 32k-counter if user need it via kernel parameter.

As far as I can think of, the situations required for dmtimer are high-frequency
perf sample and high precision trace points, so looks it is OK to take
32k-counter
at default.

Thanks,
-- 
Ming Lei


From tarun.kanti at ti.com  Mon Mar 19 08:06:56 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Mon, 19 Mar 2012 17:36:56 +0530
Subject: [PATCH v2 3/4] drivers: input: Fix OMAP_GPIO_IRQ with gpio_to_irq()
 in ams_delta_serio_exit()
In-Reply-To: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1332158817-26311-4-git-send-email-tarun.kanti@ti.com>

Even though ams-delta-serio input driver uses gpio_to_irq() in all
relevent places to get irq number, the ams_delta_serio_exit() still
uses OMAP_GPIO_IRQ macro. Fix this.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 drivers/input/serio/ams_delta_serio.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/input/serio/ams_delta_serio.c b/drivers/input/serio/ams_delta_serio.c
index d4d08bd..dbe1ae8 100644
--- a/drivers/input/serio/ams_delta_serio.c
+++ b/drivers/input/serio/ams_delta_serio.c
@@ -170,7 +170,7 @@ module_init(ams_delta_serio_init);
 static void __exit ams_delta_serio_exit(void)
 {
 	serio_unregister_port(ams_delta_serio);
-	free_irq(OMAP_GPIO_IRQ(AMS_DELTA_GPIO_PIN_KEYBRD_CLK), 0);
+	free_irq(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK), 0);
 	gpio_free(AMS_DELTA_GPIO_PIN_KEYBRD_CLK);
 	gpio_free(AMS_DELTA_GPIO_PIN_KEYBRD_DATA);
 }
-- 
1.7.0.4



From tarun.kanti at ti.com  Mon Mar 19 08:06:53 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Mon, 19 Mar 2012 17:36:53 +0530
Subject: [PATCH v2 0/4] ARM: OMAP: boards: changes to support dynamic irq alloc
Message-ID: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>

These two patches incorporate changes to OMAP1 and OMAP2 platforms
board files whereby older references to OMAP_GPIO_IRQ macro are
now replaced with gpio_to_irq(), thereby getting rid of static
irq references.

Reference: git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git omap/dt
Commit: 9a0cee711448335ec43eae83272495e9334c0098

Test info:
OMAP1 Platforms:
Boot test on OMAP1710 H3.

OMAP2PLUS Platforms:
OMAP2430SDP, OMAP3430SDP, OMAP3630-ZOOM3, OMAP4430-SDP,
OMAP4430-PANDA, OMAP4430-BLAZE

I have also done gpio functional testing after merging Grant's:
git://git.secretlab.ca/git/linux-2.6.git gpio/next
on top of these patches.

Again, I would request someone help me testing on other platforms.

v2:
- Modified the patch subjects as per convention.
- Added a new patch to remove OMAP_GPIO_IRQ from ams_delta_serio driver.
- Added a new patch to remove OMAP_GPIO_IRQ macro definition.

Tarun Kanti DebBarma (4):
  ARM: OMAP1: boards: Fix OMAP_GPIO_IRQ usage with gpio_to_irq()
  ARM: OMAP2+: boards: Fix OMAP_GPIO_IRQ usage with gpio_to_irq()
  drivers: input: Fix OMAP_GPIO_IRQ with gpio_to_irq() in
    ams_delta_serio_exit()
  ARM: OMAP: Remove OMAP_GPIO_IRQ macro definition

 arch/arm/mach-omap1/board-h2.c               |    8 ++++----
 arch/arm/mach-omap1/board-h3.c               |    9 ++++-----
 arch/arm/mach-omap1/board-htcherald.c        |    6 +++---
 arch/arm/mach-omap1/board-innovator.c        |    4 ++--
 arch/arm/mach-omap1/board-nokia770.c         |    2 +-
 arch/arm/mach-omap1/board-osk.c              |   12 ++++++------
 arch/arm/mach-omap1/board-palmte.c           |    2 +-
 arch/arm/mach-omap1/board-palmtt.c           |    2 +-
 arch/arm/mach-omap1/board-palmz71.c          |    2 +-
 arch/arm/mach-omap1/board-voiceblue.c        |   16 +++++++---------
 arch/arm/mach-omap2/board-2430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-4430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-apollon.c          |    6 ++++--
 arch/arm/mach-omap2/board-devkit8000.c       |    3 ++-
 arch/arm/mach-omap2/board-h4.c               |    2 +-
 arch/arm/mach-omap2/board-omap3evm.c         |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c       |    2 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c |    3 ++-
 arch/arm/mach-omap2/board-zoom-debugboard.c  |    3 ++-
 arch/arm/mach-omap2/board-zoom-peripherals.c |    6 ++++--
 arch/arm/mach-omap2/common-board-devices.c   |    2 +-
 arch/arm/plat-omap/include/plat/gpio.h       |    4 ----
 drivers/input/serio/ams_delta_serio.c        |    2 +-
 23 files changed, 51 insertions(+), 51 deletions(-)



From tarun.kanti at ti.com  Mon Mar 19 08:06:57 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Mon, 19 Mar 2012 17:36:57 +0530
Subject: [PATCH v2 4/4] ARM: OMAP: Remove OMAP_GPIO_IRQ macro definition
In-Reply-To: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1332158817-26311-5-git-send-email-tarun.kanti@ti.com>

Since all references to OMAP_GPIO_IRQ macro are replaced now
with gpio_to_irq(), this can be removed altogether.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 arch/arm/plat-omap/include/plat/gpio.h |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 9e86ee0..d4df414 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -158,10 +158,6 @@
 #define OMAP_MPUIO(nr)		(OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr)	((nr) >= OMAP_MAX_GPIO_LINES)
 
-#define OMAP_GPIO_IRQ(nr)	(OMAP_GPIO_IS_MPUIO(nr) ? \
-				 IH_MPUIO_BASE + ((nr) & 0x0f) : \
-				 IH_GPIO_BASE + (nr))
-
 #define METHOD_MPUIO		0
 #define METHOD_GPIO_1510	1
 #define METHOD_GPIO_1610	2
-- 
1.7.0.4



From tarun.kanti at ti.com  Mon Mar 19 08:06:55 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Mon, 19 Mar 2012 17:36:55 +0530
Subject: [PATCH v2 2/4] ARM: OMAP2+: boards: Fix OMAP_GPIO_IRQ usage with
 gpio_to_irq()
In-Reply-To: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1332158817-26311-3-git-send-email-tarun.kanti@ti.com>

With dynamic allocation of IRQ the usage of OMAP_GPIO_IRQ
is no longer valid. We should be using gpio_to_irq() instead.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 arch/arm/mach-omap2/board-2430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-4430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-apollon.c          |    6 ++++--
 arch/arm/mach-omap2/board-devkit8000.c       |    3 ++-
 arch/arm/mach-omap2/board-h4.c               |    2 +-
 arch/arm/mach-omap2/board-omap3evm.c         |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c       |    2 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c |    3 ++-
 arch/arm/mach-omap2/board-zoom-debugboard.c  |    3 ++-
 arch/arm/mach-omap2/board-zoom-peripherals.c |    6 ++++--
 arch/arm/mach-omap2/common-board-devices.c   |    2 +-
 11 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 7370983..5a1b6af 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -230,12 +230,12 @@ static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = {
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2D),
 		.flags = I2C_CLIENT_WAKE,
-		.irq = OMAP_GPIO_IRQ(78),
 	},
 };
 
 static int __init omap2430_i2c_init(void)
 {
+	sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
 	omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
 			ARRAY_SIZE(sdp2430_i2c1_boardinfo));
 	omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 4e90715..a09c699 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -873,7 +873,6 @@ static void __init omap4_sdp4430_wifi_mux_init(void)
 }
 
 static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
 	.board_ref_clock = WL12XX_REFCLOCK_26,
 	.board_tcxo_clock = WL12XX_TCXOCLOCK_26,
 };
@@ -883,6 +882,7 @@ static void __init omap4_sdp4430_wifi_init(void)
 	int ret;
 
 	omap4_sdp4430_wifi_mux_init();
+	omap4_sdp4430_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
 	ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
 	if (ret)
 		pr_err("Error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index ac77382..7dd9d4d 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -136,8 +136,6 @@ static struct resource apollon_smc91x_resources[] = {
 		.flags  = IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
-		.end	= OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -341,6 +339,10 @@ static void __init omap_apollon_init(void)
 	 * You have to mux them off in device drivers later on
 	 * if not needed.
 	 */
+	apollon_devices[1]->resource[1].start =
+					gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
+	apollon_devices[1]->resource[1].end =
+					gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
 	platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index e873063..e947dc7 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -410,7 +410,6 @@ static struct resource omap_dm9000_resources[] = {
 		.flags		= IORESOURCE_MEM,
 	},
 	[2] = {
-		.start		= OMAP_GPIO_IRQ(OMAP_DM9000_GPIO_IRQ),
 		.flags		= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
 	},
 };
@@ -637,6 +636,8 @@ static void __init devkit8000_init(void)
 	omap_dm9000_init();
 
 	devkit8000_i2c_init();
+	devkit8000_devices[2]->resource[2].start =
+					gpio_to_irq(OMAP_DM9000_GPIO_IRQ);
 	platform_add_devices(devkit8000_devices,
 			ARRAY_SIZE(devkit8000_devices));
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 54af800..0bbbabe 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -348,7 +348,6 @@ static struct at24_platform_data m24c01 = {
 static struct i2c_board_info __initdata h4_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(125),
 	},
 	{	/* EEPROM on mainboard */
 		I2C_BOARD_INFO("24c01", 0x52),
@@ -377,6 +376,7 @@ static void __init omap_h4_init(void)
 	 */
 
 	board_mkp_init();
+	h4_i2c_board_info[0].irq = gpio_to_irq(125);
 	i2c_register_board_info(1, h4_i2c_board_info,
 			ARRAY_SIZE(h4_i2c_board_info));
 
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c877236..eed88a4 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -487,7 +487,6 @@ static struct platform_device omap3evm_wlan_regulator = {
 };
 
 struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
 	.board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
 };
 #endif
@@ -623,6 +622,7 @@ static void __init omap3_evm_wl12xx_init(void)
 	int ret;
 
 	/* WL12xx WLAN Init */
+	omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
 	ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 28fc271..4496007 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -199,7 +199,6 @@ static struct platform_device omap_vwlan_device = {
 };
 
 struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
-	.irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
 	/* PANDA ref clock is 38.4 MHz */
 	.board_ref_clock = 2,
 };
@@ -494,6 +493,7 @@ static void __init omap4_panda_init(void)
 		package = OMAP_PACKAGE_CBL;
 	omap4_mux_init(board_mux, NULL, package);
 
+	omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
 	ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index acb4e77..1cec076 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -172,7 +172,6 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
 		.modalias		= "tsc2005",
 		.bus_num		= 1,
 		.chip_select		= 0,
-		.irq			= OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
 		.max_speed_hz		= 6000000,
 		.controller_data	= &tsc2005_mcspi_config,
 		.platform_data		= &tsc2005_pdata,
@@ -1124,6 +1123,8 @@ static void __init rx51_init_tsc2005(void)
 		"tsc2005 reset");
 	if (r >= 0) {
 		tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
+		rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq =
+					gpio_to_irq(RX51_TSC2005_IRQ_GPIO);
 	} else {
 		printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
 		tsc2005_pdata.esd_timeout_ms = 0;
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 369c2eb..1e8540e 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -43,7 +43,6 @@ static inline void __init zoom_init_smsc911x(void)
 static struct plat_serial8250_port serial_platform_data[] = {
 	{
 		.mapbase	= ZOOM_UART_BASE,
-		.irq		= OMAP_GPIO_IRQ(102),
 		.flags		= UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ,
 		.irqflags	= IRQF_SHARED | IRQF_TRIGGER_RISING,
 		.iotype		= UPIO_MEM,
@@ -89,6 +88,8 @@ static inline void __init zoom_init_quaduart(void)
 	if (gpio_request_one(quart_gpio, GPIOF_IN, "TL16CP754C GPIO") < 0)
 		printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n",
 								quart_gpio);
+
+	serial_platform_data[0].irq = gpio_to_irq(102);
 }
 
 static inline int omap_zoom_debugboard_detect(void)
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index c126461..a489f82 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -193,7 +193,6 @@ static struct platform_device omap_vwlan_device = {
 };
 
 static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO),
 	/* ZOOM ref clock is 26 MHz */
 	.board_ref_clock = 1,
 };
@@ -296,7 +295,10 @@ static void enable_board_wakeup_source(void)
 
 void __init zoom_peripherals_init(void)
 {
-	int ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
+	int ret;
+
+	omap_zoom_wlan_data.irq = gpio_to_irq(OMAP_ZOOM_WLAN_IRQ_GPIO);
+	ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
 
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index bcb0c58..4cb17b4 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -79,7 +79,7 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 	ads7846_config.gpio_pendown = gpio_pendown;
 
 	spi_bi->bus_num	= bus_num;
-	spi_bi->irq	= OMAP_GPIO_IRQ(gpio_pendown);
+	spi_bi->irq	= gpio_to_irq(gpio_pendown);
 
 	if (board_pdata)
 		spi_bi->platform_data = board_pdata;
-- 
1.7.0.4



From tarun.kanti at ti.com  Mon Mar 19 08:06:54 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Mon, 19 Mar 2012 17:36:54 +0530
Subject: [PATCH v2 1/4] ARM: OMAP1: boards: Fix OMAP_GPIO_IRQ usage with
 gpio_to_irq()
In-Reply-To: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1332158817-26311-2-git-send-email-tarun.kanti@ti.com>

With dynamic allocation of IRQ the usage of OMAP_GPIO_IRQ
is no longer valid. We should be using gpio_to_irq() instead.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 arch/arm/mach-omap1/board-h2.c        |    8 ++++----
 arch/arm/mach-omap1/board-h3.c        |    9 ++++-----
 arch/arm/mach-omap1/board-htcherald.c |    6 +++---
 arch/arm/mach-omap1/board-innovator.c |    4 ++--
 arch/arm/mach-omap1/board-nokia770.c  |    2 +-
 arch/arm/mach-omap1/board-osk.c       |   12 ++++++------
 arch/arm/mach-omap1/board-palmte.c    |    2 +-
 arch/arm/mach-omap1/board-palmtt.c    |    2 +-
 arch/arm/mach-omap1/board-palmz71.c   |    2 +-
 arch/arm/mach-omap1/board-voiceblue.c |   16 +++++++---------
 10 files changed, 30 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 00ad6b2..ad0eece 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -244,8 +244,6 @@ static struct resource h2_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -364,11 +362,9 @@ static struct tps65010_board tps_board = {
 static struct i2c_board_info __initdata h2_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("tps65010", 0x48),
-		.irq            = OMAP_GPIO_IRQ(58),
 		.platform_data	= &tps_board,
 	}, {
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(2),
 	},
 };
 
@@ -437,10 +433,14 @@ static void __init h2_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	h2_devices[2]->resource[1].start = gpio_to_irq(0);
+	h2_devices[2]->resource[1].end = gpio_to_irq(0);
 	platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
 	omap_board_config = h2_config;
 	omap_board_config_size = ARRAY_SIZE(h2_config);
 	omap_serial_init();
+	h2_i2c_board_info[0].irq = gpio_to_irq(58);
+	h2_i2c_board_info[1].irq = gpio_to_irq(2);
 	omap_register_i2c_bus(1, 100, h2_i2c_board_info,
 			      ARRAY_SIZE(h2_i2c_board_info));
 	omap1_usb_init(&h2_usb_config);
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 4a7f251..740ca6c 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -246,8 +246,6 @@ static struct resource smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(40),
-		.end	= OMAP_GPIO_IRQ(40),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -337,7 +335,6 @@ static struct spi_board_info h3_spi_board_info[] __initdata = {
 		.modalias	= "tsc2101",
 		.bus_num	= 2,
 		.chip_select	= 0,
-		.irq		= OMAP_GPIO_IRQ(H3_TS_GPIO),
 		.max_speed_hz	= 16000000,
 		/* .platform_data	= &tsc_platform_data, */
 	},
@@ -377,11 +374,9 @@ static struct omap_board_config_kernel h3_config[] __initdata = {
 static struct i2c_board_info __initdata h3_i2c_board_info[] = {
        {
 		I2C_BOARD_INFO("tps65013", 0x48),
-               /* .irq         = OMAP_GPIO_IRQ(??), */
        },
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(14),
 	},
 };
 
@@ -423,12 +418,16 @@ static void __init h3_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	devices[2]->resource[1].start = gpio_to_irq(40);
+	devices[2]->resource[1].end = gpio_to_irq(40);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
+	h3_spi_board_info[0].irq = gpio_to_irq(H3_TS_GPIO);
 	spi_register_board_info(h3_spi_board_info,
 				ARRAY_SIZE(h3_spi_board_info));
 	omap_board_config = h3_config;
 	omap_board_config_size = ARRAY_SIZE(h3_config);
 	omap_serial_init();
+	h3_i2c_board_info[1].irq = gpio_to_irq(14);
 	omap_register_i2c_bus(1, 100, h3_i2c_board_info,
 			      ARRAY_SIZE(h3_i2c_board_info));
 	omap1_usb_init(&h3_usb_config);
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 731cc3d..766b1e3 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -324,8 +324,6 @@ static struct platform_device gpio_leds_device = {
 
 static struct resource htcpld_resources[] = {
 	[0] = {
-		.start  = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
-		.end    = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
 		.flags  = IORESOURCE_IRQ,
 	},
 };
@@ -454,7 +452,6 @@ static struct spi_board_info __initdata htcherald_spi_board_info[] = {
 	{
 		.modalias		= "ads7846",
 		.platform_data		= &htcherald_ts_platform_data,
-		.irq			= OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS),
 		.max_speed_hz		= 2500000,
 		.bus_num		= 2,
 		.chip_select		= 1,
@@ -582,6 +579,8 @@ static void __init htcherald_init(void)
 	/* Do board initialization before we register all the devices */
 	omap_board_config = htcherald_config;
 	omap_board_config_size = ARRAY_SIZE(htcherald_config);
+	devices[2]->resource[0].start = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
+	devices[2]->resource[0].end = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	htcherald_disable_watchdog();
@@ -589,6 +588,7 @@ static void __init htcherald_init(void)
 	htcherald_usb_enable();
 	omap1_usb_init(&htcherald_usb_config);
 
+	htcherald_spi_board_info[0].irq = gpio_to_irq(HTCHERALD_GPIO_TS);
 	spi_register_board_info(htcherald_spi_board_info,
 		ARRAY_SIZE(htcherald_spi_board_info));
 
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index be2002f..965f3d7 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -244,8 +244,6 @@ static struct resource innovator1610_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -409,6 +407,8 @@ static void __init innovator_init(void)
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
 	if (!cpu_is_omap1510()) {
+		innovator1610_devices[1]->resource[1].start = gpio_to_irq(0);
+		innovator1610_devices[1]->resource[1].end = gpio_to_irq(0);
 		platform_add_devices(innovator1610_devices, ARRAY_SIZE(innovator1610_devices));
 	}
 #endif
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index f9efc03..364e3d7 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -145,7 +145,6 @@ static struct spi_board_info nokia770_spi_board_info[] __initdata = {
 		.bus_num        = 2,
 		.chip_select    = 0,
 		.max_speed_hz   = 2500000,
-		.irq		= OMAP_GPIO_IRQ(15),
 		.platform_data	= &nokia770_ads7846_platform_data,
 	},
 };
@@ -240,6 +239,7 @@ static void __init omap_nokia770_init(void)
 	omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
 
 	platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
+	nokia770_spi_board_info[1].irq = gpio_to_irq(15);
 	spi_register_board_info(nokia770_spi_board_info,
 				ARRAY_SIZE(nokia770_spi_board_info));
 	omap_serial_init();
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 675de06..6791887 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -129,8 +129,6 @@ static struct resource osk5912_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -147,8 +145,6 @@ static struct platform_device osk5912_smc91x_device = {
 
 static struct resource osk5912_cf_resources[] = {
 	[0] = {
-		.start	= OMAP_GPIO_IRQ(62),
-		.end	= OMAP_GPIO_IRQ(62),
 		.flags	= IORESOURCE_IRQ,
 	},
 };
@@ -240,7 +236,6 @@ static struct tps65010_board tps_board = {
 static struct i2c_board_info __initdata osk_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("tps65010", 0x48),
-		.irq		= OMAP_GPIO_IRQ(OMAP_MPUIO(1)),
 		.platform_data	= &tps_board,
 
 	},
@@ -414,7 +409,6 @@ static struct spi_board_info __initdata mistral_boardinfo[] = { {
 	/* MicroWire (bus 2) CS0 has an ads7846e */
 	.modalias		= "ads7846",
 	.platform_data		= &mistral_ts_info,
-	.irq			= OMAP_GPIO_IRQ(4),
 	.max_speed_hz		= 120000 /* max sample rate at 3V */
 					* 26 /* command + data + overhead */,
 	.bus_num		= 2,
@@ -477,6 +471,7 @@ static void __init osk_mistral_init(void)
 	gpio_direction_input(4);
 	irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
 
+	mistral_boardinfo[0].irq = gpio_to_irq(4);
 	spi_register_board_info(mistral_boardinfo,
 			ARRAY_SIZE(mistral_boardinfo));
 
@@ -548,6 +543,10 @@ static void __init osk_init(void)
 
 	osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
 	osk_flash_resource.end += SZ_32M - 1;
+	osk5912_devices[1]->resource[1].start = gpio_to_irq(0);
+	osk5912_devices[1]->resource[1].end = gpio_to_irq(0);
+	osk5912_devices[2]->resource[0].start = gpio_to_irq(62);
+	osk5912_devices[2]->resource[0].end = gpio_to_irq(62);
 	platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
 	omap_board_config = osk_config;
 	omap_board_config_size = ARRAY_SIZE(osk_config);
@@ -564,6 +563,7 @@ static void __init osk_init(void)
 		gpio_direction_input(OMAP_MPUIO(1));
 
 	omap_serial_init();
+	osk_i2c_board_info[0].irq = gpio_to_irq(OMAP_MPUIO(1));
 	omap_register_i2c_bus(1, 400, osk_i2c_board_info,
 			      ARRAY_SIZE(osk_i2c_board_info));
 	osk_mistral_init();
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 81fa27f..108c7d1 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -218,7 +218,6 @@ static struct spi_board_info palmte_spi_info[] __initdata = {
 		.modalias	= "tsc2102",
 		.bus_num	= 2,	/* uWire (officially) */
 		.chip_select	= 0,	/* As opposed to 3 */
-		.irq		= OMAP_GPIO_IRQ(PALMTE_PINTDAV_GPIO),
 		.max_speed_hz	= 8000000,
 	},
 };
@@ -255,6 +254,7 @@ static void __init omap_palmte_init(void)
 
 	platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices));
 
+	palmte_spi_info[0].irq = gpio_to_irq(PALMTE_PINTDAV_GPIO);
 	spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
 	palmte_misc_gpio_setup();
 	omap_serial_init();
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 81cb821..b87a92f 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -255,7 +255,6 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
 		/* MicroWire (bus 2) CS0 has an ads7846e */
 		.modalias	= "ads7846",
 		.platform_data	= &palmtt_ts_info,
-		.irq		= OMAP_GPIO_IRQ(6),
 		.max_speed_hz	= 120000	/* max sample rate at 3V */
 					* 26	/* command + data + overhead */,
 		.bus_num	= 2,
@@ -303,6 +302,7 @@ static void __init omap_palmtt_init(void)
 
 	platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices));
 
+	palmtt_boardinfo[0].irq = gpio_to_irq(6);
 	spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
 	omap_serial_init();
 	omap1_usb_init(&palmtt_usb_config);
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index e881945..0ff25fa 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -222,7 +222,6 @@ static struct spi_board_info __initdata palmz71_boardinfo[] = { {
 	/* MicroWire (bus 2) CS0 has an ads7846e */
 	.modalias	= "ads7846",
 	.platform_data	= &palmz71_ts_info,
-	.irq		= OMAP_GPIO_IRQ(PALMZ71_PENIRQ_GPIO),
 	.max_speed_hz	= 120000	/* max sample rate at 3V */
 				* 26	/* command + data + overhead */,
 	.bus_num	= 2,
@@ -318,6 +317,7 @@ omap_palmz71_init(void)
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
+	palmz71_boardinfo[0].irq = gpio_to_irq(PALMZ71_PENIRQ_GPIO);
 	spi_register_board_info(palmz71_boardinfo,
 				ARRAY_SIZE(palmz71_boardinfo));
 	omap1_usb_init(&palmz71_usb_config);
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index f83a502..63732fe 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -42,7 +42,6 @@
 static struct plat_serial8250_port voiceblue_ports[] = {
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x40000),
-		.irq		= OMAP_GPIO_IRQ(12),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -50,7 +49,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x50000),
-		.irq		= OMAP_GPIO_IRQ(13),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -58,7 +56,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x60000),
-		.irq		= OMAP_GPIO_IRQ(14),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -66,7 +63,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x70000),
-		.irq		= OMAP_GPIO_IRQ(15),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -78,9 +74,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 static struct platform_device serial_device = {
 	.name			= "serial8250",
 	.id			= PLAT8250_DEV_PLATFORM1,
-	.dev			= {
-		.platform_data	= voiceblue_ports,
-	},
 };
 
 static int __init ext_uart_init(void)
@@ -88,6 +81,11 @@ static int __init ext_uart_init(void)
 	if (!machine_is_voiceblue())
 		return -ENODEV;
 
+	voiceblue_ports[0].irq = gpio_to_irq(12);
+	voiceblue_ports[1].irq = gpio_to_irq(13);
+	voiceblue_ports[2].irq = gpio_to_irq(14);
+	voiceblue_ports[3].irq = gpio_to_irq(15);
+	serial_device.dev.platform_data = voiceblue_ports;
 	return platform_device_register(&serial_device);
 }
 arch_initcall(ext_uart_init);
@@ -126,8 +124,6 @@ static struct resource voiceblue_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(8),
-		.end	= OMAP_GPIO_IRQ(8),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -273,6 +269,8 @@ static void __init voiceblue_init(void)
 	irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
 	irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
 
+	voiceblue_devices[1]->resource[1].start = gpio_to_irq(8);
+	voiceblue_devices[1]->resource[1].end = gpio_to_irq(8);
 	platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
 	omap_board_config = voiceblue_config;
 	omap_board_config_size = ARRAY_SIZE(voiceblue_config);
-- 
1.7.0.4



From broonie at opensource.wolfsonmicro.com  Mon Mar 19 08:00:15 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 19 Mar 2012 12:00:15 +0000
Subject: [PATCH v4 2/4] mfd: mc13xxx-core: use regmap for register access
In-Reply-To: <1332129838-7080-3-git-send-email-marc@cpdesign.com.au>
References: <1332129838-7080-1-git-send-email-marc@cpdesign.com.au>
 <1332129838-7080-3-git-send-email-marc@cpdesign.com.au>
Message-ID: <20120319120015.GA5705@sirena.org.uk>

On Mon, Mar 19, 2012 at 03:03:56PM +1100, Marc Reilly wrote:
> This change converts the mc13xxx core to use regmap rather than direct
> spi r/w.
> The spidev member of mc13xxx struct becomes redundant and is removed.
> Extra debugging aids are added to mc13xxx_reg_rmw.
> Mutex init is moved to before regmap init.

Reviewed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

though like I said it'd be good to get the rmw trace into regmap - if
it's useful to you here similar trace is probably going to be useful to
other users.


From santosh.shilimkar at ti.com  Mon Mar 19 08:15:32 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Mon, 19 Mar 2012 17:45:32 +0530
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>	<1326983304-14619-2-git-send-email-hvaibhav@ti.com>	<87mx9ej8fp.fsf@ti.com>	<CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>	<79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
Message-ID: <4F672364.3020403@ti.com>

On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
> On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>>
>> I think you made very good point here. With the above patch, we are almost missing the capability of registering dmtimer as a clocksource for OMAP.
>> It will always use 32k-counter, and never fall back to dmtimer.
>>
>> Then the only options we have here is,
>>
>> 1) Register both the timers, 32k-counter and dmtimer for clocksource; let
>>   Kernel pick up best rating clocksource out of these two.
>>
>>   In case of OMAP1/2/3/4, kernel will use dmtimer, since it has better
>>   Rating. User can choose the 32k-counter clocksource via bootargs.
>>
>>   Impact: without bootargs for clocksource selection, kernel will choose
>>     dmtimer, impacting loss of time during suspend/resume.
>>
This is the right option. The problem is gptimer clocksource
doesn't work across power transitions and hence it is broken.

Even for the perf, with PM enabled, dmtimer can't be used or it needs
to be used with 32KHz clock which makes it no better than sync timer.

So here keeping 32K sync timer is default clocksource makes sense since
it is the only working and viable option.

So what can be done is register both 32K and gptimer together but make
gptimer clocksource registration depends on PM enabled.

This should solve all the needs I guess.

>>
>> 2) Let the current code be as is, means, the clocksource registration will
>>   Happened based on "#ifdef CONFIG_OMAP_32K_TIMER" and this option
>>   selection will be Controlled by Kconfig rules.
> 
We should get rid off CONFIG_OMAP_32K_TIMER.

Regards
Santosh



From santosh.shilimkar at ti.com  Mon Mar 19 08:17:45 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Mon, 19 Mar 2012 17:47:45 +0530
Subject: [PATCH v2 0/4] ARM: OMAP: boards: changes to support dynamic irq
 alloc
In-Reply-To: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <CAMQu2gx78cRN_u5NpycL-P1G=XXmdR5CaAd4bOBc8MitSJJSHw@mail.gmail.com>

On Mon, Mar 19, 2012 at 5:36 PM, Tarun Kanti DebBarma
<tarun.kanti at ti.com> wrote:
> These two patches incorporate changes to OMAP1 and OMAP2 platforms
s/two/four
I guess that's what you mean since there are 4 patches in the series.

Regards
Santosh


From tarun.kanti at ti.com  Mon Mar 19 08:30:25 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Mon, 19 Mar 2012 18:00:25 +0530
Subject: [PATCH v2 0/4] ARM: OMAP: boards: changes to support dynamic irq
 alloc
In-Reply-To: <CAMQu2gx78cRN_u5NpycL-P1G=XXmdR5CaAd4bOBc8MitSJJSHw@mail.gmail.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
 <CAMQu2gx78cRN_u5NpycL-P1G=XXmdR5CaAd4bOBc8MitSJJSHw@mail.gmail.com>
Message-ID: <CAC83ZvLFXAwjSSUywUZFYqCHaoVzUooc2UZvQM7+Aabny7nTuA@mail.gmail.com>

On Mon, Mar 19, 2012 at 5:47 PM, Shilimkar, Santosh
<santosh.shilimkar at ti.com> wrote:
> On Mon, Mar 19, 2012 at 5:36 PM, Tarun Kanti DebBarma
> <tarun.kanti at ti.com> wrote:
>> These two patches incorporate changes to OMAP1 and OMAP2 platforms
> s/two/four
> I guess that's what you mean since there are 4 patches in the series.
Yes, sorry about that. You are right, I missed changing the text. Thanks.
--
Tarun
>
> Regards
> Santosh


From broonie at opensource.wolfsonmicro.com  Mon Mar 19 09:02:22 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 19 Mar 2012 13:02:22 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120317104751.4F00E3E0910@localhost>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <201203150922.06379.arnd@arndb.de>
 <20120315102736.GA25371@avionic-0098.adnet.avionic-design.de>
 <20120317104751.4F00E3E0910@localhost>
Message-ID: <20120319130222.GC5705@sirena.org.uk>

On Sat, Mar 17, 2012 at 10:47:51AM +0000, Grant Likely wrote:

> After implementing both schemes (ie. interrupts+interrupt-names && [*-]gpios)
> I definitely prefer the fixed property name plus a separate names property.
> It is easier to use common code with that scheme, and easier to statically
> check for correctness.

It's not a fantastic experience when using the bindings as the arrays
grow large, though - keeping things matched up isn't much fun especially
if any of the elements in the array are optional.


From paul.liu at linaro.org  Mon Mar 19 09:04:29 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Mon, 19 Mar 2012 21:04:29 +0800
Subject: [PATCH] rtc: add support for Freescale SNVS RTC
Message-ID: <1332162269-16789-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

This adds an RTC driver for the Low Power (LP) section of SNVS.
It hooks into the /dev/rtc interface and supports ioctl to complete RTC
features. This driver supports device tree bindings.
It only uses the RTC hw in non-secure mode.

Signed-off-by: Anish Trivedi <anish at freescale.com>
Signed-off-by: Eric Miao <eric.miao at linaro.org>
Signed-off-by: Anson Huang <b20788 at freescale.com>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Cc: Alessandro Zummo <a.zummo at towertech.it>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/rtc/Kconfig    |   11 +
 drivers/rtc/Makefile   |    1 +
 drivers/rtc/rtc-snvs.c |  737 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 749 insertions(+), 0 deletions(-)
 create mode 100644 drivers/rtc/rtc-snvs.c

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 3a125b8..d58f4b7 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -634,6 +634,17 @@ config RTC_MXC
 	   This driver can also be built as a module, if so, the module
 	   will be called "rtc-mxc".
 
+config RTC_DRV_SNVS
+	tristate "Freescale SNVS Real Time Clock"
+	depends on ARCH_MXC
+	depends on RTC_CLASS
+	help
+	   If you say yes here you get support for the Freescale SNVS
+	   Low Power (LP) RTC module.
+
+	   This driver can also be built as a module, if so, the module
+	   will be called "rtc-snvs".
+
 config RTC_DRV_BQ4802
 	tristate "TI BQ4802"
 	help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 6e69823..8b30686 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -93,6 +93,7 @@ obj-$(CONFIG_RTC_DRV_S35390A)	+= rtc-s35390a.o
 obj-$(CONFIG_RTC_DRV_S3C)	+= rtc-s3c.o
 obj-$(CONFIG_RTC_DRV_SA1100)	+= rtc-sa1100.o
 obj-$(CONFIG_RTC_DRV_SH)	+= rtc-sh.o
+obj-$(CONFIG_RTC_DRV_SNVS)	+= rtc-snvs.o
 obj-$(CONFIG_RTC_DRV_SPEAR)	+= rtc-spear.o
 obj-$(CONFIG_RTC_DRV_STARFIRE)	+= rtc-starfire.o
 obj-$(CONFIG_RTC_DRV_STK17TA8)	+= rtc-stk17ta8.o
diff --git a/drivers/rtc/rtc-snvs.c b/drivers/rtc/rtc-snvs.c
new file mode 100644
index 0000000..49ac8a5
--- /dev/null
+++ b/drivers/rtc/rtc-snvs.c
@@ -0,0 +1,737 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+/*
+ * Implementation based on rtc-ds1553.c
+ */
+
+/*!
+ * @defgroup RTC Real Time Clock (RTC) Driver
+ */
+/*!
+ * @file rtc-snvs.c
+ * @brief Secure Real Time Clock (SRTC) interface in Freescale's SNVS module
+ *
+ * This file contains Real Time Clock interface for Linux. The Freescale
+ * SNVS module's Low Power (LP) SRTC functionality is utilized in this driver,
+ * in non-secure mode.
+ *
+ * @ingroup RTC
+ */
+
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/rtc.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/sched.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+/* Register definitions */
+#define	SNVS_HPSR	0x14	/* HP Status Register */
+#define	SNVS_LPCR	0x38	/* LP Control Register */
+#define	SNVS_LPSR	0x4C	/* LP Status Register */
+#define	SNVS_LPSRTCMR	0x50	/* LP Secure Real Time Counter MSB Register */
+#define	SNVS_LPSRTCLR	0x54	/* LP Secure Real Time Counter LSB Register */
+#define	SNVS_LPTAR	0x58	/* LP Time Alarm Register */
+#define	SNVS_LPSMCMR	0x5C	/* LP Secure Monotonic Counter MSB Register */
+#define	SNVS_LPSMCLR	0x60	/* LP Secure Monotonic Counter LSB Register */
+#define	SNVS_LPPGDR	0x64	/* LP Power Glitch Detector Register */
+#define	SNVS_LPGPR	0x68	/* LP General Purpose Register */
+
+/* Bit Definitions */
+#define	SNVS_HPSR_SSM_ST_MASK	0x00000F00
+#define	SNVS_HPSR_SSM_ST_SHIFT	8
+
+#define	SNVS_LPCR_SRTC_ENV	(1 << 0)
+#define	SNVS_LPCR_LPTA_EN	(1 << 1)
+#define	SNVS_LPCR_LPWUI_EN	(1 << 3)
+#define	SNVS_LPCR_ALL_INT_EN (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN)
+#define	SNVS_LPSR_LPTA		(1 << 0)
+#define	SNVS_LPPGDR_INIT	0x41736166
+
+/* Other defines */
+#define	SSM_ST_CHECK	0x9
+#define	SSM_ST_NON_SECURE	0xB
+#define	CNTR_TO_SECS_SH 15	/* Converts 47-bit counter to 32-bit seconds */
+
+#define RTC_READ_TIME_47BIT	_IOR('p', 0x20, unsigned long long)
+/* blocks until LPSCMR is set, returns difference */
+#define RTC_WAIT_TIME_SET	_IOR('p', 0x21, int64_t)
+
+struct rtc_drv_data {
+	struct rtc_device *rtc;
+	void __iomem *ioaddr;
+	int irq;
+	bool irq_enable;
+};
+
+static unsigned long rtc_status;
+
+static DEFINE_SPINLOCK(rtc_lock);
+DECLARE_COMPLETION(snvs_completion);
+static int64_t time_diff;
+
+/*!
+ * LP counter register reads should always use this function.
+ * This function reads 2 consective times from LP counter register
+ * until the 2 values match. This is to avoid reading corrupt
+ * value if the counter is in the middle of updating
+ */
+static inline u32 rtc_read_lp_counter(void __iomem *counter_reg)
+{
+	u64 read1, read2;
+	u32 counter_sec;
+
+	do {
+		/* MSB */
+		read1 = readl(counter_reg);
+		read1 <<= 32;
+		/* LSB */
+		read1 |= readl(counter_reg + 4);
+
+		/* MSB */
+		read2 = readl(counter_reg);
+		read2 <<= 32;
+		/* LSB */
+		read2 |= readl(counter_reg + 4);
+	} while (read1 != read2);
+
+	/* Convert 47-bit counter to 32-bit raw second count */
+	counter_sec = (u32) (read1 >> CNTR_TO_SECS_SH);
+
+	return counter_sec;
+}
+
+/*!
+ * This function does write synchronization for writes to the lp srtc block.
+ * To take care of the asynchronous CKIL clock, all writes from the IP domain
+ * will be synchronized to the CKIL domain.
+ */
+static inline void rtc_write_sync_lp(void __iomem *ioaddr)
+{
+	unsigned int i, count1, count2, count3;
+
+	/* Wait for 3 CKIL cycles */
+	for (i = 0; i < 3; i++) {
+
+		/* Do consective reads of LSB of counter to ensure integrity */
+		do {
+			count1 = readl(ioaddr + SNVS_LPSRTCLR);
+			count2 = readl(ioaddr + SNVS_LPSRTCLR);
+		} while (count1 != count2);
+
+		/* Now wait until counter value changes */
+		do {
+			do {
+				count2 = readl(ioaddr + SNVS_LPSRTCLR);
+				count3 = readl(ioaddr + SNVS_LPSRTCLR);
+			} while (count2 != count3);
+		} while (count3 == count1);
+	}
+}
+
+/*!
+ * This function updates the RTC alarm registers and then clears all the
+ * interrupt status bits.
+ *
+ * @param  alrm         the new alarm value to be updated in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	struct rtc_time alarm_tm, now_tm;
+	unsigned long now, time, lp_cr;
+	int ret;
+
+	now = rtc_read_lp_counter(ioaddr + SNVS_LPSRTCMR);
+	rtc_time_to_tm(now, &now_tm);
+
+	alarm_tm.tm_year = now_tm.tm_year;
+	alarm_tm.tm_mon = now_tm.tm_mon;
+	alarm_tm.tm_mday = now_tm.tm_mday;
+
+	alarm_tm.tm_hour = alrm->tm_hour;
+	alarm_tm.tm_min = alrm->tm_min;
+	alarm_tm.tm_sec = alrm->tm_sec;
+
+	rtc_tm_to_time(&now_tm, &now);
+	rtc_tm_to_time(&alarm_tm, &time);
+
+	if (time < now) {
+		time += 60 * 60 * 24;
+		rtc_time_to_tm(time, &alarm_tm);
+	}
+	ret = rtc_tm_to_time(&alarm_tm, &time);
+
+	/* Have to clear LPTA_EN before programming new alarm time in LPTAR */
+	lp_cr = readl(ioaddr + SNVS_LPCR);
+	writel(lp_cr & ~SNVS_LPCR_LPTA_EN, ioaddr + SNVS_LPCR);
+	rtc_write_sync_lp(ioaddr);
+
+	writel(time, ioaddr + SNVS_LPTAR);
+
+	/* clear alarm interrupt status bit */
+	writel(SNVS_LPSR_LPTA, ioaddr + SNVS_LPSR);
+
+	return ret;
+}
+
+/*!
+ * This function is the RTC interrupt service routine.
+ *
+ * @param  irq          RTC IRQ number
+ * @param  dev_id       device ID which is not used
+ *
+ * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file.
+ */
+static irqreturn_t snvs_rtc_interrupt(int irq, void *dev_id)
+{
+	struct platform_device *pdev = dev_id;
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	u32 lp_status, lp_cr;
+	u32 events = 0;
+
+	lp_status = readl(ioaddr + SNVS_LPSR);
+	lp_cr = readl(ioaddr + SNVS_LPCR);
+
+	/* update irq data & counter */
+	if (lp_status & SNVS_LPSR_LPTA) {
+		if (lp_cr & SNVS_LPCR_LPTA_EN)
+			events |= (RTC_AF | RTC_IRQF);
+
+		/* disable further lp alarm interrupts */
+		lp_cr &= ~(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
+	}
+
+	/* Update interrupt enables */
+	writel(lp_cr, ioaddr + SNVS_LPCR);
+
+	/* If no interrupts are enabled, turn off interrupts in kernel */
+	if (((lp_cr & SNVS_LPCR_ALL_INT_EN) == 0) && (pdata->irq_enable)) {
+		disable_irq_nosync(pdata->irq);
+		pdata->irq_enable = false;
+	}
+
+	/* clear interrupt status */
+	writel(lp_status, ioaddr + SNVS_LPSR);
+
+	rtc_write_sync_lp(ioaddr);
+	rtc_update_irq(pdata->rtc, 1, events);
+
+	return IRQ_HANDLED;
+}
+
+/*!
+ * This function is used to open the RTC driver.
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int snvs_rtc_open(struct device *dev)
+{
+	if (test_and_set_bit(1, &rtc_status))
+		return -EBUSY;
+
+	return 0;
+}
+
+/*!
+ * clear all interrupts and release the IRQ
+ */
+static void snvs_rtc_release(struct device *dev)
+{
+	rtc_status = 0;
+}
+
+/*!
+ * This function reads the current RTC time into tm in Gregorian date.
+ *
+ * @param  tm           contains the RTC time value upon return
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	rtc_time_to_tm(rtc_read_lp_counter(ioaddr + SNVS_LPSRTCMR), tm);
+
+	return 0;
+}
+
+/*!
+ * This function sets the internal RTC time based on tm in Gregorian date.
+ *
+ * @param  tm           the time value to be set in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	unsigned long time;
+	int ret;
+	u32 lp_cr;
+	u64 old_time_47bit, new_time_47bit;
+
+	ret = rtc_tm_to_time(tm, &time);
+	if (ret != 0)
+		return ret;
+
+	old_time_47bit = (((u64) (readl(ioaddr + SNVS_LPSRTCMR) &
+		((0x1 << CNTR_TO_SECS_SH) - 1)) << 32) |
+		((u64) readl(ioaddr + SNVS_LPSRTCLR)));
+
+	/* Disable RTC first */
+	lp_cr = readl(ioaddr + SNVS_LPCR) & ~SNVS_LPCR_SRTC_ENV;
+	writel(lp_cr, ioaddr + SNVS_LPCR);
+	while (readl(ioaddr + SNVS_LPCR) & SNVS_LPCR_SRTC_ENV)
+		;
+
+	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
+	writel(time << CNTR_TO_SECS_SH, ioaddr + SNVS_LPSRTCLR);
+	writel(time >> (32 - CNTR_TO_SECS_SH), ioaddr + SNVS_LPSRTCMR);
+
+	/* Enable RTC again */
+	writel(lp_cr | SNVS_LPCR_SRTC_ENV, ioaddr + SNVS_LPCR);
+	while (!(readl(ioaddr + SNVS_LPCR) & SNVS_LPCR_SRTC_ENV))
+		;
+
+	rtc_write_sync_lp(ioaddr);
+
+	new_time_47bit = (((u64) (readl(ioaddr + SNVS_LPSRTCMR) &
+		((0x1 << CNTR_TO_SECS_SH) - 1)) << 32) |
+		((u64) readl(ioaddr + SNVS_LPSRTCLR)));
+
+	time_diff = new_time_47bit - old_time_47bit;
+
+	/* signal all waiting threads that time changed */
+	complete_all(&snvs_completion);
+
+	/* allow signalled threads to handle the time change notification */
+	schedule();
+
+	/* reinitialize completion variable */
+	INIT_COMPLETION(snvs_completion);
+
+	return 0;
+}
+
+/*!
+ * This function reads the current alarm value into the passed in \b alrm
+ * argument. It updates the \b alrm's pending field value based on the whether
+ * an alarm interrupt occurs or not.
+ *
+ * @param  alrm         contains the RTC alarm value upon return
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	rtc_time_to_tm(readl(ioaddr + SNVS_LPTAR), &alrm->time);
+	alrm->pending =
+	    ((readl(ioaddr + SNVS_LPSR) & SNVS_LPSR_LPTA) != 0) ? 1 : 0;
+
+	return 0;
+}
+
+/*!
+ * This function sets the RTC alarm based on passed in alrm.
+ *
+ * @param  alrm         the alarm value to be set in the RTC
+ *
+ * @return  0 if successful; non-zero otherwise.
+ */
+static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	unsigned long lock_flags = 0;
+	u32 lp_cr;
+	int ret;
+
+	if (rtc_valid_tm(&alrm->time)) {
+		if (alrm->time.tm_sec > 59 ||
+		    alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) {
+			return -EINVAL;
+		}
+	}
+
+	spin_lock_irqsave(&rtc_lock, lock_flags);
+
+	ret = rtc_update_alarm(dev, &alrm->time);
+	if (ret)
+		goto out;
+
+	lp_cr = readl(ioaddr + SNVS_LPCR);
+
+	if (alrm->enabled)
+		lp_cr |= (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
+	else
+		lp_cr &= ~(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
+
+	if (lp_cr & SNVS_LPCR_ALL_INT_EN) {
+		if (!pdata->irq_enable) {
+			enable_irq(pdata->irq);
+			pdata->irq_enable = true;
+		}
+	} else {
+		if (pdata->irq_enable) {
+			disable_irq(pdata->irq);
+			pdata->irq_enable = false;
+		}
+	}
+
+	writel(lp_cr, ioaddr + SNVS_LPCR);
+
+out:
+	rtc_write_sync_lp(ioaddr);
+	spin_unlock_irqrestore(&rtc_lock, lock_flags);
+
+	return ret;
+}
+
+/*!
+ * This function is used to provide the content for the /proc/driver/rtc
+ * file.
+ *
+ * @param  seq  buffer to hold the information that the driver wants to write
+ *
+ * @return  The number of bytes written into the rtc file.
+ */
+static int snvs_rtc_proc(struct device *dev, struct seq_file *seq)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+
+	seq_printf(seq, "alarm_IRQ\t: %s\n",
+		   (((readl(ioaddr + SNVS_LPCR)) & SNVS_LPCR_LPTA_EN) !=
+		    0) ? "yes" : "no");
+
+	return 0;
+}
+
+static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	u32 lp_cr;
+	unsigned long lock_flags = 0;
+
+	spin_lock_irqsave(&rtc_lock, lock_flags);
+
+	if (enable) {
+		if (!pdata->irq_enable) {
+			enable_irq(pdata->irq);
+			pdata->irq_enable = true;
+		}
+		lp_cr = readl(ioaddr + SNVS_LPCR);
+		lp_cr |= (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
+		writel(lp_cr, ioaddr + SNVS_LPCR);
+	} else {
+		lp_cr = readl(ioaddr + SNVS_LPCR);
+		lp_cr &= ~(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
+		if (((lp_cr & SNVS_LPCR_ALL_INT_EN) == 0)
+		    && (pdata->irq_enable)) {
+			disable_irq(pdata->irq);
+			pdata->irq_enable = false;
+		}
+		writel(lp_cr, ioaddr + SNVS_LPCR);
+	}
+
+	rtc_write_sync_lp(ioaddr);
+	spin_unlock_irqrestore(&rtc_lock, lock_flags);
+
+	return 0;
+}
+
+/*!
+ * This function is used to support some ioctl calls directly.
+ * Other ioctl calls are supported indirectly through the
+ * arm/common/rtctime.c file.
+ *
+ * @param  cmd          ioctl command as defined in include/linux/rtc.h
+ * @param  arg          value for the ioctl command
+ *
+ * @return  0 if successful or negative value otherwise.
+ */
+static int snvs_rtc_ioctl(struct device *dev, unsigned int cmd,
+			 unsigned long arg)
+{
+	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
+	void __iomem *ioaddr = pdata->ioaddr;
+	u64 time_47bit;
+	int retVal;
+
+	switch (cmd) {
+	case RTC_READ_TIME_47BIT:
+		time_47bit = (((u64) (readl(ioaddr + SNVS_LPSRTCMR) &
+			((0x1 << CNTR_TO_SECS_SH) - 1)) << 32) |
+			((u64) readl(ioaddr + SNVS_LPSRTCLR)));
+
+		if (arg && copy_to_user((u64 *) arg, &time_47bit, sizeof(u64)))
+			return -EFAULT;
+
+		return 0;
+
+	/* This IOCTL to be used by processes to be notified of time changes */
+	case RTC_WAIT_TIME_SET:
+		/* don't block without releasing mutex first */
+		mutex_unlock(&pdata->rtc->ops_lock);
+
+		/* sleep till awakened by SRTC driver when LPSCMR is changed */
+		wait_for_completion(&snvs_completion);
+
+		/* relock mutex because rtc_dev_ioctl will unlock again */
+		retVal = mutex_lock_interruptible(&pdata->rtc->ops_lock);
+
+		/* copy the new time difference = new time - previous time
+		 * to the user param. The difference is a signed value */
+		if (arg && copy_to_user((int64_t *) arg, &time_diff,
+			sizeof(int64_t)))
+			return -EFAULT;
+
+		return retVal;
+
+	}
+
+	return -ENOIOCTLCMD;
+}
+
+/*!
+ * The RTC driver structure
+ */
+static struct rtc_class_ops snvs_rtc_ops = {
+	.open = snvs_rtc_open,
+	.release = snvs_rtc_release,
+	.read_time = snvs_rtc_read_time,
+	.set_time = snvs_rtc_set_time,
+	.read_alarm = snvs_rtc_read_alarm,
+	.set_alarm = snvs_rtc_set_alarm,
+	.proc = snvs_rtc_proc,
+	.ioctl = snvs_rtc_ioctl,
+	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
+};
+
+/*! SNVS RTC Power management control */
+static int __devinit snvs_rtc_probe(struct platform_device *pdev)
+{
+	struct timespec tv;
+	struct resource *res;
+	struct rtc_device *rtc;
+	struct rtc_drv_data *pdata = NULL;
+	void __iomem *ioaddr;
+	u32 lp_cr;
+	int ret = 0;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	ioaddr = ioremap(res->start, resource_size(res));
+	if (!ioaddr)
+		return -EADDRNOTAVAIL;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	pdata->ioaddr = ioaddr;
+
+	/* Configure and enable the RTC */
+	pdata->irq = platform_get_irq(pdev, 0);
+	if (pdata->irq >= 0) {
+		if (request_irq(pdata->irq, snvs_rtc_interrupt, IRQF_SHARED,
+				pdev->name, pdev) < 0) {
+			dev_warn(&pdev->dev, "interrupt not available.\n");
+			pdata->irq = -1;
+		} else {
+			disable_irq(pdata->irq);
+			pdata->irq_enable = false;
+		}
+	}
+
+	/* initialize glitch detect */
+	writel(SNVS_LPPGDR_INIT, ioaddr + SNVS_LPPGDR);
+	udelay(100);
+
+	/* clear lp interrupt status */
+	writel(0xFFFFFFFF, ioaddr + SNVS_LPSR);
+
+	/* Enable RTC */
+	lp_cr = readl(ioaddr + SNVS_LPCR);
+	if ((lp_cr & SNVS_LPCR_SRTC_ENV) == 0)
+		writel(lp_cr | SNVS_LPCR_SRTC_ENV, ioaddr + SNVS_LPCR);
+
+	udelay(100);
+
+	writel(0xFFFFFFFF, ioaddr + SNVS_LPSR);
+	udelay(100);
+
+	platform_set_drvdata(pdev, pdata);
+
+	rtc = rtc_device_register(pdev->name, &pdev->dev,
+				  &snvs_rtc_ops, THIS_MODULE);
+	if (IS_ERR(rtc)) {
+		ret = PTR_ERR(rtc);
+		goto err_out;
+	}
+
+	pdata->rtc = rtc;
+
+	tv.tv_nsec = 0;
+	tv.tv_sec = rtc_read_lp_counter(ioaddr + SNVS_LPSRTCMR);
+
+	/* By default, devices should wakeup if they can */
+	/* So snvs is set as "should wakeup" as it can */
+	device_init_wakeup(&pdev->dev, 1);
+
+	return ret;
+
+err_out:
+	iounmap(ioaddr);
+	if (pdata->irq >= 0)
+		free_irq(pdata->irq, pdev);
+
+	return ret;
+}
+
+static int __devexit snvs_rtc_remove(struct platform_device *pdev)
+{
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+	rtc_device_unregister(pdata->rtc);
+	if (pdata->irq >= 0)
+		free_irq(pdata->irq, pdev);
+	iounmap(pdata->ioaddr);
+
+	return 0;
+}
+
+/*!
+ * This function is called to save the system time delta relative to
+ * the SNVS RTC when enterring a low power state. This time delta is
+ * then used on resume to adjust the system time to account for time
+ * loss while suspended.
+ *
+ * @param   pdev  not used
+ * @param   state Power state to enter.
+ *
+ * @return  The function always returns 0.
+ */
+static int snvs_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+
+	if (device_may_wakeup(&pdev->dev)) {
+		enable_irq_wake(pdata->irq);
+	} else {
+		if (pdata->irq_enable)
+			disable_irq(pdata->irq);
+	}
+
+	return 0;
+}
+
+/*!
+ * This function is called to correct the system time based on the
+ * current SNVS RTC time relative to the time delta saved during
+ * suspend.
+ *
+ * @param   pdev  not used
+ *
+ * @return  The function always returns 0.
+ */
+static int snvs_rtc_resume(struct platform_device *pdev)
+{
+	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
+
+	if (device_may_wakeup(&pdev->dev)) {
+		disable_irq_wake(pdata->irq);
+	} else {
+		if (pdata->irq_enable)
+			enable_irq(pdata->irq);
+	}
+
+	return 0;
+}
+
+static const struct of_device_id __devinitdata snvs_dt_ids[] = {
+	{ .compatible = "fsl,snvs" },
+	{ /* sentinel */ }
+};
+
+/*!
+ * Contains pointers to the power management callback functions.
+ */
+static struct platform_driver snvs_rtc_driver = {
+	.driver = {
+		.name	= "snvs_rtc",
+		.owner	= THIS_MODULE,
+		.of_match_table = snvs_dt_ids,
+	},
+	.probe = snvs_rtc_probe,
+	.remove = __exit_p(snvs_rtc_remove),
+	.suspend = snvs_rtc_suspend,
+	.resume = snvs_rtc_resume,
+};
+
+/*!
+ * This function creates the /proc/driver/rtc file and registers the device RTC
+ * in the /dev/misc directory. It also reads the RTC value from external source
+ * and setup the internal RTC properly.
+ *
+ * @return  -1 if RTC is failed to initialize; 0 is successful.
+ */
+static int __init snvs_rtc_init(void)
+{
+	return platform_driver_register(&snvs_rtc_driver);
+}
+module_init(snvs_rtc_init);
+
+/*!
+ * This function removes the /proc/driver/rtc file and un-registers the
+ * device RTC from the /dev/misc directory.
+ */
+static void __exit snvs_rtc_exit(void)
+{
+	platform_driver_unregister(&snvs_rtc_driver);
+}
+module_exit(snvs_rtc_exit);
+
+MODULE_AUTHOR("Anish Trivedi <anish at freescale.com>, "
+	      "Eric Miao <eric.miao at linaro.org>, "
+	      "Anson Huang <b20788 at freescale.com>, "
+	      "Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
+MODULE_DESCRIPTION("SNVS Realtime Clock Driver (RTC)");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.1



From lost.distance at yahoo.com  Mon Mar 19 09:11:21 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Mon, 19 Mar 2012 13:11:21 +0000 (GMT)
Subject: [PATCH] pxa/hx4700: fix the LCD initialization
In-Reply-To: <CA+gwMcd14LVxF=pxyewQRDFUfTFxhmnTzHmxSF=_s2kJyxn5EQ@mail.gmail.com>
Message-ID: <1332162681.93014.YahooMailClassic@web29014.mail.ird.yahoo.com>

Hello Philipp,

--- On Mon, 19/3/12, Philipp Zabel <philipp.zabel at gmail.com> wrote:
> Hi Paul,
> 
> On Sat, Mar 17, 2012 at 3:48 PM, Paul Parsons <lost.distance at yahoo.com>
> wrote:
> > After some experimenting it seems that neither GPIO110
> "LCD_LVDD_3V3_ON"
> > nor GPIO112 "LCD_N2V7_7V3_ON" have any effect on the
> hx4700 LCD.
> > After the hx4700 boots I can turn either one off, or
> both off together,
> > and the LCD and touchscreen will continue to work
> normally.
> >
> > Is there an authoritative description of the 7 "LCD"
> GPIOs (GPIO59,
> > GPIO62, GPIO70, GPIO84, GPIO110, GPIO111, GPIO112) that
> are used by
> > the kernel, or the 2 "LCD" GPIOs (GPIO22, GPIO73) that
> are not used?
> > The SDG code provides no enlightenment.
> 
> that is a good question. Not having done any of the reverse
> engineering for hx4700 myself, I've always taken the SDG
> code as
> gospel.
> Unfortunately I am not aware of any hx4700 hardware
> schematics or even
> a datasheet for the acx523akm lcd panel.

I too searched for an LCD datasheet without success.

Consider this patch for LCD initialization which I have been trying for
the past couple of days:

1. Remove all references to GPIO110 and GPIO112.
2. Replace the first half of sony_lcd_init() with a one-time call to
sony_lcd_off() in hx4700_init().

It saves 21 lines and establishes symmetry in the init()/off() calls.

--- clean-3.3-rc7/arch/arm/mach-pxa/hx4700.c	2012-03-10 21:49:52.000000000 +0000
+++ linux-3.3-rc7/arch/arm/mach-pxa/hx4700.c	2012-03-19 12:54:44.420420630 +0000
@@ -331,42 +331,20 @@ static struct platform_device egpio = {
 
 static void sony_lcd_init(void)
 {
-	gpio_set_value(GPIO84_HX4700_LCD_SQN, 1);
-	gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
-	gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 0);
-	gpio_set_value(GPIO70_HX4700_LCD_SLIN1, 0);
-	gpio_set_value(GPIO62_HX4700_LCD_nRESET, 0);
-	mdelay(10);
-	gpio_set_value(GPIO59_HX4700_LCD_PC1, 0);
-	gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
-	mdelay(20);
-
-	gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 1);
-	mdelay(5);
 	gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 1);
-
-	/* FIXME: init w3220 registers here */
-
-	mdelay(5);
+	gpio_set_value(GPIO84_HX4700_LCD_SQN, 1);
 	gpio_set_value(GPIO70_HX4700_LCD_SLIN1, 1);
-	mdelay(10);
-	gpio_set_value(GPIO62_HX4700_LCD_nRESET, 1);
-	mdelay(10);
 	gpio_set_value(GPIO59_HX4700_LCD_PC1, 1);
-	mdelay(10);
-	gpio_set_value(GPIO112_HX4700_LCD_N2V7_7V3_ON, 1);
+	gpio_set_value(GPIO62_HX4700_LCD_nRESET, 1);
 }
 
 static void sony_lcd_off(void)
 {
-	gpio_set_value(GPIO59_HX4700_LCD_PC1, 0);
 	gpio_set_value(GPIO62_HX4700_LCD_nRESET, 0);
-	mdelay(10);
-	gpio_set_value(GPIO112_HX4700_LCD_N2V7_7V3_ON, 0);
-	mdelay(10);
+	gpio_set_value(GPIO59_HX4700_LCD_PC1, 0);
+	gpio_set_value(GPIO70_HX4700_LCD_SLIN1, 0);
+	gpio_set_value(GPIO84_HX4700_LCD_SQN, 0);
 	gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 0);
-	mdelay(10);
-	gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
 }
 
 #ifdef CONFIG_PM
@@ -825,7 +803,6 @@ static struct gpio global_gpios[] = {
 	{ GPIO62_HX4700_LCD_nRESET,       GPIOF_OUT_INIT_HIGH, "LCD_RESET" },
 	{ GPIO70_HX4700_LCD_SLIN1,        GPIOF_OUT_INIT_HIGH, "LCD_SLIN1" },
 	{ GPIO84_HX4700_LCD_SQN,          GPIOF_OUT_INIT_HIGH, "LCD_SQN" },
-	{ GPIO110_HX4700_LCD_LVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_LVDD" },
 	{ GPIO111_HX4700_LCD_AVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_AVDD" },
 	{ GPIO32_HX4700_RS232_ON,         GPIOF_OUT_INIT_HIGH, "RS232_ON" },
 	{ GPIO71_HX4700_ASIC3_nRESET,     GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
@@ -846,6 +823,8 @@ static void __init hx4700_init(void)
 	pxa_set_btuart_info(NULL);
 	pxa_set_stuart_info(NULL);
 
+	sony_lcd_off();
+
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	pxa_set_ficp_info(&ficp_info);



From nicolas.ferre at atmel.com  Mon Mar 19 09:30:05 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 19 Mar 2012 14:30:05 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120317094059.7C2333E08E2@localhost>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <20120317094059.7C2333E08E2@localhost>
Message-ID: <4F6734DD.3020203@atmel.com>

On 03/17/2012 10:40 AM, Grant Likely :
> On Thu, 15 Mar 2012 09:38:10 +0100, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
>> Add some basic helpers to retrieve a DMA controller device_node and the
>> DMA request specifications. By making DMA controllers register a generic
>> translation function, we allow the management of any type of DMA requests
>> specification.
>> The void * output of an of_dma_xlate() function that will be implemented
>> by the DMA controller can carry any type of "dma-request" argument.
>>
>> The DMA client will search its associated DMA controller in the list and
>> call the registered of_dam_xlate() function to retrieve the request values.
>>
>> One simple xlate function is provided for the "single number" type of
>> request binding.
>>
>> This implementation is independent from dmaengine so it can also be used
>> by legacy drivers.
>>
>> For legacy reason another API will export the DMA request number into a
>> Linux resource of type IORESOURCE_DMA.
>>
>> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
>> Signed-off-by: Benoit Cousson <b-cousson at ti.com>
> 
> Hi Nicolas,
> 
> Comments below.
> 
>> Cc: Stephen Warren <swarren at nvidia.com>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> Cc: Russell King <linux at arm.linux.org.uk>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> ---
>>  Documentation/devicetree/bindings/dma/dma.txt |   45 +++++
>>  drivers/of/Kconfig                            |    5 +
>>  drivers/of/Makefile                           |    1 +
>>  drivers/of/dma.c                              |  260 +++++++++++++++++++++++++
>>  include/linux/of_dma.h                        |   67 +++++++
>>  5 files changed, 378 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/dma/dma.txt
>>  create mode 100644 drivers/of/dma.c
>>  create mode 100644 include/linux/of_dma.h
>>
>> diff --git a/Documentation/devicetree/bindings/dma/dma.txt b/Documentation/devicetree/bindings/dma/dma.txt
>> new file mode 100644
>> index 0000000..c49e98d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/dma/dma.txt
>> @@ -0,0 +1,45 @@
>> +* Generic DMA Controller and DMA request bindings
>> +
>> +Generic binding to provide a way for a driver to retrieve the
>> +DMA request line that goes from an IP to a DMA controller.
>> +
>> +
>> +* DMA controller
>> +
>> +Required property:
>> +    - #dma-cells: Number of cells for each DMA line.
>> +
>> +
>> +Example:
>> +
>> +	sdma: dma-controller at 48000000 {
>> +		compatible = "ti,sdma-omap4"
>> +		reg = <0x48000000 0x1000>;
>> +		interrupts = <12>;
>> +		#dma-cells = <1>;
>> +	};
>> +
>> +
>> +
>> +* DMA client
>> +
>> +Client drivers should specify the DMA request property using a phandle to
>> +the controller. If needed, the DMA request identity on that controller is then
>> +added followed by optional request specifications.
>> +
>> +Required property:
>> +    - dma-request: List of phandle + dma-request + request specifications,
>> +      one group per request "line".
>> +Optional property:
>> +    - dma-request-names: list of strings in the same order as the dma-request
>> +      in the dma-request property.
>> +
>> +
>> +Example:
>> +
>> +	i2c1: i2c at 1 {
>> +		...
>> +		dma-request = <&sdma 2 &sdma 3>;
>> +		dma-request-names = "tx", "rx";
>> +		...
>> +	};
>> diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
>> index 268163d..7d1f06b 100644
>> --- a/drivers/of/Kconfig
>> +++ b/drivers/of/Kconfig
>> @@ -90,4 +90,9 @@ config OF_PCI_IRQ
>>  	help
>>  	  OpenFirmware PCI IRQ routing helpers
>>  
>> +config OF_DMA
>> +	def_bool y
>> +	help
>> +	  Device Tree DMA routing helpers
> 
> Not really any point in having this config symbol at all if it is
> always enabled.

Well, it is the same for:
config OF_DEVICE

But for sure, I can remove it: so I will add it to
obj-y = base.o <here>
in the Makefile.

>>  endmenu # OF
>> diff --git a/drivers/of/Makefile b/drivers/of/Makefile
>> index a73f5a5..6eb50c6 100644
>> --- a/drivers/of/Makefile
>> +++ b/drivers/of/Makefile
>> @@ -12,3 +12,4 @@ obj-$(CONFIG_OF_SELFTEST) += selftest.o
>>  obj-$(CONFIG_OF_MDIO)	+= of_mdio.o
>>  obj-$(CONFIG_OF_PCI)	+= of_pci.o
>>  obj-$(CONFIG_OF_PCI_IRQ)  += of_pci_irq.o
>> +obj-$(CONFIG_OF_DMA)	+= dma.o
>> diff --git a/drivers/of/dma.c b/drivers/of/dma.c
>> new file mode 100644
>> index 0000000..3315844
>> --- /dev/null
>> +++ b/drivers/of/dma.c
>> @@ -0,0 +1,260 @@
>> +/*
>> + * Device tree helpers for DMA request / controller
>> + *
>> + * Based on of_gpio.c
>> + *
>> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/module.h>
>> +#include <linux/rculist.h>
>> +#include <linux/slab.h>
>> +#include <linux/of.h>
>> +#include <linux/of_dma.h>
>> +
>> +static LIST_HEAD(of_dma_list);
>> +
>> +struct of_dma {
>> +	struct list_head of_dma_controllers;
>> +	struct device_node *of_node;
>> +	int of_dma_n_cells;
>> +	int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
>> +};
> 
> This _xlate is nearly useless as a generic API.  It solves the problem for
> the specific case where the driver is hard-coded to know which DMA engine
> to talk to, but since the returned data doesn't provide any context, it
> isn't useful if there are multiple DMA controllers to choose from.

You mean, if there is no DMA controller phandle specified in the
property? I think that it is not the purpose of this API to choose a DMA
controller, Nor to provide a channel. The only purpose of this API is to
give a HW request to be used by a DMA slave driver. This slave should
already have a channel to use and a controller to talk to.

> The void *data pointer must be replaced with a typed structure so that
> context can be returned.

I am not sure to follow you entirely... How do I address the fact that
several types of request value can be returned then?

BTW, can we imagine a phandle property with a sting as a argument?
should it be written this way?
dma-request = <&testdmac1>, "slave-rx", "slave-tx";

If yes, the of_parse_phandle_with_args() is not working on this type...

(I realize that there seems to be no way out for a generic API: maybe we
should move to one or two cases to address and concentrate on them).

>> +
>> +/**
>> + * of_dma_find_controller() - Find a DMA controller in DT DMA helpers list
>> + * @np:		device node of DMA controller
>> + */
>> +static struct of_dma *of_dma_find_controller(struct device_node *np)
>> +{
>> +	struct of_dma	*ofdma;
>> +
>> +	list_for_each_entry_rcu(ofdma, &of_dma_list, of_dma_controllers) {
>> +		if (ofdma->of_node == np)
>> +			return ofdma;
>> +	}
>> +
>> +	return NULL;
>> +}
>> +
>> +/**
>> + * of_dma_controller_register() - Register a DMA controller to DT DMA helpers
>> + * @np:			device node of DMA controller
>> + * @of_dma_xlate:	generic translation function which converts a phandle
>> + *			arguments list into a generic output value
>> + *
>> + * Returns 0 on success or appropriate errno value on error.
>> + *
>> + * If #dma-cells is not specified in DMA controller device tree node, we assume
>> + * that the DMA controller phandle will come without argument.
>> + *
>> + * Allocated memory should be freed with appropriate of_dma_controller_free()
>> + * call.
>> + */
>> +int of_dma_controller_register(struct device_node *np,
>> +			int (*of_dma_xlate)(struct of_phandle_args *, void *))
>> +{
>> +	struct of_dma	*ofdma;
>> +	const __be32	*nbcells;
>> +
>> +	if (!np || !of_dma_xlate) {
>> +		pr_err("%s: not enough information provided\n", __func__);
>> +		return -EINVAL;
>> +	}
>> +
>> +	ofdma = kzalloc(sizeof(*ofdma), GFP_KERNEL);
>> +	if (!ofdma)
>> +		return -ENOMEM;
>> +
>> +	nbcells = of_get_property(np, "#dma-cells", NULL);
>> +	if (!nbcells)
>> +		/*
>> +		 * no #dma-cells properties: assume no argument to
>> +		 * dma-request property on slave side
>> +		 */
>> +		ofdma->of_dma_n_cells = 0;
>> +	else
>> +		ofdma->of_dma_n_cells = be32_to_cpup(nbcells);
> 
> Make #dma-cells a required property

Ok.

>> +
>> +	ofdma->of_node = np;
>> +	ofdma->of_dma_xlate = of_dma_xlate;
>> +
>> +	/* Now queue of_dma controller structure in list */
>> +	list_add_tail_rcu(&ofdma->of_dma_controllers, &of_dma_list);
>> +
>> +	return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(of_dma_controller_register);
>> +
>> +/**
>> + * of_dma_controller_free() - Remove a DMA controller from DT DMA helpers list
>> + * @np:		device node of DMA controller
>> + *
>> + * Memory allocated by of_dma_controller_register() is freed here.
>> + */
>> +void of_dma_controller_free(struct device_node *np)
>> +{
>> +	struct of_dma	*ofdma;
>> +
>> +	ofdma = of_dma_find_controller(np);
>> +	if (ofdma) {
>> +		list_del_rcu(&ofdma->of_dma_controllers);
>> +		kfree(ofdma);
>> +	}
>> +}
>> +EXPORT_SYMBOL_GPL(of_dma_controller_free);
>> +
>> +/**
>> + * of_get_dma_request() - Get the associated DMA request data
>> + * @np:		device node to get DMA request from
>> + * @index:	index of the DMA request
>> + * @out_data:	a output that can be filled in by the of_dma_xlate() function
>> + *
>> + * Returns return value of of_dma_xlate() and fills out_data (if provided).
>> + * On error returns the appropriate errno value.
>> + */
>> +int of_get_dma_request(struct device_node *np, int index,
>> +		       void *out_data)
>> +{
>> +	struct of_phandle_args	dma_spec;
>> +	struct of_dma		*ofdma;
>> +	int			ret;
>> +
>> +	ret = of_parse_phandle_with_args(np, "dma-request", "#dma-cells",
>> +					 index, &dma_spec);
>> +	if (ret) {
>> +		pr_err("%s: can't parse dma property\n", np->full_name);
>> +		goto err0;
>> +	}
>> +
>> +	if (list_empty(&of_dma_list)) {
>> +		pr_debug("%s: empty DMA controller list\n",
>> +			 np->full_name);
>> +		ret = -ENOENT;
>> +		goto err1;
>> +	}
>> +
>> +	ofdma = of_dma_find_controller(dma_spec.np);
>> +	if (!ofdma) {
>> +		pr_debug("%s: DMA controller %s isn't registered\n",
>> +			 np->full_name, dma_spec.np->full_name);
>> +		ret = -ENODEV;
>> +		goto err1;
>> +	}
>> +
>> +	if (dma_spec.args_count != ofdma->of_dma_n_cells) {
>> +		pr_debug("%s: wrong #dma-cells for %s\n",
>> +			 np->full_name, dma_spec.np->full_name);
>> +		ret = -EINVAL;
>> +		goto err1;
>> +	}
>> +
>> +	ret = ofdma->of_dma_xlate(&dma_spec, out_data);
>> +
>> +err1:
>> +	of_node_put(dma_spec.np);
>> +err0:
>> +	pr_debug("%s exited with status %d\n", __func__, ret);
>> +	return ret;
>> +}
>> +EXPORT_SYMBOL_GPL(of_get_dma_request);
>> +
>> +/**
>> + * of_dma_xlate_onenumbercell() - Generic DMA xlate for direct one cell bindings
>> + *
>> + * Device Tree DMA translation function which works with one cell bindings
>> + * where the cell values map directly to the hardware request number understood
>> + * by the DMA controller.
>> + */
>> +int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec, void *dma_req)
>> +{
>> +	if (!dma_spec)
>> +		return -EINVAL;
>> +	if (WARN_ON(dma_spec->args_count != 1))
>> +		return -EINVAL;
>> +	*(int *)dma_req = dma_spec->args[0];
> 
> Following on from comment above; the void *dma_req parameter is dangerous.  How
> does this function know that it has been passed an int* pointer?

Well, that is a drawback that comes from having to address generic
cases. But anyway, if the DMA controller decide to register a .xlate()
function that returns an integer, the slave driver that will ask a
"request line" to this DMA controller will be aware that an integer has
to be passed to of_get_dma_request().

(
but I realize that a test on dma_req is certainly missing:
if (!dma_req) return -ENOBUFS;
)

It is true also that if we can find something generic and cleaner, I
will vote for it...

>> +	return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(of_dma_xlate_onenumbercell);
>> +
>> +/**
>> + * of_dma_count - Count DMA requests for a device
>> + * @np:		device node to count DMAs for
>> + *
>> + * The function returns the count of DMA requests specified for a node.
>> + *
>> + * Note that the empty DMA specifiers counts too. For example,
>> + *
>> + * dma-request = <0
>> + *                &sdma 1
>> + *                0
>> + *                &sdma 3>;
>> + *
>> + * defines four DMAs (so this function will return 4), two of which
>> + * are not specified.
>> + */
>> +unsigned int of_dma_count(struct device_node *np)
>> +{
>> +	unsigned int cnt = 0;
>> +
>> +	do {
>> +		int ret;
>> +
>> +		ret = of_parse_phandle_with_args(np, "dma-request",
>> +						 "#dma-cells", cnt, NULL);
>> +		/* A hole in the dma-request = <> counts anyway. */
>> +		if (ret < 0 && ret != -EEXIST)
>> +			break;
>> +	} while (++cnt);
>> +
>> +	return cnt;
>> +}
>> +EXPORT_SYMBOL_GPL(of_dma_count);
>> +
>> +/**
>> + * of_dma_to_resource - Decode a node's DMA and return it as a resource
>> + * @dev: pointer to device tree node
>> + * @index: zero-based index of the DMA request
>> + * @r: pointer to resource structure to return result into.
>> + *
>> + * Using a resource to export a DMA request number to a driver should
>> + * be used only for legacy purpose and on system when only one DMA controller
>> + * is present.
>> + * The proper and only scalable way is to use the native of_get_dma_request API
>> + * in order retrieve both the DMA controller device node and the DMA request
>> + * line for that controller.
>> + */
>> +int of_dma_to_resource(struct device_node *dev, int index, struct resource *r)
>> +{
>> +	const char *name = NULL;
>> +	int dma;
>> +	int ret;
>> +
>> +	if (!r)
>> +		return -EINVAL;
>> +
>> +	ret = of_get_dma_request(dev, index, &dma);
>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	/*
>> +	 * Get optional "dma-request-names" property to add a name
>> +	 * to the resource.
>> +	 */
>> +	of_property_read_string_index(dev, "dma-request-names", index,
>> +				      &name);
>> +
>> +	r->start = dma;
>> +	r->end = dma;
>> +	r->flags = IORESOURCE_DMA;
>> +	r->name = name ? name : dev->full_name;
> 
> I'll reiterate my concern here.  The dual meaning of r->name depending
> on the presence of a dma-request-names property is a real problem.  I know
> this patch set hasn't introduced the problem since it already exists for
> register regions and irqs, but it is expanding it.

After discussion between Benoit and Arnd it is clear now that the
of_dma_to_resource() API will go away.

>> +
>> +	return dma;
>> +}
>> +EXPORT_SYMBOL_GPL(of_dma_to_resource);
>> diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
>> new file mode 100644
>> index 0000000..c6147bb
>> --- /dev/null
>> +++ b/include/linux/of_dma.h
>> @@ -0,0 +1,67 @@
>> +/*
>> + * OF helpers for DMA request / controller
>> + *
>> + * Based on of_gpio.h
>> + *
>> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#ifndef __LINUX_OF_DMA_H
>> +#define __LINUX_OF_DMA_H
>> +
>> +#include <linux/of.h>
>> +
>> +struct device_node;
>> +
>> +#ifdef CONFIG_OF_DMA
>> +
>> +extern int of_dma_controller_register(struct device_node *np,
>> +			int (*of_dma_xlate)(struct of_phandle_args *, void *));
>> +extern void of_dma_controller_free(struct device_node *np);
>> +extern int of_get_dma_request(struct device_node *np, int index,
>> +			      void *out_data);
>> +extern unsigned int of_dma_count(struct device_node *np);
>> +extern int of_dma_to_resource(struct device_node *dev, int index,
>> +			      struct resource *r);
>> +
>> +extern int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
>> +				      void *dma_req);
>> +#else /* CONFIG_OF_DMA */
>> +
>> +static int of_dma_controller_register(struct device_node *np,
>> +			int (*of_dma_xlate)(struct of_phandle_args *, void *))
>> +{
>> +	return -ENOSYS;
>> +}
>> +
>> +static void of_dma_controller_free(struct device_node *np) {}
>> +
>> +extern int of_get_dma_request(struct device_node *np, int index,
>> +			      void *out_data)
>> +{
>> +	return -ENOSYS;
>> +}
>> +
>> +static inline unsigned int of_dma_count(struct device_node *np)
>> +{
>> +	return 0;
>> +}
>> +
>> +static int of_dma_to_resource(struct device_node *dev, int index,
>> +			      struct resource *r);
>> +{
>> +	return -ENOSYS;
>> +}
>> +
>> +static int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
>> +				      void *dma_req)
>> +{
>> +	return -ENOSYS;
>> +}
>> +#endif /* CONFIG_OF_DMA */
>> +
>> +#endif /* __LINUX_OF_DMA_H */
>> -- 
>> 1.7.9
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


-- 
Nicolas Ferre


From s.hauer at pengutronix.de  Mon Mar 19 09:36:01 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 14:36:01 +0100
Subject: [PATCH 3/8] ARM i.MX timer: request correct clock
In-Reply-To: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1332164166-6055-4-git-send-email-s.hauer@pengutronix.de>

We used to pass the timer clock directly to mxc_timer_init. We
should instead request the correct clock. This is an intermediate
step: For now we request the clock in the timer code when NULL
is passed as clock.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/plat-mxc/time.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 1c96cdb..462aecb 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -283,7 +283,10 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 {
 	uint32_t tctl_val;
 
-	clk_enable(timer_clk);
+	if (!timer_clk)
+		timer_clk = clk_get_sys("imx-gpt.0", "per");
+
+	clk_prepare_enable(timer_clk);
 
 	timer_base = base;
 
-- 
1.7.9.1



From s.hauer at pengutronix.de  Mon Mar 19 09:36:02 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 14:36:02 +0100
Subject: [PATCH 4/8] ARM i.MX: Add common clock support for pllv1
In-Reply-To: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1332164166-6055-5-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/Makefile    |    2 +
 arch/arm/mach-imx/clk-pllv1.c |   59 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 61 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-imx/clk-pllv1.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 55db9c4..1f138ae 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
 
 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
 
+obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o
+
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
 
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
new file mode 100644
index 0000000..afbd95f
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -0,0 +1,59 @@
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+#include "clk.h"
+
+/**
+ * pll v1
+ *
+ * @clk_hw	clock source
+ * @parent	the parent clock name
+ * @base	base address of pll registers
+ *
+ * PLL clock version 1, found on i.MX1/21/25/27/31/35
+ */
+struct clk_pllv1 {
+	struct clk_hw	hw;
+	void __iomem	*base;
+	char		*parent;
+};
+
+#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
+
+static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_pllv1 *pll = to_clk_pllv1(hw);
+
+	return mxc_decode_pll(readl(pll->base), parent_rate);
+}
+
+struct clk_ops clk_pllv1_ops = {
+	.recalc_rate = clk_pllv1_recalc_rate,
+};
+
+struct clk *imx_clk_pllv1(const char *name, char *parent,
+		void __iomem *base)
+{
+	struct clk_pllv1 *pll;
+	struct clk *clk;
+
+	pll = kmalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return NULL;
+
+	pll->base = base;
+	pll->parent = parent;
+
+	clk = clk_register(NULL, name, &clk_pllv1_ops, &pll->hw, &pll->parent,
+			1, 0);
+	if (!clk)
+		kfree(pll);
+
+	return clk;
+}
-- 
1.7.9.1



From s.hauer at pengutronix.de  Mon Mar 19 09:35:58 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 14:35:58 +0100
Subject: i.MX: Convert v4/v5 based SoCs to common clock framework
Message-ID: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>

Hi All,

The following patches convert the i.MX v4/v5 based SoCs to the common
clock framework.  They may not be completely ready, I am posting it now
because I'd like to show that the function based clock initializers are
indeed usable in real life and that the end result does not look too
bad.

This series depends on another series not yet posted which convert the
i.MX drivers to not depend on grouped clocks. I will follow up on this
after the merge window. My plan for these patches is to put them into
the arm-soc staging area after the merge window to let them stabilize
until hopefully before the next merge window there are no regressions
left.

Except the i.MX21 port all SoCs are runtime tested with the basic
devices (at least uart and network; I tested more, but not
systematically). Testers for these patches are very welcome, I will
happily integrate fixups into this series. A branch containing Mikes
latest clock patches, the driver fixups and this series can be found
here:

git://git.pengutronix.de/git/imx/linux-2.6.git work/imx-clk-v4-v5

As a side note, we currently compile all i.MX v4/v5 based SoCs in a
single defconfig. Since a kernel can only be built with or without the
common clock framework this series is not fully bisectable, you have to
disable the not yet converted SoCs in between.

The patch for removing the old clock support is not included in this
post, but with the removal the overall diffstat looks like this:

 arch/arm/mach-imx/clock-imx1.c           |  636 ---------------
 arch/arm/mach-imx/clock-imx21.c          | 1239 -------------------------------
 arch/arm/mach-imx/clock-imx25.c          |  346 --------
 arch/arm/mach-imx/clock-imx27.c          |  766 -------------------
 b/arch/arm/mach-imx/Kconfig              |    4 
 b/arch/arm/mach-imx/Makefile             |   10 
 b/arch/arm/mach-imx/clk-imx1.c           |  118 ++
 b/arch/arm/mach-imx/clk-imx21.c          |  177 ++++
 b/arch/arm/mach-imx/clk-imx25.c          |  242 ++++++
 b/arch/arm/mach-imx/clk-imx27.c          |  277 ++++++
 b/arch/arm/mach-imx/clk-pllv1.c          |   59 +
 b/arch/arm/mach-imx/clk.h                |   44 +
 b/arch/arm/plat-mxc/clock.c              |   11 
 b/arch/arm/plat-mxc/include/mach/clock.h |    4 
 b/arch/arm/plat-mxc/time.c               |    5 
 15 files changed, 946 insertions(+), 2992 deletions(-)

----------------------------------------------------------------
Sascha Hauer (7):
      ARM i.MX: prepare for common clock framework
      ARM i.MX timer: request correct clock
      ARM i.MX: Add common clock support for pllv1
      ARM i.MX1: implement clocks using common clock framework
      ARM i.MX21: implement clocks using common clock framework
      ARM i.MX25: implement clocks using common clock framework
      ARM i.MX27: implement clocks using common clock framework

 arch/arm/mach-imx/Kconfig              |    4 +
 arch/arm/mach-imx/Makefile             |   10 +-
 arch/arm/mach-imx/clk-imx1.c           |  118 ++++++++++++++
 arch/arm/mach-imx/clk-imx21.c          |  177 ++++++++++++++++++++
 arch/arm/mach-imx/clk-imx25.c          |  242 ++++++++++++++++++++++++++++
 arch/arm/mach-imx/clk-imx27.c          |  277 ++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/clk-pllv1.c          |   59 +++++++
 arch/arm/mach-imx/clk.h                |   44 +++++
 arch/arm/plat-mxc/clock.c              |   11 ++
 arch/arm/plat-mxc/include/mach/clock.h |    4 +
 arch/arm/plat-mxc/time.c               |    5 +-
 11 files changed, 946 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-imx/clk-imx1.c
 create mode 100644 arch/arm/mach-imx/clk-imx21.c
 create mode 100644 arch/arm/mach-imx/clk-imx25.c
 create mode 100644 arch/arm/mach-imx/clk-imx27.c
 create mode 100644 arch/arm/mach-imx/clk-pllv1.c
 create mode 100644 arch/arm/mach-imx/clk.h


From s.hauer at pengutronix.de  Mon Mar 19 09:36:06 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 14:36:06 +0100
Subject: [PATCH 8/8] ARM i.MX27: implement clocks using common clock framework
In-Reply-To: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1332164166-6055-9-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig     |    1 +
 arch/arm/mach-imx/Makefile    |    2 +-
 arch/arm/mach-imx/clk-imx27.c |  277 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 279 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-imx/clk-imx27.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4623865..bbef3d0 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -65,6 +65,7 @@ config SOC_IMX25
 config SOC_IMX27
 	bool
 	select MACH_MX27
+	select COMMON_CLK
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
 	select IMX_HAVE_DMA_V1
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d96e2ce..b39f2d6 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -6,7 +6,7 @@ obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
 obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
 
 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
-obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
+obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
 
 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
new file mode 100644
index 0000000..e44e70e
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -0,0 +1,277 @@
+/*
+ * Copyright 2012 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+#include "clk.h"
+
+#define IO_ADDR_CCM(off)	(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
+
+/* Register offsets */
+#define CCM_CSCR		IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0		IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1		IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0		IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1		IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL		IO_ADDR_CCM(0x14)
+#define CCM_PCDR0		IO_ADDR_CCM(0x18)
+#define CCM_PCDR1		IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0		IO_ADDR_CCM(0x20)
+#define CCM_PCCR1		IO_ADDR_CCM(0x24)
+#define CCM_CCSR		IO_ADDR_CCM(0x28)
+#define CCM_PMCTL		IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT		IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL		IO_ADDR_CCM(0x34)
+
+#define CCM_CSCR_UPDATE_DIS	(1 << 31)
+#define CCM_CSCR_SSI2		(1 << 23)
+#define CCM_CSCR_SSI1		(1 << 22)
+#define CCM_CSCR_VPU		(1 << 21)
+#define CCM_CSCR_MSHC           (1 << 20)
+#define CCM_CSCR_SPLLRES        (1 << 19)
+#define CCM_CSCR_MPLLRES        (1 << 18)
+#define CCM_CSCR_SP             (1 << 17)
+#define CCM_CSCR_MCU            (1 << 16)
+#define CCM_CSCR_OSC26MDIV      (1 << 4)
+#define CCM_CSCR_OSC26M         (1 << 3)
+#define CCM_CSCR_FPM            (1 << 2)
+#define CCM_CSCR_SPEN           (1 << 1)
+#define CCM_CSCR_MPEN           (1 << 0)
+
+/* i.MX27 TO 2+ */
+#define CCM_CSCR_ARM_SRC        (1 << 15)
+
+#define CCM_SPCTL1_LF           (1 << 15)
+#define CCM_SPCTL1_BRMO         (1 << 6)
+
+struct clkl {
+	struct clk_lookup lookup;
+	const char *clkname;
+};
+
+#define clkdev(d, n, c) \
+	{ \
+		.lookup.dev_id = d, \
+		.lookup.con_id = n, \
+		.clkname = c, \
+	},
+
+static struct clkl lookups[] = {
+	clkdev("imx21-uart.0", "ipg", "uart1_ipg_gate")
+	clkdev("imx21-uart.0", "per", "per1_gate")
+	clkdev("imx21-uart.1", "ipg", "uart2_ipg_gate")
+	clkdev("imx21-uart.1", "per", "per1_gate")
+	clkdev("imx21-uart.2", "ipg", "uart3_ipg_gate")
+	clkdev("imx21-uart.2", "per", "per1_gate")
+	clkdev("imx21-uart.3", "ipg", "uart4_ipg_gate")
+	clkdev("imx21-uart.3", "per", "per1_gate")
+	clkdev("imx21-uart.4", "ipg", "uart5_ipg_gate")
+	clkdev("imx21-uart.4", "per", "per1_gate")
+	clkdev("imx21-uart.5", "ipg", "uart6_ipg_gate")
+	clkdev("imx21-uart.5", "per", "per1_gate")
+	clkdev("imx-gpt.0", "ipg", "gpt1_ipg_gate")
+	clkdev("imx-gpt.0", "per", "per1_gate")
+	clkdev("imx-gpt.1", "ipg", "gpt2_ipg_gate")
+	clkdev("imx-gpt.1", "per", "per1_gate")
+	clkdev("imx-gpt.2", "ipg", "gpt3_ipg_gate")
+	clkdev("imx-gpt.2", "per", "per1_gate")
+	clkdev("imx-gpt.3", "ipg", "gpt4_ipg_gate")
+	clkdev("imx-gpt.3", "per", "per1_gate")
+	clkdev("imx-gpt.4", "ipg", "gpt5_ipg_gate")
+	clkdev("imx-gpt.4", "per", "per1_gate")
+	clkdev("imx-gpt.5", "ipg", "gpt6_ipg_gate")
+	clkdev("imx-gpt.5", "per", "per1_gate")
+	clkdev("mxc_pwm.0", NULL, "pwm")
+	clkdev("mxc-mmc.0", "per", "per2_gate")
+	clkdev("mxc-mmc.0", "ipg", "sdhc1_ipg_gate")
+	clkdev("mxc-mmc.1", "per", "per2_gate")
+	clkdev("mxc-mmc.1", "ipg", "sdhc2_ipg_gate")
+	clkdev("mxc-mmc.2", "per", "per2_gate")
+	clkdev("mxc-mmc.2", "ipg", "sdhc2_ipg_gate")
+	clkdev("imx27-cspi.0", NULL, "cspi1")
+	clkdev("imx27-cspi.1", NULL, "cspi2")
+	clkdev("imx27-cspi.2", NULL, "cspi3")
+	clkdev("imx-fb.0", "per", "per3_gate")
+	clkdev("imx-fb.0", "ipg", "lcdc_ipg_gate")
+	clkdev("imx-fb.0", "ahb", "lcdc_ahb_gate")
+	clkdev("mx2-camera.0", NULL, "csi")
+	clkdev("fsl-usb2-udc", "usb", "usb")
+	clkdev("fsl-usb2-udc", "usb_ahb", "usb_ahb_gate")
+	clkdev("mxc-ehci.0", "usb", "usb")
+	clkdev("mxc-ehci.0", "usb_ahb", "usb_ahb_gate")
+	clkdev("mxc-ehci.1", "usb", "usb")
+	clkdev("mxc-ehci.1", "usb_ahb", "usb_ahb_gate")
+	clkdev("mxc-ehci.2", "usb", "usb")
+	clkdev("mxc-ehci.2", "usb_ahb", "usb_ahb_gate")
+	clkdev("imx-ssi.0", NULL, "ssi1_ipg_gate")
+	clkdev("imx-ssi.1", NULL, "ssi2_ipg_gate")
+	clkdev("mxc_nand.0", NULL, "nfc_baud_gate")
+	clkdev("imx-vpu", "per", "vpu_baud_gate")
+	clkdev("imx-vpu", "ahb", "vpu_ahb_gate")
+	clkdev("imx-dma", "ahb", "dma_ahb_gate")
+	clkdev("imx-dma", "ipg", "dma_ipg_gate")
+	clkdev("imx27-fec.0", "ipg", "fec_ipg_gate")
+	clkdev("imx27-fec.0", "ahb", "fec_ahb_gate")
+	clkdev("imx2-wdt.0", NULL, "wdog_ipg_gate")
+	clkdev("imx-i2c.0", NULL, "i2c1_ipg_gate")
+	clkdev("imx-i2c.1", NULL, "i2c2_ipg_gate")
+	clkdev("mxc_w1.0", NULL, "owire_ipg_gate")
+	clkdev("imx-keypad", NULL, "kpp_ipg_gate")
+	clkdev("imx-emma", "ahb", "emma_ahb_gate")
+	clkdev("imx-emma", "ipg", "emma_ipg_gate")
+	clkdev(NULL, "iim", "iim_ipg_gate")
+	clkdev(NULL, "gpio", "gpio_ipg_gate")
+	clkdev(NULL, "brom", "brom_ahb_gate")
+	clkdev(NULL, "ata", "ata_ahb_gate")
+	clkdev(NULL, "rtc", "rtc_ipg_gate")
+	clkdev(NULL, "scc", "scc_ipg_gate")
+	clkdev(NULL, "cpu", "cpu_div")
+	clkdev(NULL, "emi_ahb" , "emi_ahb_gate")
+	clkdev("imx-ssi.0", "bitrate" , "ssi1_baud_gate")
+	clkdev("imx-ssi.1", "bitrate" , "ssi2_baud_gate")
+};
+
+static char *vpu_sel_clks[] = { "spll", "mpll_main2", };
+static char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
+static char *clko_sel_clks[] = {
+	"ckil", "prem", "ckih", "ckih",
+	"ckih", "mpll", "spll", "cpu_div",
+	"ahb", "ipg", "per1_div", "per2_div",
+	"per3_div", "per4_div", "ssi1_div", "ssi2_div",
+	"nfc_div", "mshc_div", "vpu_div", "60m",
+	"32k", "usb_div", "dptc",
+};
+
+static char *ssi_sel_clks[] = { "spll", "mpll", };
+
+int __init mx27_clocks_init(unsigned long fref)
+{
+	int i;
+	struct clk *emi_ahb;
+
+	imx_clk_fixed("dummy", 0);
+	imx_clk_fixed("ckih", fref);
+	imx_clk_fixed("ckil", 32768);
+	imx_clk_pllv1("mpll", "ckih", CCM_MPCTL0);
+	imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
+	imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
+
+	if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
+		imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
+		imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+	} else {
+		imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
+		imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
+	}
+
+	imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
+	imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
+	imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
+	imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
+	imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
+	imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
+	imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 3);
+	imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
+	imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
+	imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
+	if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
+		imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
+	else
+		imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
+	imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
+	imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+	imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+	imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
+	imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 3);
+	imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
+	imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
+	imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
+	imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
+	imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
+	imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
+	imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
+	imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
+	imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
+	imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
+	imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
+	imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
+	imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
+	imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
+	imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
+	imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
+	imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
+	imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
+	imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
+	imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
+	imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
+	imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
+	imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
+	imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
+	imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
+	imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
+	imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
+	imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
+	imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
+	imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
+	imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
+	imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1,  4);
+	imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1,  5);
+	imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1,  6);
+	imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1,  7);
+	imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1,  8);
+	imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1,  9);
+	imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
+	imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
+	imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
+	imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
+	imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
+	imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
+	imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
+	imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
+	emi_ahb = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
+	imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
+	imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
+	imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
+	imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
+	imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
+	imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
+	imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
+	imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
+	imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
+	imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
+	imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
+	imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
+
+	for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+		struct clkl *l = &lookups[i];
+		l->lookup.clk = __clk_lookup(l->clkname);
+		clkdev_add(&l->lookup);
+	}
+
+	mxc_timer_init(NULL, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
+			MX27_INT_GPT1);
+
+	clk_prepare_enable(emi_ahb);
+
+	return 0;
+}
-- 
1.7.9.1



From s.hauer at pengutronix.de  Mon Mar 19 09:35:59 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 14:35:59 +0100
Subject: [PATCH 1/8] clk: add a fixed factor clock
In-Reply-To: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1332164166-6055-2-git-send-email-s.hauer@pengutronix.de>

Having fixed factors/dividers in hardware is a common pattern, so
add a clock doing this. Currently no rate propagation is supported.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 drivers/clk/Makefile           |    2 +-
 drivers/clk/clk-fixed-factor.c |   97 ++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-provider.h   |    4 ++
 3 files changed, 102 insertions(+), 1 deletions(-)
 create mode 100644 drivers/clk/clk-fixed-factor.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1f736bc..24aa714 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,4 +1,4 @@
 
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
-				   clk-mux.o clk-divider.o
+				   clk-mux.o clk-divider.o clk-fixed-factor.o
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
new file mode 100644
index 0000000..7c5e1fc
--- /dev/null
+++ b/drivers/clk/clk-fixed-factor.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Standard functionality for the common clock API.
+ */
+#include <linux/module.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+struct clk_fixed_factor {
+	struct clk_hw	hw;
+	unsigned int	mult;
+	unsigned int	div;
+	char		*parent[1];
+};
+
+#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
+
+static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
+		unsigned long parent_rate)
+{
+	struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
+
+	return (parent_rate / fix->div) * fix->mult;
+}
+
+static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
+
+	if (prate) {
+		unsigned long best_parent;
+		best_parent = (rate / fix->mult) * fix->div;
+		*prate = __clk_round_rate(__clk_get_parent(hw->clk),
+				best_parent);
+		return (*prate / fix->div) * fix->mult;
+	} else {
+		return (__clk_get_rate(__clk_get_parent(hw->clk)) / fix->div) * fix->mult;
+	}
+}
+
+static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate)
+{
+	return 0;
+}
+
+struct clk_ops clk_fixed_factor_ops = {
+	.round_rate = clk_factor_round_rate,
+	.set_rate = clk_factor_set_rate,
+	.recalc_rate = clk_factor_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
+
+struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		unsigned int mult, unsigned int div)
+{
+	struct clk_fixed_factor *fix;
+	struct clk *clk;
+
+	fix = kmalloc(sizeof(struct clk_gate), GFP_KERNEL);
+
+	if (!fix) {
+		pr_err("%s: could not allocate gated clk\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* struct clk_gate assignments */
+	fix->mult = mult;
+	fix->div = div;
+
+	if (parent_name) {
+		fix->parent[0] = kstrdup(parent_name, GFP_KERNEL);
+		if (!fix->parent[0])
+			goto out;
+	}
+
+	clk = clk_register(dev, name,
+			&clk_fixed_factor_ops, &fix->hw,
+			fix->parent,
+			(parent_name ? 1 : 0),
+			flags);
+	if (clk)
+		return clk;
+
+out:
+	kfree(fix->parent[0]);
+	kfree(fix);
+
+	return NULL;
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5508897..21ca2f8 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -257,6 +257,10 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_mux_flags, spinlock_t *lock);
 
+struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		unsigned int mult, unsigned int div);
+
 /**
  * clk_register - allocate a new clock, register it and return an opaque cookie
  * @dev: device that is registering this clock
-- 
1.7.9.1



From s.hauer at pengutronix.de  Mon Mar 19 09:36:05 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 14:36:05 +0100
Subject: [PATCH 7/8] ARM i.MX25: implement clocks using common clock framework
In-Reply-To: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1332164166-6055-8-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig     |    1 +
 arch/arm/mach-imx/Makefile    |    2 +-
 arch/arm/mach-imx/clk-imx25.c |  242 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 244 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-imx/clk-imx25.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 8b4b4e3..4623865 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -59,6 +59,7 @@ config SOC_IMX25
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V2
 	select ARCH_MXC_IOMUX_V3
+	select COMMON_CLK
 	select MXC_AVIC
 
 config SOC_IMX27
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0a0bd05..d96e2ce 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -3,7 +3,7 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
 obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
 
-obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
+obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
 
 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
 obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
new file mode 100644
index 0000000..d617b14
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright 2012 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+#include "clk.h"
+
+#define CRM_BASE	MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
+
+#define CCM_MPCTL	0x00
+#define CCM_UPCTL	0x04
+#define CCM_CCTL	0x08
+#define CCM_CGCR0	0x0C
+#define CCM_CGCR1	0x10
+#define CCM_CGCR2	0x14
+#define CCM_PCDR0	0x18
+#define CCM_PCDR1	0x1C
+#define CCM_PCDR2	0x20
+#define CCM_PCDR3	0x24
+#define CCM_RCSR	0x28
+#define CCM_CRDR	0x2C
+#define CCM_DCVR0	0x30
+#define CCM_DCVR1	0x34
+#define CCM_DCVR2	0x38
+#define CCM_DCVR3	0x3c
+#define CCM_LTR0	0x40
+#define CCM_LTR1	0x44
+#define CCM_LTR2	0x48
+#define CCM_LTR3	0x4c
+#define CCM_MCR		0x64
+
+#define ccm(x)	(CRM_BASE + (x))
+
+struct clkl {
+	struct clk_lookup lookup;
+	const char *clkname;
+};
+
+#define clkdev(d, n, c) \
+	{ \
+		.lookup.dev_id = d, \
+		.lookup.con_id = n, \
+		.clkname = c, \
+	},
+
+static struct clkl lookups[] = {
+	/* i.mx25 has the i.mx21 type uart */
+	clkdev("imx21-uart.0", "ipg", "uart1_ipg")
+	clkdev("imx21-uart.0", "per", "uart_ipg_per")
+	clkdev("imx21-uart.1", "ipg", "uart2_ipg")
+	clkdev("imx21-uart.1", "per", "uart_ipg_per")
+	clkdev("imx21-uart.2", "ipg", "uart3_ipg")
+	clkdev("imx21-uart.2", "per", "uart_ipg_per")
+	clkdev("imx21-uart.3", "ipg", "uart4_ipg")
+	clkdev("imx21-uart.3", "per", "uart_ipg_per")
+	clkdev("imx21-uart.4", "ipg", "uart5_ipg")
+	clkdev("imx21-uart.4", "per", "uart_ipg_per")
+	clkdev("imx-gpt.0", "ipg", "ipg")
+	clkdev("imx-gpt.0", "per", "gpt_ipg_per")
+	clkdev("mxc-ehci.0", NULL, "ipg")
+	clkdev("mxc-ehci.0", "ahb", "usbotg_ahb")
+	clkdev("mxc-ehci.0", "per", "usbdiv")
+	clkdev("mxc-ehci.1", NULL, "ipg")
+	clkdev("mxc-ehci.1", "ahb", "usbotg_ahb")
+	clkdev("mxc-ehci.1", "per", "usbdiv")
+	clkdev("mxc-ehci.2", NULL, "ipg")
+	clkdev("mxc-ehci.2", "ahb", "usbotg_ahb")
+	clkdev("mxc-ehci.2", "per", "usbdiv")
+	clkdev("fsl-usb2-udc", "ahb", "usbotg_ahb")
+	clkdev("fsl-usb2-udc", "per", "usbdiv")
+	clkdev("mxc_nand.0", NULL, "nfc_ipg_per")
+	/* i.mx25 has the i.mx35 type cspi */
+	clkdev("imx35-cspi.0", NULL, "cspi1_ipg")
+	clkdev("imx35-cspi.1", NULL, "cspi2_ipg")
+	clkdev("imx35-cspi.2", NULL, "cspi3_ipg")
+	clkdev("mxc_pwm.0", "ipg", "pwm1_ipg")
+	clkdev("mxc_pwm.0", "per", "per10")
+	clkdev("mxc_pwm.1", "ipg", "pwm1_ipg")
+	clkdev("mxc_pwm.1", "per", "per10")
+	clkdev("mxc_pwm.2", "ipg", "pwm1_ipg")
+	clkdev("mxc_pwm.2", "per", "per10")
+	clkdev("mxc_pwm.3", "ipg", "pwm1_ipg")
+	clkdev("mxc_pwm.3", "per", "per10")
+	clkdev("imx-keypad", NULL, "kpp_ipg")
+	clkdev("mx25-adc", NULL, "tsc_ipg")
+	clkdev("imx-i2c.0", NULL, "i2c_ipg_per")
+	clkdev("imx-i2c.1", NULL, "i2c_ipg_per")
+	clkdev("imx-i2c.2", NULL, "i2c_ipg_per")
+	clkdev("imx25-fec.0", "ipg", "fec_ipg")
+	clkdev("imx25-fec.0", "ahb", "fec_ahb")
+	clkdev("imxdi_rtc.0", NULL, "dryice_ipg")
+	clkdev("imx-fb.0", "per", "lcdc_ipg_per")
+	clkdev("imx-fb.0", "ipg", "lcdc_ipg")
+	clkdev("imx-fb.0", "ahb", "lcdc_ahb")
+	clkdev("imx2-wdt.0", NULL, "wdt_ipg")
+	clkdev("imx-ssi.0", "per", "ssi1_ipg_per")
+	clkdev("imx-ssi.0", "ipg", "ssi1_ipg")
+	clkdev("imx-ssi.1", "per", "ssi2_ipg_per")
+	clkdev("imx-ssi.1", "ipg", "ssi2_ipg")
+	clkdev("sdhci-esdhc-imx25.0", "per", "esdhc1_ipg_per")
+	clkdev("sdhci-esdhc-imx25.0", "ipg", "esdhc1_ipg")
+	clkdev("sdhci-esdhc-imx25.0", "ahb", "esdhc1_ahb")
+	clkdev("sdhci-esdhc-imx25.1", "per", "esdhc2_ipg_per")
+	clkdev("sdhci-esdhc-imx25.1", "ipg", "esdhc2_ipg")
+	clkdev("sdhci-esdhc-imx25.1", "ahb", "esdhc2_ahb")
+	clkdev("mx2-camera.0", "per", "csi_ipg_per")
+	clkdev("mx2-camera.0", "ipg", "csi_ipg")
+	clkdev("mx2-camera.0", "ahb", "csi_ahb")
+	clkdev(NULL, "audmux", "dummy")
+	clkdev("flexcan.0", NULL, "can1_ipg")
+	clkdev("flexcan.1", NULL, "can2_ipg")
+	/* i.mx25 has the i.mx35 type sdma */
+	clkdev("imx35-sdma", "ipg", "sdma_ipg")
+	clkdev("imx35-sdma", "ahb", "sdma_ahb")
+	clkdev(NULL, "iim", "iim_ipg")
+};
+
+static char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
+static char *per_sel_clks[] = { "ahb", "upll", };
+
+int __init mx25_clocks_init(void)
+{
+	int i;
+
+	imx_clk_fixed("dummy", 0);
+	imx_clk_fixed("osc", 24000000);
+	imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
+	imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
+	imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
+	imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
+	imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2);
+	imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2);
+	imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+	imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per3_sel", ccm(CCM_MCR), 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per4_sel", ccm(CCM_MCR), 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per5_sel", ccm(CCM_MCR), 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per6_sel", ccm(CCM_MCR), 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per7_sel", ccm(CCM_MCR), 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per8_sel", ccm(CCM_MCR), 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per9_sel", ccm(CCM_MCR), 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per10_sel", ccm(CCM_MCR), 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per11_sel", ccm(CCM_MCR), 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per12_sel", ccm(CCM_MCR), 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+	imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);
+	imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6);
+	imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6);
+	imx_clk_divider("per3", "per3_sel", ccm(CCM_PCDR0), 24, 6);
+	imx_clk_divider("per4", "per4_sel", ccm(CCM_PCDR1), 0, 6);
+	imx_clk_divider("per5", "per5_sel", ccm(CCM_PCDR1), 8, 6);
+	imx_clk_divider("per6", "per6_sel", ccm(CCM_PCDR1), 16, 6);
+	imx_clk_divider("per7", "per7_sel", ccm(CCM_PCDR1), 24, 6);
+	imx_clk_divider("per8", "per8_sel", ccm(CCM_PCDR2), 0, 6);
+	imx_clk_divider("per9", "per9_sel", ccm(CCM_PCDR2), 8, 6);
+	imx_clk_divider("per10", "per10_sel", ccm(CCM_PCDR2), 16, 6);
+	imx_clk_divider("per11", "per11_sel", ccm(CCM_PCDR2), 24, 6);
+	imx_clk_divider("per12", "per12_sel", ccm(CCM_PCDR3), 0, 6);
+	imx_clk_divider("per13", "per13_sel", ccm(CCM_PCDR3), 8, 6);
+	imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6);
+	imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6);
+	imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);
+	imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0),  3);
+	imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0),  4);
+	imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0),  5);
+	imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0),  6);
+	imx_clk_gate("lcdc_ipg_per", "per8", ccm(CCM_CGCR0),  7);
+	imx_clk_gate("nfc_ipg_per", "ipg_per", ccm(CCM_CGCR0),  8);
+	imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
+	imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
+	imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);
+	imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18);
+	imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21);
+	imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22);
+	imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23);
+	imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24);
+	imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26);
+	imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28);
+	imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1),  2);
+	imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1),  3);
+	imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1),  4);
+	imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1),  5);
+	imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1),  6);
+	imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1),  7);
+	imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1),  8);
+	imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13);
+	imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14);
+	imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15);
+	imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26);
+	imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28);
+	imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29);
+	imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31);
+	imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2),  0);
+	imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2),  1);
+	imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2),  2);
+	imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2),  6);
+	imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
+	imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
+	imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
+	imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14);
+	imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15);
+	imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16);
+	imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17);
+	imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18);
+	imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
+
+	for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+		struct clkl *l = &lookups[i];
+		l->lookup.clk = __clk_lookup(l->clkname);
+		clkdev_add(&l->lookup);
+	}
+
+	mxc_timer_init(NULL, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
+	return 0;
+}
-- 
1.7.9.1



From s.hauer at pengutronix.de  Mon Mar 19 09:36:04 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 14:36:04 +0100
Subject: [PATCH 6/8] ARM i.MX21: implement clocks using common clock framework
In-Reply-To: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1332164166-6055-7-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig     |    1 +
 arch/arm/mach-imx/Makefile    |    2 +-
 arch/arm/mach-imx/clk-imx21.c |  177 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 179 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-imx/clk-imx21.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4cd86fb..8b4b4e3 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -46,6 +46,7 @@ config SOC_IMX1
 config SOC_IMX21
 	bool
 	select MACH_MX21
+	select COMMON_CLK
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
 	select IMX_HAVE_DMA_V1
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index cec4843..0a0bd05 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,7 +1,7 @@
 obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 
 obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
-obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
+obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
 
 obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
 
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
new file mode 100644
index 0000000..0807965
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2012 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include "clk.h"
+
+#define IO_ADDR_CCM(off)	(MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
+
+/* Register offsets */
+#define CCM_CSCR		IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0		IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1		IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0		IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1		IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL		IO_ADDR_CCM(0x14)
+#define CCM_PCDR0		IO_ADDR_CCM(0x18)
+#define CCM_PCDR1		IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0		IO_ADDR_CCM(0x20)
+#define CCM_PCCR1		IO_ADDR_CCM(0x24)
+#define CCM_CCSR		IO_ADDR_CCM(0x28)
+#define CCM_PMCTL		IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT		IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL		IO_ADDR_CCM(0x34)
+
+static char *mpll_sel_clks[] = { "fpm", "ckih", };
+static char *spll_sel_clks[] = { "fpm", "ckih", };
+
+struct clkl {
+	struct clk_lookup lookup;
+	const char *clkname;
+};
+
+#define clkdev(d, n, c) \
+	{ \
+		.lookup.dev_id = d, \
+		.lookup.con_id = n, \
+		.clkname = c, \
+	},
+
+static struct clkl lookups[] = {
+	clkdev("imx21-uart.0", "per", "per1")
+	clkdev("imx21-uart.0", "ipg", "uart1_ipg_gate")
+	clkdev("imx21-uart.1", "per", "per1")
+	clkdev("imx21-uart.1", "ipg", "uart2_ipg_gate")
+	clkdev("imx21-uart.2", "per", "per1")
+	clkdev("imx21-uart.2", "ipg", "uart3_ipg_gate")
+	clkdev("imx21-uart.3", "per", "per1")
+	clkdev("imx21-uart.3", "ipg", "uart4_ipg_gate")
+	clkdev("imx-gpt.0", "ipg", "gpt1_ipg_gate")
+	clkdev("imx-gpt.0", "per", "per1")
+	clkdev("imx-gpt.1", "ipg", "gpt2_ipg_gate")
+	clkdev("imx-gpt.1", "per", "per1")
+	clkdev("imx-gpt.2", "ipg", "gpt3_ipg_gate")
+	clkdev("imx-gpt.2", "per", "per1")
+	clkdev("mxc_pwm.0", "pwm", "pwm_ipg_gate")
+	clkdev("imx21-cspi.0", "per", "per2")
+	clkdev("imx21-cspi.0", "ipg", "cspi1_ipg_gate")
+	clkdev("imx21-cspi.1", "per", "per2")
+	clkdev("imx21-cspi.1", "ipg", "cspi2_ipg_gate")
+	clkdev("imx21-cspi.2", "per", "per2")
+	clkdev("imx21-cspi.2", "ipg", "cspi3_ipg_gate")
+	clkdev("imx-fb.0", "per", "per3")
+	clkdev("imx-fb.0", "ipg", "lcdc_ipg_gate")
+	clkdev("imx-fb.0", "ahb", "lcdc_hclk_gate")
+	clkdev("imx21-hcd.0", "per", "usb_gate")
+	clkdev("imx21-hcd.0", "ahb", "usb_hclk_gate")
+	clkdev("mxc_nand.0", NULL, "nfc_gate")
+	clkdev("imx-dma", "ahb", "dma_hclk_gate")
+	clkdev("imx-dma", "ipg", "dma_gate")
+	clkdev("imx2-wdt.0", NULL, "wdog_gate")
+	clkdev("imx-i2c.0", NULL, "i2c_gate")
+	clkdev("mxc-keypad", NULL, "kpp_gate")
+	clkdev("mxc_w1.0", NULL, "owire_gate")
+	clkdev(NULL, "brom", "brom_gate")
+	clkdev(NULL, "emma", "emma_gate")
+	clkdev(NULL, "slcdc", "slcdc_gate")
+	clkdev(NULL, "gpio", "gpio_gate")
+	clkdev(NULL, "rtc", "rtc_gate")
+	clkdev(NULL, "csi", "csi")
+	clkdev(NULL, "ssi1", "ssi1_gate")
+	clkdev(NULL, "ssi2", "ssi2_gate")
+	clkdev(NULL, "sdhc1", "sdhc1")
+	clkdev(NULL, "sdhc2", "sdhc2")
+};
+
+/*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+int __init mx21_clocks_init(unsigned long lref, unsigned long href)
+{
+	int i;
+
+	imx_clk_fixed("ckil", lref);
+	imx_clk_fixed("ckih", href);
+	imx_clk_fixed_factor("fpm", "ckil", 512, 1);
+	imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
+	imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));
+	imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
+	imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
+	imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
+	imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
+	imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
+	imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
+	imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
+	imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
+	imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
+	imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
+	imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
+	imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
+	imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
+	imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
+	imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
+	imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
+	imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
+	imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
+	imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
+	imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
+	imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
+	imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
+	imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
+	imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
+	imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
+	imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
+	imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
+	imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
+	imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
+	imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
+	imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
+	imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
+	imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
+	imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
+	imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
+	imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
+	imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
+	imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
+	imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
+	imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
+	imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
+	imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
+	imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
+	imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
+	imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
+	imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
+
+	for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+		struct clkl *l = &lookups[i];
+		l->lookup.clk = __clk_lookup(l->clkname);
+		clkdev_add(&l->lookup);
+	}
+
+	mxc_timer_init(NULL, MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
+			MX21_INT_GPT1);
+	return 0;
+}
-- 
1.7.9.1



From s.hauer at pengutronix.de  Mon Mar 19 09:36:00 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 14:36:00 +0100
Subject: [PATCH 2/8] ARM i.MX: prepare for common clock framework
In-Reply-To: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1332164166-6055-3-git-send-email-s.hauer@pengutronix.de>

- Add necessary #ifdefs for CONFIG_COMMON_CLOCK
- Add a global spinlock to protect the CCM registers

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/clk.h                |   44 ++++++++++++++++++++++++++++++++
 arch/arm/plat-mxc/clock.c              |   11 ++++++++
 arch/arm/plat-mxc/include/mach/clock.h |    4 +++
 3 files changed, 59 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-imx/clk.h

diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
new file mode 100644
index 0000000..2f1a7b2
--- /dev/null
+++ b/arch/arm/mach-imx/clk.h
@@ -0,0 +1,44 @@
+#ifndef __MACH_IMX_CLK_H
+#define __MACH_IMX_CLK_H
+
+#include <linux/spinlock.h>
+#include <linux/clk-provider.h>
+#include <mach/clock.h>
+
+struct clk *imx_clk_pllv1(const char *name, char *parent,
+		void __iomem *base);
+
+static inline struct clk *imx_clk_fixed(const char *name, int rate)
+{
+	return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+}
+
+static inline struct clk *imx_clk_divider(const char *name, const char *parent,
+		void __iomem *reg, u8 shift, u8 width)
+{
+	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+			reg, shift, width, 0, &imx_ccm_lock);
+}
+
+static inline struct clk *imx_clk_gate(const char *name, const char *parent,
+		void __iomem *reg, u8 shift)
+{
+	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+			shift, 0, &imx_ccm_lock);
+}
+
+static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
+		u8 shift, u8 width, char **parents, int num_parents)
+{
+	return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
+			width, 0, &imx_ccm_lock);
+}
+
+static inline struct clk *imx_clk_fixed_factor(const char *name,
+		const char *parent, unsigned int mult, unsigned int div)
+{
+	return clk_register_fixed_factor(NULL, name, parent,
+			CLK_SET_RATE_PARENT, mult, div);
+}
+
+#endif
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 2ed3ab1..5079787 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -41,6 +41,7 @@
 #include <mach/clock.h>
 #include <mach/hardware.h>
 
+#ifndef CONFIG_COMMON_CLK
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
 
@@ -200,6 +201,16 @@ struct clk *clk_get_parent(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_parent);
 
+#else
+
+/*
+ * Lock to protect the clock module (ccm) registers. Used
+ * on all i.MXs
+ */
+DEFINE_SPINLOCK(imx_ccm_lock);
+
+#endif /* CONFIG_COMMON_CLK */
+
 /*
  * Get the resulting clock rate from a PLL register value and the input
  * frequency. PLLs with this register layout can at least be found on
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 753a598..bd940c7 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -23,6 +23,7 @@
 #ifndef __ASSEMBLY__
 #include <linux/list.h>
 
+#ifndef CONFIG_COMMON_CLK
 struct module;
 
 struct clk {
@@ -59,6 +60,9 @@ struct clk {
 
 int clk_register(struct clk *clk);
 void clk_unregister(struct clk *clk);
+#endif /* CONFIG_COMMON_CLK */
+
+extern spinlock_t imx_ccm_lock;
 
 unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
 
-- 
1.7.9.1



From s.hauer at pengutronix.de  Mon Mar 19 09:36:03 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 14:36:03 +0100
Subject: [PATCH 5/8] ARM i.MX1: implement clocks using common clock framework
In-Reply-To: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1332164166-6055-6-git-send-email-s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig    |    1 +
 arch/arm/mach-imx/Makefile   |    2 +-
 arch/arm/mach-imx/clk-imx1.c |  118 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 120 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-imx/clk-imx1.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4defb97..4cd86fb 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -37,6 +37,7 @@ config ARCH_MX53
 config SOC_IMX1
 	bool
 	select ARCH_MX1
+	select COMMON_CLK
 	select CPU_ARM920T
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 1f138ae..cec4843 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,6 +1,6 @@
 obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 
-obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
+obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
 obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
 
 obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
new file mode 100644
index 0000000..b9b8589
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2012 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include "clk.h"
+
+/* CCM register addresses */
+#define IO_ADDR_CCM(off)	(MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
+
+#define CCM_CSCR	IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0	IO_ADDR_CCM(0x4)
+#define CCM_SPCTL0	IO_ADDR_CCM(0xc)
+#define CCM_PCDR	IO_ADDR_CCM(0x20)
+
+/* SCM register addresses */
+#define IO_ADDR_SCM(off)	(MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
+
+#define SCM_GCCR	IO_ADDR_SCM(0xc)
+
+struct clkl {
+	struct clk_lookup lookup;
+	const char *clkname;
+};
+
+#define clkdev(d, n, c) \
+	{ \
+		.lookup.dev_id = d, \
+		.lookup.con_id = n, \
+		.clkname = c, \
+	},
+
+static struct clkl lookups[] = {
+	clkdev(NULL, "dma", "dma_gate")
+	clkdev("mx1-camera.0", NULL, "csi_gate")
+	clkdev(NULL, "mma", "mma_gate")
+	clkdev("imx_udc.0", NULL, "usbd_gate")
+	clkdev("imx-gpt.0", "per", "per1")
+	clkdev("imx1-uart.0", "per", "per1")
+	clkdev("imx1-uart.0", "ipg", "hclk")
+	clkdev("imx1-uart.1", "per", "per1")
+	clkdev("imx1-uart.1", "ipg", "hclk")
+	clkdev("imx1-uart.2", "per", "per1")
+	clkdev("imx1-uart.2", "ipg", "hclk")
+	clkdev("imx-i2c.0", NULL, "hclk")
+	clkdev("imx1-cspi.0", "per", "per2")
+	clkdev("imx1-cspi.0", "ipg", "dummy")
+	clkdev("imx1-cspi.1", "per", "per2")
+	clkdev("imx1-cspi.1", "ipg", "dummy")
+	clkdev("imx-mmc.0", NULL, "per2")
+	clkdev("imx-fb.0", "per", "per2")
+	clkdev("imx-fb.0", "ipg", "dummy")
+	clkdev("imx-fb.0", "ahb", "dummy")
+	clkdev(NULL, "mshc", "hclk")
+	clkdev(NULL, "ssi", "per3")
+	clkdev("mxc_rtc.0", NULL, "clk32")
+	clkdev(NULL, "clko", "clko")
+};
+
+static char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
+static char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem",
+				"fclk", };
+
+int __init mx1_clocks_init(unsigned long fref)
+{
+	int i;
+
+	imx_clk_fixed("dummy", 0);
+	imx_clk_fixed("clk32", fref);
+	imx_clk_fixed("clk16m_ext", 16000000);
+	imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
+	imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
+	imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks));
+	imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
+	imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
+	imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
+	imx_clk_divider("fclk", "mpll", CCM_CSCR, 15, 1);
+	imx_clk_divider("hclk", "spll", CCM_CSCR, 10, 4);
+	imx_clk_divider("clk48m", "spll", CCM_CSCR, 26, 3);
+	imx_clk_divider("per1", "spll", CCM_PCDR, 0, 4);
+	imx_clk_divider("per2", "spll", CCM_PCDR, 4, 4);
+	imx_clk_divider("per3", "spll", CCM_PCDR, 16, 7);
+	imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
+	imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 4);
+	imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
+	imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
+	imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
+
+	for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+		struct clkl *l = &lookups[i];
+		l->lookup.clk = __clk_lookup(l->clkname);
+		clkdev_add(&l->lookup);
+	}
+
+	mxc_timer_init(NULL, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
+			MX1_TIM1_INT);
+
+	return 0;
+}
-- 
1.7.9.1



From nicolas.ferre at atmel.com  Mon Mar 19 09:37:56 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 19 Mar 2012 14:37:56 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203182013.22790.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <20120317094059.7C2333E08E2@localhost> <201203182013.22790.arnd@arndb.de>
Message-ID: <4F6736B4.4090509@atmel.com>

On 03/18/2012 09:13 PM, Arnd Bergmann :
> On Saturday 17 March 2012, Grant Likely wrote:
>>> +static LIST_HEAD(of_dma_list);
>>> +
>>> +struct of_dma {
>>> +     struct list_head of_dma_controllers;
>>> +     struct device_node *of_node;
>>> +     int of_dma_n_cells;
>>> +     int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
>>> +};
>>
>> This _xlate is nearly useless as a generic API.  It solves the problem for
>> the specific case where the driver is hard-coded to know which DMA engine
>> to talk to, but since the returned data doesn't provide any context, it
>> isn't useful if there are multiple DMA controllers to choose from.
>>
>> The void *data pointer must be replaced with a typed structure so that
>> context can be returned.
> 
> I've read up a bit more on how the existing drivers use the filter
> functions, it seems there are multiple classes of them, the classes
> that I've encountered are:
> 
> 1. matches on chan->device pointer and/or chan_id

I have the impression that we are now talking about *channel* selection.
It is not the purpose of those helper functions. It is just to retrieve
a *request line* for a particular slave interface. The
selection/filtering of a channel is a different topic (that we can
address in the future).
Maybe some DMA controllers are able to handle several "request lines"
among several DMA controller instances. But I suspect that this case
should be handled in another place, before calling this API.

>    (8 drivers)
> 2. will match anything
>    (6 drivers)
> 3. requires specific dma engine driver, then behaves like 1 or 2
>    (8 drivers, almost all freescale)
> 4. one of a kind, matches resource name string or device->dev_id
>    (two drivers)
> 5. filter function and data both provided by platform code,
>    platform picks dmaengine driver.
>    (4 amba pl* drivers, used on ARM, ux500, ...)
> 
> The last category is interesting because here, the dmaengine
> driver (pl330, coh901318, sirf-dma, ste_dma40) provides the filter
> function while in the other cases that is provided by the device
> driver! Out of these, the ste_dma40 is special because it's the
> only one where the data is a complex data structure describing the
> constraints on the driver, while all others just find the right
> channel.
> 
> Some drivers also pass assign driver specific data to chan->private.
> 
> I would hope that we can all make them use something like
>      struct dma_channel *of_dma_request_channel(struct of_node*,
> 					int index, void *driver_data);
> with an appropriate common definition behind it. In the cases
> where the driver can just match anything, I'd assume that all
> channels are equal, so #dma-cells would be 0. For the ste_dma40,
> #dma-cells needs to cover all of stedma40_chan_cfg. In most
> other cases, #dma-cells can be 1 and just enumerate the channels,
> unless we want to simplify the cases that Russell mentioned where
> we want to keep a two stage mapping channel identifiers and physical
> channel numbers.
> 
> How about an implementation like this:?
> 
> typedef bool dma_filter_simple(struct dma_chan *chan, void *filter_param)
> {
> 	/* zero #dma-cells, accept anything */
> 	return true;
> }
> 
> struct dma_channel *of_dma_request_channel(struct of_node*, int index,
> 					dma_cap_mask_t *mask,
> 					void *driver_data)
> {
> 	struct of_phandle_args dma_spec;
> 	struct dma_device *device;
> 	struct dma_chan *chan = NULL;
> 	dma_filter_fn *filter;
> 
> 	ret = of_parse_phandle_with_args(np, "dma-request", "#dma-cells",
> 					 index, &dma_spec);

Well, this property handles "request lines" not "channels". So if we
move the selection/filtering of channels in DT, we may need to create a
new property of this purpose...


> 
> 	device = dma_find_device(dma_spec->np);
> 	if (!device)
> 		goto out;
> 
> 	if (dma_spec->args_count == 0)
> 		filter = dma_filter_simple;
> 	else
> 		filter = device->dma_dt_filter; /* new member */
> 
> 	chan = private_candidate(mask, device, filter, dma_spec->args);
> 
> 	if (chan && !chan->private)
> 		chan->private = driver_data;
> out:
> 	return chan;
> }
> 
> 	Arnd
> 


-- 
Nicolas Ferre


From broonie at opensource.wolfsonmicro.com  Mon Mar 19 09:56:54 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 19 Mar 2012 13:56:54 +0000
Subject: [PATCH v5 1/8] ASoC: fsl: separate SSI and DMA Kconfig options
In-Reply-To: <1331888204-27058-2-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120319135654.GD3130@opensource.wolfsonmicro.com>

On Fri, Mar 16, 2012 at 04:56:37PM +0800, Shawn Guo wrote:
> The fsl_ssi driver will possibly be shared between Freescale PowerPC
> and ARM/IMX families, so give it a separate Kconfig option.  Then
> fsl_ssi driver can possibly be selected independently from selecting
> PowerPC DMA based PCM driver.

Applied all, thanks for doing all this work!  They'll have to wait for
3.5 at this point sadly.
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From arnd at arndb.de  Mon Mar 19 10:06:34 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 14:06:34 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <4F6734DD.3020203@atmel.com>
References: <4F22DEF2.5000807@ti.com> <20120317094059.7C2333E08E2@localhost>
 <4F6734DD.3020203@atmel.com>
Message-ID: <201203191406.35064.arnd@arndb.de>

On Monday 19 March 2012, Nicolas Ferre wrote:
> > This _xlate is nearly useless as a generic API.  It solves the problem for
> > the specific case where the driver is hard-coded to know which DMA engine
> > to talk to, but since the returned data doesn't provide any context, it
> > isn't useful if there are multiple DMA controllers to choose from.
> 
> You mean, if there is no DMA controller phandle specified in the
> property? I think that it is not the purpose of this API to choose a DMA
> controller, Nor to provide a channel. The only purpose of this API is to
> give a HW request to be used by a DMA slave driver. This slave should
> already have a channel to use and a controller to talk to.

I don't think there is consensus on this point. I would expect that
the device driver requests the channel with the same operation as
passing the request data.

Contrast the two ways this is done in atmel-mci.c and mmci.c:

==== atmel ====
/* interface between platform and driver */
struct at_dma_slave {
        struct device           *dma_dev;
        dma_addr_t              tx_reg;
        dma_addr_t              rx_reg;
        enum at_dma_slave_width reg_width;
        u32                     cfg;
        u32                     ctrla;
};
struct mci_dma_data {
        struct at_dma_slave     sdata;
};
#define slave_data_ptr(s)       (&(s)->sdata)
#define find_slave_dev(s)       ((s)->sdata.dma_dev)

/* in atmel-mci.c */
static bool atmci_filter(struct dma_chan *chan, void *slave)
{
        struct mci_dma_data     *sl = slave;

        if (sl && find_slave_dev(sl) == chan->device->dev) {
                chan->private = slave_data_ptr(sl);
                return true;
        } else {
                return false;
        }
}
static bool atmci_configure_dma(struct atmel_mci *host)
{
	...
	host->dma.chan = dma_request_channel(mask, atmci_filter, pdata->dma_slave);
	...
}

==== mmci ====
/* in drivers/dma/ste_dma40.c, others in pl330.c, coh901318.c, ... */
bool stedma40_filter(struct dma_chan *chan, void *data)
{               
        struct stedma40_chan_cfg *info = data;
        struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
        int err;                
        
        err = d40_validate_conf(d40c, info);
        if (!err)
                d40c->dma_cfg = *info;
        d40c->configured = true;
        
        return err == 0;
}
EXPORT_SYMBOL(stedma40_filter);

/* in mmci.h */
struct mmci_platform_data {
	...
        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
        void *dma_rx_param;
        void *dma_tx_param;
};

/* in mmci.c */
static void __devinit mmci_dma_setup(struct mmci_host *host)
{
	...
        host->dma_rx_channel = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
	...
}

====

Whatever we come up with obviously needs to work with both drivers.
I think we will end up with something closer to the second one, except
that the dma parameters do not come from platform_data but from the
#dma-request property, which also identifies the controller and channel.

	Arnd


From nico at fluxnic.net  Mon Mar 19 10:10:52 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 19 Mar 2012 10:10:52 -0400 (EDT)
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
Message-ID: <alpine.LFD.2.02.1203191002350.24151@xanadu.home>

On Mon, 19 Mar 2012, Boojin Kim wrote:

> This patch uses LDRD/STRD that loads and stores data as DWORD unit
> for the copy of 8-words data.
> It brings better performance than LDRM/STRM that was used originally.
> 
> Signed-off-by: Boojin Kim <boojin.kim at samsung.com>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>

Firstly, you're breaking those CPUs without ldrd/strd support.

Secondly, you're breaking to_user/from_user copies when processor 
domains are not disabled.

Then, my question is why didn't you simply provide an alternative 
implementation of ldr8w/str8w using ldrd/strd instead of interleaving 
them?  Certainly that would have allowed you to benefit from SDRAM burst 
transfers which are typically aligned to d-cache lines, as well as 
locating the subs into the unavoidable result delay slot.

> ---
>  arch/arm/lib/copy_from_user.S |   14 +++++++++-----
>  arch/arm/lib/copy_template.S  |   10 ++++++----
>  arch/arm/lib/copy_to_user.S   |   13 +++++++++----
>  arch/arm/lib/memcpy.S         |   13 +++++++++----
>  4 files changed, 33 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
> index 66a477a..15d1e1c 100644
> --- a/arch/arm/lib/copy_from_user.S
> +++ b/arch/arm/lib/copy_from_user.S
> @@ -51,11 +51,6 @@
>  	ldr1w \ptr, \reg4, \abort
>  	.endm
> 
> -	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
> -	ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
> -	ldr4w \ptr, \reg5, \reg6, \reg7, \reg8, \abort
> -	.endm
> -
>  	.macro ldr1b ptr reg cond=al abort
>  	ldrusr	\reg, \ptr, 1, \cond, abort=\abort
>  	.endm
> @@ -68,6 +63,15 @@
>  	stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
>  	.endm
> 
> +	.macro cpy8w dst src reg1 reg2 abort
> +	.irp offset, #0, #8, #16, #24
> +	ldr1w \src, \reg1, \abort
> +	ldr1w \src, \reg2, \abort
> +	strd \reg1, \reg2, [\dst, \offset]
> +	.endr
> +	add \dst, \dst, #32
> +	.endm
> +
>  	.macro str1b ptr reg cond=al abort
>  	str\cond\()b \reg, [\ptr], #1
>  	.endm
> diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
> index 805e3f8..72640aa 100644
> --- a/arch/arm/lib/copy_template.S
> +++ b/arch/arm/lib/copy_template.S
> @@ -28,9 +28,8 @@
>   *	'ptr' to the next word. The 'abort' argument is used for fixup tables.
>   *
>   * ldr4w ptr reg1 reg2 reg3 reg4 abort
> - * ldr8w ptr, reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
>   *
> - *	This loads four or eight words starting from 'ptr', stores them
> + *	This loads eight words starting from 'ptr', stores them
>   *	in provided registers and increments 'ptr' past those words.
>   *	The'abort' argument is used for fixup tables.
>   *
> @@ -47,6 +46,10 @@
>   *	Same as their ldr* counterparts, but data is stored to 'ptr' location
>   *	rather than being loaded.
>   *
> + * cpy8w src dst reg1 reg2 abort
> + *	This loads eight words starting from 'src' and stores them to 'dst'.
> + *	The 'abort' argument is used for fixup tables.
> + *
>   * enter reg1 reg2
>   *
>   *	Preserve the provided registers on the stack plus any additional
> @@ -97,9 +100,8 @@
>  	PLD(	pld	[r1, #92]		)
> 
>  3:	PLD(	pld	[r1, #124]		)
> -4:		ldr8w	r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> +4:		cpy8w   r0, r1, r4, r5, abort=20f
>  		subs	r2, r2, #32
> -		str8w	r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
>  		bge	3b
>  	PLD(	cmn	r2, #96			)
>  	PLD(	bge	4b			)
> diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
> index d066df6..9402a08 100644
> --- a/arch/arm/lib/copy_to_user.S
> +++ b/arch/arm/lib/copy_to_user.S
> @@ -48,10 +48,6 @@
>  	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
>  	.endm
> 
> -	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
> -	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
> -	.endm
> -
>  	.macro ldr1b ptr reg cond=al abort
>  	ldr\cond\()b \reg, [\ptr], #1
>  	.endm
> @@ -71,6 +67,15 @@
>  	str1w \ptr, \reg8, \abort
>  	.endm
> 
> +	.macro cpy8w dst src reg1 reg2 abort
> +	.irp offset, #0, #8, #16, #24
> +	ldrd \reg1, \reg2, [\src, \offset]
> +	str1w \dst, \reg1, \abort
> +	str1w \dst, \reg2, \abort
> +	.endr
> +	add \src, \src, #32
> +	.endm
> +
>  	.macro str1b ptr reg cond=al abort
>  	strusr	\reg, \ptr, 1, \cond, abort=\abort
>  	.endm
> diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
> index a9b9e22..25320c9 100644
> --- a/arch/arm/lib/memcpy.S
> +++ b/arch/arm/lib/memcpy.S
> @@ -24,10 +24,6 @@
>  	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
>  	.endm
> 
> -	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
> -	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
> -	.endm
> -
>  	.macro ldr1b ptr reg cond=al abort
>  	ldr\cond\()b \reg, [\ptr], #1
>  	.endm
> @@ -40,6 +36,15 @@
>  	stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
>  	.endm
> 
> +	.macro cpy8w dst src reg1 reg2 abort
> +	.irp offset, #0, #8, #16, #24
> +	ldrd \reg1, \reg2, [\src, \offset]
> +	strd \reg1, \reg2, [\dst, \offset]
> +	.endr
> +	add \src, \src, #32
> +	add \dst, \dst, #32
> +	.endm
> +
>  	.macro str1b ptr reg cond=al abort
>  	str\cond\()b \reg, [\ptr], #1
>  	.endm
> --
> 1.7.1
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


From shawn.guo at linaro.org  Mon Mar 19 10:23:29 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 19 Mar 2012 22:23:29 +0800
Subject: [PATCH 8/8] ARM i.MX27: implement clocks using common clock
 framework
In-Reply-To: <1332164166-6055-9-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
 <1332164166-6055-9-git-send-email-s.hauer@pengutronix.de>
Message-ID: <20120319142325.GA32469@S2101-09.ap.freescale.net>

On Mon, Mar 19, 2012 at 02:36:06PM +0100, Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> ---
>  arch/arm/mach-imx/Kconfig     |    1 +
>  arch/arm/mach-imx/Makefile    |    2 +-
>  arch/arm/mach-imx/clk-imx27.c |  277 +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 279 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-imx/clk-imx27.c
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 4623865..bbef3d0 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -65,6 +65,7 @@ config SOC_IMX25
>  config SOC_IMX27
>  	bool
>  	select MACH_MX27
> +	select COMMON_CLK
>  	select CPU_ARM926T
>  	select ARCH_MXC_AUDMUX_V1
>  	select IMX_HAVE_DMA_V1
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index d96e2ce..b39f2d6 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -6,7 +6,7 @@ obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
>  obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
>  
>  obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
> -obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
> +obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
>  
>  obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
>  obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
> diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
> new file mode 100644
> index 0000000..e44e70e
> --- /dev/null
> +++ b/arch/arm/mach-imx/clk-imx27.c
> @@ -0,0 +1,277 @@
> +/*
> + * Copyright 2012 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation.
> + */
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/clkdev.h>
> +#include <linux/err.h>
> +#include <linux/clk-provider.h>
> +
> +#include <mach/common.h>
> +#include <mach/hardware.h>
> +
> +#include "clk.h"
> +
> +#define IO_ADDR_CCM(off)	(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
> +
> +/* Register offsets */
> +#define CCM_CSCR		IO_ADDR_CCM(0x0)
> +#define CCM_MPCTL0		IO_ADDR_CCM(0x4)
> +#define CCM_MPCTL1		IO_ADDR_CCM(0x8)
> +#define CCM_SPCTL0		IO_ADDR_CCM(0xc)
> +#define CCM_SPCTL1		IO_ADDR_CCM(0x10)
> +#define CCM_OSC26MCTL		IO_ADDR_CCM(0x14)
> +#define CCM_PCDR0		IO_ADDR_CCM(0x18)
> +#define CCM_PCDR1		IO_ADDR_CCM(0x1c)
> +#define CCM_PCCR0		IO_ADDR_CCM(0x20)
> +#define CCM_PCCR1		IO_ADDR_CCM(0x24)
> +#define CCM_CCSR		IO_ADDR_CCM(0x28)
> +#define CCM_PMCTL		IO_ADDR_CCM(0x2c)
> +#define CCM_PMCOUNT		IO_ADDR_CCM(0x30)
> +#define CCM_WKGDCTL		IO_ADDR_CCM(0x34)
> +
> +#define CCM_CSCR_UPDATE_DIS	(1 << 31)
> +#define CCM_CSCR_SSI2		(1 << 23)
> +#define CCM_CSCR_SSI1		(1 << 22)
> +#define CCM_CSCR_VPU		(1 << 21)
> +#define CCM_CSCR_MSHC           (1 << 20)
> +#define CCM_CSCR_SPLLRES        (1 << 19)
> +#define CCM_CSCR_MPLLRES        (1 << 18)
> +#define CCM_CSCR_SP             (1 << 17)
> +#define CCM_CSCR_MCU            (1 << 16)
> +#define CCM_CSCR_OSC26MDIV      (1 << 4)
> +#define CCM_CSCR_OSC26M         (1 << 3)
> +#define CCM_CSCR_FPM            (1 << 2)
> +#define CCM_CSCR_SPEN           (1 << 1)
> +#define CCM_CSCR_MPEN           (1 << 0)
> +
> +/* i.MX27 TO 2+ */
> +#define CCM_CSCR_ARM_SRC        (1 << 15)
> +
> +#define CCM_SPCTL1_LF           (1 << 15)
> +#define CCM_SPCTL1_BRMO         (1 << 6)
> +
> +struct clkl {
> +	struct clk_lookup lookup;
> +	const char *clkname;
> +};
> +
> +#define clkdev(d, n, c) \
> +	{ \
> +		.lookup.dev_id = d, \
> +		.lookup.con_id = n, \
> +		.clkname = c, \
> +	},
> +

They should at least be defined in arch/arm/mach-imx/clk.h to avoid
the duplication in every single imx clock driver.

If using registration function becomes the common way that clock
driver registers clks, they will be needed by other platforms too.
Then, we should probably do something like below instead?

diff --git a/include/linux/clkdev.h b/include/linux/clkdev.h
index d9a4fd0..2cde34e 100644
--- a/include/linux/clkdev.h
+++ b/include/linux/clkdev.h
@@ -21,6 +21,7 @@ struct clk_lookup {
        struct list_head        node;
        const char              *dev_id;
        const char              *con_id;
+       const char              *clk_name;
        struct clk              *clk;
 };

@@ -31,6 +32,13 @@ struct clk_lookup {
                .clk = c,       \
        }

+#define CLKDEV_INIT_N(d, n, cn)        \
+       {                       \
+               .dev_id = d,    \
+               .con_id = n,    \
+               .clk_name = cn, \
+       }
+
 struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
        const char *dev_fmt, ...);

> +static struct clkl lookups[] = {
> +	clkdev("imx21-uart.0", "ipg", "uart1_ipg_gate")
> +	clkdev("imx21-uart.0", "per", "per1_gate")
> +	clkdev("imx21-uart.1", "ipg", "uart2_ipg_gate")
> +	clkdev("imx21-uart.1", "per", "per1_gate")
> +	clkdev("imx21-uart.2", "ipg", "uart3_ipg_gate")
> +	clkdev("imx21-uart.2", "per", "per1_gate")
> +	clkdev("imx21-uart.3", "ipg", "uart4_ipg_gate")
> +	clkdev("imx21-uart.3", "per", "per1_gate")
> +	clkdev("imx21-uart.4", "ipg", "uart5_ipg_gate")
> +	clkdev("imx21-uart.4", "per", "per1_gate")
> +	clkdev("imx21-uart.5", "ipg", "uart6_ipg_gate")
> +	clkdev("imx21-uart.5", "per", "per1_gate")
> +	clkdev("imx-gpt.0", "ipg", "gpt1_ipg_gate")
> +	clkdev("imx-gpt.0", "per", "per1_gate")
> +	clkdev("imx-gpt.1", "ipg", "gpt2_ipg_gate")
> +	clkdev("imx-gpt.1", "per", "per1_gate")
> +	clkdev("imx-gpt.2", "ipg", "gpt3_ipg_gate")
> +	clkdev("imx-gpt.2", "per", "per1_gate")
> +	clkdev("imx-gpt.3", "ipg", "gpt4_ipg_gate")
> +	clkdev("imx-gpt.3", "per", "per1_gate")
> +	clkdev("imx-gpt.4", "ipg", "gpt5_ipg_gate")
> +	clkdev("imx-gpt.4", "per", "per1_gate")
> +	clkdev("imx-gpt.5", "ipg", "gpt6_ipg_gate")
> +	clkdev("imx-gpt.5", "per", "per1_gate")
> +	clkdev("mxc_pwm.0", NULL, "pwm")
> +	clkdev("mxc-mmc.0", "per", "per2_gate")
> +	clkdev("mxc-mmc.0", "ipg", "sdhc1_ipg_gate")
> +	clkdev("mxc-mmc.1", "per", "per2_gate")
> +	clkdev("mxc-mmc.1", "ipg", "sdhc2_ipg_gate")
> +	clkdev("mxc-mmc.2", "per", "per2_gate")
> +	clkdev("mxc-mmc.2", "ipg", "sdhc2_ipg_gate")
> +	clkdev("imx27-cspi.0", NULL, "cspi1")
> +	clkdev("imx27-cspi.1", NULL, "cspi2")
> +	clkdev("imx27-cspi.2", NULL, "cspi3")
> +	clkdev("imx-fb.0", "per", "per3_gate")
> +	clkdev("imx-fb.0", "ipg", "lcdc_ipg_gate")
> +	clkdev("imx-fb.0", "ahb", "lcdc_ahb_gate")
> +	clkdev("mx2-camera.0", NULL, "csi")
> +	clkdev("fsl-usb2-udc", "usb", "usb")
> +	clkdev("fsl-usb2-udc", "usb_ahb", "usb_ahb_gate")
> +	clkdev("mxc-ehci.0", "usb", "usb")
> +	clkdev("mxc-ehci.0", "usb_ahb", "usb_ahb_gate")
> +	clkdev("mxc-ehci.1", "usb", "usb")
> +	clkdev("mxc-ehci.1", "usb_ahb", "usb_ahb_gate")
> +	clkdev("mxc-ehci.2", "usb", "usb")
> +	clkdev("mxc-ehci.2", "usb_ahb", "usb_ahb_gate")
> +	clkdev("imx-ssi.0", NULL, "ssi1_ipg_gate")
> +	clkdev("imx-ssi.1", NULL, "ssi2_ipg_gate")
> +	clkdev("mxc_nand.0", NULL, "nfc_baud_gate")
> +	clkdev("imx-vpu", "per", "vpu_baud_gate")
> +	clkdev("imx-vpu", "ahb", "vpu_ahb_gate")
> +	clkdev("imx-dma", "ahb", "dma_ahb_gate")
> +	clkdev("imx-dma", "ipg", "dma_ipg_gate")
> +	clkdev("imx27-fec.0", "ipg", "fec_ipg_gate")
> +	clkdev("imx27-fec.0", "ahb", "fec_ahb_gate")
> +	clkdev("imx2-wdt.0", NULL, "wdog_ipg_gate")
> +	clkdev("imx-i2c.0", NULL, "i2c1_ipg_gate")
> +	clkdev("imx-i2c.1", NULL, "i2c2_ipg_gate")
> +	clkdev("mxc_w1.0", NULL, "owire_ipg_gate")
> +	clkdev("imx-keypad", NULL, "kpp_ipg_gate")
> +	clkdev("imx-emma", "ahb", "emma_ahb_gate")
> +	clkdev("imx-emma", "ipg", "emma_ipg_gate")
> +	clkdev(NULL, "iim", "iim_ipg_gate")
> +	clkdev(NULL, "gpio", "gpio_ipg_gate")
> +	clkdev(NULL, "brom", "brom_ahb_gate")
> +	clkdev(NULL, "ata", "ata_ahb_gate")
> +	clkdev(NULL, "rtc", "rtc_ipg_gate")
> +	clkdev(NULL, "scc", "scc_ipg_gate")
> +	clkdev(NULL, "cpu", "cpu_div")
> +	clkdev(NULL, "emi_ahb" , "emi_ahb_gate")
> +	clkdev("imx-ssi.0", "bitrate" , "ssi1_baud_gate")
> +	clkdev("imx-ssi.1", "bitrate" , "ssi2_baud_gate")
> +};
> +
> +static char *vpu_sel_clks[] = { "spll", "mpll_main2", };
> +static char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
> +static char *clko_sel_clks[] = {
> +	"ckil", "prem", "ckih", "ckih",
> +	"ckih", "mpll", "spll", "cpu_div",
> +	"ahb", "ipg", "per1_div", "per2_div",
> +	"per3_div", "per4_div", "ssi1_div", "ssi2_div",
> +	"nfc_div", "mshc_div", "vpu_div", "60m",
> +	"32k", "usb_div", "dptc",
> +};
> +
> +static char *ssi_sel_clks[] = { "spll", "mpll", };
> +
> +int __init mx27_clocks_init(unsigned long fref)
> +{
> +	int i;
> +	struct clk *emi_ahb;
> +
> +	imx_clk_fixed("dummy", 0);
> +	imx_clk_fixed("ckih", fref);
> +	imx_clk_fixed("ckil", 32768);
> +	imx_clk_pllv1("mpll", "ckih", CCM_MPCTL0);
> +	imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
> +	imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
> +
> +	if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
> +		imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
> +		imx_clk_fixed_factor("ipg", "ahb", 1, 2);
> +	} else {
> +		imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
> +		imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
> +	}
> +
> +	imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
> +	imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
> +	imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
> +	imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
> +	imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
> +	imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
> +	imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 3);
> +	imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
> +	imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
> +	imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
> +	if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
> +		imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
> +	else
> +		imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
> +	imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
> +	imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
> +	imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
> +	imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
> +	imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 3);
> +	imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
> +	imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
> +	imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
> +	imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
> +	imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
> +	imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
> +	imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
> +	imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
> +	imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
> +	imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
> +	imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
> +	imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
> +	imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
> +	imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
> +	imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
> +	imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
> +	imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
> +	imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
> +	imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
> +	imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
> +	imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
> +	imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
> +	imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
> +	imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
> +	imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
> +	imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
> +	imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
> +	imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
> +	imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
> +	imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
> +	imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
> +	imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1,  4);
> +	imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1,  5);
> +	imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1,  6);
> +	imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1,  7);
> +	imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1,  8);
> +	imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1,  9);
> +	imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
> +	imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
> +	imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
> +	imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
> +	imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
> +	imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
> +	imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
> +	imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
> +	emi_ahb = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
> +	imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
> +	imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
> +	imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
> +	imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
> +	imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
> +	imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
> +	imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
> +	imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
> +	imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
> +	imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
> +	imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
> +	imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
> +
> +	for (i = 0; i < ARRAY_SIZE(lookups); i++) {
> +		struct clkl *l = &lookups[i];
> +		l->lookup.clk = __clk_lookup(l->clkname);

That's somehow unfortunate this expensive function needs to be called
to retrieve these clks, while those registration functions should ever
have them returned.

> +		clkdev_add(&l->lookup);
> +	}
> +
> +	mxc_timer_init(NULL, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
> +			MX27_INT_GPT1);
> +
> +	clk_prepare_enable(emi_ahb);
> +
> +	return 0;
> +}
> -- 
> 1.7.9.1
> 

-- 
Regards,
Shawn


From b-cousson at ti.com  Mon Mar 19 10:23:14 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 19 Mar 2012 15:23:14 +0100
Subject: [PATCH 01/12] mfd: twl-core: don't depend on pdata->irq_base/end
In-Reply-To: <87k42metna.fsf@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-2-git-send-email-b-cousson@ti.com> <87pqcegapk.fsf@ti.com>
 <87k42metna.fsf@ti.com>
Message-ID: <4F674152.5040008@ti.com>

Samuel,

On 3/14/2012 10:53 PM, Kevin Hilman wrote:
> Kevin Hilman<khilman at ti.com>  writes:
>
>> Benoit Cousson<b-cousson at ti.com>  writes:
>>
>>> From: Felipe Balbi<balbi at ti.com>
>>>
>>> With sparse IRQs the driver shouldn't depend at all on
>>> any IRQ values coming from board-file.
>>>
>>> Remove every occurences of pdata->irq_base/end.
>>
>> Well, not quite *every*. :)
>>
>> If the driver isn't going to use those fields anymore, they should also
>> be removed from the pdata struct too[1].  Also, the remaining board/init
>> code that is initializing those fields should be removed as well[2], since
>> it obviously has no effect.
>>
>> The first patch below should probably be folded into this one, and then
>> the 2nd patch removes all the users.
>
> Below is a correct version of the 2nd patch which removes all the users.
>
> The previous version wouldn't apply cleanly because I generated it on
> top of a local branch that also included some other changes to
> twl-common.c from the SMPS regulator series (which seems to have missed
> the window for v3.4.)
>
> This one applies cleanly on your for_3.4/twl_irq_gpio_mmc_fix branch.

After discussing with Kevin, we think it might be better to wait 3.5 for 
this further cleanup patches.
These patches will need some patches already queued by Tony to avoid 
breaking OMAP build.
In order to reduce dependency, let's push them for 3.5.

You can the pull the current branch.

Thanks,
Benoit

>
> Kevin
>
>  From b59a4754fb66f6f729ebbd0563c4cd2bd2cda56e Mon Sep 17 00:00:00 2001
> From: Kevin Hilman<khilman at ti.com>
> Date: Wed, 14 Mar 2012 13:56:01 -0700
> Subject: [PATCH] ARM: OMAP2+: TWL: remove usage of pdata->irq_base/_end
>
> The driver has been converted to use SPARSE_IRQ and no longer needs to
> be passed IRQ base/end.  The driver no longer uses these fields, so
> remove them from the reamaining users.
>
> Signed-off-by: Kevin Hilman<khilman at ti.com>
> ---
>   arch/arm/mach-omap2/board-2430sdp.c    |    3 ---
>   arch/arm/mach-omap2/board-omap3logic.c |    3 ---
>   arch/arm/mach-omap2/twl-common.c       |   10 ----------
>   3 files changed, 16 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
> index 7370983..7dfcb96 100644
> --- a/arch/arm/mach-omap2/board-2430sdp.c
> +++ b/arch/arm/mach-omap2/board-2430sdp.c
> @@ -218,9 +218,6 @@ static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
>   };
>
>   static struct twl4030_platform_data sdp2430_twldata = {
> -	.irq_base	= TWL4030_IRQ_BASE,
> -	.irq_end	= TWL4030_IRQ_END,
> -
>   	/* platform_data for children goes here */
>   	.gpio		=&sdp2430_gpio_data,
>   	.vmmc1		=&sdp2430_vmmc1,
> diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
> index 4198dd0..0b053b4 100644
> --- a/arch/arm/mach-omap2/board-omap3logic.c
> +++ b/arch/arm/mach-omap2/board-omap3logic.c
> @@ -85,9 +85,6 @@ static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
>   };
>
>   static struct twl4030_platform_data omap3logic_twldata = {
> -	.irq_base	= TWL4030_IRQ_BASE,
> -	.irq_end	= TWL4030_IRQ_END,
> -
>   	/* platform_data for children goes here */
>   	.gpio		=&omap3logic_gpio_data,
>   	.vmmc1		=&omap3logic_vmmc1,
> diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
> index 10b20c6..ce349ac 100644
> --- a/arch/arm/mach-omap2/twl-common.c
> +++ b/arch/arm/mach-omap2/twl-common.c
> @@ -129,11 +129,6 @@ static struct regulator_init_data omap3_vpll2_idata = {
>   void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
>   				  u32 pdata_flags, u32 regulators_flags)
>   {
> -	if (!pmic_data->irq_base)
> -		pmic_data->irq_base = TWL4030_IRQ_BASE;
> -	if (!pmic_data->irq_end)
> -		pmic_data->irq_end = TWL4030_IRQ_END;
> -
>   	/* Common platform data configurations */
>   	if (pdata_flags&  TWL_COMMON_PDATA_USB&&  !pmic_data->usb)
>   		pmic_data->usb =&omap3_usb_pdata;
> @@ -287,11 +282,6 @@ static struct regulator_init_data omap4_clk32kg_idata = {
>   void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
>   				  u32 pdata_flags, u32 regulators_flags)
>   {
> -	if (!pmic_data->irq_base)
> -		pmic_data->irq_base = TWL6030_IRQ_BASE;
> -	if (!pmic_data->irq_end)
> -		pmic_data->irq_end = TWL6030_IRQ_END;
> -
>   	/* Common platform data configurations */
>   	if (pdata_flags&  TWL_COMMON_PDATA_USB&&  !pmic_data->usb)
>   		pmic_data->usb =&omap4_usb_pdata;



From vinod.koul at intel.com  Mon Mar 19 10:35:30 2012
From: vinod.koul at intel.com (Vinod Koul)
Date: Mon, 19 Mar 2012 20:05:30 +0530
Subject: [PATCH v2 0/9] DMA engine cookie handling cleanups
In-Reply-To: <1331649534.1727.27.camel@vkoul-udesk3>
References: <20120306223321.GD15201@n2100.arm.linux.org.uk>
 <1331128466.24656.421.camel@vkoul-udesk3>
 <20120312161143.GA10830@n2100.arm.linux.org.uk>
 <1331569438.1727.3.camel@vkoul-udesk3>
 <1331628036.1727.22.camel@vkoul-udesk3>
 <20120313123121.GA20133@n2100.arm.linux.org.uk>
 <1331649534.1727.27.camel@vkoul-udesk3>
Message-ID: <1332167730.7180.53.camel@vkoul-udesk3>

On Tue, 2012-03-13 at 20:08 +0530, Vinod Koul wrote:
> On Tue, 2012-03-13 at 12:31 +0000, Russell King - ARM Linux wrote:
> > On Tue, Mar 13, 2012 at 02:10:36PM +0530, Vinod Koul wrote:
> > > Please see if the below patch is the right fix for build failures in
> > > addition to one suggested by Jassi.
> > 
> > I'm not sure that Jassi's solution is correct - and I'm wondering whether
> > any of the DMA engine drivers do the right thing when transfers are
> > terminated.  Is it right for the DMA status function to return IN_PROGRESS
> > for a previously submitted cookie which has been terminated?
> > 
> > I can see two answers to that, both equally valid:
> > 
> > 1. It allows you to find out exactly where the DMA engine got to before
> >    the transfer was terminated, and therefore recover from the termination
> >    if you wish to.
> > 
> > 2. Returning in-progress when a cookie will never be completed is
> >    misleading, and could be misinterpreted by users of the tx_status
> >    function, especially if they are waiting for a particular transaction
> >    to complete.
> > 
> > Maybe we need to introduce a DMA_TERMINATED status?
> I would agree with you that DMA_TERMINATED seems to be correct option.
> IN_PROGRESS would certainly confuse... 
> I will drop Jassi's fix from this branch. Care to send the patch? 

Even after adding such a state in dmaengine for DMA_TERMINATED, it
doesn't make much sense. In TERMINATE_ALL we do not update the
chan->complete value. So after client has terminated the channel it can
easily test to see if cookie is completed (before terminate will return
SUCCESS) or aborted (will return DMA_IN_PROGRESS)
So at present I am leaning on 1 :)

If I don't hear any opposition I will merge this (with Jassi's fix) and
then send pull to Linus

-- 
~Vinod



From s.hauer at pengutronix.de  Mon Mar 19 10:36:08 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 15:36:08 +0100
Subject: [PATCH 8/8] ARM i.MX27: implement clocks using common clock
 framework
In-Reply-To: <20120319142325.GA32469@S2101-09.ap.freescale.net>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
 <1332164166-6055-9-git-send-email-s.hauer@pengutronix.de>
 <20120319142325.GA32469@S2101-09.ap.freescale.net>
Message-ID: <20120319143608.GZ3852@pengutronix.de>

On Mon, Mar 19, 2012 at 10:23:29PM +0800, Shawn Guo wrote:
> > +
> > +struct clkl {
> > +	struct clk_lookup lookup;
> > +	const char *clkname;
> > +};
> > +
> > +#define clkdev(d, n, c) \
> > +	{ \
> > +		.lookup.dev_id = d, \
> > +		.lookup.con_id = n, \
> > +		.clkname = c, \
> > +	},
> > +
> 
> They should at least be defined in arch/arm/mach-imx/clk.h to avoid
> the duplication in every single imx clock driver.

Yes, right. See it as a quick-n-dirty solution...

> 
> If using registration function becomes the common way that clock
> driver registers clks, they will be needed by other platforms too.
> Then, we should probably do something like below instead?
> 
> diff --git a/include/linux/clkdev.h b/include/linux/clkdev.h
> index d9a4fd0..2cde34e 100644
> --- a/include/linux/clkdev.h
> +++ b/include/linux/clkdev.h
> @@ -21,6 +21,7 @@ struct clk_lookup {
>         struct list_head        node;
>         const char              *dev_id;
>         const char              *con_id;
> +       const char              *clk_name;
>         struct clk              *clk;
>  };
> 
> @@ -31,6 +32,13 @@ struct clk_lookup {
>                 .clk = c,       \
>         }
> 
> +#define CLKDEV_INIT_N(d, n, cn)        \
> +       {                       \
> +               .dev_id = d,    \
> +               .con_id = n,    \
> +               .clk_name = cn, \
> +       }
> +

...until something better is found. Adding the clock name to clk_lookup
seems like a good start.

> > +	imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
> > +	imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
> > +	imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
> > +
> > +	for (i = 0; i < ARRAY_SIZE(lookups); i++) {
> > +		struct clkl *l = &lookups[i];
> > +		l->lookup.clk = __clk_lookup(l->clkname);
> 
> That's somehow unfortunate this expensive function needs to be called
> to retrieve these clks, while those registration functions should ever
> have them returned.

I wanted to avoid having 'clkbla =' before every initializer. Maybe we
can skip struct clk from struct clk_lookup and only keep the name.
__clk_lookup could then be called in clk_get. This way looking up the
clock would be done when a clock is requested and we wouldn't do it
all at once and wouldn't add delays to the boot process.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From robherring2 at gmail.com  Mon Mar 19 10:36:41 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 19 Mar 2012 09:36:41 -0500
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <20120319085503.GL15988@n2100.arm.linux.org.uk>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <20120319085503.GL15988@n2100.arm.linux.org.uk>
Message-ID: <4F674479.8090101@gmail.com>

On 03/19/2012 03:55 AM, Russell King - ARM Linux wrote:
> On Mon, Mar 19, 2012 at 04:02:48PM +0900, Boojin Kim wrote:
>> This patch uses LDRD/STRD that loads and stores data as DWORD unit
>> for the copy of 8-words data.
>> It brings better performance than LDRM/STRM that was used originally.
> 
> And what about CPUs that don't have ldrd/strd ?
> 

And what about CPUs that do have ldrd/strd but is slower than ldm/stm?
I'm pretty sure that is almost everything currently out there.

Rob


From robherring2 at gmail.com  Mon Mar 19 10:44:41 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 19 Mar 2012 09:44:41 -0500
Subject: i.MX: Convert v4/v5 based SoCs to common clock framework
In-Reply-To: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
Message-ID: <4F674659.40207@gmail.com>

On 03/19/2012 08:35 AM, Sascha Hauer wrote:
> Hi All,
> 
> The following patches convert the i.MX v4/v5 based SoCs to the common
> clock framework.  They may not be completely ready, I am posting it now
> because I'd like to show that the function based clock initializers are
> indeed usable in real life and that the end result does not look too
> bad.
> 
> This series depends on another series not yet posted which convert the
> i.MX drivers to not depend on grouped clocks. I will follow up on this
> after the merge window. My plan for these patches is to put them into
> the arm-soc staging area after the merge window to let them stabilize
> until hopefully before the next merge window there are no regressions
> left.
> 
> Except the i.MX21 port all SoCs are runtime tested with the basic
> devices (at least uart and network; I tested more, but not
> systematically). Testers for these patches are very welcome, I will
> happily integrate fixups into this series. A branch containing Mikes
> latest clock patches, the driver fixups and this series can be found
> here:
> 
> git://git.pengutronix.de/git/imx/linux-2.6.git work/imx-clk-v4-v5
> 
> As a side note, we currently compile all i.MX v4/v5 based SoCs in a
> single defconfig. Since a kernel can only be built with or without the
> common clock framework this series is not fully bisectable, you have to
> disable the not yet converted SoCs in between.
> 
> The patch for removing the old clock support is not included in this
> post, but with the removal the overall diffstat looks like this:
> 
>  arch/arm/mach-imx/clock-imx1.c           |  636 ---------------
>  arch/arm/mach-imx/clock-imx21.c          | 1239 -------------------------------
>  arch/arm/mach-imx/clock-imx25.c          |  346 --------
>  arch/arm/mach-imx/clock-imx27.c          |  766 -------------------
>  b/arch/arm/mach-imx/Kconfig              |    4 
>  b/arch/arm/mach-imx/Makefile             |   10 
>  b/arch/arm/mach-imx/clk-imx1.c           |  118 ++
>  b/arch/arm/mach-imx/clk-imx21.c          |  177 ++++
>  b/arch/arm/mach-imx/clk-imx25.c          |  242 ++++++
>  b/arch/arm/mach-imx/clk-imx27.c          |  277 ++++++
>  b/arch/arm/mach-imx/clk-pllv1.c          |   59 +
>  b/arch/arm/mach-imx/clk.h                |   44 +
>  b/arch/arm/plat-mxc/clock.c              |   11 
>  b/arch/arm/plat-mxc/include/mach/clock.h |    4 
>  b/arch/arm/plat-mxc/time.c               |    5 
>  15 files changed, 946 insertions(+), 2992 deletions(-)
> 
> ----------------------------------------------------------------
> Sascha Hauer (7):
>       ARM i.MX: prepare for common clock framework
>       ARM i.MX timer: request correct clock
>       ARM i.MX: Add common clock support for pllv1
>       ARM i.MX1: implement clocks using common clock framework
>       ARM i.MX21: implement clocks using common clock framework
>       ARM i.MX25: implement clocks using common clock framework
>       ARM i.MX27: implement clocks using common clock framework
> 
>  arch/arm/mach-imx/Kconfig              |    4 +
>  arch/arm/mach-imx/Makefile             |   10 +-
>  arch/arm/mach-imx/clk-imx1.c           |  118 ++++++++++++++
>  arch/arm/mach-imx/clk-imx21.c          |  177 ++++++++++++++++++++
>  arch/arm/mach-imx/clk-imx25.c          |  242 ++++++++++++++++++++++++++++
>  arch/arm/mach-imx/clk-imx27.c          |  277 ++++++++++++++++++++++++++++++++
>  arch/arm/mach-imx/clk-pllv1.c          |   59 +++++++
>  arch/arm/mach-imx/clk.h                |   44 +++++
>  arch/arm/plat-mxc/clock.c              |   11 ++
>  arch/arm/plat-mxc/include/mach/clock.h |    4 +
>  arch/arm/plat-mxc/time.c               |    5 +-
>  11 files changed, 946 insertions(+), 5 deletions(-)
>  create mode 100644 arch/arm/mach-imx/clk-imx1.c
>  create mode 100644 arch/arm/mach-imx/clk-imx21.c
>  create mode 100644 arch/arm/mach-imx/clk-imx25.c
>  create mode 100644 arch/arm/mach-imx/clk-imx27.c
>  create mode 100644 arch/arm/mach-imx/clk-pllv1.c
>  create mode 100644 arch/arm/mach-imx/clk.h
> 

Do we want to move all clock code to drivers/clk? I'm not saying it has
to be done now, but is that a goal?

Rob


From grant.likely at secretlab.ca  Mon Mar 19 10:45:17 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 19 Mar 2012 14:45:17 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <4F6734DD.3020203@atmel.com>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <20120317094059.7C2333E08E2@localhost> <4F6734DD.3020203@atmel.com>
Message-ID: <20120319144517.C19E93E05A5@localhost>

On Mon, 19 Mar 2012 14:30:05 +0100, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
> On 03/17/2012 10:40 AM, Grant Likely :
> > On Thu, 15 Mar 2012 09:38:10 +0100, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
> >> +struct of_dma {
> >> +	struct list_head of_dma_controllers;
> >> +	struct device_node *of_node;
> >> +	int of_dma_n_cells;
> >> +	int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
> >> +};
> > 
> > This _xlate is nearly useless as a generic API.  It solves the problem for
> > the specific case where the driver is hard-coded to know which DMA engine
> > to talk to, but since the returned data doesn't provide any context, it
> > isn't useful if there are multiple DMA controllers to choose from.
> 
> You mean, if there is no DMA controller phandle specified in the
> property?

No; I'm assuming that dma-channel properties will alwasy have a
phandle to the dma controller node.

> I think that it is not the purpose of this API to choose a DMA
> controller, Nor to provide a channel. The only purpose of this API is to
> give a HW request to be used by a DMA slave driver. This slave should
> already have a channel to use and a controller to talk to.

Then where is the function that finds the reference to the DMA
controller?  I don't understand why it would be useful to decode that
separately.

> > The void *data pointer must be replaced with a typed structure so that
> > context can be returned.
> 
> I am not sure to follow you entirely... How do I address the fact that
> several types of request value can be returned then?
> 
> BTW, can we imagine a phandle property with a sting as a argument?
> should it be written this way?
> dma-request = <&testdmac1>, "slave-rx", "slave-tx";

No, I'm not suggesting that.  Mixing phandles and strings in a single
property is possible but ugly.  The phandle-args pattern which uses
zero or more cells as arguments should be used.

> 
> If yes, the of_parse_phandle_with_args() is not working on this type...

Right; of_parse_phandle_with_args() should do the job.

> 
> (I realize that there seems to be no way out for a generic API: maybe we
> should move to one or two cases to address and concentrate on them).

The way I read this patch, the xlate function returns a single
integer representing the DMA request number, but it doesn't provide
any data about *which* dma controller is associated with that channel.
The result of xlate needs to be something like a dma_chan reference
that identifies both the DMA engine and the channel/request on that
dma engine.

[...]
> >> +/**
> >> + * of_dma_xlate_onenumbercell() - Generic DMA xlate for direct one cell bindings
> >> + *
> >> + * Device Tree DMA translation function which works with one cell bindings
> >> + * where the cell values map directly to the hardware request number understood
> >> + * by the DMA controller.
> >> + */
> >> +int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec, void *dma_req)
> >> +{
> >> +	if (!dma_spec)
> >> +		return -EINVAL;
> >> +	if (WARN_ON(dma_spec->args_count != 1))
> >> +		return -EINVAL;
> >> +	*(int *)dma_req = dma_spec->args[0];
> > 
> > Following on from comment above; the void *dma_req parameter is dangerous.  How
> > does this function know that it has been passed an int* pointer?
> 
> Well, that is a drawback that comes from having to address generic
> cases.

Not if you do it right.  If a specific data structure is returned,
then there can be context attached as to what the data means and which
dma controller knows how to parse it.

> But anyway, if the DMA controller decide to register a .xlate()
> function that returns an integer, the slave driver that will ask a
> "request line" to this DMA controller will be aware that an integer has
> to be passed to of_get_dma_request().

The problem still remains; I don't see how the dma slave can figure
out *which* dma controller it needs to talk to.

g.

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From arnd at arndb.de  Mon Mar 19 11:01:09 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 15:01:09 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120319130222.GC5705@sirena.org.uk>
References: <4F22DEF2.5000807@ti.com> <20120317104751.4F00E3E0910@localhost>
 <20120319130222.GC5705@sirena.org.uk>
Message-ID: <201203191501.10232.arnd@arndb.de>

On Monday 19 March 2012, Mark Brown wrote:
> On Sat, Mar 17, 2012 at 10:47:51AM +0000, Grant Likely wrote:
> 
> > After implementing both schemes (ie. interrupts+interrupt-names && [*-]gpios)
> > I definitely prefer the fixed property name plus a separate names property.
> > It is easier to use common code with that scheme, and easier to statically
> > check for correctness.
> 
> It's not a fantastic experience when using the bindings as the arrays
> grow large, though - keeping things matched up isn't much fun especially
> if any of the elements in the array are optional.

Maybe one can use named properties in a new device node in that case,
like this:

	bus {
		dma: dma-controller {
			#dma-cells = <1>;
		};

		device {
			compatible = "device";
			channel: dma-channel {
				type = <0x1>;
				name = "foo";
				number = <23>;
				direction = <3>;
			};
			dma-requests = <&dma &channel>;
		};
	};

In this case, the dma engine's filter function would look up
the dma-channel device node from the phandle passed in the argument
to the dma-requests property, while a simpler dma engine would
just use a single number to identify a channel there.

	Arnd


From grant.likely at secretlab.ca  Mon Mar 19 11:06:01 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 19 Mar 2012 15:06:01 +0000
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20326.55337.249575.289067@ipc1.ka-ro>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
 <20120316030134.GA5161@shlinux2.ap.freescale.net>
 <20120318184749.BB15D3E07BF@localhost> <20326.55337.249575.289067@ipc1.ka-ro>
Message-ID: <20120319150601.B783A3E05A5@localhost>

On Mon, 19 Mar 2012 07:54:33 +0100, Lothar Wa??mann <LW at KARO-electronics.de> wrote:
> Grant Likely writes:
> > On Fri, 16 Mar 2012 11:01:35 +0800, Dong Aisheng <aisheng.dong at freescale.com> wrote:
> > > On Thu, Mar 15, 2012 at 07:22:04PM +0800, Lothar Wa??mann wrote:
> > > > Dong Aisheng writes:
> > > > > On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa??mann wrote:
> > > > Anyway there is no definite spec how the MAC address(es) are stored
> > > > in the fuse map. Thus reading the MAC from there is more or less
> > > > platform specific.
> > > > 
> > > It's just provide one more option since there are customers storing the MAC
> > > in the fuse map.
> > 
> > That should be straight forward to support; have a property that
> > specifies the method used for fetching/calculating the MAC.
> > 
> Executable code stored inside a DT blob? ;)

I know you're joking here, but I'm going to answer seriously
anyway... Absolutely not.  What I'm suggesting is a property that
specifies the method used to determine the mac address.  Something
like (off the top of my head):

	local-mac-address = [01 02 03 00 00 00];
	local-mac-mask = [0xff 0xff 0xff 0 0 0];
	mac-encoding = "append-serial-number";

> 
> > > > Currently I'm setting up the MAC address for our TX28 from the fuses
> > > > in the platform code passed via platform_data, but that will obviously
> > > > not work with DT.
> > > > 
> > > Non-dt can also use my proposal, then you only need to pass the fixed part of
> > > MAC via platfrom data, the left will be read by fec driver.
> > > 
> > > > The correct way would probably be to pass the MAC from the bootloader
> > > > via a DT blob. But that would require all bootloaders to be updated
> > > > first to support DTS. :(
> > > > 
> > > But uboot will face the same problem that can not define a valid MAC
> > > in dts, did i undertand correctly?
> > > 
> > > > An intermediate solution could be using OF_DEV_AUXDATA to pass a
> > > > platform_data struct that may contain a MAC address set up by the
> > > > platform code.
> > > > 
> > > Yes, it's a way but i'm afraid will not get accepted by dt people.
> > 
> > The problem remains; where does the platform code get the MAC address
> > from?  The kernel has to devise it from *somewhere* and the best place
> > for that should be in the MAC driver itself.
> > 
> The platform code knows how and where the MAC is stored on a specific
> platform. The driver has no business in knowing platform details like
> this. Thus only platform code (or the bootloader) can provide the MAC
> to the driver.

Okay, if so then it would be wise to have a reliable function for the
MAC driver to call to lookup it's address as determined by platform
code.  Alternately, the platform code can write the correct mac
address into the device tree node at init time (see
prom_update_property() and prom_add_property()).

BTW, prom_update_property() currently fails if the property doesn't
actually exist yet which isn't what we want I think.  Also, there are
only two users so it would be easy to change to make it add-or-update
instead of update-only.

> > I've got no problem with the idea of only specifying the OUI in the DT
> > and the driver extracting the remaining 3 bytes from the hardware.
> > 
> > In principle, that's the design intent for DT systems anyway; it
> > describes things which cannot be probed from the hardware, or tells
> > the OS how the data is encoded in the hardware.
> > 
> If all bootloaders were aware of DT this wouldn't be a problem,
> because they could place the correct MAC inside the DT blob right
> away.
> But in the mean time (AKA forever) we need some other solution.

You'll notice I haven't disputed that.

g.



From swarren at wwwdotorg.org  Mon Mar 19 11:07:48 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 09:07:48 -0600
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203191501.10232.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com> <20120317104751.4F00E3E0910@localhost>
 <20120319130222.GC5705@sirena.org.uk> <201203191501.10232.arnd@arndb.de>
Message-ID: <4F674BC4.2070802@wwwdotorg.org>

On 03/19/2012 09:01 AM, Arnd Bergmann wrote:
> On Monday 19 March 2012, Mark Brown wrote:
>> On Sat, Mar 17, 2012 at 10:47:51AM +0000, Grant Likely wrote:
>>
>>> After implementing both schemes (ie. interrupts+interrupt-names && [*-]gpios)
>>> I definitely prefer the fixed property name plus a separate names property.
>>> It is easier to use common code with that scheme, and easier to statically
>>> check for correctness.
>>
>> It's not a fantastic experience when using the bindings as the arrays
>> grow large, though - keeping things matched up isn't much fun especially
>> if any of the elements in the array are optional.
> 
> Maybe one can use named properties in a new device node in that case,
> like this:
> 
> 	bus {
> 		dma: dma-controller {
> 			#dma-cells = <1>;
> 		};
> 
> 		device {
> 			compatible = "device";
> 			channel: dma-channel {
> 				type = <0x1>;
> 				name = "foo";
> 				number = <23>;
> 				direction = <3>;
> 			};
> 			dma-requests = <&dma &channel>;
> 		};
> 	};

For reference, this is very similar to how the pinctrl bindings work,
except that they require the "channel" node to be a child of the DMA
controller, and hence "dma-requests" doesn't contain <&dma &channel>,
just <&channel>, since "dma" is the parent (or grand-parent) of "channel".


From balbi at ti.com  Mon Mar 19 11:07:38 2012
From: balbi at ti.com (Felipe Balbi)
Date: Mon, 19 Mar 2012 17:07:38 +0200
Subject: [PATCH 01/12] mfd: twl-core: don't depend on pdata->irq_base/end
In-Reply-To: <87pqcegapk.fsf@ti.com>
References: <1330707024-23730-1-git-send-email-b-cousson@ti.com>
 <1330707024-23730-2-git-send-email-b-cousson@ti.com>
 <87pqcegapk.fsf@ti.com>
Message-ID: <20120319150736.GM25935@arwen.pp.htv.fi>

Hi,

On Wed, Mar 14, 2012 at 01:59:51PM -0700, Kevin Hilman wrote:
> Benoit Cousson <b-cousson at ti.com> writes:
> 
> > From: Felipe Balbi <balbi at ti.com>
> >
> > With sparse IRQs the driver shouldn't depend at all on
> > any IRQ values coming from board-file.
> >
> > Remove every occurences of pdata->irq_base/end.
> 
> Well, not quite *every*. :)
> 
> If the driver isn't going to use those fields anymore, they should also
> be removed from the pdata struct too[1].  Also, the remaining board/init
> code that is initializing those fields should be removed as well[2], since
> it obviously has no effect.

indeed, but the idea was to decouple driver changes from arch/arm/*omap*
changes minimizing the oportunity of conflicts. So, e.g. on v3.4 we
change driver and on v3.5 we change board files.

-- 
balbi
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From peter.ujfalusi at ti.com  Mon Mar 19 11:12:45 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 19 Mar 2012 17:12:45 +0200
Subject: [PATCH 1/2] ARM: OMAP3: hwmod_data: Rename the common irq for McBSP
 ports
Message-ID: <1332169966-25400-1-git-send-email-peter.ujfalusi@ti.com>

Use 'common' as name for the common irq number in hwmod data for the McBSP
ports. The same name already in use for OMAP2430, and the OMAP4 hwmod data
will be using the same name.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3c8dd92..af84276 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2242,7 +2242,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
 
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
-	{ .name = "irq", .irq = 16 },
+	{ .name = "common", .irq = 16 },
 	{ .name = "tx", .irq = 59 },
 	{ .name = "rx", .irq = 60 },
 	{ .irq = -1 }
@@ -2293,7 +2293,7 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
 
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
-	{ .name = "irq", .irq = 17 },
+	{ .name = "common", .irq = 17 },
 	{ .name = "tx", .irq = 62 },
 	{ .name = "rx", .irq = 63 },
 	{ .irq = -1 }
@@ -2349,7 +2349,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
 
 /* mcbsp3 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
-	{ .name = "irq", .irq = 22 },
+	{ .name = "common", .irq = 22 },
 	{ .name = "tx", .irq = 89 },
 	{ .name = "rx", .irq = 90 },
 	{ .irq = -1 }
@@ -2405,7 +2405,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
 
 /* mcbsp4 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
-	{ .name = "irq", .irq = 23 },
+	{ .name = "common", .irq = 23 },
 	{ .name = "tx", .irq = 54 },
 	{ .name = "rx", .irq = 55 },
 	{ .irq = -1 }
@@ -2462,7 +2462,7 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
 
 /* mcbsp5 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
-	{ .name = "irq", .irq = 27 },
+	{ .name = "common", .irq = 27 },
 	{ .name = "tx", .irq = 81 },
 	{ .name = "rx", .irq = 82 },
 	{ .irq = -1 }
-- 
1.7.8.5



From peter.ujfalusi at ti.com  Mon Mar 19 11:12:46 2012
From: peter.ujfalusi at ti.com (Peter Ujfalusi)
Date: Mon, 19 Mar 2012 17:12:46 +0200
Subject: [PATCH 2/2] ARM: OMAP4: hwmod_data: Name the common irq for McBSP
 ports
In-Reply-To: <1332169966-25400-1-git-send-email-peter.ujfalusi@ti.com>
References: <1332169966-25400-1-git-send-email-peter.ujfalusi@ti.com>
Message-ID: <1332169966-25400-2-git-send-email-peter.ujfalusi@ti.com>

Use 'common' as name for the common irq number in hwmod data for the McBSP
ports. The same name already in use for OMAP2430, and OMAP3.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ef0524c..f8058b7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2942,7 +2942,7 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
 /* mcbsp1 */
 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
-	{ .irq = 17 + OMAP44XX_IRQ_GIC_START },
+	{ .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
 	{ .irq = -1 }
 };
 
@@ -3017,7 +3017,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
 /* mcbsp2 */
 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
-	{ .irq = 22 + OMAP44XX_IRQ_GIC_START },
+	{ .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
 	{ .irq = -1 }
 };
 
@@ -3092,7 +3092,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
 /* mcbsp3 */
 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
-	{ .irq = 23 + OMAP44XX_IRQ_GIC_START },
+	{ .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
 	{ .irq = -1 }
 };
 
@@ -3167,7 +3167,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
 /* mcbsp4 */
 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
-	{ .irq = 16 + OMAP44XX_IRQ_GIC_START },
+	{ .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
 	{ .irq = -1 }
 };
 
-- 
1.7.8.5



From linux at arm.linux.org.uk  Mon Mar 19 11:20:59 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 19 Mar 2012 15:20:59 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <4F6736B4.4090509@atmel.com>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <20120317094059.7C2333E08E2@localhost> <201203182013.22790.arnd@arndb.de>
 <4F6736B4.4090509@atmel.com>
Message-ID: <20120319152059.GE16389@n2100.arm.linux.org.uk>

On Mon, Mar 19, 2012 at 02:37:56PM +0100, Nicolas Ferre wrote:
> On 03/18/2012 09:13 PM, Arnd Bergmann :
> > On Saturday 17 March 2012, Grant Likely wrote:
> >>> +static LIST_HEAD(of_dma_list);
> >>> +
> >>> +struct of_dma {
> >>> +     struct list_head of_dma_controllers;
> >>> +     struct device_node *of_node;
> >>> +     int of_dma_n_cells;
> >>> +     int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
> >>> +};
> >>
> >> This _xlate is nearly useless as a generic API.  It solves the problem for
> >> the specific case where the driver is hard-coded to know which DMA engine
> >> to talk to, but since the returned data doesn't provide any context, it
> >> isn't useful if there are multiple DMA controllers to choose from.
> >>
> >> The void *data pointer must be replaced with a typed structure so that
> >> context can be returned.
> > 
> > I've read up a bit more on how the existing drivers use the filter
> > functions, it seems there are multiple classes of them, the classes
> > that I've encountered are:
> > 
> > 1. matches on chan->device pointer and/or chan_id
> 
> I have the impression that we are now talking about *channel* selection.
> It is not the purpose of those helper functions. It is just to retrieve
> a *request line* for a particular slave interface.

The request line on what though?  The DMA controller, or something
else?

The reason I ask is because on ARM boards, the DMA controller has N
request lines.  Three of those request lines are multiplexed in an
external FPGA to select between N different peripherals.

For example, the UART and MMCI may be routed to the FPGA multiplexer,
and either could be routed to DMA controller request signal 0, 1, or 2,
whereas a different UART might be routed directly to DMA controller
request signal 3 and 4.

At the moment, we handle this via platform data and callbacks passed
into the PL080 DMA driver, by matching virtual DMA channels based upon
strings looked up in the platform data.  This gives the range of
DMA request signal numbers on the controller, and calls a platform
provided function to setup the multiplexer.

Clearly, if your proposal is all about DMA controller request signals
only, the above scheme can't be represented in DT... and that's what
worries me - the fact is that the DMA engine API can and does cope
with this but it seems that we're building restrictions in with DT on
what can be represented.

That makes me wonder whether the model that's being chosen is anywhere
near correct for the DMA engine API.

Now, as I've said before, I'm trying to work on creating an OMAP DMA engine
implementation, and I'd _really_ like to have the freedom to do what's
necessary there without having to think one bit about DT getting in the
way.  To put it another way, I don't want to be constrained by any weirdo
DT representations at the moment, and I really don't want to waste time
discussing them at the moment, rather than getting on with that job.
Because if I end up discussing this at length, I'm not going to be able
to do anything on the OMAP DMA engine stuff.


From linux at arm.linux.org.uk  Mon Mar 19 11:33:34 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 19 Mar 2012 15:33:34 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203191406.35064.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com> <20120317094059.7C2333E08E2@localhost>
 <4F6734DD.3020203@atmel.com> <201203191406.35064.arnd@arndb.de>
Message-ID: <20120319153334.GF16389@n2100.arm.linux.org.uk>

On Mon, Mar 19, 2012 at 02:06:34PM +0000, Arnd Bergmann wrote:
> ==== mmci ====
> /* in drivers/dma/ste_dma40.c, others in pl330.c, coh901318.c, ... */
> bool stedma40_filter(struct dma_chan *chan, void *data)
> {               
>         struct stedma40_chan_cfg *info = data;
>         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
>         int err;                
>         
>         err = d40_validate_conf(d40c, info);
>         if (!err)
>                 d40c->dma_cfg = *info;
>         d40c->configured = true;
>         
>         return err == 0;
> }
> EXPORT_SYMBOL(stedma40_filter);
> 
> /* in mmci.h */
> struct mmci_platform_data {
> 	...
>         bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
>         void *dma_rx_param;
>         void *dma_tx_param;
> };
> 
> /* in mmci.c */
> static void __devinit mmci_dma_setup(struct mmci_host *host)
> {
> 	...
>         host->dma_rx_channel = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
> 	...
> }
> 
> ====
> 
> Whatever we come up with obviously needs to work with both drivers.
> I think we will end up with something closer to the second one, except
> that the dma parameters do not come from platform_data but from the
> #dma-request property, which also identifies the controller and channel.

Firstly, define what you mean by "the DMA parameters".  Things like burst
size, register width, register address?  That should all be known by the
peripheral driver and _not_ be encoded into DT in any way - and this
information should be passed to the DMA engine driver for the well defined
API for that purpose.

Secondly, there are platforms (Samsung) where peripherals are connected
to more than one DMA controller, and either DMA controller can be used -
I'm told by Jassi that there's reasons why you'd want to select one or
other as the target at runtime.

Whether it's appropriate for DT to know that or not, I'm not certain at
the moment - I suspect the _right_ solution would be a radical DMA engine
redesign which moves _all_ slave DMA to a virtual channel representation,
and for the virtual channels to be scheduled onto a set of physical DMA
channels over a range of DMA devices.  Obviously, there's restrictions on
which virtual channels could be scheduled onto which physical channels of
which DMA devices.

It seems to me, therefore, that any attempt to come up with some kind of
DT based representation of the current scheme is doomed to fail, and will
at some point become obsolete.

I think instead, rather than trying to fix this now, we persist with what
we have, but organize an effort to clean up and restructure the DMA engine
code so that:

(a) things like the Samsung, and ARM board oddities can be easily dealt
 with in a driver independent manner.
(b) get rid of all the duplicated functionality between each different
 DMA engine implementation, separating this out into core code, and
 simplifying the drivers.

The _big_ problem I see is that if we try to represent the existing
solution in DT, we're going to get locked into that way of doing things
and then any major restructuring of the DMA engine stuff will become an
impossibility - especially if we start specifying things by DMA request
signal numbers on DMA engines.


From veli-pekka.peltola at bluegiga.com  Mon Mar 19 11:36:00 2012
From: veli-pekka.peltola at bluegiga.com (Veli-Pekka Peltola)
Date: Mon, 19 Mar 2012 17:36:00 +0200
Subject: [PATCH v2] mm: module_alloc: check if size is 0
In-Reply-To: <1331125768-25454-1-git-send-email-veli-pekka.peltola@bluegiga.com>
References: <1330631119-10059-1-git-send-email-veli-pekka.peltola@bluegiga.com>
 <1331125768-25454-1-git-send-email-veli-pekka.peltola@bluegiga.com>
Message-ID: <4F675260.2010205@bluegiga.com>

Hi,

On 03/07/2012 03:09 PM, Veli-Pekka Peltola wrote:
> After commit de7d2b567d040e3b67fe7121945982f14343213d (mm/vmalloc.c: report
> more vmalloc failures) users will get a warning if vmalloc_node_range() is
> called with size 0. This happens if module's init size equals to 0. This
> patch changes ARM, MIPS and x86 module_alloc() to return NULL before calling
> vmalloc_node_range() that would also return NULL and print a warning.
>
> Signed-off-by: Veli-Pekka Peltola<veli-pekka.peltola at bluegiga.com>
> Cc: Russell King<linux at arm.linux.org.uk>
> Cc: Thomas Gleixner<tglx at linutronix.de>
> Cc: Ingo Molnar<mingo at redhat.com>
> Cc: "H. Peter Anvin"<hpa at zytor.com>
> Cc: x86 at kernel.org
> ---
> I found this with ARM but after checking out various implementations of
> module_alloc() I thought it would be better to fix all at once.
>
> One way to replicate the warning:
> compile kernel with CONFIG_KALLSYMS=n
> insmod a module without init, I used usb-common.ko
>
> Changes since v1:
>   - changed style as hpa suggested
>
>   arch/arm/kernel/module.c  |    2 ++
>   arch/mips/kernel/module.c |    2 ++
>   arch/x86/kernel/module.c  |    2 +-
>   3 files changed, 5 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
> index 1e9be5d..17648e2 100644
> --- a/arch/arm/kernel/module.c
> +++ b/arch/arm/kernel/module.c
> @@ -39,6 +39,8 @@
>   #ifdef CONFIG_MMU
>   void *module_alloc(unsigned long size)
>   {
> +	if (!size)
> +		return NULL;
>   	return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
>   				GFP_KERNEL, PAGE_KERNEL_EXEC, -1,
>   				__builtin_return_address(0));
> diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
> index a5066b1..1a51de1 100644
> --- a/arch/mips/kernel/module.c
> +++ b/arch/mips/kernel/module.c
> @@ -47,6 +47,8 @@ static DEFINE_SPINLOCK(dbe_lock);
>   #ifdef MODULE_START
>   void *module_alloc(unsigned long size)
>   {
> +	if (!size)
> +		return NULL;
>   	return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END,
>   				GFP_KERNEL, PAGE_KERNEL, -1,
>   				__builtin_return_address(0));
> diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
> index 925179f..fd44d69 100644
> --- a/arch/x86/kernel/module.c
> +++ b/arch/x86/kernel/module.c
> @@ -38,7 +38,7 @@
>
>   void *module_alloc(unsigned long size)
>   {
> -	if (PAGE_ALIGN(size)>  MODULES_LEN)
> +	if (!size || PAGE_ALIGN(size)>  MODULES_LEN)
>   		return NULL;
>   	return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
>   				GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL_EXEC,

Any comments on this? Should I split all architectures to separate patches?

I just tested 3.3 on ARM and x86, both printed a warning and call trace 
without this patch.

--
Veli-Pekka Peltola


From linux at arm.linux.org.uk  Mon Mar 19 11:41:23 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 19 Mar 2012 15:41:23 +0000
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <4F674479.8090101@gmail.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <20120319085503.GL15988@n2100.arm.linux.org.uk> <4F674479.8090101@gmail.com>
Message-ID: <20120319154123.GP15988@n2100.arm.linux.org.uk>

On Mon, Mar 19, 2012 at 09:36:41AM -0500, Rob Herring wrote:
> On 03/19/2012 03:55 AM, Russell King - ARM Linux wrote:
> > On Mon, Mar 19, 2012 at 04:02:48PM +0900, Boojin Kim wrote:
> >> This patch uses LDRD/STRD that loads and stores data as DWORD unit
> >> for the copy of 8-words data.
> >> It brings better performance than LDRM/STRM that was used originally.
> > 
> > And what about CPUs that don't have ldrd/strd ?
> > 
> 
> And what about CPUs that do have ldrd/strd but is slower than ldm/stm?
> I'm pretty sure that is almost everything currently out there.

The double-word load/stores were introduced in ARMv6.  Some Intel based
CPUs prior to this have the support as well.  Everything else doesn't.

So taht's nowhere close to 'almost everything'.


From arnd at arndb.de  Mon Mar 19 11:45:40 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 15:45:40 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <4F674BC4.2070802@wwwdotorg.org>
References: <4F22DEF2.5000807@ti.com> <201203191501.10232.arnd@arndb.de>
 <4F674BC4.2070802@wwwdotorg.org>
Message-ID: <201203191545.40933.arnd@arndb.de>

On Monday 19 March 2012, Stephen Warren wrote:
> > Maybe one can use named properties in a new device node in that case,
> > like this:
> > 
> >       bus {
> >               dma: dma-controller {
> >                       #dma-cells = <1>;
> >               };
> > 
> >               device {
> >                       compatible = "device";
> >                       channel: dma-channel {
> >                               type = <0x1>;
> >                               name = "foo";
> >                               number = <23>;
> >                               direction = <3>;
> >                       };
> >                       dma-requests = <&dma &channel>;
> >               };
> >       };
> 
> For reference, this is very similar to how the pinctrl bindings work,
> except that they require the "channel" node to be a child of the DMA
> controller, and hence "dma-requests" doesn't contain <&dma &channel>,
> just <&channel>, since "dma" is the parent (or grand-parent) of "channel".

Right, but the difference beytween the pinctrl binding and what I
describe here is that the channel description would be part of the
dma engine driver specific binding, not the generic binding that
is visible to device drivers.

As I said, one dmaengine could use a phandle while another one could
just use a single number or nothing at all. If it chooses to use
a phandle (or possible a combination of phandle and number), the
binding could mandate for the device node to be either a child of the
dma controller or the device using it. In either case it would be
sensible to do it the same way for all dmaengine drivers that want
to have a phandle in the argument.

	Arnd


From b-cousson at ti.com  Mon Mar 19 11:58:52 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 19 Mar 2012 16:58:52 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120319152059.GE16389@n2100.arm.linux.org.uk>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <20120317094059.7C2333E08E2@localhost> <201203182013.22790.arnd@arndb.de>
 <4F6736B4.4090509@atmel.com> <20120319152059.GE16389@n2100.arm.linux.org.uk>
Message-ID: <4F6757BC.50408@ti.com>

On 3/19/2012 4:20 PM, Russell King - ARM Linux wrote:
> On Mon, Mar 19, 2012 at 02:37:56PM +0100, Nicolas Ferre wrote:
>> On 03/18/2012 09:13 PM, Arnd Bergmann :
>>> On Saturday 17 March 2012, Grant Likely wrote:
>>>>> +static LIST_HEAD(of_dma_list);
>>>>> +
>>>>> +struct of_dma {
>>>>> +     struct list_head of_dma_controllers;
>>>>> +     struct device_node *of_node;
>>>>> +     int of_dma_n_cells;
>>>>> +     int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
>>>>> +};
>>>>
>>>> This _xlate is nearly useless as a generic API.  It solves the problem for
>>>> the specific case where the driver is hard-coded to know which DMA engine
>>>> to talk to, but since the returned data doesn't provide any context, it
>>>> isn't useful if there are multiple DMA controllers to choose from.
>>>>
>>>> The void *data pointer must be replaced with a typed structure so that
>>>> context can be returned.
>>>
>>> I've read up a bit more on how the existing drivers use the filter
>>> functions, it seems there are multiple classes of them, the classes
>>> that I've encountered are:
>>>
>>> 1. matches on chan->device pointer and/or chan_id
>>
>> I have the impression that we are now talking about *channel* selection.
>> It is not the purpose of those helper functions. It is just to retrieve
>> a *request line* for a particular slave interface.
>
> The request line on what though?  The DMA controller, or something
> else?

The idea is just to represent the request line from the IP to the DMA 
controller. This is exactly the same pattern than for the IRQ line 
toward the IRQ controller.

> The reason I ask is because on ARM boards, the DMA controller has N
> request lines.  Three of those request lines are multiplexed in an
> external FPGA to select between N different peripherals.
>
> For example, the UART and MMCI may be routed to the FPGA multiplexer,
> and either could be routed to DMA controller request signal 0, 1, or 2,
> whereas a different UART might be routed directly to DMA controller
> request signal 3 and 4.
>
> At the moment, we handle this via platform data and callbacks passed
> into the PL080 DMA driver, by matching virtual DMA channels based upon
> strings looked up in the platform data.  This gives the range of
> DMA request signal numbers on the controller, and calls a platform
> provided function to setup the multiplexer.
>
> Clearly, if your proposal is all about DMA controller request signals
> only, the above scheme can't be represented in DT...

Yes, this is the goal. I guess in your case you do need some DMA nexus 
node like DT is already providing for the IRQ. But you still should be 
able to describe how the HW blocks are interconnected.

> and that's what
> worries me - the fact is that the DMA engine API can and does cope
> with this but it seems that we're building restrictions in with DT on
> what can be represented.

But then you are mixing the SW representation and the HW one. DMAengine 
is the Linux way of managing DMA channel. DT is supposed to be OS 
agnostic and just describe the HW.
So you cannot take into account some DMAengine specificity to define the 
DT binding. At least in theory.

> That makes me wonder whether the model that's being chosen is anywhere
> near correct for the DMA engine API.

That's not the goal. The goal is to describe how the DMA request lines 
are connected from the IP to the controller.

> Now, as I've said before, I'm trying to work on creating an OMAP DMA engine
> implementation, and I'd _really_ like to have the freedom to do what's
> necessary there without having to think one bit about DT getting in the
> way.  To put it another way, I don't want to be constrained by any weirdo
> DT representations at the moment, and I really don't want to waste time
> discussing them at the moment, rather than getting on with that job.
> Because if I end up discussing this at length, I'm not going to be able
> to do anything on the OMAP DMA engine stuff.

The current way of representing the DMA requests for OMAP SDMA is pretty 
straightforward and fit well with the current binding. It looks to me 
that this is the ARM boards that will be tricky to handle.

Regards,
Benoit


From arnd at arndb.de  Mon Mar 19 12:11:58 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 16:11:58 +0000
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120319153334.GF16389@n2100.arm.linux.org.uk>
References: <4F22DEF2.5000807@ti.com> <201203191406.35064.arnd@arndb.de>
 <20120319153334.GF16389@n2100.arm.linux.org.uk>
Message-ID: <201203191611.59064.arnd@arndb.de>

On Monday 19 March 2012, Russell King - ARM Linux wrote:
> Firstly, define what you mean by "the DMA parameters".  Things like burst
> size, register width, register address?  That should all be known by the
> peripheral driver and not be encoded into DT in any way - and this
> information should be passed to the DMA engine driver for the well defined
> API for that purpose.

This seems to be different for each controller, I tried to use
a generic term here. In case of stedma40 (which is probably the most
complex one today), it would be this structure:

struct stedma40_chan_cfg {
        enum stedma40_xfer_dir                   dir;
        bool                                     high_priority;
        bool                                     realtime;
        enum stedma40_mode                       mode;
        enum stedma40_mode_opt                   mode_opt;
        int                                      src_dev_type;
        int                                      dst_dev_type;
        struct stedma40_half_channel_info        src_info;
        struct stedma40_half_channel_info        dst_info;

        bool                                     use_fixed_channel; 
        int                                      phy_channel;
};

All these fields are set up by the platform code today, not by
the device driver, so it would be logical to have them represented
in the device tree, though some of the fields might turn out to
be in the wrong place already.

> Secondly, there are platforms (Samsung) where peripherals are connected
> to more than one DMA controller, and either DMA controller can be used -
> I'm told by Jassi that there's reasons why you'd want to select one or
> other as the target at runtime.

How common is that? If there are only a few drivers that have this
requirement, we could have this represented in the driver binding, by
listing multiple channels and giving the device the choice.

A possible way to deal with this is to list all the alternatives
in the device tree and using the dma-names property to name them,
giving the same name to those that we need to pick one of.

> I think instead, rather than trying to fix this now, we persist with what
> we have, but organize an effort to clean up and restructure the DMA engine
> code so that:
> 
> (a) things like the Samsung, and ARM board oddities can be easily dealt
>  with in a driver independent manner.
> (b) get rid of all the duplicated functionality between each different
>  DMA engine implementation, separating this out into core code, and
>  simplifying the drivers.

At that point, we definitely need to involve the dmaenigne maintainers
who have unfortunately not been on Cc for the whole discussion so
far.

I actually hope that a lot of the issues go away if we come up with
good device tree bindings that can cover the existing corner cases
while providing a simple interface for device drivers to use.

> The big problem I see is that if we try to represent the existing
> solution in DT, we're going to get locked into that way of doing things
> and then any major restructuring of the DMA engine stuff will become an
> impossibility - especially if we start specifying things by DMA request
> signal numbers on DMA engines.

Note that Thomas Abraham has already introduced a DT support for
pl330, which is sadly seems to be anything but generic.

	Arnd


From jean.pihet at newoldbits.com  Mon Mar 19 12:12:49 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Mon, 19 Mar 2012 17:12:49 +0100
Subject: [PATCH v2 0/9] PM: Create the AVS class of drivers
Message-ID: <1332173578-27422-1-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

AVS is a power management technique which controls the operating
voltage of a device in order to optimize (i.e. reduce) its power
consumption. The voltage is adapted depending on static factors
(chip manufacturing process) and dynamic factors (temperature
depending performance).
AVS is also called SmartReflex on OMAP devices.

To that end, create the AVS framework in drivers/power/avs and
move the OMAP SmartReflex code to the new directory.

In preparation to the move of the OMAP code the following changes have been
made:
- split the include files into generic and platform specific code,
- fill in platform data from the device initialization code and pass
  it to the driver,
- create CONFIG_AVS* config options accordingly.

The platform integration data for SmartReflex is passed from hwmod
and the voltage layer to the driver using pdata.


Tested on OMAP3 Beagleboard using omap2plus_defconfig with the
CONFIG_POWER_AVS* options set.
Based on master branch of the l-o git tree (3.3.0-rc6) [1], commit
85244e0edd240da2004bb2ab7cbcbc67a336f20d.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git


History:
v2: rework after the comments on MLs
 . Keep the OMAP Kconfig options in the arch dir (Rafael),
 . Move the shared header file from plat-omap to
    include/linux/power/ (Tony)

v1: initial revision
 

Jean Pihet (9):
  ARM: OMAP3+: voltage: export functions to plat/voltage.h
  ARM: OMAP2+: SmartReflex: move the driver specific macros in
    include/linux/power
  ARM: OMAP3+: SmartReflex: class drivers should use struct omap_sr *
  ARM: OMAP2+: smartreflex: Use the names from hwmod data instead of
    voltage domains.
  ARM: OMAP3: hwmod: rename the smartreflex entries
  ARM: OMAP2+: SmartReflex: introduce a busy loop condition test macro
  ARM: OMAP2+: SmartReflex: Use per-OPP data structure
  ARM: OMAP2+: SmartReflex: add POWER_AVS Kconfig options
  ARM: OMAP: SmartReflex: Move smartreflex driver to drivers/

 arch/arm/mach-omap2/Makefile               |    4 +-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   12 +-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    3 +-
 arch/arm/mach-omap2/pm.h                   |    2 +-
 arch/arm/mach-omap2/smartreflex-class3.c   |   60 --
 arch/arm/mach-omap2/smartreflex.c          | 1165 ----------------------------
 arch/arm/mach-omap2/smartreflex.h          |  256 ------
 arch/arm/mach-omap2/sr_device.c            |   38 +-
 arch/arm/mach-omap2/voltage.h              |    1 -
 arch/arm/mach-omap2/vp.h                   |    2 -
 arch/arm/plat-omap/Kconfig                 |   30 +-
 arch/arm/plat-omap/include/plat/voltage.h  |    3 +
 drivers/power/Kconfig                      |    2 +
 drivers/power/Makefile                     |    2 +
 drivers/power/avs/Kconfig                  |   12 +
 drivers/power/avs/Makefile                 |    2 +
 drivers/power/avs/smartreflex-class3.c     |   61 ++
 drivers/power/avs/smartreflex.c            | 1118 ++++++++++++++++++++++++++
 drivers/power/avs/smartreflex.h            |  238 ++++++
 include/linux/power/smartreflex.h          |   97 +++
 20 files changed, 1590 insertions(+), 1518 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/smartreflex-class3.c
 delete mode 100644 arch/arm/mach-omap2/smartreflex.c
 delete mode 100644 arch/arm/mach-omap2/smartreflex.h
 create mode 100644 drivers/power/avs/Kconfig
 create mode 100644 drivers/power/avs/Makefile
 create mode 100644 drivers/power/avs/smartreflex-class3.c
 create mode 100644 drivers/power/avs/smartreflex.c
 create mode 100644 drivers/power/avs/smartreflex.h
 create mode 100644 include/linux/power/smartreflex.h

-- 
1.7.5.4



From jean.pihet at newoldbits.com  Mon Mar 19 12:12:50 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Mon, 19 Mar 2012 17:12:50 +0100
Subject: [PATCH 1/9] ARM: OMAP3+: voltage: export functions to plat/voltage.h
In-Reply-To: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
References: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
Message-ID: <1332173578-27422-2-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Move some functions from mach-omap2/ dir to the plat/ dir.
The SmartReflex class driver is a user of the basic voltage domains
functions (enable, disable, reset).

Signed-off-by: Jean Pihet <j-pihet at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/smartreflex-class3.c  |    1 +
 arch/arm/mach-omap2/smartreflex.h         |    2 +-
 arch/arm/mach-omap2/voltage.h             |    1 -
 arch/arm/mach-omap2/vp.h                  |    2 --
 arch/arm/plat-omap/include/plat/voltage.h |    3 +++
 5 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 955566e..e12c51e 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -12,6 +12,7 @@
  */
 
 #include "smartreflex.h"
+#include "voltage.h"
 
 static int sr_class3_enable(struct voltagedomain *voltdm)
 {
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 5809141..c4e8530 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -22,7 +22,7 @@
 
 #include <linux/platform_device.h>
 
-#include "voltage.h"
+#include <plat/voltage.h>
 
 /*
  * Different Smartreflex IPs version. The v1 is the 65nm version used in
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 16a1b09..a81dea8 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -167,6 +167,5 @@ int voltdm_for_each_pwrdm(struct voltagedomain *voltdm,
 			  int (*fn)(struct voltagedomain *voltdm,
 				    struct powerdomain *pwrdm));
 int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
-void voltdm_reset(struct voltagedomain *voltdm);
 unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
 #endif
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
index 7c155d2..837cb8d 100644
--- a/arch/arm/mach-omap2/vp.h
+++ b/arch/arm/mach-omap2/vp.h
@@ -118,8 +118,6 @@ extern struct omap_vp_instance omap4_vp_iva;
 extern struct omap_vp_instance omap4_vp_core;
 
 void omap_vp_init(struct voltagedomain *voltdm);
-void omap_vp_enable(struct voltagedomain *voltdm);
-void omap_vp_disable(struct voltagedomain *voltdm);
 int omap_vp_forceupdate_scale(struct voltagedomain *voltdm,
 			      unsigned long target_volt);
 int omap_vp_update_errorgain(struct voltagedomain *voltdm,
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
index 0a6a482..1842709 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -16,5 +16,8 @@ struct voltagedomain;
 struct voltagedomain *voltdm_lookup(const char *name);
 int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
 unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
+void voltdm_reset(struct voltagedomain *voltdm);
 
+void omap_vp_enable(struct voltagedomain *voltdm);
+void omap_vp_disable(struct voltagedomain *voltdm);
 #endif
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Mon Mar 19 12:12:51 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Mon, 19 Mar 2012 17:12:51 +0100
Subject: [PATCH 2/9] ARM: OMAP2+: SmartReflex: move the driver specific macros
 in include/linux/power
In-Reply-To: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
References: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
Message-ID: <1332173578-27422-3-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Move the driver specific macros from the smartreflex header file
(arch/arm/mach-omap2/smartreflex.h) in a new header file
include/linux/power/smartreflex.h.

This change makes the SmartReflex implementation ready for the move
to drivers/.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |    4 +-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    3 +-
 arch/arm/mach-omap2/smartreflex.c          |    2 +-
 arch/arm/mach-omap2/smartreflex.h          |   42 -----------------
 arch/arm/mach-omap2/sr_device.c            |    2 +-
 include/linux/power/smartreflex.h          |   67 ++++++++++++++++++++++++++++
 6 files changed, 72 insertions(+), 48 deletions(-)
 create mode 100644 include/linux/power/smartreflex.h

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 0cc6a40..d7d4c70 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -13,6 +13,8 @@
  *
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+#include <linux/power/smartreflex.h>
+
 #include <plat/omap_hwmod.h>
 #include <mach/irqs.h>
 #include <plat/cpu.h>
@@ -28,8 +30,6 @@
 #include <plat/dmtimer.h>
 
 #include "omap_hwmod_common_data.h"
-
-#include "smartreflex.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
 #include "wd_timer.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 48e5834..31e7b87 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -19,6 +19,7 @@
  */
 
 #include <linux/io.h>
+#include <linux/power/smartreflex.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
@@ -32,8 +33,6 @@
 #include <plat/common.h>
 
 #include "omap_hwmod_common_data.h"
-
-#include "smartreflex.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 #include "prm44xx.h"
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 008fbd7..33e2825 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -25,9 +25,9 @@
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
+#include <linux/power/smartreflex.h>
 
 #include "common.h"
-
 #include "pm.h"
 #include "smartreflex.h"
 
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index c4e8530..8835422 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -152,14 +152,6 @@ struct omap_sr_pmic_data {
 	void (*sr_pmic_init) (void);
 };
 
-/**
- * struct omap_smartreflex_dev_attr - Smartreflex Device attribute.
- *
- * @sensor_voltdm_name:       Name of voltdomain of SR instance
- */
-struct omap_smartreflex_dev_attr {
-	const char      *sensor_voltdm_name;
-};
 
 #ifdef CONFIG_OMAP_SMARTREFLEX
 /*
@@ -194,40 +186,6 @@ struct omap_sr_class_data {
 	u8 class_type;
 };
 
-/**
- * struct omap_sr_nvalue_table	- Smartreflex n-target value info
- *
- * @efuse_offs:	The offset of the efuse where n-target values are stored.
- * @nvalue:	The n-target value.
- */
-struct omap_sr_nvalue_table {
-	u32 efuse_offs;
-	u32 nvalue;
-};
-
-/**
- * struct omap_sr_data - Smartreflex platform data.
- *
- * @ip_type:		Smartreflex IP type.
- * @senp_mod:		SENPENABLE value for the sr
- * @senn_mod:		SENNENABLE value for sr
- * @nvalue_count:	Number of distinct nvalues in the nvalue table
- * @enable_on_init:	whether this sr module needs to enabled at
- *			boot up or not.
- * @nvalue_table:	table containing the  efuse offsets and nvalues
- *			corresponding to them.
- * @voltdm:		Pointer to the voltage domain associated with the SR
- */
-struct omap_sr_data {
-	int				ip_type;
-	u32				senp_mod;
-	u32				senn_mod;
-	int				nvalue_count;
-	bool				enable_on_init;
-	struct omap_sr_nvalue_table	*nvalue_table;
-	struct voltagedomain		*voltdm;
-};
-
 /* Smartreflex module enable/disable interface */
 void omap_sr_enable(struct voltagedomain *voltdm);
 void omap_sr_disable(struct voltagedomain *voltdm);
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index a503e1e..86e438e 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -17,6 +17,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/power/smartreflex.h>
 
 #include <linux/err.h>
 #include <linux/slab.h>
@@ -24,7 +25,6 @@
 
 #include <plat/omap_device.h>
 
-#include "smartreflex.h"
 #include "voltage.h"
 #include "control.h"
 #include "pm.h"
diff --git a/include/linux/power/smartreflex.h b/include/linux/power/smartreflex.h
new file mode 100644
index 0000000..4a15640
--- /dev/null
+++ b/include/linux/power/smartreflex.h
@@ -0,0 +1,67 @@
+/*
+ * OMAP Smartreflex Defines and Routines
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Jean Pihet <j-pihet at ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970 at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __POWER_SMARTREFLEX_H
+#define __POWER_SMARTREFLEX_H
+
+#include <linux/types.h>
+
+#include <plat/voltage.h>
+
+/**
+ * struct omap_sr_nvalue_table	- Smartreflex n-target value info
+ *
+ * @efuse_offs:	The offset of the efuse where n-target values are stored.
+ * @nvalue:	The n-target value.
+ */
+struct omap_sr_nvalue_table {
+	u32 efuse_offs;
+	u32 nvalue;
+};
+
+/**
+ * struct omap_sr_data - Smartreflex platform data.
+ *
+ * @ip_type:		Smartreflex IP type.
+ * @senp_mod:		SENPENABLE value for the sr
+ * @senn_mod:		SENNENABLE value for sr
+ * @nvalue_count:	Number of distinct nvalues in the nvalue table
+ * @enable_on_init:	whether this sr module needs to enabled at
+ *			boot up or not.
+ * @nvalue_table:	table containing the  efuse offsets and nvalues
+ *			corresponding to them.
+ * @voltdm:		Pointer to the voltage domain associated with the SR
+ */
+struct omap_sr_data {
+	int				ip_type;
+	u32				senp_mod;
+	u32				senn_mod;
+	int				nvalue_count;
+	bool				enable_on_init;
+	struct omap_sr_nvalue_table	*nvalue_table;
+	struct voltagedomain		*voltdm;
+};
+
+/**
+ * struct omap_smartreflex_dev_attr - Smartreflex Device attribute.
+ *
+ * @sensor_voltdm_name:       Name of voltdomain of SR instance
+ */
+struct omap_smartreflex_dev_attr {
+	const char      *sensor_voltdm_name;
+};
+
+#endif
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Mon Mar 19 12:12:52 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Mon, 19 Mar 2012 17:12:52 +0100
Subject: [PATCH 3/9] ARM: OMAP3+: SmartReflex: class drivers should use struct
 omap_sr *
In-Reply-To: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
References: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
Message-ID: <1332173578-27422-4-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Convert SmartReflex "class" functions to take a struct omap_sr *, rather than
a struct voltagedomain *.  SmartReflex code should be driver code and not
tightly coupled to OMAP subarchitecture-specific structures.

Based on Paul's original code for the SmartReflex driver conversion.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Thara Gopinath <thara at ti.com>
Cc: Nishanth Menon <nm at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/smartreflex-class3.c |   24 +++++++++---------
 arch/arm/mach-omap2/smartreflex.c        |   37 +++++------------------------
 arch/arm/mach-omap2/smartreflex.h        |    9 ++++---
 include/linux/power/smartreflex.h        |   23 ++++++++++++++++++
 4 files changed, 47 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index e12c51e..54ba048 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -14,34 +14,34 @@
 #include "smartreflex.h"
 #include "voltage.h"
 
-static int sr_class3_enable(struct voltagedomain *voltdm)
+static int sr_class3_enable(struct omap_sr *sr)
 {
-	unsigned long volt = voltdm_get_voltage(voltdm);
+	unsigned long volt = voltdm_get_voltage(sr->voltdm);
 
 	if (!volt) {
 		pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
-				__func__, voltdm->name);
+				__func__, sr->voltdm->name);
 		return -ENODATA;
 	}
 
-	omap_vp_enable(voltdm);
-	return sr_enable(voltdm, volt);
+	omap_vp_enable(sr->voltdm);
+	return sr_enable(sr->voltdm, volt);
 }
 
-static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
+static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
 {
-	sr_disable_errgen(voltdm);
-	omap_vp_disable(voltdm);
-	sr_disable(voltdm);
+	sr_disable_errgen(sr->voltdm);
+	omap_vp_disable(sr->voltdm);
+	sr_disable(sr->voltdm);
 	if (is_volt_reset)
-		voltdm_reset(voltdm);
+		voltdm_reset(sr->voltdm);
 
 	return 0;
 }
 
-static int sr_class3_configure(struct voltagedomain *voltdm)
+static int sr_class3_configure(struct omap_sr *sr)
 {
-	return sr_configure_errgen(voltdm);
+	return sr_configure_errgen(sr->voltdm);
 }
 
 /* SR class3 structure */
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 33e2825..dbb6a0c 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -35,29 +35,6 @@
 #define NVALUE_NAME_LEN		40
 #define SR_DISABLE_TIMEOUT	200
 
-struct omap_sr {
-	struct list_head		node;
-	struct platform_device		*pdev;
-	struct omap_sr_nvalue_table	*nvalue_table;
-	struct voltagedomain		*voltdm;
-	struct dentry			*dbg_dir;
-	unsigned int			irq;
-	int				srid;
-	int				ip_type;
-	int				nvalue_count;
-	bool				autocomp_active;
-	u32				clk_length;
-	u32				err_weight;
-	u32				err_minlimit;
-	u32				err_maxlimit;
-	u32				accum_data;
-	u32				senn_avgweight;
-	u32				senp_avgweight;
-	u32				senp_mod;
-	u32				senn_mod;
-	void __iomem			*base;
-};
-
 /* sr_list contains all the instances of smartreflex module */
 static LIST_HEAD(sr_list);
 
@@ -148,7 +125,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
 	}
 
 	if (sr_class->notify)
-		sr_class->notify(sr_info->voltdm, status);
+		sr_class->notify(sr_info, status);
 
 	return IRQ_HANDLED;
 }
@@ -226,7 +203,7 @@ static void sr_start_vddautocomp(struct omap_sr *sr)
 		return;
 	}
 
-	if (!sr_class->enable(sr->voltdm))
+	if (!sr_class->enable(sr))
 		sr->autocomp_active = true;
 }
 
@@ -240,7 +217,7 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
 	}
 
 	if (sr->autocomp_active) {
-		sr_class->disable(sr->voltdm, 1);
+		sr_class->disable(sr, 1);
 		sr->autocomp_active = false;
 	}
 }
@@ -655,7 +632,7 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 		return 0;
 
 	/* Configure SR */
-	ret = sr_class->configure(voltdm);
+	ret = sr_class->configure(sr);
 	if (ret)
 		return ret;
 
@@ -773,7 +750,7 @@ void omap_sr_enable(struct voltagedomain *voltdm)
 		return;
 	}
 
-	sr_class->enable(voltdm);
+	sr_class->enable(sr);
 }
 
 /**
@@ -806,7 +783,7 @@ void omap_sr_disable(struct voltagedomain *voltdm)
 		return;
 	}
 
-	sr_class->disable(voltdm, 0);
+	sr_class->disable(sr, 0);
 }
 
 /**
@@ -839,7 +816,7 @@ void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
 		return;
 	}
 
-	sr_class->disable(voltdm, 1);
+	sr_class->disable(sr, 1);
 }
 
 /**
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 8835422..6f9b677 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -21,6 +21,7 @@
 #define __ASM_ARM_OMAP_SMARTREFLEX_H
 
 #include <linux/platform_device.h>
+#include <linux/power/smartreflex.h>
 
 #include <plat/voltage.h>
 
@@ -178,10 +179,10 @@ struct omap_sr_pmic_data {
  *			based decisions.
  */
 struct omap_sr_class_data {
-	int (*enable)(struct voltagedomain *voltdm);
-	int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
-	int (*configure)(struct voltagedomain *voltdm);
-	int (*notify)(struct voltagedomain *voltdm, u32 status);
+	int (*enable)(struct omap_sr *sr);
+	int (*disable)(struct omap_sr *sr, int is_volt_reset);
+	int (*configure)(struct omap_sr *sr);
+	int (*notify)(struct omap_sr *sr, u32 status);
 	u8 notify_flags;
 	u8 class_type;
 };
diff --git a/include/linux/power/smartreflex.h b/include/linux/power/smartreflex.h
index 4a15640..cf292ac 100644
--- a/include/linux/power/smartreflex.h
+++ b/include/linux/power/smartreflex.h
@@ -21,6 +21,29 @@
 
 #include <plat/voltage.h>
 
+struct omap_sr {
+	struct list_head		node;
+	struct platform_device		*pdev;
+	struct omap_sr_nvalue_table	*nvalue_table;
+	struct voltagedomain		*voltdm;
+	struct dentry			*dbg_dir;
+	unsigned int			irq;
+	int				srid;
+	int				ip_type;
+	int				nvalue_count;
+	bool				autocomp_active;
+	u32				clk_length;
+	u32				err_weight;
+	u32				err_minlimit;
+	u32				err_maxlimit;
+	u32				accum_data;
+	u32				senn_avgweight;
+	u32				senp_avgweight;
+	u32				senp_mod;
+	u32				senn_mod;
+	void __iomem			*base;
+};
+
 /**
  * struct omap_sr_nvalue_table	- Smartreflex n-target value info
  *
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Mon Mar 19 12:12:53 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Mon, 19 Mar 2012 17:12:53 +0100
Subject: [PATCH 4/9] ARM: OMAP2+: smartreflex: Use the names from hwmod data
 instead of voltage domains.
In-Reply-To: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
References: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
Message-ID: <1332173578-27422-5-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Associate a name with each SmartReflex instance from the hwmod data,
rather than attempting to reuse the name of a voltage domain. The name
from hwmod better reflects the smartreflex integration in the system.

Also have the name passed to the drivers using pdata, which helps to remove
any dependencies on SoC-specific structures.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/smartreflex-class3.c |    4 +-
 arch/arm/mach-omap2/smartreflex.c        |   65 ++++++++++++------------------
 arch/arm/mach-omap2/sr_device.c          |    1 +
 include/linux/power/smartreflex.h        |    3 +
 4 files changed, 32 insertions(+), 41 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 54ba048..f63c950 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -19,8 +19,8 @@ static int sr_class3_enable(struct omap_sr *sr)
 	unsigned long volt = voltdm_get_voltage(sr->voltdm);
 
 	if (!volt) {
-		pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
-				__func__, sr->voltdm->name);
+		pr_warning("%s: Curr voltage unknown. Cannot enable %s\n",
+				__func__, sr->name);
 		return -ENODATA;
 	}
 
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index dbb6a0c..c18d47d 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -184,7 +184,7 @@ static void sr_set_regfields(struct omap_sr *sr)
 		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
 		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
 		sr->accum_data = OMAP3430_SR_ACCUMDATA;
-		if (!(strcmp(sr->voltdm->name, "mpu"))) {
+		if (!(strcmp(sr->name, "sr1"))) {
 			sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
 			sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
 		} else {
@@ -235,19 +235,13 @@ static void sr_stop_vddautocomp(struct omap_sr *sr)
  */
 static int sr_late_init(struct omap_sr *sr_info)
 {
-	char *name;
 	struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
 	struct resource *mem;
 	int ret = 0;
 
 	if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
-		name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
-		if (name == NULL) {
-			ret = -ENOMEM;
-			goto error;
-		}
 		ret = request_irq(sr_info->irq, sr_interrupt,
-				0, name, sr_info);
+				  0, sr_info->name, sr_info);
 		if (ret)
 			goto error;
 		disable_irq(sr_info->irq);
@@ -266,7 +260,6 @@ error:
 	dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
 		"interrupt handler. Smartreflex will"
 		"not function as desired\n", __func__);
-	kfree(name);
 	kfree(sr_info);
 
 	return ret;
@@ -396,8 +389,7 @@ int sr_configure_errgen(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return PTR_ERR(sr);
 	}
 
@@ -464,8 +456,7 @@ int sr_disable_errgen(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return PTR_ERR(sr);
 	}
 
@@ -515,8 +506,7 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return PTR_ERR(sr);
 	}
 
@@ -601,8 +591,7 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 	int ret;
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return PTR_ERR(sr);
 	}
 
@@ -655,8 +644,7 @@ void sr_disable(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return;
 	}
 
@@ -736,8 +724,7 @@ void omap_sr_enable(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return;
 	}
 
@@ -769,8 +756,7 @@ void omap_sr_disable(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return;
 	}
 
@@ -802,8 +788,7 @@ void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
 	struct omap_sr *sr = _sr_lookup(voltdm);
 
 	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for sr_%s not found\n",
-			__func__, voltdm->name);
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
 		return;
 	}
 
@@ -890,7 +875,6 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 	struct dentry *nvalue_dir;
 	struct omap_volt_data *volt_data;
 	int i, ret = 0;
-	char *name;
 
 	sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
 	if (!sr_info) {
@@ -927,6 +911,14 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_irq_safe(&pdev->dev);
 
+	sr_info->name = kasprintf(GFP_KERNEL, "sr_%s", pdata->name);
+	if (!sr_info->name) {
+		dev_err(&pdev->dev, "%s: Unable to alloc SR instance name\n",
+			__func__);
+		ret = -ENOMEM;
+		goto err_release_region;
+	}
+
 	sr_info->pdev = pdev;
 	sr_info->srid = pdev->id;
 	sr_info->voltdm = pdata->voltdm;
@@ -974,20 +966,12 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 		}
 	}
 
-	name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
-	if (!name) {
-		dev_err(&pdev->dev, "%s: Unable to alloc debugfs name\n",
-			__func__);
-		ret = -ENOMEM;
-		goto err_iounmap;
-	}
-	sr_info->dbg_dir = debugfs_create_dir(name, sr_dbg_dir);
-	kfree(name);
+	sr_info->dbg_dir = debugfs_create_dir(sr_info->name, sr_dbg_dir);
 	if (IS_ERR_OR_NULL(sr_info->dbg_dir)) {
 		dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
 			__func__);
 		ret = PTR_ERR(sr_info->dbg_dir);
-		goto err_iounmap;
+		goto err_free_name;
 	}
 
 	(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
@@ -1009,10 +993,10 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 
 	omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
 	if (!volt_data) {
-		dev_warn(&pdev->dev, "%s: No Voltage table for the"
-			" corresponding vdd vdd_%s. Cannot create debugfs"
+		dev_warn(&pdev->dev, "%s: %s: No Voltage table for the"
+			" corresponding vdd. Cannot create debugfs"
 			"entries for n-values\n",
-			__func__, sr_info->voltdm->name);
+			__func__, sr_info->name);
 		ret = -ENODATA;
 		goto err_debugfs;
 	}
@@ -1030,6 +1014,8 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 
 err_debugfs:
 	debugfs_remove_recursive(sr_info->dbg_dir);
+err_free_name:
+	kfree(sr_info->name);
 err_iounmap:
 	list_del(&sr_info->node);
 	iounmap(sr_info->base);
@@ -1066,6 +1052,7 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
 
 	list_del(&sr_info->node);
 	iounmap(sr_info->base);
+	kfree(sr_info->name);
 	kfree(sr_info);
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	release_mem_region(mem->start, resource_size(mem));
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 86e438e..e081174 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -93,6 +93,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 		goto exit;
 	}
 
+	sr_data->name = oh->name;
 	sr_data->ip_type = oh->class->rev;
 	sr_data->senn_mod = 0x1;
 	sr_data->senp_mod = 0x1;
diff --git a/include/linux/power/smartreflex.h b/include/linux/power/smartreflex.h
index cf292ac..e7dff08 100644
--- a/include/linux/power/smartreflex.h
+++ b/include/linux/power/smartreflex.h
@@ -22,6 +22,7 @@
 #include <plat/voltage.h>
 
 struct omap_sr {
+	char				*name;
 	struct list_head		node;
 	struct platform_device		*pdev;
 	struct omap_sr_nvalue_table	*nvalue_table;
@@ -58,6 +59,7 @@ struct omap_sr_nvalue_table {
 /**
  * struct omap_sr_data - Smartreflex platform data.
  *
+ * @name:		instance name
  * @ip_type:		Smartreflex IP type.
  * @senp_mod:		SENPENABLE value for the sr
  * @senn_mod:		SENNENABLE value for sr
@@ -69,6 +71,7 @@ struct omap_sr_nvalue_table {
  * @voltdm:		Pointer to the voltage domain associated with the SR
  */
 struct omap_sr_data {
+	const char			*name;
 	int				ip_type;
 	u32				senp_mod;
 	u32				senn_mod;
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Mon Mar 19 12:12:54 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Mon, 19 Mar 2012 17:12:54 +0100
Subject: [PATCH 5/9] ARM: OMAP3: hwmod: rename the smartreflex entries
In-Reply-To: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
References: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
Message-ID: <1332173578-27422-6-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Change the name field value to better reflect the smartreflex
integration in the system

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |    8 ++++----
 arch/arm/mach-omap2/smartreflex.c          |    2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index d7d4c70..40f57c4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2751,7 +2751,7 @@ static struct omap_hwmod_ocp_if *omap34xx_sr1_slaves[] = {
 };
 
 static struct omap_hwmod omap34xx_sr1_hwmod = {
-	.name		= "sr1",
+	.name		= "mpu_iva",
 	.class		= &omap34xx_smartreflex_hwmod_class,
 	.main_clk	= "sr1_fck",
 	.prcm		= {
@@ -2775,7 +2775,7 @@ static struct omap_hwmod_ocp_if *omap36xx_sr1_slaves[] = {
 };
 
 static struct omap_hwmod omap36xx_sr1_hwmod = {
-	.name		= "sr1",
+	.name		= "mpu_iva",
 	.class		= &omap36xx_smartreflex_hwmod_class,
 	.main_clk	= "sr1_fck",
 	.prcm		= {
@@ -2803,7 +2803,7 @@ static struct omap_hwmod_ocp_if *omap34xx_sr2_slaves[] = {
 };
 
 static struct omap_hwmod omap34xx_sr2_hwmod = {
-	.name		= "sr2",
+	.name		= "core",
 	.class		= &omap34xx_smartreflex_hwmod_class,
 	.main_clk	= "sr2_fck",
 	.prcm		= {
@@ -2827,7 +2827,7 @@ static struct omap_hwmod_ocp_if *omap36xx_sr2_slaves[] = {
 };
 
 static struct omap_hwmod omap36xx_sr2_hwmod = {
-	.name		= "sr2",
+	.name		= "core",
 	.class		= &omap36xx_smartreflex_hwmod_class,
 	.main_clk	= "sr2_fck",
 	.prcm		= {
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index c18d47d..b2728a5 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -184,7 +184,7 @@ static void sr_set_regfields(struct omap_sr *sr)
 		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
 		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
 		sr->accum_data = OMAP3430_SR_ACCUMDATA;
-		if (!(strcmp(sr->name, "sr1"))) {
+		if (!(strcmp(sr->name, "sr_mpu_iva"))) {
 			sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
 			sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
 		} else {
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Mon Mar 19 12:12:55 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Mon, 19 Mar 2012 17:12:55 +0100
Subject: [PATCH 6/9] ARM: OMAP2+: SmartReflex: introduce a busy loop condition
 test macro
In-Reply-To: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
References: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
Message-ID: <1332173578-27422-7-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Now that omap_test_timeout is only accessible from mach-omap2/,
introduce a similar function for SR.

This change makes the SmartReflex implementation ready for the move
to drivers/.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |   12 ++++++------
 arch/arm/mach-omap2/smartreflex.h |   23 +++++++++++++++++++++++
 2 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index b2728a5..5f3faf3 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -290,9 +290,9 @@ static void sr_v1_disable(struct omap_sr *sr)
 	 * Wait for SR to be disabled.
 	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
 	 */
-	omap_test_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
-			ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
-			timeout);
+	sr_test_cond_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
+			     ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
+			     timeout);
 
 	if (timeout >= SR_DISABLE_TIMEOUT)
 		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
@@ -335,9 +335,9 @@ static void sr_v2_disable(struct omap_sr *sr)
 	 * Wait for SR to be disabled.
 	 * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
 	 */
-	omap_test_timeout((sr_read_reg(sr, IRQSTATUS) &
-			IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
-			timeout);
+	sr_test_cond_timeout((sr_read_reg(sr, IRQSTATUS) &
+			     IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
+			     timeout);
 
 	if (timeout >= SR_DISABLE_TIMEOUT)
 		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 6f9b677..a87bac1 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -21,6 +21,7 @@
 #define __ASM_ARM_OMAP_SMARTREFLEX_H
 
 #include <linux/platform_device.h>
+#include <linux/delay.h>
 #include <linux/power/smartreflex.h>
 
 #include <plat/voltage.h>
@@ -144,6 +145,28 @@
 #define OMAP3430_SR_ERRMAXLIMIT		0x02
 
 /**
+ * test_cond_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ *
+ * Copied from omap_test_timeout
+ */
+#define sr_test_cond_timeout(cond, timeout, index)		\
+({								\
+	for (index = 0; index < timeout; index++) {		\
+		if (cond)					\
+			break;					\
+		udelay(1);					\
+	}							\
+})
+
+/**
  * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
  *				pmic specific info to smartreflex driver
  *
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Mon Mar 19 12:12:56 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Mon, 19 Mar 2012 17:12:56 +0100
Subject: [PATCH 7/9] ARM: OMAP2+: SmartReflex: Use per-OPP data structure
In-Reply-To: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
References: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
Message-ID: <1332173578-27422-8-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

The SmartReflex driver incorrectly treats some per-OPP data as data
common to all OPPs (e.g., ERRMINLIMIT).  Move this data into a per-OPP
data structure.
The SmartReflex driver should not be dependent on whether the host SoC
uses eFuses to store SmartReflex parameters or not.  (Even SoCs that
do store SR data in eFuses often need to override that data with
software-defined values.)  So, convert sr_retrieve_nvalue() to look up
per-OPP data by the OPP's nominal voltage, rather than by the eFuse
offset.

While at it:
 . tidy up the code wrt default values in the data tables,
 . remove the global errminlimit debugfs entry and create per-voltage
   entries from the data tables.

Furthermore, in order to make the SmartReflex implementation ready for
the move to drivers/, remove the dependency from the SR driver code
to the voltage layer by querying the data tables only from the SR device
init code.

Based on Paul's original code for the SmartReflex driver conversion.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Thara Gopinath <thara at ti.com>
Cc: Nishanth Menon <nm at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/smartreflex.c |   57 +++++++++++++++---------------------
 arch/arm/mach-omap2/sr_device.c   |   35 +++++++++++++++++++----
 include/linux/power/smartreflex.h |    8 ++++-
 3 files changed, 59 insertions(+), 41 deletions(-)

diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 5f3faf3..71f70ca 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -348,22 +348,24 @@ static void sr_v2_disable(struct omap_sr *sr)
 	sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
 }
 
-static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
+static struct omap_sr_nvalue_table *sr_retrieve_nvalue_row(
+				struct omap_sr *sr,
+				unsigned long volt_nominal)
 {
 	int i;
 
 	if (!sr->nvalue_table) {
 		dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
 			__func__);
-		return 0;
+		return NULL;
 	}
 
 	for (i = 0; i < sr->nvalue_count; i++) {
-		if (sr->nvalue_table[i].efuse_offs == efuse_offs)
-			return sr->nvalue_table[i].nvalue;
+		if (sr->nvalue_table[i].volt_nominal == volt_nominal)
+			return &sr->nvalue_table[i];
 	}
 
-	return 0;
+	return NULL;
 }
 
 /* Public Functions */
@@ -585,9 +587,8 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
  */
 int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 {
-	struct omap_volt_data *volt_data;
 	struct omap_sr *sr = _sr_lookup(voltdm);
-	u32 nvalue_reciprocal;
+	struct omap_sr_nvalue_table *nvalue_row;
 	int ret;
 
 	if (IS_ERR(sr)) {
@@ -595,24 +596,16 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 		return PTR_ERR(sr);
 	}
 
-	volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
-
-	if (IS_ERR(volt_data)) {
-		dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table"
-			"for nominal voltage %ld\n", __func__, volt);
-		return PTR_ERR(volt_data);
-	}
-
-	nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs);
-
-	if (!nvalue_reciprocal) {
-		dev_warn(&sr->pdev->dev, "%s: NVALUE = 0 at voltage %ld\n",
-			__func__, volt);
+	nvalue_row = sr_retrieve_nvalue_row(sr, volt);
+	if (!nvalue_row) {
+		dev_warn(&sr->pdev->dev, "%s: failure getting SR data for this voltage %ld\n",
+			 __func__, volt);
 		return -ENODATA;
 	}
 
+
 	/* errminlimit is opp dependent and hence linked to voltage */
-	sr->err_minlimit = volt_data->sr_errminlimit;
+	sr->err_minlimit = nvalue_row->errminlimit;
 
 	pm_runtime_get_sync(&sr->pdev->dev);
 
@@ -625,7 +618,7 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 	if (ret)
 		return ret;
 
-	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
+	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_row->nvalue);
 
 	/* SRCONFIG - enable SR */
 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
@@ -873,7 +866,6 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 	struct omap_sr_data *pdata = pdev->dev.platform_data;
 	struct resource *mem, *irq;
 	struct dentry *nvalue_dir;
-	struct omap_volt_data *volt_data;
 	int i, ret = 0;
 
 	sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
@@ -980,8 +972,6 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 			&sr_info->err_weight);
 	(void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
 			&sr_info->err_maxlimit);
-	(void) debugfs_create_x32("errminlimit", S_IRUGO, sr_info->dbg_dir,
-			&sr_info->err_minlimit);
 
 	nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
 	if (IS_ERR_OR_NULL(nvalue_dir)) {
@@ -991,12 +981,9 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 		goto err_debugfs;
 	}
 
-	omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
-	if (!volt_data) {
-		dev_warn(&pdev->dev, "%s: %s: No Voltage table for the"
-			" corresponding vdd. Cannot create debugfs"
-			"entries for n-values\n",
-			__func__, sr_info->name);
+	if (sr_info->nvalue_count == 0 || !sr_info->nvalue_table) {
+		dev_warn(&pdev->dev, "%s: %s: No Voltage table for the corresponding vdd. Cannot create debugfs entries for n-values\n",
+			 __func__, sr_info->name);
 		ret = -ENODATA;
 		goto err_debugfs;
 	}
@@ -1004,10 +991,14 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 	for (i = 0; i < sr_info->nvalue_count; i++) {
 		char name[NVALUE_NAME_LEN + 1];
 
-		snprintf(name, sizeof(name), "volt_%d",
-			 volt_data[i].volt_nominal);
+		snprintf(name, sizeof(name), "volt_%lu",
+			 sr_info->nvalue_table[i].volt_nominal);
 		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
 				&(sr_info->nvalue_table[i].nvalue));
+		snprintf(name, sizeof(name), "errminlimit_%lu",
+			 sr_info->nvalue_table[i].volt_nominal);
+		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
+				&(sr_info->nvalue_table[i].errminlimit));
 	}
 
 	return ret;
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index e081174..67d967e 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -36,7 +36,10 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
 				struct omap_sr_data *sr_data)
 {
 	struct omap_sr_nvalue_table *nvalue_table;
-	int i, count = 0;
+	int i, j, count = 0;
+
+	sr_data->nvalue_count = 0;
+	sr_data->nvalue_table = NULL;
 
 	while (volt_data[count].volt_nominal)
 		count++;
@@ -44,8 +47,14 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
 	nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count,
 			GFP_KERNEL);
 
-	for (i = 0; i < count; i++) {
+	if (!nvalue_table) {
+		pr_err("OMAP: SmartReflex: cannot allocate memory for n-value table\n");
+		return;
+	}
+
+	for (i = 0, j = 0; i < count; i++) {
 		u32 v;
+
 		/*
 		 * In OMAP4 the efuse registers are 24 bit aligned.
 		 * A __raw_readl will fail for non-32 bit aligned address
@@ -58,15 +67,29 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
 				omap_ctrl_readb(offset + 1) << 8 |
 				omap_ctrl_readb(offset + 2) << 16;
 		} else {
-			 v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+			v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
 		}
 
-		nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs;
-		nvalue_table[i].nvalue = v;
+		/*
+		 * Many OMAP SoCs don't have the eFuse values set.
+		 * For example, pretty much all OMAP3xxx before
+		 * ES3.something.
+		 *
+		 * XXX There needs to be some way for board files or
+		 * userspace to add these in.
+		 */
+		if (v == 0)
+			continue;
+
+		nvalue_table[j].nvalue = v;
+		nvalue_table[j].errminlimit = volt_data[i].sr_errminlimit;
+		nvalue_table[j].volt_nominal = volt_data[i].volt_nominal;
+
+		j++;
 	}
 
 	sr_data->nvalue_table = nvalue_table;
-	sr_data->nvalue_count = count;
+	sr_data->nvalue_count = j;
 }
 
 static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
diff --git a/include/linux/power/smartreflex.h b/include/linux/power/smartreflex.h
index e7dff08..0f7c81b 100644
--- a/include/linux/power/smartreflex.h
+++ b/include/linux/power/smartreflex.h
@@ -48,12 +48,16 @@ struct omap_sr {
 /**
  * struct omap_sr_nvalue_table	- Smartreflex n-target value info
  *
- * @efuse_offs:	The offset of the efuse where n-target values are stored.
- * @nvalue:	The n-target value.
+ * @efuse_offs:	  The offset of the efuse where n-target values are stored.
+ * @nvalue:	  The n-target value.
+ * @errminlimit:  The value of the ERRMINLIMIT bitfield for this n-target
+ * @volt_nominal: microvolts DC that the VDD is initially programmed to
  */
 struct omap_sr_nvalue_table {
 	u32 efuse_offs;
 	u32 nvalue;
+	u32 errminlimit;
+	unsigned long volt_nominal;
 };
 
 /**
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Mon Mar 19 12:12:57 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Mon, 19 Mar 2012 17:12:57 +0100
Subject: [PATCH 8/9] ARM: OMAP2+: SmartReflex: add POWER_AVS Kconfig options
In-Reply-To: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
References: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
Message-ID: <1332173578-27422-9-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

Add a Kconfig menu (POWER_AVS) and rename the Kconfig options
for the OMAP SmartReflex implementation:
 CONFIG_OMAP_SMARTREFLEX renames to CONFIG_POWER_AVS_OMAP
 CONFIG_OMAP_SMARTREFLEX_CLASS3 renames to CONFIG_POWER_AVS_OMAP_CLASS3

This change makes the SmartReflex implementation ready for the move
to drivers/.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/Makefile      |    5 ++-
 arch/arm/mach-omap2/pm.h          |    2 +-
 arch/arm/mach-omap2/smartreflex.h |    6 ++--
 arch/arm/plat-omap/Kconfig        |   45 ++++++++++++++++++++++++------------
 4 files changed, 37 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9746529..30666fd 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -68,8 +68,9 @@ obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o \
 obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o omap-mpuss-lowpower.o \
 					   cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
-obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
-obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-class3.o
+
+obj-$(CONFIG_POWER_AVS_OMAP)		+= sr_device.o smartreflex.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)	+= smartreflex-class3.o
 
 AFLAGS_sleep24xx.o			:=-Wa,-march=armv6
 AFLAGS_sleep34xx.o			:=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index a051431..1a2d483 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -110,7 +110,7 @@ extern void enable_omap3630_toggle_l2_on_restore(void);
 static inline void enable_omap3630_toggle_l2_on_restore(void) { }
 #endif		/* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
 
-#ifdef CONFIG_OMAP_SMARTREFLEX
+#ifdef CONFIG_POWER_AVS_OMAP
 extern int omap_devinit_smartreflex(void);
 extern void omap_enable_smartreflex_on_init(void);
 #else
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index a87bac1..754f6aa 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -17,8 +17,8 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
-#define __ASM_ARM_OMAP_SMARTREFLEX_H
+#ifndef __DRIVERS_POWER_AVS_SMARTREFLEX_H
+#define __DRIVERS_POWER_AVS_SMARTREFLEX_H
 
 #include <linux/platform_device.h>
 #include <linux/delay.h>
@@ -177,7 +177,7 @@ struct omap_sr_pmic_data {
 };
 
 
-#ifdef CONFIG_OMAP_SMARTREFLEX
+#ifdef CONFIG_POWER_AVS_OMAP
 /*
  * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
  * The smartreflex class driver should pass the class type.
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index f419a08..6ec9237 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -44,37 +44,52 @@ config OMAP_DEBUG_LEDS
 	depends on OMAP_DEBUG_DEVICES
 	default y if LEDS_CLASS
 
-config OMAP_SMARTREFLEX
-	bool "SmartReflex support"
-	depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
+menuconfig POWER_AVS
+	tristate "Adaptive Voltage Scaling class support"
 	help
-	  Say Y if you want to enable SmartReflex.
+	  AVS is a power management technique which finely controls the
+	  operating voltage of a device in order to optimize (i.e. reduce)
+	  its power consumption.
+	  At a given operating point the voltage is adapted depending on
+	  static factors (chip manufacturing process) and dynamic factors
+	  (temperature depending performance).
+	  AVS is also called SmartReflex on OMAP devices.
+
+	  Say Y here to enable Adaptive Voltage Scaling class support.
+
+if POWER_AVS
 
-	  SmartReflex can perform continuous dynamic voltage
-	  scaling around the nominal operating point voltage
-	  according to silicon characteristics and operating
-	  conditions. Enabling SmartReflex reduces power
-	  consumption.
+config POWER_AVS_OMAP
+	bool "AVS support for the OMAP IP versions 1&2"
+	depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
+	help
+	  Say Y to enable AVS support on OMAP containing the version 1 or
+	  version 2 of the SmartReflex IP.
+	  V1 is the 65nm version used in OMAP3430.
+	  V2 is the update for the 45nm version of the IP used in OMAP3630
+	  and OMAP4430
 
 	  Please note, that by default SmartReflex is only
-	  initialized. To enable the automatic voltage
-	  compensation for vdd mpu  and vdd core from user space,
+	  initialized and not enabled. To enable the automatic voltage
+	  compensation for vdd mpu and vdd core from user space,
 	  user must write 1 to
-		/debug/voltage/vdd_<X>/smartreflex/autocomp,
-	  where X is mpu or core for OMAP3.
+		/debug/smartreflex/sr_<X>/autocomp,
+	  where X is mpu_iva or core for OMAP3.
 	  Optionally autocompensation can be enabled in the kernel
 	  by default during system init via the enable_on_init flag
 	  which an be passed as platform data to the smartreflex driver.
 
-config OMAP_SMARTREFLEX_CLASS3
+config POWER_AVS_OMAP_CLASS3
 	bool "Class 3 mode of Smartreflex Implementation"
-	depends on OMAP_SMARTREFLEX && TWL4030_CORE
+	depends on POWER_AVS_OMAP && TWL4030_CORE
 	help
 	  Say Y to enable Class 3 implementation of Smartreflex
 
 	  Class 3 implementation of Smartreflex employs continuous hardware
 	  voltage calibration.
 
+endif # POWER_AVS
+
 config OMAP_RESET_CLOCKS
 	bool "Reset unused clocks during boot"
 	depends on ARCH_OMAP
-- 
1.7.5.4



From jean.pihet at newoldbits.com  Mon Mar 19 12:12:58 2012
From: jean.pihet at newoldbits.com (jean.pihet at newoldbits.com)
Date: Mon, 19 Mar 2012 17:12:58 +0100
Subject: [PATCH 9/9] ARM: OMAP: SmartReflex: Move smartreflex driver to
 drivers/
In-Reply-To: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
References: <1332173578-27422-1-git-send-email-j-pihet@ti.com>
Message-ID: <1332173578-27422-10-git-send-email-j-pihet@ti.com>

From: Jean Pihet <j-pihet at ti.com>

After a clean-up of the interfaces the OMAP IP driver and class
support code is now a generic driver.
Move it to drivers/power/avs/.

The build is controlled by the following Kconfig options:
 . CONFIG_POWER_AVS: general knob for Adaptive Voltage Scaling support,
 . CONFIG_POWER_AVS_OMAP: AVS support on OMAP containing the version 1
    or version 2 of the SmartReflex IP,
 . CONFIG_POWER_AVS_OMAP_CLASS3: Class 3 implementation of Smartreflex.

Signed-off-by: Jean Pihet <j-pihet at ti.com>
---
 arch/arm/mach-omap2/Makefile             |    3 +-
 arch/arm/mach-omap2/smartreflex-class3.c |   61 --
 arch/arm/mach-omap2/smartreflex.c        | 1120 ------------------------------
 arch/arm/mach-omap2/smartreflex.h        |  238 -------
 arch/arm/plat-omap/Kconfig               |   19 +-
 drivers/power/Kconfig                    |    2 +
 drivers/power/Makefile                   |    2 +
 drivers/power/avs/Kconfig                |   12 +
 drivers/power/avs/Makefile               |    2 +
 drivers/power/avs/smartreflex-class3.c   |   61 ++
 drivers/power/avs/smartreflex.c          | 1118 +++++++++++++++++++++++++++++
 drivers/power/avs/smartreflex.h          |  238 +++++++
 12 files changed, 1437 insertions(+), 1439 deletions(-)
 delete mode 100644 arch/arm/mach-omap2/smartreflex-class3.c
 delete mode 100644 arch/arm/mach-omap2/smartreflex.c
 delete mode 100644 arch/arm/mach-omap2/smartreflex.h
 create mode 100644 drivers/power/avs/Kconfig
 create mode 100644 drivers/power/avs/Makefile
 create mode 100644 drivers/power/avs/smartreflex-class3.c
 create mode 100644 drivers/power/avs/smartreflex.c
 create mode 100644 drivers/power/avs/smartreflex.h

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 30666fd..bb23056 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -69,8 +69,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o omap-mpuss-lowpower.o \
 					   cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 
-obj-$(CONFIG_POWER_AVS_OMAP)		+= sr_device.o smartreflex.o
-obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)	+= smartreflex-class3.o
+obj-$(CONFIG_POWER_AVS_OMAP)		+= sr_device.o
 
 AFLAGS_sleep24xx.o			:=-Wa,-march=armv6
 AFLAGS_sleep34xx.o			:=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
deleted file mode 100644
index f63c950..0000000
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Smart reflex Class 3 specific implementations
- *
- * Author: Thara Gopinath       <thara at ti.com>
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- * Thara Gopinath <thara at ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include "smartreflex.h"
-#include "voltage.h"
-
-static int sr_class3_enable(struct omap_sr *sr)
-{
-	unsigned long volt = voltdm_get_voltage(sr->voltdm);
-
-	if (!volt) {
-		pr_warning("%s: Curr voltage unknown. Cannot enable %s\n",
-				__func__, sr->name);
-		return -ENODATA;
-	}
-
-	omap_vp_enable(sr->voltdm);
-	return sr_enable(sr->voltdm, volt);
-}
-
-static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
-{
-	sr_disable_errgen(sr->voltdm);
-	omap_vp_disable(sr->voltdm);
-	sr_disable(sr->voltdm);
-	if (is_volt_reset)
-		voltdm_reset(sr->voltdm);
-
-	return 0;
-}
-
-static int sr_class3_configure(struct omap_sr *sr)
-{
-	return sr_configure_errgen(sr->voltdm);
-}
-
-/* SR class3 structure */
-static struct omap_sr_class_data class3_data = {
-	.enable = sr_class3_enable,
-	.disable = sr_class3_disable,
-	.configure = sr_class3_configure,
-	.class_type = SR_CLASS3,
-};
-
-/* Smartreflex Class3 init API to be called from board file */
-static int __init sr_class3_init(void)
-{
-	pr_info("SmartReflex Class3 initialized\n");
-	return sr_register_class(&class3_data);
-}
-late_initcall(sr_class3_init);
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
deleted file mode 100644
index 71f70ca..0000000
--- a/arch/arm/mach-omap2/smartreflex.c
+++ /dev/null
@@ -1,1120 +0,0 @@
-/*
- * OMAP SmartReflex Voltage Control
- *
- * Author: Thara Gopinath	<thara at ti.com>
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- * Thara Gopinath <thara at ti.com>
- *
- * Copyright (C) 2008 Nokia Corporation
- * Kalle Jokiniemi
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Lesly A M <x0080970 at ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/pm_runtime.h>
-#include <linux/power/smartreflex.h>
-
-#include "common.h"
-#include "pm.h"
-#include "smartreflex.h"
-
-#define SMARTREFLEX_NAME_LEN	16
-#define NVALUE_NAME_LEN		40
-#define SR_DISABLE_TIMEOUT	200
-
-/* sr_list contains all the instances of smartreflex module */
-static LIST_HEAD(sr_list);
-
-static struct omap_sr_class_data *sr_class;
-static struct omap_sr_pmic_data *sr_pmic_data;
-static struct dentry		*sr_dbg_dir;
-
-static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
-{
-	__raw_writel(value, (sr->base + offset));
-}
-
-static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
-					u32 value)
-{
-	u32 reg_val;
-
-	/*
-	 * Smartreflex error config register is special as it contains
-	 * certain status bits which if written a 1 into means a clear
-	 * of those bits. So in order to make sure no accidental write of
-	 * 1 happens to those status bits, do a clear of them in the read
-	 * value. This mean this API doesn't rewrite values in these bits
-	 * if they are currently set, but does allow the caller to write
-	 * those bits.
-	 */
-	if (sr->ip_type == SR_TYPE_V1 && offset == ERRCONFIG_V1)
-		mask |= ERRCONFIG_STATUS_V1_MASK;
-	else if (sr->ip_type == SR_TYPE_V2 && offset == ERRCONFIG_V2)
-		mask |= ERRCONFIG_VPBOUNDINTST_V2;
-
-	reg_val = __raw_readl(sr->base + offset);
-	reg_val &= ~mask;
-
-	value &= mask;
-
-	reg_val |= value;
-
-	__raw_writel(reg_val, (sr->base + offset));
-}
-
-static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
-{
-	return __raw_readl(sr->base + offset);
-}
-
-static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
-{
-	struct omap_sr *sr_info;
-
-	if (!voltdm) {
-		pr_err("%s: Null voltage domain passed!\n", __func__);
-		return ERR_PTR(-EINVAL);
-	}
-
-	list_for_each_entry(sr_info, &sr_list, node) {
-		if (voltdm == sr_info->voltdm)
-			return sr_info;
-	}
-
-	return ERR_PTR(-ENODATA);
-}
-
-static irqreturn_t sr_interrupt(int irq, void *data)
-{
-	struct omap_sr *sr_info = data;
-	u32 status = 0;
-
-	switch (sr_info->ip_type) {
-	case SR_TYPE_V1:
-		/* Read the status bits */
-		status = sr_read_reg(sr_info, ERRCONFIG_V1);
-
-		/* Clear them by writing back */
-		sr_write_reg(sr_info, ERRCONFIG_V1, status);
-		break;
-	case SR_TYPE_V2:
-		/* Read the status bits */
-		status = sr_read_reg(sr_info, IRQSTATUS);
-
-		/* Clear them by writing back */
-		sr_write_reg(sr_info, IRQSTATUS, status);
-		break;
-	default:
-		dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n",
-			sr_info->ip_type);
-		return IRQ_NONE;
-	}
-
-	if (sr_class->notify)
-		sr_class->notify(sr_info, status);
-
-	return IRQ_HANDLED;
-}
-
-static void sr_set_clk_length(struct omap_sr *sr)
-{
-	struct clk *sys_ck;
-	u32 sys_clk_speed;
-
-	if (cpu_is_omap34xx())
-		sys_ck = clk_get(NULL, "sys_ck");
-	else
-		sys_ck = clk_get(NULL, "sys_clkin_ck");
-
-	if (IS_ERR(sys_ck)) {
-		dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
-			__func__);
-		return;
-	}
-
-	sys_clk_speed = clk_get_rate(sys_ck);
-	clk_put(sys_ck);
-
-	switch (sys_clk_speed) {
-	case 12000000:
-		sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
-		break;
-	case 13000000:
-		sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
-		break;
-	case 19200000:
-		sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
-		break;
-	case 26000000:
-		sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
-		break;
-	case 38400000:
-		sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
-		break;
-	default:
-		dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n",
-			__func__, sys_clk_speed);
-		break;
-	}
-}
-
-static void sr_set_regfields(struct omap_sr *sr)
-{
-	/*
-	 * For time being these values are defined in smartreflex.h
-	 * and populated during init. May be they can be moved to board
-	 * file or pmic specific data structure. In that case these structure
-	 * fields will have to be populated using the pdata or pmic structure.
-	 */
-	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
-		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
-		sr->accum_data = OMAP3430_SR_ACCUMDATA;
-		if (!(strcmp(sr->name, "sr_mpu_iva"))) {
-			sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
-			sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
-		} else {
-			sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
-			sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
-		}
-	}
-}
-
-static void sr_start_vddautocomp(struct omap_sr *sr)
-{
-	if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
-		dev_warn(&sr->pdev->dev,
-			"%s: smartreflex class driver not registered\n",
-			__func__);
-		return;
-	}
-
-	if (!sr_class->enable(sr))
-		sr->autocomp_active = true;
-}
-
-static void sr_stop_vddautocomp(struct omap_sr *sr)
-{
-	if (!sr_class || !(sr_class->disable)) {
-		dev_warn(&sr->pdev->dev,
-			"%s: smartreflex class driver not registered\n",
-			__func__);
-		return;
-	}
-
-	if (sr->autocomp_active) {
-		sr_class->disable(sr, 1);
-		sr->autocomp_active = false;
-	}
-}
-
-/*
- * This function handles the intializations which have to be done
- * only when both sr device and class driver regiter has
- * completed. This will be attempted to be called from both sr class
- * driver register and sr device intializtion API's. Only one call
- * will ultimately succeed.
- *
- * Currently this function registers interrupt handler for a particular SR
- * if smartreflex class driver is already registered and has
- * requested for interrupts and the SR interrupt line in present.
- */
-static int sr_late_init(struct omap_sr *sr_info)
-{
-	struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
-	struct resource *mem;
-	int ret = 0;
-
-	if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
-		ret = request_irq(sr_info->irq, sr_interrupt,
-				  0, sr_info->name, sr_info);
-		if (ret)
-			goto error;
-		disable_irq(sr_info->irq);
-	}
-
-	if (pdata && pdata->enable_on_init)
-		sr_start_vddautocomp(sr_info);
-
-	return ret;
-
-error:
-	iounmap(sr_info->base);
-	mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
-	release_mem_region(mem->start, resource_size(mem));
-	list_del(&sr_info->node);
-	dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
-		"interrupt handler. Smartreflex will"
-		"not function as desired\n", __func__);
-	kfree(sr_info);
-
-	return ret;
-}
-
-static void sr_v1_disable(struct omap_sr *sr)
-{
-	int timeout = 0;
-	int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
-			ERRCONFIG_MCUBOUNDINTST;
-
-	/* Enable MCUDisableAcknowledge interrupt */
-	sr_modify_reg(sr, ERRCONFIG_V1,
-			ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
-
-	/* SRCONFIG - disable SR */
-	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
-
-	/* Disable all other SR interrupts and clear the status as needed */
-	if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1)
-		errconf_val |= ERRCONFIG_VPBOUNDINTST_V1;
-	sr_modify_reg(sr, ERRCONFIG_V1,
-			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
-			ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
-			errconf_val);
-
-	/*
-	 * Wait for SR to be disabled.
-	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
-	 */
-	sr_test_cond_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
-			     ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
-			     timeout);
-
-	if (timeout >= SR_DISABLE_TIMEOUT)
-		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
-			__func__);
-
-	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
-	sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
-			ERRCONFIG_MCUDISACKINTST);
-}
-
-static void sr_v2_disable(struct omap_sr *sr)
-{
-	int timeout = 0;
-
-	/* Enable MCUDisableAcknowledge interrupt */
-	sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
-
-	/* SRCONFIG - disable SR */
-	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
-
-	/*
-	 * Disable all other SR interrupts and clear the status
-	 * write to status register ONLY on need basis - only if status
-	 * is set.
-	 */
-	if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2)
-		sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
-			ERRCONFIG_VPBOUNDINTST_V2);
-	else
-		sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
-				0x0);
-	sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
-			IRQENABLE_MCUVALIDINT |
-			IRQENABLE_MCUBOUNDSINT));
-	sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
-			IRQSTATUS_MCVALIDINT |
-			IRQSTATUS_MCBOUNDSINT));
-
-	/*
-	 * Wait for SR to be disabled.
-	 * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
-	 */
-	sr_test_cond_timeout((sr_read_reg(sr, IRQSTATUS) &
-			     IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
-			     timeout);
-
-	if (timeout >= SR_DISABLE_TIMEOUT)
-		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
-			__func__);
-
-	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
-	sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
-	sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
-}
-
-static struct omap_sr_nvalue_table *sr_retrieve_nvalue_row(
-				struct omap_sr *sr,
-				unsigned long volt_nominal)
-{
-	int i;
-
-	if (!sr->nvalue_table) {
-		dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
-			__func__);
-		return NULL;
-	}
-
-	for (i = 0; i < sr->nvalue_count; i++) {
-		if (sr->nvalue_table[i].volt_nominal == volt_nominal)
-			return &sr->nvalue_table[i];
-	}
-
-	return NULL;
-}
-
-/* Public Functions */
-
-/**
- * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the
- *			 error generator module.
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * configure the error generator module inside the smartreflex module.
- * SR settings if using the ERROR module inside Smartreflex.
- * SR CLASS 3 by default uses only the ERROR module where as
- * SR CLASS 2 can choose between ERROR module and MINMAXAVG
- * module. Returns 0 on success and error value in case of failure.
- */
-int sr_configure_errgen(struct voltagedomain *voltdm)
-{
-	u32 sr_config, sr_errconfig, errconfig_offs;
-	u32 vpboundint_en, vpboundint_st;
-	u32 senp_en = 0, senn_en = 0;
-	u8 senp_shift, senn_shift;
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return PTR_ERR(sr);
-	}
-
-	if (!sr->clk_length)
-		sr_set_clk_length(sr);
-
-	senp_en = sr->senp_mod;
-	senn_en = sr->senn_mod;
-
-	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-		SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
-
-	switch (sr->ip_type) {
-	case SR_TYPE_V1:
-		sr_config |= SRCONFIG_DELAYCTRL;
-		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
-		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
-		errconfig_offs = ERRCONFIG_V1;
-		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
-		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
-		break;
-	case SR_TYPE_V2:
-		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
-		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
-		errconfig_offs = ERRCONFIG_V2;
-		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
-		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
-		break;
-	default:
-		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-			"module without specifying the ip\n", __func__);
-		return -EINVAL;
-	}
-
-	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
-	sr_write_reg(sr, SRCONFIG, sr_config);
-	sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
-		(sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
-		(sr->err_minlimit <<  ERRCONFIG_ERRMINLIMIT_SHIFT);
-	sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
-		SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
-		sr_errconfig);
-
-	/* Enabling the interrupts if the ERROR module is used */
-	sr_modify_reg(sr, errconfig_offs, (vpboundint_en | vpboundint_st),
-		      vpboundint_en);
-
-	return 0;
-}
-
-/**
- * sr_disable_errgen() - Disables SmartReflex AVS module's errgen component
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * disable the error generator module inside the smartreflex module.
- *
- * Returns 0 on success and error value in case of failure.
- */
-int sr_disable_errgen(struct voltagedomain *voltdm)
-{
-	u32 errconfig_offs;
-	u32 vpboundint_en, vpboundint_st;
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return PTR_ERR(sr);
-	}
-
-	switch (sr->ip_type) {
-	case SR_TYPE_V1:
-		errconfig_offs = ERRCONFIG_V1;
-		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
-		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
-		break;
-	case SR_TYPE_V2:
-		errconfig_offs = ERRCONFIG_V2;
-		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
-		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
-		break;
-	default:
-		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-			"module without specifying the ip\n", __func__);
-		return -EINVAL;
-	}
-
-	/* Disable the interrupts of ERROR module */
-	sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
-
-	/* Disable the Sensor and errorgen */
-	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0);
-
-	return 0;
-}
-
-/**
- * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the
- *			 minmaxavg module.
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * configure the minmaxavg module inside the smartreflex module.
- * SR settings if using the ERROR module inside Smartreflex.
- * SR CLASS 3 by default uses only the ERROR module where as
- * SR CLASS 2 can choose between ERROR module and MINMAXAVG
- * module. Returns 0 on success and error value in case of failure.
- */
-int sr_configure_minmax(struct voltagedomain *voltdm)
-{
-	u32 sr_config, sr_avgwt;
-	u32 senp_en = 0, senn_en = 0;
-	u8 senp_shift, senn_shift;
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return PTR_ERR(sr);
-	}
-
-	if (!sr->clk_length)
-		sr_set_clk_length(sr);
-
-	senp_en = sr->senp_mod;
-	senn_en = sr->senn_mod;
-
-	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-		SRCONFIG_SENENABLE |
-		(sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
-
-	switch (sr->ip_type) {
-	case SR_TYPE_V1:
-		sr_config |= SRCONFIG_DELAYCTRL;
-		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
-		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
-		break;
-	case SR_TYPE_V2:
-		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
-		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
-		break;
-	default:
-		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-			"module without specifying the ip\n", __func__);
-		return -EINVAL;
-	}
-
-	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
-	sr_write_reg(sr, SRCONFIG, sr_config);
-	sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
-		(sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
-	sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
-
-	/*
-	 * Enabling the interrupts if MINMAXAVG module is used.
-	 * TODO: check if all the interrupts are mandatory
-	 */
-	switch (sr->ip_type) {
-	case SR_TYPE_V1:
-		sr_modify_reg(sr, ERRCONFIG_V1,
-			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
-			ERRCONFIG_MCUBOUNDINTEN),
-			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
-			 ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
-			 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
-		break;
-	case SR_TYPE_V2:
-		sr_write_reg(sr, IRQSTATUS,
-			IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
-			IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
-		sr_write_reg(sr, IRQENABLE_SET,
-			IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
-			IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
-		break;
-	default:
-		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-			"module without specifying the ip\n", __func__);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-/**
- * sr_enable() - Enables the smartreflex module.
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- * @volt:	The voltage at which the Voltage domain associated with
- *		the smartreflex module is operating at.
- *		This is required only to program the correct Ntarget value.
- *
- * This API is to be called from the smartreflex class driver to
- * enable a smartreflex module. Returns 0 on success. Returns error
- * value if the voltage passed is wrong or if ntarget value is wrong.
- */
-int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
-{
-	struct omap_sr *sr = _sr_lookup(voltdm);
-	struct omap_sr_nvalue_table *nvalue_row;
-	int ret;
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return PTR_ERR(sr);
-	}
-
-	nvalue_row = sr_retrieve_nvalue_row(sr, volt);
-	if (!nvalue_row) {
-		dev_warn(&sr->pdev->dev, "%s: failure getting SR data for this voltage %ld\n",
-			 __func__, volt);
-		return -ENODATA;
-	}
-
-
-	/* errminlimit is opp dependent and hence linked to voltage */
-	sr->err_minlimit = nvalue_row->errminlimit;
-
-	pm_runtime_get_sync(&sr->pdev->dev);
-
-	/* Check if SR is already enabled. If yes do nothing */
-	if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
-		return 0;
-
-	/* Configure SR */
-	ret = sr_class->configure(sr);
-	if (ret)
-		return ret;
-
-	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_row->nvalue);
-
-	/* SRCONFIG - enable SR */
-	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
-	return 0;
-}
-
-/**
- * sr_disable() - Disables the smartreflex module.
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * disable a smartreflex module.
- */
-void sr_disable(struct voltagedomain *voltdm)
-{
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return;
-	}
-
-	/* Check if SR clocks are already disabled. If yes do nothing */
-	if (pm_runtime_suspended(&sr->pdev->dev))
-		return;
-
-	/*
-	 * Disable SR if only it is indeed enabled. Else just
-	 * disable the clocks.
-	 */
-	if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
-		switch (sr->ip_type) {
-		case SR_TYPE_V1:
-			sr_v1_disable(sr);
-			break;
-		case SR_TYPE_V2:
-			sr_v2_disable(sr);
-			break;
-		default:
-			dev_err(&sr->pdev->dev, "UNKNOWN IP type %d\n",
-				sr->ip_type);
-		}
-	}
-
-	pm_runtime_put_sync_suspend(&sr->pdev->dev);
-}
-
-/**
- * sr_register_class() - API to register a smartreflex class parameters.
- * @class_data:	The structure containing various sr class specific data.
- *
- * This API is to be called by the smartreflex class driver to register itself
- * with the smartreflex driver during init. Returns 0 on success else the
- * error value.
- */
-int sr_register_class(struct omap_sr_class_data *class_data)
-{
-	struct omap_sr *sr_info;
-
-	if (!class_data) {
-		pr_warning("%s:, Smartreflex class data passed is NULL\n",
-			__func__);
-		return -EINVAL;
-	}
-
-	if (sr_class) {
-		pr_warning("%s: Smartreflex class driver already registered\n",
-			__func__);
-		return -EBUSY;
-	}
-
-	sr_class = class_data;
-
-	/*
-	 * Call into late init to do intializations that require
-	 * both sr driver and sr class driver to be initiallized.
-	 */
-	list_for_each_entry(sr_info, &sr_list, node)
-		sr_late_init(sr_info);
-
-	return 0;
-}
-
-/**
- * omap_sr_enable() -  API to enable SR clocks and to call into the
- *			registered smartreflex class enable API.
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to enable
- * a particular smartreflex module. This API will do the initial
- * configurations to turn on the smartreflex module and in turn call
- * into the registered smartreflex class enable API.
- */
-void omap_sr_enable(struct voltagedomain *voltdm)
-{
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return;
-	}
-
-	if (!sr->autocomp_active)
-		return;
-
-	if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
-		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
-			"registered\n", __func__);
-		return;
-	}
-
-	sr_class->enable(sr);
-}
-
-/**
- * omap_sr_disable() - API to disable SR without resetting the voltage
- *			processor voltage
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to disable
- * a particular smartreflex module. This API will in turn call
- * into the registered smartreflex class disable API. This API will tell
- * the smartreflex class disable not to reset the VP voltage after
- * disabling smartreflex.
- */
-void omap_sr_disable(struct voltagedomain *voltdm)
-{
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return;
-	}
-
-	if (!sr->autocomp_active)
-		return;
-
-	if (!sr_class || !(sr_class->disable)) {
-		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
-			"registered\n", __func__);
-		return;
-	}
-
-	sr_class->disable(sr, 0);
-}
-
-/**
- * omap_sr_disable_reset_volt() - API to disable SR and reset the
- *				voltage processor voltage
- * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to disable
- * a particular smartreflex module. This API will in turn call
- * into the registered smartreflex class disable API. This API will tell
- * the smartreflex class disable to reset the VP voltage after
- * disabling smartreflex.
- */
-void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
-{
-	struct omap_sr *sr = _sr_lookup(voltdm);
-
-	if (IS_ERR(sr)) {
-		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
-		return;
-	}
-
-	if (!sr->autocomp_active)
-		return;
-
-	if (!sr_class || !(sr_class->disable)) {
-		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
-			"registered\n", __func__);
-		return;
-	}
-
-	sr_class->disable(sr, 1);
-}
-
-/**
- * omap_sr_register_pmic() - API to register pmic specific info.
- * @pmic_data:	The structure containing pmic specific data.
- *
- * This API is to be called from the PMIC specific code to register with
- * smartreflex driver pmic specific info. Currently the only info required
- * is the smartreflex init on the PMIC side.
- */
-void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data)
-{
-	if (!pmic_data) {
-		pr_warning("%s: Trying to register NULL PMIC data structure"
-			"with smartreflex\n", __func__);
-		return;
-	}
-
-	sr_pmic_data = pmic_data;
-}
-
-/* PM Debug FS entries to enable and disable smartreflex. */
-static int omap_sr_autocomp_show(void *data, u64 *val)
-{
-	struct omap_sr *sr_info = data;
-
-	if (!sr_info) {
-		pr_warning("%s: omap_sr struct not found\n", __func__);
-		return -EINVAL;
-	}
-
-	*val = sr_info->autocomp_active;
-
-	return 0;
-}
-
-static int omap_sr_autocomp_store(void *data, u64 val)
-{
-	struct omap_sr *sr_info = data;
-
-	if (!sr_info) {
-		pr_warning("%s: omap_sr struct not found\n", __func__);
-		return -EINVAL;
-	}
-
-	/* Sanity check */
-	if (val > 1) {
-		pr_warning("%s: Invalid argument %lld\n", __func__, val);
-		return -EINVAL;
-	}
-
-	/* control enable/disable only if there is a delta in value */
-	if (sr_info->autocomp_active != val) {
-		if (!val)
-			sr_stop_vddautocomp(sr_info);
-		else
-			sr_start_vddautocomp(sr_info);
-	}
-
-	return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
-			omap_sr_autocomp_store, "%llu\n");
-
-static int __init omap_sr_probe(struct platform_device *pdev)
-{
-	struct omap_sr *sr_info;
-	struct omap_sr_data *pdata = pdev->dev.platform_data;
-	struct resource *mem, *irq;
-	struct dentry *nvalue_dir;
-	int i, ret = 0;
-
-	sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
-	if (!sr_info) {
-		dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
-			__func__);
-		return -ENOMEM;
-	}
-
-	platform_set_drvdata(pdev, sr_info);
-
-	if (!pdata) {
-		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
-		ret = -EINVAL;
-		goto err_free_devinfo;
-	}
-
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!mem) {
-		dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
-		ret = -ENODEV;
-		goto err_free_devinfo;
-	}
-
-	mem = request_mem_region(mem->start, resource_size(mem),
-					dev_name(&pdev->dev));
-	if (!mem) {
-		dev_err(&pdev->dev, "%s: no mem region\n", __func__);
-		ret = -EBUSY;
-		goto err_free_devinfo;
-	}
-
-	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-
-	pm_runtime_enable(&pdev->dev);
-	pm_runtime_irq_safe(&pdev->dev);
-
-	sr_info->name = kasprintf(GFP_KERNEL, "sr_%s", pdata->name);
-	if (!sr_info->name) {
-		dev_err(&pdev->dev, "%s: Unable to alloc SR instance name\n",
-			__func__);
-		ret = -ENOMEM;
-		goto err_release_region;
-	}
-
-	sr_info->pdev = pdev;
-	sr_info->srid = pdev->id;
-	sr_info->voltdm = pdata->voltdm;
-	sr_info->nvalue_table = pdata->nvalue_table;
-	sr_info->nvalue_count = pdata->nvalue_count;
-	sr_info->senn_mod = pdata->senn_mod;
-	sr_info->senp_mod = pdata->senp_mod;
-	sr_info->autocomp_active = false;
-	sr_info->ip_type = pdata->ip_type;
-	sr_info->base = ioremap(mem->start, resource_size(mem));
-	if (!sr_info->base) {
-		dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
-		ret = -ENOMEM;
-		goto err_release_region;
-	}
-
-	if (irq)
-		sr_info->irq = irq->start;
-
-	sr_set_clk_length(sr_info);
-	sr_set_regfields(sr_info);
-
-	list_add(&sr_info->node, &sr_list);
-
-	/*
-	 * Call into late init to do intializations that require
-	 * both sr driver and sr class driver to be initiallized.
-	 */
-	if (sr_class) {
-		ret = sr_late_init(sr_info);
-		if (ret) {
-			pr_warning("%s: Error in SR late init\n", __func__);
-			goto err_iounmap;
-		}
-	}
-
-	dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
-	if (!sr_dbg_dir) {
-		sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
-		if (IS_ERR_OR_NULL(sr_dbg_dir)) {
-			ret = PTR_ERR(sr_dbg_dir);
-			pr_err("%s:sr debugfs dir creation failed(%d)\n",
-				__func__, ret);
-			goto err_iounmap;
-		}
-	}
-
-	sr_info->dbg_dir = debugfs_create_dir(sr_info->name, sr_dbg_dir);
-	if (IS_ERR_OR_NULL(sr_info->dbg_dir)) {
-		dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
-			__func__);
-		ret = PTR_ERR(sr_info->dbg_dir);
-		goto err_free_name;
-	}
-
-	(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
-			sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops);
-	(void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
-			&sr_info->err_weight);
-	(void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
-			&sr_info->err_maxlimit);
-
-	nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
-	if (IS_ERR_OR_NULL(nvalue_dir)) {
-		dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
-			"for n-values\n", __func__);
-		ret = PTR_ERR(nvalue_dir);
-		goto err_debugfs;
-	}
-
-	if (sr_info->nvalue_count == 0 || !sr_info->nvalue_table) {
-		dev_warn(&pdev->dev, "%s: %s: No Voltage table for the corresponding vdd. Cannot create debugfs entries for n-values\n",
-			 __func__, sr_info->name);
-		ret = -ENODATA;
-		goto err_debugfs;
-	}
-
-	for (i = 0; i < sr_info->nvalue_count; i++) {
-		char name[NVALUE_NAME_LEN + 1];
-
-		snprintf(name, sizeof(name), "volt_%lu",
-			 sr_info->nvalue_table[i].volt_nominal);
-		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
-				&(sr_info->nvalue_table[i].nvalue));
-		snprintf(name, sizeof(name), "errminlimit_%lu",
-			 sr_info->nvalue_table[i].volt_nominal);
-		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
-				&(sr_info->nvalue_table[i].errminlimit));
-	}
-
-	return ret;
-
-err_debugfs:
-	debugfs_remove_recursive(sr_info->dbg_dir);
-err_free_name:
-	kfree(sr_info->name);
-err_iounmap:
-	list_del(&sr_info->node);
-	iounmap(sr_info->base);
-err_release_region:
-	release_mem_region(mem->start, resource_size(mem));
-err_free_devinfo:
-	kfree(sr_info);
-
-	return ret;
-}
-
-static int __devexit omap_sr_remove(struct platform_device *pdev)
-{
-	struct omap_sr_data *pdata = pdev->dev.platform_data;
-	struct omap_sr *sr_info;
-	struct resource *mem;
-
-	if (!pdata) {
-		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
-		return -EINVAL;
-	}
-
-	sr_info = _sr_lookup(pdata->voltdm);
-	if (IS_ERR(sr_info)) {
-		dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
-			__func__);
-		return PTR_ERR(sr_info);
-	}
-
-	if (sr_info->autocomp_active)
-		sr_stop_vddautocomp(sr_info);
-	if (sr_info->dbg_dir)
-		debugfs_remove_recursive(sr_info->dbg_dir);
-
-	list_del(&sr_info->node);
-	iounmap(sr_info->base);
-	kfree(sr_info->name);
-	kfree(sr_info);
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	release_mem_region(mem->start, resource_size(mem));
-
-	return 0;
-}
-
-static void __devexit omap_sr_shutdown(struct platform_device *pdev)
-{
-	struct omap_sr_data *pdata = pdev->dev.platform_data;
-	struct omap_sr *sr_info;
-
-	if (!pdata) {
-		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
-		return;
-	}
-
-	sr_info = _sr_lookup(pdata->voltdm);
-	if (IS_ERR(sr_info)) {
-		dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
-			__func__);
-		return;
-	}
-
-	if (sr_info->autocomp_active)
-		sr_stop_vddautocomp(sr_info);
-
-	return;
-}
-
-static struct platform_driver smartreflex_driver = {
-	.remove         = __devexit_p(omap_sr_remove),
-	.shutdown	= __devexit_p(omap_sr_shutdown),
-	.driver		= {
-		.name	= "smartreflex",
-	},
-};
-
-static int __init sr_init(void)
-{
-	int ret = 0;
-
-	/*
-	 * sr_init is a late init. If by then a pmic specific API is not
-	 * registered either there is no need for anything to be done on
-	 * the PMIC side or somebody has forgotten to register a PMIC
-	 * handler. Warn for the second condition.
-	 */
-	if (sr_pmic_data && sr_pmic_data->sr_pmic_init)
-		sr_pmic_data->sr_pmic_init();
-	else
-		pr_warning("%s: No PMIC hook to init smartreflex\n", __func__);
-
-	ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe);
-	if (ret) {
-		pr_err("%s: platform driver register failed for SR\n",
-			__func__);
-		return ret;
-	}
-
-	return 0;
-}
-late_initcall(sr_init);
-
-static void __exit sr_exit(void)
-{
-	platform_driver_unregister(&smartreflex_driver);
-}
-module_exit(sr_exit);
-
-MODULE_DESCRIPTION("OMAP Smartreflex Driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" DRIVER_NAME);
-MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
deleted file mode 100644
index 754f6aa..0000000
--- a/arch/arm/mach-omap2/smartreflex.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * OMAP Smartreflex Defines and Routines
- *
- * Author: Thara Gopinath	<thara at ti.com>
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- * Thara Gopinath <thara at ti.com>
- *
- * Copyright (C) 2008 Nokia Corporation
- * Kalle Jokiniemi
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Lesly A M <x0080970 at ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __DRIVERS_POWER_AVS_SMARTREFLEX_H
-#define __DRIVERS_POWER_AVS_SMARTREFLEX_H
-
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/power/smartreflex.h>
-
-#include <plat/voltage.h>
-
-/*
- * Different Smartreflex IPs version. The v1 is the 65nm version used in
- * OMAP3430. The v2 is the update for the 45nm version of the IP
- * used in OMAP3630 and OMAP4430
- */
-#define SR_TYPE_V1	1
-#define SR_TYPE_V2	2
-
-/* SMART REFLEX REG ADDRESS OFFSET */
-#define SRCONFIG		0x00
-#define SRSTATUS		0x04
-#define SENVAL			0x08
-#define SENMIN			0x0C
-#define SENMAX			0x10
-#define SENAVG			0x14
-#define AVGWEIGHT		0x18
-#define NVALUERECIPROCAL	0x1c
-#define SENERROR_V1		0x20
-#define ERRCONFIG_V1		0x24
-#define IRQ_EOI			0x20
-#define IRQSTATUS_RAW		0x24
-#define IRQSTATUS		0x28
-#define IRQENABLE_SET		0x2C
-#define IRQENABLE_CLR		0x30
-#define SENERROR_V2		0x34
-#define ERRCONFIG_V2		0x38
-
-/* Bit/Shift Positions */
-
-/* SRCONFIG */
-#define SRCONFIG_ACCUMDATA_SHIFT	22
-#define SRCONFIG_SRCLKLENGTH_SHIFT	12
-#define SRCONFIG_SENNENABLE_V1_SHIFT	5
-#define SRCONFIG_SENPENABLE_V1_SHIFT	3
-#define SRCONFIG_SENNENABLE_V2_SHIFT	1
-#define SRCONFIG_SENPENABLE_V2_SHIFT	0
-#define SRCONFIG_CLKCTRL_SHIFT		0
-
-#define SRCONFIG_ACCUMDATA_MASK		(0x3ff << 22)
-
-#define SRCONFIG_SRENABLE		BIT(11)
-#define SRCONFIG_SENENABLE		BIT(10)
-#define SRCONFIG_ERRGEN_EN		BIT(9)
-#define SRCONFIG_MINMAXAVG_EN		BIT(8)
-#define SRCONFIG_DELAYCTRL		BIT(2)
-
-/* AVGWEIGHT */
-#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT	2
-#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT	0
-
-/* NVALUERECIPROCAL */
-#define NVALUERECIPROCAL_SENPGAIN_SHIFT	20
-#define NVALUERECIPROCAL_SENNGAIN_SHIFT	16
-#define NVALUERECIPROCAL_RNSENP_SHIFT	8
-#define NVALUERECIPROCAL_RNSENN_SHIFT	0
-
-/* ERRCONFIG */
-#define ERRCONFIG_ERRWEIGHT_SHIFT	16
-#define ERRCONFIG_ERRMAXLIMIT_SHIFT	8
-#define ERRCONFIG_ERRMINLIMIT_SHIFT	0
-
-#define SR_ERRWEIGHT_MASK		(0x07 << 16)
-#define SR_ERRMAXLIMIT_MASK		(0xff << 8)
-#define SR_ERRMINLIMIT_MASK		(0xff << 0)
-
-#define ERRCONFIG_VPBOUNDINTEN_V1	BIT(31)
-#define ERRCONFIG_VPBOUNDINTST_V1	BIT(30)
-#define	ERRCONFIG_MCUACCUMINTEN		BIT(29)
-#define ERRCONFIG_MCUACCUMINTST		BIT(28)
-#define	ERRCONFIG_MCUVALIDINTEN		BIT(27)
-#define ERRCONFIG_MCUVALIDINTST		BIT(26)
-#define ERRCONFIG_MCUBOUNDINTEN		BIT(25)
-#define	ERRCONFIG_MCUBOUNDINTST		BIT(24)
-#define	ERRCONFIG_MCUDISACKINTEN	BIT(23)
-#define ERRCONFIG_VPBOUNDINTST_V2	BIT(23)
-#define ERRCONFIG_MCUDISACKINTST	BIT(22)
-#define ERRCONFIG_VPBOUNDINTEN_V2	BIT(22)
-
-#define ERRCONFIG_STATUS_V1_MASK	(ERRCONFIG_VPBOUNDINTST_V1 | \
-					ERRCONFIG_MCUACCUMINTST | \
-					ERRCONFIG_MCUVALIDINTST | \
-					ERRCONFIG_MCUBOUNDINTST | \
-					ERRCONFIG_MCUDISACKINTST)
-/* IRQSTATUS */
-#define IRQSTATUS_MCUACCUMINT		BIT(3)
-#define IRQSTATUS_MCVALIDINT		BIT(2)
-#define IRQSTATUS_MCBOUNDSINT		BIT(1)
-#define IRQSTATUS_MCUDISABLEACKINT	BIT(0)
-
-/* IRQENABLE_SET and IRQENABLE_CLEAR */
-#define IRQENABLE_MCUACCUMINT		BIT(3)
-#define IRQENABLE_MCUVALIDINT		BIT(2)
-#define IRQENABLE_MCUBOUNDSINT		BIT(1)
-#define IRQENABLE_MCUDISABLEACKINT	BIT(0)
-
-/* Common Bit values */
-
-#define SRCLKLENGTH_12MHZ_SYSCLK	0x3c
-#define SRCLKLENGTH_13MHZ_SYSCLK	0x41
-#define SRCLKLENGTH_19MHZ_SYSCLK	0x60
-#define SRCLKLENGTH_26MHZ_SYSCLK	0x82
-#define SRCLKLENGTH_38MHZ_SYSCLK	0xC0
-
-/*
- * 3430 specific values. Maybe these should be passed from board file or
- * pmic structures.
- */
-#define OMAP3430_SR_ACCUMDATA		0x1f4
-
-#define OMAP3430_SR1_SENPAVGWEIGHT	0x03
-#define OMAP3430_SR1_SENNAVGWEIGHT	0x03
-
-#define OMAP3430_SR2_SENPAVGWEIGHT	0x01
-#define OMAP3430_SR2_SENNAVGWEIGHT	0x01
-
-#define OMAP3430_SR_ERRWEIGHT		0x04
-#define OMAP3430_SR_ERRMAXLIMIT		0x02
-
-/**
- * test_cond_timeout - busy-loop, testing a condition
- * @cond: condition to test until it evaluates to true
- * @timeout: maximum number of microseconds in the timeout
- * @index: loop index (integer)
- *
- * Loop waiting for @cond to become true or until at least @timeout
- * microseconds have passed.  To use, define some integer @index in the
- * calling code.  After running, if @index == @timeout, then the loop has
- * timed out.
- *
- * Copied from omap_test_timeout
- */
-#define sr_test_cond_timeout(cond, timeout, index)		\
-({								\
-	for (index = 0; index < timeout; index++) {		\
-		if (cond)					\
-			break;					\
-		udelay(1);					\
-	}							\
-})
-
-/**
- * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
- *				pmic specific info to smartreflex driver
- *
- * @sr_pmic_init:	API to initialize smartreflex on the PMIC side.
- */
-struct omap_sr_pmic_data {
-	void (*sr_pmic_init) (void);
-};
-
-
-#ifdef CONFIG_POWER_AVS_OMAP
-/*
- * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
- * The smartreflex class driver should pass the class type.
- * Should be used to populate the class_type field of the
- * omap_smartreflex_class_data structure.
- */
-#define SR_CLASS1	0x1
-#define SR_CLASS2	0x2
-#define SR_CLASS3	0x3
-
-/**
- * struct omap_sr_class_data - Smartreflex class driver info
- *
- * @enable:		API to enable a particular class smaartreflex.
- * @disable:		API to disable a particular class smartreflex.
- * @configure:		API to configure a particular class smartreflex.
- * @notify:		API to notify the class driver about an event in SR.
- *			Not needed for class3.
- * @notify_flags:	specify the events to be notified to the class driver
- * @class_type:		specify which smartreflex class.
- *			Can be used by the SR driver to take any class
- *			based decisions.
- */
-struct omap_sr_class_data {
-	int (*enable)(struct omap_sr *sr);
-	int (*disable)(struct omap_sr *sr, int is_volt_reset);
-	int (*configure)(struct omap_sr *sr);
-	int (*notify)(struct omap_sr *sr, u32 status);
-	u8 notify_flags;
-	u8 class_type;
-};
-
-/* Smartreflex module enable/disable interface */
-void omap_sr_enable(struct voltagedomain *voltdm);
-void omap_sr_disable(struct voltagedomain *voltdm);
-void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
-
-/* API to register the pmic specific data with the smartreflex driver. */
-void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
-
-/* Smartreflex driver hooks to be called from Smartreflex class driver */
-int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
-void sr_disable(struct voltagedomain *voltdm);
-int sr_configure_errgen(struct voltagedomain *voltdm);
-int sr_disable_errgen(struct voltagedomain *voltdm);
-int sr_configure_minmax(struct voltagedomain *voltdm);
-
-/* API to register the smartreflex class driver with the smartreflex driver */
-int sr_register_class(struct omap_sr_class_data *class_data);
-#else
-static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
-static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
-static inline void omap_sr_disable_reset_volt(
-		struct voltagedomain *voltdm) {}
-static inline void omap_sr_register_pmic(
-		struct omap_sr_pmic_data *pmic_data) {}
-#endif
-#endif
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 6ec9237..85f70e6 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -44,24 +44,9 @@ config OMAP_DEBUG_LEDS
 	depends on OMAP_DEBUG_DEVICES
 	default y if LEDS_CLASS
 
-menuconfig POWER_AVS
-	tristate "Adaptive Voltage Scaling class support"
-	help
-	  AVS is a power management technique which finely controls the
-	  operating voltage of a device in order to optimize (i.e. reduce)
-	  its power consumption.
-	  At a given operating point the voltage is adapted depending on
-	  static factors (chip manufacturing process) and dynamic factors
-	  (temperature depending performance).
-	  AVS is also called SmartReflex on OMAP devices.
-
-	  Say Y here to enable Adaptive Voltage Scaling class support.
-
-if POWER_AVS
-
 config POWER_AVS_OMAP
 	bool "AVS support for the OMAP IP versions 1&2"
-	depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
+	depends on POWER_AVS && (ARCH_OMAP3 || ARCH_OMAP4) && PM
 	help
 	  Say Y to enable AVS support on OMAP containing the version 1 or
 	  version 2 of the SmartReflex IP.
@@ -88,8 +73,6 @@ config POWER_AVS_OMAP_CLASS3
 	  Class 3 implementation of Smartreflex employs continuous hardware
 	  voltage calibration.
 
-endif # POWER_AVS
-
 config OMAP_RESET_CLOCKS
 	bool "Reset unused clocks during boot"
 	depends on ARCH_OMAP
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 3a8daf8..06f991e 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -275,3 +275,5 @@ config CHARGER_MAX8998
 	  platform data of MAX8998/LP3974 PMICs.
 
 endif # POWER_SUPPLY
+
+source "drivers/power/avs/Kconfig"
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index e429008..e4a8fd2 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -41,3 +41,5 @@ obj-$(CONFIG_CHARGER_GPIO)	+= gpio-charger.o
 obj-$(CONFIG_CHARGER_MANAGER)	+= charger-manager.o
 obj-$(CONFIG_CHARGER_MAX8997)	+= max8997_charger.o
 obj-$(CONFIG_CHARGER_MAX8998)	+= max8998_charger.o
+
+obj-$(CONFIG_POWER_AVS)		+= avs/
diff --git a/drivers/power/avs/Kconfig b/drivers/power/avs/Kconfig
new file mode 100644
index 0000000..18493f7
--- /dev/null
+++ b/drivers/power/avs/Kconfig
@@ -0,0 +1,12 @@
+menuconfig POWER_AVS
+	tristate "Adaptive Voltage Scaling class support"
+	help
+	  AVS is a power management technique which finely controls the
+	  operating voltage of a device in order to optimize (i.e. reduce)
+	  its power consumption.
+	  At a given operating point the voltage is adapted depending on
+	  static factors (chip manufacturing process) and dynamic factors
+	  (temperature depending performance).
+	  AVS is also called SmartReflex on OMAP devices.
+
+	  Say Y here to enable Adaptive Voltage Scaling class support.
diff --git a/drivers/power/avs/Makefile b/drivers/power/avs/Makefile
new file mode 100644
index 0000000..ac72ec5
--- /dev/null
+++ b/drivers/power/avs/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_POWER_AVS_OMAP)		+= smartreflex.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)	+= smartreflex-class3.o
diff --git a/drivers/power/avs/smartreflex-class3.c b/drivers/power/avs/smartreflex-class3.c
new file mode 100644
index 0000000..413a07b
--- /dev/null
+++ b/drivers/power/avs/smartreflex-class3.c
@@ -0,0 +1,61 @@
+/*
+ * Smart reflex Class 3 specific implementations
+ *
+ * Author: Thara Gopinath       <thara at ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "smartreflex.h"
+#include <plat/voltage.h>
+
+static int sr_class3_enable(struct omap_sr *sr)
+{
+	unsigned long volt = voltdm_get_voltage(sr->voltdm);
+
+	if (!volt) {
+		pr_warning("%s: Curr voltage unknown. Cannot enable %s\n",
+				__func__, sr->name);
+		return -ENODATA;
+	}
+
+	omap_vp_enable(sr->voltdm);
+	return sr_enable(sr->voltdm, volt);
+}
+
+static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
+{
+	sr_disable_errgen(sr->voltdm);
+	omap_vp_disable(sr->voltdm);
+	sr_disable(sr->voltdm);
+	if (is_volt_reset)
+		voltdm_reset(sr->voltdm);
+
+	return 0;
+}
+
+static int sr_class3_configure(struct omap_sr *sr)
+{
+	return sr_configure_errgen(sr->voltdm);
+}
+
+/* SR class3 structure */
+static struct omap_sr_class_data class3_data = {
+	.enable = sr_class3_enable,
+	.disable = sr_class3_disable,
+	.configure = sr_class3_configure,
+	.class_type = SR_CLASS3,
+};
+
+/* Smartreflex Class3 init API to be called from board file */
+static int __init sr_class3_init(void)
+{
+	pr_info("SmartReflex Class3 initialized\n");
+	return sr_register_class(&class3_data);
+}
+late_initcall(sr_class3_init);
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
new file mode 100644
index 0000000..d3973cb
--- /dev/null
+++ b/drivers/power/avs/smartreflex.c
@@ -0,0 +1,1118 @@
+/*
+ * OMAP SmartReflex Voltage Control
+ *
+ * Author: Thara Gopinath	<thara at ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara at ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970 at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <linux/power/smartreflex.h>
+
+#include "smartreflex.h"
+
+#define SMARTREFLEX_NAME_LEN	16
+#define NVALUE_NAME_LEN		40
+#define SR_DISABLE_TIMEOUT	200
+
+/* sr_list contains all the instances of smartreflex module */
+static LIST_HEAD(sr_list);
+
+static struct omap_sr_class_data *sr_class;
+static struct omap_sr_pmic_data *sr_pmic_data;
+static struct dentry		*sr_dbg_dir;
+
+static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
+{
+	__raw_writel(value, (sr->base + offset));
+}
+
+static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
+					u32 value)
+{
+	u32 reg_val;
+
+	/*
+	 * Smartreflex error config register is special as it contains
+	 * certain status bits which if written a 1 into means a clear
+	 * of those bits. So in order to make sure no accidental write of
+	 * 1 happens to those status bits, do a clear of them in the read
+	 * value. This mean this API doesn't rewrite values in these bits
+	 * if they are currently set, but does allow the caller to write
+	 * those bits.
+	 */
+	if (sr->ip_type == SR_TYPE_V1 && offset == ERRCONFIG_V1)
+		mask |= ERRCONFIG_STATUS_V1_MASK;
+	else if (sr->ip_type == SR_TYPE_V2 && offset == ERRCONFIG_V2)
+		mask |= ERRCONFIG_VPBOUNDINTST_V2;
+
+	reg_val = __raw_readl(sr->base + offset);
+	reg_val &= ~mask;
+
+	value &= mask;
+
+	reg_val |= value;
+
+	__raw_writel(reg_val, (sr->base + offset));
+}
+
+static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
+{
+	return __raw_readl(sr->base + offset);
+}
+
+static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
+{
+	struct omap_sr *sr_info;
+
+	if (!voltdm) {
+		pr_err("%s: Null voltage domain passed!\n", __func__);
+		return ERR_PTR(-EINVAL);
+	}
+
+	list_for_each_entry(sr_info, &sr_list, node) {
+		if (voltdm == sr_info->voltdm)
+			return sr_info;
+	}
+
+	return ERR_PTR(-ENODATA);
+}
+
+static irqreturn_t sr_interrupt(int irq, void *data)
+{
+	struct omap_sr *sr_info = data;
+	u32 status = 0;
+
+	switch (sr_info->ip_type) {
+	case SR_TYPE_V1:
+		/* Read the status bits */
+		status = sr_read_reg(sr_info, ERRCONFIG_V1);
+
+		/* Clear them by writing back */
+		sr_write_reg(sr_info, ERRCONFIG_V1, status);
+		break;
+	case SR_TYPE_V2:
+		/* Read the status bits */
+		status = sr_read_reg(sr_info, IRQSTATUS);
+
+		/* Clear them by writing back */
+		sr_write_reg(sr_info, IRQSTATUS, status);
+		break;
+	default:
+		dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n",
+			sr_info->ip_type);
+		return IRQ_NONE;
+	}
+
+	if (sr_class->notify)
+		sr_class->notify(sr_info, status);
+
+	return IRQ_HANDLED;
+}
+
+static void sr_set_clk_length(struct omap_sr *sr)
+{
+	struct clk *sys_ck;
+	u32 sys_clk_speed;
+
+	if (cpu_is_omap34xx())
+		sys_ck = clk_get(NULL, "sys_ck");
+	else
+		sys_ck = clk_get(NULL, "sys_clkin_ck");
+
+	if (IS_ERR(sys_ck)) {
+		dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
+			__func__);
+		return;
+	}
+
+	sys_clk_speed = clk_get_rate(sys_ck);
+	clk_put(sys_ck);
+
+	switch (sys_clk_speed) {
+	case 12000000:
+		sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+		break;
+	case 13000000:
+		sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+		break;
+	case 19200000:
+		sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+		break;
+	case 26000000:
+		sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+		break;
+	case 38400000:
+		sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+		break;
+	default:
+		dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n",
+			__func__, sys_clk_speed);
+		break;
+	}
+}
+
+static void sr_set_regfields(struct omap_sr *sr)
+{
+	/*
+	 * For time being these values are defined in smartreflex.h
+	 * and populated during init. May be they can be moved to board
+	 * file or pmic specific data structure. In that case these structure
+	 * fields will have to be populated using the pdata or pmic structure.
+	 */
+	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+		sr->err_weight = OMAP3430_SR_ERRWEIGHT;
+		sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+		sr->accum_data = OMAP3430_SR_ACCUMDATA;
+		if (!(strcmp(sr->name, "sr_mpu_iva"))) {
+			sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+			sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+		} else {
+			sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+			sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+		}
+	}
+}
+
+static void sr_start_vddautocomp(struct omap_sr *sr)
+{
+	if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+		dev_warn(&sr->pdev->dev,
+			"%s: smartreflex class driver not registered\n",
+			__func__);
+		return;
+	}
+
+	if (!sr_class->enable(sr))
+		sr->autocomp_active = true;
+}
+
+static void sr_stop_vddautocomp(struct omap_sr *sr)
+{
+	if (!sr_class || !(sr_class->disable)) {
+		dev_warn(&sr->pdev->dev,
+			"%s: smartreflex class driver not registered\n",
+			__func__);
+		return;
+	}
+
+	if (sr->autocomp_active) {
+		sr_class->disable(sr, 1);
+		sr->autocomp_active = false;
+	}
+}
+
+/*
+ * This function handles the intializations which have to be done
+ * only when both sr device and class driver regiter has
+ * completed. This will be attempted to be called from both sr class
+ * driver register and sr device intializtion API's. Only one call
+ * will ultimately succeed.
+ *
+ * Currently this function registers interrupt handler for a particular SR
+ * if smartreflex class driver is already registered and has
+ * requested for interrupts and the SR interrupt line in present.
+ */
+static int sr_late_init(struct omap_sr *sr_info)
+{
+	struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
+	struct resource *mem;
+	int ret = 0;
+
+	if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
+		ret = request_irq(sr_info->irq, sr_interrupt,
+				  0, sr_info->name, sr_info);
+		if (ret)
+			goto error;
+		disable_irq(sr_info->irq);
+	}
+
+	if (pdata && pdata->enable_on_init)
+		sr_start_vddautocomp(sr_info);
+
+	return ret;
+
+error:
+	iounmap(sr_info->base);
+	mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
+	release_mem_region(mem->start, resource_size(mem));
+	list_del(&sr_info->node);
+	dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
+		"interrupt handler. Smartreflex will"
+		"not function as desired\n", __func__);
+	kfree(sr_info);
+
+	return ret;
+}
+
+static void sr_v1_disable(struct omap_sr *sr)
+{
+	int timeout = 0;
+	int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
+			ERRCONFIG_MCUBOUNDINTST;
+
+	/* Enable MCUDisableAcknowledge interrupt */
+	sr_modify_reg(sr, ERRCONFIG_V1,
+			ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
+
+	/* SRCONFIG - disable SR */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+	/* Disable all other SR interrupts and clear the status as needed */
+	if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1)
+		errconf_val |= ERRCONFIG_VPBOUNDINTST_V1;
+	sr_modify_reg(sr, ERRCONFIG_V1,
+			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+			ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
+			errconf_val);
+
+	/*
+	 * Wait for SR to be disabled.
+	 * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
+	 */
+	sr_test_cond_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
+			     ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
+			     timeout);
+
+	if (timeout >= SR_DISABLE_TIMEOUT)
+		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+			__func__);
+
+	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+	sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
+			ERRCONFIG_MCUDISACKINTST);
+}
+
+static void sr_v2_disable(struct omap_sr *sr)
+{
+	int timeout = 0;
+
+	/* Enable MCUDisableAcknowledge interrupt */
+	sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
+
+	/* SRCONFIG - disable SR */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+	/*
+	 * Disable all other SR interrupts and clear the status
+	 * write to status register ONLY on need basis - only if status
+	 * is set.
+	 */
+	if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2)
+		sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+			ERRCONFIG_VPBOUNDINTST_V2);
+	else
+		sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+				0x0);
+	sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
+			IRQENABLE_MCUVALIDINT |
+			IRQENABLE_MCUBOUNDSINT));
+	sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
+			IRQSTATUS_MCVALIDINT |
+			IRQSTATUS_MCBOUNDSINT));
+
+	/*
+	 * Wait for SR to be disabled.
+	 * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
+	 */
+	sr_test_cond_timeout((sr_read_reg(sr, IRQSTATUS) &
+			     IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
+			     timeout);
+
+	if (timeout >= SR_DISABLE_TIMEOUT)
+		dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+			__func__);
+
+	/* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+	sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
+	sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
+}
+
+static struct omap_sr_nvalue_table *sr_retrieve_nvalue_row(
+				struct omap_sr *sr,
+				unsigned long volt_nominal)
+{
+	int i;
+
+	if (!sr->nvalue_table) {
+		dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
+			__func__);
+		return NULL;
+	}
+
+	for (i = 0; i < sr->nvalue_count; i++) {
+		if (sr->nvalue_table[i].volt_nominal == volt_nominal)
+			return &sr->nvalue_table[i];
+	}
+
+	return NULL;
+}
+
+/* Public Functions */
+
+/**
+ * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the
+ *			 error generator module.
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the error generator module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_errgen(struct voltagedomain *voltdm)
+{
+	u32 sr_config, sr_errconfig, errconfig_offs;
+	u32 vpboundint_en, vpboundint_st;
+	u32 senp_en = 0, senn_en = 0;
+	u8 senp_shift, senn_shift;
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return PTR_ERR(sr);
+	}
+
+	if (!sr->clk_length)
+		sr_set_clk_length(sr);
+
+	senp_en = sr->senp_mod;
+	senn_en = sr->senn_mod;
+
+	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+		SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
+
+	switch (sr->ip_type) {
+	case SR_TYPE_V1:
+		sr_config |= SRCONFIG_DELAYCTRL;
+		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+		errconfig_offs = ERRCONFIG_V1;
+		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+		break;
+	case SR_TYPE_V2:
+		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+		errconfig_offs = ERRCONFIG_V2;
+		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+		break;
+	default:
+		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+			"module without specifying the ip\n", __func__);
+		return -EINVAL;
+	}
+
+	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+	sr_write_reg(sr, SRCONFIG, sr_config);
+	sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
+		(sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
+		(sr->err_minlimit <<  ERRCONFIG_ERRMINLIMIT_SHIFT);
+	sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
+		SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+		sr_errconfig);
+
+	/* Enabling the interrupts if the ERROR module is used */
+	sr_modify_reg(sr, errconfig_offs, (vpboundint_en | vpboundint_st),
+		      vpboundint_en);
+
+	return 0;
+}
+
+/**
+ * sr_disable_errgen() - Disables SmartReflex AVS module's errgen component
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * disable the error generator module inside the smartreflex module.
+ *
+ * Returns 0 on success and error value in case of failure.
+ */
+int sr_disable_errgen(struct voltagedomain *voltdm)
+{
+	u32 errconfig_offs;
+	u32 vpboundint_en, vpboundint_st;
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return PTR_ERR(sr);
+	}
+
+	switch (sr->ip_type) {
+	case SR_TYPE_V1:
+		errconfig_offs = ERRCONFIG_V1;
+		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+		break;
+	case SR_TYPE_V2:
+		errconfig_offs = ERRCONFIG_V2;
+		vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+		vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+		break;
+	default:
+		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+			"module without specifying the ip\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Disable the interrupts of ERROR module */
+	sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
+
+	/* Disable the Sensor and errorgen */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0);
+
+	return 0;
+}
+
+/**
+ * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the
+ *			 minmaxavg module.
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the minmaxavg module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_minmax(struct voltagedomain *voltdm)
+{
+	u32 sr_config, sr_avgwt;
+	u32 senp_en = 0, senn_en = 0;
+	u8 senp_shift, senn_shift;
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return PTR_ERR(sr);
+	}
+
+	if (!sr->clk_length)
+		sr_set_clk_length(sr);
+
+	senp_en = sr->senp_mod;
+	senn_en = sr->senn_mod;
+
+	sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+		SRCONFIG_SENENABLE |
+		(sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
+
+	switch (sr->ip_type) {
+	case SR_TYPE_V1:
+		sr_config |= SRCONFIG_DELAYCTRL;
+		senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+		break;
+	case SR_TYPE_V2:
+		senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+		senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+		break;
+	default:
+		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+			"module without specifying the ip\n", __func__);
+		return -EINVAL;
+	}
+
+	sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+	sr_write_reg(sr, SRCONFIG, sr_config);
+	sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
+		(sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
+	sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
+
+	/*
+	 * Enabling the interrupts if MINMAXAVG module is used.
+	 * TODO: check if all the interrupts are mandatory
+	 */
+	switch (sr->ip_type) {
+	case SR_TYPE_V1:
+		sr_modify_reg(sr, ERRCONFIG_V1,
+			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+			ERRCONFIG_MCUBOUNDINTEN),
+			(ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
+			 ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
+			 ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
+		break;
+	case SR_TYPE_V2:
+		sr_write_reg(sr, IRQSTATUS,
+			IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
+			IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
+		sr_write_reg(sr, IRQENABLE_SET,
+			IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
+			IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
+		break;
+	default:
+		dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+			"module without specifying the ip\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ * sr_enable() - Enables the smartreflex module.
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ * @volt:	The voltage at which the Voltage domain associated with
+ *		the smartreflex module is operating at.
+ *		This is required only to program the correct Ntarget value.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * enable a smartreflex module. Returns 0 on success. Returns error
+ * value if the voltage passed is wrong or if ntarget value is wrong.
+ */
+int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
+{
+	struct omap_sr *sr = _sr_lookup(voltdm);
+	struct omap_sr_nvalue_table *nvalue_row;
+	int ret;
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return PTR_ERR(sr);
+	}
+
+	nvalue_row = sr_retrieve_nvalue_row(sr, volt);
+	if (!nvalue_row) {
+		dev_warn(&sr->pdev->dev, "%s: failure getting SR data for this voltage %ld\n",
+			 __func__, volt);
+		return -ENODATA;
+	}
+
+
+	/* errminlimit is opp dependent and hence linked to voltage */
+	sr->err_minlimit = nvalue_row->errminlimit;
+
+	pm_runtime_get_sync(&sr->pdev->dev);
+
+	/* Check if SR is already enabled. If yes do nothing */
+	if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
+		return 0;
+
+	/* Configure SR */
+	ret = sr_class->configure(sr);
+	if (ret)
+		return ret;
+
+	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_row->nvalue);
+
+	/* SRCONFIG - enable SR */
+	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
+	return 0;
+}
+
+/**
+ * sr_disable() - Disables the smartreflex module.
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * disable a smartreflex module.
+ */
+void sr_disable(struct voltagedomain *voltdm)
+{
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return;
+	}
+
+	/* Check if SR clocks are already disabled. If yes do nothing */
+	if (pm_runtime_suspended(&sr->pdev->dev))
+		return;
+
+	/*
+	 * Disable SR if only it is indeed enabled. Else just
+	 * disable the clocks.
+	 */
+	if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
+		switch (sr->ip_type) {
+		case SR_TYPE_V1:
+			sr_v1_disable(sr);
+			break;
+		case SR_TYPE_V2:
+			sr_v2_disable(sr);
+			break;
+		default:
+			dev_err(&sr->pdev->dev, "UNKNOWN IP type %d\n",
+				sr->ip_type);
+		}
+	}
+
+	pm_runtime_put_sync_suspend(&sr->pdev->dev);
+}
+
+/**
+ * sr_register_class() - API to register a smartreflex class parameters.
+ * @class_data:	The structure containing various sr class specific data.
+ *
+ * This API is to be called by the smartreflex class driver to register itself
+ * with the smartreflex driver during init. Returns 0 on success else the
+ * error value.
+ */
+int sr_register_class(struct omap_sr_class_data *class_data)
+{
+	struct omap_sr *sr_info;
+
+	if (!class_data) {
+		pr_warning("%s:, Smartreflex class data passed is NULL\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	if (sr_class) {
+		pr_warning("%s: Smartreflex class driver already registered\n",
+			__func__);
+		return -EBUSY;
+	}
+
+	sr_class = class_data;
+
+	/*
+	 * Call into late init to do intializations that require
+	 * both sr driver and sr class driver to be initiallized.
+	 */
+	list_for_each_entry(sr_info, &sr_list, node)
+		sr_late_init(sr_info);
+
+	return 0;
+}
+
+/**
+ * omap_sr_enable() -  API to enable SR clocks and to call into the
+ *			registered smartreflex class enable API.
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to enable
+ * a particular smartreflex module. This API will do the initial
+ * configurations to turn on the smartreflex module and in turn call
+ * into the registered smartreflex class enable API.
+ */
+void omap_sr_enable(struct voltagedomain *voltdm)
+{
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return;
+	}
+
+	if (!sr->autocomp_active)
+		return;
+
+	if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+			"registered\n", __func__);
+		return;
+	}
+
+	sr_class->enable(sr);
+}
+
+/**
+ * omap_sr_disable() - API to disable SR without resetting the voltage
+ *			processor voltage
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable not to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable(struct voltagedomain *voltdm)
+{
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return;
+	}
+
+	if (!sr->autocomp_active)
+		return;
+
+	if (!sr_class || !(sr_class->disable)) {
+		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+			"registered\n", __func__);
+		return;
+	}
+
+	sr_class->disable(sr, 0);
+}
+
+/**
+ * omap_sr_disable_reset_volt() - API to disable SR and reset the
+ *				voltage processor voltage
+ * @voltdm:	VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
+{
+	struct omap_sr *sr = _sr_lookup(voltdm);
+
+	if (IS_ERR(sr)) {
+		pr_warning("%s: omap_sr struct for voltdm not found\n",	__func__);
+		return;
+	}
+
+	if (!sr->autocomp_active)
+		return;
+
+	if (!sr_class || !(sr_class->disable)) {
+		dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+			"registered\n", __func__);
+		return;
+	}
+
+	sr_class->disable(sr, 1);
+}
+
+/**
+ * omap_sr_register_pmic() - API to register pmic specific info.
+ * @pmic_data:	The structure containing pmic specific data.
+ *
+ * This API is to be called from the PMIC specific code to register with
+ * smartreflex driver pmic specific info. Currently the only info required
+ * is the smartreflex init on the PMIC side.
+ */
+void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data)
+{
+	if (!pmic_data) {
+		pr_warning("%s: Trying to register NULL PMIC data structure"
+			"with smartreflex\n", __func__);
+		return;
+	}
+
+	sr_pmic_data = pmic_data;
+}
+
+/* PM Debug FS entries to enable and disable smartreflex. */
+static int omap_sr_autocomp_show(void *data, u64 *val)
+{
+	struct omap_sr *sr_info = data;
+
+	if (!sr_info) {
+		pr_warning("%s: omap_sr struct not found\n", __func__);
+		return -EINVAL;
+	}
+
+	*val = sr_info->autocomp_active;
+
+	return 0;
+}
+
+static int omap_sr_autocomp_store(void *data, u64 val)
+{
+	struct omap_sr *sr_info = data;
+
+	if (!sr_info) {
+		pr_warning("%s: omap_sr struct not found\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Sanity check */
+	if (val > 1) {
+		pr_warning("%s: Invalid argument %lld\n", __func__, val);
+		return -EINVAL;
+	}
+
+	/* control enable/disable only if there is a delta in value */
+	if (sr_info->autocomp_active != val) {
+		if (!val)
+			sr_stop_vddautocomp(sr_info);
+		else
+			sr_start_vddautocomp(sr_info);
+	}
+
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
+			omap_sr_autocomp_store, "%llu\n");
+
+static int __init omap_sr_probe(struct platform_device *pdev)
+{
+	struct omap_sr *sr_info;
+	struct omap_sr_data *pdata = pdev->dev.platform_data;
+	struct resource *mem, *irq;
+	struct dentry *nvalue_dir;
+	int i, ret = 0;
+
+	sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
+	if (!sr_info) {
+		dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
+			__func__);
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, sr_info);
+
+	if (!pdata) {
+		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+		ret = -EINVAL;
+		goto err_free_devinfo;
+	}
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem) {
+		dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
+		ret = -ENODEV;
+		goto err_free_devinfo;
+	}
+
+	mem = request_mem_region(mem->start, resource_size(mem),
+					dev_name(&pdev->dev));
+	if (!mem) {
+		dev_err(&pdev->dev, "%s: no mem region\n", __func__);
+		ret = -EBUSY;
+		goto err_free_devinfo;
+	}
+
+	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+	pm_runtime_enable(&pdev->dev);
+	pm_runtime_irq_safe(&pdev->dev);
+
+	sr_info->name = kasprintf(GFP_KERNEL, "sr_%s", pdata->name);
+	if (!sr_info->name) {
+		dev_err(&pdev->dev, "%s: Unable to alloc SR instance name\n",
+			__func__);
+		ret = -ENOMEM;
+		goto err_release_region;
+	}
+
+	sr_info->pdev = pdev;
+	sr_info->srid = pdev->id;
+	sr_info->voltdm = pdata->voltdm;
+	sr_info->nvalue_table = pdata->nvalue_table;
+	sr_info->nvalue_count = pdata->nvalue_count;
+	sr_info->senn_mod = pdata->senn_mod;
+	sr_info->senp_mod = pdata->senp_mod;
+	sr_info->autocomp_active = false;
+	sr_info->ip_type = pdata->ip_type;
+	sr_info->base = ioremap(mem->start, resource_size(mem));
+	if (!sr_info->base) {
+		dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
+		ret = -ENOMEM;
+		goto err_release_region;
+	}
+
+	if (irq)
+		sr_info->irq = irq->start;
+
+	sr_set_clk_length(sr_info);
+	sr_set_regfields(sr_info);
+
+	list_add(&sr_info->node, &sr_list);
+
+	/*
+	 * Call into late init to do intializations that require
+	 * both sr driver and sr class driver to be initiallized.
+	 */
+	if (sr_class) {
+		ret = sr_late_init(sr_info);
+		if (ret) {
+			pr_warning("%s: Error in SR late init\n", __func__);
+			goto err_iounmap;
+		}
+	}
+
+	dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
+	if (!sr_dbg_dir) {
+		sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
+		if (IS_ERR_OR_NULL(sr_dbg_dir)) {
+			ret = PTR_ERR(sr_dbg_dir);
+			pr_err("%s:sr debugfs dir creation failed(%d)\n",
+				__func__, ret);
+			goto err_iounmap;
+		}
+	}
+
+	sr_info->dbg_dir = debugfs_create_dir(sr_info->name, sr_dbg_dir);
+	if (IS_ERR_OR_NULL(sr_info->dbg_dir)) {
+		dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
+			__func__);
+		ret = PTR_ERR(sr_info->dbg_dir);
+		goto err_free_name;
+	}
+
+	(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
+			sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops);
+	(void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
+			&sr_info->err_weight);
+	(void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
+			&sr_info->err_maxlimit);
+
+	nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
+	if (IS_ERR_OR_NULL(nvalue_dir)) {
+		dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
+			"for n-values\n", __func__);
+		ret = PTR_ERR(nvalue_dir);
+		goto err_debugfs;
+	}
+
+	if (sr_info->nvalue_count == 0 || !sr_info->nvalue_table) {
+		dev_warn(&pdev->dev, "%s: %s: No Voltage table for the corresponding vdd. Cannot create debugfs entries for n-values\n",
+			 __func__, sr_info->name);
+		ret = -ENODATA;
+		goto err_debugfs;
+	}
+
+	for (i = 0; i < sr_info->nvalue_count; i++) {
+		char name[NVALUE_NAME_LEN + 1];
+
+		snprintf(name, sizeof(name), "volt_%lu",
+			 sr_info->nvalue_table[i].volt_nominal);
+		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
+				&(sr_info->nvalue_table[i].nvalue));
+		snprintf(name, sizeof(name), "errminlimit_%lu",
+			 sr_info->nvalue_table[i].volt_nominal);
+		(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
+				&(sr_info->nvalue_table[i].errminlimit));
+	}
+
+	return ret;
+
+err_debugfs:
+	debugfs_remove_recursive(sr_info->dbg_dir);
+err_free_name:
+	kfree(sr_info->name);
+err_iounmap:
+	list_del(&sr_info->node);
+	iounmap(sr_info->base);
+err_release_region:
+	release_mem_region(mem->start, resource_size(mem));
+err_free_devinfo:
+	kfree(sr_info);
+
+	return ret;
+}
+
+static int __devexit omap_sr_remove(struct platform_device *pdev)
+{
+	struct omap_sr_data *pdata = pdev->dev.platform_data;
+	struct omap_sr *sr_info;
+	struct resource *mem;
+
+	if (!pdata) {
+		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+		return -EINVAL;
+	}
+
+	sr_info = _sr_lookup(pdata->voltdm);
+	if (IS_ERR(sr_info)) {
+		dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
+			__func__);
+		return PTR_ERR(sr_info);
+	}
+
+	if (sr_info->autocomp_active)
+		sr_stop_vddautocomp(sr_info);
+	if (sr_info->dbg_dir)
+		debugfs_remove_recursive(sr_info->dbg_dir);
+
+	list_del(&sr_info->node);
+	iounmap(sr_info->base);
+	kfree(sr_info->name);
+	kfree(sr_info);
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(mem->start, resource_size(mem));
+
+	return 0;
+}
+
+static void __devexit omap_sr_shutdown(struct platform_device *pdev)
+{
+	struct omap_sr_data *pdata = pdev->dev.platform_data;
+	struct omap_sr *sr_info;
+
+	if (!pdata) {
+		dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+		return;
+	}
+
+	sr_info = _sr_lookup(pdata->voltdm);
+	if (IS_ERR(sr_info)) {
+		dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
+			__func__);
+		return;
+	}
+
+	if (sr_info->autocomp_active)
+		sr_stop_vddautocomp(sr_info);
+
+	return;
+}
+
+static struct platform_driver smartreflex_driver = {
+	.remove         = __devexit_p(omap_sr_remove),
+	.shutdown	= __devexit_p(omap_sr_shutdown),
+	.driver		= {
+		.name	= "smartreflex",
+	},
+};
+
+static int __init sr_init(void)
+{
+	int ret = 0;
+
+	/*
+	 * sr_init is a late init. If by then a pmic specific API is not
+	 * registered either there is no need for anything to be done on
+	 * the PMIC side or somebody has forgotten to register a PMIC
+	 * handler. Warn for the second condition.
+	 */
+	if (sr_pmic_data && sr_pmic_data->sr_pmic_init)
+		sr_pmic_data->sr_pmic_init();
+	else
+		pr_warning("%s: No PMIC hook to init smartreflex\n", __func__);
+
+	ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe);
+	if (ret) {
+		pr_err("%s: platform driver register failed for SR\n",
+			__func__);
+		return ret;
+	}
+
+	return 0;
+}
+late_initcall(sr_init);
+
+static void __exit sr_exit(void)
+{
+	platform_driver_unregister(&smartreflex_driver);
+}
+module_exit(sr_exit);
+
+MODULE_DESCRIPTION("OMAP Smartreflex Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/drivers/power/avs/smartreflex.h b/drivers/power/avs/smartreflex.h
new file mode 100644
index 0000000..754f6aa
--- /dev/null
+++ b/drivers/power/avs/smartreflex.h
@@ -0,0 +1,238 @@
+/*
+ * OMAP Smartreflex Defines and Routines
+ *
+ * Author: Thara Gopinath	<thara at ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara at ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970 at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DRIVERS_POWER_AVS_SMARTREFLEX_H
+#define __DRIVERS_POWER_AVS_SMARTREFLEX_H
+
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/power/smartreflex.h>
+
+#include <plat/voltage.h>
+
+/*
+ * Different Smartreflex IPs version. The v1 is the 65nm version used in
+ * OMAP3430. The v2 is the update for the 45nm version of the IP
+ * used in OMAP3630 and OMAP4430
+ */
+#define SR_TYPE_V1	1
+#define SR_TYPE_V2	2
+
+/* SMART REFLEX REG ADDRESS OFFSET */
+#define SRCONFIG		0x00
+#define SRSTATUS		0x04
+#define SENVAL			0x08
+#define SENMIN			0x0C
+#define SENMAX			0x10
+#define SENAVG			0x14
+#define AVGWEIGHT		0x18
+#define NVALUERECIPROCAL	0x1c
+#define SENERROR_V1		0x20
+#define ERRCONFIG_V1		0x24
+#define IRQ_EOI			0x20
+#define IRQSTATUS_RAW		0x24
+#define IRQSTATUS		0x28
+#define IRQENABLE_SET		0x2C
+#define IRQENABLE_CLR		0x30
+#define SENERROR_V2		0x34
+#define ERRCONFIG_V2		0x38
+
+/* Bit/Shift Positions */
+
+/* SRCONFIG */
+#define SRCONFIG_ACCUMDATA_SHIFT	22
+#define SRCONFIG_SRCLKLENGTH_SHIFT	12
+#define SRCONFIG_SENNENABLE_V1_SHIFT	5
+#define SRCONFIG_SENPENABLE_V1_SHIFT	3
+#define SRCONFIG_SENNENABLE_V2_SHIFT	1
+#define SRCONFIG_SENPENABLE_V2_SHIFT	0
+#define SRCONFIG_CLKCTRL_SHIFT		0
+
+#define SRCONFIG_ACCUMDATA_MASK		(0x3ff << 22)
+
+#define SRCONFIG_SRENABLE		BIT(11)
+#define SRCONFIG_SENENABLE		BIT(10)
+#define SRCONFIG_ERRGEN_EN		BIT(9)
+#define SRCONFIG_MINMAXAVG_EN		BIT(8)
+#define SRCONFIG_DELAYCTRL		BIT(2)
+
+/* AVGWEIGHT */
+#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT	2
+#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT	0
+
+/* NVALUERECIPROCAL */
+#define NVALUERECIPROCAL_SENPGAIN_SHIFT	20
+#define NVALUERECIPROCAL_SENNGAIN_SHIFT	16
+#define NVALUERECIPROCAL_RNSENP_SHIFT	8
+#define NVALUERECIPROCAL_RNSENN_SHIFT	0
+
+/* ERRCONFIG */
+#define ERRCONFIG_ERRWEIGHT_SHIFT	16
+#define ERRCONFIG_ERRMAXLIMIT_SHIFT	8
+#define ERRCONFIG_ERRMINLIMIT_SHIFT	0
+
+#define SR_ERRWEIGHT_MASK		(0x07 << 16)
+#define SR_ERRMAXLIMIT_MASK		(0xff << 8)
+#define SR_ERRMINLIMIT_MASK		(0xff << 0)
+
+#define ERRCONFIG_VPBOUNDINTEN_V1	BIT(31)
+#define ERRCONFIG_VPBOUNDINTST_V1	BIT(30)
+#define	ERRCONFIG_MCUACCUMINTEN		BIT(29)
+#define ERRCONFIG_MCUACCUMINTST		BIT(28)
+#define	ERRCONFIG_MCUVALIDINTEN		BIT(27)
+#define ERRCONFIG_MCUVALIDINTST		BIT(26)
+#define ERRCONFIG_MCUBOUNDINTEN		BIT(25)
+#define	ERRCONFIG_MCUBOUNDINTST		BIT(24)
+#define	ERRCONFIG_MCUDISACKINTEN	BIT(23)
+#define ERRCONFIG_VPBOUNDINTST_V2	BIT(23)
+#define ERRCONFIG_MCUDISACKINTST	BIT(22)
+#define ERRCONFIG_VPBOUNDINTEN_V2	BIT(22)
+
+#define ERRCONFIG_STATUS_V1_MASK	(ERRCONFIG_VPBOUNDINTST_V1 | \
+					ERRCONFIG_MCUACCUMINTST | \
+					ERRCONFIG_MCUVALIDINTST | \
+					ERRCONFIG_MCUBOUNDINTST | \
+					ERRCONFIG_MCUDISACKINTST)
+/* IRQSTATUS */
+#define IRQSTATUS_MCUACCUMINT		BIT(3)
+#define IRQSTATUS_MCVALIDINT		BIT(2)
+#define IRQSTATUS_MCBOUNDSINT		BIT(1)
+#define IRQSTATUS_MCUDISABLEACKINT	BIT(0)
+
+/* IRQENABLE_SET and IRQENABLE_CLEAR */
+#define IRQENABLE_MCUACCUMINT		BIT(3)
+#define IRQENABLE_MCUVALIDINT		BIT(2)
+#define IRQENABLE_MCUBOUNDSINT		BIT(1)
+#define IRQENABLE_MCUDISABLEACKINT	BIT(0)
+
+/* Common Bit values */
+
+#define SRCLKLENGTH_12MHZ_SYSCLK	0x3c
+#define SRCLKLENGTH_13MHZ_SYSCLK	0x41
+#define SRCLKLENGTH_19MHZ_SYSCLK	0x60
+#define SRCLKLENGTH_26MHZ_SYSCLK	0x82
+#define SRCLKLENGTH_38MHZ_SYSCLK	0xC0
+
+/*
+ * 3430 specific values. Maybe these should be passed from board file or
+ * pmic structures.
+ */
+#define OMAP3430_SR_ACCUMDATA		0x1f4
+
+#define OMAP3430_SR1_SENPAVGWEIGHT	0x03
+#define OMAP3430_SR1_SENNAVGWEIGHT	0x03
+
+#define OMAP3430_SR2_SENPAVGWEIGHT	0x01
+#define OMAP3430_SR2_SENNAVGWEIGHT	0x01
+
+#define OMAP3430_SR_ERRWEIGHT		0x04
+#define OMAP3430_SR_ERRMAXLIMIT		0x02
+
+/**
+ * test_cond_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ *
+ * Copied from omap_test_timeout
+ */
+#define sr_test_cond_timeout(cond, timeout, index)		\
+({								\
+	for (index = 0; index < timeout; index++) {		\
+		if (cond)					\
+			break;					\
+		udelay(1);					\
+	}							\
+})
+
+/**
+ * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
+ *				pmic specific info to smartreflex driver
+ *
+ * @sr_pmic_init:	API to initialize smartreflex on the PMIC side.
+ */
+struct omap_sr_pmic_data {
+	void (*sr_pmic_init) (void);
+};
+
+
+#ifdef CONFIG_POWER_AVS_OMAP
+/*
+ * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
+ * The smartreflex class driver should pass the class type.
+ * Should be used to populate the class_type field of the
+ * omap_smartreflex_class_data structure.
+ */
+#define SR_CLASS1	0x1
+#define SR_CLASS2	0x2
+#define SR_CLASS3	0x3
+
+/**
+ * struct omap_sr_class_data - Smartreflex class driver info
+ *
+ * @enable:		API to enable a particular class smaartreflex.
+ * @disable:		API to disable a particular class smartreflex.
+ * @configure:		API to configure a particular class smartreflex.
+ * @notify:		API to notify the class driver about an event in SR.
+ *			Not needed for class3.
+ * @notify_flags:	specify the events to be notified to the class driver
+ * @class_type:		specify which smartreflex class.
+ *			Can be used by the SR driver to take any class
+ *			based decisions.
+ */
+struct omap_sr_class_data {
+	int (*enable)(struct omap_sr *sr);
+	int (*disable)(struct omap_sr *sr, int is_volt_reset);
+	int (*configure)(struct omap_sr *sr);
+	int (*notify)(struct omap_sr *sr, u32 status);
+	u8 notify_flags;
+	u8 class_type;
+};
+
+/* Smartreflex module enable/disable interface */
+void omap_sr_enable(struct voltagedomain *voltdm);
+void omap_sr_disable(struct voltagedomain *voltdm);
+void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
+
+/* API to register the pmic specific data with the smartreflex driver. */
+void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
+
+/* Smartreflex driver hooks to be called from Smartreflex class driver */
+int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
+void sr_disable(struct voltagedomain *voltdm);
+int sr_configure_errgen(struct voltagedomain *voltdm);
+int sr_disable_errgen(struct voltagedomain *voltdm);
+int sr_configure_minmax(struct voltagedomain *voltdm);
+
+/* API to register the smartreflex class driver with the smartreflex driver */
+int sr_register_class(struct omap_sr_class_data *class_data);
+#else
+static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
+static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+static inline void omap_sr_disable_reset_volt(
+		struct voltagedomain *voltdm) {}
+static inline void omap_sr_register_pmic(
+		struct omap_sr_pmic_data *pmic_data) {}
+#endif
+#endif
-- 
1.7.5.4



From arnd at arndb.de  Mon Mar 19 12:17:47 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 16:17:47 +0000
Subject: [PATCH 8/8] ARM i.MX27: implement clocks using common clock
 framework
In-Reply-To: <20120319143608.GZ3852@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
 <20120319142325.GA32469@S2101-09.ap.freescale.net>
 <20120319143608.GZ3852@pengutronix.de>
Message-ID: <201203191617.47225.arnd@arndb.de>

On Monday 19 March 2012, Sascha Hauer wrote:
> > > +struct clkl {
> > > +   struct clk_lookup lookup;
> > > +   const char *clkname;
> > > +};
> > > +
> > > +#define clkdev(d, n, c) \
> > > +   { \
> > > +           .lookup.dev_id = d, \
> > > +           .lookup.con_id = n, \
> > > +           .clkname = c, \
> > > +   },
> > > +
> > 
> > They should at least be defined in arch/arm/mach-imx/clk.h to avoid
> > the duplication in every single imx clock driver.
> 
> Yes, right. See it as a quick-n-dirty solution...
> 

Or maybe just remove the macro. Open-coding seems to take little more space,
and I actually find it more readable:

static struct clkl lookups[] = {
	{ { .dev_id = "imx21-uart.0", .con_id = "ipg" }, "uart1_ipg_gate" },
	{ { .dev_id = "imx21-uart.0", .con_id = "per" }, "per1_gate" },
	{ { .dev_id = "imx21-uart.1", .con_id = "ipg" }, "uart2_ipg_gate" },
	{ ... },
};

	Arnd


From nicolas.ferre at atmel.com  Mon Mar 19 12:31:32 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 19 Mar 2012 17:31:32 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120319153334.GF16389@n2100.arm.linux.org.uk>
References: <4F22DEF2.5000807@ti.com> <20120317094059.7C2333E08E2@localhost>
 <4F6734DD.3020203@atmel.com> <201203191406.35064.arnd@arndb.de>
 <20120319153334.GF16389@n2100.arm.linux.org.uk>
Message-ID: <4F675F64.6070306@atmel.com>

On 03/19/2012 04:33 PM, Russell King - ARM Linux :
> On Mon, Mar 19, 2012 at 02:06:34PM +0000, Arnd Bergmann wrote:
>> ==== mmci ====
>> /* in drivers/dma/ste_dma40.c, others in pl330.c, coh901318.c, ... */
>> bool stedma40_filter(struct dma_chan *chan, void *data)
>> {               
>>         struct stedma40_chan_cfg *info = data;
>>         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
>>         int err;                
>>         
>>         err = d40_validate_conf(d40c, info);
>>         if (!err)
>>                 d40c->dma_cfg = *info;
>>         d40c->configured = true;
>>         
>>         return err == 0;
>> }
>> EXPORT_SYMBOL(stedma40_filter);
>>
>> /* in mmci.h */
>> struct mmci_platform_data {
>> 	...
>>         bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
>>         void *dma_rx_param;
>>         void *dma_tx_param;
>> };
>>
>> /* in mmci.c */
>> static void __devinit mmci_dma_setup(struct mmci_host *host)
>> {
>> 	...
>>         host->dma_rx_channel = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
>> 	...
>> }
>>
>> ====
>>
>> Whatever we come up with obviously needs to work with both drivers.
>> I think we will end up with something closer to the second one, except
>> that the dma parameters do not come from platform_data but from the
>> #dma-request property, which also identifies the controller and channel.
> 
> Firstly, define what you mean by "the DMA parameters".  Things like burst
> size, register width, register address?  That should all be known by the
> peripheral driver and _not_ be encoded into DT in any way - and this
> information should be passed to the DMA engine driver for the well defined
> API for that purpose.
> 
> Secondly, there are platforms (Samsung) where peripherals are connected
> to more than one DMA controller, and either DMA controller can be used -
> I'm told by Jassi that there's reasons why you'd want to select one or
> other as the target at runtime.
> 
> Whether it's appropriate for DT to know that or not, I'm not certain at
> the moment - I suspect the _right_ solution would be a radical DMA engine
> redesign which moves _all_ slave DMA to a virtual channel representation,
> and for the virtual channels to be scheduled onto a set of physical DMA
> channels over a range of DMA devices.  Obviously, there's restrictions on
> which virtual channels could be scheduled onto which physical channels of
> which DMA devices.

OMG! the dmaengine drivers are already not so obvious to understand. I
fear that trying to mimic some special behaviors within relatively
simple dmaengine drivers will bring confusion and prevent people to
read/contribute and fix those simple ones...

> It seems to me, therefore, that any attempt to come up with some kind of
> DT based representation of the current scheme is doomed to fail, and will
> at some point become obsolete.
> 
> I think instead, rather than trying to fix this now, we persist with what
> we have, but organize an effort to clean up and restructure the DMA engine
> code so that:
> 
> (a) things like the Samsung, and ARM board oddities can be easily dealt
>  with in a driver independent manner.
> (b) get rid of all the duplicated functionality between each different
>  DMA engine implementation, separating this out into core code, and
>  simplifying the drivers.
> 
> The _big_ problem I see is that if we try to represent the existing
> solution in DT, we're going to get locked into that way of doing things
> and then any major restructuring of the DMA engine stuff will become an
> impossibility - especially if we start specifying things by DMA request
> signal numbers on DMA engines.

Even if I understand your point, I wonder what is the solution for us
that have a pretty simple representation of *hardware* to code into DT:
should we wait for a big rework? Should we go for a private DMA binding
for each of us that have just the need for a quite simple representation?

I must say that I am puzzled by recent discussion on the topic (mix of
"channel" and "request" notions, plan for a complete rework of dmaengine
that can delay DT representation of DMA slave-controller relationship,
even my own doubts on the "void *" output parameter, etc.). It seems
that I am not familiar with all those cases and that I cannot go further
with a generic DT representation...

Best regards,
-- 
Nicolas Ferre


From mans at mansr.com  Mon Mar 19 12:34:37 2012
From: mans at mansr.com (=?iso-8859-1?Q?M=E5ns_Rullg=E5rd?=)
Date: Mon, 19 Mar 2012 16:34:37 +0000
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <20120319085503.GL15988@n2100.arm.linux.org.uk>
 <4F674479.8090101@gmail.com>
 <20120319154123.GP15988@n2100.arm.linux.org.uk>
Message-ID: <yw1xehso1rdu.fsf@unicorn.mansr.com>

Russell King - ARM Linux <linux at arm.linux.org.uk> writes:

> On Mon, Mar 19, 2012 at 09:36:41AM -0500, Rob Herring wrote:
>> On 03/19/2012 03:55 AM, Russell King - ARM Linux wrote:
>> > On Mon, Mar 19, 2012 at 04:02:48PM +0900, Boojin Kim wrote:
>> >> This patch uses LDRD/STRD that loads and stores data as DWORD unit
>> >> for the copy of 8-words data.
>> >> It brings better performance than LDRM/STRM that was used originally.
>> > 
>> > And what about CPUs that don't have ldrd/strd ?
>> > 
>> 
>> And what about CPUs that do have ldrd/strd but is slower than ldm/stm?
>> I'm pretty sure that is almost everything currently out there.

Care to give an example?  I can't find one.

> The double-word load/stores were introduced in ARMv6.

Not true.  LDRD/STRD were introduced in ARMv5TE.  ARMv6 relaxed the
alignment requirement of these instructions to 4 bytes from being
implementation defined 4 or 8 bytes in ARMv5TE.

-- 
M?ns Rullg?rd
mans at mansr.com



From robherring2 at gmail.com  Mon Mar 19 12:36:53 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 19 Mar 2012 11:36:53 -0500
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <20120319154123.GP15988@n2100.arm.linux.org.uk>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <20120319085503.GL15988@n2100.arm.linux.org.uk> <4F674479.8090101@gmail.com>
 <20120319154123.GP15988@n2100.arm.linux.org.uk>
Message-ID: <4F6760A5.9040506@gmail.com>

On 03/19/2012 10:41 AM, Russell King - ARM Linux wrote:
> On Mon, Mar 19, 2012 at 09:36:41AM -0500, Rob Herring wrote:
>> On 03/19/2012 03:55 AM, Russell King - ARM Linux wrote:
>>> On Mon, Mar 19, 2012 at 04:02:48PM +0900, Boojin Kim wrote:
>>>> This patch uses LDRD/STRD that loads and stores data as DWORD unit
>>>> for the copy of 8-words data.
>>>> It brings better performance than LDRM/STRM that was used originally.
>>>
>>> And what about CPUs that don't have ldrd/strd ?
>>>
>>
>> And what about CPUs that do have ldrd/strd but is slower than ldm/stm?
>> I'm pretty sure that is almost everything currently out there.
> 
> The double-word load/stores were introduced in ARMv6.  Some Intel based
> CPUs prior to this have the support as well.  Everything else doesn't.
> 
> So taht's nowhere close to 'almost everything'.

I meant of all platforms that support both instructions, ldm/stm will be
faster than ldrd/strd on almost all of them AFAIK. I don't think the
claim about being faster is true for an CortexA9 or anything prior.
Linaro folks have done some benchmarking in this area and would be
better to comment.

Rob


From LW at KARO-electronics.de  Mon Mar 19 12:49:02 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Mon, 19 Mar 2012 17:49:02 +0100
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120319150601.B783A3E05A5@localhost>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
 <20120316030134.GA5161@shlinux2.ap.freescale.net>
 <20120318184749.BB15D3E07BF@localhost>
 <20326.55337.249575.289067@ipc1.ka-ro>
 <20120319150601.B783A3E05A5@localhost>
Message-ID: <20327.25470.723875.916422@ipc1.ka-ro>

Hi,

Grant Likely writes:
> On Mon, 19 Mar 2012 07:54:33 +0100, Lothar Wa?mann <LW at KARO-electronics.de> wrote:
> > Grant Likely writes:
> > > On Fri, 16 Mar 2012 11:01:35 +0800, Dong Aisheng <aisheng.dong at freescale.com> wrote:
> > > > On Thu, Mar 15, 2012 at 07:22:04PM +0800, Lothar Wa?mann wrote:
> > > > > Dong Aisheng writes:
> > > > > > On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa?mann wrote:
> > > > > Anyway there is no definite spec how the MAC address(es) are stored
> > > > > in the fuse map. Thus reading the MAC from there is more or less
> > > > > platform specific.
> > > > > 
> > > > It's just provide one more option since there are customers storing the MAC
> > > > in the fuse map.
> > > 
> > > That should be straight forward to support; have a property that
> > > specifies the method used for fetching/calculating the MAC.
> > > 
> > Executable code stored inside a DT blob? ;)
> 
> I know you're joking here, but I'm going to answer seriously
> anyway... Absolutely not.  What I'm suggesting is a property that
> specifies the method used to determine the mac address.  Something
> like (off the top of my head):
> 
> 	local-mac-address = [01 02 03 00 00 00];
> 	local-mac-mask = [0xff 0xff 0xff 0 0 0];
> 	mac-encoding = "append-serial-number";
> 
That still does not specify where the remaining part of the MAC is
stored and how it should be retrieved.

> > > > > Currently I'm setting up the MAC address for our TX28 from the fuses
> > > > > in the platform code passed via platform_data, but that will obviously
> > > > > not work with DT.
> > > > > 
> > > > Non-dt can also use my proposal, then you only need to pass the fixed part of
> > > > MAC via platfrom data, the left will be read by fec driver.
> > > > 
> > > > > The correct way would probably be to pass the MAC from the bootloader
> > > > > via a DT blob. But that would require all bootloaders to be updated
> > > > > first to support DTS. :(
> > > > > 
> > > > But uboot will face the same problem that can not define a valid MAC
> > > > in dts, did i undertand correctly?
> > > > 
> > > > > An intermediate solution could be using OF_DEV_AUXDATA to pass a
> > > > > platform_data struct that may contain a MAC address set up by the
> > > > > platform code.
> > > > > 
> > > > Yes, it's a way but i'm afraid will not get accepted by dt people.
> > > 
> > > The problem remains; where does the platform code get the MAC address
> > > from?  The kernel has to devise it from *somewhere* and the best place
> > > for that should be in the MAC driver itself.
> > > 
> > The platform code knows how and where the MAC is stored on a specific
> > platform. The driver has no business in knowing platform details like
> > this. Thus only platform code (or the bootloader) can provide the MAC
> > to the driver.
> 
> Okay, if so then it would be wise to have a reliable function for the
> MAC driver to call to lookup it's address as determined by platform
> code.  Alternately, the platform code can write the correct mac
> address into the device tree node at init time (see
> prom_update_property() and prom_add_property()).
> 
That sounds good. Didn't know about those functions. That could be
used to mimic the current behaviour of supplying the MAC via
platform_data.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From swarren at wwwdotorg.org  Mon Mar 19 12:50:31 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 10:50:31 -0600
Subject: [PATCH] ARM: tegra: Include assembler.h in sleep.S to fix build break
Message-ID: <1332175831-5900-1-git-send-email-swarren@wwwdotorg.org>

Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro
IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's
sleep.S to do so.

Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
---
 arch/arm/mach-tegra/sleep.S |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 8f9fde1..48cc7c6 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -22,7 +22,10 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
+#include <asm/assembler.h>
+
 #include <linux/linkage.h>
+
 #include <mach/io.h>
 #include <mach/iomap.h>
 
-- 
1.7.0.4



From nicolas.pitre at linaro.org  Mon Mar 19 12:53:48 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Mon, 19 Mar 2012 12:53:48 -0400 (EDT)
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <4F6760A5.9040506@gmail.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <20120319085503.GL15988@n2100.arm.linux.org.uk> <4F674479.8090101@gmail.com>
 <20120319154123.GP15988@n2100.arm.linux.org.uk> <4F6760A5.9040506@gmail.com>
Message-ID: <alpine.LFD.2.02.1203191244390.24151@xanadu.home>

On Mon, 19 Mar 2012, Rob Herring wrote:

> On 03/19/2012 10:41 AM, Russell King - ARM Linux wrote:
> > On Mon, Mar 19, 2012 at 09:36:41AM -0500, Rob Herring wrote:
> >> On 03/19/2012 03:55 AM, Russell King - ARM Linux wrote:
> >>> On Mon, Mar 19, 2012 at 04:02:48PM +0900, Boojin Kim wrote:
> >>>> This patch uses LDRD/STRD that loads and stores data as DWORD unit
> >>>> for the copy of 8-words data.
> >>>> It brings better performance than LDRM/STRM that was used originally.
> >>>
> >>> And what about CPUs that don't have ldrd/strd ?
> >>>
> >>
> >> And what about CPUs that do have ldrd/strd but is slower than ldm/stm?
> >> I'm pretty sure that is almost everything currently out there.
> > 
> > The double-word load/stores were introduced in ARMv6.  Some Intel based
> > CPUs prior to this have the support as well.  Everything else doesn't.
> > 
> > So taht's nowhere close to 'almost everything'.
> 
> I meant of all platforms that support both instructions, ldm/stm will be
> faster than ldrd/strd on almost all of them AFAIK. I don't think the
> claim about being faster is true for an CortexA9 or anything prior.
> Linaro folks have done some benchmarking in this area and would be
> better to comment.

And more importantly, the generic copy functions in the kernel are 
typically used for small copies in most cases, while people tend to 
benchmark copy functions with large buffers, leading to wrong decisions.
  
The functions worth optimizing for throughput are rather copy_page(), 
copy_user_page(), clear_page(), etc.  And not forgetting that some of 
them areinvoked with a typical cache state for the involved memory.



Nicolas


From swarren at wwwdotorg.org  Mon Mar 19 12:54:01 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 10:54:01 -0600
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203191545.40933.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com> <201203191501.10232.arnd@arndb.de>
 <4F674BC4.2070802@wwwdotorg.org> <201203191545.40933.arnd@arndb.de>
Message-ID: <4F6764A9.8090907@wwwdotorg.org>

On 03/19/2012 09:45 AM, Arnd Bergmann wrote:
> On Monday 19 March 2012, Stephen Warren wrote:
>>> Maybe one can use named properties in a new device node in that case,
>>> like this:
>>>
>>>       bus {
>>>               dma: dma-controller {
>>>                       #dma-cells = <1>;
>>>               };
>>>
>>>               device {
>>>                       compatible = "device";
>>>                       channel: dma-channel {
>>>                               type = <0x1>;
>>>                               name = "foo";
>>>                               number = <23>;
>>>                               direction = <3>;
>>>                       };
>>>                       dma-requests = <&dma &channel>;
>>>               };
>>>       };
>>
>> For reference, this is very similar to how the pinctrl bindings work,
>> except that they require the "channel" node to be a child of the DMA
>> controller, and hence "dma-requests" doesn't contain <&dma &channel>,
>> just <&channel>, since "dma" is the parent (or grand-parent) of "channel".
> 
> Right, but the difference beytween the pinctrl binding and what I
> describe here is that the channel description would be part of the
> dma engine driver specific binding, not the generic binding that
> is visible to device drivers.

That's actually true for pinctrl as well: Common pinctrl bindings cover
the content/format of "dma-requests" and a requirement for a
"dma-channel" node, whereas the per-pin-controller bindings define the
content of node "dma-channel".


From robherring2 at gmail.com  Mon Mar 19 12:54:14 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 19 Mar 2012 11:54:14 -0500
Subject: [PATCH] ARM: tegra: Include assembler.h in sleep.S to fix build
 break
In-Reply-To: <1332175831-5900-1-git-send-email-swarren@wwwdotorg.org>
References: <1332175831-5900-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <4F6764B6.6050109@gmail.com>

On 03/19/2012 11:50 AM, Stephen Warren wrote:
> Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro
> IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's
> sleep.S to do so.
> 
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> ---
>  arch/arm/mach-tegra/sleep.S |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
> index 8f9fde1..48cc7c6 100644
> --- a/arch/arm/mach-tegra/sleep.S
> +++ b/arch/arm/mach-tegra/sleep.S
> @@ -22,7 +22,10 @@
>   * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
>   */
>  
> +#include <asm/assembler.h>
> +

Is there some reason you put this before linux/ include?

>  #include <linux/linkage.h>
> +
>  #include <mach/io.h>
>  #include <mach/iomap.h>
>  



From swarren at wwwdotorg.org  Mon Mar 19 12:56:32 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 10:56:32 -0600
Subject: [PATCH] ARM: tegra: Include assembler.h in sleep.S to fix build
 break
In-Reply-To: <4F6764B6.6050109@gmail.com>
References: <1332175831-5900-1-git-send-email-swarren@wwwdotorg.org>
 <4F6764B6.6050109@gmail.com>
Message-ID: <4F676540.8060903@wwwdotorg.org>

On 03/19/2012 10:54 AM, Rob Herring wrote:
> On 03/19/2012 11:50 AM, Stephen Warren wrote:
>> Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro
>> IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's
>> sleep.S to do so.
>>
>> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
>> ---
>>  arch/arm/mach-tegra/sleep.S |    3 +++
>>  1 files changed, 3 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
...
>> +#include <asm/assembler.h>
>> +
> 
> Is there some reason you put this before linux/ include?

No. I just misremembered which order linux/ and asm/ should go in. Do
you want me to repost?

>>  #include <linux/linkage.h>
>> +
>>  #include <mach/io.h>
>>  #include <mach/iomap.h>


From thierry.reding at avionic-design.de  Mon Mar 19 12:59:40 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Mon, 19 Mar 2012 17:59:40 +0100
Subject: [PATCH] ARM: tegra: Include assembler.h in sleep.S to fix build
 break
In-Reply-To: <1332175831-5900-1-git-send-email-swarren@wwwdotorg.org>
References: <1332175831-5900-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <20120319165939.GB25144@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro
> IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's
> sleep.S to do so.
> 
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> ---
>  arch/arm/mach-tegra/sleep.S |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
> index 8f9fde1..48cc7c6 100644
> --- a/arch/arm/mach-tegra/sleep.S
> +++ b/arch/arm/mach-tegra/sleep.S
> @@ -22,7 +22,10 @@
>   * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
>   */
>  
> +#include <asm/assembler.h>
> +
>  #include <linux/linkage.h>
> +
>  #include <mach/io.h>
>  #include <mach/iomap.h>

I actually had a similar patch that looked pretty much like this:

	-#include <mach/io.h>
	+#include <asm/assembler.h>

The mach/io.h is no longer required AFAICT.

Thierry
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From swarren at wwwdotorg.org  Mon Mar 19 13:07:43 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 11:07:43 -0600
Subject: [PATCH] ARM: tegra: Include assembler.h in sleep.S to fix build break
Message-ID: <1332176863-12537-1-git-send-email-swarren@wwwdotorg.org>

Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro
IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's
sleep.S to do so.

Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
---
v2: Fix linux/ vs. asm/ include ordering. Remove include of io.h too.

 arch/arm/mach-tegra/sleep.S |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 8f9fde1..5b20197 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -23,7 +23,9 @@
  */
 
 #include <linux/linkage.h>
-#include <mach/io.h>
+
+#include <asm/assembler.h>
+
 #include <mach/iomap.h>
 
 #include "flowctrl.h"
-- 
1.7.0.4



From mans.rullgard at linaro.org  Mon Mar 19 13:11:13 2012
From: mans.rullgard at linaro.org (=?iso-8859-1?Q?M=E5ns_Rullg=E5rd?=)
Date: Mon, 19 Mar 2012 17:11:13 +0000
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <20120319085503.GL15988@n2100.arm.linux.org.uk>
 <4F674479.8090101@gmail.com>
 <20120319154123.GP15988@n2100.arm.linux.org.uk>
 <4F6760A5.9040506@gmail.com>
Message-ID: <yw1xaa3c1pou.fsf@unicorn.mansr.com>

Rob Herring <robherring2 at gmail.com> writes:

> On 03/19/2012 10:41 AM, Russell King - ARM Linux wrote:
>> On Mon, Mar 19, 2012 at 09:36:41AM -0500, Rob Herring wrote:
>>> On 03/19/2012 03:55 AM, Russell King - ARM Linux wrote:
>>>> On Mon, Mar 19, 2012 at 04:02:48PM +0900, Boojin Kim wrote:
>>>>> This patch uses LDRD/STRD that loads and stores data as DWORD unit
>>>>> for the copy of 8-words data.
>>>>> It brings better performance than LDRM/STRM that was used originally.
>>>>
>>>> And what about CPUs that don't have ldrd/strd ?
>>>>
>>>
>>> And what about CPUs that do have ldrd/strd but is slower than ldm/stm?
>>> I'm pretty sure that is almost everything currently out there.
>> 
>> The double-word load/stores were introduced in ARMv6.  Some Intel based
>> CPUs prior to this have the support as well.  Everything else doesn't.
>> 
>> So taht's nowhere close to 'almost everything'.
>
> I meant of all platforms that support both instructions, ldm/stm will be
> faster than ldrd/strd on almost all of them AFAIK. I don't think the
> claim about being faster is true for an CortexA9 or anything prior.

The Cortex-A9 TRM insists ldrd and ldm should have the same timing.
However, measuring it suggests that ldm is in fact faster, at least in
some cases.

The Cortex-A8 TRM is a bit unclear, but measuring gives the same speed
for both.

The manuals for older cores suggest equivalent timing, but I don't have
any nearby to test.

-- 
M?ns Rullg?rd
mans at mansr.com



From swarren at wwwdotorg.org  Mon Mar 19 13:36:00 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 11:36:00 -0600
Subject: [PATCH] gpio: tegra: tegra_gpio_config shouldn't be __init
Message-ID: <1332178560-15658-1-git-send-email-swarren@wwwdotorg.org>

This function is called from non-__init context, just like
tegra_gpio_enable()/disable(). Remove the __init annotation to avoid
section mismatch warnings during compile.

Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
---
 drivers/gpio/gpio-tegra.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 636be99..32de670 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -461,7 +461,7 @@ static int __init tegra_gpio_init(void)
 }
 postcore_initcall(tegra_gpio_init);
 
-void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
+void tegra_gpio_config(struct tegra_gpio_table *table, int num)
 {
 	int i;
 
-- 
1.7.0.4



From b-cousson at ti.com  Mon Mar 19 13:49:18 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 19 Mar 2012 18:49:18 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <4F675F64.6070306@atmel.com>
References: <4F22DEF2.5000807@ti.com> <20120317094059.7C2333E08E2@localhost>
 <4F6734DD.3020203@atmel.com> <201203191406.35064.arnd@arndb.de>
 <20120319153334.GF16389@n2100.arm.linux.org.uk> <4F675F64.6070306@atmel.com>
Message-ID: <4F67719E.7040403@ti.com>

Hi Nico,

On 3/19/2012 5:31 PM, Nicolas Ferre wrote:
> On 03/19/2012 04:33 PM, Russell King - ARM Linux :
>> On Mon, Mar 19, 2012 at 02:06:34PM +0000, Arnd Bergmann wrote:
>>> ==== mmci ====
>>> /* in drivers/dma/ste_dma40.c, others in pl330.c, coh901318.c, ... */
>>> bool stedma40_filter(struct dma_chan *chan, void *data)
>>> {
>>>          struct stedma40_chan_cfg *info = data;
>>>          struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
>>>          int err;
>>>
>>>          err = d40_validate_conf(d40c, info);
>>>          if (!err)
>>>                  d40c->dma_cfg = *info;
>>>          d40c->configured = true;
>>>
>>>          return err == 0;
>>> }
>>> EXPORT_SYMBOL(stedma40_filter);
>>>
>>> /* in mmci.h */
>>> struct mmci_platform_data {
>>> 	...
>>>          bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
>>>          void *dma_rx_param;
>>>          void *dma_tx_param;
>>> };
>>>
>>> /* in mmci.c */
>>> static void __devinit mmci_dma_setup(struct mmci_host *host)
>>> {
>>> 	...
>>>          host->dma_rx_channel = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
>>> 	...
>>> }
>>>
>>> ====
>>>
>>> Whatever we come up with obviously needs to work with both drivers.
>>> I think we will end up with something closer to the second one, except
>>> that the dma parameters do not come from platform_data but from the
>>> #dma-request property, which also identifies the controller and channel.
>>
>> Firstly, define what you mean by "the DMA parameters".  Things like burst
>> size, register width, register address?  That should all be known by the
>> peripheral driver and _not_ be encoded into DT in any way - and this
>> information should be passed to the DMA engine driver for the well defined
>> API for that purpose.
>>
>> Secondly, there are platforms (Samsung) where peripherals are connected
>> to more than one DMA controller, and either DMA controller can be used -
>> I'm told by Jassi that there's reasons why you'd want to select one or
>> other as the target at runtime.
>>
>> Whether it's appropriate for DT to know that or not, I'm not certain at
>> the moment - I suspect the _right_ solution would be a radical DMA engine
>> redesign which moves _all_ slave DMA to a virtual channel representation,
>> and for the virtual channels to be scheduled onto a set of physical DMA
>> channels over a range of DMA devices.  Obviously, there's restrictions on
>> which virtual channels could be scheduled onto which physical channels of
>> which DMA devices.
>
> OMG! the dmaengine drivers are already not so obvious to understand. I
> fear that trying to mimic some special behaviors within relatively
> simple dmaengine drivers will bring confusion and prevent people to
> read/contribute and fix those simple ones...
>
>> It seems to me, therefore, that any attempt to come up with some kind of
>> DT based representation of the current scheme is doomed to fail, and will
>> at some point become obsolete.
>>
>> I think instead, rather than trying to fix this now, we persist with what
>> we have, but organize an effort to clean up and restructure the DMA engine
>> code so that:
>>
>> (a) things like the Samsung, and ARM board oddities can be easily dealt
>>   with in a driver independent manner.
>> (b) get rid of all the duplicated functionality between each different
>>   DMA engine implementation, separating this out into core code, and
>>   simplifying the drivers.
>>
>> The _big_ problem I see is that if we try to represent the existing
>> solution in DT, we're going to get locked into that way of doing things
>> and then any major restructuring of the DMA engine stuff will become an
>> impossibility - especially if we start specifying things by DMA request
>> signal numbers on DMA engines.
>
> Even if I understand your point, I wonder what is the solution for us
> that have a pretty simple representation of *hardware* to code into DT:
> should we wait for a big rework? Should we go for a private DMA binding
> for each of us that have just the need for a quite simple representation?
>
> I must say that I am puzzled by recent discussion on the topic (mix of
> "channel" and "request" notions, plan for a complete rework of dmaengine
> that can delay DT representation of DMA slave-controller relationship,
> even my own doubts on the "void *" output parameter, etc.). It seems
> that I am not familiar with all those cases and that I cannot go further
> with a generic DT representation...

I do agree that it appears that some DMA controllers are way more 
complex that the one we were trying to support.
On OMAP, the DMA channels and the DMA requests are completely 
orthogonal, and thus I do not have to provide any information about the 
channel in the DT binding since the SW can affect any request to any 
channel.
Reading the various points from Russell and Arnd, it seems that this is 
not always the case :-(
I guess this is probably the main cause of confusion in this discussion.

So I do not know either how we can progress further on that without a 
clear understanding of what all these DMA controllers are capable of.

Regards,
Benoit


From jassisinghbrar at gmail.com  Mon Mar 19 14:06:31 2012
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Mon, 19 Mar 2012 23:36:31 +0530
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <201203191611.59064.arnd@arndb.de>
References: <4F22DEF2.5000807@ti.com> <201203191406.35064.arnd@arndb.de>
 <20120319153334.GF16389@n2100.arm.linux.org.uk>
 <201203191611.59064.arnd@arndb.de>
Message-ID: <CABb+yY3cJZO_A+Z5vtOkyt5XEX7exhPk5ZG8Mm35n3DFryBk5w@mail.gmail.com>

On Mon, Mar 19, 2012 at 9:41 PM, Arnd Bergmann <arnd at arndb.de> wrote:
>
>> Secondly, there are platforms (Samsung) where peripherals are connected
>> to more than one DMA controller, and either DMA controller can be used -
>> I'm told by Jassi that there's reasons why you'd want to select one or
>> other as the target at runtime.
>
> How common is that? If there are only a few drivers that have this
> requirement, we could have this represented in the driver binding, by
> listing multiple channels and giving the device the choice.
>
All Samsung SoCs (last ~4yrs) with PL330 have some peripherals
that could be served by more than one PL330 instance.
The requirement is not from any driver and it is nothing Samsung specific.
Any platform with 1:n client:dmac might want to do stuff like serving
a new channel request from an already active DMAC, rather than
invoking otherwise fully idle one.
Similarly for Mem->Mem, the PL330 distributes its cycles between
active channels, so a platform might want channel allocation uniformly
across PL330 instances.

-jassi


From tony at atomide.com  Mon Mar 19 14:09:29 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 19 Mar 2012 11:09:29 -0700
Subject: [PATCH v2 7/7] ARM: OMAP2+: Mark omap_hsmmc_init and omap_mux
 related functions as __init
In-Reply-To: <1332152442.2144.27.camel@deskari>
References: <1329997247-27342-1-git-send-email-rnayak@ti.com>
 <1329997247-27342-8-git-send-email-rnayak@ti.com>
 <1332148116.2144.1.camel@deskari>
 <1332152442.2144.27.camel@deskari>
Message-ID: <20120319180928.GA9859@atomide.com>

* Tomi Valkeinen <tomi.valkeinen at ti.com> [120319 03:23]:
> On Mon, 2012-03-19 at 11:08 +0200, Tomi Valkeinen wrote:
> > Hi,
> > 
> > On Thu, 2012-02-23 at 17:10 +0530, Rajendra Nayak wrote:
> > > From: Tony Lindgren <tony at atomide.com>
> > > 
> > > Now that omap hsmmc init is split into two functions, it's safe
> > > to mark omap_hsmmc_init and omap_mux related functions to __init.
> > > 
> > > This basically reverts the following fixes for the case where
> > > TWL was compiled as a module:
> > > 
> > > a98f77b (ARM: omap: fix section mismatch warning for sdp3430_twl_gpio_setup())
> > > 8930b4e (ARM: omap: fix section mismatch warnings in mux.c caused by hsmmc.c)
> > > 
> > > Additionally it fixes up the remaining section warnings for
> > > all callers of omap_mux functions.
> > 
> > I only now noticed this patch. This breaks DSI, as the DSI muxing
> > functions are used during runtime and cannot be marked as __init.
> > 
> > Shall I make a new patch for dss tree that fixes this?
> 
> (too little coffee)
> 
> Obviously I can't make a fix in my tree for that, as the problematic
> patch is not present there... So here's a patch to fix it, based on
> arm-soc/for-next

Thanks yeah those are not even using omap_mux_init* functions, so I
must have accidentally converted blindly those while fixing up the
omap_mux_init* calling functions, sorry.

Looks like only omap4_hdmi_mux_pads needs to be __init as it's
calling omap_mux_init_signal.

It gets called from omap_hdmi_init, and omap_hdmi_init and it's callers
are already marked __init. The reason it's not producing a section
warning is probably because it gets inlined.

I've updated your patch a bit for the comments a bit and marked
omap4_hdmi_mux_pads as __init, will apply to fixes. Updated patch
below.

Regards,

Tony


From: Tomi Valkeinen <tomi.valkeinen at ti.com>
Date: Mon, 19 Mar 2012 11:08:54 +0200
Subject: [PATCH] ARM: OMAP2+: Remove __init from DSI mux functions

Commit d1589f0912533e6cb2ac8fd6f1feb3d5989fe8cb (ARM: OMAP2+: Mark
omap_hsmmc_init and omap_mux related functions as __init) changed DSI
muxing functions to __init. This doesn't work, as the muxing functions
are used every time a DSI display is enabled or disabled.

This patch removes the __inits from DSI mux functions that were
accidentally marked as __init, and makes omap4_hdmi_mux_pads __init
like it should be.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen at ti.com>
[tony at atomide.com: update comments, mark omap4_hdmi_mux_pads __init]
Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -99,7 +99,7 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
 	{ "dss_hdmi", "omapdss_hdmi", -1 },
 };
 
-static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
+static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
 {
 	u32 reg;
 	u16 control_i2c_1;
@@ -125,7 +125,7 @@ static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
 	}
 }
 
-static int __init omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
+static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 {
 	u32 enable_mask, enable_shift;
 	u32 pipd_mask, pipd_shift;
@@ -166,7 +166,7 @@ int __init omap_hdmi_init(enum omap_hdmi_flags flags)
 	return 0;
 }
 
-static int __init omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
+static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 {
 	if (cpu_is_omap44xx())
 		return omap4_dsi_mux_pads(dsi_id, lane_mask);
@@ -174,7 +174,7 @@ static int __init omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 	return 0;
 }
 
-static void __init omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
+static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
 {
 	if (cpu_is_omap44xx())
 		omap4_dsi_mux_pads(dsi_id, 0);


From robherring2 at gmail.com  Mon Mar 19 14:10:25 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Mon, 19 Mar 2012 13:10:25 -0500
Subject: [PATCH] ARM: tegra: Include assembler.h in sleep.S to fix build
 break
In-Reply-To: <1332176863-12537-1-git-send-email-swarren@wwwdotorg.org>
References: <1332176863-12537-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <4F677691.8020307@gmail.com>

On 03/19/2012 12:07 PM, Stephen Warren wrote:
> Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro
> IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's
> sleep.S to do so.
> 
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>

Acked-by: Rob Herring <rob.herring at calxeda.com>

> ---
> v2: Fix linux/ vs. asm/ include ordering. Remove include of io.h too.
> 
>  arch/arm/mach-tegra/sleep.S |    4 +++-
>  1 files changed, 3 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
> index 8f9fde1..5b20197 100644
> --- a/arch/arm/mach-tegra/sleep.S
> +++ b/arch/arm/mach-tegra/sleep.S
> @@ -23,7 +23,9 @@
>   */
>  
>  #include <linux/linkage.h>
> -#include <mach/io.h>
> +
> +#include <asm/assembler.h>
> +
>  #include <mach/iomap.h>
>  
>  #include "flowctrl.h"



From mturquette at ti.com  Mon Mar 19 14:56:11 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Mon, 19 Mar 2012 11:56:11 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <4F6404C2.7000506@codeaurora.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <4F6404C2.7000506@codeaurora.org>
Message-ID: <CAJOA=zP1HHqBNS4V2dN=Q9oOcOErQj8W__fB_qRyZeNLBk7VJg@mail.gmail.com>

On Fri, Mar 16, 2012 at 8:28 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
> On 03/15/2012 11:11 PM, Mike Turquette wrote:
>>
>> The common clock framework defines a common struct clk useful across
>> most platforms as well as an implementation of the clk api that drivers
>> can use safely for managing clocks.
>>
>> The net result is consolidation of many different struct clk definitions
>> and platform-specific clock framework implementations.
>>
>> This patch introduces the common struct clk, struct clk_ops and an
>> implementation of the well-known clock api in include/clk/clk.h.
>> Platforms may define their own hardware-specific clock structure and
>> their own clock operation callbacks, so long as it wraps an instance of
>> struct clk_hw.
>>
>> See Documentation/clk.txt for more details.
>>
>> This patch is based on the work of Jeremy Kerr, which in turn was based
>> on the work of Ben Herrenschmidt.
>>
>> Signed-off-by: Mike Turquette<mturquette at linaro.org>
>> Signed-off-by: Mike Turquette<mturquette at ti.com>
>> Reviewed-by: Thomas Gleixner<tglx at linutronix.de>
>> Tested-by: Andrew Lunn<andrew at lunn.ch>
>> Reviewed-by: Rob Herring<rob.herring<at> ?calxeda.com>
>> Cc: Russell King<linux at arm.linux.org.uk>
>> Cc: Jeremy Kerr<jeremy.kerr at canonical.com>
>> Cc: Arnd Bergman<arnd.bergmann at linaro.org>
>> Cc: Paul Walmsley<paul at pwsan.com>
>> Cc: Shawn Guo<shawn.guo at freescale.com>
>> Cc: Sascha Hauer<s.hauer at pengutronix.de>
>> Cc: Richard Zhao<richard.zhao at linaro.org>
>> Cc: Saravana Kannan<skannan at codeaurora.org>
>> Cc: Magnus Damm<magnus.damm at gmail.com>
>> Cc: Mark Brown<broonie at opensource.wolfsonmicro.com>
>> Cc: Linus Walleij<linus.walleij at stericsson.com>
>> Cc: Stephen Boyd<sboyd at codeaurora.org>
>> Cc: Amit Kucheria<amit.kucheria at linaro.org>
>> Cc: Deepak Saxena<dsaxena at linaro.org>
>> Cc: Grant Likely<grant.likely at secretlab.ca>
>> ---
>
>
> Mike,
>
> Thanks for the patches! Glad to see that it's finally getting in! I sent a
> request for a minor change as a reply to the v5 series (since it had more
> context). Can you please take a look at that and let me know if you can send
> out a v8 or a patch on top of this to do that?

Hi Saravana,

I'm not sending a v8 series since Arnd has taken in v7 for the 3.4 merge window.

I'm formulating a reply to your v5 queries, but I'm not done looking
at the implications of the initializer stuff.  Lets keep the technical
discussion in that thread for now.

Regards,
Mike

>
> Thanks,
> Saravana
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From mturquette at ti.com  Mon Mar 19 14:58:19 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Mon, 19 Mar 2012 11:58:19 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <20120318134623.GB29638@S2101-09.ap.freescale.net>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120318134623.GB29638@S2101-09.ap.freescale.net>
Message-ID: <CAJOA=zNtbcoCyrPxuH2vkfBccA9htxP-j2wNxFpJQsy_TdG++Q@mail.gmail.com>

On Sun, Mar 18, 2012 at 6:46 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> Reading the documentation of function clk_set_rate(), I'm not sure
> it exactly matches what the code does.
>
> If there is mismatch, it might be worth sending an incremental patch
> to update the documentation and avoid the confusion?

The clk_set_rate code did change rapidly leading up to the merge
request, and updating the documentation slipped through the cracks.
I'll cook up a patch and it can probably go in one of the -rc's for
3.4.  I'll take in all of your comments below.

Thanks,
Mike

>
> On Thu, Mar 15, 2012 at 11:11:19PM -0700, Mike Turquette wrote:
>> +/**
>> + * clk_set_rate - specify a new rate for clk
>> + * @clk: the clk whose rate is being changed
>> + * @rate: the new rate for clk
>> + *
>> + * In the simplest case clk_set_rate will only change the rate of clk.
>> + *
>> + * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call
>> + * will fail; only when the clk is disabled will it be able to change
>> + * its rate.
>> + *
>> + * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to
>> + * recursively propagate up to clk's parent; whether or not this happens
>> + * depends on the outcome of clk's .round_rate implementation. ?If
>> + * *parent_rate is 0 after calling .round_rate then upstream parent
>
> Might "*parent_rate is not changed" be more accurate?
>
>> + * propagation is ignored. ?If *parent_rate comes back with a new rate
>> + * for clk's parent then we propagate up to clk's parent and set it's
>> + * rate. ?Upward propagation will continue until either a clk does not
>> + * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting
>> + * changes to clk's parent_rate.
>
>> + * If there is a failure during upstream
>> + * propagation then clk_set_rate will unwind and restore each clk's rate
>> + * that had been successfully changed. ?Afterwards a rate change abort
>> + * notification will be propagated downstream, starting from the clk
>> + * that failed.
>
> I'm not sure this part still matches the code.
>
>> + *
>> + * At the end of all of the rate setting, clk_set_rate internally calls
>> + * __clk_recalc_rates and propagates the rate changes downstream,
>
> I do not see __clk_recalc_rates is called by clk_set_rate in any way.
>
> Regards,
> Shawn
>
>> + * starting from the highest clk whose rate was changed. ?This has the
>> + * added benefit of propagating post-rate change notifiers.
>> + *
>> + * Note that while post-rate change and rate change abort notifications
>> + * are guaranteed to be sent to a clk only once per call to
>> + * clk_set_rate, pre-change notifications will be sent for every clk
>> + * whose rate is changed. ?Stacking pre-change notifications is noisy
>> + * for the drivers subscribed to them, but this allows drivers to react
>> + * to intermediate clk rate changes up until the point where the final
>> + * rate is achieved at the end of upstream propagation.
>> + *
>> + * Returns 0 on success, -EERROR otherwise.
>> + */
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From mturquette at ti.com  Mon Mar 19 15:00:13 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Mon, 19 Mar 2012 12:00:13 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <20120318140707.GC29638@S2101-09.ap.freescale.net>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120318140707.GC29638@S2101-09.ap.freescale.net>
Message-ID: <CAJOA=zMQeGL-D-Zk83qhR1zaY-N+HfFufO3uhgConUbLHnab+g@mail.gmail.com>

On Sun, Mar 18, 2012 at 7:07 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> Another trivial comment. ?But if there is an incremental patch, maybe
> consider to include it.
>
> On Thu, Mar 15, 2012 at 11:11:19PM -0700, Mike Turquette wrote:
> ...
>> +#ifdef CONFIG_COMMON_CLK_DISABLE_UNUSED
>> +static int clk_disable_unused(void)
>> +{
>> + ? ? struct clk *clk;
>> + ? ? struct hlist_node *tmp;
>> +
>> + ? ? mutex_lock(&prepare_lock);
>> +
>> + ? ? hlist_for_each_entry(clk, tmp, &clk_root_list, child_node)
>> + ? ? ? ? ? ? clk_disable_unused_subtree(clk);
>> +
>> + ? ? hlist_for_each_entry(clk, tmp, &clk_orphan_list, child_node)
>> + ? ? ? ? ? ? clk_disable_unused_subtree(clk);
>> +
>> + ? ? mutex_unlock(&prepare_lock);
>> +
>> + ? ? return 0;
>> +}
>> +late_initcall(clk_disable_unused);
>> +#else
>> +static inline int clk_disable_unused(struct clk *clk) { return 0; }
>
> This #else block seems completely unnecessary to me.
>
>> +#endif /* CONFIG_COMMON_CLK_DISABLE_UNUSED */

Oops.  This is a leftover from when there was a separate
drivers/clk/clk-debug.c which implemented this stuff.  I'll make a
cleanup series and roll all these little things into it.

Thanks,
Mike


From mturquette at ti.com  Mon Mar 19 15:09:01 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Mon, 19 Mar 2012 12:09:01 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <20120319112858.GX3852@pengutronix.de>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <4F6716DD.5090900@ti.com> <20120319112858.GX3852@pengutronix.de>
Message-ID: <CAJOA=zOgHXy1_J+LG1LUWwsESwrtqAvrgHKUR22AJdsbRHa+YA@mail.gmail.com>

On Mon, Mar 19, 2012 at 4:28 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Mon, Mar 19, 2012 at 04:52:05PM +0530, Rajendra Nayak wrote:
>> Hi Mike,
>>
>> >+/*
>> >+ * calculate the new rates returning the topmost clock that has to be
>> >+ * changed.
>> >+ */
>> >+static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
>> >+{
>> >+ ? ?struct clk *top = clk;
>> >+ ? ?unsigned long best_parent_rate = clk->parent->rate;
>>
>> Shouldn't you check for a valid parent before dereferencing it? A
>> clk_set_rate() on a root clock might throw up some issues otherwise.
>>
>
> Yes, should be checked.

The clk_calc_new_rates code assumes a valid parent pointer in several
locations.  Thanks for the catch Rajendra.  Will roll into my fixes
series.

>> >+ ? ?unsigned long new_rate;
>> >+
>> >+ ? ?if (!clk->ops->round_rate&& ?!(clk->flags& ?CLK_SET_RATE_PARENT)) {
>> >+ ? ? ? ? ? ?clk->new_rate = clk->rate;
>> >+ ? ? ? ? ? ?return NULL;
>>
>> So does this mean a clk_set_rate() fails for a clk which does not have
>> a valid .round_rate and does not have a CLK_SET_RATE_PARENT flag set?
>> I was thinking this could do a..
>> ? ? ? ? ? ? ? clk->new_rate = rate;
>> ? ? ? ? ? ? ? top = clk;
>> ? ? ? ? ? ? ? goto out;
>> ..instead.
>
> The core should make sure that either both set_rate and round_rate are
> present or none of them.

Agreed.  The documentation covers which clk_ops are hard dependencies
(based on supported operations), but the code doesn't strictly check
this.  I'll add a small state machine to __clk_init which validates
that .round_rate, .recalc_rate and .set_rate are *all* present if any
one of them are present, and present a WARN if otherwise.

Thanks,
Mike


From skannan at codeaurora.org  Mon Mar 19 15:13:37 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Mon, 19 Mar 2012 12:13:37 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zP1HHqBNS4V2dN=Q9oOcOErQj8W__fB_qRyZeNLBk7VJg@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <4F6404C2.7000506@codeaurora.org>
 <CAJOA=zP1HHqBNS4V2dN=Q9oOcOErQj8W__fB_qRyZeNLBk7VJg@mail.gmail.com>
Message-ID: <4F678561.3040105@codeaurora.org>

On 03/19/2012 11:56 AM, Turquette, Mike wrote:
> On Fri, Mar 16, 2012 at 8:28 PM, Saravana Kannan<skannan at codeaurora.org>  wrote:
>> On 03/15/2012 11:11 PM, Mike Turquette wrote:
>>>
>>> The common clock framework defines a common struct clk useful across
>>> most platforms as well as an implementation of the clk api that drivers
>>> can use safely for managing clocks.
>>>
>>> The net result is consolidation of many different struct clk definitions
>>> and platform-specific clock framework implementations.
>>>
>>> This patch introduces the common struct clk, struct clk_ops and an
>>> implementation of the well-known clock api in include/clk/clk.h.
>>> Platforms may define their own hardware-specific clock structure and
>>> their own clock operation callbacks, so long as it wraps an instance of
>>> struct clk_hw.
>>>
>>> See Documentation/clk.txt for more details.
>>>
>>> This patch is based on the work of Jeremy Kerr, which in turn was based
>>> on the work of Ben Herrenschmidt.
>>>
>>> Signed-off-by: Mike Turquette<mturquette at linaro.org>
>>> Signed-off-by: Mike Turquette<mturquette at ti.com>
>>> Reviewed-by: Thomas Gleixner<tglx at linutronix.de>
>>> Tested-by: Andrew Lunn<andrew at lunn.ch>
>>> Reviewed-by: Rob Herring<rob.herring<at>    calxeda.com>
>>> Cc: Russell King<linux at arm.linux.org.uk>
>>> Cc: Jeremy Kerr<jeremy.kerr at canonical.com>
>>> Cc: Arnd Bergman<arnd.bergmann at linaro.org>
>>> Cc: Paul Walmsley<paul at pwsan.com>
>>> Cc: Shawn Guo<shawn.guo at freescale.com>
>>> Cc: Sascha Hauer<s.hauer at pengutronix.de>
>>> Cc: Richard Zhao<richard.zhao at linaro.org>
>>> Cc: Saravana Kannan<skannan at codeaurora.org>
>>> Cc: Magnus Damm<magnus.damm at gmail.com>
>>> Cc: Mark Brown<broonie at opensource.wolfsonmicro.com>
>>> Cc: Linus Walleij<linus.walleij at stericsson.com>
>>> Cc: Stephen Boyd<sboyd at codeaurora.org>
>>> Cc: Amit Kucheria<amit.kucheria at linaro.org>
>>> Cc: Deepak Saxena<dsaxena at linaro.org>
>>> Cc: Grant Likely<grant.likely at secretlab.ca>
>>> ---
>>
>>
>> Mike,
>>
>> Thanks for the patches! Glad to see that it's finally getting in! I sent a
>> request for a minor change as a reply to the v5 series (since it had more
>> context). Can you please take a look at that and let me know if you can send
>> out a v8 or a patch on top of this to do that?
>
> Hi Saravana,

Hi Mike,

> I'm not sending a v8 series since Arnd has taken in v7 for the 3.4 merge window.

Yeah, I later realized it might be better to send patches on top of v7.

> I'm formulating a reply to your v5 queries, but I'm not done looking
> at the implications of the initializer stuff.  Lets keep the technical
> discussion in that thread for now.

I saw some responses from you over the weekend but not to mine. So, I 
assumed you were busy with other stuff and I started working on a patch 
on top of v7. I will send that out if I get around to finishing it 
before you do. Hope that's alright with you.

Based on what I have done so far, to me it just looked like a search and 
replace of clk->name with clk->hw.name and similar changes for the rest 
of the fields. It looks like we might be able to remove 
clk_register_mux, clk_register_divider, etc if we go with this. No stong 
opinion about removing those, but they seemed redundant after the 
suggester refactor.

I think it would be okay to just move those init fields into clk_hw and 
not bother with renaming it to clk_initializer (I would prefer, clk_info 
or clk_common) if it makes the match much less invasive.


Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From tony at atomide.com  Mon Mar 19 15:17:44 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 19 Mar 2012 12:17:44 -0700
Subject: [PATCH v2 0/4] ARM: OMAP: boards: changes to support dynamic
 irq alloc
In-Reply-To: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <20120319191743.GB9859@atomide.com>

* Tarun Kanti DebBarma <tarun.kanti at ti.com> [120319 05:09]:
> These two patches incorporate changes to OMAP1 and OMAP2 platforms
> board files whereby older references to OMAP_GPIO_IRQ macro are
> now replaced with gpio_to_irq(), thereby getting rid of static
> irq references.
> 
> Reference: git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git omap/dt
> Commit: 9a0cee711448335ec43eae83272495e9334c0098

Can you please tell the exact two commits causing this
breakage?

I'm baffled how despite all the effort for previnting
issues like this this still happen. These all seem valid
fixes and clean up things, but how come this was not seen
earlier?

Regards,

Tony


From mturquette at ti.com  Mon Mar 19 15:33:05 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Mon, 19 Mar 2012 12:33:05 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <4F678561.3040105@codeaurora.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <4F6404C2.7000506@codeaurora.org>
 <CAJOA=zP1HHqBNS4V2dN=Q9oOcOErQj8W__fB_qRyZeNLBk7VJg@mail.gmail.com>
 <4F678561.3040105@codeaurora.org>
Message-ID: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>

On Mon, Mar 19, 2012 at 12:13 PM, Saravana Kannan
<skannan at codeaurora.org> wrote:
> I saw some responses from you over the weekend but not to mine. So, I
> assumed you were busy with other stuff and I started working on a patch on
> top of v7.

I only answer trivial emails on the weekend ;-)

> I will send that out if I get around to finishing it before you
> do. Hope that's alright with you.

I'm happy to for you to take a crack at it.  I don't know what your
implementation looks like, but here are a couple concerns I have:

1) if you're copying the data from the initializer over to the struct
clk then make sure you handle the __init data aspects of it properly

2) are the members of struct clk_hw visible to the rest of the world?
Are they modifiable (i.e., not const)?  This is undesirable.

Thanks,
Mike


From aaro.koskinen at iki.fi  Mon Mar 19 15:40:16 2012
From: aaro.koskinen at iki.fi (Aaro Koskinen)
Date: Mon, 19 Mar 2012 21:40:16 +0200
Subject: [PATCH] ARM: iop: add missing includes
In-Reply-To: <1329344682-29962-1-git-send-email-olof@lixom.net>
References: <1329344682-29962-1-git-send-email-olof@lixom.net>
Message-ID: <20120319194016.GA708@ultra.musicnaut.iki.fi>

Hi,

On Wed, Feb 15, 2012 at 02:24:42PM -0800, Olof Johansson wrote:
> Resolves two build breaks. One is a boatload of "unknown type name 'u32'"
> in iop3xx.h due to missing include of <linux/types.h>.
> 
> The other is:
> arch/arm/plat-iop/restart.c: In function 'iop3xx_restart':
> arch/arm/plat-iop/restart.c:18:2: error: implicit declaration of function 'soft_restart' [-Werror=implicit-function-declaration]
> 
> Signed-off-by: Olof Johansson <olof at lixom.net>

Any chance to get this patch into 3.3.1 (stable), when and if such is made?

The v3.3 fails to build for IOP boards without this.

> ---
> 
>  arch/arm/include/asm/hardware/iop3xx.h |    2 ++
>  arch/arm/plat-iop/restart.c            |    1 +
>  2 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
> index 077c323..ec0224d 100644
> --- a/arch/arm/include/asm/hardware/iop3xx.h
> +++ b/arch/arm/include/asm/hardware/iop3xx.h
> @@ -15,6 +15,8 @@
>  #ifndef __IOP3XX_H
>  #define __IOP3XX_H
>  
> +#include <linux/types.h>
> +
>  /*
>   * IOP3XX GPIO handling
>   */
> diff --git a/arch/arm/plat-iop/restart.c b/arch/arm/plat-iop/restart.c
> index 6a85a0c..a6ee3b6 100644
> --- a/arch/arm/plat-iop/restart.c
> +++ b/arch/arm/plat-iop/restart.c
> @@ -8,6 +8,7 @@
>   * published by the Free Software Foundation.
>   */
>  #include <asm/hardware/iop3xx.h>
> +#include <asm/system.h>
>  #include <mach/hardware.h>
>  
>  void iop3xx_restart(char mode, const char *cmd)
> -- 
> 1.7.9.209.gb6b3b

A.


From gregkh at linuxfoundation.org  Mon Mar 19 15:46:53 2012
From: gregkh at linuxfoundation.org (Greg KH)
Date: Mon, 19 Mar 2012 12:46:53 -0700
Subject: [PATCH] ARM: iop: add missing includes
In-Reply-To: <20120319194016.GA708@ultra.musicnaut.iki.fi>
References: <1329344682-29962-1-git-send-email-olof@lixom.net>
 <20120319194016.GA708@ultra.musicnaut.iki.fi>
Message-ID: <20120319194653.GA9308@kroah.com>

On Mon, Mar 19, 2012 at 09:40:16PM +0200, Aaro Koskinen wrote:
> Hi,
> 
> On Wed, Feb 15, 2012 at 02:24:42PM -0800, Olof Johansson wrote:
> > Resolves two build breaks. One is a boatload of "unknown type name 'u32'"
> > in iop3xx.h due to missing include of <linux/types.h>.
> > 
> > The other is:
> > arch/arm/plat-iop/restart.c: In function 'iop3xx_restart':
> > arch/arm/plat-iop/restart.c:18:2: error: implicit declaration of function 'soft_restart' [-Werror=implicit-function-declaration]
> > 
> > Signed-off-by: Olof Johansson <olof at lixom.net>
> 
> Any chance to get this patch into 3.3.1 (stable), when and if such is made?
> 
> The v3.3 fails to build for IOP boards without this.

<formletter>

This is not the correct way to submit patches for inclusion in the
stable kernel tree.  Please read Documentation/stable_kernel_rules.txt
for how to do this properly.

</formletter>


From skannan at codeaurora.org  Mon Mar 19 15:49:10 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Mon, 19 Mar 2012 12:49:10 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <4F6404C2.7000506@codeaurora.org>
 <CAJOA=zP1HHqBNS4V2dN=Q9oOcOErQj8W__fB_qRyZeNLBk7VJg@mail.gmail.com>
 <4F678561.3040105@codeaurora.org>
 <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
Message-ID: <4F678DB6.5090006@codeaurora.org>

On 03/19/2012 12:33 PM, Turquette, Mike wrote:
> On Mon, Mar 19, 2012 at 12:13 PM, Saravana Kannan
> <skannan at codeaurora.org>  wrote:
>> I saw some responses from you over the weekend but not to mine. So, I
>> assumed you were busy with other stuff and I started working on a patch on
>> top of v7.
>
> I only answer trivial emails on the weekend ;-)
>
>> I will send that out if I get around to finishing it before you
>> do. Hope that's alright with you.
>
> I'm happy to for you to take a crack at it.  I don't know what your
> implementation looks like, but here are a couple concerns I have:
>
> 1) if you're copying the data from the initializer over to the struct
> clk then make sure you handle the __init data aspects of it properly

Not copying them into clk again. Just leaving them in clk_hw and using 
them as is. The only fields moved into clk_hw are:
+       const char              *name;
+       const struct clk_ops    *ops;
+       char                    **parent_names;
+       u8                      num_parents;
+       unsigned long           flags;

>
> 2) are the members of struct clk_hw visible to the rest of the world?
> Are they modifiable (i.e., not const)?  This is undesirable.

I'm leaving the const as is. Some of them you can't mark as const if you 
want to dynamically create them.

Yes, they are visible to all the platform drivers (not the rest of the 
world). But these values are provided by the platform drivers anyway, so 
I don't see a problem with it.

I also don't see any useful hacks a platform driver can do by messing 
with this fields without crashing the kernel since they don't have 
access to the locks.

flags might be the one that provides some possibilities since I think 
you look at them often in the core code. We could just copy it into clk 
if people really feel strongly about it. At the worst case, we can have 
a full copy of all these fields inside clk and copy all of them over, 
but I think that would be overkill for things like names, ops and parent 
info.

Thanks,
Saravana
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From mturquette at ti.com  Mon Mar 19 15:53:50 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Mon, 19 Mar 2012 12:53:50 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <4F6716DD.5090900@ti.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <4F6716DD.5090900@ti.com>
Message-ID: <CAJOA=zMPrf-JH_Pmzvkb==1Ew0g4oVS2L=ecJE3WxXsJ4GWkgg@mail.gmail.com>

On Mon, Mar 19, 2012 at 4:22 AM, Rajendra Nayak <rnayak at ti.com> wrote:
> On Friday 16 March 2012 11:41 AM, Mike Turquette wrote:
>> +/*
>> + * calculate the new rates returning the topmost clock that has to be
>> + * changed.
>> + */
>> +static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long
>> rate)
>> +{
>> + ? ? ? struct clk *top = clk;
>> + ? ? ? unsigned long best_parent_rate = clk->parent->rate;
>
>
> Shouldn't you check for a valid parent before dereferencing it? A
> clk_set_rate() on a root clock might throw up some issues otherwise.

Yes, the clk_calc_new_rates code assumes a valid parent pointer in
several locations.  Thanks for the catch.  Will roll into my fixes
series.

Regards,
Mike


From swarren at wwwdotorg.org  Mon Mar 19 16:09:52 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 14:09:52 -0600
Subject: [PATCH] ARM: tegra: Fix device tree AUXDATA for USB/EHCI
Message-ID: <1332187792-14651-1-git-send-email-swarren@wwwdotorg.org>

Commit 4a53f4e "USB: ehci-tegra: add probing through device tree" added
AUXDATA for Tegra's USB/EHCI controller. However, it pointed the platform
data at a location containing the address of the intended platform data,
rather than the platform data itself. This change fixes that.

Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
Cc: <stable at vger.kernel.org> # 3.3
---
 arch/arm/mach-tegra/board-dt-tegra20.c |    6 +++---
 arch/arm/mach-tegra/devices.c          |    7 +++----
 arch/arm/mach-tegra/devices.h          |    5 +++++
 3 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index e20b419..0952494 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -68,11 +68,11 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra-i2s.1", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
-		       &tegra_ehci1_device.dev.platform_data),
+		       &tegra_ehci1_pdata),
 	OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
-		       &tegra_ehci2_device.dev.platform_data),
+		       &tegra_ehci2_pdata),
 	OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
-		       &tegra_ehci3_device.dev.platform_data),
+		       &tegra_ehci3_pdata),
 	{}
 };
 
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 7a2a02d..5f6b867 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -23,7 +23,6 @@
 #include <linux/fsl_devices.h>
 #include <linux/serial_8250.h>
 #include <linux/i2c-tegra.h>
-#include <linux/platform_data/tegra_usb.h>
 #include <asm/pmu.h>
 #include <mach/irqs.h>
 #include <mach/iomap.h>
@@ -446,18 +445,18 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
 	.clk = "cdev2",
 };
 
-static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
+struct tegra_ehci_platform_data tegra_ehci1_pdata = {
 	.operating_mode = TEGRA_USB_OTG,
 	.power_down_on_bus_suspend = 1,
 };
 
-static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
+struct tegra_ehci_platform_data tegra_ehci2_pdata = {
 	.phy_config = &tegra_ehci2_ulpi_phy_config,
 	.operating_mode = TEGRA_USB_HOST,
 	.power_down_on_bus_suspend = 1,
 };
 
-static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
+struct tegra_ehci_platform_data tegra_ehci3_pdata = {
 	.operating_mode = TEGRA_USB_HOST,
 	.power_down_on_bus_suspend = 1,
 };
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
index 873ecb2..ec45567 100644
--- a/arch/arm/mach-tegra/devices.h
+++ b/arch/arm/mach-tegra/devices.h
@@ -20,6 +20,11 @@
 #define __MACH_TEGRA_DEVICES_H
 
 #include <linux/platform_device.h>
+#include <linux/platform_data/tegra_usb.h>
+
+extern struct tegra_ehci_platform_data tegra_ehci1_pdata;
+extern struct tegra_ehci_platform_data tegra_ehci2_pdata;
+extern struct tegra_ehci_platform_data tegra_ehci3_pdata;
 
 extern struct platform_device tegra_gpio_device;
 extern struct platform_device tegra_pinmux_device;
-- 
1.7.0.4



From michael.hope at linaro.org  Mon Mar 19 16:11:51 2012
From: michael.hope at linaro.org (Michael Hope)
Date: Tue, 20 Mar 2012 09:11:51 +1300
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <4F6760A5.9040506@gmail.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <20120319085503.GL15988@n2100.arm.linux.org.uk> <4F674479.8090101@gmail.com>
 <20120319154123.GP15988@n2100.arm.linux.org.uk> <4F6760A5.9040506@gmail.com>
Message-ID: <CANLjY-mFsDr+cizJWVRxGFpoS2RyGiEZd=UUSeR3_u1DRVpSoQ@mail.gmail.com>

On 20 March 2012 05:36, Rob Herring <robherring2 at gmail.com> wrote:
> On 03/19/2012 10:41 AM, Russell King - ARM Linux wrote:
>> On Mon, Mar 19, 2012 at 09:36:41AM -0500, Rob Herring wrote:
>>> On 03/19/2012 03:55 AM, Russell King - ARM Linux wrote:
>>>> On Mon, Mar 19, 2012 at 04:02:48PM +0900, Boojin Kim wrote:
>>>>> This patch uses LDRD/STRD that loads and stores data as DWORD unit
>>>>> for the copy of 8-words data.
>>>>> It brings better performance than LDRM/STRM that was used originally.
>>>>
>>>> And what about CPUs that don't have ldrd/strd ?
>>>>
>>>
>>> And what about CPUs that do have ldrd/strd but is slower than ldm/stm?
>>> I'm pretty sure that is almost everything currently out there.
>>
>> The double-word load/stores were introduced in ARMv6. ?Some Intel based
>> CPUs prior to this have the support as well. ?Everything else doesn't.
>>
>> So taht's nowhere close to 'almost everything'.
>
> I meant of all platforms that support both instructions, ldm/stm will be
> faster than ldrd/strd on almost all of them AFAIK. I don't think the
> claim about being faster is true for an CortexA9 or anything prior.
> Linaro folks have done some benchmarking in this area and would be
> better to comment.

My understanding is that the A15 does well with LDRD and poorly with
LDM, all other cores do well with LDM, and the A9 at least does poorly
with LDRD.  I don't have numbers at hand to back it up.

FYI, here's ARM's Cortex-A15 LDRD based memcpy implementation:
 http://sourceware.org/ml/newlib/2011/msg00469.html

-- Michael


From arnd at arndb.de  Mon Mar 19 17:09:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 21:09:00 +0000
Subject: [PATCH] ARM: tegra: update main repo and add patchwork
In-Reply-To: <1332092651-25346-1-git-send-email-olof@lixom.net>
References: <1332092651-25346-1-git-send-email-olof@lixom.net>
Message-ID: <201203192109.00862.arnd@arndb.de>

On Sunday 18 March 2012, Olof Johansson wrote:
> Stephen is taking over the main tegra repo, so change the entry to point at his tree on kernel.org
> 
> Also, document the patchwork URL.
> 
> Signed-off-by: Olof Johansson <olof at lixom.net>
> ---
> 
> 
> Arnd, I applied the previous Tegra maintainer patch to next/maintainers
> directly, so this should just go on top of there.

Hi Olof,

I've applied all four trivial pull requests now, the dt ones ended up on the next/dt2
branch and will be sent together with the other late dt patches, which meant that
I also had to pull in the previous tegra/dt patches into both next/dt2 in addition
to next/dt.

	Arnd


From arnd at arndb.de  Mon Mar 19 17:18:09 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 21:18:09 +0000
Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulator for
 first instance
In-Reply-To: <1331080771-30687-1-git-send-email-khilman@ti.com>
References: <1331080771-30687-1-git-send-email-khilman@ti.com>
Message-ID: <201203192118.09286.arnd@arndb.de>

On Wednesday 07 March 2012, Kevin Hilman wrote:
> commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
> regulators) added regulators which are registered during
> gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
> than one instance of the SMSC911x and result in attempting to register
> the same regulator more than once which causes a panic().
> 
> Fix this by only registering the regulator when the platform_data id
> field is zero, indicating its the first instance.
> 
> Cc: Matt Porter <mporter at ti.com>
> Signed-off-by: Kevin Hilman <khilman at ti.com>

It seems that both Olof and I forgot to forward this one to Linus.

If it's ok for you, I'll add it to the fixes branch for v3.4 now
and mark it for backporting to v3.3-stable.

Sorry for the inconvenience.


	Arnd


From stigge at antcom.de  Mon Mar 19 17:18:50 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 19 Mar 2012 22:18:50 +0100
Subject: [PATCH] USB: gadget driver for LPC32xx
Message-ID: <1332191930-2433-1-git-send-email-stigge@antcom.de>

This patch adds a USB gadget driver.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Applies to v3.3


 drivers/usb/gadget/Kconfig        |   10 
 drivers/usb/gadget/Makefile       |    1 
 drivers/usb/gadget/gadget_chips.h |    3 
 drivers/usb/gadget/lpc32xx_udc.c  | 3598 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 3612 insertions(+)

--- linux-2.6.orig/drivers/usb/gadget/Kconfig
+++ linux-2.6/drivers/usb/gadget/Kconfig
@@ -147,6 +147,16 @@ config USB_AT91
 	   dynamically linked module called "at91_udc" and force all
 	   gadget drivers to also be dynamically linked.
 
+config USB_LPC32XX
+	tristate "LPC32XX USB Peripheral Controller"
+	depends on ARCH_LPC32XX
+	help
+	   This option selects the USB device controller in the LPC32xx SoC.
+
+	   Say "y" to link the driver statically, or "m" to build a
+	   dynamically linked module called "lpc32xx_udc" and force all
+	   gadget drivers to also be dynamically linked.
+
 config USB_ATMEL_USBA
 	tristate "Atmel USBA"
 	select USB_GADGET_DUALSPEED
--- linux-2.6.orig/drivers/usb/gadget/Makefile
+++ linux-2.6/drivers/usb/gadget/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_USB_CI13XXX_PCI)	+= ci13xxx
 obj-$(CONFIG_USB_S3C_HSOTG)	+= s3c-hsotg.o
 obj-$(CONFIG_USB_S3C_HSUDC)	+= s3c-hsudc.o
 obj-$(CONFIG_USB_LANGWELL)	+= langwell_udc.o
+obj-$(CONFIG_USB_LPC32XX)	+= lpc32xx_udc.o
 obj-$(CONFIG_USB_EG20T)		+= pch_udc.o
 obj-$(CONFIG_USB_MV_UDC)	+= mv_udc.o
 mv_udc-y			:= mv_udc_core.o
--- linux-2.6.orig/drivers/usb/gadget/gadget_chips.h
+++ linux-2.6/drivers/usb/gadget/gadget_chips.h
@@ -37,6 +37,7 @@
 #define gadget_is_goku(g)		(!strcmp("goku_udc", (g)->name))
 #define gadget_is_imx(g)		(!strcmp("imx_udc", (g)->name))
 #define gadget_is_langwell(g)		(!strcmp("langwell_udc", (g)->name))
+#define gadget_is_lpc32xx(g)		(!strcmp("lpc32xx_udc", (g)->name))
 #define gadget_is_m66592(g)		(!strcmp("m66592_udc", (g)->name))
 #define gadget_is_musbhdrc(g)		(!strcmp("musb-hdrc", (g)->name))
 #define gadget_is_net2272(g)		(!strcmp("net2272", (g)->name))
@@ -118,6 +119,8 @@ static inline int usb_gadget_controller_
 		return 0x31;
 	else if (gadget_is_dwc3(gadget))
 		return 0x32;
+	else if (gadget_is_lpc32xx(gadget))
+		return 0x33;
 
 	return -ENOENT;
 }
--- /dev/null
+++ linux-2.6/drivers/usb/gadget/lpc32xx_udc.c
@@ -0,0 +1,3598 @@
+/*
+ * USB Gadget driver for LPC32xx
+ *
+ * Authors:
+ *    Kevin Wells <kevin.wells at nxp.com>
+ *    Mike James
+ *    Roland Stigge <stigge at antcom.de>
+ *
+ * Copyright (C) 2006 Philips Semiconductors
+ * Copyright (C) 2009 NXP Semiconductors
+ * Copyright (C) 2012 Roland Stigge
+ *
+ * Note: This driver is based on original work done by Mike James for
+ *       the LPC3180.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>
+#include <linux/clk.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/i2c.h>
+#include <linux/kthread.h>
+#include <linux/freezer.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/workqueue.h>
+
+#include <asm/byteorder.h>
+#include <mach/hardware.h>
+#include <linux/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+
+#include <mach/platform.h>
+#include <mach/irqs.h>
+#include <mach/board.h>
+#ifdef CONFIG_USB_GADGET_DEBUG_FILES
+#include <linux/seq_file.h>
+#endif
+
+/*
+ * controller driver data structures
+ */
+
+/* 16 endpoints (not to be confused with 32 hardware endpoints) */
+#define	NUM_ENDPOINTS	16
+
+/*
+ * IRQ indices make reading the code a little easier
+ */
+#define IRQ_USB_LP	0
+#define IRQ_USB_HP	1
+#define IRQ_USB_DEVDMA	2
+#define IRQ_USB_ATX	3
+
+#define EP_OUT 0 /* RX (from host) */
+#define EP_IN 1 /* TX (to host) */
+
+/* Returns the interrupt mask for the selected hardware endpoint */
+#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
+
+#define EP_INT_TYPE 0
+#define EP_ISO_TYPE 1
+#define EP_BLK_TYPE 2
+#define EP_CTL_TYPE 3
+
+/* EP0 states */
+#define WAIT_FOR_SETUP 0 /* Wait for setup packet */
+#define DATA_IN        1 /* Expect dev->host transfer */
+#define DATA_OUT       2 /* Expect host->dev transfer */
+
+/* DD (DMA Descriptor) structure, requires word alignment, this is already
+ * defined in the LPC32XX USB device header file, but this version is slightly
+ * modified to tag some work data with each DMA descriptor. */
+struct lpc32xx_usbd_dd_gad {
+	struct lpc32xx_usbd_dd_gad *dd_next_phy;
+	u32 dd_setup;
+	dma_addr_t dd_buffer_addr;
+	u32 dd_status;
+	dma_addr_t dd_iso_ps_mem_addr;
+	dma_addr_t this_dma;
+	u32 iso_status[6]; /* 5 spare */
+	struct lpc32xx_usbd_dd_gad *dd_next_v;
+};
+
+/*
+ * Logical endpoint structure
+ */
+struct lpc32xx_ep {
+	struct usb_ep		ep;
+	struct list_head	queue;
+	struct lpc32xx_udc	*udc;
+
+	u32			hwep_num_base; /* Physical hardware EP */
+	u32			hwep_num; /* Maps to hardware endpoint */
+	u32			maxpacket;
+	u32			lep;
+
+	u32			is_in:1;
+	u32			req_pending:1;
+	u32			eptype;
+
+	u32                     totalints;
+
+	const struct usb_endpoint_descriptor *desc;
+};
+
+/*
+ * Common UDC structure
+ */
+struct lpc32xx_udc {
+	struct usb_gadget	gadget;
+	struct usb_gadget_driver *driver;
+	struct platform_device	*pdev;
+	struct device		*dev;
+	struct proc_dir_entry	*pde;
+	spinlock_t		lock;
+
+	/* Board and device specific */
+	struct lpc32xx_usbd_cfg	*board;
+	u32			io_p_start;
+	u32			io_p_size;
+	void __iomem		*udp_baseaddr;
+	int			udp_irq[4];
+	struct clk		*usb_pll_clk;
+	struct clk		*usb_slv_clk;
+
+	/* DMA support */
+	dma_addr_t		*udca_v_base;
+	dma_addr_t		udca_p_base;
+	struct dma_pool		*dd_cache;
+
+	/* Common EP and control data */
+	u32			enabled_devints;
+	u32			enabled_hwepints;
+	u32			dev_status;
+	u32			realized_eps;
+
+	/* VBUS detection, pullup, and power flags */
+	u8			vbus;
+	u8			last_vbus;
+	int			pullup;
+	int			poweron;
+
+	/* Work queues related to I2C support */
+	struct work_struct	pullup_wq;
+	struct work_struct	vbus_wq;
+	struct work_struct	power_wq;
+
+	/* USB device peripheral - various */
+	struct lpc32xx_ep	ep[NUM_ENDPOINTS];
+	u32			enabled:1;
+	u32			clocked:1;
+	u32			suspended:1;
+	u32			selfpowered:1;
+	int                     ep0state;
+	atomic_t                enabled_ep_cnt;
+	wait_queue_head_t       ep_disable_wait_queue;
+};
+
+/*
+ * Endpoint request
+ */
+struct lpc32xx_request {
+	struct usb_request	req;
+	struct list_head	queue;
+	struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
+	u32			mapped:1;
+	u32			send_zlp:1;
+};
+
+static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
+{
+	return container_of(g, struct lpc32xx_udc, gadget);
+}
+
+#define ep_dbg(epp, fmt, arg...) \
+	dev_dbg(epp->udc->dev, "%s:%s: " fmt, epp->ep.name, __func__, ## arg)
+#define ep_err(epp, fmt, arg...) \
+	dev_err(epp->udc->dev, "%s:%s: " fmt, epp->ep.name, __func__, ## arg)
+#define ep_info(epp, fmt, arg...) \
+	dev_info(epp->udc->dev, "%s:%s: " fmt, epp->ep.name, __func__, ## arg)
+#define ep_warn(epp, fmt, arg...) \
+	dev_warn(epp->udc->dev, "%s:%s:" fmt, epp->ep.name, __func__, ## arg)
+
+#define UDCA_BUFF_SIZE (128)
+
+#define USB_CTRL		IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64)
+#define USB_CLOCK_MASK		(AHB_M_CLOCK_ON | OTG_CLOCK_ON | \
+				 DEV_CLOCK_ON | I2C_CLOCK_ON)
+
+/* USB_CTRL bit defines */
+#define USB_SLAVE_HCLK_EN	(1 << 24)
+#define USB_HOST_NEED_CLK_EN	(1 << 21)
+#define USB_DEV_NEED_CLK_EN	(1 << 22)
+
+#define USB_OTG_CLK_CTRL	IO_ADDRESS(LPC32XX_USB_BASE + 0xFF4)
+#define USB_OTG_CLK_STAT	IO_ADDRESS(LPC32XX_USB_BASE + 0xFF8)
+
+/* USB_OTG_CLK_CTRL bit defines */
+#define AHB_M_CLOCK_ON		(1 << 4)
+#define OTG_CLOCK_ON		(1 << 3)
+#define I2C_CLOCK_ON		(1 << 2)
+#define DEV_CLOCK_ON		(1 << 1)
+#define HOST_CLOCK_ON		(1 << 0)
+
+#define USB_OTG_STAT_CONTROL	IO_ADDRESS(LPC32XX_USB_BASE + 0x110)
+
+/* USB_OTG_STAT_CONTROL bit defines */
+#define TRANSPARENT_I2C_EN	(1 << 7)
+#define HOST_EN			(1 << 0)
+
+/* ISP1301 USB transceiver I2C registers */
+#define	ISP1301_MODE_CONTROL_1	0x04	/* u8 read, set, +1 clear */
+
+#define	MC1_SPEED_REG		(1 << 0)
+#define	MC1_SUSPEND_REG		(1 << 1)
+#define	MC1_DAT_SE0		(1 << 2)
+#define	MC1_TRANSPARENT		(1 << 3)
+#define	MC1_BDIS_ACON_EN	(1 << 4)
+#define	MC1_OE_INT_EN		(1 << 5)
+#define	MC1_UART_EN		(1 << 6)
+#define	MC1_MASK		0x7f
+
+#define	ISP1301_MODE_CONTROL_2	0x12	/* u8 read, set, +1 clear */
+
+#define	MC2_GLOBAL_PWR_DN	(1 << 0)
+#define	MC2_SPD_SUSP_CTRL	(1 << 1)
+#define	MC2_BI_DI		(1 << 2)
+#define	MC2_TRANSP_BDIR0	(1 << 3)
+#define	MC2_TRANSP_BDIR1	(1 << 4)
+#define	MC2_AUDIO_EN		(1 << 5)
+#define	MC2_PSW_EN		(1 << 6)
+#define	MC2_EN2V7		(1 << 7)
+
+#define	ISP1301_OTG_CONTROL_1	0x06	/* u8 read, set, +1 clear */
+#define	OTG1_DP_PULLUP		(1 << 0)
+#define	OTG1_DM_PULLUP		(1 << 1)
+#define	OTG1_DP_PULLDOWN	(1 << 2)
+#define	OTG1_DM_PULLDOWN	(1 << 3)
+#define	OTG1_ID_PULLDOWN	(1 << 4)
+#define	OTG1_VBUS_DRV		(1 << 5)
+#define	OTG1_VBUS_DISCHRG	(1 << 6)
+#define	OTG1_VBUS_CHRG		(1 << 7)
+#define	ISP1301_OTG_STATUS	0x10	/* u8 readonly */
+#define	OTG_B_SESS_END		(1 << 6)
+#define	OTG_B_SESS_VLD		(1 << 7)
+
+#define INT_CR_INT		(1 << 7)
+#define INT_BDIS_ACON		(1 << 6)
+#define INT_ID_FLOAT		(1 << 5)
+#define INT_DM_HI		(1 << 4)
+#define INT_ID_GND		(1 << 3)
+#define INT_DP_HI		(1 << 2)
+#define INT_SESS_VLD		(1 << 1)
+#define INT_VBUS_VLD		(1 << 0)
+
+#define ISP1301_I2C_ADDR		0x2C
+
+#define ISP1301_I2C_MODE_CONTROL_1	0x4
+#define ISP1301_I2C_MODE_CONTROL_2	0x12
+#define ISP1301_I2C_OTG_CONTROL_1	0x6
+#define ISP1301_I2C_OTG_CONTROL_2	0x10
+#define ISP1301_I2C_INTERRUPT_SOURCE	0x8
+#define ISP1301_I2C_INTERRUPT_LATCH	0xA
+#define ISP1301_I2C_INTERRUPT_FALLING	0xC
+#define ISP1301_I2C_INTERRUPT_RISING	0xE
+#define ISP1301_I2C_REG_CLEAR_ADDR	1
+
+/**********************************************************************
+ * USB device controller register offsets
+ **********************************************************************/
+
+#define USBD_DEVINTST(x)	((x) + 0x200)
+#define USBD_DEVINTEN(x)	((x) + 0x204)
+#define USBD_DEVINTCLR(x)	((x) + 0x208)
+#define USBD_DEVINTSET(x)	((x) + 0x20C)
+#define USBD_CMDCODE(x)		((x) + 0x210)
+#define USBD_CMDDATA(x)		((x) + 0x214)
+#define USBD_RXDATA(x)		((x) + 0x218)
+#define USBD_TXDATA(x)		((x) + 0x21C)
+#define USBD_RXPLEN(x)		((x) + 0x220)
+#define USBD_TXPLEN(x)		((x) + 0x224)
+#define USBD_CTRL(x)		((x) + 0x228)
+#define USBD_DEVINTPRI(x)	((x) + 0x22C)
+#define USBD_EPINTST(x)		((x) + 0x230)
+#define USBD_EPINTEN(x)		((x) + 0x234)
+#define USBD_EPINTCLR(x)	((x) + 0x238)
+#define USBD_EPINTSET(x)	((x) + 0x23C)
+#define USBD_EPINTPRI(x)	((x) + 0x240)
+#define USBD_REEP(x)		((x) + 0x244)
+#define USBD_EPIND(x)		((x) + 0x248)
+#define USBD_EPMAXPSIZE(x)	((x) + 0x24C)
+/* DMA support registers only below */
+/* Set, clear, or get enabled state of the DMA request status. If
+ * enabled, an IN or OUT token will start a DMA transfer for the EP */
+#define USBD_DMARST(x)		((x) + 0x250)
+#define USBD_DMARCLR(x)		((x) + 0x254)
+#define USBD_DMARSET(x)		((x) + 0x258)
+/* DMA UDCA head pointer */
+#define USBD_UDCAH(x)		((x) + 0x280)
+/* EP DMA status, enable, and disable. This is used to specifically
+ * enabled or disable DMA for a specific EP */
+#define USBD_EPDMAST(x)		((x) + 0x284)
+#define USBD_EPDMAEN(x)		((x) + 0x288)
+#define USBD_EPDMADIS(x)	((x) + 0x28C)
+/* DMA master interrupts enable and pending interrupts */
+#define USBD_DMAINTST(x)	((x) + 0x290)
+#define USBD_DMAINTEN(x)	((x) + 0x294)
+/* DMA end of transfer interrupt enable, disable, status */
+#define USBD_EOTINTST(x)	((x) + 0x2A0)
+#define USBD_EOTINTCLR(x)	((x) + 0x2A4)
+#define USBD_EOTINTSET(x)	((x) + 0x2A8)
+/* New DD request interrupt enable, disable, status */
+#define USBD_NDDRTINTST(x)	((x) + 0x2AC)
+#define USBD_NDDRTINTCLR(x)	((x) + 0x2B0)
+#define USBD_NDDRTINTSET(x)	((x) + 0x2B4)
+/* DMA error interrupt enable, disable, status */
+#define USBD_SYSERRTINTST(x)	((x) + 0x2B8)
+#define USBD_SYSERRTINTCLR(x)	((x) + 0x2BC)
+#define USBD_SYSERRTINTSET(x)	((x) + 0x2C0)
+
+/**********************************************************************
+ * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
+ * USBD_DEVINTPRI register definitions
+ **********************************************************************/
+#define USBD_ERR_INT		(1 << 9)
+#define USBD_EP_RLZED		(1 << 8)
+#define USBD_TXENDPKT		(1 << 7)
+#define USBD_RXENDPKT		(1 << 6)
+#define USBD_CDFULL		(1 << 5)
+#define USBD_CCEMPTY		(1 << 4)
+#define USBD_DEV_STAT		(1 << 3)
+#define USBD_EP_SLOW		(1 << 2)
+#define USBD_EP_FAST		(1 << 1)
+#define USBD_FRAME		(1 << 0)
+
+/**********************************************************************
+ * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
+ * USBD_EPINTPRI register definitions
+ **********************************************************************/
+/* End point selection macro (RX) */
+#define USBD_RX_EP_SEL(e)	(1 << ((e) << 1))
+
+/* End point selection macro (TX) */
+#define USBD_TX_EP_SEL(e)	(1 << (((e) << 1) + 1))
+
+/**********************************************************************
+ * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
+ * USBD_EPDMAEN/USBD_EPDMADIS/
+ * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
+ * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
+ * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
+ * register definitions
+ **********************************************************************/
+/* Endpoint selection macro */
+#define USBD_EP_SEL(e)		(1 << (e))
+
+/**********************************************************************
+ * SBD_DMAINTST/USBD_DMAINTEN
+ **********************************************************************/
+#define USBD_SYS_ERR_INT	(1 << 2)
+#define USBD_NEW_DD_INT		(1 << 1)
+#define USBD_EOT_INT		(1 << 0)
+
+/**********************************************************************
+ * USBD_RXPLEN register definitions
+ **********************************************************************/
+#define USBD_PKT_RDY		(1 << 11)
+#define USBD_DV			(1 << 10)
+#define USBD_PK_LEN_MASK	0x3FF
+
+/**********************************************************************
+ * USBD_CTRL register definitions
+ **********************************************************************/
+#define USBD_LOG_ENDPOINT(e)	((e) << 2)
+#define USBD_WR_EN		(1 << 1)
+#define USBD_RD_EN		(1 << 0)
+
+/**********************************************************************
+ * USBD_CMDCODE register definitions
+ **********************************************************************/
+#define USBD_CMD_CODE(c)	((c) << 16)
+#define USBD_CMD_PHASE(p)	((p) << 8)
+
+/**********************************************************************
+ * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
+ **********************************************************************/
+#define USBD_DMAEP(e)		(1 << (e))
+
+/* DD (DMA Descriptor) structure, requires word alignment */
+struct lpc32xx_usbd_dd {
+	u32 *dd_next;
+	u32 dd_setup;
+	u32 dd_buffer_addr;
+	u32 dd_status;
+	u32 dd_iso_ps_mem_addr;
+};
+
+/* dd_setup bit defines */
+#define DD_SETUP_ATLE_DMA_MODE	0x01
+#define DD_SETUP_NEXT_DD_VALID	0x04
+#define DD_SETUP_ISO_EP		0x10
+#define DD_SETUP_PACKETLEN(n)	(((n) & 0x7FF) << 5)
+#define DD_SETUP_DMALENBYTES(n)	(((n) & 0xFFFF) << 16)
+
+/* dd_status bit defines */
+#define DD_STATUS_DD_RETIRED	0x01
+#define DD_STATUS_STS_MASK	0x1E
+#define DD_STATUS_STS_NS	0x00 /* Not serviced */
+#define DD_STATUS_STS_BS	0x02 /* Being serviced */
+#define DD_STATUS_STS_NC	0x04 /* Normal completion */
+#define DD_STATUS_STS_DUR	0x06 /* Data underrun (short packet) */
+#define DD_STATUS_STS_DOR	0x08 /* Data overrun */
+#define DD_STATUS_STS_SE	0x12 /* System error */
+#define DD_STATUS_PKT_VAL	0x20 /* Packet valid */
+#define DD_STATUS_LSB_EX	0x40 /* LS byte extracted (ATLE) */
+#define DD_STATUS_MSB_EX	0x80 /* MS byte extracted (ATLE) */
+#define DD_STATUS_MLEN(n)	(((n) >> 8) & 0x3F)
+#define DD_STATUS_CURDMACNT(n)	(((n) >> 16) & 0xFFFF)
+
+/*
+ *
+ * Protocol engine bits below
+ *
+ */
+/* Device Interrupt Bit Definitions */
+#define FRAME_INT		0x00000001
+#define EP_FAST_INT		0x00000002
+#define EP_SLOW_INT		0x00000004
+#define DEV_STAT_INT		0x00000008
+#define CCEMTY_INT		0x00000010
+#define CDFULL_INT		0x00000020
+#define RxENDPKT_INT		0x00000040
+#define TxENDPKT_INT		0x00000080
+#define EP_RLZED_INT		0x00000100
+#define ERR_INT			0x00000200
+
+/* Rx & Tx Packet Length Definitions */
+#define PKT_LNGTH_MASK		0x000003FF
+#define PKT_DV			0x00000400
+#define PKT_RDY			0x00000800
+
+/* USB Control Definitions */
+#define CTRL_RD_EN		0x00000001
+#define CTRL_WR_EN		0x00000002
+
+/* Command Codes */
+#define CMD_SET_ADDR		0x00D00500
+#define CMD_CFG_DEV		0x00D80500
+#define CMD_SET_MODE		0x00F30500
+#define CMD_RD_FRAME		0x00F50500
+#define DAT_RD_FRAME		0x00F50200
+#define CMD_RD_TEST		0x00FD0500
+#define DAT_RD_TEST		0x00FD0200
+#define CMD_SET_DEV_STAT	0x00FE0500
+#define CMD_GET_DEV_STAT	0x00FE0500
+#define DAT_GET_DEV_STAT	0x00FE0200
+#define CMD_GET_ERR_CODE	0x00FF0500
+#define DAT_GET_ERR_CODE	0x00FF0200
+#define CMD_RD_ERR_STAT		0x00FB0500
+#define DAT_RD_ERR_STAT		0x00FB0200
+#define DAT_WR_BYTE(x)		(0x00000100 | ((x) << 16))
+#define CMD_SEL_EP(x)		(0x00000500 | ((x) << 16))
+#define DAT_SEL_EP(x)		(0x00000200 | ((x) << 16))
+#define CMD_SEL_EP_CLRI(x)	(0x00400500 | ((x) << 16))
+#define DAT_SEL_EP_CLRI(x)	(0x00400200 | ((x) << 16))
+#define CMD_SET_EP_STAT(x)	(0x00400500 | ((x) << 16))
+#define CMD_CLR_BUF		0x00F20500
+#define DAT_CLR_BUF		0x00F20200
+#define CMD_VALID_BUF		0x00FA0500
+
+/* Device Address Register Definitions */
+#define DEV_ADDR_MASK		0x7F
+#define DEV_EN			0x80
+
+/* Device Configure Register Definitions */
+#define CONF_DVICE		0x01
+
+/* Device Mode Register Definitions */
+#define AP_CLK			0x01
+#define INAK_CI			0x02
+#define INAK_CO			0x04
+#define INAK_II			0x08
+#define INAK_IO			0x10
+#define INAK_BI			0x20
+#define INAK_BO			0x40
+
+/* Device Status Register Definitions */
+#define DEV_CON			0x01
+#define DEV_CON_CH		0x02
+#define DEV_SUS			0x04
+#define DEV_SUS_CH		0x08
+#define DEV_RST			0x10
+
+/* Error Code Register Definitions */
+#define ERR_EC_MASK		0x0F
+#define ERR_EA			0x10
+
+/* Error Status Register Definitions */
+#define ERR_PID			0x01
+#define ERR_UEPKT		0x02
+#define ERR_DCRC		0x04
+#define ERR_TIMOUT		0x08
+#define ERR_EOP			0x10
+#define ERR_B_OVRN		0x20
+#define ERR_BTSTF		0x40
+#define ERR_TGL			0x80
+
+/* Endpoint Select Register Definitions */
+#define EP_SEL_F		0x01
+#define EP_SEL_ST		0x02
+#define EP_SEL_STP		0x04
+#define EP_SEL_PO		0x08
+#define EP_SEL_EPN		0x10
+#define EP_SEL_B_1_FULL		0x20
+#define EP_SEL_B_2_FULL		0x40
+
+/* Endpoint Status Register Definitions */
+#define EP_STAT_ST		0x01
+#define EP_STAT_DA		0x20
+#define EP_STAT_RF_MO		0x40
+#define EP_STAT_CND_ST		0x80
+
+/* Clear Buffer Register Definitions */
+#define CLR_BUF_PO		0x01
+
+/* DMA Interrupt Bit Definitions */
+#define EOT_INT			0x01
+#define NDD_REQ_INT		0x02
+#define SYS_ERR_INT		0x04
+
+#define	DRIVER_VERSION	"1.03"
+static const char driver_name[] = "lpc32xx_udc";
+
+static void udc_set_address(struct lpc32xx_udc *udc, u32 addr);
+static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep);
+static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep);
+static int udc_ep0_in_req(struct lpc32xx_udc *udc);
+static int udc_ep0_out_req(struct lpc32xx_udc *udc);
+
+/*
+ *
+ * proc interface support
+ *
+ */
+#ifdef CONFIG_USB_GADGET_DEBUG_FILES
+static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
+static const char debug_filename[] = "driver/udc";
+
+static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
+{
+	struct lpc32xx_request *req;
+
+	seq_printf(s, "\n");
+	seq_printf(s, "%12s, maxpacket %4d %3s",
+			ep->ep.name, ep->ep.maxpacket,
+			ep->is_in ? "in" : "out");
+	seq_printf(s, " type %4s", epnames[ep->eptype]);
+	seq_printf(s, " ints: %12d", ep->totalints);
+
+	if (list_empty(&ep->queue))
+		seq_printf(s, "\t(queue empty)\n");
+	else {
+		list_for_each_entry(req, &ep->queue, queue) {
+			u32 length = req->req.actual;
+
+			seq_printf(s, "\treq %p len %d/%d buf %p\n",
+				   &req->req, length,
+				   req->req.length, req->req.buf);
+		}
+	}
+}
+
+static int proc_udc_show(struct seq_file *s, void *unused)
+{
+	struct lpc32xx_udc *udc = s->private;
+	struct lpc32xx_ep *ep;
+	unsigned long flags;
+
+	seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
+
+	spin_lock_irqsave(&udc->lock, flags);
+
+	seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
+		   udc->vbus ? "present" : "off",
+		   udc->enabled ? (udc->vbus ? "active" : "enabled") :
+		   "disabled",
+		   udc->selfpowered ? "self" : "VBUS",
+		   udc->suspended ? ", suspended" : "",
+		   udc->driver ? udc->driver->driver.name : "(none)");
+
+	if (udc->enabled && udc->vbus) {
+		proc_ep_show(s, &udc->ep[0]);
+		list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
+			if (ep->desc)
+				proc_ep_show(s, ep);
+		}
+	}
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	return 0;
+}
+
+static int proc_udc_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, proc_udc_show, PDE(inode)->data);
+}
+
+static const struct file_operations proc_ops = {
+	.owner		= THIS_MODULE,
+	.open		= proc_udc_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static void create_debug_file(struct lpc32xx_udc *udc)
+{
+	udc->pde = proc_create_data(debug_filename, 0, NULL, &proc_ops, udc);
+}
+
+static void remove_debug_file(struct lpc32xx_udc *udc)
+{
+	if (udc->pde)
+		remove_proc_entry(debug_filename, NULL);
+}
+
+#else
+static inline void create_debug_file(struct lpc32xx_udc *udc) {}
+static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
+#endif
+
+/*
+ *
+ * ISP1301 transceiver support functions
+ *
+ */
+struct i2c_driver isp1301_driver;
+struct i2c_client *isp1301_i2c_client;
+static int isp1301_probe(struct i2c_client *client,
+			 const struct i2c_device_id *i2c_id);
+static int isp1301_remove(struct i2c_client *client);
+
+static const unsigned short normal_i2c[] = {
+	ISP1301_I2C_ADDR, ISP1301_I2C_ADDR + 1, I2C_CLIENT_END
+};
+
+static const struct i2c_device_id isp1301_id[] = {
+	{ "isp1301_pnx", 0 },
+	{ }
+};
+
+struct i2c_driver isp1301_driver = {
+	.driver = {
+		.name = "isp1301_pnx",
+	},
+	.probe = isp1301_probe,
+	.remove = isp1301_remove,
+	.id_table = isp1301_id,
+};
+
+static int isp1301_probe(struct i2c_client *client,
+			 const struct i2c_device_id *i2c_id)
+{
+	return 0;
+}
+
+static int isp1301_remove(struct i2c_client *client)
+{
+	return 0;
+}
+
+static void i2c_write(u8 buf, u8 subaddr)
+{
+	char tmpbuf[2];
+
+	tmpbuf[0] = subaddr;	/* register number */
+	tmpbuf[1] = buf;	/* register data */
+	i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2);
+}
+
+static u16 i2c_read(u8 subaddr)
+{
+	u8 data;
+
+	i2c_master_send(isp1301_i2c_client, &subaddr, 1);
+	i2c_master_recv(isp1301_i2c_client, (u8 *) &data, 1);
+
+	return data;
+}
+
+static u16 i2c_read16(u8 subaddr)
+{
+	u16 data;
+
+	i2c_master_send(isp1301_i2c_client, &subaddr, 1);
+	i2c_master_recv(isp1301_i2c_client, (u8 *) &data, 2);
+
+	return data;
+}
+
+/* Primary initialization sequence for the ISP1301 transceiver */
+static void isp1301_udc_configure(struct lpc32xx_udc *udc)
+{
+	/* LPC32XX only supports DAT_SE0 USB mode */
+	/* This sequence is important */
+
+	/* Disable transparent UART mode first */
+	i2c_write(MC1_UART_EN, (ISP1301_I2C_MODE_CONTROL_1 |
+				ISP1301_I2C_REG_CLEAR_ADDR));
+
+	/* Set full speed and SE0 mode */
+	i2c_write(~0, (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write((MC1_SPEED_REG | MC1_DAT_SE0), ISP1301_I2C_MODE_CONTROL_1);
+
+	/*
+	 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
+	 */
+	i2c_write(~0, (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write((MC2_BI_DI | MC2_SPD_SUSP_CTRL), ISP1301_I2C_MODE_CONTROL_2);
+
+	/* Driver VBUS_DRV high or low depending on board setup */
+	if (udc->board->vbus_drv_pol != 0)
+		i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1);
+	else
+		i2c_write(OTG1_VBUS_DRV, (ISP1301_I2C_OTG_CONTROL_1 |
+					  ISP1301_I2C_REG_CLEAR_ADDR));
+
+	/* Bi-directional mode with suspend control
+	 * Enable both pulldowns for now - the pullup will be enable when VBUS
+	 * is detected */
+	i2c_write(~0, (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+	i2c_write((0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN),
+		  ISP1301_I2C_OTG_CONTROL_1);
+
+	/* Discharge VBUS (just in case) */
+	i2c_write(OTG1_VBUS_DISCHRG, ISP1301_I2C_OTG_CONTROL_1);
+	mdelay(1);
+	i2c_write(OTG1_VBUS_DISCHRG,
+		  (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));
+
+	/* Clear and enable VBUS high edge interrupt */
+	i2c_write(~0, ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(~0, ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(INT_VBUS_VLD, ISP1301_I2C_INTERRUPT_FALLING);
+	i2c_write(~0, ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR);
+	i2c_write(INT_VBUS_VLD, ISP1301_I2C_INTERRUPT_RISING);
+
+	/* Enable usb_need_clk clock after transceiver is initialized */
+	__raw_writel((__raw_readl(USB_CTRL) | (1 << 22)), USB_CTRL);
+
+	dev_dbg(udc->dev,
+		"USB transceiver Vendor ID  : 0x%04x\n", i2c_read16(0x00));
+	dev_dbg(udc->dev,
+		"USB transceiver Product ID : 0x%04x\n", i2c_read16(0x02));
+	dev_dbg(udc->dev,
+		"USB transceiver Version ID : 0x%04x\n", i2c_read16(0x14));
+}
+
+/* Enables or disables the USB device pullup via the ISP1301 transceiver */
+static void isp1301_pullup_set(int en_pullup)
+{
+	if (en_pullup)
+		/* Enable pullup for bus signalling */
+		i2c_write(OTG1_DP_PULLUP, ISP1301_I2C_OTG_CONTROL_1);
+	else
+		/* Enable pullup for bus signalling */
+		i2c_write(OTG1_DP_PULLUP, (ISP1301_I2C_OTG_CONTROL_1 |
+					   ISP1301_I2C_REG_CLEAR_ADDR));
+}
+
+static void pullup_work(struct work_struct *work)
+{
+	struct lpc32xx_udc *udc =
+		container_of(work, struct lpc32xx_udc, pullup_wq);
+
+	isp1301_pullup_set(udc->pullup);
+}
+
+static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
+				  int block)
+{
+	if (en_pullup == udc->pullup)
+		return;
+
+	udc->pullup = en_pullup;
+	if (block)
+		isp1301_pullup_set(en_pullup);
+	else
+		schedule_work(&udc->pullup_wq);
+}
+
+#ifdef CONFIG_PM
+/* Powers up or down the ISP1301 transceiver */
+static void isp1301_set_powerstate(int enable)
+{
+	if (enable != 0)
+		/* Power up ISP1301 - this ISP1301 will automatically wakeup
+		   when VBUS is detected */
+		i2c_write(MC2_GLOBAL_PWR_DN, (ISP1301_I2C_MODE_CONTROL_2 |
+					      ISP1301_I2C_REG_CLEAR_ADDR));
+	else
+		/* Power down ISP1301 */
+		i2c_write(MC2_GLOBAL_PWR_DN, ISP1301_I2C_MODE_CONTROL_2);
+}
+
+static void power_work(struct work_struct *work)
+{
+	struct lpc32xx_udc *udc =
+		container_of(work, struct lpc32xx_udc, power_wq);
+
+	isp1301_set_powerstate(udc->poweron);
+}
+#endif
+
+/*
+ *
+ * USB protocol engine command/data read/write helper functions
+ *
+ */
+/* Issues a single command to the USB device state machine */
+static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
+{
+	u32 pass = 0;
+	int to;
+
+	/* EP may lock on CLRI if this read isn't done */
+	u32 tmp = __raw_readl(USBD_DEVINTST(udc->udp_baseaddr));
+	(void) tmp;
+
+	while (pass == 0) {
+		__raw_writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
+
+		/* Write command code */
+		__raw_writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
+		to = 10000;
+		while (((__raw_readl(USBD_DEVINTST(udc->udp_baseaddr)) &
+			 USBD_CCEMPTY) == 0) && (to > 0)) {
+			to--;
+		}
+
+		if (to > 0)
+			pass = 1;
+	}
+}
+
+/* Issues 2 commands (or command and data) to the USB device state machine */
+static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
+					   u32 data)
+{
+	udc_protocol_cmd_w(udc, cmd);
+	udc_protocol_cmd_w(udc, data);
+}
+
+/* Issues a single command to the USB device state machine and reads
+ * response data */
+static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
+{
+	u32 tmp;
+	int to = 1000;
+
+	/* Write a command and read data from the protocol engine */
+	__raw_writel((USBD_CDFULL | USBD_CCEMPTY),
+		     USBD_DEVINTCLR(udc->udp_baseaddr));
+
+	/* Write command code */
+	udc_protocol_cmd_w(udc, cmd);
+
+	tmp = __raw_readl(USBD_DEVINTST(udc->udp_baseaddr));
+	while ((!(__raw_readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
+	       && (to > 0))
+		to--;
+	if (!to)
+		dev_dbg(udc->dev, "Protocol engine didn't receive response (CDFULL)\n");
+
+	return __raw_readl(USBD_CMDDATA(udc->udp_baseaddr));
+}
+
+/*
+ *
+ * USB device interrupt mask support functions
+ *
+ */
+/* Enable one or more USB device interrupts */
+static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
+{
+	udc->enabled_devints |= devmask;
+	__raw_writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
+}
+
+/* Disable one or more USB device interrupts */
+static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
+{
+	udc->enabled_devints &= ~mask;
+	__raw_writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
+}
+
+/* Clear one or more USB device interrupts */
+static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
+{
+	__raw_writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
+}
+
+/*
+ *
+ * Endpoint interrupt disable/enable functions
+ *
+ */
+/* Enable one or more USB endpoint interrupts */
+static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
+{
+	udc->enabled_hwepints |= (1 << hwep);
+	__raw_writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
+}
+
+/* Disable one or more USB endpoint interrupts */
+static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
+{
+	udc->enabled_hwepints &= ~(1 << hwep);
+	__raw_writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
+}
+
+/* Clear one or more USB endpoint interrupts */
+static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
+{
+	__raw_writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
+}
+
+/* Enable DMA for the HW channel */
+static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
+{
+	__raw_writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
+}
+
+/* Disable DMA for the HW channel */
+static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
+{
+	__raw_writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
+}
+
+/*
+ *
+ * Endpoint realize/unrealize functions
+ *
+ */
+/* Before an endpoint can be used, it needs to be realized
+ * in the USB protocol engine - this realizes the endpoint.
+ * The interrupt (FIFO or DMA) is not enabled with this function */
+static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
+			     u32 maxpacket)
+{
+	int to = 1000;
+
+	__raw_writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
+	__raw_writel(hwep, USBD_EPIND(udc->udp_baseaddr));
+	udc->realized_eps |= (1 << hwep);
+	__raw_writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
+	__raw_writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
+
+	/* Wait until endpoint is realized in hardware */
+	while ((!(__raw_readl(USBD_DEVINTST(udc->udp_baseaddr)) &
+		  USBD_EP_RLZED)) && (to > 0))
+		to--;
+	if (!to)
+		dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
+
+	__raw_writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
+}
+
+/* Unrealize an EP */
+static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
+{
+	udc->realized_eps &= ~(1 << hwep);
+	__raw_writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
+}
+
+/*
+ *
+ * Endpoint support functions
+ *
+ */
+/* Select and clear endpoint interrupt */
+static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
+{
+	udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
+	return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
+}
+
+/* Disables the endpoint in the USB protocol engine */
+static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
+{
+	udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
+				DAT_WR_BYTE(EP_STAT_DA));
+}
+
+/* Stalls the endpoint - endpoint will return STALL */
+static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
+{
+	udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
+				DAT_WR_BYTE(EP_STAT_ST));
+}
+
+/* Clear stall or reset endpoint */
+static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
+{
+	udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
+				DAT_WR_BYTE(0));
+}
+
+/* Select an endpoint for endpoint status, clear, validate */
+static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
+{
+	udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
+}
+
+/*
+ *
+ * Endpoint buffer management functions
+ *
+ */
+/* Clear the current endpoint's buffer */
+static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
+{
+	udc_select_hwep(udc, hwep);
+	udc_protocol_cmd_w(udc, CMD_CLR_BUF);
+}
+
+/* Validate the current endpoint's buffer */
+static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
+{
+	udc_select_hwep(udc, hwep);
+	udc_protocol_cmd_w(udc, CMD_VALID_BUF);
+}
+
+static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
+{
+	/* Clear EP interrupt */
+	uda_clear_hwepint(udc, hwep);
+	return udc_selep_clrint(udc, hwep);
+}
+
+/*
+ *
+ * USB EP DMA support
+ *
+ */
+/* Allocate a DMA Descriptor */
+static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
+{
+	dma_addr_t			dma;
+	struct lpc32xx_usbd_dd_gad	*dd;
+
+	dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc(
+			udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma);
+	if (dd)
+		dd->this_dma = dma;
+
+	return dd;
+}
+
+/* Free a DMA Descriptor */
+static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
+{
+	dma_pool_free(udc->dd_cache, dd, dd->this_dma);
+}
+
+/*
+ *
+ * USB setup and shutdown functions
+ *
+ */
+/* Enables or disables most of the USB system clocks when low power mode is
+ * needed. Clocks are typically started on a connection event, and disabled
+ * when a cable is disconnected */
+#define OTGOFF_CLK_MASK (AHB_M_CLOCK_ON | I2C_CLOCK_ON)
+static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
+{
+	int to = 1000;
+
+	if (enable != 0) {
+		if (udc->clocked)
+			return;
+
+		udc->clocked = 1;
+
+		/* 48MHz PLL up */
+		clk_enable(udc->usb_pll_clk);
+
+		/* Enable the USB device clock */
+		__raw_writel(__raw_readl(USB_CTRL) | USB_DEV_NEED_CLK_EN,
+			     USB_CTRL);
+
+		/* Set to enable all needed USB OTG clocks */
+		__raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL);
+
+		while (((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) !=
+			USB_CLOCK_MASK) && (to > 0))
+			to--;
+		if (!to)
+			dev_dbg(udc->dev, "Cannot enable USB OTG clocking\n");
+	} else {
+		if (!udc->clocked)
+			return;
+
+		udc->clocked = 0;
+
+		/* Never disable the USB_HCLK during normal operation */
+
+		/* 48MHz PLL dpwn */
+		clk_disable(udc->usb_pll_clk);
+
+		/* Enable the USB device clock */
+		__raw_writel(__raw_readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN,
+			     USB_CTRL);
+
+		/* Set to enable all needed USB OTG clocks */
+		__raw_writel(OTGOFF_CLK_MASK, USB_OTG_CLK_CTRL);
+
+		while (((__raw_readl(USB_OTG_CLK_STAT) & OTGOFF_CLK_MASK) !=
+			OTGOFF_CLK_MASK) && (to > 0))
+			to--;
+		if (!to)
+			dev_dbg(udc->dev, "Cannot disable USB OTG clocking\n");
+	}
+}
+
+static void udc_disable(struct lpc32xx_udc *udc)
+{
+	u32 i;
+
+	/* Disable device */
+	udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
+	udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
+
+	/* Disable all device interrupts (including EP0) */
+	uda_disable_devint(udc, 0x3FF);
+
+	/* Disable and reset all endpoint interrupts */
+	for (i = 0; i < 32; i++) {
+		uda_disable_hwepint(udc, i);
+		uda_clear_hwepint(udc, i);
+		udc_disable_hwep(udc, i);
+		udc_unrealize_hwep(udc, i);
+		udc->udca_v_base[i] = 0;
+
+		/* Disable and clear all interrupts and DMA */
+		udc_ep_dma_disable(udc, i);
+		__raw_writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
+		__raw_writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
+		__raw_writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
+		__raw_writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
+	}
+
+	/* Disable DMA interrupts */
+	__raw_writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
+
+	__raw_writel(0, USBD_UDCAH(udc->udp_baseaddr));
+}
+
+static void udc_enable(struct lpc32xx_udc *udc)
+{
+	u32 i;
+	struct lpc32xx_ep *ep = &udc->ep[0];
+
+	/* Start with known state */
+	udc_disable(udc);
+
+	/* Enable device */
+	udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
+
+	/* EP interrupts on high priority, FRAME interrupt on low priority */
+	__raw_writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
+	__raw_writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
+
+	/* Clear any pending device interrupts */
+	__raw_writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
+
+	/* Setup UDCA - not yet used (DMA) */
+	__raw_writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
+
+	/* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
+	for (i = 0; i <= 1; i++) {
+		udc_realize_hwep(udc, i, ep->ep.maxpacket);
+		uda_enable_hwepint(udc, i);
+		udc_select_hwep(udc, i);
+		udc_clrstall_hwep(udc, i);
+		udc_clr_buffer_hwep(udc, i);
+	}
+
+	/* Device interrupt setup */
+	uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
+			       USBD_EP_FAST));
+	uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
+				USBD_EP_FAST));
+
+	/* Set device address to 0 - called twice to force a latch in the USB
+	   engine without the need of a setup packet status closure */
+	udc_set_address(udc, 0);
+	udc_set_address(udc, 0);
+
+	/* Enable master DMA interrupts */
+	__raw_writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
+		     USBD_DMAINTEN(udc->udp_baseaddr));
+
+	udc->dev_status = 0;
+}
+
+/*
+ *
+ * USB device board specific events handled via callbacks
+ *
+ */
+/* Connection change event - notify board function of change */
+static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
+{
+	/* Just notify of a connection change event (optional) */
+	if (udc->board->conn_chgb != NULL)
+		udc->board->conn_chgb(conn);
+}
+
+/* Suspend/resume event - notify board function of change */
+static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
+{
+	/* Just notify of a Suspend/resume change event (optional) */
+	if (udc->board->susp_chgb != NULL)
+		udc->board->susp_chgb(conn);
+
+	if (conn)
+		udc->suspended = 0;
+	else
+		udc->suspended = 1;
+}
+
+/* Remote wakeup enable/disable - notify board function of change */
+static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
+{
+	if (udc->board->rmwk_chgb != NULL)
+		udc->board->rmwk_chgb(udc->dev_status &
+				      (1 << USB_DEVICE_REMOTE_WAKEUP));
+}
+
+/* Reads data from FIFO, adjusts for alignment and data size */
+static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
+{
+	int n, i, bl;
+	u16 *p16;
+	u32 *p32, tmp, cbytes;
+
+	/* Use optimal data transfer method based on source address and size */
+	switch (((u32) data) & 0x3) {
+	case 0: /* 32-bit aligned */
+		p32 = (u32 *) data;
+		cbytes = (bytes & ~0x3);
+
+		/* Copy 32-bit aligned data first */
+		for (n = 0; n < cbytes; n += 4)
+			*p32++ = __raw_readl(USBD_RXDATA(udc->udp_baseaddr));
+
+		/* Handle any remaining bytes */
+		bl = bytes - cbytes;
+		if (bl) {
+			tmp = __raw_readl(USBD_RXDATA(udc->udp_baseaddr));
+			for (n = 0; n < bl; n++)
+				data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
+
+		}
+		break;
+
+	case 1: /* 8-bit aligned */
+	case 3:
+		/* Each byte has to be handled independently */
+		for (n = 0; n < bytes; n += 4) {
+			tmp = __raw_readl(USBD_RXDATA(udc->udp_baseaddr));
+
+			bl = bytes - n;
+			if (bl > 3)
+				bl = 3;
+
+			for (i = 0; i < bl; i++)
+				data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF);
+		}
+		break;
+
+	case 2: /* 16-bit aligned */
+		p16 = (u16 *) data;
+		cbytes = (bytes & ~0x3);
+
+		/* Copy 32-bit sized objects first with 16-bit alignment */
+		for (n = 0; n < cbytes; n += 4) {
+			tmp = __raw_readl(USBD_RXDATA(udc->udp_baseaddr));
+			*p16++ = (u16)(tmp & 0xFFFF);
+			*p16++ = (u16)((tmp >> 16) & 0xFFFF);
+		}
+
+		/* Handle any remaining bytes */
+		bl = bytes - cbytes;
+		if (bl) {
+			tmp = __raw_readl(USBD_RXDATA(udc->udp_baseaddr));
+			for (n = 0; n < bl; n++)
+				data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
+		}
+		break;
+	}
+}
+
+/* Read data from the FIFO for an endpoint. This function is for endpoints (such
+ * as EP0) that don't use DMA. This function should only be called if a packet
+ * is known to be ready to read for the endpoint. Note that the endpoint must
+ * be selected in the protocol engine prior to this call. */
+static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
+			 u32 bytes)
+{
+	u32 tmpv;
+	int to = 1000;
+	u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
+
+	/* Setup read of endpoint */
+	__raw_writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
+
+	/* Wait until packet is ready */
+	while ((((tmpv = __raw_readl(USBD_RXPLEN(udc->udp_baseaddr))) &
+		 PKT_RDY) == 0)	&& (to > 0))
+		to--;
+	if (!to)
+		dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
+
+	/* Mask out count */
+	tmp = tmpv & PKT_LNGTH_MASK;
+	if (bytes < tmp)
+		tmp = bytes;
+
+	if ((tmp > 0) && (data != NULL))
+		udc_pop_fifo(udc, (u8 *) data, tmp);
+
+	__raw_writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
+
+	/* Clear the buffer */
+	udc_clr_buffer_hwep(udc, hwep);
+
+	return tmp;
+}
+
+/* Stuffs data into the FIFO, adjusts for alignment and data size */
+static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
+{
+	int n, i, bl;
+	u16 *p16;
+	u32 *p32, tmp, cbytes;
+
+	/* Use optimal data transfer method based on source address and size */
+	switch (((u32) data) & 0x3) {
+	case 0: /* 32-bit aligned */
+		p32 = (u32 *) data;
+		cbytes = (bytes & ~0x3);
+
+		/* Copy 32-bit aligned data first */
+		for (n = 0; n < cbytes; n += 4)
+			__raw_writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
+
+		/* Handle any remaining bytes */
+		bl = bytes - cbytes;
+		if (bl) {
+			tmp = 0;
+			for (n = 0; n < bl; n++)
+				tmp |= data[cbytes + n] << (n * 8);
+
+			__raw_writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
+		}
+		break;
+
+	case 1: /* 8-bit aligned */
+	case 3:
+		/* Each byte has to be handled independently */
+		for (n = 0; n < bytes; n += 4) {
+			bl = bytes - n;
+			if (bl > 4)
+				bl = 4;
+
+			tmp = 0;
+			for (i = 0; i < bl; i++)
+				tmp |= data[n + i] << (i * 8);
+
+			__raw_writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
+		}
+		break;
+
+	case 2: /* 16-bit aligned */
+		p16 = (u16 *) data;
+		cbytes = (bytes & ~0x3);
+
+		/* Copy 32-bit aligned data first */
+		for (n = 0; n < cbytes; n += 4) {
+			tmp = *p16++ & 0xFFFF;
+			tmp |= (*p16++ & 0xFFFF) << 16;
+			__raw_writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
+		}
+
+		/* Handle any remaining bytes */
+		bl = bytes - cbytes;
+		if (bl) {
+			tmp = 0;
+			for (n = 0; n < bl; n++)
+				tmp |= data[cbytes + n] << (n * 8);
+
+			__raw_writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
+		}
+		break;
+	}
+}
+
+/* Write data to the FIFO for an endpoint. This function is for endpoints (such
+ * as EP0) that don't use DMA. Note that the endpoint must be selected in the
+ * protocol engine prior to this call. */
+static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
+			   u32 bytes)
+{
+	u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
+
+	if ((bytes > 0) && (data == NULL))
+		return;
+
+	/* Setup write of endpoint */
+	__raw_writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
+
+	__raw_writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
+
+	/* Need at least 1 byte to trigger TX */
+	if (bytes == 0)
+		__raw_writel(0, USBD_TXDATA(udc->udp_baseaddr));
+	else
+		udc_stuff_fifo(udc, (u8 *) data, bytes);
+
+	__raw_writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
+
+	udc_val_buffer_hwep(udc, hwep);
+}
+
+/*
+ *
+ * USB protocol high level support functions
+ *
+ */
+/* Set/reset USB device address */
+static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
+{
+	/* Address will be latched at the end of the status phase, or
+	   latched immediately if function is called twice */
+	udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
+				DAT_WR_BYTE(DEV_EN | addr));
+}
+
+/* USB device reset - resets USB to a default state with just EP0
+   enabled */
+static void uda_usb_reset(struct lpc32xx_udc *udc)
+{
+	u32 i = 0;
+	/* Re-init device controller and EP0 */
+	udc_enable(udc);
+	udc->gadget.speed = USB_SPEED_FULL;
+
+	for (i = 1; i < NUM_ENDPOINTS; i++) {
+		struct lpc32xx_ep *ep = &udc->ep[i];
+		ep->req_pending = 0;
+	}
+}
+
+/* Send a ZLP on EP0 */
+static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
+{
+	udc_write_hwep(udc, EP_IN, NULL, 0);
+}
+
+/* Get current frame number */
+static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
+{
+	u16 flo, fhi;
+
+	udc_protocol_cmd_w(udc, CMD_RD_FRAME);
+	flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
+	fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
+
+	return (fhi << 8) | flo;
+}
+
+/* Set the device as configured - enables all endpoints */
+static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
+{
+	udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
+}
+
+/* Set the device as unconfigured - disables all endpoints */
+static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
+{
+	udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
+}
+
+/* reinit == restore initial software state */
+static void udc_reinit(struct lpc32xx_udc *udc)
+{
+	u32 i;
+
+	INIT_LIST_HEAD(&udc->gadget.ep_list);
+	INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
+
+	for (i = 0; i < NUM_ENDPOINTS; i++) {
+		struct lpc32xx_ep *ep = &udc->ep[i];
+
+		if (i != 0)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+		ep->desc = NULL;
+		ep->ep.maxpacket = ep->maxpacket;
+		INIT_LIST_HEAD(&ep->queue);
+		ep->req_pending = 0;
+	}
+
+	udc->ep0state = WAIT_FOR_SETUP;
+}
+
+/* Must be called with lock */
+static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
+{
+	struct lpc32xx_udc *udc = ep->udc;
+
+	list_del_init(&req->queue);
+	if (req->req.status == -EINPROGRESS)
+		req->req.status = status;
+	else
+		status = req->req.status;
+
+	if (ep->lep) {
+		enum dma_data_direction direction;
+
+		if (ep->is_in)
+			direction = DMA_TO_DEVICE;
+		else
+			direction = DMA_FROM_DEVICE;
+
+		if (req->mapped) {
+			dma_unmap_single(ep->udc->gadget.dev.parent,
+					req->req.dma, req->req.length,
+					direction);
+			req->req.dma = 0;
+			req->mapped = 0;
+		} else
+			dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
+						req->req.dma, req->req.length,
+						direction);
+
+		/* Free DDs */
+		udc_dd_free(udc, req->dd_desc_ptr);
+	}
+
+	if (status && status != -ESHUTDOWN)
+		ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
+
+	ep->req_pending = 0;
+	spin_unlock(&udc->lock);
+	req->req.complete(&ep->ep, &req->req);
+	spin_lock(&udc->lock);
+}
+
+/* Must be called with lock */
+static void nuke(struct lpc32xx_ep *ep, int status)
+{
+	struct lpc32xx_request *req;
+
+	while (!list_empty(&ep->queue)) {
+		req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
+		done(ep, req, status);
+	}
+
+	if (ep->desc && status == -ESHUTDOWN) {
+		uda_disable_hwepint(ep->udc, ep->hwep_num);
+		udc_disable_hwep(ep->udc, ep->hwep_num);
+	}
+}
+
+/* Must be called with lock */
+static void stop_activity(struct lpc32xx_udc *udc)
+{
+	struct usb_gadget_driver *driver = udc->driver;
+	int i;
+
+	if (udc->gadget.speed == USB_SPEED_UNKNOWN)
+		driver = NULL;
+
+	udc->gadget.speed = USB_SPEED_UNKNOWN;
+	udc->suspended = 0;
+
+	for (i = 0; i < NUM_ENDPOINTS; i++) {
+		struct lpc32xx_ep *ep = &udc->ep[i];
+		nuke(ep, -ESHUTDOWN);
+	}
+	if (driver) {
+		spin_unlock(&udc->lock);
+		driver->disconnect(&udc->gadget);
+		spin_lock(&udc->lock);
+	}
+
+	isp1301_pullup_enable(udc, 0, 0);
+	udc_disable(udc);
+	udc_reinit(udc);
+}
+
+/*
+ * Activate or kill host pullup
+ * Can be called with or without lock
+ */
+static void pullup(struct lpc32xx_udc *udc, int is_on)
+{
+	if (!udc->clocked)
+		return;
+
+	if (!udc->enabled || !udc->vbus)
+		is_on = 0;
+
+	if (is_on != udc->pullup)
+		isp1301_pullup_enable(udc, is_on, 0);
+}
+
+/* Must be called without lock */
+static int lpc32xx_ep_disable(struct usb_ep *_ep)
+{
+	struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
+	struct lpc32xx_udc *udc = ep->udc;
+	unsigned long	flags;
+
+	if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
+		return -EINVAL;
+	spin_lock_irqsave(&udc->lock, flags);
+
+	nuke(ep, -ESHUTDOWN);
+
+	/* restore the endpoint's pristine config */
+	ep->desc = NULL;
+
+	/* Clear all DMA statuses for this EP */
+	udc_ep_dma_disable(udc, ep->hwep_num);
+	__raw_writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
+	__raw_writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
+	__raw_writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
+	__raw_writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
+
+	/* Remove the DD pointer in the UDCA */
+	udc->udca_v_base[ep->hwep_num] = 0;
+
+	/* Disable and reset endpoint and interrupt */
+	uda_clear_hwepint(udc, ep->hwep_num);
+	udc_unrealize_hwep(udc, ep->hwep_num);
+
+	ep->hwep_num = 0;
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	atomic_dec(&udc->enabled_ep_cnt);
+	wake_up(&udc->ep_disable_wait_queue);
+
+	return 0;
+}
+
+/* Must be called without lock */
+static int lpc32xx_ep_enable(struct usb_ep *_ep,
+			     const struct usb_endpoint_descriptor *desc)
+{
+	struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
+	struct lpc32xx_udc *udc = ep->udc;
+	u16 maxpacket;
+	u32 tmp;
+	unsigned long flags;
+
+	/* Verify EP data */
+	if ((!_ep) || (!ep) || (!desc) || (ep->desc) ||
+	    (desc->bDescriptorType != USB_DT_ENDPOINT)) {
+		dev_dbg(udc->dev, "bad ep or descriptor\n");
+		return -EINVAL;
+	}
+	maxpacket = usb_endpoint_maxp(desc);
+	if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
+		dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
+		return -EINVAL;
+	}
+
+	/* Don't touch EP0 */
+	if (ep->hwep_num_base == 0) {
+		dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
+		return -EINVAL;
+	}
+
+	/* Is driver ready? */
+	if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
+		dev_dbg(udc->dev, "bogus device state\n");
+		return -ESHUTDOWN;
+	}
+
+	tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+	switch (tmp) {
+	case USB_ENDPOINT_XFER_CONTROL:
+		return -EINVAL;
+
+	case USB_ENDPOINT_XFER_INT:
+		if (maxpacket > ep->maxpacket) {
+			dev_dbg(udc->dev,
+				"Bad INT endpoint maxpacket %d\n", maxpacket);
+			return -EINVAL;
+		}
+		break;
+
+	case USB_ENDPOINT_XFER_BULK:
+		switch (maxpacket) {
+		case 8:
+		case 16:
+		case 32:
+		case 64:
+			break;
+
+		default:
+			dev_dbg(udc->dev,
+				"Bad BULK endpoint maxpacket %d\n", maxpacket);
+			return -EINVAL;
+		}
+		break;
+
+	case USB_ENDPOINT_XFER_ISOC:
+		break;
+	}
+	spin_lock_irqsave(&udc->lock, flags);
+
+	/* Initialize endpoint to match the selected descriptor */
+	ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
+	ep->desc = desc;
+	ep->ep.maxpacket = maxpacket;
+
+	/* Map hardware endpoint from base and direction */
+	if (ep->is_in)
+		/* IN endpoints are offset 1 from the OUT endpoint */
+		ep->hwep_num = ep->hwep_num_base + EP_IN;
+	else
+		ep->hwep_num = ep->hwep_num_base;
+
+	ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
+	       ep->hwep_num, maxpacket, (ep->is_in == 1));
+
+	/* Realize the endpoint, interrupt is enabled later when
+	 * buffers are queued, IN EPs will NAK until buffers are ready */
+	udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
+	udc_clr_buffer_hwep(udc, ep->hwep_num);
+	uda_disable_hwepint(udc, ep->hwep_num);
+	udc_clrstall_hwep(udc, ep->hwep_num);
+
+	/* Clear all DMA statuses for this EP */
+	udc_ep_dma_disable(udc, ep->hwep_num);
+	__raw_writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
+	__raw_writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
+	__raw_writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
+	__raw_writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	atomic_inc(&udc->enabled_ep_cnt);
+	return 0;
+}
+
+/*
+ * Allocate a USB request list
+ * Can be called with or without lock
+ */
+static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
+						    gfp_t gfp_flags)
+{
+	struct lpc32xx_request *req;
+
+	req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
+	if (!req)
+		return NULL;
+
+	INIT_LIST_HEAD(&req->queue);
+	return &req->req;
+}
+
+/*
+ * De-allocate a USB request list
+ * Can be called with or without lock
+ */
+static void lpc32xx_ep_free_request(struct usb_ep *_ep,
+				    struct usb_request *_req)
+{
+	struct lpc32xx_request *req;
+
+	req = container_of(_req, struct lpc32xx_request, req);
+	BUG_ON(!list_empty(&req->queue));
+	kfree(req);
+}
+
+/* Must be called without lock */
+static int lpc32xx_ep_queue(struct usb_ep *_ep,
+			    struct usb_request *_req, gfp_t gfp_flags)
+{
+	struct lpc32xx_request *req;
+	struct lpc32xx_ep *ep;
+	struct lpc32xx_udc *udc;
+	unsigned long flags;
+	int status = 0;
+
+	req = container_of(_req, struct lpc32xx_request, req);
+	ep = container_of(_ep, struct lpc32xx_ep, ep);
+
+	if (!_req || !_req->complete || !_req->buf ||
+	    !list_empty(&req->queue))
+		return -EINVAL;
+
+	udc = ep->udc;
+
+	if (!_ep || (!ep->desc && ep->hwep_num_base != 0)) {
+		dev_dbg(udc->dev, "invalid ep\n");
+		return -EINVAL;
+	}
+
+
+	if ((!udc) || (!udc->driver) ||
+	    (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
+		dev_dbg(udc->dev, "invalid device\n");
+		return -EINVAL;
+	}
+
+	if (ep->lep) {
+		enum dma_data_direction direction;
+		struct lpc32xx_usbd_dd_gad *dd;
+
+		/* Map DMA pointer */
+		if (ep->is_in)
+			direction = DMA_TO_DEVICE;
+		else
+			direction = DMA_FROM_DEVICE;
+
+		if (req->req.dma == 0) {
+			req->req.dma = dma_map_single(
+				ep->udc->gadget.dev.parent,
+				req->req.buf, req->req.length, direction);
+			req->mapped = 1;
+		} else {
+			dma_sync_single_for_device(
+				ep->udc->gadget.dev.parent, req->req.dma,
+				req->req.length, direction);
+			req->mapped = 0;
+		}
+
+		/* For the request, build a list of DDs */
+		dd = udc_dd_alloc(udc);
+		if (!dd) {
+			/* Error allocating DD */
+			return -ENOMEM;
+		}
+		req->dd_desc_ptr = dd;
+
+		/* Setup the DMA descriptor */
+		dd->dd_next_phy = dd->dd_next_v = NULL;
+		dd->dd_buffer_addr = req->req.dma;
+		dd->dd_status = 0;
+
+		/* Special handling for ISO EPs */
+		if (ep->eptype == EP_ISO_TYPE) {
+			dd->dd_setup = DD_SETUP_ISO_EP |
+				DD_SETUP_PACKETLEN(0) |
+				DD_SETUP_DMALENBYTES(1);
+			dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
+			if (ep->is_in)
+				dd->iso_status[0] = req->req.length;
+			else
+				dd->iso_status[0] = 0;
+		} else
+			dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
+				DD_SETUP_DMALENBYTES(req->req.length);
+	}
+
+	ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
+	       _req, _req->length, _req->buf, ep->is_in, _req->zero);
+
+	spin_lock_irqsave(&udc->lock, flags);
+
+	_req->status = -EINPROGRESS;
+	_req->actual = 0;
+	req->send_zlp = _req->zero;
+
+	/* Kickstart empty queues */
+	if (list_empty(&ep->queue)) {
+		list_add_tail(&req->queue, &ep->queue);
+
+		if (ep->hwep_num_base == 0) {
+			/* Handle expected data direction */
+			if (ep->is_in) {
+				/* IN packet to host */
+				udc->ep0state = DATA_IN;
+				status = udc_ep0_in_req(udc);
+			} else {
+				/* OUT packet from host */
+				udc->ep0state = DATA_OUT;
+				status = udc_ep0_out_req(udc);
+			}
+		} else if (ep->is_in) {
+			/* IN packet to host and kick off transfer */
+			if (!ep->req_pending)
+				udc_ep_in_req_dma(udc, ep);
+		} else
+			/* OUT packet from host and kick off list */
+			if (!ep->req_pending)
+				udc_ep_out_req_dma(udc, ep);
+	} else
+		list_add_tail(&req->queue, &ep->queue);
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	return (status < 0) ? status : 0;
+}
+
+/* Must be called without lock */
+static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+	struct lpc32xx_ep *ep;
+	struct lpc32xx_request *req;
+	unsigned long flags;
+
+	ep = container_of(_ep, struct lpc32xx_ep, ep);
+	if (!_ep || ep->hwep_num_base == 0)
+		return -EINVAL;
+
+	spin_lock_irqsave(&ep->udc->lock, flags);
+
+	/* make sure it's actually queued on this endpoint */
+	list_for_each_entry(req, &ep->queue, queue) {
+		if (&req->req == _req)
+			break;
+	}
+	if (&req->req != _req) {
+		spin_unlock_irqrestore(&ep->udc->lock, flags);
+		return -EINVAL;
+	}
+
+	done(ep, req, -ECONNRESET);
+
+	spin_unlock_irqrestore(&ep->udc->lock, flags);
+
+	return 0;
+}
+
+/* Must be called without lock */
+static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
+{
+	struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
+	struct lpc32xx_udc *udc = ep->udc;
+	unsigned long flags;
+
+	if ((!ep) || (ep->desc == NULL) || (ep->hwep_num <= 1))
+		return -EINVAL;
+
+	/* Don't halt an IN EP */
+	if (ep->is_in)
+		return -EAGAIN;
+
+	spin_lock_irqsave(&udc->lock, flags);
+
+	if (value == 1)
+		/* stall */
+		udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
+					DAT_WR_BYTE(EP_STAT_ST));
+	else
+		/* End stall */
+		udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
+					DAT_WR_BYTE(0));
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	return 0;
+}
+
+static const struct usb_ep_ops lpc32xx_ep_ops = {
+	.enable		= lpc32xx_ep_enable,
+	.disable	= lpc32xx_ep_disable,
+	.alloc_request	= lpc32xx_ep_alloc_request,
+	.free_request	= lpc32xx_ep_free_request,
+	.queue		= lpc32xx_ep_queue,
+	.dequeue	= lpc32xx_ep_dequeue,
+	.set_halt	= lpc32xx_ep_set_halt,
+};
+
+/* Setup up a IN request for DMA transfer - this consists of determining the
+ * list of DMA addresses for the transfer, allocating DMA Descriptors,
+ * installing the DD into the UDCA, and then enabling the DMA for that EP */
+static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
+{
+	struct lpc32xx_request *req;
+	u32 hwep = ep->hwep_num;
+
+	ep->req_pending = 1;
+
+	/* There will always be a request waiting here */
+	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
+
+	/* Place the DD Descriptor into the UDCA */
+	udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
+
+	/* Enable DMA and interrupt for the HW EP */
+	udc_ep_dma_enable(udc, hwep);
+
+	/* Clear ZLP if last packet is not of MAXP size */
+	if (req->req.length % ep->ep.maxpacket)
+		req->send_zlp = 0;
+
+	return 0;
+}
+
+/* Setup up a OUT request for DMA transfer - this consists of determining the
+ * list of DMA addresses for the transfer, allocating DMA Descriptors,
+ * installing the DD into the UDCA, and then enabling the DMA for that EP */
+static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
+{
+	struct lpc32xx_request *req;
+	u32 hwep = ep->hwep_num;
+
+	ep->req_pending = 1;
+
+	/* There will always be a request waiting here */
+	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
+
+	/* Place the DD Descriptor into the UDCA */
+	udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
+
+	/* Enable DMA and interrupt for the HW EP */
+	udc_ep_dma_enable(udc, hwep);
+	return 0;
+}
+
+/* Send a ZLP on a non-0 IN EP */
+void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
+{
+	/* Clear EP status */
+	udc_clearep_getsts(udc, ep->hwep_num);
+
+	/* Send ZLP via FIFO mechanism */
+	udc_write_hwep(udc, ep->hwep_num, NULL, 0);
+}
+
+/*
+ * Handle EP completion for ZLP
+ * This function will only be called when a delayed ZLP needs to be sent out
+ * after a DMA transfer has filled both buffers.
+ */
+void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
+{
+	u32 epstatus;
+	struct lpc32xx_request *req;
+
+	if (ep->hwep_num <= 0)
+		return;
+
+	uda_clear_hwepint(udc, ep->hwep_num);
+
+	/* If this interrupt isn't enabled, return now */
+	if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
+		return;
+
+	/* Get endpoint status */
+	epstatus = udc_clearep_getsts(udc, ep->hwep_num);
+
+	/*
+	 * This should never happen, but protect against writing to the
+	 * buffer when full.
+	 */
+	if (epstatus & EP_SEL_F)
+		return;
+
+	if (ep->is_in) {
+		udc_send_in_zlp(udc, ep);
+		uda_disable_hwepint(udc, ep->hwep_num);
+	} else
+		return;
+
+	/* If there isn't a request waiting, something went wrong */
+	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
+	if (req) {
+		done(ep, req, 0);
+
+		/* Start another request if ready */
+		if (!list_empty(&ep->queue)) {
+			if (ep->is_in)
+				udc_ep_in_req_dma(udc, ep);
+			else
+				udc_ep_out_req_dma(udc, ep);
+		} else
+			ep->req_pending = 0;
+	}
+}
+
+
+/* DMA end of transfer completion */
+static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
+{
+	u32 status, epstatus;
+	struct lpc32xx_request *req;
+	struct lpc32xx_usbd_dd_gad *dd;
+
+#ifdef CONFIG_USB_GADGET_DEBUG_FILES
+	ep->totalints++;
+#endif
+
+	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
+	if (!req) {
+		ep_err(ep, "DMA interrupt on no req!\n");
+		return;
+	}
+	dd = req->dd_desc_ptr;
+
+	/* DMA descriptor should always be retired for this call */
+	if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
+		ep_warn(ep, "DMA descriptor did not retire\n");
+
+	/* Disable DMA */
+	udc_ep_dma_disable(udc, ep->hwep_num);
+	__raw_writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
+	__raw_writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
+
+	/* System error? */
+	if (__raw_readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
+	    (1 << ep->hwep_num)) {
+		__raw_writel((1 << ep->hwep_num),
+			     USBD_SYSERRTINTCLR(udc->udp_baseaddr));
+		ep_err(ep, "AHB critical error!\n");
+		ep->req_pending = 0;
+
+		/* The error could have occurred on a packet of a multipacket
+		 * transfer, so recovering the transfer is not possible. Close
+		 * the request with an error */
+		done(ep, req, -ECONNABORTED);
+		return;
+	}
+
+	/* Handle the current DD's status */
+	status = dd->dd_status;
+	switch (status & DD_STATUS_STS_MASK) {
+	case DD_STATUS_STS_NS:
+		/* DD not serviced? This shouldn't happen! */
+		ep->req_pending = 0;
+		ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
+		       status);
+
+		done(ep, req, -ECONNABORTED);
+		return;
+
+	case DD_STATUS_STS_BS:
+		/* Interrupt only fires on EOT - This shouldn't happen! */
+		ep->req_pending = 0;
+		ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
+		       status);
+		done(ep, req, -ECONNABORTED);
+		return;
+
+	case DD_STATUS_STS_NC:
+	case DD_STATUS_STS_DUR:
+		/* Really just a short packet, not an underrun */
+		/* This is a good status and what we expect */
+		break;
+
+	default:
+		/* Data overrun, system error, or unknown */
+		ep->req_pending = 0;
+		ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
+		       status);
+		done(ep, req, -ECONNABORTED);
+		return;
+	}
+
+	/* ISO endpoints are handled differently */
+	if (ep->eptype == EP_ISO_TYPE) {
+		if (ep->is_in)
+			req->req.actual = req->req.length;
+		else
+			req->req.actual = dd->iso_status[0] & 0xFFFF;
+	} else
+		req->req.actual += DD_STATUS_CURDMACNT(status);
+
+	/* Send a ZLP if necessary. This will be done for non-int
+	 * packets which have a size that is a divisor of MAXP */
+	if (req->send_zlp) {
+		/*
+		 * If at least 1 buffer is available, send the ZLP now.
+		 * Otherwise, the ZLP send needs to be deferred until a
+		 * buffer is available.
+		 */
+		if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
+			udc_clearep_getsts(udc, ep->hwep_num);
+			uda_enable_hwepint(udc, ep->hwep_num);
+			epstatus = udc_clearep_getsts(udc, ep->hwep_num);
+
+			/* Let the EP interrupt handle the ZLP */
+			return;
+		} else
+			udc_send_in_zlp(udc, ep);
+	}
+
+	/* Transfer request is complete */
+	done(ep, req, 0);
+
+	/* Start another request if ready */
+	udc_clearep_getsts(udc, ep->hwep_num);
+	if (!list_empty((&ep->queue))) {
+		if (ep->is_in)
+			udc_ep_in_req_dma(udc, ep);
+		else
+			udc_ep_out_req_dma(udc, ep);
+	} else
+		ep->req_pending = 0;
+
+}
+
+/*
+ *
+ * Endpoint 0 functions
+ *
+ */
+static void udc_handle_dev(struct lpc32xx_udc *udc)
+{
+	u32 tmp;
+
+	udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
+	tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
+
+	if (tmp & DEV_RST)
+		uda_usb_reset(udc);
+	else if (tmp & DEV_CON_CH)
+		uda_power_event(udc, (tmp & DEV_CON));
+	else if (tmp & DEV_SUS_CH) {
+		if (tmp & DEV_SUS) {
+			if (udc->vbus == 0)
+				stop_activity(udc);
+			else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
+				 udc->driver) {
+				/* Power down transceiver */
+				udc->poweron = 0;
+				schedule_work(&udc->pullup_wq);
+				uda_resm_susp_event(udc, 1);
+			}
+		} else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
+			   udc->driver && udc->vbus) {
+			uda_resm_susp_event(udc, 0);
+			/* Power up transceiver */
+			udc->poweron = 1;
+			schedule_work(&udc->pullup_wq);
+		}
+	}
+}
+
+/* IN endpoint 0 transfer */
+static int udc_ep0_in_req(struct lpc32xx_udc *udc)
+{
+	struct lpc32xx_request *req;
+	struct lpc32xx_ep *ep0 = &udc->ep[0];
+	u32 tsend, ts = 0;
+
+	if (list_empty(&ep0->queue))
+		/* Nothing to send */
+		return 0;
+	else
+		req = list_entry(ep0->queue.next, struct lpc32xx_request,
+				 queue);
+
+	tsend = ts = req->req.length - req->req.actual;
+	if (ts == 0) {
+		/* Send a ZLP */
+		udc_ep0_send_zlp(udc);
+		done(ep0, req, 0);
+		return 1;
+	} else if (ts > ep0->ep.maxpacket)
+		ts = ep0->ep.maxpacket; /* Just send what we can */
+
+	/* Write data to the EP0 FIFO and start transfer */
+	udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
+
+	/* Increment data pointer */
+	req->req.actual += ts;
+
+	if (tsend >= ep0->ep.maxpacket)
+		return 0; /* Stay in data transfer state */
+
+	/* Transfer request is complete */
+	udc->ep0state = WAIT_FOR_SETUP;
+	done(ep0, req, 0);
+	return 1;
+}
+
+/* OUT endpoint 0 transfer */
+static int udc_ep0_out_req(struct lpc32xx_udc *udc)
+{
+	struct lpc32xx_request *req;
+	struct lpc32xx_ep *ep0 = &udc->ep[0];
+	u32 tr, bufferspace;
+
+	if (list_empty(&ep0->queue))
+		return 0;
+	else
+		req = list_entry(ep0->queue.next, struct lpc32xx_request,
+				 queue);
+
+	if (req) {
+		if (req->req.length == 0) {
+			/* Just dequeue request */
+			done(ep0, req, 0);
+			udc->ep0state = WAIT_FOR_SETUP;
+			return 1;
+		}
+
+		/* Get data from FIFO */
+		bufferspace = req->req.length - req->req.actual;
+		if (bufferspace > ep0->ep.maxpacket)
+			bufferspace = ep0->ep.maxpacket;
+
+		/* Copy data to buffer */
+		prefetchw(req->req.buf + req->req.actual);
+		tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
+				   bufferspace);
+		req->req.actual += bufferspace;
+
+		if (tr < ep0->ep.maxpacket) {
+			/* This is the last packet */
+			done(ep0, req, 0);
+			udc->ep0state = WAIT_FOR_SETUP;
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
+{
+	struct lpc32xx_ep *ep;
+	u32 ep0buff = 0, tmp;
+
+	switch (reqtype & USB_RECIP_MASK) {
+	case USB_RECIP_INTERFACE:
+		break; /* Not supported */
+
+	case USB_RECIP_DEVICE:
+		ep0buff = (udc->selfpowered << USB_DEVICE_SELF_POWERED);
+		if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
+			ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
+		break;
+
+	case USB_RECIP_ENDPOINT:
+		tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
+		ep = &udc->ep[tmp];
+		if ((tmp == 0) || (tmp >= NUM_ENDPOINTS) || (tmp && !ep->desc))
+			return -EOPNOTSUPP;
+
+		if (wIndex & USB_DIR_IN) {
+			if (!ep->is_in)
+				return -EOPNOTSUPP; /* Something's wrong */
+		} else if (ep->is_in)
+			return -EOPNOTSUPP; /* Not an IN endpoint */
+
+		/* Get status of the endpoint */
+		udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
+		tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
+
+		if (tmp & EP_SEL_ST)
+			ep0buff = (1 << USB_ENDPOINT_HALT);
+		else
+			ep0buff = 0;
+		break;
+
+	default:
+		break;
+	}
+
+	/* Return data */
+	udc_write_hwep(udc, EP_IN, &ep0buff, 2);
+
+	return 0;
+}
+
+static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
+{
+	struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
+	struct usb_ctrlrequest ctrlpkt;
+	int i, bytes;
+	u16 wIndex, wValue, wLength, reqtype, req, tmp;
+
+	/* Nuke previous transfers */
+	nuke(ep0, -EPROTO);
+
+	/* Get setup packet */
+	bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
+	if (bytes != 8) {
+		ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
+			bytes);
+		return;
+	}
+
+	/* Native endianness */
+	wIndex = le16_to_cpu(ctrlpkt.wIndex);
+	wValue = le16_to_cpu(ctrlpkt.wValue);
+	wLength = le16_to_cpu(ctrlpkt.wLength);
+	reqtype = le16_to_cpu(ctrlpkt.bRequestType);
+
+	/* Set direction of EP0 */
+	if (likely(reqtype & USB_DIR_IN))
+		ep0->is_in = 1;
+	else
+		ep0->is_in = 0;
+
+	/* Handle SETUP packet */
+	req = le16_to_cpu(ctrlpkt.bRequest);
+	switch (req) {
+	case USB_REQ_CLEAR_FEATURE:
+	case USB_REQ_SET_FEATURE:
+		switch (reqtype) {
+		case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
+			if (wValue != USB_DEVICE_REMOTE_WAKEUP)
+				goto stall; /* Nothing else handled */
+
+			/* Tell board about event */
+			if (req == USB_REQ_CLEAR_FEATURE)
+				udc->dev_status &=
+					~(1 << USB_DEVICE_REMOTE_WAKEUP);
+			else
+				udc->dev_status |=
+					(1 << USB_DEVICE_REMOTE_WAKEUP);
+			uda_remwkp_cgh(udc);
+			goto zlp_send;
+
+		case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
+			tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
+			if ((wValue != USB_ENDPOINT_HALT) ||
+			    (tmp >= NUM_ENDPOINTS))
+				break;
+
+			/* Find hardware endpoint from logical endpoint */
+			ep = &udc->ep[tmp];
+			tmp = ep->hwep_num;
+			if (tmp == 0)
+				break;
+
+			if (req == USB_REQ_SET_FEATURE)
+				udc_stall_hwep(udc, tmp);
+			else
+				udc_clrstall_hwep(udc, tmp);
+
+			goto zlp_send;
+
+		default:
+			break;
+		}
+
+
+	case USB_REQ_SET_ADDRESS:
+		if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
+			udc_set_address(udc, wValue);
+			goto zlp_send;
+		}
+		break;
+
+	case USB_REQ_GET_STATUS:
+		udc_get_status(udc, reqtype, wIndex);
+		return;
+
+	default:
+		break; /* Let GadgetFS handle the descriptor instead */
+	}
+
+	if (likely(udc->driver)) {
+		/* device-2-host (IN) or no data setup command, process
+		 * immediately */
+		spin_unlock(&udc->lock);
+		i = udc->driver->setup(&udc->gadget, &ctrlpkt);
+
+		spin_lock(&udc->lock);
+		if (req == USB_REQ_SET_CONFIGURATION) {
+			/* Configuration is set after endpoints are realized */
+			if (wValue) {
+				/* Set configuration */
+				udc_set_device_configured(udc);
+
+				udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
+							DAT_WR_BYTE(AP_CLK |
+							INAK_BI | INAK_II));
+			} else {
+				/* Clear configuration */
+				udc_set_device_unconfigured(udc);
+
+				/* Disable NAK interrupts */
+				udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
+							DAT_WR_BYTE(AP_CLK));
+			}
+		}
+
+		if (i < 0) {
+			/* setup processing failed, force stall */
+			dev_err(udc->dev,
+				"req %02x.%02x protocol STALL; stat %d\n",
+				reqtype, req, i);
+			udc->ep0state = WAIT_FOR_SETUP;
+			goto stall;
+		}
+	}
+
+	if (!ep0->is_in)
+		udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
+
+	return;
+
+stall:
+	udc_stall_hwep(udc, EP_IN);
+	return;
+
+zlp_send:
+	udc_ep0_send_zlp(udc);
+	return;
+}
+
+/* IN endpoint 0 transfer */
+static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
+{
+	struct lpc32xx_ep *ep0 = &udc->ep[0];
+	u32 epstatus;
+
+	/* Clear EP interrupt */
+	epstatus = udc_clearep_getsts(udc, EP_IN);
+
+#ifdef CONFIG_USB_GADGET_DEBUG_FILES
+	ep0->totalints++;
+#endif
+
+	/* Stalled? Clear stall and reset buffers */
+	if (epstatus & EP_SEL_ST) {
+		udc_clrstall_hwep(udc, EP_IN);
+		nuke(ep0, -ECONNABORTED);
+		udc->ep0state = WAIT_FOR_SETUP;
+		return;
+	}
+
+	/* Is a buffer available? */
+	if (!(epstatus & EP_SEL_F)) {
+		/* Handle based on current state */
+		if (udc->ep0state == DATA_IN)
+			udc_ep0_in_req(udc);
+		else {
+			/* Unknown state for EP0 oe end of DATA IN phase */
+			nuke(ep0, -ECONNABORTED);
+			udc->ep0state = WAIT_FOR_SETUP;
+		}
+	}
+}
+
+/* OUT endpoint 0 transfer */
+static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
+{
+	struct lpc32xx_ep *ep0 = &udc->ep[0];
+	u32 epstatus;
+
+	/* Clear EP interrupt */
+	epstatus = udc_clearep_getsts(udc, EP_OUT);
+
+
+#ifdef CONFIG_USB_GADGET_DEBUG_FILES
+	ep0->totalints++;
+#endif
+
+	/* Stalled? */
+	if (epstatus & EP_SEL_ST) {
+		udc_clrstall_hwep(udc, EP_OUT);
+		nuke(ep0, -ECONNABORTED);
+		udc->ep0state = WAIT_FOR_SETUP;
+		return;
+	}
+
+	/* A NAK may occur if a packet couldn't be received yet */
+	if (epstatus & EP_SEL_EPN)
+		return;
+	/* Setup packet incoming? */
+	if (epstatus & EP_SEL_STP) {
+		nuke(ep0, 0);
+		udc->ep0state = WAIT_FOR_SETUP;
+	}
+
+	/* Data available? */
+	if (epstatus & EP_SEL_F)
+		/* Handle based on current state */
+		switch (udc->ep0state) {
+		case WAIT_FOR_SETUP:
+			udc_handle_ep0_setup(udc);
+			break;
+
+		case DATA_OUT:
+			udc_ep0_out_req(udc);
+			break;
+
+		default:
+			/* Unknown state for EP0 */
+			nuke(ep0, -ECONNABORTED);
+			udc->ep0state = WAIT_FOR_SETUP;
+		}
+}
+
+/* Must be called without lock */
+static int lpc32xx_get_frame(struct usb_gadget *gadget)
+{
+	int frame;
+	unsigned long flags;
+	struct lpc32xx_udc *udc = to_udc(gadget);
+
+	if (!udc->clocked)
+		return -EINVAL;
+
+	spin_lock_irqsave(&udc->lock, flags);
+
+	frame = (int) udc_get_current_frame(udc);
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	return frame;
+}
+
+static int lpc32xx_wakeup(struct usb_gadget *gadget)
+{
+	return -ENOTSUPP;
+}
+
+static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
+{
+	struct lpc32xx_udc *udc = to_udc(gadget);
+
+	/* Always self-powered */
+	udc->selfpowered = (is_on != 0);
+
+	return 0;
+}
+
+/*
+ * vbus is here!  turn everything on that's ready
+ * Must be called without lock
+ */
+static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
+{
+	unsigned long flags;
+	struct lpc32xx_udc *udc = to_udc(gadget);
+
+	spin_lock_irqsave(&udc->lock, flags);
+
+	/* Doesn't need lock */
+	if (udc->driver) {
+		udc_clk_set(udc, 1);
+		udc_enable(udc);
+		pullup(udc, is_active);
+	} else {
+		stop_activity(udc);
+		pullup(udc, 0);
+
+		spin_unlock_irqrestore(&udc->lock, flags);
+		/*
+		 *  Wait for all the endpoints to disable,
+		 *  before disabling clocks. Don't wait if
+		 *  endpoints are not enabled.
+		 */
+		if (atomic_read(&udc->enabled_ep_cnt))
+			wait_event_interruptible(udc->ep_disable_wait_queue,
+				 (atomic_read(&udc->enabled_ep_cnt) == 0));
+
+		spin_lock_irqsave(&udc->lock, flags);
+
+		udc_clk_set(udc, 0);
+	}
+
+	spin_unlock_irqrestore(&udc->lock, flags);
+
+	return 0;
+}
+
+/* Can be called with or without lock */
+static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
+{
+	struct lpc32xx_udc *udc = to_udc(gadget);
+
+	/* Doesn't need lock */
+	pullup(udc, is_on);
+
+	return 0;
+}
+
+static int lpc32xx_start(struct usb_gadget_driver *driver,
+			 int (*bind)(struct usb_gadget *));
+static int lpc32xx_stop(struct usb_gadget_driver *driver);
+
+static const struct usb_gadget_ops lpc32xx_udc_ops = {
+	.get_frame		= lpc32xx_get_frame,
+	.wakeup			= lpc32xx_wakeup,
+	.set_selfpowered	= lpc32xx_set_selfpowered,
+	.vbus_session		= lpc32xx_vbus_session,
+	.pullup			= lpc32xx_pullup,
+	.start			= lpc32xx_start,
+	.stop			= lpc32xx_stop,
+};
+
+static void nop_release(struct device *dev)
+{
+	/* nothing to free */
+}
+
+static struct lpc32xx_udc controller = {
+	.gadget = {
+		.ops	= &lpc32xx_udc_ops,
+		.ep0	= &controller.ep[0].ep,
+		.name	= driver_name,
+		.dev	= {
+			.init_name = "gadget",
+			.release = nop_release,
+		}
+	},
+	.ep[0] = {
+		.ep = {
+			.name	= "ep0",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 64,
+		.hwep_num_base	= 0,
+		.hwep_num	= 0, /* Can be 0 or 1, has special handling */
+		.lep		= 0,
+		.eptype		= EP_CTL_TYPE,
+	},
+	.ep[1] = {
+		.ep = {
+			.name	= "ep1-int",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 64,
+		.hwep_num_base	= 2,
+		.hwep_num	= 0, /* 2 or 3, will be set later */
+		.lep		= 1,
+		.eptype		= EP_INT_TYPE,
+	},
+	.ep[2] = {
+		.ep = {
+			.name	= "ep2-bulk",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 64,
+		.hwep_num_base	= 4,
+		.hwep_num	= 0, /* 4 or 5, will be set later */
+		.lep		= 2,
+		.eptype		= EP_BLK_TYPE,
+	},
+	.ep[3] = {
+		.ep = {
+			.name	= "ep3-iso",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 1023,
+		.hwep_num_base	= 6,
+		.hwep_num	= 0, /* 6 or 7, will be set later */
+		.lep		= 3,
+		.eptype		= EP_ISO_TYPE,
+	},
+	.ep[4] = {
+		.ep = {
+			.name	= "ep4-int",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 64,
+		.hwep_num_base	= 8,
+		.hwep_num	= 0, /* 8 or 9, will be set later */
+		.lep		= 4,
+		.eptype		= EP_INT_TYPE,
+	},
+	.ep[5] = {
+		.ep = {
+			.name	= "ep5-bulk",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 64,
+		.hwep_num_base	= 10,
+		.hwep_num	= 0, /* 10 or 11, will be set later */
+		.lep		= 5,
+		.eptype		= EP_BLK_TYPE,
+	},
+	.ep[6] = {
+		.ep = {
+			.name	= "ep6-iso",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 1023,
+		.hwep_num_base	= 12,
+		.hwep_num	= 0, /* 12 or 13, will be set later */
+		.lep		= 6,
+		.eptype		= EP_ISO_TYPE,
+	},
+	.ep[7] = {
+		.ep = {
+			.name	= "ep7-int",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 64,
+		.hwep_num_base	= 14,
+		.hwep_num	= 0,
+		.lep		= 7,
+		.eptype		= EP_INT_TYPE,
+	},
+	.ep[8] = {
+		.ep = {
+			.name	= "ep8-bulk",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 64,
+		.hwep_num_base	= 16,
+		.hwep_num	= 0,
+		.lep		= 8,
+		.eptype		= EP_BLK_TYPE,
+	},
+	.ep[9] = {
+		.ep = {
+			.name	= "ep9-iso",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 1023,
+		.hwep_num_base	= 18,
+		.hwep_num	= 0,
+		.lep		= 9,
+		.eptype		= EP_ISO_TYPE,
+	},
+	.ep[10] = {
+		.ep = {
+			.name	= "ep10-int",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 64,
+		.hwep_num_base	= 20,
+		.hwep_num	= 0,
+		.lep		= 10,
+		.eptype		= EP_INT_TYPE,
+	},
+	.ep[11] = {
+		.ep = {
+			.name	= "ep11-bulk",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 64,
+		.hwep_num_base	= 22,
+		.hwep_num	= 0,
+		.lep		= 11,
+		.eptype		= EP_BLK_TYPE,
+	},
+	.ep[12] = {
+		.ep = {
+			.name	= "ep12-iso",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 1023,
+		.hwep_num_base	= 24,
+		.hwep_num	= 0,
+		.lep		= 12,
+		.eptype		= EP_ISO_TYPE,
+	},
+	.ep[13] = {
+		.ep = {
+			.name	= "ep13-int",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 64,
+		.hwep_num_base	= 26,
+		.hwep_num	= 0,
+		.lep		= 13,
+		.eptype		= EP_INT_TYPE,
+	},
+	.ep[14] = {
+		.ep = {
+			.name	= "ep14-bulk",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 64,
+		.hwep_num_base	= 28,
+		.hwep_num	= 0,
+		.lep		= 14,
+		.eptype		= EP_BLK_TYPE,
+	},
+	.ep[15] = {
+		.ep = {
+			.name	= "ep15-bulk",
+			.ops	= &lpc32xx_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= 1023,
+		.hwep_num_base	= 30,
+		.hwep_num	= 0,
+		.lep		= 15,
+		.eptype		= EP_BLK_TYPE,
+	},
+};
+
+/* ISO and status interrupts */
+static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
+{
+	u32 tmp, devstat;
+	struct lpc32xx_udc *udc = _udc;
+
+	spin_lock(&udc->lock);
+
+	/* Read the device status register */
+	devstat = __raw_readl(USBD_DEVINTST(udc->udp_baseaddr));
+
+	devstat &= ~USBD_EP_FAST;
+	__raw_writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
+	devstat = devstat & udc->enabled_devints;
+
+	/* Device specific handling needed? */
+	if (devstat & USBD_DEV_STAT)
+		udc_handle_dev(udc);
+
+	/* Start of frame? (devstat & FRAME_INT):
+	 * The frame interrupt isn't really needed for ISO support,
+	 * as the driver will queue the necessary packets */
+
+	/* Error? */
+	if (devstat & ERR_INT) {
+		/* All types of errors, from cable removal during transfer to
+		 * misc protocol and bit errors. These are mostly for just info,
+		 * as the USB hardware will work around these. If these errors
+		 * happen alot, something is wrong. */
+		udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
+		tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
+		dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
+	}
+
+	spin_unlock(&udc->lock);
+
+	return IRQ_HANDLED;
+}
+
+/* EP interrupts */
+static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
+{
+	u32 tmp;
+	struct lpc32xx_udc *udc = _udc;
+
+	spin_lock(&udc->lock);
+
+	/* Read the device status register */
+	__raw_writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
+
+	/* Endpoints */
+	tmp = __raw_readl(USBD_EPINTST(udc->udp_baseaddr));
+
+	/* Special handling for EP0 */
+	if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
+		/* Handle EP0 IN */
+		if (tmp & (EP_MASK_SEL(0, EP_IN)))
+			udc_handle_ep0_in(udc);
+
+		/* Handle EP0 OUT */
+		if (tmp & (EP_MASK_SEL(0, EP_OUT)))
+			udc_handle_ep0_out(udc);
+	}
+
+	/* All other EPs */
+	if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
+		int i;
+
+		/* Handle other EP interrupts */
+		for (i = 1; i < NUM_ENDPOINTS; i++) {
+			if (tmp & (1 << udc->ep[i].hwep_num))
+				udc_handle_eps(udc, &udc->ep[i]);
+		}
+	}
+
+	spin_unlock(&udc->lock);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
+{
+	struct lpc32xx_udc *udc = _udc;
+
+	int i;
+	u32 tmp;
+
+	spin_lock(&udc->lock);
+
+	/* Handle EP DMA EOT interrupts */
+	tmp = __raw_readl(USBD_EOTINTST(udc->udp_baseaddr)) |
+		(__raw_readl(USBD_EPDMAST(udc->udp_baseaddr)) &
+		 __raw_readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
+		__raw_readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
+	for (i = 1; i < NUM_ENDPOINTS; i++) {
+		if (tmp & (1 << udc->ep[i].hwep_num))
+			udc_handle_dma_ep(udc, &udc->ep[i]);
+	}
+
+	spin_unlock(&udc->lock);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ *
+ * VBUS detection, pullup handler, and Gadget cable state notification
+ *
+ */
+static void vbus_work(struct work_struct *work)
+{
+	u8 value;
+	struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc,
+					       vbus_wq);
+
+	if (udc->enabled != 0) {
+		/* Discharge VBUS real quick */
+		i2c_write(OTG1_VBUS_DISCHRG, ISP1301_I2C_OTG_CONTROL_1);
+
+		/* Give VBUS some time (100mS) to discharge */
+		msleep(100);
+
+		/* Disable VBUS discharge resistor */
+		i2c_write(OTG1_VBUS_DISCHRG, (ISP1301_I2C_OTG_CONTROL_1 |
+					      ISP1301_I2C_REG_CLEAR_ADDR));
+
+		/* Clear interrupt */
+		i2c_write(~0, ISP1301_I2C_INTERRUPT_LATCH |
+			  ISP1301_I2C_REG_CLEAR_ADDR);
+
+		/* Get the VBUS status from the transceiver */
+		value = i2c_read(ISP1301_I2C_OTG_CONTROL_2);
+
+		/* VBUS on or off? */
+		if (value & OTG_B_SESS_VLD)
+			udc->vbus = 1;
+		else
+			udc->vbus = 0;
+
+		/* VBUS changed? */
+		if (udc->last_vbus != udc->vbus) {
+			udc->last_vbus = udc->vbus;
+			lpc32xx_vbus_session(&udc->gadget, udc->vbus);
+		}
+	}
+
+	/* Re-enable after completion */
+	enable_irq(udc->udp_irq[IRQ_USB_ATX]);
+}
+
+static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
+{
+	struct lpc32xx_udc *udc = _udc;
+
+	/* Defer handling of VBUS IRQ to work queue */
+	disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]);
+	schedule_work(&udc->vbus_wq);
+
+	return IRQ_HANDLED;
+}
+
+static int lpc32xx_start(struct usb_gadget_driver *driver,
+			 int (*bind)(struct usb_gadget *))
+{
+	struct lpc32xx_udc *udc = &controller;
+	int retval, i;
+
+	if (!driver || driver->max_speed < USB_SPEED_FULL ||
+	    !bind || !driver->setup) {
+		dev_err(udc->dev, "bad parameter.\n");
+		return -EINVAL;
+	}
+
+	if (udc->driver) {
+		dev_err(udc->dev, "UDC already has a gadget driver\n");
+		return -EBUSY;
+	}
+
+	udc->driver = driver;
+	udc->gadget.dev.driver = &driver->driver;
+	udc->enabled = 1;
+	udc->selfpowered = 1;
+	udc->vbus = 0;
+
+	retval = bind(&udc->gadget);
+	if (retval) {
+		dev_err(udc->dev, "bind() returned %d\n", retval);
+		udc->enabled = 0;
+		udc->selfpowered = 0;
+		udc->driver = NULL;
+		udc->gadget.dev.driver = NULL;
+		return retval;
+	}
+
+	dev_dbg(udc->dev, "bound to %s\n", driver->driver.name);
+
+	/* Force VBUS process once to check for cable insertion */
+	udc->last_vbus = udc->vbus = 0;
+	schedule_work(&udc->vbus_wq);
+
+	/* Do not re-enable ATX IRQ (3) */
+	for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++)
+		enable_irq(udc->udp_irq[i]);
+
+	return 0;
+}
+
+static int lpc32xx_stop(struct usb_gadget_driver *driver)
+{
+	int i;
+	struct lpc32xx_udc *udc = &controller;
+
+	if (!driver || driver != udc->driver || !driver->unbind)
+		return -EINVAL;
+
+	/* Disable USB pullup */
+	isp1301_pullup_enable(udc, 0, 1);
+
+	for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
+		disable_irq(udc->udp_irq[i]);
+
+	if (udc->clocked) {
+
+		spin_lock(&udc->lock);
+		stop_activity(udc);
+		spin_unlock(&udc->lock);
+
+		/*
+		 *  Wait for all the endpoints to disable,
+		 *  before disabling clocks. Don't wait if
+		 *  endpoints are not enabled.
+		 */
+		if (atomic_read(&udc->enabled_ep_cnt))
+			wait_event_interruptible(udc->ep_disable_wait_queue,
+				(atomic_read(&udc->enabled_ep_cnt) == 0));
+
+		spin_lock(&udc->lock);
+		udc_clk_set(udc, 0);
+		spin_unlock(&udc->lock);
+	}
+
+	udc->enabled = 0;
+	pullup(udc, 0);
+
+	driver->unbind(&udc->gadget);
+	udc->gadget.dev.driver = NULL;
+	udc->driver = NULL;
+
+	dev_dbg(udc->dev, "unbound from %s\n", driver->driver.name);
+	return 0;
+}
+
+static void lpc32xx_udc_shutdown(struct platform_device *dev)
+{
+	/* Force disconnect on reboot */
+	struct lpc32xx_udc *udc = &controller;
+
+	pullup(udc, 0);
+}
+
+static int __init lpc32xx_udc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct lpc32xx_udc *udc = &controller;
+	int retval, i;
+	struct resource *res;
+	dma_addr_t dma_handle;
+	struct i2c_adapter *i2c_adap;
+	struct i2c_board_info i2c_info;
+
+	/* init software state */
+	udc->gadget.dev.parent = dev;
+	udc->pdev = pdev;
+	udc->dev = &pdev->dev;
+	udc->enabled = 0;
+
+	if (!dev->platform_data) {
+		dev_err(udc->dev, "missing platform_data\n");
+		return -ENODEV;
+	}
+
+	udc->board = (struct lpc32xx_usbd_cfg *) dev->platform_data;
+
+	/*
+	 * Resources are mapped as follows:
+	 *  [0] = IORESOURCE_MEM, base address and size of USB space
+	 *  [1] = IORESOURCE_IRQ, USB device low priority interrupt number
+	 *  [2] = IORESOURCE_IRQ, USB device high priority interrupt number
+	 *  [3] = IORESOURCE_IRQ, USB device interrupt number
+	 *  [4] = IORESOURCE_IRQ, USB transciever interrupt number
+	 */
+	if (pdev->num_resources != 5) {
+		dev_err(udc->dev, "invalid num_resources\n");
+		return -ENODEV;
+	}
+
+	if (pdev->resource[0].flags != IORESOURCE_MEM) {
+		dev_err(udc->dev, "invalid resource type\n");
+		return -ENODEV;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENXIO;
+
+	spin_lock_init(&udc->lock);
+
+	/* Get IRQs */
+	for (i = 0; i < 4; i++) {
+		if (pdev->resource[i + 1].flags != IORESOURCE_IRQ) {
+			dev_err(udc->dev, "invalid resource type\n");
+			return -ENODEV;
+		}
+		udc->udp_irq[i] = platform_get_irq(pdev, i);
+	}
+
+	udc->io_p_start = res->start;
+	udc->io_p_size = res->end - res->start + 1;
+	if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) {
+		dev_err(udc->dev, "someone's using UDC memory\n");
+		return -EBUSY;
+	}
+
+	/* Enable AHB slave USB clock, needed for further USB clock control */
+	__raw_writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
+
+	/* Get required clocks */
+	udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5");
+	if (IS_ERR(udc->usb_pll_clk)) {
+		dev_err(udc->dev, "failed to acquire USB PLL\n");
+		retval = PTR_ERR(udc->usb_pll_clk);
+		goto pll_get_fail;
+	}
+	udc->usb_slv_clk = clk_get(&pdev->dev, "ck_usbd");
+	if (IS_ERR(udc->usb_slv_clk)) {
+		dev_err(udc->dev, "failed to acquire USB device clock\n");
+		retval = PTR_ERR(udc->usb_slv_clk);
+		goto usb_clk_get_fail;
+	}
+
+	/* Setup PLL clock to 48MHz */
+	retval = clk_enable(udc->usb_pll_clk);
+	if (retval < 0) {
+		dev_err(udc->dev, "failed to start USB PLL\n");
+		goto pll_enable_fail;
+	}
+
+	retval = clk_set_rate(udc->usb_pll_clk, 48000);
+	if (retval < 0) {
+		dev_err(udc->dev, "failed to set USB clock rate\n");
+		goto pll_set_fail;
+	}
+
+	__raw_writel(__raw_readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL);
+
+	/* Enable USB device clock */
+	retval = clk_enable(udc->usb_slv_clk);
+	if (retval < 0) {
+		dev_err(udc->dev, "failed to start USB device clock\n");
+		goto usb_clk_enable_fail;
+	}
+
+	/* Set to enable all needed USB OTG clocks */
+	__raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL);
+
+	i = 1000;
+	while (((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) !=
+		USB_CLOCK_MASK) && (i > 0))
+		i--;
+	if (!i)
+		dev_dbg(udc->dev, "USB OTG clocks not correctly enabled\n");
+
+	/* Setup deferred workqueue data */
+	udc->poweron = udc->pullup = 0;
+	INIT_WORK(&udc->pullup_wq, pullup_work);
+	INIT_WORK(&udc->vbus_wq, vbus_work);
+#ifdef CONFIG_PM
+	INIT_WORK(&udc->power_wq, power_work);
+#endif
+
+	/* All clocks are now on */
+	udc->clocked = 1;
+
+	retval = i2c_add_driver(&isp1301_driver);
+	if (retval < 0) {
+		dev_err(udc->dev, "Failed to add ISP1301 driver\n");
+		goto i2c_add_fail;
+	}
+	i2c_adap = i2c_get_adapter(2);
+	memset(&i2c_info, 0, sizeof(struct i2c_board_info));
+	isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
+						   normal_i2c, NULL);
+	i2c_put_adapter(i2c_adap);
+	if (!isp1301_i2c_client) {
+		dev_err(udc->dev,
+			"failed to connect I2C to ISP1301 USB Transceiver\n");
+		goto i2c_probe_fail;
+	}
+
+	dev_info(udc->dev,
+		 "I2C device at address 0x%x\n", isp1301_i2c_client->addr);
+
+	isp1301_udc_configure(udc);
+	/* Map register space */
+	udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size);
+	if (!udc->udp_baseaddr) {
+		retval = -ENOMEM;
+		dev_err(udc->dev, "IO map failure\n");
+		goto io_map_fail;
+	}
+
+	/* Allocate memory for the UDCA */
+	udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
+					      &dma_handle,
+					      (GFP_KERNEL | GFP_DMA));
+	if (!udc->udca_v_base) {
+		dev_err(udc->dev, "error getting UDCA region\n");
+		retval = -ENOMEM;
+		goto dma_alloc_fail;
+	}
+	udc->udca_p_base = dma_handle;
+	dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
+		UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
+
+	/* Setup the DD DMA memory pool */
+	udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
+					sizeof(struct lpc32xx_usbd_dd_gad),
+					sizeof(u32), 0);
+	if (!udc->dd_cache) {
+		dev_err(udc->dev, "error getting DD DMA region\n");
+		retval = -ENOMEM;
+		goto dma2_alloc_fail;
+	}
+
+	/* Clear USB peripheral and initialize gadget endpoints */
+	udc_disable(udc);
+	udc_reinit(udc);
+
+	retval = device_register(&udc->gadget.dev);
+	if (retval < 0) {
+		dev_err(udc->dev, "Device registration failure\n");
+		goto dev_register_fail;
+	}
+
+	/* Request IRQs - low and high priority USB device IRQs are routed to
+	 * the same handler, while the DMA interrupt is routed elsewhere */
+	retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq,
+			     0, "udc_lp", udc);
+	if (retval < 0) {
+		dev_err(udc->dev, "LP request irq %d failed\n",
+			udc->udp_irq[IRQ_USB_LP]);
+		goto irq_lp_fail;
+	}
+	retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq,
+			     0, "udc_hp", udc);
+	if (retval < 0) {
+		dev_err(udc->dev, "HP request irq %d failed\n",
+			udc->udp_irq[IRQ_USB_HP]);
+		goto irq_hp_fail;
+	}
+
+	retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA],
+			     lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
+	if (retval < 0) {
+		dev_err(udc->dev, "DEV request irq %d failed\n",
+			udc->udp_irq[IRQ_USB_DEVDMA]);
+		goto irq_dev_fail;
+	}
+
+	/* The transceiver interrupt is used for VBUS detection and will
+	   kick off the VBUS handler function */
+	retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq,
+			     0, "udc_otg", udc);
+	if (retval < 0) {
+		dev_err(udc->dev, "VBUS request irq %d failed\n",
+			udc->udp_irq[IRQ_USB_ATX]);
+		goto irq_xcvr_fail;
+	}
+
+	/* Initialize wait queue */
+	init_waitqueue_head(&udc->ep_disable_wait_queue);
+	atomic_set(&udc->enabled_ep_cnt, 0);
+
+	/* Keep all IRQs disabled until GadgetFS starts up */
+	for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
+		disable_irq(udc->udp_irq[i]);
+
+	retval = usb_add_gadget_udc(dev, &udc->gadget);
+	if (retval < 0)
+		goto add_gadget_fail;
+
+	dev_set_drvdata(dev, udc);
+	device_init_wakeup(dev, 1);
+	create_debug_file(udc);
+
+	/* Disable clocks for now */
+	udc_clk_set(udc, 0);
+
+	dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
+	return 0;
+
+add_gadget_fail:
+	free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
+irq_xcvr_fail:
+	free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
+irq_dev_fail:
+	free_irq(udc->udp_irq[IRQ_USB_HP], udc);
+irq_hp_fail:
+	free_irq(udc->udp_irq[IRQ_USB_LP], udc);
+irq_lp_fail:
+	device_unregister(&udc->gadget.dev);
+dev_register_fail:
+	dma_pool_destroy(udc->dd_cache);
+dma2_alloc_fail:
+	dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
+			  udc->udca_v_base, udc->udca_p_base);
+dma_alloc_fail:
+	iounmap(udc->udp_baseaddr);
+io_map_fail:
+	i2c_unregister_device(isp1301_i2c_client);
+	isp1301_i2c_client = NULL;
+i2c_probe_fail:
+	i2c_del_driver(&isp1301_driver);
+i2c_add_fail:
+	clk_disable(udc->usb_slv_clk);
+usb_clk_enable_fail:
+pll_set_fail:
+	clk_disable(udc->usb_pll_clk);
+pll_enable_fail:
+	clk_put(udc->usb_slv_clk);
+usb_clk_get_fail:
+	clk_put(udc->usb_pll_clk);
+pll_get_fail:
+	release_mem_region(udc->io_p_start, udc->io_p_size);
+	dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
+
+	return retval;
+}
+
+static int __exit lpc32xx_udc_remove(struct platform_device *pdev)
+{
+	struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
+
+	usb_del_gadget_udc(&udc->gadget);
+	if (udc->driver)
+		return -EBUSY;
+
+	udc_clk_set(udc, 1);
+	udc_disable(udc);
+	pullup(udc, 0);
+
+	free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
+
+	device_init_wakeup(&pdev->dev, 0);
+	remove_debug_file(udc);
+
+	dma_pool_destroy(udc->dd_cache);
+	dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
+			  udc->udca_v_base, udc->udca_p_base);
+	free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
+	free_irq(udc->udp_irq[IRQ_USB_HP], udc);
+	free_irq(udc->udp_irq[IRQ_USB_LP], udc);
+
+	device_unregister(&udc->gadget.dev);
+
+	clk_disable(udc->usb_slv_clk);
+	clk_put(udc->usb_slv_clk);
+	clk_disable(udc->usb_pll_clk);
+	clk_put(udc->usb_pll_clk);
+	iounmap(udc->udp_baseaddr);
+	i2c_unregister_device(isp1301_i2c_client);
+	isp1301_i2c_client = NULL;
+	i2c_del_driver(&isp1301_driver);
+	release_mem_region(udc->io_p_start, udc->io_p_size);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+	int to = 1000;
+	struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
+
+	if (udc->clocked) {
+		/* Power down ISP */
+		udc->poweron = 0;
+		isp1301_set_powerstate(0);
+
+		/* Disable clocking */
+		udc_clk_set(udc, 0);
+
+		/* Keep clock flag on, so we know to re-enable clocks
+		   on resume */
+		udc->clocked = 1;
+
+		/* Kill OTG and I2C clocks */
+		__raw_writel(0, USB_OTG_CLK_CTRL);
+		while (((__raw_readl(USB_OTG_CLK_STAT) & OTGOFF_CLK_MASK) !=
+			OTGOFF_CLK_MASK) && (to > 0))
+			to--;
+		if (!to)
+			dev_dbg(udc->dev,
+				"USB OTG clocks not correctly enabled\n");
+
+		/* Kill global USB clock */
+		clk_disable(udc->usb_slv_clk);
+	}
+
+	return 0;
+}
+
+static int lpc32xx_udc_resume(struct platform_device *pdev)
+{
+	struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
+
+	if (udc->clocked) {
+		/* Enable global USB clock */
+		clk_enable(udc->usb_slv_clk);
+
+		/* Enable clocking */
+		udc_clk_set(udc, 1);
+
+		/* ISP back to normal power mode */
+		udc->poweron = 1;
+		isp1301_set_powerstate(1);
+	}
+
+	return 0;
+}
+#else
+#define	lpc32xx_udc_suspend	NULL
+#define	lpc32xx_udc_resume	NULL
+#endif
+
+static struct platform_driver lpc32xx_udc_driver = {
+	.remove		= __exit_p(lpc32xx_udc_remove),
+	.shutdown	= lpc32xx_udc_shutdown,
+	.suspend	= lpc32xx_udc_suspend,
+	.resume		= lpc32xx_udc_resume,
+	.driver		= {
+		.name	= (char *) driver_name,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init udc_init_module(void)
+{
+	return platform_driver_probe(&lpc32xx_udc_driver, lpc32xx_udc_probe);
+}
+module_init(udc_init_module);
+
+static void __exit udc_exit_module(void)
+{
+	platform_driver_unregister(&lpc32xx_udc_driver);
+}
+module_exit(udc_exit_module);
+
+MODULE_DESCRIPTION("LPC32XX udc driver");
+MODULE_AUTHOR("Kevin Wells <kevin.wells at nxp.com>");
+MODULE_AUTHOR("Roland Stigge <stigge at antcom.de>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:lpc32xx_udc");


From davem at davemloft.net  Mon Mar 19 17:20:05 2012
From: davem at davemloft.net (David Miller)
Date: Mon, 19 Mar 2012 17:20:05 -0400 (EDT)
Subject: [PATCH v8 RESEND] ARM: net: JIT compiler for packet filters
In-Reply-To: <1331933316-10197-1-git-send-email-mgherzan@gmail.com>
References: <1331933316-10197-1-git-send-email-mgherzan@gmail.com>
Message-ID: <20120319.172005.1889334604020296555.davem@davemloft.net>


I would like to see this merged however is feasible, this has been in
a catatonic state for two releases and waiting longer isn't going to
improve things enough to justify any further delay.


From stigge at antcom.de  Mon Mar 19 17:23:36 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 19 Mar 2012 22:23:36 +0100
Subject: [PATCH] ARM: LPC32xx: Mach specific support for USB gadget
Message-ID: <1332192216-2502-1-git-send-email-stigge@antcom.de>

This patch adds support for the USB gadget driver
(see separate patch for drivers/usb/gadget/*).

Signed-off-by: Roland Stigge <stigge at antcom.de>

---

Applies to v3.3 + usb + eth support in mach-lpc32xx (in arm-soc)

See also branch lpc32xx/mach-lpc32xx-eth at git://git.antcom.de/linux-2.6.git
as a baseline

 arch/arm/mach-lpc32xx/common.c             |   60 +++++++++++++++++++++++++++++
 arch/arm/mach-lpc32xx/common.h             |    1 
 arch/arm/mach-lpc32xx/include/mach/board.h |   11 +++++
 arch/arm/mach-lpc32xx/phy3250.c            |    1 
 4 files changed, 73 insertions(+)

--- linux-2.6.orig/arch/arm/mach-lpc32xx/common.c
+++ linux-2.6/arch/arm/mach-lpc32xx/common.c
@@ -185,6 +185,66 @@ struct platform_device lpc32xx_ohci_devi
 	.resource = ohci_resources,
 };
 
+static void phy3250_usbd_conn_chg(int conn)
+{
+	/* Do nothing, it might be nice to enable an LED
+	 * based on conn state being !0 */
+}
+
+static void phy3250_usbd_susp_chg(int susp)
+{
+	/* Device suspend if susp != 0 */
+}
+
+static void phy3250_rmwkup_chg(int remote_wakup_enable)
+{
+	/* Enable or disable USB remote wakeup */
+}
+
+struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
+	.vbus_drv_pol = 1,
+	.conn_chgb = &phy3250_usbd_conn_chg,
+	.susp_chgb = &phy3250_usbd_susp_chg,
+	.rmwk_chgb = &phy3250_rmwkup_chg,
+};
+
+/*
+ * USB Gadget support
+ */
+/* The dmamask must be set for USB to work, align to 128 bytes */
+static u64 usbd_dmamask = ~(u32) 0x7F;
+static struct resource usbd_resources[] = {
+	{
+		.start = LPC32XX_USB_BASE,
+		.end = LPC32XX_USB_BASE + 0x300 - 1,
+		.flags = IORESOURCE_MEM,
+	}, {
+		.start = IRQ_LPC32XX_USB_DEV_LP,
+		.flags = IORESOURCE_IRQ,
+	}, {
+		.start = IRQ_LPC32XX_USB_DEV_HP,
+		.flags = IORESOURCE_IRQ,
+	}, {
+		.start = IRQ_LPC32XX_USB_DEV_DMA,
+		.flags = IORESOURCE_IRQ,
+	}, {
+		.start = IRQ_LPC32XX_USB_OTG_ATX,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device lpc32xx_usbd_device = {
+	.name = "lpc32xx_udc",
+	.id = -1,
+	.dev = {
+		.dma_mask = &usbd_dmamask,
+		.coherent_dma_mask = 0xFFFFFFFF,
+		.platform_data  = &lpc32xx_usbddata,
+	},
+	.num_resources = ARRAY_SIZE(usbd_resources),
+	.resource = usbd_resources,
+};
+
 /*
  * Network Support
  */
--- linux-2.6.orig/arch/arm/mach-lpc32xx/common.h
+++ linux-2.6/arch/arm/mach-lpc32xx/common.h
@@ -33,6 +33,7 @@ extern struct platform_device lpc32xx_ts
 extern struct platform_device lpc32xx_adc_device;
 extern struct platform_device lpc32xx_rtc_device;
 extern struct platform_device lpc32xx_ohci_device;
+extern struct platform_device lpc32xx_usbd_device;
 extern struct platform_device lpc32xx_net_device;
 
 /*
--- linux-2.6.orig/arch/arm/mach-lpc32xx/include/mach/board.h
+++ linux-2.6/arch/arm/mach-lpc32xx/include/mach/board.h
@@ -21,4 +21,15 @@
 
 extern u32 lpc32xx_return_iram_size(void);
 
+/*
+ * USB device configuration structure
+ */
+typedef void (*usc_chg_event)(int);
+struct lpc32xx_usbd_cfg {
+	int vbus_drv_pol;   /* 0=active low drive for VBUS via ISP1301 */
+	usc_chg_event conn_chgb; /* Connection change event (optional) */
+	usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
+	usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
+};
+
 #endif  /* __ASM_ARCH_BOARD_H */
--- linux-2.6.orig/arch/arm/mach-lpc32xx/phy3250.c
+++ linux-2.6/arch/arm/mach-lpc32xx/phy3250.c
@@ -279,6 +279,7 @@ static struct platform_device *phy3250_d
 	&lpc32xx_gpio_led_device,
 	&lpc32xx_adc_device,
 	&lpc32xx_ohci_device,
+	&lpc32xx_usbd_device,
 	&lpc32xx_net_device,
 };
 


From khilman at ti.com  Mon Mar 19 17:27:03 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 19 Mar 2012 14:27:03 -0700
Subject: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting to
 add IVA OPP
In-Reply-To: <20120316142034.GA22234@senorita.am.dhcp.ti.com> (Nishanth
 Menon's message of "Fri, 16 Mar 2012 09:20:35 -0500")
References: <8762e6et1u.fsf@ti.com>
 <5448984682E7954C9BFF27F747A9C6CA56D6A8@dolphin.TIGRIS.local>
 <20120316142034.GA22234@senorita.am.dhcp.ti.com>
Message-ID: <87sjh45ljs.fsf@ti.com>

Nishanth Menon <nm at ti.com> writes:

> On 10:26-20120316, Maximilian Schwerin wrote:
> [...]
>> > >>> +
>> > >>> + ? ? ? ? ? ? if ((strcmp(opp_def->hwmod_name,"iva") == 
>> > 0) && !omap3_has_iva())
>> > >>> + ? ? ? ? ? ? ? ? ? ? continue;
>> > >>> +
>> > >>> ? ? ? ? ? ? ? oh = omap_hwmod_lookup(opp_def->hwmod_name);
>> > >>> ? ? ? ? ? ? ? if (!oh || !oh->od) {
>> > >>> ? ? ? ? ? ? ? ? ? ? ? pr_warn("%s: no hwmod or odev for %s, [%d] "
>> > >>
>> > >> Wouldn't the one-liner below do the same thing?
>> > >>
>> > >> Actually, your patch makes it less noisy at boot time, avoiding the
>> > >> pr_warn(), so is probably better.
>> > >
>> > > The only issue i have with current patch is that it 
>> > focusses to solve
>> > > a specific device IVA.
>> > > we could have similar variances if we had SGX/AESS device etc
>> > > registered in the common
>> > > table. a generic solution might be preferable - could we reduce the
>> > > severity of pr_warn to pr_debug and do a continue instead?
>> > 
>> > I agree, that would be a better generic solution.
>> > 
>> > Kevin
>> >
>> 
>> This is a pragmatic and simple solution for a well understood problem with no side effects. Why not fix the problem now and do the generic solution later on? 
>> 
>> I'm not a fulltime kernel dev. I have about two weeks to get my new board out to my customer... Every time I set up a new board, I have to fix problems using known patches that are sometimes years old. Every patch I have to find costs me hours of time I really don't have. 
>> 
>> Just my two cents (euro cents of course :-), Maximilian
> ok, so lets fix it generically - here is the patch for it. Let us know
> if this works for you
>
>
> From 5275d09c9f1a16c8f0814745e1c313c6cca049f6 Mon Sep 17 00:00:00 2001
> From: Nishanth Menon <nm at ti.com>
> Date: Fri, 16 Mar 2012 09:13:24 -0500
> Subject: [PATCH] OMAP2+: OPP: allow OPP enumeration to continue if device is not present
>
> On platforms such as OMAP3, certain variants may not have IVA, SGX
> or some specific component. We currently have a check to aid fixing
> wrong population of OPP entries for issues such as typos. This however
> causes a conflict with valid requirement where the SoC variant does
> not actually have the module present.
>
> So, reduce the severity of the print to a debug statement and skip
> registering that specific OPP, but continue down the list.
>
> Reported-by: Steve Sakoman <steve at sakoman.com>
> Reported-by: Maximilian Schwerin <mvs at tigris.de>
> Signed-off-by: Nishanth Menon <nm at ti.com>
> ---
>  arch/arm/mach-omap2/opp.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
> index 9262a6b..de6d464 100644
> --- a/arch/arm/mach-omap2/opp.c
> +++ b/arch/arm/mach-omap2/opp.c
> @@ -64,10 +64,10 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
>  		}
>  		oh = omap_hwmod_lookup(opp_def->hwmod_name);
>  		if (!oh || !oh->od) {
> -			pr_warn("%s: no hwmod or odev for %s, [%d] "
> +			pr_debug("%s: no hwmod or odev for %s, [%d] "
>  				"cannot add OPPs.\n", __func__,
>  				opp_def->hwmod_name, i);
> -			return -EINVAL;
> +			continue;
>  		}
>  		dev = &oh->od->pdev->dev;
>  

Yes, thanks for doing this more genericly.

Nishanth, can you collect the acks/tested-bys and repost and official
patch.

I'll queue this up.

Thanks,

Kevin


From nm at ti.com  Mon Mar 19 17:29:40 2012
From: nm at ti.com (Menon, Nishanth)
Date: Mon, 19 Mar 2012 16:29:40 -0500
Subject: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting to
 add IVA OPP
In-Reply-To: <87sjh45ljs.fsf@ti.com>
References: <8762e6et1u.fsf@ti.com>
 <5448984682E7954C9BFF27F747A9C6CA56D6A8@dolphin.TIGRIS.local>
 <20120316142034.GA22234@senorita.am.dhcp.ti.com> <87sjh45ljs.fsf@ti.com>
Message-ID: <CAOMWX4cXwppGu_P2csWYtHJazpRNDz0W7xQcfyAcwqJ7SJodDA@mail.gmail.com>

Kevin,
[...]
> Nishanth, can you collect the acks/tested-bys and repost and official
> patch.
>
> I'll queue this up.
Thanks. This is already done:
http://marc.info/?l=linux-omap&m=133191481703750&w=2

Regards,
Nishanth Menon


From arnd at arndb.de  Mon Mar 19 17:30:13 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 21:30:13 +0000
Subject: [PATCH] USB: gadget driver for LPC32xx
In-Reply-To: <1332191930-2433-1-git-send-email-stigge@antcom.de>
References: <1332191930-2433-1-git-send-email-stigge@antcom.de>
Message-ID: <201203192130.13583.arnd@arndb.de>

On Monday 19 March 2012, Roland Stigge wrote:
> This patch adds a USB gadget driver.
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>
> 
> ---
> 
> Applies to v3.3
> 
> 
>  drivers/usb/gadget/Kconfig        |   10 
>  drivers/usb/gadget/Makefile       |    1 
>  drivers/usb/gadget/gadget_chips.h |    3 
>  drivers/usb/gadget/lpc32xx_udc.c  | 3598 ++++++++++++++++++++++++++++++++++++++
>  4 files changed, 3612 insertions(+)

Hi Roland,

There is already a driver for the isp1301 otg part in the kernel, I don't
think we want to add another one.

From what I can tell, this shares a common ancestry with the omap version
but has diverged quite a bit. The best solution would really be to
bring the two back together and let them share a common base driver,
with the lpc32xx and omap specific bits in another file.

	Arnd


From khilman at ti.com  Mon Mar 19 17:39:12 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 19 Mar 2012 14:39:12 -0700
Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulator for
 first instance
In-Reply-To: <201203192118.09286.arnd@arndb.de> (Arnd Bergmann's message of
 "Mon, 19 Mar 2012 21:18:09 +0000")
References: <1331080771-30687-1-git-send-email-khilman@ti.com>
 <201203192118.09286.arnd@arndb.de>
Message-ID: <87mx7c5kzj.fsf@ti.com>

Hi Arnd,

Arnd Bergmann <arnd at arndb.de> writes:

> On Wednesday 07 March 2012, Kevin Hilman wrote:
>> commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
>> regulators) added regulators which are registered during
>> gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
>> than one instance of the SMSC911x and result in attempting to register
>> the same regulator more than once which causes a panic().
>> 
>> Fix this by only registering the regulator when the platform_data id
>> field is zero, indicating its the first instance.
>> 
>> Cc: Matt Porter <mporter at ti.com>
>> Signed-off-by: Kevin Hilman <khilman at ti.com>
>
> It seems that both Olof and I forgot to forward this one to Linus.
>
> If it's ok for you, I'll add it to the fixes branch for v3.4 now
> and mark it for backporting to v3.3-stable.

A slightly different version of this is already in linux-next as commit
bb60424af517d6e6148505fb5ef256caa91b5b43.

It was in your 'fixes' branch, and was merged by Olaf from Tony on 3/13:
Merge branch 'fix-smsc911x-regulator' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Kevin



From khilman at ti.com  Mon Mar 19 17:43:54 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 19 Mar 2012 14:43:54 -0700
Subject: [PATCH v3 0/2] arm: omap3: pm34xx.c: Some minor fixups
In-Reply-To: <1332033768-21986-1-git-send-email-mgreer@animalcreek.com> (Mark
 A. Greer's message of "Sat, 17 Mar 2012 18:22:46 -0700")
References: <1332033768-21986-1-git-send-email-mgreer@animalcreek.com>
Message-ID: <87ehso5krp.fsf@ti.com>

"Mark A. Greer" <mgreer at animalcreek.com> writes:

> I found some minor issues when looking through pm34xx.c recently
> so these patches try to address them.  My apologies if they are
> already fixed in another branch somewhere.  Based on latest k.o.
> master branch.

Thanks Mark.

Queueing these for v3.4-rc.

Kevin


From swarren at wwwdotorg.org  Mon Mar 19 17:45:38 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 15:45:38 -0600
Subject: [PATCH 1/5] pinctrl: add samsung pinctrl and gpiolib driver
In-Reply-To: <1331469965-28846-2-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <1331469965-28846-2-git-send-email-thomas.abraham@linaro.org>
Message-ID: <4F67A902.40409@wwwdotorg.org>

On 03/11/2012 06:46 AM, Thomas Abraham wrote:
> Add a new pinctrl and gpiolib driver for Samsung SoC's. This driver provides a
> common framework for all Samsung SoC's to interface with the pinctrl and
> gpiolib subsystems.
> 
> This driver is split into two parts: the pinctrl interface and the gpiolib
> interface. The pinctrl interface registers pinctrl devices with the pinctrl
> subsystem and gpiolib interface registers gpio chips with the gpiolib
> subsystem. The information about the pins, pin groups, pin functions and
> gpio chips, which are SoC specific, are all provided to the driver using
> driver data. The driver registers all the pinctrl devices and gpio chips
> which are found in the driver data.

> diff --git a/arch/arm/plat-samsung/include/plat/pinctrl.h b/arch/arm/plat-samsung/include/plat/pinctrl.h

It'd be nice to name this samsung-pinctrl.h, or something other than
just "pinctrl.h". That way, this new header won't cause problems for a
multi-SoC kernel in the future where multiple plat-*/include/plat or
mach-*/include/mach directories are in the include path.

> diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c

> +/* check if the selector is a valid pin function selector */
> +static int samsung_pinmux_list_funcs(struct pinctrl_dev *pctldev,
> +					unsigned selector)
> +{
> +	struct samsung_pinctrl_drv_data *drvdata;
> +
> +	drvdata = pinctrl_dev_get_drvdata(pctldev);
> +	if (selector >= drvdata->nr_groups)
> +		return -EINVAL;

That test should be against something other than nr_groups; nr_functions
or similar, right?

> +static void samsung_pimux_setup(struct pinctrl_dev *pctldev, unsigned selector,

s/pimux/pinmux/

...
> +	const unsigned int *pin;
...
> +	pin = drvdata->pin_groups[group].pins;

It might be a little clearer to rename "pin" to "pins", since it's an
array...

> +
> +	/*
> +	 * for each pin in the pin group selected, program the correspoding pin
> +	 * pin function number in the config register.
> +	 */
> +	for (cnt = 0; cnt < drvdata->pin_groups[group].num_pins; cnt++, pin++) {
> +		pin_to_reg_bank(drvdata->gc, *pin - drvdata->ctrl->base,
> +				&reg, &pin_offset, &bank);

... and say pins[cnt] instead of *pin here (and remove pin++ from the
for loop statement)

But it's just a slight suggestion; your call.

> +static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
> +		struct pinctrl_gpio_range *range, unsigned offset, bool input)
...
> +	pin_to_reg_bank(range->gc, offset, &reg, &pin_offset, &bank);
> +	mask = (1 << bank->func_width) - 1;
> +	shift = pin_offset * bank->func_width;

It might be useful to put those 3 lines into a helper function since
they're duplicating with samsung_pimux_setup() and similar code is in
samsung_pinconf_set() too.

> +static int samsung_pinconf_group_set(struct pinctrl_dev *pctldev,
> +			unsigned group, unsigned long config)

I think you can leave out group_set(), and the pinctrl core will loop
over all pins in the group for you.

> +static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
...
> +	data = readl(reg + DAT_REG);
...
> +	__raw_writel(data, reg + DAT_REG);

Why sometimes use the __raw variants and sometimes not?

> +static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
> +							int value)
...
> +	ret = pinctrl_gpio_direction_output(gc->base + offset);
> +	if (!ret)
> +		samsung_gpio_set(gc, offset, value);

This will set the GPIO to output direction before programming the output
value, which might cause a glitch. You may want to try and swap those
two function calls.

> +static int __devinit samsung_pinctrl_probe(struct platform_device *pdev)
...
> +	res = request_mem_region(res->start, resource_size(res),
> +					pdev->name);
> +	if (!res) {
> +		dev_err(&pdev->dev, "request for mem region failed\n");
> +		return -EBUSY;
> +	}
> +
> +	drvdata->virt_base = ioremap(res->start, resource_size(res));

Perhaps replace those two function calls with
devm_request_and_ioremap(), and as a bonus you won't have to unmap or
release the region either.

> +	if (!drvdata->virt_base) {
> +		dev_err(&pdev->dev, "ioremap failed\n");

i.e. you wouldn't have to add the missing error-handling here, and below.

> +		return -EINVAL;
> +	}

> +/* driver data for various samsung soc's */
> +#ifdef CONFIG_CPU_EXYNOS4210
> +
> +#define EXYNOS4210_PCTRL_DRVDATA ((kernel_ulong_t)&exynos4210_pinctrl_drv_data)
> +#else
> +#define EXYNOS4210_PCTRL_DRVDATA ((kernel_ulong_t)NULL)
> +#endif /* CONFIG_CPU_EXYNOS4210 */

Doesn't that interact badly with samsung_pinctrl_get_driver_data()
above, which just blindly adds to the .driver_data field when an entry
is found in samsung_pinctrl_driver_ids[]?

> +static struct platform_device_id samsung_pinctrl_driver_ids[] = {
> +	{
> +		.name		= "exynos4-pinctrl",
> +		.driver_data	= EXYNOS4210_PCTRL_DRVDATA,
> +	},
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(platform, samsung_pinctrl_driver_ids);


From khilman at ti.com  Mon Mar 19 17:48:31 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 19 Mar 2012 14:48:31 -0700
Subject: [PATCH] OMAP2+: OPP: allow OPP enumeration to continue if device
 is not present
In-Reply-To: <1331914749-23171-1-git-send-email-nm@ti.com> (Nishanth Menon's
 message of "Fri, 16 Mar 2012 11:19:09 -0500")
References: <1331914749-23171-1-git-send-email-nm@ti.com>
Message-ID: <8739945kk0.fsf@ti.com>

Nishanth Menon <nm at ti.com> writes:

> On platforms such as OMAP3, certain variants may not have IVA, SGX
> or some specific component. We currently have a check to aid fixing
> wrong population of OPP entries for issues such as typos. This however
> causes a conflict with valid requirement where the SoC variant does
> not actually have the module present.
>
> So, reduce the severity of the print to a debug statement and skip
> registering that specific OPP, but continue down the list.
>
> Reported-by: Steve Sakoman <steve at sakoman.com>
> Reported-by: Maximilian Schwerin <mvs at tigris.de>
> Acked-by: Steve Sakoman <steve at sakoman.com>
> Tested-by: Maximilian Schwerin <mvs at tigris.de>
> Signed-off-by: Nishanth Menon <nm at ti.com>

Thanks, queuing as a fix for for v3.4-rc (branch: for_3.4/fixes/pm)

Kevin


From grant.likely at secretlab.ca  Mon Mar 19 17:49:55 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 19 Mar 2012 21:49:55 +0000
Subject: [PATCH] gpio: tegra: tegra_gpio_config shouldn't be __init
In-Reply-To: <1332178560-15658-1-git-send-email-swarren@wwwdotorg.org>
References: <1332178560-15658-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <20120319214955.378CB3E0A04@localhost>

On Mon, 19 Mar 2012 11:36:00 -0600, Stephen Warren <swarren at wwwdotorg.org> wrote:
> This function is called from non-__init context, just like
> tegra_gpio_enable()/disable(). Remove the __init annotation to avoid
> section mismatch warnings during compile.
> 
> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>

Applied, thanks.

g.

> ---
>  drivers/gpio/gpio-tegra.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
> index 636be99..32de670 100644
> --- a/drivers/gpio/gpio-tegra.c
> +++ b/drivers/gpio/gpio-tegra.c
> @@ -461,7 +461,7 @@ static int __init tegra_gpio_init(void)
>  }
>  postcore_initcall(tegra_gpio_init);
>  
> -void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
> +void tegra_gpio_config(struct tegra_gpio_table *table, int num)
>  {
>  	int i;
>  
> -- 
> 1.7.0.4
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From swarren at wwwdotorg.org  Mon Mar 19 17:55:24 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 15:55:24 -0600
Subject: [PATCH 5/5] mmc: sdhci-s3c: setup pins using pinctrl interface
In-Reply-To: <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
References: <1331469965-28846-1-git-send-email-thomas.abraham@linaro.org>
 <1331469965-28846-6-git-send-email-thomas.abraham@linaro.org>
Message-ID: <4F67AB4C.9040801@wwwdotorg.org>

On 03/11/2012 06:46 AM, Thomas Abraham wrote:
> The platform specific callback to setup the sdhci pin mux and pin config
> is removed and the pinctrl subsystem interface is used to setup the
> mux and config.

> @@ -643,8 +649,13 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>  	}
>  
>  	/* Ensure we have minimal gpio selected CMD/CLK/Detect */
> -	if (pdata->cfg_gpio)
> -		pdata->cfg_gpio(pdev, pdata->max_width);
> +	pstate = pdata->max_width ? "sdhci-pcfg8" : "sdhci-pcfg4";

If the driver is going to select a single state ("sdhci-pcfg8" or
"sdhci-pcfg4" above) at probe() time and never change it (which seems
quite reasonable for an SDHCI controller), then the driver should always
use state PINCTRL_STATE_DEFAULT, and it should be up to the board to set
up the mapping table such that PINCTRL_STATE_DEFAULT sets up the pins
for either 4-bit or 8-bit as appropriate for the board.


From grant.likely at secretlab.ca  Mon Mar 19 18:02:24 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 19 Mar 2012 22:02:24 +0000
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20327.25470.723875.916422@ipc1.ka-ro>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
 <20120316030134.GA5161@shlinux2.ap.freescale.net>
 <20120318184749.BB15D3E07BF@localhost> <20326.55337.249575.289067@ipc1.ka-ro>
 <20120319150601.B783A3E05A5@localhost> <20327.25470.723875.916422@ipc1.ka-ro>
Message-ID: <20120319220224.ABF5A3E0A04@localhost>

On Mon, 19 Mar 2012 17:49:02 +0100, Lothar Wa??mann <LW at KARO-electronics.de> wrote:
> Hi,
> 
> Grant Likely writes:
> > On Mon, 19 Mar 2012 07:54:33 +0100, Lothar Wa??mann <LW at KARO-electronics.de> wrote:
> > > Grant Likely writes:
> > > > On Fri, 16 Mar 2012 11:01:35 +0800, Dong Aisheng <aisheng.dong at freescale.com> wrote:
> > > > > On Thu, Mar 15, 2012 at 07:22:04PM +0800, Lothar Wa??mann wrote:
> > > > > > Dong Aisheng writes:
> > > > > > > On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa??mann wrote:
> > > > > > Anyway there is no definite spec how the MAC address(es) are stored
> > > > > > in the fuse map. Thus reading the MAC from there is more or less
> > > > > > platform specific.
> > > > > > 
> > > > > It's just provide one more option since there are customers storing the MAC
> > > > > in the fuse map.
> > > > 
> > > > That should be straight forward to support; have a property that
> > > > specifies the method used for fetching/calculating the MAC.
> > > > 
> > > Executable code stored inside a DT blob? ;)
> > 
> > I know you're joking here, but I'm going to answer seriously
> > anyway... Absolutely not.  What I'm suggesting is a property that
> > specifies the method used to determine the mac address.  Something
> > like (off the top of my head):
> > 
> > 	local-mac-address = [01 02 03 00 00 00];
> > 	local-mac-mask = [0xff 0xff 0xff 0 0 0];
> > 	mac-encoding = "append-serial-number";
> > 
> That still does not specify where the remaining part of the MAC is
> stored and how it should be retrieved.

I'm suggesting that you define a string that means something specific;
that hopefully can be shared by multiple platforms.  For example,
"append-serial-number" might mean start with the values selected by
AND of local-mac-address and local-mac-mask, and OR in the board's
serial number.  You would need to define something that worked if this
was the solution you used.

> > Okay, if so then it would be wise to have a reliable function for the
> > MAC driver to call to lookup it's address as determined by platform
> > code.  Alternately, the platform code can write the correct mac
> > address into the device tree node at init time (see
> > prom_update_property() and prom_add_property()).
> > 
> That sounds good. Didn't know about those functions. That could be
> used to mimic the current behaviour of supplying the MAC via
> platform_data.

I'm okay with doing this; but make sure you remove the bogus
local-mac-address from the .dts file.

g.



From mchehab at redhat.com  Mon Mar 19 18:03:29 2012
From: mchehab at redhat.com (Mauro Carvalho Chehab)
Date: Mon, 19 Mar 2012 19:03:29 -0300
Subject: [PATCH v1] i.MX35-PDK: Add Camera support
In-Reply-To: <1331651129-30540-1-git-send-email-alexg@meprolight.com>
References: <1331651129-30540-1-git-send-email-alexg@meprolight.com>
Message-ID: <4F67AD31.8030500@redhat.com>

Em 13-03-2012 12:05, Alex Gershgorin escreveu:
> In i.MX35-PDK, OV2640  camera is populated on the
> personality board. This camera is registered as a subdevice via soc-camera interface.
> 
> Signed-off-by: Alex Gershgorin <alexg at meprolight.com>

Patch doesn't apply over v3.3:

patching file arch/arm/mach-imx/mach-mx35_3ds.c
Hunk #3 FAILED at 149.
Hunk #4 succeeded at 126 with fuzz 1 (offset -55 lines).
Hunk #5 FAILED at 323.
Hunk #6 succeeded at 277 (offset -57 lines).
Hunk #7 succeeded at 293 (offset -57 lines).
2 out of 7 hunks FAILED -- saving rejects to file arch/arm/mach-imx/mach-mx35_3ds.c.rej
 arch/arm/mach-imx/mach-mx35_3ds.c |   87 ++++++++++++++++++++++++++++++++++++++


> ---
>  arch/arm/mach-imx/mach-mx35_3ds.c |   96 +++++++++++++++++++++++++++++++++++++
>  1 files changed, 96 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
> index 0af6c9c..a7dd8e6 100644
> --- a/arch/arm/mach-imx/mach-mx35_3ds.c
> +++ b/arch/arm/mach-imx/mach-mx35_3ds.c
> @@ -4,6 +4,11 @@
>   *
>   * Author: Fabio Estevam <fabio.estevam at freescale.com>
>   *
> + * Copyright (C) 2011 Meprolight, Ltd.
> + * Alex Gershgorin <alexg at meprolight.com>
> + *
> + * Modified from i.MX31 3-Stack Development System
> + *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License as published by
>   * the Free Software Foundation; either version 2 of the License, or
> @@ -34,6 +39,7 @@
>  #include <asm/mach/arch.h>
>  #include <asm/mach/time.h>
>  #include <asm/mach/map.h>
> +#include <asm/memblock.h>
>  
>  #include <mach/hardware.h>
>  #include <mach/common.h>
> @@ -41,6 +47,8 @@
>  #include <mach/irqs.h>
>  #include <mach/3ds_debugboard.h>
>  
> +#include <media/soc_camera.h>
> +
>  #include "devices-imx35.h"
>  
>  #define EXPIO_PARENT_INT	gpio_to_irq(IMX_GPIO_NR(1, 1))
> @@ -120,6 +128,83 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
>  	/* I2C1 */
>  	MX35_PAD_I2C1_CLK__I2C1_SCL,
>  	MX35_PAD_I2C1_DAT__I2C1_SDA,
> +	/* CSI */
> +	MX35_PAD_TX1__IPU_CSI_D_6,
> +	MX35_PAD_TX0__IPU_CSI_D_7,
> +	MX35_PAD_CSI_D8__IPU_CSI_D_8,
> +	MX35_PAD_CSI_D9__IPU_CSI_D_9,
> +	MX35_PAD_CSI_D10__IPU_CSI_D_10,
> +	MX35_PAD_CSI_D11__IPU_CSI_D_11,
> +	MX35_PAD_CSI_D12__IPU_CSI_D_12,
> +	MX35_PAD_CSI_D13__IPU_CSI_D_13,
> +	MX35_PAD_CSI_D14__IPU_CSI_D_14,
> +	MX35_PAD_CSI_D15__IPU_CSI_D_15,
> +	MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC,
> +	MX35_PAD_CSI_MCLK__IPU_CSI_MCLK,
> +	MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK,
> +	MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC,
> +};
> +
> +/*
> + * Camera support
> +*/
> +static phys_addr_t mx3_camera_base __initdata;
> +#define MX35_3DS_CAMERA_BUF_SIZE SZ_8M
> +
> +static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = {
> +	.flags = MX3_CAMERA_DATAWIDTH_8,
> +	.mclk_10khz = 2000,
> +};
> +
> +static int __init imx35_3ds_init_camera(void)
> +{
> +	int dma, ret = -ENOMEM;
> +	struct platform_device *pdev =
> +		imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata);
> +
> +	if (IS_ERR(pdev))
> +		return PTR_ERR(pdev);
> +
> +	if (!mx3_camera_base)
> +		goto err;
> +
> +	dma = dma_declare_coherent_memory(&pdev->dev,
> +					mx3_camera_base, mx3_camera_base,
> +					MX35_3DS_CAMERA_BUF_SIZE,
> +					DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
> +
> +	if (!(dma & DMA_MEMORY_MAP))
> +		goto err;
> +
> +	ret = platform_device_add(pdev);
> +	if (ret)
> +err:
> +		platform_device_put(pdev);
> +
> +	return ret;
> +}
> +
> +static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = {
> +	.irq_base = MXC_IPU_IRQ_START,
> +};
> +
> +static struct i2c_board_info mx35_3ds_i2c_camera = {
> +	I2C_BOARD_INFO("ov2640", 0x30),
> +};
> +
> +static struct soc_camera_link iclink_ov2640 = {
> +	.bus_id		= 0,
> +	.board_info	= &mx35_3ds_i2c_camera,
> +	.i2c_adapter_id	= 0,
> +	.power		= NULL,
> +};
> +
> +static struct platform_device mx35_3ds_ov2640 = {
> +	.name	= "soc-camera-pdrv",
> +	.id	= 0,
> +	.dev	= {
> +		.platform_data = &iclink_ov2640,
> +	},
>  };
>  
>  static int mx35_3ds_otg_init(struct platform_device *pdev)
> @@ -204,6 +289,9 @@ static void __init mx35_3ds_init(void)
>  		pr_warn("Init of the debugboard failed, all "
>  				"devices on the debugboard are unusable.\n");
>  	imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
> +	imx35_add_ipu_core(&mx35_3ds_ipu_data);
> +	platform_device_register(&mx35_3ds_ov2640);
> +	imx35_3ds_init_camera();
>  }
>  
>  static void __init mx35pdk_timer_init(void)
> @@ -215,6 +303,13 @@ struct sys_timer mx35pdk_timer = {
>  	.init	= mx35pdk_timer_init,
>  };
>  
> +static void __init mx35_3ds_reserve(void)
> +{
> +	/* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
> +	mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE,
> +					 MX35_3DS_CAMERA_BUF_SIZE);
> +}
> +
>  MACHINE_START(MX35_3DS, "Freescale MX35PDK")
>  	/* Maintainer: Freescale Semiconductor, Inc */
>  	.atag_offset = 0x100,
> @@ -224,5 +319,6 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
>  	.handle_irq = imx35_handle_irq,
>  	.timer = &mx35pdk_timer,
>  	.init_machine = mx35_3ds_init,
> +	.reserve = mx35_3ds_reserve,
>  	.restart	= mxc_restart,
>  MACHINE_END



From swarren at wwwdotorg.org  Mon Mar 19 18:06:51 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 16:06:51 -0600
Subject: [PATCH 1/4 v7] pinctrl: introduce generic pin config
In-Reply-To: <1331586859-15619-1-git-send-email-linus.walleij@stericsson.com>
References: <1331586859-15619-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <4F67ADFB.6000608@wwwdotorg.org>

On 03/12/2012 03:14 PM, Linus Walleij wrote:
> From: Linus Walleij <linus.walleij at linaro.org>
> 
> This is a split-off from the earlier patch set which adds generic
> pin configuration for the pin controllers that want it. Since
> we may have a system with mixed generic and custom pin controllers,
> we pass a boolean in the pin controller ops vtable to indicate
> if it is generic.
> 
> ChangeLog v1->v5:
> - Follow parent patch versioning number system.
> - Document the semantic meaning of return values from pin config
>   get functions, so we can iterate over pins and check their
>   properties from debugfs as part of the generic config code.
> - Use proper cast functions in the generic debugfs pin config
>   file.
> - Expand generic config to optionally cover groups too.
> ChangeLog v5->v6:
> - Update to match underlying changes.
> ChangeLog v6->v7:
> - Drop DRIVE_OFF parameter, use bias high impedance for this
> - Delete argument for drive modes push-pull, od and os. These
>   are now just state transitions.
> - Delete slew rate rising/falling due to discussions on on
>   proper semantics
> - Drop config wakeup, struct irq_chip does this for now, add
>   back if need be.
> - Set PIN_CONFIG_END to 0x7fff making room for custom config
>   parameters from 0x8000 and up.
> - Prefix accessor functions with pinconf_

I think this is probably workable. I'm still not totally convinced that
it'll really turn out to be that "generic", but I guess we may as well
try it and see, so:

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From arnd at arndb.de  Mon Mar 19 18:09:43 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 19 Mar 2012 22:09:43 +0000
Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulator for
 first instance
In-Reply-To: <87mx7c5kzj.fsf@ti.com>
References: <1331080771-30687-1-git-send-email-khilman@ti.com>
 <201203192118.09286.arnd@arndb.de> <87mx7c5kzj.fsf@ti.com>
Message-ID: <201203192209.43906.arnd@arndb.de>

On Monday 19 March 2012, Kevin Hilman wrote:
> > On Wednesday 07 March 2012, Kevin Hilman wrote:
> >> commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
> >> regulators) added regulators which are registered during
> >> gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
> >> than one instance of the SMSC911x and result in attempting to register
> >> the same regulator more than once which causes a panic().
> >> 
> >> Fix this by only registering the regulator when the platform_data id
> >> field is zero, indicating its the first instance.
> >> 
> >> Cc: Matt Porter <mporter at ti.com>
> >> Signed-off-by: Kevin Hilman <khilman at ti.com>
> >
> > It seems that both Olof and I forgot to forward this one to Linus.
> >
> > If it's ok for you, I'll add it to the fixes branch for v3.4 now
> > and mark it for backporting to v3.3-stable.
> 
> A slightly different version of this is already in linux-next as commit
> bb60424af517d6e6148505fb5ef256caa91b5b43.
> 
> It was in your 'fixes' branch, and was merged by Olaf from Tony on 3/13:
> Merge branch 'fix-smsc911x-regulator' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
> 

Yes, I know it's in linux-next because I found it in the fixes branch.
That is the branch with stuff that should have gone into v3.3 :(

Is the bb60424af version ok? If I add a stable at vger.kernel.org tag in
there, it will obviously get a new changeset ID but I was not planning
on changing the contents to the version from the mailing list in case
that is different.

	Arnd


From mchehab at redhat.com  Mon Mar 19 18:17:27 2012
From: mchehab at redhat.com (Mauro Carvalho Chehab)
Date: Mon, 19 Mar 2012 19:17:27 -0300
Subject: [PATCH v1] i.MX35-PDK: Add Camera support
In-Reply-To: <4F67AD31.8030500@redhat.com>
References: <1331651129-30540-1-git-send-email-alexg@meprolight.com>
 <4F67AD31.8030500@redhat.com>
Message-ID: <4F67B077.5050300@redhat.com>

Em 19-03-2012 19:03, Mauro Carvalho Chehab escreveu:
> Em 13-03-2012 12:05, Alex Gershgorin escreveu:
>> In i.MX35-PDK, OV2640  camera is populated on the
>> personality board. This camera is registered as a subdevice via soc-camera interface.
>>
>> Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
> 
> Patch doesn't apply over v3.3:

Sorry, the previous version of this patch didn't apply. This compiles OK.

Sorry for the mess.

Anyway, it should be applied via arm subtree.

Regards,
Mauro

> 
> patching file arch/arm/mach-imx/mach-mx35_3ds.c
> Hunk #3 FAILED at 149.
> Hunk #4 succeeded at 126 with fuzz 1 (offset -55 lines).
> Hunk #5 FAILED at 323.
> Hunk #6 succeeded at 277 (offset -57 lines).
> Hunk #7 succeeded at 293 (offset -57 lines).
> 2 out of 7 hunks FAILED -- saving rejects to file arch/arm/mach-imx/mach-mx35_3ds.c.rej
>  arch/arm/mach-imx/mach-mx35_3ds.c |   87 ++++++++++++++++++++++++++++++++++++++
> 
> 
>> ---
>>  arch/arm/mach-imx/mach-mx35_3ds.c |   96 +++++++++++++++++++++++++++++++++++++
>>  1 files changed, 96 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
>> index 0af6c9c..a7dd8e6 100644
>> --- a/arch/arm/mach-imx/mach-mx35_3ds.c
>> +++ b/arch/arm/mach-imx/mach-mx35_3ds.c
>> @@ -4,6 +4,11 @@
>>   *
>>   * Author: Fabio Estevam <fabio.estevam at freescale.com>
>>   *
>> + * Copyright (C) 2011 Meprolight, Ltd.
>> + * Alex Gershgorin <alexg at meprolight.com>
>> + *
>> + * Modified from i.MX31 3-Stack Development System
>> + *
>>   * This program is free software; you can redistribute it and/or modify
>>   * it under the terms of the GNU General Public License as published by
>>   * the Free Software Foundation; either version 2 of the License, or
>> @@ -34,6 +39,7 @@
>>  #include <asm/mach/arch.h>
>>  #include <asm/mach/time.h>
>>  #include <asm/mach/map.h>
>> +#include <asm/memblock.h>
>>  
>>  #include <mach/hardware.h>
>>  #include <mach/common.h>
>> @@ -41,6 +47,8 @@
>>  #include <mach/irqs.h>
>>  #include <mach/3ds_debugboard.h>
>>  
>> +#include <media/soc_camera.h>
>> +
>>  #include "devices-imx35.h"
>>  
>>  #define EXPIO_PARENT_INT	gpio_to_irq(IMX_GPIO_NR(1, 1))
>> @@ -120,6 +128,83 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
>>  	/* I2C1 */
>>  	MX35_PAD_I2C1_CLK__I2C1_SCL,
>>  	MX35_PAD_I2C1_DAT__I2C1_SDA,
>> +	/* CSI */
>> +	MX35_PAD_TX1__IPU_CSI_D_6,
>> +	MX35_PAD_TX0__IPU_CSI_D_7,
>> +	MX35_PAD_CSI_D8__IPU_CSI_D_8,
>> +	MX35_PAD_CSI_D9__IPU_CSI_D_9,
>> +	MX35_PAD_CSI_D10__IPU_CSI_D_10,
>> +	MX35_PAD_CSI_D11__IPU_CSI_D_11,
>> +	MX35_PAD_CSI_D12__IPU_CSI_D_12,
>> +	MX35_PAD_CSI_D13__IPU_CSI_D_13,
>> +	MX35_PAD_CSI_D14__IPU_CSI_D_14,
>> +	MX35_PAD_CSI_D15__IPU_CSI_D_15,
>> +	MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC,
>> +	MX35_PAD_CSI_MCLK__IPU_CSI_MCLK,
>> +	MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK,
>> +	MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC,
>> +};
>> +
>> +/*
>> + * Camera support
>> +*/
>> +static phys_addr_t mx3_camera_base __initdata;
>> +#define MX35_3DS_CAMERA_BUF_SIZE SZ_8M
>> +
>> +static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = {
>> +	.flags = MX3_CAMERA_DATAWIDTH_8,
>> +	.mclk_10khz = 2000,
>> +};
>> +
>> +static int __init imx35_3ds_init_camera(void)
>> +{
>> +	int dma, ret = -ENOMEM;
>> +	struct platform_device *pdev =
>> +		imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata);
>> +
>> +	if (IS_ERR(pdev))
>> +		return PTR_ERR(pdev);
>> +
>> +	if (!mx3_camera_base)
>> +		goto err;
>> +
>> +	dma = dma_declare_coherent_memory(&pdev->dev,
>> +					mx3_camera_base, mx3_camera_base,
>> +					MX35_3DS_CAMERA_BUF_SIZE,
>> +					DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
>> +
>> +	if (!(dma & DMA_MEMORY_MAP))
>> +		goto err;
>> +
>> +	ret = platform_device_add(pdev);
>> +	if (ret)
>> +err:
>> +		platform_device_put(pdev);
>> +
>> +	return ret;
>> +}
>> +
>> +static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = {
>> +	.irq_base = MXC_IPU_IRQ_START,
>> +};
>> +
>> +static struct i2c_board_info mx35_3ds_i2c_camera = {
>> +	I2C_BOARD_INFO("ov2640", 0x30),
>> +};
>> +
>> +static struct soc_camera_link iclink_ov2640 = {
>> +	.bus_id		= 0,
>> +	.board_info	= &mx35_3ds_i2c_camera,
>> +	.i2c_adapter_id	= 0,
>> +	.power		= NULL,
>> +};
>> +
>> +static struct platform_device mx35_3ds_ov2640 = {
>> +	.name	= "soc-camera-pdrv",
>> +	.id	= 0,
>> +	.dev	= {
>> +		.platform_data = &iclink_ov2640,
>> +	},
>>  };
>>  
>>  static int mx35_3ds_otg_init(struct platform_device *pdev)
>> @@ -204,6 +289,9 @@ static void __init mx35_3ds_init(void)
>>  		pr_warn("Init of the debugboard failed, all "
>>  				"devices on the debugboard are unusable.\n");
>>  	imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
>> +	imx35_add_ipu_core(&mx35_3ds_ipu_data);
>> +	platform_device_register(&mx35_3ds_ov2640);
>> +	imx35_3ds_init_camera();
>>  }
>>  
>>  static void __init mx35pdk_timer_init(void)
>> @@ -215,6 +303,13 @@ struct sys_timer mx35pdk_timer = {
>>  	.init	= mx35pdk_timer_init,
>>  };
>>  
>> +static void __init mx35_3ds_reserve(void)
>> +{
>> +	/* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
>> +	mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE,
>> +					 MX35_3DS_CAMERA_BUF_SIZE);
>> +}
>> +
>>  MACHINE_START(MX35_3DS, "Freescale MX35PDK")
>>  	/* Maintainer: Freescale Semiconductor, Inc */
>>  	.atag_offset = 0x100,
>> @@ -224,5 +319,6 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
>>  	.handle_irq = imx35_handle_irq,
>>  	.timer = &mx35pdk_timer,
>>  	.init_machine = mx35_3ds_init,
>> +	.reserve = mx35_3ds_reserve,
>>  	.restart	= mxc_restart,
>>  MACHINE_END
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-media" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



From stigge at antcom.de  Mon Mar 19 18:26:21 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 19 Mar 2012 23:26:21 +0100
Subject: [PATCH] USB: gadget driver for LPC32xx
In-Reply-To: <201203192130.13583.arnd@arndb.de>
References: <1332191930-2433-1-git-send-email-stigge@antcom.de>
 <201203192130.13583.arnd@arndb.de>
Message-ID: <4F67B28D.3060500@antcom.de>

Hi Arnd,

On 19/03/12 22:30, Arnd Bergmann wrote:
> There is already a driver for the isp1301 otg part in the kernel, I don't
> think we want to add another one.
> 
> From what I can tell, this shares a common ancestry with the omap version
> but has diverged quite a bit. The best solution would really be to
> bring the two back together and let them share a common base driver,
> with the lpc32xx and omap specific bits in another file.

Yes, it's a good idea to share code where possible and consolidate into
one driver.

Please consider:

The LPC32xx driver is actually using only 3 functions via isp1301:

isp1301_udc_configure()
isp1301_set_powerstate()
isp1301_pullup_set()

The first of those is LPC32xx specific. The power setting function is
also done differently in isp1301_omap's power_up()/power_down() ("board
specific"). For the pullups, there is not (yet?) a dedicated API in the
OMAP driver, but it's really only two small I2C commands.

Are you still sure it's worth it to use a common driver when there is
hardly shared code?

Maybe the right thing is a common low-level isp1301 interface defining
all the registers and providing low-level (I2C) access functions,
leaving all the "higher level"/"board specific" functions up to the
existing drivers?

(I guess you meant drivers/usb/otg/isp1301_omap.c ?)

Thanks in advance,

Roland


From s.hauer at pengutronix.de  Mon Mar 19 18:37:29 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 23:37:29 +0100
Subject: [PATCH v1] i.MX35-PDK: Add Camera support
In-Reply-To: <4F67B077.5050300@redhat.com>
References: <1331651129-30540-1-git-send-email-alexg@meprolight.com>
 <4F67AD31.8030500@redhat.com> <4F67B077.5050300@redhat.com>
Message-ID: <20120319223729.GC3852@pengutronix.de>

On Mon, Mar 19, 2012 at 07:17:27PM -0300, Mauro Carvalho Chehab wrote:
> Em 19-03-2012 19:03, Mauro Carvalho Chehab escreveu:
> > Em 13-03-2012 12:05, Alex Gershgorin escreveu:
> >> In i.MX35-PDK, OV2640  camera is populated on the
> >> personality board. This camera is registered as a subdevice via soc-camera interface.
> >>
> >> Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
> > 
> > Patch doesn't apply over v3.3:
> 
> Sorry, the previous version of this patch didn't apply. This compiles OK.
> 
> Sorry for the mess.
> 
> Anyway, it should be applied via arm subtree.

It's scheduled there. I should have responded with an applied message.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From festevam at gmail.com  Mon Mar 19 18:43:32 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 19 Mar 2012 19:43:32 -0300
Subject: [PATCH v1] i.MX35-PDK: Add Camera support
In-Reply-To: <20120319223729.GC3852@pengutronix.de>
References: <1331651129-30540-1-git-send-email-alexg@meprolight.com>
 <4F67AD31.8030500@redhat.com> <4F67B077.5050300@redhat.com>
 <20120319223729.GC3852@pengutronix.de>
Message-ID: <CAOMZO5B=Qpng68xLmxGaHMqSmYzbkpObVcjHDQSXaXcz5s6gMQ@mail.gmail.com>

Hi Sascha,

On Mon, Mar 19, 2012 at 7:37 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:

> It's scheduled there. I should have responded with an applied message.

Please apply this one too: http://patchwork.ozlabs.org/patch/144942/

Otherwise camera device cannot register.


From s.hauer at pengutronix.de  Mon Mar 19 18:45:50 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 19 Mar 2012 23:45:50 +0100
Subject: [PATCH v1] i.MX35-PDK: Add Camera support
In-Reply-To: <CAOMZO5B=Qpng68xLmxGaHMqSmYzbkpObVcjHDQSXaXcz5s6gMQ@mail.gmail.com>
References: <1331651129-30540-1-git-send-email-alexg@meprolight.com>
 <4F67AD31.8030500@redhat.com> <4F67B077.5050300@redhat.com>
 <20120319223729.GC3852@pengutronix.de>
 <CAOMZO5B=Qpng68xLmxGaHMqSmYzbkpObVcjHDQSXaXcz5s6gMQ@mail.gmail.com>
Message-ID: <20120319224550.GF3852@pengutronix.de>

On Mon, Mar 19, 2012 at 07:43:32PM -0300, Fabio Estevam wrote:
> Hi Sascha,
> 
> On Mon, Mar 19, 2012 at 7:37 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> 
> > It's scheduled there. I should have responded with an applied message.
> 
> Please apply this one too: http://patchwork.ozlabs.org/patch/144942/
> 

Will do.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From tony at atomide.com  Mon Mar 19 18:48:59 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 19 Mar 2012 15:48:59 -0700
Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulator
 for first instance
In-Reply-To: <201203192209.43906.arnd@arndb.de>
References: <1331080771-30687-1-git-send-email-khilman@ti.com>
 <201203192118.09286.arnd@arndb.de> <87mx7c5kzj.fsf@ti.com>
 <201203192209.43906.arnd@arndb.de>
Message-ID: <20120319224858.GD9859@atomide.com>

* Arnd Bergmann <arnd at arndb.de> [120319 15:12]:
> On Monday 19 March 2012, Kevin Hilman wrote:
> > > On Wednesday 07 March 2012, Kevin Hilman wrote:
> > >> commit e4b0b2cbbb (ARM: OMAP2+: gpmc-smsc911x: add required smsc911x
> > >> regulators) added regulators which are registered during
> > >> gpmc_smsc911x_init().  However, some platforms (OMAP3/Overo) have more
> > >> than one instance of the SMSC911x and result in attempting to register
> > >> the same regulator more than once which causes a panic().
> > >> 
> > >> Fix this by only registering the regulator when the platform_data id
> > >> field is zero, indicating its the first instance.
> > >> 
> > >> Cc: Matt Porter <mporter at ti.com>
> > >> Signed-off-by: Kevin Hilman <khilman at ti.com>
> > >
> > > It seems that both Olof and I forgot to forward this one to Linus.
> > >
> > > If it's ok for you, I'll add it to the fixes branch for v3.4 now
> > > and mark it for backporting to v3.3-stable.
> > 
> > A slightly different version of this is already in linux-next as commit
> > bb60424af517d6e6148505fb5ef256caa91b5b43.
> > 
> > It was in your 'fixes' branch, and was merged by Olaf from Tony on 3/13:
> > Merge branch 'fix-smsc911x-regulator' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
> > 
> 
> Yes, I know it's in linux-next because I found it in the fixes branch.
> That is the branch with stuff that should have gone into v3.3 :(
> 
> Is the bb60424af version ok? If I add a stable at vger.kernel.org tag in
> there, it will obviously get a new changeset ID but I was not planning
> on changing the contents to the version from the mailing list in case
> that is different.

Let's just keep bb60424af. There are more patches needed to make
multiple smsc91x instances work, but we need to hear from people
with such boards first. Then those can be tagged for stable.

Regards,

Tony


From mchehab at redhat.com  Mon Mar 19 18:49:51 2012
From: mchehab at redhat.com (Mauro Carvalho Chehab)
Date: Mon, 19 Mar 2012 19:49:51 -0300
Subject: [PATCH v1] i.MX35-PDK: Add Camera support
In-Reply-To: <20120319223729.GC3852@pengutronix.de>
References: <1331651129-30540-1-git-send-email-alexg@meprolight.com>
 <4F67AD31.8030500@redhat.com> <4F67B077.5050300@redhat.com>
 <20120319223729.GC3852@pengutronix.de>
Message-ID: <4F67B80F.1040204@redhat.com>

Em 19-03-2012 19:37, Sascha Hauer escreveu:
> On Mon, Mar 19, 2012 at 07:17:27PM -0300, Mauro Carvalho Chehab wrote:
>> Em 19-03-2012 19:03, Mauro Carvalho Chehab escreveu:
>>> Em 13-03-2012 12:05, Alex Gershgorin escreveu:
>>>> In i.MX35-PDK, OV2640  camera is populated on the
>>>> personality board. This camera is registered as a subdevice via soc-camera interface.
>>>>
>>>> Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
>>>
>>> Patch doesn't apply over v3.3:
>>
>> Sorry, the previous version of this patch didn't apply. This compiles OK.
>>
>> Sorry for the mess.
>>
>> Anyway, it should be applied via arm subtree.
> 
> It's scheduled there. I should have responded with an applied message.

Ok, thanks! 

Regards,
Mauro


From b-cousson at ti.com  Mon Mar 19 18:58:01 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Mon, 19 Mar 2012 23:58:01 +0100
Subject: [PATCH v2 0/4] ARM: OMAP: boards: changes to support dynamic
 irq alloc
In-Reply-To: <20120319191743.GB9859@atomide.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
 <20120319191743.GB9859@atomide.com>
Message-ID: <4F67B9F9.1030906@ti.com>

Hi Tony,

On 3/19/2012 8:17 PM, Tony Lindgren wrote:
> * Tarun Kanti DebBarma<tarun.kanti at ti.com>  [120319 05:09]:
>> These two patches incorporate changes to OMAP1 and OMAP2 platforms
>> board files whereby older references to OMAP_GPIO_IRQ macro are
>> now replaced with gpio_to_irq(), thereby getting rid of static
>> irq references.
>>
>> Reference: git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git omap/dt
>> Commit: 9a0cee711448335ec43eae83272495e9334c0098
>
> Can you please tell the exact two commits causing this
> breakage?

Well, this is the GPIO DT + SPARSE_IRQ series I have done. It appears 
that the boards I have were already using properly gpio_to_irq() and 
thus were working fine with this series.

But this is unfortunately not the case of most OMAP2 and 3 legacy boards 
that were still using an old OMAP way of converting GPIO to IRQ and were 
never modified to take advantage of the gpiolib stuff.

So if these patches are apply before the GPIO DT + SPARSE_IRQ series, 
there will be no breakage at all.

All the cleanup we have never done before will hurt us at some point 
when we will start using more extensively newer fmwk (DT, sparse_irq, 
dmaengine...). It was not done on purpose, but this GPIO series 
highlighted this remaining static broken mapping inside OMAP boards.

> I'm baffled how despite all the effort for previnting
> issues like this this still happen. These all seem valid
> fixes and clean up things, but how come this was not seen
> earlier?

Maybe because there are much more boards inside mach-omap2 directory 
than inside my cubicle... :-(

Regards,
Benoit


From sylvester.nawrocki at gmail.com  Mon Mar 19 19:12:56 2012
From: sylvester.nawrocki at gmail.com (Sylwester Nawrocki)
Date: Tue, 20 Mar 2012 00:12:56 +0100
Subject: [PATCH 01/11] drivercore: Add driver probe deferral mechanism
In-Reply-To: <1331218291-16119-2-git-send-email-thierry.reding@avionic-design.de>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-2-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F67BD78.8070202@gmail.com>

On 03/08/2012 03:51 PM, Thierry Reding wrote:
> From: Grant Likely<grant.likely at secretlab.ca>
>
> Allow drivers to report at probe time that they cannot get all the resources
> required by the device, and should be retried at a later time.
>
> This should completely solve the problem of getting devices
> initialized in the right order.  Right now this is mostly handled by
> mucking about with initcall ordering which is a complete hack, and
> doesn't even remotely handle the case where device drivers are in
> modules.  This approach completely sidesteps the issues by allowing
> driver registration to occur in any order, and any driver can request
> to be retried after a few more other drivers get probed.
>
> v4: - Integrate Manjunath's addition of a separate workqueue
>      - Change -EAGAIN to -EPROBE_DEFER for drivers to trigger deferral
>      - Update comment blocks to reflect how the code really works
> v3: - Hold off workqueue scheduling until late_initcall so that the bulk
>        of driver probes are complete before we start retrying deferred devices.
>      - Tested with simple use cases.  Still needs more testing though.
>        Using it to get rid of the gpio early_initcall madness, or to replace
>        the ASoC internal probe deferral code would be ideal.
> v2: - added locking so it should no longer be utterly broken in that regard
>      - remove device from deferred list at device_del time.
>      - Still completely untested with any real use case, but has been
>        boot tested.
>
> Signed-off-by: Grant Likely<grant.likely at secretlab.ca>
> [Cc list stripped in order not to get on people's nerves]
> ---
>   drivers/base/base.h    |    1 +
>   drivers/base/core.c    |    2 +
>   drivers/base/dd.c      |  138 +++++++++++++++++++++++++++++++++++++++++++++++-
>   include/linux/device.h |    5 ++
>   include/linux/errno.h  |    1 +
>   5 files changed, 146 insertions(+), 1 deletion(-)

Is this patch going to be included in v3.4 ? I can see it's in -next,
but not sure where I could check if its really queued for v3.4.
It would be nice to have it in v3.4, I've got already one more client
of this deferred probe infrastructure.

--

Thanks,
Sylwester


From tony at atomide.com  Mon Mar 19 19:39:11 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 19 Mar 2012 16:39:11 -0700
Subject: [PATCH v2 0/4] ARM: OMAP: boards: changes to support dynamic
 irq alloc
In-Reply-To: <4F67B9F9.1030906@ti.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
 <20120319191743.GB9859@atomide.com> <4F67B9F9.1030906@ti.com>
Message-ID: <20120319233910.GF9859@atomide.com>

* Cousson, Benoit <b-cousson at ti.com> [120319 16:00]:
> Hi Tony,
> 
> On 3/19/2012 8:17 PM, Tony Lindgren wrote:
> >* Tarun Kanti DebBarma<tarun.kanti at ti.com>  [120319 05:09]:
> >>These two patches incorporate changes to OMAP1 and OMAP2 platforms
> >>board files whereby older references to OMAP_GPIO_IRQ macro are
> >>now replaced with gpio_to_irq(), thereby getting rid of static
> >>irq references.
> >>
> >>Reference: git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git omap/dt
> >>Commit: 9a0cee711448335ec43eae83272495e9334c0098
> >
> >Can you please tell the exact two commits causing this
> >breakage?
> 
> Well, this is the GPIO DT + SPARSE_IRQ series I have done. It
> appears that the boards I have were already using properly
> gpio_to_irq() and thus were working fine with this series.
> 
> But this is unfortunately not the case of most OMAP2 and 3 legacy
> boards that were still using an old OMAP way of converting GPIO to
> IRQ and were never modified to take advantage of the gpiolib stuff.
> 
> So if these patches are apply before the GPIO DT + SPARSE_IRQ
> series, there will be no breakage at all.
> 
> All the cleanup we have never done before will hurt us at some point
> when we will start using more extensively newer fmwk (DT,
> sparse_irq, dmaengine...). It was not done on purpose, but this GPIO
> series highlighted this remaining static broken mapping inside OMAP
> boards.

Yes I understand. But still, which patch(s) cause the issue
so we can put that in the changelog for the fixes?
 
> >I'm baffled how despite all the effort for previnting
> >issues like this this still happen. These all seem valid
> >fixes and clean up things, but how come this was not seen
> >earlier?
> 
> Maybe because there are much more boards inside mach-omap2 directory
> than inside my cubicle... :-(

Well somehow we need to make sure that patches get properly
tested on a reasonable selection of boards. This pretty much
breaks things for 21 boards out of the 51 board-*.c files :(

Regards,

Tony


From boojin.kim at samsung.com  Mon Mar 19 20:05:20 2012
From: boojin.kim at samsung.com (Boojin Kim)
Date: Tue, 20 Mar 2012 09:05:20 +0900
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <alpine.LFD.2.02.1203191002350.24151@xanadu.home>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <alpine.LFD.2.02.1203191002350.24151@xanadu.home>
Message-ID: <005801cd062d$24025500$6c06ff00$%kim@samsung.com>

Nicolas Pitre wrote:

> > This patch uses LDRD/STRD that loads and stores data as DWORD unit
> > for the copy of 8-words data.
> > It brings better performance than LDRM/STRM that was used originally.
> >
> > Signed-off-by: Boojin Kim <boojin.kim at samsung.com>
> > Cc: Russell King <rmk+kernel at arm.linux.org.uk>
>
> Firstly, you're breaking those CPUs without ldrd/strd support.
>
I loss the point. I will fix it on next patch.

> Secondly, you're breaking to_user/from_user copies when processor
> domains are not disabled.
Can you explain it in detail? Which one breaks the to_user/from_user copies?
Thank you for your reply.

>
> Then, my question is why didn't you simply provide an alternative
> implementation of ldr8w/str8w using ldrd/strd instead of interleaving
> them?  Certainly that would have allowed you to benefit from SDRAM burst
> transfers which are typically aligned to d-cache lines, as well as
> locating the subs into the unavoidable result delay slot.
>
> > ---
> >  arch/arm/lib/copy_from_user.S |   14 +++++++++-----
> >  arch/arm/lib/copy_template.S  |   10 ++++++----
> >  arch/arm/lib/copy_to_user.S   |   13 +++++++++----
> >  arch/arm/lib/memcpy.S         |   13 +++++++++----
> >  4 files changed, 33 insertions(+), 17 deletions(-)
> >
> > diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
> > index 66a477a..15d1e1c 100644
> > --- a/arch/arm/lib/copy_from_user.S
> > +++ b/arch/arm/lib/copy_from_user.S
> > @@ -51,11 +51,6 @@
> >  	ldr1w \ptr, \reg4, \abort
> >  	.endm
> >
> > -	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
> > -	ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
> > -	ldr4w \ptr, \reg5, \reg6, \reg7, \reg8, \abort
> > -	.endm
> > -
> >  	.macro ldr1b ptr reg cond=al abort
> >  	ldrusr	\reg, \ptr, 1, \cond, abort=\abort
> >  	.endm
> > @@ -68,6 +63,15 @@
> >  	stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
> >  	.endm
> >
> > +	.macro cpy8w dst src reg1 reg2 abort
> > +	.irp offset, #0, #8, #16, #24
> > +	ldr1w \src, \reg1, \abort
> > +	ldr1w \src, \reg2, \abort
> > +	strd \reg1, \reg2, [\dst, \offset]
> > +	.endr
> > +	add \dst, \dst, #32
> > +	.endm
> > +
> >  	.macro str1b ptr reg cond=al abort
> >  	str\cond\()b \reg, [\ptr], #1
> >  	.endm
> > diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
> > index 805e3f8..72640aa 100644
> > --- a/arch/arm/lib/copy_template.S
> > +++ b/arch/arm/lib/copy_template.S
> > @@ -28,9 +28,8 @@
> >   *	'ptr' to the next word. The 'abort' argument is used for fixup tables.
> >   *
> >   * ldr4w ptr reg1 reg2 reg3 reg4 abort
> > - * ldr8w ptr, reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
> >   *
> > - *	This loads four or eight words starting from 'ptr', stores them
> > + *	This loads eight words starting from 'ptr', stores them
> >   *	in provided registers and increments 'ptr' past those words.
> >   *	The'abort' argument is used for fixup tables.
> >   *
> > @@ -47,6 +46,10 @@
> >   *	Same as their ldr* counterparts, but data is stored to 'ptr' location
> >   *	rather than being loaded.
> >   *
> > + * cpy8w src dst reg1 reg2 abort
> > + *	This loads eight words starting from 'src' and stores them to 'dst'.
> > + *	The 'abort' argument is used for fixup tables.
> > + *
> >   * enter reg1 reg2
> >   *
> >   *	Preserve the provided registers on the stack plus any additional
> > @@ -97,9 +100,8 @@
> >  	PLD(	pld	[r1, #92]		)
> >
> >  3:	PLD(	pld	[r1, #124]		)
> > -4:		ldr8w	r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> > +4:		cpy8w   r0, r1, r4, r5, abort=20f
> >  		subs	r2, r2, #32
> > -		str8w	r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> >  		bge	3b
> >  	PLD(	cmn	r2, #96			)
> >  	PLD(	bge	4b			)
> > diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
> > index d066df6..9402a08 100644
> > --- a/arch/arm/lib/copy_to_user.S
> > +++ b/arch/arm/lib/copy_to_user.S
> > @@ -48,10 +48,6 @@
> >  	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
> >  	.endm
> >
> > -	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
> > -	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
> > -	.endm
> > -
> >  	.macro ldr1b ptr reg cond=al abort
> >  	ldr\cond\()b \reg, [\ptr], #1
> >  	.endm
> > @@ -71,6 +67,15 @@
> >  	str1w \ptr, \reg8, \abort
> >  	.endm
> >
> > +	.macro cpy8w dst src reg1 reg2 abort
> > +	.irp offset, #0, #8, #16, #24
> > +	ldrd \reg1, \reg2, [\src, \offset]
> > +	str1w \dst, \reg1, \abort
> > +	str1w \dst, \reg2, \abort
> > +	.endr
> > +	add \src, \src, #32
> > +	.endm
> > +
> >  	.macro str1b ptr reg cond=al abort
> >  	strusr	\reg, \ptr, 1, \cond, abort=\abort
> >  	.endm
> > diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
> > index a9b9e22..25320c9 100644
> > --- a/arch/arm/lib/memcpy.S
> > +++ b/arch/arm/lib/memcpy.S
> > @@ -24,10 +24,6 @@
> >  	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
> >  	.endm
> >
> > -	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
> > -	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
> > -	.endm
> > -
> >  	.macro ldr1b ptr reg cond=al abort
> >  	ldr\cond\()b \reg, [\ptr], #1
> >  	.endm
> > @@ -40,6 +36,15 @@
> >  	stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
> >  	.endm
> >
> > +	.macro cpy8w dst src reg1 reg2 abort
> > +	.irp offset, #0, #8, #16, #24
> > +	ldrd \reg1, \reg2, [\src, \offset]
> > +	strd \reg1, \reg2, [\dst, \offset]
> > +	.endr
> > +	add \src, \src, #32
> > +	add \dst, \dst, #32
> > +	.endm
> > +
> >  	.macro str1b ptr reg cond=al abort
> >  	str\cond\()b \reg, [\ptr], #1
> >  	.endm
> > --
> > 1.7.1
> >
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel




From khilman at ti.com  Mon Mar 19 20:15:43 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 19 Mar 2012 17:15:43 -0700
Subject: [PATCH] OMAP3: OPP: Test for IVA subsystem before attempting to
 add IVA OPP
In-Reply-To: <CAOMWX4cXwppGu_P2csWYtHJazpRNDz0W7xQcfyAcwqJ7SJodDA@mail.gmail.com>
 (Nishanth Menon's message of "Mon, 19 Mar 2012 16:29:40 -0500")
References: <8762e6et1u.fsf@ti.com>
 <5448984682E7954C9BFF27F747A9C6CA56D6A8@dolphin.TIGRIS.local>
 <20120316142034.GA22234@senorita.am.dhcp.ti.com>
 <87sjh45ljs.fsf@ti.com>
 <CAOMWX4cXwppGu_P2csWYtHJazpRNDz0W7xQcfyAcwqJ7SJodDA@mail.gmail.com>
Message-ID: <87r4wo3z68.fsf@ti.com>

"Menon, Nishanth" <nm at ti.com> writes:

> Kevin,
> [...]
>> Nishanth, can you collect the acks/tested-bys and repost and official
>> patch.
>>
>> I'll queue this up.
> Thanks. This is already done:
> http://marc.info/?l=linux-omap&m=133191481703750&w=2

Yeah, sorry for the noise.  I saw it after I sent this request.

Kevin


From boojin.kim at samsung.com  Mon Mar 19 20:21:01 2012
From: boojin.kim at samsung.com (Boojin Kim)
Date: Tue, 20 Mar 2012 09:21:01 +0900
Subject: [PATCH] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <4F674479.8090101@gmail.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <20120319085503.GL15988@n2100.arm.linux.org.uk> <4F674479.8090101@gmail.com>
Message-ID: <005901cd062f$54ad5e50$fe081af0$%kim@samsung.com>

Rob Herring wrote:


> On 03/19/2012 03:55 AM, Russell King - ARM Linux wrote:
> > On Mon, Mar 19, 2012 at 04:02:48PM +0900, Boojin Kim wrote:
> >> This patch uses LDRD/STRD that loads and stores data as DWORD unit
> >> for the copy of 8-words data.
> >> It brings better performance than LDRM/STRM that was used originally.
> >
> > And what about CPUs that don't have ldrd/strd ?
> >
>
> And what about CPUs that do have ldrd/strd but is slower than ldm/stm?
> I'm pretty sure that is almost everything currently out there.

Actually I didn't measure the memcpy performance on all ARM SoCs.
I just measured it with internal memcpy() benchmark on Cortex-A9 and Cortex-A15.
ldrd/strd is faster than ldm/stm on cortex-a15.
And it's similar on cortex-a9.
I will try again this patch gives meaningful effect to the targeted ARM SoCs

Thank you for your reply.
>
> Rob
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel




From khilman at ti.com  Mon Mar 19 20:37:07 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 19 Mar 2012 17:37:07 -0700
Subject: [PATCH v4 00/12] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com> (Tarun
 Kanti DebBarma's message of "Fri, 16 Mar 2012 19:35:48 +0530")
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <87aa3c3y6k.fsf@ti.com>

Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:

> The cleanup is mostly getting rid of redundant fields in struct gpio_bank{}
> as we already have them as part of bank->context now. Also, remove un-used
> variable from gpio_irq_handler. Also, the suspend/resume callbacks are
> removed bacause they are not needed any more.

OK.

> The fixes include correction of _set_gpio_irqenable() implementation,
> missing wakeup_en register update in set_gpio_wakeup(), type mismatch
> of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
> register update in set_gpio_dataout_() and few corrections in context
> save logic.

These fixes need to be separated out from the cleanups and prepared for
v3.4-rc.  We need these as standlone fixes (indepenent of the cleanups)
so they can be applied for 3.4-rc.  The rest of the cleanups will have
to wait until 3.5.

> It is baselined on top of:
> git://git.secretlab.ca/git/linux-2.6.git gpio/next
> Commit: 81b279d80a63628e580c71a31d30a8c3b3047ad4
>
> Series is available here for reference:
> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_more_cleanup_fixes
>
> Power Test: 
> Off-mode and Retention on OMAP3430 (Suspend and Idle paths).
> Also confirmed that dataout register content preserved over
> off-mode.

I've confirmed these fixes also correct off-mode GPIO ouptut glitches
that I was seeing on n900.

Kevin


From swarren at wwwdotorg.org  Mon Mar 19 21:55:27 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 19:55:27 -0600
Subject: [PATCH v4 01/10] PWM: add pwm framework support
In-Reply-To: <1331740593-10807-2-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-2-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F67E38F.6080300@wwwdotorg.org>

On 03/14/2012 09:56 AM, Thierry Reding wrote:
> From: Sascha Hauer <s.hauer at pengutronix.de>
> 
> This patch adds framework support for PWM (pulse width modulation) devices.
...
> diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
...
> +/**
> + * pwmchip_add() - register a new pwm
> + * @chip: the pwm
> + *
> + * register a new pwm. pwm->pwm_id must be initialized. if pwm_id < 0 then
> + * a dynamically assigned id will be used, otherwise the id specified,
> + */

I don't see anywhere in the code that implements "if pwm_id < 0 then a
dynamically assigned id will be used".


From stern at rowland.harvard.edu  Mon Mar 19 21:56:35 2012
From: stern at rowland.harvard.edu (Alan Stern)
Date: Mon, 19 Mar 2012 21:56:35 -0400 (EDT)
Subject: [PATCH] USB: gadget driver for LPC32xx
In-Reply-To: <1332191930-2433-1-git-send-email-stigge@antcom.de>
Message-ID: <Pine.LNX.4.44L0.1203192155150.24735-100000@netrider.rowland.org>

On Mon, 19 Mar 2012, Roland Stigge wrote:

> This patch adds a USB gadget driver.
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

...

> +static const struct usb_ep_ops lpc32xx_ep_ops = {
> +	.enable		= lpc32xx_ep_enable,
> +	.disable	= lpc32xx_ep_disable,
> +	.alloc_request	= lpc32xx_ep_alloc_request,
> +	.free_request	= lpc32xx_ep_free_request,
> +	.queue		= lpc32xx_ep_queue,
> +	.dequeue	= lpc32xx_ep_dequeue,
> +	.set_halt	= lpc32xx_ep_set_halt,
> +};

You have not implemented the set_wedge method, which is needed for the 
file-storage gadgets.

Alan Stern



From swarren at wwwdotorg.org  Mon Mar 19 22:12:51 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 20:12:51 -0600
Subject: [PATCH v4 03/10] pwm: Add device tree support
In-Reply-To: <1331740593-10807-4-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-4-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F67E7A3.3090603@wwwdotorg.org>

On 03/14/2012 09:56 AM, Thierry Reding wrote:
> This patch adds helpers to support device tree bindings for the generic
> PWM API. Device tree binding documentation for PWM controllers is also
> provided.
...
> +static struct pwm_device *of_pwm_simple_xlate(struct pwm_chip *pc,
> +					      const struct of_phandle_args *args)
...
> +	if (args->args_count < pc->of_pwm_n_cells)
> +		return ERR_PTR(-EINVAL);

I think you can drop that error-check given the code quoted below?

(and if not, shouldn't it be != not >= ?)

> +struct pwm_device *of_pwm_request(struct device_node *np,
> +				  const char *propname, int index)
...
> +	if (args.args_count != pc->of_pwm_n_cells) {
> +		pr_debug("%s: wrong #pwm-cells for %s\n", np->full_name,
> +			 args.np->full_name);
> +		pwm = ERR_PTR(-EINVAL);
> +		goto put;
> +	}
> +
> +	pwm = pc->of_xlate(pc, &args);


From swarren at wwwdotorg.org  Mon Mar 19 22:15:51 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 20:15:51 -0600
Subject: [PATCH v4 04/10] ARM: tegra: Fix PWM clock programming
In-Reply-To: <1331740593-10807-5-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-5-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F67E857.9050402@wwwdotorg.org>

On 03/14/2012 09:56 AM, Thierry Reding wrote:
> From: Simon Que <sque at chromium.org>
> 
> PWM clock source registers in Tegra 2 have different clock source selection bit
> fields than other registers.  PWM clock source bits in CLK_SOURCE_PWM_0 register
> are located at bit field bit[30:28] while others are at bit field bit[31:30] in
> their respective clock source register.
> 
> This patch updates the clock programming to correctly reflect that, by adding a
> flag to indicate the alternate bit field format and checking for it when
> selecting a clock source (parent clock).
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> Signed-off-by: Bill Huang <bilhuang at nvidia.com>
> Signed-off-by: Simon Que <sque at chromium.org>

Acked-by: Stephen Warren <swarren at wwwdotorg.org>



From swarren at wwwdotorg.org  Mon Mar 19 22:18:12 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 20:18:12 -0600
Subject: [PATCH v4 05/10] ARM: tegra: Provide clock for only one PWM
 controller
In-Reply-To: <1331740593-10807-6-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-6-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F67E8E4.7000604@wwwdotorg.org>

On 03/14/2012 09:56 AM, Thierry Reding wrote:
> A subsequent patch will add a generic PWM API driver for the Tegra PWFM
> controller, supporting all four PWM devices with a single PWM chip. The
> device will be named tegra-pwm and only one clock needs to be provided.
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> Acked-by: Stephen Warren <swarren at nvidia.com>
...
> -	CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
> -	CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
> -	CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
> -	CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
> +	CLK_DUPLICATE("pwm", "tegra-pwm", NULL),

I thought harder about this: Why not delete /all/ the CLK_DUPLICATE()s
for PWM, and change the second parameter to PERIPH_CLK for PWM from
"pwm" to "tegra-pwm"?


From swarren at wwwdotorg.org  Mon Mar 19 22:35:20 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 20:35:20 -0600
Subject: [PATCH v4 06/10] pwm: Add NVIDIA Tegra SoC support
In-Reply-To: <1331740593-10807-7-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-7-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F67ECE8.8030307@wwwdotorg.org>

On 03/14/2012 09:56 AM, Thierry Reding wrote:
> This commit adds a generic PWM framework driver for the PWFM controller
> found on NVIDIA Tegra SoCs. The driver is based on code from the
> Chromium kernel tree and was originally written by Gary King (NVIDIA)
...
> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
...
> +static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
> +{
> +	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
> +	int rc = 0;
> +
> +	if (!pc->enable[pwm->hwpwm]) {

IIRC, the new PWM core only calls the enable() op for a disabled ->
enabled transition, so this driver probably doesn't need to check the
same thing, and you can get rid of tegra_pwm_chip.enable[] and have
tegra_pwm_config() read the enable flag from the core pwm device instead.

> +		rc = clk_enable(pc->clk);
> +		if (!rc) {
> +			unsigned long offset = pwm->hwpwm << 4;
> +			u32 val;
> +
> +			val = readl(pc->mmio_base + offset);
> +			val |= PWM_ENABLE;
> +			writel(val, pc->mmio_base + offset);

It seems a little of for the driver to define a pwm_writel() function
but only use it in some places but not others. I guess it's because in
some places the code knows the clock is on, so doesn't need the
clk_enable()/disable() helper in pwm_writel(), but I'd tend towards
always using pwm_readl()/pwm_writel() throughout the driver, and lifting
the clock management out of those low-level functions myself.

> +static int __devexit tegra_pwm_remove(struct platform_device *pdev)
> +{
> +	struct tegra_pwm_chip *pwm = platform_get_drvdata(pdev);
> +	int i;
> +
> +	if (WARN_ON(!pwm))
> +		return -ENODEV;
> +
> +	pwmchip_remove(&pwm->chip);
> +
> +	for (i = 0; i < NUM_PWM; i++) {
> +		pwm_writel(pwm, i, 0);
> +
> +		if (pwm->enable[i])
> +			clk_disable(pwm->clk);

Should the core call the disable() op before the remove() op so drivers
don't need to check this? I'm a little in two minds about this; if this
decision is deferred to drivers (as the code above assumes), then I
suppose the whole remove() path might be marginally more efficient.


From tarun.kanti at ti.com  Mon Mar 19 22:35:29 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Tue, 20 Mar 2012 08:05:29 +0530
Subject: [PATCH v4 00/12] gpio/omap: Some more driver cleanup and fixes
In-Reply-To: <87aa3c3y6k.fsf@ti.com>
References: <1331906760-5259-1-git-send-email-tarun.kanti@ti.com>
 <87aa3c3y6k.fsf@ti.com>
Message-ID: <CAC83ZvJnhnh-=Kwd4cuRvuCEKjgNWAdw2OK0_8GHb7_K6qk4mw@mail.gmail.com>

On Tue, Mar 20, 2012 at 6:07 AM, Kevin Hilman <khilman at ti.com> wrote:
> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>
>> The cleanup is mostly getting rid of redundant fields in struct gpio_bank{}
>> as we already have them as part of bank->context now. Also, remove un-used
>> variable from gpio_irq_handler. Also, the suspend/resume callbacks are
>> removed bacause they are not needed any more.
>
> OK.
>
>> The fixes include correction of _set_gpio_irqenable() implementation,
>> missing wakeup_en register update in set_gpio_wakeup(), type mismatch
>> of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
>> register update in set_gpio_dataout_() and few corrections in context
>> save logic.
>
> These fixes need to be separated out from the cleanups and prepared for
> v3.4-rc. ?We need these as standlone fixes (indepenent of the cleanups)
> so they can be applied for 3.4-rc. ?The rest of the cleanups will have
> to wait until 3.5.
Sure, I will separate out the fixes and prepare new series.

>
>> It is baselined on top of:
>> git://git.secretlab.ca/git/linux-2.6.git gpio/next
>> Commit: 81b279d80a63628e580c71a31d30a8c3b3047ad4
>>
>> Series is available here for reference:
>> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_more_cleanup_fixes
>>
>> Power Test:
>> Off-mode and Retention on OMAP3430 (Suspend and Idle paths).
>> Also confirmed that dataout register content preserved over
>> off-mode.
>
> I've confirmed these fixes also correct off-mode GPIO ouptut glitches
> that I was seeing on n900.
OK, thanks.
--
Tarun
>
> Kevin


From swarren at wwwdotorg.org  Mon Mar 19 22:42:34 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 20:42:34 -0600
Subject: [PATCH v4 07/10] pwm: tegra: Add device tree support
In-Reply-To: <1331740593-10807-8-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-8-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F67EE9A.6080101@wwwdotorg.org>

On 03/14/2012 09:56 AM, Thierry Reding wrote:
> Add auxdata to instantiate the PWFM controller from a device tree,
> include the corresponding nodes in the dtsi files for Tegra 20 and
> Tegra 30 and add binding documentation.
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>

> +++ b/Documentation/devicetree/bindings/pwm/tegra-pwm.txt

Can this please be named nvidia,tegra20-pwm.txt so that if we need
different bindings for any future Tegra PWM, we won't have any filename
conflicts?

Aside from that,

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From swarren at wwwdotorg.org  Mon Mar 19 22:59:59 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 19 Mar 2012 20:59:59 -0600
Subject: [PATCH v4 10/10] pwm-backlight: Add rudimentary device tree
 support
In-Reply-To: <1331740593-10807-11-git-send-email-thierry.reding@avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-11-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F67F2AF.3020404@wwwdotorg.org>

On 03/14/2012 09:56 AM, Thierry Reding wrote:
> This commit adds very basic support for device tree probing. Currently,
> only a PWM and a list of distinct brightness levels can be specified.
> Enabling or disabling backlight power via GPIOs is not yet supported.
> 
> A pointer to the exit() callback is stored in the driver data to keep it
> around until the driver is unloaded.

> +++ b/Documentation/devicetree/bindings/video/backlight/pwm-backlight

> +pwm-backlight bindings
> +
> +Required properties:
> +  - compatible: "pwm-backlight"
> +  - pwm: OF device-tree PWM specification
> +  - num-brightness-levels: number of distinct brightness levels
> +  - brightness-levels: array of distinct brightness levels

I assume the values in this array are 0 (darkest/off) to 255 (max
brightness)? The doc should probably specify this.

> +  - default-brightness-level: the default brightness level

Likewise, this is an index into the default-brightness-level? Again,
it'd be best to explicitly state this.

...
> +		brightness-levels = <0 4 8 16 32 64 128 255>;
> +		default-brightness-level = <6>;


> +static int pwm_backlight_parse_dt(struct device *dev,
> +				  struct platform_pwm_backlight_data *data)
...
> +		ret = of_property_read_u32(node, "default-brightness-level",
> +					   &value);
> +		if (ret < 0)
> +			goto free;

Range-check that against max_brightness?

>  static int pwm_backlight_probe(struct platform_device *pdev)
...
> -	pb->pwm = pwm_request(data->pwm_id, "backlight");
> -	if (IS_ERR(pb->pwm)) {
> -		dev_err(&pdev->dev, "unable to request PWM for backlight\n");
> -		ret = PTR_ERR(pb->pwm);
> -		goto err_alloc;
> -	} else
> -		dev_dbg(&pdev->dev, "got pwm for backlight\n");
> +	if (!pb->pwm) {
> +		pb->pwm = pwm_request(data->pwm_id, "backlight");
> +		if (IS_ERR(pb->pwm)) {
> +			dev_err(&pdev->dev, "unable to request PWM for backlight\n");
> +			ret = PTR_ERR(pb->pwm);
> +			goto err_alloc;
> +		} else
> +			dev_dbg(&pdev->dev, "got pwm for backlight\n");
> +	}

Hmmm. It'd be more consistent if pwm_backlight_parse_dt() called
something like of_pwm_get() instead of of_pwm_request(), so that this
code could always call pwm_request() on the PWM and hence operate the
same irrespective of DT vs non-DT. GPIOs work that way at least.


From festevam at gmail.com  Mon Mar 19 23:09:58 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Tue, 20 Mar 2012 00:09:58 -0300
Subject: [PATCH] ARM: mach-mx35_3ds: Fix build warning due to the lack of
 'const' annotation
Message-ID: <1332212998-6234-1-git-send-email-festevam@gmail.com>

Fix the following build warning:

arch/arm/mach-imx/mach-mx35_3ds.c: In function 'mx35_3ds_lcd_set_power':
arch/arm/mach-imx/mach-mx35_3ds.c:112: warning: passing argument 2 of 'gpiochip_find' from incompatible pointer type
include/asm-generic/gpio.h:145: note: expected 'int (*)(struct gpio_chip *, const void *)' but argument is of type 'int (*)(struct gpio_chip *, void *)'

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-imx/mach-mx35_3ds.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index e14291d..6ae51c6 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -97,7 +97,7 @@ static struct i2c_board_info __initdata i2c_devices_3ds[] = {
 static int lcd_power_gpio = -ENXIO;
 
 static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
-						     void *data)
+						     const void *data)
 {
 	return !strcmp(chip->label, data);
 }
-- 
1.7.1



From paul.liu at linaro.org  Mon Mar 19 23:28:59 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Tue, 20 Mar 2012 11:28:59 +0800
Subject: [PATCH] ARM: dts: imx6q: add anatop regulators
Message-ID: <1332214139-6833-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Add anatop regulators to imx6q.dtsi for all imx6q platforms.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi |   86 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 86 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 263e8f3..dd41514 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -346,6 +346,92 @@
 				compatible = "fsl,imx6q-anatop";
 				reg = <0x020c8000 0x1000>;
 				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				regulator-vddpu at 140 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vddpu";
+					regulator-min-microvolt = <725000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-always-on;
+					reg = <0x140>;
+					anatop-vol-bit-shift = <9>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <1>;
+					anatop-min-voltage = <725000>;
+					anatop-max-voltage = <1300000>;
+				};
+
+				regulator-vddcore at 140 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "cpu";
+					regulator-min-microvolt = <725000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-always-on;
+					reg = <0x140>;
+					anatop-vol-bit-shift = <0>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <1>;
+					anatop-min-voltage = <725000>;
+					anatop-max-voltage = <1300000>;
+				};
+
+				regulator-vddsoc at 140 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vddsoc";
+					regulator-min-microvolt = <725000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-always-on;
+					reg = <0x140>;
+					anatop-vol-bit-shift = <18>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <1>;
+					anatop-min-voltage = <725000>;
+					anatop-max-voltage = <1300000>;
+				};
+
+				regulator-2p5 at 130 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd2p5";
+					regulator-min-microvolt = <2000000>;
+					regulator-max-microvolt = <2775000>;
+					regulator-always-on;
+					reg = <0x130>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <0>;
+					anatop-min-voltage = <2000000>;
+					anatop-max-voltage = <2775000>;
+				};
+
+				regulator-1p1 at 110 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd1p1";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1400000>;
+					regulator-always-on;
+					reg = <0x110>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <4>;
+					anatop-min-voltage = <800000>;
+					anatop-max-voltage = <1400000>;
+				};
+
+				regulator-3p0 at 120 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd3p0";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <3150000>;
+					regulator-always-on;
+					reg = <0x120>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <7>;
+					anatop-min-voltage = <2800000>;
+					anatop-max-voltage = <3150000>;
+				};
 			};
 
 			usbphy at 020c9000 { /* USBPHY1 */
-- 
1.7.9.1



From skannan at codeaurora.org  Mon Mar 19 23:38:25 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Mon, 19 Mar 2012 20:38:25 -0700
Subject: [PATCH 1/2] clk: Fix error handling in fixed clock hardware type
 register fn
In-Reply-To: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
Message-ID: <1332214706-675-1-git-send-email-skannan@codeaurora.org>

If memory allocation for the parents array or the parent string fails, then
fail the registration immediately instead of calling clk_register and
hoping it fails there.

Return -ENOMEM on failure.

Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Jamie Iles <jamie at jamieiles.com>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
---
There are still some memory free issues when clk_register() fails, but I will
fix it when I fixed the other register() fns to return ENOMEM of alloc
failure instead of a NULL.

 drivers/clk/clk-fixed-rate.c |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 90c79fb..6423ae9 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -61,22 +61,26 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
 
 		if (! parent_names)
-			goto out;
+			goto fail_ptr;
 
 		len = sizeof(char) * strlen(parent_name);
 
 		parent_names[0] = kmalloc(len, GFP_KERNEL);
 
 		if (!parent_names[0])
-			goto out;
+			goto fail_str;
 
 		strncpy(parent_names[0], parent_name, len);
 	}
 
-out:
 	return clk_register(dev, name,
 			&clk_fixed_rate_ops, &fixed->hw,
 			parent_names,
 			(parent_name ? 1 : 0),
 			flags);
+fail_str:
+	kfree(parent_names);
+fail_ptr:
+	kfree(fixed);
+	return ERR_PTR(-ENOMEM);
 }
-- 
1.7.8.3



From skannan at codeaurora.org  Mon Mar 19 23:38:26 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Mon, 19 Mar 2012 20:38:26 -0700
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <1332214706-675-1-git-send-email-skannan@codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
Message-ID: <1332214706-675-2-git-send-email-skannan@codeaurora.org>

This has a couple of advantages:
* Completely hides struct clk from many clock platform drivers and static
  clock initialization code.
* Simplifies the generic clk_register() function and allows adding optional
  fields in the future without modifying the function signature.
* Allows for simpler static initialization of clocks on all platforms by
  removing the need for forward delcarations.
* Halves the number of symbols added for each static clock initialization.

Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
Cc: Mike Turquette <mturquette at linaro.org>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: Arnd Bergman <arnd.bergmann at linaro.org>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Shawn Guo <shawn.guo at freescale.com>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Jamie Iles <jamie at jamieiles.com>
Cc: Richard Zhao <richard.zhao at linaro.org>
Cc: Saravana Kannan <skannan at codeaurora.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij at stericsson.com>
Cc: Stephen Boyd <sboyd at codeaurora.org>
Cc: Amit Kucheria <amit.kucheria at linaro.org>
Cc: Deepak Saxena <dsaxena at linaro.org>
Cc: Grant Likely <grant.likely at secretlab.ca>
---
 drivers/clk/clk-divider.c    |   12 ++-
 drivers/clk/clk-fixed-rate.c |   12 ++-
 drivers/clk/clk-gate.c       |   12 ++-
 drivers/clk/clk-mux.c        |    9 ++-
 drivers/clk/clk.c            |  170 +++++++++++++++++++++---------------------
 include/linux/clk-private.h  |    5 -
 include/linux/clk-provider.h |    9 ++-
 7 files changed, 118 insertions(+), 111 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index d5ac6a7..68b69ed 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -184,11 +184,13 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
 			goto out;
 	}
 
-	clk = clk_register(dev, name,
-			&clk_divider_ops, &div->hw,
-			div->parent,
-			(parent_name ? 1 : 0),
-			flags);
+	div->hw.name = name;
+	div->hw.ops = &clk_divider_ops;
+	div->hw.flags = flags;
+	div->hw.parent_names = div->parent;
+	div->hw.num_parents = (parent_name ? 1 : 0);
+
+	clk = clk_register(dev, &div->hw);
 	if (clk)
 		return clk;
 
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 6423ae9..42a0156 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -73,11 +73,13 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 		strncpy(parent_names[0], parent_name, len);
 	}
 
-	return clk_register(dev, name,
-			&clk_fixed_rate_ops, &fixed->hw,
-			parent_names,
-			(parent_name ? 1 : 0),
-			flags);
+	fixed->hw.name = name;
+	fixed->hw.ops = &clk_fixed_rate_ops;
+	fixed->hw.flags = flags;
+	fixed->hw.parent_names = parent_names;
+	fixed->hw.num_parents = (parent_name ? 1 : 0);
+
+	return clk_register(dev, &fixed->hw);
 fail_str:
 	kfree(parent_names);
 fail_ptr:
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index b5902e2..cb515c7 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -135,11 +135,13 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 			goto out;
 	}
 
-	clk = clk_register(dev, name,
-			&clk_gate_ops, &gate->hw,
-			gate->parent,
-			(parent_name ? 1 : 0),
-			flags);
+	gate->hw.name = name;
+	gate->hw.ops = &clk_gate_ops;
+	gate->hw.flags = flags;
+	gate->hw.parent_names = gate->parent;
+	gate->hw.num_parents = (parent_name ? 1 : 0);
+
+	clk = clk_register(dev, &gate->hw);
 	if (clk)
 		return clk;
 out:
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index c71ad1f..1c88230 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -111,6 +111,11 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 	mux->flags = clk_mux_flags;
 	mux->lock = lock;
 
-	return clk_register(dev, name, &clk_mux_ops, &mux->hw,
-			parent_names, num_parents, flags);
+	mux->hw.name = name;
+	mux->hw.ops = &clk_mux_ops;
+	mux->hw.flags = flags;
+	mux->hw.parent_names = parent_names;
+	mux->hw.num_parents = num_parents;
+
+	return clk_register(dev, &mux->hw);
 }
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 9cf6f59..c448809 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/clk-private.h>
+#include <linux/clk-provider.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
@@ -44,7 +45,7 @@ static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
 		goto out;
 	}
 
-	d = debugfs_create_dir(clk->name, pdentry);
+	d = debugfs_create_dir(clk->hw->name, pdentry);
 	if (!d)
 		goto out;
 
@@ -56,7 +57,7 @@ static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
 		goto err_out;
 
 	d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
-			(u32 *)&clk->flags);
+			(u32 *)&clk->hw->flags);
 	if (!d)
 		goto err_out;
 
@@ -134,7 +135,7 @@ static int clk_debug_register(struct clk *clk)
 	 * safe to add this clk to debugfs
 	 */
 	if (!parent)
-		if (clk->flags & CLK_IS_ROOT)
+		if (clk->hw->flags & CLK_IS_ROOT)
 			pdentry = rootdir;
 		else
 			pdentry = orphandir;
@@ -215,11 +216,11 @@ static void clk_disable_unused_subtree(struct clk *clk)
 	if (clk->enable_count)
 		goto unlock_out;
 
-	if (clk->flags & CLK_IGNORE_UNUSED)
+	if (clk->hw->flags & CLK_IGNORE_UNUSED)
 		goto unlock_out;
 
-	if (__clk_is_enabled(clk) && clk->ops->disable)
-		clk->ops->disable(clk->hw);
+	if (__clk_is_enabled(clk) && clk->hw->ops->disable)
+		clk->hw->ops->disable(clk->hw);
 
 unlock_out:
 	spin_unlock_irqrestore(&enable_lock, flags);
@@ -254,7 +255,7 @@ static inline int clk_disable_unused(struct clk *clk) { return 0; }
 
 inline const char *__clk_get_name(struct clk *clk)
 {
-	return !clk ? NULL : clk->name;
+	return !clk ? NULL : clk->hw->name;
 }
 
 inline struct clk_hw *__clk_get_hw(struct clk *clk)
@@ -264,7 +265,7 @@ inline struct clk_hw *__clk_get_hw(struct clk *clk)
 
 inline u8 __clk_get_num_parents(struct clk *clk)
 {
-	return !clk ? -EINVAL : clk->num_parents;
+	return !clk ? -EINVAL : clk->hw->num_parents;
 }
 
 inline struct clk *__clk_get_parent(struct clk *clk)
@@ -293,7 +294,7 @@ unsigned long __clk_get_rate(struct clk *clk)
 
 	ret = clk->rate;
 
-	if (clk->flags & CLK_IS_ROOT)
+	if (clk->hw->flags & CLK_IS_ROOT)
 		goto out;
 
 	if (!clk->parent)
@@ -305,7 +306,7 @@ out:
 
 inline unsigned long __clk_get_flags(struct clk *clk)
 {
-	return !clk ? -EINVAL : clk->flags;
+	return !clk ? -EINVAL : clk->hw->flags;
 }
 
 int __clk_is_enabled(struct clk *clk)
@@ -319,12 +320,12 @@ int __clk_is_enabled(struct clk *clk)
 	 * .is_enabled is only mandatory for clocks that gate
 	 * fall back to software usage counter if .is_enabled is missing
 	 */
-	if (!clk->ops->is_enabled) {
+	if (!clk->hw->ops->is_enabled) {
 		ret = clk->enable_count ? 1 : 0;
 		goto out;
 	}
 
-	ret = clk->ops->is_enabled(clk->hw);
+	ret = clk->hw->ops->is_enabled(clk->hw);
 out:
 	return ret;
 }
@@ -335,7 +336,7 @@ static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
 	struct clk *ret;
 	struct hlist_node *tmp;
 
-	if (!strcmp(clk->name, name))
+	if (!strcmp(clk->hw->name, name))
 		return clk;
 
 	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
@@ -388,8 +389,8 @@ void __clk_unprepare(struct clk *clk)
 
 	WARN_ON(clk->enable_count > 0);
 
-	if (clk->ops->unprepare)
-		clk->ops->unprepare(clk->hw);
+	if (clk->hw->ops->unprepare)
+		clk->hw->ops->unprepare(clk->hw);
 
 	__clk_unprepare(clk->parent);
 }
@@ -425,8 +426,8 @@ int __clk_prepare(struct clk *clk)
 		if (ret)
 			return ret;
 
-		if (clk->ops->prepare) {
-			ret = clk->ops->prepare(clk->hw);
+		if (clk->hw->ops->prepare) {
+			ret = clk->hw->ops->prepare(clk->hw);
 			if (ret) {
 				__clk_unprepare(clk->parent);
 				return ret;
@@ -474,8 +475,8 @@ static void __clk_disable(struct clk *clk)
 	if (--clk->enable_count > 0)
 		return;
 
-	if (clk->ops->disable)
-		clk->ops->disable(clk->hw);
+	if (clk->hw->ops->disable)
+		clk->hw->ops->disable(clk->hw);
 
 	__clk_disable(clk->parent);
 }
@@ -518,8 +519,8 @@ static int __clk_enable(struct clk *clk)
 		if (ret)
 			return ret;
 
-		if (clk->ops->enable) {
-			ret = clk->ops->enable(clk->hw);
+		if (clk->hw->ops->enable) {
+			ret = clk->hw->ops->enable(clk->hw);
 			if (ret) {
 				__clk_disable(clk->parent);
 				return ret;
@@ -589,13 +590,13 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
 	if (!clk)
 		return -EINVAL;
 
-	if (!clk->ops->round_rate)
+	if (!clk->hw->ops->round_rate)
 		return clk->rate;
 
-	if (clk->flags & CLK_SET_RATE_PARENT)
-		return clk->ops->round_rate(clk->hw, rate, &unused);
+	if (clk->hw->flags & CLK_SET_RATE_PARENT)
+		return clk->hw->ops->round_rate(clk->hw, rate, &unused);
 	else
-		return clk->ops->round_rate(clk->hw, rate, NULL);
+		return clk->hw->ops->round_rate(clk->hw, rate, NULL);
 }
 
 /**
@@ -681,8 +682,8 @@ static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
 	if (clk->parent)
 		parent_rate = clk->parent->rate;
 
-	if (clk->ops->recalc_rate)
-		clk->rate = clk->ops->recalc_rate(clk->hw, parent_rate);
+	if (clk->hw->ops->recalc_rate)
+		clk->rate = clk->hw->ops->recalc_rate(clk->hw, parent_rate);
 	else
 		clk->rate = parent_rate;
 
@@ -720,8 +721,8 @@ static int __clk_speculate_rates(struct clk *clk, unsigned long parent_rate)
 	unsigned long new_rate;
 	int ret = NOTIFY_DONE;
 
-	if (clk->ops->recalc_rate)
-		new_rate = clk->ops->recalc_rate(clk->hw, parent_rate);
+	if (clk->hw->ops->recalc_rate)
+		new_rate = clk->hw->ops->recalc_rate(clk->hw, parent_rate);
 	else
 		new_rate = parent_rate;
 
@@ -750,8 +751,8 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
 	clk->new_rate = new_rate;
 
 	hlist_for_each_entry(child, tmp, &clk->children, child_node) {
-		if (child->ops->recalc_rate)
-			child->new_rate = child->ops->recalc_rate(child->hw, new_rate);
+		if (child->hw->ops->recalc_rate)
+			child->new_rate = child->hw->ops->recalc_rate(child->hw, new_rate);
 		else
 			child->new_rate = new_rate;
 		clk_calc_subtree(child, child->new_rate);
@@ -767,23 +768,24 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 	struct clk *top = clk;
 	unsigned long best_parent_rate = clk->parent->rate;
 	unsigned long new_rate;
+	unsigned long flags = clk->hw->flags;
 
-	if (!clk->ops->round_rate && !(clk->flags & CLK_SET_RATE_PARENT)) {
+	if (!clk->hw->ops->round_rate && !(flags & CLK_SET_RATE_PARENT)) {
 		clk->new_rate = clk->rate;
 		return NULL;
 	}
 
-	if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) {
+	if (!clk->hw->ops->round_rate && (flags & CLK_SET_RATE_PARENT)) {
 		top = clk_calc_new_rates(clk->parent, rate);
 		new_rate = clk->new_rate = clk->parent->new_rate;
 
 		goto out;
 	}
 
-	if (clk->flags & CLK_SET_RATE_PARENT)
-		new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
+	if (flags & CLK_SET_RATE_PARENT)
+		new_rate = clk->hw->ops->round_rate(clk->hw, rate, &best_parent_rate);
 	else
-		new_rate = clk->ops->round_rate(clk->hw, rate, NULL);
+		new_rate = clk->hw->ops->round_rate(clk->hw, rate, NULL);
 
 	if (best_parent_rate != clk->parent->rate) {
 		top = clk_calc_new_rates(clk->parent, best_parent_rate);
@@ -838,11 +840,11 @@ static void clk_change_rate(struct clk *clk)
 
 	old_rate = clk->rate;
 
-	if (clk->ops->set_rate)
-		clk->ops->set_rate(clk->hw, clk->new_rate);
+	if (clk->hw->ops->set_rate)
+		clk->hw->ops->set_rate(clk->hw, clk->new_rate);
 
-	if (clk->ops->recalc_rate)
-		clk->rate = clk->ops->recalc_rate(clk->hw,
+	if (clk->hw->ops->recalc_rate)
+		clk->rate = clk->hw->ops->recalc_rate(clk->hw,
 				clk->parent->rate);
 	else
 		clk->rate = clk->parent->rate;
@@ -917,7 +919,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 	fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
 	if (fail_clk) {
 		pr_warn("%s: failed to set %s rate\n", __func__,
-				fail_clk->name);
+				fail_clk->hw->name);
 		clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
 		ret = -EBUSY;
 		goto out;
@@ -970,18 +972,19 @@ static struct clk *__clk_init_parent(struct clk *clk)
 
 	/* handle the trivial cases */
 
-	if (!clk->num_parents)
+	if (!clk->hw->num_parents)
 		goto out;
 
-	if (clk->num_parents == 1) {
+	if (clk->hw->num_parents == 1) {
 		if (IS_ERR_OR_NULL(clk->parent))
-			ret = clk->parent = __clk_lookup(clk->parent_names[0]);
+			ret = clk->parent =
+				__clk_lookup(clk->hw->parent_names[0]);
 		ret = clk->parent;
 		goto out;
 	}
 
-	if (!clk->ops->get_parent) {
-		WARN(!clk->ops->get_parent,
+	if (!clk->hw->ops->get_parent) {
+		WARN(!clk->hw->ops->get_parent,
 			"%s: multi-parent clocks must implement .get_parent\n",
 			__func__);
 		goto out;
@@ -993,18 +996,18 @@ static struct clk *__clk_init_parent(struct clk *clk)
 	 * clk->parent here; that is done by the calling function
 	 */
 
-	index = clk->ops->get_parent(clk->hw);
+	index = clk->hw->ops->get_parent(clk->hw);
 
 	if (!clk->parents)
 		clk->parents =
-			kmalloc((sizeof(struct clk*) * clk->num_parents),
+			kmalloc((sizeof(struct clk*) * clk->hw->num_parents),
 					GFP_KERNEL);
 
 	if (!clk->parents)
-		ret = __clk_lookup(clk->parent_names[index]);
+		ret = __clk_lookup(clk->hw->parent_names[index]);
 	else if (!clk->parents[index])
 		ret = clk->parents[index] =
-			__clk_lookup(clk->parent_names[index]);
+			__clk_lookup(clk->hw->parent_names[index]);
 	else
 		ret = clk->parents[index];
 
@@ -1039,12 +1042,12 @@ void __clk_reparent(struct clk *clk, struct clk *new_parent)
 		new_parent_d = orphandir;
 
 	d = debugfs_rename(clk->dentry->d_parent, clk->dentry,
-			new_parent_d, clk->name);
+			new_parent_d, clk->hw->name);
 	if (d)
 		clk->dentry = d;
 	else
 		pr_debug("%s: failed to rename debugfs entry for %s\n",
-				__func__, clk->name);
+				__func__, clk->hw->name);
 out:
 #endif
 
@@ -1063,7 +1066,7 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent)
 	old_parent = clk->parent;
 
 	/* find index of new parent clock using cached parent ptrs */
-	for (i = 0; i < clk->num_parents; i++)
+	for (i = 0; i < clk->hw->num_parents; i++)
 		if (clk->parents[i] == parent)
 			break;
 
@@ -1071,16 +1074,17 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent)
 	 * find index of new parent clock using string name comparison
 	 * also try to cache the parent to avoid future calls to __clk_lookup
 	 */
-	if (i == clk->num_parents)
-		for (i = 0; i < clk->num_parents; i++)
-			if (!strcmp(clk->parent_names[i], parent->name)) {
-				clk->parents[i] = __clk_lookup(parent->name);
+	if (i == clk->hw->num_parents)
+		for (i = 0; i < clk->hw->num_parents; i++)
+			if (!strcmp(clk->hw->parent_names[i],
+						parent->hw->name)) {
+				clk->parents[i] = __clk_lookup(parent->hw->name);
 				break;
 			}
 
-	if (i == clk->num_parents) {
+	if (i == clk->hw->num_parents) {
 		pr_debug("%s: clock %s is not a possible parent of clock %s\n",
-				__func__, parent->name, clk->name);
+				__func__, parent->hw->name, clk->hw->name);
 		goto out;
 	}
 
@@ -1095,7 +1099,7 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent)
 	spin_unlock_irqrestore(&enable_lock, flags);
 
 	/* change clock input source */
-	ret = clk->ops->set_parent(clk->hw, i);
+	ret = clk->hw->ops->set_parent(clk->hw, i);
 
 	/* clean up old prepare and enable */
 	spin_lock_irqsave(&enable_lock, flags);
@@ -1126,10 +1130,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 {
 	int ret = 0;
 
-	if (!clk || !clk->ops)
+	if (!clk || !clk->hw->ops)
 		return -EINVAL;
 
-	if (!clk->ops->set_parent)
+	if (!clk->hw->ops->set_parent)
 		return -ENOSYS;
 
 	/* prevent racing with updates to the clock topology */
@@ -1147,7 +1151,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 		goto out;
 
 	/* only re-parent if the clock is not in use */
-	if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count)
+	if ((clk->hw->flags & CLK_SET_PARENT_GATE) && clk->prepare_count)
 		ret = -EBUSY;
 	else
 		ret = __clk_set_parent(clk, parent);
@@ -1207,14 +1211,14 @@ void __clk_init(struct device *dev, struct clk *clk)
 	mutex_lock(&prepare_lock);
 
 	/* check to see if a clock with this name is already registered */
-	if (__clk_lookup(clk->name))
+	if (__clk_lookup(clk->hw->name))
 		goto out;
 
 	/* throw a WARN if any entries in parent_names are NULL */
-	for (i = 0; i < clk->num_parents; i++)
-		WARN(!clk->parent_names[i],
+	for (i = 0; i < clk->hw->num_parents; i++)
+		WARN(!clk->hw->parent_names[i],
 				"%s: invalid NULL in %s's .parent_names\n",
-				__func__, clk->name);
+				__func__, clk->hw->name);
 
 	/*
 	 * Allocate an array of struct clk *'s to avoid unnecessary string
@@ -1226,8 +1230,8 @@ void __clk_init(struct device *dev, struct clk *clk)
 	 * If clk->parents is not NULL we skip this entire block.  This allows
 	 * for clock drivers to statically initialize clk->parents.
 	 */
-	if (clk->num_parents && !clk->parents) {
-		clk->parents = kmalloc((sizeof(struct clk*) * clk->num_parents),
+	if (clk->hw->num_parents && !clk->parents) {
+		clk->parents = kmalloc((sizeof(struct clk*) * clk->hw->num_parents),
 				GFP_KERNEL);
 		/*
 		 * __clk_lookup returns NULL for parents that have not been
@@ -1236,9 +1240,9 @@ void __clk_init(struct device *dev, struct clk *clk)
 		 * missing parents later on.
 		 */
 		if (clk->parents)
-			for (i = 0; i < clk->num_parents; i++)
+			for (i = 0; i < clk->hw->num_parents; i++)
 				clk->parents[i] =
-					__clk_lookup(clk->parent_names[i]);
+					__clk_lookup(clk->hw->parent_names[i]);
 	}
 
 	clk->parent = __clk_init_parent(clk);
@@ -1256,7 +1260,7 @@ void __clk_init(struct device *dev, struct clk *clk)
 	if (clk->parent)
 		hlist_add_head(&clk->child_node,
 				&clk->parent->children);
-	else if (clk->flags & CLK_IS_ROOT)
+	else if (clk->hw->flags & CLK_IS_ROOT)
 		hlist_add_head(&clk->child_node, &clk_root_list);
 	else
 		hlist_add_head(&clk->child_node, &clk_orphan_list);
@@ -1267,8 +1271,8 @@ void __clk_init(struct device *dev, struct clk *clk)
 	 * parent's rate.  If a clock doesn't have a parent (or is orphaned)
 	 * then rate is set to zero.
 	 */
-	if (clk->ops->recalc_rate)
-		clk->rate = clk->ops->recalc_rate(clk->hw,
+	if (clk->hw->ops->recalc_rate)
+		clk->rate = clk->hw->ops->recalc_rate(clk->hw,
 				__clk_get_rate(clk->parent));
 	else if (clk->parent)
 		clk->rate = clk->parent->rate;
@@ -1280,8 +1284,9 @@ void __clk_init(struct device *dev, struct clk *clk)
 	 * this clock
 	 */
 	hlist_for_each_entry_safe(orphan, tmp, tmp2, &clk_orphan_list, child_node)
-		for (i = 0; i < orphan->num_parents; i++)
-			if (!strcmp(clk->name, orphan->parent_names[i])) {
+		for (i = 0; i < orphan->hw->num_parents; i++)
+			if (!strcmp(clk->hw->name,
+						orphan->hw->parent_names[i])) {
 				__clk_reparent(orphan, clk);
 				break;
 			}
@@ -1294,8 +1299,8 @@ void __clk_init(struct device *dev, struct clk *clk)
 	 * Please consider other ways of solving initialization problems before
 	 * using this callback, as it's use is discouraged.
 	 */
-	if (clk->ops->init)
-		clk->ops->init(clk->hw);
+	if (clk->hw->ops->init)
+		clk->hw->ops->init(clk->hw);
 
 	clk_debug_register(clk);
 
@@ -1320,9 +1325,7 @@ out:
  * cannot be dereferenced by driver code but may be used in conjuction with the
  * rest of the clock API.
  */
-struct clk *clk_register(struct device *dev, const char *name,
-		const struct clk_ops *ops, struct clk_hw *hw,
-		char **parent_names, u8 num_parents, unsigned long flags)
+struct clk *clk_register(struct device *dev, struct clk_hw *hw)
 {
 	struct clk *clk;
 
@@ -1330,12 +1333,7 @@ struct clk *clk_register(struct device *dev, const char *name,
 	if (!clk)
 		return NULL;
 
-	clk->name = name;
-	clk->ops = ops;
 	clk->hw = hw;
-	clk->flags = flags;
-	clk->parent_names = parent_names;
-	clk->num_parents = num_parents;
 	hw->clk = clk;
 
 	__clk_init(dev, clk);
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 5e4312b..f70860d 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -26,16 +26,11 @@
 #ifdef CONFIG_COMMON_CLK
 
 struct clk {
-	const char		*name;
-	const struct clk_ops	*ops;
 	struct clk_hw		*hw;
 	struct clk		*parent;
-	char			**parent_names;
 	struct clk		**parents;
-	u8			num_parents;
 	unsigned long		rate;
 	unsigned long		new_rate;
-	unsigned long		flags;
 	unsigned int		enable_count;
 	unsigned int		prepare_count;
 	struct hlist_head	children;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5508897..f032e49 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -26,6 +26,11 @@
  */
 struct clk_hw {
 	struct clk *clk;
+	const char		*name;
+	const struct clk_ops	*ops;
+	char			**parent_names;
+	u8			num_parents;
+	unsigned long		flags;
 };
 
 /*
@@ -272,9 +277,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
  * cannot be dereferenced by driver code but may be used in conjuction with the
  * rest of the clock API.
  */
-struct clk *clk_register(struct device *dev, const char *name,
-		const struct clk_ops *ops, struct clk_hw *hw,
-		char **parent_names, u8 num_parents, unsigned long flags);
+struct clk *clk_register(struct device *dev, struct clk_hw *hw);
 
 /* helper functions */
 const char *__clk_get_name(struct clk *clk);
-- 
1.7.8.3



From b29396 at freescale.com  Tue Mar 20 00:23:06 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 20 Mar 2012 12:23:06 +0800
Subject: [PATCH 1/1] net: phylib: remove the length limitation of mii bus id
Message-ID: <1332217386-3586-1-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

When convert to dt, the length of old mii bus id (17 bytes) is not
sufficent to use.
For example, the bus id could be 800f0000.ethernet-1:00 in DT.

This patch removes the bus id length limitation by changing the
bus id to a const char pionter and user could dynamically set the
bus id via kasprintf function call.

Since then no users use MII_BUS_ID_SIZE any more, just remove it.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
The simplest way may just change MII_BUS_ID_SIZE to a more bigger size,
but i'm not sure that's gonna be accepted.
So changed to remove the bus id length limitation, a lot of handwork.

Since this patch changes a lot of other ethernet drivers and i did
not have condition to test it, need each corresponding driver owners
to help review.

I just greped the macro MII_BUS_ID_SIZE in the latest kernel tree and
did the replacement.
In case any one missed(may not use MII_BUS_ID_SIZE), that driver owner
should help change it.

Only tested the fec driver on i.MX28 EVK board.
---
 arch/powerpc/platforms/82xx/ep8248e.c              |    2 +-
 arch/powerpc/platforms/pasemi/gpio_mdio.c          |    2 +-
 drivers/net/ethernet/8390/ax88796.c                |    4 +---
 drivers/net/ethernet/adi/bfin_mac.c                |    3 +--
 drivers/net/ethernet/aeroflex/greth.c              |    2 +-
 drivers/net/ethernet/amd/au1000_eth.c              |    3 +--
 drivers/net/ethernet/broadcom/bcm63xx_enet.c       |   10 +++++-----
 drivers/net/ethernet/broadcom/sb1250-mac.c         |    2 +-
 drivers/net/ethernet/broadcom/tg3.c                |    4 ++--
 drivers/net/ethernet/cadence/macb.c                |    2 +-
 drivers/net/ethernet/dnet.c                        |    2 +-
 drivers/net/ethernet/ethoc.c                       |    2 +-
 drivers/net/ethernet/faraday/ftgmac100.c           |    2 +-
 drivers/net/ethernet/freescale/fec.c               |   16 +++++++++-------
 drivers/net/ethernet/freescale/fec_mpc52xx_phy.c   |    2 +-
 .../net/ethernet/freescale/fs_enet/mii-bitbang.c   |    2 +-
 drivers/net/ethernet/freescale/fs_enet/mii-fec.c   |    2 +-
 drivers/net/ethernet/freescale/fsl_pq_mdio.c       |    6 +++---
 drivers/net/ethernet/freescale/fsl_pq_mdio.h       |    2 +-
 drivers/net/ethernet/lantiq_etop.c                 |    2 +-
 drivers/net/ethernet/marvell/mv643xx_eth.c         |    2 +-
 drivers/net/ethernet/marvell/pxa168_eth.c          |    2 +-
 drivers/net/ethernet/rdc/r6040.c                   |    4 ++--
 drivers/net/ethernet/renesas/sh_eth.c              |    7 ++++---
 drivers/net/ethernet/s6gmac.c                      |    2 +-
 drivers/net/ethernet/smsc/smsc911x.c               |    4 ++--
 drivers/net/ethernet/smsc/smsc9420.c               |    2 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |   10 ++++++----
 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c  |    4 ++--
 drivers/net/ethernet/ti/cpmac.c                    |   16 ++++++++--------
 drivers/net/ethernet/ti/davinci_mdio.c             |    4 ++--
 drivers/net/ethernet/toshiba/tc35815.c             |    2 +-
 drivers/net/ethernet/xilinx/ll_temac_mdio.c        |    2 +-
 drivers/net/ethernet/xilinx/xilinx_emaclite.c      |    2 +-
 drivers/net/ethernet/xscale/ixp4xx_eth.c           |    7 ++++---
 drivers/net/phy/fixed.c                            |    2 +-
 drivers/net/phy/mdio-gpio.c                        |    2 +-
 drivers/net/phy/mdio-octeon.c                      |    2 +-
 drivers/net/phy/phy_device.c                       |    2 +-
 drivers/of/of_mdio.c                               |    5 +++--
 drivers/staging/et131x/et131x.c                    |    2 +-
 include/linux/phy.h                                |   10 ++--------
 net/dsa/slave.c                                    |    2 +-
 43 files changed, 83 insertions(+), 86 deletions(-)

diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c
index 10ff526..21658de 100644
--- a/arch/powerpc/platforms/82xx/ep8248e.c
+++ b/arch/powerpc/platforms/82xx/ep8248e.c
@@ -139,7 +139,7 @@ static int __devinit ep8248e_mdio_probe(struct platform_device *ofdev)
 
 	bus->name = "ep8248e-mdio-bitbang";
 	bus->parent = &ofdev->dev;
-	snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
+	bus->id = kasprintf(GFP_KERNEL, "%x", res.start);
 
 	ret = of_mdiobus_register(bus, ofdev->dev.of_node);
 	if (ret)
diff --git a/arch/powerpc/platforms/pasemi/gpio_mdio.c b/arch/powerpc/platforms/pasemi/gpio_mdio.c
index 9886296..3b55962 100644
--- a/arch/powerpc/platforms/pasemi/gpio_mdio.c
+++ b/arch/powerpc/platforms/pasemi/gpio_mdio.c
@@ -241,7 +241,7 @@ static int __devinit gpio_mdio_probe(struct platform_device *ofdev)
 	new_bus->reset = &gpio_mdio_reset;
 
 	prop = of_get_property(np, "reg", NULL);
-	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", *prop);
+	new_bus->id = kasprintf(GFP_KERNEL, "%x", *prop);
 	new_bus->priv = priv;
 
 	new_bus->irq = priv->mdio_irqs;
diff --git a/drivers/net/ethernet/8390/ax88796.c b/drivers/net/ethernet/8390/ax88796.c
index 0f92e35..c70067c 100644
--- a/drivers/net/ethernet/8390/ax88796.c
+++ b/drivers/net/ethernet/8390/ax88796.c
@@ -623,9 +623,7 @@ static int ax_mii_init(struct net_device *dev)
 
 	ax->mii_bus->name = "ax88796_mii_bus";
 	ax->mii_bus->parent = dev->dev.parent;
-	snprintf(ax->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, pdev->id);
-
+	ax->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x", pdev->name, pdev->id);
 	ax->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
 	if (!ax->mii_bus->irq) {
 		err = -ENOMEM;
diff --git a/drivers/net/ethernet/adi/bfin_mac.c b/drivers/net/ethernet/adi/bfin_mac.c
index d812a10..77d473a 100644
--- a/drivers/net/ethernet/adi/bfin_mac.c
+++ b/drivers/net/ethernet/adi/bfin_mac.c
@@ -1670,8 +1670,7 @@ static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
 	miibus->name = "bfin_mii_bus";
 	miibus->phy_mask = mii_bus_pd->phy_mask;
 
-	snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, pdev->id);
+	miibus->id = kasprintf(GFP_KERNEL, "%s-%x", pdev->name, pdev->id);
 	miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
 	if (!miibus->irq)
 		goto out_err_irq_alloc;
diff --git a/drivers/net/ethernet/aeroflex/greth.c b/drivers/net/ethernet/aeroflex/greth.c
index c885aa9..df635f2 100644
--- a/drivers/net/ethernet/aeroflex/greth.c
+++ b/drivers/net/ethernet/aeroflex/greth.c
@@ -1332,7 +1332,7 @@ static int greth_mdio_init(struct greth_private *greth)
 	}
 
 	greth->mdio->name = "greth-mdio";
-	snprintf(greth->mdio->id, MII_BUS_ID_SIZE, "%s-%d", greth->mdio->name, greth->irq);
+	greth->mdio->id = kasprintf(GFP_KERNEL, "%s-%d", greth->mdio->name, greth->irq);
 	greth->mdio->read = greth_mdio_read;
 	greth->mdio->write = greth_mdio_write;
 	greth->mdio->reset = greth_mdio_reset;
diff --git a/drivers/net/ethernet/amd/au1000_eth.c b/drivers/net/ethernet/amd/au1000_eth.c
index 8b95dd3..99e0ebb 100644
--- a/drivers/net/ethernet/amd/au1000_eth.c
+++ b/drivers/net/ethernet/amd/au1000_eth.c
@@ -1171,8 +1171,7 @@ static int __devinit au1000_probe(struct platform_device *pdev)
 	aup->mii_bus->write = au1000_mdiobus_write;
 	aup->mii_bus->reset = au1000_mdiobus_reset;
 	aup->mii_bus->name = "au1000_eth_mii";
-	snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, aup->mac_id);
+	aup->mii_bus->id =  kasprintf(GFP_KERNEL, "%s-%x", pdev->name, aup->mac_id);
 	aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
 	if (aup->mii_bus->irq == NULL)
 		goto err_out;
diff --git a/drivers/net/ethernet/broadcom/bcm63xx_enet.c b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
index 986019b..8118878 100644
--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
@@ -787,7 +787,7 @@ static int bcm_enet_open(struct net_device *dev)
 	struct phy_device *phydev;
 	int i, ret;
 	unsigned int size;
-	char phy_id[MII_BUS_ID_SIZE + 3];
+	const char *phy_id;
 	void *p;
 	u32 val;
 
@@ -796,12 +796,12 @@ static int bcm_enet_open(struct net_device *dev)
 
 	if (priv->has_phy) {
 		/* connect to PHY */
-		snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
-			 priv->mac_id ? "1" : "0", priv->phy_id);
+		phy_id = kasprintf(GFP_KERNEL, PHY_ID_FMT,
+				priv->mac_id ? "1" : "0", priv->phy_id);
 
 		phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, 0,
 				     PHY_INTERFACE_MODE_MII);
-
+		kfree(phy_id);
 		if (IS_ERR(phydev)) {
 			dev_err(kdev, "could not attach to PHY\n");
 			return PTR_ERR(phydev);
@@ -1727,7 +1727,7 @@ static int __devinit bcm_enet_probe(struct platform_device *pdev)
 		bus->priv = priv;
 		bus->read = bcm_enet_mdio_read_phylib;
 		bus->write = bcm_enet_mdio_write_phylib;
-		sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
+		bus->id = kasprintf(GFP_KERNEL, "%s-%d", pdev->name, priv->mac_id);
 
 		/* only probe bus where we think the PHY is, because
 		 * the mdio read operation return 0 instead of 0xffff
diff --git a/drivers/net/ethernet/broadcom/sb1250-mac.c b/drivers/net/ethernet/broadcom/sb1250-mac.c
index 084904c..7fd5654 100644
--- a/drivers/net/ethernet/broadcom/sb1250-mac.c
+++ b/drivers/net/ethernet/broadcom/sb1250-mac.c
@@ -2259,7 +2259,7 @@ static int sbmac_init(struct platform_device *pldev, long long base)
 	}
 
 	sc->mii_bus->name = sbmac_mdio_string;
-	snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	sc->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		pldev->name, idx);
 	sc->mii_bus->priv = sc;
 	sc->mii_bus->read = sbmac_mii_read;
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index d529af9..2750e49 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -1328,8 +1328,8 @@ static int tg3_mdio_init(struct tg3 *tp)
 		return -ENOMEM;
 
 	tp->mdio_bus->name     = "tg3 mdio bus";
-	snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
-		 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
+	tp->mdio_bus->id = kasprintf(GFP_KERNEL, "%x",
+		(tp->pdev->bus->number << 8) | tp->pdev->devfn);
 	tp->mdio_bus->priv     = tp;
 	tp->mdio_bus->parent   = &tp->pdev->dev;
 	tp->mdio_bus->read     = &tg3_mdio_read;
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 2320068..62e4465 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -243,7 +243,7 @@ static int macb_mii_init(struct macb *bp)
 	bp->mii_bus->read = &macb_mdio_read;
 	bp->mii_bus->write = &macb_mdio_write;
 	bp->mii_bus->reset = &macb_mdio_reset;
-	snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	bp->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		bp->pdev->name, bp->pdev->id);
 	bp->mii_bus->priv = bp;
 	bp->mii_bus->parent = &bp->dev->dev;
diff --git a/drivers/net/ethernet/dnet.c b/drivers/net/ethernet/dnet.c
index 925c9ba..18c3c92 100644
--- a/drivers/net/ethernet/dnet.c
+++ b/drivers/net/ethernet/dnet.c
@@ -325,7 +325,7 @@ static int dnet_mii_init(struct dnet *bp)
 	bp->mii_bus->write = &dnet_mdio_write;
 	bp->mii_bus->reset = &dnet_mdio_reset;
 
-	snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	bp->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		bp->pdev->name, bp->pdev->id);
 
 	bp->mii_bus->priv = bp;
diff --git a/drivers/net/ethernet/ethoc.c b/drivers/net/ethernet/ethoc.c
index 60f0e78..e9195a5 100644
--- a/drivers/net/ethernet/ethoc.c
+++ b/drivers/net/ethernet/ethoc.c
@@ -1063,7 +1063,7 @@ static int __devinit ethoc_probe(struct platform_device *pdev)
 	}
 
 	priv->mdio->name = "ethoc-mdio";
-	snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
+	priv->mdio->id = kasprintf(GFP_KERNEL, "%s-%d",
 			priv->mdio->name, pdev->id);
 	priv->mdio->read = ethoc_mdio_read;
 	priv->mdio->write = ethoc_mdio_write;
diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c
index fb5579a..af418cd 100644
--- a/drivers/net/ethernet/faraday/ftgmac100.c
+++ b/drivers/net/ethernet/faraday/ftgmac100.c
@@ -1255,7 +1255,7 @@ static int ftgmac100_probe(struct platform_device *pdev)
 	}
 
 	priv->mii_bus->name = "ftgmac100_mdio";
-	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "ftgmac100_mii");
+	priv->mii_bus->id = kstrdup("ftgmac100_mii", GFP_KERNEL);
 
 	priv->mii_bus->priv = netdev;
 	priv->mii_bus->read = ftgmac100_mdiobus_read;
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index 7b25e9c..6e82c2d 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -961,8 +961,8 @@ static int fec_enet_mii_probe(struct net_device *ndev)
 	const struct platform_device_id *id_entry =
 				platform_get_device_id(fep->pdev);
 	struct phy_device *phy_dev = NULL;
-	char mdio_bus_id[MII_BUS_ID_SIZE];
-	char phy_name[MII_BUS_ID_SIZE + 3];
+	const char *mdio_bus_id;
+	const char *phy_name;
 	int phy_id;
 	int dev_id = fep->dev_id;
 
@@ -978,7 +978,7 @@ static int fec_enet_mii_probe(struct net_device *ndev)
 			continue;
 		if (dev_id--)
 			continue;
-		strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
+		mdio_bus_id = kstrdup(fep->mii_bus->id, GFP_KERNEL);
 		break;
 	}
 
@@ -986,13 +986,15 @@ static int fec_enet_mii_probe(struct net_device *ndev)
 		printk(KERN_INFO
 			"%s: no PHY, assuming direct connection to switch\n",
 			ndev->name);
-		strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE);
+		mdio_bus_id = kstrdup("0", GFP_KERNEL);
 		phy_id = 0;
 	}
 
-	snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
+	phy_name= kasprintf(GFP_KERNEL, PHY_ID_FMT, mdio_bus_id, phy_id);
 	phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
 			      fep->phy_interface);
+	kfree(mdio_bus_id);
+	kfree(phy_name);
 	if (IS_ERR(phy_dev)) {
 		printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
 		return PTR_ERR(phy_dev);
@@ -1080,8 +1082,8 @@ static int fec_enet_mii_init(struct platform_device *pdev)
 	fep->mii_bus->read = fec_enet_mdio_read;
 	fep->mii_bus->write = fec_enet_mdio_write;
 	fep->mii_bus->reset = fec_enet_mdio_reset;
-	snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, fep->dev_id + 1);
+	fep->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
+					pdev->name, fep->dev_id +1);
 	fep->mii_bus->priv = fep;
 	fep->mii_bus->parent = &pdev->dev;
 
diff --git a/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c b/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c
index 360a578..7724be7 100644
--- a/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c
+++ b/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c
@@ -96,7 +96,7 @@ static int mpc52xx_fec_mdio_probe(struct platform_device *of)
 		goto out_free;
 	}
 
-	snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
+	bus->id = kasprintf(GFP_KERNEL, "%x", res.start);
 	bus->priv = priv;
 
 	bus->parent = dev;
diff --git a/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c b/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c
index 0f2d1a7..9e6eac9 100644
--- a/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c
+++ b/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c
@@ -127,7 +127,7 @@ static int __devinit fs_mii_bitbang_init(struct mii_bus *bus,
 	 * we get is an int, and the odds of multiple bitbang mdio buses
 	 * is low enough that it's not worth going too crazy.
 	 */
-	snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
+	bus->id = kasprintf(GFP_KERNEL, "%x", res.start);
 
 	data = of_get_property(np, "fsl,mdio-pin", &len);
 	if (!data || len != 4)
diff --git a/drivers/net/ethernet/freescale/fs_enet/mii-fec.c b/drivers/net/ethernet/freescale/fs_enet/mii-fec.c
index 55bb867..5242f4d 100644
--- a/drivers/net/ethernet/freescale/fs_enet/mii-fec.c
+++ b/drivers/net/ethernet/freescale/fs_enet/mii-fec.c
@@ -134,7 +134,7 @@ static int __devinit fs_enet_mdio_probe(struct platform_device *ofdev)
 	if (ret)
 		goto out_res;
 
-	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", res.start);
+	new_bus->id = kasprintf(GFP_KERNEL, "%x", res.start);
 
 	fec->fecp = ioremap(res.start, resource_size(&res));
 	if (!fec->fecp)
diff --git a/drivers/net/ethernet/freescale/fsl_pq_mdio.c b/drivers/net/ethernet/freescale/fsl_pq_mdio.c
index 9eb8159..773acd5 100644
--- a/drivers/net/ethernet/freescale/fsl_pq_mdio.c
+++ b/drivers/net/ethernet/freescale/fsl_pq_mdio.c
@@ -169,7 +169,7 @@ static int fsl_pq_mdio_reset(struct mii_bus *bus)
 	return 0;
 }
 
-void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
+void fsl_pq_mdio_bus_name(char **name, struct device_node *np)
 {
 	const u32 *addr;
 	u64 taddr = OF_BAD_ADDR;
@@ -178,7 +178,7 @@ void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
 	if (addr)
 		taddr = of_translate_address(np, addr);
 
-	snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
+	*name = kasprintf(GFP_KERNEL, "%s@%llx", np->name,
 		(unsigned long long)taddr);
 }
 EXPORT_SYMBOL_GPL(fsl_pq_mdio_bus_name);
@@ -277,7 +277,7 @@ static int fsl_pq_mdio_probe(struct platform_device *ofdev)
 	new_bus->write = &fsl_pq_mdio_write,
 	new_bus->reset = &fsl_pq_mdio_reset,
 	new_bus->priv = priv;
-	fsl_pq_mdio_bus_name(new_bus->id, np);
+	fsl_pq_mdio_bus_name(&new_bus->id, np);
 
 	addrp = of_get_address(np, 0, &size, NULL);
 	if (!addrp) {
diff --git a/drivers/net/ethernet/freescale/fsl_pq_mdio.h b/drivers/net/ethernet/freescale/fsl_pq_mdio.h
index bd17a2a..b563ef7 100644
--- a/drivers/net/ethernet/freescale/fsl_pq_mdio.h
+++ b/drivers/net/ethernet/freescale/fsl_pq_mdio.h
@@ -48,5 +48,5 @@ int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
 int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs, int mii_id, int regnum);
 int __init fsl_pq_mdio_init(void);
 void fsl_pq_mdio_exit(void);
-void fsl_pq_mdio_bus_name(char *name, struct device_node *np);
+void fsl_pq_mdio_bus_name(char **name, struct device_node *np);
 #endif /* FSL_PQ_MDIO_H */
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index 85e2c6c..742e7dd 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -437,7 +437,7 @@ ltq_etop_mdio_init(struct net_device *dev)
 	priv->mii_bus->read = ltq_etop_mdio_rd;
 	priv->mii_bus->write = ltq_etop_mdio_wr;
 	priv->mii_bus->name = "ltq_mii";
-	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	priv->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		priv->pdev->name, priv->pdev->id);
 	priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
 	if (!priv->mii_bus->irq) {
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 9c049d2..e18707f 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -2613,7 +2613,7 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 		msp->smi_bus->name = "mv643xx_eth smi";
 		msp->smi_bus->read = smi_bus_read;
 		msp->smi_bus->write = smi_bus_write,
-		snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
+		msp->smi_bus->id = kasprintf(GFP_KERNEL, "%s-%d",
 			pdev->name, pdev->id);
 		msp->smi_bus->parent = &pdev->dev;
 		msp->smi_bus->phy_mask = 0xffffffff;
diff --git a/drivers/net/ethernet/marvell/pxa168_eth.c b/drivers/net/ethernet/marvell/pxa168_eth.c
index 953ba58..bf19af7 100644
--- a/drivers/net/ethernet/marvell/pxa168_eth.c
+++ b/drivers/net/ethernet/marvell/pxa168_eth.c
@@ -1552,7 +1552,7 @@ static int pxa168_eth_probe(struct platform_device *pdev)
 	pep->smi_bus->name = "pxa168_eth smi";
 	pep->smi_bus->read = pxa168_smi_read;
 	pep->smi_bus->write = pxa168_smi_write;
-	snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
+	pep->smi_bus->id = kasprintf(GFP_KERNEL, "%s-%d",
 		pdev->name, pdev->id);
 	pep->smi_bus->parent = &pdev->dev;
 	pep->smi_bus->phy_mask = 0xffffffff;
diff --git a/drivers/net/ethernet/rdc/r6040.c b/drivers/net/ethernet/rdc/r6040.c
index cb0eca8..9d890b2 100644
--- a/drivers/net/ethernet/rdc/r6040.c
+++ b/drivers/net/ethernet/rdc/r6040.c
@@ -1181,8 +1181,8 @@ static int __devinit r6040_init_one(struct pci_dev *pdev,
 	lp->mii_bus->write = r6040_mdiobus_write;
 	lp->mii_bus->reset = r6040_mdiobus_reset;
 	lp->mii_bus->name = "r6040_eth_mii";
-	snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		dev_name(&pdev->dev), card_idx);
+	lp->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
+			dev_name(&pdev->dev), card_idx);
 	lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
 	if (!lp->mii_bus->irq) {
 		dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index 813d41c..3210fd9 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -1213,10 +1213,10 @@ static void sh_eth_adjust_link(struct net_device *ndev)
 static int sh_eth_phy_init(struct net_device *ndev)
 {
 	struct sh_eth_private *mdp = netdev_priv(ndev);
-	char phy_id[MII_BUS_ID_SIZE + 3];
+	const char *phy_id;
 	struct phy_device *phydev = NULL;
 
-	snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
+	phy_id = kasprintf(GFP_KERNEL, PHY_ID_FMT,
 		mdp->mii_bus->id , mdp->phy_id);
 
 	mdp->link = PHY_DOWN;
@@ -1226,6 +1226,7 @@ static int sh_eth_phy_init(struct net_device *ndev)
 	/* Try connect to PHY */
 	phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
 				0, mdp->phy_interface);
+	kfree(phy_id);
 	if (IS_ERR(phydev)) {
 		dev_err(&ndev->dev, "phy_connect failed\n");
 		return PTR_ERR(phydev);
@@ -1702,7 +1703,7 @@ static int sh_mdio_init(struct net_device *ndev, int id,
 	/* Hook up MII support for ethtool */
 	mdp->mii_bus->name = "sh_mii";
 	mdp->mii_bus->parent = &ndev->dev;
-	snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	mdp->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		mdp->pdev->name, id);
 
 	/* PHY IRQ */
diff --git a/drivers/net/ethernet/s6gmac.c b/drivers/net/ethernet/s6gmac.c
index 22e9c01..dd5f29b 100644
--- a/drivers/net/ethernet/s6gmac.c
+++ b/drivers/net/ethernet/s6gmac.c
@@ -1004,7 +1004,7 @@ static int __devinit s6gmac_probe(struct platform_device *pdev)
 	mb->write = s6mii_write;
 	mb->reset = s6mii_reset;
 	mb->priv = pd;
-	snprintf(mb->id, MII_BUS_ID_SIZE, "%s-%x", pdev->name, pdev->id);
+	mb->id = kasprintf(GFP_KERNEL, "%s-%x", pdev->name, pdev->id);
 	mb->phy_mask = ~(1 << 0);
 	mb->irq = &pd->mii.irq[0];
 	for (i = 0; i < PHY_MAX_ADDR; i++) {
diff --git a/drivers/net/ethernet/smsc/smsc911x.c b/drivers/net/ethernet/smsc/smsc911x.c
index 24d2df0..4aab696 100644
--- a/drivers/net/ethernet/smsc/smsc911x.c
+++ b/drivers/net/ethernet/smsc/smsc911x.c
@@ -1044,8 +1044,8 @@ static int __devinit smsc911x_mii_init(struct platform_device *pdev,
 	}
 
 	pdata->mii_bus->name = SMSC_MDIONAME;
-	snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, pdev->id);
+	pdata->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
+			pdev->name, pdev->id);
 	pdata->mii_bus->priv = pdata;
 	pdata->mii_bus->read = smsc911x_mii_read;
 	pdata->mii_bus->write = smsc911x_mii_write;
diff --git a/drivers/net/ethernet/smsc/smsc9420.c b/drivers/net/ethernet/smsc/smsc9420.c
index a9efbdf..bffd175 100644
--- a/drivers/net/ethernet/smsc/smsc9420.c
+++ b/drivers/net/ethernet/smsc/smsc9420.c
@@ -1211,7 +1211,7 @@ static int smsc9420_mii_init(struct net_device *dev)
 		goto err_out_1;
 	}
 	pd->mii_bus->name = DRV_MDIONAME;
-	snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
+	pd->mii_bus->id = kasprintf(GFP_KERNEL, "%x",
 		(pd->pdev->bus->number << 8) | pd->pdev->devfn);
 	pd->mii_bus->priv = pd;
 	pd->mii_bus->read = smsc9420_mii_read;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 96fa2da..c72a50e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -300,19 +300,21 @@ static int stmmac_init_phy(struct net_device *dev)
 {
 	struct stmmac_priv *priv = netdev_priv(dev);
 	struct phy_device *phydev;
-	char phy_id[MII_BUS_ID_SIZE + 3];
-	char bus_id[MII_BUS_ID_SIZE];
+	const char *phy_id;
+	const char *bus_id;
 	int interface = priv->plat->interface;
 	priv->oldlink = 0;
 	priv->speed = 0;
 	priv->oldduplex = -1;
 
-	snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", priv->plat->bus_id);
-	snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
+	bus_id = kasprintf(GFP_KERNEL, "stmmac-%x", priv->plat->bus_id);
+	phy_id = kasprintf(GFP_KERNEL, PHY_ID_FMT, bus_id,
 		 priv->plat->phy_addr);
 	pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id);
 
 	phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
+	kfree(phy_id);
+	kfree(bus_id);
 
 	if (IS_ERR(phydev)) {
 		pr_err("%s: Could not attach to PHY\n", dev->name);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index da4a104..6a72265 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -158,8 +158,8 @@ int stmmac_mdio_register(struct net_device *ndev)
 	new_bus->read = &stmmac_mdio_read;
 	new_bus->write = &stmmac_mdio_write;
 	new_bus->reset = &stmmac_mdio_reset;
-	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		new_bus->name, mdio_bus_data->bus_id);
+	new_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
+			new_bus->name, mdio_bus_data->bus_id);
 	new_bus->priv = ndev;
 	new_bus->irq = irqlist;
 	new_bus->phy_mask = mdio_bus_data->phy_mask;
diff --git a/drivers/net/ethernet/ti/cpmac.c b/drivers/net/ethernet/ti/cpmac.c
index 4d9a28f..b448cca 100644
--- a/drivers/net/ethernet/ti/cpmac.c
+++ b/drivers/net/ethernet/ti/cpmac.c
@@ -205,7 +205,7 @@ struct cpmac_priv {
 	void __iomem *regs;
 	struct mii_bus *mii_bus;
 	struct phy_device *phy;
-	char phy_name[MII_BUS_ID_SIZE + 3];
+	const char *phy_name;
 	int oldlink, oldspeed, oldduplex;
 	u32 msg_enable;
 	struct net_device *dev;
@@ -1113,7 +1113,7 @@ static int external_switch;
 static int __devinit cpmac_probe(struct platform_device *pdev)
 {
 	int rc, phy_id;
-	char mdio_bus_id[MII_BUS_ID_SIZE];
+	const char *mdio_bus_id;
 	struct resource *mem;
 	struct cpmac_priv *priv;
 	struct net_device *dev;
@@ -1122,7 +1122,7 @@ static int __devinit cpmac_probe(struct platform_device *pdev)
 	pdata = pdev->dev.platform_data;
 
 	if (external_switch || dumb_switch) {
-		strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */
+		mdio_bus_id = kstrdup("0", GFP_KERNEL); /* fixed phys bus */
 		phy_id = pdev->id;
 	} else {
 		for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
@@ -1130,7 +1130,7 @@ static int __devinit cpmac_probe(struct platform_device *pdev)
 				continue;
 			if (!cpmac_mii->phy_map[phy_id])
 				continue;
-			strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
+			mdio_bus_id = kstrdup(cpmac_mii->id, GFP_KERNEL);
 			break;
 		}
 	}
@@ -1138,7 +1138,7 @@ static int __devinit cpmac_probe(struct platform_device *pdev)
 	if (phy_id == PHY_MAX_ADDR) {
 		dev_err(&pdev->dev, "no PHY present, falling back "
 					"to switch on MDIO bus 0\n");
-		strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */
+		mdio_bus_id = kstrdup("0", GFP_KERNEL); /* fixed phys bus */
 		phy_id = pdev->id;
 	}
 
@@ -1173,8 +1173,8 @@ static int __devinit cpmac_probe(struct platform_device *pdev)
 	priv->msg_enable = netif_msg_init(debug_level, 0xff);
 	memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
 
-	snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
-						mdio_bus_id, phy_id);
+	priv->phy_name= kasprintf(GFP_KERNEL, PHY_ID_FMT, mdio_bus_id, phy_id);
+	kfree(mdio_bus_id);
 
 	priv->phy = phy_connect(dev, priv->phy_name, cpmac_adjust_link, 0,
 						PHY_INTERFACE_MODE_MII);
@@ -1269,7 +1269,7 @@ int __devinit cpmac_init(void)
 	}
 
 	cpmac_mii->phy_mask = ~(mask | 0x80000000);
-	snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1");
+	cpmac_mii->id = kstrdup("cpmac-1", GFP_KERNEL);
 
 	res = mdiobus_register(cpmac_mii);
 	if (res)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index ef7c9c1..67ddf87 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -313,8 +313,8 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
 	data->bus->reset	= davinci_mdio_reset,
 	data->bus->parent	= dev;
 	data->bus->priv		= data;
-	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, pdev->id);
+	data->bus->id = kasprintf(GFP_KERNEL, "%s-%x",
+			pdev->name, pdev->id);
 
 	data->clk = clk_get(dev, NULL);
 	if (IS_ERR(data->clk)) {
diff --git a/drivers/net/ethernet/toshiba/tc35815.c b/drivers/net/ethernet/toshiba/tc35815.c
index 71b785c..8ffacd6 100644
--- a/drivers/net/ethernet/toshiba/tc35815.c
+++ b/drivers/net/ethernet/toshiba/tc35815.c
@@ -682,7 +682,7 @@ static int tc_mii_init(struct net_device *dev)
 	lp->mii_bus->name = "tc35815_mii_bus";
 	lp->mii_bus->read = tc_mdio_read;
 	lp->mii_bus->write = tc_mdio_write;
-	snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
+	lp->mii_bus->id = kasprintf(GFP_KERNEL, "%x",
 		 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
 	lp->mii_bus->priv = dev;
 	lp->mii_bus->parent = &lp->pci_dev->dev;
diff --git a/drivers/net/ethernet/xilinx/ll_temac_mdio.c b/drivers/net/ethernet/xilinx/ll_temac_mdio.c
index 8cf9d4f..aa9d0d5 100644
--- a/drivers/net/ethernet/xilinx/ll_temac_mdio.c
+++ b/drivers/net/ethernet/xilinx/ll_temac_mdio.c
@@ -86,7 +86,7 @@ int temac_mdio_setup(struct temac_local *lp, struct device_node *np)
 		return -ENOMEM;
 
 	of_address_to_resource(np, 0, &res);
-	snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
+	bus->id = kasprintf(GFP_KERNEL, "%.8llx",
 		 (unsigned long long)res.start);
 	bus->priv = lp;
 	bus->name = "Xilinx TEMAC MDIO";
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index 79013e5..c476861 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -866,7 +866,7 @@ static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev)
 		return -ENOMEM;
 
 	of_address_to_resource(np, 0, &res);
-	snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
+	bus->id = kasprintf(GFP_KERNEL, "%.8llx",
 		 (unsigned long long)res.start);
 	bus->priv = lp;
 	bus->name = "Xilinx Emaclite MDIO";
diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c
index 72a854f..3794959 100644
--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
+++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
@@ -529,7 +529,7 @@ static int ixp4xx_mdio_register(void)
 	mdio_bus->name = "IXP4xx MII Bus";
 	mdio_bus->read = &ixp4xx_mdio_read;
 	mdio_bus->write = &ixp4xx_mdio_write;
-	snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
+	mdio_bus->id = kstrdup("ixp4xx-eth-0", GFP_KERNEL);
 
 	if ((err = mdiobus_register(mdio_bus)))
 		mdiobus_free(mdio_bus);
@@ -1353,7 +1353,7 @@ static int __devinit eth_init_one(struct platform_device *pdev)
 	struct net_device *dev;
 	struct eth_plat_info *plat = pdev->dev.platform_data;
 	u32 regs_phys;
-	char phy_id[MII_BUS_ID_SIZE + 3];
+	const char *phy_id;
 	int err;
 
 	if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
@@ -1416,9 +1416,10 @@ static int __devinit eth_init_one(struct platform_device *pdev)
 	__raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
 	udelay(50);
 
-	snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy);
+	phy_id = kasprintf(GFP_KERNEL, PHY_ID_FMT, "0", plat->phy);
 	port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 0,
 				   PHY_INTERFACE_MODE_MII);
+	kfree(phy_id);
 	if (IS_ERR(port->phydev)) {
 		err = PTR_ERR(port->phydev);
 		goto err_free_mem;
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
index 633680d..947c7e1 100644
--- a/drivers/net/phy/fixed.c
+++ b/drivers/net/phy/fixed.c
@@ -220,7 +220,7 @@ static int __init fixed_mdio_bus_init(void)
 		goto err_mdiobus_reg;
 	}
 
-	snprintf(fmb->mii_bus->id, MII_BUS_ID_SIZE, "fixed-0");
+	fmb->mii_bus->id = kstrdup("fixed-0", GFP_KERNEL);
 	fmb->mii_bus->name = "Fixed MDIO Bus";
 	fmb->mii_bus->priv = fmb;
 	fmb->mii_bus->parent = &pdev->dev;
diff --git a/drivers/net/phy/mdio-gpio.c b/drivers/net/phy/mdio-gpio.c
index 50e8e5e..0a89f0b 100644
--- a/drivers/net/phy/mdio-gpio.c
+++ b/drivers/net/phy/mdio-gpio.c
@@ -116,7 +116,7 @@ static struct mii_bus * __devinit mdio_gpio_bus_init(struct device *dev,
 		if (!new_bus->irq[i])
 			new_bus->irq[i] = PHY_POLL;
 
-	snprintf(new_bus->id, MII_BUS_ID_SIZE, "gpio-%x", bus_id);
+	new_bus->id = kasprintf(GFP_KERNEL, "gpio-%x", bus_id);
 
 	if (gpio_request(bitbang->mdc, "mdc"))
 		goto out_free_bus;
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
index 826d961..1158353 100644
--- a/drivers/net/phy/mdio-octeon.c
+++ b/drivers/net/phy/mdio-octeon.c
@@ -118,7 +118,7 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev)
 	bus->mii_bus->priv = bus;
 	bus->mii_bus->irq = bus->phy_irq;
 	bus->mii_bus->name = "mdio-octeon";
-	snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	bus->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		bus->mii_bus->name, bus->unit);
 	bus->mii_bus->parent = &pdev->dev;
 
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index f320f46..6879e86 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -78,7 +78,7 @@ int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
 	if (!fixup)
 		return -ENOMEM;
 
-	strlcpy(fixup->bus_id, bus_id, sizeof(fixup->bus_id));
+	fixup->bus_id = kstrdup(bus_id, GFP_KERNEL);
 	fixup->phy_uid = phy_uid;
 	fixup->phy_uid_mask = phy_uid_mask;
 	fixup->run = run;
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index 980c079..4150655 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -166,7 +166,7 @@ struct phy_device *of_phy_connect_fixed_link(struct net_device *dev,
 					     phy_interface_t iface)
 {
 	struct device_node *net_np;
-	char bus_id[MII_BUS_ID_SIZE + 3];
+	const char *bus_id;
 	struct phy_device *phy;
 	const __be32 *phy_id;
 	int sz;
@@ -182,9 +182,10 @@ struct phy_device *of_phy_connect_fixed_link(struct net_device *dev,
 	if (!phy_id || sz < sizeof(*phy_id))
 		return NULL;
 
-	sprintf(bus_id, PHY_ID_FMT, "0", be32_to_cpu(phy_id[0]));
+	bus_id = kasprintf(GFP_KERNEL, PHY_ID_FMT, "0", be32_to_cpu(phy_id[0]));
 
 	phy = phy_connect(dev, bus_id, hndlr, 0, iface);
+	kfree(bus_id);
 	return IS_ERR(phy) ? NULL : phy;
 }
 EXPORT_SYMBOL(of_phy_connect_fixed_link);
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 2c4069f..5199386 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -5358,7 +5358,7 @@ static int __devinit et131x_pci_setup(struct pci_dev *pdev,
 	}
 
 	adapter->mii_bus->name = "et131x_eth_mii";
-	snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
+	adapter->mii_bus->id = kasprintf(GFP_KERNEL, "%x",
 		(adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
 	adapter->mii_bus->priv = netdev;
 	adapter->mii_bus->read = et131x_mdio_read;
diff --git a/include/linux/phy.h b/include/linux/phy.h
index c599f7e..bf051a7 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -78,12 +78,6 @@ typedef enum {
 /* Used when trying to connect to a specific phy (mii bus id:phy device id) */
 #define PHY_ID_FMT "%s:%02x"
 
-/*
- * Need to be a little smaller than phydev->dev.bus_id to leave room
- * for the ":%02x"
- */
-#define MII_BUS_ID_SIZE	(20 - 3)
-
 /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
    IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. */
 #define MII_ADDR_C45 (1<<30)
@@ -94,7 +88,7 @@ typedef enum {
  */
 struct mii_bus {
 	const char *name;
-	char id[MII_BUS_ID_SIZE];
+	const char *id;
 	void *priv;
 	int (*read)(struct mii_bus *bus, int phy_id, int regnum);
 	int (*write)(struct mii_bus *bus, int phy_id, int regnum, u16 val);
@@ -441,7 +435,7 @@ struct phy_driver {
 /* A Structure for boards to register fixups with the PHY Lib */
 struct phy_fixup {
 	struct list_head list;
-	char bus_id[20];
+	const char *bus_id;
 	u32 phy_uid;
 	u32 phy_uid_mask;
 	int (*run)(struct phy_device *phydev);
diff --git a/net/dsa/slave.c b/net/dsa/slave.c
index 56cf9b8..ae0e3ea 100644
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -41,7 +41,7 @@ void dsa_slave_mii_bus_init(struct dsa_switch *ds)
 	ds->slave_mii_bus->name = "dsa slave smi";
 	ds->slave_mii_bus->read = dsa_slave_phy_read;
 	ds->slave_mii_bus->write = dsa_slave_phy_write;
-	snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s:%.2x",
+	ds->slave_mii_bus->id = kasprintf(GFP_KERNEL, "%s:%.2x",
 			ds->master_mii_bus->id, ds->pd->sw_addr);
 	ds->slave_mii_bus->parent = &ds->master_mii_bus->dev;
 }
-- 
1.7.0.4




From b29396 at freescale.com  Tue Mar 20 00:27:59 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Tue, 20 Mar 2012 12:27:59 +0800
Subject: [PATCH 1/1] net: phylib: remove the length limitation of mii bus id
Message-ID: <1332217679-3703-1-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

When convert to dt, the length of old mii bus id (17 bytes) is not
sufficent to use.
For example, the bus id could be 800f0000.ethernet-1:00 in DT.

This patch removes the bus id length limitation by changing the
bus id to a const char pionter and user could dynamically set the
bus id via kasprintf function call.

Since then no users use MII_BUS_ID_SIZE any more, just remove it.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
The simplest way may just change MII_BUS_ID_SIZE to a more bigger size,
but i'm not sure that's gonna be accepted.
So changed to remove the bus id length limitation, a lot of handwork.

Since this patch changes a lot of other ethernet drivers and i did
not have condition to test it, need each corresponding driver owners
to help review.

I just greped the macro MII_BUS_ID_SIZE in the latest kernel tree and
did the replacement.
In case any one missed(may not use MII_BUS_ID_SIZE), that driver owner
should help change it.

Only tested the fec driver on i.MX28 EVK board.
---
 arch/powerpc/platforms/82xx/ep8248e.c              |    2 +-
 arch/powerpc/platforms/pasemi/gpio_mdio.c          |    2 +-
 drivers/net/ethernet/8390/ax88796.c                |    4 +---
 drivers/net/ethernet/adi/bfin_mac.c                |    3 +--
 drivers/net/ethernet/aeroflex/greth.c              |    2 +-
 drivers/net/ethernet/amd/au1000_eth.c              |    3 +--
 drivers/net/ethernet/broadcom/bcm63xx_enet.c       |    7 ++++---
 drivers/net/ethernet/broadcom/sb1250-mac.c         |    2 +-
 drivers/net/ethernet/broadcom/tg3.c                |    4 ++--
 drivers/net/ethernet/cadence/macb.c                |    2 +-
 drivers/net/ethernet/dnet.c                        |    2 +-
 drivers/net/ethernet/ethoc.c                       |    2 +-
 drivers/net/ethernet/faraday/ftgmac100.c           |    2 +-
 drivers/net/ethernet/freescale/fec.c               |   16 +++++++++-------
 drivers/net/ethernet/freescale/fec_mpc52xx_phy.c   |    2 +-
 .../net/ethernet/freescale/fs_enet/mii-bitbang.c   |    2 +-
 drivers/net/ethernet/freescale/fs_enet/mii-fec.c   |    2 +-
 drivers/net/ethernet/freescale/fsl_pq_mdio.c       |    6 +++---
 drivers/net/ethernet/freescale/fsl_pq_mdio.h       |    2 +-
 drivers/net/ethernet/lantiq_etop.c                 |    2 +-
 drivers/net/ethernet/marvell/mv643xx_eth.c         |    2 +-
 drivers/net/ethernet/marvell/pxa168_eth.c          |    2 +-
 drivers/net/ethernet/octeon/octeon_mgmt.c          |    6 +++---
 drivers/net/ethernet/rdc/r6040.c                   |    4 ++--
 drivers/net/ethernet/renesas/sh_eth.c              |    7 ++++---
 drivers/net/ethernet/s6gmac.c                      |    2 +-
 drivers/net/ethernet/smsc/smsc911x.c               |    4 ++--
 drivers/net/ethernet/smsc/smsc9420.c               |    2 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |   10 ++++++----
 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c  |    4 ++--
 drivers/net/ethernet/ti/cpmac.c                    |   16 ++++++++--------
 drivers/net/ethernet/ti/davinci_mdio.c             |    4 ++--
 drivers/net/ethernet/toshiba/tc35815.c             |    2 +-
 drivers/net/ethernet/xilinx/ll_temac_mdio.c        |    2 +-
 drivers/net/ethernet/xilinx/xilinx_emaclite.c      |    2 +-
 drivers/net/ethernet/xscale/ixp4xx_eth.c           |    9 +++++----
 drivers/net/phy/fixed.c                            |    2 +-
 drivers/net/phy/mdio-gpio.c                        |    2 +-
 drivers/net/phy/mdio-octeon.c                      |    2 +-
 drivers/net/phy/phy_device.c                       |    2 +-
 drivers/of/of_mdio.c                               |    5 +++--
 drivers/staging/et131x/et131x.c                    |    2 +-
 include/linux/phy.h                                |   10 ++--------
 net/dsa/slave.c                                    |    2 +-
 44 files changed, 86 insertions(+), 88 deletions(-)

diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c
index 10ff526..21658de 100644
--- a/arch/powerpc/platforms/82xx/ep8248e.c
+++ b/arch/powerpc/platforms/82xx/ep8248e.c
@@ -139,7 +139,7 @@ static int __devinit ep8248e_mdio_probe(struct platform_device *ofdev)
 
 	bus->name = "ep8248e-mdio-bitbang";
 	bus->parent = &ofdev->dev;
-	snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
+	bus->id = kasprintf(GFP_KERNEL, "%x", res.start);
 
 	ret = of_mdiobus_register(bus, ofdev->dev.of_node);
 	if (ret)
diff --git a/arch/powerpc/platforms/pasemi/gpio_mdio.c b/arch/powerpc/platforms/pasemi/gpio_mdio.c
index 9886296..3b55962 100644
--- a/arch/powerpc/platforms/pasemi/gpio_mdio.c
+++ b/arch/powerpc/platforms/pasemi/gpio_mdio.c
@@ -241,7 +241,7 @@ static int __devinit gpio_mdio_probe(struct platform_device *ofdev)
 	new_bus->reset = &gpio_mdio_reset;
 
 	prop = of_get_property(np, "reg", NULL);
-	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", *prop);
+	new_bus->id = kasprintf(GFP_KERNEL, "%x", *prop);
 	new_bus->priv = priv;
 
 	new_bus->irq = priv->mdio_irqs;
diff --git a/drivers/net/ethernet/8390/ax88796.c b/drivers/net/ethernet/8390/ax88796.c
index 0f92e35..c70067c 100644
--- a/drivers/net/ethernet/8390/ax88796.c
+++ b/drivers/net/ethernet/8390/ax88796.c
@@ -623,9 +623,7 @@ static int ax_mii_init(struct net_device *dev)
 
 	ax->mii_bus->name = "ax88796_mii_bus";
 	ax->mii_bus->parent = dev->dev.parent;
-	snprintf(ax->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, pdev->id);
-
+	ax->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x", pdev->name, pdev->id);
 	ax->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
 	if (!ax->mii_bus->irq) {
 		err = -ENOMEM;
diff --git a/drivers/net/ethernet/adi/bfin_mac.c b/drivers/net/ethernet/adi/bfin_mac.c
index d812a10..77d473a 100644
--- a/drivers/net/ethernet/adi/bfin_mac.c
+++ b/drivers/net/ethernet/adi/bfin_mac.c
@@ -1670,8 +1670,7 @@ static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
 	miibus->name = "bfin_mii_bus";
 	miibus->phy_mask = mii_bus_pd->phy_mask;
 
-	snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, pdev->id);
+	miibus->id = kasprintf(GFP_KERNEL, "%s-%x", pdev->name, pdev->id);
 	miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
 	if (!miibus->irq)
 		goto out_err_irq_alloc;
diff --git a/drivers/net/ethernet/aeroflex/greth.c b/drivers/net/ethernet/aeroflex/greth.c
index c885aa9..df635f2 100644
--- a/drivers/net/ethernet/aeroflex/greth.c
+++ b/drivers/net/ethernet/aeroflex/greth.c
@@ -1332,7 +1332,7 @@ static int greth_mdio_init(struct greth_private *greth)
 	}
 
 	greth->mdio->name = "greth-mdio";
-	snprintf(greth->mdio->id, MII_BUS_ID_SIZE, "%s-%d", greth->mdio->name, greth->irq);
+	greth->mdio->id = kasprintf(GFP_KERNEL, "%s-%d", greth->mdio->name, greth->irq);
 	greth->mdio->read = greth_mdio_read;
 	greth->mdio->write = greth_mdio_write;
 	greth->mdio->reset = greth_mdio_reset;
diff --git a/drivers/net/ethernet/amd/au1000_eth.c b/drivers/net/ethernet/amd/au1000_eth.c
index 8b95dd3..99e0ebb 100644
--- a/drivers/net/ethernet/amd/au1000_eth.c
+++ b/drivers/net/ethernet/amd/au1000_eth.c
@@ -1171,8 +1171,7 @@ static int __devinit au1000_probe(struct platform_device *pdev)
 	aup->mii_bus->write = au1000_mdiobus_write;
 	aup->mii_bus->reset = au1000_mdiobus_reset;
 	aup->mii_bus->name = "au1000_eth_mii";
-	snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, aup->mac_id);
+	aup->mii_bus->id =  kasprintf(GFP_KERNEL, "%s-%x", pdev->name, aup->mac_id);
 	aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
 	if (aup->mii_bus->irq == NULL)
 		goto err_out;
diff --git a/drivers/net/ethernet/broadcom/bcm63xx_enet.c b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
index c7ca7ec..5635be3 100644
--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
@@ -787,7 +787,7 @@ static int bcm_enet_open(struct net_device *dev)
 	struct phy_device *phydev;
 	int i, ret;
 	unsigned int size;
-	char phy_id[MII_BUS_ID_SIZE + 3];
+	const char *phy_id;
 	void *p;
 	u32 val;
 
@@ -796,12 +796,13 @@ static int bcm_enet_open(struct net_device *dev)
 
 	if (priv->has_phy) {
 		/* connect to PHY */
-		snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
+		phy_id = kasprintf(GFP_KERNEL, PHY_ID_FMT,
 			 priv->mii_bus->id, priv->phy_id);
 
 		phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, 0,
 				     PHY_INTERFACE_MODE_MII);
 
+		kfree(phy_id);
 		if (IS_ERR(phydev)) {
 			dev_err(kdev, "could not attach to PHY\n");
 			return PTR_ERR(phydev);
@@ -1727,7 +1728,7 @@ static int __devinit bcm_enet_probe(struct platform_device *pdev)
 		bus->priv = priv;
 		bus->read = bcm_enet_mdio_read_phylib;
 		bus->write = bcm_enet_mdio_write_phylib;
-		sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
+		bus->id = kasprintf(GFP_KERNEL, "%s-%d", pdev->name, priv->mac_id);
 
 		/* only probe bus where we think the PHY is, because
 		 * the mdio read operation return 0 instead of 0xffff
diff --git a/drivers/net/ethernet/broadcom/sb1250-mac.c b/drivers/net/ethernet/broadcom/sb1250-mac.c
index 084904c..7fd5654 100644
--- a/drivers/net/ethernet/broadcom/sb1250-mac.c
+++ b/drivers/net/ethernet/broadcom/sb1250-mac.c
@@ -2259,7 +2259,7 @@ static int sbmac_init(struct platform_device *pldev, long long base)
 	}
 
 	sc->mii_bus->name = sbmac_mdio_string;
-	snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	sc->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		pldev->name, idx);
 	sc->mii_bus->priv = sc;
 	sc->mii_bus->read = sbmac_mii_read;
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 35c2a20..df6c3a3 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -1328,8 +1328,8 @@ static int tg3_mdio_init(struct tg3 *tp)
 		return -ENOMEM;
 
 	tp->mdio_bus->name     = "tg3 mdio bus";
-	snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
-		 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
+	tp->mdio_bus->id = kasprintf(GFP_KERNEL, "%x",
+		(tp->pdev->bus->number << 8) | tp->pdev->devfn);
 	tp->mdio_bus->priv     = tp;
 	tp->mdio_bus->parent   = &tp->pdev->dev;
 	tp->mdio_bus->read     = &tg3_mdio_read;
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 2320068..62e4465 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -243,7 +243,7 @@ static int macb_mii_init(struct macb *bp)
 	bp->mii_bus->read = &macb_mdio_read;
 	bp->mii_bus->write = &macb_mdio_write;
 	bp->mii_bus->reset = &macb_mdio_reset;
-	snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	bp->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		bp->pdev->name, bp->pdev->id);
 	bp->mii_bus->priv = bp;
 	bp->mii_bus->parent = &bp->dev->dev;
diff --git a/drivers/net/ethernet/dnet.c b/drivers/net/ethernet/dnet.c
index 925c9ba..18c3c92 100644
--- a/drivers/net/ethernet/dnet.c
+++ b/drivers/net/ethernet/dnet.c
@@ -325,7 +325,7 @@ static int dnet_mii_init(struct dnet *bp)
 	bp->mii_bus->write = &dnet_mdio_write;
 	bp->mii_bus->reset = &dnet_mdio_reset;
 
-	snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	bp->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		bp->pdev->name, bp->pdev->id);
 
 	bp->mii_bus->priv = bp;
diff --git a/drivers/net/ethernet/ethoc.c b/drivers/net/ethernet/ethoc.c
index 60f0e78..e9195a5 100644
--- a/drivers/net/ethernet/ethoc.c
+++ b/drivers/net/ethernet/ethoc.c
@@ -1063,7 +1063,7 @@ static int __devinit ethoc_probe(struct platform_device *pdev)
 	}
 
 	priv->mdio->name = "ethoc-mdio";
-	snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
+	priv->mdio->id = kasprintf(GFP_KERNEL, "%s-%d",
 			priv->mdio->name, pdev->id);
 	priv->mdio->read = ethoc_mdio_read;
 	priv->mdio->write = ethoc_mdio_write;
diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c
index 47f85c3..a2901db 100644
--- a/drivers/net/ethernet/faraday/ftgmac100.c
+++ b/drivers/net/ethernet/faraday/ftgmac100.c
@@ -1256,7 +1256,7 @@ static int ftgmac100_probe(struct platform_device *pdev)
 	}
 
 	priv->mii_bus->name = "ftgmac100_mdio";
-	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "ftgmac100_mii");
+	priv->mii_bus->id = kstrdup("ftgmac100_mii", GFP_KERNEL);
 
 	priv->mii_bus->priv = netdev;
 	priv->mii_bus->read = ftgmac100_mdiobus_read;
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index e92ef1b..2551181 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -961,8 +961,8 @@ static int fec_enet_mii_probe(struct net_device *ndev)
 	const struct platform_device_id *id_entry =
 				platform_get_device_id(fep->pdev);
 	struct phy_device *phy_dev = NULL;
-	char mdio_bus_id[MII_BUS_ID_SIZE];
-	char phy_name[MII_BUS_ID_SIZE + 3];
+	const char *mdio_bus_id;
+	const char *phy_name;
 	int phy_id;
 	int dev_id = fep->dev_id;
 
@@ -978,7 +978,7 @@ static int fec_enet_mii_probe(struct net_device *ndev)
 			continue;
 		if (dev_id--)
 			continue;
-		strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
+		mdio_bus_id = kstrdup(fep->mii_bus->id, GFP_KERNEL);
 		break;
 	}
 
@@ -986,13 +986,15 @@ static int fec_enet_mii_probe(struct net_device *ndev)
 		printk(KERN_INFO
 			"%s: no PHY, assuming direct connection to switch\n",
 			ndev->name);
-		strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
+		mdio_bus_id = kstrdup("fixed-0", GFP_KERNEL);
 		phy_id = 0;
 	}
 
-	snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
+	phy_name= kasprintf(GFP_KERNEL, PHY_ID_FMT, mdio_bus_id, phy_id);
 	phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
 			      fep->phy_interface);
+	kfree(mdio_bus_id);
+	kfree(phy_name);
 	if (IS_ERR(phy_dev)) {
 		printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
 		return PTR_ERR(phy_dev);
@@ -1080,8 +1082,8 @@ static int fec_enet_mii_init(struct platform_device *pdev)
 	fep->mii_bus->read = fec_enet_mdio_read;
 	fep->mii_bus->write = fec_enet_mdio_write;
 	fep->mii_bus->reset = fec_enet_mdio_reset;
-	snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, fep->dev_id + 1);
+	fep->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
+					pdev->name, fep->dev_id +1);
 	fep->mii_bus->priv = fep;
 	fep->mii_bus->parent = &pdev->dev;
 
diff --git a/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c b/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c
index 360a578..7724be7 100644
--- a/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c
+++ b/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c
@@ -96,7 +96,7 @@ static int mpc52xx_fec_mdio_probe(struct platform_device *of)
 		goto out_free;
 	}
 
-	snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
+	bus->id = kasprintf(GFP_KERNEL, "%x", res.start);
 	bus->priv = priv;
 
 	bus->parent = dev;
diff --git a/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c b/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c
index 0f2d1a7..9e6eac9 100644
--- a/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c
+++ b/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c
@@ -127,7 +127,7 @@ static int __devinit fs_mii_bitbang_init(struct mii_bus *bus,
 	 * we get is an int, and the odds of multiple bitbang mdio buses
 	 * is low enough that it's not worth going too crazy.
 	 */
-	snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
+	bus->id = kasprintf(GFP_KERNEL, "%x", res.start);
 
 	data = of_get_property(np, "fsl,mdio-pin", &len);
 	if (!data || len != 4)
diff --git a/drivers/net/ethernet/freescale/fs_enet/mii-fec.c b/drivers/net/ethernet/freescale/fs_enet/mii-fec.c
index 55bb867..5242f4d 100644
--- a/drivers/net/ethernet/freescale/fs_enet/mii-fec.c
+++ b/drivers/net/ethernet/freescale/fs_enet/mii-fec.c
@@ -134,7 +134,7 @@ static int __devinit fs_enet_mdio_probe(struct platform_device *ofdev)
 	if (ret)
 		goto out_res;
 
-	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", res.start);
+	new_bus->id = kasprintf(GFP_KERNEL, "%x", res.start);
 
 	fec->fecp = ioremap(res.start, resource_size(&res));
 	if (!fec->fecp)
diff --git a/drivers/net/ethernet/freescale/fsl_pq_mdio.c b/drivers/net/ethernet/freescale/fsl_pq_mdio.c
index 9eb8159..773acd5 100644
--- a/drivers/net/ethernet/freescale/fsl_pq_mdio.c
+++ b/drivers/net/ethernet/freescale/fsl_pq_mdio.c
@@ -169,7 +169,7 @@ static int fsl_pq_mdio_reset(struct mii_bus *bus)
 	return 0;
 }
 
-void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
+void fsl_pq_mdio_bus_name(char **name, struct device_node *np)
 {
 	const u32 *addr;
 	u64 taddr = OF_BAD_ADDR;
@@ -178,7 +178,7 @@ void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
 	if (addr)
 		taddr = of_translate_address(np, addr);
 
-	snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
+	*name = kasprintf(GFP_KERNEL, "%s@%llx", np->name,
 		(unsigned long long)taddr);
 }
 EXPORT_SYMBOL_GPL(fsl_pq_mdio_bus_name);
@@ -277,7 +277,7 @@ static int fsl_pq_mdio_probe(struct platform_device *ofdev)
 	new_bus->write = &fsl_pq_mdio_write,
 	new_bus->reset = &fsl_pq_mdio_reset,
 	new_bus->priv = priv;
-	fsl_pq_mdio_bus_name(new_bus->id, np);
+	fsl_pq_mdio_bus_name(&new_bus->id, np);
 
 	addrp = of_get_address(np, 0, &size, NULL);
 	if (!addrp) {
diff --git a/drivers/net/ethernet/freescale/fsl_pq_mdio.h b/drivers/net/ethernet/freescale/fsl_pq_mdio.h
index bd17a2a..b563ef7 100644
--- a/drivers/net/ethernet/freescale/fsl_pq_mdio.h
+++ b/drivers/net/ethernet/freescale/fsl_pq_mdio.h
@@ -48,5 +48,5 @@ int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
 int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs, int mii_id, int regnum);
 int __init fsl_pq_mdio_init(void);
 void fsl_pq_mdio_exit(void);
-void fsl_pq_mdio_bus_name(char *name, struct device_node *np);
+void fsl_pq_mdio_bus_name(char **name, struct device_node *np);
 #endif /* FSL_PQ_MDIO_H */
diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
index 85e2c6c..742e7dd 100644
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -437,7 +437,7 @@ ltq_etop_mdio_init(struct net_device *dev)
 	priv->mii_bus->read = ltq_etop_mdio_rd;
 	priv->mii_bus->write = ltq_etop_mdio_wr;
 	priv->mii_bus->name = "ltq_mii";
-	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	priv->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		priv->pdev->name, priv->pdev->id);
 	priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
 	if (!priv->mii_bus->irq) {
diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
index 9edecfa..496b24c 100644
--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
@@ -2627,7 +2627,7 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 		msp->smi_bus->name = "mv643xx_eth smi";
 		msp->smi_bus->read = smi_bus_read;
 		msp->smi_bus->write = smi_bus_write,
-		snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
+		msp->smi_bus->id = kasprintf(GFP_KERNEL, "%s-%d",
 			pdev->name, pdev->id);
 		msp->smi_bus->parent = &pdev->dev;
 		msp->smi_bus->phy_mask = 0xffffffff;
diff --git a/drivers/net/ethernet/marvell/pxa168_eth.c b/drivers/net/ethernet/marvell/pxa168_eth.c
index 953ba58..bf19af7 100644
--- a/drivers/net/ethernet/marvell/pxa168_eth.c
+++ b/drivers/net/ethernet/marvell/pxa168_eth.c
@@ -1552,7 +1552,7 @@ static int pxa168_eth_probe(struct platform_device *pdev)
 	pep->smi_bus->name = "pxa168_eth smi";
 	pep->smi_bus->read = pxa168_smi_read;
 	pep->smi_bus->write = pxa168_smi_write;
-	snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
+	pep->smi_bus->id = kasprintf(GFP_KERNEL, "%s-%d",
 		pdev->name, pdev->id);
 	pep->smi_bus->parent = &pdev->dev;
 	pep->smi_bus->phy_mask = 0xffffffff;
diff --git a/drivers/net/ethernet/octeon/octeon_mgmt.c b/drivers/net/ethernet/octeon/octeon_mgmt.c
index cd827ff..54380df 100644
--- a/drivers/net/ethernet/octeon/octeon_mgmt.c
+++ b/drivers/net/ethernet/octeon/octeon_mgmt.c
@@ -670,7 +670,7 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev)
 static int octeon_mgmt_init_phy(struct net_device *netdev)
 {
 	struct octeon_mgmt *p = netdev_priv(netdev);
-	char phy_id[MII_BUS_ID_SIZE + 3];
+	const char *phy_id;
 
 	if (octeon_is_simulation()) {
 		/* No PHYs in the simulator. */
@@ -678,11 +678,11 @@ static int octeon_mgmt_init_phy(struct net_device *netdev)
 		return 0;
 	}
 
-	snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "mdio-octeon-0", p->port);
+	phy_id = kasprintf(GFP_KERNEL, PHY_ID_FMT, "mdio-octeon-0", p->port);
 
 	p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0,
 				PHY_INTERFACE_MODE_MII);
-
+	kfree(phy_id);
 	if (IS_ERR(p->phydev)) {
 		p->phydev = NULL;
 		return -1;
diff --git a/drivers/net/ethernet/rdc/r6040.c b/drivers/net/ethernet/rdc/r6040.c
index cb0eca8..9d890b2 100644
--- a/drivers/net/ethernet/rdc/r6040.c
+++ b/drivers/net/ethernet/rdc/r6040.c
@@ -1181,8 +1181,8 @@ static int __devinit r6040_init_one(struct pci_dev *pdev,
 	lp->mii_bus->write = r6040_mdiobus_write;
 	lp->mii_bus->reset = r6040_mdiobus_reset;
 	lp->mii_bus->name = "r6040_eth_mii";
-	snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		dev_name(&pdev->dev), card_idx);
+	lp->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
+			dev_name(&pdev->dev), card_idx);
 	lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
 	if (!lp->mii_bus->irq) {
 		dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index 87b6501..a81a33b 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -1215,10 +1215,10 @@ static void sh_eth_adjust_link(struct net_device *ndev)
 static int sh_eth_phy_init(struct net_device *ndev)
 {
 	struct sh_eth_private *mdp = netdev_priv(ndev);
-	char phy_id[MII_BUS_ID_SIZE + 3];
+	const char *phy_id;
 	struct phy_device *phydev = NULL;
 
-	snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
+	phy_id = kasprintf(GFP_KERNEL, PHY_ID_FMT,
 		mdp->mii_bus->id , mdp->phy_id);
 
 	mdp->link = PHY_DOWN;
@@ -1228,6 +1228,7 @@ static int sh_eth_phy_init(struct net_device *ndev)
 	/* Try connect to PHY */
 	phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
 				0, mdp->phy_interface);
+	kfree(phy_id);
 	if (IS_ERR(phydev)) {
 		dev_err(&ndev->dev, "phy_connect failed\n");
 		return PTR_ERR(phydev);
@@ -1704,7 +1705,7 @@ static int sh_mdio_init(struct net_device *ndev, int id,
 	/* Hook up MII support for ethtool */
 	mdp->mii_bus->name = "sh_mii";
 	mdp->mii_bus->parent = &ndev->dev;
-	snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	mdp->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		mdp->pdev->name, id);
 
 	/* PHY IRQ */
diff --git a/drivers/net/ethernet/s6gmac.c b/drivers/net/ethernet/s6gmac.c
index 22e9c01..dd5f29b 100644
--- a/drivers/net/ethernet/s6gmac.c
+++ b/drivers/net/ethernet/s6gmac.c
@@ -1004,7 +1004,7 @@ static int __devinit s6gmac_probe(struct platform_device *pdev)
 	mb->write = s6mii_write;
 	mb->reset = s6mii_reset;
 	mb->priv = pd;
-	snprintf(mb->id, MII_BUS_ID_SIZE, "%s-%x", pdev->name, pdev->id);
+	mb->id = kasprintf(GFP_KERNEL, "%s-%x", pdev->name, pdev->id);
 	mb->phy_mask = ~(1 << 0);
 	mb->irq = &pd->mii.irq[0];
 	for (i = 0; i < PHY_MAX_ADDR; i++) {
diff --git a/drivers/net/ethernet/smsc/smsc911x.c b/drivers/net/ethernet/smsc/smsc911x.c
index 24d2df0..4aab696 100644
--- a/drivers/net/ethernet/smsc/smsc911x.c
+++ b/drivers/net/ethernet/smsc/smsc911x.c
@@ -1044,8 +1044,8 @@ static int __devinit smsc911x_mii_init(struct platform_device *pdev,
 	}
 
 	pdata->mii_bus->name = SMSC_MDIONAME;
-	snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, pdev->id);
+	pdata->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
+			pdev->name, pdev->id);
 	pdata->mii_bus->priv = pdata;
 	pdata->mii_bus->read = smsc911x_mii_read;
 	pdata->mii_bus->write = smsc911x_mii_write;
diff --git a/drivers/net/ethernet/smsc/smsc9420.c b/drivers/net/ethernet/smsc/smsc9420.c
index a9efbdf..bffd175 100644
--- a/drivers/net/ethernet/smsc/smsc9420.c
+++ b/drivers/net/ethernet/smsc/smsc9420.c
@@ -1211,7 +1211,7 @@ static int smsc9420_mii_init(struct net_device *dev)
 		goto err_out_1;
 	}
 	pd->mii_bus->name = DRV_MDIONAME;
-	snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
+	pd->mii_bus->id = kasprintf(GFP_KERNEL, "%x",
 		(pd->pdev->bus->number << 8) | pd->pdev->devfn);
 	pd->mii_bus->priv = pd;
 	pd->mii_bus->read = smsc9420_mii_read;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 6ee593a..150b130 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -300,19 +300,21 @@ static int stmmac_init_phy(struct net_device *dev)
 {
 	struct stmmac_priv *priv = netdev_priv(dev);
 	struct phy_device *phydev;
-	char phy_id[MII_BUS_ID_SIZE + 3];
-	char bus_id[MII_BUS_ID_SIZE];
+	const char *phy_id;
+	const char *bus_id;
 	int interface = priv->plat->interface;
 	priv->oldlink = 0;
 	priv->speed = 0;
 	priv->oldduplex = -1;
 
-	snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", priv->plat->bus_id);
-	snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
+	bus_id = kasprintf(GFP_KERNEL, "stmmac-%x", priv->plat->bus_id);
+	phy_id = kasprintf(GFP_KERNEL, PHY_ID_FMT, bus_id,
 		 priv->plat->phy_addr);
 	pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id);
 
 	phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
+	kfree(phy_id);
+	kfree(bus_id);
 
 	if (IS_ERR(phydev)) {
 		pr_err("%s: Could not attach to PHY\n", dev->name);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index 7319532..269ff54 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -158,8 +158,8 @@ int stmmac_mdio_register(struct net_device *ndev)
 	new_bus->read = &stmmac_mdio_read;
 	new_bus->write = &stmmac_mdio_write;
 	new_bus->reset = &stmmac_mdio_reset;
-	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		new_bus->name, mdio_bus_data->bus_id);
+	new_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
+			new_bus->name, mdio_bus_data->bus_id);
 	new_bus->priv = ndev;
 	new_bus->irq = irqlist;
 	new_bus->phy_mask = mdio_bus_data->phy_mask;
diff --git a/drivers/net/ethernet/ti/cpmac.c b/drivers/net/ethernet/ti/cpmac.c
index cbc8df7..64cde9f 100644
--- a/drivers/net/ethernet/ti/cpmac.c
+++ b/drivers/net/ethernet/ti/cpmac.c
@@ -205,7 +205,7 @@ struct cpmac_priv {
 	void __iomem *regs;
 	struct mii_bus *mii_bus;
 	struct phy_device *phy;
-	char phy_name[MII_BUS_ID_SIZE + 3];
+	const char *phy_name;
 	int oldlink, oldspeed, oldduplex;
 	u32 msg_enable;
 	struct net_device *dev;
@@ -1113,7 +1113,7 @@ static int external_switch;
 static int __devinit cpmac_probe(struct platform_device *pdev)
 {
 	int rc, phy_id;
-	char mdio_bus_id[MII_BUS_ID_SIZE];
+	const char *mdio_bus_id;
 	struct resource *mem;
 	struct cpmac_priv *priv;
 	struct net_device *dev;
@@ -1122,7 +1122,7 @@ static int __devinit cpmac_probe(struct platform_device *pdev)
 	pdata = pdev->dev.platform_data;
 
 	if (external_switch || dumb_switch) {
-		strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
+		mdio_bus_id = kstrdup("fixed-0", GFP_KERNEL); /* fixed phys bus */
 		phy_id = pdev->id;
 	} else {
 		for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
@@ -1130,7 +1130,7 @@ static int __devinit cpmac_probe(struct platform_device *pdev)
 				continue;
 			if (!cpmac_mii->phy_map[phy_id])
 				continue;
-			strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
+			mdio_bus_id = kstrdup(cpmac_mii->id, GFP_KERNEL);
 			break;
 		}
 	}
@@ -1138,7 +1138,7 @@ static int __devinit cpmac_probe(struct platform_device *pdev)
 	if (phy_id == PHY_MAX_ADDR) {
 		dev_err(&pdev->dev, "no PHY present, falling back "
 					"to switch on MDIO bus 0\n");
-		strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
+		mdio_bus_id = kstrdup("fixed-0", GFP_KERNEL); /* fixed phys bus */
 		phy_id = pdev->id;
 	}
 
@@ -1173,8 +1173,8 @@ static int __devinit cpmac_probe(struct platform_device *pdev)
 	priv->msg_enable = netif_msg_init(debug_level, 0xff);
 	memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
 
-	snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
-						mdio_bus_id, phy_id);
+	priv->phy_name= kasprintf(GFP_KERNEL, PHY_ID_FMT, mdio_bus_id, phy_id);
+	kfree(mdio_bus_id);
 
 	priv->phy = phy_connect(dev, priv->phy_name, cpmac_adjust_link, 0,
 						PHY_INTERFACE_MODE_MII);
@@ -1269,7 +1269,7 @@ int __devinit cpmac_init(void)
 	}
 
 	cpmac_mii->phy_mask = ~(mask | 0x80000000);
-	snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1");
+	cpmac_mii->id = kstrdup("cpmac-1", GFP_KERNEL);
 
 	res = mdiobus_register(cpmac_mii);
 	if (res)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index af8b8fc..2b99461 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -313,8 +313,8 @@ static int __devinit davinci_mdio_probe(struct platform_device *pdev)
 	data->bus->reset	= davinci_mdio_reset,
 	data->bus->parent	= dev;
 	data->bus->priv		= data;
-	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
-		pdev->name, pdev->id);
+	data->bus->id = kasprintf(GFP_KERNEL, "%s-%x",
+			pdev->name, pdev->id);
 
 	data->clk = clk_get(dev, NULL);
 	if (IS_ERR(data->clk)) {
diff --git a/drivers/net/ethernet/toshiba/tc35815.c b/drivers/net/ethernet/toshiba/tc35815.c
index 71b785c..8ffacd6 100644
--- a/drivers/net/ethernet/toshiba/tc35815.c
+++ b/drivers/net/ethernet/toshiba/tc35815.c
@@ -682,7 +682,7 @@ static int tc_mii_init(struct net_device *dev)
 	lp->mii_bus->name = "tc35815_mii_bus";
 	lp->mii_bus->read = tc_mdio_read;
 	lp->mii_bus->write = tc_mdio_write;
-	snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
+	lp->mii_bus->id = kasprintf(GFP_KERNEL, "%x",
 		 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
 	lp->mii_bus->priv = dev;
 	lp->mii_bus->parent = &lp->pci_dev->dev;
diff --git a/drivers/net/ethernet/xilinx/ll_temac_mdio.c b/drivers/net/ethernet/xilinx/ll_temac_mdio.c
index 8cf9d4f..aa9d0d5 100644
--- a/drivers/net/ethernet/xilinx/ll_temac_mdio.c
+++ b/drivers/net/ethernet/xilinx/ll_temac_mdio.c
@@ -86,7 +86,7 @@ int temac_mdio_setup(struct temac_local *lp, struct device_node *np)
 		return -ENOMEM;
 
 	of_address_to_resource(np, 0, &res);
-	snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
+	bus->id = kasprintf(GFP_KERNEL, "%.8llx",
 		 (unsigned long long)res.start);
 	bus->priv = lp;
 	bus->name = "Xilinx TEMAC MDIO";
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index 79013e5..c476861 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -866,7 +866,7 @@ static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev)
 		return -ENOMEM;
 
 	of_address_to_resource(np, 0, &res);
-	snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
+	bus->id = kasprintf(GFP_KERNEL, "%.8llx",
 		 (unsigned long long)res.start);
 	bus->priv = lp;
 	bus->name = "Xilinx Emaclite MDIO";
diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c
index 41a8b5a..d44a3ae 100644
--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
+++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
@@ -529,7 +529,7 @@ static int ixp4xx_mdio_register(void)
 	mdio_bus->name = "IXP4xx MII Bus";
 	mdio_bus->read = &ixp4xx_mdio_read;
 	mdio_bus->write = &ixp4xx_mdio_write;
-	snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
+	mdio_bus->id = kstrdup("ixp4xx-eth-0", GFP_KERNEL);
 
 	if ((err = mdiobus_register(mdio_bus)))
 		mdiobus_free(mdio_bus);
@@ -1353,7 +1353,7 @@ static int __devinit eth_init_one(struct platform_device *pdev)
 	struct net_device *dev;
 	struct eth_plat_info *plat = pdev->dev.platform_data;
 	u32 regs_phys;
-	char phy_id[MII_BUS_ID_SIZE + 3];
+	const char *phy_id;
 	int err;
 
 	if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
@@ -1416,10 +1416,11 @@ static int __devinit eth_init_one(struct platform_device *pdev)
 	__raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
 	udelay(50);
 
-	snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
-		mdio_bus->id, plat->phy);
+	phy_id = kasprintf(GFP_KERNEL, PHY_ID_FMT,
+			mdio_bus->id, plat->phy);
 	port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 0,
 				   PHY_INTERFACE_MODE_MII);
+	kfree(phy_id);
 	if (IS_ERR(port->phydev)) {
 		err = PTR_ERR(port->phydev);
 		goto err_free_mem;
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
index 633680d..947c7e1 100644
--- a/drivers/net/phy/fixed.c
+++ b/drivers/net/phy/fixed.c
@@ -220,7 +220,7 @@ static int __init fixed_mdio_bus_init(void)
 		goto err_mdiobus_reg;
 	}
 
-	snprintf(fmb->mii_bus->id, MII_BUS_ID_SIZE, "fixed-0");
+	fmb->mii_bus->id = kstrdup("fixed-0", GFP_KERNEL);
 	fmb->mii_bus->name = "Fixed MDIO Bus";
 	fmb->mii_bus->priv = fmb;
 	fmb->mii_bus->parent = &pdev->dev;
diff --git a/drivers/net/phy/mdio-gpio.c b/drivers/net/phy/mdio-gpio.c
index 50e8e5e..0a89f0b 100644
--- a/drivers/net/phy/mdio-gpio.c
+++ b/drivers/net/phy/mdio-gpio.c
@@ -116,7 +116,7 @@ static struct mii_bus * __devinit mdio_gpio_bus_init(struct device *dev,
 		if (!new_bus->irq[i])
 			new_bus->irq[i] = PHY_POLL;
 
-	snprintf(new_bus->id, MII_BUS_ID_SIZE, "gpio-%x", bus_id);
+	new_bus->id = kasprintf(GFP_KERNEL, "gpio-%x", bus_id);
 
 	if (gpio_request(bitbang->mdc, "mdc"))
 		goto out_free_bus;
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
index 826d961..1158353 100644
--- a/drivers/net/phy/mdio-octeon.c
+++ b/drivers/net/phy/mdio-octeon.c
@@ -118,7 +118,7 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev)
 	bus->mii_bus->priv = bus;
 	bus->mii_bus->irq = bus->phy_irq;
 	bus->mii_bus->name = "mdio-octeon";
-	snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+	bus->mii_bus->id = kasprintf(GFP_KERNEL, "%s-%x",
 		bus->mii_bus->name, bus->unit);
 	bus->mii_bus->parent = &pdev->dev;
 
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index f320f46..6879e86 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -78,7 +78,7 @@ int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask,
 	if (!fixup)
 		return -ENOMEM;
 
-	strlcpy(fixup->bus_id, bus_id, sizeof(fixup->bus_id));
+	fixup->bus_id = kstrdup(bus_id, GFP_KERNEL);
 	fixup->phy_uid = phy_uid;
 	fixup->phy_uid_mask = phy_uid_mask;
 	fixup->run = run;
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index 483c0ad..b4d7d29 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -166,7 +166,7 @@ struct phy_device *of_phy_connect_fixed_link(struct net_device *dev,
 					     phy_interface_t iface)
 {
 	struct device_node *net_np;
-	char bus_id[MII_BUS_ID_SIZE + 3];
+	const char *bus_id;
 	struct phy_device *phy;
 	const __be32 *phy_id;
 	int sz;
@@ -182,9 +182,10 @@ struct phy_device *of_phy_connect_fixed_link(struct net_device *dev,
 	if (!phy_id || sz < sizeof(*phy_id))
 		return NULL;
 
-	sprintf(bus_id, PHY_ID_FMT, "fixed-0", be32_to_cpu(phy_id[0]));
+	bus_id = kasprintf(GFP_KERNEL, PHY_ID_FMT, "fixed-0", be32_to_cpu(phy_id[0]));
 
 	phy = phy_connect(dev, bus_id, hndlr, 0, iface);
+	kfree(bus_id);
 	return IS_ERR(phy) ? NULL : phy;
 }
 EXPORT_SYMBOL(of_phy_connect_fixed_link);
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 2c4069f..5199386 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -5358,7 +5358,7 @@ static int __devinit et131x_pci_setup(struct pci_dev *pdev,
 	}
 
 	adapter->mii_bus->name = "et131x_eth_mii";
-	snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
+	adapter->mii_bus->id = kasprintf(GFP_KERNEL, "%x",
 		(adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
 	adapter->mii_bus->priv = netdev;
 	adapter->mii_bus->read = et131x_mdio_read;
diff --git a/include/linux/phy.h b/include/linux/phy.h
index c599f7e..bf051a7 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -78,12 +78,6 @@ typedef enum {
 /* Used when trying to connect to a specific phy (mii bus id:phy device id) */
 #define PHY_ID_FMT "%s:%02x"
 
-/*
- * Need to be a little smaller than phydev->dev.bus_id to leave room
- * for the ":%02x"
- */
-#define MII_BUS_ID_SIZE	(20 - 3)
-
 /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
    IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. */
 #define MII_ADDR_C45 (1<<30)
@@ -94,7 +88,7 @@ typedef enum {
  */
 struct mii_bus {
 	const char *name;
-	char id[MII_BUS_ID_SIZE];
+	const char *id;
 	void *priv;
 	int (*read)(struct mii_bus *bus, int phy_id, int regnum);
 	int (*write)(struct mii_bus *bus, int phy_id, int regnum, u16 val);
@@ -441,7 +435,7 @@ struct phy_driver {
 /* A Structure for boards to register fixups with the PHY Lib */
 struct phy_fixup {
 	struct list_head list;
-	char bus_id[20];
+	const char *bus_id;
 	u32 phy_uid;
 	u32 phy_uid_mask;
 	int (*run)(struct phy_device *phydev);
diff --git a/net/dsa/slave.c b/net/dsa/slave.c
index 56cf9b8..ae0e3ea 100644
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -41,7 +41,7 @@ void dsa_slave_mii_bus_init(struct dsa_switch *ds)
 	ds->slave_mii_bus->name = "dsa slave smi";
 	ds->slave_mii_bus->read = dsa_slave_phy_read;
 	ds->slave_mii_bus->write = dsa_slave_phy_write;
-	snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s:%.2x",
+	ds->slave_mii_bus->id = kasprintf(GFP_KERNEL, "%s:%.2x",
 			ds->master_mii_bus->id, ds->pd->sw_addr);
 	ds->slave_mii_bus->parent = &ds->master_mii_bus->dev;
 }
-- 
1.7.0.4




From thierry.reding at avionic-design.de  Tue Mar 20 01:51:22 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 20 Mar 2012 06:51:22 +0100
Subject: [PATCH v4 03/10] pwm: Add device tree support
In-Reply-To: <4F67E7A3.3090603@wwwdotorg.org>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-4-git-send-email-thierry.reding@avionic-design.de>
 <4F67E7A3.3090603@wwwdotorg.org>
Message-ID: <20120320055122.GA25778@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> On 03/14/2012 09:56 AM, Thierry Reding wrote:
> > This patch adds helpers to support device tree bindings for the generic
> > PWM API. Device tree binding documentation for PWM controllers is also
> > provided.
> ...
> > +static struct pwm_device *of_pwm_simple_xlate(struct pwm_chip *pc,
> > +					      const struct of_phandle_args *args)
> ...
> > +	if (args->args_count < pc->of_pwm_n_cells)
> > +		return ERR_PTR(-EINVAL);
> 
> I think you can drop that error-check given the code quoted below?
> 
> (and if not, shouldn't it be != not >= ?)
> 
> > +struct pwm_device *of_pwm_request(struct device_node *np,
> > +				  const char *propname, int index)
> ...
> > +	if (args.args_count != pc->of_pwm_n_cells) {
> > +		pr_debug("%s: wrong #pwm-cells for %s\n", np->full_name,
> > +			 args.np->full_name);
> > +		pwm = ERR_PTR(-EINVAL);
> > +		goto put;
> > +	}
> > +
> > +	pwm = pc->of_xlate(pc, &args);

Yes, you're right. It is completely redundant.

Thierry
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From thierry.reding at avionic-design.de  Tue Mar 20 01:59:30 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 20 Mar 2012 06:59:30 +0100
Subject: [PATCH v4 01/10] PWM: add pwm framework support
In-Reply-To: <4F67E38F.6080300@wwwdotorg.org>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-2-git-send-email-thierry.reding@avionic-design.de>
 <4F67E38F.6080300@wwwdotorg.org>
Message-ID: <20120320055930.GB25778@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> On 03/14/2012 09:56 AM, Thierry Reding wrote:
> > From: Sascha Hauer <s.hauer at pengutronix.de>
> > 
> > This patch adds framework support for PWM (pulse width modulation) devices.
> ...
> > diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
> ...
> > +/**
> > + * pwmchip_add() - register a new pwm
> > + * @chip: the pwm
> > + *
> > + * register a new pwm. pwm->pwm_id must be initialized. if pwm_id < 0 then
> > + * a dynamically assigned id will be used, otherwise the id specified,
> > + */
> 
> I don't see anywhere in the code that implements "if pwm_id < 0 then a
> dynamically assigned id will be used".

The second patch in the series fixes up this comment when the functionality
is properly implemented. I still wanted to go over the first patch and fix up
some minor things, so maybe I'll fix this up as I go along.

Thierry
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From shawn.guo at linaro.org  Tue Mar 20 03:20:20 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 20 Mar 2012 15:20:20 +0800
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <1332214706-675-2-git-send-email-skannan@codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
Message-ID: <20120320072018.GC32469@S2101-09.ap.freescale.net>

On Mon, Mar 19, 2012 at 08:38:26PM -0700, Saravana Kannan wrote:
> This has a couple of advantages:
> * Completely hides struct clk from many clock platform drivers and static
>   clock initialization code.
> * Simplifies the generic clk_register() function and allows adding optional
>   fields in the future without modifying the function signature.
> * Allows for simpler static initialization of clocks on all platforms by
>   removing the need for forward delcarations.
> * Halves the number of symbols added for each static clock initialization.
> 
> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>

I agree this is a reasonable move.  But while you simplify the interface
of clk_register(), why not making a further step to simplify the
following interfaces simple too?

struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
                const char *parent_name, unsigned long flags,
                unsigned long fixed_rate);
struct clk *clk_register_gate(struct device *dev, const char *name,
                const char *parent_name, unsigned long flags,
                void __iomem *reg, u8 bit_idx,
                u8 clk_gate_flags, spinlock_t *lock);
struct clk *clk_register_divider(struct device *dev, const char *name,
                const char *parent_name, unsigned long flags,
                void __iomem *reg, u8 shift, u8 width,
                u8 clk_divider_flags, spinlock_t *lock);
struct clk *clk_register_mux(struct device *dev, const char *name,
                char **parent_names, u8 num_parents, unsigned long flags,
                void __iomem *reg, u8 shift, u8 width,
                u8 clk_mux_flags, spinlock_t *lock);

Otherwise,

Acked-by: Shawn Guo <shawn.guo at linaro.org>

-- 
Regards,
Shawn


From s.hauer at pengutronix.de  Tue Mar 20 03:19:57 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 20 Mar 2012 08:19:57 +0100
Subject: [PATCH 1/2] clk: Fix error handling in fixed clock hardware type
 register fn
In-Reply-To: <1332214706-675-1-git-send-email-skannan@codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
Message-ID: <20120320071957.GH3852@pengutronix.de>

On Mon, Mar 19, 2012 at 08:38:25PM -0700, Saravana Kannan wrote:
> If memory allocation for the parents array or the parent string fails, then
> fail the registration immediately instead of calling clk_register and
> hoping it fails there.
> 
> Return -ENOMEM on failure.
> 
> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
> Cc: Mike Turquette <mturquette at linaro.org>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
> Cc: Thomas Gleixner <tglx at linutronix.de>
> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Shawn Guo <shawn.guo at freescale.com>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Cc: Jamie Iles <jamie at jamieiles.com>
> Cc: Richard Zhao <richard.zhao at linaro.org>
> Cc: Saravana Kannan <skannan at codeaurora.org>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Stephen Boyd <sboyd at codeaurora.org>
> Cc: Amit Kucheria <amit.kucheria at linaro.org>
> Cc: Deepak Saxena <dsaxena at linaro.org>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> ---
> There are still some memory free issues when clk_register() fails, but I will
> fix it when I fixed the other register() fns to return ENOMEM of alloc
> failure instead of a NULL.
> 
>  drivers/clk/clk-fixed-rate.c |   10 +++++++---
>  1 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
> index 90c79fb..6423ae9 100644
> --- a/drivers/clk/clk-fixed-rate.c
> +++ b/drivers/clk/clk-fixed-rate.c
> @@ -61,22 +61,26 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
>  		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
>  
>  		if (! parent_names)
> -			goto out;
> +			goto fail_ptr;
>  
>  		len = sizeof(char) * strlen(parent_name);
>  
>  		parent_names[0] = kmalloc(len, GFP_KERNEL);
>  
>  		if (!parent_names[0])
> -			goto out;
> +			goto fail_str;
>  
>  		strncpy(parent_names[0], parent_name, len);
>  	}

It's easier to add a char *parent to struct clk_fixed and pass it to
clk_register with &fixed->parent. This saves you a kmalloc call and
makes the error path simpler. It's the same way already done in the
divider.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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From m.szyprowski at samsung.com  Tue Mar 20 03:24:43 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 20 Mar 2012 08:24:43 +0100
Subject: [GIT PULL] DMA-mapping framework updates for 3.4
Message-ID: <1332228283-29077-1-git-send-email-m.szyprowski@samsung.com>

Hi Linus,

Please pull the dma-mapping framework updates for v3.4 since commit
c16fa4f2ad19908a47c63d8fa436a1178438c7e7:

  Linux 3.3

with the top-most commit e749a9f707f1102735e02338fa564be86be3bb69

  common: DMA-mapping: add NON-CONSISTENT attribute

from the git repository at:

  git://git.infradead.org/users/kmpark/linux-samsung dma-mapping-next

Those patches introduce a new alloc method (with support for memory
attributes) in dma_map_ops structure, which will later replace
dma_alloc_coherent and dma_alloc_writecombine functions.

Thanks!

Best regards
Marek Szyprowski
Samsung Poland R&D Center

Patch summary:

Andrzej Pietrasiewicz (9):
      X86: adapt for dma_map_ops changes
      MIPS: adapt for dma_map_ops changes
      PowerPC: adapt for dma_map_ops changes
      IA64: adapt for dma_map_ops changes
      SPARC: adapt for dma_map_ops changes
      Alpha: adapt for dma_map_ops changes
      SH: adapt for dma_map_ops changes
      Microblaze: adapt for dma_map_ops changes
      Unicore32: adapt for dma_map_ops changes

Marek Szyprowski (6):
      common: dma-mapping: introduce alloc_attrs and free_attrs methods
      Hexagon: adapt for dma_map_ops changes
      common: dma-mapping: remove old alloc_coherent and free_coherent methods
      common: dma-mapping: introduce mmap method
      common: DMA-mapping: add WRITE_COMBINE attribute
      common: DMA-mapping: add NON-CONSISTENT attribute

 Documentation/DMA-attributes.txt          |   19 +++++++++++++++++++
 arch/alpha/include/asm/dma-mapping.h      |   18 ++++++++++++------
 arch/alpha/kernel/pci-noop.c              |   10 ++++++----
 arch/alpha/kernel/pci_iommu.c             |   10 ++++++----
 arch/hexagon/include/asm/dma-mapping.h    |   18 ++++++++++++------
 arch/hexagon/kernel/dma.c                 |    9 +++++----
 arch/ia64/hp/common/sba_iommu.c           |   11 ++++++-----
 arch/ia64/include/asm/dma-mapping.h       |   18 ++++++++++++------
 arch/ia64/kernel/pci-swiotlb.c            |    9 +++++----
 arch/ia64/sn/pci/pci_dma.c                |    9 +++++----
 arch/microblaze/include/asm/dma-mapping.h |   18 ++++++++++++------
 arch/microblaze/kernel/dma.c              |   10 ++++++----
 arch/mips/cavium-octeon/dma-octeon.c      |   16 ++++++++--------
 arch/mips/include/asm/dma-mapping.h       |   18 ++++++++++++------
 arch/mips/mm/dma-default.c                |    8 ++++----
 arch/powerpc/include/asm/dma-mapping.h    |   24 ++++++++++++++++--------
 arch/powerpc/kernel/dma-iommu.c           |   10 ++++++----
 arch/powerpc/kernel/dma-swiotlb.c         |    4 ++--
 arch/powerpc/kernel/dma.c                 |   10 ++++++----
 arch/powerpc/kernel/ibmebus.c             |   10 ++++++----
 arch/powerpc/kernel/vio.c                 |   14 ++++++++------
 arch/powerpc/platforms/cell/iommu.c       |   16 +++++++++-------
 arch/powerpc/platforms/ps3/system-bus.c   |   13 +++++++------
 arch/sh/include/asm/dma-mapping.h         |   28 ++++++++++++++++++----------
 arch/sh/kernel/dma-nommu.c                |    4 ++--
 arch/sh/mm/consistent.c                   |    6 ++++--
 arch/sparc/include/asm/dma-mapping.h      |   18 ++++++++++++------
 arch/sparc/kernel/iommu.c                 |   10 ++++++----
 arch/sparc/kernel/ioport.c                |   18 ++++++++++--------
 arch/sparc/kernel/pci_sun4v.c             |    9 +++++----
 arch/unicore32/include/asm/dma-mapping.h  |   18 ++++++++++++------
 arch/unicore32/mm/dma-swiotlb.c           |    4 ++--
 arch/x86/include/asm/dma-mapping.h        |   26 ++++++++++++++++----------
 arch/x86/kernel/amd_gart_64.c             |   11 ++++++-----
 arch/x86/kernel/pci-calgary_64.c          |    9 +++++----
 arch/x86/kernel/pci-dma.c                 |    3 ++-
 arch/x86/kernel/pci-nommu.c               |    6 +++---
 arch/x86/kernel/pci-swiotlb.c             |   12 +++++++-----
 arch/x86/xen/pci-swiotlb-xen.c            |    4 ++--
 drivers/iommu/amd_iommu.c                 |   10 ++++++----
 drivers/iommu/intel-iommu.c               |    9 +++++----
 drivers/xen/swiotlb-xen.c                 |    5 +++--
 include/linux/dma-attrs.h                 |    2 ++
 include/linux/dma-mapping.h               |   13 +++++++++----
 include/linux/swiotlb.h                   |    6 ++++--
 include/xen/swiotlb-xen.h                 |    6 ++++--
 lib/swiotlb.c                             |    5 +++--
 47 files changed, 338 insertions(+), 206 deletions(-)




From tomi.valkeinen at ti.com  Tue Mar 20 03:30:51 2012
From: tomi.valkeinen at ti.com (Tomi Valkeinen)
Date: Tue, 20 Mar 2012 09:30:51 +0200
Subject: [PATCH v2 7/7] ARM: OMAP2+: Mark omap_hsmmc_init and omap_mux
 related functions as __init
In-Reply-To: <20120319180928.GA9859@atomide.com>
References: <1329997247-27342-1-git-send-email-rnayak@ti.com>
 <1329997247-27342-8-git-send-email-rnayak@ti.com>
 <1332148116.2144.1.camel@deskari> <1332152442.2144.27.camel@deskari>
 <20120319180928.GA9859@atomide.com>
Message-ID: <1332228651.2409.5.camel@lappy>

On Mon, 2012-03-19 at 11:09 -0700, Tony Lindgren wrote:

> I've updated your patch a bit for the comments a bit and marked
> omap4_hdmi_mux_pads as __init, will apply to fixes. Updated patch
> below.

Hmm, is there something funny with these init changes now...

Initially the situation was that there were no __inits in display.c's
mux functions. Then "Mark omap_hsmmc_init..." patch added __inits to all
of them. My patch removed the __inits from dsi functions, but left them
to hdmi functions.

But now you modified my patch to add the __inits to hdmi functions.
Which should already have them from the "Mark omap_hsmmc_init..." patch.

 Tomi
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From skannan at codeaurora.org  Tue Mar 20 03:46:04 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 20 Mar 2012 00:46:04 -0700 (PDT)
Subject: [PATCH 1/2] clk: Fix error handling in fixed clock hardware 
 type register fn
In-Reply-To: <20120320071957.GH3852@pengutronix.de>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <20120320071957.GH3852@pengutronix.de>
Message-ID: <348585ed29fb3ff171267c03658e6c0d.squirrel@www.codeaurora.org>


On Tue, March 20, 2012 12:19 am, Sascha Hauer wrote:
> On Mon, Mar 19, 2012 at 08:38:25PM -0700, Saravana Kannan wrote:
>> If memory allocation for the parents array or the parent string fails,
>> then
>> fail the registration immediately instead of calling clk_register and
>> hoping it fails there.
>>
>> Return -ENOMEM on failure.
>>
>> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
>> Cc: Mike Turquette <mturquette at linaro.org>
>> Cc: Andrew Lunn <andrew at lunn.ch>
>> Cc: Rob Herring <rob.herring at calxeda.com>
>> Cc: Russell King <linux at arm.linux.org.uk>
>> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
>> Cc: Thomas Gleixner <tglx at linutronix.de>
>> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
>> Cc: Paul Walmsley <paul at pwsan.com>
>> Cc: Shawn Guo <shawn.guo at freescale.com>
>> Cc: Sascha Hauer <s.hauer at pengutronix.de>
>> Cc: Jamie Iles <jamie at jamieiles.com>
>> Cc: Richard Zhao <richard.zhao at linaro.org>
>> Cc: Saravana Kannan <skannan at codeaurora.org>
>> Cc: Magnus Damm <magnus.damm at gmail.com>
>> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
>> Cc: Linus Walleij <linus.walleij at stericsson.com>
>> Cc: Stephen Boyd <sboyd at codeaurora.org>
>> Cc: Amit Kucheria <amit.kucheria at linaro.org>
>> Cc: Deepak Saxena <dsaxena at linaro.org>
>> Cc: Grant Likely <grant.likely at secretlab.ca>
>> ---
>> There are still some memory free issues when clk_register() fails, but I
>> will
>> fix it when I fixed the other register() fns to return ENOMEM of alloc
>> failure instead of a NULL.
>>
>>  drivers/clk/clk-fixed-rate.c |   10 +++++++---
>>  1 files changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
>> index 90c79fb..6423ae9 100644
>> --- a/drivers/clk/clk-fixed-rate.c
>> +++ b/drivers/clk/clk-fixed-rate.c
>> @@ -61,22 +61,26 @@ struct clk *clk_register_fixed_rate(struct device
>> *dev, const char *name,
>>  		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
>>
>>  		if (! parent_names)
>> -			goto out;
>> +			goto fail_ptr;
>>
>>  		len = sizeof(char) * strlen(parent_name);
>>
>>  		parent_names[0] = kmalloc(len, GFP_KERNEL);
>>
>>  		if (!parent_names[0])
>> -			goto out;
>> +			goto fail_str;
>>
>>  		strncpy(parent_names[0], parent_name, len);
>>  	}
>
> It's easier to add a char *parent to struct clk_fixed and pass it to
> clk_register with &fixed->parent. This saves you a kmalloc call and
> makes the error path simpler. It's the same way already done in the
> divider.

I thought about that since I saw the same was done for gated and divider
(I think). Here is my guess at Mike's reasoning for this:

Gated and divider clocks have to have a parent. There's nothing to gate
otherwise. But fixed rate clocks might not have a parent. It could be XO's
or PLLs running off of always on XOs not controlled by the SoC. So, it's
arguable to not have a parent. I don't have a strong opinion on this --
since Mike took the time to write it, it left it to his subjective
preference.

I sent this patch first since it was around the place I was cleaning up. I
didn't want to actually just shuffle around a bug. As I mentioned, this
patch still leaves a bug open -- what if clk_register() fails. I plan to
fix that once my two patches are picked up (hopefully).

Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.




From w.sang at pengutronix.de  Tue Mar 20 03:50:59 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 20 Mar 2012 08:50:59 +0100
Subject: [PATCH 1/1] net: phylib: remove the length limitation of mii
 bus id
In-Reply-To: <1332217679-3703-1-git-send-email-b29396@freescale.com>
References: <1332217679-3703-1-git-send-email-b29396@freescale.com>
Message-ID: <20120320075059.GA3849@pengutronix.de>

Hi Aisheng,

> So changed to remove the bus id length limitation, a lot of handwork.

You might want to try 'coccinelle' [1] next time. This is a tool exactly for
such kind of work. Already some basic knowledge can help you for a
number of tasks.

Regards,

   Wolfram

[1] http://en.wikipedia.org/wiki/Coccinelle_%28software%29

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From skannan at codeaurora.org  Tue Mar 20 03:54:55 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 20 Mar 2012 00:54:55 -0700 (PDT)
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <20120320072018.GC32469@S2101-09.ap.freescale.net>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
Message-ID: <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>


On Tue, March 20, 2012 12:20 am, Shawn Guo wrote:
> On Mon, Mar 19, 2012 at 08:38:26PM -0700, Saravana Kannan wrote:
>> This has a couple of advantages:
>> * Completely hides struct clk from many clock platform drivers and
>> static
>>   clock initialization code.
>> * Simplifies the generic clk_register() function and allows adding
>> optional
>>   fields in the future without modifying the function signature.
>> * Allows for simpler static initialization of clocks on all platforms by
>>   removing the need for forward delcarations.
>> * Halves the number of symbols added for each static clock
>> initialization.
>>
>> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
>
> I agree this is a reasonable move.  But while you simplify the interface
> of clk_register(), why not making a further step to simplify the
> following interfaces simple too?
>
> struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
>                 const char *parent_name, unsigned long flags,
>                 unsigned long fixed_rate);
> struct clk *clk_register_gate(struct device *dev, const char *name,
>                 const char *parent_name, unsigned long flags,
>                 void __iomem *reg, u8 bit_idx,
>                 u8 clk_gate_flags, spinlock_t *lock);
> struct clk *clk_register_divider(struct device *dev, const char *name,
>                 const char *parent_name, unsigned long flags,
>                 void __iomem *reg, u8 shift, u8 width,
>                 u8 clk_divider_flags, spinlock_t *lock);
> struct clk *clk_register_mux(struct device *dev, const char *name,
>                 char **parent_names, u8 num_parents, unsigned long flags,
>                 void __iomem *reg, u8 shift, u8 width,
>                 u8 clk_mux_flags, spinlock_t *lock);

If you simplify those functions further. They would just become
clk_register(). I'm not sure I see a value in them in at that point or
even in their current form. But if others see (I'm guessing since they
acked or didn't nack it), I'm not going to ask to remove them. If everyone
agrees that we should just remove them, I would be glad to.

It's arguable that these functions for the common hardware types saves the
need to deal with the kalloc in every platform driver. But it's not clear
to me where they would get these parameters in the first place. Most
likely form some sort of static array. At which point, it might as well be
a static array of pointers to clk_gated.hw, clk_fixed_rate.hw, etc instead
of a platform specific  struct to hold these initializers.

Btw, I need to fix the macros too. Or may be even delete them. Will see
the overall response before I send out v2 to do that.

>
> Otherwise,
>
> Acked-by: Shawn Guo <shawn.guo at linaro.org>
Thanks

-Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.




From prylowski at metasoft.pl  Tue Mar 20 04:09:26 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Tue, 20 Mar 2012 09:09:26 +0100
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
Message-ID: <4F683B36.8090101@metasoft.pl>

Implement double buffering for M2M DMA channels.

Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>

Index: slave-dma/drivers/dma/ep93xx_dma.c
===================================================================
--- slave-dma.orig/drivers/dma/ep93xx_dma.c
+++ slave-dma/drivers/dma/ep93xx_dma.c
@@ -69,6 +69,7 @@
 #define M2M_CONTROL_TM_SHIFT		13
 #define M2M_CONTROL_TM_TX		(1 << M2M_CONTROL_TM_SHIFT)
 #define M2M_CONTROL_TM_RX		(2 << M2M_CONTROL_TM_SHIFT)
+#define M2M_CONTROL_NFBINT		BIT(21)
 #define M2M_CONTROL_RSS_SHIFT		22
 #define M2M_CONTROL_RSS_SSPRX		(1 << M2M_CONTROL_RSS_SHIFT)
 #define M2M_CONTROL_RSS_SSPTX		(2 << M2M_CONTROL_RSS_SHIFT)
@@ -77,7 +78,23 @@
 #define M2M_CONTROL_PWSC_SHIFT		25
 
 #define M2M_INTERRUPT			0x0004
-#define M2M_INTERRUPT_DONEINT		BIT(1)
+#define M2M_INTERRUPT_MASK		6
+
+#define M2M_STATUS			0x000c
+#define M2M_STATUS_CTL_SHIFT		1
+#define M2M_STATUS_CTL_IDLE		(0 << M2M_STATUS_CTL_SHIFT)
+#define M2M_STATUS_CTL_STALL		(1 << M2M_STATUS_CTL_SHIFT)
+#define M2M_STATUS_CTL_MEMRD		(2 << M2M_STATUS_CTL_SHIFT)
+#define M2M_STATUS_CTL_MEMWR		(3 << M2M_STATUS_CTL_SHIFT)
+#define M2M_STATUS_CTL_BWCWAIT		(4 << M2M_STATUS_CTL_SHIFT)
+#define M2M_STATUS_CTL_MASK		(7 << M2M_STATUS_CTL_SHIFT)
+#define M2M_STATUS_BUF_SHIFT		4
+#define M2M_STATUS_BUF_NO		(0 << M2M_STATUS_BUF_SHIFT)
+#define M2M_STATUS_BUF_ON		(1 << M2M_STATUS_BUF_SHIFT)
+#define M2M_STATUS_BUF_NEXT		(2 << M2M_STATUS_BUF_SHIFT)
+#define M2M_STATUS_BUF_MASK		(3 << M2M_STATUS_BUF_SHIFT)
+#define M2M_STATUS_DONE			BIT(6)
+
 
 #define M2M_BCR0			0x0010
 #define M2M_BCR1			0x0014
@@ -426,15 +443,6 @@ static int m2p_hw_interrupt(struct ep93x
 
 /*
  * M2M DMA implementation
- *
- * For the M2M transfers we don't use NFB at all. This is because it simply
- * doesn't work well with memcpy transfers. When you submit both buffers it is
- * extremely unlikely that you get an NFB interrupt, but it instead reports
- * DONE interrupt and both buffers are already transferred which means that we
- * weren't able to update the next buffer.
- *
- * So for now we "simulate" NFB by just submitting buffer after buffer
- * without double buffering.
  */
 
 static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
@@ -543,6 +551,11 @@ static void m2m_hw_submit(struct ep93xx_
 	m2m_fill_desc(edmac);
 	control |= M2M_CONTROL_DONEINT;
 
+	if (ep93xx_dma_advance_active(edmac)) {
+		m2m_fill_desc(edmac);
+		control |= M2M_CONTROL_NFBINT;
+	}
+
 	/*
 	 * Now we can finally enable the channel. For M2M channel this must be
 	 * done _after_ the BCRx registers are programmed.
@@ -560,32 +573,85 @@ static void m2m_hw_submit(struct ep93xx_
 	}
 }
 
+/*
+ * According to EP93xx User's Guide, we should receive DONE interrupt when all
+ * M2M DMA controller transactions complete normally. This is not always the
+ * case - sometimes EP93xx M2M DMA asserts DONE interrupt when the DMA channel
+ * is still running (channel Buffer FSM in DMA_BUF_ON state, and channel
+ * Control FSM in DMA_MEM_RD state, observed at least in IDE-DMA operation).
+ * In effect, disabling the channel when only DONE bit is set could stop
+ * currently running DMA transfer. To avoid this, we use Buffer FSM and
+ * Control FSM to check current state of DMA channel.
+ */
 static int m2m_hw_interrupt(struct ep93xx_dma_chan *edmac)
 {
+	u32 status = readl(edmac->regs + M2M_STATUS);
+	u32 ctl_fsm = status & M2M_STATUS_CTL_MASK;
+	u32 buf_fsm = status & M2M_STATUS_BUF_MASK;
+	bool done = status & M2M_STATUS_DONE;
+	bool last;
 	u32 control;
 
-	if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_DONEINT))
+	/* Accept only DONE and NFB interrupts */
+	if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_MASK))
 		return INTERRUPT_UNKNOWN;
 
-	/* Clear the DONE bit */
-	writel(0, edmac->regs + M2M_INTERRUPT);
+	if (done)
+		/* Clear the DONE bit */
+		writel(0, edmac->regs + M2M_INTERRUPT);
 
-	/* Disable interrupts and the channel */
-	control = readl(edmac->regs + M2M_CONTROL);
-	control &= ~(M2M_CONTROL_DONEINT | M2M_CONTROL_ENABLE);
-	writel(control, edmac->regs + M2M_CONTROL);
+	/*
+	 * Check whether we are done with descriptors or not. This, together
+	 * with DMA channel state, determines action to take in interrupt.
+	 */
+	last = list_first_entry(edmac->active.next,
+		struct ep93xx_dma_desc, node)->txd.cookie;
 
 	/*
-	 * Since we only get DONE interrupt we have to find out ourselves
-	 * whether there still is something to process. So we try to advance
-	 * the chain an see whether it succeeds.
+	 * Use M2M DMA Buffer FSM and Control FSM to check current state of
+	 * DMA channel. Using DONE and NFB bits from channel status register
+	 * or bits from channel interrupt register was proven not to be
+	 * reliable.
 	 */
-	if (ep93xx_dma_advance_active(edmac)) {
-		edmac->edma->hw_submit(edmac);
+	if (!last &&
+	    (buf_fsm == M2M_STATUS_BUF_NO ||
+	     buf_fsm == M2M_STATUS_BUF_ON)) {
+		/*
+		 * Two buffers are ready for update when Buffer FSM is in
+		 * DMA_NO_BUF state. Only one buffer can be prepared without
+		 * disabling the channel, or polling the DONE bit.
+		 * To simplify things, always prepare only one buffer.
+		 */
+		ep93xx_dma_advance_active(edmac);
+		m2m_fill_desc(edmac);
+		if (done && !edmac->chan.private) {
+			/* Software trigger for memcpy channel */
+			control = readl(edmac->regs + M2M_CONTROL);
+			control |= M2M_CONTROL_START;
+			writel(control, edmac->regs + M2M_CONTROL);
+		}
 		return INTERRUPT_NEXT_BUFFER;
 	}
 
-	return INTERRUPT_DONE;
+	/*
+	 * Disable the channel only when Buffer FSM is in DMA_NO_BUF state
+	 * and Control FSM is in DMA_STALL state.
+	 */
+	if (last &&
+	    buf_fsm == M2M_STATUS_BUF_NO &&
+	    ctl_fsm == M2M_STATUS_CTL_STALL) {
+		/* Disable interrupts and the channel */
+		control = readl(edmac->regs + M2M_CONTROL);
+		control &= ~(M2M_CONTROL_DONEINT | M2M_CONTROL_NFBINT
+			    | M2M_CONTROL_ENABLE);
+		writel(control, edmac->regs + M2M_CONTROL);
+		return INTERRUPT_DONE;
+	}
+
+	/*
+	 * Nothing to do this time.
+	 */
+	return INTERRUPT_NEXT_BUFFER;
 }
 
 /*


From shawn.guo at linaro.org  Tue Mar 20 04:13:33 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 20 Mar 2012 16:13:33 +0800
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
Message-ID: <20120320081331.GD32469@S2101-09.ap.freescale.net>

On Tue, Mar 20, 2012 at 12:54:55AM -0700, Saravana Kannan wrote:
> 
> On Tue, March 20, 2012 12:20 am, Shawn Guo wrote:
...
> > struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> >                 const char *parent_name, unsigned long flags,
> >                 unsigned long fixed_rate);
> > struct clk *clk_register_gate(struct device *dev, const char *name,
> >                 const char *parent_name, unsigned long flags,
> >                 void __iomem *reg, u8 bit_idx,
> >                 u8 clk_gate_flags, spinlock_t *lock);
> > struct clk *clk_register_divider(struct device *dev, const char *name,
> >                 const char *parent_name, unsigned long flags,
> >                 void __iomem *reg, u8 shift, u8 width,
> >                 u8 clk_divider_flags, spinlock_t *lock);
> > struct clk *clk_register_mux(struct device *dev, const char *name,
> >                 char **parent_names, u8 num_parents, unsigned long flags,
> >                 void __iomem *reg, u8 shift, u8 width,
> >                 u8 clk_mux_flags, spinlock_t *lock);
> 
> If you simplify those functions further. They would just become
> clk_register(). I'm not sure I see a value in them in at that point or
> even in their current form. But if others see (I'm guessing since they
> acked or didn't nack it), I'm not going to ask to remove them. If everyone
> agrees that we should just remove them, I would be glad to.
> 
> It's arguable that these functions for the common hardware types saves the
> need to deal with the kalloc in every platform driver. But it's not clear
> to me where they would get these parameters in the first place. Most
> likely form some sort of static array. At which point, it might as well be
> a static array of pointers to clk_gated.hw, clk_fixed_rate.hw, etc instead
> of a platform specific  struct to hold these initializers.

I share the save view on this, so would vote to remove these
registration functions for basic clks completely.

Regards,
Shawn


From B29396 at freescale.com  Tue Mar 20 04:13:47 2012
From: B29396 at freescale.com (Dong Aisheng-B29396)
Date: Tue, 20 Mar 2012 08:13:47 +0000
Subject: [PATCH 1/1] net: phylib: remove the length limitation of mii
 bus id
In-Reply-To: <20120320075059.GA3849@pengutronix.de>
References: <1332217679-3703-1-git-send-email-b29396@freescale.com>
 <20120320075059.GA3849@pengutronix.de>
Message-ID: <7FE21149F4667147B645348EC6057885146C9E@039-SN2MPN1-011.039d.mgd.msft.net>

Hi Wolfram,

> > So changed to remove the bus id length limitation, a lot of handwork.
> 
> You might want to try 'coccinelle' [1] next time. This is a tool exactly for
> such kind of work. Already some basic knowledge can help you for a number of
> tasks.
>
Good tool.
Thanks for the info. :-)
 
> Regards,
> 
>    Wolfram
> 
> [1] http://en.wikipedia.org/wiki/Coccinelle_%28software%29
>

Regards
Dong Aisheng



From arnd at arndb.de  Tue Mar 20 04:20:08 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 20 Mar 2012 08:20:08 +0000
Subject: [PATCH] ARM: OMAP2+: gpmc-smsc911x: only register regulator for
 first instance
In-Reply-To: <20120319224858.GD9859@atomide.com>
References: <1331080771-30687-1-git-send-email-khilman@ti.com>
 <201203192209.43906.arnd@arndb.de> <20120319224858.GD9859@atomide.com>
Message-ID: <201203200820.08471.arnd@arndb.de>

On Monday 19 March 2012, Tony Lindgren wrote:
> Let's just keep bb60424af. There are more patches needed to make
> multiple smsc91x instances work, but we need to hear from people
> with such boards first. Then those can be tagged for stable.
> 

Ok, I'm just putting that into the fixes branch for 3.4 then.

Thanks,

	Arnd


From shawn.guo at linaro.org  Tue Mar 20 04:32:12 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 20 Mar 2012 16:32:12 +0800
Subject: [PATCH 1/1] net: phylib: remove the length limitation of mii bus
 id
In-Reply-To: <1332217386-3586-1-git-send-email-b29396@freescale.com>
References: <1332217386-3586-1-git-send-email-b29396@freescale.com>
Message-ID: <CAAQ0ZWQEoPORMXsf3xV-KPP+hOHk2euj460fORyUALnfPn3Q8g@mail.gmail.com>

On 20 March 2012 12:23, Dong Aisheng <b29396 at freescale.com> wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
>
> When convert to dt, the length of old mii bus id (17 bytes) is not
> sufficent to use.
> For example, the bus id could be 800f0000.ethernet-1:00 in DT.
>
> This patch removes the bus id length limitation by changing the
> bus id to a const char pionter and user could dynamically set the
> bus id via kasprintf function call.
>
> Since then no users use MII_BUS_ID_SIZE any more, just remove it.
>
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
> The simplest way may just change MII_BUS_ID_SIZE to a more bigger size,
> but i'm not sure that's gonna be accepted.

The simplest fix has been applied on -next tree as below.

commit a7ed07d51c8abdb407be454c6cb6cfad613759d9
Author: Richard Zhao <richard.zhao at linaro.org>
Date:   Sun Jan 29 22:08:12 2012 +0000

    net: fec: correct phy_name buffer length when init phy_name

    Fix the bug that we got wrong phy_name on imx6q sabrelite board.
    snprintf used wrong length of phy_name.
    phy_name length is MII_BUS_ID_SIZE + 3 rather not MII_BUS_ID_SIZE.
    I change it to sizeof(phy_name).

    Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
    Acked-by: Shawn Guo <shawn.guo at linaro.org>
    Acked-by: Florian Fainelli <florian at openwrt.org>
    Signed-off-by: David S. Miller <davem at davemloft.net>

diff --git a/drivers/net/ethernet/freescale/fec.c
b/drivers/net/ethernet/freescale/fec.c
index 7b25e9c..1c7aad8 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -990,7 +990,7 @@ static int fec_enet_mii_probe(struct net_device *ndev)
                phy_id = 0;
        }

-       snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
+       snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
        phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
                              fep->phy_interface);
        if (IS_ERR(phy_dev)) {


From thierry.reding at avionic-design.de  Tue Mar 20 04:39:44 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 20 Mar 2012 09:39:44 +0100
Subject: [PATCH v4 10/10] pwm-backlight: Add rudimentary device tree
 support
In-Reply-To: <4F67F2AF.3020404@wwwdotorg.org>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-11-git-send-email-thierry.reding@avionic-design.de>
 <4F67F2AF.3020404@wwwdotorg.org>
Message-ID: <20120320083943.GA20249@avionic-0098.adnet.avionic-design.de>

* Stephen Warren wrote:
> On 03/14/2012 09:56 AM, Thierry Reding wrote:
> > This commit adds very basic support for device tree probing. Currently,
> > only a PWM and a list of distinct brightness levels can be specified.
> > Enabling or disabling backlight power via GPIOs is not yet supported.
> > 
> > A pointer to the exit() callback is stored in the driver data to keep it
> > around until the driver is unloaded.
> 
> > +++ b/Documentation/devicetree/bindings/video/backlight/pwm-backlight
> 
> > +pwm-backlight bindings
> > +
> > +Required properties:
> > +  - compatible: "pwm-backlight"
> > +  - pwm: OF device-tree PWM specification
> > +  - num-brightness-levels: number of distinct brightness levels
> > +  - brightness-levels: array of distinct brightness levels
> 
> I assume the values in this array are 0 (darkest/off) to 255 (max
> brightness)? The doc should probably specify this.

Typically yes. Although I haven't tested this it should work for pretty much
any range starting from 0 because the last value will be used to interpolate
("scale") the PWM duty cycle. So it really is 0 (darkest/off) to <last item>
(max brightness). I should document this, of course.

> > +  - default-brightness-level: the default brightness level
> 
> Likewise, this is an index into the default-brightness-level? Again,
> it'd be best to explicitly state this.

Yes. Correct.

> ...
> > +		brightness-levels = <0 4 8 16 32 64 128 255>;
> > +		default-brightness-level = <6>;
> 
> 
> > +static int pwm_backlight_parse_dt(struct device *dev,
> > +				  struct platform_pwm_backlight_data *data)
> ...
> > +		ret = of_property_read_u32(node, "default-brightness-level",
> > +					   &value);
> > +		if (ret < 0)
> > +			goto free;
> 
> Range-check that against max_brightness?

Yes, that would be good. I guess logging a warning and falling back to
max_brightness would be the proper action?

> >  static int pwm_backlight_probe(struct platform_device *pdev)
> ...
> > -	pb->pwm = pwm_request(data->pwm_id, "backlight");
> > -	if (IS_ERR(pb->pwm)) {
> > -		dev_err(&pdev->dev, "unable to request PWM for backlight\n");
> > -		ret = PTR_ERR(pb->pwm);
> > -		goto err_alloc;
> > -	} else
> > -		dev_dbg(&pdev->dev, "got pwm for backlight\n");
> > +	if (!pb->pwm) {
> > +		pb->pwm = pwm_request(data->pwm_id, "backlight");
> > +		if (IS_ERR(pb->pwm)) {
> > +			dev_err(&pdev->dev, "unable to request PWM for backlight\n");
> > +			ret = PTR_ERR(pb->pwm);
> > +			goto err_alloc;
> > +		} else
> > +			dev_dbg(&pdev->dev, "got pwm for backlight\n");
> > +	}
> 
> Hmmm. It'd be more consistent if pwm_backlight_parse_dt() called
> something like of_pwm_get() instead of of_pwm_request(), so that this
> code could always call pwm_request() on the PWM and hence operate the
> same irrespective of DT vs non-DT. GPIOs work that way at least.

That's actually what the initial patch had. Unfortunately that's pretty much
the opposite direction of where the PWM framework is headed because it would
involve getting a global index to request the PWM. I think in the long run it
would be much better to get rid of pwm_request() altogether and unify by
having the non-DT case request the PWM device on a per-chip basis.

Thierry
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From thierry.reding at avionic-design.de  Tue Mar 20 04:44:03 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 20 Mar 2012 09:44:03 +0100
Subject: [PATCH v4 05/10] ARM: tegra: Provide clock for only one PWM
 controller
In-Reply-To: <4F67E8E4.7000604@wwwdotorg.org>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-6-git-send-email-thierry.reding@avionic-design.de>
 <4F67E8E4.7000604@wwwdotorg.org>
Message-ID: <20120320084403.GB20249@avionic-0098.adnet.avionic-design.de>

* Stephen Warren wrote:
> On 03/14/2012 09:56 AM, Thierry Reding wrote:
> > A subsequent patch will add a generic PWM API driver for the Tegra PWFM
> > controller, supporting all four PWM devices with a single PWM chip. The
> > device will be named tegra-pwm and only one clock needs to be provided.
> > 
> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> > Acked-by: Stephen Warren <swarren at nvidia.com>
> ...
> > -	CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
> > -	CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
> > -	CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
> > -	CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
> > +	CLK_DUPLICATE("pwm", "tegra-pwm", NULL),
> 
> I thought harder about this: Why not delete /all/ the CLK_DUPLICATE()s
> for PWM, and change the second parameter to PERIPH_CLK for PWM from
> "pwm" to "tegra-pwm"?

I think that should work. I'll retest and will update the patch accordingly.
I assume that you're Acked-by will remain valid after those changes?

Thierry
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From thierry.reding at avionic-design.de  Tue Mar 20 04:48:07 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 20 Mar 2012 09:48:07 +0100
Subject: [PATCH v4 07/10] pwm: tegra: Add device tree support
In-Reply-To: <4F67EE9A.6080101@wwwdotorg.org>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-8-git-send-email-thierry.reding@avionic-design.de>
 <4F67EE9A.6080101@wwwdotorg.org>
Message-ID: <20120320084807.GC20249@avionic-0098.adnet.avionic-design.de>

* Stephen Warren wrote:
> On 03/14/2012 09:56 AM, Thierry Reding wrote:
> > Add auxdata to instantiate the PWFM controller from a device tree,
> > include the corresponding nodes in the dtsi files for Tegra 20 and
> > Tegra 30 and add binding documentation.
> > 
> > Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> 
> > +++ b/Documentation/devicetree/bindings/pwm/tegra-pwm.txt
> 
> Can this please be named nvidia,tegra20-pwm.txt so that if we need
> different bindings for any future Tegra PWM, we won't have any filename
> conflicts?

That file already documents the bindings for Tegra 20 and Tegra 30, that's
why I chose the move generic name. Could this perhaps be documented within
the file instead? Or should I rather add a nvidia,tegra30-pwm.txt with a
reference to the nvidia,tegra20-pwm.txt?

Thierry
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From alexg at meprolight.com  Tue Mar 20 04:54:29 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Tue, 20 Mar 2012 10:54:29 +0200
Subject: [PATCH v1] i.MX35-PDK: Add Camera support
In-Reply-To: <20120319224550.GF3852@pengutronix.de>
References: <1331651129-30540-1-git-send-email-alexg@meprolight.com>
 <4F67AD31.8030500@redhat.com> <4F67B077.5050300@redhat.com>
 <20120319223729.GC3852@pengutronix.de>
 <CAOMZO5B=Qpng68xLmxGaHMqSmYzbkpObVcjHDQSXaXcz5s6gMQ@mail.gmail.com>,
 <20120319224550.GF3852@pengutronix.de>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD0B@MEP-EXCH.meprolight.com>


Hi all,

Good news...
After several number of changes, yesterday the camera started to work :-) 
I will prepare some patches and send them. 

On Mon, Mar 19, 2012 at 07:43:32PM -0300, Fabio Estevam wrote:
> Hi Sascha,
>
> On Mon, Mar 19, 2012 at 7:37 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>
> > It's scheduled there. I should have responded with an applied message.
>
> Please apply this one too: http://patchwork.ozlabs.org/patch/144942/
>

Regards,
Alex Gershgorin


--
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From b-cousson at ti.com  Tue Mar 20 05:00:10 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Tue, 20 Mar 2012 10:00:10 +0100
Subject: [PATCH v2 0/4] ARM: OMAP: boards: changes to support dynamic
 irq alloc
In-Reply-To: <20120319233910.GF9859@atomide.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
 <20120319191743.GB9859@atomide.com> <4F67B9F9.1030906@ti.com>
 <20120319233910.GF9859@atomide.com>
Message-ID: <4F68471A.4010502@ti.com>

On 3/20/2012 12:39 AM, Tony Lindgren wrote:
> * Cousson, Benoit<b-cousson at ti.com>  [120319 16:00]:
>> Hi Tony,
>>
>> On 3/19/2012 8:17 PM, Tony Lindgren wrote:
>>> * Tarun Kanti DebBarma<tarun.kanti at ti.com>   [120319 05:09]:
>>>> These two patches incorporate changes to OMAP1 and OMAP2 platforms
>>>> board files whereby older references to OMAP_GPIO_IRQ macro are
>>>> now replaced with gpio_to_irq(), thereby getting rid of static
>>>> irq references.
>>>>
>>>> Reference: git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git omap/dt
>>>> Commit: 9a0cee711448335ec43eae83272495e9334c0098
>>>
>>> Can you please tell the exact two commits causing this
>>> breakage?
>>
>> Well, this is the GPIO DT + SPARSE_IRQ series I have done. It
>> appears that the boards I have were already using properly
>> gpio_to_irq() and thus were working fine with this series.
>>
>> But this is unfortunately not the case of most OMAP2 and 3 legacy
>> boards that were still using an old OMAP way of converting GPIO to
>> IRQ and were never modified to take advantage of the gpiolib stuff.
>>
>> So if these patches are apply before the GPIO DT + SPARSE_IRQ
>> series, there will be no breakage at all.
>>
>> All the cleanup we have never done before will hurt us at some point
>> when we will start using more extensively newer fmwk (DT,
>> sparse_irq, dmaengine...). It was not done on purpose, but this GPIO
>> series highlighted this remaining static broken mapping inside OMAP
>> boards.
>
> Yes I understand. But still, which patch(s) cause the issue
> so we can put that in the changelog for the fixes?

OK, here they are:
25db711 gpio/omap: Fix IRQ handling for SPARSE_IRQ
384ebe1 gpio/omap: Add DT support to GPIO driver

Tarun,

You should indeed add the references in your cover letter.

>>> I'm baffled how despite all the effort for previnting
>>> issues like this this still happen. These all seem valid
>>> fixes and clean up things, but how come this was not seen
>>> earlier?
>>
>> Maybe because there are much more boards inside mach-omap2 directory
>> than inside my cubicle... :-(
>
> Well somehow we need to make sure that patches get properly
> tested on a reasonable selection of boards. This pretty much
> breaks things for 21 boards out of the 51 board-*.c files :(

What is too bad is that one broken board was enough to figured out the 
issue and fix all the other ones. I just did not have that one :-(

Regards,
Benoit


From paul at pwsan.com  Tue Mar 20 05:17:16 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 20 Mar 2012 03:17:16 -0600 (MDT)
Subject: [PATCH v3 1/2] arm: omap3: pm34xx.c: Fix omap3_pm_init() error
 out paths
In-Reply-To: <1332150525.2116.334.camel@sokoban>
References: <1332033768-21986-1-git-send-email-mgreer@animalcreek.com>
 <1332033768-21986-2-git-send-email-mgreer@animalcreek.com>
 <1332150525.2116.334.camel@sokoban>
Message-ID: <alpine.DEB.2.00.1203200316300.22974@utopia.booyaka.com>

+ Kevin

On Mon, 19 Mar 2012, Tero Kristo wrote:

> On Sat, 2012-03-17 at 18:22 -0700, Mark A. Greer wrote:
> > From: "Mark A. Greer" <mgreer at animalcreek.com>
> > 
> > It appears that the error paths were overlooked when the
> > omap3_pm_init() routine had the prcm chain handler code
> > added.  Fix this by adding a goto target and reordering
> > the error handling code.  Also fix how the irq argument
> > for free_irq() is determined.
> 
> You are right, it looks like the error handling part was accidentally
> dropped from version 7 of the prcm patch set.
> 
> Acked-by: Tero Kristo <t-kristo at ti.com>
> 
> Paul, you going to grab this?

Kevin is the pm34xx.c maintainer, so unless he wants me to queue it, it's 
probably best for him to take it.


- Paul


From s.hauer at pengutronix.de  Tue Mar 20 05:40:31 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 20 Mar 2012 10:40:31 +0100
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
Message-ID: <20120320094031.GI3852@pengutronix.de>

On Tue, Mar 20, 2012 at 12:54:55AM -0700, Saravana Kannan wrote:
> 
> On Tue, March 20, 2012 12:20 am, Shawn Guo wrote:
> > On Mon, Mar 19, 2012 at 08:38:26PM -0700, Saravana Kannan wrote:
> >> This has a couple of advantages:
> >> * Completely hides struct clk from many clock platform drivers and
> >> static
> >>   clock initialization code.
> >> * Simplifies the generic clk_register() function and allows adding
> >> optional
> >>   fields in the future without modifying the function signature.
> >> * Allows for simpler static initialization of clocks on all platforms by
> >>   removing the need for forward delcarations.
> >> * Halves the number of symbols added for each static clock
> >> initialization.
> >>
> >> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
> >
> > I agree this is a reasonable move.  But while you simplify the interface
> > of clk_register(), why not making a further step to simplify the
> > following interfaces simple too?
> >
> > struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> >                 const char *parent_name, unsigned long flags,
> >                 unsigned long fixed_rate);
> > struct clk *clk_register_gate(struct device *dev, const char *name,
> >                 const char *parent_name, unsigned long flags,
> >                 void __iomem *reg, u8 bit_idx,
> >                 u8 clk_gate_flags, spinlock_t *lock);
> > struct clk *clk_register_divider(struct device *dev, const char *name,
> >                 const char *parent_name, unsigned long flags,
> >                 void __iomem *reg, u8 shift, u8 width,
> >                 u8 clk_divider_flags, spinlock_t *lock);
> > struct clk *clk_register_mux(struct device *dev, const char *name,
> >                 char **parent_names, u8 num_parents, unsigned long flags,
> >                 void __iomem *reg, u8 shift, u8 width,
> >                 u8 clk_mux_flags, spinlock_t *lock);
> 
> If you simplify those functions further. They would just become
> clk_register(). I'm not sure I see a value in them in at that point or
> even in their current form. But if others see (I'm guessing since they
> acked or didn't nack it), I'm not going to ask to remove them. If everyone
> agrees that we should just remove them, I would be glad to.
> 
> It's arguable that these functions for the common hardware types saves the
> need to deal with the kalloc in every platform driver. But it's not clear
> to me where they would get these parameters in the first place. Most
> likely form some sort of static array. At which point, it might as well be
> a static array of pointers to clk_gated.hw, clk_fixed_rate.hw, etc instead
> of a platform specific  struct to hold these initializers.

I am using these functions and don't need a static array, I just call
the functions with the desired parameters.

Overall the clock framework was written in a way that we have to expose
as little information about the internally used structs as necessary. It
seems your patches are pulling in the opposite direction now.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From u.kleine-koenig at pengutronix.de  Tue Mar 20 05:54:13 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Tue, 20 Mar 2012 10:54:13 +0100
Subject: [PATCH] ARM: davinci: implement DEBUG_LL port choice
In-Reply-To: <1331842703-4248-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1331842703-4248-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120320095413.GD15647@pengutronix.de>

Hello,

On Thu, Mar 15, 2012 at 09:18:23PM +0100, Uwe Kleine-K?nig wrote:
> Apart from the necessity to do this change for multi-platform kernels
> the previous logic depended on the zImage decompressor to write the
> physical and virtual address to a magic memory location.
> If the decompressor is unused or not correctly configured for the
> current machid, the addruart macro was an infinite loop. Moreover
> debugging the early zImage code was not possible either.
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
>  arch/arm/Kconfig.debug                           |   16 ++++++
>  arch/arm/mach-davinci/include/mach/debug-macro.S |   58 ++++++++--------------
>  arch/arm/mach-davinci/include/mach/hardware.h    |    2 +-
>  arch/arm/mach-davinci/include/mach/serial.h      |   10 ----
>  arch/arm/mach-davinci/include/mach/uncompress.h  |   25 +++-------
>  5 files changed, 44 insertions(+), 67 deletions(-)
> 
> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index e0d236d..57019be 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -108,6 +108,22 @@ choice
>  		bool "Kernel low-level debugging on 9263, 9g45 and cap9"
>  		depends on HAVE_AT91_DBGU1
>  
> +	config DEBUG_DAVINCI_UART0
> +		bool "Kernel low-level debugging on Davinci using uart0
> +		depends on ARCH_DAVINCI_DM644x
> +
> +	config DEBUG_DA8XX_UART1
> +		bool "Kernel low-level debugging on DA8xx using uart1"
> +		depends on ARCH_DAVINCI_DA8XX
> +
> +	config DEBUG_DA8XX_UART2
> +		bool "Kernel low-level debugging on DA8xx using uart2"
> +		depends on ARCH_DAVINCI_DA8XX
> +
> +	config DEBUG_TNETV107X_UART1
> +		bool "Kernel low-level debugging on TNETV107x using uart1
> +		depends on ARCH_DAVINCI_TNETV107X
> +
on the first and the last description line there are the closing "
missing. Should I resend?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From nicolas.ferre at atmel.com  Tue Mar 20 06:13:31 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 20 Mar 2012 11:13:31 +0100
Subject: [PATCH v2 1/2] of: Add generic device tree DMA helpers
In-Reply-To: <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
References: <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <6b5dc1fadfd03a48093338b6981c0a7ae7662212.1332237596.git.nicolas.ferre@atmel.com>

Add some basic helpers to retrieve a DMA controller device_node and the
DMA request specifications. By making DMA controllers register a generic
translation function, we allow the management of any type of DMA requests
specification.
The void * output of an of_dma_xlate() function that will be implemented
by the DMA controller can carry any type of "dma-request" argument.

The DMA client will search its associated DMA controller in the list and
call the registered of_dam_xlate() function to retrieve the request values.

One simple xlate function is provided for the "single number" type of
request binding.

This implementation is independent from dmaengine so it can also be used
by legacy drivers.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Signed-off-by: Benoit Cousson <b-cousson at ti.com>
Cc: Stephen Warren <swarren at nvidia.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Arnd Bergmann <arnd at arndb.de>
---
Hi all,

v2: - remove of_dma_to_resource API
    - make property #dma-cells required (no fallback anymore)
    - another check in of_dma_xlate_onenumbercell() function

This patch is just for the record as it seems that those helpers will not cover
every people expectations. So I let interested people build on top of this or
redo the whole stuff from the gound up.

Bye,

 Documentation/devicetree/bindings/dma/dma.txt |   45 +++++
 drivers/of/Makefile                           |    2 +-
 drivers/of/dma.c                              |  215 +++++++++++++++++++++++++
 include/linux/of_dma.h                        |   60 +++++++
 4 files changed, 321 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/dma/dma.txt
 create mode 100644 drivers/of/dma.c
 create mode 100644 include/linux/of_dma.h

diff --git a/Documentation/devicetree/bindings/dma/dma.txt b/Documentation/devicetree/bindings/dma/dma.txt
new file mode 100644
index 0000000..c49e98d
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/dma.txt
@@ -0,0 +1,45 @@
+* Generic DMA Controller and DMA request bindings
+
+Generic binding to provide a way for a driver to retrieve the
+DMA request line that goes from an IP to a DMA controller.
+
+
+* DMA controller
+
+Required property:
+    - #dma-cells: Number of cells for each DMA line.
+
+
+Example:
+
+	sdma: dma-controller at 48000000 {
+		compatible = "ti,sdma-omap4"
+		reg = <0x48000000 0x1000>;
+		interrupts = <12>;
+		#dma-cells = <1>;
+	};
+
+
+
+* DMA client
+
+Client drivers should specify the DMA request property using a phandle to
+the controller. If needed, the DMA request identity on that controller is then
+added followed by optional request specifications.
+
+Required property:
+    - dma-request: List of phandle + dma-request + request specifications,
+      one group per request "line".
+Optional property:
+    - dma-request-names: list of strings in the same order as the dma-request
+      in the dma-request property.
+
+
+Example:
+
+	i2c1: i2c at 1 {
+		...
+		dma-request = <&sdma 2 &sdma 3>;
+		dma-request-names = "tx", "rx";
+		...
+	};
diff --git a/drivers/of/Makefile b/drivers/of/Makefile
index a73f5a5..338c2ee 100644
--- a/drivers/of/Makefile
+++ b/drivers/of/Makefile
@@ -1,4 +1,4 @@
-obj-y = base.o
+obj-y = base.o dma.o
 obj-$(CONFIG_OF_FLATTREE) += fdt.o
 obj-$(CONFIG_OF_PROMTREE) += pdt.o
 obj-$(CONFIG_OF_ADDRESS)  += address.o
diff --git a/drivers/of/dma.c b/drivers/of/dma.c
new file mode 100644
index 0000000..e58a0dd
--- /dev/null
+++ b/drivers/of/dma.c
@@ -0,0 +1,215 @@
+/*
+ * Device tree helpers for DMA request / controller
+ *
+ * Based on of_gpio.c
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/rculist.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+
+static LIST_HEAD(of_dma_list);
+
+struct of_dma {
+	struct list_head of_dma_controllers;
+	struct device_node *of_node;
+	int of_dma_n_cells;
+	int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
+};
+
+/**
+ * of_dma_find_controller() - Find a DMA controller in DT DMA helpers list
+ * @np:		device node of DMA controller
+ */
+static struct of_dma *of_dma_find_controller(struct device_node *np)
+{
+	struct of_dma	*ofdma;
+
+	list_for_each_entry_rcu(ofdma, &of_dma_list, of_dma_controllers) {
+		if (ofdma->of_node == np)
+			return ofdma;
+	}
+
+	return NULL;
+}
+
+/**
+ * of_dma_controller_register() - Register a DMA controller to DT DMA helpers
+ * @np:			device node of DMA controller
+ * @of_dma_xlate:	generic translation function which converts a phandle
+ *			arguments list into a generic output value
+ *
+ * Returns 0 on success or appropriate errno value on error.
+ *
+ * Allocated memory should be freed with appropriate of_dma_controller_free()
+ * call.
+ */
+int of_dma_controller_register(struct device_node *np,
+			int (*of_dma_xlate)(struct of_phandle_args *, void *))
+{
+	struct of_dma	*ofdma;
+	const __be32	*nbcells;
+
+	if (!np || !of_dma_xlate) {
+		pr_err("%s: not enough information provided\n", __func__);
+		return -EINVAL;
+	}
+
+	ofdma = kzalloc(sizeof(*ofdma), GFP_KERNEL);
+	if (!ofdma)
+		return -ENOMEM;
+
+	nbcells = of_get_property(np, "#dma-cells", NULL);
+	if (!nbcells) {
+		pr_err("%s: #dma-cells property is required\n", __func__);
+		return -EINVAL;
+	} else {
+		ofdma->of_dma_n_cells = be32_to_cpup(nbcells);
+	}
+
+	ofdma->of_node = np;
+	ofdma->of_dma_xlate = of_dma_xlate;
+
+	/* Now queue of_dma controller structure in list */
+	list_add_tail_rcu(&ofdma->of_dma_controllers, &of_dma_list);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(of_dma_controller_register);
+
+/**
+ * of_dma_controller_free() - Remove a DMA controller from DT DMA helpers list
+ * @np:		device node of DMA controller
+ *
+ * Memory allocated by of_dma_controller_register() is freed here.
+ */
+void of_dma_controller_free(struct device_node *np)
+{
+	struct of_dma	*ofdma;
+
+	ofdma = of_dma_find_controller(np);
+	if (ofdma) {
+		list_del_rcu(&ofdma->of_dma_controllers);
+		kfree(ofdma);
+	}
+}
+EXPORT_SYMBOL_GPL(of_dma_controller_free);
+
+/**
+ * of_get_dma_request() - Get the associated DMA request data
+ * @np:		device node to get DMA request from
+ * @index:	index of the DMA request
+ * @out_data:	a output that can be filled in by the of_dma_xlate() function
+ *
+ * Returns return value of of_dma_xlate() and fills out_data (if provided).
+ * On error returns the appropriate errno value.
+ */
+int of_get_dma_request(struct device_node *np, int index,
+		       void *out_data)
+{
+	struct of_phandle_args	dma_spec;
+	struct of_dma		*ofdma;
+	int			ret;
+
+	ret = of_parse_phandle_with_args(np, "dma-request", "#dma-cells",
+					 index, &dma_spec);
+	if (ret) {
+		pr_err("%s: can't parse dma property\n", np->full_name);
+		goto err0;
+	}
+
+	if (list_empty(&of_dma_list)) {
+		pr_debug("%s: empty DMA controller list\n",
+			 np->full_name);
+		ret = -ENODEV;
+		goto err1;
+	}
+
+	ofdma = of_dma_find_controller(dma_spec.np);
+	if (!ofdma) {
+		pr_debug("%s: DMA controller %s isn't registered\n",
+			 np->full_name, dma_spec.np->full_name);
+		ret = -ENODEV;
+		goto err1;
+	}
+
+	if (dma_spec.args_count != ofdma->of_dma_n_cells) {
+		pr_debug("%s: wrong #dma-cells for %s\n",
+			 np->full_name, dma_spec.np->full_name);
+		ret = -EINVAL;
+		goto err1;
+	}
+
+	ret = ofdma->of_dma_xlate(&dma_spec, out_data);
+
+err1:
+	of_node_put(dma_spec.np);
+err0:
+	pr_debug("%s exited with status %d\n", __func__, ret);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(of_get_dma_request);
+
+/**
+ * of_dma_xlate_onenumbercell() - Generic DMA xlate for direct one cell bindings
+ *
+ * Device Tree DMA translation function which works with one cell bindings
+ * where the cell values map directly to the hardware request number understood
+ * by the DMA controller.
+ */
+int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec, void *dma_req)
+{
+	if (!dma_spec)
+		return -EINVAL;
+	if (!dma_req)
+		return -ENOBUFS;
+	if (WARN_ON(dma_spec->args_count != 1))
+		return -EINVAL;
+	*(int *)dma_req = dma_spec->args[0];
+	return 0;
+}
+EXPORT_SYMBOL_GPL(of_dma_xlate_onenumbercell);
+
+/**
+ * of_dma_count - Count DMA requests for a device
+ * @np:		device node to count DMAs for
+ *
+ * The function returns the count of DMA requests specified for a node.
+ *
+ * Note that the empty DMA specifiers counts too. For example,
+ *
+ * dma-request = <0
+ *                &sdma 1
+ *                0
+ *                &sdma 3>;
+ *
+ * defines four DMAs (so this function will return 4), two of which
+ * are not specified.
+ */
+unsigned int of_dma_count(struct device_node *np)
+{
+	unsigned int cnt = 0;
+
+	do {
+		int ret;
+
+		ret = of_parse_phandle_with_args(np, "dma-request",
+						 "#dma-cells", cnt, NULL);
+		/* A hole in the dma-request = <> counts anyway. */
+		if (ret < 0 && ret != -EEXIST)
+			break;
+	} while (++cnt);
+
+	return cnt;
+}
+EXPORT_SYMBOL_GPL(of_dma_count);
diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
new file mode 100644
index 0000000..2865480
--- /dev/null
+++ b/include/linux/of_dma.h
@@ -0,0 +1,60 @@
+/*
+ * OF helpers for DMA request / controller
+ *
+ * Based on of_gpio.h
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_OF_DMA_H
+#define __LINUX_OF_DMA_H
+
+#include <linux/ioport.h>
+#include <linux/of.h>
+
+struct device_node;
+
+#ifdef CONFIG_OF_DMA
+
+extern int of_dma_controller_register(struct device_node *np,
+			int (*of_dma_xlate)(struct of_phandle_args *, void *));
+extern void of_dma_controller_free(struct device_node *np);
+extern int of_get_dma_request(struct device_node *np, int index,
+			      void *out_data);
+extern unsigned int of_dma_count(struct device_node *np);
+
+extern int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
+				      void *dma_req);
+#else /* CONFIG_OF_DMA */
+
+static int of_dma_controller_register(struct device_node *np,
+			int (*of_dma_xlate)(struct of_phandle_args *, void *))
+{
+	return -ENOSYS;
+}
+
+static void of_dma_controller_free(struct device_node *np) {}
+
+extern int of_get_dma_request(struct device_node *np, int index,
+			      void *out_data)
+{
+	return -ENOSYS;
+}
+
+static inline unsigned int of_dma_count(struct device_node *np)
+{
+	return 0;
+}
+
+static int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
+				      void *dma_req)
+{
+	return -ENOSYS;
+}
+#endif /* CONFIG_OF_DMA */
+
+#endif /* __LINUX_OF_DMA_H */
-- 
1.7.9



From nicolas.ferre at atmel.com  Tue Mar 20 06:13:32 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 20 Mar 2012 11:13:32 +0100
Subject: [PATCH 2/2] of: selftest/dma: Add selftest for new DT DMA request
 helpers
In-Reply-To: <6b5dc1fadfd03a48093338b6981c0a7ae7662212.1332237596.git.nicolas.ferre@atmel.com>
References: <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <6b5dc1fadfd03a48093338b6981c0a7ae7662212.1332237596.git.nicolas.ferre@atmel.com>
Message-ID: <066e4deaddca8ac368c2c355c3a77daa9e9057cf.1332237596.git.nicolas.ferre@atmel.com>

Those selftests are covering the new DT DMA helpers. They will test both
error and normal cases.
A custom .xlate() function is also provided to show the use of this API in case
of a different need than the single cell argument.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Stephen Warren <swarren at nvidia.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Arnd Bergmann <arnd at arndb.de>
---
 arch/arm/boot/dts/at91sam9m10g45ek.dts     |    2 +
 arch/arm/boot/dts/testcases/tests-dma.dtsi |   24 +++++++
 arch/arm/boot/dts/testcases/tests.dtsi     |    1 +
 drivers/of/selftest.c                      |  100 ++++++++++++++++++++++++++++
 4 files changed, 127 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/testcases/tests-dma.dtsi

diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a387e77..18a8f3c 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -38,3 +38,5 @@
 		};
 	};
 };
+
+/include/ "testcases/tests.dtsi"
diff --git a/arch/arm/boot/dts/testcases/tests-dma.dtsi b/arch/arm/boot/dts/testcases/tests-dma.dtsi
new file mode 100644
index 0000000..5f0ba93
--- /dev/null
+++ b/arch/arm/boot/dts/testcases/tests-dma.dtsi
@@ -0,0 +1,24 @@
+
+/ {
+	testcase-data {
+		dma-tests {
+			testdmac0: test-dma-controller0 {
+				#dma-cells = <1>;
+			};
+
+			testdmac1: test-dma-controller1 {
+				#dma-cells = <2>;
+			};
+
+			dma-slave-a {
+				dma-request = <&testdmac0 42>;
+			};
+			dma-slave-b {
+				dma-request = <&testdmac1 24>; /* wrong number of values */
+			};
+			dma-slave-c {
+				dma-request = <&testdmac1 24 25>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/testcases/tests.dtsi b/arch/arm/boot/dts/testcases/tests.dtsi
index a7c5067..e3afb2b 100644
--- a/arch/arm/boot/dts/testcases/tests.dtsi
+++ b/arch/arm/boot/dts/testcases/tests.dtsi
@@ -1 +1,2 @@
 /include/ "tests-phandle.dtsi"
+/include/ "tests-dma.dtsi"
diff --git a/drivers/of/selftest.c b/drivers/of/selftest.c
index f24ffd7..3281bfd 100644
--- a/drivers/of/selftest.c
+++ b/drivers/of/selftest.c
@@ -9,6 +9,7 @@
 #include <linux/errno.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_dma.h>
 #include <linux/list.h>
 #include <linux/mutex.h>
 #include <linux/slab.h>
@@ -148,6 +149,104 @@ static void __init of_selftest_property_match_string(void)
 	selftest(rc == -EILSEQ, "unterminated string; rc=%i", rc);
 }
 
+struct two_cells {
+	int cell1;
+	int cell2;
+};
+
+static int of_dma_xlate_twonumbercell(struct of_phandle_args *dma_spec, void *cells)
+{
+	struct two_cells *tc;
+
+	if (!dma_spec)
+		return -EINVAL;
+	if (!cells)
+		return -ENOBUFS;
+	if (WARN_ON(dma_spec->args_count != 2))
+		return -EINVAL;
+
+	tc = (struct two_cells *)cells;
+
+	tc->cell1 = dma_spec->args[0];
+	tc->cell2 = dma_spec->args[1];
+	return 0;
+}
+
+static void __init of_selftest_dma(void)
+{
+	struct device_node *dma_controller0_np;
+	struct device_node *dma_controller1_np;
+	struct device_node *dma_slave_np;
+	int rc;
+	int dma_req;
+	struct two_cells tc;
+
+	pr_info("start\n");
+	dma_controller0_np = of_find_node_by_path("/testcase-data/dma-tests/test-dma-controller0");
+	dma_slave_np = of_find_node_by_path("/testcase-data/dma-tests/dma-slave-a");
+	if (!dma_controller0_np || !dma_slave_np) {
+		pr_err("No testcase data in device tree\n");
+		return;
+	}
+
+	/* wrong usage: DMA controller not registered yet! */
+	rc = of_get_dma_request(dma_slave_np, 0, &dma_req);
+	selftest(rc == -ENODEV, "selftest DMA slave request expected:-ENODEV got:%i\n", rc);
+
+	/* test DMA controller registration */
+	rc = of_dma_controller_register(dma_controller0_np, of_dma_xlate_onenumbercell);
+	selftest(rc == 0, "selftest DMA controller not found: got:%i\n", rc);
+
+	/* wrong usage and error code tests */
+	rc = of_get_dma_request(dma_slave_np, 1, &dma_req);
+	selftest(rc == -EINVAL, "selftest DMA slave request expected:-EINVAL got:%i\n", rc);
+
+	rc = of_get_dma_request(dma_slave_np, 0, NULL);
+	selftest(rc == -ENOBUFS, "selftest DMA slave request expected:-ENOBUFS got:%i\n", rc);
+
+	/* proper use of the API */
+	rc = of_get_dma_request(dma_slave_np, 0, &dma_req);
+	selftest(rc == 0, "selftest DMA slave request error: got:%i\n", rc);
+	selftest(dma_req == 42, "selftest DMA slave request line expected:42 got:%i\n", dma_req);
+
+	of_dma_controller_free(dma_controller0_np);
+
+	/* wrong usage: DMA controller not registered anymore! */
+	rc = of_get_dma_request(dma_slave_np, 0, &dma_req);
+	selftest(rc == -ENODEV, "selftest DMA slave request expected:-ENODEV got:%i\n", rc);
+
+	/* use with a two values DMA request specification */
+	dma_controller1_np = of_find_node_by_path("/testcase-data/dma-tests/test-dma-controller1");
+	dma_slave_np = of_find_node_by_path("/testcase-data/dma-tests/dma-slave-b");
+	if (!dma_controller1_np || !dma_slave_np) {
+		pr_err("No testcase data in device tree\n");
+		return;
+	}
+
+	/* DMA controller registration with custom .xlate() function */
+	rc = of_dma_controller_register(dma_controller1_np, of_dma_xlate_twonumbercell);
+	selftest(rc == 0, "selftest DMA controller not found: got:%i\n", rc);
+
+	/* wrong number of cells */
+	rc = of_get_dma_request(dma_slave_np, 0, &tc);
+	selftest(rc == -EINVAL, "selftest DMA slave request expected:-EINVAL got:%i\n", rc);
+
+	dma_slave_np = of_find_node_by_path("/testcase-data/dma-tests/dma-slave-c");
+	if (!dma_slave_np) {
+		pr_err("No dma-slave-c data in device tree\n");
+		return;
+	}
+
+	/* proper use of the API */
+	rc = of_get_dma_request(dma_slave_np, 0, &tc);
+	selftest(rc == 0, "selftest DMA slave request error: got:%i\n", rc);
+	selftest(tc.cell1 == 24, "selftest DMA slave request line expected:24 got:%i\n", tc.cell1);
+	selftest(tc.cell2 == 25, "selftest DMA slave request line expected:25 got:%i\n", tc.cell2);
+
+	of_dma_controller_free(dma_controller1_np);
+	pr_info("end - %s\n", selftest_passed ? "PASS" : "FAIL");
+}
+
 static int __init of_selftest(void)
 {
 	struct device_node *np;
@@ -162,6 +261,7 @@ static int __init of_selftest(void)
 	pr_info("start of selftest - you will see error messages\n");
 	of_selftest_parse_phandle_with_args();
 	of_selftest_property_match_string();
+	of_selftest_dma();
 	pr_info("end of selftest - %s\n", selftest_passed ? "PASS" : "FAIL");
 	return 0;
 }
-- 
1.7.9



From skannan at codeaurora.org  Tue Mar 20 06:17:10 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 20 Mar 2012 03:17:10 -0700 (PDT)
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <20120320094031.GI3852@pengutronix.de>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
Message-ID: <e22898bc8b69e85f1e6390d7d858f85c.squirrel@www.codeaurora.org>


On Tue, March 20, 2012 2:40 am, Sascha Hauer wrote:
> On Tue, Mar 20, 2012 at 12:54:55AM -0700, Saravana Kannan wrote:
>>
>> On Tue, March 20, 2012 12:20 am, Shawn Guo wrote:
>> > On Mon, Mar 19, 2012 at 08:38:26PM -0700, Saravana Kannan wrote:
>> >> This has a couple of advantages:
>> >> * Completely hides struct clk from many clock platform drivers and
>> >> static
>> >>   clock initialization code.
>> >> * Simplifies the generic clk_register() function and allows adding
>> >> optional
>> >>   fields in the future without modifying the function signature.
>> >> * Allows for simpler static initialization of clocks on all platforms
>> by
>> >>   removing the need for forward delcarations.
>> >> * Halves the number of symbols added for each static clock
>> >> initialization.
>> >>
>> >> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
>> >
>> > I agree this is a reasonable move.  But while you simplify the
>> interface
>> > of clk_register(), why not making a further step to simplify the
>> > following interfaces simple too?
>> >
>> > struct clk *clk_register_fixed_rate(struct device *dev, const char
>> *name,
>> >                 const char *parent_name, unsigned long flags,
>> >                 unsigned long fixed_rate);
>> > struct clk *clk_register_gate(struct device *dev, const char *name,
>> >                 const char *parent_name, unsigned long flags,
>> >                 void __iomem *reg, u8 bit_idx,
>> >                 u8 clk_gate_flags, spinlock_t *lock);
>> > struct clk *clk_register_divider(struct device *dev, const char *name,
>> >                 const char *parent_name, unsigned long flags,
>> >                 void __iomem *reg, u8 shift, u8 width,
>> >                 u8 clk_divider_flags, spinlock_t *lock);
>> > struct clk *clk_register_mux(struct device *dev, const char *name,
>> >                 char **parent_names, u8 num_parents, unsigned long
>> flags,
>> >                 void __iomem *reg, u8 shift, u8 width,
>> >                 u8 clk_mux_flags, spinlock_t *lock);
>>
>> If you simplify those functions further. They would just become
>> clk_register(). I'm not sure I see a value in them in at that point or
>> even in their current form. But if others see (I'm guessing since they
>> acked or didn't nack it), I'm not going to ask to remove them. If
>> everyone
>> agrees that we should just remove them, I would be glad to.
>>
>> It's arguable that these functions for the common hardware types saves
>> the
>> need to deal with the kalloc in every platform driver. But it's not
>> clear
>> to me where they would get these parameters in the first place. Most
>> likely form some sort of static array. At which point, it might as well
>> be
>> a static array of pointers to clk_gated.hw, clk_fixed_rate.hw, etc
>> instead
>> of a platform specific  struct to hold these initializers.
>
> I am using these functions and don't need a static array, I just call
> the functions with the desired parameters.

Sure, then let's leave it in. Curious, where do you get the desired
parameters from? Is it static date in code or is it from DT? You somehow
probe it?

> Overall the clock framework was written in a way that we have to expose
> as little information about the internally used structs as necessary. It
> seems your patches are pulling in the opposite direction now.

I'm not exposing anything that you don't already pass from the platform
driver. Also, you realize that this is very similar to what you suggested
with clk_initializer right? If there is a strong push, we can make a copy
of these inside the struct clk, but for these few init fields I don't see
a point (see earlier email).

-Saravana


-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.




From nicolas.ferre at atmel.com  Tue Mar 20 06:17:36 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 20 Mar 2012 11:17:36 +0100
Subject: [PATCH] of: dma/fixup
In-Reply-To: <6b5dc1fadfd03a48093338b6981c0a7ae7662212.1332237596.git.nicolas.ferre@atmel.com>
References: <6b5dc1fadfd03a48093338b6981c0a7ae7662212.1332237596.git.nicolas.ferre@atmel.com>
Message-ID: <1332238657-12668-1-git-send-email-nicolas.ferre@atmel.com>

---
 include/linux/of_dma.h |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h
index 2865480..da95e37 100644
--- a/include/linux/of_dma.h
+++ b/include/linux/of_dma.h
@@ -18,7 +18,7 @@
 
 struct device_node;
 
-#ifdef CONFIG_OF_DMA
+#ifdef CONFIG_OF
 
 extern int of_dma_controller_register(struct device_node *np,
 			int (*of_dma_xlate)(struct of_phandle_args *, void *));
@@ -29,7 +29,7 @@ extern unsigned int of_dma_count(struct device_node *np);
 
 extern int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
 				      void *dma_req);
-#else /* CONFIG_OF_DMA */
+#else /* CONFIG_OF */
 
 static int of_dma_controller_register(struct device_node *np,
 			int (*of_dma_xlate)(struct of_phandle_args *, void *))
@@ -55,6 +55,6 @@ static int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec,
 {
 	return -ENOSYS;
 }
-#endif /* CONFIG_OF_DMA */
+#endif /* CONFIG_OF */
 
 #endif /* __LINUX_OF_DMA_H */
-- 
1.7.9



From alexg at meprolight.com  Tue Mar 20 06:29:52 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Tue, 20 Mar 2012 12:29:52 +0200
Subject: [PATCH] ARM: i.MX35: Add set_rate and round_rate calls to csi_clk
Message-ID: <1332239392-12639-1-git-send-email-alexg@meprolight.com>

This patch add set_rate and round_rate calls to csi_clk. This is needed
to give mx3-camera control over master clock rate to camera.

Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
---
 arch/arm/mach-imx/clock-imx35.c |   57 +++++++++++++++++++++++++++++++++++++-
 1 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
index ac8238c..3202b56 100644
--- a/arch/arm/mach-imx/clock-imx35.c
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -254,7 +254,7 @@ static unsigned long get_rate_ssi(struct clk *clk)
 	return rate / ((div1 + 1) * (div2 + 1));
 }
 
-static unsigned long get_rate_csi(struct clk *clk)
+static unsigned long csi_get_rate(struct clk *clk)
 {
 	unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
 	unsigned long rate;
@@ -267,6 +267,45 @@ static unsigned long get_rate_csi(struct clk *clk)
 	return rate / (((pdr2 >> 16) & 0x3f) + 1);
 }
 
+static int csi_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long div;
+	unsigned long parent_rate;
+	unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+
+	if (pdr2 & (1 << 7))
+		parent_rate = get_rate_arm();
+	else
+		parent_rate = get_rate_ppll();
+
+	div = parent_rate / rate;
+
+	/* Set clock divider */
+	pdr2 |= ((div - 1) & 0x3f) << 16;
+	__raw_writel(pdr2, CCM_BASE + CCM_PDR2);
+
+	return 0;
+}
+
+static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long div;
+	unsigned long parent_rate;
+	unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+
+	if (pdr2 & (1 << 7))
+		parent_rate = get_rate_arm();
+	else
+		parent_rate = get_rate_ppll();
+
+	div = parent_rate / rate;
+
+	if (parent_rate % rate)
+		div++;
+
+	return parent_rate / div;
+}
+
 static unsigned long get_rate_otg(struct clk *clk)
 {
 	unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
@@ -353,6 +392,20 @@ static void clk_cgr_disable(struct clk *clk)
 		.disable	= clk_cgr_disable,	\
 	}
 
+#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)	\
+	static struct clk name = {                              \
+		.id             = i,                            \
+		.enable_reg     = CCM_BASE + er,                \
+		.enable_shift   = es,                           \
+		.get_rate       = getsetround##_get_rate,       \
+		.set_rate       = getsetround##_set_rate,       \
+		.round_rate     = getsetround##_round_rate,     \
+		.enable         = clk_cgr_enable,               \
+		.disable        = clk_cgr_disable,              \
+		.secondary      = s,                            \
+		.parent         = p,                            \
+	}
+
 DEFINE_CLOCK(asrc_clk,   0, CCM_CGR0,  0, NULL, NULL);
 DEFINE_CLOCK(pata_clk,    0, CCM_CGR0,  2, get_rate_ipg, NULL);
 /* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0,  4, NULL, NULL); */
@@ -403,7 +456,7 @@ DEFINE_CLOCK(wdog_clk,   0, CCM_CGR2, 24, NULL, NULL);
 DEFINE_CLOCK(max_clk,    0, CCM_CGR2, 26, NULL, NULL);
 DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
 
-DEFINE_CLOCK(csi_clk,    0, CCM_CGR3,  0, get_rate_csi, NULL);
+DEFINE_CLOCK1(csi_clk,    0, CCM_CGR3,  0, csi, NULL, NULL);
 DEFINE_CLOCK(iim_clk,    0, CCM_CGR3,  2, NULL, NULL);
 DEFINE_CLOCK(gpu2d_clk,  0, CCM_CGR3,  4, NULL, NULL);
 
-- 
1.7.0.4



From dongas86 at gmail.com  Tue Mar 20 06:53:19 2012
From: dongas86 at gmail.com (Dong Aisheng)
Date: Tue, 20 Mar 2012 03:53:19 -0700
Subject: [PATCH 1/1] net: phylib: remove the length limitation of mii bus
 id
In-Reply-To: <CAAQ0ZWQEoPORMXsf3xV-KPP+hOHk2euj460fORyUALnfPn3Q8g@mail.gmail.com>
References: <1332217386-3586-1-git-send-email-b29396@freescale.com>
 <CAAQ0ZWQEoPORMXsf3xV-KPP+hOHk2euj460fORyUALnfPn3Q8g@mail.gmail.com>
Message-ID: <CAA+hA=Ttc9RDmK1fDPCtqLpf91DYDDFSf3E6zWQ6seyw7sNqTg@mail.gmail.com>

On Tue, Mar 20, 2012 at 1:32 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On 20 March 2012 12:23, Dong Aisheng <b29396 at freescale.com> wrote:
>> From: Dong Aisheng <dong.aisheng at linaro.org>
>>
>> When convert to dt, the length of old mii bus id (17 bytes) is not
>> sufficent to use.
>> For example, the bus id could be 800f0000.ethernet-1:00 in DT.
>>
>> This patch removes the bus id length limitation by changing the
>> bus id to a const char pionter and user could dynamically set the
>> bus id via kasprintf function call.
>>
>> Since then no users use MII_BUS_ID_SIZE any more, just remove it.
>>
>> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
>> ---
>> The simplest way may just change MII_BUS_ID_SIZE to a more bigger size,
>> but i'm not sure that's gonna be accepted.
>
> The simplest fix has been applied on -next tree as below.
>
Oh, i missed it, seems my patch covers that change.
But that patch only fixed wrong phy_name buffer length issue.
My patch is totally remove the length limitation of bus id and phy_name
or the bus id name will be truncated if it's longer than MII_BUS_ID_SIZE
which is not a comfortable limitation.

> commit a7ed07d51c8abdb407be454c6cb6cfad613759d9
> Author: Richard Zhao <richard.zhao at linaro.org>
> Date: ? Sun Jan 29 22:08:12 2012 +0000
>
> ? ?net: fec: correct phy_name buffer length when init phy_name
>
> ? ?Fix the bug that we got wrong phy_name on imx6q sabrelite board.
> ? ?snprintf used wrong length of phy_name.
> ? ?phy_name length is MII_BUS_ID_SIZE + 3 rather not MII_BUS_ID_SIZE.
> ? ?I change it to sizeof(phy_name).
>
> ? ?Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> ? ?Acked-by: Shawn Guo <shawn.guo at linaro.org>
> ? ?Acked-by: Florian Fainelli <florian at openwrt.org>
> ? ?Signed-off-by: David S. Miller <davem at davemloft.net>
>
> diff --git a/drivers/net/ethernet/freescale/fec.c
> b/drivers/net/ethernet/freescale/fec.c
> index 7b25e9c..1c7aad8 100644
> --- a/drivers/net/ethernet/freescale/fec.c
> +++ b/drivers/net/ethernet/freescale/fec.c
> @@ -990,7 +990,7 @@ static int fec_enet_mii_probe(struct net_device *ndev)
> ? ? ? ? ? ? ? ?phy_id = 0;
> ? ? ? ?}
>
> - ? ? ? snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
> + ? ? ? snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
> ? ? ? ?phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?fep->phy_interface);
> ? ? ? ?if (IS_ERR(phy_dev)) {


From tarun.kanti at ti.com  Tue Mar 20 06:53:16 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Tue, 20 Mar 2012 16:23:16 +0530
Subject: [PATCH v4 RESEND 4/7] gpio/omap: fix missing dataout context save in
 _set_gpio_dataout_reg
In-Reply-To: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1332240799-6748-5-git-send-email-tarun.kanti@ti.com>

There are two functions, _set_gpio_dataout_reg() and _set_gpio_dataout_mask()
which writes to dataout register and the dataout context must be saved.
It is missing in the first function, _set_gpio_dataout_reg(). Fix this.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 drivers/gpio/gpio-omap.c |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 8901d57..bbe9648 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -120,10 +120,13 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
 	void __iomem *reg = bank->base;
 	u32 l = GPIO_BIT(bank, gpio);
 
-	if (enable)
+	if (enable) {
 		reg += bank->regs->set_dataout;
-	else
+		bank->context.dataout |= l;
+	} else {
 		reg += bank->regs->clr_dataout;
+		bank->context.dataout &= ~l;
+	}
 
 	__raw_writel(l, reg);
 }
-- 
1.7.0.4



From tarun.kanti at ti.com  Tue Mar 20 06:53:15 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Tue, 20 Mar 2012 16:23:15 +0530
Subject: [PATCH v4 RESEND 3/7] gpio/omap: fix _set_gpio_irqenable
 implementation
In-Reply-To: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1332240799-6748-4-git-send-email-tarun.kanti@ti.com>

This function should be capable of both enabling and disabling interrupts
based upon the *enable* parameter. Right now the function only enables
the interrupt and *enable* is not used at all. So add the interrupt
disable capability also using the parameter.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 2042857..8901d57 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -484,7 +484,10 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 
 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
 {
-	_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
+	if (enable)
+		_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
+	else
+		_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
 }
 
 /*
-- 
1.7.0.4



From tarun.kanti at ti.com  Tue Mar 20 06:53:17 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Tue, 20 Mar 2012 16:23:17 +0530
Subject: [PATCH v4 RESEND 5/7] gpio/omap: fix incorrect context restore logic
 in omap_gpio_runtime_*
In-Reply-To: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1332240799-6748-6-git-send-email-tarun.kanti@ti.com>

In omap_gpio_runtime_suspend/resume() the context save/restore should
be independent of bank->enabled_non_wakeup_gpios. This was preventing
context restore of GPIO lines which are not wakeup enabled.

Reported-by: Govindraj Raja <govindraj.raja at ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 drivers/gpio/gpio-omap.c |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index bbe9648..bcb1061 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1247,9 +1247,6 @@ static int omap_gpio_runtime_suspend(struct device *dev)
 	 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
 	 * generated.  See OMAP2420 Errata item 1.101.
 	 */
-	if (!(bank->enabled_non_wakeup_gpios))
-		goto update_gpio_context_count;
-
 	bank->saved_datain = __raw_readl(bank->base +
 						bank->regs->datain);
 	l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
@@ -1298,7 +1295,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
 	__raw_writel(bank->context.risingdetect,
 		     bank->base + bank->regs->risingdetect);
 
-	if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
+	if (!bank->workaround_enabled) {
 		spin_unlock_irqrestore(&bank->lock, flags);
 		return 0;
 	}
-- 
1.7.0.4



From tarun.kanti at ti.com  Tue Mar 20 06:53:18 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Tue, 20 Mar 2012 16:23:18 +0530
Subject: [PATCH v4 RESEND 6/7] gpio/omap: fix incorrect update to
 context.irqenable1
In-Reply-To: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1332240799-6748-7-git-send-email-tarun.kanti@ti.com>

In _enable_gpio_irqbank() when bank->regs->set_irqenable is valid,
gpio_mask can be directly set by writing to set_irqenable register
without overwriting current value. In order to ensure the same is
stored in context.irqenable1, we must read from regs->irqenable
instead of overwriting it with gpio_mask.
The overwriting makes sense only in the second case where irqenable
is explicitly read and updated with new gpio_mask before writing it
back. However, for consistency reading regs->irqenable into the
bank->context.irqenable1 takes care of both the scenarios.

        if (bank->regs->set_irqenable) {
                reg += bank->regs->set_irqenable;
                l = gpio_mask;
        } else {
                reg += bank->regs->irqenable;
                l = __raw_readl(reg);
                if (bank->regs->irqenable_inv)
                        l &= ~gpio_mask;
                else
                        l |= gpio_mask;
        }

Make the same change for _disable_gpio_irqbank().

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 drivers/gpio/gpio-omap.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index bcb1061..6c17e58 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -451,6 +451,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 	if (bank->regs->set_irqenable) {
 		reg += bank->regs->set_irqenable;
 		l = gpio_mask;
+		bank->context.irqenable1 |= gpio_mask;
 	} else {
 		reg += bank->regs->irqenable;
 		l = __raw_readl(reg);
@@ -458,10 +459,10 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 			l &= ~gpio_mask;
 		else
 			l |= gpio_mask;
+		bank->context.irqenable1 = l;
 	}
 
 	__raw_writel(l, reg);
-	bank->context.irqenable1 = l;
 }
 
 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
@@ -472,6 +473,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 	if (bank->regs->clr_irqenable) {
 		reg += bank->regs->clr_irqenable;
 		l = gpio_mask;
+		bank->context.irqenable1 &= ~gpio_mask;
 	} else {
 		reg += bank->regs->irqenable;
 		l = __raw_readl(reg);
@@ -479,10 +481,10 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 			l |= gpio_mask;
 		else
 			l &= ~gpio_mask;
+		bank->context.irqenable1 = l;
 	}
 
 	__raw_writel(l, reg);
-	bank->context.irqenable1 = l;
 }
 
 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
-- 
1.7.0.4



From tarun.kanti at ti.com  Tue Mar 20 06:53:13 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Tue, 20 Mar 2012 16:23:13 +0530
Subject: [PATCH v4 RESEND 1/7] gpio/omap: fix wakeup_en register update in
 _set_gpio_wakeup()
In-Reply-To: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1332240799-6748-2-git-send-email-tarun.kanti@ti.com>

There are two ways through which wakeup_en register can be programmed
using gpiolib APIs as shown below. It is seen that in the second case
in _set_gpio_wakeup(), even though bank->suspend_wakeup is updated
correctly, its value is not programmed in wakeup_en register. Fix this.

irq_set_type()->gpio_irq_type()->_set_gpio_triggering()->set_gpio_trigger()
irq_set_wake()->gpio_wake_enable()->_set_gpio_wakeup()

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 drivers/gpio/gpio-omap.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 7cbad85..1a144ac 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -511,6 +511,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
 	else
 		bank->suspend_wakeup &= ~gpio_bit;
 
+	__raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en);
 	spin_unlock_irqrestore(&bank->lock, flags);
 
 	return 0;
-- 
1.7.0.4



From tarun.kanti at ti.com  Tue Mar 20 06:53:12 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Tue, 20 Mar 2012 16:23:12 +0530
Subject: [PATCH v4 RESEND 0/7] gpio/omap: Some more driver fixes
Message-ID: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>

This series excludes the cleanup patches as suggested by Kevin from
the previously posted series.

The fixes include correction of _set_gpio_irqenable() implementation,
missing wakeup_en register update in set_gpio_wakeup(), type mismatch
of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
register update in set_gpio_dataout_() and few corrections in context
save logic.

It is baselined on top of:
git://git.secretlab.ca/git/linux-2.6.git gpio/next
Commit: 81b279d80a63628e580c71a31d30a8c3b3047ad4

Series is available here for reference:
git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_more_fixes

Power Test:
Off-mode and Retention on OMAP3430 (Suspend and Idle paths).
Also confirmed that dataout register content preserved over
off-mode.

Functional Test:
OMAP2430, OMAP3430SDP, ZOOM3, OMAP4430, OMAP4-BLAZE

v4:
a) Implemented all comments on v3 which are mostly related to
avoiding unnecessary register read while updating the context.

b) Folded:
gpio/omap: fix dataout register overwrite in _set_gpio_dataout
into:
gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg

v3:
- Added 4 more additional patches to the previous series
 which are all bug fixes.

v2:
- Added a new patch to update wakeup_en register in _set_gpio_wakeup()
 in addition to updating bank->context.wake_en.

- Added a new patch to remove redundant decoding of gpio offset in
 gpio_get(), _get_gpio_datain() and _get_gpio_dataout().

- Added a new patch to remove suspend/resume callbacks because the
 operations performed with the callbacks are redundant.

Tarun Kanti DebBarma (7):
  gpio/omap: fix wakeup_en register update in _set_gpio_wakeup()
  gpio/omap: fix trigger type to unsigned
  gpio/omap: fix _set_gpio_irqenable implementation
  gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg
  gpio/omap: fix incorrect context restore logic in omap_gpio_runtime_*
  gpio/omap: fix incorrect update to context.irqenable1
  gpio/omap: fix redundant decoding of gpio offset

 drivers/gpio/gpio-omap.c |   47 ++++++++++++++++++++++++---------------------
 1 files changed, 25 insertions(+), 22 deletions(-)



From tarun.kanti at ti.com  Tue Mar 20 06:53:19 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Tue, 20 Mar 2012 16:23:19 +0530
Subject: [PATCH v4 RESEND 7/7] gpio/omap: fix redundant decoding of gpio offset
In-Reply-To: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1332240799-6748-8-git-send-email-tarun.kanti@ti.com>

In gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of
un-necessary operation to compute gpio mask. The gpio offset passed
to gpio_get() is sufficient to do that.

Here is Russell's original comment:
Can someone explain to me this:

static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
       void __iomem *reg = bank->base + bank->regs->datain;

       return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
}

static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
       struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
       void __iomem *reg = bank->base;
       int gpio = chip->base + offset;
       u32 mask = GPIO_BIT(bank, gpio);

       if (gpio_is_input(bank, mask))
               return _get_gpio_datain(bank, gpio);
       else
               return _get_gpio_dataout(bank, gpio);
}

Given that bank->width on OMAP is either 32 or 16, and GPIO numbers for
any GPIO chip are always aligned to 32 or 16, why does this code bother
adding the chips base gpio number and then modulo the width?

Surely this means if - for argument sake - you registered a GPIO chip
with 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0
bit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be
chip 1 bit 0..7.

However, if you registered a GPIO chip with 16 lines first, it would
mean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be
chip 1 bit 0..15.

Surely this kind of behaviour is not intended?

Is there a reason why the bitmask can't just be (1 << offset) where
offset is passed into these functions as GPIO number - chip->base ?

Reported-by: Russell King - ARM Linux <linux at arm.linux.org.uk>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 drivers/gpio/gpio-omap.c |   18 +++++++-----------
 1 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 6c17e58..1adc2ec 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -147,18 +147,18 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
 	bank->context.dataout = l;
 }
 
-static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
+static int _get_gpio_datain(struct gpio_bank *bank, int offset)
 {
 	void __iomem *reg = bank->base + bank->regs->datain;
 
-	return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
+	return (__raw_readl(reg) & (1 << offset)) != 0;
 }
 
-static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
+static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
 {
 	void __iomem *reg = bank->base + bank->regs->dataout;
 
-	return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
+	return (__raw_readl(reg) & (1 << offset)) != 0;
 }
 
 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
@@ -865,19 +865,15 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
 static int gpio_get(struct gpio_chip *chip, unsigned offset)
 {
 	struct gpio_bank *bank;
-	void __iomem *reg;
-	int gpio;
 	u32 mask;
 
-	gpio = chip->base + offset;
 	bank = container_of(chip, struct gpio_bank, chip);
-	reg = bank->base;
-	mask = GPIO_BIT(bank, gpio);
+	mask = (1 << offset);
 
 	if (gpio_is_input(bank, mask))
-		return _get_gpio_datain(bank, gpio);
+		return _get_gpio_datain(bank, offset);
 	else
-		return _get_gpio_dataout(bank, gpio);
+		return _get_gpio_dataout(bank, offset);
 }
 
 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
-- 
1.7.0.4



From tarun.kanti at ti.com  Tue Mar 20 06:53:14 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Tue, 20 Mar 2012 16:23:14 +0530
Subject: [PATCH v4 RESEND 2/7] gpio/omap: fix trigger type to unsigned
In-Reply-To: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1332240799-6748-3-git-send-email-tarun.kanti@ti.com>

The GPIO trigger parameter is of type unsigned.
enum {
        IRQ_TYPE_NONE           = 0x00000000,
        IRQ_TYPE_EDGE_RISING    = 0x00000001,
        IRQ_TYPE_EDGE_FALLING   = 0x00000002,
        IRQ_TYPE_EDGE_BOTH      = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
        IRQ_TYPE_LEVEL_HIGH     = 0x00000004,
        IRQ_TYPE_LEVEL_LOW      = 0x00000008,
        IRQ_TYPE_LEVEL_MASK     = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
        IRQ_TYPE_SENSE_MASK     = 0x0000000f,

        IRQ_TYPE_PROBE          = 0x00000010,
...
};
Even though gpio_irq_type(struct irq_data *d, unsigned type) has the right type
of parameter, the subsequent called functions set_gpio_triggering() and
set_gpio_trigger() wrongly makes it signed integer. Fix this.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Felipe Balbi <balbi at ti.com>
---
 drivers/gpio/gpio-omap.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 1a144ac..2042857 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -245,7 +245,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
 }
 
 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
-						int trigger)
+						unsigned trigger)
 {
 	void __iomem *base = bank->base;
 	u32 gpio_bit = 1 << gpio;
@@ -327,7 +327,8 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 #endif
 
-static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
+static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
+							unsigned trigger)
 {
 	void __iomem *reg = bank->base;
 	void __iomem *base = bank->base;
-- 
1.7.0.4



From tarun.kanti at ti.com  Tue Mar 20 06:59:39 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Tue, 20 Mar 2012 16:29:39 +0530
Subject: [PATCH v2 0/4] ARM: OMAP: boards: changes to support dynamic irq
 alloc
In-Reply-To: <4F68471A.4010502@ti.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
 <20120319191743.GB9859@atomide.com> <4F67B9F9.1030906@ti.com>
 <20120319233910.GF9859@atomide.com> <4F68471A.4010502@ti.com>
Message-ID: <CAC83ZvLf=fkuvf6VN1gwauFirO2cQsNib3ANWnJrujWGNYS24Q@mail.gmail.com>

On Tue, Mar 20, 2012 at 2:30 PM, Cousson, Benoit <b-cousson at ti.com> wrote:
> On 3/20/2012 12:39 AM, Tony Lindgren wrote:
>>
>> * Cousson, Benoit<b-cousson at ti.com> ?[120319 16:00]:
>>>
>>> Hi Tony,
>>>
>>> On 3/19/2012 8:17 PM, Tony Lindgren wrote:
>>>>
>>>> * Tarun Kanti DebBarma<tarun.kanti at ti.com> ? [120319 05:09]:
>>>>>
>>>>> These two patches incorporate changes to OMAP1 and OMAP2 platforms
>>>>> board files whereby older references to OMAP_GPIO_IRQ macro are
>>>>> now replaced with gpio_to_irq(), thereby getting rid of static
>>>>> irq references.
>>>>>
>>>>> Reference:
>>>>> git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git omap/dt
>>>>> Commit: 9a0cee711448335ec43eae83272495e9334c0098
>>>>
>>>>
>>>> Can you please tell the exact two commits causing this
>>>> breakage?
>>>
>>>
>>> Well, this is the GPIO DT + SPARSE_IRQ series I have done. It
>>> appears that the boards I have were already using properly
>>> gpio_to_irq() and thus were working fine with this series.
>>>
>>> But this is unfortunately not the case of most OMAP2 and 3 legacy
>>> boards that were still using an old OMAP way of converting GPIO to
>>> IRQ and were never modified to take advantage of the gpiolib stuff.
>>>
>>> So if these patches are apply before the GPIO DT + SPARSE_IRQ
>>> series, there will be no breakage at all.
>>>
>>> All the cleanup we have never done before will hurt us at some point
>>> when we will start using more extensively newer fmwk (DT,
>>> sparse_irq, dmaengine...). It was not done on purpose, but this GPIO
>>> series highlighted this remaining static broken mapping inside OMAP
>>> boards.
>>
>>
>> Yes I understand. But still, which patch(s) cause the issue
>> so we can put that in the changelog for the fixes?
>
>
> OK, here they are:
> 25db711 gpio/omap: Fix IRQ handling for SPARSE_IRQ
> 384ebe1 gpio/omap: Add DT support to GPIO driver
>
> Tarun,
>
> You should indeed add the references in your cover letter.
Yes, I will specify them in the cover letter.
--
Tarun
>
>
>>>> I'm baffled how despite all the effort for previnting
>>>> issues like this this still happen. These all seem valid
>>>> fixes and clean up things, but how come this was not seen
>>>> earlier?
>>>
>>>
>>> Maybe because there are much more boards inside mach-omap2 directory
>>> than inside my cubicle... :-(
>>
>>
>> Well somehow we need to make sure that patches get properly
>> tested on a reasonable selection of boards. This pretty much
>> breaks things for 21 boards out of the 51 board-*.c files :(
>
>
> What is too bad is that one broken board was enough to figured out the issue
> and fix all the other ones. I just did not have that one :-(
>
> Regards,
> Benoit


From dongas86 at gmail.com  Tue Mar 20 08:49:06 2012
From: dongas86 at gmail.com (Dong Aisheng)
Date: Tue, 20 Mar 2012 05:49:06 -0700
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20120319220224.ABF5A3E0A04@localhost>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
 <20120316030134.GA5161@shlinux2.ap.freescale.net>
 <20120318184749.BB15D3E07BF@localhost>
 <20326.55337.249575.289067@ipc1.ka-ro>
 <20120319150601.B783A3E05A5@localhost>
 <20327.25470.723875.916422@ipc1.ka-ro>
 <20120319220224.ABF5A3E0A04@localhost>
Message-ID: <CAA+hA=R8hLZMyRASRim28MNzX4jyE3nsaJ3DPzgxDtUmqtH62w@mail.gmail.com>

On Mon, Mar 19, 2012 at 3:02 PM, Grant Likely <grant.likely at secretlab.ca> wrote:
> On Mon, 19 Mar 2012 17:49:02 +0100, Lothar Wa?mann <LW at KARO-electronics.de> wrote:
>> Hi,
>>
>> Grant Likely writes:
>> > On Mon, 19 Mar 2012 07:54:33 +0100, Lothar Wa?mann <LW at KARO-electronics.de> wrote:
>> > > Grant Likely writes:
>> > > > On Fri, 16 Mar 2012 11:01:35 +0800, Dong Aisheng <aisheng.dong at freescale.com> wrote:
>> > > > > On Thu, Mar 15, 2012 at 07:22:04PM +0800, Lothar Wa?mann wrote:
>> > > > > > Dong Aisheng writes:
>> > > > > > > On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa?mann wrote:
>> > > > > > Anyway there is no definite spec how the MAC address(es) are stored
>> > > > > > in the fuse map. Thus reading the MAC from there is more or less
>> > > > > > platform specific.
>> > > > > >
>> > > > > It's just provide one more option since there are customers storing the MAC
>> > > > > in the fuse map.
>> > > >
>> > > > That should be straight forward to support; have a property that
>> > > > specifies the method used for fetching/calculating the MAC.
>> > > >
>> > > Executable code stored inside a DT blob? ;)
>> >
>> > I know you're joking here, but I'm going to answer seriously
>> > anyway... Absolutely not. ?What I'm suggesting is a property that
>> > specifies the method used to determine the mac address. ?Something
>> > like (off the top of my head):
>> >
>> > ? ? local-mac-address = [01 02 03 00 00 00];
>> > ? ? local-mac-mask = [0xff 0xff 0xff 0 0 0];
>> > ? ? mac-encoding = "append-serial-number";
>> >
>> That still does not specify where the remaining part of the MAC is
>> stored and how it should be retrieved.
>
> I'm suggesting that you define a string that means something specific;
> that hopefully can be shared by multiple platforms. ?For example,
> "append-serial-number" might mean start with the values selected by
> AND of local-mac-address and local-mac-mask, and OR in the board's
> serial number. ?You would need to define something that worked if this
> was the solution you used.
>
I'm intend to Grant's this suggestion.
This can be shared by all other imx platforms which stores mac address in
fuse map and this is commonly used by customer.
Then we do not need keep writing repeat code for different platforms
via platform
data.

For Lothar's question, we can add a property fuse_mac_offset to indicate
read mac from fuse map and where to read it.
For how many bytes to read, we can calculate it from the local-mac-mask.
For example, local-mac-mask = [0xff 0xff 0xff 0 0 0], we can get the size
as 3 bypes.

Then we have three properties:
local-mac-address = [01 02 03 00 00 00];
local-mac-mask = [0xff 0xff 0xff 0 0 0];
fuse_mac_offset = <1>;

In fec driver, the final mac address can be got by:
local-mac-address & local-mac-mask | (read_fuse(1) & 0xffffff)

Lathar,
Do you think if this is ok?

>> > Okay, if so then it would be wise to have a reliable function for the
>> > MAC driver to call to lookup it's address as determined by platform
>> > code. ?Alternately, the platform code can write the correct mac
>> > address into the device tree node at init time (see
>> > prom_update_property() and prom_add_property()).
>> >
>> That sounds good. Didn't know about those functions. That could be
>> used to mimic the current behaviour of supplying the MAC via
>> platform_data.
>
> I'm okay with doing this; but make sure you remove the bogus
> local-mac-address from the .dts file.
>
This is a backup solution to me if the above solution you suggested can not
work.

Regards
Dong Aisheng


From prakash.pm at ti.com  Tue Mar 20 08:57:55 2012
From: prakash.pm at ti.com (Manjunathappa, Prakash)
Date: Tue, 20 Mar 2012 12:57:55 +0000
Subject: [PATCH v5 2/3] arm:davinci: move emif driver to mfd framework
In-Reply-To: <20120316172908.GG20524@sortiz-mobl>
References: <y> <1330005504-25321-3-git-send-email-prakash.pm@ti.com>
 <20120227142638.GN27687@sortiz-mobl>
 <A73F36158E33644199EB82C5EC81C7BC3176D103@DBDE01.ent.ti.com>
 <20120301112329.GI9008@sortiz-mobl>
 <A73F36158E33644199EB82C5EC81C7BC317702E9@DBDE01.ent.ti.com>
 <20120316172908.GG20524@sortiz-mobl>
Message-ID: <A73F36158E33644199EB82C5EC81C7BC3178627F@DBDE01.ent.ti.com>

Hi Samuel,

On Fri, Mar 16, 2012 at 22:59:08, Samuel Ortiz wrote:
> Hi Prakash,
> 
> On Tue, Mar 06, 2012 at 01:12:25PM +0000, Manjunathappa, Prakash wrote:
> > Hi Samuel,
> > 
> > May be I did not do a good job giving complete information on this earlier.
> > So I have replied on top of my mail with below information (seems you missed it)
> > 
> I did get it, sorry for not being able to reply earlier.
> 
> 
> > Taking above points into consideration Arnd Bergmann suggested to move AEMIF driver to
> > MFD framework [1], relevant portion of his mail as follows,
> > 
> > " If you want it to provide endpoint devices that are handled by
> > distinct subsystems in Linux, I would make it an mfd multifunction
> > device and make the common... "
> You're missing that part of the quote:
> 
> "...code a driver that scans the connected memories in order to register
> its child devices for each of the subsystems."
> 

emif is not discoverable interface, does not support scanning for connected devices.

Could you please let me know if there is any other way to achieve this? I will be happy
to incorporate that and submit next version of the patch.

Thanks,
Prakash


From s.hauer at pengutronix.de  Tue Mar 20 09:08:05 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 20 Mar 2012 14:08:05 +0100
Subject: [PATCH] ARM: i.MX35: Add set_rate and round_rate calls to csi_clk
In-Reply-To: <1332239392-12639-1-git-send-email-alexg@meprolight.com>
References: <1332239392-12639-1-git-send-email-alexg@meprolight.com>
Message-ID: <20120320130805.GK3852@pengutronix.de>

On Tue, Mar 20, 2012 at 12:29:52PM +0200, Alex Gershgorin wrote:
> This patch add set_rate and round_rate calls to csi_clk. This is needed
> to give mx3-camera control over master clock rate to camera.

The file you are patching is scheduled for removal in favour for the
common clock framework, so you are flogging a dead horse here. I suggest
that you wait some time until I finished the i.MX35 patches for this.

> +static int csi_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	unsigned long div;
> +	unsigned long parent_rate;
> +	unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
> +
> +	if (pdr2 & (1 << 7))
> +		parent_rate = get_rate_arm();
> +	else
> +		parent_rate = get_rate_ppll();
> +
> +	div = parent_rate / rate;
> +
> +	/* Set clock divider */
> +	pdr2 |= ((div - 1) & 0x3f) << 16;

btw you forget to clear the divider bits in pdr2 before
setting the new values.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From LW at KARO-electronics.de  Tue Mar 20 09:17:48 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Tue, 20 Mar 2012 14:17:48 +0100
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <CAA+hA=R8hLZMyRASRim28MNzX4jyE3nsaJ3DPzgxDtUmqtH62w@mail.gmail.com>
References: <1331628428-24017-1-git-send-email-b29396@freescale.com>
 <1331628428-24017-2-git-send-email-b29396@freescale.com>
 <20120313172351.97C5E3E053B@localhost>
 <20120314124512.GG1180@shlinux2.ap.freescale.net>
 <20120314141643.GP3852@pengutronix.de>
 <20120315030206.GB13022@shlinux2.ap.freescale.net>
 <20321.37353.63115.664975@ipc1.ka-ro>
 <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
 <20120316030134.GA5161@shlinux2.ap.freescale.net>
 <20120318184749.BB15D3E07BF@localhost>
 <20326.55337.249575.289067@ipc1.ka-ro>
 <20120319150601.B783A3E05A5@localhost>
 <20327.25470.723875.916422@ipc1.ka-ro>
 <20120319220224.ABF5A3E0A04@localhost>
 <CAA+hA=R8hLZMyRASRim28MNzX4jyE3nsaJ3DPzgxDtUmqtH62w@mail.gmail.com>
Message-ID: <20328.33660.472382.117901@ipc1.ka-ro>

Hi,

Dong Aisheng writes:
> On Mon, Mar 19, 2012 at 3:02 PM, Grant Likely <grant.likely at secretlab.ca> wrote:
> > On Mon, 19 Mar 2012 17:49:02 +0100, Lothar Wa?mann <LW at KARO-electronics.de> wrote:
> >> Hi,
> >>
> >> Grant Likely writes:
> >> > On Mon, 19 Mar 2012 07:54:33 +0100, Lothar Wa?mann <LW at KARO-electronics.de> wrote:
> >> > > Grant Likely writes:
> >> > > > On Fri, 16 Mar 2012 11:01:35 +0800, Dong Aisheng <aisheng.dong at freescale.com> wrote:
> >> > > > > On Thu, Mar 15, 2012 at 07:22:04PM +0800, Lothar Wa?mann wrote:
> >> > > > > > Dong Aisheng writes:
> >> > > > > > > On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa?mann wrote:
> >> > > > > > Anyway there is no definite spec how the MAC address(es) are stored
> >> > > > > > in the fuse map. Thus reading the MAC from there is more or less
> >> > > > > > platform specific.
> >> > > > > >
> >> > > > > It's just provide one more option since there are customers storing the MAC
> >> > > > > in the fuse map.
> >> > > >
> >> > > > That should be straight forward to support; have a property that
> >> > > > specifies the method used for fetching/calculating the MAC.
> >> > > >
> >> > > Executable code stored inside a DT blob? ;)
> >> >
> >> > I know you're joking here, but I'm going to answer seriously
> >> > anyway... Absolutely not. ?What I'm suggesting is a property that
> >> > specifies the method used to determine the mac address. ?Something
> >> > like (off the top of my head):
> >> >
> >> > ? ? local-mac-address = [01 02 03 00 00 00];
> >> > ? ? local-mac-mask = [0xff 0xff 0xff 0 0 0];
> >> > ? ? mac-encoding = "append-serial-number";
> >> >
> >> That still does not specify where the remaining part of the MAC is
> >> stored and how it should be retrieved.
> >
> > I'm suggesting that you define a string that means something specific;
> > that hopefully can be shared by multiple platforms. ?For example,
> > "append-serial-number" might mean start with the values selected by
> > AND of local-mac-address and local-mac-mask, and OR in the board's
> > serial number. ?You would need to define something that worked if this
> > was the solution you used.
> >
> I'm intend to Grant's this suggestion.
> This can be shared by all other imx platforms which stores mac address in
> fuse map and this is commonly used by customer.
> Then we do not need keep writing repeat code for different platforms
> via platform
> data.
> 
> For Lothar's question, we can add a property fuse_mac_offset to indicate
> read mac from fuse map and where to read it.
>
That's not really enough. The format (big-endian vs. little-endian)
may also differ. But it's not really necessary, if the solution with
prom_update_property() works, since then platform code has full
control over the MAC.

> For how many bytes to read, we can calculate it from the local-mac-mask.
> For example, local-mac-mask = [0xff 0xff 0xff 0 0 0], we can get the size
> as 3 bypes.
> 
> Then we have three properties:
> local-mac-address = [01 02 03 00 00 00];
> local-mac-mask = [0xff 0xff 0xff 0 0 0];
> fuse_mac_offset = <1>;
> 
> In fec driver, the final mac address can be got by:
> local-mac-address & local-mac-mask | (read_fuse(1) & 0xffffff)
> 
> Lathar,
> Do you think if this is ok?
>
No. IMO the FEC driver itself should not read any fuses.
Reading fuses is a SoC specific thing and the FEC driver should not
depend on the idiosyncrasies of some SoC wrt. anything else but the
implementation of the FEC itself.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From subashrp at gmail.com  Tue Mar 20 09:50:37 2012
From: subashrp at gmail.com (Subash Patel)
Date: Tue, 20 Mar 2012 19:20:37 +0530
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <CAHQjnOO5DLOj8Fw=ZriSnXg8W3k7y8Dnu--Peqe6JJX0xGMhoQ@mail.gmail.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <CAHQjnOO5DLOj8Fw=ZriSnXg8W3k7y8Dnu--Peqe6JJX0xGMhoQ@mail.gmail.com>
Message-ID: <4F688B2D.20808@gmail.com>

Sorry for digging this very late. But as part of integrating dma_map v7 
& sysmmu v12 on 3.3-rc5, I am facing below issue:

a) By un-selecting IOMMU in menu config, I am able to allocate memory in 
vb2-dma-contig

b) When I enable SYSMMU support for the IP's, I am receiving below fault:

Unhandled fault: external abort on non-linefetch (0x818) at 0xb6f55000

I think this has something to do with the access to the SYSMMU registers 
for writing the page table. Has anyone of you faced this issue while 
testing these(dma_map+iommu) patches on kernel mentioned above? This 
must be something related to recent changes, as I didn't have issues 
with these patches on 3.2 kernel.

Regards,
Subash


On 03/02/2012 01:35 PM, KyongHo Cho wrote:
> On Thu, Mar 1, 2012 at 12:04 AM, Marek Szyprowski
> <m.szyprowski at samsung.com>  wrote:
>> +/**
>> + * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
>> + * @dev: valid struct device pointer
>> + * @sg: list of buffers
>> + * @nents: number of buffers to map
>> + * @dir: DMA transfer direction
>> + *
>> + * Map a set of buffers described by scatterlist in streaming mode for DMA.
>> + * The scatter gather list elements are merged together (if possible) and
>> + * tagged with the appropriate dma address and length. They are obtained via
>> + * sg_dma_{address,length}.
>> + */
>> +int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
>> +                    enum dma_data_direction dir, struct dma_attrs *attrs)
>> +{
>> +       struct scatterlist *s = sg, *dma = sg, *start = sg;
>> +       int i, count = 0;
>> +       unsigned int offset = s->offset;
>> +       unsigned int size = s->offset + s->length;
>> +       unsigned int max = dma_get_max_seg_size(dev);
>> +
>> +       for (i = 1; i<  nents; i++) {
>> +               s->dma_address = ARM_DMA_ERROR;
>> +               s->dma_length = 0;
>> +
>> +               s = sg_next(s);
>> +
>> +               if (s->offset || (size&  ~PAGE_MASK) || size + s->length>  max) {
>> +                       if (__map_sg_chunk(dev, start, size,&dma->dma_address,
>> +                           dir)<  0)
>> +                               goto bad_mapping;
>> +
>> +                       dma->dma_address += offset;
>> +                       dma->dma_length = size - offset;
>> +
>> +                       size = offset = s->offset;
>> +                       start = s;
>> +                       dma = sg_next(dma);
>> +                       count += 1;
>> +               }
>> +               size += s->length;
>> +       }
>> +       if (__map_sg_chunk(dev, start, size,&dma->dma_address, dir)<  0)
>> +               goto bad_mapping;
>> +
>> +       dma->dma_address += offset;
>> +       dma->dma_length = size - offset;
>> +
>> +       return count+1;
>> +
>> +bad_mapping:
>> +       for_each_sg(sg, s, count, i)
>> +               __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
>> +       return 0;
>> +}
>> +
> This looks that the given sg list specifies the list of physical
> memory chunks and
> the list of IO virtual memory chunks at the same time after calling
> arm_dma_map_sg().
> It can happen that dma_address and dma_length of a sg entry does not
> correspond to
> physical memory information of the sg entry.
>
> I think it is beneficial for handling IO virtual memory.
>
> However, I worry about any other problems caused by a single sg entry contains
> information from 2 different context.
>
> Regards,
>
> Cho KyongHo.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From alexg at meprolight.com  Tue Mar 20 09:57:52 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Tue, 20 Mar 2012 15:57:52 +0200
Subject: [PATCH] ARM: i.MX35: Add set_rate and round_rate calls to csi_clk
In-Reply-To: <20120320130805.GK3852@pengutronix.de>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CC34C59E5@MEP-EXCH.meprolight.com>


Hi Sascha,

Thanks for you comments.

On Tue, Mar 20, 2012 at 12:29:52PM +0200, Alex Gershgorin wrote:
> This patch add set_rate and round_rate calls to csi_clk. This is needed
> to give mx3-camera control over master clock rate to camera.

> >The file you are patching is scheduled for removal in favour for the
> >common clock framework, so you are flogging a dead horse here. I suggest
> >that you wait some time until I finished the i.MX35 patches for this.

This patch allows me to move forward, without this patch the camera just does not work. I'll use it as a temporary patch and happily wait for you to finish your work on i.MX35 patches :-)
 
> +static int csi_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	unsigned long div;
> +	unsigned long parent_rate;
> +	unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
> +
> +	if (pdr2 & (1 << 7))
> +		parent_rate = get_rate_arm();
> +	else
> +		parent_rate = get_rate_ppll();
> +
> +	div = parent_rate / rate;
> +
> +	/* Set clock divider */
> +	pdr2 |= ((div - 1) & 0x3f) << 16;

> >btw you forget to clear the divider bits in pdr2 before
> >setting the new values.

 Totally agree with you.



Regards,
Alex Gershgorin




From shawn.guo at linaro.org  Tue Mar 20 10:02:24 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 20 Mar 2012 22:02:24 +0800
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <1331878280-2758-3-git-send-email-mturquette@linaro.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
Message-ID: <20120320140220.GE32469@S2101-09.ap.freescale.net>

On Thu, Mar 15, 2012 at 11:11:19PM -0700, Mike Turquette wrote:
...
> +struct clk_ops {
> +	int		(*prepare)(struct clk_hw *hw);
> +	void		(*unprepare)(struct clk_hw *hw);
> +	int		(*enable)(struct clk_hw *hw);
> +	void		(*disable)(struct clk_hw *hw);
> +	int		(*is_enabled)(struct clk_hw *hw);
> +	unsigned long	(*recalc_rate)(struct clk_hw *hw,
> +					unsigned long parent_rate);

I believe I have heard people love the interface with parent_rate
passed in.  I love that too.  But I would like to ask the same thing
on .round_rate and .set_rate as well for the same reason why we have
it for .recalc_rate.

> +	long		(*round_rate)(struct clk_hw *hw, unsigned long,
> +					unsigned long *);

Yes, we already have parent_rate passed in .round_rate with an pointer.
But I think it'd be better to have it passed in no matter flag
CLK_SET_RATE_PARENT is set or not.  Something like:

8<---
@@ -584,7 +584,7 @@ EXPORT_SYMBOL_GPL(clk_get_rate);
  */
 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
 {
-       unsigned long unused;
+       unsigned long parent_rate = 0;

        if (!clk)
                return -EINVAL;
@@ -592,10 +592,10 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
        if (!clk->ops->round_rate)
                return clk->rate;

-       if (clk->flags & CLK_SET_RATE_PARENT)
-               return clk->ops->round_rate(clk->hw, rate, &unused);
-       else
-               return clk->ops->round_rate(clk->hw, rate, NULL);
+       if (clk->parent)
+               parent_rate = clk->parent->rate;
+
+       return clk->ops->round_rate(clk->hw, rate, &parent_rate);
 }

 /**
@@ -765,9 +765,12 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
 static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
 {
        struct clk *top = clk;
-       unsigned long best_parent_rate = clk->parent->rate;
+       unsigned long best_parent_rate = 0;
        unsigned long new_rate;

+       if (clk->parent)
+               best_parent_rate = clk->parent->rate;
+
        if (!clk->ops->round_rate && !(clk->flags & CLK_SET_RATE_PARENT)) {
                clk->new_rate = clk->rate;
                return NULL;
@@ -780,10 +783,7 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
                goto out;
        }

-       if (clk->flags & CLK_SET_RATE_PARENT)
-               new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
-       else
-               new_rate = clk->ops->round_rate(clk->hw, rate, NULL);
+       new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);

        if (best_parent_rate != clk->parent->rate) {
                top = clk_calc_new_rates(clk->parent, best_parent_rate);

--->8

The reason behind the change is that any clk implements .round_rate will
mostly need to get the parent rate, no matter flag CLK_SET_RATE_PARENT
is set or not.  Instead of expecting every .round_rate implementation
to get the parent rate in the way beloe

	 parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));

we can just pass the parent rate into .round_rate.

> +	int		(*set_parent)(struct clk_hw *hw, u8 index);
> +	u8		(*get_parent)(struct clk_hw *hw);
> +	int		(*set_rate)(struct clk_hw *hw, unsigned long);

For the same reason, I would change .set_rate interface like below.

8<---

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index d5ac6a7..6bd8037 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -119,7 +119,8 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
 }
 EXPORT_SYMBOL_GPL(clk_divider_round_rate);

-static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
+static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long parent_rate)
 {
        struct clk_divider *divider = to_clk_divider(hw);
        unsigned int div;
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index dbc310a..d74ac4b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -833,17 +833,18 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even
 static void clk_change_rate(struct clk *clk)
 {
        struct clk *child;
-       unsigned long old_rate;
+       unsigned long old_rate, parent_rate = 0;
        struct hlist_node *tmp;

        old_rate = clk->rate;
+       if (clk->parent)
+               parent_rate = clk->parent->rate;

        if (clk->ops->set_rate)
-               clk->ops->set_rate(clk->hw, clk->new_rate);
+               clk->ops->set_rate(clk->hw, clk->new_rate, parent_rate);

        if (clk->ops->recalc_rate)
-               clk->rate = clk->ops->recalc_rate(clk->hw,
-                               clk->parent->rate);
+               clk->rate = clk->ops->recalc_rate(clk->hw, parent_rate);
        else
                clk->rate = clk->parent->rate;

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5508897..1031f1f 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -125,7 +125,8 @@ struct clk_ops {
                                        unsigned long *);
        int             (*set_parent)(struct clk_hw *hw, u8 index);
        u8              (*get_parent)(struct clk_hw *hw);
-       int             (*set_rate)(struct clk_hw *hw, unsigned long);
+       int             (*set_rate)(struct clk_hw *hw, unsigned long,
+                                       unsigned long);
        void            (*init)(struct clk_hw *hw);
 };

--->8

Then with parent rate passed into .round_rate and .set_rate like what
we do with .recalc_rate right now, we can save particular clk
implementation from calling __clk_get_parent() and __clk_get_rate to
get parent rate.

For example, the following will the be diff we gain on clk-divider.

8<---

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6bd8037..8a28ffb 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -68,8 +68,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
        if (divider->flags & CLK_DIVIDER_ONE_BASED)
                maxdiv--;

-       if (!best_parent_rate) {
-               parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
+       if (!(divider->flags & CLK_SET_RATE_PARENT)) {
+               parent_rate = *best_parent_rate;
                bestdiv = DIV_ROUND_UP(parent_rate, rate);
                bestdiv = bestdiv == 0 ? 1 : bestdiv;
                bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
@@ -109,13 +109,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
        int div;
        div = clk_divider_bestdiv(hw, rate, prate);

-       if (prate)
-               return *prate / div;
-       else {
-               unsigned long r;
-               r = __clk_get_rate(__clk_get_parent(hw->clk));
-               return r / div;
-       }
+       return *prate / div;
 }
 EXPORT_SYMBOL_GPL(clk_divider_round_rate);

@@ -127,7 +121,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
        unsigned long flags = 0;
        u32 val;

-       div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate;
+       div = parent_rate / rate;

        if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
                div--;

--->8

I always get a sense of worry in using functions named in __xxx which
sounds like something somehow internal.  With the requested interface
change above, I can get all __xxx functions out of my clk_ops
implementation.

> +	void		(*init)(struct clk_hw *hw);
> +};

-- 
Regards,
Shawn


From mporter at ti.com  Tue Mar 20 10:02:13 2012
From: mporter at ti.com (Matt Porter)
Date: Tue, 20 Mar 2012 10:02:13 -0400
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <4F626180.2010902@ti.com>
References: <4F22DEF2.5000807@ti.com> <4F621939.9040906@ti.com>
 <20120315195753.GA2842@n2100.arm.linux.org.uk>
 <201203152041.53754.arnd@arndb.de> <4F626180.2010902@ti.com>
Message-ID: <20120320140213.GG14084@beef>

On Thu, Mar 15, 2012 at 10:39:12PM +0100, Cousson, Benoit wrote:
> On 3/15/2012 9:41 PM, Arnd Bergmann wrote:
> >The numbers definitely need to become local to each of the controllers, but
> >that is the case pretty much automatically using the proposed binding,
> >because each dma request identifier starts with the phandle of the
> >controller.
> 
> Indeed, and in the case of the OMAP SDMA controller, it can handle
> up to 127 DMA request lines numbered from 0 to 126... So a local
> number seems to be a good representation... especially for a number.
> I'm not sure to understand the issue with this binding.
> 
> And AFAIK, there is the only one general purpose DMA controller in
> OMAP so far. The other ones are private to some IPs like MMC or USB,
> so they do not need necessarily need any DT representation.

AM335x has an EDMA controller instead of SDMA. This is the same EDMA
found on mach-davinci/ parts.

-Matt


From khilman at ti.com  Tue Mar 20 10:02:40 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 20 Mar 2012 07:02:40 -0700
Subject: [PATCH v3 1/2] arm: omap3: pm34xx.c: Fix omap3_pm_init() error
 out paths
In-Reply-To: <alpine.DEB.2.00.1203200316300.22974@utopia.booyaka.com> (Paul
 Walmsley's message of "Tue, 20 Mar 2012 03:17:16 -0600 (MDT)")
References: <1332033768-21986-1-git-send-email-mgreer@animalcreek.com>
 <1332033768-21986-2-git-send-email-mgreer@animalcreek.com>
 <1332150525.2116.334.camel@sokoban>
 <alpine.DEB.2.00.1203200316300.22974@utopia.booyaka.com>
Message-ID: <87sjh32wvz.fsf@ti.com>

Paul Walmsley <paul at pwsan.com> writes:

> + Kevin
>
> On Mon, 19 Mar 2012, Tero Kristo wrote:
>
>> On Sat, 2012-03-17 at 18:22 -0700, Mark A. Greer wrote:
>> > From: "Mark A. Greer" <mgreer at animalcreek.com>
>> > 
>> > It appears that the error paths were overlooked when the
>> > omap3_pm_init() routine had the prcm chain handler code
>> > added.  Fix this by adding a goto target and reordering
>> > the error handling code.  Also fix how the irq argument
>> > for free_irq() is determined.
>> 
>> You are right, it looks like the error handling part was accidentally
>> dropped from version 7 of the prcm patch set.
>> 
>> Acked-by: Tero Kristo <t-kristo at ti.com>
>> 
>> Paul, you going to grab this?
>
> Kevin is the pm34xx.c maintainer, so unless he wants me to queue it, it's 
> probably best for him to take it.

Yeah, I've already queued these for v3.4.  (branch: for_3.4/fixes/pm)

Kevin


From florian at openwrt.org  Tue Mar 20 10:06:57 2012
From: florian at openwrt.org (Florian Fainelli)
Date: Tue, 20 Mar 2012 15:06:57 +0100
Subject: [PATCH 1/1] net: phylib: remove the length limitation of mii
 bus id
In-Reply-To: <CAA+hA=Ttc9RDmK1fDPCtqLpf91DYDDFSf3E6zWQ6seyw7sNqTg@mail.gmail.com>
References: <1332217386-3586-1-git-send-email-b29396@freescale.com>
 <CAAQ0ZWQEoPORMXsf3xV-KPP+hOHk2euj460fORyUALnfPn3Q8g@mail.gmail.com>
 <CAA+hA=Ttc9RDmK1fDPCtqLpf91DYDDFSf3E6zWQ6seyw7sNqTg@mail.gmail.com>
Message-ID: <4F688F01.40604@openwrt.org>

Hi,

Le 03/20/12 11:53, Dong Aisheng a ?crit :
> On Tue, Mar 20, 2012 at 1:32 AM, Shawn Guo<shawn.guo at linaro.org>  wrote:
>> On 20 March 2012 12:23, Dong Aisheng<b29396 at freescale.com>  wrote:
>>> From: Dong Aisheng<dong.aisheng at linaro.org>
>>>
>>> When convert to dt, the length of old mii bus id (17 bytes) is not
>>> sufficent to use.
>>> For example, the bus id could be 800f0000.ethernet-1:00 in DT.
>>>
>>> This patch removes the bus id length limitation by changing the
>>> bus id to a const char pionter and user could dynamically set the
>>> bus id via kasprintf function call.
>>>
>>> Since then no users use MII_BUS_ID_SIZE any more, just remove it.
>>>
>>> Signed-off-by: Dong Aisheng<dong.aisheng at linaro.org>
>>> ---
>>> The simplest way may just change MII_BUS_ID_SIZE to a more bigger size,
>>> but i'm not sure that's gonna be accepted.
>>
>> The simplest fix has been applied on -next tree as below.
>>
> Oh, i missed it, seems my patch covers that change.
> But that patch only fixed wrong phy_name buffer length issue.
> My patch is totally remove the length limitation of bus id and phy_name
> or the bus id name will be truncated if it's longer than MII_BUS_ID_SIZE
> which is not a comfortable limitation.

Then just increase the bus id size locally for your driver. Drivers that 
can live with a static allocation are better of using it.

Your patch completely missed testing the return value of kasprintf(), 
and its return value can be NULL, please fix this at least.

>
>> commit a7ed07d51c8abdb407be454c6cb6cfad613759d9
>> Author: Richard Zhao<richard.zhao at linaro.org>
>> Date:   Sun Jan 29 22:08:12 2012 +0000
>>
>>     net: fec: correct phy_name buffer length when init phy_name
>>
>>     Fix the bug that we got wrong phy_name on imx6q sabrelite board.
>>     snprintf used wrong length of phy_name.
>>     phy_name length is MII_BUS_ID_SIZE + 3 rather not MII_BUS_ID_SIZE.
>>     I change it to sizeof(phy_name).
>>
>>     Signed-off-by: Richard Zhao<richard.zhao at linaro.org>
>>     Acked-by: Shawn Guo<shawn.guo at linaro.org>
>>     Acked-by: Florian Fainelli<florian at openwrt.org>
>>     Signed-off-by: David S. Miller<davem at davemloft.net>
>>
>> diff --git a/drivers/net/ethernet/freescale/fec.c
>> b/drivers/net/ethernet/freescale/fec.c
>> index 7b25e9c..1c7aad8 100644
>> --- a/drivers/net/ethernet/freescale/fec.c
>> +++ b/drivers/net/ethernet/freescale/fec.c
>> @@ -990,7 +990,7 @@ static int fec_enet_mii_probe(struct net_device *ndev)
>>                 phy_id = 0;
>>         }
>>
>> -       snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
>> +       snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
>>         phy_dev = phy_connect(ndev, phy_name,&fec_enet_adjust_link, 0,
>>                               fep->phy_interface);
>>         if (IS_ERR(phy_dev)) {
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From grant.likely at secretlab.ca  Tue Mar 20 10:16:54 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 20 Mar 2012 14:16:54 +0000
Subject: [PATCH 2/2] of: selftest/dma: Add selftest for new DT DMA request
 helpers
In-Reply-To: <066e4deaddca8ac368c2c355c3a77daa9e9057cf.1332237596.git.nicolas.ferre@atmel.com>
References: <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <6b5dc1fadfd03a48093338b6981c0a7ae7662212.1332237596.git.nicolas.ferre@atmel.com>
 <066e4deaddca8ac368c2c355c3a77daa9e9057cf.1332237596.git.nicolas.ferre@atmel.com>
Message-ID: <20120320141654.15D943E0A04@localhost>

On Tue, 20 Mar 2012 11:13:32 +0100, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
> Those selftests are covering the new DT DMA helpers. They will test both
> error and normal cases.
> A custom .xlate() function is also provided to show the use of this API in case
> of a different need than the single cell argument.

I'm very happy to see test case code.  Thanks.

However, since we both understand that this series doesn't address my
major concerns, I'm not spending any time reviewing this version.

g.

> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Stephen Warren <swarren at nvidia.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Arnd Bergmann <arnd at arndb.de>
> ---
>  arch/arm/boot/dts/at91sam9m10g45ek.dts     |    2 +
>  arch/arm/boot/dts/testcases/tests-dma.dtsi |   24 +++++++
>  arch/arm/boot/dts/testcases/tests.dtsi     |    1 +
>  drivers/of/selftest.c                      |  100 ++++++++++++++++++++++++++++
>  4 files changed, 127 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/testcases/tests-dma.dtsi
> 
> diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
> index a387e77..18a8f3c 100644
> --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
> +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
> @@ -38,3 +38,5 @@
>  		};
>  	};
>  };
> +
> +/include/ "testcases/tests.dtsi"
> diff --git a/arch/arm/boot/dts/testcases/tests-dma.dtsi b/arch/arm/boot/dts/testcases/tests-dma.dtsi
> new file mode 100644
> index 0000000..5f0ba93
> --- /dev/null
> +++ b/arch/arm/boot/dts/testcases/tests-dma.dtsi
> @@ -0,0 +1,24 @@
> +
> +/ {
> +	testcase-data {
> +		dma-tests {
> +			testdmac0: test-dma-controller0 {
> +				#dma-cells = <1>;
> +			};
> +
> +			testdmac1: test-dma-controller1 {
> +				#dma-cells = <2>;
> +			};
> +
> +			dma-slave-a {
> +				dma-request = <&testdmac0 42>;
> +			};
> +			dma-slave-b {
> +				dma-request = <&testdmac1 24>; /* wrong number of values */
> +			};
> +			dma-slave-c {
> +				dma-request = <&testdmac1 24 25>;
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/testcases/tests.dtsi b/arch/arm/boot/dts/testcases/tests.dtsi
> index a7c5067..e3afb2b 100644
> --- a/arch/arm/boot/dts/testcases/tests.dtsi
> +++ b/arch/arm/boot/dts/testcases/tests.dtsi
> @@ -1 +1,2 @@
>  /include/ "tests-phandle.dtsi"
> +/include/ "tests-dma.dtsi"
> diff --git a/drivers/of/selftest.c b/drivers/of/selftest.c
> index f24ffd7..3281bfd 100644
> --- a/drivers/of/selftest.c
> +++ b/drivers/of/selftest.c
> @@ -9,6 +9,7 @@
>  #include <linux/errno.h>
>  #include <linux/module.h>
>  #include <linux/of.h>
> +#include <linux/of_dma.h>
>  #include <linux/list.h>
>  #include <linux/mutex.h>
>  #include <linux/slab.h>
> @@ -148,6 +149,104 @@ static void __init of_selftest_property_match_string(void)
>  	selftest(rc == -EILSEQ, "unterminated string; rc=%i", rc);
>  }
>  
> +struct two_cells {
> +	int cell1;
> +	int cell2;
> +};
> +
> +static int of_dma_xlate_twonumbercell(struct of_phandle_args *dma_spec, void *cells)
> +{
> +	struct two_cells *tc;
> +
> +	if (!dma_spec)
> +		return -EINVAL;
> +	if (!cells)
> +		return -ENOBUFS;
> +	if (WARN_ON(dma_spec->args_count != 2))
> +		return -EINVAL;
> +
> +	tc = (struct two_cells *)cells;
> +
> +	tc->cell1 = dma_spec->args[0];
> +	tc->cell2 = dma_spec->args[1];
> +	return 0;
> +}
> +
> +static void __init of_selftest_dma(void)
> +{
> +	struct device_node *dma_controller0_np;
> +	struct device_node *dma_controller1_np;
> +	struct device_node *dma_slave_np;
> +	int rc;
> +	int dma_req;
> +	struct two_cells tc;
> +
> +	pr_info("start\n");
> +	dma_controller0_np = of_find_node_by_path("/testcase-data/dma-tests/test-dma-controller0");
> +	dma_slave_np = of_find_node_by_path("/testcase-data/dma-tests/dma-slave-a");
> +	if (!dma_controller0_np || !dma_slave_np) {
> +		pr_err("No testcase data in device tree\n");
> +		return;
> +	}
> +
> +	/* wrong usage: DMA controller not registered yet! */
> +	rc = of_get_dma_request(dma_slave_np, 0, &dma_req);
> +	selftest(rc == -ENODEV, "selftest DMA slave request expected:-ENODEV got:%i\n", rc);
> +
> +	/* test DMA controller registration */
> +	rc = of_dma_controller_register(dma_controller0_np, of_dma_xlate_onenumbercell);
> +	selftest(rc == 0, "selftest DMA controller not found: got:%i\n", rc);
> +
> +	/* wrong usage and error code tests */
> +	rc = of_get_dma_request(dma_slave_np, 1, &dma_req);
> +	selftest(rc == -EINVAL, "selftest DMA slave request expected:-EINVAL got:%i\n", rc);
> +
> +	rc = of_get_dma_request(dma_slave_np, 0, NULL);
> +	selftest(rc == -ENOBUFS, "selftest DMA slave request expected:-ENOBUFS got:%i\n", rc);
> +
> +	/* proper use of the API */
> +	rc = of_get_dma_request(dma_slave_np, 0, &dma_req);
> +	selftest(rc == 0, "selftest DMA slave request error: got:%i\n", rc);
> +	selftest(dma_req == 42, "selftest DMA slave request line expected:42 got:%i\n", dma_req);
> +
> +	of_dma_controller_free(dma_controller0_np);
> +
> +	/* wrong usage: DMA controller not registered anymore! */
> +	rc = of_get_dma_request(dma_slave_np, 0, &dma_req);
> +	selftest(rc == -ENODEV, "selftest DMA slave request expected:-ENODEV got:%i\n", rc);
> +
> +	/* use with a two values DMA request specification */
> +	dma_controller1_np = of_find_node_by_path("/testcase-data/dma-tests/test-dma-controller1");
> +	dma_slave_np = of_find_node_by_path("/testcase-data/dma-tests/dma-slave-b");
> +	if (!dma_controller1_np || !dma_slave_np) {
> +		pr_err("No testcase data in device tree\n");
> +		return;
> +	}
> +
> +	/* DMA controller registration with custom .xlate() function */
> +	rc = of_dma_controller_register(dma_controller1_np, of_dma_xlate_twonumbercell);
> +	selftest(rc == 0, "selftest DMA controller not found: got:%i\n", rc);
> +
> +	/* wrong number of cells */
> +	rc = of_get_dma_request(dma_slave_np, 0, &tc);
> +	selftest(rc == -EINVAL, "selftest DMA slave request expected:-EINVAL got:%i\n", rc);
> +
> +	dma_slave_np = of_find_node_by_path("/testcase-data/dma-tests/dma-slave-c");
> +	if (!dma_slave_np) {
> +		pr_err("No dma-slave-c data in device tree\n");
> +		return;
> +	}
> +
> +	/* proper use of the API */
> +	rc = of_get_dma_request(dma_slave_np, 0, &tc);
> +	selftest(rc == 0, "selftest DMA slave request error: got:%i\n", rc);
> +	selftest(tc.cell1 == 24, "selftest DMA slave request line expected:24 got:%i\n", tc.cell1);
> +	selftest(tc.cell2 == 25, "selftest DMA slave request line expected:25 got:%i\n", tc.cell2);
> +
> +	of_dma_controller_free(dma_controller1_np);
> +	pr_info("end - %s\n", selftest_passed ? "PASS" : "FAIL");
> +}
> +
>  static int __init of_selftest(void)
>  {
>  	struct device_node *np;
> @@ -162,6 +261,7 @@ static int __init of_selftest(void)
>  	pr_info("start of selftest - you will see error messages\n");
>  	of_selftest_parse_phandle_with_args();
>  	of_selftest_property_match_string();
> +	of_selftest_dma();
>  	pr_info("end of selftest - %s\n", selftest_passed ? "PASS" : "FAIL");
>  	return 0;
>  }
> -- 
> 1.7.9
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From shawn.guo at linaro.org  Tue Mar 20 10:18:14 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 20 Mar 2012 22:18:14 +0800
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <20120320094031.GI3852@pengutronix.de>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
Message-ID: <20120320141811.GF32469@S2101-09.ap.freescale.net>

On Tue, Mar 20, 2012 at 10:40:31AM +0100, Sascha Hauer wrote:
...
> I am using these functions and don't need a static array, I just call
> the functions with the desired parameters.
> 
With this patch getting in, you do not have to use them then.  I feel
a static array will be much more readable than a long list of function
calls with a long list of hardcoded arguments to each.

-- 
Regards,
Shawn


From grant.likely at secretlab.ca  Tue Mar 20 10:21:58 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 20 Mar 2012 14:21:58 +0000
Subject: [PATCH 01/11] drivercore: Add driver probe deferral mechanism
In-Reply-To: <4F67BD78.8070202@gmail.com>
References: <1331218291-16119-1-git-send-email-thierry.reding@avionic-design.de>
 <1331218291-16119-2-git-send-email-thierry.reding@avionic-design.de>
 <4F67BD78.8070202@gmail.com>
Message-ID: <20120320142158.CCA213E2834@localhost>

On Tue, 20 Mar 2012 00:12:56 +0100, Sylwester Nawrocki <sylvester.nawrocki at gmail.com> wrote:
> On 03/08/2012 03:51 PM, Thierry Reding wrote:
> > From: Grant Likely<grant.likely at secretlab.ca>
> >
> > Allow drivers to report at probe time that they cannot get all the resources
> > required by the device, and should be retried at a later time.
> >
> > This should completely solve the problem of getting devices
> > initialized in the right order.  Right now this is mostly handled by
> > mucking about with initcall ordering which is a complete hack, and
> > doesn't even remotely handle the case where device drivers are in
> > modules.  This approach completely sidesteps the issues by allowing
> > driver registration to occur in any order, and any driver can request
> > to be retried after a few more other drivers get probed.
> >
> > v4: - Integrate Manjunath's addition of a separate workqueue
> >      - Change -EAGAIN to -EPROBE_DEFER for drivers to trigger deferral
> >      - Update comment blocks to reflect how the code really works
> > v3: - Hold off workqueue scheduling until late_initcall so that the bulk
> >        of driver probes are complete before we start retrying deferred devices.
> >      - Tested with simple use cases.  Still needs more testing though.
> >        Using it to get rid of the gpio early_initcall madness, or to replace
> >        the ASoC internal probe deferral code would be ideal.
> > v2: - added locking so it should no longer be utterly broken in that regard
> >      - remove device from deferred list at device_del time.
> >      - Still completely untested with any real use case, but has been
> >        boot tested.
> >
> > Signed-off-by: Grant Likely<grant.likely at secretlab.ca>
> > [Cc list stripped in order not to get on people's nerves]
> > ---
> >   drivers/base/base.h    |    1 +
> >   drivers/base/core.c    |    2 +
> >   drivers/base/dd.c      |  138 +++++++++++++++++++++++++++++++++++++++++++++++-
> >   include/linux/device.h |    5 ++
> >   include/linux/errno.h  |    1 +
> >   5 files changed, 146 insertions(+), 1 deletion(-)
> 
> Is this patch going to be included in v3.4 ? I can see it's in -next,
> but not sure where I could check if its really queued for v3.4.
> It would be nice to have it in v3.4, I've got already one more client
> of this deferred probe infrastructure.

Greg has sent it on to Linus for merging, so yes.

g.



From grant.likely at secretlab.ca  Tue Mar 20 10:35:44 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 20 Mar 2012 14:35:44 +0000
Subject: [PATCH v4 RESEND 0/7] gpio/omap: Some more driver fixes
In-Reply-To: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <20120320143544.AA6E93E2834@localhost>

On Tue, 20 Mar 2012 16:23:12 +0530, Tarun Kanti DebBarma <tarun.kanti at ti.com> wrote:
> This series excludes the cleanup patches as suggested by Kevin from
> the previously posted series.
> 
> The fixes include correction of _set_gpio_irqenable() implementation,
> missing wakeup_en register update in set_gpio_wakeup(), type mismatch
> of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
> register update in set_gpio_dataout_() and few corrections in context
> save logic.
> 
> It is baselined on top of:
> git://git.secretlab.ca/git/linux-2.6.git gpio/next
> Commit: 81b279d80a63628e580c71a31d30a8c3b3047ad4
> 
> Series is available here for reference:
> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_more_fixes

Merged; thanks

g.

> 
> Power Test:
> Off-mode and Retention on OMAP3430 (Suspend and Idle paths).
> Also confirmed that dataout register content preserved over
> off-mode.
> 
> Functional Test:
> OMAP2430, OMAP3430SDP, ZOOM3, OMAP4430, OMAP4-BLAZE
> 
> v4:
> a) Implemented all comments on v3 which are mostly related to
> avoiding unnecessary register read while updating the context.
> 
> b) Folded:
> gpio/omap: fix dataout register overwrite in _set_gpio_dataout
> into:
> gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg
> 
> v3:
> - Added 4 more additional patches to the previous series
>  which are all bug fixes.
> 
> v2:
> - Added a new patch to update wakeup_en register in _set_gpio_wakeup()
>  in addition to updating bank->context.wake_en.
> 
> - Added a new patch to remove redundant decoding of gpio offset in
>  gpio_get(), _get_gpio_datain() and _get_gpio_dataout().
> 
> - Added a new patch to remove suspend/resume callbacks because the
>  operations performed with the callbacks are redundant.
> 
> Tarun Kanti DebBarma (7):
>   gpio/omap: fix wakeup_en register update in _set_gpio_wakeup()
>   gpio/omap: fix trigger type to unsigned
>   gpio/omap: fix _set_gpio_irqenable implementation
>   gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg
>   gpio/omap: fix incorrect context restore logic in omap_gpio_runtime_*
>   gpio/omap: fix incorrect update to context.irqenable1
>   gpio/omap: fix redundant decoding of gpio offset
> 
>  drivers/gpio/gpio-omap.c |   47 ++++++++++++++++++++++++---------------------
>  1 files changed, 25 insertions(+), 22 deletions(-)
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From linux.melwyn at gmail.com  Tue Mar 20 10:49:02 2012
From: linux.melwyn at gmail.com (melwyn lobo)
Date: Tue, 20 Mar 2012 20:19:02 +0530
Subject: [PATCH] CPUIdle: Reevaluate C-states under CPU load to favor
 deeper C-states
In-Reply-To: <37CAE120BAE10B42A790DD1418C8021D0136C7@DNCE02.ent.ti.com>
References: <1316475315-5905-1-git-send-email-khilman@ti.com>
 <87d3d75zo6.fsf@ti.com> <4EBA6046.2060305@linux.vnet.ibm.com>
 <37CAE120BAE10B42A790DD1418C8021D0136C7@DNCE02.ent.ti.com>
Message-ID: <CAHSGOuuexpCDNoP1G1Gyge2DCep0rsPmUwrVyZFDQ1_tH+Du7Q@mail.gmail.com>

Hey Kevin,
I would like to try out this patch in my platform see the benefits
that you are reporting. But there is one issue in this patch. You have
not initialized "hrtimer_timeout" variable.
This will always be 0 right ?.
Thanks,
-M

On Wed, Nov 9, 2011 at 11:36 PM, Chalhoub, Nicole <n-chalhoub at ti.com> wrote:
> Hi Deepthi,
>
>>
> Texas Instruments France SA, 821 Avenue Jack Kilby, 06270 Villeneuve Loubet. 036 420 040 R.C.S Antibes. Capital de EUR 753.920
>
> -----Original Message-----
>> From: Deepthi Dharwar [mailto:deepthi at linux.vnet.ibm.com]
>> Sent: Wednesday, November 09, 2011 12:13 PM
>> To: Hilman, Kevin
>> Cc: linux-kernel at vger.kernel.org; Arjan van de Ven; linux-arm-
>> kernel at lists.infradead.org; linux-omap at vger.kernel.org; linux-
>> pm at lists.linux-foundation.org; Chalhoub, Nicole
>> Subject: Re: [PATCH] CPUIdle: Reevaluate C-states under CPU load to favor
>> deeper C-states
>
> [...]
>> By setting timers when we enter non-deepest C-state possible, such that
>> when it fires we
>> can re-evaluate and try moving into deeper and deeper C-states enhancing
>> the
>> power savings is a good feature to have.
>>
>> Looking at the current implementation, is it possible to have it as
>> configurable option
>> where one can enable/disable this functionality through the backhand
>> driver ?
>
> The timeout values of the c state timers are set in the backhand driver.
> By setting the timeout to 0 the timers will not fire so you'll not have this functionality enabled
>
>> Also I am thinking, instead of having them in governor
>> wouldnt it be a good idea to have it implemented in
>> the backhand driver itself ?
>> --Deepthi
>
>
> In fact each C-state had its own configurable timer, so it is a parameter characterizing a C-state as it is for the exit_latency and target_residency parameters.
> And we wanted the timer to fire only when we do not go in deep Cstate due to a high load. This decision is made in the CPU idle governor. So the functionality should be seen from the governor..
>
> Thanks and Regards
> Nicole
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at ?http://www.tux.org/lkml/


From nicolas.ferre at atmel.com  Tue Mar 20 10:54:45 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Tue, 20 Mar 2012 15:54:45 +0100
Subject: [PATCH] of: Add generic device tree DMA helpers
In-Reply-To: <20120319144517.C19E93E05A5@localhost>
References: <4F22DEF2.5000807@ti.com>
 <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <20120317094059.7C2333E08E2@localhost> <4F6734DD.3020203@atmel.com>
 <20120319144517.C19E93E05A5@localhost>
Message-ID: <4F689A35.2080305@atmel.com>

On 03/19/2012 03:45 PM, Grant Likely :
> On Mon, 19 Mar 2012 14:30:05 +0100, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
>> On 03/17/2012 10:40 AM, Grant Likely :
>>> On Thu, 15 Mar 2012 09:38:10 +0100, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
>>>> +struct of_dma {
>>>> +	struct list_head of_dma_controllers;
>>>> +	struct device_node *of_node;
>>>> +	int of_dma_n_cells;
>>>> +	int (*of_dma_xlate)(struct of_phandle_args *dma_spec, void *data);
>>>> +};
>>>
>>> This _xlate is nearly useless as a generic API.  It solves the problem for
>>> the specific case where the driver is hard-coded to know which DMA engine
>>> to talk to, but since the returned data doesn't provide any context, it
>>> isn't useful if there are multiple DMA controllers to choose from.
>>
>> You mean, if there is no DMA controller phandle specified in the
>> property?
> 
> No; I'm assuming that dma-channel properties will alwasy have a
> phandle to the dma controller node.
> 
>> I think that it is not the purpose of this API to choose a DMA
>> controller, Nor to provide a channel. The only purpose of this API is to
>> give a HW request to be used by a DMA slave driver. This slave should
>> already have a channel to use and a controller to talk to.
> 
> Then where is the function that finds the reference to the DMA
> controller?  I don't understand why it would be useful to decode that
> separately.
> 
>>> The void *data pointer must be replaced with a typed structure so that
>>> context can be returned.
>>
>> I am not sure to follow you entirely... How do I address the fact that
>> several types of request value can be returned then?
>>
>> BTW, can we imagine a phandle property with a sting as a argument?
>> should it be written this way?
>> dma-request = <&testdmac1>, "slave-rx", "slave-tx";
> 
> No, I'm not suggesting that.  Mixing phandles and strings in a single
> property is possible but ugly.  The phandle-args pattern which uses
> zero or more cells as arguments should be used.
> 
>>
>> If yes, the of_parse_phandle_with_args() is not working on this type...
> 
> Right; of_parse_phandle_with_args() should do the job.
> 
>>
>> (I realize that there seems to be no way out for a generic API: maybe we
>> should move to one or two cases to address and concentrate on them).
> 
> The way I read this patch, the xlate function returns a single
> integer representing the DMA request number, but it doesn't provide
> any data about *which* dma controller is associated with that channel.
> The result of xlate needs to be something like a dma_chan reference
> that identifies both the DMA engine and the channel/request on that
> dma engine.
> 
> [...]
>>>> +/**
>>>> + * of_dma_xlate_onenumbercell() - Generic DMA xlate for direct one cell bindings
>>>> + *
>>>> + * Device Tree DMA translation function which works with one cell bindings
>>>> + * where the cell values map directly to the hardware request number understood
>>>> + * by the DMA controller.
>>>> + */
>>>> +int of_dma_xlate_onenumbercell(struct of_phandle_args *dma_spec, void *dma_req)
>>>> +{
>>>> +	if (!dma_spec)
>>>> +		return -EINVAL;
>>>> +	if (WARN_ON(dma_spec->args_count != 1))
>>>> +		return -EINVAL;
>>>> +	*(int *)dma_req = dma_spec->args[0];
>>>
>>> Following on from comment above; the void *dma_req parameter is dangerous.  How
>>> does this function know that it has been passed an int* pointer?
>>
>> Well, that is a drawback that comes from having to address generic
>> cases.
> 
> Not if you do it right.  If a specific data structure is returned,
> then there can be context attached as to what the data means and which
> dma controller knows how to parse it.
> 
>> But anyway, if the DMA controller decide to register a .xlate()
>> function that returns an integer, the slave driver that will ask a
>> "request line" to this DMA controller will be aware that an integer has
>> to be passed to of_get_dma_request().
> 
> The problem still remains; I don't see how the dma slave can figure
> out *which* dma controller it needs to talk to.

Is not it what the phandle to the dma controller is made for?

Bye,
-- 
Nicolas Ferre


From swarren at wwwdotorg.org  Tue Mar 20 11:27:04 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 20 Mar 2012 09:27:04 -0600
Subject: [PATCH v4 10/10] pwm-backlight: Add rudimentary device tree
 support
In-Reply-To: <20120320083943.GA20249@avionic-0098.adnet.avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-11-git-send-email-thierry.reding@avionic-design.de>
 <4F67F2AF.3020404@wwwdotorg.org>
 <20120320083943.GA20249@avionic-0098.adnet.avionic-design.de>
Message-ID: <4F68A1C8.5080608@wwwdotorg.org>

On 03/20/2012 02:39 AM, Thierry Reding wrote:
> * Stephen Warren wrote:
>> On 03/14/2012 09:56 AM, Thierry Reding wrote:
>>> This commit adds very basic support for device tree probing. Currently,
>>> only a PWM and a list of distinct brightness levels can be specified.
>>> Enabling or disabling backlight power via GPIOs is not yet supported.
>>>
>>> A pointer to the exit() callback is stored in the driver data to keep it
>>> around until the driver is unloaded.
...
>>>  static int pwm_backlight_probe(struct platform_device *pdev)
>> ...
>>> -	pb->pwm = pwm_request(data->pwm_id, "backlight");
>>> -	if (IS_ERR(pb->pwm)) {
>>> -		dev_err(&pdev->dev, "unable to request PWM for backlight\n");
>>> -		ret = PTR_ERR(pb->pwm);
>>> -		goto err_alloc;
>>> -	} else
>>> -		dev_dbg(&pdev->dev, "got pwm for backlight\n");
>>> +	if (!pb->pwm) {
>>> +		pb->pwm = pwm_request(data->pwm_id, "backlight");
>>> +		if (IS_ERR(pb->pwm)) {
>>> +			dev_err(&pdev->dev, "unable to request PWM for backlight\n");
>>> +			ret = PTR_ERR(pb->pwm);
>>> +			goto err_alloc;
>>> +		} else
>>> +			dev_dbg(&pdev->dev, "got pwm for backlight\n");
>>> +	}
>>
>> Hmmm. It'd be more consistent if pwm_backlight_parse_dt() called
>> something like of_pwm_get() instead of of_pwm_request(), so that this
>> code could always call pwm_request() on the PWM and hence operate the
>> same irrespective of DT vs non-DT. GPIOs work that way at least.
> 
> That's actually what the initial patch had. Unfortunately that's pretty much
> the opposite direction of where the PWM framework is headed because it would
> involve getting a global index to request the PWM.

Not necessarily; get() could return a controller+index pair, which could
then be passed to request().

> I think in the long run it
> would be much better to get rid of pwm_request() altogether and unify by
> having the non-DT case request the PWM device on a per-chip basis.

That might also work.


From swarren at wwwdotorg.org  Tue Mar 20 11:27:58 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 20 Mar 2012 09:27:58 -0600
Subject: [PATCH v4 05/10] ARM: tegra: Provide clock for only one PWM
 controller
In-Reply-To: <20120320084403.GB20249@avionic-0098.adnet.avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-6-git-send-email-thierry.reding@avionic-design.de>
 <4F67E8E4.7000604@wwwdotorg.org>
 <20120320084403.GB20249@avionic-0098.adnet.avionic-design.de>
Message-ID: <4F68A1FE.2080906@wwwdotorg.org>

On 03/20/2012 02:44 AM, Thierry Reding wrote:
> * Stephen Warren wrote:
>> On 03/14/2012 09:56 AM, Thierry Reding wrote:
>>> A subsequent patch will add a generic PWM API driver for the Tegra PWFM
>>> controller, supporting all four PWM devices with a single PWM chip. The
>>> device will be named tegra-pwm and only one clock needs to be provided.
>>>
>>> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
>>> Acked-by: Stephen Warren <swarren at nvidia.com>
>> ...
>>> -	CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
>>> -	CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
>>> -	CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
>>> -	CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
>>> +	CLK_DUPLICATE("pwm", "tegra-pwm", NULL),
>>
>> I thought harder about this: Why not delete /all/ the CLK_DUPLICATE()s
>> for PWM, and change the second parameter to PERIPH_CLK for PWM from
>> "pwm" to "tegra-pwm"?
> 
> I think that should work. I'll retest and will update the patch accordingly.
> I assume that you're Acked-by will remain valid after those changes?

Yes in this case, assuming the patch looks like what I think it will:-)


From swarren at wwwdotorg.org  Tue Mar 20 11:33:01 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 20 Mar 2012 09:33:01 -0600
Subject: [PATCH v4 07/10] pwm: tegra: Add device tree support
In-Reply-To: <20120320084807.GC20249@avionic-0098.adnet.avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-8-git-send-email-thierry.reding@avionic-design.de>
 <4F67EE9A.6080101@wwwdotorg.org>
 <20120320084807.GC20249@avionic-0098.adnet.avionic-design.de>
Message-ID: <4F68A32D.1000402@wwwdotorg.org>

On 03/20/2012 02:48 AM, Thierry Reding wrote:
> * Stephen Warren wrote:
>> On 03/14/2012 09:56 AM, Thierry Reding wrote:
>>> Add auxdata to instantiate the PWFM controller from a device tree,
>>> include the corresponding nodes in the dtsi files for Tegra 20 and
>>> Tegra 30 and add binding documentation.
>>>
>>> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
>>
>>> +++ b/Documentation/devicetree/bindings/pwm/tegra-pwm.txt
>>
>> Can this please be named nvidia,tegra20-pwm.txt so that if we need
>> different bindings for any future Tegra PWM, we won't have any filename
>> conflicts?
> 
> That file already documents the bindings for Tegra 20 and Tegra 30, that's
> why I chose the move generic name. Could this perhaps be documented within
> the file instead? Or should I rather add a nvidia,tegra30-pwm.txt with a
> reference to the nvidia,tegra20-pwm.txt?

I think it's fine for a file of name nvidia,tegra20-pwm.txt to document
both Tegra20 and Tegra30; the file is named after the first/earliest
compatible value it documents. The issue is more that /if/ say TegraNN
needs a different binding, I want the naming consistent (e.g.
nvidia,tegraNN-pwm.txt) rather than having the old file with one style
and the new file named using a different style.


From swarren at wwwdotorg.org  Tue Mar 20 11:38:55 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 20 Mar 2012 09:38:55 -0600
Subject: [PATCH v2 1/2] of: Add generic device tree DMA helpers
In-Reply-To: <6b5dc1fadfd03a48093338b6981c0a7ae7662212.1332237596.git.nicolas.ferre@atmel.com>
References: <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <6b5dc1fadfd03a48093338b6981c0a7ae7662212.1332237596.git.nicolas.ferre@atmel.com>
Message-ID: <4F68A48F.2000803@wwwdotorg.org>

On 03/20/2012 04:13 AM, Nicolas Ferre wrote:
> Add some basic helpers to retrieve a DMA controller device_node and the
> DMA request specifications. By making DMA controllers register a generic
> translation function, we allow the management of any type of DMA requests
> specification.
> The void * output of an of_dma_xlate() function that will be implemented
> by the DMA controller can carry any type of "dma-request" argument.
> 
> The DMA client will search its associated DMA controller in the list and
> call the registered of_dam_xlate() function to retrieve the request values.
> 
> One simple xlate function is provided for the "single number" type of
> request binding.
> 
> This implementation is independent from dmaengine so it can also be used
> by legacy drivers.

> +++ b/Documentation/devicetree/bindings/dma/dma.txt

> +* DMA client
> +
> +Client drivers should specify the DMA request property using a phandle to
> +the controller. If needed, the DMA request identity on that controller is then
> +added followed by optional request specifications.
> +
> +Required property:
> +    - dma-request: List of phandle + dma-request + request specifications,
> +      one group per request "line".

Should the property name be plural, i.e. "dma-requests"? For PWM I
believe we settled on "pwms" not "pwm", and that was for consistency
with other bindings like interrupts and GPIOs.


From thierry.reding at avionic-design.de  Tue Mar 20 11:43:30 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 20 Mar 2012 16:43:30 +0100
Subject: [PATCH v4 10/10] pwm-backlight: Add rudimentary device tree
 support
In-Reply-To: <4F68A1C8.5080608@wwwdotorg.org>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-11-git-send-email-thierry.reding@avionic-design.de>
 <4F67F2AF.3020404@wwwdotorg.org>
 <20120320083943.GA20249@avionic-0098.adnet.avionic-design.de>
 <4F68A1C8.5080608@wwwdotorg.org>
Message-ID: <20120320154330.GA8651@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> On 03/20/2012 02:39 AM, Thierry Reding wrote:
> > * Stephen Warren wrote:
> >> On 03/14/2012 09:56 AM, Thierry Reding wrote:
> >>> This commit adds very basic support for device tree probing. Currently,
> >>> only a PWM and a list of distinct brightness levels can be specified.
> >>> Enabling or disabling backlight power via GPIOs is not yet supported.
> >>>
> >>> A pointer to the exit() callback is stored in the driver data to keep it
> >>> around until the driver is unloaded.
> ...
> >>>  static int pwm_backlight_probe(struct platform_device *pdev)
> >> ...
> >>> -	pb->pwm = pwm_request(data->pwm_id, "backlight");
> >>> -	if (IS_ERR(pb->pwm)) {
> >>> -		dev_err(&pdev->dev, "unable to request PWM for backlight\n");
> >>> -		ret = PTR_ERR(pb->pwm);
> >>> -		goto err_alloc;
> >>> -	} else
> >>> -		dev_dbg(&pdev->dev, "got pwm for backlight\n");
> >>> +	if (!pb->pwm) {
> >>> +		pb->pwm = pwm_request(data->pwm_id, "backlight");
> >>> +		if (IS_ERR(pb->pwm)) {
> >>> +			dev_err(&pdev->dev, "unable to request PWM for backlight\n");
> >>> +			ret = PTR_ERR(pb->pwm);
> >>> +			goto err_alloc;
> >>> +		} else
> >>> +			dev_dbg(&pdev->dev, "got pwm for backlight\n");
> >>> +	}
> >>
> >> Hmmm. It'd be more consistent if pwm_backlight_parse_dt() called
> >> something like of_pwm_get() instead of of_pwm_request(), so that this
> >> code could always call pwm_request() on the PWM and hence operate the
> >> same irrespective of DT vs non-DT. GPIOs work that way at least.
> > 
> > That's actually what the initial patch had. Unfortunately that's pretty much
> > the opposite direction of where the PWM framework is headed because it would
> > involve getting a global index to request the PWM.
> 
> Not necessarily; get() could return a controller+index pair, which could
> then be passed to request().

This is pretty much what of_pwm_request() does internally (actually via the
of_xlate() function), and it goes one step further by requesting the
corresponding PWM.

I don't really like the fact that the DT parsing code needs to store a
requested PWM device in the platform data. The only other solution would be,
as you suggest, to obtain two indices and request based on them. However that
comes with a whole lot of problems of its own (race between getting the
controller index and the actual requesting of the PWM device, ...).

One other alternative could be to not pass the PWM device via platform data
but rather return it from the pwm_backlight_parse_dt() function (either via
the return value or an output parameter).

> > I think in the long run it
> > would be much better to get rid of pwm_request() altogether and unify by
> > having the non-DT case request the PWM device on a per-chip basis.
> 
> That might also work.

What I'm not sure about is how to represent this in the non-DT case. The
problem would be how to identify the individual PWM chips. From a quick
glance, pinctrl seems to do this purely on a name lookup basis, similar to
the clock framework.

What would be a good way to represent this in platform data?

Thierry
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From thierry.reding at avionic-design.de  Tue Mar 20 11:44:52 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Tue, 20 Mar 2012 16:44:52 +0100
Subject: [PATCH v4 07/10] pwm: tegra: Add device tree support
In-Reply-To: <4F68A32D.1000402@wwwdotorg.org>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-8-git-send-email-thierry.reding@avionic-design.de>
 <4F67EE9A.6080101@wwwdotorg.org>
 <20120320084807.GC20249@avionic-0098.adnet.avionic-design.de>
 <4F68A32D.1000402@wwwdotorg.org>
Message-ID: <20120320154452.GB8651@avionic-0098.mockup.avionic-design.de>

* Stephen Warren wrote:
> On 03/20/2012 02:48 AM, Thierry Reding wrote:
> > * Stephen Warren wrote:
> >> On 03/14/2012 09:56 AM, Thierry Reding wrote:
> >>> Add auxdata to instantiate the PWFM controller from a device tree,
> >>> include the corresponding nodes in the dtsi files for Tegra 20 and
> >>> Tegra 30 and add binding documentation.
> >>>
> >>> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> >>
> >>> +++ b/Documentation/devicetree/bindings/pwm/tegra-pwm.txt
> >>
> >> Can this please be named nvidia,tegra20-pwm.txt so that if we need
> >> different bindings for any future Tegra PWM, we won't have any filename
> >> conflicts?
> > 
> > That file already documents the bindings for Tegra 20 and Tegra 30, that's
> > why I chose the move generic name. Could this perhaps be documented within
> > the file instead? Or should I rather add a nvidia,tegra30-pwm.txt with a
> > reference to the nvidia,tegra20-pwm.txt?
> 
> I think it's fine for a file of name nvidia,tegra20-pwm.txt to document
> both Tegra20 and Tegra30; the file is named after the first/earliest
> compatible value it documents. The issue is more that /if/ say TegraNN
> needs a different binding, I want the naming consistent (e.g.
> nvidia,tegraNN-pwm.txt) rather than having the old file with one style
> and the new file named using a different style.

Understood. I'll rename it for the next version.

Thierry
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From swarren at wwwdotorg.org  Tue Mar 20 11:56:09 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Tue, 20 Mar 2012 09:56:09 -0600
Subject: [PATCH v4 10/10] pwm-backlight: Add rudimentary device tree
 support
In-Reply-To: <20120320154330.GA8651@avionic-0098.mockup.avionic-design.de>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-11-git-send-email-thierry.reding@avionic-design.de>
 <4F67F2AF.3020404@wwwdotorg.org>
 <20120320083943.GA20249@avionic-0098.adnet.avionic-design.de>
 <4F68A1C8.5080608@wwwdotorg.org>
 <20120320154330.GA8651@avionic-0098.mockup.avionic-design.de>
Message-ID: <4F68A899.3030009@wwwdotorg.org>

On 03/20/2012 09:43 AM, Thierry Reding wrote:
> * Stephen Warren wrote:
>> On 03/20/2012 02:39 AM, Thierry Reding wrote:
...
>>> I think in the long run it
>>> would be much better to get rid of pwm_request() altogether and unify by
>>> having the non-DT case request the PWM device on a per-chip basis.
>>
>> That might also work.
> 
> What I'm not sure about is how to represent this in the non-DT case. The
> problem would be how to identify the individual PWM chips. From a quick
> glance, pinctrl seems to do this purely on a name lookup basis, similar to
> the clock framework.
> 
> What would be a good way to represent this in platform data?

I think most get subsystems have a get API that works for both DT and
non-DT, rather than using platform data:

# works in DT right now IIRC:
regulator_get(dev, supply_name)

# patches posted to make this work in DT. Near checkin:
p = pinctrl_get(dev); s = pinctrl_lookup_state(p, state_name)

# patches posted to make this work in DT. I'm not sure how
# near they are to check-in.
clk_get(dev, clk_name)

That way, there could be a pwm_get(dev, name) for both non-DT (use some
table registered by board files) and DT (use the OF lookup code you've
written).

Admittedly, GPIOs don't work quite this way. Interrupts kinda do via the
platform resources.

For board files, this would rely on some table which mapped from the get
parameters to the returned object. IIRC, most of these tables are
indexed by (dev_name(dev), name) and probably return the dev_name() of
the providing device (or whatever internally makes sense to identify the
device) plus some subsystem-specific data (e.g. PWM index).


From broonie at opensource.wolfsonmicro.com  Tue Mar 20 12:08:36 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 20 Mar 2012 16:08:36 +0000
Subject: [PATCH v4 10/10] pwm-backlight: Add rudimentary device tree
 support
In-Reply-To: <4F68A899.3030009@wwwdotorg.org>
References: <1331740593-10807-1-git-send-email-thierry.reding@avionic-design.de>
 <1331740593-10807-11-git-send-email-thierry.reding@avionic-design.de>
 <4F67F2AF.3020404@wwwdotorg.org>
 <20120320083943.GA20249@avionic-0098.adnet.avionic-design.de>
 <4F68A1C8.5080608@wwwdotorg.org>
 <20120320154330.GA8651@avionic-0098.mockup.avionic-design.de>
 <4F68A899.3030009@wwwdotorg.org>
Message-ID: <20120320160832.GL3445@opensource.wolfsonmicro.com>

On Tue, Mar 20, 2012 at 09:56:09AM -0600, Stephen Warren wrote:
> On 03/20/2012 09:43 AM, Thierry Reding wrote:

> > What would be a good way to represent this in platform data?

> I think most get subsystems have a get API that works for both DT and
> non-DT, rather than using platform data:

Yes, please - having to have explict handling in drivers to select a
mechanism to look up stuff in the subsystem would be very sad.

> # works in DT right now IIRC:
> regulator_get(dev, supply_name)

Yes, that's totally transparent to the device.

> For board files, this would rely on some table which mapped from the get
> parameters to the returned object. IIRC, most of these tables are
> indexed by (dev_name(dev), name) and probably return the dev_name() of
> the providing device (or whatever internally makes sense to identify the
> device) plus some subsystem-specific data (e.g. PWM index).

That's how regulator and clk do it (I think pinctrl too, and IIO also
does this though it's in staging) - the consumer works with the struct
device and the name of the thing it's requesting and the things doing
the mapping (boards, SoCs, whatever) map this onto the actual device
with a lookup table which works in terms of dev_name() for the
requesting device.  We use dev_name() because many buses don't make a
struct device available until very late in system startup.
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From arnd at arndb.de  Tue Mar 20 09:01:49 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 20 Mar 2012 13:01:49 +0000
Subject: [PATCH] USB: gadget driver for LPC32xx
In-Reply-To: <4F67B28D.3060500@antcom.de>
References: <1332191930-2433-1-git-send-email-stigge@antcom.de>
 <201203192130.13583.arnd@arndb.de> <4F67B28D.3060500@antcom.de>
Message-ID: <201203201301.50159.arnd@arndb.de>

On Monday 19 March 2012, Roland Stigge wrote:
> Hi Arnd,
> 
> On 19/03/12 22:30, Arnd Bergmann wrote:
> > There is already a driver for the isp1301 otg part in the kernel, I don't
> > think we want to add another one.
> > 
> > From what I can tell, this shares a common ancestry with the omap version
> > but has diverged quite a bit. The best solution would really be to
> > bring the two back together and let them share a common base driver,
> > with the lpc32xx and omap specific bits in another file.
> 
> Yes, it's a good idea to share code where possible and consolidate into
> one driver.
> 
> Please consider:
> 
> The LPC32xx driver is actually using only 3 functions via isp1301:
> 
> isp1301_udc_configure()
> isp1301_set_powerstate()
> isp1301_pullup_set()
> 
> The first of those is LPC32xx specific. The power setting function is
> also done differently in isp1301_omap's power_up()/power_down() ("board
> specific"). For the pullups, there is not (yet?) a dedicated API in the
> OMAP driver, but it's really only two small I2C commands.
> 
> Are you still sure it's worth it to use a common driver when there is
> hardly shared code?

No, I guess I should have looked closed. I found a few common functions
and assumed that this would be the same driver.

> Maybe the right thing is a common low-level isp1301 interface defining
> all the registers and providing low-level (I2C) access functions,
> leaving all the "higher level"/"board specific" functions up to the
> existing drivers?
> 
> (I guess you meant drivers/usb/otg/isp1301_omap.c ?)

Yes, that sounds like a very good idea. Can you describe which part of
the function isp1301 does? It's not clear how the layering between
that and the platform driver should end up.

	Arnd


From arnd at arndb.de  Tue Mar 20 09:03:10 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 20 Mar 2012 13:03:10 +0000
Subject: [PATCH v2 1/2] of: Add generic device tree DMA helpers
In-Reply-To: <6b5dc1fadfd03a48093338b6981c0a7ae7662212.1332237596.git.nicolas.ferre@atmel.com>
References: <1331800690-21518-1-git-send-email-nicolas.ferre@atmel.com>
 <6b5dc1fadfd03a48093338b6981c0a7ae7662212.1332237596.git.nicolas.ferre@atmel.com>
Message-ID: <201203201303.11175.arnd@arndb.de>

On Tuesday 20 March 2012, Nicolas Ferre wrote:
> 
> Add some basic helpers to retrieve a DMA controller device_node and the
> DMA request specifications. By making DMA controllers register a generic
> translation function, we allow the management of any type of DMA requests
> specification.
> The void * output of an of_dma_xlate() function that will be implemented
> by the DMA controller can carry any type of "dma-request" argument.
> 
> The DMA client will search its associated DMA controller in the list and
> call the registered of_dam_xlate() function to retrieve the request values.
> 
> One simple xlate function is provided for the "single number" type of
> request binding.
> 
> This implementation is independent from dmaengine so it can also be used
> by legacy drivers.

Thanks a lot of posting this updated version, I think it will be very
useful as we proceed. I still hope that in the end we find that the
differences are not all that big and we can do it all with bindings
very much like what you have here.

	Arnd


From consul.kautuk at gmail.com  Tue Mar 20 12:30:57 2012
From: consul.kautuk at gmail.com (Kautuk Consul)
Date: Tue, 20 Mar 2012 12:30:57 -0400
Subject: [PATCH 1/1] arm: fault.c: correct how the tsk->[maj|min]_flt gets
 incremented
Message-ID: <1332261057-2399-1-git-send-email-consul.kautuk@gmail.com>

commit 8878a539ff19a43cf3729e7562cd528f490246ae was done by me
to make the page fault handler retryable as well as interruptible.

Due to this commit, there is a mistake in the way in which
tsk->[maj|min]_flt counter gets incremented for VM_FAULT_ERROR:
If VM_FAULT_ERROR is returned in the fault flags by handle_mm_fault,
then either maj_flt or min_flt will get incremented. This is wrong
as in the case of a VM_FAULT_ERROR we need to be skip ahead to the
error handling code in do_page_fault.

Added a check after the call to __do_page_fault() to check for
(fault & VM_FAULT_ERROR).

Signed-off-by: Kautuk Consul <consul.kautuk at gmail.com>
---
 arch/arm/mm/fault.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index bb7eac3..ec8c88b 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -318,7 +318,7 @@ retry:
 	 */
 
 	perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
-	if (flags & FAULT_FLAG_ALLOW_RETRY) {
+	if (!(fault & VM_FAULT_ERROR) && (flags & FAULT_FLAG_ALLOW_RETRY)) {
 		if (fault & VM_FAULT_MAJOR) {
 			tsk->maj_flt++;
 			perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
-- 
1.7.5.4



From tony at atomide.com  Tue Mar 20 12:51:10 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 20 Mar 2012 09:51:10 -0700
Subject: [PATCH v2 0/4] ARM: OMAP: boards: changes to support dynamic
 irq alloc
In-Reply-To: <CAC83ZvLf=fkuvf6VN1gwauFirO2cQsNib3ANWnJrujWGNYS24Q@mail.gmail.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
 <20120319191743.GB9859@atomide.com> <4F67B9F9.1030906@ti.com>
 <20120319233910.GF9859@atomide.com> <4F68471A.4010502@ti.com>
 <CAC83ZvLf=fkuvf6VN1gwauFirO2cQsNib3ANWnJrujWGNYS24Q@mail.gmail.com>
Message-ID: <20120320165109.GG9859@atomide.com>

* DebBarma, Tarun Kanti <tarun.kanti at ti.com> [120320 04:02]:
> On Tue, Mar 20, 2012 at 2:30 PM, Cousson, Benoit <b-cousson at ti.com> wrote:
> > On 3/20/2012 12:39 AM, Tony Lindgren wrote:
> >>
> >> Yes I understand. But still, which patch(s) cause the issue
> >> so we can put that in the changelog for the fixes?
> >
> > OK, here they are:
> > 25db711 gpio/omap: Fix IRQ handling for SPARSE_IRQ
> > 384ebe1 gpio/omap: Add DT support to GPIO driver

Thanks, I'll update the comments for the first two patches
for this and apply them.

If I get an ack from Dmitry for patch 3/4, I'll apply them too.

Regards,

Tony


From tony at atomide.com  Tue Mar 20 12:52:46 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 20 Mar 2012 09:52:46 -0700
Subject: [PATCH v2 3/4] drivers: input: Fix OMAP_GPIO_IRQ with
 gpio_to_irq() in ams_delta_serio_exit()
In-Reply-To: <1332158817-26311-4-git-send-email-tarun.kanti@ti.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
 <1332158817-26311-4-git-send-email-tarun.kanti@ti.com>
Message-ID: <20120320165246.GH9859@atomide.com>

Hi Dmitry,

* Tarun Kanti DebBarma <tarun.kanti at ti.com> [120319 05:09]:
> Even though ams-delta-serio input driver uses gpio_to_irq() in all
> relevent places to get irq number, the ams_delta_serio_exit() still
> uses OMAP_GPIO_IRQ macro. Fix this.
> 
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>

Care to ack this one? I'd like to apply all four as fixes
at the end of the merge window so we can drop the old and
now broken OMAP_GPIO_IRQ macro.

Regards,

Tony

> ---
>  drivers/input/serio/ams_delta_serio.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/input/serio/ams_delta_serio.c b/drivers/input/serio/ams_delta_serio.c
> index d4d08bd..dbe1ae8 100644
> --- a/drivers/input/serio/ams_delta_serio.c
> +++ b/drivers/input/serio/ams_delta_serio.c
> @@ -170,7 +170,7 @@ module_init(ams_delta_serio_init);
>  static void __exit ams_delta_serio_exit(void)
>  {
>  	serio_unregister_port(ams_delta_serio);
> -	free_irq(OMAP_GPIO_IRQ(AMS_DELTA_GPIO_PIN_KEYBRD_CLK), 0);
> +	free_irq(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK), 0);
>  	gpio_free(AMS_DELTA_GPIO_PIN_KEYBRD_CLK);
>  	gpio_free(AMS_DELTA_GPIO_PIN_KEYBRD_DATA);
>  }
> -- 
> 1.7.0.4
> 


From jonsmirl at gmail.com  Tue Mar 20 12:52:58 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Tue, 20 Mar 2012 12:52:58 -0400
Subject: Device tree and IO map_desc.
Message-ID: <CAKON4OyHRVvdtZGt+HiCnsRT_5zTuDVBVgOx22kFC2xxFLnD+Q@mail.gmail.com>

Is there a helper for building the IO map_desc from the device tree?

For example on Versatile. All of this map_io data is already in the
device tree, it is just repeated here.


DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
	.map_io		= versatile_map_io,
	.init_early	= versatile_init_early,
....
MACHINE_END

void __init versatile_map_io(void)
{
	iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
}

static struct map_desc versatile_io_desc[] __initdata = {
	{
		.virtual	=  IO_ADDRESS(VERSATILE_SYS_BASE),
		.pfn		= __phys_to_pfn(VERSATILE_SYS_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	=  IO_ADDRESS(VERSATILE_SIC_BASE),
		.pfn		= __phys_to_pfn(VERSATILE_SIC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	=  IO_ADDRESS(VERSATILE_VIC_BASE),
		.pfn		= __phys_to_pfn(VERSATILE_VIC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
...

-- 
Jon Smirl
jonsmirl at gmail.com


From dmitry.torokhov at gmail.com  Tue Mar 20 13:36:41 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Tue, 20 Mar 2012 10:36:41 -0700
Subject: [PATCH v2 3/4] drivers: input: Fix OMAP_GPIO_IRQ with
 gpio_to_irq() in ams_delta_serio_exit()
In-Reply-To: <20120320165246.GH9859@atomide.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
 <1332158817-26311-4-git-send-email-tarun.kanti@ti.com>
 <20120320165246.GH9859@atomide.com>
Message-ID: <20120320173641.GA6464@core.coreip.homeip.net>

On Tue, Mar 20, 2012 at 09:52:46AM -0700, Tony Lindgren wrote:
> Hi Dmitry,
> 
> * Tarun Kanti DebBarma <tarun.kanti at ti.com> [120319 05:09]:
> > Even though ams-delta-serio input driver uses gpio_to_irq() in all
> > relevent places to get irq number, the ams_delta_serio_exit() still
> > uses OMAP_GPIO_IRQ macro. Fix this.
> > 
> > Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> 
> Care to ack this one? I'd like to apply all four as fixes
> at the end of the merge window so we can drop the old and
> now broken OMAP_GPIO_IRQ macro.

Sure.

Acked-by: Dmitry Torokhov <dtor at mail.ru>

Thanks.

-- 
Dmitry


From skannan at codeaurora.org  Tue Mar 20 13:46:11 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 20 Mar 2012 10:46:11 -0700 (PDT)
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <20120320140220.GE32469@S2101-09.ap.freescale.net>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
Message-ID: <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>


On Tue, March 20, 2012 7:02 am, Shawn Guo wrote:
> On Thu, Mar 15, 2012 at 11:11:19PM -0700, Mike Turquette wrote:
> ...
>> +struct clk_ops {
>> +	int		(*prepare)(struct clk_hw *hw);
>> +	void		(*unprepare)(struct clk_hw *hw);
>> +	int		(*enable)(struct clk_hw *hw);
>> +	void		(*disable)(struct clk_hw *hw);
>> +	int		(*is_enabled)(struct clk_hw *hw);
>> +	unsigned long	(*recalc_rate)(struct clk_hw *hw,
>> +					unsigned long parent_rate);
>
> I believe I have heard people love the interface with parent_rate
> passed in.  I love that too.  But I would like to ask the same thing
> on .round_rate and .set_rate as well for the same reason why we have
> it for .recalc_rate.

In my case, for most clocks, set rate involves reparenting. So, what does
passing parent_rate for these even mean? Passing parent_rate seems more
apt for recalc_rate since it's called when the parent rate changes -- so,
the actual parent itself is not expected to change.

I could ignore the parameter, but just wondering how many of the others
see value in this. And if we do add this parameter, it shouldn't be made
mandatory for the platform driver to use it (due to other assumptions the
clock framework might make).

-Saravana


-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.




From khilman at ti.com  Tue Mar 20 13:46:57 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 20 Mar 2012 10:46:57 -0700
Subject: [PATCH v4 RESEND 0/7] gpio/omap: Some more driver fixes
In-Reply-To: <20120320143544.AA6E93E2834@localhost> (Grant Likely's message of
 "Tue, 20 Mar 2012 14:35:44 +0000")
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
 <20120320143544.AA6E93E2834@localhost>
Message-ID: <87haxj17xq.fsf@ti.com>

Hi Grant,

Grant Likely <grant.likely at secretlab.ca> writes:

> On Tue, 20 Mar 2012 16:23:12 +0530, Tarun Kanti DebBarma <tarun.kanti at ti.com> wrote:
>> This series excludes the cleanup patches as suggested by Kevin from
>> the previously posted series.
>> 
>> The fixes include correction of _set_gpio_irqenable() implementation,
>> missing wakeup_en register update in set_gpio_wakeup(), type mismatch
>> of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
>> register update in set_gpio_dataout_() and few corrections in context
>> save logic.
>> 
>> It is baselined on top of:
>> git://git.secretlab.ca/git/linux-2.6.git gpio/next
>> Commit: 81b279d80a63628e580c71a31d30a8c3b3047ad4
>> 
>> Series is available here for reference:
>> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_more_fixes
>
> Merged; thanks

Can you hold off slightly before merging this.

I haven't been through v4 yet or tested the fixes alone now that they're
separated from the other cleanups.

Expect a pull request from me when ready.

Thanks,

Kevin


From khilman at ti.com  Tue Mar 20 13:49:45 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 20 Mar 2012 10:49:45 -0700
Subject: [PATCH] CPUIdle: Reevaluate C-states under CPU load to favor
 deeper C-states
In-Reply-To: <CAHSGOuuexpCDNoP1G1Gyge2DCep0rsPmUwrVyZFDQ1_tH+Du7Q@mail.gmail.com>
 (melwyn lobo's message of "Tue, 20 Mar 2012 20:19:02 +0530")
References: <1316475315-5905-1-git-send-email-khilman@ti.com>
 <87d3d75zo6.fsf@ti.com> <4EBA6046.2060305@linux.vnet.ibm.com>
 <37CAE120BAE10B42A790DD1418C8021D0136C7@DNCE02.ent.ti.com>
 <CAHSGOuuexpCDNoP1G1Gyge2DCep0rsPmUwrVyZFDQ1_tH+Du7Q@mail.gmail.com>
Message-ID: <878viv17t2.fsf@ti.com>

melwyn lobo <linux.melwyn at gmail.com> writes:

> Hey Kevin,
> I would like to try out this patch in my platform see the benefits
> that you are reporting. But there is one issue in this patch. You have
> not initialized "hrtimer_timeout" variable.
> This will always be 0 right ?.

Correct.

The generic code defaults to zero so that the default behavior with this
patch is unchanged from previous behavior.  In order to use this
feature, your platform-specific code which creates your C-states sets
the per-C-state timer values.

Kevin

> Thanks,
> -M
>
> On Wed, Nov 9, 2011 at 11:36 PM, Chalhoub, Nicole <n-chalhoub at ti.com> wrote:
>> Hi Deepthi,
>>
>>>
>> Texas Instruments France SA, 821 Avenue Jack Kilby, 06270 Villeneuve Loubet. 036 420 040 R.C.S Antibes. Capital de EUR 753.920
>>
>> -----Original Message-----
>>> From: Deepthi Dharwar [mailto:deepthi at linux.vnet.ibm.com]
>>> Sent: Wednesday, November 09, 2011 12:13 PM
>>> To: Hilman, Kevin
>>> Cc: linux-kernel at vger.kernel.org; Arjan van de Ven; linux-arm-
>>> kernel at lists.infradead.org; linux-omap at vger.kernel.org; linux-
>>> pm at lists.linux-foundation.org; Chalhoub, Nicole
>>> Subject: Re: [PATCH] CPUIdle: Reevaluate C-states under CPU load to favor
>>> deeper C-states
>>
>> [...]
>>> By setting timers when we enter non-deepest C-state possible, such that
>>> when it fires we
>>> can re-evaluate and try moving into deeper and deeper C-states enhancing
>>> the
>>> power savings is a good feature to have.
>>>
>>> Looking at the current implementation, is it possible to have it as
>>> configurable option
>>> where one can enable/disable this functionality through the backhand
>>> driver ?
>>
>> The timeout values of the c state timers are set in the backhand driver.
>> By setting the timeout to 0 the timers will not fire so you'll not have this functionality enabled
>>
>>> Also I am thinking, instead of having them in governor
>>> wouldnt it be a good idea to have it implemented in
>>> the backhand driver itself ?
>>> --Deepthi
>>
>>
>> In fact each C-state had its own configurable timer, so it is a parameter characterizing a C-state as it is for the exit_latency and target_residency parameters.
>> And we wanted the timer to fire only when we do not go in deep Cstate due to a high load. This decision is made in the CPU idle governor. So the functionality should be seen from the governor..
>>
>> Thanks and Regards
>> Nicole
>>
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>> Please read the FAQ at ?http://www.tux.org/lkml/
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From khilman at ti.com  Tue Mar 20 14:01:00 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 20 Mar 2012 11:01:00 -0700
Subject: [PATCH v4 RESEND 6/7] gpio/omap: fix incorrect update to
 context.irqenable1
In-Reply-To: <1332240799-6748-7-git-send-email-tarun.kanti@ti.com> (Tarun
 Kanti DebBarma's message of "Tue, 20 Mar 2012 16:23:18 +0530")
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
 <1332240799-6748-7-git-send-email-tarun.kanti@ti.com>
Message-ID: <87zkbbywwz.fsf@ti.com>

Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:

> In _enable_gpio_irqbank() when bank->regs->set_irqenable is valid,
> gpio_mask can be directly set by writing to set_irqenable register
> without overwriting current value. In order to ensure the same is
> stored in context.irqenable1, we must read from regs->irqenable
> instead of overwriting it with gpio_mask.

> The overwriting makes sense only in the second case where irqenable
> is explicitly read and updated with new gpio_mask before writing it
> back. However, for consistency reading regs->irqenable into the
> bank->context.irqenable1 takes care of both the scenarios.

...except that the code doesn't do this anymore.

I like the newer version (I hope so, since I suggested it :), but please
update the changlog to describe what the code is actually doing.

Thanks,

Kevin


From s.hauer at pengutronix.de  Tue Mar 20 14:10:50 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 20 Mar 2012 19:10:50 +0100
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <20120320141811.GF32469@S2101-09.ap.freescale.net>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <20120320141811.GF32469@S2101-09.ap.freescale.net>
Message-ID: <20120320181050.GN3852@pengutronix.de>

On Tue, Mar 20, 2012 at 10:18:14PM +0800, Shawn Guo wrote:
> On Tue, Mar 20, 2012 at 10:40:31AM +0100, Sascha Hauer wrote:
> ...
> > I am using these functions and don't need a static array, I just call
> > the functions with the desired parameters.
> > 
> With this patch getting in, you do not have to use them then.  I feel
> a static array will be much more readable than a long list of function
> calls with a long list of hardcoded arguments to each.

I'm also not a fan of long argument lists; a divider like defined in my
tree takes 5 arguments, a gate 4 and a mux 6. While 6 is already at the
border I think it's still acceptable.

What I like in terms of readability is one line per clock which makes
for quite short clock files.

So when we use structs to initialize the clocks we'll probably have
something like this:

static struct clk_divider somediv = {
	.reg = CCM_BASE + 0x14,
	.width = 3,
	.shift = 17,
	.lock = &ccm_lock,
	.hw.parent = "someotherdiv",
	.hw.flags = CLK_SET_RATE_PARENT,
};

This will make a 4000 line file out of a 500 line file. Now when for
some reason struct clk_divider changes we end with big patches. If the
clk core gets a new fancy CLK_ flag which we want to have then again
we end up with big patches. Then there's also the possibility that
someone finds out that .lock and .hw.flags are common to all dividers
and comes up with a #define DEFINE_CLK_DIVIDER again to share common
fields.

All this can be solved when we introduce a small wrapper function and
use it in the clock files:

static inline struct clk *imx_clk_divider(const char *name, const char *parent,
		void __iomem *reg, u8 shift, u8 width)
{
	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
			reg, shift, width, 0, &imx_ccm_lock);
}

It decouples us from the structs used by the clock framework, we can
add our preferred flags and still can share common fields like the lock.

While this was not the intention when I first converted from struct
initializers to function initializers I am confident that it will make
a good job.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Mar 20 14:14:41 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 20 Mar 2012 19:14:41 +0100
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <e22898bc8b69e85f1e6390d7d858f85c.squirrel@www.codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <e22898bc8b69e85f1e6390d7d858f85c.squirrel@www.codeaurora.org>
Message-ID: <20120320181441.GO3852@pengutronix.de>

On Tue, Mar 20, 2012 at 03:17:10AM -0700, Saravana Kannan wrote:
> 
> On Tue, March 20, 2012 2:40 am, Sascha Hauer wrote:
> > On Tue, Mar 20, 2012 at 12:54:55AM -0700, Saravana Kannan wrote:
> >>
> > I am using these functions and don't need a static array, I just call
> > the functions with the desired parameters.
> 
> Sure, then let's leave it in. Curious, where do you get the desired
> parameters from? Is it static date in code or is it from DT? You somehow
> probe it?

It's not from DT. See this thread:

http://www.spinics.net/lists/arm-kernel/msg165839.html

> 
> > Overall the clock framework was written in a way that we have to expose
> > as little information about the internally used structs as necessary. It
> > seems your patches are pulling in the opposite direction now.
> 
> I'm not exposing anything that you don't already pass from the platform
> driver. Also, you realize that this is very similar to what you suggested
> with clk_initializer right? If there is a strong push, we can make a copy
> of these inside the struct clk, but for these few init fields I don't see
> a point (see earlier email).

The difference is that a struct clk_initializer is only used to
initialize a clock and not actively used by the clock framework. But as
you already mentioned using a copy inside the clock framework has the
same effect.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From stigge at antcom.de  Tue Mar 20 14:20:12 2012
From: stigge at antcom.de (Roland Stigge)
Date: Tue, 20 Mar 2012 19:20:12 +0100
Subject: [PATCH] USB: gadget driver for LPC32xx
In-Reply-To: <201203201301.50159.arnd@arndb.de>
References: <1332191930-2433-1-git-send-email-stigge@antcom.de>
 <201203192130.13583.arnd@arndb.de> <4F67B28D.3060500@antcom.de>
 <201203201301.50159.arnd@arndb.de>
Message-ID: <4F68CA5C.2090406@antcom.de>

Hi Arnd,

On 03/20/2012 02:01 PM, Arnd Bergmann wrote:
>> Maybe the right thing is a common low-level isp1301 interface defining
>> all the registers and providing low-level (I2C) access functions,
>> leaving all the "higher level"/"board specific" functions up to the
>> existing drivers?
>>
>> (I guess you meant drivers/usb/otg/isp1301_omap.c ?)
> 
> Yes, that sounds like a very good idea. Can you describe which part of
> the function isp1301 does? It's not clear how the layering between
> that and the platform driver should end up.

The ISP1301 is a relatively simple transceiver where the actual
differential USB signals end up being generated/decoded. It contains
some registers and is controlled via I2C to manipulate electrical
settings (pull up / power etc.).

At a first glance, I found the following drivers to be using it:

ohci-nxp (was: ohci-pnx4008 + ohci-lpc32xx)
isp1301_omap
lpc32xx_udc (WIP)

The common functions that all of them are using are some low-level
functions like read/write byte, read/write word. (For ohci-nxp, I used
smbus commands.) I propose exporting just the defines for all the
registers and their bits together with some accessor functions.

Would those be the correct places for header and driver:

drivers/usb/misc/isp1301.c
include/linux/usb/isp1301.h

?

As an example usage, I would let the next update of the lpc32xx_udc use
it and separately provide patches to make the other drivers above also
use it.

Thanks in advance,

Roland


From john at szakmeister.net  Tue Mar 20 14:28:15 2012
From: john at szakmeister.net (John Szakmeister)
Date: Tue, 20 Mar 2012 14:28:15 -0400
Subject: No subject
Message-ID: <CAEBDL5WkFo-W32zTrJ6d_T2RzkocOVr-8aOU-ydApwxAH4fcFw@mail.gmail.com>

We've been running into several issues on the cache flushing front,
and I'm hoping that someone here can help clarify what should be
happening from a kernel perspective.

Late last year we discovered a few interesting problems.  One of them
is definitely our fault: we weren't flushing the cache after we read
data from a block device a wrote it into the page.  However, there was
another issue we noticed that made less sense: we had to flush a page
before writing it to our block device, otherwise we end up writing
some stale data.  The brd device ran into this issue before, and fixed
it in commit c2572f2b[1].  In that commit Nick Pidgin says:
    "brd is missing a flush_dcache_page. On 2nd thoughts, perhaps it is the
     pagecache's responsibility to flush user virtual aliases (the driver of
     course should flush kernel virtual mappings)... but anyway, there
     already exists cache flushing for one direction of transfer, so we
     should add the other."

I can't help but to feel he's right.  It was very surprising to me
that I had to flush the user virtual aliases before writing the data
to the device.  Is it expected that we (as device driver writers) have
to do that for block device drivers?  I love Linux, but one of the
aspects I find most frustrating is that I don't know what I can safely
assume at interface boundaries.  Even modeling my work after existing
code yields problems, because a number of drivers in the tree seem to
be broken in this regard.

But it leads to another concern.  Since I do have to flush on writes,
it got me thinking about whether it's necessary to flush user mode
aliases before conducting a read.  Consider the fact that a page can
span multiple blocks.  Is it possible that:
  * we're asked to read a block of data
  * a user app has scribbled on the page (so it's dirty, but not flushed)
  * we read the requested data from the device
  * load it into the page
  * do a flush_dcache_page()
  * then the data read from the device becomes corrupt because cached user data
    is written to RAM?

Or, instead of that, the cached data gets dropped entirely because it
was on the page, but shouldn't have been because we didn't read new
data into that area, and now that user data is lost?  I confess this
may all be my lack of understanding about Linux's block i/o subsystem,
but I'm thoroughly confused at this point.  What I do know is that
other device drivers are not flushing the page before writing the data
to a device.  For instance, the mmc driver for the at91 architecture
suffers from this problem, and I've been able to see that problem
using mmap.  My concern is that many other drivers also suffer from
this problem, so I'm not sure what the fix needs to be: fix the page
cache, fix the driver, or both.

Also, is there somewhere that says what's guaranteed on entry into my
block device driver?  I've scoured everything I could find... the
Documentation area (including cachetlb.txt), Linux sites, books...
I've yet to find anything mentioning the need to call
flush_dcache_page() much less talk about what the assumptions are.

Thanks in advance for the help.

-John

[1]: <http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=c2572f2b4ffc27ba79211aceee3bef53a59bb5cd>


From paul.gortmaker at windriver.com  Tue Mar 20 14:34:04 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Tue, 20 Mar 2012 14:34:04 -0400
Subject: linux-next: "ARM: make mach/io.h include optional" commit breaks
 cm_x2xx_defconfig
Message-ID: <4F68CD9C.3090001@windriver.com>

Hi Rob,

If you have a moment can you check this build failure?

http://kisskb.ellerman.id.au/kisskb/buildresult/5923845/

A git bisect seems to want to blame your commit for it.

Thanks,
Paul.

---

c334bc150524f833db3c76a0aaf55fb5044444e1 is the first bad commit
commit c334bc150524f833db3c76a0aaf55fb5044444e1
Author: Rob Herring <rob.herring at calxeda.com>
Date:   Sun Mar 4 22:03:33 2012 -0600

    ARM: make mach/io.h include optional


git bisect start
# good: [fde7d9049e55ab85a390be7f415d74c9f62dd0f9] Linux 3.3-rc7
git bisect good fde7d9049e55ab85a390be7f415d74c9f62dd0f9
# bad: [f355e8684f7e8e7077ca6d3988f24e01047804b6] Add linux-next specific files for 20120320
git bisect bad f355e8684f7e8e7077ca6d3988f24e01047804b6
# good: [5fe35ba6690ea0136d649cb2a07ac3f64a4c3cfb] Merge remote-tracking branch 'sound/for-next'
git bisect good 5fe35ba6690ea0136d649cb2a07ac3f64a4c3cfb
# good: [5260d60f170ebd381538dd56f6f6b765cbf9db29] Merge remote-tracking branch 'tip/auto-latest'
git bisect good 5260d60f170ebd381538dd56f6f6b765cbf9db29
# good: [2eb0aaa70022cbd3cdac7bdb610ed79a3b0c60a7] Merge remote-tracking branch 'writeback/writeback-for-next'
git bisect good 2eb0aaa70022cbd3cdac7bdb610ed79a3b0c60a7
# bad: [da7499ed07635785926c4a12915f54c61dc44170] Merge branch 'next/clk' into for-next
git bisect bad da7499ed07635785926c4a12915f54c61dc44170
# good: [eae71abd0e6d466105c66a40115907335a3e20fa] Merge branch 'next/boards' into for-next
git bisect good eae71abd0e6d466105c66a40115907335a3e20fa
# good: [cdc3df6f44f72c5924a16a47e1663c3fb0e57820] Merge branch 'dt-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
git bisect good cdc3df6f44f72c5924a16a47e1663c3fb0e57820
# good: [f66f9bdf6d2c2b540f73bb57bd24b886b39beb14] Merge branch 'lpc32xx/drivers' into next/drivers
git bisect good f66f9bdf6d2c2b540f73bb57bd24b886b39beb14
# good: [e5412a49eceeab5b9ecb761b536ad7ac829e1c45] Merge branch 'next/dt' into for-next
git bisect good e5412a49eceeab5b9ecb761b536ad7ac829e1c45
# good: [efa497b9ec8cc534f8883a2d1d42f52174070f38] ARM: dove: add explicit include of dove.h to addr-map.c
git bisect good efa497b9ec8cc534f8883a2d1d42f52174070f38
# bad: [accf709b39a9cdbeaf6233000ccb9af966fd691e] Merge branch 'io-cleanup-for-3.4' of git://sources.calxeda.com/kernel/linux into next/cleanup2
git bisect bad accf709b39a9cdbeaf6233000ccb9af966fd691e
# bad: [708795cd975579ba7115666f585c428f8cebd572] Merge branch 'io-cleanup-for-3.4' of git://sources.calxeda.com/kernel/linux into next/cleanup2
git bisect bad 708795cd975579ba7115666f585c428f8cebd572
# bad: [c334bc150524f833db3c76a0aaf55fb5044444e1] ARM: make mach/io.h include optional
git bisect bad c334bc150524f833db3c76a0aaf55fb5044444e1
# good: [41e32c906054be3a600cdeb69eb70350066e0a91] ARM: clps711x: remove unneeded include of mach/io.h
git bisect good 41e32c906054be3a600cdeb69eb70350066e0a91


From john at szakmeister.net  Tue Mar 20 15:03:38 2012
From: john at szakmeister.net (John Szakmeister)
Date: Tue, 20 Mar 2012 15:03:38 -0400
Subject: Cache flushing....
Message-ID: <CAEBDL5UtwetYm7WFLL1hEWT3xiyEy3C6p=GuDM7iSi71RcbFdg@mail.gmail.com>

Sorry for the re-post.  I forgot to put a title on the message.
Original text follows.

We've been running into several issues on the cache flushing front,
and I'm hoping that someone here can help clarify what should be
happening from a kernel perspective.

Late last year we discovered a few interesting problems.  One of them
is definitely our fault: we weren't flushing the cache after we read
data from a block device a wrote it into the page.  However, there was
another issue we noticed that made less sense: we had to flush a page
before writing it to our block device, otherwise we end up writing
some stale data.  The brd device ran into this issue before, and fixed
it in commit c2572f2b[1].  In that commit Nick Pidgin says:
   "brd is missing a flush_dcache_page. On 2nd thoughts, perhaps it is the
    pagecache's responsibility to flush user virtual aliases (the driver of
    course should flush kernel virtual mappings)... but anyway, there
    already exists cache flushing for one direction of transfer, so we
    should add the other."

I can't help but to feel he's right.  It was very surprising to me
that I had to flush the user virtual aliases before writing the data
to the device.  Is it expected that we (as device driver writers) have
to do that for block device drivers?  I love Linux, but one of the
aspects I find most frustrating is that I don't know what I can safely
assume at interface boundaries.  Even modeling my work after existing
code yields problems, because a number of drivers in the tree seem to
be broken in this regard.

But it leads to another concern.  Since I do have to flush on writes,
it got me thinking about whether it's necessary to flush user mode
aliases before conducting a read.  Consider the fact that a page can
span multiple blocks.  Is it possible that:
 * we're asked to read a block of data
 * a user app has scribbled on the page (so it's dirty, but not flushed)
 * we read the requested data from the device
 * load it into the page
 * do a flush_dcache_page()
 * then the data read from the device becomes corrupt because cached user data
   is written to RAM?

Or, instead of that, the cached data gets dropped entirely because it
was on the page, but shouldn't have been because we didn't read new
data into that area, and now that user data is lost?  I confess this
may all be my lack of understanding about Linux's block i/o subsystem,
but I'm thoroughly confused at this point.  What I do know is that
other device drivers are not flushing the page before writing the data
to a device.  For instance, the mmc driver for the at91 architecture
suffers from this problem, and I've been able to see that problem
using mmap.  My concern is that many other drivers also suffer from
this problem, so I'm not sure what the fix needs to be: fix the page
cache, fix the driver, or both.

Also, is there somewhere that says what's guaranteed on entry into my
block device driver?  I've scoured everything I could find... the
Documentation area (including cachetlb.txt), Linux sites, books...
I've yet to find anything mentioning the need to call
flush_dcache_page() much less talk about what the assumptions are.

Thanks in advance for the help.

-John

[1]: <http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=c2572f2b4ffc27ba79211aceee3bef53a59bb5cd>


From arnd at arndb.de  Tue Mar 20 15:21:50 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 20 Mar 2012 19:21:50 +0000
Subject: [PATCH] USB: gadget driver for LPC32xx
In-Reply-To: <4F68CA5C.2090406@antcom.de>
References: <1332191930-2433-1-git-send-email-stigge@antcom.de>
 <201203201301.50159.arnd@arndb.de> <4F68CA5C.2090406@antcom.de>
Message-ID: <201203201921.51253.arnd@arndb.de>

On Tuesday 20 March 2012, Roland Stigge wrote:
> The ISP1301 is a relatively simple transceiver where the actual
> differential USB signals end up being generated/decoded. It contains
> some registers and is controlled via I2C to manipulate electrical
> settings (pull up / power etc.).
> 
> At a first glance, I found the following drivers to be using it:
> 
> ohci-nxp (was: ohci-pnx4008 + ohci-lpc32xx)
> isp1301_omap
> lpc32xx_udc (WIP)
> 
> The common functions that all of them are using are some low-level
> functions like read/write byte, read/write word. (For ohci-nxp, I used
> smbus commands.) I propose exporting just the defines for all the
> registers and their bits together with some accessor functions.

Sounds great. 

> Would those be the correct places for header and driver:
> 
> drivers/usb/misc/isp1301.c
> include/linux/usb/isp1301.h

I believe drivers/usb/misc/ is for usb devices, not for usb hots
(otg or otherwise), but I'm not sure where else it would go.

> As an example usage, I would let the next update of the lpc32xx_udc use
> it and separately provide patches to make the other drivers above also
> use it.

Ok. One thing I'm not sure about is how you would pair the i2c
device with the platform specific driver. The easiest solution would
be to assume that there is always just one of each, so isp1301 binds
to the i2c device and exports functions to be used by the platform
driver. This would fail if you ever have more than one isp1301
in the system, but neither omap nor pnx4008 seem to be doing that.

I guess we can always add support for that later if needed, using
a device tree phandle link, or a pointer to the i2c device in
platform_data.

	Arnd


From skannan at codeaurora.org  Tue Mar 20 16:06:34 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 20 Mar 2012 13:06:34 -0700
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <20120320181050.GN3852@pengutronix.de>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <20120320141811.GF32469@S2101-09.ap.freescale.net>
 <20120320181050.GN3852@pengutronix.de>
Message-ID: <4F68E34A.70207@codeaurora.org>

On 03/20/2012 11:10 AM, Sascha Hauer wrote:
> On Tue, Mar 20, 2012 at 10:18:14PM +0800, Shawn Guo wrote:
>> On Tue, Mar 20, 2012 at 10:40:31AM +0100, Sascha Hauer wrote:
>> ...
>>> I am using these functions and don't need a static array, I just call
>>> the functions with the desired parameters.
>>>
>> With this patch getting in, you do not have to use them then.  I feel
>> a static array will be much more readable than a long list of function
>> calls with a long list of hardcoded arguments to each.
>
> I'm also not a fan of long argument lists; a divider like defined in my
> tree takes 5 arguments, a gate 4 and a mux 6. While 6 is already at the
> border I think it's still acceptable.
>
> What I like in terms of readability is one line per clock which makes
> for quite short clock files.

It certainly makes for short clock files, but it's definitely less 
readable that the expanded struct. For the original author the "one line 
per clock" looks readable since they wrote it. But for someone looking 
at the code to modify it, the expanded one would be much easier to read. 
Also, you can always declare your own macro if you really want to follow 
the one line approach.

> So when we use structs to initialize the clocks we'll probably have
> something like this:
>
> static struct clk_divider somediv = {
> 	.reg = CCM_BASE + 0x14,
> 	.width = 3,
> 	.shift = 17,
> 	.lock =&ccm_lock,
> 	.hw.parent = "someotherdiv",
> 	.hw.flags = CLK_SET_RATE_PARENT,
> };

Taken from your patches:

imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, 
ARRAY_SIZE(spll_sel_clks));

Compare the struct to the one line call. Now tell me, what does "1" 
represent? No clue. But in the struct, I can immediately tell what each 
one of the parameters are.

Anyway, my patch certainly isn't forcing you to use multiple lines. So, 
hopefully this won't be a point of contention.

> This will make a 4000 line file out of a 500 line file. Now when for
> some reason struct clk_divider changes we end with big patches. If the
> clk core gets a new fancy CLK_ flag which we want to have then again
> we end up with big patches. Then there's also the possibility that
> someone finds out that .lock and .hw.flags are common to all dividers
> and comes up with a #define DEFINE_CLK_DIVIDER again to share common
> fields.

This patch won't prevent you from doing any of that. You can still 
create macros for that (there are already one for that). Also, what you 
are pointing out is a bigger problem for the current clk_register() 
function since you might have to change the no. of params of all the 
callers even if a new field is optional.

> All this can be solved when we introduce a small wrapper function and
> use it in the clock files:
>
> static inline struct clk *imx_clk_divider(const char *name, const char *parent,
> 		void __iomem *reg, u8 shift, u8 width)
> {
> 	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
> 			reg, shift, width, 0,&imx_ccm_lock);
> }
>
> It decouples us from the structs used by the clock framework, we can
> add our preferred flags and still can share common fields like the lock.
>
> While this was not the intention when I first converted from struct
> initializers to function initializers I am confident that it will make
> a good job.

Now I'm confused -- it's not clear if you are leaning towards my patch 
or away from it?

I also think we are talking about issues orthogonal to my patch. I don't 
think my patch prevents you from doing any of this as long as you are up 
for wrapper fns or macros.

-Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From skannan at codeaurora.org  Tue Mar 20 16:14:51 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 20 Mar 2012 13:14:51 -0700
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <20120320181441.GO3852@pengutronix.de>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <e22898bc8b69e85f1e6390d7d858f85c.squirrel@www.codeaurora.org>
 <20120320181441.GO3852@pengutronix.de>
Message-ID: <4F68E53B.7040800@codeaurora.org>

On 03/20/2012 11:14 AM, Sascha Hauer wrote:
> On Tue, Mar 20, 2012 at 03:17:10AM -0700, Saravana Kannan wrote:
>>
>> On Tue, March 20, 2012 2:40 am, Sascha Hauer wrote:
>>> On Tue, Mar 20, 2012 at 12:54:55AM -0700, Saravana Kannan wrote:
>>>>
>>> I am using these functions and don't need a static array, I just call
>>> the functions with the desired parameters.
>>
>> Sure, then let's leave it in. Curious, where do you get the desired
>> parameters from? Is it static date in code or is it from DT? You somehow
>> probe it?
>
> It's not from DT. See this thread:
>
> http://www.spinics.net/lists/arm-kernel/msg165839.html

Ah, I see. That's a lot of functions calls. I think it would be much 
more efficient if you just have an array and loop over it. With my 
patch, you can just call a single register function for all these clocks.

>>
>>> Overall the clock framework was written in a way that we have to expose
>>> as little information about the internally used structs as necessary. It
>>> seems your patches are pulling in the opposite direction now.
>>
>> I'm not exposing anything that you don't already pass from the platform
>> driver. Also, you realize that this is very similar to what you suggested
>> with clk_initializer right? If there is a strong push, we can make a copy
>> of these inside the struct clk, but for these few init fields I don't see
>> a point (see earlier email).
>
> The difference is that a struct clk_initializer is only used to
> initialize a clock and not actively used by the clock framework. But as
> you already mentioned using a copy inside the clock framework has the
> same effect.

My opinion on this is to follow a wait and watch approach on the "flags" 
field. I really can't think of a safe way anyone can misuse it. If 
people start doing that, we can just do the copy and let them deal with 
their broken code. Until that happens, I don't want to waste time/space 
by copying it. The rest of the fields aren't actively used by the common 
clock code after init.

Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From heiko at sntech.de  Tue Mar 20 16:20:45 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Tue, 20 Mar 2012 21:20:45 +0100
Subject: [PATCH][RESEND] ARM: SAMSUNG: make SAMSUNG_PM_DEBUG select DEBUG_LL
Message-ID: <201203202120.45806.heiko@sntech.de>

From: Maurus Cuelenaere <mcuelenaere at gmail.com>

When selecting SAMSUNG_PM_DEBUG, it complains about a missing printascii()
function if you do not select DEBUG_LL, so make the former select the latter.

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
Acked-by: Heiko Stuebner <heiko at sntech.de>
---
This was originally sent in september 2010, but seems to have been forgotten.
As this problem has bitten me today, here it is again.

 arch/arm/plat-samsung/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 6a2abe6..ec84c1a 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -302,6 +302,7 @@ comment "Power management"
 config SAMSUNG_PM_DEBUG
 	bool "S3C2410 PM Suspend debug"
 	depends on PM
+	select DEBUG_LL
 	help
 	  Say Y here if you want verbose debugging from the PM Suspend and
 	  Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
-- 
1.7.2.3



From rob.lee at linaro.org  Tue Mar 20 16:22:41 2012
From: rob.lee at linaro.org (Robert Lee)
Date: Tue, 20 Mar 2012 15:22:41 -0500
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
Message-ID: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>

This patch series moves various functionality duplicated in platform 
cpuidle drivers to the core cpuidle driver. Also, the platform irq
disabling was removed as it appears that all calls into 
cpuidle_call_idle will have already called local_irq_disable().

These changes have been pulled into linux-next.

Len, Andrew, can a request be made for Linus to pull these changes?

Acked-by: Jean Pihet<j-pihet at ti.com>  (v6)
Tested-by: Jean Pihet<j-pihet at ti.com>  (v6, omap3)
Tested-by: Amit Daniel<amit.kachhap at linaro.org>  (v6, Exynos4)
Tested-by: Robert Lee<rob.lee at linaro.org>  (imx51, imx6q)
Reviewed-by: Kevin Hilman <khilman at ti.com>
Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Reviewed-by: Deepthi Dharwar<deepthi at linux.vnet.ibm.com> (core cpuidle only)

v8 changes:
* v7 testing in linux-next revealed a bug reported by Hugh Dickins on x86
platforms.  Investigated and fixed by Daniel Lezcano.
* Made a slight change to the defaut ARM WFI state macro as Daniel Lezcano
suggested the previous interface was prone to mis-use by platforms that 
set power_specified to 1.
* updated to kernel v3.3

These v8 fixes have been applied to the pull tree being used by linux-next:
git://git.linaro.org/people/rob_lee/linux.git cpuidle_consol_pull

v7 submission can be found here:
http://www.spinics.net/lists/arm-kernel/msg162290.html

v7 changes:
* Made some  struct whitespace alignment changes.
* Fixed a coding style violation (thanks Jean Pihet)
* Fixed a bug in davinci cpuidle (thanks Jean Pihet)
* Corrected the common ARM cpuidle WFI state description to be ARM platform
 agnostic (thanks Kevin Hilman)
* Fixed the problem causing x86 and PPC builds to fail (thanks Deepthi)
* Re-added a line of code that was mistakenly removed (thanks Deepthi)

v6 submission can be found here:
http://www.spinics.net/lists/arm-kernel/msg162018.html

v6 changes:
* Fixed mindless bug in CONFIG_ARCH_HAS_RELAX code in drivers/cpuidle/cpuidle.c
* Removed inline from wrapper function (thanks Mike Turquette and Rob Herring)
* Add zeroing out of last_residency if error value is returned (thanks Mike)
* Made drivers/cpuidle/cpuidle.c more intelligently handle en_core_tk_irqen
flag allowing removal of the if (en_core_tk_irqen) in cpuidle_idle_call (thanks
Daniel Lezcano)
* Moved CPUIDLE_ARM_WFI_STATE macro to arch/arm/include/asm/cpuidle.h (thanks
Jean Pihet)
* Cleaned up some comments and a stray change (thanks Jean)

v5 submission can be found here:
http://www.spinics.net/lists/arm-kernel/msg161596.html

v5 changes:
* Added common cpu_do_idle function to core cpuidle
* Added time keep irq en wrapper to core cpuidle
* Removed pre/post enter
* Re-added platforms that can use new common code.

v4 submission can be found here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/082742.html

v4 changes:
* Removed drivers/cpuidle/common.c
** Removed the initialization helper functions
** Removed the wrapper used to consolidate time keeping and irq enable/disable
* Add time keeping and local_irq_disable handling in cpuidle_call_idle().
* Made necessary modifications to a few platforms that required the most changes
** Note on omap3: changed structure of omap3_idle_drvdata and added
 per_next_state and per_saved_state vars to accomodate new framework.

v3 submission can be found here:
http://www.spinics.net/lists/arm-kernel/msg156751.html

v3 changes:
* Made various code organization and style changes as suggested in v2 review.
 (thanks Mark Brown, Rob Herring, Mike Turquette, Kevin Hillman, Daniel Lezcano)
* Removed at91 use of common code.  A separate effort is underway to clean
at91 code and the author has offered to convert to common interface as part
of those changes (if this common interface is accepted in time).
* Made platform cpuidle_driver objects __initdata and dynamically added one
persistent instance of this object in common code.
* Removed imx5 pm usage of gpc_dvfs clock as it is no longer needed after
being enabled during clock initialization.
* Re-organized patches.

v2 submission can be found here:
http://comments.gmane.org/gmane.linux.ports.arm.kernel/144199

v2 changes:
* Common interface moved to drivers/cpuidle and made non arch-specific.
* Made various fixes and suggested additions to the common cpuidle
code from v1 review. (Thanks Rob Herring and Mark Brown)
* Added callback for filling in driver_data field as needed.
* Modified the various platforms with these changes.

v1 submission can be found here:
http://comments.gmane.org/gmane.linux.ports.arm.kernel/142791

Robert Lee (8):
  cpuidle: Add common time keeping and irq enabling
  ARM: at91: Consolidate time keeping and irq enable
  ARM: kirkwood: Consolidate time keeping and irq enable
  ARM: davinci: Consolidate time keeping and irq enable
  ARM: omap: Consolidate OMAP3 time keeping and irq enable
  ARM: omap: Consolidate OMAP4 time keeping and irq enable
  ARM: shmobile: Consolidate time keeping and irq enable
  SH: shmobile: Consolidate time keeping and irq enable

 arch/arm/include/asm/cpuidle.h        |   30 ++++++++++++
 arch/arm/kernel/Makefile              |    2 +-
 arch/arm/kernel/cpuidle.c             |   21 +++++++++
 arch/arm/mach-at91/cpuidle.c          |   67 ++++++++++-----------------
 arch/arm/mach-davinci/cpuidle.c       |   82 +++++++++++++--------------------
 arch/arm/mach-kirkwood/cpuidle.c      |   72 +++++++++--------------------
 arch/arm/mach-omap2/cpuidle34xx.c     |   42 +++++++----------
 arch/arm/mach-omap2/cpuidle44xx.c     |   21 ++-------
 arch/arm/mach-shmobile/cpuidle.c      |   31 +++----------
 arch/sh/kernel/cpu/shmobile/cpuidle.c |   10 ++--
 drivers/cpuidle/cpuidle.c             |   66 +++++++++++++++++++++++---
 include/linux/cpuidle.h               |   13 +++++-
 12 files changed, 231 insertions(+), 226 deletions(-)
 create mode 100644 arch/arm/include/asm/cpuidle.h
 create mode 100644 arch/arm/kernel/cpuidle.c

-- 
1.7.9.4



From rob.lee at linaro.org  Tue Mar 20 16:22:42 2012
From: rob.lee at linaro.org (Robert Lee)
Date: Tue, 20 Mar 2012 15:22:42 -0500
Subject: [PATCH v8 1/8] cpuidle: Add common time keeping and irq enabling
In-Reply-To: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
Message-ID: <1332274969-15782-2-git-send-email-rob.lee@linaro.org>

Make necessary changes to implement time keeping and irq enabling
in the core cpuidle code.  This will allow the removal of these
functionalities from various platform cpuidle implementations whose
timekeeping and irq enabling follows the form in this common code.

Signed-off-by: Robert Lee <rob.lee at linaro.org>
Tested-by: Jean Pihet<j-pihet at ti.com>
Tested-by: Amit Daniel<amit.kachhap at linaro.org>
Tested-by: Robert Lee<rob.lee at linaro.org>
Reviewed-by: Kevin Hilman <khilman at ti.com>
Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Reviewed-by: Deepthi Dharwar<deepthi at linux.vnet.ibm.com>
Acked-by: Jean Pihet<j-pihet at ti.com>
---
 arch/arm/include/asm/cpuidle.h |   30 ++++++++++++++++++
 arch/arm/kernel/Makefile       |    2 +-
 arch/arm/kernel/cpuidle.c      |   21 +++++++++++++
 drivers/cpuidle/cpuidle.c      |   66 +++++++++++++++++++++++++++++++++++-----
 include/linux/cpuidle.h        |   13 +++++++-
 5 files changed, 123 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/include/asm/cpuidle.h
 create mode 100644 arch/arm/kernel/cpuidle.c

diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h
new file mode 100644
index 0000000..9322f444
--- /dev/null
+++ b/arch/arm/include/asm/cpuidle.h
@@ -0,0 +1,30 @@
+#ifndef __ASM_ARM_CPUIDLE_H
+#define __ASM_ARM_CPUIDLE_H
+
+#ifdef CONFIG_CPU_IDLE
+extern int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
+		struct cpuidle_driver *drv, int index);
+#else
+static inline int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
+		struct cpuidle_driver *drv, int index) { return -ENODEV; }
+#endif
+
+/* Common ARM WFI state */
+#define ARM_CPUIDLE_WFI_STATE_PWR(p) {\
+	.enter                  = arm_cpuidle_simple_enter,\
+	.exit_latency           = 1,\
+	.target_residency       = 1,\
+	.power_usage		= p,\
+	.flags                  = CPUIDLE_FLAG_TIME_VALID,\
+	.name                   = "WFI",\
+	.desc                   = "ARM WFI",\
+}
+
+/*
+ * in case power_specified == 1, give a default WFI power value needed
+ * by some governors
+ */
+#define ARM_CPUIDLE_WFI_STATE ARM_CPUIDLE_WFI_STATE_PWR(UINT_MAX)
+
+#endif
+
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 43b740d..940c27f 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -21,7 +21,7 @@ obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
 
 obj-$(CONFIG_LEDS)		+= leds.o
 obj-$(CONFIG_OC_ETM)		+= etm.o
-
+obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 obj-$(CONFIG_ISA_DMA_API)	+= dma.o
 obj-$(CONFIG_ARCH_ACORN)	+= ecard.o 
 obj-$(CONFIG_FIQ)		+= fiq.o fiqasm.o
diff --git a/arch/arm/kernel/cpuidle.c b/arch/arm/kernel/cpuidle.c
new file mode 100644
index 0000000..89545f6
--- /dev/null
+++ b/arch/arm/kernel/cpuidle.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/cpuidle.h>
+#include <asm/proc-fns.h>
+
+int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
+		struct cpuidle_driver *drv, int index)
+{
+	cpu_do_idle();
+
+	return index;
+}
diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index 59f4261..4869b55 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -53,6 +53,24 @@ static void cpuidle_kick_cpus(void) {}
 
 static int __cpuidle_register_device(struct cpuidle_device *dev);
 
+static inline int cpuidle_enter(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv, int index)
+{
+	struct cpuidle_state *target_state = &drv->states[index];
+	return target_state->enter(dev, drv, index);
+}
+
+static inline int cpuidle_enter_tk(struct cpuidle_device *dev,
+			       struct cpuidle_driver *drv, int index)
+{
+	return cpuidle_wrap_enter(dev, drv, index, cpuidle_enter);
+}
+
+typedef int (*cpuidle_enter_t)(struct cpuidle_device *dev,
+			       struct cpuidle_driver *drv, int index);
+
+static cpuidle_enter_t cpuidle_enter_ops;
+
 /**
  * cpuidle_idle_call - the main idle loop
  *
@@ -63,7 +81,6 @@ int cpuidle_idle_call(void)
 {
 	struct cpuidle_device *dev = __this_cpu_read(cpuidle_devices);
 	struct cpuidle_driver *drv = cpuidle_get_driver();
-	struct cpuidle_state *target_state;
 	int next_state, entered_state;
 
 	if (off)
@@ -92,12 +109,10 @@ int cpuidle_idle_call(void)
 		return 0;
 	}
 
-	target_state = &drv->states[next_state];
-
 	trace_power_start(POWER_CSTATE, next_state, dev->cpu);
 	trace_cpu_idle(next_state, dev->cpu);
 
-	entered_state = target_state->enter(dev, drv, next_state);
+	entered_state = cpuidle_enter_ops(dev, drv, next_state);
 
 	trace_power_end(dev->cpu);
 	trace_cpu_idle(PWR_EVENT_EXIT, dev->cpu);
@@ -110,6 +125,8 @@ int cpuidle_idle_call(void)
 		dev->states_usage[entered_state].time +=
 				(unsigned long long)dev->last_residency;
 		dev->states_usage[entered_state].usage++;
+	} else {
+		dev->last_residency = 0;
 	}
 
 	/* give the governor an opportunity to reflect on the outcome */
@@ -164,6 +181,37 @@ void cpuidle_resume_and_unlock(void)
 
 EXPORT_SYMBOL_GPL(cpuidle_resume_and_unlock);
 
+/**
+ * cpuidle_wrap_enter - performs timekeeping and irqen around enter function
+ * @dev: pointer to a valid cpuidle_device object
+ * @drv: pointer to a valid cpuidle_driver object
+ * @index: index of the target cpuidle state.
+ */
+int cpuidle_wrap_enter(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv, int index,
+				int (*enter)(struct cpuidle_device *dev,
+					struct cpuidle_driver *drv, int index))
+{
+	ktime_t time_start, time_end;
+	s64 diff;
+
+	time_start = ktime_get();
+
+	index = enter(dev, drv, index);
+
+	time_end = ktime_get();
+
+	local_irq_enable();
+
+	diff = ktime_to_us(ktime_sub(time_end, time_start));
+	if (diff > INT_MAX)
+		diff = INT_MAX;
+
+	dev->last_residency = (int) diff;
+
+	return index;
+}
+
 #ifdef CONFIG_ARCH_HAS_CPU_RELAX
 static int poll_idle(struct cpuidle_device *dev,
 		struct cpuidle_driver *drv, int index)
@@ -212,10 +260,11 @@ static void poll_idle_init(struct cpuidle_driver *drv) {}
 int cpuidle_enable_device(struct cpuidle_device *dev)
 {
 	int ret, i;
+	struct cpuidle_driver *drv = cpuidle_get_driver();
 
 	if (dev->enabled)
 		return 0;
-	if (!cpuidle_get_driver() || !cpuidle_curr_governor)
+	if (!drv || !cpuidle_curr_governor)
 		return -EIO;
 	if (!dev->state_count)
 		return -EINVAL;
@@ -226,13 +275,16 @@ int cpuidle_enable_device(struct cpuidle_device *dev)
 			return ret;
 	}
 
-	poll_idle_init(cpuidle_get_driver());
+	cpuidle_enter_ops = drv->en_core_tk_irqen ?
+		cpuidle_enter_tk : cpuidle_enter;
+
+	poll_idle_init(drv);
 
 	if ((ret = cpuidle_add_state_sysfs(dev)))
 		return ret;
 
 	if (cpuidle_curr_governor->enable &&
-	    (ret = cpuidle_curr_governor->enable(cpuidle_get_driver(), dev)))
+	    (ret = cpuidle_curr_governor->enable(drv, dev)))
 		goto fail_sysfs;
 
 	for (i = 0; i < dev->state_count; i++) {
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 712abcc..927db28 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -15,6 +15,7 @@
 #include <linux/list.h>
 #include <linux/kobject.h>
 #include <linux/completion.h>
+#include <linux/hrtimer.h>
 
 #define CPUIDLE_STATE_MAX	8
 #define CPUIDLE_NAME_LEN	16
@@ -122,6 +123,8 @@ struct cpuidle_driver {
 	struct module 		*owner;
 
 	unsigned int		power_specified:1;
+	/* set to 1 to use the core cpuidle time keeping (for all states). */
+	unsigned int		en_core_tk_irqen:1;
 	struct cpuidle_state	states[CPUIDLE_STATE_MAX];
 	int			state_count;
 	int			safe_state_index;
@@ -140,7 +143,10 @@ extern void cpuidle_pause_and_lock(void);
 extern void cpuidle_resume_and_unlock(void);
 extern int cpuidle_enable_device(struct cpuidle_device *dev);
 extern void cpuidle_disable_device(struct cpuidle_device *dev);
-
+extern int cpuidle_wrap_enter(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv, int index,
+				int (*enter)(struct cpuidle_device *dev,
+					struct cpuidle_driver *drv, int index));
 #else
 static inline void disable_cpuidle(void) { }
 static inline int cpuidle_idle_call(void) { return -ENODEV; }
@@ -157,6 +163,11 @@ static inline void cpuidle_resume_and_unlock(void) { }
 static inline int cpuidle_enable_device(struct cpuidle_device *dev)
 {return -ENODEV; }
 static inline void cpuidle_disable_device(struct cpuidle_device *dev) { }
+static inline int cpuidle_wrap_enter(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv, int index,
+				int (*enter)(struct cpuidle_device *dev,
+					struct cpuidle_driver *drv, int index))
+{ return -ENODEV; }
 
 #endif
 
-- 
1.7.9.4



From rob.lee at linaro.org  Tue Mar 20 16:22:43 2012
From: rob.lee at linaro.org (Robert Lee)
Date: Tue, 20 Mar 2012 15:22:43 -0500
Subject: [PATCH v8 2/8] ARM: at91: Consolidate time keeping and irq enable
In-Reply-To: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
Message-ID: <1332274969-15782-3-git-send-email-rob.lee@linaro.org>

Enable core cpuidle timekeeping and irq enabling and remove that
handling from this code.

Signed-off-by: Robert Lee <rob.lee at linaro.org>
Reviewed-by: Kevin Hilman <khilman at ti.com>
Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Acked-by: Jean Pihet<j-pihet at ti.com>
---
 arch/arm/mach-at91/cpuidle.c |   67 +++++++++++++++---------------------------
 1 file changed, 24 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index a851e6c..d40b3f3 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -17,9 +17,10 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/cpuidle.h>
-#include <asm/proc-fns.h>
 #include <linux/io.h>
 #include <linux/export.h>
+#include <asm/proc-fns.h>
+#include <asm/cpuidle.h>
 
 #include "pm.h"
 
@@ -27,66 +28,46 @@
 
 static DEFINE_PER_CPU(struct cpuidle_device, at91_cpuidle_device);
 
-static struct cpuidle_driver at91_idle_driver = {
-	.name =         "at91_idle",
-	.owner =        THIS_MODULE,
-};
-
 /* Actual code that puts the SoC in different idle states */
 static int at91_enter_idle(struct cpuidle_device *dev,
 			struct cpuidle_driver *drv,
 			       int index)
 {
-	struct timeval before, after;
-	int idle_time;
 	u32 saved_lpr;
 
-	local_irq_disable();
-	do_gettimeofday(&before);
-	if (index == 0)
-		/* Wait for interrupt state */
-		cpu_do_idle();
-	else if (index == 1) {
-		asm("b 1f; .align 5; 1:");
-		asm("mcr p15, 0, r0, c7, c10, 4");	/* drain write buffer */
-		saved_lpr = sdram_selfrefresh_enable();
-		cpu_do_idle();
-		sdram_selfrefresh_disable(saved_lpr);
-	}
-	do_gettimeofday(&after);
-	local_irq_enable();
-	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
-			(after.tv_usec - before.tv_usec);
+	__asm__("b 1f; .align 5; 1:\n"
+	"	mcr p15, 0, r0, c7, c10, 4");	/* drain write buffer */
+
+	saved_lpr = sdram_selfrefresh_enable();
+	cpu_do_idle();
+	sdram_selfrefresh_disable(saved_lpr);
 
-	dev->last_residency = idle_time;
 	return index;
 }
 
+static struct cpuidle_driver at91_idle_driver = {
+	.name			= "at91_idle",
+	.owner			= THIS_MODULE,
+	.en_core_tk_irqen	= 1,
+	.states[0]		= ARM_CPUIDLE_WFI_STATE,
+	.states[1]		= {
+		.enter			= at91_enter_idle,
+		.exit_latency		= 10,
+		.target_residency	= 100000,
+		.flags			= CPUIDLE_FLAG_TIME_VALID,
+		.name			= "RAM_SR",
+		.desc			= "WFI and DDR Self Refresh",
+	},
+	.state_count = AT91_MAX_STATES,
+};
+
 /* Initialize CPU idle by registering the idle states */
 static int at91_init_cpuidle(void)
 {
 	struct cpuidle_device *device;
-	struct cpuidle_driver *driver = &at91_idle_driver;
 
 	device = &per_cpu(at91_cpuidle_device, smp_processor_id());
 	device->state_count = AT91_MAX_STATES;
-	driver->state_count = AT91_MAX_STATES;
-
-	/* Wait for interrupt state */
-	driver->states[0].enter = at91_enter_idle;
-	driver->states[0].exit_latency = 1;
-	driver->states[0].target_residency = 10000;
-	driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
-	strcpy(driver->states[0].name, "WFI");
-	strcpy(driver->states[0].desc, "Wait for interrupt");
-
-	/* Wait for interrupt and RAM self refresh state */
-	driver->states[1].enter = at91_enter_idle;
-	driver->states[1].exit_latency = 10;
-	driver->states[1].target_residency = 10000;
-	driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
-	strcpy(driver->states[1].name, "RAM_SR");
-	strcpy(driver->states[1].desc, "WFI and RAM Self Refresh");
 
 	cpuidle_register_driver(&at91_idle_driver);
 
-- 
1.7.9.4



From rob.lee at linaro.org  Tue Mar 20 16:22:44 2012
From: rob.lee at linaro.org (Robert Lee)
Date: Tue, 20 Mar 2012 15:22:44 -0500
Subject: [PATCH v8 3/8] ARM: kirkwood: Consolidate time keeping and irq enable
In-Reply-To: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
Message-ID: <1332274969-15782-4-git-send-email-rob.lee@linaro.org>

Enable core cpuidle timekeeping and irq enabling and remove that
handling from this code.

Signed-off-by: Robert Lee <rob.lee at linaro.org>
Reviewed-by: Kevin Hilman <khilman at ti.com>
Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Acked-by: Jean Pihet<j-pihet at ti.com>
---
 arch/arm/mach-kirkwood/cpuidle.c |   72 +++++++++++---------------------------
 1 file changed, 21 insertions(+), 51 deletions(-)

diff --git a/arch/arm/mach-kirkwood/cpuidle.c b/arch/arm/mach-kirkwood/cpuidle.c
index 7088180..0f17109 100644
--- a/arch/arm/mach-kirkwood/cpuidle.c
+++ b/arch/arm/mach-kirkwood/cpuidle.c
@@ -20,77 +20,47 @@
 #include <linux/io.h>
 #include <linux/export.h>
 #include <asm/proc-fns.h>
+#include <asm/cpuidle.h>
 #include <mach/kirkwood.h>
 
 #define KIRKWOOD_MAX_STATES	2
 
-static struct cpuidle_driver kirkwood_idle_driver = {
-	.name =         "kirkwood_idle",
-	.owner =        THIS_MODULE,
-};
-
-static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device);
-
 /* Actual code that puts the SoC in different idle states */
 static int kirkwood_enter_idle(struct cpuidle_device *dev,
 				struct cpuidle_driver *drv,
 			       int index)
 {
-	struct timeval before, after;
-	int idle_time;
-
-	local_irq_disable();
-	do_gettimeofday(&before);
-	if (index == 0)
-		/* Wait for interrupt state */
-		cpu_do_idle();
-	else if (index == 1) {
-		/*
-		 * Following write will put DDR in self refresh.
-		 * Note that we have 256 cycles before DDR puts it
-		 * self in self-refresh, so the wait-for-interrupt
-		 * call afterwards won't get the DDR from self refresh
-		 * mode.
-		 */
-		writel(0x7, DDR_OPERATION_BASE);
-		cpu_do_idle();
-	}
-	do_gettimeofday(&after);
-	local_irq_enable();
-	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
-			(after.tv_usec - before.tv_usec);
-
-	/* Update last residency */
-	dev->last_residency = idle_time;
+	writel(0x7, DDR_OPERATION_BASE);
+	cpu_do_idle();
 
 	return index;
 }
 
+static struct cpuidle_driver kirkwood_idle_driver = {
+	.name			= "kirkwood_idle",
+	.owner			= THIS_MODULE,
+	.en_core_tk_irqen	= 1,
+	.states[0]		= ARM_CPUIDLE_WFI_STATE,
+	.states[1]		= {
+		.enter			= kirkwood_enter_idle,
+		.exit_latency		= 10,
+		.target_residency	= 100000,
+		.flags			= CPUIDLE_FLAG_TIME_VALID,
+		.name			= "DDR SR",
+		.desc			= "WFI and DDR Self Refresh",
+	},
+	.state_count = KIRKWOOD_MAX_STATES,
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device);
+
 /* Initialize CPU idle by registering the idle states */
 static int kirkwood_init_cpuidle(void)
 {
 	struct cpuidle_device *device;
-	struct cpuidle_driver *driver = &kirkwood_idle_driver;
 
 	device = &per_cpu(kirkwood_cpuidle_device, smp_processor_id());
 	device->state_count = KIRKWOOD_MAX_STATES;
-	driver->state_count = KIRKWOOD_MAX_STATES;
-
-	/* Wait for interrupt state */
-	driver->states[0].enter = kirkwood_enter_idle;
-	driver->states[0].exit_latency = 1;
-	driver->states[0].target_residency = 10000;
-	driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
-	strcpy(driver->states[0].name, "WFI");
-	strcpy(driver->states[0].desc, "Wait for interrupt");
-
-	/* Wait for interrupt and DDR self refresh state */
-	driver->states[1].enter = kirkwood_enter_idle;
-	driver->states[1].exit_latency = 10;
-	driver->states[1].target_residency = 10000;
-	driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
-	strcpy(driver->states[1].name, "DDR SR");
-	strcpy(driver->states[1].desc, "WFI and DDR Self Refresh");
 
 	cpuidle_register_driver(&kirkwood_idle_driver);
 	if (cpuidle_register_device(device)) {
-- 
1.7.9.4



From rob.lee at linaro.org  Tue Mar 20 16:22:45 2012
From: rob.lee at linaro.org (Robert Lee)
Date: Tue, 20 Mar 2012 15:22:45 -0500
Subject: [PATCH v8 4/8] ARM: davinci: Consolidate time keeping and irq enable
In-Reply-To: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
Message-ID: <1332274969-15782-5-git-send-email-rob.lee@linaro.org>

Enable core cpuidle timekeeping and irq enabling and remove that
handling from this code.

Signed-off-by: Robert Lee <rob.lee at linaro.org>
Reviewed-by: Kevin Hilman <khilman at ti.com>
Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Acked-by: Jean Pihet<j-pihet at ti.com>
---
 arch/arm/mach-davinci/cpuidle.c |   82 ++++++++++++++++-----------------------
 1 file changed, 33 insertions(+), 49 deletions(-)

diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index a30c7c5..93ae096 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -18,6 +18,7 @@
 #include <linux/io.h>
 #include <linux/export.h>
 #include <asm/proc-fns.h>
+#include <asm/cpuidle.h>
 
 #include <mach/cpuidle.h>
 #include <mach/ddr2.h>
@@ -30,12 +31,42 @@ struct davinci_ops {
 	u32 flags;
 };
 
+/* Actual code that puts the SoC in different idle states */
+static int davinci_enter_idle(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv,
+						int index)
+{
+	struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
+	struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
+
+	if (ops && ops->enter)
+		ops->enter(ops->flags);
+
+	index = cpuidle_wrap_enter(dev,	drv, index,
+				arm_cpuidle_simple_enter);
+
+	if (ops && ops->exit)
+		ops->exit(ops->flags);
+
+	return index;
+}
+
 /* fields in davinci_ops.flags */
 #define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN	BIT(0)
 
 static struct cpuidle_driver davinci_idle_driver = {
-	.name	= "cpuidle-davinci",
-	.owner	= THIS_MODULE,
+	.name		= "cpuidle-davinci",
+	.owner		= THIS_MODULE,
+	.states[0]	= ARM_CPUIDLE_WFI_STATE,
+	.states[1]	= {
+		.enter			= davinci_enter_idle,
+		.exit_latency		= 10,
+		.target_residency	= 100000,
+		.flags			= CPUIDLE_FLAG_TIME_VALID,
+		.name			= "DDR SR",
+		.desc			= "WFI and DDR Self Refresh",
+	},
+	.state_count = DAVINCI_CPUIDLE_MAX_STATES,
 };
 
 static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
@@ -77,41 +108,10 @@ static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
 	},
 };
 
-/* Actual code that puts the SoC in different idle states */
-static int davinci_enter_idle(struct cpuidle_device *dev,
-				struct cpuidle_driver *drv,
-						int index)
-{
-	struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
-	struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
-	struct timeval before, after;
-	int idle_time;
-
-	local_irq_disable();
-	do_gettimeofday(&before);
-
-	if (ops && ops->enter)
-		ops->enter(ops->flags);
-	/* Wait for interrupt state */
-	cpu_do_idle();
-	if (ops && ops->exit)
-		ops->exit(ops->flags);
-
-	do_gettimeofday(&after);
-	local_irq_enable();
-	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
-			(after.tv_usec - before.tv_usec);
-
-	dev->last_residency = idle_time;
-
-	return index;
-}
-
 static int __init davinci_cpuidle_probe(struct platform_device *pdev)
 {
 	int ret;
 	struct cpuidle_device *device;
-	struct cpuidle_driver *driver = &davinci_idle_driver;
 	struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
 
 	device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
@@ -123,27 +123,11 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
 
 	ddr2_reg_base = pdata->ddr2_ctlr_base;
 
-	/* Wait for interrupt state */
-	driver->states[0].enter = davinci_enter_idle;
-	driver->states[0].exit_latency = 1;
-	driver->states[0].target_residency = 10000;
-	driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
-	strcpy(driver->states[0].name, "WFI");
-	strcpy(driver->states[0].desc, "Wait for interrupt");
-
-	/* Wait for interrupt and DDR self refresh state */
-	driver->states[1].enter = davinci_enter_idle;
-	driver->states[1].exit_latency = 10;
-	driver->states[1].target_residency = 10000;
-	driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
-	strcpy(driver->states[1].name, "DDR SR");
-	strcpy(driver->states[1].desc, "WFI and DDR Self Refresh");
 	if (pdata->ddr2_pdown)
 		davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
 	cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]);
 
 	device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
-	driver->state_count = DAVINCI_CPUIDLE_MAX_STATES;
 
 	ret = cpuidle_register_driver(&davinci_idle_driver);
 	if (ret) {
-- 
1.7.9.4



From rob.lee at linaro.org  Tue Mar 20 16:22:46 2012
From: rob.lee at linaro.org (Robert Lee)
Date: Tue, 20 Mar 2012 15:22:46 -0500
Subject: [PATCH v8 5/8] ARM: omap: Consolidate OMAP3 time keeping and irq
 enable
In-Reply-To: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
Message-ID: <1332274969-15782-6-git-send-email-rob.lee@linaro.org>

Use core cpuidle timekeeping and irqen wrapper and remove that
handling from this code.

Signed-off-by: Robert Lee <rob.lee at linaro.org>
Reviewed-by: Kevin Hilman <khilman at ti.com>
Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Tested-by: Jean Pihet<j-pihet at ti.com>
Acked-by: Jean Pihet<j-pihet at ti.com>
---
 arch/arm/mach-omap2/cpuidle34xx.c |   42 +++++++++++++++----------------------
 1 file changed, 17 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 464cffd..5358664 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -87,29 +87,14 @@ static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
 	return 0;
 }
 
-/**
- * omap3_enter_idle - Programs OMAP3 to enter the specified state
- * @dev: cpuidle device
- * @drv: cpuidle driver
- * @index: the index of state to be entered
- *
- * Called from the CPUidle framework to program the device to the
- * specified target state selected by the governor.
- */
-static int omap3_enter_idle(struct cpuidle_device *dev,
+static int __omap3_enter_idle(struct cpuidle_device *dev,
 				struct cpuidle_driver *drv,
 				int index)
 {
 	struct omap3_idle_statedata *cx =
 			cpuidle_get_statedata(&dev->states_usage[index]);
-	struct timespec ts_preidle, ts_postidle, ts_idle;
 	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
-	int idle_time;
-
-	/* Used to keep track of the total time in idle */
-	getnstimeofday(&ts_preidle);
 
-	local_irq_disable();
 	local_fiq_disable();
 
 	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
@@ -148,22 +133,29 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 	}
 
 return_sleep_time:
-	getnstimeofday(&ts_postidle);
-	ts_idle = timespec_sub(ts_postidle, ts_preidle);
 
-	local_irq_enable();
 	local_fiq_enable();
 
-	idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
-								USEC_PER_SEC;
-
-	/* Update cpuidle counters */
-	dev->last_residency = idle_time;
-
 	return index;
 }
 
 /**
+ * omap3_enter_idle - Programs OMAP3 to enter the specified state
+ * @dev: cpuidle device
+ * @drv: cpuidle driver
+ * @index: the index of state to be entered
+ *
+ * Called from the CPUidle framework to program the device to the
+ * specified target state selected by the governor.
+ */
+static inline int omap3_enter_idle(struct cpuidle_device *dev,
+				struct cpuidle_driver *drv,
+				int index)
+{
+	return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
+}
+
+/**
  * next_valid_state - Find next valid C-state
  * @dev: cpuidle device
  * @drv: cpuidle driver
-- 
1.7.9.4



From rob.lee at linaro.org  Tue Mar 20 16:22:47 2012
From: rob.lee at linaro.org (Robert Lee)
Date: Tue, 20 Mar 2012 15:22:47 -0500
Subject: [PATCH v8 6/8] ARM: omap: Consolidate OMAP4 time keeping and irq
 enable
In-Reply-To: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
Message-ID: <1332274969-15782-7-git-send-email-rob.lee@linaro.org>

Enable core cpuidle timekeeping and irq enabling and remove that
handling from this code.

Signed-off-by: Robert Lee <rob.lee at linaro.org>
Reviewed-by: Kevin Hilman <khilman at ti.com>
Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Acked-by: Jean Pihet<j-pihet at ti.com>
---
 arch/arm/mach-omap2/cpuidle44xx.c |   21 +++------------------
 1 file changed, 3 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 72e018b..f386cbe 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -62,15 +62,9 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
 {
 	struct omap4_idle_statedata *cx =
 			cpuidle_get_statedata(&dev->states_usage[index]);
-	struct timespec ts_preidle, ts_postidle, ts_idle;
 	u32 cpu1_state;
-	int idle_time;
 	int cpu_id = smp_processor_id();
 
-	/* Used to keep track of the total time in idle */
-	getnstimeofday(&ts_preidle);
-
-	local_irq_disable();
 	local_fiq_disable();
 
 	/*
@@ -128,26 +122,17 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
 	if (index > 0)
 		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
 
-	getnstimeofday(&ts_postidle);
-	ts_idle = timespec_sub(ts_postidle, ts_preidle);
-
-	local_irq_enable();
 	local_fiq_enable();
 
-	idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
-								USEC_PER_SEC;
-
-	/* Update cpuidle counters */
-	dev->last_residency = idle_time;
-
 	return index;
 }
 
 DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
 
 struct cpuidle_driver omap4_idle_driver = {
-	.name =		"omap4_idle",
-	.owner =	THIS_MODULE,
+	.name				= "omap4_idle",
+	.owner				= THIS_MODULE,
+	.en_core_tk_irqen		= 1,
 };
 
 static inline void _fill_cstate(struct cpuidle_driver *drv,
-- 
1.7.9.4



From rob.lee at linaro.org  Tue Mar 20 16:22:48 2012
From: rob.lee at linaro.org (Robert Lee)
Date: Tue, 20 Mar 2012 15:22:48 -0500
Subject: [PATCH v8 7/8] ARM: shmobile: Consolidate time keeping and irq enable
In-Reply-To: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
Message-ID: <1332274969-15782-8-git-send-email-rob.lee@linaro.org>

Enable core cpuidle timekeeping and irq enabling and remove that
handling from this code.

Signed-off-by: Robert Lee <rob.lee at linaro.org>
Reviewed-by: Kevin Hilman <khilman at ti.com>
Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Acked-by: Jean Pihet<j-pihet at ti.com>
---
 arch/arm/mach-shmobile/cpuidle.c |   31 +++++++------------------------
 1 file changed, 7 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
index 1b23342..ca23b20 100644
--- a/arch/arm/mach-shmobile/cpuidle.c
+++ b/arch/arm/mach-shmobile/cpuidle.c
@@ -14,6 +14,7 @@
 #include <linux/module.h>
 #include <linux/err.h>
 #include <asm/system.h>
+#include <asm/cpuidle.h>
 #include <asm/io.h>
 
 static void shmobile_enter_wfi(void)
@@ -29,37 +30,19 @@ static int shmobile_cpuidle_enter(struct cpuidle_device *dev,
 				  struct cpuidle_driver *drv,
 				  int index)
 {
-	ktime_t before, after;
-
-	before = ktime_get();
-
-	local_irq_disable();
-	local_fiq_disable();
-
 	shmobile_cpuidle_modes[index]();
 
-	local_irq_enable();
-	local_fiq_enable();
-
-	after = ktime_get();
-	dev->last_residency = ktime_to_ns(ktime_sub(after, before)) >> 10;
-
 	return index;
 }
 
 static struct cpuidle_device shmobile_cpuidle_dev;
 static struct cpuidle_driver shmobile_cpuidle_driver = {
-	.name =		"shmobile_cpuidle",
-	.owner =	THIS_MODULE,
-	.states[0] = {
-		.name = "C1",
-		.desc = "WFI",
-		.exit_latency = 1,
-		.target_residency = 1 * 2,
-		.flags = CPUIDLE_FLAG_TIME_VALID,
-	},
-	.safe_state_index = 0, /* C1 */
-	.state_count = 1,
+	.name			= "shmobile_cpuidle",
+	.owner			= THIS_MODULE,
+	.en_core_tk_irqen	= 1,
+	.states[0]		= ARM_CPUIDLE_WFI_STATE,
+	.safe_state_index	= 0, /* C1 */
+	.state_count		= 1,
 };
 
 void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
-- 
1.7.9.4



From rob.lee at linaro.org  Tue Mar 20 16:22:49 2012
From: rob.lee at linaro.org (Robert Lee)
Date: Tue, 20 Mar 2012 15:22:49 -0500
Subject: [PATCH v8 8/8] SH: shmobile: Consolidate time keeping and irq enable
In-Reply-To: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
Message-ID: <1332274969-15782-9-git-send-email-rob.lee@linaro.org>

Enable core cpuidle timekeeping and irq enabling and remove that
handling from this code.

Signed-off-by: Robert Lee <rob.lee at linaro.org>
Reviewed-by: Kevin Hilman <khilman at ti.com>
Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
Acked-by: Jean Pihet<j-pihet at ti.com>
---
 arch/sh/kernel/cpu/shmobile/cpuidle.c |   10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index 6d62eb4..1ddc876 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -29,7 +29,6 @@ static int cpuidle_sleep_enter(struct cpuidle_device *dev,
 				int index)
 {
 	unsigned long allowed_mode = SUSP_SH_SLEEP;
-	ktime_t before, after;
 	int requested_state = index;
 	int allowed_state;
 	int k;
@@ -47,19 +46,16 @@ static int cpuidle_sleep_enter(struct cpuidle_device *dev,
 	 */
 	k = min_t(int, allowed_state, requested_state);
 
-	before = ktime_get();
 	sh_mobile_call_standby(cpuidle_mode[k]);
-	after = ktime_get();
-
-	dev->last_residency = (int)ktime_to_ns(ktime_sub(after, before)) >> 10;
 
 	return k;
 }
 
 static struct cpuidle_device cpuidle_dev;
 static struct cpuidle_driver cpuidle_driver = {
-	.name =		"sh_idle",
-	.owner =	THIS_MODULE,
+	.name			= "sh_idle",
+	.owner			= THIS_MODULE,
+	.en_core_tk_irqen	= 1,
 };
 
 void sh_mobile_setup_cpuidle(void)
-- 
1.7.9.4



From robherring2 at gmail.com  Tue Mar 20 17:33:38 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 20 Mar 2012 16:33:38 -0500
Subject: linux-next: "ARM: make mach/io.h include optional" commit breaks
 cm_x2xx_defconfig
In-Reply-To: <4F68CD9C.3090001@windriver.com>
References: <4F68CD9C.3090001@windriver.com>
Message-ID: <4F68F7B2.4000002@gmail.com>

On 03/20/2012 01:34 PM, Paul Gortmaker wrote:
> Hi Rob,
> 
> If you have a moment can you check this build failure?
> 
> http://kisskb.ellerman.id.au/kisskb/buildresult/5923845/
> 
> A git bisect seems to want to blame your commit for it.
> 

Thanks. I've got a fix done and am running some builds.

Rob

> Thanks,
> Paul.
> 
> ---
> 
> c334bc150524f833db3c76a0aaf55fb5044444e1 is the first bad commit
> commit c334bc150524f833db3c76a0aaf55fb5044444e1
> Author: Rob Herring <rob.herring at calxeda.com>
> Date:   Sun Mar 4 22:03:33 2012 -0600
> 
>     ARM: make mach/io.h include optional
> 
> 
> git bisect start
> # good: [fde7d9049e55ab85a390be7f415d74c9f62dd0f9] Linux 3.3-rc7
> git bisect good fde7d9049e55ab85a390be7f415d74c9f62dd0f9
> # bad: [f355e8684f7e8e7077ca6d3988f24e01047804b6] Add linux-next specific files for 20120320
> git bisect bad f355e8684f7e8e7077ca6d3988f24e01047804b6
> # good: [5fe35ba6690ea0136d649cb2a07ac3f64a4c3cfb] Merge remote-tracking branch 'sound/for-next'
> git bisect good 5fe35ba6690ea0136d649cb2a07ac3f64a4c3cfb
> # good: [5260d60f170ebd381538dd56f6f6b765cbf9db29] Merge remote-tracking branch 'tip/auto-latest'
> git bisect good 5260d60f170ebd381538dd56f6f6b765cbf9db29
> # good: [2eb0aaa70022cbd3cdac7bdb610ed79a3b0c60a7] Merge remote-tracking branch 'writeback/writeback-for-next'
> git bisect good 2eb0aaa70022cbd3cdac7bdb610ed79a3b0c60a7
> # bad: [da7499ed07635785926c4a12915f54c61dc44170] Merge branch 'next/clk' into for-next
> git bisect bad da7499ed07635785926c4a12915f54c61dc44170
> # good: [eae71abd0e6d466105c66a40115907335a3e20fa] Merge branch 'next/boards' into for-next
> git bisect good eae71abd0e6d466105c66a40115907335a3e20fa
> # good: [cdc3df6f44f72c5924a16a47e1663c3fb0e57820] Merge branch 'dt-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
> git bisect good cdc3df6f44f72c5924a16a47e1663c3fb0e57820
> # good: [f66f9bdf6d2c2b540f73bb57bd24b886b39beb14] Merge branch 'lpc32xx/drivers' into next/drivers
> git bisect good f66f9bdf6d2c2b540f73bb57bd24b886b39beb14
> # good: [e5412a49eceeab5b9ecb761b536ad7ac829e1c45] Merge branch 'next/dt' into for-next
> git bisect good e5412a49eceeab5b9ecb761b536ad7ac829e1c45
> # good: [efa497b9ec8cc534f8883a2d1d42f52174070f38] ARM: dove: add explicit include of dove.h to addr-map.c
> git bisect good efa497b9ec8cc534f8883a2d1d42f52174070f38
> # bad: [accf709b39a9cdbeaf6233000ccb9af966fd691e] Merge branch 'io-cleanup-for-3.4' of git://sources.calxeda.com/kernel/linux into next/cleanup2
> git bisect bad accf709b39a9cdbeaf6233000ccb9af966fd691e
> # bad: [708795cd975579ba7115666f585c428f8cebd572] Merge branch 'io-cleanup-for-3.4' of git://sources.calxeda.com/kernel/linux into next/cleanup2
> git bisect bad 708795cd975579ba7115666f585c428f8cebd572
> # bad: [c334bc150524f833db3c76a0aaf55fb5044444e1] ARM: make mach/io.h include optional
> git bisect bad c334bc150524f833db3c76a0aaf55fb5044444e1
> # good: [41e32c906054be3a600cdeb69eb70350066e0a91] ARM: clps711x: remove unneeded include of mach/io.h
> git bisect good 41e32c906054be3a600cdeb69eb70350066e0a91
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From arnd.bergmann at linaro.org  Tue Mar 20 17:58:07 2012
From: arnd.bergmann at linaro.org (Arnd Bergmann)
Date: Tue, 20 Mar 2012 21:58:07 +0000
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
Message-ID: <201203202158.08042.arnd.bergmann@linaro.org>

On Tuesday 20 March 2012, Robert Lee wrote:
> This patch series moves various functionality duplicated in platform 
> cpuidle drivers to the core cpuidle driver. Also, the platform irq
> disabling was removed as it appears that all calls into 
> cpuidle_call_idle will have already called local_irq_disable().
> 
> These changes have been pulled into linux-next.
> 
> Len, Andrew, can a request be made for Linus to pull these changes?

FWIW, Len seems to be rather inactive on the kernel mailing list right
now and generally not very interested in anything outside of x86 and
acpi. If he doesn't reply in the next few days and Andrew also isn't
interested in handling these patches, I'd suggest you just send the pull
request to Linus, with Len on Cc and explain that you tried to send
them through him but gave up in the end.

	Arnd


From s.hauer at pengutronix.de  Tue Mar 20 18:40:21 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 20 Mar 2012 23:40:21 +0100
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <4F68E53B.7040800@codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <e22898bc8b69e85f1e6390d7d858f85c.squirrel@www.codeaurora.org>
 <20120320181441.GO3852@pengutronix.de>
 <4F68E53B.7040800@codeaurora.org>
Message-ID: <20120320224021.GF29317@pengutronix.de>

On Tue, Mar 20, 2012 at 01:14:51PM -0700, Saravana Kannan wrote:
> On 03/20/2012 11:14 AM, Sascha Hauer wrote:
> >On Tue, Mar 20, 2012 at 03:17:10AM -0700, Saravana Kannan wrote:
> >>
> >>On Tue, March 20, 2012 2:40 am, Sascha Hauer wrote:
> >>>On Tue, Mar 20, 2012 at 12:54:55AM -0700, Saravana Kannan wrote:
> >>>>
> >>>I am using these functions and don't need a static array, I just call
> >>>the functions with the desired parameters.
> >>
> >>Sure, then let's leave it in. Curious, where do you get the desired
> >>parameters from? Is it static date in code or is it from DT? You somehow
> >>probe it?
> >
> >It's not from DT. See this thread:
> >
> >http://www.spinics.net/lists/arm-kernel/msg165839.html
> 
> Ah, I see. That's a lot of functions calls. I think it would be much
> more efficient if you just have an array and loop over it. With my
> patch, you can just call a single register function for all these
> clocks.

I was curious and gave it a try. I registered a fixed clock and 100
gates as child clocks. I tried both DEFINE_CLK_GATE and
clk_register_gate. It turned out there was no difference in speed.

> 
> >
> >The difference is that a struct clk_initializer is only used to
> >initialize a clock and not actively used by the clock framework. But as
> >you already mentioned using a copy inside the clock framework has the
> >same effect.
> 
> My opinion on this is to follow a wait and watch approach on the
> "flags" field. I really can't think of a safe way anyone can misuse
> it. If people start doing that, we can just do the copy and let them
> deal with their broken code. Until that happens, I don't want to
> waste time/space by copying it. The rest of the fields aren't
> actively used by the common clock code after init.

Actually you will save space by copying it because you can put the
initializers in __initdata and throw the initializers of unused SoCs
compiled into the kernel away during runtime.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From tony at atomide.com  Tue Mar 20 18:17:02 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 20 Mar 2012 15:17:02 -0700
Subject: [PATCH v2 7/7] ARM: OMAP2+: Mark omap_hsmmc_init and omap_mux
 related functions as __init
In-Reply-To: <1332228651.2409.5.camel@lappy>
References: <1329997247-27342-1-git-send-email-rnayak@ti.com>
 <1329997247-27342-8-git-send-email-rnayak@ti.com>
 <1332148116.2144.1.camel@deskari>
 <1332152442.2144.27.camel@deskari>
 <20120319180928.GA9859@atomide.com> <1332228651.2409.5.camel@lappy>
Message-ID: <20120320221701.GI9859@atomide.com>

* Tomi Valkeinen <tomi.valkeinen at ti.com> [120320 00:41]:
> On Mon, 2012-03-19 at 11:09 -0700, Tony Lindgren wrote:
> 
> > I've updated your patch a bit for the comments a bit and marked
> > omap4_hdmi_mux_pads as __init, will apply to fixes. Updated patch
> > below.
> 
> Hmm, is there something funny with these init changes now...
> 
> Initially the situation was that there were no __inits in display.c's
> mux functions. Then "Mark omap_hsmmc_init..." patch added __inits to all
> of them. My patch removed the __inits from dsi functions, but left them
> to hdmi functions.
> 
> But now you modified my patch to add the __inits to hdmi functions.
> Which should already have them from the "Mark omap_hsmmc_init..." patch.

Looks like the original patch missed making omap4_hdmi_mux_pads __init
though. I'm just changing omap4_hdmi_mux_pads to make it __init like
it should be.

Regards,

Tony


From khilman at ti.com  Tue Mar 20 18:48:45 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 20 Mar 2012 15:48:45 -0700
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <201203202158.08042.arnd.bergmann@linaro.org> (Arnd Bergmann's
 message of "Tue, 20 Mar 2012 21:58:07 +0000")
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <201203202158.08042.arnd.bergmann@linaro.org>
Message-ID: <873992zy5u.fsf@ti.com>

Arnd Bergmann <arnd.bergmann at linaro.org> writes:

> On Tuesday 20 March 2012, Robert Lee wrote:
>> This patch series moves various functionality duplicated in platform 
>> cpuidle drivers to the core cpuidle driver. Also, the platform irq
>> disabling was removed as it appears that all calls into 
>> cpuidle_call_idle will have already called local_irq_disable().
>> 
>> These changes have been pulled into linux-next.
>> 
>> Len, Andrew, can a request be made for Linus to pull these changes?
>
> FWIW, Len seems to be rather inactive on the kernel mailing list right
> now and generally not very interested in anything outside of x86 and
> acpi. If he doesn't reply in the next few days and Andrew also isn't
> interested in handling these patches, I'd suggest you just send the pull
> request to Linus, with Len on Cc and explain that you tried to send
> them through him but gave up in the end.

FWIW, I have not had good luck getting response for proposed core
CPUidle changes either:

        http://lkml.org/lkml/2011/9/19/374

Maybe it's time that drivers/cpuidle gets a maintainer.  With lots of
discussions of scheduler changes that affect load estimation, I suspect
we're all going to have a bit of CPUidle work to do in the
not-so-distant future.
 
Kevin


From arnd.bergmann at linaro.org  Tue Mar 20 19:05:37 2012
From: arnd.bergmann at linaro.org (Arnd Bergmann)
Date: Tue, 20 Mar 2012 23:05:37 +0000
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <873992zy5u.fsf@ti.com>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <201203202158.08042.arnd.bergmann@linaro.org> <873992zy5u.fsf@ti.com>
Message-ID: <201203202305.37952.arnd.bergmann@linaro.org>

On Tuesday 20 March 2012, Kevin Hilman wrote:
> Maybe it's time that drivers/cpuidle gets a maintainer.  With lots of
> discussions of scheduler changes that affect load estimation, I suspect
> we're all going to have a bit of CPUidle work to do in the
> not-so-distant future.

Hmm, according to the script, you are the maintainer ;-)

$ scripts/get_maintainer.pl -f drivers/cpuidle/cpuidle.c
Kevin Hilman <khilman at ti.com> (commit_signer:8/10=80%)
Len Brown <len.brown at intel.com> (commit_signer:7/10=70%)
Trinabh Gupta <g.trinabh at gmail.com> (commit_signer:4/10=40%)
Arjan van de Ven <arjan at linux.intel.com> (commit_signer:4/10=40%)
Deepthi Dharwar <deepthi at linux.vnet.ibm.com> (commit_signer:4/10=40%)

While I realize that the get_maintainers.pl is not the final word,
you could be the acting cpuidle maintainer for this merge window
and send the pull request.

	Arnd


From amit.kucheria at linaro.org  Tue Mar 20 19:06:46 2012
From: amit.kucheria at linaro.org (Amit Kucheria)
Date: Wed, 21 Mar 2012 01:06:46 +0200
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <873992zy5u.fsf@ti.com>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <201203202158.08042.arnd.bergmann@linaro.org>
 <873992zy5u.fsf@ti.com>
Message-ID: <CAP245DXwhCMOJaspW8SY7jtqsA3d5SK4Ctr+JvS+cw4yHfL-mw@mail.gmail.com>

On Wed, Mar 21, 2012 at 12:48 AM, Kevin Hilman <khilman at ti.com> wrote:
> Arnd Bergmann <arnd.bergmann at linaro.org> writes:
>
>> On Tuesday 20 March 2012, Robert Lee wrote:
>>> This patch series moves various functionality duplicated in platform
>>> cpuidle drivers to the core cpuidle driver. Also, the platform irq
>>> disabling was removed as it appears that all calls into
>>> cpuidle_call_idle will have already called local_irq_disable().
>>>
>>> These changes have been pulled into linux-next.
>>>
>>> Len, Andrew, can a request be made for Linus to pull these changes?
>>
>> FWIW, Len seems to be rather inactive on the kernel mailing list right
>> now and generally not very interested in anything outside of x86 and
>> acpi. If he doesn't reply in the next few days and Andrew also isn't
>> interested in handling these patches, I'd suggest you just send the pull
>> request to Linus, with Len on Cc and explain that you tried to send
>> them through him but gave up in the end.
>
> FWIW, I have not had good luck getting response for proposed core
> CPUidle changes either:
>
> ? ? ? ?http://lkml.org/lkml/2011/9/19/374
>
> Maybe it's time that drivers/cpuidle gets a maintainer. ?With lots of
> discussions of scheduler changes that affect load estimation, I suspect
> we're all going to have a bit of CPUidle work to do in the
> not-so-distant future.
>

I don't mean to be piling on to Len here, but Daniel Lezcano too has a
bunch of clean ups that didn't get any maintainer review for over two
months. He has now refreshed them for 3.3 and is getting ready to send
them out again. We (Linaro) expect to be spending a lot of time on
cpuidle in the future and would be glad to help review, test and
collect patches into a tree for Linus/Andrew to pull while we wait for
Len to respond or another maintainer to emerge.

/Amit


From s.hauer at pengutronix.de  Tue Mar 20 19:12:42 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 21 Mar 2012 00:12:42 +0100
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <4F68E34A.70207@codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <20120320141811.GF32469@S2101-09.ap.freescale.net>
 <20120320181050.GN3852@pengutronix.de>
 <4F68E34A.70207@codeaurora.org>
Message-ID: <20120320231242.GP3852@pengutronix.de>

On Tue, Mar 20, 2012 at 01:06:34PM -0700, Saravana Kannan wrote:
> On 03/20/2012 11:10 AM, Sascha Hauer wrote:
> >On Tue, Mar 20, 2012 at 10:18:14PM +0800, Shawn Guo wrote:
> >>On Tue, Mar 20, 2012 at 10:40:31AM +0100, Sascha Hauer wrote:
> >>...
> >>>I am using these functions and don't need a static array, I just call
> >>>the functions with the desired parameters.
> >>>
> >>With this patch getting in, you do not have to use them then.  I feel
> >>a static array will be much more readable than a long list of function
> >>calls with a long list of hardcoded arguments to each.
> >
> >I'm also not a fan of long argument lists; a divider like defined in my
> >tree takes 5 arguments, a gate 4 and a mux 6. While 6 is already at the
> >border I think it's still acceptable.
> >
> >What I like in terms of readability is one line per clock which makes
> >for quite short clock files.
> 
> It certainly makes for short clock files, but it's definitely less
> readable that the expanded struct. For the original author the "one
> line per clock" looks readable since they wrote it. But for someone
> looking at the code to modify it, the expanded one would be much
> easier to read. Also, you can always declare your own macro if you
> really want to follow the one line approach.
> 
> >So when we use structs to initialize the clocks we'll probably have
> >something like this:
> >
> >static struct clk_divider somediv = {
> >	.reg = CCM_BASE + 0x14,
> >	.width = 3,
> >	.shift = 17,
> >	.lock =&ccm_lock,
> >	.hw.parent = "someotherdiv",
> >	.hw.flags = CLK_SET_RATE_PARENT,
> >};
> 
> Taken from your patches:
> 
> imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
> ARRAY_SIZE(spll_sel_clks));
> 
> Compare the struct to the one line call. Now tell me, what does "1"
> represent? No clue. But in the struct, I can immediately tell what
> each one of the parameters are.
> 
> Anyway, my patch certainly isn't forcing you to use multiple lines.
> So, hopefully this won't be a point of contention.
> 
> >This will make a 4000 line file out of a 500 line file. Now when for
> >some reason struct clk_divider changes we end with big patches. If the
> >clk core gets a new fancy CLK_ flag which we want to have then again
> >we end up with big patches. Then there's also the possibility that
> >someone finds out that .lock and .hw.flags are common to all dividers
> >and comes up with a #define DEFINE_CLK_DIVIDER again to share common
> >fields.
> 
> This patch won't prevent you from doing any of that. You can still
> create macros for that (there are already one for that). Also, what
> you are pointing out is a bigger problem for the current
> clk_register() function since you might have to change the no. of
> params of all the callers even if a new field is optional.
> 
> >All this can be solved when we introduce a small wrapper function and
> >use it in the clock files:
> >
> >static inline struct clk *imx_clk_divider(const char *name, const char *parent,
> >		void __iomem *reg, u8 shift, u8 width)
> >{
> >	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
> >			reg, shift, width, 0,&imx_ccm_lock);
> >}
> >
> >It decouples us from the structs used by the clock framework, we can
> >add our preferred flags and still can share common fields like the lock.
> >
> >While this was not the intention when I first converted from struct
> >initializers to function initializers I am confident that it will make
> >a good job.
> 
> Now I'm confused -- it's not clear if you are leaning towards my
> patch or away from it?

There was a tendency to get rid of static initializers and I like the
idea of not exposing any of the internally used members outside the
clock framework.
Now people try their best to make themselves comfortable with the
static initializers and you even discussed the possibility of removing
the clk_register_* functions (which make it possible for users not
to use any of the internal struct members). That's what I don't like
about your patches. But if we go for static initializers anyway then your
patches probably change things for the better.

Sascha

-- 
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From mturquette at ti.com  Tue Mar 20 19:27:28 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 20 Mar 2012 16:27:28 -0700
Subject: i.MX: Convert v4/v5 based SoCs to common clock framework
In-Reply-To: <4F674659.40207@gmail.com>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
 <4F674659.40207@gmail.com>
Message-ID: <CAJOA=zPXJL_ssa0M4SG3iN5xH=6MfWD0N3A29H5Ek26L4VORZw@mail.gmail.com>

On Mon, Mar 19, 2012 at 7:44 AM, Rob Herring <robherring2 at gmail.com> wrote:
> Do we want to move all clock code to drivers/clk? I'm not saying it has
> to be done now, but is that a goal?

My knee jerk response is to say "no".  Back in January a similar topic
came up for the AT91 CPUidle driver migrating to drivers/cpuidle/.
See Russell's reply here:
http://article.gmane.org/gmane.linux.ports.arm.kernel/147849

If a platform's clock code lives in a silo and is nicely walled off
from other platform-specific bits then migration to drivers/clk/ is
possible.  In practice I think that more complex clock code and data
will have a hard time doing so.  Even the simple task of sharing a
header which exposes commonly used register addresses, offsets and
widths starts to get complicated when some of the code/data that uses
it lives in arch/* and some of it lives in drivers/*

Regards,
Mike


From paul at pwsan.com  Tue Mar 20 19:31:33 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 20 Mar 2012 17:31:33 -0600 (MDT)
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <20120316234706.GJ3852@pengutronix.de>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <20120316234706.GJ3852@pengutronix.de>
Message-ID: <alpine.DEB.2.00.1203201611330.22974@utopia.booyaka.com>

Hello Sascha,

On Sat, 17 Mar 2012, Sascha Hauer wrote:

> On Fri, Mar 16, 2012 at 04:21:17PM -0600, Paul Walmsley wrote:
>  
> > If the common clock code is to go upstream now, it should be marked as 
> > experimental.
> 
> No, please don't do this. This effectively marks the architectures using
> the generic clock framework experimental. We can mark drivers as 'you
> have been warned', but marking an architecture as experimental is the
> wrong sign for both its users and people willing to adopt the framework.
> Also we get this:
> 
> warning: (ARCH_MX1 && MACH_MX21 && ARCH_MX25 && MACH_MX27) selects COMMON_CLK which has unmet direct dependencies (EXPERIMENTAL)
> 
> (and no, I don't want to support to clock frameworks in parallel)

It sounds as if your objection is with CONFIG_EXPERIMENTAL.  If that is 
indeed your objection, I personally have no objection to simply marking 
the code experimental in the Kconfig text.  (Patch at the bottom of this 
message.)

We need to indicate in some way that the existing code and API is very 
likely to change in ways that could involve quite a bit of work for 
adopters.

> > This is because we know the API is not well-defined, and 
> > that both the API and the underlying mechanics will almost certainly need 
> > to change for non-trivial uses of the rate changing code (e.g., DVFS with 
> > external I/O devices).
> 
> Please leave DVFS out of the game. DVFS will use the clock framework for
> the F part and the regulator framework for the V part, but the clock
> framework should not get extended with DVFS features. The notifiers we
> currently have in the clock framework should give enough information
> for DVFS implementations.

Sadly, that's not so.

Consider a CPUFreq driver as one common clock framework user.  This driver 
will attempt to repeatedly change the rate of a clock.  Changing that 
clock's rate may also involve changing the rate of several other clocks 
used by active devices.  So drivers for these devices will need to 
register rate change notifiers.  The notifier callbacks might involve 
heavyweight work, such as asserting flow control to an 
externally-connected device.

Suppose now that the last registered device in the notifier chain cannot 
handle the frequency transition and must abort it.  This in turn will 
require notifier callbacks to all of the previously-notified devices to 
abort the change.  And then shortly after that, CPUFreq is likely to 
request the same frequency change again: hammering a notifier chain that 
can never succeed.

Bad enough.  We know at least one way to solve this problem.  We can use 
something like the clk_{block,allow}_changes() functions that have been 
discussed for some time now.  But these quickly reveal another problem in 
the existing API.  By default, when there are multiple enabled users of a 
clock, another entity is allowed to change the clock's rate, or the rate 
of any parent of that clock (!).

This has several implications.  One that is significant is that for any 
non-trivial clock tree, any driver that cares about its clock's rate will 
need to implement notifier callbacks.  This is because the driver has no 
way of knowing if or when any other code on the system will attempt to 
change that clock's rate or source.  Or any parent clock's rate or source 
might change.  Should we really force all current drivers using the clock 
code to implement these callbacks?  Or can we restrict the situations in 
which the clock's rate or parent can change by placing restrictions on the 
API?  But then, driver code may need to be rewritten, and behavior 
assumptions may change.

> Even if they don't and we have to change something here this will have 
> no influence on the architectures implementing their clock tree with the 
> common clock framework.

That sounds pretty confident.  Are you sure that the semantics are so well 
understood?

For example, should we allow clk_set_rate() on disabled clocks?  How about 
prepared, but disabled clocks?  If so, what exactly should the clock 
framework do in these circumstances?  Should notifier callbacks go out 
immediately to registered callbacks?  Or should those callbacks be delayed 
until the clock is prepared or enabled?  How should that work when 
clk_enable() cannot block?  And are you confident that any other user of 
the clock framework will answer these undefined questions in the same way 
you would?

The above questions are simply "scratching the surface."  (Just as 
examples, there are still significant questions about locking, reentrancy, 
and so on - [1] is just one example)

These questions have reasonable answers that I think can be mostly aligned 
on.  Thinking through the use-cases, and implications, and answering them, 
should have been the first task in working on the common clock code.  I am 
sorry to say -- and perhaps this is partially my fault -- that it seems as 
if most people are not even aware that these questions exist, despite 
discussions at several conferences and on the mailing lists.

Anyway.  It is okay if we want to have some starter common clock framework 
in mainline; this is why deferring the merge hasn't been proposed.  But 
the point is that anyone who bases their code or platform on the common 
clock framework needs to be aware that, to satisfy one of its major 
use-cases, the behavior and/or API of the common clock code may need to 
change significantly.

Explicitly stating this is not only simple courtesy to its users, many of 
whom won't have been privy to its development.  It also is intended to 
make the code easier to change once it reaches mainline.  Once several 
platforms start using it, there will naturally be resistance and 
conservatism in changing its semantics and interface.  Many drivers may 
have to be changed, across many different maintainers.  And power 
management code may well need to be revalidated on the platforms that use 
it.  PM code, in my opinion, is generally the most difficult code to debug 
in the kernel.

So, until the API is well-defined and does all that it needs to do for its 
major users, we should at least have something like the following patch 
applied.


- Paul

1. King, Russell.  _Re: [PATCH v3 3/5] clk: introduce the common clock 
framework_.  2 Dec 2011 20:23:06 +0000.  linux-omap mailing list.  
http://www.spinics.net/lists/linux-omap/msg61024.html


From: Paul Walmsley <paul at pwsan.com>
Date: Tue, 20 Mar 2012 17:19:06 -0600
Subject: [PATCH] clk: note that the common clk code is still subject to
 significant change

Indicate that the common clk code and API is still likely to require
significant change.  The API is not well-defined and both it and the
underlying mechanics are likely to need significant changes to support
non-trivial uses of the rate changing code, such as DVFS with external
I/O devices.  So any platforms that switch their implementation over
to this may need to revise much of their driver code and revalidate
their implementations until the behavior of the code is
better-defined.

A good time for removing this help text would be after at least two
platforms that do DVFS on groups of external I/O devices have ported
their clock implementations over to the common clk code.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Mike Turquette <mturquette at ti.com>
---
 drivers/clk/Kconfig |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 2eaf17e..dd2d528 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -21,6 +21,11 @@ menuconfig COMMON_CLK
 	  this option for loadable modules requiring the common clock
 	  framework.
 
+	  The API and implementation enabled by this option is still
+	  incomplete.  The API and implementation is expected to be
+	  fluid and subject to change at any time, potentially
+	  breaking existing users.
+
 	  If in doubt, say "N".
 
 if COMMON_CLK
-- 
1.7.9.1



From paul at pwsan.com  Tue Mar 20 19:40:02 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 20 Mar 2012 17:40:02 -0600 (MDT)
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <201203170905.33191.arnd@arndb.de>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <CAJOA=zPmy7Dwzw8EOCW_+cvy2Dv=w0TPUq7Zg_s=Y0rs+v+u2w@mail.gmail.com>
 <201203170905.33191.arnd@arndb.de>
Message-ID: <alpine.DEB.2.00.1203201731550.22974@utopia.booyaka.com>

Hello Arnd,

On Sat, 17 Mar 2012, Arnd Bergmann wrote:

> I think it's rather pointless, because the option is not going to
> be user selectable but will get selected by the platform unless I'm
> mistaken. The platform maintainers that care already know the state
> of the framework.

This is where we have differing views, I think.  Clearly, Sascha, 
Saravana, Rob, and I have at least slightly different opinions on the 
durability of the existing API and code.  So it seems reasonable to assume 
that others who have not followed the development of the common clock code 
might mistake the implementation or API as being stable and well-defined.

It sounds like the primary objection is to the use of CONFIG_EXPERIMENTAL.  
So here is a patch to simply note the status of this code in its Kconfig 
text.


- Paul

From: Paul Walmsley <paul at pwsan.com>
Date: Tue, 20 Mar 2012 17:19:06 -0600
Subject: [PATCH] clk: note that the common clk code is still subject to
 significant change

Indicate that the common clk code and API is still likely to require
significant change.  The API is not well-defined and both it and the
underlying mechanics are likely to need significant changes to support
non-trivial uses of the rate changing code, such as DVFS with external
I/O devices.  So any platforms that switch their implementation over
to this may need to revise much of their driver code and revalidate
their implementations until the behavior of the code is
better-defined.

A good time for removing this help text would be after at least two
platforms that do DVFS on groups of external I/O devices have ported
their clock implementations over to the common clk code.

Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Mike Turquette <mturquette at ti.com>
---
 drivers/clk/Kconfig |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 2eaf17e..dd2d528 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -21,6 +21,11 @@ menuconfig COMMON_CLK
 	  this option for loadable modules requiring the common clock
 	  framework.
 
+	  The API and implementation enabled by this option is still
+	  incomplete.  The API and implementation is expected to be
+	  fluid and subject to change at any time, potentially
+	  breaking existing users.
+
 	  If in doubt, say "N".
 
 if COMMON_CLK
-- 
1.7.9.1



From mturquette at ti.com  Tue Mar 20 19:46:38 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 20 Mar 2012 16:46:38 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <20120320140220.GE32469@S2101-09.ap.freescale.net>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
Message-ID: <CAJOA=zOZ=XNwhEwUSD34AERi+f8fnMqG9EmS5hxCx+2u8qnkgw@mail.gmail.com>

On Tue, Mar 20, 2012 at 7:02 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Thu, Mar 15, 2012 at 11:11:19PM -0700, Mike Turquette wrote:
> ...
>> +struct clk_ops {
>> + ? ? int ? ? ? ? ? ? (*prepare)(struct clk_hw *hw);
>> + ? ? void ? ? ? ? ? ?(*unprepare)(struct clk_hw *hw);
>> + ? ? int ? ? ? ? ? ? (*enable)(struct clk_hw *hw);
>> + ? ? void ? ? ? ? ? ?(*disable)(struct clk_hw *hw);
>> + ? ? int ? ? ? ? ? ? (*is_enabled)(struct clk_hw *hw);
>> + ? ? unsigned long ? (*recalc_rate)(struct clk_hw *hw,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long parent_rate);
>
> I believe I have heard people love the interface with parent_rate
> passed in. ?I love that too. ?But I would like to ask the same thing
> on .round_rate and .set_rate as well for the same reason why we have
> it for .recalc_rate.

This is something that was discussed on the list but not taken in due
to rapid flux in code.  I always liked the idea however.

>
>> + ? ? long ? ? ? ? ? ?(*round_rate)(struct clk_hw *hw, unsigned long,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long *);
>
> Yes, we already have parent_rate passed in .round_rate with an pointer.
> But I think it'd be better to have it passed in no matter flag
> CLK_SET_RATE_PARENT is set or not. ?Something like:

This places the burden of checking the flags onto the .round_rate
implementation with __clk_get_flags, but that's not a problem really.

>
> 8<---
> @@ -584,7 +584,7 @@ EXPORT_SYMBOL_GPL(clk_get_rate);
> ?*/
> ?unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
> ?{
> - ? ? ? unsigned long unused;
> + ? ? ? unsigned long parent_rate = 0;
>
> ? ? ? ?if (!clk)
> ? ? ? ? ? ? ? ?return -EINVAL;
> @@ -592,10 +592,10 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
> ? ? ? ?if (!clk->ops->round_rate)
> ? ? ? ? ? ? ? ?return clk->rate;
>
> - ? ? ? if (clk->flags & CLK_SET_RATE_PARENT)
> - ? ? ? ? ? ? ? return clk->ops->round_rate(clk->hw, rate, &unused);
> - ? ? ? else
> - ? ? ? ? ? ? ? return clk->ops->round_rate(clk->hw, rate, NULL);
> + ? ? ? if (clk->parent)
> + ? ? ? ? ? ? ? parent_rate = clk->parent->rate;
> +
> + ? ? ? return clk->ops->round_rate(clk->hw, rate, &parent_rate);
> ?}
>
> ?/**
> @@ -765,9 +765,12 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
> ?static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
> ?{
> ? ? ? ?struct clk *top = clk;
> - ? ? ? unsigned long best_parent_rate = clk->parent->rate;
> + ? ? ? unsigned long best_parent_rate = 0;
> ? ? ? ?unsigned long new_rate;
>
> + ? ? ? if (clk->parent)
> + ? ? ? ? ? ? ? best_parent_rate = clk->parent->rate;
> +
> ? ? ? ?if (!clk->ops->round_rate && !(clk->flags & CLK_SET_RATE_PARENT)) {
> ? ? ? ? ? ? ? ?clk->new_rate = clk->rate;
> ? ? ? ? ? ? ? ?return NULL;
> @@ -780,10 +783,7 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
> ? ? ? ? ? ? ? ?goto out;
> ? ? ? ?}
>
> - ? ? ? if (clk->flags & CLK_SET_RATE_PARENT)
> - ? ? ? ? ? ? ? new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
> - ? ? ? else
> - ? ? ? ? ? ? ? new_rate = clk->ops->round_rate(clk->hw, rate, NULL);
> + ? ? ? new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
>
> ? ? ? ?if (best_parent_rate != clk->parent->rate) {
> ? ? ? ? ? ? ? ?top = clk_calc_new_rates(clk->parent, best_parent_rate);
>
> --->8

ACK

>
> The reason behind the change is that any clk implements .round_rate will
> mostly need to get the parent rate, no matter flag CLK_SET_RATE_PARENT
> is set or not. ?Instead of expecting every .round_rate implementation
> to get the parent rate in the way beloe
>
> ? ? ? ? parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
>
> we can just pass the parent rate into .round_rate.
>
>> + ? ? int ? ? ? ? ? ? (*set_parent)(struct clk_hw *hw, u8 index);
>> + ? ? u8 ? ? ? ? ? ? ?(*get_parent)(struct clk_hw *hw);
>> + ? ? int ? ? ? ? ? ? (*set_rate)(struct clk_hw *hw, unsigned long);
>
> For the same reason, I would change .set_rate interface like below.
>
> 8<---
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index d5ac6a7..6bd8037 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -119,7 +119,8 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
> ?}
> ?EXPORT_SYMBOL_GPL(clk_divider_round_rate);
>
> -static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
> +static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long parent_rate)
> ?{
> ? ? ? ?struct clk_divider *divider = to_clk_divider(hw);
> ? ? ? ?unsigned int div;
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index dbc310a..d74ac4b 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -833,17 +833,18 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even
> ?static void clk_change_rate(struct clk *clk)
> ?{
> ? ? ? ?struct clk *child;
> - ? ? ? unsigned long old_rate;
> + ? ? ? unsigned long old_rate, parent_rate = 0;
> ? ? ? ?struct hlist_node *tmp;
>
> ? ? ? ?old_rate = clk->rate;
> + ? ? ? if (clk->parent)
> + ? ? ? ? ? ? ? parent_rate = clk->parent->rate;
>
> ? ? ? ?if (clk->ops->set_rate)
> - ? ? ? ? ? ? ? clk->ops->set_rate(clk->hw, clk->new_rate);
> + ? ? ? ? ? ? ? clk->ops->set_rate(clk->hw, clk->new_rate, parent_rate);
>
> ? ? ? ?if (clk->ops->recalc_rate)
> - ? ? ? ? ? ? ? clk->rate = clk->ops->recalc_rate(clk->hw,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? clk->parent->rate);
> + ? ? ? ? ? ? ? clk->rate = clk->ops->recalc_rate(clk->hw, parent_rate);
> ? ? ? ?else
> ? ? ? ? ? ? ? ?clk->rate = clk->parent->rate;
>
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 5508897..1031f1f 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -125,7 +125,8 @@ struct clk_ops {
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long *);
> ? ? ? ?int ? ? ? ? ? ? (*set_parent)(struct clk_hw *hw, u8 index);
> ? ? ? ?u8 ? ? ? ? ? ? ?(*get_parent)(struct clk_hw *hw);
> - ? ? ? int ? ? ? ? ? ? (*set_rate)(struct clk_hw *hw, unsigned long);
> + ? ? ? int ? ? ? ? ? ? (*set_rate)(struct clk_hw *hw, unsigned long,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long);
> ? ? ? ?void ? ? ? ? ? ?(*init)(struct clk_hw *hw);
> ?};
>
> --->8

ACK

>
> Then with parent rate passed into .round_rate and .set_rate like what
> we do with .recalc_rate right now, we can save particular clk
> implementation from calling __clk_get_parent() and __clk_get_rate to
> get parent rate.
>
> For example, the following will the be diff we gain on clk-divider.
>
> 8<---
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 6bd8037..8a28ffb 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -68,8 +68,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
> ? ? ? ?if (divider->flags & CLK_DIVIDER_ONE_BASED)
> ? ? ? ? ? ? ? ?maxdiv--;
>
> - ? ? ? if (!best_parent_rate) {
> - ? ? ? ? ? ? ? parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
> + ? ? ? if (!(divider->flags & CLK_SET_RATE_PARENT)) {

This is wrong.  CLK_SET_RATE_PARENT is a common clock flag applied to
struct clk's .flags member, not the divider.  This function must still
use __clk_get_flags(hw->clk) here, but that's OK.

> + ? ? ? ? ? ? ? parent_rate = *best_parent_rate;
> ? ? ? ? ? ? ? ?bestdiv = DIV_ROUND_UP(parent_rate, rate);
> ? ? ? ? ? ? ? ?bestdiv = bestdiv == 0 ? 1 : bestdiv;
> ? ? ? ? ? ? ? ?bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
> @@ -109,13 +109,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
> ? ? ? ?int div;
> ? ? ? ?div = clk_divider_bestdiv(hw, rate, prate);
>
> - ? ? ? if (prate)
> - ? ? ? ? ? ? ? return *prate / div;
> - ? ? ? else {
> - ? ? ? ? ? ? ? unsigned long r;
> - ? ? ? ? ? ? ? r = __clk_get_rate(__clk_get_parent(hw->clk));
> - ? ? ? ? ? ? ? return r / div;
> - ? ? ? }
> + ? ? ? return *prate / div;
> ?}
> ?EXPORT_SYMBOL_GPL(clk_divider_round_rate);
>
> @@ -127,7 +121,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
> ? ? ? ?unsigned long flags = 0;
> ? ? ? ?u32 val;
>
> - ? ? ? div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate;
> + ? ? ? div = parent_rate / rate;
>
> ? ? ? ?if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
> ? ? ? ? ? ? ? ?div--;
>
> --->8

ACK, besides my comment above.

>
> I always get a sense of worry in using functions named in __xxx which
> sounds like something somehow internal. ?With the requested interface
> change above, I can get all __xxx functions out of my clk_ops
> implementation.

As mentioned above, you'll still need to check for CLK_SET_RATE_PARENT
in your .round_rate implementation with __clk_get_flags(hw->clk).

Did you want to send a formal patch or just have me absorb this into
the fixes I'm brewing already?  I've already fixed the potential null
ptr dereferences in clk_calc_new_rates, but that's no big deal.

Regards,
Mike


From paul at pwsan.com  Tue Mar 20 19:47:42 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 20 Mar 2012 17:47:42 -0600 (MDT)
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <20120320181050.GN3852@pengutronix.de>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <20120320141811.GF32469@S2101-09.ap.freescale.net>
 <20120320181050.GN3852@pengutronix.de>
Message-ID: <alpine.DEB.2.00.1203201740470.22974@utopia.booyaka.com>

Hello Sascha

On Tue, 20 Mar 2012, Sascha Hauer wrote:

> [ C99 structure initializer elided ]
> 
> This will make a 4000 line file out of a 500 line file. Now when for
> some reason struct clk_divider changes we end with big patches. If the
> clk core gets a new fancy CLK_ flag which we want to have then again
> we end up with big patches. Then there's also the possibility that
> someone finds out that .lock and .hw.flags are common to all dividers
> and comes up with a #define DEFINE_CLK_DIVIDER again to share common
> fields.

At least we can understand easily what is being changed.  Readability, 
particularly by others not familiar with the clock data, is more important 
to me.

So like Saravana, I too prefer C99 structure initializers.  At least there 
should be a choice.

Quick quiz: in this line below:

imx_clk_divider("foo_clk", "bar_clk", CCM_BASE + 0x20, 0x5, 0x3);

which field is the bitfield shift and which is the bitfield width? :-)


- Paul



From mturquette at ti.com  Tue Mar 20 19:53:56 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 20 Mar 2012 16:53:56 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
Message-ID: <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>

On Tue, Mar 20, 2012 at 10:46 AM, Saravana Kannan
<skannan at codeaurora.org> wrote:
> On Tue, March 20, 2012 7:02 am, Shawn Guo wrote:
>> On Thu, Mar 15, 2012 at 11:11:19PM -0700, Mike Turquette wrote:
>> ...
>>> +struct clk_ops {
>>> + ? ?int ? ? ? ? ? ? (*prepare)(struct clk_hw *hw);
>>> + ? ?void ? ? ? ? ? ?(*unprepare)(struct clk_hw *hw);
>>> + ? ?int ? ? ? ? ? ? (*enable)(struct clk_hw *hw);
>>> + ? ?void ? ? ? ? ? ?(*disable)(struct clk_hw *hw);
>>> + ? ?int ? ? ? ? ? ? (*is_enabled)(struct clk_hw *hw);
>>> + ? ?unsigned long ? (*recalc_rate)(struct clk_hw *hw,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long parent_rate);
>>
>> I believe I have heard people love the interface with parent_rate
>> passed in. ?I love that too. ?But I would like to ask the same thing
>> on .round_rate and .set_rate as well for the same reason why we have
>> it for .recalc_rate.
>
> In my case, for most clocks, set rate involves reparenting. So, what does
> passing parent_rate for these even mean? Passing parent_rate seems more
> apt for recalc_rate since it's called when the parent rate changes -- so,
> the actual parent itself is not expected to change.

>From my conversations with folks across many platforms, I think that
the way your clock tree expects to change rates is the exception, not
the rule.  As such you should just ignore the parent_rate parameter as
it useless to you.

> I could ignore the parameter, but just wondering how many of the others
> see value in this. And if we do add this parameter, it shouldn't be made
> mandatory for the platform driver to use it (due to other assumptions the
> clock framework might make).

>From my rough census of folks that actually need .set_rate support, I
think that everyone except MSM could benefit from this.  Your concept
of clk_set_rate is everyone else's clk_set_parent.

Ignoring the new parameter should cause you no harm.  It does make me
wonder if it would be a good idea to pass in the parent rate for
.set_parent, which is analogous to .set_rate in many ways.

Regards,
Mike

> -Saravana


From pullip.cho at samsung.com  Tue Mar 20 19:56:51 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Wed, 21 Mar 2012 08:56:51 +0900
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <4F688B2D.20808@gmail.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <CAHQjnOO5DLOj8Fw=ZriSnXg8W3k7y8Dnu--Peqe6JJX0xGMhoQ@mail.gmail.com>
 <4F688B2D.20808@gmail.com>
Message-ID: <CAHQjnOMjSPDOymJe356AWnJszQv+X-QWrVrB7ahYDkXBr5HrQw@mail.gmail.com>

On Tue, Mar 20, 2012 at 10:50 PM, Subash Patel <subashrp at gmail.com> wrote:
> Sorry for digging this very late. But as part of integrating dma_map v7 &
> sysmmu v12 on 3.3-rc5, I am facing below issue:
>
> a) By un-selecting IOMMU in menu config, I am able to allocate memory in
> vb2-dma-contig
>
> b) When I enable SYSMMU support for the IP's, I am receiving below fault:
>
> Unhandled fault: external abort on non-linefetch (0x818) at 0xb6f55000
>
> I think this has something to do with the access to the SYSMMU registers for
> writing the page table. Has anyone of you faced this issue while testing
> these(dma_map+iommu) patches on kernel mentioned above? This must be
> something related to recent changes, as I didn't have issues with these
> patches on 3.2 kernel.
>

0xb6f55000 is not an address of SYSMMU register if your kernel starts
at 0xc0000000.

Can you tell me any detailed information or situation?

Regards,

KyongHo.


From khilman at ti.com  Tue Mar 20 19:56:51 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 20 Mar 2012 16:56:51 -0700
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <201203202305.37952.arnd.bergmann@linaro.org> (Arnd Bergmann's
 message of "Tue, 20 Mar 2012 23:05:37 +0000")
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <201203202158.08042.arnd.bergmann@linaro.org> <873992zy5u.fsf@ti.com>
 <201203202305.37952.arnd.bergmann@linaro.org>
Message-ID: <87ty1ix1vg.fsf@ti.com>

Arnd Bergmann <arnd.bergmann at linaro.org> writes:

> On Tuesday 20 March 2012, Kevin Hilman wrote:
>> Maybe it's time that drivers/cpuidle gets a maintainer.  With lots of
>> discussions of scheduler changes that affect load estimation, I suspect
>> we're all going to have a bit of CPUidle work to do in the
>> not-so-distant future.
>
> Hmm, according to the script, you are the maintainer ;-)

doh, I knew I should've kept quiet :/

> $ scripts/get_maintainer.pl -f drivers/cpuidle/cpuidle.c
> Kevin Hilman <khilman at ti.com> (commit_signer:8/10=80%)
> Len Brown <len.brown at intel.com> (commit_signer:7/10=70%)
> Trinabh Gupta <g.trinabh at gmail.com> (commit_signer:4/10=40%)
> Arjan van de Ven <arjan at linux.intel.com> (commit_signer:4/10=40%)
> Deepthi Dharwar <deepthi at linux.vnet.ibm.com> (commit_signer:4/10=40%)
>
> While I realize that the get_maintainers.pl is not the final word,
> you could be the acting cpuidle maintainer for this merge window
> and send the pull request.

Not exactly the outcome I was hoping for (I have enough stuff to look
after at the moment.) 

However, if you think it would help and won't be seen as a take over
attempt (I don't want to maintain CPUidle), I can possibly do it for
this merge window.  

Before doing that though, I'll need give this series a final once over
before I'm willing to send a potentially flame-attracting pull request.

Kevin




From rjw at sisk.pl  Tue Mar 20 20:01:07 2012
From: rjw at sisk.pl (Rafael J. Wysocki)
Date: Wed, 21 Mar 2012 01:01:07 +0100
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <CAP245DXwhCMOJaspW8SY7jtqsA3d5SK4Ctr+JvS+cw4yHfL-mw@mail.gmail.com>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <873992zy5u.fsf@ti.com>
 <CAP245DXwhCMOJaspW8SY7jtqsA3d5SK4Ctr+JvS+cw4yHfL-mw@mail.gmail.com>
Message-ID: <201203210101.08361.rjw@sisk.pl>

On Wednesday, March 21, 2012, Amit Kucheria wrote:
> On Wed, Mar 21, 2012 at 12:48 AM, Kevin Hilman <khilman at ti.com> wrote:
> > Arnd Bergmann <arnd.bergmann at linaro.org> writes:
> >
> >> On Tuesday 20 March 2012, Robert Lee wrote:
> >>> This patch series moves various functionality duplicated in platform
> >>> cpuidle drivers to the core cpuidle driver. Also, the platform irq
> >>> disabling was removed as it appears that all calls into
> >>> cpuidle_call_idle will have already called local_irq_disable().
> >>>
> >>> These changes have been pulled into linux-next.
> >>>
> >>> Len, Andrew, can a request be made for Linus to pull these changes?
> >>
> >> FWIW, Len seems to be rather inactive on the kernel mailing list right
> >> now and generally not very interested in anything outside of x86 and
> >> acpi. If he doesn't reply in the next few days and Andrew also isn't
> >> interested in handling these patches, I'd suggest you just send the pull
> >> request to Linus, with Len on Cc and explain that you tried to send
> >> them through him but gave up in the end.
> >
> > FWIW, I have not had good luck getting response for proposed core
> > CPUidle changes either:
> >
> >        http://lkml.org/lkml/2011/9/19/374
> >
> > Maybe it's time that drivers/cpuidle gets a maintainer.  With lots of
> > discussions of scheduler changes that affect load estimation, I suspect
> > we're all going to have a bit of CPUidle work to do in the
> > not-so-distant future.
> >
> 
> I don't mean to be piling on to Len here, but Daniel Lezcano too has a
> bunch of clean ups that didn't get any maintainer review for over two
> months. He has now refreshed them for 3.3 and is getting ready to send
> them out again. We (Linaro) expect to be spending a lot of time on
> cpuidle in the future and would be glad to help review, test and
> collect patches into a tree for Linus/Andrew to pull while we wait for
> Len to respond or another maintainer to emerge.

Well, I discussed that before with Arjan and he said he would maintain
CPUidle if Len didn't have the time, but it seems he didn't expect that
there would be a lot of work on it in the near future.

So, I suggest that if neither Len nor Arjan reappear shortly, people can
send CPUidle patches to me.

Thanks,
Rafael


From khilman at ti.com  Tue Mar 20 20:10:52 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 20 Mar 2012 17:10:52 -0700
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <1332274969-15782-1-git-send-email-rob.lee@linaro.org> (Robert
 Lee's message of "Tue, 20 Mar 2012 15:22:41 -0500")
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
Message-ID: <87wr6evmnn.fsf@ti.com>

Hi Rob,

Robert Lee <rob.lee at linaro.org> writes:

> This patch series moves various functionality duplicated in platform 
> cpuidle drivers to the core cpuidle driver. Also, the platform irq
> disabling was removed as it appears that all calls into 
> cpuidle_call_idle will have already called local_irq_disable().
>
> These changes have been pulled into linux-next.
>
> Len, Andrew, can a request be made for Linus to pull these changes?
>
> Acked-by: Jean Pihet<j-pihet at ti.com>  (v6)
> Tested-by: Jean Pihet<j-pihet at ti.com>  (v6, omap3)
> Tested-by: Amit Daniel<amit.kachhap at linaro.org>  (v6, Exynos4)
> Tested-by: Robert Lee<rob.lee at linaro.org>  (imx51, imx6q)

Note that there's a space missing between the name and email in these
tags (and for Deepthi's below also.)  That seems to exist in all the
patches.

> Reviewed-by: Kevin Hilman <khilman at ti.com>

For my Reviewed-by, it only applies to the core code and the OMAP
changes.  I haven't reviewed the other platform-specific drivers.  I
believe the same applies to Jean Pihet who works with me on OMAP.

> Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> Reviewed-by: Deepthi Dharwar<deepthi at linux.vnet.ibm.com> (core cpuidle only)

Looks like you never heard from anyone actively working on at91,
shmobile, kirwood or davinci.

I'm not sure we should merge those platform-specific changes without an
ack from those platform maintainers.

For 3.4, maybe we should just merge the core code and the platforms that
have been reviewed/ack'd, and for 3.5, spent some time nagging the other
platform maintainers to review and test.

Kevin



From mturquette at ti.com  Tue Mar 20 20:13:08 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 20 Mar 2012 17:13:08 -0700
Subject: [PATCH 1/2] clk: Fix error handling in fixed clock hardware type
 register fn
In-Reply-To: <348585ed29fb3ff171267c03658e6c0d.squirrel@www.codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <20120320071957.GH3852@pengutronix.de>
 <348585ed29fb3ff171267c03658e6c0d.squirrel@www.codeaurora.org>
Message-ID: <CAJOA=zO=wp9oyuBZONk2oCRYdWU1c4qanKJik-8-sFg51p27MQ@mail.gmail.com>

On Tue, Mar 20, 2012 at 12:46 AM, Saravana Kannan
<skannan at codeaurora.org> wrote:
> On Tue, March 20, 2012 12:19 am, Sascha Hauer wrote:
>> On Mon, Mar 19, 2012 at 08:38:25PM -0700, Saravana Kannan wrote:
>>> If memory allocation for the parents array or the parent string fails,
>>> then
>>> fail the registration immediately instead of calling clk_register and
>>> hoping it fails there.
>>>
>>> Return -ENOMEM on failure.
>>>
>>> Signed-off-by: Saravana Kannan <skannan at codeaurora.org>
>>> Cc: Mike Turquette <mturquette at linaro.org>
>>> Cc: Andrew Lunn <andrew at lunn.ch>
>>> Cc: Rob Herring <rob.herring at calxeda.com>
>>> Cc: Russell King <linux at arm.linux.org.uk>
>>> Cc: Jeremy Kerr <jeremy.kerr at canonical.com>
>>> Cc: Thomas Gleixner <tglx at linutronix.de>
>>> Cc: Arnd Bergman <arnd.bergmann at linaro.org>
>>> Cc: Paul Walmsley <paul at pwsan.com>
>>> Cc: Shawn Guo <shawn.guo at freescale.com>
>>> Cc: Sascha Hauer <s.hauer at pengutronix.de>
>>> Cc: Jamie Iles <jamie at jamieiles.com>
>>> Cc: Richard Zhao <richard.zhao at linaro.org>
>>> Cc: Saravana Kannan <skannan at codeaurora.org>
>>> Cc: Magnus Damm <magnus.damm at gmail.com>
>>> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
>>> Cc: Linus Walleij <linus.walleij at stericsson.com>
>>> Cc: Stephen Boyd <sboyd at codeaurora.org>
>>> Cc: Amit Kucheria <amit.kucheria at linaro.org>
>>> Cc: Deepak Saxena <dsaxena at linaro.org>
>>> Cc: Grant Likely <grant.likely at secretlab.ca>
>>> ---
>>> There are still some memory free issues when clk_register() fails, but I
>>> will
>>> fix it when I fixed the other register() fns to return ENOMEM of alloc
>>> failure instead of a NULL.
>>>
>>> ?drivers/clk/clk-fixed-rate.c | ? 10 +++++++---
>>> ?1 files changed, 7 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
>>> index 90c79fb..6423ae9 100644
>>> --- a/drivers/clk/clk-fixed-rate.c
>>> +++ b/drivers/clk/clk-fixed-rate.c
>>> @@ -61,22 +61,26 @@ struct clk *clk_register_fixed_rate(struct device
>>> *dev, const char *name,
>>> ? ? ? ? ? ? ?parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
>>>
>>> ? ? ? ? ? ? ?if (! parent_names)
>>> - ? ? ? ? ? ? ? ? ? ?goto out;
>>> + ? ? ? ? ? ? ? ? ? ?goto fail_ptr;
>>>
>>> ? ? ? ? ? ? ?len = sizeof(char) * strlen(parent_name);
>>>
>>> ? ? ? ? ? ? ?parent_names[0] = kmalloc(len, GFP_KERNEL);
>>>
>>> ? ? ? ? ? ? ?if (!parent_names[0])
>>> - ? ? ? ? ? ? ? ? ? ?goto out;
>>> + ? ? ? ? ? ? ? ? ? ?goto fail_str;
>>>
>>> ? ? ? ? ? ? ?strncpy(parent_names[0], parent_name, len);
>>> ? ? ?}
>>
>> It's easier to add a char *parent to struct clk_fixed and pass it to
>> clk_register with &fixed->parent. This saves you a kmalloc call and
>> makes the error path simpler. It's the same way already done in the
>> divider.

I thought I had done this for v7... hmm looks like one got left out.
I'll line up a patch to get it in sync with the others as part of my
fixes.

> I thought about that since I saw the same was done for gated and divider
> (I think). Here is my guess at Mike's reasoning for this:
>
> Gated and divider clocks have to have a parent. There's nothing to gate
> otherwise. But fixed rate clocks might not have a parent. It could be XO's
> or PLLs running off of always on XOs not controlled by the SoC. So, it's
> arguable to not have a parent. I don't have a strong opinion on this --
> since Mike took the time to write it, it left it to his subjective
> preference.

I appreciate the thoughtfulness.  Re-using the same type of mechanism
as the divider and gate clocks will still allow the fixed-rate clock
to be parentless, and it makes for cleaner code, one less allocation
and lines up with how the other single-parent basic clocks are done,
so I'll take that method in instead of your patch.

> I sent this patch first since it was around the place I was cleaning up. I
> didn't want to actually just shuffle around a bug. As I mentioned, this
> patch still leaves a bug open -- what if clk_register() fails. I plan to
> fix that once my two patches are picked up (hopefully).

Do you still find it useful to return -ENOMEM from the registration
function instead of a NULL clock?  I'm always worried that people
don't check for error codes on pointers in their platform code and
only check for NULL...

Regards,
Mike

> Thanks,
> Saravana


From nicolas.pitre at linaro.org  Tue Mar 20 21:45:49 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Tue, 20 Mar 2012 21:45:49 -0400 (EDT)
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <87wr6evmnn.fsf@ti.com>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <87wr6evmnn.fsf@ti.com>
Message-ID: <alpine.LFD.2.02.1203202138130.24151@xanadu.home>

On Tue, 20 Mar 2012, Kevin Hilman wrote:

> Looks like you never heard from anyone actively working on at91,
> shmobile, kirwood or davinci.
> 
> I'm not sure we should merge those platform-specific changes without an
> ack from those platform maintainers.

Depends.  There is a limit to how long you may be willing to wait after 
people.  Sometimes the only way to make progress is to merge the thing 
and hope that someone who cares will test the stuff during the ~2 months 
-rc period and provide any fix then.  And if that doesn't happen during 
that time then either the code is just right and no one noticed the 
change, or no one cares anymore.

IMHO, Rob posted those patches many times now for quite a while (many 
months) already.  So I'd suggest simply pushing that stuff into mainline 
as is.


Nicolas


From mturquette at ti.com  Tue Mar 20 21:47:08 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 20 Mar 2012 18:47:08 -0700
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <20120320231242.GP3852@pengutronix.de>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <20120320141811.GF32469@S2101-09.ap.freescale.net>
 <20120320181050.GN3852@pengutronix.de> <4F68E34A.70207@codeaurora.org>
 <20120320231242.GP3852@pengutronix.de>
Message-ID: <CAJOA=zOGTW7OqACWgJQW6HSPLVev+apdNhv4vNXjHTcp=7N+uQ@mail.gmail.com>

On Tue, Mar 20, 2012 at 4:12 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Tue, Mar 20, 2012 at 01:06:34PM -0700, Saravana Kannan wrote:
>> On 03/20/2012 11:10 AM, Sascha Hauer wrote:
>> >On Tue, Mar 20, 2012 at 10:18:14PM +0800, Shawn Guo wrote:
>> >>On Tue, Mar 20, 2012 at 10:40:31AM +0100, Sascha Hauer wrote:
>> >>...
>> >>>I am using these functions and don't need a static array, I just call
>> >>>the functions with the desired parameters.
>> >>>
>> >>With this patch getting in, you do not have to use them then. ?I feel
>> >>a static array will be much more readable than a long list of function
>> >>calls with a long list of hardcoded arguments to each.
>> >
>> >I'm also not a fan of long argument lists; a divider like defined in my
>> >tree takes 5 arguments, a gate 4 and a mux 6. While 6 is already at the
>> >border I think it's still acceptable.
>> >
>> >What I like in terms of readability is one line per clock which makes
>> >for quite short clock files.
>>
>> It certainly makes for short clock files, but it's definitely less
>> readable that the expanded struct. For the original author the "one
>> line per clock" looks readable since they wrote it. But for someone
>> looking at the code to modify it, the expanded one would be much
>> easier to read. Also, you can always declare your own macro if you
>> really want to follow the one line approach.
>>
>> >So when we use structs to initialize the clocks we'll probably have
>> >something like this:
>> >
>> >static struct clk_divider somediv = {
>> > ? ? .reg = CCM_BASE + 0x14,
>> > ? ? .width = 3,
>> > ? ? .shift = 17,
>> > ? ? .lock =&ccm_lock,
>> > ? ? .hw.parent = "someotherdiv",
>> > ? ? .hw.flags = CLK_SET_RATE_PARENT,
>> >};
>>
>> Taken from your patches:
>>
>> imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
>> ARRAY_SIZE(spll_sel_clks));
>>
>> Compare the struct to the one line call. Now tell me, what does "1"
>> represent? No clue. But in the struct, I can immediately tell what
>> each one of the parameters are.
>>
>> Anyway, my patch certainly isn't forcing you to use multiple lines.
>> So, hopefully this won't be a point of contention.
>>
>> >This will make a 4000 line file out of a 500 line file. Now when for
>> >some reason struct clk_divider changes we end with big patches. If the
>> >clk core gets a new fancy CLK_ flag which we want to have then again
>> >we end up with big patches. Then there's also the possibility that
>> >someone finds out that .lock and .hw.flags are common to all dividers
>> >and comes up with a #define DEFINE_CLK_DIVIDER again to share common
>> >fields.
>>
>> This patch won't prevent you from doing any of that. You can still
>> create macros for that (there are already one for that). Also, what
>> you are pointing out is a bigger problem for the current
>> clk_register() function since you might have to change the no. of
>> params of all the callers even if a new field is optional.
>>
>> >All this can be solved when we introduce a small wrapper function and
>> >use it in the clock files:
>> >
>> >static inline struct clk *imx_clk_divider(const char *name, const char *parent,
>> > ? ? ? ? ? ? void __iomem *reg, u8 shift, u8 width)
>> >{
>> > ? ? return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
>> > ? ? ? ? ? ? ? ? ? ? reg, shift, width, 0,&imx_ccm_lock);
>> >}
>> >
>> >It decouples us from the structs used by the clock framework, we can
>> >add our preferred flags and still can share common fields like the lock.
>> >
>> >While this was not the intention when I first converted from struct
>> >initializers to function initializers I am confident that it will make
>> >a good job.
>>
>> Now I'm confused -- it's not clear if you are leaning towards my
>> patch or away from it?
>
> There was a tendency to get rid of static initializers and I like the
> idea of not exposing any of the internally used members outside the
> clock framework.

I'm with Sascha on this.  I feel that dividing the interface strictly
into two halves is the best way.  I have an uneasy feeling about
exposing this stuff into struct clk_hw (or clk_initializer or
whatever).  This stretches the data out across three structures and
just doesn't feel right to me.

> Now people try their best to make themselves comfortable with the
> static initializers and you even discussed the possibility of removing
> the clk_register_* functions (which make it possible for users not
> to use any of the internal struct members). That's what I don't like
> about your patches. But if we go for static initializers anyway then your
> patches probably change things for the better.

Static initialization is something I have fought for; in fact the
original patches provided no way to do it, so clearly what we have
today is some progress for the folks desiring static init.  The patch
above doesn't actually prevent allocation from happening as it still
must call into clk_register and kmalloc struct clk, so besides
readability, I'm not sure what these patches buy us.

Assuming that C99 designated initializers (for the sole purpose of
readability) is the main draw of the above patch, please let me know
what you think about modifying the existing static init macros so that
your clock data looks like this:

DEFINE_CLK_DIVIDER(dpll_iva_m5x2_ck, &dpll_iva_x2_ck, "dpll_iva_x2_ck",
        .flags = 0x0,
        .reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
        .shift = OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT,
        .width = OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH,
        .flags = CLK_DIVIDER_ONE_BASED,
        .lock = NULL
);

Note that the first argument is the name of this clock (and will be
properly stringified for .name = "whatever") and that the second and
third arguments are both the parent clock, used for initializing the
parent pointer and .parent_names, respectively.  If that aspect of the
macro is too ugly then those can even be broken out into a separate
macro since they are independent data structure (struct clk **parents,
and char **parent_names).  Or you could just open code those data
structures and only use a macro for struct clk and struct clk_foo.

This gives you the readability of C99 designated initializers while
keeping struct clk's members totally hidden from the rest of the
world.

Regards,
Mike


From robherring2 at gmail.com  Tue Mar 20 22:15:48 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 20 Mar 2012 21:15:48 -0500
Subject: [PATCH 1/2] ARM: dma-mapping: convert ARCH_HAS_DMA_SET_COHERENT_MASK
 to kconfig symbol
In-Reply-To: <4F68CD9C.3090001@windriver.com>
References: <4F68CD9C.3090001@windriver.com>
Message-ID: <1332296149-28110-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

The only users of ARCH_HAS_DMA_SET_COHERENT_MASK are 2 ARM platforms:
ixp4xx and pxa cm_x2xx. We've been getting lucky that the define is
implicitly included before dma-mapping.h, but the removal of io.h broke
things (c334bc1 ARM: make mach/io.h include optional). Since memory.h
is the correct place, but no longer exists, convert the define to a
kconfig entry.

Reported-by: Paul Gortmaker <paul.gortmaker at windriver.com>
Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Imre Kaloz <kaloz at openwrt.org>
Cc: Krzysztof Halasa <khc at pm.waw.pl>
Cc: Eric Miao <eric.y.miao at gmail.com>
Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
Cc: Vinod Koul <vinod.koul at intel.com>
Cc: Dan Williams <dan.j.williams at intel.com>
---
 arch/arm/Kconfig                             |    4 ++++
 arch/arm/mach-ixp4xx/include/mach/hardware.h |    2 --
 arch/arm/mach-pxa/Kconfig                    |    1 +
 arch/arm/mach-pxa/include/mach/hardware.h    |    4 ----
 include/linux/dma-mapping.h                  |    2 +-
 5 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 31a2ddc..d3999a5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -180,6 +180,9 @@ config ZONE_DMA
 config NEED_DMA_MAP_STATE
        def_bool y
 
+config ARCH_HAS_DMA_SET_COHERENT_MASK
+	bool
+
 config GENERIC_ISA_DMA
 	bool
 
@@ -547,6 +550,7 @@ config ARCH_IXP2000
 config ARCH_IXP4XX
 	bool "IXP4xx-based"
 	depends on MMU
+	select ARCH_HAS_DMA_SET_COHERENT_MASK
 	select CLKSRC_MMIO
 	select CPU_XSCALE
 	select GENERIC_GPIO
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
index c30e7e9..034bb2a 100644
--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -23,8 +23,6 @@
 #define PCIBIOS_MAX_MEM		0x4BFFFFFF
 #endif
 
-#define ARCH_HAS_DMA_SET_COHERENT_MASK
-
 /* Register locations and bits */
 #include "ixp4xx-regs.h"
 
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 61d3c72..109ccd2 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -108,6 +108,7 @@ config CSB726_CSB701
 
 config MACH_ARMCORE
 	bool "CompuLab CM-X255/CM-X270 modules"
+	select ARCH_HAS_DMA_SET_COHERENT_MASK if PCI
 	select PXA27x
 	select IWMMXT
 	select PXA25x
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 8184669..54b64ea 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -337,8 +337,4 @@ extern unsigned int get_memclk_frequency_10khz(void);
 extern unsigned long get_clock_tick_rate(void);
 #endif
 
-#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
-#define ARCH_HAS_DMA_SET_COHERENT_MASK
-#endif
-
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index e13117c..5a736af 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -77,7 +77,7 @@ static inline u64 dma_get_mask(struct device *dev)
 	return DMA_BIT_MASK(32);
 }
 
-#ifdef ARCH_HAS_DMA_SET_COHERENT_MASK
+#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
 int dma_set_coherent_mask(struct device *dev, u64 mask);
 #else
 static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
-- 
1.7.5.4



From robherring2 at gmail.com  Tue Mar 20 22:15:49 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Tue, 20 Mar 2012 21:15:49 -0500
Subject: [PATCH 2/2] ARM: pxa: use commom IOMEM definiton
In-Reply-To: <1332296149-28110-1-git-send-email-robherring2@gmail.com>
References: <4F68CD9C.3090001@windriver.com>
 <1332296149-28110-1-git-send-email-robherring2@gmail.com>
Message-ID: <1332296149-28110-2-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

pxa was missed in the moving of IOMEM to a common defintion, so lots of
IOMEM redefined warnings were introduced. So remove pxa IOMEM definition
and fix all the fallout.

Reported-by: Paul Gortmaker <paul.gortmaker at windriver.com>
Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Eric Miao <eric.y.miao at gmail.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
Cc: Alessandro Zummo <a.zummo at towertech.it>
Cc: Jaroslav Kysela <perex at perex.cz>
Cc: Takashi Iwai <tiwai at suse.de>
Cc: rtc-linux at googlegroups.com
Cc: alsa-devel at alsa-project.org
---
 arch/arm/mach-pxa/clock-pxa2xx.c          |    1 +
 arch/arm/mach-pxa/corgi_pm.c              |    1 +
 arch/arm/mach-pxa/cpufreq-pxa3xx.c        |    1 +
 arch/arm/mach-pxa/include/mach/hardware.h |    2 --
 arch/arm/mach-pxa/mfp-pxa2xx.c            |    1 +
 arch/arm/mach-pxa/pxa2xx.c                |    1 +
 arch/arm/mach-pxa/pxa300.c                |    1 +
 arch/arm/mach-pxa/pxa320.c                |    1 +
 arch/arm/mach-pxa/sharpsl_pm.c            |    1 +
 drivers/rtc/rtc-sa1100.c                  |    1 +
 sound/arm/pxa2xx-ac97-lib.c               |    1 +
 sound/arm/pxa2xx-ac97.c                   |    1 +
 sound/soc/pxa/pxa2xx-ac97.c               |    1 +
 13 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-pxa/clock-pxa2xx.c b/arch/arm/mach-pxa/clock-pxa2xx.c
index 1d5859d..9ee2ad6 100644
--- a/arch/arm/mach-pxa/clock-pxa2xx.c
+++ b/arch/arm/mach-pxa/clock-pxa2xx.c
@@ -9,6 +9,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/syscore_ops.h>
 
 #include <mach/pxa2xx-regs.h>
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 39e265c..048c429 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -19,6 +19,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/apm-emulation.h>
+#include <linux/io.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
index 88fbec0..b85b4ab 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
+#include <linux/io.h>
 
 #include <mach/pxa3xx-regs.h>
 
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 54b64ea..56d92e5 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -40,7 +40,6 @@
 #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
 
 #ifndef __ASSEMBLY__
-# define IOMEM(x) ((void __iomem *)(x))
 # define __REG(x)	(*((volatile u32 __iomem *)io_p2v(x)))
 
 /* With indexed regs we don't want to feed the index through io_p2v()
@@ -52,7 +51,6 @@
 
 #else
 
-# define IOMEM(x)	x 
 # define __REG(x)	io_p2v(x)
 # define __PREG(x)	io_v2p(x)
 
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index f147755..b029562 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -17,6 +17,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/syscore_ops.h>
 
 #include <mach/pxa2xx-regs.h>
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c
index 8682704..f8ec854 100644
--- a/arch/arm/mach-pxa/pxa2xx.c
+++ b/arch/arm/mach-pxa/pxa2xx.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/device.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <mach/pxa2xx-regs.h>
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 40bb165..17cbc0c 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <mach/pxa300.h>
 
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index 8d614ec..6dc99d4 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <mach/pxa320.h>
 
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 8d5168d..6d3b39f 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -24,6 +24,7 @@
 #include <linux/leds.h>
 #include <linux/suspend.h>
 #include <linux/gpio.h>
+#include <linux/io.h>
 
 #include <asm/mach-types.h>
 #include <mach/pm.h>
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index cb9a585..398ab7a 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -30,6 +30,7 @@
 #include <linux/string.h>
 #include <linux/pm.h>
 #include <linux/bitops.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c
index d1aa421..d760371 100644
--- a/sound/arm/pxa2xx-ac97-lib.c
+++ b/sound/arm/pxa2xx-ac97-lib.c
@@ -17,6 +17,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/module.h>
+#include <linux/io.h>
 
 #include <sound/ac97_codec.h>
 #include <sound/pxa2xx-lib.h>
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
index 3a39626..afef72c 100644
--- a/sound/arm/pxa2xx-ac97.c
+++ b/sound/arm/pxa2xx-ac97.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index 837ff34..b4bfd97 100644
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-- 
1.7.5.4



From paul.gortmaker at windriver.com  Tue Mar 20 22:15:28 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Tue, 20 Mar 2012 22:15:28 -0400
Subject: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h
Message-ID: <1332296128-16262-1-git-send-email-paul.gortmaker@windriver.com>

Commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c (linux-next)

    "ATMEL: fix nand ecc support"

indicated that it wanted to "Move platform data to a common
header include/linux/platform_data/atmel_nand.h" and the new
header even had re-include protectors with:

    #ifndef __ATMEL_NAND_H__

However, the file that was added was simply called atmel.h
and this caused avr32 defconfig to fail with:

  In file included from arch/avr32/boards/atstk1000/setup.c:22:
  arch/avr32/mach-at32ap/include/mach/board.h:10:44: error: linux/platform_data/atmel_nand.h: No such file or directory
  In file included from arch/avr32/boards/atstk1000/setup.c:22:
  arch/avr32/mach-at32ap/include/mach/board.h:121: warning: 'struct atmel_nand_data' declared inside parameter list
  arch/avr32/mach-at32ap/include/mach/board.h:121: warning: its scope is only this definition or declaration, which is probably not what you want
  make[2]: *** [arch/avr32/boards/atstk1000/setup.o] Error 1

Rename the file to match the original intention, and fix up the
users who reference the bad name without the _nand suffix.

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
CC: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
CC: Hans-Christian Egtvedt <egtvedt at samfundet.no>
CC: David Woodhouse <dwmw2 at infradead.org>
---
 arch/arm/mach-at91/include/mach/board.h            |    2 +-
 drivers/mtd/nand/atmel_nand.c                      |    2 +-
 .../linux/platform_data/{atmel.h => atmel_nand.h}  |    0
 3 files changed, 2 insertions(+), 2 deletions(-)
 rename include/linux/platform_data/{atmel.h => atmel_nand.h} (100%)

diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 544a5d5..aa0e083 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -41,7 +41,7 @@
 #include <sound/atmel-ac97c.h>
 #include <linux/serial.h>
 #include <linux/platform_data/macb.h>
-#include <linux/platform_data/atmel.h>
+#include <linux/platform_data/atmel_nand.h>
 
  /* USB Device */
 struct at91_udc_data {
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 2165576..7b599a9 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -38,7 +38,7 @@
 #include <linux/dmaengine.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
-#include <linux/platform_data/atmel.h>
+#include <linux/platform_data/atmel_nand.h>
 
 #include <mach/cpu.h>
 
diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel_nand.h
similarity index 100%
rename from include/linux/platform_data/atmel.h
rename to include/linux/platform_data/atmel_nand.h
-- 
1.7.9.1



From nicolas.pitre at linaro.org  Tue Mar 20 22:23:53 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Tue, 20 Mar 2012 22:23:53 -0400 (EDT)
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <CAP245DXwhCMOJaspW8SY7jtqsA3d5SK4Ctr+JvS+cw4yHfL-mw@mail.gmail.com>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <201203202158.08042.arnd.bergmann@linaro.org> <873992zy5u.fsf@ti.com>
 <CAP245DXwhCMOJaspW8SY7jtqsA3d5SK4Ctr+JvS+cw4yHfL-mw@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1203202146131.24151@xanadu.home>

On Wed, 21 Mar 2012, Amit Kucheria wrote:

> On Wed, Mar 21, 2012 at 12:48 AM, Kevin Hilman <khilman at ti.com> wrote:
> > Maybe it's time that drivers/cpuidle gets a maintainer. ?With lots of
> > discussions of scheduler changes that affect load estimation, I suspect
> > we're all going to have a bit of CPUidle work to do in the
> > not-so-distant future.
> >
> 
> I don't mean to be piling on to Len here, but Daniel Lezcano too has a
> bunch of clean ups that didn't get any maintainer review for over two
> months. He has now refreshed them for 3.3 and is getting ready to send
> them out again. We (Linaro) expect to be spending a lot of time on
> cpuidle in the future and would be glad to help review, test and
> collect patches into a tree for Linus/Andrew to pull while we wait for
> Len to respond or another maintainer to emerge.

As I advised recently, it is usually a good idea for the person/group 
who is working the most on a subsystem to simply take the lead and 
become the new maintainer.  Waiting for another maintainer to emerge 
could be compared to cowardice.


Nicolas

From nico at fluxnic.net  Tue Mar 20 22:30:53 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 20 Mar 2012 22:30:53 -0400 (EDT)
Subject: [PATCH 1/2] ARM: dma-mapping: convert
 ARCH_HAS_DMA_SET_COHERENT_MASK to kconfig symbol
In-Reply-To: <1332296149-28110-1-git-send-email-robherring2@gmail.com>
References: <4F68CD9C.3090001@windriver.com>
 <1332296149-28110-1-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203202230230.24151@xanadu.home>

On Tue, 20 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> The only users of ARCH_HAS_DMA_SET_COHERENT_MASK are 2 ARM platforms:
> ixp4xx and pxa cm_x2xx. We've been getting lucky that the define is
> implicitly included before dma-mapping.h, but the removal of io.h broke
> things (c334bc1 ARM: make mach/io.h include optional). Since memory.h
> is the correct place, but no longer exists, convert the define to a
> kconfig entry.
> 
> Reported-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Imre Kaloz <kaloz at openwrt.org>
> Cc: Krzysztof Halasa <khc at pm.waw.pl>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
> Cc: Vinod Koul <vinod.koul at intel.com>
> Cc: Dan Williams <dan.j.williams at intel.com>

Acked-by: Nicolas Pitre <nico at linaro.org>

> ---
>  arch/arm/Kconfig                             |    4 ++++
>  arch/arm/mach-ixp4xx/include/mach/hardware.h |    2 --
>  arch/arm/mach-pxa/Kconfig                    |    1 +
>  arch/arm/mach-pxa/include/mach/hardware.h    |    4 ----
>  include/linux/dma-mapping.h                  |    2 +-
>  5 files changed, 6 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 31a2ddc..d3999a5 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -180,6 +180,9 @@ config ZONE_DMA
>  config NEED_DMA_MAP_STATE
>         def_bool y
>  
> +config ARCH_HAS_DMA_SET_COHERENT_MASK
> +	bool
> +
>  config GENERIC_ISA_DMA
>  	bool
>  
> @@ -547,6 +550,7 @@ config ARCH_IXP2000
>  config ARCH_IXP4XX
>  	bool "IXP4xx-based"
>  	depends on MMU
> +	select ARCH_HAS_DMA_SET_COHERENT_MASK
>  	select CLKSRC_MMIO
>  	select CPU_XSCALE
>  	select GENERIC_GPIO
> diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
> index c30e7e9..034bb2a 100644
> --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
> +++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
> @@ -23,8 +23,6 @@
>  #define PCIBIOS_MAX_MEM		0x4BFFFFFF
>  #endif
>  
> -#define ARCH_HAS_DMA_SET_COHERENT_MASK
> -
>  /* Register locations and bits */
>  #include "ixp4xx-regs.h"
>  
> diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
> index 61d3c72..109ccd2 100644
> --- a/arch/arm/mach-pxa/Kconfig
> +++ b/arch/arm/mach-pxa/Kconfig
> @@ -108,6 +108,7 @@ config CSB726_CSB701
>  
>  config MACH_ARMCORE
>  	bool "CompuLab CM-X255/CM-X270 modules"
> +	select ARCH_HAS_DMA_SET_COHERENT_MASK if PCI
>  	select PXA27x
>  	select IWMMXT
>  	select PXA25x
> diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
> index 8184669..54b64ea 100644
> --- a/arch/arm/mach-pxa/include/mach/hardware.h
> +++ b/arch/arm/mach-pxa/include/mach/hardware.h
> @@ -337,8 +337,4 @@ extern unsigned int get_memclk_frequency_10khz(void);
>  extern unsigned long get_clock_tick_rate(void);
>  #endif
>  
> -#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
> -#define ARCH_HAS_DMA_SET_COHERENT_MASK
> -#endif
> -
>  #endif  /* _ASM_ARCH_HARDWARE_H */
> diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
> index e13117c..5a736af 100644
> --- a/include/linux/dma-mapping.h
> +++ b/include/linux/dma-mapping.h
> @@ -77,7 +77,7 @@ static inline u64 dma_get_mask(struct device *dev)
>  	return DMA_BIT_MASK(32);
>  }
>  
> -#ifdef ARCH_HAS_DMA_SET_COHERENT_MASK
> +#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
>  int dma_set_coherent_mask(struct device *dev, u64 mask);
>  #else
>  static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
> -- 
> 1.7.5.4
> 


From skannan at codeaurora.org  Tue Mar 20 22:32:56 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 20 Mar 2012 19:32:56 -0700
Subject: [PATCH 1/2] clk: Fix error handling in fixed clock hardware type
 register fn
In-Reply-To: <CAJOA=zO=wp9oyuBZONk2oCRYdWU1c4qanKJik-8-sFg51p27MQ@mail.gmail.com>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <20120320071957.GH3852@pengutronix.de>
 <348585ed29fb3ff171267c03658e6c0d.squirrel@www.codeaurora.org>
 <CAJOA=zO=wp9oyuBZONk2oCRYdWU1c4qanKJik-8-sFg51p27MQ@mail.gmail.com>
Message-ID: <4F693DD8.7070305@codeaurora.org>

On 03/20/2012 05:13 PM, Turquette, Mike wrote:
> On Tue, Mar 20, 2012 at 12:46 AM, Saravana Kannan
> <skannan at codeaurora.org>  wrote:
>> On Tue, March 20, 2012 12:19 am, Sascha Hauer wrote:
>>> On Mon, Mar 19, 2012 at 08:38:25PM -0700, Saravana Kannan wrote:
>>>> If memory allocation for the parents array or the parent string fails,
>>>> then
>>>> fail the registration immediately instead of calling clk_register and
>>>> hoping it fails there.
>>>>
>>>> Return -ENOMEM on failure.
>>>>
>>>> Signed-off-by: Saravana Kannan<skannan at codeaurora.org>
>>>> Cc: Mike Turquette<mturquette at linaro.org>
>>>> Cc: Andrew Lunn<andrew at lunn.ch>
>>>> Cc: Rob Herring<rob.herring at calxeda.com>
>>>> Cc: Russell King<linux at arm.linux.org.uk>
>>>> Cc: Jeremy Kerr<jeremy.kerr at canonical.com>
>>>> Cc: Thomas Gleixner<tglx at linutronix.de>
>>>> Cc: Arnd Bergman<arnd.bergmann at linaro.org>
>>>> Cc: Paul Walmsley<paul at pwsan.com>
>>>> Cc: Shawn Guo<shawn.guo at freescale.com>
>>>> Cc: Sascha Hauer<s.hauer at pengutronix.de>
>>>> Cc: Jamie Iles<jamie at jamieiles.com>
>>>> Cc: Richard Zhao<richard.zhao at linaro.org>
>>>> Cc: Saravana Kannan<skannan at codeaurora.org>
>>>> Cc: Magnus Damm<magnus.damm at gmail.com>
>>>> Cc: Mark Brown<broonie at opensource.wolfsonmicro.com>
>>>> Cc: Linus Walleij<linus.walleij at stericsson.com>
>>>> Cc: Stephen Boyd<sboyd at codeaurora.org>
>>>> Cc: Amit Kucheria<amit.kucheria at linaro.org>
>>>> Cc: Deepak Saxena<dsaxena at linaro.org>
>>>> Cc: Grant Likely<grant.likely at secretlab.ca>
>>>> ---
>>>> There are still some memory free issues when clk_register() fails, but I
>>>> will
>>>> fix it when I fixed the other register() fns to return ENOMEM of alloc
>>>> failure instead of a NULL.
>>>>
>>>>   drivers/clk/clk-fixed-rate.c |   10 +++++++---
>>>>   1 files changed, 7 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
>>>> index 90c79fb..6423ae9 100644
>>>> --- a/drivers/clk/clk-fixed-rate.c
>>>> +++ b/drivers/clk/clk-fixed-rate.c
>>>> @@ -61,22 +61,26 @@ struct clk *clk_register_fixed_rate(struct device
>>>> *dev, const char *name,
>>>>               parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
>>>>
>>>>               if (! parent_names)
>>>> -                    goto out;
>>>> +                    goto fail_ptr;
>>>>
>>>>               len = sizeof(char) * strlen(parent_name);
>>>>
>>>>               parent_names[0] = kmalloc(len, GFP_KERNEL);
>>>>
>>>>               if (!parent_names[0])
>>>> -                    goto out;
>>>> +                    goto fail_str;
>>>>
>>>>               strncpy(parent_names[0], parent_name, len);
>>>>       }
>>>
>>> It's easier to add a char *parent to struct clk_fixed and pass it to
>>> clk_register with&fixed->parent. This saves you a kmalloc call and
>>> makes the error path simpler. It's the same way already done in the
>>> divider.
>
> I thought I had done this for v7... hmm looks like one got left out.
> I'll line up a patch to get it in sync with the others as part of my
> fixes.
>
>> I thought about that since I saw the same was done for gated and divider
>> (I think). Here is my guess at Mike's reasoning for this:
>>
>> Gated and divider clocks have to have a parent. There's nothing to gate
>> otherwise. But fixed rate clocks might not have a parent. It could be XO's
>> or PLLs running off of always on XOs not controlled by the SoC. So, it's
>> arguable to not have a parent. I don't have a strong opinion on this --
>> since Mike took the time to write it, it left it to his subjective
>> preference.
>
> I appreciate the thoughtfulness.  Re-using the same type of mechanism
> as the divider and gate clocks will still allow the fixed-rate clock
> to be parentless, and it makes for cleaner code, one less allocation
> and lines up with how the other single-parent basic clocks are done,
> so I'll take that method in instead of your patch.

No problem, go for it.

>
>> I sent this patch first since it was around the place I was cleaning up. I
>> didn't want to actually just shuffle around a bug. As I mentioned, this
>> patch still leaves a bug open -- what if clk_register() fails. I plan to
>> fix that once my two patches are picked up (hopefully).
>
> Do you still find it useful to return -ENOMEM from the registration
> function instead of a NULL clock?  I'm always worried that people
> don't check for error codes on pointers in their platform code and
> only check for NULL...

The last discussion I remember, NULL was considered a valid clock. So, I 
think on error, we shouldn't ever return NULL when the return type is 
struct clk *.

Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From nico at fluxnic.net  Tue Mar 20 22:33:07 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 20 Mar 2012 22:33:07 -0400 (EDT)
Subject: [PATCH 2/2] ARM: pxa: use commom IOMEM definiton
In-Reply-To: <1332296149-28110-2-git-send-email-robherring2@gmail.com>
References: <4F68CD9C.3090001@windriver.com>
 <1332296149-28110-1-git-send-email-robherring2@gmail.com>
 <1332296149-28110-2-git-send-email-robherring2@gmail.com>
Message-ID: <alpine.LFD.2.02.1203202231420.24151@xanadu.home>

On Tue, 20 Mar 2012, Rob Herring wrote:

> From: Rob Herring <rob.herring at calxeda.com>
> 
> pxa was missed in the moving of IOMEM to a common defintion, so lots of
> IOMEM redefined warnings were introduced. So remove pxa IOMEM definition
> and fix all the fallout.

You've got at least 3 typos in the above, with 2 of them in the subject 
line alone.  ;-)


Nicolas


From deepthi at linux.vnet.ibm.com  Tue Mar 20 22:38:41 2012
From: deepthi at linux.vnet.ibm.com (Deepthi Dharwar)
Date: Wed, 21 Mar 2012 08:08:41 +0530
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <201203210101.08361.rjw@sisk.pl>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <873992zy5u.fsf@ti.com>
 <CAP245DXwhCMOJaspW8SY7jtqsA3d5SK4Ctr+JvS+cw4yHfL-mw@mail.gmail.com>
 <201203210101.08361.rjw@sisk.pl>
Message-ID: <4F693F31.6030309@linux.vnet.ibm.com>

On 03/21/2012 05:31 AM, Rafael J. Wysocki wrote:

> On Wednesday, March 21, 2012, Amit Kucheria wrote:
>> On Wed, Mar 21, 2012 at 12:48 AM, Kevin Hilman <khilman at ti.com> wrote:
>>> Arnd Bergmann <arnd.bergmann at linaro.org> writes:
>>>
>>>> On Tuesday 20 March 2012, Robert Lee wrote:
>>>>> This patch series moves various functionality duplicated in platform
>>>>> cpuidle drivers to the core cpuidle driver. Also, the platform irq
>>>>> disabling was removed as it appears that all calls into
>>>>> cpuidle_call_idle will have already called local_irq_disable().
>>>>>
>>>>> These changes have been pulled into linux-next.
>>>>>
>>>>> Len, Andrew, can a request be made for Linus to pull these changes?
>>>>
>>>> FWIW, Len seems to be rather inactive on the kernel mailing list right
>>>> now and generally not very interested in anything outside of x86 and
>>>> acpi. If he doesn't reply in the next few days and Andrew also isn't
>>>> interested in handling these patches, I'd suggest you just send the pull
>>>> request to Linus, with Len on Cc and explain that you tried to send
>>>> them through him but gave up in the end.
>>>
>>> FWIW, I have not had good luck getting response for proposed core
>>> CPUidle changes either:
>>>
>>>        http://lkml.org/lkml/2011/9/19/374
>>>
>>> Maybe it's time that drivers/cpuidle gets a maintainer.  With lots of
>>> discussions of scheduler changes that affect load estimation, I suspect
>>> we're all going to have a bit of CPUidle work to do in the
>>> not-so-distant future.
>>>
>>
>> I don't mean to be piling on to Len here, but Daniel Lezcano too has a
>> bunch of clean ups that didn't get any maintainer review for over two
>> months. He has now refreshed them for 3.3 and is getting ready to send
>> them out again. We (Linaro) expect to be spending a lot of time on
>> cpuidle in the future and would be glad to help review, test and
>> collect patches into a tree for Linus/Andrew to pull while we wait for
>> Len to respond or another maintainer to emerge.
> 
> Well, I discussed that before with Arjan and he said he would maintain
> CPUidle if Len didn't have the time, but it seems he didn't expect that
> there would be a lot of work on it in the near future.
> 
> So, I suggest that if neither Len nor Arjan reappear shortly, people can
> send CPUidle patches to me.
> 
> Thanks,
> Rafael
> 


I'll be glad to assist you in this.

Cheers,
Deepthi



From tarun.kanti at ti.com  Tue Mar 20 22:40:40 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Wed, 21 Mar 2012 08:10:40 +0530
Subject: [PATCH v4 RESEND 6/7] gpio/omap: fix incorrect update to
 context.irqenable1
In-Reply-To: <87zkbbywwz.fsf@ti.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
 <1332240799-6748-7-git-send-email-tarun.kanti@ti.com>
 <87zkbbywwz.fsf@ti.com>
Message-ID: <CAC83ZvKRbvVU5Qa1jwud0E6WT-DBU1Z1XEweiXay9x+eLcn0hg@mail.gmail.com>

On Tue, Mar 20, 2012 at 11:31 PM, Kevin Hilman <khilman at ti.com> wrote:
> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>
>> In _enable_gpio_irqbank() when bank->regs->set_irqenable is valid,
>> gpio_mask can be directly set by writing to set_irqenable register
>> without overwriting current value. In order to ensure the same is
>> stored in context.irqenable1, we must read from regs->irqenable
>> instead of overwriting it with gpio_mask.
>
>> The overwriting makes sense only in the second case where irqenable
>> is explicitly read and updated with new gpio_mask before writing it
>> back. However, for consistency reading regs->irqenable into the
>> bank->context.irqenable1 takes care of both the scenarios.
>
> ...except that the code doesn't do this anymore.
Yes.
>
> I like the newer version (I hope so, since I suggested it :), but please
> update the changlog to describe what the code is actually doing.
Sure.
--
Tarun
>
> Thanks,
>
> Kevin


From skannan at codeaurora.org  Tue Mar 20 23:01:24 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 20 Mar 2012 20:01:24 -0700
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <CAJOA=zOGTW7OqACWgJQW6HSPLVev+apdNhv4vNXjHTcp=7N+uQ@mail.gmail.com>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <20120320141811.GF32469@S2101-09.ap.freescale.net>
 <20120320181050.GN3852@pengutronix.de> <4F68E34A.70207@codeaurora.org>
 <20120320231242.GP3852@pengutronix.de>
 <CAJOA=zOGTW7OqACWgJQW6HSPLVev+apdNhv4vNXjHTcp=7N+uQ@mail.gmail.com>
Message-ID: <4F694484.1030706@codeaurora.org>

On 03/20/2012 06:47 PM, Turquette, Mike wrote:
> On Tue, Mar 20, 2012 at 4:12 PM, Sascha Hauer<s.hauer at pengutronix.de>  wrote:
>> On Tue, Mar 20, 2012 at 01:06:34PM -0700, Saravana Kannan wrote:
>>> On 03/20/2012 11:10 AM, Sascha Hauer wrote:
>>>> On Tue, Mar 20, 2012 at 10:18:14PM +0800, Shawn Guo wrote:
>>>>> On Tue, Mar 20, 2012 at 10:40:31AM +0100, Sascha Hauer wrote:
>>>>> ...
>>>>>> I am using these functions and don't need a static array, I just call
>>>>>> the functions with the desired parameters.
>>>>>>
>>>>> With this patch getting in, you do not have to use them then.  I feel
>>>>> a static array will be much more readable than a long list of function
>>>>> calls with a long list of hardcoded arguments to each.
>>>>
>>>> I'm also not a fan of long argument lists; a divider like defined in my
>>>> tree takes 5 arguments, a gate 4 and a mux 6. While 6 is already at the
>>>> border I think it's still acceptable.
>>>>
>>>> What I like in terms of readability is one line per clock which makes
>>>> for quite short clock files.
>>>
>>> It certainly makes for short clock files, but it's definitely less
>>> readable that the expanded struct. For the original author the "one
>>> line per clock" looks readable since they wrote it. But for someone
>>> looking at the code to modify it, the expanded one would be much
>>> easier to read. Also, you can always declare your own macro if you
>>> really want to follow the one line approach.
>>>
>>>> So when we use structs to initialize the clocks we'll probably have
>>>> something like this:
>>>>
>>>> static struct clk_divider somediv = {
>>>>      .reg = CCM_BASE + 0x14,
>>>>      .width = 3,
>>>>      .shift = 17,
>>>>      .lock =&ccm_lock,
>>>>      .hw.parent = "someotherdiv",
>>>>      .hw.flags = CLK_SET_RATE_PARENT,
>>>> };
>>>
>>> Taken from your patches:
>>>
>>> imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
>>> ARRAY_SIZE(spll_sel_clks));
>>>
>>> Compare the struct to the one line call. Now tell me, what does "1"
>>> represent? No clue. But in the struct, I can immediately tell what
>>> each one of the parameters are.
>>>
>>> Anyway, my patch certainly isn't forcing you to use multiple lines.
>>> So, hopefully this won't be a point of contention.
>>>
>>>> This will make a 4000 line file out of a 500 line file. Now when for
>>>> some reason struct clk_divider changes we end with big patches. If the
>>>> clk core gets a new fancy CLK_ flag which we want to have then again
>>>> we end up with big patches. Then there's also the possibility that
>>>> someone finds out that .lock and .hw.flags are common to all dividers
>>>> and comes up with a #define DEFINE_CLK_DIVIDER again to share common
>>>> fields.
>>>
>>> This patch won't prevent you from doing any of that. You can still
>>> create macros for that (there are already one for that). Also, what
>>> you are pointing out is a bigger problem for the current
>>> clk_register() function since you might have to change the no. of
>>> params of all the callers even if a new field is optional.
>>>
>>>> All this can be solved when we introduce a small wrapper function and
>>>> use it in the clock files:
>>>>
>>>> static inline struct clk *imx_clk_divider(const char *name, const char *parent,
>>>>              void __iomem *reg, u8 shift, u8 width)
>>>> {
>>>>      return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
>>>>                      reg, shift, width, 0,&imx_ccm_lock);
>>>> }
>>>>
>>>> It decouples us from the structs used by the clock framework, we can
>>>> add our preferred flags and still can share common fields like the lock.
>>>>
>>>> While this was not the intention when I first converted from struct
>>>> initializers to function initializers I am confident that it will make
>>>> a good job.
>>>
>>> Now I'm confused -- it's not clear if you are leaning towards my
>>> patch or away from it?
>>
>> There was a tendency to get rid of static initializers and I like the
>> idea of not exposing any of the internally used members outside the
>> clock framework.
>
> I'm with Sascha on this.  I feel that dividing the interface strictly
> into two halves is the best way.

I addressed this concern in my earlier comments. We can make a copy or 
we can agree the fields I moved to clk_hw aren't really useful wrt 
writing hacky code and call it a day. Can you please clarify why neither 
of these options are acceptable?

> I have an uneasy feeling about
> exposing this stuff into struct clk_hw (or clk_initializer or
> whatever).  This stretches the data out across three structures and
> just doesn't feel right to me.

Wrt this discussion, there are three distinct classes of data:
1) Those specific to the platform driver that the common code shouldn't 
care about.
2) Those specific to the common code that the platform driver shouldn't 
care about.
3) Stuff that's shared/passed between common code and the platform driver.

When we have three classes of data, I don't what's wrong with having 
three struct types to contain them. If anything, it's better than the 
current approach of exposing the common clock code specific data (struct 
clk) to code outside of common clock code just because we want to allow 
static initialization. The end goal should be to move struct clk inside 
clk.c.

I think this patch just takes us one step close to that since IMX and 
MSM won't have to include clk-private.h in any of our platform specific 
files while also allowing OMAP to include it for the near term.

>> Now people try their best to make themselves comfortable with the
>> static initializers and you even discussed the possibility of removing
>> the clk_register_* functions (which make it possible for users not
>> to use any of the internal struct members). That's what I don't like
>> about your patches. But if we go for static initializers anyway then your
>> patches probably change things for the better.
>
> Static initialization is something I have fought for; in fact the
> original patches provided no way to do it, so clearly what we have
> today is some progress for the folks desiring static init.

I too desire static init. Sorry if I was unclear and gave people the 
misconception that I wanted to remove static init.

> The patch
> above doesn't actually prevent allocation from happening as it still
> must call into clk_register and kmalloc struct clk,

Correct.

> so besides
> readability, I'm not sure what these patches buy us.

I think readability is very important and if this buys us nothing but 
readability, we should still take this patch. But there are other 
benefits too -- I mentioned them in the commit text.

> Assuming that C99 designated initializers (for the sole purpose of
> readability) is the main draw of the above patch, please let me know
> what you think about modifying the existing static init macros so that
> your clock data looks like this:
>
> DEFINE_CLK_DIVIDER(dpll_iva_m5x2_ck,&dpll_iva_x2_ck, "dpll_iva_x2_ck",
>          .flags = 0x0,
>          .reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
>          .shift = OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT,
>          .width = OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH,
>          .flags = CLK_DIVIDER_ONE_BASED,
>          .lock = NULL
> );
>
> Note that the first argument is the name of this clock (and will be
> properly stringified for .name = "whatever") and that the second and
> third arguments are both the parent clock, used for initializing the
> parent pointer and .parent_names, respectively.  If that aspect of the
> macro is too ugly then those can even be broken out into a separate
> macro since they are independent data structure (struct clk **parents,
> and char **parent_names).  Or you could just open code those data
> structures and only use a macro for struct clk and struct clk_foo.
>
> This gives you the readability of C99 designated initializers while
> keeping struct clk's members totally hidden from the rest of the
> world.

But it still leaves the struct clk exposed to people who do static init 
of the clock tree. I think agreeing that the name, parent names, flags 
and ops are not used to hack with or just making a copy of all of them 
(and mark the originals as __init if that's doable). is a better 
solution than trying to go with macros and leave struct clk exposed to 
everyone who want to do static init of the clock tree.

At a later point when we are ready to move struct clk inside clk.c, with 
this patch applied right now, IMX and MSM won't have to churn their code.

Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From skannan at codeaurora.org  Tue Mar 20 23:10:34 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 20 Mar 2012 20:10:34 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
Message-ID: <4F6946AA.4070201@codeaurora.org>

On 03/20/2012 04:53 PM, Turquette, Mike wrote:
> On Tue, Mar 20, 2012 at 10:46 AM, Saravana Kannan
> <skannan at codeaurora.org>  wrote:
>> On Tue, March 20, 2012 7:02 am, Shawn Guo wrote:
>>> On Thu, Mar 15, 2012 at 11:11:19PM -0700, Mike Turquette wrote:
>>> ...
>>>> +struct clk_ops {
>>>> +    int             (*prepare)(struct clk_hw *hw);
>>>> +    void            (*unprepare)(struct clk_hw *hw);
>>>> +    int             (*enable)(struct clk_hw *hw);
>>>> +    void            (*disable)(struct clk_hw *hw);
>>>> +    int             (*is_enabled)(struct clk_hw *hw);
>>>> +    unsigned long   (*recalc_rate)(struct clk_hw *hw,
>>>> +                                    unsigned long parent_rate);
>>>
>>> I believe I have heard people love the interface with parent_rate
>>> passed in.  I love that too.  But I would like to ask the same thing
>>> on .round_rate and .set_rate as well for the same reason why we have
>>> it for .recalc_rate.
>>
>> In my case, for most clocks, set rate involves reparenting. So, what does
>> passing parent_rate for these even mean? Passing parent_rate seems more
>> apt for recalc_rate since it's called when the parent rate changes -- so,
>> the actual parent itself is not expected to change.
>
>  From my conversations with folks across many platforms, I think that
> the way your clock tree expects to change rates is the exception, not
> the rule.  As such you should just ignore the parent_rate parameter as
> it useless to you.
>
>> I could ignore the parameter, but just wondering how many of the others
>> see value in this. And if we do add this parameter, it shouldn't be made
>> mandatory for the platform driver to use it (due to other assumptions the
>> clock framework might make).
>
>  From my rough census of folks that actually need .set_rate support, I
> think that everyone except MSM could benefit from this.  Your concept
> of clk_set_rate is everyone else's clk_set_parent.

To clarify, MSM's set parent is a subset of steps needed to be done to 
finish set parent. So, it's not that we just randomly decided to swap 
the meanings of these two functions.

Also, I think don't think the difference in view of set_rate is due to 
the difference in the clock trees between platforms with complicated 
trees. I think it's more because of who actually decides the rates for 
the clock tree. It looks like some platforms pick a top-down approach to 
deciding the rates of the clock tre while others pick a bottom-up approach.

> Ignoring the new parameter should cause you no harm.

As long as this is guaranteed, I have no problems with Shawn's suggestion.

> It does make me
> wonder if it would be a good idea to pass in the parent rate for
> .set_parent, which is analogous to .set_rate in many ways.

I need to think a bit more about this.

-Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From nicolas.pitre at linaro.org  Tue Mar 20 23:15:48 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Tue, 20 Mar 2012 23:15:48 -0400 (EDT)
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <alpine.DEB.2.00.1203201611330.22974@utopia.booyaka.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <20120316234706.GJ3852@pengutronix.de>
 <alpine.DEB.2.00.1203201611330.22974@utopia.booyaka.com>
Message-ID: <alpine.LFD.2.02.1203202233340.24151@xanadu.home>

On Tue, 20 Mar 2012, Paul Walmsley wrote:

> We need to indicate in some way that the existing code and API is very 
> likely to change in ways that could involve quite a bit of work for 
> adopters.

[...]

> Anyway.  It is okay if we want to have some starter common clock framework 
> in mainline; this is why deferring the merge hasn't been proposed.  But 
> the point is that anyone who bases their code or platform on the common 
> clock framework needs to be aware that, to satisfy one of its major 
> use-cases, the behavior and/or API of the common clock code may need to 
> change significantly.

Paul,

While I understand your concern, please don't forget that the perfect is 
the enemy of the good.

This common clk API has been under development for over *two* years 
already, with several attempts to merge it.  And each previous merge 
attempt aborted because someone came along at the last minute to do 
exactly what you are doing i.e. underline all the flaws and call for a 
redesign.  This is becoming a bad joke.

We finally have something that the majority of reviewers are happy with 
and which should cover the majority of existing cases out there.  Let's 
give it a chance, shall we? Otherwise one might ask where were you 
during those development years if you claim that the behavior and/or API 
of the common clock code still need to change significantly?

> Explicitly stating this is not only simple courtesy to its users, many of 
> whom won't have been privy to its development.  It also is intended to 
> make the code easier to change once it reaches mainline.

The code will be easier to change once it is in mainline, simply due to 
the fact that you can also change all its users at once.  And it is well 
possible that most users won't have to deal with the same magnitude of 
complexity as yours, again reducing the scope for resistance to changes.

Let's see how things go with the current code and improve it 
incrementally.  Otherwise no one will get involved with this API which 
is almost just as bad as not having the code merged at all.

> So, until the API is well-defined and does all that it needs to do for its 
> major users, [...]

No, the API simply can't ever be well defined if people don't actually 
start using it to eventually refine it further.  Major users were 
converted to it, and in most cases The API does all that it needs to do 
already.  Otherwise you'll be stuck in a catch22 situation forever.

And APIs in the Linux kernel do change all the time.  There is no stable 
API in the kernel.  Extensions will come about eventually, and existing 
users (simple ones by definition if the current API already meets their 
needs) should be converted over easily.


Nicolas


From skannan at codeaurora.org  Tue Mar 20 23:26:34 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 20 Mar 2012 20:26:34 -0700
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <alpine.LFD.2.02.1203202233340.24151@xanadu.home>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <20120316234706.GJ3852@pengutronix.de>
 <alpine.DEB.2.00.1203201611330.22974@utopia.booyaka.com>
 <alpine.LFD.2.02.1203202233340.24151@xanadu.home>
Message-ID: <4F694A6A.4050706@codeaurora.org>

On 03/20/2012 08:15 PM, Nicolas Pitre wrote:
> On Tue, 20 Mar 2012, Paul Walmsley wrote:
>
>> We need to indicate in some way that the existing code and API is very
>> likely to change in ways that could involve quite a bit of work for
>> adopters.
>
> [...]
>
>> Anyway.  It is okay if we want to have some starter common clock framework
>> in mainline; this is why deferring the merge hasn't been proposed.  But
>> the point is that anyone who bases their code or platform on the common
>> clock framework needs to be aware that, to satisfy one of its major
>> use-cases, the behavior and/or API of the common clock code may need to
>> change significantly.
>
> Paul,
>
> While I understand your concern, please don't forget that the perfect is
> the enemy of the good.
>
> This common clk API has been under development for over *two* years
> already, with several attempts to merge it.  And each previous merge
> attempt aborted because someone came along at the last minute to do
> exactly what you are doing i.e. underline all the flaws and call for a
> redesign.  This is becoming a bad joke.
>
> We finally have something that the majority of reviewers are happy with
> and which should cover the majority of existing cases out there.  Let's
> give it a chance, shall we? Otherwise one might ask where were you
> during those development years if you claim that the behavior and/or API
> of the common clock code still need to change significantly?
>
>> Explicitly stating this is not only simple courtesy to its users, many of
>> whom won't have been privy to its development.  It also is intended to
>> make the code easier to change once it reaches mainline.
>
> The code will be easier to change once it is in mainline, simply due to
> the fact that you can also change all its users at once.  And it is well
> possible that most users won't have to deal with the same magnitude of
> complexity as yours, again reducing the scope for resistance to changes.
>
> Let's see how things go with the current code and improve it
> incrementally.  Otherwise no one will get involved with this API which
> is almost just as bad as not having the code merged at all.
>
>> So, until the API is well-defined and does all that it needs to do for its
>> major users, [...]
>
> No, the API simply can't ever be well defined if people don't actually
> start using it to eventually refine it further.  Major users were
> converted to it, and in most cases The API does all that it needs to do
> already.  Otherwise you'll be stuck in a catch22 situation forever.
>
> And APIs in the Linux kernel do change all the time.  There is no stable
> API in the kernel.  Extensions will come about eventually, and existing
> users (simple ones by definition if the current API already meets their
> needs) should be converted over easily.

+1 to the general idea in Nicolas's email.

To add a few more thoughts, while I agree with Paul that there is room 
for improvement in the APIs, I think the difference in opinion comes 
when we ask the question:

"When we eventually refine the APIs in the future to be more expressive, 
do we think that the current APIs can or cannot be made as wrappers 
around the new more expressive APIs?"

Absolutes are almost never right, so I can't give an absolute answer. 
But I'm strongly leaning towards "we can" as the answer to the question. 
That combined with the reasons Nicholas mentioned is why I think the 
APIs should not be marked as experimental in anyway.

-Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From rob.lee at linaro.org  Wed Mar 21 00:45:04 2012
From: rob.lee at linaro.org (Rob Lee)
Date: Tue, 20 Mar 2012 23:45:04 -0500
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <87wr6evmnn.fsf@ti.com>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <87wr6evmnn.fsf@ti.com>
Message-ID: <CAMXH7KGs7TsgvVbaher2oMW=s=Y+5TMnQcffDG8kcdAfn7z8zg@mail.gmail.com>

On Tue, Mar 20, 2012 at 7:10 PM, Kevin Hilman <khilman at ti.com> wrote:
> Hi Rob,
>
> Robert Lee <rob.lee at linaro.org> writes:
>
>> This patch series moves various functionality duplicated in platform
>> cpuidle drivers to the core cpuidle driver. Also, the platform irq
>> disabling was removed as it appears that all calls into
>> cpuidle_call_idle will have already called local_irq_disable().
>>
>> These changes have been pulled into linux-next.
>>
>> Len, Andrew, can a request be made for Linus to pull these changes?
>>
>> Acked-by: Jean Pihet<j-pihet at ti.com> ?(v6)
>> Tested-by: Jean Pihet<j-pihet at ti.com> ?(v6, omap3)
>> Tested-by: Amit Daniel<amit.kachhap at linaro.org> ?(v6, Exynos4)
>> Tested-by: Robert Lee<rob.lee at linaro.org> ?(imx51, imx6q)
>
> Note that there's a space missing between the name and email in these
> tags (and for Deepthi's below also.) ?That seems to exist in all the
> patches.
>

Thanks.  This is now fixed in my pull tree.

>> Reviewed-by: Kevin Hilman <khilman at ti.com>
>
> For my Reviewed-by, it only applies to the core code and the OMAP
> changes. ?I haven't reviewed the other platform-specific drivers. ?I
> believe the same applies to Jean Pihet who works with me on OMAP.
>
>> Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
>> Reviewed-by: Deepthi Dharwar<deepthi at linux.vnet.ibm.com> (core cpuidle only)
>
> Looks like you never heard from anyone actively working on at91,
> shmobile, kirwood or davinci.
>
> I'm not sure we should merge those platform-specific changes without an
> ack from those platform maintainers.
>
> For 3.4, maybe we should just merge the core code and the platforms that
> have been reviewed/ack'd, and for 3.5, spent some time nagging the other
> platform maintainers to review and test.
>
> Kevin
>


From tom.leiming at gmail.com  Wed Mar 21 00:49:36 2012
From: tom.leiming at gmail.com (Ming Lei)
Date: Wed, 21 Mar 2012 12:49:36 +0800
Subject: [PATCH] ARM: OMAP3+: fix oops triggered in
 omap_prcm_register_chain_handler
Message-ID: <1332305376-27038-1-git-send-email-tom.leiming@gmail.com>

This patch fixes the oos below:

[    1.790242] Unable to handle kernel NULL pointer dereference at virtual
address 00000004
[    1.798632] pgd = c0004000
[    1.801638] [00000004] *pgd=00000000
[    1.805400] Internal error: Oops: 805 [#1] PREEMPT SMP THUMB2
[    1.811381] Modules linked in:
[    1.814601] CPU: 1    Not tainted  (3.3.0-next-20120320+ #733)
[    1.820683] PC is at irq_setup_generic_chip+0x6a/0x84
[    1.825951] LR is at irq_get_irq_data+0x7/0x8
[    1.830508] pc : [<c006465e>]    lr : [<c0063a03>]    psr: 20000133
[    1.830512] sp : ee04ff58  ip : 00000000  fp : 00000000
[    1.842461] r10: 00000000  r9 : 00000000  r8 : 00000800
[    1.847905] r7 : c064e260  r6 : 000001dc  r5 : 00000001  r4 : ee0accc0
[    1.854687] r3 : 00000002  r2 : 00000800  r1 : 000001dc  r0 : 00000000
[    1.861472] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA Thumb  Segment kernel
[    1.869234] Control: 50c5387d  Table: 8000404a  DAC: 00000015
[    1.875215] Process swapper/0 (pid: 1, stack limit = 0xee04e2f8)
[    1.881463] Stack: (0xee04ff58 to 0xee050000)
[    1.886017] ff40: c061b668 00000008
[    1.894497] ff60: c0682090 ee0accc0 00000003 c001c637 00000000 00000000 00000201 00000000
[    1.902976] ff80: 00000004 c0473820 c0473800 c0459e8d c0680ac0 c000866d 00000004 00000004
[    1.911455] ffa0: ee04ffa8 00000004 c047381c 00000004 c0473820 c0473800 c0680ac0 00000082
[    1.919934] ffc0: c0489694 c045265f 00000004 00000004 c0452135 c000d105 00000033 00000000
[    1.928413] ffe0: c04525b5 c000d111 00000033 00000000 00000000 c000d111 aaaaaaaa aaaaaaaa
[    1.936912] [<c006465e>] (irq_setup_generic_chip+0x6a/0x84) from [<c001c637>] (omap_prcm_register_chain_handler+0x147/0x1a0)
[    1.948516] [<c001c637>] (omap_prcm_register_chain_handler+0x147/0x1a0) from [<c000866d>] (do_one_initcall+0x65/0xf4)
[    1.959500] [<c000866d>] (do_one_initcall+0x65/0xf4) from [<c045265f>] (kernel_init+0xab/0x138)
[    1.968529] [<c045265f>] (kernel_init+0xab/0x138) from [<c000d111>] (kernel_thread_exit+0x1/0x6)
[    1.977632] Code: f7ff f9d1 6b23 1af3 (6043) 086d
[    1.982684] ---[ end trace 1b75b31a2719ed1c ]---
[    1.987526] Kernel panic - not syncing: Attempted to kill init!
exitcode=0x0000000b

Cc: Tero Kristo <t-kristo at ti.com>
Signed-off-by: Ming Lei <tom.leiming at gmail.com>
---
 arch/arm/mach-omap2/prm_common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 873b51d..d28f848 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -290,7 +290,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 		goto err;
 	}
 
-	for (i = 0; i <= irq_setup->nr_regs; i++) {
+	for (i = 0; i < irq_setup->nr_regs; i++) {
 		gc = irq_alloc_generic_chip("PRCM", 1,
 			irq_setup->base_irq + i * 32, prm_base,
 			handle_level_irq);
-- 
1.7.9.1



From lenb at kernel.org  Wed Mar 21 00:53:53 2012
From: lenb at kernel.org (Len Brown)
Date: Wed, 21 Mar 2012 00:53:53 -0400
Subject: [PATCH v8 0/8] Consolidate cpuidle functionality
In-Reply-To: <201203210101.08361.rjw@sisk.pl>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <873992zy5u.fsf@ti.com>
 <CAP245DXwhCMOJaspW8SY7jtqsA3d5SK4Ctr+JvS+cw4yHfL-mw@mail.gmail.com>
 <201203210101.08361.rjw@sisk.pl>
Message-ID: <4F695EE1.10001@kernel.org>


> So, I suggest that if neither Len nor Arjan reappear shortly, people can
> send CPUidle patches to me.


/me reappears

this series is in my tree now, and I'll be poking at it a bit tomorrow.
If everything is happy I'll send it for 3.4.


thanks,
-Len


From tarun.kanti at ti.com  Wed Mar 21 01:01:48 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Wed, 21 Mar 2012 10:31:48 +0530
Subject: [PATCH v4 RESEND 6/7] gpio/omap: fix incorrect update to
 context.irqenable1
In-Reply-To: <CAC83ZvKRbvVU5Qa1jwud0E6WT-DBU1Z1XEweiXay9x+eLcn0hg@mail.gmail.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
 <1332240799-6748-7-git-send-email-tarun.kanti@ti.com>
 <87zkbbywwz.fsf@ti.com>
 <CAC83ZvKRbvVU5Qa1jwud0E6WT-DBU1Z1XEweiXay9x+eLcn0hg@mail.gmail.com>
Message-ID: <CAC83ZvLgPWO2C6cpRBEsoqFdac1rMyo4OvTXB2_y_mCzaFzJXA@mail.gmail.com>

On Wed, Mar 21, 2012 at 8:10 AM, DebBarma, Tarun Kanti
<tarun.kanti at ti.com> wrote:
> On Tue, Mar 20, 2012 at 11:31 PM, Kevin Hilman <khilman at ti.com> wrote:
>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>>
>>> In _enable_gpio_irqbank() when bank->regs->set_irqenable is valid,
>>> gpio_mask can be directly set by writing to set_irqenable register
>>> without overwriting current value. In order to ensure the same is
>>> stored in context.irqenable1, we must read from regs->irqenable
>>> instead of overwriting it with gpio_mask.
>>
>>> The overwriting makes sense only in the second case where irqenable
>>> is explicitly read and updated with new gpio_mask before writing it
>>> back. However, for consistency reading regs->irqenable into the
>>> bank->context.irqenable1 takes care of both the scenarios.
>>
>> ...except that the code doesn't do this anymore.
> Yes.
>>
>> I like the newer version (I hope so, since I suggested it :), but please
>> update the changlog to describe what the code is actually doing.
> Sure.
I have updated the change log here:
git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev
for_3.4/gpio_more_fixes
--
Tarun
>>
>> Thanks,
>>
>> Kevin


From mturquette at ti.com  Wed Mar 21 01:45:36 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 20 Mar 2012 22:45:36 -0700
Subject: [PATCH 1/2] clk: Fix error handling in fixed clock hardware type
 register fn
In-Reply-To: <4F693DD8.7070305@codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <20120320071957.GH3852@pengutronix.de>
 <348585ed29fb3ff171267c03658e6c0d.squirrel@www.codeaurora.org>
 <CAJOA=zO=wp9oyuBZONk2oCRYdWU1c4qanKJik-8-sFg51p27MQ@mail.gmail.com>
 <4F693DD8.7070305@codeaurora.org>
Message-ID: <CAJOA=zNteC+24oWpqkQJRnL8oqAJe2NcsjHNLbJb1MGN--VEsw@mail.gmail.com>

On Tue, Mar 20, 2012 at 7:32 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
> On 03/20/2012 05:13 PM, Turquette, Mike wrote:
>>
>> On Tue, Mar 20, 2012 at 12:46 AM, Saravana Kannan
>> <skannan at codeaurora.org> ?wrote:
>>>
>>> On Tue, March 20, 2012 12:19 am, Sascha Hauer wrote:
>>>>
>>>> On Mon, Mar 19, 2012 at 08:38:25PM -0700, Saravana Kannan wrote:
>>>>>
>>>>> If memory allocation for the parents array or the parent string fails,
>>>>> then
>>>>> fail the registration immediately instead of calling clk_register and
>>>>> hoping it fails there.
>>>>>
>>>>> Return -ENOMEM on failure.
>>>>>
>>>>> Signed-off-by: Saravana Kannan<skannan at codeaurora.org>
>>>>> Cc: Mike Turquette<mturquette at linaro.org>
>>>>> Cc: Andrew Lunn<andrew at lunn.ch>
>>>>> Cc: Rob Herring<rob.herring at calxeda.com>
>>>>> Cc: Russell King<linux at arm.linux.org.uk>
>>>>> Cc: Jeremy Kerr<jeremy.kerr at canonical.com>
>>>>> Cc: Thomas Gleixner<tglx at linutronix.de>
>>>>> Cc: Arnd Bergman<arnd.bergmann at linaro.org>
>>>>> Cc: Paul Walmsley<paul at pwsan.com>
>>>>> Cc: Shawn Guo<shawn.guo at freescale.com>
>>>>> Cc: Sascha Hauer<s.hauer at pengutronix.de>
>>>>> Cc: Jamie Iles<jamie at jamieiles.com>
>>>>> Cc: Richard Zhao<richard.zhao at linaro.org>
>>>>> Cc: Saravana Kannan<skannan at codeaurora.org>
>>>>> Cc: Magnus Damm<magnus.damm at gmail.com>
>>>>> Cc: Mark Brown<broonie at opensource.wolfsonmicro.com>
>>>>> Cc: Linus Walleij<linus.walleij at stericsson.com>
>>>>> Cc: Stephen Boyd<sboyd at codeaurora.org>
>>>>> Cc: Amit Kucheria<amit.kucheria at linaro.org>
>>>>> Cc: Deepak Saxena<dsaxena at linaro.org>
>>>>> Cc: Grant Likely<grant.likely at secretlab.ca>
>>>>> ---
>>>>> There are still some memory free issues when clk_register() fails, but
>>>>> I
>>>>> will
>>>>> fix it when I fixed the other register() fns to return ENOMEM of alloc
>>>>> failure instead of a NULL.
>>>>>
>>>>> ?drivers/clk/clk-fixed-rate.c | ? 10 +++++++---
>>>>> ?1 files changed, 7 insertions(+), 3 deletions(-)
>>>>>
>>>>> diff --git a/drivers/clk/clk-fixed-rate.c
>>>>> b/drivers/clk/clk-fixed-rate.c
>>>>> index 90c79fb..6423ae9 100644
>>>>> --- a/drivers/clk/clk-fixed-rate.c
>>>>> +++ b/drivers/clk/clk-fixed-rate.c
>>>>> @@ -61,22 +61,26 @@ struct clk *clk_register_fixed_rate(struct device
>>>>> *dev, const char *name,
>>>>> ? ? ? ? ? ? ?parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
>>>>>
>>>>> ? ? ? ? ? ? ?if (! parent_names)
>>>>> - ? ? ? ? ? ? ? ? ? ?goto out;
>>>>> + ? ? ? ? ? ? ? ? ? ?goto fail_ptr;
>>>>>
>>>>> ? ? ? ? ? ? ?len = sizeof(char) * strlen(parent_name);
>>>>>
>>>>> ? ? ? ? ? ? ?parent_names[0] = kmalloc(len, GFP_KERNEL);
>>>>>
>>>>> ? ? ? ? ? ? ?if (!parent_names[0])
>>>>> - ? ? ? ? ? ? ? ? ? ?goto out;
>>>>> + ? ? ? ? ? ? ? ? ? ?goto fail_str;
>>>>>
>>>>> ? ? ? ? ? ? ?strncpy(parent_names[0], parent_name, len);
>>>>> ? ? ?}
>>>>
>>>>
>>>> It's easier to add a char *parent to struct clk_fixed and pass it to
>>>> clk_register with&fixed->parent. This saves you a kmalloc call and
>>>>
>>>> makes the error path simpler. It's the same way already done in the
>>>> divider.
>>
>>
>> I thought I had done this for v7... hmm looks like one got left out.
>> I'll line up a patch to get it in sync with the others as part of my
>> fixes.
>>
>>> I thought about that since I saw the same was done for gated and divider
>>> (I think). Here is my guess at Mike's reasoning for this:
>>>
>>> Gated and divider clocks have to have a parent. There's nothing to gate
>>> otherwise. But fixed rate clocks might not have a parent. It could be
>>> XO's
>>> or PLLs running off of always on XOs not controlled by the SoC. So, it's
>>> arguable to not have a parent. I don't have a strong opinion on this --
>>> since Mike took the time to write it, it left it to his subjective
>>> preference.
>>
>>
>> I appreciate the thoughtfulness. ?Re-using the same type of mechanism
>> as the divider and gate clocks will still allow the fixed-rate clock
>> to be parentless, and it makes for cleaner code, one less allocation
>> and lines up with how the other single-parent basic clocks are done,
>> so I'll take that method in instead of your patch.
>
>
> No problem, go for it.
>
>
>>
>>> I sent this patch first since it was around the place I was cleaning up.
>>> I
>>> didn't want to actually just shuffle around a bug. As I mentioned, this
>>> patch still leaves a bug open -- what if clk_register() fails. I plan to
>>> fix that once my two patches are picked up (hopefully).
>>
>>
>> Do you still find it useful to return -ENOMEM from the registration
>> function instead of a NULL clock? ?I'm always worried that people
>> don't check for error codes on pointers in their platform code and
>> only check for NULL...
>
>
> The last discussion I remember, NULL was considered a valid clock. So, I
> think on error, we shouldn't ever return NULL when the return type is struct
> clk *.

IIRC, that discussion was with respect to the .parent member of struct
clk.  It was decided that having .parent = NULL does not imply that a
clock is a root clock, but instead we rely on the CLK_IS_ROOT flag.  I
can't think of any other instance where a NULL clk when returned from
a registration function would be useful.

Regards,
Mike

> Thanks,
> Saravana


From shawn.guo at linaro.org  Wed Mar 21 01:46:28 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 21 Mar 2012 13:46:28 +0800
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zOZ=XNwhEwUSD34AERi+f8fnMqG9EmS5hxCx+2u8qnkgw@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <CAJOA=zOZ=XNwhEwUSD34AERi+f8fnMqG9EmS5hxCx+2u8qnkgw@mail.gmail.com>
Message-ID: <CAAQ0ZWRyowjHvR0_T-cA8UmbMNpo6yd6OLJ_HPh4foVULF0Tyg@mail.gmail.com>

On 21 March 2012 07:46, Turquette, Mike <mturquette at ti.com> wrote:
...
> As mentioned above, you'll still need to check for CLK_SET_RATE_PARENT
> in your .round_rate implementation with __clk_get_flags(hw->clk).
>
For my particular case, the clk is PLL with fixed rate clk
(oscillator) as parent.  It's known that flag CLK_SET_RATE_PARENT will
never be set for this type of clks.

> Did you want to send a formal patch or just have me absorb this into
> the fixes I'm brewing already? ?I've already fixed the potential null
> ptr dereferences in clk_calc_new_rates, but that's no big deal.
>
The code was attached for better discussion, and I would leave the
formal patch to you.

Regards,
Shawn


From skannan at codeaurora.org  Wed Mar 21 02:33:05 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 20 Mar 2012 23:33:05 -0700 (PDT)
Subject: [PATCH 1/2] clk: Fix error handling in fixed clock hardware 
 type register fn
In-Reply-To: <CAJOA=zNteC+24oWpqkQJRnL8oqAJe2NcsjHNLbJb1MGN--VEsw@mail.gmail.com>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <20120320071957.GH3852@pengutronix.de>
 <348585ed29fb3ff171267c03658e6c0d.squirrel@www.codeaurora.org>
 <CAJOA=zO=wp9oyuBZONk2oCRYdWU1c4qanKJik-8-sFg51p27MQ@mail.gmail.com>
 <4F693DD8.7070305@codeaurora.org>
 <CAJOA=zNteC+24oWpqkQJRnL8oqAJe2NcsjHNLbJb1MGN--VEsw@mail.gmail.com>
Message-ID: <82f47abcdd341a5071f8c0a178d52310.squirrel@www.codeaurora.org>


On Tue, March 20, 2012 10:45 pm, Turquette, Mike wrote:
> IIRC, that discussion was with respect to the .parent member of struct
> clk.  It was decided that having .parent = NULL does not imply that a
> clock is a root clock, but instead we rely on the CLK_IS_ROOT flag.  I
> can't think of any other instance where a NULL clk when returned from
> a registration function would be useful.

I wasn't referring to a discussion with regards to this patch series. I'm
referring to what I believe was a discussion with Russell King on whether
a NULL from clk_get() should be considered a clock and whether it should
be usable as a "clock" with the clock APIs. That's the reason clk_get()
returns -ENOENT instead of NULL.

-Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.




From khlebnikov at openvz.org  Wed Mar 21 02:56:42 2012
From: khlebnikov at openvz.org (Konstantin Khlebnikov)
Date: Wed, 21 Mar 2012 10:56:42 +0400
Subject: [PATCH 07/16] mm/arm: use vm_flags_t for vma flags
In-Reply-To: <20120321065140.13852.52315.stgit@zurg>
References: <20120321065140.13852.52315.stgit@zurg>
Message-ID: <20120321065642.13852.95838.stgit@zurg>

Cast vm_flags to unsigned int for __cpuc_flush_user_range(),
because its vm_flags argument declared as unsigned int.
Asssembler code wants to test VM_EXEC bit on vma->vm_flags,
but for big-endian we should get upper word for this.

Signed-off-by: Konstantin Khlebnikov <khlebnikov at openvz.org>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/include/asm/cacheflush.h |    5 +++--
 arch/arm/kernel/asm-offsets.c     |    6 +++++-
 arch/arm/mm/fault.c               |    2 +-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index d5d8d5c..5aab2c4 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -217,7 +217,7 @@ vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned
 {
 	if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
 		__cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
-					vma->vm_flags);
+					(__force unsigned int)vma->vm_flags);
 }
 
 static inline void
@@ -225,7 +225,8 @@ vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
 {
 	if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
 		unsigned long addr = user_addr & PAGE_MASK;
-		__cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
+		__cpuc_flush_user_range(addr, addr + PAGE_SIZE,
+					(__force unsigned int)vma->vm_flags);
 	}
 }
 
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 1429d89..8150c7e 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -109,9 +109,13 @@ int main(void)
   BLANK();
 #endif
   DEFINE(VMA_VM_MM,		offsetof(struct vm_area_struct, vm_mm));
+#if defined(CONFIG_CPU_BIG_ENDIAN) && (NR_VMA_FLAGS > 32)
+  DEFINE(VMA_VM_FLAGS,		offsetof(struct vm_area_struct, vm_flags) + 4);
+#else
   DEFINE(VMA_VM_FLAGS,		offsetof(struct vm_area_struct, vm_flags));
+#endif
   BLANK();
-  DEFINE(VM_EXEC,	       	VM_EXEC);
+  DEFINE(VM_EXEC,		(__force unsigned int)VM_EXEC);
   BLANK();
   DEFINE(PAGE_SZ,	       	PAGE_SIZE);
   BLANK();
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 40c43a9..371ad65 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -209,7 +209,7 @@ void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
  */
 static inline bool access_error(unsigned int fsr, struct vm_area_struct *vma)
 {
-	unsigned int mask = VM_READ | VM_WRITE | VM_EXEC;
+	vm_flags_t mask = VM_READ | VM_WRITE | VM_EXEC;
 
 	if (fsr & FSR_WRITE)
 		mask = VM_WRITE;



From mika.westerberg at iki.fi  Wed Mar 21 03:07:07 2012
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Wed, 21 Mar 2012 09:07:07 +0200
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <4F683B36.8090101@metasoft.pl>
References: <4F683B36.8090101@metasoft.pl>
Message-ID: <20120321070707.GA25052@mwesterb-mobl.ger.corp.intel.com>

On Tue, Mar 20, 2012 at 09:09:26AM +0100, Rafal Prylowski wrote:
> Implement double buffering for M2M DMA channels.
> 
> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
> 
> Index: slave-dma/drivers/dma/ep93xx_dma.c
> ===================================================================
> --- slave-dma.orig/drivers/dma/ep93xx_dma.c
> +++ slave-dma/drivers/dma/ep93xx_dma.c
> @@ -69,6 +69,7 @@

Which tree this is supposed to apply? I tried both mainline and -next and it
doesn't apply cleanly there.


From egtvedt at samfundet.no  Wed Mar 21 03:26:32 2012
From: egtvedt at samfundet.no (Hans-Christian Egtvedt)
Date: Wed, 21 Mar 2012 08:26:32 +0100
Subject: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h
In-Reply-To: <1332296128-16262-1-git-send-email-paul.gortmaker@windriver.com>
References: <1332296128-16262-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <20120321072632.GA15703@samfundet.no>

Around Tue 20 Mar 2012 22:15:28 -0400 or thereabout, Paul Gortmaker wrote:
> Commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c (linux-next)
> 
>     "ATMEL: fix nand ecc support"
> 
> indicated that it wanted to "Move platform data to a common
> header include/linux/platform_data/atmel_nand.h" and the new
> header even had re-include protectors with:
> 
>     #ifndef __ATMEL_NAND_H__
> 
> However, the file that was added was simply called atmel.h
> and this caused avr32 defconfig to fail with:
> 
>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>   arch/avr32/mach-at32ap/include/mach/board.h:10:44: error: linux/platform_data/atmel_nand.h: No such file or directory
>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: 'struct atmel_nand_data' declared inside parameter list
>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: its scope is only this definition or declaration, which is probably not what you want
>   make[2]: *** [arch/avr32/boards/atstk1000/setup.o] Error 1
> 
> Rename the file to match the original intention, and fix up the
> users who reference the bad name without the _nand suffix.

Thanks fixing this.

> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> CC: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> CC: Hans-Christian Egtvedt <egtvedt at samfundet.no>
> CC: David Woodhouse <dwmw2 at infradead.org>

Acked-by: Hans-Christian Egtvedt <egtvedt at samfundet.no>

> ---
>  arch/arm/mach-at91/include/mach/board.h            |    2 +-
>  drivers/mtd/nand/atmel_nand.c                      |    2 +-
>  .../linux/platform_data/{atmel.h => atmel_nand.h}  |    0
>  3 files changed, 2 insertions(+), 2 deletions(-)
>  rename include/linux/platform_data/{atmel.h => atmel_nand.h} (100%)
> 
> diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
> index 544a5d5..aa0e083 100644
> --- a/arch/arm/mach-at91/include/mach/board.h
> +++ b/arch/arm/mach-at91/include/mach/board.h
> @@ -41,7 +41,7 @@
>  #include <sound/atmel-ac97c.h>
>  #include <linux/serial.h>
>  #include <linux/platform_data/macb.h>
> -#include <linux/platform_data/atmel.h>
> +#include <linux/platform_data/atmel_nand.h>
>  
>   /* USB Device */
>  struct at91_udc_data {
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index 2165576..7b599a9 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -38,7 +38,7 @@
>  #include <linux/dmaengine.h>
>  #include <linux/gpio.h>
>  #include <linux/io.h>
> -#include <linux/platform_data/atmel.h>
> +#include <linux/platform_data/atmel_nand.h>
>  
>  #include <mach/cpu.h>
>  
> diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel_nand.h
> similarity index 100%
> rename from include/linux/platform_data/atmel.h
> rename to include/linux/platform_data/atmel_nand.h
-- 
mvh
Hans-Christian Egtvedt


From paul at pwsan.com  Wed Mar 21 03:30:13 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 21 Mar 2012 01:30:13 -0600 (MDT)
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <alpine.LFD.2.02.1203202233340.24151@xanadu.home>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <20120316234706.GJ3852@pengutronix.de>
 <alpine.DEB.2.00.1203201611330.22974@utopia.booyaka.com>
 <alpine.LFD.2.02.1203202233340.24151@xanadu.home>
Message-ID: <alpine.DEB.2.00.1203210018260.30543@utopia.booyaka.com>

Hello Nico,

On Tue, 20 Mar 2012, Nicolas Pitre wrote:

> This common clk API has been under development for over *two* years 
> already, with several attempts to merge it.  And each previous merge 
> attempt aborted because someone came along at the last minute to do 
> exactly what you are doing i.e. underline all the flaws and call for a 
> redesign.  This is becoming a bad joke.

There is a misunderstanding.  I am not calling for a redesign.  I am 
simply stating that the current maturity level of the API and code should 
be documented in the Kconfig dependencies or description text before the 
code goes upstream.  The objectives are to make future changes easier, set 
expectations, and clearly disclose the extent to which the API and code 
will need to change.

> The code will be easier to change once it is in mainline, simply due to 
> the fact that you can also change all its users at once.  And it is well 
> possible that most users won't have to deal with the same magnitude of 
> complexity as yours, again reducing the scope for resistance to changes.

I hope you are right.  To me, these conclusions seem unlikely.  It seems 
equally likely that these rationales will make it much more difficult to 
change the code once it's upstream and platforms are depending on it.  
Particularly given the ongoing sensitivity to reducing "churn" of mainline 
code, so publicly discussed.  So it seems like a good idea to attempt to 
address these potential roadblocks and criticisms to major clock framework 
changes early.

> And APIs in the Linux kernel do change all the time.  There is no stable 
> API in the kernel.  Extensions will come about eventually, and existing 
> users (simple ones by definition if the current API already meets their 
> needs) should be converted over easily.

Yes, simple extensions should be straightforward.  Of greater concern are 
changes to the existing interface that will probably be required.  These 
could involve significant changes to driver or platform code.  It seems 
likely that there will be strong inertia to making these changes after 
platforms and drivers are converted.

However, if we clearly state that these API changes are likely until the 
API is well-defined, we will hopefully reduce some angst by disclosing
what some of us know.

...

One last comment to address which is orthogonal to the technical content 
of this discussion.

> Otherwise one might ask where were you during those development years if 
> you claim that the behavior and/or API of the common clock code still 
> need to change significantly?

One might ask this.  If one were to ask this, another might briefly 
outline the participation in public and private clock discussions at 
Linaro Connect in Budapest and Redwood Shores, at LPC in Santa Rosa, at 
ELCE/KS in Prague, at ELC in Redwood Shores, in conference calls, IRC 
sessions, and private E-mails with many of the people included in the 
header of this message, not to mention the list posts.

None of the concerns that have been described are new.  There has been an 
endeavour to discuss them with anyone who seemed even remotely interested.

Of course it is a personal source of regret that the participation could 
not have been greater, but this regret is hardly limited to the common 
clock project.


regards,

- Paul



From paul at pwsan.com  Wed Mar 21 03:44:01 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 21 Mar 2012 01:44:01 -0600 (MDT)
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <4F694A6A.4050706@codeaurora.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <20120316234706.GJ3852@pengutronix.de>
 <alpine.DEB.2.00.1203201611330.22974@utopia.booyaka.com>
 <alpine.LFD.2.02.1203202233340.24151@xanadu.home>
 <4F694A6A.4050706@codeaurora.org>
Message-ID: <alpine.DEB.2.00.1203210130520.30543@utopia.booyaka.com>

Hello Saravana,

On Tue, 20 Mar 2012, Saravana Kannan wrote:

> To add a few more thoughts, while I agree with Paul that there is room for
> improvement in the APIs, I think the difference in opinion comes when we ask
> the question:
> 
> "When we eventually refine the APIs in the future to be more expressive, do we
> think that the current APIs can or cannot be made as wrappers around the new
> more expressive APIs?"
> 
> Absolutes are almost never right, so I can't give an absolute answer. 
> But I'm strongly leaning towards "we can" as the answer to the question.  
> That combined with the reasons Nicholas mentioned is why I think the 
> APIs should not be marked as experimental in anyway.

The resistance to documenting that the clock interface is not 
well-defined, and that therefore it is likely to change, and that users 
should not expect it to be stable, is perplexing to me.

Certainly a Kconfig help text change seems trivial enough.  But even the 
resistance to CONFIG_EXPERIMENTAL has been quite surprising to me, given 
that every single defconfig in arch/arm/defconfig sets it:

$ find arch/arm/configs -type f  | wc -l
122
$ fgrep -r CONFIG_EXPERIMENTAL=y arch/arm/configs | wc -l
122
$

(that includes iMX, by the way...)

Certainly, neither Kconfig change is going to prevent us on OMAP from 
figuring out what else is needed to convert our platform to the common 
clock code.  And given the level of enthusiasm on the lists, I don't think 
it's going to prevent many of the other ARM platforms from experimenting 
with the conversion, either.

So it would be interesting to know more about why you (or anyone else) 
perceive that the Kconfig changes would be harmful.


- Paul


From prylowski at metasoft.pl  Wed Mar 21 03:47:22 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Wed, 21 Mar 2012 08:47:22 +0100
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <20120321070707.GA25052@mwesterb-mobl.ger.corp.intel.com>
References: <4F683B36.8090101@metasoft.pl>
 <20120321070707.GA25052@mwesterb-mobl.ger.corp.intel.com>
Message-ID: <4F69878A.4070901@metasoft.pl>

On 2012-03-21 08:07, Mika Westerberg wrote:
> 
> Which tree this is supposed to apply? I tried both mainline and -next and it
> doesn't apply cleanly there.
> 

I prepared it for git://git.infradead.org/users/vkoul/slave-dma.git tree.
Also, I checked that it applies cleanly to:
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
(I'm assuming this is mainline).


From javier.martin at vista-silicon.com  Wed Mar 21 03:49:11 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Wed, 21 Mar 2012 08:49:11 +0100
Subject: [PATCH v3 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <1331723694.1727.28.camel@vkoul-udesk3>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
 <20120309174411.GI3852@pengutronix.de>
 <CACKLOr0XzE0PZk=k5xQQvOA_5dfBk1mYDVyKCep36=3w7ugwWg@mail.gmail.com>
 <1331723694.1727.28.camel@vkoul-udesk3>
Message-ID: <CACKLOr0m5a2p5wzi1OnqnvfZVCP3sRC4b+iZk-ZoRu6rV5SEVw@mail.gmail.com>

>> Vinod,
>> I think with Sascha's ack, this series is ready to be merged. It's
>> quite important for us that it makes it for 3.4.
>>
>> Please, don't forget the following patch too, which is meant to be
>> applied on top of this series:
>>
>> [PATCH] dmaengine: i.MX: Add support for interleaved transfers.
>>
> This is my merge queue which means I will merged it after the cookie
> fixes (hate rebasing that series again)

Do you think it will make it for 3.4?

Regards.
-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From t-kristo at ti.com  Wed Mar 21 04:05:48 2012
From: t-kristo at ti.com (Tero Kristo)
Date: Wed, 21 Mar 2012 10:05:48 +0200
Subject: [PATCH] ARM: OMAP3+: fix oops triggered in
 omap_prcm_register_chain_handler
In-Reply-To: <1332305376-27038-1-git-send-email-tom.leiming@gmail.com>
References: <1332305376-27038-1-git-send-email-tom.leiming@gmail.com>
Message-ID: <1332317148.2116.366.camel@sokoban>

On Wed, 2012-03-21 at 12:49 +0800, Ming Lei wrote:
> This patch fixes the oos below:
> 
> [    1.790242] Unable to handle kernel NULL pointer dereference at virtual
> address 00000004
> [    1.798632] pgd = c0004000
> [    1.801638] [00000004] *pgd=00000000
> [    1.805400] Internal error: Oops: 805 [#1] PREEMPT SMP THUMB2
> [    1.811381] Modules linked in:
> [    1.814601] CPU: 1    Not tainted  (3.3.0-next-20120320+ #733)
> [    1.820683] PC is at irq_setup_generic_chip+0x6a/0x84
> [    1.825951] LR is at irq_get_irq_data+0x7/0x8
> [    1.830508] pc : [<c006465e>]    lr : [<c0063a03>]    psr: 20000133
> [    1.830512] sp : ee04ff58  ip : 00000000  fp : 00000000
> [    1.842461] r10: 00000000  r9 : 00000000  r8 : 00000800
> [    1.847905] r7 : c064e260  r6 : 000001dc  r5 : 00000001  r4 : ee0accc0
> [    1.854687] r3 : 00000002  r2 : 00000800  r1 : 000001dc  r0 : 00000000
> [    1.861472] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA Thumb  Segment kernel
> [    1.869234] Control: 50c5387d  Table: 8000404a  DAC: 00000015
> [    1.875215] Process swapper/0 (pid: 1, stack limit = 0xee04e2f8)
> [    1.881463] Stack: (0xee04ff58 to 0xee050000)
> [    1.886017] ff40: c061b668 00000008
> [    1.894497] ff60: c0682090 ee0accc0 00000003 c001c637 00000000 00000000 00000201 00000000
> [    1.902976] ff80: 00000004 c0473820 c0473800 c0459e8d c0680ac0 c000866d 00000004 00000004
> [    1.911455] ffa0: ee04ffa8 00000004 c047381c 00000004 c0473820 c0473800 c0680ac0 00000082
> [    1.919934] ffc0: c0489694 c045265f 00000004 00000004 c0452135 c000d105 00000033 00000000
> [    1.928413] ffe0: c04525b5 c000d111 00000033 00000000 00000000 c000d111 aaaaaaaa aaaaaaaa
> [    1.936912] [<c006465e>] (irq_setup_generic_chip+0x6a/0x84) from [<c001c637>] (omap_prcm_register_chain_handler+0x147/0x1a0)
> [    1.948516] [<c001c637>] (omap_prcm_register_chain_handler+0x147/0x1a0) from [<c000866d>] (do_one_initcall+0x65/0xf4)
> [    1.959500] [<c000866d>] (do_one_initcall+0x65/0xf4) from [<c045265f>] (kernel_init+0xab/0x138)
> [    1.968529] [<c045265f>] (kernel_init+0xab/0x138) from [<c000d111>] (kernel_thread_exit+0x1/0x6)
> [    1.977632] Code: f7ff f9d1 6b23 1af3 (6043) 086d
> [    1.982684] ---[ end trace 1b75b31a2719ed1c ]---
> [    1.987526] Kernel panic - not syncing: Attempted to kill init!
> exitcode=0x0000000b
> 
> Cc: Tero Kristo <t-kristo at ti.com>
> Signed-off-by: Ming Lei <tom.leiming at gmail.com>
> ---
>  arch/arm/mach-omap2/prm_common.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
> index 873b51d..d28f848 100644
> --- a/arch/arm/mach-omap2/prm_common.c
> +++ b/arch/arm/mach-omap2/prm_common.c
> @@ -290,7 +290,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
>  		goto err;
>  	}
>  
> -	for (i = 0; i <= irq_setup->nr_regs; i++) {
> +	for (i = 0; i < irq_setup->nr_regs; i++) {
>  		gc = irq_alloc_generic_chip("PRCM", 1,
>  			irq_setup->base_irq + i * 32, prm_base,
>  			handle_level_irq);

Wow, I feel ashamed now. Best thing is it is correctly elsewhere in
code. :) You could probably write a better changelog for this but other
than that, acked.

-Tero




From haojian.zhuang at gmail.com  Wed Mar 21 04:15:55 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 21 Mar 2012 16:15:55 +0800
Subject: [PATCH 1/2] ARM: dma-mapping: convert
 ARCH_HAS_DMA_SET_COHERENT_MASK to kconfig symbol
In-Reply-To: <alpine.LFD.2.02.1203202230230.24151@xanadu.home>
References: <4F68CD9C.3090001@windriver.com>
 <1332296149-28110-1-git-send-email-robherring2@gmail.com>
 <alpine.LFD.2.02.1203202230230.24151@xanadu.home>
Message-ID: <CAN1soZwXh6DviO5CHcj_ogM1VK23V2c4CKZf+iMmeP43rwtW9w@mail.gmail.com>

On Wed, Mar 21, 2012 at 10:30 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Tue, 20 Mar 2012, Rob Herring wrote:
>
>> From: Rob Herring <rob.herring at calxeda.com>
>>
>> The only users of ARCH_HAS_DMA_SET_COHERENT_MASK are 2 ARM platforms:
>> ixp4xx and pxa cm_x2xx. We've been getting lucky that the define is
>> implicitly included before dma-mapping.h, but the removal of io.h broke
>> things (c334bc1 ARM: make mach/io.h include optional). Since memory.h
>> is the correct place, but no longer exists, convert the define to a
>> kconfig entry.
>>
>> Reported-by: Paul Gortmaker <paul.gortmaker at windriver.com>
>> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
>> Cc: Russell King <linux at arm.linux.org.uk>
>> Cc: Imre Kaloz <kaloz at openwrt.org>
>> Cc: Krzysztof Halasa <khc at pm.waw.pl>
>> Cc: Eric Miao <eric.y.miao at gmail.com>
>> Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
>> Cc: Vinod Koul <vinod.koul at intel.com>
>> Cc: Dan Williams <dan.j.williams at intel.com>
>
> Acked-by: Nicolas Pitre <nico at linaro.org>
>
Acked.

Imre & Krzysztof,

Do you mind that I merge these patches into arch-pxa git tree? Since a
lot of files in arch-pxa are changed.

Best Regards
Haojian


From nicolas.ferre at atmel.com  Wed Mar 21 04:26:23 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 21 Mar 2012 09:26:23 +0100
Subject: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h
In-Reply-To: <20120321072632.GA15703@samfundet.no>
References: <1332296128-16262-1-git-send-email-paul.gortmaker@windriver.com>
 <20120321072632.GA15703@samfundet.no>
Message-ID: <4F6990AF.2000004@atmel.com>

On 03/21/2012 08:26 AM, Hans-Christian Egtvedt :
> Around Tue 20 Mar 2012 22:15:28 -0400 or thereabout, Paul Gortmaker wrote:
>> Commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c (linux-next)
>>
>>     "ATMEL: fix nand ecc support"
>>
>> indicated that it wanted to "Move platform data to a common
>> header include/linux/platform_data/atmel_nand.h" and the new
>> header even had re-include protectors with:
>>
>>     #ifndef __ATMEL_NAND_H__
>>
>> However, the file that was added was simply called atmel.h
>> and this caused avr32 defconfig to fail with:
>>
>>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>>   arch/avr32/mach-at32ap/include/mach/board.h:10:44: error: linux/platform_data/atmel_nand.h: No such file or directory
>>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: 'struct atmel_nand_data' declared inside parameter list
>>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: its scope is only this definition or declaration, which is probably not what you want
>>   make[2]: *** [arch/avr32/boards/atstk1000/setup.o] Error 1
>>
>> Rename the file to match the original intention, and fix up the
>> users who reference the bad name without the _nand suffix.
> 
> Thanks fixing this.


Yes, we need to fix this. But I would not like to see this
"platform_data/atmel.h" renamed: I think that this file was designed to
collect several common platform data (ie: not just NAND related).

So maybe we should just rename the entry that exists in
mach-at32ap/include/mach/board.h
and remove all occurrences of platform_data/atmel_nand.h


>> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
>> CC: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>> CC: Hans-Christian Egtvedt <egtvedt at samfundet.no>
>> CC: David Woodhouse <dwmw2 at infradead.org>
> 
> Acked-by: Hans-Christian Egtvedt <egtvedt at samfundet.no>
> 
>> ---
>>  arch/arm/mach-at91/include/mach/board.h            |    2 +-
>>  drivers/mtd/nand/atmel_nand.c                      |    2 +-
>>  .../linux/platform_data/{atmel.h => atmel_nand.h}  |    0
>>  3 files changed, 2 insertions(+), 2 deletions(-)
>>  rename include/linux/platform_data/{atmel.h => atmel_nand.h} (100%)

No please.

>>
>> diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
>> index 544a5d5..aa0e083 100644
>> --- a/arch/arm/mach-at91/include/mach/board.h
>> +++ b/arch/arm/mach-at91/include/mach/board.h
>> @@ -41,7 +41,7 @@
>>  #include <sound/atmel-ac97c.h>
>>  #include <linux/serial.h>
>>  #include <linux/platform_data/macb.h>
>> -#include <linux/platform_data/atmel.h>
>> +#include <linux/platform_data/atmel_nand.h>
>>  
>>   /* USB Device */
>>  struct at91_udc_data {
>> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
>> index 2165576..7b599a9 100644
>> --- a/drivers/mtd/nand/atmel_nand.c
>> +++ b/drivers/mtd/nand/atmel_nand.c
>> @@ -38,7 +38,7 @@
>>  #include <linux/dmaengine.h>
>>  #include <linux/gpio.h>
>>  #include <linux/io.h>
>> -#include <linux/platform_data/atmel.h>
>> +#include <linux/platform_data/atmel_nand.h>
>>  
>>  #include <mach/cpu.h>
>>  
>> diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel_nand.h
>> similarity index 100%
>> rename from include/linux/platform_data/atmel.h
>> rename to include/linux/platform_data/atmel_nand.h

Best regards,
-- 
Nicolas Ferre


From linux at arm.linux.org.uk  Wed Mar 21 05:07:31 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 21 Mar 2012 09:07:31 +0000
Subject: [PATCH 1/2] clk: Fix error handling in fixed clock hardware
 type register fn
In-Reply-To: <CAJOA=zNteC+24oWpqkQJRnL8oqAJe2NcsjHNLbJb1MGN--VEsw@mail.gmail.com>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <20120320071957.GH3852@pengutronix.de>
 <348585ed29fb3ff171267c03658e6c0d.squirrel@www.codeaurora.org>
 <CAJOA=zO=wp9oyuBZONk2oCRYdWU1c4qanKJik-8-sFg51p27MQ@mail.gmail.com>
 <4F693DD8.7070305@codeaurora.org>
 <CAJOA=zNteC+24oWpqkQJRnL8oqAJe2NcsjHNLbJb1MGN--VEsw@mail.gmail.com>
Message-ID: <20120321090730.GR15988@n2100.arm.linux.org.uk>

On Tue, Mar 20, 2012 at 10:45:36PM -0700, Turquette, Mike wrote:
> IIRC, that discussion was with respect to the .parent member of struct
> clk.  It was decided that having .parent = NULL does not imply that a
> clock is a root clock, but instead we rely on the CLK_IS_ROOT flag.  I
> can't think of any other instance where a NULL clk when returned from
> a registration function would be useful.

No.  What I've been saying is that in _drivers_ which use clk_get(),
the error range is defined by IS_ERR(clk).  Every other value of
clk must be assumed by the driver to be valid, no ifs or buts.

What the clk API assumes about struct clk is its own business.  If it
wishes to interpret the NULL clk in a specific way, that's its business
to do so.  But it's still not the drivers business to then go and
interpret NULL as being any different from any other valid clock.

This is part of the clk API contract, which is as I said in the first
paragraph, and I keep on saying.  I'm not sure what's so difficult
about this.


From s.hauer at pengutronix.de  Wed Mar 21 05:10:37 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 21 Mar 2012 10:10:37 +0100
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <alpine.DEB.2.00.1203210130520.30543@utopia.booyaka.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <20120316234706.GJ3852@pengutronix.de>
 <alpine.DEB.2.00.1203201611330.22974@utopia.booyaka.com>
 <alpine.LFD.2.02.1203202233340.24151@xanadu.home>
 <4F694A6A.4050706@codeaurora.org>
 <alpine.DEB.2.00.1203210130520.30543@utopia.booyaka.com>
Message-ID: <20120321091037.GQ3852@pengutronix.de>

On Wed, Mar 21, 2012 at 01:44:01AM -0600, Paul Walmsley wrote:
> Hello Saravana,
> 
> Certainly a Kconfig help text change seems trivial enough.  But even the 
> resistance to CONFIG_EXPERIMENTAL has been quite surprising to me, given 
> that every single defconfig in arch/arm/defconfig sets it:
> 
> $ find arch/arm/configs -type f  | wc -l
> 122
> $ fgrep -r CONFIG_EXPERIMENTAL=y arch/arm/configs | wc -l
> 122
> $
> 
> (that includes iMX, by the way...)
> 
> Certainly, neither Kconfig change is going to prevent us on OMAP from 
> figuring out what else is needed to convert our platform to the common 
> clock code.  And given the level of enthusiasm on the lists, I don't think 
> it's going to prevent many of the other ARM platforms from experimenting 
> with the conversion, either.
> 
> So it would be interesting to know more about why you (or anyone else) 
> perceive that the Kconfig changes would be harmful.

Mainly because COMMON_CLK is an invisible option which has to be
selected by architectures. So with the Kconfig change we either have to:

config ARCH_MXC
	depends on EXPERIMENTAL

or:

config ARCH_MXC
	select EXPERIMENTAL
	select COMMON_CLK

Neither of both seems very appealing to me.

You can add a warning to the Kconfig help text if you like, I
have no problem with that. As you said it will prevent noone
from using it anyway.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From thomas.abraham at linaro.org  Wed Mar 21 05:13:53 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 21 Mar 2012 14:43:53 +0530
Subject: [PATCH v4 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and
 EXYNOS5
In-Reply-To: <1331736138-28964-6-git-send-email-kgene.kim@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
 <1331736138-28964-6-git-send-email-kgene.kim@samsung.com>
Message-ID: <CAJuYYwTJsA1M1Qj2P1-1K=pWzi0BPo8YJNDSx4NqGC7NX0030g@mail.gmail.com>

On 14 March 2012 20:12, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Actually, the base address of uart is different between EXYNOS4
> and EXYNOS5 and this patch enables to support uart for EXYNOS4
> and EXYNOS5 SoCs at runtime.
>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---

[...]

> diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
> index 6cacf16..6c857ff 100644
> --- a/arch/arm/mach-exynos/include/mach/debug-macro.S
> +++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
> @@ -21,8 +21,13 @@
> ? ? ? ? */
>
> ? ? ? ?.macro addruart, rp, rv, tmp
> - ? ? ? ? ? ? ? ldr ? ? \rp, = S3C_PA_UART
> - ? ? ? ? ? ? ? ldr ? ? \rv, = S3C_VA_UART
> + ? ? ? ? ? ? ? mov ? ? \rp, #0x10000000

This is physical address of Exynos4/5 CPUID register which cannot be
used here. And virtual address S5P_VA_CPUID also cannot be used here
since this will be called before paging_init when earlyprintk boot
param is used. So, with this change, earlyprintk does not work for
both Exynos4 and Exynos5.

Thanks,
Thomas.


From s.hauer at pengutronix.de  Wed Mar 21 05:16:25 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 21 Mar 2012 10:16:25 +0100
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <alpine.DEB.2.00.1203201740470.22974@utopia.booyaka.com>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <20120320141811.GF32469@S2101-09.ap.freescale.net>
 <20120320181050.GN3852@pengutronix.de>
 <alpine.DEB.2.00.1203201740470.22974@utopia.booyaka.com>
Message-ID: <20120321091625.GR3852@pengutronix.de>

On Tue, Mar 20, 2012 at 05:47:42PM -0600, Paul Walmsley wrote:
> Hello Sascha
> 
> On Tue, 20 Mar 2012, Sascha Hauer wrote:
> 
> > [ C99 structure initializer elided ]
> > 
> > This will make a 4000 line file out of a 500 line file. Now when for
> > some reason struct clk_divider changes we end with big patches. If the
> > clk core gets a new fancy CLK_ flag which we want to have then again
> > we end up with big patches. Then there's also the possibility that
> > someone finds out that .lock and .hw.flags are common to all dividers
> > and comes up with a #define DEFINE_CLK_DIVIDER again to share common
> > fields.
> 
> At least we can understand easily what is being changed.  Readability, 
> particularly by others not familiar with the clock data, is more important 
> to me.
> 
> So like Saravana, I too prefer C99 structure initializers.  At least there 
> should be a choice.
> 
> Quick quiz: in this line below:
> 
> imx_clk_divider("foo_clk", "bar_clk", CCM_BASE + 0x20, 0x5, 0x3);
> 
> which field is the bitfield shift and which is the bitfield width? :-)

I can't even remember the argument order in memset, but I never voted
for a struct memset_init ;)

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From daniel.lezcano at linaro.org  Wed Mar 21 05:27:45 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 10:27:45 +0100
Subject: [RFC][PATCH 2/7] ARM: OMAP4: cpuidle - Declare the states with the
 driver declaration
In-Reply-To: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332322070-24577-3-git-send-email-daniel.lezcano@linaro.org>

The cpuidle API allows to declare statically the states in the driver
structure. Let's use it.
We do no longer need the fill_cstate function called at runtime and
by the way adding more instructions at boot time.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle44xx.c |   56 +++++++++++++++++++++----------------
 1 files changed, 32 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 1210229..cd6bee7 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -148,21 +148,38 @@ DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
 struct cpuidle_driver omap4_idle_driver = {
 	.name =		"omap4_idle",
 	.owner =	THIS_MODULE,
+	.states = {
+		{
+			/* C1 - CPU0 ON + CPU1 ON + MPU ON */
+			.exit_latency = 2 + 2,
+			.target_residency = 5,
+			.flags = CPUIDLE_FLAG_TIME_VALID,
+			.enter = omap4_enter_idle,
+			.name = "C1",
+			.desc = "MPUSS ON"
+		},
+		{
+                        /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
+			.exit_latency = 328 + 440,
+			.target_residency = 960,
+			.flags = CPUIDLE_FLAG_TIME_VALID,
+			.enter = omap4_enter_idle,
+			.name = "C2",
+			.desc = "MPUSS CSWR",
+		},
+		{
+			/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+			.exit_latency = 460 + 518,
+			.target_residency = 1100,
+			.flags = CPUIDLE_FLAG_TIME_VALID,
+			.enter = omap4_enter_idle,
+			.name = "C3",
+			.desc = "MPUSS OSWR",
+		},
+	},
+	.state_count = OMAP4_NUM_STATES,
 };
 
-static inline void _fill_cstate(struct cpuidle_driver *drv,
-					int idx, const char *descr)
-{
-	struct cpuidle_state *state = &drv->states[idx];
-
-	state->exit_latency	= cpuidle_params_table[idx].exit_latency;
-	state->target_residency	= cpuidle_params_table[idx].target_residency;
-	state->flags		= CPUIDLE_FLAG_TIME_VALID;
-	state->enter		= omap4_enter_idle;
-	sprintf(state->name, "C%d", idx + 1);
-	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
-}
-
 static inline struct omap4_idle_statedata *_fill_cstate_usage(
 					struct cpuidle_device *dev,
 					int idx)
@@ -196,37 +213,28 @@ int __init omap4_idle_init(void)
 	if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
 		return -ENODEV;
 
-
-	drv->safe_state_index = -1;
 	dev = &per_cpu(omap4_idle_dev, cpu_id);
 	dev->cpu = cpu_id;
 
-	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
-	_fill_cstate(drv, 0, "MPUSS ON");
-	drv->safe_state_index = 0;
 	cx = _fill_cstate_usage(dev, 0);
 	cx->cpu_state = PWRDM_POWER_ON;
 	cx->mpu_state = PWRDM_POWER_ON;
 	cx->mpu_logic_state = PWRDM_POWER_RET;
 
-	/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
-	_fill_cstate(drv, 1, "MPUSS CSWR");
 	cx = _fill_cstate_usage(dev, 1);
 	cx->cpu_state = PWRDM_POWER_OFF;
 	cx->mpu_state = PWRDM_POWER_RET;
 	cx->mpu_logic_state = PWRDM_POWER_RET;
 
-	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
-	_fill_cstate(drv, 2, "MPUSS OSWR");
 	cx = _fill_cstate_usage(dev, 2);
 	cx->cpu_state = PWRDM_POWER_OFF;
 	cx->mpu_state = PWRDM_POWER_RET;
 	cx->mpu_logic_state = PWRDM_POWER_OFF;
 
-	drv->state_count = OMAP4_NUM_STATES;
 	cpuidle_register_driver(&omap4_idle_driver);
 
-	dev->state_count = OMAP4_NUM_STATES;
+	dev->state_count = drv->state_count;
+
 	if (cpuidle_register_device(dev)) {
 		pr_err("%s: CPUidle register device failed\n", __func__);
 			return -EIO;
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Wed Mar 21 05:27:44 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 10:27:44 +0100
Subject: [RFC][PATCH 1/7] ARM: OMAP4: cpuidle - Remove unused valid field
In-Reply-To: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332322070-24577-2-git-send-email-daniel.lezcano@linaro.org>

The 'valid' field is never used in the code, let's remove it.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle44xx.c |    9 +++------
 1 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index cfdbb86..1210229 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -29,16 +29,15 @@ struct omap4_idle_statedata {
 	u32 cpu_state;
 	u32 mpu_logic_state;
 	u32 mpu_state;
-	u8 valid;
 };
 
 static struct cpuidle_params cpuidle_params_table[] = {
 	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
-	{.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
+	{.exit_latency = 2 + 2 , .target_residency = 5 },
 	/* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
-	{.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
+	{.exit_latency = 328 + 440 , .target_residency = 960 },
 	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
-	{.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
+	{.exit_latency = 460 + 518 , .target_residency = 1100 },
 };
 
 #define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
@@ -171,7 +170,6 @@ static inline struct omap4_idle_statedata *_fill_cstate_usage(
 	struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
 	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
 
-	cx->valid		= cpuidle_params_table[idx].valid;
 	cpuidle_set_statedata(state_usage, cx);
 
 	return cx;
@@ -207,7 +205,6 @@ int __init omap4_idle_init(void)
 	_fill_cstate(drv, 0, "MPUSS ON");
 	drv->safe_state_index = 0;
 	cx = _fill_cstate_usage(dev, 0);
-	cx->valid = 1;	/* C1 is always valid */
 	cx->cpu_state = PWRDM_POWER_ON;
 	cx->mpu_state = PWRDM_POWER_ON;
 	cx->mpu_logic_state = PWRDM_POWER_RET;
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Wed Mar 21 05:27:43 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 10:27:43 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
Message-ID: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>

This patchset is a proposition to improve a bit the code.
The changes are code cleanup and does not change the behavior of the
driver itself.

A couple a things call my intention. Why the cpuidle device is set for cpu0 only
and why the WFI is not used ?

Daniel Lezcano (7):
  ARM: OMAP4: cpuidle - Remove unused valid field
  ARM: OMAP4: cpuidle - Declare the states with the driver declaration
  ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
  ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
  ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
  ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
  ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
    time

 arch/arm/mach-omap2/cpuidle44xx.c |  126 ++++++++++++++++---------------------
 1 files changed, 54 insertions(+), 72 deletions(-)

-- 
1.7.5.4



From daniel.lezcano at linaro.org  Wed Mar 21 05:27:46 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 10:27:46 +0100
Subject: [RFC][PATCH 3/7] ARM: OMAP4: cpuidle - Remove the
 cpuidle_params_table table
In-Reply-To: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332322070-24577-4-git-send-email-daniel.lezcano@linaro.org>

We do not longer need this table as we defined the values
in the driver states.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle44xx.c |   11 +----------
 1 files changed, 1 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index cd6bee7..0455858 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -31,16 +31,7 @@ struct omap4_idle_statedata {
 	u32 mpu_state;
 };
 
-static struct cpuidle_params cpuidle_params_table[] = {
-	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
-	{.exit_latency = 2 + 2 , .target_residency = 5 },
-	/* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
-	{.exit_latency = 328 + 440 , .target_residency = 960 },
-	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
-	{.exit_latency = 460 + 518 , .target_residency = 1100 },
-};
-
-#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
+#define OMAP4_NUM_STATES 3
 
 struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
 static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Wed Mar 21 05:27:47 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 10:27:47 +0100
Subject: [RFC][PATCH 4/7] ARM: OMAP4: cpuidle - fix static omap4_idle_data
 declaration
In-Reply-To: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332322070-24577-5-git-send-email-daniel.lezcano@linaro.org>

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle44xx.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 0455858..254f97b 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -33,7 +33,7 @@ struct omap4_idle_statedata {
 
 #define OMAP4_NUM_STATES 3
 
-struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
+static struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
 static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
 
 /**
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Wed Mar 21 05:27:49 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 10:27:49 +0100
Subject: [RFC][PATCH 6/7] ARM: OMAP4: cpuidle - use the omap4_idle_data
 variable directly
In-Reply-To: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332322070-24577-7-git-send-email-daniel.lezcano@linaro.org>

We are storing the 'omap4_idle_data' in the private data field
if the cpuidle device. As we are using this variable only in this file,
that does not really make sense. Let's use the global variable directly
instead dereferencing pointers in an idle critical loop.

Also, that simplfies the code.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle44xx.c |   17 +++++------------
 1 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index e14cd56..cb91d1f 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -24,7 +24,7 @@
 
 #ifdef CONFIG_CPU_IDLE
 
-/* Machine specific information to be recorded in the C-state driver_data */
+/* Machine specific information */
 struct omap4_idle_statedata {
 	u32 cpu_state;
 	u32 mpu_logic_state;
@@ -67,8 +67,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
 			struct cpuidle_driver *drv,
 			int index)
 {
-	struct omap4_idle_statedata *cx =
-			cpuidle_get_statedata(&dev->states_usage[index]);
+	struct omap4_idle_statedata *cx = &omap4_idle_data[index];
 	struct timespec ts_preidle, ts_postidle, ts_idle;
 	u32 cpu1_state;
 	int idle_time;
@@ -92,7 +91,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
 	cpu1_state = pwrdm_read_pwrst(cpu1_pd);
 	if (cpu1_state != PWRDM_POWER_OFF) {
 		new_state_idx = drv->safe_state_index;
-		cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
+		cx = &omap4_idle_data[new_state_idx]
 	}
 
 	if (index > 0)
@@ -193,15 +192,9 @@ static inline struct omap4_idle_statedata *_fill_cstate_usage(
 					int idx)
 {
 	struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
-	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
-
-	cpuidle_set_statedata(state_usage, cx);
-
 	return cx;
 }
 
-
-
 /**
  * omap4_idle_init - Init routine for OMAP4 idle
  *
@@ -210,9 +203,9 @@ static inline struct omap4_idle_statedata *_fill_cstate_usage(
  */
 int __init omap4_idle_init(void)
 {
-	struct omap4_idle_statedata *cx;
-	struct cpuidle_device *dev;
+	struct omap4_idle_statedata *cx = &omap4_idle_data[index];
 	struct cpuidle_driver *drv = &omap4_idle_driver;
+	struct cpuidle_device *dev;
 	unsigned int cpu_id = 0;
 
 	mpu_pd = pwrdm_lookup("mpu_pwrdm");
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Wed Mar 21 05:27:50 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 10:27:50 +0100
Subject: [RFC][PATCH 7/7] ARM: OMAP4: cpuidle - remove omap4_idle_data
 initialization at boot time
In-Reply-To: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332322070-24577-8-git-send-email-daniel.lezcano@linaro.org>

We initialized it at compile time, no need to do that at boot
time.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle44xx.c |   26 +-------------------------
 1 files changed, 1 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index cb91d1f..fd220f9 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -33,7 +33,7 @@ struct omap4_idle_statedata {
 
 #define OMAP4_NUM_STATES 3
 
-static struct omap4_idle_statedata omap4_idle_data[] = {
+static struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES] = {
 	{
 		.cpu_state = PWRDM_POWER_ON,
 		.mpu_state = PWRDM_POWER_ON,
@@ -187,14 +187,6 @@ struct cpuidle_driver omap4_idle_driver = {
 	.state_count = OMAP4_NUM_STATES,
 };
 
-static inline struct omap4_idle_statedata *_fill_cstate_usage(
-					struct cpuidle_device *dev,
-					int idx)
-{
-	struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
-	return cx;
-}
-
 /**
  * omap4_idle_init - Init routine for OMAP4 idle
  *
@@ -203,7 +195,6 @@ static inline struct omap4_idle_statedata *_fill_cstate_usage(
  */
 int __init omap4_idle_init(void)
 {
-	struct omap4_idle_statedata *cx = &omap4_idle_data[index];
 	struct cpuidle_driver *drv = &omap4_idle_driver;
 	struct cpuidle_device *dev;
 	unsigned int cpu_id = 0;
@@ -217,21 +208,6 @@ int __init omap4_idle_init(void)
 	dev = &per_cpu(omap4_idle_dev, cpu_id);
 	dev->cpu = cpu_id;
 
-	cx = _fill_cstate_usage(dev, 0);
-	cx->cpu_state = PWRDM_POWER_ON;
-	cx->mpu_state = PWRDM_POWER_ON;
-	cx->mpu_logic_state = PWRDM_POWER_RET;
-
-	cx = _fill_cstate_usage(dev, 1);
-	cx->cpu_state = PWRDM_POWER_OFF;
-	cx->mpu_state = PWRDM_POWER_RET;
-	cx->mpu_logic_state = PWRDM_POWER_RET;
-
-	cx = _fill_cstate_usage(dev, 2);
-	cx->cpu_state = PWRDM_POWER_OFF;
-	cx->mpu_state = PWRDM_POWER_RET;
-	cx->mpu_logic_state = PWRDM_POWER_OFF;
-
 	cpuidle_register_driver(&omap4_idle_driver);
 
 	dev->state_count = drv->state_count;
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Wed Mar 21 05:27:48 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 10:27:48 +0100
Subject: [RFC][PATCH 5/7] ARM: OMAP4: cpuidle - Initialize omap4_idle_data at
 compile time
In-Reply-To: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332322070-24577-6-git-send-email-daniel.lezcano@linaro.org>

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle44xx.c |   19 ++++++++++++++++++-
 1 files changed, 18 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 254f97b..e14cd56 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -33,7 +33,24 @@ struct omap4_idle_statedata {
 
 #define OMAP4_NUM_STATES 3
 
-static struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
+static struct omap4_idle_statedata omap4_idle_data[] = {
+	{
+		.cpu_state = PWRDM_POWER_ON,
+		.mpu_state = PWRDM_POWER_ON,
+		.mpu_logic_state = PWRDM_POWER_RET,
+	},
+	{
+		.cpu_state = PWRDM_POWER_OFF,
+		.mpu_state = PWRDM_POWER_RET,
+		.mpu_logic_state = PWRDM_POWER_RET,
+	},
+	{
+		.cpu_state = PWRDM_POWER_OFF,
+		.mpu_state = PWRDM_POWER_RET,
+		.mpu_logic_state = PWRDM_POWER_OFF,
+	},
+};
+
 static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
 
 /**
-- 
1.7.5.4



From santosh.shilimkar at ti.com  Wed Mar 21 05:36:30 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 21 Mar 2012 15:06:30 +0530
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <CAMQu2gxit11dSbruPLCGx37TRwo9mwNCN9JXn0fZLDTVGu2GcA@mail.gmail.com>

On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
<daniel.lezcano at linaro.org> wrote:
> This patchset is a proposition to improve a bit the code.
> The changes are code cleanup and does not change the behavior of the
> driver itself.
>
Thanks. Will have a look at your series.

> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
Because the mainline code CPUIDLE is supported along with CPUhotplug.
This is going to change though with Couple CPUIDLE and corresponding
OMAP updates.

> and why the WFI is not used ?
>
I didn't get this question. Do you mean the generic WFI?
If yes, then, it's mainly because OMAP need additional
custom barriers.

Regards
Santosh


From santosh.shilimkar at ti.com  Wed Mar 21 05:41:12 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 21 Mar 2012 15:11:12 +0530
Subject: [RFC][PATCH 1/7] ARM: OMAP4: cpuidle - Remove unused valid field
In-Reply-To: <1332322070-24577-2-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <1332322070-24577-2-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <CAMQu2gw+GGnpG_s6TCk2fH094Lfmj1zgAZqQ4zdQmpj3ZZhu3w@mail.gmail.com>

On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
<daniel.lezcano at linaro.org> wrote:
> The 'valid' field is never used in the code, let's remove it.
>
> Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> ---
It is used during the registration. This field has been very useful for
debug when need to disable a C-state etc.
So unless and until there is a strong reason, i would like to retain it.

Regards
Santosh


From daniel.lezcano at linaro.org  Wed Mar 21 05:46:34 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 10:46:34 +0100
Subject: [RFC][PATCH 1/7] ARM: OMAP4: cpuidle - Remove unused valid field
In-Reply-To: <CAMQu2gw+GGnpG_s6TCk2fH094Lfmj1zgAZqQ4zdQmpj3ZZhu3w@mail.gmail.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <1332322070-24577-2-git-send-email-daniel.lezcano@linaro.org>
 <CAMQu2gw+GGnpG_s6TCk2fH094Lfmj1zgAZqQ4zdQmpj3ZZhu3w@mail.gmail.com>
Message-ID: <4F69A37A.7020606@linaro.org>

On 03/21/2012 10:41 AM, Shilimkar, Santosh wrote:
> On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
> <daniel.lezcano at linaro.org>  wrote:
>> The 'valid' field is never used in the code, let's remove it.
>>
>> Signed-off-by: Daniel Lezcano<daniel.lezcano at linaro.org>
>> ---
> It is used during the registration. This field has been very useful for
> debug when need to disable a C-state etc.
> So unless and until there is a strong reason, i would like to retain it.

IMO if it used for debug purpose, it should be moved to the debug code 
and if the debug code is not upstream, then that 'valid' should not be 
here but in the out-of-tree code.

By the way, this may be a debate for nothing because a patchset is on 
the way to disable C-states from sysfs.

-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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From santosh.shilimkar at ti.com  Wed Mar 21 05:50:20 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 21 Mar 2012 15:20:20 +0530
Subject: [RFC][PATCH 2/7] ARM: OMAP4: cpuidle - Declare the states with
 the driver declaration
In-Reply-To: <1332322070-24577-3-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <1332322070-24577-3-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <4F69A45C.5050802@ti.com>

+ Jean,

On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
> The cpuidle API allows to declare statically the states in the driver
> structure. Let's use it.
> We do no longer need the fill_cstate function called at runtime and
> by the way adding more instructions at boot time.
> 
> Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> ---
Jean added the fill_cstate() kind of helpers o.w in the old
cpuidle code9OMAP30, static tables were used. Ofcourse those
tables were not uinsg the cpuidle driver structure.

Regards
santosh


From daniel.lezcano at linaro.org  Wed Mar 21 05:51:33 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 10:51:33 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <CAMQu2gxit11dSbruPLCGx37TRwo9mwNCN9JXn0fZLDTVGu2GcA@mail.gmail.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <CAMQu2gxit11dSbruPLCGx37TRwo9mwNCN9JXn0fZLDTVGu2GcA@mail.gmail.com>
Message-ID: <4F69A4A5.5020208@linaro.org>

On 03/21/2012 10:36 AM, Shilimkar, Santosh wrote:
> On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
> <daniel.lezcano at linaro.org>  wrote:
>> This patchset is a proposition to improve a bit the code.
>> The changes are code cleanup and does not change the behavior of the
>> driver itself.
>>
> Thanks. Will have a look at your series.

Cool, thanks.

>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
> Because the mainline code CPUIDLE is supported along with CPUhotplug.
> This is going to change though with Couple CPUIDLE and corresponding
> OMAP updates.

Ok, thanks for the information. I will look deeper. What happens to cpu1 
when it is online and has nothing to do ?

>> and why the WFI is not used ?
>>
> I didn't get this question. Do you mean the generic WFI?

yes.

> If yes, then, it's mainly because OMAP need additional
> custom barriers.

Ah, ok. I am not sure if it is possible but that may be cool if we can 
call cpu_do_idle instead with additional barrier.


> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From santosh.shilimkar at ti.com  Wed Mar 21 05:51:50 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 21 Mar 2012 15:21:50 +0530
Subject: [RFC][PATCH 4/7] ARM: OMAP4: cpuidle - fix static omap4_idle_data
 declaration
In-Reply-To: <1332322070-24577-5-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <1332322070-24577-5-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <4F69A4B6.7030305@ti.com>

On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
> Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> ---
>  arch/arm/mach-omap2/cpuidle44xx.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
> index 0455858..254f97b 100644
> --- a/arch/arm/mach-omap2/cpuidle44xx.c
> +++ b/arch/arm/mach-omap2/cpuidle44xx.c
> @@ -33,7 +33,7 @@ struct omap4_idle_statedata {
>  
>  #define OMAP4_NUM_STATES 3
>  
> -struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
> +static struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
OK

Regards
santosh


From santosh.shilimkar at ti.com  Wed Mar 21 05:56:10 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 21 Mar 2012 15:26:10 +0530
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <4F69A4A5.5020208@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <CAMQu2gxit11dSbruPLCGx37TRwo9mwNCN9JXn0fZLDTVGu2GcA@mail.gmail.com>
 <4F69A4A5.5020208@linaro.org>
Message-ID: <4F69A5BA.1080804@ti.com>

On Wednesday 21 March 2012 03:21 PM, Daniel Lezcano wrote:
> On 03/21/2012 10:36 AM, Shilimkar, Santosh wrote:
>> On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
>> <daniel.lezcano at linaro.org>  wrote:
>>> This patchset is a proposition to improve a bit the code.
>>> The changes are code cleanup and does not change the behavior of the
>>> driver itself.
>>>
>> Thanks. Will have a look at your series.
> 
> Cool, thanks.
> 
>>> A couple a things call my intention. Why the cpuidle device is set
>>> for cpu0 only
>> Because the mainline code CPUIDLE is supported along with CPUhotplug.
>> This is going to change though with Couple CPUIDLE and corresponding
>> OMAP updates.
> 
> Ok, thanks for the information. I will look deeper. What happens to cpu1
> when it is online and has nothing to do ?
> 
>>> and why the WFI is not used ?
>>>
>> I didn't get this question. Do you mean the generic WFI?
> 
I execute default idle loop.

> yes.
> 
>> If yes, then, it's mainly because OMAP need additional
>> custom barriers.
> 
> Ah, ok. I am not sure if it is possible but that may be cool if we can
> call cpu_do_idle instead with additional barrier.
>
There is no need. Since code around WFI is customised, it make no sense
to call cpu_do_idle(0 ofr only that instruction sake.

Regards
Santosh


From ludovic.desroches at atmel.com  Wed Mar 21 06:02:11 2012
From: ludovic.desroches at atmel.com (Ludovic Desroches)
Date: Wed, 21 Mar 2012 11:02:11 +0100
Subject: [PATCH 3/6] mmc: atmel-mci: remove the need for
 CONFIG_MMC_ATMELMCI_DMA
In-Reply-To: <c7df6b7863557d95bb8457f5c2b4002ea44c86ff.1331826095.git.nicolas.ferre@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
 <c7df6b7863557d95bb8457f5c2b4002ea44c86ff.1331826095.git.nicolas.ferre@atmel.com>
Message-ID: <20120321100211.GJ11834@ldesroches-Latitude-E6320>

On Thu, Mar 15, 2012 at 04:57:19PM +0100, Nicolas Ferre wrote:
> This Kconfig option is not needed anymore, so remove it.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Thanks

Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Regards

Ludovic

> ---
>  drivers/mmc/host/Kconfig     |   10 ----------
>  drivers/mmc/host/atmel-mci.c |    2 --
>  2 files changed, 0 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 455a414..a6fc44a 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -288,16 +288,6 @@ config MMC_ATMELMCI
>  
>  	  If unsure, say N.
>  
> -config MMC_ATMELMCI_DMA
> -	bool "Atmel MCI DMA support"
> -	depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE
> -	help
> -	  Say Y here to have the Atmel MCI driver use a DMA engine to
> -	  do data transfers and thus increase the throughput and
> -	  reduce the CPU utilization.
> -
> -	  If unsure, say N.
> -
>  config MMC_IMX
>  	tristate "Motorola i.MX Multimedia Card Interface support"
>  	depends on ARCH_MX1
> diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> index e4449a5..b5693fd 100644
> --- a/drivers/mmc/host/atmel-mci.c
> +++ b/drivers/mmc/host/atmel-mci.c
> @@ -2164,10 +2164,8 @@ static int __exit atmci_remove(struct platform_device *pdev)
>  	atmci_readl(host, ATMCI_SR);
>  	clk_disable(host->mck);
>  
> -#ifdef CONFIG_MMC_ATMELMCI_DMA
>  	if (host->dma.chan)
>  		dma_release_channel(host->dma.chan);
> -#endif
>  
>  	free_irq(platform_get_irq(pdev, 0), host);
>  	iounmap(host->regs);
> -- 
> 1.7.9
> 


From santosh.shilimkar at ti.com  Wed Mar 21 06:03:14 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 21 Mar 2012 15:33:14 +0530
Subject: [RFC][PATCH 1/7] ARM: OMAP4: cpuidle - Remove unused valid field
In-Reply-To: <4F69A37A.7020606@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <1332322070-24577-2-git-send-email-daniel.lezcano@linaro.org>
 <CAMQu2gw+GGnpG_s6TCk2fH094Lfmj1zgAZqQ4zdQmpj3ZZhu3w@mail.gmail.com>
 <4F69A37A.7020606@linaro.org>
Message-ID: <4F69A762.5070006@ti.com>

On Wednesday 21 March 2012 03:16 PM, Daniel Lezcano wrote:
> On 03/21/2012 10:41 AM, Shilimkar, Santosh wrote:
>> On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
>> <daniel.lezcano at linaro.org>  wrote:
>>> The 'valid' field is never used in the code, let's remove it.
>>>
>>> Signed-off-by: Daniel Lezcano<daniel.lezcano at linaro.org>
>>> ---
>> It is used during the registration. This field has been very useful for
>> debug when need to disable a C-state etc.
>> So unless and until there is a strong reason, i would like to retain it.
> 
> IMO if it used for debug purpose, it should be moved to the debug code
> and if the debug code is not upstream, then that 'valid' should not be
> here but in the out-of-tree code.
>
When I said debug, I mean CPUIDLE debug and not any special debug code.

> By the way, this may be a debate for nothing because a patchset is on
> the way to disable C-states from sysfs.
> 
I see but sysfs won't solve that because you want to disable certain
C-state so that CPUIDLE driver don't use that state.

Let say if the C4 which is OSWR is broken. In such cases, just
setting valid flag let you disable it.

Again I don't have strong objection to this change.

Regards
santosh


From arnd at arndb.de  Wed Mar 21 04:59:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 21 Mar 2012 08:59:11 +0000
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <alpine.DEB.2.00.1203201731550.22974@utopia.booyaka.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <201203170905.33191.arnd@arndb.de>
 <alpine.DEB.2.00.1203201731550.22974@utopia.booyaka.com>
Message-ID: <201203210859.11899.arnd@arndb.de>

On Tuesday 20 March 2012, Paul Walmsley wrote:
> Hello Arnd,
> 
> On Sat, 17 Mar 2012, Arnd Bergmann wrote:
> 
> > I think it's rather pointless, because the option is not going to
> > be user selectable but will get selected by the platform unless I'm
> > mistaken. The platform maintainers that care already know the state
> > of the framework.
> 
> This is where we have differing views, I think.  Clearly, Sascha, 
> Saravana, Rob, and I have at least slightly different opinions on the 
> durability of the existing API and code.  So it seems reasonable to assume 
> that others who have not followed the development of the common clock code 
> might mistake the implementation or API as being stable and well-defined.
> 
> It sounds like the primary objection is to the use of CONFIG_EXPERIMENTAL.  
> So here is a patch to simply note the status of this code in its Kconfig 
> text.

Yes, looks good to me. If there are no objections, I'll apply this one.

Thanks,

	Arnd



From govindraj.raja at ti.com  Wed Mar 21 06:02:29 2012
From: govindraj.raja at ti.com (Govindraj.R)
Date: Wed, 21 Mar 2012 15:32:29 +0530
Subject: [RESEND PATCH] ARM :OMAP2+: UART: Remove some of uart default pads
Message-ID: <1332324149-16058-1-git-send-email-govindraj.raja@ti.com>

From: "Govindraj.R" <govindraj.raja at ti.com>

The following commit:
(7496ba3  ARM: OMAP2+: UART: Add default mux for all uarts)
added default pads for all uarts. But not all boards tend to
use all uarts and most of unused uart pins are muxed for
other purpose. This commit breaks the modules which where trying
to use unused uart pins on their boards.

So remove all default pads except uart1/3 as most boards
tend to use either uart1/3 as console port and use only tx/rx
lines, declare only those pads for uart1/3.
If any boards tend to use any other uart other uart1/3
the mux data should to passed from board file and init individual
uart port using omap_serial_init_port api.

These pads are needed not only for muxing but are also used to specify
pad wakeup capability for console uart, prior to commit specified we used
to do raw_write to mux pin to enable wakeup capability to uart1/2/3 now
with runtime changes we are using the hwmod/mux framework.

Cc: Felipe Balbi <balbi at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Reported-by: Tony Lindgren <tony at atomide.com>
Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
---
Based on Linux 3.3
Tested on Beagle XM and Zoom3 board.

 arch/arm/mach-omap2/serial.c |   78 ------------------------------------------
 1 files changed, 0 insertions(+), 78 deletions(-)

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 83ab5a2..4dccf14 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -124,14 +124,6 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {}
 #ifdef CONFIG_OMAP_MUX
 static struct omap_device_pad default_uart1_pads[] __initdata = {
 	{
-		.name	= "uart1_cts.uart1_cts",
-		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-	},
-	{
-		.name	= "uart1_rts.uart1_rts",
-		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-	},
-	{
 		.name	= "uart1_tx.uart1_tx",
 		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
 	},
@@ -143,37 +135,8 @@ static struct omap_device_pad default_uart1_pads[] __initdata = {
 	},
 };
 
-static struct omap_device_pad default_uart2_pads[] __initdata = {
-	{
-		.name	= "uart2_cts.uart2_cts",
-		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-	},
-	{
-		.name	= "uart2_rts.uart2_rts",
-		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-	},
-	{
-		.name	= "uart2_tx.uart2_tx",
-		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-	},
-	{
-		.name	= "uart2_rx.uart2_rx",
-		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-		.idle	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-	},
-};
-
 static struct omap_device_pad default_uart3_pads[] __initdata = {
 	{
-		.name	= "uart3_cts_rctx.uart3_cts_rctx",
-		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-	},
-	{
-		.name	= "uart3_rts_sd.uart3_rts_sd",
-		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-	},
-	{
 		.name	= "uart3_tx_irtx.uart3_tx_irtx",
 		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
 	},
@@ -185,32 +148,6 @@ static struct omap_device_pad default_uart3_pads[] __initdata = {
 	},
 };
 
-static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
-	{
-		.name   = "gpmc_wait2.uart4_tx",
-		.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-	},
-	{
-		.name	= "gpmc_wait3.uart4_rx",
-		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-	},
-};
-
-static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
-	{
-		.name	= "uart4_tx.uart4_tx",
-		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-	},
-	{
-		.name	= "uart4_rx.uart4_rx",
-		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-	},
-};
-
 static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
 {
 	switch (bdata->id) {
@@ -218,25 +155,10 @@ static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
 		bdata->pads = default_uart1_pads;
 		bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
 		break;
-	case 1:
-		bdata->pads = default_uart2_pads;
-		bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
-		break;
 	case 2:
 		bdata->pads = default_uart3_pads;
 		bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
 		break;
-	case 3:
-		if (cpu_is_omap44xx()) {
-			bdata->pads = default_omap4_uart4_pads;
-			bdata->pads_cnt =
-				ARRAY_SIZE(default_omap4_uart4_pads);
-		} else if (cpu_is_omap3630()) {
-			bdata->pads = default_omap36xx_uart4_pads;
-			bdata->pads_cnt =
-				ARRAY_SIZE(default_omap36xx_uart4_pads);
-		}
-		break;
 	default:
 		break;
 	}
-- 
1.7.5.4



From ludovic.desroches at atmel.com  Wed Mar 21 05:59:07 2012
From: ludovic.desroches at atmel.com (Ludovic Desroches)
Date: Wed, 21 Mar 2012 10:59:07 +0100
Subject: [PATCH 2/6] mmc: Kconfig: remove choice between at91_mci and
 atmel-mci
In-Reply-To: <d86c9743d2434e2c6a2a34cefe6c989e0efa9652.1331826095.git.nicolas.ferre@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
 <d86c9743d2434e2c6a2a34cefe6c989e0efa9652.1331826095.git.nicolas.ferre@atmel.com>
Message-ID: <20120321095907.GI11834@ldesroches-Latitude-E6320>

On Thu, Mar 15, 2012 at 04:57:18PM +0100, Nicolas Ferre wrote:
> This choice is not so important now that atmel-mci supports every
> Atmel AT91 SoC except AT91RM9200. As this newer driver is better
> maintained choose this one to avoid confusion.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Thanks for this patch, it's a new step to have only one mci driver.

Acked-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Regards

Ludovic

> ---
>  drivers/mmc/host/Kconfig |   13 ++-----------
>  1 files changed, 2 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 00fcbed..455a414 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -270,16 +270,9 @@ config MMC_AU1X
>  
>  	  If unsure, say N.
>  
> -choice
> -	prompt "Atmel SD/MMC Driver"
> -	depends on AVR32 || ARCH_AT91
> -	default MMC_ATMELMCI if AVR32
> -	help
> -	  Choose which driver to use for the Atmel MCI Silicon
> -
>  config MMC_AT91
>  	tristate "AT91 SD/MMC Card Interface support"
> -	depends on ARCH_AT91
> +	depends on ARCH_AT91RM9200
>  	help
>  	  This selects the AT91 MCI controller.
>  
> @@ -287,7 +280,7 @@ config MMC_AT91
>  
>  config MMC_ATMELMCI
>  	tristate "Atmel Multimedia Card Interface support"
> -	depends on AVR32 || ARCH_AT91
> +	depends on AVR32 || (ARCH_AT91 && !ARCH_AT91RM9200)
>  	help
>  	  This selects the Atmel Multimedia Card Interface driver. If
>  	  you have an AT32 (AVR32) or AT91 platform with a Multimedia
> @@ -295,8 +288,6 @@ config MMC_ATMELMCI
>  
>  	  If unsure, say N.
>  
> -endchoice
> -
>  config MMC_ATMELMCI_DMA
>  	bool "Atmel MCI DMA support"
>  	depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE
> -- 
> 1.7.9
> 


From santosh.shilimkar at ti.com  Wed Mar 21 06:07:46 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Wed, 21 Mar 2012 15:37:46 +0530
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <4F69A872.50203@ti.com>

Daniel,

On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
> This patchset is a proposition to improve a bit the code.
> The changes are code cleanup and does not change the behavior of the
> driver itself.
> 
> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
> and why the WFI is not used ?
> 
> Daniel Lezcano (7):
>   ARM: OMAP4: cpuidle - Remove unused valid field
>   ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>   ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>   ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>   ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>   ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>   ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>     time
> 
The series looks fine to me in general. This clean-up is applicable
for OMAP3 cpuidle code as well.

I want Jean to look at this series because some of his earlier
clean up has introduced those custom functions which
are getting removed in this series.

Regards
santosh




From govindraj.raja at ti.com  Wed Mar 21 06:24:58 2012
From: govindraj.raja at ti.com (Govindraj.R)
Date: Wed, 21 Mar 2012 15:54:58 +0530
Subject: [PATCH 0/3] OMAP2+: UART: Enable tx wakeup + remove cpu checks
Message-ID: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>

From: "Govindraj.R" <govindraj.raja at ti.com>

Based on Linux-OMAP tree uart branch.
(git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
remotes/origin/uart)

* Removes the cpu checks wherever possible and use version reg
  for populating features and errata's
* enable tx wakeup available in wer reg for applicable
  module revision's

Govindraj.R (3):
  OMAP2+: UART: Remove cpu checks for populating errata flags
  OMAP2+: UART: enable tx wakeup bit for wer reg
  OMAP2+: UART: replace omap34xx/omap4xx cpu checks with not omap24xx

 arch/arm/mach-omap2/serial.c                  |   13 +----
 arch/arm/plat-omap/include/plat/omap-serial.h |    8 +++-
 drivers/tty/serial/omap-serial.c              |   71 ++++++++++++++++++++++++-
 3 files changed, 78 insertions(+), 14 deletions(-)

-- 
1.7.5.4



From govindraj.raja at ti.com  Wed Mar 21 06:24:59 2012
From: govindraj.raja at ti.com (Govindraj.R)
Date: Wed, 21 Mar 2012 15:54:59 +0530
Subject: [PATCH 1/3] OMAP2+: UART: Remove cpu checks for populating errata
 flags
In-Reply-To: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
Message-ID: <1332325501-10467-2-git-send-email-govindraj.raja@ti.com>

From: "Govindraj.R" <govindraj.raja at ti.com>

Currently the errata is populated based on cpu checks this can
be removed and replaced with module version check of uart ip block.
MVR reg is provided within the uart reg map use the same
to populate the errata and thus now errata population and handling
can be managed within the driver itself.

Cc: Paul Walmsley <paul at pwsan.com>
Cc: Kevin Hilman <khilman at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
---
 arch/arm/mach-omap2/serial.c                  |    8 ---
 arch/arm/plat-omap/include/plat/omap-serial.h |    1 -
 drivers/tty/serial/omap-serial.c              |   62 ++++++++++++++++++++++++-
 3 files changed, 61 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index f590afc..330ee04 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -357,14 +357,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
 	omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
 	omap_up.autosuspend_timeout = info->autosuspend_timeout;
 
-	/* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
-	if (!cpu_is_omap2420() && !cpu_is_ti816x())
-		omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
-
-	/* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
-	if (cpu_is_omap34xx() || cpu_is_omap3630())
-		omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
-
 	pdata = &omap_up;
 	pdata_size = sizeof(struct omap_uart_port_info);
 
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 9ff4444..1a52725 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -65,7 +65,6 @@ struct omap_uart_port_info {
 	bool			dma_enabled;	/* To specify DMA Mode */
 	unsigned int		uartclk;	/* UART clock rate */
 	upf_t			flags;		/* UPF_* flags */
-	u32			errata;
 	unsigned int		dma_rx_buf_size;
 	unsigned int		dma_rx_timeout;
 	unsigned int		autosuspend_timeout;
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index f809041..c7666d6 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -44,6 +44,13 @@
 #include <plat/dmtimer.h>
 #include <plat/omap-serial.h>
 
+#define UART_BUILD_REVISION(x, y)	(((x) << 8) | (y))
+
+#define OMAP_UART_REV_42 0x0402
+#define OMAP_UART_REV_46 0x0406
+#define OMAP_UART_REV_52 0x0502
+#define OMAP_UART_REV_63 0x0603
+
 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
 
 /* SCR register bitmasks */
@@ -1346,6 +1353,58 @@ static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
 	return;
 }
 
+static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
+{
+	u32 mvr, scheme;
+	u16 revision, major, minor;
+
+	mvr = serial_in(up, UART_OMAP_MVER);
+
+	/* Check revision register scheme */
+	scheme = mvr & (0x03 << 30);
+	scheme >>= 30;
+
+	switch (scheme) {
+	case 0: /* Legacy Scheme: OMAP2/3 */
+		/* MINOR_REV[0:4], MAJOR_REV[4:7] */
+		major = (mvr & 0xf0) >> 4;
+		minor = (mvr & 0x0f);
+		break;
+	case 1:
+		/* New Scheme: OMAP4+ */
+		/* MINOR_REV[0:5], MAJOR_REV[8:10] */
+		major = (mvr & 0x7 << 8) >> 8;
+		minor = (mvr & 0x3f);
+		break;
+	default:
+		dev_warn(&up->pdev->dev,
+			"Unknown %s revision, defaulting to highest\n",
+			up->name);
+		/* highest possible revision */
+		major = 0xff;
+		minor = 0xff;
+	}
+
+	/* normalize revision for the driver */
+	revision = UART_BUILD_REVISION(major, minor);
+
+	switch (revision) {
+	case OMAP_UART_REV_46:
+		up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
+				UART_ERRATA_i291_DMA_FORCEIDLE);
+		break;
+	case OMAP_UART_REV_52:
+		up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
+				UART_ERRATA_i291_DMA_FORCEIDLE);
+		break;
+	case OMAP_UART_REV_63:
+		up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
+		break;
+	default:
+		break;
+	}
+}
+
 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
 {
 	struct omap_uart_port_info *omap_up_info;
@@ -1443,7 +1502,6 @@ static int serial_omap_probe(struct platform_device *pdev)
 						"%d\n", DEFAULT_CLK_SPEED);
 	}
 	up->uart_dma.uart_base = mem->start;
-	up->errata = omap_up_info->errata;
 
 	if (omap_up_info->dma_enabled) {
 		up->uart_dma.uart_dma_tx = dma_tx->start;
@@ -1473,6 +1531,8 @@ static int serial_omap_probe(struct platform_device *pdev)
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_get_sync(&pdev->dev);
 
+	omap_serial_fill_features_erratas(up);
+
 	ui[up->port.line] = up;
 	serial_omap_add_console_port(up);
 
-- 
1.7.5.4



From govindraj.raja at ti.com  Wed Mar 21 06:25:00 2012
From: govindraj.raja at ti.com (Govindraj.R)
Date: Wed, 21 Mar 2012 15:55:00 +0530
Subject: [PATCH 2/3] OMAP2+: UART: enable tx wakeup bit for wer reg
In-Reply-To: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
Message-ID: <1332325501-10467-3-git-send-email-govindraj.raja@ti.com>

From: "Govindraj.R" <govindraj.raja at ti.com>

>From omap36xx onwards the module wakeup enable reg
wer has TX wakeup bit available enable the same
by populating the necessary tx wakeup flag for the
applicable module ip blocks and use the same
while configuaring wer reg.

Also wer is not context restored, restore wer when
context is lost.

Cc: Paul Walmsley <paul at pwsan.com>
Cc: Felipe Balbi <balbi at ti.com
Cc: Kevin Hilman <khilman at ti.com>
Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
---
 arch/arm/plat-omap/include/plat/omap-serial.h |    7 +++++++
 drivers/tty/serial/omap-serial.c              |    9 ++++++++-
 2 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 1a52725..8a4ca5c 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -61,6 +61,11 @@
 #define UART_ERRATA_i202_MDR1_ACCESS	BIT(0)
 #define UART_ERRATA_i291_DMA_FORCEIDLE	BIT(1)
 
+#define OMAP_UART_TX_WAKEUP_EN	BIT(7)
+
+/* Feature flags */
+#define OMAP_UART_WER_HAS_TX_WAKEUP	BIT(0)
+
 struct omap_uart_port_info {
 	bool			dma_enabled;	/* To specify DMA Mode */
 	unsigned int		uartclk;	/* UART clock rate */
@@ -116,6 +121,7 @@ struct uart_omap_port {
 	unsigned char		dlh;
 	unsigned char		mdr1;
 	unsigned char		scr;
+	unsigned char		wer;
 
 	int			use_dma;
 	/*
@@ -129,6 +135,7 @@ struct uart_omap_port {
 	unsigned long		port_activity;
 	u32			context_loss_cnt;
 	u32			errata;
+	u32			features;
 	u8			wakeups_enabled;
 
 	struct pm_qos_request	pm_qos_request;
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index c7666d6..20d568d 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -585,7 +585,11 @@ static int serial_omap_startup(struct uart_port *port)
 	serial_out(up, UART_IER, up->ier);
 
 	/* Enable module level wake up */
-	serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
+	up->wer = OMAP_UART_WER_MOD_WKUP;
+	if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
+		up->wer |= OMAP_UART_TX_WAKEUP_EN;
+
+	serial_out(up, UART_OMAP_WER, up->wer);
 
 	pm_runtime_mark_last_busy(&up->pdev->dev);
 	pm_runtime_put_autosuspend(&up->pdev->dev);
@@ -1396,9 +1400,11 @@ static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
 	case OMAP_UART_REV_52:
 		up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
 				UART_ERRATA_i291_DMA_FORCEIDLE);
+		up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
 		break;
 	case OMAP_UART_REV_63:
 		up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
+		up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
 		break;
 	default:
 		break;
@@ -1629,6 +1635,7 @@ static void serial_omap_restore_context(struct uart_omap_port *up)
 		serial_omap_mdr1_errataset(up, up->mdr1);
 	else
 		serial_out(up, UART_OMAP_MDR1, up->mdr1);
+	serial_out(up, UART_OMAP_WER, up->wer);
 }
 
 static int serial_omap_runtime_suspend(struct device *dev)
-- 
1.7.5.4



From govindraj.raja at ti.com  Wed Mar 21 06:25:01 2012
From: govindraj.raja at ti.com (Govindraj.R)
Date: Wed, 21 Mar 2012 15:55:01 +0530
Subject: [PATCH 3/3] OMAP2+: UART: replace omap34xx/omap4xx cpu checks with
 not omap24xx
In-Reply-To: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
Message-ID: <1332325501-10467-4-git-send-email-govindraj.raja@ti.com>

From: "Govindraj.R" <govindraj.raja at ti.com>

Minor cleanup, replace all omap34xx/omap44xx cpu checks with
cpu is not omap24xx check.

Cc: Paul Walmsley <paul at pwsan.com>
Cc: Felipe Balbi <balbi at ti.com
Cc: Kevin Hilman <khilman at ti.com>
Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
---
 arch/arm/mach-omap2/serial.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 330ee04..83ab5a2 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -377,8 +377,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
 
 	oh->dev_attr = uart;
 
-	if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
-			&& !uart_debug)
+	if ((!cpu_is_omap24xx() && bdata->pads)	&& !uart_debug)
 		device_init_wakeup(&pdev->dev, true);
 }
 
@@ -401,7 +400,7 @@ void __init omap_serial_board_init(struct omap_uart_port_info *info)
 		bdata.pads = NULL;
 		bdata.pads_cnt = 0;
 
-		if (cpu_is_omap44xx() || cpu_is_omap34xx())
+		if (!cpu_is_omap24xx())
 			omap_serial_fill_default_pads(&bdata);
 
 		if (!info)
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Wed Mar 21 06:43:29 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 11:43:29 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <4F69A5BA.1080804@ti.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <CAMQu2gxit11dSbruPLCGx37TRwo9mwNCN9JXn0fZLDTVGu2GcA@mail.gmail.com>
 <4F69A4A5.5020208@linaro.org> <4F69A5BA.1080804@ti.com>
Message-ID: <4F69B0D1.6020608@linaro.org>

On 03/21/2012 10:56 AM, Santosh Shilimkar wrote:
> On Wednesday 21 March 2012 03:21 PM, Daniel Lezcano wrote:
>> On 03/21/2012 10:36 AM, Shilimkar, Santosh wrote:
>>> On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
>>> <daniel.lezcano at linaro.org>   wrote:
>>>> This patchset is a proposition to improve a bit the code.
>>>> The changes are code cleanup and does not change the behavior of the
>>>> driver itself.
>>>>
>>> Thanks. Will have a look at your series.
>>
>> Cool, thanks.
>>
>>>> A couple a things call my intention. Why the cpuidle device is set
>>>> for cpu0 only
>>> Because the mainline code CPUIDLE is supported along with CPUhotplug.
>>> This is going to change though with Couple CPUIDLE and corresponding
>>> OMAP updates.
>>
>> Ok, thanks for the information. I will look deeper. What happens to cpu1
>> when it is online and has nothing to do ?
>>
>>>> and why the WFI is not used ?
>>>>
>>> I didn't get this question. Do you mean the generic WFI?
>>
> I execute default idle loop.

So is it not possible to add a cpuidle device for cpu1 and define only 
one state for the 'wfi-for-omap' ?

>> yes.
>>
>>> If yes, then, it's mainly because OMAP need additional
>>> custom barriers.
>>
>> Ah, ok. I am not sure if it is possible but that may be cool if we can
>> call cpu_do_idle instead with additional barrier.
>>
> There is no need. Since code around WFI is customised, it make no sense
> to call cpu_do_idle(0 ofr only that instruction sake.

For my personal information, why the WFI is customised for omap4 ?

Thanks
   -- Daniel



-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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From m.szyprowski at samsung.com  Wed Mar 21 06:45:41 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 21 Mar 2012 11:45:41 +0100
Subject: [PATCH v4 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and
 EXYNOS5
In-Reply-To: <CAJuYYwTJsA1M1Qj2P1-1K=pWzi0BPo8YJNDSx4NqGC7NX0030g@mail.gmail.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
 <1331736138-28964-6-git-send-email-kgene.kim@samsung.com>
 <CAJuYYwTJsA1M1Qj2P1-1K=pWzi0BPo8YJNDSx4NqGC7NX0030g@mail.gmail.com>
Message-ID: <074401cd074f$c2946b90$47bd42b0$%szyprowski@samsung.com>

Hello,

On Wednesday, March 21, 2012 10:14 AM Thomas Abraham wrote:

> On 14 March 2012 20:12, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > Actually, the base address of uart is different between EXYNOS4
> > and EXYNOS5 and this patch enables to support uart for EXYNOS4
> > and EXYNOS5 SoCs at runtime.
> >
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> > ---
> 
> [...]
> 
> > diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-
> exynos/include/mach/debug-macro.S
> > index 6cacf16..6c857ff 100644
> > --- a/arch/arm/mach-exynos/include/mach/debug-macro.S
> > +++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
> > @@ -21,8 +21,13 @@
> > ? ? ? ? */
> >
> > ? ? ? ?.macro addruart, rp, rv, tmp
> > - ? ? ? ? ? ? ? ldr ? ? \rp, = S3C_PA_UART
> > - ? ? ? ? ? ? ? ldr ? ? \rv, = S3C_VA_UART
> > + ? ? ? ? ? ? ? mov ? ? \rp, #0x10000000
> 
> This is physical address of Exynos4/5 CPUID register which cannot be
> used here. And virtual address S5P_VA_CPUID also cannot be used here
> since this will be called before paging_init when earlyprintk boot
> param is used. So, with this change, earlyprintk does not work for
> both Exynos4 and Exynos5.

I confirm, printascii freeze the system on EXYNOS4 after that patch,
tested on Exynos4210 Nuri board.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From nicolas.ferre at atmel.com  Wed Mar 21 06:45:45 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 21 Mar 2012 11:45:45 +0100
Subject: [PATCH 0/6] AT91 drivers Kconfig cleanup
In-Reply-To: <7104123.IANagkT9hm@dtor-d630.eng.vmware.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
 <7104123.IANagkT9hm@dtor-d630.eng.vmware.com>
Message-ID: <4F69B159.5030101@atmel.com>

On 03/15/2012 05:50 PM, Dmitry Torokhov :
> On Thursday, March 15, 2012 04:57:16 PM Nicolas Ferre wrote:
>> This is a series which deals with AT91 drivers Kconfig entries. Its goal is
>> to remove too restrictive dependencies on SoC names.
>> This will allow to add support for newer SoC seamlessly.
>>
>> One question remains: should I submit those patches through dedicated
>> sub-maintainer's git trees or can I queue the whole series in arm-soc?
> 
> I'm fine if you queue input piece through arm-soc.

Ok, good: I have "Acknowledgement" by several maintainers: so yes, I
will send this series via arm-soc.

Is this means that I can add your "Acked-by"?

Best regards,
-- 
Nicolas Ferre


From daniel.lezcano at linaro.org  Wed Mar 21 06:49:01 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 11:49:01 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <4F69A872.50203@ti.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <4F69A872.50203@ti.com>
Message-ID: <4F69B21D.4050302@linaro.org>

On 03/21/2012 11:07 AM, Santosh Shilimkar wrote:
> Daniel,
>
> On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
>> This patchset is a proposition to improve a bit the code.
>> The changes are code cleanup and does not change the behavior of the
>> driver itself.
>>
>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
>> and why the WFI is not used ?
>>
>> Daniel Lezcano (7):
>>    ARM: OMAP4: cpuidle - Remove unused valid field
>>    ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>>    ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>>    ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>>    ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>>    ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>>    ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>>      time
>>
> The series looks fine to me in general. This clean-up is applicable
> for OMAP3 cpuidle code as well.

Yes, I am planning to do the same for omap3.

Thanks for reviewing.

   -- Daniel

> I want Jean to look at this series because some of his earlier
> clean up has introduced those custom functions which
> are getting removed in this series.
>
> Regards
> santosh
>
>


-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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From santosh.shilimkar at ti.com  Wed Mar 21 06:49:22 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 21 Mar 2012 16:19:22 +0530
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <4F69B0D1.6020608@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <CAMQu2gxit11dSbruPLCGx37TRwo9mwNCN9JXn0fZLDTVGu2GcA@mail.gmail.com>
 <4F69A4A5.5020208@linaro.org> <4F69A5BA.1080804@ti.com>
 <4F69B0D1.6020608@linaro.org>
Message-ID: <CAMQu2gwDtHBV=iPtxaOyyUHUVwPBTE2woY22U0SSdqruBNuo3Q@mail.gmail.com>

On Wed, Mar 21, 2012 at 4:13 PM, Daniel Lezcano
<daniel.lezcano at linaro.org> wrote:
> On 03/21/2012 10:56 AM, Santosh Shilimkar wrote:
>>
>> On Wednesday 21 March 2012 03:21 PM, Daniel Lezcano wrote:
>>>
>>> On 03/21/2012 10:36 AM, Shilimkar, Santosh wrote:
>>>>
>>>> On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
>>>> <daniel.lezcano at linaro.org> ? wrote:
>>>>>
>>>>> This patchset is a proposition to improve a bit the code.
>>>>> The changes are code cleanup and does not change the behavior of the
>>>>> driver itself.
>>>>>
>>>> Thanks. Will have a look at your series.
>>>
>>>
>>> Cool, thanks.
>>>
>>>>> A couple a things call my intention. Why the cpuidle device is set
>>>>> for cpu0 only
>>>>
>>>> Because the mainline code CPUIDLE is supported along with CPUhotplug.
>>>> This is going to change though with Couple CPUIDLE and corresponding
>>>> OMAP updates.
>>>
>>>
>>> Ok, thanks for the information. I will look deeper. What happens to cpu1
>>> when it is online and has nothing to do ?
>>>
>>>>> and why the WFI is not used ?
>>>>>
>>>> I didn't get this question. Do you mean the generic WFI?
>>>
>>>
>> I execute default idle loop.
>
>
> So is it not possible to add a cpuidle device for cpu1 and define only one
> state for the 'wfi-for-omap' ?
>
That's how my post was handling it. But after the review Kevin suggested
me to drop the CPU1 shallow state since it was same as default idle.

>
>>> yes.
>>>
>>>> If yes, then, it's mainly because OMAP need additional
>>>> custom barriers.
>>>
>>>
>>> Ah, ok. I am not sure if it is possible but that may be cool if we can
>>> call cpu_do_idle instead with additional barrier.
>>>
>> There is no need. Since code around WFI is customised, it make no sense
>> to call cpu_do_idle(0 ofr only that instruction sake.
>
>
> For my personal information, why the WFI is customised for omap4 ?
>
OMAP4 silicon has couple of hardware issues around interconnect
and needs to drain the axi buffers with strongly order writes to
ensure that data reaches to peripherals and not get stuck. That
lead to have custom function. Note that, the wfi instruction
itself is same.


From aisheng.dong at freescale.com  Wed Mar 21 07:06:15 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 21 Mar 2012 19:06:15 +0800
Subject: [PATCH v1 1/5] ARM: imx28: add basic dt support
In-Reply-To: <20328.33660.472382.117901@ipc1.ka-ro>
References: <20120315105927.GE13022@shlinux2.ap.freescale.net>
 <20321.53468.310199.875966@ipc1.ka-ro>
 <20120316030134.GA5161@shlinux2.ap.freescale.net>
 <20120318184749.BB15D3E07BF@localhost>
 <20326.55337.249575.289067@ipc1.ka-ro>
 <20120319150601.B783A3E05A5@localhost>
 <20327.25470.723875.916422@ipc1.ka-ro>
 <20120319220224.ABF5A3E0A04@localhost>
 <CAA+hA=R8hLZMyRASRim28MNzX4jyE3nsaJ3DPzgxDtUmqtH62w@mail.gmail.com>
 <20328.33660.472382.117901@ipc1.ka-ro>
Message-ID: <20120321110613.GA4905@shlinux2.ap.freescale.net>

On Tue, Mar 20, 2012 at 09:17:48PM +0800, Lothar Wa?mann wrote:
> Hi,
> 
> Dong Aisheng writes:
> > On Mon, Mar 19, 2012 at 3:02 PM, Grant Likely <grant.likely at secretlab.ca> wrote:
> > > On Mon, 19 Mar 2012 17:49:02 +0100, Lothar Wa?mann <LW at KARO-electronics.de> wrote:
> > >> Hi,
> > >>
> > >> Grant Likely writes:
> > >> > On Mon, 19 Mar 2012 07:54:33 +0100, Lothar Wa?mann <LW at KARO-electronics.de> wrote:
> > >> > > Grant Likely writes:
> > >> > > > On Fri, 16 Mar 2012 11:01:35 +0800, Dong Aisheng <aisheng.dong at freescale.com> wrote:
> > >> > > > > On Thu, Mar 15, 2012 at 07:22:04PM +0800, Lothar Wa?mann wrote:
> > >> > > > > > Dong Aisheng writes:
> > >> > > > > > > On Thu, Mar 15, 2012 at 02:53:29PM +0800, Lothar Wa?mann wrote:
> > >> > > > > > Anyway there is no definite spec how the MAC address(es) are stored
> > >> > > > > > in the fuse map. Thus reading the MAC from there is more or less
> > >> > > > > > platform specific.
> > >> > > > > >
> > >> > > > > It's just provide one more option since there are customers storing the MAC
> > >> > > > > in the fuse map.
> > >> > > >
> > >> > > > That should be straight forward to support; have a property that
> > >> > > > specifies the method used for fetching/calculating the MAC.
> > >> > > >
> > >> > > Executable code stored inside a DT blob? ;)
> > >> >
> > >> > I know you're joking here, but I'm going to answer seriously
> > >> > anyway... Absolutely not. ?What I'm suggesting is a property that
> > >> > specifies the method used to determine the mac address. ?Something
> > >> > like (off the top of my head):
> > >> >
> > >> > ? ? local-mac-address = [01 02 03 00 00 00];
> > >> > ? ? local-mac-mask = [0xff 0xff 0xff 0 0 0];
> > >> > ? ? mac-encoding = "append-serial-number";
> > >> >
> > >> That still does not specify where the remaining part of the MAC is
> > >> stored and how it should be retrieved.
> > >
> > > I'm suggesting that you define a string that means something specific;
> > > that hopefully can be shared by multiple platforms. ?For example,
> > > "append-serial-number" might mean start with the values selected by
> > > AND of local-mac-address and local-mac-mask, and OR in the board's
> > > serial number. ?You would need to define something that worked if this
> > > was the solution you used.
> > >
> > I'm intend to Grant's this suggestion.
> > This can be shared by all other imx platforms which stores mac address in
> > fuse map and this is commonly used by customer.
> > Then we do not need keep writing repeat code for different platforms
> > via platform
> > data.
> > 
> > For Lothar's question, we can add a property fuse_mac_offset to indicate
> > read mac from fuse map and where to read it.
> >
> That's not really enough. The format (big-endian vs. little-endian)
> may also differ. But it's not really necessary, if the solution with
> prom_update_property() works, since then platform code has full
> control over the MAC.
> 
> > For how many bytes to read, we can calculate it from the local-mac-mask.
> > For example, local-mac-mask = [0xff 0xff 0xff 0 0 0], we can get the size
> > as 3 bypes.
> > 
> > Then we have three properties:
> > local-mac-address = [01 02 03 00 00 00];
> > local-mac-mask = [0xff 0xff 0xff 0 0 0];
> > fuse_mac_offset = <1>;
> > 
> > In fec driver, the final mac address can be got by:
> > local-mac-address & local-mac-mask | (read_fuse(1) & 0xffffff)
> > 
> > Lathar,
> > Do you think if this is ok?
> >
> No. IMO the FEC driver itself should not read any fuses.
> Reading fuses is a SoC specific thing and the FEC driver should not
> depend on the idiosyncrasies of some SoC wrt. anything else but the
> implementation of the FEC itself.
> 
Yes, i think i'm agree with this point.
Okay, i will do that with prom_update_property.
Thanks for suggestion.

Regards
Dong Aisheng



From daniel.lezcano at linaro.org  Wed Mar 21 06:59:21 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 11:59:21 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <CAMQu2gwDtHBV=iPtxaOyyUHUVwPBTE2woY22U0SSdqruBNuo3Q@mail.gmail.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <CAMQu2gxit11dSbruPLCGx37TRwo9mwNCN9JXn0fZLDTVGu2GcA@mail.gmail.com>
 <4F69A4A5.5020208@linaro.org> <4F69A5BA.1080804@ti.com>
 <4F69B0D1.6020608@linaro.org>
 <CAMQu2gwDtHBV=iPtxaOyyUHUVwPBTE2woY22U0SSdqruBNuo3Q@mail.gmail.com>
Message-ID: <4F69B489.9070004@linaro.org>

On 03/21/2012 11:49 AM, Shilimkar, Santosh wrote:
> On Wed, Mar 21, 2012 at 4:13 PM, Daniel Lezcano
> <daniel.lezcano at linaro.org>  wrote:
>> On 03/21/2012 10:56 AM, Santosh Shilimkar wrote:
>>>
>>> On Wednesday 21 March 2012 03:21 PM, Daniel Lezcano wrote:
>>>>
>>>> On 03/21/2012 10:36 AM, Shilimkar, Santosh wrote:
>>>>>
>>>>> On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
>>>>> <daniel.lezcano at linaro.org>     wrote:
>>>>>>
>>>>>> This patchset is a proposition to improve a bit the code.
>>>>>> The changes are code cleanup and does not change the behavior of the
>>>>>> driver itself.
>>>>>>
>>>>> Thanks. Will have a look at your series.
>>>>
>>>>
>>>> Cool, thanks.
>>>>
>>>>>> A couple a things call my intention. Why the cpuidle device is set
>>>>>> for cpu0 only
>>>>>
>>>>> Because the mainline code CPUIDLE is supported along with CPUhotplug.
>>>>> This is going to change though with Couple CPUIDLE and corresponding
>>>>> OMAP updates.
>>>>
>>>>
>>>> Ok, thanks for the information. I will look deeper. What happens to cpu1
>>>> when it is online and has nothing to do ?
>>>>
>>>>>> and why the WFI is not used ?
>>>>>>
>>>>> I didn't get this question. Do you mean the generic WFI?
>>>>
>>>>
>>> I execute default idle loop.
>>
>>
>> So is it not possible to add a cpuidle device for cpu1 and define only one
>> state for the 'wfi-for-omap' ?
>>
> That's how my post was handling it. But after the review Kevin suggested
> me to drop the CPU1 shallow state since it was same as default idle.

Ok, thanks. I am asking that because the more I am looking at the 
different SoCs cpuidle drivers, the more I am convinced we can factor 
out more code across SoCs.

>>>> yes.
>>>>
>>>>> If yes, then, it's mainly because OMAP need additional
>>>>> custom barriers.
>>>>
>>>>
>>>> Ah, ok. I am not sure if it is possible but that may be cool if we can
>>>> call cpu_do_idle instead with additional barrier.
>>>>
>>> There is no need. Since code around WFI is customised, it make no sense
>>> to call cpu_do_idle(0 ofr only that instruction sake.
>>
>>
>> For my personal information, why the WFI is customised for omap4 ?
>>
> OMAP4 silicon has couple of hardware issues around interconnect
> and needs to drain the axi buffers with strongly order writes to
> ensure that data reaches to peripherals and not get stuck. That
> lead to have custom function. Note that, the wfi instruction
> itself is same.

Thanks for the explanation.

   -- Daniel

-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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<http://www.linaro.org/linaro-blog/> Blog



From hvaibhav at ti.com  Wed Mar 21 06:58:19 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Wed, 21 Mar 2012 16:28:19 +0530
Subject: [PATCH] ARM: OMAP2+: control: Add AM33XX control reg & sec clkctrl
 offset
Message-ID: <1332327499-29946-1-git-send-email-hvaibhav@ti.com>

Define AM33XX control register, in order to allow access to
control register address space, also add CONTROL_SEC_CLK_CTRL
register offset; both are required in clock tree data,
for wdt0 and timer0 clock source select configuration.

CONTROL.SEC_CLK_CTRL register is provided to select/configure
clock input for WDT0 and TIMER0.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
CC: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/control.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a406fd0..2858b80 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -28,6 +28,8 @@
 		OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)					\
 		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define AM33XX_CTRL_REGADDR(reg)					\
+		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
 #else
 #define OMAP242X_CTRL_REGADDR(reg)					\
 		OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -35,6 +37,8 @@
 		OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)					\
 		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define AM33XX_CTRL_REGADDR(reg)					\
+		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
 #endif /* __ASSEMBLY__ */

 /*
@@ -341,6 +345,7 @@
  * CONTROL AM33XX STATUS register
  */
 #define AM33XX_CONTROL_STATUS		0x040
+#define AM33XX_CONTROL_SEC_CLK_CTRL	0x1bc

 /*
  * CONTROL OMAP STATUS register to identify OMAP3 features
--
1.7.0.4



From aisheng.dong at freescale.com  Wed Mar 21 07:26:56 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 21 Mar 2012 19:26:56 +0800
Subject: [PATCH 1/1] net: phylib: remove the length limitation of mii
 bus id
In-Reply-To: <4F688F01.40604@openwrt.org>
References: <1332217386-3586-1-git-send-email-b29396@freescale.com>
 <CAAQ0ZWQEoPORMXsf3xV-KPP+hOHk2euj460fORyUALnfPn3Q8g@mail.gmail.com>
 <CAA+hA=Ttc9RDmK1fDPCtqLpf91DYDDFSf3E6zWQ6seyw7sNqTg@mail.gmail.com>
 <4F688F01.40604@openwrt.org>
Message-ID: <20120321112655.GB4905@shlinux2.ap.freescale.net>

On Tue, Mar 20, 2012 at 10:06:57PM +0800, Florian Fainelli wrote:
> Hi,
> 
> Le 03/20/12 11:53, Dong Aisheng a ?crit :
> > On Tue, Mar 20, 2012 at 1:32 AM, Shawn Guo<shawn.guo at linaro.org>  wrote:
> >> On 20 March 2012 12:23, Dong Aisheng<b29396 at freescale.com>  wrote:
> >>> From: Dong Aisheng<dong.aisheng at linaro.org>
> >>>
> >>> When convert to dt, the length of old mii bus id (17 bytes) is not
> >>> sufficent to use.
> >>> For example, the bus id could be 800f0000.ethernet-1:00 in DT.
> >>>
> >>> This patch removes the bus id length limitation by changing the
> >>> bus id to a const char pionter and user could dynamically set the
> >>> bus id via kasprintf function call.
> >>>
> >>> Since then no users use MII_BUS_ID_SIZE any more, just remove it.
> >>>
> >>> Signed-off-by: Dong Aisheng<dong.aisheng at linaro.org>
> >>> ---
> >>> The simplest way may just change MII_BUS_ID_SIZE to a more bigger size,
> >>> but i'm not sure that's gonna be accepted.
> >>
> >> The simplest fix has been applied on -next tree as below.
> >>
> > Oh, i missed it, seems my patch covers that change.
> > But that patch only fixed wrong phy_name buffer length issue.
> > My patch is totally remove the length limitation of bus id and phy_name
> > or the bus id name will be truncated if it's longer than MII_BUS_ID_SIZE
> > which is not a comfortable limitation.
> 
> Then just increase the bus id size locally for your driver. Drivers that 
> can live with a static allocation are better of using it.
> 
That's the common part, can not change it locally by driver.
Or we can change MII_BUS_ID_SIZE to a more big size in common code,
maybe 30 bytes, but when is the end?

> Your patch completely missed testing the return value of kasprintf(), 
> and its return value can be NULL, please fix this at least.
> 
Yes, thanks for the reminder.
I will fix it.

Regards
Dong Aisheng



From hvaibhav at ti.com  Wed Mar 21 07:29:24 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 21 Mar 2012 11:29:24 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>	<87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831823816@DBDE01.ent.ti.com>

On Mon, Mar 19, 2012 at 17:14:30, Ming Lei wrote:
> On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >
> > I think you made very good point here. With the above patch, we are almost missing the capability of registering dmtimer as a clocksource for OMAP.
> > It will always use 32k-counter, and never fall back to dmtimer.
> >
> > Then the only options we have here is,
> >
> > 1) Register both the timers, 32k-counter and dmtimer for clocksource; let
> > ? Kernel pick up best rating clocksource out of these two.
> >
> > ? In case of OMAP1/2/3/4, kernel will use dmtimer, since it has better
> > ? Rating. User can choose the 32k-counter clocksource via bootargs.
> >
> > ? Impact: without bootargs for clocksource selection, kernel will choose
> > ? ? dmtimer, impacting loss of time during suspend/resume.
> >
> >
> > 2) Let the current code be as is, means, the clocksource registration will
> > ? Happened based on "#ifdef CONFIG_OMAP_32K_TIMER" and this option
> > ? selection will be Controlled by Kconfig rules.
> 
> How about the 3rd option?
> 
> 3), take the way in your patch 1) at default, but will switch to
> register dmtimer
> directly and bypass 32k-counter if user need it via kernel parameter.
> 
> As far as I can think of, the situations required for dmtimer are high-frequency
> perf sample and high precision trace points, so looks it is OK to take
> 32k-counter
> at default.
> 
But if you register both the timers (dmtimer & 32ksync), then initially kernel will only pick up dmtimer, as this has better rating. And late in
the boot sequence clocksource switch will happen, base on 
kernel parameter (clocksource=).

So logically dmtimer will be always used as a default here.

Thanks,
Vaibhav

> Thanks,
> -- 
> Ming Lei
> 



From viresh.kumar at st.com  Wed Mar 21 07:32:05 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 21 Mar 2012 17:02:05 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203151339.36173.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <4F61AFAB.6080301@st.com> <201203151138.51508.sr@denx.de>
 <201203151339.36173.arnd@arndb.de>
Message-ID: <4F69BC35.4010400@st.com>

On 3/15/2012 7:09 PM, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Stefan Roese wrote:
>> On Thursday 15 March 2012 10:00:27 Viresh Kumar wrote:
>>> On 3/15/2012 2:18 PM, Stefan Roese wrote:
>>>>>>>> +static const struct of_device_id vic_of_match[] __initconst = {
>>>>>>>> +     { .compatible = "arm,pl190-vic", .data = vic_of_init, },
>>>>>>>> +     { /* Sentinel */ }
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +static void __init spear6xx_dt_init_irq(void)
>>>>>>>> +{
>>>>>>>> +     of_irq_init(vic_of_match);
>>>>>>>> +}
>>>>>>>> +
>>>>>>
>>>>>> What about adding this routine in vic.c file, which can then be used
>>>>>> by all platforms, instead of replicating this code.
>>>>
>>>> We can't move vic_of_match to the vic.c, since there are differences
>>>> between the boards using it. And only moving spear6xx_dt_init_irq()
>>>> (renamed of course) doesn't seem worth it.
>>>
>>> I knew this. Actually my thought was, we have two compatible strings for
>>> vic: pl190 and pl192.
>>>
>>> So, create two vic_of_match* arrays and two vic*_dt_init_irq() routines.
>>> That will solve the issue i believe.
>>
>> I still don't think its worth it. But please feel free to send an add-on 
>> patch, to "clean this up".
> 
> What's wrong with one vic_dt_init_irq() function and an array with two entries?

Hey Arnd,

Actually i was doing 3xx DT porting and again came to this thing. I believe what
you suggested should be fine too as the actual vic model/name is going to be
passed from .dts file.

If this is acceptable to you, i will add patch for both vic & gic in my
patchset.

-- 
viresh


From aisheng.dong at freescale.com  Wed Mar 21 07:45:17 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 21 Mar 2012 19:45:17 +0800
Subject: [PATCH 1/1] net: phylib: add error checking if no phy found
In-Reply-To: <4F5F5ABF.5030103@openwrt.org>
References: <1331636302-18256-1-git-send-email-b29396@freescale.com>
 <4F5F5ABF.5030103@openwrt.org>
Message-ID: <20120321114516.GC4905@shlinux2.ap.freescale.net>

On Tue, Mar 13, 2012 at 10:33:35PM +0800, Florian Fainelli wrote:
> Hi,
> 
> Le 03/13/12 11:58, Dong Aisheng a ?crit :
> > From: Dong Aisheng<dong.aisheng at linaro.org>
> >
> > Signed-off-by: Dong Aisheng<dong.aisheng at linaro.org>
> > ---
> >   drivers/net/phy/mdio_bus.c |   11 ++++++++++-
> >   1 files changed, 10 insertions(+), 1 deletions(-)
> >
> > diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
> > index 88cc5db..d8e044d 100644
> > --- a/drivers/net/phy/mdio_bus.c
> > +++ b/drivers/net/phy/mdio_bus.c
> > @@ -101,6 +101,7 @@ static struct class mdio_bus_class = {
> >   int mdiobus_register(struct mii_bus *bus)
> >   {
> >   	int i, err;
> > +	u32 phynum = 0;
> >
> >   	if (NULL == bus || NULL == bus->name ||
> >   			NULL == bus->read ||
> > @@ -134,12 +135,20 @@ int mdiobus_register(struct mii_bus *bus)
> >   			if (IS_ERR(phydev)) {
> >   				err = PTR_ERR(phydev);
> >   				goto error;
> > +			} else if (phydev != NULL) {
> > +				phynum++;
> >   			}
> >   		}
> >   	}
> >
> > +	if (!phynum) {
> > +		err = -ENODEV;
> > +		printk(KERN_ERR "%s: no phys found\n", bus->name);
> > +		goto error;
> > +	}
> 
> I am not sure if this is a good idea to change it, especially if:
> - the MII bus probing is also done later (quite some drivers do this)
> - if we want to attach a fixed PHY because we could not probe one at 
> registration time
> 
You're correct.
It seems keep it as before is the right solution right now.
Thanks for the info.

Regards
Dong Aisheng



From hvaibhav at ti.com  Wed Mar 21 07:42:26 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 21 Mar 2012 11:42:26 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <4F672364.3020403@ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>	<87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>

On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
> On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
> > On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >>
> >> I think you made very good point here. With the above patch, we are almost missing the capability of registering dmtimer as a clocksource for OMAP.
> >> It will always use 32k-counter, and never fall back to dmtimer.
> >>
> >> Then the only options we have here is,
> >>
> >> 1) Register both the timers, 32k-counter and dmtimer for clocksource; let
> >>   Kernel pick up best rating clocksource out of these two.
> >>
> >>   In case of OMAP1/2/3/4, kernel will use dmtimer, since it has better
> >>   Rating. User can choose the 32k-counter clocksource via bootargs.
> >>
> >>   Impact: without bootargs for clocksource selection, kernel will choose
> >>     dmtimer, impacting loss of time during suspend/resume.
> >>
> This is the right option. The problem is gptimer clocksource
> doesn't work across power transitions and hence it is broken.
> 
> Even for the perf, with PM enabled, dmtimer can't be used or it needs
> to be used with 32KHz clock which makes it no better than sync timer.
> 
> So here keeping 32K sync timer is default clocksource makes sense since
> it is the only working and viable option.
> 
> So what can be done is register both 32K and gptimer together but make
> gptimer clocksource registration depends on PM enabled.
> 
> This should solve all the needs I guess.
> 

I am not sure this will work on all platforms, for example, AM33XX, where
We do not have 32ksync timer available, but we need PM support. Also, I 
personally think, we should not again use compile time option here.

So the only option I have here is, register both the clocksources, let dmtimer be a default clocksource for the kernel (since it has better rating),
And based on kernel parameter user can change the clocksource, specially 
for PM use-cases.


Implementation point of view, I just need to do something like,

static void __init omap2_gp_clocksource_init(int gptimer_id,
							const char *fck_source)
{
	int res;

	res = omap_init_clocksource_32k();
	if (!res)
		pr_err("failed to register 32ksync counter as a clocksource\n");

	/* 
	 * Continue with dmtimer registration as well, irrespective of
	 * whether 32ksync timer registration succeeded or not.
	 */
}

> >>
> >> 2) Let the current code be as is, means, the clocksource registration will
> >>   Happened based on "#ifdef CONFIG_OMAP_32K_TIMER" and this option
> >>   selection will be Controlled by Kconfig rules.
> > 
> We should get rid off CONFIG_OMAP_32K_TIMER.
> 

Agreed, I will take this activity once I close on this.

Thanks,
Vaibhav

> Regards
> Santosh
> 
> 



From shubhrajyoti at ti.com  Wed Mar 21 07:52:22 2012
From: shubhrajyoti at ti.com (Shubhrajyoti D)
Date: Wed, 21 Mar 2012 17:22:22 +0530
Subject: [PATCH v2] omap-serial: Fix the error handling in the omap_serial
 probe
Message-ID: <1332330742-22375-1-git-send-email-shubhrajyoti@ti.com>

The patch does the following

- The pm_runtime_disable is called in the remove not in the error
  case of probe.The patch calls the pm_runtime_disable in the error
  case.
- Calls pm_runtime_put in the error case.
- The  up is not freed in the error path. Fix the memory leak by using
  devm_* so that the memory need not be freed in the driver.
- Also the iounmap is not called fix the same by calling using devm_ioremap.
- Make the name of the error tags more meaningful.

Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Govindraj.R <govindraj.raja at ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti at ti.com>
---
Changes from the v1:
Use devm_* functions instead of freeing in the driver.

 drivers/tty/serial/omap-serial.c |   43 +++++++++++++++++--------------------
 1 files changed, 20 insertions(+), 23 deletions(-)

diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index 1e193fc..5386239 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -1381,29 +1381,24 @@ static int serial_omap_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	if (!request_mem_region(mem->start, resource_size(mem),
+	if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
 				pdev->dev.driver->name)) {
 		dev_err(&pdev->dev, "memory region already claimed\n");
 		return -EBUSY;
 	}
 
 	dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
-	if (!dma_rx) {
-		ret = -EINVAL;
-		goto err;
-	}
+	if (!dma_rx)
+		return -ENXIO;
 
 	dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
-	if (!dma_tx) {
-		ret = -EINVAL;
-		goto err;
-	}
+	if (!dma_tx)
+		return -ENXIO;
+
+	up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
+	if (!up)
+		return -ENOMEM;
 
-	up = kzalloc(sizeof(*up), GFP_KERNEL);
-	if (up == NULL) {
-		ret = -ENOMEM;
-		goto do_release_region;
-	}
 	up->pdev = pdev;
 	up->port.dev = &pdev->dev;
 	up->port.type = PORT_OMAP;
@@ -1423,16 +1418,17 @@ static int serial_omap_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
 								up->port.line);
 		ret = -ENODEV;
-		goto err;
+		goto err_port_line;
 	}
 
 	sprintf(up->name, "OMAP UART%d", up->port.line);
 	up->port.mapbase = mem->start;
-	up->port.membase = ioremap(mem->start, resource_size(mem));
+	up->port.membase = devm_ioremap(&pdev->dev, mem->start,
+						resource_size(mem));
 	if (!up->port.membase) {
 		dev_err(&pdev->dev, "can't ioremap UART\n");
 		ret = -ENOMEM;
-		goto err;
+		goto err_ioremap;
 	}
 
 	up->port.flags = omap_up_info->flags;
@@ -1478,16 +1474,19 @@ static int serial_omap_probe(struct platform_device *pdev)
 
 	ret = uart_add_one_port(&serial_omap_reg, &up->port);
 	if (ret != 0)
-		goto do_release_region;
+		goto err_add_port;
 
 	pm_runtime_put(&pdev->dev);
 	platform_set_drvdata(pdev, up);
 	return 0;
-err:
+
+err_add_port:
+	pm_runtime_put(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+err_ioremap:
+err_port_line:
 	dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
 				pdev->id, __func__, ret);
-do_release_region:
-	release_mem_region(mem->start, resource_size(mem));
 	return ret;
 }
 
@@ -1499,8 +1498,6 @@ static int serial_omap_remove(struct platform_device *dev)
 		pm_runtime_disable(&up->pdev->dev);
 		uart_remove_one_port(&serial_omap_reg, &up->port);
 		pm_qos_remove_request(&up->pm_qos_request);
-
-		kfree(up);
 	}
 
 	platform_set_drvdata(dev, NULL);
-- 
1.7.1



From viresh.linux at gmail.com  Wed Mar 21 07:58:27 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Wed, 21 Mar 2012 17:28:27 +0530
Subject: [PATCH v3] serial: PL011: clear pending interrupts
In-Reply-To: <1331641643-25929-1-git-send-email-linus.walleij@stericsson.com>
References: <1331641643-25929-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <CAOh2x=nh-aiJ1FQecm=5WsNw=Fph5osNh5C2YU6x9TGrKBoMmA@mail.gmail.com>

On Tue, Mar 13, 2012 at 5:57 PM, Linus Walleij
<linus.walleij at stericsson.com> wrote:
> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
> @@ -1927,6 +1930,10 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
> ? ? ? ? ? ? ? ?goto unmap;
> ? ? ? ?}
>
> + ? ? ? /* Ensure interrupts from this UART are masked and cleared */
> + ? ? ? writew(0, uap->port.membase + UART011_IMSC);
> + ? ? ? writew(0xffff, uap->port.membase + UART011_ICR);
> +


Hey Linus,

I was working on v3.3 and found a crash for my SoC. When i checked i got a crash
due to above changes.

There are two issues here
 - uap->port is uninitialized
 - clk is not enabled.

How is this working for you?

--
viresh


From arnd at arndb.de  Wed Mar 21 08:36:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 21 Mar 2012 12:36:37 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <4F69BC35.4010400@st.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203151339.36173.arnd@arndb.de> <4F69BC35.4010400@st.com>
Message-ID: <201203211236.37891.arnd@arndb.de>

On Wednesday 21 March 2012, Viresh Kumar wrote:
> > 
> > What's wrong with one vic_dt_init_irq() function and an array with two entries?
> 
> Hey Arnd,
> 
> Actually i was doing 3xx DT porting and again came to this thing. I believe what
> you suggested should be fine too as the actual vic model/name is going to be
> passed from .dts file.
> 
> If this is acceptable to you, i will add patch for both vic & gic in my
> patchset.

Ok, sounds good.

Let's make sure we're on the same page with the process though. I hope
you're aware that I took Stefan's spear6xx v5 patch. I just now saw that
you were not on Cc on the submission of the patch nor on my reply, but you
had given your Ack on the patch. Just let me know how you want to handle
these things in the future -- the normal way would be to always let you
forward the patches to me, rather than having them applied to arm-soc
directly.

Regarding the spear3xx patches, I'm looking forward to your patches.
I think spear is simple and clean enough that it can serve as an example
for others doing DT conversion. Do you also plan to unify 3xx and 6xx?
I think there is hardly anything left in mach-spear6xx that justifies
having a separate platform, especially since with the DT conversion done,
we can actually remove most of the header file contents as well.

	Arnd


From FlorianSchandinat at gmx.de  Wed Mar 21 08:47:46 2012
From: FlorianSchandinat at gmx.de (Florian Tobias Schandinat)
Date: Wed, 21 Mar 2012 12:47:46 +0000
Subject: [PATCH] ARM: fix lcd power build failure in collie_defconfig
In-Reply-To: <1331051502-22361-1-git-send-email-paul.gortmaker@windriver.com>
References: <1331051502-22361-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <4F69CDF2.3020609@gmx.de>

On 03/06/2012 04:31 PM, Paul Gortmaker wrote:
> Commit 086ada54abaa4316e8603f02410fe8ebc9ba2de1 (linux-next)
> 
>   "FB: sa1100: remove global sa1100fb_.*_power function pointers"
> 
> got rid of all instances but one in locomolcd.c -- which was
> conditional on CONFIG_SA1100_COLLIE.  The associated .power
> field which replaces the global is populated in mach-sa1100/collie.c
> so move the assignment there, but make it conditional on the
> locomolcd support, so use CONFIG_BACKLIGHT_LOCOMO in that file.
> 
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>

What about this patch?
I assumed Russel would pick it up as the commit referenced is also in
his tree but it looks like this patch is still not in -next. Any reasons
for this?


Best regards,

Florian Tobias Schandinat

> 
> diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
> index 48885b7..c7f418b 100644
> --- a/arch/arm/mach-sa1100/collie.c
> +++ b/arch/arm/mach-sa1100/collie.c
> @@ -313,6 +313,10 @@ static struct sa1100fb_mach_info collie_lcd_info = {
>  
>  	.lccr0		= LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
>  	.lccr3		= LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
> +
> +#ifdef CONFIG_BACKLIGHT_LOCOMO
> +	.lcd_power	= locomolcd_power
> +#endif
>  };
>  
>  static void __init collie_init(void)
> diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
> index 52acda7..f33679d 100644
> --- a/arch/arm/mach-sa1100/include/mach/collie.h
> +++ b/arch/arm/mach-sa1100/include/mach/collie.h
> @@ -1,7 +1,7 @@
>  /*
>   * arch/arm/mach-sa1100/include/mach/collie.h
>   *
> - * This file contains the hardware specific definitions for Assabet
> + * This file contains the hardware specific definitions for Collie
>   * Only include this file from SA1100-specific files.
>   *
>   * ChangeLog:
> @@ -13,6 +13,7 @@
>  #ifndef __ASM_ARCH_COLLIE_H
>  #define __ASM_ARCH_COLLIE_H
>  
> +extern void locomolcd_power(int on);
>  
>  #define COLLIE_SCOOP_GPIO_BASE	(GPIO_MAX + 1)
>  #define COLLIE_GPIO_CHARGE_ON	(COLLIE_SCOOP_GPIO_BASE + 0)
> diff --git a/drivers/video/backlight/locomolcd.c b/drivers/video/backlight/locomolcd.c
> index be20b5c..3a6d541 100644
> --- a/drivers/video/backlight/locomolcd.c
> +++ b/drivers/video/backlight/locomolcd.c
> @@ -229,14 +229,7 @@ static struct locomo_driver poodle_lcd_driver = {
>  
>  static int __init locomolcd_init(void)
>  {
> -	int ret = locomo_driver_register(&poodle_lcd_driver);
> -	if (ret)
> -		return ret;
> -
> -#ifdef CONFIG_SA1100_COLLIE
> -	sa1100fb_lcd_power = locomolcd_power;
> -#endif
> -	return 0;
> +	return locomo_driver_register(&poodle_lcd_driver);
>  }
>  
>  static void __exit locomolcd_exit(void)



From robherring2 at gmail.com  Wed Mar 21 09:09:57 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 21 Mar 2012 08:09:57 -0500
Subject: Device tree and IO map_desc.
In-Reply-To: <CAKON4OyHRVvdtZGt+HiCnsRT_5zTuDVBVgOx22kFC2xxFLnD+Q@mail.gmail.com>
References: <CAKON4OyHRVvdtZGt+HiCnsRT_5zTuDVBVgOx22kFC2xxFLnD+Q@mail.gmail.com>
Message-ID: <4F69D325.1000500@gmail.com>

On 03/20/2012 11:52 AM, jonsmirl at gmail.com wrote:
> Is there a helper for building the IO map_desc from the device tree?
> 

No. This is one of those things that device tree cannot have knowledge
of what needs to be statically mapped as that's not a h/w description.

We could probably have a list of nodes to map and extract the size and
physical addresses from the DT. There's lots of register defines
typically associated with the static mappings, so you would still have
duplicated information.

> For example on Versatile. All of this map_io data is already in the
> device tree, it is just repeated here.
> 
> 
> DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
> 	.map_io		= versatile_map_io,
> 	.init_early	= versatile_init_early,
> ....
> MACHINE_END
> 
> void __init versatile_map_io(void)
> {
> 	iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
> }
> 
> static struct map_desc versatile_io_desc[] __initdata = {
> 	{
> 		.virtual	=  IO_ADDRESS(VERSATILE_SYS_BASE),
> 		.pfn		= __phys_to_pfn(VERSATILE_SYS_BASE),
> 		.length		= SZ_4K,
> 		.type		= MT_DEVICE
> 	}, {
> 		.virtual	=  IO_ADDRESS(VERSATILE_SIC_BASE),
> 		.pfn		= __phys_to_pfn(VERSATILE_SIC_BASE),
> 		.length		= SZ_4K,
> 		.type		= MT_DEVICE
> 	}, {
> 		.virtual	=  IO_ADDRESS(VERSATILE_VIC_BASE),
> 		.pfn		= __phys_to_pfn(VERSATILE_VIC_BASE),
> 		.length		= SZ_4K,
> 		.type		= MT_DEVICE

The SIC and VIC should get converted to ioremap and using of_irq_init.
There's already DT init support for the VIC at least, so the conversion
should be easy. I think Linus W was working on this.

Rob

> 	}, {
> ...
> 



From jean.pihet at newoldbits.com  Wed Mar 21 09:19:05 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 21 Mar 2012 14:19:05 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <4F69A872.50203@ti.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <4F69A872.50203@ti.com>
Message-ID: <CAORVsuUL3Z_vw+n26eWaa8eAJ0yhXB=VRNmuCeSZjStG527Gag@mail.gmail.com>

Hi Santosh, Daniel,

On Wed, Mar 21, 2012 at 11:07 AM, Santosh Shilimkar
<santosh.shilimkar at ti.com> wrote:
> Daniel,
>
> On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
>> This patchset is a proposition to improve a bit the code.
>> The changes are code cleanup and does not change the behavior of the
>> driver itself.
>>
>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
>> and why the WFI is not used ?
>>
>> Daniel Lezcano (7):
>> ? ARM: OMAP4: cpuidle - Remove unused valid field
>> ? ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>> ? ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>> ? ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>> ? ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>> ? ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>> ? ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>> ? ? time
>>
> The series looks fine to me in general. This clean-up is applicable
> for OMAP3 cpuidle code as well.
>
> I want Jean to look at this series because some of his earlier
> clean up has introduced those custom functions which
> are getting removed in this series.
I am OK with the patch set, I only have minor remarks to the individual patches.

Reviewed-by: Jean Pihet <j-pihet at ti.com>

>
> Regards
> santosh
>
>

Thanks!
Jean


From nicolas.pitre at linaro.org  Wed Mar 21 09:23:44 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Wed, 21 Mar 2012 09:23:44 -0400 (EDT)
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <alpine.DEB.2.00.1203210018260.30543@utopia.booyaka.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <20120316234706.GJ3852@pengutronix.de>
 <alpine.DEB.2.00.1203201611330.22974@utopia.booyaka.com>
 <alpine.LFD.2.02.1203202233340.24151@xanadu.home>
 <alpine.DEB.2.00.1203210018260.30543@utopia.booyaka.com>
Message-ID: <alpine.LFD.2.02.1203210855510.24151@xanadu.home>

On Wed, 21 Mar 2012, Paul Walmsley wrote:

> Hello Nico,
> 
> On Tue, 20 Mar 2012, Nicolas Pitre wrote:
> 
> > This common clk API has been under development for over *two* years 
> > already, with several attempts to merge it.  And each previous merge 
> > attempt aborted because someone came along at the last minute to do 
> > exactly what you are doing i.e. underline all the flaws and call for a 
> > redesign.  This is becoming a bad joke.
> 
> There is a misunderstanding.  I am not calling for a redesign.  I am 
> simply stating that the current maturity level of the API and code should 
> be documented in the Kconfig dependencies or description text before the 
> code goes upstream.  The objectives are to make future changes easier, set 
> expectations, and clearly disclose the extent to which the API and code 
> will need to change.

Maybe there is no actual consensus on that extent.

> > The code will be easier to change once it is in mainline, simply due to 
> > the fact that you can also change all its users at once.  And it is well 
> > possible that most users won't have to deal with the same magnitude of 
> > complexity as yours, again reducing the scope for resistance to changes.
> 
> I hope you are right.  To me, these conclusions seem unlikely.  It seems 
> equally likely that these rationales will make it much more difficult to 
> change the code once it's upstream and platforms are depending on it.  

No code should go upstream if no one depends on it.  Therefore we change 
code that many platforms depend on all the time.  What is killing us is 
the need to synchronize with multiple external code bases scattered 
around.

> Particularly given the ongoing sensitivity to reducing "churn" of mainline 
> code, so publicly discussed.

Please stop buying into that crap.  We congratulate ourselves every 
merge cycles with the current process being able to deal with around 
half a million of lines changed every 3 months or so.  It's pointless 
churn that is frowned upon, not useful and incremental API changes.  I 
don't think that "pointless" would apply here.

> So it seems like a good idea to attempt to address these potential 
> roadblocks and criticisms to major clock framework changes early.

I understand your concern, however I don't think it is as serious as you 
are making it.

> One last comment to address which is orthogonal to the technical content 
> of this discussion.
> 
> > Otherwise one might ask where were you during those development years if 
> > you claim that the behavior and/or API of the common clock code still 
> > need to change significantly?
> 
> One might ask this.  If one were to ask this, another might briefly 
> outline the participation in public and private clock discussions at 
> Linaro Connect in Budapest and Redwood Shores, at LPC in Santa Rosa, at 
> ELCE/KS in Prague, at ELC in Redwood Shores, in conference calls, IRC 
> sessions, and private E-mails with many of the people included in the 
> header of this message, not to mention the list posts.

Sure.  I was there too and came across you many times.  I just don't 
understand why some apparent consensus was built around the current 
submission, that people involved appeared to be highly satisfied at 
last, given the emphasis you are giving to your present concern which 
doesn't seem to be widely shared.  This is a bit surprising.

> None of the concerns that have been described are new.  There has been an 
> endeavour to discuss them with anyone who seemed even remotely interested.

Let's change tactics then.  We've been discussing this code for over two 
years and no one could really benefit from it during that time.  Maybe 
future discussion could become more productive and concrete when some 
code is merged _and_ used at last.


Nicolas


From viresh.linux at gmail.com  Wed Mar 21 09:28:41 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Wed, 21 Mar 2012 18:58:41 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203211236.37891.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203151339.36173.arnd@arndb.de> <4F69BC35.4010400@st.com>
 <201203211236.37891.arnd@arndb.de>
Message-ID: <CAOh2x==J4qkp29w+v=GWORBua-DE3yb0MRGOtBLyELxbGZwcuA@mail.gmail.com>

On Wed, Mar 21, 2012 at 6:06 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> Let's make sure we're on the same page with the process though. I hope
> you're aware that I took Stefan's spear6xx v5 patch.

Ya. I already know that. :)

> Just let me know how you want to handle
> these things in the future -- the normal way would be to always let you
> forward the patches to me, rather than having them applied to arm-soc
> directly.

Hmmm. I don't know how exactly it works, but maybe you can add me as
an custodian for SPEAr, with a git repo somewhere in kernel.org (?).
So that i can apply patches directly to my branch, you pull it.
What do you say?

> I think spear is simple and clean enough that it can serve as an example
> for others doing DT conversion. Do you also plan to unify 3xx and 6xx?
> I think there is hardly anything left in mach-spear6xx that justifies
> having a separate platform, especially since with the DT conversion done,
> we can actually remove most of the header file contents as well.

I issue with us was that we were not able to push stuff mainline in time and
were too busy supporting customers.

We have lot of patches locally, that we would like to upstream. But it
can't happen
without updating it with new expectations of list. I actually wanted
to ask you few
things:

- DT: Obviously we would have this in our patches
- Pinmux: I would remove our padmux and use pinmux, but what about its
DT support.
  I know stephen had few patches for it, but don't know there
progress. I don't want to
  do stuff twice. First add support for it in board and the *.dts files.
- Clock Framework: Is common clock framework ready for use or can we update our
  local clock framework?

I will see if merging 3xx & 6xx is feasible. If yes, then i will
surely move in that direction.
I always like cleaning stuff. :)

I would be adding 13xx (cortex-A9) patches again later, once done with 3xx.

--
viresh


From jean.pihet at newoldbits.com  Wed Mar 21 09:28:52 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 21 Mar 2012 14:28:52 +0100
Subject: [RFC][PATCH 1/7] ARM: OMAP4: cpuidle - Remove unused valid field
In-Reply-To: <4F69A762.5070006@ti.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <1332322070-24577-2-git-send-email-daniel.lezcano@linaro.org>
 <CAMQu2gw+GGnpG_s6TCk2fH094Lfmj1zgAZqQ4zdQmpj3ZZhu3w@mail.gmail.com>
 <4F69A37A.7020606@linaro.org> <4F69A762.5070006@ti.com>
Message-ID: <CAORVsuUtQ3EYdrBMUkFm=nd-avz0q9D1BVmwKD-06qgaF3wDqA@mail.gmail.com>

On Wed, Mar 21, 2012 at 11:03 AM, Santosh Shilimkar
<santosh.shilimkar at ti.com> wrote:
> On Wednesday 21 March 2012 03:16 PM, Daniel Lezcano wrote:
>> On 03/21/2012 10:41 AM, Shilimkar, Santosh wrote:
>>> On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
>>> <daniel.lezcano at linaro.org> ?wrote:
>>>> The 'valid' field is never used in the code, let's remove it.
>>>>
>>>> Signed-off-by: Daniel Lezcano<daniel.lezcano at linaro.org>
>>>> ---
>>> It is used during the registration. This field has been very useful for
>>> debug when need to disable a C-state etc.
>>> So unless and until there is a strong reason, i would like to retain it.
>>
>> IMO if it used for debug purpose, it should be moved to the debug code
>> and if the debug code is not upstream, then that 'valid' should not be
>> here but in the out-of-tree code.
>>
> When I said debug, I mean CPUIDLE debug and not any special debug code.
>
>> By the way, this may be a debate for nothing because a patchset is on
>> the way to disable C-states from sysfs.
>>
> I see but sysfs won't solve that because you want to disable certain
> C-state so that CPUIDLE driver don't use that state.
This will solve the problem, the only difference is that you need the
user space to switch the disable knob from sysfs.
>From the kernel space, for debug, you can set the .disable value to 1
in the cpuidle_driver->states struct.

>
> Let say if the C4 which is OSWR is broken. In such cases, just
> setting valid flag let you disable it.
>
> Again I don't have strong objection to this change.
>
> Regards
> santosh

Regards,
Jean

>
> _______________________________________________
> linaro-dev mailing list
> linaro-dev at lists.linaro.org
> http://lists.linaro.org/mailman/listinfo/linaro-dev


From jean.pihet at newoldbits.com  Wed Mar 21 09:31:46 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 21 Mar 2012 14:31:46 +0100
Subject: [RFC][PATCH 2/7] ARM: OMAP4: cpuidle - Declare the states with
 the driver declaration
In-Reply-To: <1332322070-24577-3-git-send-email-daniel.lezcano@linaro.org>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <1332322070-24577-3-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <CAORVsuV-0xQx6W0iKGO_UduESFwdD-44vsBAcVXD0Yy-VB_eGw@mail.gmail.com>

On Wed, Mar 21, 2012 at 10:27 AM, Daniel Lezcano
<daniel.lezcano at linaro.org> wrote:
> The cpuidle API allows to declare statically the states in the driver
> structure. Let's use it.
> We do no longer need the fill_cstate function called at runtime and
> by the way adding more instructions at boot time.
>
> Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> ---
> ?arch/arm/mach-omap2/cpuidle44xx.c | ? 56 +++++++++++++++++++++----------------
> ?1 files changed, 32 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
> index 1210229..cd6bee7 100644
> --- a/arch/arm/mach-omap2/cpuidle44xx.c
> +++ b/arch/arm/mach-omap2/cpuidle44xx.c
> @@ -148,21 +148,38 @@ DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
> ?struct cpuidle_driver omap4_idle_driver = {
> ? ? ? ?.name = ? ? ? ? "omap4_idle",
> ? ? ? ?.owner = ? ? ? ?THIS_MODULE,
> + ? ? ? .states = {
> + ? ? ? ? ? ? ? {
> + ? ? ? ? ? ? ? ? ? ? ? /* C1 - CPU0 ON + CPU1 ON + MPU ON */
> + ? ? ? ? ? ? ? ? ? ? ? .exit_latency = 2 + 2,
> + ? ? ? ? ? ? ? ? ? ? ? .target_residency = 5,
> + ? ? ? ? ? ? ? ? ? ? ? .flags = CPUIDLE_FLAG_TIME_VALID,
> + ? ? ? ? ? ? ? ? ? ? ? .enter = omap4_enter_idle,
> + ? ? ? ? ? ? ? ? ? ? ? .name = "C1",
> + ? ? ? ? ? ? ? ? ? ? ? .desc = "MPUSS ON"
> + ? ? ? ? ? ? ? },
...
> + ? ? ? },
> + ? ? ? .state_count = OMAP4_NUM_STATES,
> ?};
>
> -static inline void _fill_cstate(struct cpuidle_driver *drv,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int idx, const char *descr)
> -{
> - ? ? ? struct cpuidle_state *state = &drv->states[idx];
> -
> - ? ? ? state->exit_latency ? ? = cpuidle_params_table[idx].exit_latency;
> - ? ? ? state->target_residency = cpuidle_params_table[idx].target_residency;
> - ? ? ? state->flags ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID;
> - ? ? ? state->enter ? ? ? ? ? ?= omap4_enter_idle;
> - ? ? ? sprintf(state->name, "C%d", idx + 1);
> - ? ? ? strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
> -}
I am OK with this change, which makes the code more readable (and so
maintainable).

> -
> ?static inline struct omap4_idle_statedata *_fill_cstate_usage(
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct cpuidle_device *dev,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int idx)
> @@ -196,37 +213,28 @@ int __init omap4_idle_init(void)
> ? ? ? ?if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
> ? ? ? ? ? ? ? ?return -ENODEV;
>
> -
> - ? ? ? drv->safe_state_index = -1;
> ? ? ? ?dev = &per_cpu(omap4_idle_dev, cpu_id);
> ? ? ? ?dev->cpu = cpu_id;
>
> - ? ? ? /* C1 - CPU0 ON + CPU1 ON + MPU ON */
> - ? ? ? _fill_cstate(drv, 0, "MPUSS ON");
> - ? ? ? drv->safe_state_index = 0;
I would keep this or add a clear comment that C1 is the safe state.

...

Thanks,
Jean

> --
> 1.7.5.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html


From ludovic.desroches at atmel.com  Wed Mar 21 11:41:20 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 21 Mar 2012 16:41:20 +0100
Subject: [PATCH 0/3] atmel-mci fixes 
Message-ID: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>

Hi,

The following patches provide some fixes for atmel-mci driver:
- data timeout calculation was not correct and can cause serious issues when
using a rootfs on the sd card.
- the r/w proof features is available only from 2xx hsmci version
- supports for odd clock dividers available from 5xx hsmci version

Regards

Ludovic



From ludovic.desroches at atmel.com  Wed Mar 21 11:41:23 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 21 Mar 2012 16:41:23 +0100
Subject: [PATCH 3/3] mmc: atmel-mci: add support for odd clock dividers
In-Reply-To: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
References: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1332344483-3915-4-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Add an odd clock divider capability available from v5xx. It also involves
changing the clock divider calculation.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 drivers/mmc/host/atmel-mci-regs.h |    1 +
 drivers/mmc/host/atmel-mci.c      |   48 ++++++++++++++++++++++--------------
 2 files changed, 30 insertions(+), 19 deletions(-)

diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
index 000b3ad..787aba1 100644
--- a/drivers/mmc/host/atmel-mci-regs.h
+++ b/drivers/mmc/host/atmel-mci-regs.h
@@ -31,6 +31,7 @@
 # define ATMCI_MR_PDCFBYTE		(  1 << 13)	/* Force Byte Transfer */
 # define ATMCI_MR_PDCPADV		(  1 << 14)	/* Padding Value */
 # define ATMCI_MR_PDCMODE		(  1 << 15)	/* PDC-oriented Mode */
+# define ATMCI_MR_CLKODD(x)		((x) << 16)	/* LSB of Clock Divider */
 #define ATMCI_DTOR			0x0008	/* Data Timeout */
 # define ATMCI_DTOCYC(x)		((x) <<  0)	/* Data Timeout Cycles */
 # define ATMCI_DTOMUL(x)		((x) <<  4)	/* Data Timeout Multiplier */
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index 9dcb236..75e28c0 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -76,6 +76,7 @@ struct atmel_mci_caps {
 	bool    has_cstor_reg;
 	bool    has_highspeed;
 	bool    has_rwproof;
+	bool	has_odd_clk_div;
 };
 
 struct atmel_mci_dma {
@@ -1124,16 +1125,27 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		}
 
 		/* Calculate clock divider */
-		clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
-		if (clkdiv > 255) {
-			dev_warn(&mmc->class_dev,
-				"clock %u too slow; using %lu\n",
-				clock_min, host->bus_hz / (2 * 256));
-			clkdiv = 255;
+		if (host->caps.has_odd_clk_div) {
+			clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
+			if (clkdiv > 511) {
+				dev_warn(&mmc->class_dev,
+				         "clock %u too slow; using %lu\n",
+				         clock_min, host->bus_hz / (511 + 2));
+				clkdiv = 511;
+			}
+			host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
+			                 | ATMCI_MR_CLKODD(clkdiv & 1);
+		} else {
+			clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
+			if (clkdiv > 255) {
+				dev_warn(&mmc->class_dev,
+				         "clock %u too slow; using %lu\n",
+				         clock_min, host->bus_hz / (2 * 256));
+				clkdiv = 255;
+			}
+			host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
 		}
 
-		host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
-
 		/*
 		 * WRPROOF and RDPROOF prevent overruns/underruns by
 		 * stopping the clock when the FIFO is full/empty.
@@ -2000,37 +2012,35 @@ static void __init atmci_get_cap(struct atmel_mci *host)
 			"version: 0x%x\n", version);
 
 	host->caps.has_dma = 0;
-	host->caps.has_pdc = 0;
+	host->caps.has_pdc = 1;
 	host->caps.has_cfg_reg = 0;
 	host->caps.has_cstor_reg = 0;
 	host->caps.has_highspeed = 0;
 	host->caps.has_rwproof = 0;
+	host->caps.has_odd_clk_div = 0;
 
 	/* keep only major version number */
 	switch (version & 0xf00) {
-	case 0x100:
-		host->caps.has_pdc = 1;
-		break;
-	case 0x200:
-		host->caps.has_pdc = 1;
-		host->caps.has_rwproof = 1;
-		break;
-	case 0x300:
-	case 0x400:
 	case 0x500:
+		host->caps.has_odd_clk_div = 1;
+	case 0x400:
+	case 0x300:
 #ifdef CONFIG_AT_HDMAC
 		host->caps.has_dma = 1;
 #else
-		host->caps.has_dma = 0;
 		dev_info(&host->pdev->dev,
 			"has dma capability but dma engine is not selected, then use pio\n");
 #endif
+		host->caps.has_pdc = 0;
 		host->caps.has_cfg_reg = 1;
 		host->caps.has_cstor_reg = 1;
 		host->caps.has_highspeed = 1;
+	case 0x200:
 		host->caps.has_rwproof = 1;
+	case 0x100:
 		break;
 	default:
+		host->caps.has_pdc = 0;
 		dev_warn(&host->pdev->dev,
 				"Unmanaged mci version, set minimum capabilities\n");
 		break;
-- 
1.7.5.4



From ludovic.desroches at atmel.com  Wed Mar 21 11:41:22 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 21 Mar 2012 16:41:22 +0100
Subject: [PATCH 2/3] mmc: atmel-mci: r/w proof capability only available since
 v2xx
In-Reply-To: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
References: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1332344483-3915-3-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 drivers/mmc/host/atmel-mci.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index e161452..9dcb236 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -2009,6 +2009,8 @@ static void __init atmci_get_cap(struct atmel_mci *host)
 	/* keep only major version number */
 	switch (version & 0xf00) {
 	case 0x100:
+		host->caps.has_pdc = 1;
+		break;
 	case 0x200:
 		host->caps.has_pdc = 1;
 		host->caps.has_rwproof = 1;
-- 
1.7.5.4



From ludovic.desroches at atmel.com  Wed Mar 21 11:41:21 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 21 Mar 2012 16:41:21 +0100
Subject: [PATCH 1/3] mmc: atmel-mci: correct data timeout computation
In-Reply-To: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
References: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1332344483-3915-2-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

The HSMCI operates at a rate of up to Master Clock divided by two.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 drivers/mmc/host/atmel-mci.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index e4449a5..e161452 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -480,7 +480,7 @@ err:
 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
 					unsigned int ns)
 {
-	return (ns * (host->bus_hz / 1000000) + 999) / 1000;
+	return (ns * ((host->bus_hz/2) / 1000000) + 999) / 1000;
 }
 
 static void atmci_set_timeout(struct atmel_mci *host,
-- 
1.7.5.4



From m.szyprowski at samsung.com  Wed Mar 21 09:43:46 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 21 Mar 2012 14:43:46 +0100
Subject: [GIT PULL] DMA-mapping framework updates for 3.4
In-Reply-To: <1332228283-29077-1-git-send-email-m.szyprowski@samsung.com>
References: <1332228283-29077-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <079801cd0768$a3623d10$ea26b730$%szyprowski@samsung.com>

Hello,

On Tuesday, March 20, 2012 8:25 AM Marek Szyprowski wrote:

> Hi Linus,
> 
> Please pull the dma-mapping framework updates for v3.4 since commit
> c16fa4f2ad19908a47c63d8fa436a1178438c7e7:
> 
>   Linux 3.3
> 
> with the top-most commit e749a9f707f1102735e02338fa564be86be3bb69
> 
>   common: DMA-mapping: add NON-CONSISTENT attribute
> 
> from the git repository at:
> 
>   git://git.infradead.org/users/kmpark/linux-samsung dma-mapping-next
> 
> Those patches introduce a new alloc method (with support for memory
> attributes) in dma_map_ops structure, which will later replace
> dma_alloc_coherent and dma_alloc_writecombine functions.
 
I've been pointed out that this summary is quite short and misses the main
rationale for the proposed changes.

A few limitations have been identified in the current dma-mapping design and 
its implementations for various architectures. There exist more than one function
for allocating and freeing the buffers: currently these 3 are used dma_{alloc,
free}_coherent, dma_{alloc,free}_writecombine, dma_{alloc,free}_noncoherent.

For most of the systems these calls are almost equivalent and can be interchanged.
For others, especially the truly non-coherent ones (like ARM), the difference can
be easily noticed in overall driver performance. Sadly not all architectures 
provide implementations for all of them, so the drivers might need to be adapted 
and cannot be easily shared between different architectures. The provided patches
unify all these functions and hide the differences under the already existing
dma attributes concept. The thread with more references is available here: 
http://www.spinics.net/lists/linux-sh/msg09777.html

These patches are also a prerequisite for unifying DMA-mapping implementation
on ARM architecture with the common one provided by dma_map_ops structure and 
extending it with IOMMU support. More information is available in the following 
thread: http://thread.gmane.org/gmane.linux.kernel.cross-arch/12819

More works on dma-mapping framework are planned, especially in the area of buffer
sharing and managing the shared mappings (together with the recently introduced 
dma_buf interface: commit d15bd7ee445d0702ad801fdaece348fdb79e6581 "dma-buf: 
Introduce dma buffer sharing mechanism" ).

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From jean.pihet at newoldbits.com  Wed Mar 21 09:43:58 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Wed, 21 Mar 2012 14:43:58 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <4F69A872.50203@ti.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <4F69A872.50203@ti.com>
Message-ID: <CAORVsuUeE046O7YJ_fE49NbW1OjZHZX+GuNiDkF0AnzBnSMbxA@mail.gmail.com>

On Wed, Mar 21, 2012 at 11:07 AM, Santosh Shilimkar
<santosh.shilimkar at ti.com> wrote:
> Daniel,
>
> On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
>> This patchset is a proposition to improve a bit the code.
>> The changes are code cleanup and does not change the behavior of the
>> driver itself.
>>
>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
>> and why the WFI is not used ?
>>
>> Daniel Lezcano (7):
>> ? ARM: OMAP4: cpuidle - Remove unused valid field
>> ? ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>> ? ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>> ? ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>> ? ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>> ? ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>> ? ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>> ? ? time
>>
> The series looks fine to me in general. This clean-up is applicable
> for OMAP3 cpuidle code as well.
Great!
However OMAP3 has a few specific things that cannot be removed as easily:
- the 'valid' flag is used because only certain combinations of power
domains states are possible,
- the latency settings can be overriden by the board code, so the
cpuidle_params struct is needed.

> I want Jean to look at this series because some of his earlier
> clean up has introduced those custom functions which
> are getting removed in this series.
>
> Regards
> santosh
>
>

Thanks,
Jean


From santosh.shilimkar at ti.com  Wed Mar 21 10:00:01 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 21 Mar 2012 19:30:01 +0530
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
Message-ID: <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>

On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
>> On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
>> > On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>> >>
>> >> I think you made very good point here. With the above patch, we are almost missing the capability of registering dmtimer as a clocksource for OMAP.
>> >> It will always use 32k-counter, and never fall back to dmtimer.
>> >>
>> >> Then the only options we have here is,
>> >>
>> >> 1) Register both the timers, 32k-counter and dmtimer for clocksource; let
>> >> ? Kernel pick up best rating clocksource out of these two.
>> >>
>> >> ? In case of OMAP1/2/3/4, kernel will use dmtimer, since it has better
>> >> ? Rating. User can choose the 32k-counter clocksource via bootargs.
>> >>
>> >> ? Impact: without bootargs for clocksource selection, kernel will choose
>> >> ? ? dmtimer, impacting loss of time during suspend/resume.
>> >>
>> This is the right option. The problem is gptimer clocksource
>> doesn't work across power transitions and hence it is broken.
>>
>> Even for the perf, with PM enabled, dmtimer can't be used or it needs
>> to be used with 32KHz clock which makes it no better than sync timer.
>>
>> So here keeping 32K sync timer is default clocksource makes sense since
>> it is the only working and viable option.
>>
>> So what can be done is register both 32K and gptimer together but make
>> gptimer clocksource registration depends on PM enabled.
>>
>> This should solve all the needs I guess.
>>
>
> I am not sure this will work on all platforms, for example, AM33XX, where
> We do not have 32ksync timer available, but we need PM support. Also, I
> personally think, we should not again use compile time option here.
>
Why not ?
If 32ksync timer is not available, don't register it. Then in AM case
you just have one clock-source. I am against the idea of making
gptimer as the default and asking user to choose sync32k from
command-line.

Btw, if you need PM, how are you going to use GPTIMER
as a clocksource. Note sys-clock is generally stopped in
low power states. So that leaves you option with using
gptimer with 32K clock and in that case, GPTIMER
is not a better clock-source compare to 32K sync timer
and so shouldn't be the rating.

Regards
Santosh


From paul.gortmaker at windriver.com  Wed Mar 21 10:02:44 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Wed, 21 Mar 2012 10:02:44 -0400
Subject: [PATCH] ARM: fix lcd power build failure in collie_defconfig
In-Reply-To: <4F69CDF2.3020609@gmx.de>
References: <1331051502-22361-1-git-send-email-paul.gortmaker@windriver.com>
 <4F69CDF2.3020609@gmx.de>
Message-ID: <4F69DF84.8050605@windriver.com>

On 12-03-21 08:47 AM, Florian Tobias Schandinat wrote:
> On 03/06/2012 04:31 PM, Paul Gortmaker wrote:
>> Commit 086ada54abaa4316e8603f02410fe8ebc9ba2de1 (linux-next)
>>
>>   "FB: sa1100: remove global sa1100fb_.*_power function pointers"
>>
>> got rid of all instances but one in locomolcd.c -- which was
>> conditional on CONFIG_SA1100_COLLIE.  The associated .power
>> field which replaces the global is populated in mach-sa1100/collie.c
>> so move the assignment there, but make it conditional on the
>> locomolcd support, so use CONFIG_BACKLIGHT_LOCOMO in that file.
>>
>> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> 
> What about this patch?
> I assumed Russel would pick it up as the commit referenced is also in
> his tree but it looks like this patch is still not in -next. Any reasons
> for this?

Not that I'm aware of.  I didn't get any negative feedback or change
requests asking for a v2.   There are probably about a half dozen
linux-next build failures in my triage list that I've fixed but
the commits have not yet looped back around through the various
maintainers for one reason or another.

http://marc.info/?l=linux-next&m=133227360822405&w=2

It would be nice to have them all crossed off...

Paul.
---

> 
> 
> Best regards,
> 
> Florian Tobias Schandinat
> 
>>
>> diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
>> index 48885b7..c7f418b 100644
>> --- a/arch/arm/mach-sa1100/collie.c
>> +++ b/arch/arm/mach-sa1100/collie.c
>> @@ -313,6 +313,10 @@ static struct sa1100fb_mach_info collie_lcd_info = {
>>  
>>  	.lccr0		= LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
>>  	.lccr3		= LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
>> +
>> +#ifdef CONFIG_BACKLIGHT_LOCOMO
>> +	.lcd_power	= locomolcd_power
>> +#endif
>>  };
>>  
>>  static void __init collie_init(void)
>> diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
>> index 52acda7..f33679d 100644
>> --- a/arch/arm/mach-sa1100/include/mach/collie.h
>> +++ b/arch/arm/mach-sa1100/include/mach/collie.h
>> @@ -1,7 +1,7 @@
>>  /*
>>   * arch/arm/mach-sa1100/include/mach/collie.h
>>   *
>> - * This file contains the hardware specific definitions for Assabet
>> + * This file contains the hardware specific definitions for Collie
>>   * Only include this file from SA1100-specific files.
>>   *
>>   * ChangeLog:
>> @@ -13,6 +13,7 @@
>>  #ifndef __ASM_ARCH_COLLIE_H
>>  #define __ASM_ARCH_COLLIE_H
>>  
>> +extern void locomolcd_power(int on);
>>  
>>  #define COLLIE_SCOOP_GPIO_BASE	(GPIO_MAX + 1)
>>  #define COLLIE_GPIO_CHARGE_ON	(COLLIE_SCOOP_GPIO_BASE + 0)
>> diff --git a/drivers/video/backlight/locomolcd.c b/drivers/video/backlight/locomolcd.c
>> index be20b5c..3a6d541 100644
>> --- a/drivers/video/backlight/locomolcd.c
>> +++ b/drivers/video/backlight/locomolcd.c
>> @@ -229,14 +229,7 @@ static struct locomo_driver poodle_lcd_driver = {
>>  
>>  static int __init locomolcd_init(void)
>>  {
>> -	int ret = locomo_driver_register(&poodle_lcd_driver);
>> -	if (ret)
>> -		return ret;
>> -
>> -#ifdef CONFIG_SA1100_COLLIE
>> -	sa1100fb_lcd_power = locomolcd_power;
>> -#endif
>> -	return 0;
>> +	return locomo_driver_register(&poodle_lcd_driver);
>>  }
>>  
>>  static void __exit locomolcd_exit(void)
> 


From khilman at ti.com  Wed Mar 21 10:06:30 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 21 Mar 2012 07:06:30 -0700
Subject: [PATCH v4 RESEND 6/7] gpio/omap: fix incorrect update to
 context.irqenable1
In-Reply-To: <CAC83ZvLgPWO2C6cpRBEsoqFdac1rMyo4OvTXB2_y_mCzaFzJXA@mail.gmail.com>
 (Tarun Kanti DebBarma's message of "Wed, 21 Mar 2012 10:31:48 +0530")
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
 <1332240799-6748-7-git-send-email-tarun.kanti@ti.com>
 <87zkbbywwz.fsf@ti.com>
 <CAC83ZvKRbvVU5Qa1jwud0E6WT-DBU1Z1XEweiXay9x+eLcn0hg@mail.gmail.com>
 <CAC83ZvLgPWO2C6cpRBEsoqFdac1rMyo4OvTXB2_y_mCzaFzJXA@mail.gmail.com>
Message-ID: <87y5qurqu1.fsf@ti.com>

"DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:

> On Wed, Mar 21, 2012 at 8:10 AM, DebBarma, Tarun Kanti
> <tarun.kanti at ti.com> wrote:
>> On Tue, Mar 20, 2012 at 11:31 PM, Kevin Hilman <khilman at ti.com> wrote:
>>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>>>
>>>> In _enable_gpio_irqbank() when bank->regs->set_irqenable is valid,
>>>> gpio_mask can be directly set by writing to set_irqenable register
>>>> without overwriting current value. In order to ensure the same is
>>>> stored in context.irqenable1, we must read from regs->irqenable
>>>> instead of overwriting it with gpio_mask.
>>>
>>>> The overwriting makes sense only in the second case where irqenable
>>>> is explicitly read and updated with new gpio_mask before writing it
>>>> back. However, for consistency reading regs->irqenable into the
>>>> bank->context.irqenable1 takes care of both the scenarios.
>>>
>>> ...except that the code doesn't do this anymore.
>> Yes.
>>>
>>> I like the newer version (I hope so, since I suggested it :), but please
>>> update the changlog to describe what the code is actually doing.
>> Sure.
> I have updated the change log here:
> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev
> for_3.4/gpio_more_fixes

Please also post and updated version of the patch for review.

Kevin


From arnd at arndb.de  Wed Mar 21 10:04:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 21 Mar 2012 14:04:35 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <CAOh2x==J4qkp29w+v=GWORBua-DE3yb0MRGOtBLyELxbGZwcuA@mail.gmail.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203211236.37891.arnd@arndb.de>
 <CAOh2x==J4qkp29w+v=GWORBua-DE3yb0MRGOtBLyELxbGZwcuA@mail.gmail.com>
Message-ID: <201203211404.35847.arnd@arndb.de>

On Wednesday 21 March 2012, viresh kumar wrote:
> On Wed, Mar 21, 2012 at 6:06 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > Just let me know how you want to handle
> > these things in the future -- the normal way would be to always let you
> > forward the patches to me, rather than having them applied to arm-soc
> > directly.
> 
> Hmmm. I don't know how exactly it works, but maybe you can add me as
> an custodian for SPEAr, with a git repo somewhere in kernel.org (?).
> So that i can apply patches directly to my branch, you pull it.
> What do you say?

Yes, that would be the ideal way. You are already listed in the MAINTAINERS
file, so nothing would change in theory. If you don't have an account on
kernel.org yet, see http://www.kernel.org/faq/#account for how to get
one. This will require that you have your gpg keys signed by at least
one person in the kernel web of trust, so you may have to find people
locally who can sign yours and are already signed.

> > I think spear is simple and clean enough that it can serve as an example
> > for others doing DT conversion. Do you also plan to unify 3xx and 6xx?
> > I think there is hardly anything left in mach-spear6xx that justifies
> > having a separate platform, especially since with the DT conversion done,
> > we can actually remove most of the header file contents as well.
> 
> I issue with us was that we were not able to push stuff mainline in time and
> were too busy supporting customers.
> 
> We have lot of patches locally, that we would like to upstream. But it
> can't happen
> without updating it with new expectations of list. I actually wanted
> to ask you few
> things:
> 
> - DT: Obviously we would have this in our patches
> - Pinmux: I would remove our padmux and use pinmux, but what about its
> DT support.
>   I know stephen had few patches for it, but don't know there
> progress. I don't want to
>   do stuff twice. First add support for it in board and the *.dts files.

AFAICT, the pinmux DT binding should be ready for v3.5, I don't think it
made it into v3.4.

> - Clock Framework: Is common clock framework ready for use or can we update our
>   local clock framework?

I'm sending it to Linus now and you can start using it, but it may still
change in a number of ways based on the requirements of new platforms that
start migrate to it.

> I will see if merging 3xx & 6xx is feasible. If yes, then i will
> surely move in that direction.
> I always like cleaning stuff. :)

I've looked at this earlier today out of curiosity and found:

debug_macro.h, gpio.h, hardware.h, timex.h, uncompress.h:
	 identical already
clock.c: almost identical, can be easily merged, or both copies
         kept around during transition.
misc_regs.h: can be merged into clock.c
spear.h: can merged into spear6xx.c but mostly go away
generic.h, irqs.h: not needed any more for spear6xx

Once you have taken care of these, files, you can enable building 3xx
and 6xx together, and move the contents of mach-spear3xx, mach-spear6xx
and plat-spear into one directory.

> I would be adding 13xx (cortex-A9) patches again later, once done with 3xx.

Ok, excellent. Note that there is no requirement to do it all in the order
you line out above. You can always get support for new stuff into the
existing platform without cleaning up all of it right away, as long as you
have a good balance between cleanups and new functionality.

In particular, you don't have to start using pinctrl and the common clk
immediately for spear3xx, although you might find that it helps you.

For spear13xx, the platform being completely new, I would however ask
you to use those from the start.

	Arnd


From daniel.lezcano at linaro.org  Wed Mar 21 10:12:31 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 15:12:31 +0100
Subject: [RFC][PATCH 2/7] ARM: OMAP4: cpuidle - Declare the states with
 the driver declaration
In-Reply-To: <CAORVsuV-0xQx6W0iKGO_UduESFwdD-44vsBAcVXD0Yy-VB_eGw@mail.gmail.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <1332322070-24577-3-git-send-email-daniel.lezcano@linaro.org>
 <CAORVsuV-0xQx6W0iKGO_UduESFwdD-44vsBAcVXD0Yy-VB_eGw@mail.gmail.com>
Message-ID: <4F69E1CF.8030703@linaro.org>

On 03/21/2012 02:31 PM, Jean Pihet wrote:
> On Wed, Mar 21, 2012 at 10:27 AM, Daniel Lezcano
> <daniel.lezcano at linaro.org>  wrote:
>> The cpuidle API allows to declare statically the states in the driver
>> structure. Let's use it.
>> We do no longer need the fill_cstate function called at runtime and
>> by the way adding more instructions at boot time.
>>
>> Signed-off-by: Daniel Lezcano<daniel.lezcano at linaro.org>
>> ---
>>   arch/arm/mach-omap2/cpuidle44xx.c |   56 +++++++++++++++++++++----------------
>>   1 files changed, 32 insertions(+), 24 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
>> index 1210229..cd6bee7 100644
>> --- a/arch/arm/mach-omap2/cpuidle44xx.c
>> +++ b/arch/arm/mach-omap2/cpuidle44xx.c
>> @@ -148,21 +148,38 @@ DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
>>   struct cpuidle_driver omap4_idle_driver = {
>>         .name =         "omap4_idle",
>>         .owner =        THIS_MODULE,
>> +       .states = {
>> +               {
>> +                       /* C1 - CPU0 ON + CPU1 ON + MPU ON */
>> +                       .exit_latency = 2 + 2,
>> +                       .target_residency = 5,
>> +                       .flags = CPUIDLE_FLAG_TIME_VALID,
>> +                       .enter = omap4_enter_idle,
>> +                       .name = "C1",
>> +                       .desc = "MPUSS ON"
>> +               },
> ...
>> +       },
>> +       .state_count = OMAP4_NUM_STATES,
>>   };
>>
>> -static inline void _fill_cstate(struct cpuidle_driver *drv,
>> -                                       int idx, const char *descr)
>> -{
>> -       struct cpuidle_state *state =&drv->states[idx];
>> -
>> -       state->exit_latency     = cpuidle_params_table[idx].exit_latency;
>> -       state->target_residency = cpuidle_params_table[idx].target_residency;
>> -       state->flags            = CPUIDLE_FLAG_TIME_VALID;
>> -       state->enter            = omap4_enter_idle;
>> -       sprintf(state->name, "C%d", idx + 1);
>> -       strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
>> -}
> I am OK with this change, which makes the code more readable (and so
> maintainable).
>
>> -
>>   static inline struct omap4_idle_statedata *_fill_cstate_usage(
>>                                         struct cpuidle_device *dev,
>>                                         int idx)
>> @@ -196,37 +213,28 @@ int __init omap4_idle_init(void)
>>         if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
>>                 return -ENODEV;
>>
>> -
>> -       drv->safe_state_index = -1;
>>         dev =&per_cpu(omap4_idle_dev, cpu_id);
>>         dev->cpu = cpu_id;
>>
>> -       /* C1 - CPU0 ON + CPU1 ON + MPU ON */
>> -       _fill_cstate(drv, 0, "MPUSS ON");
>> -       drv->safe_state_index = 0;
> I would keep this or add a clear comment that C1 is the safe state.

Actually with the driver's states declaration, the safe_state_index is 
initialized to zero, which means the default safe_state is always 0 with 
the new API. But I can add the initialization anyway in the structure 
declaration if you want.

> ...
>
> Thanks,
> Jean
>
>> --
>> 1.7.5.4
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html


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From daniel.lezcano at linaro.org  Wed Mar 21 10:13:02 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 15:13:02 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <CAORVsuUL3Z_vw+n26eWaa8eAJ0yhXB=VRNmuCeSZjStG527Gag@mail.gmail.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <4F69A872.50203@ti.com>
 <CAORVsuUL3Z_vw+n26eWaa8eAJ0yhXB=VRNmuCeSZjStG527Gag@mail.gmail.com>
Message-ID: <4F69E1EE.708@linaro.org>

On 03/21/2012 02:19 PM, Jean Pihet wrote:
> Hi Santosh, Daniel,
>
> On Wed, Mar 21, 2012 at 11:07 AM, Santosh Shilimkar
> <santosh.shilimkar at ti.com>  wrote:
>> Daniel,
>>
>> On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
>>> This patchset is a proposition to improve a bit the code.
>>> The changes are code cleanup and does not change the behavior of the
>>> driver itself.
>>>
>>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
>>> and why the WFI is not used ?
>>>
>>> Daniel Lezcano (7):
>>>    ARM: OMAP4: cpuidle - Remove unused valid field
>>>    ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>>>    ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>>>    ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>>>    ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>>>    ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>>>    ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>>>      time
>>>
>> The series looks fine to me in general. This clean-up is applicable
>> for OMAP3 cpuidle code as well.
>>
>> I want Jean to look at this series because some of his earlier
>> clean up has introduced those custom functions which
>> are getting removed in this series.
> I am OK with the patch set, I only have minor remarks to the individual patches.
>
> Reviewed-by: Jean Pihet<j-pihet at ti.com>

Thanks for the review Jean.

>>
>>
>
> Thanks!
> Jean


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From nicolas.ferre at atmel.com  Wed Mar 21 10:13:00 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 21 Mar 2012 15:13:00 +0100
Subject: [PATCH] ARM: at91/at91sam9x5: add clkdev entries for DMA controllers
Message-ID: <1332339180-4670-1-git-send-email-nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/at91sam9x5.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index b6831ee..13c8cae 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -223,6 +223,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
 	CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
+	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
+	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
 	CLKDEV_CON_ID("pioA", &pioAB_clk),
 	CLKDEV_CON_ID("pioB", &pioAB_clk),
 	CLKDEV_CON_ID("pioC", &pioCD_clk),
-- 
1.7.9



From khilman at ti.com  Wed Mar 21 10:13:56 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 21 Mar 2012 07:13:56 -0700
Subject: [PATCH] ARM: OMAP3+: fix oops triggered in
 omap_prcm_register_chain_handler
In-Reply-To: <1332305376-27038-1-git-send-email-tom.leiming@gmail.com> (Ming
 Lei's message of "Wed, 21 Mar 2012 12:49:36 +0800")
References: <1332305376-27038-1-git-send-email-tom.leiming@gmail.com>
Message-ID: <87r4wmrqhn.fsf@ti.com>

Ming Lei <tom.leiming at gmail.com> writes:

> This patch fixes the oos below:

As Tero mentioned, please add a bit more description to the changelog
about why the iterator is wrong and repost.

Thanks for the patch.  After the above changes, I'll queue this up for v3.4-rc.

Kevin

> [    1.790242] Unable to handle kernel NULL pointer dereference at virtual
> address 00000004
> [    1.798632] pgd = c0004000
> [    1.801638] [00000004] *pgd=00000000
> [    1.805400] Internal error: Oops: 805 [#1] PREEMPT SMP THUMB2
> [    1.811381] Modules linked in:
> [    1.814601] CPU: 1    Not tainted  (3.3.0-next-20120320+ #733)
> [    1.820683] PC is at irq_setup_generic_chip+0x6a/0x84
> [    1.825951] LR is at irq_get_irq_data+0x7/0x8
> [    1.830508] pc : [<c006465e>]    lr : [<c0063a03>]    psr: 20000133
> [    1.830512] sp : ee04ff58  ip : 00000000  fp : 00000000
> [    1.842461] r10: 00000000  r9 : 00000000  r8 : 00000800
> [    1.847905] r7 : c064e260  r6 : 000001dc  r5 : 00000001  r4 : ee0accc0
> [    1.854687] r3 : 00000002  r2 : 00000800  r1 : 000001dc  r0 : 00000000
> [    1.861472] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA Thumb  Segment kernel
> [    1.869234] Control: 50c5387d  Table: 8000404a  DAC: 00000015
> [    1.875215] Process swapper/0 (pid: 1, stack limit = 0xee04e2f8)
> [    1.881463] Stack: (0xee04ff58 to 0xee050000)
> [    1.886017] ff40: c061b668 00000008
> [    1.894497] ff60: c0682090 ee0accc0 00000003 c001c637 00000000 00000000 00000201 00000000
> [    1.902976] ff80: 00000004 c0473820 c0473800 c0459e8d c0680ac0 c000866d 00000004 00000004
> [    1.911455] ffa0: ee04ffa8 00000004 c047381c 00000004 c0473820 c0473800 c0680ac0 00000082
> [    1.919934] ffc0: c0489694 c045265f 00000004 00000004 c0452135 c000d105 00000033 00000000
> [    1.928413] ffe0: c04525b5 c000d111 00000033 00000000 00000000 c000d111 aaaaaaaa aaaaaaaa
> [    1.936912] [<c006465e>] (irq_setup_generic_chip+0x6a/0x84) from [<c001c637>] (omap_prcm_register_chain_handler+0x147/0x1a0)
> [    1.948516] [<c001c637>] (omap_prcm_register_chain_handler+0x147/0x1a0) from [<c000866d>] (do_one_initcall+0x65/0xf4)
> [    1.959500] [<c000866d>] (do_one_initcall+0x65/0xf4) from [<c045265f>] (kernel_init+0xab/0x138)
> [    1.968529] [<c045265f>] (kernel_init+0xab/0x138) from [<c000d111>] (kernel_thread_exit+0x1/0x6)
> [    1.977632] Code: f7ff f9d1 6b23 1af3 (6043) 086d
> [    1.982684] ---[ end trace 1b75b31a2719ed1c ]---
> [    1.987526] Kernel panic - not syncing: Attempted to kill init!
> exitcode=0x0000000b
>
> Cc: Tero Kristo <t-kristo at ti.com>
> Signed-off-by: Ming Lei <tom.leiming at gmail.com>
> ---
>  arch/arm/mach-omap2/prm_common.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
> index 873b51d..d28f848 100644
> --- a/arch/arm/mach-omap2/prm_common.c
> +++ b/arch/arm/mach-omap2/prm_common.c
> @@ -290,7 +290,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
>  		goto err;
>  	}
>  
> -	for (i = 0; i <= irq_setup->nr_regs; i++) {
> +	for (i = 0; i < irq_setup->nr_regs; i++) {
>  		gc = irq_alloc_generic_chip("PRCM", 1,
>  			irq_setup->base_irq + i * 32, prm_base,
>  			handle_level_irq);


From viresh.linux at gmail.com  Wed Mar 21 10:18:26 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Wed, 21 Mar 2012 19:48:26 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203211404.35847.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203211236.37891.arnd@arndb.de>
 <CAOh2x==J4qkp29w+v=GWORBua-DE3yb0MRGOtBLyELxbGZwcuA@mail.gmail.com>
 <201203211404.35847.arnd@arndb.de>
Message-ID: <CAOh2x=mtjvitkhz=BXOZPAaKZ2i3QQuKrYA3HcHNERHhF5xFoA@mail.gmail.com>

On Wed, Mar 21, 2012 at 7:34 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Wednesday 21 March 2012, viresh kumar wrote:
>> - Pinmux: I would remove our padmux and use pinmux, but what about its
>> DT support.
>> ? I know stephen had few patches for it, but don't know there
>> progress. I don't want to
>> ? do stuff twice. First add support for it in board and the *.dts files.
>
> AFAICT, the pinmux DT binding should be ready for v3.5, I don't think it
> made it into v3.4.

So, i can add stuff in board file for pinmux for now?

> I've looked at this earlier today out of curiosity and found:
>
> clock.c: almost identical, can be easily merged, or both copies
> ? ? ? ? kept around during transition.

Would make it very confusing if we merge these two. Some clock
structures are same, but others are not. Mostly differences are in the
macros (or bit positions in registers), rather than hierarchy. So, i would
like to keep them separate. But still have a look again to see if they can
really be merged.

> misc_regs.h: can be merged into clock.c

it has more than clock stuff. it is used in pinmux and some other places too,
that may not be in mainline for now.

> Once you have taken care of these, files, you can enable building 3xx
> and 6xx together, and move the contents of mach-spear3xx, mach-spear6xx
> and plat-spear into one directory.

plat-spear would be required for 13xx too. So, merging 3xx and 6xx only would
be possible.

> Ok, excellent. Note that there is no requirement to do it all in the order
> you line out above. You can always get support for new stuff into the
> existing platform without cleaning up all of it right away, as long as you
> have a good balance between cleanups and new functionality.

Ya. I just wanted to get some hands on experience with this new stuff, before
touching 13xx.

> In particular, you don't have to start using pinctrl and the common clk
> immediately for spear3xx, although you might find that it helps you.

But, can i update padmux and clock framework of SPEAr platform? Because
without the latest code for both padmux and clock, other code for SPEAr
might not be that effective or usable.

> For spear13xx, the platform being completely new, I would however ask
> you to use those from the start.

Sure.

--
viresh


From daniel.lezcano at linaro.org  Wed Mar 21 10:19:15 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 15:19:15 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <CAORVsuUeE046O7YJ_fE49NbW1OjZHZX+GuNiDkF0AnzBnSMbxA@mail.gmail.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <4F69A872.50203@ti.com>
 <CAORVsuUeE046O7YJ_fE49NbW1OjZHZX+GuNiDkF0AnzBnSMbxA@mail.gmail.com>
Message-ID: <4F69E363.4020709@linaro.org>

On 03/21/2012 02:43 PM, Jean Pihet wrote:
> On Wed, Mar 21, 2012 at 11:07 AM, Santosh Shilimkar
> <santosh.shilimkar at ti.com>  wrote:
>> Daniel,
>>
>> On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
>>> This patchset is a proposition to improve a bit the code.
>>> The changes are code cleanup and does not change the behavior of the
>>> driver itself.
>>>
>>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
>>> and why the WFI is not used ?
>>>
>>> Daniel Lezcano (7):
>>>    ARM: OMAP4: cpuidle - Remove unused valid field
>>>    ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>>>    ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>>>    ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>>>    ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>>>    ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>>>    ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>>>      time
>>>
>> The series looks fine to me in general. This clean-up is applicable
>> for OMAP3 cpuidle code as well.
> Great!
> However OMAP3 has a few specific things that cannot be removed as easily:
> - the 'valid' flag is used because only certain combinations of power
> domains states are possible,
> - the latency settings can be overriden by the board code, so the
> cpuidle_params struct is needed.

Right, I noticed that. I am looking for a way to have a similar cleanup 
for omap3 but without breaking the rx51 board.

Thanks
   -- Daniel


>> I want Jean to look at this series because some of his earlier
>> clean up has introduced those custom functions which
>> are getting removed in this series.
>>
>> Regards
>> santosh
>>
>>
>
> Thanks,
> Jean


-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From jonsmirl at gmail.com  Wed Mar 21 10:23:15 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Wed, 21 Mar 2012 10:23:15 -0400
Subject: Device tree and IO map_desc.
In-Reply-To: <4F69D325.1000500@gmail.com>
References: <CAKON4OyHRVvdtZGt+HiCnsRT_5zTuDVBVgOx22kFC2xxFLnD+Q@mail.gmail.com>
 <4F69D325.1000500@gmail.com>
Message-ID: <CAKON4OxxmO_Et8FTVp=i7h9uODWAtdjHOmZrFWLtgqYVAjAAGg@mail.gmail.com>

On Wed, Mar 21, 2012 at 9:09 AM, Rob Herring <robherring2 at gmail.com> wrote:
> On 03/20/2012 11:52 AM, jonsmirl at gmail.com wrote:
>> Is there a helper for building the IO map_desc from the device tree?
>>
>
> No. This is one of those things that device tree cannot have knowledge
> of what needs to be statically mapped as that's not a h/w description.

What's an example of something that is described in the device tree
and is dynamically mapped? Things like PCI cards shouldn't be in the
device tree since they are discoverable.

Nodes have 'status' in them, could this be used to control mapping?

				uart1: uart at 02020000 {
					compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02020000 0x4000>;
					interrupts = <0 26 0x04>;
					status = "disabled";
				};

Probably the right solution is that the individual drivers should map
themselves by calling into a helper function with address and range.
The helper would coalesce and merge ranges to reduce the number of
mappings.

This is a piece of a lpc3131 three I am working on. I could add a tiny
driver for the adp node that creates the mapping. Then as the
dependent devices ask for mappings they'd be inside the larger node.

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		isram0: memory at 11028000 {
			reg = <0x11028000 0x18000>;
		};
		isram1: memory at 11040000 {
			reg = <0x11040000 0x18000>;
		};

		apb0: apb at 13000000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x13000000 0x13000000 0x8000>;

			evtr at 13000000 {
				compatible = "nxp,lpc31xx-evtr";
				reg = <0x13000000 0x800>;
			};
			adc at 13002000 {
				compatible = "nxp,lpc31xx-adc";
				reg = <0x13002000 0x400>;
				interrupts = <1>;
			};


>
> We could probably have a list of nodes to map and extract the size and
> physical addresses from the DT. There's lots of register defines
> typically associated with the static mappings, so you would still have
> duplicated information.
>
>> For example on Versatile. All of this map_io data is already in the
>> device tree, it is just repeated here.
>>
>>
>> DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
>> ? ? ? .map_io ? ? ? ? = versatile_map_io,
>> ? ? ? .init_early ? ? = versatile_init_early,
>> ....
>> MACHINE_END
>>
>> void __init versatile_map_io(void)
>> {
>> ? ? ? iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
>> }
>>
>> static struct map_desc versatile_io_desc[] __initdata = {
>> ? ? ? {
>> ? ? ? ? ? ? ? .virtual ? ? ? ?= ?IO_ADDRESS(VERSATILE_SYS_BASE),
>> ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(VERSATILE_SYS_BASE),
>> ? ? ? ? ? ? ? .length ? ? ? ? = SZ_4K,
>> ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE
>> ? ? ? }, {
>> ? ? ? ? ? ? ? .virtual ? ? ? ?= ?IO_ADDRESS(VERSATILE_SIC_BASE),
>> ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(VERSATILE_SIC_BASE),
>> ? ? ? ? ? ? ? .length ? ? ? ? = SZ_4K,
>> ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE
>> ? ? ? }, {
>> ? ? ? ? ? ? ? .virtual ? ? ? ?= ?IO_ADDRESS(VERSATILE_VIC_BASE),
>> ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(VERSATILE_VIC_BASE),
>> ? ? ? ? ? ? ? .length ? ? ? ? = SZ_4K,
>> ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE
>
> The SIC and VIC should get converted to ioremap and using of_irq_init.
> There's already DT init support for the VIC at least, so the conversion
> should be easy. I think Linus W was working on this.
>
> Rob
>
>> ? ? ? }, {
>> ...
>>
>



-- 
Jon Smirl
jonsmirl at gmail.com


From santosh.shilimkar at ti.com  Wed Mar 21 10:23:07 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 21 Mar 2012 19:53:07 +0530
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <CAORVsuUL3Z_vw+n26eWaa8eAJ0yhXB=VRNmuCeSZjStG527Gag@mail.gmail.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <4F69A872.50203@ti.com>
 <CAORVsuUL3Z_vw+n26eWaa8eAJ0yhXB=VRNmuCeSZjStG527Gag@mail.gmail.com>
Message-ID: <CAMQu2gxrUycJq07Ngs-TXq+jqqe4uBH4Y_CZjFict=OL9ifb_g@mail.gmail.com>

On Wed, Mar 21, 2012 at 6:49 PM, Jean Pihet <jean.pihet at newoldbits.com> wrote:
> Hi Santosh, Daniel,
>
> On Wed, Mar 21, 2012 at 11:07 AM, Santosh Shilimkar
> <santosh.shilimkar at ti.com> wrote:
>> Daniel,
>>
>> On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
>>> This patchset is a proposition to improve a bit the code.
>>> The changes are code cleanup and does not change the behavior of the
>>> driver itself.
>>>
>>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
>>> and why the WFI is not used ?
>>>
>>> Daniel Lezcano (7):
>>> ? ARM: OMAP4: cpuidle - Remove unused valid field
>>> ? ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>>> ? ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>>> ? ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>>> ? ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>>> ? ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>>> ? ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>>> ? ? time
>>>
>> The series looks fine to me in general. This clean-up is applicable
>> for OMAP3 cpuidle code as well.
>>
>> I want Jean to look at this series because some of his earlier
>> clean up has introduced those custom functions which
>> are getting removed in this series.
> I am OK with the patch set, I only have minor remarks to the individual patches.
>
> Reviewed-by: Jean Pihet <j-pihet at ti.com>
>
Thanks Jean for looking at it.

Daniel,
Feel free to add.
 Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>


From rob.lee at linaro.org  Wed Mar 21 10:28:18 2012
From: rob.lee at linaro.org (Rob Lee)
Date: Wed, 21 Mar 2012 09:28:18 -0500
Subject: [PATCH v8 4/8] ARM: davinci: Consolidate time keeping and irq
 enable
In-Reply-To: <1332274969-15782-5-git-send-email-rob.lee@linaro.org>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <1332274969-15782-5-git-send-email-rob.lee@linaro.org>
Message-ID: <CAMXH7KH5kS=wPFdC8QrtnhE6_sZqmsJ8h=6Gs3kfHOTbeHjacA@mail.gmail.com>

Sekhar tested this patch on Davinci last night and found a problem.  I
looked at the code again and found a mindless omission on my part (see
below).  Fix is trivial.  I've check all other platforms and confirmed
this problem does not exist for those.  Will resend a v9 of the
patchset shortly.

On Tue, Mar 20, 2012 at 3:22 PM, Robert Lee <rob.lee at linaro.org> wrote:
> Enable core cpuidle timekeeping and irq enabling and remove that
> handling from this code.
>
> Signed-off-by: Robert Lee <rob.lee at linaro.org>
> Reviewed-by: Kevin Hilman <khilman at ti.com>
> Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> Acked-by: Jean Pihet<j-pihet at ti.com>
> ---
> ?arch/arm/mach-davinci/cpuidle.c | ? 82 ++++++++++++++++-----------------------
> ?1 file changed, 33 insertions(+), 49 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
> index a30c7c5..93ae096 100644
> --- a/arch/arm/mach-davinci/cpuidle.c
> +++ b/arch/arm/mach-davinci/cpuidle.c
> @@ -18,6 +18,7 @@
> ?#include <linux/io.h>
> ?#include <linux/export.h>
> ?#include <asm/proc-fns.h>
> +#include <asm/cpuidle.h>
>
> ?#include <mach/cpuidle.h>
> ?#include <mach/ddr2.h>
> @@ -30,12 +31,42 @@ struct davinci_ops {
> ? ? ? ?u32 flags;
> ?};
>
> +/* Actual code that puts the SoC in different idle states */
> +static int davinci_enter_idle(struct cpuidle_device *dev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct cpuidle_driver *drv,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int index)
> +{
> + ? ? ? struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
> + ? ? ? struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
> +
> + ? ? ? if (ops && ops->enter)
> + ? ? ? ? ? ? ? ops->enter(ops->flags);
> +
> + ? ? ? index = cpuidle_wrap_enter(dev, drv, index,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? arm_cpuidle_simple_enter);
> +
> + ? ? ? if (ops && ops->exit)
> + ? ? ? ? ? ? ? ops->exit(ops->flags);
> +
> + ? ? ? return index;
> +}
> +
> ?/* fields in davinci_ops.flags */
> ?#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN ? ? ? ?BIT(0)
>
> ?static struct cpuidle_driver davinci_idle_driver = {
> - ? ? ? .name ? = "cpuidle-davinci",
> - ? ? ? .owner ?= THIS_MODULE,
> + ? ? ? .name ? ? ? ? ? = "cpuidle-davinci",
> + ? ? ? .owner ? ? ? ? ?= THIS_MODULE,

Argh! I am missing the ".en_core_tk_irqen = 1" here.


> + ? ? ? .states[0] ? ? ?= ARM_CPUIDLE_WFI_STATE,
> + ? ? ? .states[1] ? ? ?= {
> + ? ? ? ? ? ? ? .enter ? ? ? ? ? ? ? ? ?= davinci_enter_idle,
> + ? ? ? ? ? ? ? .exit_latency ? ? ? ? ? = 10,
> + ? ? ? ? ? ? ? .target_residency ? ? ? = 100000,
> + ? ? ? ? ? ? ? .flags ? ? ? ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID,
> + ? ? ? ? ? ? ? .name ? ? ? ? ? ? ? ? ? = "DDR SR",
> + ? ? ? ? ? ? ? .desc ? ? ? ? ? ? ? ? ? = "WFI and DDR Self Refresh",
> + ? ? ? },
> + ? ? ? .state_count = DAVINCI_CPUIDLE_MAX_STATES,
> ?};
>
> ?static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
> @@ -77,41 +108,10 @@ static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
> ? ? ? ?},
> ?};
>
> -/* Actual code that puts the SoC in different idle states */
> -static int davinci_enter_idle(struct cpuidle_device *dev,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct cpuidle_driver *drv,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int index)
> -{
> - ? ? ? struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
> - ? ? ? struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
> - ? ? ? struct timeval before, after;
> - ? ? ? int idle_time;
> -
> - ? ? ? local_irq_disable();
> - ? ? ? do_gettimeofday(&before);
> -
> - ? ? ? if (ops && ops->enter)
> - ? ? ? ? ? ? ? ops->enter(ops->flags);
> - ? ? ? /* Wait for interrupt state */
> - ? ? ? cpu_do_idle();
> - ? ? ? if (ops && ops->exit)
> - ? ? ? ? ? ? ? ops->exit(ops->flags);
> -
> - ? ? ? do_gettimeofday(&after);
> - ? ? ? local_irq_enable();
> - ? ? ? idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
> - ? ? ? ? ? ? ? ? ? ? ? (after.tv_usec - before.tv_usec);
> -
> - ? ? ? dev->last_residency = idle_time;
> -
> - ? ? ? return index;
> -}
> -
> ?static int __init davinci_cpuidle_probe(struct platform_device *pdev)
> ?{
> ? ? ? ?int ret;
> ? ? ? ?struct cpuidle_device *device;
> - ? ? ? struct cpuidle_driver *driver = &davinci_idle_driver;
> ? ? ? ?struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
>
> ? ? ? ?device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
> @@ -123,27 +123,11 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
>
> ? ? ? ?ddr2_reg_base = pdata->ddr2_ctlr_base;
>
> - ? ? ? /* Wait for interrupt state */
> - ? ? ? driver->states[0].enter = davinci_enter_idle;
> - ? ? ? driver->states[0].exit_latency = 1;
> - ? ? ? driver->states[0].target_residency = 10000;
> - ? ? ? driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
> - ? ? ? strcpy(driver->states[0].name, "WFI");
> - ? ? ? strcpy(driver->states[0].desc, "Wait for interrupt");
> -
> - ? ? ? /* Wait for interrupt and DDR self refresh state */
> - ? ? ? driver->states[1].enter = davinci_enter_idle;
> - ? ? ? driver->states[1].exit_latency = 10;
> - ? ? ? driver->states[1].target_residency = 10000;
> - ? ? ? driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
> - ? ? ? strcpy(driver->states[1].name, "DDR SR");
> - ? ? ? strcpy(driver->states[1].desc, "WFI and DDR Self Refresh");
> ? ? ? ?if (pdata->ddr2_pdown)
> ? ? ? ? ? ? ? ?davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
> ? ? ? ?cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]);
>
> ? ? ? ?device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
> - ? ? ? driver->state_count = DAVINCI_CPUIDLE_MAX_STATES;
>
> ? ? ? ?ret = cpuidle_register_driver(&davinci_idle_driver);
> ? ? ? ?if (ret) {
> --
> 1.7.9.4
>


From khilman at ti.com  Wed Mar 21 10:28:46 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 21 Mar 2012 07:28:46 -0700
Subject: [PATCH 0/3] OMAP2+: UART: Enable tx wakeup + remove cpu checks
In-Reply-To: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
 (Govindraj R.'s message of "Wed, 21 Mar 2012 15:54:58 +0530")
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
Message-ID: <87limurpsx.fsf@ti.com>

"Govindraj.R" <govindraj.raja at ti.com> writes:

> From: "Govindraj.R" <govindraj.raja at ti.com>
>
> Based on Linux-OMAP tree uart branch.
> (git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
> remotes/origin/uart)
>
> * Removes the cpu checks wherever possible and use version reg
>   for populating features and errata's
> * enable tx wakeup available in wer reg for applicable
>   module revision's

As this affects multiple SoCs, please report what SoCs it was tested on
as well.

Thanks,

Kevin

> Govindraj.R (3):
>   OMAP2+: UART: Remove cpu checks for populating errata flags
>   OMAP2+: UART: enable tx wakeup bit for wer reg
>   OMAP2+: UART: replace omap34xx/omap4xx cpu checks with not omap24xx
>
>  arch/arm/mach-omap2/serial.c                  |   13 +----
>  arch/arm/plat-omap/include/plat/omap-serial.h |    8 +++-
>  drivers/tty/serial/omap-serial.c              |   71 ++++++++++++++++++++++++-
>  3 files changed, 78 insertions(+), 14 deletions(-)


From rob.lee at linaro.org  Wed Mar 21 10:36:20 2012
From: rob.lee at linaro.org (Rob Lee)
Date: Wed, 21 Mar 2012 09:36:20 -0500
Subject: [PATCH v8 4/8] ARM: davinci: Consolidate time keeping and irq
 enable
In-Reply-To: <CAMXH7KH5kS=wPFdC8QrtnhE6_sZqmsJ8h=6Gs3kfHOTbeHjacA@mail.gmail.com>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <1332274969-15782-5-git-send-email-rob.lee@linaro.org>
 <CAMXH7KH5kS=wPFdC8QrtnhE6_sZqmsJ8h=6Gs3kfHOTbeHjacA@mail.gmail.com>
Message-ID: <CAMXH7KGCTP0=YGfSgEVYYJoFK22GOLt-KfShpa6CuDi=PQ1-Pw@mail.gmail.com>

On Wed, Mar 21, 2012 at 9:28 AM, Rob Lee <rob.lee at linaro.org> wrote:
> Sekhar tested this patch on Davinci last night and found a problem. ?I
> looked at the code again and found a mindless omission on my part (see
> below). ?Fix is trivial. ?I've check all other platforms and confirmed
> this problem does not exist for those. ?Will resend a v9 of the
> patchset shortly.
>

Kevin just informed me that Len already has v8 patchset queued so I'll
just send this fix out as a separate patch.

> On Tue, Mar 20, 2012 at 3:22 PM, Robert Lee <rob.lee at linaro.org> wrote:
>> Enable core cpuidle timekeeping and irq enabling and remove that
>> handling from this code.
>>
>> Signed-off-by: Robert Lee <rob.lee at linaro.org>
>> Reviewed-by: Kevin Hilman <khilman at ti.com>
>> Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
>> Acked-by: Jean Pihet<j-pihet at ti.com>
>> ---
>> ?arch/arm/mach-davinci/cpuidle.c | ? 82 ++++++++++++++++-----------------------
>> ?1 file changed, 33 insertions(+), 49 deletions(-)
>>
>> diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
>> index a30c7c5..93ae096 100644
>> --- a/arch/arm/mach-davinci/cpuidle.c
>> +++ b/arch/arm/mach-davinci/cpuidle.c
>> @@ -18,6 +18,7 @@
>> ?#include <linux/io.h>
>> ?#include <linux/export.h>
>> ?#include <asm/proc-fns.h>
>> +#include <asm/cpuidle.h>
>>
>> ?#include <mach/cpuidle.h>
>> ?#include <mach/ddr2.h>
>> @@ -30,12 +31,42 @@ struct davinci_ops {
>> ? ? ? ?u32 flags;
>> ?};
>>
>> +/* Actual code that puts the SoC in different idle states */
>> +static int davinci_enter_idle(struct cpuidle_device *dev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct cpuidle_driver *drv,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int index)
>> +{
>> + ? ? ? struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
>> + ? ? ? struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
>> +
>> + ? ? ? if (ops && ops->enter)
>> + ? ? ? ? ? ? ? ops->enter(ops->flags);
>> +
>> + ? ? ? index = cpuidle_wrap_enter(dev, drv, index,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? arm_cpuidle_simple_enter);
>> +
>> + ? ? ? if (ops && ops->exit)
>> + ? ? ? ? ? ? ? ops->exit(ops->flags);
>> +
>> + ? ? ? return index;
>> +}
>> +
>> ?/* fields in davinci_ops.flags */
>> ?#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN ? ? ? ?BIT(0)
>>
>> ?static struct cpuidle_driver davinci_idle_driver = {
>> - ? ? ? .name ? = "cpuidle-davinci",
>> - ? ? ? .owner ?= THIS_MODULE,
>> + ? ? ? .name ? ? ? ? ? = "cpuidle-davinci",
>> + ? ? ? .owner ? ? ? ? ?= THIS_MODULE,
>
> Argh! I am missing the ".en_core_tk_irqen = 1" here.
>
>
>> + ? ? ? .states[0] ? ? ?= ARM_CPUIDLE_WFI_STATE,
>> + ? ? ? .states[1] ? ? ?= {
>> + ? ? ? ? ? ? ? .enter ? ? ? ? ? ? ? ? ?= davinci_enter_idle,
>> + ? ? ? ? ? ? ? .exit_latency ? ? ? ? ? = 10,
>> + ? ? ? ? ? ? ? .target_residency ? ? ? = 100000,
>> + ? ? ? ? ? ? ? .flags ? ? ? ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID,
>> + ? ? ? ? ? ? ? .name ? ? ? ? ? ? ? ? ? = "DDR SR",
>> + ? ? ? ? ? ? ? .desc ? ? ? ? ? ? ? ? ? = "WFI and DDR Self Refresh",
>> + ? ? ? },
>> + ? ? ? .state_count = DAVINCI_CPUIDLE_MAX_STATES,
>> ?};
>>
>> ?static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
>> @@ -77,41 +108,10 @@ static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
>> ? ? ? ?},
>> ?};
>>
>> -/* Actual code that puts the SoC in different idle states */
>> -static int davinci_enter_idle(struct cpuidle_device *dev,
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct cpuidle_driver *drv,
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int index)
>> -{
>> - ? ? ? struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
>> - ? ? ? struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
>> - ? ? ? struct timeval before, after;
>> - ? ? ? int idle_time;
>> -
>> - ? ? ? local_irq_disable();
>> - ? ? ? do_gettimeofday(&before);
>> -
>> - ? ? ? if (ops && ops->enter)
>> - ? ? ? ? ? ? ? ops->enter(ops->flags);
>> - ? ? ? /* Wait for interrupt state */
>> - ? ? ? cpu_do_idle();
>> - ? ? ? if (ops && ops->exit)
>> - ? ? ? ? ? ? ? ops->exit(ops->flags);
>> -
>> - ? ? ? do_gettimeofday(&after);
>> - ? ? ? local_irq_enable();
>> - ? ? ? idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
>> - ? ? ? ? ? ? ? ? ? ? ? (after.tv_usec - before.tv_usec);
>> -
>> - ? ? ? dev->last_residency = idle_time;
>> -
>> - ? ? ? return index;
>> -}
>> -
>> ?static int __init davinci_cpuidle_probe(struct platform_device *pdev)
>> ?{
>> ? ? ? ?int ret;
>> ? ? ? ?struct cpuidle_device *device;
>> - ? ? ? struct cpuidle_driver *driver = &davinci_idle_driver;
>> ? ? ? ?struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
>>
>> ? ? ? ?device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
>> @@ -123,27 +123,11 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
>>
>> ? ? ? ?ddr2_reg_base = pdata->ddr2_ctlr_base;
>>
>> - ? ? ? /* Wait for interrupt state */
>> - ? ? ? driver->states[0].enter = davinci_enter_idle;
>> - ? ? ? driver->states[0].exit_latency = 1;
>> - ? ? ? driver->states[0].target_residency = 10000;
>> - ? ? ? driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
>> - ? ? ? strcpy(driver->states[0].name, "WFI");
>> - ? ? ? strcpy(driver->states[0].desc, "Wait for interrupt");
>> -
>> - ? ? ? /* Wait for interrupt and DDR self refresh state */
>> - ? ? ? driver->states[1].enter = davinci_enter_idle;
>> - ? ? ? driver->states[1].exit_latency = 10;
>> - ? ? ? driver->states[1].target_residency = 10000;
>> - ? ? ? driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
>> - ? ? ? strcpy(driver->states[1].name, "DDR SR");
>> - ? ? ? strcpy(driver->states[1].desc, "WFI and DDR Self Refresh");
>> ? ? ? ?if (pdata->ddr2_pdown)
>> ? ? ? ? ? ? ? ?davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
>> ? ? ? ?cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]);
>>
>> ? ? ? ?device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
>> - ? ? ? driver->state_count = DAVINCI_CPUIDLE_MAX_STATES;
>>
>> ? ? ? ?ret = cpuidle_register_driver(&davinci_idle_driver);
>> ? ? ? ?if (ret) {
>> --
>> 1.7.9.4
>>


From amit.kucheria at linaro.org  Wed Mar 21 10:36:29 2012
From: amit.kucheria at linaro.org (Amit Kucheria)
Date: Wed, 21 Mar 2012 16:36:29 +0200
Subject: [PATCH v8 4/8] ARM: davinci: Consolidate time keeping and irq
 enable
In-Reply-To: <CAMXH7KH5kS=wPFdC8QrtnhE6_sZqmsJ8h=6Gs3kfHOTbeHjacA@mail.gmail.com>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <1332274969-15782-5-git-send-email-rob.lee@linaro.org>
 <CAMXH7KH5kS=wPFdC8QrtnhE6_sZqmsJ8h=6Gs3kfHOTbeHjacA@mail.gmail.com>
Message-ID: <CAP245DW9SdTYNc8XXwiuHzo5Y-aZrLc2qP0MekKkyAT2TosjbQ@mail.gmail.com>

Rob, you should start a new '3.4-fixes' branch containing such
bugfixes that can be pushed to Len after -rc1.

On Wed, Mar 21, 2012 at 4:28 PM, Rob Lee <rob.lee at linaro.org> wrote:
> Sekhar tested this patch on Davinci last night and found a problem. ?I
> looked at the code again and found a mindless omission on my part (see
> below). ?Fix is trivial. ?I've check all other platforms and confirmed
> this problem does not exist for those. ?Will resend a v9 of the
> patchset shortly.
>
> On Tue, Mar 20, 2012 at 3:22 PM, Robert Lee <rob.lee at linaro.org> wrote:
>> Enable core cpuidle timekeeping and irq enabling and remove that
>> handling from this code.
>>
>> Signed-off-by: Robert Lee <rob.lee at linaro.org>
>> Reviewed-by: Kevin Hilman <khilman at ti.com>
>> Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
>> Acked-by: Jean Pihet<j-pihet at ti.com>
>> ---
>> ?arch/arm/mach-davinci/cpuidle.c | ? 82 ++++++++++++++++-----------------------
>> ?1 file changed, 33 insertions(+), 49 deletions(-)
>>
>> diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
>> index a30c7c5..93ae096 100644
>> --- a/arch/arm/mach-davinci/cpuidle.c
>> +++ b/arch/arm/mach-davinci/cpuidle.c
>> @@ -18,6 +18,7 @@
>> ?#include <linux/io.h>
>> ?#include <linux/export.h>
>> ?#include <asm/proc-fns.h>
>> +#include <asm/cpuidle.h>
>>
>> ?#include <mach/cpuidle.h>
>> ?#include <mach/ddr2.h>
>> @@ -30,12 +31,42 @@ struct davinci_ops {
>> ? ? ? ?u32 flags;
>> ?};
>>
>> +/* Actual code that puts the SoC in different idle states */
>> +static int davinci_enter_idle(struct cpuidle_device *dev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct cpuidle_driver *drv,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int index)
>> +{
>> + ? ? ? struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
>> + ? ? ? struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
>> +
>> + ? ? ? if (ops && ops->enter)
>> + ? ? ? ? ? ? ? ops->enter(ops->flags);
>> +
>> + ? ? ? index = cpuidle_wrap_enter(dev, drv, index,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? arm_cpuidle_simple_enter);
>> +
>> + ? ? ? if (ops && ops->exit)
>> + ? ? ? ? ? ? ? ops->exit(ops->flags);
>> +
>> + ? ? ? return index;
>> +}
>> +
>> ?/* fields in davinci_ops.flags */
>> ?#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN ? ? ? ?BIT(0)
>>
>> ?static struct cpuidle_driver davinci_idle_driver = {
>> - ? ? ? .name ? = "cpuidle-davinci",
>> - ? ? ? .owner ?= THIS_MODULE,
>> + ? ? ? .name ? ? ? ? ? = "cpuidle-davinci",
>> + ? ? ? .owner ? ? ? ? ?= THIS_MODULE,
>
> Argh! I am missing the ".en_core_tk_irqen = 1" here.
>
>
>> + ? ? ? .states[0] ? ? ?= ARM_CPUIDLE_WFI_STATE,
>> + ? ? ? .states[1] ? ? ?= {
>> + ? ? ? ? ? ? ? .enter ? ? ? ? ? ? ? ? ?= davinci_enter_idle,
>> + ? ? ? ? ? ? ? .exit_latency ? ? ? ? ? = 10,
>> + ? ? ? ? ? ? ? .target_residency ? ? ? = 100000,
>> + ? ? ? ? ? ? ? .flags ? ? ? ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID,
>> + ? ? ? ? ? ? ? .name ? ? ? ? ? ? ? ? ? = "DDR SR",
>> + ? ? ? ? ? ? ? .desc ? ? ? ? ? ? ? ? ? = "WFI and DDR Self Refresh",
>> + ? ? ? },
>> + ? ? ? .state_count = DAVINCI_CPUIDLE_MAX_STATES,
>> ?};
>>
>> ?static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
>> @@ -77,41 +108,10 @@ static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
>> ? ? ? ?},
>> ?};
>>
>> -/* Actual code that puts the SoC in different idle states */
>> -static int davinci_enter_idle(struct cpuidle_device *dev,
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct cpuidle_driver *drv,
>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int index)
>> -{
>> - ? ? ? struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
>> - ? ? ? struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
>> - ? ? ? struct timeval before, after;
>> - ? ? ? int idle_time;
>> -
>> - ? ? ? local_irq_disable();
>> - ? ? ? do_gettimeofday(&before);
>> -
>> - ? ? ? if (ops && ops->enter)
>> - ? ? ? ? ? ? ? ops->enter(ops->flags);
>> - ? ? ? /* Wait for interrupt state */
>> - ? ? ? cpu_do_idle();
>> - ? ? ? if (ops && ops->exit)
>> - ? ? ? ? ? ? ? ops->exit(ops->flags);
>> -
>> - ? ? ? do_gettimeofday(&after);
>> - ? ? ? local_irq_enable();
>> - ? ? ? idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
>> - ? ? ? ? ? ? ? ? ? ? ? (after.tv_usec - before.tv_usec);
>> -
>> - ? ? ? dev->last_residency = idle_time;
>> -
>> - ? ? ? return index;
>> -}
>> -
>> ?static int __init davinci_cpuidle_probe(struct platform_device *pdev)
>> ?{
>> ? ? ? ?int ret;
>> ? ? ? ?struct cpuidle_device *device;
>> - ? ? ? struct cpuidle_driver *driver = &davinci_idle_driver;
>> ? ? ? ?struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
>>
>> ? ? ? ?device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
>> @@ -123,27 +123,11 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
>>
>> ? ? ? ?ddr2_reg_base = pdata->ddr2_ctlr_base;
>>
>> - ? ? ? /* Wait for interrupt state */
>> - ? ? ? driver->states[0].enter = davinci_enter_idle;
>> - ? ? ? driver->states[0].exit_latency = 1;
>> - ? ? ? driver->states[0].target_residency = 10000;
>> - ? ? ? driver->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
>> - ? ? ? strcpy(driver->states[0].name, "WFI");
>> - ? ? ? strcpy(driver->states[0].desc, "Wait for interrupt");
>> -
>> - ? ? ? /* Wait for interrupt and DDR self refresh state */
>> - ? ? ? driver->states[1].enter = davinci_enter_idle;
>> - ? ? ? driver->states[1].exit_latency = 10;
>> - ? ? ? driver->states[1].target_residency = 10000;
>> - ? ? ? driver->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
>> - ? ? ? strcpy(driver->states[1].name, "DDR SR");
>> - ? ? ? strcpy(driver->states[1].desc, "WFI and DDR Self Refresh");
>> ? ? ? ?if (pdata->ddr2_pdown)
>> ? ? ? ? ? ? ? ?davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
>> ? ? ? ?cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]);
>>
>> ? ? ? ?device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
>> - ? ? ? driver->state_count = DAVINCI_CPUIDLE_MAX_STATES;
>>
>> ? ? ? ?ret = cpuidle_register_driver(&davinci_idle_driver);
>> ? ? ? ?if (ret) {
>> --
>> 1.7.9.4
>>


From robherring2 at gmail.com  Wed Mar 21 10:37:25 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 21 Mar 2012 09:37:25 -0500
Subject: Device tree and IO map_desc.
In-Reply-To: <CAKON4OxxmO_Et8FTVp=i7h9uODWAtdjHOmZrFWLtgqYVAjAAGg@mail.gmail.com>
References: <CAKON4OyHRVvdtZGt+HiCnsRT_5zTuDVBVgOx22kFC2xxFLnD+Q@mail.gmail.com>
 <4F69D325.1000500@gmail.com>
 <CAKON4OxxmO_Et8FTVp=i7h9uODWAtdjHOmZrFWLtgqYVAjAAGg@mail.gmail.com>
Message-ID: <4F69E7A5.4090101@gmail.com>

On 03/21/2012 09:23 AM, jonsmirl at gmail.com wrote:
> On Wed, Mar 21, 2012 at 9:09 AM, Rob Herring <robherring2 at gmail.com> wrote:
>> On 03/20/2012 11:52 AM, jonsmirl at gmail.com wrote:
>>> Is there a helper for building the IO map_desc from the device tree?
>>>
>>
>> No. This is one of those things that device tree cannot have knowledge
>> of what needs to be statically mapped as that's not a h/w description.
> 
> What's an example of something that is described in the device tree
> and is dynamically mapped? Things like PCI cards shouldn't be in the
> device tree since they are discoverable.
> 

I mean mapped into cpu virtual memory. Static mapping is map_desc.
Dynamic mapping is ioremap.

> Nodes have 'status' in them, could this be used to control mapping?
> 
> 				uart1: uart at 02020000 {
> 					compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
> 					reg = <0x02020000 0x4000>;
> 					interrupts = <0 26 0x04>;
> 					status = "disabled";
> 				};
> 
> Probably the right solution is that the individual drivers should map
> themselves by calling into a helper function with address and range.
> The helper would coalesce and merge ranges to reduce the number of
> mappings.

This is what most drivers do. The static mappings in map_desc are often
special cases where ioremap doesn't work. LL_DEBUG is one example.

> 
> This is a piece of a lpc3131 three I am working on. I could add a tiny
> driver for the adp node that creates the mapping. Then as the
> dependent devices ask for mappings they'd be inside the larger node.
> 

Use ioremap unless there is a reason you can't.

Rob

> 	ahb {
> 		compatible = "simple-bus";
> 		#address-cells = <1>;
> 		#size-cells = <1>;
> 		ranges;
> 
> 		isram0: memory at 11028000 {
> 			reg = <0x11028000 0x18000>;
> 		};
> 		isram1: memory at 11040000 {
> 			reg = <0x11040000 0x18000>;
> 		};
> 
> 		apb0: apb at 13000000 {
> 			compatible = "simple-bus";
> 			#address-cells = <1>;
> 			#size-cells = <1>;
> 			ranges = <0x13000000 0x13000000 0x8000>;
> 
> 			evtr at 13000000 {
> 				compatible = "nxp,lpc31xx-evtr";
> 				reg = <0x13000000 0x800>;
> 			};
> 			adc at 13002000 {
> 				compatible = "nxp,lpc31xx-adc";
> 				reg = <0x13002000 0x400>;
> 				interrupts = <1>;
> 			};
> 
> 
>>
>> We could probably have a list of nodes to map and extract the size and
>> physical addresses from the DT. There's lots of register defines
>> typically associated with the static mappings, so you would still have
>> duplicated information.
>>
>>> For example on Versatile. All of this map_io data is already in the
>>> device tree, it is just repeated here.
>>>
>>>
>>> DT_MACHINE_START(VERSATILE_PB, "ARM-Versatile (Device Tree Support)")
>>>       .map_io         = versatile_map_io,
>>>       .init_early     = versatile_init_early,
>>> ....
>>> MACHINE_END
>>>
>>> void __init versatile_map_io(void)
>>> {
>>>       iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
>>> }
>>>
>>> static struct map_desc versatile_io_desc[] __initdata = {
>>>       {
>>>               .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
>>>               .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
>>>               .length         = SZ_4K,
>>>               .type           = MT_DEVICE
>>>       }, {
>>>               .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
>>>               .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
>>>               .length         = SZ_4K,
>>>               .type           = MT_DEVICE
>>>       }, {
>>>               .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
>>>               .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
>>>               .length         = SZ_4K,
>>>               .type           = MT_DEVICE
>>
>> The SIC and VIC should get converted to ioremap and using of_irq_init.
>> There's already DT init support for the VIC at least, so the conversion
>> should be easy. I think Linus W was working on this.
>>
>> Rob
>>
>>>       }, {
>>> ...
>>>
>>
> 
> 
> 



From arnd at arndb.de  Wed Mar 21 10:42:50 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 21 Mar 2012 14:42:50 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <CAOh2x=mtjvitkhz=BXOZPAaKZ2i3QQuKrYA3HcHNERHhF5xFoA@mail.gmail.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203211404.35847.arnd@arndb.de>
 <CAOh2x=mtjvitkhz=BXOZPAaKZ2i3QQuKrYA3HcHNERHhF5xFoA@mail.gmail.com>
Message-ID: <201203211442.50683.arnd@arndb.de>

On Wednesday 21 March 2012, viresh kumar wrote:
> On Wed, Mar 21, 2012 at 7:34 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Wednesday 21 March 2012, viresh kumar wrote:
> >> - Pinmux: I would remove our padmux and use pinmux, but what about its
> >> DT support.
> >>   I know stephen had few patches for it, but don't know there
> >> progress. I don't want to
> >>   do stuff twice. First add support for it in board and the *.dts files.
> >
> > AFAICT, the pinmux DT binding should be ready for v3.5, I don't think it
> > made it into v3.4.
> 
> So, i can add stuff in board file for pinmux for now?

Probably yes. It depends on the scale though: if you add more code than
what is needed to convert to the pinctrl framework, we might decide that
it's not worth it.

Note that moving to the pinctrl subsystem can be done independent from
doing the device tree conversion, and it does not depend on the
pinctrl dt binding even if you already have DT support.

> > I've looked at this earlier today out of curiosity and found:
> >
> > clock.c: almost identical, can be easily merged, or both copies
> >         kept around during transition.
> 
> Would make it very confusing if we merge these two. Some clock
> structures are same, but others are not. Mostly differences are in the
> macros (or bit positions in registers), rather than hierarchy. So, i would
> like to keep them separate. But still have a look again to see if they can
> really be merged.

Ok, I see.

> > misc_regs.h: can be merged into clock.c
> 
> it has more than clock stuff. it is used in pinmux and some other places too,
> that may not be in mainline for now.

Right, I was only looking at the stuff that is actually being used in mainline.
However I think this file should not be needed at all -- any contents that
are specific to one driver can just live in that driver, and stuff that is
shared across multiple drivers generally looks like it is also shared between
3xx and 6xx.

> > Once you have taken care of these, files, you can enable building 3xx
> > and 6xx together, and move the contents of mach-spear3xx, mach-spear6xx
> > and plat-spear into one directory.
> 
> plat-spear would be required for 13xx too. So, merging 3xx and 6xx only would
> be possible.

There is not all that much that can be shared here:

* clock.c would go into drivers/clk/ for spear13xx and possibly for the others
  too.
* padmux.c would go into drivers/pinctrl
* time.c would go into drivers/clocksource
* shirq.c is potentially shared, but we've discussed in the past about
  creating a new drivers/irqchip where this can live.
* restart.c is very small, there is no harm in duplicating this.
* The header files will have to go elsewhere, too, as we move towards
  have a single multiplatform zImage.

> > Ok, excellent. Note that there is no requirement to do it all in the order
> > you line out above. You can always get support for new stuff into the
> > existing platform without cleaning up all of it right away, as long as you
> > have a good balance between cleanups and new functionality.
> 
> Ya. I just wanted to get some hands on experience with this new stuff, before
> touching 13xx.

Good idea. As Stefan has shown, it's not really all that hard to get a lot
done for the older platforms, and spear13xx will likely be much harder
because of the increased hardware complexity.

> > In particular, you don't have to start using pinctrl and the common clk
> > immediately for spear3xx, although you might find that it helps you.
> 
> But, can i update padmux and clock framework of SPEAr platform? Because
> without the latest code for both padmux and clock, other code for SPEAr
> might not be that effective or usable.

Yes, you can do updates in there that are logical and keep the current
basic structure or improve it. I would only object if you do a more or
less complete rewrite of those files but don't use the common infrastructure
in the process.

	Arnd


From javier.martin at vista-silicon.com  Wed Mar 21 11:19:41 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed, 21 Mar 2012 16:19:41 +0100
Subject: [PATCH] MX2: Fix mx2_camera clock regression.
Message-ID: <1332343181-16968-1-git-send-email-javier.martin@vista-silicon.com>

The following patch breaks mx2_camera driver:
http://git.linuxtv.org/media_tree.git?a=commitdiff;h=52f1a845e25dc0c6435153aca1a170e20b282429

This change fixes the problem.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/mach-imx/clock-imx27.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index b9a95ed..98e04f5 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -662,6 +662,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "dma", dma_clk)
 	_REGISTER_CLOCK(NULL, "rtic", rtic_clk)
 	_REGISTER_CLOCK(NULL, "brom", brom_clk)
+	_REGISTER_CLOCK(NULL, "emma", emma_clk)
 	_REGISTER_CLOCK("m2m-emmaprp.0", NULL, emma_clk)
 	_REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
 	_REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
-- 
1.7.0.4



From sshtylyov at mvista.com  Wed Mar 21 12:26:04 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 21 Mar 2012 19:26:04 +0300
Subject: [PATCH 1/3] mmc: atmel-mci: correct data timeout computation
In-Reply-To: <1332344483-3915-2-git-send-email-ludovic.desroches@atmel.com>
References: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
 <1332344483-3915-2-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <4F6A011C.3000900@mvista.com>

Hello.

On 03/21/2012 06:41 PM, ludovic.desroches at atmel.com wrote:

> From: Ludovic Desroches<ludovic.desroches at atmel.com>

> The HSMCI operates at a rate of up to Master Clock divided by two.

> Signed-off-by: Ludovic Desroches<ludovic.desroches at atmel.com>
> ---
>   drivers/mmc/host/atmel-mci.c |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)

> diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> index e4449a5..e161452 100644
> --- a/drivers/mmc/host/atmel-mci.c
> +++ b/drivers/mmc/host/atmel-mci.c
> @@ -480,7 +480,7 @@ err:
>   static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
>   					unsigned int ns)
>   {
> -	return (ns * (host->bus_hz / 1000000) + 999) / 1000;
> +	return (ns * ((host->bus_hz/2) / 1000000) + 999) / 1000;

    Why don't you keep the notation by addign spaces around '/'?
    BTW, could use DIV_ROUND_UP() here.

WBR, Sergei


From nsekhar at ti.com  Wed Mar 21 11:33:33 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 21 Mar 2012 15:33:33 +0000
Subject: [PATCH v8 4/8] ARM: davinci: Consolidate time keeping and irq
 enable
In-Reply-To: <1332274969-15782-5-git-send-email-rob.lee@linaro.org>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <1332274969-15782-5-git-send-email-rob.lee@linaro.org>
Message-ID: <DF0F476B391FA8409C78302C7BA518B631800A07@DBDE01.ent.ti.com>

Hi Rob,

On Wed, Mar 21, 2012 at 01:52:45, Robert Lee wrote:
> Enable core cpuidle timekeeping and irq enabling and remove that
> handling from this code.
> 
> Signed-off-by: Robert Lee <rob.lee at linaro.org>
> Reviewed-by: Kevin Hilman <khilman at ti.com>
> Reviewed-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> Acked-by: Jean Pihet<j-pihet at ti.com>

>  static struct cpuidle_driver davinci_idle_driver = {
> -	.name	= "cpuidle-davinci",
> -	.owner	= THIS_MODULE,
> +	.name		= "cpuidle-davinci",
> +	.owner		= THIS_MODULE,
> +	.states[0]	= ARM_CPUIDLE_WFI_STATE,
> +	.states[1]	= {
> +		.enter			= davinci_enter_idle,
> +		.exit_latency		= 10,
> +		.target_residency	= 100000,

Apart from your other fix patch, can you also update the
target residency of this state to 10000 as is the case
with current code? With the new value the board is entering
this state really infrequently.

Thanks,
Sekhar


From vinod.koul at linux.intel.com  Wed Mar 21 11:39:23 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Wed, 21 Mar 2012 21:09:23 +0530
Subject: [PATCH v3 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332344363.19804.12.camel@vkoul-udesk3>

On Fri, 2012-03-09 at 16:20 +0100, Javier Martin wrote:
> The following series have to be applied on top of the following patches:
> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
> 
> As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
> is deprecated and no new patches are accepted for it.
> 
> This series merges this code into the imx-dma.c dmaengine driver.
> 
> Notes for v3:
>  - I send the whole series again despite some patches being the same. I think
>  this is more comfortable for Vinod than just sending those patches that have
>  been modified.
>  - I've generated my series with the following command this time:
>  'git format-patch -s -13 -M -B --subject-prefix="PATCH v3"' as suggested by
>  Sascha but still removing two files in 01/13 generates a lot of noisy diffs.
>  Sorry about that.
>  - I don't include Sascha's Tested-by since maybe he wants to test this last
>  version.
This doesn't apply for me (starting with 6th) on current slave-dma.next
due to obvious changes which have gone into imx.

Can you quickly rebase the series and resend.

Also while at it please fix the checkpatch error

ERROR: space required after that ',' (ctx:VxV)
#4143: FILE: drivers/dma/imx-dma.c:275:
+       dev_dbg(imxdma->dev,"%s channel %d\n", __func__, channel);


-- 
~Vinod



From nsekhar at ti.com  Wed Mar 21 11:37:57 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 21 Mar 2012 15:37:57 +0000
Subject: [PATCH v8 4/8] ARM: davinci: Consolidate time keeping and irq
 enable
In-Reply-To: <CAP245DW9SdTYNc8XXwiuHzo5Y-aZrLc2qP0MekKkyAT2TosjbQ@mail.gmail.com>
References: <1332274969-15782-1-git-send-email-rob.lee@linaro.org>
 <1332274969-15782-5-git-send-email-rob.lee@linaro.org>
 <CAMXH7KH5kS=wPFdC8QrtnhE6_sZqmsJ8h=6Gs3kfHOTbeHjacA@mail.gmail.com>
 <CAP245DW9SdTYNc8XXwiuHzo5Y-aZrLc2qP0MekKkyAT2TosjbQ@mail.gmail.com>
Message-ID: <DF0F476B391FA8409C78302C7BA518B631800A29@DBDE01.ent.ti.com>

Hi Amit,

On Wed, Mar 21, 2012 at 20:06:29, Amit Kucheria wrote:
> Rob, you should start a new '3.4-fixes' branch containing such
> bugfixes that can be pushed to Len after -rc1.

I think it is OK to send the fixes to Len right away so
he can queue the fixes during merge window if he gets the
chance. That way we may get a non-broken -rc1.

Thanks,
Sekhar


From nsekhar at ti.com  Wed Mar 21 11:50:36 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 21 Mar 2012 15:50:36 +0000
Subject: [PATCH] ARM: davinci: implement DEBUG_LL port choice
In-Reply-To: <20120320095413.GD15647@pengutronix.de>
References: <1331842703-4248-1-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120320095413.GD15647@pengutronix.de>
Message-ID: <DF0F476B391FA8409C78302C7BA518B631800A8C@DBDE01.ent.ti.com>

Hi Uwe,

On Tue, Mar 20, 2012 at 15:24:13, Uwe Kleine-K?nig wrote:

> > diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> > index e0d236d..57019be 100644
> > --- a/arch/arm/Kconfig.debug
> > +++ b/arch/arm/Kconfig.debug
> > @@ -108,6 +108,22 @@ choice
> >  		bool "Kernel low-level debugging on 9263, 9g45 and cap9"
> >  		depends on HAVE_AT91_DBGU1
> >  
> > +	config DEBUG_DAVINCI_UART0
> > +		bool "Kernel low-level debugging on Davinci using uart0
> > +		depends on ARCH_DAVINCI_DM644x
> > +
> > +	config DEBUG_DA8XX_UART1
> > +		bool "Kernel low-level debugging on DA8xx using uart1"
> > +		depends on ARCH_DAVINCI_DA8XX
> > +
> > +	config DEBUG_DA8XX_UART2
> > +		bool "Kernel low-level debugging on DA8xx using uart2"
> > +		depends on ARCH_DAVINCI_DA8XX
> > +
> > +	config DEBUG_TNETV107X_UART1
> > +		bool "Kernel low-level debugging on TNETV107x using uart1
> > +		depends on ARCH_DAVINCI_TNETV107X
> > +
> on the first and the last description line there are the closing "
> missing. Should I resend?

Yes, please do so. I have not yet reviewed/tested this.

Thanks,
Sekhar


From vinod.koul at linux.intel.com  Wed Mar 21 11:59:31 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Wed, 21 Mar 2012 21:29:31 +0530
Subject: [PATCH] dmaengine: at_hdmac: add slave config operation
In-Reply-To: <1331725303-26298-1-git-send-email-nicolas.ferre@atmel.com>
References: <1331725303-26298-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <1332345571.19804.13.camel@vkoul-udesk3>

On Wed, 2012-03-14 at 12:41 +0100, Nicolas Ferre wrote:
> This patch introduces DMA_SLAVE_CONFIG to at_hdmac Atmel DMA driver.
> 
> It is needed to fix a regression in the use of atmel-mci.c driver on Atmel
> AT91 platforms brouth by e2b35f3:
> "dmaengine/dw_dmac: Fix dw_dmac user drivers to adapt to slave_config changes"
> 
> We remove some parts of the private structure "at_dma_slave" and use the
> information provided by "struct dma_slave_config": source/destination
> peripheral registers and access width.
> 
> AT_DMA_SLAVE_WIDTH_* values used previously are not needed anymore as we
> now use the standard ones. Although some conversion functions are needed to
> match register expected values.
> 
> Some AT91 sub-architecture specific files are slightly touched by this patch
> but it cannot be split because it can break compilation.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Applied, thanks
> ---
>  arch/arm/mach-at91/at91sam9g45_devices.c   |    1 -
>  arch/arm/mach-at91/include/mach/at_hdmac.h |   15 -------
>  drivers/dma/at_hdmac.c                     |   56 +++++++++++++++++++++------
>  drivers/dma/at_hdmac_regs.h                |   32 ++++++++++++++++
>  4 files changed, 75 insertions(+), 29 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
> index 96e2adc..28d3401 100644
> --- a/arch/arm/mach-at91/at91sam9g45_devices.c
> +++ b/arch/arm/mach-at91/at91sam9g45_devices.c
> @@ -432,7 +432,6 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
>  
>  	/* DMA slave channel configuration */
>  	atslave->dma_dev = &at_hdmac_device.dev;
> -	atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
>  	atslave->cfg = ATC_FIFOCFG_HALFFIFO
>  			| ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
>  	atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
> diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h
> index 187cb58..fff48d1 100644
> --- a/arch/arm/mach-at91/include/mach/at_hdmac.h
> +++ b/arch/arm/mach-at91/include/mach/at_hdmac.h
> @@ -24,18 +24,6 @@ struct at_dma_platform_data {
>  };
>  
>  /**
> - * enum at_dma_slave_width - DMA slave register access width.
> - * @AT_DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
> - * @AT_DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
> - * @AT_DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
> - */
> -enum at_dma_slave_width {
> -	AT_DMA_SLAVE_WIDTH_8BIT = 0,
> -	AT_DMA_SLAVE_WIDTH_16BIT,
> -	AT_DMA_SLAVE_WIDTH_32BIT,
> -};
> -
> -/**
>   * struct at_dma_slave - Controller-specific information about a slave
>   * @dma_dev: required DMA master device
>   * @tx_reg: physical address of data register used for
> @@ -48,9 +36,6 @@ enum at_dma_slave_width {
>   */
>  struct at_dma_slave {
>  	struct device		*dma_dev;
> -	dma_addr_t		tx_reg;
> -	dma_addr_t		rx_reg;
> -	enum at_dma_slave_width	reg_width;
>  	u32			cfg;
>  	u32			ctrla;
>  };
> diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
> index 5d225dd..b015a5c 100644
> --- a/drivers/dma/at_hdmac.c
> +++ b/drivers/dma/at_hdmac.c
> @@ -647,6 +647,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
>  {
>  	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
>  	struct at_dma_slave	*atslave = chan->private;
> +	struct dma_slave_config	*sconfig = &atchan->dma_sconfig;
>  	struct at_desc		*first = NULL;
>  	struct at_desc		*prev = NULL;
>  	u32			ctrla;
> @@ -668,19 +669,18 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
>  		return NULL;
>  	}
>  
> -	reg_width = atslave->reg_width;
> -
>  	ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla;
>  	ctrlb = ATC_IEN;
>  
>  	switch (direction) {
>  	case DMA_MEM_TO_DEV:
> +		reg_width = convert_buswidth(sconfig->dst_addr_width);
>  		ctrla |=  ATC_DST_WIDTH(reg_width);
>  		ctrlb |=  ATC_DST_ADDR_MODE_FIXED
>  			| ATC_SRC_ADDR_MODE_INCR
>  			| ATC_FC_MEM2PER
>  			| ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF);
> -		reg = atslave->tx_reg;
> +		reg = sconfig->dst_addr;
>  		for_each_sg(sgl, sg, sg_len, i) {
>  			struct at_desc	*desc;
>  			u32		len;
> @@ -708,13 +708,14 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
>  		}
>  		break;
>  	case DMA_DEV_TO_MEM:
> +		reg_width = convert_buswidth(sconfig->src_addr_width);
>  		ctrla |=  ATC_SRC_WIDTH(reg_width);
>  		ctrlb |=  ATC_DST_ADDR_MODE_INCR
>  			| ATC_SRC_ADDR_MODE_FIXED
>  			| ATC_FC_PER2MEM
>  			| ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF);
>  
> -		reg = atslave->rx_reg;
> +		reg = sconfig->src_addr;
>  		for_each_sg(sgl, sg, sg_len, i) {
>  			struct at_desc	*desc;
>  			u32		len;
> @@ -790,12 +791,15 @@ err_out:
>   * atc_dma_cyclic_fill_desc - Fill one period decriptor
>   */
>  static int
> -atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
> +atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
>  		unsigned int period_index, dma_addr_t buf_addr,
> -		size_t period_len, enum dma_transfer_direction direction)
> +		unsigned int reg_width, size_t period_len,
> +		enum dma_transfer_direction direction)
>  {
> -	u32		ctrla;
> -	unsigned int	reg_width = atslave->reg_width;
> +	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
> +	struct at_dma_slave	*atslave = chan->private;
> +	struct dma_slave_config	*sconfig = &atchan->dma_sconfig;
> +	u32			ctrla;
>  
>  	/* prepare common CRTLA value */
>  	ctrla =   ATC_DEFAULT_CTRLA | atslave->ctrla
> @@ -806,7 +810,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
>  	switch (direction) {
>  	case DMA_MEM_TO_DEV:
>  		desc->lli.saddr = buf_addr + (period_len * period_index);
> -		desc->lli.daddr = atslave->tx_reg;
> +		desc->lli.daddr = sconfig->dst_addr;
>  		desc->lli.ctrla = ctrla;
>  		desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED
>  				| ATC_SRC_ADDR_MODE_INCR
> @@ -816,7 +820,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
>  		break;
>  
>  	case DMA_DEV_TO_MEM:
> -		desc->lli.saddr = atslave->rx_reg;
> +		desc->lli.saddr = sconfig->src_addr;
>  		desc->lli.daddr = buf_addr + (period_len * period_index);
>  		desc->lli.ctrla = ctrla;
>  		desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR
> @@ -847,9 +851,11 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
>  {
>  	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
>  	struct at_dma_slave	*atslave = chan->private;
> +	struct dma_slave_config	*sconfig = &atchan->dma_sconfig;
>  	struct at_desc		*first = NULL;
>  	struct at_desc		*prev = NULL;
>  	unsigned long		was_cyclic;
> +	unsigned int		reg_width;
>  	unsigned int		periods = buf_len / period_len;
>  	unsigned int		i;
>  
> @@ -869,8 +875,13 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
>  		return NULL;
>  	}
>  
> +	if (sconfig->direction == DMA_MEM_TO_DEV)
> +		reg_width = convert_buswidth(sconfig->dst_addr_width);
> +	else
> +		reg_width = convert_buswidth(sconfig->src_addr_width);
> +
>  	/* Check for too big/unaligned periods and unaligned DMA buffer */
> -	if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr,
> +	if (atc_dma_cyclic_check_values(reg_width, buf_addr,
>  					period_len, direction))
>  		goto err_out;
>  
> @@ -882,8 +893,8 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
>  		if (!desc)
>  			goto err_desc_get;
>  
> -		if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr,
> -						period_len, direction))
> +		if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr,
> +					     reg_width, period_len, direction))
>  			goto err_desc_get;
>  
>  		atc_desc_chain(&first, &prev, desc);
> @@ -906,6 +917,23 @@ err_out:
>  	return NULL;
>  }
>  
> +static int set_runtime_config(struct dma_chan *chan,
> +			      struct dma_slave_config *sconfig)
> +{
> +	struct at_dma_chan	*atchan = to_at_dma_chan(chan);
> +
> +	/* Check if it is chan is configured for slave transfers */
> +	if (!chan->private)
> +		return -EINVAL;
> +
> +	memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig));
> +
> +	convert_burst(&atchan->dma_sconfig.src_maxburst);
> +	convert_burst(&atchan->dma_sconfig.dst_maxburst);
> +
> +	return 0;
> +}
> +
>  
>  static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
>  		       unsigned long arg)
> @@ -966,6 +994,8 @@ static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
>  		clear_bit(ATC_IS_CYCLIC, &atchan->status);
>  
>  		spin_unlock_irqrestore(&atchan->lock, flags);
> +	} else if (cmd == DMA_SLAVE_CONFIG) {
> +		return set_runtime_config(chan, (struct dma_slave_config *)arg);
>  	} else {
>  		return -ENXIO;
>  	}
> diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h
> index 08fd8a0..897a8bc 100644
> --- a/drivers/dma/at_hdmac_regs.h
> +++ b/drivers/dma/at_hdmac_regs.h
> @@ -207,6 +207,7 @@ enum atc_status {
>   * @save_cfg: configuration register that is saved on suspend/resume cycle
>   * @save_dscr: for cyclic operations, preserve next descriptor address in
>   *             the cyclic list on suspend/resume cycle
> + * @dma_sconfig: configuration for slave transfers, passed via DMA_SLAVE_CONFIG
>   * @lock: serializes enqueue/dequeue operations to descriptors lists
>   * @active_list: list of descriptors dmaengine is being running on
>   * @queue: list of descriptors ready to be submitted to engine
> @@ -222,6 +223,7 @@ struct at_dma_chan {
>  	struct tasklet_struct	tasklet;
>  	u32			save_cfg;
>  	u32			save_dscr;
> +	struct dma_slave_config dma_sconfig;
>  
>  	spinlock_t		lock;
>  
> @@ -243,6 +245,36 @@ static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
>  	return container_of(dchan, struct at_dma_chan, chan_common);
>  }
>  
> +/*
> + * Fix sconfig's burst size according to at_hdmac. We need to convert them as:
> + * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
> + *
> + * This can be done by finding most significant bit set.
> + */
> +static inline void convert_burst(u32 *maxburst)
> +{
> +	if (*maxburst > 1)
> +		*maxburst = fls(*maxburst) - 2;
> +	else
> +		*maxburst = 0;
> +}
> +
> +/*
> + * Fix sconfig's bus width according to at_hdmac.
> + * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
> + */
> +static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
> +{
> +	switch (addr_width) {
> +	case DMA_SLAVE_BUSWIDTH_2_BYTES:
> +		return 1;
> +	case DMA_SLAVE_BUSWIDTH_4_BYTES:
> +		return 2;
> +	default:
> +		/* For 1 byte width or fallback */
> +		return 0;
> +	}
> +}
>  
>  /*--  Controller  ------------------------------------------------------*/
>  


-- 
~Vinod



From ludovic.desroches at atmel.com  Wed Mar 21 14:03:10 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 21 Mar 2012 19:03:10 +0100
Subject: [PATCH 0/4] atmel-mci device tree support 
Message-ID: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>

Hi,

This patch-set adds device tree support for atmel-mci.

Regards

Ludovic

 .../devicetree/bindings/mmc/atmel-hsmci.txt        |   55 +++++++++++++++
 arch/arm/boot/dts/at91sam9g25ek.dts                |   16 ++++
 arch/arm/boot/dts/at91sam9x5.dtsi                  |   14 ++++
 arch/arm/mach-at91/at91sam9x5.c                    |    2 +
 drivers/mmc/host/atmel-mci.c                       |   74 +++++++++++++++++++-
 5 files changed, 158 insertions(+), 3 deletions(-)
 



From ludovic.desroches at atmel.com  Wed Mar 21 14:03:12 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 21 Mar 2012 19:03:12 +0100
Subject: [PATCH 2/4] arm: at91: at91sam9x5 add mci clk_lookup
In-Reply-To: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
References: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1332352994-20983-3-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/mach-at91/at91sam9x5.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 13c8cae..39cbef3 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -225,6 +225,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
+	CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
+	CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
 	CLKDEV_CON_ID("pioA", &pioAB_clk),
 	CLKDEV_CON_ID("pioB", &pioAB_clk),
 	CLKDEV_CON_ID("pioC", &pioCD_clk),
-- 
1.7.5.4



From ludovic.desroches at atmel.com  Wed Mar 21 14:03:14 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 21 Mar 2012 19:03:14 +0100
Subject: [PATCH 4/4] arm: at91: dt: sam9g25ek add mci support
In-Reply-To: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
References: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1332352994-20983-5-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/boot/dts/at91sam9g25ek.dts |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 7a13d09..960de2b 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -32,6 +32,22 @@
 				phy-mode = "rmii";
 				status = "okay";
 			};
+
+			mmc0: mmc at f0008000 {
+				status = "okay";
+				slot at 0 {
+					bus-width = <4>;
+					cd-gpios = <&pioD 15 0>;
+				};
+			};
+
+			mmc1: mmc at f000c000 {
+				status = "okay";
+				slot at 0 {
+					bus-width = <4>;
+					cd-gpios = <&pioD 14 0>;
+				};
+			};
 		};
 
 		usb0: ohci at 00600000 {
-- 
1.7.5.4



From ludovic.desroches at atmel.com  Wed Mar 21 14:03:11 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 21 Mar 2012 19:03:11 +0100
Subject: [PATCH 1/4] mmc: atmel-mci: add device tree support
In-Reply-To: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
References: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1332352994-20983-2-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 .../devicetree/bindings/mmc/atmel-hsmci.txt        |   55 +++++++++++++++
 drivers/mmc/host/atmel-mci.c                       |   74 +++++++++++++++++++-
 2 files changed, 126 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/atmel-hsmci.txt

diff --git a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
new file mode 100644
index 0000000..657f9de
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
@@ -0,0 +1,55 @@
+* Atmel High Speed MultiMedia Card Interface
+
+This controller on atmel products provides an interface for MMC, SD and SDIO
+types of memory cards.
+
+1) MCI node
+
+Required properties:
+- compatible: no blank "atmel,hsmci"
+- reg: should contain HSMCI registers location and length
+- interrupts: should contain HSMCI interrupt number
+- at least one slot node
+
+The node contains child nodes for each slot that the platform uses
+
+Example MCI node:
+
+mmc0: mmc at f0008000 {
+	compatible = "atmel,hsmci";
+	reg = <0xf0008000 0x600>;
+	interrupts = <12 4>;
+
+	[ child node definitions...]
+};
+
+2) slot nodes
+
+Optional properties:
+- bus-width: number of data lines connected to the controller
+- cd-gpios: specify GPIOs for card detection
+- cd-invert: invert the value of external card detect gpio line
+- wp-gpios: specify GPIOs for write protection
+
+Example slot node:
+
+slot at 0 {
+	bus-width = <4>;
+	cd-gpios = <&pioD 15 0>
+	cd-invert;
+};
+
+Example full MCI node:
+mmc0: mmc at f0008000 {
+	compatible = "atmel,hsmci";
+	reg = <0xf0008000 0x600>;
+	interrupts = <12 4>;
+	slot at 0 {
+		bus-width = <4>;
+		cd-gpios = <&pioD 15 0>
+		cd-invert;
+	};
+	slot at 1 {
+		bus-width = <4>;
+	};
+};
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index b5693fd..2d6a04a 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -19,6 +19,9 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
 #include <linux/platform_device.h>
 #include <linux/scatterlist.h>
 #include <linux/seq_file.h>
@@ -477,6 +480,54 @@ err:
 	dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id atmci_dt_ids[] = {
+	{ .compatible = "atmel,hsmci" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, atmci_dt_ids);
+
+static void __init
+atmci_get_of_slots(struct device *dev, struct mci_platform_data *pdata)
+{
+	struct device_node *np = dev->of_node;
+	struct device_node *cnp;
+	unsigned int slot_nb = 0;
+
+	if (!np)
+		return;
+
+	for_each_child_of_node(np, cnp) {
+		if (slot_nb > (ATMCI_MAX_NR_SLOTS-1)) {
+			dev_warn(dev, "can't have more than %d slots\n",
+			         ATMCI_MAX_NR_SLOTS);
+			break;
+		}
+		if (of_property_read_u32(cnp, "bus-width",
+		                         &pdata->slot[slot_nb].bus_width))
+			pdata->slot[slot_nb].bus_width = 1;
+
+		pdata->slot[slot_nb].detect_pin =
+			of_get_named_gpio(cnp, "cd-gpios", 0);
+
+		if (of_find_property(cnp, "cd-invert", NULL))
+			pdata->slot[slot_nb].detect_is_active_high = true;
+
+		pdata->slot[slot_nb].wp_pin =
+			of_get_named_gpio(cnp, "wp-gpios", 0);
+
+		slot_nb++;
+	}
+}
+#else /* CONFIG_OF */
+static inline void
+atmci_get_of_slots(struct device *dev, struct mci_platform_data *pdata)
+{
+	return;
+}
+#endif
+
 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
 					unsigned int ns)
 {
@@ -1847,6 +1898,13 @@ static int __init atmci_init_slot(struct atmel_mci *host,
 	slot->sdc_reg = sdc_reg;
 	slot->sdio_irq = sdio_irq;
 
+	dev_dbg(&mmc->class_dev,
+	        "slot[%u]: bus_width=%u, detect_pin=%d, "
+		"detect_is_active_high=%s, wp_pin=%d\n",
+		id, slot_data->bus_width, slot_data->detect_pin,
+		slot_data->detect_is_active_high ? "true" : "false",
+		slot_data->wp_pin);
+
 	mmc->ops = &atmci_ops;
 	mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
 	mmc->f_max = host->bus_hz / 2;
@@ -2047,9 +2105,17 @@ static int __init atmci_probe(struct platform_device *pdev)
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!regs)
 		return -ENXIO;
-	pdata = pdev->dev.platform_data;
-	if (!pdata)
-		return -ENXIO;
+
+	if (pdev->dev.of_node) {
+		pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+		if (!pdata)
+			return -ENOMEM;
+	} else {
+		pdata = pdev->dev.platform_data;
+		if (!pdata)
+			return -ENXIO;
+	}
+
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0)
 		return irq;
@@ -2109,6 +2175,7 @@ static int __init atmci_probe(struct platform_device *pdev)
 	/* We need at least one slot to succeed */
 	nr_slots = 0;
 	ret = -ENODEV;
+	atmci_get_of_slots(&pdev->dev, pdata);
 	if (pdata->slot[0].bus_width) {
 		ret = atmci_init_slot(host, &pdata->slot[0],
 				0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
@@ -2242,6 +2309,7 @@ static struct platform_driver atmci_driver = {
 	.driver		= {
 		.name		= "atmel_mci",
 		.pm		= ATMCI_PM_OPS,
+		.of_match_table	= of_match_ptr(atmci_dt_ids),
 	},
 };
 
-- 
1.7.5.4



From ludovic.desroches at atmel.com  Wed Mar 21 14:03:13 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 21 Mar 2012 19:03:13 +0100
Subject: [PATCH 3/4] arm: at91: dt: sam9x5 add mci support
In-Reply-To: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
References: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1332352994-20983-4-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/boot/dts/at91sam9x5.dtsi |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index c111001..5846f99 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -191,6 +191,20 @@
 				interrupts = <27 4>;
 				status = "disabled";
 			};
+
+			mmc0: mmc at f0008000 {
+				compatible = "atmel,hsmci";
+				reg = <0xf0008000 0x600>;
+				interrupts = <12 4>;
+				status = "disabled";
+			};
+
+			mmc1: mmc at f000c000 {
+				compatible = "atmel,hsmci";
+				reg = <0xf000c000 0x600>;
+				interrupts = <26 4>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand at 40000000 {
-- 
1.7.5.4



From swarren at wwwdotorg.org  Wed Mar 21 12:15:49 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 21 Mar 2012 10:15:49 -0600
Subject: [PATCH] ARM: tegra: Include assembler.h in sleep.S to fix build
 break
In-Reply-To: <4F677691.8020307@gmail.com>
References: <1332176863-12537-1-git-send-email-swarren@wwwdotorg.org>
 <4F677691.8020307@gmail.com>
Message-ID: <4F69FEB5.2020901@wwwdotorg.org>

On 03/19/2012 12:10 PM, Rob Herring wrote:
> On 03/19/2012 12:07 PM, Stephen Warren wrote:
>> Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro
>> IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's
>> sleep.S to do so.
>>
>> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
> 
> Acked-by: Rob Herring <rob.herring at calxeda.com>

Arnd,

Can you pick up this fix directly into arm-soc, or do you want me to
generate a pull request for this kind of thing too?

ARM: tegra: Include assembler.h in sleep.S to fix build break
http://patchwork.ozlabs.org/patch/147587/

The same goes for:

ARM: tegra: Fix device tree AUXDATA for USB/EHCI
http://patchwork.ozlabs.org/patch/147616/

Thanks.


From dmitry.torokhov at gmail.com  Wed Mar 21 12:32:12 2012
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Wed, 21 Mar 2012 09:32:12 -0700
Subject: [PATCH 0/6] AT91 drivers Kconfig cleanup
In-Reply-To: <4F69B159.5030101@atmel.com>
References: <cover.1331826095.git.nicolas.ferre@atmel.com>
 <7104123.IANagkT9hm@dtor-d630.eng.vmware.com> <4F69B159.5030101@atmel.com>
Message-ID: <2721722.1bE9GCKTjd@dtor-d630.eng.vmware.com>

On Wednesday, March 21, 2012 11:45:45 AM Nicolas Ferre wrote:
> On 03/15/2012 05:50 PM, Dmitry Torokhov :
> > On Thursday, March 15, 2012 04:57:16 PM Nicolas Ferre wrote:
> >> This is a series which deals with AT91 drivers Kconfig entries. Its goal
> >> is
> >> to remove too restrictive dependencies on SoC names.
> >> This will allow to add support for newer SoC seamlessly.
> >> 
> >> One question remains: should I submit those patches through dedicated
> >> sub-maintainer's git trees or can I queue the whole series in arm-soc?
> > 
> > I'm fine if you queue input piece through arm-soc.
> 
> Ok, good: I have "Acknowledgement" by several maintainers: so yes, I
> will send this series via arm-soc.
> 
> Is this means that I can add your "Acked-by"?

Yes, please.

Acked-by: Dmitry Torokhov <dtor at mail.ru>

Thanks.

-- 
Dmitry


From daniel.lezcano at linaro.org  Wed Mar 21 12:42:27 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 17:42:27 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <CAORVsuUeE046O7YJ_fE49NbW1OjZHZX+GuNiDkF0AnzBnSMbxA@mail.gmail.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <4F69A872.50203@ti.com>
 <CAORVsuUeE046O7YJ_fE49NbW1OjZHZX+GuNiDkF0AnzBnSMbxA@mail.gmail.com>
Message-ID: <4F6A04F3.6050306@linaro.org>

On 03/21/2012 02:43 PM, Jean Pihet wrote:
> On Wed, Mar 21, 2012 at 11:07 AM, Santosh Shilimkar
> <santosh.shilimkar at ti.com>  wrote:
>> Daniel,
>>
>> On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
>>> This patchset is a proposition to improve a bit the code.
>>> The changes are code cleanup and does not change the behavior of the
>>> driver itself.
>>>
>>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
>>> and why the WFI is not used ?
>>>
>>> Daniel Lezcano (7):
>>>    ARM: OMAP4: cpuidle - Remove unused valid field
>>>    ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>>>    ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>>>    ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>>>    ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>>>    ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>>>    ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>>>      time
>>>
>> The series looks fine to me in general. This clean-up is applicable
>> for OMAP3 cpuidle code as well.
> Great!
> However OMAP3 has a few specific things that cannot be removed as easily:
> - the 'valid' flag is used because only certain combinations of power
> domains states are possible,

When I look the board-rx51 code I see:

static struct cpuidle_params rx51_cpuidle_params[] = {
	/* C1 */
	{110 + 162, 5 , 1},
	/* C2 */
	{106 + 180, 309, 1},
	/* C3 */
	{107 + 410, 46057, 0},
	/* C4 */
	{121 + 3374, 46057, 0},
	/* C5 */
	{855 + 1146, 46057, 1},
	/* C6 */
	{7580 + 4134, 484329, 0},
	/* C7 */
	{7505 + 15274, 484329, 1},
};

If C3, C4, C6 are not valid, so AFAICS never used in the cpuidle code
why the values are 'exit_latency' and 'target_residency' specified ? I 
mean why don't we have { 0, 0, 0 } ? Is it just for information ?

I understand the purpose of this code but it looks a bit tricky and hard 
to factor out. Is it acceptable to create a new cpuidle driver for rx51 
then we factor out the code between omap3, omap4 and rx51 when all the 
code consistent ?

> - the latency settings can be overriden by the board code, so the
> cpuidle_params struct is needed.
>
>> I want Jean to look at this series because some of his earlier
>> clean up has introduced those custom functions which
>> are getting removed in this series.
>>
>> Regards
>> santosh
>>
>>
>
> Thanks,
> Jean


-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From rob.lee at linaro.org  Wed Mar 21 12:48:25 2012
From: rob.lee at linaro.org (Robert Lee)
Date: Wed, 21 Mar 2012 11:48:25 -0500
Subject: [PATCH] ARM: davinci: Fix for cpuidle consolidation changes
Message-ID: <1332348505-28780-1-git-send-email-rob.lee@linaro.org>

The recent cpuidle consolidation changes erroneously omitted one
critical line of code.

Signed-off-by: Robert Lee <rob.lee at linaro.org>
---
 arch/arm/mach-davinci/cpuidle.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index 93ae096..9107691 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -55,10 +55,11 @@ static int davinci_enter_idle(struct cpuidle_device *dev,
 #define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN	BIT(0)
 
 static struct cpuidle_driver davinci_idle_driver = {
-	.name		= "cpuidle-davinci",
-	.owner		= THIS_MODULE,
-	.states[0]	= ARM_CPUIDLE_WFI_STATE,
-	.states[1]	= {
+	.name			= "cpuidle-davinci",
+	.owner			= THIS_MODULE,
+	.en_core_tk_irqen	= 1,
+	.states[0]		= ARM_CPUIDLE_WFI_STATE,
+	.states[1]		= {
 		.enter			= davinci_enter_idle,
 		.exit_latency		= 10,
 		.target_residency	= 100000,
-- 
1.7.4.1



From robherring2 at gmail.com  Wed Mar 21 13:02:17 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 21 Mar 2012 12:02:17 -0500
Subject: [PATCH] ARM: tegra: Include assembler.h in sleep.S to fix build
 break
In-Reply-To: <4F69FEB5.2020901@wwwdotorg.org>
References: <1332176863-12537-1-git-send-email-swarren@wwwdotorg.org>
 <4F677691.8020307@gmail.com> <4F69FEB5.2020901@wwwdotorg.org>
Message-ID: <4F6A0999.9020104@gmail.com>

On 03/21/2012 11:15 AM, Stephen Warren wrote:
> On 03/19/2012 12:10 PM, Rob Herring wrote:
>> On 03/19/2012 12:07 PM, Stephen Warren wrote:
>>> Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro
>>> IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's
>>> sleep.S to do so.
>>>
>>> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
>>
>> Acked-by: Rob Herring <rob.herring at calxeda.com>
> 
> Arnd,
> 
> Can you pick up this fix directly into arm-soc, or do you want me to
> generate a pull request for this kind of thing too?
> 
> ARM: tegra: Include assembler.h in sleep.S to fix build break
> http://patchwork.ozlabs.org/patch/147587/
> 
> The same goes for:
> 
> ARM: tegra: Fix device tree AUXDATA for USB/EHCI
> http://patchwork.ozlabs.org/patch/147616/
> 

I can take it and send the pull request. I've got a couple of other
fixes as well.

Rob


From swarren at wwwdotorg.org  Wed Mar 21 13:05:08 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 21 Mar 2012 11:05:08 -0600
Subject: [PATCH] ARM: tegra: Include assembler.h in sleep.S to fix build
 break
In-Reply-To: <4F6A0999.9020104@gmail.com>
References: <1332176863-12537-1-git-send-email-swarren@wwwdotorg.org>
 <4F677691.8020307@gmail.com> <4F69FEB5.2020901@wwwdotorg.org>
 <4F6A0999.9020104@gmail.com>
Message-ID: <4F6A0A44.3010304@wwwdotorg.org>

On 03/21/2012 11:02 AM, Rob Herring wrote:
> On 03/21/2012 11:15 AM, Stephen Warren wrote:
>> On 03/19/2012 12:10 PM, Rob Herring wrote:
>>> On 03/19/2012 12:07 PM, Stephen Warren wrote:
>>>> Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro
>>>> IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's
>>>> sleep.S to do so.
>>>>
>>>> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
>>>
>>> Acked-by: Rob Herring <rob.herring at calxeda.com>
>>
>> Arnd,
>>
>> Can you pick up this fix directly into arm-soc, or do you want me to
>> generate a pull request for this kind of thing too?
>>
>> ARM: tegra: Include assembler.h in sleep.S to fix build break
>> http://patchwork.ozlabs.org/patch/147587/
>>
>> The same goes for:
>>
>> ARM: tegra: Fix device tree AUXDATA for USB/EHCI
>> http://patchwork.ozlabs.org/patch/147616/
> 
> I can take it and send the pull request. I've got a couple of other
> fixes as well.

That's just for the sleep.S change, right.


From hartleys at visionengravers.com  Wed Mar 21 13:12:11 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 21 Mar 2012 12:12:11 -0500
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <4F683B36.8090101@metasoft.pl>
References: <4F683B36.8090101@metasoft.pl>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>

On Tuesday, March 20, 2012 1:09 AM, Rafal Prylowski wrote:
>
> Implement double buffering for M2M DMA channels.
>
> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>

Hmm... This isn't working on my ep9307 board...

When the system boots I get stormed with messages:

dma dma1chan0: unknown interrupt!
dma dma1chan0: unknown interrupt!
dma dma1chan0: unknown interrupt!
dma dma1chan1: unknown interrupt!
dma dma1chan1: unknown interrupt!
dma dma1chan1: unknown interrupt!
dma dma1chan0: unknown interrupt!
dma dma1chan0: unknown interrupt!
dma dma1chan1: unknown interrupt!

Note, I have use_dma set for the ep93xx_spi driver and am using mmc_spi.

Also note, without your patch I also get a couple messages:

dma dma1chan1: got interrupt while active list is empty

But, the mmc card is working fine. I haven't tracked down why I get these
yet. Mika, any ideas?

Regards,
Hartley



From robherring2 at gmail.com  Wed Mar 21 13:19:21 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 21 Mar 2012 12:19:21 -0500
Subject: [PATCH] ARM: tegra: Include assembler.h in sleep.S to fix build
 break
In-Reply-To: <4F6A0A44.3010304@wwwdotorg.org>
References: <1332176863-12537-1-git-send-email-swarren@wwwdotorg.org>
 <4F677691.8020307@gmail.com> <4F69FEB5.2020901@wwwdotorg.org>
 <4F6A0999.9020104@gmail.com> <4F6A0A44.3010304@wwwdotorg.org>
Message-ID: <4F6A0D99.2000309@gmail.com>

On 03/21/2012 12:05 PM, Stephen Warren wrote:
> On 03/21/2012 11:02 AM, Rob Herring wrote:
>> On 03/21/2012 11:15 AM, Stephen Warren wrote:
>>> On 03/19/2012 12:10 PM, Rob Herring wrote:
>>>> On 03/19/2012 12:07 PM, Stephen Warren wrote:
>>>>> Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro
>>>>> IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's
>>>>> sleep.S to do so.
>>>>>
>>>>> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
>>>>
>>>> Acked-by: Rob Herring <rob.herring at calxeda.com>
>>>
>>> Arnd,
>>>
>>> Can you pick up this fix directly into arm-soc, or do you want me to
>>> generate a pull request for this kind of thing too?
>>>
>>> ARM: tegra: Include assembler.h in sleep.S to fix build break
>>> http://patchwork.ozlabs.org/patch/147587/
>>>
>>> The same goes for:
>>>
>>> ARM: tegra: Fix device tree AUXDATA for USB/EHCI
>>> http://patchwork.ozlabs.org/patch/147616/
>>
>> I can take it and send the pull request. I've got a couple of other
>> fixes as well.
> 
> That's just for the sleep.S change, right.

Ah, I missed the 2nd one. So it makes less sense now for me to take it.
I'm still happy to, but it doesn't really save you anything.

Rob

Rob


From jorgeluis.zapata at gmail.com  Wed Mar 21 13:40:24 2012
From: jorgeluis.zapata at gmail.com (Jorge Luis Zapata Muga)
Date: Wed, 21 Mar 2012 18:40:24 +0100
Subject: AMP IPC
Message-ID: <CANThrT_wahTpwRDcx-DGQWpDW7j0psKZsk92-4_+vy_Y=xyvtw@mail.gmail.com>

Hi all,

I have to add support for an ARM based board and develop an IPC
mechanism for its multiple AMP cores it has, looking on the current
state of things, seems that there are several attempts for this,
basically:

- remoteporc/rpmsg based in virtio
- peripheral image loader (PIL)
- PRUSS (Programmable Real-time Unit Sub System)
- maybe others I'm missing?

Could someone explain what has been adopted? is there some common
effort for this need? is there some branch where the patches have been
accepted?

Best Regards


From tony at atomide.com  Wed Mar 21 14:05:37 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 21 Mar 2012 11:05:37 -0700
Subject: [GIT PULL] omap fixes for merge window
Message-ID: <20120321180536.GK9859@atomide.com>

Hi Arnd & Olof,

Here's a set of fixes that would be nice to get merged during
the merge window before the GPIO changes get merged to avoid
boot issues on many omap boards.

The changes queued in the GPIO tree require getting rid of
OMAP_GPIO_IRQ and use gpio_to_irq() instead. This is needed for
dynamically allocated GPIO interrupt ranges.

Ideally these changes would have been done way earlier of course.
Unfortunately this issue was not discovered until last week while
testing linux-next.

Also included is one fix for the wrong __init changes for display.c.

This branch is based on the previously merged fixes-non-critical-part3
as that's pretty much the earliest point where these apply.

Note that these might add on a bit to the existing trivial
merge conflicts with drivers/video related board file clean-up
queued by Tomi.

Regards,

Tony


The following changes since commit 4647ca5761f5534470e98d06494403a2fd0d7b32:
  Tony Lindgren (1):
        ARM: OMAP2+: Fix build for omap4 only builds with missing include of linux/bug.h

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap cleanup-fixes

Tarun Kanti DebBarma (3):
      ARM: OMAP: boards: Fix OMAP_GPIO_IRQ usage with gpio_to_irq()
      drivers: input: Fix OMAP_GPIO_IRQ with gpio_to_irq() in ams_delta_serio_exit()
      ARM: OMAP: Remove OMAP_GPIO_IRQ macro definition

Tomi Valkeinen (1):
      ARM: OMAP2+: Remove __init from DSI mux functions

 arch/arm/mach-omap1/board-h2.c               |    8 ++++----
 arch/arm/mach-omap1/board-h3.c               |    9 ++++-----
 arch/arm/mach-omap1/board-htcherald.c        |    6 +++---
 arch/arm/mach-omap1/board-innovator.c        |    4 ++--
 arch/arm/mach-omap1/board-nokia770.c         |    2 +-
 arch/arm/mach-omap1/board-osk.c              |   12 ++++++------
 arch/arm/mach-omap1/board-palmte.c           |    2 +-
 arch/arm/mach-omap1/board-palmtt.c           |    2 +-
 arch/arm/mach-omap1/board-palmz71.c          |    2 +-
 arch/arm/mach-omap1/board-voiceblue.c        |   16 +++++++---------
 arch/arm/mach-omap2/board-2430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-4430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-apollon.c          |    6 ++++--
 arch/arm/mach-omap2/board-devkit8000.c       |    3 ++-
 arch/arm/mach-omap2/board-h4.c               |    2 +-
 arch/arm/mach-omap2/board-omap3evm.c         |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c       |    2 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c |    3 ++-
 arch/arm/mach-omap2/board-zoom-debugboard.c  |    3 ++-
 arch/arm/mach-omap2/board-zoom-peripherals.c |    6 ++++--
 arch/arm/mach-omap2/common-board-devices.c   |    2 +-
 arch/arm/mach-omap2/display.c                |    8 ++++----
 arch/arm/plat-omap/include/plat/gpio.h       |    4 ----
 drivers/input/serio/ams_delta_serio.c        |    2 +-
 24 files changed, 55 insertions(+), 55 deletions(-)


From nsekhar at ti.com  Wed Mar 21 14:05:54 2012
From: nsekhar at ti.com (Nori, Sekhar)
Date: Wed, 21 Mar 2012 18:05:54 +0000
Subject: [PATCH] ARM: davinci: Fix for cpuidle consolidation changes
In-Reply-To: <1332348505-28780-1-git-send-email-rob.lee@linaro.org>
References: <1332348505-28780-1-git-send-email-rob.lee@linaro.org>
Message-ID: <DF0F476B391FA8409C78302C7BA518B631800C76@DBDE01.ent.ti.com>

On Wed, Mar 21, 2012 at 22:18:25, Robert Lee wrote:
> The recent cpuidle consolidation changes erroneously omitted one
> critical line of code.
> 
> Signed-off-by: Robert Lee <rob.lee at linaro.org>

Tested this on a DA850 EVM.

Acked-by: Sekhar Nori <nsekhar at ti.com>

Thanks,
Sekhar



From swarren at wwwdotorg.org  Wed Mar 21 14:16:10 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 21 Mar 2012 12:16:10 -0600
Subject: [GIT PULL] USB AUXDATA fix for tegra
Message-ID: <4F6A1AEA.7070505@wwwdotorg.org>

Arnd,

This is my first pull request for Tegra; hopefully it all works out OK!

Note: Nobody has ack'd this change. I'm a maintainer for the files that
are touched, but I'm not sure if maintainers are supposed to have
another maintainer ack the change before committing it and sending a
pull request (in particular for their own changes), or if it's up to
their discretion?

The following changes since commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7:
  Linus Torvalds (1):
        Linux 3.3

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git
for-3.4/fixes-for-rc1-and-v3.3

Stephen Warren (1):
      ARM: tegra: Fix device tree AUXDATA for USB/EHCI

 arch/arm/mach-tegra/board-dt-tegra20.c |    6 +++---
 arch/arm/mach-tegra/devices.c          |    7 +++----
 arch/arm/mach-tegra/devices.h          |    5 +++++
 3 files changed, 11 insertions(+), 7 deletions(-)


From arnd at arndb.de  Wed Mar 21 14:26:38 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 21 Mar 2012 18:26:38 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203211404.35847.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <CAOh2x==J4qkp29w+v=GWORBua-DE3yb0MRGOtBLyELxbGZwcuA@mail.gmail.com>
 <201203211404.35847.arnd@arndb.de>
Message-ID: <201203211826.38993.arnd@arndb.de>

On Wednesday 21 March 2012, Arnd Bergmann wrote:
> 
> On Wednesday 21 March 2012, viresh kumar wrote:
> > On Wed, Mar 21, 2012 at 6:06 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > > Just let me know how you want to handle
> > > these things in the future -- the normal way would be to always let you
> > > forward the patches to me, rather than having them applied to arm-soc
> > > directly.
> > 
> > Hmmm. I don't know how exactly it works, but maybe you can add me as
> > an custodian for SPEAr, with a git repo somewhere in kernel.org (?).
> > So that i can apply patches directly to my branch, you pull it.
> > What do you say?
> 
> Yes, that would be the ideal way. You are already listed in the MAINTAINERS
> file, so nothing would change in theory. If you don't have an account on
> kernel.org yet, see http://www.kernel.org/faq/#account for how to get
> one. This will require that you have your gpg keys signed by at least
> one person in the kernel web of trust, so you may have to find people
> locally who can sign yours and are already signed.

I just noticed that you have git trees on http://git.stlinux.com/,
which I would personally prefer you to use actually. git.kernel.org
is most useful for people that don't have their own git servers.

	Arnd


From arnd at arndb.de  Wed Mar 21 14:30:24 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 21 Mar 2012 18:30:24 +0000
Subject: [GIT PULL] USB AUXDATA fix for tegra
In-Reply-To: <4F6A1AEA.7070505@wwwdotorg.org>
References: <4F6A1AEA.7070505@wwwdotorg.org>
Message-ID: <201203211830.25161.arnd@arndb.de>

On Wednesday 21 March 2012, Stephen Warren wrote:
> This is my first pull request for Tegra; hopefully it all works out OK!
> 
> Note: Nobody has ack'd this change. I'm a maintainer for the files that
> are touched, but I'm not sure if maintainers are supposed to have
> another maintainer ack the change before committing it and sending a
> pull request (in particular for their own changes), or if it's up to
> their discretion?
> 

Hi Stephen,

The pull request looks good. There is no need for anyone else to ack
your patches, but you should always post them on the appropriate
mailing lists so people can weigh in if they see something wrong.

I'm currently trying to get the first set of my v3.4 pull requests
out to Linus, so I'll apply this when I'm done with that.

	Arnd


From hartleys at visionengravers.com  Wed Mar 21 14:35:49 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 21 Mar 2012 11:35:49 -0700
Subject: [PATCH] arm: ep93xx: use DEFINE_RES_* macros
Message-ID: <201203211135.49295.hartleys@visionengravers.com>

Use the DEFINE_RES_* macros to reduce some of the boilerplate code.

Signed-off-by: Hartley Sweeten <hsweeten at visionengravers.com>
Cc: Ryan Mallon <rmallon at gmail.com>
Cc: Mika Westerberg <mika.westerberg at iki.fi>

---

diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 8d25895..a2cb176 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -241,11 +241,7 @@ unsigned int ep93xx_chip_revision(void)
  * EP93xx GPIO
  *************************************************************************/
 static struct resource ep93xx_gpio_resource[] = {
-	{
-		.start		= EP93XX_GPIO_PHYS_BASE,
-		.end		= EP93XX_GPIO_PHYS_BASE + 0xcc - 1,
-		.flags		= IORESOURCE_MEM,
-	},
+	DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc),
 };
 
 static struct platform_device ep93xx_gpio_device = {
@@ -288,11 +284,7 @@ static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
 	{ IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
 
 static struct resource ep93xx_rtc_resource[] = {
-	{
-		.start		= EP93XX_RTC_PHYS_BASE,
-		.end		= EP93XX_RTC_PHYS_BASE + 0x10c - 1,
-		.flags		= IORESOURCE_MEM,
-	},
+	DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c),
 };
 
 static struct platform_device ep93xx_rtc_device = {
@@ -304,16 +296,8 @@ static struct platform_device ep93xx_rtc_device = {
 
 
 static struct resource ep93xx_ohci_resources[] = {
-	[0] = {
-		.start	= EP93XX_USB_PHYS_BASE,
-		.end	= EP93XX_USB_PHYS_BASE + 0x0fff,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= IRQ_EP93XX_USB,
-		.end	= IRQ_EP93XX_USB,
-		.flags	= IORESOURCE_IRQ,
-	},
+	DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000),
+	DEFINE_RES_IRQ(IRQ_EP93XX_USB),
 };
 
 
@@ -372,15 +356,8 @@ void __init ep93xx_register_flash(unsigned int width,
 static struct ep93xx_eth_data ep93xx_eth_data;
 
 static struct resource ep93xx_eth_resource[] = {
-	{
-		.start	= EP93XX_ETHERNET_PHYS_BASE,
-		.end	= EP93XX_ETHERNET_PHYS_BASE + 0xffff,
-		.flags	= IORESOURCE_MEM,
-	}, {
-		.start	= IRQ_EP93XX_ETHERNET,
-		.end	= IRQ_EP93XX_ETHERNET,
-		.flags	= IORESOURCE_IRQ,
-	}
+	DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000),
+	DEFINE_REQ_IRQ(IRQ_EP93XX_ETHERNET),
 };
 
 static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
@@ -461,16 +438,8 @@ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
 static struct ep93xx_spi_info ep93xx_spi_master_data;
 
 static struct resource ep93xx_spi_resources[] = {
-	{
-		.start	= EP93XX_SPI_PHYS_BASE,
-		.end	= EP93XX_SPI_PHYS_BASE + 0x18 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		.start	= IRQ_EP93XX_SSP,
-		.end	= IRQ_EP93XX_SSP,
-		.flags	= IORESOURCE_IRQ,
-	},
+	DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18),
+	DEFINE_RES_IRQ(IRQ_EP93XX_SSP),
 };
 
 static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
@@ -541,11 +510,7 @@ static struct platform_device ep93xx_leds = {
  * EP93xx pwm peripheral handling
  *************************************************************************/
 static struct resource ep93xx_pwm0_resource[] = {
-	{
-		.start	= EP93XX_PWM_PHYS_BASE,
-		.end	= EP93XX_PWM_PHYS_BASE + 0x10 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
+	DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10),
 };
 
 static struct platform_device ep93xx_pwm0_device = {
@@ -556,11 +521,7 @@ static struct platform_device ep93xx_pwm0_device = {
 };
 
 static struct resource ep93xx_pwm1_resource[] = {
-	{
-		.start	= EP93XX_PWM_PHYS_BASE + 0x20,
-		.end	= EP93XX_PWM_PHYS_BASE + 0x30 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
+	DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10),
 };
 
 static struct platform_device ep93xx_pwm1_device = {
@@ -628,11 +589,7 @@ EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
 static struct ep93xxfb_mach_info ep93xxfb_data;
 
 static struct resource ep93xx_fb_resource[] = {
-	{
-		.start		= EP93XX_RASTER_PHYS_BASE,
-		.end		= EP93XX_RASTER_PHYS_BASE + 0x800 - 1,
-		.flags		= IORESOURCE_MEM,
-	},
+	DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800),
 };
 
 static struct platform_device ep93xx_fb_device = {
@@ -680,15 +637,8 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
 static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
 
 static struct resource ep93xx_keypad_resource[] = {
-	{
-		.start	= EP93XX_KEY_MATRIX_PHYS_BASE,
-		.end	= EP93XX_KEY_MATRIX_PHYS_BASE + 0x0c - 1,
-		.flags	= IORESOURCE_MEM,
-	}, {
-		.start	= IRQ_EP93XX_KEY,
-		.end	= IRQ_EP93XX_KEY,
-		.flags	= IORESOURCE_IRQ,
-	},
+	DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c),
+	DEFINE_RES_IRQ(IRQ_EP93XX_KEY),
 };
 
 static struct platform_device ep93xx_keypad_device = {
@@ -761,11 +711,7 @@ EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
  * EP93xx I2S audio peripheral handling
  *************************************************************************/
 static struct resource ep93xx_i2s_resource[] = {
-	{
-		.start	= EP93XX_I2S_PHYS_BASE,
-		.end	= EP93XX_I2S_PHYS_BASE + 0x100 - 1,
-		.flags	= IORESOURCE_MEM,
-	},
+	DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
 };
 
 static struct platform_device ep93xx_i2s_device = {
@@ -824,16 +770,8 @@ EXPORT_SYMBOL(ep93xx_i2s_release);
  * EP93xx AC97 audio peripheral handling
  *************************************************************************/
 static struct resource ep93xx_ac97_resources[] = {
-	{
-		.start	= EP93XX_AAC_PHYS_BASE,
-		.end	= EP93XX_AAC_PHYS_BASE + 0xac - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		.start	= IRQ_EP93XX_AACINTR,
-		.end	= IRQ_EP93XX_AACINTR,
-		.flags	= IORESOURCE_IRQ,
-	},
+	DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac),
+	DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR),
 };
 
 static struct platform_device ep93xx_ac97_device = {


From skannan at codeaurora.org  Wed Mar 21 14:38:58 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 21 Mar 2012 11:38:58 -0700
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <alpine.DEB.2.00.1203210130520.30543@utopia.booyaka.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <CAP245DXV5oE+-y+PQCcSM016h-J+UgTi1efmdrcyeQge4k1Cfw@mail.gmail.com>
 <201203161218.05125.arnd.bergmann@linaro.org>
 <201203162057.58706.arnd@arndb.de>
 <alpine.DEB.2.00.1203161509470.4395@utopia.booyaka.com>
 <20120316234706.GJ3852@pengutronix.de>
 <alpine.DEB.2.00.1203201611330.22974@utopia.booyaka.com>
 <alpine.LFD.2.02.1203202233340.24151@xanadu.home>
 <4F694A6A.4050706@codeaurora.org>
 <alpine.DEB.2.00.1203210130520.30543@utopia.booyaka.com>
Message-ID: <4F6A2042.9030302@codeaurora.org>

On 03/21/2012 12:44 AM, Paul Walmsley wrote:
> Hello Saravana,
>
> On Tue, 20 Mar 2012, Saravana Kannan wrote:
>
>> To add a few more thoughts, while I agree with Paul that there is room for
>> improvement in the APIs, I think the difference in opinion comes when we ask
>> the question:
>>
>> "When we eventually refine the APIs in the future to be more expressive, do we
>> think that the current APIs can or cannot be made as wrappers around the new
>> more expressive APIs?"
>>
>> Absolutes are almost never right, so I can't give an absolute answer.
>> But I'm strongly leaning towards "we can" as the answer to the question.
>> That combined with the reasons Nicholas mentioned is why I think the
>> APIs should not be marked as experimental in anyway.
>
> The resistance to documenting that the clock interface is not
> well-defined, and that therefore it is likely to change, and that users
> should not expect it to be stable, is perplexing to me.
>
> Certainly a Kconfig help text change seems trivial enough.  But even the
> resistance to CONFIG_EXPERIMENTAL has been quite surprising to me, given
> that every single defconfig in arch/arm/defconfig sets it:
>
> $ find arch/arm/configs -type f  | wc -l
> 122
> $ fgrep -r CONFIG_EXPERIMENTAL=y arch/arm/configs | wc -l
> 122
> $
>
> (that includes iMX, by the way...)
>
> Certainly, neither Kconfig change is going to prevent us on OMAP from
> figuring out what else is needed to convert our platform to the common
> clock code.  And given the level of enthusiasm on the lists,

I think the enthusiasm we are seeing are from the clock driver 
developers. And for good reasons. Everyone is tired of having to write 
or rewrite their own implementation.

> I don't think
> it's going to prevent many of the other ARM platforms from experimenting
> with the conversion, either.
>
> So it would be interesting to know more about why you (or anyone else)
> perceive that the Kconfig changes would be harmful.

But the enthusiasm of the clock driver developers doesn't necessarily 
translate to users of the clock APIs (other driver devs). My worry with 
marking it as experimental in Kconfig and to a certain extent in the 
documentation is that it will discourage the driver devs from switching 
to the new APIs. If no one is using the new APIs, then platforms can't 
switch to the common clock framework either. If a lot of platform don't 
convert to the common clock framework, the effort to get it merged in 
now is not also very meaningful.

Also, at the rate at which we come to an agreement on new APIs, I think 
these new APIs should be considered quite stable :-) It's certainly 
better than what we have today. We should encourage driver devs to move 
to these new APIs and get the benefits while we go on another 2 yr cycle 
to agree on the next set of APIs improvements.

And as I said before, I think it's much less likely that we will break 
backward source compatibility when we do the next improvement. We could 
have mostly avoid this large scale change by calling the APIs 
prepare/unprepare/gate/ungate (or whatever) and make clk_enable/disable 
similar to clk_prepare_enable/clk_disable_unprepare(). That would have 
avoid a lot of drivers from having to mess with their clock calls. But 
we didn't think about that in the excitement for improved APIs. I think 
this will still be seared in our minds enough to make sure we don't 
repeat that in the future.

That covers all I have to say on this topic.

-Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From broonie at opensource.wolfsonmicro.com  Wed Mar 21 15:07:42 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 21 Mar 2012 19:07:42 +0000
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <4F6A2042.9030302@codeaurora.org>
References: <4F6A2042.9030302@codeaurora.org>
Message-ID: <20120321190741.GL3226@opensource.wolfsonmicro.com>

On Wed, Mar 21, 2012 at 11:38:58AM -0700, Saravana Kannan wrote:

> >So it would be interesting to know more about why you (or anyone else)
> >perceive that the Kconfig changes would be harmful.

> But the enthusiasm of the clock driver developers doesn't
> necessarily translate to users of the clock APIs (other driver
> devs). My worry with marking it as experimental in Kconfig and to a
> certain extent in the documentation is that it will discourage the
> driver devs from switching to the new APIs. If no one is using the
> new APIs, then platforms can't switch to the common clock framework

These aren't new APIs, the clock API has been around since forever.
For driver authors working on anything that isn't platform specific the
issue has been that it's not implemented at all on the overwhelming
majority of architectures and those that do all have their own random
implementations with their own random quirks and with no ability for
anything except the platform to even try to do incredibly basic stuff
like register a new clock.

Simply having something, anything, in place even if it's going to churn
is a massive step forward here for people working with clocks.
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From linus.walleij at linaro.org  Wed Mar 21 15:08:43 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 21 Mar 2012 20:08:43 +0100
Subject: [PATCH v3] serial: PL011: clear pending interrupts
In-Reply-To: <CAOh2x=nh-aiJ1FQecm=5WsNw=Fph5osNh5C2YU6x9TGrKBoMmA@mail.gmail.com>
References: <1331641643-25929-1-git-send-email-linus.walleij@stericsson.com>
 <CAOh2x=nh-aiJ1FQecm=5WsNw=Fph5osNh5C2YU6x9TGrKBoMmA@mail.gmail.com>
Message-ID: <CACRpkdZ-epTV8dAY4gT9HKgPifRS_wfooy0QqEGsSgCqZ98MYw@mail.gmail.com>

On Wed, Mar 21, 2012 at 12:58 PM, viresh kumar <viresh.linux at gmail.com> wrote:
> On Tue, Mar 13, 2012 at 5:57 PM, Linus Walleij
> <linus.walleij at stericsson.com> wrote:
>> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
>> @@ -1927,6 +1930,10 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
>> ? ? ? ? ? ? ? ?goto unmap;
>> ? ? ? ?}
>>
>> + ? ? ? /* Ensure interrupts from this UART are masked and cleared */
>> + ? ? ? writew(0, uap->port.membase + UART011_IMSC);
>> + ? ? ? writew(0xffff, uap->port.membase + UART011_ICR);
>> +
>
> I was working on v3.3 and found a crash for my SoC. When i checked i got a crash
> due to above changes.

Strange, because these changes are not even in 3.3. Did you mean 3.4
HEAD?

> There are two issues here
> ?- uap->port is uninitialized
> ?- clk is not enabled.
>
> How is this working for you?

The uap->port is likely the problem. The clock does not need to be
enabled for this, the clock that need to be enabled is the pclk and that
should be taken care of by the amba/primecell core.

It worked because I had some system which didn't scream when it wrote
into that NULL-address for some reason :-(

I'm sending a fixup patch to sort out my own screwing up.

Yours,
Linus Walleij


From broonie at opensource.wolfsonmicro.com  Wed Mar 21 15:15:07 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 21 Mar 2012 19:15:07 +0000
Subject: [PATCH] clk: Constify parent name arrays
Message-ID: <1332357307-10693-1-git-send-email-broonie@opensource.wolfsonmicro.com>

Drivers should be able to declare their arrays of parent names as const
so the APIs need to accept const arguments.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---

We should probably have a MAINTAINERS entry for the clk API...

 drivers/clk/clk-mux.c        |    2 +-
 drivers/clk/clk.c            |    2 +-
 include/linux/clk-private.h  |    2 +-
 include/linux/clk-provider.h |    4 ++--
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index c71ad1f..bf9f42e 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -91,7 +91,7 @@ struct clk_ops clk_mux_ops = {
 EXPORT_SYMBOL_GPL(clk_mux_ops);
 
 struct clk *clk_register_mux(struct device *dev, const char *name,
-		char **parent_names, u8 num_parents, unsigned long flags,
+		const char **parent_names, u8 num_parents, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_mux_flags, spinlock_t *lock)
 {
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 9cf6f59..33ef0df 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1322,7 +1322,7 @@ out:
  */
 struct clk *clk_register(struct device *dev, const char *name,
 		const struct clk_ops *ops, struct clk_hw *hw,
-		char **parent_names, u8 num_parents, unsigned long flags)
+		const char **parent_names, u8 num_parents, unsigned long flags)
 {
 	struct clk *clk;
 
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 5e4312b..164e115 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -30,7 +30,7 @@ struct clk {
 	const struct clk_ops	*ops;
 	struct clk_hw		*hw;
 	struct clk		*parent;
-	char			**parent_names;
+	const char		**parent_names;
 	struct clk		**parents;
 	u8			num_parents;
 	unsigned long		rate;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5508897..1fa0b0d 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -253,7 +253,7 @@ struct clk_mux {
 #define CLK_MUX_INDEX_BIT		BIT(1)
 
 struct clk *clk_register_mux(struct device *dev, const char *name,
-		char **parent_names, u8 num_parents, unsigned long flags,
+		const char **parent_names, u8 num_parents, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_mux_flags, spinlock_t *lock);
 
@@ -274,7 +274,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
  */
 struct clk *clk_register(struct device *dev, const char *name,
 		const struct clk_ops *ops, struct clk_hw *hw,
-		char **parent_names, u8 num_parents, unsigned long flags);
+		const char **parent_names, u8 num_parents, unsigned long flags);
 
 /* helper functions */
 const char *__clk_get_name(struct clk *clk);
-- 
1.7.9.1



From linus.walleij at linaro.org  Wed Mar 21 15:15:18 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 21 Mar 2012 20:15:18 +0100
Subject: [PATCH] serial: PL011: move interrupt clearing
Message-ID: <1332357318-8017-1-git-send-email-linus.walleij@linaro.org>

Commit 360f748b204275229f8398cb2f9f53955db1503b
"serial: PL011: clear pending interrupts"
attempts to clear interrupts by writing to a
yet-unassigned memory address. This fixes the issue.

The breaking patch is marked for stable so should be
carried along with the other patch.

Cc: Shreshtha Kumar Sahu <shreshthakumar.sahu at stericsson.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: stable <stable at vger.kernel.org>
Reported-by: Viresh Kumar <viresh.kumar at st.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/tty/serial/amba-pl011.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 7e01399..4ed35c5 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1930,10 +1930,6 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 		goto unmap;
 	}
 
-	/* Ensure interrupts from this UART are masked and cleared */
-	writew(0, uap->port.membase + UART011_IMSC);
-	writew(0xffff, uap->port.membase + UART011_ICR);
-
 	uap->vendor = vendor;
 	uap->lcrh_rx = vendor->lcrh_rx;
 	uap->lcrh_tx = vendor->lcrh_tx;
@@ -1951,6 +1947,10 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 	uap->port.line = i;
 	pl011_dma_probe(uap);
 
+	/* Ensure interrupts from this UART are masked and cleared */
+	writew(0, uap->port.membase + UART011_IMSC);
+	writew(0xffff, uap->port.membase + UART011_ICR);
+
 	snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
 
 	amba_ports[i] = uap;
-- 
1.7.7.6



From tony at atomide.com  Wed Mar 21 15:33:04 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 21 Mar 2012 12:33:04 -0700
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <20120321190741.GL3226@opensource.wolfsonmicro.com>
References: <4F6A2042.9030302@codeaurora.org>
 <20120321190741.GL3226@opensource.wolfsonmicro.com>
Message-ID: <20120321193304.GO9859@atomide.com>

* Mark Brown <broonie at opensource.wolfsonmicro.com> [120321 12:11]:
> On Wed, Mar 21, 2012 at 11:38:58AM -0700, Saravana Kannan wrote:
> 
> > >So it would be interesting to know more about why you (or anyone else)
> > >perceive that the Kconfig changes would be harmful.
> 
> > But the enthusiasm of the clock driver developers doesn't
> > necessarily translate to users of the clock APIs (other driver
> > devs). My worry with marking it as experimental in Kconfig and to a
> > certain extent in the documentation is that it will discourage the
> > driver devs from switching to the new APIs. If no one is using the
> > new APIs, then platforms can't switch to the common clock framework
> 
> These aren't new APIs, the clock API has been around since forever.
> For driver authors working on anything that isn't platform specific the
> issue has been that it's not implemented at all on the overwhelming
> majority of architectures and those that do all have their own random
> implementations with their own random quirks and with no ability for
> anything except the platform to even try to do incredibly basic stuff
> like register a new clock.
> 
> Simply having something, anything, in place even if it's going to churn
> is a massive step forward here for people working with clocks.

Right, and now at least the people reading this thread are pretty
aware of the yet unsolved issues with clock fwk api :)

Regards,

Tony


From mika.westerberg at iki.fi  Wed Mar 21 15:32:31 2012
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Wed, 21 Mar 2012 21:32:31 +0200
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>
References: <4F683B36.8090101@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>
Message-ID: <20120321193231.GA3740@mwesterb-mobl.ger.corp.intel.com>

On Wed, Mar 21, 2012 at 12:12:11PM -0500, H Hartley Sweeten wrote:
> On Tuesday, March 20, 2012 1:09 AM, Rafal Prylowski wrote:
> >
> > Implement double buffering for M2M DMA channels.
> >
> > Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
> 
> Hmm... This isn't working on my ep9307 board...
> 
> When the system boots I get stormed with messages:
> 
> dma dma1chan0: unknown interrupt!
> dma dma1chan0: unknown interrupt!
> dma dma1chan0: unknown interrupt!
> dma dma1chan1: unknown interrupt!
> dma dma1chan1: unknown interrupt!
> dma dma1chan1: unknown interrupt!
> dma dma1chan0: unknown interrupt!
> dma dma1chan0: unknown interrupt!
> dma dma1chan1: unknown interrupt!
> 
> Note, I have use_dma set for the ep93xx_spi driver and am using mmc_spi.
> 
> Also note, without your patch I also get a couple messages:
> 
> dma dma1chan1: got interrupt while active list is empty
> 
> But, the mmc card is working fine. I haven't tracked down why I get these
> yet. Mika, any ideas?

I've noticed the same. But they also happen without this patch applied. I've
tracked it down to MULTI_IRQ_HANDLER support patches for ARM vic but not sure
what might be wrong there (or is the ep93xx_dma driver behaving badly). I
noticed that when we get that 'got interrupt while active list is empty' we
don't have any interrupts set in the M2M_INTERRUPT register but we still got
an interrupt.. weird.

Below is a workaround I've been using lately but it certainly is a hack and we
should figure out what is the root cause for this.

diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index dcb004a..cb6b49a 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -441,11 +441,9 @@ static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
 	u32 stat, irq;
 	int handled = 0;
 
-	stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
-	while (stat) {
+	while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
 		irq = ffs(stat) - 1;
 		handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
-		stat &= ~(1 << irq);
 		handled = 1;
 	}
 


From mika.westerberg at iki.fi  Wed Mar 21 15:33:54 2012
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Wed, 21 Mar 2012 21:33:54 +0200
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <4F69878A.4070901@metasoft.pl>
References: <4F683B36.8090101@metasoft.pl>
 <20120321070707.GA25052@mwesterb-mobl.ger.corp.intel.com>
 <4F69878A.4070901@metasoft.pl>
Message-ID: <20120321193354.GB3740@mwesterb-mobl.ger.corp.intel.com>

On Wed, Mar 21, 2012 at 08:47:22AM +0100, Rafal Prylowski wrote:
> On 2012-03-21 08:07, Mika Westerberg wrote:
> > 
> > Which tree this is supposed to apply? I tried both mainline and -next and it
> > doesn't apply cleanly there.
> > 
> 
> I prepared it for git://git.infradead.org/users/vkoul/slave-dma.git tree.
> Also, I checked that it applies cleanly to:
> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
> (I'm assuming this is mainline).

Yes, it applies cleanly. I messed up when applying it. Sorry about that.


From mika.westerberg at iki.fi  Wed Mar 21 15:38:36 2012
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Wed, 21 Mar 2012 21:38:36 +0200
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <4F683B36.8090101@metasoft.pl>
References: <4F683B36.8090101@metasoft.pl>
Message-ID: <20120321193836.GC3740@mwesterb-mobl.ger.corp.intel.com>

On Tue, Mar 20, 2012 at 09:09:26AM +0100, Rafal Prylowski wrote:
> Implement double buffering for M2M DMA channels.
> 
> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>

The subject line prefix should probably be 'dmaengine/ep93xx_dma: ' but
otherwise this looks good.

Acked-by: Mika Westerberg <mika.westerberg at iki.fi>


From skannan at codeaurora.org  Wed Mar 21 15:41:41 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 21 Mar 2012 12:41:41 -0700
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <20120321193304.GO9859@atomide.com>
References: <4F6A2042.9030302@codeaurora.org>
 <20120321190741.GL3226@opensource.wolfsonmicro.com>
 <20120321193304.GO9859@atomide.com>
Message-ID: <4F6A2EF5.3010008@codeaurora.org>

On 03/21/2012 12:33 PM, Tony Lindgren wrote:
> * Mark Brown<broonie at opensource.wolfsonmicro.com>  [120321 12:11]:
>> On Wed, Mar 21, 2012 at 11:38:58AM -0700, Saravana Kannan wrote:
>>
>>>> So it would be interesting to know more about why you (or anyone else)
>>>> perceive that the Kconfig changes would be harmful.
>>
>>> But the enthusiasm of the clock driver developers doesn't
>>> necessarily translate to users of the clock APIs (other driver
>>> devs). My worry with marking it as experimental in Kconfig and to a
>>> certain extent in the documentation is that it will discourage the
>>> driver devs from switching to the new APIs. If no one is using the
>>> new APIs, then platforms can't switch to the common clock framework
>>
>> These aren't new APIs, the clock API has been around since forever.

I disagree. When I say clock API, I mean the actual functions and their 
semantics. Not the existence of a header file.

The meaning of clk_enable/disable has been changed and they won't work 
without calling clk_prepare/unprepare. So, these are definitely new 
APIs. If it weren't new APIs, then none of the general drivers would 
need to change.

>> For driver authors working on anything that isn't platform specific the
>> issue has been that it's not implemented at all on the overwhelming
>> majority of architectures and those that do all have their own random
>> implementations with their own random quirks and with no ability for
>> anything except the platform to even try to do incredibly basic stuff
>> like register a new clock.
>>
>> Simply having something, anything, in place even if it's going to churn
>> is a massive step forward here for people working with clocks.
>
> Right, and now at least the people reading this thread are pretty
> aware of the yet unsolved issues with clock fwk api :)

:-) Shhh... not so loud!

-Saravana


-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From mika.westerberg at iki.fi  Wed Mar 21 15:44:13 2012
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Wed, 21 Mar 2012 21:44:13 +0200
Subject: [PATCH] arm: ep93xx: use DEFINE_RES_* macros
In-Reply-To: <201203211135.49295.hartleys@visionengravers.com>
References: <201203211135.49295.hartleys@visionengravers.com>
Message-ID: <20120321194413.GD3740@mwesterb-mobl.ger.corp.intel.com>

On Wed, Mar 21, 2012 at 11:35:49AM -0700, H Hartley Sweeten wrote:
> Use the DEFINE_RES_* macros to reduce some of the boilerplate code.
> 
> Signed-off-by: Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <rmallon at gmail.com>
> Cc: Mika Westerberg <mika.westerberg at iki.fi>

Nice!

Acked-by: Mika Westerberg <mika.westerberg at iki.fi>


From mturquette at ti.com  Wed Mar 21 15:56:21 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 21 Mar 2012 12:56:21 -0700
Subject: [PATCH 1/2] clk: Fix error handling in fixed clock hardware type
 register fn
In-Reply-To: <20120321090730.GR15988@n2100.arm.linux.org.uk>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <20120320071957.GH3852@pengutronix.de>
 <348585ed29fb3ff171267c03658e6c0d.squirrel@www.codeaurora.org>
 <CAJOA=zO=wp9oyuBZONk2oCRYdWU1c4qanKJik-8-sFg51p27MQ@mail.gmail.com>
 <4F693DD8.7070305@codeaurora.org>
 <CAJOA=zNteC+24oWpqkQJRnL8oqAJe2NcsjHNLbJb1MGN--VEsw@mail.gmail.com>
 <20120321090730.GR15988@n2100.arm.linux.org.uk>
Message-ID: <CAJOA=zMEkPOkSgM2kDrRWaXbyeXKA81Uq3Wv3KrbMbQOVv9CNA@mail.gmail.com>

On Wed, Mar 21, 2012 at 2:07 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Tue, Mar 20, 2012 at 10:45:36PM -0700, Turquette, Mike wrote:
>> IIRC, that discussion was with respect to the .parent member of struct
>> clk. ?It was decided that having .parent = NULL does not imply that a
>> clock is a root clock, but instead we rely on the CLK_IS_ROOT flag. ?I
>> can't think of any other instance where a NULL clk when returned from
>> a registration function would be useful.
>
> No. ?What I've been saying is that in _drivers_ which use clk_get(),
> the error range is defined by IS_ERR(clk). ?Every other value of
> clk must be assumed by the driver to be valid, no ifs or buts.

Drivers certainly might make calls to clk_register_foo, despite it
being outside of the traditional clock api.  For the sake of
consistency I'll convert the clk_register_foo functions to return
error codes.

Regards,
Mike


From broonie at opensource.wolfsonmicro.com  Wed Mar 21 15:56:34 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 21 Mar 2012 19:56:34 +0000
Subject: [PATCH] clk: Constify parent name arrays
In-Reply-To: <1332357307-10693-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1332357307-10693-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <20120321195633.GB27778@sirena.org.uk>

On Wed, Mar 21, 2012 at 07:15:07PM +0000, Mark Brown wrote:
> Drivers should be able to declare their arrays of parent names as const
> so the APIs need to accept const arguments.

Slight oversight in this one and the updates for the new API version
were simpler than I thought so sending a new version shortly.


From broonie at opensource.wolfsonmicro.com  Wed Mar 21 15:56:56 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 21 Mar 2012 19:56:56 +0000
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <4F6A2EF5.3010008@codeaurora.org>
References: <4F6A2042.9030302@codeaurora.org>
 <20120321190741.GL3226@opensource.wolfsonmicro.com>
 <20120321193304.GO9859@atomide.com>
 <4F6A2EF5.3010008@codeaurora.org>
Message-ID: <20120321195656.GN3226@opensource.wolfsonmicro.com>

On Wed, Mar 21, 2012 at 12:41:41PM -0700, Saravana Kannan wrote:
> On 03/21/2012 12:33 PM, Tony Lindgren wrote:
> >* Mark Brown<broonie at opensource.wolfsonmicro.com>  [120321 12:11]:

> >>These aren't new APIs, the clock API has been around since forever.

> I disagree. When I say clock API, I mean the actual functions and
> their semantics. Not the existence of a header file.

> The meaning of clk_enable/disable has been changed and they won't
> work without calling clk_prepare/unprepare. So, these are definitely
> new APIs. If it weren't new APIs, then none of the general drivers
> would need to change.

clk_prepare() and clk_unprepare() are already there for any clk.h user
and are stubbed in no matter what, they're really not a meaningful
barrier here.
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From broonie at opensource.wolfsonmicro.com  Wed Mar 21 16:01:19 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 21 Mar 2012 20:01:19 +0000
Subject: [PATCH 1/4] clk: fixed-rate: Don't open code kstrdup()
Message-ID: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>

Save a little code by using the library function.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 drivers/clk/clk-fixed-rate.c |    7 +------
 1 files changed, 1 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 90c79fb..cf84e41 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -45,7 +45,6 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 {
 	struct clk_fixed_rate *fixed;
 	char **parent_names = NULL;
-	u8 len;
 
 	fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
 
@@ -63,14 +62,10 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 		if (! parent_names)
 			goto out;
 
-		len = sizeof(char) * strlen(parent_name);
-
-		parent_names[0] = kmalloc(len, GFP_KERNEL);
+		parent_names[0] = kstrdup(parent_name, GFP_KERNEL);
 
 		if (!parent_names[0])
 			goto out;
-
-		strncpy(parent_names[0], parent_name, len);
 	}
 
 out:
-- 
1.7.9.1



From broonie at opensource.wolfsonmicro.com  Wed Mar 21 16:01:21 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 21 Mar 2012 20:01:21 +0000
Subject: [PATCH 3/4] clk: Provide dummy clk_unregister()
In-Reply-To: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <1332360082-25092-3-git-send-email-broonie@opensource.wolfsonmicro.com>

While there's no actual implementation behind it having the call to use
in drivers makes them feel neater from a driver author point of view. An
actual implementation can wait for someone who needs to use the function
in a real system.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 drivers/clk/clk.c            |   12 ++++++++++++
 include/linux/clk-provider.h |    1 +
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 33ef0df..31419ca 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1344,6 +1344,18 @@ struct clk *clk_register(struct device *dev, const char *name,
 }
 EXPORT_SYMBOL_GPL(clk_register);
 
+/**
+ * clk_unregister - unregister a currently registered clock
+ * @clk: clock to unregister
+ *
+ * Currently unimplemented.
+ */
+int clk_unregister(struct clk *clk)
+{
+	return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(clk_unregister);
+
 /***        clk rate change notifiers        ***/
 
 /**
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 340acbc..57c0bd1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -275,6 +275,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 struct clk *clk_register(struct device *dev, const char *name,
 		const struct clk_ops *ops, struct clk_hw *hw,
 		const char **parent_names, u8 num_parents, unsigned long flags);
+int clk_unregister(struct clk *clk);
 
 /* helper functions */
 const char *__clk_get_name(struct clk *clk);
-- 
1.7.9.1



From broonie at opensource.wolfsonmicro.com  Wed Mar 21 16:01:20 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 21 Mar 2012 20:01:20 +0000
Subject: [PATCH 2/4] clk: Constify parent name arrays
In-Reply-To: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <1332360082-25092-2-git-send-email-broonie@opensource.wolfsonmicro.com>

Drivers should be able to declare their arrays of parent names as const
so the APIs need to accept const arguments.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 drivers/clk/clk-fixed-rate.c |    2 +-
 drivers/clk/clk-mux.c        |    2 +-
 drivers/clk/clk.c            |    2 +-
 include/linux/clk-private.h  |    2 +-
 include/linux/clk-provider.h |    6 +++---
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index cf84e41..16bf679 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -44,7 +44,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 		unsigned long fixed_rate)
 {
 	struct clk_fixed_rate *fixed;
-	char **parent_names = NULL;
+	const char **parent_names = NULL;
 
 	fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
 
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index c71ad1f..bf9f42e 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -91,7 +91,7 @@ struct clk_ops clk_mux_ops = {
 EXPORT_SYMBOL_GPL(clk_mux_ops);
 
 struct clk *clk_register_mux(struct device *dev, const char *name,
-		char **parent_names, u8 num_parents, unsigned long flags,
+		const char **parent_names, u8 num_parents, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_mux_flags, spinlock_t *lock)
 {
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 9cf6f59..33ef0df 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1322,7 +1322,7 @@ out:
  */
 struct clk *clk_register(struct device *dev, const char *name,
 		const struct clk_ops *ops, struct clk_hw *hw,
-		char **parent_names, u8 num_parents, unsigned long flags)
+		const char **parent_names, u8 num_parents, unsigned long flags)
 {
 	struct clk *clk;
 
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 5e4312b..164e115 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -30,7 +30,7 @@ struct clk {
 	const struct clk_ops	*ops;
 	struct clk_hw		*hw;
 	struct clk		*parent;
-	char			**parent_names;
+	const char		**parent_names;
 	struct clk		**parents;
 	u8			num_parents;
 	unsigned long		rate;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5508897..340acbc 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -212,7 +212,7 @@ struct clk_divider {
 	u8		width;
 	u8		flags;
 	spinlock_t	*lock;
-	char		*parent[1];
+	const char	*parent[1];
 };
 
 #define CLK_DIVIDER_ONE_BASED		BIT(0)
@@ -253,7 +253,7 @@ struct clk_mux {
 #define CLK_MUX_INDEX_BIT		BIT(1)
 
 struct clk *clk_register_mux(struct device *dev, const char *name,
-		char **parent_names, u8 num_parents, unsigned long flags,
+		const char **parent_names, u8 num_parents, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_mux_flags, spinlock_t *lock);
 
@@ -274,7 +274,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
  */
 struct clk *clk_register(struct device *dev, const char *name,
 		const struct clk_ops *ops, struct clk_hw *hw,
-		char **parent_names, u8 num_parents, unsigned long flags);
+		const char **parent_names, u8 num_parents, unsigned long flags);
 
 /* helper functions */
 const char *__clk_get_name(struct clk *clk);
-- 
1.7.9.1



From broonie at opensource.wolfsonmicro.com  Wed Mar 21 16:01:22 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 21 Mar 2012 20:01:22 +0000
Subject: [PATCH 4/4] clk: wm831x: Add initial WM831x clock driver
In-Reply-To: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <1332360082-25092-4-git-send-email-broonie@opensource.wolfsonmicro.com>

The WM831x and WM832x series of PMICs contain a flexible clocking
subsystem intended to provide always on and system core clocks.  It
features:

- A 32.768kHz crystal oscillator which can optionally be used to pass
  through an externally generated clock.
- A FLL which can be clocked from either the 32.768kHz oscillator or
  the CLKIN pin.
- A CLKOUT pin which can bring out either the oscillator or the FLL
  output.
- The 32.768kHz clock can also optionally be brought out on the GPIO
  pins of the device.

This driver fully supports the 32.768kHz oscillator and CLKOUT.  The FLL
is supported only in AUTO mode, the full flexibility of the FLL cannot
currently be used.

Due to a lack of access to systems where the core SoC has been converted
to use the generic clock API this driver has been compile tested only.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 MAINTAINERS              |    1 +
 drivers/clk/Kconfig      |    7 +
 drivers/clk/Makefile     |    1 +
 drivers/clk/clk-wm831x.c |  412 ++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 421 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-wm831x.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 19b25e7..bf8ddc3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7475,6 +7475,7 @@ W:	http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices
 S:	Supported
 F:	Documentation/hwmon/wm83??
 F:	arch/arm/mach-s3c64xx/mach-crag6410*
+F:	drivers/clk/clk-wm83*.c
 F:	drivers/leds/leds-wm83*.c
 F:	drivers/hwmon/wm83??-hwmon.c
 F:	drivers/input/misc/wm831x-on.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 165e1fe..367ba74 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -44,4 +44,11 @@ config COMMON_CLK_DEBUG
 	  clk_flags, clk_prepare_count, clk_enable_count &
 	  clk_notifier_count.
 
+config COMMON_CLK_WM831X
+	tristate "Clock driver for WM831x/2x PMICs"
+	depends on MFD_WM831X
+	---help---
+          Supports the clocking subsystem of the WM831x/2x series of
+	  PMICs from Wolfson Microlectronics.
+
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1f736bc..a155102 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -2,3 +2,4 @@
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
 				   clk-mux.o clk-divider.o
+obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
new file mode 100644
index 0000000..24efd31
--- /dev/null
+++ b/drivers/clk/clk-wm831x.c
@@ -0,0 +1,412 @@
+/*
+ * WM831x clock control
+ *
+ * Copyright 2011-2 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie at opensource.wolfsonmicro.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/wm831x/core.h>
+
+struct wm831x_clk {
+	struct wm831x *wm831x;
+	struct clk_hw xtal_hw;
+	struct clk_hw fll_hw;
+	struct clk_hw clkout_hw;
+	bool xtal_ena;
+};
+
+static int wm831x_xtal_is_enabled(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  xtal_hw);
+
+	return clkdata->xtal_ena;
+}
+
+static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
+					     unsigned long parent_rate)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  xtal_hw);
+
+	if (clkdata->xtal_ena)
+		return 32768;
+	else
+		return 0;
+}
+
+static const struct clk_ops wm831x_xtal_ops = {
+	.is_enabled = wm831x_xtal_is_enabled,
+	.recalc_rate = wm831x_xtal_recalc_rate,
+};
+
+static const unsigned long wm831x_fll_auto_rates[] = {
+	 2048000,
+	11289600,
+	12000000,
+	12288000,
+	19200000,
+	22579600,
+	24000000,
+	24576000,
+};
+
+static int wm831x_fll_is_enabled(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
+			ret);
+		return true;
+	}
+
+	return (ret & WM831X_FLL_ENA) != 0;
+}
+
+static int wm831x_fll_prepare(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2,
+			      WM831X_FLL_ENA, WM831X_FLL_ENA);
+	if (ret != 0)
+		dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
+
+	udelay_range(2000, 2000);
+
+	return ret;
+}
+
+static void wm831x_fll_unprepare(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2, WM831X_FLL_ENA, 0);
+	if (ret != 0)
+		dev_crit(wm831x->dev, "Failed to disaable FLL: %d\n", ret);
+}
+
+static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
+					    unsigned long parent_rate)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
+			ret);
+		return 0;
+	}
+
+	if (ret & WM831X_FLL_AUTO)
+		return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
+
+	dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");
+
+	return 0;
+}
+
+static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
+				  unsigned long *unused)
+{
+	int best = 0;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
+		if (abs(wm831x_fll_auto_rates[i] - rate) <
+		    abs(wm831x_fll_auto_rates[best] - rate))
+			best = i;
+
+	return wm831x_fll_auto_rates[best];
+}
+
+static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
+		if (wm831x_fll_auto_rates[i] == rate)
+			break;
+	if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
+		return -EINVAL;
+
+	if (wm831x_fll_is_enabled(hw))
+		return -EPERM;
+
+	return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
+			       WM831X_FLL_AUTO_FREQ_MASK, i);
+}
+
+static const char *wm831x_fll_parents[] = {
+	"xtal",
+	"clkin",
+};
+
+static u8 wm831x_fll_get_parent(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	/* AUTO mode is always clocked from the crystal */
+	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
+			ret);
+		return 0;
+	}
+
+	if (ret & WM831X_FLL_AUTO)
+		return 0;
+
+	ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
+			ret);
+		return 0;
+	}
+
+	switch (ret & WM831X_FLL_CLK_SRC_MASK) {
+	case 0:
+		return 0;
+	case 1:
+		return 1;
+	default:
+		dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
+			ret & WM831X_FLL_CLK_SRC_MASK);
+		return 0;
+	}
+}
+
+static const struct clk_ops wm831x_fll_ops = {
+	.is_enabled = wm831x_fll_is_enabled,
+	.prepare = wm831x_fll_prepare,
+	.unprepare = wm831x_fll_unprepare,
+	.round_rate = wm831x_fll_round_rate,
+	.recalc_rate = wm831x_fll_recalc_rate,
+	.set_rate = wm831x_fll_set_rate,
+	.get_parent = wm831x_fll_get_parent,
+};
+
+static int wm831x_clkout_is_enabled(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  clkout_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
+			ret);
+		return true;
+	}
+
+	return (ret & WM831X_CLKOUT_ENA) != 0;
+}
+
+static int wm831x_clkout_prepare(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  clkout_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_unlock(wm831x);
+	if (ret != 0) {
+		dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
+		return ret;
+	}
+
+	ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
+			      WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
+	if (ret != 0)
+		dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
+
+	wm831x_reg_lock(wm831x);
+
+	return ret;
+}
+
+static void wm831x_clkout_unprepare(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  clkout_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_unlock(wm831x);
+	if (ret != 0) {
+		dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
+		return;
+	}
+
+	ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
+			      WM831X_CLKOUT_ENA, 0);
+	if (ret != 0)
+		dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
+
+	wm831x_reg_lock(wm831x);
+}
+
+static unsigned long wm831x_clkout_recalc_rate(struct clk_hw *hw,
+					       unsigned long parent_rate)
+{
+	return parent_rate;
+}
+
+static const char *wm831x_clkout_parents[] = {
+	"xtal",
+	"fll",
+};
+
+static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  clkout_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
+			ret);
+		return 0;
+	}
+
+	if (ret & WM831X_CLKOUT_SRC)
+		return 0;
+	else
+		return 1;
+}
+
+static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  clkout_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+
+	if (parent > ARRAY_SIZE(wm831x_clkout_parents))
+		return -EINVAL;
+
+	return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
+			       WM831X_CLKOUT_SRC,
+			       parent << WM831X_CLKOUT_SRC_SHIFT);
+}
+
+static const struct clk_ops wm831x_clkout_ops = {
+	.is_enabled = wm831x_clkout_is_enabled,
+	.prepare = wm831x_clkout_prepare,
+	.unprepare = wm831x_clkout_unprepare,
+	.recalc_rate = wm831x_clkout_recalc_rate,
+	.get_parent = wm831x_clkout_get_parent,
+	.set_parent = wm831x_clkout_set_parent,
+};
+
+static __devinit int wm831x_clk_probe(struct platform_device *pdev)
+{
+	struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
+	struct wm831x_clk *clkdata;
+	int ret;
+
+	clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
+	if (!clkdata)
+		return -ENOMEM;
+
+	/* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
+	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
+			ret);
+		return ret;
+	}
+	clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
+
+	if (!clk_register(&pdev->dev, "xtal", &wm831x_xtal_ops,
+			  &clkdata->xtal_hw, NULL, 0, CLK_IS_ROOT))
+		return -EINVAL;
+
+	if (!clk_register(&pdev->dev, "fll", &wm831x_fll_ops, &clkdata->fll_hw,
+			  wm831x_fll_parents, ARRAY_SIZE(wm831x_fll_parents),
+			  0)) {
+		ret = -EINVAL;
+		goto err_xtal;
+	}
+
+	if (!clk_register(&pdev->dev, "clkout", &wm831x_clkout_ops,
+			  &clkdata->clkout_hw, wm831x_clkout_parents,
+			  ARRAY_SIZE(wm831x_clkout_parents),
+			  CLK_SET_RATE_PARENT)) {
+		ret = -EINVAL;
+		goto err_fll;
+	}
+
+	dev_set_drvdata(&pdev->dev, clkdata);
+
+	return 0;
+
+err_fll:
+	clk_unregister(clkdata->fll_hw.clk);
+err_xtal:
+	clk_unregister(clkdata->xtal_hw.clk);
+	return ret;
+}
+
+static __devexit int wm831x_clk_remove(struct platform_device *pdev)
+{
+	struct wm831x_clk *clkdata = dev_get_drvdata(&pdev->dev);
+
+	clk_unregister(clkdata->clkout_hw.clk);
+	clk_unregister(clkdata->fll_hw.clk);
+	clk_unregister(clkdata->xtal_hw.clk);
+
+	return 0;
+}
+
+static struct platform_driver wm831x_clk_driver = {
+	.probe = wm831x_clk_probe,
+	.remove = __devexit_p(wm831x_clk_remove),
+	.driver		= {
+		.name	= "wm831x-clk",
+		.owner	= THIS_MODULE,
+	},
+};
+
+module_platform_driver(wm831x_clk_driver);
+
+/* Module information */
+MODULE_AUTHOR("Mark Brown <broonie at opensource.wolfsonmicro.com>");
+MODULE_DESCRIPTION("WM831x clock driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:wm831x-clk");
-- 
1.7.9.1



From skannan at codeaurora.org  Wed Mar 21 16:04:22 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 21 Mar 2012 13:04:22 -0700
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <20120321195656.GN3226@opensource.wolfsonmicro.com>
References: <4F6A2042.9030302@codeaurora.org>
 <20120321190741.GL3226@opensource.wolfsonmicro.com>
 <20120321193304.GO9859@atomide.com> <4F6A2EF5.3010008@codeaurora.org>
 <20120321195656.GN3226@opensource.wolfsonmicro.com>
Message-ID: <4F6A3446.9020809@codeaurora.org>

On 03/21/2012 12:56 PM, Mark Brown wrote:
> On Wed, Mar 21, 2012 at 12:41:41PM -0700, Saravana Kannan wrote:
>> On 03/21/2012 12:33 PM, Tony Lindgren wrote:
>>> * Mark Brown<broonie at opensource.wolfsonmicro.com>   [120321 12:11]:
>
>>>> These aren't new APIs, the clock API has been around since forever.
>
>> I disagree. When I say clock API, I mean the actual functions and
>> their semantics. Not the existence of a header file.
>
>> The meaning of clk_enable/disable has been changed and they won't
>> work without calling clk_prepare/unprepare. So, these are definitely
>> new APIs. If it weren't new APIs, then none of the general drivers
>> would need to change.
>
> clk_prepare() and clk_unprepare() are already there for any clk.h user
> and are stubbed in no matter what, they're really not a meaningful
> barrier here.

Isn't this whole experimental vs non-experimental discussion about the 
actual external facing clock APIs and not the platform driver facing APIs?

Sure, prepare/unprepare are already there in the .h file. But they are 
stubs and have no impact till we move to the common clock framework or 
platforms move to them with their own implementation (certainly not 
happening in upstream, so let's leave that part out of this discussion).

So. IMO, for all practical purposes, common clk fwk forces the move to 
these new APIs and hence IMO forces the new APIs.

-Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From broonie at opensource.wolfsonmicro.com  Wed Mar 21 16:10:16 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 21 Mar 2012 20:10:16 +0000
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <4F6A3446.9020809@codeaurora.org>
References: <4F6A2042.9030302@codeaurora.org>
 <20120321190741.GL3226@opensource.wolfsonmicro.com>
 <20120321193304.GO9859@atomide.com>
 <4F6A2EF5.3010008@codeaurora.org>
 <20120321195656.GN3226@opensource.wolfsonmicro.com>
 <4F6A3446.9020809@codeaurora.org>
Message-ID: <20120321201015.GP3226@opensource.wolfsonmicro.com>

On Wed, Mar 21, 2012 at 01:04:22PM -0700, Saravana Kannan wrote:

> Sure, prepare/unprepare are already there in the .h file. But they
> are stubs and have no impact till we move to the common clock
> framework or platforms move to them with their own implementation
> (certainly not happening in upstream, so let's leave that part out
> of this discussion).

> So. IMO, for all practical purposes, common clk fwk forces the move
> to these new APIs and hence IMO forces the new APIs.

Sure, if you want to look at it from that point of view - anything
wanting to run on a platform which uses the generic API needs to use
them, but there's no blocker on the user from this (it can convert with
or without the platform it runs on) - but it's hardly a tough sell.
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From robherring2 at gmail.com  Wed Mar 21 16:13:49 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 21 Mar 2012 15:13:49 -0500
Subject: [PATCH 1/2] ARM: dma-mapping: convert
 ARCH_HAS_DMA_SET_COHERENT_MASK to kconfig symbol
In-Reply-To: <CAN1soZwXh6DviO5CHcj_ogM1VK23V2c4CKZf+iMmeP43rwtW9w@mail.gmail.com>
References: <4F68CD9C.3090001@windriver.com>
 <1332296149-28110-1-git-send-email-robherring2@gmail.com>
 <alpine.LFD.2.02.1203202230230.24151@xanadu.home>
 <CAN1soZwXh6DviO5CHcj_ogM1VK23V2c4CKZf+iMmeP43rwtW9w@mail.gmail.com>
Message-ID: <4F6A367D.9090102@gmail.com>

On 03/21/2012 03:15 AM, Haojian Zhuang wrote:
> On Wed, Mar 21, 2012 at 10:30 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
>> On Tue, 20 Mar 2012, Rob Herring wrote:
>>
>>> From: Rob Herring <rob.herring at calxeda.com>
>>>
>>> The only users of ARCH_HAS_DMA_SET_COHERENT_MASK are 2 ARM platforms:
>>> ixp4xx and pxa cm_x2xx. We've been getting lucky that the define is
>>> implicitly included before dma-mapping.h, but the removal of io.h broke
>>> things (c334bc1 ARM: make mach/io.h include optional). Since memory.h
>>> is the correct place, but no longer exists, convert the define to a
>>> kconfig entry.
>>>
>>> Reported-by: Paul Gortmaker <paul.gortmaker at windriver.com>
>>> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
>>> Cc: Russell King <linux at arm.linux.org.uk>
>>> Cc: Imre Kaloz <kaloz at openwrt.org>
>>> Cc: Krzysztof Halasa <khc at pm.waw.pl>
>>> Cc: Eric Miao <eric.y.miao at gmail.com>
>>> Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
>>> Cc: Vinod Koul <vinod.koul at intel.com>
>>> Cc: Dan Williams <dan.j.williams at intel.com>
>>
>> Acked-by: Nicolas Pitre <nico at linaro.org>
>>
> Acked.
> 
> Imre & Krzysztof,
> 
> Do you mind that I merge these patches into arch-pxa git tree? Since a
> lot of files in arch-pxa are changed.
> 

I plan to send these 2 along with another fix to arm-soc if that's okay.

Rob


From mturquette at ti.com  Wed Mar 21 16:32:49 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 21 Mar 2012 13:32:49 -0700
Subject: [PATCH 1/4] clk: fixed-rate: Don't open code kstrdup()
In-Reply-To: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <CAJOA=zOCGqUckxXiv5-N6oNXUyMExmEOC6FvdWLJmS_r+QMbTQ@mail.gmail.com>

On Wed, Mar 21, 2012 at 1:01 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> Save a little code by using the library function.
>
> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

Hi Mark,

Thanks for the patch.  I've already solved this in my clk-fixes branch
(working on it now, not yet on the list).  I'm going to re-use the
same approach for the fixed-rate clock as is used for the divider and
gate; the registration functions for those types store the parent_name
in the struct clk_foo and use kstrdup as your patch does below.

Thanks again,
Mike

> ---
> ?drivers/clk/clk-fixed-rate.c | ? ?7 +------
> ?1 files changed, 1 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
> index 90c79fb..cf84e41 100644
> --- a/drivers/clk/clk-fixed-rate.c
> +++ b/drivers/clk/clk-fixed-rate.c
> @@ -45,7 +45,6 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> ?{
> ? ? ? ?struct clk_fixed_rate *fixed;
> ? ? ? ?char **parent_names = NULL;
> - ? ? ? u8 len;
>
> ? ? ? ?fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
>
> @@ -63,14 +62,10 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> ? ? ? ? ? ? ? ?if (! parent_names)
> ? ? ? ? ? ? ? ? ? ? ? ?goto out;
>
> - ? ? ? ? ? ? ? len = sizeof(char) * strlen(parent_name);
> -
> - ? ? ? ? ? ? ? parent_names[0] = kmalloc(len, GFP_KERNEL);
> + ? ? ? ? ? ? ? parent_names[0] = kstrdup(parent_name, GFP_KERNEL);
>
> ? ? ? ? ? ? ? ?if (!parent_names[0])
> ? ? ? ? ? ? ? ? ? ? ? ?goto out;
> -
> - ? ? ? ? ? ? ? strncpy(parent_names[0], parent_name, len);
> ? ? ? ?}
>
> ?out:
> --
> 1.7.9.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From mturquette at ti.com  Wed Mar 21 16:36:36 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 21 Mar 2012 13:36:36 -0700
Subject: [PATCH 3/4] clk: Provide dummy clk_unregister()
In-Reply-To: <1332360082-25092-3-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1332360082-25092-3-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <CAJOA=zP4fbvZf2LFvV8s1DYqMZbbOrCZfWQxY53GOPqvh=R+KQ@mail.gmail.com>

On Wed, Mar 21, 2012 at 1:01 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> While there's no actual implementation behind it having the call to use
> in drivers makes them feel neater from a driver author point of view. An
> actual implementation can wait for someone who needs to use the function
> in a real system.

Thanks for the patch Mark.  I'll include this in my fixes branch.

Regards,
Mike

> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---
> ?drivers/clk/clk.c ? ? ? ? ? ?| ? 12 ++++++++++++
> ?include/linux/clk-provider.h | ? ?1 +
> ?2 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 33ef0df..31419ca 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1344,6 +1344,18 @@ struct clk *clk_register(struct device *dev, const char *name,
> ?}
> ?EXPORT_SYMBOL_GPL(clk_register);
>
> +/**
> + * clk_unregister - unregister a currently registered clock
> + * @clk: clock to unregister
> + *
> + * Currently unimplemented.
> + */
> +int clk_unregister(struct clk *clk)
> +{
> + ? ? ? return -EINVAL;
> +}
> +EXPORT_SYMBOL_GPL(clk_unregister);
> +
> ?/*** ? ? ? ?clk rate change notifiers ? ? ? ?***/
>
> ?/**
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 340acbc..57c0bd1 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -275,6 +275,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
> ?struct clk *clk_register(struct device *dev, const char *name,
> ? ? ? ? ? ? ? ?const struct clk_ops *ops, struct clk_hw *hw,
> ? ? ? ? ? ? ? ?const char **parent_names, u8 num_parents, unsigned long flags);
> +int clk_unregister(struct clk *clk);
>
> ?/* helper functions */
> ?const char *__clk_get_name(struct clk *clk);
> --
> 1.7.9.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From khilman at ti.com  Wed Mar 21 17:54:23 2012
From: khilman at ti.com (Kevin Hilman)
Date: Wed, 21 Mar 2012 14:54:23 -0700
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <4F6A04F3.6050306@linaro.org> (Daniel Lezcano's message of "Wed, 
 21 Mar 2012 17:42:27 +0100")
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <4F69A872.50203@ti.com>
 <CAORVsuUeE046O7YJ_fE49NbW1OjZHZX+GuNiDkF0AnzBnSMbxA@mail.gmail.com>
 <4F6A04F3.6050306@linaro.org>
Message-ID: <873991d3hs.fsf@ti.com>

Daniel Lezcano <daniel.lezcano at linaro.org> writes:

> On 03/21/2012 02:43 PM, Jean Pihet wrote:
>> On Wed, Mar 21, 2012 at 11:07 AM, Santosh Shilimkar
>> <santosh.shilimkar at ti.com>  wrote:
>>> Daniel,
>>>
>>> On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
>>>> This patchset is a proposition to improve a bit the code.
>>>> The changes are code cleanup and does not change the behavior of the
>>>> driver itself.
>>>>
>>>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
>>>> and why the WFI is not used ?
>>>>
>>>> Daniel Lezcano (7):
>>>>    ARM: OMAP4: cpuidle - Remove unused valid field
>>>>    ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>>>>    ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>>>>    ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>>>>    ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>>>>    ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>>>>    ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>>>>      time
>>>>
>>> The series looks fine to me in general. This clean-up is applicable
>>> for OMAP3 cpuidle code as well.
>> Great!
>> However OMAP3 has a few specific things that cannot be removed as easily:
>> - the 'valid' flag is used because only certain combinations of power
>> domains states are possible,
>
> When I look the board-rx51 code I see:
>
> static struct cpuidle_params rx51_cpuidle_params[] = {
> 	/* C1 */
> 	{110 + 162, 5 , 1},
> 	/* C2 */
> 	{106 + 180, 309, 1},
> 	/* C3 */
> 	{107 + 410, 46057, 0},
> 	/* C4 */
> 	{121 + 3374, 46057, 0},
> 	/* C5 */
> 	{855 + 1146, 46057, 1},
> 	/* C6 */
> 	{7580 + 4134, 484329, 0},
> 	/* C7 */
> 	{7505 + 15274, 484329, 1},
> };
>
> If C3, C4, C6 are not valid, so AFAICS never used in the cpuidle code
> why the values are 'exit_latency' and 'target_residency' specified ? I
> mean why don't we have { 0, 0, 0 } ? Is it just for information ?

Yes, because getting those numbers were based on some board-specific
measurements, and we don't want those values to be lost.  Also, some
usage patterns might want to (re)enable those states.

> I understand the purpose of this code but it looks a bit tricky and
> hard to factor out. Is it acceptable to create a new cpuidle driver
> for rx51 then we factor out the code between omap3, omap4 and rx51
> when all the code consistent ?

I don't like that idea.  All the code is the same, the only thing we
need is the ability to pass in board-specific latency numbers for the
C-states.

These latency numbers are obviously quite significant when it comes to
the final power consumption, and these values often depend on
board-specific settings.  Until there are generic frameworks for
defining all the latencies involved, passing these values in from board
files is absolutly needed.

Kevin


From haojian.zhuang at gmail.com  Wed Mar 21 18:17:57 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Thu, 22 Mar 2012 06:17:57 +0800
Subject: [PATCH 1/2] ARM: dma-mapping: convert
 ARCH_HAS_DMA_SET_COHERENT_MASK to kconfig symbol
In-Reply-To: <4F6A367D.9090102@gmail.com>
References: <4F68CD9C.3090001@windriver.com>
 <1332296149-28110-1-git-send-email-robherring2@gmail.com>
 <alpine.LFD.2.02.1203202230230.24151@xanadu.home>
 <CAN1soZwXh6DviO5CHcj_ogM1VK23V2c4CKZf+iMmeP43rwtW9w@mail.gmail.com>
 <4F6A367D.9090102@gmail.com>
Message-ID: <CAN1soZwuvPof9xPH6Q9NhrLBVWcce9+Hn_hVBWR_eFgP0LR4vw@mail.gmail.com>

On Thu, Mar 22, 2012 at 4:13 AM, Rob Herring <robherring2 at gmail.com> wrote:
> On 03/21/2012 03:15 AM, Haojian Zhuang wrote:
>> On Wed, Mar 21, 2012 at 10:30 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
>>> On Tue, 20 Mar 2012, Rob Herring wrote:
>>>
>>>> From: Rob Herring <rob.herring at calxeda.com>
>>>>
>>>> The only users of ARCH_HAS_DMA_SET_COHERENT_MASK are 2 ARM platforms:
>>>> ixp4xx and pxa cm_x2xx. We've been getting lucky that the define is
>>>> implicitly included before dma-mapping.h, but the removal of io.h broke
>>>> things (c334bc1 ARM: make mach/io.h include optional). Since memory.h
>>>> is the correct place, but no longer exists, convert the define to a
>>>> kconfig entry.
>>>>
>>>> Reported-by: Paul Gortmaker <paul.gortmaker at windriver.com>
>>>> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
>>>> Cc: Russell King <linux at arm.linux.org.uk>
>>>> Cc: Imre Kaloz <kaloz at openwrt.org>
>>>> Cc: Krzysztof Halasa <khc at pm.waw.pl>
>>>> Cc: Eric Miao <eric.y.miao at gmail.com>
>>>> Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
>>>> Cc: Vinod Koul <vinod.koul at intel.com>
>>>> Cc: Dan Williams <dan.j.williams at intel.com>
>>>
>>> Acked-by: Nicolas Pitre <nico at linaro.org>
>>>
>> Acked.
>>
>> Imre & Krzysztof,
>>
>> Do you mind that I merge these patches into arch-pxa git tree? Since a
>> lot of files in arch-pxa are changed.
>>
>
> I plan to send these 2 along with another fix to arm-soc if that's okay.
>
> Rob

No problem


From daniel.lezcano at linaro.org  Wed Mar 21 18:20:32 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Wed, 21 Mar 2012 23:20:32 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <873991d3hs.fsf@ti.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <4F69A872.50203@ti.com>
 <CAORVsuUeE046O7YJ_fE49NbW1OjZHZX+GuNiDkF0AnzBnSMbxA@mail.gmail.com>
 <4F6A04F3.6050306@linaro.org> <873991d3hs.fsf@ti.com>
Message-ID: <4F6A5430.2090501@linaro.org>

On 03/21/2012 10:54 PM, Kevin Hilman wrote:
> Daniel Lezcano<daniel.lezcano at linaro.org>  writes:
>
>> On 03/21/2012 02:43 PM, Jean Pihet wrote:
>>> On Wed, Mar 21, 2012 at 11:07 AM, Santosh Shilimkar
>>> <santosh.shilimkar at ti.com>   wrote:
>>>> Daniel,
>>>>
>>>> On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
>>>>> This patchset is a proposition to improve a bit the code.
>>>>> The changes are code cleanup and does not change the behavior of the
>>>>> driver itself.
>>>>>
>>>>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
>>>>> and why the WFI is not used ?
>>>>>
>>>>> Daniel Lezcano (7):
>>>>>     ARM: OMAP4: cpuidle - Remove unused valid field
>>>>>     ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>>>>>     ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>>>>>     ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>>>>>     ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>>>>>     ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>>>>>     ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>>>>>       time
>>>>>
>>>> The series looks fine to me in general. This clean-up is applicable
>>>> for OMAP3 cpuidle code as well.
>>> Great!
>>> However OMAP3 has a few specific things that cannot be removed as easily:
>>> - the 'valid' flag is used because only certain combinations of power
>>> domains states are possible,
>>
>> When I look the board-rx51 code I see:
>>
>> static struct cpuidle_params rx51_cpuidle_params[] = {
>> 	/* C1 */
>> 	{110 + 162, 5 , 1},
>> 	/* C2 */
>> 	{106 + 180, 309, 1},
>> 	/* C3 */
>> 	{107 + 410, 46057, 0},
>> 	/* C4 */
>> 	{121 + 3374, 46057, 0},
>> 	/* C5 */
>> 	{855 + 1146, 46057, 1},
>> 	/* C6 */
>> 	{7580 + 4134, 484329, 0},
>> 	/* C7 */
>> 	{7505 + 15274, 484329, 1},
>> };
>>
>> If C3, C4, C6 are not valid, so AFAICS never used in the cpuidle code
>> why the values are 'exit_latency' and 'target_residency' specified ? I
>> mean why don't we have { 0, 0, 0 } ? Is it just for information ?
>
> Yes, because getting those numbers were based on some board-specific
> measurements, and we don't want those values to be lost.  Also, some
> usage patterns might want to (re)enable those states.

When you say re-enable you mean for a custom kernel ?

>> I understand the purpose of this code but it looks a bit tricky and
>> hard to factor out. Is it acceptable to create a new cpuidle driver
>> for rx51 then we factor out the code between omap3, omap4 and rx51
>> when all the code consistent ?
>
> I don't like that idea.  All the code is the same, the only thing we
> need is the ability to pass in board-specific latency numbers for the
> C-states.

Sorry I was not clear, I was not saying duplicating the code. What I 
meant is to create a driver:

struct cpuidle_driver rx51_idle_driver = {
  	.name = 	"rx51_idle",
	.owner = 	THIS_MODULE,
	.states = {
		{
			/* What is in rx51_cpuidle_params */
		}
	};

We put in there only the valid fields and we keep in a comment the table 
with the latency numbers.

Assuming the valid field is for handling the table overwritting, we can 
then remove it. By this way, we simplify the next_valid_state function.

Depending if we have rx51 or not, we register the rx51 driver or the 
omap3 driver in the init function. That has also the benefit to group 
the cpuidle code in the cpuidle34xx file.


> These latency numbers are obviously quite significant when it comes to
> the final power consumption, and these values often depend on
> board-specific settings.  Until there are generic frameworks for
> defining all the latencies involved, passing these values in from board
> files is absolutly needed.

Yes but before creating the generic framework, we have to do a 
transversal cpuidle consolidation across the SoC, factor out the code 
when possible, and ensure the consistency between the different platform 
and see a common pattern to emerge from this work.

-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From w.sang at pengutronix.de  Wed Mar 21 18:21:59 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed, 21 Mar 2012 23:21:59 +0100
Subject: [PATCH 3/3] rtc: stmp3xxx: use global stmp_device functionality
In-Reply-To: <1332368519-22660-1-git-send-email-w.sang@pengutronix.de>
References: <1332368519-22660-1-git-send-email-w.sang@pengutronix.de>
Message-ID: <1332368519-22660-4-git-send-email-w.sang@pengutronix.de>

The former mach specific reset_block function has been converted to a global
one. Use the new one to remove mach dependency from the driver. Also simplify
code using the new STMP_REG_* macros.

Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
---
 drivers/rtc/Kconfig        |    1 +
 drivers/rtc/rtc-stmp3xxx.c |   29 ++++++++++-------------------
 2 files changed, 11 insertions(+), 19 deletions(-)

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 3a125b8..e124f93 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -983,6 +983,7 @@ config RTC_DRV_COH901331
 config RTC_DRV_STMP
 	tristate "Freescale STMP3xxx/i.MX23/i.MX28 RTC"
 	depends on ARCH_MXS
+	select STMP_DEVICE
 	help
 	  If you say yes here you will get support for the onboard
 	  STMP3xxx/i.MX23/i.MX28 RTC.
diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c
index 1028786..e755d3e 100644
--- a/drivers/rtc/rtc-stmp3xxx.c
+++ b/drivers/rtc/rtc-stmp3xxx.c
@@ -25,11 +25,9 @@
 #include <linux/interrupt.h>
 #include <linux/rtc.h>
 #include <linux/slab.h>
-
-#include <mach/common.h>
+#include <linux/stmp_device.h>
 
 #define STMP3XXX_RTC_CTRL			0x0
-#define STMP3XXX_RTC_CTRL_SET			0x4
 #define STMP3XXX_RTC_CTRL_CLR			0x8
 #define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN		0x00000001
 #define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN	0x00000002
@@ -44,7 +42,6 @@
 #define STMP3XXX_RTC_ALARM			0x40
 
 #define STMP3XXX_RTC_PERSISTENT0		0x60
-#define STMP3XXX_RTC_PERSISTENT0_SET		0x64
 #define STMP3XXX_RTC_PERSISTENT0_CLR		0x68
 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN	0x00000002
 #define STMP3XXX_RTC_PERSISTENT0_ALARM_EN	0x00000004
@@ -106,20 +103,14 @@ static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
 static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
 {
 	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
+	u32 set_clr_offset = enabled ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
+
+	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
+		STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
+		rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + set_clr_offset);
+	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
+		rtc_data->io + STMP3XXX_RTC_CTRL + set_clr_offset);
 
-	if (enabled) {
-		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
-				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
-				rtc_data->io + STMP3XXX_RTC_PERSISTENT0_SET);
-		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
-				rtc_data->io + STMP3XXX_RTC_CTRL_SET);
-	} else {
-		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
-				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
-				rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR);
-		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
-				rtc_data->io + STMP3XXX_RTC_CTRL_CLR);
-	}
 	return 0;
 }
 
@@ -206,7 +197,7 @@ static int stmp3xxx_rtc_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, rtc_data);
 
-	mxs_reset_block(rtc_data->io);
+	stmp_reset_block(rtc_data->io);
 	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
 			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
@@ -253,7 +244,7 @@ static int stmp3xxx_rtc_resume(struct platform_device *dev)
 {
 	struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(dev);
 
-	mxs_reset_block(rtc_data->io);
+	stmp_reset_block(rtc_data->io);
 	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
 			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
-- 
1.7.2.5



From w.sang at pengutronix.de  Wed Mar 21 18:21:56 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed, 21 Mar 2012 23:21:56 +0100
Subject: [PATCH V2 0/3] introduce stmp-style devices
Message-ID: <1332368519-22660-1-git-send-email-w.sang@pengutronix.de>

This series makes support for a certain type of devices mach independant. We
want that because such devices (having a special register layout) have been
found in mach-mxs and mach-mx6 meanwhile. Please refer to patch 1/3 for a more
detailed description.

Patch 1/3 adds the basic support and is of main interest to get upstream.
Patches 2/3 and 3/3 are usage examples and will be send to the relevant
subsystems once the basic support is accepted.

Main changes since the V1:

* moved stmp_device.c from drivers/base to lib/

Main changes since the RFC:

* renamed the macros to STMP_OFFSET_*
* rebased to 3.3-rc6

Tested with a TX28 board.

Thanks,

   Wolfram

Wolfram Sang (3):
  lib: add support for stmp-style devices
  i2c: mxs: use global reset function
  rtc: stmp3xxx: use global stmp_device functionality

 drivers/i2c/busses/Kconfig   |    1 +
 drivers/i2c/busses/i2c-mxs.c |    9 +----
 drivers/rtc/Kconfig          |    1 +
 drivers/rtc/rtc-stmp3xxx.c   |   29 +++++----------
 include/linux/stmp_device.h  |   20 ++++++++++
 lib/Kconfig                  |    3 ++
 lib/Makefile                 |    2 +
 lib/stmp_device.c            |   80 ++++++++++++++++++++++++++++++++++++++++++
 8 files changed, 119 insertions(+), 26 deletions(-)
 create mode 100644 include/linux/stmp_device.h
 create mode 100644 lib/stmp_device.c

-- 
1.7.2.5



From w.sang at pengutronix.de  Wed Mar 21 18:21:58 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed, 21 Mar 2012 23:21:58 +0100
Subject: [PATCH 2/3] i2c: mxs: use global reset function
In-Reply-To: <1332368519-22660-1-git-send-email-w.sang@pengutronix.de>
References: <1332368519-22660-1-git-send-email-w.sang@pengutronix.de>
Message-ID: <1332368519-22660-3-git-send-email-w.sang@pengutronix.de>

The former mach specific reset_block function has been converted to a global
one. Use the new one to remove mach dependency from the driver.

Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
---
 drivers/i2c/busses/Kconfig   |    1 +
 drivers/i2c/busses/i2c-mxs.c |    9 ++-------
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 3101dd5..d4378cf 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -467,6 +467,7 @@ config I2C_MV64XXX
 config I2C_MXS
 	tristate "Freescale i.MX28 I2C interface"
 	depends on SOC_IMX28
+	select STMP_DEVICE
 	help
 	  Say Y here if you want to use the I2C bus controller on
 	  the Freescale i.MX28 processors.
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 3d471d5..0834802 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -26,8 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/jiffies.h>
 #include <linux/io.h>
-
-#include <mach/common.h>
+#include <linux/stmp_device.h>
 
 #define DRIVER_NAME "mxs-i2c"
 
@@ -111,13 +110,9 @@ struct mxs_i2c_dev {
 	struct i2c_adapter adapter;
 };
 
-/*
- * TODO: check if calls to here are really needed. If not, we could get rid of
- * mxs_reset_block and the mach-dependency. Needs an I2C analyzer, probably.
- */
 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
 {
-	mxs_reset_block(i2c->regs);
+	stmp_reset_block(i2c->regs);
 	writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 	writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
 			i2c->regs + MXS_I2C_QUEUECTRL_SET);
-- 
1.7.2.5



From w.sang at pengutronix.de  Wed Mar 21 18:21:57 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed, 21 Mar 2012 23:21:57 +0100
Subject: [PATCH V2 1/3] lib: add support for stmp-style devices
In-Reply-To: <1332368519-22660-1-git-send-email-w.sang@pengutronix.de>
References: <1332368519-22660-1-git-send-email-w.sang@pengutronix.de>
Message-ID: <1332368519-22660-2-git-send-email-w.sang@pengutronix.de>

MX23/28 use IP cores which follow a register layout I have first seen on
STMP3xxx SoCs. In this layout, every register actually has four u32:

 1.) to store a value directly
 2.) a SET register where every 1-bit sets the corresponding bit,
     others are unaffected
 3.) same with a CLR register
 4.) same with a TOG (toggle) register

Also, the 2 MSBs in register 0 are always the same and can be used to reset
the IP core.

All this is strictly speaking not mach-specific (but IP core specific) and,
thus, doesn't need to be in mach-mxs/include. At least, mx6 and mx50 also
utilize IP cores following this stmp-style. So:

Introduce a stmp-style device, put the code and defines for that in a public
place (lib/), and let drivers for stmp-style devices select that code.
To avoid regressions and ease reviewing, the actual code is simply copied from
mach-mxs. It definately wants updates, but those need a seperate patch series.

Voila, mach dependency gone, reusable code introduced. Note that I didn't
remove the duplicated code from mach-mxs yet, first the drivers have to be
converted.

Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
Acked-by: Shawn Guo <shawn.guo at linaro.org>
---
 include/linux/stmp_device.h |   20 +++++++++++
 lib/Kconfig                 |    3 ++
 lib/Makefile                |    2 +
 lib/stmp_device.c           |   80 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 105 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/stmp_device.h
 create mode 100644 lib/stmp_device.c

diff --git a/include/linux/stmp_device.h b/include/linux/stmp_device.h
new file mode 100644
index 0000000..6cf7ec9
--- /dev/null
+++ b/include/linux/stmp_device.h
@@ -0,0 +1,20 @@
+/*
+ * basic functions for devices following the "stmp" style register layout
+ *
+ * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __STMP_DEVICE_H__
+#define __STMP_DEVICE_H__
+
+#define STMP_OFFSET_REG_SET	0x4
+#define STMP_OFFSET_REG_CLR	0x8
+#define STMP_OFFSET_REG_TOG	0xc
+
+extern int stmp_reset_block(void __iomem *);
+#endif /* __STMP_DEVICE_H__ */
diff --git a/lib/Kconfig b/lib/Kconfig
index 028aba9..d4af46f 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -29,6 +29,9 @@ config GENERIC_IOMAP
 	bool
 	select GENERIC_PCI_IOMAP
 
+config STMP_DEVICE
+	bool
+
 config CRC_CCITT
 	tristate "CRC-CCITT functions"
 	help
diff --git a/lib/Makefile b/lib/Makefile
index 18515f0..f78dbcd 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -123,6 +123,8 @@ obj-$(CONFIG_SIGNATURE) += digsig.o
 
 obj-$(CONFIG_CLZ_TAB) += clz_tab.o
 
+obj-$(CONFIG_STMP_DEVICE) += stmp_device.o
+
 hostprogs-y	:= gen_crc32table
 clean-files	:= crc32table.h
 
diff --git a/lib/stmp_device.c b/lib/stmp_device.c
new file mode 100644
index 0000000..8ac9bcc
--- /dev/null
+++ b/lib/stmp_device.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel at pengutronix.de
+ * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok at emcraft.com
+ * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/stmp_device.h>
+
+#define STMP_MODULE_CLKGATE	(1 << 30)
+#define STMP_MODULE_SFTRST	(1 << 31)
+
+/*
+ * Clear the bit and poll it cleared.  This is usually called with
+ * a reset address and mask being either SFTRST(bit 31) or CLKGATE
+ * (bit 30).
+ */
+static int stmp_clear_poll_bit(void __iomem *addr, u32 mask)
+{
+	int timeout = 0x400;
+
+	writel(mask, addr + STMP_OFFSET_REG_CLR);
+	udelay(1);
+	while ((readl(addr) & mask) && --timeout)
+		/* nothing */;
+
+	return !timeout;
+}
+
+int stmp_reset_block(void __iomem *reset_addr)
+{
+	int ret;
+	int timeout = 0x400;
+
+	/* clear and poll SFTRST */
+	ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
+	if (unlikely(ret))
+		goto error;
+
+	/* clear CLKGATE */
+	writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR);
+
+	/* set SFTRST to reset the block */
+	writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET);
+	udelay(1);
+
+	/* poll CLKGATE becoming set */
+	while ((!(readl(reset_addr) & STMP_MODULE_CLKGATE)) && --timeout)
+		/* nothing */;
+	if (unlikely(!timeout))
+		goto error;
+
+	/* clear and poll SFTRST */
+	ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
+	if (unlikely(ret))
+		goto error;
+
+	/* clear and poll CLKGATE */
+	ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_CLKGATE);
+	if (unlikely(ret))
+		goto error;
+
+	return 0;
+
+error:
+	pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
+	return -ETIMEDOUT;
+}
+EXPORT_SYMBOL(stmp_reset_block);
-- 
1.7.2.5



From s.hauer at pengutronix.de  Wed Mar 21 18:26:22 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 21 Mar 2012 23:26:22 +0100
Subject: [PATCH 4/4] clk: wm831x: Add initial WM831x clock driver
In-Reply-To: <1332360082-25092-4-git-send-email-broonie@opensource.wolfsonmicro.com>
References: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1332360082-25092-4-git-send-email-broonie@opensource.wolfsonmicro.com>
Message-ID: <20120321222622.GG29317@pengutronix.de>

On Wed, Mar 21, 2012 at 08:01:22PM +0000, Mark Brown wrote:
> The WM831x and WM832x series of PMICs contain a flexible clocking
> subsystem intended to provide always on and system core clocks.  It
> features:
> 
> - A 32.768kHz crystal oscillator which can optionally be used to pass
>   through an externally generated clock.
> - A FLL which can be clocked from either the 32.768kHz oscillator or
>   the CLKIN pin.
> - A CLKOUT pin which can bring out either the oscillator or the FLL
>   output.
> - The 32.768kHz clock can also optionally be brought out on the GPIO
>   pins of the device.
> 
> This driver fully supports the 32.768kHz oscillator and CLKOUT.  The FLL
> is supported only in AUTO mode, the full flexibility of the FLL cannot
> currently be used.
> 
> Due to a lack of access to systems where the core SoC has been converted
> to use the generic clock API this driver has been compile tested only.
> 
> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---

[...]

> +
> +static unsigned long wm831x_clkout_recalc_rate(struct clk_hw *hw,
> +					       unsigned long parent_rate)
> +{
> +	return parent_rate;
> +}

You should be able to drop this. The clock framework will use the parent
rate automatically if recalc_rate is not present.

> +
> +static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
> +{
> +	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
> +						  clkout_hw);
> +	struct wm831x *wm831x = clkdata->wm831x;
> +
> +	if (parent > ARRAY_SIZE(wm831x_clkout_parents))
> +		return -EINVAL;

Unless you mistrust the clock framework isn't necessary. The framework
checks this already.

> +
> +static __devinit int wm831x_clk_probe(struct platform_device *pdev)
> +{
> +	struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
> +	struct wm831x_clk *clkdata;
> +	int ret;
> +
> +	clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
> +	if (!clkdata)
> +		return -ENOMEM;
> +
> +	/* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
> +	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
> +	if (ret < 0) {
> +		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
> +			ret);
> +		return ret;
> +	}
> +	clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
> +
> +	if (!clk_register(&pdev->dev, "xtal", &wm831x_xtal_ops,
> +			  &clkdata->xtal_hw, NULL, 0, CLK_IS_ROOT))
> +		return -EINVAL;

The clock names are unique identifiers for the clock, so clocks in
drivers should probably have dev_name encoded into them.

You could also use the fixed rate generic clock here.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From snjw23 at gmail.com  Wed Mar 21 18:38:11 2012
From: snjw23 at gmail.com (Sylwester Nawrocki)
Date: Wed, 21 Mar 2012 23:38:11 +0100
Subject: Handling device shared SFR on dt platform
Message-ID: <4F6A5853.9090809@gmail.com>


Hello,

I'm working on adding the device tree support for two devices that
share some IO registers. Exactly, there is one shared SFR that 
contains a common bit to enable two PHY devices, and another two
bits, each to separately reset each PHY.

Currently this shared register is statically memory mapped and it is
handled by a platform specific callback, that both drivers use to
control their corresponding (sub)devices in synchronised manner.

The two devices are a MIPI-CSI2 receiver and a MIPI-DSI transmitter, 
and the common register is there to control the camera and the display 
port PHY. The hardware design is a bit unfortunate, but there is not
much I could do about it.

The callback can be looked at at:
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=arch/arm/plat-s5p/setup-mipiphy.c

I have been trying to find method to handle this on a dt platform. 
Has anyone faced similar issue before ? I would appreciate any ideas
or suggestions.

One of ideas was to create some sort of PHY framework, similar to
clock API, and perhaps handle such platform quirks outside DT.

--

Thanks,
Sylwester


From viresh.linux at gmail.com  Wed Mar 21 20:41:19 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Thu, 22 Mar 2012 06:11:19 +0530
Subject: [PATCH v3] serial: PL011: clear pending interrupts
In-Reply-To: <CACRpkdZ-epTV8dAY4gT9HKgPifRS_wfooy0QqEGsSgCqZ98MYw@mail.gmail.com>
References: <1331641643-25929-1-git-send-email-linus.walleij@stericsson.com>
 <CAOh2x=nh-aiJ1FQecm=5WsNw=Fph5osNh5C2YU6x9TGrKBoMmA@mail.gmail.com>
 <CACRpkdZ-epTV8dAY4gT9HKgPifRS_wfooy0QqEGsSgCqZ98MYw@mail.gmail.com>
Message-ID: <CAOh2x=mrjzX=BuoQW+pdcHsdzyenXFEbt0jNTYf-HV0GNk--1Q@mail.gmail.com>

On Thu, Mar 22, 2012 at 12:38 AM, Linus Walleij
<linus.walleij at linaro.org> wrote:
> Strange, because these changes are not even in 3.3. Did you mean 3.4
> HEAD?

Ya. you are correct, actually i was switching between both of them and so
wrote 3.3 :(

> The uap->port is likely the problem. The clock does not need to be
> enabled for this, the clock that need to be enabled is the pclk and that
> should be taken care of by the amba/primecell core.

Ya. I know uap->port is the problem. But i thought like normal platform drivers
writers: "we need to enable clk too". And i was wrong :(.

> I'm sending a fixup patch to sort out my own screwing up.

Waiting for that.

--
viresh


From linux at arm.linux.org.uk  Wed Mar 21 20:42:58 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 22 Mar 2012 00:42:58 +0000
Subject: [PATCH v7 1/3] Documentation: common clk API
In-Reply-To: <4F6A2EF5.3010008@codeaurora.org>
References: <4F6A2042.9030302@codeaurora.org>
 <20120321190741.GL3226@opensource.wolfsonmicro.com>
 <20120321193304.GO9859@atomide.com> <4F6A2EF5.3010008@codeaurora.org>
Message-ID: <20120322004258.GG16389@n2100.arm.linux.org.uk>

On Wed, Mar 21, 2012 at 12:41:41PM -0700, Saravana Kannan wrote:
> The meaning of clk_enable/disable has been changed and they won't work  
> without calling clk_prepare/unprepare. So, these are definitely new  
> APIs. If it weren't new APIs, then none of the general drivers would  
> need to change.

Yes and no.  I disagree that the meaning of clk_enable/disable() has
changed.  It hasn't.  What has changed is the preconditions for calling
those functions, and necessarily so in the interest of being able to
unify the different implementations.


From viresh.linux at gmail.com  Wed Mar 21 20:45:45 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Thu, 22 Mar 2012 06:15:45 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203211826.38993.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <CAOh2x==J4qkp29w+v=GWORBua-DE3yb0MRGOtBLyELxbGZwcuA@mail.gmail.com>
 <201203211404.35847.arnd@arndb.de>
 <201203211826.38993.arnd@arndb.de>
Message-ID: <CAOh2x=nZUobbRJo7kdAwmEG+s51BabxPwUVz=S3oNJyTpuRpCQ@mail.gmail.com>

On Wed, Mar 21, 2012 at 11:56 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> I just noticed that you have git trees on http://git.stlinux.com/,
> which I would personally prefer you to use actually. git.kernel.org
> is most useful for people that don't have their own git servers.

Ah, that's even better for me too. I don't really have to manage
two trees.

Just to understand the flow, how does this work now?
There can be two sources of patches:
- From ST internal developers
- From external developers

Should i apply them all to my tree and then send you a pull request?
Or you automatically pull everyday from some specific branch?

Sorry i am new to this. :(

--
viresh


From hartleys at visionengravers.com  Wed Mar 21 20:47:52 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 21 Mar 2012 19:47:52 -0500
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <20120321193231.GA3740@mwesterb-mobl.ger.corp.intel.com>
References: <4F683B36.8090101@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>
 <20120321193231.GA3740@mwesterb-mobl.ger.corp.intel.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020696D48AB1@AUSP01VMBX24.collaborationhost.net>

On Wednesday, March 21, 2012 12:33 PM, Mika Westerberg wrote:
> On Wed, Mar 21, 2012 at 12:12:11PM -0500, H Hartley Sweeten wrote:
>> On Tuesday, March 20, 2012 1:09 AM, Rafal Prylowski wrote:
>>>
>>> Implement double buffering for M2M DMA channels.
>>>
>>> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
>> 
>> Hmm... This isn't working on my ep9307 board...
>> 
>> When the system boots I get stormed with messages:
>> 
>> dma dma1chan0: unknown interrupt!
>> dma dma1chan0: unknown interrupt!
>> dma dma1chan0: unknown interrupt!
>> dma dma1chan1: unknown interrupt!
>> dma dma1chan1: unknown interrupt!
>> dma dma1chan1: unknown interrupt!
>> dma dma1chan0: unknown interrupt!
>> dma dma1chan0: unknown interrupt!
>> dma dma1chan1: unknown interrupt!
>> 
>> Note, I have use_dma set for the ep93xx_spi driver and am using mmc_spi.
>> 
>> Also note, without your patch I also get a couple messages:
>> 
>> dma dma1chan1: got interrupt while active list is empty
>> 
>> But, the mmc card is working fine. I haven't tracked down why I get these
>> yet. Mika, any ideas?
>
> I've noticed the same. But they also happen without this patch applied. I've
> tracked it down to MULTI_IRQ_HANDLER support patches for ARM vic but not sure
> what might be wrong there (or is the ep93xx_dma driver behaving badly). I
> Noticed that when we get that 'got interrupt while active list is empty' we
> don't have any interrupts set in the M2M_INTERRUPT register but we still got
> an interrupt.. weird.

I think you misunderstood my comment above.

With this patch applied I get the "unknown interrupt!" storm. These messages
keep getting spewed until I power off the board.

Without this patch I get the "got interrupt while active list is empty" messages
but only occasionally. Other than the messages the mmc_spi driver seems to
be working ok with dma.

I hacked in a dump of the DMA Global Interrupt register when I get the
"got interrupt while active list is empty" messages and get this:

dma dma1chan1: got interrupt while active list is empty (00000000)

So, according to the DMAGlInt register, there are no channels with an
active interrupt.

Are we missing a write to the INTERRUPT registers somewhere to clear the
current interrupt?

Regards,
Hartley

> Below is a workaround I've been using lately but it certainly is a hack and we
> should figure out what is the root cause for this.
>
> diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
> index dcb004a..cb6b49a 100644
> --- a/arch/arm/common/vic.c
> +++ b/arch/arm/common/vic.c
> @@ -441,11 +441,9 @@ static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
>  	u32 stat, irq;
>  	int handled = 0;
>  
> -	stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
> -	while (stat) {
> +	while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
>  		irq = ffs(stat) - 1;
>  		handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
> -		stat &= ~(1 << irq);
>  		handled = 1;
>  	}
 


From rmallon at gmail.com  Wed Mar 21 20:57:17 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Thu, 22 Mar 2012 11:57:17 +1100
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <4F683B36.8090101@metasoft.pl>
References: <4F683B36.8090101@metasoft.pl>
Message-ID: <4F6A78ED.3050403@gmail.com>

On 20/03/12 19:09, Rafal Prylowski wrote:

> Implement double buffering for M2M DMA channels.
> 


I haven't looked through the patch yet, since I'm waiting on more
information from Mika and Hartley's testing.

However, the commit log doesn't tell me why we want this change. Is it a
performance improvement? If so, do you have some numbers that we can
paste into the commit log?

Thanks,
~Ryan

> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
> 
> Index: slave-dma/drivers/dma/ep93xx_dma.c
> ===================================================================
> --- slave-dma.orig/drivers/dma/ep93xx_dma.c
> +++ slave-dma/drivers/dma/ep93xx_dma.c
> @@ -69,6 +69,7 @@
>  #define M2M_CONTROL_TM_SHIFT		13
>  #define M2M_CONTROL_TM_TX		(1 << M2M_CONTROL_TM_SHIFT)
>  #define M2M_CONTROL_TM_RX		(2 << M2M_CONTROL_TM_SHIFT)
> +#define M2M_CONTROL_NFBINT		BIT(21)
>  #define M2M_CONTROL_RSS_SHIFT		22
>  #define M2M_CONTROL_RSS_SSPRX		(1 << M2M_CONTROL_RSS_SHIFT)
>  #define M2M_CONTROL_RSS_SSPTX		(2 << M2M_CONTROL_RSS_SHIFT)
> @@ -77,7 +78,23 @@
>  #define M2M_CONTROL_PWSC_SHIFT		25
>  
>  #define M2M_INTERRUPT			0x0004
> -#define M2M_INTERRUPT_DONEINT		BIT(1)
> +#define M2M_INTERRUPT_MASK		6
> +
> +#define M2M_STATUS			0x000c
> +#define M2M_STATUS_CTL_SHIFT		1
> +#define M2M_STATUS_CTL_IDLE		(0 << M2M_STATUS_CTL_SHIFT)
> +#define M2M_STATUS_CTL_STALL		(1 << M2M_STATUS_CTL_SHIFT)
> +#define M2M_STATUS_CTL_MEMRD		(2 << M2M_STATUS_CTL_SHIFT)
> +#define M2M_STATUS_CTL_MEMWR		(3 << M2M_STATUS_CTL_SHIFT)
> +#define M2M_STATUS_CTL_BWCWAIT		(4 << M2M_STATUS_CTL_SHIFT)
> +#define M2M_STATUS_CTL_MASK		(7 << M2M_STATUS_CTL_SHIFT)
> +#define M2M_STATUS_BUF_SHIFT		4
> +#define M2M_STATUS_BUF_NO		(0 << M2M_STATUS_BUF_SHIFT)
> +#define M2M_STATUS_BUF_ON		(1 << M2M_STATUS_BUF_SHIFT)
> +#define M2M_STATUS_BUF_NEXT		(2 << M2M_STATUS_BUF_SHIFT)
> +#define M2M_STATUS_BUF_MASK		(3 << M2M_STATUS_BUF_SHIFT)
> +#define M2M_STATUS_DONE			BIT(6)
> +
>  
>  #define M2M_BCR0			0x0010
>  #define M2M_BCR1			0x0014
> @@ -426,15 +443,6 @@ static int m2p_hw_interrupt(struct ep93x
>  
>  /*
>   * M2M DMA implementation
> - *
> - * For the M2M transfers we don't use NFB at all. This is because it simply
> - * doesn't work well with memcpy transfers. When you submit both buffers it is
> - * extremely unlikely that you get an NFB interrupt, but it instead reports
> - * DONE interrupt and both buffers are already transferred which means that we
> - * weren't able to update the next buffer.
> - *
> - * So for now we "simulate" NFB by just submitting buffer after buffer
> - * without double buffering.
>   */
>  
>  static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
> @@ -543,6 +551,11 @@ static void m2m_hw_submit(struct ep93xx_
>  	m2m_fill_desc(edmac);
>  	control |= M2M_CONTROL_DONEINT;
>  
> +	if (ep93xx_dma_advance_active(edmac)) {
> +		m2m_fill_desc(edmac);
> +		control |= M2M_CONTROL_NFBINT;
> +	}
> +
>  	/*
>  	 * Now we can finally enable the channel. For M2M channel this must be
>  	 * done _after_ the BCRx registers are programmed.
> @@ -560,32 +573,85 @@ static void m2m_hw_submit(struct ep93xx_
>  	}
>  }
>  
> +/*
> + * According to EP93xx User's Guide, we should receive DONE interrupt when all
> + * M2M DMA controller transactions complete normally. This is not always the
> + * case - sometimes EP93xx M2M DMA asserts DONE interrupt when the DMA channel
> + * is still running (channel Buffer FSM in DMA_BUF_ON state, and channel
> + * Control FSM in DMA_MEM_RD state, observed at least in IDE-DMA operation).
> + * In effect, disabling the channel when only DONE bit is set could stop
> + * currently running DMA transfer. To avoid this, we use Buffer FSM and
> + * Control FSM to check current state of DMA channel.
> + */
>  static int m2m_hw_interrupt(struct ep93xx_dma_chan *edmac)
>  {
> +	u32 status = readl(edmac->regs + M2M_STATUS);
> +	u32 ctl_fsm = status & M2M_STATUS_CTL_MASK;
> +	u32 buf_fsm = status & M2M_STATUS_BUF_MASK;
> +	bool done = status & M2M_STATUS_DONE;
> +	bool last;
>  	u32 control;
>  
> -	if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_DONEINT))
> +	/* Accept only DONE and NFB interrupts */
> +	if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_MASK))
>  		return INTERRUPT_UNKNOWN;
>  
> -	/* Clear the DONE bit */
> -	writel(0, edmac->regs + M2M_INTERRUPT);
> +	if (done)
> +		/* Clear the DONE bit */
> +		writel(0, edmac->regs + M2M_INTERRUPT);
>  
> -	/* Disable interrupts and the channel */
> -	control = readl(edmac->regs + M2M_CONTROL);
> -	control &= ~(M2M_CONTROL_DONEINT | M2M_CONTROL_ENABLE);
> -	writel(control, edmac->regs + M2M_CONTROL);
> +	/*
> +	 * Check whether we are done with descriptors or not. This, together
> +	 * with DMA channel state, determines action to take in interrupt.
> +	 */
> +	last = list_first_entry(edmac->active.next,
> +		struct ep93xx_dma_desc, node)->txd.cookie;
>  
>  	/*
> -	 * Since we only get DONE interrupt we have to find out ourselves
> -	 * whether there still is something to process. So we try to advance
> -	 * the chain an see whether it succeeds.
> +	 * Use M2M DMA Buffer FSM and Control FSM to check current state of
> +	 * DMA channel. Using DONE and NFB bits from channel status register
> +	 * or bits from channel interrupt register was proven not to be
> +	 * reliable.
>  	 */
> -	if (ep93xx_dma_advance_active(edmac)) {
> -		edmac->edma->hw_submit(edmac);
> +	if (!last &&
> +	    (buf_fsm == M2M_STATUS_BUF_NO ||
> +	     buf_fsm == M2M_STATUS_BUF_ON)) {
> +		/*
> +		 * Two buffers are ready for update when Buffer FSM is in
> +		 * DMA_NO_BUF state. Only one buffer can be prepared without
> +		 * disabling the channel, or polling the DONE bit.
> +		 * To simplify things, always prepare only one buffer.
> +		 */
> +		ep93xx_dma_advance_active(edmac);
> +		m2m_fill_desc(edmac);
> +		if (done && !edmac->chan.private) {
> +			/* Software trigger for memcpy channel */
> +			control = readl(edmac->regs + M2M_CONTROL);
> +			control |= M2M_CONTROL_START;
> +			writel(control, edmac->regs + M2M_CONTROL);
> +		}
>  		return INTERRUPT_NEXT_BUFFER;
>  	}
>  
> -	return INTERRUPT_DONE;
> +	/*
> +	 * Disable the channel only when Buffer FSM is in DMA_NO_BUF state
> +	 * and Control FSM is in DMA_STALL state.
> +	 */
> +	if (last &&
> +	    buf_fsm == M2M_STATUS_BUF_NO &&
> +	    ctl_fsm == M2M_STATUS_CTL_STALL) {
> +		/* Disable interrupts and the channel */
> +		control = readl(edmac->regs + M2M_CONTROL);
> +		control &= ~(M2M_CONTROL_DONEINT | M2M_CONTROL_NFBINT
> +			    | M2M_CONTROL_ENABLE);
> +		writel(control, edmac->regs + M2M_CONTROL);
> +		return INTERRUPT_DONE;
> +	}
> +
> +	/*
> +	 * Nothing to do this time.
> +	 */
> +	return INTERRUPT_NEXT_BUFFER;
>  }
>  
>  /*




From viresh.linux at gmail.com  Wed Mar 21 21:04:37 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Thu, 22 Mar 2012 06:34:37 +0530
Subject: [PATCH] serial: PL011: move interrupt clearing
In-Reply-To: <1332357318-8017-1-git-send-email-linus.walleij@linaro.org>
References: <1332357318-8017-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <CAOh2x==5QHEcA3h216p8rJukx0LR=cVcGYN84aqzw=fnhu8Y-g@mail.gmail.com>

On Thu, Mar 22, 2012 at 12:45 AM, Linus Walleij
<linus.walleij at linaro.org> wrote:
> Commit 360f748b204275229f8398cb2f9f53955db1503b
> "serial: PL011: clear pending interrupts"
> attempts to clear interrupts by writing to a
> yet-unassigned memory address. This fixes the issue.
>
> The breaking patch is marked for stable so should be
> carried along with the other patch.
>
> Cc: Shreshtha Kumar Sahu <shreshthakumar.sahu at stericsson.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: stable <stable at vger.kernel.org>
> Reported-by: Viresh Kumar <viresh.kumar at st.com>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
> ?drivers/tty/serial/amba-pl011.c | ? ?8 ++++----
> ?1 files changed, 4 insertions(+), 4 deletions(-)

You missed me in CC??

>
> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
> index 7e01399..4ed35c5 100644
> --- a/drivers/tty/serial/amba-pl011.c
> +++ b/drivers/tty/serial/amba-pl011.c
> @@ -1930,10 +1930,6 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
> ? ? ? ? ? ? ? ?goto unmap;
> ? ? ? ?}
>
> - ? ? ? /* Ensure interrupts from this UART are masked and cleared */
> - ? ? ? writew(0, uap->port.membase + UART011_IMSC);
> - ? ? ? writew(0xffff, uap->port.membase + UART011_ICR);
> -
> ? ? ? ?uap->vendor = vendor;
> ? ? ? ?uap->lcrh_rx = vendor->lcrh_rx;
> ? ? ? ?uap->lcrh_tx = vendor->lcrh_tx;
> @@ -1951,6 +1947,10 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
> ? ? ? ?uap->port.line = i;
> ? ? ? ?pl011_dma_probe(uap);
>
> + ? ? ? /* Ensure interrupts from this UART are masked and cleared */
> + ? ? ? writew(0, uap->port.membase + UART011_IMSC);
> + ? ? ? writew(0xffff, uap->port.membase + UART011_ICR);
> +
> ? ? ? ?snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
>
> ? ? ? ?amba_ports[i] = uap;

Reviewed-by: Viresh Kumar <viresh.kumar at st.com>

--
viresh


From tom.leiming at gmail.com  Wed Mar 21 21:23:37 2012
From: tom.leiming at gmail.com (Ming Lei)
Date: Thu, 22 Mar 2012 09:23:37 +0800
Subject: [PATCH] ARM: OMAP3+: fix oops triggered in
 omap_prcm_register_chain_handler(v1)
Message-ID: <1332379417-7408-1-git-send-email-tom.leiming@gmail.com>

This patch fixes the oops below[1].

Obviously, the count of "struct irq_chip_generic" instances to be
allocated and setup should be irq_setup->nr_regs instead of
irq_setup->nr_regs plus one, so just fix the iterator to avoid
the oops. 

[1], oops log.

[    1.790242] Unable to handle kernel NULL pointer dereference at virtual address 00000004
[    1.798632] pgd = c0004000
[    1.801638] [00000004] *pgd=00000000
[    1.805400] Internal error: Oops: 805 [#1] PREEMPT SMP THUMB2
[    1.811381] Modules linked in:
[    1.814601] CPU: 1    Not tainted  (3.3.0-next-20120320+ #733)
[    1.820683] PC is at irq_setup_generic_chip+0x6a/0x84
[    1.825951] LR is at irq_get_irq_data+0x7/0x8
[    1.830508] pc : [<c006465e>]    lr : [<c0063a03>]    psr: 20000133
[    1.830512] sp : ee04ff58  ip : 00000000  fp : 00000000
[    1.842461] r10: 00000000  r9 : 00000000  r8 : 00000800
[    1.847905] r7 : c064e260  r6 : 000001dc  r5 : 00000001  r4 : ee0accc0
[    1.854687] r3 : 00000002  r2 : 00000800  r1 : 000001dc  r0 : 00000000
[    1.861472] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA Thumb  Segment kernel
[    1.869234] Control: 50c5387d  Table: 8000404a  DAC: 00000015
[    1.875215] Process swapper/0 (pid: 1, stack limit = 0xee04e2f8)
[    1.881463] Stack: (0xee04ff58 to 0xee050000)
[    1.886017] ff40: c061b668 00000008
[    1.894497] ff60: c0682090 ee0accc0 00000003 c001c637 00000000 00000000 00000201 00000000
[    1.902976] ff80: 00000004 c0473820 c0473800 c0459e8d c0680ac0 c000866d 00000004 00000004
[    1.911455] ffa0: ee04ffa8 00000004 c047381c 00000004 c0473820 c0473800 c0680ac0 00000082
[    1.919934] ffc0: c0489694 c045265f 00000004 00000004 c0452135 c000d105 00000033 00000000
[    1.928413] ffe0: c04525b5 c000d111 00000033 00000000 00000000 c000d111 aaaaaaaa aaaaaaaa
[    1.936912] [<c006465e>] (irq_setup_generic_chip+0x6a/0x84) from [<c001c637>] (omap_prcm_register_chain_handler+0x147/0x1a0)
[    1.948516] [<c001c637>] (omap_prcm_register_chain_handler+0x147/0x1a0) from [<c000866d>] (do_one_initcall+0x65/0xf4)
[    1.959500] [<c000866d>] (do_one_initcall+0x65/0xf4) from [<c045265f>] (kernel_init+0xab/0x138)
[    1.968529] [<c045265f>] (kernel_init+0xab/0x138) from [<c000d111>] (kernel_thread_exit+0x1/0x6)
[    1.977632] Code: f7ff f9d1 6b23 1af3 (6043) 086d
[    1.982684] ---[ end trace 1b75b31a2719ed1c ]---
[    1.987526] Kernel panic - not syncing: Attempted to kill init!
exitcode=0x0000000b

Cc: Kevin Hilman <khilman at ti.com>
Acked-by: Tero Kristo <t-kristo at ti.com>
Signed-off-by: Ming Lei <tom.leiming at gmail.com>
---
v1:
	-add a bit more description to the changelog as suggested by
	Tero and Kevin.

 arch/arm/mach-omap2/prm_common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 873b51d..d28f848 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -290,7 +290,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 		goto err;
 	}
 
-	for (i = 0; i <= irq_setup->nr_regs; i++) {
+	for (i = 0; i < irq_setup->nr_regs; i++) {
 		gc = irq_alloc_generic_chip("PRCM", 1,
 			irq_setup->base_irq + i * 32, prm_base,
 			handle_level_irq);
-- 
1.7.9.1



From tom.leiming at gmail.com  Wed Mar 21 21:25:26 2012
From: tom.leiming at gmail.com (Ming Lei)
Date: Thu, 22 Mar 2012 09:25:26 +0800
Subject: [PATCH] ARM: OMAP3+: fix oops triggered in
 omap_prcm_register_chain_handler
In-Reply-To: <87r4wmrqhn.fsf@ti.com>
References: <1332305376-27038-1-git-send-email-tom.leiming@gmail.com>
 <87r4wmrqhn.fsf@ti.com>
Message-ID: <CACVXFVPAnXF2mxBoz_CrRv1o4NHbo5T2fT626m2V7Qe+YRjx3Q@mail.gmail.com>

On Wed, Mar 21, 2012 at 10:13 PM, Kevin Hilman <khilman at ti.com> wrote:
> Ming Lei <tom.leiming at gmail.com> writes:
>
>> This patch fixes the oos below:
>
> As Tero mentioned, please add a bit more description to the changelog
> about why the iterator is wrong and repost.

The revised version has been sent out.

Thanks,
-- 
Ming Lei


From tarun.kanti at ti.com  Wed Mar 21 22:10:00 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Thu, 22 Mar 2012 07:40:00 +0530
Subject: [PATCH v4 RESEND 6/7] gpio/omap: fix incorrect update to
 context.irqenable1
In-Reply-To: <87y5qurqu1.fsf@ti.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
 <1332240799-6748-7-git-send-email-tarun.kanti@ti.com>
 <87zkbbywwz.fsf@ti.com>
 <CAC83ZvKRbvVU5Qa1jwud0E6WT-DBU1Z1XEweiXay9x+eLcn0hg@mail.gmail.com>
 <CAC83ZvLgPWO2C6cpRBEsoqFdac1rMyo4OvTXB2_y_mCzaFzJXA@mail.gmail.com>
 <87y5qurqu1.fsf@ti.com>
Message-ID: <CAC83ZvJNsFmgABsGd_OPYJwNfDuKBw5iVwqrwZ48HyR05qT8tA@mail.gmail.com>

On Wed, Mar 21, 2012 at 7:36 PM, Kevin Hilman <khilman at ti.com> wrote:
> "DebBarma, Tarun Kanti" <tarun.kanti at ti.com> writes:
>
>> On Wed, Mar 21, 2012 at 8:10 AM, DebBarma, Tarun Kanti
>> <tarun.kanti at ti.com> wrote:
>>> On Tue, Mar 20, 2012 at 11:31 PM, Kevin Hilman <khilman at ti.com> wrote:
>>>> Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:
>>>>
>>>>> In _enable_gpio_irqbank() when bank->regs->set_irqenable is valid,
>>>>> gpio_mask can be directly set by writing to set_irqenable register
>>>>> without overwriting current value. In order to ensure the same is
>>>>> stored in context.irqenable1, we must read from regs->irqenable
>>>>> instead of overwriting it with gpio_mask.
>>>>
>>>>> The overwriting makes sense only in the second case where irqenable
>>>>> is explicitly read and updated with new gpio_mask before writing it
>>>>> back. However, for consistency reading regs->irqenable into the
>>>>> bank->context.irqenable1 takes care of both the scenarios.
>>>>
>>>> ...except that the code doesn't do this anymore.
>>> Yes.
>>>>
>>>> I like the newer version (I hope so, since I suggested it :), but please
>>>> update the changlog to describe what the code is actually doing.
>>> Sure.
>> I have updated the change log here:
>> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev
>> for_3.4/gpio_more_fixes
>
> Please also post and updated version of the patch for review.
Sure.
--
Tarun
>
> Kevin


From shawn.guo at linaro.org  Wed Mar 21 23:23:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 22 Mar 2012 11:23:26 +0800
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <20120320224021.GF29317@pengutronix.de>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <e22898bc8b69e85f1e6390d7d858f85c.squirrel@www.codeaurora.org>
 <20120320181441.GO3852@pengutronix.de>
 <4F68E53B.7040800@codeaurora.org>
 <20120320224021.GF29317@pengutronix.de>
Message-ID: <20120322032323.GA2213@S2101-09.ap.freescale.net>

On Tue, Mar 20, 2012 at 11:40:21PM +0100, Sascha Hauer wrote:
> On Tue, Mar 20, 2012 at 01:14:51PM -0700, Saravana Kannan wrote:
...
> > Ah, I see. That's a lot of functions calls. I think it would be much
> > more efficient if you just have an array and loop over it. With my
> > patch, you can just call a single register function for all these
> > clocks.
> 
> I was curious and gave it a try. I registered a fixed clock and 100
> gates as child clocks. I tried both DEFINE_CLK_GATE and
> clk_register_gate. It turned out there was no difference in speed.
> 
While there is no difference in speed efficiency, I think we will
gain space efficiency if we can have Saravana's patch to copy the
clk_hw fields and make the static array __initdata as you mentioned.

-- 
Regards,
Shawn


From vaibhav.bedia at ti.com  Thu Mar 22 00:23:23 2012
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Thu, 22 Mar 2012 04:23:23 +0000
Subject: Occasional crashes in suspend-resume with MMC transactions
Message-ID: <B5906170F1614E41A8A28DE3B8D12143317FDFBB@DBDE01.ent.ti.com>

Hi,

I am trying to do suspend-resume test with a file copy on MMC/SD going on
in the background. The test involves simply copying a 450MB file on an ext3
partition to the same partition under a different name.

This is on an AM335x board which uses the omap_hsmmc driver. 
The kernel is v3.2 and I have also applied the following patch 

commit 6b9dc6b5f2a1b7953e46e897eb3e91e885322ed0
Author: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
Date:   Wed Jan 4 15:28:45 2012 +0100

    mmc: fix a deadlock between system suspend and MMC block IO

    Performing MMC block IO with simultaneous STR can lead to a deadlock: the
    mmc_pm_notify() function claims the host and then calls bus .remove()
    method, which lands in mmc_blk_remove(), which calls mmc_blk_remove_req()
    then it goes to -> mmc_cleanup_queue() -> kthread_stop(), which waits for
    the mmc-block thread to stop. If the mmc-block thread at that time is
    processing block requests, it will also try to claim the host in
    mmc_blk_issue_rq() and block there. This patch fixes the problem by
    calling .remove() before claiming the host.

    Signed-off-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
    Acked-by: Arindam Nath <arindam.nath at amd.com>
    Signed-off-by: Chris Ball <cjb at laptop.org>


In some iterations the resume part gets into issues with the following dump

...
[  229.716033] PM: Syncing filesystems ... done.
[  281.389129] Freezing user space processes ... (elapsed 0.95 seconds) done.
[  282.357757] Freezing remaining freezable tasks ... (elapsed 4.36 seconds) done.
[  286.764099] PM: suspend of devices complete after 29.815 msecs
[  286.765777] PM: late suspend of devices complete after 1.647 msecs

( resume using a uart keystroke)
[  290.121765] GFX domain entered low power stat
[  290.123748] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa06022c
[  290.123809] Internal error: : 1028 [#1]
[  290.123840] Modules linked in:
[  290.123870] CPU: 0    Not tainted  (3.2.0-12280-g6b9dc6b-dirty #12)
[  290.123931] PC is at omap_hsmmc_request+0xcc/0x4d8
[  290.123962] LR is at mmc_start_request+0x110/0x20c
[  290.123992] pc : [<c030baec>]    lr : [<c02fbff8>]    psr: a0000113
[  290.124023] sp : cf373e58  ip : cf373ea0  fp : cf373e9c
[  290.124053] r10: 00000000  r9 : ce55e218  r8 : cfa6202c
[  290.124053] r7 : cfa620dc  r6 : cf3b6000  r5 : cfa6202c  r4 : cf3b6280
[  290.124084] r3 : fa060100  r2 : fa060100  r1 : 00000080  r0 : cf3b6000
[  290.124145] Flags: NzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
[  290.124176] Control: 10c5387d  Table: 8edf4019  DAC: 00000015
[  290.124206] Process mmcqd/0 (pid: 666, stack limit = 0xcf3722f0)
[  290.124237] Stack: (0xcf373e58 to 0xcf374000)
[  290.124237] 3e40:                                                       cf373e9c cf373e68
[  290.124298] 3e60: c001991c c01c7898 cf362c40 00000001 00002000 cfa6202c cf3b6000 c0616550
[  290.124359] 3e80: cfa620dc cfa6202c ce55e218 00000000 cf373ed4 cf373ea0 c02fbff8 c030ba2c
[  290.124389] 3ea0: 00000001 00000000 cfa6202c 00000000 cf373ed4 cf3b6000 cfa6211c 00000000
[  290.124420] 3ec0: cf373f14 cfa6202c cf373efc cf373ed8 c02fce8c c02fbef4 00000000 cfa62400
[  290.124481] 3ee0: cfa62004 cf372000 cfa62400 cfa62000 cf373f44 cf373f00 c03089fc c02fcd88
[  290.124542] 3f00: cf373f54 00000000 cfa6223c c312e8d8 00100100 00200200 c02fc47c cfa62400
[  290.124572] 3f20: cfa62004 cf372000 cfa62000 c312e8d8 ce55e218 cfa62000 cf373f8c cf373f48
[  290.124633] 3f40: c0308e5c c0308998 00000000 c312e8d8 cf373f74 cf373f60 c01ab760 c01af878
[  290.124664] 3f60: c312e8d8 cfa62004 00000000 cf372000 00000001 cf3a8ae8 ce55e218 cfa6200c
[  290.124725] 3f80: cf373fbc cf373f90 c03095f8 c0308cd0 00000000 cf835cb0 cfa62004 c030959c
[  290.124755] 3fa0: 00000013 00000000 00000000 00000000 cf373ff4 cf373fc0 c0055a30 c03095a8
[  290.124786] 3fc0: cf835cb0 00000000 cfa62004 00000000 cf373fd0 cf373fd0 00000000 cf835cb0
[  290.124847] 3fe0: c00559a0 c004018c 00000000 cf373ff8 c004018c c00559ac f52322cc f291067e
[  290.124877] Backtrace:
[  290.124938] [<c030ba20>] (omap_hsmmc_request+0x0/0x4d8) from [<c02fbff8>] (mmc_start_request+0x110/0x20c)
[  290.125000] [<c02fbee8>] (mmc_start_request+0x0/0x20c) from [<c02fce8c>] (mmc_start_req+0x110/0x160)
[  290.125030]  r8:cfa6202c r7:cf373f14 r6:00000000 r5:cfa6211c r4:cf3b6000
[  290.125091] [<c02fcd7c>] (mmc_start_req+0x0/0x160) from [<c03089fc>] (mmc_blk_issue_rw_rq+0x70/0x338)
[  290.125122]  r8:cfa62000 r7:cfa62400 r6:cf372000 r5:cfa62004 r4:cfa62400
[  290.125183] r3:00000000
[  290.125213] [<c030898c>] (mmc_blk_issue_rw_rq+0x0/0x338) from [<c0308e5c>] (mmc_blk_issue_rq+0x198/0x460)
[  290.125274] [<c0308cc4>] (mmc_blk_issue_rq+0x0/0x460) from [<c03095f8>] (mmc_queue_thread+0x5c/0xf0)
[  290.125335] [<c030959c>] (mmc_queue_thread+0x0/0xf0) from [<c0055a30>] (kthread+0x90/0x94)
[  290.125396] [<c00559a0>] (kthread+0x0/0x94) from [<c004018c>] (do_exit+0x0/0x67c)
[  290.125427]  r6:c004018c r5:c00559a0 r4:cf835cb0
[  290.125457] Code: e5933008 e1833801 e5823104 e5943034 (e593212c)
[  290.125488] ---[ end trace 82f48b7910402960 ]---
[  290.329986] PM: early resume of devices complete after 207.732 msecs
[  290.465484] CPSW phy found : id is : 0x4dd074
[  290.467193] PHY 0:01 not found
[  290.469512] PM: resume of devices complete after 139.156 msecs
[  290.921264] Successfully transitioned all domains to low power state
[  290.928375] PM: Finishing wakeup.
[  290.932250] Restarting tasks ... 
[  290.960052] done.
[  293.461608] PHY: 0:00 - Link is Up - 100/Full

Whenever this happens, the file copy doesn't continue after resume.

A snapshot of the blocked tasks gives the following info

root at arago-armv7:/media/mmcblk0p3# echo w > /proc/sysrq-trigger
[  364.364807] SysRq : Show Blocked State
[  364.368743]   task                PC stack   pid father
[  364.374206] kworker/u:0     D c0411548     0     5      2 0x00000000
[  364.380859] Backtrace:
[  364.383422] [<c0411388>] (__schedule+0x0/0x394) from [<c0411810>] (schedule+0x50/0x68)
[  364.391693] [<c04117c0>] (schedule+0x0/0x68) from [<c02fc604>] (__mmc_claim_host+0x138/0x144)
[  364.400604] [<c02fc4cc>] (__mmc_claim_host+0x0/0x144) from [<c030184c>] (mmc_sd_detect+0x28/0x80)
[  364.409881] [<c0301824>] (mmc_sd_detect+0x0/0x80) from [<c02fdff0>] (mmc_rescan+0x120/0x250)
[  364.418670]  r5:cf8d2e00 r4:cf3b6000
[  364.422424] [<c02fded0>] (mmc_rescan+0x0/0x250) from [<c004fba0>] (process_one_work+0x124/0x384)
[  364.431579]  r6:cf834000 r5:cf8d2e00 r4:cf817f00 r3:60000013
[  364.437500] [<c004fa7c>] (process_one_work+0x0/0x384) from [<c0051a18>] (worker_thread+0x15c/0x330)
[  364.446960] [<c00518bc>] (worker_thread+0x0/0x330) from [<c0055a30>] (kthread+0x90/0x94)
[  364.455413] [<c00559a0>] (kthread+0x0/0x94) from [<c004018c>] (do_exit+0x0/0x67c)
[  364.463226]  r6:c004018c r5:c00559a0 r4:cf81dee0
[  364.468078] kjournald       D c0411548     0  1747      2 0x00000000
[  364.474700] Backtrace:
[  364.477264] [<c0411388>] (__schedule+0x0/0x394) from [<c0411810>] (schedule+0x50/0x68)
[  364.485534] [<c04117c0>] (schedule+0x0/0x68) from [<c0411890>] (io_schedule+0x68/0x90)
[  364.493804] [<c0411828>] (io_schedule+0x0/0x90) from [<c01aabc4>] (get_request_wait+0xcc/0x170)
[  364.502868]  r6:cf3a8ae8 r5:cfb53d9c r4:cfb53da8 r3:cede3c00
[  364.508789] [<c01aaaf8>] (get_request_wait+0x0/0x170) from [<c01abde8>] (blk_queue_bio+0x4c/0x298)
[  364.518157] [<c01abd9c>] (blk_queue_bio+0x0/0x298) from [<c01a9c64>] (generic_make_request+0xb4/0xd4)
[  364.527770] [<c01a9bb0>] (generic_make_request+0x0/0xd4) from [<c01a9d08>] (submit_bio+0x84/0xf8)
[  364.537017]  r6:00000211 r5:00000008 r4:c3538240
[  364.541870] [<c01a9c84>] (submit_bio+0x0/0xf8) from [<c00cd198>] (submit_bh+0x13c/0x16c)
[  364.550323] [<c00cd05c>] (submit_bh+0x0/0x16c) from [<c011ecb0>] (journal_do_submit_data.clone.23+0x3c/0x48)
[  364.560577]  r7:00000200 r6:c00d0c68 r5:cee2ee80 r4:000001a0
[  364.566497] [<c011ec74>] (journal_do_submit_data.clone.23+0x0/0x48) from [<c011fab0>] (journal_commit_transaction+0xdf4/0xf1c)
[  364.578369]  r7:c600cec0 r6:00000200 r5:c600ce88 r4:cec053c0
[  364.584289] [<c011ecbc>] (journal_commit_transaction+0x0/0xf1c) from [<c0121e54>] (kjournald+0xc4/0x1d8)
[  364.594207] [<c0121d90>] (kjournald+0x0/0x1d8) from [<c0055a30>] (kthread+0x90/0x94)
[  364.602264] [<c00559a0>] (kthread+0x0/0x94) from [<c004018c>] (do_exit+0x0/0x67c)
[  364.610076]  r6:c004018c r5:c00559a0 r4:cedfbcd8
[  364.614929] cp              D c0411548     0  1915   1877 0x00000000
[  364.621551] Backtrace:
[  364.624114] [<c0411388>] (__schedule+0x0/0x394) from [<c0411810>] (schedule+0x50/0x68)
[  364.632354] [<c04117c0>] (schedule+0x0/0x68) from [<c0411890>] (io_schedule+0x68/0x90)
[  364.640625] [<c0411828>] (io_schedule+0x0/0x90) from [<c01aabc4>] (get_request_wait+0xcc/0x170)
[  364.649719]  r6:cf3a8ae8 r5:c17aba84 r4:c17aba90 r3:cede2600
[  364.655639] [<c01aaaf8>] (get_request_wait+0x0/0x170) from [<c01abde8>] (blk_queue_bio+0x4c/0x298)
[  364.664978] [<c01abd9c>] (blk_queue_bio+0x0/0x298) from [<c01a9c64>] (generic_make_request+0xb4/0xd4)
[  364.674591] [<c01a9bb0>] (generic_make_request+0x0/0xd4) from [<c01a9d08>] (submit_bio+0x84/0xf8)
[  364.683868]  r6:00000001 r5:00000080 r4:cfac3a40
[  364.688690] [<c01a9c84>] (submit_bio+0x0/0xf8) from [<c00d9870>] (do_mpage_readpage+0x468/0x774)
[  364.697845] [<c00d9408>] (do_mpage_readpage+0x0/0x774) from [<c00d9cec>] (mpage_readpages+0xec/0x148)
[  364.707489] [<c00d9c00>] (mpage_readpages+0x0/0x148) from [<c01060a0>] (ext3_readpages+0x24/0x28)
[  364.716766] [<c010607c>] (ext3_readpages+0x0/0x28) from [<c0083448>] (__do_page_cache_readahead+0x198/0x27c)
[  364.727020] [<c00832b0>] (__do_page_cache_readahead+0x0/0x27c) from [<c00837f8>] (ra_submit+0x28/0x30)
[  364.736724] [<c00837d0>] (ra_submit+0x0/0x30) from [<c0083908>] (ondemand_readahead+0x108/0x1e8)
[  364.745910] [<c0083800>] (ondemand_readahead+0x0/0x1e8) from [<c0083ae0>] (page_cache_sync_readahead+0x4c/0x68)
[  364.756439] [<c0083a94>] (page_cache_sync_readahead+0x0/0x68) from [<c007be18>] (generic_file_aio_read+0x42c/0x770)
[  364.767333]  r5:cf576888 r4:00000000
[  364.771057] [<c007b9ec>] (generic_file_aio_read+0x0/0x770) from [<c00a7694>] (do_sync_read+0xac/0xec)
[  364.780700] [<c00a75e8>] (do_sync_read+0x0/0xec) from [<c00a7e20>] (vfs_read+0xb8/0x14c)
[  364.789123]  r8:00001000 r7:c17abf70 r6:bea1da58 r5:00001000 r4:ced3a740
[  364.796142] [<c00a7d68>] (vfs_read+0x0/0x14c) from [<c00a7ef8>] (sys_read+0x44/0x74)
[  364.804229]  r8:00001000 r7:bea1da58 r6:ced3a740 r5:00000000 r4:09adc000
[  364.811248] [<c00a7eb4>] (sys_read+0x0/0x74) from [<c0014200>] (ret_fast_syscall+0x0/0x30)
[  364.819854]  r8:c00143a8 r7:00000003 r6:bea1da58 r5:00000003 r4:00001000

Debugging a bit further I found that runtime resume of hsmmc does not take place in the
failed iterations. Since this doesn't happen in every iteration I would hazard a guess
that there's some sort of race condition between the MMC core resuming and the 
pm_runtime_get_sync() call.

Any pointers on what could be going wrong here and how to debug this further.

Regards,
Vaibhav


From tarun.kanti at ti.com  Thu Mar 22 01:12:09 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Thu, 22 Mar 2012 10:42:09 +0530
Subject: [PATCH v4 RESEND 6/7] gpio/omap: fix incorrect update to
 context.irqenable1
Message-ID: <1332393130-10636-1-git-send-email-tarun.kanti@ti.com>

In _enable_gpio_irqbank() when bank->regs->set_irqenable is TRUE,
gpio_mask can be directly set by writing to set_irqenable register
without overwriting current value. In order to ensure the same is
stored in context.irqenable1, we must avoid overwriting it with
gpio_mask at the end of the function. Instead, update irqenable1
appropriately by OR'ing with gpio_mask.
For the case where bank->regs->set_irqenable is FALSE, irqenable1
can be directly overwritten with 'l' which holds correct computed
value.

        if (bank->regs->set_irqenable) {
                reg += bank->regs->set_irqenable;
                l = gpio_mask;
        } else {
                reg += bank->regs->irqenable;
                l = __raw_readl(reg);
                if (bank->regs->irqenable_inv)
                        l &= ~gpio_mask;
                else
                        l |= gpio_mask;
        }

Make similar change for _disable_gpio_irqbank().

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
Updated change log as per Kevin's suggestion.

 drivers/gpio/gpio-omap.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index bcb1061..6c17e58 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -451,6 +451,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 	if (bank->regs->set_irqenable) {
 		reg += bank->regs->set_irqenable;
 		l = gpio_mask;
+		bank->context.irqenable1 |= gpio_mask;
 	} else {
 		reg += bank->regs->irqenable;
 		l = __raw_readl(reg);
@@ -458,10 +459,10 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 			l &= ~gpio_mask;
 		else
 			l |= gpio_mask;
+		bank->context.irqenable1 = l;
 	}
 
 	__raw_writel(l, reg);
-	bank->context.irqenable1 = l;
 }
 
 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
@@ -472,6 +473,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 	if (bank->regs->clr_irqenable) {
 		reg += bank->regs->clr_irqenable;
 		l = gpio_mask;
+		bank->context.irqenable1 &= ~gpio_mask;
 	} else {
 		reg += bank->regs->irqenable;
 		l = __raw_readl(reg);
@@ -479,10 +481,10 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 			l |= gpio_mask;
 		else
 			l &= ~gpio_mask;
+		bank->context.irqenable1 = l;
 	}
 
 	__raw_writel(l, reg);
-	bank->context.irqenable1 = l;
 }
 
 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
-- 
1.7.0.4



From paul.gortmaker at windriver.com  Thu Mar 22 01:18:40 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Thu, 22 Mar 2012 01:18:40 -0400
Subject: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h
In-Reply-To: <4F6990AF.2000004@atmel.com>
References: <1332296128-16262-1-git-send-email-paul.gortmaker@windriver.com>
 <20120321072632.GA15703@samfundet.no> <4F6990AF.2000004@atmel.com>
Message-ID: <20120322051840.GC923@windriver.com>

[Re: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h] On 21/03/2012 (Wed 09:26) Nicolas Ferre wrote:

> On 03/21/2012 08:26 AM, Hans-Christian Egtvedt :
> > Around Tue 20 Mar 2012 22:15:28 -0400 or thereabout, Paul Gortmaker wrote:
> >> Commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c (linux-next)
> >>
> >>     "ATMEL: fix nand ecc support"
> >>
> >> indicated that it wanted to "Move platform data to a common
> >> header include/linux/platform_data/atmel_nand.h" and the new
> >> header even had re-include protectors with:
> >>
> >>     #ifndef __ATMEL_NAND_H__
> >>
> >> However, the file that was added was simply called atmel.h
> >> and this caused avr32 defconfig to fail with:
> >>
> >>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
> >>   arch/avr32/mach-at32ap/include/mach/board.h:10:44: error: linux/platform_data/atmel_nand.h: No such file or directory
> >>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
> >>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: 'struct atmel_nand_data' declared inside parameter list
> >>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: its scope is only this definition or declaration, which is probably not what you want
> >>   make[2]: *** [arch/avr32/boards/atstk1000/setup.o] Error 1
> >>
> >> Rename the file to match the original intention, and fix up the
> >> users who reference the bad name without the _nand suffix.
> > 
> > Thanks fixing this.
> 
> 
> Yes, we need to fix this. But I would not like to see this
> "platform_data/atmel.h" renamed: I think that this file was designed to
> collect several common platform data (ie: not just NAND related).
> 
> So maybe we should just rename the entry that exists in
> mach-at32ap/include/mach/board.h
> and remove all occurrences of platform_data/atmel_nand.h

Funny, since this is what I did 1st before I re-read the original commit
log in more detail. :)  Oh well.  Here is the alternate solution.  You
guys can pick whichever one you like best.  I compile tested this one
as well.

Thanks,
Paul.
---

>From 73c01b7ed8fd2732661fa1ca726c48096f4651f2 Mon Sep 17 00:00:00 2001
From: Paul Gortmaker <paul.gortmaker at windriver.com>
Date: Tue, 20 Mar 2012 21:55:46 -0400
Subject: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h

Commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c (linux-next)

    "ATMEL: fix nand ecc support"

indicated that it wanted to "Move platform data to a common
header include/linux/platform_data/atmel_nand.h" and the new
header even had re-include protectors with:

    #ifndef __ATMEL_NAND_H__

However, the file that was added was simply called atmel.h
and this caused avr32 defconfig to fail with:

  In file included from arch/avr32/boards/atstk1000/setup.c:22:
  arch/avr32/mach-at32ap/include/mach/board.h:10:44: error: linux/platform_data/atmel_nand.h: No such file or directory
  In file included from arch/avr32/boards/atstk1000/setup.c:22:
  arch/avr32/mach-at32ap/include/mach/board.h:121: warning: 'struct atmel_nand_data' declared inside parameter list
  arch/avr32/mach-at32ap/include/mach/board.h:121: warning: its scope is only this definition or declaration, which is probably not what you want
  make[2]: *** [arch/avr32/boards/atstk1000/setup.o] Error 1

It seems the scope of the file contents will expand beyond
just nand, so ignore the original intention, and fix up the
users who reference the bad name with the _nand suffix.

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
CC: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
CC: Hans-Christian Egtvedt <egtvedt at samfundet.no>
CC: David Woodhouse <dwmw2 at infradead.org>

diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
index 7173386..70742ec 100644
--- a/arch/avr32/mach-at32ap/include/mach/board.h
+++ b/arch/avr32/mach-at32ap/include/mach/board.h
@@ -7,7 +7,7 @@
 #include <linux/types.h>
 #include <linux/serial.h>
 #include <linux/platform_data/macb.h>
-#include <linux/platform_data/atmel_nand.h>
+#include <linux/platform_data/atmel.h>
 
 #define GPIO_PIN_NONE	(-1)
 
diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel.h
index d056263..b0f2c56 100644
--- a/include/linux/platform_data/atmel.h
+++ b/include/linux/platform_data/atmel.h
@@ -4,8 +4,8 @@
  * GPL v2 Only
  */
 
-#ifndef __ATMEL_NAND_H__
-#define __ATMEL_NAND_H__
+#ifndef __ATMEL_H__
+#define __ATMEL_H__
 
 #include <linux/mtd/nand.h>
 
@@ -24,4 +24,4 @@ struct atmel_nand_data {
 	unsigned int	num_parts;
 };
 
-#endif /* __ATMEL_NAND_H__ */
+#endif /* __ATMEL_H__ */
-- 
1.7.9.1



From lenb at kernel.org  Thu Mar 22 01:20:11 2012
From: lenb at kernel.org (Len Brown)
Date: Thu, 22 Mar 2012 01:20:11 -0400
Subject: [PATCH] ARM: davinci: Fix for cpuidle consolidation changes
In-Reply-To: <DF0F476B391FA8409C78302C7BA518B631800C76@DBDE01.ent.ti.com>
References: <1332348505-28780-1-git-send-email-rob.lee@linaro.org>
 <DF0F476B391FA8409C78302C7BA518B631800C76@DBDE01.ent.ti.com>
Message-ID: <4F6AB68B.4040605@kernel.org>

applied.

thanks,
Len Brown, Intel Open Source Technology Center


From shawn.guo at linaro.org  Thu Mar 22 01:24:51 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 22 Mar 2012 13:24:51 +0800
Subject: [PATCH v13] Regulator: Add Anatop regulator driver
In-Reply-To: <1331692152-9256-1-git-send-email-paul.liu@linaro.org>
References: <1331692152-9256-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120322052449.GB2213@S2101-09.ap.freescale.net>

On Wed, Mar 14, 2012 at 10:29:12AM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Anatop is an integrated regulator inside i.MX6 SoC.
> There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
> And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
> This patch adds the Anatop regulator driver.
> 
> Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Acked-by: Shawn Guo <shawn.guo at linaro.org>
> Reviewed-by: Axel Lin <axel.lin at gmail.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Liam Girdwood <lrg at ti.com>
> Cc: Samuel Ortiz <sameo at linux.intel.com>
> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
>  drivers/regulator/Kconfig            |    8 +
>  drivers/regulator/Makefile           |    1 +
>  drivers/regulator/anatop-regulator.c |  241 ++++++++++++++++++++++++++++++++++
>  3 files changed, 250 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/regulator/anatop-regulator.c
> 
I just noticed that the binding document below got lost since v11 of
the series.

  Documentation/devicetree/bindings/regulator/anatop-regulator.txt

It got lost by mistaken or you dropped it for some reason?

-- 
Regards,
Shawn


From kumarrav at codeaurora.org  Thu Mar 22 02:40:36 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Thu, 22 Mar 2012 12:10:36 +0530
Subject: [PATCH 1/2] dmaengine: Add context parameter to prep_dma_sg and
 prep_interleaved_dma
In-Reply-To: <1332398437-13306-1-git-send-email-kumarrav@codeaurora.org>
References: <1332398437-13306-1-git-send-email-kumarrav@codeaurora.org>
Message-ID: <1332398437-13306-2-git-send-email-kumarrav@codeaurora.org>

Add new context parameter to DMA SG and Interleaveid mode for passing
per transfer specific private data, using this it enables the
dma devices which needs to pass the parameters which changes per
each transfer

Change-Id: Ia9ee19f2c253e68b8e5ff254a57478dcc51014ca
Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
---
 drivers/dma/fsldma.c                    |    2 +-
 drivers/dma/sirf-dma.c                  |    2 +-
 drivers/dma/ste_dma40.c                 |    2 +-
 drivers/misc/carma/carma-fpga-program.c |    2 +-
 drivers/misc/carma/carma-fpga.c         |    7 ++---
 include/linux/dmaengine.h               |   45 +++++++++++++++++++++++++++++-
 6 files changed, 50 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index b98070c..f9f77db 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -645,7 +645,7 @@ fail:
 static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
 	struct scatterlist *dst_sg, unsigned int dst_nents,
 	struct scatterlist *src_sg, unsigned int src_nents,
-	unsigned long flags)
+	unsigned long flags, void *context)
 {
 	struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
 	struct fsldma_chan *chan = to_fsl_chan(dchan);
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 2333810..ff4d344 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -428,7 +428,7 @@ sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 
 static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
 	struct dma_chan *chan, struct dma_interleaved_template *xt,
-	unsigned long flags)
+	unsigned long flags, void *context)
 {
 	struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
 	struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index cc5ecbc..2f58ba9 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2287,7 +2287,7 @@ static struct dma_async_tx_descriptor *
 d40_prep_memcpy_sg(struct dma_chan *chan,
 		   struct scatterlist *dst_sg, unsigned int dst_nents,
 		   struct scatterlist *src_sg, unsigned int src_nents,
-		   unsigned long dma_flags)
+		   unsigned long dma_flags, void *context)
 {
 	if (dst_nents != src_nents)
 		return NULL;
diff --git a/drivers/misc/carma/carma-fpga-program.c b/drivers/misc/carma/carma-fpga-program.c
index a2d25e4..3739a12 100644
--- a/drivers/misc/carma/carma-fpga-program.c
+++ b/drivers/misc/carma/carma-fpga-program.c
@@ -530,7 +530,7 @@ static noinline int fpga_program_dma(struct fpga_dev *priv)
 	}
 
 	/* setup and submit the DMA transaction */
-	tx = chan->device->device_prep_dma_sg(chan,
+	tx = chan->device->dmaengine_prep_dma_sg(chan,
 					      table.sgl, num_pages,
 					      vb->sglist, vb->sglen, 0);
 	if (!tx) {
diff --git a/drivers/misc/carma/carma-fpga.c b/drivers/misc/carma/carma-fpga.c
index 14e974b2..be0baf6 100644
--- a/drivers/misc/carma/carma-fpga.c
+++ b/drivers/misc/carma/carma-fpga.c
@@ -638,10 +638,9 @@ static int data_submit_dma(struct fpga_device *priv, struct data_buf *buf)
 	 */
 
 	/* setup the scatterlist to scatterlist transfer */
-	tx = chan->device->device_prep_dma_sg(chan,
-					      dst_sg, dst_nents,
-					      src_sg, src_nents,
-					      0);
+	tx = dmaengine_prep_dma_sg(chan, dst_sg, dst_nents,
+					 src_sg, src_nents,
+					 0);
 	if (!tx) {
 		dev_err(priv->dev, "unable to prep scatterlist DMA\n");
 		return -ENOMEM;
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 679b349..61afc79 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -570,7 +570,7 @@ struct dma_device {
 		struct dma_chan *chan,
 		struct scatterlist *dst_sg, unsigned int dst_nents,
 		struct scatterlist *src_sg, unsigned int src_nents,
-		unsigned long flags);
+		unsigned long flags, void *context);
 
 	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
 		struct dma_chan *chan, struct scatterlist *sgl,
@@ -581,7 +581,7 @@ struct dma_device {
 		size_t period_len, enum dma_transfer_direction direction);
 	struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
 		struct dma_chan *chan, struct dma_interleaved_template *xt,
-		unsigned long flags);
+		unsigned long flags, void *context);
 	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		unsigned long arg);
 
@@ -615,6 +615,47 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
 	return chan->device->device_prep_slave_sg(chan, &sg, 1, dir, flags);
 }
 
+static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
+			struct dma_chan *chan, struct scatterlist *dst_sg,
+			unsigned int dst_nents,	struct scatterlist *src_sg,
+			unsigned int src_nents,	unsigned long flags)
+{
+	return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents,
+					src_sg, src_nents, flags, NULL);
+}
+
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg_ext(
+			struct dma_chan *chan, struct scatterlist *dst_sg,
+			unsigned int dst_nents,	struct scatterlist *src_sg,
+			unsigned int src_nents,	unsigned long flags,
+					void *context)
+{
+	return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents,
+					src_sg, src_nents, flags, context);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
+			struct dma_chan *chan,
+			struct dma_interleaved_template *xt,
+			unsigned long flags)
+{
+	return chan->device->device_prep_interleaved_dma(chan, xt,
+							flags, NULL);
+}
+
+
+static inline struct dma_async_tx_descriptor
+			*dmaengine_prep_interleaved_dma_ext(
+			struct dma_chan *chan,
+			struct dma_interleaved_template *xt,
+			unsigned long flags,
+			void *context)
+{
+	return chan->device->device_prep_interleaved_dma(chan, xt,
+							flags, context);
+}
+
 static inline int dmaengine_terminate_all(struct dma_chan *chan)
 {
 	return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From kumarrav at codeaurora.org  Thu Mar 22 02:40:37 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Thu, 22 Mar 2012 12:10:37 +0530
Subject: [PATCH 2/2] DMAEngine: Add DMAEngine driver based on old MSM ADM DMA
 APIs
In-Reply-To: <1332398437-13306-1-git-send-email-kumarrav@codeaurora.org>
References: <1332398437-13306-1-git-send-email-kumarrav@codeaurora.org>
Message-ID: <1332398437-13306-3-git-send-email-kumarrav@codeaurora.org>

Add DMAEngine based driver using the old MSM ADM DMA APIs internally.
The benefit of this approach is that not all the drivers
have to get converted to DMAEngine APIs simultaneosly while
both the drivers can stay enabled in the kernel. The client
drivers using the old MSM APIs directly can now convert to
DMAEngine one by one.

Change-Id: I3647ed7b8c73b3078dfa8877a3560db3cb0a2373
Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
---
 arch/arm/mach-msm/include/mach/dma.h |   35 ++
 drivers/dma/Kconfig                  |   12 +
 drivers/dma/Makefile                 |    1 +
 drivers/dma/msm_adm_dma.c            |  728 ++++++++++++++++++++++++++++++++++
 4 files changed, 776 insertions(+), 0 deletions(-)
 create mode 100644 drivers/dma/msm_adm_dma.c

diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 05583f5..95b7b15 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -18,6 +18,36 @@
 #include <linux/list.h>
 #include <mach/msm_iomap.h>
 
+#define sg_dma_offset(sg)               ((sg)->offset)
+#define box_dma_row_address(box)        ((box)->dma_row_address)
+#define box_dma_row_len(box)            ((box)->dma_row_len)
+#define box_dma_row_num(box)            ((box)->dma_row_num)
+#define box_dma_row_offset(box)         ((box)->dma_row_offset)
+
+#define MSM_DMA_CMD_MASK		0x9FFF8
+#define MSM_DMA_CMD_SHIFT		0
+#define MSM_BOX_SRC_RLEN_MASK		0xFFFF
+#define MSM_BOX_SRC_RLEN_SHIFT		16
+#define MSM_BOX_SRC_RNUM_MASK		0xFFFF
+#define MSM_BOX_SRC_RNUM_SHIFT		16
+#define MSM_BOX_SRC_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_SRC_ROFFSET_SHIFT	16
+#define MSM_BOX_DST_RLEN_MASK		0xFFFF
+#define MSM_BOX_DST_RNUM_MASK		0xFFFF
+#define MSM_BOX_DST_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_MODE_CMD		0x3
+
+enum adm_flush_type {
+	ADM_FORCED_FLUSH,
+	ADM_GRACEFUL_FLUSH,
+};
+
+enum adm_dma_type {
+	ADM_SINGLE_MODE,
+	ADM_SG_MODE,
+	ADM_BOX_MODE,
+};
+
 struct msm_dmov_errdata {
 	uint32_t flush[6];
 };
@@ -32,6 +62,11 @@ struct msm_dmov_cmd {
 	void *data;
 };
 
+struct msm_adm_cmd_config {
+	uint32_t num_cmd;
+	uint32_t *cmd_cntrl;
+};
+
 #ifndef CONFIG_ARCH_MSM8X60
 void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
 void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f1a2749..1f99362 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -252,6 +252,18 @@ config EP93XX_DMA
 	help
 	  Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
 
+config MSM_ADM_DMA
+	tristate "Qualcomm MSM ADM DMA support"
+	depends on ARCH_MSM
+	select DMA_ENGINE
+	help
+	  Support the Qualcomm DMA engine. This engine is integrated into
+	  Qualcomm chips.
+
+	  Say Y here if you have such a chipset.
+
+	  If unsure, say N.
+
 config DMA_ENGINE
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 009a222..f55fb57 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
 obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
 obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
 obj-$(CONFIG_IMX_DMA) += imx-dma.o
+obj-$(CONFIG_MSM_ADM_DMA) += msm_adm_dma.o
 obj-$(CONFIG_MXS_DMA) += mxs-dma.o
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
diff --git a/drivers/dma/msm_adm_dma.c b/drivers/dma/msm_adm_dma.c
new file mode 100644
index 0000000..f5bbdc5
--- /dev/null
+++ b/drivers/dma/msm_adm_dma.c
@@ -0,0 +1,728 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/dmapool.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/dma.h>
+
+#define SD3_CHAN_START			0
+#define MSM_DMOV_CRCI_COUNT		16
+#define MSM_DMA_MAX_CHANS_PER_DEVICE	16
+#define MAX_TRANSFER_LENGTH		65535
+#define NO_ERR_CHAN_STATUS		0x80000002
+#define to_msm_chan(chan) container_of(chan, struct msm_dma_chan, channel)
+
+struct msm_dma_chan {
+	int chan_id;
+	dma_cookie_t completed_cookie;
+	dma_cookie_t error_cookie;
+	spinlock_t lock;
+	struct list_head active_list;
+	struct list_head pending_list;
+	struct dma_chan channel;
+	struct dma_pool *desc_pool;
+	struct device *dev;
+	int max_len;
+	int err;
+	struct tasklet_struct tasklet;
+};
+
+struct msm_dma_device {
+	void __iomem *base;
+	struct device *dev;
+	struct dma_device common;
+	struct msm_dma_chan *chan[MSM_DMA_MAX_CHANS_PER_DEVICE];
+};
+
+struct msm_dma_desc_hw {
+	unsigned int cmd_list_ptr;
+} __aligned(8);
+
+/* Single Item Mode */
+struct adm_cmd_t {
+	unsigned int cmd_cntrl;
+	unsigned int src;
+	unsigned int dst;
+	unsigned int len;
+};
+
+struct adm_box_cmd_t {
+	uint32_t cmd_cntrl;
+	uint32_t src_row_addr;
+	uint32_t dst_row_addr;
+	uint32_t src_dst_len;
+	uint32_t num_rows;
+	uint32_t row_offset;
+};
+
+struct msm_dma_desc_sw {
+	struct msm_dma_desc_hw hw;
+	struct adm_cmd_t *vaddr_cmd;
+	struct adm_box_cmd_t *vaddr_box_cmd;
+	size_t coherent_size;
+	dma_addr_t paddr_cmd_list;
+	struct list_head node;
+	struct msm_dmov_cmd dmov_cmd;
+	struct dma_async_tx_descriptor async_tx;
+} __aligned(8);
+
+static int msm_dma_alloc_chan_resources(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+
+	/* Has this channel already been allocated? */
+	if (chan->desc_pool)
+		return 1;
+
+	/*
+	 * We need the descriptor to be aligned to 8bytes
+	 * for meeting ADM specification requirement.
+	 */
+	chan->desc_pool = dma_pool_create("msm_dma_desc_pool",
+					chan->dev,
+					sizeof(struct msm_dma_desc_sw),
+				__alignof__(struct msm_dma_desc_sw), 0);
+	if (!chan->desc_pool) {
+		dev_err(chan->dev, "unable to allocate channel %d "
+				"descriptor pool\n", chan->chan_id);
+		return -ENOMEM;
+	}
+
+	chan->completed_cookie = 1;
+	dchan->cookie = 1;
+
+	/* there is at least one descriptor free to be allocated */
+	return 1;
+}
+
+static void msm_dma_free_desc_list(struct msm_dma_chan *chan,
+						struct list_head *list)
+{
+	struct msm_dma_desc_sw *desc, *_desc;
+
+	list_for_each_entry_safe(desc, _desc, list, node) {
+		list_del(&desc->node);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	}
+}
+
+static void msm_dma_free_chan_resources(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	unsigned long flags;
+
+	dev_dbg(chan->dev, "Free all channel resources.\n");
+	spin_lock_irqsave(&chan->lock, flags);
+	msm_dma_free_desc_list(chan, &chan->active_list);
+	msm_dma_free_desc_list(chan, &chan->pending_list);
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	dma_pool_destroy(chan->desc_pool);
+	chan->desc_pool = NULL;
+}
+
+static enum dma_status msm_dma_desc_status(struct msm_dma_chan *chan,
+					struct msm_dma_desc_sw *desc)
+{
+	return dma_async_is_complete(desc->async_tx.cookie,
+					chan->completed_cookie,
+					chan->channel.cookie);
+}
+
+static void msm_chan_desc_cleanup(struct msm_dma_chan *chan)
+{
+	struct msm_dma_desc_sw *desc, *_desc;
+	unsigned long flags;
+
+	dev_dbg(chan->dev, "Cleaning completed descriptor of channel %d\n",
+							chan->chan_id);
+	spin_lock_irqsave(&chan->lock, flags);
+
+	list_for_each_entry_safe(desc, _desc, &chan->active_list, node) {
+		dma_async_tx_callback callback;
+		void *callback_param;
+
+		if (msm_dma_desc_status(chan, desc) == DMA_IN_PROGRESS)
+			break;
+
+		/* Remove from the list of running transactions */
+		list_del(&desc->node);
+
+		/* Run the link descriptor callback function */
+		callback = desc->async_tx.callback;
+		callback_param = desc->async_tx.callback_param;
+		if (callback) {
+			spin_unlock_irqrestore(&chan->lock, flags);
+			callback(callback_param);
+			spin_lock_irqsave(&chan->lock, flags);
+		}
+
+		/* Run any dependencies, then free the descriptor */
+		dma_run_dependencies(&desc->async_tx);
+		spin_unlock_irqrestore(&chan->lock, flags);
+
+		if (desc->vaddr_cmd) {
+			dma_free_coherent(chan->dev, desc->coherent_size,
+						(void *)desc->vaddr_cmd,
+							desc->paddr_cmd_list);
+		} else {
+			dma_free_coherent(chan->dev, desc->coherent_size,
+						(void *)desc->vaddr_box_cmd,
+							desc->paddr_cmd_list);
+		}
+		spin_lock_irqsave(&chan->lock, flags);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	}
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+static void dma_do_tasklet(unsigned long data)
+{
+	struct msm_dma_chan *chan = (struct msm_dma_chan *)data;
+	msm_chan_desc_cleanup(chan);
+}
+
+static void
+msm_dma_complete_func(struct msm_dmov_cmd *cmd,
+				unsigned int result,
+				struct msm_dmov_errdata *err)
+{
+	unsigned long flags;
+	struct msm_dma_desc_sw *desch = container_of(cmd,
+				struct msm_dma_desc_sw, dmov_cmd);
+	struct msm_dma_chan *chan = to_msm_chan(desch->async_tx.chan);
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if ((result != NO_ERR_CHAN_STATUS) && err)
+		chan->error_cookie = desch->async_tx.cookie;
+	chan->completed_cookie = desch->async_tx.cookie;
+
+	tasklet_schedule(&chan->tasklet);
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+/*
+ *  Passes transfer descriptors to DMA hardware.
+ */
+static void msm_dma_issue_pending(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	struct msm_dma_desc_sw *desch;
+	unsigned long flags;
+
+	if (chan->err)
+		return;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if (list_empty(&chan->pending_list))
+		goto out_unlock;
+
+	desch = list_first_entry(&chan->pending_list, struct msm_dma_desc_sw,
+									node);
+	list_del(&desch->node);
+	desch->dmov_cmd.complete_func = msm_dma_complete_func;
+	desch->dmov_cmd.execute_func = NULL;
+	desch->dmov_cmd.cmdptr = DMOV_CMD_ADDR(desch->async_tx.phys);
+	list_add_tail(&desch->node, &chan->active_list);
+	mb();
+	msm_dmov_enqueue_cmd(chan->chan_id, &desch->dmov_cmd);
+out_unlock:
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+/*
+ *  Assignes cookie for each transfer descriptor passed.
+ *  Returns
+ *	Assigend cookie for success.
+ *	Error value for failure.
+ */
+static dma_cookie_t msm_dma_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	struct msm_dma_chan *chan = to_msm_chan(tx->chan);
+	struct msm_dma_desc_sw *desc = container_of(tx,
+	struct msm_dma_desc_sw, async_tx);
+	unsigned long flags;
+	dma_cookie_t cookie = -EBUSY;
+
+	if (chan->err)
+		return cookie;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	/*
+	 * assign cookies to all of the software descriptors
+	 * that make up this transaction
+	 */
+	cookie = chan->channel.cookie;
+	cookie++;
+	if (cookie < 0)
+		cookie = DMA_MIN_COOKIE;
+
+	desc->async_tx.cookie = cookie;
+	chan->channel.cookie = cookie;
+
+	/* put this transaction onto the tail of the pending queue */
+	list_add_tail(&desc->node, &chan->pending_list);
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	return cookie;
+}
+
+/*
+ *  Returns the DMA transfer status of a particular cookie
+ */
+static enum dma_status msm_tx_status(struct dma_chan *dchan,
+					dma_cookie_t cookie,
+				struct dma_tx_state *txstate)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	dma_cookie_t last_used;
+	dma_cookie_t last_complete;
+	enum dma_status status;
+
+	last_used = dchan->cookie;
+	last_complete = chan->completed_cookie;
+
+	dma_set_tx_state(txstate, last_complete, last_used, 0);
+
+	status = dma_async_is_complete(cookie, last_complete, last_used);
+
+	if (status != DMA_IN_PROGRESS)
+		if (chan->error_cookie == cookie)
+			status = DMA_ERROR;
+
+	return status;
+}
+
+static struct msm_dma_desc_sw *msm_dma_alloc_descriptor(
+				struct msm_dma_chan *chan,
+				int cmd_cnt,
+				enum adm_dma_type mask)
+{
+	struct msm_dma_desc_sw *desc;
+	dma_addr_t pdesc_addr;
+	dma_addr_t paddr_cmd_list;
+	void *err = NULL;
+
+	desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc_addr);
+	if (!desc) {
+		dev_dbg(chan->dev, "out of memory for desc\n");
+		return ERR_CAST(desc);
+	}
+
+	memset(desc, 0, sizeof(*desc));
+	desc->async_tx.phys = pdesc_addr;
+
+	if (mask == ADM_BOX_MODE) {
+		desc->coherent_size = sizeof(struct adm_box_cmd_t);
+		desc->vaddr_box_cmd = dma_alloc_coherent(chan->dev,
+				sizeof(struct adm_box_cmd_t),
+				&paddr_cmd_list, GFP_ATOMIC);
+		if (!desc->vaddr_box_cmd) {
+			dev_dbg(chan->dev, "out of memory for desc\n");
+			err = desc->vaddr_box_cmd;
+			goto fail;
+		}
+	} else {
+		desc->coherent_size = sizeof(struct adm_cmd_t)*cmd_cnt;
+
+		desc->vaddr_cmd = dma_alloc_coherent(chan->dev,
+				sizeof(struct adm_cmd_t)*cmd_cnt,
+				&paddr_cmd_list, GFP_ATOMIC);
+
+		if (!desc->vaddr_cmd) {
+			dev_dbg(chan->dev, "out of memory for desc\n");
+			err = desc->vaddr_cmd;
+			goto fail;
+		}
+	}
+
+	dma_async_tx_descriptor_init(&desc->async_tx, &chan->channel);
+	desc->async_tx.tx_submit = msm_dma_tx_submit;
+	desc->paddr_cmd_list = paddr_cmd_list;
+	desc->hw.cmd_list_ptr = (paddr_cmd_list >> 3) | CMD_PTR_LP;
+	return desc;
+fail:
+	dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	return ERR_CAST(err);
+}
+
+/*
+ *  Prepares the transfer descriptors for SG transaction.
+ *  Returns
+ *	address of dma_async_tx_descriptor for success.
+ *	Pointer of error value for failure.
+ */
+static struct dma_async_tx_descriptor *msm_dma_prep_sg(
+		struct dma_chan *dchan,
+		struct scatterlist *dst_sg, unsigned int dst_nents,
+		struct scatterlist *src_sg, unsigned int src_nents,
+		unsigned long flags, void *context)
+{
+
+	struct msm_dma_chan *chan;
+	struct msm_dma_desc_sw *new;
+	size_t copy, len;
+	int cmd_cnt = 0;
+	int first = 0;
+	int i;
+	dma_addr_t src;
+	dma_addr_t dst;
+	struct adm_cmd_t *cmdlist_vaddr;
+	struct scatterlist *sg;
+	struct msm_adm_cmd_config *cmd_config = context;
+
+	if (!dchan)
+		return ERR_PTR(-EINVAL);
+
+	if (dst_nents == 0 || src_nents == 0)
+		return ERR_PTR(-EINVAL);
+	if (!dst_sg || !src_sg)
+		return ERR_PTR(-EINVAL);
+
+	if ((dst_nents != src_nents) || (cmd_config->num_cmd != src_nents))
+		return ERR_PTR(-EINVAL);
+
+	chan = to_msm_chan(dchan);
+
+	cmd_cnt = src_nents;
+	for (i = 0; i < src_nents; i++) {
+		len = sg_dma_len(src_sg + i);
+		if (len != MAX_TRANSFER_LENGTH)
+			cmd_cnt += len/MAX_TRANSFER_LENGTH;
+	}
+
+	new = msm_dma_alloc_descriptor(chan, cmd_cnt, ADM_SG_MODE);
+
+	if (!new) {
+		dev_err(chan->dev,
+			"No free memory for link descriptor\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	cmdlist_vaddr = new->vaddr_cmd;
+
+	for_each_sg(src_sg, sg, src_nents, i) {
+		len = sg_dma_len(sg);
+		src = sg_dma_address(sg);
+		do {
+			copy = (len >= MAX_TRANSFER_LENGTH) ?
+						MAX_TRANSFER_LENGTH : len;
+			cmdlist_vaddr->src = src;
+			cmdlist_vaddr->len = copy;
+			cmdlist_vaddr->cmd_cntrl =
+					*(cmd_config->cmd_cntrl + i) &
+							MSM_DMA_CMD_MASK;
+			if (first == 0) {
+				if (cmd_cnt == 1)
+					cmdlist_vaddr->cmd_cntrl |= CMD_LC;
+				else
+					cmdlist_vaddr->cmd_cntrl |= CMD_OCB;
+				first = 1;
+			}
+			cmdlist_vaddr++;
+			len -= copy;
+			src += copy;
+		} while (len);
+	}
+	if (cmd_cnt > 1) {
+		cmdlist_vaddr--;
+		cmdlist_vaddr->cmd_cntrl |= CMD_LC | CMD_OCU;
+	}
+
+	cmdlist_vaddr = new->vaddr_cmd;
+
+	for_each_sg(dst_sg, sg, src_nents, i) {
+		len = sg_dma_len(sg);
+		dst = sg_dma_address(sg);
+		do {
+			copy = (len >= MAX_TRANSFER_LENGTH) ?
+					MAX_TRANSFER_LENGTH : len;
+			cmdlist_vaddr->dst = dst;
+			cmdlist_vaddr++;
+			len -= copy;
+			dst += copy;
+		} while (len);
+
+	}
+
+#ifdef DEBUG
+	cmdlist_vaddr = new->vaddr_cmd;
+	i = 0;
+	do {
+		dev_dbg(chan->dev, "cmd %d src 0x%x dst 0x%x len 0x%x "
+						"cntrl 0x%x\n",
+				i, cmdlist_vaddr->src, cmdlist_vaddr->dst,
+				cmdlist_vaddr->len, cmdlist_vaddr->cmd_cntrl);
+			cmdlist_vaddr++;
+	} while (!((cmdlist_vaddr-1)->cmd_cntrl & CMD_LC));
+#endif
+	new->async_tx.flags = flags;
+	new->async_tx.cookie = -EBUSY;
+
+	return &new->async_tx;
+}
+
+struct dma_async_tx_descriptor *msm_dma_prep_interleaved(
+				struct dma_chan *dchan,
+				struct dma_interleaved_template *xt,
+				unsigned long flags,
+				void *context)
+{
+
+	struct msm_dma_chan *chan;
+	struct msm_dma_desc_sw *new;
+	struct adm_box_cmd_t *box_cmd_vaddr;
+	struct msm_adm_cmd_config *cmd_config = context;
+
+	if (!dchan)
+		return ERR_PTR(-EINVAL);
+
+	if (!xt)
+		return ERR_PTR(-EINVAL);
+
+	chan = to_msm_chan(dchan);
+
+	new = msm_dma_alloc_descriptor(chan, 1, ADM_BOX_MODE);
+
+	if (!new) {
+		dev_err(chan->dev,
+			"No free memory for link descriptor\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	box_cmd_vaddr = new->vaddr_box_cmd;
+
+
+	box_cmd_vaddr->src_row_addr = xt->src_start;
+	box_cmd_vaddr->dst_row_addr = xt->dst_start;
+	box_cmd_vaddr->src_dst_len =
+			((xt->sgl[0].size & MSM_BOX_SRC_RLEN_MASK) <<
+					MSM_BOX_SRC_RLEN_SHIFT) |
+				(xt->sgl[0].size & MSM_BOX_DST_RLEN_MASK);
+
+	box_cmd_vaddr->cmd_cntrl =
+			(cmd_config->cmd_cntrl[0] & MSM_DMA_CMD_MASK) |
+						MSM_BOX_MODE_CMD | CMD_LC;
+
+	box_cmd_vaddr->num_rows =
+			((xt->numf & MSM_BOX_SRC_RNUM_MASK) <<
+			MSM_BOX_SRC_RNUM_SHIFT) |
+			(xt->numf & MSM_BOX_DST_RNUM_MASK);
+
+	if ((xt->src_sgl) && (xt->src_inc))
+		box_cmd_vaddr->row_offset =
+				((xt->sgl[0].size + xt->sgl[0].icg) &
+				MSM_BOX_SRC_ROFFSET_MASK) <<
+				MSM_BOX_SRC_ROFFSET_SHIFT;
+	else if ((!xt->src_sgl) && (xt->src_inc))
+		box_cmd_vaddr->row_offset = ((xt->sgl[0].size) &
+				MSM_BOX_SRC_ROFFSET_MASK) <<
+				MSM_BOX_SRC_ROFFSET_SHIFT;
+	else
+		box_cmd_vaddr->row_offset =
+			(0 & MSM_BOX_SRC_ROFFSET_MASK) <<
+			MSM_BOX_SRC_ROFFSET_SHIFT;
+
+
+	if ((xt->dst_sgl) && (xt->dst_inc))
+		box_cmd_vaddr->row_offset |=
+			((xt->sgl[0].size + xt->sgl[0].icg) &
+			MSM_BOX_DST_ROFFSET_MASK);
+	else if ((!xt->dst_sgl) && (xt->dst_inc))
+		box_cmd_vaddr->row_offset |= ((xt->sgl[0].size) &
+					MSM_BOX_DST_ROFFSET_MASK);
+	else
+		box_cmd_vaddr->row_offset |= (0 & MSM_BOX_DST_ROFFSET_MASK);
+
+	new->async_tx.flags = flags;
+	new->async_tx.cookie = -EBUSY;
+
+	return &new->async_tx;
+}
+
+/*
+ *  Controlling the hardware channel like stopping, flushing.
+ */
+static int msm_dma_chan_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+							unsigned long arg)
+{
+	enum adm_flush_type cmd_type = arg;
+
+	if (cmd == DMA_TERMINATE_ALL) {
+		switch (cmd_type) {
+		case ADM_GRACEFUL_FLUSH:
+				msm_dmov_stop_cmd(chan->chan_id, NULL, 1);
+			break;
+		case ADM_FORCED_FLUSH:
+			/*
+			 * We treate default as forced flush
+			 * so we fall through
+			 */
+		default:
+				msm_dmov_stop_cmd(chan->chan_id, NULL, 0);
+			break;
+		}
+	}
+	return 0;
+}
+
+static void msm_dma_chan_remove(struct msm_dma_chan *chan)
+{
+	tasklet_kill(&chan->tasklet);
+	list_del(&chan->channel.device_node);
+	kfree(chan);
+}
+
+static __devinit int msm_dma_chan_probe(struct msm_dma_device *qdev,
+					int channel)
+{
+	struct msm_dma_chan *chan;
+
+	chan = kzalloc(sizeof(*chan), GFP_KERNEL);
+	if (!chan) {
+		dev_err(qdev->dev, "no free memory for DMA channels!\n");
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&chan->lock);
+	INIT_LIST_HEAD(&chan->pending_list);
+	INIT_LIST_HEAD(&chan->active_list);
+
+	chan->chan_id = channel;
+	chan->completed_cookie = 0;
+	chan->channel.cookie = 0;
+	chan->max_len = MAX_TRANSFER_LENGTH;
+	chan->err = 0;
+	qdev->chan[channel] = chan;
+	chan->channel.device = &qdev->common;
+	chan->dev = qdev->dev;
+
+	tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
+
+	list_add_tail(&chan->channel.device_node, &qdev->common.channels);
+	qdev->common.chancnt++;
+
+	return 0;
+}
+
+static int __devinit msm_dma_probe(struct platform_device *pdev)
+{
+	struct msm_dma_device *qdev;
+	int i;
+	int ret = 0;
+
+	qdev = kzalloc(sizeof(*qdev), GFP_KERNEL);
+	if (!qdev) {
+		dev_err(&pdev->dev, "Not enough memory for device\n");
+		return -ENOMEM;
+	}
+
+	qdev->dev = &pdev->dev;
+	INIT_LIST_HEAD(&qdev->common.channels);
+	qdev->common.device_alloc_chan_resources =
+				msm_dma_alloc_chan_resources;
+	qdev->common.device_free_chan_resources =
+				msm_dma_free_chan_resources;
+	dma_cap_set(DMA_SG, qdev->common.cap_mask);
+	dma_cap_set(DMA_INTERLEAVE, qdev->common.cap_mask);
+
+	qdev->common.device_prep_dma_sg = msm_dma_prep_sg;
+	qdev->common.device_prep_interleaved_dma = msm_dma_prep_interleaved;
+	qdev->common.device_issue_pending = msm_dma_issue_pending;
+	qdev->common.dev = &pdev->dev;
+	qdev->common.device_tx_status = msm_tx_status;
+	qdev->common.device_control = msm_dma_chan_control;
+
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		ret = msm_dma_chan_probe(qdev, i);
+		if (ret) {
+			dev_err(&pdev->dev, "channel %d probe failed\n", i);
+			goto chan_free;
+		}
+	}
+
+	dev_info(&pdev->dev, "registering dma device\n");
+
+	ret = dma_async_device_register(&qdev->common);
+
+	if (ret) {
+		dev_err(&pdev->dev, "Registering Dma device failed\n");
+		goto chan_free;
+	}
+
+	dev_set_drvdata(&pdev->dev, qdev);
+	return 0;
+chan_free:
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		if (qdev->chan[i])
+			msm_dma_chan_remove(qdev->chan[i]);
+	}
+	kfree(qdev);
+	return ret;
+}
+
+static int  __devexit msm_dma_remove(struct platform_device *pdev)
+{
+	struct msm_dma_device *qdev = platform_get_drvdata(pdev);
+	int i;
+
+	dma_async_device_unregister(&qdev->common);
+
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		if (qdev->chan[i])
+			msm_dma_chan_remove(qdev->chan[i]);
+	}
+
+	dev_set_drvdata(&pdev->dev, NULL);
+	kfree(qdev);
+
+	return 0;
+}
+
+static struct platform_driver msm_dma_driver = {
+	.remove = __devexit_p(msm_dma_remove),
+	.driver = {
+		.name = "msm_dma",
+		.owner = THIS_MODULE,
+	},
+};
+
+static __init int msm_dma_init(void)
+{
+	return platform_driver_probe(&msm_dma_driver, msm_dma_probe);
+}
+subsys_initcall(msm_dma_init);
+
+static void __exit msm_dma_exit(void)
+{
+	platform_driver_unregister(&msm_dma_driver);
+}
+module_exit(msm_dma_exit);
+
+MODULE_DESCRIPTION("Qualcomm DMA driver");
+MODULE_LICENSE("GPL v2");
-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From paul.liu at linaro.org  Thu Mar 22 02:49:36 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Thu, 22 Mar 2012 14:49:36 +0800
Subject: [PATCH v13] Regulator: Add Anatop regulator driver
In-Reply-To: <20120322052449.GB2213@S2101-09.ap.freescale.net>
References: <1331692152-9256-1-git-send-email-paul.liu@linaro.org>
 <20120322052449.GB2213@S2101-09.ap.freescale.net>
Message-ID: <4F6ACB80.10809@linaro.org>

(2012?03?22? 13:24), Shawn Guo wrote:
> On Wed, Mar 14, 2012 at 10:29:12AM +0800, Ying-Chun Liu (PaulLiu) wrote:
>> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
>>
>> Anatop is an integrated regulator inside i.MX6 SoC.
>> There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
>> And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
>> This patch adds the Anatop regulator driver.
>>
>> Signed-off-by: Nancy Chen <Nancy.Chen at freescale.com>
>> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
>> Acked-by: Shawn Guo <shawn.guo at linaro.org>
>> Reviewed-by: Axel Lin <axel.lin at gmail.com>
>> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
>> Cc: Liam Girdwood <lrg at ti.com>
>> Cc: Samuel Ortiz <sameo at linux.intel.com>
>> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>> ---
>>  drivers/regulator/Kconfig            |    8 +
>>  drivers/regulator/Makefile           |    1 +
>>  drivers/regulator/anatop-regulator.c |  241 ++++++++++++++++++++++++++++++++++
>>  3 files changed, 250 insertions(+), 0 deletions(-)
>>  create mode 100644 drivers/regulator/anatop-regulator.c
>>
> I just noticed that the binding document below got lost since v11 of
> the series.
> 
>   Documentation/devicetree/bindings/regulator/anatop-regulator.txt
> 
> It got lost by mistaken or you dropped it for some reason?
> 

Ouch. I'll prepare a separate patch to add back the documentation.

Sorry,

Paul



From govindraj.raja at ti.com  Thu Mar 22 02:59:56 2012
From: govindraj.raja at ti.com (Raja, Govindraj)
Date: Thu, 22 Mar 2012 12:29:56 +0530
Subject: [PATCH 0/3] OMAP2+: UART: Enable tx wakeup + remove cpu checks
In-Reply-To: <87limurpsx.fsf@ti.com>
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
 <87limurpsx.fsf@ti.com>
Message-ID: <CAMrsUdLtC0iVk2qDDDXj2tteAzP5UQJXNvsCoJLEC9Yty2QjvQ@mail.gmail.com>

On Wed, Mar 21, 2012 at 7:58 PM, Kevin Hilman <khilman at ti.com> wrote:
> "Govindraj.R" <govindraj.raja at ti.com> writes:
>
>> From: "Govindraj.R" <govindraj.raja at ti.com>
>>
>> Based on Linux-OMAP tree uart branch.
>> (git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
>> remotes/origin/uart)
>>
>> * Removes the cpu checks wherever possible and use version reg
>> ? for populating features and errata's
>> * enable tx wakeup available in wer reg for applicable
>> ? module revision's
>
> As this affects multiple SoCs, please report what SoCs it was tested on
> as well.

Sorry I for got to add that, here are details on what was tested.

1.) OMAP2430 SDP : Boot tested with uart1 as console.

2.) OMAP3430 SDP: Boot test, suspend/resume tests, retention off mode
                               (checking retention and off mode count
in cpu idle cases)

3.) OMAP3630 - Beagle XM:  Boot test, suspend/resume tests, retention off mode
                                            (checking retention and
off mode count in cpu idle cases)

4.) OMAP4430 - PANDA: Boot test, suspend/resume tests

5.) OMAP4460 - PANDA: Boot test.

--
Thanks,
Govindraj.R


>
> Thanks,
>
> Kevin
>
>> Govindraj.R (3):
>> ? OMAP2+: UART: Remove cpu checks for populating errata flags
>> ? OMAP2+: UART: enable tx wakeup bit for wer reg
>> ? OMAP2+: UART: replace omap34xx/omap4xx cpu checks with not omap24xx
>>
>> ?arch/arm/mach-omap2/serial.c ? ? ? ? ? ? ? ? ?| ? 13 +----
>> ?arch/arm/plat-omap/include/plat/omap-serial.h | ? ?8 +++-
>> ?drivers/tty/serial/omap-serial.c ? ? ? ? ? ? ?| ? 71 ++++++++++++++++++++++++-
>> ?3 files changed, 78 insertions(+), 14 deletions(-)


From shawn.guo at linaro.org  Thu Mar 22 03:11:54 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 22 Mar 2012 15:11:54 +0800
Subject: [PATCH v13] Regulator: Add Anatop regulator driver
In-Reply-To: <4F6ACB80.10809@linaro.org>
References: <1331692152-9256-1-git-send-email-paul.liu@linaro.org>
 <20120322052449.GB2213@S2101-09.ap.freescale.net>
 <4F6ACB80.10809@linaro.org>
Message-ID: <20120322071152.GC2213@S2101-09.ap.freescale.net>

On Thu, Mar 22, 2012 at 02:49:36PM +0800, Ying-Chun Liu (PaulLiu) wrote:
...
> Ouch. I'll prepare a separate patch to add back the documentation.
> 
I just gave a quick testing on the driver with the dts change you
posted on imx6.  There is some little problem we may need to address.

prom_parse: Bad cell count for /soc/aips-bus at 02000000/anatop at 020c8000/regulator-vddpu at 140
vddpu: 725 <--> 1300 mV at 1100 mV
prom_parse: Bad cell count for /soc/aips-bus at 02000000/anatop at 020c8000/regulator-vddcore at 140
cpu: 725 <--> 1300 mV at 1100 mV
prom_parse: Bad cell count for /soc/aips-bus at 02000000/anatop at 020c8000/regulator-vddsoc at 140
vddsoc: 725 <--> 1300 mV at 1100 mV
prom_parse: Bad cell count for /soc/aips-bus at 02000000/anatop at 020c8000/regulator-2p5 at 130
vdd2p5: 2000 <--> 2775 mV at 2400 mV
prom_parse: Bad cell count for /soc/aips-bus at 02000000/anatop at 020c8000/regulator-1p1 at 110
vdd1p1: 800 <--> 1400 mV at 1100 mV
prom_parse: Bad cell count for /soc/aips-bus at 02000000/anatop at 020c8000/regulator-3p0 at 120
vdd3p0: 2800 <--> 3150 mV at 3000 mV

The DT core function __of_translate_address will give some annoying
error messages.  We call of_platform_populate from anatop mfd driver
to populate regulator device, and during the call, DT core tries to
translate "reg" property to address resource, and will complain if
!(#size-cells > 0). 

To fix that, we may want to rename "reg" property to something else,
e.g. "anatop-reg-offset".  I tested the following changes removed the
error messages above.

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 56d3c16..65bad45 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -346,16 +346,14 @@
                                compatible = "fsl,imx6q-anatop";
                                reg = <0x020c8000 0x1000>;
                                interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
-                               #address-cells = <1>;
-                               #size-cells = <0>;

-                               regulator-vddpu at 140 {
+                               regulator-vddpu {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddpu";
                                        regulator-min-microvolt = <725000>;
                                        regulator-max-microvolt = <1300000>;
                                        regulator-always-on;
-                                       reg = <0x140>;
+                                       anatop-reg-offset = <0x140>;
                                        anatop-vol-bit-shift = <9>;
                                        anatop-vol-bit-width = <5>;
                                        anatop-min-bit-val = <1>;
@@ -363,13 +361,13 @@
                                        anatop-max-voltage = <1300000>;
                                };

-                               regulator-vddcore at 140 {
+                               regulator-vddcore {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "cpu";
                                        regulator-min-microvolt = <725000>;
                                        regulator-max-microvolt = <1300000>;
                                        regulator-always-on;
-                                       reg = <0x140>;
+                                       anatop-reg-offset = <0x140>;
                                        anatop-vol-bit-shift = <0>;
                                        anatop-vol-bit-width = <5>;
                                        anatop-min-bit-val = <1>;
@@ -377,13 +375,13 @@
                                        anatop-max-voltage = <1300000>;
                                };

-                               regulator-vddsoc at 140 {
+                               regulator-vddsoc {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vddsoc";
                                        regulator-min-microvolt = <725000>;
                                        regulator-max-microvolt = <1300000>;
                                        regulator-always-on;
-                                       reg = <0x140>;
+                                       anatop-reg-offset = <0x140>;
                                        anatop-vol-bit-shift = <18>;
                                        anatop-vol-bit-width = <5>;
                                        anatop-min-bit-val = <1>;
@@ -391,13 +389,13 @@
                                        anatop-max-voltage = <1300000>;
                                };

-                               regulator-2p5 at 130 {
+                               regulator-2p5 {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd2p5";
                                        regulator-min-microvolt = <2000000>;
                                        regulator-max-microvolt = <2775000>;
                                        regulator-always-on;
-                                       reg = <0x130>;
+                                       anatop-reg-offset = <0x130>;
                                        anatop-vol-bit-shift = <8>;
                                        anatop-vol-bit-width = <5>;
                                        anatop-min-bit-val = <0>;
@@ -405,13 +403,13 @@
                                        anatop-max-voltage = <2775000>;
                                };

-                               regulator-1p1 at 110 {
+                               regulator-1p1 {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd1p1";
                                        regulator-min-microvolt = <800000>;
                                        regulator-max-microvolt = <1400000>;
                                        regulator-always-on;
-                                       reg = <0x110>;
+                                       anatop-reg-offset = <0x110>;
                                        anatop-vol-bit-shift = <8>;
                                        anatop-vol-bit-width = <5>;
                                        anatop-min-bit-val = <4>;
@@ -419,13 +417,13 @@
                                        anatop-max-voltage = <1400000>;
                                };

-                               regulator-3p0 at 120 {
+                               regulator-3p0 {
                                        compatible = "fsl,anatop-regulator";
                                        regulator-name = "vdd3p0";
                                        regulator-min-microvolt = <2800000>;
                                        regulator-max-microvolt = <3150000>;
                                        regulator-always-on;
-                                       reg = <0x120>;
+                                       anatop-reg-offset = <0x120>;
                                        anatop-vol-bit-shift = <8>;
                                        anatop-vol-bit-width = <5>;
                                        anatop-min-bit-val = <7>;
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
index 17499a5..632c087 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -138,9 +138,9 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
        rdesc->type = REGULATOR_VOLTAGE;
        rdesc->owner = THIS_MODULE;
        sreg->mfd = anatopmfd;
-       ret = of_property_read_u32(np, "reg", &sreg->control_reg);
+       ret = of_property_read_u32(np, "anatop-reg-offset", &sreg->control_reg);
        if (ret) {
-               dev_err(dev, "no reg property set\n");
+               dev_err(dev, "no anatop-reg-offset property set\n");
                goto anatop_probe_end;
        }
        ret = of_property_read_u32(np, "anatop-vol-bit-width",


-- 
Regards,
Shawn


From mika.westerberg at iki.fi  Thu Mar 22 03:37:50 2012
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Thu, 22 Mar 2012 09:37:50 +0200
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F0020696D48AB1@AUSP01VMBX24.collaborationhost.net>
References: <4F683B36.8090101@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>
 <20120321193231.GA3740@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48AB1@AUSP01VMBX24.collaborationhost.net>
Message-ID: <20120322073750.GA637@mwesterb-mobl.ger.corp.intel.com>

On Wed, Mar 21, 2012 at 07:47:52PM -0500, H Hartley Sweeten wrote:

> I think you misunderstood my comment above.
> 
> With this patch applied I get the "unknown interrupt!" storm. These messages
> keep getting spewed until I power off the board.

Ah, right you are. Sorry.

With my Sim.One board, I don't see any interrupt storms at all and I also have
mmc_spi with DMA enabled.

> Without this patch I get the "got interrupt while active list is empty" messages
> but only occasionally. Other than the messages the mmc_spi driver seems to
> be working ok with dma.
> 
> I hacked in a dump of the DMA Global Interrupt register when I get the
> "got interrupt while active list is empty" messages and get this:
> 
> dma dma1chan1: got interrupt while active list is empty (00000000)

In addition to these messages my board hangs almost every boot.

> So, according to the DMAGlInt register, there are no channels with an
> active interrupt.
> 
> Are we missing a write to the INTERRUPT registers somewhere to clear the
> current interrupt?

In the current code we only enable DONE interrupt and we always clear that at
the beginning of the ISR.

The VIC code was changed in 3.3. Its behaviour is different now as it tries to
handle as many IRQs as possible in one go whereas before it only handled one
IRQ at a time. Could it be that the VIC in ep93xx doesn't cope with that?


From shawn.guo at linaro.org  Thu Mar 22 03:45:23 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 22 Mar 2012 15:45:23 +0800
Subject: [PATCH] ARM: dts: imx6q: add anatop regulators
In-Reply-To: <1332214139-6833-1-git-send-email-paul.liu@linaro.org>
References: <1332214139-6833-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120322074520.GD2213@S2101-09.ap.freescale.net>

On Tue, Mar 20, 2012 at 11:28:59AM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Add anatop regulators to imx6q.dtsi for all imx6q platforms.
> 
I would expect all those regulator device nodes be sorted by
register offset, and for the devices sharing the same register they
can be sorted by anatop-vol-bit-shift.

I'm looking at the IMX6DQRM Rev. C, and commenting the differences
I'm seeing from the document below.

> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> ---
>  arch/arm/boot/dts/imx6q.dtsi |   86 ++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 86 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
> index 263e8f3..dd41514 100644
> --- a/arch/arm/boot/dts/imx6q.dtsi
> +++ b/arch/arm/boot/dts/imx6q.dtsi
> @@ -346,6 +346,92 @@
>  				compatible = "fsl,imx6q-anatop";
>  				reg = <0x020c8000 0x1000>;
>  				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				regulator-vddpu at 140 {
> +					compatible = "fsl,anatop-regulator";
> +					regulator-name = "vddpu";
> +					regulator-min-microvolt = <725000>;
> +					regulator-max-microvolt = <1300000>;
> +					regulator-always-on;
> +					reg = <0x140>;
> +					anatop-vol-bit-shift = <9>;
> +					anatop-vol-bit-width = <5>;
> +					anatop-min-bit-val = <1>;
> +					anatop-min-voltage = <725000>;
> +					anatop-max-voltage = <1300000>;

1.450V

> +				};
> +
> +				regulator-vddcore at 140 {
> +					compatible = "fsl,anatop-regulator";
> +					regulator-name = "cpu";
> +					regulator-min-microvolt = <725000>;
> +					regulator-max-microvolt = <1300000>;
> +					regulator-always-on;
> +					reg = <0x140>;
> +					anatop-vol-bit-shift = <0>;
> +					anatop-vol-bit-width = <5>;
> +					anatop-min-bit-val = <1>;
> +					anatop-min-voltage = <725000>;
> +					anatop-max-voltage = <1300000>;

Ditto

> +				};
> +
> +				regulator-vddsoc at 140 {
> +					compatible = "fsl,anatop-regulator";
> +					regulator-name = "vddsoc";
> +					regulator-min-microvolt = <725000>;
> +					regulator-max-microvolt = <1300000>;
> +					regulator-always-on;
> +					reg = <0x140>;
> +					anatop-vol-bit-shift = <18>;
> +					anatop-vol-bit-width = <5>;
> +					anatop-min-bit-val = <1>;
> +					anatop-min-voltage = <725000>;
> +					anatop-max-voltage = <1300000>;

Ditto

> +				};
> +
> +				regulator-2p5 at 130 {
> +					compatible = "fsl,anatop-regulator";
> +					regulator-name = "vdd2p5";
> +					regulator-min-microvolt = <2000000>;
> +					regulator-max-microvolt = <2775000>;
> +					regulator-always-on;
> +					reg = <0x130>;
> +					anatop-vol-bit-shift = <8>;
> +					anatop-vol-bit-width = <5>;
> +					anatop-min-bit-val = <0>;
> +					anatop-min-voltage = <2000000>;
> +					anatop-max-voltage = <2775000>;

2.75V

> +				};
> +
> +				regulator-1p1 at 110 {
> +					compatible = "fsl,anatop-regulator";
> +					regulator-name = "vdd1p1";
> +					regulator-min-microvolt = <800000>;
> +					regulator-max-microvolt = <1400000>;
> +					regulator-always-on;
> +					reg = <0x110>;
> +					anatop-vol-bit-shift = <8>;
> +					anatop-vol-bit-width = <5>;
> +					anatop-min-bit-val = <4>;
> +					anatop-min-voltage = <800000>;
> +					anatop-max-voltage = <1400000>;

1.375V

> +				};
> +
> +				regulator-3p0 at 120 {
> +					compatible = "fsl,anatop-regulator";
> +					regulator-name = "vdd3p0";
> +					regulator-min-microvolt = <2800000>;
> +					regulator-max-microvolt = <3150000>;
> +					regulator-always-on;
> +					reg = <0x120>;
> +					anatop-vol-bit-shift = <8>;
> +					anatop-vol-bit-width = <5>;
> +					anatop-min-bit-val = <7>;

0

> +					anatop-min-voltage = <2800000>;

2.625V

> +					anatop-max-voltage = <3150000>;

3.4V

> +				};
>  			};
>  
>  			usbphy at 020c9000 { /* USBPHY1 */
> -- 
> 1.7.9.1
> 

-- 
Regards,
Shawn


From linus.walleij at linaro.org  Thu Mar 22 04:00:44 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 22 Mar 2012 09:00:44 +0100
Subject: [PATCH] serial: PL011: move interrupt clearing
In-Reply-To: <CAOh2x==5QHEcA3h216p8rJukx0LR=cVcGYN84aqzw=fnhu8Y-g@mail.gmail.com>
References: <1332357318-8017-1-git-send-email-linus.walleij@linaro.org>
 <CAOh2x==5QHEcA3h216p8rJukx0LR=cVcGYN84aqzw=fnhu8Y-g@mail.gmail.com>
Message-ID: <CACRpkdate+sQJvS8H7qNXiwe6c+F58g=OF0Qg=TxxnTwPXBrYQ@mail.gmail.com>

On Thu, Mar 22, 2012 at 2:04 AM, viresh kumar <viresh.linux at gmail.com> wrote:

>> Cc: Shreshtha Kumar Sahu <shreshthakumar.sahu at stericsson.com>
>> Cc: Russell King <linux at arm.linux.org.uk>
>> Cc: stable <stable at vger.kernel.org>
>> Reported-by: Viresh Kumar <viresh.kumar at st.com>
>> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
>> ---
>> ?drivers/tty/serial/amba-pl011.c | ? ?8 ++++----
>> ?1 files changed, 4 insertions(+), 4 deletions(-)
>
> You missed me in CC??

I put you in Reported-by, then used --cc at the prompt because git send-email
still does not realize it must put Reported-by: tags on the CC list.

Yours,
Linus Walleij


From arnd at arndb.de  Thu Mar 22 04:10:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 22 Mar 2012 08:10:00 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <CAOh2x=nZUobbRJo7kdAwmEG+s51BabxPwUVz=S3oNJyTpuRpCQ@mail.gmail.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203211826.38993.arnd@arndb.de>
 <CAOh2x=nZUobbRJo7kdAwmEG+s51BabxPwUVz=S3oNJyTpuRpCQ@mail.gmail.com>
Message-ID: <201203220810.00628.arnd@arndb.de>

On Thursday 22 March 2012, viresh kumar wrote:
> On Wed, Mar 21, 2012 at 11:56 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> > I just noticed that you have git trees on http://git.stlinux.com/,
> > which I would personally prefer you to use actually. git.kernel.org
> > is most useful for people that don't have their own git servers.
> 
> Ah, that's even better for me too. I don't really have to manage
> two trees.
> 
> Just to understand the flow, how does this work now?
> There can be two sources of patches:
> - From ST internal developers
> - From external developers
> 
> Should i apply them all to my tree and then send you a pull request?
> Or you automatically pull everyday from some specific branch?
> 
> Sorry i am new to this. :(

No problem. Just apply them all to one tree and send me pull
requests when you think they are stable enough and should get into
arm-soc. Once they are in there, I'm not rebasing the patches
any more, but you are free to rebase and reorder the patches
before you send them to me.

If you would like me to take patches that are still under work
and may have to get changed, that's fine too, but tell me in advance
so we can put them into a staging branch that will be part of 
the linux-next kernel but can still get rebased. I'm not sending
staging branches to Linus though, unless you tell me to turn
them into stable branches before the merge window.

Also, please base all your pull requests on an -rc release from
Linus, or (if you have special dependencies) on a stable branch
from another person that then needs to get sent to Linus before
I send your changes. The pull requests should be split up by
topic, e.g. 'general cleanup', 'consolidation of SPEAr3xx and
SPEAr600', 'device tree conversion', 'board specific changes'
etc. so we can combine them with similar topics from other
platform maintainers when sending them out to Linus.

There are two bug fix branches, one for the current kernel (now
3.4) and one for the 'next' kernel (will be 3.5). Any important
changes should go into the 'current' fixes branch, and patches
that also apply to older kernels should get marked 'Cc:
stable at vger.kernel.org' so that Greg will automatically grab
them and apply them to his stable kernel series.

When you send a pull request, please send it to arm at kernel.org
so it reaches both Olof and me, as we are taking turns in
applying them to the arm-soc tree.

Don't hesitate to ask if you have further process questions, I
know this can be confusing and we're doing things much stricter
than other maintainters in order to keep up with ~600 patches
per merge window.

	Arnd


From LW at KARO-electronics.de  Thu Mar 22 04:18:17 2012
From: LW at KARO-electronics.de (=?UTF-8?q?Lothar=20Wa=C3=9Fmann?=)
Date: Thu, 22 Mar 2012 09:18:17 +0100
Subject: [PATCH] ARM: mxs: enforce semantics of clk_prepare()/clk_unprepare()
 and clk_enable()/clk_disable()
Message-ID: <1332404298-18891-1-git-send-email-LW@KARO-electronics.de>

After introducing clk_prepare()/clk_unprepare() there may still be
drivers out there that don't use the new functions.
This patch warns about drivers calling clk_enable() without a
preceding clk_prepare() and various other invalid sequences of calls
to clk_enable()/clk_disable() and clk_prepare()/clk_unprepare().

To not make a system unusable due to excessive warning messages the
warnings are limited to 1 per clk by a flag in the 'flags' member of
struct clk.


Signed-off-by: Lothar Wa?mann <LW at KARO-electronics.de>
---
 arch/arm/mach-mxs/clock.c              |   98 ++++++++++++++++++++++++++++----
 arch/arm/mach-mxs/include/mach/clock.h |    6 ++
 2 files changed, 93 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c
index 97a6f4a..4c23351 100644
--- a/arch/arm/mach-mxs/clock.c
+++ b/arch/arm/mach-mxs/clock.c
@@ -56,24 +56,61 @@ static void __clk_disable(struct clk *clk)
 	if (!(--clk->usecount)) {
 		if (clk->disable)
 			clk->disable(clk);
-		__clk_disable(clk->parent);
 	}
 }
 
 static int __clk_enable(struct clk *clk)
 {
-	if (clk == NULL || IS_ERR(clk))
-		return -EINVAL;
+	if (clk == NULL)
+		return 0;
 
-	if (clk->usecount++ == 0) {
-		__clk_enable(clk->parent);
+	if (IS_ERR(clk))
+		return -EINVAL;
 
-		if (clk->enable)
-			clk->enable(clk);
+	if (clk->usecount == 0) {
+		if (clk->enable) {
+			int ret = clk->enable(clk);
+			if (ret)
+				return ret;
+		}
 	}
+	clk->usecount++;
+
 	return 0;
 }
 
+static void __clk_unprepare(struct clk *clk)
+{
+	if (clk == NULL || IS_ERR(clk))
+		return;
+
+	if (clk->parent)
+		__clk_unprepare(clk->parent);
+
+	__clk_disable(clk);
+}
+
+static int __clk_prepare(struct clk *clk)
+{
+	int ret;
+
+	if (clk == NULL)
+		return 0;
+
+	if (IS_ERR(clk))
+		return -EINVAL;
+
+	ret = __clk_prepare(clk->parent);
+	if (ret)
+		return ret;
+
+	ret = __clk_enable(clk);
+	if (ret)
+		__clk_unprepare(clk->parent);
+
+	return ret;
+}
+
 /*
  * The clk_enable/clk_disable could be called by drivers in atomic context,
  * so they should not really hold mutex.  Instead, clk_prepare/clk_unprepare
@@ -86,11 +123,18 @@ int clk_prepare(struct clk *clk)
 {
 	int ret = 0;
 
-	if (clk == NULL || IS_ERR(clk))
+	if (clk == NULL)
+		return 0;
+
+	if (IS_ERR(clk))
 		return -EINVAL;
 
 	mutex_lock(&clocks_mutex);
-	ret = __clk_enable(clk);
+	if (clk->prepared++ == 0) {
+		ret = __clk_prepare(clk);
+		if (ret)
+			clk->prepared--;
+	}
 	mutex_unlock(&clocks_mutex);
 
 	return ret;
@@ -103,20 +147,52 @@ void clk_unprepare(struct clk *clk)
 		return;
 
 	mutex_lock(&clocks_mutex);
-	__clk_disable(clk);
+	if (WARN_ON(!clk->prepared && !(clk->flags & CLK_WARNED))) {
+		pr_err("clk_unprepare() called without clk_prepare()\n");
+		clk->flags |= CLK_WARNED;
+	}
+	if (WARN_ON(clk->prepared == 1 && clk->usecount > 1)) {
+		pr_err("unbalanced calls (%d) to clk_enable()/clk_disable() before clk_unprepare()\n",
+			clk->usecount);
+		clk->flags |= CLK_WARNED;
+	}
+	if (!(--clk->prepared))
+		__clk_unprepare(clk);
 	mutex_unlock(&clocks_mutex);
 }
 EXPORT_SYMBOL(clk_unprepare);
 
 int clk_enable(struct clk *clk)
 {
+	if (clk == NULL)
+		return 0;
+
+	if (IS_ERR(clk))
+		return -EINVAL;
+
+	if (WARN_ON(!clk->prepared && !(clk->flags & CLK_WARNED))) {
+		pr_err("clk_enable() called without clk_prepare()\n");
+		clk->flags |= CLK_WARNED;
+	}
+	clk->usecount++;
 	return 0;
 }
 EXPORT_SYMBOL(clk_enable);
 
 void clk_disable(struct clk *clk)
 {
-	/* nothing to do */
+	if (clk == NULL || IS_ERR(clk))
+		return;
+
+	if (WARN_ON(!clk->prepared && !(clk->flags & CLK_WARNED))) {
+		pr_err("clk_disable() called without clk_prepare()\n");
+		clk->flags |= CLK_WARNED;
+	}
+	if (WARN_ON(clk->usecount <= 1 && !(clk->flags & CLK_WARNED))) {
+		pr_err("unbalanced clk_disable()\n");
+		clk->flags |= CLK_WARNED;
+	}
+	clk->usecount--;
 }
 EXPORT_SYMBOL(clk_disable);
 
diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h
index 592c9ab..285ca6b 100644
--- a/arch/arm/mach-mxs/include/mach/clock.h
+++ b/arch/arm/mach-mxs/include/mach/clock.h
@@ -25,12 +25,18 @@
 
 struct module;
 
+enum clk_flags {
+	CLK_WARNED = 0x01,
+};
+
 struct clk {
 	int id;
 	/* Source clock this clk depends on */
 	struct clk *parent;
 	/* Reference count of clock enable/disable */
 	__s8 usecount;
+	/* Reference count of clock prepare/unprepare */
+	__s8 prepared;
 	/* Register bit position for clock's enable/disable control. */
 	u8 enable_shift;
 	/* Register address for clock's enable/disable control. */
-- 
1.7.2.5



From shawn.guo at linaro.org  Thu Mar 22 04:34:59 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 22 Mar 2012 16:34:59 +0800
Subject: [PATCH] ARM: mxs: enforce semantics of
 clk_prepare()/clk_unprepare() and clk_enable()/clk_disable()
In-Reply-To: <1332404298-18891-1-git-send-email-LW@KARO-electronics.de>
References: <1332404298-18891-1-git-send-email-LW@KARO-electronics.de>
Message-ID: <20120322083457.GE2213@S2101-09.ap.freescale.net>

On Thu, Mar 22, 2012 at 09:18:17AM +0100, Lothar Wa?mann wrote:
> After introducing clk_prepare()/clk_unprepare() there may still be
> drivers out there that don't use the new functions.
> This patch warns about drivers calling clk_enable() without a
> preceding clk_prepare() and various other invalid sequences of calls
> to clk_enable()/clk_disable() and clk_prepare()/clk_unprepare().
> 

I plan to migrate the mxs clock driver to common clk framework in the
next merge window.  Thus, I do not see much point to take this patch.

> To not make a system unusable due to excessive warning messages the
> warnings are limited to 1 per clk by a flag in the 'flags' member of
> struct clk.
> 
> 
> Signed-off-by: Lothar Wa?mann <LW at KARO-electronics.de>
> ---
>  arch/arm/mach-mxs/clock.c              |   98 ++++++++++++++++++++++++++++----
>  arch/arm/mach-mxs/include/mach/clock.h |    6 ++
>  2 files changed, 93 insertions(+), 11 deletions(-)

-- 
Regards,
Shawn


From ludovic.desroches at atmel.com  Thu Mar 22 04:57:37 2012
From: ludovic.desroches at atmel.com (Ludovic Desroches)
Date: Thu, 22 Mar 2012 09:57:37 +0100
Subject: [PATCH 1/3] mmc: atmel-mci: correct data timeout computation
In-Reply-To: <4F6A011C.3000900@mvista.com>
References: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
 <1332344483-3915-2-git-send-email-ludovic.desroches@atmel.com>
 <4F6A011C.3000900@mvista.com>
Message-ID: <20120322085736.GM11834@ldesroches-Latitude-E6320>

Hello Sergei,

On Wed, Mar 21, 2012 at 07:26:04PM +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 03/21/2012 06:41 PM, ludovic.desroches at atmel.com wrote:
> 
> >From: Ludovic Desroches<ludovic.desroches at atmel.com>
> 
> >The HSMCI operates at a rate of up to Master Clock divided by two.
> 
> >Signed-off-by: Ludovic Desroches<ludovic.desroches at atmel.com>
> >---
> >  drivers/mmc/host/atmel-mci.c |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> >diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> >index e4449a5..e161452 100644
> >--- a/drivers/mmc/host/atmel-mci.c
> >+++ b/drivers/mmc/host/atmel-mci.c
> >@@ -480,7 +480,7 @@ err:
> >  static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
> >  					unsigned int ns)
> >  {
> >-	return (ns * (host->bus_hz / 1000000) + 999) / 1000;
> >+	return (ns * ((host->bus_hz/2) / 1000000) + 999) / 1000;
> 
>    Why don't you keep the notation by addign spaces around '/'?
>    BTW, could use DIV_ROUND_UP() here.
> 

Thanks for your comments. BTW I have realized (when testing values return using
DIV_ROUND_UP) that I may have another issue with this timeout calculation.
I will send a new patch.

Regards

Ludovic


From grant.likely at secretlab.ca  Wed Mar 21 10:34:37 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Wed, 21 Mar 2012 14:34:37 +0000
Subject: [PATCH v4 RESEND 0/7] gpio/omap: Some more driver fixes
In-Reply-To: <87haxj17xq.fsf@ti.com>
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
 <20120320143544.AA6E93E2834@localhost> <87haxj17xq.fsf@ti.com>
Message-ID: <20120321143437.8AF563E0648@localhost>

On Tue, 20 Mar 2012 10:46:57 -0700, Kevin Hilman <khilman at ti.com> wrote:
> Hi Grant,
> 
> Grant Likely <grant.likely at secretlab.ca> writes:
> 
> > On Tue, 20 Mar 2012 16:23:12 +0530, Tarun Kanti DebBarma <tarun.kanti at ti.com> wrote:
> >> This series excludes the cleanup patches as suggested by Kevin from
> >> the previously posted series.
> >> 
> >> The fixes include correction of _set_gpio_irqenable() implementation,
> >> missing wakeup_en register update in set_gpio_wakeup(), type mismatch
> >> of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
> >> register update in set_gpio_dataout_() and few corrections in context
> >> save logic.
> >> 
> >> It is baselined on top of:
> >> git://git.secretlab.ca/git/linux-2.6.git gpio/next
> >> Commit: 81b279d80a63628e580c71a31d30a8c3b3047ad4
> >> 
> >> Series is available here for reference:
> >> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_more_fixes
> >
> > Merged; thanks
> 
> Can you hold off slightly before merging this.
> 
> I haven't been through v4 yet or tested the fixes alone now that they're
> separated from the other cleanups.
> 
> Expect a pull request from me when ready.

Okay.  It's in linux-next at the moment, but I'll pull it back out.

g.



From u.kleine-koenig at pengutronix.de  Thu Mar 22 05:29:23 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 22 Mar 2012 10:29:23 +0100
Subject: [PATCH v2] ARM: davinci: implement DEBUG_LL port choice
In-Reply-To: <DF0F476B391FA8409C78302C7BA518B631800A8C@DBDE01.ent.ti.com>
References: <DF0F476B391FA8409C78302C7BA518B631800A8C@DBDE01.ent.ti.com>
Message-ID: <1332408563-18444-1-git-send-email-u.kleine-koenig@pengutronix.de>

Apart from the necessity to do this change for multi-platform kernels
the previous logic depended on the zImage decompressor to write the
physical and virtual address to a magic memory location.
If the decompressor is unused or not correctly configured for the
current machid, the addruart macro was an infinite loop. Moreover
debugging the early zImage code was not possible either.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
Changes since (implicit) v1:
 - add closing " to description strings
 - remove debug setting for unmainlined machine id in uncompress.h

 arch/arm/Kconfig.debug                           |   16 ++++++
 arch/arm/mach-davinci/include/mach/debug-macro.S |   58 ++++++++--------------
 arch/arm/mach-davinci/include/mach/hardware.h    |    2 +-
 arch/arm/mach-davinci/include/mach/serial.h      |   10 ----
 arch/arm/mach-davinci/include/mach/uncompress.h  |   24 ++-------
 5 files changed, 43 insertions(+), 67 deletions(-)

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e0d236d..4c2fb44 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -108,6 +108,22 @@ choice
 		bool "Kernel low-level debugging on 9263, 9g45 and cap9"
 		depends on HAVE_AT91_DBGU1
 
+	config DEBUG_DAVINCI_UART0
+		bool "Kernel low-level debugging on Davinci using uart0"
+		depends on ARCH_DAVINCI_DM644x
+
+	config DEBUG_DA8XX_UART1
+		bool "Kernel low-level debugging on DA8xx using uart1"
+		depends on ARCH_DAVINCI_DA8XX
+
+	config DEBUG_DA8XX_UART2
+		bool "Kernel low-level debugging on DA8xx using uart2"
+		depends on ARCH_DAVINCI_DA8XX
+
+	config DEBUG_TNETV107X_UART1
+		bool "Kernel low-level debugging on TNETV107x using uart1"
+		depends on ARCH_DAVINCI_TNETV107X
+
 	config DEBUG_FOOTBRIDGE_COM1
 		bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
 		depends on FOOTBRIDGE
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index cf94552..9c08295 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -22,46 +22,28 @@
 
 #define UART_SHIFT	2
 
-		.pushsection .data
-davinci_uart_phys:	.word	0
-davinci_uart_virt:	.word	0
-		.popsection
-
-		.macro addruart, rp, rv, tmp
-
-		/* Use davinci_uart_phys/virt if already configured */
-10:		adr	\rp, 99f		@ get effective addr of 99f
-		ldr	\rv, [\rp]		@ get absolute addr of 99f
-		sub	\rv, \rv, \rp		@ offset between the two
-		ldr	\rp, [\rp, #4]		@ abs addr of omap_uart_phys
-		sub	\tmp, \rp, \rv		@ make it effective
-		ldr	\rp, [\tmp, #0]		@ davinci_uart_phys
-		ldr	\rv, [\tmp, #4]		@ davinci_uart_virt
-		cmp	\rp, #0			@ is port configured?
-		cmpne	\rv, #0
-		bne	100f			@ already configured
-
-		/* Check the debug UART address set in uncompress.h */
-		and	\rp, pc, #0xff000000
-		ldr	\rv, =DAVINCI_UART_INFO_OFS
-		add	\rp, \rp, \rv
-
-		/* Copy uart phys address from decompressor uart info */
-		ldr	\rv, [\rp, #0]
-		str	\rv, [\tmp, #0]
-
-		/* Copy uart virt address from decompressor uart info */
-		ldr	\rv, [\rp, #4]
-		str	\rv, [\tmp, #4]
-
-		b	10b
+#if defined(CONFIG_DEBUG_DAVINCI_UART0)
+#define UART_BASE	DAVINCI_UART0_BASE
+#elif defined(CONFIG_DEBUG_DA8XX_UART0)
+#define UART_BASE	DA8XX_UART0_BASE
+#elif defined(CONFIG_DEBUG_DA8XX_UART1)
+#define UART_BASE	DA8XX_UART1_BASE
+#elif defined(CONFIG_DEBUG_DA8XX_UART2)
+#define UART_BASE	DA8XX_UART2_BASE
+#elif defined(CONFIG_DEBUG_TNETV107X_UART1)
+#define UART_BASE	TNETV107X_UART2_BASE
+#define UART_VIRTBASE	TNETV107X_UART2_VIRT
+#else
+#error "Select a specifc port for DEBUG_LL"
+#endif
 
-		.align
-99:		.word	.
-		.word	davinci_uart_phys
-		.ltorg
+#ifndef UART_VIRTBASE
+#define UART_VIRTBASE IO_ADDRESS(UART_BASE)
+#endif
 
-100:
+		.macro addruart, rp, rv, tmp
+		ldr     \rp, =UART_BASE
+		ldr     \rv, =UART_VIRTBASE
 		.endm
 
 		.macro	senduart,rd,rx
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 414e0b9..649ddc2 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -24,7 +24,7 @@
 /*
  * I/O mapping
  */
-#define IO_PHYS				0x01c00000UL
+#define IO_PHYS				UL(0x01c00000)
 #define IO_OFFSET			0xfd000000 /* Virtual IO = 0xfec00000 */
 #define IO_SIZE				0x00400000
 #define IO_VIRT				(IO_PHYS + IO_OFFSET)
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index e347d88..46b3cd1 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -15,16 +15,6 @@
 
 #include <mach/hardware.h>
 
-/*
- * Stolen area that contains debug uart physical and virtual addresses.  These
- * addresses are filled in by the uncompress.h code, and are used by the debug
- * macros in debug-macro.S.
- *
- * This area sits just below the page tables (see arch/arm/kernel/head.S).
- * We define it as a relative offset from start of usable RAM.
- */
-#define DAVINCI_UART_INFO_OFS	0x3ff8
-
 #define DAVINCI_UART0_BASE	(IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE	(IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE	(IO_PHYS + 0x20800)
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 9dc7cf9..0ff7363 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -41,37 +41,25 @@ static inline void flush(void)
 		barrier();
 }
 
-static inline void set_uart_info(u32 phys, void * __iomem virt)
+static inline void set_uart_info(u32 phys)
 {
-	/*
-	 * Get address of some.bss variable and round it down
-	 * a la CONFIG_AUTO_ZRELADDR.
-	 */
-	u32 ram_start = (u32)&uart & 0xf8000000;
-	u32 *uart_info = (u32 *)(ram_start + DAVINCI_UART_INFO_OFS);
-
 	uart = (u32 *)phys;
-	uart_info[0] = phys;
-	uart_info[1] = (u32)virt;
 }
 
-#define _DEBUG_LL_ENTRY(machine, phys, virt)			\
+#define _DEBUG_LL_ENTRY(machine, phys)				\
 	if (machine_is_##machine()) {				\
-		set_uart_info(phys, virt);			\
+		set_uart_info(phys);				\
 		break;						\
 	}
 
 #define DEBUG_LL_DAVINCI(machine, port)				\
-	_DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE,	\
-			IO_ADDRESS(DAVINCI_UART##port##_BASE))
+	_DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE)
 
 #define DEBUG_LL_DA8XX(machine, port)				\
-	_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE,	\
-			IO_ADDRESS(DA8XX_UART##port##_BASE))
+	_DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
 
 #define DEBUG_LL_TNETV107X(machine, port)			\
-	_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE,	\
-			TNETV107X_UART##port##_VIRT)
+	_DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE)
 
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
-- 
1.7.9.1



From u.kleine-koenig at pengutronix.de  Thu Mar 22 05:33:55 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 22 Mar 2012 10:33:55 +0100
Subject: [PATCH] ARM: davinci: make all struct davinci_uart_config const and
 __initconst
Message-ID: <1332408835-22030-1-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
Hello,

I'm not sure it's worth to do this because I guess it becomes obsolete when
davinci is converted to dt. But as I did the patch and I don't know
when/if davinci is converted I'm sending it anyhow.

Best regards
Uwe

 arch/arm/mach-davinci/board-da830-evm.c     |    2 +-
 arch/arm/mach-davinci/board-da850-evm.c     |    2 +-
 arch/arm/mach-davinci/board-dm355-evm.c     |    2 +-
 arch/arm/mach-davinci/board-dm355-leopard.c |    2 +-
 arch/arm/mach-davinci/board-dm365-evm.c     |    2 +-
 arch/arm/mach-davinci/board-dm644x-evm.c    |    2 +-
 arch/arm/mach-davinci/board-dm646x-evm.c    |    2 +-
 arch/arm/mach-davinci/board-mityomapl138.c  |    2 +-
 arch/arm/mach-davinci/board-neuros-osd2.c   |    2 +-
 arch/arm/mach-davinci/board-omapl138-hawk.c |    3 ++-
 arch/arm/mach-davinci/board-sffsdr.c        |    2 +-
 arch/arm/mach-davinci/include/mach/serial.h |    2 +-
 arch/arm/mach-davinci/serial.c              |    2 +-
 13 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index dc1afe5..a4976dc 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -185,7 +185,7 @@ static __init void da830_evm_usb_init(void)
 			   __func__, ret);
 }
 
-static struct davinci_uart_config da830_evm_uart_config __initdata = {
+static const struct davinci_uart_config da830_evm_uart_config __initconst = {
 	.enabled_uarts = 0x7,
 };
 
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index d508890..1ca1e56 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -734,7 +734,7 @@ static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
 	.bus_delay	= 0,	/* usec */
 };
 
-static struct davinci_uart_config da850_evm_uart_config __initdata = {
+static const struct davinci_uart_config da850_evm_uart_config __initconst = {
 	.enabled_uarts = 0x7,
 };
 
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 275341f..e5ebe57 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -246,7 +246,7 @@ static struct platform_device *davinci_evm_devices[] __initdata = {
 	&davinci_nand_device,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
+static const struct davinci_uart_config uart_config __initconst = {
 	.enabled_uarts = (1 << 0),
 };
 
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index e99db28..f21e2d4 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -171,7 +171,7 @@ static struct platform_device *davinci_leopard_devices[] __initdata = {
 	&davinci_nand_device,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
+static const struct davinci_uart_config uart_config __initconst = {
 	.enabled_uarts = (1 << 0),
 };
 
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 849311d..35cecc0 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -557,7 +557,7 @@ fail:
 	/* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
 }
 
-static struct davinci_uart_config uart_config __initdata = {
+static const struct davinci_uart_config uart_config __initconst = {
 	.enabled_uarts = (1 << 0),
 };
 
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 1247ecd..8e204e1 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -617,7 +617,7 @@ static struct platform_device *davinci_evm_devices[] __initdata = {
 	&rtc_dev,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
+static const struct davinci_uart_config uart_config __initconst = {
 	.enabled_uarts = (1 << 0),
 };
 
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 872ac69..d4b7b53 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -732,7 +732,7 @@ static void __init davinci_map_io(void)
 	cdce_clk_init();
 }
 
-static struct davinci_uart_config uart_config __initdata = {
+static const struct davinci_uart_config uart_config __initconst = {
 	.enabled_uarts = (1 << 0),
 };
 
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 672d820..9432ae2 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -434,7 +434,7 @@ static void __init mityomapl138_setup_nand(void)
 				 ARRAY_SIZE(mityomapl138_devices));
 }
 
-static struct davinci_uart_config mityomapl138_uart_config __initdata = {
+static const struct davinci_uart_config mityomapl138_uart_config __initconst = {
 	.enabled_uarts = 0x7,
 };
 
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 8d34f51..adaf8cd 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -152,7 +152,7 @@ static struct platform_device *davinci_ntosd2_devices[] __initdata = {
 	&ntosd2_leds_dev,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
+static const struct davinci_uart_config uart_config __initconst = {
 	.enabled_uarts = (1 << 0),
 };
 
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 45e8157..5f5e0ac 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -293,7 +293,8 @@ usb11_setup_oc_fail:
 	gpio_free(DA850_USB1_VBUS_PIN);
 }
 
-static struct davinci_uart_config omapl138_hawk_uart_config __initdata = {
+static const struct davinci_uart_config
+		omapl138_hawk_uart_config __initconst = {
 	.enabled_uarts = 0x7,
 };
 
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 31da3c5..0fdd0cb 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -124,7 +124,7 @@ static struct platform_device *davinci_sffsdr_devices[] __initdata = {
 	&davinci_sffsdr_nandflash_device,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
+static const struct davinci_uart_config uart_config __initconst = {
 	.enabled_uarts = (1 << 0),
 };
 
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 46b3cd1..2429aee 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -42,7 +42,7 @@ struct davinci_uart_config {
 	unsigned int enabled_uarts;
 };
 
-extern int davinci_serial_init(struct davinci_uart_config *);
+extern int davinci_serial_init(const struct davinci_uart_config *);
 #endif
 
 #endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 1875740..0d054c4 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -70,7 +70,7 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p)
 				 UART_DM646X_SCR_TX_WATERMARK);
 }
 
-int __init davinci_serial_init(struct davinci_uart_config *info)
+int __init davinci_serial_init(const struct davinci_uart_config *info)
 {
 	int i;
 	char name[16];
-- 
1.7.9.1



From javier.martin at vista-silicon.com  Thu Mar 22 05:39:39 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Thu, 22 Mar 2012 10:39:39 +0100
Subject: [PATCH v3 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <1332344363.19804.12.camel@vkoul-udesk3>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
 <1332344363.19804.12.camel@vkoul-udesk3>
Message-ID: <CACKLOr03tTymT1vdTH7=nqEHu3OvAinPUHEusK+mR+J6Yc35mQ@mail.gmail.com>

On 21 March 2012 16:39, Vinod Koul <vinod.koul at linux.intel.com> wrote:
> On Fri, 2012-03-09 at 16:20 +0100, Javier Martin wrote:
>> The following series have to be applied on top of the following patches:
>> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
>> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
>>
>> As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
>> is deprecated and no new patches are accepted for it.
>>
>> This series merges this code into the imx-dma.c dmaengine driver.
>>
>> Notes for v3:
>> ?- I send the whole series again despite some patches being the same. I think
>> ?this is more comfortable for Vinod than just sending those patches that have
>> ?been modified.
>> ?- I've generated my series with the following command this time:
>> ?'git format-patch -s -13 -M -B --subject-prefix="PATCH v3"' as suggested by
>> ?Sascha but still removing two files in 01/13 generates a lot of noisy diffs.
>> ?Sorry about that.
>> ?- I don't include Sascha's Tested-by since maybe he wants to test this last
>> ?version.
> This doesn't apply for me (starting with 6th) on current slave-dma.next
> due to obvious changes which have gone into imx.
>
> Can you quickly rebase the series and resend.

Great,
now your 'next' branch is actually broken for imx-dma.

I'm currently trying a bisect to find out what is the commit
responsible for that but I suspect it will be related to the cookie
changes submitted by Russell.

-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From prylowski at metasoft.pl  Thu Mar 22 06:00:37 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Thu, 22 Mar 2012 11:00:37 +0100
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <4F6A78ED.3050403@gmail.com>
References: <4F683B36.8090101@metasoft.pl> <4F6A78ED.3050403@gmail.com>
Message-ID: <4F6AF845.9070209@metasoft.pl>

On 2012-03-22 01:57, Ryan Mallon wrote:
> I haven't looked through the patch yet, since I'm waiting on more
> information from Mika and Hartley's testing.
> 
> However, the commit log doesn't tell me why we want this change. Is it a
> performance improvement? If so, do you have some numbers that we can
> paste into the commit log?

In principle, using double buffering should be faster than using only
one buffer and disabling/enabling channel each time. But my measurements
doesn't show any significant change.

The real reason for this change is that current code is not 100% reliable
in IDE-DMA (I'm planning to submit ep93xx ide driver to linux-ide soon).
Although using only one buffer and DONE interrupt is simple, surprisingly
we can get interrupt when M2M DMA is in DMA_BUF_ON and DMA_STALL state.
If we disable the channel at this moment, we end with ata timeout.


From prylowski at metasoft.pl  Thu Mar 22 06:16:57 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Thu, 22 Mar 2012 11:16:57 +0100
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>
References: <4F683B36.8090101@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>
Message-ID: <4F6AFC19.9040003@metasoft.pl>

On 2012-03-21 18:12, H Hartley Sweeten wrote:
> Hmm... This isn't working on my ep9307 board...
> 
> When the system boots I get stormed with messages:
> 
> dma dma1chan0: unknown interrupt!
> dma dma1chan0: unknown interrupt!
> dma dma1chan0: unknown interrupt!
> dma dma1chan1: unknown interrupt!
> dma dma1chan1: unknown interrupt!
> dma dma1chan1: unknown interrupt!
> dma dma1chan0: unknown interrupt!
> dma dma1chan0: unknown interrupt!
> dma dma1chan1: unknown interrupt!
> 
> Note, I have use_dma set for the ep93xx_spi driver and am using mmc_spi.

Thanks for testing. Unfortunately, I'm unable to test this patch with SPI,
because my hardware uses it only for very simple communication (one byte
commands, I noticed that DMA is not used in this case, even if enabled).

In current mainline I also get these messages:

dma dma1chan0: unknown interrupt!
dma dma1chan1: got interrupt while active list is empty

With my patch applied they happen more often (maybe because NFB interrupt
is enabled), but the system is usable. Changing kernel to 3.2.x or using
hack proposed by Mika makes the problem is gone.



From kumarrav at codeaurora.org  Thu Mar 22 06:51:36 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Thu, 22 Mar 2012 16:21:36 +0530
Subject: [PATCH v4 0/2] Add Qualcomm MSM ADM DMAEngine driver 
Message-ID: <1332413496-8246-1-git-send-email-kumarrav@codeaurora.org>

Following are the changes we have done from the previous
v1 posted here: https://lkml.org/lkml/2011/12/22/148

As our ADM Scatter-gather hardware needs
-32-bit command configuration parameter
 apart from
-32-bit source address
-32-bit destination address
-16-bit length

So,we have added new parameter in struct scatterlist to support xfer descriptor
specific private data, and for supporting ADM Box mode DMA we added new
API and data structure.

Changes done from v2:

As per our previous discussion you had suggested us to follow the below patch
https://lkml.org/lkml/2012/1/26/405
Please check the below link of our discussion
https://lkml.org/lkml/2012/1/30/48

So we have added the new context parameter in device_prep_dma_sg and
device_prep_interleave_dma API's to support for passing client channel specific
private data associated with every transfer descriptor.

We are using
Interleaved API for BOX type transfer.
SG API for SG type transfer.

Changes done from v3:

Implemented the wrappers as suggested by Russell King in following patch
https://lkml.org/lkml/2012/2/3/269
Fixed the dmaengine & client drivers to follow above changes

Ravi Kumar V (2):
  dmaengine: Add context parameter to prep_dma_sg and
    prep_interleaved_dma
  DMAEngine: Add DMAEngine driver based on old MSM ADM DMA APIs

 arch/arm/mach-msm/include/mach/dma.h    |   35 ++
 drivers/dma/Kconfig                     |   12 +
 drivers/dma/Makefile                    |    1 +
 drivers/dma/fsldma.c                    |    2 +-
 drivers/dma/msm_adm_dma.c               |  728 +++++++++++++++++++++++++++++++
 drivers/dma/sirf-dma.c                  |    2 +-
 drivers/dma/ste_dma40.c                 |    2 +-
 drivers/misc/carma/carma-fpga-program.c |    2 +-
 drivers/misc/carma/carma-fpga.c         |    7 +-
 include/linux/dmaengine.h               |   22 +-
 10 files changed, 803 insertions(+), 10 deletions(-)
 create mode 100644 drivers/dma/msm_adm_dma.c

-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From kumarrav at codeaurora.org  Thu Mar 22 06:54:52 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Thu, 22 Mar 2012 16:24:52 +0530
Subject: [PATCH v4 1/2] dmaengine: Add context parameter to prep_dma_sg and
 prep_interleaved_dma
Message-ID: <1332413692-8312-1-git-send-email-kumarrav@codeaurora.org>

Add new context parameter to DMA SG and Interleaveid mode for passing
per transfer specific private data, using this it enables the
dma devices which needs to pass the parameters which changes per
each transfer

Change-Id: Ia9ee19f2c253e68b8e5ff254a57478dcc51014ca
Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
---
 drivers/dma/fsldma.c                    |    2 +-
 drivers/dma/sirf-dma.c                  |    2 +-
 drivers/dma/ste_dma40.c                 |    2 +-
 drivers/misc/carma/carma-fpga-program.c |    2 +-
 drivers/misc/carma/carma-fpga.c         |    7 +++----
 include/linux/dmaengine.h               |   22 ++++++++++++++++++++--
 6 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index b98070c..f9f77db 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -645,7 +645,7 @@ fail:
 static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
 	struct scatterlist *dst_sg, unsigned int dst_nents,
 	struct scatterlist *src_sg, unsigned int src_nents,
-	unsigned long flags)
+	unsigned long flags, void *context)
 {
 	struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
 	struct fsldma_chan *chan = to_fsl_chan(dchan);
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 2333810..ff4d344 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -428,7 +428,7 @@ sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 
 static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
 	struct dma_chan *chan, struct dma_interleaved_template *xt,
-	unsigned long flags)
+	unsigned long flags, void *context)
 {
 	struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
 	struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index cc5ecbc..2f58ba9 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2287,7 +2287,7 @@ static struct dma_async_tx_descriptor *
 d40_prep_memcpy_sg(struct dma_chan *chan,
 		   struct scatterlist *dst_sg, unsigned int dst_nents,
 		   struct scatterlist *src_sg, unsigned int src_nents,
-		   unsigned long dma_flags)
+		   unsigned long dma_flags, void *context)
 {
 	if (dst_nents != src_nents)
 		return NULL;
diff --git a/drivers/misc/carma/carma-fpga-program.c b/drivers/misc/carma/carma-fpga-program.c
index a2d25e4..3739a12 100644
--- a/drivers/misc/carma/carma-fpga-program.c
+++ b/drivers/misc/carma/carma-fpga-program.c
@@ -530,7 +530,7 @@ static noinline int fpga_program_dma(struct fpga_dev *priv)
 	}
 
 	/* setup and submit the DMA transaction */
-	tx = chan->device->device_prep_dma_sg(chan,
+	tx = chan->device->dmaengine_prep_dma_sg(chan,
 					      table.sgl, num_pages,
 					      vb->sglist, vb->sglen, 0);
 	if (!tx) {
diff --git a/drivers/misc/carma/carma-fpga.c b/drivers/misc/carma/carma-fpga.c
index 14e974b2..be0baf6 100644
--- a/drivers/misc/carma/carma-fpga.c
+++ b/drivers/misc/carma/carma-fpga.c
@@ -638,10 +638,9 @@ static int data_submit_dma(struct fpga_device *priv, struct data_buf *buf)
 	 */
 
 	/* setup the scatterlist to scatterlist transfer */
-	tx = chan->device->device_prep_dma_sg(chan,
-					      dst_sg, dst_nents,
-					      src_sg, src_nents,
-					      0);
+	tx = dmaengine_prep_dma_sg(chan, dst_sg, dst_nents,
+					 src_sg, src_nents,
+					 0);
 	if (!tx) {
 		dev_err(priv->dev, "unable to prep scatterlist DMA\n");
 		return -ENOMEM;
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 679b349..68a57da 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -570,7 +570,7 @@ struct dma_device {
 		struct dma_chan *chan,
 		struct scatterlist *dst_sg, unsigned int dst_nents,
 		struct scatterlist *src_sg, unsigned int src_nents,
-		unsigned long flags);
+		unsigned long flags, void *context);
 
 	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
 		struct dma_chan *chan, struct scatterlist *sgl,
@@ -581,7 +581,7 @@ struct dma_device {
 		size_t period_len, enum dma_transfer_direction direction);
 	struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
 		struct dma_chan *chan, struct dma_interleaved_template *xt,
-		unsigned long flags);
+		unsigned long flags, void *context);
 	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		unsigned long arg);
 
@@ -615,6 +615,24 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
 	return chan->device->device_prep_slave_sg(chan, &sg, 1, dir, flags);
 }
 
+static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
+			struct dma_chan *chan, struct scatterlist *dst_sg,
+			unsigned int dst_nents,	struct scatterlist *src_sg,
+			unsigned int src_nents,	unsigned long flags)
+{
+	return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents,
+					src_sg, src_nents, flags, NULL);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
+			struct dma_chan *chan,
+			struct dma_interleaved_template *xt,
+			unsigned long flags)
+{
+	return chan->device->device_prep_interleaved_dma(chan, xt,
+							flags, NULL);
+}
+
 static inline int dmaengine_terminate_all(struct dma_chan *chan)
 {
 	return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From kumarrav at codeaurora.org  Thu Mar 22 06:55:36 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Thu, 22 Mar 2012 16:25:36 +0530
Subject: [PATCH 2/2] DMAEngine: Add DMAEngine driver based on old MSM ADM DMA
 APIs
Message-ID: <1332413736-8379-1-git-send-email-kumarrav@codeaurora.org>

Add DMAEngine based driver using the old MSM ADM DMA APIs internally.
The benefit of this approach is that not all the drivers
have to get converted to DMAEngine APIs simultaneosly while
both the drivers can stay enabled in the kernel. The client
drivers using the old MSM APIs directly can now convert to
DMAEngine one by one.

Change-Id: I3647ed7b8c73b3078dfa8877a3560db3cb0a2373
Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
---
 arch/arm/mach-msm/include/mach/dma.h |   35 ++
 drivers/dma/Kconfig                  |   12 +
 drivers/dma/Makefile                 |    1 +
 drivers/dma/msm_adm_dma.c            |  728 ++++++++++++++++++++++++++++++++++
 4 files changed, 776 insertions(+), 0 deletions(-)
 create mode 100644 drivers/dma/msm_adm_dma.c

diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 05583f5..95b7b15 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -18,6 +18,36 @@
 #include <linux/list.h>
 #include <mach/msm_iomap.h>
 
+#define sg_dma_offset(sg)               ((sg)->offset)
+#define box_dma_row_address(box)        ((box)->dma_row_address)
+#define box_dma_row_len(box)            ((box)->dma_row_len)
+#define box_dma_row_num(box)            ((box)->dma_row_num)
+#define box_dma_row_offset(box)         ((box)->dma_row_offset)
+
+#define MSM_DMA_CMD_MASK		0x9FFF8
+#define MSM_DMA_CMD_SHIFT		0
+#define MSM_BOX_SRC_RLEN_MASK		0xFFFF
+#define MSM_BOX_SRC_RLEN_SHIFT		16
+#define MSM_BOX_SRC_RNUM_MASK		0xFFFF
+#define MSM_BOX_SRC_RNUM_SHIFT		16
+#define MSM_BOX_SRC_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_SRC_ROFFSET_SHIFT	16
+#define MSM_BOX_DST_RLEN_MASK		0xFFFF
+#define MSM_BOX_DST_RNUM_MASK		0xFFFF
+#define MSM_BOX_DST_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_MODE_CMD		0x3
+
+enum adm_flush_type {
+	ADM_FORCED_FLUSH,
+	ADM_GRACEFUL_FLUSH,
+};
+
+enum adm_dma_type {
+	ADM_SINGLE_MODE,
+	ADM_SG_MODE,
+	ADM_BOX_MODE,
+};
+
 struct msm_dmov_errdata {
 	uint32_t flush[6];
 };
@@ -32,6 +62,11 @@ struct msm_dmov_cmd {
 	void *data;
 };
 
+struct msm_adm_cmd_config {
+	uint32_t num_cmd;
+	uint32_t *cmd_cntrl;
+};
+
 #ifndef CONFIG_ARCH_MSM8X60
 void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
 void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f1a2749..1f99362 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -252,6 +252,18 @@ config EP93XX_DMA
 	help
 	  Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
 
+config MSM_ADM_DMA
+	tristate "Qualcomm MSM ADM DMA support"
+	depends on ARCH_MSM
+	select DMA_ENGINE
+	help
+	  Support the Qualcomm DMA engine. This engine is integrated into
+	  Qualcomm chips.
+
+	  Say Y here if you have such a chipset.
+
+	  If unsure, say N.
+
 config DMA_ENGINE
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 009a222..f55fb57 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
 obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
 obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
 obj-$(CONFIG_IMX_DMA) += imx-dma.o
+obj-$(CONFIG_MSM_ADM_DMA) += msm_adm_dma.o
 obj-$(CONFIG_MXS_DMA) += mxs-dma.o
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
diff --git a/drivers/dma/msm_adm_dma.c b/drivers/dma/msm_adm_dma.c
new file mode 100644
index 0000000..f5bbdc5
--- /dev/null
+++ b/drivers/dma/msm_adm_dma.c
@@ -0,0 +1,728 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/dmapool.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/dma.h>
+
+#define SD3_CHAN_START			0
+#define MSM_DMOV_CRCI_COUNT		16
+#define MSM_DMA_MAX_CHANS_PER_DEVICE	16
+#define MAX_TRANSFER_LENGTH		65535
+#define NO_ERR_CHAN_STATUS		0x80000002
+#define to_msm_chan(chan) container_of(chan, struct msm_dma_chan, channel)
+
+struct msm_dma_chan {
+	int chan_id;
+	dma_cookie_t completed_cookie;
+	dma_cookie_t error_cookie;
+	spinlock_t lock;
+	struct list_head active_list;
+	struct list_head pending_list;
+	struct dma_chan channel;
+	struct dma_pool *desc_pool;
+	struct device *dev;
+	int max_len;
+	int err;
+	struct tasklet_struct tasklet;
+};
+
+struct msm_dma_device {
+	void __iomem *base;
+	struct device *dev;
+	struct dma_device common;
+	struct msm_dma_chan *chan[MSM_DMA_MAX_CHANS_PER_DEVICE];
+};
+
+struct msm_dma_desc_hw {
+	unsigned int cmd_list_ptr;
+} __aligned(8);
+
+/* Single Item Mode */
+struct adm_cmd_t {
+	unsigned int cmd_cntrl;
+	unsigned int src;
+	unsigned int dst;
+	unsigned int len;
+};
+
+struct adm_box_cmd_t {
+	uint32_t cmd_cntrl;
+	uint32_t src_row_addr;
+	uint32_t dst_row_addr;
+	uint32_t src_dst_len;
+	uint32_t num_rows;
+	uint32_t row_offset;
+};
+
+struct msm_dma_desc_sw {
+	struct msm_dma_desc_hw hw;
+	struct adm_cmd_t *vaddr_cmd;
+	struct adm_box_cmd_t *vaddr_box_cmd;
+	size_t coherent_size;
+	dma_addr_t paddr_cmd_list;
+	struct list_head node;
+	struct msm_dmov_cmd dmov_cmd;
+	struct dma_async_tx_descriptor async_tx;
+} __aligned(8);
+
+static int msm_dma_alloc_chan_resources(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+
+	/* Has this channel already been allocated? */
+	if (chan->desc_pool)
+		return 1;
+
+	/*
+	 * We need the descriptor to be aligned to 8bytes
+	 * for meeting ADM specification requirement.
+	 */
+	chan->desc_pool = dma_pool_create("msm_dma_desc_pool",
+					chan->dev,
+					sizeof(struct msm_dma_desc_sw),
+				__alignof__(struct msm_dma_desc_sw), 0);
+	if (!chan->desc_pool) {
+		dev_err(chan->dev, "unable to allocate channel %d "
+				"descriptor pool\n", chan->chan_id);
+		return -ENOMEM;
+	}
+
+	chan->completed_cookie = 1;
+	dchan->cookie = 1;
+
+	/* there is at least one descriptor free to be allocated */
+	return 1;
+}
+
+static void msm_dma_free_desc_list(struct msm_dma_chan *chan,
+						struct list_head *list)
+{
+	struct msm_dma_desc_sw *desc, *_desc;
+
+	list_for_each_entry_safe(desc, _desc, list, node) {
+		list_del(&desc->node);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	}
+}
+
+static void msm_dma_free_chan_resources(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	unsigned long flags;
+
+	dev_dbg(chan->dev, "Free all channel resources.\n");
+	spin_lock_irqsave(&chan->lock, flags);
+	msm_dma_free_desc_list(chan, &chan->active_list);
+	msm_dma_free_desc_list(chan, &chan->pending_list);
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	dma_pool_destroy(chan->desc_pool);
+	chan->desc_pool = NULL;
+}
+
+static enum dma_status msm_dma_desc_status(struct msm_dma_chan *chan,
+					struct msm_dma_desc_sw *desc)
+{
+	return dma_async_is_complete(desc->async_tx.cookie,
+					chan->completed_cookie,
+					chan->channel.cookie);
+}
+
+static void msm_chan_desc_cleanup(struct msm_dma_chan *chan)
+{
+	struct msm_dma_desc_sw *desc, *_desc;
+	unsigned long flags;
+
+	dev_dbg(chan->dev, "Cleaning completed descriptor of channel %d\n",
+							chan->chan_id);
+	spin_lock_irqsave(&chan->lock, flags);
+
+	list_for_each_entry_safe(desc, _desc, &chan->active_list, node) {
+		dma_async_tx_callback callback;
+		void *callback_param;
+
+		if (msm_dma_desc_status(chan, desc) == DMA_IN_PROGRESS)
+			break;
+
+		/* Remove from the list of running transactions */
+		list_del(&desc->node);
+
+		/* Run the link descriptor callback function */
+		callback = desc->async_tx.callback;
+		callback_param = desc->async_tx.callback_param;
+		if (callback) {
+			spin_unlock_irqrestore(&chan->lock, flags);
+			callback(callback_param);
+			spin_lock_irqsave(&chan->lock, flags);
+		}
+
+		/* Run any dependencies, then free the descriptor */
+		dma_run_dependencies(&desc->async_tx);
+		spin_unlock_irqrestore(&chan->lock, flags);
+
+		if (desc->vaddr_cmd) {
+			dma_free_coherent(chan->dev, desc->coherent_size,
+						(void *)desc->vaddr_cmd,
+							desc->paddr_cmd_list);
+		} else {
+			dma_free_coherent(chan->dev, desc->coherent_size,
+						(void *)desc->vaddr_box_cmd,
+							desc->paddr_cmd_list);
+		}
+		spin_lock_irqsave(&chan->lock, flags);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	}
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+static void dma_do_tasklet(unsigned long data)
+{
+	struct msm_dma_chan *chan = (struct msm_dma_chan *)data;
+	msm_chan_desc_cleanup(chan);
+}
+
+static void
+msm_dma_complete_func(struct msm_dmov_cmd *cmd,
+				unsigned int result,
+				struct msm_dmov_errdata *err)
+{
+	unsigned long flags;
+	struct msm_dma_desc_sw *desch = container_of(cmd,
+				struct msm_dma_desc_sw, dmov_cmd);
+	struct msm_dma_chan *chan = to_msm_chan(desch->async_tx.chan);
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if ((result != NO_ERR_CHAN_STATUS) && err)
+		chan->error_cookie = desch->async_tx.cookie;
+	chan->completed_cookie = desch->async_tx.cookie;
+
+	tasklet_schedule(&chan->tasklet);
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+/*
+ *  Passes transfer descriptors to DMA hardware.
+ */
+static void msm_dma_issue_pending(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	struct msm_dma_desc_sw *desch;
+	unsigned long flags;
+
+	if (chan->err)
+		return;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if (list_empty(&chan->pending_list))
+		goto out_unlock;
+
+	desch = list_first_entry(&chan->pending_list, struct msm_dma_desc_sw,
+									node);
+	list_del(&desch->node);
+	desch->dmov_cmd.complete_func = msm_dma_complete_func;
+	desch->dmov_cmd.execute_func = NULL;
+	desch->dmov_cmd.cmdptr = DMOV_CMD_ADDR(desch->async_tx.phys);
+	list_add_tail(&desch->node, &chan->active_list);
+	mb();
+	msm_dmov_enqueue_cmd(chan->chan_id, &desch->dmov_cmd);
+out_unlock:
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+/*
+ *  Assignes cookie for each transfer descriptor passed.
+ *  Returns
+ *	Assigend cookie for success.
+ *	Error value for failure.
+ */
+static dma_cookie_t msm_dma_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	struct msm_dma_chan *chan = to_msm_chan(tx->chan);
+	struct msm_dma_desc_sw *desc = container_of(tx,
+	struct msm_dma_desc_sw, async_tx);
+	unsigned long flags;
+	dma_cookie_t cookie = -EBUSY;
+
+	if (chan->err)
+		return cookie;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	/*
+	 * assign cookies to all of the software descriptors
+	 * that make up this transaction
+	 */
+	cookie = chan->channel.cookie;
+	cookie++;
+	if (cookie < 0)
+		cookie = DMA_MIN_COOKIE;
+
+	desc->async_tx.cookie = cookie;
+	chan->channel.cookie = cookie;
+
+	/* put this transaction onto the tail of the pending queue */
+	list_add_tail(&desc->node, &chan->pending_list);
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	return cookie;
+}
+
+/*
+ *  Returns the DMA transfer status of a particular cookie
+ */
+static enum dma_status msm_tx_status(struct dma_chan *dchan,
+					dma_cookie_t cookie,
+				struct dma_tx_state *txstate)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	dma_cookie_t last_used;
+	dma_cookie_t last_complete;
+	enum dma_status status;
+
+	last_used = dchan->cookie;
+	last_complete = chan->completed_cookie;
+
+	dma_set_tx_state(txstate, last_complete, last_used, 0);
+
+	status = dma_async_is_complete(cookie, last_complete, last_used);
+
+	if (status != DMA_IN_PROGRESS)
+		if (chan->error_cookie == cookie)
+			status = DMA_ERROR;
+
+	return status;
+}
+
+static struct msm_dma_desc_sw *msm_dma_alloc_descriptor(
+				struct msm_dma_chan *chan,
+				int cmd_cnt,
+				enum adm_dma_type mask)
+{
+	struct msm_dma_desc_sw *desc;
+	dma_addr_t pdesc_addr;
+	dma_addr_t paddr_cmd_list;
+	void *err = NULL;
+
+	desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc_addr);
+	if (!desc) {
+		dev_dbg(chan->dev, "out of memory for desc\n");
+		return ERR_CAST(desc);
+	}
+
+	memset(desc, 0, sizeof(*desc));
+	desc->async_tx.phys = pdesc_addr;
+
+	if (mask == ADM_BOX_MODE) {
+		desc->coherent_size = sizeof(struct adm_box_cmd_t);
+		desc->vaddr_box_cmd = dma_alloc_coherent(chan->dev,
+				sizeof(struct adm_box_cmd_t),
+				&paddr_cmd_list, GFP_ATOMIC);
+		if (!desc->vaddr_box_cmd) {
+			dev_dbg(chan->dev, "out of memory for desc\n");
+			err = desc->vaddr_box_cmd;
+			goto fail;
+		}
+	} else {
+		desc->coherent_size = sizeof(struct adm_cmd_t)*cmd_cnt;
+
+		desc->vaddr_cmd = dma_alloc_coherent(chan->dev,
+				sizeof(struct adm_cmd_t)*cmd_cnt,
+				&paddr_cmd_list, GFP_ATOMIC);
+
+		if (!desc->vaddr_cmd) {
+			dev_dbg(chan->dev, "out of memory for desc\n");
+			err = desc->vaddr_cmd;
+			goto fail;
+		}
+	}
+
+	dma_async_tx_descriptor_init(&desc->async_tx, &chan->channel);
+	desc->async_tx.tx_submit = msm_dma_tx_submit;
+	desc->paddr_cmd_list = paddr_cmd_list;
+	desc->hw.cmd_list_ptr = (paddr_cmd_list >> 3) | CMD_PTR_LP;
+	return desc;
+fail:
+	dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	return ERR_CAST(err);
+}
+
+/*
+ *  Prepares the transfer descriptors for SG transaction.
+ *  Returns
+ *	address of dma_async_tx_descriptor for success.
+ *	Pointer of error value for failure.
+ */
+static struct dma_async_tx_descriptor *msm_dma_prep_sg(
+		struct dma_chan *dchan,
+		struct scatterlist *dst_sg, unsigned int dst_nents,
+		struct scatterlist *src_sg, unsigned int src_nents,
+		unsigned long flags, void *context)
+{
+
+	struct msm_dma_chan *chan;
+	struct msm_dma_desc_sw *new;
+	size_t copy, len;
+	int cmd_cnt = 0;
+	int first = 0;
+	int i;
+	dma_addr_t src;
+	dma_addr_t dst;
+	struct adm_cmd_t *cmdlist_vaddr;
+	struct scatterlist *sg;
+	struct msm_adm_cmd_config *cmd_config = context;
+
+	if (!dchan)
+		return ERR_PTR(-EINVAL);
+
+	if (dst_nents == 0 || src_nents == 0)
+		return ERR_PTR(-EINVAL);
+	if (!dst_sg || !src_sg)
+		return ERR_PTR(-EINVAL);
+
+	if ((dst_nents != src_nents) || (cmd_config->num_cmd != src_nents))
+		return ERR_PTR(-EINVAL);
+
+	chan = to_msm_chan(dchan);
+
+	cmd_cnt = src_nents;
+	for (i = 0; i < src_nents; i++) {
+		len = sg_dma_len(src_sg + i);
+		if (len != MAX_TRANSFER_LENGTH)
+			cmd_cnt += len/MAX_TRANSFER_LENGTH;
+	}
+
+	new = msm_dma_alloc_descriptor(chan, cmd_cnt, ADM_SG_MODE);
+
+	if (!new) {
+		dev_err(chan->dev,
+			"No free memory for link descriptor\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	cmdlist_vaddr = new->vaddr_cmd;
+
+	for_each_sg(src_sg, sg, src_nents, i) {
+		len = sg_dma_len(sg);
+		src = sg_dma_address(sg);
+		do {
+			copy = (len >= MAX_TRANSFER_LENGTH) ?
+						MAX_TRANSFER_LENGTH : len;
+			cmdlist_vaddr->src = src;
+			cmdlist_vaddr->len = copy;
+			cmdlist_vaddr->cmd_cntrl =
+					*(cmd_config->cmd_cntrl + i) &
+							MSM_DMA_CMD_MASK;
+			if (first == 0) {
+				if (cmd_cnt == 1)
+					cmdlist_vaddr->cmd_cntrl |= CMD_LC;
+				else
+					cmdlist_vaddr->cmd_cntrl |= CMD_OCB;
+				first = 1;
+			}
+			cmdlist_vaddr++;
+			len -= copy;
+			src += copy;
+		} while (len);
+	}
+	if (cmd_cnt > 1) {
+		cmdlist_vaddr--;
+		cmdlist_vaddr->cmd_cntrl |= CMD_LC | CMD_OCU;
+	}
+
+	cmdlist_vaddr = new->vaddr_cmd;
+
+	for_each_sg(dst_sg, sg, src_nents, i) {
+		len = sg_dma_len(sg);
+		dst = sg_dma_address(sg);
+		do {
+			copy = (len >= MAX_TRANSFER_LENGTH) ?
+					MAX_TRANSFER_LENGTH : len;
+			cmdlist_vaddr->dst = dst;
+			cmdlist_vaddr++;
+			len -= copy;
+			dst += copy;
+		} while (len);
+
+	}
+
+#ifdef DEBUG
+	cmdlist_vaddr = new->vaddr_cmd;
+	i = 0;
+	do {
+		dev_dbg(chan->dev, "cmd %d src 0x%x dst 0x%x len 0x%x "
+						"cntrl 0x%x\n",
+				i, cmdlist_vaddr->src, cmdlist_vaddr->dst,
+				cmdlist_vaddr->len, cmdlist_vaddr->cmd_cntrl);
+			cmdlist_vaddr++;
+	} while (!((cmdlist_vaddr-1)->cmd_cntrl & CMD_LC));
+#endif
+	new->async_tx.flags = flags;
+	new->async_tx.cookie = -EBUSY;
+
+	return &new->async_tx;
+}
+
+struct dma_async_tx_descriptor *msm_dma_prep_interleaved(
+				struct dma_chan *dchan,
+				struct dma_interleaved_template *xt,
+				unsigned long flags,
+				void *context)
+{
+
+	struct msm_dma_chan *chan;
+	struct msm_dma_desc_sw *new;
+	struct adm_box_cmd_t *box_cmd_vaddr;
+	struct msm_adm_cmd_config *cmd_config = context;
+
+	if (!dchan)
+		return ERR_PTR(-EINVAL);
+
+	if (!xt)
+		return ERR_PTR(-EINVAL);
+
+	chan = to_msm_chan(dchan);
+
+	new = msm_dma_alloc_descriptor(chan, 1, ADM_BOX_MODE);
+
+	if (!new) {
+		dev_err(chan->dev,
+			"No free memory for link descriptor\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	box_cmd_vaddr = new->vaddr_box_cmd;
+
+
+	box_cmd_vaddr->src_row_addr = xt->src_start;
+	box_cmd_vaddr->dst_row_addr = xt->dst_start;
+	box_cmd_vaddr->src_dst_len =
+			((xt->sgl[0].size & MSM_BOX_SRC_RLEN_MASK) <<
+					MSM_BOX_SRC_RLEN_SHIFT) |
+				(xt->sgl[0].size & MSM_BOX_DST_RLEN_MASK);
+
+	box_cmd_vaddr->cmd_cntrl =
+			(cmd_config->cmd_cntrl[0] & MSM_DMA_CMD_MASK) |
+						MSM_BOX_MODE_CMD | CMD_LC;
+
+	box_cmd_vaddr->num_rows =
+			((xt->numf & MSM_BOX_SRC_RNUM_MASK) <<
+			MSM_BOX_SRC_RNUM_SHIFT) |
+			(xt->numf & MSM_BOX_DST_RNUM_MASK);
+
+	if ((xt->src_sgl) && (xt->src_inc))
+		box_cmd_vaddr->row_offset =
+				((xt->sgl[0].size + xt->sgl[0].icg) &
+				MSM_BOX_SRC_ROFFSET_MASK) <<
+				MSM_BOX_SRC_ROFFSET_SHIFT;
+	else if ((!xt->src_sgl) && (xt->src_inc))
+		box_cmd_vaddr->row_offset = ((xt->sgl[0].size) &
+				MSM_BOX_SRC_ROFFSET_MASK) <<
+				MSM_BOX_SRC_ROFFSET_SHIFT;
+	else
+		box_cmd_vaddr->row_offset =
+			(0 & MSM_BOX_SRC_ROFFSET_MASK) <<
+			MSM_BOX_SRC_ROFFSET_SHIFT;
+
+
+	if ((xt->dst_sgl) && (xt->dst_inc))
+		box_cmd_vaddr->row_offset |=
+			((xt->sgl[0].size + xt->sgl[0].icg) &
+			MSM_BOX_DST_ROFFSET_MASK);
+	else if ((!xt->dst_sgl) && (xt->dst_inc))
+		box_cmd_vaddr->row_offset |= ((xt->sgl[0].size) &
+					MSM_BOX_DST_ROFFSET_MASK);
+	else
+		box_cmd_vaddr->row_offset |= (0 & MSM_BOX_DST_ROFFSET_MASK);
+
+	new->async_tx.flags = flags;
+	new->async_tx.cookie = -EBUSY;
+
+	return &new->async_tx;
+}
+
+/*
+ *  Controlling the hardware channel like stopping, flushing.
+ */
+static int msm_dma_chan_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+							unsigned long arg)
+{
+	enum adm_flush_type cmd_type = arg;
+
+	if (cmd == DMA_TERMINATE_ALL) {
+		switch (cmd_type) {
+		case ADM_GRACEFUL_FLUSH:
+				msm_dmov_stop_cmd(chan->chan_id, NULL, 1);
+			break;
+		case ADM_FORCED_FLUSH:
+			/*
+			 * We treate default as forced flush
+			 * so we fall through
+			 */
+		default:
+				msm_dmov_stop_cmd(chan->chan_id, NULL, 0);
+			break;
+		}
+	}
+	return 0;
+}
+
+static void msm_dma_chan_remove(struct msm_dma_chan *chan)
+{
+	tasklet_kill(&chan->tasklet);
+	list_del(&chan->channel.device_node);
+	kfree(chan);
+}
+
+static __devinit int msm_dma_chan_probe(struct msm_dma_device *qdev,
+					int channel)
+{
+	struct msm_dma_chan *chan;
+
+	chan = kzalloc(sizeof(*chan), GFP_KERNEL);
+	if (!chan) {
+		dev_err(qdev->dev, "no free memory for DMA channels!\n");
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&chan->lock);
+	INIT_LIST_HEAD(&chan->pending_list);
+	INIT_LIST_HEAD(&chan->active_list);
+
+	chan->chan_id = channel;
+	chan->completed_cookie = 0;
+	chan->channel.cookie = 0;
+	chan->max_len = MAX_TRANSFER_LENGTH;
+	chan->err = 0;
+	qdev->chan[channel] = chan;
+	chan->channel.device = &qdev->common;
+	chan->dev = qdev->dev;
+
+	tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
+
+	list_add_tail(&chan->channel.device_node, &qdev->common.channels);
+	qdev->common.chancnt++;
+
+	return 0;
+}
+
+static int __devinit msm_dma_probe(struct platform_device *pdev)
+{
+	struct msm_dma_device *qdev;
+	int i;
+	int ret = 0;
+
+	qdev = kzalloc(sizeof(*qdev), GFP_KERNEL);
+	if (!qdev) {
+		dev_err(&pdev->dev, "Not enough memory for device\n");
+		return -ENOMEM;
+	}
+
+	qdev->dev = &pdev->dev;
+	INIT_LIST_HEAD(&qdev->common.channels);
+	qdev->common.device_alloc_chan_resources =
+				msm_dma_alloc_chan_resources;
+	qdev->common.device_free_chan_resources =
+				msm_dma_free_chan_resources;
+	dma_cap_set(DMA_SG, qdev->common.cap_mask);
+	dma_cap_set(DMA_INTERLEAVE, qdev->common.cap_mask);
+
+	qdev->common.device_prep_dma_sg = msm_dma_prep_sg;
+	qdev->common.device_prep_interleaved_dma = msm_dma_prep_interleaved;
+	qdev->common.device_issue_pending = msm_dma_issue_pending;
+	qdev->common.dev = &pdev->dev;
+	qdev->common.device_tx_status = msm_tx_status;
+	qdev->common.device_control = msm_dma_chan_control;
+
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		ret = msm_dma_chan_probe(qdev, i);
+		if (ret) {
+			dev_err(&pdev->dev, "channel %d probe failed\n", i);
+			goto chan_free;
+		}
+	}
+
+	dev_info(&pdev->dev, "registering dma device\n");
+
+	ret = dma_async_device_register(&qdev->common);
+
+	if (ret) {
+		dev_err(&pdev->dev, "Registering Dma device failed\n");
+		goto chan_free;
+	}
+
+	dev_set_drvdata(&pdev->dev, qdev);
+	return 0;
+chan_free:
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		if (qdev->chan[i])
+			msm_dma_chan_remove(qdev->chan[i]);
+	}
+	kfree(qdev);
+	return ret;
+}
+
+static int  __devexit msm_dma_remove(struct platform_device *pdev)
+{
+	struct msm_dma_device *qdev = platform_get_drvdata(pdev);
+	int i;
+
+	dma_async_device_unregister(&qdev->common);
+
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		if (qdev->chan[i])
+			msm_dma_chan_remove(qdev->chan[i]);
+	}
+
+	dev_set_drvdata(&pdev->dev, NULL);
+	kfree(qdev);
+
+	return 0;
+}
+
+static struct platform_driver msm_dma_driver = {
+	.remove = __devexit_p(msm_dma_remove),
+	.driver = {
+		.name = "msm_dma",
+		.owner = THIS_MODULE,
+	},
+};
+
+static __init int msm_dma_init(void)
+{
+	return platform_driver_probe(&msm_dma_driver, msm_dma_probe);
+}
+subsys_initcall(msm_dma_init);
+
+static void __exit msm_dma_exit(void)
+{
+	platform_driver_unregister(&msm_dma_driver);
+}
+module_exit(msm_dma_exit);
+
+MODULE_DESCRIPTION("Qualcomm DMA driver");
+MODULE_LICENSE("GPL v2");
-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From kumarrav at codeaurora.org  Thu Mar 22 06:58:02 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Thu, 22 Mar 2012 16:28:02 +0530
Subject: [PATCH v4 2/2] DMAEngine: Add DMAEngine driver based on old MSM ADM
 DMA APIs
Message-ID: <1332413882-8456-1-git-send-email-kumarrav@codeaurora.org>

Add DMAEngine based driver using the old MSM ADM DMA APIs internally.
The benefit of this approach is that not all the drivers
have to get converted to DMAEngine APIs simultaneosly while
both the drivers can stay enabled in the kernel. The client
drivers using the old MSM APIs directly can now convert to
DMAEngine one by one.

Change-Id: I3647ed7b8c73b3078dfa8877a3560db3cb0a2373
Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
---
 arch/arm/mach-msm/include/mach/dma.h |   35 ++
 drivers/dma/Kconfig                  |   12 +
 drivers/dma/Makefile                 |    1 +
 drivers/dma/msm_adm_dma.c            |  728 ++++++++++++++++++++++++++++++++++
 4 files changed, 776 insertions(+), 0 deletions(-)
 create mode 100644 drivers/dma/msm_adm_dma.c

diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 05583f5..95b7b15 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -18,6 +18,36 @@
 #include <linux/list.h>
 #include <mach/msm_iomap.h>
 
+#define sg_dma_offset(sg)               ((sg)->offset)
+#define box_dma_row_address(box)        ((box)->dma_row_address)
+#define box_dma_row_len(box)            ((box)->dma_row_len)
+#define box_dma_row_num(box)            ((box)->dma_row_num)
+#define box_dma_row_offset(box)         ((box)->dma_row_offset)
+
+#define MSM_DMA_CMD_MASK		0x9FFF8
+#define MSM_DMA_CMD_SHIFT		0
+#define MSM_BOX_SRC_RLEN_MASK		0xFFFF
+#define MSM_BOX_SRC_RLEN_SHIFT		16
+#define MSM_BOX_SRC_RNUM_MASK		0xFFFF
+#define MSM_BOX_SRC_RNUM_SHIFT		16
+#define MSM_BOX_SRC_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_SRC_ROFFSET_SHIFT	16
+#define MSM_BOX_DST_RLEN_MASK		0xFFFF
+#define MSM_BOX_DST_RNUM_MASK		0xFFFF
+#define MSM_BOX_DST_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_MODE_CMD		0x3
+
+enum adm_flush_type {
+	ADM_FORCED_FLUSH,
+	ADM_GRACEFUL_FLUSH,
+};
+
+enum adm_dma_type {
+	ADM_SINGLE_MODE,
+	ADM_SG_MODE,
+	ADM_BOX_MODE,
+};
+
 struct msm_dmov_errdata {
 	uint32_t flush[6];
 };
@@ -32,6 +62,11 @@ struct msm_dmov_cmd {
 	void *data;
 };
 
+struct msm_adm_cmd_config {
+	uint32_t num_cmd;
+	uint32_t *cmd_cntrl;
+};
+
 #ifndef CONFIG_ARCH_MSM8X60
 void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
 void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f1a2749..1f99362 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -252,6 +252,18 @@ config EP93XX_DMA
 	help
 	  Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
 
+config MSM_ADM_DMA
+	tristate "Qualcomm MSM ADM DMA support"
+	depends on ARCH_MSM
+	select DMA_ENGINE
+	help
+	  Support the Qualcomm DMA engine. This engine is integrated into
+	  Qualcomm chips.
+
+	  Say Y here if you have such a chipset.
+
+	  If unsure, say N.
+
 config DMA_ENGINE
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 009a222..f55fb57 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
 obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
 obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
 obj-$(CONFIG_IMX_DMA) += imx-dma.o
+obj-$(CONFIG_MSM_ADM_DMA) += msm_adm_dma.o
 obj-$(CONFIG_MXS_DMA) += mxs-dma.o
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
diff --git a/drivers/dma/msm_adm_dma.c b/drivers/dma/msm_adm_dma.c
new file mode 100644
index 0000000..f5bbdc5
--- /dev/null
+++ b/drivers/dma/msm_adm_dma.c
@@ -0,0 +1,728 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/dmapool.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/dma.h>
+
+#define SD3_CHAN_START			0
+#define MSM_DMOV_CRCI_COUNT		16
+#define MSM_DMA_MAX_CHANS_PER_DEVICE	16
+#define MAX_TRANSFER_LENGTH		65535
+#define NO_ERR_CHAN_STATUS		0x80000002
+#define to_msm_chan(chan) container_of(chan, struct msm_dma_chan, channel)
+
+struct msm_dma_chan {
+	int chan_id;
+	dma_cookie_t completed_cookie;
+	dma_cookie_t error_cookie;
+	spinlock_t lock;
+	struct list_head active_list;
+	struct list_head pending_list;
+	struct dma_chan channel;
+	struct dma_pool *desc_pool;
+	struct device *dev;
+	int max_len;
+	int err;
+	struct tasklet_struct tasklet;
+};
+
+struct msm_dma_device {
+	void __iomem *base;
+	struct device *dev;
+	struct dma_device common;
+	struct msm_dma_chan *chan[MSM_DMA_MAX_CHANS_PER_DEVICE];
+};
+
+struct msm_dma_desc_hw {
+	unsigned int cmd_list_ptr;
+} __aligned(8);
+
+/* Single Item Mode */
+struct adm_cmd_t {
+	unsigned int cmd_cntrl;
+	unsigned int src;
+	unsigned int dst;
+	unsigned int len;
+};
+
+struct adm_box_cmd_t {
+	uint32_t cmd_cntrl;
+	uint32_t src_row_addr;
+	uint32_t dst_row_addr;
+	uint32_t src_dst_len;
+	uint32_t num_rows;
+	uint32_t row_offset;
+};
+
+struct msm_dma_desc_sw {
+	struct msm_dma_desc_hw hw;
+	struct adm_cmd_t *vaddr_cmd;
+	struct adm_box_cmd_t *vaddr_box_cmd;
+	size_t coherent_size;
+	dma_addr_t paddr_cmd_list;
+	struct list_head node;
+	struct msm_dmov_cmd dmov_cmd;
+	struct dma_async_tx_descriptor async_tx;
+} __aligned(8);
+
+static int msm_dma_alloc_chan_resources(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+
+	/* Has this channel already been allocated? */
+	if (chan->desc_pool)
+		return 1;
+
+	/*
+	 * We need the descriptor to be aligned to 8bytes
+	 * for meeting ADM specification requirement.
+	 */
+	chan->desc_pool = dma_pool_create("msm_dma_desc_pool",
+					chan->dev,
+					sizeof(struct msm_dma_desc_sw),
+				__alignof__(struct msm_dma_desc_sw), 0);
+	if (!chan->desc_pool) {
+		dev_err(chan->dev, "unable to allocate channel %d "
+				"descriptor pool\n", chan->chan_id);
+		return -ENOMEM;
+	}
+
+	chan->completed_cookie = 1;
+	dchan->cookie = 1;
+
+	/* there is at least one descriptor free to be allocated */
+	return 1;
+}
+
+static void msm_dma_free_desc_list(struct msm_dma_chan *chan,
+						struct list_head *list)
+{
+	struct msm_dma_desc_sw *desc, *_desc;
+
+	list_for_each_entry_safe(desc, _desc, list, node) {
+		list_del(&desc->node);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	}
+}
+
+static void msm_dma_free_chan_resources(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	unsigned long flags;
+
+	dev_dbg(chan->dev, "Free all channel resources.\n");
+	spin_lock_irqsave(&chan->lock, flags);
+	msm_dma_free_desc_list(chan, &chan->active_list);
+	msm_dma_free_desc_list(chan, &chan->pending_list);
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	dma_pool_destroy(chan->desc_pool);
+	chan->desc_pool = NULL;
+}
+
+static enum dma_status msm_dma_desc_status(struct msm_dma_chan *chan,
+					struct msm_dma_desc_sw *desc)
+{
+	return dma_async_is_complete(desc->async_tx.cookie,
+					chan->completed_cookie,
+					chan->channel.cookie);
+}
+
+static void msm_chan_desc_cleanup(struct msm_dma_chan *chan)
+{
+	struct msm_dma_desc_sw *desc, *_desc;
+	unsigned long flags;
+
+	dev_dbg(chan->dev, "Cleaning completed descriptor of channel %d\n",
+							chan->chan_id);
+	spin_lock_irqsave(&chan->lock, flags);
+
+	list_for_each_entry_safe(desc, _desc, &chan->active_list, node) {
+		dma_async_tx_callback callback;
+		void *callback_param;
+
+		if (msm_dma_desc_status(chan, desc) == DMA_IN_PROGRESS)
+			break;
+
+		/* Remove from the list of running transactions */
+		list_del(&desc->node);
+
+		/* Run the link descriptor callback function */
+		callback = desc->async_tx.callback;
+		callback_param = desc->async_tx.callback_param;
+		if (callback) {
+			spin_unlock_irqrestore(&chan->lock, flags);
+			callback(callback_param);
+			spin_lock_irqsave(&chan->lock, flags);
+		}
+
+		/* Run any dependencies, then free the descriptor */
+		dma_run_dependencies(&desc->async_tx);
+		spin_unlock_irqrestore(&chan->lock, flags);
+
+		if (desc->vaddr_cmd) {
+			dma_free_coherent(chan->dev, desc->coherent_size,
+						(void *)desc->vaddr_cmd,
+							desc->paddr_cmd_list);
+		} else {
+			dma_free_coherent(chan->dev, desc->coherent_size,
+						(void *)desc->vaddr_box_cmd,
+							desc->paddr_cmd_list);
+		}
+		spin_lock_irqsave(&chan->lock, flags);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	}
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+static void dma_do_tasklet(unsigned long data)
+{
+	struct msm_dma_chan *chan = (struct msm_dma_chan *)data;
+	msm_chan_desc_cleanup(chan);
+}
+
+static void
+msm_dma_complete_func(struct msm_dmov_cmd *cmd,
+				unsigned int result,
+				struct msm_dmov_errdata *err)
+{
+	unsigned long flags;
+	struct msm_dma_desc_sw *desch = container_of(cmd,
+				struct msm_dma_desc_sw, dmov_cmd);
+	struct msm_dma_chan *chan = to_msm_chan(desch->async_tx.chan);
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if ((result != NO_ERR_CHAN_STATUS) && err)
+		chan->error_cookie = desch->async_tx.cookie;
+	chan->completed_cookie = desch->async_tx.cookie;
+
+	tasklet_schedule(&chan->tasklet);
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+/*
+ *  Passes transfer descriptors to DMA hardware.
+ */
+static void msm_dma_issue_pending(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	struct msm_dma_desc_sw *desch;
+	unsigned long flags;
+
+	if (chan->err)
+		return;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if (list_empty(&chan->pending_list))
+		goto out_unlock;
+
+	desch = list_first_entry(&chan->pending_list, struct msm_dma_desc_sw,
+									node);
+	list_del(&desch->node);
+	desch->dmov_cmd.complete_func = msm_dma_complete_func;
+	desch->dmov_cmd.execute_func = NULL;
+	desch->dmov_cmd.cmdptr = DMOV_CMD_ADDR(desch->async_tx.phys);
+	list_add_tail(&desch->node, &chan->active_list);
+	mb();
+	msm_dmov_enqueue_cmd(chan->chan_id, &desch->dmov_cmd);
+out_unlock:
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+/*
+ *  Assignes cookie for each transfer descriptor passed.
+ *  Returns
+ *	Assigend cookie for success.
+ *	Error value for failure.
+ */
+static dma_cookie_t msm_dma_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	struct msm_dma_chan *chan = to_msm_chan(tx->chan);
+	struct msm_dma_desc_sw *desc = container_of(tx,
+	struct msm_dma_desc_sw, async_tx);
+	unsigned long flags;
+	dma_cookie_t cookie = -EBUSY;
+
+	if (chan->err)
+		return cookie;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	/*
+	 * assign cookies to all of the software descriptors
+	 * that make up this transaction
+	 */
+	cookie = chan->channel.cookie;
+	cookie++;
+	if (cookie < 0)
+		cookie = DMA_MIN_COOKIE;
+
+	desc->async_tx.cookie = cookie;
+	chan->channel.cookie = cookie;
+
+	/* put this transaction onto the tail of the pending queue */
+	list_add_tail(&desc->node, &chan->pending_list);
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	return cookie;
+}
+
+/*
+ *  Returns the DMA transfer status of a particular cookie
+ */
+static enum dma_status msm_tx_status(struct dma_chan *dchan,
+					dma_cookie_t cookie,
+				struct dma_tx_state *txstate)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	dma_cookie_t last_used;
+	dma_cookie_t last_complete;
+	enum dma_status status;
+
+	last_used = dchan->cookie;
+	last_complete = chan->completed_cookie;
+
+	dma_set_tx_state(txstate, last_complete, last_used, 0);
+
+	status = dma_async_is_complete(cookie, last_complete, last_used);
+
+	if (status != DMA_IN_PROGRESS)
+		if (chan->error_cookie == cookie)
+			status = DMA_ERROR;
+
+	return status;
+}
+
+static struct msm_dma_desc_sw *msm_dma_alloc_descriptor(
+				struct msm_dma_chan *chan,
+				int cmd_cnt,
+				enum adm_dma_type mask)
+{
+	struct msm_dma_desc_sw *desc;
+	dma_addr_t pdesc_addr;
+	dma_addr_t paddr_cmd_list;
+	void *err = NULL;
+
+	desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc_addr);
+	if (!desc) {
+		dev_dbg(chan->dev, "out of memory for desc\n");
+		return ERR_CAST(desc);
+	}
+
+	memset(desc, 0, sizeof(*desc));
+	desc->async_tx.phys = pdesc_addr;
+
+	if (mask == ADM_BOX_MODE) {
+		desc->coherent_size = sizeof(struct adm_box_cmd_t);
+		desc->vaddr_box_cmd = dma_alloc_coherent(chan->dev,
+				sizeof(struct adm_box_cmd_t),
+				&paddr_cmd_list, GFP_ATOMIC);
+		if (!desc->vaddr_box_cmd) {
+			dev_dbg(chan->dev, "out of memory for desc\n");
+			err = desc->vaddr_box_cmd;
+			goto fail;
+		}
+	} else {
+		desc->coherent_size = sizeof(struct adm_cmd_t)*cmd_cnt;
+
+		desc->vaddr_cmd = dma_alloc_coherent(chan->dev,
+				sizeof(struct adm_cmd_t)*cmd_cnt,
+				&paddr_cmd_list, GFP_ATOMIC);
+
+		if (!desc->vaddr_cmd) {
+			dev_dbg(chan->dev, "out of memory for desc\n");
+			err = desc->vaddr_cmd;
+			goto fail;
+		}
+	}
+
+	dma_async_tx_descriptor_init(&desc->async_tx, &chan->channel);
+	desc->async_tx.tx_submit = msm_dma_tx_submit;
+	desc->paddr_cmd_list = paddr_cmd_list;
+	desc->hw.cmd_list_ptr = (paddr_cmd_list >> 3) | CMD_PTR_LP;
+	return desc;
+fail:
+	dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	return ERR_CAST(err);
+}
+
+/*
+ *  Prepares the transfer descriptors for SG transaction.
+ *  Returns
+ *	address of dma_async_tx_descriptor for success.
+ *	Pointer of error value for failure.
+ */
+static struct dma_async_tx_descriptor *msm_dma_prep_sg(
+		struct dma_chan *dchan,
+		struct scatterlist *dst_sg, unsigned int dst_nents,
+		struct scatterlist *src_sg, unsigned int src_nents,
+		unsigned long flags, void *context)
+{
+
+	struct msm_dma_chan *chan;
+	struct msm_dma_desc_sw *new;
+	size_t copy, len;
+	int cmd_cnt = 0;
+	int first = 0;
+	int i;
+	dma_addr_t src;
+	dma_addr_t dst;
+	struct adm_cmd_t *cmdlist_vaddr;
+	struct scatterlist *sg;
+	struct msm_adm_cmd_config *cmd_config = context;
+
+	if (!dchan)
+		return ERR_PTR(-EINVAL);
+
+	if (dst_nents == 0 || src_nents == 0)
+		return ERR_PTR(-EINVAL);
+	if (!dst_sg || !src_sg)
+		return ERR_PTR(-EINVAL);
+
+	if ((dst_nents != src_nents) || (cmd_config->num_cmd != src_nents))
+		return ERR_PTR(-EINVAL);
+
+	chan = to_msm_chan(dchan);
+
+	cmd_cnt = src_nents;
+	for (i = 0; i < src_nents; i++) {
+		len = sg_dma_len(src_sg + i);
+		if (len != MAX_TRANSFER_LENGTH)
+			cmd_cnt += len/MAX_TRANSFER_LENGTH;
+	}
+
+	new = msm_dma_alloc_descriptor(chan, cmd_cnt, ADM_SG_MODE);
+
+	if (!new) {
+		dev_err(chan->dev,
+			"No free memory for link descriptor\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	cmdlist_vaddr = new->vaddr_cmd;
+
+	for_each_sg(src_sg, sg, src_nents, i) {
+		len = sg_dma_len(sg);
+		src = sg_dma_address(sg);
+		do {
+			copy = (len >= MAX_TRANSFER_LENGTH) ?
+						MAX_TRANSFER_LENGTH : len;
+			cmdlist_vaddr->src = src;
+			cmdlist_vaddr->len = copy;
+			cmdlist_vaddr->cmd_cntrl =
+					*(cmd_config->cmd_cntrl + i) &
+							MSM_DMA_CMD_MASK;
+			if (first == 0) {
+				if (cmd_cnt == 1)
+					cmdlist_vaddr->cmd_cntrl |= CMD_LC;
+				else
+					cmdlist_vaddr->cmd_cntrl |= CMD_OCB;
+				first = 1;
+			}
+			cmdlist_vaddr++;
+			len -= copy;
+			src += copy;
+		} while (len);
+	}
+	if (cmd_cnt > 1) {
+		cmdlist_vaddr--;
+		cmdlist_vaddr->cmd_cntrl |= CMD_LC | CMD_OCU;
+	}
+
+	cmdlist_vaddr = new->vaddr_cmd;
+
+	for_each_sg(dst_sg, sg, src_nents, i) {
+		len = sg_dma_len(sg);
+		dst = sg_dma_address(sg);
+		do {
+			copy = (len >= MAX_TRANSFER_LENGTH) ?
+					MAX_TRANSFER_LENGTH : len;
+			cmdlist_vaddr->dst = dst;
+			cmdlist_vaddr++;
+			len -= copy;
+			dst += copy;
+		} while (len);
+
+	}
+
+#ifdef DEBUG
+	cmdlist_vaddr = new->vaddr_cmd;
+	i = 0;
+	do {
+		dev_dbg(chan->dev, "cmd %d src 0x%x dst 0x%x len 0x%x "
+						"cntrl 0x%x\n",
+				i, cmdlist_vaddr->src, cmdlist_vaddr->dst,
+				cmdlist_vaddr->len, cmdlist_vaddr->cmd_cntrl);
+			cmdlist_vaddr++;
+	} while (!((cmdlist_vaddr-1)->cmd_cntrl & CMD_LC));
+#endif
+	new->async_tx.flags = flags;
+	new->async_tx.cookie = -EBUSY;
+
+	return &new->async_tx;
+}
+
+struct dma_async_tx_descriptor *msm_dma_prep_interleaved(
+				struct dma_chan *dchan,
+				struct dma_interleaved_template *xt,
+				unsigned long flags,
+				void *context)
+{
+
+	struct msm_dma_chan *chan;
+	struct msm_dma_desc_sw *new;
+	struct adm_box_cmd_t *box_cmd_vaddr;
+	struct msm_adm_cmd_config *cmd_config = context;
+
+	if (!dchan)
+		return ERR_PTR(-EINVAL);
+
+	if (!xt)
+		return ERR_PTR(-EINVAL);
+
+	chan = to_msm_chan(dchan);
+
+	new = msm_dma_alloc_descriptor(chan, 1, ADM_BOX_MODE);
+
+	if (!new) {
+		dev_err(chan->dev,
+			"No free memory for link descriptor\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	box_cmd_vaddr = new->vaddr_box_cmd;
+
+
+	box_cmd_vaddr->src_row_addr = xt->src_start;
+	box_cmd_vaddr->dst_row_addr = xt->dst_start;
+	box_cmd_vaddr->src_dst_len =
+			((xt->sgl[0].size & MSM_BOX_SRC_RLEN_MASK) <<
+					MSM_BOX_SRC_RLEN_SHIFT) |
+				(xt->sgl[0].size & MSM_BOX_DST_RLEN_MASK);
+
+	box_cmd_vaddr->cmd_cntrl =
+			(cmd_config->cmd_cntrl[0] & MSM_DMA_CMD_MASK) |
+						MSM_BOX_MODE_CMD | CMD_LC;
+
+	box_cmd_vaddr->num_rows =
+			((xt->numf & MSM_BOX_SRC_RNUM_MASK) <<
+			MSM_BOX_SRC_RNUM_SHIFT) |
+			(xt->numf & MSM_BOX_DST_RNUM_MASK);
+
+	if ((xt->src_sgl) && (xt->src_inc))
+		box_cmd_vaddr->row_offset =
+				((xt->sgl[0].size + xt->sgl[0].icg) &
+				MSM_BOX_SRC_ROFFSET_MASK) <<
+				MSM_BOX_SRC_ROFFSET_SHIFT;
+	else if ((!xt->src_sgl) && (xt->src_inc))
+		box_cmd_vaddr->row_offset = ((xt->sgl[0].size) &
+				MSM_BOX_SRC_ROFFSET_MASK) <<
+				MSM_BOX_SRC_ROFFSET_SHIFT;
+	else
+		box_cmd_vaddr->row_offset =
+			(0 & MSM_BOX_SRC_ROFFSET_MASK) <<
+			MSM_BOX_SRC_ROFFSET_SHIFT;
+
+
+	if ((xt->dst_sgl) && (xt->dst_inc))
+		box_cmd_vaddr->row_offset |=
+			((xt->sgl[0].size + xt->sgl[0].icg) &
+			MSM_BOX_DST_ROFFSET_MASK);
+	else if ((!xt->dst_sgl) && (xt->dst_inc))
+		box_cmd_vaddr->row_offset |= ((xt->sgl[0].size) &
+					MSM_BOX_DST_ROFFSET_MASK);
+	else
+		box_cmd_vaddr->row_offset |= (0 & MSM_BOX_DST_ROFFSET_MASK);
+
+	new->async_tx.flags = flags;
+	new->async_tx.cookie = -EBUSY;
+
+	return &new->async_tx;
+}
+
+/*
+ *  Controlling the hardware channel like stopping, flushing.
+ */
+static int msm_dma_chan_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+							unsigned long arg)
+{
+	enum adm_flush_type cmd_type = arg;
+
+	if (cmd == DMA_TERMINATE_ALL) {
+		switch (cmd_type) {
+		case ADM_GRACEFUL_FLUSH:
+				msm_dmov_stop_cmd(chan->chan_id, NULL, 1);
+			break;
+		case ADM_FORCED_FLUSH:
+			/*
+			 * We treate default as forced flush
+			 * so we fall through
+			 */
+		default:
+				msm_dmov_stop_cmd(chan->chan_id, NULL, 0);
+			break;
+		}
+	}
+	return 0;
+}
+
+static void msm_dma_chan_remove(struct msm_dma_chan *chan)
+{
+	tasklet_kill(&chan->tasklet);
+	list_del(&chan->channel.device_node);
+	kfree(chan);
+}
+
+static __devinit int msm_dma_chan_probe(struct msm_dma_device *qdev,
+					int channel)
+{
+	struct msm_dma_chan *chan;
+
+	chan = kzalloc(sizeof(*chan), GFP_KERNEL);
+	if (!chan) {
+		dev_err(qdev->dev, "no free memory for DMA channels!\n");
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&chan->lock);
+	INIT_LIST_HEAD(&chan->pending_list);
+	INIT_LIST_HEAD(&chan->active_list);
+
+	chan->chan_id = channel;
+	chan->completed_cookie = 0;
+	chan->channel.cookie = 0;
+	chan->max_len = MAX_TRANSFER_LENGTH;
+	chan->err = 0;
+	qdev->chan[channel] = chan;
+	chan->channel.device = &qdev->common;
+	chan->dev = qdev->dev;
+
+	tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
+
+	list_add_tail(&chan->channel.device_node, &qdev->common.channels);
+	qdev->common.chancnt++;
+
+	return 0;
+}
+
+static int __devinit msm_dma_probe(struct platform_device *pdev)
+{
+	struct msm_dma_device *qdev;
+	int i;
+	int ret = 0;
+
+	qdev = kzalloc(sizeof(*qdev), GFP_KERNEL);
+	if (!qdev) {
+		dev_err(&pdev->dev, "Not enough memory for device\n");
+		return -ENOMEM;
+	}
+
+	qdev->dev = &pdev->dev;
+	INIT_LIST_HEAD(&qdev->common.channels);
+	qdev->common.device_alloc_chan_resources =
+				msm_dma_alloc_chan_resources;
+	qdev->common.device_free_chan_resources =
+				msm_dma_free_chan_resources;
+	dma_cap_set(DMA_SG, qdev->common.cap_mask);
+	dma_cap_set(DMA_INTERLEAVE, qdev->common.cap_mask);
+
+	qdev->common.device_prep_dma_sg = msm_dma_prep_sg;
+	qdev->common.device_prep_interleaved_dma = msm_dma_prep_interleaved;
+	qdev->common.device_issue_pending = msm_dma_issue_pending;
+	qdev->common.dev = &pdev->dev;
+	qdev->common.device_tx_status = msm_tx_status;
+	qdev->common.device_control = msm_dma_chan_control;
+
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		ret = msm_dma_chan_probe(qdev, i);
+		if (ret) {
+			dev_err(&pdev->dev, "channel %d probe failed\n", i);
+			goto chan_free;
+		}
+	}
+
+	dev_info(&pdev->dev, "registering dma device\n");
+
+	ret = dma_async_device_register(&qdev->common);
+
+	if (ret) {
+		dev_err(&pdev->dev, "Registering Dma device failed\n");
+		goto chan_free;
+	}
+
+	dev_set_drvdata(&pdev->dev, qdev);
+	return 0;
+chan_free:
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		if (qdev->chan[i])
+			msm_dma_chan_remove(qdev->chan[i]);
+	}
+	kfree(qdev);
+	return ret;
+}
+
+static int  __devexit msm_dma_remove(struct platform_device *pdev)
+{
+	struct msm_dma_device *qdev = platform_get_drvdata(pdev);
+	int i;
+
+	dma_async_device_unregister(&qdev->common);
+
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		if (qdev->chan[i])
+			msm_dma_chan_remove(qdev->chan[i]);
+	}
+
+	dev_set_drvdata(&pdev->dev, NULL);
+	kfree(qdev);
+
+	return 0;
+}
+
+static struct platform_driver msm_dma_driver = {
+	.remove = __devexit_p(msm_dma_remove),
+	.driver = {
+		.name = "msm_dma",
+		.owner = THIS_MODULE,
+	},
+};
+
+static __init int msm_dma_init(void)
+{
+	return platform_driver_probe(&msm_dma_driver, msm_dma_probe);
+}
+subsys_initcall(msm_dma_init);
+
+static void __exit msm_dma_exit(void)
+{
+	platform_driver_unregister(&msm_dma_driver);
+}
+module_exit(msm_dma_exit);
+
+MODULE_DESCRIPTION("Qualcomm DMA driver");
+MODULE_LICENSE("GPL v2");
-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From broonie at opensource.wolfsonmicro.com  Thu Mar 22 07:15:31 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 22 Mar 2012 11:15:31 +0000
Subject: [PATCH 4/4] clk: wm831x: Add initial WM831x clock driver
In-Reply-To: <20120321222622.GG29317@pengutronix.de>
References: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1332360082-25092-4-git-send-email-broonie@opensource.wolfsonmicro.com>
 <20120321222622.GG29317@pengutronix.de>
Message-ID: <20120322111531.GA3091@opensource.wolfsonmicro.com>

On Wed, Mar 21, 2012 at 11:26:22PM +0100, Sascha Hauer wrote:
> On Wed, Mar 21, 2012 at 08:01:22PM +0000, Mark Brown wrote:

> > +	if (!clk_register(&pdev->dev, "xtal", &wm831x_xtal_ops,
> > +			  &clkdata->xtal_hw, NULL, 0, CLK_IS_ROOT))
> > +		return -EINVAL;

> The clock names are unique identifiers for the clock, so clocks in
> drivers should probably have dev_name encoded into them.

No, that's not sensible.  We shouldn't be open coding this into each
individual driver that provides clocks, and we shouldn't have clock
users having to guess at what scheme the driver author used to dedupe
the clocks.  As a driver author you would assume that the reason we're
providing the struct device to the registration function in the first
place is so that the core has the information it needs to do that.

I did provide patches to do what you suggest in the core for one of the
earlier versions of the API, I have to say I didn't check to see if they
got dropped during the general lulls.

> You could also use the fixed rate generic clock here.

It doesn't really do what I want with reporting the enables - for
diagnostic purposes I wanted to always have the clock present but
non-enablable so we could actually look at the clock tree and see 
what's going on directly when there's no clock coming out.
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From s.hauer at pengutronix.de  Thu Mar 22 07:26:13 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 22 Mar 2012 12:26:13 +0100
Subject: [PATCH 4/4] clk: wm831x: Add initial WM831x clock driver
In-Reply-To: <20120322111531.GA3091@opensource.wolfsonmicro.com>
References: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1332360082-25092-4-git-send-email-broonie@opensource.wolfsonmicro.com>
 <20120321222622.GG29317@pengutronix.de>
 <20120322111531.GA3091@opensource.wolfsonmicro.com>
Message-ID: <20120322112613.GA3852@pengutronix.de>

On Thu, Mar 22, 2012 at 11:15:31AM +0000, Mark Brown wrote:
> On Wed, Mar 21, 2012 at 11:26:22PM +0100, Sascha Hauer wrote:
> > On Wed, Mar 21, 2012 at 08:01:22PM +0000, Mark Brown wrote:
> 
> > > +	if (!clk_register(&pdev->dev, "xtal", &wm831x_xtal_ops,
> > > +			  &clkdata->xtal_hw, NULL, 0, CLK_IS_ROOT))
> > > +		return -EINVAL;
> 
> > The clock names are unique identifiers for the clock, so clocks in
> > drivers should probably have dev_name encoded into them.
> 
> No, that's not sensible.  We shouldn't be open coding this into each
> individual driver that provides clocks, and we shouldn't have clock
> users having to guess at what scheme the driver author used to dedupe
> the clocks.  As a driver author you would assume that the reason we're
> providing the struct device to the registration function in the first
> place is so that the core has the information it needs to do that.
> 
> I did provide patches to do what you suggest in the core for one of the
> earlier versions of the API, I have to say I didn't check to see if they
> got dropped during the general lulls.

It seems they got dropped. Currently the clock framework does nothing
with the device argument. But right, it could use this argument to
generate a suitable name.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From broonie at opensource.wolfsonmicro.com  Thu Mar 22 07:33:40 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 22 Mar 2012 11:33:40 +0000
Subject: [PATCH] clk: wm831x: Add initial WM831x clock driver
Message-ID: <1332416020-27616-1-git-send-email-broonie@opensource.wolfsonmicro.com>

The WM831x and WM832x series of PMICs contain a flexible clocking
subsystem intended to provide always on and system core clocks.  It
features:

- A 32.768kHz crystal oscillator which can optionally be used to pass
  through an externally generated clock.
- A FLL which can be clocked from either the 32.768kHz oscillator or
  the CLKIN pin.
- A CLKOUT pin which can bring out either the oscillator or the FLL
  output.
- The 32.768kHz clock can also optionally be brought out on the GPIO
  pins of the device.

This driver fully supports the 32.768kHz oscillator and CLKOUT.  The FLL
is supported only in AUTO mode, the full flexibility of the FLL cannot
currently be used.

Due to a lack of access to systems where the core SoC has been converted
to use the generic clock API this driver has been compile tested only.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 MAINTAINERS              |    1 +
 drivers/clk/Kconfig      |    7 +
 drivers/clk/Makefile     |    1 +
 drivers/clk/clk-wm831x.c |  402 ++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 411 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-wm831x.c

diff --git a/MAINTAINERS b/MAINTAINERS
index e247af8..d02b233 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7475,6 +7475,7 @@ W:	http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices
 S:	Supported
 F:	Documentation/hwmon/wm83??
 F:	arch/arm/mach-s3c64xx/mach-crag6410*
+F:	drivers/clk/clk-wm83*.c
 F:	drivers/leds/leds-wm83*.c
 F:	drivers/hwmon/wm83??-hwmon.c
 F:	drivers/input/misc/wm831x-on.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 165e1fe..367ba74 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -44,4 +44,11 @@ config COMMON_CLK_DEBUG
 	  clk_flags, clk_prepare_count, clk_enable_count &
 	  clk_notifier_count.
 
+config COMMON_CLK_WM831X
+	tristate "Clock driver for WM831x/2x PMICs"
+	depends on MFD_WM831X
+	---help---
+          Supports the clocking subsystem of the WM831x/2x series of
+	  PMICs from Wolfson Microlectronics.
+
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1f736bc..a155102 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -2,3 +2,4 @@
 obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
 obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-fixed-rate.o clk-gate.o \
 				   clk-mux.o clk-divider.o
+obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
new file mode 100644
index 0000000..3474591
--- /dev/null
+++ b/drivers/clk/clk-wm831x.c
@@ -0,0 +1,402 @@
+/*
+ * WM831x clock control
+ *
+ * Copyright 2011-2 Wolfson Microelectronics PLC.
+ *
+ * Author: Mark Brown <broonie at opensource.wolfsonmicro.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/wm831x/core.h>
+
+struct wm831x_clk {
+	struct wm831x *wm831x;
+	struct clk_hw xtal_hw;
+	struct clk_hw fll_hw;
+	struct clk_hw clkout_hw;
+	bool xtal_ena;
+};
+
+static int wm831x_xtal_is_enabled(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  xtal_hw);
+
+	return clkdata->xtal_ena;
+}
+
+static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
+					     unsigned long parent_rate)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  xtal_hw);
+
+	if (clkdata->xtal_ena)
+		return 32768;
+	else
+		return 0;
+}
+
+static const struct clk_ops wm831x_xtal_ops = {
+	.is_enabled = wm831x_xtal_is_enabled,
+	.recalc_rate = wm831x_xtal_recalc_rate,
+};
+
+static const unsigned long wm831x_fll_auto_rates[] = {
+	 2048000,
+	11289600,
+	12000000,
+	12288000,
+	19200000,
+	22579600,
+	24000000,
+	24576000,
+};
+
+static int wm831x_fll_is_enabled(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
+			ret);
+		return true;
+	}
+
+	return (ret & WM831X_FLL_ENA) != 0;
+}
+
+static int wm831x_fll_prepare(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2,
+			      WM831X_FLL_ENA, WM831X_FLL_ENA);
+	if (ret != 0)
+		dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
+
+	usleep_range(2000, 2000);
+
+	return ret;
+}
+
+static void wm831x_fll_unprepare(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_2, WM831X_FLL_ENA, 0);
+	if (ret != 0)
+		dev_crit(wm831x->dev, "Failed to disaable FLL: %d\n", ret);
+}
+
+static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
+					    unsigned long parent_rate)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
+			ret);
+		return 0;
+	}
+
+	if (ret & WM831X_FLL_AUTO)
+		return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
+
+	dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");
+
+	return 0;
+}
+
+static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
+				  unsigned long *unused)
+{
+	int best = 0;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
+		if (abs(wm831x_fll_auto_rates[i] - rate) <
+		    abs(wm831x_fll_auto_rates[best] - rate))
+			best = i;
+
+	return wm831x_fll_auto_rates[best];
+}
+
+static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
+		if (wm831x_fll_auto_rates[i] == rate)
+			break;
+	if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
+		return -EINVAL;
+
+	if (wm831x_fll_is_enabled(hw))
+		return -EPERM;
+
+	return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
+			       WM831X_FLL_AUTO_FREQ_MASK, i);
+}
+
+static const char *wm831x_fll_parents[] = {
+	"xtal",
+	"clkin",
+};
+
+static u8 wm831x_fll_get_parent(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  fll_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	/* AUTO mode is always clocked from the crystal */
+	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
+			ret);
+		return 0;
+	}
+
+	if (ret & WM831X_FLL_AUTO)
+		return 0;
+
+	ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
+			ret);
+		return 0;
+	}
+
+	switch (ret & WM831X_FLL_CLK_SRC_MASK) {
+	case 0:
+		return 0;
+	case 1:
+		return 1;
+	default:
+		dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
+			ret & WM831X_FLL_CLK_SRC_MASK);
+		return 0;
+	}
+}
+
+static const struct clk_ops wm831x_fll_ops = {
+	.is_enabled = wm831x_fll_is_enabled,
+	.prepare = wm831x_fll_prepare,
+	.unprepare = wm831x_fll_unprepare,
+	.round_rate = wm831x_fll_round_rate,
+	.recalc_rate = wm831x_fll_recalc_rate,
+	.set_rate = wm831x_fll_set_rate,
+	.get_parent = wm831x_fll_get_parent,
+};
+
+static int wm831x_clkout_is_enabled(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  clkout_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
+			ret);
+		return true;
+	}
+
+	return (ret & WM831X_CLKOUT_ENA) != 0;
+}
+
+static int wm831x_clkout_prepare(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  clkout_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_unlock(wm831x);
+	if (ret != 0) {
+		dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
+		return ret;
+	}
+
+	ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
+			      WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
+	if (ret != 0)
+		dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
+
+	wm831x_reg_lock(wm831x);
+
+	return ret;
+}
+
+static void wm831x_clkout_unprepare(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  clkout_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_unlock(wm831x);
+	if (ret != 0) {
+		dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
+		return;
+	}
+
+	ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
+			      WM831X_CLKOUT_ENA, 0);
+	if (ret != 0)
+		dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
+
+	wm831x_reg_lock(wm831x);
+}
+
+static const char *wm831x_clkout_parents[] = {
+	"xtal",
+	"fll",
+};
+
+static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  clkout_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+	int ret;
+
+	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
+			ret);
+		return 0;
+	}
+
+	if (ret & WM831X_CLKOUT_SRC)
+		return 0;
+	else
+		return 1;
+}
+
+static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
+{
+	struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
+						  clkout_hw);
+	struct wm831x *wm831x = clkdata->wm831x;
+
+	return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
+			       WM831X_CLKOUT_SRC,
+			       parent << WM831X_CLKOUT_SRC_SHIFT);
+}
+
+static const struct clk_ops wm831x_clkout_ops = {
+	.is_enabled = wm831x_clkout_is_enabled,
+	.prepare = wm831x_clkout_prepare,
+	.unprepare = wm831x_clkout_unprepare,
+	.get_parent = wm831x_clkout_get_parent,
+	.set_parent = wm831x_clkout_set_parent,
+};
+
+static __devinit int wm831x_clk_probe(struct platform_device *pdev)
+{
+	struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
+	struct wm831x_clk *clkdata;
+	int ret;
+
+	clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
+	if (!clkdata)
+		return -ENOMEM;
+
+	/* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
+	ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
+	if (ret < 0) {
+		dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
+			ret);
+		return ret;
+	}
+	clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
+
+	if (!clk_register(&pdev->dev, "xtal", &wm831x_xtal_ops,
+			  &clkdata->xtal_hw, NULL, 0, CLK_IS_ROOT))
+		return -EINVAL;
+
+	if (!clk_register(&pdev->dev, "fll", &wm831x_fll_ops, &clkdata->fll_hw,
+			  wm831x_fll_parents, ARRAY_SIZE(wm831x_fll_parents),
+			  0)) {
+		ret = -EINVAL;
+		goto err_xtal;
+	}
+
+	if (!clk_register(&pdev->dev, "clkout", &wm831x_clkout_ops,
+			  &clkdata->clkout_hw, wm831x_clkout_parents,
+			  ARRAY_SIZE(wm831x_clkout_parents),
+			  CLK_SET_RATE_PARENT)) {
+		ret = -EINVAL;
+		goto err_fll;
+	}
+
+	dev_set_drvdata(&pdev->dev, clkdata);
+
+	return 0;
+
+err_fll:
+	clk_unregister(clkdata->fll_hw.clk);
+err_xtal:
+	clk_unregister(clkdata->xtal_hw.clk);
+	return ret;
+}
+
+static __devexit int wm831x_clk_remove(struct platform_device *pdev)
+{
+	struct wm831x_clk *clkdata = dev_get_drvdata(&pdev->dev);
+
+	clk_unregister(clkdata->clkout_hw.clk);
+	clk_unregister(clkdata->fll_hw.clk);
+	clk_unregister(clkdata->xtal_hw.clk);
+
+	return 0;
+}
+
+static struct platform_driver wm831x_clk_driver = {
+	.probe = wm831x_clk_probe,
+	.remove = __devexit_p(wm831x_clk_remove),
+	.driver		= {
+		.name	= "wm831x-clk",
+		.owner	= THIS_MODULE,
+	},
+};
+
+module_platform_driver(wm831x_clk_driver);
+
+/* Module information */
+MODULE_AUTHOR("Mark Brown <broonie at opensource.wolfsonmicro.com>");
+MODULE_DESCRIPTION("WM831x clock driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:wm831x-clk");
-- 
1.7.9.1



From broonie at opensource.wolfsonmicro.com  Thu Mar 22 07:33:56 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 22 Mar 2012 11:33:56 +0000
Subject: [PATCH 4/4] clk: wm831x: Add initial WM831x clock driver
In-Reply-To: <20120322112613.GA3852@pengutronix.de>
References: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1332360082-25092-4-git-send-email-broonie@opensource.wolfsonmicro.com>
 <20120321222622.GG29317@pengutronix.de>
 <20120322111531.GA3091@opensource.wolfsonmicro.com>
 <20120322112613.GA3852@pengutronix.de>
Message-ID: <20120322113356.GC3091@opensource.wolfsonmicro.com>

On Thu, Mar 22, 2012 at 12:26:13PM +0100, Sascha Hauer wrote:
> On Thu, Mar 22, 2012 at 11:15:31AM +0000, Mark Brown wrote:

> > No, that's not sensible.  We shouldn't be open coding this into each
> > individual driver that provides clocks, and we shouldn't have clock
> > users having to guess at what scheme the driver author used to dedupe
> > the clocks.  As a driver author you would assume that the reason we're

> It seems they got dropped. Currently the clock framework does nothing
> with the device argument. But right, it could use this argument to
> generate a suitable name.

Indeed, and as with adding the stub clk_unregister() it seems like it's
better at this point to just code the drivers as we'd expect them to
work and fill out the framework to handle this rather than introducing
workarounds in the drivers.
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From lars at metafoo.de  Thu Mar 22 07:49:48 2012
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Thu, 22 Mar 2012 12:49:48 +0100
Subject: [PATCH v4 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 ADM DMA APIs
In-Reply-To: <1332413882-8456-1-git-send-email-kumarrav@codeaurora.org>
References: <1332413882-8456-1-git-send-email-kumarrav@codeaurora.org>
Message-ID: <4F6B11DC.9090401@metafoo.de>

On 03/22/2012 11:58 AM, Ravi Kumar V wrote:
> [...]
> +static struct dma_async_tx_descriptor *msm_dma_prep_sg(
> +		struct dma_chan *dchan,
> +		struct scatterlist *dst_sg, unsigned int dst_nents,
> +		struct scatterlist *src_sg, unsigned int src_nents,
> +		unsigned long flags, void *context)
> +{
> [...]
> +
> +	if (!dchan)
> +		return ERR_PTR(-EINVAL);
> +
> +	if (dst_nents == 0 || src_nents == 0)
> +		return ERR_PTR(-EINVAL);
> +	if (!dst_sg || !src_sg)
> +		return ERR_PTR(-EINVAL);
> +
> +	if ((dst_nents != src_nents) || (cmd_config->num_cmd != src_nents))
> +		return ERR_PTR(-EINVAL);
> +
> + [...]
> +
> +	if (!new) {
> +		dev_err(chan->dev,
> +			"No free memory for link descriptor\n");
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> [...]
> +	return &new->async_tx;
> +}

Same comment as before. This is supposed to return either a valid descriptor
or NULL, but not an ERR_PTR.



From external.Peter.Waechtler at de.bosch.com  Thu Mar 22 08:24:47 2012
From: external.Peter.Waechtler at de.bosch.com (EXTERNAL Waechtler Peter (Fa. TCP, CM-AI/PJ-CF31))
Date: Thu, 22 Mar 2012 13:24:47 +0100
Subject: ARM11MPcore: tlb_ops_need_broadcast causes deadlock
Message-ID: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>

Here we are again with another issue on ARM11mpcore (2 cores for Linux):

In relatively rare circumstances the system soft-locks up:


cpuA                                                                cpuB

kswapd searches for pages to reclaim
via shrink_zone
page_referenced
page_referenced_one
    page_check_address(&ptl)   <- ptl gets locked!
    ptep_clear_flush_young_notify                                   jump to the "innocent" page
                                                                        IRQS OFF
                                                                        do_DataAbort-> handle_mm_fault
                                                                            handle_pte_fault (inlined)
                                                                            ptl = pte_lockptr(mm, pmd);
                                                                            spin_lock(ptl);

        flush_tlb_page
            tlb_ops_need_broadcast
            on_each_cpu_mask(ipi_flush_tlb_page, with WAIT)
                csd_lock_wait()
                                          DEADLOCK, IPI on cpuB does not finish because IRQs are OFF
    pte_unmap_unlock(pte, ptl);



And here is some explanation:

Every then and now pages are marked inaccessible in the hardware PTE
(page table entry) so that the VM subsystem can check if the page is
accessed at all. If it's frequently accessed it will become a "young" page.
On memory pressure "old" pages will be the first to get evicted.

The kswapd kernel thread goes through a list of pages to check if they
were accessed in a given interval and mark our target page as young.

The cpuB executes some user code hitting that page and because the PTE
is marked "inaccessible", so that the attempt can be stored, it results
in a page fault.

Unluckily the kswapd calls tlb_flush and that is configured to inform all
cpus about that change via IPIs. cpuB is in an user abort handler (__dabt_usr)
and the disaster takes its course:

For checking if it's a thumb instruction that caused the fault the abort handler
accesses the page resulting into another fault - but now entering svc abort handler
(__dabt_svc) and that turns off interrupts!

That leads to cpuA waiting in csd_lock_wait for the IPI to signal its end of execution
(via csd->flags) but that does not happen because IRQs are off on cpuB that
is stuck in the page fault handler spinning to get the lock for the mm->page_table_lock
but this is still held on cpuA waiting for the IPIs to finish.

possible solutions:

a) do not wait for that particular IPI since the mapping does not change
 (just the access bits)

b) open code the ptep_set_access_flags() and change the sequence that the IPI
 is called without holding the page_table_lock anymore

This shows up on CPUs where tlb_ops_need_broadcast() returns true.


Input welcome how to resolve this issue.

regards

        Peter


From egtvedt at samfundet.no  Thu Mar 22 08:33:27 2012
From: egtvedt at samfundet.no (Hans-Christian Egtvedt)
Date: Thu, 22 Mar 2012 13:33:27 +0100
Subject: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h
In-Reply-To: <20120322051840.GC923@windriver.com>
References: <1332296128-16262-1-git-send-email-paul.gortmaker@windriver.com>
 <20120321072632.GA15703@samfundet.no> <4F6990AF.2000004@atmel.com>
 <20120322051840.GC923@windriver.com>
Message-ID: <20120322123327.GA14690@samfundet.no>

Around Thu 22 Mar 2012 01:18:40 -0400 or thereabout, Paul Gortmaker wrote:
> [Re: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h] On 21/03/2012 (Wed 09:26) Nicolas Ferre wrote:
> 
>> On 03/21/2012 08:26 AM, Hans-Christian Egtvedt :
>> > Around Tue 20 Mar 2012 22:15:28 -0400 or thereabout, Paul Gortmaker wrote:
>> >> Commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c (linux-next)
>> >>
>> >>     "ATMEL: fix nand ecc support"
>> >>
>> >> indicated that it wanted to "Move platform data to a common
>> >> header include/linux/platform_data/atmel_nand.h" and the new
>> >> header even had re-include protectors with:
>> >>
>> >>     #ifndef __ATMEL_NAND_H__
>> >>
>> >> However, the file that was added was simply called atmel.h
>> >> and this caused avr32 defconfig to fail with:
>> >>
>> >>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>> >>   arch/avr32/mach-at32ap/include/mach/board.h:10:44: error: linux/platform_data/atmel_nand.h: No such file or directory
>> >>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>> >>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: 'struct atmel_nand_data' declared inside parameter list
>> >>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: its scope is only this definition or declaration, which is probably not what you want
>> >>   make[2]: *** [arch/avr32/boards/atstk1000/setup.o] Error 1
>> >>
>> >> Rename the file to match the original intention, and fix up the
>> >> users who reference the bad name without the _nand suffix.
>> > 
>> > Thanks fixing this.
>> 
>> 
>> Yes, we need to fix this. But I would not like to see this
>> "platform_data/atmel.h" renamed: I think that this file was designed to
>> collect several common platform data (ie: not just NAND related).
>> 
>> So maybe we should just rename the entry that exists in
>> mach-at32ap/include/mach/board.h
>> and remove all occurrences of platform_data/atmel_nand.h
> 
> Funny, since this is what I did 1st before I re-read the original commit
> log in more detail. :)  Oh well.  Here is the alternate solution.  You
> guys can pick whichever one you like best.  I compile tested this one
> as well.

I'll leave it to Nicolas to sign-off on this, but the changes look fine for
me.

> ---
> 
> From 73c01b7ed8fd2732661fa1ca726c48096f4651f2 Mon Sep 17 00:00:00 2001
> From: Paul Gortmaker <paul.gortmaker at windriver.com>
> Date: Tue, 20 Mar 2012 21:55:46 -0400
> Subject: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h
> 
> Commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c (linux-next)
> 
>     "ATMEL: fix nand ecc support"
> 
> indicated that it wanted to "Move platform data to a common
> header include/linux/platform_data/atmel_nand.h" and the new
> header even had re-include protectors with:
> 
>     #ifndef __ATMEL_NAND_H__
> 
> However, the file that was added was simply called atmel.h
> and this caused avr32 defconfig to fail with:
> 
>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>   arch/avr32/mach-at32ap/include/mach/board.h:10:44: error: linux/platform_data/atmel_nand.h: No such file or directory
>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: 'struct atmel_nand_data' declared inside parameter list
>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: its scope is only this definition or declaration, which is probably not what you want
>   make[2]: *** [arch/avr32/boards/atstk1000/setup.o] Error 1
> 
> It seems the scope of the file contents will expand beyond
> just nand, so ignore the original intention, and fix up the
> users who reference the bad name with the _nand suffix.
> 
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> CC: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> CC: Hans-Christian Egtvedt <egtvedt at samfundet.no>
> CC: David Woodhouse <dwmw2 at infradead.org>

Acked-by: Hans-Christian Egtvedt <egtvedt at samfundet.no>

> diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
> index 7173386..70742ec 100644
> --- a/arch/avr32/mach-at32ap/include/mach/board.h
> +++ b/arch/avr32/mach-at32ap/include/mach/board.h
> @@ -7,7 +7,7 @@
>  #include <linux/types.h>
>  #include <linux/serial.h>
>  #include <linux/platform_data/macb.h>
> -#include <linux/platform_data/atmel_nand.h>
> +#include <linux/platform_data/atmel.h>
>  
>  #define GPIO_PIN_NONE	(-1)
>  
> diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel.h
> index d056263..b0f2c56 100644
> --- a/include/linux/platform_data/atmel.h
> +++ b/include/linux/platform_data/atmel.h
> @@ -4,8 +4,8 @@
>   * GPL v2 Only
>   */
>  
> -#ifndef __ATMEL_NAND_H__
> -#define __ATMEL_NAND_H__
> +#ifndef __ATMEL_H__
> +#define __ATMEL_H__
>  
>  #include <linux/mtd/nand.h>
>  
> @@ -24,4 +24,4 @@ struct atmel_nand_data {
>  	unsigned int	num_parts;
>  };
>  
> -#endif /* __ATMEL_NAND_H__ */
> +#endif /* __ATMEL_H__ */
-- 
mvh
Hans-Christian Egtvedt


From sr at denx.de  Thu Mar 22 08:41:13 2012
From: sr at denx.de (Stefan Roese)
Date: Thu, 22 Mar 2012 13:41:13 +0100
Subject: [PATCH] ARM: SPEAr600: Change FSMC and SMI clock names
Message-ID: <1332420073-17703-1-git-send-email-sr@denx.de>

Change FSMC and SMI clock names to match the ones needed for DT based
probing.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/mach-spear6xx/clock.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index a86499a..f051804 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -660,8 +660,8 @@ static struct clk_lookup spear_clk_lookups[] = {
 	{ .dev_id = "dma",		.clk = &dma_clk},
 	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
 	{ .dev_id = "gmac",		.clk = &gmac_clk},
-	{ .dev_id = "smi",		.clk = &smi_clk},
-	{ .dev_id = "fsmc-nand",	.clk = &fsmc_clk},
+	{ .dev_id = "fc000000.flash",	.clk = &smi_clk},
+	{ .dev_id = "d1800000.flash",	.clk = &fsmc_clk},
 	/* clock derived from apb clk */
 	{ .dev_id = "adc",		.clk = &adc_clk},
 	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
-- 
1.7.9.2



From sshtylyov at mvista.com  Thu Mar 22 09:14:12 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Thu, 22 Mar 2012 17:14:12 +0400
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <4F6AF845.9070209@metasoft.pl>
References: <4F683B36.8090101@metasoft.pl> <4F6A78ED.3050403@gmail.com>
 <4F6AF845.9070209@metasoft.pl>
Message-ID: <4F6B25A4.4090006@mvista.com>

Hello.

On 22-03-2012 14:00, Rafal Prylowski wrote:

>> I haven't looked through the patch yet, since I'm waiting on more
>> information from Mika and Hartley's testing.

>> However, the commit log doesn't tell me why we want this change. Is it a
>> performance improvement? If so, do you have some numbers that we can
>> paste into the commit log?

> In principle, using double buffering should be faster than using only
> one buffer and disabling/enabling channel each time. But my measurements
> doesn't show any significant change.

> The real reason for this change is that current code is not 100% reliable
> in IDE-DMA (I'm planning to submit ep93xx ide driver to linux-ide soon).

    IDE or libata driver? Asking because IDE drivers are not accepted anymore.

WBR, Sergei


From vaibhav.bedia at ti.com  Thu Mar 22 09:20:53 2012
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Thu, 22 Mar 2012 13:20:53 +0000
Subject: Occasional crashes in suspend-resume with MMC transactions
In-Reply-To: <B5906170F1614E41A8A28DE3B8D12143317FDFBB@DBDE01.ent.ti.com>
References: <B5906170F1614E41A8A28DE3B8D12143317FDFBB@DBDE01.ent.ti.com>
Message-ID: <B5906170F1614E41A8A28DE3B8D12143317FF773@DBDE01.ent.ti.com>

On Thu, Mar 22, 2012 at 09:53:23, Bedia, Vaibhav wrote:
> Hi,
> 
> I am trying to do suspend-resume test with a file copy on MMC/SD going on
> in the background. The test involves simply copying a 450MB file on an ext3
> partition to the same partition under a different name.
> 
> This is on an AM335x board which uses the omap_hsmmc driver. 
> The kernel is v3.2 and I have also applied the following patch 
> 

[...]

I found that whenever this issue crops up, mmc_host_suspend() is not able to claim the host
And returns -EBUSY. omap_hsmmc driver does not pass on this error code to the PM core and
hence the suspend process continues. When the driver is made to return -EBUSY, the suspend
process gets aborted and the user can try suspending again. I am not sure whether this sort
of suspend failure is acceptable or the driver is doing something wrong. The following
workaround is what I came up with. Do this look a reasonable thing to do?

---

>From a4040dd1869b351a5fa29dacd08facf6e24df609 Mon Sep 17 00:00:00 2001
From: Vaibhav Bedia <vaibhav.bedia at ti.com>
Date: Thu, 22 Mar 2012 17:14:49 +0530
Subject: [PATCH 1/1] mmc: omap_hsmmc: Pass on the suspend failure to the PM core

In some cases mmc_host_suspend() is not able to claim the
host and proceed with the suspend process. The core returns
-EBUSY to the host controller driver. Unfortunately, the
host controller driver does not pass on this information
to the PM core and hence the system suspend process continues.

In these cases the MMC core gets to an unexpected state
during resume and multiple issues related to MMC crop up.
1. Host controller driver starts accessing the device registers
before the clocks are enabled which leads to a prefetch abort.
2. A file copy thread which was launched before suspend gets
stuck due to the host not being reclaimed during resume.

To avoid such problems pass on the -EBUSY status to the PM core
from the host controller driver. With this change, MMC core
suspend might still fail but it does not end up making the
system unusable. Suspend gets aborted and the user can try
suspending the system again.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
---
 drivers/mmc/host/omap_hsmmc.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 3d8dbbb..1f938d9 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -2238,6 +2238,7 @@ static int omap_hsmmc_suspend(struct device *dev)
                                        dev_dbg(mmc_dev(host->mmc),
                                                "Unmask interrupt failed\n");
                        }
+                       ret = -EBUSY;
                        goto err;
                }

--
1.7.0.4


From robherring2 at gmail.com  Thu Mar 22 09:42:41 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Thu, 22 Mar 2012 08:42:41 -0500
Subject: [PATCH v2] ARM: pxa: use common IOMEM definition
In-Reply-To: <1332296149-28110-2-git-send-email-robherring2@gmail.com>
References: <1332296149-28110-2-git-send-email-robherring2@gmail.com>
Message-ID: <1332423761-27205-1-git-send-email-robherring2@gmail.com>

From: Rob Herring <rob.herring at calxeda.com>

pxa was missed in the moving of IOMEM to a common definition, so lots of
IOMEM redefined warnings were introduced. So remove pxa IOMEM definition
and fix all the fallout.

Reported-by: Paul Gortmaker <paul.gortmaker at windriver.com>
Signed-off-by: Rob Herring <rob.herring at calxeda.com>
Cc: Eric Miao <eric.y.miao at gmail.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
Cc: Alessandro Zummo <a.zummo at towertech.it>
Cc: Jaroslav Kysela <perex at perex.cz>
Cc: Takashi Iwai <tiwai at suse.de>
Cc: rtc-linux at googlegroups.com
Cc: alsa-devel at alsa-project.org
---
v2:
- fix my commit msg typos
- add fix for sa1100_wdt.c

I plan to send this fix thru the arm-soc tree.

Rob

 arch/arm/mach-pxa/clock-pxa2xx.c          |    1 +
 arch/arm/mach-pxa/corgi_pm.c              |    1 +
 arch/arm/mach-pxa/cpufreq-pxa3xx.c        |    1 +
 arch/arm/mach-pxa/include/mach/hardware.h |    2 --
 arch/arm/mach-pxa/mfp-pxa2xx.c            |    1 +
 arch/arm/mach-pxa/pxa2xx.c                |    1 +
 arch/arm/mach-pxa/pxa300.c                |    1 +
 arch/arm/mach-pxa/pxa320.c                |    1 +
 arch/arm/mach-pxa/sharpsl_pm.c            |    1 +
 drivers/rtc/rtc-sa1100.c                  |    1 +
 drivers/watchdog/sa1100_wdt.c             |    1 +
 sound/arm/pxa2xx-ac97-lib.c               |    1 +
 sound/arm/pxa2xx-ac97.c                   |    1 +
 sound/soc/pxa/pxa2xx-ac97.c               |    1 +
 14 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-pxa/clock-pxa2xx.c b/arch/arm/mach-pxa/clock-pxa2xx.c
index 1d5859d..9ee2ad6 100644
--- a/arch/arm/mach-pxa/clock-pxa2xx.c
+++ b/arch/arm/mach-pxa/clock-pxa2xx.c
@@ -9,6 +9,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/syscore_ops.h>
 
 #include <mach/pxa2xx-regs.h>
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 39e265c..048c429 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -19,6 +19,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/apm-emulation.h>
+#include <linux/io.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
index 88fbec0..b85b4ab 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
+#include <linux/io.h>
 
 #include <mach/pxa3xx-regs.h>
 
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 54b64ea..56d92e5 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -40,7 +40,6 @@
 #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
 
 #ifndef __ASSEMBLY__
-# define IOMEM(x) ((void __iomem *)(x))
 # define __REG(x)	(*((volatile u32 __iomem *)io_p2v(x)))
 
 /* With indexed regs we don't want to feed the index through io_p2v()
@@ -52,7 +51,6 @@
 
 #else
 
-# define IOMEM(x)	x 
 # define __REG(x)	io_p2v(x)
 # define __PREG(x)	io_v2p(x)
 
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index f147755..b029562 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -17,6 +17,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/syscore_ops.h>
 
 #include <mach/pxa2xx-regs.h>
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c
index 8682704..f8ec854 100644
--- a/arch/arm/mach-pxa/pxa2xx.c
+++ b/arch/arm/mach-pxa/pxa2xx.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/device.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <mach/pxa2xx-regs.h>
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 40bb165..17cbc0c 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <mach/pxa300.h>
 
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index 8d614ec..6dc99d4 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 
 #include <mach/pxa320.h>
 
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 8d5168d..6d3b39f 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -24,6 +24,7 @@
 #include <linux/leds.h>
 #include <linux/suspend.h>
 #include <linux/gpio.h>
+#include <linux/io.h>
 
 #include <asm/mach-types.h>
 #include <mach/pm.h>
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index cb9a585..398ab7a 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -30,6 +30,7 @@
 #include <linux/string.h>
 #include <linux/pm.h>
 #include <linux/bitops.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c
index 0162454..a3ff321 100644
--- a/drivers/watchdog/sa1100_wdt.c
+++ b/drivers/watchdog/sa1100_wdt.c
@@ -25,6 +25,7 @@
 #include <linux/miscdevice.h>
 #include <linux/watchdog.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/bitops.h>
 #include <linux/uaccess.h>
 #include <linux/timex.h>
diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c
index d1aa421..d760371 100644
--- a/sound/arm/pxa2xx-ac97-lib.c
+++ b/sound/arm/pxa2xx-ac97-lib.c
@@ -17,6 +17,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/module.h>
+#include <linux/io.h>
 
 #include <sound/ac97_codec.h>
 #include <sound/pxa2xx-lib.h>
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
index 3a39626..afef72c 100644
--- a/sound/arm/pxa2xx-ac97.c
+++ b/sound/arm/pxa2xx-ac97.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index 837ff34..b4bfd97 100644
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-- 
1.7.5.4



From subashrp at gmail.com  Thu Mar 22 09:45:02 2012
From: subashrp at gmail.com (Subash Patel)
Date: Thu, 22 Mar 2012 19:15:02 +0530
Subject: [PATCHv7 8/9] ARM: dma-mapping: use alloc, mmap, free from dma_ops
In-Reply-To: <1330527862-16234-9-git-send-email-m.szyprowski@samsung.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-9-git-send-email-m.szyprowski@samsung.com>
Message-ID: <4F6B2CDE.4020601@gmail.com>

Hello,

I have found out an issue with dma_mmap_writecombine() and coherent devices.

On 02/29/2012 08:34 PM, Marek Szyprowski wrote:
> This patch converts dma_alloc/free/mmap_{coherent,writecombine}
> functions to use generic alloc/free/mmap methods from dma_map_ops
> structure. A new DMA_ATTR_WRITE_COMBINE DMA attribute have been
> introduced to implement writecombine methods.
>
> Signed-off-by: Marek Szyprowski<m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park<kyungmin.park at samsung.com>
> ---
>   arch/arm/common/dmabounce.c        |    3 +
>   arch/arm/include/asm/dma-mapping.h |  107 ++++++++++++++++++++++++++----------
>   arch/arm/mm/dma-mapping.c          |   53 ++++++------------
>   3 files changed, 98 insertions(+), 65 deletions(-)
>
> diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
> index 119f487..dbae5ad 100644
> --- a/arch/arm/common/dmabounce.c
> +++ b/arch/arm/common/dmabounce.c
> @@ -449,6 +449,9 @@ static int dmabounce_set_mask(struct device *dev, u64 dma_mask)
>   }
>
>   static struct dma_map_ops dmabounce_ops = {
> +	.alloc			= arm_dma_alloc,
> +	.free			= arm_dma_free,
> +	.mmap			= arm_dma_mmap,
>   	.map_page		= dmabounce_map_page,
>   	.unmap_page		= dmabounce_unmap_page,
>   	.sync_single_for_cpu	= dmabounce_sync_for_cpu,
> diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
> index 266cba6..4342b75 100644
> --- a/arch/arm/include/asm/dma-mapping.h
> +++ b/arch/arm/include/asm/dma-mapping.h
> @@ -5,6 +5,7 @@
>
>   #include<linux/mm_types.h>
>   #include<linux/scatterlist.h>
> +#include<linux/dma-attrs.h>
>   #include<linux/dma-debug.h>
>
>   #include<asm-generic/dma-coherent.h>
> @@ -110,68 +111,115 @@ static inline void dma_free_noncoherent(struct device *dev, size_t size,
>   extern int dma_supported(struct device *dev, u64 mask);
>
>   /**
> - * dma_alloc_coherent - allocate consistent memory for DMA
> + * arm_dma_alloc - allocate consistent memory for DMA
>    * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
>    * @size: required memory size
>    * @handle: bus-specific DMA address
> + * @attrs: optinal attributes that specific mapping properties
>    *
> - * Allocate some uncached, unbuffered memory for a device for
> - * performing DMA.  This function allocates pages, and will
> - * return the CPU-viewed address, and sets @handle to be the
> - * device-viewed address.
> + * Allocate some memory for a device for performing DMA.  This function
> + * allocates pages, and will return the CPU-viewed address, and sets @handle
> + * to be the device-viewed address.
>    */
> -extern void *dma_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t);
> +extern void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
> +			   gfp_t gfp, struct dma_attrs *attrs);
> +
> +#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL)
> +
> +static inline void *dma_alloc_attrs(struct device *dev, size_t size,
> +				       dma_addr_t *dma_handle, gfp_t flag,
> +				       struct dma_attrs *attrs)
> +{
> +	struct dma_map_ops *ops = get_dma_ops(dev);
> +	void *cpu_addr;
> +	BUG_ON(!ops);
> +
> +	cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
> +	debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
> +	return cpu_addr;
> +}
>
>   /**
> - * dma_free_coherent - free memory allocated by dma_alloc_coherent
> + * arm_dma_free - free memory allocated by arm_dma_alloc
>    * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
>    * @size: size of memory originally requested in dma_alloc_coherent
>    * @cpu_addr: CPU-view address returned from dma_alloc_coherent
>    * @handle: device-view address returned from dma_alloc_coherent
> + * @attrs: optinal attributes that specific mapping properties
>    *
>    * Free (and unmap) a DMA buffer previously allocated by
> - * dma_alloc_coherent().
> + * arm_dma_alloc().
>    *
>    * References to memory and mappings associated with cpu_addr/handle
>    * during and after this call executing are illegal.
>    */
> -extern void dma_free_coherent(struct device *, size_t, void *, dma_addr_t);
> +extern void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
> +			 dma_addr_t handle, struct dma_attrs *attrs);
> +
> +#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
> +
> +static inline void dma_free_attrs(struct device *dev, size_t size,
> +				     void *cpu_addr, dma_addr_t dma_handle,
> +				     struct dma_attrs *attrs)
> +{
> +	struct dma_map_ops *ops = get_dma_ops(dev);
> +	BUG_ON(!ops);
> +
> +	debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
> +	ops->free(dev, size, cpu_addr, dma_handle, attrs);
> +}
>
>   /**
> - * dma_mmap_coherent - map a coherent DMA allocation into user space
> + * arm_dma_mmap - map a coherent DMA allocation into user space
>    * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
>    * @vma: vm_area_struct describing requested user mapping
>    * @cpu_addr: kernel CPU-view address returned from dma_alloc_coherent
>    * @handle: device-view address returned from dma_alloc_coherent
>    * @size: size of memory originally requested in dma_alloc_coherent
> + * @attrs: optinal attributes that specific mapping properties
>    *
>    * Map a coherent DMA buffer previously allocated by dma_alloc_coherent
>    * into user space.  The coherent DMA buffer must not be freed by the
>    * driver until the user space mapping has been released.
>    */
> -int dma_mmap_coherent(struct device *, struct vm_area_struct *,
> -		void *, dma_addr_t, size_t);
> +extern int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
> +			void *cpu_addr, dma_addr_t dma_addr, size_t size,
> +			struct dma_attrs *attrs);
>
> +#define dma_mmap_coherent(d,v,c,h,s) dma_mmap_attrs(d,v,c,h,s,NULL)
>
> -/**
> - * dma_alloc_writecombine - allocate writecombining memory for DMA
> - * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
> - * @size: required memory size
> - * @handle: bus-specific DMA address
> - *
> - * Allocate some uncached, buffered memory for a device for
> - * performing DMA.  This function allocates pages, and will
> - * return the CPU-viewed address, and sets @handle to be the
> - * device-viewed address.
> - */
> -extern void *dma_alloc_writecombine(struct device *, size_t, dma_addr_t *,
> -		gfp_t);
> +static inline int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
> +				  void *cpu_addr, dma_addr_t dma_addr,
> +				  size_t size, struct dma_attrs *attrs)
> +{
> +	struct dma_map_ops *ops = get_dma_ops(dev);
> +	BUG_ON(!ops);
> +	return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
> +}
>
> -#define dma_free_writecombine(dev,size,cpu_addr,handle) \
> -	dma_free_coherent(dev,size,cpu_addr,handle)
> +static inline void *dma_alloc_writecombine(struct device *dev, size_t size,
> +				       dma_addr_t *dma_handle, gfp_t flag)
> +{
> +	DEFINE_DMA_ATTRS(attrs);
> +	dma_set_attr(DMA_ATTR_WRITE_COMBINE,&attrs);
> +	return dma_alloc_attrs(dev, size, dma_handle, flag,&attrs);
> +}
>
> -int dma_mmap_writecombine(struct device *, struct vm_area_struct *,
> -		void *, dma_addr_t, size_t);
> +static inline void dma_free_writecombine(struct device *dev, size_t size,
> +				     void *cpu_addr, dma_addr_t dma_handle)
> +{
> +	DEFINE_DMA_ATTRS(attrs);
> +	dma_set_attr(DMA_ATTR_WRITE_COMBINE,&attrs);
> +	return dma_free_attrs(dev, size, cpu_addr, dma_handle,&attrs);
> +}
> +
> +static inline int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
> +		      void *cpu_addr, dma_addr_t dma_addr, size_t size)
> +{
> +	DEFINE_DMA_ATTRS(attrs);
> +	dma_set_attr(DMA_ATTR_WRITE_COMBINE,&attrs);
> +	return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size,&attrs);
> +}
>
For devices, which do not have a coherent/reserved pool, then the 
allocation in function __dma_alloc() happens, and the memory will be 
remapped by calling __dma_alloc_remap(). In the above function, 
arm_vmregion_find() will be called, and it succeeds to get the map and 
it will be mapped to used.

This has issues with devices with coherent memory. If we have any device 
which has declared coherent memory, then the allocation happens from 
per-device coherent area. Eg: Exynos MFC which declares: 
s5p_mfc_reserve_mem(). In that case, dma_mmap_writecombine() fails, and 
hence vb2_dc_mmap() fails as well.
>   /*
>    * This can be called during boot to increase the size of the consistent
> @@ -180,7 +228,6 @@ int dma_mmap_writecombine(struct device *, struct vm_area_struct *,
>    */
>   extern void __init init_consistent_dma_size(unsigned long size);
>
> -
>   /*
>    * For SA-1111, IXP425, and ADI systems  the dma-mapping functions are "magic"
>    * and utilize bounce buffers as needed to work around limited DMA windows.
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index cd54b2d..67fe7e2 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -113,6 +113,9 @@ static void arm_dma_sync_single_for_device(struct device *dev,
>   static int arm_dma_set_mask(struct device *dev, u64 dma_mask);
>
>   struct dma_map_ops arm_dma_ops = {
> +	.alloc			= arm_dma_alloc,
> +	.free			= arm_dma_free,
> +	.mmap			= arm_dma_mmap,
>   	.map_page		= arm_dma_map_page,
>   	.unmap_page		= arm_dma_unmap_page,
>   	.map_sg			= arm_dma_map_sg,
> @@ -461,33 +464,26 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
>    * Allocate DMA-coherent memory space and return both the kernel remapped
>    * virtual and bus address for that space.
>    */
> -void *
> -dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp)
> +void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
> +		    gfp_t gfp, struct dma_attrs *attrs)
>   {
> +	pgprot_t prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
> +			pgprot_writecombine(pgprot_kernel) :
> +			pgprot_dmacoherent(pgprot_kernel);
>   	void *memory;
>
>   	if (dma_alloc_from_coherent(dev, size, handle,&memory))
>   		return memory;
>
> -	return __dma_alloc(dev, size, handle, gfp,
> -			   pgprot_dmacoherent(pgprot_kernel));
> +	return __dma_alloc(dev, size, handle, gfp, prot);
>   }
> -EXPORT_SYMBOL(dma_alloc_coherent);
>
>   /*
> - * Allocate a writecombining region, in much the same way as
> - * dma_alloc_coherent above.
> + * Create userspace mapping for the DMA-coherent memory.
>    */
> -void *
> -dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp)
> -{
> -	return __dma_alloc(dev, size, handle, gfp,
> -			   pgprot_writecombine(pgprot_kernel));
> -}
> -EXPORT_SYMBOL(dma_alloc_writecombine);
> -
> -static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
> -		    void *cpu_addr, dma_addr_t dma_addr, size_t size)
> +int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
> +		 void *cpu_addr, dma_addr_t dma_addr, size_t size,
> +		 struct dma_attrs *attrs)
>   {
>   	int ret = -ENXIO;
>   #ifdef CONFIG_MMU
> @@ -495,6 +491,9 @@ static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
>   	struct arm_vmregion *c;
>
>   	user_size = (vma->vm_end - vma->vm_start)>>  PAGE_SHIFT;
> +	vma->vm_page_prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
> +			    pgprot_writecombine(vma->vm_page_prot) :
> +			    pgprot_dmacoherent(vma->vm_page_prot);
>
>   	c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
>   	if (c) {
> @@ -515,27 +514,12 @@ static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
>   	return ret;
>   }
>
> -int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
> -		      void *cpu_addr, dma_addr_t dma_addr, size_t size)
> -{
> -	vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot);
> -	return dma_mmap(dev, vma, cpu_addr, dma_addr, size);
> -}
> -EXPORT_SYMBOL(dma_mmap_coherent);
> -
> -int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
> -			  void *cpu_addr, dma_addr_t dma_addr, size_t size)
> -{
> -	vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
> -	return dma_mmap(dev, vma, cpu_addr, dma_addr, size);
> -}
> -EXPORT_SYMBOL(dma_mmap_writecombine);
> -
>   /*
>    * free a page as defined by the above mapping.
>    * Must not be called with IRQs disabled.
>    */
> -void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
> +void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
> +		  dma_addr_t handle, struct dma_attrs *attrs)
>   {
>   	WARN_ON(irqs_disabled());
>
> @@ -549,7 +533,6 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr
>
>   	__dma_free_buffer(pfn_to_page(dma_to_pfn(dev, handle)), size);
>   }
> -EXPORT_SYMBOL(dma_free_coherent);
>
>   static void dma_cache_maint_page(struct page *page, unsigned long offset,
>   	size_t size, enum dma_data_direction dir,
Regards,
Subash


From javier.martin at vista-silicon.com  Thu Mar 22 09:54:00 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:00 +0100
Subject: [PATCH v4 00/15] dmaengine: imx-dma: rebase of features for 3.4.
Message-ID: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>

Hi, 
as requested by Vinod yesterday, this is a rebase onto 'next' branch of 
all imx-dma pending changes for 3.4.

It is utterly important for us that these changes make into mainline 
for 3.4. 

I will be out of the office until next Monday so please Vinod, if you 
see any minor issue could you just merge it so that I can send a small
fix next week in order not to miss the merge window?

[PATCH v4 01/15] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
[PATCH v4 02/15] dmaengine: imx-dma: remove data member from internal structure.
[PATCH v4 03/15] dmaengine: imx-dma: remove dma_mode member of internal structure.
[PATCH v4 04/15] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw' function.
[PATCH v4 05/15] dmaengine: imx-dma: remove 'imxdma_config_channel_hw' function.
[PATCH v4 06/15] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw' function.
[PATCH v4 07/15] dmaengine: imx-dma: remove sg member from internal structure.
[PATCH v4 08/15] dmaengine: imx-dma: remove 'in_use' field of 'internal' structure.
[PATCH v4 09/15] dmaengine: imx-dma: remove 'resbytes' field of 'internal' structure.
[PATCH v4 10/15] dmaengine: imx-dma: remove internal structure.
[PATCH v4 11/15] dmaengine: imx-dma: remove unused arg of imxdma_sg_next.
[PATCH v4 12/15] dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and 'dma_clk'.
[PATCH v4 13/15] dmaengine: imx-dma: use 'dev_dbg' and 'dev_warn' for messages.
[PATCH v4 14/15] dmaengine: i.MX: Add support for interleaved transfers.
[PATCH v4 15/15] dmaengine: i.MX: Fix merge of cookie branch.


From javier.martin at vista-silicon.com  Thu Mar 22 09:54:02 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:02 +0100
Subject: [PATCH v4 02/15] dmaengine: imx-dma: remove data member from internal
 structure.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-3-git-send-email-javier.martin@vista-silicon.com>

Internal structure is just an auxiliary structure used for the initial
merge which is meant to be gone. As data member is not use anywhere
we can simply remove it.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index fbb1aaa..8603c75 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -133,7 +133,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	void *data;
 	unsigned int dma_mode;
 	struct scatterlist *sg;
 	unsigned int resbytes;
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:03 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:03 +0100
Subject: [PATCH v4 03/15] dmaengine: imx-dma: remove dma_mode member of
 internal structure.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-4-git-send-email-javier.martin@vista-silicon.com>

dmaengine now provides 'enum dma_transfer_direction' to properly
specify DMA transfer direction. For this reason, DMA_MODE_* defines
are replaced by this new type and therefore dma_mode member becomes
redundant.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |  103 +++++++++++++++++++++---------------------------
 1 files changed, 45 insertions(+), 58 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 8603c75..04a2c14 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -36,10 +36,6 @@
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
 #define IMX_DMA_CHANNELS  16
 
-#define DMA_MODE_READ		0
-#define DMA_MODE_WRITE		1
-#define DMA_MODE_MASK		1
-
 #define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
 #define IMX_DMA_MEMSIZE_32	(0 << 4)
 #define IMX_DMA_MEMSIZE_8	(1 << 4)
@@ -133,7 +129,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	unsigned int dma_mode;
 	struct scatterlist *sg;
 	unsigned int resbytes;
 
@@ -154,7 +149,7 @@ struct imxdma_desc {
 	dma_addr_t			src;
 	dma_addr_t			dest;
 	size_t				len;
-	unsigned int			dmamode;
+	enum dma_transfer_direction	direction;
 	enum imxdma_prep_type		type;
 	/* For memcpy and interleaved */
 	unsigned int			config_port;
@@ -239,8 +234,9 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
 /*
  * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
  */
-static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	unsigned long now;
 
@@ -248,7 +244,7 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
 	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
 		imxdma->resbytes -= now;
 
-	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+	if (d->direction == DMA_DEV_TO_MEM)
 		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
 	else
 		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
@@ -265,14 +261,12 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
 }
 
 static int
-imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr,
-		     unsigned int dmamode)
+imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+		     unsigned int dma_length, unsigned int dev_addr)
 {
 	int channel = imxdmac->channel;
 
 	imxdmac->internal.sg = NULL;
-	imxdmac->internal.dma_mode = dmamode;
 
 	if (!dma_address) {
 		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
@@ -286,38 +280,24 @@ imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
 		return -EINVAL;
 	}
 
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
+	pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+		"dev_addr=0x%08x for write\n",
+		channel, __func__, (unsigned int)dma_address,
+		dma_length, dev_addr);
 
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(dma_address, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dma_address, DMA_SAR(channel));
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_to_device,
-				DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
+	imx_dmav1_writel(dma_address, DMA_SAR(channel));
+	imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+	imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+			 DMA_CCR(channel));
 
 	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
 
 	return 0;
 }
 
-static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+static void imxdma_enable_hw(struct imxdma_desc *d)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -338,7 +318,7 @@ static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
 		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
 		if (imxdmac->internal.sg) {
 			u32 tmp;
-			imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+			imxdma_sg_next(d, imxdmac->internal.sg);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -395,18 +375,18 @@ imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_por
 }
 
 static int
-imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+imxdma_setup_sg_hw(struct imxdma_desc *d,
 		 struct scatterlist *sg, unsigned int sgcount,
 		 unsigned int dma_length, unsigned int dev_addr,
-		 unsigned int dmamode)
+		 enum dma_transfer_direction direction)
 {
+	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	int channel = imxdmac->channel;
 
 	if (imxdmac->internal.in_use)
 		return -EBUSY;
 
 	imxdmac->internal.sg = sg;
-	imxdmac->internal.dma_mode = dmamode;
 	imxdmac->internal.resbytes = dma_length;
 
 	if (!sg || !sgcount) {
@@ -421,14 +401,14 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
 		return -EINVAL;
 	}
 
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+	if (direction == DMA_DEV_TO_MEM) {
 		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
 			"dev_addr=0x%08x for read\n",
 			channel, __func__, sg, sgcount, dma_length, dev_addr);
 
 		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
 		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+	} else if (direction == DMA_MEM_TO_DEV) {
 		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
 			"dev_addr=0x%08x for write\n",
 			channel, __func__, sg, sgcount, dma_length, dev_addr);
@@ -441,7 +421,7 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
 		return -EINVAL;
 	}
 
-	imxdma_sg_next(imxdmac, sg);
+	imxdma_sg_next(d, sg);
 
 	return 0;
 }
@@ -519,13 +499,26 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
 	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	int chno = imxdmac->channel;
+	struct imxdma_desc *desc;
 
 	if (imxdma->sg) {
 		u32 tmp;
 		imxdma->sg = sg_next(imxdma->sg);
 
 		if (imxdma->sg) {
-			imxdma_sg_next(imxdmac, imxdma->sg);
+
+			spin_lock(&imxdmac->lock);
+			if (list_empty(&imxdmac->ld_active)) {
+				spin_unlock(&imxdmac->lock);
+				goto out;
+			}
+
+			desc = list_first_entry(&imxdmac->ld_active,
+						struct imxdma_desc,
+						node);
+			spin_unlock(&imxdmac->lock);
+
+			imxdma_sg_next(desc, imxdma->sg);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -558,6 +551,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		}
 	}
 
+out:
 	imx_dmav1_writel(0, DMA_CCR(chno));
 	imxdma->in_use = 0;
 	/* Tasklet irq */
@@ -601,8 +595,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 					  d->config_port, d->config_mem, 0, 0);
 		if (ret < 0)
 			return ret;
-		ret = imxdma_setup_single_hw(imxdmac, d->src,
-					   d->len, d->dest, d->dmamode);
+		ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
 		if (ret < 0)
 			return ret;
 		break;
@@ -610,19 +603,15 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		if (d->dmamode == DMA_MODE_READ)
-			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
-				       d->sgcount, d->len, d->src, d->dmamode);
-		else
-			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
-				      d->sgcount, d->len, d->dest, d->dmamode);
+		ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
+					 imxdmac->per_address, d->direction);
 		if (ret < 0)
 			return ret;
 		break;
 	default:
 		return -EINVAL;
 	}
-	imxdma_enable_hw(imxdmac);
+	imxdma_enable_hw(d);
 	return 0;
 }
 
@@ -839,11 +828,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
 	desc->sg = sgl;
 	desc->sgcount = sg_len;
 	desc->len = dma_length;
+	desc->direction = direction;
 	if (direction == DMA_DEV_TO_MEM) {
-		desc->dmamode = DMA_MODE_READ;
 		desc->src = imxdmac->per_address;
 	} else {
-		desc->dmamode = DMA_MODE_WRITE;
 		desc->dest = imxdmac->per_address;
 	}
 	desc->desc.callback = NULL;
@@ -900,11 +888,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
 	desc->sg = imxdmac->sg_list;
 	desc->sgcount = periods;
 	desc->len = IMX_DMA_LENGTH_LOOP;
+	desc->direction = direction;
 	if (direction == DMA_DEV_TO_MEM) {
-		desc->dmamode = DMA_MODE_READ;
 		desc->src = imxdmac->per_address;
 	} else {
-		desc->dmamode = DMA_MODE_WRITE;
 		desc->dest = imxdmac->per_address;
 	}
 	desc->desc.callback = NULL;
@@ -934,7 +921,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
 	desc->src = src;
 	desc->dest = dest;
 	desc->len = len;
-	desc->dmamode = DMA_MODE_WRITE;
+	desc->direction = DMA_MEM_TO_MEM;
 	desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 	desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 	desc->desc.callback = NULL;
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:04 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:04 +0100
Subject: [PATCH v4 04/15] dmaengine: imx-dma: remove 'imxdma_setup_mem2mem_hw'
 function.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-5-git-send-email-javier.martin@vista-silicon.com>

This function is only used once in the driver and has a lot of checks
that are not needed anymore. For this reason it's been merged
with 'imxdma_enable_hw'.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   57 ++++++++++++-------------------------------------
 1 files changed, 14 insertions(+), 43 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 04a2c14..dcb2c70 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -260,41 +260,6 @@ static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 	return now;
 }
 
-static int
-imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr)
-{
-	int channel = imxdmac->channel;
-
-	imxdmac->internal.sg = NULL;
-
-	if (!dma_address) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!dma_length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-		"dev_addr=0x%08x for write\n",
-		channel, __func__, (unsigned int)dma_address,
-		dma_length, dev_addr);
-
-	imx_dmav1_writel(dma_address, DMA_SAR(channel));
-	imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-	imx_dmav1_writel(imxdmac->internal.ccr_to_device,
-			 DMA_CCR(channel));
-
-	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
-	return 0;
-}
-
 static void imxdma_enable_hw(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -586,20 +551,26 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int ret;
 
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		ret = imxdma_config_channel_hw(imxdmac,
-					  d->config_port, d->config_mem, 0, 0);
-		if (ret < 0)
-			return ret;
-		ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
-		if (ret < 0)
-			return ret;
-		break;
+		imxdmac->internal.sg = NULL;
+
+		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+			 DMA_CCR(imxdmac->channel));
 
+		imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+
+		dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
+			"dma_length=%d\n", __func__, imxdmac->channel,
+			d->dest, d->src, d->len);
+
+		break;
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:05 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:05 +0100
Subject: [PATCH v4 05/15] dmaengine: imx-dma: remove
 'imxdma_config_channel_hw' function.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-6-git-send-email-javier.martin@vista-silicon.com>

This function is only used once in the driver and uses some
intermediary variables that are not needed anymore. For this
reason it's been merged with 'imxdma_control'.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   46 +++++++++++++---------------------------------
 1 files changed, 13 insertions(+), 33 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index dcb2c70..25b4108 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -314,32 +314,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 }
 
 static int
-imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
-	int channel = imxdmac->channel;
-	u32 dreq = 0;
-
-	imxdmac->internal.hw_chaining = 0;
-
-	if (hw_chaining) {
-		imxdmac->internal.hw_chaining = 1;
-		if (!imxdma_hw_chain(&imxdmac->internal))
-			return -EINVAL;
-	}
-
-	if (dmareq)
-		dreq = CCR_REN;
-
-	imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
-	imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
-
-	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
-	return 0;
-}
-
-static int
 imxdma_setup_sg_hw(struct imxdma_desc *d,
 		 struct scatterlist *sg, unsigned int sgcount,
 		 unsigned int dma_length, unsigned int dev_addr,
@@ -628,7 +602,6 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct dma_slave_config *dmaengine_cfg = (void *)arg;
-	int ret;
 	unsigned long flags;
 	unsigned int mode = 0;
 
@@ -664,13 +637,20 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			mode = IMX_DMA_MEMSIZE_32;
 			break;
 		}
-		ret = imxdma_config_channel_hw(imxdmac,
-				mode | IMX_DMA_TYPE_FIFO,
-				IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
-				imxdmac->dma_request, 1);
 
-		if (ret)
-			return ret;
+		imxdmac->internal.hw_chaining = 1;
+		if (!imxdma_hw_chain(&imxdmac->internal))
+			return -EINVAL;
+		imxdmac->internal.ccr_from_device =
+			(mode | IMX_DMA_TYPE_FIFO) |
+			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
+			CCR_REN;
+		imxdmac->internal.ccr_to_device =
+			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
+			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
+		imx_dmav1_writel(imxdmac->dma_request,
+				 DMA_RSSR(imxdmac->channel));
+
 		/* Set burst length */
 		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
 				 DMA_BLR(imxdmac->channel));
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:01 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:01 +0100
Subject: [PATCH v4 01/15] dmaengine: imx-dma: merge old dma-v1.c with imx-dma.c
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-2-git-send-email-javier.martin@vista-silicon.com>

It is mainly a simple merge changing the prefix of some
functions to fit the imx-dma namings.

As there are no users of the old dma-v1.c api we can safely
remove this file.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/mach-imx/Kconfig               |    6 -
 arch/arm/mach-imx/Makefile              |    2 -
 arch/arm/mach-imx/dma-v1.c              |  846 -------------------------------
 arch/arm/mach-imx/include/mach/dma-v1.h |  103 ----
 drivers/dma/Kconfig                     |    1 -
 drivers/dma/imx-dma.c                   |  604 ++++++++++++++++++++--
 6 files changed, 552 insertions(+), 1010 deletions(-)
 delete mode 100644 arch/arm/mach-imx/dma-v1.c
 delete mode 100644 arch/arm/mach-imx/include/mach/dma-v1.h

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0e6de36..3da1421 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,6 +1,3 @@
-config IMX_HAVE_DMA_V1
-	bool
-
 config HAVE_IMX_GPC
 	bool
 
@@ -26,7 +23,6 @@ config SOC_IMX1
 	bool
 	select ARCH_MX1
 	select CPU_ARM920T
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
@@ -35,7 +31,6 @@ config SOC_IMX21
 	select MACH_MX21
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
@@ -52,7 +47,6 @@ config SOC_IMX27
 	select MACH_MX27
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	select MXC_AVIC
 
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f5920c2..a62dc3a 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,5 +1,3 @@
-obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
-
 obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
 obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
 
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
deleted file mode 100644
index 42afc29..0000000
--- a/arch/arm/mach-imx/dma-v1.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/*
- *  linux/arch/arm/plat-mxc/dma-v1.c
- *
- *  i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/scatterlist.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/dma-v1.h>
-
-#define DMA_DCR     0x00		/* Control Register */
-#define DMA_DISR    0x04		/* Interrupt status Register */
-#define DMA_DIMR    0x08		/* Interrupt mask Register */
-#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
-#define DMA_DRTOSR  0x10		/* Request timeout Register */
-#define DMA_DSESR   0x14		/* Transfer Error Status Register */
-#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
-#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
-#define DMA_WSRA    0x40		/* W-Size Register A */
-#define DMA_XSRA    0x44		/* X-Size Register A */
-#define DMA_YSRA    0x48		/* Y-Size Register A */
-#define DMA_WSRB    0x4c		/* W-Size Register B */
-#define DMA_XSRB    0x50		/* X-Size Register B */
-#define DMA_YSRB    0x54		/* Y-Size Register B */
-#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
-#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
-#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
-#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
-#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
-#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
-#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
-#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
-#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */
-
-#define DCR_DRST           (1<<1)
-#define DCR_DEN            (1<<0)
-#define DBTOCR_EN          (1<<15)
-#define DBTOCR_CNT(x)      ((x) & 0x7fff)
-#define CNTR_CNT(x)        ((x) & 0xffffff)
-#define CCR_ACRPT          (1<<14)
-#define CCR_DMOD_LINEAR    (0x0 << 12)
-#define CCR_DMOD_2D        (0x1 << 12)
-#define CCR_DMOD_FIFO      (0x2 << 12)
-#define CCR_DMOD_EOBFIFO   (0x3 << 12)
-#define CCR_SMOD_LINEAR    (0x0 << 10)
-#define CCR_SMOD_2D        (0x1 << 10)
-#define CCR_SMOD_FIFO      (0x2 << 10)
-#define CCR_SMOD_EOBFIFO   (0x3 << 10)
-#define CCR_MDIR_DEC       (1<<9)
-#define CCR_MSEL_B         (1<<8)
-#define CCR_DSIZ_32        (0x0 << 6)
-#define CCR_DSIZ_8         (0x1 << 6)
-#define CCR_DSIZ_16        (0x2 << 6)
-#define CCR_SSIZ_32        (0x0 << 4)
-#define CCR_SSIZ_8         (0x1 << 4)
-#define CCR_SSIZ_16        (0x2 << 4)
-#define CCR_REN            (1<<3)
-#define CCR_RPT            (1<<2)
-#define CCR_FRC            (1<<1)
-#define CCR_CEN            (1<<0)
-#define RTOR_EN            (1<<15)
-#define RTOR_CLK           (1<<14)
-#define RTOR_PSC           (1<<13)
-
-/*
- * struct imx_dma_channel - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- *            (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imx_dma_channel only as extension to it.
- */
-
-struct imx_dma_channel {
-	const char *name;
-	void (*irq_handler) (int, void *);
-	void (*err_handler) (int, void *, int errcode);
-	void (*prog_handler) (int, void *, struct scatterlist *);
-	void *data;
-	unsigned int dma_mode;
-	struct scatterlist *sg;
-	unsigned int resbytes;
-	int dma_num;
-
-	int in_use;
-
-	u32 ccr_from_device;
-	u32 ccr_to_device;
-
-	struct timer_list watchdog;
-
-	int hw_chaining;
-};
-
-static void __iomem *imx_dmav1_baseaddr;
-
-static void imx_dmav1_writel(unsigned val, unsigned offset)
-{
-	__raw_writel(val, imx_dmav1_baseaddr + offset);
-}
-
-static unsigned imx_dmav1_readl(unsigned offset)
-{
-	return __raw_readl(imx_dmav1_baseaddr + offset);
-}
-
-static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
-
-static struct clk *dma_clk;
-
-static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
-{
-	if (cpu_is_mx27())
-		return imxdma->hw_chaining;
-	else
-		return 0;
-}
-
-/*
- * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
- */
-static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long now;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return 0;
-	}
-
-	now = min(imxdma->resbytes, sg->length);
-	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
-		imxdma->resbytes -= now;
-
-	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
-		imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
-	else
-		imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
-
-	imx_dmav1_writel(now, DMA_CNTR(channel));
-
-	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
-		"size 0x%08x\n", channel,
-		 imx_dmav1_readl(DMA_DAR(channel)),
-		 imx_dmav1_readl(DMA_SAR(channel)),
-		 imx_dmav1_readl(DMA_CNTR(channel)));
-
-	return now;
-}
-
-/**
- * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
- * device transfer
- *
- * @channel: i.MX DMA channel number
- * @dma_address: the DMA/physical memory address of the linear data block
- *		to transfer
- * @dma_length: length of the data block in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- *		Zero indicates success.
- */
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr,
-		     unsigned int dmamode)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	imxdma->sg = NULL;
-	imxdma->dma_mode = dmamode;
-
-	if (!dma_address) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!dma_length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(dma_address, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dma_address, DMA_SAR(channel));
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_to_device,
-				DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_single);
-
-/**
- * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
- * @channel: i.MX DMA channel number
- * @sg: pointer to the scatter-gather list/vector
- * @sgcount: scatter-gather list hungs count
- * @dma_length: total length of the transfer request in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * The function sets up DMA channel state and registers to be ready for
- * transfer specified by provided parameters. The scatter-gather emulation
- * is set up according to the parameters.
- *
- * The full preparation of the transfer requires setup of more register
- * by the caller before imx_dma_enable() can be called.
- *
- * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
- *
- * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
- *
- * %CCR(channel) has to specify transfer parameters, the next settings is
- * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
- * specified
- *
- * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
- *
- * The typical setup for %DMA_MODE_WRITE is specified by next options
- * combination
- *
- * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
- *
- * Be careful here and do not mistakenly mix source and target device
- * port sizes constants, they are really different:
- * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
- * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- * Zero indicates success.
- */
-int
-imx_dma_setup_sg(int channel,
-		 struct scatterlist *sg, unsigned int sgcount,
-		 unsigned int dma_length, unsigned int dev_addr,
-		 unsigned int dmamode)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	if (imxdma->in_use)
-		return -EBUSY;
-
-	imxdma->sg = sg;
-	imxdma->dma_mode = dmamode;
-	imxdma->resbytes = dma_length;
-
-	if (!sg || !sgcount) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!sg->length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imx_dma_sg_next(channel, sg);
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_sg);
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	u32 dreq = 0;
-
-	imxdma->hw_chaining = 0;
-
-	if (hw_chaining) {
-		imxdma->hw_chaining = 1;
-		if (!imx_dma_hw_chain(imxdma))
-			return -EINVAL;
-	}
-
-	if (dmareq)
-		dreq = CCR_REN;
-
-	imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
-	imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
-
-	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_config_channel);
-
-void imx_dma_config_burstlen(int channel, unsigned int burstlen)
-{
-	imx_dmav1_writel(burstlen, DMA_BLR(channel));
-}
-EXPORT_SYMBOL(imx_dma_config_burstlen);
-
-/**
- * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
- * handlers
- * @channel: i.MX DMA channel number
- * @irq_handler: the pointer to the function called if the transfer
- *		ends successfully
- * @err_handler: the pointer to the function called if the premature
- *		end caused by error occurs
- * @data: user specified value to be passed to the handlers
- */
-int
-imx_dma_setup_handlers(int channel,
-		       void (*irq_handler) (int, void *),
-		       void (*err_handler) (int, void *, int),
-		       void *data)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return -ENODEV;
-	}
-
-	local_irq_save(flags);
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdma->irq_handler = irq_handler;
-	imxdma->err_handler = err_handler;
-	imxdma->data = data;
-	local_irq_restore(flags);
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_handlers);
-
-/**
- * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
- * handlers
- * @channel: i.MX DMA channel number
- * @prog_handler: the pointer to the function called if the transfer progresses
- */
-int
-imx_dma_setup_progression_handler(int channel,
-			void (*prog_handler) (int, void*, struct scatterlist*))
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return -ENODEV;
-	}
-
-	local_irq_save(flags);
-	imxdma->prog_handler = prog_handler;
-	local_irq_restore(flags);
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_progression_handler);
-
-/**
- * imx_dma_enable - function to start i.MX DMA channel operation
- * @channel: i.MX DMA channel number
- *
- * The channel has to be allocated by driver through imx_dma_request()
- * or imx_dma_request_by_prio() function.
- * The transfer parameters has to be set to the channel registers through
- * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
- * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
- * be set prior this function call by the channel user.
- */
-void imx_dma_enable(int channel)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	pr_debug("imxdma%d: imx_dma_enable\n", channel);
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return;
-	}
-
-	if (imxdma->in_use)
-		return;
-
-	local_irq_save(flags);
-
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
-		CCR_ACRPT, DMA_CCR(channel));
-
-	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			imxdma->sg && imx_dma_hw_chain(imxdma)) {
-		imxdma->sg = sg_next(imxdma->sg);
-		if (imxdma->sg) {
-			u32 tmp;
-			imx_dma_sg_next(channel, imxdma->sg);
-			tmp = imx_dmav1_readl(DMA_CCR(channel));
-			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
-				DMA_CCR(channel));
-		}
-	}
-	imxdma->in_use = 1;
-
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_enable);
-
-/**
- * imx_dma_disable - stop, finish i.MX DMA channel operatin
- * @channel: i.MX DMA channel number
- */
-void imx_dma_disable(int channel)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	pr_debug("imxdma%d: imx_dma_disable\n", channel);
-
-	if (imx_dma_hw_chain(imxdma))
-		del_timer(&imxdma->watchdog);
-
-	local_irq_save(flags);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
-			DMA_CCR(channel));
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdma->in_use = 0;
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_disable);
-
-static void imx_dma_watchdog(unsigned long chno)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
-	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
-	imxdma->sg = NULL;
-
-	if (imxdma->err_handler)
-		imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
-}
-
-static irqreturn_t dma_err_handler(int irq, void *dev_id)
-{
-	int i, disr;
-	struct imx_dma_channel *imxdma;
-	unsigned int err_mask;
-	int errcode;
-
-	disr = imx_dmav1_readl(DMA_DISR);
-
-	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
-		   imx_dmav1_readl(DMA_DRTOSR) |
-		   imx_dmav1_readl(DMA_DSESR)  |
-		   imx_dmav1_readl(DMA_DBOSR);
-
-	if (!err_mask)
-		return IRQ_HANDLED;
-
-	imx_dmav1_writel(disr & err_mask, DMA_DISR);
-
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (!(err_mask & (1 << i)))
-			continue;
-		imxdma = &imx_dma_channels[i];
-		errcode = 0;
-
-		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBTOSR);
-			errcode |= IMX_DMA_ERR_BURST;
-		}
-		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DRTOSR);
-			errcode |= IMX_DMA_ERR_REQUEST;
-		}
-		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DSESR);
-			errcode |= IMX_DMA_ERR_TRANSFER;
-		}
-		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBOSR);
-			errcode |= IMX_DMA_ERR_BUFFER;
-		}
-		if (imxdma->name && imxdma->err_handler) {
-			imxdma->err_handler(i, imxdma->data, errcode);
-			continue;
-		}
-
-		imx_dma_channels[i].sg = NULL;
-
-		printk(KERN_WARNING
-		       "DMA timeout on channel %d (%s) -%s%s%s%s\n",
-		       i, imxdma->name,
-		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
-		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
-		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
-		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
-	}
-	return IRQ_HANDLED;
-}
-
-static void dma_irq_handle_channel(int chno)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
-	if (!imxdma->name) {
-		/*
-		 * IRQ for an unregistered DMA channel:
-		 * let's clear the interrupts and disable it.
-		 */
-		printk(KERN_WARNING
-		       "spurious IRQ for DMA channel %d\n", chno);
-		return;
-	}
-
-	if (imxdma->sg) {
-		u32 tmp;
-		struct scatterlist *current_sg = imxdma->sg;
-		imxdma->sg = sg_next(imxdma->sg);
-
-		if (imxdma->sg) {
-			imx_dma_sg_next(chno, imxdma->sg);
-
-			tmp = imx_dmav1_readl(DMA_CCR(chno));
-
-			if (imx_dma_hw_chain(imxdma)) {
-				/* FIXME: The timeout should probably be
-				 * configurable
-				 */
-				mod_timer(&imxdma->watchdog,
-					jiffies + msecs_to_jiffies(500));
-
-				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
-				imx_dmav1_writel(tmp, DMA_CCR(chno));
-			} else {
-				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
-				tmp |= CCR_CEN;
-			}
-
-			imx_dmav1_writel(tmp, DMA_CCR(chno));
-
-			if (imxdma->prog_handler)
-				imxdma->prog_handler(chno, imxdma->data,
-						current_sg);
-
-			return;
-		}
-
-		if (imx_dma_hw_chain(imxdma)) {
-			del_timer(&imxdma->watchdog);
-			return;
-		}
-	}
-
-	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
-	if (imxdma->irq_handler)
-		imxdma->irq_handler(chno, imxdma->data);
-}
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-	int i, disr;
-
-	if (cpu_is_mx21() || cpu_is_mx27())
-		dma_err_handler(irq, dev_id);
-
-	disr = imx_dmav1_readl(DMA_DISR);
-
-	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
-		     disr);
-
-	imx_dmav1_writel(disr, DMA_DISR);
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (disr & (1 << i))
-			dma_irq_handle_channel(i);
-	}
-
-	return IRQ_HANDLED;
-}
-
-/**
- * imx_dma_request - request/allocate specified channel number
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- */
-int imx_dma_request(int channel, const char *name)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-	int ret = 0;
-
-	/* basic sanity checks */
-	if (!name)
-		return -EINVAL;
-
-	if (channel >= IMX_DMA_CHANNELS) {
-		printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
-		       __func__, channel);
-		return -EINVAL;
-	}
-
-	local_irq_save(flags);
-	if (imxdma->name) {
-		local_irq_restore(flags);
-		return -EBUSY;
-	}
-	memset(imxdma, 0, sizeof(*imxdma));
-	imxdma->name = name;
-	local_irq_restore(flags); /* request_irq() can block */
-
-	if (cpu_is_mx21() || cpu_is_mx27()) {
-		ret = request_irq(MX2x_INT_DMACH0 + channel,
-				dma_irq_handler, 0, "DMA", NULL);
-		if (ret) {
-			imxdma->name = NULL;
-			pr_crit("Can't register IRQ %d for DMA channel %d\n",
-					MX2x_INT_DMACH0 + channel, channel);
-			return ret;
-		}
-		init_timer(&imxdma->watchdog);
-		imxdma->watchdog.function = &imx_dma_watchdog;
-		imxdma->watchdog.data = channel;
-	}
-
-	return ret;
-}
-EXPORT_SYMBOL(imx_dma_request);
-
-/**
- * imx_dma_free - release previously acquired channel
- * @channel: i.MX DMA channel number
- */
-void imx_dma_free(int channel)
-{
-	unsigned long flags;
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT
-		       "%s: trying to free free channel %d\n",
-		       __func__, channel);
-		return;
-	}
-
-	local_irq_save(flags);
-	/* Disable interrupts */
-	imx_dma_disable(channel);
-	imxdma->name = NULL;
-
-	if (cpu_is_mx21() || cpu_is_mx27())
-		free_irq(MX2x_INT_DMACH0 + channel, NULL);
-
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_free);
-
-/**
- * imx_dma_request_by_prio - find and request some of free channels best
- * suiting requested priority
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- *
- * This function tries to find a free channel in the specified priority group
- * if the priority cannot be achieved it tries to look for free channel
- * in the higher and then even lower priority groups.
- *
- * Return value: If there is no free channel to allocate, -%ENODEV is returned.
- *               On successful allocation channel is returned.
- */
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
-{
-	int i;
-	int best;
-
-	switch (prio) {
-	case (DMA_PRIO_HIGH):
-		best = 8;
-		break;
-	case (DMA_PRIO_MEDIUM):
-		best = 4;
-		break;
-	case (DMA_PRIO_LOW):
-	default:
-		best = 0;
-		break;
-	}
-
-	for (i = best; i < IMX_DMA_CHANNELS; i++)
-		if (!imx_dma_request(i, name))
-			return i;
-
-	for (i = best - 1; i >= 0; i--)
-		if (!imx_dma_request(i, name))
-			return i;
-
-	printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
-
-	return -ENODEV;
-}
-EXPORT_SYMBOL(imx_dma_request_by_prio);
-
-static int __init imx_dma_init(void)
-{
-	int ret = 0;
-	int i;
-
-	if (cpu_is_mx1())
-		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
-	else if (cpu_is_mx21())
-		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
-	else if (cpu_is_mx27())
-		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
-	else
-		return 0;
-
-	dma_clk = clk_get(NULL, "dma");
-	if (IS_ERR(dma_clk))
-		return PTR_ERR(dma_clk);
-	clk_enable(dma_clk);
-
-	/* reset DMA module */
-	imx_dmav1_writel(DCR_DRST, DMA_DCR);
-
-	if (cpu_is_mx1()) {
-		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
-		if (ret) {
-			pr_crit("Wow!  Can't register IRQ for DMA\n");
-			return ret;
-		}
-
-		ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
-		if (ret) {
-			pr_crit("Wow!  Can't register ERRIRQ for DMA\n");
-			free_irq(MX1_DMA_INT, NULL);
-			return ret;
-		}
-	}
-
-	/* enable DMA module */
-	imx_dmav1_writel(DCR_DEN, DMA_DCR);
-
-	/* clear all interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
-
-	/* disable interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		imx_dma_channels[i].sg = NULL;
-		imx_dma_channels[i].dma_num = i;
-	}
-
-	return ret;
-}
-
-arch_initcall(imx_dma_init);
diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h
deleted file mode 100644
index ac6fd71..0000000
--- a/arch/arm/mach-imx/include/mach/dma-v1.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- *  linux/arch/arm/mach-imx/include/mach/dma-v1.h
- *
- *  i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_DMA_V1_H__
-#define __MACH_DMA_V1_H__
-
-#define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
-
-#include <mach/dma.h>
-
-#define IMX_DMA_CHANNELS  16
-
-#define DMA_MODE_READ		0
-#define DMA_MODE_WRITE		1
-#define DMA_MODE_MASK		1
-
-#define MX1_DMA_REG(offset)	MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
-
-/* DMA Interrupt Mask Register */
-#define MX1_DMA_DIMR		MX1_DMA_REG(0x08)
-
-/* Channel Control Register */
-#define MX1_DMA_CCR(x)		MX1_DMA_REG(0x8c + ((x) << 6))
-
-#define IMX_DMA_MEMSIZE_32	(0 << 4)
-#define IMX_DMA_MEMSIZE_8	(1 << 4)
-#define IMX_DMA_MEMSIZE_16	(2 << 4)
-#define IMX_DMA_TYPE_LINEAR	(0 << 10)
-#define IMX_DMA_TYPE_2D		(1 << 10)
-#define IMX_DMA_TYPE_FIFO	(2 << 10)
-
-#define IMX_DMA_ERR_BURST     (1 << 0)
-#define IMX_DMA_ERR_REQUEST   (1 << 1)
-#define IMX_DMA_ERR_TRANSFER  (1 << 2)
-#define IMX_DMA_ERR_BUFFER    (1 << 3)
-#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining);
-
-void
-imx_dma_config_burstlen(int channel, unsigned int burstlen);
-
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
-		unsigned int dma_length, unsigned int dev_addr,
-		unsigned int dmamode);
-
-
-/*
- * Use this flag as the dma_length argument to imx_dma_setup_sg()
- * to create an endless running dma loop. The end of the scatterlist
- * must be linked to the beginning for this to work.
- */
-#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
-
-int
-imx_dma_setup_sg(int channel, struct scatterlist *sg,
-		unsigned int sgcount, unsigned int dma_length,
-		unsigned int dev_addr, unsigned int dmamode);
-
-int
-imx_dma_setup_handlers(int channel,
-		void (*irq_handler) (int, void *),
-		void (*err_handler) (int, void *, int), void *data);
-
-int
-imx_dma_setup_progression_handler(int channel,
-		void (*prog_handler) (int, void*, struct scatterlist*));
-
-void imx_dma_enable(int channel);
-
-void imx_dma_disable(int channel);
-
-int imx_dma_request(int channel, const char *name);
-
-void imx_dma_free(int channel);
-
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
-
-#endif	/* __MACH_DMA_V1_H__ */
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 65c61db..b4a53a0 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -230,7 +230,6 @@ config IMX_SDMA
 
 config IMX_DMA
 	tristate "i.MX DMA support"
-	depends on IMX_HAVE_DMA_V1
 	select DMA_ENGINE
 	help
 	  Support the i.MX DMA engine. This engine is integrated into
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 304839a..fbb1aaa 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -14,7 +14,6 @@
  * http://www.opensource.org/licenses/gpl-license.html
  * http://www.gnu.org/copyleft/gpl.html
  */
-
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/types.h>
@@ -25,15 +24,89 @@
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 #include <linux/dmaengine.h>
 #include <linux/module.h>
 
 #include <asm/irq.h>
-#include <mach/dma-v1.h>
+#include <mach/dma.h>
 #include <mach/hardware.h>
 
 #include "dmaengine.h"
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
+#define IMX_DMA_CHANNELS  16
+
+#define DMA_MODE_READ		0
+#define DMA_MODE_WRITE		1
+#define DMA_MODE_MASK		1
+
+#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
+#define IMX_DMA_MEMSIZE_32	(0 << 4)
+#define IMX_DMA_MEMSIZE_8	(1 << 4)
+#define IMX_DMA_MEMSIZE_16	(2 << 4)
+#define IMX_DMA_TYPE_LINEAR	(0 << 10)
+#define IMX_DMA_TYPE_2D		(1 << 10)
+#define IMX_DMA_TYPE_FIFO	(2 << 10)
+
+#define IMX_DMA_ERR_BURST     (1 << 0)
+#define IMX_DMA_ERR_REQUEST   (1 << 1)
+#define IMX_DMA_ERR_TRANSFER  (1 << 2)
+#define IMX_DMA_ERR_BUFFER    (1 << 3)
+#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
+
+#define DMA_DCR     0x00		/* Control Register */
+#define DMA_DISR    0x04		/* Interrupt status Register */
+#define DMA_DIMR    0x08		/* Interrupt mask Register */
+#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
+#define DMA_DRTOSR  0x10		/* Request timeout Register */
+#define DMA_DSESR   0x14		/* Transfer Error Status Register */
+#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
+#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
+#define DMA_WSRA    0x40		/* W-Size Register A */
+#define DMA_XSRA    0x44		/* X-Size Register A */
+#define DMA_YSRA    0x48		/* Y-Size Register A */
+#define DMA_WSRB    0x4c		/* W-Size Register B */
+#define DMA_XSRB    0x50		/* X-Size Register B */
+#define DMA_YSRB    0x54		/* Y-Size Register B */
+#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
+#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
+#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
+#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
+#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
+#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
+#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
+#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
+#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff)
+#define CNTR_CNT(x)        ((x) & 0xffffff)
+#define CCR_ACRPT          (1<<14)
+#define CCR_DMOD_LINEAR    (0x0 << 12)
+#define CCR_DMOD_2D        (0x1 << 12)
+#define CCR_DMOD_FIFO      (0x2 << 12)
+#define CCR_DMOD_EOBFIFO   (0x3 << 12)
+#define CCR_SMOD_LINEAR    (0x0 << 10)
+#define CCR_SMOD_2D        (0x1 << 10)
+#define CCR_SMOD_FIFO      (0x2 << 10)
+#define CCR_SMOD_EOBFIFO   (0x3 << 10)
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        (0x0 << 6)
+#define CCR_DSIZ_8         (0x1 << 6)
+#define CCR_DSIZ_16        (0x2 << 6)
+#define CCR_SSIZ_32        (0x0 << 4)
+#define CCR_SSIZ_8         (0x1 << 4)
+#define CCR_SSIZ_16        (0x2 << 4)
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
 
 enum  imxdma_prep_type {
 	IMXDMA_DESC_MEMCPY,
@@ -42,6 +115,39 @@ enum  imxdma_prep_type {
 	IMXDMA_DESC_CYCLIC,
 };
 
+/*
+ * struct imxdma_channel_internal - i.MX specific DMA extension
+ * @name: name specified by DMA client
+ * @irq_handler: client callback for end of transfer
+ * @err_handler: client callback for error condition
+ * @data: clients context data for callbacks
+ * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
+ * @sg: pointer to the actual read/written chunk for scatter-gather emulation
+ * @resbytes: total residual number of bytes to transfer
+ *            (it can be lower or same as sum of SG mapped chunk sizes)
+ * @sgcount: number of chunks to be read/written
+ *
+ * Structure is used for IMX DMA processing. It would be probably good
+ * @struct dma_struct in the future for external interfacing and use
+ * @struct imxdma_channel_internal only as extension to it.
+ */
+
+struct imxdma_channel_internal {
+	void *data;
+	unsigned int dma_mode;
+	struct scatterlist *sg;
+	unsigned int resbytes;
+
+	int in_use;
+
+	u32 ccr_from_device;
+	u32 ccr_to_device;
+
+	struct timer_list watchdog;
+
+	int hw_chaining;
+};
+
 struct imxdma_desc {
 	struct list_head		node;
 	struct dma_async_tx_descriptor	desc;
@@ -64,9 +170,9 @@ struct imxdma_desc {
 };
 
 struct imxdma_channel {
+	struct imxdma_channel_internal	internal;
 	struct imxdma_engine		*imxdma;
 	unsigned int			channel;
-	unsigned int			imxdma_channel;
 
 	struct tasklet_struct		dma_tasklet;
 	struct list_head		ld_free;
@@ -84,13 +190,11 @@ struct imxdma_channel {
 	struct scatterlist		*sg_list;
 };
 
-#define MAX_DMA_CHANNELS 8
-
 struct imxdma_engine {
 	struct device			*dev;
 	struct device_dma_parameters	dma_parms;
 	struct dma_device		dma_device;
-	struct imxdma_channel		channel[MAX_DMA_CHANNELS];
+	struct imxdma_channel		channel[IMX_DMA_CHANNELS];
 };
 
 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
@@ -111,28 +215,381 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 	return false;
 }
 
-static void imxdma_irq_handler(int channel, void *data)
+/* TODO: put this inside any struct */
+static void __iomem *imx_dmav1_baseaddr;
+static struct clk *dma_clk;
+
+static void imx_dmav1_writel(unsigned val, unsigned offset)
+{
+	__raw_writel(val, imx_dmav1_baseaddr + offset);
+}
+
+static unsigned imx_dmav1_readl(unsigned offset)
 {
-	struct imxdma_channel *imxdmac = data;
+	return __raw_readl(imx_dmav1_baseaddr + offset);
+}
 
-	tasklet_schedule(&imxdmac->dma_tasklet);
+static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
+{
+	if (cpu_is_mx27())
+		return imxdma->hw_chaining;
+	else
+		return 0;
+}
+
+/*
+ * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
+ */
+static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
+{
+	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+	unsigned long now;
+
+	now = min(imxdma->resbytes, sg->length);
+	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
+		imxdma->resbytes -= now;
+
+	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+	else
+		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+
+	imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+
+	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
+		"size 0x%08x\n", imxdmac->channel,
+		 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
+		 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
+		 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+
+	return now;
+}
+
+static int
+imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
+		     unsigned int dma_length, unsigned int dev_addr,
+		     unsigned int dmamode)
+{
+	int channel = imxdmac->channel;
+
+	imxdmac->internal.sg = NULL;
+	imxdmac->internal.dma_mode = dmamode;
+
+	if (!dma_address) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if (!dma_length) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+			"dev_addr=0x%08x for read\n",
+			channel, __func__, (unsigned int)dma_address,
+			dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+		imx_dmav1_writel(dma_address, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+			"dev_addr=0x%08x for write\n",
+			channel, __func__, (unsigned int)dma_address,
+			dma_length, dev_addr);
+
+		imx_dmav1_writel(dma_address, DMA_SAR(channel));
+		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_to_device,
+				DMA_CCR(channel));
+	} else {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
+
+	return 0;
+}
+
+static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
+{
+	int channel = imxdmac->channel;
+	unsigned long flags;
+
+	pr_debug("imxdma%d: imx_dma_enable\n", channel);
+
+	if (imxdmac->internal.in_use)
+		return;
+
+	local_irq_save(flags);
+
+	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
+		CCR_ACRPT, DMA_CCR(channel));
+
+	if ((cpu_is_mx21() || cpu_is_mx27()) &&
+			imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
+		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
+		if (imxdmac->internal.sg) {
+			u32 tmp;
+			imxdma_sg_next(imxdmac, imxdmac->internal.sg);
+			tmp = imx_dmav1_readl(DMA_CCR(channel));
+			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
+				DMA_CCR(channel));
+		}
+	}
+	imxdmac->internal.in_use = 1;
+
+	local_irq_restore(flags);
+}
+
+static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
+{
+	int channel = imxdmac->channel;
+	unsigned long flags;
+
+	pr_debug("imxdma%d: imx_dma_disable\n", channel);
+
+	if (imxdma_hw_chain(&imxdmac->internal))
+		del_timer(&imxdmac->internal.watchdog);
+
+	local_irq_save(flags);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
+			DMA_CCR(channel));
+	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imxdmac->internal.in_use = 0;
+	local_irq_restore(flags);
+}
+
+static int
+imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_port,
+	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
+{
+	int channel = imxdmac->channel;
+	u32 dreq = 0;
+
+	imxdmac->internal.hw_chaining = 0;
+
+	if (hw_chaining) {
+		imxdmac->internal.hw_chaining = 1;
+		if (!imxdma_hw_chain(&imxdmac->internal))
+			return -EINVAL;
+	}
+
+	if (dmareq)
+		dreq = CCR_REN;
+
+	imxdmac->internal.ccr_from_device = config_port | (config_mem << 2) | dreq;
+	imxdmac->internal.ccr_to_device = config_mem | (config_port << 2) | dreq;
+
+	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
+
+	return 0;
+}
+
+static int
+imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
+		 struct scatterlist *sg, unsigned int sgcount,
+		 unsigned int dma_length, unsigned int dev_addr,
+		 unsigned int dmamode)
+{
+	int channel = imxdmac->channel;
+
+	if (imxdmac->internal.in_use)
+		return -EBUSY;
+
+	imxdmac->internal.sg = sg;
+	imxdmac->internal.dma_mode = dmamode;
+	imxdmac->internal.resbytes = dma_length;
+
+	if (!sg || !sgcount) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if (!sg->length) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+			"dev_addr=0x%08x for read\n",
+			channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
+	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+			"dev_addr=0x%08x for write\n",
+			channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+		imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
+	} else {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	imxdma_sg_next(imxdmac, sg);
+
+	return 0;
 }
 
-static void imxdma_err_handler(int channel, void *data, int error)
+static void imxdma_watchdog(unsigned long data)
 {
-	struct imxdma_channel *imxdmac = data;
+	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+	int channel = imxdmac->channel;
 
+	imx_dmav1_writel(0, DMA_CCR(channel));
+	imxdmac->internal.in_use = 0;
+	imxdmac->internal.sg = NULL;
+
+	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
+	pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+}
+
+static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
+{
+	struct imxdma_engine *imxdma = dev_id;
+	struct imxdma_channel_internal *internal;
+	unsigned int err_mask;
+	int i, disr;
+	int errcode;
+
+	disr = imx_dmav1_readl(DMA_DISR);
+
+	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
+		   imx_dmav1_readl(DMA_DRTOSR) |
+		   imx_dmav1_readl(DMA_DSESR)  |
+		   imx_dmav1_readl(DMA_DBOSR);
+
+	if (!err_mask)
+		return IRQ_HANDLED;
+
+	imx_dmav1_writel(disr & err_mask, DMA_DISR);
+
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+		if (!(err_mask & (1 << i)))
+			continue;
+		internal = &imxdma->channel[i].internal;
+		errcode = 0;
+
+		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DBTOSR);
+			errcode |= IMX_DMA_ERR_BURST;
+		}
+		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DRTOSR);
+			errcode |= IMX_DMA_ERR_REQUEST;
+		}
+		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DSESR);
+			errcode |= IMX_DMA_ERR_TRANSFER;
+		}
+		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DBOSR);
+			errcode |= IMX_DMA_ERR_BUFFER;
+		}
+		/* Tasklet error handler */
+		tasklet_schedule(&imxdma->channel[i].dma_tasklet);
+
+		printk(KERN_WARNING
+		       "DMA timeout on channel %d -%s%s%s%s\n", i,
+		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
+		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
+		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
+		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
+	}
+	return IRQ_HANDLED;
 }
 
-static void imxdma_progression(int channel, void *data,
-		struct scatterlist *sg)
+static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
-	struct imxdma_channel *imxdmac = data;
+	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
+	int chno = imxdmac->channel;
+
+	if (imxdma->sg) {
+		u32 tmp;
+		imxdma->sg = sg_next(imxdma->sg);
+
+		if (imxdma->sg) {
+			imxdma_sg_next(imxdmac, imxdma->sg);
+
+			tmp = imx_dmav1_readl(DMA_CCR(chno));
+
+			if (imxdma_hw_chain(imxdma)) {
+				/* FIXME: The timeout should probably be
+				 * configurable
+				 */
+				mod_timer(&imxdma->watchdog,
+					jiffies + msecs_to_jiffies(500));
+
+				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
+				imx_dmav1_writel(tmp, DMA_CCR(chno));
+			} else {
+				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+				tmp |= CCR_CEN;
+			}
+
+			imx_dmav1_writel(tmp, DMA_CCR(chno));
+
+			if (imxdma_chan_is_doing_cyclic(imxdmac))
+				/* Tasklet progression */
+				tasklet_schedule(&imxdmac->dma_tasklet);
 
+			return;
+		}
+
+		if (imxdma_hw_chain(imxdma)) {
+			del_timer(&imxdma->watchdog);
+			return;
+		}
+	}
+
+	imx_dmav1_writel(0, DMA_CCR(chno));
+	imxdma->in_use = 0;
+	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
 
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+	struct imxdma_engine *imxdma = dev_id;
+	struct imxdma_channel_internal *internal;
+	int i, disr;
+
+	if (cpu_is_mx21() || cpu_is_mx27())
+		imxdma_err_handler(irq, dev_id);
+
+	disr = imx_dmav1_readl(DMA_DISR);
+
+	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
+		     disr);
+
+	imx_dmav1_writel(disr, DMA_DISR);
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+		if (disr & (1 << i)) {
+			internal = &imxdma->channel[i].internal;
+			dma_irq_handle_channel(&imxdma->channel[i]);
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
 static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
@@ -141,31 +598,24 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+		ret = imxdma_config_channel_hw(imxdmac,
 					  d->config_port, d->config_mem, 0, 0);
 		if (ret < 0)
 			return ret;
-		ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
+		ret = imxdma_setup_single_hw(imxdmac, d->src,
 					   d->len, d->dest, d->dmamode);
 		if (ret < 0)
 			return ret;
 		break;
+
+	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
-		ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
-							imxdma_progression);
-		if (ret < 0)
-			return ret;
-		/*
-		 * We fall through here since cyclic transfer is the same as
-		 * slave_sg adding a progression handler and a specific sg
-		 * configuration which is done in 'imxdma_prep_dma_cyclic'.
-		 */
 	case IMXDMA_DESC_SLAVE_SG:
 		if (d->dmamode == DMA_MODE_READ)
-			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
 				       d->sgcount, d->len, d->src, d->dmamode);
 		else
-			ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
+			ret = imxdma_setup_sg_hw(imxdmac, d->sg,
 				      d->sgcount, d->len, d->dest, d->dmamode);
 		if (ret < 0)
 			return ret;
@@ -173,7 +623,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	default:
 		return -EINVAL;
 	}
-	imx_dma_enable(imxdmac->imxdma_channel);
+	imxdma_enable_hw(imxdmac);
 	return 0;
 }
 
@@ -225,7 +675,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 
 	switch (cmd) {
 	case DMA_TERMINATE_ALL:
-		imx_dma_disable(imxdmac->imxdma_channel);
+		imxdma_disable_hw(imxdmac);
 
 		spin_lock_irqsave(&imxdmac->lock, flags);
 		list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
@@ -255,16 +705,16 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			mode = IMX_DMA_MEMSIZE_32;
 			break;
 		}
-		ret = imx_dma_config_channel(imxdmac->imxdma_channel,
+		ret = imxdma_config_channel_hw(imxdmac,
 				mode | IMX_DMA_TYPE_FIFO,
 				IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
 				imxdmac->dma_request, 1);
 
 		if (ret)
 			return ret;
-
-		imx_dma_config_burstlen(imxdmac->imxdma_channel,
-				imxdmac->watermark_level * imxdmac->word_size);
+		/* Set burst length */
+		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
+				 DMA_BLR(imxdmac->channel));
 
 		return 0;
 	default:
@@ -333,7 +783,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
 
 	spin_lock_irqsave(&imxdmac->lock, flags);
 
-	imx_dma_disable(imxdmac->imxdma_channel);
+	imxdma_disable_hw(imxdmac);
 	list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 	list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 
@@ -520,10 +970,51 @@ static void imxdma_issue_pending(struct dma_chan *chan)
 }
 
 static int __init imxdma_probe(struct platform_device *pdev)
-{
+	{
 	struct imxdma_engine *imxdma;
 	int ret, i;
 
+	if (cpu_is_mx1())
+		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+	else if (cpu_is_mx21())
+		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+	else if (cpu_is_mx27())
+		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+	else
+		return 0;
+
+	dma_clk = clk_get(NULL, "dma");
+	if (IS_ERR(dma_clk))
+		return PTR_ERR(dma_clk);
+	clk_enable(dma_clk);
+
+	/* reset DMA module */
+	imx_dmav1_writel(DCR_DRST, DMA_DCR);
+
+	if (cpu_is_mx1()) {
+		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
+		if (ret) {
+			pr_crit("Can't register IRQ for DMA\n");
+			return ret;
+		}
+
+		ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
+		if (ret) {
+			pr_crit("Can't register ERRIRQ for DMA\n");
+			free_irq(MX1_DMA_INT, NULL);
+			return ret;
+		}
+	}
+
+	/* enable DMA module */
+	imx_dmav1_writel(DCR_DEN, DMA_DCR);
+
+	/* clear all interrupts */
+	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+
+	/* disable interrupts */
+	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
+
 	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
 	if (!imxdma)
 		return -ENOMEM;
@@ -535,19 +1026,22 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
 
 	/* Initialize channel parameters */
-	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
-		imxdmac->imxdma_channel = imx_dma_request_by_prio("dmaengine",
-				DMA_PRIO_MEDIUM);
-		if ((int)imxdmac->channel < 0) {
-			ret = -ENODEV;
-			goto err_init;
+		memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+		if (cpu_is_mx21() || cpu_is_mx27()) {
+			ret = request_irq(MX2x_INT_DMACH0 + i,
+					dma_irq_handler, 0, "DMA", imxdma);
+			if (ret) {
+				pr_crit("Can't register IRQ %d for DMA channel %d\n",
+						MX2x_INT_DMACH0 + i, i);
+				goto err_init;
+			}
+			init_timer(&imxdmac->internal.watchdog);
+			imxdmac->internal.watchdog.function = &imxdma_watchdog;
+			imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
 		}
 
-		imx_dma_setup_handlers(imxdmac->imxdma_channel,
-		       imxdma_irq_handler, imxdma_err_handler, imxdmac);
-
 		imxdmac->imxdma = imxdma;
 		spin_lock_init(&imxdmac->lock);
 
@@ -593,9 +1087,13 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	return 0;
 
 err_init:
-	while (--i >= 0) {
-		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-		imx_dma_free(imxdmac->imxdma_channel);
+
+	if (cpu_is_mx21() || cpu_is_mx27()) {
+		while (--i >= 0)
+			free_irq(MX2x_INT_DMACH0 + i, NULL);
+	} else if cpu_is_mx1() {
+		free_irq(MX1_DMA_INT, NULL);
+		free_irq(MX1_DMA_ERR, NULL);
 	}
 
 	kfree(imxdma);
@@ -609,10 +1107,12 @@ static int __exit imxdma_remove(struct platform_device *pdev)
 
         dma_async_device_unregister(&imxdma->dma_device);
 
-	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
-		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-
-		 imx_dma_free(imxdmac->imxdma_channel);
+	if (cpu_is_mx21() || cpu_is_mx27()) {
+		for (i = 0; i < IMX_DMA_CHANNELS; i++)
+			free_irq(MX2x_INT_DMACH0 + i, NULL);
+	} else if cpu_is_mx1() {
+		free_irq(MX1_DMA_INT, NULL);
+		free_irq(MX1_DMA_ERR, NULL);
 	}
 
         kfree(imxdma);
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:07 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:07 +0100
Subject: [PATCH v4 07/15] dmaengine: imx-dma: remove sg member from internal
 structure.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-8-git-send-email-javier.martin@vista-silicon.com>

This member is redundant, because it is already present in
descriptor structure. Removing it will make further removing
of 'internal' structure easier.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   42 ++++++++++++++++++------------------------
 1 files changed, 18 insertions(+), 24 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 484f353..82d4099 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -129,7 +129,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	struct scatterlist *sg;
 	unsigned int resbytes;
 
 	int in_use;
@@ -278,11 +277,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
-		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
-		if (imxdmac->internal.sg) {
+			d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+		d->sg = sg_next(d->sg);
+		if (d->sg) {
 			u32 tmp;
-			imxdma_sg_next(d, imxdmac->internal.sg);
+			imxdma_sg_next(d, d->sg);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -319,7 +318,6 @@ static void imxdma_watchdog(unsigned long data)
 
 	imx_dmav1_writel(0, DMA_CCR(channel));
 	imxdmac->internal.in_use = 0;
-	imxdmac->internal.sg = NULL;
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -387,24 +385,23 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
-	if (imxdma->sg) {
-		u32 tmp;
-		imxdma->sg = sg_next(imxdma->sg);
-
-		if (imxdma->sg) {
+	spin_lock(&imxdmac->lock);
+	if (list_empty(&imxdmac->ld_active)) {
+		spin_unlock(&imxdmac->lock);
+		goto out;
+	}
 
-			spin_lock(&imxdmac->lock);
-			if (list_empty(&imxdmac->ld_active)) {
-				spin_unlock(&imxdmac->lock);
-				goto out;
-			}
+	desc = list_first_entry(&imxdmac->ld_active,
+				struct imxdma_desc,
+				node);
+	spin_unlock(&imxdmac->lock);
 
-			desc = list_first_entry(&imxdmac->ld_active,
-						struct imxdma_desc,
-						node);
-			spin_unlock(&imxdmac->lock);
+	if (desc->sg) {
+		u32 tmp;
+		desc->sg = sg_next(desc->sg);
 
-			imxdma_sg_next(desc, imxdma->sg);
+		if (desc->sg) {
+			imxdma_sg_next(desc, desc->sg);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -477,8 +474,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		imxdmac->internal.sg = NULL;
-
 		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
 		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
 		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
@@ -494,7 +489,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		imxdmac->internal.sg = d->sg;
 		imxdmac->internal.resbytes = d->len;
 
 		if (d->direction == DMA_DEV_TO_MEM) {
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:06 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:06 +0100
Subject: [PATCH v4 06/15] dmaengine: imx-dma: remove 'imxdma_setup_sg_hw'
 function.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-7-git-send-email-javier.martin@vista-silicon.com>

Removing this function allows moving 'ccr_to_device' and
'ccr_from_device' from internal struct to channel struct.
This repesents a step forward towards removing auxiliary
'internal' structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   98 +++++++++++++++++-------------------------------
 1 files changed, 35 insertions(+), 63 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 25b4108..484f353 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -134,9 +134,6 @@ struct imxdma_channel_internal {
 
 	int in_use;
 
-	u32 ccr_from_device;
-	u32 ccr_to_device;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -182,6 +179,8 @@ struct imxdma_channel {
 	enum dma_status			status;
 	int				dma_request;
 	struct scatterlist		*sg_list;
+	u32				ccr_from_device;
+	u32				ccr_to_device;
 };
 
 struct imxdma_engine {
@@ -313,58 +312,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	local_irq_restore(flags);
 }
 
-static int
-imxdma_setup_sg_hw(struct imxdma_desc *d,
-		 struct scatterlist *sg, unsigned int sgcount,
-		 unsigned int dma_length, unsigned int dev_addr,
-		 enum dma_transfer_direction direction)
-{
-	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
-	int channel = imxdmac->channel;
-
-	if (imxdmac->internal.in_use)
-		return -EBUSY;
-
-	imxdmac->internal.sg = sg;
-	imxdmac->internal.resbytes = dma_length;
-
-	if (!sg || !sgcount) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg empty sg list\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!sg->length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (direction == DMA_DEV_TO_MEM) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
-	} else if (direction == DMA_MEM_TO_DEV) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdmac->internal.ccr_to_device, DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imxdma_sg_next(d, sg);
-
-	return 0;
-}
-
 static void imxdma_watchdog(unsigned long data)
 {
 	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
@@ -526,7 +473,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
-	int ret;
 
 	/* Configure and enable */
 	switch (d->type) {
@@ -548,10 +494,37 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
-					 imxdmac->per_address, d->direction);
-		if (ret < 0)
-			return ret;
+		imxdmac->internal.sg = d->sg;
+		imxdmac->internal.resbytes = d->len;
+
+		if (d->direction == DMA_DEV_TO_MEM) {
+			imx_dmav1_writel(imxdmac->per_address,
+					 DMA_SAR(imxdmac->channel));
+			imx_dmav1_writel(imxdmac->ccr_from_device,
+					 DMA_CCR(imxdmac->channel));
+
+			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+				"total length=%d dev_addr=0x%08x (dev2mem)\n",
+				__func__, imxdmac->channel, d->sg, d->sgcount,
+				d->len, imxdmac->per_address);
+		} else if (d->direction == DMA_MEM_TO_DEV) {
+			imx_dmav1_writel(imxdmac->per_address,
+					 DMA_DAR(imxdmac->channel));
+			imx_dmav1_writel(imxdmac->ccr_to_device,
+					 DMA_CCR(imxdmac->channel));
+
+			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
+				"total length=%d dev_addr=0x%08x (mem2dev)\n",
+				__func__, imxdmac->channel, d->sg, d->sgcount,
+				d->len, imxdmac->per_address);
+		} else {
+			dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
+				__func__, imxdmac->channel);
+			return -EINVAL;
+		}
+
+		imxdma_sg_next(d, d->sg);
+
 		break;
 	default:
 		return -EINVAL;
@@ -641,11 +614,10 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		imxdmac->internal.hw_chaining = 1;
 		if (!imxdma_hw_chain(&imxdmac->internal))
 			return -EINVAL;
-		imxdmac->internal.ccr_from_device =
-			(mode | IMX_DMA_TYPE_FIFO) |
+		imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
 			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
 			CCR_REN;
-		imxdmac->internal.ccr_to_device =
+		imxdmac->ccr_to_device =
 			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
 			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
 		imx_dmav1_writel(imxdmac->dma_request,
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:08 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:08 +0100
Subject: [PATCH v4 08/15] dmaengine: imx-dma: remove 'in_use' field of
 'internal' structure.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-9-git-send-email-javier.martin@vista-silicon.com>

It makes no sense keeping an 'in_use' flag when the multiple descriptor
mechanism already prevents a new DMA transfer to be issued when another
one is in course.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |    9 ---------
 1 files changed, 0 insertions(+), 9 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 82d4099..d7309e4 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -131,8 +131,6 @@ enum  imxdma_prep_type {
 struct imxdma_channel_internal {
 	unsigned int resbytes;
 
-	int in_use;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -266,9 +264,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 	pr_debug("imxdma%d: imx_dma_enable\n", channel);
 
-	if (imxdmac->internal.in_use)
-		return;
-
 	local_irq_save(flags);
 
 	imx_dmav1_writel(1 << channel, DMA_DISR);
@@ -287,7 +282,6 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 				DMA_CCR(channel));
 		}
 	}
-	imxdmac->internal.in_use = 1;
 
 	local_irq_restore(flags);
 }
@@ -307,7 +301,6 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
 			DMA_CCR(channel));
 	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdmac->internal.in_use = 0;
 	local_irq_restore(flags);
 }
 
@@ -317,7 +310,6 @@ static void imxdma_watchdog(unsigned long data)
 	int channel = imxdmac->channel;
 
 	imx_dmav1_writel(0, DMA_CCR(channel));
-	imxdmac->internal.in_use = 0;
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -436,7 +428,6 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 
 out:
 	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
 	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:09 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:09 +0100
Subject: [PATCH v4 09/15] dmaengine: imx-dma: remove 'resbytes' field of
 'internal' structure.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-10-git-send-email-javier.martin@vista-silicon.com>

Use per-descriptor 'len' field to keep track of the remaining bytes
instead. This goes on the direction of eventually removing the
'internal' structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   11 +++--------
 1 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index d7309e4..6e03f92 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -129,8 +129,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	unsigned int resbytes;
-
 	struct timer_list watchdog;
 
 	int hw_chaining;
@@ -233,12 +231,11 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
 static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
-	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	unsigned long now;
 
-	now = min(imxdma->resbytes, sg->length);
-	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
-		imxdma->resbytes -= now;
+	now = min(d->len, sg->length);
+	if (d->len != IMX_DMA_LENGTH_LOOP)
+		d->len -= now;
 
 	if (d->direction == DMA_DEV_TO_MEM)
 		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
@@ -480,8 +477,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		imxdmac->internal.resbytes = d->len;
-
 		if (d->direction == DMA_DEV_TO_MEM) {
 			imx_dmav1_writel(imxdmac->per_address,
 					 DMA_SAR(imxdmac->channel));
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:10 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:10 +0100
Subject: [PATCH v4 10/15] dmaengine: imx-dma: remove internal structure.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-11-git-send-email-javier.martin@vista-silicon.com>

This structure was created to allow an smoothless
merge but was meant to be removed. Remaining members
'hw_chaining' and 'watchdog' are moved to the channel
structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   64 +++++++++++++-----------------------------------
 1 files changed, 18 insertions(+), 46 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 6e03f92..629be35 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -111,29 +111,6 @@ enum  imxdma_prep_type {
 	IMXDMA_DESC_CYCLIC,
 };
 
-/*
- * struct imxdma_channel_internal - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- *            (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imxdma_channel_internal only as extension to it.
- */
-
-struct imxdma_channel_internal {
-	struct timer_list watchdog;
-
-	int hw_chaining;
-};
-
 struct imxdma_desc {
 	struct list_head		node;
 	struct dma_async_tx_descriptor	desc;
@@ -156,7 +133,8 @@ struct imxdma_desc {
 };
 
 struct imxdma_channel {
-	struct imxdma_channel_internal	internal;
+	int				hw_chaining;
+	struct timer_list		watchdog;
 	struct imxdma_engine		*imxdma;
 	unsigned int			channel;
 
@@ -217,10 +195,10 @@ static unsigned imx_dmav1_readl(unsigned offset)
 	return __raw_readl(imx_dmav1_baseaddr + offset);
 }
 
-static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
+static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 {
 	if (cpu_is_mx27())
-		return imxdma->hw_chaining;
+		return imxdmac->hw_chaining;
 	else
 		return 0;
 }
@@ -269,7 +247,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+			d->sg && imxdma_hw_chain(imxdmac)) {
 		d->sg = sg_next(d->sg);
 		if (d->sg) {
 			u32 tmp;
@@ -290,8 +268,8 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 
 	pr_debug("imxdma%d: imx_dma_disable\n", channel);
 
-	if (imxdma_hw_chain(&imxdmac->internal))
-		del_timer(&imxdmac->internal.watchdog);
+	if (imxdma_hw_chain(imxdmac))
+		del_timer(&imxdmac->watchdog);
 
 	local_irq_save(flags);
 	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
@@ -316,7 +294,6 @@ static void imxdma_watchdog(unsigned long data)
 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 {
 	struct imxdma_engine *imxdma = dev_id;
-	struct imxdma_channel_internal *internal;
 	unsigned int err_mask;
 	int i, disr;
 	int errcode;
@@ -336,7 +313,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (!(err_mask & (1 << i)))
 			continue;
-		internal = &imxdma->channel[i].internal;
 		errcode = 0;
 
 		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
@@ -370,7 +346,6 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 
 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
-	struct imxdma_channel_internal *imxdma = &imxdmac->internal;
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
@@ -394,11 +369,11 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
-			if (imxdma_hw_chain(imxdma)) {
+			if (imxdma_hw_chain(imxdmac)) {
 				/* FIXME: The timeout should probably be
 				 * configurable
 				 */
-				mod_timer(&imxdma->watchdog,
+				mod_timer(&imxdmac->watchdog,
 					jiffies + msecs_to_jiffies(500));
 
 				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
@@ -417,8 +392,8 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 			return;
 		}
 
-		if (imxdma_hw_chain(imxdma)) {
-			del_timer(&imxdma->watchdog);
+		if (imxdma_hw_chain(imxdmac)) {
+			del_timer(&imxdmac->watchdog);
 			return;
 		}
 	}
@@ -432,7 +407,6 @@ out:
 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 {
 	struct imxdma_engine *imxdma = dev_id;
-	struct imxdma_channel_internal *internal;
 	int i, disr;
 
 	if (cpu_is_mx21() || cpu_is_mx27())
@@ -445,10 +419,8 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 
 	imx_dmav1_writel(disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (disr & (1 << i)) {
-			internal = &imxdma->channel[i].internal;
+		if (disr & (1 << i))
 			dma_irq_handle_channel(&imxdma->channel[i]);
-		}
 	}
 
 	return IRQ_HANDLED;
@@ -591,8 +563,8 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 			break;
 		}
 
-		imxdmac->internal.hw_chaining = 1;
-		if (!imxdma_hw_chain(&imxdmac->internal))
+		imxdmac->hw_chaining = 1;
+		if (!imxdma_hw_chain(imxdmac))
 			return -EINVAL;
 		imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
 			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
@@ -917,7 +889,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	/* Initialize channel parameters */
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		struct imxdma_channel *imxdmac = &imxdma->channel[i];
-		memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
+
 		if (cpu_is_mx21() || cpu_is_mx27()) {
 			ret = request_irq(MX2x_INT_DMACH0 + i,
 					dma_irq_handler, 0, "DMA", imxdma);
@@ -926,9 +898,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
 						MX2x_INT_DMACH0 + i, i);
 				goto err_init;
 			}
-			init_timer(&imxdmac->internal.watchdog);
-			imxdmac->internal.watchdog.function = &imxdma_watchdog;
-			imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
+			init_timer(&imxdmac->watchdog);
+			imxdmac->watchdog.function = &imxdma_watchdog;
+			imxdmac->watchdog.data = (unsigned long)imxdmac;
 		}
 
 		imxdmac->imxdma = imxdma;
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:11 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:11 +0100
Subject: [PATCH v4 11/15] dmaengine: imx-dma: remove unused arg of
 imxdma_sg_next.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-12-git-send-email-javier.martin@vista-silicon.com>

Since this function is always used with 'desc' as first argument
and 'desc->sg' as second argument, the latter is clearly redundant
and can be removed.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 629be35..628b0f6 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -206,9 +206,10 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 /*
  * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
  */
-static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
+static inline int imxdma_sg_next(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct scatterlist *sg = d->sg;
 	unsigned long now;
 
 	now = min(d->len, sg->length);
@@ -251,7 +252,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		d->sg = sg_next(d->sg);
 		if (d->sg) {
 			u32 tmp;
-			imxdma_sg_next(d, d->sg);
+			imxdma_sg_next(d);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -365,7 +366,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		desc->sg = sg_next(desc->sg);
 
 		if (desc->sg) {
-			imxdma_sg_next(desc, desc->sg);
+			imxdma_sg_next(desc);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -475,7 +476,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 			return -EINVAL;
 		}
 
-		imxdma_sg_next(d, d->sg);
+		imxdma_sg_next(d);
 
 		break;
 	default:
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:12 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:12 +0100
Subject: [PATCH v4 12/15] dmaengine: imx-dma: remove 'imx_dmav1_baseaddr' and
 'dma_clk'.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-13-git-send-email-javier.martin@vista-silicon.com>

These global variables are integrated into the dmaengine structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |  169 +++++++++++++++++++++++++++----------------------
 1 files changed, 93 insertions(+), 76 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 628b0f6..cdca95a 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -160,6 +160,8 @@ struct imxdma_engine {
 	struct device			*dev;
 	struct device_dma_parameters	dma_parms;
 	struct dma_device		dma_device;
+	void __iomem			*base;
+	struct clk			*dma_clk;
 	struct imxdma_channel		channel[IMX_DMA_CHANNELS];
 };
 
@@ -181,18 +183,17 @@ static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 	return false;
 }
 
-/* TODO: put this inside any struct */
-static void __iomem *imx_dmav1_baseaddr;
-static struct clk *dma_clk;
 
-static void imx_dmav1_writel(unsigned val, unsigned offset)
+
+static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
+			     unsigned offset)
 {
-	__raw_writel(val, imx_dmav1_baseaddr + offset);
+	__raw_writel(val, imxdma->base + offset);
 }
 
-static unsigned imx_dmav1_readl(unsigned offset)
+static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
 {
-	return __raw_readl(imx_dmav1_baseaddr + offset);
+	return __raw_readl(imxdma->base + offset);
 }
 
 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
@@ -209,6 +210,7 @@ static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 static inline int imxdma_sg_next(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	struct scatterlist *sg = d->sg;
 	unsigned long now;
 
@@ -217,17 +219,19 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 		d->len -= now;
 
 	if (d->direction == DMA_DEV_TO_MEM)
-		imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, sg->dma_address,
+				 DMA_DAR(imxdmac->channel));
 	else
-		imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, sg->dma_address,
+				 DMA_SAR(imxdmac->channel));
 
-	imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
+	imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
 
 	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
 		"size 0x%08x\n", imxdmac->channel,
-		 imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
-		 imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
-		 imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
+		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
+		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
+		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
 
 	return now;
 }
@@ -235,6 +239,7 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 static void imxdma_enable_hw(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -242,10 +247,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 	local_irq_save(flags);
 
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
-		CCR_ACRPT, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
+			 ~(1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
+			 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
 			d->sg && imxdma_hw_chain(imxdmac)) {
@@ -253,9 +259,9 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		if (d->sg) {
 			u32 tmp;
 			imxdma_sg_next(d);
-			tmp = imx_dmav1_readl(DMA_CCR(channel));
-			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
-				DMA_CCR(channel));
+			tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
+			imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
+					 DMA_CCR(channel));
 		}
 	}
 
@@ -264,6 +270,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 
 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 {
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
@@ -273,19 +280,21 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 		del_timer(&imxdmac->watchdog);
 
 	local_irq_save(flags);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
-			DMA_CCR(channel));
-	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
+			 (1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
+			 ~CCR_CEN, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
 	local_irq_restore(flags);
 }
 
 static void imxdma_watchdog(unsigned long data)
 {
 	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int channel = imxdmac->channel;
 
-	imx_dmav1_writel(0, DMA_CCR(channel));
+	imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -299,37 +308,37 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 	int i, disr;
 	int errcode;
 
-	disr = imx_dmav1_readl(DMA_DISR);
+	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
-	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
-		   imx_dmav1_readl(DMA_DRTOSR) |
-		   imx_dmav1_readl(DMA_DSESR)  |
-		   imx_dmav1_readl(DMA_DBOSR);
+	err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
+		   imx_dmav1_readl(imxdma, DMA_DRTOSR) |
+		   imx_dmav1_readl(imxdma, DMA_DSESR)  |
+		   imx_dmav1_readl(imxdma, DMA_DBOSR);
 
 	if (!err_mask)
 		return IRQ_HANDLED;
 
-	imx_dmav1_writel(disr & err_mask, DMA_DISR);
+	imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
 
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (!(err_mask & (1 << i)))
 			continue;
 		errcode = 0;
 
-		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBTOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
 			errcode |= IMX_DMA_ERR_BURST;
 		}
-		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DRTOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
 			errcode |= IMX_DMA_ERR_REQUEST;
 		}
-		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DSESR);
+		if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
 			errcode |= IMX_DMA_ERR_TRANSFER;
 		}
-		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBOSR);
+		if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
+			imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
 			errcode |= IMX_DMA_ERR_BUFFER;
 		}
 		/* Tasklet error handler */
@@ -347,6 +356,7 @@ static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 
 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 {
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
@@ -368,7 +378,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 		if (desc->sg) {
 			imxdma_sg_next(desc);
 
-			tmp = imx_dmav1_readl(DMA_CCR(chno));
+			tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
 
 			if (imxdma_hw_chain(imxdmac)) {
 				/* FIXME: The timeout should probably be
@@ -378,13 +388,14 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 					jiffies + msecs_to_jiffies(500));
 
 				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
-				imx_dmav1_writel(tmp, DMA_CCR(chno));
+				imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 			} else {
-				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+				imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
+						 DMA_CCR(chno));
 				tmp |= CCR_CEN;
 			}
 
-			imx_dmav1_writel(tmp, DMA_CCR(chno));
+			imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 
 			if (imxdma_chan_is_doing_cyclic(imxdmac))
 				/* Tasklet progression */
@@ -400,7 +411,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 	}
 
 out:
-	imx_dmav1_writel(0, DMA_CCR(chno));
+	imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
 	/* Tasklet irq */
 	tasklet_schedule(&imxdmac->dma_tasklet);
 }
@@ -413,12 +424,12 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 	if (cpu_is_mx21() || cpu_is_mx27())
 		imxdma_err_handler(irq, dev_id);
 
-	disr = imx_dmav1_readl(DMA_DISR);
+	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
 	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
 		     disr);
 
-	imx_dmav1_writel(disr, DMA_DISR);
+	imx_dmav1_writel(imxdma, disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 		if (disr & (1 << i))
 			dma_irq_handle_channel(&imxdma->channel[i]);
@@ -435,12 +446,12 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
-		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
-		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
+		imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
 			 DMA_CCR(imxdmac->channel));
 
-		imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
 
 		dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
 			"dma_length=%d\n", __func__, imxdmac->channel,
@@ -451,9 +462,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
 		if (d->direction == DMA_DEV_TO_MEM) {
-			imx_dmav1_writel(imxdmac->per_address,
+			imx_dmav1_writel(imxdma, imxdmac->per_address,
 					 DMA_SAR(imxdmac->channel));
-			imx_dmav1_writel(imxdmac->ccr_from_device,
+			imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
 					 DMA_CCR(imxdmac->channel));
 
 			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -461,9 +472,9 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 				__func__, imxdmac->channel, d->sg, d->sgcount,
 				d->len, imxdmac->per_address);
 		} else if (d->direction == DMA_MEM_TO_DEV) {
-			imx_dmav1_writel(imxdmac->per_address,
+			imx_dmav1_writel(imxdma, imxdmac->per_address,
 					 DMA_DAR(imxdmac->channel));
-			imx_dmav1_writel(imxdmac->ccr_to_device,
+			imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
 					 DMA_CCR(imxdmac->channel));
 
 			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
@@ -528,6 +539,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 	struct dma_slave_config *dmaengine_cfg = (void *)arg;
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	unsigned long flags;
 	unsigned int mode = 0;
 
@@ -573,12 +585,12 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		imxdmac->ccr_to_device =
 			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
 			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
-		imx_dmav1_writel(imxdmac->dma_request,
+		imx_dmav1_writel(imxdma, imxdmac->dma_request,
 				 DMA_RSSR(imxdmac->channel));
 
 		/* Set burst length */
-		imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
-				 DMA_BLR(imxdmac->channel));
+		imx_dmav1_writel(imxdma, imxdmac->watermark_level *
+				imxdmac->word_size, DMA_BLR(imxdmac->channel));
 
 		return 0;
 	default:
@@ -836,27 +848,35 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	struct imxdma_engine *imxdma;
 	int ret, i;
 
-	if (cpu_is_mx1())
-		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
-	else if (cpu_is_mx21())
-		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
-	else if (cpu_is_mx27())
-		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
-	else
+
+	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
+	if (!imxdma)
+		return -ENOMEM;
+
+	if (cpu_is_mx1()) {
+		imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+	} else if (cpu_is_mx21()) {
+		imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+	} else if (cpu_is_mx27()) {
+		imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+	} else {
+		kfree(imxdma);
 		return 0;
+	}
 
-	dma_clk = clk_get(NULL, "dma");
-	if (IS_ERR(dma_clk))
-		return PTR_ERR(dma_clk);
-	clk_enable(dma_clk);
+	imxdma->dma_clk = clk_get(NULL, "dma");
+	if (IS_ERR(imxdma->dma_clk))
+		return PTR_ERR(imxdma->dma_clk);
+	clk_enable(imxdma->dma_clk);
 
 	/* reset DMA module */
-	imx_dmav1_writel(DCR_DRST, DMA_DCR);
+	imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
 
 	if (cpu_is_mx1()) {
 		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
 		if (ret) {
 			pr_crit("Can't register IRQ for DMA\n");
+			kfree(imxdma);
 			return ret;
 		}
 
@@ -864,22 +884,19 @@ static int __init imxdma_probe(struct platform_device *pdev)
 		if (ret) {
 			pr_crit("Can't register ERRIRQ for DMA\n");
 			free_irq(MX1_DMA_INT, NULL);
+			kfree(imxdma);
 			return ret;
 		}
 	}
 
 	/* enable DMA module */
-	imx_dmav1_writel(DCR_DEN, DMA_DCR);
+	imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
 
 	/* clear all interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
 
 	/* disable interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
-	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
-	if (!imxdma)
-		return -ENOMEM;
+	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
 
 	INIT_LIST_HEAD(&imxdma->dma_device.channels);
 
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:13 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:13 +0100
Subject: [PATCH v4 13/15] dmaengine: imx-dma: use 'dev_dbg' and 'dev_warn' for
 messages.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-14-git-send-email-javier.martin@vista-silicon.com>

There were some 'pr_crit' and 'pr_debug' messages due to the
initial merge. Replace them by 'dev_dbg' and 'dev_warn' to be
consistent.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |   23 ++++++++++++-----------
 1 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index cdca95a..38c41c4 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -227,8 +227,8 @@ static inline int imxdma_sg_next(struct imxdma_desc *d)
 
 	imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
 
-	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
-		"size 0x%08x\n", imxdmac->channel,
+	dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
+		"size 0x%08x\n", __func__, imxdmac->channel,
 		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
 		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
 		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
@@ -243,7 +243,7 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
-	pr_debug("imxdma%d: imx_dma_enable\n", channel);
+	dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
 
 	local_irq_save(flags);
 
@@ -274,7 +274,7 @@ static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 	int channel = imxdmac->channel;
 	unsigned long flags;
 
-	pr_debug("imxdma%d: imx_dma_disable\n", channel);
+	dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
 
 	if (imxdma_hw_chain(imxdmac))
 		del_timer(&imxdmac->watchdog);
@@ -298,7 +298,8 @@ static void imxdma_watchdog(unsigned long data)
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
-	pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
+	dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
+		imxdmac->channel);
 }
 
 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
@@ -426,8 +427,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 
 	disr = imx_dmav1_readl(imxdma, DMA_DISR);
 
-	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
-		     disr);
+	dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
 
 	imx_dmav1_writel(imxdma, disr, DMA_DISR);
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
@@ -875,14 +875,14 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	if (cpu_is_mx1()) {
 		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
 		if (ret) {
-			pr_crit("Can't register IRQ for DMA\n");
+			dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
 			kfree(imxdma);
 			return ret;
 		}
 
 		ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
 		if (ret) {
-			pr_crit("Can't register ERRIRQ for DMA\n");
+			dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
 			free_irq(MX1_DMA_INT, NULL);
 			kfree(imxdma);
 			return ret;
@@ -912,8 +912,9 @@ static int __init imxdma_probe(struct platform_device *pdev)
 			ret = request_irq(MX2x_INT_DMACH0 + i,
 					dma_irq_handler, 0, "DMA", imxdma);
 			if (ret) {
-				pr_crit("Can't register IRQ %d for DMA channel %d\n",
-						MX2x_INT_DMACH0 + i, i);
+				dev_warn(imxdma->dev, "Can't register IRQ %d "
+					 "for DMA channel %d\n",
+					 MX2x_INT_DMACH0 + i, i);
 				goto err_init;
 			}
 			init_timer(&imxdmac->watchdog);
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:14 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:14 +0100
Subject: [PATCH v4 14/15] dmaengine: i.MX: Add support for interleaved
 transfers.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-15-git-send-email-javier.martin@vista-silicon.com>

i.MX2 and i.MX1 chips have the possibility to do
interleaved transfers with two constraints:
- Only one chunk can be used (i.e. only 2D transfers are allowed).
- Only 2 interleaved configurations can be applied at the same time
for all channels.

Since this patch adds a new resource 'slots_2d' which is shared
by all the DMA channels and to avoid disgustin locking BUGs, the
'lock' member has been moved to the global 'imxdma_engine' structure.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |  146 ++++++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 131 insertions(+), 15 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 38c41c4..2155d82 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -36,6 +36,10 @@
 #define IMXDMA_MAX_CHAN_DESCRIPTORS	16
 #define IMX_DMA_CHANNELS  16
 
+#define IMX_DMA_2D_SLOTS	2
+#define IMX_DMA_2D_SLOT_A	0
+#define IMX_DMA_2D_SLOT_B	1
+
 #define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
 #define IMX_DMA_MEMSIZE_32	(0 << 4)
 #define IMX_DMA_MEMSIZE_8	(1 << 4)
@@ -111,6 +115,13 @@ enum  imxdma_prep_type {
 	IMXDMA_DESC_CYCLIC,
 };
 
+struct imx_dma_2d_config {
+	u16		xsr;
+	u16		ysr;
+	u16		wsr;
+	int		count;
+};
+
 struct imxdma_desc {
 	struct list_head		node;
 	struct dma_async_tx_descriptor	desc;
@@ -147,13 +158,14 @@ struct imxdma_channel {
 	dma_addr_t			per_address;
 	u32				watermark_level;
 	struct dma_chan			chan;
-	spinlock_t			lock;
 	struct dma_async_tx_descriptor	desc;
 	enum dma_status			status;
 	int				dma_request;
 	struct scatterlist		*sg_list;
 	u32				ccr_from_device;
 	u32				ccr_to_device;
+	bool				enabled_2d;
+	int				slot_2d;
 };
 
 struct imxdma_engine {
@@ -162,6 +174,8 @@ struct imxdma_engine {
 	struct dma_device		dma_device;
 	void __iomem			*base;
 	struct clk			*dma_clk;
+	spinlock_t			lock;
+	struct imx_dma_2d_config	slots_2d[IMX_DMA_2D_SLOTS];
 	struct imxdma_channel		channel[IMX_DMA_CHANNELS];
 };
 
@@ -361,16 +375,16 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
-	spin_lock(&imxdmac->lock);
+	spin_lock(&imxdma->lock);
 	if (list_empty(&imxdmac->ld_active)) {
-		spin_unlock(&imxdmac->lock);
+		spin_unlock(&imxdma->lock);
 		goto out;
 	}
 
 	desc = list_first_entry(&imxdmac->ld_active,
 				struct imxdma_desc,
 				node);
-	spin_unlock(&imxdmac->lock);
+	spin_unlock(&imxdma->lock);
 
 	if (desc->sg) {
 		u32 tmp;
@@ -442,9 +456,53 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
+	unsigned long flags;
+	int slot = -1;
+	int i;
 
 	/* Configure and enable */
 	switch (d->type) {
+	case IMXDMA_DESC_INTERLEAVED:
+		/* Try to get a free 2D slot */
+		spin_lock_irqsave(&imxdma->lock, flags);
+		for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
+			if ((imxdma->slots_2d[i].count > 0) &&
+			((imxdma->slots_2d[i].xsr != d->x) ||
+			(imxdma->slots_2d[i].ysr != d->y) ||
+			(imxdma->slots_2d[i].wsr != d->w)))
+				continue;
+			slot = i;
+			break;
+		}
+		if (slot < 0)
+			return -EBUSY;
+
+		imxdma->slots_2d[slot].xsr = d->x;
+		imxdma->slots_2d[slot].ysr = d->y;
+		imxdma->slots_2d[slot].wsr = d->w;
+		imxdma->slots_2d[slot].count++;
+
+		imxdmac->slot_2d = slot;
+		imxdmac->enabled_2d = true;
+		spin_unlock_irqrestore(&imxdma->lock, flags);
+
+		if (slot == IMX_DMA_2D_SLOT_A) {
+			d->config_mem &= ~CCR_MSEL_B;
+			d->config_port &= ~CCR_MSEL_B;
+			imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
+			imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
+			imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
+		} else {
+			d->config_mem |= CCR_MSEL_B;
+			d->config_port |= CCR_MSEL_B;
+			imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
+			imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
+			imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
+		}
+		/*
+		 * We fall-through here intentionally, since a 2D transfer is
+		 * similar to MEMCPY just adding the 2D slot configuration.
+		 */
 	case IMXDMA_DESC_MEMCPY:
 		imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
 		imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
@@ -503,7 +561,7 @@ static void imxdma_tasklet(unsigned long data)
 	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	struct imxdma_desc *desc;
 
-	spin_lock(&imxdmac->lock);
+	spin_lock(&imxdma->lock);
 
 	if (list_empty(&imxdmac->ld_active)) {
 		/* Someone might have called terminate all */
@@ -520,6 +578,12 @@ static void imxdma_tasklet(unsigned long data)
 	if (imxdma_chan_is_doing_cyclic(imxdmac))
 		goto out;
 
+	/* Free 2D slot if it was an interleaved transfer */
+	if (imxdmac->enabled_2d) {
+		imxdma->slots_2d[imxdmac->slot_2d].count--;
+		imxdmac->enabled_2d = false;
+	}
+
 	list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
 
 	if (!list_empty(&imxdmac->ld_queue)) {
@@ -531,7 +595,7 @@ static void imxdma_tasklet(unsigned long data)
 				 __func__, imxdmac->channel);
 	}
 out:
-	spin_unlock(&imxdmac->lock);
+	spin_unlock(&imxdma->lock);
 }
 
 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
@@ -547,10 +611,10 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 	case DMA_TERMINATE_ALL:
 		imxdma_disable_hw(imxdmac);
 
-		spin_lock_irqsave(&imxdmac->lock, flags);
+		spin_lock_irqsave(&imxdma->lock, flags);
 		list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 		list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
-		spin_unlock_irqrestore(&imxdmac->lock, flags);
+		spin_unlock_irqrestore(&imxdma->lock, flags);
 		return 0;
 	case DMA_SLAVE_CONFIG:
 		if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
@@ -610,12 +674,13 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	dma_cookie_t cookie;
 	unsigned long flags;
 
-	spin_lock_irqsave(&imxdmac->lock, flags);
+	spin_lock_irqsave(&imxdma->lock, flags);
 	cookie = dma_cookie_assign(tx);
-	spin_unlock_irqrestore(&imxdmac->lock, flags);
+	spin_unlock_irqrestore(&imxdma->lock, flags);
 
 	return cookie;
 }
@@ -654,16 +719,17 @@ static int imxdma_alloc_chan_resources(struct dma_chan *chan)
 static void imxdma_free_chan_resources(struct dma_chan *chan)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
 	struct imxdma_desc *desc, *_desc;
 	unsigned long flags;
 
-	spin_lock_irqsave(&imxdmac->lock, flags);
+	spin_lock_irqsave(&imxdma->lock, flags);
 
 	imxdma_disable_hw(imxdmac);
 	list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 	list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 
-	spin_unlock_irqrestore(&imxdmac->lock, flags);
+	spin_unlock_irqrestore(&imxdma->lock, flags);
 
 	list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
 		kfree(desc);
@@ -818,6 +884,49 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
 	return &desc->desc;
 }
 
+static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
+	struct dma_chan *chan, struct dma_interleaved_template *xt,
+	unsigned long flags)
+{
+	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
+	struct imxdma_engine *imxdma = imxdmac->imxdma;
+	struct imxdma_desc *desc;
+
+	dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
+		"   src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
+		imxdmac->channel, xt->src_start, xt->dst_start,
+		xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
+		xt->numf, xt->frame_size);
+
+	if (list_empty(&imxdmac->ld_free) ||
+	    imxdma_chan_is_doing_cyclic(imxdmac))
+		return NULL;
+
+	if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
+		return NULL;
+
+	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
+
+	desc->type = IMXDMA_DESC_INTERLEAVED;
+	desc->src = xt->src_start;
+	desc->dest = xt->dst_start;
+	desc->x = xt->sgl[0].size;
+	desc->y = xt->numf;
+	desc->w = xt->sgl[0].icg + desc->x;
+	desc->len = desc->x * desc->y;
+	desc->direction = DMA_MEM_TO_MEM;
+	desc->config_port = IMX_DMA_MEMSIZE_32;
+	desc->config_mem = IMX_DMA_MEMSIZE_32;
+	if (xt->src_sgl)
+		desc->config_mem |= IMX_DMA_TYPE_2D;
+	if (xt->dst_sgl)
+		desc->config_port |= IMX_DMA_TYPE_2D;
+	desc->desc.callback = NULL;
+	desc->desc.callback_param = NULL;
+
+	return &desc->desc;
+}
+
 static void imxdma_issue_pending(struct dma_chan *chan)
 {
 	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
@@ -825,7 +934,7 @@ static void imxdma_issue_pending(struct dma_chan *chan)
 	struct imxdma_desc *desc;
 	unsigned long flags;
 
-	spin_lock_irqsave(&imxdmac->lock, flags);
+	spin_lock_irqsave(&imxdma->lock, flags);
 	if (list_empty(&imxdmac->ld_active) &&
 	    !list_empty(&imxdmac->ld_queue)) {
 		desc = list_first_entry(&imxdmac->ld_queue,
@@ -840,7 +949,7 @@ static void imxdma_issue_pending(struct dma_chan *chan)
 				       &imxdmac->ld_active);
 		}
 	}
-	spin_unlock_irqrestore(&imxdmac->lock, flags);
+	spin_unlock_irqrestore(&imxdma->lock, flags);
 }
 
 static int __init imxdma_probe(struct platform_device *pdev)
@@ -903,6 +1012,13 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
 	dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
 	dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
+	dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
+
+	/* Initialize 2D global parameters */
+	for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
+		imxdma->slots_2d[i].count = 0;
+
+	spin_lock_init(&imxdma->lock);
 
 	/* Initialize channel parameters */
 	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
@@ -923,7 +1039,6 @@ static int __init imxdma_probe(struct platform_device *pdev)
 		}
 
 		imxdmac->imxdma = imxdma;
-		spin_lock_init(&imxdmac->lock);
 
 		INIT_LIST_HEAD(&imxdmac->ld_queue);
 		INIT_LIST_HEAD(&imxdmac->ld_free);
@@ -949,6 +1064,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
 	imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
 	imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
 	imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
+	imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
 	imxdma->dma_device.device_control = imxdma_control;
 	imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
 
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Thu Mar 22 09:54:15 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Thu, 22 Mar 2012 14:54:15 +0100
Subject: [PATCH v4 15/15] dmaengine: i.MX: Fix merge of cookie branch.
In-Reply-To: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332424455-15594-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332424455-15594-16-git-send-email-javier.martin@vista-silicon.com>

When merging DMA cookie changes a small chunk
of code was dropped. This broke imx-dma driver.

This patch adds this chunk again and fixes the problem.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/dma/imx-dma.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index 2155d82..32b1f86 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -679,6 +679,7 @@ static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 	unsigned long flags;
 
 	spin_lock_irqsave(&imxdma->lock, flags);
+	list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
 	cookie = dma_cookie_assign(tx);
 	spin_unlock_irqrestore(&imxdma->lock, flags);
 
-- 
1.7.0.4



From subashrp at gmail.com  Thu Mar 22 09:59:42 2012
From: subashrp at gmail.com (Subash Patel)
Date: Thu, 22 Mar 2012 19:29:42 +0530
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <CAHQjnOMjSPDOymJe356AWnJszQv+X-QWrVrB7ahYDkXBr5HrQw@mail.gmail.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <CAHQjnOO5DLOj8Fw=ZriSnXg8W3k7y8Dnu--Peqe6JJX0xGMhoQ@mail.gmail.com>
 <4F688B2D.20808@gmail.com>
 <CAHQjnOMjSPDOymJe356AWnJszQv+X-QWrVrB7ahYDkXBr5HrQw@mail.gmail.com>
Message-ID: <4F6B304E.5010402@gmail.com>

Hi KyongHo,

On 03/21/2012 05:26 AM, KyongHo Cho wrote:
> On Tue, Mar 20, 2012 at 10:50 PM, Subash Patel<subashrp at gmail.com>  wrote:
>> Sorry for digging this very late. But as part of integrating dma_map v7&
>> sysmmu v12 on 3.3-rc5, I am facing below issue:
>>
>> a) By un-selecting IOMMU in menu config, I am able to allocate memory in
>> vb2-dma-contig
>>
>> b) When I enable SYSMMU support for the IP's, I am receiving below fault:
>>
>> Unhandled fault: external abort on non-linefetch (0x818) at 0xb6f55000
>>
>> I think this has something to do with the access to the SYSMMU registers for
>> writing the page table. Has anyone of you faced this issue while testing
>> these(dma_map+iommu) patches on kernel mentioned above? This must be
>> something related to recent changes, as I didn't have issues with these
>> patches on 3.2 kernel.
>>
>
> 0xb6f55000 is not an address of SYSMMU register if your kernel starts
> at 0xc0000000.
>
> Can you tell me any detailed information or situation?
I hate to say this, but I am not able to catch the fault location even 
with JTAG. Once the fault comes, the debugger looses all control over. I 
think now possible method is reproduction at your end :)
>
> Regards,
>
> KyongHo.
Regards,
Subash


From nicolas.ferre at atmel.com  Thu Mar 22 10:04:31 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 22 Mar 2012 15:04:31 +0100
Subject: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h
In-Reply-To: <20120322123327.GA14690@samfundet.no>
References: <1332296128-16262-1-git-send-email-paul.gortmaker@windriver.com>
 <20120321072632.GA15703@samfundet.no> <4F6990AF.2000004@atmel.com>
 <20120322051840.GC923@windriver.com> <20120322123327.GA14690@samfundet.no>
Message-ID: <4F6B316F.5080307@atmel.com>

On 03/22/2012 01:33 PM, Hans-Christian Egtvedt :
> Around Thu 22 Mar 2012 01:18:40 -0400 or thereabout, Paul Gortmaker wrote:
>> [Re: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h] On 21/03/2012 (Wed 09:26) Nicolas Ferre wrote:
>>
>>> On 03/21/2012 08:26 AM, Hans-Christian Egtvedt :
>>>> Around Tue 20 Mar 2012 22:15:28 -0400 or thereabout, Paul Gortmaker wrote:
>>>>> Commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c (linux-next)
>>>>>
>>>>>     "ATMEL: fix nand ecc support"
>>>>>
>>>>> indicated that it wanted to "Move platform data to a common
>>>>> header include/linux/platform_data/atmel_nand.h" and the new
>>>>> header even had re-include protectors with:
>>>>>
>>>>>     #ifndef __ATMEL_NAND_H__
>>>>>
>>>>> However, the file that was added was simply called atmel.h
>>>>> and this caused avr32 defconfig to fail with:
>>>>>
>>>>>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>>>>>   arch/avr32/mach-at32ap/include/mach/board.h:10:44: error: linux/platform_data/atmel_nand.h: No such file or directory
>>>>>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>>>>>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: 'struct atmel_nand_data' declared inside parameter list
>>>>>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: its scope is only this definition or declaration, which is probably not what you want
>>>>>   make[2]: *** [arch/avr32/boards/atstk1000/setup.o] Error 1
>>>>>
>>>>> Rename the file to match the original intention, and fix up the
>>>>> users who reference the bad name without the _nand suffix.
>>>>
>>>> Thanks fixing this.
>>>
>>>
>>> Yes, we need to fix this. But I would not like to see this
>>> "platform_data/atmel.h" renamed: I think that this file was designed to
>>> collect several common platform data (ie: not just NAND related).
>>>
>>> So maybe we should just rename the entry that exists in
>>> mach-at32ap/include/mach/board.h
>>> and remove all occurrences of platform_data/atmel_nand.h
>>
>> Funny, since this is what I did 1st before I re-read the original commit
>> log in more detail. :)  Oh well.  Here is the alternate solution.  You
>> guys can pick whichever one you like best.  I compile tested this one
>> as well.
> 
> I'll leave it to Nicolas to sign-off on this, but the changes look fine for
> me.

Ok, which way do you want to follow for inclusion in mainline? I take it
through arm-soc?

>> ---
>>
>> From 73c01b7ed8fd2732661fa1ca726c48096f4651f2 Mon Sep 17 00:00:00 2001
>> From: Paul Gortmaker <paul.gortmaker at windriver.com>
>> Date: Tue, 20 Mar 2012 21:55:46 -0400
>> Subject: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h
>>
>> Commit bf4289cba02b8cf770ecd7959ca70839f0dd9d3c (linux-next)
>>
>>     "ATMEL: fix nand ecc support"
>>
>> indicated that it wanted to "Move platform data to a common
>> header include/linux/platform_data/atmel_nand.h" and the new
>> header even had re-include protectors with:
>>
>>     #ifndef __ATMEL_NAND_H__
>>
>> However, the file that was added was simply called atmel.h
>> and this caused avr32 defconfig to fail with:
>>
>>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>>   arch/avr32/mach-at32ap/include/mach/board.h:10:44: error: linux/platform_data/atmel_nand.h: No such file or directory
>>   In file included from arch/avr32/boards/atstk1000/setup.c:22:
>>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: 'struct atmel_nand_data' declared inside parameter list
>>   arch/avr32/mach-at32ap/include/mach/board.h:121: warning: its scope is only this definition or declaration, which is probably not what you want
>>   make[2]: *** [arch/avr32/boards/atstk1000/setup.o] Error 1
>>
>> It seems the scope of the file contents will expand beyond
>> just nand, so ignore the original intention, and fix up the
>> users who reference the bad name with the _nand suffix.
>>
>> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
>> CC: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
>> CC: Hans-Christian Egtvedt <egtvedt at samfundet.no>
>> CC: David Woodhouse <dwmw2 at infradead.org>
> 
> Acked-by: Hans-Christian Egtvedt <egtvedt at samfundet.no>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> 
>> diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
>> index 7173386..70742ec 100644
>> --- a/arch/avr32/mach-at32ap/include/mach/board.h
>> +++ b/arch/avr32/mach-at32ap/include/mach/board.h
>> @@ -7,7 +7,7 @@
>>  #include <linux/types.h>
>>  #include <linux/serial.h>
>>  #include <linux/platform_data/macb.h>
>> -#include <linux/platform_data/atmel_nand.h>
>> +#include <linux/platform_data/atmel.h>
>>  
>>  #define GPIO_PIN_NONE	(-1)
>>  
>> diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel.h
>> index d056263..b0f2c56 100644
>> --- a/include/linux/platform_data/atmel.h
>> +++ b/include/linux/platform_data/atmel.h
>> @@ -4,8 +4,8 @@
>>   * GPL v2 Only
>>   */
>>  
>> -#ifndef __ATMEL_NAND_H__
>> -#define __ATMEL_NAND_H__
>> +#ifndef __ATMEL_H__
>> +#define __ATMEL_H__
>>  
>>  #include <linux/mtd/nand.h>
>>  
>> @@ -24,4 +24,4 @@ struct atmel_nand_data {
>>  	unsigned int	num_parts;
>>  };
>>  
>> -#endif /* __ATMEL_NAND_H__ */
>> +#endif /* __ATMEL_H__ */


-- 
Nicolas Ferre


From kgene.kim at samsung.com  Thu Mar 22 10:08:22 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 22 Mar 2012 07:08:22 -0700
Subject: [PATCH v4 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and
 EXYNOS5
In-Reply-To: <074401cd074f$c2946b90$47bd42b0$%szyprowski@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
 <1331736138-28964-6-git-send-email-kgene.kim@samsung.com>
 <CAJuYYwTJsA1M1Qj2P1-1K=pWzi0BPo8YJNDSx4NqGC7NX0030g@mail.gmail.com>
 <074401cd074f$c2946b90$47bd42b0$%szyprowski@samsung.com>
Message-ID: <4F6B3256.40304@samsung.com>

On 03/21/12 03:45, Marek Szyprowski wrote:
> Hello,
>
> On Wednesday, March 21, 2012 10:14 AM Thomas Abraham wrote:
>
>> On 14 March 2012 20:12, Kukjin Kim<kgene.kim at samsung.com>  wrote:
>>> Actually, the base address of uart is different between EXYNOS4
>>> and EXYNOS5 and this patch enables to support uart for EXYNOS4
>>> and EXYNOS5 SoCs at runtime.
>>>
>>> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
>>> ---
>>
>> [...]
>>
>>> diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-
>> exynos/include/mach/debug-macro.S
>>> index 6cacf16..6c857ff 100644
>>> --- a/arch/arm/mach-exynos/include/mach/debug-macro.S
>>> +++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
>>> @@ -21,8 +21,13 @@
>>>          */
>>>
>>>         .macro addruart, rp, rv, tmp
>>> -               ldr     \rp, = S3C_PA_UART
>>> -               ldr     \rv, = S3C_VA_UART
>>> +               mov     \rp, #0x10000000
>>
>> This is physical address of Exynos4/5 CPUID register which cannot be
>> used here. And virtual address S5P_VA_CPUID also cannot be used here
>> since this will be called before paging_init when earlyprintk boot
>> param is used. So, with this change, earlyprintk does not work for
>> both Exynos4 and Exynos5.
>
> I confirm, printascii freeze the system on EXYNOS4 after that patch,
> tested on Exynos4210 Nuri board.
>
Hi,

I think, it can be solved with following and if no problems, it will be 
fixed during v3.4-rcX.

diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S 
b/arch/arm/mach-exynos/in
index 6c857ff..a865417 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -21,10 +21,10 @@
          */

         .macro addruart, rp, rv, tmp
-               mov     \rp, #0x10000000
-               ldr     \rp, [\rp, #0x0]
-               and     \rp, \rp, #0xf00000
-               teq     \rp, #0x500000          @@ EXYNOS5
+               mrc     p15, 0, \tmp, c0, c0, 0
+               and     \tmp, \tmp, #0xf0
+               teq     \tmp, #0xf0             @@ A15
+
                 ldreq   \rp, =EXYNOS5_PA_UART
                 movne   \rp, #EXYNOS4_PA_UART   @@ EXYNOS4
                 ldr     \rv, =S3C_VA_UART


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From javier.martin at vista-silicon.com  Thu Mar 22 10:11:52 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Thu, 22 Mar 2012 15:11:52 +0100
Subject: [PATCH v3 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <CACKLOr03tTymT1vdTH7=nqEHu3OvAinPUHEusK+mR+J6Yc35mQ@mail.gmail.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
 <1332344363.19804.12.camel@vkoul-udesk3>
 <CACKLOr03tTymT1vdTH7=nqEHu3OvAinPUHEusK+mR+J6Yc35mQ@mail.gmail.com>
Message-ID: <CACKLOr0JTgp+poXCNg8+8pXko3s2JWQhovMw8Z1j-q4aL4oaKQ@mail.gmail.com>

On 22 March 2012 10:39, javier Martin <javier.martin at vista-silicon.com> wrote:
> On 21 March 2012 16:39, Vinod Koul <vinod.koul at linux.intel.com> wrote:
>> On Fri, 2012-03-09 at 16:20 +0100, Javier Martin wrote:
>>> The following series have to be applied on top of the following patches:
>>> [PATCH v2 1/2] dmaengine: Add support for MEMCPY for imx-dma.
>>> [PATCH v3 2/2] dmaengine: Add support for multiple descriptors for imx-dma.
>>>
>>> As discussed with Vinod and Sascha, the file 'arch/arm/mach-imx/dma-v1.c'
>>> is deprecated and no new patches are accepted for it.
>>>
>>> This series merges this code into the imx-dma.c dmaengine driver.
>>>
>>> Notes for v3:
>>> ?- I send the whole series again despite some patches being the same. I think
>>> ?this is more comfortable for Vinod than just sending those patches that have
>>> ?been modified.
>>> ?- I've generated my series with the following command this time:
>>> ?'git format-patch -s -13 -M -B --subject-prefix="PATCH v3"' as suggested by
>>> ?Sascha but still removing two files in 01/13 generates a lot of noisy diffs.
>>> ?Sorry about that.
>>> ?- I don't include Sascha's Tested-by since maybe he wants to test this last
>>> ?version.
>> This doesn't apply for me (starting with 6th) on current slave-dma.next
>> due to obvious changes which have gone into imx.
>>
>> Can you quickly rebase the series and resend.
>
> Great,
> now your 'next' branch is actually broken for imx-dma.
>
> I'm currently trying a bisect to find out what is the commit
> responsible for that but I suspect it will be related to the cookie
> changes submitted by Russell.

Here,
take a look at this series:

[PATCH v4 00/15] dmaengine: imx-dma: rebase of features for 3.4.

I've included a new fix patch which solves the merge issue.

Regards.
-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From prylowski at metasoft.pl  Thu Mar 22 10:13:45 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Thu, 22 Mar 2012 15:13:45 +0100
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <4F6B25A4.4090006@mvista.com>
References: <4F683B36.8090101@metasoft.pl> <4F6A78ED.3050403@gmail.com>
 <4F6AF845.9070209@metasoft.pl> <4F6B25A4.4090006@mvista.com>
Message-ID: <4F6B3399.2010501@metasoft.pl>

On 2012-03-22 14:14, Sergei Shtylyov wrote:
>    IDE or libata driver? Asking because IDE drivers are not accepted anymore.

Libata. Basically, it's the driver posted by Bartlomiej Zolnierkiewicz with
some changes (the most important being UDMA support).


From arnd at arndb.de  Thu Mar 22 10:20:09 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 22 Mar 2012 14:20:09 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <CAOh2x=k6ZfamB8DnPgVPjxZ7E1gTuHOQYg6s1Nd1ybA+TSquWA@mail.gmail.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203211236.37891.arnd@arndb.de>
 <CAOh2x=k6ZfamB8DnPgVPjxZ7E1gTuHOQYg6s1Nd1ybA+TSquWA@mail.gmail.com>
Message-ID: <201203221420.10127.arnd@arndb.de>

On Thursday 22 March 2012, viresh kumar wrote:
> On Mar 21, 2012 6:09 PM, "Arnd Bergmann" <arnd at arndb.de> wrote:
> > Regarding the spear3xx patches, I'm looking forward to your patches.
> > I think spear is simple and clean enough that it can serve as an example
> > for others doing DT conversion.
> 
> I was doing DT stuff for 3xx and have a doubt
> regarding DT. How are boards identified at runtime now? Earlier we had
> machine_is_*() to do that.

The direct replacement is of_machine_is_compatible(), but there are a lot
of cases where it's better to have a local property in the device node
that a driver is using.

For instance, in case of your clock driver, I would suggest you use
the "compatible" property of the clock device node, and do

/* null terminated array, turn the lookups into null termination as well */
struct of_device_id spear_clock_match = {
	{ "st,spear300-clock", &spear300_clk_lookups },
	{ "st,spear310-clock", &spear310_clk_lookups },
	{ "st,spear320-clock", &spear320_clk_lookups },
	{ },
};

void __init spear3xx_of_clk_init(void)
{
	struct device_node *np;
	struct of_device_id *match;
	struct clk_lookup *lookup;

	for_each_matching_node(np, &spear_clock_match)
		match = of_match_node(&spear_clock_match, np);

	for (lookup = match->data; lookup->clk; lookup++)
		clk_register(lookup);

	for (lookup = spear_clk_lookups; lookup->clk; lookup++)
		clk_register(lookup);
}

> Also why are both DT_MACHINE_START and MACHINE_START present on some SoC's?

This is for the transition phase where you want to be able to boot both
using ATAG and using DT.

	Arnd


From kumarrav at codeaurora.org  Thu Mar 22 10:22:02 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Thu, 22 Mar 2012 19:52:02 +0530
Subject: [PATCH v5 0/2] Add Qualcomm MSM ADM DMAEngine driver
Message-ID: <1332426122-25174-1-git-send-email-kumarrav@codeaurora.org>

Following are the changes we have done from the previous
v1 posted here: https://lkml.org/lkml/2011/12/22/148

As our ADM Scatter-gather hardware needs
-32-bit command configuration parameter
 apart from
-32-bit source address
-32-bit destination address
-16-bit length

So,we have added new parameter in struct scatterlist to support xfer descriptor
specific private data, and for supporting ADM Box mode DMA we added new
API and data structure.

Changes done from v2:

As per our previous discussion you had suggested us to follow the below patch
https://lkml.org/lkml/2012/1/26/405
Please check the below link of our discussion
https://lkml.org/lkml/2012/1/30/48

So we have added the new context parameter in device_prep_dma_sg and
device_prep_interleave_dma API's to support for passing client channel specific
private data associated with every transfer descriptor.

We are using
Interleaved API for BOX type transfer.
SG API for SG type transfer.

Changes done from v3:

Implemented the wrappers as suggested by Russell King in following patch
https://lkml.org/lkml/2012/2/3/269
Fixed the dmaengine & client drivers to follow above changes

Changes done from v4:

Changed return value of prep_dma_sg & prep_interleaved_dma to NULL
when some thing fails inside the API
 
Ravi Kumar V (2):
  dmaengine: Add context parameter to prep_dma_sg and
    prep_interleaved_dma
  DMAEngine: Add DMAEngine driver based on old MSM ADM DMA APIs

 arch/arm/mach-msm/include/mach/dma.h    |   35 ++
 drivers/dma/Kconfig                     |   12 +
 drivers/dma/Makefile                    |    1 +
 drivers/dma/fsldma.c                    |    2 +-
 drivers/dma/msm_adm_dma.c               |  728 +++++++++++++++++++++++++++++++
 drivers/dma/sirf-dma.c                  |    2 +-
 drivers/dma/ste_dma40.c                 |    2 +-
 drivers/misc/carma/carma-fpga-program.c |    2 +-
 drivers/misc/carma/carma-fpga.c         |    7 +-
 include/linux/dmaengine.h               |   22 +-
 10 files changed, 803 insertions(+), 10 deletions(-)
 create mode 100644 drivers/dma/msm_adm_dma.c

-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From kumarrav at codeaurora.org  Thu Mar 22 10:22:47 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Thu, 22 Mar 2012 19:52:47 +0530
Subject: [PATCH v5 1/2] dmaengine: Add context parameter to prep_dma_sg and
 prep_interleaved_dma
Message-ID: <1332426167-25213-1-git-send-email-kumarrav@codeaurora.org>

Add new context parameter to DMA SG and Interleaveid mode for passing
per transfer specific private data, using this it enables the
dma devices which needs to pass the parameters which changes per
each transfer

Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
---
 drivers/dma/fsldma.c                    |    2 +-
 drivers/dma/sirf-dma.c                  |    2 +-
 drivers/dma/ste_dma40.c                 |    2 +-
 drivers/misc/carma/carma-fpga-program.c |    2 +-
 drivers/misc/carma/carma-fpga.c         |    7 +++----
 include/linux/dmaengine.h               |   22 ++++++++++++++++++++--
 6 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index b98070c..f9f77db 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -645,7 +645,7 @@ fail:
 static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
 	struct scatterlist *dst_sg, unsigned int dst_nents,
 	struct scatterlist *src_sg, unsigned int src_nents,
-	unsigned long flags)
+	unsigned long flags, void *context)
 {
 	struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
 	struct fsldma_chan *chan = to_fsl_chan(dchan);
diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
index 2333810..ff4d344 100644
--- a/drivers/dma/sirf-dma.c
+++ b/drivers/dma/sirf-dma.c
@@ -428,7 +428,7 @@ sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 
 static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
 	struct dma_chan *chan, struct dma_interleaved_template *xt,
-	unsigned long flags)
+	unsigned long flags, void *context)
 {
 	struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
 	struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index cc5ecbc..2f58ba9 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2287,7 +2287,7 @@ static struct dma_async_tx_descriptor *
 d40_prep_memcpy_sg(struct dma_chan *chan,
 		   struct scatterlist *dst_sg, unsigned int dst_nents,
 		   struct scatterlist *src_sg, unsigned int src_nents,
-		   unsigned long dma_flags)
+		   unsigned long dma_flags, void *context)
 {
 	if (dst_nents != src_nents)
 		return NULL;
diff --git a/drivers/misc/carma/carma-fpga-program.c b/drivers/misc/carma/carma-fpga-program.c
index a2d25e4..3739a12 100644
--- a/drivers/misc/carma/carma-fpga-program.c
+++ b/drivers/misc/carma/carma-fpga-program.c
@@ -530,7 +530,7 @@ static noinline int fpga_program_dma(struct fpga_dev *priv)
 	}
 
 	/* setup and submit the DMA transaction */
-	tx = chan->device->device_prep_dma_sg(chan,
+	tx = chan->device->dmaengine_prep_dma_sg(chan,
 					      table.sgl, num_pages,
 					      vb->sglist, vb->sglen, 0);
 	if (!tx) {
diff --git a/drivers/misc/carma/carma-fpga.c b/drivers/misc/carma/carma-fpga.c
index 14e974b2..be0baf6 100644
--- a/drivers/misc/carma/carma-fpga.c
+++ b/drivers/misc/carma/carma-fpga.c
@@ -638,10 +638,9 @@ static int data_submit_dma(struct fpga_device *priv, struct data_buf *buf)
 	 */
 
 	/* setup the scatterlist to scatterlist transfer */
-	tx = chan->device->device_prep_dma_sg(chan,
-					      dst_sg, dst_nents,
-					      src_sg, src_nents,
-					      0);
+	tx = dmaengine_prep_dma_sg(chan, dst_sg, dst_nents,
+					 src_sg, src_nents,
+					 0);
 	if (!tx) {
 		dev_err(priv->dev, "unable to prep scatterlist DMA\n");
 		return -ENOMEM;
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 679b349..68a57da 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -570,7 +570,7 @@ struct dma_device {
 		struct dma_chan *chan,
 		struct scatterlist *dst_sg, unsigned int dst_nents,
 		struct scatterlist *src_sg, unsigned int src_nents,
-		unsigned long flags);
+		unsigned long flags, void *context);
 
 	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
 		struct dma_chan *chan, struct scatterlist *sgl,
@@ -581,7 +581,7 @@ struct dma_device {
 		size_t period_len, enum dma_transfer_direction direction);
 	struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
 		struct dma_chan *chan, struct dma_interleaved_template *xt,
-		unsigned long flags);
+		unsigned long flags, void *context);
 	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		unsigned long arg);
 
@@ -615,6 +615,24 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
 	return chan->device->device_prep_slave_sg(chan, &sg, 1, dir, flags);
 }
 
+static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
+			struct dma_chan *chan, struct scatterlist *dst_sg,
+			unsigned int dst_nents,	struct scatterlist *src_sg,
+			unsigned int src_nents,	unsigned long flags)
+{
+	return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents,
+					src_sg, src_nents, flags, NULL);
+}
+
+static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
+			struct dma_chan *chan,
+			struct dma_interleaved_template *xt,
+			unsigned long flags)
+{
+	return chan->device->device_prep_interleaved_dma(chan, xt,
+							flags, NULL);
+}
+
 static inline int dmaengine_terminate_all(struct dma_chan *chan)
 {
 	return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From kumarrav at codeaurora.org  Thu Mar 22 10:23:36 2012
From: kumarrav at codeaurora.org (Ravi Kumar V)
Date: Thu, 22 Mar 2012 19:53:36 +0530
Subject: [PATCH v5 2/2] DMAEngine: Add DMAEngine driver based on old MSM ADM
 DMA APIs
Message-ID: <1332426216-25273-1-git-send-email-kumarrav@codeaurora.org>

Add DMAEngine based driver using the old MSM ADM DMA APIs internally.
The benefit of this approach is that not all the drivers
have to get converted to DMAEngine APIs simultaneosly while
both the drivers can stay enabled in the kernel. The client
drivers using the old MSM APIs directly can now convert to
DMAEngine one by one.

Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
---
 arch/arm/mach-msm/include/mach/dma.h |   35 ++
 drivers/dma/Kconfig                  |   12 +
 drivers/dma/Makefile                 |    1 +
 drivers/dma/msm_adm_dma.c            |  728 ++++++++++++++++++++++++++++++++++
 4 files changed, 776 insertions(+), 0 deletions(-)
 create mode 100644 drivers/dma/msm_adm_dma.c

diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 05583f5..95b7b15 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -18,6 +18,36 @@
 #include <linux/list.h>
 #include <mach/msm_iomap.h>
 
+#define sg_dma_offset(sg)               ((sg)->offset)
+#define box_dma_row_address(box)        ((box)->dma_row_address)
+#define box_dma_row_len(box)            ((box)->dma_row_len)
+#define box_dma_row_num(box)            ((box)->dma_row_num)
+#define box_dma_row_offset(box)         ((box)->dma_row_offset)
+
+#define MSM_DMA_CMD_MASK		0x9FFF8
+#define MSM_DMA_CMD_SHIFT		0
+#define MSM_BOX_SRC_RLEN_MASK		0xFFFF
+#define MSM_BOX_SRC_RLEN_SHIFT		16
+#define MSM_BOX_SRC_RNUM_MASK		0xFFFF
+#define MSM_BOX_SRC_RNUM_SHIFT		16
+#define MSM_BOX_SRC_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_SRC_ROFFSET_SHIFT	16
+#define MSM_BOX_DST_RLEN_MASK		0xFFFF
+#define MSM_BOX_DST_RNUM_MASK		0xFFFF
+#define MSM_BOX_DST_ROFFSET_MASK	0xFFFF
+#define MSM_BOX_MODE_CMD		0x3
+
+enum adm_flush_type {
+	ADM_FORCED_FLUSH,
+	ADM_GRACEFUL_FLUSH,
+};
+
+enum adm_dma_type {
+	ADM_SINGLE_MODE,
+	ADM_SG_MODE,
+	ADM_BOX_MODE,
+};
+
 struct msm_dmov_errdata {
 	uint32_t flush[6];
 };
@@ -32,6 +62,11 @@ struct msm_dmov_cmd {
 	void *data;
 };
 
+struct msm_adm_cmd_config {
+	uint32_t num_cmd;
+	uint32_t *cmd_cntrl;
+};
+
 #ifndef CONFIG_ARCH_MSM8X60
 void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
 void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index f1a2749..1f99362 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -252,6 +252,18 @@ config EP93XX_DMA
 	help
 	  Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
 
+config MSM_ADM_DMA
+	tristate "Qualcomm MSM ADM DMA support"
+	depends on ARCH_MSM
+	select DMA_ENGINE
+	help
+	  Support the Qualcomm DMA engine. This engine is integrated into
+	  Qualcomm chips.
+
+	  Say Y here if you have such a chipset.
+
+	  If unsure, say N.
+
 config DMA_ENGINE
 	bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 009a222..f55fb57 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
 obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
 obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
 obj-$(CONFIG_IMX_DMA) += imx-dma.o
+obj-$(CONFIG_MSM_ADM_DMA) += msm_adm_dma.o
 obj-$(CONFIG_MXS_DMA) += mxs-dma.o
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
diff --git a/drivers/dma/msm_adm_dma.c b/drivers/dma/msm_adm_dma.c
new file mode 100644
index 0000000..55038d1
--- /dev/null
+++ b/drivers/dma/msm_adm_dma.c
@@ -0,0 +1,728 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/dmapool.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/dma.h>
+
+#define SD3_CHAN_START			0
+#define MSM_DMOV_CRCI_COUNT		16
+#define MSM_DMA_MAX_CHANS_PER_DEVICE	16
+#define MAX_TRANSFER_LENGTH		65535
+#define NO_ERR_CHAN_STATUS		0x80000002
+#define to_msm_chan(chan) container_of(chan, struct msm_dma_chan, channel)
+
+struct msm_dma_chan {
+	int chan_id;
+	dma_cookie_t completed_cookie;
+	dma_cookie_t error_cookie;
+	spinlock_t lock;
+	struct list_head active_list;
+	struct list_head pending_list;
+	struct dma_chan channel;
+	struct dma_pool *desc_pool;
+	struct device *dev;
+	int max_len;
+	int err;
+	struct tasklet_struct tasklet;
+};
+
+struct msm_dma_device {
+	void __iomem *base;
+	struct device *dev;
+	struct dma_device common;
+	struct msm_dma_chan *chan[MSM_DMA_MAX_CHANS_PER_DEVICE];
+};
+
+struct msm_dma_desc_hw {
+	unsigned int cmd_list_ptr;
+} __aligned(8);
+
+/* Single Item Mode */
+struct adm_cmd_t {
+	unsigned int cmd_cntrl;
+	unsigned int src;
+	unsigned int dst;
+	unsigned int len;
+};
+
+struct adm_box_cmd_t {
+	uint32_t cmd_cntrl;
+	uint32_t src_row_addr;
+	uint32_t dst_row_addr;
+	uint32_t src_dst_len;
+	uint32_t num_rows;
+	uint32_t row_offset;
+};
+
+struct msm_dma_desc_sw {
+	struct msm_dma_desc_hw hw;
+	struct adm_cmd_t *vaddr_cmd;
+	struct adm_box_cmd_t *vaddr_box_cmd;
+	size_t coherent_size;
+	dma_addr_t paddr_cmd_list;
+	struct list_head node;
+	struct msm_dmov_cmd dmov_cmd;
+	struct dma_async_tx_descriptor async_tx;
+} __aligned(8);
+
+static int msm_dma_alloc_chan_resources(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+
+	/* Has this channel already been allocated? */
+	if (chan->desc_pool)
+		return 1;
+
+	/*
+	 * We need the descriptor to be aligned to 8bytes
+	 * for meeting ADM specification requirement.
+	 */
+	chan->desc_pool = dma_pool_create("msm_dma_desc_pool",
+					chan->dev,
+					sizeof(struct msm_dma_desc_sw),
+				__alignof__(struct msm_dma_desc_sw), 0);
+	if (!chan->desc_pool) {
+		dev_err(chan->dev, "unable to allocate channel %d "
+				"descriptor pool\n", chan->chan_id);
+		return -ENOMEM;
+	}
+
+	chan->completed_cookie = 1;
+	dchan->cookie = 1;
+
+	/* there is at least one descriptor free to be allocated */
+	return 1;
+}
+
+static void msm_dma_free_desc_list(struct msm_dma_chan *chan,
+						struct list_head *list)
+{
+	struct msm_dma_desc_sw *desc, *_desc;
+
+	list_for_each_entry_safe(desc, _desc, list, node) {
+		list_del(&desc->node);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	}
+}
+
+static void msm_dma_free_chan_resources(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	unsigned long flags;
+
+	dev_dbg(chan->dev, "Free all channel resources.\n");
+	spin_lock_irqsave(&chan->lock, flags);
+	msm_dma_free_desc_list(chan, &chan->active_list);
+	msm_dma_free_desc_list(chan, &chan->pending_list);
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	dma_pool_destroy(chan->desc_pool);
+	chan->desc_pool = NULL;
+}
+
+static enum dma_status msm_dma_desc_status(struct msm_dma_chan *chan,
+					struct msm_dma_desc_sw *desc)
+{
+	return dma_async_is_complete(desc->async_tx.cookie,
+					chan->completed_cookie,
+					chan->channel.cookie);
+}
+
+static void msm_chan_desc_cleanup(struct msm_dma_chan *chan)
+{
+	struct msm_dma_desc_sw *desc, *_desc;
+	unsigned long flags;
+
+	dev_dbg(chan->dev, "Cleaning completed descriptor of channel %d\n",
+							chan->chan_id);
+	spin_lock_irqsave(&chan->lock, flags);
+
+	list_for_each_entry_safe(desc, _desc, &chan->active_list, node) {
+		dma_async_tx_callback callback;
+		void *callback_param;
+
+		if (msm_dma_desc_status(chan, desc) == DMA_IN_PROGRESS)
+			break;
+
+		/* Remove from the list of running transactions */
+		list_del(&desc->node);
+
+		/* Run the link descriptor callback function */
+		callback = desc->async_tx.callback;
+		callback_param = desc->async_tx.callback_param;
+		if (callback) {
+			spin_unlock_irqrestore(&chan->lock, flags);
+			callback(callback_param);
+			spin_lock_irqsave(&chan->lock, flags);
+		}
+
+		/* Run any dependencies, then free the descriptor */
+		dma_run_dependencies(&desc->async_tx);
+		spin_unlock_irqrestore(&chan->lock, flags);
+
+		if (desc->vaddr_cmd) {
+			dma_free_coherent(chan->dev, desc->coherent_size,
+						(void *)desc->vaddr_cmd,
+							desc->paddr_cmd_list);
+		} else {
+			dma_free_coherent(chan->dev, desc->coherent_size,
+						(void *)desc->vaddr_box_cmd,
+							desc->paddr_cmd_list);
+		}
+		spin_lock_irqsave(&chan->lock, flags);
+		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	}
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+static void dma_do_tasklet(unsigned long data)
+{
+	struct msm_dma_chan *chan = (struct msm_dma_chan *)data;
+	msm_chan_desc_cleanup(chan);
+}
+
+static void
+msm_dma_complete_func(struct msm_dmov_cmd *cmd,
+				unsigned int result,
+				struct msm_dmov_errdata *err)
+{
+	unsigned long flags;
+	struct msm_dma_desc_sw *desch = container_of(cmd,
+				struct msm_dma_desc_sw, dmov_cmd);
+	struct msm_dma_chan *chan = to_msm_chan(desch->async_tx.chan);
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if ((result != NO_ERR_CHAN_STATUS) && err)
+		chan->error_cookie = desch->async_tx.cookie;
+	chan->completed_cookie = desch->async_tx.cookie;
+
+	tasklet_schedule(&chan->tasklet);
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+/*
+ *  Passes transfer descriptors to DMA hardware.
+ */
+static void msm_dma_issue_pending(struct dma_chan *dchan)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	struct msm_dma_desc_sw *desch;
+	unsigned long flags;
+
+	if (chan->err)
+		return;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	if (list_empty(&chan->pending_list))
+		goto out_unlock;
+
+	desch = list_first_entry(&chan->pending_list, struct msm_dma_desc_sw,
+									node);
+	list_del(&desch->node);
+	desch->dmov_cmd.complete_func = msm_dma_complete_func;
+	desch->dmov_cmd.execute_func = NULL;
+	desch->dmov_cmd.cmdptr = DMOV_CMD_ADDR(desch->async_tx.phys);
+	list_add_tail(&desch->node, &chan->active_list);
+	mb();
+	msm_dmov_enqueue_cmd(chan->chan_id, &desch->dmov_cmd);
+out_unlock:
+	spin_unlock_irqrestore(&chan->lock, flags);
+}
+
+/*
+ *  Assignes cookie for each transfer descriptor passed.
+ *  Returns
+ *	Assigend cookie for success.
+ *	Error value for failure.
+ */
+static dma_cookie_t msm_dma_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	struct msm_dma_chan *chan = to_msm_chan(tx->chan);
+	struct msm_dma_desc_sw *desc = container_of(tx,
+	struct msm_dma_desc_sw, async_tx);
+	unsigned long flags;
+	dma_cookie_t cookie = -EBUSY;
+
+	if (chan->err)
+		return cookie;
+
+	spin_lock_irqsave(&chan->lock, flags);
+
+	/*
+	 * assign cookies to all of the software descriptors
+	 * that make up this transaction
+	 */
+	cookie = chan->channel.cookie;
+	cookie++;
+	if (cookie < 0)
+		cookie = DMA_MIN_COOKIE;
+
+	desc->async_tx.cookie = cookie;
+	chan->channel.cookie = cookie;
+
+	/* put this transaction onto the tail of the pending queue */
+	list_add_tail(&desc->node, &chan->pending_list);
+
+	spin_unlock_irqrestore(&chan->lock, flags);
+
+	return cookie;
+}
+
+/*
+ *  Returns the DMA transfer status of a particular cookie
+ */
+static enum dma_status msm_tx_status(struct dma_chan *dchan,
+					dma_cookie_t cookie,
+				struct dma_tx_state *txstate)
+{
+	struct msm_dma_chan *chan = to_msm_chan(dchan);
+	dma_cookie_t last_used;
+	dma_cookie_t last_complete;
+	enum dma_status status;
+
+	last_used = dchan->cookie;
+	last_complete = chan->completed_cookie;
+
+	dma_set_tx_state(txstate, last_complete, last_used, 0);
+
+	status = dma_async_is_complete(cookie, last_complete, last_used);
+
+	if (status != DMA_IN_PROGRESS)
+		if (chan->error_cookie == cookie)
+			status = DMA_ERROR;
+
+	return status;
+}
+
+static struct msm_dma_desc_sw *msm_dma_alloc_descriptor(
+				struct msm_dma_chan *chan,
+				int cmd_cnt,
+				enum adm_dma_type mask)
+{
+	struct msm_dma_desc_sw *desc;
+	dma_addr_t pdesc_addr;
+	dma_addr_t paddr_cmd_list;
+	void *err = NULL;
+
+	desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc_addr);
+	if (!desc) {
+		dev_dbg(chan->dev, "out of memory for desc\n");
+		return ERR_CAST(desc);
+	}
+
+	memset(desc, 0, sizeof(*desc));
+	desc->async_tx.phys = pdesc_addr;
+
+	if (mask == ADM_BOX_MODE) {
+		desc->coherent_size = sizeof(struct adm_box_cmd_t);
+		desc->vaddr_box_cmd = dma_alloc_coherent(chan->dev,
+				sizeof(struct adm_box_cmd_t),
+				&paddr_cmd_list, GFP_ATOMIC);
+		if (!desc->vaddr_box_cmd) {
+			dev_dbg(chan->dev, "out of memory for desc\n");
+			err = desc->vaddr_box_cmd;
+			goto fail;
+		}
+	} else {
+		desc->coherent_size = sizeof(struct adm_cmd_t)*cmd_cnt;
+
+		desc->vaddr_cmd = dma_alloc_coherent(chan->dev,
+				sizeof(struct adm_cmd_t)*cmd_cnt,
+				&paddr_cmd_list, GFP_ATOMIC);
+
+		if (!desc->vaddr_cmd) {
+			dev_dbg(chan->dev, "out of memory for desc\n");
+			err = desc->vaddr_cmd;
+			goto fail;
+		}
+	}
+
+	dma_async_tx_descriptor_init(&desc->async_tx, &chan->channel);
+	desc->async_tx.tx_submit = msm_dma_tx_submit;
+	desc->paddr_cmd_list = paddr_cmd_list;
+	desc->hw.cmd_list_ptr = (paddr_cmd_list >> 3) | CMD_PTR_LP;
+	return desc;
+fail:
+	dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+	return ERR_CAST(err);
+}
+
+/*
+ *  Prepares the transfer descriptors for SG transaction.
+ *  Returns
+ *	address of dma_async_tx_descriptor for success.
+ *	Pointer of error value for failure.
+ */
+static struct dma_async_tx_descriptor *msm_dma_prep_sg(
+		struct dma_chan *dchan,
+		struct scatterlist *dst_sg, unsigned int dst_nents,
+		struct scatterlist *src_sg, unsigned int src_nents,
+		unsigned long flags, void *context)
+{
+
+	struct msm_dma_chan *chan;
+	struct msm_dma_desc_sw *new;
+	size_t copy, len;
+	int cmd_cnt = 0;
+	int first = 0;
+	int i;
+	dma_addr_t src;
+	dma_addr_t dst;
+	struct adm_cmd_t *cmdlist_vaddr;
+	struct scatterlist *sg;
+	struct msm_adm_cmd_config *cmd_config = context;
+
+	if (!dchan)
+		return NULL;
+
+	if (dst_nents == 0 || src_nents == 0)
+		return NULL;
+	if (!dst_sg || !src_sg)
+		return NULL;
+
+	if ((dst_nents != src_nents) || (cmd_config->num_cmd != src_nents))
+		return NULL;
+
+	chan = to_msm_chan(dchan);
+
+	cmd_cnt = src_nents;
+	for (i = 0; i < src_nents; i++) {
+		len = sg_dma_len(src_sg + i);
+		if (len != MAX_TRANSFER_LENGTH)
+			cmd_cnt += len/MAX_TRANSFER_LENGTH;
+	}
+
+	new = msm_dma_alloc_descriptor(chan, cmd_cnt, ADM_SG_MODE);
+
+	if (!new) {
+		dev_err(chan->dev,
+			"No free memory for link descriptor\n");
+		return NULL;
+	}
+
+	cmdlist_vaddr = new->vaddr_cmd;
+
+	for_each_sg(src_sg, sg, src_nents, i) {
+		len = sg_dma_len(sg);
+		src = sg_dma_address(sg);
+		do {
+			copy = (len >= MAX_TRANSFER_LENGTH) ?
+						MAX_TRANSFER_LENGTH : len;
+			cmdlist_vaddr->src = src;
+			cmdlist_vaddr->len = copy;
+			cmdlist_vaddr->cmd_cntrl =
+					*(cmd_config->cmd_cntrl + i) &
+							MSM_DMA_CMD_MASK;
+			if (first == 0) {
+				if (cmd_cnt == 1)
+					cmdlist_vaddr->cmd_cntrl |= CMD_LC;
+				else
+					cmdlist_vaddr->cmd_cntrl |= CMD_OCB;
+				first = 1;
+			}
+			cmdlist_vaddr++;
+			len -= copy;
+			src += copy;
+		} while (len);
+	}
+	if (cmd_cnt > 1) {
+		cmdlist_vaddr--;
+		cmdlist_vaddr->cmd_cntrl |= CMD_LC | CMD_OCU;
+	}
+
+	cmdlist_vaddr = new->vaddr_cmd;
+
+	for_each_sg(dst_sg, sg, src_nents, i) {
+		len = sg_dma_len(sg);
+		dst = sg_dma_address(sg);
+		do {
+			copy = (len >= MAX_TRANSFER_LENGTH) ?
+					MAX_TRANSFER_LENGTH : len;
+			cmdlist_vaddr->dst = dst;
+			cmdlist_vaddr++;
+			len -= copy;
+			dst += copy;
+		} while (len);
+
+	}
+
+#ifdef DEBUG
+	cmdlist_vaddr = new->vaddr_cmd;
+	i = 0;
+	do {
+		dev_dbg(chan->dev, "cmd %d src 0x%x dst 0x%x len 0x%x "
+						"cntrl 0x%x\n",
+				i, cmdlist_vaddr->src, cmdlist_vaddr->dst,
+				cmdlist_vaddr->len, cmdlist_vaddr->cmd_cntrl);
+			cmdlist_vaddr++;
+	} while (!((cmdlist_vaddr-1)->cmd_cntrl & CMD_LC));
+#endif
+	new->async_tx.flags = flags;
+	new->async_tx.cookie = -EBUSY;
+
+	return &new->async_tx;
+}
+
+struct dma_async_tx_descriptor *msm_dma_prep_interleaved(
+				struct dma_chan *dchan,
+				struct dma_interleaved_template *xt,
+				unsigned long flags,
+				void *context)
+{
+
+	struct msm_dma_chan *chan;
+	struct msm_dma_desc_sw *new;
+	struct adm_box_cmd_t *box_cmd_vaddr;
+	struct msm_adm_cmd_config *cmd_config = context;
+
+	if (!dchan)
+		return NULL;
+
+	if (!xt)
+		return NULL;
+
+	chan = to_msm_chan(dchan);
+
+	new = msm_dma_alloc_descriptor(chan, 1, ADM_BOX_MODE);
+
+	if (!new) {
+		dev_err(chan->dev,
+			"No free memory for link descriptor\n");
+		return NULL;
+	}
+
+	box_cmd_vaddr = new->vaddr_box_cmd;
+
+
+	box_cmd_vaddr->src_row_addr = xt->src_start;
+	box_cmd_vaddr->dst_row_addr = xt->dst_start;
+	box_cmd_vaddr->src_dst_len =
+			((xt->sgl[0].size & MSM_BOX_SRC_RLEN_MASK) <<
+					MSM_BOX_SRC_RLEN_SHIFT) |
+				(xt->sgl[0].size & MSM_BOX_DST_RLEN_MASK);
+
+	box_cmd_vaddr->cmd_cntrl =
+			(cmd_config->cmd_cntrl[0] & MSM_DMA_CMD_MASK) |
+						MSM_BOX_MODE_CMD | CMD_LC;
+
+	box_cmd_vaddr->num_rows =
+			((xt->numf & MSM_BOX_SRC_RNUM_MASK) <<
+			MSM_BOX_SRC_RNUM_SHIFT) |
+			(xt->numf & MSM_BOX_DST_RNUM_MASK);
+
+	if ((xt->src_sgl) && (xt->src_inc))
+		box_cmd_vaddr->row_offset =
+				((xt->sgl[0].size + xt->sgl[0].icg) &
+				MSM_BOX_SRC_ROFFSET_MASK) <<
+				MSM_BOX_SRC_ROFFSET_SHIFT;
+	else if ((!xt->src_sgl) && (xt->src_inc))
+		box_cmd_vaddr->row_offset = ((xt->sgl[0].size) &
+				MSM_BOX_SRC_ROFFSET_MASK) <<
+				MSM_BOX_SRC_ROFFSET_SHIFT;
+	else
+		box_cmd_vaddr->row_offset =
+			(0 & MSM_BOX_SRC_ROFFSET_MASK) <<
+			MSM_BOX_SRC_ROFFSET_SHIFT;
+
+
+	if ((xt->dst_sgl) && (xt->dst_inc))
+		box_cmd_vaddr->row_offset |=
+			((xt->sgl[0].size + xt->sgl[0].icg) &
+			MSM_BOX_DST_ROFFSET_MASK);
+	else if ((!xt->dst_sgl) && (xt->dst_inc))
+		box_cmd_vaddr->row_offset |= ((xt->sgl[0].size) &
+					MSM_BOX_DST_ROFFSET_MASK);
+	else
+		box_cmd_vaddr->row_offset |= (0 & MSM_BOX_DST_ROFFSET_MASK);
+
+	new->async_tx.flags = flags;
+	new->async_tx.cookie = -EBUSY;
+
+	return &new->async_tx;
+}
+
+/*
+ *  Controlling the hardware channel like stopping, flushing.
+ */
+static int msm_dma_chan_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+							unsigned long arg)
+{
+	enum adm_flush_type cmd_type = arg;
+
+	if (cmd == DMA_TERMINATE_ALL) {
+		switch (cmd_type) {
+		case ADM_GRACEFUL_FLUSH:
+				msm_dmov_stop_cmd(chan->chan_id, NULL, 1);
+			break;
+		case ADM_FORCED_FLUSH:
+			/*
+			 * We treate default as forced flush
+			 * so we fall through
+			 */
+		default:
+				msm_dmov_stop_cmd(chan->chan_id, NULL, 0);
+			break;
+		}
+	}
+	return 0;
+}
+
+static void msm_dma_chan_remove(struct msm_dma_chan *chan)
+{
+	tasklet_kill(&chan->tasklet);
+	list_del(&chan->channel.device_node);
+	kfree(chan);
+}
+
+static __devinit int msm_dma_chan_probe(struct msm_dma_device *qdev,
+					int channel)
+{
+	struct msm_dma_chan *chan;
+
+	chan = kzalloc(sizeof(*chan), GFP_KERNEL);
+	if (!chan) {
+		dev_err(qdev->dev, "no free memory for DMA channels!\n");
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&chan->lock);
+	INIT_LIST_HEAD(&chan->pending_list);
+	INIT_LIST_HEAD(&chan->active_list);
+
+	chan->chan_id = channel;
+	chan->completed_cookie = 0;
+	chan->channel.cookie = 0;
+	chan->max_len = MAX_TRANSFER_LENGTH;
+	chan->err = 0;
+	qdev->chan[channel] = chan;
+	chan->channel.device = &qdev->common;
+	chan->dev = qdev->dev;
+
+	tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
+
+	list_add_tail(&chan->channel.device_node, &qdev->common.channels);
+	qdev->common.chancnt++;
+
+	return 0;
+}
+
+static int __devinit msm_dma_probe(struct platform_device *pdev)
+{
+	struct msm_dma_device *qdev;
+	int i;
+	int ret = 0;
+
+	qdev = kzalloc(sizeof(*qdev), GFP_KERNEL);
+	if (!qdev) {
+		dev_err(&pdev->dev, "Not enough memory for device\n");
+		return -ENOMEM;
+	}
+
+	qdev->dev = &pdev->dev;
+	INIT_LIST_HEAD(&qdev->common.channels);
+	qdev->common.device_alloc_chan_resources =
+				msm_dma_alloc_chan_resources;
+	qdev->common.device_free_chan_resources =
+				msm_dma_free_chan_resources;
+	dma_cap_set(DMA_SG, qdev->common.cap_mask);
+	dma_cap_set(DMA_INTERLEAVE, qdev->common.cap_mask);
+
+	qdev->common.device_prep_dma_sg = msm_dma_prep_sg;
+	qdev->common.device_prep_interleaved_dma = msm_dma_prep_interleaved;
+	qdev->common.device_issue_pending = msm_dma_issue_pending;
+	qdev->common.dev = &pdev->dev;
+	qdev->common.device_tx_status = msm_tx_status;
+	qdev->common.device_control = msm_dma_chan_control;
+
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		ret = msm_dma_chan_probe(qdev, i);
+		if (ret) {
+			dev_err(&pdev->dev, "channel %d probe failed\n", i);
+			goto chan_free;
+		}
+	}
+
+	dev_info(&pdev->dev, "registering dma device\n");
+
+	ret = dma_async_device_register(&qdev->common);
+
+	if (ret) {
+		dev_err(&pdev->dev, "Registering Dma device failed\n");
+		goto chan_free;
+	}
+
+	dev_set_drvdata(&pdev->dev, qdev);
+	return 0;
+chan_free:
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		if (qdev->chan[i])
+			msm_dma_chan_remove(qdev->chan[i]);
+	}
+	kfree(qdev);
+	return ret;
+}
+
+static int  __devexit msm_dma_remove(struct platform_device *pdev)
+{
+	struct msm_dma_device *qdev = platform_get_drvdata(pdev);
+	int i;
+
+	dma_async_device_unregister(&qdev->common);
+
+	for (i = SD3_CHAN_START; i < MSM_DMA_MAX_CHANS_PER_DEVICE; i++) {
+		if (qdev->chan[i])
+			msm_dma_chan_remove(qdev->chan[i]);
+	}
+
+	dev_set_drvdata(&pdev->dev, NULL);
+	kfree(qdev);
+
+	return 0;
+}
+
+static struct platform_driver msm_dma_driver = {
+	.remove = __devexit_p(msm_dma_remove),
+	.driver = {
+		.name = "msm_dma",
+		.owner = THIS_MODULE,
+	},
+};
+
+static __init int msm_dma_init(void)
+{
+	return platform_driver_probe(&msm_dma_driver, msm_dma_probe);
+}
+subsys_initcall(msm_dma_init);
+
+static void __exit msm_dma_exit(void)
+{
+	platform_driver_unregister(&msm_dma_driver);
+}
+module_exit(msm_dma_exit);
+
+MODULE_DESCRIPTION("Qualcomm DMA driver");
+MODULE_LICENSE("GPL v2");
-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From svenkatr at ti.com  Thu Mar 22 10:27:16 2012
From: svenkatr at ti.com (S, Venkatraman)
Date: Thu, 22 Mar 2012 19:57:16 +0530
Subject: Occasional crashes in suspend-resume with MMC transactions
In-Reply-To: <B5906170F1614E41A8A28DE3B8D12143317FF773@DBDE01.ent.ti.com>
References: <B5906170F1614E41A8A28DE3B8D12143317FDFBB@DBDE01.ent.ti.com>
 <B5906170F1614E41A8A28DE3B8D12143317FF773@DBDE01.ent.ti.com>
Message-ID: <CANfBPZ9b=6dLbY2D3oAg=Gz_vwAOJ+KC_Bo5ugVJEwumeej_Bw@mail.gmail.com>

On Thu, Mar 22, 2012 at 6:50 PM, Bedia, Vaibhav <vaibhav.bedia at ti.com> wrote:
> On Thu, Mar 22, 2012 at 09:53:23, Bedia, Vaibhav wrote:
>> Hi,
>>
>> I am trying to do suspend-resume test with a file copy on MMC/SD going on
>> in the background. The test involves simply copying a 450MB file on an ext3
>> partition to the same partition under a different name.
>>
>> This is on an AM335x board which uses the omap_hsmmc driver.
>> The kernel is v3.2 and I have also applied the following patch
>>
>
> [...]
>
> I found that whenever this issue crops up, mmc_host_suspend() is not able to claim the host
> And returns -EBUSY. omap_hsmmc driver does not pass on this error code to the PM core and
> hence the suspend process continues. When the driver is made to return -EBUSY, the suspend
> process gets aborted and the user can try suspending again. I am not sure whether this sort
> of suspend failure is acceptable or the driver is doing something wrong. The following
> workaround is what I came up with. Do this look a reasonable thing to do?
>
> ---
>
> From a4040dd1869b351a5fa29dacd08facf6e24df609 Mon Sep 17 00:00:00 2001
> From: Vaibhav Bedia <vaibhav.bedia at ti.com>
> Date: Thu, 22 Mar 2012 17:14:49 +0530
> Subject: [PATCH 1/1] mmc: omap_hsmmc: Pass on the suspend failure to the PM core
>
> In some cases mmc_host_suspend() is not able to claim the
> host and proceed with the suspend process. The core returns
> -EBUSY to the host controller driver. Unfortunately, the
> host controller driver does not pass on this information
> to the PM core and hence the system suspend process continues.
>
> In these cases the MMC core gets to an unexpected state
> during resume and multiple issues related to MMC crop up.
> 1. Host controller driver starts accessing the device registers
> before the clocks are enabled which leads to a prefetch abort.
> 2. A file copy thread which was launched before suspend gets
> stuck due to the host not being reclaimed during resume.
>
> To avoid such problems pass on the -EBUSY status to the PM core
> from the host controller driver. With this change, MMC core
> suspend might still fail but it does not end up making the
> system unusable. Suspend gets aborted and the user can try
> suspending the system again.
>
> Signed-off-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
> ---
> ?drivers/mmc/host/omap_hsmmc.c | ? ?1 +
> ?1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index 3d8dbbb..1f938d9 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -2238,6 +2238,7 @@ static int omap_hsmmc_suspend(struct device *dev)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?dev_dbg(mmc_dev(host->mmc),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"Unmask interrupt failed\n");
> ? ? ? ? ? ? ? ? ? ? ? ?}
> + ? ? ? ? ? ? ? ? ? ? ? ret = -EBUSY;
> ? ? ? ? ? ? ? ? ? ? ? ?goto err;
> ? ? ? ? ? ? ? ?}
>
> --
> 1.7.0.4

I see (in 3.3) that the host controller driver does a "return ret" and
that means the errors is propagated.
Where is the return code lost /overridden ?


From kgene.kim at samsung.com  Thu Mar 22 10:39:06 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 22 Mar 2012 07:39:06 -0700
Subject: [PATCH][RESEND] ARM: SAMSUNG: make SAMSUNG_PM_DEBUG select
 DEBUG_LL
In-Reply-To: <201203202120.45806.heiko@sntech.de>
References: <201203202120.45806.heiko@sntech.de>
Message-ID: <4F6B398A.8040703@samsung.com>

On 03/20/12 13:20, Heiko St?bner wrote:
> From: Maurus Cuelenaere<mcuelenaere at gmail.com>
>
> When selecting SAMSUNG_PM_DEBUG, it complains about a missing printascii()
> function if you do not select DEBUG_LL, so make the former select the latter.
>
> Signed-off-by: Maurus Cuelenaere<mcuelenaere at gmail.com>
> Acked-by: Heiko Stuebner<heiko at sntech.de>
> ---
> This was originally sent in september 2010, but seems to have been forgotten.
> As this problem has bitten me today, here it is again.
>
Yeah, missed. Looks good to me and will apply.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

>   arch/arm/plat-samsung/Kconfig |    1 +
>   1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
> index 6a2abe6..ec84c1a 100644
> --- a/arch/arm/plat-samsung/Kconfig
> +++ b/arch/arm/plat-samsung/Kconfig
> @@ -302,6 +302,7 @@ comment "Power management"
>   config SAMSUNG_PM_DEBUG
>   	bool "S3C2410 PM Suspend debug"
>   	depends on PM
> +	select DEBUG_LL
>   	help
>   	  Say Y here if you want verbose debugging from the PM Suspend and
>   	  Resume code. See<file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>


From vaibhav.bedia at ti.com  Thu Mar 22 10:43:16 2012
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Thu, 22 Mar 2012 14:43:16 +0000
Subject: Occasional crashes in suspend-resume with MMC transactions
In-Reply-To: <CANfBPZ9b=6dLbY2D3oAg=Gz_vwAOJ+KC_Bo5ugVJEwumeej_Bw@mail.gmail.com>
References: <B5906170F1614E41A8A28DE3B8D12143317FDFBB@DBDE01.ent.ti.com>
 <B5906170F1614E41A8A28DE3B8D12143317FF773@DBDE01.ent.ti.com>
 <CANfBPZ9b=6dLbY2D3oAg=Gz_vwAOJ+KC_Bo5ugVJEwumeej_Bw@mail.gmail.com>
Message-ID: <B5906170F1614E41A8A28DE3B8D12143317FFAC0@DBDE01.ent.ti.com>

On Thu, Mar 22, 2012 at 19:57:16, S, Venkatraman wrote:
[...]
> 
> I see (in 3.3) that the host controller driver does a "return ret" and
> that means the errors is propagated.
> Where is the return code lost /overridden ?
> 

The return code gets overridden due to the call to host->pdata->resume()
which always returns 0.

static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
{
        struct omap_mmc_platform_data *mmc = dev->platform_data;

        enable_irq(mmc->slots[0].card_detect_irq);
        return 0;
}

Regards,
Vaibhav


From nicolas.ferre at atmel.com  Thu Mar 22 10:44:51 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 22 Mar 2012 15:44:51 +0100
Subject: [PATCH 2/3] mmc: atmel-mci: r/w proof capability only available
 since v2xx
In-Reply-To: <1332344483-3915-3-git-send-email-ludovic.desroches@atmel.com>
References: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
 <1332344483-3915-3-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <4F6B3AE3.6080901@atmel.com>

On 03/21/2012 04:41 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> ---
>  drivers/mmc/host/atmel-mci.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> index e161452..9dcb236 100644
> --- a/drivers/mmc/host/atmel-mci.c
> +++ b/drivers/mmc/host/atmel-mci.c
> @@ -2009,6 +2009,8 @@ static void __init atmci_get_cap(struct atmel_mci *host)
>  	/* keep only major version number */
>  	switch (version & 0xf00) {
>  	case 0x100:
> +		host->caps.has_pdc = 1;
> +		break;
>  	case 0x200:
>  		host->caps.has_pdc = 1;
>  		host->caps.has_rwproof = 1;


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Thu Mar 22 10:48:48 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 22 Mar 2012 15:48:48 +0100
Subject: [PATCH 3/3] mmc: atmel-mci: add support for odd clock dividers
In-Reply-To: <1332344483-3915-4-git-send-email-ludovic.desroches@atmel.com>
References: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
 <1332344483-3915-4-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <4F6B3BD0.4060702@atmel.com>

On 03/21/2012 04:41 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Add an odd clock divider capability available from v5xx. It also involves
> changing the clock divider calculation.

Also tell here that you have changed the way that the switch/case
directive has been implemented.

> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Otherwise:
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>


> ---
>  drivers/mmc/host/atmel-mci-regs.h |    1 +
>  drivers/mmc/host/atmel-mci.c      |   48 ++++++++++++++++++++++--------------
>  2 files changed, 30 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
> index 000b3ad..787aba1 100644
> --- a/drivers/mmc/host/atmel-mci-regs.h
> +++ b/drivers/mmc/host/atmel-mci-regs.h
> @@ -31,6 +31,7 @@
>  # define ATMCI_MR_PDCFBYTE		(  1 << 13)	/* Force Byte Transfer */
>  # define ATMCI_MR_PDCPADV		(  1 << 14)	/* Padding Value */
>  # define ATMCI_MR_PDCMODE		(  1 << 15)	/* PDC-oriented Mode */
> +# define ATMCI_MR_CLKODD(x)		((x) << 16)	/* LSB of Clock Divider */
>  #define ATMCI_DTOR			0x0008	/* Data Timeout */
>  # define ATMCI_DTOCYC(x)		((x) <<  0)	/* Data Timeout Cycles */
>  # define ATMCI_DTOMUL(x)		((x) <<  4)	/* Data Timeout Multiplier */
> diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> index 9dcb236..75e28c0 100644
> --- a/drivers/mmc/host/atmel-mci.c
> +++ b/drivers/mmc/host/atmel-mci.c
> @@ -76,6 +76,7 @@ struct atmel_mci_caps {
>  	bool    has_cstor_reg;
>  	bool    has_highspeed;
>  	bool    has_rwproof;
> +	bool	has_odd_clk_div;
>  };
>  
>  struct atmel_mci_dma {
> @@ -1124,16 +1125,27 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>  		}
>  
>  		/* Calculate clock divider */
> -		clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
> -		if (clkdiv > 255) {
> -			dev_warn(&mmc->class_dev,
> -				"clock %u too slow; using %lu\n",
> -				clock_min, host->bus_hz / (2 * 256));
> -			clkdiv = 255;
> +		if (host->caps.has_odd_clk_div) {
> +			clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
> +			if (clkdiv > 511) {
> +				dev_warn(&mmc->class_dev,
> +				         "clock %u too slow; using %lu\n",
> +				         clock_min, host->bus_hz / (511 + 2));
> +				clkdiv = 511;
> +			}
> +			host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
> +			                 | ATMCI_MR_CLKODD(clkdiv & 1);
> +		} else {
> +			clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
> +			if (clkdiv > 255) {
> +				dev_warn(&mmc->class_dev,
> +				         "clock %u too slow; using %lu\n",
> +				         clock_min, host->bus_hz / (2 * 256));
> +				clkdiv = 255;
> +			}
> +			host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
>  		}
>  
> -		host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
> -
>  		/*
>  		 * WRPROOF and RDPROOF prevent overruns/underruns by
>  		 * stopping the clock when the FIFO is full/empty.
> @@ -2000,37 +2012,35 @@ static void __init atmci_get_cap(struct atmel_mci *host)
>  			"version: 0x%x\n", version);
>  
>  	host->caps.has_dma = 0;
> -	host->caps.has_pdc = 0;
> +	host->caps.has_pdc = 1;
>  	host->caps.has_cfg_reg = 0;
>  	host->caps.has_cstor_reg = 0;
>  	host->caps.has_highspeed = 0;
>  	host->caps.has_rwproof = 0;
> +	host->caps.has_odd_clk_div = 0;
>  
>  	/* keep only major version number */
>  	switch (version & 0xf00) {
> -	case 0x100:
> -		host->caps.has_pdc = 1;
> -		break;
> -	case 0x200:
> -		host->caps.has_pdc = 1;
> -		host->caps.has_rwproof = 1;
> -		break;
> -	case 0x300:
> -	case 0x400:
>  	case 0x500:
> +		host->caps.has_odd_clk_div = 1;
> +	case 0x400:
> +	case 0x300:
>  #ifdef CONFIG_AT_HDMAC
>  		host->caps.has_dma = 1;
>  #else
> -		host->caps.has_dma = 0;
>  		dev_info(&host->pdev->dev,
>  			"has dma capability but dma engine is not selected, then use pio\n");
>  #endif
> +		host->caps.has_pdc = 0;
>  		host->caps.has_cfg_reg = 1;
>  		host->caps.has_cstor_reg = 1;
>  		host->caps.has_highspeed = 1;
> +	case 0x200:
>  		host->caps.has_rwproof = 1;
> +	case 0x100:
>  		break;
>  	default:
> +		host->caps.has_pdc = 0;
>  		dev_warn(&host->pdev->dev,
>  				"Unmanaged mci version, set minimum capabilities\n");
>  		break;


-- 
Nicolas Ferre


From gururaja.hebbar at ti.com  Thu Mar 22 10:49:51 2012
From: gururaja.hebbar at ti.com (Hebbar, Gururaja)
Date: Thu, 22 Mar 2012 14:49:51 +0000
Subject: Occasional crashes in suspend-resume with MMC transactions
In-Reply-To: <CANfBPZ9b=6dLbY2D3oAg=Gz_vwAOJ+KC_Bo5ugVJEwumeej_Bw@mail.gmail.com>
References: <B5906170F1614E41A8A28DE3B8D12143317FDFBB@DBDE01.ent.ti.com>
 <B5906170F1614E41A8A28DE3B8D12143317FF773@DBDE01.ent.ti.com>
 <CANfBPZ9b=6dLbY2D3oAg=Gz_vwAOJ+KC_Bo5ugVJEwumeej_Bw@mail.gmail.com>
Message-ID: <1BAFE6F6C881BF42822005164F1491C3317FA311@DBDE01.ent.ti.com>

On Thu, Mar 22, 2012 at 19:57:16, S, Venkatraman wrote:
> On Thu, Mar 22, 2012 at 6:50 PM, Bedia, Vaibhav <vaibhav.bedia at ti.com> wrote:
> > On Thu, Mar 22, 2012 at 09:53:23, Bedia, Vaibhav wrote:
> >> Hi,
> >>
> >> I am trying to do suspend-resume test with a file copy on MMC/SD going on
> >> in the background. The test involves simply copying a 450MB file on an ext3
> >> partition to the same partition under a different name.
> >>
> >> This is on an AM335x board which uses the omap_hsmmc driver.
> >> The kernel is v3.2 and I have also applied the following patch
> >>
> >
> > [...]
> >
> > I found that whenever this issue crops up, mmc_host_suspend() is not able to claim the host
> > And returns -EBUSY. omap_hsmmc driver does not pass on this error code to the PM core and
> > hence the suspend process continues. When the driver is made to return -EBUSY, the suspend
> > process gets aborted and the user can try suspending again. I am not sure whether this sort
> > of suspend failure is acceptable or the driver is doing something wrong. The following
> > workaround is what I came up with. Do this look a reasonable thing to do?
> >
> > ---
> >
> > From a4040dd1869b351a5fa29dacd08facf6e24df609 Mon Sep 17 00:00:00 2001
> > From: Vaibhav Bedia <vaibhav.bedia at ti.com>
> > Date: Thu, 22 Mar 2012 17:14:49 +0530
> > Subject: [PATCH 1/1] mmc: omap_hsmmc: Pass on the suspend failure to the PM core
> >
> > In some cases mmc_host_suspend() is not able to claim the
> > host and proceed with the suspend process. The core returns
> > -EBUSY to the host controller driver. Unfortunately, the
> > host controller driver does not pass on this information
> > to the PM core and hence the system suspend process continues.
> >
> > In these cases the MMC core gets to an unexpected state
> > during resume and multiple issues related to MMC crop up.
> > 1. Host controller driver starts accessing the device registers
> > before the clocks are enabled which leads to a prefetch abort.
> > 2. A file copy thread which was launched before suspend gets
> > stuck due to the host not being reclaimed during resume.
> >
> > To avoid such problems pass on the -EBUSY status to the PM core
> > from the host controller driver. With this change, MMC core
> > suspend might still fail but it does not end up making the
> > system unusable. Suspend gets aborted and the user can try
> > suspending the system again.
> >
> > Signed-off-by: Vaibhav Bedia <vaibhav.bedia at ti.com>
> > ---
> > ?drivers/mmc/host/omap_hsmmc.c | ? ?1 +
> > ?1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> > index 3d8dbbb..1f938d9 100644
> > --- a/drivers/mmc/host/omap_hsmmc.c
> > +++ b/drivers/mmc/host/omap_hsmmc.c
> > @@ -2238,6 +2238,7 @@ static int omap_hsmmc_suspend(struct device *dev)
> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?dev_dbg(mmc_dev(host->mmc),
> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"Unmask interrupt failed\n");
> > ? ? ? ? ? ? ? ? ? ? ? ?}
> > + ? ? ? ? ? ? ? ? ? ? ? ret = -EBUSY;
> > ? ? ? ? ? ? ? ? ? ? ? ?goto err;
> > ? ? ? ? ? ? ? ?}
> >
> > --
> > 1.7.0.4
> 
> I see (in 3.3) that the host controller driver does a "return ret" and
> that means the errors is propagated.
> Where is the return code lost /overridden ?

As seen from http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=drivers/mmc/host/omap_hsmmc.c;h=fd0c661bbad38a7152a37955146ff6068d4d7137;hb=refs/tags/v3.3

omap_hsmmc.c 

@ 2045

pdata->resume = omap_hsmmc_resume_cdirq;


@227

static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
{
        struct omap_mmc_platform_data *mmc = dev->platform_data;

        enable_irq(mmc->slots[0].card_detect_irq);
        return 0;							-----> always return 0
}

@2167

                        if (host->pdata->resume) {
                                ret = host->pdata->resume(&pdev->dev,		--> ret becomes zero irrespective of its previous value.
                                                          host->slot_id);
                                if (ret)
                                        dev_dbg(mmc_dev(host->mmc),
                                                "Unmask interrupt failed\n");
                        }


> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


Regards, 
Gururaja


From nicolas.ferre at atmel.com  Thu Mar 22 10:50:48 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 22 Mar 2012 15:50:48 +0100
Subject: [PATCH 1/4] mmc: atmel-mci: add device tree support
In-Reply-To: <1332352994-20983-2-git-send-email-ludovic.desroches@atmel.com>
References: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
 <1332352994-20983-2-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <4F6B3C48.90002@atmel.com>

On 03/21/2012 07:03 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> ---
>  .../devicetree/bindings/mmc/atmel-hsmci.txt        |   55 +++++++++++++++
>  drivers/mmc/host/atmel-mci.c                       |   74 +++++++++++++++++++-
>  2 files changed, 126 insertions(+), 3 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
> 
> diff --git a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
> new file mode 100644
> index 0000000..657f9de
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
> @@ -0,0 +1,55 @@
> +* Atmel High Speed MultiMedia Card Interface
> +
> +This controller on atmel products provides an interface for MMC, SD and SDIO
> +types of memory cards.
> +
> +1) MCI node
> +
> +Required properties:
> +- compatible: no blank "atmel,hsmci"
> +- reg: should contain HSMCI registers location and length
> +- interrupts: should contain HSMCI interrupt number
> +- at least one slot node
> +
> +The node contains child nodes for each slot that the platform uses
> +
> +Example MCI node:
> +
> +mmc0: mmc at f0008000 {
> +	compatible = "atmel,hsmci";
> +	reg = <0xf0008000 0x600>;
> +	interrupts = <12 4>;
> +
> +	[ child node definitions...]
> +};
> +
> +2) slot nodes
> +
> +Optional properties:
> +- bus-width: number of data lines connected to the controller
> +- cd-gpios: specify GPIOs for card detection
> +- cd-invert: invert the value of external card detect gpio line
> +- wp-gpios: specify GPIOs for write protection
> +
> +Example slot node:
> +
> +slot at 0 {
> +	bus-width = <4>;
> +	cd-gpios = <&pioD 15 0>
> +	cd-invert;
> +};
> +
> +Example full MCI node:
> +mmc0: mmc at f0008000 {
> +	compatible = "atmel,hsmci";
> +	reg = <0xf0008000 0x600>;
> +	interrupts = <12 4>;
> +	slot at 0 {
> +		bus-width = <4>;
> +		cd-gpios = <&pioD 15 0>
> +		cd-invert;
> +	};
> +	slot at 1 {
> +		bus-width = <4>;
> +	};
> +};
> diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> index b5693fd..2d6a04a 100644
> --- a/drivers/mmc/host/atmel-mci.c
> +++ b/drivers/mmc/host/atmel-mci.c
> @@ -19,6 +19,9 @@
>  #include <linux/interrupt.h>
>  #include <linux/ioport.h>
>  #include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
>  #include <linux/platform_device.h>
>  #include <linux/scatterlist.h>
>  #include <linux/seq_file.h>
> @@ -477,6 +480,54 @@ err:
>  	dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
>  }
>  
> +#if defined(CONFIG_OF)
> +static const struct of_device_id atmci_dt_ids[] = {
> +	{ .compatible = "atmel,hsmci" },
> +	{ /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, atmci_dt_ids);
> +
> +static void __init
> +atmci_get_of_slots(struct device *dev, struct mci_platform_data *pdata)
> +{
> +	struct device_node *np = dev->of_node;
> +	struct device_node *cnp;
> +	unsigned int slot_nb = 0;
> +
> +	if (!np)
> +		return;
> +
> +	for_each_child_of_node(np, cnp) {
> +		if (slot_nb > (ATMCI_MAX_NR_SLOTS-1)) {
> +			dev_warn(dev, "can't have more than %d slots\n",
> +			         ATMCI_MAX_NR_SLOTS);
> +			break;
> +		}
> +		if (of_property_read_u32(cnp, "bus-width",
> +		                         &pdata->slot[slot_nb].bus_width))
> +			pdata->slot[slot_nb].bus_width = 1;
> +
> +		pdata->slot[slot_nb].detect_pin =
> +			of_get_named_gpio(cnp, "cd-gpios", 0);
> +
> +		if (of_find_property(cnp, "cd-invert", NULL))
> +			pdata->slot[slot_nb].detect_is_active_high = true;
> +
> +		pdata->slot[slot_nb].wp_pin =
> +			of_get_named_gpio(cnp, "wp-gpios", 0);
> +
> +		slot_nb++;
> +	}
> +}
> +#else /* CONFIG_OF */
> +static inline void
> +atmci_get_of_slots(struct device *dev, struct mci_platform_data *pdata)
> +{
> +	return;
> +}
> +#endif
> +
>  static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
>  					unsigned int ns)
>  {
> @@ -1847,6 +1898,13 @@ static int __init atmci_init_slot(struct atmel_mci *host,
>  	slot->sdc_reg = sdc_reg;
>  	slot->sdio_irq = sdio_irq;
>  
> +	dev_dbg(&mmc->class_dev,
> +	        "slot[%u]: bus_width=%u, detect_pin=%d, "
> +		"detect_is_active_high=%s, wp_pin=%d\n",
> +		id, slot_data->bus_width, slot_data->detect_pin,
> +		slot_data->detect_is_active_high ? "true" : "false",
> +		slot_data->wp_pin);
> +
>  	mmc->ops = &atmci_ops;
>  	mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
>  	mmc->f_max = host->bus_hz / 2;
> @@ -2047,9 +2105,17 @@ static int __init atmci_probe(struct platform_device *pdev)
>  	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	if (!regs)
>  		return -ENXIO;
> -	pdata = pdev->dev.platform_data;
> -	if (!pdata)
> -		return -ENXIO;
> +
> +	if (pdev->dev.of_node) {
> +		pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> +		if (!pdata)
> +			return -ENOMEM;
> +	} else {
> +		pdata = pdev->dev.platform_data;
> +		if (!pdata)
> +			return -ENXIO;
> +	}
> +
>  	irq = platform_get_irq(pdev, 0);
>  	if (irq < 0)
>  		return irq;
> @@ -2109,6 +2175,7 @@ static int __init atmci_probe(struct platform_device *pdev)
>  	/* We need at least one slot to succeed */
>  	nr_slots = 0;
>  	ret = -ENODEV;
> +	atmci_get_of_slots(&pdev->dev, pdata);
>  	if (pdata->slot[0].bus_width) {
>  		ret = atmci_init_slot(host, &pdata->slot[0],
>  				0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
> @@ -2242,6 +2309,7 @@ static struct platform_driver atmci_driver = {
>  	.driver		= {
>  		.name		= "atmel_mci",
>  		.pm		= ATMCI_PM_OPS,
> +		.of_match_table	= of_match_ptr(atmci_dt_ids),
>  	},
>  };
>  


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Thu Mar 22 10:51:42 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 22 Mar 2012 15:51:42 +0100
Subject: [PATCH 2/4] arm: at91: at91sam9x5 add mci clk_lookup
In-Reply-To: <1332352994-20983-3-git-send-email-ludovic.desroches@atmel.com>
References: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
 <1332352994-20983-3-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <4F6B3C7E.5050305@atmel.com>

On 03/21/2012 07:03 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> ---
>  arch/arm/mach-at91/at91sam9x5.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
> index 13c8cae..39cbef3 100644
> --- a/arch/arm/mach-at91/at91sam9x5.c
> +++ b/arch/arm/mach-at91/at91sam9x5.c
> @@ -225,6 +225,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
>  	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
>  	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
>  	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
> +	CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
> +	CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
>  	CLKDEV_CON_ID("pioA", &pioAB_clk),
>  	CLKDEV_CON_ID("pioB", &pioAB_clk),
>  	CLKDEV_CON_ID("pioC", &pioCD_clk),


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Thu Mar 22 10:52:13 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 22 Mar 2012 15:52:13 +0100
Subject: [PATCH 3/4] arm: at91: dt: sam9x5 add mci support
In-Reply-To: <1332352994-20983-4-git-send-email-ludovic.desroches@atmel.com>
References: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
 <1332352994-20983-4-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <4F6B3C9D.60300@atmel.com>

On 03/21/2012 07:03 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> ---
>  arch/arm/boot/dts/at91sam9x5.dtsi |   14 ++++++++++++++
>  1 files changed, 14 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> index c111001..5846f99 100644
> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> @@ -191,6 +191,20 @@
>  				interrupts = <27 4>;
>  				status = "disabled";
>  			};
> +
> +			mmc0: mmc at f0008000 {
> +				compatible = "atmel,hsmci";
> +				reg = <0xf0008000 0x600>;
> +				interrupts = <12 4>;
> +				status = "disabled";
> +			};
> +
> +			mmc1: mmc at f000c000 {
> +				compatible = "atmel,hsmci";
> +				reg = <0xf000c000 0x600>;
> +				interrupts = <26 4>;
> +				status = "disabled";
> +			};
>  		};
>  
>  		nand0: nand at 40000000 {


-- 
Nicolas Ferre


From nicolas.ferre at atmel.com  Thu Mar 22 10:53:01 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 22 Mar 2012 15:53:01 +0100
Subject: [PATCH 4/4] arm: at91: dt: sam9g25ek add mci support
In-Reply-To: <1332352994-20983-5-git-send-email-ludovic.desroches@atmel.com>
References: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
 <1332352994-20983-5-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <4F6B3CCD.7070105@atmel.com>

On 03/21/2012 07:03 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> ---
>  arch/arm/boot/dts/at91sam9g25ek.dts |   16 ++++++++++++++++
>  1 files changed, 16 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
> index 7a13d09..960de2b 100644
> --- a/arch/arm/boot/dts/at91sam9g25ek.dts
> +++ b/arch/arm/boot/dts/at91sam9g25ek.dts
> @@ -32,6 +32,22 @@
>  				phy-mode = "rmii";
>  				status = "okay";
>  			};
> +
> +			mmc0: mmc at f0008000 {
> +				status = "okay";
> +				slot at 0 {
> +					bus-width = <4>;
> +					cd-gpios = <&pioD 15 0>;
> +				};
> +			};
> +
> +			mmc1: mmc at f000c000 {
> +				status = "okay";
> +				slot at 0 {
> +					bus-width = <4>;
> +					cd-gpios = <&pioD 14 0>;
> +				};
> +			};
>  		};
>  
>  		usb0: ohci at 00600000 {


-- 
Nicolas Ferre


From tsoni at codeaurora.org  Thu Mar 22 11:11:14 2012
From: tsoni at codeaurora.org (Trilok Soni)
Date: Thu, 22 Mar 2012 20:41:14 +0530
Subject: [PATCH v4 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 ADM DMA APIs
In-Reply-To: <4F6B11DC.9090401@metafoo.de>
References: <1332413882-8456-1-git-send-email-kumarrav@codeaurora.org>
 <4F6B11DC.9090401@metafoo.de>
Message-ID: <4F6B4112.7060404@codeaurora.org>

Hi Peter,

On 3/22/2012 5:19 PM, Lars-Peter Clausen wrote:
>
> Same comment as before. This is supposed to return either a valid descriptor
> or NULL, but not an ERR_PTR.

Ravi has just posted v5 addressing your comments. Please check.

---Trilok Soni
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From shawn.guo at linaro.org  Thu Mar 22 11:11:59 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 22 Mar 2012 23:11:59 +0800
Subject: [PATCH] rtc: add support for Freescale SNVS RTC
In-Reply-To: <1332162269-16789-1-git-send-email-paul.liu@linaro.org>
References: <1332162269-16789-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120322151156.GF2213@S2101-09.ap.freescale.net>

On Mon, Mar 19, 2012 at 09:04:29PM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> This adds an RTC driver for the Low Power (LP) section of SNVS.
> It hooks into the /dev/rtc interface and supports ioctl to complete RTC
> features. This driver supports device tree bindings.

Then, you need to have a document in Documentation/devicetree/bindings.

> It only uses the RTC hw in non-secure mode.
> 
> Signed-off-by: Anish Trivedi <anish at freescale.com>
> Signed-off-by: Eric Miao <eric.miao at linaro.org>
> Signed-off-by: Anson Huang <b20788 at freescale.com>
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Cc: Alessandro Zummo <a.zummo at towertech.it>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> ---
>  drivers/rtc/Kconfig    |   11 +
>  drivers/rtc/Makefile   |    1 +
>  drivers/rtc/rtc-snvs.c |  737 ++++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 749 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/rtc/rtc-snvs.c
> 
> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
> index 3a125b8..d58f4b7 100644
> --- a/drivers/rtc/Kconfig
> +++ b/drivers/rtc/Kconfig
> @@ -634,6 +634,17 @@ config RTC_MXC
>  	   This driver can also be built as a module, if so, the module
>  	   will be called "rtc-mxc".
>  
> +config RTC_DRV_SNVS
> +	tristate "Freescale SNVS Real Time Clock"
> +	depends on ARCH_MXC
> +	depends on RTC_CLASS

I'm not sure this is really necessary, since this config is included
in "if RTC_CLASS".

> +	help
> +	   If you say yes here you get support for the Freescale SNVS
> +	   Low Power (LP) RTC module.
> +
> +	   This driver can also be built as a module, if so, the module
> +	   will be called "rtc-snvs".
> +
>  config RTC_DRV_BQ4802
>  	tristate "TI BQ4802"
>  	help
> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
> index 6e69823..8b30686 100644
> --- a/drivers/rtc/Makefile
> +++ b/drivers/rtc/Makefile
> @@ -93,6 +93,7 @@ obj-$(CONFIG_RTC_DRV_S35390A)	+= rtc-s35390a.o
>  obj-$(CONFIG_RTC_DRV_S3C)	+= rtc-s3c.o
>  obj-$(CONFIG_RTC_DRV_SA1100)	+= rtc-sa1100.o
>  obj-$(CONFIG_RTC_DRV_SH)	+= rtc-sh.o
> +obj-$(CONFIG_RTC_DRV_SNVS)	+= rtc-snvs.o
>  obj-$(CONFIG_RTC_DRV_SPEAR)	+= rtc-spear.o
>  obj-$(CONFIG_RTC_DRV_STARFIRE)	+= rtc-starfire.o
>  obj-$(CONFIG_RTC_DRV_STK17TA8)	+= rtc-stk17ta8.o
> diff --git a/drivers/rtc/rtc-snvs.c b/drivers/rtc/rtc-snvs.c
> new file mode 100644
> index 0000000..49ac8a5
> --- /dev/null
> +++ b/drivers/rtc/rtc-snvs.c
> @@ -0,0 +1,737 @@
> +/*
> + * Copyright (C) 2011 Freescale Semiconductor, Inc.
> + */
> +
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + */
> +/*
> + * Implementation based on rtc-ds1553.c
> + */
> +
> +/*!

I'm not sure "/*!" is the format for kernel-doc.  Please take a look
at Documentation/kernel-doc-nano-HOWTO.txt.

> + * @defgroup RTC Real Time Clock (RTC) Driver
> + */
> +/*!
> + * @file rtc-snvs.c
> + * @brief Secure Real Time Clock (SRTC) interface in Freescale's SNVS module
> + *
> + * This file contains Real Time Clock interface for Linux. The Freescale
> + * SNVS module's Low Power (LP) SRTC functionality is utilized in this driver,
> + * in non-secure mode.
> + *
> + * @ingroup RTC
> + */
> +
I feel above several sections of documents can just be in one multiple
line comment section.

> +#include <linux/slab.h>
> +#include <linux/delay.h>
> +#include <linux/rtc.h>
> +#include <linux/module.h>
> +#include <linux/fs.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/uaccess.h>
> +#include <linux/io.h>
> +#include <linux/sched.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +
> +/* Register definitions */
> +#define	SNVS_HPSR	0x14	/* HP Status Register */

Normally, we have one space rather than tab after "#define".

> +#define	SNVS_LPCR	0x38	/* LP Control Register */
> +#define	SNVS_LPSR	0x4C	/* LP Status Register */
> +#define	SNVS_LPSRTCMR	0x50	/* LP Secure Real Time Counter MSB Register */
> +#define	SNVS_LPSRTCLR	0x54	/* LP Secure Real Time Counter LSB Register */
> +#define	SNVS_LPTAR	0x58	/* LP Time Alarm Register */
> +#define	SNVS_LPSMCMR	0x5C	/* LP Secure Monotonic Counter MSB Register */
> +#define	SNVS_LPSMCLR	0x60	/* LP Secure Monotonic Counter LSB Register */
> +#define	SNVS_LPPGDR	0x64	/* LP Power Glitch Detector Register */
> +#define	SNVS_LPGPR	0x68	/* LP General Purpose Register */
> +
> +/* Bit Definitions */
> +#define	SNVS_HPSR_SSM_ST_MASK	0x00000F00
> +#define	SNVS_HPSR_SSM_ST_SHIFT	8
> +
> +#define	SNVS_LPCR_SRTC_ENV	(1 << 0)
> +#define	SNVS_LPCR_LPTA_EN	(1 << 1)
> +#define	SNVS_LPCR_LPWUI_EN	(1 << 3)
> +#define	SNVS_LPCR_ALL_INT_EN (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN)

Align the indentation?

> +#define	SNVS_LPSR_LPTA		(1 << 0)
> +#define	SNVS_LPPGDR_INIT	0x41736166
> +
> +/* Other defines */
> +#define	SSM_ST_CHECK	0x9
> +#define	SSM_ST_NON_SECURE	0xB
> +#define	CNTR_TO_SECS_SH 15	/* Converts 47-bit counter to 32-bit seconds */

Ditto

> +
> +#define RTC_READ_TIME_47BIT	_IOR('p', 0x20, unsigned long long)
> +/* blocks until LPSCMR is set, returns difference */
> +#define RTC_WAIT_TIME_SET	_IOR('p', 0x21, int64_t)
> +

What are these local ioctl number exactly for?  How can user space
use these driver private numbers?

> +struct rtc_drv_data {
> +	struct rtc_device *rtc;
> +	void __iomem *ioaddr;
> +	int irq;
> +	bool irq_enable;
> +};
> +
> +static unsigned long rtc_status;
> +
> +static DEFINE_SPINLOCK(rtc_lock);
> +DECLARE_COMPLETION(snvs_completion);
> +static int64_t time_diff;
> +
> +/*!
> + * LP counter register reads should always use this function.
> + * This function reads 2 consective times from LP counter register
> + * until the 2 values match. This is to avoid reading corrupt
> + * value if the counter is in the middle of updating
> + */

If you write kernel doc for functions, please follow the format
documented in Dcumentation/kernel-doc-nano-HOWTO.txt

> +static inline u32 rtc_read_lp_counter(void __iomem *counter_reg)
> +{
> +	u64 read1, read2;
> +	u32 counter_sec;
> +
> +	do {
> +		/* MSB */
> +		read1 = readl(counter_reg);
> +		read1 <<= 32;
> +		/* LSB */
> +		read1 |= readl(counter_reg + 4);
> +
> +		/* MSB */
> +		read2 = readl(counter_reg);
> +		read2 <<= 32;
> +		/* LSB */
> +		read2 |= readl(counter_reg + 4);
> +	} while (read1 != read2);
> +
> +	/* Convert 47-bit counter to 32-bit raw second count */
> +	counter_sec = (u32) (read1 >> CNTR_TO_SECS_SH);
> +
> +	return counter_sec;
> +}
> +
It seems the function is only used to read register SNVS_LPSRTCMR, just
like that the function below is only writing register SNVS_LPSRTCLR.
Why they are using different semantics.  The above function takes
register address as argument while the following one takes snvs base
address?

> +/*!
> + * This function does write synchronization for writes to the lp srtc block.
> + * To take care of the asynchronous CKIL clock, all writes from the IP domain
> + * will be synchronized to the CKIL domain.
> + */
> +static inline void rtc_write_sync_lp(void __iomem *ioaddr)
> +{
> +	unsigned int i, count1, count2, count3;
> +
> +	/* Wait for 3 CKIL cycles */
> +	for (i = 0; i < 3; i++) {

Each loop consumes 1 CKIL cycle?

> +
> +		/* Do consective reads of LSB of counter to ensure integrity */
> +		do {
> +			count1 = readl(ioaddr + SNVS_LPSRTCLR);
> +			count2 = readl(ioaddr + SNVS_LPSRTCLR);
> +		} while (count1 != count2);
> +
> +		/* Now wait until counter value changes */
> +		do {
> +			do {
> +				count2 = readl(ioaddr + SNVS_LPSRTCLR);
> +				count3 = readl(ioaddr + SNVS_LPSRTCLR);
> +			} while (count2 != count3);
> +		} while (count3 == count1);
> +	}
> +}
> +
> +/*!
> + * This function updates the RTC alarm registers and then clears all the
> + * interrupt status bits.
> + *
> + * @param  alrm         the new alarm value to be updated in the RTC
> + *
> + * @return  0 if successful; non-zero otherwise.
> + */
> +static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
> +{
> +	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
> +	void __iomem *ioaddr = pdata->ioaddr;
> +	struct rtc_time alarm_tm, now_tm;
> +	unsigned long now, time, lp_cr;
> +	int ret;
> +
> +	now = rtc_read_lp_counter(ioaddr + SNVS_LPSRTCMR);
> +	rtc_time_to_tm(now, &now_tm);
> +
> +	alarm_tm.tm_year = now_tm.tm_year;
> +	alarm_tm.tm_mon = now_tm.tm_mon;
> +	alarm_tm.tm_mday = now_tm.tm_mday;
> +
> +	alarm_tm.tm_hour = alrm->tm_hour;
> +	alarm_tm.tm_min = alrm->tm_min;
> +	alarm_tm.tm_sec = alrm->tm_sec;
> +
> +	rtc_tm_to_time(&now_tm, &now);
> +	rtc_tm_to_time(&alarm_tm, &time);
> +
> +	if (time < now) {
> +		time += 60 * 60 * 24;
> +		rtc_time_to_tm(time, &alarm_tm);
> +	}
> +	ret = rtc_tm_to_time(&alarm_tm, &time);
> +
> +	/* Have to clear LPTA_EN before programming new alarm time in LPTAR */
> +	lp_cr = readl(ioaddr + SNVS_LPCR);
> +	writel(lp_cr & ~SNVS_LPCR_LPTA_EN, ioaddr + SNVS_LPCR);
> +	rtc_write_sync_lp(ioaddr);
> +
> +	writel(time, ioaddr + SNVS_LPTAR);
> +
> +	/* clear alarm interrupt status bit */
> +	writel(SNVS_LPSR_LPTA, ioaddr + SNVS_LPSR);
> +
> +	return ret;
> +}
> +
> +/*!
> + * This function is the RTC interrupt service routine.
> + *
> + * @param  irq          RTC IRQ number
> + * @param  dev_id       device ID which is not used
> + *
> + * @return IRQ_HANDLED as defined in the include/linux/interrupt.h file.
> + */
> +static irqreturn_t snvs_rtc_interrupt(int irq, void *dev_id)
> +{
> +	struct platform_device *pdev = dev_id;
> +	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
> +	void __iomem *ioaddr = pdata->ioaddr;
> +	u32 lp_status, lp_cr;
> +	u32 events = 0;
> +
> +	lp_status = readl(ioaddr + SNVS_LPSR);
> +	lp_cr = readl(ioaddr + SNVS_LPCR);
> +
> +	/* update irq data & counter */
> +	if (lp_status & SNVS_LPSR_LPTA) {
> +		if (lp_cr & SNVS_LPCR_LPTA_EN)
> +			events |= (RTC_AF | RTC_IRQF);
> +
> +		/* disable further lp alarm interrupts */
> +		lp_cr &= ~(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
> +	}
> +
> +	/* Update interrupt enables */
> +	writel(lp_cr, ioaddr + SNVS_LPCR);
> +
> +	/* If no interrupts are enabled, turn off interrupts in kernel */
> +	if (((lp_cr & SNVS_LPCR_ALL_INT_EN) == 0) && (pdata->irq_enable)) {
> +		disable_irq_nosync(pdata->irq);
> +		pdata->irq_enable = false;
> +	}
> +
> +	/* clear interrupt status */
> +	writel(lp_status, ioaddr + SNVS_LPSR);
> +
> +	rtc_write_sync_lp(ioaddr);
> +	rtc_update_irq(pdata->rtc, 1, events);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +/*!
> + * This function is used to open the RTC driver.
> + *
> + * @return  0 if successful; non-zero otherwise.
> + */
> +static int snvs_rtc_open(struct device *dev)
> +{
> +	if (test_and_set_bit(1, &rtc_status))
> +		return -EBUSY;
> +
> +	return 0;
> +}
> +
> +/*!
> + * clear all interrupts and release the IRQ
> + */
> +static void snvs_rtc_release(struct device *dev)
> +{
> +	rtc_status = 0;
> +}
> +

This couple of hooks seem completely unnecessary to me, since they do
nothing but just checking reentry, which has been done by rtc core.

> +/*!
> + * This function reads the current RTC time into tm in Gregorian date.
> + *
> + * @param  tm           contains the RTC time value upon return
> + *
> + * @return  0 if successful; non-zero otherwise.
> + */
> +static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
> +{
> +	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
> +	void __iomem *ioaddr = pdata->ioaddr;
> +
> +	rtc_time_to_tm(rtc_read_lp_counter(ioaddr + SNVS_LPSRTCMR), tm);
> +
> +	return 0;
> +}
> +
> +/*!
> + * This function sets the internal RTC time based on tm in Gregorian date.
> + *
> + * @param  tm           the time value to be set in the RTC
> + *
> + * @return  0 if successful; non-zero otherwise.
> + */
> +static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
> +{
> +	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
> +	void __iomem *ioaddr = pdata->ioaddr;
> +	unsigned long time;
> +	int ret;
> +	u32 lp_cr;
> +	u64 old_time_47bit, new_time_47bit;
> +
> +	ret = rtc_tm_to_time(tm, &time);
> +	if (ret != 0)
> +		return ret;
> +
> +	old_time_47bit = (((u64) (readl(ioaddr + SNVS_LPSRTCMR) &
> +		((0x1 << CNTR_TO_SECS_SH) - 1)) << 32) |
> +		((u64) readl(ioaddr + SNVS_LPSRTCLR)));
> +
> +	/* Disable RTC first */
> +	lp_cr = readl(ioaddr + SNVS_LPCR) & ~SNVS_LPCR_SRTC_ENV;
> +	writel(lp_cr, ioaddr + SNVS_LPCR);
> +	while (readl(ioaddr + SNVS_LPCR) & SNVS_LPCR_SRTC_ENV)
> +		;

Don't you need proper timeout?

> +
> +	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
> +	writel(time << CNTR_TO_SECS_SH, ioaddr + SNVS_LPSRTCLR);
> +	writel(time >> (32 - CNTR_TO_SECS_SH), ioaddr + SNVS_LPSRTCMR);
> +
> +	/* Enable RTC again */
> +	writel(lp_cr | SNVS_LPCR_SRTC_ENV, ioaddr + SNVS_LPCR);
> +	while (!(readl(ioaddr + SNVS_LPCR) & SNVS_LPCR_SRTC_ENV))
> +		;

Ditto

> +
> +	rtc_write_sync_lp(ioaddr);
> +
> +	new_time_47bit = (((u64) (readl(ioaddr + SNVS_LPSRTCMR) &
> +		((0x1 << CNTR_TO_SECS_SH) - 1)) << 32) |
> +		((u64) readl(ioaddr + SNVS_LPSRTCLR)));
> +
> +	time_diff = new_time_47bit - old_time_47bit;
> +
> +	/* signal all waiting threads that time changed */
> +	complete_all(&snvs_completion);
> +
> +	/* allow signalled threads to handle the time change notification */
> +	schedule();
> +
> +	/* reinitialize completion variable */
> +	INIT_COMPLETION(snvs_completion);
> +

Are you sure all these sync need to get done in driver?

> +	return 0;
> +}
> +
> +/*!
> + * This function reads the current alarm value into the passed in \b alrm
> + * argument. It updates the \b alrm's pending field value based on the whether
> + * an alarm interrupt occurs or not.
> + *
> + * @param  alrm         contains the RTC alarm value upon return
> + *
> + * @return  0 if successful; non-zero otherwise.
> + */
> +static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
> +{
> +	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
> +	void __iomem *ioaddr = pdata->ioaddr;
> +
> +	rtc_time_to_tm(readl(ioaddr + SNVS_LPTAR), &alrm->time);
> +	alrm->pending =
> +	    ((readl(ioaddr + SNVS_LPSR) & SNVS_LPSR_LPTA) != 0) ? 1 : 0;
> +
> +	return 0;
> +}
> +
> +/*!
> + * This function sets the RTC alarm based on passed in alrm.
> + *
> + * @param  alrm         the alarm value to be set in the RTC
> + *
> + * @return  0 if successful; non-zero otherwise.
> + */
> +static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
> +{
> +	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
> +	void __iomem *ioaddr = pdata->ioaddr;
> +	unsigned long lock_flags = 0;
> +	u32 lp_cr;
> +	int ret;
> +
> +	if (rtc_valid_tm(&alrm->time)) {
> +		if (alrm->time.tm_sec > 59 ||
> +		    alrm->time.tm_hour > 23 || alrm->time.tm_min > 59) {

Haven't all these checking been covered by rtc_valid_tm()?

> +			return -EINVAL;
> +		}
> +	}
> +
> +	spin_lock_irqsave(&rtc_lock, lock_flags);
> +
> +	ret = rtc_update_alarm(dev, &alrm->time);
> +	if (ret)
> +		goto out;
> +
> +	lp_cr = readl(ioaddr + SNVS_LPCR);
> +
> +	if (alrm->enabled)
> +		lp_cr |= (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
> +	else
> +		lp_cr &= ~(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
> +
> +	if (lp_cr & SNVS_LPCR_ALL_INT_EN) {
> +		if (!pdata->irq_enable) {
> +			enable_irq(pdata->irq);
> +			pdata->irq_enable = true;
> +		}
> +	} else {
> +		if (pdata->irq_enable) {
> +			disable_irq(pdata->irq);
> +			pdata->irq_enable = false;
> +		}
> +	}
> +
> +	writel(lp_cr, ioaddr + SNVS_LPCR);
> +
> +out:
> +	rtc_write_sync_lp(ioaddr);
> +	spin_unlock_irqrestore(&rtc_lock, lock_flags);
> +
> +	return ret;
> +}
> +
> +/*!
> + * This function is used to provide the content for the /proc/driver/rtc
> + * file.
> + *
> + * @param  seq  buffer to hold the information that the driver wants to write
> + *
> + * @return  The number of bytes written into the rtc file.
> + */
> +static int snvs_rtc_proc(struct device *dev, struct seq_file *seq)
> +{
> +	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
> +	void __iomem *ioaddr = pdata->ioaddr;
> +
> +	seq_printf(seq, "alarm_IRQ\t: %s\n",
> +		   (((readl(ioaddr + SNVS_LPCR)) & SNVS_LPCR_LPTA_EN) !=
> +		    0) ? "yes" : "no");
> +
> +	return 0;
> +}
> +
> +static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
> +{
> +	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
> +	void __iomem *ioaddr = pdata->ioaddr;
> +	u32 lp_cr;
> +	unsigned long lock_flags = 0;
> +
> +	spin_lock_irqsave(&rtc_lock, lock_flags);
> +
> +	if (enable) {
> +		if (!pdata->irq_enable) {
> +			enable_irq(pdata->irq);
> +			pdata->irq_enable = true;
> +		}
> +		lp_cr = readl(ioaddr + SNVS_LPCR);
> +		lp_cr |= (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
> +		writel(lp_cr, ioaddr + SNVS_LPCR);
> +	} else {
> +		lp_cr = readl(ioaddr + SNVS_LPCR);
> +		lp_cr &= ~(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
> +		if (((lp_cr & SNVS_LPCR_ALL_INT_EN) == 0)
> +		    && (pdata->irq_enable)) {
> +			disable_irq(pdata->irq);
> +			pdata->irq_enable = false;
> +		}
> +		writel(lp_cr, ioaddr + SNVS_LPCR);
> +	}
> +
> +	rtc_write_sync_lp(ioaddr);
> +	spin_unlock_irqrestore(&rtc_lock, lock_flags);
> +
> +	return 0;
> +}
> +
> +/*!
> + * This function is used to support some ioctl calls directly.
> + * Other ioctl calls are supported indirectly through the
> + * arm/common/rtctime.c file.
> + *
> + * @param  cmd          ioctl command as defined in include/linux/rtc.h
> + * @param  arg          value for the ioctl command
> + *
> + * @return  0 if successful or negative value otherwise.
> + */
> +static int snvs_rtc_ioctl(struct device *dev, unsigned int cmd,
> +			 unsigned long arg)
> +{
> +	struct rtc_drv_data *pdata = dev_get_drvdata(dev);
> +	void __iomem *ioaddr = pdata->ioaddr;
> +	u64 time_47bit;
> +	int retVal;
> +
> +	switch (cmd) {
> +	case RTC_READ_TIME_47BIT:
> +		time_47bit = (((u64) (readl(ioaddr + SNVS_LPSRTCMR) &
> +			((0x1 << CNTR_TO_SECS_SH) - 1)) << 32) |
> +			((u64) readl(ioaddr + SNVS_LPSRTCLR)));
> +
> +		if (arg && copy_to_user((u64 *) arg, &time_47bit, sizeof(u64)))
> +			return -EFAULT;
> +
> +		return 0;
> +
> +	/* This IOCTL to be used by processes to be notified of time changes */
> +	case RTC_WAIT_TIME_SET:
> +		/* don't block without releasing mutex first */
> +		mutex_unlock(&pdata->rtc->ops_lock);
> +
> +		/* sleep till awakened by SRTC driver when LPSCMR is changed */
> +		wait_for_completion(&snvs_completion);
> +
> +		/* relock mutex because rtc_dev_ioctl will unlock again */
> +		retVal = mutex_lock_interruptible(&pdata->rtc->ops_lock);
> +
> +		/* copy the new time difference = new time - previous time
> +		 * to the user param. The difference is a signed value */
> +		if (arg && copy_to_user((int64_t *) arg, &time_diff,
> +			sizeof(int64_t)))
> +			return -EFAULT;
> +
> +		return retVal;
> +
> +	}
> +
> +	return -ENOIOCTLCMD;
> +}

I haven't completely understood this, and will need more study.

> +
> +/*!
> + * The RTC driver structure
> + */
> +static struct rtc_class_ops snvs_rtc_ops = {
> +	.open = snvs_rtc_open,
> +	.release = snvs_rtc_release,
> +	.read_time = snvs_rtc_read_time,
> +	.set_time = snvs_rtc_set_time,
> +	.read_alarm = snvs_rtc_read_alarm,
> +	.set_alarm = snvs_rtc_set_alarm,
> +	.proc = snvs_rtc_proc,
> +	.ioctl = snvs_rtc_ioctl,
> +	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
> +};
> +
> +/*! SNVS RTC Power management control */
> +static int __devinit snvs_rtc_probe(struct platform_device *pdev)
> +{
> +	struct timespec tv;
> +	struct resource *res;
> +	struct rtc_device *rtc;
> +	struct rtc_drv_data *pdata = NULL;
> +	void __iomem *ioaddr;
> +	u32 lp_cr;
> +	int ret = 0;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res)
> +		return -ENODEV;
> +
> +	ioaddr = ioremap(res->start, resource_size(res));
> +	if (!ioaddr)
> +		return -EADDRNOTAVAIL;

Use of_iomap() can save the call of platform_get_resource().

> +
> +	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata)
> +		return -ENOMEM;
> +
> +	pdata->ioaddr = ioaddr;
> +
> +	/* Configure and enable the RTC */
> +	pdata->irq = platform_get_irq(pdev, 0);
> +	if (pdata->irq >= 0) {
> +		if (request_irq(pdata->irq, snvs_rtc_interrupt, IRQF_SHARED,
> +				pdev->name, pdev) < 0) {
> +			dev_warn(&pdev->dev, "interrupt not available.\n");
> +			pdata->irq = -1;
> +		} else {
> +			disable_irq(pdata->irq);
> +			pdata->irq_enable = false;
> +		}
> +	}
> +
> +	/* initialize glitch detect */
> +	writel(SNVS_LPPGDR_INIT, ioaddr + SNVS_LPPGDR);
> +	udelay(100);
> +
> +	/* clear lp interrupt status */
> +	writel(0xFFFFFFFF, ioaddr + SNVS_LPSR);
> +
> +	/* Enable RTC */
> +	lp_cr = readl(ioaddr + SNVS_LPCR);
> +	if ((lp_cr & SNVS_LPCR_SRTC_ENV) == 0)
> +		writel(lp_cr | SNVS_LPCR_SRTC_ENV, ioaddr + SNVS_LPCR);
> +
> +	udelay(100);
> +
> +	writel(0xFFFFFFFF, ioaddr + SNVS_LPSR);
> +	udelay(100);

All these udelay calls are necessary?

> +
> +	platform_set_drvdata(pdev, pdata);
> +
> +	rtc = rtc_device_register(pdev->name, &pdev->dev,
> +				  &snvs_rtc_ops, THIS_MODULE);
> +	if (IS_ERR(rtc)) {
> +		ret = PTR_ERR(rtc);
> +		goto err_out;
> +	}
> +
> +	pdata->rtc = rtc;
> +
> +	tv.tv_nsec = 0;
> +	tv.tv_sec = rtc_read_lp_counter(ioaddr + SNVS_LPSRTCMR);
> +
> +	/* By default, devices should wakeup if they can */
> +	/* So snvs is set as "should wakeup" as it can */
> +	device_init_wakeup(&pdev->dev, 1);
> +
> +	return ret;
> +
> +err_out:
> +	iounmap(ioaddr);
> +	if (pdata->irq >= 0)
> +		free_irq(pdata->irq, pdev);
> +
> +	return ret;
> +}
> +
> +static int __devexit snvs_rtc_remove(struct platform_device *pdev)
> +{
> +	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
> +	rtc_device_unregister(pdata->rtc);
> +	if (pdata->irq >= 0)
> +		free_irq(pdata->irq, pdev);
> +	iounmap(pdata->ioaddr);
> +
> +	return 0;
> +}
> +
> +/*!
> + * This function is called to save the system time delta relative to
> + * the SNVS RTC when enterring a low power state. This time delta is
> + * then used on resume to adjust the system time to account for time
> + * loss while suspended.
> + *
> + * @param   pdev  not used
> + * @param   state Power state to enter.
> + *
> + * @return  The function always returns 0.
> + */
> +static int snvs_rtc_suspend(struct platform_device *pdev, pm_message_t state)
> +{
> +	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
> +
> +	if (device_may_wakeup(&pdev->dev)) {
> +		enable_irq_wake(pdata->irq);
> +	} else {
> +		if (pdata->irq_enable)
> +			disable_irq(pdata->irq);
> +	}
> +
> +	return 0;
> +}
> +
> +/*!
> + * This function is called to correct the system time based on the
> + * current SNVS RTC time relative to the time delta saved during
> + * suspend.
> + *
> + * @param   pdev  not used
> + *
> + * @return  The function always returns 0.
> + */
> +static int snvs_rtc_resume(struct platform_device *pdev)
> +{
> +	struct rtc_drv_data *pdata = platform_get_drvdata(pdev);
> +
> +	if (device_may_wakeup(&pdev->dev)) {
> +		disable_irq_wake(pdata->irq);
> +	} else {
> +		if (pdata->irq_enable)
> +			enable_irq(pdata->irq);
> +	}
> +
> +	return 0;
> +}
> +

Shouldn't these 2 functions be wrapped by #ifdef CONFIG_PM?

> +static const struct of_device_id __devinitdata snvs_dt_ids[] = {
> +	{ .compatible = "fsl,snvs" },

"fsl,snvs-rtc"?

> +	{ /* sentinel */ }
> +};
> +
> +/*!
> + * Contains pointers to the power management callback functions.
> + */
> +static struct platform_driver snvs_rtc_driver = {
> +	.driver = {
> +		.name	= "snvs_rtc",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = snvs_dt_ids,
> +	},
> +	.probe = snvs_rtc_probe,
> +	.remove = __exit_p(snvs_rtc_remove),
> +	.suspend = snvs_rtc_suspend,
> +	.resume = snvs_rtc_resume,
> +};
> +

...
> +/*!
> + * This function creates the /proc/driver/rtc file and registers the device RTC
> + * in the /dev/misc directory. It also reads the RTC value from external source
> + * and setup the internal RTC properly.
> + *
> + * @return  -1 if RTC is failed to initialize; 0 is successful.
> + */
> +static int __init snvs_rtc_init(void)
> +{
> +	return platform_driver_register(&snvs_rtc_driver);
> +}
> +module_init(snvs_rtc_init);
> +
> +/*!
> + * This function removes the /proc/driver/rtc file and un-registers the
> + * device RTC from the /dev/misc directory.
> + */
> +static void __exit snvs_rtc_exit(void)
> +{
> +	platform_driver_unregister(&snvs_rtc_driver);
> +}
> +module_exit(snvs_rtc_exit);

These can just be module_platform_driver(snvs_rtc_driver)?

> +
> +MODULE_AUTHOR("Anish Trivedi <anish at freescale.com>, "
> +	      "Eric Miao <eric.miao at linaro.org>, "
> +	      "Anson Huang <b20788 at freescale.com>, "
> +	      "Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>");
> +MODULE_DESCRIPTION("SNVS Realtime Clock Driver (RTC)");
> +MODULE_LICENSE("GPL v2");

MODULE_ALIAS?

> -- 
> 1.7.9.1
> 

-- 
Regards,
Shawn


From m.szyprowski at samsung.com  Thu Mar 22 11:31:46 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Thu, 22 Mar 2012 16:31:46 +0100
Subject: [PATCH v4 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and
 EXYNOS5
In-Reply-To: <4F6B3256.40304@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
 <1331736138-28964-6-git-send-email-kgene.kim@samsung.com>
 <CAJuYYwTJsA1M1Qj2P1-1K=pWzi0BPo8YJNDSx4NqGC7NX0030g@mail.gmail.com>
 <074401cd074f$c2946b90$47bd42b0$%szyprowski@samsung.com>
 <4F6B3256.40304@samsung.com>
Message-ID: <084601cd0840$e4a414a0$adec3de0$%szyprowski@samsung.com>

Hello,

On Thursday, March 22, 2012 3:08 PM Kukjin Kim wrote:

> On 03/21/12 03:45, Marek Szyprowski wrote:
> > Hello,
> >
> > On Wednesday, March 21, 2012 10:14 AM Thomas Abraham wrote:
> >
> >> On 14 March 2012 20:12, Kukjin Kim<kgene.kim at samsung.com>  wrote:
> >>> Actually, the base address of uart is different between EXYNOS4
> >>> and EXYNOS5 and this patch enables to support uart for EXYNOS4
> >>> and EXYNOS5 SoCs at runtime.
> >>>
> >>> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
> >>> ---
> >>
> >> [...]
> >>
> >>> diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-
> >> exynos/include/mach/debug-macro.S
> >>> index 6cacf16..6c857ff 100644
> >>> --- a/arch/arm/mach-exynos/include/mach/debug-macro.S
> >>> +++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
> >>> @@ -21,8 +21,13 @@
> >>>          */
> >>>
> >>>         .macro addruart, rp, rv, tmp
> >>> -               ldr     \rp, = S3C_PA_UART
> >>> -               ldr     \rv, = S3C_VA_UART
> >>> +               mov     \rp, #0x10000000
> >>
> >> This is physical address of Exynos4/5 CPUID register which cannot be
> >> used here. And virtual address S5P_VA_CPUID also cannot be used here
> >> since this will be called before paging_init when earlyprintk boot
> >> param is used. So, with this change, earlyprintk does not work for
> >> both Exynos4 and Exynos5.
> >
> > I confirm, printascii freeze the system on EXYNOS4 after that patch,
> > tested on Exynos4210 Nuri board.
> >
> Hi,
> 
> I think, it can be solved with following and if no problems, it will be
> fixed during v3.4-rcX.
> 
> diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S
> b/arch/arm/mach-exynos/in
> index 6c857ff..a865417 100644
> --- a/arch/arm/mach-exynos/include/mach/debug-macro.S
> +++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
> @@ -21,10 +21,10 @@
>           */
> 
>          .macro addruart, rp, rv, tmp
> -               mov     \rp, #0x10000000
> -               ldr     \rp, [\rp, #0x0]
> -               and     \rp, \rp, #0xf00000
> -               teq     \rp, #0x500000          @@ EXYNOS5
> +               mrc     p15, 0, \tmp, c0, c0, 0
> +               and     \tmp, \tmp, #0xf0
> +               teq     \tmp, #0xf0             @@ A15
> +
>                  ldreq   \rp, =EXYNOS5_PA_UART
>                  movne   \rp, #EXYNOS4_PA_UART   @@ EXYNOS4
>                  ldr     \rv, =S3C_VA_UART
> 

The above patch solved the problem on Exynos4.

Tested-by: Marek Szyprowski <m.szyprowski at samsung.com>

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From sbabic at denx.de  Thu Mar 22 12:03:22 2012
From: sbabic at denx.de (Stefano Babic)
Date: Thu, 22 Mar 2012 17:03:22 +0100
Subject: [PATCH] ARM: OMAP: Add support for AM35xx UART4/ttyO3
In-Reply-To: <1318963661-27755-1-git-send-email-kyle.manna@fuel7.com>
References: <1318963661-27755-1-git-send-email-kyle.manna@fuel7.com>
Message-ID: <4F6B4D4A.2040103@denx.de>

On 18/10/2011 20:47, Kyle Manna wrote:
> Add hwmod support to enable access to UART4 of the AM35xx series of
> chips.  The UART4 device referenced from the TRM will show up as ttyO3.
> 
> This was tested on an AM3505.
> 
> Signed-off-by: Kyle Manna <kyle.manna at fuel7.com>
> ---

Hi Kyle,

>  arch/arm/mach-omap2/clock3xxx_data.c       |   11 ++++++
>  arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   52 ++++++++++++++++++++++++++++
>  arch/arm/mach-omap2/prcm-common.h          |    2 +
>  arch/arm/plat-omap/include/plat/irqs.h     |    2 +-
>  arch/arm/plat-omap/include/plat/serial.h   |    1 +
>  5 files changed, 67 insertions(+), 1 deletions(-)

Can I gently ask you which pinmux setup do you use to test your patch ?

I am trying to make uart4 working on a am3517 with mainline kernel
(3.3+, your patch is merged). However, on my board the uart4 pins are
shared with the camera, and not with SD, as maybe is more common. I set
the pinmux to switch the pins (gpio_95 / gpio_96 / gpio_97 /gpio_98) to
the uart4, and ttyO3 is registered and available, and thanks your patch
both clocks iclk and fclk are active. However, I cannot see activity on
the tx line if I try to send some characters.

Maybe do you use the same pinmux and am I forgetting something else ?

Thanks,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================


From svenkatr at ti.com  Thu Mar 22 12:06:36 2012
From: svenkatr at ti.com (S, Venkatraman)
Date: Thu, 22 Mar 2012 21:36:36 +0530
Subject: Occasional crashes in suspend-resume with MMC transactions
In-Reply-To: <B5906170F1614E41A8A28DE3B8D12143317FFAC0@DBDE01.ent.ti.com>
References: <B5906170F1614E41A8A28DE3B8D12143317FDFBB@DBDE01.ent.ti.com>
 <B5906170F1614E41A8A28DE3B8D12143317FF773@DBDE01.ent.ti.com>
 <CANfBPZ9b=6dLbY2D3oAg=Gz_vwAOJ+KC_Bo5ugVJEwumeej_Bw@mail.gmail.com>
 <B5906170F1614E41A8A28DE3B8D12143317FFAC0@DBDE01.ent.ti.com>
Message-ID: <CANfBPZ9AU+W7qP+uE2s2EnpzKhUqVQLdEgN=CUeNJZkSoh7+5A@mail.gmail.com>

On Thu, Mar 22, 2012 at 8:13 PM, Bedia, Vaibhav <vaibhav.bedia at ti.com> wrote:
> On Thu, Mar 22, 2012 at 19:57:16, S, Venkatraman wrote:
> [...]
>>
>> I see (in 3.3) that the host controller driver does a "return ret" and
>> that means the errors is propagated.
>> Where is the return code lost /overridden ?
>>
>
> The return code gets overridden due to the call to host->pdata->resume()
> which always returns 0.

Thanks - I see what you mean. But the patch is clunky.
A clean fix would be to not capture the return code of resume() in
"ret" and let the old
value of ret be propagated as is.

>
> static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
> {
> ? ? ? ?struct omap_mmc_platform_data *mmc = dev->platform_data;
>
> ? ? ? ?enable_irq(mmc->slots[0].card_detect_irq);
> ? ? ? ?return 0;
> }
>
> Regards,
> Vaibhav


From vaibhav.bedia at ti.com  Thu Mar 22 12:13:03 2012
From: vaibhav.bedia at ti.com (Bedia, Vaibhav)
Date: Thu, 22 Mar 2012 16:13:03 +0000
Subject: Occasional crashes in suspend-resume with MMC transactions
In-Reply-To: <CANfBPZ9AU+W7qP+uE2s2EnpzKhUqVQLdEgN=CUeNJZkSoh7+5A@mail.gmail.com>
References: <B5906170F1614E41A8A28DE3B8D12143317FDFBB@DBDE01.ent.ti.com>
 <B5906170F1614E41A8A28DE3B8D12143317FF773@DBDE01.ent.ti.com>
 <CANfBPZ9b=6dLbY2D3oAg=Gz_vwAOJ+KC_Bo5ugVJEwumeej_Bw@mail.gmail.com>
 <B5906170F1614E41A8A28DE3B8D12143317FFAC0@DBDE01.ent.ti.com>
 <CANfBPZ9AU+W7qP+uE2s2EnpzKhUqVQLdEgN=CUeNJZkSoh7+5A@mail.gmail.com>
Message-ID: <B5906170F1614E41A8A28DE3B8D12143317FFC59@DBDE01.ent.ti.com>

On Thu, Mar 22, 2012 at 21:36:36, S, Venkatraman wrote:
> On Thu, Mar 22, 2012 at 8:13 PM, Bedia, Vaibhav <vaibhav.bedia at ti.com> wrote:
> > On Thu, Mar 22, 2012 at 19:57:16, S, Venkatraman wrote:
> > [...]
> >>
> >> I see (in 3.3) that the host controller driver does a "return ret" and
> >> that means the errors is propagated.
> >> Where is the return code lost /overridden ?
> >>
> >
> > The return code gets overridden due to the call to host->pdata->resume()
> > which always returns 0.
> 
> Thanks - I see what you mean. But the patch is clunky.
> A clean fix would be to not capture the return code of resume() in
> "ret" and let the old
> value of ret be propagated as is.
> 

I agree. However, right now there's a dev_dbg() which checks for the return code.
I could change the host->pdata->resume() and host->pdata->suspend() to not return
anything if that's acceptable.

More importantly, is this the right fix or does the driver need some other fix
to make sure that such suspend failures do not occur at all?


From kyle.manna at fuel7.com  Thu Mar 22 13:00:00 2012
From: kyle.manna at fuel7.com (Kyle Manna)
Date: Thu, 22 Mar 2012 12:00:00 -0500
Subject: [PATCH] ARM: OMAP: Add support for AM35xx UART4/ttyO3
In-Reply-To: <4F6B4D4A.2040103@denx.de>
References: <1318963661-27755-1-git-send-email-kyle.manna@fuel7.com>
 <4F6B4D4A.2040103@denx.de>
Message-ID: <4F6B5A90.6030808@fuel7.com>

On 03/22/2012 11:03 AM, Stefano Babic wrote:
> On 18/10/2011 20:47, Kyle Manna wrote:
>> Add hwmod support to enable access to UART4 of the AM35xx series of
>> chips.  The UART4 device referenced from the TRM will show up as ttyO3.
>>
>> This was tested on an AM3505.
>>
>> Signed-off-by: Kyle Manna<kyle.manna at fuel7.com>
>> ---
> Hi Kyle,
>
>>   arch/arm/mach-omap2/clock3xxx_data.c       |   11 ++++++
>>   arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   52 ++++++++++++++++++++++++++++
>>   arch/arm/mach-omap2/prcm-common.h          |    2 +
>>   arch/arm/plat-omap/include/plat/irqs.h     |    2 +-
>>   arch/arm/plat-omap/include/plat/serial.h   |    1 +
>>   5 files changed, 67 insertions(+), 1 deletions(-)
> Can I gently ask you which pinmux setup do you use to test your patch ?
>
> I am trying to make uart4 working on a am3517 with mainline kernel
> (3.3+, your patch is merged). However, on my board the uart4 pins are
> shared with the camera, and not with SD, as maybe is more common. I set
> the pinmux to switch the pins (gpio_95 / gpio_96 / gpio_97 /gpio_98) to
> the uart4, and ttyO3 is registered and available, and thanks your patch
> both clocks iclk and fclk are active. However, I cannot see activity on
> the tx line if I try to send some characters.
>
> Maybe do you use the same pinmux and am I forgetting something else ?

My pin mux is configured in u-boot and is as follows:

     /* CCDC_FIELD: gpio_95, uP-TXD4 */ \
     MUX_VAL(CP(CCDC_FIELD),     (IDIS | PTD | DIS | M2)) \
     /* CCDC_HD: gpio_96, uP-RTS4# */ \
     MUX_VAL(CP(CCDC_HD),        (IDIS | PTD | DIS | M2)) \
     /* CCDC_VD: gpio_97, uP-CTS4# */ \
     MUX_VAL(CP(CCDC_VD),        (IEN  | PTD | EN  | M2)) \
     /* CCDC_WEN: gpio_98, uP-RXD4 */ \
     MUX_VAL(CP(CCDC_WEN),       (IEN  | PTD | DIS | M2)) \

I've just validated my AM3505 board does in fact toggle the TX line and 
writes valid data.  The running kernel is based on a linux-omap-3.1 and 
was the source for that patch.

Since it sounds like you have the same pinmux, perhaps something changed 
elsewhere in the kernel?  Have you tried validating that your hardware 
can toggle the pin as a GPIO first to eliminate any possibility of shorts?

- Kyle


From khilman at ti.com  Thu Mar 22 13:02:46 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 22 Mar 2012 10:02:46 -0700
Subject: [PATCH v4 RESEND 0/7] gpio/omap: Some more driver fixes
In-Reply-To: <20120321143437.8AF563E0648@localhost> (Grant Likely's message of
 "Wed, 21 Mar 2012 14:34:37 +0000")
References: <1332240799-6748-1-git-send-email-tarun.kanti@ti.com>
 <20120320143544.AA6E93E2834@localhost> <87haxj17xq.fsf@ti.com>
 <20120321143437.8AF563E0648@localhost>
Message-ID: <87limsbmbt.fsf@ti.com>

Grant Likely <grant.likely at secretlab.ca> writes:

> On Tue, 20 Mar 2012 10:46:57 -0700, Kevin Hilman <khilman at ti.com> wrote:
>> Hi Grant,
>> 
>> Grant Likely <grant.likely at secretlab.ca> writes:
>> 
>> > On Tue, 20 Mar 2012 16:23:12 +0530, Tarun Kanti DebBarma <tarun.kanti at ti.com> wrote:
>> >> This series excludes the cleanup patches as suggested by Kevin from
>> >> the previously posted series.
>> >> 
>> >> The fixes include correction of _set_gpio_irqenable() implementation,
>> >> missing wakeup_en register update in set_gpio_wakeup(), type mismatch
>> >> of gpio trigger parameter in set_gpio_trigger(), incorrect dataout
>> >> register update in set_gpio_dataout_() and few corrections in context
>> >> save logic.
>> >> 
>> >> It is baselined on top of:
>> >> git://git.secretlab.ca/git/linux-2.6.git gpio/next
>> >> Commit: 81b279d80a63628e580c71a31d30a8c3b3047ad4
>> >> 
>> >> Series is available here for reference:
>> >> git://gitorious.org/~tarunkanti/omap-sw-develoment/tarunkantis-linux-omap-dev for_3.4/gpio_more_fixes
>> >
>> > Merged; thanks
>> 
>> Can you hold off slightly before merging this.
>> 
>> I haven't been through v4 yet or tested the fixes alone now that they're
>> separated from the other cleanups.
>> 
>> Expect a pull request from me when ready.
>
> Okay.  It's in linux-next at the moment, but I'll pull it back out.

Thanks.

I've been through this series now, pull request coming shortly.
Hopefully it can still make it for v3.4 since this fixes some
regressions introduced by the previous series. :(

Kevin


From sbabic at denx.de  Thu Mar 22 13:11:59 2012
From: sbabic at denx.de (Stefano Babic)
Date: Thu, 22 Mar 2012 18:11:59 +0100
Subject: [PATCH] ARM: OMAP: Add support for AM35xx UART4/ttyO3
In-Reply-To: <4F6B5A90.6030808@fuel7.com>
References: <1318963661-27755-1-git-send-email-kyle.manna@fuel7.com>
 <4F6B4D4A.2040103@denx.de> <4F6B5A90.6030808@fuel7.com>
Message-ID: <4F6B5D5F.90206@denx.de>

On 22/03/2012 18:00, Kyle Manna wrote:

> 
> My pin mux is configured in u-boot and is as follows:
> 
>     /* CCDC_FIELD: gpio_95, uP-TXD4 */ \
>     MUX_VAL(CP(CCDC_FIELD),     (IDIS | PTD | DIS | M2)) \
>     /* CCDC_HD: gpio_96, uP-RTS4# */ \
>     MUX_VAL(CP(CCDC_HD),        (IDIS | PTD | DIS | M2)) \
>     /* CCDC_VD: gpio_97, uP-CTS4# */ \
>     MUX_VAL(CP(CCDC_VD),        (IEN  | PTD | EN  | M2)) \
>     /* CCDC_WEN: gpio_98, uP-RXD4 */ \
>     MUX_VAL(CP(CCDC_WEN),       (IEN  | PTD | DIS | M2)) \
> 

Well, we are using the same pins !

> I've just validated my AM3505 board does in fact toggle the TX line and
> writes valid data.  The running kernel is based on a linux-omap-3.1 and
> was the source for that patch.
> 
> Since it sounds like you have the same pinmux, perhaps something changed
> elsewhere in the kernel?

Maybe, but registers looks good - and tracing the serial driver I have
not seen anything wrong.

>  Have you tried validating that your hardware
> can toggle the pin as a GPIO first to eliminate any possibility of shorts?

I will do it now.

Thanks,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================


From linus.walleij at linaro.org  Thu Mar 22 14:09:15 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 22 Mar 2012 19:09:15 +0100
Subject: [PATCH] watchdog/coh901327: convert to use watchdog core
In-Reply-To: <20120322144950.GU10698@spo001.leaseweb.com>
References: <1331131929-22383-1-git-send-email-linus.walleij@stericsson.com>
 <20120307164240.GA1130@pengutronix.de>
 <CACRpkdaE5HASdF27db7EfnSoaUF8mA5bWoKUhaAzSegdBKsKFQ@mail.gmail.com>
 <20120315212705.GH10698@spo001.leaseweb.com>
 <CACRpkdZ9tD8XQ3tOwTHMa3jOhivkwW7YZO0WZgG7r5BYDNktCQ@mail.gmail.com>
 <20120322144950.GU10698@spo001.leaseweb.com>
Message-ID: <CACRpkdZ9iWVYSfnW4mRxvG8JxauV+ypjHbo25MCEp2HUzwqHyA@mail.gmail.com>

On Thu, Mar 22, 2012 at 3:49 PM, Wim Van Sebroeck <wim at iguana.be> wrote:

> I added it. Only issue left is that you don't set the timeout value properly.
> This will result in faulty values for the WDIOC_GETTIMEOUT iotcl.
> Furthermore margin should be unsigned int. And there is also no check to see
> if margin is a valid parameter after it is loaded as a module.
>
> Could you test attached patch?

I cannot test it right now because I'm out of reach for the hardware,
but it looks good to me so:
Acked-by: Linus Walleij <linus.walleij at linaro.org>

If I find any problems later I can surely fix them.

Yours,
Linus Walleij


From mturquette at ti.com  Thu Mar 22 14:35:29 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Thu, 22 Mar 2012 11:35:29 -0700
Subject: [PATCH 4/4] clk: wm831x: Add initial WM831x clock driver
In-Reply-To: <20120322113356.GC3091@opensource.wolfsonmicro.com>
References: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1332360082-25092-4-git-send-email-broonie@opensource.wolfsonmicro.com>
 <20120321222622.GG29317@pengutronix.de>
 <20120322111531.GA3091@opensource.wolfsonmicro.com>
 <20120322112613.GA3852@pengutronix.de>
 <20120322113356.GC3091@opensource.wolfsonmicro.com>
Message-ID: <CAJOA=zOYfwy-smo6ukX7GSE2jrwz4UxwpgcFJiW876ga7ksShw@mail.gmail.com>

On Thu, Mar 22, 2012 at 4:33 AM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Thu, Mar 22, 2012 at 12:26:13PM +0100, Sascha Hauer wrote:
>> On Thu, Mar 22, 2012 at 11:15:31AM +0000, Mark Brown wrote:
>
>> > No, that's not sensible. ?We shouldn't be open coding this into each
>> > individual driver that provides clocks, and we shouldn't have clock
>> > users having to guess at what scheme the driver author used to dedupe
>> > the clocks. ?As a driver author you would assume that the reason we're
>
>> It seems they got dropped. Currently the clock framework does nothing
>> with the device argument. But right, it could use this argument to
>> generate a suitable name.
>
> Indeed, and as with adding the stub clk_unregister() it seems like it's
> better at this point to just code the drivers as we'd expect them to
> work and fill out the framework to handle this rather than introducing
> workarounds in the drivers.

Agreed.  I put this off some time back, but I figured the WM831X
driver would bring the issue back up.

I'm happy for the core to concatenate the strings when a struct device
*dev is passed in.  However the reason I dropped this in the first
place is that I have some ideas on providing something like clk_get
directly from the common clk core and I hadn't figured out all of the
details yet.  For now we can handle the string concatenation in the
core and figure out those tricky details if/when the time comes to
provide a clk_get which is more closely linked to the clock framework
implementation.

I'll roll in a patch for my fixes series.

Regards,
Mike


From khilman at ti.com  Thu Mar 22 14:36:04 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 22 Mar 2012 11:36:04 -0700
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <4F6A5430.2090501@linaro.org> (Daniel Lezcano's message of "Wed, 
 21 Mar 2012 23:20:32 +0100")
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <4F69A872.50203@ti.com>
 <CAORVsuUeE046O7YJ_fE49NbW1OjZHZX+GuNiDkF0AnzBnSMbxA@mail.gmail.com>
 <4F6A04F3.6050306@linaro.org> <873991d3hs.fsf@ti.com>
 <4F6A5430.2090501@linaro.org>
Message-ID: <87fwd07aaz.fsf@ti.com>

Daniel Lezcano <daniel.lezcano at linaro.org> writes:

> On 03/21/2012 10:54 PM, Kevin Hilman wrote:
>> Daniel Lezcano<daniel.lezcano at linaro.org>  writes:
>>
>>> On 03/21/2012 02:43 PM, Jean Pihet wrote:
>>>> On Wed, Mar 21, 2012 at 11:07 AM, Santosh Shilimkar
>>>> <santosh.shilimkar at ti.com>   wrote:
>>>>> Daniel,
>>>>>
>>>>> On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
>>>>>> This patchset is a proposition to improve a bit the code.
>>>>>> The changes are code cleanup and does not change the behavior of the
>>>>>> driver itself.
>>>>>>
>>>>>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
>>>>>> and why the WFI is not used ?
>>>>>>
>>>>>> Daniel Lezcano (7):
>>>>>>     ARM: OMAP4: cpuidle - Remove unused valid field
>>>>>>     ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>>>>>>     ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>>>>>>     ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>>>>>>     ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>>>>>>     ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>>>>>>     ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>>>>>>       time
>>>>>>
>>>>> The series looks fine to me in general. This clean-up is applicable
>>>>> for OMAP3 cpuidle code as well.
>>>> Great!
>>>> However OMAP3 has a few specific things that cannot be removed as easily:
>>>> - the 'valid' flag is used because only certain combinations of power
>>>> domains states are possible,
>>>
>>> When I look the board-rx51 code I see:
>>>
>>> static struct cpuidle_params rx51_cpuidle_params[] = {
>>> 	/* C1 */
>>> 	{110 + 162, 5 , 1},
>>> 	/* C2 */
>>> 	{106 + 180, 309, 1},
>>> 	/* C3 */
>>> 	{107 + 410, 46057, 0},
>>> 	/* C4 */
>>> 	{121 + 3374, 46057, 0},
>>> 	/* C5 */
>>> 	{855 + 1146, 46057, 1},
>>> 	/* C6 */
>>> 	{7580 + 4134, 484329, 0},
>>> 	/* C7 */
>>> 	{7505 + 15274, 484329, 1},
>>> };
>>>
>>> If C3, C4, C6 are not valid, so AFAICS never used in the cpuidle code
>>> why the values are 'exit_latency' and 'target_residency' specified ? I
>>> mean why don't we have { 0, 0, 0 } ? Is it just for information ?
>>
>> Yes, because getting those numbers were based on some board-specific
>> measurements, and we don't want those values to be lost.  Also, some
>> usage patterns might want to (re)enable those states.
>
> When you say re-enable you mean for a custom kernel ?

Yes.

>>> I understand the purpose of this code but it looks a bit tricky and
>>> hard to factor out. Is it acceptable to create a new cpuidle driver
>>> for rx51 then we factor out the code between omap3, omap4 and rx51
>>> when all the code consistent ?
>>
>> I don't like that idea.  All the code is the same, the only thing we
>> need is the ability to pass in board-specific latency numbers for the
>> C-states.
>
> Sorry I was not clear, I was not saying duplicating the code. What I
> meant is to create a driver:
>
> struct cpuidle_driver rx51_idle_driver = {
>  	.name = 	"rx51_idle",
> 	.owner = 	THIS_MODULE,
> 	.states = {
> 		{
> 			/* What is in rx51_cpuidle_params */
> 		}
> 	};
>
> We put in there only the valid fields and we keep in a comment the
> table with the latency numbers.

Ah, OK.  I misunderstood.

> Assuming the valid field is for handling the table overwritting, we
> can then remove it. By this way, we simplify the next_valid_state
> function.

probably we can remove next_valid_state all together after 3.4 since the
new sysfs entry for that feature looks to be queued in linux-next.

> Depending if we have rx51 or not, we register the rx51 driver or the
> omap3 driver in the init function. That has also the benefit to group
> the cpuidle code in the cpuidle34xx file.

yes, but with board-specific data in SoC-specific code, which is not a
clean separation IMO.  How would you plan to pass which board it's
running on?

>> These latency numbers are obviously quite significant when it comes to
>> the final power consumption, and these values often depend on
>> board-specific settings.  Until there are generic frameworks for
>> defining all the latencies involved, passing these values in from board
>> files is absolutly needed.
>
> Yes but before creating the generic framework, we have to do a
> transversal cpuidle consolidation across the SoC, factor out the code
> when possible, and ensure the consistency between the different
> platform and see a common pattern to emerge from this work.

Agreed, but if that means ignoring platform-specific customization, and
not putting in other mechanisms to configure platform specific details,
it is throwing away useful infrastructure.

IMO, any consolidated framework needs some way to customize or pass in
latencies from platform-specific code.  Long term, I suppose this needs
to be DT based.

That being said, I do want to see this consolidation happen, so...

In OMAP land, we are in the middle of putting in place a better
framework for defining/tracking the various latencies involved in PM
transitions (using per-device PM Qos.) After that, we will likely be
reworking and revalidating these latency numbers for all OMAPs

So maybe the best approach to help in consolidation is just to drop the
board-rx51 data all together for now, as well as the ability to pass
custom C states from board files.  

The default, unoptimized OMAP3 numbers will work fine for that board,
and anyone wanting to do optimized power work for that platform can
still do it with a custom kernel.  (There is still lots of out of tree
work for the n900 that never made it upstream, so I doubt the mainline
users of n900 will be affected by this level of power tweaking.)

If we do that, then as part of the consolidation effort, some DT-based
customization should be defined as well to override/customize C states.

Kevin


From swarren at wwwdotorg.org  Thu Mar 22 14:40:38 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 22 Mar 2012 12:40:38 -0600
Subject: [PATCH] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
References: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <4F6B7226.8000102@wwwdotorg.org>

On 03/16/2012 03:03 PM, Stephen Warren wrote:
> All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
> to avoid duplication.
> 
> All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
> parameterized version in Makefile.lib to avoid duplication.

Michal,

Does this change look reasonable? It has acks from people working on 4
of the 7 affected architectures; would you prefer acks from all?

Thanks.


From broonie at opensource.wolfsonmicro.com  Thu Mar 22 14:44:15 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 22 Mar 2012 18:44:15 +0000
Subject: [PATCH 4/4] clk: wm831x: Add initial WM831x clock driver
In-Reply-To: <CAJOA=zOYfwy-smo6ukX7GSE2jrwz4UxwpgcFJiW876ga7ksShw@mail.gmail.com>
References: <1332360082-25092-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <1332360082-25092-4-git-send-email-broonie@opensource.wolfsonmicro.com>
 <20120321222622.GG29317@pengutronix.de>
 <20120322111531.GA3091@opensource.wolfsonmicro.com>
 <20120322112613.GA3852@pengutronix.de>
 <20120322113356.GC3091@opensource.wolfsonmicro.com>
 <CAJOA=zOYfwy-smo6ukX7GSE2jrwz4UxwpgcFJiW876ga7ksShw@mail.gmail.com>
Message-ID: <20120322184415.GA3291@opensource.wolfsonmicro.com>

On Thu, Mar 22, 2012 at 11:35:29AM -0700, Turquette, Mike wrote:

> I'm happy for the core to concatenate the strings when a struct device
> *dev is passed in.  However the reason I dropped this in the first
> place is that I have some ideas on providing something like clk_get
> directly from the common clk core and I hadn't figured out all of the
> details yet.  For now we can handle the string concatenation in the
> core and figure out those tricky details if/when the time comes to
> provide a clk_get which is more closely linked to the clock framework
> implementation.

Yeah, it's that sort of feature that most pushes against doing it in the
drivers - for example, the regulator API never ends up doing anything
like the concatenation.
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From hartleys at visionengravers.com  Thu Mar 22 14:52:52 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Thu, 22 Mar 2012 13:52:52 -0500
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <20120322073750.GA637@mwesterb-mobl.ger.corp.intel.com>
References: <4F683B36.8090101@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>
 <20120321193231.GA3740@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48AB1@AUSP01VMBX24.collaborationhost.net>
 <20120322073750.GA637@mwesterb-mobl.ger.corp.intel.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020696D48CAF@AUSP01VMBX24.collaborationhost.net>

On Thursday, March 22, 2012 12:38 AM, Mika Westerberg wrote:
> On Wed, Mar 21, 2012 at 07:47:52PM -0500, H Hartley Sweeten wrote:
>> Without this patch I get the "got interrupt while active list is empty" messages
>> but only occasionally. Other than the messages the mmc_spi driver seems to
>> be working ok with dma.
>> 
>> I hacked in a dump of the DMA Global Interrupt register when I get the
>> "got interrupt while active list is empty" messages and get this:
>> 
>> dma dma1chan1: got interrupt while active list is empty (00000000)

Mika,

I hacked this back to the handle_one_vic function. It looks like every time
I get the message above the stat read in that function shows an active
interrupt for DMAM2M0 (the dma rx channel) and DMAM2M1 (the dma
tx channel). Because of the way handle_one_vic processes the irq's, the
DMAM2M0 interrupt gets handled first. When it's done it must be clearing
the DMAM2M1 interrupt automatically for some reason. So, when it's
handled there is no interrupt pending so we get the message.

The "cleanest" fix I can think of is the following patch.  This is against
linux-next.

---

From: H Hartley Sweeten <hsweeten at visionengravers.com>

dma: ep93xx: check for spurious interrupts

The ep93xx dma controller generates spurious interrupts on dma1chan1 when
used with the mmc_spi driver. Catch these early by making sure there is an
interrupt to actually process.

Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>

---

diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index e6f133b..3cfabe6 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -38,7 +38,7 @@
 #define M2P_CONTROL_ENABLE		BIT(4)
 #define M2P_CONTROL_ICE			BIT(6)
 
-#define M2P_INTERRUPT			0x0004
+#define M2X_INTERRUPT			0x0004	/* M2P and M2M */
 #define M2P_INTERRUPT_STALL		BIT(0)
 #define M2P_INTERRUPT_NFB		BIT(1)
 #define M2P_INTERRUPT_ERROR		BIT(3)
@@ -78,7 +78,6 @@
 #define M2M_CONTROL_NO_HDSK		BIT(24)
 #define M2M_CONTROL_PWSC_SHIFT		25
 
-#define M2M_INTERRUPT			0x0004
 #define M2M_INTERRUPT_DONEINT		BIT(1)
 
 #define M2M_BCR0			0x0010
@@ -187,7 +186,8 @@ struct ep93xx_dma_engine {
 	int			(*hw_setup)(struct ep93xx_dma_chan *);
 	void			(*hw_shutdown)(struct ep93xx_dma_chan *);
 	void			(*hw_submit)(struct ep93xx_dma_chan *);
-	int			(*hw_interrupt)(struct ep93xx_dma_chan *);
+	int			(*hw_interrupt)(struct ep93xx_dma_chan *,
+						u32 irq_status);
 #define INTERRUPT_UNKNOWN	0
 #define INTERRUPT_DONE		1
 #define INTERRUPT_NEXT_BUFFER	2
@@ -376,16 +376,15 @@ static void m2p_hw_submit(struct ep93xx_dma_chan *edmac)
 	m2p_set_control(edmac, control);
 }
 
-static int m2p_hw_interrupt(struct ep93xx_dma_chan *edmac)
+static int m2p_hw_interrupt(struct ep93xx_dma_chan *edmac, u32 irq_status)
 {
-	u32 irq_status = readl(edmac->regs + M2P_INTERRUPT);
 	u32 control;
 
 	if (irq_status & M2P_INTERRUPT_ERROR) {
 		struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
 
 		/* Clear the error interrupt */
-		writel(1, edmac->regs + M2P_INTERRUPT);
+		writel(1, edmac->regs + M2X_INTERRUPT);
 
 		/*
 		 * It seems that there is no easy way of reporting errors back
@@ -560,15 +559,15 @@ static void m2m_hw_submit(struct ep93xx_dma_chan *edmac)
 	}
 }
 
-static int m2m_hw_interrupt(struct ep93xx_dma_chan *edmac)
+static int m2m_hw_interrupt(struct ep93xx_dma_chan *edmac, u32 irq_status)
 {
 	u32 control;
 
-	if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_DONEINT))
+	if (!(irq_status & M2M_INTERRUPT_DONEINT))
 		return INTERRUPT_UNKNOWN;
 
 	/* Clear the DONE bit */
-	writel(0, edmac->regs + M2M_INTERRUPT);
+	writel(0, edmac->regs + M2X_INTERRUPT);
 
 	/* Disable interrupts and the channel */
 	control = readl(edmac->regs + M2M_CONTROL);
@@ -735,6 +734,12 @@ static irqreturn_t ep93xx_dma_interrupt(int irq, void *dev_id)
 	struct ep93xx_dma_chan *edmac = dev_id;
 	struct ep93xx_dma_desc *desc;
 	irqreturn_t ret = IRQ_HANDLED;
+	u32 irq_status;
+
+	/* Make sure we actually have an interrupt to process */
+	irq_status = readl(edmac->regs + M2X_INTERRUPT);
+	if (!irq_status)
+		return IRQ_NONE;
 
 	spin_lock(&edmac->lock);




From mika.westerberg at iki.fi  Thu Mar 22 16:03:39 2012
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Thu, 22 Mar 2012 22:03:39 +0200
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F0020696D48CAF@AUSP01VMBX24.collaborationhost.net>
References: <4F683B36.8090101@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>
 <20120321193231.GA3740@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48AB1@AUSP01VMBX24.collaborationhost.net>
 <20120322073750.GA637@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48CAF@AUSP01VMBX24.collaborationhost.net>
Message-ID: <20120322200339.GA5812@mwesterb-mobl.ger.corp.intel.com>

On Thu, Mar 22, 2012 at 01:52:52PM -0500, H Hartley Sweeten wrote:

> I hacked this back to the handle_one_vic function. It looks like every time
> I get the message above the stat read in that function shows an active
> interrupt for DMAM2M0 (the dma rx channel) and DMAM2M1 (the dma
> tx channel). Because of the way handle_one_vic processes the irq's, the
> DMAM2M0 interrupt gets handled first. When it's done it must be clearing
> the DMAM2M1 interrupt automatically for some reason. So, when it's
> handled there is no interrupt pending so we get the message.
> 
> The "cleanest" fix I can think of is the following patch.  This is against
> linux-next.

I can't figure out any better fix unless we move ep93xx back to use
!MULTI_IRQ_HANDLER which obviously is not good thing to do.

> From: H Hartley Sweeten <hsweeten at visionengravers.com>
> 
> dma: ep93xx: check for spurious interrupts
> 
> The ep93xx dma controller generates spurious interrupts on dma1chan1 when
> used with the mmc_spi driver. Catch these early by making sure there is an
> interrupt to actually process.
> 
> Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>

Tested-by: Mika Westerberg <mika.westerberg at iki.fi>

Thanks for investigating this. You missed one thing though, see below.
Otherwise it doesn't compile :)

diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index e1cc87a..614bff4 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -751,7 +751,7 @@ static irqreturn_t ep93xx_dma_interrupt(int irq, void *dev_id)
 		return IRQ_NONE;
 	}
 
-	switch (edmac->edma->hw_interrupt(edmac)) {
+	switch (edmac->edma->hw_interrupt(edmac, irq_status)) {
 	case INTERRUPT_DONE:
 		desc->complete = true;
 		tasklet_schedule(&edmac->tasklet);


From khilman at ti.com  Thu Mar 22 16:49:35 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 22 Mar 2012 13:49:35 -0700
Subject: [GIT PULL] gpio/omap: more fixes for v3.4
Message-ID: <871uok5pk0.fsf@ti.com>

Hi Grant,

Please pull these OMAP GPIO fixes for v3.4.  These fix some rather
serious regressions introduced by the cleanup and runtime PM conversion
series which is also queued for v3.4.  This branch is based on your
gpio/next branch.

This version is functionally the same as the version you previously
merged (and I asked you to back it out), but this version has some
better changlogs, and I added reviewed-by and s-o-b from me as well.

Thanks,

Kevin



The following changes since commit 81b279d80a63628e580c71a31d30a8c3b3047ad4:

  gpio/davinci: fix enabling unbanked GPIO IRQs (2012-03-12 11:53:33 -0600)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/fixes/gpio-2

for you to fetch changes up to 7fcca715de3438b8fc3c8a144702f3a95c8ff63c:

  gpio/omap: fix redundant decoding of gpio offset (2012-03-21 10:21:24 +0530)

----------------------------------------------------------------
Tarun Kanti DebBarma (7):
      gpio/omap: fix wakeup_en register update in _set_gpio_wakeup()
      gpio/omap: fix trigger type to unsigned
      gpio/omap: fix _set_gpio_irqenable implementation
      gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg
      gpio/omap: fix incorrect context restore logic in omap_gpio_runtime_*
      gpio/omap: fix incorrect update to context.irqenable1
      gpio/omap: fix redundant decoding of gpio offset

 drivers/gpio/gpio-omap.c |   47 ++++++++++++++++++++++++----------------------
 1 file changed, 25 insertions(+), 22 deletions(-)


From vapier at gentoo.org  Thu Mar 22 16:53:13 2012
From: vapier at gentoo.org (Mike Frysinger)
Date: Thu, 22 Mar 2012 16:53:13 -0400
Subject: [PATCH] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <4F6B7226.8000102@wwwdotorg.org>
References: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
 <4F6B7226.8000102@wwwdotorg.org>
Message-ID: <201203221653.19268.vapier@gentoo.org>

On Thursday 22 March 2012 14:40:38 Stephen Warren wrote:
> On 03/16/2012 03:03 PM, Stephen Warren wrote:
> > All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
> > to avoid duplication.
> > 
> > All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
> > parameterized version in Makefile.lib to avoid duplication.
> 
> Does this change look reasonable? It has acks from people working on 4
> of the 7 affected architectures; would you prefer acks from all?

isn't that what linux-next is for ? ;)
-mike
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From akpm at linux-foundation.org  Thu Mar 22 17:21:06 2012
From: akpm at linux-foundation.org (Andrew Morton)
Date: Thu, 22 Mar 2012 14:21:06 -0700
Subject: [PATCH 07/16] mm/arm: use vm_flags_t for vma flags
In-Reply-To: <20120321065642.13852.95838.stgit@zurg>
References: <20120321065140.13852.52315.stgit@zurg>
 <20120321065642.13852.95838.stgit@zurg>
Message-ID: <20120322142106.3aa383a5.akpm@linux-foundation.org>

On Wed, 21 Mar 2012 10:56:42 +0400
Konstantin Khlebnikov <khlebnikov at openvz.org> wrote:

> Cast vm_flags to unsigned int for __cpuc_flush_user_range(),
> because its vm_flags argument declared as unsigned int.
> Asssembler code wants to test VM_EXEC bit on vma->vm_flags,
> but for big-endian we should get upper word for this.
> 
> ...
>
> --- a/arch/arm/include/asm/cacheflush.h
> +++ b/arch/arm/include/asm/cacheflush.h
> @@ -217,7 +217,7 @@ vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned
>  {
>  	if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
>  		__cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
> -					vma->vm_flags);
> +					(__force unsigned int)vma->vm_flags);
>  }

This won't work if a later version of __cpuc_flush_user_range() needs
access to newly-added flags in the upper 32 bits.

I guess we don't have to do anything about it at this stage, and that
if we do ever hit this problem, we'll need to put those newly-added
flags into the lower 32 bits of the vm_flags_t.


From hartleys at visionengravers.com  Thu Mar 22 17:36:51 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Thu, 22 Mar 2012 16:36:51 -0500
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <20120322200339.GA5812@mwesterb-mobl.ger.corp.intel.com>
References: <4F683B36.8090101@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>
 <20120321193231.GA3740@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48AB1@AUSP01VMBX24.collaborationhost.net>
 <20120322073750.GA637@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48CAF@AUSP01VMBX24.collaborationhost.net>
 <20120322200339.GA5812@mwesterb-mobl.ger.corp.intel.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020696D48D83@AUSP01VMBX24.collaborationhost.net>

On Thursday, March 22, 2012 1:04 PM, Mika Westerberg wrote:
> On Thu, Mar 22, 2012 at 01:52:52PM -0500, H Hartley Sweeten wrote:
>
>> I hacked this back to the handle_one_vic function. It looks like every time
>> I get the message above the stat read in that function shows an active
>> interrupt for DMAM2M0 (the dma rx channel) and DMAM2M1 (the dma
>> tx channel). Because of the way handle_one_vic processes the irq's, the
>> DMAM2M0 interrupt gets handled first. When it's done it must be clearing
>> the DMAM2M1 interrupt automatically for some reason. So, when it's
>> handled there is no interrupt pending so we get the message.
>> 
>> The "cleanest" fix I can think of is the following patch.  This is against
>> linux-next.
>
> I can't figure out any better fix unless we move ep93xx back to use
> !MULTI_IRQ_HANDLER which obviously is not good thing to do.

I agree.

>> From: H Hartley Sweeten <hsweeten at visionengravers.com>
>> 
>> dma: ep93xx: check for spurious interrupts
>> 
>> The ep93xx dma controller generates spurious interrupts on dma1chan1 when
>> used with the mmc_spi driver. Catch these early by making sure there is an
>> interrupt to actually process.
>> 
>> Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
>
> Tested-by: Mika Westerberg <mika.westerberg at iki.fi>
>
> Thanks for investigating this. You missed one thing though, see below.
> Otherwise it doesn't compile :)
>
> diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
> index e1cc87a..614bff4 100644
> --- a/drivers/dma/ep93xx_dma.c
> +++ b/drivers/dma/ep93xx_dma.c
> @@ -751,7 +751,7 @@ static irqreturn_t ep93xx_dma_interrupt(int irq, void *dev_id)
> 		return IRQ_NONE;
>  	}
>  
> -	switch (edmac->edma->hw_interrupt(edmac)) {
> +	switch (edmac->edma->hw_interrupt(edmac, irq_status)) {
> 	case INTERRUPT_DONE:
> 		desc->complete = true;
> 		tasklet_schedule(&edmac->tasklet);

Gah... Misstyped it when I created the patch.

I'll fix it and post a proper patch with your Tested-by.

Thanks,
Hartley



From daniel.lezcano at linaro.org  Thu Mar 22 17:45:03 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Thu, 22 Mar 2012 22:45:03 +0100
Subject: [RFC][PATCH 0/7] OMAP4 cpuidle cleanup
In-Reply-To: <87fwd07aaz.fsf@ti.com>
References: <1332322070-24577-1-git-send-email-daniel.lezcano@linaro.org>
 <4F69A872.50203@ti.com>
 <CAORVsuUeE046O7YJ_fE49NbW1OjZHZX+GuNiDkF0AnzBnSMbxA@mail.gmail.com>
 <4F6A04F3.6050306@linaro.org> <873991d3hs.fsf@ti.com>
 <4F6A5430.2090501@linaro.org> <87fwd07aaz.fsf@ti.com>
Message-ID: <4F6B9D5F.9040602@linaro.org>

On 03/22/2012 07:36 PM, Kevin Hilman wrote:
> Daniel Lezcano<daniel.lezcano at linaro.org>  writes:
>
>> On 03/21/2012 10:54 PM, Kevin Hilman wrote:
>>> Daniel Lezcano<daniel.lezcano at linaro.org>   writes:
>>>
>>>> On 03/21/2012 02:43 PM, Jean Pihet wrote:
>>>>> On Wed, Mar 21, 2012 at 11:07 AM, Santosh Shilimkar
>>>>> <santosh.shilimkar at ti.com>    wrote:
>>>>>> Daniel,
>>>>>>
>>>>>> On Wednesday 21 March 2012 02:57 PM, Daniel Lezcano wrote:
>>>>>>> This patchset is a proposition to improve a bit the code.
>>>>>>> The changes are code cleanup and does not change the behavior of the
>>>>>>> driver itself.
>>>>>>>
>>>>>>> A couple a things call my intention. Why the cpuidle device is set for cpu0 only
>>>>>>> and why the WFI is not used ?
>>>>>>>
>>>>>>> Daniel Lezcano (7):
>>>>>>>      ARM: OMAP4: cpuidle - Remove unused valid field
>>>>>>>      ARM: OMAP4: cpuidle - Declare the states with the driver declaration
>>>>>>>      ARM: OMAP4: cpuidle - Remove the cpuidle_params_table table
>>>>>>>      ARM: OMAP4: cpuidle - fix static omap4_idle_data declaration
>>>>>>>      ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile time
>>>>>>>      ARM: OMAP4: cpuidle - use the omap4_idle_data variable directly
>>>>>>>      ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot
>>>>>>>        time
>>>>>>>
>>>>>> The series looks fine to me in general. This clean-up is applicable
>>>>>> for OMAP3 cpuidle code as well.
>>>>> Great!
>>>>> However OMAP3 has a few specific things that cannot be removed as easily:
>>>>> - the 'valid' flag is used because only certain combinations of power
>>>>> domains states are possible,
>>>>
>>>> When I look the board-rx51 code I see:
>>>>
>>>> static struct cpuidle_params rx51_cpuidle_params[] = {
>>>> 	/* C1 */
>>>> 	{110 + 162, 5 , 1},
>>>> 	/* C2 */
>>>> 	{106 + 180, 309, 1},
>>>> 	/* C3 */
>>>> 	{107 + 410, 46057, 0},
>>>> 	/* C4 */
>>>> 	{121 + 3374, 46057, 0},
>>>> 	/* C5 */
>>>> 	{855 + 1146, 46057, 1},
>>>> 	/* C6 */
>>>> 	{7580 + 4134, 484329, 0},
>>>> 	/* C7 */
>>>> 	{7505 + 15274, 484329, 1},
>>>> };
>>>>
>>>> If C3, C4, C6 are not valid, so AFAICS never used in the cpuidle code
>>>> why the values are 'exit_latency' and 'target_residency' specified ? I
>>>> mean why don't we have { 0, 0, 0 } ? Is it just for information ?
>>>
>>> Yes, because getting those numbers were based on some board-specific
>>> measurements, and we don't want those values to be lost.  Also, some
>>> usage patterns might want to (re)enable those states.
>>
>> When you say re-enable you mean for a custom kernel ?
>
> Yes.
>
>>>> I understand the purpose of this code but it looks a bit tricky and
>>>> hard to factor out. Is it acceptable to create a new cpuidle driver
>>>> for rx51 then we factor out the code between omap3, omap4 and rx51
>>>> when all the code consistent ?
>>>
>>> I don't like that idea.  All the code is the same, the only thing we
>>> need is the ability to pass in board-specific latency numbers for the
>>> C-states.
>>
>> Sorry I was not clear, I was not saying duplicating the code. What I
>> meant is to create a driver:
>>
>> struct cpuidle_driver rx51_idle_driver = {
>>   	.name = 	"rx51_idle",
>> 	.owner = 	THIS_MODULE,
>> 	.states = {
>> 		{
>> 			/* What is in rx51_cpuidle_params */
>> 		}
>> 	};
>>
>> We put in there only the valid fields and we keep in a comment the
>> table with the latency numbers.
>
> Ah, OK.  I misunderstood.
>
>> Assuming the valid field is for handling the table overwritting, we
>> can then remove it. By this way, we simplify the next_valid_state
>> function.
>
> probably we can remove next_valid_state all together after 3.4 since the
> new sysfs entry for that feature looks to be queued in linux-next.

Oh, that could be very cool. That will remove a reasonable chunk of code.

>> Depending if we have rx51 or not, we register the rx51 driver or the
>> omap3 driver in the init function. That has also the benefit to group
>> the cpuidle code in the cpuidle34xx file.
>
> yes, but with board-specific data in SoC-specific code, which is not a
> clean separation IMO.  How would you plan to pass which board it's
> running on?

I was thinking using the same code path than the array overriding for 
cpuidle_data initialization. I did not looked at this initialization 
part in details neither the order.

>>> These latency numbers are obviously quite significant when it comes to
>>> the final power consumption, and these values often depend on
>>> board-specific settings.  Until there are generic frameworks for
>>> defining all the latencies involved, passing these values in from board
>>> files is absolutly needed.
>>
>> Yes but before creating the generic framework, we have to do a
>> transversal cpuidle consolidation across the SoC, factor out the code
>> when possible, and ensure the consistency between the different
>> platform and see a common pattern to emerge from this work.
>
> Agreed, but if that means ignoring platform-specific customization, and
> not putting in other mechanisms to configure platform specific details,
> it is throwing away useful infrastructure.

Yes, I agree.

> IMO, any consolidated framework needs some way to customize or pass in
> latencies from platform-specific code.  Long term, I suppose this needs
> to be DT based.

A random thought here. What do you think if we can write the latencies 
from the userspace via sysfs ? At present, the 'latency' file is 
read-only, may be we can add the exit_latency and make them both 
writable. That will have the benefit of letting the userspace to tweak 
that depending of the board without recompiling a new kernel and also 
help to debug/improve without rebooting the host, no ?

> That being said, I do want to see this consolidation happen, so...
>
> In OMAP land, we are in the middle of putting in place a better
> framework for defining/tracking the various latencies involved in PM
> transitions (using per-device PM Qos.) After that, we will likely be
> reworking and revalidating these latency numbers for all OMAPs
>
> So maybe the best approach to help in consolidation is just to drop the
> board-rx51 data all together for now, as well as the ability to pass
> custom C states from board files.

Good. If this is acceptable then that will simplify the consolidation.

> The default, unoptimized OMAP3 numbers will work fine for that board,
> and anyone wanting to do optimized power work for that platform can
> still do it with a custom kernel.  (There is still lots of out of tree
> work for the n900 that never made it upstream, so I doubt the mainline
> users of n900 will be affected by this level of power tweaking.)
>
> If we do that, then as part of the consolidation effort, some DT-based
> customization should be defined as well to override/customize C states.

Ok, I will give a try by removing the rx51 specific cpuidle data. Then I 
will be able to do similar changes than OMAP4 for OMAP3.

Thanks Kevin

   -- Daniel


-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From matt at grid-net.com  Thu Mar 22 19:05:01 2012
From: matt at grid-net.com (Matt Burtch)
Date: Thu, 22 Mar 2012 16:05:01 -0700
Subject: [PATCH 1/1] ARM iMX28: incorrect frac/div calculation
Message-ID: <1332457501-8153-1-git-send-email-matt@grid-net.com>

The frac and div values in _CLK_SET_RATE are calculated incorrectly
for some clock rates ie. CPU clk of 454.73MHz, 392.72MHz, 261.81Mhz,
etc.

Now the frac and div values which result in the closest actual clock
rate to that requested is selected.  Also there are no limitations
on what frac values can be used, as long as they fall in the valid
(18 < frac < 35) range.

Tested on custom iMX28 board.

Signed-off-by: Matt Burtch <matt at grid-net.com>
---
 arch/arm/mach-mxs/clock-mx28.c |    8 ++------
 1 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5d68e41..a058b99 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -354,19 +354,15 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
 		}							\
 		for (d = 1; d <= div_max; d++) {			\
 			f = parent_rate * 18 / d / rate;		\
-			if ((parent_rate * 18 / d) % rate)		\
-				f++;					\
 			if (f < 18 || f > 35)				\
 				continue;				\
 									\
 			calc_rate = parent_rate * 18 / f / d;		\
-			if (calc_rate > rate)				\
-				continue;				\
 									\
-			if (rate - calc_rate < diff) {			\
+			if (abs(rate - calc_rate) < diff) {		\
 				frac = f;				\
 				div = d;				\
-				diff = rate - calc_rate;		\
+				diff = abs(rate - calc_rate);		\
 			}						\
 									\
 			if (diff == 0)					\
-- 
1.7.5.4



From khilman at ti.com  Thu Mar 22 19:09:07 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 22 Mar 2012 16:09:07 -0700
Subject: [PATCH v4 RESEND 6/7] gpio/omap: fix incorrect update to
 context.irqenable1
In-Reply-To: <1332393130-10636-1-git-send-email-tarun.kanti@ti.com> (Tarun
 Kanti DebBarma's message of "Thu, 22 Mar 2012 10:42:09 +0530")
References: <1332393130-10636-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <87vclw44j0.fsf@ti.com>

Tarun Kanti DebBarma <tarun.kanti at ti.com> writes:

> In _enable_gpio_irqbank() when bank->regs->set_irqenable is TRUE,
> gpio_mask can be directly set by writing to set_irqenable register
> without overwriting current value. In order to ensure the same is
> stored in context.irqenable1, we must avoid overwriting it with
> gpio_mask at the end of the function. Instead, update irqenable1
> appropriately by OR'ing with gpio_mask.
> For the case where bank->regs->set_irqenable is FALSE, irqenable1
> can be directly overwritten with 'l' which holds correct computed
> value.
>
>         if (bank->regs->set_irqenable) {
>                 reg += bank->regs->set_irqenable;
>                 l = gpio_mask;
>         } else {
>                 reg += bank->regs->irqenable;
>                 l = __raw_readl(reg);
>                 if (bank->regs->irqenable_inv)
>                         l &= ~gpio_mask;
>                 else
>                         l |= gpio_mask;
>         }
>
> Make similar change for _disable_gpio_irqbank().
>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> ---
> Updated change log as per Kevin's suggestion.


Thanks for the update.  I've queued the updated version of this series,
and sent pull request to Grant.

Thanks Tarun,

Kevin



From khilman at ti.com  Thu Mar 22 19:12:21 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 22 Mar 2012 16:12:21 -0700
Subject: [PATCH] ARM: OMAP3+: fix oops triggered in
 omap_prcm_register_chain_handler(v1)
In-Reply-To: <1332379417-7408-1-git-send-email-tom.leiming@gmail.com> (Ming
 Lei's message of "Thu, 22 Mar 2012 09:23:37 +0800")
References: <1332379417-7408-1-git-send-email-tom.leiming@gmail.com>
Message-ID: <87mx7844dm.fsf@ti.com>

Ming Lei <tom.leiming at gmail.com> writes:

> This patch fixes the oops below[1].
>
> Obviously, the count of "struct irq_chip_generic" instances to be
> allocated and setup should be irq_setup->nr_regs instead of
> irq_setup->nr_regs plus one, so just fix the iterator to avoid
> the oops. 

[...]

> ---
> v1:
> 	-add a bit more description to the changelog as suggested by
> 	Tero and Kevin.

Thanks for the updated version.

Queuing as a fix for v3.4-rc (branch: for_3.4/fixes/pm)

Kevin


From paul at pwsan.com  Thu Mar 22 19:40:50 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 22 Mar 2012 17:40:50 -0600 (MDT)
Subject: [PATCH 0/3] OMAP2+: UART: Enable tx wakeup + remove cpu checks
In-Reply-To: <CAMrsUdLtC0iVk2qDDDXj2tteAzP5UQJXNvsCoJLEC9Yty2QjvQ@mail.gmail.com>
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
 <87limurpsx.fsf@ti.com>
 <CAMrsUdLtC0iVk2qDDDXj2tteAzP5UQJXNvsCoJLEC9Yty2QjvQ@mail.gmail.com>
Message-ID: <alpine.DEB.2.00.1203221740140.24425@utopia.booyaka.com>

Hi

On Thu, 22 Mar 2012, Raja, Govindraj wrote:

> Sorry I for got to add that, here are details on what was tested.
> 
> 1.) OMAP2430 SDP : Boot tested with uart1 as console.
> 
> 2.) OMAP3430 SDP: Boot test, suspend/resume tests, retention off mode
>                                (checking retention and off mode count
> in cpu idle cases)
> 
> 3.) OMAP3630 - Beagle XM:  Boot test, suspend/resume tests, retention off mode
>                                             (checking retention and
> off mode count in cpu idle cases)
> 
> 4.) OMAP4430 - PANDA: Boot test, suspend/resume tests
> 
> 5.) OMAP4460 - PANDA: Boot test.

What kernel .config was used for these tests?


- Paul


From alexgershgorin at gmail.com  Thu Mar 22 19:52:14 2012
From: alexgershgorin at gmail.com (Alex)
Date: Fri, 23 Mar 2012 01:52:14 +0200
Subject: [PATCH] regulator: i.MX35-PDK Add regulator support
Message-ID: <1332460334-11173-1-git-send-email-alexg@meprolight.com>

This patch register MC13892 PMIC which connected
via I2C bus and allow set the voltage domains
and constraints for each regulator.

Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
---
This patch is based on the following patches from Marc Reilly:
[PATCH v4 1/4] mfd: mc13xxx-core: Prepare for separate spi and i2c backends.
[PATCH v4 2/4] mfd: mc13xxx-core: use regmap for register access.
[PATCH v4 3/4] mfd: mc13xxx-core: Move spi specific code into separate module.
[PATCH v4 4/4] mfd: mc13xxx: Add i2c driver
---
 arch/arm/mach-imx/mach-mx35_3ds.c |  212 ++++++++++++++++++++++++++++++++++++-
 1 files changed, 211 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c..3096335 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -29,6 +29,8 @@
 #include <linux/usb/otg.h>
 
 #include <linux/mtd/physmap.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -43,6 +45,7 @@
 
 #include "devices-imx35.h"
 
+#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
 #define EXPIO_PARENT_INT	gpio_to_irq(IMX_GPIO_NR(1, 1))
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -55,7 +58,7 @@ static struct physmap_flash_data mx35pdk_flash_data = {
 
 static struct resource mx35pdk_flash_resource = {
 	.start	= MX35_CS0_BASE_ADDR,
-	.end	= MX35_CS0_BASE_ADDR + SZ_64M - 1,
+	.end    = MX35_CS0_BASE_ADDR + SZ_64M - 1,
 	.flags	= IORESOURCE_MEM,
 };
 
@@ -120,8 +123,214 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
 	/* I2C1 */
 	MX35_PAD_I2C1_CLK__I2C1_SCL,
 	MX35_PAD_I2C1_DAT__I2C1_SDA,
+	/*PMIC IRQ*/
+	MX35_PAD_GPIO2_0__GPIO2_0,
 };
 
+static struct regulator_init_data sw1_init = {
+	.constraints = {
+		.name = "SW1",
+		.min_uV = 600000,
+		.max_uV = 1375000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.valid_modes_mask = 0,
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data sw2_init = {
+	.constraints = {
+		.name = "SW2",
+		.min_uV = 900000,
+		.max_uV = 1850000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data sw3_init = {
+	.constraints = {
+		.name = "SW3",
+		.min_uV = 1100000,
+		.max_uV = 1850000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data sw4_init = {
+	.constraints = {
+		.name = "SW4",
+		.min_uV = 1100000,
+		.max_uV = 1850000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data viohi_init = {
+	.constraints = {
+		.name = "VIOHI",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vusb_init = {
+	.constraints = {
+		.name = "VUSB",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vdig_init = {
+	.constraints = {
+		.name = "VDIG",
+		.min_uV = 1050000,
+		.max_uV = 1800000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vpll_init = {
+	.constraints = {
+		.name = "VPLL",
+		.min_uV = 1050000,
+		.max_uV = 1800000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vusb2_init = {
+	.constraints = {
+		.name = "VUSB2",
+		.min_uV = 2400000,
+		.max_uV = 2775000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vvideo_init = {
+	.constraints = {
+		.name = "VVIDEO",
+		.min_uV = 2500000,
+		.max_uV = 2775000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1
+	}
+};
+
+static struct regulator_init_data vaudio_init = {
+	.constraints = {
+		.name = "VAUDIO",
+		.min_uV = 2300000,
+		.max_uV = 3000000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1
+	}
+};
+
+static struct regulator_init_data vsd_init = {
+	.constraints = {
+		.name = "VSD",
+		.min_uV = 1800000,
+		.max_uV = 3150000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	}
+};
+
+static struct regulator_init_data vcam_init = {
+	.constraints = {
+		.name = "VCAM",
+		.min_uV = 2500000,
+		.max_uV = 3000000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+					REGULATOR_CHANGE_MODE,
+		.valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
+		.boot_on = 1
+	},
+};
+
+static struct regulator_init_data vgen1_init = {
+	.constraints = {
+		.name = "VGEN1",
+		.min_uV = 1200000,
+		.max_uV = 3150000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	}
+};
+
+static struct regulator_init_data vgen2_init = {
+	.constraints = {
+		.name = "VGEN2",
+		.min_uV = 1200000,
+		.max_uV = 3150000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vgen3_init = {
+	.constraints = {
+		.name = "VGEN3",
+		.min_uV = 1800000,
+		.max_uV = 2900000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	}
+};
+
+static struct mc13xxx_regulator_init_data mx35_3ds_regulators[] = {
+	{ .id = MC13892_SW1, .init_data = &sw1_init },
+	{ .id = MC13892_SW2, .init_data = &sw2_init },
+	{ .id = MC13892_SW3, .init_data = &sw3_init },
+	{ .id = MC13892_SW4, .init_data = &sw4_init },
+	{ .id = MC13892_VIOHI, .init_data = &viohi_init },
+	{ .id = MC13892_VPLL, .init_data = &vpll_init },
+	{ .id = MC13892_VDIG, .init_data = &vdig_init },
+	{ .id = MC13892_VSD, .init_data = &vsd_init },
+	{ .id = MC13892_VUSB2, .init_data = &vusb2_init },
+	{ .id = MC13892_VVIDEO, .init_data = &vvideo_init },
+	{ .id = MC13892_VAUDIO, .init_data = &vaudio_init },
+	{ .id = MC13892_VCAM, .init_data = &vcam_init },
+	{ .id = MC13892_VGEN1, .init_data = &vgen1_init },
+	{ .id = MC13892_VGEN2, .init_data = &vgen2_init },
+	{ .id = MC13892_VGEN3, .init_data = &vgen3_init },
+	{ .id = MC13892_VUSB, .init_data = &vusb_init },
+};
+
+static struct mc13xxx_platform_data mx35_3ds_mc13892_data = {
+	.flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
+	.regulators = {
+		.num_regulators = ARRAY_SIZE(mx35_3ds_regulators),
+		.regulators = mx35_3ds_regulators,
+	},
+};
+
+static struct i2c_board_info mx35_3ds_i2c_mc13892 = {
+
+	I2C_BOARD_INFO("mc13892", 0x08),
+	.platform_data = &mx35_3ds_mc13892_data,
+	.irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
+};
+
+static void __init imx35_3ds_init_mc13892(void)
+{
+	int ret = gpio_request_one(GPIO_PMIC_INT, GPIOF_DIR_IN, "pmic irq");
+
+	if (ret) {
+		pr_err("failed to get pmic irq: %d\n", ret);
+		return;
+	}
+
+	i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1);
+}
+
 static int mx35_3ds_otg_init(struct platform_device *pdev)
 {
 	return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
@@ -204,6 +413,7 @@ static void __init mx35_3ds_init(void)
 		pr_warn("Init of the debugboard failed, all "
 				"devices on the debugboard are unusable.\n");
 	imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+	imx35_3ds_init_mc13892();
 }
 
 static void __init mx35pdk_timer_init(void)
-- 
1.7.1



From hartleys at visionengravers.com  Thu Mar 22 19:56:30 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Thu, 22 Mar 2012 18:56:30 -0500
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <20120322200339.GA5812@mwesterb-mobl.ger.corp.intel.com>
References: <4F683B36.8090101@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>
 <20120321193231.GA3740@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48AB1@AUSP01VMBX24.collaborationhost.net>
 <20120322073750.GA637@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48CAF@AUSP01VMBX24.collaborationhost.net>
 <20120322200339.GA5812@mwesterb-mobl.ger.corp.intel.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020696D48E1A@AUSP01VMBX24.collaborationhost.net>

On Thursday, March 22, 2012 1:04 PM, Mika Westerberg wrote:
> On Thu, Mar 22, 2012 at 01:52:52PM -0500, H Hartley Sweeten wrote:
>
>> I hacked this back to the handle_one_vic function. It looks like every time
>> I get the message above the stat read in that function shows an active
>> interrupt for DMAM2M0 (the dma rx channel) and DMAM2M1 (the dma
>> tx channel). Because of the way handle_one_vic processes the irq's, the
>> DMAM2M0 interrupt gets handled first. When it's done it must be clearing
>> the DMAM2M1 interrupt automatically for some reason. So, when it's
>> handled there is no interrupt pending so we get the message.
>> 
>> The "cleanest" fix I can think of is the following patch.  This is against
>> linux-next.
>
> I can't figure out any better fix unless we move ep93xx back to use
> !MULTI_IRQ_HANDLER which obviously is not good thing to do.

Mika,

I wonder if the spurious interrupts were the real problem behind what
was causing the Oops that prompted your patch:

dma/ep93xx_dma: prevent ep93xx_dma_tasklet() to reference an empty list

???

Hartley



From jonsmirl at gmail.com  Thu Mar 22 20:23:58 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Thu, 22 Mar 2012 20:23:58 -0400
Subject: ioremap to a specific virtual address
Message-ID: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>

When iotable is used to initially map memory you can specify the
mapping address. In this case IO_SDMMC_PHYS is 0x18000000 and it gets
mapped to  0xf1800000

NXP has supplied this handly macro
#define io_p2v(x) (0xf0000000 | (((x) & 0xff000000) >> 4) | ((x) & 0x000fffff))

iotable_init(lpc313x_io_desc, ARRAY_SIZE(lpc313x_io_desc));

	{
		.virtual	= io_p2v(IO_SDMMC_PHYS),
		.pfn		= __phys_to_pfn(IO_SDMMC_PHYS),
		.length		= IO_SDMMC_SIZE,
		.type		= MT_DEVICE
	},

The supplied kernel is full of code that uses this type of addressing.
It has macros for register definition that all depend on the registers
being mapped to a well know location - io_p2v(x).

I'd like to move the map out of the core code and into the SDMMC
device driver and then only do it if the driver loads.  Is there some
way to ioremap to a specific address on ARM? Or is there another way
to build the mapping in the driver?

-- 
Jon Smirl
jonsmirl at gmail.com


From rusty at rustcorp.com.au  Thu Mar 22 20:32:12 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 23 Mar 2012 11:02:12 +1030
Subject: [PATCH] ARM: test for PMU feature on v7.
References: <4F590411.9060201@arm.com>
Message-ID: <87ty1g88dv.fsf@rustcorp.com.au>

The v7 ARM (B4.1.82) specifies that bits 27-24 of the ID_DFR0 reg show
what performance monitoring (if any) is available.  We should test this
before assuming (useful for inside virtualized environments, for example).

Signed-off-by: Rusty Russell <rusty.russell at linaro.org>

diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 6933244..303d1e1 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1108,6 +1108,12 @@ static struct arm_pmu armv7pmu = {
 	.max_period		= (1LLU << 32) - 1,
 };
 
+static bool armv7_pmu_avail(void)
+{
+	/* 0 means unknown (maybe v1), 1 means v2, 2 means v2, 15 means none */
+	return ((read_cpuid_ext(CPUID_EXT_DFR0) >> 24) & 0xF) != 0xF;
+}
+
 static u32 __init armv7_read_num_pmnc_events(void)
 {
 	u32 nb_cnt;
@@ -1121,6 +1127,8 @@ static u32 __init armv7_read_num_pmnc_events(void)
 
 static struct arm_pmu *__init armv7_a8_pmu_init(void)
 {
+	if (!armv7_pmu_avail())
+		return NULL;
 	armv7pmu.id		= ARM_PERF_PMU_ID_CA8;
 	armv7pmu.name		= "ARMv7 Cortex-A8";
 	armv7pmu.map_event	= armv7_a8_map_event;
@@ -1130,6 +1138,8 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a9_pmu_init(void)
 {
+	if (!armv7_pmu_avail())
+		return NULL;
 	armv7pmu.id		= ARM_PERF_PMU_ID_CA9;
 	armv7pmu.name		= "ARMv7 Cortex-A9";
 	armv7pmu.map_event	= armv7_a9_map_event;
@@ -1139,6 +1149,8 @@ static struct arm_pmu *__init armv7_a9_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a5_pmu_init(void)
 {
+	if (!armv7_pmu_avail())
+		return NULL;
 	armv7pmu.id		= ARM_PERF_PMU_ID_CA5;
 	armv7pmu.name		= "ARMv7 Cortex-A5";
 	armv7pmu.map_event	= armv7_a5_map_event;
@@ -1148,6 +1160,8 @@ static struct arm_pmu *__init armv7_a5_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a15_pmu_init(void)
 {
+	if (!armv7_pmu_avail())
+		return NULL;
 	armv7pmu.id		= ARM_PERF_PMU_ID_CA15;
 	armv7pmu.name		= "ARMv7 Cortex-A15";
 	armv7pmu.map_event	= armv7_a15_map_event;


From rusty at rustcorp.com.au  Thu Mar 22 20:34:57 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Fri, 23 Mar 2012 11:04:57 +1030
Subject: [PATCH] ARM: test for PMU feature on v7 (v2 with typo fix)
In-Reply-To: <87ty1g88dv.fsf@rustcorp.com.au>
References: <4F590411.9060201@arm.com> <87ty1g88dv.fsf@rustcorp.com.au>
Message-ID: <87r4wk889a.fsf@rustcorp.com.au>

The v7 ARM (B4.1.82) specifies that bits 27-24 of the ID_DFR0 reg show
what performance monitoring (if any) is available.  We should test this
before assuming (useful for inside virtualized environments, for example).

Signed-off-by: Rusty Russell <rusty.russell at linaro.org>

diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 6933244..303d1e1 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1108,6 +1108,12 @@ static struct arm_pmu armv7pmu = {
 	.max_period		= (1LLU << 32) - 1,
 };
 
+static bool armv7_pmu_avail(void)
+{
+	/* 0 means unknown (maybe v1), 1 means v1, 2 means v2, 15 means none */
+	return ((read_cpuid_ext(CPUID_EXT_DFR0) >> 24) & 0xF) != 0xF;
+}
+
 static u32 __init armv7_read_num_pmnc_events(void)
 {
 	u32 nb_cnt;
@@ -1121,6 +1127,8 @@ static u32 __init armv7_read_num_pmnc_events(void)
 
 static struct arm_pmu *__init armv7_a8_pmu_init(void)
 {
+	if (!armv7_pmu_avail())
+		return NULL;
 	armv7pmu.id		= ARM_PERF_PMU_ID_CA8;
 	armv7pmu.name		= "ARMv7 Cortex-A8";
 	armv7pmu.map_event	= armv7_a8_map_event;
@@ -1130,6 +1138,8 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a9_pmu_init(void)
 {
+	if (!armv7_pmu_avail())
+		return NULL;
 	armv7pmu.id		= ARM_PERF_PMU_ID_CA9;
 	armv7pmu.name		= "ARMv7 Cortex-A9";
 	armv7pmu.map_event	= armv7_a9_map_event;
@@ -1139,6 +1149,8 @@ static struct arm_pmu *__init armv7_a9_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a5_pmu_init(void)
 {
+	if (!armv7_pmu_avail())
+		return NULL;
 	armv7pmu.id		= ARM_PERF_PMU_ID_CA5;
 	armv7pmu.name		= "ARMv7 Cortex-A5";
 	armv7pmu.map_event	= armv7_a5_map_event;
@@ -1148,6 +1160,8 @@ static struct arm_pmu *__init armv7_a5_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a15_pmu_init(void)
 {
+	if (!armv7_pmu_avail())
+		return NULL;
 	armv7pmu.id		= ARM_PERF_PMU_ID_CA15;
 	armv7pmu.name		= "ARMv7 Cortex-A15";
 	armv7pmu.map_event	= armv7_a15_map_event;


From festevam at gmail.com  Thu Mar 22 20:47:02 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Thu, 22 Mar 2012 21:47:02 -0300
Subject: [PATCH v1] i.MX35-PDK: Add Camera support
In-Reply-To: <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD0B@MEP-EXCH.meprolight.com>
References: <1331651129-30540-1-git-send-email-alexg@meprolight.com>
 <4F67AD31.8030500@redhat.com> <4F67B077.5050300@redhat.com>
 <20120319223729.GC3852@pengutronix.de>
 <CAOMZO5B=Qpng68xLmxGaHMqSmYzbkpObVcjHDQSXaXcz5s6gMQ@mail.gmail.com>
 <20120319224550.GF3852@pengutronix.de>
 <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD0B@MEP-EXCH.meprolight.com>
Message-ID: <CAOMZO5BhRbjP2hojQQPgNjsyt3hKTz5FSmCDwsgERDi8srZ78w@mail.gmail.com>

Hi Alex,

On Tue, Mar 20, 2012 at 5:54 AM, Alex Gershgorin <alexg at meprolight.com> wrote:
>
> Hi all,
>
> Good news...
> After several number of changes, yesterday the camera started to work :-)
> I will prepare some patches and send them.

Ok, great! Besides your mx35 clock patches: any other patch is
required to getting the camera to work?

Are you getting the camera image with the correct colors?

Thanks,

Fabio Estevam


From hartleys at visionengravers.com  Thu Mar 22 22:19:10 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Thu, 22 Mar 2012 21:19:10 -0500
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <20120321193836.GC3740@mwesterb-mobl.ger.corp.intel.com>
References: <4F683B36.8090101@metasoft.pl>
 <20120321193836.GC3740@mwesterb-mobl.ger.corp.intel.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020696D48E3E@AUSP01VMBX24.collaborationhost.net>

On Wednesday, March 21, 2012 12:39 PM, Mika Westerberg wrote:
> On Tue, Mar 20, 2012 at 09:09:26AM +0100, Rafal Prylowski wrote:
>> Implement double buffering for M2M DMA channels.
>> 
>> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
>
> The subject line prefix should probably be 'dmaengine/ep93xx_dma: ' but
> otherwise this looks good.
>
> Acked-by: Mika Westerberg <mika.westerberg at iki.fi>

Mika,

Did you test this patch or just review it?

On my system it doesn't work. I think it has something to do with the
changes to m2m_hw_interrupt but I haven't tracked it down yet.

It looks like what's missing is a:

	edmac->edma->hw_submit(edmac);

But, maybe that's not needed with double buffering?

Regards,
Hartley




From marc at cpdesign.com.au  Thu Mar 22 21:23:09 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Fri, 23 Mar 2012 12:23:09 +1100
Subject: [PATCH] regulator: i.MX35-PDK Add regulator support
In-Reply-To: <1332460334-11173-1-git-send-email-alexg@meprolight.com>
References: <1332460334-11173-1-git-send-email-alexg@meprolight.com>
Message-ID: <201203231223.10043.marc@cpdesign.com.au>

Hi,

I'm not very experienced with the regulator driver, but noticed a couple of 
minor things with your patch..

<snip>

> 
>  static const struct imxuart_platform_data uart_pdata __initconst = {
> @@ -55,7 +58,7 @@ static struct physmap_flash_data mx35pdk_flash_data = {
> 
>  static struct resource mx35pdk_flash_resource = {
>  	.start	= MX35_CS0_BASE_ADDR,
> -	.end	= MX35_CS0_BASE_ADDR + SZ_64M - 1,
> +	.end    = MX35_CS0_BASE_ADDR + SZ_64M - 1,

did you mean to change this?

>  	.flags	= IORESOURCE_MEM,
>  };
> 
> @@ -120,8 +123,214 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
>  	/* I2C1 */
>  	MX35_PAD_I2C1_CLK__I2C1_SCL,
>  	MX35_PAD_I2C1_DAT__I2C1_SDA,
> +	/*PMIC IRQ*/
> +	MX35_PAD_GPIO2_0__GPIO2_0,
>  };
> 
> +static struct regulator_init_data sw1_init = {
> +	.constraints = {
> +		.name = "SW1",
> +		.min_uV = 600000,
> +		.max_uV = 1375000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +		.valid_modes_mask = 0,
> +		.always_on = 1,
> +		.boot_on = 1,
> +	}
> +};
> +
> +static struct regulator_init_data sw2_init = {
> +	.constraints = {
> +		.name = "SW2",
> +		.min_uV = 900000,
> +		.max_uV = 1850000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +		.always_on = 1,
> +		.boot_on = 1,
> +	}
> +};
> +
> +static struct regulator_init_data sw3_init = {
> +	.constraints = {
> +		.name = "SW3",
> +		.min_uV = 1100000,
> +		.max_uV = 1850000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +		.always_on = 1,
> +		.boot_on = 1,
> +	}
> +};
> +
> +static struct regulator_init_data sw4_init = {
> +	.constraints = {
> +		.name = "SW4",
> +		.min_uV = 1100000,
> +		.max_uV = 1850000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +		.always_on = 1,
> +		.boot_on = 1,
> +	}
> +};
> +
> +static struct regulator_init_data viohi_init = {
> +	.constraints = {
> +		.name = "VIOHI",
> +		.boot_on = 1,
> +	}
> +};
> +
> +static struct regulator_init_data vusb_init = {
> +	.constraints = {
> +		.name = "VUSB",
> +		.boot_on = 1,
> +	}
> +};
> +
> +static struct regulator_init_data vdig_init = {
> +	.constraints = {
> +		.name = "VDIG",
> +		.min_uV = 1050000,
> +		.max_uV = 1800000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +		.boot_on = 1,
> +	}
> +};
> +
> +static struct regulator_init_data vpll_init = {
> +	.constraints = {
> +		.name = "VPLL",
> +		.min_uV = 1050000,
> +		.max_uV = 1800000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +		.boot_on = 1,
> +	}
> +};
> +
> +static struct regulator_init_data vusb2_init = {
> +	.constraints = {
> +		.name = "VUSB2",
> +		.min_uV = 2400000,
> +		.max_uV = 2775000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +		.boot_on = 1,
> +	}
> +};
> +
> +static struct regulator_init_data vvideo_init = {
> +	.constraints = {
> +		.name = "VVIDEO",
> +		.min_uV = 2500000,
> +		.max_uV = 2775000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +		.boot_on = 1
> +	}
> +};
> +
> +static struct regulator_init_data vaudio_init = {
> +	.constraints = {
> +		.name = "VAUDIO",
> +		.min_uV = 2300000,
> +		.max_uV = 3000000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +		.boot_on = 1
> +	}
> +};
> +
> +static struct regulator_init_data vsd_init = {
> +	.constraints = {
> +		.name = "VSD",
> +		.min_uV = 1800000,
> +		.max_uV = 3150000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +	}
> +};

I think this is on at power up too (for imx35)

Cheers,
Marc


From shawn.guo at linaro.org  Thu Mar 22 22:52:11 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 23 Mar 2012 10:52:11 +0800
Subject: [PATCH 1/1] ARM iMX28: incorrect frac/div calculation
In-Reply-To: <1332457501-8153-1-git-send-email-matt@grid-net.com>
References: <1332457501-8153-1-git-send-email-matt@grid-net.com>
Message-ID: <20120323025208.GG2213@S2101-09.ap.freescale.net>

On Thu, Mar 22, 2012 at 04:05:01PM -0700, Matt Burtch wrote:
> The frac and div values in _CLK_SET_RATE are calculated incorrectly
> for some clock rates ie. CPU clk of 454.73MHz, 392.72MHz, 261.81Mhz,
> etc.
> 
> Now the frac and div values which result in the closest actual clock
> rate to that requested is selected.

My understanding on clk_set_rate is we need to set the clk to a rate
closest to the requested one but never exceeding it.  Does your change
ensure that?

Regards,
Shawn

> Also there are no limitations
> on what frac values can be used, as long as they fall in the valid
> (18 < frac < 35) range.
> 
> Tested on custom iMX28 board.
> 
> Signed-off-by: Matt Burtch <matt at grid-net.com>
> ---
>  arch/arm/mach-mxs/clock-mx28.c |    8 ++------
>  1 files changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
> index 5d68e41..a058b99 100644
> --- a/arch/arm/mach-mxs/clock-mx28.c
> +++ b/arch/arm/mach-mxs/clock-mx28.c
> @@ -354,19 +354,15 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
>  		}							\
>  		for (d = 1; d <= div_max; d++) {			\
>  			f = parent_rate * 18 / d / rate;		\
> -			if ((parent_rate * 18 / d) % rate)		\
> -				f++;					\
>  			if (f < 18 || f > 35)				\
>  				continue;				\
>  									\
>  			calc_rate = parent_rate * 18 / f / d;		\
> -			if (calc_rate > rate)				\
> -				continue;				\
>  									\
> -			if (rate - calc_rate < diff) {			\
> +			if (abs(rate - calc_rate) < diff) {		\
>  				frac = f;				\
>  				div = d;				\
> -				diff = rate - calc_rate;		\
> +				diff = abs(rate - calc_rate);		\
>  			}						\
>  									\
>  			if (diff == 0)					\
> -- 
> 1.7.5.4
> 


From viresh.kumar at st.com  Thu Mar 22 23:29:28 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 23 Mar 2012 08:59:28 +0530
Subject: [PATCH] ARM: SPEAr600: Change FSMC and SMI clock names
In-Reply-To: <1332420073-17703-1-git-send-email-sr@denx.de>
References: <1332420073-17703-1-git-send-email-sr@denx.de>
Message-ID: <4F6BEE18.1080209@st.com>

On 3/22/2012 6:11 PM, Stefan Roese wrote:
> Change FSMC and SMI clock names to match the ones needed for DT based
> probing.
> 

please keep spear-devel at list.st.com in cc. :)

> Signed-off-by: Stefan Roese <sr at denx.de>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> ---
>  arch/arm/mach-spear6xx/clock.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
> index a86499a..f051804 100644
> --- a/arch/arm/mach-spear6xx/clock.c
> +++ b/arch/arm/mach-spear6xx/clock.c
> @@ -660,8 +660,8 @@ static struct clk_lookup spear_clk_lookups[] = {
>  	{ .dev_id = "dma",		.clk = &dma_clk},
>  	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
>  	{ .dev_id = "gmac",		.clk = &gmac_clk},
> -	{ .dev_id = "smi",		.clk = &smi_clk},
> -	{ .dev_id = "fsmc-nand",	.clk = &fsmc_clk},
> +	{ .dev_id = "fc000000.flash",	.clk = &smi_clk},
> +	{ .dev_id = "d1800000.flash",	.clk = &fsmc_clk},
>  	/* clock derived from apb clk */
>  	{ .dev_id = "adc",		.clk = &adc_clk},
>  	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},

Acked-by: Viresh Kumar <viresh.kumar at st.com>

@Arnd: I would start to apply these patches on my git tree from now
onwards and will send you pull request later.

-- 
viresh


From viresh.linux at gmail.com  Thu Mar 22 23:39:16 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Fri, 23 Mar 2012 09:09:16 +0530
Subject: [PATCH] serial: PL011: move interrupt clearing
In-Reply-To: <CACRpkdate+sQJvS8H7qNXiwe6c+F58g=OF0Qg=TxxnTwPXBrYQ@mail.gmail.com>
References: <1332357318-8017-1-git-send-email-linus.walleij@linaro.org>
 <CAOh2x==5QHEcA3h216p8rJukx0LR=cVcGYN84aqzw=fnhu8Y-g@mail.gmail.com>
 <CACRpkdate+sQJvS8H7qNXiwe6c+F58g=OF0Qg=TxxnTwPXBrYQ@mail.gmail.com>
Message-ID: <CAOh2x=kqTZxzyEMEF0bYFQ0a0zMEQNZWrzw48e1WFiMxYpRSeg@mail.gmail.com>

On Thu, Mar 22, 2012 at 1:30 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> On Thu, Mar 22, 2012 at 2:04 AM, viresh kumar <viresh.linux at gmail.com> wrote:
>> You missed me in CC??
>
> I put you in Reported-by, then used --cc at the prompt because git send-email
> still does not realize it must put Reported-by: tags on the CC list.

That's strange. When i check my mail on @st.com id, i see myself in cc
list, but on
gmail i see following cc list in your first mail.

linux-serial at vger.kernel.org, Greg Kroah-Hartman
<gregkh at linuxfoundation.org>, Russell King <linux at arm.linux.org.uk>,
Jong-Sung Kim <neidhard.kim at lge.com>, stable <stable at vger.kernel.org>,
Chanho Min <chanho0207 at gmail.com>,
linux-arm-kernel at lists.infradead.org, Shreshtha Kumar Sahu
<shreshthakumar.sahu at stericsson.com>

Why don't i see myself in cc here?

I have seen similar issues earlier too, with our ST internal and
Mainline mailing lists.
Any ideas?

--
viresh


From jonsmirl at gmail.com  Fri Mar 23 00:17:18 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Fri, 23 Mar 2012 00:17:18 -0400
Subject: ioremap to a specific virtual address
In-Reply-To: <alpine.LFD.2.02.1203222348210.24151@xanadu.home>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <alpine.LFD.2.02.1203222348210.24151@xanadu.home>
Message-ID: <CAKON4OxjX94js19KqMx3W_hvqj8VwacAwFLMQF_BahME4XH-3A@mail.gmail.com>

On Fri, Mar 23, 2012 at 12:00 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Thu, 22 Mar 2012, jonsmirl at gmail.com wrote:
>
>> When iotable is used to initially map memory you can specify the
>> mapping address. In this case IO_SDMMC_PHYS is 0x18000000 and it gets
>> mapped to ?0xf1800000
>>
>> NXP has supplied this handly macro
>> #define io_p2v(x) (0xf0000000 | (((x) & 0xff000000) >> 4) | ((x) & 0x000fffff))
>>
>> iotable_init(lpc313x_io_desc, ARRAY_SIZE(lpc313x_io_desc));
>>
>> ? ? ? {
>> ? ? ? ? ? ? ? .virtual ? ? ? ?= io_p2v(IO_SDMMC_PHYS),
>> ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(IO_SDMMC_PHYS),
>> ? ? ? ? ? ? ? .length ? ? ? ? = IO_SDMMC_SIZE,
>> ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE
>> ? ? ? },
>>
>> The supplied kernel is full of code that uses this type of addressing.
>> It has macros for register definition that all depend on the registers
>> being mapped to a well know location - io_p2v(x).
>>
>> I'd like to move the map out of the core code and into the SDMMC
>> device driver and then only do it if the driver loads.
>
> Why would you do that? ?Those static mappings are meant to be global and
> remain there. ?The handy macro is in fact not handy at all as it forces
> virtual addresses on you.

I'm ok with global static mappings. What I'd like to do is build the
static iotable from the device tree instead of repeating every device
in the map_desc array. I suppose I could dynamically allocate it, fill
it in from the device tree and call iotable_init().

What is the right way to make the initial static mappings?

>
> It is OK to keep the static mappings as you can use 1MB regions and the
> mapping code will use first level mappings which are better with TLB
> usage.

CPU is arm926ejs. Peripherals are small blocks spread out on 16MB
boundaries. There are eleven groups.

>
> But drivers should really be using:

This is the style I'm used too. I'll assess how much work it is to
convert everything.

>
> ? ? ? ?iobase = ioremap(IO_SDMMC_PHYS);
>
> and the various registers should be defined as offsets from that base.
> Then you would use:
>
> ? ? ? ?val = readl(iobase + SDMMC_FOO_REG);
>
> where you could have:
>
> #define SDMMC_FOO_REG ? 0x10
>
> With a recent kernel, the ioremap code will reuse any static mappings
> that matches the physical address you give it, or create a new mapping
> otherwise. ?But in either cases the actual virtual address used
> shouldn't matter anymore.
>
>
> Nicolas



-- 
Jon Smirl
jonsmirl at gmail.com


From nico at fluxnic.net  Fri Mar 23 00:28:48 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 23 Mar 2012 00:28:48 -0400 (EDT)
Subject: ioremap to a specific virtual address
In-Reply-To: <CAKON4OxjX94js19KqMx3W_hvqj8VwacAwFLMQF_BahME4XH-3A@mail.gmail.com>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <alpine.LFD.2.02.1203222348210.24151@xanadu.home>
 <CAKON4OxjX94js19KqMx3W_hvqj8VwacAwFLMQF_BahME4XH-3A@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1203230023060.24151@xanadu.home>

On Fri, 23 Mar 2012, jonsmirl at gmail.com wrote:

> On Fri, Mar 23, 2012 at 12:00 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> > On Thu, 22 Mar 2012, jonsmirl at gmail.com wrote:
> >
> >> When iotable is used to initially map memory you can specify the
> >> mapping address. In this case IO_SDMMC_PHYS is 0x18000000 and it gets
> >> mapped to ?0xf1800000
> >>
> >> NXP has supplied this handly macro
> >> #define io_p2v(x) (0xf0000000 | (((x) & 0xff000000) >> 4) | ((x) & 0x000fffff))
> >>
> >> iotable_init(lpc313x_io_desc, ARRAY_SIZE(lpc313x_io_desc));
> >>
> >> ? ? ? {
> >> ? ? ? ? ? ? ? .virtual ? ? ? ?= io_p2v(IO_SDMMC_PHYS),
> >> ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(IO_SDMMC_PHYS),
> >> ? ? ? ? ? ? ? .length ? ? ? ? = IO_SDMMC_SIZE,
> >> ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE
> >> ? ? ? },
> >>
> >> The supplied kernel is full of code that uses this type of addressing.
> >> It has macros for register definition that all depend on the registers
> >> being mapped to a well know location - io_p2v(x).
> >>
> >> I'd like to move the map out of the core code and into the SDMMC
> >> device driver and then only do it if the driver loads.
> >
> > Why would you do that? ?Those static mappings are meant to be global and
> > remain there. ?The handy macro is in fact not handy at all as it forces
> > virtual addresses on you.
> 
> I'm ok with global static mappings. What I'd like to do is build the
> static iotable from the device tree instead of repeating every device
> in the map_desc array. I suppose I could dynamically allocate it, fill
> it in from the device tree and call iotable_init().

Well, if you have a device tree with that stuff, then you may as well 
just forget about the static mappings.

> What is the right way to make the initial static mappings?

Typically by declaring it in the code.  Otherwise there is some 
infrastructure already in place for drivers to map their hardware 
dynamically from DT information.


Nicolas

From nico at fluxnic.net  Fri Mar 23 00:00:51 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 23 Mar 2012 00:00:51 -0400 (EDT)
Subject: ioremap to a specific virtual address
In-Reply-To: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1203222348210.24151@xanadu.home>

On Thu, 22 Mar 2012, jonsmirl at gmail.com wrote:

> When iotable is used to initially map memory you can specify the
> mapping address. In this case IO_SDMMC_PHYS is 0x18000000 and it gets
> mapped to  0xf1800000
> 
> NXP has supplied this handly macro
> #define io_p2v(x) (0xf0000000 | (((x) & 0xff000000) >> 4) | ((x) & 0x000fffff))
> 
> iotable_init(lpc313x_io_desc, ARRAY_SIZE(lpc313x_io_desc));
> 
> 	{
> 		.virtual	= io_p2v(IO_SDMMC_PHYS),
> 		.pfn		= __phys_to_pfn(IO_SDMMC_PHYS),
> 		.length		= IO_SDMMC_SIZE,
> 		.type		= MT_DEVICE
> 	},
> 
> The supplied kernel is full of code that uses this type of addressing.
> It has macros for register definition that all depend on the registers
> being mapped to a well know location - io_p2v(x).
> 
> I'd like to move the map out of the core code and into the SDMMC
> device driver and then only do it if the driver loads.

Why would you do that?  Those static mappings are meant to be global and 
remain there.  The handy macro is in fact not handy at all as it forces 
virtual addresses on you.

It is OK to keep the static mappings as you can use 1MB regions and the 
mapping code will use first level mappings which are better with TLB 
usage.

But drivers should really be using:

	iobase = ioremap(IO_SDMMC_PHYS);

and the various registers should be defined as offsets from that base.  
Then you would use:

	val = readl(iobase + SDMMC_FOO_REG);

where you could have:

#define SDMMC_FOO_REG	0x10

With a recent kernel, the ioremap code will reuse any static mappings 
that matches the physical address you give it, or create a new mapping 
otherwise.  But in either cases the actual virtual address used 
shouldn't matter anymore.


Nicolas


From kuninori.morimoto.gx at renesas.com  Fri Mar 23 01:41:52 2012
From: kuninori.morimoto.gx at renesas.com (Kuninori Morimoto)
Date: Thu, 22 Mar 2012 22:41:52 -0700 (PDT)
Subject: [PATCH] ARM: fixup section mismatch warning for alloc_init_pud()
Message-ID: <87398zswkj.wl%kuninori.morimoto.gx@renesas.com>

This patch fixup below warning

WARNING: arch/arm/mm/built-in.o(.text+0x2320):
Section mismatch in reference from the function alloc_init_pud()
to the function .init.text:alloc_init_section()
The function alloc_init_pud() references
the function __init alloc_init_section().
This is often because alloc_init_pud lacks a __init
annotation or the annotation of alloc_init_section is wrong.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
---
 arch/arm/mm/mmu.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 94c5a0c..95a8098 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -616,7 +616,7 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
 	}
 }
 
-static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
+static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
 	unsigned long phys, const struct mem_type *type)
 {
 	pud_t *pud = pud_offset(pgd, addr);
-- 
1.7.5.4



From haojian.zhuang at gmail.com  Fri Mar 23 02:22:35 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 23 Mar 2012 14:22:35 +0800
Subject: [GIT PULL][for 3.4] pull request from arch-pxa git for board branch
Message-ID: <CAN1soZyCRQSVUQe+iBWX0nGwViWjp=W32BkYCcUUDmR894PJ9w@mail.gmail.com>

Hi Arnd & Olof,

Please help to merge this patch from arch-pxa git tree.

The following changes since commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7:

  Linux 3.3 (2012-03-18 16:15:34 -0700)

are available in the git repository at:
  git://github.com/hzhuang1/linux.git board-specific

Paul Parsons (1):
      pxa/hx4700: Add standard UART to hx4700_pin_config[]

 arch/arm/mach-pxa/hx4700.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)


From afzal at ti.com  Fri Mar 23 02:36:07 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Fri, 23 Mar 2012 12:06:07 +0530
Subject: [RFC][PATCH 0/5] Convert GPMC to driver
Message-ID: <1332484567-21710-1-git-send-email-afzal@ti.com>

Hi,

Convert GPCM code to be a driver. Existing GPMC
NAND platform handling has been modified to work
with the new GPMC driver (patches 2 & 3). Patch 5
is to test the driver in OMAP3EVM.

Once all the users has been converted to use this
driver, would be converted to MFD type.

TODO:
1. Let OMAP NAND driver deal with GPMC NAND block
2. Remove struct gpmc * stored as static
3. Convert all peripherals to use GPMC driver
4. Devise method to handle OneNAND cleanly
5. Handle acquiring CS# cases
6. Convert to MFD driver

Regards
Afzal

Afzal Mohammed (5):
  ARM: OMAP2+: gpmc: driver conversion
  ARM: OMAP2+: nand: create platform data structure
  ARM: OMAP2+: gpmc-nand: populate gpmc configs
  mtd: nand: omap2: obtain memory from resource
  OMAP3EVM: Test gpmc-nand

 arch/arm/mach-omap2/board-devkit8000.c     |    6 +-
 arch/arm/mach-omap2/board-flash.c          |   63 +-
 arch/arm/mach-omap2/board-flash.h          |   13 +-
 arch/arm/mach-omap2/board-ldp.c            |    4 +-
 arch/arm/mach-omap2/board-omap3beagle.c    |    6 +-
 arch/arm/mach-omap2/board-omap3evm.c       |   82 +++
 arch/arm/mach-omap2/board-omap3touchbook.c |    6 +-
 arch/arm/mach-omap2/board-overo.c          |    5 +-
 arch/arm/mach-omap2/board-zoom.c           |    5 +-
 arch/arm/mach-omap2/common-board-devices.c |   46 --
 arch/arm/mach-omap2/common-board-devices.h |    1 -
 arch/arm/mach-omap2/gpmc-nand.c            |   88 +--
 arch/arm/mach-omap2/gpmc.c                 | 1083 ++++++++++++++++------------
 arch/arm/plat-omap/include/plat/gpmc.h     |   34 +-
 arch/arm/plat-omap/include/plat/nand.h     |    9 +-
 drivers/mtd/nand/omap2.c                   |   19 +-
 16 files changed, 869 insertions(+), 601 deletions(-)

-- 
1.7.9.3



From afzal at ti.com  Fri Mar 23 02:36:40 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Fri, 23 Mar 2012 12:06:40 +0530
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
Message-ID: <1332484600-21947-1-git-send-email-afzal@ti.com>

Convert GPMC code to driver. Boards using GPMC
should provide driver with type of configuration,
timing, GPMC address space details (if already
configured, driver will retrieve, as is existing).
Platform devices would the be created for each
connected peripheral (peripheral details also to
be passed by board so that it reaches respective
driver). And GPMC driver would populate memory
resource details for the driver of connected
peripheral.

A peripheral connected to GPMC can have multiple
address spaces using different chip select. Hence
GPMC driver has been provided capability to
distinguish this scenario, i.e. create platform
devices only once for each connected peripheral,
and not for each configured chip select. The
peripheral that made it necessary was tusb6010.

Final destination aimed for this driver is MFD.
But before that all existing GPMC users has to be
converted to work with this driver. This would
likely result in removal of gpmc_create_child
and probably use MFD APIs instead.

NAND driver for GPMC is tightly coupled with GPMC
driver (GPMC has few blocks exclusively for NAND),
while that is not the case for most of the other
users (they need GPMCs help only for initial
configuration). Currently NAND driver manage using
exported GPMC symbols. This is being planned to
remove later & would need informing NAND driver
about GPMC NAND registers. This would help to have
export symbol free GPMC driver, and probably
"mv omap2.c gpmc-nand.c" for OMAP NAND driver.
Thanks to Vaibhav Hiremath for his ideas on this.

Acquiring CS# for NAND is done on a few boards.
It means, depending on bootloader to embed this
information. Probably CS# being used can be set
in the Kernel, and acquiring it can be removed.
If ever this capbility is needed, GPMC driver
has to be made aware of handling it.

OneNAND - as it may involve reconfiguring GPMC for
synchronous may need a quirk to handle or driver
has to be made more intelligent to handle it.

Code below comment "GPMC CLK related" may have
to continue live in platform folders (even if the
driver is moved to MFD) as input clock is beyond
the control of GPMC and calculating timing for
the peripheral may need other helpers.

TODO (or not?)
1. NAND driver deal with GPMC NAND block
2. Remove struct gpmc * stored as static
3. Convert all peripherals to use GPMC driver
4. Devise method to handle OneNAND cleanly
5. Handle acquiring CS# cases
6. Convert to MFD driver

Signed-off-by: Afzal Mohammed <afzal at ti.com>
Cc: Vaibhav Hiremath <hvaibhav at ti.com>
---
 arch/arm/mach-omap2/gpmc.c             | 1083 +++++++++++++++++++-------------
 arch/arm/plat-omap/include/plat/gpmc.h |   34 +-
 2 files changed, 672 insertions(+), 445 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 00d5108..954fa22 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -14,8 +14,11 @@
  */
 #undef DEBUG
 
+#include <linux/platform_device.h>
+
 #include <linux/irq.h>
 #include <linux/kernel.h>
+#include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/err.h>
 #include <linux/clk.h>
@@ -64,248 +67,99 @@
 #define ENABLE_PREFETCH		(0x1 << 7)
 #define DMA_MPU_MODE		2
 
-/* Structure to save gpmc cs context */
-struct gpmc_cs_config {
-	u32 config1;
-	u32 config2;
-	u32 config3;
-	u32 config4;
-	u32 config5;
-	u32 config6;
-	u32 config7;
-	int is_valid;
-};
-
-/*
- * Structure to save/restore gpmc context
- * to support core off on OMAP3
- */
-struct omap3_gpmc_regs {
-	u32 sysconfig;
-	u32 irqenable;
-	u32 timeout_ctrl;
-	u32 config;
-	u32 prefetch_config1;
-	u32 prefetch_config2;
-	u32 prefetch_control;
-	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
-};
-
-static struct resource	gpmc_mem_root;
-static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
-static DEFINE_SPINLOCK(gpmc_mem_lock);
-static unsigned int gpmc_cs_map;	/* flag for cs which are initialized */
-static int gpmc_ecc_used = -EINVAL;	/* cs using ecc engine */
-
-static void __iomem *gpmc_base;
-
-static struct clk *gpmc_l3_clk;
-
-static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 
-static void gpmc_write_reg(int idx, u32 val)
-{
-	__raw_writel(val, gpmc_base + idx);
-}
-
-static u32 gpmc_read_reg(int idx)
-{
-	return __raw_readl(gpmc_base + idx);
-}
-
-static void gpmc_cs_write_byte(int cs, int idx, u8 val)
-{
-	void __iomem *reg_addr;
+#define	DRIVER_NAME	"omap-gpmc"
 
-	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-	__raw_writeb(val, reg_addr);
-}
+struct gpmc_child {
+	char			*name;
+	int			id;
+	struct resource		*res;
+	unsigned		num_res;
+	struct resource		gpmc_res[GPMC_CS_NUM];
+	unsigned		gpmc_num_res;
+	void			*pdata;
+	unsigned		pdata_size;
+};
 
-static u8 gpmc_cs_read_byte(int cs, int idx)
-{
-	void __iomem *reg_addr;
+struct gpmc {
+	struct device		*dev;
+	unsigned long		fclk_rate;
+	void __iomem		*io_base;
+	unsigned long		phys_base;
+	u32			memsize;
+	unsigned		cs_map;
+	int			ecc_used;
+	spinlock_t		mem_lock;
+	struct resource		mem_root;
+	struct resource		cs_mem[GPMC_CS_NUM];
+	struct gpmc_child	child_device[GPMC_CS_NUM];
+	unsigned		num_child;
+	unsigned		num_device;
+};
 
-	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-	return __raw_readb(reg_addr);
-}
+static struct gpmc *gpmc;
 
+/* Make function static */
 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 {
 	void __iomem *reg_addr;
 
-	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-	__raw_writel(val, reg_addr);
+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+	writel(val, reg_addr);
 }
 
+/* Make function static */
 u32 gpmc_cs_read_reg(int cs, int idx)
 {
 	void __iomem *reg_addr;
 
-	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-	return __raw_readl(reg_addr);
+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+	return readl(reg_addr);
 }
 
-/* TODO: Add support for gpmc_fck to clock framework and use it */
-unsigned long gpmc_get_fclk_period(void)
+static void gpmc_write_reg(int idx, u32 val)
 {
-	unsigned long rate = clk_get_rate(gpmc_l3_clk);
-
-	if (rate == 0) {
-		printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
-		return 0;
-	}
-
-	rate /= 1000;
-	rate = 1000000000 / rate;	/* In picoseconds */
-
-	return rate;
+	writel(val, gpmc->io_base + idx);
 }
 
-unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
+static u32 gpmc_read_reg(int idx)
 {
-	unsigned long tick_ps;
-
-	/* Calculate in picosecs to yield more exact results */
-	tick_ps = gpmc_get_fclk_period();
-
-	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
+	return readl(gpmc->io_base + idx);
 }
 
-unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
+static void gpmc_cs_write_byte(int cs, int idx, u8 val)
 {
-	unsigned long tick_ps;
-
-	/* Calculate in picosecs to yield more exact results */
-	tick_ps = gpmc_get_fclk_period();
-
-	return (time_ps + tick_ps - 1) / tick_ps;
-}
+	void __iomem *reg_addr;
 
-unsigned int gpmc_ticks_to_ns(unsigned int ticks)
-{
-	return ticks * gpmc_get_fclk_period() / 1000;
+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+	writeb(val, reg_addr);
 }
 
-unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
+static u8 gpmc_cs_read_byte(int cs, int idx)
 {
-	unsigned long ticks = gpmc_ns_to_ticks(time_ns);
+	void __iomem *reg_addr;
 
-	return ticks * gpmc_get_fclk_period() / 1000;
+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+	return readb(reg_addr);
 }
 
-#ifdef DEBUG
-static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
-			       int time, const char *name)
-#else
-static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
-			       int time)
-#endif
+static int gpmc_cs_set_reserved(int cs, int reserved)
 {
-	u32 l;
-	int ticks, mask, nr_bits;
-
-	if (time == 0)
-		ticks = 0;
-	else
-		ticks = gpmc_ns_to_ticks(time);
-	nr_bits = end_bit - st_bit + 1;
-	if (ticks >= 1 << nr_bits) {
-#ifdef DEBUG
-		printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
-				cs, name, time, ticks, 1 << nr_bits);
-#endif
-		return -1;
-	}
+	if (cs > GPMC_CS_NUM)
+		return -ENODEV;
 
-	mask = (1 << nr_bits) - 1;
-	l = gpmc_cs_read_reg(cs, reg);
-#ifdef DEBUG
-	printk(KERN_INFO
-		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
-	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
-			(l >> st_bit) & mask, time);
-#endif
-	l &= ~(mask << st_bit);
-	l |= ticks << st_bit;
-	gpmc_cs_write_reg(cs, reg, l);
+	gpmc->cs_map &= ~(1 << cs);
+	gpmc->cs_map |= (reserved ? 1 : 0) << cs;
 
 	return 0;
 }
 
-#ifdef DEBUG
-#define GPMC_SET_ONE(reg, st, end, field) \
-	if (set_gpmc_timing_reg(cs, (reg), (st), (end),		\
-			t->field, #field) < 0)			\
-		return -1
-#else
-#define GPMC_SET_ONE(reg, st, end, field) \
-	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
-		return -1
-#endif
-
-int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
-{
-	int div;
-	u32 l;
-
-	l = sync_clk + (gpmc_get_fclk_period() - 1);
-	div = l / gpmc_get_fclk_period();
-	if (div > 4)
-		return -1;
-	if (div <= 0)
-		div = 1;
-
-	return div;
-}
-
-int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
+static int gpmc_cs_reserved(int cs)
 {
-	int div;
-	u32 l;
-
-	div = gpmc_cs_calc_divider(cs, t->sync_clk);
-	if (div < 0)
-		return -1;
-
-	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
-	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
-	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
-
-	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
-	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
-	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
-
-	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
-	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
-	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
-	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
-
-	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
-	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
-	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
-
-	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
-
-	if (cpu_is_omap34xx()) {
-		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
-		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
-	}
-
-	/* caller is expected to have initialized CONFIG1 to cover
-	 * at least sync vs async
-	 */
-	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-	if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
-#ifdef DEBUG
-		printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
-				cs, (div * gpmc_get_fclk_period()) / 1000, div);
-#endif
-		l &= ~0x03;
-		l |= (div - 1);
-		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
-	}
+	if (cs > GPMC_CS_NUM)
+		return -ENODEV;
 
-	return 0;
+	return gpmc->cs_map & (1 << cs);
 }
 
 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
@@ -332,17 +186,6 @@ static void gpmc_cs_disable_mem(int cs)
 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 }
 
-static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
-{
-	u32 l;
-	u32 mask;
-
-	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
-	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
-	mask = (l >> 8) & 0x0f;
-	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
-}
-
 static int gpmc_cs_mem_enabled(int cs)
 {
 	u32 l;
@@ -351,25 +194,6 @@ static int gpmc_cs_mem_enabled(int cs)
 	return l & GPMC_CONFIG7_CSVALID;
 }
 
-int gpmc_cs_set_reserved(int cs, int reserved)
-{
-	if (cs > GPMC_CS_NUM)
-		return -ENODEV;
-
-	gpmc_cs_map &= ~(1 << cs);
-	gpmc_cs_map |= (reserved ? 1 : 0) << cs;
-
-	return 0;
-}
-
-int gpmc_cs_reserved(int cs)
-{
-	if (cs > GPMC_CS_NUM)
-		return -ENODEV;
-
-	return gpmc_cs_map & (1 << cs);
-}
-
 static unsigned long gpmc_mem_align(unsigned long size)
 {
 	int order;
@@ -384,24 +208,9 @@ static unsigned long gpmc_mem_align(unsigned long size)
 	return size;
 }
 
-static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
-{
-	struct resource	*res = &gpmc_cs_mem[cs];
-	int r;
-
-	size = gpmc_mem_align(size);
-	spin_lock(&gpmc_mem_lock);
-	res->start = base;
-	res->end = base + size - 1;
-	r = request_resource(&gpmc_mem_root, res);
-	spin_unlock(&gpmc_mem_lock);
-
-	return r;
-}
-
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
-	struct resource *res = &gpmc_cs_mem[cs];
+	struct resource *res = &gpmc->cs_mem[cs];
 	int r = -1;
 
 	if (cs > GPMC_CS_NUM)
@@ -411,7 +220,7 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 	if (size > (1 << GPMC_SECTION_SHIFT))
 		return -ENOMEM;
 
-	spin_lock(&gpmc_mem_lock);
+	spin_lock(&gpmc->mem_lock);
 	if (gpmc_cs_reserved(cs)) {
 		r = -EBUSY;
 		goto out;
@@ -419,7 +228,7 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 	if (gpmc_cs_mem_enabled(cs))
 		r = adjust_resource(res, res->start & ~(size - 1), size);
 	if (r < 0)
-		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
+		r = allocate_resource(&gpmc->mem_root, res, size, 0, ~0,
 				      size, NULL, NULL);
 	if (r < 0)
 		goto out;
@@ -428,66 +237,28 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 	*base = res->start;
 	gpmc_cs_set_reserved(cs, 1);
 out:
-	spin_unlock(&gpmc_mem_lock);
+	spin_unlock(&gpmc->mem_lock);
 	return r;
 }
 EXPORT_SYMBOL(gpmc_cs_request);
 
 void gpmc_cs_free(int cs)
 {
-	spin_lock(&gpmc_mem_lock);
+	spin_lock(&gpmc->mem_lock);
 	if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
 		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
 		BUG();
-		spin_unlock(&gpmc_mem_lock);
+		spin_unlock(&gpmc->mem_lock);
 		return;
 	}
 	gpmc_cs_disable_mem(cs);
-	release_resource(&gpmc_cs_mem[cs]);
+	release_resource(&gpmc->cs_mem[cs]);
 	gpmc_cs_set_reserved(cs, 0);
-	spin_unlock(&gpmc_mem_lock);
+	spin_unlock(&gpmc->mem_lock);
 }
 EXPORT_SYMBOL(gpmc_cs_free);
 
 /**
- * gpmc_read_status - read access request to get the different gpmc status
- * @cmd: command type
- * @return status
- */
-int gpmc_read_status(int cmd)
-{
-	int	status = -EINVAL;
-	u32	regval = 0;
-
-	switch (cmd) {
-	case GPMC_GET_IRQ_STATUS:
-		status = gpmc_read_reg(GPMC_IRQSTATUS);
-		break;
-
-	case GPMC_PREFETCH_FIFO_CNT:
-		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
-		status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
-		break;
-
-	case GPMC_PREFETCH_COUNT:
-		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
-		status = GPMC_PREFETCH_STATUS_COUNT(regval);
-		break;
-
-	case GPMC_STATUS_BUFFER:
-		regval = gpmc_read_reg(GPMC_STATUS);
-		/* 1 : buffer is available to write */
-		status = regval & GPMC_STATUS_BUFF_EMPTY;
-		break;
-
-	default:
-		printk(KERN_ERR "gpmc_read_status: Not supported\n");
-	}
-	return status;
-}
-EXPORT_SYMBOL(gpmc_read_status);
-
-/**
  * gpmc_cs_configure - write request to configure gpmc
  * @cs: chip select number
  * @cmd: command type
@@ -555,120 +326,143 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
 }
 EXPORT_SYMBOL(gpmc_cs_configure);
 
-/**
- * gpmc_nand_read - nand specific read access request
- * @cs: chip select number
- * @cmd: command type
+/* This is a duplication of an existing function; before GPMC probe
+   invocation, platform code may need to find divider value, hence
+   other function (gpmc_cs_calc_divider) is not removed, functions
+   like it that are required by platform, probably can be put in
+   common omap platform file. gpmc_calc_divider will get invoked
+   only after GPMC driver gets probed. gpmc_cs_calc_divider is not
+   invoked by GPMC driver to cleanly separate platform & driver
+   code, although both should return sme value.
  */
-int gpmc_nand_read(int cs, int cmd)
+static int gpmc_calc_divider(u32 sync_clk)
 {
-	int rval = -EINVAL;
-
-	switch (cmd) {
-	case GPMC_NAND_DATA:
-		rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
-		break;
+	int div;
+	u32 l;
 
-	default:
-		printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
-	}
-	return rval;
+	l = sync_clk + (gpmc->fclk_rate - 1);
+	div = l / gpmc->fclk_rate;
+	if (div > 4)
+		return -1;
+	if (div <= 0)
+		div = 1;
+
+	return div;
 }
-EXPORT_SYMBOL(gpmc_nand_read);
 
-/**
- * gpmc_nand_write - nand specific write request
- * @cs: chip select number
- * @cmd: command type
- * @wval: value to write
- */
-int gpmc_nand_write(int cs, int cmd, int wval)
+static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
+			       int time, const char *name)
 {
-	int err = 0;
-
-	switch (cmd) {
-	case GPMC_NAND_COMMAND:
-		gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
-		break;
+	u32 l;
+	int ticks, mask, nr_bits;
 
-	case GPMC_NAND_ADDRESS:
-		gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
-		break;
+	if (time == 0)
+		ticks = 0;
+	else
+		ticks = gpmc_ns_to_ticks(time);
+	nr_bits = end_bit - st_bit + 1;
+	if (ticks >= 1 << nr_bits) {
+		printk(KERN_DEBUG "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
+				cs, name, time, ticks, 1 << nr_bits);
+		return -1;
+	}
 
-	case GPMC_NAND_DATA:
-		gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
+	mask = (1 << nr_bits) - 1;
+	l = gpmc_cs_read_reg(cs, reg);
+	printk(KERN_DEBUG
+		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
+	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
+			(l >> st_bit) & mask, time);
+	l &= ~(mask << st_bit);
+	l |= ticks << st_bit;
+	gpmc_cs_write_reg(cs, reg, l);
 
-	default:
-		printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
-		err = -EINVAL;
-	}
-	return err;
+	return 0;
 }
-EXPORT_SYMBOL(gpmc_nand_write);
-
 
+#define GPMC_SET_ONE(reg, st, end, field) \
+	do {							\
+		if (set_gpmc_timing_reg(cs, (reg), (st), (end),	\
+				t->field, #field) < 0)		\
+			return -1;				\
+	} while (0)
 
-/**
- * gpmc_prefetch_enable - configures and starts prefetch transfer
- * @cs: cs (chip select) number
- * @fifo_th: fifo threshold to be used for read/ write
- * @dma_mode: dma mode enable (1) or disable (0)
- * @u32_count: number of bytes to be transferred
- * @is_write: prefetch read(0) or write post(1) mode
- */
-int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
-				unsigned int u32_count, int is_write)
+int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 {
+	int div;
+	u32 l;
 
-	if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
-		pr_err("gpmc: fifo threshold is not supported\n");
+	div = gpmc_calc_divider(t->sync_clk);
+	if (div < 0)
 		return -1;
-	} else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
-		/* Set the amount of bytes to be prefetched */
-		gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
 
-		/* Set dma/mpu mode, the prefetch read / post write and
-		 * enable the engine. Set which cs is has requested for.
-		 */
-		gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
-					PREFETCH_FIFOTHRESHOLD(fifo_th) |
-					ENABLE_PREFETCH |
-					(dma_mode << DMA_MPU_MODE) |
-					(0x1 & is_write)));
+	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
+	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
+	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 
-		/*  Start the prefetch engine */
-		gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
-	} else {
-		return -EBUSY;
+	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
+	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
+	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
+
+	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
+	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
+	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
+	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
+
+	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
+	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
+	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
+
+	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
+
+	if (cpu_is_omap34xx()) {
+		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
+		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
+	}
+
+	/* caller is expected to have initialized CONFIG1 to cover
+	 * at least sync vs async
+	 */
+	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+	if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
+		printk(KERN_DEBUG "GPMC CS%d CLK period is %lu ns (div %d)\n",
+				cs, (div * gpmc_get_fclk_period()) / 1000, div);
+		l &= ~0x03;
+		l |= (div - 1);
+		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 	}
 
 	return 0;
 }
-EXPORT_SYMBOL(gpmc_prefetch_enable);
 
-/**
- * gpmc_prefetch_reset - disables and stops the prefetch engine
- */
-int gpmc_prefetch_reset(int cs)
+static __devinit void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 {
-	u32 config1;
+	u32 l;
+	u32 mask;
 
-	/* check if the same module/cs is trying to reset */
-	config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
-	if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
-		return -EINVAL;
+	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
+	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
+	mask = (l >> 8) & 0x0f;
+	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
+}
 
-	/* Stop the PFPW engine */
-	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
+static __devinit
+int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
+{
+	struct resource	*res = &gpmc->cs_mem[cs];
+	int r;
 
-	/* Reset/disable the PFPW engine */
-	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
+	size = gpmc_mem_align(size);
+	spin_lock(&gpmc->mem_lock);
+	res->start = base;
+	res->end = base + size - 1;
+	r = request_resource(&gpmc->mem_root, res);
+	spin_unlock(&gpmc->mem_lock);
 
-	return 0;
+	return r;
 }
-EXPORT_SYMBOL(gpmc_prefetch_reset);
 
-static void __init gpmc_mem_init(void)
+static __devinit void gpmc_mem_init(void)
 {
 	int cs;
 	unsigned long boot_rom_space = 0;
@@ -680,8 +474,8 @@ static void __init gpmc_mem_init(void)
 	/* In apollon the CS0 is mapped as 0x0000 0000 */
 	if (machine_is_omap_apollon())
 		boot_rom_space = 0;
-	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
-	gpmc_mem_root.end = GPMC_MEM_END;
+	gpmc->mem_root.start = GPMC_MEM_START + boot_rom_space;
+	gpmc->mem_root.end = GPMC_MEM_END;
 
 	/* Reserve all regions that has been set up by bootloader */
 	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
@@ -695,88 +489,245 @@ static void __init gpmc_mem_init(void)
 	}
 }
 
-static int __init gpmc_init(void)
+static inline int __devinit gpmc_find_next_child_slot(void)
 {
-	u32 l, irq;
-	int cs, ret = -EINVAL;
-	int gpmc_irq;
-	char *ck = NULL;
+	return gpmc->num_child;
+}
 
-	if (cpu_is_omap24xx()) {
-		ck = "core_l3_ck";
-		if (cpu_is_omap2420())
-			l = OMAP2420_GPMC_BASE;
-		else
-			l = OMAP34XX_GPMC_BASE;
-		gpmc_irq = INT_34XX_GPMC_IRQ;
-	} else if (cpu_is_omap34xx()) {
-		ck = "gpmc_fck";
-		l = OMAP34XX_GPMC_BASE;
-		gpmc_irq = INT_34XX_GPMC_IRQ;
-	} else if (cpu_is_omap44xx()) {
-		ck = "gpmc_ck";
-		l = OMAP44XX_GPMC_BASE;
-		gpmc_irq = OMAP44XX_IRQ_GPMC;
-	}
+static int __devinit gpmc_match_child(char *name, int id)
+{
+	int i;
+	struct gpmc_child *p;
 
-	if (WARN_ON(!ck))
+	for (i = 0, p = gpmc->child_device; i < gpmc->num_child; i++, p++)
+		if (!strcmp(p->name, name) && (p->id == id))
+			return i;
+
+	return -ENOENT;
+}
+
+static __devinit int gpmc_setup_child(struct gpmc_device_pdata *gdev)
+{
+	struct gpmc_config *c;
+	int i, ret = 0;
+	struct resource res;
+	unsigned long start;
+
+	start = gdev->mem_start;
+
+	ret = gpmc_cs_request(gdev->cs, gdev->mem_size, &start);
+	if (IS_ERR_VALUE(ret)) {
+		dev_err(gpmc->dev, "error: gpmc request on CS: %u\n", gdev->cs);
 		return ret;
+	}
 
-	gpmc_l3_clk = clk_get(NULL, ck);
-	if (IS_ERR(gpmc_l3_clk)) {
-		printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
-		BUG();
+	c = gdev->config;
+	if (!c) {
+		dev_err(gpmc->dev, "config not present for CS: %u\n", gdev->cs);
+		return -EINVAL;
 	}
 
-	gpmc_base = ioremap(l, SZ_4K);
-	if (!gpmc_base) {
-		clk_put(gpmc_l3_clk);
-		printk(KERN_ERR "Could not get GPMC register memory\n");
-		BUG();
+	for (i = 0; i < gdev->num_config; c++, i++) {
+		ret = gpmc_cs_configure(gdev->cs, c->cmd, c->val);
+		if (IS_ERR_VALUE(ret)) {
+			dev_err(gpmc->dev, "invalid cmd or value on CS:	\
+			 %u: cmd: %d value: %d\n", gdev->cs, c->cmd, c->val);
+			return ret;
+		}
+	}
+
+	if (gdev->timing) {
+		ret = gpmc_cs_set_timings(gdev->cs, gdev->timing);
+		if (IS_ERR_VALUE(ret)) {
+			dev_err(gpmc->dev, "error: setting timing on CS: %d\n",
+								gdev->cs);
+			return ret;
+		}
 	}
 
-	clk_enable(gpmc_l3_clk);
+	res.start = start + gdev->mem_offset;
+	res.end = res.start + gdev->mem_size - 1;
+	res.flags = IORESOURCE_MEM;
+
+	i = gpmc_match_child(gdev->name, gdev->id);
+	/* i >= GPMC_CS_NUM can never happen, this is for compiler to shutup */
+	if (i >= 0 && i < GPMC_CS_NUM) {
+		int j;
+
+		j = gpmc->child_device[i].gpmc_num_res;
+		gpmc->child_device[i].gpmc_res[j] = res;
+	} else if (i == -ENOENT) {
+		i = gpmc_find_next_child_slot();
+		if (IS_ERR_VALUE(i)) {
+			dev_err(gpmc->dev, "error: childs exceeded\n");
+			return -ENODEV;
+		}
+		gpmc->child_device[i].name = gdev->name;
+		gpmc->child_device[i].id = gdev->id;
+		gpmc->child_device[i].pdata = gdev->pdata;
+		gpmc->child_device[i].pdata_size = gdev->pdata_size;
+		gpmc->child_device[i].gpmc_res[0] = res;
+	} else {
+		/* should never come here */
+		dev_err(gpmc->dev, "error: childs exceeded\n");
+		return -ENODEV;
+	}
+
+	gpmc->child_device[i].gpmc_num_res++;
+
+	return ret;
+}
+
+static __devinit int gpmc_create_child(int cnt)
+{
+	struct gpmc_child *p = gpmc->child_device + cnt;
+	int num = p->num_res + p->gpmc_num_res;
+	struct resource *res;
+
+	res = kzalloc(sizeof(struct resource) * num, GFP_KERNEL);
+	if (!res) {
+		dev_err(gpmc->dev, "error: allocating memory\n");
+		return -ENOMEM;
+	}
+
+	memcpy((char *)res, (const char *) p->gpmc_res,
+				sizeof(struct resource) * p->gpmc_num_res);
+	memcpy((char *)(res + p->gpmc_num_res), (const char *)p->res,
+				sizeof(struct resource) * p->num_res);
+
+	platform_device_register_resndata(gpmc->dev, p->name, p->id, res,
+						num, p->pdata, p->pdata_size);
+
+	return 0;
+}
+
+static __devinit int gpmc_probe(struct platform_device *pdev)
+{
+	u32 l;
+	int i;
+	int ret = -EINVAL;
+	struct resource *res = NULL;
+	struct gpmc_pdata *gd = dev_get_platdata(&pdev->dev);
+	struct gpmc_device_pdata *gdev = NULL;
+
+	gpmc = devm_kzalloc(&pdev->dev, sizeof(struct gpmc), GFP_KERNEL);
+	if (!gpmc) {
+		dev_err(&pdev->dev, "Failed to allocate memory\n");
+		return -ENOMEM;
+	}
+
+	gpmc->dev = &pdev->dev;
+	gpmc->fclk_rate = gd->fclk_rate;
+	gpmc->num_device = gd->num_device;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		ret = -ENOENT;
+		dev_err(gpmc->dev, "Failed to get resource: memory\n");
+		goto err_res;
+	}
+	gpmc->phys_base = res->start;
+	gpmc->memsize = resource_size(res);
+
+	if (request_mem_region(gpmc->phys_base,
+		gpmc->memsize, DRIVER_NAME) == NULL) {
+		ret = -ENOMEM;
+		dev_err(gpmc->dev, "Failed to request memory region\n");
+		goto err_mem;
+	}
+
+	gpmc->io_base = ioremap(gpmc->phys_base, gpmc->memsize);
+	if (!gpmc->io_base) {
+		ret = -ENOMEM;
+		dev_err(gpmc->dev, "Failed to ioremap memory\n");
+		goto err_remap;
+	}
+
+	gpmc->ecc_used = -EINVAL;
+	spin_lock_init(&gpmc->mem_lock);
+	platform_set_drvdata(pdev, gpmc);
 
 	l = gpmc_read_reg(GPMC_REVISION);
-	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
-	/* Set smart idle mode and automatic L3 clock gating */
-	l = gpmc_read_reg(GPMC_SYSCONFIG);
-	l &= 0x03 << 3;
-	l |= (0x02 << 3) | (1 << 0);
-	gpmc_write_reg(GPMC_SYSCONFIG, l);
+	dev_info(gpmc->dev, "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
+
 	gpmc_mem_init();
 
-	/* initalize the irq_chained */
-	irq = OMAP_GPMC_IRQ_BASE;
-	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-		irq_set_chip_and_handler(irq, &dummy_irq_chip,
-						handle_simple_irq);
-		set_irq_flags(irq, IRQF_VALID);
-		irq++;
+	for (i = 0, gdev = gd->device_pdata; i < gd->num_device; gdev++, i++) {
+		ret = gpmc_setup_child(gdev);
+		if (IS_ERR_VALUE(ret))
+			dev_err(gpmc->dev, "gpmc setup on CS: %u failed\n",
+								gdev->cs);
+		else
+			gpmc->num_child++;
 	}
 
-	ret = request_irq(gpmc_irq,
-			gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
-	if (ret)
-		pr_err("gpmc: irq-%d could not claim: err %d\n",
-						gpmc_irq, ret);
+	/* XXX: This would get modified once MFD */
+	for (i = 0; i < gpmc->num_child; i++)
+		gpmc_create_child(i);
+
+	return ret;
+
+err_remap:
+	release_mem_region(gpmc->phys_base, gpmc->memsize);
+err_mem:
+err_res:
+	devm_kfree(&pdev->dev, gpmc);
 	return ret;
 }
-postcore_initcall(gpmc_init);
 
-static irqreturn_t gpmc_handle_irq(int irq, void *dev)
+static __devexit int gpmc_remove(struct platform_device *pdev)
 {
-	u8 cs;
+	struct gpmc *gpmc = platform_get_drvdata(pdev);
 
-	/* check cs to invoke the irq */
-	cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
-	if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
-		generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
+	platform_set_drvdata(pdev, NULL);
+	iounmap(gpmc->io_base);
+	release_mem_region(gpmc->phys_base, gpmc->memsize);
+	devm_kfree(&pdev->dev, gpmc);
 
-	return IRQ_HANDLED;
+	return 0;
 }
 
+static struct platform_driver gpmc_driver = {
+	.probe		= gpmc_probe,
+	.remove		= __devexit_p(gpmc_remove),
+	.driver		= {
+		.name	= DRIVER_NAME,
+		.owner	= THIS_MODULE,
+	},
+};
+
+module_platform_driver(gpmc_driver);
+
+/* Suspend - resume support */
+
 #ifdef CONFIG_ARCH_OMAP3
+/* Structure to save gpmc cs context */
+struct gpmc_cs_config {
+	u32 config1;
+	u32 config2;
+	u32 config3;
+	u32 config4;
+	u32 config5;
+	u32 config6;
+	u32 config7;
+	int is_valid;
+};
+
+/*
+ * Structure to save/restore gpmc context
+ * to support core off on OMAP3
+ */
+struct omap3_gpmc_regs {
+	u32 sysconfig;
+	u32 irqenable;
+	u32 timeout_ctrl;
+	u32 config;
+	u32 prefetch_config1;
+	u32 prefetch_config2;
+	u32 prefetch_control;
+	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
+};
+
 static struct omap3_gpmc_regs gpmc_context;
 
 void omap3_gpmc_save_context(void)
@@ -843,6 +794,159 @@ void omap3_gpmc_restore_context(void)
 }
 #endif /* CONFIG_ARCH_OMAP3 */
 
+/* GPMC NAND related */
+
+/**
+ * gpmc_read_status - read access request to get the different gpmc status
+ * @cmd: command type
+ * @return status
+ */
+int gpmc_read_status(int cmd)
+{
+	int	status = -EINVAL;
+	u32	regval = 0;
+
+	switch (cmd) {
+	case GPMC_GET_IRQ_STATUS:
+		status = gpmc_read_reg(GPMC_IRQSTATUS);
+		break;
+
+	case GPMC_PREFETCH_FIFO_CNT:
+		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
+		status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
+		break;
+
+	case GPMC_PREFETCH_COUNT:
+		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
+		status = GPMC_PREFETCH_STATUS_COUNT(regval);
+		break;
+
+	case GPMC_STATUS_BUFFER:
+		regval = gpmc_read_reg(GPMC_STATUS);
+		/* 1 : buffer is available to write */
+		status = regval & GPMC_STATUS_BUFF_EMPTY;
+		break;
+
+	default:
+		printk(KERN_ERR "gpmc_read_status: Not supported\n");
+	}
+	return status;
+}
+EXPORT_SYMBOL(gpmc_read_status);
+
+/**
+ * gpmc_nand_read - nand specific read access request
+ * @cs: chip select number
+ * @cmd: command type
+ */
+int gpmc_nand_read(int cs, int cmd)
+{
+	int rval = -EINVAL;
+
+	switch (cmd) {
+	case GPMC_NAND_DATA:
+		rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
+		break;
+
+	default:
+		printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
+	}
+	return rval;
+}
+EXPORT_SYMBOL(gpmc_nand_read);
+
+/**
+ * gpmc_nand_write - nand specific write request
+ * @cs: chip select number
+ * @cmd: command type
+ * @wval: value to write
+ */
+int gpmc_nand_write(int cs, int cmd, int wval)
+{
+	int err = 0;
+
+	switch (cmd) {
+	case GPMC_NAND_COMMAND:
+		gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
+		break;
+
+	case GPMC_NAND_ADDRESS:
+		gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
+		break;
+
+	case GPMC_NAND_DATA:
+		gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
+
+	default:
+		printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
+		err = -EINVAL;
+	}
+	return err;
+}
+EXPORT_SYMBOL(gpmc_nand_write);
+
+
+
+/**
+ * gpmc_prefetch_enable - configures and starts prefetch transfer
+ * @cs: cs (chip select) number
+ * @fifo_th: fifo threshold to be used for read/ write
+ * @dma_mode: dma mode enable (1) or disable (0)
+ * @u32_count: number of bytes to be transferred
+ * @is_write: prefetch read(0) or write post(1) mode
+ */
+int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
+				unsigned int u32_count, int is_write)
+{
+
+	if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
+		pr_err("gpmc: fifo threshold is not supported\n");
+		return -1;
+	} else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
+		/* Set the amount of bytes to be prefetched */
+		gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
+
+		/* Set dma/mpu mode, the prefetch read / post write and
+		 * enable the engine. Set which cs is has requested for.
+		 */
+		gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
+					PREFETCH_FIFOTHRESHOLD(fifo_th) |
+					ENABLE_PREFETCH |
+					(dma_mode << DMA_MPU_MODE) |
+					(0x1 & is_write)));
+
+		/*  Start the prefetch engine */
+		gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
+	} else {
+		return -EBUSY;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(gpmc_prefetch_enable);
+
+/**
+ * gpmc_prefetch_reset - disables and stops the prefetch engine
+ */
+int gpmc_prefetch_reset(int cs)
+{
+	u32 config1;
+
+	/* check if the same module/cs is trying to reset */
+	config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
+	if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
+		return -EINVAL;
+
+	/* Stop the PFPW engine */
+	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
+
+	/* Reset/disable the PFPW engine */
+	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
+
+	return 0;
+}
+EXPORT_SYMBOL(gpmc_prefetch_reset);
+
 /**
  * gpmc_enable_hwecc - enable hardware ecc functionality
  * @cs: chip select number
@@ -855,10 +959,10 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
 	unsigned int val;
 
 	/* check if ecc module is in used */
-	if (gpmc_ecc_used != -EINVAL)
+	if (gpmc->ecc_used != -EINVAL)
 		return -EINVAL;
 
-	gpmc_ecc_used = cs;
+	gpmc->ecc_used = cs;
 
 	/* clear ecc and enable bits */
 	val = ((0x00000001<<8) | 0x00000001);
@@ -906,7 +1010,7 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
 {
 	unsigned int val = 0x0;
 
-	if (gpmc_ecc_used != cs)
+	if (gpmc->ecc_used != cs)
 		return -EINVAL;
 
 	/* read ecc result */
@@ -916,7 +1020,100 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
 	/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
 	*ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
 
-	gpmc_ecc_used = -EINVAL;
+	gpmc->ecc_used = -EINVAL;
 	return 0;
 }
 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
+
+/* GPMC CLK related */
+
+static struct clk *gpmc_l3_clk;
+
+static int __init gpmc_clk_init(void)
+{
+	char *ck = NULL;
+
+	if (cpu_is_omap24xx())
+		ck = "core_l3_ck";
+	else if (cpu_is_omap34xx())
+		ck = "gpmc_fck";
+	else if (cpu_is_omap44xx())
+		ck = "gpmc_ck";
+	if (WARN_ON(!ck))
+		return -EINVAL;
+
+	gpmc_l3_clk = clk_get(NULL, ck);
+	if (WARN_ON(IS_ERR(gpmc_l3_clk)))
+		return -EINVAL;
+
+	if (WARN_ON(IS_ERR_VALUE(clk_enable(gpmc_l3_clk)))) {
+		clk_put(gpmc_l3_clk);
+		return -EIO;
+	}
+
+	return 0;
+}
+postcore_initcall(gpmc_clk_init);
+
+/* TODO: Add support for gpmc_fck to clock framework and use it */
+unsigned long gpmc_get_fclk_period(void)
+{
+	unsigned long rate = clk_get_rate(gpmc_l3_clk);
+
+	if (rate == 0) {
+		printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
+		return 0;
+	}
+
+	rate /= 1000;
+	rate = 1000000000 / rate;	/* In picoseconds */
+
+	return rate;
+}
+
+unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
+{
+	unsigned long tick_ps;
+
+	/* Calculate in picosecs to yield more exact results */
+	tick_ps = gpmc_get_fclk_period();
+
+	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
+}
+
+unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
+{
+	unsigned long tick_ps;
+
+	/* Calculate in picosecs to yield more exact results */
+	tick_ps = gpmc_get_fclk_period();
+
+	return (time_ps + tick_ps - 1) / tick_ps;
+}
+
+unsigned int gpmc_ticks_to_ns(unsigned int ticks)
+{
+	return ticks * gpmc_get_fclk_period() / 1000;
+}
+
+unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
+{
+	unsigned long ticks = gpmc_ns_to_ticks(time_ns);
+
+	return ticks * gpmc_get_fclk_period() / 1000;
+}
+
+int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
+{
+	int div;
+	u32 l;
+
+	l = sync_clk + (gpmc_get_fclk_period() - 1);
+	div = l / gpmc_get_fclk_period();
+	if (div > 4)
+		return -1;
+	if (div <= 0)
+		div = 1;
+
+	return div;
+}
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 1527929..b949c0c 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -131,6 +131,38 @@ struct gpmc_timings {
 	u16 wr_data_mux_bus;	/* WRDATAONADMUXBUS */
 };
 
+struct gpmc_config {
+	int cmd;
+	int val;
+};
+
+struct gpmc_device_pdata {
+	/* connected peripheral specific */
+	char			*name;
+	int			id;
+	/* resources configured via GPMC will be created by GPMC driver */
+	struct resource		*res;
+	unsigned		num_res;
+	void			*pdata;
+	unsigned		pdata_size;
+
+	/* GPMC specific */
+	unsigned		cs;
+	unsigned long		mem_size;
+	unsigned long		mem_start;
+	unsigned long		mem_offset;
+	struct gpmc_config	*config;
+	unsigned		num_config;
+	struct gpmc_timings	*timing;
+};
+
+struct gpmc_pdata {
+	/* GPMC_FCLK rate in picoseconds */
+	unsigned long			fclk_rate;
+	struct gpmc_device_pdata	*device_pdata;
+	unsigned			num_device;
+};
+
 extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
 extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
@@ -143,8 +175,6 @@ extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
-extern int gpmc_cs_set_reserved(int cs, int reserved);
-extern int gpmc_cs_reserved(int cs);
 extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
 					unsigned int u32_count, int is_write);
 extern int gpmc_prefetch_reset(int cs);
-- 
1.7.9.3



From afzal at ti.com  Fri Mar 23 02:36:48 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Fri, 23 Mar 2012 12:06:48 +0530
Subject: [RFC][PATCH 2/5] ARM: OMAP2+: nand: create platform data structure
Message-ID: <1332484608-21989-1-git-send-email-afzal@ti.com>

New API for updating nand platform data. This has
been created by unifying the two existing ones and
taking out gpmc hardware handling.

>From now on, platforms can call omap_nand_init to
initialize platform nand structures, it's fields.
Or can statically create the same.

Acquiring gpmc CS has been removed. Acquiring CS
probably should be avoided, if ever required, do
in GPMC driver.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/board-devkit8000.c     |    6 ++-
 arch/arm/mach-omap2/board-flash.c          |   63 ++++++++++++++--------------
 arch/arm/mach-omap2/board-flash.h          |   13 ++++--
 arch/arm/mach-omap2/board-ldp.c            |    4 +-
 arch/arm/mach-omap2/board-omap3beagle.c    |    6 ++-
 arch/arm/mach-omap2/board-omap3touchbook.c |    6 ++-
 arch/arm/mach-omap2/board-overo.c          |    5 ++-
 arch/arm/mach-omap2/board-zoom.c           |    5 ++-
 arch/arm/mach-omap2/common-board-devices.c |   46 --------------------
 arch/arm/mach-omap2/common-board-devices.h |    1 -
 10 files changed, 61 insertions(+), 94 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 11cd2a8..1a9ce9d 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -59,6 +59,7 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
 #define OMAP_DM9000_GPIO_IRQ	25
@@ -648,8 +649,9 @@ static void __init devkit8000_init(void)
 
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
-	omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
-			     ARRAY_SIZE(devkit8000_nand_partitions));
+	omap_nand_init(devkit8000_nand_partitions,
+		ARRAY_SIZE(devkit8000_nand_partitions), GPMC_CS_NUM + 1,
+		NAND_BUSWIDTH_16, NULL);
 
 	/* Ensure SDRC pins are mux'd for self-refresh */
 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 0349fd2..26c70b8 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -108,45 +108,45 @@ __init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
 		defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 
 /* Note that all values in this struct are in nanoseconds */
-static struct gpmc_timings nand_timings = {
+struct gpmc_timings nand_default_timings[1] = {
+	{
+		.sync_clk = 0,
 
-	.sync_clk = 0,
+		.cs_on = 0,
+		.cs_rd_off = 36,
+		.cs_wr_off = 36,
 
-	.cs_on = 0,
-	.cs_rd_off = 36,
-	.cs_wr_off = 36,
+		.adv_on = 6,
+		.adv_rd_off = 24,
+		.adv_wr_off = 36,
 
-	.adv_on = 6,
-	.adv_rd_off = 24,
-	.adv_wr_off = 36,
+		.we_off = 30,
+		.oe_off = 48,
 
-	.we_off = 30,
-	.oe_off = 48,
+		.access = 54,
+		.rd_cycle = 72,
+		.wr_cycle = 72,
 
-	.access = 54,
-	.rd_cycle = 72,
-	.wr_cycle = 72,
-
-	.wr_access = 30,
-	.wr_data_mux_bus = 0,
+		.wr_access = 30,
+		.wr_data_mux_bus = 0,
+	},
 };
 
-static struct omap_nand_platform_data board_nand_data = {
-	.gpmc_t		= &nand_timings,
+static struct omap_nand_platform_data omap_nand_data = {
+	.gpmc_t		= nand_default_timings,
 };
 
-void
-__init board_nand_init(struct mtd_partition *nand_parts,
-			u8 nr_parts, u8 cs, int nand_type)
+struct omap_nand_platform_data *
+__init omap_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
+				int nand_type, struct gpmc_timings *gpmc_t)
 {
-	board_nand_data.cs		= cs;
-	board_nand_data.parts		= nand_parts;
-	board_nand_data.nr_parts	= nr_parts;
-	board_nand_data.devsize		= nand_type;
-
-	board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
-	board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
-	gpmc_nand_init(&board_nand_data);
+	omap_nand_data.cs		= cs;
+	omap_nand_data.parts		= nand_parts;
+	omap_nand_data.nr_parts		= nr_parts;
+	omap_nand_data.devsize		= nand_type;
+	omap_nand_data.gpmc_t		= gpmc_t;
+
+	return &omap_nand_data;
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
 
@@ -242,6 +242,7 @@ void __init board_flash_init(struct flash_partitions partition_info[],
 	if (nandcs > GPMC_CS_NUM)
 		pr_err("NAND: Unable to find configuration in GPMC\n");
 	else
-		board_nand_init(partition_info[2].parts,
-			partition_info[2].nr_parts, nandcs, nand_type);
+		omap_nand_init(partition_info[2].parts,
+			partition_info[2].nr_parts, nandcs,
+			nand_type, nand_default_timings);
 }
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index d25503a..1d3f039 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -39,11 +39,16 @@ static inline void board_flash_init(struct flash_partitions part[],
 
 #if defined(CONFIG_MTD_NAND_OMAP2) || \
 		defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-extern void board_nand_init(struct mtd_partition *nand_parts,
-					u8 nr_parts, u8 cs, int nand_type);
+extern struct gpmc_timings nand_default_timings[];
+extern struct omap_nand_platform_data *
+__init omap_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
+				int nand_type, struct gpmc_timings *gpmc_t);
 #else
-static inline void board_nand_init(struct mtd_partition *nand_parts,
-					u8 nr_parts, u8 cs, int nand_type)
+#define	nand_default_timings	NULL
+static inline struct omap_nand_platform_data *
+omap_nand_init(struct mtd_partition *nand_parts,
+		u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
 {
+	return NULL;
 }
 #endif
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d50a562a..c3f7220 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -420,8 +420,8 @@ static void __init omap_ldp_init(void)
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
 	usb_musb_init(NULL);
-	board_nand_init(ldp_nand_partitions,
-		ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
+	omap_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
+				ZOOM_NAND_CS, 0, nand_default_timings);
 
 	omap_hsmmc_init(mmc);
 	ldp_display_init();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7be8d65..f9beece 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -51,6 +51,7 @@
 #include "mux.h"
 #include "hsmmc.h"
 #include "pm.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
 /*
@@ -542,8 +543,9 @@ static void __init omap3_beagle_init(void)
 
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
-	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
-			     ARRAY_SIZE(omap3beagle_nand_partitions));
+	omap_nand_init(omap3beagle_nand_partitions,
+		ARRAY_SIZE(omap3beagle_nand_partitions), GPMC_CS_NUM + 1,
+		NAND_BUSWIDTH_16, NULL);
 
 	/* Ensure msecure is mux'd to be able to set the RTC. */
 	omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 8842e04..6a3e77e 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -51,6 +51,7 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
 #include <asm/setup.h>
@@ -369,8 +370,9 @@ static void __init omap3_touchbook_init(void)
 	omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
-	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3touchbook_nand_partitions,
-			     ARRAY_SIZE(omap3touchbook_nand_partitions));
+	omap_nand_init(omap3touchbook_nand_partitions,
+		ARRAY_SIZE(omap3touchbook_nand_partitions), GPMC_CS_NUM + 1,
+		NAND_BUSWIDTH_16, NULL);
 
 	/* Ensure SDRC pins are mux'd for self-refresh */
 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 668533e..28cbdb5 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -57,6 +57,7 @@
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
 #define OVERO_GPIO_BT_XGATE	15
@@ -509,8 +510,8 @@ static void __init overo_init(void)
 	omap_serial_init();
 	omap_sdrc_init(mt46h32m32lf6_sdrc_params,
 				  mt46h32m32lf6_sdrc_params);
-	omap_nand_flash_init(0, overo_nand_partitions,
-			     ARRAY_SIZE(overo_nand_partitions));
+	omap_nand_init(overo_nand_partitions,
+		ARRAY_SIZE(overo_nand_partitions), GPMC_CS_NUM + 1, 0, NULL);
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
 	overo_spi_init();
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 5c20bcc..0faef81 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -114,8 +114,9 @@ static void __init omap_zoom_init(void)
 		usbhs_init(&usbhs_bdata);
 	}
 
-	board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
-						ZOOM_NAND_CS, NAND_BUSWIDTH_16);
+	omap_nand_init(zoom_nand_partitions,
+			ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS,
+			NAND_BUSWIDTH_16, nand_default_timings);
 	zoom_debugboard_init();
 	zoom_peripherals_init();
 
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 9498b0f..ab8702d 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -93,49 +93,3 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 {
 }
 #endif
-
-#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-static struct omap_nand_platform_data nand_data;
-
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
-				 int nr_parts)
-{
-	u8 cs = 0;
-	u8 nandcs = GPMC_CS_NUM + 1;
-
-	/* find out the chip-select on which NAND exists */
-	while (cs < GPMC_CS_NUM) {
-		u32 ret = 0;
-		ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-		if ((ret & 0xC00) == 0x800) {
-			printk(KERN_INFO "Found NAND on CS%d\n", cs);
-			if (nandcs > GPMC_CS_NUM)
-				nandcs = cs;
-		}
-		cs++;
-	}
-
-	if (nandcs > GPMC_CS_NUM) {
-		printk(KERN_INFO "NAND: Unable to find configuration "
-				 "in GPMC\n ");
-		return;
-	}
-
-	if (nandcs < GPMC_CS_NUM) {
-		nand_data.cs = nandcs;
-		nand_data.parts = parts;
-		nand_data.nr_parts = nr_parts;
-		nand_data.devsize = options;
-
-		printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-		if (gpmc_nand_init(&nand_data) < 0)
-			printk(KERN_ERR "Unable to register NAND device\n");
-	}
-}
-#else
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
-				 int nr_parts)
-{
-}
-#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index a0b4a428..72bb41b 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -10,6 +10,5 @@ struct ads7846_platform_data;
 
 void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 		       struct ads7846_platform_data *board_pdata);
-void omap_nand_flash_init(int opts, struct mtd_partition *parts, int n_parts);
 
 #endif /* __OMAP_COMMON_BOARD_DEVICES__ */
-- 
1.7.9.3



From afzal at ti.com  Fri Mar 23 02:36:55 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Fri, 23 Mar 2012 12:06:55 +0530
Subject: [RFC][PATCH 3/5] ARM: OMAP2+: gpmc-nand: populate gpmc configs
Message-ID: <1332484615-22030-1-git-send-email-afzal@ti.com>

Currently gpmc is configured in platform for nand.
As configuring gpmc has been moved to gpmc driver,
populate details needed for the driver to configure
gpmc. gpmc driver would configure based on this
information.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/gpmc-nand.c        |   88 ++++++++++++--------------------
 arch/arm/plat-omap/include/plat/nand.h |    8 +--
 2 files changed, 39 insertions(+), 57 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 386dec8..acec0ea 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -21,24 +21,29 @@
 #include <plat/board.h>
 #include <plat/gpmc.h>
 
-static struct resource gpmc_nand_resource = {
-	.flags		= IORESOURCE_MEM,
+
+#define	GPMC_NAND_CONFIG_NUM	3
+
+static struct gpmc_config gpmc_nand_config[GPMC_NAND_CONFIG_NUM] = {
+	{ GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND},
 };
 
-static struct platform_device gpmc_nand_device = {
+static struct gpmc_device_pdata gpmc_nand_info = {
 	.name		= "omap2-nand",
 	.id		= 0,
-	.num_resources	= 1,
-	.resource	= &gpmc_nand_resource,
+	.config		= gpmc_nand_config,
+	.num_config	= ARRAY_SIZE(gpmc_nand_config),
 };
 
-static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
-{
-	struct gpmc_timings t;
-	int err;
+static struct gpmc_timings t;
 
-	if (!gpmc_nand_data->gpmc_t)
+static struct gpmc_timings *
+gpmc_nand_retime(struct omap_nand_platform_data *gpmc_nand_data)
+{
+	if (!gpmc_nand_data->gpmc_t) {
+		pr_warn("gpmc timings not provided\n");
 		return 0;
+	}
 
 	memset(&t, 0, sizeof(t));
 	t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk;
@@ -68,56 +73,31 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data
 	t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off);
 	t.wr_cycle  = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
 
-	/* Configure GPMC */
-	if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
-		gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
-	else
-		gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
-	gpmc_cs_configure(gpmc_nand_data->cs,
-			GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
-	err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
-	if (err)
-		return err;
-
-	return 0;
+	return &t;
 }
 
-int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
+struct gpmc_device_pdata *
+__init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
 {
-	int err	= 0;
-	struct device *dev = &gpmc_nand_device.dev;
+	gpmc_nand_info.pdata = gpmc_nand_data;
+	gpmc_nand_info.pdata_size = sizeof(*gpmc_nand_data);
 
-	gpmc_nand_device.dev.platform_data = gpmc_nand_data;
+	gpmc_nand_info.cs = gpmc_nand_data->cs;
+	gpmc_nand_info.mem_size = NAND_IO_SIZE;
 
-	err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
-				&gpmc_nand_data->phys_base);
-	if (err < 0) {
-		dev_err(dev, "Cannot request GPMC CS\n");
-		return err;
-	}
+	gpmc_nand_info.timing = gpmc_nand_retime(gpmc_nand_data);
 
-	 /* Set timings in GPMC */
-	err = omap2_nand_gpmc_retime(gpmc_nand_data);
-	if (err < 0) {
-		dev_err(dev, "Unable to set gpmc timings: %d\n", err);
-		return err;
-	}
-
-	/* Enable RD PIN Monitoring Reg */
-	if (gpmc_nand_data->dev_ready) {
-		gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
-	}
-
-	err = platform_device_register(&gpmc_nand_device);
-	if (err < 0) {
-		dev_err(dev, "Unable to register NAND device\n");
-		goto out_free_cs;
-	}
-
-	return 0;
+	gpmc_nand_config[1].cmd = GPMC_CONFIG_DEV_SIZE;
+	if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
+		gpmc_nand_config[1].val = 1;
+	else
+		gpmc_nand_config[1].val = 0;
 
-out_free_cs:
-	gpmc_cs_free(gpmc_nand_data->cs);
+	gpmc_nand_config[2].cmd = GPMC_CONFIG_RDY_BSY;
+	if (gpmc_nand_data->dev_ready)
+		gpmc_nand_config[2].val = 1;
+	else
+		gpmc_nand_config[2].val = 0;
 
-	return err;
+	return &gpmc_nand_info;
 }
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 67fc506..d2daeba 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -35,10 +35,12 @@ struct omap_nand_platform_data {
 #define	NAND_IO_SIZE	4
 
 #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-extern int gpmc_nand_init(struct omap_nand_platform_data *d);
+extern struct gpmc_device_pdata *
+gpmc_nand_init(struct omap_nand_platform_data *d);
 #else
-static inline int gpmc_nand_init(struct omap_nand_platform_data *d)
+static inline struct gpmc_device_pdata *
+gpmc_nand_init(struct omap_nand_platform_data *d)
 {
-	return 0;
+	return NULL;
 }
 #endif
-- 
1.7.9.3



From afzal at ti.com  Fri Mar 23 02:37:03 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Fri, 23 Mar 2012 12:07:03 +0530
Subject: [RFC][PATCH 4/5] mtd: nand: omap2: obtain memory from resource
Message-ID: <1332484623-22070-1-git-send-email-afzal@ti.com>

gpmc being converted to driver, provides drivers
of peripheral connected memory space used by the
peripheral as memory resource.

Modify nand omap driver to obtain memory detials
from resource structure.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/plat-omap/include/plat/nand.h |    1 -
 drivers/mtd/nand/omap2.c               |   19 +++++++++++++++----
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index d2daeba..fa49fc4 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -26,7 +26,6 @@ struct omap_nand_platform_data {
 	bool			dev_ready;
 	int			gpmc_irq;
 	enum nand_io		xfer_type;
-	unsigned long		phys_base;
 	int			devsize;
 	enum omap_ecc           ecc_opt;
 };
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index b3a883e..f6c018e 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -118,6 +118,7 @@ struct omap_nand_info {
 
 	int				gpmc_cs;
 	unsigned long			phys_base;
+	unsigned long			mem_size;
 	struct completion		comp;
 	int				dma_ch;
 	int				gpmc_irq;
@@ -931,6 +932,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 	struct omap_nand_platform_data	*pdata;
 	int				err;
 	int				i, offset;
+	struct resource			*res;
 
 	pdata = pdev->dev.platform_data;
 	if (pdata == NULL) {
@@ -950,7 +952,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 	info->pdev = pdev;
 
 	info->gpmc_cs		= pdata->cs;
-	info->phys_base		= pdata->phys_base;
 
 	info->mtd.priv		= &info->nand;
 	info->mtd.name		= dev_name(&pdev->dev);
@@ -962,13 +963,23 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 	/* NAND write protect off */
 	gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
 
-	if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		err = -EINVAL;
+		dev_err(&pdev->dev, "error getting memory resource\n");
+		goto out_free_info;
+	}
+
+	info->phys_base = res->start;
+	info->mem_size = resource_size(res);
+
+	if (!request_mem_region(info->phys_base, info->mem_size,
 				pdev->dev.driver->name)) {
 		err = -EBUSY;
 		goto out_free_info;
 	}
 
-	info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
+	info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size);
 	if (!info->nand.IO_ADDR_R) {
 		err = -ENOMEM;
 		goto out_release_mem_region;
@@ -1109,7 +1120,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 	return 0;
 
 out_release_mem_region:
-	release_mem_region(info->phys_base, NAND_IO_SIZE);
+	release_mem_region(info->phys_base, info->mem_size);
 out_free_info:
 	kfree(info);
 
-- 
1.7.9.3



From afzal at ti.com  Fri Mar 23 02:37:10 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Fri, 23 Mar 2012 12:07:10 +0530
Subject: [TMP][PATCH 5/5] OMAP3EVM: Test gpmc-nand
Message-ID: <1332484630-22181-1-git-send-email-afzal@ti.com>

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/board-omap3evm.c |   82 ++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index a659e19..9ed48d4 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -23,6 +23,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/leds.h>
 #include <linux/interrupt.h>
+#include <linux/mtd/nand.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -41,6 +42,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include <plat/nand.h>
 #include <plat/board.h>
 #include <plat/usb.h>
 #include "common.h"
@@ -52,6 +54,7 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
+#include "board-flash.h"
 
 #define OMAP3_EVM_TS_GPIO	175
 #define OMAP3_EVM_EHCI_VBUS	22
@@ -102,6 +105,9 @@ static void __init omap3_evm_get_revision(void)
 	}
 }
 
+#undef CONFIG_SMSC911X
+#undef CONFIG_SMSC911X_MODULE
+
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #include <plat/gpmc-smsc911x.h>
 
@@ -533,6 +539,41 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
 	.reset_gpio_port[2]  = -EINVAL
 };
 
+/*
+ * NAND
+ */
+static struct mtd_partition omap3_evm_nand_partitions[] = {
+	/* All the partition sizes are listed in terms of NAND block size */
+	{
+		.name		= "X-Loader-NAND",
+		.offset		= 0,
+		.size		= 4 * (64 * 2048),
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	{
+		.name		= "U-Boot-NAND",
+		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x80000 */
+		.size		= 10 * (64 * 2048),
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	{
+		.name		= "Boot Env-NAND",
+
+		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x1c0000 */
+		.size		= 6 * (64 * 2048),
+	},
+	{
+		.name		= "Kernel-NAND",
+		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x280000 */
+		.size		= 40 * (64 * 2048),
+	},
+	{
+		.name		= "File System - NAND",
+		.size		= MTDPART_SIZ_FULL,
+		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x780000 */
+	},
+};
+
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux omap35x_board_mux[] __initdata = {
 	OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
@@ -632,8 +673,30 @@ static void __init omap3_evm_wl12xx_init(void)
 #endif
 }
 
+static struct gpmc_pdata gpmc_data;
+
+static struct resource gpmc_resources[] = {
+	{
+		.start = OMAP34XX_GPMC_BASE,
+		.end   = OMAP34XX_GPMC_BASE + SZ_4K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device gpmc_device = {
+	.name		= "omap-gpmc",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(gpmc_resources),
+	.resource	= gpmc_resources,
+	.dev	= {
+		.platform_data = &gpmc_data,
+	}
+};
+
 static void __init omap3_evm_init(void)
 {
+	struct omap_nand_platform_data *nand_data;
+
 	omap3_evm_get_revision();
 
 	if (cpu_is_omap3630())
@@ -684,6 +747,25 @@ static void __init omap3_evm_init(void)
 	omap3evm_init_smsc911x();
 	omap3_evm_display_init();
 	omap3_evm_wl12xx_init();
+	/* NAND */
+	nand_data = omap_nand_init(omap3_evm_nand_partitions,
+			ARRAY_SIZE(omap3_evm_nand_partitions),
+			0, NAND_BUSWIDTH_16, nand_default_timings);
+	if (nand_data == NULL) {
+		pr_err("omap_nand_init() failed\n");
+		return;
+	}
+
+	gpmc_data.device_pdata = gpmc_nand_init(nand_data);
+	if (gpmc_data.device_pdata == NULL) {
+		pr_err("gpmc_nand_init() failed\n");
+		return;
+	}
+
+	gpmc_data.num_device++;
+	gpmc_data.fclk_rate = gpmc_get_fclk_period();
+
+	platform_device_register(&gpmc_device);
 }
 
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
-- 
1.7.9.3



From mika.westerberg at iki.fi  Fri Mar 23 03:00:39 2012
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Fri, 23 Mar 2012 09:00:39 +0200
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F0020696D48E1A@AUSP01VMBX24.collaborationhost.net>
References: <4F683B36.8090101@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F0020696D488E3@AUSP01VMBX24.collaborationhost.net>
 <20120321193231.GA3740@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48AB1@AUSP01VMBX24.collaborationhost.net>
 <20120322073750.GA637@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48CAF@AUSP01VMBX24.collaborationhost.net>
 <20120322200339.GA5812@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48E1A@AUSP01VMBX24.collaborationhost.net>
Message-ID: <20120323070039.GB5812@mwesterb-mobl.ger.corp.intel.com>

On Thu, Mar 22, 2012 at 06:56:30PM -0500, H Hartley Sweeten wrote:

> I wonder if the spurious interrupts were the real problem behind what
> was causing the Oops that prompted your patch:
> 
> dma/ep93xx_dma: prevent ep93xx_dma_tasklet() to reference an empty list

No, it was a different problem spotted by Rafal. It was related to calling
dma_terminate_all() in a interrupt context or something like that.


From mika.westerberg at iki.fi  Fri Mar 23 03:04:46 2012
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Fri, 23 Mar 2012 09:04:46 +0200
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F0020696D48E3E@AUSP01VMBX24.collaborationhost.net>
References: <4F683B36.8090101@metasoft.pl>
 <20120321193836.GC3740@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48E3E@AUSP01VMBX24.collaborationhost.net>
Message-ID: <20120323070446.GC5812@mwesterb-mobl.ger.corp.intel.com>

On Thu, Mar 22, 2012 at 09:19:10PM -0500, H Hartley Sweeten wrote:

> Did you test this patch or just review it?

I tested and reviewed it.

> On my system it doesn't work. I think it has something to do with the
> changes to m2m_hw_interrupt but I haven't tracked it down yet.
> 
> It looks like what's missing is a:
> 
> 	edmac->edma->hw_submit(edmac);
> 
> But, maybe that's not needed with double buffering?

Did you try without your patch and adding my VIC hack? That's what I did when
I first got this patch and I saw no problems. I tested with audio (M2P),
mmc_spi (M2M) and dmatest (M2M).


From LW at KARO-electronics.de  Fri Mar 23 03:13:28 2012
From: LW at KARO-electronics.de (=?utf-8?Q?Lothar_Wa=C3=9Fmann?=)
Date: Fri, 23 Mar 2012 08:13:28 +0100
Subject: [PATCH 1/1] ARM iMX28: incorrect frac/div calculation
In-Reply-To: <1332457501-8153-1-git-send-email-matt@grid-net.com>
References: <1332457501-8153-1-git-send-email-matt@grid-net.com>
Message-ID: <20332.8856.841320.610752@ipc1.ka-ro>

Hi,

Matt Burtch writes:
> The frac and div values in _CLK_SET_RATE are calculated incorrectly
> for some clock rates ie. CPU clk of 454.73MHz, 392.72MHz, 261.81Mhz,
> etc.
> 
> Now the frac and div values which result in the closest actual clock
> rate to that requested is selected.  Also there are no limitations
> on what frac values can be used, as long as they fall in the valid
> (18 < frac < 35) range.
> 
> Tested on custom iMX28 board.
> 
> Signed-off-by: Matt Burtch <matt at grid-net.com>
> ---
>  arch/arm/mach-mxs/clock-mx28.c |    8 ++------
>  1 files changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
> index 5d68e41..a058b99 100644
> --- a/arch/arm/mach-mxs/clock-mx28.c
> +++ b/arch/arm/mach-mxs/clock-mx28.c
> @@ -354,19 +354,15 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
>  		}							\
>  		for (d = 1; d <= div_max; d++) {			\
>  			f = parent_rate * 18 / d / rate;		\
> -			if ((parent_rate * 18 / d) % rate)		\
> -				f++;					\
>  			if (f < 18 || f > 35)				\
>  				continue;				\
>  									\
>  			calc_rate = parent_rate * 18 / f / d;		\
> -			if (calc_rate > rate)				\
> -				continue;				\
>  									\
> -			if (rate - calc_rate < diff) {			\
> +			if (abs(rate - calc_rate) < diff) {		\
Shouldn't this actually be '<=' (also in the original code)?


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From philipp.zabel at gmail.com  Fri Mar 23 03:37:52 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Fri, 23 Mar 2012 08:37:52 +0100
Subject: [PATCH 1/8] clk: add a fixed factor clock
In-Reply-To: <1332164166-6055-2-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
 <1332164166-6055-2-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1332488272.2876.5.camel@flow>

Hi Sascha,

Am Montag, den 19.03.2012, 14:35 +0100 schrieb Sascha Hauer:
> Having fixed factors/dividers in hardware is a common pattern, so
> add a clock doing this. Currently no rate propagation is supported.
> 
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>

Tested-by: Philipp Zabel <philipp.zabel at gmail.com>

Only a few clk-gateisms remain in clk_register_fixed_factor:

diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 7c5e1fc..d99b842 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -64,14 +64,14 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
 	struct clk_fixed_factor *fix;
 	struct clk *clk;
 
-	fix = kmalloc(sizeof(struct clk_gate), GFP_KERNEL);
+	fix = kmalloc(sizeof(struct clk_fixed_factor), GFP_KERNEL);
 
 	if (!fix) {
-		pr_err("%s: could not allocate gated clk\n", __func__);
+		pr_err("%s: could not allocate fixed factor clk\n", __func__);
 		return ERR_PTR(-ENOMEM);
 	}
 
-	/* struct clk_gate assignments */
+	/* struct clk_fixed_factor assignments */
 	fix->mult = mult;
 	fix->div = div;
 
--
1.7.9.1

regards
Philipp



From egtvedt at samfundet.no  Fri Mar 23 03:38:50 2012
From: egtvedt at samfundet.no (Hans-Christian Egtvedt)
Date: Fri, 23 Mar 2012 08:38:50 +0100
Subject: [PATCH] avr32: fix build failures from mis-naming of atmel_nand.h
In-Reply-To: <4F6B316F.5080307@atmel.com>
References: <1332296128-16262-1-git-send-email-paul.gortmaker@windriver.com>
 <20120321072632.GA15703@samfundet.no> <4F6990AF.2000004@atmel.com>
 <20120322051840.GC923@windriver.com>
 <20120322123327.GA14690@samfundet.no> <4F6B316F.5080307@atmel.com>
Message-ID: <20120323073850.GB31010@samfundet.no>

Around Thu 22 Mar 2012 15:04:31 +0100 or thereabout, Nicolas Ferre wrote:
> On 03/22/2012 01:33 PM, Hans-Christian Egtvedt :
>> Around Thu 22 Mar 2012 01:18:40 -0400 or thereabout, Paul Gortmaker wrote:

<snipp Atmel NAND cleanup>

>>>> Yes, we need to fix this. But I would not like to see this
>>>> "platform_data/atmel.h" renamed: I think that this file was designed to
>>>> collect several common platform data (ie: not just NAND related).
>>>>
>>>> So maybe we should just rename the entry that exists in
>>>> mach-at32ap/include/mach/board.h
>>>> and remove all occurrences of platform_data/atmel_nand.h
>>>
>>> Funny, since this is what I did 1st before I re-read the original commit
>>> log in more detail. :)  Oh well.  Here is the alternate solution.  You
>>> guys can pick whichever one you like best.  I compile tested this one
>>> as well.
>> 
>> I'll leave it to Nicolas to sign-off on this, but the changes look fine for
>> me.
> 
> Ok, which way do you want to follow for inclusion in mainline? I take it
> through arm-soc?

I have not gotten my key signed by any kernel developers yet, so typically
I've asked people to take it through Andrew's tree.

<snipp>

-- 
HcE


From philipp.zabel at gmail.com  Fri Mar 23 03:41:29 2012
From: philipp.zabel at gmail.com (Philipp Zabel)
Date: Fri, 23 Mar 2012 08:41:29 +0100
Subject: [PATCH 1/8] clk: add a fixed factor clock
In-Reply-To: <1332164166-6055-2-git-send-email-s.hauer@pengutronix.de>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
 <1332164166-6055-2-git-send-email-s.hauer@pengutronix.de>
Message-ID: <1332488489.2876.8.camel@flow>

Am Montag, den 19.03.2012, 14:35 +0100 schrieb Sascha Hauer:
> Having fixed factors/dividers in hardware is a common pattern, so
> add a clock doing this. Currently no rate propagation is supported.

Also, could I convince you to move struct clk_fixed_factor into
clk-provider.h and provide a DEFINE_CLK_FIXED_FACTOR macro to align with
the other basic clocks?

---
 drivers/clk/clk-fixed-factor.c |   15 +++++++++------
 include/linux/clk-private.h    |   28 ++++++++++++++++++++++++++++
 include/linux/clk-provider.h   |   19 +++++++++++++++++++
 3 files changed, 56 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index d99b842..8ca427a 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -12,12 +12,15 @@
 #include <linux/slab.h>
 #include <linux/err.h>
 
-struct clk_fixed_factor {
-	struct clk_hw	hw;
-	unsigned int	mult;
-	unsigned int	div;
-	char		*parent[1];
-};
+/*
+ * DOC: basic fixed multiplier and divider clock that cannot gate
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is fixed.  clk->rate = parent->rate / div * mult
+ * parent - fixed parent.  No clk_set_parent support
+ */
 
 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
 
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 5e4312b..9501eab 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -170,6 +170,34 @@ extern struct clk_ops clk_mux_ops;
 		.flags = _flags,				\
 	};
 
+extern struct clk_ops clk_fixed_factor_ops;
+
+#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name,		\
+				_parent_ptr, _flags,		\
+				_mult, _div)			\
+	static struct clk _name;				\
+	static struct clk *_name##_parents[] = {		\
+		_parent_ptr,					\
+	};							\
+	static struct clk_fixed_factor _name##_hw = {		\
+		.hw = {						\
+			.clk = &_name,				\
+		},						\
+		.mult = _mult,					\
+		.div = _div,					\
+		.parent[0] = _parent_name,			\
+	};							\
+	static struct clk _name = {				\
+		.name = #_name,					\
+		.ops = &clk_fixed_factor_ops,			\
+		.hw = &_name##_hw.hw,				\
+		.parent_names = _name##_hw.parent,		\
+		.num_parents =					\
+			ARRAY_SIZE(_name##_hw.parent),		\
+		.parents = _name##_parents,			\
+		.flags = _flags,				\
+	};
+
 /**
  * __clk_init - initialize the data structures in a struct clk
  * @dev:	device initializing this clk, placeholder for now
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 21ca2f8..b58f846 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -257,6 +257,25 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_mux_flags, spinlock_t *lock);
 
+/**
+ * struct clk_fixed_factor - fixed multiplier and divider clock
+ *
+ * @hw:         handle between common and hardware-specific interfaces
+ * @mult:	multiplier
+ * @div:        divider
+ *
+ * Clock with a fixed multiplier and divider. The output frequency is the
+ * parent clock rate divided by div and multiplied by mult.
+ * Implements .recalc_rate, .set_rate and .round_rate
+ */
+
+struct clk_fixed_factor {
+        struct clk_hw   hw;
+        unsigned int    mult;
+        unsigned int    div;
+        char            *parent[1];
+};
+
 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div);
-- 
1.7.9.1




From govindraj.raja at ti.com  Fri Mar 23 03:47:29 2012
From: govindraj.raja at ti.com (Raja, Govindraj)
Date: Fri, 23 Mar 2012 13:17:29 +0530
Subject: [PATCH 0/3] OMAP2+: UART: Enable tx wakeup + remove cpu checks
In-Reply-To: <alpine.DEB.2.00.1203221740140.24425@utopia.booyaka.com>
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
 <87limurpsx.fsf@ti.com>
 <CAMrsUdLtC0iVk2qDDDXj2tteAzP5UQJXNvsCoJLEC9Yty2QjvQ@mail.gmail.com>
 <alpine.DEB.2.00.1203221740140.24425@utopia.booyaka.com>
Message-ID: <CAMrsUdKn6i9cNfHia+TqZ2By7V3NhXHF+1Bt-eadJd0ZWkERNQ@mail.gmail.com>

Hi Paul,

On Fri, Mar 23, 2012 at 5:10 AM, Paul Walmsley <paul at pwsan.com> wrote:
> Hi
>
> On Thu, 22 Mar 2012, Raja, Govindraj wrote:
>
>> Sorry I for got to add that, here are details on what was tested.
>>
>> 1.) OMAP2430 SDP : Boot tested with uart1 as console.
>>
>> 2.) OMAP3430 SDP: Boot test, suspend/resume tests, retention off mode
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(checking retention and off mode count
>> in cpu idle cases)
>>
>> 3.) OMAP3630 - Beagle XM: ?Boot test, suspend/resume tests, retention off mode
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (checking retention and
>> off mode count in cpu idle cases)
>>
>> 4.) OMAP4430 - PANDA: Boot test, suspend/resume tests
>>
>> 5.) OMAP4460 - PANDA: Boot test.
>
> What kernel .config was used for these tests?

omap2plus_defconfig was used.

the same kernel image was tested with all these boards.
(kernel image was built along with initramfs support
using minimal busybox filesystem)

--
Thanks,
Govindraj.R


From viresh.kumar at st.com  Fri Mar 23 03:49:27 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 23 Mar 2012 13:19:27 +0530
Subject: [PATCH 2/2] ARM: GIC: Create common infrastructure for GIC DT bindings
In-Reply-To: <4bfe7af3761f6f40506a2089fd67866015f6d7f3.1332488625.git.viresh.kumar@st.com>
References: <4bfe7af3761f6f40506a2089fd67866015f6d7f3.1332488625.git.viresh.kumar@st.com>
Message-ID: <23b4d2ea357a7a785b6c42d0fa7ae9478bad552b.1332488625.git.viresh.kumar@st.com>

Few platforms define there own struct of_device_id[] for GIC. They don't
do anything specific in init_irq() other than of_irq_init().

This patch creates this struct array in gic.c and make other platforms use it.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/common/gic.c               |   10 ++++++++++
 arch/arm/include/asm/hardware/gic.h |    1 +
 arch/arm/mach-exynos/common.c       |    9 +--------
 arch/arm/mach-highbank/highbank.c   |    7 +------
 arch/arm/mach-imx/mach-imx6q.c      |    2 +-
 arch/arm/mach-tegra/common.c        |    7 +------
 arch/arm/mach-ux500/cpu.c           |    7 +------
 arch/arm/mach-vexpress/v2m.c        |   12 +-----------
 8 files changed, 17 insertions(+), 38 deletions(-)

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index aa52699..77afdae 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -781,4 +781,14 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
 	gic_cnt++;
 	return 0;
 }
+
+static const struct of_device_id gic_of_match[] __initconst = {
+	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ /* Sentinel */ }
+};
+
+void __init gic_init_irq(void)
+{
+	of_irq_init(gic_of_match);
+}
 #endif
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 4b1ce6c..7bce4bd 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -42,6 +42,7 @@ void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
 		    u32 offset, struct device_node *);
 int gic_of_init(struct device_node *node, struct device_node *parent);
 void gic_secondary_init(unsigned int);
+void __init gic_init_irq(void);
 void gic_handle_irq(struct pt_regs *regs);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 85ed8b5..76f6079 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -502,13 +502,6 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
 	}
 }
 
-#ifdef CONFIG_OF
-static const struct of_device_id exynos4_dt_irq_match[] = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-	{},
-};
-#endif
-
 void __init exynos4_init_irq(void)
 {
 	int irq;
@@ -520,7 +513,7 @@ void __init exynos4_init_irq(void)
 		gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 #ifdef CONFIG_OF
 	else
-		of_irq_init(exynos4_dt_irq_match);
+		gic_init_irq();
 #endif
 
 	for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 410a112..42b30c6 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -80,14 +80,9 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
 			  HB_JUMP_TABLE_PHYS(cpu) + 15);
 }
 
-const static struct of_device_id irq_match[] = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-	{}
-};
-
 static void __init highbank_init_irq(void)
 {
-	of_irq_init(irq_match);
+	gic_init_irq();
 	l2x0_of_init(0, ~0UL);
 }
 
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 7696dfa..ebaf6c5 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -105,7 +105,6 @@ static int __init imx6q_gpio_add_irq_domain(struct device_node *np,
 }
 
 static const struct of_device_id imx6q_irq_match[] __initconst = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 	{ .compatible = "fsl,imx6q-gpio", .data = imx6q_gpio_add_irq_domain, },
 	{ /* sentinel */ }
 };
@@ -115,6 +114,7 @@ static void __init imx6q_init_irq(void)
 	l2x0_of_init(0, ~0UL);
 	imx_src_init();
 	imx_gpc_init();
+	gic_init_irq();
 	of_irq_init(imx6q_irq_match);
 }
 
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 22df10f..c8d6208 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -52,15 +52,10 @@ u32 tegra_uart_config[3] = {
 };
 
 #ifdef CONFIG_OF
-static const struct of_device_id tegra_dt_irq_match[] __initconst = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
-	{ }
-};
-
 void __init tegra_dt_init_irq(void)
 {
 	tegra_init_irq();
-	of_irq_init(tegra_dt_irq_match);
+	gic_init_irq();
 }
 #endif
 
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index d11f389..3bb6f13 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -30,11 +30,6 @@
 
 void __iomem *_PRCMU_BASE;
 
-static const struct of_device_id ux500_dt_irq_match[] = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-	{},
-};
-
 void __init ux500_init_irq(void)
 {
 	void __iomem *dist_base;
@@ -51,7 +46,7 @@ void __init ux500_init_irq(void)
 
 #ifdef CONFIG_OF
 	if (of_have_populated_dt())
-		of_irq_init(ux500_dt_irq_match);
+		gic_init_irq();
 	else
 #endif
 		gic_init(0, 29, dist_base, cpu_base);
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 47cdcca..3d875f2 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -619,16 +619,6 @@ void __init v2m_dt_init_early(void)
 	versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
 }
 
-static  struct of_device_id vexpress_irq_match[] __initdata = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-	{}
-};
-
-static void __init v2m_dt_init_irq(void)
-{
-	of_irq_init(vexpress_irq_match);
-}
-
 static void __init v2m_dt_timer_init(void)
 {
 	struct device_node *node;
@@ -677,7 +667,7 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
 	.dt_compat	= v2m_dt_match,
 	.map_io		= v2m_dt_map_io,
 	.init_early	= v2m_dt_init_early,
-	.init_irq	= v2m_dt_init_irq,
+	.init_irq	= gic_init_irq,
 	.timer		= &v2m_dt_timer,
 	.init_machine	= v2m_dt_init,
 	.handle_irq	= gic_handle_irq,
-- 
1.7.8.110.g4cb5d



From viresh.kumar at st.com  Fri Mar 23 03:49:26 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 23 Mar 2012 13:19:26 +0530
Subject: [PATCH 1/2] ARM: VIC: Create common infrastructure for vic DT bindings
Message-ID: <4bfe7af3761f6f40506a2089fd67866015f6d7f3.1332488625.git.viresh.kumar@st.com>

Few platforms define there own struct of_device_id[] for vic pl19*. They don't
do anything specific in init_irq() other than of_irq_init().

This patch creates this struct array in vic.c and make other platforms use it.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/common/vic.c               |   14 +++++++++++++-
 arch/arm/include/asm/hardware/vic.h |    3 ++-
 arch/arm/mach-picoxcell/common.c    |   12 +-----------
 arch/arm/mach-spear6xx/spear6xx.c   |   12 +-----------
 4 files changed, 17 insertions(+), 24 deletions(-)

diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 7a66311..190813e 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -398,7 +398,8 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 }
 
 #ifdef CONFIG_OF
-int __init vic_of_init(struct device_node *node, struct device_node *parent)
+static int __init vic_of_init(struct device_node *node, struct device_node
+		*parent)
 {
 	void __iomem *regs;
 	int irq_base;
@@ -423,6 +424,17 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
 
 	return -EIO;
 }
+
+static const struct of_device_id vic_of_match[] __initconst = {
+	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ .compatible = "arm,pl192-vic", .data = vic_of_init, },
+	{ /* Sentinel */ }
+};
+
+void __init vic_init_irq(void)
+{
+	of_irq_init(vic_of_match);
+}
 #endif /* CONFIG OF */
 
 /*
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
index e14af1a..02056a8 100644
--- a/arch/arm/include/asm/hardware/vic.h
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -42,6 +42,7 @@
 
 #ifndef __ASSEMBLY__
 #include <linux/compiler.h>
+#include <linux/init.h>
 #include <linux/types.h>
 
 struct device_node;
@@ -50,7 +51,7 @@ struct pt_regs;
 void __vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources,
 		u32 resume_sources, struct device_node *node);
 void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
-int vic_of_init(struct device_node *node, struct device_node *parent);
+void __init vic_init_irq(void);
 void vic_handle_irq(struct pt_regs *regs);
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index a2e8ae8..fa0d7e9 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -68,16 +68,6 @@ static const char *picoxcell_dt_match[] = {
 	NULL
 };
 
-static const struct of_device_id vic_of_match[] __initconst = {
-	{ .compatible = "arm,pl192-vic", .data = vic_of_init, },
-	{ /* Sentinel */ }
-};
-
-static void __init picoxcell_init_irq(void)
-{
-	of_irq_init(vic_of_match);
-}
-
 static void picoxcell_wdt_restart(char mode, const char *cmd)
 {
 	/*
@@ -95,7 +85,7 @@ static void picoxcell_wdt_restart(char mode, const char *cmd)
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
 	.map_io		= picoxcell_map_io,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= picoxcell_init_irq,
+	.init_irq	= vic_init_irq,
 	.handle_irq	= vic_handle_irq,
 	.timer		= &picoxcell_timer,
 	.init_machine	= picoxcell_init_machine,
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14..d436118 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -102,19 +102,9 @@ static const char *spear600_dt_board_compat[] = {
 	NULL
 };
 
-static const struct of_device_id vic_of_match[] __initconst = {
-	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
-	{ /* Sentinel */ }
-};
-
-static void __init spear6xx_dt_init_irq(void)
-{
-	of_irq_init(vic_of_match);
-}
-
 DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
 	.map_io		=	spear6xx_map_io,
-	.init_irq	=	spear6xx_dt_init_irq,
+	.init_irq	=	vic_init_irq,
 	.handle_irq	=	vic_handle_irq,
 	.timer		=	&spear6xx_timer,
 	.init_machine	=	spear600_dt_init,
-- 
1.7.8.110.g4cb5d



From linus.walleij at linaro.org  Fri Mar 23 04:17:44 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 23 Mar 2012 09:17:44 +0100
Subject: [PATCH] serial: PL011: move interrupt clearing
In-Reply-To: <CAOh2x=kqTZxzyEMEF0bYFQ0a0zMEQNZWrzw48e1WFiMxYpRSeg@mail.gmail.com>
References: <1332357318-8017-1-git-send-email-linus.walleij@linaro.org>
 <CAOh2x==5QHEcA3h216p8rJukx0LR=cVcGYN84aqzw=fnhu8Y-g@mail.gmail.com>
 <CACRpkdate+sQJvS8H7qNXiwe6c+F58g=OF0Qg=TxxnTwPXBrYQ@mail.gmail.com>
 <CAOh2x=kqTZxzyEMEF0bYFQ0a0zMEQNZWrzw48e1WFiMxYpRSeg@mail.gmail.com>
Message-ID: <CACRpkdY+vmSsqH80ty6H5vFbc-SjRSeNboCv5e5O0OtkAVSTSg@mail.gmail.com>

On Fri, Mar 23, 2012 at 4:39 AM, viresh kumar <viresh.linux at gmail.com> wrote:

> That's strange. When i check my mail on @st.com id, i see myself in cc
> list, but on
> gmail i see following cc list in your first mail.
(...)
>
> Why don't i see myself in cc here?

No clue :-(

On *my* gmail it looks like this:

Cc: linux-arm-kernel at lists.infradead.org,
	Chanho Min <chanho0207 at gmail.com>,
	Jong-Sung Kim <neidhard.kim at lge.com>,
	Viresh Kumar <viresh.kumar at st.com>,
	Linus Walleij <linus.walleij at linaro.org>,
	Shreshtha Kumar Sahu <shreshthakumar.sahu at stericsson.com>,
	Russell King <linux at arm.linux.org.uk>,
	stable <stable at vger.kernel.org>

Trust no gmail...

Linus Walleij


From tom.leiming at gmail.com  Fri Mar 23 04:20:25 2012
From: tom.leiming at gmail.com (Ming Lei)
Date: Fri, 23 Mar 2012 16:20:25 +0800
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A831823816@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831823816@DBDE01.ent.ti.com>
Message-ID: <CACVXFVPTsFY7UJMH5jZa16V0KYEZB=o7WRYqVEYyNJw1tMq-yw@mail.gmail.com>

On Wed, Mar 21, 2012 at 7:29 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> On Mon, Mar 19, 2012 at 17:14:30, Ming Lei wrote:
>> On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>> >
>> > I think you made very good point here. With the above patch, we are almost missing the capability of registering dmtimer as a clocksource for OMAP.
>> > It will always use 32k-counter, and never fall back to dmtimer.
>> >
>> > Then the only options we have here is,
>> >
>> > 1) Register both the timers, 32k-counter and dmtimer for clocksource; let
>> > ? Kernel pick up best rating clocksource out of these two.
>> >
>> > ? In case of OMAP1/2/3/4, kernel will use dmtimer, since it has better
>> > ? Rating. User can choose the 32k-counter clocksource via bootargs.
>> >
>> > ? Impact: without bootargs for clocksource selection, kernel will choose
>> > ? ? dmtimer, impacting loss of time during suspend/resume.
>> >
>> >
>> > 2) Let the current code be as is, means, the clocksource registration will
>> > ? Happened based on "#ifdef CONFIG_OMAP_32K_TIMER" and this option
>> > ? selection will be Controlled by Kconfig rules.
>>
>> How about the 3rd option?
>>
>> 3), take the way in your patch 1) at default, but will switch to
>> register dmtimer
>> directly and bypass 32k-counter if user need it via kernel parameter.
>>
>> As far as I can think of, the situations required for dmtimer are high-frequency
>> perf sample and high precision trace points, so looks it is OK to take
>> 32k-counter
>> at default.
>>
> But if you register both the timers (dmtimer & 32ksync), then initially kernel will only pick up dmtimer, as this has better rating. And late in

Looks not so, I found that 32ksync is always selected as the default
clocksource if both are registered.

> the boot sequence clocksource switch will happen, base on
> kernel parameter (clocksource=).
>
> So logically dmtimer will be always used as a default here.

Not so at least on my Pandaboard.


Thanks,
-- 
Ming Lei


From viresh.kumar at st.com  Fri Mar 23 04:16:18 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 23 Mar 2012 13:46:18 +0530
Subject: [PATCH] SPEAr: Use CLKDEV_INIT for defining clk_lookups
Message-ID: <57103011de8747743f95eb41c8dc30c632d097a8.1332490263.git.viresh.kumar@st.com>

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
Arnd,

I have applied this patch after applying Stefan's patch:
"ARM: SPEAr600: Change FSMC and SMI clock names"

I have applied both these patches in my following branch:
spear-dt

in following repo
git://stlinux.com/spear/linux-2.6.git

You can pull them directly if they look fine to you.

 arch/arm/mach-spear3xx/clock.c |  111 ++++++++++++++++++++--------------------
 arch/arm/mach-spear6xx/clock.c |   80 ++++++++++++++--------------
 2 files changed, 96 insertions(+), 95 deletions(-)

diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6c4841f..6b2cd9b 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -11,6 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/clkdev.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
@@ -652,85 +653,85 @@ static struct clk pwm_clk = {
 
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-	{ .con_id = "apb_pclk",		.clk = &dummy_apb_pclk},
+	CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
 	/* root clks */
-	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
-	{ .con_id = "osc_24m_clk",	.clk = &osc_24m_clk},
+	CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+	CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
 	/* clock derived from 32 KHz osc clk */
-	{ .dev_id = "rtc-spear",	.clk = &rtc_clk},
+	CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
 	/* clock derived from 24 MHz osc clk */
-	{ .con_id = "pll1_clk",		.clk = &pll1_clk},
-	{ .con_id = "pll3_48m_clk",	.clk = &pll3_48m_clk},
-	{ .dev_id = "wdt",		.clk = &wdt_clk},
+	CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+	CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+	CLKDEV_INIT("wdt", NULL, &wdt_clk),
 	/* clock derived from pll1 clk */
-	{ .con_id = "cpu_clk",		.clk = &cpu_clk},
-	{ .con_id = "ahb_clk",		.clk = &ahb_clk},
-	{ .con_id = "uart_synth_clk",	.clk = &uart_synth_clk},
-	{ .con_id = "firda_synth_clk",	.clk = &firda_synth_clk},
-	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
-	{ .con_id = "gpt1_synth_clk",	.clk = &gpt1_synth_clk},
-	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
-	{ .dev_id = "uart",		.clk = &uart_clk},
-	{ .dev_id = "firda",		.clk = &firda_clk},
-	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
-	{ .dev_id = "gpt1",		.clk = &gpt1_clk},
-	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
+	CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+	CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+	CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+	CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+	CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+	CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
+	CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+	CLKDEV_INIT("uart", NULL, &uart_clk),
+	CLKDEV_INIT("firda", NULL, &firda_clk),
+	CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+	CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+	CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
 	/* clock derived from pll3 clk */
-	{ .dev_id = "designware_udc",   .clk = &usbd_clk},
-	{ .con_id = "usbh_clk",		.clk = &usbh_clk},
+	CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+	CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
 	/* clock derived from ahb clk */
-	{ .con_id = "apb_clk",		.clk = &apb_clk},
-	{ .dev_id = "i2c_designware.0",	.clk = &i2c_clk},
-	{ .dev_id = "dma",		.clk = &dma_clk},
-	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
-	{ .dev_id = "gmac",		.clk = &gmac_clk},
-	{ .dev_id = "smi",		.clk = &smi_clk},
-	{ .dev_id = "c3",		.clk = &c3_clk},
+	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+	CLKDEV_INIT("i2c_designware.0", NULL, &i2c_clk),
+	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+	CLKDEV_INIT("gmac", NULL, &gmac_clk),
+	CLKDEV_INIT("smi", NULL, &smi_clk),
+	CLKDEV_INIT("c3", NULL, &c3_clk),
 	/* clock derived from apb clk */
-	{ .dev_id = "adc",		.clk = &adc_clk},
-	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
-	{ .dev_id = "gpio",		.clk = &gpio_clk},
+	CLKDEV_INIT("adc", NULL, &adc_clk),
+	CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
+	CLKDEV_INIT("gpio", NULL, &gpio_clk),
 };
 
 /* array of all spear 300 clock lookups */
 #ifdef CONFIG_MACH_SPEAR300
 static struct clk_lookup spear300_clk_lookups[] = {
-	{ .dev_id = "clcd",		.clk = &clcd_clk},
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
-	{ .dev_id = "gpio1",		.clk = &gpio1_clk},
-	{ .dev_id = "keyboard",		.clk = &kbd_clk},
-	{ .dev_id = "sdhci",		.clk = &sdhci_clk},
+	CLKDEV_INIT("clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+	CLKDEV_INIT("gpio1", NULL, &gpio1_clk),
+	CLKDEV_INIT("keyboard", NULL, &kbd_clk),
+	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
 };
 #endif
 
 /* array of all spear 310 clock lookups */
 #ifdef CONFIG_MACH_SPEAR310
 static struct clk_lookup spear310_clk_lookups[] = {
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
-	{ .con_id = "emi",		.clk = &emi_clk},
-	{ .dev_id = "uart1",		.clk = &uart1_clk},
-	{ .dev_id = "uart2",		.clk = &uart2_clk},
-	{ .dev_id = "uart3",		.clk = &uart3_clk},
-	{ .dev_id = "uart4",		.clk = &uart4_clk},
-	{ .dev_id = "uart5",		.clk = &uart5_clk},
+	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+	CLKDEV_INIT(NULL, "emi", &emi_clk),
+	CLKDEV_INIT("uart1", NULL, &uart1_clk),
+	CLKDEV_INIT("uart2", NULL, &uart2_clk),
+	CLKDEV_INIT("uart3", NULL, &uart3_clk),
+	CLKDEV_INIT("uart4", NULL, &uart4_clk),
+	CLKDEV_INIT("uart5", NULL, &uart5_clk),
 };
 #endif
 
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
 static struct clk_lookup spear320_clk_lookups[] = {
-	{ .dev_id = "clcd",		.clk = &clcd_clk},
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
-	{ .dev_id = "i2c_designware.1",	.clk = &i2c1_clk},
-	{ .con_id = "emi",		.clk = &emi_clk},
-	{ .dev_id = "pwm",		.clk = &pwm_clk},
-	{ .dev_id = "sdhci",		.clk = &sdhci_clk},
-	{ .dev_id = "c_can_platform.0",	.clk = &can0_clk},
-	{ .dev_id = "c_can_platform.1",	.clk = &can1_clk},
-	{ .dev_id = "ssp-pl022.1",	.clk = &ssp1_clk},
-	{ .dev_id = "ssp-pl022.2",	.clk = &ssp2_clk},
-	{ .dev_id = "uart1",		.clk = &uart1_clk},
-	{ .dev_id = "uart2",		.clk = &uart2_clk},
+	CLKDEV_INIT("clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+	CLKDEV_INIT("i2c_designware.1", NULL, &i2c1_clk),
+	CLKDEV_INIT(NULL, "emi", &emi_clk),
+	CLKDEV_INIT("pwm", NULL, &pwm_clk),
+	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
+	CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
+	CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
+	CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
+	CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
+	CLKDEV_INIT("uart1", NULL, &uart1_clk),
+	CLKDEV_INIT("uart2", NULL, &uart2_clk),
 };
 #endif
 
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index f051804..5a46980 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -623,53 +623,53 @@ static struct clk dummy_apb_pclk;
 
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-	{ .con_id = "apb_pclk",		.clk = &dummy_apb_pclk},
+	CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
 	/* root clks */
-	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
-	{ .con_id = "osc_30m_clk",	.clk = &osc_30m_clk},
+	CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+	CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk),
 	/* clock derived from 32 KHz os		 clk */
-	{ .dev_id = "rtc-spear",	.clk = &rtc_clk},
+	CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
 	/* clock derived from 30 MHz os		 clk */
-	{ .con_id = "pll1_clk",		.clk = &pll1_clk},
-	{ .con_id = "pll3_48m_clk",	.clk = &pll3_48m_clk},
-	{ .dev_id = "wdt",		.clk = &wdt_clk},
+	CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+	CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+	CLKDEV_INIT("wdt", NULL, &wdt_clk),
 	/* clock derived from pll1 clk */
-	{ .con_id = "cpu_clk",		.clk = &cpu_clk},
-	{ .con_id = "ahb_clk",		.clk = &ahb_clk},
-	{ .con_id = "uart_synth_clk",	.clk = &uart_synth_clk},
-	{ .con_id = "firda_synth_clk",	.clk = &firda_synth_clk},
-	{ .con_id = "clcd_synth_clk",	.clk = &clcd_synth_clk},
-	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
-	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
-	{ .con_id = "gpt3_synth_clk",	.clk = &gpt3_synth_clk},
-	{ .dev_id = "d0000000.serial",	.clk = &uart0_clk},
-	{ .dev_id = "d0080000.serial",	.clk = &uart1_clk},
-	{ .dev_id = "firda",		.clk = &firda_clk},
-	{ .dev_id = "clcd",		.clk = &clcd_clk},
-	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
-	{ .dev_id = "gpt1",		.clk = &gpt1_clk},
-	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
-	{ .dev_id = "gpt3",		.clk = &gpt3_clk},
+	CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+	CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+	CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+	CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+	CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk),
+	CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+	CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+	CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk),
+	CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk),
+	CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk),
+	CLKDEV_INIT("firda", NULL, &firda_clk),
+	CLKDEV_INIT("clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+	CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+	CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
+	CLKDEV_INIT("gpt3", NULL, &gpt3_clk),
 	/* clock derived from pll3 clk */
-	{ .dev_id = "designware_udc",	.clk = &usbd_clk},
-	{ .con_id = "usbh.0_clk",	.clk = &usbh0_clk},
-	{ .con_id = "usbh.1_clk",	.clk = &usbh1_clk},
+	CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+	CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+	CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
 	/* clock derived from ahb clk */
-	{ .con_id = "apb_clk",		.clk = &apb_clk},
-	{ .dev_id = "d0200000.i2c",	.clk = &i2c_clk},
-	{ .dev_id = "dma",		.clk = &dma_clk},
-	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
-	{ .dev_id = "gmac",		.clk = &gmac_clk},
-	{ .dev_id = "fc000000.flash",	.clk = &smi_clk},
-	{ .dev_id = "d1800000.flash",	.clk = &fsmc_clk},
+	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+	CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
+	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+	CLKDEV_INIT("gmac", NULL, &gmac_clk),
+	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
+	CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk),
 	/* clock derived from apb clk */
-	{ .dev_id = "adc",		.clk = &adc_clk},
-	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
-	{ .dev_id = "ssp-pl022.1",	.clk = &ssp1_clk},
-	{ .dev_id = "ssp-pl022.2",	.clk = &ssp2_clk},
-	{ .dev_id = "f0100000.gpio",	.clk = &gpio0_clk},
-	{ .dev_id = "fc980000.gpio",	.clk = &gpio1_clk},
-	{ .dev_id = "d8100000.gpio",	.clk = &gpio2_clk},
+	CLKDEV_INIT("adc", NULL, &adc_clk),
+	CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
+	CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
+	CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
+	CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk),
+	CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk),
+	CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk),
 };
 
 void __init spear6xx_clk_init(void)
-- 
1.7.8.110.g4cb5d



From s.hauer at pengutronix.de  Fri Mar 23 04:40:00 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 23 Mar 2012 09:40:00 +0100
Subject: [PATCH 1/8] clk: add a fixed factor clock
In-Reply-To: <1332488272.2876.5.camel@flow>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
 <1332164166-6055-2-git-send-email-s.hauer@pengutronix.de>
 <1332488272.2876.5.camel@flow>
Message-ID: <20120323084000.GJ3852@pengutronix.de>

Hi Philipp,

On Fri, Mar 23, 2012 at 08:37:52AM +0100, Philipp Zabel wrote:
> Hi Sascha,
> 
> Am Montag, den 19.03.2012, 14:35 +0100 schrieb Sascha Hauer:
> > Having fixed factors/dividers in hardware is a common pattern, so
> > add a clock doing this. Currently no rate propagation is supported.

Also this is not true anymore, rate propagation now is supported.

> > 
> > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> 
> Tested-by: Philipp Zabel <philipp.zabel at gmail.com>
> 
> Only a few clk-gateisms remain in clk_register_fixed_factor:

Thanks, I'll integrate this.

Sascha

> diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
> index 7c5e1fc..d99b842 100644
> --- a/drivers/clk/clk-fixed-factor.c
> +++ b/drivers/clk/clk-fixed-factor.c
> @@ -64,14 +64,14 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
>  	struct clk_fixed_factor *fix;
>  	struct clk *clk;
>  
> -	fix = kmalloc(sizeof(struct clk_gate), GFP_KERNEL);
> +	fix = kmalloc(sizeof(struct clk_fixed_factor), GFP_KERNEL);
>  
>  	if (!fix) {
> -		pr_err("%s: could not allocate gated clk\n", __func__);
> +		pr_err("%s: could not allocate fixed factor clk\n", __func__);
>  		return ERR_PTR(-ENOMEM);
>  	}
>  
> -	/* struct clk_gate assignments */
> +	/* struct clk_fixed_factor assignments */
>  	fix->mult = mult;
>  	fix->div = div;
>  
> --
> 1.7.9.1
> 
> regards
> Philipp
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Fri Mar 23 04:42:06 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 23 Mar 2012 09:42:06 +0100
Subject: [PATCH 1/8] clk: add a fixed factor clock
In-Reply-To: <1332488489.2876.8.camel@flow>
References: <1332164166-6055-1-git-send-email-s.hauer@pengutronix.de>
 <1332164166-6055-2-git-send-email-s.hauer@pengutronix.de>
 <1332488489.2876.8.camel@flow>
Message-ID: <20120323084206.GK3852@pengutronix.de>

On Fri, Mar 23, 2012 at 08:41:29AM +0100, Philipp Zabel wrote:
> Am Montag, den 19.03.2012, 14:35 +0100 schrieb Sascha Hauer:
> > Having fixed factors/dividers in hardware is a common pattern, so
> > add a clock doing this. Currently no rate propagation is supported.
> 
> Also, could I convince you to move struct clk_fixed_factor into
> clk-provider.h and provide a DEFINE_CLK_FIXED_FACTOR macro to align with
> the other basic clocks?

Given that this is the current way to statically initialize clocks, yes
I'll integrate it, but not without grumbling about these macros in
general...

> 
> ---
>  drivers/clk/clk-fixed-factor.c |   15 +++++++++------
>  include/linux/clk-private.h    |   28 ++++++++++++++++++++++++++++
>  include/linux/clk-provider.h   |   19 +++++++++++++++++++
>  3 files changed, 56 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
> index d99b842..8ca427a 100644
> --- a/drivers/clk/clk-fixed-factor.c
> +++ b/drivers/clk/clk-fixed-factor.c
> @@ -12,12 +12,15 @@
>  #include <linux/slab.h>
>  #include <linux/err.h>
>  
> -struct clk_fixed_factor {
> -	struct clk_hw	hw;
> -	unsigned int	mult;
> -	unsigned int	div;
> -	char		*parent[1];
> -};
> +/*
> + * DOC: basic fixed multiplier and divider clock that cannot gate
> + *
> + * Traits of this clock:
> + * prepare - clk_prepare only ensures that parents are prepared
> + * enable - clk_enable only ensures that parents are enabled
> + * rate - rate is fixed.  clk->rate = parent->rate / div * mult
> + * parent - fixed parent.  No clk_set_parent support
> + */
>  
>  #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
>  
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> index 5e4312b..9501eab 100644
> --- a/include/linux/clk-private.h
> +++ b/include/linux/clk-private.h
> @@ -170,6 +170,34 @@ extern struct clk_ops clk_mux_ops;
>  		.flags = _flags,				\
>  	};
>  
> +extern struct clk_ops clk_fixed_factor_ops;
> +
> +#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name,		\
> +				_parent_ptr, _flags,		\
> +				_mult, _div)			\
> +	static struct clk _name;				\
> +	static struct clk *_name##_parents[] = {		\
> +		_parent_ptr,					\
> +	};							\
> +	static struct clk_fixed_factor _name##_hw = {		\
> +		.hw = {						\
> +			.clk = &_name,				\
> +		},						\
> +		.mult = _mult,					\
> +		.div = _div,					\
> +		.parent[0] = _parent_name,			\
> +	};							\
> +	static struct clk _name = {				\
> +		.name = #_name,					\
> +		.ops = &clk_fixed_factor_ops,			\
> +		.hw = &_name##_hw.hw,				\
> +		.parent_names = _name##_hw.parent,		\
> +		.num_parents =					\
> +			ARRAY_SIZE(_name##_hw.parent),		\
> +		.parents = _name##_parents,			\
> +		.flags = _flags,				\
> +	};
> +
>  /**
>   * __clk_init - initialize the data structures in a struct clk
>   * @dev:	device initializing this clk, placeholder for now
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 21ca2f8..b58f846 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -257,6 +257,25 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
>  		void __iomem *reg, u8 shift, u8 width,
>  		u8 clk_mux_flags, spinlock_t *lock);
>  
> +/**
> + * struct clk_fixed_factor - fixed multiplier and divider clock
> + *
> + * @hw:         handle between common and hardware-specific interfaces
> + * @mult:	multiplier
> + * @div:        divider
> + *
> + * Clock with a fixed multiplier and divider. The output frequency is the
> + * parent clock rate divided by div and multiplied by mult.
> + * Implements .recalc_rate, .set_rate and .round_rate
> + */
> +
> +struct clk_fixed_factor {
> +        struct clk_hw   hw;
> +        unsigned int    mult;
> +        unsigned int    div;
> +        char            *parent[1];
> +};
> +
>  struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
>  		const char *parent_name, unsigned long flags,
>  		unsigned int mult, unsigned int div);
> -- 
> 1.7.9.1
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From grant.likely at secretlab.ca  Fri Mar 23 04:49:18 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 23 Mar 2012 08:49:18 +0000
Subject: [GIT PULL] gpio/omap: more fixes for v3.4
In-Reply-To: <871uok5pk0.fsf@ti.com>
References: <871uok5pk0.fsf@ti.com>
Message-ID: <CACxGe6vvDLVyirAxFw6JxaZYNzWSr1Z6cVgfnJS4+Sna1EZ+1g@mail.gmail.com>

On Thu, Mar 22, 2012 at 8:49 PM, Kevin Hilman <khilman at ti.com> wrote:
> Hi Grant,
>
> Please pull these OMAP GPIO fixes for v3.4. ?These fix some rather
> serious regressions introduced by the cleanup and runtime PM conversion
> series which is also queued for v3.4. ?This branch is based on your
> gpio/next branch.
>
> This version is functionally the same as the version you previously
> merged (and I asked you to back it out), but this version has some
> better changlogs, and I added reviewed-by and s-o-b from me as well.
>
> Thanks,
>
> Kevin

Merged, thanks.

g.

>
>
>
> The following changes since commit 81b279d80a63628e580c71a31d30a8c3b3047ad4:
>
> ?gpio/davinci: fix enabling unbanked GPIO IRQs (2012-03-12 11:53:33 -0600)
>
> are available in the git repository at:
>
> ?git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/fixes/gpio-2
>
> for you to fetch changes up to 7fcca715de3438b8fc3c8a144702f3a95c8ff63c:
>
> ?gpio/omap: fix redundant decoding of gpio offset (2012-03-21 10:21:24 +0530)
>
> ----------------------------------------------------------------
> Tarun Kanti DebBarma (7):
> ? ? ?gpio/omap: fix wakeup_en register update in _set_gpio_wakeup()
> ? ? ?gpio/omap: fix trigger type to unsigned
> ? ? ?gpio/omap: fix _set_gpio_irqenable implementation
> ? ? ?gpio/omap: fix missing dataout context save in _set_gpio_dataout_reg
> ? ? ?gpio/omap: fix incorrect context restore logic in omap_gpio_runtime_*
> ? ? ?gpio/omap: fix incorrect update to context.irqenable1
> ? ? ?gpio/omap: fix redundant decoding of gpio offset
>
> ?drivers/gpio/gpio-omap.c | ? 47 ++++++++++++++++++++++++----------------------
> ?1 file changed, 25 insertions(+), 22 deletions(-)



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From b-cousson at ti.com  Fri Mar 23 05:10:35 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Fri, 23 Mar 2012 10:10:35 +0100
Subject: [RFC][PATCH 0/5] Convert GPMC to driver
In-Reply-To: <1332484567-21710-1-git-send-email-afzal@ti.com>
References: <1332484567-21710-1-git-send-email-afzal@ti.com>
Message-ID: <4F6C3E0B.9090004@ti.com>

Hi Mohammed,

On 3/23/2012 7:36 AM, Afzal Mohammed wrote:
> Hi,
>
> Convert GPCM code to be a driver. Existing GPMC
> NAND platform handling has been modified to work
> with the new GPMC driver (patches 2&  3). Patch 5
> is to test the driver in OMAP3EVM.

Hehe, cool, thanks for that series,
Benoit

>
> Once all the users has been converted to use this
> driver, would be converted to MFD type.
>
> TODO:
> 1. Let OMAP NAND driver deal with GPMC NAND block
> 2. Remove struct gpmc * stored as static
> 3. Convert all peripherals to use GPMC driver
> 4. Devise method to handle OneNAND cleanly
> 5. Handle acquiring CS# cases
> 6. Convert to MFD driver
>
> Regards
> Afzal
>
> Afzal Mohammed (5):
>    ARM: OMAP2+: gpmc: driver conversion
>    ARM: OMAP2+: nand: create platform data structure
>    ARM: OMAP2+: gpmc-nand: populate gpmc configs
>    mtd: nand: omap2: obtain memory from resource
>    OMAP3EVM: Test gpmc-nand
>
>   arch/arm/mach-omap2/board-devkit8000.c     |    6 +-
>   arch/arm/mach-omap2/board-flash.c          |   63 +-
>   arch/arm/mach-omap2/board-flash.h          |   13 +-
>   arch/arm/mach-omap2/board-ldp.c            |    4 +-
>   arch/arm/mach-omap2/board-omap3beagle.c    |    6 +-
>   arch/arm/mach-omap2/board-omap3evm.c       |   82 +++
>   arch/arm/mach-omap2/board-omap3touchbook.c |    6 +-
>   arch/arm/mach-omap2/board-overo.c          |    5 +-
>   arch/arm/mach-omap2/board-zoom.c           |    5 +-
>   arch/arm/mach-omap2/common-board-devices.c |   46 --
>   arch/arm/mach-omap2/common-board-devices.h |    1 -
>   arch/arm/mach-omap2/gpmc-nand.c            |   88 +--
>   arch/arm/mach-omap2/gpmc.c                 | 1083 ++++++++++++++++------------
>   arch/arm/plat-omap/include/plat/gpmc.h     |   34 +-
>   arch/arm/plat-omap/include/plat/nand.h     |    9 +-
>   drivers/mtd/nand/omap2.c                   |   19 +-
>   16 files changed, 869 insertions(+), 601 deletions(-)
>



From daniel.lezcano at linaro.org  Fri Mar 23 05:26:27 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 23 Mar 2012 10:26:27 +0100
Subject: [RFC][PATCH 2/9] ARM: OMAP3: cpuidle - remove next_valid_state
 function
In-Reply-To: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332494794-7810-2-git-send-email-daniel.lezcano@linaro.org>

As we will be able to remove C-states from userspace with the sysfs
API, this function is no longer needed. We remove it and that simplifies
the code for more consolidation.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle34xx.c |   85 +------------------------------------
 1 files changed, 2 insertions(+), 83 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index d67431a..65b4e7aa 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -164,84 +164,6 @@ return_sleep_time:
 }
 
 /**
- * next_valid_state - Find next valid C-state
- * @dev: cpuidle device
- * @drv: cpuidle driver
- * @index: Index of currently selected c-state
- *
- * If the state corresponding to index is valid, index is returned back
- * to the caller. Else, this function searches for a lower c-state which is
- * still valid (as defined in omap3_power_states[]) and returns its index.
- *
- * A state is valid if the 'valid' field is enabled and
- * if it satisfies the enable_off_mode condition.
- */
-static int next_valid_state(struct cpuidle_device *dev,
-			struct cpuidle_driver *drv,
-				int index)
-{
-	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
-	struct cpuidle_state *curr = &drv->states[index];
-	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
-	u32 mpu_deepest_state = PWRDM_POWER_RET;
-	u32 core_deepest_state = PWRDM_POWER_RET;
-	int next_index = -1;
-
-	if (enable_off_mode) {
-		mpu_deepest_state = PWRDM_POWER_OFF;
-		/*
-		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
-		 * CORE OFF mode is not supported in a stable form, restrict
-		 * instead the CORE state to RET.
-		 */
-		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
-			core_deepest_state = PWRDM_POWER_OFF;
-	}
-
-	/* Check if current state is valid */
-	if ((cx->valid) &&
-	    (cx->mpu_state >= mpu_deepest_state) &&
-	    (cx->core_state >= core_deepest_state)) {
-		return index;
-	} else {
-		int idx = OMAP3_NUM_STATES - 1;
-
-		/* Reach the current state starting at highest C-state */
-		for (; idx >= 0; idx--) {
-			if (&drv->states[idx] == curr) {
-				next_index = idx;
-				break;
-			}
-		}
-
-		/* Should never hit this condition */
-		WARN_ON(next_index == -1);
-
-		/*
-		 * Drop to next valid state.
-		 * Start search from the next (lower) state.
-		 */
-		idx--;
-		for (; idx >= 0; idx--) {
-			cx = cpuidle_get_statedata(&dev->states_usage[idx]);
-			if ((cx->valid) &&
-			    (cx->mpu_state >= mpu_deepest_state) &&
-			    (cx->core_state >= core_deepest_state)) {
-				next_index = idx;
-				break;
-			}
-		}
-		/*
-		 * C1 is always valid.
-		 * So, no need to check for 'next_index == -1' outside
-		 * this loop.
-		 */
-	}
-
-	return next_index;
-}
-
-/**
  * omap3_enter_idle_bm - Checks for any bus activity
  * @dev: cpuidle device
  * @drv: cpuidle driver
@@ -254,7 +176,6 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 				struct cpuidle_driver *drv,
 			       int index)
 {
-	int new_state_idx;
 	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
 	struct omap3_idle_statedata *cx;
 	int ret;
@@ -265,7 +186,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 	 */
 	cam_state = pwrdm_read_pwrst(cam_pd);
 	if (cam_state == PWRDM_POWER_ON) {
-		new_state_idx = drv->safe_state_index;
+		index = drv->safe_state_index;
 		goto select_state;
 	}
 
@@ -292,10 +213,8 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 	if (per_next_state != per_saved_state)
 		pwrdm_set_next_pwrst(per_pd, per_next_state);
 
-	new_state_idx = next_valid_state(dev, drv, index);
-
 select_state:
-	ret = omap3_enter_idle(dev, drv, new_state_idx);
+	ret = omap3_enter_idle(dev, drv, index);
 
 	/* Restore original PER state if it was modified */
 	if (per_next_state != per_saved_state)
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Fri Mar 23 05:26:26 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 23 Mar 2012 10:26:26 +0100
Subject: [RFC][PATCH 1/9] ARM: OMAP3: cpuidle - remove rx51 cpuidle parameters
 table
Message-ID: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>

As suggested, this table is an optimized version for rx51 and we
remove it in order to consolidate the cpuidle code between omap3
and omap4, we remove this specific data definition which is used
to override the default omap3 latencies but at the cost of extra
code and complexity.

In order to not lose the values which probably took time to be
measured, the table is converted into a comment with an array
description.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/board-rx51.c  |   38 +++++++++++++++++-------------------
 arch/arm/mach-omap2/cpuidle34xx.c |   17 ----------------
 arch/arm/mach-omap2/pm.h          |    9 --------
 3 files changed, 18 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 27f01f0..2da92a6 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -59,25 +59,24 @@ static struct platform_device leds_gpio = {
 };
 
 /*
- * cpuidle C-states definition override from the default values.
- * The 'exit_latency' field is the sum of sleep and wake-up latencies.
- */
-static struct cpuidle_params rx51_cpuidle_params[] = {
-	/* C1 */
-	{110 + 162, 5 , 1},
-	/* C2 */
-	{106 + 180, 309, 1},
-	/* C3 */
-	{107 + 410, 46057, 0},
-	/* C4 */
-	{121 + 3374, 46057, 0},
-	/* C5 */
-	{855 + 1146, 46057, 1},
-	/* C6 */
-	{7580 + 4134, 484329, 0},
-	/* C7 */
-	{7505 + 15274, 484329, 1},
-};
+ * cpuidle C-states definition for rx51.
+ *
+ * The 'exit_latency' field is the sum of sleep
+ * and wake-up latencies.
+
+    ---------------------------------------------
+   | state |  exit_latency  |  target_residency  |
+    ---------------------------------------------
+   |  C1   |    110 + 162   |            5       |
+   |  C2   |    106 + 180   |          309       |
+   |  C3   |    107 + 410   |        46057       |
+   |  C4   |    121 + 3374  |        46057       |
+   |  C5   |    855 + 1146  |        46057       |
+   |  C6   |   7580 + 4134  |       484329       |
+   |  C7   |   7505 + 15274 |       484329       |
+    ---------------------------------------------
+
+*/
 
 extern void __init rx51_peripherals_init(void);
 
@@ -98,7 +97,6 @@ static void __init rx51_init(void)
 	struct omap_sdrc_params *sdrc_params;
 
 	omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-	omap3_pm_init_cpuidle(rx51_cpuidle_params);
 	omap_serial_init();
 
 	sdrc_params = nokia_get_sdram_timings();
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 464cffd..d67431a 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -306,23 +306,6 @@ select_state:
 
 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 
-void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
-{
-	int i;
-
-	if (!cpuidle_board_params)
-		return;
-
-	for (i = 0; i < OMAP3_NUM_STATES; i++) {
-		cpuidle_params_table[i].valid =	cpuidle_board_params[i].valid;
-		cpuidle_params_table[i].exit_latency =
-			cpuidle_board_params[i].exit_latency;
-		cpuidle_params_table[i].target_residency =
-			cpuidle_board_params[i].target_residency;
-	}
-	return;
-}
-
 struct cpuidle_driver omap3_idle_driver = {
 	.name = 	"omap3_idle",
 	.owner = 	THIS_MODULE,
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index a051431..af73a86 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -51,15 +51,6 @@ struct cpuidle_params {
 	u8 valid;		/* validates the C-state */
 };
 
-#if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
-extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
-#else
-static
-inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
-{
-}
-#endif
-
 extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
 extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
 
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Fri Mar 23 05:26:28 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 23 Mar 2012 10:26:28 +0100
Subject: [RFC][PATCH 3/9] ARM: OMAP3: cpuidle - set enable_off_mode as static
In-Reply-To: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332494794-7810-3-git-send-email-daniel.lezcano@linaro.org>

This variable is only used in the pm-debug.c file.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/pm-debug.c |    2 +-
 arch/arm/mach-omap2/pm.h       |   30 ++++++++++++------------------
 2 files changed, 13 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 814bcd9..86aa398 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -38,7 +38,7 @@
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
 
-u32 enable_off_mode;
+static u32 enable_off_mode;
 
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index af73a86..f5c3072 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -25,6 +25,18 @@ extern int omap4_idle_init(void);
 extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
 extern int (*omap_pm_suspend)(void);
 
+/*
+ * cpuidle mach specific parameters
+ *
+ * The board code can override the default C-states definition using
+ * omap3_pm_init_cpuidle
+ */
+struct cpuidle_params {
+       u32 exit_latency;       /* exit_latency = sleep + wake-up latencies */
+       u32 target_residency;
+       u8 valid;               /* validates the C-state */
+};
+
 #if defined(CONFIG_PM_OPP)
 extern int omap3_opp_init(void);
 extern int omap4_opp_init(void);
@@ -39,27 +51,9 @@ static inline int omap4_opp_init(void)
 }
 #endif
 
-/*
- * cpuidle mach specific parameters
- *
- * The board code can override the default C-states definition using
- * omap3_pm_init_cpuidle
- */
-struct cpuidle_params {
-	u32 exit_latency;	/* exit_latency = sleep + wake-up latencies */
-	u32 target_residency;
-	u8 valid;		/* validates the C-state */
-};
-
 extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
 extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
 
-#ifdef CONFIG_PM_DEBUG
-extern u32 enable_off_mode;
-#else
-#define enable_off_mode 0
-#endif
-
 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
 extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
 #else
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Fri Mar 23 05:26:29 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 23 Mar 2012 10:26:29 +0100
Subject: [RFC][PATCH 4/9] ARM: OMAP3: define cpuidle statically
In-Reply-To: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332494794-7810-4-git-send-email-daniel.lezcano@linaro.org>

Use the new cpuidle API and define in the driver the states.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle34xx.c |   85 +++++++++++++++++++++++++-----------
 1 files changed, 59 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 65b4e7aa..62e3cfd 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -228,23 +228,67 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 struct cpuidle_driver omap3_idle_driver = {
 	.name = 	"omap3_idle",
 	.owner = 	THIS_MODULE,
+	.states = {
+		{
+			.enter		  = omap3_enter_idle,
+			.exit_latency	  = 2 + 2,
+			.target_residency = 5,
+			.flags		  = CPUIDLE_FLAG_TIME_VALID,
+			.name		  = "C1",
+			.desc		  = "MPU ON + CORE ON",
+		},
+		{
+			.enter		  = omap3_enter_idle_bm,
+			.exit_latency	  = 10 + 10,
+			.target_residency = 30,
+			.flags		  = CPUIDLE_FLAG_TIME_VALID,
+			.name		  = "C2",
+			.desc		  = "MPU ON + CORE ON",
+		},
+		{
+			.enter		  = omap3_enter_idle_bm,
+			.exit_latency	  = 50 + 50,
+			.target_residency = 300,
+			.flags		  = CPUIDLE_FLAG_TIME_VALID,
+			.name		  = "C3",
+			.desc		  = "MPU RET + CORE ON",
+		},
+		{
+			.enter		  = omap3_enter_idle_bm,
+			.exit_latency	  = 1500 + 1800,
+			.target_residency = 4000,
+			.flags		  = CPUIDLE_FLAG_TIME_VALID,
+			.name		  = "C4",
+			.desc		  = "MPU OFF + CORE ON",
+		},
+		{
+			.enter		  = omap3_enter_idle_bm,
+			.exit_latency	  = 2500 + 7500,
+			.target_residency = 12000,
+			.flags		  = CPUIDLE_FLAG_TIME_VALID,
+			.name		  = "C5",
+			.desc		  = "MPU RET + CORE RET",
+		},
+		{
+			.enter		  = omap3_enter_idle_bm,
+			.exit_latency	  = 3000 + 8500,
+			.target_residency = 15000,
+			.flags		  = CPUIDLE_FLAG_TIME_VALID,
+			.name		  = "C6",
+			.desc		  = "MPU OFF + CORE RET",
+		},
+		{
+			.enter		  = omap3_enter_idle_bm,
+			.exit_latency	  = 10000 + 30000,
+			.target_residency = 30000,
+			.flags		  = CPUIDLE_FLAG_TIME_VALID,
+			.name		  = "C7",
+			.desc		  = "MPU OFF + CORE OFF",
+		},
+	},
+	.state_count = OMAP3_NUM_STATES,
 };
 
-/* Helper to fill the C-state common data*/
-static inline void _fill_cstate(struct cpuidle_driver *drv,
-					int idx, const char *descr)
-{
-	struct cpuidle_state *state = &drv->states[idx];
-
-	state->exit_latency	= cpuidle_params_table[idx].exit_latency;
-	state->target_residency	= cpuidle_params_table[idx].target_residency;
-	state->flags		= CPUIDLE_FLAG_TIME_VALID;
-	state->enter		= omap3_enter_idle_bm;
-	sprintf(state->name, "C%d", idx + 1);
-	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
-
-}
-
 /* Helper to register the driver_data */
 static inline struct omap3_idle_statedata *_fill_cstate_usage(
 					struct cpuidle_device *dev,
@@ -277,50 +321,40 @@ int __init omap3_idle_init(void)
 	cam_pd = pwrdm_lookup("cam_pwrdm");
 
 
-	drv->safe_state_index = -1;
 	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 
 	/* C1 . MPU WFI + Core active */
-	_fill_cstate(drv, 0, "MPU ON + CORE ON");
-	(&drv->states[0])->enter = omap3_enter_idle;
-	drv->safe_state_index = 0;
 	cx = _fill_cstate_usage(dev, 0);
 	cx->valid = 1;	/* C1 is always valid */
 	cx->mpu_state = PWRDM_POWER_ON;
 	cx->core_state = PWRDM_POWER_ON;
 
 	/* C2 . MPU WFI + Core inactive */
-	_fill_cstate(drv, 1, "MPU ON + CORE ON");
 	cx = _fill_cstate_usage(dev, 1);
 	cx->mpu_state = PWRDM_POWER_ON;
 	cx->core_state = PWRDM_POWER_ON;
 
 	/* C3 . MPU CSWR + Core inactive */
-	_fill_cstate(drv, 2, "MPU RET + CORE ON");
 	cx = _fill_cstate_usage(dev, 2);
 	cx->mpu_state = PWRDM_POWER_RET;
 	cx->core_state = PWRDM_POWER_ON;
 
 	/* C4 . MPU OFF + Core inactive */
-	_fill_cstate(drv, 3, "MPU OFF + CORE ON");
 	cx = _fill_cstate_usage(dev, 3);
 	cx->mpu_state = PWRDM_POWER_OFF;
 	cx->core_state = PWRDM_POWER_ON;
 
 	/* C5 . MPU RET + Core RET */
-	_fill_cstate(drv, 4, "MPU RET + CORE RET");
 	cx = _fill_cstate_usage(dev, 4);
 	cx->mpu_state = PWRDM_POWER_RET;
 	cx->core_state = PWRDM_POWER_RET;
 
 	/* C6 . MPU OFF + Core RET */
-	_fill_cstate(drv, 5, "MPU OFF + CORE RET");
 	cx = _fill_cstate_usage(dev, 5);
 	cx->mpu_state = PWRDM_POWER_OFF;
 	cx->core_state = PWRDM_POWER_RET;
 
 	/* C7 . MPU OFF + Core OFF */
-	_fill_cstate(drv, 6, "MPU OFF + CORE OFF");
 	cx = _fill_cstate_usage(dev, 6);
 	/*
 	 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
@@ -338,7 +372,6 @@ int __init omap3_idle_init(void)
 	drv->state_count = OMAP3_NUM_STATES;
 	cpuidle_register_driver(&omap3_idle_driver);
 
-	dev->state_count = OMAP3_NUM_STATES;
 	if (cpuidle_register_device(dev)) {
 		printk(KERN_ERR "%s: CPUidle register device failed\n",
 		       __func__);
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Fri Mar 23 05:26:30 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 23 Mar 2012 10:26:30 +0100
Subject: [RFC][PATCH 5/9] ARM: OMAP3: cpuidle - remove the 'valid' field
In-Reply-To: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332494794-7810-5-git-send-email-daniel.lezcano@linaro.org>

With the previous changes all the states are valid, except
the last state which can be handled by decreasing the number
of states.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle34xx.c |    6 +-----
 1 files changed, 1 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 62e3cfd..39aa1b8 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -67,7 +67,6 @@ static struct cpuidle_params cpuidle_params_table[] = {
 struct omap3_idle_statedata {
 	u32 mpu_state;
 	u32 core_state;
-	u8 valid;
 };
 struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
 
@@ -297,7 +296,6 @@ static inline struct omap3_idle_statedata *_fill_cstate_usage(
 	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
 	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
 
-	cx->valid		= cpuidle_params_table[idx].valid;
 	cpuidle_set_statedata(state_usage, cx);
 
 	return cx;
@@ -325,7 +323,6 @@ int __init omap3_idle_init(void)
 
 	/* C1 . MPU WFI + Core active */
 	cx = _fill_cstate_usage(dev, 0);
-	cx->valid = 1;	/* C1 is always valid */
 	cx->mpu_state = PWRDM_POWER_ON;
 	cx->core_state = PWRDM_POWER_ON;
 
@@ -362,14 +359,13 @@ int __init omap3_idle_init(void)
 	 * We disable C7 state as a result.
 	 */
 	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
-		cx->valid = 0;
+		drv->state_count = OMAP3_NUM_STATES - 1;
 		pr_warn("%s: core off state C7 disabled due to i583\n",
 			__func__);
 	}
 	cx->mpu_state = PWRDM_POWER_OFF;
 	cx->core_state = PWRDM_POWER_OFF;
 
-	drv->state_count = OMAP3_NUM_STATES;
 	cpuidle_register_driver(&omap3_idle_driver);
 
 	if (cpuidle_register_device(dev)) {
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Fri Mar 23 05:26:31 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 23 Mar 2012 10:26:31 +0100
Subject: [RFC][PATCH 6/9] ARM: OMAP3: cpuidle - remove cpuidle_params_table
In-Reply-To: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332494794-7810-6-git-send-email-daniel.lezcano@linaro.org>

We do not longer need the ''cpuidle_params_table' array as
we defined the states in the driver and we checked they are
all valid.

We also remove the structure definition as it is no longer used.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle34xx.c |   28 +++-------------------------
 arch/arm/mach-omap2/pm.h          |   12 ------------
 2 files changed, 3 insertions(+), 37 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 39aa1b8..877a7e1 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -38,36 +38,14 @@
 
 #ifdef CONFIG_CPU_IDLE
 
-/*
- * The latencies/thresholds for various C states have
- * to be configured from the respective board files.
- * These are some default values (which might not provide
- * the best power savings) used on boards which do not
- * pass these details from the board file.
- */
-static struct cpuidle_params cpuidle_params_table[] = {
-	/* C1 */
-	{2 + 2, 5, 1},
-	/* C2 */
-	{10 + 10, 30, 1},
-	/* C3 */
-	{50 + 50, 300, 1},
-	/* C4 */
-	{1500 + 1800, 4000, 1},
-	/* C5 */
-	{2500 + 7500, 12000, 1},
-	/* C6 */
-	{3000 + 8500, 15000, 1},
-	/* C7 */
-	{10000 + 30000, 300000, 1},
-};
-#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
-
 /* Mach specific information to be recorded in the C-state driver_data */
 struct omap3_idle_statedata {
 	u32 mpu_state;
 	u32 core_state;
 };
+
+#define OMAP3_NUM_STATES 7
+
 struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
 
 struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index f5c3072..a41c8dd 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -25,18 +25,6 @@ extern int omap4_idle_init(void);
 extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
 extern int (*omap_pm_suspend)(void);
 
-/*
- * cpuidle mach specific parameters
- *
- * The board code can override the default C-states definition using
- * omap3_pm_init_cpuidle
- */
-struct cpuidle_params {
-       u32 exit_latency;       /* exit_latency = sleep + wake-up latencies */
-       u32 target_residency;
-       u8 valid;               /* validates the C-state */
-};
-
 #if defined(CONFIG_PM_OPP)
 extern int omap3_opp_init(void);
 extern int omap4_opp_init(void);
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Fri Mar 23 05:26:32 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 23 Mar 2012 10:26:32 +0100
Subject: [RFC][PATCH 7/9] ARM: OMAP3: define statically the omap3_idle_data
In-Reply-To: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332494794-7810-7-git-send-email-daniel.lezcano@linaro.org>

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle34xx.c |   31 ++++++++++++++++++++++++++++++-
 1 files changed, 30 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 877a7e1..34e1e34 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -46,7 +46,36 @@ struct omap3_idle_statedata {
 
 #define OMAP3_NUM_STATES 7
 
-struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
+struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES] = {
+	{
+		.mpu_state = PWRDM_POWER_ON,
+		.core_state = PWRDM_POWER_ON,
+	},
+	{
+		.mpu_state = PWRDM_POWER_ON,
+		.core_state = PWRDM_POWER_ON,
+	},
+	{
+		.mpu_state = PWRDM_POWER_RET,
+		.core_state = PWRDM_POWER_ON,
+	},
+	{
+		.mpu_state = PWRDM_POWER_OFF,
+		.core_state = PWRDM_POWER_ON,
+	},
+	{
+		.mpu_state = PWRDM_POWER_RET,
+		.core_state = PWRDM_POWER_RET,
+	},
+	{
+		.mpu_state = PWRDM_POWER_OFF,
+		.core_state = PWRDM_POWER_RET,
+	},
+	{
+		.mpu_state = PWRDM_POWER_OFF,
+		.core_state = PWRDM_POWER_OFF,
+	},
+};
 
 struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
 
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Fri Mar 23 05:26:33 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 23 Mar 2012 10:26:33 +0100
Subject: [RFC][PATCH 8/9] ARM: OMAP3: cpuidle - use omap3_idle_data directly
In-Reply-To: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332494794-7810-8-git-send-email-daniel.lezcano@linaro.org>

We are storing the 'omap3_idle_data' in the private data field
if the cpuidle device. As we are using this variable only in this file,
that does not really make sense. Let's use the global variable directly
instead dereferencing pointers in an idle critical loop.

As the table is initialized statically, let's remove the initialization at
startup too.

Also, that simplfies the code.

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/cpuidle34xx.c |   60 ++++---------------------------------
 1 files changed, 6 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 34e1e34..726f0bf 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -106,8 +106,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 				struct cpuidle_driver *drv,
 				int index)
 {
-	struct omap3_idle_statedata *cx =
-			cpuidle_get_statedata(&dev->states_usage[index]);
+	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
 	struct timespec ts_preidle, ts_postidle, ts_idle;
 	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
 	int idle_time;
@@ -208,7 +207,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 	 * Prevent PER off if CORE is not in retention or off as this
 	 * would disable PER wakeups completely.
 	 */
-	cx = cpuidle_get_statedata(&dev->states_usage[index]);
+	cx = &omap3_idle_data[index];
 	core_next_state = cx->core_state;
 	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
 	if ((per_next_state == PWRDM_POWER_OFF) &&
@@ -295,19 +294,6 @@ struct cpuidle_driver omap3_idle_driver = {
 	.state_count = OMAP3_NUM_STATES,
 };
 
-/* Helper to register the driver_data */
-static inline struct omap3_idle_statedata *_fill_cstate_usage(
-					struct cpuidle_device *dev,
-					int idx)
-{
-	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
-	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
-
-	cpuidle_set_statedata(state_usage, cx);
-
-	return cx;
-}
-
 /**
  * omap3_idle_init - Init routine for OMAP3 idle
  *
@@ -318,48 +304,12 @@ int __init omap3_idle_init(void)
 {
 	struct cpuidle_device *dev;
 	struct cpuidle_driver *drv = &omap3_idle_driver;
-	struct omap3_idle_statedata *cx;
 
 	mpu_pd = pwrdm_lookup("mpu_pwrdm");
 	core_pd = pwrdm_lookup("core_pwrdm");
 	per_pd = pwrdm_lookup("per_pwrdm");
 	cam_pd = pwrdm_lookup("cam_pwrdm");
 
-
-	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
-
-	/* C1 . MPU WFI + Core active */
-	cx = _fill_cstate_usage(dev, 0);
-	cx->mpu_state = PWRDM_POWER_ON;
-	cx->core_state = PWRDM_POWER_ON;
-
-	/* C2 . MPU WFI + Core inactive */
-	cx = _fill_cstate_usage(dev, 1);
-	cx->mpu_state = PWRDM_POWER_ON;
-	cx->core_state = PWRDM_POWER_ON;
-
-	/* C3 . MPU CSWR + Core inactive */
-	cx = _fill_cstate_usage(dev, 2);
-	cx->mpu_state = PWRDM_POWER_RET;
-	cx->core_state = PWRDM_POWER_ON;
-
-	/* C4 . MPU OFF + Core inactive */
-	cx = _fill_cstate_usage(dev, 3);
-	cx->mpu_state = PWRDM_POWER_OFF;
-	cx->core_state = PWRDM_POWER_ON;
-
-	/* C5 . MPU RET + Core RET */
-	cx = _fill_cstate_usage(dev, 4);
-	cx->mpu_state = PWRDM_POWER_RET;
-	cx->core_state = PWRDM_POWER_RET;
-
-	/* C6 . MPU OFF + Core RET */
-	cx = _fill_cstate_usage(dev, 5);
-	cx->mpu_state = PWRDM_POWER_OFF;
-	cx->core_state = PWRDM_POWER_RET;
-
-	/* C7 . MPU OFF + Core OFF */
-	cx = _fill_cstate_usage(dev, 6);
 	/*
 	 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
 	 * enable OFF mode in a stable form for previous revisions.
@@ -370,11 +320,13 @@ int __init omap3_idle_init(void)
 		pr_warn("%s: core off state C7 disabled due to i583\n",
 			__func__);
 	}
-	cx->mpu_state = PWRDM_POWER_OFF;
-	cx->core_state = PWRDM_POWER_OFF;
 
 	cpuidle_register_driver(&omap3_idle_driver);
 
+	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
+	dev->cpu = 0;
+	dev->state_count = drv->state_count;
+
 	if (cpuidle_register_device(dev)) {
 		printk(KERN_ERR "%s: CPUidle register device failed\n",
 		       __func__);
-- 
1.7.5.4



From daniel.lezcano at linaro.org  Fri Mar 23 05:26:34 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 23 Mar 2012 10:26:34 +0100
Subject: [RFC][PATCH 9/9] ARM: OMAP3/4: consolidate cpuidle Makefile
In-Reply-To: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <1332494794-7810-9-git-send-email-daniel.lezcano@linaro.org>

Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
---
 arch/arm/mach-omap2/Makefile      |   11 +++++++----
 arch/arm/mach-omap2/cpuidle34xx.c |    8 --------
 arch/arm/mach-omap2/cpuidle44xx.c |    8 --------
 arch/arm/mach-omap2/pm.h          |   17 +++++++++++++++--
 4 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index bd76394..93819c4 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -63,10 +63,8 @@ endif
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o
-obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o \
-					   cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o omap-mpuss-lowpower.o \
-					   cpuidle44xx.o
+obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o
+obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o omap-mpuss-lowpower.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)	+= smartreflex-class3.o
@@ -80,6 +78,11 @@ endif
 
 endif
 
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
+endif
+
 # PRCM
 obj-y					+= prm_common.o
 obj-$(CONFIG_ARCH_OMAP2)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 726f0bf..579424c 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -36,8 +36,6 @@
 #include "control.h"
 #include "common.h"
 
-#ifdef CONFIG_CPU_IDLE
-
 /* Mach specific information to be recorded in the C-state driver_data */
 struct omap3_idle_statedata {
 	u32 mpu_state;
@@ -335,9 +333,3 @@ int __init omap3_idle_init(void)
 
 	return 0;
 }
-#else
-int __init omap3_idle_init(void)
-{
-	return 0;
-}
-#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index f6a6194..d251187 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -22,8 +22,6 @@
 #include "pm.h"
 #include "prm.h"
 
-#ifdef CONFIG_CPU_IDLE
-
 /* Machine specific information */
 struct omap4_idle_statedata {
 	u32 cpu_state;
@@ -219,9 +217,3 @@ int __init omap4_idle_init(void)
 
 	return 0;
 }
-#else
-int __init omap4_idle_init(void)
-{
-	return 0;
-}
-#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index a41c8dd..d9a97e8 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -15,13 +15,26 @@
 
 #include "powerdomain.h"
 
+#ifdef CONFIG_CPU_IDLE
+extern int omap3_idle_init(void);
+extern int omap4_idle_init(void);
+#else
+static inline int omap3_idle_init(void)
+{
+	return 0;
+}
+
+static inline int omap4_idle_init(void)
+{
+	return 0;
+}
+#endif
+
 extern void *omap3_secure_ram_storage;
 extern void omap3_pm_off_mode_enable(int);
 extern void omap_sram_idle(void);
 extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
-extern int omap3_idle_init(void);
-extern int omap4_idle_init(void);
 extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
 extern int (*omap_pm_suspend)(void);
 
-- 
1.7.5.4



From b-cousson at ti.com  Fri Mar 23 05:37:30 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Fri, 23 Mar 2012 10:37:30 +0100
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <1332484600-21947-1-git-send-email-afzal@ti.com>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
Message-ID: <4F6C445A.3040103@ti.com>

On 3/23/2012 7:36 AM, Afzal Mohammed wrote:
> Convert GPMC code to driver. Boards using GPMC
> should provide driver with type of configuration,
> timing, GPMC address space details (if already
> configured, driver will retrieve, as is existing).
> Platform devices would the be created for each
> connected peripheral (peripheral details also to
> be passed by board so that it reaches respective
> driver). And GPMC driver would populate memory
> resource details for the driver of connected
> peripheral.
>
> A peripheral connected to GPMC can have multiple
> address spaces using different chip select. Hence
> GPMC driver has been provided capability to
> distinguish this scenario, i.e. create platform
> devices only once for each connected peripheral,
> and not for each configured chip select. The
> peripheral that made it necessary was tusb6010.
>
> Final destination aimed for this driver is MFD.

Why? Are you sure this is appropriate? This is not really a 
multifunction device but rather a bus device that can manage multiple 
kind of devices.

> But before that all existing GPMC users has to be
> converted to work with this driver. This would
> likely result in removal of gpmc_create_child
> and probably use MFD APIs instead.
>
> NAND driver for GPMC is tightly coupled with GPMC
> driver (GPMC has few blocks exclusively for NAND),
> while that is not the case for most of the other
> users (they need GPMCs help only for initial
> configuration). Currently NAND driver manage using
> exported GPMC symbols. This is being planned to
> remove later&  would need informing NAND driver
> about GPMC NAND registers. This would help to have
> export symbol free GPMC driver, and probably
> "mv omap2.c gpmc-nand.c" for OMAP NAND driver.
> Thanks to Vaibhav Hiremath for his ideas on this.
>
> Acquiring CS# for NAND is done on a few boards.
> It means, depending on bootloader to embed this
> information. Probably CS# being used can be set
> in the Kernel, and acquiring it can be removed.
> If ever this capbility is needed, GPMC driver
> has to be made aware of handling it.
>
> OneNAND - as it may involve reconfiguring GPMC for
> synchronous may need a quirk to handle or driver
> has to be made more intelligent to handle it.
>
> Code below comment "GPMC CLK related" may have
> to continue live in platform folders (even if the
> driver is moved to MFD) as input clock is beyond
> the control of GPMC and calculating timing for
> the peripheral may need other helpers.
>
> TODO (or not?)
> 1. NAND driver deal with GPMC NAND block
> 2. Remove struct gpmc * stored as static
> 3. Convert all peripherals to use GPMC driver
> 4. Devise method to handle OneNAND cleanly
> 5. Handle acquiring CS# cases
> 6. Convert to MFD driver
>
> Signed-off-by: Afzal Mohammed<afzal at ti.com>
> Cc: Vaibhav Hiremath<hvaibhav at ti.com>
> ---
>   arch/arm/mach-omap2/gpmc.c             | 1083 +++++++++++++++++++-------------

You should probably find the proper location first, move the code and 
convert to driver.
I will let Tony comment but this is the strategy today for all this 
pseudo driver that should not be in OMAP arch directory anymore.

>   arch/arm/plat-omap/include/plat/gpmc.h |   34 +-
>   2 files changed, 672 insertions(+), 445 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
> index 00d5108..954fa22 100644
> --- a/arch/arm/mach-omap2/gpmc.c
> +++ b/arch/arm/mach-omap2/gpmc.c
> @@ -14,8 +14,11 @@
>    */
>   #undef DEBUG
>
> +#include<linux/platform_device.h>
> +
>   #include<linux/irq.h>
>   #include<linux/kernel.h>
> +#include<linux/slab.h>
>   #include<linux/init.h>
>   #include<linux/err.h>
>   #include<linux/clk.h>
> @@ -64,248 +67,99 @@
>   #define ENABLE_PREFETCH		(0x1<<  7)
>   #define DMA_MPU_MODE		2
>
> -/* Structure to save gpmc cs context */
> -struct gpmc_cs_config {
> -	u32 config1;
> -	u32 config2;
> -	u32 config3;
> -	u32 config4;
> -	u32 config5;
> -	u32 config6;
> -	u32 config7;
> -	int is_valid;
> -};
> -
> -/*
> - * Structure to save/restore gpmc context
> - * to support core off on OMAP3
> - */
> -struct omap3_gpmc_regs {
> -	u32 sysconfig;
> -	u32 irqenable;
> -	u32 timeout_ctrl;
> -	u32 config;
> -	u32 prefetch_config1;
> -	u32 prefetch_config2;
> -	u32 prefetch_control;
> -	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
> -};
> -
> -static struct resource	gpmc_mem_root;
> -static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
> -static DEFINE_SPINLOCK(gpmc_mem_lock);
> -static unsigned int gpmc_cs_map;	/* flag for cs which are initialized */
> -static int gpmc_ecc_used = -EINVAL;	/* cs using ecc engine */
> -
> -static void __iomem *gpmc_base;
> -
> -static struct clk *gpmc_l3_clk;
> -
> -static irqreturn_t gpmc_handle_irq(int irq, void *dev);
>
> -static void gpmc_write_reg(int idx, u32 val)
> -{
> -	__raw_writel(val, gpmc_base + idx);
> -}
> -
> -static u32 gpmc_read_reg(int idx)
> -{
> -	return __raw_readl(gpmc_base + idx);
> -}
> -
> -static void gpmc_cs_write_byte(int cs, int idx, u8 val)
> -{
> -	void __iomem *reg_addr;
> +#define	DRIVER_NAME	"omap-gpmc"
>
> -	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> -	__raw_writeb(val, reg_addr);
> -}
> +struct gpmc_child {
> +	char			*name;
> +	int			id;
> +	struct resource		*res;
> +	unsigned		num_res;
> +	struct resource		gpmc_res[GPMC_CS_NUM];
> +	unsigned		gpmc_num_res;
> +	void			*pdata;
> +	unsigned		pdata_size;
> +};
>
> -static u8 gpmc_cs_read_byte(int cs, int idx)
> -{
> -	void __iomem *reg_addr;
> +struct gpmc {
> +	struct device		*dev;
> +	unsigned long		fclk_rate;
> +	void __iomem		*io_base;
> +	unsigned long		phys_base;
> +	u32			memsize;
> +	unsigned		cs_map;
> +	int			ecc_used;
> +	spinlock_t		mem_lock;
> +	struct resource		mem_root;
> +	struct resource		cs_mem[GPMC_CS_NUM];
> +	struct gpmc_child	child_device[GPMC_CS_NUM];
> +	unsigned		num_child;
> +	unsigned		num_device;
> +};
>
> -	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> -	return __raw_readb(reg_addr);
> -}
> +static struct gpmc *gpmc;
>
> +/* Make function static */
>   void gpmc_cs_write_reg(int cs, int idx, u32 val)
>   {
>   	void __iomem *reg_addr;
>
> -	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> -	__raw_writel(val, reg_addr);
> +	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> +	writel(val, reg_addr);
>   }
>
> +/* Make function static */
>   u32 gpmc_cs_read_reg(int cs, int idx)
>   {
>   	void __iomem *reg_addr;
>
> -	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> -	return __raw_readl(reg_addr);
> +	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> +	return readl(reg_addr);
>   }
>
> -/* TODO: Add support for gpmc_fck to clock framework and use it */
> -unsigned long gpmc_get_fclk_period(void)
> +static void gpmc_write_reg(int idx, u32 val)
>   {
> -	unsigned long rate = clk_get_rate(gpmc_l3_clk);
> -
> -	if (rate == 0) {
> -		printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
> -		return 0;
> -	}
> -
> -	rate /= 1000;
> -	rate = 1000000000 / rate;	/* In picoseconds */
> -
> -	return rate;
> +	writel(val, gpmc->io_base + idx);
>   }
>
> -unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
> +static u32 gpmc_read_reg(int idx)
>   {
> -	unsigned long tick_ps;
> -
> -	/* Calculate in picosecs to yield more exact results */
> -	tick_ps = gpmc_get_fclk_period();
> -
> -	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
> +	return readl(gpmc->io_base + idx);
>   }
>
> -unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
> +static void gpmc_cs_write_byte(int cs, int idx, u8 val)
>   {
> -	unsigned long tick_ps;
> -
> -	/* Calculate in picosecs to yield more exact results */
> -	tick_ps = gpmc_get_fclk_period();
> -
> -	return (time_ps + tick_ps - 1) / tick_ps;
> -}
> +	void __iomem *reg_addr;
>
> -unsigned int gpmc_ticks_to_ns(unsigned int ticks)
> -{
> -	return ticks * gpmc_get_fclk_period() / 1000;
> +	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> +	writeb(val, reg_addr);
>   }
>
> -unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
> +static u8 gpmc_cs_read_byte(int cs, int idx)
>   {
> -	unsigned long ticks = gpmc_ns_to_ticks(time_ns);
> +	void __iomem *reg_addr;
>
> -	return ticks * gpmc_get_fclk_period() / 1000;
> +	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> +	return readb(reg_addr);
>   }
>
> -#ifdef DEBUG
> -static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
> -			       int time, const char *name)
> -#else
> -static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
> -			       int time)
> -#endif
> +static int gpmc_cs_set_reserved(int cs, int reserved)
>   {
> -	u32 l;
> -	int ticks, mask, nr_bits;
> -
> -	if (time == 0)
> -		ticks = 0;
> -	else
> -		ticks = gpmc_ns_to_ticks(time);
> -	nr_bits = end_bit - st_bit + 1;
> -	if (ticks>= 1<<  nr_bits) {
> -#ifdef DEBUG
> -		printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks>= %d\n",
> -				cs, name, time, ticks, 1<<  nr_bits);
> -#endif
> -		return -1;
> -	}
> +	if (cs>  GPMC_CS_NUM)
> +		return -ENODEV;
>
> -	mask = (1<<  nr_bits) - 1;
> -	l = gpmc_cs_read_reg(cs, reg);
> -#ifdef DEBUG
> -	printk(KERN_INFO
> -		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
> -	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
> -			(l>>  st_bit)&  mask, time);
> -#endif
> -	l&= ~(mask<<  st_bit);
> -	l |= ticks<<  st_bit;
> -	gpmc_cs_write_reg(cs, reg, l);
> +	gpmc->cs_map&= ~(1<<  cs);
> +	gpmc->cs_map |= (reserved ? 1 : 0)<<  cs;
>
>   	return 0;
>   }
>
> -#ifdef DEBUG
> -#define GPMC_SET_ONE(reg, st, end, field) \
> -	if (set_gpmc_timing_reg(cs, (reg), (st), (end),		\
> -			t->field, #field)<  0)			\
> -		return -1
> -#else
> -#define GPMC_SET_ONE(reg, st, end, field) \
> -	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field)<  0) \
> -		return -1
> -#endif
> -
> -int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
> -{
> -	int div;
> -	u32 l;
> -
> -	l = sync_clk + (gpmc_get_fclk_period() - 1);
> -	div = l / gpmc_get_fclk_period();
> -	if (div>  4)
> -		return -1;
> -	if (div<= 0)
> -		div = 1;
> -
> -	return div;
> -}
> -
> -int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
> +static int gpmc_cs_reserved(int cs)
>   {
> -	int div;
> -	u32 l;
> -
> -	div = gpmc_cs_calc_divider(cs, t->sync_clk);
> -	if (div<  0)
> -		return -1;
> -
> -	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
> -
> -	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
> -
> -	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
> -
> -	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
> -
> -	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
> -
> -	if (cpu_is_omap34xx()) {
> -		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
> -		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
> -	}
> -
> -	/* caller is expected to have initialized CONFIG1 to cover
> -	 * at least sync vs async
> -	 */
> -	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
> -	if (l&  (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
> -#ifdef DEBUG
> -		printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
> -				cs, (div * gpmc_get_fclk_period()) / 1000, div);
> -#endif
> -		l&= ~0x03;
> -		l |= (div - 1);
> -		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
> -	}
> +	if (cs>  GPMC_CS_NUM)
> +		return -ENODEV;
>
> -	return 0;
> +	return gpmc->cs_map&  (1<<  cs);
>   }
>
>   static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
> @@ -332,17 +186,6 @@ static void gpmc_cs_disable_mem(int cs)
>   	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
>   }
>
> -static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
> -{
> -	u32 l;
> -	u32 mask;
> -
> -	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
> -	*base = (l&  0x3f)<<  GPMC_CHUNK_SHIFT;
> -	mask = (l>>  8)&  0x0f;
> -	*size = (1<<  GPMC_SECTION_SHIFT) - (mask<<  GPMC_CHUNK_SHIFT);
> -}
> -
>   static int gpmc_cs_mem_enabled(int cs)
>   {
>   	u32 l;
> @@ -351,25 +194,6 @@ static int gpmc_cs_mem_enabled(int cs)
>   	return l&  GPMC_CONFIG7_CSVALID;
>   }
>
> -int gpmc_cs_set_reserved(int cs, int reserved)
> -{
> -	if (cs>  GPMC_CS_NUM)
> -		return -ENODEV;
> -
> -	gpmc_cs_map&= ~(1<<  cs);
> -	gpmc_cs_map |= (reserved ? 1 : 0)<<  cs;
> -
> -	return 0;
> -}
> -
> -int gpmc_cs_reserved(int cs)
> -{
> -	if (cs>  GPMC_CS_NUM)
> -		return -ENODEV;
> -
> -	return gpmc_cs_map&  (1<<  cs);
> -}
> -
>   static unsigned long gpmc_mem_align(unsigned long size)
>   {
>   	int order;
> @@ -384,24 +208,9 @@ static unsigned long gpmc_mem_align(unsigned long size)
>   	return size;
>   }
>
> -static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
> -{
> -	struct resource	*res =&gpmc_cs_mem[cs];
> -	int r;
> -
> -	size = gpmc_mem_align(size);
> -	spin_lock(&gpmc_mem_lock);
> -	res->start = base;
> -	res->end = base + size - 1;
> -	r = request_resource(&gpmc_mem_root, res);
> -	spin_unlock(&gpmc_mem_lock);
> -
> -	return r;
> -}
> -
>   int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
>   {
> -	struct resource *res =&gpmc_cs_mem[cs];
> +	struct resource *res =&gpmc->cs_mem[cs];
>   	int r = -1;
>
>   	if (cs>  GPMC_CS_NUM)
> @@ -411,7 +220,7 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
>   	if (size>  (1<<  GPMC_SECTION_SHIFT))
>   		return -ENOMEM;
>
> -	spin_lock(&gpmc_mem_lock);
> +	spin_lock(&gpmc->mem_lock);
>   	if (gpmc_cs_reserved(cs)) {
>   		r = -EBUSY;
>   		goto out;
> @@ -419,7 +228,7 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
>   	if (gpmc_cs_mem_enabled(cs))
>   		r = adjust_resource(res, res->start&  ~(size - 1), size);
>   	if (r<  0)
> -		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
> +		r = allocate_resource(&gpmc->mem_root, res, size, 0, ~0,
>   				      size, NULL, NULL);
>   	if (r<  0)
>   		goto out;
> @@ -428,66 +237,28 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
>   	*base = res->start;
>   	gpmc_cs_set_reserved(cs, 1);
>   out:
> -	spin_unlock(&gpmc_mem_lock);
> +	spin_unlock(&gpmc->mem_lock);
>   	return r;
>   }
>   EXPORT_SYMBOL(gpmc_cs_request);
>
>   void gpmc_cs_free(int cs)
>   {
> -	spin_lock(&gpmc_mem_lock);
> +	spin_lock(&gpmc->mem_lock);
>   	if (cs>= GPMC_CS_NUM || cs<  0 || !gpmc_cs_reserved(cs)) {
>   		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
>   		BUG();
> -		spin_unlock(&gpmc_mem_lock);
> +		spin_unlock(&gpmc->mem_lock);
>   		return;
>   	}
>   	gpmc_cs_disable_mem(cs);
> -	release_resource(&gpmc_cs_mem[cs]);
> +	release_resource(&gpmc->cs_mem[cs]);
>   	gpmc_cs_set_reserved(cs, 0);
> -	spin_unlock(&gpmc_mem_lock);
> +	spin_unlock(&gpmc->mem_lock);
>   }
>   EXPORT_SYMBOL(gpmc_cs_free);
>
>   /**
> - * gpmc_read_status - read access request to get the different gpmc status
> - * @cmd: command type
> - * @return status
> - */
> -int gpmc_read_status(int cmd)
> -{
> -	int	status = -EINVAL;
> -	u32	regval = 0;
> -
> -	switch (cmd) {
> -	case GPMC_GET_IRQ_STATUS:
> -		status = gpmc_read_reg(GPMC_IRQSTATUS);
> -		break;
> -
> -	case GPMC_PREFETCH_FIFO_CNT:
> -		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
> -		status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
> -		break;
> -
> -	case GPMC_PREFETCH_COUNT:
> -		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
> -		status = GPMC_PREFETCH_STATUS_COUNT(regval);
> -		break;
> -
> -	case GPMC_STATUS_BUFFER:
> -		regval = gpmc_read_reg(GPMC_STATUS);
> -		/* 1 : buffer is available to write */
> -		status = regval&  GPMC_STATUS_BUFF_EMPTY;
> -		break;
> -
> -	default:
> -		printk(KERN_ERR "gpmc_read_status: Not supported\n");
> -	}
> -	return status;
> -}
> -EXPORT_SYMBOL(gpmc_read_status);
> -
> -/**
>    * gpmc_cs_configure - write request to configure gpmc
>    * @cs: chip select number
>    * @cmd: command type
> @@ -555,120 +326,143 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
>   }
>   EXPORT_SYMBOL(gpmc_cs_configure);
>
> -/**
> - * gpmc_nand_read - nand specific read access request
> - * @cs: chip select number
> - * @cmd: command type
> +/* This is a duplication of an existing function; before GPMC probe
> +   invocation, platform code may need to find divider value, hence
> +   other function (gpmc_cs_calc_divider) is not removed, functions
> +   like it that are required by platform, probably can be put in
> +   common omap platform file. gpmc_calc_divider will get invoked
> +   only after GPMC driver gets probed. gpmc_cs_calc_divider is not
> +   invoked by GPMC driver to cleanly separate platform&  driver
> +   code, although both should return sme value.
>    */
> -int gpmc_nand_read(int cs, int cmd)
> +static int gpmc_calc_divider(u32 sync_clk)
>   {
> -	int rval = -EINVAL;
> -
> -	switch (cmd) {
> -	case GPMC_NAND_DATA:
> -		rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
> -		break;
> +	int div;
> +	u32 l;
>
> -	default:
> -		printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
> -	}
> -	return rval;
> +	l = sync_clk + (gpmc->fclk_rate - 1);
> +	div = l / gpmc->fclk_rate;
> +	if (div>  4)
> +		return -1;
> +	if (div<= 0)
> +		div = 1;
> +
> +	return div;
>   }
> -EXPORT_SYMBOL(gpmc_nand_read);
>
> -/**
> - * gpmc_nand_write - nand specific write request
> - * @cs: chip select number
> - * @cmd: command type
> - * @wval: value to write
> - */
> -int gpmc_nand_write(int cs, int cmd, int wval)
> +static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
> +			       int time, const char *name)
>   {
> -	int err = 0;
> -
> -	switch (cmd) {
> -	case GPMC_NAND_COMMAND:
> -		gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
> -		break;
> +	u32 l;
> +	int ticks, mask, nr_bits;
>
> -	case GPMC_NAND_ADDRESS:
> -		gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
> -		break;
> +	if (time == 0)
> +		ticks = 0;
> +	else
> +		ticks = gpmc_ns_to_ticks(time);
> +	nr_bits = end_bit - st_bit + 1;
> +	if (ticks>= 1<<  nr_bits) {
> +		printk(KERN_DEBUG "GPMC CS%d: %-10s* %3d ns, %3d ticks>= %d\n",

Nit, but since you are cleaning extensively this code, you should use 
pr_ macros instead or even dev_ macros since you do have a real driver 
now with real devices now.

> +				cs, name, time, ticks, 1<<  nr_bits);
> +		return -1;
> +	}
>
> -	case GPMC_NAND_DATA:
> -		gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
> +	mask = (1<<  nr_bits) - 1;
> +	l = gpmc_cs_read_reg(cs, reg);
> +	printk(KERN_DEBUG
> +		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
> +	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
> +			(l>>  st_bit)&  mask, time);
> +	l&= ~(mask<<  st_bit);
> +	l |= ticks<<  st_bit;
> +	gpmc_cs_write_reg(cs, reg, l);
>
> -	default:
> -		printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
> -		err = -EINVAL;
> -	}
> -	return err;
> +	return 0;
>   }
> -EXPORT_SYMBOL(gpmc_nand_write);
> -
>
> +#define GPMC_SET_ONE(reg, st, end, field) \
> +	do {							\
> +		if (set_gpmc_timing_reg(cs, (reg), (st), (end),	\
> +				t->field, #field)<  0)		\
> +			return -1;				\
> +	} while (0)
>
> -/**
> - * gpmc_prefetch_enable - configures and starts prefetch transfer
> - * @cs: cs (chip select) number
> - * @fifo_th: fifo threshold to be used for read/ write
> - * @dma_mode: dma mode enable (1) or disable (0)
> - * @u32_count: number of bytes to be transferred
> - * @is_write: prefetch read(0) or write post(1) mode
> - */
> -int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
> -				unsigned int u32_count, int is_write)
> +int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
>   {
> +	int div;
> +	u32 l;
>
> -	if (fifo_th>  PREFETCH_FIFOTHRESHOLD_MAX) {
> -		pr_err("gpmc: fifo threshold is not supported\n");
> +	div = gpmc_calc_divider(t->sync_clk);
> +	if (div<  0)
>   		return -1;
> -	} else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
> -		/* Set the amount of bytes to be prefetched */
> -		gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
>
> -		/* Set dma/mpu mode, the prefetch read / post write and
> -		 * enable the engine. Set which cs is has requested for.
> -		 */
> -		gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs<<  CS_NUM_SHIFT) |
> -					PREFETCH_FIFOTHRESHOLD(fifo_th) |
> -					ENABLE_PREFETCH |
> -					(dma_mode<<  DMA_MPU_MODE) |
> -					(0x1&  is_write)));
> +	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
>
> -		/*  Start the prefetch engine */
> -		gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
> -	} else {
> -		return -EBUSY;
> +	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
> +
> +	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
> +
> +	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
> +
> +	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
> +
> +	if (cpu_is_omap34xx()) {
> +		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
> +		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
> +	}
> +
> +	/* caller is expected to have initialized CONFIG1 to cover
> +	 * at least sync vs async
> +	 */
> +	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
> +	if (l&  (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
> +		printk(KERN_DEBUG "GPMC CS%d CLK period is %lu ns (div %d)\n",
> +				cs, (div * gpmc_get_fclk_period()) / 1000, div);
> +		l&= ~0x03;
> +		l |= (div - 1);
> +		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
>   	}
>
>   	return 0;
>   }
> -EXPORT_SYMBOL(gpmc_prefetch_enable);
>
> -/**
> - * gpmc_prefetch_reset - disables and stops the prefetch engine
> - */
> -int gpmc_prefetch_reset(int cs)
> +static __devinit void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
>   {
> -	u32 config1;
> +	u32 l;
> +	u32 mask;
>
> -	/* check if the same module/cs is trying to reset */
> -	config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
> -	if (((config1>>  CS_NUM_SHIFT)&  0x7) != cs)
> -		return -EINVAL;
> +	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
> +	*base = (l&  0x3f)<<  GPMC_CHUNK_SHIFT;
> +	mask = (l>>  8)&  0x0f;
> +	*size = (1<<  GPMC_SECTION_SHIFT) - (mask<<  GPMC_CHUNK_SHIFT);
> +}
>
> -	/* Stop the PFPW engine */
> -	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
> +static __devinit
> +int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
> +{
> +	struct resource	*res =&gpmc->cs_mem[cs];
> +	int r;
>
> -	/* Reset/disable the PFPW engine */
> -	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
> +	size = gpmc_mem_align(size);
> +	spin_lock(&gpmc->mem_lock);
> +	res->start = base;
> +	res->end = base + size - 1;
> +	r = request_resource(&gpmc->mem_root, res);
> +	spin_unlock(&gpmc->mem_lock);
>
> -	return 0;
> +	return r;
>   }
> -EXPORT_SYMBOL(gpmc_prefetch_reset);
>
> -static void __init gpmc_mem_init(void)
> +static __devinit void gpmc_mem_init(void)
>   {
>   	int cs;
>   	unsigned long boot_rom_space = 0;
> @@ -680,8 +474,8 @@ static void __init gpmc_mem_init(void)
>   	/* In apollon the CS0 is mapped as 0x0000 0000 */
>   	if (machine_is_omap_apollon())
>   		boot_rom_space = 0;
> -	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
> -	gpmc_mem_root.end = GPMC_MEM_END;
> +	gpmc->mem_root.start = GPMC_MEM_START + boot_rom_space;
> +	gpmc->mem_root.end = GPMC_MEM_END;
>
>   	/* Reserve all regions that has been set up by bootloader */
>   	for (cs = 0; cs<  GPMC_CS_NUM; cs++) {
> @@ -695,88 +489,245 @@ static void __init gpmc_mem_init(void)
>   	}
>   }
>
> -static int __init gpmc_init(void)
> +static inline int __devinit gpmc_find_next_child_slot(void)
>   {
> -	u32 l, irq;
> -	int cs, ret = -EINVAL;
> -	int gpmc_irq;
> -	char *ck = NULL;
> +	return gpmc->num_child;
> +}
>
> -	if (cpu_is_omap24xx()) {
> -		ck = "core_l3_ck";
> -		if (cpu_is_omap2420())
> -			l = OMAP2420_GPMC_BASE;
> -		else
> -			l = OMAP34XX_GPMC_BASE;
> -		gpmc_irq = INT_34XX_GPMC_IRQ;
> -	} else if (cpu_is_omap34xx()) {
> -		ck = "gpmc_fck";
> -		l = OMAP34XX_GPMC_BASE;
> -		gpmc_irq = INT_34XX_GPMC_IRQ;
> -	} else if (cpu_is_omap44xx()) {
> -		ck = "gpmc_ck";
> -		l = OMAP44XX_GPMC_BASE;
> -		gpmc_irq = OMAP44XX_IRQ_GPMC;
> -	}
> +static int __devinit gpmc_match_child(char *name, int id)
> +{
> +	int i;
> +	struct gpmc_child *p;
>
> -	if (WARN_ON(!ck))
> +	for (i = 0, p = gpmc->child_device; i<  gpmc->num_child; i++, p++)
> +		if (!strcmp(p->name, name)&&  (p->id == id))
> +			return i;
> +
> +	return -ENOENT;
> +}
> +
> +static __devinit int gpmc_setup_child(struct gpmc_device_pdata *gdev)
> +{
> +	struct gpmc_config *c;
> +	int i, ret = 0;
> +	struct resource res;
> +	unsigned long start;
> +
> +	start = gdev->mem_start;
> +
> +	ret = gpmc_cs_request(gdev->cs, gdev->mem_size,&start);
> +	if (IS_ERR_VALUE(ret)) {
> +		dev_err(gpmc->dev, "error: gpmc request on CS: %u\n", gdev->cs);
>   		return ret;
> +	}
>
> -	gpmc_l3_clk = clk_get(NULL, ck);
> -	if (IS_ERR(gpmc_l3_clk)) {
> -		printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
> -		BUG();
> +	c = gdev->config;
> +	if (!c) {
> +		dev_err(gpmc->dev, "config not present for CS: %u\n", gdev->cs);
> +		return -EINVAL;
>   	}
>
> -	gpmc_base = ioremap(l, SZ_4K);
> -	if (!gpmc_base) {
> -		clk_put(gpmc_l3_clk);
> -		printk(KERN_ERR "Could not get GPMC register memory\n");
> -		BUG();
> +	for (i = 0; i<  gdev->num_config; c++, i++) {
> +		ret = gpmc_cs_configure(gdev->cs, c->cmd, c->val);
> +		if (IS_ERR_VALUE(ret)) {
> +			dev_err(gpmc->dev, "invalid cmd or value on CS:	\
> +			 %u: cmd: %d value: %d\n", gdev->cs, c->cmd, c->val);
> +			return ret;
> +		}
> +	}
> +
> +	if (gdev->timing) {
> +		ret = gpmc_cs_set_timings(gdev->cs, gdev->timing);
> +		if (IS_ERR_VALUE(ret)) {
> +			dev_err(gpmc->dev, "error: setting timing on CS: %d\n",
> +								gdev->cs);
> +			return ret;
> +		}
>   	}
>
> -	clk_enable(gpmc_l3_clk);
> +	res.start = start + gdev->mem_offset;
> +	res.end = res.start + gdev->mem_size - 1;
> +	res.flags = IORESOURCE_MEM;
> +
> +	i = gpmc_match_child(gdev->name, gdev->id);
> +	/* i>= GPMC_CS_NUM can never happen, this is for compiler to shutup */
> +	if (i>= 0&&  i<  GPMC_CS_NUM) {
> +		int j;
> +
> +		j = gpmc->child_device[i].gpmc_num_res;
> +		gpmc->child_device[i].gpmc_res[j] = res;
> +	} else if (i == -ENOENT) {
> +		i = gpmc_find_next_child_slot();
> +		if (IS_ERR_VALUE(i)) {
> +			dev_err(gpmc->dev, "error: childs exceeded\n");
> +			return -ENODEV;
> +		}
> +		gpmc->child_device[i].name = gdev->name;
> +		gpmc->child_device[i].id = gdev->id;
> +		gpmc->child_device[i].pdata = gdev->pdata;
> +		gpmc->child_device[i].pdata_size = gdev->pdata_size;
> +		gpmc->child_device[i].gpmc_res[0] = res;
> +	} else {
> +		/* should never come here */
> +		dev_err(gpmc->dev, "error: childs exceeded\n");
> +		return -ENODEV;
> +	}
> +
> +	gpmc->child_device[i].gpmc_num_res++;
> +
> +	return ret;
> +}
> +
> +static __devinit int gpmc_create_child(int cnt)
> +{
> +	struct gpmc_child *p = gpmc->child_device + cnt;
> +	int num = p->num_res + p->gpmc_num_res;
> +	struct resource *res;
> +
> +	res = kzalloc(sizeof(struct resource) * num, GFP_KERNEL);
> +	if (!res) {
> +		dev_err(gpmc->dev, "error: allocating memory\n");
> +		return -ENOMEM;
> +	}
> +
> +	memcpy((char *)res, (const char *) p->gpmc_res,
> +				sizeof(struct resource) * p->gpmc_num_res);
> +	memcpy((char *)(res + p->gpmc_num_res), (const char *)p->res,
> +				sizeof(struct resource) * p->num_res);
> +
> +	platform_device_register_resndata(gpmc->dev, p->name, p->id, res,
> +						num, p->pdata, p->pdata_size);
> +
> +	return 0;
> +}
> +
> +static __devinit int gpmc_probe(struct platform_device *pdev)
> +{
> +	u32 l;
> +	int i;
> +	int ret = -EINVAL;
> +	struct resource *res = NULL;
> +	struct gpmc_pdata *gd = dev_get_platdata(&pdev->dev);
> +	struct gpmc_device_pdata *gdev = NULL;
> +
> +	gpmc = devm_kzalloc(&pdev->dev, sizeof(struct gpmc), GFP_KERNEL);
> +	if (!gpmc) {
> +		dev_err(&pdev->dev, "Failed to allocate memory\n");
> +		return -ENOMEM;
> +	}
> +
> +	gpmc->dev =&pdev->dev;
> +	gpmc->fclk_rate = gd->fclk_rate;
> +	gpmc->num_device = gd->num_device;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		ret = -ENOENT;
> +		dev_err(gpmc->dev, "Failed to get resource: memory\n");
> +		goto err_res;
> +	}
> +	gpmc->phys_base = res->start;
> +	gpmc->memsize = resource_size(res);
> +
> +	if (request_mem_region(gpmc->phys_base,
> +		gpmc->memsize, DRIVER_NAME) == NULL) {
> +		ret = -ENOMEM;
> +		dev_err(gpmc->dev, "Failed to request memory region\n");
> +		goto err_mem;
> +	}
> +
> +	gpmc->io_base = ioremap(gpmc->phys_base, gpmc->memsize);
> +	if (!gpmc->io_base) {
> +		ret = -ENOMEM;
> +		dev_err(gpmc->dev, "Failed to ioremap memory\n");
> +		goto err_remap;
> +	}
> +
> +	gpmc->ecc_used = -EINVAL;
> +	spin_lock_init(&gpmc->mem_lock);
> +	platform_set_drvdata(pdev, gpmc);
>
>   	l = gpmc_read_reg(GPMC_REVISION);
> -	printk(KERN_INFO "GPMC revision %d.%d\n", (l>>  4)&  0x0f, l&  0x0f);
> -	/* Set smart idle mode and automatic L3 clock gating */
> -	l = gpmc_read_reg(GPMC_SYSCONFIG);
> -	l&= 0x03<<  3;
> -	l |= (0x02<<  3) | (1<<  0);
> -	gpmc_write_reg(GPMC_SYSCONFIG, l);
> +	dev_info(gpmc->dev, "GPMC revision %d.%d\n", (l>>  4)&  0x0f, l&  0x0f);
> +
>   	gpmc_mem_init();
>
> -	/* initalize the irq_chained */
> -	irq = OMAP_GPMC_IRQ_BASE;
> -	for (cs = 0; cs<  GPMC_CS_NUM; cs++) {
> -		irq_set_chip_and_handler(irq,&dummy_irq_chip,
> -						handle_simple_irq);
> -		set_irq_flags(irq, IRQF_VALID);
> -		irq++;
> +	for (i = 0, gdev = gd->device_pdata; i<  gd->num_device; gdev++, i++) {
> +		ret = gpmc_setup_child(gdev);
> +		if (IS_ERR_VALUE(ret))
> +			dev_err(gpmc->dev, "gpmc setup on CS: %u failed\n",
> +								gdev->cs);
> +		else
> +			gpmc->num_child++;
>   	}
>
> -	ret = request_irq(gpmc_irq,
> -			gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
> -	if (ret)
> -		pr_err("gpmc: irq-%d could not claim: err %d\n",
> -						gpmc_irq, ret);
> +	/* XXX: This would get modified once MFD */
> +	for (i = 0; i<  gpmc->num_child; i++)
> +		gpmc_create_child(i);
> +
> +	return ret;
> +
> +err_remap:
> +	release_mem_region(gpmc->phys_base, gpmc->memsize);
> +err_mem:
> +err_res:
> +	devm_kfree(&pdev->dev, gpmc);
>   	return ret;
>   }
> -postcore_initcall(gpmc_init);
>
> -static irqreturn_t gpmc_handle_irq(int irq, void *dev)
> +static __devexit int gpmc_remove(struct platform_device *pdev)
>   {
> -	u8 cs;
> +	struct gpmc *gpmc = platform_get_drvdata(pdev);
>
> -	/* check cs to invoke the irq */
> -	cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1))>>  CS_NUM_SHIFT)&  0x7;
> -	if (OMAP_GPMC_IRQ_BASE+cs<= OMAP_GPMC_IRQ_END)
> -		generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
> +	platform_set_drvdata(pdev, NULL);
> +	iounmap(gpmc->io_base);
> +	release_mem_region(gpmc->phys_base, gpmc->memsize);
> +	devm_kfree(&pdev->dev, gpmc);
>
> -	return IRQ_HANDLED;
> +	return 0;
>   }
>
> +static struct platform_driver gpmc_driver = {
> +	.probe		= gpmc_probe,
> +	.remove		= __devexit_p(gpmc_remove),
> +	.driver		= {
> +		.name	= DRIVER_NAME,
> +		.owner	= THIS_MODULE,
> +	},
> +};
> +
> +module_platform_driver(gpmc_driver);
> +
> +/* Suspend - resume support */
> +
>   #ifdef CONFIG_ARCH_OMAP3
> +/* Structure to save gpmc cs context */
> +struct gpmc_cs_config {
> +	u32 config1;
> +	u32 config2;
> +	u32 config3;
> +	u32 config4;
> +	u32 config5;
> +	u32 config6;
> +	u32 config7;
> +	int is_valid;
> +};

OK, so this code was just moved and not removed. Becasue of these big 
code move, the patch is not super readable. We cannot really see what 
part is new and what was changed.

Maybe you should try to split that in sevarl patches or minized the move.

> +
> +/*
> + * Structure to save/restore gpmc context
> + * to support core off on OMAP3
> + */
> +struct omap3_gpmc_regs {
> +	u32 sysconfig;
> +	u32 irqenable;
> +	u32 timeout_ctrl;
> +	u32 config;
> +	u32 prefetch_config1;
> +	u32 prefetch_config2;
> +	u32 prefetch_control;
> +	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
> +};
> +
>   static struct omap3_gpmc_regs gpmc_context;
>
>   void omap3_gpmc_save_context(void)
> @@ -843,6 +794,159 @@ void omap3_gpmc_restore_context(void)
>   }
>   #endif /* CONFIG_ARCH_OMAP3 */
>
> +/* GPMC NAND related */
> +
> +/**
> + * gpmc_read_status - read access request to get the different gpmc status
> + * @cmd: command type
> + * @return status
> + */
> +int gpmc_read_status(int cmd)
> +{
> +	int	status = -EINVAL;
> +	u32	regval = 0;
> +
> +	switch (cmd) {
> +	case GPMC_GET_IRQ_STATUS:
> +		status = gpmc_read_reg(GPMC_IRQSTATUS);
> +		break;
> +
> +	case GPMC_PREFETCH_FIFO_CNT:
> +		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
> +		status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
> +		break;
> +
> +	case GPMC_PREFETCH_COUNT:
> +		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
> +		status = GPMC_PREFETCH_STATUS_COUNT(regval);
> +		break;
> +
> +	case GPMC_STATUS_BUFFER:
> +		regval = gpmc_read_reg(GPMC_STATUS);
> +		/* 1 : buffer is available to write */
> +		status = regval&  GPMC_STATUS_BUFF_EMPTY;
> +		break;
> +
> +	default:
> +		printk(KERN_ERR "gpmc_read_status: Not supported\n");
> +	}
> +	return status;
> +}
> +EXPORT_SYMBOL(gpmc_read_status);
> +
> +/**
> + * gpmc_nand_read - nand specific read access request
> + * @cs: chip select number
> + * @cmd: command type
> + */
> +int gpmc_nand_read(int cs, int cmd)
> +{
> +	int rval = -EINVAL;
> +
> +	switch (cmd) {
> +	case GPMC_NAND_DATA:
> +		rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
> +		break;
> +
> +	default:
> +		printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
> +	}
> +	return rval;
> +}
> +EXPORT_SYMBOL(gpmc_nand_read);
> +
> +/**
> + * gpmc_nand_write - nand specific write request
> + * @cs: chip select number
> + * @cmd: command type
> + * @wval: value to write
> + */
> +int gpmc_nand_write(int cs, int cmd, int wval)
> +{
> +	int err = 0;
> +
> +	switch (cmd) {
> +	case GPMC_NAND_COMMAND:
> +		gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
> +		break;
> +
> +	case GPMC_NAND_ADDRESS:
> +		gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
> +		break;
> +
> +	case GPMC_NAND_DATA:
> +		gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
> +
> +	default:
> +		printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
> +		err = -EINVAL;
> +	}
> +	return err;
> +}
> +EXPORT_SYMBOL(gpmc_nand_write);
> +
> +
> +
> +/**
> + * gpmc_prefetch_enable - configures and starts prefetch transfer
> + * @cs: cs (chip select) number
> + * @fifo_th: fifo threshold to be used for read/ write
> + * @dma_mode: dma mode enable (1) or disable (0)
> + * @u32_count: number of bytes to be transferred
> + * @is_write: prefetch read(0) or write post(1) mode
> + */
> +int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
> +				unsigned int u32_count, int is_write)
> +{
> +
> +	if (fifo_th>  PREFETCH_FIFOTHRESHOLD_MAX) {
> +		pr_err("gpmc: fifo threshold is not supported\n");
> +		return -1;
> +	} else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
> +		/* Set the amount of bytes to be prefetched */
> +		gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
> +
> +		/* Set dma/mpu mode, the prefetch read / post write and
> +		 * enable the engine. Set which cs is has requested for.
> +		 */
> +		gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs<<  CS_NUM_SHIFT) |
> +					PREFETCH_FIFOTHRESHOLD(fifo_th) |
> +					ENABLE_PREFETCH |
> +					(dma_mode<<  DMA_MPU_MODE) |
> +					(0x1&  is_write)));
> +
> +		/*  Start the prefetch engine */
> +		gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
> +	} else {
> +		return -EBUSY;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(gpmc_prefetch_enable);
> +
> +/**
> + * gpmc_prefetch_reset - disables and stops the prefetch engine
> + */
> +int gpmc_prefetch_reset(int cs)
> +{
> +	u32 config1;
> +
> +	/* check if the same module/cs is trying to reset */
> +	config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
> +	if (((config1>>  CS_NUM_SHIFT)&  0x7) != cs)
> +		return -EINVAL;
> +
> +	/* Stop the PFPW engine */
> +	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
> +
> +	/* Reset/disable the PFPW engine */
> +	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(gpmc_prefetch_reset);
> +
>   /**
>    * gpmc_enable_hwecc - enable hardware ecc functionality
>    * @cs: chip select number
> @@ -855,10 +959,10 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
>   	unsigned int val;
>
>   	/* check if ecc module is in used */
> -	if (gpmc_ecc_used != -EINVAL)
> +	if (gpmc->ecc_used != -EINVAL)
>   		return -EINVAL;
>
> -	gpmc_ecc_used = cs;
> +	gpmc->ecc_used = cs;
>
>   	/* clear ecc and enable bits */
>   	val = ((0x00000001<<8) | 0x00000001);
> @@ -906,7 +1010,7 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
>   {
>   	unsigned int val = 0x0;
>
> -	if (gpmc_ecc_used != cs)
> +	if (gpmc->ecc_used != cs)
>   		return -EINVAL;
>
>   	/* read ecc result */
> @@ -916,7 +1020,100 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
>   	/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
>   	*ecc_code++ = ((val>>  8)&  0x0f) | ((val>>  20)&  0xf0);
>
> -	gpmc_ecc_used = -EINVAL;
> +	gpmc->ecc_used = -EINVAL;
>   	return 0;
>   }
>   EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
> +
> +/* GPMC CLK related */
> +
> +static struct clk *gpmc_l3_clk;
> +
> +static int __init gpmc_clk_init(void)
> +{
> +	char *ck = NULL;
> +
> +	if (cpu_is_omap24xx())
> +		ck = "core_l3_ck";
> +	else if (cpu_is_omap34xx())
> +		ck = "gpmc_fck";
> +	else if (cpu_is_omap44xx())
> +		ck = "gpmc_ck";

Please don't do that anymore. The CLKDEV array is done to create alias 
and avoid this kind of hacks. Moreover you should rely on hwmod for 
device creation and thus main clock alias will already be populated for 
free.

Regards,
Benoit


From arnd at arndb.de  Fri Mar 23 04:48:51 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 23 Mar 2012 08:48:51 +0000
Subject: [PATCH] SPEAr: Use CLKDEV_INIT for defining clk_lookups
In-Reply-To: <57103011de8747743f95eb41c8dc30c632d097a8.1332490263.git.viresh.kumar@st.com>
References: <57103011de8747743f95eb41c8dc30c632d097a8.1332490263.git.viresh.kumar@st.com>
Message-ID: <201203230848.52010.arnd@arndb.de>

On Friday 23 March 2012, Viresh Kumar wrote:
> Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
> ---
> Arnd,
> 
> I have applied this patch after applying Stefan's patch:
> "ARM: SPEAr600: Change FSMC and SMI clock names"
> 
> I have applied both these patches in my following branch:
> spear-dt
> 

Hi Viresh,

Since we're in the middle of the merge window now, I would
prefer not to pull any cosmetic changes or new features but
instead just take the bug fix. Once -rc1 is done, we will
start taking patches for v3.5.

If the second patch is actually required and nit just cosmetic,
please provide a description why that is so.

Finally, the branch you mentioned does not seem to be there
on the server.

I recommend using 'git request-pull', which will actually check
that the branch you refer to can be pulled and holds the right
contents.

	Arnd



From arnd at arndb.de  Fri Mar 23 04:38:54 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 23 Mar 2012 08:38:54 +0000
Subject: [PATCH] USB: gadget driver for LPC32xx
In-Reply-To: <1332191930-2433-1-git-send-email-stigge@antcom.de>
References: <1332191930-2433-1-git-send-email-stigge@antcom.de>
Message-ID: <201203230838.55014.arnd@arndb.de>

On Monday 19 March 2012, Roland Stigge wrote:
> This patch adds a USB gadget driver.
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>

Some more comments:
> +
> +	/* DMA support */
> +	dma_addr_t		*udca_v_base;

I think you mean either

	u32 			*udca_v_base;
or
	void			*udca_v_base;

Since it's not a pointer to dma_addr_t variables:
dma_addr_t can be either 32 or 64 bit, depending on
kernel config options, while your hardware certainly
expects a fixed size.


> +/* DD (DMA Descriptor) structure, requires word alignment, this is already
> + * defined in the LPC32XX USB device header file, but this version is slightly
> + * modified to tag some work data with each DMA descriptor. */
> +struct lpc32xx_usbd_dd_gad {
> +       struct lpc32xx_usbd_dd_gad *dd_next_phy;
> +       u32 dd_setup;
> +       dma_addr_t dd_buffer_addr;
> +       u32 dd_status;
> +       dma_addr_t dd_iso_ps_mem_addr;
> +       dma_addr_t this_dma;
> +       u32 iso_status[6]; /* 5 spare */
> +       struct lpc32xx_usbd_dd_gad *dd_next_v;
> +};

If this is a structure that is shared with hardware, it should have no
variable length fields in it, in particular no pointers or dma_addr_t members.

> +	/* Work queues related to I2C support */
> +	struct work_struct	pullup_wq;
> +	struct work_struct	vbus_wq;
> +	struct work_struct	power_wq;

These are not actually work queues, that would be
a workqueue_struct, but they are work elements or
jobs that get sent to the global workqueue.

> +	/* USB device peripheral - various */
> +	struct lpc32xx_ep	ep[NUM_ENDPOINTS];
> +	u32			enabled:1;
> +	u32			clocked:1;
> +	u32			suspended:1;
> +	u32			selfpowered:1;

defining a u32 member with a size other than 32 bits is
a bit confusing. I would suggest turning these into 'bool'
or using a single unsigned long with set_bit()/test_bit()
for clarity.

If you really like bit fields that much, using bool or
unsigned int would be more appropriate.

> +
> +#define ep_dbg(epp, fmt, arg...) \
> +	dev_dbg(epp->udc->dev, "%s:%s: " fmt, epp->ep.name, __func__, ## arg)
> +#define ep_err(epp, fmt, arg...) \
> +	dev_err(epp->udc->dev, "%s:%s: " fmt, epp->ep.name, __func__, ## arg)
> +#define ep_info(epp, fmt, arg...) \
> +	dev_info(epp->udc->dev, "%s:%s: " fmt, epp->ep.name, __func__, ## arg)
> +#define ep_warn(epp, fmt, arg...) \
> +	dev_warn(epp->udc->dev, "%s:%s:" fmt, epp->ep.name, __func__, ## arg)

it seems redundant to pass the name a second time when dev_* already prints
the device name.

> +#define UDCA_BUFF_SIZE (128)
> +
> +#define USB_CTRL		IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64)
> +#define USB_CLOCK_MASK		(AHB_M_CLOCK_ON | OTG_CLOCK_ON | \
> +				 DEV_CLOCK_ON | I2C_CLOCK_ON)
> +
> +/* USB_CTRL bit defines */
> +#define USB_SLAVE_HCLK_EN	(1 << 24)
> +#define USB_HOST_NEED_CLK_EN	(1 << 21)
> +#define USB_DEV_NEED_CLK_EN	(1 << 22)
> +
> +#define USB_OTG_CLK_CTRL	IO_ADDRESS(LPC32XX_USB_BASE + 0xFF4)
> +#define USB_OTG_CLK_STAT	IO_ADDRESS(LPC32XX_USB_BASE + 0xFF8)

All the instances of IO_ADDRESS need to be replaced by platform device
resources that you ioremap. In case of the clock register, you should
probably use the clock framework.

> +
> +static void udc_set_address(struct lpc32xx_udc *udc, u32 addr);
> +static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep);
> +static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep);
> +static int udc_ep0_in_req(struct lpc32xx_udc *udc);
> +static int udc_ep0_out_req(struct lpc32xx_udc *udc);

Best remove any forward declarations by reordering the functions in call order.

> +static void create_debug_file(struct lpc32xx_udc *udc)
> +{
> +	udc->pde = proc_create_data(debug_filename, 0, NULL, &proc_ops, udc);
> +}
> +
> +static void remove_debug_file(struct lpc32xx_udc *udc)
> +{
> +	if (udc->pde)
> +		remove_proc_entry(debug_filename, NULL);
> +}

Do not introduce new driver specific /proc files. Instead, use 
debugfs_create_file() to put the file into debugfs.
> +
> +	/* Discharge VBUS (just in case) */
> +	i2c_write(OTG1_VBUS_DISCHRG, ISP1301_I2C_OTG_CONTROL_1);
> +	mdelay(1);
> +	i2c_write(OTG1_VBUS_DISCHRG,
> +		  (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR));

mdelay() is very nasty because it blocks the CPU for a long time.
Use msleep() instead, so another process can do useful work or the
CPU can go into low power during this time.

> +	/* Enable usb_need_clk clock after transceiver is initialized */
> +	__raw_writel((__raw_readl(USB_CTRL) | (1 << 22)), USB_CTRL);

__raw_readl/__raw_writel are not appropriate for device drivers. Better
use readl/writel for normal I/O, or readl_relaxed()/writel_relaxed() if
it's performance critical and you know that the device does not perform
DMA operations that interact with those accesses.

> +/* Enables or disables the USB device pullup via the ISP1301 transceiver */
> +static void isp1301_pullup_set(int en_pullup)
> +{
> +	if (en_pullup)
> +		/* Enable pullup for bus signalling */
> +		i2c_write(OTG1_DP_PULLUP, ISP1301_I2C_OTG_CONTROL_1);
> +	else
> +		/* Enable pullup for bus signalling */
> +		i2c_write(OTG1_DP_PULLUP, (ISP1301_I2C_OTG_CONTROL_1 |
> +					   ISP1301_I2C_REG_CLEAR_ADDR));
> +}
> +
> +static void pullup_work(struct work_struct *work)
> +{
> +	struct lpc32xx_udc *udc =
> +		container_of(work, struct lpc32xx_udc, pullup_wq);
> +
> +	isp1301_pullup_set(udc->pullup);
> +}
> +
> +static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
> +				  int block)
> +{
> +	if (en_pullup == udc->pullup)
> +		return;
> +
> +	udc->pullup = en_pullup;
> +	if (block)
> +		isp1301_pullup_set(en_pullup);
> +	else
> +		schedule_work(&udc->pullup_wq);
> +}

Can you add a comment here why you need to use a workqueue in the second
case? I assume it's necessary but it's not clear from the code why that
is the case.

> +/*
> + *
> + * USB protocol engine command/data read/write helper functions
> + *
> + */
> +/* Issues a single command to the USB device state machine */
> +static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
> +{
> +	u32 pass = 0;
> +	int to;
> +
> +	/* EP may lock on CLRI if this read isn't done */
> +	u32 tmp = __raw_readl(USBD_DEVINTST(udc->udp_baseaddr));
> +	(void) tmp;
> +
> +	while (pass == 0) {
> +		__raw_writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
> +
> +		/* Write command code */
> +		__raw_writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
> +		to = 10000;
> +		while (((__raw_readl(USBD_DEVINTST(udc->udp_baseaddr)) &
> +			 USBD_CCEMPTY) == 0) && (to > 0)) {
> +			to--;
> +		}
> +
> +		if (to > 0)
> +			pass = 1;
> +	}
> +}

This can take an unbounded amount of time. I would suggest you add a
cond_resched() in an appropriate place if you are allowed to sleep here.
if not, it at least do cpu_relax().

>
> +	/*
> +	 * Resources are mapped as follows:
> +	 *  [0] = IORESOURCE_MEM, base address and size of USB space
> +	 *  [1] = IORESOURCE_IRQ, USB device low priority interrupt number
> +	 *  [2] = IORESOURCE_IRQ, USB device high priority interrupt number
> +	 *  [3] = IORESOURCE_IRQ, USB device interrupt number
> +	 *  [4] = IORESOURCE_IRQ, USB transciever interrupt number
> +	 */
> +	if (pdev->num_resources != 5) {
> +		dev_err(udc->dev, "invalid num_resources\n");
> +		return -ENODEV;
> +	}
> +
> +	if (pdev->resource[0].flags != IORESOURCE_MEM) {
> +		dev_err(udc->dev, "invalid resource type\n");
> +		return -ENODEV;
> +	}

This check looks bogus and will probably fail when you move
to device tree based probing.

> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res)
> +		return -ENXIO;
> +
> +	spin_lock_init(&udc->lock);
> +
> +	/* Get IRQs */
> +	for (i = 0; i < 4; i++) {
> +		if (pdev->resource[i + 1].flags != IORESOURCE_IRQ) {
> +			dev_err(udc->dev, "invalid resource type\n");
> +			return -ENODEV;
> +		}
> +		udc->udp_irq[i] = platform_get_irq(pdev, i);
> +	}
> +
> +	udc->io_p_start = res->start;
> +	udc->io_p_size = res->end - res->start + 1;

resource_size()

> +	/* All clocks are now on */
> +	udc->clocked = 1;
> +
> +	retval = i2c_add_driver(&isp1301_driver);
> +	if (retval < 0) {
> +		dev_err(udc->dev, "Failed to add ISP1301 driver\n");
> +		goto i2c_add_fail;
> +	}

You can't register a driver from a probe() function, that would fail horribly
if you have two devices of the same type because each driver can only be
registered once.

> +	i2c_adap = i2c_get_adapter(2);

What is "2"?

> +
> +static int __exit lpc32xx_udc_remove(struct platform_device *pdev)

__devexit

> +
> +static struct platform_driver lpc32xx_udc_driver = {
> +	.remove		= __exit_p(lpc32xx_udc_remove),

			__devexit_p()

	Arnd



From will.deacon at arm.com  Fri Mar 23 05:53:14 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 23 Mar 2012 09:53:14 +0000
Subject: [PATCH] ARM: test for PMU feature on v7 (v2 with typo fix)
In-Reply-To: <87r4wk889a.fsf@rustcorp.com.au>
References: <4F590411.9060201@arm.com> <87ty1g88dv.fsf@rustcorp.com.au>
 <87r4wk889a.fsf@rustcorp.com.au>
Message-ID: <20120323095314.GA13622@mudshark.cambridge.arm.com>

Hi Rusty,

On Fri, Mar 23, 2012 at 12:34:57AM +0000, Rusty Russell wrote:
> The v7 ARM (B4.1.82) specifies that bits 27-24 of the ID_DFR0 reg show
> what performance monitoring (if any) is available.  We should test this
> before assuming (useful for inside virtualized environments, for example).

Ok, I can see why you don't want to emulate a PMU but I don't agree with the
patch :)

> diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
> index 6933244..303d1e1 100644
> --- a/arch/arm/kernel/perf_event_v7.c
> +++ b/arch/arm/kernel/perf_event_v7.c
> @@ -1108,6 +1108,12 @@ static struct arm_pmu armv7pmu = {
>  	.max_period		= (1LLU << 32) - 1,
>  };
>  
> +static bool armv7_pmu_avail(void)
> +{
> +	/* 0 means unknown (maybe v1), 1 means v1, 2 means v2, 15 means none */
> +	return ((read_cpuid_ext(CPUID_EXT_DFR0) >> 24) & 0xF) != 0xF;
> +}
> +
>  static u32 __init armv7_read_num_pmnc_events(void)
>  {
>  	u32 nb_cnt;
> @@ -1121,6 +1127,8 @@ static u32 __init armv7_read_num_pmnc_events(void)
>  
>  static struct arm_pmu *__init armv7_a8_pmu_init(void)
>  {
> +	if (!armv7_pmu_avail())
> +		return NULL;

This code is only executed if we know for sure that we are running on a
Cortex-A8. Cortex-A8 implementations have a PMU, so I don't like having the
probe here in case we are running on a virtualised CPU that doesn't quite
match the hardware.

Would you be able to advertise 0 event counters instead and treat the PMU
largely as RAZ/WI? The only tricky bit I can see is the cycle counter, which
is mandated by the presence of a PMU, however this could also just RAZ
initially.

>  	armv7pmu.id		= ARM_PERF_PMU_ID_CA8;
>  	armv7pmu.name		= "ARMv7 Cortex-A8";
>  	armv7pmu.map_event	= armv7_a8_map_event;
> @@ -1130,6 +1138,8 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void)
>  
>  static struct arm_pmu *__init armv7_a9_pmu_init(void)
>  {
> +	if (!armv7_pmu_avail())
> +		return NULL;

Similarly for A5, A9, A7 and A15...

Cheers,

Will


From viresh.kumar at st.com  Fri Mar 23 05:56:42 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 23 Mar 2012 15:26:42 +0530
Subject: [PATCH] SPEAr: Use CLKDEV_INIT for defining clk_lookups
In-Reply-To: <201203230848.52010.arnd@arndb.de>
References: <57103011de8747743f95eb41c8dc30c632d097a8.1332490263.git.viresh.kumar@st.com>
 <201203230848.52010.arnd@arndb.de>
Message-ID: <4F6C48DA.9080005@st.com>

On 3/23/2012 2:18 PM, Arnd Bergmann wrote:
> Since we're in the middle of the merge window now, I would
> prefer not to pull any cosmetic changes or new features but
> instead just take the bug fix. Once -rc1 is done, we will
> start taking patches for v3.5.
> 

Ok.

> If the second patch is actually required and nit just cosmetic,
> please provide a description why that is so.

It is just an cosmetic one. I posted it, so stefan can work over
it and i don't have to rework on it again. What's the preferred
way of handling such stuff during merge window?

> Finally, the branch you mentioned does not seem to be there
> on the server.

I am so sorry. Actually we have two interfaces to stlinux, one
is ST internal and other is external. I have pushed the branch
at the time i posted it, but stlinux site takes a bit to get
everything synched (i came to know this today only :( ).

> I recommend using 'git request-pull', which will actually check
> that the branch you refer to can be pulled and holds the right
> contents.

Sure.

--
Viresh


From afzal at ti.com  Fri Mar 23 06:20:38 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Fri, 23 Mar 2012 10:20:38 +0000
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <4F6C445A.3040103@ti.com>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
 <4F6C445A.3040103@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A9317A6A83@DBDE01.ent.ti.com>

Hi Benoit,

On Fri, Mar 23, 2012 at 15:07:30, Cousson, Benoit wrote:
> > Final destination aimed for this driver is MFD.
> 
> Why? Are you sure this is appropriate? This is not really a 
> multifunction device but rather a bus device that can manage multiple 
> kind of devices.


Agree, this not an MFD, but can we call this a bus?, as there is
nothing like GPMC protocol. We considered it logically as MFD &
proceeded and there was a similar attempt for davinci EMIF [1,2].
   

> >   arch/arm/mach-omap2/gpmc.c             | 1083 +++++++++++++++++++-------------
> 
> You should probably find the proper location first, move the code and 
> convert to driver.
> I will let Tony comment but this is the strategy today for all this 
> pseudo driver that should not be in OMAP arch directory anymore.

Please let me know whether you have any suggestions on where GPMC driver
should live.

> > +		printk(KERN_DEBUG "GPMC CS%d: %-10s* %3d ns, %3d ticks>= %d\n",
> 
> Nit, but since you are cleaning extensively this code, you should use 
> pr_ macros instead or even dev_ macros since you do have a real driver 
> now with real devices now.

Sure, this was overlooked

> > +struct gpmc_cs_config {
> > +	u32 config1;
> > +	u32 config2;
> > +	u32 config3;
> > +	u32 config4;
> > +	u32 config5;
> > +	u32 config6;
> > +	u32 config7;
> > +	int is_valid;
> > +};
> 
> OK, so this code was just moved and not removed. Becasue of these big 
> code move, the patch is not super readable. We cannot really see what 
> part is new and what was changed.
> 
> Maybe you should try to split that in sevarl patches or minized the move.

Yes, I was really in two minds before the coding started. Lot of code in
this patch has been moved from one place to other, this was done to put
codes that handle similar things together, so that trees can be made
visible easily in the forest. And once the patch is applied, as similar
sections are together, it may be easy to make further changes

If an initial patch just to rearrange the code to have similar section
together & then new changes in a another patch, would that be fine?

> +static int __init gpmc_clk_init(void)
> > +{
> > +	char *ck = NULL;
> > +
> > +	if (cpu_is_omap24xx())
> > +		ck = "core_l3_ck";
> > +	else if (cpu_is_omap34xx())
> > +		ck = "gpmc_fck";
> > +	else if (cpu_is_omap44xx())
> > +		ck = "gpmc_ck";
> 
> Please don't do that anymore. The CLKDEV array is done to create alias 
> and avoid this kind of hacks. Moreover you should rely on hwmod for 
> device creation and thus main clock alias will already be populated for 
> free.

There are not added, they are existing code, result of rearranging the
code. These sections were given not given much importance as these won't
go into driver. But noted the point you are making.

Thanks for your quick comments.

Regards
Afzal

[1] http://lkml.indiana.edu/hypermail/linux/kernel/1202.2/03228.html
[2] http://davinci-linux-open-source.1494791.n2.nabble.com/PATCH-arm-davinci-configure-davinci-aemif-chipselects-through-OF-tt7059739.html#none



From santosh.shilimkar at ti.com  Fri Mar 23 06:35:47 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 23 Mar 2012 16:05:47 +0530
Subject: [RFC][PATCH 0/5] Convert GPMC to driver
In-Reply-To: <1332484567-21710-1-git-send-email-afzal@ti.com>
References: <1332484567-21710-1-git-send-email-afzal@ti.com>
Message-ID: <CAMQu2gzSk26kWgB4+xjB007_zogxQkR9c0po42n56wYYySz65w@mail.gmail.com>

On Fri, Mar 23, 2012 at 12:06 PM, Afzal Mohammed <afzal at ti.com> wrote:
> Hi,
>
> Convert GPCM code to be a driver. Existing GPMC
> NAND platform handling has been modified to work
> with the new GPMC driver (patches 2 & 3). Patch 5
> is to test the driver in OMAP3EVM.
>
> Once all the users has been converted to use this
> driver, would be converted to MFD type.
>
Much needed series. Thanks Afzal for doing it.

> TODO:
> 1. Let OMAP NAND driver deal with GPMC NAND block
> 2. Remove struct gpmc * stored as static
> 3. Convert all peripherals to use GPMC driver
> 4. Devise method to handle OneNAND cleanly
> 5. Handle acquiring CS# cases
> 6. Convert to MFD driver
>


> Afzal Mohammed (5):
> ?ARM: OMAP2+: gpmc: driver conversion
> ?ARM: OMAP2+: nand: create platform data structure
> ?ARM: OMAP2+: gpmc-nand: populate gpmc configs
> ?mtd: nand: omap2: obtain memory from resource
> ?OMAP3EVM: Test gpmc-nand
>
Will have a look at your series next week.

Regards
Santosh


From ludovic.desroches at atmel.com  Fri Mar 23 06:38:01 2012
From: ludovic.desroches at atmel.com (Ludovic Desroches)
Date: Fri, 23 Mar 2012 11:38:01 +0100
Subject: [PATCH 1/4] mmc: atmel-mci: add device tree support
In-Reply-To: <4F6B3C48.90002@atmel.com>
References: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
 <1332352994-20983-2-git-send-email-ludovic.desroches@atmel.com>
 <4F6B3C48.90002@atmel.com>
Message-ID: <20120323103801.GH3473@ldesroches-Latitude-E6320>

On Thu, Mar 22, 2012 at 03:50:48PM +0100, Nicolas Ferre wrote:
> On 03/21/2012 07:03 PM, ludovic.desroches at atmel.com :

[...]

> > diff --git a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
> > new file mode 100644
> > index 0000000..657f9de
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
> > @@ -0,0 +1,55 @@
> > +* Atmel High Speed MultiMedia Card Interface
> > +
> > +This controller on atmel products provides an interface for MMC, SD and SDIO
> > +types of memory cards.
> > +
> > +1) MCI node
> > +
> > +Required properties:
> > +- compatible: no blank "atmel,hsmci"
> > +- reg: should contain HSMCI registers location and length
> > +- interrupts: should contain HSMCI interrupt number
> > +- at least one slot node
> > +
> > +The node contains child nodes for each slot that the platform uses
> > +
> > +Example MCI node:
> > +
> > +mmc0: mmc at f0008000 {
> > +	compatible = "atmel,hsmci";
> > +	reg = <0xf0008000 0x600>;
> > +	interrupts = <12 4>;
> > +
> > +	[ child node definitions...]
> > +};
> > +
> > +2) slot nodes
> > +
> > +Optional properties:
> > +- bus-width: number of data lines connected to the controller
> > +- cd-gpios: specify GPIOs for card detection
> > +- cd-invert: invert the value of external card detect gpio line
> > +- wp-gpios: specify GPIOs for write protection
> > +
> > +Example slot node:
> > +
> > +slot at 0 {
> > +	bus-width = <4>;
> > +	cd-gpios = <&pioD 15 0>
> > +	cd-invert;
> > +};
> > +
> > +Example full MCI node:
> > +mmc0: mmc at f0008000 {
> > +	compatible = "atmel,hsmci";
> > +	reg = <0xf0008000 0x600>;
> > +	interrupts = <12 4>;
> > +	slot at 0 {
> > +		bus-width = <4>;
> > +		cd-gpios = <&pioD 15 0>
> > +		cd-invert;
> > +	};
> > +	slot at 1 {
> > +		bus-width = <4>;
> > +	};
> > +};

[...]

> > +static void __init
> > +atmci_get_of_slots(struct device *dev, struct mci_platform_data *pdata)
> > +{
> > +	struct device_node *np = dev->of_node;
> > +	struct device_node *cnp;
> > +	unsigned int slot_nb = 0;
> > +
> > +	if (!np)
> > +		return;
> > +
> > +	for_each_child_of_node(np, cnp) {
> > +		if (slot_nb > (ATMCI_MAX_NR_SLOTS-1)) {
> > +			dev_warn(dev, "can't have more than %d slots\n",
> > +			         ATMCI_MAX_NR_SLOTS);
> > +			break;
> > +		}
> > +		if (of_property_read_u32(cnp, "bus-width",
> > +		                         &pdata->slot[slot_nb].bus_width))
> > +			pdata->slot[slot_nb].bus_width = 1;
> > +
> > +		pdata->slot[slot_nb].detect_pin =
> > +			of_get_named_gpio(cnp, "cd-gpios", 0);
> > +
> > +		if (of_find_property(cnp, "cd-invert", NULL))
> > +			pdata->slot[slot_nb].detect_is_active_high = true;
> > +
> > +		pdata->slot[slot_nb].wp_pin =
> > +			of_get_named_gpio(cnp, "wp-gpios", 0);
> > +
> > +		slot_nb++;
> > +	}
> > +}

In fact this part of code is not correct. Each mci can have two slots: slot0
and slot1. If someone wants to use only slot1, I will fill only pdata->slot[0]
that is incorrect because later in the driver there is:

if (pdata->slot[0].bus_width) {
	ret = atmci_init_slot(host, &pdata->slot[0], 
			0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
	if (!ret)
		nr_slots++;
}
if (pdata->slot[1].bus_width) {
	ret = atmci_init_slot(host, &pdata->slot[1],
			1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
	if (!ret)
		nr_slots++;
}

So what is the best solution to solve this issue?

- Adding a property slot id? I would like to use only existing bindings hoping 
we can have a generic binding for mmc.

- Using aliases?
aliases {
	slot0 = &mmc-slot0;
}

mmc0: mmc at f0008000 {
	compatible = "atmel,hsmci";
	reg = <0xf0008000 0x600>;
	interrupts = <12 4>;              
	mmc-slot0: slot at 0 {
	};                                                                
	status = "disabled";
};

- Using reg property as an index?


Thanks for your help.

Regards

Ludovic


From arnd at arndb.de  Fri Mar 23 07:39:23 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 23 Mar 2012 11:39:23 +0000
Subject: [PATCH] SPEAr: Use CLKDEV_INIT for defining clk_lookups
In-Reply-To: <4F6C48DA.9080005@st.com>
References: <57103011de8747743f95eb41c8dc30c632d097a8.1332490263.git.viresh.kumar@st.com>
 <201203230848.52010.arnd@arndb.de> <4F6C48DA.9080005@st.com>
Message-ID: <201203231139.23574.arnd@arndb.de>

On Friday 23 March 2012, Viresh Kumar wrote:
> > If the second patch is actually required and nit just cosmetic,
> > please provide a description why that is so.
> 
> It is just an cosmetic one. I posted it, so stefan can work over
> it and i don't have to rework on it again. What's the preferred
> way of handling such stuff during merge window?

Best just send bug fixes for inclusion, but no other patches. You
can of course post any patches for review and discuss them on
the list, but I won't apply stuff for v3.5 before Linus has taken
the base v3.4 stuff.

	Arnd


From m.szyprowski at samsung.com  Fri Mar 23 08:12:16 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 23 Mar 2012 13:12:16 +0100
Subject: [PATCHv7 8/9] ARM: dma-mapping: use alloc, mmap, free from dma_ops
In-Reply-To: <4F6B2CDE.4020601@gmail.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-9-git-send-email-m.szyprowski@samsung.com>
 <4F6B2CDE.4020601@gmail.com>
Message-ID: <08af01cd08ee$2fd04770$8f70d650$%szyprowski@samsung.com>

Hello,

On Thursday, March 22, 2012 2:45 PM Subash Patel wrote:

> I have found out an issue with dma_mmap_writecombine() and coherent devices.
> 
> On 02/29/2012 08:34 PM, Marek Szyprowski wrote:
> > This patch converts dma_alloc/free/mmap_{coherent,writecombine}
> > functions to use generic alloc/free/mmap methods from dma_map_ops
> > structure. A new DMA_ATTR_WRITE_COMBINE DMA attribute have been
> > introduced to implement writecombine methods.
> >
> > Signed-off-by: Marek Szyprowski<m.szyprowski at samsung.com>
> > Signed-off-by: Kyungmin Park<kyungmin.park at samsung.com>
> > ---
> >   arch/arm/common/dmabounce.c        |    3 +
> >   arch/arm/include/asm/dma-mapping.h |  107 ++++++++++++++++++++++++++----------
> >   arch/arm/mm/dma-mapping.c          |   53 ++++++------------
> >   3 files changed, 98 insertions(+), 65 deletions(-)
> >
> > diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
> > index 119f487..dbae5ad 100644
> > --- a/arch/arm/common/dmabounce.c
> > +++ b/arch/arm/common/dmabounce.c
> > @@ -449,6 +449,9 @@ static int dmabounce_set_mask(struct device *dev, u64 dma_mask)
> >   }
> >
> >   static struct dma_map_ops dmabounce_ops = {
> > +	.alloc			= arm_dma_alloc,
> > +	.free			= arm_dma_free,
> > +	.mmap			= arm_dma_mmap,
> >   	.map_page		= dmabounce_map_page,
> >   	.unmap_page		= dmabounce_unmap_page,
> >   	.sync_single_for_cpu	= dmabounce_sync_for_cpu,
> > diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
> > index 266cba6..4342b75 100644
> > --- a/arch/arm/include/asm/dma-mapping.h
> > +++ b/arch/arm/include/asm/dma-mapping.h
> > @@ -5,6 +5,7 @@
> >
> >   #include<linux/mm_types.h>
> >   #include<linux/scatterlist.h>
> > +#include<linux/dma-attrs.h>
> >   #include<linux/dma-debug.h>
> >
> >   #include<asm-generic/dma-coherent.h>
> > @@ -110,68 +111,115 @@ static inline void dma_free_noncoherent(struct device *dev, size_t
> size,
> >   extern int dma_supported(struct device *dev, u64 mask);
> >
> >   /**
> > - * dma_alloc_coherent - allocate consistent memory for DMA
> > + * arm_dma_alloc - allocate consistent memory for DMA
> >    * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
> >    * @size: required memory size
> >    * @handle: bus-specific DMA address
> > + * @attrs: optinal attributes that specific mapping properties
> >    *
> > - * Allocate some uncached, unbuffered memory for a device for
> > - * performing DMA.  This function allocates pages, and will
> > - * return the CPU-viewed address, and sets @handle to be the
> > - * device-viewed address.
> > + * Allocate some memory for a device for performing DMA.  This function
> > + * allocates pages, and will return the CPU-viewed address, and sets @handle
> > + * to be the device-viewed address.
> >    */
> > -extern void *dma_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t);
> > +extern void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
> > +			   gfp_t gfp, struct dma_attrs *attrs);
> > +
> > +#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL)
> > +
> > +static inline void *dma_alloc_attrs(struct device *dev, size_t size,
> > +				       dma_addr_t *dma_handle, gfp_t flag,
> > +				       struct dma_attrs *attrs)
> > +{
> > +	struct dma_map_ops *ops = get_dma_ops(dev);
> > +	void *cpu_addr;
> > +	BUG_ON(!ops);
> > +
> > +	cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
> > +	debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
> > +	return cpu_addr;
> > +}
> >
> >   /**
> > - * dma_free_coherent - free memory allocated by dma_alloc_coherent
> > + * arm_dma_free - free memory allocated by arm_dma_alloc
> >    * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
> >    * @size: size of memory originally requested in dma_alloc_coherent
> >    * @cpu_addr: CPU-view address returned from dma_alloc_coherent
> >    * @handle: device-view address returned from dma_alloc_coherent
> > + * @attrs: optinal attributes that specific mapping properties
> >    *
> >    * Free (and unmap) a DMA buffer previously allocated by
> > - * dma_alloc_coherent().
> > + * arm_dma_alloc().
> >    *
> >    * References to memory and mappings associated with cpu_addr/handle
> >    * during and after this call executing are illegal.
> >    */
> > -extern void dma_free_coherent(struct device *, size_t, void *, dma_addr_t);
> > +extern void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
> > +			 dma_addr_t handle, struct dma_attrs *attrs);
> > +
> > +#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
> > +
> > +static inline void dma_free_attrs(struct device *dev, size_t size,
> > +				     void *cpu_addr, dma_addr_t dma_handle,
> > +				     struct dma_attrs *attrs)
> > +{
> > +	struct dma_map_ops *ops = get_dma_ops(dev);
> > +	BUG_ON(!ops);
> > +
> > +	debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
> > +	ops->free(dev, size, cpu_addr, dma_handle, attrs);
> > +}
> >
> >   /**
> > - * dma_mmap_coherent - map a coherent DMA allocation into user space
> > + * arm_dma_mmap - map a coherent DMA allocation into user space
> >    * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
> >    * @vma: vm_area_struct describing requested user mapping
> >    * @cpu_addr: kernel CPU-view address returned from dma_alloc_coherent
> >    * @handle: device-view address returned from dma_alloc_coherent
> >    * @size: size of memory originally requested in dma_alloc_coherent
> > + * @attrs: optinal attributes that specific mapping properties
> >    *
> >    * Map a coherent DMA buffer previously allocated by dma_alloc_coherent
> >    * into user space.  The coherent DMA buffer must not be freed by the
> >    * driver until the user space mapping has been released.
> >    */
> > -int dma_mmap_coherent(struct device *, struct vm_area_struct *,
> > -		void *, dma_addr_t, size_t);
> > +extern int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
> > +			void *cpu_addr, dma_addr_t dma_addr, size_t size,
> > +			struct dma_attrs *attrs);
> >
> > +#define dma_mmap_coherent(d,v,c,h,s) dma_mmap_attrs(d,v,c,h,s,NULL)
> >
> > -/**
> > - * dma_alloc_writecombine - allocate writecombining memory for DMA
> > - * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
> > - * @size: required memory size
> > - * @handle: bus-specific DMA address
> > - *
> > - * Allocate some uncached, buffered memory for a device for
> > - * performing DMA.  This function allocates pages, and will
> > - * return the CPU-viewed address, and sets @handle to be the
> > - * device-viewed address.
> > - */
> > -extern void *dma_alloc_writecombine(struct device *, size_t, dma_addr_t *,
> > -		gfp_t);
> > +static inline int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
> > +				  void *cpu_addr, dma_addr_t dma_addr,
> > +				  size_t size, struct dma_attrs *attrs)
> > +{
> > +	struct dma_map_ops *ops = get_dma_ops(dev);
> > +	BUG_ON(!ops);
> > +	return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
> > +}
> >
> > -#define dma_free_writecombine(dev,size,cpu_addr,handle) \
> > -	dma_free_coherent(dev,size,cpu_addr,handle)
> > +static inline void *dma_alloc_writecombine(struct device *dev, size_t size,
> > +				       dma_addr_t *dma_handle, gfp_t flag)
> > +{
> > +	DEFINE_DMA_ATTRS(attrs);
> > +	dma_set_attr(DMA_ATTR_WRITE_COMBINE,&attrs);
> > +	return dma_alloc_attrs(dev, size, dma_handle, flag,&attrs);
> > +}
> >
> > -int dma_mmap_writecombine(struct device *, struct vm_area_struct *,
> > -		void *, dma_addr_t, size_t);
> > +static inline void dma_free_writecombine(struct device *dev, size_t size,
> > +				     void *cpu_addr, dma_addr_t dma_handle)
> > +{
> > +	DEFINE_DMA_ATTRS(attrs);
> > +	dma_set_attr(DMA_ATTR_WRITE_COMBINE,&attrs);
> > +	return dma_free_attrs(dev, size, cpu_addr, dma_handle,&attrs);
> > +}
> > +
> > +static inline int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
> > +		      void *cpu_addr, dma_addr_t dma_addr, size_t size)
> > +{
> > +	DEFINE_DMA_ATTRS(attrs);
> > +	dma_set_attr(DMA_ATTR_WRITE_COMBINE,&attrs);
> > +	return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size,&attrs);
> > +}
> >
> For devices, which do not have a coherent/reserved pool, then the
> allocation in function __dma_alloc() happens, and the memory will be
> remapped by calling __dma_alloc_remap(). In the above function,
> arm_vmregion_find() will be called, and it succeeds to get the map and
> it will be mapped to used.
> 
> This has issues with devices with coherent memory. If we have any device
> which has declared coherent memory, then the allocation happens from
> per-device coherent area. Eg: Exynos MFC which declares:
> s5p_mfc_reserve_mem(). In that case, dma_mmap_writecombine() fails, and
> hence vb2_dc_mmap() fails as well.

Right, I missed that case. Now I prepared a fix, I will send the patches in a minute. 
Please check if it works for you.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From jean.pihet at newoldbits.com  Fri Mar 23 08:21:23 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Fri, 23 Mar 2012 13:21:23 +0100
Subject: [RFC][PATCH 2/9] ARM: OMAP3: cpuidle - remove next_valid_state
 function
In-Reply-To: <1332494794-7810-2-git-send-email-daniel.lezcano@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
 <1332494794-7810-2-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <CAORVsuVMSF-LEuGfkFWjm6QLv79RM4ewz4sZqNdWj66K55iB-w@mail.gmail.com>

Hi Daniel,

On Fri, Mar 23, 2012 at 10:26 AM, Daniel Lezcano
<daniel.lezcano at linaro.org> wrote:
> As we will be able to remove C-states from userspace with the sysfs
> API, this function is no longer needed. We remove it and that simplifies
> the code for more consolidation.
>
> Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> ---
> ?arch/arm/mach-omap2/cpuidle34xx.c | ? 85 +------------------------------------
> ?1 files changed, 2 insertions(+), 83 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
> index d67431a..65b4e7aa 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -164,84 +164,6 @@ return_sleep_time:
> ?}
>
> ?/**
> - * next_valid_state - Find next valid C-state
> - * @dev: cpuidle device
> - * @drv: cpuidle driver
> - * @index: Index of currently selected c-state
> - *
> - * If the state corresponding to index is valid, index is returned back
> - * to the caller. Else, this function searches for a lower c-state which is
> - * still valid (as defined in omap3_power_states[]) and returns its index.
> - *
> - * A state is valid if the 'valid' field is enabled and
> - * if it satisfies the enable_off_mode condition.
> - */
> -static int next_valid_state(struct cpuidle_device *dev,
> - ? ? ? ? ? ? ? ? ? ? ? struct cpuidle_driver *drv,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int index)
> -{
> - ? ? ? struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
> - ? ? ? struct cpuidle_state *curr = &drv->states[index];
> - ? ? ? struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
> - ? ? ? u32 mpu_deepest_state = PWRDM_POWER_RET;
> - ? ? ? u32 core_deepest_state = PWRDM_POWER_RET;
> - ? ? ? int next_index = -1;
> -
> - ? ? ? if (enable_off_mode) {
> - ? ? ? ? ? ? ? mpu_deepest_state = PWRDM_POWER_OFF;
> - ? ? ? ? ? ? ? /*
> - ? ? ? ? ? ? ? ?* Erratum i583: valable for ES rev < Es1.2 on 3630.
> - ? ? ? ? ? ? ? ?* CORE OFF mode is not supported in a stable form, restrict
> - ? ? ? ? ? ? ? ?* instead the CORE state to RET.
> - ? ? ? ? ? ? ? ?*/
> - ? ? ? ? ? ? ? if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
> - ? ? ? ? ? ? ? ? ? ? ? core_deepest_state = PWRDM_POWER_OFF;
> - ? ? ? }
I am OK to remove the function but some of the code needs to stay (can
be moved into enter_idle_bm).
The errata code is needed.

> -
> - ? ? ? /* Check if current state is valid */
> - ? ? ? if ((cx->valid) &&
> - ? ? ? ? ? (cx->mpu_state >= mpu_deepest_state) &&
> - ? ? ? ? ? (cx->core_state >= core_deepest_state)) {
> - ? ? ? ? ? ? ? return index;
> - ? ? ? } else {
> - ? ? ? ? ? ? ? int idx = OMAP3_NUM_STATES - 1;
On OMAP3 not all the power states combinations are allowed, so this
code looks for a C-state which satisfies the enable_off_mode flag.
I am planning to remove the enable_off_mode flag but this has to come
with the per-device PM QoS constraints code.

> -
> - ? ? ? ? ? ? ? /* Reach the current state starting at highest C-state */
> - ? ? ? ? ? ? ? for (; idx >= 0; idx--) {
> - ? ? ? ? ? ? ? ? ? ? ? if (&drv->states[idx] == curr) {
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? next_index = idx;
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break;
> - ? ? ? ? ? ? ? ? ? ? ? }
> - ? ? ? ? ? ? ? }
> -
> - ? ? ? ? ? ? ? /* Should never hit this condition */
> - ? ? ? ? ? ? ? WARN_ON(next_index == -1);
> -
> - ? ? ? ? ? ? ? /*
> - ? ? ? ? ? ? ? ?* Drop to next valid state.
> - ? ? ? ? ? ? ? ?* Start search from the next (lower) state.
> - ? ? ? ? ? ? ? ?*/
> - ? ? ? ? ? ? ? idx--;
> - ? ? ? ? ? ? ? for (; idx >= 0; idx--) {
> - ? ? ? ? ? ? ? ? ? ? ? cx = cpuidle_get_statedata(&dev->states_usage[idx]);
> - ? ? ? ? ? ? ? ? ? ? ? if ((cx->valid) &&
> - ? ? ? ? ? ? ? ? ? ? ? ? ? (cx->mpu_state >= mpu_deepest_state) &&
> - ? ? ? ? ? ? ? ? ? ? ? ? ? (cx->core_state >= core_deepest_state)) {
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? next_index = idx;
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break;
> - ? ? ? ? ? ? ? ? ? ? ? }
> - ? ? ? ? ? ? ? }
> - ? ? ? ? ? ? ? /*
> - ? ? ? ? ? ? ? ?* C1 is always valid.
> - ? ? ? ? ? ? ? ?* So, no need to check for 'next_index == -1' outside
> - ? ? ? ? ? ? ? ?* this loop.
> - ? ? ? ? ? ? ? ?*/
> - ? ? ? }
> -
> - ? ? ? return next_index;
> -}
> -
> -/**
> ?* omap3_enter_idle_bm - Checks for any bus activity
> ?* @dev: cpuidle device
> ?* @drv: cpuidle driver
> @@ -254,7 +176,6 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct cpuidle_driver *drv,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int index)
> ?{
> - ? ? ? int new_state_idx;
> ? ? ? ?u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
> ? ? ? ?struct omap3_idle_statedata *cx;
> ? ? ? ?int ret;
> @@ -265,7 +186,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
> ? ? ? ? */
> ? ? ? ?cam_state = pwrdm_read_pwrst(cam_pd);
> ? ? ? ?if (cam_state == PWRDM_POWER_ON) {
> - ? ? ? ? ? ? ? new_state_idx = drv->safe_state_index;
> + ? ? ? ? ? ? ? index = drv->safe_state_index;
> ? ? ? ? ? ? ? ?goto select_state;
> ? ? ? ?}
>
> @@ -292,10 +213,8 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
> ? ? ? ?if (per_next_state != per_saved_state)
> ? ? ? ? ? ? ? ?pwrdm_set_next_pwrst(per_pd, per_next_state);
>
> - ? ? ? new_state_idx = next_valid_state(dev, drv, index);
> -
> ?select_state:
> - ? ? ? ret = omap3_enter_idle(dev, drv, new_state_idx);
> + ? ? ? ret = omap3_enter_idle(dev, drv, index);
>
> ? ? ? ?/* Restore original PER state if it was modified */
> ? ? ? ?if (per_next_state != per_saved_state)
> --
> 1.7.5.4
>

Regards,
Jean


From jean.pihet at newoldbits.com  Fri Mar 23 08:22:32 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Fri, 23 Mar 2012 13:22:32 +0100
Subject: [RFC][PATCH 3/9] ARM: OMAP3: cpuidle - set enable_off_mode as
 static
In-Reply-To: <1332494794-7810-3-git-send-email-daniel.lezcano@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
 <1332494794-7810-3-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <CAORVsuVBC2TgVyt-PFWV878mXpM1GqETQnzdVi0ZYH-2x8D4nQ@mail.gmail.com>

On Fri, Mar 23, 2012 at 10:26 AM, Daniel Lezcano
<daniel.lezcano at linaro.org> wrote:
> This variable is only used in the pm-debug.c file.
>
> Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> ---
> ?arch/arm/mach-omap2/pm-debug.c | ? ?2 +-
> ?arch/arm/mach-omap2/pm.h ? ? ? | ? 30 ++++++++++++------------------
> ?2 files changed, 13 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
> index 814bcd9..86aa398 100644
> --- a/arch/arm/mach-omap2/pm-debug.c
> +++ b/arch/arm/mach-omap2/pm-debug.c
> @@ -38,7 +38,7 @@
> ?#include "prm2xxx_3xxx.h"
> ?#include "pm.h"
>
> -u32 enable_off_mode;
> +static u32 enable_off_mode;
It is stil needed in cpuidle34xx.c.

>
> ?#ifdef CONFIG_DEBUG_FS
> ?#include <linux/debugfs.h>
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index af73a86..f5c3072 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -25,6 +25,18 @@ extern int omap4_idle_init(void);
> ?extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
> ?extern int (*omap_pm_suspend)(void);
>
> +/*
> + * cpuidle mach specific parameters
> + *
> + * The board code can override the default C-states definition using
> + * omap3_pm_init_cpuidle
> + */
> +struct cpuidle_params {
> + ? ? ? u32 exit_latency; ? ? ? /* exit_latency = sleep + wake-up latencies */
> + ? ? ? u32 target_residency;
> + ? ? ? u8 valid; ? ? ? ? ? ? ? /* validates the C-state */
> +};
> +
Is this move needed? This will be removed in a later patch.

> ?#if defined(CONFIG_PM_OPP)
> ?extern int omap3_opp_init(void);
> ?extern int omap4_opp_init(void);
> @@ -39,27 +51,9 @@ static inline int omap4_opp_init(void)
> ?}
> ?#endif
>
> -/*
> - * cpuidle mach specific parameters
> - *
> - * The board code can override the default C-states definition using
> - * omap3_pm_init_cpuidle
> - */
> -struct cpuidle_params {
> - ? ? ? u32 exit_latency; ? ? ? /* exit_latency = sleep + wake-up latencies */
> - ? ? ? u32 target_residency;
> - ? ? ? u8 valid; ? ? ? ? ? ? ? /* validates the C-state */
> -};
> -
> ?extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
> ?extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
>
> -#ifdef CONFIG_PM_DEBUG
> -extern u32 enable_off_mode;
> -#else
> -#define enable_off_mode 0
> -#endif
> -
> ?#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
> ?extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
> ?#else
> --
> 1.7.5.4
>

Jean


From m.szyprowski at samsung.com  Fri Mar 23 08:26:02 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 23 Mar 2012 13:26:02 +0100
Subject: [PATCH 1/2] common: add dma_mmap_from_coherent() function
In-Reply-To: <1332505563-17646-1-git-send-email-m.szyprowski@samsung.com>
References: <08af01cd08ee$2fd04770$8f70d650$%szyprowski@samsung.com>
 <1332505563-17646-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332505563-17646-2-git-send-email-m.szyprowski@samsung.com>

Add a common helper for dma-mapping core for mapping a coherent buffer
to userspace.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 drivers/base/dma-coherent.c        |   42 ++++++++++++++++++++++++++++++++++++
 include/asm-generic/dma-coherent.h |    4 ++-
 2 files changed, 45 insertions(+), 1 deletions(-)

diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
index bb0025c..ef5ae05 100644
--- a/drivers/base/dma-coherent.c
+++ b/drivers/base/dma-coherent.c
@@ -10,6 +10,7 @@
 struct dma_coherent_mem {
 	void		*virt_base;
 	dma_addr_t	device_base;
+	phys_addr_t	pfn_base;
 	int		size;
 	int		flags;
 	unsigned long	*bitmap;
@@ -44,6 +45,7 @@ int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
 
 	dev->dma_mem->virt_base = mem_base;
 	dev->dma_mem->device_base = device_addr;
+	dev->dma_mem->pfn_base = PFN_DOWN(bus_addr);
 	dev->dma_mem->size = pages;
 	dev->dma_mem->flags = flags;
 
@@ -176,3 +178,43 @@ int dma_release_from_coherent(struct device *dev, int order, void *vaddr)
 	return 0;
 }
 EXPORT_SYMBOL(dma_release_from_coherent);
+
+/**
+ * dma_mmap_from_coherent() - try to mmap the memory allocated from 
+ * per-device coherent memory pool to userspace
+ * @dev:	device from which the memory was allocated
+ * @vma:	vm_area for the userspace memory
+ * @vaddr:	cpu address returned by dma_alloc_from_coherent
+ * @size:	size of the memory buffer allocated by dma_alloc_from_coherent
+ *
+ * This checks whether the memory was allocated from the per-device
+ * coherent memory pool and if so, maps that memory to the provided vma.
+ *
+ * Returns 1 if we correctly mapped the memory, or 0 if
+ * dma_release_coherent() should proceed with mapping memory from
+ * generic pools.
+ */
+int dma_mmap_from_coherent(struct device *dev, struct vm_area_struct *vma,
+			   void *vaddr, size_t size, int *ret)
+{
+	struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL;
+
+	if (mem && vaddr >= mem->virt_base && vaddr + size <=
+		   (mem->virt_base + (mem->size << PAGE_SHIFT))) {
+		unsigned long off = vma->vm_pgoff;
+		int start = (vaddr - mem->virt_base) >> PAGE_SHIFT;
+		int user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
+		int count = size >> PAGE_SHIFT;
+
+		*ret = -ENXIO;
+		if (off < count && user_count <= count - off) {
+			unsigned pfn = mem->pfn_base + start + off;
+			*ret = remap_pfn_range(vma, vma->vm_start, pfn,
+					       user_count << PAGE_SHIFT,
+					       vma->vm_page_prot);
+		}
+		return 1;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(dma_mmap_from_coherent);
diff --git a/include/asm-generic/dma-coherent.h b/include/asm-generic/dma-coherent.h
index 85a3ffa..b82051d 100644
--- a/include/asm-generic/dma-coherent.h
+++ b/include/asm-generic/dma-coherent.h
@@ -3,13 +3,15 @@
 
 #ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT
 /*
- * These two functions are only for dma allocator.
+ * These three functions are only for dma allocator.
  * Don't use them in device drivers.
  */
 int dma_alloc_from_coherent(struct device *dev, ssize_t size,
 				       dma_addr_t *dma_handle, void **ret);
 int dma_release_from_coherent(struct device *dev, int order, void *vaddr);
 
+int dma_mmap_from_coherent(struct device *dev, struct vm_area_struct *vma,
+                           void *cpu_addr, size_t size, int *ret);
 /*
  * Standard interface
  */
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Fri Mar 23 08:26:01 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 23 Mar 2012 13:26:01 +0100
Subject: [PATCH 0/2] ARM: dma-mapping: Fix mmap support for coherent buffers
In-Reply-To: <08af01cd08ee$2fd04770$8f70d650$%szyprowski@samsung.com>
References: <08af01cd08ee$2fd04770$8f70d650$%szyprowski@samsung.com>
Message-ID: <1332505563-17646-1-git-send-email-m.szyprowski@samsung.com>

Hello,

This patchset contains patches to fix broken mmap operation for memory
buffers allocated from 'dma_declare_coherent' pool after applying my dma
mapping redesign patches [1]. These issues have been reported by Subash
Patel.

[1] http://thread.gmane.org/gmane.linux.kernel.cross-arch/12819 

Patch summary:

Marek Szyprowski (2):
  common: add dma_mmap_from_coherent() function
  arm: dma-mapping: use dma_mmap_from_coherent()

 arch/arm/mm/dma-mapping.c          |    3 ++
 drivers/base/dma-coherent.c        |   42 ++++++++++++++++++++++++++++++++++++
 include/asm-generic/dma-coherent.h |    4 ++-
 3 files changed, 48 insertions(+), 1 deletions(-)

-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Fri Mar 23 08:26:03 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 23 Mar 2012 13:26:03 +0100
Subject: [PATCH 2/2] arm: dma-mapping: use dma_mmap_from_coherent()
In-Reply-To: <1332505563-17646-1-git-send-email-m.szyprowski@samsung.com>
References: <08af01cd08ee$2fd04770$8f70d650$%szyprowski@samsung.com>
 <1332505563-17646-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332505563-17646-3-git-send-email-m.szyprowski@samsung.com>

Use dma_mmap_from_coherent() to fix broken mapping of the coherent buffers
to userspace.

Reported-by: Subash Patel <subashrp at gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/mm/dma-mapping.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 6c24218..0cee054 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -511,6 +511,9 @@ int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
 			    pgprot_writecombine(vma->vm_page_prot) :
 			    pgprot_dmacoherent(vma->vm_page_prot);
 
+	if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
+		return ret;
+
 	c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
 	if (c) {
 		unsigned long off = vma->vm_pgoff;
-- 
1.7.1.569.g6f426



From jean.pihet at newoldbits.com  Fri Mar 23 08:35:12 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Fri, 23 Mar 2012 13:35:12 +0100
Subject: [RFC][PATCH 4/9] ARM: OMAP3: define cpuidle statically
In-Reply-To: <1332494794-7810-4-git-send-email-daniel.lezcano@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
 <1332494794-7810-4-git-send-email-daniel.lezcano@linaro.org>
Message-ID: <CAORVsuUZUWrwzx0hYT4YC0HhwAzTKF+q++LPvg43iy-iYbTivA@mail.gmail.com>

On Fri, Mar 23, 2012 at 10:26 AM, Daniel Lezcano
<daniel.lezcano at linaro.org> wrote:
> Use the new cpuidle API and define in the driver the states.
>
> Signed-off-by: Daniel Lezcano <daniel.lezcano at linaro.org>
> ---
> ?arch/arm/mach-omap2/cpuidle34xx.c | ? 85 +++++++++++++++++++++++++-----------
> ?1 files changed, 59 insertions(+), 26 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
> index 65b4e7aa..62e3cfd 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -228,23 +228,67 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
> ?struct cpuidle_driver omap3_idle_driver = {
> ? ? ? ?.name = ? ? ? ? "omap3_idle",
> ? ? ? ?.owner = ? ? ? ?THIS_MODULE,
> + ? ? ? .states = {
> + ? ? ? ? ? ? ? {
> + ? ? ? ? ? ? ? ? ? ? ? .enter ? ? ? ? ? ?= omap3_enter_idle,
> + ? ? ? ? ? ? ? ? ? ? ? .exit_latency ? ? = 2 + 2,
> + ? ? ? ? ? ? ? ? ? ? ? .target_residency = 5,
> + ? ? ? ? ? ? ? ? ? ? ? .flags ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID,
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? ? = "C1",
> + ? ? ? ? ? ? ? ? ? ? ? .desc ? ? ? ? ? ? = "MPU ON + CORE ON",
> + ? ? ? ? ? ? ? },
> + ? ? ? ? ? ? ? {
> + ? ? ? ? ? ? ? ? ? ? ? .enter ? ? ? ? ? ?= omap3_enter_idle_bm,
> + ? ? ? ? ? ? ? ? ? ? ? .exit_latency ? ? = 10 + 10,
> + ? ? ? ? ? ? ? ? ? ? ? .target_residency = 30,
> + ? ? ? ? ? ? ? ? ? ? ? .flags ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID,
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? ? = "C2",
> + ? ? ? ? ? ? ? ? ? ? ? .desc ? ? ? ? ? ? = "MPU ON + CORE ON",
> + ? ? ? ? ? ? ? },
> + ? ? ? ? ? ? ? {
> + ? ? ? ? ? ? ? ? ? ? ? .enter ? ? ? ? ? ?= omap3_enter_idle_bm,
> + ? ? ? ? ? ? ? ? ? ? ? .exit_latency ? ? = 50 + 50,
> + ? ? ? ? ? ? ? ? ? ? ? .target_residency = 300,
> + ? ? ? ? ? ? ? ? ? ? ? .flags ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID,
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? ? = "C3",
> + ? ? ? ? ? ? ? ? ? ? ? .desc ? ? ? ? ? ? = "MPU RET + CORE ON",
> + ? ? ? ? ? ? ? },
> + ? ? ? ? ? ? ? {
> + ? ? ? ? ? ? ? ? ? ? ? .enter ? ? ? ? ? ?= omap3_enter_idle_bm,
> + ? ? ? ? ? ? ? ? ? ? ? .exit_latency ? ? = 1500 + 1800,
> + ? ? ? ? ? ? ? ? ? ? ? .target_residency = 4000,
> + ? ? ? ? ? ? ? ? ? ? ? .flags ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID,
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? ? = "C4",
> + ? ? ? ? ? ? ? ? ? ? ? .desc ? ? ? ? ? ? = "MPU OFF + CORE ON",
> + ? ? ? ? ? ? ? },
> + ? ? ? ? ? ? ? {
> + ? ? ? ? ? ? ? ? ? ? ? .enter ? ? ? ? ? ?= omap3_enter_idle_bm,
> + ? ? ? ? ? ? ? ? ? ? ? .exit_latency ? ? = 2500 + 7500,
> + ? ? ? ? ? ? ? ? ? ? ? .target_residency = 12000,
> + ? ? ? ? ? ? ? ? ? ? ? .flags ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID,
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? ? = "C5",
> + ? ? ? ? ? ? ? ? ? ? ? .desc ? ? ? ? ? ? = "MPU RET + CORE RET",
> + ? ? ? ? ? ? ? },
> + ? ? ? ? ? ? ? {
> + ? ? ? ? ? ? ? ? ? ? ? .enter ? ? ? ? ? ?= omap3_enter_idle_bm,
> + ? ? ? ? ? ? ? ? ? ? ? .exit_latency ? ? = 3000 + 8500,
> + ? ? ? ? ? ? ? ? ? ? ? .target_residency = 15000,
> + ? ? ? ? ? ? ? ? ? ? ? .flags ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID,
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? ? = "C6",
> + ? ? ? ? ? ? ? ? ? ? ? .desc ? ? ? ? ? ? = "MPU OFF + CORE RET",
> + ? ? ? ? ? ? ? },
> + ? ? ? ? ? ? ? {
> + ? ? ? ? ? ? ? ? ? ? ? .enter ? ? ? ? ? ?= omap3_enter_idle_bm,
> + ? ? ? ? ? ? ? ? ? ? ? .exit_latency ? ? = 10000 + 30000,
> + ? ? ? ? ? ? ? ? ? ? ? .target_residency = 30000,
> + ? ? ? ? ? ? ? ? ? ? ? .flags ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID,
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? ? = "C7",
> + ? ? ? ? ? ? ? ? ? ? ? .desc ? ? ? ? ? ? = "MPU OFF + CORE OFF",
> + ? ? ? ? ? ? ? },
C7 is enabled depending on the errata i583, cf. below.

> + ? ? ? },
> + ? ? ? .state_count = OMAP3_NUM_STATES,
> ?};
>
> -/* Helper to fill the C-state common data*/
> -static inline void _fill_cstate(struct cpuidle_driver *drv,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int idx, const char *descr)
> -{
> - ? ? ? struct cpuidle_state *state = &drv->states[idx];
> -
> - ? ? ? state->exit_latency ? ? = cpuidle_params_table[idx].exit_latency;
> - ? ? ? state->target_residency = cpuidle_params_table[idx].target_residency;
> - ? ? ? state->flags ? ? ? ? ? ?= CPUIDLE_FLAG_TIME_VALID;
> - ? ? ? state->enter ? ? ? ? ? ?= omap3_enter_idle_bm;
> - ? ? ? sprintf(state->name, "C%d", idx + 1);
> - ? ? ? strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
> -
> -}
> -
> ?/* Helper to register the driver_data */
> ?static inline struct omap3_idle_statedata *_fill_cstate_usage(
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct cpuidle_device *dev,
> @@ -277,50 +321,40 @@ int __init omap3_idle_init(void)
> ? ? ? ?cam_pd = pwrdm_lookup("cam_pwrdm");
>
>
> - ? ? ? drv->safe_state_index = -1;
> ? ? ? ?dev = &per_cpu(omap3_idle_dev, smp_processor_id());
>
> ? ? ? ?/* C1 . MPU WFI + Core active */
> - ? ? ? _fill_cstate(drv, 0, "MPU ON + CORE ON");
> - ? ? ? (&drv->states[0])->enter = omap3_enter_idle;
> - ? ? ? drv->safe_state_index = 0;
Same minor remark about the safe_state_index as in the previous series.

> ? ? ? ?cx = _fill_cstate_usage(dev, 0);
> ? ? ? ?cx->valid = 1; ?/* C1 is always valid */
> ? ? ? ?cx->mpu_state = PWRDM_POWER_ON;
> ? ? ? ?cx->core_state = PWRDM_POWER_ON;
>
> ? ? ? ?/* C2 . MPU WFI + Core inactive */
> - ? ? ? _fill_cstate(drv, 1, "MPU ON + CORE ON");
> ? ? ? ?cx = _fill_cstate_usage(dev, 1);
> ? ? ? ?cx->mpu_state = PWRDM_POWER_ON;
> ? ? ? ?cx->core_state = PWRDM_POWER_ON;
>
> ? ? ? ?/* C3 . MPU CSWR + Core inactive */
> - ? ? ? _fill_cstate(drv, 2, "MPU RET + CORE ON");
> ? ? ? ?cx = _fill_cstate_usage(dev, 2);
> ? ? ? ?cx->mpu_state = PWRDM_POWER_RET;
> ? ? ? ?cx->core_state = PWRDM_POWER_ON;
>
> ? ? ? ?/* C4 . MPU OFF + Core inactive */
> - ? ? ? _fill_cstate(drv, 3, "MPU OFF + CORE ON");
> ? ? ? ?cx = _fill_cstate_usage(dev, 3);
> ? ? ? ?cx->mpu_state = PWRDM_POWER_OFF;
> ? ? ? ?cx->core_state = PWRDM_POWER_ON;
>
> ? ? ? ?/* C5 . MPU RET + Core RET */
> - ? ? ? _fill_cstate(drv, 4, "MPU RET + CORE RET");
> ? ? ? ?cx = _fill_cstate_usage(dev, 4);
> ? ? ? ?cx->mpu_state = PWRDM_POWER_RET;
> ? ? ? ?cx->core_state = PWRDM_POWER_RET;
>
> ? ? ? ?/* C6 . MPU OFF + Core RET */
> - ? ? ? _fill_cstate(drv, 5, "MPU OFF + CORE RET");
> ? ? ? ?cx = _fill_cstate_usage(dev, 5);
> ? ? ? ?cx->mpu_state = PWRDM_POWER_OFF;
> ? ? ? ?cx->core_state = PWRDM_POWER_RET;
>
> ? ? ? ?/* C7 . MPU OFF + Core OFF */
> - ? ? ? _fill_cstate(drv, 6, "MPU OFF + CORE OFF");
> ? ? ? ?cx = _fill_cstate_usage(dev, 6);
> ? ? ? ?/*
> ? ? ? ? * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
C7 is enabled only if the errata does not apply.
This causes a problem with the statically defined C-states and also
with the per C-state sysfs disable knob. A consistency check should be
performed before trying to enter a state.

> @@ -338,7 +372,6 @@ int __init omap3_idle_init(void)
> ? ? ? ?drv->state_count = OMAP3_NUM_STATES;
> ? ? ? ?cpuidle_register_driver(&omap3_idle_driver);
>
> - ? ? ? dev->state_count = OMAP3_NUM_STATES;
> ? ? ? ?if (cpuidle_register_device(dev)) {
> ? ? ? ? ? ? ? ?printk(KERN_ERR "%s: CPUidle register device failed\n",
> ? ? ? ? ? ? ? ? ? ? ? __func__);
> --
> 1.7.5.4
>

Thanks!
Jean


From daniel.lezcano at linaro.org  Fri Mar 23 08:38:10 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 23 Mar 2012 13:38:10 +0100
Subject: [RFC][PATCH 3/9] ARM: OMAP3: cpuidle - set enable_off_mode as
 static
In-Reply-To: <CAORVsuVBC2TgVyt-PFWV878mXpM1GqETQnzdVi0ZYH-2x8D4nQ@mail.gmail.com>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
 <1332494794-7810-3-git-send-email-daniel.lezcano@linaro.org>
 <CAORVsuVBC2TgVyt-PFWV878mXpM1GqETQnzdVi0ZYH-2x8D4nQ@mail.gmail.com>
Message-ID: <4F6C6EB2.70101@linaro.org>

On 03/23/2012 01:22 PM, Jean Pihet wrote:
> On Fri, Mar 23, 2012 at 10:26 AM, Daniel Lezcano
> <daniel.lezcano at linaro.org>  wrote:
>> This variable is only used in the pm-debug.c file.
>>
>> Signed-off-by: Daniel Lezcano<daniel.lezcano at linaro.org>
>> ---
>>   arch/arm/mach-omap2/pm-debug.c |    2 +-
>>   arch/arm/mach-omap2/pm.h       |   30 ++++++++++++------------------
>>   2 files changed, 13 insertions(+), 19 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
>> index 814bcd9..86aa398 100644
>> --- a/arch/arm/mach-omap2/pm-debug.c
>> +++ b/arch/arm/mach-omap2/pm-debug.c
>> @@ -38,7 +38,7 @@
>>   #include "prm2xxx_3xxx.h"
>>   #include "pm.h"
>>
>> -u32 enable_off_mode;
>> +static u32 enable_off_mode;
> It is stil needed in cpuidle34xx.c.

ok.

>>   #ifdef CONFIG_DEBUG_FS
>>   #include<linux/debugfs.h>
>> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
>> index af73a86..f5c3072 100644
>> --- a/arch/arm/mach-omap2/pm.h
>> +++ b/arch/arm/mach-omap2/pm.h
>> @@ -25,6 +25,18 @@ extern int omap4_idle_init(void);
>>   extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
>>   extern int (*omap_pm_suspend)(void);
>>
>> +/*
>> + * cpuidle mach specific parameters
>> + *
>> + * The board code can override the default C-states definition using
>> + * omap3_pm_init_cpuidle
>> + */
>> +struct cpuidle_params {
>> +       u32 exit_latency;       /* exit_latency = sleep + wake-up latencies */
>> +       u32 target_residency;
>> +       u8 valid;               /* validates the C-state */
>> +};
>> +
> Is this move needed? This will be removed in a later patch.

No, I think I did a bad manipulation.

>>   #if defined(CONFIG_PM_OPP)
>>   extern int omap3_opp_init(void);
>>   extern int omap4_opp_init(void);
>> @@ -39,27 +51,9 @@ static inline int omap4_opp_init(void)
>>   }
>>   #endif
>>
>> -/*
>> - * cpuidle mach specific parameters
>> - *
>> - * The board code can override the default C-states definition using
>> - * omap3_pm_init_cpuidle
>> - */
>> -struct cpuidle_params {
>> -       u32 exit_latency;       /* exit_latency = sleep + wake-up latencies */
>> -       u32 target_residency;
>> -       u8 valid;               /* validates the C-state */
>> -};
>> -
>>   extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
>>   extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
>>
>> -#ifdef CONFIG_PM_DEBUG
>> -extern u32 enable_off_mode;
>> -#else
>> -#define enable_off_mode 0
>> -#endif
>> -
>>   #if defined(CONFIG_PM_DEBUG)&&  defined(CONFIG_DEBUG_FS)
>>   extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
>>   #else
>> --
>> 1.7.5.4
>>
>
> Jean


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From robherring2 at gmail.com  Fri Mar 23 08:40:18 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 23 Mar 2012 07:40:18 -0500
Subject: [PATCH 1/2] ARM: VIC: Create common infrastructure for vic DT
 bindings
In-Reply-To: <4bfe7af3761f6f40506a2089fd67866015f6d7f3.1332488625.git.viresh.kumar@st.com>
References: <4bfe7af3761f6f40506a2089fd67866015f6d7f3.1332488625.git.viresh.kumar@st.com>
Message-ID: <4F6C6F32.10800@gmail.com>

On 03/23/2012 02:49 AM, Viresh Kumar wrote:
> Few platforms define there own struct of_device_id[] for vic pl19*. They don't
> do anything specific in init_irq() other than of_irq_init().
> 
> This patch creates this struct array in vic.c and make other platforms use it.
> 
> Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
> ---
>  arch/arm/common/vic.c               |   14 +++++++++++++-
>  arch/arm/include/asm/hardware/vic.h |    3 ++-
>  arch/arm/mach-picoxcell/common.c    |   12 +-----------
>  arch/arm/mach-spear6xx/spear6xx.c   |   12 +-----------
>  4 files changed, 17 insertions(+), 24 deletions(-)
> 

NAK

None of these platforms have gpio interrupts or any other board
interrupt controllers which need to be initialized early? I don't think
DT conversions are complete enough to tell.

We could do something like this, but there only needs to be a single
match list of all controllers and function. We should consolidate the
irqchips to drivers/irqchip first though. I have that action from Connect...

Rob

> diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
> index 7a66311..190813e 100644
> --- a/arch/arm/common/vic.c
> +++ b/arch/arm/common/vic.c
> @@ -398,7 +398,8 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
>  }
>  
>  #ifdef CONFIG_OF
> -int __init vic_of_init(struct device_node *node, struct device_node *parent)
> +static int __init vic_of_init(struct device_node *node, struct device_node
> +		*parent)
>  {
>  	void __iomem *regs;
>  	int irq_base;
> @@ -423,6 +424,17 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
>  
>  	return -EIO;
>  }
> +
> +static const struct of_device_id vic_of_match[] __initconst = {
> +	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
> +	{ .compatible = "arm,pl192-vic", .data = vic_of_init, },
> +	{ /* Sentinel */ }
> +};
> +
> +void __init vic_init_irq(void)
> +{
> +	of_irq_init(vic_of_match);
> +}
>  #endif /* CONFIG OF */
>  
>  /*
> diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
> index e14af1a..02056a8 100644
> --- a/arch/arm/include/asm/hardware/vic.h
> +++ b/arch/arm/include/asm/hardware/vic.h
> @@ -42,6 +42,7 @@
>  
>  #ifndef __ASSEMBLY__
>  #include <linux/compiler.h>
> +#include <linux/init.h>
>  #include <linux/types.h>
>  
>  struct device_node;
> @@ -50,7 +51,7 @@ struct pt_regs;
>  void __vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources,
>  		u32 resume_sources, struct device_node *node);
>  void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
> -int vic_of_init(struct device_node *node, struct device_node *parent);
> +void __init vic_init_irq(void);
>  void vic_handle_irq(struct pt_regs *regs);
>  
>  #endif /* __ASSEMBLY__ */
> diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
> index a2e8ae8..fa0d7e9 100644
> --- a/arch/arm/mach-picoxcell/common.c
> +++ b/arch/arm/mach-picoxcell/common.c
> @@ -68,16 +68,6 @@ static const char *picoxcell_dt_match[] = {
>  	NULL
>  };
>  
> -static const struct of_device_id vic_of_match[] __initconst = {
> -	{ .compatible = "arm,pl192-vic", .data = vic_of_init, },
> -	{ /* Sentinel */ }
> -};
> -
> -static void __init picoxcell_init_irq(void)
> -{
> -	of_irq_init(vic_of_match);
> -}
> -
>  static void picoxcell_wdt_restart(char mode, const char *cmd)
>  {
>  	/*
> @@ -95,7 +85,7 @@ static void picoxcell_wdt_restart(char mode, const char *cmd)
>  DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
>  	.map_io		= picoxcell_map_io,
>  	.nr_irqs	= NR_IRQS_LEGACY,
> -	.init_irq	= picoxcell_init_irq,
> +	.init_irq	= vic_init_irq,
>  	.handle_irq	= vic_handle_irq,
>  	.timer		= &picoxcell_timer,
>  	.init_machine	= picoxcell_init_machine,
> diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
> index 2ed8b14..d436118 100644
> --- a/arch/arm/mach-spear6xx/spear6xx.c
> +++ b/arch/arm/mach-spear6xx/spear6xx.c
> @@ -102,19 +102,9 @@ static const char *spear600_dt_board_compat[] = {
>  	NULL
>  };
>  
> -static const struct of_device_id vic_of_match[] __initconst = {
> -	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
> -	{ /* Sentinel */ }
> -};
> -
> -static void __init spear6xx_dt_init_irq(void)
> -{
> -	of_irq_init(vic_of_match);
> -}
> -
>  DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
>  	.map_io		=	spear6xx_map_io,
> -	.init_irq	=	spear6xx_dt_init_irq,
> +	.init_irq	=	vic_init_irq,
>  	.handle_irq	=	vic_handle_irq,
>  	.timer		=	&spear6xx_timer,
>  	.init_machine	=	spear600_dt_init,



From daniel.lezcano at linaro.org  Fri Mar 23 08:41:48 2012
From: daniel.lezcano at linaro.org (Daniel Lezcano)
Date: Fri, 23 Mar 2012 13:41:48 +0100
Subject: [RFC][PATCH 4/9] ARM: OMAP3: define cpuidle statically
In-Reply-To: <CAORVsuUZUWrwzx0hYT4YC0HhwAzTKF+q++LPvg43iy-iYbTivA@mail.gmail.com>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
 <1332494794-7810-4-git-send-email-daniel.lezcano@linaro.org>
 <CAORVsuUZUWrwzx0hYT4YC0HhwAzTKF+q++LPvg43iy-iYbTivA@mail.gmail.com>
Message-ID: <4F6C6F8C.8010307@linaro.org>

On 03/23/2012 01:35 PM, Jean Pihet wrote:
> On Fri, Mar 23, 2012 at 10:26 AM, Daniel Lezcano
> <daniel.lezcano at linaro.org>  wrote:
>> Use the new cpuidle API and define in the driver the states.
>>
>> Signed-off-by: Daniel Lezcano<daniel.lezcano at linaro.org>
>> ---

[ ... ]

>>         /*
>>          * Erratum i583: implementation for ES rev<  Es1.2 on 3630. We cannot
> C7 is enabled only if the errata does not apply.
> This causes a problem with the statically defined C-states and also
> with the per C-state sysfs disable knob. A consistency check should be
> performed before trying to enter a state.

In the patch 5/9, I decrement the state_count if the errata applies. I 
believe it is still compatible with the static C-states.

>> @@ -338,7 +372,6 @@ int __init omap3_idle_init(void)
>>         drv->state_count = OMAP3_NUM_STATES;
>>         cpuidle_register_driver(&omap3_idle_driver);
>>
>> -       dev->state_count = OMAP3_NUM_STATES;
>>         if (cpuidle_register_device(dev)) {
>>                 printk(KERN_ERR "%s: CPUidle register device failed\n",
>>                        __func__);
>> --
>> 1.7.5.4
>>
>
> Thanks!
> Jean


-- 
  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog



From external.Peter.Waechtler at de.bosch.com  Fri Mar 23 09:15:44 2012
From: external.Peter.Waechtler at de.bosch.com (EXTERNAL Waechtler Peter (Fa. TCP, CM-AI/PJ-CF31))
Date: Fri, 23 Mar 2012 14:15:44 +0100
Subject: [PATCH] mm: overwrite __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
Message-ID: <274124B9C6907D4B8CE985903EAA19E91B2D579456@SI-MBX06.de.bosch.com>

On ARM at least upto ARMv6 the accessed bit (YOUNG/OLD) are not
supported in hardware - they solely live in the Linux software
shadow page table.

There is no need to flush the TLB if only the young bit gets
cleared by kswapd.

There is a nasty deadlock because tlb_ops_need_broadcast() is set
and the page fault handler "double faults" resulting in IRQs turned
off.

If the kswapd decides to clear the young bit on one cpu and a
page fault is entered on the other cpu a deadlock can happen:

see
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/091116.html

Signed-off-by: Peter Waechtler <external.peter.waechtler at de.bosch.com>
---
 arch/arm/include/asm/pgtable.h |   26 ++++++++++++++++++++++++++
 1 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 1122d93..5e5d4e9 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -469,6 +469,32 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 /* FIXME: this is not correct */
 #define kern_addr_valid(addr)  (1)

+#if __LINUX_ARM_ARCH__ <= 6
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+#define ptep_test_and_clear_young(__vma, __address, __ptep)            \
+({                                                                     \
+       pte_t __pte = *(__ptep);                                        \
+       int r = 1;                                                      \
+       if (!pte_young(__pte))                                          \
+               r = 0;                                                  \
+       else                                                            \
+               set_pte_at((__vma)->vm_mm, (__address),                 \
+                          (__ptep), pte_mkold(__pte));                 \
+       r;                                                              \
+})
+
+
+#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
+static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
+               unsigned long address, pte_t *ptep)
+{
+       /* No need to flush TLB
+        * On armv6 reference bits are never in TLB
+        */
+       return ptep_test_and_clear_young(vma, address, ptep);
+}
+#endif /* __LINUX_ARM_ARCH__ <= 6 */
+
 #include <asm-generic/pgtable.h>

 /*
--
1.6.0.4



From jean.pihet at newoldbits.com  Fri Mar 23 09:17:13 2012
From: jean.pihet at newoldbits.com (Jean Pihet)
Date: Fri, 23 Mar 2012 14:17:13 +0100
Subject: [RFC][PATCH 4/9] ARM: OMAP3: define cpuidle statically
In-Reply-To: <4F6C6F8C.8010307@linaro.org>
References: <1332494794-7810-1-git-send-email-daniel.lezcano@linaro.org>
 <1332494794-7810-4-git-send-email-daniel.lezcano@linaro.org>
 <CAORVsuUZUWrwzx0hYT4YC0HhwAzTKF+q++LPvg43iy-iYbTivA@mail.gmail.com>
 <4F6C6F8C.8010307@linaro.org>
Message-ID: <CAORVsuX0CXjfJkeGyS8LHNsAuTf3yP8Qtqr-G7sm17J83_L1VA@mail.gmail.com>

On Fri, Mar 23, 2012 at 1:41 PM, Daniel Lezcano
<daniel.lezcano at linaro.org> wrote:
> On 03/23/2012 01:35 PM, Jean Pihet wrote:
>>
>> On Fri, Mar 23, 2012 at 10:26 AM, Daniel Lezcano
>> <daniel.lezcano at linaro.org> ?wrote:
>>>
>>> Use the new cpuidle API and define in the driver the states.
>>>
>>> Signed-off-by: Daniel Lezcano<daniel.lezcano at linaro.org>
>>> ---
>
>
> [ ... ]
>
>
>>> ? ? ? ?/*
>>> ? ? ? ? * Erratum i583: implementation for ES rev< ?Es1.2 on 3630. We
>>> cannot
>>
>> C7 is enabled only if the errata does not apply.
>> This causes a problem with the statically defined C-states and also
>> with the per C-state sysfs disable knob. A consistency check should be
>> performed before trying to enter a state.
>
>
> In the patch 5/9, I decrement the state_count if the errata applies. I
> believe it is still compatible with the static C-states.
Correct! That solves the issue with the statically defined C-states.
The (dynamic) per C-state sysfs disable knob requires a runtime check
on .disable though, in case the cpuidle chosen C-state is demoted
(depending on the value of enable_off_mode and later the latency
constraints on the power domain).

>
>
>>> @@ -338,7 +372,6 @@ int __init omap3_idle_init(void)
>>> ? ? ? ?drv->state_count = OMAP3_NUM_STATES;
>>> ? ? ? ?cpuidle_register_driver(&omap3_idle_driver);
>>>
>>> - ? ? ? dev->state_count = OMAP3_NUM_STATES;
>>> ? ? ? ?if (cpuidle_register_device(dev)) {
>>> ? ? ? ? ? ? ? ?printk(KERN_ERR "%s: CPUidle register device failed\n",
>>> ? ? ? ? ? ? ? ? ? ? ? __func__);
>>> --
>>> 1.7.5.4
>>>
>>
Thanks!
Jean

>
>
>
> --
> ?<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
>
> Follow Linaro: ?<http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter |
> <http://www.linaro.org/linaro-blog/> Blog
>


From jonsmirl at gmail.com  Fri Mar 23 09:25:30 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Fri, 23 Mar 2012 09:25:30 -0400
Subject: ioremap to a specific virtual address
In-Reply-To: <alpine.LFD.2.02.1203230023060.24151@xanadu.home>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <alpine.LFD.2.02.1203222348210.24151@xanadu.home>
 <CAKON4OxjX94js19KqMx3W_hvqj8VwacAwFLMQF_BahME4XH-3A@mail.gmail.com>
 <alpine.LFD.2.02.1203230023060.24151@xanadu.home>
Message-ID: <CAKON4Ox6sp5YMryr2jzOAqYNmJG9RyahLTusrHZ_jcNQ40DAfQ@mail.gmail.com>

On Fri, Mar 23, 2012 at 12:28 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Fri, 23 Mar 2012, jonsmirl at gmail.com wrote:
>
>> On Fri, Mar 23, 2012 at 12:00 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
>> > On Thu, 22 Mar 2012, jonsmirl at gmail.com wrote:
>> >
>> >> When iotable is used to initially map memory you can specify the
>> >> mapping address. In this case IO_SDMMC_PHYS is 0x18000000 and it gets
>> >> mapped to ?0xf1800000
>> >>
>> >> NXP has supplied this handly macro
>> >> #define io_p2v(x) (0xf0000000 | (((x) & 0xff000000) >> 4) | ((x) & 0x000fffff))
>> >>
>> >> iotable_init(lpc313x_io_desc, ARRAY_SIZE(lpc313x_io_desc));
>> >>
>> >> ? ? ? {
>> >> ? ? ? ? ? ? ? .virtual ? ? ? ?= io_p2v(IO_SDMMC_PHYS),
>> >> ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(IO_SDMMC_PHYS),
>> >> ? ? ? ? ? ? ? .length ? ? ? ? = IO_SDMMC_SIZE,
>> >> ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE
>> >> ? ? ? },
>> >>
>> >> The supplied kernel is full of code that uses this type of addressing.
>> >> It has macros for register definition that all depend on the registers
>> >> being mapped to a well know location - io_p2v(x).
>> >>
>> >> I'd like to move the map out of the core code and into the SDMMC
>> >> device driver and then only do it if the driver loads.
>> >
>> > Why would you do that? ?Those static mappings are meant to be global and
>> > remain there. ?The handy macro is in fact not handy at all as it forces
>> > virtual addresses on you.
>>
>> I'm ok with global static mappings. What I'd like to do is build the
>> static iotable from the device tree instead of repeating every device
>> in the map_desc array. I suppose I could dynamically allocate it, fill
>> it in from the device tree and call iotable_init().
>
> Well, if you have a device tree with that stuff, then you may as well
> just forget about the static mappings.
>
>> What is the right way to make the initial static mappings?
>
> Typically by declaring it in the code. ?Otherwise there is some
> infrastructure already in place for drivers to map their hardware
> dynamically from DT information.

So there are two ways to build these mappings..

1) At init time. I can extract the 11 regions, dynamically build a
'struct map_desc' and call iotable_init. Doing it at init time via the
device tree will work, but it is complicated by the existence of nodes
in the device tree that have their status set to disabled. The init
time code will need to sort this out which duplicates what the driver
load system does.

2) Driver load time. This is why I asked the initial question about
how to do ioremap to the specific virtual address. I didn't want to
rewrite all of the existing code to use the more normal style of
mapping. So is there some way to create the static mapping at a
specific address when the driver first loads?

Is there any real advantage to doing the mapping at init time other
than being able to control which virtual address you get?

I can start looking at how much code needs to be converted to the base
+ offset model. One advantage to converting is that I'll get an
immediate GPF each time I mess up. Converting the code will let it
work with the random address from ioremap.

This is a NXP BSP for the lpc31xx from about three years ago. I've
forward ported it up to v3.3 and I want to get device tree going in
it. We have products based on this chip and I'd like to be able to
build a single kernel that works in all of the various configurations.






-- 
Jon Smirl
jonsmirl at gmail.com


From arnd at arndb.de  Fri Mar 23 10:07:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 23 Mar 2012 14:07:00 +0000
Subject: ioremap to a specific virtual address
In-Reply-To: <CAKON4Ox6sp5YMryr2jzOAqYNmJG9RyahLTusrHZ_jcNQ40DAfQ@mail.gmail.com>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <alpine.LFD.2.02.1203230023060.24151@xanadu.home>
 <CAKON4Ox6sp5YMryr2jzOAqYNmJG9RyahLTusrHZ_jcNQ40DAfQ@mail.gmail.com>
Message-ID: <201203231407.00686.arnd@arndb.de>

On Friday 23 March 2012, jonsmirl at gmail.com wrote:
> So there are two ways to build these mappings..
> 
> 1) At init time. I can extract the 11 regions, dynamically build a
> 'struct map_desc' and call iotable_init. Doing it at init time via the
> device tree will work, but it is complicated by the existence of nodes
> in the device tree that have their status set to disabled. The init
> time code will need to sort this out which duplicates what the driver
> load system does.

There is nothing wrong with setting up the static mappings at boot
time for all devices, you don't need to check whether they are actually
present. I would assume that you have plenty of virtual address space
on lpc31xx, given that those machines tend to come with rather little
physical memory.

> 2) Driver load time. This is why I asked the initial question about
> how to do ioremap to the specific virtual address. I didn't want to
> rewrite all of the existing code to use the more normal style of
> mapping. So is there some way to create the static mapping at a
> specific address when the driver first loads?
> 
> Is there any real advantage to doing the mapping at init time other
> than being able to control which virtual address you get?

The main reason why we do it in a lot of drivers is to allow the
drivers to be used across multiple platforms that have the devices
at a different location. We will soon (for some definition of that
term) have multiplatform kernels that can run e.g. on lpc31xx and
lpc32xx, and those two families can have the same devices at a different
memory location, or could have a different number of devices of
the same kind.

In particular, in order to enable the multiplatform kernel, we have
to restrict access of device drivers to platform specific header file
in all cases where those have conflicting contents.

> I can start looking at how much code needs to be converted to the base
> + offset model. One advantage to converting is that I'll get an
> immediate GPF each time I mess up. Converting the code will let it
> work with the random address from ioremap.
> 
> This is a NXP BSP for the lpc31xx from about three years ago. I've
> forward ported it up to v3.3 and I want to get device tree going in
> it. We have products based on this chip and I'd like to be able to
> build a single kernel that works in all of the various configurations.

I think you should work together with Roland Stigge, who is currently
looking into doing the same for lpc32xx. My guess is that you can save
a lot of work by combining your efforts, while you would get conflicting
DT bindings if you don't. Note that Roland has done a lot of patches
already for nxp device drivers that will be part of v3.4. He has not yet
started on DT patches but wants to work on that for v3.5.

	Arnd


From b29396 at freescale.com  Fri Mar 23 10:31:10 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Fri, 23 Mar 2012 22:31:10 +0800
Subject: [PATCH v2 1/1] ARM: imx28: add basic dt support
Message-ID: <1332513070-5400-1-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

This patch includes basic dt support which can boot via nfs rootfs.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog v1->v2:
 * Some fixes addressed Rob's review comments.
   Remove using of OF_DEV_AUXDATA.
 * Remove mac address from dts file
   Currently we use the mac address got from uboot to work.
   Will submit a p separate atch using prom_update_property to fix this
   issue for driver based on suggestions from Grant and Lothar.
 * rename mxs-dt.c to mach-mxs.c which is supposed to support mx23 dt
   too in the future.
 * add compatible string "fsl,imx28" per Sascha's suggestion
 * add more devices in dtsi file
   For those devices still not in use, set the state to "disabled"
   by default.

For other patches i sent with this in the first series like mmc and sdma
dt support, i will send out them separately since this patch does not depend
on them and does not block you to run dt via nfs rootfs.
---
 Documentation/devicetree/bindings/arm/fsl.txt |    4 +
 arch/arm/boot/dts/imx28-evk.dts               |   35 +++
 arch/arm/boot/dts/imx28.dtsi                  |  358 +++++++++++++++++++++++++
 arch/arm/mach-mxs/Kconfig                     |    8 +
 arch/arm/mach-mxs/Makefile                    |    1 +
 arch/arm/mach-mxs/clock-mx28.c                |    4 +
 arch/arm/mach-mxs/mach-mxs.c                  |   69 +++++
 7 files changed, 479 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx28-evk.dts
 create mode 100644 arch/arm/boot/dts/imx28.dtsi
 create mode 100644 arch/arm/mach-mxs/mach-mxs.c

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 54bddda..9f21faf 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -1,6 +1,10 @@
 Freescale i.MX Platforms Device Tree Bindings
 -----------------------------------------------
 
+i.MX28 Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx28-evk", "fsl,imx28";
+
 i.MX51 Babbage Board
 Required root node properties:
     - compatible = "fsl,imx51-babbage", "fsl,imx51";
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
new file mode 100644
index 0000000..5402495
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+	model = "Freescale i.MX28 Evaluation Kit";
+	compatible = "fsl,imx28-evk", "fsl,imx28";
+
+	memory {
+		device_type = "memory";
+		reg = <0x40000000 0x08000000>;
+	};
+
+	ahb at 80080000 {
+		ethernet at 800f0000 {
+			phy-mode = "rmii";
+			status = "okay";
+		};
+
+		ethernet at 800f4000 {
+			phy-mode = "rmii";
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
new file mode 100644
index 0000000..9152354
--- /dev/null
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -0,0 +1,358 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&icoll>;
+
+	aliases {
+		serial0 = &duart;
+	};
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	apb at 80000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80000000 0x80000>;
+		ranges;
+
+		apbh at 80000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x80000000 0x3c900>;
+			ranges;
+
+			icoll: interrupt-controller at 80000000 {
+				compatible = "fsl,imx28-icoll";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x80000000 0x2000>;
+			};
+
+			hsadc at 80002000 {
+				reg = <0x80002000 2000>;
+				interrupts = <13 87>;
+				status = "disabled";
+			};
+
+			dma-apbh at 80004000 {
+				reg = <0x80004000 2000>;
+				status = "disabled";
+			};
+
+			perfmon at 80006000 {
+				reg = <0x80006000 800>;
+				interrupts = <27>;
+				status = "disabled";
+			};
+
+			bch at 8000a000 {
+				reg = <0x8000a000 2000>;
+				interrupts = <41>;
+				status = "disabled";
+			};
+
+			gpmi at 8000c000 {
+				reg = <0x8000c000 2000>;
+				interrupts = <42 88>;
+				status = "disabled";
+			};
+
+			ssp at 80010000 {
+				reg = <0x80010000 2000>;
+				interrupts = <96 82>;
+				status = "disabled";
+			};
+
+			ssp at 80012000 {
+				reg = <0x80012000 2000>;
+				interrupts = <97 83>;
+				status = "disabled";
+			};
+
+			ssp at 80014000 {
+				reg = <0x80014000 2000>;
+				interrupts = <98 84>;
+				status = "disabled";
+			};
+
+			ssp at 80016000 {
+				reg = <0x80016000 2000>;
+				interrupts = <99 85>;
+				status = "disabled";
+			};
+
+			pinctrl at 80018000 {
+				reg = <0x80018000 2000>;
+				status = "disabled";
+			};
+
+			digctl at 8001c000 {
+				reg = <0x8001c000 2000>;
+				interrupts = <89>;
+				status = "disabled";
+			};
+
+			etm at 80022000 {
+				reg = <0x80022000 2000>;
+				status = "disabled";
+			};
+
+			dma-apbx at 80024000 {
+				reg = <0x80024000 2000>;
+				status = "disabled";
+			};
+
+			dcp at 80028000 {
+				reg = <0x80028000 2000>;
+				interrupts = <52 53 54>;
+				status = "disabled";
+			};
+
+			pxp at 8002a000 {
+				reg = <0x8002a000 2000>;
+				interrupts = <39>;
+				status = "disabled";
+			};
+
+			ocotp at 8002c000 {
+				reg = <0x8002c000 2000>;
+				status = "disabled";
+			};
+
+			axi-ahb at 8002e000 {
+				reg = <0x8002e000 2000>;
+				status = "disabled";
+			};
+
+			lcdif at 80030000 {
+				reg = <0x80030000 2000>;
+				interrupts = <38 86>;
+				status = "disabled";
+			};
+
+			can at 80032000 {
+				reg = <0x80032000 2000>;
+				interrupts = <8>;
+				status = "disabled";
+			};
+
+			can at 80034000 {
+				reg = <0x80034000 2000>;
+				interrupts = <9>;
+				status = "disabled";
+			};
+
+			simdbg at 8003c000 {
+				reg = <0x8003c000 200>;
+				status = "disabled";
+			};
+
+			simgpmisel at 8003c200 {
+				reg = <0x8003c200 100>;
+				status = "disabled";
+			};
+
+			simsspsel at 8003c300 {
+				reg = <0x8003c300 100>;
+				status = "disabled";
+			};
+
+			simmemsel at 8003c400 {
+				reg = <0x8003c400 100>;
+				status = "disabled";
+			};
+
+			gpiomon at 8003c500 {
+				reg = <0x8003c500 100>;
+				status = "disabled";
+			};
+
+			simenet at 8003c700 {
+				reg = <0x8003c700 100>;
+				status = "disabled";
+			};
+
+			armjtag at 8003c800 {
+				reg = <0x8003c800 100>;
+				status = "disabled";
+			};
+                };
+
+		apbx at 80040000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x80040000 0x40000>;
+			ranges;
+
+			clkctl at 80040000 {
+				reg = <0x80040000 2000>;
+				status = "disabled";
+			};
+
+			saif at 80042000 {
+				reg = <0x80042000 2000>;
+				interrupts = <59 80>;
+				status = "disabled";
+			};
+
+			power at 80044000 {
+				reg = <0x80044000 2000>;
+				status = "disabled";
+			};
+
+			saif at 80046000 {
+				reg = <0x80046000 2000>;
+				interrupts = <58 81>;
+				status = "disabled";
+			};
+
+			lradc at 80050000 {
+				reg = <0x80050000 2000>;
+				status = "disabled";
+			};
+
+			spdif at 80054000 {
+				reg = <0x80054000 2000>;
+				interrupts = <45 66>;
+				status = "disabled";
+			};
+
+			rtc at 80056000 {
+				reg = <0x80056000 2000>;
+				interrupts = <28 29>;
+				status = "disabled";
+			};
+
+			i2c at 80058000 {
+				reg = <0x80058000 2000>;
+				interrupts = <111 68>;
+				status = "disabled";
+			};
+
+			i2c at 8005a000 {
+				reg = <0x8005a000 2000>;
+				interrupts = <110 69>;
+				status = "disabled";
+			};
+
+			pwm at 80064000 {
+				reg = <0x80064000 2000>;
+				status = "disabled";
+			};
+
+			timrot at 80068000 {
+				reg = <0x80068000 2000>;
+				status = "disabled";
+			};
+
+			serial at 8006a000 {
+				reg = <0x8006a000 0x2000>;
+				interrupts = <112 70 71>;
+				status = "disabled";
+			};
+
+			serial at 8006c000 {
+				reg = <0x8006c000 0x2000>;
+				interrupts = <113 72 73>;
+				status = "disabled";
+			};
+
+			serial at 8006e000 {
+				reg = <0x8006e000 0x2000>;
+				interrupts = <114 74 75>;
+				status = "disabled";
+			};
+
+			serial at 80070000 {
+				reg = <0x80070000 0x2000>;
+				interrupts = <115 76 77>;
+				status = "disabled";
+			};
+
+			serial at 80072000 {
+				reg = <0x80072000 0x2000>;
+				interrupts = <116 78 79>;
+				status = "disabled";
+			};
+
+			duart: serial at 80074000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x80074000 0x1000>;
+				interrupts = <47>;
+			};
+
+			usbphy at 8007c000 {
+				reg = <0x8007c000 0x2000>;
+				status = "disabled";
+			};
+
+			usbphy at 8007e000 {
+				reg = <0x8007e000 0x2000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	ahb at 80080000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80080000 0x80000>;
+		ranges;
+
+		usbctrl at 80080000 {
+			reg = <0x80080000 0x10000>;
+			status = "disabled";
+		};
+
+		usbctrl at 80090000 {
+			reg = <0x80090000 0x10000>;
+			status = "disabled";
+		};
+
+		dflpt at 800c0000 {
+			reg = <0x800c0000 0x10000>;
+			status = "disabled";
+		};
+
+		ethernet at 800f0000 {
+			compatible = "fsl,imx28-fec";
+			reg = <0x800f0000 0x4000>;
+			interrupts = <101>;
+			status = "disabled";
+		};
+
+		ethernet at 800f4000 {
+			compatible = "fsl,imx28-fec";
+			reg = <0x800f4000 0x4000>;
+			interrupts = <102>;
+			status = "disabled";
+		};
+
+		switch at 800f8000 {
+			reg = <0x800f8000 0x8000>;
+			status = "disabled";
+		};
+
+	};
+};
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c57f996..c776aef 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -17,6 +17,14 @@ config SOC_IMX28
 
 comment "MXS platforms:"
 
+config MACH_MXS_DT
+	bool "Support MXS platforms from device tree"
+	select SOC_IMX28
+	select USE_OF
+	help
+	  Include support for Freescale MXS platforms(i.MX23 and i.MX28)
+	  using the device tree for discovery
+
 config MACH_STMP378X_DEVB
 	bool "Support STMP378x_devb Platform"
 	select SOC_IMX23
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 908bf9a..8328c45 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
 obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
 obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
 
+obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
 obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5d68e41..88ed30c 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -671,6 +671,10 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
 	_REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
 	_REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
+	/* for DT */
+	_REGISTER_CLOCK("80074000.serial", NULL, uart_clk)
+	_REGISTER_CLOCK("800f0000.ethernet", NULL, fec_clk)
+	_REGISTER_CLOCK("800f4000.ethernet", NULL, fec_clk)
 };
 
 static int clk_misc_init(void)
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
new file mode 100644
index 0000000..6d1e331
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx28.h>
+
+static int __init imx28_icoll_add_irq_domain(struct device_node *np,
+				struct device_node *interrupt_parent)
+{
+	irq_domain_add_simple(np, 0);
+
+	return 0;
+}
+
+static const struct of_device_id mxs_irq_match[] __initconst = {
+	{ .compatible = "fsl,imx28-icoll", .data = imx28_icoll_add_irq_domain, },
+	{ /* sentinel */ }
+};
+
+static void __init mxs_dt_init_irq(void)
+{
+	icoll_init_irq();
+	of_irq_init(mxs_irq_match);
+}
+
+static void __init imx28_timer_init(void)
+{
+	mx28_clocks_init();
+}
+
+static struct sys_timer imx28_timer = {
+	.init = imx28_timer_init,
+};
+
+static void __init imx28_machine_init(void)
+{
+       of_platform_populate(NULL, of_default_bus_match_table,
+		NULL, NULL);
+}
+
+static const char *imx28_dt_compat[] __initdata = {
+	"fsl,imx28",
+	"fsl,imx28-evk",
+	NULL,
+};
+
+DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
+	.map_io		= mx28_map_io,
+	.init_irq	= mxs_dt_init_irq,
+	.timer		= &imx28_timer,
+	.init_machine	= imx28_machine_init,
+	.dt_compat	= imx28_dt_compat,
+	.restart	= mxs_restart,
+MACHINE_END
-- 
1.7.0.4




From jonsmirl at gmail.com  Fri Mar 23 10:32:32 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Fri, 23 Mar 2012 10:32:32 -0400
Subject: ioremap to a specific virtual address
In-Reply-To: <201203231407.00686.arnd@arndb.de>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <alpine.LFD.2.02.1203230023060.24151@xanadu.home>
 <CAKON4Ox6sp5YMryr2jzOAqYNmJG9RyahLTusrHZ_jcNQ40DAfQ@mail.gmail.com>
 <201203231407.00686.arnd@arndb.de>
Message-ID: <CAKON4OzF9KV=51yAR2pVHJZNQsGDkXVhBwbn4njhZPRjeh=-dA@mail.gmail.com>

On Fri, Mar 23, 2012 at 10:07 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 23 March 2012, jonsmirl at gmail.com wrote:
>> So there are two ways to build these mappings..
>>
>> 1) At init time. I can extract the 11 regions, dynamically build a
>> 'struct map_desc' and call iotable_init. Doing it at init time via the
>> device tree will work, but it is complicated by the existence of nodes
>> in the device tree that have their status set to disabled. The init
>> time code will need to sort this out which duplicates what the driver
>> load system does.
>
> There is nothing wrong with setting up the static mappings at boot
> time for all devices, you don't need to check whether they are actually
> present. I would assume that you have plenty of virtual address space
> on lpc31xx, given that those machines tend to come with rather little
> physical memory.
>
>> 2) Driver load time. This is why I asked the initial question about
>> how to do ioremap to the specific virtual address. I didn't want to
>> rewrite all of the existing code to use the more normal style of
>> mapping. So is there some way to create the static mapping at a
>> specific address when the driver first loads?
>>
>> Is there any real advantage to doing the mapping at init time other
>> than being able to control which virtual address you get?
>
> The main reason why we do it in a lot of drivers is to allow the
> drivers to be used across multiple platforms that have the devices
> at a different location. We will soon (for some definition of that
> term) have multiplatform kernels that can run e.g. on lpc31xx and
> lpc32xx, and those two families can have the same devices at a different
> memory location, or could have a different number of devices of
> the same kind.
>
> In particular, in order to enable the multiplatform kernel, we have
> to restrict access of device drivers to platform specific header file
> in all cases where those have conflicting contents.

Isn't this a symptom of not having device trees? If the devices are
identical the header files should be identical except for the base
address. The device tree allows you to get that base address out of
the header file.

Assuming that we can clear up the conflicts in the header files, then
wouldn't it make sense to use ioremap in the  driver, let it assign a
random address, and then fix my code to the base+offset model?


>> I can start looking at how much code needs to be converted to the base
>> + offset model. One advantage to converting is that I'll get an
>> immediate GPF each time I mess up. Converting the code will let it
>> work with the random address from ioremap.
>>
>> This is a NXP BSP for the lpc31xx from about three years ago. I've
>> forward ported it up to v3.3 and I want to get device tree going in
>> it. We have products based on this chip and I'd like to be able to
>> build a single kernel that works in all of the various configurations.
>
> I think you should work together with Roland Stigge, who is currently
> looking into doing the same for lpc32xx. My guess is that you can save
> a lot of work by combining your efforts, while you would get conflicting
> DT bindings if you don't. Note that Roland has done a lot of patches
> already for nxp device drivers that will be part of v3.4. He has not yet
> started on DT patches but wants to work on that for v3.5.

I will need to check how similar the chips actually are. NXP did not
use primecells in the lpc31xx family.

I'd be happy to have some help. My trees are here:
https://github.com/jonsmirl

I haven't pushed out my device tree support because it doesn't work
yet. Its about half finished. Roland, check out the SPL support in
u-boot for the lpc31xx.

>
> ? ? ? ?Arnd



-- 
Jon Smirl
jonsmirl at gmail.com


From arnd at arndb.de  Fri Mar 23 10:38:08 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 23 Mar 2012 14:38:08 +0000
Subject: AMP IPC
In-Reply-To: <CANThrT_wahTpwRDcx-DGQWpDW7j0psKZsk92-4_+vy_Y=xyvtw@mail.gmail.com>
References: <CANThrT_wahTpwRDcx-DGQWpDW7j0psKZsk92-4_+vy_Y=xyvtw@mail.gmail.com>
Message-ID: <201203231438.08577.arnd@arndb.de>

On Wednesday 21 March 2012, Jorge Luis Zapata Muga wrote:
> I have to add support for an ARM based board and develop an IPC
> mechanism for its multiple AMP cores it has, looking on the current
> state of things, seems that there are several attempts for this,
> basically:
> 
> - remoteporc/rpmsg based in virtio
> - peripheral image loader (PIL)
> - PRUSS (Programmable Real-time Unit Sub System)
> - maybe others I'm missing?
> 
> Could someone explain what has been adopted? is there some common
> effort for this need? is there some branch where the patches have been
> accepted?
> 

remoteproc/rpmsg is in the arm-soc tree now and I'm submitting it
for inclusion into v3.4. There are lots of others that won't make
it in, and the chances for anything else are drastically decreasing
once we have this one.

I believe all the Linaro members have agreed to use remoteproc/rpmsg
in future products instead of their own solutions and a number of
other people are looking into doing the same.

	Arnd


From marek.vasut at gmail.com  Fri Mar 23 10:43:54 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 23 Mar 2012 15:43:54 +0100
Subject: [PATCH v2 1/1] ARM: imx28: add basic dt support
In-Reply-To: <1332513070-5400-1-git-send-email-b29396@freescale.com>
References: <1332513070-5400-1-git-send-email-b29396@freescale.com>
Message-ID: <201203231543.54588.marek.vasut@gmail.com>

Dear Dong Aisheng,

> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> This patch includes basic dt support which can boot via nfs rootfs.
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
> ChangeLog v1->v2:
>  * Some fixes addressed Rob's review comments.
>    Remove using of OF_DEV_AUXDATA.
>  * Remove mac address from dts file
>    Currently we use the mac address got from uboot to work.
>    Will submit a p separate atch using prom_update_property to fix this
>    issue for driver based on suggestions from Grant and Lothar.
>  * rename mxs-dt.c to mach-mxs.c which is supposed to support mx23 dt
>    too in the future.
>  * add compatible string "fsl,imx28" per Sascha's suggestion
>  * add more devices in dtsi file
>    For those devices still not in use, set the state to "disabled"
>    by default.
> 
> For other patches i sent with this in the first series like mmc and sdma
> dt support, i will send out them separately since this patch does not
> depend on them and does not block you to run dt via nfs rootfs.
> ---
>  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
>  arch/arm/boot/dts/imx28-evk.dts               |   35 +++

Isn't this supposed to be "mx28evk.dts"?

>  arch/arm/boot/dts/imx28.dtsi                  |  358
> +++++++++++++++++++++++++ arch/arm/mach-mxs/Kconfig                     | 
>   8 +
>  arch/arm/mach-mxs/Makefile                    |    1 +
>  arch/arm/mach-mxs/clock-mx28.c                |    4 +
>  arch/arm/mach-mxs/mach-mxs.c                  |   69 +++++
>  7 files changed, 479 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/imx28-evk.dts
>  create mode 100644 arch/arm/boot/dts/imx28.dtsi
>  create mode 100644 arch/arm/mach-mxs/mach-mxs.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
> b/Documentation/devicetree/bindings/arm/fsl.txt index 54bddda..9f21faf
> 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -1,6 +1,10 @@
>  Freescale i.MX Platforms Device Tree Bindings
>  -----------------------------------------------
> 
> +i.MX28 Evaluation Kit
> +Required root node properties:
> +    - compatible = "fsl,imx28-evk", "fsl,imx28";
> +
>  i.MX51 Babbage Board
>  Required root node properties:
>      - compatible = "fsl,imx51-babbage", "fsl,imx51";
> diff --git a/arch/arm/boot/dts/imx28-evk.dts
> b/arch/arm/boot/dts/imx28-evk.dts new file mode 100644
> index 0000000..5402495
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx28-evk.dts
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "imx28.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX28 Evaluation Kit";
> +	compatible = "fsl,imx28-evk", "fsl,imx28";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x40000000 0x08000000>;
> +	};
> +
> +	ahb at 80080000 {
> +		ethernet at 800f0000 {

fec at ... would be more readable, but I think this was decided before to be like 
this?

> +			phy-mode = "rmii";
> +			status = "okay";
> +		};
> +

[...]

> diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
> index 908bf9a..8328c45 100644
> --- a/arch/arm/mach-mxs/Makefile
> +++ b/arch/arm/mach-mxs/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
>  obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
>  obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
> 
> +obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
>  obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
>  obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
>  obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
> diff --git a/arch/arm/mach-mxs/clock-mx28.c
> b/arch/arm/mach-mxs/clock-mx28.c index 5d68e41..88ed30c 100644
> --- a/arch/arm/mach-mxs/clock-mx28.c
> +++ b/arch/arm/mach-mxs/clock-mx28.c
> @@ -671,6 +671,10 @@ static struct clk_lookup lookups[] = {
>  	_REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
>  	_REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
>  	_REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
> +	/* for DT */
> +	_REGISTER_CLOCK("80074000.serial", NULL, uart_clk)
> +	_REGISTER_CLOCK("800f0000.ethernet", NULL, fec_clk)
> +	_REGISTER_CLOCK("800f4000.ethernet", NULL, fec_clk)

Wasn't the DT stuff supposed to be more symbolic? Aka. this seems weird.

>  };
> 
>  static int clk_misc_init(void)

Best regards,


From arnd at arndb.de  Fri Mar 23 10:49:11 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 23 Mar 2012 14:49:11 +0000
Subject: ioremap to a specific virtual address
In-Reply-To: <CAKON4OzF9KV=51yAR2pVHJZNQsGDkXVhBwbn4njhZPRjeh=-dA@mail.gmail.com>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <201203231407.00686.arnd@arndb.de>
 <CAKON4OzF9KV=51yAR2pVHJZNQsGDkXVhBwbn4njhZPRjeh=-dA@mail.gmail.com>
Message-ID: <201203231449.12209.arnd@arndb.de>

On Friday 23 March 2012, jonsmirl at gmail.com wrote:
> > In particular, in order to enable the multiplatform kernel, we have
> > to restrict access of device drivers to platform specific header file
> > in all cases where those have conflicting contents.
> 
> Isn't this a symptom of not having device trees? If the devices are
> identical the header files should be identical except for the base
> address. The device tree allows you to get that base address out of
> the header file.

Well, device trees are not the only solution that works for this.
You can also get the base address out of statically declared platform
devices in the platform code. The problem here is not the lack
of device trees, but code that is not written to be run time
configured. Moving to device tree requires the same changes though.

> Assuming that we can clear up the conflicts in the header files, then
> wouldn't it make sense to use ioremap in the  driver, let it assign a
> random address, and then fix my code to the base+offset model?

I think that is the right solution in any case, as it helps with
both the multiplatform kernels and device trees.

	Arnd


From wade_farnsworth at mentor.com  Fri Mar 23 10:50:22 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Fri, 23 Mar 2012 07:50:22 -0700
Subject: [PATCH v4 0/3] ARM support for syscall tracing
In-Reply-To: <4F54D0D4.7070905@mentor.com>
References: <4F44FF58.3060907@mentor.com> <4F4E3780.4060904@mentor.com>
 <4F54D0D4.7070905@mentor.com>
Message-ID: <4F6C8DAE.9070209@mentor.com>

This is a rework of Steven Walter's syscall tracing patches first
posted here:

http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074454.html

I've rebased the patches against the current mainline master branch, as well
as implemented several changes based on feedback from Will Deacon and
Russel King.

v2: - Tested on EABI and OABI.
    - Removed an instance of the ?: operator in syscall_set_return_value()
    - Moved #define of NR_syscalls to syscall.h
    - Changed the test of NR_syscalls vs __NR_syscalls in entry-common.S
      to .ifne
v3: - Added Will Deacon's Reviewed-by line.  Code is identical to v2.
v4: - Updated comment and error string for the NR_syscalls test to
      reflect that it's now testing for inequality.

Russell, now that this has been reviewed by Will and tested with both
ABIs, is this okay to submit to your patch tracker?

Wade Farnsworth (3):
  ARM: add support for the generic syscall.h interface
  ARM: add TRACEHOOK support
  ARM: support syscall tracing

 arch/arm/Kconfig                   |    2 +
 arch/arm/include/asm/ptrace.h      |    5 ++
 arch/arm/include/asm/syscall.h     |   97 ++++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/thread_info.h |    2 +
 arch/arm/include/asm/unistd.h      |    8 +++
 arch/arm/kernel/entry-common.S     |   18 ++++++-
 arch/arm/kernel/ptrace.c           |   34 +++++++------
 arch/arm/kernel/signal.c           |    2 +
 8 files changed, 151 insertions(+), 17 deletions(-)
 create mode 100644 arch/arm/include/asm/syscall.h



From wade_farnsworth at mentor.com  Fri Mar 23 10:51:12 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Fri, 23 Mar 2012 07:51:12 -0700
Subject: [PATCH v4 1/3] ARM: add support for the generic syscall.h interface
In-Reply-To: <4F6C8DAE.9070209@mentor.com>
References: <4F44FF58.3060907@mentor.com> <4F4E3780.4060904@mentor.com>
 <4F54D0D4.7070905@mentor.com> <4F6C8DAE.9070209@mentor.com>
Message-ID: <4F6C8DE0.4010803@mentor.com>

Supplying the asm-generic/syscall.h interface is a
pre-requisite for HAVE_ARCH_TRACEHOOK

Signed-off-by: Steven Walter <stevenrwalter at gmail.com>
Signed-off-by: Wade Farnsworth <wade_farnsworth at mentor.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/syscall.h |   93 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 93 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/syscall.h

diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
new file mode 100644
index 0000000..c334a23
--- /dev/null
+++ b/arch/arm/include/asm/syscall.h
@@ -0,0 +1,93 @@
+/*
+ * Access to user system call parameters and results
+ *
+ * See asm-generic/syscall.h for descriptions of what we must do here.
+ */
+
+#ifndef _ASM_ARM_SYSCALL_H
+#define _ASM_ARM_SYSCALL_H
+
+#include <linux/err.h>
+
+extern const unsigned long sys_call_table[];
+
+static inline int syscall_get_nr(struct task_struct *task,
+				 struct pt_regs *regs)
+{
+	return task_thread_info(task)->syscall;
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+				    struct pt_regs *regs)
+{
+	regs->ARM_r0 = regs->ARM_ORIG_r0;
+}
+
+static inline long syscall_get_error(struct task_struct *task,
+				     struct pt_regs *regs)
+{
+	unsigned long error = regs->ARM_r0;
+	return IS_ERR_VALUE(error) ? error : 0;
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+					    struct pt_regs *regs)
+{
+	return regs->ARM_r0;
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+					    struct pt_regs *regs,
+					    int error, long val)
+{
+	regs->ARM_r0 = (long) error ? error : val;
+}
+
+#define SYSCALL_MAX_ARGS 7
+
+static inline void syscall_get_arguments(struct task_struct *task,
+					 struct pt_regs *regs,
+					 unsigned int i, unsigned int n,
+					 unsigned long *args)
+{
+	if (i + n > SYSCALL_MAX_ARGS) {
+		unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
+		unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
+		pr_warning("%s called with max args %d, handling only %d\n",
+			   __func__, i + n, SYSCALL_MAX_ARGS);
+		memset(args_bad, 0, n_bad * sizeof(args[0]));
+		n = SYSCALL_MAX_ARGS - i;
+	}
+
+	if (i == 0) {
+		args[0] = regs->ARM_ORIG_r0;
+		args++;
+		i++;
+		n--;
+	}
+
+	memcpy(args, &regs->ARM_r0 + i, n * sizeof(args[0]));
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+					 struct pt_regs *regs,
+					 unsigned int i, unsigned int n,
+					 const unsigned long *args)
+{
+	if (i + n > SYSCALL_MAX_ARGS) {
+		pr_warning("%s called with max args %d, handling only %d\n",
+			   __func__, i + n, SYSCALL_MAX_ARGS);
+		n = SYSCALL_MAX_ARGS - i;
+	}
+
+	if (i == 0) {
+		regs->ARM_ORIG_r0 = args[0];
+		args++;
+		i++;
+		n--;
+	}
+
+	memcpy(&regs->ARM_r0 + i, args, n * sizeof(args[0]));
+}
+
+#endif /* _ASM_ARM_SYSCALL_H */
-- 
1.7.0.4



From stigge at antcom.de  Fri Mar 23 10:52:05 2012
From: stigge at antcom.de (Roland Stigge)
Date: Fri, 23 Mar 2012 15:52:05 +0100
Subject: ioremap to a specific virtual address
In-Reply-To: <201203231407.00686.arnd@arndb.de>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <alpine.LFD.2.02.1203230023060.24151@xanadu.home>
 <CAKON4Ox6sp5YMryr2jzOAqYNmJG9RyahLTusrHZ_jcNQ40DAfQ@mail.gmail.com>
 <201203231407.00686.arnd@arndb.de>
Message-ID: <4F6C8E15.5050104@antcom.de>

Hi Jon,

On 23/03/12 15:07, Arnd Bergmann wrote:
> I think you should work together with Roland Stigge, who is currently
> looking into doing the same for lpc32xx. My guess is that you can save
> a lot of work by combining your efforts, while you would get conflicting
> DT bindings if you don't. Note that Roland has done a lot of patches
> already for nxp device drivers that will be part of v3.4. He has not yet
> started on DT patches but wants to work on that for v3.5.

You wrote about NXP's BSP from 3 years ago. At git.lpclinux.com, you can
find lpc31xx's branches, updated only some weeks ago, based on Linux 2.6.33.

Feel free to join my efforts for DT on lpc32xx. Don't know how much
lpc31xx and lpc32xx have in common, and I currently don't have access to
an lpc31xx device. However, I will post patches for DT support on
lpc32xx, based on the patches I already have at git.antcom.de and
antcom.de/lpc32xx/ (some of which already go into v3.4).

Thanks,

Roland


From wade_farnsworth at mentor.com  Fri Mar 23 10:52:25 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Fri, 23 Mar 2012 07:52:25 -0700
Subject: [PATCH v4 2/3] ARM: add TRACEHOOK support
In-Reply-To: <4F6C8DAE.9070209@mentor.com>
References: <4F44FF58.3060907@mentor.com> <4F4E3780.4060904@mentor.com>
 <4F54D0D4.7070905@mentor.com> <4F6C8DAE.9070209@mentor.com>
Message-ID: <4F6C8E29.3070801@mentor.com>

Add calls to tracehook_report_syscall_{entry,exit} and tracehook_signal_handler

Signed-off-by: Steven Walter <stevenrwalter at gmail.com>
Signed-off-by: Wade Farnsworth <wade_farnsworth at mentor.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig              |    1 +
 arch/arm/include/asm/ptrace.h |    5 +++++
 arch/arm/kernel/ptrace.c      |   21 ++++++---------------
 arch/arm/kernel/signal.c      |    2 ++
 4 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dfb0312..c87e23f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -10,6 +10,7 @@ config ARM
 	select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
 	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
 	select HAVE_ARCH_KGDB
+	select HAVE_ARCH_TRACEHOOK
 	select HAVE_KPROBES if !XIP_KERNEL
 	select HAVE_KRETPROBES if (HAVE_KPROBES)
 	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 451808b..355ece5 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -249,6 +249,11 @@ static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
 	return regs->ARM_sp;
 }
 
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+	return regs->ARM_sp;
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index ede6443..46f4b41 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -24,6 +24,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/regset.h>
 #include <linux/audit.h>
+#include <linux/tracehook.h>
 
 #include <asm/pgtable.h>
 #include <asm/system.h>
@@ -930,24 +931,14 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
 
 	if (!test_thread_flag(TIF_SYSCALL_TRACE))
 		return scno;
-	if (!(current->ptrace & PT_PTRACED))
-		return scno;
 
 	current_thread_info()->syscall = scno;
 
-	/* the 0x80 provides a way for the tracing parent to distinguish
-	   between a syscall stop and SIGTRAP delivery */
-	ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
-				 ? 0x80 : 0));
-	/*
-	 * this isn't the same as continuing with a signal, but it will do
-	 * for normal use.  strace only continues with a signal if the
-	 * stopping signal is not SIGTRAP.  -brl
-	 */
-	if (current->exit_code) {
-		send_sig(current->exit_code, current, 1);
-		current->exit_code = 0;
-	}
+	if (why)
+		tracehook_report_syscall_exit(regs, 0);
+	else if (tracehook_report_syscall_entry(regs))
+		current_thread_info()->syscall = -1;
+
 	regs->ARM_ip = ip;
 
 	return current_thread_info()->syscall;
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 9e617bd..6f084c1 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -644,6 +644,8 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
 	recalc_sigpending();
 	spin_unlock_irq(&tsk->sighand->siglock);
 
+	tracehook_signal_handler(sig, info, ka, regs, 0);
+
 	return 0;
 }
 
-- 
1.7.0.4



From wade_farnsworth at mentor.com  Fri Mar 23 10:53:15 2012
From: wade_farnsworth at mentor.com (Wade Farnsworth)
Date: Fri, 23 Mar 2012 07:53:15 -0700
Subject: [PATCH v4 3/3] ARM: support syscall tracing
In-Reply-To: <4F6C8DAE.9070209@mentor.com>
References: <4F44FF58.3060907@mentor.com> <4F4E3780.4060904@mentor.com>
 <4F54D0D4.7070905@mentor.com> <4F6C8DAE.9070209@mentor.com>
Message-ID: <4F6C8E5B.7030004@mentor.com>

As specified by ftrace-design.txt, TIF_SYSCALL_TRACEPOINT was
added, as well as NR_syscalls in asm/unistd.h.  Additionally,
__sys_trace was modified to call trace_sys_enter and
trace_sys_exit when appropriate.

Tests #2 - #4 of "perf test" now complete successfully.

Signed-off-by: Steven Walter <stevenrwalter at gmail.com>
Signed-off-by: Wade Farnsworth <wade_farnsworth at mentor.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig                   |    1 +
 arch/arm/include/asm/syscall.h     |    4 ++++
 arch/arm/include/asm/thread_info.h |    2 ++
 arch/arm/include/asm/unistd.h      |    8 ++++++++
 arch/arm/kernel/entry-common.S     |   18 ++++++++++++++++--
 arch/arm/kernel/ptrace.c           |   23 ++++++++++++++++++-----
 6 files changed, 49 insertions(+), 7 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c87e23f..5603715 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -11,6 +11,7 @@ config ARM
 	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
 	select HAVE_ARCH_KGDB
 	select HAVE_ARCH_TRACEHOOK
+	select HAVE_SYSCALL_TRACEPOINTS
 	select HAVE_KPROBES if !XIP_KERNEL
 	select HAVE_KRETPROBES if (HAVE_KPROBES)
 	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
index c334a23..47486a4 100644
--- a/arch/arm/include/asm/syscall.h
+++ b/arch/arm/include/asm/syscall.h
@@ -9,6 +9,10 @@
 
 #include <linux/err.h>
 
+#include <asm/unistd.h>
+
+#define NR_syscalls (__NR_syscalls)
+
 extern const unsigned long sys_call_table[];
 
 static inline int syscall_get_nr(struct task_struct *task,
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index d4c24d4..f2ff2de 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -146,6 +146,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define TIF_MEMDIE		18	/* is terminating due to OOM killer */
 #define TIF_RESTORE_SIGMASK	20
 #define TIF_SECCOMP		21
+#define TIF_SYSCALL_TRACEPOINT	22
 
 #define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
@@ -156,6 +157,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define _TIF_USING_IWMMXT	(1 << TIF_USING_IWMMXT)
 #define _TIF_RESTORE_SIGMASK	(1 << TIF_RESTORE_SIGMASK)
 #define _TIF_SECCOMP		(1 << TIF_SECCOMP)
+#define _TIF_SYSCALL_TRACEPOINT	(1 << TIF_SYSCALL_TRACEPOINT)
 
 /* Checks for any syscall work in entry-common.S */
 #define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 512cd14..d27d7d7 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -406,6 +406,14 @@
 #define __NR_process_vm_writev		(__NR_SYSCALL_BASE+377)
 
 /*
+ * This may need to be greater than __NR_last_syscall+1 in order to
+ * account for the padding in the syscall table
+ */
+#ifdef __KERNEL__
+#define __NR_syscalls  (380)
+#endif /* __KERNEL__ */
+
+/*
  * The following SWIs are ARM private.
  */
 #define __ARM_NR_BASE			(__NR_SYSCALL_BASE+0x0f0000)
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 9fd0ba9..3df0ca3 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -79,6 +79,11 @@ no_work_pending:
 ENDPROC(ret_to_user_from_irq)
 ENDPROC(ret_to_user)
 
+.macro test_syscall_tracing reg
+       tst     \reg, #_TIF_SYSCALL_WORK
+       tsteq   \reg, #_TIF_SYSCALL_TRACEPOINT
+.endm
+
 /*
  * This is how we return from a fork.
  */
@@ -87,7 +92,7 @@ ENTRY(ret_from_fork)
 	get_thread_info tsk
 	ldr	r1, [tsk, #TI_FLAGS]		@ check for syscall tracing
 	mov	why, #1
-	tst	r1, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
+	test_syscall_tracing r1
 	beq	ret_slow_syscall
 	mov	r1, sp
 	mov	r0, #1				@ trace exit [IP = 1]
@@ -98,6 +103,15 @@ ENDPROC(ret_from_fork)
 	.equ NR_syscalls,0
 #define CALL(x) .equ NR_syscalls,NR_syscalls+1
 #include "calls.S"
+
+/*
+ * Ensure that the system call table is equal to __NR_syscalls,
+ * which is the value the rest of the system sees
+ */
+.ifne NR_syscalls - __NR_syscalls
+.error "__NR_syscalls is not equal to the size of the syscall table"
+.endif
+
 #undef CALL
 #define CALL(x) .long x
 
@@ -446,7 +460,7 @@ ENTRY(vector_swi)
 1:
 #endif
 
-	tst	r10, #_TIF_SYSCALL_WORK		@ are we tracing syscalls?
+	test_syscall_tracing r10
 	bne	__sys_trace
 
 	cmp	scno, #NR_syscalls		@ check upper syscall limit
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 46f4b41..dbbf4ce 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -30,6 +30,9 @@
 #include <asm/system.h>
 #include <asm/traps.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
 #define REG_PC	15
 #define REG_PSR	16
 /*
@@ -929,15 +932,25 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
 		audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0,
 				    regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
 
-	if (!test_thread_flag(TIF_SYSCALL_TRACE))
+	if (!test_thread_flag(TIF_SYSCALL_TRACE) &&
+	    !test_thread_flag(TIF_SYSCALL_TRACEPOINT))
 		return scno;
 
 	current_thread_info()->syscall = scno;
 
-	if (why)
-		tracehook_report_syscall_exit(regs, 0);
-	else if (tracehook_report_syscall_entry(regs))
-		current_thread_info()->syscall = -1;
+	if (test_thread_flag(TIF_SYSCALL_TRACE)) {
+		if (why)
+			tracehook_report_syscall_exit(regs, 0);
+		else if (tracehook_report_syscall_entry(regs))
+			current_thread_info()->syscall = -1;
+	}
+
+	if (test_thread_flag(TIF_SYSCALL_TRACEPOINT)) {
+		if (why)
+			trace_sys_exit(regs, scno);
+		else
+			trace_sys_enter(regs, scno);
+	}
 
 	regs->ARM_ip = ip;
 
-- 
1.7.0.4



From jonsmirl at gmail.com  Fri Mar 23 11:05:12 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Fri, 23 Mar 2012 11:05:12 -0400
Subject: ioremap to a specific virtual address
In-Reply-To: <4F6C8E15.5050104@antcom.de>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <alpine.LFD.2.02.1203230023060.24151@xanadu.home>
 <CAKON4Ox6sp5YMryr2jzOAqYNmJG9RyahLTusrHZ_jcNQ40DAfQ@mail.gmail.com>
 <201203231407.00686.arnd@arndb.de> <4F6C8E15.5050104@antcom.de>
Message-ID: <CAKON4Oz8465uJnv8R_TgCeju9UqG8MTTxVSC_tfS4mP40ARp1A@mail.gmail.com>

On Fri, Mar 23, 2012 at 10:52 AM, Roland Stigge <stigge at antcom.de> wrote:
> Hi Jon,
>
> On 23/03/12 15:07, Arnd Bergmann wrote:
>> I think you should work together with Roland Stigge, who is currently
>> looking into doing the same for lpc32xx. My guess is that you can save
>> a lot of work by combining your efforts, while you would get conflicting
>> DT bindings if you don't. Note that Roland has done a lot of patches
>> already for nxp device drivers that will be part of v3.4. He has not yet
>> started on DT patches but wants to work on that for v3.5.
>
> You wrote about NXP's BSP from 3 years ago. At git.lpclinux.com, you can
> find lpc31xx's branches, updated only some weeks ago, based on Linux 2.6.33.

I've taken the 2.6.33 code and forward ported it to v3.3 in my git
tree. I've been incorporating the patches posted to lpclinux.com.

>
> Feel free to join my efforts for DT on lpc32xx. Don't know how much
> lpc31xx and lpc32xx have in common, and I currently don't have access to

Bangaragiri --- which peripherals do the lpc31xx and the lpc32xx
families have in common?

I know I2C is common and the lpc31xx uses the common driver.
LCD is completely different.
No Ethernet on the lpc31xx.

What about USB? There is code for a NXP variation on EHCI in the
lpc31xx port, does the lpc32xx use the same EHCI block?

Does the lpc32xx have the same event router for interrupts?

What about the rest of the peripherals?

> an lpc31xx device. However, I will post patches for DT support on
> lpc32xx, based on the patches I already have at git.antcom.de and
> antcom.de/lpc32xx/ (some of which already go into v3.4).
>
> Thanks,
>
> Roland



-- 
Jon Smirl
jonsmirl at gmail.com


From stigge at antcom.de  Fri Mar 23 11:12:44 2012
From: stigge at antcom.de (Roland Stigge)
Date: Fri, 23 Mar 2012 16:12:44 +0100
Subject: ioremap to a specific virtual address
In-Reply-To: <CAKON4Oz8465uJnv8R_TgCeju9UqG8MTTxVSC_tfS4mP40ARp1A@mail.gmail.com>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <alpine.LFD.2.02.1203230023060.24151@xanadu.home>
 <CAKON4Ox6sp5YMryr2jzOAqYNmJG9RyahLTusrHZ_jcNQ40DAfQ@mail.gmail.com>
 <201203231407.00686.arnd@arndb.de> <4F6C8E15.5050104@antcom.de>
 <CAKON4Oz8465uJnv8R_TgCeju9UqG8MTTxVSC_tfS4mP40ARp1A@mail.gmail.com>
Message-ID: <4F6C92EC.2050200@antcom.de>

On 23/03/12 16:05, jonsmirl at gmail.com wrote:
> I've taken the 2.6.33 code and forward ported it to v3.3 in my git
> tree. I've been incorporating the patches posted to lpclinux.com.

Similar to what I did with lpc32xx. :-) NXP maintains lpc31xx and
lpc32xx at different repos, though.

> What about USB? There is code for a NXP variation on EHCI in the
> lpc31xx port, does the lpc32xx use the same EHCI block?

LPC32xx only has OHCI. For v3.4, I joined ohci-pnx4008 and ohci-lpc32xx
into ohci-nxp since only some transceiver I2C initialization was different.

Roland


From arnd at arndb.de  Fri Mar 23 11:20:22 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 23 Mar 2012 15:20:22 +0000
Subject: ioremap to a specific virtual address
In-Reply-To: <CAKON4OzF9KV=51yAR2pVHJZNQsGDkXVhBwbn4njhZPRjeh=-dA@mail.gmail.com>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <201203231407.00686.arnd@arndb.de>
 <CAKON4OzF9KV=51yAR2pVHJZNQsGDkXVhBwbn4njhZPRjeh=-dA@mail.gmail.com>
Message-ID: <201203231520.22588.arnd@arndb.de>

On Friday 23 March 2012, jonsmirl at gmail.com wrote:
> I will need to check how similar the chips actually are. NXP did not
> use primecells in the lpc31xx family.
> 
> I'd be happy to have some help. My trees are here:
> https://github.com/jonsmirl

I've taken a brief look at your tree, some comments:

* Once you're done with the DT conversion, you should be able to
  completely remvoe the three board files. You probably know that already

* We're merging the new common clock framework in v3.4. Once that has
  matured, all new platforms will be required to use it. You should probably
  move to that already.

* The dma driver uses a nonstandard interface and should be moved to
  drivers/dma, using the dmaengine API.

* The __REG needs to be removed. All MMIO register accesses should go
  through readl/writel or readl_relaxed/writel_relaxed, using a pointer
  you get from ioremap.

* gpio*.c should get moved to drivers/gpio/gpio-lpc31xx. If it's similar
  to the 32xx version, merge the two

* i2c.c should no longer be needed with the device tree, but you might
  have to add stuff to i2c-pnx.c. That file is shared with pnx4008 and
  lpc32xx.

* irq.c will eventually go to drivers/irqchip/. We have a plan to create
  that directory, but nobody has started moving drivers there.

* Some of the header files have been removed on other platforms, you
  should do the same.

* Regarding the static mappings, it certainly makes sense to map all of
  ABP01_PHYS and IO_APB2_PHYS using 1MB mappings, for performance reasons,
  and I guess you need INTC_PHYS to be mapped, too, for the interrupt
  controller code to work. However, none of the drivers should be aware
  of this and just call ioremap anyway, which will now return an address
  from the static mapping.

	Arnd


From b-cousson at ti.com  Fri Mar 23 11:39:21 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Fri, 23 Mar 2012 16:39:21 +0100
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A9317A6A83@DBDE01.ent.ti.com>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
 <4F6C445A.3040103@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A9317A6A83@DBDE01.ent.ti.com>
Message-ID: <4F6C9929.6030704@ti.com>

+ Felipe

On 3/23/2012 11:20 AM, Mohammed, Afzal wrote:
> Hi Benoit,
>
> On Fri, Mar 23, 2012 at 15:07:30, Cousson, Benoit wrote:
>>> Final destination aimed for this driver is MFD.
>>
>> Why? Are you sure this is appropriate? This is not really a
>> multifunction device but rather a bus device that can manage multiple
>> kind of devices.
>
>
> Agree, this not an MFD, but can we call this a bus?, as there is
> nothing like GPMC protocol. We considered it logically as MFD&
> proceeded and there was a similar attempt for davinci EMIF [1,2].

But EMIF does not have anything to do in MFD either :-)

What was the feedback for this series?

We discussed that at Linaro connect, but it looks like MFD is becoming 
the place for miscellaneous drivers that we do not know where to put.

Maybe we should introduce a driver/memory/ directory for memory 
controller. At least for EMIF.
In the case of GMPC, it is slightly different because it can handle 
NOR/NAND memory but as well behave like an ISA bus controller for 
Ethernet ISA chip.
But since it can control several devices thanks the chipselects lines it 
has, it behaves like a multi-protocol bus controller.
But in anycase, it does not look like an MFD for my point of view. For 
me a MFD is like a small soc, it does contain several completely 
unrelated block (Power, Audio, GPIO...), but does share some memory 
space / IRQ lines.

Is this the only controller doing that kind of stuff in the kernel so far?

>>>    arch/arm/mach-omap2/gpmc.c             | 1083 +++++++++++++++++++-------------
>>
>> You should probably find the proper location first, move the code and
>> convert to driver.
>> I will let Tony comment but this is the strategy today for all this
>> pseudo driver that should not be in OMAP arch directory anymore.
>
> Please let me know whether you have any suggestions on where GPMC driver
> should live.
>
>>> +		printk(KERN_DEBUG "GPMC CS%d: %-10s* %3d ns, %3d ticks>= %d\n",
>>
>> Nit, but since you are cleaning extensively this code, you should use
>> pr_ macros instead or even dev_ macros since you do have a real driver
>> now with real devices now.
>
> Sure, this was overlooked
>
>>> +struct gpmc_cs_config {
>>> +	u32 config1;
>>> +	u32 config2;
>>> +	u32 config3;
>>> +	u32 config4;
>>> +	u32 config5;
>>> +	u32 config6;
>>> +	u32 config7;
>>> +	int is_valid;
>>> +};
>>
>> OK, so this code was just moved and not removed. Becasue of these big
>> code move, the patch is not super readable. We cannot really see what
>> part is new and what was changed.
>>
>> Maybe you should try to split that in sevarl patches or minized the move.
>
> Yes, I was really in two minds before the coding started. Lot of code in
> this patch has been moved from one place to other, this was done to put
> codes that handle similar things together, so that trees can be made
> visible easily in the forest. And once the patch is applied, as similar
> sections are together, it may be easy to make further changes
>
> If an initial patch just to rearrange the code to have similar section
> together&  then new changes in a another patch, would that be fine?

Well, if this is just comestic, I will even do that after the driver 
conversion. Because if you do that before you will move some piece of 
code that you might completely delete later. So you should fix the code 
first and then potentially, move some part if that will improve the 
readability.

>
>> +static int __init gpmc_clk_init(void)
>>> +{
>>> +	char *ck = NULL;
>>> +
>>> +	if (cpu_is_omap24xx())
>>> +		ck = "core_l3_ck";
>>> +	else if (cpu_is_omap34xx())
>>> +		ck = "gpmc_fck";
>>> +	else if (cpu_is_omap44xx())
>>> +		ck = "gpmc_ck";
>>
>> Please don't do that anymore. The CLKDEV array is done to create alias
>> and avoid this kind of hacks. Moreover you should rely on hwmod for
>> device creation and thus main clock alias will already be populated for
>> free.
>
> There are not added, they are existing code, result of rearranging the
> code. These sections were given not given much importance as these won't
> go into driver. But noted the point you are making.

The issue is that the cpu_is_XXX should not be accessed from outside 
mach-omap2 directory, so you should get rid of that before trying to 
move the gpmc in the XXX location.

Regards,
Benoit


From hartleys at visionengravers.com  Fri Mar 23 12:09:50 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Fri, 23 Mar 2012 11:09:50 -0500
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <20120323070446.GC5812@mwesterb-mobl.ger.corp.intel.com>
References: <4F683B36.8090101@metasoft.pl>
 <20120321193836.GC3740@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48E3E@AUSP01VMBX24.collaborationhost.net>
 <20120323070446.GC5812@mwesterb-mobl.ger.corp.intel.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020696D48EEB@AUSP01VMBX24.collaborationhost.net>

On Friday, March 23, 2012 12:05 AM, Mika Westerberg wrote:
> On Thu, Mar 22, 2012 at 09:19:10PM -0500, H Hartley Sweeten wrote:
>
>> Did you test this patch or just review it?
>
> I tested and reviewed it.

OK. What kernel? My tests so far have been with 3.3.

>> On my system it doesn't work. I think it has something to do with the
>> changes to m2m_hw_interrupt but I haven't tracked it down yet.
>> 
>> It looks like what's missing is a:
>> 
>> 	edmac->edma->hw_submit(edmac);
>> 
>> But, maybe that's not needed with double buffering?
>
> Did you try without your patch and adding my VIC hack? That's what I did when
> I first got this patch and I saw no problems. I tested with audio (M2P),
> mmc_spi (M2M) and dmatest (M2M).

No, I have not applied your VIC hack.

Until we get a working solution, without any hacks, I don't want this to go in.

Regards,
Hartley



From balbi at ti.com  Fri Mar 23 12:29:00 2012
From: balbi at ti.com (Felipe Balbi)
Date: Fri, 23 Mar 2012 18:29:00 +0200
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <4F6C9929.6030704@ti.com>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
 <4F6C445A.3040103@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A9317A6A83@DBDE01.ent.ti.com>
 <4F6C9929.6030704@ti.com>
Message-ID: <20120323162859.GC24544@arwen.pp.htv.fi>

Hi,

On Fri, Mar 23, 2012 at 04:39:21PM +0100, Cousson, Benoit wrote:
> + Felipe
> 
> On 3/23/2012 11:20 AM, Mohammed, Afzal wrote:
> >Hi Benoit,
> >
> >On Fri, Mar 23, 2012 at 15:07:30, Cousson, Benoit wrote:
> >>>Final destination aimed for this driver is MFD.
> >>
> >>Why? Are you sure this is appropriate? This is not really a
> >>multifunction device but rather a bus device that can manage multiple
> >>kind of devices.
> >
> >
> >Agree, this not an MFD, but can we call this a bus?, as there is
> >nothing like GPMC protocol. We considered it logically as MFD&
> >proceeded and there was a similar attempt for davinci EMIF [1,2].
> 
> But EMIF does not have anything to do in MFD either :-)
> 
> What was the feedback for this series?
> 
> We discussed that at Linaro connect, but it looks like MFD is
> becoming the place for miscellaneous drivers that we do not know
> where to put.
> 
> Maybe we should introduce a driver/memory/ directory for memory
> controller. At least for EMIF.

yeah, I was thinking about drivers/ocd (off-chip devices) or
drivers/mmio... and that should be flexible enough to hold gpmc, lli and
c2c (from OMAP's perspective).

> In the case of GMPC, it is slightly different because it can handle
> NOR/NAND memory but as well behave like an ISA bus controller for
> Ethernet ISA chip.
> But since it can control several devices thanks the chipselects lines
> it has, it behaves like a multi-protocol bus controller.

indeed.

> >>>   arch/arm/mach-omap2/gpmc.c             | 1083 +++++++++++++++++++-------------
> >>
> >>You should probably find the proper location first, move the code and
> >>convert to driver.

I wouldn't do that. I would only move after the driver is cleaned up.
Are you concerned with the diffstat alone ? that'd be silly :-p

> >>I will let Tony comment but this is the strategy today for all this
> >>pseudo driver that should not be in OMAP arch directory anymore.

indeed, there are a bunch of those still:

$ git grep -e module_init arch/arm/*omap*
arch/arm/mach-omap1/mailbox.c:module_init(omap1_mbox_init);
arch/arm/mach-omap2/dsp.c:module_init(omap_dsp_init);
arch/arm/mach-omap2/iommu2.c:module_init(omap2_iommu_init);
arch/arm/mach-omap2/mailbox.c:module_init(omap2_mbox_init);
arch/arm/plat-omap/dmtimer.c:module_init(omap_dm_timer_driver_init);
arch/arm/plat-omap/ocpi.c:module_init(omap_ocpi_init);

> >Please let me know whether you have any suggestions on where GPMC driver
> >should live.
> >
> >>>+		printk(KERN_DEBUG "GPMC CS%d: %-10s* %3d ns, %3d ticks>= %d\n",
> >>
> >>Nit, but since you are cleaning extensively this code, you should use
> >>pr_ macros instead or even dev_ macros since you do have a real driver
> >>now with real devices now.

if we have a struct device pointer, don't use anything other than dev_*

> >Sure, this was overlooked
> >
> >>>+struct gpmc_cs_config {
> >>>+	u32 config1;
> >>>+	u32 config2;
> >>>+	u32 config3;
> >>>+	u32 config4;
> >>>+	u32 config5;
> >>>+	u32 config6;
> >>>+	u32 config7;
> >>>+	int is_valid;
> >>>+};
> >>
> >>OK, so this code was just moved and not removed. Becasue of these big
> >>code move, the patch is not super readable. We cannot really see what
> >>part is new and what was changed.
> >>
> >>Maybe you should try to split that in sevarl patches or minized the move.

sounds plausible to me.

> >Yes, I was really in two minds before the coding started. Lot of code in
> >this patch has been moved from one place to other, this was done to put
> >codes that handle similar things together, so that trees can be made
> >visible easily in the forest. And once the patch is applied, as similar
> >sections are together, it may be easy to make further changes
> >
> >If an initial patch just to rearrange the code to have similar section
> >together&  then new changes in a another patch, would that be fine?
> 
> Well, if this is just comestic, I will even do that after the driver
> conversion. Because if you do that before you will move some piece of
> code that you might completely delete later. So you should fix the
> code first and then potentially, move some part if that will improve
> the readability.
> 
> >
> >>+static int __init gpmc_clk_init(void)
> >>>+{
> >>>+	char *ck = NULL;
> >>>+
> >>>+	if (cpu_is_omap24xx())
> >>>+		ck = "core_l3_ck";
> >>>+	else if (cpu_is_omap34xx())
> >>>+		ck = "gpmc_fck";
> >>>+	else if (cpu_is_omap44xx())
> >>>+		ck = "gpmc_ck";
> >>
> >>Please don't do that anymore. The CLKDEV array is done to create alias
> >>and avoid this kind of hacks. Moreover you should rely on hwmod for
> >>device creation and thus main clock alias will already be populated for
> >>free.
> >
> >There are not added, they are existing code, result of rearranging the
> >code. These sections were given not given much importance as these won't
> >go into driver. But noted the point you are making.
> 
> The issue is that the cpu_is_XXX should not be accessed from outside
> mach-omap2 directory, so you should get rid of that before trying to
> move the gpmc in the XXX location.

yes, that's right. But until he can move the code, there's still a lot
of work to be done, right ? This included.

ps: can someone bounce the thread to me ? I don't seem to have it on my
inbox (damn mail servers) and replying by lookin' at the archives is
rather difficult.

-- 
balbi
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From swarren at wwwdotorg.org  Fri Mar 23 12:55:44 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 23 Mar 2012 10:55:44 -0600
Subject: [PATCH 2/2] ARM: GIC: Create common infrastructure for GIC DT
 bindings
In-Reply-To: <23b4d2ea357a7a785b6c42d0fa7ae9478bad552b.1332488625.git.viresh.kumar@st.com>
References: <4bfe7af3761f6f40506a2089fd67866015f6d7f3.1332488625.git.viresh.kumar@st.com>
 <23b4d2ea357a7a785b6c42d0fa7ae9478bad552b.1332488625.git.viresh.kumar@st.com>
Message-ID: <4F6CAB10.2020204@wwwdotorg.org>

On 03/23/2012 01:49 AM, Viresh Kumar wrote:
> Few platforms define there own struct of_device_id[] for GIC. They don't
> do anything specific in init_irq() other than of_irq_init().
> 
> This patch creates this struct array in gic.c and make other platforms use it.
> 
> Signed-off-by: Viresh Kumar <viresh.kumar at st.com>

For Tegra,
Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From mathieu.poirier at linaro.org  Fri Mar 23 13:13:47 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Fri, 23 Mar 2012 11:13:47 -0600
Subject: [PATCH 0/9] omap randconfig fixes for v3.3
Message-ID: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>

From: "Arnd Bergmann" <arnd at arndb.de>

The following is a set of patches that have been sent
out during the 3.1 cycle that were not acked or merged.

Sending again for completeness.  

Tony, please pull if there are no objections:

The following changes since commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7:

  Linux 3.3 (2012-03-18 16:15:34 -0700)

are available in the git repository at:
  git://git.linaro.org/people/mpoirier/linux.git randconfig-omap
 

Arnd Bergmann (8):
  arm/omap: enable building omap2 without omap2420/2430
  omap: fix visibility of omap2_mbox_iva_priv
  ARM: omap2+: fix building without i2c
  tty/serial/omap: console can only be built-in
  omap2: select twl4030 support on boards that need it
  omap2plus: ensure that one of omap2/3/4 is selected
  arm: OMAP depends on MMU
  ARM: omap: select CPU_FREQ_TABLE where needed

Russell King (1):
  ARM: omap2/n8x0: work around modular omap mmc

 arch/arm/Kconfig                           |    1 +
 arch/arm/mach-omap2/Kconfig                |   19 +++++++++++++++++++
 arch/arm/mach-omap2/board-n8x0.c           |    6 ++++--
 arch/arm/mach-omap2/mailbox.c              |    2 +-
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |    2 +-
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |    2 +-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |    2 +-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    2 +-
 arch/arm/plat-omap/Kconfig                 |    5 +++++
 arch/arm/plat-omap/include/plat/multi.h    |    5 +++++
 drivers/tty/serial/Kconfig                 |    2 +-
 11 files changed, 40 insertions(+), 8 deletions(-)

-- 
1.7.5.4



From mathieu.poirier at linaro.org  Fri Mar 23 13:13:48 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Fri, 23 Mar 2012 11:13:48 -0600
Subject: [PATCH 1/9] arm/omap: enable building omap2 without omap2420/2430
In-Reply-To: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <1332522836-29517-2-git-send-email-mathieu.poirier@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

Kconfig allows selecting CONFIG_OMAP2 but no specific SOC, the options
being omap2420 and omap2430, but that leads to a build error when
omap3 or omap4 are also enabled and the MULTI_OMAP2 symbol is
undefined.

This adds another clause to plat/multi.h, mainly to allow all
possible randconfig combinations to build cleanly.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/plat-omap/include/plat/multi.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index 999ffba..fb7f196 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -82,6 +82,11 @@
 #  define OMAP_NAME omap2430
 # endif
 #endif
+#ifdef CONFIG_ARCH_OMAP2
+# ifndef OMAP_NAME
+#  define OMAP_NAME omap2
+# endif
+#endif
 #ifdef CONFIG_ARCH_OMAP3
 # ifdef OMAP_NAME
 #  undef  MULTI_OMAP2
-- 
1.7.5.4



From mathieu.poirier at linaro.org  Fri Mar 23 13:13:49 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Fri, 23 Mar 2012 11:13:49 -0600
Subject: [PATCH 2/9] omap: fix visibility of omap2_mbox_iva_priv
In-Reply-To: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <1332522836-29517-3-git-send-email-mathieu.poirier@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

map2_mbox_iva_priv is used on multiple omap2 socs but is hidden
in an outdated #ifdef that is specific to a single soc.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/mailbox.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 415a6f1..ef01f6c 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -258,7 +258,7 @@ struct omap_mbox mbox_dsp_info = {
 struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
 #endif
 
-#if defined(CONFIG_SOC_OMAP2420)
+#if defined(CONFIG_ARCH_OMAP2)
 /* IVA */
 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
 	.tx_fifo = {
-- 
1.7.5.4



From mathieu.poirier at linaro.org  Fri Mar 23 13:13:51 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Fri, 23 Mar 2012 11:13:51 -0600
Subject: [PATCH 4/9] ARM: omap2+: fix building without i2c
In-Reply-To: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <1332522836-29517-5-git-send-email-mathieu.poirier@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

A trivial typo causes build breakage when I2C is disabled
and omap_i2c_reset is set to NULL on OMAP:

omap_hwmod_44xx_data.c:2287:11: error: lvalue required as unary '&' operand

Removing the '&' character solves this.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Cc: Avinash.H.M <avinashhm at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |    2 +-
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |    2 +-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |    2 +-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a5409ce..d74c76f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -1038,7 +1038,7 @@ static struct omap_hwmod_class i2c_class = {
 	.name		= "i2c",
 	.sysc		= &i2c_sysc,
 	.rev		= OMAP_I2C_IP_VERSION_1,
-	.reset		= &omap_i2c_reset,
+	.reset		= omap_i2c_reset,
 };
 
 static struct omap_i2c_dev_attr i2c_dev_attr = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c4f56cb..69c91b3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -1088,7 +1088,7 @@ static struct omap_hwmod_class i2c_class = {
 	.name		= "i2c",
 	.sysc		= &i2c_sysc,
 	.rev		= OMAP_I2C_IP_VERSION_1,
-	.reset		= &omap_i2c_reset,
+	.reset		= omap_i2c_reset,
 };
 
 static struct omap_i2c_dev_attr i2c_dev_attr = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3c8dd92..d8eb79f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1367,7 +1367,7 @@ static struct omap_hwmod_class i2c_class = {
 	.name	= "i2c",
 	.sysc	= &i2c_sysc,
 	.rev	= OMAP_I2C_IP_VERSION_1,
-	.reset	= &omap_i2c_reset,
+	.reset	= omap_i2c_reset,
 };
 
 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ef0524c..9adf749 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2258,7 +2258,7 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
 	.name	= "i2c",
 	.sysc	= &omap44xx_i2c_sysc,
 	.rev	= OMAP_I2C_IP_VERSION_2,
-	.reset	= &omap_i2c_reset,
+	.reset	= omap_i2c_reset,
 };
 
 static struct omap_i2c_dev_attr i2c_dev_attr = {
-- 
1.7.5.4



From mathieu.poirier at linaro.org  Fri Mar 23 13:13:52 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Fri, 23 Mar 2012 11:13:52 -0600
Subject: [PATCH 5/9] tty/serial/omap: console can only be built-in
In-Reply-To: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <1332522836-29517-6-git-send-email-mathieu.poirier@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

When the omap serial driver is built as a module, we must
not allow the console driver to be selected, because consoles
can not be loadable modules.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
Acked-by: Govindraj.R <govindraj.raja at ti.com>
---
 drivers/tty/serial/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 2de9924..bcf7e24 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1041,7 +1041,7 @@ config SERIAL_OMAP
 
 config SERIAL_OMAP_CONSOLE
 	bool "Console on OMAP serial port"
-	depends on SERIAL_OMAP
+	depends on SERIAL_OMAP=y
 	select SERIAL_CORE_CONSOLE
 	help
 	  Select this option if you would like to use omap serial port as
-- 
1.7.5.4



From mathieu.poirier at linaro.org  Fri Mar 23 13:13:53 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Fri, 23 Mar 2012 11:13:53 -0600
Subject: [PATCH 6/9] omap2: select twl4030 support on boards that need it
In-Reply-To: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <1332522836-29517-7-git-send-email-mathieu.poirier@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

These three boards unconditionally use the twl4030 driver
from the board-zoom-display.c file. Make sure that the driver
is always there.
We also need to select the I2C core so we are able to build
that driver.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index e20c8ab..0279e9e 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -265,6 +265,9 @@ config MACH_OMAP_ZOOM2
 	select SERIAL_CORE_CONSOLE
 	select SERIAL_8250_CONSOLE
 	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+	select TWL4030_CORE
+	select MFD_SUPPORT
+	select I2C
 
 config MACH_OMAP_ZOOM3
 	bool "OMAP3630 Zoom3 board"
@@ -275,6 +278,9 @@ config MACH_OMAP_ZOOM3
 	select SERIAL_CORE_CONSOLE
 	select SERIAL_8250_CONSOLE
 	select REGULATOR_FIXED_VOLTAGE if REGULATOR
+	select TWL4030_CORE
+	select MFD_SUPPORT
+	select I2C
 
 config MACH_CM_T35
 	bool "CompuLab CM-T35/CM-T3730 modules"
@@ -316,6 +322,9 @@ config MACH_OMAP_3630SDP
 	depends on ARCH_OMAP3
 	default y
 	select OMAP_PACKAGE_CBP
+	select TWL4030_CORE
+	select MFD_SUPPORT
+	select I2C
 
 config MACH_TI8168EVM
 	bool "TI8168 Evaluation Module"
-- 
1.7.5.4



From mathieu.poirier at linaro.org  Fri Mar 23 13:13:50 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Fri, 23 Mar 2012 11:13:50 -0600
Subject: [PATCH 3/9] ARM: omap2/n8x0: work around modular omap mmc
In-Reply-To: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <1332522836-29517-4-git-send-email-mathieu.poirier@linaro.org>

From: Russell King <linux at arm.linux.org.uk>

When the omap driver is built as a module for n8x0,
n8x0_mmc_set_power_menelaus cannot call into the driver:

arch/arm/mach-omap2/board-n8x0.c:374: undefined reference
to `omap_mmc_notify_cover_event'

As a workaround, do not provide that device in this case. This needs
to be fixed properly, e.g. by converting n8x0 to be probed through the
device tree and moving that code into the driver.

Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
Suggested-by: Russell King <linux at arm.linux.org.uk>
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-n8x0.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 6722627..8529ca0 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -193,8 +193,10 @@ static struct omap_onenand_platform_data board_onenand_data[] = {
 };
 #endif
 
-#if defined(CONFIG_MENELAUS) &&						\
-	(defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
+#ifdef CONFIG_MMC_OMAP_MODULE
+#warning FIXME: cannot call omap_mmc_notify_cover_event for CONFIG_MMC_OMAP_MODULE
+#endif
+#if defined(CONFIG_MENELAUS) && (defined(CONFIG_MMC_OMAP)
 
 /*
  * On both N800 and N810, only the first of the two MMC controllers is in use.
-- 
1.7.5.4



From mathieu.poirier at linaro.org  Fri Mar 23 13:13:54 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Fri, 23 Mar 2012 11:13:54 -0600
Subject: [PATCH 7/9] omap2plus: ensure that one of omap2/3/4 is selected
In-Reply-To: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <1332522836-29517-8-git-send-email-mathieu.poirier@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

Random configurations can fail if none of the omap families
in mach-omap2 is selected. This patch automatically selects
omap2 if the user has not made any other choice.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 0279e9e..b244e80 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -55,6 +55,16 @@ config ARCH_OMAP4
 	select USB_ARCH_HAS_EHCI
 	select ARM_CPU_SUSPEND if PM
 
+config ARCH_OMAP2_AUTO
+	bool
+	depends on !ARCH_OMAP3 && !ARCH_OMAP4
+	select ARCH_OMAP2
+	default y
+	help
+	  At least one of OMAP2/OMAP3/OMAP4 needs to be enabled, this
+	  selects OMAP2 if nothing else gets selected, to avoid non-building
+	  configurations.
+
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
 
-- 
1.7.5.4



From mathieu.poirier at linaro.org  Fri Mar 23 13:13:55 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Fri, 23 Mar 2012 11:13:55 -0600
Subject: [PATCH 8/9] arm: OMAP depends on MMU
In-Reply-To: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <1332522836-29517-9-git-send-email-mathieu.poirier@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

There is no way to build OMAP kernels without an MMU
at this point because of dependencies on MMU-only functions.

As long as nobody is interested in fixing this, let's just disable
this platforms for nommu kernels.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dfb0312..8124ce0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -939,6 +939,7 @@ config ARCH_DAVINCI
 
 config ARCH_OMAP
 	bool "TI OMAP"
+	depends on MMU
 	select HAVE_CLK
 	select ARCH_REQUIRE_GPIOLIB
 	select ARCH_HAS_CPUFREQ
-- 
1.7.5.4



From mathieu.poirier at linaro.org  Fri Mar 23 13:13:56 2012
From: mathieu.poirier at linaro.org (mathieu.poirier at linaro.org)
Date: Fri, 23 Mar 2012 11:13:56 -0600
Subject: [PATCH 9/9] ARM: omap: select CPU_FREQ_TABLE where needed
In-Reply-To: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <1332522836-29517-10-git-send-email-mathieu.poirier@linaro.org>

From: Arnd Bergmann <arnd at arndb.de>

The omap platform requires CPU_FREQ_TABLE support to be enabled for its
CPU_FREQ implementations, so automatically select that when CPU_FREQ
is enabled.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
---
 arch/arm/plat-omap/Kconfig |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index aa59f42..1983d16 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -207,6 +207,11 @@ config OMAP_PM_NOOP
 
 endchoice
 
+config OMAP_CPU_FREQ
+	def_bool "y"
+	depends on CPU_FREQ
+	select CPU_FREQ_TABLE
+
 endmenu
 
 endif
-- 
1.7.5.4



From dongas86 at gmail.com  Fri Mar 23 13:21:38 2012
From: dongas86 at gmail.com (Dong Aisheng)
Date: Sat, 24 Mar 2012 01:21:38 +0800
Subject: [PATCH v2 1/1] ARM: imx28: add basic dt support
In-Reply-To: <201203231543.54588.marek.vasut@gmail.com>
References: <1332513070-5400-1-git-send-email-b29396@freescale.com>
 <201203231543.54588.marek.vasut@gmail.com>
Message-ID: <CAA+hA=RV=pfAUT5Q+kXe5WXwwKx5kgAAaV+e9F5heCCBC=HoSQ@mail.gmail.com>

Hi Marek,

On Fri, Mar 23, 2012 at 10:43 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dear Dong Aisheng,
>
>> From: Dong Aisheng <dong.aisheng at linaro.org>
>>
>> This patch includes basic dt support which can boot via nfs rootfs.
>>
>> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
>> ---
>> ChangeLog v1->v2:
>> ?* Some fixes addressed Rob's review comments.
>> ? ?Remove using of OF_DEV_AUXDATA.
>> ?* Remove mac address from dts file
>> ? ?Currently we use the mac address got from uboot to work.
>> ? ?Will submit a p separate atch using prom_update_property to fix this
>> ? ?issue for driver based on suggestions from Grant and Lothar.
>> ?* rename mxs-dt.c to mach-mxs.c which is supposed to support mx23 dt
>> ? ?too in the future.
>> ?* add compatible string "fsl,imx28" per Sascha's suggestion
>> ?* add more devices in dtsi file
>> ? ?For those devices still not in use, set the state to "disabled"
>> ? ?by default.
>>
>> For other patches i sent with this in the first series like mmc and sdma
>> dt support, i will send out them separately since this patch does not
>> depend on them and does not block you to run dt via nfs rootfs.
>> ---
>> ?Documentation/devicetree/bindings/arm/fsl.txt | ? ?4 +
>> ?arch/arm/boot/dts/imx28-evk.dts ? ? ? ? ? ? ? | ? 35 +++
>
> Isn't this supposed to be "mx28evk.dts"?
>
I just keep consistent with other existing imx dts file like imx6q-arm2.dts.

>> ?arch/arm/boot/dts/imx28.dtsi ? ? ? ? ? ? ? ? ?| ?358
>> +++++++++++++++++++++++++ arch/arm/mach-mxs/Kconfig ? ? ? ? ? ? ? ? ? ? |
>> ? 8 +
>> ?arch/arm/mach-mxs/Makefile ? ? ? ? ? ? ? ? ? ?| ? ?1 +
>> ?arch/arm/mach-mxs/clock-mx28.c ? ? ? ? ? ? ? ?| ? ?4 +
>> ?arch/arm/mach-mxs/mach-mxs.c ? ? ? ? ? ? ? ? ?| ? 69 +++++
>> ?7 files changed, 479 insertions(+), 0 deletions(-)
>> ?create mode 100644 arch/arm/boot/dts/imx28-evk.dts
>> ?create mode 100644 arch/arm/boot/dts/imx28.dtsi
>> ?create mode 100644 arch/arm/mach-mxs/mach-mxs.c
>>
>> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
>> b/Documentation/devicetree/bindings/arm/fsl.txt index 54bddda..9f21faf
>> 100644
>> --- a/Documentation/devicetree/bindings/arm/fsl.txt
>> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
>> @@ -1,6 +1,10 @@
>> ?Freescale i.MX Platforms Device Tree Bindings
>> ?-----------------------------------------------
>>
>> +i.MX28 Evaluation Kit
>> +Required root node properties:
>> + ? ?- compatible = "fsl,imx28-evk", "fsl,imx28";
>> +
>> ?i.MX51 Babbage Board
>> ?Required root node properties:
>> ? ? ?- compatible = "fsl,imx51-babbage", "fsl,imx51";
>> diff --git a/arch/arm/boot/dts/imx28-evk.dts
>> b/arch/arm/boot/dts/imx28-evk.dts new file mode 100644
>> index 0000000..5402495
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx28-evk.dts
>> @@ -0,0 +1,35 @@
>> +/*
>> + * Copyright 2012 Freescale Semiconductor, Inc.
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +/dts-v1/;
>> +/include/ "imx28.dtsi"
>> +
>> +/ {
>> + ? ? model = "Freescale i.MX28 Evaluation Kit";
>> + ? ? compatible = "fsl,imx28-evk", "fsl,imx28";
>> +
>> + ? ? memory {
>> + ? ? ? ? ? ? device_type = "memory";
>> + ? ? ? ? ? ? reg = <0x40000000 0x08000000>;
>> + ? ? };
>> +
>> + ? ? ahb at 80080000 {
>> + ? ? ? ? ? ? ethernet at 800f0000 {
>
> fec at ... would be more readable, but I think this was decided before to be like
> this?
>
Yes.

>> + ? ? ? ? ? ? ? ? ? ? phy-mode = "rmii";
>> + ? ? ? ? ? ? ? ? ? ? status = "okay";
>> + ? ? ? ? ? ? };
>> +
>
> [...]
>
>> diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
>> index 908bf9a..8328c45 100644
>> --- a/arch/arm/mach-mxs/Makefile
>> +++ b/arch/arm/mach-mxs/Makefile
>> @@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
>> ?obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
>> ?obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
>>
>> +obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
>> ?obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
>> ?obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
>> ?obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
>> diff --git a/arch/arm/mach-mxs/clock-mx28.c
>> b/arch/arm/mach-mxs/clock-mx28.c index 5d68e41..88ed30c 100644
>> --- a/arch/arm/mach-mxs/clock-mx28.c
>> +++ b/arch/arm/mach-mxs/clock-mx28.c
>> @@ -671,6 +671,10 @@ static struct clk_lookup lookups[] = {
>> ? ? ? _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
>> ? ? ? _REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
>> ? ? ? _REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
>> + ? ? /* for DT */
>> + ? ? _REGISTER_CLOCK("80074000.serial", NULL, uart_clk)
>> + ? ? _REGISTER_CLOCK("800f0000.ethernet", NULL, fec_clk)
>> + ? ? _REGISTER_CLOCK("800f4000.ethernet", NULL, fec_clk)
>
> Wasn't the DT stuff supposed to be more symbolic? Aka. this seems weird.
>
Sorry, i'm not quite understand.
What's your suggestion to change?

Regards
Dong Aisheng


From tony at atomide.com  Fri Mar 23 13:22:17 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 23 Mar 2012 10:22:17 -0700
Subject: [PATCH 4/9] ARM: omap2+: fix building without i2c
In-Reply-To: <1332522836-29517-5-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
 <1332522836-29517-5-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <20120323172216.GB9859@atomide.com>

* mathieu.poirier at linaro.org <mathieu.poirier at linaro.org> [120323 10:16]:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> A trivial typo causes build breakage when I2C is disabled
> and omap_i2c_reset is set to NULL on OMAP:
> 
> omap_hwmod_44xx_data.c:2287:11: error: lvalue required as unary '&' operand
> 
> Removing the '&' character solves this.

We are now building in the omap_i2c_reset always, so this
should be revalidated. We currently don't have NULL version
of omap_i2c_reset any longer, so those '&' for functions are
mostly cosmetic right now.

Anyways, at least the commit message should be changed to
be current.

Regards,

Tony


From tony at atomide.com  Fri Mar 23 13:28:45 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 23 Mar 2012 10:28:45 -0700
Subject: [PATCH 7/9] omap2plus: ensure that one of omap2/3/4 is selected
In-Reply-To: <1332522836-29517-8-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
 <1332522836-29517-8-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <20120323172845.GC9859@atomide.com>

* mathieu.poirier at linaro.org <mathieu.poirier at linaro.org> [120323 10:16]:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> Random configurations can fail if none of the omap families
> in mach-omap2 is selected. This patch automatically selects
> omap2 if the user has not made any other choice.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Acked-by: Tony Lindgren <tony at atomide.com>
> ---
>  arch/arm/mach-omap2/Kconfig |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 0279e9e..b244e80 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -55,6 +55,16 @@ config ARCH_OMAP4
>  	select USB_ARCH_HAS_EHCI
>  	select ARM_CPU_SUSPEND if PM
>  
> +config ARCH_OMAP2_AUTO
> +	bool
> +	depends on !ARCH_OMAP3 && !ARCH_OMAP4
> +	select ARCH_OMAP2
> +	default y
> +	help
> +	  At least one of OMAP2/OMAP3/OMAP4 needs to be enabled, this
> +	  selects OMAP2 if nothing else gets selected, to avoid non-building
> +	  configurations.
> +
>  comment "OMAP Core Type"
>  	depends on ARCH_OMAP2

Hmm yeah omap2 makes the smallest build, so randconfig builds
faster than it would for omap3 or 4.

But isn't there now still a chance that randconfig does not
select ARCH_OMAP2_AUTO either?

Regards,

Tony


From tony at atomide.com  Fri Mar 23 13:29:54 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 23 Mar 2012 10:29:54 -0700
Subject: [PATCH 3/9] ARM: omap2/n8x0: work around modular omap mmc
In-Reply-To: <1332522836-29517-4-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
 <1332522836-29517-4-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <20120323172953.GD9859@atomide.com>

* mathieu.poirier at linaro.org <mathieu.poirier at linaro.org> [120323 10:16]:
> From: Russell King <linux at arm.linux.org.uk>
> 
> When the omap driver is built as a module for n8x0,
> n8x0_mmc_set_power_menelaus cannot call into the driver:
> 
> arch/arm/mach-omap2/board-n8x0.c:374: undefined reference
> to `omap_mmc_notify_cover_event'
> 
> As a workaround, do not provide that device in this case. This needs
> to be fixed properly, e.g. by converting n8x0 to be probed through the
> device tree and moving that code into the driver.

This too should be fixed now in a way where just the cover events
won't work if compiled as a module.

Regards,

Tony


From will.deacon at arm.com  Fri Mar 23 13:30:55 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 23 Mar 2012 17:30:55 +0000
Subject: ARM11MPcore: tlb_ops_need_broadcast causes deadlock
In-Reply-To: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
References: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
Message-ID: <20120323173055.GC16225@mudshark.cambridge.arm.com>

Hi Peter,

Thanks for the detailed explanation. However, there's one bit I'm not sure
that I follow:

On Thu, Mar 22, 2012 at 12:24:47PM +0000, EXTERNAL Waechtler Peter (Fa. TCP, CM-AI/PJ-CF31) wrote:
> The cpuB executes some user code hitting that page and because the PTE
> is marked "inaccessible", so that the attempt can be stored, it results
> in a page fault.

Shouldn't this trigger a prefetch abort rather than a data abort?

> Unluckily the kswapd calls tlb_flush and that is configured to inform all
> cpus about that change via IPIs. cpuB is in an user abort handler (__dabt_usr)
> and the disaster takes its course:
> 
> For checking if it's a thumb instruction that caused the fault the abort handler
> accesses the page resulting into another fault - but now entering svc abort handler
> (__dabt_svc) and that turns off interrupts!

This is where I'm confused - why are we in the data abort handler due to an
I-side fault?

Thanks,

Will


From arnd at arndb.de  Fri Mar 23 13:38:05 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 23 Mar 2012 17:38:05 +0000
Subject: [PATCH 7/9] omap2plus: ensure that one of omap2/3/4 is selected
In-Reply-To: <20120323172845.GC9859@atomide.com>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
 <1332522836-29517-8-git-send-email-mathieu.poirier@linaro.org>
 <20120323172845.GC9859@atomide.com>
Message-ID: <201203231738.05742.arnd@arndb.de>

On Friday 23 March 2012, Tony Lindgren wrote:
> >  
> > +config ARCH_OMAP2_AUTO
> > +     bool
> > +     depends on !ARCH_OMAP3 && !ARCH_OMAP4
> > +     select ARCH_OMAP2
> > +     default y
> > +     help
> > +       At least one of OMAP2/OMAP3/OMAP4 needs to be enabled, this
> > +       selects OMAP2 if nothing else gets selected, to avoid non-building
> > +       configurations.
> > +
> >  comment "OMAP Core Type"
> >       depends on ARCH_OMAP2
> 
> Hmm yeah omap2 makes the smallest build, so randconfig builds
> faster than it would for omap3 or 4.
> 
> But isn't there now still a chance that randconfig does not
> select ARCH_OMAP2_AUTO either?

No. ARCH_OMAP2_AUTO is only disabled if one of OMAP3 or OMAP4
are enabled.

	Arnd


From alexgershgorin at gmail.com  Fri Mar 23 14:11:07 2012
From: alexgershgorin at gmail.com (Alex Gershgorin)
Date: Fri, 23 Mar 2012 20:11:07 +0200
Subject: [PATCH] regulator: i.MX35-PDK Add regulator support
Message-ID: <1332526267-3236-1-git-send-email-alexg@meprolight.com>

From: Alex <alexg at meprolight.com>

Hi Marc,

Thanks for the patches.

v4 3/4 not directly applicable to Linux version 3.3,
I installed it manually, you could check it out?

> > I'm not very experienced with the regulator driver, but noticed a couple of 
> > minor things with your patch...

I think that my experience in the regulator driver a little less than you :-)

>  static struct resource mx35pdk_flash_resource = {
>  	.start	= MX35_CS0_BASE_ADDR,
> -	.end	= MX35_CS0_BASE_ADDR + SZ_64M - 1,
> +	.end    = MX35_CS0_BASE_ADDR + SZ_64M - 1,

> > did you mean to change this?

No, I will correct this.

> +static struct regulator_init_data vsd_init = {
> +	.constraints = {
> +		.name = "VSD",
> +		.min_uV = 1800000,
> +		.max_uV = 3150000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +	}
> +};

> > I think this is on at power up too (for imx35)

Maybe you're right, but in this case, the i.MX35 PDK
Do not use PMIC "VSD" regulator, but instead it is used 
a different power source.
I think it can be removed from here :-)


Regards,
Alex Gershgorin






From tony at atomide.com  Fri Mar 23 14:14:56 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 23 Mar 2012 11:14:56 -0700
Subject: [PATCH 7/9] omap2plus: ensure that one of omap2/3/4 is selected
In-Reply-To: <201203231738.05742.arnd@arndb.de>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
 <1332522836-29517-8-git-send-email-mathieu.poirier@linaro.org>
 <20120323172845.GC9859@atomide.com>
 <201203231738.05742.arnd@arndb.de>
Message-ID: <20120323181455.GE9859@atomide.com>

* Arnd Bergmann <arnd at arndb.de> [120323 10:40]:
> On Friday 23 March 2012, Tony Lindgren wrote:
> > >  
> > > +config ARCH_OMAP2_AUTO
> > > +     bool
> > > +     depends on !ARCH_OMAP3 && !ARCH_OMAP4
> > > +     select ARCH_OMAP2
> > > +     default y
> > > +     help
> > > +       At least one of OMAP2/OMAP3/OMAP4 needs to be enabled, this
> > > +       selects OMAP2 if nothing else gets selected, to avoid non-building
> > > +       configurations.
> > > +
> > >  comment "OMAP Core Type"
> > >       depends on ARCH_OMAP2
> > 
> > Hmm yeah omap2 makes the smallest build, so randconfig builds
> > faster than it would for omap3 or 4.
> > 
> > But isn't there now still a chance that randconfig does not
> > select ARCH_OMAP2_AUTO either?
> 
> No. ARCH_OMAP2_AUTO is only disabled if one of OMAP3 or OMAP4
> are enabled.

And then no description in bool keeps it hidden from selection.
Nice, this works. Too bad these got forgotten in your branch.

Regards,

Tony


From tony at atomide.com  Fri Mar 23 14:27:46 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 23 Mar 2012 11:27:46 -0700
Subject: [PATCH 9/9] ARM: omap: select CPU_FREQ_TABLE where needed
In-Reply-To: <1332522836-29517-10-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
 <1332522836-29517-10-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <20120323182746.GF9859@atomide.com>

* mathieu.poirier at linaro.org <mathieu.poirier at linaro.org> [120323 10:17]:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> The omap platform requires CPU_FREQ_TABLE support to be enabled for its
> CPU_FREQ implementations, so automatically select that when CPU_FREQ
> is enabled.

I think this is also solved now, Kevin might be able to confirm this.

Regards,

Tony
 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
> ---
>  arch/arm/plat-omap/Kconfig |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
> index aa59f42..1983d16 100644
> --- a/arch/arm/plat-omap/Kconfig
> +++ b/arch/arm/plat-omap/Kconfig
> @@ -207,6 +207,11 @@ config OMAP_PM_NOOP
>  
>  endchoice
>  
> +config OMAP_CPU_FREQ
> +	def_bool "y"
> +	depends on CPU_FREQ
> +	select CPU_FREQ_TABLE
> +
>  endmenu
>  
>  endif
> -- 
> 1.7.5.4
> 


From jonsmirl at gmail.com  Fri Mar 23 14:28:28 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Fri, 23 Mar 2012 14:28:28 -0400
Subject: ioremap to a specific virtual address
In-Reply-To: <201203231520.22588.arnd@arndb.de>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <201203231407.00686.arnd@arndb.de>
 <CAKON4OzF9KV=51yAR2pVHJZNQsGDkXVhBwbn4njhZPRjeh=-dA@mail.gmail.com>
 <201203231520.22588.arnd@arndb.de>
Message-ID: <CAKON4OybXXwLEmg19NJnLsE5kB16U6Dm4ay3=XCUB57fRfz+ng@mail.gmail.com>

On Fri, Mar 23, 2012 at 11:20 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 23 March 2012, jonsmirl at gmail.com wrote:
>> I will need to check how similar the chips actually are. NXP did not
>> use primecells in the lpc31xx family.
>>
>> I'd be happy to have some help. My trees are here:
>> https://github.com/jonsmirl
>
> I've taken a brief look at your tree, some comments:
>
> * Once you're done with the DT conversion, you should be able to
> ?completely remvoe the three board files. You probably know that already

Thanks for the feedback.

I don't think I can completely remove the board files. Some of the
generic devices have board specific callbacks. DM9000 for example. I
am setting up of_dev_auxdata for the boards so that I can pass these
callbacks in.

# define DM_IO_DELAY()	do { gpio_get_value(GPIO_MNAND_RYBN3);} while(0)

static void dm9000_dumpblk(void __iomem *reg, int count)
{
	int i;
	int tmp;

	count = (count + 1) >> 1;
	for (i = 0; i < count; i++) {
		DM_IO_DELAY();
		tmp = readw(reg);
	}
}

static void dm9000_inblk(void __iomem *reg, void *data, int count)
{
	int i;
	u16* pdata = (u16*)data;
	count = (count + 1) >> 1;
	for (i = 0; i < count; i++) {
		DM_IO_DELAY();
		*pdata++ = readw(reg);
	}
}

static struct dm9000_plat_data dm9000_platdata = {
	.flags		= DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM |
DM9000_PLATF_SIMPLE_PHY,
	.dumpblk = dm9000_dumpblk,
	.inblk = dm9000_inblk,
};

>
> * We're merging the new common clock framework in v3.4. Once that has
> ?matured, all new platforms will be required to use it. You should probably
> ?move to that already.
>
> * The dma driver uses a nonstandard interface and should be moved to
> ?drivers/dma, using the dmaengine API.
>
> * The __REG needs to be removed. All MMIO register accesses should go
> ?through readl/writel or readl_relaxed/writel_relaxed, using a pointer
> ?you get from ioremap.
>
> * gpio*.c should get moved to drivers/gpio/gpio-lpc31xx. If it's similar
> ?to the 32xx version, merge the two
>
> * i2c.c should no longer be needed with the device tree, but you might
> ?have to add stuff to i2c-pnx.c. That file is shared with pnx4008 and
> ?lpc32xx.
>
> * irq.c will eventually go to drivers/irqchip/. We have a plan to create
> ?that directory, but nobody has started moving drivers there.
>
> * Some of the header files have been removed on other platforms, you
> ?should do the same.
>
> * Regarding the static mappings, it certainly makes sense to map all of
> ?ABP01_PHYS and IO_APB2_PHYS using 1MB mappings, for performance reasons,
> ?and I guess you need INTC_PHYS to be mapped, too, for the interrupt
> ?controller code to work. However, none of the drivers should be aware
> ?of this and just call ioremap anyway, which will now return an address
> ?from the static mapping.
>
> ? ? ? ?Arnd



-- 
Jon Smirl
jonsmirl at gmail.com


From tony at atomide.com  Fri Mar 23 14:30:59 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 23 Mar 2012 11:30:59 -0700
Subject: [PATCH 2/9] omap: fix visibility of omap2_mbox_iva_priv
In-Reply-To: <1332522836-29517-3-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
 <1332522836-29517-3-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <20120323183057.GG9859@atomide.com>

* mathieu.poirier at linaro.org <mathieu.poirier at linaro.org> [120323 10:16]:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> map2_mbox_iva_priv is used on multiple omap2 socs but is hidden
> in an outdated #ifdef that is specific to a single soc.

I think this got fixed with 655850ed (ARM: OMAP2: fix mailbox init code).

Tony


From tony at atomide.com  Fri Mar 23 14:33:39 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 23 Mar 2012 11:33:39 -0700
Subject: [PATCH 5/9] tty/serial/omap: console can only be built-in
In-Reply-To: <1332522836-29517-6-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
 <1332522836-29517-6-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <20120323183339.GH9859@atomide.com>

* mathieu.poirier at linaro.org <mathieu.poirier at linaro.org> [120323 10:16]:
> From: Arnd Bergmann <arnd at arndb.de>
> 
> When the omap serial driver is built as a module, we must
> not allow the console driver to be selected, because consoles
> can not be loadable modules.

Looks valid to me, this should get posted and merged via
linux-serial at vger.kernel.org.

Tony

> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
> Acked-by: Govindraj.R <govindraj.raja at ti.com>
> ---
>  drivers/tty/serial/Kconfig |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
> index 2de9924..bcf7e24 100644
> --- a/drivers/tty/serial/Kconfig
> +++ b/drivers/tty/serial/Kconfig
> @@ -1041,7 +1041,7 @@ config SERIAL_OMAP
>  
>  config SERIAL_OMAP_CONSOLE
>  	bool "Console on OMAP serial port"
> -	depends on SERIAL_OMAP
> +	depends on SERIAL_OMAP=y
>  	select SERIAL_CORE_CONSOLE
>  	help
>  	  Select this option if you would like to use omap serial port as
> -- 
> 1.7.5.4
> 


From matt at grid-net.com  Fri Mar 23 14:38:41 2012
From: matt at grid-net.com (Matt Burtch)
Date: Fri, 23 Mar 2012 11:38:41 -0700
Subject: [PATCH 1/1] ARM iMX28: incorrect frac/div calculation
In-Reply-To: <20120323025208.GG2213@S2101-09.ap.freescale.net>
References: <1332457501-8153-1-git-send-email-matt@grid-net.com>
 <20120323025208.GG2213@S2101-09.ap.freescale.net>
Message-ID: <4F6CC331.20505@grid-net.com>

On 03/22/2012 07:52 PM, Shawn Guo wrote:
> On Thu, Mar 22, 2012 at 04:05:01PM -0700, Matt Burtch wrote:
>> The frac and div values in _CLK_SET_RATE are calculated incorrectly
>> for some clock rates ie. CPU clk of 454.73MHz, 392.72MHz, 261.81Mhz,
>> etc.
>>
>> Now the frac and div values which result in the closest actual clock
>> rate to that requested is selected.
> My understanding on clk_set_rate is we need to set the clk to a rate
> closest to the requested one but never exceeding it.  Does your change
> ensure that?
>
> Regards,
> Shawn

It currently doesn't check that the resultant clock is lower than the 
requested.  I can certainly make that change and resubmit.  I wasn't 
aware of this requirement.

So with the patch as it stands, if you request a CPU clock of 391Mhz, 
it'll give you 392.71MHz. Would it be correct for the clock to be set at 
375.65MHz (the next closest valid clock rate without going over)?

Thanks,
Matt

>> Also there are no limitations
>> on what frac values can be used, as long as they fall in the valid
>> (18<  frac<  35) range.
>>
>> Tested on custom iMX28 board.
>>
>> Signed-off-by: Matt Burtch<matt at grid-net.com>
>> ---
>>   arch/arm/mach-mxs/clock-mx28.c |    8 ++------
>>   1 files changed, 2 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
>> index 5d68e41..a058b99 100644
>> --- a/arch/arm/mach-mxs/clock-mx28.c
>> +++ b/arch/arm/mach-mxs/clock-mx28.c
>> @@ -354,19 +354,15 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
>>   		}							\
>>   		for (d = 1; d<= div_max; d++) {			\
>>   			f = parent_rate * 18 / d / rate;		\
>> -			if ((parent_rate * 18 / d) % rate)		\
>> -				f++;					\
>>   			if (f<  18 || f>  35)				\
>>   				continue;				\
>>   									\
>>   			calc_rate = parent_rate * 18 / f / d;		\
>> -			if (calc_rate>  rate)				\
>> -				continue;				\
>>   									\
>> -			if (rate - calc_rate<  diff) {			\
>> +			if (abs(rate - calc_rate)<  diff) {		\
>>   				frac = f;				\
>>   				div = d;				\
>> -				diff = rate - calc_rate;		\
>> +				diff = abs(rate - calc_rate);		\
>>   			}						\
>>   									\
>>   			if (diff == 0)					\
>> -- 
>> 1.7.5.4
>>




From matt at grid-net.com  Fri Mar 23 14:38:58 2012
From: matt at grid-net.com (Matt Burtch)
Date: Fri, 23 Mar 2012 11:38:58 -0700
Subject: [PATCH 1/1] ARM iMX28: incorrect frac/div calculation
In-Reply-To: <20332.8856.841320.610752@ipc1.ka-ro>
References: <1332457501-8153-1-git-send-email-matt@grid-net.com>
 <20332.8856.841320.610752@ipc1.ka-ro>
Message-ID: <4F6CC342.4010609@grid-net.com>

On 03/23/2012 12:13 AM, Lothar Wa?mann wrote:
> Hi,
>
> Matt Burtch writes:
>> The frac and div values in _CLK_SET_RATE are calculated incorrectly
>> for some clock rates ie. CPU clk of 454.73MHz, 392.72MHz, 261.81Mhz,
>> etc.
>>
>> Now the frac and div values which result in the closest actual clock
>> rate to that requested is selected.  Also there are no limitations
>> on what frac values can be used, as long as they fall in the valid
>> (18<  frac<  35) range.
>>
>> Tested on custom iMX28 board.
>>
>> Signed-off-by: Matt Burtch<matt at grid-net.com>
>> ---
>>   arch/arm/mach-mxs/clock-mx28.c |    8 ++------
>>   1 files changed, 2 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
>> index 5d68e41..a058b99 100644
>> --- a/arch/arm/mach-mxs/clock-mx28.c
>> +++ b/arch/arm/mach-mxs/clock-mx28.c
>> @@ -354,19 +354,15 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
>>   		}							\
>>   		for (d = 1; d<= div_max; d++) {			\
>>   			f = parent_rate * 18 / d / rate;		\
>> -			if ((parent_rate * 18 / d) % rate)		\
>> -				f++;					\
>>   			if (f<  18 || f>  35)				\
>>   				continue;				\
>>   									\
>>   			calc_rate = parent_rate * 18 / f / d;		\
>> -			if (calc_rate>  rate)				\
>> -				continue;				\
>>   									\
>> -			if (rate - calc_rate<  diff) {			\
>> +			if (abs(rate - calc_rate)<  diff) {		\
> Shouldn't this actually be '<=' (also in the original code)?
Hi Lothar,

It shouldn't make a difference. If it was '<=' it would result in a 
different frac and higher div value but the difference between the 
requested rate and actual would be the same.

Thanks,
Matt Burtch
> Lothar Wa?mann




From arnd at arndb.de  Fri Mar 23 15:31:05 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 23 Mar 2012 19:31:05 +0000
Subject: ioremap to a specific virtual address
In-Reply-To: <CAKON4OybXXwLEmg19NJnLsE5kB16U6Dm4ay3=XCUB57fRfz+ng@mail.gmail.com>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <201203231520.22588.arnd@arndb.de>
 <CAKON4OybXXwLEmg19NJnLsE5kB16U6Dm4ay3=XCUB57fRfz+ng@mail.gmail.com>
Message-ID: <201203231931.06376.arnd@arndb.de>

On Friday 23 March 2012, jonsmirl at gmail.com wrote:
> On Fri, Mar 23, 2012 at 11:20 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> > On Friday 23 March 2012, jonsmirl at gmail.com wrote:
> >> I will need to check how similar the chips actually are. NXP did not
> >> use primecells in the lpc31xx family.
> >>
> >> I'd be happy to have some help. My trees are here:
> >> https://github.com/jonsmirl
> >
> > I've taken a brief look at your tree, some comments:
> >
> > * Once you're done with the DT conversion, you should be able to
> >  completely remvoe the three board files. You probably know that already
> 
> Thanks for the feedback.
> 
> I don't think I can completely remove the board files. Some of the
> generic devices have board specific callbacks. DM9000 for example. I
> am setting up of_dev_auxdata for the boards so that I can pass these
> callbacks in.

There are some cases where it's not possible to avoid platform_data,
but in most cases there is another better solution.

If you end up having to use platform_data, the auxdata mechanism
is the way to go.

> # define DM_IO_DELAY()	do { gpio_get_value(GPIO_MNAND_RYBN3);} while(0)
> 
> static void dm9000_dumpblk(void __iomem *reg, int count)
> {
> 	int i;
> 	int tmp;
> 
> 	count = (count + 1) >> 1;
> 	for (i = 0; i < count; i++) {
> 		DM_IO_DELAY();
> 		tmp = readw(reg);
> 	}
> }
> 
> static void dm9000_inblk(void __iomem *reg, void *data, int count)
> {
> 	int i;
> 	u16* pdata = (u16*)data;
> 	count = (count + 1) >> 1;
> 	for (i = 0; i < count; i++) {
> 		DM_IO_DELAY();
> 		*pdata++ = readw(reg);
> 	}
> }
> 
> static struct dm9000_plat_data dm9000_platdata = {
> 	.flags		= DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM |
> DM9000_PLATF_SIMPLE_PHY,

The flags can become simple empty properties if necessary, so there is no
need to keep these.

> 	.dumpblk = dm9000_dumpblk,
> 	.inblk = dm9000_inblk,
> };

I can see two possible ways besides platform_data for the register access:

1. generalize the driver's accessors. Since your platform wants to read
a gpio pin before every access, you can provide a gpio line as the
property in the dm9000 device node and access that in the same place
in the common code if the gpio line is set, but skip the access otherwise.
No other platform in mainline actually needs to overrid the functions,
so there are hardly any disadvantages to this. 

2. convert the entire driver to use the "regmap" infrastructure to abstract
the registers, and implement a driver that implements the slow I/O. This
would be a rather complex solution and probably not worth it, compared
with the overhead of the first one or just staying with auxdata.

If any problem turns out to be really hard to convert over from
platform_data to device tree properties, auxdata is usually an acceptable
solution, or you could submit the port with more of those hacks when
there is reason to believe that you will fix them up later.

	Arnd


From tsoni at codeaurora.org  Fri Mar 23 16:22:05 2012
From: tsoni at codeaurora.org (Trilok Soni)
Date: Sat, 24 Mar 2012 01:52:05 +0530
Subject: [PATCH v3 1/1] rc: Add support for GPIO based IR Receiver driver.
In-Reply-To: <4F5070A0.9070609@codeaurora.org>
References: <1330408300-21939-1-git-send-email-kumarrav@codeaurora.org>
 <20120228202944.GA9373@balrog> <4F4E1911.5050208@codeaurora.org>
 <4F5070A0.9070609@codeaurora.org>
Message-ID: <4F6CDB6D.9030801@codeaurora.org>

Hi Mauro,

>>>
>>
>> Please review this patch.
>>
>> Thank you James for the review comments.
>
> Please review and check if this patch can be merged in your tree.
>

Sorry to ping you again, but I am bit curious due to open merge window, 
if would be good if this patch can make it into the mainline by this 
merge window if it looks good. Thanks.

---Trilok Soni

-- 
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From festevam at gmail.com  Fri Mar 23 16:37:26 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 23 Mar 2012 17:37:26 -0300
Subject: [PATCH v1] i.MX35-PDK: Add Camera support
In-Reply-To: <1332529371-3994-1-git-send-email-alexg@meprolight.com>
References: <1332529371-3994-1-git-send-email-alexg@meprolight.com>
Message-ID: <CAOMZO5Cf11Z3JNnsDU2c1YX5Fh=4qznc+26xndKHB1wQMDMu_g@mail.gmail.com>

Hi Alex,

On Fri, Mar 23, 2012 at 4:02 PM, Alex Gershgorin
<alexgershgorin at gmail.com> wrote:
> Yes, yesterday I sended to Sascha and ARM mailing list another patch
> i.MX35-PDK-Add-regulator-support, this also will need be used.

Ok, good. I saw that patch as well.

It would be really nice if you could fix the I2C issues you reported
earlier in software.

Otherwise the camera will only work on your own modified mx35pdk ;-)

Regards,

Fabio Estevam


From skannan at codeaurora.org  Fri Mar 23 17:33:00 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Fri, 23 Mar 2012 14:33:00 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <4F6946AA.4070201@codeaurora.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
 <4F6946AA.4070201@codeaurora.org>
Message-ID: <4F6CEC0C.4060704@codeaurora.org>

On 03/20/2012 08:10 PM, Saravana Kannan wrote:
> On 03/20/2012 04:53 PM, Turquette, Mike wrote:
>> It does make me
>> wonder if it would be a good idea to pass in the parent rate for
>> .set_parent, which is analogous to .set_rate in many ways.
>
> I need to think a bit more about this.

I was thinking about this. I think the common clock fwk should let the 
set_parent ops "return" the rate of the clock in addition to passing the 
rate of the parent in.

Say this is a divider clock and some one changes the parent. The cached 
"rate" of the clock in the clock fwk is no longer correct. So, the clock 
fwk should also add a "*new_rate" param to set parent ops.

Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From torvalds at linux-foundation.org  Fri Mar 23 17:35:48 2012
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Fri, 23 Mar 2012 14:35:48 -0700
Subject: [GIT PULL] DMA-mapping framework updates for 3.4
In-Reply-To: <1332228283-29077-1-git-send-email-m.szyprowski@samsung.com>
References: <1332228283-29077-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <CA+55aFy9oxMrfm-+deMqV=XnFOa98aKXqW+8PR-P-zOARtC2BQ@mail.gmail.com>

On Tue, Mar 20, 2012 at 12:24 AM, Marek Szyprowski
<m.szyprowski at samsung.com> wrote:
>
> ?git://git.infradead.org/users/kmpark/linux-samsung dma-mapping-next
>
> Those patches introduce a new alloc method (with support for memory
> attributes) in dma_map_ops structure, which will later replace
> dma_alloc_coherent and dma_alloc_writecombine functions.

So I'm quite unhappy with these patches.

Here's just the few problems I saw from some *very* quick look-through
of the git tree:

 - I'm not seeing ack's from the architecture maintainers for the
patches that change some architecture.

 - Even more importantly, what I really want is acks and comments from
the people who are expected to *use* this.

 - it looks like patches break compilation half-way through the
series. Just one example I noticed: the "x86 adaptation" patch changes
the functions in lib/swiotlb.c, but afaik ia64 *also* uses those. So
now ia64 is broken until a couple of patches later. I suspect there
are other examples like that.

 - the sign-off chains are odd. What happened there? Several patches
are signed off by Kyungmin Park, but he doesn't seem to be "in the
chain" at all. Whazzup? (*)

(Btw, I notice the same thing in the tree I pulled from Dave Airlie,
btw - what the F is going on with samsung submissions - those are
marked as committed by Dave Airlie, and don't have Dave in the
sign-off chain at all!)

 - Finally, how/why are "dma attributes" different from the per-device
dma limits ("device_dma_parameters")

Hmm?

                  Linus

(*) Btw, I notice the same thing in the tree I pulled from Dave
Airlie, btw - what the F is going on with samsung submissions - those
are marked as committed by Dave Airlie, and don't have Dave in the
sign-off chain at all! Dave?


From mturquette at ti.com  Fri Mar 23 17:39:53 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 23 Mar 2012 14:39:53 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <4F6CEC0C.4060704@codeaurora.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
 <4F6946AA.4070201@codeaurora.org> <4F6CEC0C.4060704@codeaurora.org>
Message-ID: <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>

On Fri, Mar 23, 2012 at 2:33 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
> On 03/20/2012 08:10 PM, Saravana Kannan wrote:
>>
>> On 03/20/2012 04:53 PM, Turquette, Mike wrote:
>>>
>>> It does make me
>>> wonder if it would be a good idea to pass in the parent rate for
>>> .set_parent, which is analogous to .set_rate in many ways.
>>
>>
>> I need to think a bit more about this.
>
>
> I was thinking about this. I think the common clock fwk should let the
> set_parent ops "return" the rate of the clock in addition to passing the
> rate of the parent in.
>
> Say this is a divider clock and some one changes the parent. The cached
> "rate" of the clock in the clock fwk is no longer correct. So, the clock fwk
> should also add a "*new_rate" param to set parent ops.

__clk_recalc_rates is called by __clk_reparent which is called by
clk_set_parent.  __clk_recalc_rates is also called by clk_set_rate.

Does this not handle the old cached clk->rate for you?

Thanks,
Mike

>
> Thanks,
>
> Saravana
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From skannan at codeaurora.org  Fri Mar 23 17:51:20 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Fri, 23 Mar 2012 14:51:20 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
 <4F6946AA.4070201@codeaurora.org> <4F6CEC0C.4060704@codeaurora.org>
 <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>
Message-ID: <4F6CF058.5020007@codeaurora.org>

On 03/23/2012 02:39 PM, Turquette, Mike wrote:
> On Fri, Mar 23, 2012 at 2:33 PM, Saravana Kannan<skannan at codeaurora.org>  wrote:
>> On 03/20/2012 08:10 PM, Saravana Kannan wrote:
>>>
>>> On 03/20/2012 04:53 PM, Turquette, Mike wrote:
>>>>
>>>> It does make me
>>>> wonder if it would be a good idea to pass in the parent rate for
>>>> .set_parent, which is analogous to .set_rate in many ways.
>>>
>>>
>>> I need to think a bit more about this.
>>
>>
>> I was thinking about this. I think the common clock fwk should let the
>> set_parent ops "return" the rate of the clock in addition to passing the
>> rate of the parent in.
>>
>> Say this is a divider clock and some one changes the parent. The cached
>> "rate" of the clock in the clock fwk is no longer correct. So, the clock fwk
>> should also add a "*new_rate" param to set parent ops.
>
> __clk_recalc_rates is called by __clk_reparent which is called by
> clk_set_parent.  __clk_recalc_rates is also called by clk_set_rate.
>
> Does this not handle the old cached clk->rate for you?
>

Yeah, I realized this just after I sent the email. I'm looking at the 
code to see if that's sufficient or not. Will get back soon.

-Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From skannan at codeaurora.org  Fri Mar 23 18:12:37 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Fri, 23 Mar 2012 15:12:37 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
 <4F6946AA.4070201@codeaurora.org> <4F6CEC0C.4060704@codeaurora.org>
 <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>
Message-ID: <4F6CF555.4080109@codeaurora.org>

On 03/23/2012 02:39 PM, Turquette, Mike wrote:
> On Fri, Mar 23, 2012 at 2:33 PM, Saravana Kannan<skannan at codeaurora.org>  wrote:
>> On 03/20/2012 08:10 PM, Saravana Kannan wrote:
>>>
>>> On 03/20/2012 04:53 PM, Turquette, Mike wrote:
>>>>
>>>> It does make me
>>>> wonder if it would be a good idea to pass in the parent rate for
>>>> .set_parent, which is analogous to .set_rate in many ways.
>>>
>>>
>>> I need to think a bit more about this.
>>
>>
>> I was thinking about this. I think the common clock fwk should let the
>> set_parent ops "return" the rate of the clock in addition to passing the
>> rate of the parent in.
>>
>> Say this is a divider clock and some one changes the parent. The cached
>> "rate" of the clock in the clock fwk is no longer correct. So, the clock fwk
>> should also add a "*new_rate" param to set parent ops.
>
> __clk_recalc_rates is called by __clk_reparent which is called by
> clk_set_parent.  __clk_recalc_rates is also called by clk_set_rate.
>
> Does this not handle the old cached clk->rate for you?

For the set_parent case, ops->recalc_rate() is called twice. Once for 
PRE_CHANGE and once for POST_CHANGE. For this clock, I can only really 
recalc the rate during the POST_CHANGE call. So, how should I 
differentiate the two cases?

On a separate note:
Sorry if I missed any earlier discussion on this, but what's the reason 
for calling recalc_rate() pre-change and post-change but without giving 
it the ability to differentiate between the two?

I think it's quite useful for recalc_rate to be called pre/post change 
(some steps have to be done pre/post change depending on whether the 
parent rate is increasing or decreasing). But I don't see the "msg" 
being passed along.

Also, I noticed that clk_set_parent() is treating a NULL as an invalid 
clock. Should that be fixed? set_parent(NULL) could be treated as a 
grounding the clock. Should we let the ops->set_parent determine if NULL 
is valid option?

Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From mturquette at ti.com  Fri Mar 23 18:32:58 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 23 Mar 2012 15:32:58 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <4F6CF555.4080109@codeaurora.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
 <4F6946AA.4070201@codeaurora.org> <4F6CEC0C.4060704@codeaurora.org>
 <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>
 <4F6CF555.4080109@codeaurora.org>
Message-ID: <CAJOA=zOnR1NwZ1Cmkfb+b7f7=N_vg+txAUqKXF2Nf2nVYFMjjg@mail.gmail.com>

On Fri, Mar 23, 2012 at 3:12 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
> On 03/23/2012 02:39 PM, Turquette, Mike wrote:
>> __clk_recalc_rates is called by __clk_reparent which is called by
>> clk_set_parent. ?__clk_recalc_rates is also called by clk_set_rate.
>>
>> Does this not handle the old cached clk->rate for you?
>
> For the set_parent case, ops->recalc_rate() is called twice. Once for
> PRE_CHANGE and once for POST_CHANGE. For this clock, I can only really
> recalc the rate during the POST_CHANGE call. So, how should I differentiate
> the two cases?

.recalc_rate serves two purposes: first it recalculates the rate after
the rate has changed and you pass in a new parent_rate argument.  The
second purpose is to "speculate" a rate change.  You can pass in any
rate for the parent_rate parameter when you call .recalc_rates.  This
is what __speculate_rates does before the rate changes.  For
clk_set_parent we call,

__clk_speculate_rates(clk, parent->rate);

Where parent above is the *new* parent.  So this will let us propagate
pre-rate change notifiers with the new rate.

Your .recalc_rate callback doesn't need to differentiate between the
two calls to .recalc_rate.  It should just take in the parent_rate
value and do the calculation required of it.

Take a look at __clk_speculate_rates and __clk_recalc_rates and you'll
see how to use it.

> On a separate note:
> Sorry if I missed any earlier discussion on this, but what's the reason for
> calling recalc_rate() pre-change and post-change but without giving it the
> ability to differentiate between the two?

I think my answer above covers this.  The .recalc_rate callback only
exists to perform a hardware-specific calculation.  The context of
pre- or post-change is irrelevant since the parent_rate passed in
could be the actual rate of the parent or a future rate of the parent.

> I think it's quite useful for recalc_rate to be called pre/post change (some
> steps have to be done pre/post change depending on whether the parent rate
> is increasing or decreasing). But I don't see the "msg" being passed along.

What kind of steps?  Does your .recalc_rate perform these steps?  I
need more details to understand your requirements.

> Also, I noticed that clk_set_parent() is treating a NULL as an invalid
> clock. Should that be fixed? set_parent(NULL) could be treated as a
> grounding the clock. Should we let the ops->set_parent determine if NULL is
> valid option?

We must be looking at different code.  clk_set_parent doesn't return
any error if parent == NULL.  Bringing this to my attention does show
that we do deref the parent pointer without a check though...

Do you have a real use case for this?  Due to the way that we match
the parent pointer with the cached clk->parents member it would be
painful to support NULL parents as valid.

It is also worth considering whether clk_set_parent is really the
correct operation for grounding a clock.  clk_unprepare might be a
better candidate.

Regards,
Mike


From skannan at codeaurora.org  Fri Mar 23 19:04:07 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Fri, 23 Mar 2012 16:04:07 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zOnR1NwZ1Cmkfb+b7f7=N_vg+txAUqKXF2Nf2nVYFMjjg@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
 <4F6946AA.4070201@codeaurora.org> <4F6CEC0C.4060704@codeaurora.org>
 <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>
 <4F6CF555.4080109@codeaurora.org>
 <CAJOA=zOnR1NwZ1Cmkfb+b7f7=N_vg+txAUqKXF2Nf2nVYFMjjg@mail.gmail.com>
Message-ID: <4F6D0167.3040704@codeaurora.org>

On 03/23/2012 03:32 PM, Turquette, Mike wrote:
> On Fri, Mar 23, 2012 at 3:12 PM, Saravana Kannan<skannan at codeaurora.org>  wrote:
>> On 03/23/2012 02:39 PM, Turquette, Mike wrote:
>>> __clk_recalc_rates is called by __clk_reparent which is called by
>>> clk_set_parent.  __clk_recalc_rates is also called by clk_set_rate.
>>>
>>> Does this not handle the old cached clk->rate for you?
>>
>> For the set_parent case, ops->recalc_rate() is called twice. Once for
>> PRE_CHANGE and once for POST_CHANGE. For this clock, I can only really
>> recalc the rate during the POST_CHANGE call. So, how should I differentiate
>> the two cases?
>
> .recalc_rate serves two purposes: first it recalculates the rate after
> the rate has changed and you pass in a new parent_rate argument.  The
> second purpose is to "speculate" a rate change.  You can pass in any
> rate for the parent_rate parameter when you call .recalc_rates.  This
> is what __speculate_rates does before the rate changes.  For
> clk_set_parent we call,
>
> __clk_speculate_rates(clk, parent->rate);
>
> Where parent above is the *new* parent.  So this will let us propagate
> pre-rate change notifiers with the new rate.
>
> Your .recalc_rate callback doesn't need to differentiate between the
> two calls to .recalc_rate.  It should just take in the parent_rate
> value and do the calculation required of it.

Yeah, this is generally true. But, in this specific case, the clock is a 
mux that can literally measure the real rate. I would like the rate of 
this mux clock to be the real measured rate and not just the parent rate.

I could actually measure the current rate and return that for 
recalc_rate(), but then the reported rate change during the pre-change 
notification would be wrong. Having the "msg" will let us at least fake 
the rate correctly for pre change notifiers.

>> I think it's quite useful for recalc_rate to be called pre/post change (some
>> steps have to be done pre/post change depending on whether the parent rate
>> is increasing or decreasing). But I don't see the "msg" being passed along.
>
> What kind of steps?  Does your .recalc_rate perform these steps?  I
> need more details to understand your requirements.

Nevermind, my brain isn't working today. I can just do that different 
ordering in ops->set_parent(). But the measure clocks case is still true 
though.

But this did bring up another point in my head. Hopefully this one isn't 
my brain playing tricks again today.

How does a child (or grand child) clock (not a driver using the clock) 
reject a rate change if it know it can't handle that freq from the 
parent? I won't claim to know this part of the code thoroughly, but I 
can't find an easy way to do this.

Reason for rejection could be things like the counter (for division, 
etc) has an upper limit on how fast it can run.

>> Also, I noticed that clk_set_parent() is treating a NULL as an invalid
>> clock. Should that be fixed? set_parent(NULL) could be treated as a
>> grounding the clock. Should we let the ops->set_parent determine if NULL is
>> valid option?
>
> We must be looking at different code.  clk_set_parent doesn't return
> any error if parent == NULL.  Bringing this to my attention does show
> that we do deref the parent pointer without a check though...
>
> Do you have a real use case for this?  Due to the way that we match
> the parent pointer with the cached clk->parents member it would be
> painful to support NULL parents as valid.

I don't have a real use case for MSM. We just have a ground_clock.

> It is also worth considering whether clk_set_parent is really the
> correct operation for grounding a clock.  clk_unprepare might be a
> better candidate.

Yeah, not a real use case for MSM.

Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From jon-hunter at ti.com  Fri Mar 23 19:21:13 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Fri, 23 Mar 2012 18:21:13 -0500
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <1332484600-21947-1-git-send-email-afzal@ti.com>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
Message-ID: <4F6D0569.6080203@ti.com>

Hi Afzal,

On 03/23/2012 01:36 AM, Afzal Mohammed wrote:

[snip]

> +struct gpmc_child {
> +	char			*name;
> +	int			id;
> +	struct resource		*res;
> +	unsigned		num_res;
> +	struct resource		gpmc_res[GPMC_CS_NUM];

Does this imply a gpmc child device can use more than one chip-select? I 
am trying to understand the link between number of resources and 
GPMC_CS_NUM.

> +	unsigned		gpmc_num_res;
> +	void			*pdata;
> +	unsigned		pdata_size;
> +};

Does pdata_size need to be stored? If pdata is always of type 
gpmc_device_pdata then you could avoid using void * and elsewhere use 
sizeof.

> -static u8 gpmc_cs_read_byte(int cs, int idx)
> -{
> -	void __iomem *reg_addr;
> +struct gpmc {
> +	struct device		*dev;
> +	unsigned long		fclk_rate;
> +	void __iomem		*io_base;
> +	unsigned long		phys_base;
> +	u32			memsize;
> +	unsigned		cs_map;
> +	int			ecc_used;
> +	spinlock_t		mem_lock;
> +	struct resource		mem_root;
> +	struct resource		cs_mem[GPMC_CS_NUM];
> +	struct gpmc_child	child_device[GPMC_CS_NUM];
> +	unsigned		num_child;
> +	unsigned		num_device;
> +};
>
> -	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> -	return __raw_readb(reg_addr);
> -}
> +static struct gpmc *gpmc;
>
> +/* Make function static */
>   void gpmc_cs_write_reg(int cs, int idx, u32 val)
>   {
>   	void __iomem *reg_addr;
>
> -	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> -	__raw_writel(val, reg_addr);
> +	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> +	writel(val, reg_addr);
>   }

I understand this was inherited from the original code, but I think that 
we should drop the "GPMC_CS0_OFFSET". We are already passing an index 
and so we should use this as an offset. This obviously implies changing 
the defintion of the GPMC_CS_xxxx registers in gpmc.h. This would save 
one addition too.

> +/* Make function static */
>   u32 gpmc_cs_read_reg(int cs, int idx)
>   {
>   	void __iomem *reg_addr;
>
> -	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> -	return __raw_readl(reg_addr);
> +	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> +	return readl(reg_addr);
>   }

Same as above.

> -/* TODO: Add support for gpmc_fck to clock framework and use it */
> -unsigned long gpmc_get_fclk_period(void)
> +static void gpmc_write_reg(int idx, u32 val)
>   {
> -	unsigned long rate = clk_get_rate(gpmc_l3_clk);
> -
> -	if (rate == 0) {
> -		printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
> -		return 0;
> -	}
> -
> -	rate /= 1000;
> -	rate = 1000000000 / rate;	/* In picoseconds */
> -
> -	return rate;
> +	writel(val, gpmc->io_base + idx);
>   }
>
> -unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
> +static u32 gpmc_read_reg(int idx)
>   {
> -	unsigned long tick_ps;
> -
> -	/* Calculate in picosecs to yield more exact results */
> -	tick_ps = gpmc_get_fclk_period();
> -
> -	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
> +	return readl(gpmc->io_base + idx);
>   }
>
> -unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
> +static void gpmc_cs_write_byte(int cs, int idx, u8 val)
>   {
> -	unsigned long tick_ps;
> -
> -	/* Calculate in picosecs to yield more exact results */
> -	tick_ps = gpmc_get_fclk_period();
> -
> -	return (time_ps + tick_ps - 1) / tick_ps;
> -}
> +	void __iomem *reg_addr;
>
> -unsigned int gpmc_ticks_to_ns(unsigned int ticks)
> -{
> -	return ticks * gpmc_get_fclk_period() / 1000;
> +	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> +	writeb(val, reg_addr);
>   }

Again here, can we get rid of GPMC_CS0_OFFSET?

> -unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
> +static u8 gpmc_cs_read_byte(int cs, int idx)
>   {
> -	unsigned long ticks = gpmc_ns_to_ticks(time_ns);
> +	void __iomem *reg_addr;
>
> -	return ticks * gpmc_get_fclk_period() / 1000;
> +	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> +	return readb(reg_addr);
>   }

And here, can we get rid of GPMC_CS0_OFFSET?

> -#ifdef DEBUG
> -static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
> -			       int time, const char *name)
> -#else
> -static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
> -			       int time)
> -#endif
> +static int gpmc_cs_set_reserved(int cs, int reserved)
>   {
> -	u32 l;
> -	int ticks, mask, nr_bits;
> -
> -	if (time == 0)
> -		ticks = 0;
> -	else
> -		ticks = gpmc_ns_to_ticks(time);
> -	nr_bits = end_bit - st_bit + 1;
> -	if (ticks>= 1<<  nr_bits) {
> -#ifdef DEBUG
> -		printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks>= %d\n",
> -				cs, name, time, ticks, 1<<  nr_bits);
> -#endif
> -		return -1;
> -	}
> +	if (cs>  GPMC_CS_NUM)
> +		return -ENODEV;
>
> -	mask = (1<<  nr_bits) - 1;
> -	l = gpmc_cs_read_reg(cs, reg);
> -#ifdef DEBUG
> -	printk(KERN_INFO
> -		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
> -	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
> -			(l>>  st_bit)&  mask, time);
> -#endif
> -	l&= ~(mask<<  st_bit);
> -	l |= ticks<<  st_bit;
> -	gpmc_cs_write_reg(cs, reg, l);
> +	gpmc->cs_map&= ~(1<<  cs);
> +	gpmc->cs_map |= (reserved ? 1 : 0)<<  cs;
>
>   	return 0;
>   }
>
> -#ifdef DEBUG
> -#define GPMC_SET_ONE(reg, st, end, field) \
> -	if (set_gpmc_timing_reg(cs, (reg), (st), (end),		\
> -			t->field, #field)<  0)			\
> -		return -1
> -#else
> -#define GPMC_SET_ONE(reg, st, end, field) \
> -	if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field)<  0) \
> -		return -1
> -#endif
> -
> -int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
> -{
> -	int div;
> -	u32 l;
> -
> -	l = sync_clk + (gpmc_get_fclk_period() - 1);
> -	div = l / gpmc_get_fclk_period();
> -	if (div>  4)
> -		return -1;
> -	if (div<= 0)
> -		div = 1;
> -
> -	return div;
> -}
> -
> -int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
> +static int gpmc_cs_reserved(int cs)
>   {
> -	int div;
> -	u32 l;
> -
> -	div = gpmc_cs_calc_divider(cs, t->sync_clk);
> -	if (div<  0)
> -		return -1;
> -
> -	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
> -
> -	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
> -
> -	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
> -
> -	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
> -	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
> -
> -	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
> -
> -	if (cpu_is_omap34xx()) {
> -		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
> -		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
> -	}
> -
> -	/* caller is expected to have initialized CONFIG1 to cover
> -	 * at least sync vs async
> -	 */
> -	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
> -	if (l&  (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
> -#ifdef DEBUG
> -		printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
> -				cs, (div * gpmc_get_fclk_period()) / 1000, div);
> -#endif
> -		l&= ~0x03;
> -		l |= (div - 1);
> -		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
> -	}
> +	if (cs>  GPMC_CS_NUM)
> +		return -ENODEV;
>
> -	return 0;
> +	return gpmc->cs_map&  (1<<  cs);
>   }
>
>   static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
> @@ -332,17 +186,6 @@ static void gpmc_cs_disable_mem(int cs)
>   	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
>   }
>
> -static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
> -{
> -	u32 l;
> -	u32 mask;
> -
> -	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
> -	*base = (l&  0x3f)<<  GPMC_CHUNK_SHIFT;
> -	mask = (l>>  8)&  0x0f;
> -	*size = (1<<  GPMC_SECTION_SHIFT) - (mask<<  GPMC_CHUNK_SHIFT);
> -}
> -
>   static int gpmc_cs_mem_enabled(int cs)
>   {
>   	u32 l;
> @@ -351,25 +194,6 @@ static int gpmc_cs_mem_enabled(int cs)
>   	return l&  GPMC_CONFIG7_CSVALID;
>   }
>
> -int gpmc_cs_set_reserved(int cs, int reserved)
> -{
> -	if (cs>  GPMC_CS_NUM)
> -		return -ENODEV;
> -
> -	gpmc_cs_map&= ~(1<<  cs);
> -	gpmc_cs_map |= (reserved ? 1 : 0)<<  cs;
> -
> -	return 0;
> -}
> -
> -int gpmc_cs_reserved(int cs)
> -{
> -	if (cs>  GPMC_CS_NUM)
> -		return -ENODEV;
> -
> -	return gpmc_cs_map&  (1<<  cs);
> -}
> -
>   static unsigned long gpmc_mem_align(unsigned long size)
>   {
>   	int order;
> @@ -384,24 +208,9 @@ static unsigned long gpmc_mem_align(unsigned long size)
>   	return size;
>   }
>
> -static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
> -{
> -	struct resource	*res =&gpmc_cs_mem[cs];
> -	int r;
> -
> -	size = gpmc_mem_align(size);
> -	spin_lock(&gpmc_mem_lock);
> -	res->start = base;
> -	res->end = base + size - 1;
> -	r = request_resource(&gpmc_mem_root, res);
> -	spin_unlock(&gpmc_mem_lock);
> -
> -	return r;
> -}
> -
>   int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
>   {
> -	struct resource *res =&gpmc_cs_mem[cs];
> +	struct resource *res =&gpmc->cs_mem[cs];
>   	int r = -1;
>
>   	if (cs>  GPMC_CS_NUM)
> @@ -411,7 +220,7 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
>   	if (size>  (1<<  GPMC_SECTION_SHIFT))
>   		return -ENOMEM;
>
> -	spin_lock(&gpmc_mem_lock);
> +	spin_lock(&gpmc->mem_lock);
>   	if (gpmc_cs_reserved(cs)) {
>   		r = -EBUSY;
>   		goto out;
> @@ -419,7 +228,7 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
>   	if (gpmc_cs_mem_enabled(cs))
>   		r = adjust_resource(res, res->start&  ~(size - 1), size);
>   	if (r<  0)
> -		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
> +		r = allocate_resource(&gpmc->mem_root, res, size, 0, ~0,
>   				      size, NULL, NULL);
>   	if (r<  0)
>   		goto out;
> @@ -428,66 +237,28 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
>   	*base = res->start;
>   	gpmc_cs_set_reserved(cs, 1);
>   out:
> -	spin_unlock(&gpmc_mem_lock);
> +	spin_unlock(&gpmc->mem_lock);
>   	return r;
>   }
>   EXPORT_SYMBOL(gpmc_cs_request);
>
>   void gpmc_cs_free(int cs)
>   {
> -	spin_lock(&gpmc_mem_lock);
> +	spin_lock(&gpmc->mem_lock);
>   	if (cs>= GPMC_CS_NUM || cs<  0 || !gpmc_cs_reserved(cs)) {
>   		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
>   		BUG();
> -		spin_unlock(&gpmc_mem_lock);
> +		spin_unlock(&gpmc->mem_lock);
>   		return;
>   	}
>   	gpmc_cs_disable_mem(cs);
> -	release_resource(&gpmc_cs_mem[cs]);
> +	release_resource(&gpmc->cs_mem[cs]);
>   	gpmc_cs_set_reserved(cs, 0);
> -	spin_unlock(&gpmc_mem_lock);
> +	spin_unlock(&gpmc->mem_lock);
>   }
>   EXPORT_SYMBOL(gpmc_cs_free);
>
>   /**
> - * gpmc_read_status - read access request to get the different gpmc status
> - * @cmd: command type
> - * @return status
> - */
> -int gpmc_read_status(int cmd)
> -{
> -	int	status = -EINVAL;
> -	u32	regval = 0;
> -
> -	switch (cmd) {
> -	case GPMC_GET_IRQ_STATUS:
> -		status = gpmc_read_reg(GPMC_IRQSTATUS);
> -		break;
> -
> -	case GPMC_PREFETCH_FIFO_CNT:
> -		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
> -		status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
> -		break;
> -
> -	case GPMC_PREFETCH_COUNT:
> -		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
> -		status = GPMC_PREFETCH_STATUS_COUNT(regval);
> -		break;
> -
> -	case GPMC_STATUS_BUFFER:
> -		regval = gpmc_read_reg(GPMC_STATUS);
> -		/* 1 : buffer is available to write */
> -		status = regval&  GPMC_STATUS_BUFF_EMPTY;
> -		break;
> -
> -	default:
> -		printk(KERN_ERR "gpmc_read_status: Not supported\n");
> -	}
> -	return status;
> -}
> -EXPORT_SYMBOL(gpmc_read_status);
> -
> -/**
>    * gpmc_cs_configure - write request to configure gpmc
>    * @cs: chip select number
>    * @cmd: command type
> @@ -555,120 +326,143 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
>   }
>   EXPORT_SYMBOL(gpmc_cs_configure);
>
> -/**
> - * gpmc_nand_read - nand specific read access request
> - * @cs: chip select number
> - * @cmd: command type
> +/* This is a duplication of an existing function; before GPMC probe
> +   invocation, platform code may need to find divider value, hence
> +   other function (gpmc_cs_calc_divider) is not removed, functions
> +   like it that are required by platform, probably can be put in
> +   common omap platform file. gpmc_calc_divider will get invoked
> +   only after GPMC driver gets probed. gpmc_cs_calc_divider is not
> +   invoked by GPMC driver to cleanly separate platform&  driver
> +   code, although both should return sme value.
>    */
> -int gpmc_nand_read(int cs, int cmd)
> +static int gpmc_calc_divider(u32 sync_clk)
>   {
> -	int rval = -EINVAL;
> -
> -	switch (cmd) {
> -	case GPMC_NAND_DATA:
> -		rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
> -		break;
> +	int div;
> +	u32 l;
>
> -	default:
> -		printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
> -	}
> -	return rval;
> +	l = sync_clk + (gpmc->fclk_rate - 1);

This was a little confusing to me at first. When I see fclk_rate I think 
frequency (eg. clk_get_rate()) and not period. The original code had a 
function called gpmc_get_fclk_period. I would consider renaming the 
variable to fclk_period to be clear.

> +	div = l / gpmc->fclk_rate;
> +	if (div>  4)
> +		return -1;
> +	if (div<= 0)
> +		div = 1;
> +
> +	return div;
>   }
> -EXPORT_SYMBOL(gpmc_nand_read);
>
> -/**
> - * gpmc_nand_write - nand specific write request
> - * @cs: chip select number
> - * @cmd: command type
> - * @wval: value to write
> - */
> -int gpmc_nand_write(int cs, int cmd, int wval)
> +static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
> +			       int time, const char *name)
>   {
> -	int err = 0;
> -
> -	switch (cmd) {
> -	case GPMC_NAND_COMMAND:
> -		gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
> -		break;
> +	u32 l;
> +	int ticks, mask, nr_bits;
>
> -	case GPMC_NAND_ADDRESS:
> -		gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
> -		break;
> +	if (time == 0)
> +		ticks = 0;
> +	else
> +		ticks = gpmc_ns_to_ticks(time);
> +	nr_bits = end_bit - st_bit + 1;
> +	if (ticks>= 1<<  nr_bits) {
> +		printk(KERN_DEBUG "GPMC CS%d: %-10s* %3d ns, %3d ticks>= %d\n",
> +				cs, name, time, ticks, 1<<  nr_bits);
> +		return -1;
> +	}
>
> -	case GPMC_NAND_DATA:
> -		gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
> +	mask = (1<<  nr_bits) - 1;
> +	l = gpmc_cs_read_reg(cs, reg);
> +	printk(KERN_DEBUG
> +		"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
> +	       cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
> +			(l>>  st_bit)&  mask, time);
> +	l&= ~(mask<<  st_bit);
> +	l |= ticks<<  st_bit;
> +	gpmc_cs_write_reg(cs, reg, l);
>
> -	default:
> -		printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
> -		err = -EINVAL;
> -	}
> -	return err;
> +	return 0;
>   }
> -EXPORT_SYMBOL(gpmc_nand_write);
> -
>
> +#define GPMC_SET_ONE(reg, st, end, field) \

Nit-pick, set-one is a bit generic, maybe GPMC_SET_TIME?

> +	do {							\
> +		if (set_gpmc_timing_reg(cs, (reg), (st), (end),	\
> +				t->field, #field)<  0)		\
> +			return -1;				\
> +	} while (0)
>
> -/**
> - * gpmc_prefetch_enable - configures and starts prefetch transfer
> - * @cs: cs (chip select) number
> - * @fifo_th: fifo threshold to be used for read/ write
> - * @dma_mode: dma mode enable (1) or disable (0)
> - * @u32_count: number of bytes to be transferred
> - * @is_write: prefetch read(0) or write post(1) mode
> - */
> -int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
> -				unsigned int u32_count, int is_write)
> +int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
>   {
> +	int div;
> +	u32 l;
>
> -	if (fifo_th>  PREFETCH_FIFOTHRESHOLD_MAX) {
> -		pr_err("gpmc: fifo threshold is not supported\n");
> +	div = gpmc_calc_divider(t->sync_clk);
> +	if (div<  0)
>   		return -1;
> -	} else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
> -		/* Set the amount of bytes to be prefetched */
> -		gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
>
> -		/* Set dma/mpu mode, the prefetch read / post write and
> -		 * enable the engine. Set which cs is has requested for.
> -		 */
> -		gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs<<  CS_NUM_SHIFT) |
> -					PREFETCH_FIFOTHRESHOLD(fifo_th) |
> -					ENABLE_PREFETCH |
> -					(dma_mode<<  DMA_MPU_MODE) |
> -					(0x1&  is_write)));
> +	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
>
> -		/*  Start the prefetch engine */
> -		gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
> -	} else {
> -		return -EBUSY;
> +	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
> +
> +	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
> +
> +	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
> +	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
> +
> +	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
> +
> +	if (cpu_is_omap34xx()) {
> +		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
> +		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
> +	}

OMAP4/5 also has the above fields and so maybe this should be 
(!cpu_is_omap24xx()).

> +
> +	/* caller is expected to have initialized CONFIG1 to cover
> +	 * at least sync vs async
> +	 */
> +	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
> +	if (l&  (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {

Is it valid to have READTYPE != WRITETYPE? I am wondering if there 
should be a check here to see if READTYPE and WRITETYPE are not equal?

> +		printk(KERN_DEBUG "GPMC CS%d CLK period is %lu ns (div %d)\n",
> +				cs, (div * gpmc_get_fclk_period()) / 1000, div);
> +		l&= ~0x03;

I think we should define GPMC_CONFIG1_FCLK_DIV_MASK for this.

> +		l |= (div - 1);
> +		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
>   	}
>
>   	return 0;
>   }
> -EXPORT_SYMBOL(gpmc_prefetch_enable);
>
> -/**
> - * gpmc_prefetch_reset - disables and stops the prefetch engine
> - */
> -int gpmc_prefetch_reset(int cs)
> +static __devinit void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
>   {
> -	u32 config1;
> +	u32 l;
> +	u32 mask;
>
> -	/* check if the same module/cs is trying to reset */
> -	config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
> -	if (((config1>>  CS_NUM_SHIFT)&  0x7) != cs)
> -		return -EINVAL;
> +	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
> +	*base = (l&  0x3f)<<  GPMC_CHUNK_SHIFT;

Define GPMC_CONFIG7_BASEADDRESS_MASK

> +	mask = (l>>  8)&  0x0f;

Define GPMC_CONFIG7_MASKADDRESS_MASK/SHIFT

> +	*size = (1<<  GPMC_SECTION_SHIFT) - (mask<<  GPMC_CHUNK_SHIFT);
> +}
>
> -	/* Stop the PFPW engine */
> -	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
> +static __devinit
> +int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
> +{
> +	struct resource	*res =&gpmc->cs_mem[cs];
> +	int r;
>
> -	/* Reset/disable the PFPW engine */
> -	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
> +	size = gpmc_mem_align(size);
> +	spin_lock(&gpmc->mem_lock);
> +	res->start = base;
> +	res->end = base + size - 1;
> +	r = request_resource(&gpmc->mem_root, res);
> +	spin_unlock(&gpmc->mem_lock);
>
> -	return 0;
> +	return r;
>   }
> -EXPORT_SYMBOL(gpmc_prefetch_reset);
>
> -static void __init gpmc_mem_init(void)
> +static __devinit void gpmc_mem_init(void)
>   {
>   	int cs;
>   	unsigned long boot_rom_space = 0;
> @@ -680,8 +474,8 @@ static void __init gpmc_mem_init(void)
>   	/* In apollon the CS0 is mapped as 0x0000 0000 */
>   	if (machine_is_omap_apollon())
>   		boot_rom_space = 0;
> -	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
> -	gpmc_mem_root.end = GPMC_MEM_END;
> +	gpmc->mem_root.start = GPMC_MEM_START + boot_rom_space;
> +	gpmc->mem_root.end = GPMC_MEM_END;
>
>   	/* Reserve all regions that has been set up by bootloader */
>   	for (cs = 0; cs<  GPMC_CS_NUM; cs++) {
> @@ -695,88 +489,245 @@ static void __init gpmc_mem_init(void)
>   	}
>   }
>
> -static int __init gpmc_init(void)
> +static inline int __devinit gpmc_find_next_child_slot(void)
>   {
> -	u32 l, irq;
> -	int cs, ret = -EINVAL;
> -	int gpmc_irq;
> -	char *ck = NULL;
> +	return gpmc->num_child;
> +}
>
> -	if (cpu_is_omap24xx()) {
> -		ck = "core_l3_ck";
> -		if (cpu_is_omap2420())
> -			l = OMAP2420_GPMC_BASE;
> -		else
> -			l = OMAP34XX_GPMC_BASE;
> -		gpmc_irq = INT_34XX_GPMC_IRQ;
> -	} else if (cpu_is_omap34xx()) {
> -		ck = "gpmc_fck";
> -		l = OMAP34XX_GPMC_BASE;
> -		gpmc_irq = INT_34XX_GPMC_IRQ;
> -	} else if (cpu_is_omap44xx()) {
> -		ck = "gpmc_ck";
> -		l = OMAP44XX_GPMC_BASE;
> -		gpmc_irq = OMAP44XX_IRQ_GPMC;
> -	}
> +static int __devinit gpmc_match_child(char *name, int id)
> +{
> +	int i;
> +	struct gpmc_child *p;
>
> -	if (WARN_ON(!ck))
> +	for (i = 0, p = gpmc->child_device; i<  gpmc->num_child; i++, p++)
> +		if (!strcmp(p->name, name)&&  (p->id == id))
> +			return i;
> +
> +	return -ENOENT;
> +}
> +
> +static __devinit int gpmc_setup_child(struct gpmc_device_pdata *gdev)

Nit-pick, gdev was a bit confusing to me, maybe just pdata instead?

> +{
> +	struct gpmc_config *c;
> +	int i, ret = 0;
> +	struct resource res;
> +	unsigned long start;
> +
> +	start = gdev->mem_start;
> +
> +	ret = gpmc_cs_request(gdev->cs, gdev->mem_size,&start);
> +	if (IS_ERR_VALUE(ret)) {
> +		dev_err(gpmc->dev, "error: gpmc request on CS: %u\n", gdev->cs);
>   		return ret;
> +	}
>
> -	gpmc_l3_clk = clk_get(NULL, ck);
> -	if (IS_ERR(gpmc_l3_clk)) {
> -		printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
> -		BUG();
> +	c = gdev->config;
> +	if (!c) {
> +		dev_err(gpmc->dev, "config not present for CS: %u\n", gdev->cs);
> +		return -EINVAL;
>   	}
>
> -	gpmc_base = ioremap(l, SZ_4K);
> -	if (!gpmc_base) {
> -		clk_put(gpmc_l3_clk);
> -		printk(KERN_ERR "Could not get GPMC register memory\n");
> -		BUG();
> +	for (i = 0; i<  gdev->num_config; c++, i++) {
> +		ret = gpmc_cs_configure(gdev->cs, c->cmd, c->val);
> +		if (IS_ERR_VALUE(ret)) {
> +			dev_err(gpmc->dev, "invalid cmd or value on CS:	\
> +			 %u: cmd: %d value: %d\n", gdev->cs, c->cmd, c->val);
> +			return ret;
> +		}
> +	}
> +
> +	if (gdev->timing) {
> +		ret = gpmc_cs_set_timings(gdev->cs, gdev->timing);
> +		if (IS_ERR_VALUE(ret)) {
> +			dev_err(gpmc->dev, "error: setting timing on CS: %d\n",
> +								gdev->cs);
> +			return ret;
> +		}
>   	}
>
> -	clk_enable(gpmc_l3_clk);
> +	res.start = start + gdev->mem_offset;
> +	res.end = res.start + gdev->mem_size - 1;
> +	res.flags = IORESOURCE_MEM;
> +
> +	i = gpmc_match_child(gdev->name, gdev->id);
> +	/* i>= GPMC_CS_NUM can never happen, this is for compiler to shutup */
> +	if (i>= 0&&  i<  GPMC_CS_NUM) {
> +		int j;
> +
> +		j = gpmc->child_device[i].gpmc_num_res;
> +		gpmc->child_device[i].gpmc_res[j] = res;

So struct "res" is a local variable and you are storing in a global 
structure? Did you intend to store the address of the pdata struct passed?

> +	} else if (i == -ENOENT) {
> +		i = gpmc_find_next_child_slot();
> +		if (IS_ERR_VALUE(i)) {
> +			dev_err(gpmc->dev, "error: childs exceeded\n");
> +			return -ENODEV;
> +		}
> +		gpmc->child_device[i].name = gdev->name;
> +		gpmc->child_device[i].id = gdev->id;
> +		gpmc->child_device[i].pdata = gdev->pdata;
> +		gpmc->child_device[i].pdata_size = gdev->pdata_size;
> +		gpmc->child_device[i].gpmc_res[0] = res;

Same here as above.

To be honest, I find this whole section of code confusing. This probably 
goes back to my initial questions of number of resources versus number 
of chip-selects.

> +	} else {
> +		/* should never come here */
> +		dev_err(gpmc->dev, "error: childs exceeded\n");
> +		return -ENODEV;
> +	}
> +
> +	gpmc->child_device[i].gpmc_num_res++;
> +
> +	return ret;
> +}
> +
> +static __devinit int gpmc_create_child(int cnt)
> +{
> +	struct gpmc_child *p = gpmc->child_device + cnt;
> +	int num = p->num_res + p->gpmc_num_res;
> +	struct resource *res;
> +
> +	res = kzalloc(sizeof(struct resource) * num, GFP_KERNEL);
> +	if (!res) {
> +		dev_err(gpmc->dev, "error: allocating memory\n");
> +		return -ENOMEM;
> +	}
> +
> +	memcpy((char *)res, (const char *) p->gpmc_res,
> +				sizeof(struct resource) * p->gpmc_num_res);
> +	memcpy((char *)(res + p->gpmc_num_res), (const char *)p->res,
> +				sizeof(struct resource) * p->num_res);
> +
> +	platform_device_register_resndata(gpmc->dev, p->name, p->id, res,
> +						num, p->pdata, p->pdata_size);
> +
> +	return 0;
> +}
> +
> +static __devinit int gpmc_probe(struct platform_device *pdev)
> +{
> +	u32 l;
> +	int i;
> +	int ret = -EINVAL;
> +	struct resource *res = NULL;
> +	struct gpmc_pdata *gd = dev_get_platdata(&pdev->dev);
> +	struct gpmc_device_pdata *gdev = NULL;
> +
> +	gpmc = devm_kzalloc(&pdev->dev, sizeof(struct gpmc), GFP_KERNEL);
> +	if (!gpmc) {
> +		dev_err(&pdev->dev, "Failed to allocate memory\n");
> +		return -ENOMEM;
> +	}
> +
> +	gpmc->dev =&pdev->dev;
> +	gpmc->fclk_rate = gd->fclk_rate;
> +	gpmc->num_device = gd->num_device;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		ret = -ENOENT;
> +		dev_err(gpmc->dev, "Failed to get resource: memory\n");
> +		goto err_res;
> +	}
> +	gpmc->phys_base = res->start;
> +	gpmc->memsize = resource_size(res);
> +
> +	if (request_mem_region(gpmc->phys_base,
> +		gpmc->memsize, DRIVER_NAME) == NULL) {
> +		ret = -ENOMEM;
> +		dev_err(gpmc->dev, "Failed to request memory region\n");
> +		goto err_mem;
> +	}
> +
> +	gpmc->io_base = ioremap(gpmc->phys_base, gpmc->memsize);
> +	if (!gpmc->io_base) {
> +		ret = -ENOMEM;
> +		dev_err(gpmc->dev, "Failed to ioremap memory\n");
> +		goto err_remap;
> +	}
> +
> +	gpmc->ecc_used = -EINVAL;

Why not 0?

> +	spin_lock_init(&gpmc->mem_lock);
> +	platform_set_drvdata(pdev, gpmc);
>
>   	l = gpmc_read_reg(GPMC_REVISION);
> -	printk(KERN_INFO "GPMC revision %d.%d\n", (l>>  4)&  0x0f, l&  0x0f);
> -	/* Set smart idle mode and automatic L3 clock gating */
> -	l = gpmc_read_reg(GPMC_SYSCONFIG);
> -	l&= 0x03<<  3;
> -	l |= (0x02<<  3) | (1<<  0);
> -	gpmc_write_reg(GPMC_SYSCONFIG, l);

Really need to clean up the above with some #defines. Ideally we would 
be using hwmod/pm_runtime for configuring the SYSCONFIG.

> +	dev_info(gpmc->dev, "GPMC revision %d.%d\n", (l>>  4)&  0x0f, l&  0x0f);
> +
>   	gpmc_mem_init();
>
> -	/* initalize the irq_chained */
> -	irq = OMAP_GPMC_IRQ_BASE;
> -	for (cs = 0; cs<  GPMC_CS_NUM; cs++) {
> -		irq_set_chip_and_handler(irq,&dummy_irq_chip,
> -						handle_simple_irq);
> -		set_irq_flags(irq, IRQF_VALID);
> -		irq++;
> +	for (i = 0, gdev = gd->device_pdata; i<  gd->num_device; gdev++, i++) {
> +		ret = gpmc_setup_child(gdev);
> +		if (IS_ERR_VALUE(ret))
> +			dev_err(gpmc->dev, "gpmc setup on CS: %u failed\n",
> +								gdev->cs);
> +		else
> +			gpmc->num_child++;
>   	}
>
> -	ret = request_irq(gpmc_irq,
> -			gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
> -	if (ret)
> -		pr_err("gpmc: irq-%d could not claim: err %d\n",
> -						gpmc_irq, ret);
> +	/* XXX: This would get modified once MFD */
> +	for (i = 0; i<  gpmc->num_child; i++)
> +		gpmc_create_child(i);
> +
> +	return ret;
> +
> +err_remap:
> +	release_mem_region(gpmc->phys_base, gpmc->memsize);
> +err_mem:
> +err_res:
> +	devm_kfree(&pdev->dev, gpmc);
>   	return ret;
>   }
> -postcore_initcall(gpmc_init);
>
> -static irqreturn_t gpmc_handle_irq(int irq, void *dev)
> +static __devexit int gpmc_remove(struct platform_device *pdev)
>   {
> -	u8 cs;
> +	struct gpmc *gpmc = platform_get_drvdata(pdev);
>
> -	/* check cs to invoke the irq */
> -	cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1))>>  CS_NUM_SHIFT)&  0x7;
> -	if (OMAP_GPMC_IRQ_BASE+cs<= OMAP_GPMC_IRQ_END)
> -		generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
> +	platform_set_drvdata(pdev, NULL);
> +	iounmap(gpmc->io_base);
> +	release_mem_region(gpmc->phys_base, gpmc->memsize);
> +	devm_kfree(&pdev->dev, gpmc);

Do we need to free irqs here?

> -	return IRQ_HANDLED;
> +	return 0;
>   }
>
> +static struct platform_driver gpmc_driver = {
> +	.probe		= gpmc_probe,
> +	.remove		= __devexit_p(gpmc_remove),
> +	.driver		= {
> +		.name	= DRIVER_NAME,
> +		.owner	= THIS_MODULE,
> +	},
> +};
> +
> +module_platform_driver(gpmc_driver);
> +
> +/* Suspend - resume support */
> +
>   #ifdef CONFIG_ARCH_OMAP3
> +/* Structure to save gpmc cs context */
> +struct gpmc_cs_config {
> +	u32 config1;
> +	u32 config2;
> +	u32 config3;
> +	u32 config4;
> +	u32 config5;
> +	u32 config6;
> +	u32 config7;
> +	int is_valid;
> +};
> +
> +/*
> + * Structure to save/restore gpmc context
> + * to support core off on OMAP3
> + */
> +struct omap3_gpmc_regs {
> +	u32 sysconfig;
> +	u32 irqenable;
> +	u32 timeout_ctrl;
> +	u32 config;
> +	u32 prefetch_config1;
> +	u32 prefetch_config2;
> +	u32 prefetch_control;
> +	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
> +};
> +
>   static struct omap3_gpmc_regs gpmc_context;
>
>   void omap3_gpmc_save_context(void)
> @@ -843,6 +794,159 @@ void omap3_gpmc_restore_context(void)
>   }
>   #endif /* CONFIG_ARCH_OMAP3 */
>
> +/* GPMC NAND related */
> +
> +/**
> + * gpmc_read_status - read access request to get the different gpmc status
> + * @cmd: command type
> + * @return status
> + */
> +int gpmc_read_status(int cmd)
> +{
> +	int	status = -EINVAL;
> +	u32	regval = 0;
> +
> +	switch (cmd) {
> +	case GPMC_GET_IRQ_STATUS:
> +		status = gpmc_read_reg(GPMC_IRQSTATUS);
> +		break;
> +
> +	case GPMC_PREFETCH_FIFO_CNT:
> +		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
> +		status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
> +		break;
> +
> +	case GPMC_PREFETCH_COUNT:
> +		regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
> +		status = GPMC_PREFETCH_STATUS_COUNT(regval);
> +		break;
> +
> +	case GPMC_STATUS_BUFFER:
> +		regval = gpmc_read_reg(GPMC_STATUS);
> +		/* 1 : buffer is available to write */
> +		status = regval&  GPMC_STATUS_BUFF_EMPTY;
> +		break;
> +
> +	default:
> +		printk(KERN_ERR "gpmc_read_status: Not supported\n");
> +	}
> +	return status;
> +}
> +EXPORT_SYMBOL(gpmc_read_status);
> +
> +/**
> + * gpmc_nand_read - nand specific read access request
> + * @cs: chip select number
> + * @cmd: command type
> + */
> +int gpmc_nand_read(int cs, int cmd)
> +{
> +	int rval = -EINVAL;
> +
> +	switch (cmd) {
> +	case GPMC_NAND_DATA:
> +		rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
> +		break;
> +
> +	default:
> +		printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
> +	}
> +	return rval;
> +}
> +EXPORT_SYMBOL(gpmc_nand_read);
> +
> +/**
> + * gpmc_nand_write - nand specific write request
> + * @cs: chip select number
> + * @cmd: command type
> + * @wval: value to write
> + */
> +int gpmc_nand_write(int cs, int cmd, int wval)
> +{
> +	int err = 0;
> +
> +	switch (cmd) {
> +	case GPMC_NAND_COMMAND:
> +		gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
> +		break;
> +
> +	case GPMC_NAND_ADDRESS:
> +		gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
> +		break;
> +
> +	case GPMC_NAND_DATA:
> +		gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
> +
> +	default:
> +		printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
> +		err = -EINVAL;
> +	}
> +	return err;
> +}
> +EXPORT_SYMBOL(gpmc_nand_write);
> +
> +
> +
> +/**
> + * gpmc_prefetch_enable - configures and starts prefetch transfer
> + * @cs: cs (chip select) number
> + * @fifo_th: fifo threshold to be used for read/ write
> + * @dma_mode: dma mode enable (1) or disable (0)
> + * @u32_count: number of bytes to be transferred
> + * @is_write: prefetch read(0) or write post(1) mode
> + */
> +int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
> +				unsigned int u32_count, int is_write)
> +{
> +
> +	if (fifo_th>  PREFETCH_FIFOTHRESHOLD_MAX) {
> +		pr_err("gpmc: fifo threshold is not supported\n");
> +		return -1;
> +	} else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
> +		/* Set the amount of bytes to be prefetched */
> +		gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
> +
> +		/* Set dma/mpu mode, the prefetch read / post write and
> +		 * enable the engine. Set which cs is has requested for.
> +		 */
> +		gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs<<  CS_NUM_SHIFT) |
> +					PREFETCH_FIFOTHRESHOLD(fifo_th) |
> +					ENABLE_PREFETCH |
> +					(dma_mode<<  DMA_MPU_MODE) |
> +					(0x1&  is_write)));

#define GPMC_PREFETCH_CONFIG1_ACCESSMODE

> +
> +		/*  Start the prefetch engine */
> +		gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
> +	} else {
> +		return -EBUSY;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(gpmc_prefetch_enable);
> +
> +/**
> + * gpmc_prefetch_reset - disables and stops the prefetch engine
> + */
> +int gpmc_prefetch_reset(int cs)
> +{
> +	u32 config1;
> +
> +	/* check if the same module/cs is trying to reset */
> +	config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
> +	if (((config1>>  CS_NUM_SHIFT)&  0x7) != cs)

Maybe define a mask value for the ENGINECSSELECTOR

> +		return -EINVAL;
> +
> +	/* Stop the PFPW engine */
> +	gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
> +
> +	/* Reset/disable the PFPW engine */
> +	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(gpmc_prefetch_reset);
> +
>   /**
>    * gpmc_enable_hwecc - enable hardware ecc functionality
>    * @cs: chip select number
> @@ -855,10 +959,10 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
>   	unsigned int val;
>
>   	/* check if ecc module is in used */
> -	if (gpmc_ecc_used != -EINVAL)
> +	if (gpmc->ecc_used != -EINVAL)
>   		return -EINVAL;

As mentioned above we could set ecc_used to 0 by default.

> -	gpmc_ecc_used = cs;
> +	gpmc->ecc_used = cs;
>
>   	/* clear ecc and enable bits */
>   	val = ((0x00000001<<8) | 0x00000001);
> @@ -906,7 +1010,7 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
>   {
>   	unsigned int val = 0x0;
>
> -	if (gpmc_ecc_used != cs)
> +	if (gpmc->ecc_used != cs)
>   		return -EINVAL;
>
>   	/* read ecc result */
> @@ -916,7 +1020,100 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
>   	/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
>   	*ecc_code++ = ((val>>  8)&  0x0f) | ((val>>  20)&  0xf0);
>
> -	gpmc_ecc_used = -EINVAL;
> +	gpmc->ecc_used = -EINVAL;

ecc_used = 0

>   	return 0;
>   }
>   EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
> +
> +/* GPMC CLK related */
> +
> +static struct clk *gpmc_l3_clk;
> +
> +static int __init gpmc_clk_init(void)
> +{
> +	char *ck = NULL;
> +
> +	if (cpu_is_omap24xx())
> +		ck = "core_l3_ck";
> +	else if (cpu_is_omap34xx())
> +		ck = "gpmc_fck";
> +	else if (cpu_is_omap44xx())
> +		ck = "gpmc_ck";
> +	if (WARN_ON(!ck))
> +		return -EINVAL;
> +
> +	gpmc_l3_clk = clk_get(NULL, ck);
> +	if (WARN_ON(IS_ERR(gpmc_l3_clk)))
> +		return -EINVAL;
> +
> +	if (WARN_ON(IS_ERR_VALUE(clk_enable(gpmc_l3_clk)))) {
> +		clk_put(gpmc_l3_clk);
> +		return -EIO;
> +	}
> +
> +	return 0;
> +}
> +postcore_initcall(gpmc_clk_init);
> +
> +/* TODO: Add support for gpmc_fck to clock framework and use it */
> +unsigned long gpmc_get_fclk_period(void)
> +{
> +	unsigned long rate = clk_get_rate(gpmc_l3_clk);
> +
> +	if (rate == 0) {
> +		printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
> +		return 0;
> +	}
> +
> +	rate /= 1000;
> +	rate = 1000000000 / rate;	/* In picoseconds */
> +
> +	return rate;
> +}
> +
> +unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
> +{
> +	unsigned long tick_ps;
> +
> +	/* Calculate in picosecs to yield more exact results */
> +	tick_ps = gpmc_get_fclk_period();
> +
> +	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
> +}
> +
> +unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
> +{
> +	unsigned long tick_ps;
> +
> +	/* Calculate in picosecs to yield more exact results */
> +	tick_ps = gpmc_get_fclk_period();
> +
> +	return (time_ps + tick_ps - 1) / tick_ps;
> +}
> +
> +unsigned int gpmc_ticks_to_ns(unsigned int ticks)
> +{
> +	return ticks * gpmc_get_fclk_period() / 1000;
> +}
> +
> +unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
> +{
> +	unsigned long ticks = gpmc_ns_to_ticks(time_ns);
> +
> +	return ticks * gpmc_get_fclk_period() / 1000;
> +}
> +
> +int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
> +{
> +	int div;
> +	u32 l;
> +
> +	l = sync_clk + (gpmc_get_fclk_period() - 1);
> +	div = l / gpmc_get_fclk_period();
> +	if (div>  4)
> +		return -1;
> +	if (div<= 0)
> +		div = 1;
> +
> +	return div;
> +}
> diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
> index 1527929..b949c0c 100644
> --- a/arch/arm/plat-omap/include/plat/gpmc.h
> +++ b/arch/arm/plat-omap/include/plat/gpmc.h
> @@ -131,6 +131,38 @@ struct gpmc_timings {
>   	u16 wr_data_mux_bus;	/* WRDATAONADMUXBUS */
>   };
>
> +struct gpmc_config {
> +	int cmd;
> +	int val;
> +};
> +
> +struct gpmc_device_pdata {
> +	/* connected peripheral specific */
> +	char			*name;
> +	int			id;
> +	/* resources configured via GPMC will be created by GPMC driver */
> +	struct resource		*res;
> +	unsigned		num_res;
> +	void			*pdata;
> +	unsigned		pdata_size;

Do you need pdata_size here?

> +
> +	/* GPMC specific */
> +	unsigned		cs;
> +	unsigned long		mem_size;
> +	unsigned long		mem_start;
> +	unsigned long		mem_offset;
> +	struct gpmc_config	*config;
> +	unsigned		num_config;
> +	struct gpmc_timings	*timing;
> +};
> +
> +struct gpmc_pdata {
> +	/* GPMC_FCLK rate in picoseconds */
> +	unsigned long			fclk_rate;

fclk_period

> +	struct gpmc_device_pdata	*device_pdata;
> +	unsigned			num_device;
> +};

Do you need both gpmc_pdata and gpmc_device_pdata? Would not a single 
structure work?

Cheers
Jon


From rusty at rustcorp.com.au  Fri Mar 23 19:17:07 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Sat, 24 Mar 2012 09:47:07 +1030
Subject: [PATCH] ARM: test for PMU feature on v7 (v2 with typo fix)
In-Reply-To: <20120323095314.GA13622@mudshark.cambridge.arm.com>
References: <4F590411.9060201@arm.com> <87ty1g88dv.fsf@rustcorp.com.au>
 <87r4wk889a.fsf@rustcorp.com.au>
 <20120323095314.GA13622@mudshark.cambridge.arm.com>
Message-ID: <87fwcy9abw.fsf@rustcorp.com.au>

On Fri, 23 Mar 2012 09:53:14 +0000, Will Deacon <will.deacon at arm.com> wrote:
> Hi Rusty,
> 
> On Fri, Mar 23, 2012 at 12:34:57AM +0000, Rusty Russell wrote:
> > The v7 ARM (B4.1.82) specifies that bits 27-24 of the ID_DFR0 reg show
> > what performance monitoring (if any) is available.  We should test this
> > before assuming (useful for inside virtualized environments, for example).
> 
> Ok, I can see why you don't want to emulate a PMU but I don't agree with the
> patch :)
...
> >  static struct arm_pmu *__init armv7_a8_pmu_init(void)
> >  {
> > +	if (!armv7_pmu_avail())
> > +		return NULL;
> 
> This code is only executed if we know for sure that we are running on a
> Cortex-A8. Cortex-A8 implementations have a PMU, so I don't like having the
> probe here in case we are running on a virtualised CPU that doesn't quite
> match the hardware.

OK, I see that argument, but I don't like it.  eg. the Cortex A-15 is
defined to have a PMUv2 with 6 counters, and below you're arguing we
should implement zero of them.

I had assumed that as we trend towards a common cross-platform kernel,
we should be relying on feature registers where available, not the
model.

> Would you be able to advertise 0 event counters instead and treat the PMU
> largely as RAZ/WI? The only tricky bit I can see is the cycle counter, which
> is mandated by the presence of a PMU, however this could also just RAZ
> initially.

Yes, that's the effect of the current emulation hack.  Far better not to
lie to the guest, however, than get weird results from profiling.

Cheers,
Rusty.
-- 
  How could I marry someone with more hair than me?  http://baldalex.org


From mturquette at ti.com  Fri Mar 23 19:28:16 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Fri, 23 Mar 2012 16:28:16 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <4F6D0167.3040704@codeaurora.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
 <4F6946AA.4070201@codeaurora.org> <4F6CEC0C.4060704@codeaurora.org>
 <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>
 <4F6CF555.4080109@codeaurora.org>
 <CAJOA=zOnR1NwZ1Cmkfb+b7f7=N_vg+txAUqKXF2Nf2nVYFMjjg@mail.gmail.com>
 <4F6D0167.3040704@codeaurora.org>
Message-ID: <CAJOA=zM47mB8tY2hV1QDVm1GZRqQrjrktkbLQ-Vp7hBjA8H5xg@mail.gmail.com>

On Fri, Mar 23, 2012 at 4:04 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
> On 03/23/2012 03:32 PM, Turquette, Mike wrote:
>> .recalc_rate serves two purposes: first it recalculates the rate after
>> the rate has changed and you pass in a new parent_rate argument. ?The
>> second purpose is to "speculate" a rate change. ?You can pass in any
>> rate for the parent_rate parameter when you call .recalc_rates. ?This
>> is what __speculate_rates does before the rate changes. ?For
>> clk_set_parent we call,
>>
>> __clk_speculate_rates(clk, parent->rate);
>>
>> Where parent above is the *new* parent. ?So this will let us propagate
>> pre-rate change notifiers with the new rate.
>>
>> Your .recalc_rate callback doesn't need to differentiate between the
>> two calls to .recalc_rate. ?It should just take in the parent_rate
>> value and do the calculation required of it.
>
> Yeah, this is generally true. But, in this specific case, the clock is a mux
> that can literally measure the real rate. I would like the rate of this mux
> clock to be the real measured rate and not just the parent rate.

That's pretty cool hardware.  Do you find that software-only tracking
doesn't match up with sampling the frequency in hardware?  If software
tracking of the rate changes is correct then you could just skip using
this hardware feature.

> I could actually measure the current rate and return that for recalc_rate(),
> but then the reported rate change during the pre-change notification would
> be wrong. Having the "msg" will let us at least fake the rate correctly for
> pre change notifiers.

In previous series I had separate .recalc_rate and .speculate_rate
callbacks.  I merged them since they were almost identical.  I'd
prefer not to reintroduce them since it creates a burden on others to
support seperate callbacks, and passing in the message is one way to
solve that... I'll think on this a bit more.

> How does a child (or grand child) clock (not a driver using the clock)
> reject a rate change if it know it can't handle that freq from the parent? I
> won't claim to know this part of the code thoroughly, but I can't find an
> easy way to do this.

Technically you could subscribe a notifier to your grand-child clock,
even if there is no driver for it.  The same code that implements your
platform's clock operations could register the notifier handler.

You can see how this works in clk_propagate_rate_change.  That usage
is certainly targeted more at drivers but could be made to work for
your case.  Let me know what you think; this is an interesting issue.

> Reason for rejection could be things like the counter (for division, etc)
> has an upper limit on how fast it can run.

Are you hitting this in practice today?  The clock framework shouldn't
be a perfect piece of code that can validate every possible
combination imaginable.  Some burden falls on the code calling the clk
api (especially if that code is platform code) to make sure that it
doesn't do stupid things.

>>> Also, I noticed that clk_set_parent() is treating a NULL as an invalid
>>> clock. Should that be fixed? set_parent(NULL) could be treated as a
>>> grounding the clock. Should we let the ops->set_parent determine if NULL
>>> is
>>> valid option?
>>
>>
>> We must be looking at different code. ?clk_set_parent doesn't return
>> any error if parent == NULL. ?Bringing this to my attention does show
>> that we do deref the parent pointer without a check though...
>>
>> Do you have a real use case for this? ?Due to the way that we match
>> the parent pointer with the cached clk->parents member it would be
>> painful to support NULL parents as valid.
>
> I don't have a real use case for MSM. We just have a ground_clock.

I'm electing to ignore the issue until we have a real use-case for it.

Regards,
Mike


From marc at cpdesign.com.au  Fri Mar 23 18:43:06 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Sat, 24 Mar 2012 09:43:06 +1100
Subject: [PATCH] regulator: i.MX35-PDK Add regulator support
In-Reply-To: <1332526267-3236-1-git-send-email-alexg@meprolight.com>
References: <1332526267-3236-1-git-send-email-alexg@meprolight.com>
Message-ID: <201203240943.06346.marc@cpdesign.com.au>

Hi Alex, 

> Thanks for the patches.
> 
> v4 3/4 not directly applicable to Linux version 3.3,
> I installed it manually, you could check it out?

That patch series was based on mfd-2.6/for-next because it should be accepted 
in the kernel through the mfd tree. (look in the Maintainers file for the mfd 
git repo uri).

You could rebase it for 3.3 kernel for your own use. My guess is that the 
confilcts are in the Kconfig or Makefile so it won't be too much trouble.

Cheers,
Marc


From jonsmirl at gmail.com  Fri Mar 23 21:14:19 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Fri, 23 Mar 2012 21:14:19 -0400
Subject: ioremap to a specific virtual address
In-Reply-To: <201203231931.06376.arnd@arndb.de>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <201203231520.22588.arnd@arndb.de>
 <CAKON4OybXXwLEmg19NJnLsE5kB16U6Dm4ay3=XCUB57fRfz+ng@mail.gmail.com>
 <201203231931.06376.arnd@arndb.de>
Message-ID: <CAKON4OwhcFDMC4dWjU7x4u2CPT7C2BxVuCDkTN0j14gTndi3tA@mail.gmail.com>

On Fri, Mar 23, 2012 at 3:31 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 23 March 2012, jonsmirl at gmail.com wrote:
>> On Fri, Mar 23, 2012 at 11:20 AM, Arnd Bergmann <arnd at arndb.de> wrote:
>> > On Friday 23 March 2012, jonsmirl at gmail.com wrote:
>> >> I will need to check how similar the chips actually are. NXP did not
>> >> use primecells in the lpc31xx family.
>> >>
>> >> I'd be happy to have some help. My trees are here:
>> >> https://github.com/jonsmirl
>> >
>> > I've taken a brief look at your tree, some comments:
>> >
>> > * Once you're done with the DT conversion, you should be able to
>> > ?completely remvoe the three board files. You probably know that already
>>
>> Thanks for the feedback.
>>
>> I don't think I can completely remove the board files. Some of the
>> generic devices have board specific callbacks. DM9000 for example. I
>> am setting up of_dev_auxdata for the boards so that I can pass these
>> callbacks in.
>
> There are some cases where it's not possible to avoid platform_data,
> but in most cases there is another better solution.
>
> If you end up having to use platform_data, the auxdata mechanism
> is the way to go.
>
>> # define DM_IO_DELAY() ? ? ? ?do { gpio_get_value(GPIO_MNAND_RYBN3);} while(0)
>>
>> static void dm9000_dumpblk(void __iomem *reg, int count)
>> {
>> ? ? ? int i;
>> ? ? ? int tmp;
>>
>> ? ? ? count = (count + 1) >> 1;
>> ? ? ? for (i = 0; i < count; i++) {
>> ? ? ? ? ? ? ? DM_IO_DELAY();
>> ? ? ? ? ? ? ? tmp = readw(reg);
>> ? ? ? }
>> }
>>
>> static void dm9000_inblk(void __iomem *reg, void *data, int count)
>> {
>> ? ? ? int i;
>> ? ? ? u16* pdata = (u16*)data;
>> ? ? ? count = (count + 1) >> 1;
>> ? ? ? for (i = 0; i < count; i++) {
>> ? ? ? ? ? ? ? DM_IO_DELAY();
>> ? ? ? ? ? ? ? *pdata++ = readw(reg);
>> ? ? ? }
>> }
>>
>> static struct dm9000_plat_data dm9000_platdata = {
>> ? ? ? .flags ? ? ? ? ?= DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM |
>> DM9000_PLATF_SIMPLE_PHY,
>
> The flags can become simple empty properties if necessary, so there is no
> need to keep these.
>
>> ? ? ? .dumpblk = dm9000_dumpblk,
>> ? ? ? .inblk = dm9000_inblk,
>> };
>
> I can see two possible ways besides platform_data for the register access:

The dm9000 is on the LPC3131 reference design board. It is not our
hardware so I'm not sure what it is doing with the GPIO pin. I'm
porting the reference board code in the hopes that someone will help
out in this effort.

Another piece of board specific glue is this bit that needs to be
executed before accessing the dm9000. It puts the bus in the board's
range in 8/16/32b mode, timings, etc.

tatic void __init ea_add_device_dm9000(void)
{
	/*
	 * Configure Chip-Select 2 on SMC for the DM9000.
	 * Note: These timings were calculated for MASTER_CLOCK = 90000000
	 *  according to the DM9000 timings.
	 */
	MPMC_STCONFIG1 = 0x81;
	MPMC_STWTWEN1 = 1;
	MPMC_STWTOEN1 = 1;
	MPMC_STWTRD1 = 4;
	MPMC_STWTPG1 = 1;
	MPMC_STWTWR1 = 1;
	MPMC_STWTTURN1 = 2;
	/* enable oe toggle between consec reads */
	SYS_MPMC_WTD_DEL1 = _BIT(5) | 4;

An external  LCD controller on CS1 needs a different setup.

static void __init ea_add_device_ssd1289(void)
{
	MPMC_STCONFIG0 = 0x81;
	MPMC_STWTWEN0  = 0;
	MPMC_STWTOEN0  = 0;
	MPMC_STWTRD0   = 31;
	MPMC_STWTPG0   = 0;
	MPMC_STWTWR0   = 3;
	MPMC_STWTTURN0 = 0;

>
> 1. generalize the driver's accessors. Since your platform wants to read
> a gpio pin before every access, you can provide a gpio line as the
> property in the dm9000 device node and access that in the same place
> in the common code if the gpio line is set, but skip the access otherwise.
> No other platform in mainline actually needs to override the functions,
> so there are hardly any disadvantages to this.
>
> 2. convert the entire driver to use the "regmap" infrastructure to abstract
> the registers, and implement a driver that implements the slow I/O. This
> would be a rather complex solution and probably not worth it, compared
> with the overhead of the first one or just staying with auxdata.
>
> If any problem turns out to be really hard to convert over from
> platform_data to device tree properties, auxdata is usually an acceptable
> solution, or you could submit the port with more of those hacks when
> there is reason to believe that you will fix them up later.
>
> ? ? ? ?Arnd



-- 
Jon Smirl
jonsmirl at gmail.com


From mika.westerberg at iki.fi  Sat Mar 24 03:32:07 2012
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Sat, 24 Mar 2012 09:32:07 +0200
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F0020696D48EEB@AUSP01VMBX24.collaborationhost.net>
References: <4F683B36.8090101@metasoft.pl>
 <20120321193836.GC3740@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48E3E@AUSP01VMBX24.collaborationhost.net>
 <20120323070446.GC5812@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48EEB@AUSP01VMBX24.collaborationhost.net>
Message-ID: <20120324073207.GD5812@mwesterb-mobl.ger.corp.intel.com>

On Fri, Mar 23, 2012 at 11:09:50AM -0500, H Hartley Sweeten wrote:
> On Friday, March 23, 2012 12:05 AM, Mika Westerberg wrote:
> > On Thu, Mar 22, 2012 at 09:19:10PM -0500, H Hartley Sweeten wrote:
> >
> >> Did you test this patch or just review it?
> >
> > I tested and reviewed it.
> 
> OK. What kernel? My tests so far have been with 3.3.

3.3 and -next.

> >> On my system it doesn't work. I think it has something to do with the
> >> changes to m2m_hw_interrupt but I haven't tracked it down yet.
> >> 
> >> It looks like what's missing is a:
> >> 
> >> 	edmac->edma->hw_submit(edmac);
> >> 
> >> But, maybe that's not needed with double buffering?
> >
> > Did you try without your patch and adding my VIC hack? That's what I did when
> > I first got this patch and I saw no problems. I tested with audio (M2P),
> > mmc_spi (M2M) and dmatest (M2M).
> 
> No, I have not applied your VIC hack.

Please try it. The point there was that we have a problem in ep93xx VIC/DMA
code but it is totally different thing and not related to Rafal's patch. We
can sort the VIC thing out separately IMHO. ep93xx dma in 3.3 is broken
regardless this patch.


From linux at arm.linux.org.uk  Sat Mar 24 05:23:16 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 24 Mar 2012 09:23:16 +0000
Subject: [PATCH 3/9] ARM: omap2/n8x0: work around modular omap mmc
In-Reply-To: <1332522836-29517-4-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
 <1332522836-29517-4-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <20120324092316.GA22608@n2100.arm.linux.org.uk>

On Fri, Mar 23, 2012 at 11:13:50AM -0600, mathieu.poirier at linaro.org wrote:
> From: Russell King <linux at arm.linux.org.uk>

This is wrong.  I am not the author of this patch.

> When the omap driver is built as a module for n8x0,
> n8x0_mmc_set_power_menelaus cannot call into the driver:
> 
> arch/arm/mach-omap2/board-n8x0.c:374: undefined reference
> to `omap_mmc_notify_cover_event'
> 
> As a workaround, do not provide that device in this case. This needs
> to be fixed properly, e.g. by converting n8x0 to be probed through the
> device tree and moving that code into the driver.
> 
> Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
> Suggested-by: Russell King <linux at arm.linux.org.uk>
> Acked-by: Tony Lindgren <tony at atomide.com>
> ---
>  arch/arm/mach-omap2/board-n8x0.c |    6 ++++--
>  1 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
> index 6722627..8529ca0 100644
> --- a/arch/arm/mach-omap2/board-n8x0.c
> +++ b/arch/arm/mach-omap2/board-n8x0.c
> @@ -193,8 +193,10 @@ static struct omap_onenand_platform_data board_onenand_data[] = {
>  };
>  #endif
>  
> -#if defined(CONFIG_MENELAUS) &&						\
> -	(defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
> +#ifdef CONFIG_MMC_OMAP_MODULE
> +#warning FIXME: cannot call omap_mmc_notify_cover_event for CONFIG_MMC_OMAP_MODULE
> +#endif
> +#if defined(CONFIG_MENELAUS) && (defined(CONFIG_MMC_OMAP)
>  
>  /*
>   * On both N800 and N810, only the first of the two MMC controllers is in use.
> -- 
> 1.7.5.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From thomas.abraham at linaro.org  Sat Mar 24 05:33:01 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 15:03:01 +0530
Subject: [PATCH v5 0/2] ARM: Exynos: Add irq_domain and device tree support for
 combiner
Message-ID: <1332581583-16100-1-git-send-email-thomas.abraham@linaro.org>

Changes since v4:
- In patch 2/2, removed the #ifdef CONFIF_OF around irq_of_parse_and_map() as
  suggested by Grant Likely. Hence this patch series depends on the patch
  with subject "of/irq: add empty irq_of_parse_and_map() for non-dt builds".

- Rebased to the latest kgene/for-next branch which now includes support for
  Exynos5. Since this patchset modifies portions of code that are common for
  both Exynos4 and Exynos5, there are minor modifications in this patch series
  to accommodate Exynos5 dt support as well.

- v4 of this patchset was acked by Grant Likely and Rob Herring. This patch
  series (v5) has minor modifications over v4 to include Exynos5 support. Since
  those modifications are minor (not related to irq_domain or dt functionality),
  I am retaining the Ack from Grant and Rob for this series.

Changes since v3:
- In dt case, the use of fixed gic linux irq number to map the combiner
  interrupt output is removed. This is replaced with the interrupt number
  obtained from the gic irq domain. (Thanks to Rob Herring and Grant
  Likely for this suggestion).
- Split the patch into two parts - irq_domain and device tree support
  addition.

Changes since v2:
- Rebased to Grant's irqdomain/next branch.

Changes since v1:
- Includes all changes suggested by Rob Herring.
- Tested with SPARSE_IRQ enabled.

This patchset adds irq_domain and device tree support for the Exynos Interrupt
Combiner controller.

The first patch adds a common irq domain for the interrupts managed by the
interrupt combiners. All the instances of irq combiner reference the common irq
domain for translating hardware interrupts to linux irq number.

The second patch adds a interrupt specifier translator to support device tree
based instantiation. It can translate interrupt specifiers for device nodes
which use combiner as their interrupt parent.

This patchset is based on
http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]

with all patches merged from
http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]

Thomas Abraham (2):
  ARM: Exynos: Add irq_domain support for interrupt combiner
  ARM: Exynos: Add device tree support for interrupt combiner

 .../bindings/arm/samsung/interrupt-combiner.txt    |   52 ++++++++
 arch/arm/mach-exynos/common.c                      |  138 ++++++++++++++-----
 2 files changed, 153 insertions(+), 37 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt




From thomas.abraham at linaro.org  Sat Mar 24 05:33:02 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 15:03:02 +0530
Subject: [PATCH v5 1/2] ARM: Exynos: Add irq_domain support for interrupt
 combiner
In-Reply-To: <1332581583-16100-1-git-send-email-thomas.abraham@linaro.org>
References: <1332581583-16100-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332581583-16100-2-git-send-email-thomas.abraham@linaro.org>

Add irq_domain support for hardware interrupts of the interrupt combiner.
The hardware interrupts of all the instances of the combiner are grouped
in a single irq_domain.

Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
Acked-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/mach-exynos/common.c |   87 +++++++++++++++++++++++-----------------
 1 files changed, 50 insertions(+), 37 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 85ed8b5..7518945 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -19,6 +19,8 @@
 #include <linux/serial_core.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/export.h>
+#include <linux/irqdomain.h>
 
 #include <asm/proc-fns.h>
 #include <asm/exception.h>
@@ -394,6 +396,7 @@ struct combiner_chip_data {
 	void __iomem *base;
 };
 
+static struct irq_domain *combiner_irq_domain;
 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 
 static inline void __iomem *combiner_base(struct irq_data *data)
@@ -406,14 +409,14 @@ static inline void __iomem *combiner_base(struct irq_data *data)
 
 static void combiner_mask_irq(struct irq_data *data)
 {
-	u32 mask = 1 << (data->irq % 32);
+	u32 mask = 1 << (data->hwirq % 32);
 
 	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 }
 
 static void combiner_unmask_irq(struct irq_data *data)
 {
-	u32 mask = 1 << (data->irq % 32);
+	u32 mask = 1 << (data->hwirq % 32);
 
 	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 }
@@ -469,36 +472,59 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
 	irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 }
 
-static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
-			  unsigned int irq_start)
+static void __init combiner_init_one(unsigned int combiner_nr,
+						void __iomem *base)
 {
-	unsigned int i;
-	unsigned int max_nr;
-
-	if (soc_is_exynos5250())
-		max_nr = EXYNOS5_MAX_COMBINER_NR;
-	else
-		max_nr = EXYNOS4_MAX_COMBINER_NR;
-
-	if (combiner_nr >= max_nr)
-		BUG();
-
 	combiner_data[combiner_nr].base = base;
-	combiner_data[combiner_nr].irq_offset = irq_start;
+	combiner_data[combiner_nr].irq_offset = irq_find_mapping(
+		combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
 	combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 
 	/* Disable all interrupts */
 
 	__raw_writel(combiner_data[combiner_nr].irq_mask,
 		     base + COMBINER_ENABLE_CLEAR);
+}
+
+static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
+					irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
+	irq_set_chip_data(irq, &combiner_data[hw >> 3]);
+	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+	return 0;
+}
+
+static struct irq_domain_ops combiner_irq_domain_ops = {
+	.map = combiner_irq_domain_map,
+};
 
-	/* Setup the Linux IRQ subsystem */
+void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
+{
+	int i, irq_base;
+	unsigned int max_nr, nr_irq;
+
+	max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
+						EXYNOS4_MAX_COMBINER_NR;
+	nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
+
+	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
+	if (IS_ERR_VALUE(irq_base)) {
+		irq_base = COMBINER_IRQ(0, 0);
+		pr_warning("%s: irq desc alloc failed. Continuing with %d as "
+				"linux irq base\n", __func__, irq_base);
+	}
+
+	combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
+				&combiner_irq_domain_ops, &combiner_data);
+	if (WARN_ON(!combiner_irq_domain)) {
+		pr_warning("%s: irq domain init failed\n", __func__);
+		return;
+	}
 
-	for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
-				+ MAX_IRQ_IN_COMBINER; i++) {
-		irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
-		irq_set_chip_data(i, &combiner_data[combiner_nr]);
-		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+	for (i = 0; i < max_nr; i++) {
+		combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
+		combiner_cascade_irq(i, IRQ_SPI(i));
 	}
 }
 
@@ -511,7 +537,6 @@ static const struct of_device_id exynos4_dt_irq_match[] = {
 
 void __init exynos4_init_irq(void)
 {
-	int irq;
 	unsigned int gic_bank_offset;
 
 	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
@@ -523,12 +548,7 @@ void __init exynos4_init_irq(void)
 		of_irq_init(exynos4_dt_irq_match);
 #endif
 
-	for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
-
-		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-				COMBINER_IRQ(irq, 0));
-		combiner_cascade_irq(irq, IRQ_SPI(irq));
-	}
+	combiner_init(S5P_VA_COMBINER_BASE, NULL);
 
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
@@ -540,15 +560,8 @@ void __init exynos4_init_irq(void)
 
 void __init exynos5_init_irq(void)
 {
-	int irq;
-
 	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
-
-	for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
-		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-				COMBINER_IRQ(irq, 0));
-		combiner_cascade_irq(irq, IRQ_SPI(irq));
-	}
+	combiner_init(S5P_VA_COMBINER_BASE, NULL);
 
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sat Mar 24 05:33:03 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 15:03:03 +0530
Subject: [PATCH v5 2/2] ARM: Exynos: Add device tree support for interrupt
 combiner
In-Reply-To: <1332581583-16100-1-git-send-email-thomas.abraham@linaro.org>
References: <1332581583-16100-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332581583-16100-3-git-send-email-thomas.abraham@linaro.org>

Add device tree based instantiation of the interrupt combiner controller.

Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
Acked-by: Rob Herring <rob.herring at calxeda.com>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
---
 .../bindings/arm/samsung/interrupt-combiner.txt    |   52 +++++++++++++++++
 arch/arm/mach-exynos/common.c                      |   61 ++++++++++++++++++--
 2 files changed, 108 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt

diff --git a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
new file mode 100644
index 0000000..f2f2171
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
@@ -0,0 +1,52 @@
+* Samsung Exynos Interrupt Combiner Controller
+
+Samsung's Exynos architecture includes a interrupt combiner controller which
+can combine interrupt sources as a group and provide a single interrupt request
+for the group. The interrupt request from each group are connected to a parent
+interrupt controller, such as GIC in case of Exynos4210.
+
+The interrupt combiner controller consists of multiple combiners. Upto eight
+interrupt sources can be connected to a combiner. The combiner outputs one
+combined interrupt for its eight interrupt sources. The combined interrupt
+is usually connected to a parent interrupt controller.
+
+A single node in the device tree is used to describe the interrupt combiner
+controller module (which includes multiple combiners). A combiner in the
+interrupt controller module shares config/control registers with other
+combiners. For example, a 32-bit interrupt enable/disable config register
+can accommodate upto 4 interrupt combiners (with each combiner supporting
+upto 8 interrupt sources).
+
+Required properties:
+- compatible: should be "samsung,exynos4210-combiner".
+- interrupt-controller: Identifies the node as an interrupt controller.
+- #interrupt-cells: should be <2>. The meaning of the cells are
+	* First Cell: Combiner Group Number.
+	* Second Cell: Interrupt number within the group.
+- reg: Base address and size of interrupt combiner registers.
+- interrupts: The list of interrupts generated by the combiners which are then
+    connected to a parent interrupt controller. The format of the interrupt
+    specifier depends in the interrupt parent controller.
+
+Optional properties:
+- samsung,combiner-nr: The number of interrupt combiners supported. If this
+  property is not specified, the default number of combiners is assumed
+  to be 16.
+- interrupt-parent: pHandle of the parent interrupt controller, if not
+  inherited from the parent node.
+
+
+Example:
+
+	The following is a an example from the Exynos4210 SoC dtsi file.
+
+	combiner:interrupt-controller at 10440000 {
+		compatible = "samsung,exynos4210-combiner";
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		reg = <0x10440000 0x1000>;
+		interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+			     <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+			     <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+	};
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 7518945..36b5837 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -21,6 +21,7 @@
 #include <linux/of_irq.h>
 #include <linux/export.h>
 #include <linux/irqdomain.h>
+#include <linux/of_address.h>
 
 #include <asm/proc-fns.h>
 #include <asm/exception.h>
@@ -486,6 +487,30 @@ static void __init combiner_init_one(unsigned int combiner_nr,
 		     base + COMBINER_ENABLE_CLEAR);
 }
 
+#ifdef CONFIG_OF
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+		struct device_node *controller, const u32 *intspec,
+		unsigned int intsize, unsigned long *out_hwirq,
+		unsigned int *out_type)
+{
+	if (d->of_node != controller)
+		return -EINVAL;
+	if (intsize < 2)
+		return -EINVAL;
+	*out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
+	*out_type = 0;
+	return 0;
+}
+#else
+static int combiner_irq_domain_xlate(struct irq_domain *d,
+		struct device_node *controller, const u32 *intspec,
+		unsigned int intsize, unsigned long *out_hwirq,
+		unsigned int *out_type)
+{
+	return -EINVAL;
+}
+#endif
+
 static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
 					irq_hw_number_t hw)
 {
@@ -496,16 +521,26 @@ static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
 }
 
 static struct irq_domain_ops combiner_irq_domain_ops = {
+	.xlate = combiner_irq_domain_xlate,
 	.map = combiner_irq_domain_map,
 };
 
 void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
 {
-	int i, irq_base;
+	int i, irq, irq_base;
 	unsigned int max_nr, nr_irq;
 
-	max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
+	if (np) {
+		if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
+			pr_warning("%s: number of combiners not specified, "
+				"setting default as %d.\n",
+				__func__, EXYNOS4_MAX_COMBINER_NR);
+			max_nr = EXYNOS4_MAX_COMBINER_NR;
+		}
+	} else {
+		max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
 						EXYNOS4_MAX_COMBINER_NR;
+	}
 	nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 
 	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
@@ -524,13 +559,29 @@ void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
 
 	for (i = 0; i < max_nr; i++) {
 		combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
-		combiner_cascade_irq(i, IRQ_SPI(i));
+		irq = np ? irq_of_parse_and_map(np, i) : IRQ_SPI(i);
+		combiner_cascade_irq(i, irq);
 	}
 }
 
 #ifdef CONFIG_OF
+void __init combiner_of_init(struct device_node *np, struct device_node *parent)
+{
+	void __iomem *combiner_base;
+
+	combiner_base = of_iomap(np, 0);
+	if (!combiner_base) {
+		pr_err("%s: failed to map combiner registers\n", __func__);
+		return;
+	}
+
+	combiner_init(combiner_base, np);
+}
+
 static const struct of_device_id exynos4_dt_irq_match[] = {
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ .compatible = "samsung,exynos4210-combiner",
+			.data = combiner_of_init, },
 	{},
 };
 #endif
@@ -548,7 +599,8 @@ void __init exynos4_init_irq(void)
 		of_irq_init(exynos4_dt_irq_match);
 #endif
 
-	combiner_init(S5P_VA_COMBINER_BASE, NULL);
+	if (!of_have_populated_dt())
+		combiner_init(S5P_VA_COMBINER_BASE, NULL);
 
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
@@ -561,7 +613,6 @@ void __init exynos4_init_irq(void)
 void __init exynos5_init_irq(void)
 {
 	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
-	combiner_init(S5P_VA_COMBINER_BASE, NULL);
 
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sat Mar 24 05:41:11 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 15:11:11 +0530
Subject: [PATCH v4 0/4] ARM: Exynos4: Add irq domain and device tree support
 for wakeup interrupts
Message-ID: <1332582075-16204-1-git-send-email-thomas.abraham@linaro.org>

Changes since v3:
- Rebased the patches to the latest kgene/for-next branch which now includes
  Exynos5 support as well. In this process, there are some significant changes,
  when compared to v3 version of this patchset, related to device tree support
  in patch 4/4 and code simplification in patch 1/4. Since v3 of this series
  was acked by Rob Herring, I have added the his Ack for patches 2/4 and
  3/4 but not in patches 1/4 and 4/4 (due to the new set of changes).

- Patch 4/4 includes modifications which are required to support Exynos5
  wakeup interrupt controller that has two interrupt parents (gic and
  interrupt combiner).

Changes since v2:
- Reworked irq domain support based on v5 of the irq_domain generalization
  patches.

Changes since v1: (only patch 4/4 has changes)
- Fixes based on Rob's comments:
  a. Fixed the function prototype of exynos4_init_irq_eint(void)
  b. Included interrupt-parent as an optional property for wakeup interrupt
      controller node.

Samsung Exynos4 includes 32 external wakeup interrupt sources. The first 16
of these interrupts are connected to GIC SPI[31:16]. The last 16 of these
interrupts are grouped together into one interrupt and connected to GIC
SPI[32].

Samsung Exynos5 also includes 32 external wakeup interrupt sources. The first
16 of these interrupts are connected to interrupt combiner controller. The
last 16 of these interrupts are grouped together into one interrupt and
connected to GIC SPI[32].

This patchset adds irq domain and device tree support for these interrupts.
Since there are users of fixed linux irq numbers of the external wakeup
interrupts, the legacy mapping is used for the irq domain.

This patchset is based on
http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]

with all patches merged from
http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]

This patchset should be applied after applying the following patch.
[PATCH v5] ARM: Exynos: Add irq domain and device tree support for interrupt combiner

Thomas Abraham (4):
  ARM: Exynos: Simplify the wakeup interrupt setup code
  ARM: Exynos: Add irq_domain support for gpio wakeup interrupts
  ARM: Exynos: Remove arch_initcall for wakeup interrupt initialization
  ARM: Exynos: Add device tree support for gpio wakeup interrupt controller

 .../bindings/arm/samsung/wakeup-eint.txt           |  152 ++++++++++++++++++++
 arch/arm/mach-exynos/common.c                      |  138 ++++++++++++------
 arch/arm/mach-exynos/include/mach/regs-gpio.h      |    4 +-
 3 files changed, 247 insertions(+), 47 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt



From thomas.abraham at linaro.org  Sat Mar 24 05:41:12 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 15:11:12 +0530
Subject: [PATCH v4 1/4] ARM: Exynos: Simplify the wakeup interrupt setup code
In-Reply-To: <1332582075-16204-1-git-send-email-thomas.abraham@linaro.org>
References: <1332582075-16204-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332582075-16204-2-git-send-email-thomas.abraham@linaro.org>

Simplify the wakeup interrupt setup code in order to add irq domain
and device tree support.

Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/common.c |   32 +++++++++++---------------------
 1 files changed, 11 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 36b5837..3768efa 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -995,16 +995,14 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 
 static int __init exynos_init_irq_eint(void)
 {
-	int irq;
+	int irq, *src_int;
+	unsigned int paddr;
 
-	if (soc_is_exynos5250())
-		exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
-	else
-		exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
-
-	if (exynos_eint_base == NULL) {
+	paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 : EXYNOS4_PA_GPIO2;
+	exynos_eint_base = ioremap(paddr, SZ_4K);
+	if (!exynos_eint_base) {
 		pr_err("unable to ioremap for EINT base address\n");
-		return -ENOMEM;
+		return -ENXIO;
 	}
 
 	for (irq = 0 ; irq <= 31 ; irq++) {
@@ -1015,20 +1013,12 @@ static int __init exynos_init_irq_eint(void)
 
 	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 
-	for (irq = 0 ; irq <= 15 ; irq++) {
+	for (irq = 0 ; irq <= 15; irq++) {
 		eint0_15_data[irq] = IRQ_EINT(irq);
-
-		if (soc_is_exynos5250()) {
-			irq_set_handler_data(exynos5_eint0_15_src_int[irq],
-					     &eint0_15_data[irq]);
-			irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
-						exynos_irq_eint0_15);
-		} else {
-			irq_set_handler_data(exynos4_eint0_15_src_int[irq],
-					     &eint0_15_data[irq]);
-			irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
-						exynos_irq_eint0_15);
-		}
+		src_int = soc_is_exynos5250() ? exynos5_eint0_15_src_int :
+						exynos4_eint0_15_src_int;
+		irq_set_handler_data(src_int[irq], &eint0_15_data[irq]);
+		irq_set_chained_handler(src_int[irq], exynos_irq_eint0_15);
 	}
 
 	return 0;
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sat Mar 24 05:41:13 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 15:11:13 +0530
Subject: [PATCH v4 2/4] ARM: Exynos: Add irq_domain support for gpio wakeup
 interrupts
In-Reply-To: <1332582075-16204-1-git-send-email-thomas.abraham@linaro.org>
References: <1332582075-16204-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332582075-16204-3-git-send-email-thomas.abraham@linaro.org>

Add a irq_domain for all the 32 gpio external wakeup interrupt sources.
Since there are users of fixed linux irq numbers of the external wakeup
interrupts, the legacy mapping is used for the irq domain. The fixups
required to use irq domain based interrupt mapping is also included.

Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
Acked-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/mach-exynos/common.c                 |   67 +++++++++++++++++--------
 arch/arm/mach-exynos/include/mach/regs-gpio.h |    4 +-
 2 files changed, 48 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 3768efa..b69f36a 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -759,6 +759,9 @@ static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
 
+#define EXYNOS_EINT_NR 32
+static struct irq_domain *irq_domain;
+
 static inline int exynos4_irq_to_gpio(unsigned int irq)
 {
 	if (irq < IRQ_EINT(0))
@@ -849,9 +852,9 @@ static inline void exynos_irq_eint_mask(struct irq_data *data)
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-	mask |= EINT_OFFSET_BIT(data->irq);
-	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
+	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->hwirq));
+	mask |= EINT_OFFSET_BIT(data->hwirq);
+	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->hwirq));
 	spin_unlock(&eint_lock);
 }
 
@@ -860,16 +863,16 @@ static void exynos_irq_eint_unmask(struct irq_data *data)
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-	mask &= ~(EINT_OFFSET_BIT(data->irq));
-	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
+	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->hwirq));
+	mask &= ~(EINT_OFFSET_BIT(data->hwirq));
+	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->hwirq));
 	spin_unlock(&eint_lock);
 }
 
 static inline void exynos_irq_eint_ack(struct irq_data *data)
 {
-	__raw_writel(EINT_OFFSET_BIT(data->irq),
-		     EINT_PEND(exynos_eint_base, data->irq));
+	__raw_writel(EINT_OFFSET_BIT(data->hwirq),
+		     EINT_PEND(exynos_eint_base, data->hwirq));
 }
 
 static void exynos_irq_eint_maskack(struct irq_data *data)
@@ -880,7 +883,7 @@ static void exynos_irq_eint_maskack(struct irq_data *data)
 
 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
-	int offs = EINT_OFFSET(data->irq);
+	int offs = data->hwirq;
 	int shift;
 	u32 ctrl, mask;
 	u32 newvalue = 0;
@@ -915,10 +918,10 @@ static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 	mask = 0x7 << shift;
 
 	spin_lock(&eint_lock);
-	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
+	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->hwirq));
 	ctrl &= ~mask;
 	ctrl |= newvalue << shift;
-	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
+	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->hwirq));
 	spin_unlock(&eint_lock);
 
 	if (soc_is_exynos5250())
@@ -962,7 +965,7 @@ static inline void exynos_irq_demux_eint(unsigned int start)
 
 	while (status) {
 		irq = fls(status) - 1;
-		generic_handle_irq(irq + start);
+		generic_handle_irq(irq_find_mapping(irq_domain, irq + start));
 		status &= ~(1 << irq);
 	}
 }
@@ -971,8 +974,8 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_get_chip(irq);
 	chained_irq_enter(chip, desc);
-	exynos_irq_demux_eint(IRQ_EINT(16));
-	exynos_irq_demux_eint(IRQ_EINT(24));
+	exynos_irq_demux_eint(16);
+	exynos_irq_demux_eint(24);
 	chained_irq_exit(chip, desc);
 }
 
@@ -980,6 +983,7 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 {
 	u32 *irq_data = irq_get_handler_data(irq);
 	struct irq_chip *chip = irq_get_chip(irq);
+	int eint_irq;
 
 	chained_irq_enter(chip, desc);
 	chip->irq_mask(&desc->irq_data);
@@ -987,15 +991,28 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 	if (chip->irq_ack)
 		chip->irq_ack(&desc->irq_data);
 
-	generic_handle_irq(*irq_data);
+	eint_irq = irq_find_mapping(irq_domain, *irq_data);
+	generic_handle_irq(eint_irq);
 
 	chip->irq_unmask(&desc->irq_data);
 	chained_irq_exit(chip, desc);
 }
 
+static int exynos_eint_irq_domain_map(struct irq_domain *d, unsigned int irq,
+					irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &exynos_irq_eint, handle_level_irq);
+	set_irq_flags(irq, IRQF_VALID);
+	return 0;
+}
+
+static struct irq_domain_ops exynos_eint_irq_domain_ops = {
+	.map = exynos_eint_irq_domain_map,
+};
+
 static int __init exynos_init_irq_eint(void)
 {
-	int irq, *src_int;
+	int irq, *src_int, irq_base;
 	unsigned int paddr;
 
 	paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 : EXYNOS4_PA_GPIO2;
@@ -1005,16 +1022,24 @@ static int __init exynos_init_irq_eint(void)
 		return -ENXIO;
 	}
 
-	for (irq = 0 ; irq <= 31 ; irq++) {
-		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
-					 handle_level_irq);
-		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+	irq_base = irq_alloc_descs(IRQ_EINT(0), 1, EXYNOS_EINT_NR, 0);
+	if (IS_ERR_VALUE(irq_base)) {
+		irq_base = IRQ_EINT(0);
+		pr_warning("%s: irq desc alloc failed. Continuing with %d as "
+				"linux irq base\n", __func__, irq_base);
+	}
+
+	irq_domain = irq_domain_add_legacy(NULL, EXYNOS_EINT_NR, irq_base, 0,
+					 &exynos_eint_irq_domain_ops, NULL);
+	if (WARN_ON(!irq_domain)) {
+		pr_warning("%s: irq domain init failed\n", __func__);
+		return 0;
 	}
 
 	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 
 	for (irq = 0 ; irq <= 15; irq++) {
-		eint0_15_data[irq] = IRQ_EINT(irq);
+		eint0_15_data[irq] = irq;
 		src_int = soc_is_exynos5250() ? exynos5_eint0_15_src_int :
 						exynos4_eint0_15_src_int;
 		irq_set_handler_data(src_int[irq], &eint0_15_data[irq]);
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index e4b5b60..24bf4ec 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -16,13 +16,13 @@
 #include <mach/map.h>
 #include <mach/irqs.h>
 
-#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
+#define EINT_REG_NR(x)			((x) >> 3)
 #define EINT_CON(b, x)			(b + 0xE00 + (EINT_REG_NR(x) * 4))
 #define EINT_FLTCON(b, x)		(b + 0xE80 + (EINT_REG_NR(x) * 4))
 #define EINT_MASK(b, x)			(b + 0xF00 + (EINT_REG_NR(x) * 4))
 #define EINT_PEND(b, x)			(b + 0xF40 + (EINT_REG_NR(x) * 4))
 
-#define EINT_OFFSET_BIT(x)		(1 << (EINT_OFFSET(x) & 0x7))
+#define EINT_OFFSET_BIT(x)		(1 << ((x) & 0x7))
 
 /* compatibility for plat-s5p/irq-pm.c */
 #define EXYNOS4_EINT40CON		(S5P_VA_GPIO2 + 0xE00)
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sat Mar 24 05:41:14 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 15:11:14 +0530
Subject: [PATCH v4 3/4] ARM: Exynos: Remove arch_initcall for wakeup interrupt
 initialization
In-Reply-To: <1332582075-16204-1-git-send-email-thomas.abraham@linaro.org>
References: <1332582075-16204-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332582075-16204-4-git-send-email-thomas.abraham@linaro.org>

The of_irq_init function would be setup to invoke the exynos4_init_irq_eint
function when booting using device tree. The arch_initcall for
exynos4_init_irq_eint would duplicate its invocation in that case. Hence,
arch_initcall for exynos4_init_irq_eint is removed and this function is invoked
from the exynos4_init_irq for non-dt case.

Moreover, with single kernel image build, the exynos4_init_irq_eint has no checks
to ensure that it is running on a exynos4 platform. So it would be appropriate
to invoke it from exynos4_init_irq.

Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
Acked-by: Rob Herring <rob.herring at calxeda.com>
---
 arch/arm/mach-exynos/common.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index b69f36a..7aa1919 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -64,6 +64,7 @@ static void exynos4_init_clocks(int xtal);
 static void exynos5_init_clocks(int xtal);
 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
+static int exynos_init_irq_eint(void);
 
 static struct cpu_table cpu_ids[] __initdata = {
 	{
@@ -608,6 +609,7 @@ void __init exynos4_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
+	exynos_init_irq_eint();
 }
 
 void __init exynos5_init_irq(void)
@@ -620,6 +622,7 @@ void __init exynos5_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
+	exynos_init_irq_eint();
 }
 
 struct bus_type exynos4_subsys = {
@@ -1048,4 +1051,3 @@ static int __init exynos_init_irq_eint(void)
 
 	return 0;
 }
-arch_initcall(exynos_init_irq_eint);
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sat Mar 24 05:41:15 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 15:11:15 +0530
Subject: [PATCH v4 4/4] ARM: Exynos: Add device tree support for gpio wakeup
 interrupt controller
In-Reply-To: <1332582075-16204-1-git-send-email-thomas.abraham@linaro.org>
References: <1332582075-16204-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332582075-16204-5-git-send-email-thomas.abraham@linaro.org>

Add device tree support for gpio wakeup source interrupt controller for
Exynos platforms.

Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 .../bindings/arm/samsung/wakeup-eint.txt           |  152 ++++++++++++++++++++
 arch/arm/mach-exynos/common.c                      |   55 ++++++--
 2 files changed, 195 insertions(+), 12 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt

diff --git a/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
new file mode 100644
index 0000000..04bbf25
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/wakeup-eint.txt
@@ -0,0 +1,152 @@
+* Samsung GPIO Wakeup Interrupt Controller
+
+This document is split into following sections.
+
+[1] Samsung Exynos4 GPIO Wakeup Interrupt Source Controller
+[2] Samsung Exynos5 GPIO Wakeup Interrupt Source Controller
+
+
+[1] Samsung Exynos4 GPIO Wakeup Interrupt Source Controller
+
+Samsung Exynos4 processor supports 32 external wakeup interrupt sources. First
+16 of these interrupts are directly connected to GIC and the rest 16 of the
+interrupts are grouped together to deliver a single interrupt to GIC.
+
+Required properties:
+
+    - compatible: should be "samsung,exynos4210-wakeup-eint".
+
+    - reg: physical base address of the controller and length of memory
+      mapped region.
+
+    - interrupt-controller: Identifies the node as an interrupt controller.
+
+    - interrupt-cells: Specifies the number of cells required to specify the
+      interrupt source number. The value of should be <2>. The first cell
+      represents the wakeup interrupt source number and the second cell
+      should be zero (currently unused).
+
+    - interrupts: List of interrupts generated by the gpio wakeup interrupt
+      controller which are connected to a parent interrupt controller. The
+      format of the interrupt specifier depends on the interrupt parent
+      controller.
+
+Optional properties:
+
+    - interrupt-parent: phandle of the parent interrupt controller, required
+      if not inheriting the interrupt parent from the parent node.
+
+Example:
+
+	The following example is from the Exynos4210 dtsi file.
+
+	wakeup_eint: interrupt-controller-wakeup-eint {
+		compatible = "samsung,exynos4210-wakeup-eint";
+		reg = <0x11000000 0x1000>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+				<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+				<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+				<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
+				<0 32 0>;
+	};
+
+
+[2] Samsung Exynos5 GPIO Wakeup Interrupt Source Controller
+
+Samsung Exynos5 processor supports 32 external wakeup interrupt sources. First
+16 of these interrupts are directly connected to GIC and the rest 16 of the
+interrupts are grouped together to deliver a single interrupt to interrupt
+combiner controller.
+
+Since the wakeup interrupts has two interrupt parents, a interrupt nexus
+child node is used that includes a interrupt-map used to translate wakeup
+interrupt specifiers into gic and combiner domain interrupts.
+
+Required properties:
+
+    - compatible: should be "samsung,exynos5210-wakeup-eint".
+
+    - reg: physical base address of the controller and length of memory
+      mapped region.
+
+    - interrupt-controller: Identifies the node as an interrupt controller.
+
+    - interrupt-cells: Specifies the number of cells required to specify the
+      interrupt source number. The value of should be <2>. The first cell
+      represents the wakeup interrupt source number and the second cell
+      should be zero (currently unused).
+
+    - interrupts: List of interrupts generated by the gpio wakeup interrupt
+      controller. Since both gic and combiner controllers are interrupt
+      parents, a interrupt nexus child node is used to translate the interrupt
+      specifiers into respective gic and combiner interrupt domains (see below).
+      The interrupt specifier should be two cells - the first cell should be the
+      interrupt number originating from the wakeup controller and the second
+      cell should be zero (unused).
+
+    - interrupt-parent: The phandle of the interrupt nexus child node.
+
+    - interrupt-nexus child node: This node is used to translate the interrupt
+      specifiers of the wakeup interrupt controller node to the respecitive
+      gic or combiner interrupt domain. The interrupt nexus node should include
+      the following properties.
+
+      - interrupt-cells: Specifies the number of cells required to specify the
+        interrupt source number. The value of should be <2>. The first cell
+        represents the wakeup interrupt source number and the second cell
+        should be zero (currently unused).
+
+      - #address-cells: value of this property should be zero.
+
+      - #size-cells: value of this property should be zero.
+
+      - interrupt-map: The interrpt-map specifies how interrupt specifiers are
+        translated. There should be a interrupt-map entry for each interrupt
+        generated by the wakeup interrupt controller. The format of each entry
+        in the interrupt map should be
+
+              <#intr 0 parent-phandle parent-interrupt-specifier>
+
+	 where #intr is one of the entries in the 'interrupts' property of the
+        parent node.
+
+
+Example:
+
+	wakeup_eint: interrupt-controller at 11400000 {
+		compatible = "samsung,exynos5210-wakeup-eint";
+		reg = <0x11400000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&eint_nexus>;
+		interrupts = <0x0 0>, <0x1 0>, <0x2 0>, <0x3 0>,
+			     <0x4 0>, <0x5 0>, <0x6 0>, <0x7 0>,
+			     <0x8 0>, <0x9 0>, <0xa 0>, <0xb 0>,
+			     <0xc 0>, <0xd 0>, <0xe 0>, <0xf 0>,
+			     <0x10 0>;
+
+                wakeup_map: interrupt-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &combiner 23 0>,
+                                        <0x1 0 &combiner 24 0>,
+                                        <0x2 0 &combiner 25 0>,
+                                        <0x3 0 &combiner 25 1>,
+                                        <0x4 0 &combiner 26 0>,
+                                        <0x5 0 &combiner 26 1>,
+                                        <0x6 0 &combiner 27 0>,
+                                        <0x7 0 &combiner 27 1>,
+                                        <0x8 0 &combiner 28 0>,
+                                        <0x9 0 &combiner 28 1>,
+                                        <0xa 0 &combiner 29 0>,
+                                        <0xb 0 &combiner 29 1>,
+                                        <0xc 0 &combiner 30 0>,
+                                        <0xd 0 &combiner 30 1>,
+                                        <0xe 0 &combiner 31 0>,
+                                        <0xf 0 &combiner 31 1>,
+                                        <0x10 0 &gic 0 32 0>;
+                };
+        };
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 7aa1919..d7a321f 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -64,7 +64,8 @@ static void exynos4_init_clocks(int xtal);
 static void exynos5_init_clocks(int xtal);
 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
-static int exynos_init_irq_eint(void);
+static int exynos_init_irq_eint(struct device_node *np,
+				struct device_node *parent);
 
 static struct cpu_table cpu_ids[] __initdata = {
 	{
@@ -583,6 +584,8 @@ static const struct of_device_id exynos4_dt_irq_match[] = {
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 	{ .compatible = "samsung,exynos4210-combiner",
 			.data = combiner_of_init, },
+	{ .compatible = "samsung,exynos4210-wakeup-eint",
+			.data = exynos_init_irq_eint, },
 	{},
 };
 #endif
@@ -600,8 +603,10 @@ void __init exynos4_init_irq(void)
 		of_irq_init(exynos4_dt_irq_match);
 #endif
 
-	if (!of_have_populated_dt())
+	if (!of_have_populated_dt()) {
 		combiner_init(S5P_VA_COMBINER_BASE, NULL);
+		exynos_init_irq_eint(NULL, NULL);
+	}
 
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
@@ -609,20 +614,38 @@ void __init exynos4_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
-	exynos_init_irq_eint();
 }
 
 void __init exynos5_init_irq(void)
 {
+	struct device_node *np;
+
 	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 
 	/*
+	 * The Exynos5 wakeup interrupt controller has two-interrupt parents,
+	 * gic and combiner. Hence, a interrupt nexus node is used to translate
+	 * interrupt specifers for the interrupts which wakeup interrupt
+	 * controller deliver to the gic and combiner.
+	 *
+	 * When using a interrupt nexus node (which is child node of the wakeup
+	 * controller node), the interrupt parent of the wakeup controller node
+	 * is set as the nexus node and the nexus node does not have a
+	 * 'interrupt-controller' property. Hence, the of_irq_init function
+	 * will not be able to invoke the intializer function for wakeup
+	 * interrupt controller. So call the initiazer explicitly here.
+	 */
+	np = of_find_compatible_node(NULL, NULL,
+					"samsung,exynos5210-wakeup-eint");
+	if (np)
+		exynos_init_irq_eint(np, NULL);
+
+	/*
 	 * The parameters of s5p_init_irq() are for VIC init.
 	 * Theses parameters should be NULL and 0 because EXYNOS4
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
-	exynos_init_irq_eint();
 }
 
 struct bus_type exynos4_subsys = {
@@ -1013,13 +1036,19 @@ static struct irq_domain_ops exynos_eint_irq_domain_ops = {
 	.map = exynos_eint_irq_domain_map,
 };
 
-static int __init exynos_init_irq_eint(void)
+static int __init exynos_init_irq_eint(struct device_node *np,
+					struct device_node *parent)
 {
-	int irq, *src_int, irq_base;
+	int irq, *src_int, irq_base, irq_eint;
 	unsigned int paddr;
 
-	paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 : EXYNOS4_PA_GPIO2;
-	exynos_eint_base = ioremap(paddr, SZ_4K);
+	if (!np) {
+		paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 :
+						EXYNOS4_PA_GPIO2;
+		exynos_eint_base = ioremap(paddr, SZ_4K);
+	} else {
+		exynos_eint_base = of_iomap(np, 0);
+	}
 	if (!exynos_eint_base) {
 		pr_err("unable to ioremap for EINT base address\n");
 		return -ENXIO;
@@ -1032,21 +1061,23 @@ static int __init exynos_init_irq_eint(void)
 				"linux irq base\n", __func__, irq_base);
 	}
 
-	irq_domain = irq_domain_add_legacy(NULL, EXYNOS_EINT_NR, irq_base, 0,
+	irq_domain = irq_domain_add_legacy(np, EXYNOS_EINT_NR, irq_base, 0,
 					 &exynos_eint_irq_domain_ops, NULL);
 	if (WARN_ON(!irq_domain)) {
 		pr_warning("%s: irq domain init failed\n", __func__);
 		return 0;
 	}
 
-	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
+	irq_eint = np ? irq_of_parse_and_map(np, 16) : EXYNOS_IRQ_EINT16_31;
+	irq_set_chained_handler(irq_eint, exynos_irq_demux_eint16_31);
 
 	for (irq = 0 ; irq <= 15; irq++) {
 		eint0_15_data[irq] = irq;
 		src_int = soc_is_exynos5250() ? exynos5_eint0_15_src_int :
 						exynos4_eint0_15_src_int;
-		irq_set_handler_data(src_int[irq], &eint0_15_data[irq]);
-		irq_set_chained_handler(src_int[irq], exynos_irq_eint0_15);
+		irq_eint = np ? irq_of_parse_and_map(np, irq) : src_int[irq];
+		irq_set_handler_data(irq_eint, &eint0_15_data[irq]);
+		irq_set_chained_handler(irq_eint, exynos_irq_eint0_15);
 	}
 
 	return 0;
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sat Mar 24 05:49:48 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 15:19:48 +0530
Subject: [PATCH v4 0/2] regulator: add irq domain and device tree support for
 MAX8997
Message-ID: <1332582590-16382-1-git-send-email-thomas.abraham@linaro.org>

Changes since v3:
- Fixed all comments from Grant Likely.
  - In patch 1/2, since linear mapping is used, the handle_nested_irq() is
    called only for allocated irq's.
  - In patch 2/2, the incorrect assignment of platform data pointer to
    dev->platform_data is reworked and fixed.

Changes since v2:
- Atleast one voltage level has to be specfied for Buck 1/2/5 even if GPIO
  DVS option is not used (suggested by MyungJoo Ham).
- Reworked the irq_domain support based the v5 of irq_domain generalization
  patches.

MAX8997 is a multi-function device which includes support for regulators, rtc,
battery charger and other sub-blocks. This patchset adds device tree support
for the pmic (regulators) sub-block.

The first patch adds irq domain support for the interrupts supported by max8997
mainly for removing the need to pass a irq_base from the platform code. The
irq_base could not anyway be passed in case of device tree based instantiation.
The reverse mapping method used is linear since the sub-drivers of max8997 has
access to the max8997 irq_domain from which the linux irq number can be
obtained.

The second patch adds device tree support for max8997. This patch modifies both
mfd and regulator portions of the max8997 code.

This patchset is based on the following tree.
http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]

with all patches merged from
http://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git [for-next]
http://git.secretlab.ca/git/linux-2.6.git [irqdomain/next]

and depends on the following patchset.
[PATCH v4 0/4] ARM: Exynos4: Add irq domain and device tree support for wakeup interrupts.

This patchset has been tested on Origen board.

Thomas Abraham (2):
  mfd: add irq domain support for max8997 interrupts
  regulator: add device tree support for max8997

 .../devicetree/bindings/regulator/max8997-pmic.txt |  133 ++++++++++++++++++
 arch/arm/mach-exynos/mach-nuri.c                   |    4 -
 arch/arm/mach-exynos/mach-origen.c                 |    1 -
 drivers/mfd/max8997-irq.c                          |   61 +++++----
 drivers/mfd/max8997.c                              |   74 ++++++++++-
 drivers/regulator/max8997.c                        |  143 +++++++++++++++++++-
 include/linux/mfd/max8997-private.h                |    5 +-
 include/linux/mfd/max8997.h                        |    2 +-
 8 files changed, 386 insertions(+), 37 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/max8997-pmic.txt



From thomas.abraham at linaro.org  Sat Mar 24 05:49:49 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 15:19:49 +0530
Subject: [PATCH v4 1/2] mfd: add irq domain support for max8997 interrupts
In-Reply-To: <1332582590-16382-1-git-send-email-thomas.abraham@linaro.org>
References: <1332582590-16382-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332582590-16382-2-git-send-email-thomas.abraham@linaro.org>

Add irq domain support for max8997 interrupts. The reverse mapping method
used is linear mapping since the sub-drivers of max8997 such as regulator
and charger drivers can use the max8997 irq_domain to get the linux irq
number for max8997 interrupts. All uses of irq_base in platform data and
max8997 driver private data are removed.

Cc: MyungJoo Ham <myungjoo.ham at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
Acked-by: Grant Likely <grant.likely at secretlab.ca>
---
 arch/arm/mach-exynos/mach-nuri.c    |    4 --
 arch/arm/mach-exynos/mach-origen.c  |    1 -
 drivers/mfd/max8997-irq.c           |   61 ++++++++++++++++++++--------------
 drivers/mfd/max8997.c               |    1 -
 include/linux/mfd/max8997-private.h |    4 ++-
 include/linux/mfd/max8997.h         |    1 -
 6 files changed, 39 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 7ac81ce..b21d85d 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1077,12 +1077,8 @@ static struct platform_device nuri_max8903_device = {
 static void __init nuri_power_init(void)
 {
 	int gpio;
-	int irq_base = IRQ_GPIO_END + 1;
 	int ta_en = 0;
 
-	nuri_max8997_pdata.irq_base = irq_base;
-	irq_base += MAX8997_IRQ_NR;
-
 	gpio = EXYNOS4_GPX0(7);
 	gpio_request(gpio, "AP_PMIC_IRQ");
 	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 827cb99..d3b2e9d 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -424,7 +424,6 @@ static struct max8997_platform_data __initdata origen_max8997_pdata = {
 	.buck1_gpiodvs	= false,
 	.buck2_gpiodvs	= false,
 	.buck5_gpiodvs	= false,
-	.irq_base	= IRQ_GPIO_END + 1,
 
 	.ignore_gpiodvs_side_effect = true,
 	.buck125_default_idx = 0x0,
diff --git a/drivers/mfd/max8997-irq.c b/drivers/mfd/max8997-irq.c
index 09274cf..00390a1 100644
--- a/drivers/mfd/max8997-irq.c
+++ b/drivers/mfd/max8997-irq.c
@@ -142,7 +142,8 @@ static void max8997_irq_sync_unlock(struct irq_data *data)
 static const inline struct max8997_irq_data *
 irq_to_max8997_irq(struct max8997_dev *max8997, int irq)
 {
-	return &max8997_irqs[irq - max8997->irq_base];
+	struct irq_data *data = irq_get_irq_data(irq);
+	return &max8997_irqs[data->hwirq];
 }
 
 static void max8997_irq_mask(struct irq_data *data)
@@ -182,7 +183,7 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
 	u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
 	u8 irq_src;
 	int ret;
-	int i;
+	int i, cur_irq;
 
 	ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
 	if (ret < 0) {
@@ -269,8 +270,11 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
 
 	/* Report */
 	for (i = 0; i < MAX8997_IRQ_NR; i++) {
-		if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask)
-			handle_nested_irq(max8997->irq_base + i);
+		if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
+			cur_irq = irq_find_mapping(max8997->irq_domain, i);
+			if (cur_irq)
+				handle_nested_irq(cur_irq);
+		}
 	}
 
 	return IRQ_HANDLED;
@@ -278,26 +282,40 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
 
 int max8997_irq_resume(struct max8997_dev *max8997)
 {
-	if (max8997->irq && max8997->irq_base)
-		max8997_irq_thread(max8997->irq_base, max8997);
+	if (max8997->irq && max8997->irq_domain)
+		max8997_irq_thread(0, max8997);
+	return 0;
+}
+
+static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
+					irq_hw_number_t hw)
+{
+	struct max8997_dev *max8997 = d->host_data;
+
+	irq_set_chip_data(irq, max8997);
+	irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
+	irq_set_nested_thread(irq, 1);
+#ifdef CONFIG_ARM
+	set_irq_flags(irq, IRQF_VALID);
+#else
+	irq_set_noprobe(irq);
+#endif
 	return 0;
 }
 
+static struct irq_domain_ops max8997_irq_domain_ops = {
+	.map = max8997_irq_domain_map,
+};
+
 int max8997_irq_init(struct max8997_dev *max8997)
 {
+	struct irq_domain *domain;
 	int i;
-	int cur_irq;
 	int ret;
 	u8 val;
 
 	if (!max8997->irq) {
 		dev_warn(max8997->dev, "No interrupt specified.\n");
-		max8997->irq_base = 0;
-		return 0;
-	}
-
-	if (!max8997->irq_base) {
-		dev_err(max8997->dev, "No interrupt base specified.\n");
 		return 0;
 	}
 
@@ -327,18 +345,11 @@ int max8997_irq_init(struct max8997_dev *max8997)
 					true : false;
 	}
 
-	/* Register with genirq */
-	for (i = 0; i < MAX8997_IRQ_NR; i++) {
-		cur_irq = i + max8997->irq_base;
-		irq_set_chip_data(cur_irq, max8997);
-		irq_set_chip_and_handler(cur_irq, &max8997_irq_chip,
-				handle_edge_irq);
-		irq_set_nested_thread(cur_irq, 1);
-#ifdef CONFIG_ARM
-		set_irq_flags(cur_irq, IRQF_VALID);
-#else
-		irq_set_noprobe(cur_irq);
-#endif
+	domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR,
+					&max8997_irq_domain_ops, &max8997);
+	if (!domain) {
+		dev_err(max8997->dev, "could not create irq domain\n");
+		return -ENODEV;
 	}
 
 	ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
diff --git a/drivers/mfd/max8997.c b/drivers/mfd/max8997.c
index cb83a7a..20ecad3 100644
--- a/drivers/mfd/max8997.c
+++ b/drivers/mfd/max8997.c
@@ -143,7 +143,6 @@ static int max8997_i2c_probe(struct i2c_client *i2c,
 	if (!pdata)
 		goto err;
 
-	max8997->irq_base = pdata->irq_base;
 	max8997->ono = pdata->ono;
 
 	mutex_init(&max8997->iolock);
diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
index 3f4deb6..830152c 100644
--- a/include/linux/mfd/max8997-private.h
+++ b/include/linux/mfd/max8997-private.h
@@ -23,6 +23,8 @@
 #define __LINUX_MFD_MAX8997_PRIV_H
 
 #include <linux/i2c.h>
+#include <linux/export.h>
+#include <linux/irqdomain.h>
 
 #define MAX8997_REG_INVALID	(0xff)
 
@@ -325,7 +327,7 @@ struct max8997_dev {
 
 	int irq;
 	int ono;
-	int irq_base;
+	struct irq_domain *irq_domain;
 	struct mutex irqlock;
 	int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
 	int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
index fff5905..818486c 100644
--- a/include/linux/mfd/max8997.h
+++ b/include/linux/mfd/max8997.h
@@ -155,7 +155,6 @@ struct max8997_led_platform_data {
 
 struct max8997_platform_data {
 	/* IRQ */
-	int irq_base;
 	int ono;
 	int wakeup;
 
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sat Mar 24 05:49:50 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 15:19:50 +0530
Subject: [PATCH v4 2/2] regulator: add device tree support for max8997
In-Reply-To: <1332582590-16382-1-git-send-email-thomas.abraham@linaro.org>
References: <1332582590-16382-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332582590-16382-3-git-send-email-thomas.abraham@linaro.org>

Add device tree based discovery support for max8997.

Cc: MyungJoo Ham <myungjoo.ham at samsung.com>
Cc: Rajendra Nayak <rnayak at ti.com>
Cc: Rob Herring <rob.herring at calxeda.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 .../devicetree/bindings/regulator/max8997-pmic.txt |  133 ++++++++++++++++++
 drivers/mfd/max8997.c                              |   73 ++++++++++-
 drivers/regulator/max8997.c                        |  143 +++++++++++++++++++-
 include/linux/mfd/max8997-private.h                |    1 +
 include/linux/mfd/max8997.h                        |    1 +
 5 files changed, 347 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/max8997-pmic.txt

diff --git a/Documentation/devicetree/bindings/regulator/max8997-pmic.txt b/Documentation/devicetree/bindings/regulator/max8997-pmic.txt
new file mode 100644
index 0000000..90a730b
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max8997-pmic.txt
@@ -0,0 +1,133 @@
+* Maxim MAX8997 Voltage and Current Regulator
+
+The Maxim MAX8997 is a multi-function device which includes volatage and
+current regulators, rtc, charger controller and other sub-blocks. It is
+interfaced to the host controller using a i2c interface. Each sub-block is
+addressed by the host system using different i2c slave address. This document
+describes the bindings for 'pmic' sub-block of max8997.
+
+Required properties:
+- compatible: Should be "maxim,max8997-pmic".
+- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
+
+- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck1 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck2 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck5 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+
+[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+    property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage'
+    property should specify atleast one voltage level (which would be a
+    safe operating voltage).
+
+    If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+    property is specified, then all the eigth voltage values for the
+    'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified.
+
+Optional properties:
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the interrupts from max8997 are delivered to.
+- interrupts: Interrupt specifiers for two interrupt sources.
+  - First interrupt specifier is for 'irq1' interrupt.
+  - Second interrupt specifier is for 'alert' interrupt.
+- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs.
+- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
+- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs.
+
+Additional properties required if either of the optional properties are used:
+- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for
+  multiple bucks, changing the voltage value of one of the bucks may affect
+  that of another buck, which is the side effect of the change (set_voltage).
+  Use this property to ignore such side effects and change the voltage.
+
+- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from
+  the possible 8 options selectable by the dvs gpios. The value of this
+  property should be between 0 and 7. If not specified or if out of range, the
+  default value of this property is set to 0.
+
+- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used
+  for dvs. The format of the gpio specifier depends in the gpio controller.
+
+
+Regulators: The regulators of max8997 that have to be instantiated should be
+included in a sub-node named 'regulators'. Regulator nodes included in this
+sub-node should be of the format as below. Note: The 'n' in LDOn and BUCKn
+represents the LDO or BUCK number as per the datasheet of max8997.
+
+    For LDO's:
+		LDOn {
+			standard regulator bindings here
+		};
+
+    For BUCK's:
+		BUCKn {
+			standard regulator bindings here
+		};
+
+The bindings inside the regulator nodes use the standard regulator bindings
+which are documented elsewhere.
+
+Example:
+
+	max8997_pmic at 66 {
+		compatible = "maxim,max8997-pmic";
+		interrupt-parent = <&wakeup_eint>;
+		reg = <0x66>;
+		interrupts = <4 0>, <3 0>;
+
+		max8997,pmic-buck1-uses-gpio-dvs;
+		max8997,pmic-buck2-uses-gpio-dvs;
+		max8997,pmic-buck5-uses-gpio-dvs;
+
+		max8997,pmic-ignore-gpiodvs-side-effect;
+		max8997,pmic-buck125-default-dvs-idx = <0>;
+
+		max8997,pmic-buck125-dvs-gpios = <&gpx0 0 1 0 0>, /* SET1 */
+						 <&gpx0 1 1 0 0>, /* SET2 */
+						 <&gpx0 2 1 0 0>; /* SET3 */
+
+		max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
+						 <1250000>, <1200000>,
+						 <1150000>, <1100000>,
+						 <1000000>, <950000>;
+
+		max8997,pmic-buck2-dvs-voltage = <1100000>, <1100000>,
+				    		 <1100000>, <1100000>,
+						 <1000000>, <1000000>,
+						 <1000000>, <1000000>;
+
+		max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
+						 <1200000>, <1200000>,
+						 <1200000>, <1200000>,
+						 <1200000>, <1200000>;
+
+		regulators {
+			ldo1_reg: LDO1 {
+				regulator-name = "VDD_ABB_3.3V";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-name = "VDD_ALIVE_1.1V";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-always-on;
+			};
+
+			buck1_reg: BUCK1 {
+				regulator-name = "VDD_ARM_1.2V";
+				regulator-min-microvolt = <950000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+		};
+	};
diff --git a/drivers/mfd/max8997.c b/drivers/mfd/max8997.c
index 20ecad3..1c38e98 100644
--- a/drivers/mfd/max8997.c
+++ b/drivers/mfd/max8997.c
@@ -21,8 +21,10 @@
  * This driver is based on max8998.c
  */
 
+#include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/i2c.h>
+#include <linux/of_irq.h>
 #include <linux/interrupt.h>
 #include <linux/pm_runtime.h>
 #include <linux/module.h>
@@ -47,6 +49,13 @@ static struct mfd_cell max8997_devs[] = {
 	{ .name = "max8997-led", .id = 2 },
 };
 
+#ifdef CONFIG_OF
+static struct of_device_id __devinitdata max8997_pmic_dt_match[] = {
+	{ .compatible = "maxim,max8997-pmic", .data = TYPE_MAX8997 },
+	{},
+};
+#endif
+
 int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest)
 {
 	struct max8997_dev *max8997 = i2c_get_clientdata(i2c);
@@ -123,6 +132,58 @@ int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask)
 }
 EXPORT_SYMBOL_GPL(max8997_update_reg);
 
+#ifdef CONFIG_OF
+/*
+ * Only the common platform data elements for max8997 are parsed here from the
+ * device tree. Other sub-modules of max8997 such as pmic, rtc and others have
+ * to parse their own platform data elements from device tree.
+ *
+ * The max8997 platform data structure is instantiated here and the drivers for
+ * the sub-modules need not instantiate another instance while parsing their
+ * platform data.
+ */
+static struct max8997_platform_data *max8997_i2c_parse_dt_pdata(
+					struct device *dev)
+{
+	struct max8997_platform_data *pd;
+
+	pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+	if (!pd) {
+		dev_err(dev, "could not allocate memory for pdata\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	pd->ono = irq_of_parse_and_map(dev->of_node, 1);
+
+	/*
+	 * ToDo: the 'wakeup' member in the platform data is more of a linux
+	 * specfic information. Hence, there is no binding for that yet and
+	 * not parsed here.
+	 */
+
+	return pd;
+}
+#else
+static int max8997_i2c_parse_dt_pdata(struct device *dev,
+					struct max8997_platform_data **pdata)
+{
+	return 0;
+}
+#endif
+
+static inline int max8997_i2c_get_driver_data(struct i2c_client *i2c,
+						const struct i2c_device_id *id)
+{
+#ifdef CONFIG_OF
+	if (i2c->dev.of_node) {
+		const struct of_device_id *match;
+		match = of_match_node(max8997_pmic_dt_match, i2c->dev.of_node);
+		return (int)match->data;
+	}
+#endif
+	return (int)id->driver_data;
+}
+
 static int max8997_i2c_probe(struct i2c_client *i2c,
 			    const struct i2c_device_id *id)
 {
@@ -137,12 +198,21 @@ static int max8997_i2c_probe(struct i2c_client *i2c,
 	i2c_set_clientdata(i2c, max8997);
 	max8997->dev = &i2c->dev;
 	max8997->i2c = i2c;
-	max8997->type = id->driver_data;
+	max8997->type = max8997_i2c_get_driver_data(i2c, id);
 	max8997->irq = i2c->irq;
 
+	if (max8997->dev->of_node) {
+		pdata = max8997_i2c_parse_dt_pdata(max8997->dev);
+		if (IS_ERR(pdata)) {
+			ret = PTR_ERR(pdata);
+			goto err;
+		}
+	}
+
 	if (!pdata)
 		goto err;
 
+	max8997->pdata = pdata;
 	max8997->ono = pdata->ono;
 
 	mutex_init(&max8997->iolock);
@@ -434,6 +504,7 @@ static struct i2c_driver max8997_i2c_driver = {
 		   .name = "max8997",
 		   .owner = THIS_MODULE,
 		   .pm = &max8997_pm,
+		   .of_match_table = of_match_ptr(max8997_pmic_dt_match),
 	},
 	.probe = max8997_i2c_probe,
 	.remove = max8997_i2c_remove,
diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index 9657929..dce8aaf 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -25,6 +25,7 @@
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
+#include <linux/of_gpio.h>
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
@@ -32,6 +33,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/mfd/max8997.h>
 #include <linux/mfd/max8997-private.h>
+#include <linux/regulator/of_regulator.h>
 
 struct max8997_data {
 	struct device *dev;
@@ -953,21 +955,155 @@ static struct regulator_desc regulators[] = {
 	},
 };
 
+#ifdef CONFIG_OF
+static int max8997_pmic_dt_parse_dvs_gpio(struct max8997_dev *iodev,
+			struct max8997_platform_data *pdata,
+			struct device_node *pmic_np)
+{
+	int i, gpio;
+
+	for (i = 0; i < 3; i++) {
+		gpio = of_get_named_gpio(pmic_np,
+					"max8997,pmic-buck125-dvs-gpios", i);
+		if (!gpio_is_valid(gpio)) {
+			dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
+			return -EINVAL;
+		}
+		pdata->buck125_gpios[i] = gpio;
+	}
+	return 0;
+}
+
+static int max8997_pmic_dt_parse_pdata(struct max8997_dev *iodev,
+					struct max8997_platform_data *pdata)
+{
+	struct device_node *pmic_np, *regulators_np, *reg_np;
+	struct max8997_regulator_data *rdata;
+	unsigned int i, dvs_voltage_nr = 1, ret;
+
+	pmic_np = iodev->dev->of_node;
+	if (!pmic_np) {
+		dev_err(iodev->dev, "could not find pmic sub-node\n");
+		return -ENODEV;
+	}
+
+	regulators_np = of_find_node_by_name(pmic_np, "regulators");
+	if (!regulators_np) {
+		dev_err(iodev->dev, "could not find regulators sub-node\n");
+		return -EINVAL;
+	}
+
+	/* count the number of regulators to be supported in pmic */
+	pdata->num_regulators = 0;
+	for_each_child_of_node(regulators_np, reg_np)
+		pdata->num_regulators++;
+
+	rdata = devm_kzalloc(iodev->dev, sizeof(*rdata) *
+				pdata->num_regulators, GFP_KERNEL);
+	if (!rdata) {
+		dev_err(iodev->dev, "could not allocate memory for "
+						"regulator data\n");
+		return -ENOMEM;
+	}
+
+	pdata->regulators = rdata;
+	for_each_child_of_node(regulators_np, reg_np) {
+		for (i = 0; i < ARRAY_SIZE(regulators); i++)
+			if (!of_node_cmp(reg_np->name, regulators[i].name))
+				break;
+		rdata->id = i;
+		rdata->initdata = of_get_regulator_init_data(
+						iodev->dev, reg_np);
+		rdata->reg_node = reg_np;
+		rdata++;
+	}
+
+	if (of_get_property(pmic_np, "max8997,pmic-buck1-uses-gpio-dvs", NULL))
+		pdata->buck1_gpiodvs = true;
+
+	if (of_get_property(pmic_np, "max8997,pmic-buck2-uses-gpio-dvs", NULL))
+		pdata->buck2_gpiodvs = true;
+
+	if (of_get_property(pmic_np, "max8997,pmic-buck5-uses-gpio-dvs", NULL))
+		pdata->buck5_gpiodvs = true;
+
+	if (pdata->buck1_gpiodvs || pdata->buck2_gpiodvs ||
+						pdata->buck5_gpiodvs) {
+		ret = max8997_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np);
+		if (ret)
+			return -EINVAL;
+
+		if (of_property_read_u32(pmic_np,
+				"max8997,pmic-buck125-default-dvs-idx",
+				&pdata->buck125_default_idx)) {
+			pdata->buck125_default_idx = 0;
+		} else {
+			if (pdata->buck125_default_idx >= 8) {
+				pdata->buck125_default_idx = 0;
+				dev_info(iodev->dev, "invalid value for "
+				"default dvs index, using 0 instead\n");
+			}
+		}
+
+		if (of_get_property(pmic_np,
+			"max8997,pmic-ignore-gpiodvs-side-effect", NULL))
+			pdata->ignore_gpiodvs_side_effect = true;
+
+		dvs_voltage_nr = 8;
+	}
+
+	if (of_property_read_u32_array(pmic_np,
+				"max8997,pmic-buck1-dvs-voltage",
+				pdata->buck1_voltage, dvs_voltage_nr)) {
+		dev_err(iodev->dev, "buck1 voltages not specified\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32_array(pmic_np,
+				"max8997,pmic-buck2-dvs-voltage",
+				pdata->buck2_voltage, dvs_voltage_nr)) {
+		dev_err(iodev->dev, "buck2 voltages not specified\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32_array(pmic_np,
+				"max8997,pmic-buck5-dvs-voltage",
+				pdata->buck5_voltage, dvs_voltage_nr)) {
+		dev_err(iodev->dev, "buck5 voltages not specified\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#else
+static int max8997_pmic_dt_parse_pdata(struct max8997_dev *iodev,
+					struct max8997_platform_data *pdata)
+{
+	return 0;
+}
+#endif /* CONFIG_OF */
+
 static __devinit int max8997_pmic_probe(struct platform_device *pdev)
 {
 	struct max8997_dev *iodev = dev_get_drvdata(pdev->dev.parent);
-	struct max8997_platform_data *pdata = dev_get_platdata(iodev->dev);
+	struct max8997_platform_data *pdata = iodev->pdata;
 	struct regulator_dev **rdev;
 	struct max8997_data *max8997;
 	struct i2c_client *i2c;
 	int i, ret, size;
 	u8 max_buck1 = 0, max_buck2 = 0, max_buck5 = 0;
 
-	if (!pdata) {
+	if (IS_ERR_OR_NULL(pdata)) {
 		dev_err(pdev->dev.parent, "No platform init data supplied.\n");
 		return -ENODEV;
 	}
 
+	if (iodev->dev->of_node) {
+		ret = max8997_pmic_dt_parse_pdata(iodev, pdata);
+		if (ret)
+			return ret;
+	}
+
 	max8997 = kzalloc(sizeof(struct max8997_data), GFP_KERNEL);
 	if (!max8997)
 		return -ENOMEM;
@@ -1141,7 +1277,8 @@ static __devinit int max8997_pmic_probe(struct platform_device *pdev)
 			regulators[id].n_voltages = 16;
 
 		rdev[i] = regulator_register(&regulators[id], max8997->dev,
-				pdata->regulators[i].initdata, max8997, NULL);
+				pdata->regulators[i].initdata, max8997,
+				pdata->regulators[i].reg_node);
 		if (IS_ERR(rdev[i])) {
 			ret = PTR_ERR(rdev[i]);
 			dev_err(max8997->dev, "regulator init failed for %d\n",
diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
index 830152c..6ae21bf 100644
--- a/include/linux/mfd/max8997-private.h
+++ b/include/linux/mfd/max8997-private.h
@@ -316,6 +316,7 @@ enum max8997_irq {
 #define MAX8997_NUM_GPIO	12
 struct max8997_dev {
 	struct device *dev;
+	struct max8997_platform_data *pdata;
 	struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
 	struct i2c_client *rtc; /* slave addr 0x0c */
 	struct i2c_client *haptic; /* slave addr 0x90 */
diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
index 818486c..ba92375 100644
--- a/include/linux/mfd/max8997.h
+++ b/include/linux/mfd/max8997.h
@@ -75,6 +75,7 @@ enum max8998_regulators {
 struct max8997_regulator_data {
 	int id;
 	struct regulator_init_data *initdata;
+	struct device_node *reg_node;
 };
 
 enum max8997_muic_usb_type {
-- 
1.6.6.rc2



From anton.vorontsov at linaro.org  Sat Mar 24 06:26:12 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 14:26:12 +0400
Subject: [PATCH v2 0/10] Fixes for common mistakes w/ for_each_process and
 task->mm
Message-ID: <20120324102609.GA28356@lizard>

Hi all,

This is a reincarnation of the task->mm fixes. Several architectures
were traverse the tasklist in an unsafe manner, plus there are a
few cases of unsafe access to task->mm.

In v2 I decided to introduce a small helper in cpu.c: most arches
duplicate the same [buggy] code snippet, so it's better to fix it
and move the logic into a common function.

Thanks!

-- 
Anton Vorontsov
Email: cbouatmailru at gmail.com


From anton.vorontsov at linaro.org  Sat Mar 24 06:27:51 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 14:27:51 +0400
Subject: [PATCH 01/10] cpu: Introduce clear_tasks_mm_cpumask() helper
In-Reply-To: <20120324102609.GA28356@lizard>
References: <20120324102609.GA28356@lizard>
Message-ID: <20120324102751.GA29067@lizard>

Many architctures clear tasks' mm_cpumask like this:

	read_lock(&tasklist_lock);
	for_each_process(p) {
		if (p->mm)
			cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
	}
	read_unlock(&tasklist_lock);

The code above has several problems, such as:

1. Working with task->mm w/o getting mm or grabing the task lock is
   dangerous as ->mm might disappear (exit_mm() assigns NULL under
   task_lock(), so tasklist lock is not enough).

2. Checking for process->mm is not enough because process' main
   thread may exit or detach its mm via use_mm(), but other threads
   may still have a valid mm.

This patch implements a small helper function that does things
correctly, i.e.:

1. We take the task's lock while whe handle its mm (we can't use
   get_task_mm()/mmput() pair as mmput() might sleep);

2. To catch exited main thread case, we use find_lock_task_mm(),
   which walks up all threads and returns an appropriate task
   (with task lock held).

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 include/linux/cpu.h |    1 +
 kernel/cpu.c        |   18 ++++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 1f65875..941e865 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -171,6 +171,7 @@ extern void put_online_cpus(void);
 #define hotcpu_notifier(fn, pri)	cpu_notifier(fn, pri)
 #define register_hotcpu_notifier(nb)	register_cpu_notifier(nb)
 #define unregister_hotcpu_notifier(nb)	unregister_cpu_notifier(nb)
+void clear_tasks_mm_cpumask(int cpu);
 int cpu_down(unsigned int cpu);
 
 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 2060c6e..5255936 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -10,6 +10,7 @@
 #include <linux/sched.h>
 #include <linux/unistd.h>
 #include <linux/cpu.h>
+#include <linux/oom.h>
 #include <linux/export.h>
 #include <linux/kthread.h>
 #include <linux/stop_machine.h>
@@ -171,6 +172,23 @@ void __ref unregister_cpu_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_cpu_notifier);
 
+void clear_tasks_mm_cpumask(int cpu)
+{
+	struct task_struct *p;
+
+	read_lock(&tasklist_lock);
+	for_each_process(p) {
+		struct task_struct *t;
+
+		t = find_lock_task_mm(p);
+		if (!t)
+			continue;
+		cpumask_clear_cpu(cpu, mm_cpumask(t->mm));
+		task_unlock(t);
+	}
+	read_unlock(&tasklist_lock);
+}
+
 static inline void check_for_tasks(int cpu)
 {
 	struct task_struct *p;
-- 
1.7.9.2



From anton.vorontsov at linaro.org  Sat Mar 24 06:28:08 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 14:28:08 +0400
Subject: [PATCH 02/10] arm: Use clear_tasks_mm_cpumask()
In-Reply-To: <20120324102609.GA28356@lizard>
References: <20120324102609.GA28356@lizard>
Message-ID: <20120324102808.GB29067@lizard>

Current CPU hotplug code has some task->mm handling issues:

1. Working with task->mm w/o getting mm or grabing the task lock is
   dangerous as ->mm might disappear (exit_mm() assigns NULL under
   task_lock(), so tasklist lock is not enough).

   We can't use get_task_mm()/mmput() pair as mmput() might sleep,
   so we must take the task lock while handle its mm.

2. Checking for process->mm is not enough because process' main
   thread may exit or detach its mm via use_mm(), but other threads
   may still have a valid mm.

   To fix this we would need to use find_lock_task_mm(), which would
   walk up all threads and returns an appropriate task (with task
   lock held).

clear_tasks_mm_cpumask() has all the issues fixed, so let's use it.

Suggested-by: Oleg Nesterov <oleg at redhat.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/arm/kernel/smp.c |    8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index cdeb727..880b93a 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -136,7 +136,6 @@ static void percpu_timer_stop(void);
 int __cpu_disable(void)
 {
 	unsigned int cpu = smp_processor_id();
-	struct task_struct *p;
 	int ret;
 
 	ret = platform_cpu_disable(cpu);
@@ -166,12 +165,7 @@ int __cpu_disable(void)
 	flush_cache_all();
 	local_flush_tlb_all();
 
-	read_lock(&tasklist_lock);
-	for_each_process(p) {
-		if (p->mm)
-			cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
-	}
-	read_unlock(&tasklist_lock);
+	clear_tasks_mm_cpumask(cpu);
 
 	return 0;
 }
-- 
1.7.9.2



From anton.vorontsov at linaro.org  Sat Mar 24 06:28:31 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 14:28:31 +0400
Subject: [PATCH 03/10] powerpc: Use clear_tasks_mm_cpumask()
In-Reply-To: <20120324102609.GA28356@lizard>
References: <20120324102609.GA28356@lizard>
Message-ID: <20120324102831.GC29067@lizard>

Current CPU hotplug code has some task->mm handling issues:

1. Working with task->mm w/o getting mm or grabing the task lock is
   dangerous as ->mm might disappear (exit_mm() assigns NULL under
   task_lock(), so tasklist lock is not enough).

   We can't use get_task_mm()/mmput() pair as mmput() might sleep,
   so we must take the task lock while handle its mm.

2. Checking for process->mm is not enough because process' main
   thread may exit or detach its mm via use_mm(), but other threads
   may still have a valid mm.

   To fix this we would need to use find_lock_task_mm(), which would
   walk up all threads and returns an appropriate task (with task
   lock held).

clear_tasks_mm_cpumask() has all the issues fixed, so let's use it.

Suggested-by: Oleg Nesterov <oleg at redhat.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/powerpc/mm/mmu_context_nohash.c |   11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index 5b63bd3..e779642 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -333,9 +333,7 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
 					    unsigned long action, void *hcpu)
 {
 	unsigned int cpu = (unsigned int)(long)hcpu;
-#ifdef CONFIG_HOTPLUG_CPU
-	struct task_struct *p;
-#endif
+
 	/* We don't touch CPU 0 map, it's allocated at aboot and kept
 	 * around forever
 	 */
@@ -358,12 +356,7 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
 		stale_map[cpu] = NULL;
 
 		/* We also clear the cpu_vm_mask bits of CPUs going away */
-		read_lock(&tasklist_lock);
-		for_each_process(p) {
-			if (p->mm)
-				cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
-		}
-		read_unlock(&tasklist_lock);
+		clear_tasks_mm_cpumask(cpu);
 	break;
 #endif /* CONFIG_HOTPLUG_CPU */
 	}
-- 
1.7.9.2



From anton.vorontsov at linaro.org  Sat Mar 24 06:28:59 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 14:28:59 +0400
Subject: [PATCH 04/10] sh: Use clear_tasks_mm_cpumask()
In-Reply-To: <20120324102609.GA28356@lizard>
References: <20120324102609.GA28356@lizard>
Message-ID: <20120324102859.GD29067@lizard>

Current CPU hotplug code has some task->mm handling issues:

1. Working with task->mm w/o getting mm or grabing the task lock is
   dangerous as ->mm might disappear (exit_mm() assigns NULL under
   task_lock(), so tasklist lock is not enough).

   We can't use get_task_mm()/mmput() pair as mmput() might sleep,
   so we must take the task lock while handle its mm.

2. Checking for process->mm is not enough because process' main
   thread may exit or detach its mm via use_mm(), but other threads
   may still have a valid mm.

   To fix this we would need to use find_lock_task_mm(), which would
   walk up all threads and returns an appropriate task (with task
   lock held).

clear_tasks_mm_cpumask() has all the issues fixed, so let's use it.

Suggested-by: Oleg Nesterov <oleg at redhat.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/sh/kernel/smp.c |    7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
index f624174..2470c83 100644
--- a/arch/sh/kernel/smp.c
+++ b/arch/sh/kernel/smp.c
@@ -123,7 +123,6 @@ void native_play_dead(void)
 int __cpu_disable(void)
 {
 	unsigned int cpu = smp_processor_id();
-	struct task_struct *p;
 	int ret;
 
 	ret = mp_ops->cpu_disable(cpu);
@@ -153,11 +152,7 @@ int __cpu_disable(void)
 	flush_cache_all();
 	local_flush_tlb_all();
 
-	read_lock(&tasklist_lock);
-	for_each_process(p)
-		if (p->mm)
-			cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
-	read_unlock(&tasklist_lock);
+	clear_tasks_mm_cpumask(cpu);
 
 	return 0;
 }
-- 
1.7.9.2



From anton.vorontsov at linaro.org  Sat Mar 24 06:29:39 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 14:29:39 +0400
Subject: [PATCH 05/10] blackfin: A couple of task->mm handling fixes
In-Reply-To: <20120324102609.GA28356@lizard>
References: <20120324102609.GA28356@lizard>
Message-ID: <20120324102939.GE29067@lizard>

The patch fixes two problems:

1. Working with task->mm w/o getting mm or grabing the task lock is
   dangerous as ->mm might disappear (exit_mm() assigns NULL under
   task_lock(), so tasklist lock is not enough).

   We can't use get_task_mm()/mmput() pair as mmput() might sleep,
   so we have to take the task lock while handle its mm.

2. Checking for process->mm is not enough because process' main
   thread may exit or detach its mm via use_mm(), but other threads
   may still have a valid mm.

   To catch this we use find_lock_task_mm(), which walks up all
   threads and returns an appropriate task (with task lock held).

Suggested-by: Oleg Nesterov <oleg at redhat.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/blackfin/kernel/trace.c |   26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c
index 050db44..5102cdf 100644
--- a/arch/blackfin/kernel/trace.c
+++ b/arch/blackfin/kernel/trace.c
@@ -10,6 +10,8 @@
 #include <linux/hardirq.h>
 #include <linux/thread_info.h>
 #include <linux/mm.h>
+#include <linux/oom.h>
+#include <linux/sched.h>
 #include <linux/uaccess.h>
 #include <linux/module.h>
 #include <linux/kallsyms.h>
@@ -27,7 +29,6 @@ void decode_address(char *buf, unsigned long address)
 	struct task_struct *p;
 	struct mm_struct *mm;
 	unsigned long flags, offset;
-	unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
 	struct rb_node *n;
 
 #ifdef CONFIG_KALLSYMS
@@ -113,15 +114,15 @@ void decode_address(char *buf, unsigned long address)
 	 */
 	write_lock_irqsave(&tasklist_lock, flags);
 	for_each_process(p) {
-		mm = (in_atomic ? p->mm : get_task_mm(p));
-		if (!mm)
-			continue;
+		struct task_struct *t;
 
-		if (!down_read_trylock(&mm->mmap_sem)) {
-			if (!in_atomic)
-				mmput(mm);
+		t = find_lock_task_mm(p);
+		if (!t)
 			continue;
-		}
+
+		mm = t->mm;
+		if (!down_read_trylock(&mm->mmap_sem))
+			goto __continue;
 
 		for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
 			struct vm_area_struct *vma;
@@ -130,7 +131,7 @@ void decode_address(char *buf, unsigned long address)
 
 			if (address >= vma->vm_start && address < vma->vm_end) {
 				char _tmpbuf[256];
-				char *name = p->comm;
+				char *name = t->comm;
 				struct file *file = vma->vm_file;
 
 				if (file) {
@@ -163,8 +164,7 @@ void decode_address(char *buf, unsigned long address)
 						name, vma->vm_start, vma->vm_end);
 
 				up_read(&mm->mmap_sem);
-				if (!in_atomic)
-					mmput(mm);
+				task_unlock(t);
 
 				if (buf[0] == '\0')
 					sprintf(buf, "[ %s ] dynamic memory", name);
@@ -174,8 +174,8 @@ void decode_address(char *buf, unsigned long address)
 		}
 
 		up_read(&mm->mmap_sem);
-		if (!in_atomic)
-			mmput(mm);
+__continue:
+		task_unlock(t);
 	}
 
 	/*
-- 
1.7.9.2



From anton.vorontsov at linaro.org  Sat Mar 24 06:30:08 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 14:30:08 +0400
Subject: [PATCH 06/10] blackfin: Fix possible deadlock in decode_address()
In-Reply-To: <20120324102609.GA28356@lizard>
References: <20120324102609.GA28356@lizard>
Message-ID: <20120324103008.GF29067@lizard>

Oleg Nesterov found an interesting deadlock possibility:

> sysrq_showregs_othercpus() does smp_call_function(showacpu)
> and showacpu() show_stack()->decode_address(). Now suppose that IPI
> interrupts the task holding read_lock(tasklist).

To fix this, blackfin should not grab the write_ variant of the
tasklist lock, read_ one is enough.

Suggested-by: Oleg Nesterov <oleg at redhat.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/blackfin/kernel/trace.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c
index 5102cdf..9cc9302 100644
--- a/arch/blackfin/kernel/trace.c
+++ b/arch/blackfin/kernel/trace.c
@@ -28,7 +28,7 @@ void decode_address(char *buf, unsigned long address)
 {
 	struct task_struct *p;
 	struct mm_struct *mm;
-	unsigned long flags, offset;
+	unsigned long offset;
 	struct rb_node *n;
 
 #ifdef CONFIG_KALLSYMS
@@ -112,7 +112,7 @@ void decode_address(char *buf, unsigned long address)
 	 * mappings of all our processes and see if we can't be a whee
 	 * bit more specific
 	 */
-	write_lock_irqsave(&tasklist_lock, flags);
+	read_lock(&tasklist_lock);
 	for_each_process(p) {
 		struct task_struct *t;
 
@@ -185,7 +185,7 @@ __continue:
 	sprintf(buf, "/* kernel dynamic memory */");
 
 done:
-	write_unlock_irqrestore(&tasklist_lock, flags);
+	read_unlock(&tasklist_lock);
 }
 
 #define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
-- 
1.7.9.2



From anton.vorontsov at linaro.org  Sat Mar 24 06:30:30 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 14:30:30 +0400
Subject: [PATCH 07/10] um: Should hold tasklist_lock while traversing processes
In-Reply-To: <20120324102609.GA28356@lizard>
References: <20120324102609.GA28356@lizard>
Message-ID: <20120324103030.GG29067@lizard>

Traversing the tasks requires holding tasklist_lock, otherwise it
is unsafe.

p.s. However, I'm not sure that calling os_kill_ptraced_process()
in the atomic context is correct. It seem to work, but please
take a closer look.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/um/kernel/reboot.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/um/kernel/reboot.c b/arch/um/kernel/reboot.c
index 4d93dff..66d754c 100644
--- a/arch/um/kernel/reboot.c
+++ b/arch/um/kernel/reboot.c
@@ -4,6 +4,7 @@
  */
 
 #include "linux/sched.h"
+#include "linux/spinlock.h"
 #include "linux/slab.h"
 #include "kern_util.h"
 #include "os.h"
@@ -22,6 +23,7 @@ static void kill_off_processes(void)
 		struct task_struct *p;
 		int pid;
 
+		read_lock(&tasklist_lock);
 		for_each_process(p) {
 			if (p->mm == NULL)
 				continue;
@@ -29,6 +31,7 @@ static void kill_off_processes(void)
 			pid = p->mm->context.id.u.pid;
 			os_kill_ptraced_process(pid, 1);
 		}
+		read_unlock(&tasklist_lock);
 	}
 }
 
-- 
1.7.9.2



From anton.vorontsov at linaro.org  Sat Mar 24 06:30:50 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 14:30:50 +0400
Subject: [PATCH 08/10] um: Fix possible race on task->mm
In-Reply-To: <20120324102609.GA28356@lizard>
References: <20120324102609.GA28356@lizard>
Message-ID: <20120324103050.GH29067@lizard>

Checking for task->mm is dangerous as ->mm might disappear (exit_mm()
assigns NULL under task_lock(), so tasklist lock is not enough).

We can't use get_task_mm()/mmput() pair as mmput() might sleep,
so let's take the task lock while we care about its mm.

Note that we should also use find_lock_task_mm() to check all process'
threads for a valid mm, but for uml we'll do it in a separate patch.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/um/kernel/reboot.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/um/kernel/reboot.c b/arch/um/kernel/reboot.c
index 66d754c..1411f4e 100644
--- a/arch/um/kernel/reboot.c
+++ b/arch/um/kernel/reboot.c
@@ -25,10 +25,13 @@ static void kill_off_processes(void)
 
 		read_lock(&tasklist_lock);
 		for_each_process(p) {
-			if (p->mm == NULL)
+			task_lock(p);
+			if (!p->mm) {
+				task_unlock(p);
 				continue;
-
+			}
 			pid = p->mm->context.id.u.pid;
+			task_unlock(p);
 			os_kill_ptraced_process(pid, 1);
 		}
 		read_unlock(&tasklist_lock);
-- 
1.7.9.2



From anton.vorontsov at linaro.org  Sat Mar 24 06:31:10 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 14:31:10 +0400
Subject: [PATCH 09/10] um: Properly check all process' threads for a live mm
In-Reply-To: <20120324102609.GA28356@lizard>
References: <20120324102609.GA28356@lizard>
Message-ID: <20120324103110.GI29067@lizard>

kill_off_processes() might miss a valid process, this is because
checking for process->mm is not enough. Process' main thread may
exit or detach its mm via use_mm(), but other threads may still
have a valid mm.

To catch this we use find_lock_task_mm(), which walks up all
threads and returns an appropriate task (with task lock held).

Suggested-by: Oleg Nesterov <oleg at redhat.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---
 arch/um/kernel/reboot.c |   13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/um/kernel/reboot.c b/arch/um/kernel/reboot.c
index 1411f4e..3d15243 100644
--- a/arch/um/kernel/reboot.c
+++ b/arch/um/kernel/reboot.c
@@ -6,6 +6,7 @@
 #include "linux/sched.h"
 #include "linux/spinlock.h"
 #include "linux/slab.h"
+#include "linux/oom.h"
 #include "kern_util.h"
 #include "os.h"
 #include "skas.h"
@@ -25,13 +26,13 @@ static void kill_off_processes(void)
 
 		read_lock(&tasklist_lock);
 		for_each_process(p) {
-			task_lock(p);
-			if (!p->mm) {
-				task_unlock(p);
+			struct task_struct *t;
+
+			t = find_lock_task_mm(p);
+			if (!t)
 				continue;
-			}
-			pid = p->mm->context.id.u.pid;
-			task_unlock(p);
+			pid = t->mm->context.id.u.pid;
+			task_unlock(t);
 			os_kill_ptraced_process(pid, 1);
 		}
 		read_unlock(&tasklist_lock);
-- 
1.7.9.2



From anton.vorontsov at linaro.org  Sat Mar 24 06:31:27 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 14:31:27 +0400
Subject: [PATCH 10/10] oom: Make find_lock_task_mm() sparse-aware
In-Reply-To: <20120324102609.GA28356@lizard>
References: <20120324102609.GA28356@lizard>
Message-ID: <20120324103127.GJ29067@lizard>

This is needed so that callers would not get 'context imbalance'
warnings from the sparse tool.

As a side effect, this patch fixes the following sparse warnings:

  CHECK   mm/oom_kill.c
  mm/oom_kill.c:201:28: warning: context imbalance in 'oom_badness' -
  unexpected unlock
  include/linux/rcupdate.h:249:30: warning: context imbalance in
  'dump_tasks' - unexpected unlock
  mm/oom_kill.c:453:9: warning: context imbalance in 'oom_kill_task' -
  unexpected unlock
  CHECK   mm/memcontrol.c
  ...
  mm/memcontrol.c:1130:17: warning: context imbalance in
  'task_in_mem_cgroup' - unexpected unlock

p.s. I know Peter Zijlstra detest the __cond_lock() stuff, but untill
     we have anything better in sparse, let's use it. This particular
     patch helped me to detect one bug that I myself made during
     task->mm fixup series. So, it is useful.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
Acked-by: KOSAKI Motohiro <kosaki.motohiro at jp.fujitsu.com>
---
 include/linux/oom.h |   12 +++++++++++-
 mm/oom_kill.c       |    2 +-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/include/linux/oom.h b/include/linux/oom.h
index 552fba9..26cf628 100644
--- a/include/linux/oom.h
+++ b/include/linux/oom.h
@@ -21,6 +21,7 @@
 
 #ifdef __KERNEL__
 
+#include <linux/compiler.h>
 #include <linux/sched.h>
 #include <linux/types.h>
 #include <linux/nodemask.h>
@@ -65,7 +66,16 @@ static inline void oom_killer_enable(void)
 	oom_killer_disabled = false;
 }
 
-extern struct task_struct *find_lock_task_mm(struct task_struct *p);
+extern struct task_struct *__find_lock_task_mm(struct task_struct *p);
+
+static inline struct task_struct *find_lock_task_mm(struct task_struct *p)
+{
+	struct task_struct *ret;
+
+	ret = __find_lock_task_mm(p);
+	(void)__cond_lock(&ret->alloc_lock, ret);
+	return ret;
+}
 
 /* sysctls */
 extern int sysctl_oom_dump_tasks;
diff --git a/mm/oom_kill.c b/mm/oom_kill.c
index 2958fd8..0ebb383 100644
--- a/mm/oom_kill.c
+++ b/mm/oom_kill.c
@@ -136,7 +136,7 @@ static bool has_intersects_mems_allowed(struct task_struct *tsk,
  * pointer.  Return p, or any of its subthreads with a valid ->mm, with
  * task_lock() held.
  */
-struct task_struct *find_lock_task_mm(struct task_struct *p)
+struct task_struct *__find_lock_task_mm(struct task_struct *p)
 {
 	struct task_struct *t = p;
 
-- 
1.7.9.2


From richard at nod.at  Sat Mar 24 07:12:21 2012
From: richard at nod.at (Richard Weinberger)
Date: Sat, 24 Mar 2012 12:12:21 +0100
Subject: [PATCH 09/10] um: Properly check all process' threads for a live
 mm
In-Reply-To: <20120324103110.GI29067@lizard>
References: <20120324102609.GA28356@lizard> <20120324103110.GI29067@lizard>
Message-ID: <4F6DAC15.7040702@nod.at>

Am 24.03.2012 11:31, schrieb Anton Vorontsov:
> kill_off_processes() might miss a valid process, this is because
> checking for process->mm is not enough. Process' main thread may
> exit or detach its mm via use_mm(), but other threads may still
> have a valid mm.
> 
> To catch this we use find_lock_task_mm(), which walks up all
> threads and returns an appropriate task (with task lock held).
> 
> Suggested-by: Oleg Nesterov <oleg at redhat.com>
> Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>

Acked-by: Richard Weinberger <richard at nod.at>

Thanks,
//richard

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From richard at nod.at  Sat Mar 24 07:12:12 2012
From: richard at nod.at (Richard Weinberger)
Date: Sat, 24 Mar 2012 12:12:12 +0100
Subject: [PATCH 08/10] um: Fix possible race on task->mm
In-Reply-To: <20120324103050.GH29067@lizard>
References: <20120324102609.GA28356@lizard> <20120324103050.GH29067@lizard>
Message-ID: <4F6DAC0C.4010203@nod.at>

Am 24.03.2012 11:30, schrieb Anton Vorontsov:
> Checking for task->mm is dangerous as ->mm might disappear (exit_mm()
> assigns NULL under task_lock(), so tasklist lock is not enough).
> 
> We can't use get_task_mm()/mmput() pair as mmput() might sleep,
> so let's take the task lock while we care about its mm.
> 
> Note that we should also use find_lock_task_mm() to check all process'
> threads for a valid mm, but for uml we'll do it in a separate patch.
> 
> Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>

Acked-by: Richard Weinberger <richard at nod.at>

Thanks,
//richard

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From richard at nod.at  Sat Mar 24 07:12:40 2012
From: richard at nod.at (Richard Weinberger)
Date: Sat, 24 Mar 2012 12:12:40 +0100
Subject: [PATCH 07/10] um: Should hold tasklist_lock while traversing
 processes
In-Reply-To: <20120324103030.GG29067@lizard>
References: <20120324102609.GA28356@lizard> <20120324103030.GG29067@lizard>
Message-ID: <4F6DAC28.301@nod.at>

Am 24.03.2012 11:30, schrieb Anton Vorontsov:
> Traversing the tasks requires holding tasklist_lock, otherwise it
> is unsafe.
> 
> p.s. However, I'm not sure that calling os_kill_ptraced_process()
> in the atomic context is correct. It seem to work, but please
> take a closer look.

os_kill_ptraced_process() calls a host function.
From UML's point of view nothing sleeps, so this is fine.

Acked-by: Richard Weinberger <richard at nod.at>

Thanks,
//richard

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From a.p.zijlstra at chello.nl  Sat Mar 24 08:43:41 2012
From: a.p.zijlstra at chello.nl (Peter Zijlstra)
Date: Sat, 24 Mar 2012 13:43:41 +0100
Subject: [PATCH 01/10] cpu: Introduce clear_tasks_mm_cpumask() helper
In-Reply-To: <20120324102751.GA29067@lizard>
References: <20120324102609.GA28356@lizard> <20120324102751.GA29067@lizard>
Message-ID: <1332593021.16159.27.camel@twins>

On Sat, 2012-03-24 at 14:27 +0400, Anton Vorontsov wrote:
> +void clear_tasks_mm_cpumask(int cpu)
> +{
> +       struct task_struct *p;
> +
> +       read_lock(&tasklist_lock);
> +       for_each_process(p) {
> +               struct task_struct *t;
> +
> +               t = find_lock_task_mm(p);
> +               if (!t)
> +                       continue;
> +               cpumask_clear_cpu(cpu, mm_cpumask(t->mm));
> +               task_unlock(t);
> +       }
> +       read_unlock(&tasklist_lock);
> +} 

Why bother with the tasklist_lock at all anymore, afaict you could use
rcu_read_lock() here. This all is called after the cpu is taken down and
marked offline, so its not like new tasks will ever get this cpu set in
their mm mask.




From a.p.zijlstra at chello.nl  Sat Mar 24 08:48:23 2012
From: a.p.zijlstra at chello.nl (Peter Zijlstra)
Date: Sat, 24 Mar 2012 13:48:23 +0100
Subject: [PATCH 07/10] um: Should hold tasklist_lock while traversing
 processes
In-Reply-To: <20120324103030.GG29067@lizard>
References: <20120324102609.GA28356@lizard> <20120324103030.GG29067@lizard>
Message-ID: <1332593303.16159.28.camel@twins>

On Sat, 2012-03-24 at 14:30 +0400, Anton Vorontsov wrote:
> Traversing the tasks requires holding tasklist_lock, otherwise it
> is unsafe. 

No it doesn't, it either requires tasklist_lock or rcu_read_lock().


From a.p.zijlstra at chello.nl  Sat Mar 24 08:52:54 2012
From: a.p.zijlstra at chello.nl (Peter Zijlstra)
Date: Sat, 24 Mar 2012 13:52:54 +0100
Subject: [PATCH 10/10] oom: Make find_lock_task_mm() sparse-aware
In-Reply-To: <20120324103127.GJ29067@lizard>
References: <20120324102609.GA28356@lizard> <20120324103127.GJ29067@lizard>
Message-ID: <1332593574.16159.31.camel@twins>

On Sat, 2012-03-24 at 14:31 +0400, Anton Vorontsov wrote:
> This is needed so that callers would not get 'context imbalance'
> warnings from the sparse tool.
> 
> As a side effect, this patch fixes the following sparse warnings:
> 
>   CHECK   mm/oom_kill.c
>   mm/oom_kill.c:201:28: warning: context imbalance in 'oom_badness' -
>   unexpected unlock
>   include/linux/rcupdate.h:249:30: warning: context imbalance in
>   'dump_tasks' - unexpected unlock
>   mm/oom_kill.c:453:9: warning: context imbalance in 'oom_kill_task' -
>   unexpected unlock
>   CHECK   mm/memcontrol.c
>   ...
>   mm/memcontrol.c:1130:17: warning: context imbalance in
>   'task_in_mem_cgroup' - unexpected unlock
> 
> p.s. I know Peter Zijlstra detest the __cond_lock() stuff, but untill
>      we have anything better in sparse, let's use it. This particular
>      patch helped me to detect one bug that I myself made during
>      task->mm fixup series. So, it is useful.

Yeah, so Nacked-by: Peter Zijlstra <a.p.zijlstra at chello.nl>

Also, why didn't lockdep catch it?

Fix sparse already instead of smearing ugly all over.


From jm at lentin.co.uk  Sat Mar 24 09:14:33 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sat, 24 Mar 2012 13:14:33 +0000
Subject: [PATCH V2 0/3] Add support for DNS-320 and DNS-325 using devicetree
Message-ID: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>

Thankyou to Arnd and Jason for taking the time to review, sorry it's taken a
while to get back to you both with an updated version.

Changes since v1:
* Rebase against kirkwood_dt_for_3.4, removing premature devicetree ports.
* Move additions into a separate board-dnskw.c. It could be separated further
  into a board-dns320.c and board-dns325.c but it probably isn't worth it.
* s/marvell,/mrvl,/g
* Include an example dtb partition in documentation
* Copy structure of serial nodes to allow common options for NAND to be set
  in kirkwood.dtsi
* Simplifications in orion-nand.c
    
I looked into adding a dtb partition into the d-link partition scheme. However
D-Link supplied userland references all partitions by number and there isn't
any obvious space that would be safe to use. Regardless, if you still have
D-Link userland around, you probably still have D-Link u-boot, which won't load
the dtb for you anyway.

Jamie Lentin (3):
  ARM: kirkwood: Basic support for DNS-320 and DNS-325
  ARM: kirkwood: Convert orion-nand to fdt
  ARM: kirkwood: Define NAND partitions in dts

 .../devicetree/bindings/mtd/orion-nand.txt         |   46 ++++
 arch/arm/boot/dts/kirkwood-dns320.dts              |   64 +++++
 arch/arm/boot/dts/kirkwood-dns325.dts              |   59 +++++
 arch/arm/boot/dts/kirkwood.dtsi                    |   15 +-
 arch/arm/mach-kirkwood/Kconfig                     |   23 ++
 arch/arm/mach-kirkwood/Makefile                    |    1 +
 arch/arm/mach-kirkwood/Makefile.boot               |    2 +
 arch/arm/mach-kirkwood/board-dnskw.c               |  275 ++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c                  |    5 +
 arch/arm/mach-kirkwood/common.c                    |   12 +
 arch/arm/mach-kirkwood/common.h                    |    6 +
 drivers/mtd/nand/orion_nand.c                      |   34 +++-
 12 files changed, 539 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt
 create mode 100644 arch/arm/boot/dts/kirkwood-dns320.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-dns325.dts
 create mode 100644 arch/arm/mach-kirkwood/board-dnskw.c

-- 
1.7.9.1



From jm at lentin.co.uk  Sat Mar 24 09:14:36 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sat, 24 Mar 2012 13:14:36 +0000
Subject: [PATCH V2 3/3] ARM: kirkwood: Define NAND partitions in dts
In-Reply-To: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1332594876-8673-4-git-send-email-jm@lentin.co.uk>

Use devicetree to define NAND partitions. Use D-link partition scheme by
default, to be vaguely compatible with their userland.

Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
 arch/arm/boot/dts/kirkwood-dns320.dts |   35 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-dns325.dts |   35 +++++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dnskw.c  |   31 -----------------------------
 3 files changed, 70 insertions(+), 31 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index 58de7f2..fbf55ff 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -25,5 +25,40 @@
 			clock-frequency = <166666667>;
 			status = "ok";
 		};
+
+		nand at 3000000 {
+			status = "ok";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x0100000 0x500000>;
+			};
+
+			partition at 600000 {
+				label = "ramdisk";
+				reg = <0x0600000 0x500000>;
+			};
+
+			partition at b00000 {
+				label = "image";
+				reg = <0x0b00000 0x6600000>;
+			};
+
+			partition at 7100000 {
+				label = "mini firmware";
+				reg = <0x7100000 0xa00000>;
+			};
+
+			partition at 7b00000 {
+				label = "config";
+				reg = <0x7b00000 0x500000>;
+			};
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index 79b1133..b6238db 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -20,5 +20,40 @@
 			clock-frequency = <200000000>;
 			status = "ok";
 		};
+
+		nand at 3000000 {
+			status = "ok";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x0100000 0x500000>;
+			};
+
+			partition at 600000 {
+				label = "ramdisk";
+				reg = <0x0600000 0x500000>;
+			};
+
+			partition at b00000 {
+				label = "image";
+				reg = <0x0b00000 0x6600000>;
+			};
+
+			partition at 7100000 {
+				label = "mini firmware";
+				reg = <0x7100000 0xa00000>;
+			};
+
+			partition at 7b00000 {
+				label = "config";
+				reg = <0x7b00000 0x500000>;
+			};
+		};
 	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 7cb7f6a..dc4e80a 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -23,7 +23,6 @@
 #include <linux/gpio_keys.h>
 #include <linux/gpio-fan.h>
 #include <linux/leds.h>
-#include <linux/mtd/physmap.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,35 +31,6 @@
 #include "common.h"
 #include "mpp.h"
 
-static struct mtd_partition dnskw_nand_parts[] = {
-	{
-		.name		= "u-boot",
-		.offset		= 0,
-		.size		= SZ_1M,
-		.mask_flags	= MTD_WRITEABLE
-	}, {
-		.name		= "uImage",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	}, {
-		.name		= "ramdisk",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	}, {
-		.name		= "image",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 102 * SZ_1M
-	}, {
-		.name		= "mini firmware",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 10 * SZ_1M
-	}, {
-		.name		= "config",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	},
-};
-
 static struct mv643xx_eth_platform_data dnskw_ge00_data = {
 	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
 };
@@ -272,7 +242,6 @@ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
 void __init dnskw_init(void)
 {
 	kirkwood_mpp_conf(dnskw_mpp_config);
-	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
 
 	kirkwood_ehci_init();
 	kirkwood_ge00_init(&dnskw_ge00_data);
-- 
1.7.9.1



From jm at lentin.co.uk  Sat Mar 24 09:14:35 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sat, 24 Mar 2012 13:14:35 +0000
Subject: [PATCH V2 2/3] ARM: kirkwood: Convert orion-nand to fdt
In-Reply-To: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1332594876-8673-3-git-send-email-jm@lentin.co.uk>

Convert orion-nand to use fdt and add common setup to kirkwood.dtsi, including
a default value for chip-delay (all current boards seem to use 25 anyway).

Add placeholder documentation for the bindings, for someone more knowledgable
than me to fill in the details of the properties.

Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
 .../devicetree/bindings/mtd/orion-nand.txt         |   46 ++++++++++++++++++++
 arch/arm/boot/dts/kirkwood.dtsi                    |   15 ++++++-
 arch/arm/mach-kirkwood/common.c                    |   12 +++++
 drivers/mtd/nand/orion_nand.c                      |   34 ++++++++++++++-
 4 files changed, 104 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
new file mode 100644
index 0000000..d347999
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/orion-nand.txt
@@ -0,0 +1,46 @@
+NAND support for Marvell Orion SoC platforms
+
+Required properties:
+- compatible : "mrvl,orion-nand".
+- reg : Base physical address of the NAND and length of memory mapped
+	region
+
+Optional properties:
+- cle :
+- ale :
+- width :
+- chip-delay :
+
+Examples:
+
+nand at f4000000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cle = <0>;
+	ale = <1>;
+	width = <8>;
+	chip-delay = <25>;
+	compatible = "mrvl,orion-nand";
+	reg = <0xf4000000 0x400>;
+
+	partition at 0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+		read-only;
+	};
+
+	partition at 100000 {
+		label = "uImage";
+		reg = <0x0100000 0x200000>;
+	};
+
+	partition at 300000 {
+		label = "dtb";
+		reg = <0x0300000 0x100000>;
+	};
+
+	partition at 400000 {
+		label = "root";
+		reg = <0x0400000 0x7d00000>;
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 3474ef8..82ffc3e 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -5,7 +5,7 @@
 
 	ocp at f1000000 {
 		compatible = "simple-bus";
-		ranges = <0 0xf1000000 0x1000000>;
+		ranges = <0 0xf1000000 0x4000000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
@@ -32,5 +32,18 @@
 			reg = <0x10300 0x20>;
 			interrupts = <53>;
 		};
+
+		nand at 3000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cle = <0>;
+			ale = <1>;
+			width = <8>;
+			compatible = "mrvl,orion-nand";
+			reg = <0x3000000 0x400>;
+			chip-delay = <25>;
+			/* set partition map and/or chip-delay in board dts */
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index a02cae8..3ad0373 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -15,6 +15,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mtd/nand.h>
 #include <linux/dma-mapping.h>
+#include <linux/of.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -482,6 +483,9 @@ static int __init kirkwood_clock_gate(void)
 	unsigned int curr = readl(CLOCK_GATING_CTRL);
 	u32 dev, rev;
 
+#ifdef CONFIG_OF
+	struct device_node *np;
+#endif
 	kirkwood_pcie_id(&dev, &rev);
 	printk(KERN_DEBUG "Gating clock of unused units\n");
 	printk(KERN_DEBUG "before: 0x%08x\n", curr);
@@ -489,6 +493,14 @@ static int __init kirkwood_clock_gate(void)
 	/* Make sure those units are accessible */
 	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 
+#ifdef CONFIG_OF
+	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-nand");
+	if (np && of_device_is_available(np)) {
+		kirkwood_clk_ctrl |= CGC_RUNIT;
+		of_node_put(np);
+	}
+#endif
+
 	/* For SATA: first shutdown the phy */
 	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
 		/* Disable PLL and IVREF */
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index 29f505a..4cb0244 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -13,6 +13,7 @@
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
@@ -74,11 +75,13 @@ static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 static int __init orion_nand_probe(struct platform_device *pdev)
 {
 	struct mtd_info *mtd;
+	struct mtd_part_parser_data ppdata = {};
 	struct nand_chip *nc;
 	struct orion_nand_data *board;
 	struct resource *res;
 	void __iomem *io_base;
 	int ret = 0;
+	u32 val = 0;
 
 	nc = kzalloc(sizeof(struct nand_chip) + sizeof(struct mtd_info), GFP_KERNEL);
 	if (!nc) {
@@ -101,7 +104,25 @@ static int __init orion_nand_probe(struct platform_device *pdev)
 		goto no_res;
 	}
 
-	board = pdev->dev.platform_data;
+	if (pdev->dev.of_node) {
+		board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data),
+					GFP_KERNEL);
+		if (!board) {
+			printk(KERN_ERR "orion_nand: failed to allocate board structure.\n");
+			ret = -ENOMEM;
+			goto no_res;
+		}
+		if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
+			board->cle = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
+			board->ale = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node, "width", &val))
+			board->width = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node,
+						"chip-delay", &val))
+			board->chip_delay = (u8)val;
+	} else
+		board = pdev->dev.platform_data;
 
 	mtd->priv = nc;
 	mtd->owner = THIS_MODULE;
@@ -129,7 +150,8 @@ static int __init orion_nand_probe(struct platform_device *pdev)
 	}
 
 	mtd->name = "orion_nand";
-	ret = mtd_device_parse_register(mtd, NULL, 0,
+	ppdata.of_node = pdev->dev.of_node;
+	ret = mtd_device_parse_register(mtd, NULL, &ppdata,
 			board->parts, board->nr_parts);
 	if (ret) {
 		nand_release(mtd);
@@ -161,11 +183,19 @@ static int __devexit orion_nand_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id orion_nand_of_match_table[] = {
+	{ .compatible = "mrvl,orion-nand", },
+	{},
+};
+#endif
+
 static struct platform_driver orion_nand_driver = {
 	.remove		= __devexit_p(orion_nand_remove),
 	.driver		= {
 		.name	= "orion_nand",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(orion_nand_of_match_table),
 	},
 };
 
-- 
1.7.9.1



From jm at lentin.co.uk  Sat Mar 24 09:14:34 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sat, 24 Mar 2012 13:14:34 +0000
Subject: [PATCH V2 1/3] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1332594876-8673-2-git-send-email-jm@lentin.co.uk>

Add support for the DNS-320 and DNS-325. Describe as much as currently possible
in the devicetree files, create a board-dnskw.c for everything else.

Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
 arch/arm/boot/dts/kirkwood-dns320.dts |   29 +++
 arch/arm/boot/dts/kirkwood-dns325.dts |   24 +++
 arch/arm/mach-kirkwood/Kconfig        |   23 +++
 arch/arm/mach-kirkwood/Makefile       |    1 +
 arch/arm/mach-kirkwood/Makefile.boot  |    2 +
 arch/arm/mach-kirkwood/board-dnskw.c  |  306 +++++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c     |    5 +
 arch/arm/mach-kirkwood/common.h       |    6 +
 8 files changed, 396 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-dns320.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-dns325.dts
 create mode 100644 arch/arm/mach-kirkwood/board-dnskw.c

diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
new file mode 100644
index 0000000..58de7f2
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "D-Link DNS-320 NAS (Rev A1)";
+	compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		serial at 12000 {
+			clock-frequency = <166666667>;
+			status = "ok";
+		};
+
+		serial at 12100 {
+			clock-frequency = <166666667>;
+			status = "ok";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
new file mode 100644
index 0000000..79b1133
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "D-Link DNS-325 NAS (Rev A1)";
+	compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "ok";
+		};
+	};
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 90ceab7..d594b6e 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -58,6 +58,29 @@ config MACH_DREAMPLUG_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell DreamPlug (Flattened Device Tree).
 
+config MACH_DNSKW_DT
+        bool
+
+config MACH_DNS320_DT
+	bool "D-Link DNS-320 (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	select MACH_DNSKW_DT
+	select CONFIG_MTD_OF_PARTS
+	select CONFIG_SERIAL_OF_PLATFORM
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  D-Link DNS-320 NAS, using Flattened Device Tree.
+
+config MACH_DNS325_DT
+	bool "D-Link DNS-325 (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	select MACH_DNSKW_DT
+	select CONFIG_MTD_OF_PARTS
+	select CONFIG_SERIAL_OF_PLATFORM
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  D-Link DNS-325 NAS, using Flattened Device Tree.
+
 config MACH_TS219
 	bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
 	help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e299a95..b092af5 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_T5325)		+= t5325-setup.o
 obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_DREAMPLUG_DT)		+= board-dreamplug.o
+obj-$(CONFIG_MACH_DNSKW_DT)		+= board-dnskw.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 16f9385..9c5e45f 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -3,3 +3,5 @@ params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
 
 dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
+dtb-$(CONFIG_MACH_DNS320_DT) += kirkwood-dns320.dtb
+dtb-$(CONFIG_MACH_DNS325_DT) += kirkwood-dns325.dtb
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
new file mode 100644
index 0000000..7cb7f6a
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright 2012 (C), Jamie Lentin <jm at lentin.co.uk>
+ *
+ * arch/arm/mach-kirkwood/board-dnskw.c
+ *
+ * D-link DNS-320 & DNS-325 NAS Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio-fan.h>
+#include <linux/leds.h>
+#include <linux/mtd/physmap.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mtd_partition dnskw_nand_parts[] = {
+	{
+		.name		= "u-boot",
+		.offset		= 0,
+		.size		= SZ_1M,
+		.mask_flags	= MTD_WRITEABLE
+	}, {
+		.name		= "uImage",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 5 * SZ_1M
+	}, {
+		.name		= "ramdisk",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 5 * SZ_1M
+	}, {
+		.name		= "image",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 102 * SZ_1M
+	}, {
+		.name		= "mini firmware",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 10 * SZ_1M
+	}, {
+		.name		= "config",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 5 * SZ_1M
+	},
+};
+
+static struct mv643xx_eth_platform_data dnskw_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
+};
+
+static struct mv_sata_platform_data dnskw_sata_data = {
+	.n_ports	= 2,
+};
+
+static unsigned int dnskw_mpp_config[] __initdata = {
+	MPP13_UART1_TXD,	/* Custom ... */
+	MPP14_UART1_RXD,	/* ... Controller (DNS-320 only) */
+	MPP20_SATA1_ACTn,	/* LED: White Right HDD */
+	MPP21_SATA0_ACTn,	/* LED: White Left HDD */
+	MPP24_GPIO,
+	MPP25_GPIO,
+	MPP26_GPIO,	/* LED: Power */
+	MPP27_GPIO,	/* LED: Red Right HDD */
+	MPP28_GPIO,	/* LED: Red Left HDD */
+	MPP29_GPIO,	/* LED: Red USB (DNS-325 only) */
+	MPP30_GPIO,
+	MPP31_GPIO,
+	MPP32_GPIO,
+	MPP33_GPO,
+	MPP34_GPIO,	/* Button: Front power */
+	MPP35_GPIO,	/* LED: Red USB (DNS-320 only) */
+	MPP36_GPIO,	/* Power: Turn off board */
+	MPP37_GPIO,	/* Power: Turn back on after power failure */
+	MPP38_GPIO,
+	MPP39_GPIO,	/* Power: SATA0 */
+	MPP40_GPIO,	/* Power: SATA1 */
+	MPP41_GPIO,
+	MPP42_GPIO,
+	MPP43_GPIO,	/* LED: White USB */
+	MPP44_GPIO,	/* Fan: Tachometer Pin */
+	MPP45_GPIO,	/* Fan: high speed */
+	MPP46_GPIO,	/* Fan: low speed */
+	MPP47_GPIO,	/* Button: Back unmount */
+	MPP48_GPIO,	/* Button: Back reset */
+	MPP49_GPIO,	/* Pin of unused U5 (DNS-320 only) */
+	0
+};
+
+static struct gpio_led dns325_led_pins[] = {
+	{
+		.name	= "dns325:white:power",
+		.gpio	= 26,
+		.active_low = 1,
+		.default_trigger = "default-on",
+	},
+	{
+		.name	= "dns325:white:usb",
+		.gpio	= 43,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns325:red:l_hdd",
+		.gpio	= 28,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns325:red:r_hdd",
+		.gpio	= 27,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns325:red:usb",
+		.gpio	= 29,
+		.active_low = 1,
+	},
+};
+
+static struct gpio_led_platform_data dns325_led_data = {
+	.num_leds	= ARRAY_SIZE(dns325_led_pins),
+	.leds		= dns325_led_pins,
+};
+
+static struct platform_device dns325_led_device = {
+	.name		= "leds-gpio",
+	.id		= -1,
+	.dev		= {
+		.platform_data	= &dns325_led_data,
+	},
+};
+
+static struct gpio_led dns320_led_pins[] = {
+	{
+		.name	= "dns320:blue:power",
+		.gpio	= 26,
+		.active_low = 1,
+		.default_trigger = "default-on",
+	},
+	{
+		.name	= "dns320:blue:usb",
+		.gpio	= 43,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns320:orange:l_hdd",
+		.gpio	= 28,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns320:orange:r_hdd",
+		.gpio	= 27,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns320:orange:usb",
+		.gpio	= 35,
+		.active_low = 1,
+	},
+};
+
+static struct gpio_led_platform_data dns320_led_data = {
+	.num_leds	= ARRAY_SIZE(dns320_led_pins),
+	.leds		= dns320_led_pins,
+};
+
+static struct platform_device dns320_led_device = {
+	.name		= "leds-gpio",
+	.id		= -1,
+	.dev		= {
+		.platform_data	= &dns320_led_data,
+	},
+};
+
+static struct i2c_board_info dns325_i2c_board_info[] __initdata = {
+	{
+		I2C_BOARD_INFO("lm75", 0x48),
+	},
+	/* Something at 0x0c also */
+};
+
+static struct gpio_keys_button dnskw_button_pins[] = {
+	{
+		.code		= KEY_POWER,
+		.gpio		= 34,
+		.desc		= "Power button",
+		.active_low	= 1,
+	},
+	{
+		.code		= KEY_EJECTCD,
+		.gpio		= 47,
+		.desc		= "USB unmount button",
+		.active_low	= 1,
+	},
+	{
+		.code		= KEY_RESTART,
+		.gpio		= 48,
+		.desc		= "Reset button",
+		.active_low	= 1,
+	},
+};
+
+static struct gpio_keys_platform_data dnskw_button_data = {
+	.buttons	= dnskw_button_pins,
+	.nbuttons	= ARRAY_SIZE(dnskw_button_pins),
+};
+
+static struct platform_device dnskw_button_device = {
+	.name		= "gpio-keys",
+	.id		= -1,
+	.num_resources	= 0,
+	.dev		= {
+		.platform_data	= &dnskw_button_data,
+	}
+};
+
+/* Fan: ADDA AD045HB-G73 40mm 6000rpm at 5v */
+static struct gpio_fan_speed dnskw_fan_speed[] = {
+	{    0,  0 },
+	{ 3000,	 1 },
+	{ 6000,	 2 },
+};
+static unsigned dnskw_fan_pins[] = {46, 45};
+
+static struct gpio_fan_platform_data dnskw_fan_data = {
+	.num_ctrl	= ARRAY_SIZE(dnskw_fan_pins),
+	.ctrl		= dnskw_fan_pins,
+	.num_speed	= ARRAY_SIZE(dnskw_fan_speed),
+	.speed		= dnskw_fan_speed,
+};
+
+static struct platform_device dnskw_fan_device = {
+	.name	= "gpio-fan",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &dnskw_fan_data,
+	},
+};
+
+static void dnskw_power_off(void)
+{
+	gpio_set_value(36, 1);
+}
+
+/* Register any GPIO for output and set the value */
+static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
+{
+	if (gpio_request(gpio, name) == 0 &&
+	    gpio_direction_output(gpio, 0) == 0) {
+		gpio_set_value(gpio, def);
+		if (gpio_export(gpio, 0) != 0)
+			pr_err("dnskw: Failed to export GPIO %s\n", name);
+	} else
+		pr_err("dnskw: Failed to register %s\n", name);
+}
+
+void __init dnskw_init(void)
+{
+	kirkwood_mpp_conf(dnskw_mpp_config);
+	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
+
+	kirkwood_ehci_init();
+	kirkwood_ge00_init(&dnskw_ge00_data);
+	kirkwood_sata_init(&dnskw_sata_data);
+	kirkwood_i2c_init();
+
+	platform_device_register(&dnskw_button_device);
+	platform_device_register(&dnskw_fan_device);
+
+	if (of_machine_is_compatible("dlink,dns-325")) {
+		i2c_register_board_info(0, dns325_i2c_board_info,
+					ARRAY_SIZE(dns325_i2c_board_info));
+		platform_device_register(&dns325_led_device);
+
+	} else if (of_machine_is_compatible("dlink,dns-320"))
+		platform_device_register(&dns320_led_device);
+
+	/* Register power-off GPIO. */
+	if (gpio_request(36, "dnskw:power:off") == 0
+	    && gpio_direction_output(36, 0) == 0)
+		pm_power_off = dnskw_power_off;
+	else
+		pr_err("dnskw: failed to configure power-off GPIO\n");
+
+	/* Ensure power is supplied to both HDDs */
+	dnskw_gpio_register(39, "dnskw:power:sata0", 1);
+	dnskw_gpio_register(40, "dnskw:power:sata1", 1);
+
+	/* Set NAS to turn back on after a power failure */
+	dnskw_gpio_register(37, "dnskw:power:recover", 1);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 1c672d9..eadc4d7 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -55,11 +55,16 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("globalscale,dreamplug"))
 		dreamplug_init();
 
+	if (of_machine_is_compatible("dlink,dns-kirkwood"))
+		dnskw_init();
+
 	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
 }
 
 static const char *kirkwood_dt_board_compat[] = {
 	"globalscale,dreamplug",
+	"dlink,dns-320",
+	"dlink,dns-325",
 	NULL
 };
 
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index fa8e768..8c8c733 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -58,6 +58,12 @@ void dreamplug_init(void);
 static inline void dreamplug_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_DNSKW_DT
+void dnskw_init(void);
+#else
+static inline void dnskw_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-- 
1.7.9.1



From anton.vorontsov at linaro.org  Sat Mar 24 12:21:52 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 20:21:52 +0400
Subject: [PATCH 10/10] oom: Make find_lock_task_mm() sparse-aware
In-Reply-To: <1332593574.16159.31.camel@twins>
References: <20120324102609.GA28356@lizard> <20120324103127.GJ29067@lizard>
 <1332593574.16159.31.camel@twins>
Message-ID: <20120324162151.GA3640@lizard>

On Sat, Mar 24, 2012 at 01:52:54PM +0100, Peter Zijlstra wrote:
[...]
> > p.s. I know Peter Zijlstra detest the __cond_lock() stuff, but untill
> >      we have anything better in sparse, let's use it. This particular
> >      patch helped me to detect one bug that I myself made during
> >      task->mm fixup series. So, it is useful.
> 
> Yeah, so Nacked-by: Peter Zijlstra <a.p.zijlstra at chello.nl>
> 
> Also, why didn't lockdep catch it?

Because patch authors test their patches on architectures they own
(well, sometimes I do check patches on exotic architectures w/ qemu,
but it is less convenient than just build/sparse-test the patch w/
a cross compiler).

And since lockdep is a runtime checker, it is not very useful.

Sparse is a build-time checker, so it is even better in the sense
that it is able to catch bugs even in code that is executed rarely.

> Fix sparse already instead of smearing ugly all over.

Just wonder how do you see the feature implemented?

Something like this?

#define __ret_cond_locked(l, c)	__attribute__((ret_cond_locked(l, c)))
#define __ret_value		__attribute__((ret_value))
#define __ret_locked_nonnull(l)	__ret_cond_locked(l, __ret_value);

extern struct task_struct *find_lock_task_mm(struct task_struct *p)
	__ret_locked_nonnull(&__ret_value->alloc_lock);

Thanks,

-- 
Anton Vorontsov
Email: cbouatmailru at gmail.com


From thomas.abraham at linaro.org  Sat Mar 24 12:28:44 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 21:58:44 +0530
Subject: [PATCH v3 0/4] video: s3c-fb: Rearrange the elements in platform data
Message-ID: <1332606528-32338-1-git-send-email-thomas.abraham@linaro.org>

Changes since v2:
- Patch 3/4 is a new patch in this series. The real6410 and mini6410 boards
  use the display controllers window configuration data to represent video
  timing of two different lcd panels. Since the window configuration data
  should be not be used to specify timing of two different panels, this has
  been reworked in such a way that two instance of display controller's
  platform data is setup for the two supported lcd panels. Depending on the
  lcd panel specified using boot parameters, the corresponding platform data
  is registered. This maintains backward compatibility with existing
  functionality of supporting multiple lcd panels at runtime.

Changes since v1:
- Includes all changes suggested by Jingoo Han.
- Reworked s3c-fb platform data in all Samsung SoC based board files.

This patchset rearranges the elements in the platform data of the s3c-fb
driver with the intent of adding device tree support to the driver in
subsequent patches.

The first patch moves the video timing information from the individual window
setup data into the platform specific configuration section in the platform
data. The video timing is independent of the window setup. The resolution of
the window could be smaller than that of the lcd panel attached. So the video
timing data is removed from window configuration data.

The second patch removes the need for the 'default_win' element in the
platform data. This element was used to decide whether the video data
output from the controller should be enabled or disabled when the window
specified by 'default_win' is enabled or disabled. With the first patch
removing the need for atleast one window to be of the same resolution as
that of the lcd panel, it is now possible to decide when to enable/disable
the video data output based on the state of each window. If any of the
window is active, the lcd data output is enabled. Otherwise, the lcd data
output is disabled. Hence, the 'default_win' parameter from the platform
data can be removed, which anyways cannot be specified when using
device tree.

The third patch reworks the display controller's platform data that was
used to supply video timing information for two different panels on the
mini6410 and real6410 boards. That was not the correct usage of the window
data and hence reworks the runtime handling of two different lcd panels.

For all the Samsung SoC based boards, the forth patch reworks the platform
data of the display controller based on the changes introduced in the first
two patches.

This patch series is based on
http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]

with all patches merged from
https://github.com/schandinat/linux-2.6.git [fbdev-next]

and tested one Exynos4210 based Origen board (only compile tested for
other boards)

Thomas Abraham (4):
  video: s3c-fb: move video interface timing out of window setup data
  video: s3c-fb: remove 'default_win' element from platform data
  ARM: s3c64xx: Decouple lcd type from display controller window data
  ARM: Samsung: Rework platform data of s3c-fb driver

 arch/arm/mach-exynos/mach-nuri.c           |   26 +++---
 arch/arm/mach-exynos/mach-origen.c         |   24 +++--
 arch/arm/mach-exynos/mach-smdkv310.c       |   28 ++++---
 arch/arm/mach-exynos/mach-universal_c210.c |   26 +++---
 arch/arm/mach-s3c24xx/mach-smdk2416.c      |   27 +++---
 arch/arm/mach-s3c64xx/mach-anw6410.c       |   25 +++---
 arch/arm/mach-s3c64xx/mach-crag6410.c      |   25 +++---
 arch/arm/mach-s3c64xx/mach-hmt.c           |   24 +++--
 arch/arm/mach-s3c64xx/mach-mini6410.c      |   92 +++++++++++--------
 arch/arm/mach-s3c64xx/mach-real6410.c      |   90 +++++++++++--------
 arch/arm/mach-s3c64xx/mach-smartq5.c       |   26 +++---
 arch/arm/mach-s3c64xx/mach-smartq7.c       |   26 +++---
 arch/arm/mach-s3c64xx/mach-smdk6410.c      |   25 +++---
 arch/arm/mach-s5p64x0/mach-smdk6440.c      |   24 +++--
 arch/arm/mach-s5p64x0/mach-smdk6450.c      |   24 +++--
 arch/arm/mach-s5pc100/mach-smdkc100.c      |   27 +++---
 arch/arm/mach-s5pv210/mach-aquila.c        |   36 ++++----
 arch/arm/mach-s5pv210/mach-goni.c          |   26 +++---
 arch/arm/mach-s5pv210/mach-smdkv210.c      |   24 +++--
 arch/arm/plat-samsung/include/plat/fb.h    |   11 ++-
 drivers/video/s3c-fb.c                     |  135 +++++++++++++--------------
 21 files changed, 426 insertions(+), 345 deletions(-)



From thomas.abraham at linaro.org  Sat Mar 24 12:28:45 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 21:58:45 +0530
Subject: [PATCH v3 1/4] video: s3c-fb: move video interface timing out of
 window setup data
In-Reply-To: <1332606528-32338-1-git-send-email-thomas.abraham@linaro.org>
References: <1332606528-32338-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332606528-32338-2-git-send-email-thomas.abraham@linaro.org>

The video interface timing is independent of the window setup data.
The resolution of the window can be smaller than that of the lcd
panel to which the video data is output.

So move the video timing data from the per-window setup data to the
platform specific section in the platform data. This also removes
the restriction that atleast one window should have the same
resolution as that of the panel attached.

Cc: Ben Dooks <ben-linux at fluff.org>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
Acked-by: Jingoo Han <jg1.han at samsung.com>
---
 arch/arm/plat-samsung/include/plat/fb.h |    9 ++-
 drivers/video/s3c-fb.c                  |  112 +++++++++++++++++--------------
 2 files changed, 67 insertions(+), 54 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 0fedf47..39d6bd7 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -24,15 +24,16 @@
 
 /**
  * struct s3c_fb_pd_win - per window setup data
- * @win_mode: The display parameters to initialise (not for window 0)
+ * @xres     : The window X size.
+ * @yres     : The window Y size.
  * @virtual_x: The virtual X size.
  * @virtual_y: The virtual Y size.
  */
 struct s3c_fb_pd_win {
-	struct fb_videomode	win_mode;
-
 	unsigned short		default_bpp;
 	unsigned short		max_bpp;
+	unsigned short		xres;
+	unsigned short		yres;
 	unsigned short		virtual_x;
 	unsigned short		virtual_y;
 };
@@ -45,6 +46,7 @@ struct s3c_fb_pd_win {
  * @default_win: default window layer number to be used for UI layer.
  * @vidcon0: The base vidcon0 values to control the panel data format.
  * @vidcon1: The base vidcon1 values to control the panel data output.
+ * @vtiming: Video timing when connected to a RGB type panel.
  * @win: The setup data for each hardware window, or NULL for unused.
  * @display_mode: The LCD output display mode.
  *
@@ -58,6 +60,7 @@ struct s3c_fb_platdata {
 	void	(*setup_gpio)(void);
 
 	struct s3c_fb_pd_win	*win[S3C_FB_MAX_WIN];
+	struct fb_videomode     *vtiming;
 
 	u32			 default_win;
 
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index f310516..c94f40d 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -495,7 +495,6 @@ static int s3c_fb_set_par(struct fb_info *info)
 	u32 alpha = 0;
 	u32 data;
 	u32 pagewidth;
-	int clkdiv;
 
 	dev_dbg(sfb->dev, "setting framebuffer parameters\n");
 
@@ -532,48 +531,9 @@ static int s3c_fb_set_par(struct fb_info *info)
 	/* disable the window whilst we update it */
 	writel(0, regs + WINCON(win_no));
 
-	/* use platform specified window as the basis for the lcd timings */
-
-	if (win_no == sfb->pdata->default_win) {
-		clkdiv = s3c_fb_calc_pixclk(sfb, var->pixclock);
-
-		data = sfb->pdata->vidcon0;
-		data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
-
-		if (clkdiv > 1)
-			data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
-		else
-			data &= ~VIDCON0_CLKDIR;	/* 1:1 clock */
-
-		/* write the timing data to the panel */
-
-		if (sfb->variant.is_2443)
-			data |= (1 << 5);
-
-		writel(data, regs + VIDCON0);
-
+	if (win_no == sfb->pdata->default_win)
 		s3c_fb_enable(sfb, 1);
 
-		data = VIDTCON0_VBPD(var->upper_margin - 1) |
-		       VIDTCON0_VFPD(var->lower_margin - 1) |
-		       VIDTCON0_VSPW(var->vsync_len - 1);
-
-		writel(data, regs + sfb->variant.vidtcon);
-
-		data = VIDTCON1_HBPD(var->left_margin - 1) |
-		       VIDTCON1_HFPD(var->right_margin - 1) |
-		       VIDTCON1_HSPW(var->hsync_len - 1);
-
-		/* VIDTCON1 */
-		writel(data, regs + sfb->variant.vidtcon + 4);
-
-		data = VIDTCON2_LINEVAL(var->yres - 1) |
-		       VIDTCON2_HOZVAL(var->xres - 1) |
-		       VIDTCON2_LINEVAL_E(var->yres - 1) |
-		       VIDTCON2_HOZVAL_E(var->xres - 1);
-		writel(data, regs + sfb->variant.vidtcon + 8);
-	}
-
 	/* write the buffer address */
 
 	/* start and end registers stride is 8 */
@@ -1144,11 +1104,11 @@ static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
 
 	dev_dbg(sfb->dev, "allocating memory for display\n");
 
-	real_size = windata->win_mode.xres * windata->win_mode.yres;
+	real_size = windata->xres * windata->yres;
 	virt_size = windata->virtual_x * windata->virtual_y;
 
 	dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
-		real_size, windata->win_mode.xres, windata->win_mode.yres,
+		real_size, windata->xres, windata->yres,
 		virt_size, windata->virtual_x, windata->virtual_y);
 
 	size = (real_size > virt_size) ? real_size : virt_size;
@@ -1230,7 +1190,7 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 				      struct s3c_fb_win **res)
 {
 	struct fb_var_screeninfo *var;
-	struct fb_videomode *initmode;
+	struct fb_videomode initmode;
 	struct s3c_fb_pd_win *windata;
 	struct s3c_fb_win *win;
 	struct fb_info *fbinfo;
@@ -1251,11 +1211,11 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 	}
 
 	windata = sfb->pdata->win[win_no];
-	initmode = &windata->win_mode;
+	initmode = *sfb->pdata->vtiming;
 
 	WARN_ON(windata->max_bpp == 0);
-	WARN_ON(windata->win_mode.xres == 0);
-	WARN_ON(windata->win_mode.yres == 0);
+	WARN_ON(windata->xres == 0);
+	WARN_ON(windata->yres == 0);
 
 	win = fbinfo->par;
 	*res = win;
@@ -1294,7 +1254,9 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 	}
 
 	/* setup the initial video mode from the window */
-	fb_videomode_to_var(&fbinfo->var, initmode);
+	initmode.xres = windata->xres;
+	initmode.yres = windata->yres;
+	fb_videomode_to_var(&fbinfo->var, &initmode);
 
 	fbinfo->fix.type	= FB_TYPE_PACKED_PIXELS;
 	fbinfo->fix.accel	= FB_ACCEL_NONE;
@@ -1339,6 +1301,53 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 }
 
 /**
+ * s3c_fb_set_rgb_timing() - set video timing for rgb interface.
+ * @sfb: The base resources for the hardware.
+ *
+ * Set horizontal and vertical lcd rgb interface timing.
+ */
+static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb)
+{
+	struct fb_videomode *vmode = sfb->pdata->vtiming;
+	void __iomem *regs = sfb->regs;
+	int clkdiv;
+	u32 data;
+
+	if (!vmode->pixclock)
+		s3c_fb_missing_pixclock(vmode);
+
+	clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock);
+
+	data = sfb->pdata->vidcon0;
+	data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
+
+	if (clkdiv > 1)
+		data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
+	else
+		data &= ~VIDCON0_CLKDIR;	/* 1:1 clock */
+
+	if (sfb->variant.is_2443)
+		data |= (1 << 5);
+	writel(data, regs + VIDCON0);
+
+	data = VIDTCON0_VBPD(vmode->upper_margin - 1) |
+	       VIDTCON0_VFPD(vmode->lower_margin - 1) |
+	       VIDTCON0_VSPW(vmode->vsync_len - 1);
+	writel(data, regs + sfb->variant.vidtcon);
+
+	data = VIDTCON1_HBPD(vmode->left_margin - 1) |
+	       VIDTCON1_HFPD(vmode->right_margin - 1) |
+	       VIDTCON1_HSPW(vmode->hsync_len - 1);
+	writel(data, regs + sfb->variant.vidtcon + 4);
+
+	data = VIDTCON2_LINEVAL(vmode->yres - 1) |
+	       VIDTCON2_HOZVAL(vmode->xres - 1) |
+	       VIDTCON2_LINEVAL_E(vmode->yres - 1) |
+	       VIDTCON2_HOZVAL_E(vmode->xres - 1);
+	writel(data, regs + sfb->variant.vidtcon + 8);
+}
+
+/**
  * s3c_fb_clear_win() - clear hardware window registers.
  * @sfb: The base resources for the hardware.
  * @win: The window to process.
@@ -1481,15 +1490,14 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
 		writel(0xffffff, regs + WKEYCON1);
 	}
 
+	s3c_fb_set_rgb_timing(sfb);
+
 	/* we have the register setup, start allocating framebuffers */
 
 	for (win = 0; win < fbdrv->variant.nr_windows; win++) {
 		if (!pd->win[win])
 			continue;
 
-		if (!pd->win[win]->win_mode.pixclock)
-			s3c_fb_missing_pixclock(&pd->win[win]->win_mode);
-
 		ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
 				       &sfb->windows[win]);
 		if (ret < 0) {
@@ -1623,6 +1631,8 @@ static int s3c_fb_resume(struct device *dev)
 		shadow_protect_win(win, 0);
 	}
 
+	s3c_fb_set_rgb_timing(sfb);
+
 	/* restore framebuffers */
 	for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
 		win = sfb->windows[win_no];
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sat Mar 24 12:28:46 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 21:58:46 +0530
Subject: [PATCH v3 2/4] video: s3c-fb: remove 'default_win' element from
 platform data
In-Reply-To: <1332606528-32338-1-git-send-email-thomas.abraham@linaro.org>
References: <1332606528-32338-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332606528-32338-3-git-send-email-thomas.abraham@linaro.org>

The decision to enable or disable the data output to the lcd panel from
the controller need not be based on the value of 'default_win' element
in the platform data. Instead, the data output to the panel is enabled
if any of the windows are active, else data output is disabled.

Cc: Ben Dooks <ben-linux at fluff.org>
Signed-off-by: Jingoo Han <jg1.han at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/plat-samsung/include/plat/fb.h |    2 --
 drivers/video/s3c-fb.c                  |   25 +++++--------------------
 2 files changed, 5 insertions(+), 22 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 39d6bd7..536002f 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -62,8 +62,6 @@ struct s3c_fb_platdata {
 	struct s3c_fb_pd_win	*win[S3C_FB_MAX_WIN];
 	struct fb_videomode     *vtiming;
 
-	u32			 default_win;
-
 	u32			 vidcon0;
 	u32			 vidcon1;
 };
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index c94f40d..18c84b8 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -531,7 +531,7 @@ static int s3c_fb_set_par(struct fb_info *info)
 	/* disable the window whilst we update it */
 	writel(0, regs + WINCON(win_no));
 
-	if (win_no == sfb->pdata->default_win)
+	if (!sfb->output_on)
 		s3c_fb_enable(sfb, 1);
 
 	/* write the buffer address */
@@ -799,6 +799,7 @@ static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 	struct s3c_fb *sfb = win->parent;
 	unsigned int index = win->index;
 	u32 wincon;
+	u32 output_on = sfb->output_on;
 
 	dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
 
@@ -837,34 +838,18 @@ static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 
 	shadow_protect_win(win, 1);
 	writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
-	shadow_protect_win(win, 0);
 
 	/* Check the enabled state to see if we need to be running the
 	 * main LCD interface, as if there are no active windows then
 	 * it is highly likely that we also do not need to output
 	 * anything.
 	 */
-
-	/* We could do something like the following code, but the current
-	 * system of using framebuffer events means that we cannot make
-	 * the distinction between just window 0 being inactive and all
-	 * the windows being down.
-	 *
-	 * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
-	*/
-
-	/* we're stuck with this until we can do something about overriding
-	 * the power control using the blanking event for a single fb.
-	 */
-	if (index == sfb->pdata->default_win) {
-		shadow_protect_win(win, 1);
-		s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
-		shadow_protect_win(win, 0);
-	}
+	s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
+	shadow_protect_win(win, 0);
 
 	pm_runtime_put_sync(sfb->dev);
 
-	return 0;
+	return output_on == sfb->output_on;
 }
 
 /**
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sat Mar 24 12:28:47 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 21:58:47 +0530
Subject: [PATCH v3 3/4] ARM: s3c64xx: Decouple lcd type from display controller
 window data
In-Reply-To: <1332606528-32338-1-git-send-email-thomas.abraham@linaro.org>
References: <1332606528-32338-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332606528-32338-4-git-send-email-thomas.abraham@linaro.org>

The display controller window data should contain window configuration data
for only one type of lcd panel. So, for real6410 and mini6410 boards, split
the existing display controller window data, which contains window
configuration data for two different types of lcd panels, into two seperate
instances and register one of them depending on the type of the lcd panel
detected at runtime.

This is a prerequisite change for a subsequent commit that reorders the
platform data of display controller by moving video interface timing out
of window setup data.

Cc: Darius Augulis <augulis.darius at gmail.com>
Cc: Jingoo Han <jg1.han at samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-s3c64xx/mach-mini6410.c |   82 +++++++++++++++++---------------
 arch/arm/mach-s3c64xx/mach-real6410.c |   82 +++++++++++++++++---------------
 2 files changed, 88 insertions(+), 76 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index c34c2ab..34f5195 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -151,41 +151,49 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
 	.sets		= mini6410_nand_sets,
 };
 
-static struct s3c_fb_pd_win mini6410_fb_win[] = {
-	{
-		.win_mode	= {	/* 4.3" 480x272 */
-			.left_margin	= 3,
-			.right_margin	= 2,
-			.upper_margin	= 1,
-			.lower_margin	= 1,
-			.hsync_len	= 40,
-			.vsync_len	= 1,
-			.xres		= 480,
-			.yres		= 272,
-		},
-		.max_bpp	= 32,
-		.default_bpp	= 16,
-	}, {
-		.win_mode	= {	/* 7.0" 800x480 */
-			.left_margin	= 8,
-			.right_margin	= 13,
-			.upper_margin	= 7,
-			.lower_margin	= 5,
-			.hsync_len	= 3,
-			.vsync_len	= 1,
-			.xres		= 800,
-			.yres		= 480,
-		},
-		.max_bpp	= 32,
-		.default_bpp	= 16,
+static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
+	.win_mode	= {	/* 4.3" 480x272 */
+		.left_margin	= 3,
+		.right_margin	= 2,
+		.upper_margin	= 1,
+		.lower_margin	= 1,
+		.hsync_len	= 40,
+		.vsync_len	= 1,
+		.xres		= 480,
+		.yres		= 272,
 	},
+	.max_bpp	= 32,
+	.default_bpp	= 16,
 };
 
-static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
-	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
-	.win[0]		= &mini6410_fb_win[0],
-	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
+	.win_mode	= {	/* 7.0" 800x480 */
+		.left_margin	= 8,
+		.right_margin	= 13,
+		.upper_margin	= 7,
+		.lower_margin	= 5,
+		.hsync_len	= 3,
+		.vsync_len	= 1,
+		.xres		= 800,
+		.yres		= 480,
+	},
+	.max_bpp	= 32,
+	.default_bpp	= 16,
+};
+
+static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
+	{
+		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+		.win[0]		= &mini6410_lcd_type0_fb_win,
+		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+	}, {
+		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+		.win[0]		= &mini6410_lcd_type1_fb_win,
+		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+	},
+	{ },
 };
 
 static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
@@ -283,7 +291,7 @@ static void mini6410_parse_features(
 					"screen type already set\n", f);
 			} else {
 				int li = f - '0';
-				if (li >= ARRAY_SIZE(mini6410_fb_win))
+				if (li >= ARRAY_SIZE(mini6410_lcd_pdata))
 					printk(KERN_INFO "MINI6410: '%c' out "
 						"of range LCD mode\n", f);
 				else {
@@ -307,14 +315,12 @@ static void __init mini6410_machine_init(void)
 	/* Parse the feature string */
 	mini6410_parse_features(&features, mini6410_features_str);
 
-	mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
-
 	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
-		mini6410_lcd_pdata.win[0]->win_mode.xres,
-		mini6410_lcd_pdata.win[0]->win_mode.yres);
+		mini6410_lcd_pdata[features.lcd_index].win[0]->win_mode.xres,
+		mini6410_lcd_pdata[features.lcd_index].win[0]->win_mode.yres);
 
 	s3c_nand_set_platdata(&mini6410_nand_info);
-	s3c_fb_set_platdata(&mini6410_lcd_pdata);
+	s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
 	s3c24xx_ts_set_platdata(NULL);
 
 	/* configure nCS1 width to 16 bits */
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index be2a9a2..21f91e5 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -117,41 +117,49 @@ static struct platform_device real6410_device_eth = {
 	},
 };
 
-static struct s3c_fb_pd_win real6410_fb_win[] = {
-	{
-		.win_mode	= {	/* 4.3" 480x272 */
-			.left_margin	= 3,
-			.right_margin	= 2,
-			.upper_margin	= 1,
-			.lower_margin	= 1,
-			.hsync_len	= 40,
-			.vsync_len	= 1,
-			.xres		= 480,
-			.yres		= 272,
-		},
-		.max_bpp	= 32,
-		.default_bpp	= 16,
-	}, {
-		.win_mode	= {	/* 7.0" 800x480 */
-			.left_margin	= 8,
-			.right_margin	= 13,
-			.upper_margin	= 7,
-			.lower_margin	= 5,
-			.hsync_len	= 3,
-			.vsync_len	= 1,
-			.xres		= 800,
-			.yres		= 480,
-		},
-		.max_bpp	= 32,
-		.default_bpp	= 16,
+static struct s3c_fb_pd_win real6410_lcd_type0_fb_win = {
+	.win_mode	= {	/* 4.3" 480x272 */
+		.left_margin	= 3,
+		.right_margin	= 2,
+		.upper_margin	= 1,
+		.lower_margin	= 1,
+		.hsync_len	= 40,
+		.vsync_len	= 1,
+		.xres		= 480,
+		.yres		= 272,
 	},
+	.max_bpp	= 32,
+	.default_bpp	= 16,
 };
 
-static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
-	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
-	.win[0]		= &real6410_fb_win[0],
-	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+static struct s3c_fb_pd_win real6410_lcd_type1_fb_win = {
+	.win_mode	= {	/* 7.0" 800x480 */
+		.left_margin	= 8,
+		.right_margin	= 13,
+		.upper_margin	= 7,
+		.lower_margin	= 5,
+		.hsync_len	= 3,
+		.vsync_len	= 1,
+		.xres		= 800,
+		.yres		= 480,
+	},
+	.max_bpp	= 32,
+	.default_bpp	= 16,
+};
+
+static struct s3c_fb_platdata real6410_lcd_pdata[] __initdata = {
+	{
+		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+		.win[0]		= &real6410_lcd_type0_fb_win,
+		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+	}, {
+		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+		.win[0]		= &real6410_lcd_type1_fb_win,
+		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+	},
+	{ },
 };
 
 static struct mtd_partition real6410_nand_part[] = {
@@ -264,7 +272,7 @@ static void real6410_parse_features(
 					"screen type already set\n", f);
 			} else {
 				int li = f - '0';
-				if (li >= ARRAY_SIZE(real6410_fb_win))
+				if (li >= ARRAY_SIZE(real6410_lcd_pdata))
 					printk(KERN_INFO "REAL6410: '%c' out "
 						"of range LCD mode\n", f);
 				else {
@@ -288,13 +296,11 @@ static void __init real6410_machine_init(void)
 	/* Parse the feature string */
 	real6410_parse_features(&features, real6410_features_str);
 
-	real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
-
 	printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
-		real6410_lcd_pdata.win[0]->win_mode.xres,
-		real6410_lcd_pdata.win[0]->win_mode.yres);
+		real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.xres,
+		real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.yres);
 
-	s3c_fb_set_platdata(&real6410_lcd_pdata);
+	s3c_fb_set_platdata(&real6410_lcd_pdata[features.lcd_index]);
 	s3c_nand_set_platdata(&real6410_nand_info);
 	s3c24xx_ts_set_platdata(NULL);
 
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Sat Mar 24 12:28:48 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Sat, 24 Mar 2012 21:58:48 +0530
Subject: [PATCH v3 4/4] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <1332606528-32338-1-git-send-email-thomas.abraham@linaro.org>
References: <1332606528-32338-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332606528-32338-5-git-send-email-thomas.abraham@linaro.org>

For all the Samsung SoC based boards which have the platform data for
s3c-fb driver, the 'default_win' element in the platform data is removed
and the lcd panel video timing values are moved out of individual window
configuration data.

Cc: Jingoo Han <jg1.han at samsung.com>
Cc: Kyungmin Park <kyungmin.park at samsung.com>
Cc: JeongHyeon Kim <jhkim at insignal.co.kr>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Heiko Stuebner <heiko at sntech.de>
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Kwangwoo Lee <kwangwoo.lee at gmail.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Peter Korsgaard <jacmet at sunsite.dk>
Cc: Darius Augulis <augulis.darius at gmail.com>
Cc: Maurus Cuelenaere <mcuelenaere at gmail.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/mach-nuri.c           |   26 ++++++++------
 arch/arm/mach-exynos/mach-origen.c         |   24 +++++++-----
 arch/arm/mach-exynos/mach-smdkv310.c       |   28 ++++++++------
 arch/arm/mach-exynos/mach-universal_c210.c |   26 ++++++++------
 arch/arm/mach-s3c24xx/mach-smdk2416.c      |   27 ++++++++------
 arch/arm/mach-s3c64xx/mach-anw6410.c       |   25 +++++++------
 arch/arm/mach-s3c64xx/mach-crag6410.c      |   25 +++++++------
 arch/arm/mach-s3c64xx/mach-hmt.c           |   24 +++++++-----
 arch/arm/mach-s3c64xx/mach-mini6410.c      |   54 ++++++++++++++++-----------
 arch/arm/mach-s3c64xx/mach-real6410.c      |   52 +++++++++++++++-----------
 arch/arm/mach-s3c64xx/mach-smartq5.c       |   26 ++++++++------
 arch/arm/mach-s3c64xx/mach-smartq7.c       |   26 ++++++++------
 arch/arm/mach-s3c64xx/mach-smdk6410.c      |   25 +++++++------
 arch/arm/mach-s5p64x0/mach-smdk6440.c      |   24 +++++++-----
 arch/arm/mach-s5p64x0/mach-smdk6450.c      |   24 +++++++-----
 arch/arm/mach-s5pc100/mach-smdkc100.c      |   27 ++++++++------
 arch/arm/mach-s5pv210/mach-aquila.c        |   36 ++++++++----------
 arch/arm/mach-s5pv210/mach-goni.c          |   26 ++++++++------
 arch/arm/mach-s5pv210/mach-smdkv210.c      |   24 +++++++-----
 19 files changed, 311 insertions(+), 238 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 7ac81ce..a7e6731 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -212,25 +212,29 @@ static struct platform_device nuri_gpio_keys = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win nuri_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 64,
-		.right_margin	= 16,
-		.upper_margin	= 64,
-		.lower_margin	= 1,
-		.hsync_len	= 48,
-		.vsync_len	= 3,
-		.xres		= 1024,
-		.yres		= 600,
-		.refresh	= 60,
-	},
 	.max_bpp	= 24,
 	.default_bpp	= 16,
+	.xres		= 1024,
+	.yres		= 600,
 	.virtual_x	= 1024,
 	.virtual_y	= 2 * 600,
 };
 
+static struct fb_videomode nuri_lcd_timing = {
+	.left_margin	= 64,
+	.right_margin	= 16,
+	.upper_margin	= 64,
+	.lower_margin	= 1,
+	.hsync_len	= 48,
+	.vsync_len	= 3,
+	.xres		= 1024,
+	.yres		= 600,
+	.refresh	= 60,
+};
+
 static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
 	.win[0]		= &nuri_fb_win0,
+	.vtiming	= &nuri_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
 			  VIDCON0_CLKSEL_LCD,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 25c9b46..de71237 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -583,22 +583,26 @@ static struct platform_device origen_lcd_hv070wsa = {
 };
 
 static struct s3c_fb_pd_win origen_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 64,
-		.right_margin	= 16,
-		.upper_margin	= 64,
-		.lower_margin	= 16,
-		.hsync_len	= 48,
-		.vsync_len	= 3,
-		.xres		= 1024,
-		.yres		= 600,
-	},
+	.xres			= 1024,
+	.yres			= 600,
 	.max_bpp		= 32,
 	.default_bpp		= 24,
 };
 
+static struct fb_videomode origen_lcd_timing = {
+	.left_margin	= 64,
+	.right_margin	= 16,
+	.upper_margin	= 64,
+	.lower_margin	= 16,
+	.hsync_len	= 48,
+	.vsync_len	= 3,
+	.xres		= 1024,
+	.yres		= 600,
+};
+
 static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
 	.win[0]		= &origen_fb_win0,
+	.vtiming	= &origen_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
 				VIDCON1_INV_VCLK,
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index f08529f..6c00fa6 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -157,22 +157,26 @@ static struct platform_device smdkv310_lcd_lte480wv = {
 };
 
 static struct s3c_fb_pd_win smdkv310_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 13,
-		.right_margin	= 8,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
-	.max_bpp		= 32,
-	.default_bpp		= 24,
+	.max_bpp	= 32,
+	.default_bpp	= 24,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smdkv310_lcd_timing = {
+	.left_margin	= 13,
+	.right_margin	= 8,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
 	.win[0]		= &smdkv310_fb_win0,
+	.vtiming	= &smdkv310_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 57e4418..67a9547 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -813,25 +813,29 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win universal_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 16,
-		.right_margin	= 16,
-		.upper_margin	= 2,
-		.lower_margin	= 28,
-		.hsync_len	= 2,
-		.vsync_len	= 1,
-		.xres		= 480,
-		.yres		= 800,
-		.refresh	= 55,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 480,
+	.yres		= 800,
 	.virtual_x	= 480,
 	.virtual_y	= 2 * 800,
 };
 
+static struct fb_videomode universal_lcd_timing = {
+	.left_margin	= 16,
+	.right_margin	= 16,
+	.upper_margin	= 2,
+	.lower_margin	= 28,
+	.hsync_len	= 2,
+	.vsync_len	= 1,
+	.xres		= 480,
+	.yres		= 800,
+	.refresh	= 55,
+};
+
 static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
 	.win[0]		= &universal_fb_win0,
+	.vtiming	= &universal_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
 			  VIDCON0_CLKSEL_LCD,
 	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index 30a44f8..c3100a0 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -148,23 +148,25 @@ static struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
 
 static struct s3c_fb_pd_win smdk2416_fb_win[] = {
 	[0] = {
-		/* think this is the same as the smdk6410 */
-		.win_mode	= {
-			.pixclock	= 41094,
-			.left_margin	= 8,
-			.right_margin	= 13,
-			.upper_margin	= 7,
-			.lower_margin	= 5,
-			.hsync_len	= 3,
-			.vsync_len	= 1,
-			.xres           = 800,
-			.yres           = 480,
-		},
 		.default_bpp	= 16,
 		.max_bpp	= 32,
+		.xres           = 800,
+		.yres           = 480,
 	},
 };
 
+static struct fb_videomode smdk2416_lcd_timing = {
+	.pixclock	= 41094,
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres           = 800,
+	.yres           = 480,
+};
+
 static void s3c2416_fb_gpio_setup_24bpp(void)
 {
 	unsigned int gpio;
@@ -187,6 +189,7 @@ static void s3c2416_fb_gpio_setup_24bpp(void)
 
 static struct s3c_fb_platdata smdk2416_fb_platdata = {
 	.win[0]		= &smdk2416_fb_win[0],
+	.vtiming	= &smdk2416_lcd_timing,
 	.setup_gpio	= s3c2416_fb_gpio_setup_24bpp,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index b86f277..58fd0e3 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -134,24 +134,27 @@ static struct platform_device anw6410_lcd_powerdev = {
 };
 
 static struct s3c_fb_pd_win anw6410_fb_win0 = {
-	/* this is to ensure we use win0 */
-	.win_mode	= {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode anw6410_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
 static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &anw6410_lcd_timing,
 	.win[0]		= &anw6410_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index e20bf58..c1ef57e 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -151,26 +151,29 @@ static struct platform_device crag6410_lcd_powerdev = {
 
 /* 640x480 URT */
 static struct s3c_fb_pd_win crag6410_fb_win0 = {
-	/* this is to ensure we use win0 */
-	.win_mode	= {
-		.left_margin	= 150,
-		.right_margin	= 80,
-		.upper_margin	= 40,
-		.lower_margin	= 5,
-		.hsync_len	= 40,
-		.vsync_len	= 5,
-		.xres		= 640,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 640,
+	.yres		= 480,
 	.virtual_y	= 480 * 2,
 	.virtual_x	= 640,
 };
 
+static struct fb_videomode crag6410_lcd_timing = {
+	.left_margin	= 150,
+	.right_margin	= 80,
+	.upper_margin	= 40,
+	.lower_margin	= 5,
+	.hsync_len	= 40,
+	.vsync_len	= 5,
+	.xres		= 640,
+	.yres		= 480,
+};
+
 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
 static struct s3c_fb_platdata crag6410_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &crag6410_lcd_timing,
 	.win[0]		= &crag6410_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 521e07b..4e9b1ac 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -129,23 +129,27 @@ static struct platform_device hmt_backlight_device = {
 };
 
 static struct s3c_fb_pd_win hmt_fb_win0 = {
-	.win_mode	= {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode hmt_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
 static struct s3c_fb_platdata hmt_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &hmt_lcd_timing,
 	.win[0]		= &hmt_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 34f5195..2f425d5 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -152,43 +152,53 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
 };
 
 static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
-	.win_mode	= {	/* 4.3" 480x272 */
-		.left_margin	= 3,
-		.right_margin	= 2,
-		.upper_margin	= 1,
-		.lower_margin	= 1,
-		.hsync_len	= 40,
-		.vsync_len	= 1,
-		.xres		= 480,
-		.yres		= 272,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 480,
+	.yres		= 272,
+};
+
+static struct fb_videomode mini6410_lcd_type0_timing = {
+	/* 4.3" 480x272 */
+	.left_margin	= 3,
+	.right_margin	= 2,
+	.upper_margin	= 1,
+	.lower_margin	= 1,
+	.hsync_len	= 40,
+	.vsync_len	= 1,
+	.xres		= 480,
+	.yres		= 272,
 };
 
 static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
-	.win_mode	= {	/* 7.0" 800x480 */
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode mini6410_lcd_type1_timing = {
+	/* 7.0" 800x480 */
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
 	{
 		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+		.vtiming	= &mini6410_lcd_type0_timing,
 		.win[0]		= &mini6410_lcd_type0_fb_win,
 		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	}, {
 		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+		.vtiming	= &mini6410_lcd_type1_timing,
 		.win[0]		= &mini6410_lcd_type1_fb_win,
 		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
@@ -316,8 +326,8 @@ static void __init mini6410_machine_init(void)
 	mini6410_parse_features(&features, mini6410_features_str);
 
 	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
-		mini6410_lcd_pdata[features.lcd_index].win[0]->win_mode.xres,
-		mini6410_lcd_pdata[features.lcd_index].win[0]->win_mode.yres);
+		mini6410_lcd_pdata[features.lcd_index].win[0]->xres,
+		mini6410_lcd_pdata[features.lcd_index].win[0]->yres);
 
 	s3c_nand_set_platdata(&mini6410_nand_info);
 	s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 21f91e5..0fbd32c 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -118,43 +118,51 @@ static struct platform_device real6410_device_eth = {
 };
 
 static struct s3c_fb_pd_win real6410_lcd_type0_fb_win = {
-	.win_mode	= {	/* 4.3" 480x272 */
-		.left_margin	= 3,
-		.right_margin	= 2,
-		.upper_margin	= 1,
-		.lower_margin	= 1,
-		.hsync_len	= 40,
-		.vsync_len	= 1,
-		.xres		= 480,
-		.yres		= 272,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 480,
+	.yres		= 272,
+};
+
+static struct fb_videomode real6410_lcd_type0_timing = {
+	/* 4.3" 480x272 */
+	.left_margin	= 3,
+	.right_margin	= 2,
+	.upper_margin	= 1,
+	.lower_margin	= 1,
+	.hsync_len	= 40,
+	.vsync_len	= 1,
 };
 
 static struct s3c_fb_pd_win real6410_lcd_type1_fb_win = {
-	.win_mode	= {	/* 7.0" 800x480 */
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode real6410_lcd_type1_timing = {
+	/* 7.0" 800x480 */
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 static struct s3c_fb_platdata real6410_lcd_pdata[] __initdata = {
 	{
 		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+		.vtiming	= &real6410_lcd_type0_timing,
 		.win[0]		= &real6410_lcd_type0_fb_win,
 		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	}, {
 		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+		.vtiming	= &real6410_lcd_type1_timing,
 		.win[0]		= &real6410_lcd_type1_fb_win,
 		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
@@ -297,8 +305,8 @@ static void __init real6410_machine_init(void)
 	real6410_parse_features(&features, real6410_features_str);
 
 	printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
-		real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.xres,
-		real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.yres);
+		real6410_lcd_pdata[features.lcd_index].win[0]->xres,
+		real6410_lcd_pdata[features.lcd_index].win[0]->yres);
 
 	s3c_fb_set_platdata(&real6410_lcd_pdata[features.lcd_index]);
 	s3c_nand_set_platdata(&real6410_nand_info);
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index 3f42431..03a2f88 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -108,23 +108,27 @@ static struct platform_device smartq5_buttons_device  = {
 };
 
 static struct s3c_fb_pd_win smartq5_fb_win0 = {
-	.win_mode	= {
-		.left_margin	= 216,
-		.right_margin	= 40,
-		.upper_margin	= 35,
-		.lower_margin	= 10,
-		.hsync_len	= 1,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-		.refresh	= 80,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smartq5_lcd_timing = {
+	.left_margin	= 216,
+	.right_margin	= 40,
+	.upper_margin	= 35,
+	.lower_margin	= 10,
+	.hsync_len	= 1,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
+	.refresh	= 80,
 };
 
 static struct s3c_fb_platdata smartq5_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &smartq5_lcd_timing,
 	.win[0]		= &smartq5_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index e5c09b6..4e3b038 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -124,23 +124,27 @@ static struct platform_device smartq7_buttons_device  = {
 };
 
 static struct s3c_fb_pd_win smartq7_fb_win0 = {
-	.win_mode	= {
-		.left_margin	= 3,
-		.right_margin	= 5,
-		.upper_margin	= 1,
-		.lower_margin	= 20,
-		.hsync_len	= 10,
-		.vsync_len	= 3,
-		.xres		= 800,
-		.yres		= 480,
-		.refresh	= 80,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smartq7_lcd_timing = {
+	.left_margin	= 3,
+	.right_margin	= 5,
+	.upper_margin	= 1,
+	.lower_margin	= 20,
+	.hsync_len	= 10,
+	.vsync_len	= 3,
+	.xres		= 800,
+	.yres		= 480,
+	.refresh	= 80,
 };
 
 static struct s3c_fb_platdata smartq7_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &smartq7_lcd_timing,
 	.win[0]		= &smartq7_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index d55bc96..3cfc90f 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -146,26 +146,29 @@ static struct platform_device smdk6410_lcd_powerdev = {
 };
 
 static struct s3c_fb_pd_win smdk6410_fb_win0 = {
-	/* this is to ensure we use win0 */
-	.win_mode	= {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
 	.virtual_y	= 480 * 2,
 	.virtual_x	= 800,
 };
 
+static struct fb_videomode smdk6410_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
+};
+
 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
 static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
+	.vtiming	= &smdk6410_lcd_timing,
 	.win[0]		= &smdk6410_fb_win0,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index a40e325..92fefad 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -103,22 +103,26 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win smdk6440_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 24,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smdk6440_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = {
 	.win[0]		= &smdk6440_fb_win0,
+	.vtiming	= &smdk6440_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= s5p64x0_fb_gpio_setup_24bpp,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index efb69e2..e2335ec 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -121,22 +121,26 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win smdk6450_fb_win0 = {
-	.win_mode	= {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 24,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smdk6450_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = {
 	.win[0]		= &smdk6450_fb_win0,
+	.vtiming	= &smdk6450_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= s5p64x0_fb_gpio_setup_24bpp,
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 674d229..0c3ae38 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -136,24 +136,27 @@ static struct platform_device smdkc100_lcd_powerdev = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win smdkc100_fb_win0 = {
-	/* this is to ensure we use win0 */
-	.win_mode	= {
-		.left_margin	= 8,
-		.right_margin	= 13,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-		.refresh	= 80,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smdkc100_lcd_timing = {
+	.left_margin	= 8,
+	.right_margin	= 13,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
+	.refresh	= 80,
 };
 
 static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
 	.win[0]		= &smdkc100_fb_win0,
+	.vtiming	= &smdkc100_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= s5pc100_fb_gpio_setup_24bpp,
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index a9ea64e..7b91bbf 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -96,38 +96,34 @@ static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win aquila_fb_win0 = {
-	.win_mode = {
-		.left_margin = 16,
-		.right_margin = 16,
-		.upper_margin = 3,
-		.lower_margin = 28,
-		.hsync_len = 2,
-		.vsync_len = 2,
-		.xres = 480,
-		.yres = 800,
-	},
 	.max_bpp = 32,
 	.default_bpp = 16,
+	.xres = 480,
+	.yres = 800,
 };
 
 static struct s3c_fb_pd_win aquila_fb_win1 = {
-	.win_mode = {
-		.left_margin = 16,
-		.right_margin = 16,
-		.upper_margin = 3,
-		.lower_margin = 28,
-		.hsync_len = 2,
-		.vsync_len = 2,
-		.xres = 480,
-		.yres = 800,
-	},
 	.max_bpp = 32,
 	.default_bpp = 16,
+	.xres = 480,
+	.yres = 800,
+};
+
+static struct fb_videomode aquila_lcd_timing = {
+	.left_margin = 16,
+	.right_margin = 16,
+	.upper_margin = 3,
+	.lower_margin = 28,
+	.hsync_len = 2,
+	.vsync_len = 2,
+	.xres = 480,
+	.yres = 800,
 };
 
 static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
 	.win[0]		= &aquila_fb_win0,
 	.win[1]		= &aquila_fb_win1,
+	.vtiming	= &aquila_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
 			  VIDCON1_INV_VCLK | VIDCON1_INV_VDEN,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 2cf5ed7..07a840d 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -105,25 +105,29 @@ static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
 
 /* Frame Buffer */
 static struct s3c_fb_pd_win goni_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 16,
-		.right_margin	= 16,
-		.upper_margin	= 2,
-		.lower_margin	= 28,
-		.hsync_len	= 2,
-		.vsync_len	= 1,
-		.xres		= 480,
-		.yres		= 800,
-		.refresh	= 55,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 16,
+	.xres		= 480,
+	.yres		= 800,
 	.virtual_x	= 480,
 	.virtual_y	= 2 * 800,
 };
 
+static struct fb_videomode goni_lcd_timing = {
+	.left_margin	= 16,
+	.right_margin	= 16,
+	.upper_margin	= 2,
+	.lower_margin	= 28,
+	.hsync_len	= 2,
+	.vsync_len	= 1,
+	.xres		= 480,
+	.yres		= 800,
+	.refresh	= 55,
+};
+
 static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
 	.win[0]		= &goni_fb_win0,
+	.vtiming	= &goni_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
 			  VIDCON0_CLKSEL_LCD,
 	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 91d4ad8..5e0c955 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -189,22 +189,26 @@ static struct platform_device smdkv210_lcd_lte480wv = {
 };
 
 static struct s3c_fb_pd_win smdkv210_fb_win0 = {
-	.win_mode = {
-		.left_margin	= 13,
-		.right_margin	= 8,
-		.upper_margin	= 7,
-		.lower_margin	= 5,
-		.hsync_len	= 3,
-		.vsync_len	= 1,
-		.xres		= 800,
-		.yres		= 480,
-	},
 	.max_bpp	= 32,
 	.default_bpp	= 24,
+	.xres		= 800,
+	.yres		= 480,
+};
+
+static struct fb_videomode smdkv210_lcd_timing = {
+	.left_margin	= 13,
+	.right_margin	= 8,
+	.upper_margin	= 7,
+	.lower_margin	= 5,
+	.hsync_len	= 3,
+	.vsync_len	= 1,
+	.xres		= 800,
+	.yres		= 480,
 };
 
 static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
 	.win[0]		= &smdkv210_fb_win0,
+	.vtiming	= &smdkv210_lcd_timing,
 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 	.setup_gpio	= s5pv210_fb_gpio_setup_24bpp,
-- 
1.6.6.rc2



From a.p.zijlstra at chello.nl  Sat Mar 24 12:43:27 2012
From: a.p.zijlstra at chello.nl (Peter Zijlstra)
Date: Sat, 24 Mar 2012 17:43:27 +0100
Subject: [PATCH 10/10] oom: Make find_lock_task_mm() sparse-aware
In-Reply-To: <20120324162151.GA3640@lizard>
References: <20120324102609.GA28356@lizard> <20120324103127.GJ29067@lizard>
 <1332593574.16159.31.camel@twins> <20120324162151.GA3640@lizard>
Message-ID: <1332607407.16159.51.camel@twins>

On Sat, 2012-03-24 at 20:21 +0400, Anton Vorontsov wrote:

> Just wonder how do you see the feature implemented?
> 
> Something like this?
> 
> #define __ret_cond_locked(l, c)	__attribute__((ret_cond_locked(l, c)))
> #define __ret_value		__attribute__((ret_value))
> #define __ret_locked_nonnull(l)	__ret_cond_locked(l, __ret_value);
> 
> extern struct task_struct *find_lock_task_mm(struct task_struct *p)
> 	__ret_locked_nonnull(&__ret_value->alloc_lock);

Yeah, see the email I just CC'ed you on to linux-sparse.

Basically extend __attribute__((context())) to allow things similar to
what you proposed.


From anton.vorontsov at linaro.org  Sat Mar 24 12:43:16 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 20:43:16 +0400
Subject: [PATCH v2.1 01/10] cpu: Introduce clear_tasks_mm_cpumask() helper
In-Reply-To: <1332593021.16159.27.camel@twins>
References: <20120324102609.GA28356@lizard> <20120324102751.GA29067@lizard>
 <1332593021.16159.27.camel@twins>
Message-ID: <20120324164316.GB3640@lizard>

Many architctures clear tasks' mm_cpumask like this:

	read_lock(&tasklist_lock);
	for_each_process(p) {
		if (p->mm)
			cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
	}
	read_unlock(&tasklist_lock);

The code above has several problems, such as:

1. Working with task->mm w/o getting mm or grabing the task lock is
   dangerous as ->mm might disappear (exit_mm() assigns NULL under
   task_lock(), so tasklist lock is not enough).

2. Checking for process->mm is not enough because process' main
   thread may exit or detach its mm via use_mm(), but other threads
   may still have a valid mm.

This patch implements a small helper function that does things
correctly, i.e.:

1. We take the task's lock while whe handle its mm (we can't use
   get_task_mm()/mmput() pair as mmput() might sleep);

2. To catch exited main thread case, we use find_lock_task_mm(),
   which walks up all threads and returns an appropriate task
   (with task lock held).

Also, Per Peter Zijlstra's idea, now we don't grab tasklist_lock in
the new helper, instead we take the rcu read lock. We can do this
because the function is called after the cpu is taken down and marked
offline, so no new tasks will get this cpu set in their mm mask.

Signed-off-by: Anton Vorontsov <anton.vorontsov at linaro.org>
---

On Sat, Mar 24, 2012 at 01:43:41PM +0100, Peter Zijlstra wrote:
> On Sat, 2012-03-24 at 14:27 +0400, Anton Vorontsov wrote:
> > +       read_unlock(&tasklist_lock);
> > +} 
> 
> Why bother with the tasklist_lock at all anymore, afaict you could use
> rcu_read_lock() here. This all is called after the cpu is taken down and
> marked offline, so its not like new tasks will ever get this cpu set in
> their mm mask.

I guess you're right. Well, this would make the code a bit fragile,
but a comment might help.

How about this version?

 include/linux/cpu.h |    1 +
 kernel/cpu.c        |   26 ++++++++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 1f65875..941e865 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -171,6 +171,7 @@ extern void put_online_cpus(void);
 #define hotcpu_notifier(fn, pri)	cpu_notifier(fn, pri)
 #define register_hotcpu_notifier(nb)	register_cpu_notifier(nb)
 #define unregister_hotcpu_notifier(nb)	unregister_cpu_notifier(nb)
+void clear_tasks_mm_cpumask(int cpu);
 int cpu_down(unsigned int cpu);
 
 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 2060c6e..ecdf499 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -10,6 +10,8 @@
 #include <linux/sched.h>
 #include <linux/unistd.h>
 #include <linux/cpu.h>
+#include <linux/oom.h>
+#include <linux/rcupdate.h>
 #include <linux/export.h>
 #include <linux/kthread.h>
 #include <linux/stop_machine.h>
@@ -171,6 +173,30 @@ void __ref unregister_cpu_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL(unregister_cpu_notifier);
 
+void clear_tasks_mm_cpumask(int cpu)
+{
+	struct task_struct *p;
+
+	/*
+	 * This function is called after the cpu is taken down and marked
+	 * offline, so its not like new tasks will ever get this cpu set in
+	 * their mm mask. -- Peter Zijlstra
+	 * Thus, we may use rcu_read_lock() here, instead of grabbing
+	 * full-fledged tasklist_lock.
+	 */
+	rcu_read_lock();
+	for_each_process(p) {
+		struct task_struct *t;
+
+		t = find_lock_task_mm(p);
+		if (!t)
+			continue;
+		cpumask_clear_cpu(cpu, mm_cpumask(t->mm));
+		task_unlock(t);
+	}
+	rcu_read_unlock();
+}
+
 static inline void check_for_tasks(int cpu)
 {
 	struct task_struct *p;
-- 
1.7.9.2



From anton.vorontsov at linaro.org  Sat Mar 24 12:43:35 2012
From: anton.vorontsov at linaro.org (Anton Vorontsov)
Date: Sat, 24 Mar 2012 20:43:35 +0400
Subject: [PATCH 07/10] um: Should hold tasklist_lock while traversing
 processes
In-Reply-To: <1332593303.16159.28.camel@twins>
References: <20120324102609.GA28356@lizard> <20120324103030.GG29067@lizard>
 <1332593303.16159.28.camel@twins>
Message-ID: <20120324164335.GA4955@lizard>

On Sat, Mar 24, 2012 at 01:48:23PM +0100, Peter Zijlstra wrote:
> On Sat, 2012-03-24 at 14:30 +0400, Anton Vorontsov wrote:
> > Traversing the tasks requires holding tasklist_lock, otherwise it
> > is unsafe. 
> 
> No it doesn't, it either requires tasklist_lock or rcu_read_lock().

Well, currently the code does neither. :-)

-- 
Anton Vorontsov
Email: cbouatmailru at gmail.com


From arnd at arndb.de  Sat Mar 24 15:01:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 24 Mar 2012 19:01:00 +0000
Subject: [PATCH V2 2/3] ARM: kirkwood: Convert orion-nand to fdt
In-Reply-To: <1332594876-8673-3-git-send-email-jm@lentin.co.uk>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <1332594876-8673-3-git-send-email-jm@lentin.co.uk>
Message-ID: <201203241901.00405.arnd@arndb.de>

On Saturday 24 March 2012, Jamie Lentin wrote:
> Convert orion-nand to use fdt and add common setup to kirkwood.dtsi, including
> a default value for chip-delay (all current boards seem to use 25 anyway).
> 
> Add placeholder documentation for the bindings, for someone more knowledgable
> than me to fill in the details of the properties.

Looks very good. Two small comments:

> diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
> new file mode 100644
> index 0000000..d347999
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/orion-nand.txt
> @@ -0,0 +1,46 @@
> +NAND support for Marvell Orion SoC platforms
> +
> +Required properties:
> +- compatible : "mrvl,orion-nand".
> +- reg : Base physical address of the NAND and length of memory mapped
> +	region
> +
> +Optional properties:
> +- cle :
> +- ale :
> +- width :
> +- chip-delay :

I think the "width" property should be called "bank-width" to match the other
bindings.

> +Examples:
> +
> +nand at f4000000 {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	cle = <0>;
> +	ale = <1>;
> +	width = <8>;
> +	chip-delay = <25>;
> +	compatible = "mrvl,orion-nand";
> +	reg = <0xf4000000 0x400>;
> +
> +	partition at 0 {
> +		label = "u-boot";
> +		reg = <0x0000000 0x100000>;
> +		read-only;
> +	};

You don't describe the partitions in the binding. Others have the same omission,
but I think it's worth mentioning. Either point to the mtd-physmap.txt file,
or make your patch move the partition support into a new file that everything
else can refer to.

	Arnd


From arnd at arndb.de  Sat Mar 24 15:01:41 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 24 Mar 2012 19:01:41 +0000
Subject: [PATCH V2 3/3] ARM: kirkwood: Define NAND partitions in dts
In-Reply-To: <1332594876-8673-4-git-send-email-jm@lentin.co.uk>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <1332594876-8673-4-git-send-email-jm@lentin.co.uk>
Message-ID: <201203241901.41397.arnd@arndb.de>

On Saturday 24 March 2012, Jamie Lentin wrote:
> Use devicetree to define NAND partitions. Use D-link partition scheme by
> default, to be vaguely compatible with their userland.
> 
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>

Acked-by: Arnd Bergmann <arnd at arndb.de>


From arnd at arndb.de  Sat Mar 24 15:26:00 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 24 Mar 2012 19:26:00 +0000
Subject: [PATCH V2 1/3] ARM: kirkwood: Basic support for DNS-320 and
 DNS-325
In-Reply-To: <1332594876-8673-2-git-send-email-jm@lentin.co.uk>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <1332594876-8673-2-git-send-email-jm@lentin.co.uk>
Message-ID: <201203241926.00597.arnd@arndb.de>

On Saturday 24 March 2012, Jamie Lentin wrote:
> 
> Add support for the DNS-320 and DNS-325. Describe as much as currently possible
> in the devicetree files, create a board-dnskw.c for everything else.
> 
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>

Looks good to me. 

Jason, do you want to add these to your tree? You are already have some
the patches for dreamplug, and I think it makes sense to update these two
together when you have more patches.

Since the dnskw board file contains mostly gpio setup, I think it would
be good if one of you could take that part on next: once the gpio controller
uses DT probing, you can move all the gpio leds and buttons into the
device tree, which drastically shrinks the dnskw file.

Acked-by: Arnd Bergmann <arnd at arndb.de>

	Arnd


From arnd at arndb.de  Sat Mar 24 18:02:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sat, 24 Mar 2012 22:02:37 +0000
Subject: =?UTF-8?q?=5BGIT=20PULL=200/9=5D=20arm-soc=20updates=2C=20first=20batch?=
Message-ID: <1332626568-17812-1-git-send-email-arnd@arndb.de>

Hi Linus,

These are the first nine pull requests for arm-soc in the v3.4 merge
window. We have queued up a total of 683 non-merge changesets this
time, and today you get 576 of those. This is more than for v3.3,
where we had lots of ugly merge conflicts and ended up not sending
everything. Despite the larger number of changes, I have a better
feeling this time, mostly because of the new way we handle conflicts
between the Russell's ARM tree and the arm-soc tree and resolve
them much earlier in the cycle.

There are a few conflicts left for you to clean up, but I resolved
most of the ones between the branches I'm sending and some particularly
annoying ones with stuff you already pulled from other branches.
I've provided an extra branch "test-merge" in the same git tree
for you with all of these merged. If you compare that with your
resolutions, you can point out afterwards what I merged wrong. ;-)

The remaining pull requests are either for stuff that is based on
branches you have not pulled yet, or that has not spent enough time
in linux-next because it was sent in the last week before the merge
window, and I plan to send them early next week. Since you've said
that you're away till Tuesday, you might get them at the same time
though.

	Arnd

=== Tags included in this series ===

1. fixes-non-critical ARM: Non-critical bug fixes
2. maintainers     ARM: subarch maintainer updates
3. cleanup         ARM: global cleanups
4. timer           ARM: timer cleanup work
5. soc             ARM: SoC specific updates
6. boards          ARM: board specific updates
7. rpmsg           remoteproc/rpmsg: new subsystem
8. drivers         ARM: driver specific updates
9. dt              ARM: device tree work

=== Dirstat ===

   1.2% Documentation/devicetree/bindings/arm/
   3.4% Documentation/
   5.0% arch/arm/boot/dts/
   5.7% arch/arm/mach-at91/include/mach/
  11.8% arch/arm/mach-at91/
   1.5% arch/arm/mach-davinci/
   1.7% arch/arm/mach-ep93xx/
   1.9% arch/arm/mach-exynos/include/mach/
   9.9% arch/arm/mach-exynos/
   2.9% arch/arm/mach-imx/
   1.6% arch/arm/mach-mxs/
   1.2% arch/arm/mach-omap1/
   4.6% arch/arm/mach-omap2/
   1.8% arch/arm/mach-s3c24xx/
   1.5% arch/arm/mach-shmobile/
  12.4% arch/arm/mach-tegra/
   1.7% arch/arm/mach-vexpress/
  10.7% arch/arm/
   1.0% arch/
   6.3% drivers/remoteproc/
   2.8% drivers/rpmsg/
   4.9% drivers/
   2.8% include/linux/

=== Shortlog ===

Aaro Koskinen (1):
      ARM: OMAP: add minimal support for Nokia RM-696

Afzal Mohammed (1):
      ARM: OMAP2+: id: Add am33xx SoC type detection

Alex (1):
      ARM: OMAP: Add omap_reserve functionality

Alex Gershgorin (1):
      i.MX35-PDK: Add Camera support

Amit Daniel Kachhap (5):
      ARM: EXYNOS: Add support AFTR mode on EXYNOS4210
      ARM: S5P: add L2 early resume code
      ARM: EXYNOS: save L2 settings during bootup
      ARM: EXYNOS: remove useless code to save/restore L2
      ARM: EXYNOS: Enable l2 configuration through device tree

Andrzej Pietrasiewicz (3):
      ARM: EXYNOS: add support JPEG
      ARM: EXYNOS: Register JPEG on universal_c210
      ARM: EXYNOS: Register JPEG on nuri

Arnd Bergmann (108):
      Merge branch 'v3.4-next/devel-samsung-rtc' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'depends/driver-core' into next/soc2
      Merge branch 'ux500/soc' into next/soc2
      Merge branch 'lpc32xx/drivers' into next/drivers
      Merge tag 'rpmsg-for-3.4' of git://git.kernel.org/.../ohad/remoteproc into next/rpmsg
      Merge branch 'vexpress-dt-v3.3-rc4' of git://git.linaro.org/people/pawelmoll/linux into next/dt
      Merge branch 'features/cs89x0' of git://git.pengutronix.de/git/imx/linux-2.6 into next/drivers
      Merge branch 'imx-fixes' of git://git.pengutronix.de/git/imx/linux-2.6 into next/fixes-non-critical
      Merge branch 'imx-cleanup' of git://git.pengutronix.de/git/imx/linux-2.6 into next/cleanup
      Merge branch 'imx-drivers' of git://git.pengutronix.de/git/imx/linux-2.6 into next/drivers
      Merge branch 'v3.4/fixes' of git://gitorious.org/linux-davinci/linux-davinci into next/fixes-non-critical
      ARM: davinci: add back dummy header files
      Merge branch 'davinci/cleanups' into next/cleanup
      Merge branch 'kirkwood/board' into next/boards
      Merge branch 'lpc32xx/fixes-non-critical' of git://git.antcom.de/linux-2.6 into next/fixes-non-critical
      Merge branch 'mxs/gpmi' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/drivers
      Merge branch 'imx/driver' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/drivers
      Merge branch 'imx/dt' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
      Merge branch 'imx/defconfig' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
      Merge branch 'rtc-sa1100' of git://github.com/hzhuang1/linux into next/drivers
      Merge branch 'cleanup-3.4' of git://github.com/hzhuang1/linux into next/cleanup
      Merge branch 'board-specific' of git://github.com/hzhuang1/linux into next/boards
      Merge branch 'at91-3.4-base2+cleanup' of git://github.com/at91linux/linux-at91 into at91/staging/base2+cleanup
      ARM: ux500: U8500 depends on MMU
      ARM: ux500: add board autoselection
      ARM: ux500: select L2X0 cache on ux500
      ARM: ux500: select CPU_FREQ_TABLE where needed
      Merge branch 'fixes-non-critical' of git://git.kernel.org/.../tmlind/linux-omap into next/fixes-non-critical
      Merge branch 'soc' of git://git.kernel.org/.../tmlind/linux-omap into next/soc
      Merge branch 'omap1' of git://git.kernel.org/.../tmlind/linux-omap into next/boards
      Merge branch 'dt' of git://git.kernel.org/.../tmlind/linux-omap into next/dt
      Merge branch 'cleanup' of git://git.kernel.org/.../tmlind/linux-omap into omap/cleanup
      Merge branch 'cleanup' of git://git.kernel.org/.../tmlind/linux-omap into next/cleanup
      Merge branch 'depends/omap/gpio/runtime-pm-cleanup' into next/cleanup
      Merge branches 'depends/irqdomain' and 'at91/base2+cleanup' into next/dt
      Merge branch 'at91-3.4-cleanup2+DT' of git://github.com/at91linux/linux-at91 into next/dt
      Merge branch 'features/imx27-visstrim' of git://git.pengutronix.de/git/imx/linux-2.6 into next/boards
      Merge branch 'features/imx27-dt' of git://git.pengutronix.de/git/imx/linux-2.6 into next/dt
      Merge branch 'features/imx31-moboard' of git://git.pengutronix.de/git/imx/linux-2.6 into next/boards
      Merge branch 'features/imx3' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
      ARM: tegra: select CPU_FREQ_TABLE
      ARM: tegra: build localtimer support only when needed
      ARM: tegra: export usb phy symbols
      Merge tag 'tegra-cleanups' of git://git.kernel.org/.../olof/tegra into tegra/cleanups
      Merge tag 'tegra-cleanups' of git://git.kernel.org/.../olof/tegra into tegra/cleanups
      Merge tag 'tegra-dt' of git://git.kernel.org/.../olof/tegra into tegra/dt
      Merge tag 'tegra-soc' of git://git.kernel.org/.../olof/tegra into tegra/soc
      Merge tag 'tegra-soc-drivers' of git://git.kernel.org/.../olof/tegra into tegra/soc-drivers
      Merge tag 'tegra-soc2' of git://git.kernel.org/.../olof/tegra into tegra/soc2
      Merge tag 'tegra-boards' of git://git.kernel.org/.../olof/tegra into tegra/boards
      Merge branch 'depends/irqdomain' into next/drivers
      Merge branch 'ux500-fixes-20120301' of git://git.kernel.org/.../linusw/linux-stericsson into next/fixes-non-critical
      Merge branch 'ux500/timers' into next/timer
      Merge branch 'vexpress/timer' into next/timer
      Merge branch 'local_timers-for-arm-soc' of git://git.kernel.org/.../maz/arm-platforms into next/timer
      ARM: shmobile: remove additional __io() macro use
      Merge branch 'local_timers-for-arm-soc' of git://git.kernel.org/.../maz/arm-platforms into next/timer
      Merge tag 'imx25-iomux-ds' of git://git.pengutronix.de/git/imx/linux-2.6 into next/fixes-non-critical
      Merge branches 'lpc32xx/mach-lpc32xx-eth' and 'lpc32xx/mach-lpc32xx-usb' of git://git.antcom.de/linux-2.6 into lpc32xx/drivers
      Merge branch 'lpc32xx/drivers' into next/drivers
      Merge branch 'ep93xx-for-arm-soc' of git://github.com/RyanMallon/linux-2.6 into next/cleanup
      Merge branch 'fixes' of git://gitorious.org/linux-davinci/linux-davinci into next/fixes-non-critical
      Merge branch 'board-specific' of git://github.com/hzhuang1/linux into next/boards
      Merge branch 'fixes-non-critical' of git://github.com/hzhuang1/linux into next/maintainers
      Merge tag 'imx35-cam-fb' of git://git.pengutronix.de/git/imx/linux-2.6 into next/boards
      Merge branch 'renesas/fixes' into renesas/soc
      Merge branch 'renesas/soc' into next/soc
      Merge branch 'v3.4/features' of git://gitorious.org/linux-davinci/linux-davinci into next/drivers
      Merge branch 'next/soc-exynos5250-gpio' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'next/soc-exynos5250-arch' of git://git.kernel.org/.../kgene/linux-samsung into samsung/exynos5
      Merge branch 'for-armsoc' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm into next/soc2
      Merge branch 'samsung/exynos5' into next/soc2
      Merge branch 'samsung/soc' into next/soc2
      Merge branch 'at91-3.4-cleanup2-DT2' of git://github.com/at91linux/linux-at91 into next/dt
      Merge branch 'at91-3.4-cleanup2-DT2+USB' of git://github.com/at91linux/linux-at91 into next/dt
      Merge branch 'ux500/soc' into ux500/dt
      Merge branch 'depends/driver-core' into ux500/dt
      ARM: ux500: Initial Device Tree support for Snowball
      ARM: ux500: combine the board init functions for DT boot
      ARM: ux500: split dts file for snowball into generic part
      Merge branch 'ux500/dt' into next/dt2
      Merge branch 'spear/dt' into next/dt2
      ARM: tegra: select USB_ULPI if USB is selected
      clk: make CONFIG_COMMON_CLK invisible
      Merge branch 'for-3.4/dt' of git://git.kernel.org/.../olof/tegra into next/dt2
      Merge branch 'for-3.4/cleanup-and-fixes' of git://git.kernel.org/.../olof/tegra into tegra/cleanups
      Merge branch 'tegra/cleanups' into next/cleanup2
      Merge branch 'for-3.4/boards' of git://git.kernel.org/.../olof/tegra into next/boards
      Merge branch 'fixes' into next/fixes-non-critical
      Merge branch 'renesas/timer' into next/timer
      Merge branch 'samsung/cleanup-exynos-clock' into next/soc
      Merge branch 'imx/defconfig' into next/drivers
      Merge branch 'next/fixes-non-critical' into next/drivers
      Merge branch 'tegra/cleanups' into next/timer
      Merge branch 'next/fixes-non-critical' into for-next
      Merge branch 'next/maintainers' into for-next
      Merge branch 'next/cleanup' into for-next
      Merge branch 'next/timer' into for-next
      Merge branch 'next/soc' into for-next
      Merge branch 'next/boards' into for-next
      Merge branch 'next/rpmsg' into for-next
      Merge branch 'next/drivers' into for-next
      Merge branch 'next/dt' into for-next
      Merge branch 'next/cleanup2' into for-next
      Merge branch 'next/drivers2' into for-next
      Merge branch 'next/clk' into for-next
      Merge branch 'next/soc2' into for-next
      Merge branch 'next/dt2' into for-next

Axel Lin (1):
      rpmsg: rename virtqueue_add_buf_gfp to virtqueue_add_buf

Benoit Cousson (14):
      arm/dts: OMAP: Remove bootargs node from board files
      ARM: OMAP2+: kconfig: Enable devicetree by default for OMAP2+ systems
      ARM: OMAP2+: board-generic: Remove un-needed .atag_offset for DT_MACHINE
      ARM: OMAP2+: omap_device: Replace dev_warn by dev_dbg in omap_device_build_from_dt
      ARM: OMAP2+: pm: Do not init statically the SR and voltage layer with DT
      ARM: OMAP1: kconfig: Enable IRQ_DOMAIN by default for OMAP1 platforms
      arm/dts: OMAP3&4: Remove the '0x' prefix for serial nodes
      arm/dts: OMAP4: Add i2c controller nodes
      arm/dts: OMAP3: Add i2c controller nodes
      arm/dts: OMAP4: Update DTS file with new GIC bindings
      Merge branch 'irqdomain/next' of git://git.secretlab.ca/git/linux-2.6 into for_3.4/dt_irq_domain2
      ARM: OMAP2/3: intc: Add DT support for TI interrupt controller
      arm/dts: OMAP3: Add interrupt-controller bindings for INTC
      ARM: OMAP2+: board-generic: Use of_irq_init API

Bernhard Walle (1):
      ARM: OMAP2+: GPMC: Export gpmc_enable_hwecc and gpmc_calculate_ecc

Boojin Kim (2):
      ARM: EXYNOS: Enable MDMA driver
      ARM: EXYNOS: add support DMA for EXYNOS4X12 SoC

Changhwan Youn (1):
      ARM: EXYNOS: fix cycle count for periodic mode of clock event timers

Dan Liang (2):
      ARM: at91/at91sam9x5: overall definition
      ARM: at91/at91sam9x5: SoC basic support

Daniel Lezcano (4):
      ARM: at91: coding style fixes
      ARM: at91: declare header name
      ARM: at91: remove wait_for_interrupt definition
      ARM: at91: implement the standby function for pm/cpuidle

Danny Kukawka (3):
      ARM: ux500: included linux/gpio.h twice
      ARM: OMAP: clock.c: included linux/debugfs.h twice
      ARM: OMAP2+: included some headers twice

Dirk Behme (1):
      ARM: imx6: Rename DEBUG_IMX6Q_UART to UART4

Dmitry Artamonow (3):
      arm/tegra: fix harmony pinmux for PCIe
      arm/tegra: add timeout to PCIe PLL lock detection loop
      arm/tegra: pcie: fix return value of function

Doug Anderson (2):
      ARM: tegra: Introduce define DEBUG_UART_SHIFT
      ARM: tegra: uncompress.h: Store UART address in a variable

Eunki Kim (1):
      ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5

Fabio Estevam (16):
      ARM: mx28: Let audio support be built by default
      ARM: mx28: Remove duplicate OCOTP error message
      ARM: mx28evk: Simplify GPIO requests
      ARM: mxs: Use a proper timeout mechanism
      ARM: mach-pcm038: Fix field name of regulator_consumer_supply struct
      ARM: imx_v4_v5_defconfig: Fix the selection of 32 bit flash support for iMX21ADS board
      ARM: imx_v6_v7_defconfig: Add support for framebuffer and camera on mx31
      ARM: mx27_3ds: Add camera support
      ARM: imx_v4_v5_defconfig: Update defconfig
      ARM: plat-mxc: audmux-v1: Remove unneeded ifdef's
      ARM: mx3: Let mx31 and mx35 share the same CCM header file
      ARM: mach-imx: mx3: Fix section mismatch in imx3_init_l2x0()
      ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI
      ARM: mx3: Setup AIPS registers
      ARM: mx5: Use common function for configuring AIPS
      ARM: mx35: Setup the AIPS registers

Felipe Balbi (4):
      ARM: OMAP3+: SmartReflex: add missing platform_set_drvdata()
      ARM: OMAP3+: SmartReflex: move late_initcall() closer to its argument
      ARM: OMAP3+: SmartReflex: misc cleanups
      ARM: OMAP3+: SmartReflex: micro-optimization for sanity check

Felipe Contreras (1):
      ARM: OMAP: mailbox: trivial whitespace fix

Grazvydas Ignotas (2):
      ARM: OMAP: pandora: add support for backlight and poweroff
      ARM: omap: pandora: fix usbhs platform data

H Hartley Sweeten (1):
      ep93xx: Convert the watchdog driver into a platform device.

Haojian Zhuang (16):
      rtc: sa1100: remove periodic code
      rtc: sa1100: remove verification code of alarm
      rtc: sa1100: declare irq in resource
      ARM: pxa: add rtc dummy clock
      rtc: sa1100: enable clk support
      ARM: mmp: append irq name of gpio device
      ARM: pxa: add dummy clock for pxa25x and pxa27x
      ARM: mmp: enable rtc in pxa910
      rtc: sa1100: add OF support
      serial: pxa: add OF support
      i2c: pxa: add OF support
      ARM: mmp: enable rtc clk in pxa168
      ARM: mmp: append OF support on pxa168
      ARM: dts: append DTS file of pxa168
      Document: devicetree: add OF documents for arch-mmp
      MAINTAINERS: update MAINTAINERS email entry

Heiko Schocher (1):
      ARM: davinci: map default_queue to edma channels

Heiko Stuebner (21):
      ARM: S3C24XX: remove unused spi gpio setup functions
      ARM: S3C24XX: move spi-s3c24xx platdata out of mach
      ARM: S3C24XX: Remove extern declaration of clk_msysclk
      ARM: S3C24XX: move common S3C2443 clock definitions to clock.h
      ARM: S3C2410: move s3c2410_baseclk_add to clock.h
      ARM: SAMSUNG: cleanup of rtc register definitions
      rtc-s3c: make room for more variants in devicetree block
      rtc-s3c: add variants for S3C2443 and S3C2416
      ARM: S3C2443/S3C2416: add s3c_rtc_setname and rename rtc devices
      ARM: S3C24XX: Move s3c2443-clock.c to mach-s3c24xx
      ARM: S3C24XX: Move common-smdk code to mach directory
      ARM: S3C24XX: move simtec-specific code to mach directory
      ARM: S3C24XX: Consolidate Simtec extensions
      ARM: S3C24XX: Move device setup files to mach directory
      ARM: S3C24XX: Fix indentation of dma-s3c2443
      ARM: S3C24XX: Reuse S3C2443 dma for S3C2416
      ARM: S3C24XX: remove obsolete S3C2416_DMA option
      ARM: S3C24XX: remove XXX_setup_clocks method from S3C2443
      ARM: S3C24XX: add get_rate for clk_h on S3C2416/2443
      ARM: S3C24XX: add get_rate for clk_p on S3C2416/2443
      ARM: S3C24XX: remove call to s3c24xx_setup_clocks

Heiko St?bner (2):
      pxa: magician/hx4700: Convert to gpio-regulator from bq24022
      regulator: Remove bq24022 regulator driver

Hong Xu (1):
      ARM: at91: Update struct atmel_nand_data to support PMECC

Huang Shijie (1):
      ARM: mxs: add GPMI-NAND support for imx23/imx28

Igor Grinberg (1):
      ARM: OMAP3: cm-t3517: add EMAC support

Ilya Yanok (3):
      ARM: OMAP: move generic EMAC init to separate file
      arm/dts: mt_ventoux: very basic support for TeeJet Mt.Ventoux board
      ARM: OMAP2+: ads7846_init: put gpio_pendown into pdata if it's provided

Jaccon Bastiaansen (4):
      CS89x0 : add platform driver support
      CS89x0 : add CS89x0 platform device to the iMX21ADS board
      CS89x0 : remove QQ2440 board support from the CS89x0 driver
      CS89x0 : add CS89x0 platform device to the iMX31ADS board

Jaecheol Lee (1):
      ARM: EXYNOS: add clock registers for exynos4x12-cpufreq

Jaehoon Chung (3):
      ARM: SAMSUNG: support the second capability for samsung-soc
      mmc: sdhci-s3c: add platform data for the second capability
      ARM: SAMSUNG: change the name from s3c-sdhci to exynos4-sdhci

Janusz Krzysztofik (12):
      ARM: OMAP1: ams-delta: register latch dependent devices later
      ARM: OMAP1: ams-delta: convert latches to basic_mmio_gpio
      ARM: OMAP1: ams-delta: supersede custom led device by leds-gpio
      LED: drop leds-ams-delta driver
      MTD: NAND: ams-delta: use GPIO instead of custom I/O
      omapfb: lcd_ams_delta: drive control lines over GPIO
      input: serio: ams-delta: toggle keyboard power over GPIO
      ARM: OMAP1: ams-delta: fix incorrect section tags
      ARM: OMAP1: ams-delta: clean up init data section assignments
      ARM: OMAP1: ams-delta: set up regulator over modem reset GPIO pin
      ARM: OMAP1: ams-delta: update the modem to use regulator API
      ASoC: OMAP: ams-delta: drop .set_bias_level callback

Jarkko Nikula (1):
      ARM: OMAP: McSPI: Remove unused flag from struct omap2_mcspi_device_config

Jason Cooper (2):
      ARM: kirkwood: add dreamplug (fdt) support.
      ARM: kirkwood: convert uart0 to devicetree.

Javier Martin (5):
      i.MX27: visstrim_m10: Add m41t00 RTC support.
      i.MX27: visstrim_m10: Sort IMX_HAVE_PLATFORM_MXC_MMC properly.
      i.MX27: visstrim_m10: Register I2C devices after I2C busses have been added.
      i.MX27: visstrim_m10: Add video support.
      i.MX27: visstrim_m10: Add led support.

Jean Pihet (3):
      ARM: OMAP3+: SmartReflex: fix the use of debugfs_create_* API
      ARM: OMAP3+: SmartReflex: fix error handling
      ARM: OMAP2+: PM debug: fix the use of debugfs_create_* API

Jean-Christophe PLAGNIOL-VILLARD (50):
      ARM: at91: code removal of CAP9 SoC
      ARM: at91: factorise duplicated at91sam9 idle
      ARM: at91/at91x40: remove use of at91_sys_read/write
      ARM: at91: make matrix register base soc independent
      ARM: at91: make ST (System Timer) soc independent
      ARM: at91/pm_slowclock: rename register to named define
      ARM: at91/pm_slowclock: function slow_clock() accepts parameters
      ARM: at91: move at91rm9200 sdramc defines to at91rm9200_sdramc.h
      ARM: at91: make sdram/ddr register base soc independent
      ARM: at91/pm_slowclock: add runtime detection of memory contoller
      ARM: at91/PMC: make register base soc independent
      ARM: at91/rtc-at91sam9: each SoC can select the RTT device to use
      ARM: at91:rtc/rtc-at91sam9: ioremap register bank
      ARM: at91/rtc-at91sam9: pass the GPBR to use via resources
      ARM: at91: finally drop at91_sys_read/write
      ARM: at91: merge SRAM Memory banks thanks to mirroring
      Atmel: move console default platform_device to serial driver
      ARM: at91/board-dt: drop default console
      ARM: at91: properly sort dtb files in Makefile.boot
      ARM: at91: pit add DT support
      ARM: at91: usb_a9g20/dt: add leds support
      ARM: at91: at91sam9m10g45ek/dt: add leds support
      ARM: at91: at91sam9m10g45ek/dt: add gpio-keys support
      ARM: at91: usb_a9g20/dt: add gpio-keys support
      ARM: at91: at91sam9x5cm/dt: add leds support
      ATMEL: fix nand ecc support
      mtd/atmel_nand: add on_flash_bbt to enable the use of On Flash BBT
      ARM: at91: enable on flash bbt for Atmel Reference and DT boards
      of: introduce helper to manage boolean
      of/mtd/nand: add generic bindings and helpers
      atmel/nand: add DT support
      ARM: at91: sam9x5 add nand support
      i2c/gpio: add DT support
      ARM: at91: sam9g20 add i2c DT support
      ARM: at91: usb_a9g20 add DT i2c support
      ARM: at91: sam9g45 add i2c DT support
      ARM: at91: sam9x5 add i2c DT support
      ARM: at91/dt: add Calao DAB-MMX daugther board support for USB-A9G20
      ARM: at91/dt: add specific DT soc init
      ARM: at91: add pmc DT support
      ARM: at91: always enable sam9 restart
      ARM: at91: add RSTC (Reset Controller) dt support
      ARM: at91: add ram controller DT support
      ARM: at91: add Shutdown Controller (SHDWC) DT support
      ARM: at91: usb ohci add dt support
      ARM: at91: dt: enable usb ohci for sam9g20, sam9g45 amd sam9x5
      ARM: at91: usb ehci add dt support
      ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5
      USB: at91: Device udc add dt support
      ARM: at91: sam9g20 udc add dt support

Jesper Juhl (1):
      ARM: Remove redundant ';' from avic_irq_set_priority()

Jett.Zhou (1):
      ARM: sa1100: clean up clock support

Jingoo Han (1):
      ARM: SAMSUNG: Add a callback 'notify_after' for PWM backlight control

Jon Hunter (1):
      ARM: OMAP: Remove definition cpu_is_omap4430()

Joonyoung Shim (2):
      ARM: S3C64XX: Add usb otg phy control
      ARM: S5PV210: Add usb otg phy control

Josh Wu (2):
      ARM: at91: add clock selection parameter for at91_add_device_isi()
      ARM: at91: add Atmel ISI and ov2640 support on sam9m10g45 board

Kamil Debski (3):
      ARM: EXYNOS: add G2D to mach-nuri
      ARM: EXYNOS: add G2D to mach-universal
      ARM: SAMSUNG: add G2D to plat-s5p and mach-exynos

Kevin Hilman (6):
      ARM: OMAP: convert omap_device_build() and callers to __init
      Merge remote-tracking branch 'omap/hsmmc' into for_3.4/cleanup/pm-base
      ARM: OMAP: omap_device: remove omap_device_parent
      ARM: OMAP2+: PM: fix section mismatch with omap2_init_processor_devices()
      ARM: OMAP2+: PM: fix wakeupgen warning when hotplug disabled
      ARM: OMAP2+: gpmc-smsc911x: only register regulator for first instance

Kukjin Kim (32):
      ARM: EXYNOS: use static declaration when it is not used in other files
      ARM: S3C24XX: use static declaration when it is not used in other files
      ARM: S3C64XX: use static declaration when it is not used in other files
      ARM: S5P64X0: use static declaration when it is not used in other files
      ARM: S5PC100: use static declaration when it is not used in other files
      ARM: S5PV210: use static declaration when it is not used in other files
      ARM: SAMSUNG: use static declaration when it is not used in other files
      ARM: S3C24XX: change the ARCH_S3C2410 to ARCH_S3C24XX
      ARM: S3C2410: move mach-s3c2410/* into mach-s3c24xx/
      ARM: S3C2412: move mach-s3c2412/* into mach-s3c24xx/
      ARM: S3C2416: move mach-s3c2416/* into mach-s3c24xx/
      ARM: S3C2440: move mach-s3c2440/* into mach-s3c24xx/
      ARM: S3C2443: move mach-s3c2443/* into mach-s3c24xx/
      ARM: s3c2410_defconfig: update s3c2410_defconfig
      Merge branch 'topic/cleanup-s3c24xx' into next/cleanup-s3c24xx
      Merge branch 'topic/cleanup-use-static' into next/cleanup-use-static
      Merge branch 'next/cleanup-use-static' into next/cleanup-exynos-clock
      ARM: EXYNOS: replace clock.c for other new EXYNOS SoCs
      ARM: EXYNOS: use static declaration on regarding clock
      ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock
      PM / devfreq: update the name of EXYNOS clock register
      ARM: EXYNOS: to declare static for mach-exynos/common.c
      ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts()
      ARM: EXYNOS: add clock part for EXYNOS5250 SoC
      ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
      ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
      ARM: EXYNOS: add support for EXYNOS5250 SoC
      ARM: EXYNOS: add interrupt definitions for EXYNOS5250
      ARM: EXYNOS: add support get_core_count() for EXYNOS5250
      ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5 SoCs
      ARM: EXYNOS: add support device tree enabled board file for EXYNOS5
      ARM: dts: add initial dts file for EXYNOS5250, SMDK5250

Lauri Hintsala (1):
      ARM: mxs: Add initial support for Bluegiga APX4 Development Kit

Laxman Dewangan (2):
      ARM: tegra: Pause DMA when reading transfer count
      ARM: tegra: dma: not required to move requestor when stopping.

Lee Jones (11):
      ARM: ux500: pass parent pointer to each platform device
      ARM: ux500: export System-on-Chip information ux500 via sysfs
      ARM: ux500: move top level platform devices in sysfs to /sys/devices/socX
      ARM: ux500: remove intermediary add_platform_device* functions
      ARM: ux500: CONFIG: Enable Device Tree support for future endeavours
      ARM: ux500: db8500: list most devices in the snowball device tree
      ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt Controller) in Device Tree
      ARM: ux500: Enable PL011 AMBA UART Controller for Device Tree
      ARM: ux500: Enable PL310 Level 2 Cache Controller in Device Tree
      ARM: ux500: Enable PL022 SSP Controller in Device Tree
      ARM: ux500: Provide local timer support for Device Tree

Leon Romanovsky (3):
      ARM: dt: tegra: Enable device tree audio codec on PAZ00 board.
      ARM: dt: tegra: Enable headset autodetection on PAZ00 board.
      ASoC: DT: Add digital microphone binding to PAZ00 board.

Linus Walleij (5):
      ARM: plat-nomadik: get rid of global mtu base pointer
      ARM: plat-nomadik: handle clocking properly
      ARM: plat-nomadik: modernize MTU timer
      ARM: ux500: delete TPS6105X selection
      ARM: ux500: solve some Kconfig mess

Lothar Wa?mann (1):
      arm/mxs: Add support for SSP/MMC ports 2 & 3

Magnus Damm (35):
      sh: introduce sh_clk_ops in parallel with clk_ops
      sh: convert cpg code to sh_clk_ops
      ARM: mach-shmobile: sh7367 sh_clk_ops rename
      ARM: mach-shmobile: sh7377 sh_clk_ops rename
      ARM: mach-shmobile: sh7372 sh_clk_ops rename
      ARM: mach-shmobile: sh73a0 sh_clk_ops rename
      ARM: mach-shmobile: r8a7740 sh_clk_ops rename
      ARM: mach-shmobile: r8a7779 sh_clk_ops rename
      sh: sh header sh_clk_ops rename
      sh: sh2 sh_clk_ops rename
      sh: sh2a sh_clk_ops rename
      sh: sh3 sh_clk_ops rename
      sh: sh4 sh_clk_ops rename
      sh: sh4a sh_clk_ops rename
      sh: sh5 sh_clk_ops rename
      sh: board sh_clk_ops rename
      sh: remove clk_ops
      ARM: mach-shmobile: sh7367 map_io and init_early update
      ARM: mach-shmobile: sh7377 map_io and init_early update
      ARM: mach-shmobile: sh7372 map_io and init_early update
      ARM: mach-shmobile: sh73a0 map_io and init_early update
      ARM: mach-shmobile: r8a7740 map_io and init_early update
      ARM: mach-shmobile: r8a7779 map_io and init_early update
      ARM: mach-shmobile: r8a7779 L2 cache support
      ARM: mach-shmobile: rename clk_init() to shmobile_clk_init()
      ARM: mach-shmobile: Move sh7372 Mackerel external clk setup
      ARM: mach-shmobile: Move sh7372 AP4EVB external clk setup
      ARM: mach-shmobile: add shmobile_earlytimer_init()
      ARM: mach-shmobile: sh7367 and G3EVM timer rework
      ARM: mach-shmobile: sh7377 and G4EVM timer rework
      ARM: mach-shmobile: sh7372, AP4EVB and Mackerel timer rework
      ARM: mach-shmobile: sh73a0, AG5EVM and Kota2 timer rework
      ARM: mach-shmobile: r8a7740 and Bonito timer rework
      ARM: mach-shmobile: r8a7779 and Marzen timer rework
      ARM: mach-shmobile: default to no earlytimer

Manjunath Hadli (10):
      ARM: davinci: dm644x: move private definitions to C file
      ARM: davinci: dm365: move private definitions to C file
      ARM: davinci: dm646x: move private definitions to C file
      ARM: davinci: create new common platform header for davinci
      ARM: davinci: streamline sysmod access
      ARM: davinci: dm644x: improve readability using macro
      ARM: davinci: dm644x: fix inconsistent variable naming
      ARM: davinci: dm644x: don't force vpfe registeration on all boards
      ARM: davinci: dm644x: add support for v4l2 video display
      ARM: davinci: dm644x evm: add support for VPBE display

Marc Dietrich (5):
      ARM: tegra: paz00: fix wrong SD1 power gpio
      ARM: tegra: paz00: fix wrong UART port on mini-pcie plug
      ARM: dt: tegra: add ADT7461 temperature sensor to paz00 device tree
      ARM: dt: tegra: add the power gpio key to paz00 device tree
      ARM: dt: tegra: add the wifi led to paz00 device tree

Marc Zyngier (16):
      ARM: smp_twd: make local_timer_stop a symbol instead of a #define
      ARM: local timers: introduce a new registration interface
      ARM: smp_twd: add runtime registration support
      ARM: smp_twd: add device tree support
      ARM: OMAP4: convert to twd_local_timer_register() interface
      ARM: plat-versatile: convert to twd_local_timer_register() interface
      ARM: tegra: convert to twd_local_timer_register() interface
      ARM: shmobile: convert to twd_local_timer_register() interface
      ARM: ux500: convert to twd_local_timer_register() interface
      ARM: highbank: convert to twd_local_timer_register() interface
      ARM: imx6q: convert to twd_local_timer_register() interface
      ARM: smp_twd: remove old local timer interface
      ARM: local timers: convert exynos to runtime registration interface
      ARM: local timers: convert MSM to runtime registration interface
      ARM: local timers: make the runtime registration interface mandatory
      ARM: ux500: fix compilation after local timer rework

Mark Asselstine (1):
      rpmsg: fix build warning when dma_addr_t is 64-bit

Mark Brown (12):
      ARM: S3C64XX: Support GPIO LEDs on Cragganmore
      ARM: S3C64XX: Fix build of Cragganmore after SPI changes
      ARM: S3C64XX: Enable power management for disk on Cragganmore
      ARM: S3C64XX: Enable power management for WiFi on Cragganmore
      ARM: S3C64XX: Add hookup for Tomatin module on Cragganmore
      ARM: S3C64XX: Add basic cpuidle driver
      ARM: S3C64XX: Add a SPKVDD supply for CODECs on Cragganmore
      ARM: S3C64XX: Gate some more clocks by default
      ARM: S3C64XX: Reduce residency requirement for cpuidle WFI mode
      ARM: S3C64XX: Define some additional always off clocks
      ARM: S3C64XX: Add some more Cragganmore module IDs to the table
      ARM: S3C64XX: Supply platform data for SPI on Cragganmore

Mark Grosen (2):
      remoteproc: do not require an iommu
      remoteproc: avoid registering a virtio device if not supported

Masanari Iida (1):
      ARM: OMAP1: Fix typo in lcd_dma.c

Maxim Osipov (1):
      ARM: at91: Add external RTC for Flexibity board

Mehnert (1):
      iomux-mx25.h slew rate adjusted for LCD __LD pins

Mike Turquette (3):
      Documentation: common clk API
      clk: introduce the common clock framework
      clk: basic clock hardware types

Minho Ban (1):
      ARM: SAMSUNG: use spin_lock_irqsave() in clk_{enable,disable}

Mircea Gherzan (1):
      ARM: OMAP: enable Bluetooth on the PandaBoard

MyungJoo Ham (4):
      ARM: EXYNOS: Add DMC1, allow PPMU access for DMC
      PM / devfreq: update the name of EXYNOS clock registers that were omitted
      ARM: EXYNOS: Add clock register addresses for EXYNOS4X12 bus devfreq driver
      ARM: EXYNOS: support Exynos4210-bus Devfreq driver on Nuri board

NeilBrown (2):
      ARM: OMAP2+: UART: remove unused fields in omap_uart_state.
      ARM: OMAP2+: remove some orphan function declarations.

Nicolas Ferre (29):
      Merge remote-tracking branch 'armsoc/depends/rmk/for-armsoc' into at91-3.4-base
      ARM: at91/dma: remove platform data from DMA controller
      ARM: at91/dma: DMA controller registering with DT support
      ARM: at91/at91sam9x5: PMC header file
      ARM: at91/at91sam9x5: clock management for at91sam9x5 chip family
      ARM: at91/at91sam9x5: Configuration and Makefile
      ARM: at91/at91sam9x5: Device tree definition files
      Merge remote-tracking branch 'armsoc/at91/device-board' into at91-3.4-base2
      Merge remote-tracking branch 'armsoc/at91/9x5' into at91-3.4-base2
      ARM: at91/ST: remove not needed casts
      ARM: at91/PMC: move assignment out of printf
      ARM: at91: add at91sam9g25ek.dts in Makefile.boot
      Merge branch 'irqdomain/next' of git://git.secretlab.ca/git/linux-2.6
      ARM: at91/aic: add irq domain and device tree support
      ARM: at91/snapper9260: move gpio_to_irq out of structure initialization
      ARM/USB: at91/ohci-at91: remove the use of irq_to_gpio
      ARM: at91/gpio: change comments and one variable name
      ARM: at91/gpio: add irqdomain and DT support
      ARM: at91/gpio: non-DT builds do not have gpio_chip.of_node field
      ARM: at91/gpio: add .to_irq gpio_chip handler
      ARM: at91/gpio: remove the static specification of gpio_chip.base
      ARM: at91/board-dt: remove AIC irq domain from board file
      ARM: at91: AIC and GPIO IRQ device tree initialization
      ARM: at91/pit: add traces in case of error
      ARM: at91/tclib: take iomem size from resource
      ARM: at91/tc: add device tree support to atmel_tclib
      ARM: at91/tc/clocksource: Add 32 bit variant to Timer Counter
      ARM: at91: add sam9_smc.o to at91sam9x5 build
      ARM: at91/pio: add new PIO3 features

Nishanth Menon (6):
      ARM: OMAP3+: SmartReflex: fix err interrupt disable sequence
      ARM: OMAP3+: SmartReflex Class3: disable errorgen before disable VP
      ARM: OMAP3+: SmartReflex: Add a shutdown hook
      ARM: OMAP3+: SmartReflex: Fix status masking in ERRCONFIG register
      ARM: OMAP3+: SmartReflex: clear ERRCONFIG_VPBOUNDINTST only on a need
      ARM: OMAP3+: hwmod: add SmartReflex IRQs

Ohad Ben-Cohen (30):
      remoteproc: add framework for controlling remote processors
      remoteproc: add debugfs entries
      remoteproc: create rpmsg virtio device
      remoteproc/omap: add a remoteproc driver for OMAP4
      rpmsg: add virtio-based remote processor messaging bus
      samples/rpmsg: add an rpmsg driver sample
      remoteproc: remove unused resource type
      remoteproc/omap: utilize module_platform_driver
      remoteproc: look for truncated firmware images
      remoteproc: add Kconfig menu
      rpmsg: add Kconfig menu
      ARM: OMAP: omap_device: Expose omap_device_{alloc, delete, register}
      remoteproc: depend on EXPERIMENTAL
      rpmsg: depend on EXPERIMENTAL
      remoteproc: don't use virtio's weak barriers
      remoteproc: bail out if firmware has different endianess
      remoteproc: s/big switch/lookup table/
      remoteproc: make sure we're parsing a 32bit firmware
      remoteproc/omap: two Kconfig fixes
      rpmsg: fix name service endpoint leak
      rpmsg: validate incoming message length before propagating
      rpmsg: fix published buffer length in rpmsg_recv_done
      ARM: OMAP: don't build hwspinlock in vain
      remoteproc: resource table overhaul
      remoteproc: remoteproc_rpmsg -> remoteproc_virtio
      remoteproc: safer boot/shutdown order
      remoteproc: remove the single rpmsg vdev limitation
      remoteproc/omap: remove the mbox_callback limitation
      remoteproc: remove the hardcoded vring alignment
      remoteproc: cleanup resource table parsing paths

Ola Lilja (3):
      ARM: ux500: Add placeholder for clk_set_parent
      ARM: ux500: Add DMA-channels for MSP
      ARM: ux500: Add audio-regulators

Olof Johansson (56):
      ARM: tegra: emc: device tree bindings
      ARM: tegra: seaboard: add EMC table to device tree
      ARM: tegra: Don't WARN_ON() for too early dma channel allocations
      ARM: tegra: use APB DMA for accessing APB devices
      ARM: tegra: fuse: use apbio dma for register access
      ARM: tegra: fuse: add functions to access chip revision
      ARM: tegra: fuse: add bct strapping reading
      ARM: tegra: emc: convert tegra2_emc to a platform driver
      ARM: tegra: emc: device tree support
      Merge branch 'ux500-timers' of git://git.kernel.org/.../linusw/linux-stericsson into ux500/timers
      Merge branch 'at91-3.4-base' of git://github.com/at91linux/linux-at91 into next/cleanup
      Merge branch 'at91-3.4-base+pm_cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup
      Merge branch 'at91-3.4-base' of git://github.com/at91linux/linux-at91 into at91/base
      Merge branch 'at91-3.4-base+device_board' of git://github.com/at91linux/linux-at91 into at91/device-board
      Merge branch 'at91-3.4-base+pm_cleanup' of git://github.com/at91linux/linux-at91 into at91/pm_cleanup
      Merge branch 'at91-3.4-base+9x5' of git://github.com/at91linux/linux-at91 into at91/9x5
      Merge branch 'ux500-timers' of git://git.kernel.org/.../linusw/linux-stericsson into next/soc
      Merge branch 'mxs/clk' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
      Merge branch 'mxs/defconfig' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
      Merge branch 'at91-3.4-base+9x5' of git://github.com/at91linux/linux-at91 into next/soc
      Merge branch 'at91-3.4-base+device_board' of git://github.com/at91linux/linux-at91 into next/drivers
      Merge branch 'mxs/boards' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/boards
      Merge branch 'features/imx-clk-prepare' of git://git.pengutronix.de/git/imx/linux-2.6 into next/drivers
      Merge branch 'for-arm-soc' of git://sources.calxeda.com/kernel/linux into next/soc
      Merge branch 'for-3.4/soc' into for-3.4/t30-smp
      Merge branch 'for-3.4/soc-drivers' into for-3.4/t30-smp
      Merge branch 'depends/rmk/for-armsoc' into for-3.4/cleanup-and-fixes
      Merge branch 'fixes-non-critical' of git://git.kernel.org/.../tmlind/linux-omap into next/fixes-non-critical
      Merge branch 'cleanup' of git://git.kernel.org/.../tmlind/linux-omap into next/cleanup
      Merge branch 'next/cleanup-use-static' of git://git.kernel.org/.../kgene/linux-samsung into next/cleanup
      Merge branch 'maintainers' of git://gitorious.org/linux-davinci/linux-davinci into next/maintainers
      Merge branch 'fixes-non-critical-part2' of git://git.kernel.org/.../tmlind/linux-omap into next/fixes-non-critical
      Merge tag 'rpmsg-fixes-and-more-for-3.4' of git://git.kernel.org/.../ohad/remoteproc into next/rpmsg
      Merge branch 'next/cleanup-s3c24xx' of git://git.kernel.org/.../kgene/linux-samsung into next/cleanup
      Merge tag 'imx35-imx5-aips-setup' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
      Merge branch 'dt' of git://github.com/hzhuang1/linux into next/dt
      Merge branch 'regulator' of git://github.com/hzhuang1/linux into next/drivers
      Merge branch 'rtc' of git://github.com/hzhuang1/linux into next/drivers
      Merge branch 'io-cleanup-for-3.4' of git://sources.calxeda.com/kernel/linux into next/cleanup2
      Merge branch 'fixes-non-critical-part3' of git://git.kernel.org/.../tmlind/linux-omap into next/fixes-non-critical
      Merge branch 'ams-delta' of git://git.kernel.org/.../tmlind/linux-omap into next/boards
      Merge branch 'cleanup-pm' of git://git.kernel.org/.../tmlind/linux-omap into next/cleanup
      Merge branch 'uart' of git://git.kernel.org/.../tmlind/linux-omap into next/cleanup
      Merge branch 'dt-part2' of git://git.kernel.org/.../tmlind/linux-omap into next/dt
      Merge branch 'sr' of git://git.kernel.org/.../tmlind/linux-omap into next/drivers
      Merge branch 'board' of git://git.kernel.org/.../tmlind/linux-omap into next/boards
      Merge branch 'next/devel-samsung' of git://git.kernel.org/.../kgene/linux-samsung into next/soc
      Merge branch 'fix-smsc911x-regulator' of git://git.kernel.org/.../tmlind/linux-omap into fixes
      Merge branch 'next/cleanup-exynos-clock' of git://git.kernel.org/.../kgene/linux-samsung into next/cleanup
      Merge branch 'next/board-samsung' of git://git.kernel.org/.../kgene/linux-samsung into next/boards
      Merge branch 'next/devel-samsung-mmc' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'next/devel-samsung-dma' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'next/devel-samsung-pd' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'soc' of git://git.kernel.org/.../rafael/renesas into next/soc
      Merge branch 'io-cleanup-for-3.4' of git://sources.calxeda.com/kernel/linux into next/cleanup2
      ARM: tegra: update main repo and add patchwork

Paul Parsons (6):
      pxa/hx4700: Correct StrataFlash block size discovery
      pxa/hx4700: Add ASIC3 LED support
      pxa/hx4700: Fix PXA_GPIO_IRQ_BASE/IRQ_NUM values
      ARM: pxa/hx4700: Remove unwanted request for GPIO105
      ARM: pxa/hx4700: Reduce sleep mode battery discharge by 35%
      pxa/hx4700: Remove pcmcia platform_device structure

Paul Walmsley (7):
      ARM: OMAP2+: I2C: always compile I2C reset code, even if I2C driver is not built
      ARM: OMAP2xxx: PM: remove obsolete timer disable code in the suspend path
      ARM: OMAP3: PM: remove superfluous calls to pwrdm_clear_all_prev_pwrst()
      ARM: OMAP2+: PM: clean up omap_set_pwrdm_state()
      ARM: OMAP2+: PM: share clkdms_setup() across OMAP2, 3, 4
      ARM: OMAP2+: omap_device: call all suspend, resume callbacks when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set
      ARM: OMAP2+: PM: share some suspend-related functions across OMAP2, 3, 4

Pawel Moll (8):
      ARM: vexpress: Get rid of MMIO_P2V
      ARM: versatile: Map local timers using Device Tree when possible
      ARM: vexpress: Use FDT data in platform SMP calls
      ARM: vexpress: Add Device Tree support
      ARM: vexpress: Motherboard RS1 memory map support
      ARM: vexpress: Add Device Tree for V2P-CA5s core tile
      ARM: vexpress: Add Device Tree for V2P-CA9 core tile
      ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)

Peter De Schrijver (20):
      ARM: tegra: add support for tegra30 interrupts
      ARM: tegra: add support for new clock framework features
      ARM: tegra: implement basic tegra30 clock framework
      ARM: tegra: enable tegra30 clock framework
      ARM: tegra: initialize basic system clocks
      ARM: tegra: definitions for flow controller
      ARM: tegra: assembler code for LP3
      ARM: tegra: cpuidle driver for tegra
      ARM: tegra: Avoid compiling cpuidle code when not configured
      ARM: tegra: cleanup use of chipid register
      ARM: tegra: export Tegra chipid
      ARM: tegra: initialize Tegra chipid early
      ARM: tegra: functions to access the flowcontroller
      ARM: tegra: rework Tegra secondary CPU core bringup
      ARM: tegra: prepare powergate.c for multiple variants
      ARM: tegra: export tegra_powergate_is_powered()
      ARM: tegra: add support for Tegra30 powerdomains
      ARM: tegra: support for Tegra30 CPU powerdomains
      ARM: tegra: support for secondary cores on Tegra30
      ARM: tegra: Enable CPUIdle on Tegra20

Peter Ujfalusi (1):
      OMAP4: dma: Correct CPU version check for dma_common_ch_end

Philipp Zabel (1):
      MAINTAINERS: update maintainer entry for pxa/hx4700

Philippe Langlais (2):
      ARM: ux500: set ARCH_NR_GPIO to 355 on U8500 platforms
      ARM: ux500: fix around AB8500 GPIO macro name

Philippe R?tornaz (2):
      mx31moboard: update maintainer
      mx31moboard: Add watchdog support

Richard Zhao (15):
      ARM: mxc: time: add clk_prepare/clk_unprepare
      ARM: mxc: ahci: add clk_prepare/clk_unprepare
      ARM: mxc: pwm: add clk_prepare/clk_unprepare
      ARM: mxc: epit: add clk_prepare/clk_unprepare
      ARM: mxc: arch_reset: add clk_prepare/clk_unprepare
      ARM: mxc: audmux-v2: add clk_prepare/clk_unprepare
      ARM: pm-imx5: add clk_prepare/clk_unprepare
      ARM: mx31moboard: add clk_prepare/clk_unprepare
      serial: imx: add clk_prepare/clk_unprepare
      i2c: imx: add clk_prepare/clk_unprepare
      mmc: sdhci-esdhc-imx: add clk_prepare/clk_unprepare
      ARM: dts: imx6q-sabrelite: add 2p5v and 3p3v regulators
      ARM: dts: imx6q-sabrelite: add sgtl5000 audio codec
      ARM: mxc: make imx_dma_is_general_purpose more generic for sdma
      ARM: imx6q: add cko1 clock

Rob Herring (29):
      ARM: timer-sp: add sched_clock support
      ARM: highbank: enable sp804 based sched_clock
      ARM: highbank: remove unused memory.h
      Merge remote-tracking branch 'arm-soc/at91/base2+cleanup' into cleanup-base
      usb: ohci-pxa27x: add explicit include of hardware.h
      ARM: provide runtime hook for ioremap/iounmap
      ARM: imx: convert to common runtime ioremap hook
      ARM: msm: use runtime ioremap hook
      ARM: iop13xx: use runtime ioremap hook
      ARM: ixp4xx: use runtime ioremap hook
      ARM: ebsa110: use runtime ioremap hook
      ARM: remove compile time __arch_ioremap/__arch_iounmap
      ARM: iop13xx: move io.h externs to pci.h
      ARM: msm: clean-up mach/io.h
      [media] davinci: remove includes of mach/io.h
      ARM: davinci: remove unneeded mach/io.h include
      ARM: orion5x: clean-up mach/io.h
      ARM: tegra: clean-up mach/io.h
      ARM: ep93xx: clean-up mach/io.h
      ARM: at91: add explicit include of hardware.h to uncompressor
      ARM: dove: add explicit include of dove.h to addr-map.c
      ARM: clps711x: remove unneeded include of mach/io.h
      ARM: make mach/io.h include optional
      ARM: remove bunch of now unused mach/io.h files
      ARM: kill off __mem_pci
      ARM: fix ioremap/iounmap for !CONFIG_MMU
      ARM: iop13xx: fix missing declaration of iop13xx_init_early
      ARM: create a common IOMEM definition
      ARM: __io abuse cleanup

Roland Stigge (21):
      ARM: LPC32xx: Added lpc32xx_defconfig
      ARM: LPC32xx: clock.c: warning fix
      ARM: LPC32xx: clock.c: Fix mutex lock issues
      ARM: LPC32XX: Remove broken non-static declaration
      ARM: LPC32xx: clock.c: Missing header file
      ARM: LPC32xx: clock.c: jiffies wrapping
      ARM: LPC32xx: clock.c: Clock registration fixes
      ARM: LPC32xx: Added lpc32xx_defconfig
      ARM: LPC32xx: clock.c: warning fix
      ARM: LPC32xx: clock.c: Fix mutex lock issues
      ARM: LPC32XX: Remove broken non-static declaration
      ARM: LPC32xx: clock.c: Missing header file
      ARM: LPC32xx: clock.c: jiffies wrapping
      ARM: LPC32xx: clock.c: Clock registration fixes
      ARM: LPC32xx: ADC support for mach-lpc32xx
      ARM: LPC32xx: Fix missing and bad LPC32XX macros
      Merge branch 'lpc32xx/fixup' of git://git.kernel.org/.../arm/arm-soc into lpc32xx/tmp
      Merge branch 'lpc32xx/fixup2' of git://git.kernel.org/.../arm/arm-soc into lpc32xx/tmp
      Merge branch 'lpc32xx/drivers' of git://git.kernel.org/.../arm/arm-soc into lpc32xx/tmp
      ARM: LPC32xx: USB Support
      ARM: LPC32xx: Ethernet support

Ryan Mallon (10):
      ep93xx: Move PHYS_BASE defines to local SoC header file
      ep93xx: Don't use system controller defines in audio drivers
      ep93xx: Move GPIO defines to gpio-ep93xx.h
      ep93xx: Use ioremap for backlight driver
      ep93xx: Move peripheral defines to local SoC header
      ep93xx: Configure GPIO ports in core code
      ep93xx: Make syscon access functions private to SoC
      ep93xx: Move crunch code to mach-ep93xx directory
      ep93xx: Move EP93XX_SYSCON defines to SoC private header
      ep93xx: Remove unnecessary includes of ep93xx-regs.h

Sachin Kamat (15):
      ARM: EXYNOS: Enable G2D on ORIGEN
      ARM: S5PV210: Add missing FIMC media device to Aquila
      ARM: EXYNOS: Add missing FIMC media device to SMDKV310
      ARM: EXYNOS: Add missing FIMC media device to Origen
      ARM: EXYNOS: Hook up G2D PD to generic PD infrastructure
      ARM: EXYNOS: Hook up JPEG PD to generic PD infrastructure
      ARM: EXYNOS: Enable G2D on SMDKV310
      ARM: S5PV210: Enable MFC on SMDKV210
      ARM: S5PV210: Enable MFC on SMDKC110
      ARM: S5PV210: Enable FIMC on SMDKV210
      ARM: S5PV210: Enable FIMC on SMDKC110
      ARM: EXYNOS: Enable JPEG on SMDKV310
      ARM: EXYNOS: Enable JPEG on Origen
      ARM: S5PV210: Add JPEG board definition
      ARM: S5PV210: Enable JPEG on SMDKV210

Sangsu Park (3):
      ARM: EXYNOS: add support GPIO for EXYNOS5250
      gpio/samsung: add support GPIOlib for EXYNOS5250
      gpio/samsung: use ioremap() for EXYNOS4 GPIOlib

Sangwook Lee (1):
      ARM: EXYNOS: Enable Bluetooth on ORIGEN

Santosh Shilimkar (2):
      ARM: OMAP: fix section mismatch warning for omap4_hotplug_cpu()
      ARM: OMAP: Fix section mismatch warning for platform_cpu_die()

Sascha Hauer (4):
      ARM i.MX5/6: Add dt support for generic boards
      ARM i.MX27: Add devicetree support
      ARM i.MX: Add phytec phycore-i.MX27 (aka pcm038) devicetree support
      devicetree-bindings: Add documentation for i.MX generic boards

Sekhar Nori (2):
      MAINTAINERS: mark TI DaVinci list as "moderated"
      MAINTAINERS: add TI DaVinci git tree information

Shawn Guo (8):
      ARM: mxs: detect SoC by checking CHIPID register
      ARM: imx5: generate dtbs for imx5 boards
      ARM: dts: imx51-babbage: update mc13892 device
      ARM: dts: imx6q-arm2: add vmmc-supply for usdhc
      ARM: dts: imx6q-sabrelite: add vmmc-supply for usdhc
      MAINTAINERS: remove arch/arm/mach-mx*/ from IMX entry
      ARM: imx: update imx_v6_v7_defconfig
      ARM: defconfig: imx_v6_v7: build in REGULATOR_FIXED_VOLTAGE

Shweta Gulati (1):
      ARM: OMAP3+: SmartReflex: use voltage domain name in device attributes

Simon Glass (3):
      arm: tegra: dts: Support host/device selection and legacy mode
      arm: tegra: dts: Add legacy mode support to Tegra2x USB1 port
      arm: tegra: dts: Mark USB1 as an OTG port on Seaboard

Stefan Roese (1):
      ARM: SPEAr600: Add device-tree support to SPEAr600 boards

Stephen Warren (27):
      dt: tegra gpio: Flesh out binding documentation
      ARM: dt: tegra30.dtsi: Reformat gpio's interrupts property
      ARM: dt: tegra30.dtsi: Add extra GPIO interrupt
      ARM: dt: tegra: Add Tegra APB DMA device tree binding
      ARM: dt: tegra: Modify I2S nodes to match binding
      ARM: dt: tegra: Add labels for I2S controllers
      ARM: dt: tegra: Enable audio on WM8903 boards, disable others
      ARM: dt: Add binding for Tegra PMC
      ARM: tegra: Support Tegra30 in decompressor UART setup
      ARM: tegra: uncompress.h: Choose a UART at runtime
      ARM: tegra: Pass uncompress.h UART selection to DEBUG_LL
      ARM: tegra: Remove use of TEGRA_GPIO_TO_IRQ
      gpio: tegra: Dynamically allocate IRQ base, and support DT
      gpio: tegra: Parameterize the number of banks
      ARM: tegra: Fix EMC pdata initialization from registers
      ARM: tegra: Add a simple PMC driver
      ARM: tegra: Remove duplicate PMU interrupt inversion code
      gpio: tegra: Fix build issue due to irq_domain rework.
      ARM: dt: Add SD controller configuration to Tegra Cardhu
      ARM: tegra: Demote EMC clock inconsistency BUG to WARN
      ARM: tegra: select required CPU and L2 errata options
      ARM: tegra: uncompress.h: Don't depend on kernel headers
      ARM: tegra: match SoC name not board name in DT board files
      ARM: dt: Add ARM PMU to tegra*.dtsi
      ARM: dt: Explicitly configure all serial ports on Tegra Cardhu
      ARM: tegra: update defconfig
      MAINTAINERS: ARM: tegra: update Stephen's email address

Sylwester Nawrocki (4):
      ARM: EXYNOS: Increase virtual framebuffer size on Universal C210 board
      ARM: EXYNOS: Add support for S5K6AAFX image sensor on Universal C210 board
      ARM: SAMSUNG: Add support for S5K6AAFX camera on Nuri board
      ARM: SAMSUNG: Correct MIPI-CSIS io memory resource definition

Tarun Kanti DebBarma (1):
      ARM: OMAP: dmtimer: fix missing content/correction in low-power mode support

Thierry Reding (1):
      ARM: tegra: PCIe: Provide 3.3V supply voltage

Tony Lindgren (42):
      Merge branch 'omap1-part2' into omap1
      Merge branch 'soc-part2' into soc
      Merge branch 'for_3.4/dt_base' of git://git.kernel.org/.../bcousson/linux-omap-dt into dt
      ARM: OMAP2+: Split omap2_hsmmc_init() to properly support I2C GPIO pins
      ARM: OMAP2+: Set Kconfig dependencies for PROC_DEVICETREE
      ARM: OMAP2+: Fix Kconfig dependencies for USB_ARCH_HAS_EHCI
      ARM: OMAP2+: Fix OMAP_HDQ_BASE build error
      ARM: OMAP2+: Fix board_mux section type conflict when OMAP_MUX is not set
      ARM: OMAP2+: Fix zoom LCD backlight if TWL_CORE is not selected
      ARM: OMAP: Fix devexit for dma when CONFIG_HOTPLUG is not set
      ARM: OMAP2+: Fix multiple randconfig errors with SOC_OMAP and SOC_OMAP_NOOP
      ARM: OMAP2+: Fix devexit for smartreflex when CONFIG_HOTPLUG is not set
      ARM: OMAP2+: Drop DISPC L3 firewall code
      ARM: OMAP2+: Move SDRC related functions from io.h into local common.h
      ARM: OMAP: Move omap_init_consistent_dma_size() to local common.h
      ARM: OMAP1: Move 16xx GPIO system clock to platform init code
      ARM: OMAP1: Move most of plat/io.h into local iomap.h
      ARM: OMAP2+: Move most of plat/io.h into local iomap.h
      ARM: OMAP: Remove plat/io.h by splitting it into mach/io.h and mach/hardware.h
      ARM: OMAP2+: Limit omap_read/write usage to legacy USB drivers
      ARM: OMAP2+: Mark omap_hsmmc_init and omap_mux related functions as __init
      Merge branch 'for_3.4/dts_updates' of git://git.kernel.org/.../bcousson/linux-omap-dt into dt
      Merge branch 'iomap' into cleanup
      Merge branch 'randconfig' into fixes-non-critical
      Merge branch 'hsmmc' into fixes-non-critical
      ARM: OMAP2+: Fix L4_EMU_34XX_BASE error after iomap changes
      Merge branch 'for_3.4/dt_irq_domain' of git://git.kernel.org/.../bcousson/linux-omap-dt into dt-part2
      Merge branch 'omap1' into ams-delta
      ARM: OMAP2+: Fix build error when only ARCH_OMAP2/3 or 4 is selected
      ARM: OMAP2+: Remove extra ifdefs for board-generic
      Merge branch 'for_3.4/cleanup/sr' of git://git.kernel.org/.../khilman/linux-omap-pm into sr
      Revert "ARM: OMAP2+: Fix multiple randconfig errors with SOC_OMAP and SOC_OMAP_NOOP"
      ARM: OMAP1: Fix section mismatch for omap1_init_early()
      ARM: OMAP2+: Fix omap24xx_io_desc warning if SoC subtypes are not selected
      ARM: OMAP2: Fix section warning for n8x0 when CONFIG_MMC_OMAP is not set
      Merge branch 'for_3.4/cleanup/pm' of git://git.kernel.org/.../khilman/linux-omap-pm into cleanup-pm
      Merge branch 'for_3.4/cleanup/uart' of git://git.kernel.org/.../khilman/linux-omap-pm into uart
      ARM: OMAP: Remove remaining includes for mach/io.h
      ARM: OMAP2+: Fix build error after merge
      ARM: OMAP2+: Fix build issues with missing include of linux/bug.h
      ARM: OMAP2+: Fix section warnings for hsmmc_init_one
      ARM: OMAP2+: Fix build for omap4 only builds with missing include of linux/bug.h

Tushar Behera (7):
      ARM: SAMSUNG: Add __init attribute to samsung_bl_set()
      ARM: SAMSUNG: fix __init attribute on regarding s3c_set_platdata()
      ARM: EXYNOS: Add __init attribute to nuri_camera_init()
      ARM: EXYNOS: Add __init attribute to universal_camera_init()
      ARM: EXYNOS: Add apb_pclk clkdev entry for mdma1
      ARM: EXYNOS: Add clkdev lookup entry for lcd clock
      ARM: EXYNOS: Fix compilation error with mach-exynos4-dt board

Uwe Kleine-K?nig (3):
      ARM: OMAP4: board-4430sdp: don't initialize value that is never used
      ARM: davinci: cpufreq: fix compiler warning
      ARM: davinci: DA850: move da850_register_pm to .init.text

Vaibhav Bedia (1):
      ARM: OMAP: sram: Add am33xx SRAM support (minimal)

Vaibhav Hiremath (3):
      ARM: OMAP2+: Make cpu_rev static global variable
      ARM: OMAP2+: split omap2/3/4_check_revision function
      arm/dts: Add support for TI OMAP3 EVM board

Vladimir Zapolskiy (1):
      ARM: OMAP3: RX-51: add explicit mux configuration of tsc2005 control gpios

Wolfram Sang (4):
      ARM: mx28: check for gated clocks when setting saif divider
      ARM: mxs: read correct values when setting up MAC
      arm: lpc32xx: phy3250: add rtc & touch device
      arm: lpc32xx: phy3250: add rtc & touch device

Yuan Jiangli (1):
      ARM: OMAP3+: PM: VP: fix integer truncation error

wu guoxing (1):
      ARM : mx35: 3ds-board: add framebuffer device



From stigge at antcom.de  Sat Mar 24 19:48:43 2012
From: stigge at antcom.de (Roland Stigge)
Date: Sun, 25 Mar 2012 00:48:43 +0100
Subject: uImage with integrated dtb file
Message-ID: <4F6E5D5B.8050306@antcom.de>

Hi,

since I will need to maintain some machines with DT enabled kernels but 
containing a U-Boot without DT support, I sometimes need to integrate a 
dtb file into uImage.

I'm sure others have got the same issue. But searching for a while I 
only got older/meanwhile neglected approaches like:

git://kernel.ubuntu.com/jk/dt/linux-2.6.git - branch: dtbimage

I'm currently using a simple hack like attached below.

Wondering what others are doing.

Sorry if this topic has already been discussed.

Roland


--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -70,9 +70,11 @@ $(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
 clean-files := *.dtb
 
 quiet_cmd_uimage = UIMAGE  $@
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
+      cmd_uimage = cat $< arch/arm/boot/*.dtb > $<.tmp ; \
+                  $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
                   -C none -a $(LOADADDR) -e $(STARTADDR) \
-                  -n 'Linux-$(KERNELRELEASE)' -d $< $@
+                  -n 'Linux-$(KERNELRELEASE)' -d $<.tmp $@ ; \
+                  rm -f $<.tmp
 
 ifeq ($(CONFIG_ZBOOT_ROM),y)
 $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)


From jm at lentin.co.uk  Sat Mar 24 20:17:24 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sun, 25 Mar 2012 00:17:24 +0000 (GMT)
Subject: [PATCH V3 2/3] ARM: kirkwood: Convert orion-nand to fdt
In-Reply-To: <201203241901.00405.arnd@arndb.de>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <1332594876-8673-3-git-send-email-jm@lentin.co.uk>
 <201203241901.00405.arnd@arndb.de>
Message-ID: <alpine.DEB.2.02.1203250012060.8994@gonzo>

Convert orion-nand to use fdt and add common setup to kirkwood.dtsi, including
a default value for chip-delay (all current boards seem to use 25 anyway).

Add placeholder documentation for the bindings, for someone more knowledgable
than me to fill in the details of the properties.

Move common partition table documentation into a separate file and reference
this.

Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
Re-arranged documentation as you suggest, however it's tempting to have 
this as a separate patch and add references to partition.txt for the other 
binding documentation files. Let me know if you want me to do this.

Cheers for your help!

  .../devicetree/bindings/mtd/mtd-physmap.txt        |   24 +--------
  .../devicetree/bindings/mtd/orion-nand.txt         |   50 ++++++++++++++++++++
  .../devicetree/bindings/mtd/partition.txt          |   38 +++++++++++++++
  arch/arm/boot/dts/kirkwood.dtsi                    |   15 ++++++-
  arch/arm/mach-kirkwood/common.c                    |   12 +++++
  drivers/mtd/nand/orion_nand.c                      |   34 +++++++++++++-
  6 files changed, 149 insertions(+), 24 deletions(-)
  create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt
  create mode 100644 Documentation/devicetree/bindings/mtd/partition.txt

diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
index 80152cb..9b873d4 100644
--- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
@@ -23,27 +23,9 @@ are defined:
   - vendor-id : Contains the flash chip's vendor id (1 byte).
   - device-id : Contains the flash chip's device id (1 byte).

-In addition to the information on the mtd bank itself, the
-device tree may optionally contain additional information
-describing partitions of the address space.  This can be
-used on platforms which have strong conventions about which
-portions of a flash are used for what purposes, but which don't
-use an on-flash partition table such as RedBoot.
-
-Each partition is represented as a sub-node of the mtd device.
-Each node's name represents the name of the corresponding
-partition of the mtd device.
-
-Flash partitions
- - reg : The partition's offset and size within the mtd bank.
- - label : (optional) The label / name for this partition.
-   If omitted, the label is taken from the node name (excluding
-   the unit address).
- - read-only : (optional) This parameter, if present, is a hint to
-   Linux that this partition should only be mounted
-   read-only.  This is usually used for flash partitions
-   containing early-boot firmware images or data which should not
-   be clobbered.
+In addition to the information on the mtd bank itself, the device tree may
+optionally contain additional sub-nodes describing partitions of the address
+space. See partition.txt for more detail.

  Example:

diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
new file mode 100644
index 0000000..e9acbd2
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/orion-nand.txt
@@ -0,0 +1,50 @@
+NAND support for Marvell Orion SoC platforms
+
+Required properties:
+- compatible : "mrvl,orion-nand".
+- reg : Base physical address of the NAND and length of memory mapped
+	region
+
+Optional properties:
+- cle :
+- ale :
+- bank-width :
+- chip-delay :
+
+In addition to the information on the mtd bank itself, the device tree may
+optionally contain additional sub-nodes describing partitions of the address
+space. See partition.txt for more detail.
+
+Examples:
+
+nand at f4000000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cle = <0>;
+	ale = <1>;
+	bank-width = <8>;
+	chip-delay = <25>;
+	compatible = "mrvl,orion-nand";
+	reg = <0xf4000000 0x400>;
+
+	partition at 0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+		read-only;
+	};
+
+	partition at 100000 {
+		label = "uImage";
+		reg = <0x0100000 0x200000>;
+	};
+
+	partition at 300000 {
+		label = "dtb";
+		reg = <0x0300000 0x100000>;
+	};
+
+	partition at 400000 {
+		label = "root";
+		reg = <0x0400000 0x7d00000>;
+	};
+};
diff --git a/Documentation/devicetree/bindings/mtd/partition.txt b/Documentation/devicetree/bindings/mtd/partition.txt
new file mode 100644
index 0000000..f114ce1
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/partition.txt
@@ -0,0 +1,38 @@
+Representing flash partitions in devicetree
+
+Partitions can be represented by sub-nodes of an mtd device. This can be used
+on platforms which have strong conventions about which portions of a flash are
+used for what purposes, but which don't use an on-flash partition table such
+as RedBoot.
+
+#address-cells & #size-cells must both be present in the mtd device and be
+equal to 1.
+
+Required properties:
+- reg : The partition's offset and size within the mtd bank.
+
+Optional properties:
+- label : The label / name for this partition.  If omitted, the label is taken
+  from the node name (excluding the unit address).
+- read-only : This parameter, if present, is a hint to Linux that this
+  partition should only be mounted read-only. This is usually used for flash
+  partitions containing early-boot firmware images or data which should not be
+  clobbered.
+
+Examples:
+
+
+flash at 0 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition at 0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+		read-only;
+	};
+
+	uimage at 100000 {
+		reg = <0x0100000 0x200000>;
+	};
+];
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 3474ef8..6b80374 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -5,7 +5,7 @@

  	ocp at f1000000 {
  		compatible = "simple-bus";
-		ranges = <0 0xf1000000 0x1000000>;
+		ranges = <0 0xf1000000 0x4000000>;
  		#address-cells = <1>;
  		#size-cells = <1>;

@@ -32,5 +32,18 @@
  			reg = <0x10300 0x20>;
  			interrupts = <53>;
  		};
+
+		nand at 3000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cle = <0>;
+			ale = <1>;
+			bank-width = <8>;
+			compatible = "mrvl,orion-nand";
+			reg = <0x3000000 0x400>;
+			chip-delay = <25>;
+			/* set partition map and/or chip-delay in board dts */
+			status = "disabled";
+		};
  	};
  };
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index a02cae8..3ad0373 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -15,6 +15,7 @@
  #include <linux/ata_platform.h>
  #include <linux/mtd/nand.h>
  #include <linux/dma-mapping.h>
+#include <linux/of.h>
  #include <net/dsa.h>
  #include <asm/page.h>
  #include <asm/timex.h>
@@ -482,6 +483,9 @@ static int __init kirkwood_clock_gate(void)
  	unsigned int curr = readl(CLOCK_GATING_CTRL);
  	u32 dev, rev;

+#ifdef CONFIG_OF
+	struct device_node *np;
+#endif
  	kirkwood_pcie_id(&dev, &rev);
  	printk(KERN_DEBUG "Gating clock of unused units\n");
  	printk(KERN_DEBUG "before: 0x%08x\n", curr);
@@ -489,6 +493,14 @@ static int __init kirkwood_clock_gate(void)
  	/* Make sure those units are accessible */
  	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);

+#ifdef CONFIG_OF
+	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-nand");
+	if (np && of_device_is_available(np)) {
+		kirkwood_clk_ctrl |= CGC_RUNIT;
+		of_node_put(np);
+	}
+#endif
+
  	/* For SATA: first shutdown the phy */
  	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
  		/* Disable PLL and IVREF */
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index 29f505a..6a5f47b 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -13,6 +13,7 @@
  #include <linux/slab.h>
  #include <linux/module.h>
  #include <linux/platform_device.h>
+#include <linux/of.h>
  #include <linux/mtd/mtd.h>
  #include <linux/mtd/nand.h>
  #include <linux/mtd/partitions.h>
@@ -74,11 +75,13 @@ static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  static int __init orion_nand_probe(struct platform_device *pdev)
  {
  	struct mtd_info *mtd;
+	struct mtd_part_parser_data ppdata = {};
  	struct nand_chip *nc;
  	struct orion_nand_data *board;
  	struct resource *res;
  	void __iomem *io_base;
  	int ret = 0;
+	u32 val = 0;

  	nc = kzalloc(sizeof(struct nand_chip) + sizeof(struct mtd_info), GFP_KERNEL);
  	if (!nc) {
@@ -101,7 +104,25 @@ static int __init orion_nand_probe(struct platform_device *pdev)
  		goto no_res;
  	}

-	board = pdev->dev.platform_data;
+	if (pdev->dev.of_node) {
+		board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data),
+					GFP_KERNEL);
+		if (!board) {
+			printk(KERN_ERR "orion_nand: failed to allocate board structure.\n");
+			ret = -ENOMEM;
+			goto no_res;
+		}
+		if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
+			board->cle = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
+			board->ale = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node, "bank-width", &val))
+			board->width = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node,
+						"chip-delay", &val))
+			board->chip_delay = (u8)val;
+	} else
+		board = pdev->dev.platform_data;

  	mtd->priv = nc;
  	mtd->owner = THIS_MODULE;
@@ -129,7 +150,8 @@ static int __init orion_nand_probe(struct platform_device *pdev)
  	}

  	mtd->name = "orion_nand";
-	ret = mtd_device_parse_register(mtd, NULL, 0,
+	ppdata.of_node = pdev->dev.of_node;
+	ret = mtd_device_parse_register(mtd, NULL, &ppdata,
  			board->parts, board->nr_parts);
  	if (ret) {
  		nand_release(mtd);
@@ -161,11 +183,19 @@ static int __devexit orion_nand_remove(struct platform_device *pdev)
  	return 0;
  }

+#ifdef CONFIG_OF
+static struct of_device_id orion_nand_of_match_table[] = {
+	{ .compatible = "mrvl,orion-nand", },
+	{},
+};
+#endif
+
  static struct platform_driver orion_nand_driver = {
  	.remove		= __devexit_p(orion_nand_remove),
  	.driver		= {
  		.name	= "orion_nand",
  		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(orion_nand_of_match_table),
  	},
  };

-- 
1.7.9.1


From grant.likely at secretlab.ca  Sat Mar 24 15:10:06 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sat, 24 Mar 2012 19:10:06 +0000
Subject: [PATCH 4/4] arm: at91: dt: sam9g25ek add mci support
In-Reply-To: <4F6B3CCD.7070105@atmel.com>
References: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
 <1332352994-20983-5-git-send-email-ludovic.desroches@atmel.com>
 <4F6B3CCD.7070105@atmel.com>
Message-ID: <20120324191006.8FC3A3E0AD0@localhost>

On Thu, 22 Mar 2012 15:53:01 +0100, Nicolas Ferre <nicolas.ferre at atmel.com> wrote:
> On 03/21/2012 07:03 PM, ludovic.desroches at atmel.com :
> > From: Ludovic Desroches <ludovic.desroches at atmel.com>
> > 
> > Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

I think you really mean "Acked-by".  It is only appropriate to add a
"Signed-off-by" tag when you have actually picked up and either
committed or reposted a patch.  When replying to a patch on the
mailing list and giving your okay, the correct tag is either
"Acked-by" or "Reviewed-by"  (The difference being that "Acked-by"
infers that you have some authority over the areas touched by the
patch).

See Documentation/SubmittingPatches

g.

> 
> > ---
> >  arch/arm/boot/dts/at91sam9g25ek.dts |   16 ++++++++++++++++
> >  1 files changed, 16 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
> > index 7a13d09..960de2b 100644
> > --- a/arch/arm/boot/dts/at91sam9g25ek.dts
> > +++ b/arch/arm/boot/dts/at91sam9g25ek.dts
> > @@ -32,6 +32,22 @@
> >  				phy-mode = "rmii";
> >  				status = "okay";
> >  			};
> > +
> > +			mmc0: mmc at f0008000 {
> > +				status = "okay";
> > +				slot at 0 {
> > +					bus-width = <4>;
> > +					cd-gpios = <&pioD 15 0>;
> > +				};
> > +			};
> > +
> > +			mmc1: mmc at f000c000 {
> > +				status = "okay";
> > +				slot at 0 {
> > +					bus-width = <4>;
> > +					cd-gpios = <&pioD 14 0>;
> > +				};
> > +			};
> >  		};
> >  
> >  		usb0: ohci at 00600000 {
> 
> 
> -- 
> Nicolas Ferre
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From grant.likely at secretlab.ca  Sat Mar 24 15:32:00 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sat, 24 Mar 2012 19:32:00 +0000
Subject: Handling device shared SFR on dt platform
In-Reply-To: <4F6A5853.9090809@gmail.com>
References: <4F6A5853.9090809@gmail.com>
Message-ID: <20120324193200.822AD3E0B06@localhost>

On Wed, 21 Mar 2012 23:38:11 +0100, Sylwester Nawrocki <snjw23 at gmail.com> wrote:
> 
> Hello,
> 
> I'm working on adding the device tree support for two devices that
> share some IO registers. Exactly, there is one shared SFR that 
> contains a common bit to enable two PHY devices, and another two
> bits, each to separately reset each PHY.
> 
> Currently this shared register is statically memory mapped and it is
> handled by a platform specific callback, that both drivers use to
> control their corresponding (sub)devices in synchronised manner.
> 
> The two devices are a MIPI-CSI2 receiver and a MIPI-DSI transmitter, 
> and the common register is there to control the camera and the display 
> port PHY. The hardware design is a bit unfortunate, but there is not
> much I could do about it.

Generally, this is handled by having a third node for the shared
register block and both device nodes holding a phandle to it.

No, there isn't any common infrastructure for implementing this, but
it isn't very much code.

g.


From grant.likely at secretlab.ca  Sat Mar 24 15:01:19 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sat, 24 Mar 2012 19:01:19 +0000
Subject: [PATCH v2 1/1] ARM: imx28: add basic dt support
In-Reply-To: <201203231543.54588.marek.vasut@gmail.com>
References: <1332513070-5400-1-git-send-email-b29396@freescale.com>
 <201203231543.54588.marek.vasut@gmail.com>
Message-ID: <20120324190119.B5E643E0ACD@localhost>

On Fri, 23 Mar 2012 15:43:54 +0100, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dear Dong Aisheng,
> 
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> > 
> > This patch includes basic dt support which can boot via nfs rootfs.
> > 
> > Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> > ---
> > ChangeLog v1->v2:
> >  * Some fixes addressed Rob's review comments.
> >    Remove using of OF_DEV_AUXDATA.
> >  * Remove mac address from dts file
> >    Currently we use the mac address got from uboot to work.
> >    Will submit a p separate atch using prom_update_property to fix this
> >    issue for driver based on suggestions from Grant and Lothar.
> >  * rename mxs-dt.c to mach-mxs.c which is supposed to support mx23 dt
> >    too in the future.
> >  * add compatible string "fsl,imx28" per Sascha's suggestion
> >  * add more devices in dtsi file
> >    For those devices still not in use, set the state to "disabled"
> >    by default.
> > 
> > For other patches i sent with this in the first series like mmc and sdma
> > dt support, i will send out them separately since this patch does not
> > depend on them and does not block you to run dt via nfs rootfs.
> > ---
> >  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
> >  arch/arm/boot/dts/imx28-evk.dts               |   35 +++
> 
> Isn't this supposed to be "mx28evk.dts"?
> 
> >  arch/arm/boot/dts/imx28.dtsi                  |  358
> > +++++++++++++++++++++++++ arch/arm/mach-mxs/Kconfig                     | 
> >   8 +
> >  arch/arm/mach-mxs/Makefile                    |    1 +
> >  arch/arm/mach-mxs/clock-mx28.c                |    4 +
> >  arch/arm/mach-mxs/mach-mxs.c                  |   69 +++++
> >  7 files changed, 479 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/boot/dts/imx28-evk.dts
> >  create mode 100644 arch/arm/boot/dts/imx28.dtsi
> >  create mode 100644 arch/arm/mach-mxs/mach-mxs.c
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
> > b/Documentation/devicetree/bindings/arm/fsl.txt index 54bddda..9f21faf
> > 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.txt
> > +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> > @@ -1,6 +1,10 @@
> >  Freescale i.MX Platforms Device Tree Bindings
> >  -----------------------------------------------
> > 
> > +i.MX28 Evaluation Kit
> > +Required root node properties:
> > +    - compatible = "fsl,imx28-evk", "fsl,imx28";
> > +
> >  i.MX51 Babbage Board
> >  Required root node properties:
> >      - compatible = "fsl,imx51-babbage", "fsl,imx51";
> > diff --git a/arch/arm/boot/dts/imx28-evk.dts
> > b/arch/arm/boot/dts/imx28-evk.dts new file mode 100644
> > index 0000000..5402495
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx28-evk.dts
> > @@ -0,0 +1,35 @@
> > +/*
> > + * Copyright 2012 Freescale Semiconductor, Inc.
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/dts-v1/;
> > +/include/ "imx28.dtsi"
> > +
> > +/ {
> > +	model = "Freescale i.MX28 Evaluation Kit";
> > +	compatible = "fsl,imx28-evk", "fsl,imx28";
> > +
> > +	memory {
> > +		device_type = "memory";
> > +		reg = <0x40000000 0x08000000>;
> > +	};
> > +
> > +	ahb at 80080000 {
> > +		ethernet at 800f0000 {
> 
> fec at ... would be more readable, but I think this was decided before to be like 
> this?

ethernet at ... is the correct naming.

> 
> > +			phy-mode = "rmii";
> > +			status = "okay";
> > +		};
> > +
> 
> [...]
> 
> > diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
> > index 908bf9a..8328c45 100644
> > --- a/arch/arm/mach-mxs/Makefile
> > +++ b/arch/arm/mach-mxs/Makefile
> > @@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
> >  obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
> >  obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
> > 
> > +obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
> >  obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
> >  obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
> >  obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
> > diff --git a/arch/arm/mach-mxs/clock-mx28.c
> > b/arch/arm/mach-mxs/clock-mx28.c index 5d68e41..88ed30c 100644
> > --- a/arch/arm/mach-mxs/clock-mx28.c
> > +++ b/arch/arm/mach-mxs/clock-mx28.c
> > @@ -671,6 +671,10 @@ static struct clk_lookup lookups[] = {
> >  	_REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
> >  	_REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
> >  	_REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
> > +	/* for DT */
> > +	_REGISTER_CLOCK("80074000.serial", NULL, uart_clk)
> > +	_REGISTER_CLOCK("800f0000.ethernet", NULL, fec_clk)
> > +	_REGISTER_CLOCK("800f4000.ethernet", NULL, fec_clk)
> 
> Wasn't the DT stuff supposed to be more symbolic? Aka. this seems weird.

Indeed.  It is a symptom of the common clock and DT clock bindings not
being merged yet.  Expect this to be able to be removed in a couple of
kernel releases.

g.



From consul.kautuk at gmail.com  Sun Mar 25 00:07:53 2012
From: consul.kautuk at gmail.com (Kautuk Consul)
Date: Sun, 25 Mar 2012 00:07:53 -0400
Subject: [PATCH 1/1] arm: fault.c: correct how the tsk->[maj|min]_flt gets
 incremented
In-Reply-To: <1332261057-2399-1-git-send-email-consul.kautuk@gmail.com>
References: <1332261057-2399-1-git-send-email-consul.kautuk@gmail.com>
Message-ID: <CAFPAmTRiYm-kauXjJAek=VWB=6TEhNo0M6-F7VA4YV8snqiP4w@mail.gmail.com>

Hi,

did anyone get an opportunity to review this change ?


On Tue, Mar 20, 2012 at 12:30 PM, Kautuk Consul <consul.kautuk at gmail.com> wrote:
> commit 8878a539ff19a43cf3729e7562cd528f490246ae was done by me
> to make the page fault handler retryable as well as interruptible.
>
> Due to this commit, there is a mistake in the way in which
> tsk->[maj|min]_flt counter gets incremented for VM_FAULT_ERROR:
> If VM_FAULT_ERROR is returned in the fault flags by handle_mm_fault,
> then either maj_flt or min_flt will get incremented. This is wrong
> as in the case of a VM_FAULT_ERROR we need to be skip ahead to the
> error handling code in do_page_fault.
>
> Added a check after the call to __do_page_fault() to check for
> (fault & VM_FAULT_ERROR).
>
> Signed-off-by: Kautuk Consul <consul.kautuk at gmail.com>
> ---
> ?arch/arm/mm/fault.c | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> index bb7eac3..ec8c88b 100644
> --- a/arch/arm/mm/fault.c
> +++ b/arch/arm/mm/fault.c
> @@ -318,7 +318,7 @@ retry:
> ? ? ? ? */
>
> ? ? ? ?perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
> - ? ? ? if (flags & FAULT_FLAG_ALLOW_RETRY) {
> + ? ? ? if (!(fault & VM_FAULT_ERROR) && (flags & FAULT_FLAG_ALLOW_RETRY)) {
> ? ? ? ? ? ? ? ?if (fault & VM_FAULT_MAJOR) {
> ? ? ? ? ? ? ? ? ? ? ? ?tsk->maj_flt++;
> ? ? ? ? ? ? ? ? ? ? ? ?perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
> --
> 1.7.5.4
>


From dirk.behme at googlemail.com  Sun Mar 25 02:21:17 2012
From: dirk.behme at googlemail.com (Dirk Behme)
Date: Sun, 25 Mar 2012 08:21:17 +0200
Subject: uImage with integrated dtb file
In-Reply-To: <4F6E5D5B.8050306@antcom.de>
References: <4F6E5D5B.8050306@antcom.de>
Message-ID: <4F6EB95D.7040601@googlemail.com>

On 25.03.2012 00:48, Roland Stigge wrote:
> Hi,
>
> since I will need to maintain some machines with DT enabled kernels but
> containing a U-Boot without DT support, I sometimes need to integrate a
> dtb file into uImage.
>
> I'm sure others have got the same issue. But searching for a while I
> only got older/meanwhile neglected approaches like:
>
> git://kernel.ubuntu.com/jk/dt/linux-2.6.git - branch: dtbimage

Would have been nice if you would have provided a http link ;)

> I'm currently using a simple hack like attached below.
>
> Wondering what others are doing.

In the past I saw people using something like

http://lists.infradead.org/pipermail/linux-arm-kernel/2011-September/064353.html

I'm not sure if the is the most recent version, though.

Best regards

Dirk

> Sorry if this topic has already been discussed.
>
> Roland
>
>
> --- a/arch/arm/boot/Makefile
> +++ b/arch/arm/boot/Makefile
> @@ -70,9 +70,11 @@ $(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
>   clean-files := *.dtb
>
>   quiet_cmd_uimage = UIMAGE  $@
> -      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
> +      cmd_uimage = cat $<  arch/arm/boot/*.dtb>  $<.tmp ; \
> +                  $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
>                     -C none -a $(LOADADDR) -e $(STARTADDR) \
> -                  -n 'Linux-$(KERNELRELEASE)' -d $<  $@
> +                  -n 'Linux-$(KERNELRELEASE)' -d $<.tmp $@ ; \
> +                  rm -f $<.tmp
>
>   ifeq ($(CONFIG_ZBOOT_ROM),y)
>   $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



From viresh.linux at gmail.com  Sun Mar 25 03:31:32 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Sun, 25 Mar 2012 13:01:32 +0530
Subject: [PATCH 1/2] ARM: VIC: Create common infrastructure for vic DT
 bindings
In-Reply-To: <4F6C6F32.10800@gmail.com>
References: <4bfe7af3761f6f40506a2089fd67866015f6d7f3.1332488625.git.viresh.kumar@st.com>
 <4F6C6F32.10800@gmail.com>
Message-ID: <CAOh2x=n-sZ6jV1M9XY9cOp7_8EeRfvqkjL5y3AakgpYymFRHkg@mail.gmail.com>

On Fri, Mar 23, 2012 at 6:10 PM, Rob Herring <robherring2 at gmail.com> wrote:
> NAK
>
> None of these platforms have gpio interrupts or any other board
> interrupt controllers which need to be initialized early?

Atleast SPEAr600 have GPIO interrupts.

> I don't think DT conversions are complete enough to tell.

Couldn't get your comment, sorry.

> We could do something like this, but there only needs to be a single
> match list of all controllers and function. We should consolidate the
> irqchips to drivers/irqchip first though. I have that action from Connect...

That would be good.
I am updating DT support for SPEAr3xx, where i need to use VIC OF
support. So i would still like to get this patch going and you can consilidate
code at irqchips level later. What do you say?

--
viresh


From linux at arm.linux.org.uk  Sun Mar 25 03:47:44 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 25 Mar 2012 08:47:44 +0100
Subject: [PATCH v2] ARM: pxa: use common IOMEM definition
In-Reply-To: <1332423761-27205-1-git-send-email-robherring2@gmail.com>
References: <1332296149-28110-2-git-send-email-robherring2@gmail.com>
 <1332423761-27205-1-git-send-email-robherring2@gmail.com>
Message-ID: <20120325074744.GB5611@n2100.arm.linux.org.uk>

What's happening about this and your other patch for PXA?  PXA is
currently broken in arm-soc, and has been for the past week.  See
http://www.arm.linux.org.uk/developer/build/

On Thu, Mar 22, 2012 at 08:42:41AM -0500, Rob Herring wrote:
> From: Rob Herring <rob.herring at calxeda.com>
> 
> pxa was missed in the moving of IOMEM to a common definition, so lots of
> IOMEM redefined warnings were introduced. So remove pxa IOMEM definition
> and fix all the fallout.
> 
> Reported-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> Signed-off-by: Rob Herring <rob.herring at calxeda.com>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Haojian Zhuang <haojian.zhuang at marvell.com>
> Cc: Alessandro Zummo <a.zummo at towertech.it>
> Cc: Jaroslav Kysela <perex at perex.cz>
> Cc: Takashi Iwai <tiwai at suse.de>
> Cc: rtc-linux at googlegroups.com
> Cc: alsa-devel at alsa-project.org
> ---
> v2:
> - fix my commit msg typos
> - add fix for sa1100_wdt.c
> 
> I plan to send this fix thru the arm-soc tree.
> 
> Rob
> 
>  arch/arm/mach-pxa/clock-pxa2xx.c          |    1 +
>  arch/arm/mach-pxa/corgi_pm.c              |    1 +
>  arch/arm/mach-pxa/cpufreq-pxa3xx.c        |    1 +
>  arch/arm/mach-pxa/include/mach/hardware.h |    2 --
>  arch/arm/mach-pxa/mfp-pxa2xx.c            |    1 +
>  arch/arm/mach-pxa/pxa2xx.c                |    1 +
>  arch/arm/mach-pxa/pxa300.c                |    1 +
>  arch/arm/mach-pxa/pxa320.c                |    1 +
>  arch/arm/mach-pxa/sharpsl_pm.c            |    1 +
>  drivers/rtc/rtc-sa1100.c                  |    1 +
>  drivers/watchdog/sa1100_wdt.c             |    1 +
>  sound/arm/pxa2xx-ac97-lib.c               |    1 +
>  sound/arm/pxa2xx-ac97.c                   |    1 +
>  sound/soc/pxa/pxa2xx-ac97.c               |    1 +
>  14 files changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-pxa/clock-pxa2xx.c b/arch/arm/mach-pxa/clock-pxa2xx.c
> index 1d5859d..9ee2ad6 100644
> --- a/arch/arm/mach-pxa/clock-pxa2xx.c
> +++ b/arch/arm/mach-pxa/clock-pxa2xx.c
> @@ -9,6 +9,7 @@
>  #include <linux/module.h>
>  #include <linux/kernel.h>
>  #include <linux/init.h>
> +#include <linux/io.h>
>  #include <linux/syscore_ops.h>
>  
>  #include <mach/pxa2xx-regs.h>
> diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
> index 39e265c..048c429 100644
> --- a/arch/arm/mach-pxa/corgi_pm.c
> +++ b/arch/arm/mach-pxa/corgi_pm.c
> @@ -19,6 +19,7 @@
>  #include <linux/interrupt.h>
>  #include <linux/platform_device.h>
>  #include <linux/apm-emulation.h>
> +#include <linux/io.h>
>  
>  #include <asm/irq.h>
>  #include <asm/mach-types.h>
> diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
> index 88fbec0..b85b4ab 100644
> --- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
> +++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
> @@ -15,6 +15,7 @@
>  #include <linux/init.h>
>  #include <linux/cpufreq.h>
>  #include <linux/slab.h>
> +#include <linux/io.h>
>  
>  #include <mach/pxa3xx-regs.h>
>  
> diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
> index 54b64ea..56d92e5 100644
> --- a/arch/arm/mach-pxa/include/mach/hardware.h
> +++ b/arch/arm/mach-pxa/include/mach/hardware.h
> @@ -40,7 +40,6 @@
>  #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
>  
>  #ifndef __ASSEMBLY__
> -# define IOMEM(x) ((void __iomem *)(x))
>  # define __REG(x)	(*((volatile u32 __iomem *)io_p2v(x)))
>  
>  /* With indexed regs we don't want to feed the index through io_p2v()
> @@ -52,7 +51,6 @@
>  
>  #else
>  
> -# define IOMEM(x)	x 
>  # define __REG(x)	io_p2v(x)
>  # define __PREG(x)	io_v2p(x)
>  
> diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
> index f147755..b029562 100644
> --- a/arch/arm/mach-pxa/mfp-pxa2xx.c
> +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
> @@ -17,6 +17,7 @@
>  #include <linux/module.h>
>  #include <linux/kernel.h>
>  #include <linux/init.h>
> +#include <linux/io.h>
>  #include <linux/syscore_ops.h>
>  
>  #include <mach/pxa2xx-regs.h>
> diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c
> index 8682704..f8ec854 100644
> --- a/arch/arm/mach-pxa/pxa2xx.c
> +++ b/arch/arm/mach-pxa/pxa2xx.c
> @@ -13,6 +13,7 @@
>  #include <linux/module.h>
>  #include <linux/kernel.h>
>  #include <linux/device.h>
> +#include <linux/io.h>
>  
>  #include <mach/hardware.h>
>  #include <mach/pxa2xx-regs.h>
> diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
> index 40bb165..17cbc0c 100644
> --- a/arch/arm/mach-pxa/pxa300.c
> +++ b/arch/arm/mach-pxa/pxa300.c
> @@ -16,6 +16,7 @@
>  #include <linux/module.h>
>  #include <linux/kernel.h>
>  #include <linux/platform_device.h>
> +#include <linux/io.h>
>  
>  #include <mach/pxa300.h>
>  
> diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
> index 8d614ec..6dc99d4 100644
> --- a/arch/arm/mach-pxa/pxa320.c
> +++ b/arch/arm/mach-pxa/pxa320.c
> @@ -16,6 +16,7 @@
>  #include <linux/module.h>
>  #include <linux/kernel.h>
>  #include <linux/platform_device.h>
> +#include <linux/io.h>
>  
>  #include <mach/pxa320.h>
>  
> diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
> index 8d5168d..6d3b39f 100644
> --- a/arch/arm/mach-pxa/sharpsl_pm.c
> +++ b/arch/arm/mach-pxa/sharpsl_pm.c
> @@ -24,6 +24,7 @@
>  #include <linux/leds.h>
>  #include <linux/suspend.h>
>  #include <linux/gpio.h>
> +#include <linux/io.h>
>  
>  #include <asm/mach-types.h>
>  #include <mach/pm.h>
> diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
> index cb9a585..398ab7a 100644
> --- a/drivers/rtc/rtc-sa1100.c
> +++ b/drivers/rtc/rtc-sa1100.c
> @@ -30,6 +30,7 @@
>  #include <linux/string.h>
>  #include <linux/pm.h>
>  #include <linux/bitops.h>
> +#include <linux/io.h>
>  
>  #include <mach/hardware.h>
>  #include <asm/irq.h>
> diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c
> index 0162454..a3ff321 100644
> --- a/drivers/watchdog/sa1100_wdt.c
> +++ b/drivers/watchdog/sa1100_wdt.c
> @@ -25,6 +25,7 @@
>  #include <linux/miscdevice.h>
>  #include <linux/watchdog.h>
>  #include <linux/init.h>
> +#include <linux/io.h>
>  #include <linux/bitops.h>
>  #include <linux/uaccess.h>
>  #include <linux/timex.h>
> diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c
> index d1aa421..d760371 100644
> --- a/sound/arm/pxa2xx-ac97-lib.c
> +++ b/sound/arm/pxa2xx-ac97-lib.c
> @@ -17,6 +17,7 @@
>  #include <linux/clk.h>
>  #include <linux/delay.h>
>  #include <linux/module.h>
> +#include <linux/io.h>
>  
>  #include <sound/ac97_codec.h>
>  #include <sound/pxa2xx-lib.h>
> diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
> index 3a39626..afef72c 100644
> --- a/sound/arm/pxa2xx-ac97.c
> +++ b/sound/arm/pxa2xx-ac97.c
> @@ -11,6 +11,7 @@
>   */
>  
>  #include <linux/init.h>
> +#include <linux/io.h>
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
>  
> diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
> index 837ff34..b4bfd97 100644
> --- a/sound/soc/pxa/pxa2xx-ac97.c
> +++ b/sound/soc/pxa/pxa2xx-ac97.c
> @@ -11,6 +11,7 @@
>   */
>  
>  #include <linux/init.h>
> +#include <linux/io.h>
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
>  
> -- 
> 1.7.5.4
> 


From arnd at arndb.de  Sun Mar 25 03:52:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 25 Mar 2012 07:52:56 +0000
Subject: [PATCH V3 2/3] ARM: kirkwood: Convert orion-nand to fdt
In-Reply-To: <alpine.DEB.2.02.1203250012060.8994@gonzo>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <201203241901.00405.arnd@arndb.de> <alpine.DEB.2.02.1203250012060.8994@gonzo>
Message-ID: <201203250752.56733.arnd@arndb.de>

On Sunday 25 March 2012, Jamie Lentin wrote:
> Re-arranged documentation as you suggest, however it's tempting to have 
> this as a separate patch and add references to partition.txt for the other 
> binding documentation files. Let me know if you want me to do this.
> 

Sounds lika a good idea, yes. This version is also fine with me though,

Acked-by: Arnd Bergmann <arnd at arndb.de>


From mgherzan at gmail.com  Sun Mar 25 05:51:49 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Sun, 25 Mar 2012 11:51:49 +0200
Subject: [PATCH v8 RESEND] ARM: net: JIT compiler for packet filters
In-Reply-To: <20120319.172005.1889334604020296555.davem@davemloft.net>
References: <1331933316-10197-1-git-send-email-mgherzan@gmail.com>
 <20120319.172005.1889334604020296555.davem@davemloft.net>
Message-ID: <4F6EEAB5.7070009@gmail.com>

Am 19.03.2012 22:20, schrieb David Miller:
> I would like to see this merged however is feasible, this has been in
> a catatonic state for two releases and waiting longer isn't going to
> improve things enough to justify any further delay.

It has been merged into the ARM tree more than a week ago, but
unfortunately it seems it will not make it into 3.4.

Mircea


From linux at arm.linux.org.uk  Sun Mar 25 05:57:11 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 25 Mar 2012 10:57:11 +0100
Subject: [PATCH v8 RESEND] ARM: net: JIT compiler for packet filters
In-Reply-To: <4F6EEAB5.7070009@gmail.com>
References: <1331933316-10197-1-git-send-email-mgherzan@gmail.com>
 <20120319.172005.1889334604020296555.davem@davemloft.net>
 <4F6EEAB5.7070009@gmail.com>
Message-ID: <20120325095711.GC5611@n2100.arm.linux.org.uk>

On Sun, Mar 25, 2012 at 11:51:49AM +0200, Mircea Gherzan wrote:
> Am 19.03.2012 22:20, schrieb David Miller:
> > I would like to see this merged however is feasible, this has been in
> > a catatonic state for two releases and waiting longer isn't going to
> > improve things enough to justify any further delay.
> 
> It has been merged into the ARM tree more than a week ago, but
> unfortunately it seems it will not make it into 3.4.

Why do you say that?


From arnd at arndb.de  Sun Mar 25 06:21:58 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 25 Mar 2012 10:21:58 +0000
Subject: [GIT PULL 02/09] ARM: global cleanups
In-Reply-To: <1332626568-17812-3-git-send-email-arnd@arndb.de>
References: <1332626568-17812-1-git-send-email-arnd@arndb.de>
 <1332626568-17812-3-git-send-email-arnd@arndb.de>
Message-ID: <201203251021.59187.arnd@arndb.de>

On Saturday 24 March 2012, Arnd Bergmann wrote:
> Quite a bit of code gets removed, and some stuff moved around, mostly
> the old samsung s3c24xx stuff. There should be no functional changes in
> this series otherwise. Some cleanups have dependencies on other arm-soc
> branches and will be sent in the second round.
> 
> The at91cap9 platform is removed and no longer listed in
> Documentation/feature-removal-schedule.txt, which conflicts with two
> new entries in that file.
> 
> arch/arm/plat-mxc/audmux-v1.c was removed, so the changes to its comments
> are meaningless now.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>

Hi Linus,

I've just had to update this tag again, the top commit is now 24d2e18,
this fixes a regression pointed out by Russell, which was introduced
in the cleanup branch but fixed in another commit that you have already
pulled. I've merged that branch into mine to keep this (more) bisectible.

	Arnd


From linux at arm.linux.org.uk  Sun Mar 25 06:50:54 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 25 Mar 2012 11:50:54 +0100
Subject: [GIT PULL 0/9] arm-soc updates, first batch
In-Reply-To: <1332626568-17812-1-git-send-email-arnd@arndb.de>
References: <1332626568-17812-1-git-send-email-arnd@arndb.de>
Message-ID: <20120325105054.GD5611@n2100.arm.linux.org.uk>

On Sat, Mar 24, 2012 at 10:02:37PM +0000, Arnd Bergmann wrote:
> Rob Herring (29):
>       ARM: timer-sp: add sched_clock support
>       ARM: highbank: enable sp804 based sched_clock
>       ARM: highbank: remove unused memory.h
>       Merge remote-tracking branch 'arm-soc/at91/base2+cleanup' into cleanup-base
>       usb: ohci-pxa27x: add explicit include of hardware.h
>       ARM: provide runtime hook for ioremap/iounmap
>       ARM: imx: convert to common runtime ioremap hook
>       ARM: msm: use runtime ioremap hook
>       ARM: iop13xx: use runtime ioremap hook
>       ARM: ixp4xx: use runtime ioremap hook
>       ARM: ebsa110: use runtime ioremap hook
>       ARM: remove compile time __arch_ioremap/__arch_iounmap
>       ARM: iop13xx: move io.h externs to pci.h
>       ARM: msm: clean-up mach/io.h
>       [media] davinci: remove includes of mach/io.h
>       ARM: davinci: remove unneeded mach/io.h include
>       ARM: orion5x: clean-up mach/io.h
>       ARM: tegra: clean-up mach/io.h
>       ARM: ep93xx: clean-up mach/io.h
>       ARM: at91: add explicit include of hardware.h to uncompressor
>       ARM: dove: add explicit include of dove.h to addr-map.c
>       ARM: clps711x: remove unneeded include of mach/io.h
>       ARM: make mach/io.h include optional
>       ARM: remove bunch of now unused mach/io.h files
>       ARM: kill off __mem_pci
>       ARM: fix ioremap/iounmap for !CONFIG_MMU
>       ARM: iop13xx: fix missing declaration of iop13xx_init_early
>       ARM: create a common IOMEM definition
>       ARM: __io abuse cleanup

Arnd, I assume this shortlog is for the entire arm-soc queue rather than
this set of 9 pull requests?  If so fine.

If not, I couldn't find Rob's IO stuff in this set of 9 pulls - at the
moment because PXA currently fails to build because of that, and there's
a couple of patches on the list from Rob sent on the 20th to solve that.
However, Rob hasn't sent them to you yet.  I've already prodded over them
to try and find out what's happening.


From linux at arm.linux.org.uk  Sun Mar 25 07:20:35 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 25 Mar 2012 12:20:35 +0100
Subject: Inconsistent kallsyms data on ARM.
In-Reply-To: <201203141321.47010.arnd@arndb.de>
References: <CAP=VYLoStscdVJretZ-Rkbp7V3Vsm8N0oWcjih7ruHFiDN7CiA@mail.gmail.com>
 <201203141321.47010.arnd@arndb.de>
Message-ID: <20120325112035.GE5611@n2100.arm.linux.org.uk>

On Wed, Mar 14, 2012 at 01:21:46PM +0000, Arnd Bergmann wrote:
> On Tuesday 13 March 2012, Paul Gortmaker wrote:
> > This bug(?)  has been seen to float from one ARM build to another since
> > I started tracking the day-to-day changes in Stephen's linux-next builds.
> > 
> > I see it was discussed earlier:
> > 
> >    https://lkml.org/lkml/2011/8/2/233
> >    https://lkml.org/lkml/2011/10/8/70
> > 
> > but no concrete cause was nailed down.  Can the linux-next build results
> > help shed some light on this in any way?  Since it seems sporadic, is
> > there value in embedding a diagnostic of some sort in the infrastructure
> > so that when the error is detected, that it prints out more detailed info?
> > 
> > I can provide links to failed linux-next builds, but at the moment, all they
> > really seem to have is the same repeated error message, like this one:
> > 
> >    http://kisskb.ellerman.id.au/kisskb/buildresult/5869367/
> > 
> > and I don't see that helping folks all that much....
> > 
> 
> I'm sure I can reproduce it if necessary, but I need to know what to
> look for to find out what the problem is.

Right, last night's omap3430ldp build failed because of this, so I've
re-run the build and taken a look at what's happened:

$ arm-linux-nm -n .tmp_vmlinux1 > vm1.syms
$ arm-linux-nm -n .tmp_vmlinux2 > vm2.syms
$ arm-linux-nm -n vmlinux > vm3.syms
$ diff -u <(sed s,^...........,, vm2.syms) <(sed s,^...........,, vm3.syms) 
$

.tmp_vmlinux1 is the vmlinux file with no kallsyms data.  .tmp_vmlinux2 is
the vmlinux file with kallsyms data generated from the first image.
vmlinux is the vmlinux file with kallsyms data generated from the second
image.

What the above shows is that we have the same symbols in the same order
in the second and third stage.  However:

$ diff -u vm2.syms vm3.syms
...
 c0352900 R kallsyms_names
-c03acd00 R kallsyms_markers
-c03acf10 R kallsyms_token_table
-c03ad290 R kallsyms_token_index
...
+c03accf0 R kallsyms_markers
+c03acf00 R kallsyms_token_table
+c03ad280 R kallsyms_token_index

So, the size of the kallsyms names has changed.

Now, looking at the differences between stage 1 and stage 2:

@@ -1,9 +1,3 @@
-kallsyms_addresses
-kallsyms_markers
-kallsyms_names
-kallsyms_num_syms
-kallsyms_token_index
-kallsyms_token_table
 syscalls_padding
 cpu_v7_suspend_size
 NR_syscalls
@@ -17151,6 +17145,12 @@
 rpc_info_operations
 svc_pool_stats_seq_ops
 rpc_proc_fops
+kallsyms_addresses
+kallsyms_num_syms
+kallsyms_names
+kallsyms_markers
+kallsyms_token_table
+kallsyms_token_index
 __end_builtin_fw
 __end_pci_fixups_early
 __end_pci_fixups_enable
@@ -28372,11 +28372,11 @@
 __security_initcall_start
 __initramfs_size
 __irf_end
-__data_loc
 __init_end
 __per_cpu_end
 __per_cpu_load
 __per_cpu_start
+__data_loc
 _data
 _sdata
 init_thread_union


The difference in placement for the kallsyms symbols is more or less
expected, because these appear as weak symbols in stage 1.  However,
notice that __data_loc has moved in relative position.

As the names are compressed, this causes the size of the kallsyms name
data to change size (because we end up with a different compression)
which then causes the subsequent kallsyms data and other read-only data
to move.  This then causes 'inconsistent kallsyms data' error.

Now, looking at the __data_loc values in these files:

vm1.syms-c03bd408 t __irf_start
vm1.syms-c03bd408 T __security_initcall_end
vm1.syms-c03bd408 T __security_initcall_start
vm1.syms-c03bd608 T __initramfs_size
vm1.syms-c03bd608 t __irf_end
vm1.syms:c03be000 A __data_loc
vm1.syms-c03be000 A __init_end
vm1.syms-c03be000 D __per_cpu_end
vm1.syms-c03be000 D __per_cpu_load
vm1.syms-c03be000 D __per_cpu_start
vm1.syms-c03be000 D _data
--
vm2.syms-c0438608 t __irf_end
vm2.syms-c0439000 A __init_end
vm2.syms-c0439000 T __per_cpu_end
vm2.syms-c0439000 T __per_cpu_load
vm2.syms-c0439000 T __per_cpu_start
vm2.syms:c043a000 A __data_loc
vm2.syms-c043a000 D _data
vm2.syms-c043a000 D _sdata
vm2.syms-c043a000 D init_thread_union
vm2.syms-c043c000 D __nosave_begin
vm2.syms-c043c000 D __nosave_end

What we see here is the start of the data section aligned to 8K as
required for the init task data.  The per-cpu data is aligned to a 4K
boundary immediately before it.  However, as it is an empty section,
it can be aligned to the same 8K boundary as the data section depending
on the size and placement of the previous sections which include the
kallsyms data.

The solution?  We could artificially increase the alignment of the
per-cpu data, or waste a byte after the per-cpu data to ensure that we
don't align both together.  That could mean wasting up to 12K of space
for no reason other than to avoid this error which is exceedingly silly.

I'm not sure whether the kallsyms name data generation could be
changed so that this kind of thing doesn't matter but I suspect
that's an exceedingly difficult problem to crack.

In the mean time, I'd suggest building with the additional kallsyms pass
when it's required.


From thierry.reding at avionic-design.de  Sun Mar 25 07:48:16 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Sun, 25 Mar 2012 13:48:16 +0200
Subject: uImage with integrated dtb file
In-Reply-To: <4F6E5D5B.8050306@antcom.de>
References: <4F6E5D5B.8050306@antcom.de>
Message-ID: <20120325114816.GA13903@avionic-0098.mockup.avionic-design.de>

* Roland Stigge wrote:
> Hi,
> 
> since I will need to maintain some machines with DT enabled kernels but 
> containing a U-Boot without DT support, I sometimes need to integrate a 
> dtb file into uImage.

I use the new image format that is itself based on FDT and has support for
appending a DTB. Some documentation can be found here:

	http://git.denx.de/u-boot.git/?p=u-boot.git;a=tree;f=doc/uImage.FIT

Thierry
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From javier at dowhile0.org  Sun Mar 25 08:31:06 2012
From: javier at dowhile0.org (Javier Martinez Canillas)
Date: Sun, 25 Mar 2012 14:31:06 +0200
Subject: [PATCH RESEND 1/2] omap3: nand: Make board_onenand_init() visible to
 board code
Message-ID: <1332678667-4185-1-git-send-email-javier@dowhile0.org>

board_onenand_init() and board_nand_init() initialization functions are
used to initialize OneNAND and NAND memories respectively. But only
board_nand_init() was visible to be used from board code. This patch makes
possible to initialize a OneNAND flash memory within platform code.

Signed-off-by: Javier Martinez Canillas <javier at dowhile0.org>
---
 arch/arm/mach-omap2/board-flash.c |    4 ++--
 arch/arm/mach-omap2/board-flash.h |   11 +++++++++++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 0349fd2..70a81f9 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -87,7 +87,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
 	.dma_channel	= -1,   /* disable DMA in OMAP OneNAND driver */
 };
 
-static void
+void
 __init board_onenand_init(struct mtd_partition *onenand_parts,
 				u8 nr_parts, u8 cs)
 {
@@ -98,7 +98,7 @@ __init board_onenand_init(struct mtd_partition *onenand_parts,
 	gpmc_onenand_init(&board_onenand_data);
 }
 #else
-static void
+void
 __init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
 {
 }
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index d25503a..c44b70d 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -47,3 +47,14 @@ static inline void board_nand_init(struct mtd_partition *nand_parts,
 {
 }
 #endif
+
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+		defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+extern void board_onenand_init(struct mtd_partition *nand_parts,
+					u8 nr_parts, u8 cs);
+#else
+static inline void board_onenand_init(struct mtd_partition *nand_parts,
+					u8 nr_parts, u8 cs)
+{
+}
+#endif
-- 
1.7.7.6



From javier at dowhile0.org  Sun Mar 25 08:31:07 2012
From: javier at dowhile0.org (Javier Martinez Canillas)
Date: Sun, 25 Mar 2012 14:31:07 +0200
Subject: [PATCH RESEND 2/2] OMAP3: igep0020: Add support for Micron NAND Flash
 storage memory
In-Reply-To: <1332678667-4185-1-git-send-email-javier@dowhile0.org>
References: <1332678667-4185-1-git-send-email-javier@dowhile0.org>
Message-ID: <1332678667-4185-2-git-send-email-javier@dowhile0.org>

IGEP-based boards can have two different flash memories, a OneNAND or
a NAND device. The boot configuration pins (sys_boot) are used to
specify which memory is available. This patch is necessary in order to use
newer boards that come with NAND memories.

Also, it removes unnecesary code for registering the OneNAND.

Signed-off-by: Javier Martinez Canillas <javier at dowhile0.org>
---

 arch/arm/mach-omap2/board-igep0020.c |   75 ++++++++++++++--------------------
 1 files changed, 31 insertions(+), 44 deletions(-)

diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index e558800..dbd13b2 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -24,6 +24,8 @@
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
 
+#include <linux/mtd/nand.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
@@ -39,6 +41,8 @@
 #include "hsmmc.h"
 #include "sdram-numonyx-m65kxxxxam.h"
 #include "common-board-devices.h"
+#include "board-flash.h"
+#include "control.h"
 
 #define IGEP2_SMSC911X_CS       5
 #define IGEP2_SMSC911X_GPIO     176
@@ -60,6 +64,10 @@
 #define IGEP3_GPIO_LED1_RED	16
 #define IGEP3_GPIO_USBH_NRESET  183
 
+#define IGEP_SYSBOOT_MASK           0x1f
+#define IGEP_SYSBOOT_NAND           0x0f
+#define IGEP_SYSBOOT_ONENAND        0x10
+
 /*
  * IGEP2 Hardware Revision Table
  *
@@ -110,8 +118,10 @@ static void __init igep2_get_revision(void)
 	gpio_free(IGEP2_GPIO_LED1_RED);
 }
 
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
-	defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+#if defined(CONFIG_MTD_ONENAND_OMAP2) ||		\
+	defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) ||	\
+	defined(CONFIG_MTD_NAND_OMAP2) ||		\
+	defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 
 #define ONENAND_MAP             0x20000000
 
@@ -123,7 +133,7 @@ static void __init igep2_get_revision(void)
  * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
  */
 
-static struct mtd_partition igep_onenand_partitions[] = {
+static struct mtd_partition igep_flash_partitions[] = {
 	{
 		.name           = "X-Loader",
 		.offset         = 0,
@@ -151,50 +161,27 @@ static struct mtd_partition igep_onenand_partitions[] = {
 	},
 };
 
-static struct omap_onenand_platform_data igep_onenand_data = {
-	.parts = igep_onenand_partitions,
-	.nr_parts = ARRAY_SIZE(igep_onenand_partitions),
-	.dma_channel	= -1,	/* disable DMA in OMAP OneNAND driver */
-};
-
-static struct platform_device igep_onenand_device = {
-	.name		= "omap2-onenand",
-	.id		= -1,
-	.dev = {
-		.platform_data = &igep_onenand_data,
-	},
-};
+static inline u32 igep_get_sysboot_value(void)
+{
+	return omap_ctrl_readl(OMAP343X_CONTROL_STATUS) & IGEP_SYSBOOT_MASK;
+}
 
 static void __init igep_flash_init(void)
 {
-	u8 cs = 0;
-	u8 onenandcs = GPMC_CS_NUM + 1;
-
-	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-		u32 ret;
-		ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-		/* Check if NAND/oneNAND is configured */
-		if ((ret & 0xC00) == 0x800)
-			/* NAND found */
-			pr_err("IGEP: Unsupported NAND found\n");
-		else {
-			ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
-			if ((ret & 0x3F) == (ONENAND_MAP >> 24))
-				/* ONENAND found */
-				onenandcs = cs;
-		}
-	}
-
-	if (onenandcs > GPMC_CS_NUM) {
-		pr_err("IGEP: Unable to find configuration in GPMC\n");
-		return;
-	}
-
-	igep_onenand_data.cs = onenandcs;
-
-	if (platform_device_register(&igep_onenand_device) < 0)
-		pr_err("IGEP: Unable to register OneNAND device\n");
+	u32 mux;
+	mux = igep_get_sysboot_value();
+
+	if (mux == IGEP_SYSBOOT_NAND) {
+		pr_info("IGEP: initializing NAND memory device\n");
+		board_nand_init(igep_flash_partitions,
+				ARRAY_SIZE(igep_flash_partitions),
+				0, NAND_BUSWIDTH_16);
+	} else if (mux == IGEP_SYSBOOT_ONENAND) {
+		pr_info("IGEP: initializing OneNAND memory device\n");
+		board_onenand_init(igep_flash_partitions,
+				   ARRAY_SIZE(igep_flash_partitions), 0);
+	} else
+		pr_err("IGEP: Flash: unsupported sysboot sequence found\n");
 }
 
 #else
-- 
1.7.7.6



From pwaechtler at mac.com  Sun Mar 25 08:08:47 2012
From: pwaechtler at mac.com (Peter Waechtler)
Date: Sun, 25 Mar 2012 12:08:47 +0000 (UTC)
Subject: ARM11MPcore: =?utf-8?b?dGxiX29wc19uZWVkX2Jyb2FkY2FzdA==?= causes
 deadlock
References: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
 <20120323173055.GC16225@mudshark.cambridge.arm.com>
Message-ID: <loom.20120325T135816-592@post.gmane.org>

Will Deacon <will.deacon <at> arm.com> writes:

> 
> > The cpuB executes some user code hitting that page and because the PTE
> > is marked "inaccessible", so that the attempt can be stored, it results
> > in a page fault.
> 
> Shouldn't this trigger a prefetch abort rather than a data abort?
> 

Yes, I think the abort part is not completely understood yet.

So it's a data abort, some code referenced a page resulting in a dabrt_usr.
Then the abort handler tries to read the instruction and gets another dabrt.

That would mean that the code page was marked as inaccessible in the
mean time.
Now how could that happen? Probably on the other cpu?

Weird stuff.

But Will, is that tlb_flush necessary at all? The ARM has only 3 permission
bits in the page table (APX and AP0 and AP1). The young/accessed bit is done
via software.


    Peter






From linux at arm.linux.org.uk  Sun Mar 25 09:09:12 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 25 Mar 2012 14:09:12 +0100
Subject: ARM11MPcore: tlb_ops_need_broadcast causes deadlock
In-Reply-To: <loom.20120325T135816-592@post.gmane.org>
References: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
 <20120323173055.GC16225@mudshark.cambridge.arm.com>
 <loom.20120325T135816-592@post.gmane.org>
Message-ID: <20120325130912.GF5611@n2100.arm.linux.org.uk>

On Sun, Mar 25, 2012 at 12:08:47PM +0000, Peter Waechtler wrote:
> But Will, is that tlb_flush necessary at all? The ARM has only 3 permission
> bits in the page table (APX and AP0 and AP1). The young/accessed bit is done
> via software.

Yes it most definitely is, because setting a page to be young means we
must receive a subsequent fault to make it 'old' again.  This means we
must set the page to be inaccessible to get that fault, and flush the
TLBs across all CPUs so that any CPU accessing that page receives a
fault.


From mgherzan at gmail.com  Sun Mar 25 09:12:34 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Sun, 25 Mar 2012 15:12:34 +0200
Subject: [PATCH v8 RESEND] ARM: net: JIT compiler for packet filters
In-Reply-To: <20120325095711.GC5611@n2100.arm.linux.org.uk>
References: <1331933316-10197-1-git-send-email-mgherzan@gmail.com>
 <20120319.172005.1889334604020296555.davem@davemloft.net>
 <4F6EEAB5.7070009@gmail.com> <20120325095711.GC5611@n2100.arm.linux.org.uk>
Message-ID: <4F6F19C2.60602@gmail.com>

Am 25.03.2012 11:57, schrieb Russell King - ARM Linux:
> On Sun, Mar 25, 2012 at 11:51:49AM +0200, Mircea Gherzan wrote:
>> Am 19.03.2012 22:20, schrieb David Miller:
>>> I would like to see this merged however is feasible, this has been in
>>> a catatonic state for two releases and waiting longer isn't going to
>>> improve things enough to justify any further delay.
>>
>> It has been merged into the ARM tree more than a week ago, but
>> unfortunately it seems it will not make it into 3.4.
> 
> Why do you say that?

The patch is nowhere to be found in any of the branches of your
linaro.org tree, the tree from which Linus pulls.


From linux at arm.linux.org.uk  Sun Mar 25 09:35:06 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 25 Mar 2012 14:35:06 +0100
Subject: [PATCH v8 RESEND] ARM: net: JIT compiler for packet filters
In-Reply-To: <4F6F19C2.60602@gmail.com>
References: <1331933316-10197-1-git-send-email-mgherzan@gmail.com>
 <20120319.172005.1889334604020296555.davem@davemloft.net>
 <4F6EEAB5.7070009@gmail.com> <20120325095711.GC5611@n2100.arm.linux.org.uk>
 <4F6F19C2.60602@gmail.com>
Message-ID: <20120325133506.GG5611@n2100.arm.linux.org.uk>

On Sun, Mar 25, 2012 at 03:12:34PM +0200, Mircea Gherzan wrote:
> Am 25.03.2012 11:57, schrieb Russell King - ARM Linux:
> > On Sun, Mar 25, 2012 at 11:51:49AM +0200, Mircea Gherzan wrote:
> >> Am 19.03.2012 22:20, schrieb David Miller:
> >>> I would like to see this merged however is feasible, this has been in
> >>> a catatonic state for two releases and waiting longer isn't going to
> >>> improve things enough to justify any further delay.
> >>
> >> It has been merged into the ARM tree more than a week ago, but
> >> unfortunately it seems it will not make it into 3.4.
> > 
> > Why do you say that?
> 
> The patch is nowhere to be found in any of the branches of your
> linaro.org tree, the tree from which Linus pulls.

I only push stuff out there just before asking Linus to pull.  The main
tree is on zeniv aka ftp.arm.linux.org.uk as detailed on my website which
does contain your patch - and its this tree with linux-next fetches.

As Linus is away on an extended weekend, don't expect to see many more
pushes from me before Monday/Tuesday.

But, rest assured, I _am_ intending sending it for this merge window.


From arnd at arndb.de  Sun Mar 25 10:55:43 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 25 Mar 2012 14:55:43 +0000
Subject: [GIT PULL 0/9] arm-soc updates, first batch
In-Reply-To: <20120325105054.GD5611@n2100.arm.linux.org.uk>
References: <1332626568-17812-1-git-send-email-arnd@arndb.de>
 <20120325105054.GD5611@n2100.arm.linux.org.uk>
Message-ID: <201203251455.43473.arnd@arndb.de>

On Sunday 25 March 2012, Russell King - ARM Linux wrote:
> Arnd, I assume this shortlog is for the entire arm-soc queue rather than
> this set of 9 pull requests?  If so fine.
> 
> If not, I couldn't find Rob's IO stuff in this set of 9 pulls - at the
> moment because PXA currently fails to build because of that, and there's
> a couple of patches on the list from Rob sent on the 20th to solve that.
> However, Rob hasn't sent them to you yet.  I've already prodded over them
> to try and find out what's happening.

Yes, that's right. My script was comparing the wrong versions here.

See below for the actual shortlog of the current set of pull requests.

	Arnd

---

Aaro Koskinen (1):
      ARM: OMAP: add minimal support for Nokia RM-696

Afzal Mohammed (1):
      ARM: OMAP2+: id: Add am33xx SoC type detection

Alex (1):
      ARM: OMAP: Add omap_reserve functionality

Alex Gershgorin (1):
      i.MX35-PDK: Add Camera support

Amit Daniel Kachhap (5):
      ARM: EXYNOS: Add support AFTR mode on EXYNOS4210
      ARM: S5P: add L2 early resume code
      ARM: EXYNOS: save L2 settings during bootup
      ARM: EXYNOS: remove useless code to save/restore L2
      ARM: EXYNOS: Enable l2 configuration through device tree

Andrew Lunn (2):
      ARM: orion: spi: remove enable_clock_fix which is not used
      ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data.

Andrzej Pietrasiewicz (3):
      ARM: EXYNOS: add support JPEG
      ARM: EXYNOS: Register JPEG on universal_c210
      ARM: EXYNOS: Register JPEG on nuri

Arnd Bergmann (122):
      Merge branch 'v3.4-next/devel-samsung-rtc' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'depends/driver-core' into next/soc2
      Merge branch 'ux500/soc' into next/soc2
      Merge branch 'lpc32xx/drivers' into next/drivers
      Merge tag 'rpmsg-for-3.4' of git://git.kernel.org/.../ohad/remoteproc into next/rpmsg
      Merge branch 'vexpress-dt-v3.3-rc4' of git://git.linaro.org/people/pawelmoll/linux into next/dt
      Merge branch 'features/cs89x0' of git://git.pengutronix.de/git/imx/linux-2.6 into next/drivers
      Merge branch 'imx-fixes' of git://git.pengutronix.de/git/imx/linux-2.6 into next/fixes-non-critical
      Merge branch 'imx-cleanup' of git://git.pengutronix.de/git/imx/linux-2.6 into next/cleanup
      Merge branch 'imx-drivers' of git://git.pengutronix.de/git/imx/linux-2.6 into next/drivers
      Merge branch 'v3.4/fixes' of git://gitorious.org/linux-davinci/linux-davinci into next/fixes-non-critical
      ARM: davinci: add back dummy header files
      Merge branch 'davinci/cleanups' into next/cleanup
      Merge branch 'kirkwood/board' into next/boards
      Merge branch 'lpc32xx/fixes-non-critical' of git://git.antcom.de/linux-2.6 into next/fixes-non-critical
      Merge branch 'mxs/gpmi' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/drivers
      Merge branch 'imx/driver' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/drivers
      Merge branch 'imx/dt' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
      Merge branch 'imx/defconfig' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
      Merge branch 'rtc-sa1100' of git://github.com/hzhuang1/linux into next/drivers
      Merge branch 'cleanup-3.4' of git://github.com/hzhuang1/linux into next/cleanup
      Merge branch 'board-specific' of git://github.com/hzhuang1/linux into next/boards
      Merge branch 'at91-3.4-base2+cleanup' of git://github.com/at91linux/linux-at91 into at91/staging/base2+cleanup
      ARM: ux500: U8500 depends on MMU
      ARM: ux500: add board autoselection
      ARM: ux500: select L2X0 cache on ux500
      ARM: ux500: select CPU_FREQ_TABLE where needed
      Merge branch 'fixes-non-critical' of git://git.kernel.org/.../tmlind/linux-omap into next/fixes-non-critical
      Merge branch 'soc' of git://git.kernel.org/.../tmlind/linux-omap into next/soc
      Merge branch 'omap1' of git://git.kernel.org/.../tmlind/linux-omap into next/boards
      Merge branch 'dt' of git://git.kernel.org/.../tmlind/linux-omap into next/dt
      Merge branch 'cleanup' of git://git.kernel.org/.../tmlind/linux-omap into omap/cleanup
      Merge branch 'cleanup' of git://git.kernel.org/.../tmlind/linux-omap into next/cleanup
      Merge branch 'depends/omap/gpio/runtime-pm-cleanup' into next/cleanup
      Merge branches 'depends/irqdomain' and 'at91/base2+cleanup' into next/dt
      Merge branch 'at91-3.4-cleanup2+DT' of git://github.com/at91linux/linux-at91 into next/dt
      Merge branch 'features/imx27-visstrim' of git://git.pengutronix.de/git/imx/linux-2.6 into next/boards
      Merge branch 'features/imx27-dt' of git://git.pengutronix.de/git/imx/linux-2.6 into next/dt
      Merge branch 'features/imx31-moboard' of git://git.pengutronix.de/git/imx/linux-2.6 into next/boards
      Merge branch 'features/imx3' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
      ARM: tegra: select CPU_FREQ_TABLE
      ARM: tegra: build localtimer support only when needed
      ARM: tegra: export usb phy symbols
      Merge tag 'tegra-cleanups' of git://git.kernel.org/.../olof/tegra into tegra/cleanups
      Merge tag 'tegra-cleanups' of git://git.kernel.org/.../olof/tegra into tegra/cleanups
      Merge tag 'tegra-dt' of git://git.kernel.org/.../olof/tegra into tegra/dt
      Merge tag 'tegra-soc' of git://git.kernel.org/.../olof/tegra into tegra/soc
      Merge tag 'tegra-soc-drivers' of git://git.kernel.org/.../olof/tegra into tegra/soc-drivers
      Merge tag 'tegra-soc2' of git://git.kernel.org/.../olof/tegra into tegra/soc2
      Merge tag 'tegra-boards' of git://git.kernel.org/.../olof/tegra into tegra/boards
      Merge branch 'depends/irqdomain' into next/drivers
      Merge branch 'ux500-fixes-20120301' of git://git.kernel.org/.../linusw/linux-stericsson into next/fixes-non-critical
      Merge branch 'ux500/timers' into next/timer
      Merge branch 'vexpress/timer' into next/timer
      Merge branch 'local_timers-for-arm-soc' of git://git.kernel.org/.../maz/arm-platforms into next/timer
      ARM: shmobile: remove additional __io() macro use
      Merge branch 'local_timers-for-arm-soc' of git://git.kernel.org/.../maz/arm-platforms into next/timer
      Merge tag 'imx25-iomux-ds' of git://git.pengutronix.de/git/imx/linux-2.6 into next/fixes-non-critical
      Merge branches 'lpc32xx/mach-lpc32xx-eth' and 'lpc32xx/mach-lpc32xx-usb' of git://git.antcom.de/linux-2.6 into lpc32xx/drivers
      Merge branch 'lpc32xx/drivers' into next/drivers
      Merge branch 'ep93xx-for-arm-soc' of git://github.com/RyanMallon/linux-2.6 into next/cleanup
      Merge branch 'fixes' of git://gitorious.org/linux-davinci/linux-davinci into next/fixes-non-critical
      Merge branch 'board-specific' of git://github.com/hzhuang1/linux into next/boards
      Merge branch 'fixes-non-critical' of git://github.com/hzhuang1/linux into next/maintainers
      Merge tag 'imx35-cam-fb' of git://git.pengutronix.de/git/imx/linux-2.6 into next/boards
      Merge branch 'renesas/fixes' into renesas/soc
      Merge branch 'renesas/soc' into next/soc
      Merge branch 'v3.4/features' of git://gitorious.org/linux-davinci/linux-davinci into next/drivers
      Merge branch 'next/soc-exynos5250-gpio' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'next/soc-exynos5250-arch' of git://git.kernel.org/.../kgene/linux-samsung into samsung/exynos5
      Merge branch 'for-armsoc' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm into next/soc2
      Merge branch 'samsung/exynos5' into next/soc2
      Merge branch 'samsung/soc' into next/soc2
      Merge branch 'at91-3.4-cleanup2-DT2' of git://github.com/at91linux/linux-at91 into next/dt
      Merge branch 'at91-3.4-cleanup2-DT2+USB' of git://github.com/at91linux/linux-at91 into next/dt
      Merge branch 'ux500/soc' into ux500/dt
      Merge branch 'depends/driver-core' into ux500/dt
      ARM: ux500: Initial Device Tree support for Snowball
      ARM: ux500: combine the board init functions for DT boot
      ARM: ux500: split dts file for snowball into generic part
      Merge branch 'ux500/dt' into next/dt2
      Merge branch 'kirkwood_dt_for_3.4_v3' of git://git.infradead.org/users/jcooper/linux-kirkwood into kirkwood/dt
      Merge branch 'spear/dt' into next/dt2
      ARM: tegra: select USB_ULPI if USB is selected
      clk: make CONFIG_COMMON_CLK invisible
      Merge branch 'for-3.4/dt' of git://git.kernel.org/.../olof/tegra into next/dt2
      Merge branch 'for-3.4/cleanup-and-fixes' of git://git.kernel.org/.../olof/tegra into tegra/cleanups
      Merge branch 'tegra/cleanups' into next/cleanup2
      Merge branch 'for-3.4/boards' of git://git.kernel.org/.../olof/tegra into next/boards
      Merge branch 'fixes' into next/fixes-non-critical
      Merge branch 'renesas/timer' into next/timer
      Merge branch 'samsung/cleanup-exynos-clock' into next/soc
      Merge branch 'imx/defconfig' into next/drivers
      Merge branch 'next/fixes-non-critical' into next/drivers
      Merge branch 'tegra/cleanups' into next/timer
      Merge branch 'for-3.4' of git://gitorious.org/linux-omap-dss2/linux into next/cleanup
      Merge tag 'regulator-3.4' of git://git.kernel.org/.../broonie/regulator into next/drivers
      Merge tag 'asoc-3.4' of git://git.kernel.org/.../broonie/sound into next/boards
      Merge branch 'omap/fixes-non-critical-part2' into next/cleanup
      Merge branch 'rmobile-fixes-for-linus' of git://github.com/pmundt/linux-sh into renesas/soc
      Merge branch 'renesas/soc' into next/soc2
      Merge branch 'kirkwood/dt' into next/dt2
      Merge branch 'depends/omap/gpio/runtime-pm-cleanup' into for-next
      Merge branch 'next/fixes-non-critical' into for-next
      Merge branch 'next/cleanup' into for-next
      Merge branch 'next/maintainers' into for-next
      Merge branch 'next/timer' into for-next
      Merge branch 'next/soc' into for-next
      Merge branch 'next/boards' into for-next
      Merge branch 'next/rpmsg' into for-next
      Merge branch 'next/drivers' into for-next
      Merge branch 'next/dt' into for-next
      Merge branch 'next/cleanup2' into for-next
      Merge branch 'next/drivers2' into for-next
      Merge branch 'next/clk' into for-next
      Merge branch 'next/soc2' into for-next
      Merge branch 'next/dt2' into for-next
      [arm-soc internal] add back contents file
      Merge tag 'fbdev-updates-for-3.4' of git://github.com/schandinat/linux-2.6 into omap/cleanup
      Merge branch 'omap/fixes-non-critical-part2' into omap/cleanup
      Merge branch 'omap/cleanup' into next/cleanup
      Merge branch 'next/cleanup' into for-next

Axel Lin (1):
      rpmsg: rename virtqueue_add_buf_gfp to virtqueue_add_buf

Benoit Cousson (14):
      arm/dts: OMAP: Remove bootargs node from board files
      ARM: OMAP2+: kconfig: Enable devicetree by default for OMAP2+ systems
      ARM: OMAP2+: board-generic: Remove un-needed .atag_offset for DT_MACHINE
      ARM: OMAP2+: omap_device: Replace dev_warn by dev_dbg in omap_device_build_from_dt
      ARM: OMAP2+: pm: Do not init statically the SR and voltage layer with DT
      ARM: OMAP1: kconfig: Enable IRQ_DOMAIN by default for OMAP1 platforms
      arm/dts: OMAP3&4: Remove the '0x' prefix for serial nodes
      arm/dts: OMAP4: Add i2c controller nodes
      arm/dts: OMAP3: Add i2c controller nodes
      arm/dts: OMAP4: Update DTS file with new GIC bindings
      Merge branch 'irqdomain/next' of git://git.secretlab.ca/git/linux-2.6 into for_3.4/dt_irq_domain2
      ARM: OMAP2/3: intc: Add DT support for TI interrupt controller
      arm/dts: OMAP3: Add interrupt-controller bindings for INTC
      ARM: OMAP2+: board-generic: Use of_irq_init API

Bernhard Walle (1):
      ARM: OMAP2+: GPMC: Export gpmc_enable_hwecc and gpmc_calculate_ecc

Boojin Kim (2):
      ARM: EXYNOS: Enable MDMA driver
      ARM: EXYNOS: add support DMA for EXYNOS4X12 SoC

Changhwan Youn (1):
      ARM: EXYNOS: fix cycle count for periodic mode of clock event timers

Charulatha V (8):
      gpio/omap: remove dependency on gpio_bank_count
      gpio/omap: use flag to identify wakeup domain
      gpio/omap: make gpio_context part of gpio_bank structure
      gpio/omap: make non-wakeup GPIO part of pdata
      gpio/omap: avoid cpu checks during module ena/disable
      gpio/omap: use pinctrl offset instead of macro
      gpio/omap: remove bank->method & METHOD_* macros
      gpio/omap: fix bankwidth for OMAP7xx MPUIO

Dan Liang (2):
      ARM: at91/at91sam9x5: overall definition
      ARM: at91/at91sam9x5: SoC basic support

Daniel Lezcano (4):
      ARM: at91: coding style fixes
      ARM: at91: declare header name
      ARM: at91: remove wait_for_interrupt definition
      ARM: at91: implement the standby function for pm/cpuidle

Danny Kukawka (3):
      ARM: ux500: included linux/gpio.h twice
      ARM: OMAP: clock.c: included linux/debugfs.h twice
      ARM: OMAP2+: included some headers twice

Dirk Behme (1):
      ARM: imx6: Rename DEBUG_IMX6Q_UART to UART4

Dmitry Artamonow (3):
      arm/tegra: fix harmony pinmux for PCIe
      arm/tegra: add timeout to PCIe PLL lock detection loop
      arm/tegra: pcie: fix return value of function

Doug Anderson (2):
      ARM: tegra: Introduce define DEBUG_UART_SHIFT
      ARM: tegra: uncompress.h: Store UART address in a variable

Eunki Kim (1):
      ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5

Fabio Estevam (16):
      ARM: mx28: Let audio support be built by default
      ARM: mx28: Remove duplicate OCOTP error message
      ARM: mx28evk: Simplify GPIO requests
      ARM: mxs: Use a proper timeout mechanism
      ARM: mach-pcm038: Fix field name of regulator_consumer_supply struct
      ARM: imx_v4_v5_defconfig: Fix the selection of 32 bit flash support for iMX21ADS board
      ARM: imx_v6_v7_defconfig: Add support for framebuffer and camera on mx31
      ARM: mx27_3ds: Add camera support
      ARM: imx_v4_v5_defconfig: Update defconfig
      ARM: plat-mxc: audmux-v1: Remove unneeded ifdef's
      ARM: mx3: Let mx31 and mx35 share the same CCM header file
      ARM: mach-imx: mx3: Fix section mismatch in imx3_init_l2x0()
      ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI
      ARM: mx3: Setup AIPS registers
      ARM: mx5: Use common function for configuring AIPS
      ARM: mx35: Setup the AIPS registers

Felipe Balbi (4):
      ARM: OMAP3+: SmartReflex: add missing platform_set_drvdata()
      ARM: OMAP3+: SmartReflex: move late_initcall() closer to its argument
      ARM: OMAP3+: SmartReflex: misc cleanups
      ARM: OMAP3+: SmartReflex: micro-optimization for sanity check

Felipe Contreras (1):
      ARM: OMAP: mailbox: trivial whitespace fix

Grazvydas Ignotas (2):
      ARM: OMAP: pandora: add support for backlight and poweroff
      ARM: omap: pandora: fix usbhs platform data

H Hartley Sweeten (1):
      ep93xx: Convert the watchdog driver into a platform device.

Haojian Zhuang (16):
      rtc: sa1100: remove periodic code
      rtc: sa1100: remove verification code of alarm
      rtc: sa1100: declare irq in resource
      ARM: pxa: add rtc dummy clock
      rtc: sa1100: enable clk support
      ARM: mmp: append irq name of gpio device
      ARM: pxa: add dummy clock for pxa25x and pxa27x
      ARM: mmp: enable rtc in pxa910
      rtc: sa1100: add OF support
      serial: pxa: add OF support
      i2c: pxa: add OF support
      ARM: mmp: enable rtc clk in pxa168
      ARM: mmp: append OF support on pxa168
      ARM: dts: append DTS file of pxa168
      Document: devicetree: add OF documents for arch-mmp
      MAINTAINERS: update MAINTAINERS email entry

Heiko Schocher (1):
      ARM: davinci: map default_queue to edma channels

Heiko Stuebner (21):
      ARM: S3C24XX: remove unused spi gpio setup functions
      ARM: S3C24XX: move spi-s3c24xx platdata out of mach
      ARM: S3C24XX: Remove extern declaration of clk_msysclk
      ARM: S3C24XX: move common S3C2443 clock definitions to clock.h
      ARM: S3C2410: move s3c2410_baseclk_add to clock.h
      ARM: SAMSUNG: cleanup of rtc register definitions
      rtc-s3c: make room for more variants in devicetree block
      rtc-s3c: add variants for S3C2443 and S3C2416
      ARM: S3C2443/S3C2416: add s3c_rtc_setname and rename rtc devices
      ARM: S3C24XX: Move s3c2443-clock.c to mach-s3c24xx
      ARM: S3C24XX: Move common-smdk code to mach directory
      ARM: S3C24XX: move simtec-specific code to mach directory
      ARM: S3C24XX: Consolidate Simtec extensions
      ARM: S3C24XX: Move device setup files to mach directory
      ARM: S3C24XX: Fix indentation of dma-s3c2443
      ARM: S3C24XX: Reuse S3C2443 dma for S3C2416
      ARM: S3C24XX: remove obsolete S3C2416_DMA option
      ARM: S3C24XX: remove XXX_setup_clocks method from S3C2443
      ARM: S3C24XX: add get_rate for clk_h on S3C2416/2443
      ARM: S3C24XX: add get_rate for clk_p on S3C2416/2443
      ARM: S3C24XX: remove call to s3c24xx_setup_clocks

Heiko St?bner (2):
      pxa: magician/hx4700: Convert to gpio-regulator from bq24022
      regulator: Remove bq24022 regulator driver

Hong Xu (1):
      ARM: at91: Update struct atmel_nand_data to support PMECC

Huang Shijie (1):
      ARM: mxs: add GPMI-NAND support for imx23/imx28

Igor Grinberg (1):
      ARM: OMAP3: cm-t3517: add EMAC support

Ilya Yanok (3):
      ARM: OMAP: move generic EMAC init to separate file
      arm/dts: mt_ventoux: very basic support for TeeJet Mt.Ventoux board
      ARM: OMAP2+: ads7846_init: put gpio_pendown into pdata if it's provided

Jaccon Bastiaansen (4):
      CS89x0 : add platform driver support
      CS89x0 : add CS89x0 platform device to the iMX21ADS board
      CS89x0 : remove QQ2440 board support from the CS89x0 driver
      CS89x0 : add CS89x0 platform device to the iMX31ADS board

Jaecheol Lee (1):
      ARM: EXYNOS: add clock registers for exynos4x12-cpufreq

Jaehoon Chung (3):
      ARM: SAMSUNG: support the second capability for samsung-soc
      mmc: sdhci-s3c: add platform data for the second capability
      ARM: SAMSUNG: change the name from s3c-sdhci to exynos4-sdhci

Janusz Krzysztofik (12):
      ARM: OMAP1: ams-delta: register latch dependent devices later
      ARM: OMAP1: ams-delta: convert latches to basic_mmio_gpio
      ARM: OMAP1: ams-delta: supersede custom led device by leds-gpio
      LED: drop leds-ams-delta driver
      MTD: NAND: ams-delta: use GPIO instead of custom I/O
      omapfb: lcd_ams_delta: drive control lines over GPIO
      input: serio: ams-delta: toggle keyboard power over GPIO
      ARM: OMAP1: ams-delta: fix incorrect section tags
      ARM: OMAP1: ams-delta: clean up init data section assignments
      ARM: OMAP1: ams-delta: set up regulator over modem reset GPIO pin
      ARM: OMAP1: ams-delta: update the modem to use regulator API
      ASoC: OMAP: ams-delta: drop .set_bias_level callback

Jarkko Nikula (1):
      ARM: OMAP: McSPI: Remove unused flag from struct omap2_mcspi_device_config

Jason Cooper (9):
      ARM: kirkwood: add dreamplug (fdt) support.
      ARM: kirkwood: convert uart0 to devicetree.
      ARM: orion: wdt: use resource vice direct access
      ARM: kirkwood: fdt: use mrvl ticker symbol
      ARM: kirkwood: fdt: absorb kirkwood_init()
      ARM: kirkwood: fdt: facilitate new boards during fdt migration
      ARM: kirkwood: fdt: define uart[01] as disabled, enable uart0
      ARM: kirkwood: rtc-mv devicetree bindings
      ARM: kirkwood: use devicetree for rtc-mv

Javier Martin (5):
      i.MX27: visstrim_m10: Add m41t00 RTC support.
      i.MX27: visstrim_m10: Sort IMX_HAVE_PLATFORM_MXC_MMC properly.
      i.MX27: visstrim_m10: Register I2C devices after I2C busses have been added.
      i.MX27: visstrim_m10: Add video support.
      i.MX27: visstrim_m10: Add led support.

Jean Pihet (3):
      ARM: OMAP3+: SmartReflex: fix the use of debugfs_create_* API
      ARM: OMAP3+: SmartReflex: fix error handling
      ARM: OMAP2+: PM debug: fix the use of debugfs_create_* API

Jean-Christophe PLAGNIOL-VILLARD (50):
      ARM: at91: code removal of CAP9 SoC
      ARM: at91: factorise duplicated at91sam9 idle
      ARM: at91/at91x40: remove use of at91_sys_read/write
      ARM: at91: make matrix register base soc independent
      ARM: at91: make ST (System Timer) soc independent
      ARM: at91/pm_slowclock: rename register to named define
      ARM: at91/pm_slowclock: function slow_clock() accepts parameters
      ARM: at91: move at91rm9200 sdramc defines to at91rm9200_sdramc.h
      ARM: at91: make sdram/ddr register base soc independent
      ARM: at91/pm_slowclock: add runtime detection of memory contoller
      ARM: at91/PMC: make register base soc independent
      ARM: at91/rtc-at91sam9: each SoC can select the RTT device to use
      ARM: at91:rtc/rtc-at91sam9: ioremap register bank
      ARM: at91/rtc-at91sam9: pass the GPBR to use via resources
      ARM: at91: finally drop at91_sys_read/write
      ARM: at91: merge SRAM Memory banks thanks to mirroring
      Atmel: move console default platform_device to serial driver
      ARM: at91/board-dt: drop default console
      ARM: at91: properly sort dtb files in Makefile.boot
      ARM: at91: pit add DT support
      ARM: at91: usb_a9g20/dt: add leds support
      ARM: at91: at91sam9m10g45ek/dt: add leds support
      ARM: at91: at91sam9m10g45ek/dt: add gpio-keys support
      ARM: at91: usb_a9g20/dt: add gpio-keys support
      ARM: at91: at91sam9x5cm/dt: add leds support
      ATMEL: fix nand ecc support
      mtd/atmel_nand: add on_flash_bbt to enable the use of On Flash BBT
      ARM: at91: enable on flash bbt for Atmel Reference and DT boards
      of: introduce helper to manage boolean
      of/mtd/nand: add generic bindings and helpers
      atmel/nand: add DT support
      ARM: at91: sam9x5 add nand support
      i2c/gpio: add DT support
      ARM: at91: sam9g20 add i2c DT support
      ARM: at91: usb_a9g20 add DT i2c support
      ARM: at91: sam9g45 add i2c DT support
      ARM: at91: sam9x5 add i2c DT support
      ARM: at91/dt: add Calao DAB-MMX daugther board support for USB-A9G20
      ARM: at91/dt: add specific DT soc init
      ARM: at91: add pmc DT support
      ARM: at91: always enable sam9 restart
      ARM: at91: add RSTC (Reset Controller) dt support
      ARM: at91: add ram controller DT support
      ARM: at91: add Shutdown Controller (SHDWC) DT support
      ARM: at91: usb ohci add dt support
      ARM: at91: dt: enable usb ohci for sam9g20, sam9g45 amd sam9x5
      ARM: at91: usb ehci add dt support
      ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5
      USB: at91: Device udc add dt support
      ARM: at91: sam9g20 udc add dt support

Jesper Juhl (1):
      ARM: Remove redundant ';' from avic_irq_set_priority()

Jett.Zhou (1):
      ARM: sa1100: clean up clock support

Jingoo Han (1):
      ARM: SAMSUNG: Add a callback 'notify_after' for PWM backlight control

Jon Hunter (1):
      ARM: OMAP: Remove definition cpu_is_omap4430()

Joonyoung Shim (2):
      ARM: S3C64XX: Add usb otg phy control
      ARM: S5PV210: Add usb otg phy control

Josh Wu (2):
      ARM: at91: add clock selection parameter for at91_add_device_isi()
      ARM: at91: add Atmel ISI and ov2640 support on sam9m10g45 board

Kamil Debski (3):
      ARM: EXYNOS: add G2D to mach-nuri
      ARM: EXYNOS: add G2D to mach-universal
      ARM: SAMSUNG: add G2D to plat-s5p and mach-exynos

Kevin Hilman (6):
      ARM: OMAP: convert omap_device_build() and callers to __init
      Merge remote-tracking branch 'omap/hsmmc' into for_3.4/cleanup/pm-base
      ARM: OMAP: omap_device: remove omap_device_parent
      ARM: OMAP2+: PM: fix section mismatch with omap2_init_processor_devices()
      ARM: OMAP2+: PM: fix wakeupgen warning when hotplug disabled
      ARM: OMAP2+: gpmc-smsc911x: only register regulator for first instance

Kukjin Kim (32):
      ARM: EXYNOS: use static declaration when it is not used in other files
      ARM: S3C24XX: use static declaration when it is not used in other files
      ARM: S3C64XX: use static declaration when it is not used in other files
      ARM: S5P64X0: use static declaration when it is not used in other files
      ARM: S5PC100: use static declaration when it is not used in other files
      ARM: S5PV210: use static declaration when it is not used in other files
      ARM: SAMSUNG: use static declaration when it is not used in other files
      ARM: S3C24XX: change the ARCH_S3C2410 to ARCH_S3C24XX
      ARM: S3C2410: move mach-s3c2410/* into mach-s3c24xx/
      ARM: S3C2412: move mach-s3c2412/* into mach-s3c24xx/
      ARM: S3C2416: move mach-s3c2416/* into mach-s3c24xx/
      ARM: S3C2440: move mach-s3c2440/* into mach-s3c24xx/
      ARM: S3C2443: move mach-s3c2443/* into mach-s3c24xx/
      ARM: s3c2410_defconfig: update s3c2410_defconfig
      Merge branch 'topic/cleanup-s3c24xx' into next/cleanup-s3c24xx
      Merge branch 'topic/cleanup-use-static' into next/cleanup-use-static
      Merge branch 'next/cleanup-use-static' into next/cleanup-exynos-clock
      ARM: EXYNOS: replace clock.c for other new EXYNOS SoCs
      ARM: EXYNOS: use static declaration on regarding clock
      ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock
      PM / devfreq: update the name of EXYNOS clock register
      ARM: EXYNOS: to declare static for mach-exynos/common.c
      ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts()
      ARM: EXYNOS: add clock part for EXYNOS5250 SoC
      ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
      ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
      ARM: EXYNOS: add support for EXYNOS5250 SoC
      ARM: EXYNOS: add interrupt definitions for EXYNOS5250
      ARM: EXYNOS: add support get_core_count() for EXYNOS5250
      ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5 SoCs
      ARM: EXYNOS: add support device tree enabled board file for EXYNOS5
      ARM: dts: add initial dts file for EXYNOS5250, SMDK5250

Kuninori Morimoto (1):
      ARM: mach-shmobile: ap4evb: Reserve DMA memory for the frame buffer

Lauri Hintsala (1):
      ARM: mxs: Add initial support for Bluegiga APX4 Development Kit

Laxman Dewangan (2):
      ARM: tegra: Pause DMA when reading transfer count
      ARM: tegra: dma: not required to move requestor when stopping.

Lee Jones (11):
      ARM: ux500: pass parent pointer to each platform device
      ARM: ux500: export System-on-Chip information ux500 via sysfs
      ARM: ux500: move top level platform devices in sysfs to /sys/devices/socX
      ARM: ux500: remove intermediary add_platform_device* functions
      ARM: ux500: CONFIG: Enable Device Tree support for future endeavours
      ARM: ux500: db8500: list most devices in the snowball device tree
      ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt Controller) in Device Tree
      ARM: ux500: Enable PL011 AMBA UART Controller for Device Tree
      ARM: ux500: Enable PL310 Level 2 Cache Controller in Device Tree
      ARM: ux500: Enable PL022 SSP Controller in Device Tree
      ARM: ux500: Provide local timer support for Device Tree

Leon Romanovsky (3):
      ARM: dt: tegra: Enable device tree audio codec on PAZ00 board.
      ARM: dt: tegra: Enable headset autodetection on PAZ00 board.
      ASoC: DT: Add digital microphone binding to PAZ00 board.

Linus Walleij (5):
      ARM: plat-nomadik: get rid of global mtu base pointer
      ARM: plat-nomadik: handle clocking properly
      ARM: plat-nomadik: modernize MTU timer
      ARM: ux500: delete TPS6105X selection
      ARM: ux500: solve some Kconfig mess

Lothar Wa?mann (1):
      arm/mxs: Add support for SSP/MMC ports 2 & 3

Magnus Damm (35):
      sh: introduce sh_clk_ops in parallel with clk_ops
      sh: convert cpg code to sh_clk_ops
      ARM: mach-shmobile: sh7367 sh_clk_ops rename
      ARM: mach-shmobile: sh7377 sh_clk_ops rename
      ARM: mach-shmobile: sh7372 sh_clk_ops rename
      ARM: mach-shmobile: sh73a0 sh_clk_ops rename
      ARM: mach-shmobile: r8a7740 sh_clk_ops rename
      ARM: mach-shmobile: r8a7779 sh_clk_ops rename
      sh: sh header sh_clk_ops rename
      sh: sh2 sh_clk_ops rename
      sh: sh2a sh_clk_ops rename
      sh: sh3 sh_clk_ops rename
      sh: sh4 sh_clk_ops rename
      sh: sh4a sh_clk_ops rename
      sh: sh5 sh_clk_ops rename
      sh: board sh_clk_ops rename
      sh: remove clk_ops
      ARM: mach-shmobile: sh7367 map_io and init_early update
      ARM: mach-shmobile: sh7377 map_io and init_early update
      ARM: mach-shmobile: sh7372 map_io and init_early update
      ARM: mach-shmobile: sh73a0 map_io and init_early update
      ARM: mach-shmobile: r8a7740 map_io and init_early update
      ARM: mach-shmobile: r8a7779 map_io and init_early update
      ARM: mach-shmobile: r8a7779 L2 cache support
      ARM: mach-shmobile: rename clk_init() to shmobile_clk_init()
      ARM: mach-shmobile: Move sh7372 Mackerel external clk setup
      ARM: mach-shmobile: Move sh7372 AP4EVB external clk setup
      ARM: mach-shmobile: add shmobile_earlytimer_init()
      ARM: mach-shmobile: sh7367 and G3EVM timer rework
      ARM: mach-shmobile: sh7377 and G4EVM timer rework
      ARM: mach-shmobile: sh7372, AP4EVB and Mackerel timer rework
      ARM: mach-shmobile: sh73a0, AG5EVM and Kota2 timer rework
      ARM: mach-shmobile: r8a7740 and Bonito timer rework
      ARM: mach-shmobile: r8a7779 and Marzen timer rework
      ARM: mach-shmobile: default to no earlytimer

Manjunath Hadli (10):
      ARM: davinci: dm644x: move private definitions to C file
      ARM: davinci: dm365: move private definitions to C file
      ARM: davinci: dm646x: move private definitions to C file
      ARM: davinci: create new common platform header for davinci
      ARM: davinci: streamline sysmod access
      ARM: davinci: dm644x: improve readability using macro
      ARM: davinci: dm644x: fix inconsistent variable naming
      ARM: davinci: dm644x: don't force vpfe registeration on all boards
      ARM: davinci: dm644x: add support for v4l2 video display
      ARM: davinci: dm644x evm: add support for VPBE display

Marc Dietrich (5):
      ARM: tegra: paz00: fix wrong SD1 power gpio
      ARM: tegra: paz00: fix wrong UART port on mini-pcie plug
      ARM: dt: tegra: add ADT7461 temperature sensor to paz00 device tree
      ARM: dt: tegra: add the power gpio key to paz00 device tree
      ARM: dt: tegra: add the wifi led to paz00 device tree

Marc Zyngier (16):
      ARM: smp_twd: make local_timer_stop a symbol instead of a #define
      ARM: local timers: introduce a new registration interface
      ARM: smp_twd: add runtime registration support
      ARM: smp_twd: add device tree support
      ARM: OMAP4: convert to twd_local_timer_register() interface
      ARM: plat-versatile: convert to twd_local_timer_register() interface
      ARM: tegra: convert to twd_local_timer_register() interface
      ARM: shmobile: convert to twd_local_timer_register() interface
      ARM: ux500: convert to twd_local_timer_register() interface
      ARM: highbank: convert to twd_local_timer_register() interface
      ARM: imx6q: convert to twd_local_timer_register() interface
      ARM: smp_twd: remove old local timer interface
      ARM: local timers: convert exynos to runtime registration interface
      ARM: local timers: convert MSM to runtime registration interface
      ARM: local timers: make the runtime registration interface mandatory
      ARM: ux500: fix compilation after local timer rework

Mark Asselstine (1):
      rpmsg: fix build warning when dma_addr_t is 64-bit

Mark Brown (12):
      ARM: S3C64XX: Support GPIO LEDs on Cragganmore
      ARM: S3C64XX: Fix build of Cragganmore after SPI changes
      ARM: S3C64XX: Enable power management for disk on Cragganmore
      ARM: S3C64XX: Enable power management for WiFi on Cragganmore
      ARM: S3C64XX: Add hookup for Tomatin module on Cragganmore
      ARM: S3C64XX: Add basic cpuidle driver
      ARM: S3C64XX: Add a SPKVDD supply for CODECs on Cragganmore
      ARM: S3C64XX: Gate some more clocks by default
      ARM: S3C64XX: Reduce residency requirement for cpuidle WFI mode
      ARM: S3C64XX: Define some additional always off clocks
      ARM: S3C64XX: Add some more Cragganmore module IDs to the table
      ARM: S3C64XX: Supply platform data for SPI on Cragganmore

Mark Grosen (2):
      remoteproc: do not require an iommu
      remoteproc: avoid registering a virtio device if not supported

Masanari Iida (1):
      ARM: OMAP1: Fix typo in lcd_dma.c

Maxim Osipov (1):
      ARM: at91: Add external RTC for Flexibity board

Mehnert (1):
      iomux-mx25.h slew rate adjusted for LCD __LD pins

Mike Turquette (3):
      Documentation: common clk API
      clk: introduce the common clock framework
      clk: basic clock hardware types

Minho Ban (1):
      ARM: SAMSUNG: use spin_lock_irqsave() in clk_{enable,disable}

Mircea Gherzan (1):
      ARM: OMAP: enable Bluetooth on the PandaBoard

MyungJoo Ham (4):
      ARM: EXYNOS: Add DMC1, allow PPMU access for DMC
      PM / devfreq: update the name of EXYNOS clock registers that were omitted
      ARM: EXYNOS: Add clock register addresses for EXYNOS4X12 bus devfreq driver
      ARM: EXYNOS: support Exynos4210-bus Devfreq driver on Nuri board

NeilBrown (2):
      ARM: OMAP2+: UART: remove unused fields in omap_uart_state.
      ARM: OMAP2+: remove some orphan function declarations.

Nicolas Ferre (29):
      Merge remote-tracking branch 'armsoc/depends/rmk/for-armsoc' into at91-3.4-base
      ARM: at91/dma: remove platform data from DMA controller
      ARM: at91/dma: DMA controller registering with DT support
      ARM: at91/at91sam9x5: PMC header file
      ARM: at91/at91sam9x5: clock management for at91sam9x5 chip family
      ARM: at91/at91sam9x5: Configuration and Makefile
      ARM: at91/at91sam9x5: Device tree definition files
      Merge remote-tracking branch 'armsoc/at91/device-board' into at91-3.4-base2
      Merge remote-tracking branch 'armsoc/at91/9x5' into at91-3.4-base2
      ARM: at91/ST: remove not needed casts
      ARM: at91/PMC: move assignment out of printf
      ARM: at91: add at91sam9g25ek.dts in Makefile.boot
      Merge branch 'irqdomain/next' of git://git.secretlab.ca/git/linux-2.6
      ARM: at91/aic: add irq domain and device tree support
      ARM: at91/snapper9260: move gpio_to_irq out of structure initialization
      ARM/USB: at91/ohci-at91: remove the use of irq_to_gpio
      ARM: at91/gpio: change comments and one variable name
      ARM: at91/gpio: add irqdomain and DT support
      ARM: at91/gpio: non-DT builds do not have gpio_chip.of_node field
      ARM: at91/gpio: add .to_irq gpio_chip handler
      ARM: at91/gpio: remove the static specification of gpio_chip.base
      ARM: at91/board-dt: remove AIC irq domain from board file
      ARM: at91: AIC and GPIO IRQ device tree initialization
      ARM: at91/pit: add traces in case of error
      ARM: at91/tclib: take iomem size from resource
      ARM: at91/tc: add device tree support to atmel_tclib
      ARM: at91/tc/clocksource: Add 32 bit variant to Timer Counter
      ARM: at91: add sam9_smc.o to at91sam9x5 build
      ARM: at91/pio: add new PIO3 features

Nishanth Menon (10):
      gpio/omap: save and restore debounce registers
      gpio/omap: enable irq at the end of all configuration in restore
      gpio/omap: restore OE only after setting the output level
      gpio/omap: handle set_dataout reg capable IP on restore
      ARM: OMAP3+: SmartReflex: fix err interrupt disable sequence
      ARM: OMAP3+: SmartReflex Class3: disable errorgen before disable VP
      ARM: OMAP3+: SmartReflex: Add a shutdown hook
      ARM: OMAP3+: SmartReflex: Fix status masking in ERRCONFIG register
      ARM: OMAP3+: SmartReflex: clear ERRCONFIG_VPBOUNDINTST only on a need
      ARM: OMAP3+: hwmod: add SmartReflex IRQs

Ohad Ben-Cohen (30):
      remoteproc: add framework for controlling remote processors
      remoteproc: add debugfs entries
      remoteproc: create rpmsg virtio device
      remoteproc/omap: add a remoteproc driver for OMAP4
      rpmsg: add virtio-based remote processor messaging bus
      samples/rpmsg: add an rpmsg driver sample
      remoteproc: remove unused resource type
      remoteproc/omap: utilize module_platform_driver
      remoteproc: look for truncated firmware images
      remoteproc: add Kconfig menu
      rpmsg: add Kconfig menu
      ARM: OMAP: omap_device: Expose omap_device_{alloc, delete, register}
      remoteproc: depend on EXPERIMENTAL
      rpmsg: depend on EXPERIMENTAL
      remoteproc: don't use virtio's weak barriers
      remoteproc: bail out if firmware has different endianess
      remoteproc: s/big switch/lookup table/
      remoteproc: make sure we're parsing a 32bit firmware
      remoteproc/omap: two Kconfig fixes
      rpmsg: fix name service endpoint leak
      rpmsg: validate incoming message length before propagating
      rpmsg: fix published buffer length in rpmsg_recv_done
      ARM: OMAP: don't build hwspinlock in vain
      remoteproc: resource table overhaul
      remoteproc: remoteproc_rpmsg -> remoteproc_virtio
      remoteproc: safer boot/shutdown order
      remoteproc: remove the single rpmsg vdev limitation
      remoteproc/omap: remove the mbox_callback limitation
      remoteproc: remove the hardcoded vring alignment
      remoteproc: cleanup resource table parsing paths

Ola Lilja (3):
      ARM: ux500: Add placeholder for clk_set_parent
      ARM: ux500: Add DMA-channels for MSP
      ARM: ux500: Add audio-regulators

Olof Johansson (57):
      ARM: tegra: emc: device tree bindings
      ARM: tegra: seaboard: add EMC table to device tree
      ARM: tegra: Don't WARN_ON() for too early dma channel allocations
      ARM: tegra: use APB DMA for accessing APB devices
      ARM: tegra: fuse: use apbio dma for register access
      ARM: tegra: fuse: add functions to access chip revision
      ARM: tegra: fuse: add bct strapping reading
      ARM: tegra: emc: convert tegra2_emc to a platform driver
      ARM: tegra: emc: device tree support
      Merge branch 'ux500-timers' of git://git.kernel.org/.../linusw/linux-stericsson into ux500/timers
      Merge branch 'at91-3.4-base' of git://github.com/at91linux/linux-at91 into next/cleanup
      Merge branch 'at91-3.4-base+pm_cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup
      Merge branch 'at91-3.4-base' of git://github.com/at91linux/linux-at91 into at91/base
      Merge branch 'at91-3.4-base+device_board' of git://github.com/at91linux/linux-at91 into at91/device-board
      Merge branch 'at91-3.4-base+pm_cleanup' of git://github.com/at91linux/linux-at91 into at91/pm_cleanup
      Merge branch 'at91-3.4-base+9x5' of git://github.com/at91linux/linux-at91 into at91/9x5
      Merge branch 'ux500-timers' of git://git.kernel.org/.../linusw/linux-stericsson into next/soc
      Merge branch 'mxs/clk' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
      Merge branch 'mxs/defconfig' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
      Merge branch 'at91-3.4-base+9x5' of git://github.com/at91linux/linux-at91 into next/soc
      Merge branch 'at91-3.4-base+device_board' of git://github.com/at91linux/linux-at91 into next/drivers
      Merge branch 'mxs/boards' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/boards
      Merge branch 'features/imx-clk-prepare' of git://git.pengutronix.de/git/imx/linux-2.6 into next/drivers
      Merge branch 'for-arm-soc' of git://sources.calxeda.com/kernel/linux into next/soc
      Merge branch 'for-3.4/soc' into for-3.4/t30-smp
      Merge branch 'for-3.4/soc-drivers' into for-3.4/t30-smp
      Merge branch 'depends/rmk/for-armsoc' into for-3.4/cleanup-and-fixes
      Merge branch 'cleanup' of git://git.kernel.org/.../tmlind/linux-omap into omap/cleanup
      Merge branch 'fixes-non-critical' of git://git.kernel.org/.../tmlind/linux-omap into next/fixes-non-critical
      Merge branch 'cleanup' of git://git.kernel.org/.../tmlind/linux-omap into next/cleanup
      Merge branch 'next/cleanup-use-static' of git://git.kernel.org/.../kgene/linux-samsung into next/cleanup
      Merge branch 'maintainers' of git://gitorious.org/linux-davinci/linux-davinci into next/maintainers
      Merge branch 'fixes-non-critical-part2' of git://git.kernel.org/.../tmlind/linux-omap into next/fixes-non-critical
      Merge tag 'rpmsg-fixes-and-more-for-3.4' of git://git.kernel.org/.../ohad/remoteproc into next/rpmsg
      Merge branch 'next/cleanup-s3c24xx' of git://git.kernel.org/.../kgene/linux-samsung into next/cleanup
      Merge tag 'imx35-imx5-aips-setup' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc
      Merge branch 'dt' of git://github.com/hzhuang1/linux into next/dt
      Merge branch 'regulator' of git://github.com/hzhuang1/linux into next/drivers
      Merge branch 'rtc' of git://github.com/hzhuang1/linux into next/drivers
      Merge branch 'io-cleanup-for-3.4' of git://sources.calxeda.com/kernel/linux into next/cleanup2
      Merge branch 'fixes-non-critical-part3' of git://git.kernel.org/.../tmlind/linux-omap into next/fixes-non-critical
      Merge branch 'ams-delta' of git://git.kernel.org/.../tmlind/linux-omap into next/boards
      Merge branch 'cleanup-pm' of git://git.kernel.org/.../tmlind/linux-omap into next/cleanup
      Merge branch 'uart' of git://git.kernel.org/.../tmlind/linux-omap into next/cleanup
      Merge branch 'dt-part2' of git://git.kernel.org/.../tmlind/linux-omap into next/dt
      Merge branch 'sr' of git://git.kernel.org/.../tmlind/linux-omap into next/drivers
      Merge branch 'board' of git://git.kernel.org/.../tmlind/linux-omap into next/boards
      Merge branch 'next/devel-samsung' of git://git.kernel.org/.../kgene/linux-samsung into next/soc
      Merge branch 'fix-smsc911x-regulator' of git://git.kernel.org/.../tmlind/linux-omap into fixes
      Merge branch 'next/cleanup-exynos-clock' of git://git.kernel.org/.../kgene/linux-samsung into next/cleanup
      Merge branch 'next/board-samsung' of git://git.kernel.org/.../kgene/linux-samsung into next/boards
      Merge branch 'next/devel-samsung-mmc' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'next/devel-samsung-dma' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'next/devel-samsung-pd' of git://git.kernel.org/.../kgene/linux-samsung into next/drivers
      Merge branch 'soc' of git://git.kernel.org/.../rafael/renesas into next/soc
      Merge branch 'io-cleanup-for-3.4' of git://sources.calxeda.com/kernel/linux into next/cleanup2
      ARM: tegra: update main repo and add patchwork

Paul Parsons (6):
      pxa/hx4700: Correct StrataFlash block size discovery
      pxa/hx4700: Add ASIC3 LED support
      pxa/hx4700: Fix PXA_GPIO_IRQ_BASE/IRQ_NUM values
      ARM: pxa/hx4700: Remove unwanted request for GPIO105
      ARM: pxa/hx4700: Reduce sleep mode battery discharge by 35%
      pxa/hx4700: Remove pcmcia platform_device structure

Paul Walmsley (7):
      ARM: OMAP2+: I2C: always compile I2C reset code, even if I2C driver is not built
      ARM: OMAP2xxx: PM: remove obsolete timer disable code in the suspend path
      ARM: OMAP3: PM: remove superfluous calls to pwrdm_clear_all_prev_pwrst()
      ARM: OMAP2+: PM: clean up omap_set_pwrdm_state()
      ARM: OMAP2+: PM: share clkdms_setup() across OMAP2, 3, 4
      ARM: OMAP2+: omap_device: call all suspend, resume callbacks when OMAP_DEVICE_NO_IDLE_ON_SUSPEND is set
      ARM: OMAP2+: PM: share some suspend-related functions across OMAP2, 3, 4

Pawel Moll (8):
      ARM: vexpress: Get rid of MMIO_P2V
      ARM: versatile: Map local timers using Device Tree when possible
      ARM: vexpress: Use FDT data in platform SMP calls
      ARM: vexpress: Add Device Tree support
      ARM: vexpress: Motherboard RS1 memory map support
      ARM: vexpress: Add Device Tree for V2P-CA5s core tile
      ARM: vexpress: Add Device Tree for V2P-CA9 core tile
      ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)

Peter De Schrijver (20):
      ARM: tegra: add support for tegra30 interrupts
      ARM: tegra: add support for new clock framework features
      ARM: tegra: implement basic tegra30 clock framework
      ARM: tegra: enable tegra30 clock framework
      ARM: tegra: initialize basic system clocks
      ARM: tegra: definitions for flow controller
      ARM: tegra: assembler code for LP3
      ARM: tegra: cpuidle driver for tegra
      ARM: tegra: Avoid compiling cpuidle code when not configured
      ARM: tegra: cleanup use of chipid register
      ARM: tegra: export Tegra chipid
      ARM: tegra: initialize Tegra chipid early
      ARM: tegra: functions to access the flowcontroller
      ARM: tegra: rework Tegra secondary CPU core bringup
      ARM: tegra: prepare powergate.c for multiple variants
      ARM: tegra: export tegra_powergate_is_powered()
      ARM: tegra: add support for Tegra30 powerdomains
      ARM: tegra: support for Tegra30 CPU powerdomains
      ARM: tegra: support for secondary cores on Tegra30
      ARM: tegra: Enable CPUIdle on Tegra20

Peter Ujfalusi (1):
      OMAP4: dma: Correct CPU version check for dma_common_ch_end

Philipp Zabel (1):
      MAINTAINERS: update maintainer entry for pxa/hx4700

Philippe Langlais (2):
      ARM: ux500: set ARCH_NR_GPIO to 355 on U8500 platforms
      ARM: ux500: fix around AB8500 GPIO macro name

Philippe R?tornaz (2):
      mx31moboard: update maintainer
      mx31moboard: Add watchdog support

Richard Zhao (15):
      ARM: mxc: time: add clk_prepare/clk_unprepare
      ARM: mxc: ahci: add clk_prepare/clk_unprepare
      ARM: mxc: pwm: add clk_prepare/clk_unprepare
      ARM: mxc: epit: add clk_prepare/clk_unprepare
      ARM: mxc: arch_reset: add clk_prepare/clk_unprepare
      ARM: mxc: audmux-v2: add clk_prepare/clk_unprepare
      ARM: pm-imx5: add clk_prepare/clk_unprepare
      ARM: mx31moboard: add clk_prepare/clk_unprepare
      serial: imx: add clk_prepare/clk_unprepare
      i2c: imx: add clk_prepare/clk_unprepare
      mmc: sdhci-esdhc-imx: add clk_prepare/clk_unprepare
      ARM: dts: imx6q-sabrelite: add 2p5v and 3p3v regulators
      ARM: dts: imx6q-sabrelite: add sgtl5000 audio codec
      ARM: mxc: make imx_dma_is_general_purpose more generic for sdma
      ARM: imx6q: add cko1 clock

Rob Herring (29):
      ARM: timer-sp: add sched_clock support
      ARM: highbank: enable sp804 based sched_clock
      ARM: highbank: remove unused memory.h
      Merge remote-tracking branch 'arm-soc/at91/base2+cleanup' into cleanup-base
      usb: ohci-pxa27x: add explicit include of hardware.h
      ARM: provide runtime hook for ioremap/iounmap
      ARM: imx: convert to common runtime ioremap hook
      ARM: msm: use runtime ioremap hook
      ARM: iop13xx: use runtime ioremap hook
      ARM: ixp4xx: use runtime ioremap hook
      ARM: ebsa110: use runtime ioremap hook
      ARM: remove compile time __arch_ioremap/__arch_iounmap
      ARM: iop13xx: move io.h externs to pci.h
      ARM: msm: clean-up mach/io.h
      [media] davinci: remove includes of mach/io.h
      ARM: davinci: remove unneeded mach/io.h include
      ARM: orion5x: clean-up mach/io.h
      ARM: tegra: clean-up mach/io.h
      ARM: ep93xx: clean-up mach/io.h
      ARM: at91: add explicit include of hardware.h to uncompressor
      ARM: dove: add explicit include of dove.h to addr-map.c
      ARM: clps711x: remove unneeded include of mach/io.h
      ARM: make mach/io.h include optional
      ARM: remove bunch of now unused mach/io.h files
      ARM: kill off __mem_pci
      ARM: fix ioremap/iounmap for !CONFIG_MMU
      ARM: iop13xx: fix missing declaration of iop13xx_init_early
      ARM: create a common IOMEM definition
      ARM: __io abuse cleanup

Roland Stigge (21):
      ARM: LPC32xx: Added lpc32xx_defconfig
      ARM: LPC32xx: clock.c: warning fix
      ARM: LPC32xx: clock.c: Fix mutex lock issues
      ARM: LPC32XX: Remove broken non-static declaration
      ARM: LPC32xx: clock.c: Missing header file
      ARM: LPC32xx: clock.c: jiffies wrapping
      ARM: LPC32xx: clock.c: Clock registration fixes
      ARM: LPC32xx: Added lpc32xx_defconfig
      ARM: LPC32xx: clock.c: warning fix
      ARM: LPC32xx: clock.c: Fix mutex lock issues
      ARM: LPC32XX: Remove broken non-static declaration
      ARM: LPC32xx: clock.c: Missing header file
      ARM: LPC32xx: clock.c: jiffies wrapping
      ARM: LPC32xx: clock.c: Clock registration fixes
      ARM: LPC32xx: ADC support for mach-lpc32xx
      ARM: LPC32xx: Fix missing and bad LPC32XX macros
      Merge branch 'lpc32xx/fixup' of git://git.kernel.org/.../arm/arm-soc into lpc32xx/tmp
      Merge branch 'lpc32xx/fixup2' of git://git.kernel.org/.../arm/arm-soc into lpc32xx/tmp
      Merge branch 'lpc32xx/drivers' of git://git.kernel.org/.../arm/arm-soc into lpc32xx/tmp
      ARM: LPC32xx: USB Support
      ARM: LPC32xx: Ethernet support

Ryan Mallon (10):
      ep93xx: Move PHYS_BASE defines to local SoC header file
      ep93xx: Don't use system controller defines in audio drivers
      ep93xx: Move GPIO defines to gpio-ep93xx.h
      ep93xx: Use ioremap for backlight driver
      ep93xx: Move peripheral defines to local SoC header
      ep93xx: Configure GPIO ports in core code
      ep93xx: Make syscon access functions private to SoC
      ep93xx: Move crunch code to mach-ep93xx directory
      ep93xx: Move EP93XX_SYSCON defines to SoC private header
      ep93xx: Remove unnecessary includes of ep93xx-regs.h

Sachin Kamat (15):
      ARM: EXYNOS: Enable G2D on ORIGEN
      ARM: S5PV210: Add missing FIMC media device to Aquila
      ARM: EXYNOS: Add missing FIMC media device to SMDKV310
      ARM: EXYNOS: Add missing FIMC media device to Origen
      ARM: EXYNOS: Hook up G2D PD to generic PD infrastructure
      ARM: EXYNOS: Hook up JPEG PD to generic PD infrastructure
      ARM: EXYNOS: Enable G2D on SMDKV310
      ARM: S5PV210: Enable MFC on SMDKV210
      ARM: S5PV210: Enable MFC on SMDKC110
      ARM: S5PV210: Enable FIMC on SMDKV210
      ARM: S5PV210: Enable FIMC on SMDKC110
      ARM: EXYNOS: Enable JPEG on SMDKV310
      ARM: EXYNOS: Enable JPEG on Origen
      ARM: S5PV210: Add JPEG board definition
      ARM: S5PV210: Enable JPEG on SMDKV210

Sangsu Park (3):
      ARM: EXYNOS: add support GPIO for EXYNOS5250
      gpio/samsung: add support GPIOlib for EXYNOS5250
      gpio/samsung: use ioremap() for EXYNOS4 GPIOlib

Sangwook Lee (1):
      ARM: EXYNOS: Enable Bluetooth on ORIGEN

Santosh Shilimkar (2):
      ARM: OMAP: fix section mismatch warning for omap4_hotplug_cpu()
      ARM: OMAP: Fix section mismatch warning for platform_cpu_die()

Sascha Hauer (4):
      ARM i.MX5/6: Add dt support for generic boards
      ARM i.MX27: Add devicetree support
      ARM i.MX: Add phytec phycore-i.MX27 (aka pcm038) devicetree support
      devicetree-bindings: Add documentation for i.MX generic boards

Sekhar Nori (2):
      MAINTAINERS: mark TI DaVinci list as "moderated"
      MAINTAINERS: add TI DaVinci git tree information

Shawn Guo (8):
      ARM: mxs: detect SoC by checking CHIPID register
      ARM: imx5: generate dtbs for imx5 boards
      ARM: dts: imx51-babbage: update mc13892 device
      ARM: dts: imx6q-arm2: add vmmc-supply for usdhc
      ARM: dts: imx6q-sabrelite: add vmmc-supply for usdhc
      MAINTAINERS: remove arch/arm/mach-mx*/ from IMX entry
      ARM: imx: update imx_v6_v7_defconfig
      ARM: defconfig: imx_v6_v7: build in REGULATOR_FIXED_VOLTAGE

Shweta Gulati (1):
      ARM: OMAP3+: SmartReflex: use voltage domain name in device attributes

Simon Glass (3):
      arm: tegra: dts: Support host/device selection and legacy mode
      arm: tegra: dts: Add legacy mode support to Tegra2x USB1 port
      arm: tegra: dts: Mark USB1 as an OTG port on Seaboard

Stefan Roese (1):
      ARM: SPEAr600: Add device-tree support to SPEAr600 boards

Stephen Warren (27):
      dt: tegra gpio: Flesh out binding documentation
      ARM: dt: tegra30.dtsi: Reformat gpio's interrupts property
      ARM: dt: tegra30.dtsi: Add extra GPIO interrupt
      ARM: dt: tegra: Add Tegra APB DMA device tree binding
      ARM: dt: tegra: Modify I2S nodes to match binding
      ARM: dt: tegra: Add labels for I2S controllers
      ARM: dt: tegra: Enable audio on WM8903 boards, disable others
      ARM: dt: Add binding for Tegra PMC
      ARM: tegra: Support Tegra30 in decompressor UART setup
      ARM: tegra: uncompress.h: Choose a UART at runtime
      ARM: tegra: Pass uncompress.h UART selection to DEBUG_LL
      ARM: tegra: Remove use of TEGRA_GPIO_TO_IRQ
      gpio: tegra: Dynamically allocate IRQ base, and support DT
      gpio: tegra: Parameterize the number of banks
      ARM: tegra: Fix EMC pdata initialization from registers
      ARM: tegra: Add a simple PMC driver
      ARM: tegra: Remove duplicate PMU interrupt inversion code
      gpio: tegra: Fix build issue due to irq_domain rework.
      ARM: dt: Add SD controller configuration to Tegra Cardhu
      ARM: tegra: Demote EMC clock inconsistency BUG to WARN
      ARM: tegra: select required CPU and L2 errata options
      ARM: tegra: uncompress.h: Don't depend on kernel headers
      ARM: tegra: match SoC name not board name in DT board files
      ARM: dt: Add ARM PMU to tegra*.dtsi
      ARM: dt: Explicitly configure all serial ports on Tegra Cardhu
      ARM: tegra: update defconfig
      MAINTAINERS: ARM: tegra: update Stephen's email address

Sylwester Nawrocki (4):
      ARM: EXYNOS: Increase virtual framebuffer size on Universal C210 board
      ARM: EXYNOS: Add support for S5K6AAFX image sensor on Universal C210 board
      ARM: SAMSUNG: Add support for S5K6AAFX camera on Nuri board
      ARM: SAMSUNG: Correct MIPI-CSIS io memory resource definition

Tarun Kanti DebBarma (14):
      gpio/omap: handle save/restore context in GPIO driver
      gpio/omap: further cleanup using wkup_en register
      gpio/omap: use level/edge detect reg offsets
      gpio/omap: remove hardcoded offsets in context save/restore
      gpio/omap: cleanup set_gpio_triggering function
      gpio/omap: cleanup omap_gpio_mod_init function
      gpio/omap: remove unnecessary bit-masking for read access
      gpio/omap: use pm-runtime framework
      gpio/omap: optimize suspend and resume functions
      gpio/omap: cleanup prepare_for_idle and resume_after_idle
      gpio/omap: fix debounce clock handling
      gpio/omap: fix incorrect access of debounce module
      gpio/omap: remove omap_gpio_save_context overhead
      ARM: OMAP: dmtimer: fix missing content/correction in low-power mode support

Thierry Reding (1):
      ARM: tegra: PCIe: Provide 3.3V supply voltage

Tony Lindgren (42):
      Merge branch 'omap1-part2' into omap1
      Merge branch 'soc-part2' into soc
      Merge branch 'for_3.4/dt_base' of git://git.kernel.org/.../bcousson/linux-omap-dt into dt
      ARM: OMAP2+: Split omap2_hsmmc_init() to properly support I2C GPIO pins
      ARM: OMAP2+: Set Kconfig dependencies for PROC_DEVICETREE
      ARM: OMAP2+: Fix Kconfig dependencies for USB_ARCH_HAS_EHCI
      ARM: OMAP2+: Fix OMAP_HDQ_BASE build error
      ARM: OMAP2+: Fix board_mux section type conflict when OMAP_MUX is not set
      ARM: OMAP2+: Fix zoom LCD backlight if TWL_CORE is not selected
      ARM: OMAP: Fix devexit for dma when CONFIG_HOTPLUG is not set
      ARM: OMAP2+: Fix multiple randconfig errors with SOC_OMAP and SOC_OMAP_NOOP
      ARM: OMAP2+: Fix devexit for smartreflex when CONFIG_HOTPLUG is not set
      ARM: OMAP2+: Drop DISPC L3 firewall code
      ARM: OMAP2+: Move SDRC related functions from io.h into local common.h
      ARM: OMAP: Move omap_init_consistent_dma_size() to local common.h
      ARM: OMAP1: Move 16xx GPIO system clock to platform init code
      ARM: OMAP1: Move most of plat/io.h into local iomap.h
      ARM: OMAP2+: Move most of plat/io.h into local iomap.h
      ARM: OMAP: Remove plat/io.h by splitting it into mach/io.h and mach/hardware.h
      ARM: OMAP2+: Limit omap_read/write usage to legacy USB drivers
      ARM: OMAP2+: Mark omap_hsmmc_init and omap_mux related functions as __init
      Merge branch 'for_3.4/dts_updates' of git://git.kernel.org/.../bcousson/linux-omap-dt into dt
      Merge branch 'iomap' into cleanup
      Merge branch 'randconfig' into fixes-non-critical
      Merge branch 'hsmmc' into fixes-non-critical
      ARM: OMAP2+: Fix L4_EMU_34XX_BASE error after iomap changes
      Merge branch 'for_3.4/dt_irq_domain' of git://git.kernel.org/.../bcousson/linux-omap-dt into dt-part2
      Merge branch 'omap1' into ams-delta
      ARM: OMAP2+: Fix build error when only ARCH_OMAP2/3 or 4 is selected
      ARM: OMAP2+: Remove extra ifdefs for board-generic
      Merge branch 'for_3.4/cleanup/sr' of git://git.kernel.org/.../khilman/linux-omap-pm into sr
      Revert "ARM: OMAP2+: Fix multiple randconfig errors with SOC_OMAP and SOC_OMAP_NOOP"
      ARM: OMAP1: Fix section mismatch for omap1_init_early()
      ARM: OMAP2+: Fix omap24xx_io_desc warning if SoC subtypes are not selected
      ARM: OMAP2: Fix section warning for n8x0 when CONFIG_MMC_OMAP is not set
      Merge branch 'for_3.4/cleanup/pm' of git://git.kernel.org/.../khilman/linux-omap-pm into cleanup-pm
      Merge branch 'for_3.4/cleanup/uart' of git://git.kernel.org/.../khilman/linux-omap-pm into uart
      ARM: OMAP: Remove remaining includes for mach/io.h
      ARM: OMAP2+: Fix build error after merge
      ARM: OMAP2+: Fix build issues with missing include of linux/bug.h
      ARM: OMAP2+: Fix section warnings for hsmmc_init_one
      ARM: OMAP2+: Fix build for omap4 only builds with missing include of linux/bug.h

Tushar Behera (7):
      ARM: SAMSUNG: Add __init attribute to samsung_bl_set()
      ARM: SAMSUNG: fix __init attribute on regarding s3c_set_platdata()
      ARM: EXYNOS: Add __init attribute to nuri_camera_init()
      ARM: EXYNOS: Add __init attribute to universal_camera_init()
      ARM: EXYNOS: Add apb_pclk clkdev entry for mdma1
      ARM: EXYNOS: Add clkdev lookup entry for lcd clock
      ARM: EXYNOS: Fix compilation error with mach-exynos4-dt board

Uwe Kleine-K?nig (3):
      ARM: OMAP4: board-4430sdp: don't initialize value that is never used
      ARM: davinci: cpufreq: fix compiler warning
      ARM: davinci: DA850: move da850_register_pm to .init.text

Vaibhav Bedia (1):
      ARM: OMAP: sram: Add am33xx SRAM support (minimal)

Vaibhav Hiremath (3):
      ARM: OMAP2+: Make cpu_rev static global variable
      ARM: OMAP2+: split omap2/3/4_check_revision function
      arm/dts: Add support for TI OMAP3 EVM board

Vladimir Zapolskiy (1):
      ARM: OMAP3: RX-51: add explicit mux configuration of tsc2005 control gpios

Wolfram Sang (4):
      ARM: mx28: check for gated clocks when setting saif divider
      ARM: mxs: read correct values when setting up MAC
      arm: lpc32xx: phy3250: add rtc & touch device
      arm: lpc32xx: phy3250: add rtc & touch device

Yuan Jiangli (1):
      ARM: OMAP3+: PM: VP: fix integer truncation error

wu guoxing (1):
      ARM : mx35: 3ds-board: add framebuffer device



From jason at lakedaemon.net  Sun Mar 25 11:05:14 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 25 Mar 2012 11:05:14 -0400
Subject: [PATCH V2 1/3] ARM: kirkwood: Basic support for DNS-320 and
 DNS-325
In-Reply-To: <201203241926.00597.arnd@arndb.de>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <1332594876-8673-2-git-send-email-jm@lentin.co.uk>
 <201203241926.00597.arnd@arndb.de>
Message-ID: <20120325150514.GP2484@titan.lakedaemon.net>

On Sat, Mar 24, 2012 at 07:26:00PM +0000, Arnd Bergmann wrote:
> On Saturday 24 March 2012, Jamie Lentin wrote:
> > 
> > Add support for the DNS-320 and DNS-325. Describe as much as currently possible
> > in the devicetree files, create a board-dnskw.c for everything else.
> > 
> > Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> 
> Looks good to me. 

Me as well.  Jamie, if you could just incorporate the
orion_nand/kirkwood split and then resubmit (don't forget the acks),
I'll pull them in.

> Jason, do you want to add these to your tree? You are already have some
> the patches for dreamplug, and I think it makes sense to update these two
> together when you have more patches.

Will do.

> Since the dnskw board file contains mostly gpio setup, I think it would
> be good if one of you could take that part on next: once the gpio controller
> uses DT probing, you can move all the gpio leds and buttons into the
> device tree, which drastically shrinks the dnskw file.

Agreed.  Jamie, would you mind working on that while I work on the irq
controller?

Other than my one comment about the patch split, please consider this
series:

Acked-by: Jason Cooper <jason at lakedaemon.net>

thx,

Jason.

> 
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> 
> 	Arnd


From jason at lakedaemon.net  Sun Mar 25 10:57:44 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sun, 25 Mar 2012 10:57:44 -0400
Subject: [PATCH V3 2/3] ARM: kirkwood: Convert orion-nand to fdt
In-Reply-To: <alpine.DEB.2.02.1203250012060.8994@gonzo>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <1332594876-8673-3-git-send-email-jm@lentin.co.uk>
 <201203241901.00405.arnd@arndb.de>
 <alpine.DEB.2.02.1203250012060.8994@gonzo>
Message-ID: <20120325145744.GO2484@titan.lakedaemon.net>

On Sun, Mar 25, 2012 at 12:17:24AM +0000, Jamie Lentin wrote:
> Convert orion-nand to use fdt and add common setup to kirkwood.dtsi, including
> a default value for chip-delay (all current boards seem to use 25 anyway).
> 
> Add placeholder documentation for the bindings, for someone more knowledgable
> than me to fill in the details of the properties.
> 
> Move common partition table documentation into a separate file and reference
> this.

Jamie,

This looks great!  In addition to Arnd's comments, could you split this
into two?  The orion_nand dt bindings work, and kirkwood making use of
it?  It's not earth-shattering, but it helps folks on orion5x/dove/etc
pull it in and try it without worrying about kirkwood.

> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> ---
> Re-arranged documentation as you suggest, however it's tempting to
> have this as a separate patch and add references to partition.txt
> for the other binding documentation files. Let me know if you want
> me to do this.

If it's not too much trouble, this would be appreciated.

thx,

Jason.

> Cheers for your help!
> 
>  .../devicetree/bindings/mtd/mtd-physmap.txt        |   24 +--------
>  .../devicetree/bindings/mtd/orion-nand.txt         |   50 ++++++++++++++++++++
>  .../devicetree/bindings/mtd/partition.txt          |   38 +++++++++++++++
>  arch/arm/boot/dts/kirkwood.dtsi                    |   15 ++++++-
>  arch/arm/mach-kirkwood/common.c                    |   12 +++++
>  drivers/mtd/nand/orion_nand.c                      |   34 +++++++++++++-
>  6 files changed, 149 insertions(+), 24 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt
>  create mode 100644 Documentation/devicetree/bindings/mtd/partition.txt
> 
> diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
> index 80152cb..9b873d4 100644
> --- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
> +++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
> @@ -23,27 +23,9 @@ are defined:
>   - vendor-id : Contains the flash chip's vendor id (1 byte).
>   - device-id : Contains the flash chip's device id (1 byte).
> 
> -In addition to the information on the mtd bank itself, the
> -device tree may optionally contain additional information
> -describing partitions of the address space.  This can be
> -used on platforms which have strong conventions about which
> -portions of a flash are used for what purposes, but which don't
> -use an on-flash partition table such as RedBoot.
> -
> -Each partition is represented as a sub-node of the mtd device.
> -Each node's name represents the name of the corresponding
> -partition of the mtd device.
> -
> -Flash partitions
> - - reg : The partition's offset and size within the mtd bank.
> - - label : (optional) The label / name for this partition.
> -   If omitted, the label is taken from the node name (excluding
> -   the unit address).
> - - read-only : (optional) This parameter, if present, is a hint to
> -   Linux that this partition should only be mounted
> -   read-only.  This is usually used for flash partitions
> -   containing early-boot firmware images or data which should not
> -   be clobbered.
> +In addition to the information on the mtd bank itself, the device tree may
> +optionally contain additional sub-nodes describing partitions of the address
> +space. See partition.txt for more detail.
> 
>  Example:
> 
> diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
> new file mode 100644
> index 0000000..e9acbd2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/orion-nand.txt
> @@ -0,0 +1,50 @@
> +NAND support for Marvell Orion SoC platforms
> +
> +Required properties:
> +- compatible : "mrvl,orion-nand".
> +- reg : Base physical address of the NAND and length of memory mapped
> +	region
> +
> +Optional properties:
> +- cle :
> +- ale :
> +- bank-width :
> +- chip-delay :
> +
> +In addition to the information on the mtd bank itself, the device tree may
> +optionally contain additional sub-nodes describing partitions of the address
> +space. See partition.txt for more detail.
> +
> +Examples:
> +
> +nand at f4000000 {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	cle = <0>;
> +	ale = <1>;
> +	bank-width = <8>;
> +	chip-delay = <25>;
> +	compatible = "mrvl,orion-nand";
> +	reg = <0xf4000000 0x400>;
> +
> +	partition at 0 {
> +		label = "u-boot";
> +		reg = <0x0000000 0x100000>;
> +		read-only;
> +	};
> +
> +	partition at 100000 {
> +		label = "uImage";
> +		reg = <0x0100000 0x200000>;
> +	};
> +
> +	partition at 300000 {
> +		label = "dtb";
> +		reg = <0x0300000 0x100000>;
> +	};
> +
> +	partition at 400000 {
> +		label = "root";
> +		reg = <0x0400000 0x7d00000>;
> +	};
> +};
> diff --git a/Documentation/devicetree/bindings/mtd/partition.txt b/Documentation/devicetree/bindings/mtd/partition.txt
> new file mode 100644
> index 0000000..f114ce1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/partition.txt
> @@ -0,0 +1,38 @@
> +Representing flash partitions in devicetree
> +
> +Partitions can be represented by sub-nodes of an mtd device. This can be used
> +on platforms which have strong conventions about which portions of a flash are
> +used for what purposes, but which don't use an on-flash partition table such
> +as RedBoot.
> +
> +#address-cells & #size-cells must both be present in the mtd device and be
> +equal to 1.
> +
> +Required properties:
> +- reg : The partition's offset and size within the mtd bank.
> +
> +Optional properties:
> +- label : The label / name for this partition.  If omitted, the label is taken
> +  from the node name (excluding the unit address).
> +- read-only : This parameter, if present, is a hint to Linux that this
> +  partition should only be mounted read-only. This is usually used for flash
> +  partitions containing early-boot firmware images or data which should not be
> +  clobbered.
> +
> +Examples:
> +
> +
> +flash at 0 {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	partition at 0 {
> +		label = "u-boot";
> +		reg = <0x0000000 0x100000>;
> +		read-only;
> +	};
> +
> +	uimage at 100000 {
> +		reg = <0x0100000 0x200000>;
> +	};
> +];
> diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
> index 3474ef8..6b80374 100644
> --- a/arch/arm/boot/dts/kirkwood.dtsi
> +++ b/arch/arm/boot/dts/kirkwood.dtsi
> @@ -5,7 +5,7 @@
> 
>  	ocp at f1000000 {
>  		compatible = "simple-bus";
> -		ranges = <0 0xf1000000 0x1000000>;
> +		ranges = <0 0xf1000000 0x4000000>;
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> 
> @@ -32,5 +32,18 @@
>  			reg = <0x10300 0x20>;
>  			interrupts = <53>;
>  		};
> +
> +		nand at 3000000 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			cle = <0>;
> +			ale = <1>;
> +			bank-width = <8>;
> +			compatible = "mrvl,orion-nand";
> +			reg = <0x3000000 0x400>;
> +			chip-delay = <25>;
> +			/* set partition map and/or chip-delay in board dts */
> +			status = "disabled";
> +		};
>  	};
>  };
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index a02cae8..3ad0373 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -15,6 +15,7 @@
>  #include <linux/ata_platform.h>
>  #include <linux/mtd/nand.h>
>  #include <linux/dma-mapping.h>
> +#include <linux/of.h>
>  #include <net/dsa.h>
>  #include <asm/page.h>
>  #include <asm/timex.h>
> @@ -482,6 +483,9 @@ static int __init kirkwood_clock_gate(void)
>  	unsigned int curr = readl(CLOCK_GATING_CTRL);
>  	u32 dev, rev;
> 
> +#ifdef CONFIG_OF
> +	struct device_node *np;
> +#endif
>  	kirkwood_pcie_id(&dev, &rev);
>  	printk(KERN_DEBUG "Gating clock of unused units\n");
>  	printk(KERN_DEBUG "before: 0x%08x\n", curr);
> @@ -489,6 +493,14 @@ static int __init kirkwood_clock_gate(void)
>  	/* Make sure those units are accessible */
>  	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
> 
> +#ifdef CONFIG_OF
> +	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-nand");
> +	if (np && of_device_is_available(np)) {
> +		kirkwood_clk_ctrl |= CGC_RUNIT;
> +		of_node_put(np);
> +	}
> +#endif
> +
>  	/* For SATA: first shutdown the phy */
>  	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
>  		/* Disable PLL and IVREF */
> diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
> index 29f505a..6a5f47b 100644
> --- a/drivers/mtd/nand/orion_nand.c
> +++ b/drivers/mtd/nand/orion_nand.c
> @@ -13,6 +13,7 @@
>  #include <linux/slab.h>
>  #include <linux/module.h>
>  #include <linux/platform_device.h>
> +#include <linux/of.h>
>  #include <linux/mtd/mtd.h>
>  #include <linux/mtd/nand.h>
>  #include <linux/mtd/partitions.h>
> @@ -74,11 +75,13 @@ static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>  static int __init orion_nand_probe(struct platform_device *pdev)
>  {
>  	struct mtd_info *mtd;
> +	struct mtd_part_parser_data ppdata = {};
>  	struct nand_chip *nc;
>  	struct orion_nand_data *board;
>  	struct resource *res;
>  	void __iomem *io_base;
>  	int ret = 0;
> +	u32 val = 0;
> 
>  	nc = kzalloc(sizeof(struct nand_chip) + sizeof(struct mtd_info), GFP_KERNEL);
>  	if (!nc) {
> @@ -101,7 +104,25 @@ static int __init orion_nand_probe(struct platform_device *pdev)
>  		goto no_res;
>  	}
> 
> -	board = pdev->dev.platform_data;
> +	if (pdev->dev.of_node) {
> +		board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data),
> +					GFP_KERNEL);
> +		if (!board) {
> +			printk(KERN_ERR "orion_nand: failed to allocate board structure.\n");
> +			ret = -ENOMEM;
> +			goto no_res;
> +		}
> +		if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
> +			board->cle = (u8)val;
> +		if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
> +			board->ale = (u8)val;
> +		if (!of_property_read_u32(pdev->dev.of_node, "bank-width", &val))
> +			board->width = (u8)val;
> +		if (!of_property_read_u32(pdev->dev.of_node,
> +						"chip-delay", &val))
> +			board->chip_delay = (u8)val;
> +	} else
> +		board = pdev->dev.platform_data;
> 
>  	mtd->priv = nc;
>  	mtd->owner = THIS_MODULE;
> @@ -129,7 +150,8 @@ static int __init orion_nand_probe(struct platform_device *pdev)
>  	}
> 
>  	mtd->name = "orion_nand";
> -	ret = mtd_device_parse_register(mtd, NULL, 0,
> +	ppdata.of_node = pdev->dev.of_node;
> +	ret = mtd_device_parse_register(mtd, NULL, &ppdata,
>  			board->parts, board->nr_parts);
>  	if (ret) {
>  		nand_release(mtd);
> @@ -161,11 +183,19 @@ static int __devexit orion_nand_remove(struct platform_device *pdev)
>  	return 0;
>  }
> 
> +#ifdef CONFIG_OF
> +static struct of_device_id orion_nand_of_match_table[] = {
> +	{ .compatible = "mrvl,orion-nand", },
> +	{},
> +};
> +#endif
> +
>  static struct platform_driver orion_nand_driver = {
>  	.remove		= __devexit_p(orion_nand_remove),
>  	.driver		= {
>  		.name	= "orion_nand",
>  		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(orion_nand_of_match_table),
>  	},
>  };
> 
> -- 
> 1.7.9.1


From arnd at arndb.de  Sun Mar 25 13:34:41 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Sun, 25 Mar 2012 17:34:41 +0000
Subject: ioremap to a specific virtual address
In-Reply-To: <CAKON4OwhcFDMC4dWjU7x4u2CPT7C2BxVuCDkTN0j14gTndi3tA@mail.gmail.com>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <201203231931.06376.arnd@arndb.de>
 <CAKON4OwhcFDMC4dWjU7x4u2CPT7C2BxVuCDkTN0j14gTndi3tA@mail.gmail.com>
Message-ID: <201203251734.41780.arnd@arndb.de>

On Saturday 24 March 2012, jonsmirl at gmail.com wrote:
> The dm9000 is on the LPC3131 reference design board. It is not our
> hardware so I'm not sure what it is doing with the GPIO pin. I'm
> porting the reference board code in the hopes that someone will help
> out in this effort.

Ok, so it's possible that nobody knows why the gpio read was put
in then and it might be completely bogus?

> Another piece of board specific glue is this bit that needs to be
> executed before accessing the dm9000. It puts the bus in the board's
> range in 8/16/32b mode, timings, etc.
> 
> static void __init ea_add_device_dm9000(void)
> {
>         /*
>          * Configure Chip-Select 2 on SMC for the DM9000.
>          * Note: These timings were calculated for MASTER_CLOCK = 90000000
>          *  according to the DM9000 timings.
>          */
>         MPMC_STCONFIG1 = 0x81;
>         MPMC_STWTWEN1 = 1;
>         MPMC_STWTOEN1 = 1;
>         MPMC_STWTRD1 = 4;
>         MPMC_STWTPG1 = 1;
>         MPMC_STWTWR1 = 1;
>         MPMC_STWTTURN1 = 2;
>         /* enable oe toggle between consec reads */
>         SYS_MPMC_WTD_DEL1 = _BIT(5) | 4;
> 

I would try to describe the MPMC static memory configuration using a device
node containing these, if you can't reliably move the configuration into the
boot loader itself.

In the device tree, this can look like:

/ {

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mpmc at 17008200 {
			compatible = "nxp,lpc31xx-mpmc";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x20000000 0x20000>; /* map to sram0 */
			reg = <0x17008200 0x20>;
			status = "disabled"; /* unused here */
		};

		mpmc at 17008220 {
			compatible = "nxp,lpc31xx-mpmc";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x20020000 0x20000>; /* map to sram1 */
			reg = <0x17008220 0x20>;

			/* mpmc configuration */
			mpmc-static-config     = <0x81>;
			mpmc-static-wait-wen   = <1>;
			mpmc-static-wait-oen   = <1>;
			mpmc-static-wait-rd    = <4>;
			mpmc-static-wait-page  = <1>;
			mpmc-static-wait-write = <1>;
			mpmc-static-wait-turn  = <2>;

			ethernet at 20020000 {
				compatible = "davicom,dm9000";
				reg = <0 100  10000 100>; /* local address */
				interrupts = <0x1>; /* ??? */
				gpios = <&gpio-i2stx 0>;
			}
		};
	};
};

This means you will need a driver for mpmc, but since all its code is only
run at boot time, it can live entirely in the init section.

	Arnd


From oleg at redhat.com  Sun Mar 25 13:42:10 2012
From: oleg at redhat.com (Oleg Nesterov)
Date: Sun, 25 Mar 2012 19:42:10 +0200
Subject: [PATCH v2.1 01/10] cpu: Introduce clear_tasks_mm_cpumask() helper
In-Reply-To: <20120324164316.GB3640@lizard>
References: <20120324102609.GA28356@lizard> <20120324102751.GA29067@lizard>
 <1332593021.16159.27.camel@twins> <20120324164316.GB3640@lizard>
Message-ID: <20120325174210.GA23605@redhat.com>

On 03/24, Anton Vorontsov wrote:
>
> Many architctures clear tasks' mm_cpumask like this:
>
> 	read_lock(&tasklist_lock);
> 	for_each_process(p) {
> 		if (p->mm)
> 			cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
> 	}
> 	read_unlock(&tasklist_lock);

Namely arm, powerpc, and sh.

> The code above has several problems, such as:
>
> 1. Working with task->mm w/o getting mm or grabing the task lock is
>    dangerous as ->mm might disappear (exit_mm() assigns NULL under
>    task_lock(), so tasklist lock is not enough).

This is not actually true for arm and sh, afaics. They do not even
need tasklist or rcu lock for for_each_process().

__cpu_disable() is called by __stop_machine(), we know that nobody
can preempt us and other CPUs can do nothing.

> 2. Checking for process->mm is not enough because process' main
>    thread may exit or detach its mm via use_mm(), but other threads
>    may still have a valid mm.

Yes,

> Also, Per Peter Zijlstra's idea, now we don't grab tasklist_lock in
> the new helper, instead we take the rcu read lock. We can do this
> because the function is called after the cpu is taken down and marked
> offline, so no new tasks will get this cpu set in their mm mask.

And only powerpc needs rcu_read_lock() and task_lock().

OTOH, I do not understand why powepc does this on CPU_DEAD...
And probably CPU_UP_CANCELED doesn't need to clear mm_cpumask().

That said, personally I think these patches are fine, the common
helper makes sense.

Oleg.



From pwaechtler at mac.com  Sun Mar 25 14:22:05 2012
From: pwaechtler at mac.com (Peter Waechtler)
Date: Sun, 25 Mar 2012 20:22:05 +0200
Subject: ARM11MPcore: tlb_ops_need_broadcast causes deadlock
In-Reply-To: <20120325130912.GF5611@n2100.arm.linux.org.uk>
References: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
 <20120323173055.GC16225@mudshark.cambridge.arm.com>
 <loom.20120325T135816-592@post.gmane.org>
 <20120325130912.GF5611@n2100.arm.linux.org.uk>
Message-ID: <4F6F624D.8060409@mac.com>

On 25.03.2012 15:09, Russell King - ARM Linux wrote:
> On Sun, Mar 25, 2012 at 12:08:47PM +0000, Peter Waechtler wrote:
>> But Will, is that tlb_flush necessary at all? The ARM has only 3 permission
>> bits in the page table (APX and AP0 and AP1). The young/accessed bit is done
>> via software.
> Yes it most definitely is, because setting a page to be young means we
> must receive a subsequent fault to make it 'old' again.  This means we
> must set the page to be inaccessible to get that fault, and flush the
> TLBs across all CPUs so that any CPU accessing that page receives a
> fault.
Ok I see, it's also not the "right or perfect" fix.

But the worst thing that can happen is:

young page: causes no page fault anymore and stays longer young than
kswapd wants in case a TLB has a stale entry but that access would have
marked it young again - no big deal?

old page: causes a page fault so that it can be made young, a stale TLB
would cause still a page fault - but in that path the tlb_flush still 
happens

 From my point of view: I definitively prefer to avoid the deadlock ;)

I'm afraid that I missed something? I hope not :)

     Peter



From linux at arm.linux.org.uk  Sun Mar 25 15:15:57 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 25 Mar 2012 20:15:57 +0100
Subject: ARM11MPcore: tlb_ops_need_broadcast causes deadlock
In-Reply-To: <4F6F624D.8060409@mac.com>
References: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
 <20120323173055.GC16225@mudshark.cambridge.arm.com>
 <loom.20120325T135816-592@post.gmane.org>
 <20120325130912.GF5611@n2100.arm.linux.org.uk> <4F6F624D.8060409@mac.com>
Message-ID: <20120325191556.GA3147@n2100.arm.linux.org.uk>

On Sun, Mar 25, 2012 at 08:22:05PM +0200, Peter Waechtler wrote:
> On 25.03.2012 15:09, Russell King - ARM Linux wrote:
>> On Sun, Mar 25, 2012 at 12:08:47PM +0000, Peter Waechtler wrote:
>>> But Will, is that tlb_flush necessary at all? The ARM has only 3 permission
>>> bits in the page table (APX and AP0 and AP1). The young/accessed bit is done
>>> via software.
>> Yes it most definitely is, because setting a page to be young means we
>> must receive a subsequent fault to make it 'old' again.  This means we
>> must set the page to be inaccessible to get that fault, and flush the
>> TLBs across all CPUs so that any CPU accessing that page receives a
>> fault.
> Ok I see, it's also not the "right or perfect" fix.

It's not a fix or anything, it's required behaviour - otherwise we could
end up throwing out pages from the system which are actually 'hot' because
they've stayed in the TLB and we haven't received a fault to make them
young again.

Moreover, what about the case where we actually remove the page?

Aren't we also holding the pte lock there?  So I don't think there's an
obvious solution to your deadlock.

I think the real question is - in your example - why are you touching
a userspace page with IRQs off _and_ expecting the fault to be fixed up?
You never really explained what CPU B was doing.


From pwaechtler at mac.com  Sun Mar 25 16:22:49 2012
From: pwaechtler at mac.com (Peter Waechtler)
Date: Sun, 25 Mar 2012 22:22:49 +0200
Subject: ARM11MPcore: tlb_ops_need_broadcast causes deadlock
In-Reply-To: <20120325191556.GA3147@n2100.arm.linux.org.uk>
References: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
 <20120323173055.GC16225@mudshark.cambridge.arm.com>
 <loom.20120325T135816-592@post.gmane.org>
 <20120325130912.GF5611@n2100.arm.linux.org.uk> <4F6F624D.8060409@mac.com>
 <20120325191556.GA3147@n2100.arm.linux.org.uk>
Message-ID: <4F6F7E99.1020500@mac.com>

On 25.03.2012 21:15, Russell King - ARM Linux wrote:
> On Sun, Mar 25, 2012 at 08:22:05PM +0200, Peter Waechtler wrote:
>> On 25.03.2012 15:09, Russell King - ARM Linux wrote:
>>> On Sun, Mar 25, 2012 at 12:08:47PM +0000, Peter Waechtler wrote:
>>>> But Will, is that tlb_flush necessary at all? The ARM has only 3 permission
>>>> bits in the page table (APX and AP0 and AP1). The young/accessed bit is done
>>>> via software.
>>> Yes it most definitely is, because setting a page to be young means we
>>> must receive a subsequent fault to make it 'old' again.  This means we
>>> must set the page to be inaccessible to get that fault, and flush the
>>> TLBs across all CPUs so that any CPU accessing that page receives a
>>> fault.
>> Ok I see, it's also not the "right or perfect" fix.
> It's not a fix or anything, it's required behaviour - otherwise we could
> end up throwing out pages from the system which are actually 'hot' because
> they've stayed in the TLB and we haven't received a fault to make them
> young again.

I'm arguing solely on kswapd making a young page old. So it can't be a 
hot page.
But yes in theory it's possible that it just become hot on another cpu...

And again I don't understand the abort handler: why do we get a page 
fault on
a young page then? grrh

> Moreover, what about the case where we actually remove the page?
I don't claim that this is the only way to deadlock - but this is the 
case we encounter.

> Aren't we also holding the pte lock there?  So I don't think there's an
> obvious solution to your deadlock.
>
> I think the real question is - in your example - why are you touching
> a userspace page with IRQs off _and_ expecting the fault to be fixed up?
> You never really explained what CPU B was doing.
It was running some user space program. It was not in the kernel.
I will post the jtag probe screenshots tomorrow.

     Peter





From linux at arm.linux.org.uk  Sun Mar 25 17:55:35 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sun, 25 Mar 2012 22:55:35 +0100
Subject: ARM11MPcore: tlb_ops_need_broadcast causes deadlock
In-Reply-To: <4F6F7E99.1020500@mac.com>
References: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
 <20120323173055.GC16225@mudshark.cambridge.arm.com>
 <loom.20120325T135816-592@post.gmane.org>
 <20120325130912.GF5611@n2100.arm.linux.org.uk> <4F6F624D.8060409@mac.com>
 <20120325191556.GA3147@n2100.arm.linux.org.uk> <4F6F7E99.1020500@mac.com>
Message-ID: <20120325215535.GB3147@n2100.arm.linux.org.uk>

On Sun, Mar 25, 2012 at 10:22:49PM +0200, Peter Waechtler wrote:
> On 25.03.2012 21:15, Russell King - ARM Linux wrote:
>> On Sun, Mar 25, 2012 at 08:22:05PM +0200, Peter Waechtler wrote:
>>> On 25.03.2012 15:09, Russell King - ARM Linux wrote:
>>>> On Sun, Mar 25, 2012 at 12:08:47PM +0000, Peter Waechtler wrote:
>>>>> But Will, is that tlb_flush necessary at all? The ARM has only 3 permission
>>>>> bits in the page table (APX and AP0 and AP1). The young/accessed bit is done
>>>>> via software.
>>>> Yes it most definitely is, because setting a page to be young means we
>>>> must receive a subsequent fault to make it 'old' again.  This means we
>>>> must set the page to be inaccessible to get that fault, and flush the
>>>> TLBs across all CPUs so that any CPU accessing that page receives a
>>>> fault.
>>> Ok I see, it's also not the "right or perfect" fix.
>> It's not a fix or anything, it's required behaviour - otherwise we could
>> end up throwing out pages from the system which are actually 'hot' because
>> they've stayed in the TLB and we haven't received a fault to make them
>> young again.
>
> I'm arguing solely on kswapd making a young page old. So it can't be a  
> hot page.

No, it can be a hot page because the way it finds out that it's a hot
page is when it has to make the page repeatedly young, having first
made it old.

There's no other way the system can know what pages are being accessed
by userspace.

> But yes in theory it's possible that it just become hot on another cpu...
>
> And again I don't understand the abort handler: why do we get a page  
> fault on
> a young page then? grrh

Permissions?  Userspace trying to write to the page when it isn't marked
writable and dirty?

>> Moreover, what about the case where we actually remove the page?
> I don't claim that this is the only way to deadlock - but this is the  
> case we encounter.

No, but you're arguing that we drop the TLB flush for your specific case.
I'm telling you that's pointless if there's other cases as well which
we'll deadlock.

But that's neither here nor there because you haven't fully explained
what the problem is yet...

>> Aren't we also holding the pte lock there?  So I don't think there's an
>> obvious solution to your deadlock.
>>
>> I think the real question is - in your example - why are you touching
>> a userspace page with IRQs off _and_ expecting the fault to be fixed up?
>> You never really explained what CPU B was doing.
> It was running some user space program. It was not in the kernel.
> I will post the jtag probe screenshots tomorrow.

Why do we need silly screen shots, why can't you explain it, or paste
the output?  I'm not going to bother looking at GIFs, PNGs or jpegs
because my mail reader is text only.

Moreover, user space programs can't disable interrupts.  So you should
not be receiving a data abort from userspace with interrupts disabled.
Yes, when the CPU enters the data abort handler, it will disable
interrupts, but we re-enable them before processing the abort.


From jonathan at jonmasters.org  Sun Mar 25 19:59:44 2012
From: jonathan at jonmasters.org (Jon Masters)
Date: Sun, 25 Mar 2012 19:59:44 -0400
Subject: Inconsistent kallsyms data on ARM.
In-Reply-To: <20120325112035.GE5611@n2100.arm.linux.org.uk>
References: <CAP=VYLoStscdVJretZ-Rkbp7V3Vsm8N0oWcjih7ruHFiDN7CiA@mail.gmail.com>
 <201203141321.47010.arnd@arndb.de>
 <20120325112035.GE5611@n2100.arm.linux.org.uk>
Message-ID: <4F6FB170.1040109@jonmasters.org>

On 03/25/2012 07:20 AM, Russell King - ARM Linux wrote:
> On Wed, Mar 14, 2012 at 01:21:46PM +0000, Arnd Bergmann wrote:
>> On Tuesday 13 March 2012, Paul Gortmaker wrote:
>>> This bug(?)  has been seen to float from one ARM build to another since
>>> I started tracking the day-to-day changes in Stephen's linux-next builds.
>>>
>>> I see it was discussed earlier:
>>>
>>>    https://lkml.org/lkml/2011/8/2/233
>>>    https://lkml.org/lkml/2011/10/8/70
>>>
>>> but no concrete cause was nailed down.  Can the linux-next build results
>>> help shed some light on this in any way?  Since it seems sporadic, is
>>> there value in embedding a diagnostic of some sort in the infrastructure
>>> so that when the error is detected, that it prints out more detailed info?
>>>
>>> I can provide links to failed linux-next builds, but at the moment, all they
>>> really seem to have is the same repeated error message, like this one:
>>>
>>>    http://kisskb.ellerman.id.au/kisskb/buildresult/5869367/
>>>
>>> and I don't see that helping folks all that much....
>>>
>>
>> I'm sure I can reproduce it if necessary, but I need to know what to
>> look for to find out what the problem is.
> 
> Right, last night's omap3430ldp build failed because of this, so I've
> re-run the build and taken a look at what's happened:
> 
> $ arm-linux-nm -n .tmp_vmlinux1 > vm1.syms
> $ arm-linux-nm -n .tmp_vmlinux2 > vm2.syms
> $ arm-linux-nm -n vmlinux > vm3.syms
> $ diff -u <(sed s,^...........,, vm2.syms) <(sed s,^...........,, vm3.syms) 
> $
> 
> .tmp_vmlinux1 is the vmlinux file with no kallsyms data.  .tmp_vmlinux2 is
> the vmlinux file with kallsyms data generated from the first image.
> vmlinux is the vmlinux file with kallsyms data generated from the second
> image.
> 
> What the above shows is that we have the same symbols in the same order
> in the second and third stage.  However:
> 
> $ diff -u vm2.syms vm3.syms
> ...
>  c0352900 R kallsyms_names
> -c03acd00 R kallsyms_markers
> -c03acf10 R kallsyms_token_table
> -c03ad290 R kallsyms_token_index
> ...
> +c03accf0 R kallsyms_markers
> +c03acf00 R kallsyms_token_table
> +c03ad280 R kallsyms_token_index
> 
> So, the size of the kallsyms names has changed.
> 
> Now, looking at the differences between stage 1 and stage 2:
> 
> @@ -1,9 +1,3 @@
> -kallsyms_addresses
> -kallsyms_markers
> -kallsyms_names
> -kallsyms_num_syms
> -kallsyms_token_index
> -kallsyms_token_table
>  syscalls_padding
>  cpu_v7_suspend_size
>  NR_syscalls
> @@ -17151,6 +17145,12 @@
>  rpc_info_operations
>  svc_pool_stats_seq_ops
>  rpc_proc_fops
> +kallsyms_addresses
> +kallsyms_num_syms
> +kallsyms_names
> +kallsyms_markers
> +kallsyms_token_table
> +kallsyms_token_index
>  __end_builtin_fw
>  __end_pci_fixups_early
>  __end_pci_fixups_enable
> @@ -28372,11 +28372,11 @@
>  __security_initcall_start
>  __initramfs_size
>  __irf_end
> -__data_loc
>  __init_end
>  __per_cpu_end
>  __per_cpu_load
>  __per_cpu_start
> +__data_loc
>  _data
>  _sdata
>  init_thread_union
> 
> 
> The difference in placement for the kallsyms symbols is more or less
> expected, because these appear as weak symbols in stage 1.  However,
> notice that __data_loc has moved in relative position.
> 
> As the names are compressed, this causes the size of the kallsyms name
> data to change size (because we end up with a different compression)
> which then causes the subsequent kallsyms data and other read-only data
> to move.  This then causes 'inconsistent kallsyms data' error.
> 
> Now, looking at the __data_loc values in these files:
> 
> vm1.syms-c03bd408 t __irf_start
> vm1.syms-c03bd408 T __security_initcall_end
> vm1.syms-c03bd408 T __security_initcall_start
> vm1.syms-c03bd608 T __initramfs_size
> vm1.syms-c03bd608 t __irf_end
> vm1.syms:c03be000 A __data_loc
> vm1.syms-c03be000 A __init_end
> vm1.syms-c03be000 D __per_cpu_end
> vm1.syms-c03be000 D __per_cpu_load
> vm1.syms-c03be000 D __per_cpu_start
> vm1.syms-c03be000 D _data
> --
> vm2.syms-c0438608 t __irf_end
> vm2.syms-c0439000 A __init_end
> vm2.syms-c0439000 T __per_cpu_end
> vm2.syms-c0439000 T __per_cpu_load
> vm2.syms-c0439000 T __per_cpu_start
> vm2.syms:c043a000 A __data_loc
> vm2.syms-c043a000 D _data
> vm2.syms-c043a000 D _sdata
> vm2.syms-c043a000 D init_thread_union
> vm2.syms-c043c000 D __nosave_begin
> vm2.syms-c043c000 D __nosave_end
> 
> What we see here is the start of the data section aligned to 8K as
> required for the init task data.  The per-cpu data is aligned to a 4K
> boundary immediately before it.  However, as it is an empty section,
> it can be aligned to the same 8K boundary as the data section depending
> on the size and placement of the previous sections which include the
> kallsyms data.
> 
> The solution?  We could artificially increase the alignment of the
> per-cpu data, or waste a byte after the per-cpu data to ensure that we
> don't align both together.  That could mean wasting up to 12K of space
> for no reason other than to avoid this error which is exceedingly silly.
> 
> I'm not sure whether the kallsyms name data generation could be
> changed so that this kind of thing doesn't matter but I suspect
> that's an exceedingly difficult problem to crack.
> 
> In the mean time, I'd suggest building with the additional kallsyms pass
> when it's required.

We've been hitting this in Fedora on particularly UP kernel builds. I
also came to the same conclusions that you did (see Google+) and had a
chat with Arnd about it. A test build with the __per_cpu_* data removed
from the linker vmlinux.lds succeeds in building for the reasons cited.
That's not to say that was the intended fix, just an experiment to
confirm that this is the problem we've been hitting on some builds.

The "problem" is that kallsyms uses a "compression" algorithm that
derives the name compressed from the type+symbol_name so
"T__per_cpu_start" becomes "D__per_cpu_start". The compression is very
trivial in that unused characters in the set of input symbols are used
to represent popular character pairs, etc. So when the symbol changes
type according to nm output (as you explain), the size of kallsyms_names
will likely change, changing all the offsets. I was going to report this
either this evening or in the morning, but I have been waiting for some
tests to complete. Glad you found it.

As to longer term, I am happy to work up something that will spot this
particular kind of failure (symbol changes type) and output something
more useful during the kallsyms generation if you would like.

Are you planning to pull in either of the fixes you mention?

Jon.


From robherring2 at gmail.com  Sun Mar 25 21:36:44 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sun, 25 Mar 2012 20:36:44 -0500
Subject: [GIT PULL] pxa io.h clean-up fixes
Message-ID: <4F6FC82C.2040303@gmail.com>

Arnd, Olof,

Here's a couple more fixes for pxa from mach/io.h cleanup. This is based
on my previous pull request.

This still doesn't get pxa completely working on my branch. I had to add
commit e23e8c0690d (ARM/PCI: Remove ARM's duplicate definition of
'pcibios_max_latency') to get my tree building for pxa. This commit is
already in final 3.3.

There's some new breakage when I merged the current next in and built
with Russell's pxa test config. The failures are due to struct device
removal in this commit:

commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0
Author: Mark Brown <broonie at opensource.wolfsonmicro.com>
Date:   Thu Feb 2 00:10:51 2012 +0000

    regulator: Remove support for supplies specified by struct device

    This has been deprecated for a very long time now.

    Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
    Reviewed-by: Linus Walleij <linus.walleij at linaro.org>
    Acked-by: Liam Girdwood <lrg at ti.com>

Rob

The following changes since commit a2a47ca36642e3995e982957bc42678cf11ca6ac:

  ARM: __io abuse cleanup (2012-03-13 21:25:21 -0500)

are available in the git repository at:
  git://sources.calxeda.com/kernel/linux.git io-cleanup-for-3.4

Rob Herring (2):
      ARM: dma-mapping: convert ARCH_HAS_DMA_SET_COHERENT_MASK to
kconfig symbol
      ARM: pxa: use common IOMEM definition

 arch/arm/Kconfig                             |    4 ++++
 arch/arm/mach-ixp4xx/include/mach/hardware.h |    2 --
 arch/arm/mach-pxa/Kconfig                    |    1 +
 arch/arm/mach-pxa/clock-pxa2xx.c             |    1 +
 arch/arm/mach-pxa/corgi_pm.c                 |    1 +
 arch/arm/mach-pxa/cpufreq-pxa3xx.c           |    1 +
 arch/arm/mach-pxa/include/mach/hardware.h    |    6 ------
 arch/arm/mach-pxa/mfp-pxa2xx.c               |    1 +
 arch/arm/mach-pxa/pxa2xx.c                   |    1 +
 arch/arm/mach-pxa/pxa300.c                   |    1 +
 arch/arm/mach-pxa/pxa320.c                   |    1 +
 arch/arm/mach-pxa/sharpsl_pm.c               |    1 +
 drivers/rtc/rtc-sa1100.c                     |    1 +
 drivers/watchdog/sa1100_wdt.c                |    1 +
 include/linux/dma-mapping.h                  |    2 +-
 sound/arm/pxa2xx-ac97-lib.c                  |    1 +
 sound/arm/pxa2xx-ac97.c                      |    1 +
 sound/soc/pxa/pxa2xx-ac97.c                  |    1 +
 18 files changed, 19 insertions(+), 9 deletions(-)


From robherring2 at gmail.com  Sun Mar 25 21:50:44 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sun, 25 Mar 2012 20:50:44 -0500
Subject: [PATCH] ARM: tegra: Include assembler.h in sleep.S to fix build
 break
In-Reply-To: <4F6A0D99.2000309@gmail.com>
References: <1332176863-12537-1-git-send-email-swarren@wwwdotorg.org>
 <4F677691.8020307@gmail.com> <4F69FEB5.2020901@wwwdotorg.org>
 <4F6A0999.9020104@gmail.com> <4F6A0A44.3010304@wwwdotorg.org>
 <4F6A0D99.2000309@gmail.com>
Message-ID: <4F6FCB74.7010706@gmail.com>

Stephen,

On 03/21/2012 12:19 PM, Rob Herring wrote:
> On 03/21/2012 12:05 PM, Stephen Warren wrote:
>> On 03/21/2012 11:02 AM, Rob Herring wrote:
>>> On 03/21/2012 11:15 AM, Stephen Warren wrote:
>>>> On 03/19/2012 12:10 PM, Rob Herring wrote:
>>>>> On 03/19/2012 12:07 PM, Stephen Warren wrote:
>>>>>> Commit 6f6f6a7 "ARM: create a common IOMEM definition" moved macro
>>>>>> IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's
>>>>>> sleep.S to do so.
>>>>>>
>>>>>> Signed-off-by: Stephen Warren <swarren at wwwdotorg.org>
>>>>>
>>>>> Acked-by: Rob Herring <rob.herring at calxeda.com>
>>>>
>>>> Arnd,
>>>>
>>>> Can you pick up this fix directly into arm-soc, or do you want me to
>>>> generate a pull request for this kind of thing too?
>>>>
>>>> ARM: tegra: Include assembler.h in sleep.S to fix build break
>>>> http://patchwork.ozlabs.org/patch/147587/
>>>>
>>>> The same goes for:
>>>>
>>>> ARM: tegra: Fix device tree AUXDATA for USB/EHCI
>>>> http://patchwork.ozlabs.org/patch/147616/
>>>
>>> I can take it and send the pull request. I've got a couple of other
>>> fixes as well.
>>
>> That's just for the sleep.S change, right.
> 
> Ah, I missed the 2nd one. So it makes less sense now for me to take it.
> I'm still happy to, but it doesn't really save you anything.

After our irc discussion, I pulled this in and then realized this is a
newly added file that's not in my tree. So you should send this fix to
Arnd/Olof.

Rob


From robherring2 at gmail.com  Sun Mar 25 21:59:22 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Sun, 25 Mar 2012 20:59:22 -0500
Subject: [PATCH 1/2] ARM: VIC: Create common infrastructure for vic DT
 bindings
In-Reply-To: <CAOh2x=n-sZ6jV1M9XY9cOp7_8EeRfvqkjL5y3AakgpYymFRHkg@mail.gmail.com>
References: <4bfe7af3761f6f40506a2089fd67866015f6d7f3.1332488625.git.viresh.kumar@st.com>
 <4F6C6F32.10800@gmail.com>
 <CAOh2x=n-sZ6jV1M9XY9cOp7_8EeRfvqkjL5y3AakgpYymFRHkg@mail.gmail.com>
Message-ID: <4F6FCD7A.3030804@gmail.com>

On 03/25/2012 02:31 AM, viresh kumar wrote:
> On Fri, Mar 23, 2012 at 6:10 PM, Rob Herring <robherring2 at gmail.com> wrote:
>> NAK
>>
>> None of these platforms have gpio interrupts or any other board
>> interrupt controllers which need to be initialized early?
> 
> Atleast SPEAr600 have GPIO interrupts.
> 
>> I don't think DT conversions are complete enough to tell.
> 
> Couldn't get your comment, sorry.

Some DT enabled platforms may only have the gic or vic included in their
match list currently because other interrupt controllers aren't yet
converted to DT. I believe Exynos is one such example.

> 
>> We could do something like this, but there only needs to be a single
>> match list of all controllers and function. We should consolidate the
>> irqchips to drivers/irqchip first though. I have that action from Connect...
> 
> That would be good.
> I am updating DT support for SPEAr3xx, where i need to use VIC OF
> support. So i would still like to get this patch going and you can consilidate
> code at irqchips level later. What do you say?

No. I don't think moving this into the gic and vic code just to move it
back out later is a good idea. Just looking at the diffstat, the net
number of lines removed is not very compelling either.

Rob

> 
> --
> viresh



From oleg at redhat.com  Sun Mar 25 13:42:10 2012
From: oleg at redhat.com (Oleg Nesterov)
Date: Sun, 25 Mar 2012 19:42:10 +0200
Subject: [PATCH v2.1 01/10] cpu: Introduce clear_tasks_mm_cpumask() helper
In-Reply-To: <20120324164316.GB3640@lizard>
References: <20120324102609.GA28356@lizard> <20120324102751.GA29067@lizard>
 <1332593021.16159.27.camel@twins> <20120324164316.GB3640@lizard>
Message-ID: <20120325174210.GA23605@redhat.com>

On 03/24, Anton Vorontsov wrote:
>
> Many architctures clear tasks' mm_cpumask like this:
>
> 	read_lock(&tasklist_lock);
> 	for_each_process(p) {
> 		if (p->mm)
> 			cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
> 	}
> 	read_unlock(&tasklist_lock);

Namely arm, powerpc, and sh.

> The code above has several problems, such as:
>
> 1. Working with task->mm w/o getting mm or grabing the task lock is
>    dangerous as ->mm might disappear (exit_mm() assigns NULL under
>    task_lock(), so tasklist lock is not enough).

This is not actually true for arm and sh, afaics. They do not even
need tasklist or rcu lock for for_each_process().

__cpu_disable() is called by __stop_machine(), we know that nobody
can preempt us and other CPUs can do nothing.

> 2. Checking for process->mm is not enough because process' main
>    thread may exit or detach its mm via use_mm(), but other threads
>    may still have a valid mm.

Yes,

> Also, Per Peter Zijlstra's idea, now we don't grab tasklist_lock in
> the new helper, instead we take the rcu read lock. We can do this
> because the function is called after the cpu is taken down and marked
> offline, so no new tasks will get this cpu set in their mm mask.

And only powerpc needs rcu_read_lock() and task_lock().

OTOH, I do not understand why powepc does this on CPU_DEAD...
And probably CPU_UP_CANCELED doesn't need to clear mm_cpumask().

That said, personally I think these patches are fine, the common
helper makes sense.

Oleg.

_______________________________________________
Linuxppc-dev mailing list
Linuxppc-dev at lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev


From vinod.koul at linux.intel.com  Mon Mar 26 02:03:53 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Mon, 26 Mar 2012 11:33:53 +0530
Subject: [PATCH v3 00/13] dmaengine: imx-dma: merge dma arch code into
 dmaengine.
In-Reply-To: <CACKLOr0JTgp+poXCNg8+8pXko3s2JWQhovMw8Z1j-q4aL4oaKQ@mail.gmail.com>
References: <1331306449-28591-1-git-send-email-javier.martin@vista-silicon.com>
 <1332344363.19804.12.camel@vkoul-udesk3>
 <CACKLOr03tTymT1vdTH7=nqEHu3OvAinPUHEusK+mR+J6Yc35mQ@mail.gmail.com>
 <CACKLOr0JTgp+poXCNg8+8pXko3s2JWQhovMw8Z1j-q4aL4oaKQ@mail.gmail.com>
Message-ID: <1332741833.19804.17.camel@vkoul-udesk3>

On Thu, 2012-03-22 at 15:11 +0100, javier Martin wrote:
> On 22 March 2012 10:39, javier Martin <javier.martin at vista-silicon.com> wrote:
> > On 21 March 2012 16:39, Vinod Koul <vinod.koul at linux.intel.com> wrote:
> >> This doesn't apply for me (starting with 6th) on current slave-dma.next
> >> due to obvious changes which have gone into imx.
> >>
> >> Can you quickly rebase the series and resend.
> >
> > Great,
> > now your 'next' branch is actually broken for imx-dma.
> >
> > I'm currently trying a bisect to find out what is the commit
> > responsible for that but I suspect it will be related to the cookie
> > changes submitted by Russell.
I had these in branch for quite some time for people to look and point
out any issues with merge.
> 
> Here,
> take a look at this series:
> 
> [PATCH v4 00/15] dmaengine: imx-dma: rebase of features for 3.4.
> 
> I've included a new fix patch which solves the merge issue.
Thanks Applied all, now
> 
> Regards.


-- 
~Vinod



From afzal at ti.com  Mon Mar 26 02:03:21 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 26 Mar 2012 06:03:21 +0000
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <4F6C9929.6030704@ti.com>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
 <4F6C445A.3040103@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A9317A6A83@DBDE01.ent.ti.com>
 <4F6C9929.6030704@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A9317BAF9E@DBDE01.ent.ti.com>

Hi Benoit,

On Fri, Mar 23, 2012 at 21:09:21, Cousson, Benoit wrote:
> But EMIF does not have anything to do in MFD either :-)
> 
> What was the feedback for this series?
> 
> We discussed that at Linaro connect, but it looks like MFD is becoming 
> the place for miscellaneous drivers that we do not know where to put.
> 
> Maybe we should introduce a driver/memory/ directory for memory 
> controller. At least for EMIF.
> In the case of GMPC, it is slightly different because it can handle 
> NOR/NAND memory but as well behave like an ISA bus controller for 
> Ethernet ISA chip.
> But since it can control several devices thanks the chipselects lines it 
> has, it behaves like a multi-protocol bus controller.
> But in anycase, it does not look like an MFD for my point of view. For 
> me a MFD is like a small soc, it does contain several completely 
> unrelated block (Power, Audio, GPIO...), but does share some memory 
> space / IRQ lines.
> 
> Is this the only controller doing that kind of stuff in the kernel so far?

An additional intention of sending RFC early was to find out whether selection
of MFD was acceptable. Coding so far has been done so that it can easily move
to MFD or other types.

Frankly I had not done much research on where GPMC driver should belong,
my thought was first convert it into a driver (but vaguely in mind it may have
to go to MFD), later decide on where it should go. Probably task of finding
correct place for GPMC driver should happen in parallel with driver conversion.

For davinci EMIF, afaik, no conclusion has been reached yet.

I will try to find whether there is anything similar already in Kernel,
and find out a suitable place for GPMC driver.

> > If an initial patch just to rearrange the code to have similar section
> > together&  then new changes in a another patch, would that be fine?
> 
> Well, if this is just comestic, I will even do that after the driver 
> conversion. Because if you do that before you will move some piece of 
> code that you might completely delete later. So you should fix the code 
> first and then potentially, move some part if that will improve the 
> readability.

Ok

Regards
Afzal


From afzal at ti.com  Mon Mar 26 02:07:49 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 26 Mar 2012 06:07:49 +0000
Subject: [RFC][PATCH 0/5] Convert GPMC to driver
In-Reply-To: <CAMQu2gzSk26kWgB4+xjB007_zogxQkR9c0po42n56wYYySz65w@mail.gmail.com>
References: <1332484567-21710-1-git-send-email-afzal@ti.com>
 <CAMQu2gzSk26kWgB4+xjB007_zogxQkR9c0po42n56wYYySz65w@mail.gmail.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A9317BAFB3@DBDE01.ent.ti.com>

Hi Santosh,

On Fri, Mar 23, 2012 at 16:05:47, Shilimkar, Santosh wrote:
> Much needed series. Thanks Afzal for doing it.

Probably going through this first version, your thanks would have evaporated;
else if (thanks > 0)
	redirected to Vaibhav Hiremath & Sekhar Nori.

Regards
Afzal


From afzal at ti.com  Mon Mar 26 02:14:10 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 26 Mar 2012 06:14:10 +0000
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <20120323162859.GC24544@arwen.pp.htv.fi>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
 <4F6C445A.3040103@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A9317A6A83@DBDE01.ent.ti.com>
 <4F6C9929.6030704@ti.com> <20120323162859.GC24544@arwen.pp.htv.fi>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A9317BAFCF@DBDE01.ent.ti.com>

Hi Balbi,

On Fri, Mar 23, 2012 at 21:59:00, Balbi, Felipe wrote:
> yeah, I was thinking about drivers/ocd (off-chip devices) or
> drivers/mmio... and that should be flexible enough to hold gpmc, lli and
> c2c (from OMAP's perspective).

Ok, I will check feasibility of having GPMC driver at those places.

> I wouldn't do that. I would only move after the driver is cleaned up.
> Are you concerned with the diffstat alone ? that'd be silly :-p

Ok

Regards
Afzal


From vinod.koul at linux.intel.com  Mon Mar 26 02:24:33 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Mon, 26 Mar 2012 11:54:33 +0530
Subject: [PATCH v5 1/2] dmaengine: Add context parameter to prep_dma_sg
 and prep_interleaved_dma
In-Reply-To: <1332426167-25213-1-git-send-email-kumarrav@codeaurora.org>
References: <1332426167-25213-1-git-send-email-kumarrav@codeaurora.org>
Message-ID: <1332743073.19804.26.camel@vkoul-udesk3>

On Thu, 2012-03-22 at 19:52 +0530, Ravi Kumar V wrote:
> Add new context parameter to DMA SG and Interleaveid mode for passing
Typo					  ^^^^^^^^^^^^
> per transfer specific private data, using this it enables the
> dma devices which needs to pass the parameters which changes per
> each transfer
> 
> Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
> ---
>  drivers/dma/fsldma.c                    |    2 +-
>  drivers/dma/sirf-dma.c                  |    2 +-
>  drivers/dma/ste_dma40.c                 |    2 +-
>  drivers/misc/carma/carma-fpga-program.c |    2 +-
>  drivers/misc/carma/carma-fpga.c         |    7 +++----
>  include/linux/dmaengine.h               |   22 ++++++++++++++++++++--
>  6 files changed, 27 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
> index b98070c..f9f77db 100644
> --- a/drivers/dma/fsldma.c
> +++ b/drivers/dma/fsldma.c
> @@ -645,7 +645,7 @@ fail:
>  static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
>  	struct scatterlist *dst_sg, unsigned int dst_nents,
>  	struct scatterlist *src_sg, unsigned int src_nents,
> -	unsigned long flags)
> +	unsigned long flags, void *context)
>  {
>  	struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
>  	struct fsldma_chan *chan = to_fsl_chan(dchan);
> diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c
> index 2333810..ff4d344 100644
> --- a/drivers/dma/sirf-dma.c
> +++ b/drivers/dma/sirf-dma.c
> @@ -428,7 +428,7 @@ sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
>  
>  static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
>  	struct dma_chan *chan, struct dma_interleaved_template *xt,
> -	unsigned long flags)
> +	unsigned long flags, void *context)
>  {
>  	struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
>  	struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index cc5ecbc..2f58ba9 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -2287,7 +2287,7 @@ static struct dma_async_tx_descriptor *
>  d40_prep_memcpy_sg(struct dma_chan *chan,
>  		   struct scatterlist *dst_sg, unsigned int dst_nents,
>  		   struct scatterlist *src_sg, unsigned int src_nents,
> -		   unsigned long dma_flags)
> +		   unsigned long dma_flags, void *context)
>  {
>  	if (dst_nents != src_nents)
>  		return NULL;
> diff --git a/drivers/misc/carma/carma-fpga-program.c b/drivers/misc/carma/carma-fpga-program.c
> index a2d25e4..3739a12 100644
> --- a/drivers/misc/carma/carma-fpga-program.c
> +++ b/drivers/misc/carma/carma-fpga-program.c
> @@ -530,7 +530,7 @@ static noinline int fpga_program_dma(struct fpga_dev *priv)
>  	}
>  
>  	/* setup and submit the DMA transaction */
> -	tx = chan->device->device_prep_dma_sg(chan,
> +	tx = chan->device->dmaengine_prep_dma_sg(chan,
>  					      table.sgl, num_pages,
>  					      vb->sglist, vb->sglen, 0);
No the idea is that clients will not know anything about additionlay
parameter hence avoiding abuse. You need to reread the patches sent by
Alexandre.

You need to 
1) add wrappers over interleaved api which dont expose this additional
parameter
2) move existing users to use these wrappers
3) add a new API which has your additional argument (not an opaque
object) and this calls .device_xx callback with additional arg.
4. Above can be under conditional of your specific subsystem where these
parameters are valid.

>  	if (!tx) {
> diff --git a/drivers/misc/carma/carma-fpga.c b/drivers/misc/carma/carma-fpga.c
> index 14e974b2..be0baf6 100644
> --- a/drivers/misc/carma/carma-fpga.c
> +++ b/drivers/misc/carma/carma-fpga.c
> @@ -638,10 +638,9 @@ static int data_submit_dma(struct fpga_device *priv, struct data_buf *buf)
>  	 */
>  
>  	/* setup the scatterlist to scatterlist transfer */
> -	tx = chan->device->device_prep_dma_sg(chan,
> -					      dst_sg, dst_nents,
> -					      src_sg, src_nents,
> -					      0);
> +	tx = dmaengine_prep_dma_sg(chan, dst_sg, dst_nents,
> +					 src_sg, src_nents,
> +					 0);
>  	if (!tx) {
>  		dev_err(priv->dev, "unable to prep scatterlist DMA\n");
>  		return -ENOMEM;
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index 679b349..68a57da 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -570,7 +570,7 @@ struct dma_device {
>  		struct dma_chan *chan,
>  		struct scatterlist *dst_sg, unsigned int dst_nents,
>  		struct scatterlist *src_sg, unsigned int src_nents,
> -		unsigned long flags);
> +		unsigned long flags, void *context);
>  
>  	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
>  		struct dma_chan *chan, struct scatterlist *sgl,
> @@ -581,7 +581,7 @@ struct dma_device {
>  		size_t period_len, enum dma_transfer_direction direction);
>  	struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
>  		struct dma_chan *chan, struct dma_interleaved_template *xt,
> -		unsigned long flags);
> +		unsigned long flags, void *context);
>  	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
>  		unsigned long arg);
>  
> @@ -615,6 +615,24 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
>  	return chan->device->device_prep_slave_sg(chan, &sg, 1, dir, flags);
>  }
>  
> +static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
> +			struct dma_chan *chan, struct scatterlist *dst_sg,
> +			unsigned int dst_nents,	struct scatterlist *src_sg,
> +			unsigned int src_nents,	unsigned long flags)
> +{
> +	return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents,
> +					src_sg, src_nents, flags, NULL);
> +}
> +
> +static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
> +			struct dma_chan *chan,
> +			struct dma_interleaved_template *xt,
> +			unsigned long flags)
> +{
> +	return chan->device->device_prep_interleaved_dma(chan, xt,
> +							flags, NULL);
> +}
> +
>  static inline int dmaengine_terminate_all(struct dma_chan *chan)
>  {
>  	return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);


-- 
~Vinod



From prylowski at metasoft.pl  Mon Mar 26 02:44:34 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Mon, 26 Mar 2012 08:44:34 +0200
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <20120324073207.GD5812@mwesterb-mobl.ger.corp.intel.com>
References: <4F683B36.8090101@metasoft.pl>
 <20120321193836.GC3740@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48E3E@AUSP01VMBX24.collaborationhost.net>
 <20120323070446.GC5812@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48EEB@AUSP01VMBX24.collaborationhost.net>
 <20120324073207.GD5812@mwesterb-mobl.ger.corp.intel.com>
Message-ID: <4F701052.5000509@metasoft.pl>

On 2012-03-24 08:32, Mika Westerberg wrote:
> Please try it. The point there was that we have a problem in ep93xx VIC/DMA
> code but it is totally different thing and not related to Rafal's patch. We
> can sort the VIC thing out separately IMHO. ep93xx dma in 3.3 is broken
> regardless this patch.

I think, that we can't be 100% sure that these two problems are not related
at all. If some changes to VIC/ep93xx interrupt handling etc will be send
to list, I'll test them in my configuration without my patch. If it will
help (to fix the problem I'm observing also in 3.2), then double buffering
for M2M could be much simplier.

Now, I'm trying to test mmc_spi in ep93xx and let you know what the results
are.


From svenkatr at ti.com  Mon Mar 26 02:49:12 2012
From: svenkatr at ti.com (S, Venkatraman)
Date: Mon, 26 Mar 2012 12:19:12 +0530
Subject: Occasional crashes in suspend-resume with MMC transactions
In-Reply-To: <B5906170F1614E41A8A28DE3B8D12143317FFC59@DBDE01.ent.ti.com>
References: <B5906170F1614E41A8A28DE3B8D12143317FDFBB@DBDE01.ent.ti.com>
 <B5906170F1614E41A8A28DE3B8D12143317FF773@DBDE01.ent.ti.com>
 <CANfBPZ9b=6dLbY2D3oAg=Gz_vwAOJ+KC_Bo5ugVJEwumeej_Bw@mail.gmail.com>
 <B5906170F1614E41A8A28DE3B8D12143317FFAC0@DBDE01.ent.ti.com>
 <CANfBPZ9AU+W7qP+uE2s2EnpzKhUqVQLdEgN=CUeNJZkSoh7+5A@mail.gmail.com>
 <B5906170F1614E41A8A28DE3B8D12143317FFC59@DBDE01.ent.ti.com>
Message-ID: <CANfBPZ8SD4jimMsrbFNrYemNUQzb5dLbwdMKB=x8EADWCJktvw@mail.gmail.com>

On Thu, Mar 22, 2012 at 9:43 PM, Bedia, Vaibhav <vaibhav.bedia at ti.com> wrote:
> On Thu, Mar 22, 2012 at 21:36:36, S, Venkatraman wrote:
>> On Thu, Mar 22, 2012 at 8:13 PM, Bedia, Vaibhav <vaibhav.bedia at ti.com> wrote:
>> > On Thu, Mar 22, 2012 at 19:57:16, S, Venkatraman wrote:
>> > [...]
>> >>
>> >> I see (in 3.3) that the host controller driver does a "return ret" and
>> >> that means the errors is propagated.
>> >> Where is the return code lost /overridden ?
>> >>
>> >
>> > The return code gets overridden due to the call to host->pdata->resume()
>> > which always returns 0.
>>
>> Thanks - I see what you mean. But the patch is clunky.
>> A clean fix would be to not capture the return code of resume() in
>> "ret" and let the old
>> value of ret be propagated as is.
>>
>
> I agree. However, right now there's a dev_dbg() which checks for the return code.
> I could change the host->pdata->resume() and host->pdata->suspend() to not return
> anything if that's acceptable.
>
That's a good idea.

> More importantly, is this the right fix or does the driver need some other fix
> to make sure that such suspend failures do not occur at all?

I will look into this - but haven't seen such failures here to know
what's behind the symptom.


From tsoni at codeaurora.org  Mon Mar 26 02:55:56 2012
From: tsoni at codeaurora.org (Trilok Soni)
Date: Mon, 26 Mar 2012 12:25:56 +0530
Subject: [PATCH v5 1/2] dmaengine: Add context parameter to prep_dma_sg
 and prep_interleaved_dma
In-Reply-To: <1332743073.19804.26.camel@vkoul-udesk3>
References: <1332426167-25213-1-git-send-email-kumarrav@codeaurora.org>
 <1332743073.19804.26.camel@vkoul-udesk3>
Message-ID: <4F7012FC.10203@codeaurora.org>

On 3/26/2012 11:54 AM, Vinod Koul wrote:
> On Thu, 2012-03-22 at 19:52 +0530, Ravi Kumar V wrote:
>> Add new context parameter to DMA SG and Interleaveid mode for passing
> Typo					  ^^^^^^^^^^^^

Sorry, we will fix this.

>> diff --git a/drivers/misc/carma/carma-fpga-program.c b/drivers/misc/carma/carma-fpga-program.c
>> index a2d25e4..3739a12 100644
>> --- a/drivers/misc/carma/carma-fpga-program.c
>> +++ b/drivers/misc/carma/carma-fpga-program.c
>> @@ -530,7 +530,7 @@ static noinline int fpga_program_dma(struct fpga_dev *priv)
>>   	}
>>
>>   	/* setup and submit the DMA transaction */
>> -	tx = chan->device->device_prep_dma_sg(chan,
>> +	tx = chan->device->dmaengine_prep_dma_sg(chan,
>>   					      table.sgl, num_pages,
>>   					      vb->sglist, vb->sglen, 0);
> No the idea is that clients will not know anything about additionlay
> parameter hence avoiding abuse. You need to reread the patches sent by
> Alexandre.
>
> You need to
> 1) add wrappers over interleaved api which dont expose this additional
> parameter
> 2) move existing users to use these wrappers

Above two steps would be exactly same as 
https://lkml.org/lkml/2012/3/8/401 - [PATCH 1/2 V2] dmaengine/dma_slave: 
introduce inline wrappers, right?

> 3) add a new API which has your additional argument (not an opaque
> object) and this calls .device_xx callback with additional arg.
> 4. Above can be under conditional of your specific subsystem where these
> parameters are valid.

Now, this would be different from what Alexandre had submitted, since he 
had added "void *context" parameter directly to existing callbacks 
dma_slave_sg and and cyclic under struct dma_device.

And you prefer that we add new callbacks under "struct dma_device" for 
our specific requirement with new name and with that extra non-opaque 
object. After that add wrappers for these two new callbacks say
dmaengine_prep_dma_sg_ext and dmagengine_prep_interleaved_dma_ext (same
name goes for callback).

---Trilok Soni

-- 
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From vinod.koul at linux.intel.com  Mon Mar 26 03:07:29 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Mon, 26 Mar 2012 12:37:29 +0530
Subject: [PATCH v5 2/2] DMAEngine: Add DMAEngine driver based on old
 MSM ADM DMA APIs
In-Reply-To: <1332426216-25273-1-git-send-email-kumarrav@codeaurora.org>
References: <1332426216-25273-1-git-send-email-kumarrav@codeaurora.org>
Message-ID: <1332745649.19804.69.camel@vkoul-udesk3>

On Thu, 2012-03-22 at 19:53 +0530, Ravi Kumar V wrote:
> Add DMAEngine based driver using the old MSM ADM DMA APIs internally.
> The benefit of this approach is that not all the drivers
> have to get converted to DMAEngine APIs simultaneosly while
typo again!				
> both the drivers can stay enabled in the kernel. The client
> drivers using the old MSM APIs directly can now convert to
> DMAEngine one by one.
> 
> Signed-off-by: Ravi Kumar V <kumarrav at codeaurora.org>
> ---
>  arch/arm/mach-msm/include/mach/dma.h |   35 ++
>  drivers/dma/Kconfig                  |   12 +
>  drivers/dma/Makefile                 |    1 +
>  drivers/dma/msm_adm_dma.c            |  728 ++++++++++++++++++++++++++++++++++
>  4 files changed, 776 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/dma/msm_adm_dma.c
> 
> diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
> index 05583f5..95b7b15 100644
> --- a/arch/arm/mach-msm/include/mach/dma.h
> +++ b/arch/arm/mach-msm/include/mach/dma.h
> @@ -18,6 +18,36 @@
>  #include <linux/list.h>
>  #include <mach/msm_iomap.h>
>  
> +#define sg_dma_offset(sg)               ((sg)->offset)
> +#define box_dma_row_address(box)        ((box)->dma_row_address)
> +#define box_dma_row_len(box)            ((box)->dma_row_len)
> +#define box_dma_row_num(box)            ((box)->dma_row_num)
> +#define box_dma_row_offset(box)         ((box)->dma_row_offset)
> +
> +#define MSM_DMA_CMD_MASK		0x9FFF8
> +#define MSM_DMA_CMD_SHIFT		0
> +#define MSM_BOX_SRC_RLEN_MASK		0xFFFF
> +#define MSM_BOX_SRC_RLEN_SHIFT		16
> +#define MSM_BOX_SRC_RNUM_MASK		0xFFFF
> +#define MSM_BOX_SRC_RNUM_SHIFT		16
> +#define MSM_BOX_SRC_ROFFSET_MASK	0xFFFF
> +#define MSM_BOX_SRC_ROFFSET_SHIFT	16
> +#define MSM_BOX_DST_RLEN_MASK		0xFFFF
> +#define MSM_BOX_DST_RNUM_MASK		0xFFFF
> +#define MSM_BOX_DST_ROFFSET_MASK	0xFFFF
> +#define MSM_BOX_MODE_CMD		0x3
> +
> +enum adm_flush_type {
> +	ADM_FORCED_FLUSH,
> +	ADM_GRACEFUL_FLUSH,
> +};
> +
> +enum adm_dma_type {
> +	ADM_SINGLE_MODE,
> +	ADM_SG_MODE,
> +	ADM_BOX_MODE,
> +};
> +
>  struct msm_dmov_errdata {
>  	uint32_t flush[6];
>  };
> @@ -32,6 +62,11 @@ struct msm_dmov_cmd {
>  	void *data;
>  };
>  
> +struct msm_adm_cmd_config {
> +	uint32_t num_cmd;
> +	uint32_t *cmd_cntrl;
> +};
> +
>  #ifndef CONFIG_ARCH_MSM8X60
>  void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
>  void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index f1a2749..1f99362 100644

> +++ b/drivers/dma/msm_adm_dma.c
> +struct msm_dma_chan {
> +	int chan_id;
> +	dma_cookie_t completed_cookie;
> +	dma_cookie_t error_cookie;
i suspect you haven't updated this to use new cookie helpers
> +	spinlock_t lock;
> +	struct list_head active_list;
> +	struct list_head pending_list;
> +	struct dma_chan channel;
> +	struct dma_pool *desc_pool;
> +	struct device *dev;
> +	int max_len;
> +	int err;
> +	struct tasklet_struct tasklet;
> +};
> +
> +struct msm_dma_device {
> +	void __iomem *base;
> +	struct device *dev;
> +	struct dma_device common;
> +	struct msm_dma_chan *chan[MSM_DMA_MAX_CHANS_PER_DEVICE];
> +};
> +
> +struct msm_dma_desc_hw {
> +	unsigned int cmd_list_ptr;
> +} __aligned(8);
> +
> +/* Single Item Mode */
> +struct adm_cmd_t {
> +	unsigned int cmd_cntrl;
> +	unsigned int src;
> +	unsigned int dst;
> +	unsigned int len;
> +};
> +
> +struct adm_box_cmd_t {
> +	uint32_t cmd_cntrl;
> +	uint32_t src_row_addr;
> +	uint32_t dst_row_addr;
> +	uint32_t src_dst_len;
> +	uint32_t num_rows;
> +	uint32_t row_offset;
> +};
> +
> +struct msm_dma_desc_sw {
> +	struct msm_dma_desc_hw hw;
> +	struct adm_cmd_t *vaddr_cmd;
> +	struct adm_box_cmd_t *vaddr_box_cmd;
> +	size_t coherent_size;
> +	dma_addr_t paddr_cmd_list;
> +	struct list_head node;
> +	struct msm_dmov_cmd dmov_cmd;
> +	struct dma_async_tx_descriptor async_tx;
> +} __aligned(8);
> +
> +static int msm_dma_alloc_chan_resources(struct dma_chan *dchan)
> +{
> +	struct msm_dma_chan *chan = to_msm_chan(dchan);
> +
> +	/* Has this channel already been allocated? */
> +	if (chan->desc_pool)
> +		return 1;
> +
> +	/*
> +	 * We need the descriptor to be aligned to 8bytes
> +	 * for meeting ADM specification requirement.
> +	 */
> +	chan->desc_pool = dma_pool_create("msm_dma_desc_pool",
> +					chan->dev,
> +					sizeof(struct msm_dma_desc_sw),
> +				__alignof__(struct msm_dma_desc_sw), 0);
> +	if (!chan->desc_pool) {
> +		dev_err(chan->dev, "unable to allocate channel %d "
> +				"descriptor pool\n", chan->chan_id);
> +		return -ENOMEM;
> +	}
> +
> +	chan->completed_cookie = 1;
> +	dchan->cookie = 1;
rightly guessed...

> +
> +	/* there is at least one descriptor free to be allocated */
> +	return 1;
hrm?
You need to return the number of descriptors you allocate. And then why
1 here?
> +}
> +

> +static void msm_dma_free_chan_resources(struct dma_chan *dchan)
> +{
> +	struct msm_dma_chan *chan = to_msm_chan(dchan);
> +	unsigned long flags;
> +
> +	dev_dbg(chan->dev, "Free all channel resources.\n");
> +	spin_lock_irqsave(&chan->lock, flags);
> +	msm_dma_free_desc_list(chan, &chan->active_list);
> +	msm_dma_free_desc_list(chan, &chan->pending_list);
Shouldnt you check if dma is active?

> +	spin_unlock_irqrestore(&chan->lock, flags);
> +
> +	dma_pool_destroy(chan->desc_pool);
> +	chan->desc_pool = NULL;
> +}
> +
> +static enum dma_status msm_dma_desc_status(struct msm_dma_chan *chan,
> +					struct msm_dma_desc_sw *desc)
> +{
> +	return dma_async_is_complete(desc->async_tx.cookie,
> +					chan->completed_cookie,
> +					chan->channel.cookie);
> +}
> +
> +static void msm_chan_desc_cleanup(struct msm_dma_chan *chan)
> +{
> +	struct msm_dma_desc_sw *desc, *_desc;
> +	unsigned long flags;
> +
> +	dev_dbg(chan->dev, "Cleaning completed descriptor of channel %d\n",
> +							chan->chan_id);
> +	spin_lock_irqsave(&chan->lock, flags);
> +
> +	list_for_each_entry_safe(desc, _desc, &chan->active_list, node) {
> +		dma_async_tx_callback callback;
> +		void *callback_param;
> +
> +		if (msm_dma_desc_status(chan, desc) == DMA_IN_PROGRESS)
> +			break;
> +
> +		/* Remove from the list of running transactions */
> +		list_del(&desc->node);
> +
> +		/* Run the link descriptor callback function */
> +		callback = desc->async_tx.callback;
> +		callback_param = desc->async_tx.callback_param;
> +		if (callback) {
> +			spin_unlock_irqrestore(&chan->lock, flags);
> +			callback(callback_param);
> +			spin_lock_irqsave(&chan->lock, flags);
> +		}
> +
> +		/* Run any dependencies, then free the descriptor */
> +		dma_run_dependencies(&desc->async_tx);
> +		spin_unlock_irqrestore(&chan->lock, flags);
> +
> +		if (desc->vaddr_cmd) {
> +			dma_free_coherent(chan->dev, desc->coherent_size,
> +						(void *)desc->vaddr_cmd,
> +							desc->paddr_cmd_list);
> +		} else {
> +			dma_free_coherent(chan->dev, desc->coherent_size,
> +						(void *)desc->vaddr_box_cmd,
> +							desc->paddr_cmd_list);
> +		}
> +		spin_lock_irqsave(&chan->lock, flags);
> +		dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
> +	}
> +
> +	spin_unlock_irqrestore(&chan->lock, flags);
> +}
> +
> +static void dma_do_tasklet(unsigned long data)
> +{
> +	struct msm_dma_chan *chan = (struct msm_dma_chan *)data;
> +	msm_chan_desc_cleanup(chan);
> +}
> +
> +static void
> +msm_dma_complete_func(struct msm_dmov_cmd *cmd,
> +				unsigned int result,
> +				struct msm_dmov_errdata *err)
> +{
> +	unsigned long flags;
> +	struct msm_dma_desc_sw *desch = container_of(cmd,
> +				struct msm_dma_desc_sw, dmov_cmd);
> +	struct msm_dma_chan *chan = to_msm_chan(desch->async_tx.chan);
> +
> +	spin_lock_irqsave(&chan->lock, flags);
> +
> +	if ((result != NO_ERR_CHAN_STATUS) && err)
> +		chan->error_cookie = desch->async_tx.cookie;
> +	chan->completed_cookie = desch->async_tx.cookie;
> +
> +	tasklet_schedule(&chan->tasklet);
> +
> +	spin_unlock_irqrestore(&chan->lock, flags);
> +}
> +
> +/*
> + *  Passes transfer descriptors to DMA hardware.
> + */
> +static void msm_dma_issue_pending(struct dma_chan *dchan)
> +{
> +	struct msm_dma_chan *chan = to_msm_chan(dchan);
> +	struct msm_dma_desc_sw *desch;
> +	unsigned long flags;
> +
> +	if (chan->err)
> +		return;
> +
> +	spin_lock_irqsave(&chan->lock, flags);
> +
> +	if (list_empty(&chan->pending_list))
> +		goto out_unlock;
> +
> +	desch = list_first_entry(&chan->pending_list, struct msm_dma_desc_sw,
> +									node);
> +	list_del(&desch->node);
> +	desch->dmov_cmd.complete_func = msm_dma_complete_func;
> +	desch->dmov_cmd.execute_func = NULL;
> +	desch->dmov_cmd.cmdptr = DMOV_CMD_ADDR(desch->async_tx.phys);
> +	list_add_tail(&desch->node, &chan->active_list);
> +	mb();
> +	msm_dmov_enqueue_cmd(chan->chan_id, &desch->dmov_cmd);
> +out_unlock:
> +	spin_unlock_irqrestore(&chan->lock, flags);
> +}
> +
> +/*
> + *  Assignes cookie for each transfer descriptor passed.
> + *  Returns
> + *	Assigend cookie for success.
> + *	Error value for failure.
> + */
> +static dma_cookie_t msm_dma_tx_submit(struct dma_async_tx_descriptor *tx)
> +{
> +	struct msm_dma_chan *chan = to_msm_chan(tx->chan);
> +	struct msm_dma_desc_sw *desc = container_of(tx,
> +	struct msm_dma_desc_sw, async_tx);
> +	unsigned long flags;
> +	dma_cookie_t cookie = -EBUSY;
> +
> +	if (chan->err)
> +		return cookie;
> +
> +	spin_lock_irqsave(&chan->lock, flags);
> +
> +	/*
> +	 * assign cookies to all of the software descriptors
> +	 * that make up this transaction
> +	 */
> +	cookie = chan->channel.cookie;
> +	cookie++;
> +	if (cookie < 0)
> +		cookie = DMA_MIN_COOKIE;
this needs update
> +
> +	desc->async_tx.cookie = cookie;
> +	chan->channel.cookie = cookie;
> +
> +	/* put this transaction onto the tail of the pending queue */
> +	list_add_tail(&desc->node, &chan->pending_list);
> +
> +	spin_unlock_irqrestore(&chan->lock, flags);
> +
> +	return cookie;
> +}
> +
> +/*
> + *  Returns the DMA transfer status of a particular cookie
> + */
> +static enum dma_status msm_tx_status(struct dma_chan *dchan,
> +					dma_cookie_t cookie,
> +				struct dma_tx_state *txstate)
> +{
> +	struct msm_dma_chan *chan = to_msm_chan(dchan);
> +	dma_cookie_t last_used;
> +	dma_cookie_t last_complete;
> +	enum dma_status status;
> +
> +	last_used = dchan->cookie;
> +	last_complete = chan->completed_cookie;
> +
> +	dma_set_tx_state(txstate, last_complete, last_used, 0);
> +
> +	status = dma_async_is_complete(cookie, last_complete, last_used);
> +
> +	if (status != DMA_IN_PROGRESS)
> +		if (chan->error_cookie == cookie)
> +			status = DMA_ERROR;
> +
> +	return status;
> +}
same here
> +
> +static struct msm_dma_desc_sw *msm_dma_alloc_descriptor(
> +				struct msm_dma_chan *chan,
> +				int cmd_cnt,
> +				enum adm_dma_type mask)
> +{
> +	struct msm_dma_desc_sw *desc;
> +	dma_addr_t pdesc_addr;
> +	dma_addr_t paddr_cmd_list;
> +	void *err = NULL;
> +
> +	desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc_addr);
why atomic?
> +	if (!desc) {
> +		dev_dbg(chan->dev, "out of memory for desc\n");
> +		return ERR_CAST(desc);
> +	}
> +
> +	memset(desc, 0, sizeof(*desc));
> +	desc->async_tx.phys = pdesc_addr;
> +
> +	if (mask == ADM_BOX_MODE) {
> +		desc->coherent_size = sizeof(struct adm_box_cmd_t);
> +		desc->vaddr_box_cmd = dma_alloc_coherent(chan->dev,
> +				sizeof(struct adm_box_cmd_t),
> +				&paddr_cmd_list, GFP_ATOMIC);
> +		if (!desc->vaddr_box_cmd) {
> +			dev_dbg(chan->dev, "out of memory for desc\n");
> +			err = desc->vaddr_box_cmd;
> +			goto fail;
> +		}
> +	} else {
> +		desc->coherent_size = sizeof(struct adm_cmd_t)*cmd_cnt;
> +
> +		desc->vaddr_cmd = dma_alloc_coherent(chan->dev,
> +				sizeof(struct adm_cmd_t)*cmd_cnt,
> +				&paddr_cmd_list, GFP_ATOMIC);
> +
> +		if (!desc->vaddr_cmd) {
> +			dev_dbg(chan->dev, "out of memory for desc\n");
> +			err = desc->vaddr_cmd;
> +			goto fail;
> +		}
> +	}
> +
> +	dma_async_tx_descriptor_init(&desc->async_tx, &chan->channel);
> +	desc->async_tx.tx_submit = msm_dma_tx_submit;
> +	desc->paddr_cmd_list = paddr_cmd_list;
> +	desc->hw.cmd_list_ptr = (paddr_cmd_list >> 3) | CMD_PTR_LP;
> +	return desc;
> +fail:
> +	dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
> +	return ERR_CAST(err);
> +}
> +
> +/*
> + *  Prepares the transfer descriptors for SG transaction.
> + *  Returns
> + *	address of dma_async_tx_descriptor for success.
> + *	Pointer of error value for failure.
Kernel style is to use kernel-doc for this kind of description
> + */
> +static struct dma_async_tx_descriptor *msm_dma_prep_sg(
> +		struct dma_chan *dchan,
> +		struct scatterlist *dst_sg, unsigned int dst_nents,
> +		struct scatterlist *src_sg, unsigned int src_nents,
> +		unsigned long flags, void *context)
> +{
> +
> +	struct msm_dma_chan *chan;
> +	struct msm_dma_desc_sw *new;
> +	size_t copy, len;
> +	int cmd_cnt = 0;
> +	int first = 0;
> +	int i;
> +	dma_addr_t src;
> +	dma_addr_t dst;
> +	struct adm_cmd_t *cmdlist_vaddr;
> +	struct scatterlist *sg;
> +	struct msm_adm_cmd_config *cmd_config = context;
> +
> +	if (!dchan)
> +		return NULL;
> +
> +	if (dst_nents == 0 || src_nents == 0)
> +		return NULL;
> +	if (!dst_sg || !src_sg)
> +		return NULL;
> +
> +	if ((dst_nents != src_nents) || (cmd_config->num_cmd != src_nents))
> +		return NULL;
> +
> +	chan = to_msm_chan(dchan);
> +
> +	cmd_cnt = src_nents;
> +	for (i = 0; i < src_nents; i++) {
> +		len = sg_dma_len(src_sg + i);
> +		if (len != MAX_TRANSFER_LENGTH)
> +			cmd_cnt += len/MAX_TRANSFER_LENGTH;
> +	}
> +
> +	new = msm_dma_alloc_descriptor(chan, cmd_cnt, ADM_SG_MODE);
> +
> +	if (!new) {
> +		dev_err(chan->dev,
> +			"No free memory for link descriptor\n");
> +		return NULL;
> +	}
> +
> +	cmdlist_vaddr = new->vaddr_cmd;
> +
> +	for_each_sg(src_sg, sg, src_nents, i) {
> +		len = sg_dma_len(sg);
> +		src = sg_dma_address(sg);
> +		do {
> +			copy = (len >= MAX_TRANSFER_LENGTH) ?
> +						MAX_TRANSFER_LENGTH : len;
> +			cmdlist_vaddr->src = src;
> +			cmdlist_vaddr->len = copy;
> +			cmdlist_vaddr->cmd_cntrl =
> +					*(cmd_config->cmd_cntrl + i) &
> +							MSM_DMA_CMD_MASK;
> +			if (first == 0) {
> +				if (cmd_cnt == 1)
> +					cmdlist_vaddr->cmd_cntrl |= CMD_LC;
> +				else
> +					cmdlist_vaddr->cmd_cntrl |= CMD_OCB;
> +				first = 1;
> +			}
> +			cmdlist_vaddr++;
> +			len -= copy;
> +			src += copy;
> +		} while (len);
> +	}
> +	if (cmd_cnt > 1) {
> +		cmdlist_vaddr--;
> +		cmdlist_vaddr->cmd_cntrl |= CMD_LC | CMD_OCU;
> +	}
> +
> +	cmdlist_vaddr = new->vaddr_cmd;
> +
> +	for_each_sg(dst_sg, sg, src_nents, i) {
> +		len = sg_dma_len(sg);
> +		dst = sg_dma_address(sg);
> +		do {
> +			copy = (len >= MAX_TRANSFER_LENGTH) ?
> +					MAX_TRANSFER_LENGTH : len;
> +			cmdlist_vaddr->dst = dst;
> +			cmdlist_vaddr++;
> +			len -= copy;
> +			dst += copy;
> +		} while (len);
> +
> +	}
> +
> +#ifdef DEBUG
> +	cmdlist_vaddr = new->vaddr_cmd;
> +	i = 0;
> +	do {
> +		dev_dbg(chan->dev, "cmd %d src 0x%x dst 0x%x len 0x%x "
> +						"cntrl 0x%x\n",
> +				i, cmdlist_vaddr->src, cmdlist_vaddr->dst,
> +				cmdlist_vaddr->len, cmdlist_vaddr->cmd_cntrl);
> +			cmdlist_vaddr++;
> +	} while (!((cmdlist_vaddr-1)->cmd_cntrl & CMD_LC));
> +#endif
> +	new->async_tx.flags = flags;
> +	new->async_tx.cookie = -EBUSY;
> +
> +	return &new->async_tx;
> +}
> +
> +/*
> + *  Controlling the hardware channel like stopping, flushing.
> + */
> +static int msm_dma_chan_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> +							unsigned long arg)
> +{
> +	enum adm_flush_type cmd_type = arg;
> +
> +	if (cmd == DMA_TERMINATE_ALL) {
> +		switch (cmd_type) {
> +		case ADM_GRACEFUL_FLUSH:
> +				msm_dmov_stop_cmd(chan->chan_id, NULL, 1);
> +			break;
> +		case ADM_FORCED_FLUSH:
> +			/*
> +			 * We treate default as forced flush
> +			 * so we fall through
> +			 */
> +		default:
> +				msm_dmov_stop_cmd(chan->chan_id, NULL, 0);
> +			break;
> +		}
> +	}
No slave? How do you pass the peripheral properties like addr etc?

> +	return 0;
> +}


> +
> +MODULE_DESCRIPTION("Qualcomm DMA driver");
> +MODULE_LICENSE("GPL v2");
MODULE_ALIAS, OWNER, AUTHOR pls


-- 
~Vinod



From linus.walleij at linaro.org  Mon Mar 26 03:17:55 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 26 Mar 2012 09:17:55 +0200
Subject: [PATCH v5 2/2] DMAEngine: Add DMAEngine driver based on old MSM
 ADM DMA APIs
In-Reply-To: <1332426216-25273-1-git-send-email-kumarrav@codeaurora.org>
References: <1332426216-25273-1-git-send-email-kumarrav@codeaurora.org>
Message-ID: <CACRpkdbk=Hu6CzXSkkTgNsXGN0tPjfzLYfUpL8D5sxz2=efFxQ@mail.gmail.com>

On Thu, Mar 22, 2012 at 3:23 PM, Ravi Kumar V <kumarrav at codeaurora.org> wrote:

This stuff:

> +enum adm_flush_type {
> + ? ? ? ADM_FORCED_FLUSH,
> + ? ? ? ADM_GRACEFUL_FLUSH,
> +};

> +/*
> + * ?Controlling the hardware channel like stopping, flushing.
> + */
> +static int msm_dma_chan_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long arg)
> +{
> + ? ? ? enum adm_flush_type cmd_type = arg;
> +
> + ? ? ? if (cmd == DMA_TERMINATE_ALL) {
> + ? ? ? ? ? ? ? switch (cmd_type) {
> + ? ? ? ? ? ? ? case ADM_GRACEFUL_FLUSH:
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? msm_dmov_stop_cmd(chan->chan_id, NULL, 1);
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case ADM_FORCED_FLUSH:
> + ? ? ? ? ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ? ? ? ? ?* We treate default as forced flush
> + ? ? ? ? ? ? ? ? ? ? ? ?* so we fall through
> + ? ? ? ? ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? default:
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? msm_dmov_stop_cmd(chan->chan_id, NULL, 0);
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> + ? ? ? return 0;
> +}

This is an interesting way of using the opaque arg. Can you describe
the different semantics of graceful vs forced flush so we understand
the usecases for them?

DMA_TERMINATE_ALL is usually not very graceful.

DMA_PAUSE might be the semantic you're looking for as the
graceful path, and then you can do away with this strange
enum altogether.

Yours,
Linus Walleij


From vinod.koul at linux.intel.com  Mon Mar 26 03:24:11 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Mon, 26 Mar 2012 12:54:11 +0530
Subject: [PATCH v5 1/2] dmaengine: Add context parameter to prep_dma_sg
 and prep_interleaved_dma
In-Reply-To: <4F7012FC.10203@codeaurora.org>
References: <1332426167-25213-1-git-send-email-kumarrav@codeaurora.org>
 <1332743073.19804.26.camel@vkoul-udesk3>  <4F7012FC.10203@codeaurora.org>
Message-ID: <1332746651.19804.81.camel@vkoul-udesk3>

On Mon, 2012-03-26 at 12:25 +0530, Trilok Soni wrote:
> >
> > You need to
> > 1) add wrappers over interleaved api which dont expose this
> additional
> > parameter
> > 2) move existing users to use these wrappers
> 
> Above two steps would be exactly same as 
> https://lkml.org/lkml/2012/3/8/401 - [PATCH 1/2 V2]
> dmaengine/dma_slave: 
> introduce inline wrappers, right?
> 
> > 3) add a new API which has your additional argument (not an opaque
> > object) and this calls .device_xx callback with additional arg.
> > 4. Above can be under conditional of your specific subsystem where
> these
> > parameters are valid.
> 
> Now, this would be different from what Alexandre had submitted, since
> he 
> had added "void *context" parameter directly to existing callbacks 
> dma_slave_sg and and cyclic under struct dma_device.
In that case the wrappers existed, so he modified them and ensured all
clients use these and not the .device callbacks

So you need to create the new wrappers without any context parameter and
ensure all clients use these.
> 
> And you prefer that we add new callbacks under "struct dma_device"
> for 
> our specific requirement with new name and with that extra non-opaque 
> object. After that add wrappers for these two new callbacks say
> dmaengine_prep_dma_sg_ext and dmagengine_prep_interleaved_dma_ext
> (same
> name goes for callback).
> 
> 
-- 
~Vinod



From vinod.koul at linux.intel.com  Mon Mar 26 03:28:38 2012
From: vinod.koul at linux.intel.com (Vinod Koul)
Date: Mon, 26 Mar 2012 12:58:38 +0530
Subject: [PATCH v5 2/2] DMAEngine: Add DMAEngine driver based on old
 MSM ADM DMA APIs
In-Reply-To: <CACRpkdbk=Hu6CzXSkkTgNsXGN0tPjfzLYfUpL8D5sxz2=efFxQ@mail.gmail.com>
References: <1332426216-25273-1-git-send-email-kumarrav@codeaurora.org>
 <CACRpkdbk=Hu6CzXSkkTgNsXGN0tPjfzLYfUpL8D5sxz2=efFxQ@mail.gmail.com>
Message-ID: <1332746918.19804.84.camel@vkoul-udesk3>

On Mon, 2012-03-26 at 09:17 +0200, Linus Walleij wrote:
> On Thu, Mar 22, 2012 at 3:23 PM, Ravi Kumar V <kumarrav at codeaurora.org> wrote:
> 
> This stuff:
> 
> > +enum adm_flush_type {
> > +       ADM_FORCED_FLUSH,
> > +       ADM_GRACEFUL_FLUSH,
> > +};
> 
> > +/*
> > + *  Controlling the hardware channel like stopping, flushing.
> > + */
> > +static int msm_dma_chan_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> > +                                                       unsigned long arg)
> > +{
> > +       enum adm_flush_type cmd_type = arg;
> > +
> > +       if (cmd == DMA_TERMINATE_ALL) {
> > +               switch (cmd_type) {
> > +               case ADM_GRACEFUL_FLUSH:
> > +                               msm_dmov_stop_cmd(chan->chan_id, NULL, 1);
> > +                       break;
> > +               case ADM_FORCED_FLUSH:
> > +                       /*
> > +                        * We treate default as forced flush
> > +                        * so we fall through
> > +                        */
> > +               default:
> > +                               msm_dmov_stop_cmd(chan->chan_id, NULL, 0);
> > +                       break;
> > +               }
> > +       }
> > +       return 0;
> > +}
> 
> This is an interesting way of using the opaque arg. Can you describe
> the different semantics of graceful vs forced flush so we understand
> the usecases for them?
> 
> DMA_TERMINATE_ALL is usually not very graceful.
> 
> DMA_PAUSE might be the semantic you're looking for as the
> graceful path, and then you can do away with this strange
> enum altogether.
I am not a big fan of opaque objects. Btw client should use
dmaengine_terminate_all() only


-- 
~Vinod



From linux at arm.linux.org.uk  Mon Mar 26 03:37:04 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 26 Mar 2012 08:37:04 +0100
Subject: Inconsistent kallsyms data on ARM.
In-Reply-To: <4F6FB170.1040109@jonmasters.org>
References: <CAP=VYLoStscdVJretZ-Rkbp7V3Vsm8N0oWcjih7ruHFiDN7CiA@mail.gmail.com>
 <201203141321.47010.arnd@arndb.de>
 <20120325112035.GE5611@n2100.arm.linux.org.uk>
 <4F6FB170.1040109@jonmasters.org>
Message-ID: <20120326073704.GH5611@n2100.arm.linux.org.uk>

On Sun, Mar 25, 2012 at 07:59:44PM -0400, Jon Masters wrote:
> As to longer term, I am happy to work up something that will spot this
> particular kind of failure (symbol changes type) and output something
> more useful during the kallsyms generation if you would like.
> 
> Are you planning to pull in either of the fixes you mention?

I'm not, because those are all sub-optimal - I don't see why we should
bloat the kernel image just for the sake of working around kallsyms.

The best I've come up with so far which avoids that is to force
KALLSYMS_EXTRA_PASS to always be set on ARM.


From u.kleine-koenig at pengutronix.de  Mon Mar 26 03:45:33 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 26 Mar 2012 09:45:33 +0200
Subject: Inconsistent kallsyms data on ARM.
In-Reply-To: <20120326073704.GH5611@n2100.arm.linux.org.uk>
References: <CAP=VYLoStscdVJretZ-Rkbp7V3Vsm8N0oWcjih7ruHFiDN7CiA@mail.gmail.com>
 <201203141321.47010.arnd@arndb.de>
 <20120325112035.GE5611@n2100.arm.linux.org.uk>
 <4F6FB170.1040109@jonmasters.org>
 <20120326073704.GH5611@n2100.arm.linux.org.uk>
Message-ID: <20120326074533.GL15647@pengutronix.de>

Hello,

On Mon, Mar 26, 2012 at 08:37:04AM +0100, Russell King - ARM Linux wrote:
> On Sun, Mar 25, 2012 at 07:59:44PM -0400, Jon Masters wrote:
> > As to longer term, I am happy to work up something that will spot this
> > particular kind of failure (symbol changes type) and output something
> > more useful during the kallsyms generation if you would like.
> > 
> > Are you planning to pull in either of the fixes you mention?
> 
> I'm not, because those are all sub-optimal - I don't see why we should
> bloat the kernel image just for the sake of working around kallsyms.
> 
> The best I've come up with so far which avoids that is to force
> KALLSYMS_EXTRA_PASS to always be set on ARM.
Just to let you know: I even saw failures with KALLSYMS_EXTRA_PASS set.
Not so in the recent past and sometimes not even reproducible IIRC.
I will save the build results next time it happens now that I saw what
to look for.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From a.p.zijlstra at chello.nl  Mon Mar 26 03:59:06 2012
From: a.p.zijlstra at chello.nl (Peter Zijlstra)
Date: Mon, 26 Mar 2012 09:59:06 +0200
Subject: [PATCH v2.1 01/10] cpu: Introduce clear_tasks_mm_cpumask() helper
In-Reply-To: <20120325174210.GA23605@redhat.com>
References: <20120324102609.GA28356@lizard> <20120324102751.GA29067@lizard>
 <1332593021.16159.27.camel@twins> <20120324164316.GB3640@lizard>
 <20120325174210.GA23605@redhat.com>
Message-ID: <1332748746.16159.62.camel@twins>

On Sun, 2012-03-25 at 19:42 +0200, Oleg Nesterov wrote:
> __cpu_disable() is called by __stop_machine(), we know that nobody
> can preempt us and other CPUs can do nothing. 

It would be very good to not rely on that though, I would love to get
rid of the stop_machine usage in cpu hotplug some day.


From linus.walleij at stericsson.com  Mon Mar 26 04:01:08 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 26 Mar 2012 10:01:08 +0200
Subject: [PATCH] serial: pl011: implement workaround for CTS clear event issue
Message-ID: <1332748868-10172-1-git-send-email-linus.walleij@stericsson.com>

From: "Rajanikanth H.V" <rajanikanth.hv at stericsson.com>

Problem Observed:
- interrupt status is set by rising or falling edge on CTS line
- interrupt status is cleared on a .0. to .1. transition of the
  interrupt-clear register bit 1.
- interrupt-clear register is reset by hardware once the interrupt
  status is .0..
  Remark: It seems not possible to read this register back by the
  CPU though, but internally this register exists.
- when simultaneous set and reset event on the interrupt status
  happens, then the set-event has priority and the status remains
  .1.. As a result the interrupt-clear register is not reset to
  .0., and no new .0. to .1. transition can be detected on it when
  writing a .1. to it.
  This implies race condition, the clear must be performed at least
  one UARTCLK the riding edge of CTS RIS interrupt.

Fix:
  Instead of resetting UART as done in commit
  c16d51a32bbb61ac8fd96f78b5ce2fccfe0fb4c3
  "amba pl011: workaround for uart registers lockup" do the
  following:

  write .0. and then  .1. to the interrupt-clear register to make
  sure that this transition is detected. According to the datasheet
  writing a .0. does not have any effect, but actually it allows to
  reset the internal interrupt-clear register.

  Take into account:
  The .0. needs to last at least for one clk_uart clock period
  (~ 38 MHz, 26.08ns)

This way we can do away with the tasklet and keep only a tiny
fix triggered by the variant flag introduced in this patch.

Signed-off-by: Guillaume Jaunet <guillaume.jaunet at stericsson.com>
Signed-off-by: Christophe Arnal <christophe.arnal at stericsson.com>
Signed-off-by: Matthias Locher  <Matthias.Locher at stericsson.com>
Signed-off-by: Rajanikanth H.V <rajanikanth.hv at stericsson.com>
Reviewed-by: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
 drivers/tty/serial/amba-pl011.c |  114 +++++++--------------------------------
 1 file changed, 18 insertions(+), 96 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 4ed35c5..e48211d 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -61,35 +61,9 @@
 #define SERIAL_AMBA_MINOR	64
 #define SERIAL_AMBA_NR		UART_NR
 
-#define AMBA_ISR_PASS_LIMIT	256
-
 #define UART_DR_ERROR		(UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
 #define UART_DUMMY_DR_RX	(1 << 16)
 
-
-#define UART_WA_SAVE_NR 14
-
-static void pl011_lockup_wa(unsigned long data);
-static const u32 uart_wa_reg[UART_WA_SAVE_NR] = {
-	ST_UART011_DMAWM,
-	ST_UART011_TIMEOUT,
-	ST_UART011_LCRH_RX,
-	UART011_IBRD,
-	UART011_FBRD,
-	ST_UART011_LCRH_TX,
-	UART011_IFLS,
-	ST_UART011_XFCR,
-	ST_UART011_XON1,
-	ST_UART011_XON2,
-	ST_UART011_XOFF1,
-	ST_UART011_XOFF2,
-	UART011_CR,
-	UART011_IMSC
-};
-
-static u32 uart_wa_regdata[UART_WA_SAVE_NR];
-static DECLARE_TASKLET(pl011_lockup_tlet, pl011_lockup_wa, 0);
-
 /* There is by now at least one vendor with differing details, so handle it */
 struct vendor_data {
 	unsigned int		ifls;
@@ -99,6 +73,7 @@ struct vendor_data {
 	bool			oversampling;
 	bool			interrupt_may_hang;   /* vendor-specific */
 	bool			dma_threshold;
+	bool			cts_event_workaround;
 };
 
 static struct vendor_data vendor_arm = {
@@ -108,6 +83,7 @@ static struct vendor_data vendor_arm = {
 	.lcrh_rx		= UART011_LCRH,
 	.oversampling		= false,
 	.dma_threshold		= false,
+	.cts_event_workaround	= false,
 };
 
 static struct vendor_data vendor_st = {
@@ -118,6 +94,7 @@ static struct vendor_data vendor_st = {
 	.oversampling		= true,
 	.interrupt_may_hang	= true,
 	.dma_threshold		= true,
+	.cts_event_workaround	= true,
 };
 
 static struct uart_amba_port *amba_ports[UART_NR];
@@ -1038,69 +1015,6 @@ static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
 #define pl011_dma_flush_buffer	NULL
 #endif
 
-
-/*
- * pl011_lockup_wa
- * This workaround aims to break the deadlock situation
- * when after long transfer over uart in hardware flow
- * control, uart interrupt registers cannot be cleared.
- * Hence uart transfer gets blocked.
- *
- * It is seen that during such deadlock condition ICR
- * don't get cleared even on multiple write. This leads
- * pass_counter to decrease and finally reach zero. This
- * can be taken as trigger point to run this UART_BT_WA.
- *
- */
-static void pl011_lockup_wa(unsigned long data)
-{
-	struct uart_amba_port *uap = amba_ports[0];
-	void __iomem *base = uap->port.membase;
-	struct circ_buf *xmit = &uap->port.state->xmit;
-	struct tty_struct *tty = uap->port.state->port.tty;
-	int buf_empty_retries = 200;
-	int loop;
-
-	/* Stop HCI layer from submitting data for tx */
-	tty->hw_stopped = 1;
-	while (!uart_circ_empty(xmit)) {
-		if (buf_empty_retries-- == 0)
-			break;
-		udelay(100);
-	}
-
-	/* Backup registers */
-	for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
-		uart_wa_regdata[loop] = readl(base + uart_wa_reg[loop]);
-
-	/* Disable UART so that FIFO data is flushed out */
-	writew(0x00, uap->port.membase + UART011_CR);
-
-	/* Soft reset UART module */
-	if (uap->port.dev->platform_data) {
-		struct amba_pl011_data *plat;
-
-		plat = uap->port.dev->platform_data;
-		if (plat->reset)
-			plat->reset();
-	}
-
-	/* Restore registers */
-	for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
-		writew(uart_wa_regdata[loop] ,
-				uap->port.membase + uart_wa_reg[loop]);
-
-	/* Initialise the old status of the modem signals */
-	uap->old_status = readw(uap->port.membase + UART01x_FR) &
-		UART01x_FR_MODEM_ANY;
-
-	if (readl(base + UART011_MIS) & 0x2)
-		printk(KERN_EMERG "UART_BT_WA: ***FAILED***\n");
-
-	/* Start Tx/Rx */
-	tty->hw_stopped = 0;
-}
-
 static void pl011_stop_tx(struct uart_port *port)
 {
 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
@@ -1227,14 +1141,28 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
 {
 	struct uart_amba_port *uap = dev_id;
 	unsigned long flags;
-	unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
+	unsigned int status;
 	int handled = 0;
+	unsigned int dummy_read;
 
 	spin_lock_irqsave(&uap->port.lock, flags);
 
 	status = readw(uap->port.membase + UART011_MIS);
 	if (status) {
 		do {
+			if (uap->vendor->cts_event_workaround) {
+				/* workaround to make sure that all bits are unlocked.. */
+				writew(0x00, uap->port.membase + UART011_ICR);
+
+				/*
+				 * WA: introduce 26ns(1 uart clk) delay before W1C;
+				 * single apb access will incur 2 pclk(133.12Mhz) delay,
+				 * so add 2 dummy reads
+				 */
+				dummy_read = readw(uap->port.membase + UART011_ICR);
+				dummy_read = readw(uap->port.membase + UART011_ICR);
+			}
+
 			writew(status & ~(UART011_TXIS|UART011_RTIS|
 					  UART011_RXIS),
 			       uap->port.membase + UART011_ICR);
@@ -1251,12 +1179,6 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
 			if (status & UART011_TXIS)
 				pl011_tx_chars(uap);
 
-			if (pass_counter-- == 0) {
-				if (uap->interrupt_may_hang)
-					tasklet_schedule(&pl011_lockup_tlet);
-				break;
-			}
-
 			status = readw(uap->port.membase + UART011_MIS);
 		} while (status != 0);
 		handled = 1;
-- 
1.7.9.2



From afzal at ti.com  Mon Mar 26 04:04:50 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 26 Mar 2012 08:04:50 +0000
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <4F6D0569.6080203@ti.com>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
 <4F6D0569.6080203@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A9317BB895@DBDE01.ent.ti.com>

Hi Jon,

On Sat, Mar 24, 2012 at 04:51:13, Hunter, Jon wrote:
> > +struct gpmc_child {
> > +	char			*name;
> > +	int			id;
> > +	struct resource		*res;
> > +	unsigned		num_res;
> > +	struct resource		gpmc_res[GPMC_CS_NUM];
> 
> Does this imply a gpmc child device can use more than one chip-select? I 
> am trying to understand the link between number of resources and 
> GPMC_CS_NUM.

Yes, relevant portion in commit message as follows,

A peripheral connected to GPMC can have multiple
address spaces using different chip select. Hence
GPMC driver has been provided capability to
distinguish this scenario, i.e. create platform
devices only once for each connected peripheral,
and not for each configured chip select. The
peripheral that made it necessary was tusb6010.


> 
> > +	unsigned		gpmc_num_res;
> > +	void			*pdata;
> > +	unsigned		pdata_size;
> > +};
> 
> Does pdata_size need to be stored? If pdata is always of type 
> gpmc_device_pdata then you could avoid using void * and elsewhere use 
> sizeof.

This is the size of platform data of peripheral connected to GPMC,
like NAND.

> > -	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> > -	__raw_writel(val, reg_addr);
> > +	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
> > +	writel(val, reg_addr);
> >   }
> 
> I understand this was inherited from the original code, but I think that 
> we should drop the "GPMC_CS0_OFFSET". We are already passing an index 
> and so we should use this as an offset. This obviously implies changing 
> the defintion of the GPMC_CS_xxxx registers in gpmc.h. This would save 
> one addition too.

Ok

> > +/* This is a duplication of an existing function; before GPMC probe
> > +   invocation, platform code may need to find divider value, hence
> > +   other function (gpmc_cs_calc_divider) is not removed, functions
> > +   like it that are required by platform, probably can be put in
> > +   common omap platform file. gpmc_calc_divider will get invoked
> > +   only after GPMC driver gets probed. gpmc_cs_calc_divider is not
> > +   invoked by GPMC driver to cleanly separate platform&  driver
> > +   code, although both should return sme value.
> >    */
> > -int gpmc_nand_read(int cs, int cmd)
> > +static int gpmc_calc_divider(u32 sync_clk)
> >   {
> > -	int rval = -EINVAL;
> > -
> > -	switch (cmd) {
> > -	case GPMC_NAND_DATA:
> > -		rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
> > -		break;
> > +	int div;
> > +	u32 l;
> >
> > -	default:
> > -		printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
> > -	}
> > -	return rval;
> > +	l = sync_clk + (gpmc->fclk_rate - 1);
> 
> This was a little confusing to me at first. When I see fclk_rate I think 
> frequency (eg. clk_get_rate()) and not period. The original code had a 
> function called gpmc_get_fclk_period. I would consider renaming the 
> variable to fclk_period to be clear.

Agree

> > +#define GPMC_SET_ONE(reg, st, end, field) \
> 
> Nit-pick, set-one is a bit generic, maybe GPMC_SET_TIME?

Agree

> > +	if (cpu_is_omap34xx()) {
> > +		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
> > +		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
> > +	}
> 
> OMAP4/5 also has the above fields and so maybe this should be 
> (!cpu_is_omap24xx()).

Will try to remove the usage of cpu_is_xxx itself

> 
> > +
> > +	/* caller is expected to have initialized CONFIG1 to cover
> > +	 * at least sync vs async
> > +	 */
> > +	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
> > +	if (l&  (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
> 
> Is it valid to have READTYPE != WRITETYPE? I am wondering if there 
> should be a check here to see if READTYPE and WRITETYPE are not equal?

Seems possible, but not sure, will look into this
 
> > +		printk(KERN_DEBUG "GPMC CS%d CLK period is %lu ns (div %d)\n",
> > +				cs, (div * gpmc_get_fclk_period()) / 1000, div);
> > +		l&= ~0x03;
> 
> I think we should define GPMC_CONFIG1_FCLK_DIV_MASK for this.

Ok

> +	*base = (l&  0x3f)<<  GPMC_CHUNK_SHIFT;
> 
> Define GPMC_CONFIG7_BASEADDRESS_MASK

Ok

> > +	mask = (l>>  8)&  0x0f;
> 
> Define GPMC_CONFIG7_MASKADDRESS_MASK/SHIFT

Ok

> > +static __devinit int gpmc_setup_child(struct gpmc_device_pdata *gdev)
> 
> Nit-pick, gdev was a bit confusing to me, maybe just pdata instead?

Ok

> > +		gpmc->child_device[i].gpmc_res[j] = res;
> 
> So struct "res" is a local variable and you are storing in a global 
> structure? Did you intend to store the address of the pdata struct passed?


No, copy res structure

> > +	gpmc->ecc_used = -EINVAL;
> 
> Why not 0?

That may modify default behavior of OMAP NAND driver w.r.t ECC,
will check this.
 
> > +	spin_lock_init(&gpmc->mem_lock);
> > +	platform_set_drvdata(pdev, gpmc);
> >
> >   	l = gpmc_read_reg(GPMC_REVISION);
> > -	printk(KERN_INFO "GPMC revision %d.%d\n", (l>>  4)&  0x0f, l&  0x0f);
> > -	/* Set smart idle mode and automatic L3 clock gating */
> > -	l = gpmc_read_reg(GPMC_SYSCONFIG);
> > -	l&= 0x03<<  3;
> > -	l |= (0x02<<  3) | (1<<  0);
> > -	gpmc_write_reg(GPMC_SYSCONFIG, l);
> 
> Really need to clean up the above with some #defines. Ideally we would 
> be using hwmod/pm_runtime for configuring the SYSCONFIG.

Ok

> Do we need to free irqs here?

Irqs has been conveniently forgotten in this patch, in mainline, I could
not find any platforms using GPMC irq. This can be added later once
driver conversion is done, if required.

> > +		gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs<<  CS_NUM_SHIFT) |
> > +					PREFETCH_FIFOTHRESHOLD(fifo_th) |
> > +					ENABLE_PREFETCH |
> > +					(dma_mode<<  DMA_MPU_MODE) |
> > +					(0x1&  is_write)));
> 
> #define GPMC_PREFETCH_CONFIG1_ACCESSMODE

Ok

> > +	/* check if the same module/cs is trying to reset */
> > +	config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
> > +	if (((config1>>  CS_NUM_SHIFT)&  0x7) != cs)
> 
> Maybe define a mask value for the ENGINECSSELECTOR

Ok

> > +	/* GPMC specific */
> > +	unsigned		cs;
> > +	unsigned long		mem_size;
> > +	unsigned long		mem_start;
> > +	unsigned long		mem_offset;
> > +	struct gpmc_config	*config;
> > +	unsigned		num_config;
> > +	struct gpmc_timings	*timing;
> > +};
> > +
> > +struct gpmc_pdata {
> > +	/* GPMC_FCLK rate in picoseconds */
> > +	unsigned long			fclk_rate;
> 
> fclk_period
> 
> > +	struct gpmc_device_pdata	*device_pdata;
> > +	unsigned			num_device;
> > +};
> 
> Do you need both gpmc_pdata and gpmc_device_pdata? Would not a single 
> structure work?

Gpmc_device_data is dedicated to each CS, gpmc_pdata is required
at least to inform driver about clock rate.

Generally, as the change involved moving a lot of code, seems more reviews
are on those than the actual changes than what I intended to get reviewed,
next patch series will be modified not to move existing code, hence some
of your suggested changes may not be present in it, probably those to be
done as another cleanup patch.

Regards
Afzal


From linux at arm.linux.org.uk  Mon Mar 26 04:17:56 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 26 Mar 2012 09:17:56 +0100
Subject: [PATCH] serial: pl011: implement workaround for CTS clear
 event issue
In-Reply-To: <1332748868-10172-1-git-send-email-linus.walleij@stericsson.com>
References: <1332748868-10172-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20120326081756.GI5611@n2100.arm.linux.org.uk>

On Mon, Mar 26, 2012 at 10:01:08AM +0200, Linus Walleij wrote:
> -	unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
> +	unsigned int status;

Why are you removing the pass counter and associated code, which was
there before your work-around patch was applied?


From linux at arm.linux.org.uk  Mon Mar 26 04:32:56 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 26 Mar 2012 09:32:56 +0100
Subject: [PATCH 6/6] ARM: OMAP: fix cpufreq build
In-Reply-To: <E1S87xU-0000N8-6u@rmk-PC.arm.linux.org.uk>
References: <20120315102845.GB16389@n2100.arm.linux.org.uk>
 <E1S87xU-0000N8-6u@rmk-PC.arm.linux.org.uk>
Message-ID: <20120326083256.GC22608@n2100.arm.linux.org.uk>

Kevin,

I only just found this via the arm-soc tree, while trying to merge the
kautobuildv2 build tree.

You changed my patch and broke it:

config ARM_OMAP2PLUS_CPUFREQ
        bool "TI OMAP2+"
        default ARCH_OMAP2PLUS
        select CPU_FREQ_TABLE

So now, OMAP2 CPUFREQ is selectable on ANYTHING but it will only build
successfully on OMAP.

If you're going to change someone elses patch, do them the favour of
re-posting it back to them for comment *BEFORE* you commit it and send
it upstream, rather than making it look like they're a total tosser for
authoring a patch which fucks up other architecture builds.

Many thanks for that.

On Thu, Mar 15, 2012 at 10:31:00AM +0000, Russell King wrote:
> OMAPs cpufreq requires the frequency table support, but nothing ensures
> that this is selected.  This can result in configurations which fail to
> build:
> 
> drivers/built-in.o:(.data+0x5238): undefined reference to `cpufreq_freq_attr_scaling_available_freqs'
> drivers/cpufreq/omap-cpufreq.c:88: undefined reference to `cpufreq_frequency_table_target'
> drivers/cpufreq/omap-cpufreq.c:60: undefined reference to `cpufreq_frequency_table_verify'
> drivers/cpufreq/omap-cpufreq.c:186: undefined reference to `cpufreq_frequency_table_cpuinfo'
> drivers/cpufreq/omap-cpufreq.c:190: undefined reference to `cpufreq_frequency_table_get_attr'
> 
> Fix this by introducing a new configuration variable and having that
> select CPU_FREQ_TABLE.
> 
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---
>  arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c |    2 +-
>  arch/arm/mach-omap2/clock.c                  |    2 +-
>  arch/arm/mach-omap2/clock.h                  |    2 +-
>  arch/arm/plat-omap/clock.c                   |    2 +-
>  arch/arm/plat-omap/include/plat/clock.h      |    4 ++--
>  drivers/cpufreq/Kconfig.arm                  |    5 +++++
>  drivers/cpufreq/Makefile                     |    2 +-
>  7 files changed, 12 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> index 39f9d5a..4705b50 100644
> --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> @@ -165,7 +165,7 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
>  	return 0;
>  }
>  
> -#ifdef CONFIG_CPU_FREQ
> +#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
>  /*
>   * Walk PRCM rate table and fillout cpufreq freq_table
>   * XXX This should be replaced by an OPP layer in the near future
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index f57ed5b..450feb0 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -536,7 +536,7 @@ struct clk_functions omap2_clk_functions = {
>  	.clk_set_rate		= omap2_clk_set_rate,
>  	.clk_set_parent		= omap2_clk_set_parent,
>  	.clk_disable_unused	= omap2_clk_disable_unused,
> -#ifdef CONFIG_CPU_FREQ
> +#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
>  	/* These will be removed when the OPP code is integrated */
>  	.clk_init_cpufreq_table	= omap2_clk_init_cpufreq_table,
>  	.clk_exit_cpufreq_table	= omap2_clk_exit_cpufreq_table,
> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
> index b8c2a68..f331cfc 100644
> --- a/arch/arm/mach-omap2/clock.h
> +++ b/arch/arm/mach-omap2/clock.h
> @@ -146,7 +146,7 @@ extern const struct clksel_rate gpt_sys_rates[];
>  extern const struct clksel_rate gfx_l3_rates[];
>  extern const struct clksel_rate dsp_ick_rates[];
>  
> -#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
> +#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_ARM_OMAP2PLUS_CPUFREQ)
>  extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
>  extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
>  #else
> diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
> index 567e4b5..2e2efb6 100644
> --- a/arch/arm/plat-omap/clock.c
> +++ b/arch/arm/plat-omap/clock.c
> @@ -399,7 +399,7 @@ struct clk dummy_ck = {
>  	.ops	= &clkops_null,
>  };
>  
> -#ifdef CONFIG_CPU_FREQ
> +#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
>  void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
>  {
>  	unsigned long flags;
> diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
> index 240a7b9..879ba27 100644
> --- a/arch/arm/plat-omap/include/plat/clock.h
> +++ b/arch/arm/plat-omap/include/plat/clock.h
> @@ -283,7 +283,7 @@ struct clk_functions {
>  	void		(*clk_allow_idle)(struct clk *clk);
>  	void		(*clk_deny_idle)(struct clk *clk);
>  	void		(*clk_disable_unused)(struct clk *clk);
> -#ifdef CONFIG_CPU_FREQ
> +#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
>  	void		(*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
>  	void		(*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
>  #endif
> @@ -301,7 +301,7 @@ extern void recalculate_root_clocks(void);
>  extern unsigned long followparent_recalc(struct clk *clk);
>  extern void clk_enable_init_clocks(void);
>  unsigned long omap_fixed_divisor_recalc(struct clk *clk);
> -#ifdef CONFIG_CPU_FREQ
> +#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
>  extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
>  extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
>  #endif
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index c8bde43..74e8b55 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -2,6 +2,11 @@
>  # ARM CPU Frequency scaling drivers
>  #
>  
> +config ARM_OMAP2PLUS_CPUFREQ
> +	bool
> +	depends on ARCH_OMAP2PLUS
> +	select CPU_FREQ_TABLE
> +
>  config ARM_S3C64XX_CPUFREQ
>  	bool "Samsung S3C64XX"
>  	depends on CPU_S3C6410
> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> index ac000fa..fda94c7 100644
> --- a/drivers/cpufreq/Makefile
> +++ b/drivers/cpufreq/Makefile
> @@ -44,7 +44,7 @@ obj-$(CONFIG_ARM_S3C64XX_CPUFREQ)	+= s3c64xx-cpufreq.o
>  obj-$(CONFIG_ARM_S5PV210_CPUFREQ)	+= s5pv210-cpufreq.o
>  obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
>  obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
> -obj-$(CONFIG_ARCH_OMAP2PLUS)            += omap-cpufreq.o
> +obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)     += omap-cpufreq.o
>  
>  ##################################################################################
>  # PowerPC platform drivers
> -- 
> 1.7.4.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From arnd at arndb.de  Mon Mar 26 04:39:46 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 26 Mar 2012 08:39:46 +0000
Subject: Inconsistent kallsyms data on ARM.
In-Reply-To: <20120326074533.GL15647@pengutronix.de>
References: <CAP=VYLoStscdVJretZ-Rkbp7V3Vsm8N0oWcjih7ruHFiDN7CiA@mail.gmail.com>
 <20120326073704.GH5611@n2100.arm.linux.org.uk>
 <20120326074533.GL15647@pengutronix.de>
Message-ID: <201203260839.46858.arnd@arndb.de>

On Monday 26 March 2012, Uwe Kleine-K?nig wrote:
> On Mon, Mar 26, 2012 at 08:37:04AM +0100, Russell King - ARM Linux wrote:
> > On Sun, Mar 25, 2012 at 07:59:44PM -0400, Jon Masters wrote:
> > > As to longer term, I am happy to work up something that will spot this
> > > particular kind of failure (symbol changes type) and output something
> > > more useful during the kallsyms generation if you would like.
> > > 
> > > Are you planning to pull in either of the fixes you mention?
> > 
> > I'm not, because those are all sub-optimal - I don't see why we should
> > bloat the kernel image just for the sake of working around kallsyms.
> > 
> > The best I've come up with so far which avoids that is to force
> > KALLSYMS_EXTRA_PASS to always be set on ARM.
> Just to let you know: I even saw failures with KALLSYMS_EXTRA_PASS set.
> Not so in the recent past and sometimes not even reproducible IIRC.
> I will save the build results next time it happens now that I saw what
> to look for.

Yes, I saw these too in my randconfig builds some time ago. Maybe a handful
of builds among 50000 configurations.

	Arnd


From thomas.abraham at linaro.org  Mon Mar 26 04:46:38 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 26 Mar 2012 14:16:38 +0530
Subject: [PATCH v3 0/2] Add lcd driver for panels with gpio controlled panel
 reset
Message-ID: <1332751600-11371-1-git-send-email-thomas.abraham@linaro.org>

Changes since v2:
- Reworked as per comments[1] from Mark Brown.
  - removed the setting of regulator voltage.

[1] http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg08743.html

Changes since v1:
- Fixed gpio leak, added MODULE_DEVICE_TABLE and dev_pm_ops.
- Changed device tree bindings.

This patchset adds support for passive panels that use a nRESET line which is
controlled by a GPIO of the host system and which do not use a serial comamnd
interface (i2c or spi) or memory-mapped-io interface. Platforms that do not
require any additional control apart from the nRESET line can use this driver
for lcd power control.

The first patch adds driver for passive raster-type lcd's with gpio controlled
panel reset. It includes support for both dt and non-dt platforms. The second
patch adds support for using this driver on Origen board.

Thomas Abraham (2):
  backlight: lcd: add driver for raster-type lcd's with gpio controlled panel reset
  ARM: Exynos: Use lcd power control driver for lcd panel

 .../devicetree/bindings/lcd/lcd-pwrctrl.txt        |   36 +++
 arch/arm/mach-exynos/mach-origen.c                 |   29 +--
 drivers/video/backlight/Kconfig                    |    7 +
 drivers/video/backlight/Makefile                   |    1 +
 drivers/video/backlight/lcd_pwrctrl.c              |  226 ++++++++++++++++++++
 include/video/lcd_pwrctrl.h                        |   24 ++
 6 files changed, 300 insertions(+), 23 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/lcd/lcd-pwrctrl.txt
 create mode 100644 drivers/video/backlight/lcd_pwrctrl.c
 create mode 100644 include/video/lcd_pwrctrl.h



From thomas.abraham at linaro.org  Mon Mar 26 04:46:39 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 26 Mar 2012 14:16:39 +0530
Subject: [PATCH v3 1/2] backlight: lcd: add driver for raster-type lcd's with
 gpio controlled panel reset
In-Reply-To: <1332751600-11371-1-git-send-email-thomas.abraham@linaro.org>
References: <1332751600-11371-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332751600-11371-2-git-send-email-thomas.abraham@linaro.org>

Add a lcd panel driver for simple raster-type lcd's which uses a gpio
controlled panel reset. The driver controls the nRESET line of the panel
using a gpio connected from the host system. The Vcc supply to the panel
is (optionally) controlled using a voltage regulator. This driver excludes
support for lcd panels that use a serial command interface or direct
memory mapped IO interface.

Suggested-by: Lars-Peter Clausen <lars at metafoo.de>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 .../devicetree/bindings/lcd/lcd-pwrctrl.txt        |   36 +++
 drivers/video/backlight/Kconfig                    |    7 +
 drivers/video/backlight/Makefile                   |    1 +
 drivers/video/backlight/lcd_pwrctrl.c              |  226 ++++++++++++++++++++
 include/video/lcd_pwrctrl.h                        |   24 ++
 5 files changed, 294 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/lcd/lcd-pwrctrl.txt
 create mode 100644 drivers/video/backlight/lcd_pwrctrl.c
 create mode 100644 include/video/lcd_pwrctrl.h

diff --git a/Documentation/devicetree/bindings/lcd/lcd-pwrctrl.txt b/Documentation/devicetree/bindings/lcd/lcd-pwrctrl.txt
new file mode 100644
index 0000000..22604a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/lcd/lcd-pwrctrl.txt
@@ -0,0 +1,36 @@
+* Power controller for simple lcd panels
+
+Some LCD panels provide a simple control interface for the host system. The
+control mechanism would include a nRESET line connected to a gpio of the host
+system and a Vcc supply line which the host can optionally be controlled using
+a voltage regulator. Such simple panels do not support serial command
+interface (such as i2c or spi) or memory-mapped-io interface.
+
+Required properties:
+- compatible: should be 'lcd-powercontrol'
+
+- lcd-reset-gpio: The GPIO number of the host system used to control the
+  nRESET line. The format of the gpio specifier depends on the gpio controller
+  of the host system.
+
+Optional properties:
+- lcd-reset-active-high: When the nRESET line is asserted low, the lcd panel
+  is reset and stays in reset mode as long as the nRESET line is asserted low.
+  This is the default behaviour of most lcd panels. If a lcd panel requires the
+  nRESET line to be asserted high for panel reset, then this property is used.
+  Note: Some platforms might allow inverting the polarity of the gpio output
+  in the 'lcd-reset-gpio' gpio specifier. On such platforms, if the polarity
+  is used to control the output of the gpio, then this property should not be
+  used.
+
+- vcc-lcd-supply: phandle of the regulator that controls the vcc supply to
+  the lcd panel.
+
+Example:
+
+	lcd_pwrctrl {
+		compatible = "lcd-powercontrol";
+		lcd-reset-gpio = <&gpe0 4 1 0 0>;
+		lcd-reset-active-high;
+		lcd-vcc-supply = <&regulator7>;
+	};
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index 681b369..9b52ea8 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -86,6 +86,13 @@ config LCD_PLATFORM
 	  This driver provides a platform-device registered LCD power
 	  control interface.
 
+config LCD_PWRCTRL
+	tristate "LCD panel power control"
+	help
+	  Say y here, if you have a lcd panel that allows reset and vcc to be
+	  controlled by the host system, and which does not use a serial command
+	  interface (such as i2c or spi) or memory-mapped-io interface.
+
 config LCD_TOSA
 	tristate "Sharp SL-6000 LCD Driver"
 	depends on SPI && MACH_TOSA
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index af5cf65..d85c8d2 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_LCD_LMS283GF05)	   += lms283gf05.o
 obj-$(CONFIG_LCD_LTV350QV)	   += ltv350qv.o
 obj-$(CONFIG_LCD_ILI9320)	   += ili9320.o
 obj-$(CONFIG_LCD_PLATFORM)	   += platform_lcd.o
+obj-$(CONFIG_LCD_PWRCTRL)	   += lcd_pwrctrl.o
 obj-$(CONFIG_LCD_VGG2432A4)	   += vgg2432a4.o
 obj-$(CONFIG_LCD_TDO24M)	   += tdo24m.o
 obj-$(CONFIG_LCD_TOSA)		   += tosa_lcd.o
diff --git a/drivers/video/backlight/lcd_pwrctrl.c b/drivers/video/backlight/lcd_pwrctrl.c
new file mode 100644
index 0000000..917d842
--- /dev/null
+++ b/drivers/video/backlight/lcd_pwrctrl.c
@@ -0,0 +1,226 @@
+/*
+ * Simple lcd panel power control driver.
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ *
+ * This driver is for controlling power for raster type lcd panels that requires
+ * its nRESET interface line to be connected and controlled by a GPIO of the
+ * host system and the Vcc line controlled by a voltage regulator.  This
+ * excludes support for lcd panels that use a serial command interface or direct
+ * memory mapped IO interface.
+ *
+ * The nRESET interface line of the panel should be connected to a gpio of the
+ * host system. The Vcc pin is controlled using a external volatage regulator.
+ * Panel backlight is not controlled by this driver.
+ *
+ * This driver is derived from platform-lcd.c which was written by
+ * Ben Dooks <ben at simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+#include <linux/lcd.h>
+#include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/regulator/consumer.h>
+#include <video/lcd_pwrctrl.h>
+
+struct lcd_pwrctrl {
+	struct device		*dev;
+	struct lcd_device	*lcd;
+	struct lcd_pwrctrl_data	*pdata;
+	struct regulator	*regulator;
+	unsigned int		power;
+	bool			suspended;
+	bool			pwr_en;
+};
+
+static int lcd_pwrctrl_get_power(struct lcd_device *lcd)
+{
+	struct lcd_pwrctrl *lp = lcd_get_data(lcd);
+	return lp->power;
+}
+
+static int lcd_pwrctrl_set_power(struct lcd_device *lcd, int power)
+{
+	struct lcd_pwrctrl *lp = lcd_get_data(lcd);
+	struct lcd_pwrctrl_data *pd = lp->pdata;
+	bool lcd_enable;
+	int lcd_reset, ret = 0;
+
+	lcd_enable = (power == FB_BLANK_POWERDOWN || lp->suspended) ? 0 : 1;
+	lcd_reset = (pd->invert) ? !lcd_enable : lcd_enable;
+
+	if (lp->pwr_en == lcd_enable)
+		return 0;
+
+	if (!IS_ERR_OR_NULL(lp->regulator)) {
+		if (lcd_enable) {
+			if (regulator_enable(lp->regulator)) {
+				dev_info(lp->dev, "regulator enable failed\n");
+				ret = -EPERM;
+			}
+		} else {
+			if (regulator_disable(lp->regulator)) {
+				dev_info(lp->dev, "regulator disable failed\n");
+				ret = -EPERM;
+			}
+		}
+	}
+
+	gpio_direction_output(lp->pdata->gpio, lcd_reset);
+	lp->power = power;
+	lp->pwr_en = lcd_enable;
+	return ret;
+}
+
+static int lcd_pwrctrl_check_fb(struct lcd_device *lcd, struct fb_info *info)
+{
+	struct lcd_pwrctrl *lp = lcd_get_data(lcd);
+	return lp->dev->parent == info->device;
+}
+
+static struct lcd_ops lcd_pwrctrl_ops = {
+	.get_power	= lcd_pwrctrl_get_power,
+	.set_power	= lcd_pwrctrl_set_power,
+	.check_fb	= lcd_pwrctrl_check_fb,
+};
+
+#ifdef CONFIG_OF
+static void __devinit lcd_pwrctrl_parse_dt(struct device *dev,
+					struct lcd_pwrctrl_data *pdata)
+{
+	struct device_node *np = dev->of_node;
+
+	pdata->gpio = of_get_named_gpio(np, "lcd-reset-gpio", 0);
+	if (of_get_property(np, "lcd-reset-active-high", NULL))
+		pdata->invert = true;
+}
+#endif
+
+static int __devinit lcd_pwrctrl_probe(struct platform_device *pdev)
+{
+	struct lcd_pwrctrl *lp;
+	struct lcd_pwrctrl_data *pdata = pdev->dev.platform_data;
+	struct device *dev = &pdev->dev;
+	int err;
+
+#ifdef CONFIG_OF
+	if (dev->of_node) {
+		pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+		if (!pdata) {
+			dev_err(dev, "memory allocation for pdata failed\n");
+			return -ENOMEM;
+		}
+		lcd_pwrctrl_parse_dt(dev, pdata);
+	}
+#endif
+
+	if (!pdata) {
+		dev_err(dev, "platform data not available\n");
+		return -EINVAL;
+	}
+
+	lp = devm_kzalloc(dev, sizeof(struct lcd_pwrctrl), GFP_KERNEL);
+	if (!lp) {
+		dev_err(dev, "memory allocation failed for private data\n");
+		return -ENOMEM;
+	}
+
+	err = gpio_request(pdata->gpio, "LCD-nRESET");
+	if (err) {
+		dev_err(dev, "gpio [%d] request failed\n", pdata->gpio);
+		return err;
+	}
+
+	/*
+	 * If power to lcd and/or lcd interface is controlled using a regulator,
+	 * get the handle to the regulator for later use during power switching.
+	 */
+	lp->regulator = devm_regulator_get(dev, "vcc-lcd");
+	if (IS_ERR(lp->regulator))
+		dev_info(dev, "could not find regulator\n");
+
+	lp->dev = dev;
+	lp->pdata = pdata;
+	lp->lcd = lcd_device_register(dev_name(dev), dev, lp, &lcd_pwrctrl_ops);
+	if (IS_ERR(lp->lcd)) {
+		dev_err(dev, "cannot register lcd device\n");
+		gpio_free(pdata->gpio);
+		return PTR_ERR(lp->lcd);
+	}
+
+	platform_set_drvdata(pdev, lp);
+	lcd_pwrctrl_set_power(lp->lcd, FB_BLANK_NORMAL);
+	return 0;
+}
+
+static int __devexit lcd_pwrctrl_remove(struct platform_device *pdev)
+{
+	struct lcd_pwrctrl *lp = platform_get_drvdata(pdev);
+	lcd_device_unregister(lp->lcd);
+	gpio_free(lp->pdata->gpio);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int lcd_pwrctrl_suspend(struct device *dev)
+{
+	struct lcd_pwrctrl *lp = dev_get_drvdata(dev);
+
+	lp->suspended = true;
+	lcd_pwrctrl_set_power(lp->lcd, FB_BLANK_POWERDOWN);
+	return 0;
+}
+
+static int lcd_pwrctrl_resume(struct device *dev)
+{
+	struct lcd_pwrctrl *lp = dev_get_drvdata(dev);
+
+	lp->suspended = false;
+	lcd_pwrctrl_set_power(lp->lcd, FB_BLANK_UNBLANK);
+	return 0;
+}
+
+static const struct dev_pm_ops lcd_pwrctrl_dev_pm_ops = {
+	.suspend	= lcd_pwrctrl_suspend,
+	.resume		= lcd_pwrctrl_resume,
+};
+
+#define LCD_PWRCTRL_DEV_PM_OPS	(&lcd_pwrctrl_dev_pm_ops)
+#else
+#define LCD_PWRCTRL_DEV_PM_OPS	NULL
+#endif /* CONFIG_PM */
+
+#ifdef CONFIG_OF
+static const struct of_device_id lcd_pwrctrl_match[] = {
+	{ .compatible = "lcd-powercontrol", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, lcd_pwrctrl_match);
+#endif
+
+static struct platform_driver lcd_pwrctrl_driver = {
+	.driver		= {
+		.name	= "lcd-pwrctrl",
+		.owner	= THIS_MODULE,
+		.pm	= LCD_PWRCTRL_DEV_PM_OPS,
+		.of_match_table	= of_match_ptr(lcd_pwrctrl_match),
+	},
+	.probe		= lcd_pwrctrl_probe,
+	.remove		= lcd_pwrctrl_remove,
+};
+
+module_platform_driver(lcd_pwrctrl_driver);
+
+MODULE_AUTHOR("Thomas Abraham <thomas.ab at samsung.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:lcd-pwrctrl");
diff --git a/include/video/lcd_pwrctrl.h b/include/video/lcd_pwrctrl.h
new file mode 100644
index 0000000..924bfd2
--- /dev/null
+++ b/include/video/lcd_pwrctrl.h
@@ -0,0 +1,24 @@
+/*
+ * Simple lcd panel power control driver.
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ *
+ * This driver is derived from platform-lcd.h which was written by
+ * Ben Dooks <ben at simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+/**
+ * struct lcd_pwrctrl_data - platform data for lcd_pwrctrl driver.
+ * @gpio: GPIO number of the host system that connects to nRESET line.
+ * @invert: True, if output of gpio connected to nRESET should be inverted.
+ */
+struct lcd_pwrctrl_data {
+	int		gpio;
+	bool		invert;
+};
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Mon Mar 26 04:46:40 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 26 Mar 2012 14:16:40 +0530
Subject: [PATCH v3 2/2] ARM: Exynos: Use lcd power control driver for lcd panel
In-Reply-To: <1332751600-11371-1-git-send-email-thomas.abraham@linaro.org>
References: <1332751600-11371-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332751600-11371-3-git-send-email-thomas.abraham@linaro.org>

The Hydis hv070wsa lcd panel used with the Origen board uses a gpio
for reset and the Vcc supply to the panel can be controlled using
a voltage regulator. Switch to using the lcd power control driver
for controlling the power to the lcd panel.

Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 arch/arm/mach-exynos/mach-origen.c |   29 ++++++-----------------------
 1 files changed, 6 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index d3b2e9d..6c4997c 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -26,7 +26,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 
-#include <video/platform_lcd.h>
+#include <video/lcd_pwrctrl.h>
 
 #include <plat/regs-serial.h>
 #include <plat/regs-fb-v4.h>
@@ -129,7 +129,7 @@ static struct regulator_consumer_supply __initdata buck3_consumer[] = {
 	REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
 };
 static struct regulator_consumer_supply __initdata buck7_consumer[] = {
-	REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
+	REGULATOR_SUPPLY("vcc-lcd", "lcd-pwrctrl.0"), /* LCD */
 };
 
 static struct regulator_init_data __initdata max8997_ldo1_data = {
@@ -384,7 +384,7 @@ static struct regulator_init_data __initdata max8997_buck7_data = {
 		.name		= "VDD_LCD_3.3V",
 		.min_uV		= 3300000,
 		.max_uV		= 3300000,
-		.boot_on	= 1,
+		.boot_on	= 0,
 		.apply_uV	= 1,
 		.valid_ops_mask	= REGULATOR_CHANGE_STATUS,
 		.state_mem	= {
@@ -553,29 +553,12 @@ static struct platform_device origen_device_gpiokeys = {
 	},
 };
 
-static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
-{
-	int ret;
-
-	if (power)
-		ret = gpio_request_one(EXYNOS4_GPE3(4),
-					GPIOF_OUT_INIT_HIGH, "GPE3_4");
-	else
-		ret = gpio_request_one(EXYNOS4_GPE3(4),
-					GPIOF_OUT_INIT_LOW, "GPE3_4");
-
-	gpio_free(EXYNOS4_GPE3(4));
-
-	if (ret)
-		pr_err("failed to request gpio for LCD power: %d\n", ret);
-}
-
-static struct plat_lcd_data origen_lcd_hv070wsa_data = {
-	.set_power = lcd_hv070wsa_set_power,
+static struct lcd_pwrctrl_data origen_lcd_hv070wsa_data = {
+	.gpio	= EXYNOS4_GPE3(4),
 };
 
 static struct platform_device origen_lcd_hv070wsa = {
-	.name			= "platform-lcd",
+	.name			= "lcd-pwrctrl",
 	.dev.parent		= &s5p_device_fimd0.dev,
 	.dev.platform_data	= &origen_lcd_hv070wsa_data,
 };
-- 
1.6.6.rc2



From arnd at arndb.de  Mon Mar 26 04:47:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 26 Mar 2012 08:47:37 +0000
Subject: ioremap to a specific virtual address
In-Reply-To: <201203251734.41780.arnd@arndb.de>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <CAKON4OwhcFDMC4dWjU7x4u2CPT7C2BxVuCDkTN0j14gTndi3tA@mail.gmail.com>
 <201203251734.41780.arnd@arndb.de>
Message-ID: <201203260847.38176.arnd@arndb.de>

On Sunday 25 March 2012, Arnd Bergmann wrote:
>                         /* mpmc configuration */
>                         mpmc-static-config     = <0x81>;
>                         mpmc-static-wait-wen   = <1>;
>                         mpmc-static-wait-oen   = <1>;
>                         mpmc-static-wait-rd    = <4>;
>                         mpmc-static-wait-page  = <1>;
>                         mpmc-static-wait-write = <1>;
>                         mpmc-static-wait-turn  = <2>;

On second though, I guess you can turn these into a single
property named "mpmc-timings" or such and then just copy
them to the registers.

I also wonder whether the timings are actually correct for your
dm9000 device. Maybe the additional gpio read in there was
just an indication that someone worked around incorrect timings?

	Arnd


From linus.walleij at linaro.org  Mon Mar 26 05:05:16 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 26 Mar 2012 11:05:16 +0200
Subject: [PATCH] serial: pl011: implement workaround for CTS clear event
 issue
In-Reply-To: <20120326081756.GI5611@n2100.arm.linux.org.uk>
References: <1332748868-10172-1-git-send-email-linus.walleij@stericsson.com>
 <20120326081756.GI5611@n2100.arm.linux.org.uk>
Message-ID: <CACRpkdZAc0yk6URPzQ7x8UGaVHBMV-3MB2r0gu-7muc3hsh6aA@mail.gmail.com>

On Mon, Mar 26, 2012 at 10:17 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Mar 26, 2012 at 10:01:08AM +0200, Linus Walleij wrote:
>> - ? ? unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
>> + ? ? unsigned int status;
>
> Why are you removing the pass counter and associated code, which was
> there before your work-around patch was applied?

Good point, I'll cook a v2 which restores that counter an break clause to
what it was before the workaround was added.

Yours,
Linus Walleij


From rajanikanth.hv at stericsson.com  Mon Mar 26 05:07:39 2012
From: rajanikanth.hv at stericsson.com (Rajanikanth H V)
Date: Mon, 26 Mar 2012 11:07:39 +0200
Subject: [PATCH] serial: pl011: implement workaround for CTS clear	event
 issue
In-Reply-To: <20120326081756.GI5611@n2100.arm.linux.org.uk>
References: <1332748868-10172-1-git-send-email-linus.walleij@stericsson.com>
 <20120326081756.GI5611@n2100.arm.linux.org.uk>
Message-ID: <2B1D156D95AE9B4EAD379CB9E465FE73255E4BB903@EXDCVYMBSTM005.EQ1STM.local>

Russell,

As per my understanding, pass counter helps to identify/break the 
Deadlock situation and triggers bottom half handler in which
Uart controller will be forced to reset (save and restore of UART register happens).

It has been found from hardware analysis that race condition(explained in my commit message)
was causing the situation to persist (i.e. CTS ack was not happening in spite of W1C),
hence, assuming UART controller in deadlock state is wrong.


Thanks,
Rajanikanth

-----Original Message-----
From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] 
Sent: Monday, March 26, 2012 1:48 PM
To: Linus WALLEIJ
Cc: Greg Kroah-Hartman; linux-serial at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Christophe ARNAL; Guillaume JAUNET; Matthias LOCHER; Chanho Min; Linus Walleij; Rajanikanth H V
Subject: Re: [PATCH] serial: pl011: implement workaround for CTS clear event issue

On Mon, Mar 26, 2012 at 10:01:08AM +0200, Linus Walleij wrote:
> -	unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
> +	unsigned int status;

Why are you removing the pass counter and associated code, which was
there before your work-around patch was applied?


From linus.walleij at linaro.org  Mon Mar 26 05:14:56 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Mon, 26 Mar 2012 11:14:56 +0200
Subject: [PATCH] serial: pl011: implement workaround for CTS clear event
 issue
In-Reply-To: <2B1D156D95AE9B4EAD379CB9E465FE73255E4BB903@EXDCVYMBSTM005.EQ1STM.local>
References: <1332748868-10172-1-git-send-email-linus.walleij@stericsson.com>
 <20120326081756.GI5611@n2100.arm.linux.org.uk>
 <2B1D156D95AE9B4EAD379CB9E465FE73255E4BB903@EXDCVYMBSTM005.EQ1STM.local>
Message-ID: <CACRpkdaHoDawAXnXSK4KG4L_fusbWny2-b=UOS8LcQh4pdQS2g@mail.gmail.com>

On Mon, Mar 26, 2012 at 11:07 AM, Rajanikanth H V
<rajanikanth.hv at stericsson.com> wrote:

> As per my understanding, pass counter helps to identify/break the
> Deadlock situation and triggers bottom half handler in which
> Uart controller will be forced to reset (save and restore of UART register happens).

It was there before the fix for the deadlock situation found in ST hardwares,
which was solved by the tasklet, was ever introduced.

It has been around forever as a simple guard to stop the ISR from
going into a loop... which is nice coding practice anyway so let's
keep it.

Yours,
Linus Walleij


From linus.walleij at stericsson.com  Mon Mar 26 05:17:02 2012
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 26 Mar 2012 11:17:02 +0200
Subject: [PATCH v2] serial: pl011: implement workaround for CTS clear event
 issue
Message-ID: <1332753422-12178-1-git-send-email-linus.walleij@stericsson.com>

From: "Rajanikanth H.V" <rajanikanth.hv at stericsson.com>

Problem Observed:
- interrupt status is set by rising or falling edge on CTS line
- interrupt status is cleared on a .0. to .1. transition of the
  interrupt-clear register bit 1.
- interrupt-clear register is reset by hardware once the interrupt
  status is .0..
  Remark: It seems not possible to read this register back by the
  CPU though, but internally this register exists.
- when simultaneous set and reset event on the interrupt status
  happens, then the set-event has priority and the status remains
  .1.. As a result the interrupt-clear register is not reset to
  .0., and no new .0. to .1. transition can be detected on it when
  writing a .1. to it.
  This implies race condition, the clear must be performed at least
  one UARTCLK the riding edge of CTS RIS interrupt.

Fix:
  Instead of resetting UART as done in commit
  c16d51a32bbb61ac8fd96f78b5ce2fccfe0fb4c3
  "amba pl011: workaround for uart registers lockup" do the
  following:

  write .0. and then  .1. to the interrupt-clear register to make
  sure that this transition is detected. According to the datasheet
  writing a .0. does not have any effect, but actually it allows to
  reset the internal interrupt-clear register.

  Take into account:
  The .0. needs to last at least for one clk_uart clock period
  (~ 38 MHz, 26.08ns)

This way we can do away with the tasklet and keep only a tiny
fix triggered by the variant flag introduced in this patch.

Signed-off-by: Guillaume Jaunet <guillaume.jaunet at stericsson.com>
Signed-off-by: Christophe Arnal <christophe.arnal at stericsson.com>
Signed-off-by: Matthias Locher  <Matthias.Locher at stericsson.com>
Signed-off-by: Rajanikanth H.V <rajanikanth.hv at stericsson.com>
Reviewed-by: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
---
ChangeLog v1->v2:
- Restore the ISR loop lockup guard pass_counter to what it was
  before the lockup fix tasklet was introduced.
---
 drivers/tty/serial/amba-pl011.c |  109 +++++++--------------------------------
 1 file changed, 18 insertions(+), 91 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 4ed35c5..5001a88 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -66,30 +66,6 @@
 #define UART_DR_ERROR		(UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
 #define UART_DUMMY_DR_RX	(1 << 16)
 
-
-#define UART_WA_SAVE_NR 14
-
-static void pl011_lockup_wa(unsigned long data);
-static const u32 uart_wa_reg[UART_WA_SAVE_NR] = {
-	ST_UART011_DMAWM,
-	ST_UART011_TIMEOUT,
-	ST_UART011_LCRH_RX,
-	UART011_IBRD,
-	UART011_FBRD,
-	ST_UART011_LCRH_TX,
-	UART011_IFLS,
-	ST_UART011_XFCR,
-	ST_UART011_XON1,
-	ST_UART011_XON2,
-	ST_UART011_XOFF1,
-	ST_UART011_XOFF2,
-	UART011_CR,
-	UART011_IMSC
-};
-
-static u32 uart_wa_regdata[UART_WA_SAVE_NR];
-static DECLARE_TASKLET(pl011_lockup_tlet, pl011_lockup_wa, 0);
-
 /* There is by now at least one vendor with differing details, so handle it */
 struct vendor_data {
 	unsigned int		ifls;
@@ -99,6 +75,7 @@ struct vendor_data {
 	bool			oversampling;
 	bool			interrupt_may_hang;   /* vendor-specific */
 	bool			dma_threshold;
+	bool			cts_event_workaround;
 };
 
 static struct vendor_data vendor_arm = {
@@ -108,6 +85,7 @@ static struct vendor_data vendor_arm = {
 	.lcrh_rx		= UART011_LCRH,
 	.oversampling		= false,
 	.dma_threshold		= false,
+	.cts_event_workaround	= false,
 };
 
 static struct vendor_data vendor_st = {
@@ -118,6 +96,7 @@ static struct vendor_data vendor_st = {
 	.oversampling		= true,
 	.interrupt_may_hang	= true,
 	.dma_threshold		= true,
+	.cts_event_workaround	= true,
 };
 
 static struct uart_amba_port *amba_ports[UART_NR];
@@ -1038,69 +1017,6 @@ static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
 #define pl011_dma_flush_buffer	NULL
 #endif
 
-
-/*
- * pl011_lockup_wa
- * This workaround aims to break the deadlock situation
- * when after long transfer over uart in hardware flow
- * control, uart interrupt registers cannot be cleared.
- * Hence uart transfer gets blocked.
- *
- * It is seen that during such deadlock condition ICR
- * don't get cleared even on multiple write. This leads
- * pass_counter to decrease and finally reach zero. This
- * can be taken as trigger point to run this UART_BT_WA.
- *
- */
-static void pl011_lockup_wa(unsigned long data)
-{
-	struct uart_amba_port *uap = amba_ports[0];
-	void __iomem *base = uap->port.membase;
-	struct circ_buf *xmit = &uap->port.state->xmit;
-	struct tty_struct *tty = uap->port.state->port.tty;
-	int buf_empty_retries = 200;
-	int loop;
-
-	/* Stop HCI layer from submitting data for tx */
-	tty->hw_stopped = 1;
-	while (!uart_circ_empty(xmit)) {
-		if (buf_empty_retries-- == 0)
-			break;
-		udelay(100);
-	}
-
-	/* Backup registers */
-	for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
-		uart_wa_regdata[loop] = readl(base + uart_wa_reg[loop]);
-
-	/* Disable UART so that FIFO data is flushed out */
-	writew(0x00, uap->port.membase + UART011_CR);
-
-	/* Soft reset UART module */
-	if (uap->port.dev->platform_data) {
-		struct amba_pl011_data *plat;
-
-		plat = uap->port.dev->platform_data;
-		if (plat->reset)
-			plat->reset();
-	}
-
-	/* Restore registers */
-	for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
-		writew(uart_wa_regdata[loop] ,
-				uap->port.membase + uart_wa_reg[loop]);
-
-	/* Initialise the old status of the modem signals */
-	uap->old_status = readw(uap->port.membase + UART01x_FR) &
-		UART01x_FR_MODEM_ANY;
-
-	if (readl(base + UART011_MIS) & 0x2)
-		printk(KERN_EMERG "UART_BT_WA: ***FAILED***\n");
-
-	/* Start Tx/Rx */
-	tty->hw_stopped = 0;
-}
-
 static void pl011_stop_tx(struct uart_port *port)
 {
 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
@@ -1229,12 +1145,26 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
 	unsigned long flags;
 	unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
 	int handled = 0;
+	unsigned int dummy_read;
 
 	spin_lock_irqsave(&uap->port.lock, flags);
 
 	status = readw(uap->port.membase + UART011_MIS);
 	if (status) {
 		do {
+			if (uap->vendor->cts_event_workaround) {
+				/* workaround to make sure that all bits are unlocked.. */
+				writew(0x00, uap->port.membase + UART011_ICR);
+
+				/*
+				 * WA: introduce 26ns(1 uart clk) delay before W1C;
+				 * single apb access will incur 2 pclk(133.12Mhz) delay,
+				 * so add 2 dummy reads
+				 */
+				dummy_read = readw(uap->port.membase + UART011_ICR);
+				dummy_read = readw(uap->port.membase + UART011_ICR);
+			}
+
 			writew(status & ~(UART011_TXIS|UART011_RTIS|
 					  UART011_RXIS),
 			       uap->port.membase + UART011_ICR);
@@ -1251,11 +1181,8 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
 			if (status & UART011_TXIS)
 				pl011_tx_chars(uap);
 
-			if (pass_counter-- == 0) {
-				if (uap->interrupt_may_hang)
-					tasklet_schedule(&pl011_lockup_tlet);
+			if (pass_counter-- == 0)
 				break;
-			}
 
 			status = readw(uap->port.membase + UART011_MIS);
 		} while (status != 0);
-- 
1.7.9.2



From will.deacon at arm.com  Mon Mar 26 05:40:54 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 26 Mar 2012 10:40:54 +0100
Subject: [PATCH] ARM: test for PMU feature on v7 (v2 with typo fix)
In-Reply-To: <87fwcy9abw.fsf@rustcorp.com.au>
References: <4F590411.9060201@arm.com> <87ty1g88dv.fsf@rustcorp.com.au>
 <87r4wk889a.fsf@rustcorp.com.au>
 <20120323095314.GA13622@mudshark.cambridge.arm.com>
 <87fwcy9abw.fsf@rustcorp.com.au>
Message-ID: <20120326094054.GA2475@mudshark.cambridge.arm.com>

[removed some dead email addresses from CC]

On Fri, Mar 23, 2012 at 11:17:07PM +0000, Rusty Russell wrote:
> On Fri, 23 Mar 2012 09:53:14 +0000, Will Deacon <will.deacon at arm.com> wrote:
> > On Fri, Mar 23, 2012 at 12:34:57AM +0000, Rusty Russell wrote:
> ...
> > >  static struct arm_pmu *__init armv7_a8_pmu_init(void)
> > >  {
> > > +	if (!armv7_pmu_avail())
> > > +		return NULL;
> > 
> > This code is only executed if we know for sure that we are running on a
> > Cortex-A8. Cortex-A8 implementations have a PMU, so I don't like having the
> > probe here in case we are running on a virtualised CPU that doesn't quite
> > match the hardware.
> 
> OK, I see that argument, but I don't like it.  eg. the Cortex A-15 is
> defined to have a PMUv2 with 6 counters, and below you're arguing we
> should implement zero of them.

Well, I think you should actually implement all 6 of them if that's the
target which you're emulating. However, there are bigger peripherals to fry
than the PMU so if you want to get something working quickly then a dummy
PMU makes sense as a stopgap.

> I had assumed that as we trend towards a common cross-platform kernel,
> we should be relying on feature registers where available, not the
> model.

The PMU is very tightly coupled with the CPU and it is necessary to know
exactly which CPU you have so that you can map microarchitectural events to
their identifiers. This is not discoverable in the architecture [PMUv2
provides some support for discovering the status of architected events, but
that is still not enough and is only present on A7 and A15 so far] so that's
why we probe the CPU instead.

Now, if everything was device-tree based then we could simply use a
different binding for each CPU but since we support perf on non-DT
platforms, probing the CPU type is the best solution. I would like to avoid
the probing code if we are initialised from DT, but I've not got round to it
yet (this would be useful for big.LITTLE).

> > Would you be able to advertise 0 event counters instead and treat the PMU
> > largely as RAZ/WI? The only tricky bit I can see is the cycle counter, which
> > is mandated by the presence of a PMU, however this could also just RAZ
> > initially.
> 
> Yes, that's the effect of the current emulation hack.  Far better not to
> lie to the guest, however, than get weird results from profiling.

I'd rather lie to the guest than modify it just to avoid emulating the
device correctly. Even then, the profiling results wouldn't be especially
weird -- everything would be 0, which is a lot better than random numbers.

Will


From peter.maydell at linaro.org  Mon Mar 26 05:50:35 2012
From: peter.maydell at linaro.org (Peter Maydell)
Date: Mon, 26 Mar 2012 10:50:35 +0100
Subject: [Android-virt] [PATCH] ARM: test for PMU feature on v7 (v2 with
 typo fix)
In-Reply-To: <20120326094054.GA2475@mudshark.cambridge.arm.com>
References: <4F590411.9060201@arm.com> <87ty1g88dv.fsf@rustcorp.com.au>
 <87r4wk889a.fsf@rustcorp.com.au>
 <20120323095314.GA13622@mudshark.cambridge.arm.com>
 <87fwcy9abw.fsf@rustcorp.com.au>
 <20120326094054.GA2475@mudshark.cambridge.arm.com>
Message-ID: <CAFEAcA-S3pN0AihjMZdchRyvFpifvKN8rNytpEP_iaA3H5RWfQ@mail.gmail.com>

On 26 March 2012 10:40, Will Deacon <will.deacon at arm.com> wrote:
> [removed some dead email addresses from CC]
>
> On Fri, Mar 23, 2012 at 11:17:07PM +0000, Rusty Russell wrote:
>> On Fri, 23 Mar 2012 09:53:14 +0000, Will Deacon <will.deacon at arm.com> wrote:
>> > This code is only executed if we know for sure that we are running on a
>> > Cortex-A8. Cortex-A8 implementations have a PMU, so I don't like having the
>> > probe here in case we are running on a virtualised CPU that doesn't quite
>> > match the hardware.
>>
>> OK, I see that argument, but I don't like it. ?eg. the Cortex A-15 is
>> defined to have a PMUv2 with 6 counters, and below you're arguing we
>> should implement zero of them.
>
> Well, I think you should actually implement all 6 of them if that's the
> target which you're emulating.

The trouble with this line of thought is that it leads to the requirement
to support nested virtualization and virtualization of TrustZone, neither
of which are actually particularly useful or simple to do. At some point
we're going to end up saying that the "A15" we expose to the guest is
not an exact match to the real hardware, that it's missing certain
features (and hopefully that the lack of those features is advertised
via the feature registers). So the question is where you draw the line...

-- PMM


From catalin.marinas at arm.com  Mon Mar 26 06:38:54 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 26 Mar 2012 11:38:54 +0100
Subject: [PATCH] ARM: fixup section mismatch warning for alloc_init_pud()
In-Reply-To: <87398zswkj.wl%kuninori.morimoto.gx@renesas.com>
References: <87398zswkj.wl%kuninori.morimoto.gx@renesas.com>
Message-ID: <20120326103854.GG30455@arm.com>

On Fri, Mar 23, 2012 at 05:41:52AM +0000, Kuninori Morimoto wrote:
> This patch fixup below warning
> 
> WARNING: arch/arm/mm/built-in.o(.text+0x2320):
> Section mismatch in reference from the function alloc_init_pud()
> to the function .init.text:alloc_init_section()
> The function alloc_init_pud() references
> the function __init alloc_init_section().
> This is often because alloc_init_pud lacks a __init
> annotation or the annotation of alloc_init_section is wrong.
> 
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>

-- 
Catalin


From subashrp at gmail.com  Mon Mar 26 07:04:28 2012
From: subashrp at gmail.com (Subash Patel)
Date: Mon, 26 Mar 2012 16:34:28 +0530
Subject: [PATCH 0/2] ARM: dma-mapping: Fix mmap support for coherent
 buffers
In-Reply-To: <1332505563-17646-1-git-send-email-m.szyprowski@samsung.com>
References: <08af01cd08ee$2fd04770$8f70d650$%szyprowski@samsung.com>
 <1332505563-17646-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <4F704D3C.50003@gmail.com>

Hi Marek,

I have tested these patch series for origen board, and they mmap the 
buffers to user-space for the coherent pool. You can add:

Tested-By: Subash Patel <subashrp at gmail.com>

Regards,
Subash

On 03/23/2012 05:56 PM, Marek Szyprowski wrote:
> Hello,
>
> This patchset contains patches to fix broken mmap operation for memory
> buffers allocated from 'dma_declare_coherent' pool after applying my dma
> mapping redesign patches [1]. These issues have been reported by Subash
> Patel.
>
> [1] http://thread.gmane.org/gmane.linux.kernel.cross-arch/12819
>
> Patch summary:
>
> Marek Szyprowski (2):
>    common: add dma_mmap_from_coherent() function
>    arm: dma-mapping: use dma_mmap_from_coherent()
>
>   arch/arm/mm/dma-mapping.c          |    3 ++
>   drivers/base/dma-coherent.c        |   42 ++++++++++++++++++++++++++++++++++++
>   include/asm-generic/dma-coherent.h |    4 ++-
>   3 files changed, 48 insertions(+), 1 deletions(-)
>


From javier.martin at vista-silicon.com  Mon Mar 26 07:20:01 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon, 26 Mar 2012 13:20:01 +0200
Subject: [PATCH 0/3] media: tvp5150: Fix mbus format to UYUV instead of YUYV.
Message-ID: <1332760804-22743-1-git-send-email-javier.martin@vista-silicon.com>

[PATCH 1/3] media: tvp5150: Fix mbus format.
[PATCH 2/3] media: mx2_camera: Fix mbus format handling.
[PATCH 3/3] i.MX27: visstrim_m10: Remove use of MX2_CAMERA_SWAP16.


From javier.martin at vista-silicon.com  Mon Mar 26 07:20:02 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon, 26 Mar 2012 13:20:02 +0200
Subject: [PATCH 1/3] media: tvp5150: Fix mbus format.
In-Reply-To: <1332760804-22743-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332760804-22743-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332760804-22743-2-git-send-email-javier.martin@vista-silicon.com>

According to p.14 fig 3-3 of the datasheet (SLES098A)
this decoder transmits data in UYVY format.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/media/video/tvp5150.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/media/video/tvp5150.c b/drivers/media/video/tvp5150.c
index e292c46..30c88e0 100644
--- a/drivers/media/video/tvp5150.c
+++ b/drivers/media/video/tvp5150.c
@@ -821,7 +821,7 @@ static int tvp5150_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
 	if (index)
 		return -EINVAL;
 
-	*code = V4L2_MBUS_FMT_YUYV8_2X8;
+	*code = V4L2_MBUS_FMT_UYVY8_2X8;
 	return 0;
 }
 
@@ -845,7 +845,7 @@ static int tvp5150_mbus_fmt(struct v4l2_subdev *sd,
 	f->width = decoder->rect.width;
 	f->height = decoder->rect.height;
 
-	f->code = V4L2_MBUS_FMT_YUYV8_2X8;
+	f->code = V4L2_MBUS_FMT_UYVY8_2X8;
 	f->field = V4L2_FIELD_SEQ_TB;
 	f->colorspace = V4L2_COLORSPACE_SMPTE170M;
 
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar 26 07:20:03 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon, 26 Mar 2012 13:20:03 +0200
Subject: [PATCH 2/3] media: mx2_camera: Fix mbus format handling.
In-Reply-To: <1332760804-22743-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332760804-22743-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332760804-22743-3-git-send-email-javier.martin@vista-silicon.com>

Remove MX2_CAMERA_SWAP16 and MX2_CAMERA_PACK_DIR_MSB flags
so that the driver can negotiate with the attached sensor
whether the mbus format needs convertion from UYUV to YUYV
or not.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/plat-mxc/include/mach/mx2_cam.h |    2 -
 drivers/media/video/mx2_camera.c         |   52 +++++++++++++++++++++++++++---
 2 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h
index 3c080a3..7ded6f1 100644
--- a/arch/arm/plat-mxc/include/mach/mx2_cam.h
+++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h
@@ -23,7 +23,6 @@
 #ifndef __MACH_MX2_CAM_H_
 #define __MACH_MX2_CAM_H_
 
-#define MX2_CAMERA_SWAP16		(1 << 0)
 #define MX2_CAMERA_EXT_VSYNC		(1 << 1)
 #define MX2_CAMERA_CCIR			(1 << 2)
 #define MX2_CAMERA_CCIR_INTERLACE	(1 << 3)
@@ -31,7 +30,6 @@
 #define MX2_CAMERA_GATED_CLOCK		(1 << 5)
 #define MX2_CAMERA_INV_DATA		(1 << 6)
 #define MX2_CAMERA_PCLK_SAMPLE_RISING	(1 << 7)
-#define MX2_CAMERA_PACK_DIR_MSB		(1 << 8)
 
 /**
  * struct mx2_camera_platform_data - optional platform data for mx2_camera
diff --git a/drivers/media/video/mx2_camera.c b/drivers/media/video/mx2_camera.c
index 8df624f..9274a53 100644
--- a/drivers/media/video/mx2_camera.c
+++ b/drivers/media/video/mx2_camera.c
@@ -348,6 +348,19 @@ static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
 					PRP_INTR_CH2OVF,
 		}
 	},
+	{
+		.in_fmt		= V4L2_MBUS_FMT_UYVY8_2X8,
+		.out_fmt	= V4L2_PIX_FMT_YUV420,
+		.cfg		= {
+			.channel	= 2,
+			.in_fmt		= PRP_CNTL_DATA_IN_YUV422,
+			.out_fmt	= PRP_CNTL_CH2_OUT_YUV420,
+			.src_pixel	= 0x22000888, /* YUV422 (YUYV) */
+			.irq_flags	= PRP_INTR_RDERR | PRP_INTR_CH2WERR |
+					PRP_INTR_CH2FC | PRP_INTR_LBOVF |
+					PRP_INTR_CH2OVF,
+		}
+	},
 };
 
 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
@@ -990,6 +1003,7 @@ static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
 	struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
 	struct mx2_camera_dev *pcdev = ici->priv;
 	struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
+	const struct soc_camera_format_xlate *xlate;
 	unsigned long common_flags;
 	int ret;
 	int bytesperline;
@@ -1034,14 +1048,31 @@ static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
 		return ret;
 	}
 
+	xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
+	if (!xlate) {
+		dev_warn(icd->parent, "Format %x not found\n", pixfmt);
+		return -EINVAL;
+	}
+
+	if (xlate->code == V4L2_MBUS_FMT_YUYV8_2X8) {
+		csicr1 |= CSICR1_PACK_DIR;
+		csicr1 &= ~CSICR1_SWAP16_EN;
+		dev_dbg(icd->parent, "already yuyv format, don't convert\n");
+	} else if (xlate->code == V4L2_MBUS_FMT_UYVY8_2X8) {
+		csicr1 &= ~CSICR1_PACK_DIR;
+		csicr1 |= CSICR1_SWAP16_EN;
+		dev_dbg(icd->parent, "convert uyvy mbus format into yuyv\n");
+	} else {
+		dev_warn(icd->parent, "mbus format not supported\n");
+		return -EINVAL;
+	}
+
 	if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
 		csicr1 |= CSICR1_REDGE;
 	if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
 		csicr1 |= CSICR1_SOF_POL;
 	if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
 		csicr1 |= CSICR1_HSYNC_POL;
-	if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
-		csicr1 |= CSICR1_SWAP16_EN;
 	if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
 		csicr1 |= CSICR1_EXT_VSYNC;
 	if (pcdev->platform_flags & MX2_CAMERA_CCIR)
@@ -1052,8 +1083,6 @@ static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
 		csicr1 |= CSICR1_GCLK_MODE;
 	if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
 		csicr1 |= CSICR1_INV_DATA;
-	if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
-		csicr1 |= CSICR1_PACK_DIR;
 
 	pcdev->csicr1 = csicr1;
 
@@ -1128,7 +1157,8 @@ static int mx2_camera_get_formats(struct soc_camera_device *icd,
 		return 0;
 	}
 
-	if (code == V4L2_MBUS_FMT_YUYV8_2X8) {
+	if (code == V4L2_MBUS_FMT_YUYV8_2X8 ||
+	    code == V4L2_MBUS_FMT_UYVY8_2X8) {
 		formats++;
 		if (xlate) {
 			/*
@@ -1144,6 +1174,18 @@ static int mx2_camera_get_formats(struct soc_camera_device *icd,
 		}
 	}
 
+	if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
+		formats++;
+		if (xlate) {
+			xlate->host_fmt =
+				soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8);
+			xlate->code	= code;
+			dev_dbg(dev, "Providing host format %s for sensor code %d\n",
+				xlate->host_fmt->name, code);
+			xlate++;
+		}
+	}
+
 	/* Generic pass-trough */
 	formats++;
 	if (xlate) {
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar 26 07:20:04 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon, 26 Mar 2012 13:20:04 +0200
Subject: [PATCH 3/3] i.MX27: visstrim_m10: Remove use of MX2_CAMERA_SWAP16.
In-Reply-To: <1332760804-22743-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332760804-22743-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332760804-22743-4-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 3128cfe..4db00c6 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -164,7 +164,7 @@ static struct platform_device visstrim_tvp5150 = {
 
 
 static struct mx2_camera_platform_data visstrim_camera = {
-	.flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | MX2_CAMERA_SWAP16 | MX2_CAMERA_PCLK_SAMPLE_RISING,
+	.flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | MX2_CAMERA_PCLK_SAMPLE_RISING,
 	.clk = 100000,
 };
 
-- 
1.7.0.4



From jonsmirl at gmail.com  Mon Mar 26 07:21:02 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Mon, 26 Mar 2012 07:21:02 -0400
Subject: ioremap to a specific virtual address
In-Reply-To: <201203231931.06376.arnd@arndb.de>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <201203231520.22588.arnd@arndb.de>
 <CAKON4OybXXwLEmg19NJnLsE5kB16U6Dm4ay3=XCUB57fRfz+ng@mail.gmail.com>
 <201203231931.06376.arnd@arndb.de>
Message-ID: <CAKON4Oy=C8EsCGyWu7ZiZPKQp29NLcohCKzz2LGUL-WWK=FxyQ@mail.gmail.com>

On Fri, Mar 23, 2012 at 3:31 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 23 March 2012, jonsmirl at gmail.com wrote:
>> On Fri, Mar 23, 2012 at 11:20 AM, Arnd Bergmann <arnd at arndb.de> wrote:
>> > On Friday 23 March 2012, jonsmirl at gmail.com wrote:
>> >> I will need to check how similar the chips actually are. NXP did not
>> >> use primecells in the lpc31xx family.
>> >>
>> >> I'd be happy to have some help. My trees are here:
>> >> https://github.com/jonsmirl
>> >
>> > I've taken a brief look at your tree, some comments:
>> >
>> > * Once you're done with the DT conversion, you should be able to
>> > ?completely remvoe the three board files. You probably know that already
>>
>> Thanks for the feedback.
>>
>> I don't think I can completely remove the board files. Some of the
>> generic devices have board specific callbacks. DM9000 for example. I
>> am setting up of_dev_auxdata for the boards so that I can pass these
>> callbacks in.
>
> There are some cases where it's not possible to avoid platform_data,
> but in most cases there is another better solution.
>
> If you end up having to use platform_data, the auxdata mechanism
> is the way to go.

Here's the answer from the owners of the hardware...


---------- Forwarded message ----------
From: Support at EmbeddedArtists.com <support at embeddedartists.com>
Date: Mon, Mar 26, 2012 at 2:31 AM
Subject: Re: [Ticket#10005612] DM9000 on EA3131 board
To: "jonsmirl at gmail.com" <jonsmirl at gmail.com>


Hi Jon,
This driver was created a long time ago and it was not done by us.
If I remember correctly the delay is needed because the LPC31xx memory
controller does some strange things when you change memory regions. It
can for example happen if an interrupt happen in the middle of some
other operation in external memory. We have actually forgot about the
exact details but you can probably find it in the LPC31xx user's
manual from NXP or by asking NXP directly.

Kind Regards,
Anders Rosvall
Embedded Artists AB





>
>> # define DM_IO_DELAY() ? ? ? ?do { gpio_get_value(GPIO_MNAND_RYBN3);} while(0)
>>
>> static void dm9000_dumpblk(void __iomem *reg, int count)
>> {
>> ? ? ? int i;
>> ? ? ? int tmp;
>>
>> ? ? ? count = (count + 1) >> 1;
>> ? ? ? for (i = 0; i < count; i++) {
>> ? ? ? ? ? ? ? DM_IO_DELAY();
>> ? ? ? ? ? ? ? tmp = readw(reg);
>> ? ? ? }
>> }
>>
>> static void dm9000_inblk(void __iomem *reg, void *data, int count)
>> {
>> ? ? ? int i;
>> ? ? ? u16* pdata = (u16*)data;
>> ? ? ? count = (count + 1) >> 1;
>> ? ? ? for (i = 0; i < count; i++) {
>> ? ? ? ? ? ? ? DM_IO_DELAY();
>> ? ? ? ? ? ? ? *pdata++ = readw(reg);
>> ? ? ? }
>> }
>>
>> static struct dm9000_plat_data dm9000_platdata = {
>> ? ? ? .flags ? ? ? ? ?= DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM |
>> DM9000_PLATF_SIMPLE_PHY,
>
> The flags can become simple empty properties if necessary, so there is no
> need to keep these.
>
>> ? ? ? .dumpblk = dm9000_dumpblk,
>> ? ? ? .inblk = dm9000_inblk,
>> };
>
> I can see two possible ways besides platform_data for the register access:
>
> 1. generalize the driver's accessors. Since your platform wants to read
> a gpio pin before every access, you can provide a gpio line as the
> property in the dm9000 device node and access that in the same place
> in the common code if the gpio line is set, but skip the access otherwise.
> No other platform in mainline actually needs to overrid the functions,
> so there are hardly any disadvantages to this.
>
> 2. convert the entire driver to use the "regmap" infrastructure to abstract
> the registers, and implement a driver that implements the slow I/O. This
> would be a rather complex solution and probably not worth it, compared
> with the overhead of the first one or just staying with auxdata.
>
> If any problem turns out to be really hard to convert over from
> platform_data to device tree properties, auxdata is usually an acceptable
> solution, or you could submit the port with more of those hacks when
> there is reason to believe that you will fix them up later.
>
> ? ? ? ?Arnd



-- 
Jon Smirl
jonsmirl at gmail.com


From subashrp at gmail.com  Mon Mar 26 07:38:35 2012
From: subashrp at gmail.com (Subash Patel)
Date: Mon, 26 Mar 2012 17:08:35 +0530
Subject: [PATCHv7 5/9] ARM: dma-mapping: implement dma sg methods on top
 of any generic dma ops
In-Reply-To: <1330527862-16234-6-git-send-email-m.szyprowski@samsung.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-6-git-send-email-m.szyprowski@samsung.com>
Message-ID: <4F70553B.2000100@gmail.com>

Hi Marek,

As per our discussion over IRC, I would like to check with you the 
feasibility to extend the dma operation calls for the coherent regions. 
You said that since struct page wont be available for the buffers in 
these regions, functions like arm_dma_map_sg() (below) will fail in the 
cache maintenance operations. Infact, I am facing this issue when I 
integrated dma-buf buffer sharing + v4l2/vb2 exporter patch series + 
dma_mapping (v7) and use coherent memory.

So I want to know opinion of you, others about extending the dma-mapping 
framework for scenarios which use device coherent memory.

Regards,
Subash

On 02/29/2012 08:34 PM, Marek Szyprowski wrote:
> This patch converts all dma_sg methods to be generic (independent of the
> current DMA mapping implementation for ARM architecture). All dma sg
> operations are now implemented on top of respective
> dma_map_page/dma_sync_single_for* operations from dma_map_ops structure.
>
> Signed-off-by: Marek Szyprowski<m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park<kyungmin.park at samsung.com>
> ---
>   arch/arm/mm/dma-mapping.c |   43 +++++++++++++++++++------------------------
>   1 files changed, 19 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index cd5ed8d..a5a0b5b 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -616,7 +616,7 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
>   EXPORT_SYMBOL(___dma_page_dev_to_cpu);
>
>   /**
> - * dma_map_sg - map a set of SG buffers for streaming mode DMA
> + * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
>    * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
>    * @sg: list of buffers
>    * @nents: number of buffers to map
> @@ -634,12 +634,13 @@ EXPORT_SYMBOL(___dma_page_dev_to_cpu);
>   int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
>   		enum dma_data_direction dir, struct dma_attrs *attrs)
>   {
> +	struct dma_map_ops *ops = get_dma_ops(dev);
>   	struct scatterlist *s;
>   	int i, j;
>
>   	for_each_sg(sg, s, nents, i) {
> -		s->dma_address = __dma_map_page(dev, sg_page(s), s->offset,
> -						s->length, dir);
> +		s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
> +						s->length, dir, attrs);
>   		if (dma_mapping_error(dev, s->dma_address))
>   			goto bad_mapping;
>   	}
> @@ -647,12 +648,12 @@ int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
>
>    bad_mapping:
>   	for_each_sg(sg, s, i, j)
> -		__dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
> +		ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
>   	return 0;
>   }
>
>   /**
> - * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
> + * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
>    * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
>    * @sg: list of buffers
>    * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
> @@ -664,15 +665,17 @@ int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
>   void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
>   		enum dma_data_direction dir, struct dma_attrs *attrs)
>   {
> +	struct dma_map_ops *ops = get_dma_ops(dev);
>   	struct scatterlist *s;
> +
>   	int i;
>
>   	for_each_sg(sg, s, nents, i)
> -		__dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
> +		ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
>   }
>
>   /**
> - * dma_sync_sg_for_cpu
> + * arm_dma_sync_sg_for_cpu
>    * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
>    * @sg: list of buffers
>    * @nents: number of buffers to map (returned from dma_map_sg)
> @@ -681,21 +684,17 @@ void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
>   void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
>   			int nents, enum dma_data_direction dir)
>   {
> +	struct dma_map_ops *ops = get_dma_ops(dev);
>   	struct scatterlist *s;
>   	int i;
>
> -	for_each_sg(sg, s, nents, i) {
> -		if (!dmabounce_sync_for_cpu(dev, sg_dma_address(s),
> -					    sg_dma_len(s), dir))
> -			continue;
> -
> -		__dma_page_dev_to_cpu(sg_page(s), s->offset,
> -				      s->length, dir);
> -	}
> +	for_each_sg(sg, s, nents, i)
> +		ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
> +					 dir);
>   }
>
>   /**
> - * dma_sync_sg_for_device
> + * arm_dma_sync_sg_for_device
>    * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
>    * @sg: list of buffers
>    * @nents: number of buffers to map (returned from dma_map_sg)
> @@ -704,17 +703,13 @@ void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
>   void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
>   			int nents, enum dma_data_direction dir)
>   {
> +	struct dma_map_ops *ops = get_dma_ops(dev);
>   	struct scatterlist *s;
>   	int i;
>
> -	for_each_sg(sg, s, nents, i) {
> -		if (!dmabounce_sync_for_device(dev, sg_dma_address(s),
> -					sg_dma_len(s), dir))
> -			continue;
> -
> -		__dma_page_cpu_to_dev(sg_page(s), s->offset,
> -				      s->length, dir);
> -	}
> +	for_each_sg(sg, s, nents, i)
> +		ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
> +					    dir);
>   }
>
>   /*


From viresh.kumar at st.com  Mon Mar 26 07:43:57 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 26 Mar 2012 17:13:57 +0530
Subject: [PATCH 1/5] SPEAr6xx: Add compilation support for dtbs using 'make
 dtbs'
In-Reply-To: <cover.1332762103.git.viresh.kumar@st.com>
References: <cover.1332762103.git.viresh.kumar@st.com>
Message-ID: <7f41195f813f788d9c72f139fcef2f024bf20a6a.1332762103.git.viresh.kumar@st.com>

'make dtbs' compiles all dtbs for a family. For this we need to add entries for
all board dtb's in Makefile.boot file. This patch does it.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/mach-spear6xx/Makefile.boot |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c..af493da 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_BOARD_SPEAR600_DT)	+= spear600-evb.dtb
-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Mon Mar 26 07:43:58 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 26 Mar 2012 17:13:58 +0530
Subject: [PATCH 2/5] SPEAr3xx: Replace printk() with pr_*()
In-Reply-To: <cover.1332762103.git.viresh.kumar@st.com>
References: <cover.1332762103.git.viresh.kumar@st.com>
Message-ID: <e6e6b8c9f3298ac9524a480f1085d7e0ce06b7af.1332762103.git.viresh.kumar@st.com>

For better print logs/messages, it is advisable to use pr_*() routines instead
of directly calling printks. This patch removes direct calling of printks for
spear3xx.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/mach-spear3xx/spear300.c |    8 +++++---
 arch/arm/mach-spear3xx/spear310.c |   13 +++++++------
 arch/arm/mach-spear3xx/spear320.c |   11 ++++++-----
 arch/arm/mach-spear3xx/spear3xx.c |    2 ++
 4 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db668..adee72b 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr300: " fmt
+
 #include <linux/types.h>
 #include <linux/amba/pl061.h>
 #include <linux/ptrace.h>
@@ -447,7 +449,7 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 	if (shirq_ras1.regs.base) {
 		ret = spear_shirq_register(&shirq_ras1);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ\n");
+			pr_err("Error registering Shared IRQ\n");
 	}
 
 	/* pmx initialization */
@@ -459,8 +461,8 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 	if (pmx_driver.base) {
 		ret = pmx_register(&pmx_driver);
 		if (ret)
-			printk(KERN_ERR "padmux: registration failed. err no"
-					": %d\n", ret);
+			pr_err("padmux: registration failed. err no: %d\n",
+					ret);
 		/* Free Mapping, device selection already done */
 		iounmap(pmx_driver.base);
 	}
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6f..b7c2876 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr310: " fmt
+
 #include <linux/ptrace.h>
 #include <asm/irq.h>
 #include <plat/shirq.h>
@@ -274,25 +276,25 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 		shirq_ras1.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras1);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 1\n");
+			pr_err("Error registering Shared IRQ 1\n");
 
 		/* shirq 2 */
 		shirq_ras2.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras2);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 2\n");
+			pr_err("Error registering Shared IRQ 2\n");
 
 		/* shirq 3 */
 		shirq_ras3.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras3);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 3\n");
+			pr_err("Error registering Shared IRQ 3\n");
 
 		/* shirq 4 */
 		shirq_intrcomm_ras.regs.base = base;
 		ret = spear_shirq_register(&shirq_intrcomm_ras);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 4\n");
+			pr_err("Error registering Shared IRQ 4\n");
 	}
 
 	/* pmx initialization */
@@ -303,6 +305,5 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 
 	ret = pmx_register(&pmx_driver);
 	if (ret)
-		printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-				ret);
+		pr_err("padmux: registration failed. err no: %d\n", ret);
 }
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf19..7bd39c0 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr320: " fmt
+
 #include <linux/ptrace.h>
 #include <asm/irq.h>
 #include <plat/shirq.h>
@@ -527,19 +529,19 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 		shirq_ras1.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras1);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 1\n");
+			pr_err("Error registering Shared IRQ 1\n");
 
 		/* shirq 3 */
 		shirq_ras3.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras3);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 3\n");
+			pr_err("Error registering Shared IRQ 3\n");
 
 		/* shirq 4 */
 		shirq_intrcomm_ras.regs.base = base;
 		ret = spear_shirq_register(&shirq_intrcomm_ras);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 4\n");
+			pr_err("Error registering Shared IRQ 4\n");
 	}
 
 	/* pmx initialization */
@@ -550,6 +552,5 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 
 	ret = pmx_register(&pmx_driver);
 	if (ret)
-		printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-				ret);
+		pr_err("padmux: registration failed. err no: %d\n", ret);
 }
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c3..a236925 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr3xx: " fmt
+
 #include <linux/types.h>
 #include <linux/amba/pl061.h>
 #include <linux/ptrace.h>
-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Mon Mar 26 07:43:56 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 26 Mar 2012 17:13:56 +0530
Subject: [PATCH 0/5] SPEAr DT support updates
Message-ID: <cover.1332762103.git.viresh.kumar@st.com>

Hello,

This patchset updates DT support for SPEAr3xx and 6xx.
It has following changes:
- updates DT support Mainly for SPEAr3xx family
- updates dma support for SPEAr6xx
- updates defconfig

It has dependency on following patchsets:
- ehci & ohci: http://www.spinics.net/lists/linux-usb/msg60362.html
- rtc: http://lkml.org/lkml/2012/3/26/96
- keyboard: Link not yet available:
  subject: Input: spear-keyboard: add device tree bindings
- SPEAr patches: http://comments.gmane.org/gmane.linux.ports.arm.kernel/158865

Viresh Kumar (5):
  SPEAr6xx: Add compilation support for dtbs using 'make dtbs'
  SPEAr3xx: Replace printk() with pr_*()
  ARM: SPEAr3xx: Add device-tree support to SPEAr3xx architecture
  SPEAr: Add PL080 DMA support for 3xx and 6xx
  SPEAr: Update defconfigs

 Documentation/arm/SPEAr/overview.txt            |   13 +-
 Documentation/devicetree/bindings/arm/spear.txt |   18 ++
 arch/arm/Makefile                               |    6 +-
 arch/arm/boot/dts/spear300-evb.dts              |  181 +++++++++++
 arch/arm/boot/dts/spear300.dtsi                 |   74 +++++
 arch/arm/boot/dts/spear310-evb.dts              |  102 +++++++
 arch/arm/boot/dts/spear310.dtsi                 |   75 +++++
 arch/arm/boot/dts/spear320-evb.dts              |  110 +++++++
 arch/arm/boot/dts/spear320.dtsi                 |   92 ++++++
 arch/arm/boot/dts/spear3xx.dtsi                 |  151 +++++++++
 arch/arm/boot/dts/spear600-evb.dts              |    4 +
 arch/arm/boot/dts/spear600.dtsi                 |    8 +
 arch/arm/configs/spear3xx_defconfig             |   52 +++-
 arch/arm/configs/spear6xx_defconfig             |   41 ++-
 arch/arm/mach-spear3xx/Kconfig                  |   40 +--
 arch/arm/mach-spear3xx/Makefile                 |   19 +-
 arch/arm/mach-spear3xx/Makefile.boot            |    4 +
 arch/arm/mach-spear3xx/clock.c                  |   93 +++---
 arch/arm/mach-spear3xx/include/mach/generic.h   |   48 ++-
 arch/arm/mach-spear3xx/include/mach/irqs.h      |    6 +-
 arch/arm/mach-spear3xx/include/mach/spear300.h  |    4 +-
 arch/arm/mach-spear3xx/include/mach/spear310.h  |    4 +-
 arch/arm/mach-spear3xx/include/mach/spear320.h  |    4 +-
 arch/arm/mach-spear3xx/spear300.c               |  253 +++++++++++++--
 arch/arm/mach-spear3xx/spear300_evb.c           |   75 -----
 arch/arm/mach-spear3xx/spear310.c               |  293 ++++++++++++++++--
 arch/arm/mach-spear3xx/spear310_evb.c           |   81 -----
 arch/arm/mach-spear3xx/spear320.c               |  293 ++++++++++++++++--
 arch/arm/mach-spear3xx/spear320_evb.c           |   79 -----
 arch/arm/mach-spear3xx/spear3xx.c               |  131 ++++++--
 arch/arm/mach-spear6xx/Makefile.boot            |    2 +
 arch/arm/mach-spear6xx/clock.c                  |    2 +-
 arch/arm/mach-spear6xx/spear6xx.c               |  372 ++++++++++++++++++++++-
 arch/arm/plat-spear/Kconfig                     |    5 +-
 arch/arm/plat-spear/Makefile                    |    4 +-
 arch/arm/plat-spear/include/plat/pl080.h        |   21 ++
 arch/arm/plat-spear/pl080.c                     |   79 +++++
 37 files changed, 2371 insertions(+), 468 deletions(-)
 create mode 100644 arch/arm/boot/dts/spear300-evb.dts
 create mode 100644 arch/arm/boot/dts/spear300.dtsi
 create mode 100644 arch/arm/boot/dts/spear310-evb.dts
 create mode 100644 arch/arm/boot/dts/spear310.dtsi
 create mode 100644 arch/arm/boot/dts/spear320-evb.dts
 create mode 100644 arch/arm/boot/dts/spear320.dtsi
 create mode 100644 arch/arm/boot/dts/spear3xx.dtsi
 delete mode 100644 arch/arm/mach-spear3xx/spear300_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear310_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear320_evb.c
 create mode 100644 arch/arm/plat-spear/include/plat/pl080.h
 create mode 100644 arch/arm/plat-spear/pl080.c

-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Mon Mar 26 07:44:00 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 26 Mar 2012 17:14:00 +0530
Subject: [PATCH 4/5] SPEAr: Add PL080 DMA support for 3xx and 6xx
In-Reply-To: <cover.1332762103.git.viresh.kumar@st.com>
References: <cover.1332762103.git.viresh.kumar@st.com>
Message-ID: <ef2f5015b01a46ea83e994f7e28d13e6ecaef0de.1332762104.git.viresh.kumar@st.com>

Both SPEAr3xx and SPEAr6xx families have one instance of ARM PL080 DMA
controller. This patch adds in support for that.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/boot/dts/spear300-evb.dts            |    4 +
 arch/arm/boot/dts/spear310-evb.dts            |    4 +
 arch/arm/boot/dts/spear320-evb.dts            |    4 +
 arch/arm/boot/dts/spear3xx.dtsi               |    8 +
 arch/arm/boot/dts/spear600-evb.dts            |    4 +
 arch/arm/boot/dts/spear600.dtsi               |    8 +
 arch/arm/mach-spear3xx/clock.c                |    2 +-
 arch/arm/mach-spear3xx/include/mach/generic.h |    2 +
 arch/arm/mach-spear3xx/spear300.c             |  190 +++++++++++++
 arch/arm/mach-spear3xx/spear310.c             |  190 +++++++++++++
 arch/arm/mach-spear3xx/spear320.c             |  190 +++++++++++++
 arch/arm/mach-spear3xx/spear3xx.c             |   21 ++
 arch/arm/mach-spear6xx/clock.c                |    2 +-
 arch/arm/mach-spear6xx/spear6xx.c             |  372 ++++++++++++++++++++++++-
 arch/arm/plat-spear/Makefile                  |    2 +-
 arch/arm/plat-spear/include/plat/pl080.h      |   21 ++
 arch/arm/plat-spear/pl080.c                   |   79 ++++++
 17 files changed, 1099 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/plat-spear/include/plat/pl080.h
 create mode 100644 arch/arm/plat-spear/pl080.c

diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index be3df48..4764ba3 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -29,6 +29,10 @@
 			status = "okay";
 		};
 
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		fsmc: flash at 94000000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index 1e14bf3..e46496f 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -25,6 +25,10 @@
 	};
 
 	ahb {
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		fsmc: flash at 44000000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index 7dea99c..ca72645 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -29,6 +29,10 @@
 			status = "okay";
 		};
 
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		fsmc: flash at 4c000000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index 1a85ff2..dc85461 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -38,6 +38,14 @@
 			#interrupt-cells = <1>;
 		};
 
+		dma at fc400000 {
+			compatible = "arm,pl080", "arm,primecell";
+			reg = <0xfc400000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <8>;
+			status = "disabled";
+		};
+
 		gmac: eth at e0800000 {
 			compatible = "st,spear600-gmac";
 			reg = <0xe0800000 0x8000>;
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e..790a7a8 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,6 +24,10 @@
 	};
 
 	ahb {
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		gmac: ethernet at e0800000 {
 			phy-mode = "gmii";
 			status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885..d777e3a 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
 			#interrupt-cells = <1>;
 		};
 
+		dma at fc400000 {
+			compatible = "arm,pl080", "arm,primecell";
+			reg = <0xfc400000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <10>;
+			status = "disabled";
+		};
+
 		gmac: ethernet at e0800000 {
 			compatible = "st,spear600-gmac";
 			reg = <0xe0800000 0x8000>;
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 1e2ddd0..d073133 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -683,7 +683,7 @@ static struct clk_lookup spear_clk_lookups[] = {
 	/* clock derived from ahb clk */
 	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
 	CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
-	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
 	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
 	CLKDEV_INIT("e080000.eth", NULL, &gmac_clk),
 	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 3469377..882b074 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,6 +14,7 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
 
+#include <linux/amba/pl08x.h>
 #include <linux/init.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
@@ -33,6 +34,7 @@
 
 /* Add spear3xx family device structure declarations here */
 extern struct sys_timer spear3xx_timer;
+extern struct pl08x_platform_data pl080_plat_data;
 
 /* Add spear3xx family function declarations here */
 void __init spear3xx_clk_init(void);
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 4d0f6c7..3a6e888 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -19,6 +19,7 @@
 #include <linux/of_platform.h>
 #include <linux/types.h>
 #include <linux/amba/pl061.h>
+#include <linux/amba/pl08x.h>
 #include <linux/ptrace.h>
 #include <asm/irq.h>
 #include <plat/shirq.h>
@@ -429,6 +430,193 @@ static struct spear_shirq shirq_ras1 = {
 	},
 };
 
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear300_dma_info[] = {
+	{
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	},
+};
+
 static struct pl061_platform_data pl061_plat_data = {
 	.gpio_base	= 8,
 	.irq_base	= SPEAR300_GPIO1_INT_BASE,
@@ -461,6 +649,8 @@ int __init spear300_init(void)
 {
 	int ret = 0;
 
+	pl080_plat_data.slave_channels = spear300_dma_info;
+	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
 
 	/* shared irq registration */
 	shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 90156bf..e2d8021 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -13,6 +13,7 @@
 
 #define pr_fmt(fmt) "SPEAr310: " fmt
 
+#include <linux/amba/pl08x.h>
 #include <linux/amba/serial.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -262,6 +263,193 @@ static struct spear_shirq shirq_intrcomm_ras = {
 	},
 };
 
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear310_dma_info[] = {
+	{
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	},
+};
+
 /* uart devices plat data */
 static struct amba_pl011_data uart_data[] = {
 	{
@@ -327,6 +515,8 @@ int __init spear310_init(void)
 	void __iomem *base;
 	int ret = 0;
 
+	pl080_plat_data.slave_channels = spear310_dma_info;
+	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
 
 	/* shared irq registration */
 	base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 582d1af..3668ea9 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -14,6 +14,7 @@
 #define pr_fmt(fmt) "SPEAr320: " fmt
 
 #include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
 #include <linux/amba/serial.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -516,6 +517,193 @@ static struct spear_shirq shirq_intrcomm_ras = {
 	},
 };
 
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear320_dma_info[] = {
+	{
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c0_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c0_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp1_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp1_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp2_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp2_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c1_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c1_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c2_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c2_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "rs485_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "rs485_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	},
+};
+
 static struct pl022_ssp_controller ssp_data[] = {
 	{
 		.bus_id = 1,
@@ -582,6 +770,8 @@ int __init spear320_init(void)
 	void __iomem *base;
 	int ret = 0;
 
+	pl080_plat_data.slave_channels = spear320_dma_info;
+	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
 
 	/* shared irq registration */
 	base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index a2bfb86..90cd9fb 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -15,6 +15,7 @@
 
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl061.h>
+#include <linux/amba/pl08x.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -22,9 +23,11 @@
 #include <linux/types.h>
 #include <linux/ptrace.h>
 #include <linux/io.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
@@ -53,6 +56,22 @@ static struct pl061_platform_data pl061_plat_data = {
 	.irq_base	= SPEAR3XX_GPIO_INT_BASE,
 };
 
+/* dmac device registration */
+struct pl08x_platform_data pl080_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl080_get_signal,
+	.put_signal = pl080_put_signal,
+};
 
 /* Add auxdata to pass platform data */
 struct of_dev_auxdata spear3xx_auxdata_lookup[] __initdata = {
@@ -60,6 +79,8 @@ struct of_dev_auxdata spear3xx_auxdata_lookup[] __initdata = {
 			&pl022_plat_data),
 	OF_DEV_AUXDATA("arm,pl061", SPEAR3XX_ICM3_GPIO_BASE, NULL,
 			&pl061_plat_data),
+	OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+			&pl080_plat_data),
 	{}
 };
 
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 5a46980..adadef2 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -657,7 +657,7 @@ static struct clk_lookup spear_clk_lookups[] = {
 	/* clock derived from ahb clk */
 	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
 	CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
-	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
 	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
 	CLKDEV_INIT("gmac", NULL, &gmac_clk),
 	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index d436118..8bbbee3 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,15 +13,377 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/amba/pl08x.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
+/* dmac device registration */
+static struct pl08x_channel_data spear600_dma_info[] = {
+	{
+		.bus_id = "ssp1_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp1_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp2_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp2_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ext0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	},
+};
+
+struct pl08x_platform_data pl080_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl080_get_signal,
+	.put_signal = pl080_put_signal,
+	.slave_channels = spear600_dma_info,
+	.num_slave_channels = ARRAY_SIZE(spear600_dma_info),
+};
+
 /* Following will create static virtual/physical mappings */
 static struct map_desc spear6xx_io_desc[] __initdata = {
 	{
@@ -92,9 +454,17 @@ struct sys_timer spear6xx_timer = {
 	.init = spear6xx_timer_init,
 };
 
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
+			&pl080_plat_data),
+	{}
+};
+
 static void __init spear600_dt_init(void)
 {
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table,
+			spear6xx_auxdata_lookup, NULL);
 }
 
 static const char *spear600_dt_board_compat[] = {
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 4b906bb..cc87823 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
 #
 
 # Common support
-obj-y	:= clock.o restart.o time.o
+obj-y	:= clock.o restart.o time.o pl080.o
 
 obj-$(CONFIG_ARCH_SPEAR3XX_DT)	+= shirq.o padmux.o
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644
index 0000000..e14a3e4
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/plat-spear/include/plat/pl080.h
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PL080_H
+#define __PLAT_PL080_H
+
+struct pl08x_dma_chan;
+int pl080_get_signal(struct pl08x_dma_chan *ch);
+void pl080_put_signal(struct pl08x_dma_chan *ch);
+
+#endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644
index 0000000..d53d75e
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,79 @@
+/*
+ * arch/arm/plat-spear/pl080.c
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/bus.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spinlock_types.h>
+#include <mach/misc_regs.h>
+
+static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
+
+struct {
+	unsigned char busy;
+	unsigned char val;
+} signals[16] = {{0, 0}, };
+
+int pl080_get_signal(struct pl08x_dma_chan *ch)
+{
+	const struct pl08x_channel_data *cd = ch->cd;
+	unsigned int signal = cd->min_signal, val;
+	unsigned long flags;
+
+	spin_lock_irqsave(&lock, flags);
+
+	/* Return if signal is already acquired by somebody else */
+	if (signals[signal].busy &&
+			(signals[signal].val != cd->muxval)) {
+		spin_unlock_irqrestore(&lock, flags);
+		return -EBUSY;
+	}
+
+	/* If acquiring for the first time, configure it */
+	if (!signals[signal].busy) {
+		val = readl(DMA_CHN_CFG);
+
+		/*
+		 * Each request line has two bits in DMA_CHN_CFG register. To
+		 * goto the bits of current request line, do left shift of
+		 * value by 2 * signal number.
+		 */
+		val &= ~(0x3 << (signal * 2));
+		val |= cd->muxval << (signal * 2);
+		writel(val, DMA_CHN_CFG);
+	}
+
+	signals[signal].busy++;
+	signals[signal].val = cd->muxval;
+	spin_unlock_irqrestore(&lock, flags);
+
+	return signal;
+}
+
+void pl080_put_signal(struct pl08x_dma_chan *ch)
+{
+	const struct pl08x_channel_data *cd = ch->cd;
+	unsigned long flags;
+
+	spin_lock_irqsave(&lock, flags);
+
+	/* if signal is not used */
+	if (!signals[cd->min_signal].busy)
+		BUG();
+
+	signals[cd->min_signal].busy--;
+
+	spin_unlock_irqrestore(&lock, flags);
+}
-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Mon Mar 26 07:44:01 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 26 Mar 2012 17:14:01 +0530
Subject: [PATCH 5/5] SPEAr: Update defconfigs
In-Reply-To: <cover.1332762103.git.viresh.kumar@st.com>
References: <cover.1332762103.git.viresh.kumar@st.com>
Message-ID: <f839f59849ad27bf0ab54afd45da67ff97fcaa79.1332762104.git.viresh.kumar@st.com>

Recently device tree support is added for SPEAr3xx & SPEAr6xx and we must
upgrade defconfig for that to get compiled. This patches does it.

There are few more rearrangements done in defconfig automatically, when i run
make savedefconfig.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/configs/spear3xx_defconfig |   52 +++++++++++++++++++++++++++--------
 arch/arm/configs/spear6xx_defconfig |   41 +++++++++++++++++++++------
 2 files changed, 74 insertions(+), 19 deletions(-)

diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f..1fba278 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,67 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
-CONFIG_BOARD_SPEAR300_EVB=y
-CONFIG_BOARD_SPEAR310_EVB=y
-CONFIG_BOARD_SPEAR320_EVB=y
+CONFIG_MACH_SPEAR300_DT=y
+CONFIG_MACH_SPEAR310_DT=y
+CONFIG_MACH_SPEAR320_DT=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
 # CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +73,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -48,6 +80,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e83..cf94bc7 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,58 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
-CONFIG_BOARD_SPEAR600_EVB=y
+CONFIG_BOARD_SPEAR600_DT=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +64,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -44,6 +71,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Mon Mar 26 07:43:59 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Mon, 26 Mar 2012 17:13:59 +0530
Subject: [PATCH 3/5] ARM: SPEAr3xx: Add device-tree support to SPEAr3xx
 architecture
In-Reply-To: <cover.1332762103.git.viresh.kumar@st.com>
References: <cover.1332762103.git.viresh.kumar@st.com>
Message-ID: <c9e1f541b04b60c1fbc2ed120c94f2d1b6b6e091.1332762103.git.viresh.kumar@st.com>

This patch adds a generic target for SPEAr3xx machines that can be configured
via the device-tree. Currently the following devices are supported via the
devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- PL110 CLCD
- SP805 WDT
- Synopsys DW I2C
- Synopsys DW ethernet
- ST FSMC-NAND
- ST SPEAR-SMI
- ST SPEAR-KEYBOARD
- ST SPEAR-RTC
- ARASAN SDHCI-SPEAR
- SPEAR-EHCI
- SPEAR-OHCI

Other peripheral devices will follow in later patches.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 Documentation/arm/SPEAr/overview.txt            |   13 +-
 Documentation/devicetree/bindings/arm/spear.txt |   18 +++
 arch/arm/Makefile                               |    6 +-
 arch/arm/boot/dts/spear300-evb.dts              |  177 +++++++++++++++++++++++
 arch/arm/boot/dts/spear300.dtsi                 |   74 ++++++++++
 arch/arm/boot/dts/spear310-evb.dts              |   98 +++++++++++++
 arch/arm/boot/dts/spear310.dtsi                 |   75 ++++++++++
 arch/arm/boot/dts/spear320-evb.dts              |  106 ++++++++++++++
 arch/arm/boot/dts/spear320.dtsi                 |   92 ++++++++++++
 arch/arm/boot/dts/spear3xx.dtsi                 |  143 ++++++++++++++++++
 arch/arm/mach-spear3xx/Kconfig                  |   40 ++---
 arch/arm/mach-spear3xx/Makefile                 |   19 +--
 arch/arm/mach-spear3xx/Makefile.boot            |    4 +
 arch/arm/mach-spear3xx/clock.c                  |   91 ++++++------
 arch/arm/mach-spear3xx/include/mach/generic.h   |   46 +++---
 arch/arm/mach-spear3xx/include/mach/irqs.h      |    6 +-
 arch/arm/mach-spear3xx/include/mach/spear300.h  |    4 +-
 arch/arm/mach-spear3xx/include/mach/spear310.h  |    4 +-
 arch/arm/mach-spear3xx/include/mach/spear320.h  |    4 +-
 arch/arm/mach-spear3xx/spear300.c               |   55 +++++--
 arch/arm/mach-spear3xx/spear300_evb.c           |   75 ----------
 arch/arm/mach-spear3xx/spear310.c               |   90 ++++++++++--
 arch/arm/mach-spear3xx/spear310_evb.c           |   81 -----------
 arch/arm/mach-spear3xx/spear320.c               |   92 ++++++++++--
 arch/arm/mach-spear3xx/spear320_evb.c           |   79 ----------
 arch/arm/mach-spear3xx/spear3xx.c               |  108 +++++++++++---
 arch/arm/plat-spear/Kconfig                     |    5 +-
 arch/arm/plat-spear/Makefile                    |    2 +-
 28 files changed, 1176 insertions(+), 431 deletions(-)
 create mode 100644 arch/arm/boot/dts/spear300-evb.dts
 create mode 100644 arch/arm/boot/dts/spear300.dtsi
 create mode 100644 arch/arm/boot/dts/spear310-evb.dts
 create mode 100644 arch/arm/boot/dts/spear310.dtsi
 create mode 100644 arch/arm/boot/dts/spear320-evb.dts
 create mode 100644 arch/arm/boot/dts/spear320.dtsi
 create mode 100644 arch/arm/boot/dts/spear3xx.dtsi
 delete mode 100644 arch/arm/mach-spear3xx/spear300_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear310_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear320_evb.c

diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c..28a9af9 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -17,14 +17,14 @@ Introduction
   SPEAr (Platform)
 	- SPEAr3XX (3XX SOC series, based on ARM9)
 		- SPEAr300 (SOC)
-			- SPEAr300_EVB (Evaluation Board)
+			- SPEAr300 Evaluation Board
 		- SPEAr310 (SOC)
-			- SPEAr310_EVB (Evaluation Board)
+			- SPEAr310 Evaluation Board
 		- SPEAr320 (SOC)
-			- SPEAr320_EVB (Evaluation Board)
+			- SPEAr320 Evaluation Board
 	- SPEAr6XX (6XX SOC series, based on ARM9)
 		- SPEAr600 (SOC)
-			- SPEAr600_EVB (Evaluation Board)
+			- SPEAr600 Evaluation Board
 	- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
 		- SPEAr1300 (SOC)
 
@@ -51,10 +51,11 @@ Introduction
   Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
   spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
   specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
-  mach-spear* also contains board specific files for each machine type.
+  mach-spear* doesn't contains board specific files as they fully support
+  Flattened Device Tree.
 
 
   Document Author
   ---------------
 
-  Viresh Kumar, (c) 2010 ST Microelectronics
+  Viresh Kumar <viresh.kumar at st.com>, (c) 2010-2012 ST Microelectronics
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
index f8e54f0..aa5f355 100644
--- a/Documentation/devicetree/bindings/arm/spear.txt
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -6,3 +6,21 @@ Boards with the ST SPEAr600 SoC shall have the following properties:
 Required root node property:
 
 compatible = "st,spear600";
+
+Boards with the ST SPEAr300 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear300";
+
+Boards with the ST SPEAr310 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear310";
+
+Boards with the ST SPEAr320 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear320";
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 047a207..0f0acd9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -192,9 +192,9 @@ machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
 machine-$(CONFIG_ARCH_VT8500)		:= vt8500
 machine-$(CONFIG_ARCH_W90X900)		:= w90x900
 machine-$(CONFIG_FOOTBRIDGE)		:= footbridge
-machine-$(CONFIG_MACH_SPEAR300)		:= spear3xx
-machine-$(CONFIG_MACH_SPEAR310)		:= spear3xx
-machine-$(CONFIG_MACH_SPEAR320)		:= spear3xx
+machine-$(CONFIG_MACH_SPEAR300_DT)	:= spear3xx
+machine-$(CONFIG_MACH_SPEAR310_DT)	:= spear3xx
+machine-$(CONFIG_MACH_SPEAR320_DT)	:= spear3xx
 machine-$(CONFIG_MACH_SPEAR600)		:= spear6xx
 machine-$(CONFIG_ARCH_ZYNQ)		:= zynq
 
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644
index 0000000..be3df48
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,177 @@
+/*
+ * DTS file for SPEAr300 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear300.dtsi"
+
+/ {
+	model = "ST SPEAr300 Evaluation Board";
+	compatible = "st,spear300-evb", "st,spear300";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		clcd at 60000000 {
+			status = "okay";
+		};
+
+		fsmc: flash at 94000000 {
+			status = "okay";
+		};
+
+		gmac: eth at e0800000 {
+			status = "okay";
+		};
+
+		sdhci at 70000000 {
+			status = "okay";
+		};
+
+		smi: flash at fc000000 {
+			status = "okay";
+		};
+
+		spi at d0100000 {
+			status = "okay";
+		};
+
+		ehci at e1800000 {
+			status = "okay";
+		};
+
+		ohci at e1900000 {
+			status = "okay";
+		};
+
+		ohci at e2100000 {
+			status = "okay";
+		};
+
+		apb {
+			gpio0: gpio at fc980000 {
+			       status = "okay";
+			};
+
+			gpio1: gpio at a9000000 {
+			       status = "okay";
+			};
+
+			i2c at d0180000 {
+			       status = "okay";
+			};
+
+			kbd at a0000000 {
+				linux,keymap = < 0x00010000
+						 0x00020100
+						 0x00030200
+						 0x00040300
+						 0x00050400
+						 0x00060500
+						 0x00070600
+						 0x00080700
+						 0x00090800
+						 0x000a0001
+						 0x000c0101
+						 0x000d0201
+						 0x000e0301
+						 0x000f0401
+						 0x00100501
+						 0x00110601
+						 0x00120701
+						 0x00130801
+						 0x00140002
+						 0x00150102
+						 0x00160202
+						 0x00170302
+						 0x00180402
+						 0x00190502
+						 0x001a0602
+						 0x001b0702
+						 0x001c0802
+						 0x001d0003
+						 0x001e0103
+						 0x001f0203
+						 0x00200303
+						 0x00210403
+						 0x00220503
+						 0x00230603
+						 0x00240703
+						 0x00250803
+						 0x00260004
+						 0x00270104
+						 0x00280204
+						 0x00290304
+						 0x002a0404
+						 0x002b0504
+						 0x002c0604
+						 0x002d0704
+						 0x002e0804
+						 0x002f0005
+						 0x00300105
+						 0x00310205
+						 0x00320305
+						 0x00330405
+						 0x00340505
+						 0x00350605
+						 0x00360705
+						 0x00370805
+						 0x00380006
+						 0x00390106
+						 0x003a0206
+						 0x003b0306
+						 0x003c0406
+						 0x003d0506
+						 0x003e0606
+						 0x003f0706
+						 0x00400806
+						 0x00410007
+						 0x00420107
+						 0x00430207
+						 0x00440307
+						 0x00450407
+						 0x00460507
+						 0x00470607
+						 0x00480707
+						 0x00490807
+						 0x004a0008
+						 0x004b0108
+						 0x004c0208
+						 0x004d0308
+						 0x004e0408
+						 0x004f0508
+						 0x00500608
+						 0x00510708
+						 0x00520808 >;
+			       autorepeat;
+			       mode = <0>;
+			       status = "okay";
+			};
+
+			rtc at fc900000 {
+			       status = "okay";
+			};
+
+			serial at d0000000 {
+			       status = "okay";
+			};
+
+			wdt at fc880000 {
+			       status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644
index 0000000..ed8ecd8
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,74 @@
+/*
+ * DTS file for SPEAr300 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x60000000 0x60000000 0x50000000
+			  0xd0000000 0xd0000000 0x30000000>;
+
+		clcd at 60000000 {
+			compatible = "arm,clcd-pl110", "arm,primecell";
+			reg = <0x60000000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <30>;
+			status = "disabled";
+		};
+
+		fsmc: flash at 94000000 {
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x94000000 0x1000	/* FSMC Register */
+			       0x80000000 0x0010>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x20000>;
+			st,cle-off = <0x10000>;
+			status = "disabled";
+		};
+
+		sdhci at 70000000 {
+			compatible = "st,sdhci-spear";
+			reg = <0x70000000 0x100>;
+			interrupt-parent = <&vic>;
+			interrupts = <1>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xa0000000 0xa0000000 0x10000000
+				  0xd0000000 0xd0000000 0x30000000>;
+
+			gpio1: gpio at a9000000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xa9000000 0x1000>;
+				status = "disabled";
+			};
+
+			kbd at a0000000 {
+				compatible = "st,spear-kbd";
+				reg = <0xa0000000 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644
index 0000000..1e14bf3
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,98 @@
+/*
+ * DTS file for SPEAr310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear310.dtsi"
+
+/ {
+	model = "ST SPEAr310 Evaluation Board";
+	compatible = "st,spear310-evb", "st,spear310";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		fsmc: flash at 44000000 {
+			status = "okay";
+		};
+
+		gmac: eth at e0800000 {
+			status = "okay";
+		};
+
+		smi: flash at fc000000 {
+			status = "okay";
+		};
+
+		spi at d0100000 {
+			status = "okay";
+		};
+
+		ehci at e1800000 {
+			status = "okay";
+		};
+
+		ohci at e1900000 {
+			status = "okay";
+		};
+
+		ohci at e2100000 {
+			status = "okay";
+		};
+
+		apb {
+			gpio0: gpio at fc980000 {
+			       status = "okay";
+			};
+
+			i2c at d0180000 {
+			       status = "okay";
+			};
+
+			rtc at fc900000 {
+			       status = "okay";
+			};
+
+			serial at d0000000 {
+			       status = "okay";
+			};
+
+			serial at b2000000 {
+			       status = "okay";
+			};
+
+			serial at b2080000 {
+			       status = "okay";
+			};
+
+			serial at b2100000 {
+			       status = "okay";
+			};
+
+			serial at b2180000 {
+			       status = "okay";
+			};
+
+			serial at b2200000 {
+			       status = "okay";
+			};
+
+			wdt at fc880000 {
+			       status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644
index 0000000..dc7fa14
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,75 @@
+/*
+ * DTS file for SPEAr310 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x40000000 0x40000000 0x10000000
+			  0xb0000000 0xb0000000 0x10000000
+			  0xd0000000 0xd0000000 0x30000000>;
+
+		fsmc: flash at 44000000 {
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x44000000 0x1000	/* FSMC Register */
+			       0x40000000 0x0010>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x10000>;
+			st,cle-off = <0x20000>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xb0000000 0xb0000000 0x10000000
+				  0xd0000000 0xd0000000 0x30000000>;
+
+			serial at b2000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2000000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2080000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2080000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2100000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2100000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2180000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2180000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2200000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2200000 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644
index 0000000..7dea99c
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,106 @@
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear320.dtsi"
+
+/ {
+	model = "ST SPEAr300 Evaluation Board";
+	compatible = "st,spear300-evb", "st,spear300";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		clcd at 90000000 {
+			status = "okay";
+		};
+
+		fsmc: flash at 4c000000 {
+			status = "okay";
+		};
+
+		gmac: eth at e0800000 {
+			status = "okay";
+		};
+
+		sdhci at 70000000 {
+			status = "okay";
+		};
+
+		smi: flash at fc000000 {
+			status = "okay";
+		};
+
+		spi at d0100000 {
+			status = "okay";
+		};
+
+		spi at a5000000 {
+			status = "okay";
+		};
+
+		spi at a6000000 {
+			status = "okay";
+		};
+
+		ehci at e1800000 {
+			status = "okay";
+		};
+
+		ohci at e1900000 {
+			status = "okay";
+		};
+
+		ohci at e2100000 {
+			status = "okay";
+		};
+
+		apb {
+			gpio0: gpio at fc980000 {
+			       status = "okay";
+			};
+
+			i2c at d0180000 {
+			       status = "okay";
+			};
+
+			i2c at a7000000 {
+			       status = "okay";
+			};
+
+			rtc at fc900000 {
+			       status = "okay";
+			};
+
+			serial at d0000000 {
+			       status = "okay";
+			};
+
+			serial at a3000000 {
+			       status = "okay";
+			};
+
+			serial at a4000000 {
+			       status = "okay";
+			};
+
+			wdt at fc880000 {
+			       status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644
index 0000000..422f508
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,92 @@
+/*
+ * DTS file for SPEAr320 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x40000000 0x40000000 0x70000000
+			  0xd0000000 0xd0000000 0x30000000>;
+
+		clcd at 90000000 {
+			compatible = "arm,clcd-pl110", "arm,primecell";
+			reg = <0x90000000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <33>;
+			status = "disabled";
+		};
+
+		fsmc: flash at 4c000000 {
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x4c000000 0x1000	/* FSMC Register */
+			       0x50000000 0x0010>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x20000>;
+			st,cle-off = <0x10000>;
+			status = "disabled";
+		};
+
+		sdhci at 70000000 {
+			compatible = "st,sdhci-spear";
+			reg = <0x70000000 0x100>;
+			interrupt-parent = <&vic>;
+			interrupts = <29>;
+			status = "disabled";
+		};
+
+		spi at a5000000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0xa5000000 0x1000>;
+			status = "disabled";
+		};
+
+		spi at a6000000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0xa6000000 0x1000>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xa0000000 0xa0000000 0x10000000
+				  0xd0000000 0xd0000000 0x30000000>;
+
+			i2c at a7000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,designware-i2c";
+				reg = <0xa7000000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at a3000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xa3000000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at a4000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xa4000000 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644
index 0000000..1a85ff2
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,143 @@
+/*
+ * DTS file for all SPEAr3xx SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+		vic: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		gmac: eth at e0800000 {
+			compatible = "st,spear600-gmac";
+			reg = <0xe0800000 0x8000>;
+			interrupt-parent = <&vic>;
+			interrupts = <23 22>;
+			interrupt-names = "macirq", "eth_wake_irq";
+			status = "disabled";
+		};
+
+		smi: flash at fc000000 {
+			compatible = "st,spear600-smi";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xfc000000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <9>;
+			status = "disabled";
+		};
+
+		spi at d0100000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0xd0100000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <20>;
+			status = "disabled";
+		};
+
+		ehci at e1800000 {
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe1800000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <26>;
+			status = "disabled";
+		};
+
+		ohci at e1900000 {
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe1900000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <25>;
+			status = "disabled";
+		};
+
+		ohci at e2100000 {
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe2100000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <27>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+			gpio0: gpio at fc980000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xfc980000 0x1000>;
+				interrupt-parent = <&vic>;
+				interrupts = <11>;
+				status = "disabled";
+			};
+
+			i2c at d0180000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,designware-i2c";
+				reg = <0xd0180000 0x1000>;
+				interrupt-parent = <&vic>;
+				interrupts = <21>;
+				status = "disabled";
+			};
+
+			rtc at fc900000 {
+				compatible = "st,spear-rtc";
+				reg = <0xfc900000 0x1000>;
+				interrupt-parent = <&vic>;
+				interrupts = <10>;
+				status = "disabled";
+			};
+
+			serial at d0000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0000000 0x1000>;
+				interrupt-parent = <&vic>;
+				interrupts = <19>;
+				status = "disabled";
+			};
+
+			wdt at fc880000 {
+				compatible = "arm,sp805", "arm,primecell";
+				reg = <0xfc880000 0x1000>;
+				interrupt-parent = <&vic>;
+				interrupts = <12>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0..2817b46 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -2,42 +2,22 @@
 # SPEAr3XX Machine configuration file
 #
 
-if ARCH_SPEAR3XX
+if ARCH_SPEAR3XX_DT
 
 menu "SPEAr3xx Implementations"
-config BOARD_SPEAR300_EVB
-	bool "SPEAr300 Evaluation Board"
-	select MACH_SPEAR300
+config MACH_SPEAR300_DT
+	bool "SPEAr300 Machine support with Device Tree"
 	help
-	  Supports ST SPEAr300 Evaluation Board
+	  Supports ST SPEAr300 machine configured via the device-tree
 
-config BOARD_SPEAR310_EVB
-	bool "SPEAr310 Evaluation Board"
-	select MACH_SPEAR310
+config MACH_SPEAR310_DT
+	bool "SPEAr310 Machine support with Device Tree"
 	help
-	  Supports ST SPEAr310 Evaluation Board
+	  Supports ST SPEAr310 machine configured via the device-tree
 
-config BOARD_SPEAR320_EVB
-	bool "SPEAr320 Evaluation Board"
-	select MACH_SPEAR320
+config MACH_SPEAR320_DT
+	bool "SPEAr320 Machine support with Device Tree"
 	help
-	  Supports ST SPEAr320 Evaluation Board
-
+	  Supports ST SPEAr320 machine configured via the device-tree
 endmenu
-
-config MACH_SPEAR300
-	bool "SPEAr300"
-	help
-	  Supports ST SPEAr300 Machine
-
-config MACH_SPEAR310
-	bool "SPEAr310"
-	help
-	  Supports ST SPEAr310 Machine
-
-config MACH_SPEAR320
-	bool "SPEAr320"
-	help
-	  Supports ST SPEAr320 Machine
-
 endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b248624..25526b6 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
 #
 
 # common files
-obj-y	+= spear3xx.o clock.o
+obj-$(CONFIG_ARCH_SPEAR3XX_DT)	+= spear3xx.o clock.o
 
 # spear300 specific files
-obj-$(CONFIG_MACH_SPEAR300) += spear300.o
-
-# spear300 boards files
-obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
-
+obj-$(CONFIG_MACH_SPEAR300_DT) += spear300.o
 
 # spear310 specific files
-obj-$(CONFIG_MACH_SPEAR310) += spear310.o
-
-# spear310 boards files
-obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
-
+obj-$(CONFIG_MACH_SPEAR310_DT) += spear310.o
 
 # spear320 specific files
-obj-$(CONFIG_MACH_SPEAR320) += spear320.o
-
-# spear320 boards files
-obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
+obj-$(CONFIG_MACH_SPEAR320_DT) += spear320.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c..fe371b7 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
 zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR300_DT)	+= spear300-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR310_DT)	+= spear310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR320_DT)	+= spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6b2cd9b..1e2ddd0 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of_platform.h>
 #include <asm/mach-types.h>
 #include <plat/clock.h>
 #include <mach/misc_regs.h>
@@ -493,7 +494,7 @@ static struct clk adc_clk = {
 	.recalc = &follow_parent,
 };
 
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR310_DT) || defined(CONFIG_MACH_SPEAR320_DT)
 /* emi clock */
 static struct clk emi_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -520,8 +521,8 @@ static struct clk gpio_clk = {
 
 static struct clk dummy_apb_pclk;
 
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
-	defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR300_DT) || defined(CONFIG_MACH_SPEAR310_DT) || \
+	defined(CONFIG_MACH_SPEAR320_DT)
 /* fsmc clock */
 static struct clk fsmc_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -531,7 +532,7 @@ static struct clk fsmc_clk = {
 #endif
 
 /* common clocks to spear310 and spear320 */
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR310_DT) || defined(CONFIG_MACH_SPEAR320_DT)
 /* uart1 clock */
 static struct clk uart1_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -545,10 +546,10 @@ static struct clk uart2_clk = {
 	.pclk = &apb_clk,
 	.recalc = &follow_parent,
 };
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
+#endif /* CONFIG_MACH_SPEAR310_DT || CONFIG_MACH_SPEAR320_DT */
 
 /* common clocks to spear300 and spear320 */
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR300_DT) || defined(CONFIG_MACH_SPEAR310_DT)
 /* clcd clock */
 static struct clk clcd_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -562,10 +563,10 @@ static struct clk sdhci_clk = {
 	.pclk = &ahb_clk,
 	.recalc = &follow_parent,
 };
-#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
+#endif /* CONFIG_MACH_SPEAR300_DT || CONFIG_MACH_SPEAR320_DT */
 
 /* spear300 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR300
+#ifdef CONFIG_MACH_SPEAR300_DT
 /* gpio1 clock */
 static struct clk gpio1_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -583,7 +584,7 @@ static struct clk kbd_clk = {
 #endif
 
 /* spear310 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR310
+#ifdef CONFIG_MACH_SPEAR310_DT
 /* uart3 clock */
 static struct clk uart3_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -607,7 +608,7 @@ static struct clk uart5_clk = {
 #endif
 
 /* spear320 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR320
+#ifdef CONFIG_MACH_SPEAR320_DT
 /* can0 clock */
 static struct clk can0_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -658,11 +659,11 @@ static struct clk_lookup spear_clk_lookups[] = {
 	CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
 	CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
 	/* clock derived from 32 KHz osc clk */
-	CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
+	CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk),
 	/* clock derived from 24 MHz osc clk */
 	CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
 	CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
-	CLKDEV_INIT("wdt", NULL, &wdt_clk),
+	CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk),
 	/* clock derived from pll1 clk */
 	CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
 	CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
@@ -671,7 +672,7 @@ static struct clk_lookup spear_clk_lookups[] = {
 	CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
 	CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
 	CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
-	CLKDEV_INIT("uart", NULL, &uart_clk),
+	CLKDEV_INIT("d0000000.serial", NULL, &uart_clk),
 	CLKDEV_INIT("firda", NULL, &firda_clk),
 	CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
 	CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
@@ -681,69 +682,69 @@ static struct clk_lookup spear_clk_lookups[] = {
 	CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
 	/* clock derived from ahb clk */
 	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
-	CLKDEV_INIT("i2c_designware.0", NULL, &i2c_clk),
+	CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
 	CLKDEV_INIT("dma", NULL, &dma_clk),
 	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
-	CLKDEV_INIT("gmac", NULL, &gmac_clk),
-	CLKDEV_INIT("smi", NULL, &smi_clk),
+	CLKDEV_INIT("e080000.eth", NULL, &gmac_clk),
+	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
 	CLKDEV_INIT("c3", NULL, &c3_clk),
 	/* clock derived from apb clk */
 	CLKDEV_INIT("adc", NULL, &adc_clk),
-	CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
-	CLKDEV_INIT("gpio", NULL, &gpio_clk),
+	CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk),
+	CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk),
 };
 
 /* array of all spear 300 clock lookups */
-#ifdef CONFIG_MACH_SPEAR300
 static struct clk_lookup spear300_clk_lookups[] = {
-	CLKDEV_INIT("clcd", NULL, &clcd_clk),
-	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
-	CLKDEV_INIT("gpio1", NULL, &gpio1_clk),
-	CLKDEV_INIT("keyboard", NULL, &kbd_clk),
-	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
-};
+#ifdef CONFIG_MACH_SPEAR300_DT
+	CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk),
+	CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk),
+	CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk),
+	CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
 #endif
+};
 
 /* array of all spear 310 clock lookups */
-#ifdef CONFIG_MACH_SPEAR310
 static struct clk_lookup spear310_clk_lookups[] = {
-	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+#ifdef CONFIG_MACH_SPEAR310_DT
+	CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk),
 	CLKDEV_INIT(NULL, "emi", &emi_clk),
-	CLKDEV_INIT("uart1", NULL, &uart1_clk),
-	CLKDEV_INIT("uart2", NULL, &uart2_clk),
-	CLKDEV_INIT("uart3", NULL, &uart3_clk),
-	CLKDEV_INIT("uart4", NULL, &uart4_clk),
-	CLKDEV_INIT("uart5", NULL, &uart5_clk),
-};
+	CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk),
+	CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk),
+	CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk),
+	CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk),
+	CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk),
 #endif
+};
 
 /* array of all spear 320 clock lookups */
-#ifdef CONFIG_MACH_SPEAR320
 static struct clk_lookup spear320_clk_lookups[] = {
-	CLKDEV_INIT("clcd", NULL, &clcd_clk),
-	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
-	CLKDEV_INIT("i2c_designware.1", NULL, &i2c1_clk),
+#ifdef CONFIG_MACH_SPEAR320_DT
+	CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk),
+	CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk),
 	CLKDEV_INIT(NULL, "emi", &emi_clk),
 	CLKDEV_INIT("pwm", NULL, &pwm_clk),
-	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
+	CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
 	CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
 	CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
-	CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
-	CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
-	CLKDEV_INIT("uart1", NULL, &uart1_clk),
-	CLKDEV_INIT("uart2", NULL, &uart2_clk),
-};
+	CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk),
+	CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk),
+	CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk),
+	CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk),
 #endif
+};
 
 void __init spear3xx_clk_init(void)
 {
 	int i, cnt;
 	struct clk_lookup *lookups;
 
-	if (machine_is_spear300()) {
+	if (of_machine_is_compatible("st,spear300")) {
 		cnt = ARRAY_SIZE(spear300_clk_lookups);
 		lookups = spear300_clk_lookups;
-	} else if (machine_is_spear310()) {
+	} else if (of_machine_is_compatible("st,spear310")) {
 		cnt = ARRAY_SIZE(spear310_clk_lookups);
 		lookups = spear310_clk_lookups;
 	} else {
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5..3469377 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -15,6 +15,7 @@
 #define __MACH_GENERIC_H
 
 #include <linux/init.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <asm/mach/time.h>
@@ -31,15 +32,12 @@
 #define SPEAR_GPT0_CHAN1_IRQ	SPEAR3XX_IRQ_CPU_GPT1_2
 
 /* Add spear3xx family device structure declarations here */
-extern struct amba_device spear3xx_gpio_device;
-extern struct amba_device spear3xx_uart_device;
 extern struct sys_timer spear3xx_timer;
 
 /* Add spear3xx family function declarations here */
 void __init spear3xx_clk_init(void);
 void __init spear_setup_timer(void);
 void __init spear3xx_map_io(void);
-void __init spear3xx_init_irq(void);
 void __init spear3xx_init(void);
 
 void spear_restart(char, const char *);
@@ -78,7 +76,7 @@ extern struct pmx_dev spear3xx_pmx_uart0;
 extern struct pmx_dev spear3xx_pmx_timer_3_4;
 extern struct pmx_dev spear3xx_pmx_timer_1_2;
 
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR310_DT) || defined(CONFIG_MACH_SPEAR320_DT)
 /* padmux plgpio devices */
 extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
 extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
@@ -98,10 +96,7 @@ extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
 #endif
 
 /* spear300 declarations */
-#ifdef CONFIG_MACH_SPEAR300
-/* Add spear300 machine device structure declarations here */
-extern struct amba_device spear300_gpio1_device;
-
+#ifdef CONFIG_MACH_SPEAR300_DT
 /* pad mux modes */
 extern struct pmx_mode spear300_nand_mode;
 extern struct pmx_mode spear300_nor_mode;
@@ -133,16 +128,15 @@ extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
 extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
 extern struct pmx_dev spear300_pmx_gpio1;
 
-/* Add spear300 machine function declarations here */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count);
+/* Add spear300 machine declarations here */
+extern struct of_dev_auxdata spear300_auxdata_lookup[] __initdata;
 
-#endif /* CONFIG_MACH_SPEAR300 */
+int __init spear300_init(void);
 
-/* spear310 declarations */
-#ifdef CONFIG_MACH_SPEAR310
-/* Add spear310 machine device structure declarations here */
+#endif /* CONFIG_MACH_SPEAR300_DT */
 
+/* spear310 declarations */
+#ifdef CONFIG_MACH_SPEAR310_DT
 /* pad mux devices */
 extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
 extern struct pmx_dev spear310_pmx_emi_cs_2_3;
@@ -153,16 +147,15 @@ extern struct pmx_dev spear310_pmx_fsmc;
 extern struct pmx_dev spear310_pmx_rs485_0_1;
 extern struct pmx_dev spear310_pmx_tdm0;
 
-/* Add spear310 machine function declarations here */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count);
+/* Add spear310 machine declarations here */
+extern struct of_dev_auxdata spear310_auxdata_lookup[] __initdata;
 
-#endif /* CONFIG_MACH_SPEAR310 */
+int __init spear310_init(void);
 
-/* spear320 declarations */
-#ifdef CONFIG_MACH_SPEAR320
-/* Add spear320 machine device structure declarations here */
+#endif /* CONFIG_MACH_SPEAR310_DT */
 
+/* spear320 declarations */
+#ifdef CONFIG_MACH_SPEAR320_DT
 /* pad mux modes */
 extern struct pmx_mode spear320_auto_net_smii_mode;
 extern struct pmx_mode spear320_auto_net_mii_mode;
@@ -193,10 +186,11 @@ extern struct pmx_dev spear320_pmx_smii0;
 extern struct pmx_dev spear320_pmx_smii1;
 extern struct pmx_dev spear320_pmx_i2c1;
 
-/* Add spear320 machine function declarations here */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count);
+/* Add spear320 machine declarations here */
+extern struct of_dev_auxdata spear320_auxdata_lookup[] __initdata;
+
+int __init spear320_init(void);
 
-#endif /* CONFIG_MACH_SPEAR320 */
+#endif /* CONFIG_MACH_SPEAR320_DT */
 
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e26544..90ed5ef 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -129,9 +129,9 @@
  * Use the lowest number for the GPIO virtual IRQs base on which subarchs
  * we have compiled in
  */
-#if defined(CONFIG_MACH_SPEAR310)
+#if defined(CONFIG_MACH_SPEAR310_DT)
 #define SPEAR3XX_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 18)
-#elif defined(CONFIG_MACH_SPEAR320)
+#elif defined(CONFIG_MACH_SPEAR320_DT)
 #define SPEAR3XX_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 17)
 #else
 #define SPEAR3XX_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 9)
@@ -140,7 +140,7 @@
 #define SPEAR300_GPIO1_INT_BASE			(SPEAR3XX_GPIO_INT_BASE + 8)
 #define SPEAR3XX_PLGPIO_COUNT	102
 
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR310_DT) || defined(CONFIG_MACH_SPEAR320_DT)
 #define SPEAR3XX_PLGPIO_INT_BASE		(SPEAR3XX_GPIO_INT_BASE + 8)
 #define SPEAR3XX_GPIO_INT_END			(SPEAR3XX_PLGPIO_INT_BASE + \
 							SPEAR3XX_PLGPIO_COUNT)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index 3b6ea07..260794d 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -11,7 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifdef	CONFIG_MACH_SPEAR300
+#ifdef	CONFIG_MACH_SPEAR300_DT
 
 #ifndef __MACH_SPEAR300_H
 #define __MACH_SPEAR300_H
@@ -51,4 +51,4 @@
 
 #endif /* __MACH_SPEAR300_H */
 
-#endif /* CONFIG_MACH_SPEAR300 */
+#endif /* CONFIG_MACH_SPEAR300_DT */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 1567d0da..bc9c06d 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -11,7 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifdef	CONFIG_MACH_SPEAR310
+#ifdef	CONFIG_MACH_SPEAR310_DT
 
 #ifndef __MACH_SPEAR310_H
 #define __MACH_SPEAR310_H
@@ -55,4 +55,4 @@
 
 #endif /* __MACH_SPEAR310_H */
 
-#endif /* CONFIG_MACH_SPEAR310 */
+#endif /* CONFIG_MACH_SPEAR310_DT */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 8cfa83f..e6ac0da 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -11,7 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifdef	CONFIG_MACH_SPEAR320
+#ifdef	CONFIG_MACH_SPEAR320_DT
 
 #ifndef __MACH_SPEAR320_H
 #define __MACH_SPEAR320_H
@@ -64,4 +64,4 @@
 
 #endif /* __MACH_SPEAR320_H */
 
-#endif /* CONFIG_MACH_SPEAR320 */
+#endif /* CONFIG_MACH_SPEAR300_DT */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index adee72b..4d0f6c7 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,8 +3,8 @@
  *
  * SPEAr300 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,6 +13,10 @@
 
 #define pr_fmt(fmt) "SPEAr300: " fmt
 
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <linux/types.h>
 #include <linux/amba/pl061.h>
 #include <linux/ptrace.h>
@@ -425,24 +429,38 @@ static struct spear_shirq shirq_ras1 = {
 	},
 };
 
-/* Add spear300 specific devices here */
-/* arm gpio1 device registration */
-static struct pl061_platform_data gpio1_plat_data = {
+static struct pl061_platform_data pl061_plat_data = {
 	.gpio_base	= 8,
 	.irq_base	= SPEAR300_GPIO1_INT_BASE,
 };
 
-AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
-	{SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl061", SPEAR300_GPIO_BASE, NULL, &pl061_plat_data),
+	{}
+};
+
+/* padmux devices to enable */
+static struct pmx_dev *spear300_evb_pmx_devs[] = {
+	/* spear3xx specific devices */
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp_cs,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_mii,
+	&spear3xx_pmx_uart0,
+
+	/* spear300 specific devices */
+	&spear300_pmx_fsmc_2_chips,
+	&spear300_pmx_clcd,
+	&spear300_pmx_telecom_sdhci_4bit,
+	&spear300_pmx_gpio1,
+};
 
 /* spear300 routines */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count)
+int __init spear300_init(void)
 {
 	int ret = 0;
 
-	/* call spear3xx family common init function */
-	spear3xx_init();
 
 	/* shared irq registration */
 	shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
@@ -452,10 +470,15 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 			pr_err("Error registering Shared IRQ\n");
 	}
 
-	/* pmx initialization */
-	pmx_driver.mode = pmx_mode;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = pmx_dev_count;
+	if (of_machine_is_compatible("st,spear300-evb")) {
+		/* pmx initialization */
+		pmx_driver.mode = &spear300_photo_frame_mode;
+		pmx_driver.devs = spear300_evb_pmx_devs;
+		pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
+	} else {
+		pr_err("Invalid board\n");
+		return -EINVAL;
+	}
 
 	pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
 	if (pmx_driver.base) {
@@ -466,4 +489,6 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 		/* Free Mapping, device selection already done */
 		iounmap(pmx_driver.base);
 	}
+
+	return 0;
 }
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9..0000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear300_evb.c
- *
- * SPEAr300 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-	/* spear3xx specific devices */
-	&spear3xx_pmx_i2c,
-	&spear3xx_pmx_ssp_cs,
-	&spear3xx_pmx_ssp,
-	&spear3xx_pmx_mii,
-	&spear3xx_pmx_uart0,
-
-	/* spear300 specific devices */
-	&spear300_pmx_fsmc_2_chips,
-	&spear300_pmx_clcd,
-	&spear300_pmx_telecom_sdhci_4bit,
-	&spear300_pmx_gpio1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	/* spear3xx specific devices */
-	&spear3xx_gpio_device,
-	&spear3xx_uart_device,
-
-	/* spear300 specific devices */
-	&spear300_gpio1_device,
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-	/* spear3xx specific devices */
-
-	/* spear300 specific devices */
-};
-
-static void __init spear300_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear300 machine init function */
-	spear300_init(&spear300_photo_frame_mode, pmx_devs,
-			ARRAY_SIZE(pmx_devs));
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear3xx_map_io,
-	.init_irq	=	spear3xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear3xx_timer,
-	.init_machine	=	spear300_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index b7c2876..90156bf 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,8 +3,8 @@
  *
  * SPEAr310 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,6 +13,11 @@
 
 #define pr_fmt(fmt) "SPEAr310: " fmt
 
+#include <linux/amba/serial.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <linux/ptrace.h>
 #include <asm/irq.h>
 #include <plat/shirq.h>
@@ -257,17 +262,71 @@ static struct spear_shirq shirq_intrcomm_ras = {
 	},
 };
 
-/* Add spear310 specific devices here */
+/* uart devices plat data */
+static struct amba_pl011_data uart_data[] = {
+	{
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart1_tx",
+		.dma_rx_param = "uart1_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart2_tx",
+		.dma_rx_param = "uart2_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart3_tx",
+		.dma_rx_param = "uart3_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart4_tx",
+		.dma_rx_param = "uart4_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart5_tx",
+		.dma_rx_param = "uart5_rx",
+	},
+};
+
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, &uart_data[0]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL, &uart_data[1]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL, &uart_data[2]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL, &uart_data[3]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL, &uart_data[4]),
+	{}
+};
+
+/* padmux devices to enable */
+static struct pmx_dev *spear310_evb_pmx_devs[] = {
+	/* spear3xx specific devices */
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_gpio_pin0,
+	&spear3xx_pmx_gpio_pin1,
+	&spear3xx_pmx_gpio_pin2,
+	&spear3xx_pmx_gpio_pin3,
+	&spear3xx_pmx_gpio_pin4,
+	&spear3xx_pmx_gpio_pin5,
+	&spear3xx_pmx_uart0,
+
+	/* spear310 specific devices */
+	&spear310_pmx_emi_cs_0_1_4_5,
+	&spear310_pmx_emi_cs_2_3,
+	&spear310_pmx_uart1,
+	&spear310_pmx_uart2,
+	&spear310_pmx_uart3_4_5,
+	&spear310_pmx_fsmc,
+	&spear310_pmx_rs485_0_1,
+	&spear310_pmx_tdm0,
+};
 
 /* spear310 routines */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count)
+int __init spear310_init(void)
 {
 	void __iomem *base;
 	int ret = 0;
 
-	/* call spear3xx family common init function */
-	spear3xx_init();
 
 	/* shared irq registration */
 	base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -297,13 +356,20 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 			pr_err("Error registering Shared IRQ 4\n");
 	}
 
-	/* pmx initialization */
-	pmx_driver.base = base;
-	pmx_driver.mode = pmx_mode;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = pmx_dev_count;
+	if (of_machine_is_compatible("st,spear310-evb")) {
+		/* pmx initialization */
+		pmx_driver.base = base;
+		pmx_driver.mode = NULL;
+		pmx_driver.devs = spear310_evb_pmx_devs;
+		pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs);
+	} else {
+		pr_err("Invalid board\n");
+		return -EINVAL;
+	}
 
 	ret = pmx_register(&pmx_driver);
 	if (ret)
 		pr_err("padmux: registration failed. err no: %d\n", ret);
+
+	return 0;
 }
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c499..0000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear310_evb.c
- *
- * SPEAr310 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-	/* spear3xx specific devices */
-	&spear3xx_pmx_i2c,
-	&spear3xx_pmx_ssp,
-	&spear3xx_pmx_gpio_pin0,
-	&spear3xx_pmx_gpio_pin1,
-	&spear3xx_pmx_gpio_pin2,
-	&spear3xx_pmx_gpio_pin3,
-	&spear3xx_pmx_gpio_pin4,
-	&spear3xx_pmx_gpio_pin5,
-	&spear3xx_pmx_uart0,
-
-	/* spear310 specific devices */
-	&spear310_pmx_emi_cs_0_1_4_5,
-	&spear310_pmx_emi_cs_2_3,
-	&spear310_pmx_uart1,
-	&spear310_pmx_uart2,
-	&spear310_pmx_uart3_4_5,
-	&spear310_pmx_fsmc,
-	&spear310_pmx_rs485_0_1,
-	&spear310_pmx_tdm0,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	/* spear3xx specific devices */
-	&spear3xx_gpio_device,
-	&spear3xx_uart_device,
-
-	/* spear310 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-	/* spear3xx specific devices */
-
-	/* spear310 specific devices */
-};
-
-static void __init spear310_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear310 machine init function */
-	spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear3xx_map_io,
-	.init_irq	=	spear3xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear3xx_timer,
-	.init_machine	=	spear310_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 7bd39c0..582d1af 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,8 +3,8 @@
  *
  * SPEAr320 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,6 +13,12 @@
 
 #define pr_fmt(fmt) "SPEAr320: " fmt
 
+#include <linux/amba/pl022.h>
+#include <linux/amba/serial.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <linux/ptrace.h>
 #include <asm/irq.h>
 #include <plat/shirq.h>
@@ -510,17 +516,72 @@ static struct spear_shirq shirq_intrcomm_ras = {
 	},
 };
 
-/* Add spear320 specific devices here */
+static struct pl022_ssp_controller ssp_data[] = {
+	{
+		.bus_id = 1,
+		.enable_dma = 1,
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "ssp1_tx",
+		.dma_rx_param = "ssp1_rx",
+		.num_chipselect = 2,
+	}, {
+		.bus_id = 2,
+		.enable_dma = 1,
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "ssp2_tx",
+		.dma_rx_param = "ssp2_rx",
+		.num_chipselect = 2,
+	}
+};
+
+static struct amba_pl011_data uart_data[] = {
+	{
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart1_tx",
+		.dma_rx_param = "uart1_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart2_tx",
+		.dma_rx_param = "uart2_rx",
+	},
+};
+
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL, &ssp_data[0]),
+	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL, &ssp_data[1]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL, &uart_data[0]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL, &uart_data[1]),
+	{}
+};
+
+/* padmux devices to enable */
+static struct pmx_dev *spear320_evb_pmx_devs[] = {
+	/* spear3xx specific devices */
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_mii,
+	&spear3xx_pmx_uart0,
+
+	/* spear320 specific devices */
+	&spear320_pmx_fsmc,
+	&spear320_pmx_sdhci,
+	&spear320_pmx_i2s,
+	&spear320_pmx_uart1,
+	&spear320_pmx_uart2,
+	&spear320_pmx_can,
+	&spear320_pmx_pwm0,
+	&spear320_pmx_pwm1,
+	&spear320_pmx_pwm2,
+	&spear320_pmx_mii1,
+};
 
 /* spear320 routines */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count)
+int __init spear320_init(void)
 {
 	void __iomem *base;
 	int ret = 0;
 
-	/* call spear3xx family common init function */
-	spear3xx_init();
 
 	/* shared irq registration */
 	base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -544,13 +605,20 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 			pr_err("Error registering Shared IRQ 4\n");
 	}
 
-	/* pmx initialization */
-	pmx_driver.base = base;
-	pmx_driver.mode = pmx_mode;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = pmx_dev_count;
+	if (of_machine_is_compatible("st,spear320-evb")) {
+		/* pmx initialization */
+		pmx_driver.base = base;
+		pmx_driver.mode = &spear320_auto_net_mii_mode;
+		pmx_driver.devs = spear320_evb_pmx_devs;
+		pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
+	} else {
+		pr_err("Invalid board\n");
+		return -EINVAL;
+	}
 
 	ret = pmx_register(&pmx_driver);
 	if (ret)
 		pr_err("padmux: registration failed. err no: %d\n", ret);
+
+	return 0;
 }
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334a..0000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear320_evb.c
- *
- * SPEAr320 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-	/* spear3xx specific devices */
-	&spear3xx_pmx_i2c,
-	&spear3xx_pmx_ssp,
-	&spear3xx_pmx_mii,
-	&spear3xx_pmx_uart0,
-
-	/* spear320 specific devices */
-	&spear320_pmx_fsmc,
-	&spear320_pmx_sdhci,
-	&spear320_pmx_i2s,
-	&spear320_pmx_uart1,
-	&spear320_pmx_uart2,
-	&spear320_pmx_can,
-	&spear320_pmx_pwm0,
-	&spear320_pmx_pwm1,
-	&spear320_pmx_pwm2,
-	&spear320_pmx_mii1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	/* spear3xx specific devices */
-	&spear3xx_gpio_device,
-	&spear3xx_uart_device,
-
-	/* spear320 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-	/* spear3xx specific devices */
-
-	/* spear320 specific devices */
-};
-
-static void __init spear320_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear320 machine init function */
-	spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
-			ARRAY_SIZE(pmx_devs));
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear3xx_map_io,
-	.init_irq	=	spear3xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear3xx_timer,
-	.init_machine	=	spear320_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index a236925..a2bfb86 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,8 +3,8 @@
  *
  * SPEAr3XX machines common source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,8 +13,13 @@
 
 #define pr_fmt(fmt) "SPEAr3xx: " fmt
 
-#include <linux/types.h>
+#include <linux/amba/pl022.h>
 #include <linux/amba/pl061.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/types.h>
 #include <linux/ptrace.h>
 #include <linux/io.h>
 #include <asm/hardware/vic.h>
@@ -23,30 +28,73 @@
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
-/* Add spear3xx machines common devices here */
+/* ssp device registration */
+static struct pl022_ssp_controller pl022_plat_data = {
+	.bus_id = 0,
+	.enable_dma = 1,
+	.dma_filter = pl08x_filter_id,
+	.dma_tx_param = "ssp0_tx",
+	.dma_rx_param = "ssp0_rx",
+	/*
+	 * This is number of spi devices that can be connected to spi. There are
+	 * two type of chipselects on which slave devices can work. One is chip
+	 * select provided by spi masters other is controlled through external
+	 * gpio's. We can't use chipselect provided from spi master (because as
+	 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+	 * this number now depends on number of gpios available for spi. each
+	 * slave on each master requires a separate gpio pin.
+	 */
+	.num_chipselect = 2,
+};
+
 /* gpio device registration */
-static struct pl061_platform_data gpio_plat_data = {
+static struct pl061_platform_data pl061_plat_data = {
 	.gpio_base	= 0,
 	.irq_base	= SPEAR3XX_GPIO_INT_BASE,
 };
 
-AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
-	{SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
 
-/* uart device registration */
-AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
-	{SPEAR3XX_IRQ_UART}, NULL);
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear3xx_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+			&pl022_plat_data),
+	OF_DEV_AUXDATA("arm,pl061", SPEAR3XX_ICM3_GPIO_BASE, NULL,
+			&pl061_plat_data),
+	{}
+};
 
-/* Do spear3xx familiy common initialization part here */
-void __init spear3xx_init(void)
+static void __init spear3xx_dt_init(void)
 {
-	/* nothing to do for now */
-}
+	int ret = -EINVAL;
+
+	of_platform_populate(NULL, of_default_bus_match_table,
+			spear3xx_auxdata_lookup, NULL);
+
+	if (of_machine_is_compatible("st,spear300")) {
+#ifdef CONFIG_MACH_SPEAR300_DT
+		of_platform_populate(NULL, of_default_bus_match_table,
+				spear300_auxdata_lookup, NULL);
+
+		ret = spear300_init();
+#endif
+	} else if (of_machine_is_compatible("st,spear310")) {
+#ifdef CONFIG_MACH_SPEAR310_DT
+		of_platform_populate(NULL, of_default_bus_match_table,
+				spear300_auxdata_lookup, NULL);
+
+		ret = spear310_init();
+#endif
+	} else if (of_machine_is_compatible("st,spear320")) {
+#ifdef CONFIG_MACH_SPEAR300_DT
+		of_platform_populate(NULL, of_default_bus_match_table,
+				spear300_auxdata_lookup, NULL);
+
+		ret = spear320_init();
+#endif
+	}
 
-/* This will initialize vic */
-void __init spear3xx_init_irq(void)
-{
-	vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
+	if (ret)
+		pr_err("Initialization Failed");
 }
 
 /* Following will create static virtual/physical mappings */
@@ -295,7 +343,7 @@ struct pmx_dev spear3xx_pmx_timer_1_2 = {
 	.enb_on_reset = 0,
 };
 
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR310_DT) || defined(CONFIG_MACH_SPEAR320_DT)
 /* plgpios devices */
 static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
 	{
@@ -506,7 +554,7 @@ struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
 	.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
 	.enb_on_reset = 1,
 };
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
+#endif /* CONFIG_MACH_SPEAR310_DT || CONFIG_MACH_SPEAR320_DT */
 
 static void __init spear3xx_timer_init(void)
 {
@@ -538,3 +586,23 @@ static void __init spear3xx_timer_init(void)
 struct sys_timer spear3xx_timer = {
 	.init = spear3xx_timer_init,
 };
+
+static const char * const spear3xx_dt_board_compat[] = {
+	"st,spear300",
+	"st,spear310",
+	"st,spear320",
+	"st,spear300-evb",
+	"st,spear310-evb",
+	"st,spear320-evb",
+	NULL
+};
+
+DT_MACHINE_START(SPEAR3XX_DT, "ST SPEAr3xx (Flattened Device Tree)")
+	.map_io		=	spear3xx_map_io,
+	.init_irq	=	vic_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear3xx_timer,
+	.init_machine	=	spear3xx_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear3xx_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbc..a6ff4c8 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -8,10 +8,11 @@ choice
 	prompt "ST SPEAr Family"
 	default ARCH_SPEAR3XX
 
-config ARCH_SPEAR3XX
-	bool "SPEAr3XX"
+config ARCH_SPEAR3XX_DT
+	bool "ST SPEAr3xx with Device Tree"
 	select ARM_VIC
 	select CPU_ARM926T
+	select USE_OF
 	help
 	  Supports for ARM's SPEAR3XX family
 
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b..4b906bb 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -5,4 +5,4 @@
 # Common support
 obj-y	:= clock.o restart.o time.o
 
-obj-$(CONFIG_ARCH_SPEAR3XX)	+= shirq.o padmux.o
+obj-$(CONFIG_ARCH_SPEAR3XX_DT)	+= shirq.o padmux.o
-- 
1.7.10.rc2.10.gb47606



From baruch at tkos.co.il  Mon Mar 26 08:10:23 2012
From: baruch at tkos.co.il (Baruch Siach)
Date: Mon, 26 Mar 2012 14:10:23 +0200
Subject: [PATCH 3/3] i.MX27: visstrim_m10: Remove use of MX2_CAMERA_SWAP16.
In-Reply-To: <1332760804-22743-4-git-send-email-javier.martin@vista-silicon.com>
References: <1332760804-22743-1-git-send-email-javier.martin@vista-silicon.com>
 <1332760804-22743-4-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20120326121023.GD18420@sapphire.tkos.co.il>

Hi Javier,

On Mon, Mar 26, 2012 at 01:20:04PM +0200, Javier Martin wrote:
> 
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> ---
>  arch/arm/mach-imx/mach-imx27_visstrim_m10.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> index 3128cfe..4db00c6 100644
> --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
> @@ -164,7 +164,7 @@ static struct platform_device visstrim_tvp5150 = {
>  
>  
>  static struct mx2_camera_platform_data visstrim_camera = {
> -	.flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | MX2_CAMERA_SWAP16 | MX2_CAMERA_PCLK_SAMPLE_RISING,
> +	.flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | MX2_CAMERA_PCLK_SAMPLE_RISING,
>  	.clk = 100000,
>  };

The order of the last two patches in this series should be switched to 
preserve bisectability.

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From myungjoo.ham at samsung.com  Mon Mar 26 08:20:47 2012
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Mon, 26 Mar 2012 21:20:47 +0900
Subject: [PATCH v4 1/2] mfd: add irq domain support for max8997 interrupts
In-Reply-To: <1332582590-16382-2-git-send-email-thomas.abraham@linaro.org>
References: <1332582590-16382-1-git-send-email-thomas.abraham@linaro.org>
 <1332582590-16382-2-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CAJ0PZbSw3LcgkCw0-_VvmM2ijJOU0gKk_EEnwhoY4r7J8rU3_Q@mail.gmail.com>

On Sat, Mar 24, 2012 at 6:49 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:
> Add irq domain support for max8997 interrupts. The reverse mapping method
> used is linear mapping since the sub-drivers of max8997 such as regulator
> and charger drivers can use the max8997 irq_domain to get the linux irq
> number for max8997 interrupts. All uses of irq_base in platform data and
> max8997 driver private data are removed.
>
> Cc: MyungJoo Ham <myungjoo.ham at samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> Acked-by: Grant Likely <grant.likely at secretlab.ca>

Acked-by: MyungJoo Ham <myungjoo.ham at samsung.com>

> ---
> ?arch/arm/mach-exynos/mach-nuri.c ? ?| ? ?4 --
> ?arch/arm/mach-exynos/mach-origen.c ?| ? ?1 -
> ?drivers/mfd/max8997-irq.c ? ? ? ? ? | ? 61 ++++++++++++++++++++--------------
> ?drivers/mfd/max8997.c ? ? ? ? ? ? ? | ? ?1 -
> ?include/linux/mfd/max8997-private.h | ? ?4 ++-
> ?include/linux/mfd/max8997.h ? ? ? ? | ? ?1 -
> ?6 files changed, 39 insertions(+), 33 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
> index 7ac81ce..b21d85d 100644
> --- a/arch/arm/mach-exynos/mach-nuri.c
> +++ b/arch/arm/mach-exynos/mach-nuri.c
> @@ -1077,12 +1077,8 @@ static struct platform_device nuri_max8903_device = {
> ?static void __init nuri_power_init(void)
> ?{
> ? ? ? ?int gpio;
> - ? ? ? int irq_base = IRQ_GPIO_END + 1;
> ? ? ? ?int ta_en = 0;
>
> - ? ? ? nuri_max8997_pdata.irq_base = irq_base;
> - ? ? ? irq_base += MAX8997_IRQ_NR;
> -
> ? ? ? ?gpio = EXYNOS4_GPX0(7);
> ? ? ? ?gpio_request(gpio, "AP_PMIC_IRQ");
> ? ? ? ?s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
> diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
> index 827cb99..d3b2e9d 100644
> --- a/arch/arm/mach-exynos/mach-origen.c
> +++ b/arch/arm/mach-exynos/mach-origen.c
> @@ -424,7 +424,6 @@ static struct max8997_platform_data __initdata origen_max8997_pdata = {
> ? ? ? ?.buck1_gpiodvs ?= false,
> ? ? ? ?.buck2_gpiodvs ?= false,
> ? ? ? ?.buck5_gpiodvs ?= false,
> - ? ? ? .irq_base ? ? ? = IRQ_GPIO_END + 1,
>
> ? ? ? ?.ignore_gpiodvs_side_effect = true,
> ? ? ? ?.buck125_default_idx = 0x0,
> diff --git a/drivers/mfd/max8997-irq.c b/drivers/mfd/max8997-irq.c
> index 09274cf..00390a1 100644
> --- a/drivers/mfd/max8997-irq.c
> +++ b/drivers/mfd/max8997-irq.c
> @@ -142,7 +142,8 @@ static void max8997_irq_sync_unlock(struct irq_data *data)
> ?static const inline struct max8997_irq_data *
> ?irq_to_max8997_irq(struct max8997_dev *max8997, int irq)
> ?{
> - ? ? ? return &max8997_irqs[irq - max8997->irq_base];
> + ? ? ? struct irq_data *data = irq_get_irq_data(irq);
> + ? ? ? return &max8997_irqs[data->hwirq];
> ?}
>
> ?static void max8997_irq_mask(struct irq_data *data)
> @@ -182,7 +183,7 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
> ? ? ? ?u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
> ? ? ? ?u8 irq_src;
> ? ? ? ?int ret;
> - ? ? ? int i;
> + ? ? ? int i, cur_irq;
>
> ? ? ? ?ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
> ? ? ? ?if (ret < 0) {
> @@ -269,8 +270,11 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
>
> ? ? ? ?/* Report */
> ? ? ? ?for (i = 0; i < MAX8997_IRQ_NR; i++) {
> - ? ? ? ? ? ? ? if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask)
> - ? ? ? ? ? ? ? ? ? ? ? handle_nested_irq(max8997->irq_base + i);
> + ? ? ? ? ? ? ? if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
> + ? ? ? ? ? ? ? ? ? ? ? cur_irq = irq_find_mapping(max8997->irq_domain, i);
> + ? ? ? ? ? ? ? ? ? ? ? if (cur_irq)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? handle_nested_irq(cur_irq);
> + ? ? ? ? ? ? ? }
> ? ? ? ?}
>
> ? ? ? ?return IRQ_HANDLED;
> @@ -278,26 +282,40 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
>
> ?int max8997_irq_resume(struct max8997_dev *max8997)
> ?{
> - ? ? ? if (max8997->irq && max8997->irq_base)
> - ? ? ? ? ? ? ? max8997_irq_thread(max8997->irq_base, max8997);
> + ? ? ? if (max8997->irq && max8997->irq_domain)
> + ? ? ? ? ? ? ? max8997_irq_thread(0, max8997);
> + ? ? ? return 0;
> +}
> +
> +static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? irq_hw_number_t hw)
> +{
> + ? ? ? struct max8997_dev *max8997 = d->host_data;
> +
> + ? ? ? irq_set_chip_data(irq, max8997);
> + ? ? ? irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
> + ? ? ? irq_set_nested_thread(irq, 1);
> +#ifdef CONFIG_ARM
> + ? ? ? set_irq_flags(irq, IRQF_VALID);
> +#else
> + ? ? ? irq_set_noprobe(irq);
> +#endif
> ? ? ? ?return 0;
> ?}
>
> +static struct irq_domain_ops max8997_irq_domain_ops = {
> + ? ? ? .map = max8997_irq_domain_map,
> +};
> +
> ?int max8997_irq_init(struct max8997_dev *max8997)
> ?{
> + ? ? ? struct irq_domain *domain;
> ? ? ? ?int i;
> - ? ? ? int cur_irq;
> ? ? ? ?int ret;
> ? ? ? ?u8 val;
>
> ? ? ? ?if (!max8997->irq) {
> ? ? ? ? ? ? ? ?dev_warn(max8997->dev, "No interrupt specified.\n");
> - ? ? ? ? ? ? ? max8997->irq_base = 0;
> - ? ? ? ? ? ? ? return 0;
> - ? ? ? }
> -
> - ? ? ? if (!max8997->irq_base) {
> - ? ? ? ? ? ? ? dev_err(max8997->dev, "No interrupt base specified.\n");
> ? ? ? ? ? ? ? ?return 0;
> ? ? ? ?}
>
> @@ -327,18 +345,11 @@ int max8997_irq_init(struct max8997_dev *max8997)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?true : false;
> ? ? ? ?}
>
> - ? ? ? /* Register with genirq */
> - ? ? ? for (i = 0; i < MAX8997_IRQ_NR; i++) {
> - ? ? ? ? ? ? ? cur_irq = i + max8997->irq_base;
> - ? ? ? ? ? ? ? irq_set_chip_data(cur_irq, max8997);
> - ? ? ? ? ? ? ? irq_set_chip_and_handler(cur_irq, &max8997_irq_chip,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? handle_edge_irq);
> - ? ? ? ? ? ? ? irq_set_nested_thread(cur_irq, 1);
> -#ifdef CONFIG_ARM
> - ? ? ? ? ? ? ? set_irq_flags(cur_irq, IRQF_VALID);
> -#else
> - ? ? ? ? ? ? ? irq_set_noprobe(cur_irq);
> -#endif
> + ? ? ? domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &max8997_irq_domain_ops, &max8997);
> + ? ? ? if (!domain) {
> + ? ? ? ? ? ? ? dev_err(max8997->dev, "could not create irq domain\n");
> + ? ? ? ? ? ? ? return -ENODEV;
> ? ? ? ?}
>
> ? ? ? ?ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
> diff --git a/drivers/mfd/max8997.c b/drivers/mfd/max8997.c
> index cb83a7a..20ecad3 100644
> --- a/drivers/mfd/max8997.c
> +++ b/drivers/mfd/max8997.c
> @@ -143,7 +143,6 @@ static int max8997_i2c_probe(struct i2c_client *i2c,
> ? ? ? ?if (!pdata)
> ? ? ? ? ? ? ? ?goto err;
>
> - ? ? ? max8997->irq_base = pdata->irq_base;
> ? ? ? ?max8997->ono = pdata->ono;
>
> ? ? ? ?mutex_init(&max8997->iolock);
> diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
> index 3f4deb6..830152c 100644
> --- a/include/linux/mfd/max8997-private.h
> +++ b/include/linux/mfd/max8997-private.h
> @@ -23,6 +23,8 @@
> ?#define __LINUX_MFD_MAX8997_PRIV_H
>
> ?#include <linux/i2c.h>
> +#include <linux/export.h>
> +#include <linux/irqdomain.h>
>
> ?#define MAX8997_REG_INVALID ? ?(0xff)
>
> @@ -325,7 +327,7 @@ struct max8997_dev {
>
> ? ? ? ?int irq;
> ? ? ? ?int ono;
> - ? ? ? int irq_base;
> + ? ? ? struct irq_domain *irq_domain;
> ? ? ? ?struct mutex irqlock;
> ? ? ? ?int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
> ? ? ? ?int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
> diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
> index fff5905..818486c 100644
> --- a/include/linux/mfd/max8997.h
> +++ b/include/linux/mfd/max8997.h
> @@ -155,7 +155,6 @@ struct max8997_led_platform_data {
>
> ?struct max8997_platform_data {
> ? ? ? ?/* IRQ */
> - ? ? ? int irq_base;
> ? ? ? ?int ono;
> ? ? ? ?int wakeup;
>
> --
> 1.6.6.rc2
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html



-- 
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab, DMC Business, Samsung Electronics


From will.deacon at arm.com  Mon Mar 26 08:43:59 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 26 Mar 2012 13:43:59 +0100
Subject: [PATCH] ARM: ptrace: fix ptrace_read_user for !CONFIG_MMU
 platforms
In-Reply-To: <20120229185237.GO2983@mudshark.cambridge.arm.com>
References: <201202210124.23028.paul@codesourcery.com>
 <20120221083612.GG22562@n2100.arm.linux.org.uk>
 <20120221100041.GA19696@mudshark.cambridge.arm.com>
 <20120221101052.GH22562@n2100.arm.linux.org.uk>
 <20120221105250.GC19696@mudshark.cambridge.arm.com>
 <20120221113548.GK22562@n2100.arm.linux.org.uk>
 <20120221132216.GJ19696@mudshark.cambridge.arm.com>
 <20120224143655.GH13504@mudshark.cambridge.arm.com>
 <20120224181621.GH22562@n2100.arm.linux.org.uk>
 <20120229185237.GO2983@mudshark.cambridge.arm.com>
Message-ID: <20120326124359.GD2475@mudshark.cambridge.arm.com>

On Wed, Feb 29, 2012 at 06:52:37PM +0000, Will Deacon wrote:
> On Fri, Feb 24, 2012 at 06:16:21PM +0000, Russell King - ARM Linux wrote:
> > On Fri, Feb 24, 2012 at 02:36:55PM +0000, Will Deacon wrote:
> > > It seems as though my ptrace patch makes *no difference* because these
> > > tools don't even use the PT_ADDR_TEXT etc magic offsets! As a result,
> > > trying to set a breakpoint by symbol fails miserably because it tries to
> > > poke the symbol offset directly, without adding on the base address of the
> > > text.
> > > 
> > > Are there any tools available that use these magic numbers or are mine just
> > > too old? Given that the whole thing dies after a while with:
> > > 
> > > [  909.062821] [430] gdbserver: obsolete system call 02b37558.
> > > 
> > > I'm not entirely convinced by the stability of what I'm using (that syscall
> > > number looks like an address to me).
> > 
> > That suggests that this stuff definitely hasn't been tested, and there's
> > no users of it (if there were I'm sure someone - either gdb folk or
> > some kernel people) would've seen a bug report.
> 
> My glancing at the latest GDB sources does suggest that this stuff ought to
> be getting used, so I should probably try building a nommu configuration
> from a more recent codebase. It seems that you're right that nobody is using
> this stuff though.

Ok, I have an update on this now. I had to hack GDB as well as the kernel
(!) since it wasn't picking up our PT_* definitions from asm/ptrace.h. With
that change in place, GDB can be persuaded to add on the offsets correctly
and, with a fixed kernel, breakpoints and symbol resolution start to work.

So now the question is: do I fix GDB or the kernel first? I can imagine the
GDB guys not wanting to merge anything until the kernel has a working ptrace
interface in this regard.

Will


From m.szyprowski at samsung.com  Mon Mar 26 08:55:34 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 26 Mar 2012 14:55:34 +0200
Subject: [PATCH v12 3/3] iommu/exynos: Add iommu driver for Exynos
 Platforms
In-Reply-To: <000301cd0286$2f4310d0$8dc93270$%cho@samsung.com>
References: <000301cd0286$2f4310d0$8dc93270$%cho@samsung.com>
Message-ID: <001401cd0b4f$bbf0e120$33d2a360$%szyprowski@samsung.com>

Hello,

I'm sorry for a delay, I was quite busy recently, but I have finally found some
time to review the code.

On Thursday, March 15, 2012 9:33 AM Cho KyongHo wrote:

> This is the System MMU driver and IOMMU API implementation for
> Exynos SOC platforms. Exynos platforms has more than 10 System
> MMUs dedicated for each multimedia accelerators.
> 
> The System MMU driver is already in arc/arm/plat-s5p but it is
> moved to drivers/iommu due to Ohad Ben-Cohen gathered IOMMU drivers
> there
> 
> Any device driver in Exynos platforms that needs to control its
> System MMU must call platform_set_sysmmu() to inform System MMU
> driver who will control it.
> platform_set_sysmmu() is defined in <mach/sysmmu.h>
> 
> Cc: Joerg Roedel <joerg.roedel at amd.com>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>


(snipped)

> diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
> new file mode 100644
> index 0000000..b8daf7c
> --- /dev/null
> +++ b/drivers/iommu/exynos-iommu.c
> @@ -0,0 +1,1057 @@
> +/* linux/drivers/iommu/exynos_iommu.c
> + *
> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */

(snipped)

> +static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
> +{
> +	/* SYSMMU is in blocked when interrupt occurred. */
> +	struct sysmmu_drvdata *data = dev_id;
> +	struct resource *irqres;
> +	struct platform_device *pdev;
> +	enum exynos_sysmmu_inttype itype;
> +	unsigned long addr = -1;
> +
> +	int i, ret = -ENOSYS;
> +
> +	read_lock(&data->lock);
> +
> +	WARN_ON(!is_sysmmu_active(data));
> +
> +	pdev = to_platform_device(data->sysmmu);
> +	for (i = 0; i < pdev->num_resources; i++) {
> +		irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
> +		if (irqres && ((int)irqres->start == irq))
> +			break;
> +	}
> +
> +	if (i == pdev->num_resources) {
> +		itype = SYSMMU_FAULT_UNKNOWN;
> +	} else {
> +		i /= 2;
> +
> +		itype = (enum exynos_sysmmu_inttype)
> +			__ffs(__raw_readl(data->sfrbases[i] + REG_INT_STATUS));
> +		if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
> +			itype = SYSMMU_FAULT_UNKNOWN;
> +		else
> +			addr = __raw_readl(
> +				data->sfrbases[i] + fault_reg_offset[itype]);
> +	}
> +
> +	if (data->domain)
> +		ret = report_iommu_fault(data->domain, data->dev,
> +				addr, itype);
> +
> +	if ((ret == -ENOSYS) && data->fault_handler) {
> +		unsigned long base = data->pgtable;
> +		if (itype != SYSMMU_FAULT_UNKNOWN)
> +			base = __raw_readl(
> +					data->sfrbases[i] + REG_PT_BASE_ADDR);
> +		ret = data->fault_handler(itype, base, addr);
> +	}
> +
> +	if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
> +		__raw_writel(1 << itype, data->sfrbases[i] + REG_INT_CLEAR);
> +	else
> +		dev_dbg(data->sysmmu, "(%s) %s is not handled.\n",
> +				data->dbgname, sysmmu_fault_name[itype]);
> +
> +	if (itype != SYSMMU_FAULT_UNKNOWN)
> +		sysmmu_unblock(data->sfrbases[i]);
> +
> +	read_unlock(&data->lock);
> +
> +	return IRQ_HANDLED;
> +}

(snipped)

> +static int exynos_sysmmu_probe(struct platform_device *pdev)
> +{
> +	int i, ret;
> +	struct device *dev;
> +	struct sysmmu_drvdata *data;
> +
> +	dev = &pdev->dev;
> +
> +	data = kzalloc(sizeof(*data), GFP_KERNEL);
> +	if (!data) {
> +		dev_dbg(dev, "Not enough memory\n");
> +		ret = -ENOMEM;
> +		goto err_alloc;
> +	}
> +
> +	ret = dev_set_drvdata(dev, data);
> +	if (ret) {
> +		dev_dbg(dev, "Unabled to initialize driver data\n");
> +		goto err_init;
> +	}
> +
> +	data->nsfrs = pdev->num_resources / 2;
> +	data->sfrbases = kmalloc(sizeof(*data->sfrbases) * data->nsfrs,
> +								GFP_KERNEL);
> +	if (data->sfrbases == NULL) {
> +		dev_dbg(dev, "Not enough memory\n");
> +		ret = -ENOMEM;
> +		goto err_init;
> +	}
> +
> +	for (i = 0; i < data->nsfrs; i++) {
> +		struct resource *res;
> +		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
> +		if (!res) {
> +			dev_dbg(dev, "Unable to find IOMEM region\n");
> +			ret = -ENOENT;
> +			goto err_res;
> +		}
> +
> +		data->sfrbases[i] = ioremap(res->start, resource_size(res));
> +		if (!data->sfrbases[i]) {
> +			dev_dbg(dev, "Unable to map IOMEM @ PA:%#x\n",
> +							res->start);
> +			ret = -ENOENT;
> +			goto err_res;
> +		}
> +	}
> +
> +	for (i = 0; i < data->nsfrs; i++) {
> +		ret = platform_get_irq(pdev, i);
> +		if (ret <= 0) {
> +			dev_dbg(dev, "Unable to find IRQ resource\n");
> +			goto err_irq;
> +		}
> +
> +		ret = request_irq(ret, exynos_sysmmu_irq, 0,
> +					dev_name(dev), data);
> +		if (ret) {
> +			dev_dbg(dev, "Unabled to register interrupt handler\n");
> +			goto err_irq;
> +		}
> +	}

Please look at those loops and the interrupt function above. Those for-loops over 
all the resources looks really ugly and makes the driver less portable. The previous 
version (v8 afair) had much cleaned design.

It would be better not to squash multiple sysmmu controllers into a single instance
of the driver. Please keep the driver simple. Sysmmu driver's resource should consist
only of one io register area and one irq, nothing more. Such approach will remove 
the need for all that custom data in platform_data and it also make the future 
integration much easier for other non-samsung platforms (the sysmmu hardware is also
used by other hw vendors). Support for device tree is also easier to add if the device
driver is kept simple (supporting only one instance of the hardware block).

The only reason I can see, which might have suggested you to squash hardware sysmmu 
controllers into one single instance was to provide the same virtual io mappings
for all these sub-devices (it is mainly used by fims-isp complex block). 

This can be achieved in a much clearer design by using one, common iommu domain 
and attaching all these separate iommu controllers to it. Of course this will also
require having a separate platform devices for each sub-device, but sooner or later
you will need them anyway. The good example here is the MFC module, which already
have separate devices: mfc_l and mfc_r for each memory controller.

> +	if (dev_get_platdata(dev)) {
> +		char *deli, *beg;
> +		struct sysmmu_platform_data *platdata = dev_get_platdata(dev);
> +
> +		beg = platdata->clockname;
> +
> +		for (deli = beg; (*deli != '\0') && (*deli != ','); deli++)
> +			/* NOTHING */;
> +
> +		if (*deli == '\0')
> +			deli = NULL;
> +		else
> +			*deli = '\0';
> +
> +		data->clk[0] = clk_get(dev, beg);
> +		if (IS_ERR(data->clk[0])) {
> +			data->clk[0] = NULL;
> +			dev_dbg(dev, "No clock descriptor registered\n");
> +		}
> +
> +		if (data->clk[0] && deli) {
> +			*deli = ',';
> +			data->clk[1] = clk_get(dev, deli + 1);
> +			if (IS_ERR(data->clk[1]))
> +				data->clk[1] = NULL;
> +		}
> +
> +		data->dbgname = platdata->dbgname;
> +	}

Passing clocks via platform data is also considered as a bad idea, especially if 
you need to parse string to extract the clock names. It would be much cleaner to
have 2 (or more if required) variants of sysmmu driver, each one for a different
version of the sysmmu hardware (I noticed only that some of the sysmmu units 
require one clock, the other require 2 clocks).

> +
> +	data->sysmmu = dev;
> +	rwlock_init(&data->lock);
> +	INIT_LIST_HEAD(&data->node);
> +
> +	__set_fault_handler(data, &default_fault_handler);
> +
> +	if (dev->parent)
> +		pm_runtime_enable(dev);
> +
> +	dev_dbg(dev, "(%s) Initialized\n", data->dbgname);
> +	return 0;
> +err_irq:
> +	while (i-- > 0) {
> +		int irq;
> +
> +		irq = platform_get_irq(pdev, i);
> +		free_irq(irq, data);
> +	}
> +err_res:
> +	while (data->nsfrs-- > 0)
> +		iounmap(data->sfrbases[data->nsfrs]);
> +	kfree(data->sfrbases);
> +err_init:
> +	kfree(data);
> +err_alloc:
> +	dev_err(dev, "Failed to initialize\n");
> +	return ret;
> +}
> +
> +static struct platform_driver exynos_sysmmu_driver = {
> +	.probe		= exynos_sysmmu_probe,
> +	.driver		= {
> +		.owner		= THIS_MODULE,
> +		.name		= "exynos-sysmmu",
> +	}
> +};
> +

(snipped)

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From javier.martin at vista-silicon.com  Mon Mar 26 08:56:19 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Mon, 26 Mar 2012 14:56:19 +0200
Subject: [PATCH 3/3] i.MX27: visstrim_m10: Remove use of MX2_CAMERA_SWAP16.
In-Reply-To: <20120326121023.GD18420@sapphire.tkos.co.il>
References: <1332760804-22743-1-git-send-email-javier.martin@vista-silicon.com>
 <1332760804-22743-4-git-send-email-javier.martin@vista-silicon.com>
 <20120326121023.GD18420@sapphire.tkos.co.il>
Message-ID: <CACKLOr0abquyZ2bZMnq8pXTL8BXqzN_izK92hdA=gPJ6dBsTdA@mail.gmail.com>

On 26 March 2012 14:10, Baruch Siach <baruch at tkos.co.il> wrote:
> Hi Javier,
>
> On Mon, Mar 26, 2012 at 01:20:04PM +0200, Javier Martin wrote:
>>
>> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
>> ---
>> ?arch/arm/mach-imx/mach-imx27_visstrim_m10.c | ? ?2 +-
>> ?1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
>> index 3128cfe..4db00c6 100644
>> --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
>> +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
>> @@ -164,7 +164,7 @@ static struct platform_device visstrim_tvp5150 = {
>>
>>
>> ?static struct mx2_camera_platform_data visstrim_camera = {
>> - ? ? .flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | MX2_CAMERA_SWAP16 | MX2_CAMERA_PCLK_SAMPLE_RISING,
>> + ? ? .flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | MX2_CAMERA_PCLK_SAMPLE_RISING,
>> ? ? ? .clk = 100000,
>> ?};
>
> The order of the last two patches in this series should be switched to
> preserve bisectability.
>
> baruch

You are right.
Thanks.

-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From nicolas.ferre at atmel.com  Mon Mar 26 09:08:10 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 26 Mar 2012 15:08:10 +0200
Subject: [GIT PULL] AT91 drivers Kconfig cleanup
Message-ID: <4F706A3A.1070309@atmel.com>

(previous email without mailing-lists addresses)

Arnd, Olof,

This is a series which deals with AT91 drivers Kconfig entries. Its goal is
to remove too restrictive dependencies on SoC names.
This will allow to add support for newer SoC seamlessly.
Some very "cosmetic" changes are also added (entry names, comments, etc.).

Some patches are dealing with other subsystem Kconfig files. I have
collected
"Acked-by" and included them in this series.

I have built this pull-request on top of arm-soc/next/dt2 branch for
easy merge with
at91 material that is already queued for 3.4. It is for sure a very late
pull request
for 3.4, event though it is non intrusive. So, feel free to delay it to
3.5 or
a "staging" branch...

The following changes since commit 7d1206bc2859c6e9f46e35ae697c138e7d7858a7:

  Merge branch 'kirkwood/dt' into next/dt2 (2012-03-24 19:16:04 +0000)

are available in the git repository at:


  git://github.com/at91linux/linux-at91.git armsoc-next-dt2+at91-kconfig

for you to fetch changes up to 40ef130751f4438ae73603ab00aa2a2590a3201d:

  hwrng: Kconfig: remove dependency for atmel-rng driver (2012-03-26
14:06:23 +0200)

----------------------------------------------------------------
Nicolas Ferre (12):
      ARM: at91: change AT91 Kconfig entry comment
      ARM: at91/Kconfig: change at91sam9g45 entry
      ARM: at91/Kconfig: add comment to at91sam9x5 family entry
      ARM: at91/Kconfig: add clarifications to AT91SAM9M10G45-EK entry
      ARM: at91/Kconfig: add AT91SAM9x5 family to AT91_EARLY_DBGU0 entry
      ARM: at91/Kconfig: website link for AT91SAM9G20-EK
      dmaengine: Kconfig: fix Atmel at_hdmac entry
      mmc: Kconfig: remove choice between at91_mci and atmel-mci
      mmc: atmel-mci: remove the need for CONFIG_MMC_ATMELMCI_DMA
      rtc: Kconfig: remove dependency for AT91 rtc driver
      Input: Kconfig: remove dependency for atmel_tsadcc driver
      hwrng: Kconfig: remove dependency for atmel-rng driver

 arch/arm/Kconfig                  |    4 ++--
 arch/arm/mach-at91/Kconfig        |   21 ++++++++++++++++-----
 drivers/char/hw_random/Kconfig    |    2 +-
 drivers/dma/Kconfig               |    5 ++---
 drivers/input/touchscreen/Kconfig |    4 ++--
 drivers/mmc/host/Kconfig          |   23 ++---------------------
 drivers/mmc/host/atmel-mci.c      |    2 --
 drivers/rtc/Kconfig               |    2 +-
 8 files changed, 26 insertions(+), 37 deletions(-)

Thanks, best regards,
-- 
Nicolas Ferre


From jonsmirl at gmail.com  Mon Mar 26 09:11:45 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Mon, 26 Mar 2012 09:11:45 -0400
Subject: ioremap to a specific virtual address
In-Reply-To: <201203260847.38176.arnd@arndb.de>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <CAKON4OwhcFDMC4dWjU7x4u2CPT7C2BxVuCDkTN0j14gTndi3tA@mail.gmail.com>
 <201203251734.41780.arnd@arndb.de>
 <201203260847.38176.arnd@arndb.de>
Message-ID: <CAKON4OyPpTNHoWbYQ+jOHEF+c9Rz983wMjArsqkMnUKnYe_V0w@mail.gmail.com>

On Mon, Mar 26, 2012 at 4:47 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Sunday 25 March 2012, Arnd Bergmann wrote:
>> ? ? ? ? ? ? ? ? ? ? ? ? /* mpmc configuration */
>> ? ? ? ? ? ? ? ? ? ? ? ? mpmc-static-config ? ? = <0x81>;
>> ? ? ? ? ? ? ? ? ? ? ? ? mpmc-static-wait-wen ? = <1>;
>> ? ? ? ? ? ? ? ? ? ? ? ? mpmc-static-wait-oen ? = <1>;
>> ? ? ? ? ? ? ? ? ? ? ? ? mpmc-static-wait-rd ? ?= <4>;
>> ? ? ? ? ? ? ? ? ? ? ? ? mpmc-static-wait-page ?= <1>;
>> ? ? ? ? ? ? ? ? ? ? ? ? mpmc-static-wait-write = <1>;
>> ? ? ? ? ? ? ? ? ? ? ? ? mpmc-static-wait-turn ?= <2>;
>
> On second though, I guess you can turn these into a single
> property named "mpmc-timings" or such and then just copy
> them to the registers.
>
> I also wonder whether the timings are actually correct for your
> dm9000 device. Maybe the additional gpio read in there was
> just an indication that someone worked around incorrect timings?

Maybe the GPIO read is bogus? Looks like they needed a 70ns delay and
the GPIO read was a way of getting that.

How do MPNC delays work? Shouldn't the CPU enforce this delay in hardware?

/* ARM MPMC contoller as part of low power design doesn't de-assert
nCS and nOE for consecutive reads but just changes address. But DM9000
requires nCS and nOE change between address. So access other chip
select area (nCS0) to force de-assertion of nCS1 and nOE1. Or else
wait for long time such as 80 usecs.
LPC313x has external logic outside of MPMC IP to toggle nOE to split
consecutive reads.

The latest Apex bootloader patch makes use of this feature. For this
to work SYS_MPMC_WTD_DEL0 & SYS_MPMC_WTD_DEL1 should be programmed
with MPMC_STWTRD0 & MPMC_STWTRD1 values. The logic only deactivates
the nOE for one clock cycle which is 11nsec but DM9000 needs 80nsec
between nOEs. So lets add some dummy instructions such as reading a
GPIO register to compensate for extra 70nsec.
*/

WTD_DEL1
This following register is used for the static device0 of the MPMC. It
provides that the output enable signal for the static device0 (OE) is
split up into two equal portions, with one inactive cycle in the
middle. This is needed because some memories do no detect consecutive
reads within one OE period

MPMCStaticExtendedWait is set to 4 which should be a 2us delay.



-- 
Jon Smirl
jonsmirl at gmail.com


From andreas.westin at stericsson.com  Mon Mar 26 09:12:43 2012
From: andreas.westin at stericsson.com (Andreas Westin)
Date: Mon, 26 Mar 2012 15:12:43 +0200
Subject: [PATCH] mach-ux500: Crypto: core support for CRYP/HASH module
Message-ID: <1332767564-23577-1-git-send-email-andreas.westin@stericsson.com>

Hi,

This is the core code required for supporting the UX500 CRYP and HASH
hardware crypto and hash module in the ST-Ericsson UX500 platform.

/Andreas

Andreas Westin (1):
  mach-ux500: Crypto: core support for CRYP/HASH module.

 arch/arm/mach-ux500/board-mop500.c         |   48 ++++++++++++++++++++++++++++
 arch/arm/mach-ux500/board-u5500.c          |   48 ++++++++++++++++++++++++++++
 arch/arm/mach-ux500/clock.c                |   18 ++++++-----
 arch/arm/mach-ux500/devices-common.c       |   16 ++++++++++
 arch/arm/mach-ux500/devices-common.h       |   23 +++++++++++++
 arch/arm/mach-ux500/devices-db5500.h       |    4 +++
 arch/arm/mach-ux500/devices-db8500.h       |    4 +++
 arch/arm/mach-ux500/include/mach/devices.h |    3 ++
 arch/arm/mach-ux500/ste-dma40-db5500.h     |    9 ++++--
 9 files changed, 162 insertions(+), 11 deletions(-)

-- 
1.7.9.4



From andreas.westin at stericsson.com  Mon Mar 26 09:12:44 2012
From: andreas.westin at stericsson.com (Andreas Westin)
Date: Mon, 26 Mar 2012 15:12:44 +0200
Subject: [PATCH] mach-ux500: Crypto: core support for CRYP/HASH module.
In-Reply-To: <1332767564-23577-1-git-send-email-andreas.westin@stericsson.com>
References: <1332767564-23577-1-git-send-email-andreas.westin@stericsson.com>
Message-ID: <1332767564-23577-2-git-send-email-andreas.westin@stericsson.com>

This adds the required platform data and calls to enable
the CRYP/HASH driver.

Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Andreas Westin <andreas.westin at stericsson.com>
---
 arch/arm/mach-ux500/board-mop500.c         |   48 ++++++++++++++++++++++++++++
 arch/arm/mach-ux500/board-u5500.c          |   48 ++++++++++++++++++++++++++++
 arch/arm/mach-ux500/clock.c                |   18 ++++++-----
 arch/arm/mach-ux500/devices-common.c       |   16 ++++++++++
 arch/arm/mach-ux500/devices-common.h       |   23 +++++++++++++
 arch/arm/mach-ux500/devices-db5500.h       |    4 +++
 arch/arm/mach-ux500/devices-db8500.h       |    4 +++
 arch/arm/mach-ux500/include/mach/devices.h |    3 ++
 arch/arm/mach-ux500/ste-dma40-db5500.h     |    9 ++++--
 9 files changed, 162 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 5c00712..4e9bcd6 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -44,6 +44,7 @@
 #include <mach/setup.h>
 #include <mach/devices.h>
 #include <mach/irqs.h>
+#include <mach/crypto-ux500.h>
 
 #include "pins-db8500.h"
 #include "ste-dma40-db8500.h"
@@ -409,6 +410,45 @@ static void mop500_prox_deactivate(struct device *dev)
 	regulator_put(prox_regulator);
 }
 
+static struct cryp_platform_data u8500_cryp1_platform_data = {
+		.mem_to_engine = {
+				.dir = STEDMA40_MEM_TO_PERIPH,
+				.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+				.dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,
+				.src_info.data_width = STEDMA40_WORD_WIDTH,
+				.dst_info.data_width = STEDMA40_WORD_WIDTH,
+				.mode = STEDMA40_MODE_LOGICAL,
+				.src_info.psize = STEDMA40_PSIZE_LOG_4,
+				.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+		},
+		.engine_to_mem = {
+				.dir = STEDMA40_PERIPH_TO_MEM,
+				.src_dev_type = DB8500_DMA_DEV48_CAC1_RX,
+				.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+				.src_info.data_width = STEDMA40_WORD_WIDTH,
+				.dst_info.data_width = STEDMA40_WORD_WIDTH,
+				.mode = STEDMA40_MODE_LOGICAL,
+				.src_info.psize = STEDMA40_PSIZE_LOG_4,
+				.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+		}
+};
+
+static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
+		.dir = STEDMA40_MEM_TO_PERIPH,
+		.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+		.dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,
+		.src_info.data_width = STEDMA40_WORD_WIDTH,
+		.dst_info.data_width = STEDMA40_WORD_WIDTH,
+		.mode = STEDMA40_MODE_LOGICAL,
+		.src_info.psize = STEDMA40_PSIZE_LOG_16,
+		.dst_info.psize = STEDMA40_PSIZE_LOG_16,
+};
+
+static struct hash_platform_data u8500_hash1_platform_data = {
+		.mem_to_engine = &u8500_hash_dma_cfg_tx,
+		.dma_filter = stedma40_filter,
+};
+
 /* add any platform devices here - TODO */
 static struct platform_device *mop500_platform_devs[] __initdata = {
 	&mop500_gpio_keys_device,
@@ -594,6 +634,12 @@ static void __init mop500_uart_init(void)
 	db8500_add_uart2(&uart2_plat);
 }
 
+static void __init u8500_cryp1_hash1_init(void)
+{
+	db8500_add_cryp1(&u8500_cryp1_platform_data);
+	db8500_add_hash1(&u8500_hash1_platform_data);
+}
+
 static struct platform_device *snowball_platform_devs[] __initdata = {
 	&snowball_led_dev,
 	&snowball_key_dev,
@@ -611,6 +657,8 @@ static void __init mop500_init_machine(void)
 
 	mop500_pins_init();
 
+	u8500_cryp1_hash1_init();
+
 	platform_add_devices(mop500_platform_devs,
 			ARRAY_SIZE(mop500_platform_devs));
 
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 9de9e9c..865aaf8 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -23,9 +23,11 @@
 #include <mach/hardware.h>
 #include <mach/devices.h>
 #include <mach/setup.h>
+#include <mach/crypto-ux500.h>
 
 #include "pins-db5500.h"
 #include "devices-db5500.h"
+#include "ste-dma40-db5500.h"
 #include <linux/led-lm3530.h>
 
 /*
@@ -89,6 +91,45 @@ static struct lm3530_platform_data u5500_als_platform_data = {
 	.brt_val = 0x7F,	/* Max brightness */
 };
 
+static struct cryp_platform_data u5500_cryp1_platform_data = {
+		.mem_to_engine = {
+				.dir = STEDMA40_MEM_TO_PERIPH,
+				.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+				.dst_dev_type = DB5500_DMA_DEV48_CRYPTO1_TX,
+				.src_info.data_width = STEDMA40_WORD_WIDTH,
+				.dst_info.data_width = STEDMA40_WORD_WIDTH,
+				.mode = STEDMA40_MODE_LOGICAL,
+				.src_info.psize = STEDMA40_PSIZE_LOG_4,
+				.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+		},
+		.engine_to_mem = {
+				.dir = STEDMA40_PERIPH_TO_MEM,
+				.src_dev_type = DB5500_DMA_DEV48_CRYPTO1_RX,
+				.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+				.src_info.data_width = STEDMA40_WORD_WIDTH,
+				.dst_info.data_width = STEDMA40_WORD_WIDTH,
+				.mode = STEDMA40_MODE_LOGICAL,
+				.src_info.psize = STEDMA40_PSIZE_LOG_4,
+				.dst_info.psize = STEDMA40_PSIZE_LOG_4,
+		}
+};
+
+static struct stedma40_chan_cfg u5500_hash_dma_cfg_tx = {
+		.dir = STEDMA40_MEM_TO_PERIPH,
+		.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+		.dst_dev_type = DB5500_DMA_DEV50_HASH1_TX,
+		.src_info.data_width = STEDMA40_WORD_WIDTH,
+		.dst_info.data_width = STEDMA40_WORD_WIDTH,
+		.mode = STEDMA40_MODE_LOGICAL,
+		.src_info.psize = STEDMA40_PSIZE_LOG_16,
+		.dst_info.psize = STEDMA40_PSIZE_LOG_16,
+};
+
+static struct hash_platform_data u5500_hash1_platform_data = {
+		.mem_to_engine = &u5500_hash_dma_cfg_tx,
+		.dma_filter = stedma40_filter,
+};
+
 static struct i2c_board_info __initdata u5500_i2c2_devices[] = {
 	{
 		/* Backlight */
@@ -103,6 +144,12 @@ static void __init u5500_i2c_init(void)
 	i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices));
 }
 
+static void __init u5500_cryp1_hash1_init(void)
+{
+	db5500_add_cryp1(&u5500_cryp1_platform_data);
+	db5500_add_hash1(&u5500_hash1_platform_data);
+}
+
 static struct ab5500_platform_data ab5500_plf_data = {
 	.irq = {
 		.base = 0,
@@ -140,6 +187,7 @@ static void __init u5500_init_machine(void)
 	u5500_i2c_init();
 	u5500_sdi_init();
 	u5500_uart_init();
+	u5500_cryp1_hash1_init();
 
 	platform_add_devices(u5500_platform_devices,
 		ARRAY_SIZE(u5500_platform_devices));
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 7379075..0b4e40c 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -375,14 +375,15 @@ static DEFINE_PRCC_CLK(5, usb,		0,  0, NULL);
 /* Peripheral Cluster #6 */
 
 /* MTU ID in data */
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1);
-static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0);
-static DEFINE_PRCC_CLK(6, cfgreg,	6,  6, NULL);
-static DEFINE_PRCC_CLK(6, hash1,	5, -1, NULL);
-static DEFINE_PRCC_CLK(6, unipro,	4,  1, &clk_uniproclk);
-static DEFINE_PRCC_CLK(6, pka,		3, -1, NULL);
-static DEFINE_PRCC_CLK(6, hash0,	2, -1, NULL);
-static DEFINE_PRCC_CLK(6, cryp0,	1, -1, NULL);
+static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
+static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
+static DEFINE_PRCC_CLK(6, cfgreg,	7,  7, NULL);
+static DEFINE_PRCC_CLK(6, hash1,	6, -1, NULL);
+static DEFINE_PRCC_CLK(6, unipro,	5,  1, &clk_uniproclk);
+static DEFINE_PRCC_CLK(6, pka,		4, -1, NULL);
+static DEFINE_PRCC_CLK(6, hash0,	3, -1, NULL);
+static DEFINE_PRCC_CLK(6, cryp0,	2, -1, NULL);
+static DEFINE_PRCC_CLK(6, cryp1,    1, -1, NULL);
 static DEFINE_PRCC_CLK(6, rng,	0,  0, &clk_rngclk);
 
 static struct clk clk_dummy_apb_pclk = {
@@ -424,6 +425,7 @@ static struct clk_lookup u8500_clks[] = {
 	CLK(pka,	"pka",		NULL),
 	CLK(hash0,	"hash0",	NULL),
 	CLK(cryp0,	"cryp0",	NULL),
+	CLK(cryp1,  "cryp1",    NULL),
 
 	/* PRCMU level clock gating */
 
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index c563e54..e2dbb4e 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -108,6 +108,22 @@ dbx500_add_platform_device_4k1irq(const char *name, int id,
 					  ARRAY_SIZE(resources));
 }
 
+struct platform_device *
+dbx500_add_platform_device_noirq(const char *name, int id,
+		resource_size_t base, void *pdata)
+{
+	struct resource resources[] = {
+			[0] = {
+					.start  = base,
+					.end    = base + SZ_4K - 1,
+					.flags  = IORESOURCE_MEM,
+			}
+	};
+
+	return dbx500_add_platform_device(name, id, pdata, resources,
+			ARRAY_SIZE(resources));
+}
+
 static struct platform_device *
 dbx500_add_gpio(int id, resource_size_t addr, int irq,
 		struct nmk_gpio_platform_data *pdata)
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index 7825705..d4fea76 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -17,6 +17,10 @@ dbx500_add_platform_device_4k1irq(const char *name, int id,
 				  resource_size_t base,
 				  int irq, void *pdata);
 
+extern struct platform_device *
+dbx500_add_platform_device_noirq(const char *name, int id,
+		resource_size_t base, void *pdata);
+
 struct spi_master_cntlr;
 
 static inline struct amba_device *
@@ -79,6 +83,25 @@ dbx500_add_rtc(resource_size_t base, int irq)
 	return dbx500_add_amba_device("rtc-pl031", base, irq, NULL, 0);
 }
 
+struct cryp_platform_data;
+
+static inline struct platform_device *
+dbx500_add_cryp1(int id, resource_size_t base, int irq,
+		struct cryp_platform_data *pdata)
+{
+	return dbx500_add_platform_device_4k1irq("cryp1", id, base, irq,
+			pdata);
+}
+
+struct hash_platform_data;
+
+static inline struct platform_device *
+dbx500_add_hash1(int id, resource_size_t base,
+		struct hash_platform_data *pdata)
+{
+	return dbx500_add_platform_device_noirq("hash1", id, base, pdata);
+}
+
 struct nmk_gpio_platform_data;
 
 void dbx500_add_gpios(resource_size_t *base, int num, int irq,
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
index 0c4bccd..d40ce40 100644
--- a/arch/arm/mach-ux500/devices-db5500.h
+++ b/arch/arm/mach-ux500/devices-db5500.h
@@ -76,4 +76,8 @@
 #define db5500_add_uart3(plat) \
 	dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3, plat)
 
+#define db5500_add_cryp1(pdata) \
+	dbx500_add_cryp1(-1, U5500_CRYP1_BASE, IRQ_DB5500_CRYP1, pdata)
+#define db5500_add_hash1(pdata) \
+	dbx500_add_hash1(-1, U5500_HASH1_BASE, pdata)
 #endif
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index cbd4a9a..8fa045c 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -98,4 +98,8 @@ db8500_add_ssp(const char *name, resource_size_t base, int irq,
 #define db8500_add_uart2(pdata) \
 	dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2, pdata)
 
+#define db8500_add_cryp1(pdata) \
+	dbx500_add_cryp1(-1, U8500_CRYP1_BASE, IRQ_DB8500_CRYP1, pdata)
+#define db8500_add_hash1(pdata) \
+	dbx500_add_hash1(-1, U8500_HASH1_BASE, pdata)
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index 5f6cb71..a55454a 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -15,6 +15,9 @@ extern struct platform_device u8500_gpio_devs[];
 
 extern struct amba_device ux500_pl031_device;
 
+extern struct platform_device ux500_hash1_device;
+extern struct platform_device ux500_cryp1_device;
+
 extern struct platform_device u8500_dma40_device;
 extern struct platform_device ux500_ske_keypad_device;
 
diff --git a/arch/arm/mach-ux500/ste-dma40-db5500.h b/arch/arm/mach-ux500/ste-dma40-db5500.h
index cb2110c..c35f454 100644
--- a/arch/arm/mach-ux500/ste-dma40-db5500.h
+++ b/arch/arm/mach-ux500/ste-dma40-db5500.h
@@ -42,7 +42,10 @@ enum dma_src_dev_type {
 	DB5500_DMA_DEV26_SDMMC2_RX = 26,
 	DB5500_DMA_DEV27_SDMMC3_RX = 27,
 	DB5500_DMA_DEV28_SDMMC4_RX = 28,
-	/* 29 - 32 not used */
+	/* 29 not used */
+	DB5500_DMA_DEV30_HASH1_TX = 30, /* v2 */
+	DB5500_DMA_DEV31_CRYPTO1_RX = 31, /* v2 */
+	/* 32 not used */
 	DB5500_DMA_DEV33_SDMMC0_RX = 33,
 	DB5500_DMA_DEV34_SDMMC1_RX = 34,
 	DB5500_DMA_DEV35_SDMMC2_RX = 35,
@@ -56,10 +59,10 @@ enum dma_src_dev_type {
 	DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43,
 	DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44,
 	DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45,
-	/* 46 not used */
+	DB5500_DMA_DEV46_CRYPTO1_RX = 46, /* v2 */
 	DB5500_DMA_DEV47_MCDE_RX = 47,
 	DB5500_DMA_DEV48_CRYPTO1_RX = 48,
-	/* 49, 50 not used */
+	/* 49 - 50 not used */
 	DB5500_DMA_DEV49_I2C1_RX = 51,
 	DB5500_DMA_DEV50_I2C3_RX = 52,
 	DB5500_DMA_DEV51_I2C2_RX = 53,
-- 
1.7.9.4



From javier.martin at vista-silicon.com  Mon Mar 26 09:17:45 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon, 26 Mar 2012 15:17:45 +0200
Subject: [PATCH v2 0/3] media: tvp5150: Fix mbus format to UYUV instead of
 YUYV.
Message-ID: <1332767868-2531-1-git-send-email-javier.martin@vista-silicon.com>

Changes since v2:
- Swap order of patches 3 and 4 to make the series bisectable.

[PATCH v2 1/3] media: tvp5150: Fix mbus format.
[PATCH v2 2/3] i.MX27: visstrim_m10: Remove use of MX2_CAMERA_SWAP16.
[PATCH v2 3/3] media: mx2_camera: Fix mbus format handling.


From javier.martin at vista-silicon.com  Mon Mar 26 09:17:48 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon, 26 Mar 2012 15:17:48 +0200
Subject: [PATCH v2 3/3] media: mx2_camera: Fix mbus format handling.
In-Reply-To: <1332767868-2531-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332767868-2531-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332767868-2531-4-git-send-email-javier.martin@vista-silicon.com>

Remove MX2_CAMERA_SWAP16 and MX2_CAMERA_PACK_DIR_MSB flags
so that the driver can negotiate with the attached sensor
whether the mbus format needs convertion from UYUV to YUYV
or not.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/plat-mxc/include/mach/mx2_cam.h |    2 -
 drivers/media/video/mx2_camera.c         |   52 +++++++++++++++++++++++++++---
 2 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h
index 3c080a3..7ded6f1 100644
--- a/arch/arm/plat-mxc/include/mach/mx2_cam.h
+++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h
@@ -23,7 +23,6 @@
 #ifndef __MACH_MX2_CAM_H_
 #define __MACH_MX2_CAM_H_
 
-#define MX2_CAMERA_SWAP16		(1 << 0)
 #define MX2_CAMERA_EXT_VSYNC		(1 << 1)
 #define MX2_CAMERA_CCIR			(1 << 2)
 #define MX2_CAMERA_CCIR_INTERLACE	(1 << 3)
@@ -31,7 +30,6 @@
 #define MX2_CAMERA_GATED_CLOCK		(1 << 5)
 #define MX2_CAMERA_INV_DATA		(1 << 6)
 #define MX2_CAMERA_PCLK_SAMPLE_RISING	(1 << 7)
-#define MX2_CAMERA_PACK_DIR_MSB		(1 << 8)
 
 /**
  * struct mx2_camera_platform_data - optional platform data for mx2_camera
diff --git a/drivers/media/video/mx2_camera.c b/drivers/media/video/mx2_camera.c
index 8df624f..9274a53 100644
--- a/drivers/media/video/mx2_camera.c
+++ b/drivers/media/video/mx2_camera.c
@@ -348,6 +348,19 @@ static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
 					PRP_INTR_CH2OVF,
 		}
 	},
+	{
+		.in_fmt		= V4L2_MBUS_FMT_UYVY8_2X8,
+		.out_fmt	= V4L2_PIX_FMT_YUV420,
+		.cfg		= {
+			.channel	= 2,
+			.in_fmt		= PRP_CNTL_DATA_IN_YUV422,
+			.out_fmt	= PRP_CNTL_CH2_OUT_YUV420,
+			.src_pixel	= 0x22000888, /* YUV422 (YUYV) */
+			.irq_flags	= PRP_INTR_RDERR | PRP_INTR_CH2WERR |
+					PRP_INTR_CH2FC | PRP_INTR_LBOVF |
+					PRP_INTR_CH2OVF,
+		}
+	},
 };
 
 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
@@ -990,6 +1003,7 @@ static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
 	struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
 	struct mx2_camera_dev *pcdev = ici->priv;
 	struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
+	const struct soc_camera_format_xlate *xlate;
 	unsigned long common_flags;
 	int ret;
 	int bytesperline;
@@ -1034,14 +1048,31 @@ static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
 		return ret;
 	}
 
+	xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
+	if (!xlate) {
+		dev_warn(icd->parent, "Format %x not found\n", pixfmt);
+		return -EINVAL;
+	}
+
+	if (xlate->code == V4L2_MBUS_FMT_YUYV8_2X8) {
+		csicr1 |= CSICR1_PACK_DIR;
+		csicr1 &= ~CSICR1_SWAP16_EN;
+		dev_dbg(icd->parent, "already yuyv format, don't convert\n");
+	} else if (xlate->code == V4L2_MBUS_FMT_UYVY8_2X8) {
+		csicr1 &= ~CSICR1_PACK_DIR;
+		csicr1 |= CSICR1_SWAP16_EN;
+		dev_dbg(icd->parent, "convert uyvy mbus format into yuyv\n");
+	} else {
+		dev_warn(icd->parent, "mbus format not supported\n");
+		return -EINVAL;
+	}
+
 	if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
 		csicr1 |= CSICR1_REDGE;
 	if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
 		csicr1 |= CSICR1_SOF_POL;
 	if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
 		csicr1 |= CSICR1_HSYNC_POL;
-	if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
-		csicr1 |= CSICR1_SWAP16_EN;
 	if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
 		csicr1 |= CSICR1_EXT_VSYNC;
 	if (pcdev->platform_flags & MX2_CAMERA_CCIR)
@@ -1052,8 +1083,6 @@ static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
 		csicr1 |= CSICR1_GCLK_MODE;
 	if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
 		csicr1 |= CSICR1_INV_DATA;
-	if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
-		csicr1 |= CSICR1_PACK_DIR;
 
 	pcdev->csicr1 = csicr1;
 
@@ -1128,7 +1157,8 @@ static int mx2_camera_get_formats(struct soc_camera_device *icd,
 		return 0;
 	}
 
-	if (code == V4L2_MBUS_FMT_YUYV8_2X8) {
+	if (code == V4L2_MBUS_FMT_YUYV8_2X8 ||
+	    code == V4L2_MBUS_FMT_UYVY8_2X8) {
 		formats++;
 		if (xlate) {
 			/*
@@ -1144,6 +1174,18 @@ static int mx2_camera_get_formats(struct soc_camera_device *icd,
 		}
 	}
 
+	if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
+		formats++;
+		if (xlate) {
+			xlate->host_fmt =
+				soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8);
+			xlate->code	= code;
+			dev_dbg(dev, "Providing host format %s for sensor code %d\n",
+				xlate->host_fmt->name, code);
+			xlate++;
+		}
+	}
+
 	/* Generic pass-trough */
 	formats++;
 	if (xlate) {
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar 26 09:17:47 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon, 26 Mar 2012 15:17:47 +0200
Subject: [PATCH v2 2/3] i.MX27: visstrim_m10: Remove use of MX2_CAMERA_SWAP16.
In-Reply-To: <1332767868-2531-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332767868-2531-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332767868-2531-3-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 3128cfe..4db00c6 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -164,7 +164,7 @@ static struct platform_device visstrim_tvp5150 = {
 
 
 static struct mx2_camera_platform_data visstrim_camera = {
-	.flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | MX2_CAMERA_SWAP16 | MX2_CAMERA_PCLK_SAMPLE_RISING,
+	.flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | MX2_CAMERA_PCLK_SAMPLE_RISING,
 	.clk = 100000,
 };
 
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Mon Mar 26 09:17:46 2012
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Mon, 26 Mar 2012 15:17:46 +0200
Subject: [PATCH v2 1/3] media: tvp5150: Fix mbus format.
In-Reply-To: <1332767868-2531-1-git-send-email-javier.martin@vista-silicon.com>
References: <1332767868-2531-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <1332767868-2531-2-git-send-email-javier.martin@vista-silicon.com>

According to p.14 fig 3-3 of the datasheet (SLES098A)
this decoder transmits data in UYVY format.

Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 drivers/media/video/tvp5150.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/media/video/tvp5150.c b/drivers/media/video/tvp5150.c
index e292c46..30c88e0 100644
--- a/drivers/media/video/tvp5150.c
+++ b/drivers/media/video/tvp5150.c
@@ -821,7 +821,7 @@ static int tvp5150_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
 	if (index)
 		return -EINVAL;
 
-	*code = V4L2_MBUS_FMT_YUYV8_2X8;
+	*code = V4L2_MBUS_FMT_UYVY8_2X8;
 	return 0;
 }
 
@@ -845,7 +845,7 @@ static int tvp5150_mbus_fmt(struct v4l2_subdev *sd,
 	f->width = decoder->rect.width;
 	f->height = decoder->rect.height;
 
-	f->code = V4L2_MBUS_FMT_YUYV8_2X8;
+	f->code = V4L2_MBUS_FMT_UYVY8_2X8;
 	f->field = V4L2_FIELD_SEQ_TB;
 	f->colorspace = V4L2_COLORSPACE_SMPTE170M;
 
-- 
1.7.0.4



From jonathan at jonmasters.org  Mon Mar 26 09:07:44 2012
From: jonathan at jonmasters.org (Jon Masters)
Date: Mon, 26 Mar 2012 09:07:44 -0400
Subject: Inconsistent kallsyms data on ARM.
In-Reply-To: <20120326073704.GH5611@n2100.arm.linux.org.uk>
References: <CAP=VYLoStscdVJretZ-Rkbp7V3Vsm8N0oWcjih7ruHFiDN7CiA@mail.gmail.com>
 <201203141321.47010.arnd@arndb.de>
 <20120325112035.GE5611@n2100.arm.linux.org.uk>
 <4F6FB170.1040109@jonmasters.org>
 <20120326073704.GH5611@n2100.arm.linux.org.uk>
Message-ID: <4F706A20.6020302@jonmasters.org>

On 03/26/2012 03:37 AM, Russell King - ARM Linux wrote:
> On Sun, Mar 25, 2012 at 07:59:44PM -0400, Jon Masters wrote:
>> As to longer term, I am happy to work up something that will spot this
>> particular kind of failure (symbol changes type) and output something
>> more useful during the kallsyms generation if you would like.
>>
>> Are you planning to pull in either of the fixes you mention?
> 
> I'm not, because those are all sub-optimal - I don't see why we should
> bloat the kernel image just for the sake of working around kallsyms.
> 
> The best I've come up with so far which avoids that is to force
> KALLSYMS_EXTRA_PASS to always be set on ARM.

Or just increasing the base number of kallsyms runs on ARM? That way,
you can have a real extra extra pass in the case of something else :)

Jon.



From mmarek at suse.cz  Mon Mar 26 09:48:42 2012
From: mmarek at suse.cz (Michal Marek)
Date: Mon, 26 Mar 2012 15:48:42 +0200
Subject: [PATCH] Kbuild: centralize MKIMAGE and cmd_uimage definitions
In-Reply-To: <4F6B7226.8000102@wwwdotorg.org>
References: <1331931835-12346-1-git-send-email-swarren@wwwdotorg.org>
 <4F6B7226.8000102@wwwdotorg.org>
Message-ID: <4F7073BA.6040403@suse.cz>

On 22.3.2012 19:40, Stephen Warren wrote:
> On 03/16/2012 03:03 PM, Stephen Warren wrote:
>> All ARCHs have the same definition of MKIMAGE. Move it to Makefile.lib
>> to avoid duplication.
>>
>> All ARCHs have similar definitions of cmd_uimage. Place a sufficiently
>> parameterized version in Makefile.lib to avoid duplication.
> 
> Michal,
> 
> Does this change look reasonable?

Absolutely.

> It has acks from people working on 4
> of the 7 affected architectures; would you prefer acks from all?

I will apply it now.

Michal


From thomas.abraham at linaro.org  Mon Mar 26 10:12:12 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Mon, 26 Mar 2012 19:42:12 +0530
Subject: [PATCH v4 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and
 EXYNOS5
In-Reply-To: <4F6B3256.40304@samsung.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
 <1331736138-28964-6-git-send-email-kgene.kim@samsung.com>
 <CAJuYYwTJsA1M1Qj2P1-1K=pWzi0BPo8YJNDSx4NqGC7NX0030g@mail.gmail.com>
 <074401cd074f$c2946b90$47bd42b0$%szyprowski@samsung.com>
 <4F6B3256.40304@samsung.com>
Message-ID: <CAJuYYwT5_EHPD4D+Qx0rX8bUVGLbLYUps2BYSUihLbuKGnhHdA@mail.gmail.com>

2012/3/22 Kukjin Kim <kgene.kim at samsung.com>:
> On 03/21/12 03:45, Marek Szyprowski wrote:
>>
>> Hello,
>>
>> On Wednesday, March 21, 2012 10:14 AM Thomas Abraham wrote:
>>
>>> On 14 March 2012 20:12, Kukjin Kim<kgene.kim at samsung.com> ?wrote:
>>>>
>>>> Actually, the base address of uart is different between EXYNOS4
>>>> and EXYNOS5 and this patch enables to support uart for EXYNOS4
>>>> and EXYNOS5 SoCs at runtime.
>>>>
>>>> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
>>>> ---
>>>
>>>
>>> [...]
>>>
>>>> diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S
>>>> b/arch/arm/mach-
>>>
>>> exynos/include/mach/debug-macro.S
>>>>
>>>> index 6cacf16..6c857ff 100644
>>>> --- a/arch/arm/mach-exynos/include/mach/debug-macro.S
>>>> +++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
>>>> @@ -21,8 +21,13 @@
>>>> ? ? ? ? */
>>>>
>>>> ? ? ? ?.macro addruart, rp, rv, tmp
>>>> - ? ? ? ? ? ? ? ldr ? ? \rp, = S3C_PA_UART
>>>> - ? ? ? ? ? ? ? ldr ? ? \rv, = S3C_VA_UART
>>>> + ? ? ? ? ? ? ? mov ? ? \rp, #0x10000000
>>>
>>>
>>> This is physical address of Exynos4/5 CPUID register which cannot be
>>> used here. And virtual address S5P_VA_CPUID also cannot be used here
>>> since this will be called before paging_init when earlyprintk boot
>>> param is used. So, with this change, earlyprintk does not work for
>>> both Exynos4 and Exynos5.
>>
>>
>> I confirm, printascii freeze the system on EXYNOS4 after that patch,
>> tested on Exynos4210 Nuri board.
>>
> Hi,
>
> I think, it can be solved with following and if no problems, it will be
> fixed during v3.4-rcX.
>
> diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S
> b/arch/arm/mach-exynos/in
> index 6c857ff..a865417 100644
> --- a/arch/arm/mach-exynos/include/mach/debug-macro.S
> +++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
> @@ -21,10 +21,10 @@
>
> ? ? ? ? */
>
> ? ? ? ?.macro addruart, rp, rv, tmp
> - ? ? ? ? ? ? ? mov ? ? \rp, #0x10000000
> - ? ? ? ? ? ? ? ldr ? ? \rp, [\rp, #0x0]
> - ? ? ? ? ? ? ? and ? ? \rp, \rp, #0xf00000
> - ? ? ? ? ? ? ? teq ? ? \rp, #0x500000 ? ? ? ? ?@@ EXYNOS5
> + ? ? ? ? ? ? ? mrc ? ? p15, 0, \tmp, c0, c0, 0
> + ? ? ? ? ? ? ? and ? ? \tmp, \tmp, #0xf0
> + ? ? ? ? ? ? ? teq ? ? \tmp, #0xf0 ? ? ? ? ? ? @@ A15
> +
> ? ? ? ? ? ? ? ?ldreq ? \rp, =EXYNOS5_PA_UART
>
> ? ? ? ? ? ? ? ?movne ? \rp, #EXYNOS4_PA_UART ? @@ EXYNOS4
> ? ? ? ? ? ? ? ?ldr ? ? \rv, =S3C_VA_UART
>

Dear Mr. Kim,

I have tested the above patch on Exynos5. Thanks.

Tested-by: Thomas Abraham <thomas.abraham at linaro.org>


From alexg at meprolight.com  Mon Mar 26 10:36:33 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Mon, 26 Mar 2012 16:36:33 +0200
Subject: [PATCH v1] regulator: i.MX35-PDK Add regulator support
Message-ID: <1332772593-13313-1-git-send-email-alexg@meprolight.com>

This patch register MC13892 PMIC which connected
via I2C bus and allow set the voltage domains
and constraints for each regulator.

Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
---
 arch/arm/mach-imx/mach-mx35_3ds.c |  200 +++++++++++++++++++++++++++++++++++++
 1 files changed, 200 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c..33ba6fe 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -29,6 +29,8 @@
 #include <linux/usb/otg.h>
 
 #include <linux/mtd/physmap.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -43,6 +45,7 @@
 
 #include "devices-imx35.h"
 
+#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
 #define EXPIO_PARENT_INT	gpio_to_irq(IMX_GPIO_NR(1, 1))
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -120,8 +123,204 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
 	/* I2C1 */
 	MX35_PAD_I2C1_CLK__I2C1_SCL,
 	MX35_PAD_I2C1_DAT__I2C1_SDA,
+	/*PMIC IRQ*/
+	MX35_PAD_GPIO2_0__GPIO2_0,
 };
 
+static struct regulator_init_data sw1_init = {
+	.constraints = {
+		.name = "SW1",
+		.min_uV = 600000,
+		.max_uV = 1375000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.valid_modes_mask = 0,
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data sw2_init = {
+	.constraints = {
+		.name = "SW2",
+		.min_uV = 900000,
+		.max_uV = 1850000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data sw3_init = {
+	.constraints = {
+		.name = "SW3",
+		.min_uV = 1100000,
+		.max_uV = 1850000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data sw4_init = {
+	.constraints = {
+		.name = "SW4",
+		.min_uV = 1100000,
+		.max_uV = 1850000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data viohi_init = {
+	.constraints = {
+		.name = "VIOHI",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vusb_init = {
+	.constraints = {
+		.name = "VUSB",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vdig_init = {
+	.constraints = {
+		.name = "VDIG",
+		.min_uV = 1050000,
+		.max_uV = 1800000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vpll_init = {
+	.constraints = {
+		.name = "VPLL",
+		.min_uV = 1050000,
+		.max_uV = 1800000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vusb2_init = {
+	.constraints = {
+		.name = "VUSB2",
+		.min_uV = 2400000,
+		.max_uV = 2775000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vvideo_init = {
+	.constraints = {
+		.name = "VVIDEO",
+		.min_uV = 2500000,
+		.max_uV = 2775000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1
+	}
+};
+
+static struct regulator_init_data vaudio_init = {
+	.constraints = {
+		.name = "VAUDIO",
+		.min_uV = 2300000,
+		.max_uV = 3000000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1
+	}
+};
+
+static struct regulator_init_data vcam_init = {
+	.constraints = {
+		.name = "VCAM",
+		.min_uV = 2500000,
+		.max_uV = 3000000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+					REGULATOR_CHANGE_MODE,
+		.valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
+		.boot_on = 1
+	},
+};
+
+static struct regulator_init_data vgen1_init = {
+	.constraints = {
+		.name = "VGEN1",
+		.min_uV = 1200000,
+		.max_uV = 3150000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	}
+};
+
+static struct regulator_init_data vgen2_init = {
+	.constraints = {
+		.name = "VGEN2",
+		.min_uV = 1200000,
+		.max_uV = 3150000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vgen3_init = {
+	.constraints = {
+		.name = "VGEN3",
+		.min_uV = 1800000,
+		.max_uV = 2900000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	}
+};
+
+static struct mc13xxx_regulator_init_data mx35_3ds_regulators[] = {
+	{ .id = MC13892_SW1, .init_data = &sw1_init },
+	{ .id = MC13892_SW2, .init_data = &sw2_init },
+	{ .id = MC13892_SW3, .init_data = &sw3_init },
+	{ .id = MC13892_SW4, .init_data = &sw4_init },
+	{ .id = MC13892_VIOHI, .init_data = &viohi_init },
+	{ .id = MC13892_VPLL, .init_data = &vpll_init },
+	{ .id = MC13892_VDIG, .init_data = &vdig_init },
+	{ .id = MC13892_VUSB2, .init_data = &vusb2_init },
+	{ .id = MC13892_VVIDEO, .init_data = &vvideo_init },
+	{ .id = MC13892_VAUDIO, .init_data = &vaudio_init },
+	{ .id = MC13892_VCAM, .init_data = &vcam_init },
+	{ .id = MC13892_VGEN1, .init_data = &vgen1_init },
+	{ .id = MC13892_VGEN2, .init_data = &vgen2_init },
+	{ .id = MC13892_VGEN3, .init_data = &vgen3_init },
+	{ .id = MC13892_VUSB, .init_data = &vusb_init },
+};
+
+static struct mc13xxx_platform_data mx35_3ds_mc13892_data = {
+	.flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
+	.regulators = {
+		.num_regulators = ARRAY_SIZE(mx35_3ds_regulators),
+		.regulators = mx35_3ds_regulators,
+	},
+};
+
+static struct i2c_board_info mx35_3ds_i2c_mc13892 = {
+
+	I2C_BOARD_INFO("mc13892", 0x08),
+	.platform_data = &mx35_3ds_mc13892_data,
+	.irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
+};
+
+static void __init imx35_3ds_init_mc13892(void)
+{
+	int ret = gpio_request_one(GPIO_PMIC_INT, GPIOF_DIR_IN, "pmic irq");
+
+	if (ret) {
+		pr_err("failed to get pmic irq: %d\n", ret);
+		return;
+	}
+
+	i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1);
+}
+
 static int mx35_3ds_otg_init(struct platform_device *pdev)
 {
 	return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
@@ -204,6 +403,7 @@ static void __init mx35_3ds_init(void)
 		pr_warn("Init of the debugboard failed, all "
 				"devices on the debugboard are unusable.\n");
 	imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+	imx35_3ds_init_mc13892();
 }
 
 static void __init mx35pdk_timer_init(void)
-- 
1.7.1



From alexg at meprolight.com  Mon Mar 26 10:40:08 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Mon, 26 Mar 2012 16:40:08 +0200
Subject: [PATCH] regmap: Add 24 bits support
Message-ID: <1332772808-13346-1-git-send-email-alexg@meprolight.com>

This patch adds support for PMIC who use regmap and 24 bit registers
For example MC13892, the patch was tested on i.MX35-PDK

Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
---
 drivers/base/regmap/internal.h |    1 +
 drivers/base/regmap/regmap.c   |   18 ++++++++++++++++++
 2 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h
index 1a02b75..3c5d204 100644
--- a/drivers/base/regmap/internal.h
+++ b/drivers/base/regmap/internal.h
@@ -122,5 +122,6 @@ int regcache_lookup_reg(struct regmap *map, unsigned int reg);
 
 extern struct regcache_ops regcache_rbtree_ops;
 extern struct regcache_ops regcache_lzo_ops;
+typedef struct { __u8 b[3]; } __be24;
 
 #endif
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index 6555803..499ee6a 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -114,6 +114,13 @@ static void regmap_format_16(void *buf, unsigned int val)
 	b[0] = cpu_to_be16(val);
 }
 
+static void regmap_format_24(void *buf, unsigned int val)
+{
+	__be24 *b = buf;
+
+	b[0] = (__be24){ {(val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff } };
+}
+
 static unsigned int regmap_parse_8(void *buf)
 {
 	u8 *b = buf;
@@ -130,6 +137,13 @@ static unsigned int regmap_parse_16(void *buf)
 	return b[0];
 }
 
+static unsigned int regmap_parse_24(void *buf)
+{
+	__be24 *b = buf;
+
+	return (b->b[0] << 16) | (b->b[1] << 8) | (b->b[2]);
+}
+
 /**
  * regmap_init(): Initialise register map
  *
@@ -229,6 +243,10 @@ struct regmap *regmap_init(struct device *dev,
 		map->format.format_val = regmap_format_16;
 		map->format.parse_val = regmap_parse_16;
 		break;
+	case 24:
+		map->format.format_val = regmap_format_24;
+		map->format.parse_val = regmap_parse_24;
+		break;
 	}
 
 	if (!map->format.format_write &&
-- 
1.7.0.4



From broonie at opensource.wolfsonmicro.com  Mon Mar 26 10:50:55 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 26 Mar 2012 15:50:55 +0100
Subject: [PATCH] regmap: Add 24 bits support
In-Reply-To: <1332772808-13346-1-git-send-email-alexg@meprolight.com>
References: <1332772808-13346-1-git-send-email-alexg@meprolight.com>
Message-ID: <20120326145054.GV3098@opensource.wolfsonmicro.com>

On Mon, Mar 26, 2012 at 04:40:08PM +0200, Alex Gershgorin wrote:
> This patch adds support for PMIC who use regmap and 24 bit registers
> For example MC13892, the patch was tested on i.MX35-PDK

A similar patch from Marc Reilly has already been applied.  You don't
have his signoff here but then...

> +typedef struct { __u8 b[3]; } __be24;

...you're adding stuff like this to the regmap headers which *clearly*
isn't regmap specific so this looks like a separate development.
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From grinberg at compulab.co.il  Mon Mar 26 10:51:10 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Mon, 26 Mar 2012 16:51:10 +0200
Subject: [PATCH] ARM: OMAP: fix section mismatches in usb-host.c
Message-ID: <1332773470-22800-1-git-send-email-grinberg@compulab.co.il>

Fix the below section mismatch warning and alike:

WARNING: vmlinux.o(.text+0x281d4): Section mismatch in reference from
the function setup_ehci_io_mux() to the function
.init.text:omap_mux_init_signal()
The function setup_ehci_io_mux() references
the function __init omap_mux_init_signal().
This is often because setup_ehci_io_mux lacks a __init
annotation or the annotation of omap_mux_init_signal is wrong.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/mach-omap2/usb-host.c |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index f51348d..dde8a11 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -54,7 +54,7 @@ static struct omap_device_pm_latency omap_uhhtll_latency[] = {
 /*
  * setup_ehci_io_mux - initialize IO pad mux for USBHOST
  */
-static void setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
+static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 {
 	switch (port_mode[0]) {
 	case OMAP_EHCI_PORT_MODE_PHY:
@@ -197,7 +197,8 @@ static void setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 	return;
 }
 
-static void setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
+static
+void __init setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 {
 	switch (port_mode[0]) {
 	case OMAP_EHCI_PORT_MODE_PHY:
@@ -315,7 +316,7 @@ static void setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 	}
 }
 
-static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
+static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 {
 	switch (port_mode[0]) {
 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
@@ -412,7 +413,8 @@ static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 	}
 }
 
-static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
+static
+void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 {
 	switch (port_mode[0]) {
 	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
-- 
1.7.3.4



From broonie at opensource.wolfsonmicro.com  Mon Mar 26 10:47:12 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 26 Mar 2012 15:47:12 +0100
Subject: [PATCH v1] regulator: i.MX35-PDK Add regulator support
In-Reply-To: <1332772593-13313-1-git-send-email-alexg@meprolight.com>
References: <1332772593-13313-1-git-send-email-alexg@meprolight.com>
Message-ID: <20120326144712.GA8579@sirena.org.uk>

On Mon, Mar 26, 2012 at 04:36:33PM +0200, Alex Gershgorin wrote:

> +static struct regulator_init_data sw1_init = {
> +	.constraints = {
> +		.name = "SW1",
> +		.min_uV = 600000,
> +		.max_uV = 1375000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +		.valid_modes_mask = 0,
> +		.always_on = 1,
> +		.boot_on = 1,
> +	}
> +};

These constraints don't make sense, you've got a voltage range and the
ability to change voltages but no consumers so nothing that could ever
change the voltage...

> +static struct regulator_init_data vpll_init = {
> +	.constraints = {
> +		.name = "VPLL",
> +		.min_uV = 1050000,
> +		.max_uV = 1800000,
> +		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +		.boot_on = 1,
> +	}
> +};

...and in many cases the supply names don't look like things I'd expect
to be varying too much at runtime.  It looks like you just typed the
maximum datasheet ranges in, not things that make sense for the board.


From swarren at wwwdotorg.org  Mon Mar 26 11:06:02 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 26 Mar 2012 09:06:02 -0600
Subject: uImage with integrated dtb file
In-Reply-To: <4F6E5D5B.8050306@antcom.de>
References: <4F6E5D5B.8050306@antcom.de>
Message-ID: <4F7085DA.6030402@wwwdotorg.org>

On 03/24/2012 05:48 PM, Roland Stigge wrote:
> Hi,
> 
> since I will need to maintain some machines with DT enabled kernels but 
> containing a U-Boot without DT support, I sometimes need to integrate a 
> dtb file into uImage.
> 
> I'm sure others have got the same issue. But searching for a while I 
> only got older/meanwhile neglected approaches like:
> 
> git://kernel.ubuntu.com/jk/dt/linux-2.6.git - branch: dtbimage
> 
> I'm currently using a simple hack like attached below.
...
> --- a/arch/arm/boot/Makefile
...
>  quiet_cmd_uimage = UIMAGE  $@
> -      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
> +      cmd_uimage = cat $< arch/arm/boot/*.dtb > $<.tmp ; \

That won't work well when multiple .dtb files are built. That's
certainly common for Tegra, and probably most subarchs.

The concatenation should be optional; people not using
CONFIG_APPENDED_DTB (hopefully the majority) wouldn't want this for example.

Please be aware of:

https://lkml.org/lkml/2012/3/16/450
Kbuild: centralize MKIMAGE and cmd_uimage definitions

I believe previous discussion around this topic has resolved into people
not wanting to make CONFIG_APPENDED_DTB to easy to use, so that people
who don't need to use it won't be tempted to just use it instead of
explicit FDT support in bootloaders. For example, see:

https://lkml.org/lkml/2011/8/2/200
Build a uImage with dtb already appended

... which Grant has specifically stated he didn't want applied upstream
for the reason I mention above.

> +                  $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
>                    -C none -a $(LOADADDR) -e $(STARTADDR) \
> -                  -n 'Linux-$(KERNELRELEASE)' -d $< $@
> +                  -n 'Linux-$(KERNELRELEASE)' -d $<.tmp $@ ; \
> +                  rm -f $<.tmp


From will.deacon at arm.com  Mon Mar 26 11:15:19 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 26 Mar 2012 16:15:19 +0100
Subject: [Android-virt] [PATCH] ARM: test for PMU feature on v7 (v2 with
 typo fix)
In-Reply-To: <CAFEAcA-S3pN0AihjMZdchRyvFpifvKN8rNytpEP_iaA3H5RWfQ@mail.gmail.com>
References: <4F590411.9060201@arm.com> <87ty1g88dv.fsf@rustcorp.com.au>
 <87r4wk889a.fsf@rustcorp.com.au>
 <20120323095314.GA13622@mudshark.cambridge.arm.com>
 <87fwcy9abw.fsf@rustcorp.com.au>
 <20120326094054.GA2475@mudshark.cambridge.arm.com>
 <CAFEAcA-S3pN0AihjMZdchRyvFpifvKN8rNytpEP_iaA3H5RWfQ@mail.gmail.com>
Message-ID: <20120326151519.GJ2475@mudshark.cambridge.arm.com>

On Mon, Mar 26, 2012 at 10:50:35AM +0100, Peter Maydell wrote:
> On 26 March 2012 10:40, Will Deacon <will.deacon at arm.com> wrote:
> > On Fri, Mar 23, 2012 at 11:17:07PM +0000, Rusty Russell wrote:
> >>
> >> OK, I see that argument, but I don't like it. ?eg. the Cortex A-15 is
> >> defined to have a PMUv2 with 6 counters, and below you're arguing we
> >> should implement zero of them.
> >
> > Well, I think you should actually implement all 6 of them if that's the
> > target which you're emulating.
> 
> The trouble with this line of thought is that it leads to the requirement
> to support nested virtualization and virtualization of TrustZone, neither
> of which are actually particularly useful or simple to do. At some point
> we're going to end up saying that the "A15" we expose to the guest is
> not an exact match to the real hardware, that it's missing certain
> features (and hopefully that the lack of those features is advertised
> via the feature registers). So the question is where you draw the line...

I'd be inclined to say that, at least for kvm, you should draw the line at
the point where the guest doesn't need modifications to run in the virtual
environment. That is, everything used by Linux is emulated enough for the
kernel to run happily. Clearly you can improve on that in the areas which
are considered to be most critical.

Aside: given that guests have to run non-secure, how would you emulate a
secure platform without emulating the corresponding TrustZone API? Or is
that one of the reasons why you're currently targetting Versatile Express?

Will


From will.deacon at arm.com  Mon Mar 26 11:20:37 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 26 Mar 2012 16:20:37 +0100
Subject: ARM11MPcore: tlb_ops_need_broadcast causes deadlock
In-Reply-To: <20120325215535.GB3147@n2100.arm.linux.org.uk>
References: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
 <20120323173055.GC16225@mudshark.cambridge.arm.com>
 <loom.20120325T135816-592@post.gmane.org>
 <20120325130912.GF5611@n2100.arm.linux.org.uk>
 <4F6F624D.8060409@mac.com>
 <20120325191556.GA3147@n2100.arm.linux.org.uk>
 <4F6F7E99.1020500@mac.com>
 <20120325215535.GB3147@n2100.arm.linux.org.uk>
Message-ID: <20120326152037.GK2475@mudshark.cambridge.arm.com>

Hmm, I somehow got dropped from this, but I'll pick it back up here.

On Sun, Mar 25, 2012 at 10:55:35PM +0100, Russell King - ARM Linux wrote:
> On Sun, Mar 25, 2012 at 10:22:49PM +0200, Peter Waechtler wrote:
> > And again I don't understand the abort handler: why do we get a page  
> > fault on
> > a young page then? grrh
> 
> Permissions?  Userspace trying to write to the page when it isn't marked
> writable and dirty?
> 
> >> Moreover, what about the case where we actually remove the page?
> > I don't claim that this is the only way to deadlock - but this is the  
> > case we encounter.
> 
> No, but you're arguing that we drop the TLB flush for your specific case.
> I'm telling you that's pointless if there's other cases as well which
> we'll deadlock.
> 
> But that's neither here nor there because you haven't fully explained
> what the problem is yet..

Yes, I'm inclined to agree with Russell here. Things don't add up and
without further information there's not a lot we can do.

Peter - are you able to reproduce and investigate this problem or was it a
one-off observation? If you can figure out what really goes on inside CPU B
in your example, then we may be able to look into this further. A good first
step might be to work out what triggers the initial data abort and look at
the state of the world at that point.

Will


From alexg at meprolight.com  Mon Mar 26 11:28:55 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Mon, 26 Mar 2012 17:28:55 +0200
Subject: [PATCH v1] regulator: i.MX35-PDK Add regulator support
In-Reply-To: <20120326144712.GA8579@sirena.org.uk>
References: <1332772593-13313-1-git-send-email-alexg@meprolight.com>,
 <20120326144712.GA8579@sirena.org.uk>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD16@MEP-EXCH.meprolight.com>


Hi Mark,

Thanks for you quick responds and comments.
 
On Mon, Mar 26, 2012 at 04:36:33PM +0200, Alex Gershgorin wrote:

> +static struct regulator_init_data sw1_init = {
> +     .constraints = {
> +             .name = "SW1",
> +             .min_uV = 600000,
> +             .max_uV = 1375000,
> +             .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +             .valid_modes_mask = 0,
> +             .always_on = 1,
> +             .boot_on = 1,
> +     }
> +};

> >These constraints don't make sense, you've got a voltage range and the
> >ability to change voltages but no consumers so nothing that could ever
> >change the voltage...

Yes, you are right I will add  consumers. 

> +static struct regulator_init_data vpll_init = {
> +     .constraints = {
> +             .name = "VPLL",
> +             .min_uV = 1050000,
> +             .max_uV = 1800000,
> +             .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> +             .boot_on = 1,
> +     }
> +};

> >...and in many cases the supply names don't look like things I'd expect
> >to be varying too much at runtime.  It looks like you just typed the
> >maximum datasheet ranges in, not things that make sense for the board.

It's not quite true, I was based on the Freescale BSP and I assume, that this is checked.
I also tested it on v3.3

Regards,
Alex Gershgorin 



From broonie at opensource.wolfsonmicro.com  Mon Mar 26 11:34:29 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 26 Mar 2012 16:34:29 +0100
Subject: [PATCH v1] regulator: i.MX35-PDK Add regulator support
In-Reply-To: <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD16@MEP-EXCH.meprolight.com>
References: <1332772593-13313-1-git-send-email-alexg@meprolight.com>
 <20120326144712.GA8579@sirena.org.uk>
 <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD16@MEP-EXCH.meprolight.com>
Message-ID: <20120326153429.GX3098@opensource.wolfsonmicro.com>

On Mon, Mar 26, 2012 at 05:28:55PM +0200, Alex Gershgorin wrote:
> On Mon, Mar 26, 2012 at 04:36:33PM +0200, Alex Gershgorin wrote:

Fix your mailer to word wrap within paragraphs, I reflowed your text to
be legible.

> > >...and in many cases the supply names don't look like things I'd expect
> > >to be varying too much at runtime.  It looks like you just typed the
> > >maximum datasheet ranges in, not things that make sense for the board.

> It's not quite true, I was based on the Freescale BSP and I assume,
> that this is checked.  I also tested it on v3.3

Uh, presence in a vendor BSP isn't a guarantee of sanity...  Since you
didn't specify any consumers the regulator API obviously won't do
anything with the voltage range provided but to repeat it's really not
at all obvious that anything sane ever would.
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From scottwood at freescale.com  Mon Mar 26 11:53:29 2012
From: scottwood at freescale.com (Scott Wood)
Date: Mon, 26 Mar 2012 10:53:29 -0500
Subject: [PATCH V2 3/3] ARM: kirkwood: Define NAND partitions in dts
In-Reply-To: <1332594876-8673-4-git-send-email-jm@lentin.co.uk>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <1332594876-8673-4-git-send-email-jm@lentin.co.uk>
Message-ID: <4F7090F9.5000603@freescale.com>

On 03/24/2012 08:14 AM, Jamie Lentin wrote:
> Use devicetree to define NAND partitions. Use D-link partition scheme by
> default, to be vaguely compatible with their userland.
> 
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> ---
>  arch/arm/boot/dts/kirkwood-dns320.dts |   35 +++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/kirkwood-dns325.dts |   35 +++++++++++++++++++++++++++++++++
>  arch/arm/mach-kirkwood/board-dnskw.c  |   31 -----------------------------
>  3 files changed, 70 insertions(+), 31 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
> index 58de7f2..fbf55ff 100644
> --- a/arch/arm/boot/dts/kirkwood-dns320.dts
> +++ b/arch/arm/boot/dts/kirkwood-dns320.dts
> @@ -25,5 +25,40 @@
>  			clock-frequency = <166666667>;
>  			status = "ok";
>  		};
> +
> +		nand at 3000000 {
> +			status = "ok";
> +

This should be "okay", not "ok" -- see IEEE1275.  Or just leave it out.

-Scott



From jason at lakedaemon.net  Mon Mar 26 12:20:50 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 26 Mar 2012 12:20:50 -0400
Subject: [PATCH V2 3/3] ARM: kirkwood: Define NAND partitions in dts
In-Reply-To: <4F7090F9.5000603@freescale.com>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <1332594876-8673-4-git-send-email-jm@lentin.co.uk>
 <4F7090F9.5000603@freescale.com>
Message-ID: <20120326162050.GT2484@titan.lakedaemon.net>

On Mon, Mar 26, 2012 at 10:53:29AM -0500, Scott Wood wrote:
> On 03/24/2012 08:14 AM, Jamie Lentin wrote:
> > Use devicetree to define NAND partitions. Use D-link partition scheme by
> > default, to be vaguely compatible with their userland.
> > 
> > Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> > ---
> >  arch/arm/boot/dts/kirkwood-dns320.dts |   35 +++++++++++++++++++++++++++++++++
> >  arch/arm/boot/dts/kirkwood-dns325.dts |   35 +++++++++++++++++++++++++++++++++
> >  arch/arm/mach-kirkwood/board-dnskw.c  |   31 -----------------------------
> >  3 files changed, 70 insertions(+), 31 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
> > index 58de7f2..fbf55ff 100644
> > --- a/arch/arm/boot/dts/kirkwood-dns320.dts
> > +++ b/arch/arm/boot/dts/kirkwood-dns320.dts
> > @@ -25,5 +25,40 @@
> >  			clock-frequency = <166666667>;
> >  			status = "ok";
> >  		};
> > +
> > +		nand at 3000000 {
> > +			status = "ok";
> > +
> 
> This should be "okay", not "ok" -- see IEEE1275.  Or just leave it out.

Ack, but it needs to be there.  Most, but not all, kirkwood boards have
nand, so we define it in kirkwood.dtsi and set it as disabled.
Individual boards can then enable it as needed.

As for 'okay', looks like we may need to patch of_device_is_available()
in drivers/of/base.c (~284) if we want to be consistent with IEEE1275.

The following boards would need to be updated:

arch/arm/boot/dts/kirkwood-dreamplug.dts
arch/powerpc/boot/dts/currituck.dts
arch/powerpc/boot/dts/iss4xx-mpic.dts

Grant, any thoughts on this?

thx,

Jason.


From swarren at wwwdotorg.org  Mon Mar 26 12:19:47 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Mon, 26 Mar 2012 10:19:47 -0600
Subject: [GIT PULL] ARM: tegra: Include assembler.h in sleep.S to fix build
 break
Message-ID: <4F709723.4080206@wwwdotorg.org>

Arnd, Olof,

This pull request depends on the merge of:

git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
devel/io-cleanup
(specifically 6f6f6a7 ARM: create a common IOMEM definition)

and:

git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git for-3.4/soc
(specifically c76fcc8 ARM: tegra: assembler code for LP3)

and is based on a local branch that merges the two branches above.

The following changes since commit 1ad105fc77e61f9dd7a272659a248e2979fdb893:
  Stephen Warren (1):
        Merge remote branch 'remotes/korg_olof_tegra/for-3.4/soc' into
for-3.4/fixes-for-io-cleanup

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git
for-3.4/fixes-for-io-cleanup

Stephen Warren (1):
      ARM: tegra: Include assembler.h in sleep.S to fix build break

 arch/arm/mach-tegra/sleep.S |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)



From scottwood at freescale.com  Mon Mar 26 12:28:14 2012
From: scottwood at freescale.com (Scott Wood)
Date: Mon, 26 Mar 2012 11:28:14 -0500
Subject: [PATCH V2 3/3] ARM: kirkwood: Define NAND partitions in dts
In-Reply-To: <20120326162050.GT2484@titan.lakedaemon.net>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <1332594876-8673-4-git-send-email-jm@lentin.co.uk>
 <4F7090F9.5000603@freescale.com> <20120326162050.GT2484@titan.lakedaemon.net>
Message-ID: <4F70991E.1000204@freescale.com>

On 03/26/2012 11:20 AM, Jason Cooper wrote:
> On Mon, Mar 26, 2012 at 10:53:29AM -0500, Scott Wood wrote:
>> On 03/24/2012 08:14 AM, Jamie Lentin wrote:
>>> Use devicetree to define NAND partitions. Use D-link partition scheme by
>>> default, to be vaguely compatible with their userland.
>>>
>>> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
>>> ---
>>>  arch/arm/boot/dts/kirkwood-dns320.dts |   35 +++++++++++++++++++++++++++++++++
>>>  arch/arm/boot/dts/kirkwood-dns325.dts |   35 +++++++++++++++++++++++++++++++++
>>>  arch/arm/mach-kirkwood/board-dnskw.c  |   31 -----------------------------
>>>  3 files changed, 70 insertions(+), 31 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
>>> index 58de7f2..fbf55ff 100644
>>> --- a/arch/arm/boot/dts/kirkwood-dns320.dts
>>> +++ b/arch/arm/boot/dts/kirkwood-dns320.dts
>>> @@ -25,5 +25,40 @@
>>>  			clock-frequency = <166666667>;
>>>  			status = "ok";
>>>  		};
>>> +
>>> +		nand at 3000000 {
>>> +			status = "ok";
>>> +
>>
>> This should be "okay", not "ok" -- see IEEE1275.  Or just leave it out.
> 
> Ack, but it needs to be there.  Most, but not all, kirkwood boards have
> nand, so we define it in kirkwood.dtsi and set it as disabled.
> Individual boards can then enable it as needed.
> 
> As for 'okay', looks like we may need to patch of_device_is_available()
> in drivers/of/base.c (~284) if we want to be consistent with IEEE1275.

No need to change of_device_is_available() -- it handles the
standards-compliant "okay" as well as "ok" which is non-compliant but
probably exists in some broken real OF trees (and even if not, it's bad
to break compatibility with older device trees without a good reason).

Maybe add a comment indicating which should be used.

-Scott



From jason at lakedaemon.net  Mon Mar 26 12:43:25 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 26 Mar 2012 12:43:25 -0400
Subject: [PATCH V2 3/3] ARM: kirkwood: Define NAND partitions in dts
In-Reply-To: <alpine.DEB.2.00.1203261730590.23719@marmot.wormnet.eu>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <1332594876-8673-4-git-send-email-jm@lentin.co.uk>
 <4F7090F9.5000603@freescale.com>
 <20120326162050.GT2484@titan.lakedaemon.net>
 <4F70991E.1000204@freescale.com>
 <alpine.DEB.2.00.1203261730590.23719@marmot.wormnet.eu>
Message-ID: <20120326164325.GU2484@titan.lakedaemon.net>

On Mon, Mar 26, 2012 at 05:36:10PM +0100, Jamie Lentin wrote:
> On Mon, 26 Mar 2012, Scott Wood wrote:
> 
> >On 03/26/2012 11:20 AM, Jason Cooper wrote:
> >>On Mon, Mar 26, 2012 at 10:53:29AM -0500, Scott Wood wrote:
> >>>On 03/24/2012 08:14 AM, Jamie Lentin wrote:
> >>>>Use devicetree to define NAND partitions. Use D-link partition scheme by
> >>>>default, to be vaguely compatible with their userland.
> >>>>
> >>>>Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> >>>>---
> >>>> arch/arm/boot/dts/kirkwood-dns320.dts |   35 +++++++++++++++++++++++++++++++++
> >>>> arch/arm/boot/dts/kirkwood-dns325.dts |   35 +++++++++++++++++++++++++++++++++
> >>>> arch/arm/mach-kirkwood/board-dnskw.c  |   31 -----------------------------
> >>>> 3 files changed, 70 insertions(+), 31 deletions(-)
> >>>>
> >>>>diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
> >>>>index 58de7f2..fbf55ff 100644
> >>>>--- a/arch/arm/boot/dts/kirkwood-dns320.dts
> >>>>+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
> >>>>@@ -25,5 +25,40 @@
> >>>> 			clock-frequency = <166666667>;
> >>>> 			status = "ok";
> >>>> 		};
> >>>>+
> >>>>+		nand at 3000000 {
> >>>>+			status = "ok";
> >>>>+
> >>>
> >>>This should be "okay", not "ok" -- see IEEE1275.  Or just leave it out.
> >>
> >>Ack, but it needs to be there.  Most, but not all, kirkwood boards have
> >>nand, so we define it in kirkwood.dtsi and set it as disabled.
> >>Individual boards can then enable it as needed.
> >>
> >>As for 'okay', looks like we may need to patch of_device_is_available()
> >>in drivers/of/base.c (~284) if we want to be consistent with IEEE1275.
> >
> >No need to change of_device_is_available() -- it handles the
> >standards-compliant "okay" as well as "ok" which is non-compliant but
> >probably exists in some broken real OF trees (and even if not, it's bad
> >to break compatibility with older device trees without a good reason).
> >
> >Maybe add a comment indicating which should be used.
> 
> I need to re-jig this part anyway, so will update to "okay"
> too---looks like a fairly harmless change.
> 
> Would it make sense to change drivers/of/base.c to emit a warning if
> "ok" is used? Or are there already too many devicetrees in the wild
> that use "ok"?

There's only two powerpc boards using this.  I have a patch I'm about
to submit that just adds a comment above the test.  Since that's where I
pulled "ok" from, that should prevent others in the future from repeating
my mistake.

thx,

Jason.


From jm at lentin.co.uk  Mon Mar 26 12:36:10 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Mon, 26 Mar 2012 17:36:10 +0100 (BST)
Subject: [PATCH V2 3/3] ARM: kirkwood: Define NAND partitions in dts
In-Reply-To: <4F70991E.1000204@freescale.com>
References: <1332594876-8673-1-git-send-email-jm@lentin.co.uk>
 <1332594876-8673-4-git-send-email-jm@lentin.co.uk>
 <4F7090F9.5000603@freescale.com> <20120326162050.GT2484@titan.lakedaemon.net>
 <4F70991E.1000204@freescale.com>
Message-ID: <alpine.DEB.2.00.1203261730590.23719@marmot.wormnet.eu>

On Mon, 26 Mar 2012, Scott Wood wrote:

> On 03/26/2012 11:20 AM, Jason Cooper wrote:
>> On Mon, Mar 26, 2012 at 10:53:29AM -0500, Scott Wood wrote:
>>> On 03/24/2012 08:14 AM, Jamie Lentin wrote:
>>>> Use devicetree to define NAND partitions. Use D-link partition scheme by
>>>> default, to be vaguely compatible with their userland.
>>>>
>>>> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
>>>> ---
>>>>  arch/arm/boot/dts/kirkwood-dns320.dts |   35 +++++++++++++++++++++++++++++++++
>>>>  arch/arm/boot/dts/kirkwood-dns325.dts |   35 +++++++++++++++++++++++++++++++++
>>>>  arch/arm/mach-kirkwood/board-dnskw.c  |   31 -----------------------------
>>>>  3 files changed, 70 insertions(+), 31 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
>>>> index 58de7f2..fbf55ff 100644
>>>> --- a/arch/arm/boot/dts/kirkwood-dns320.dts
>>>> +++ b/arch/arm/boot/dts/kirkwood-dns320.dts
>>>> @@ -25,5 +25,40 @@
>>>>  			clock-frequency = <166666667>;
>>>>  			status = "ok";
>>>>  		};
>>>> +
>>>> +		nand at 3000000 {
>>>> +			status = "ok";
>>>> +
>>>
>>> This should be "okay", not "ok" -- see IEEE1275.  Or just leave it out.
>>
>> Ack, but it needs to be there.  Most, but not all, kirkwood boards have
>> nand, so we define it in kirkwood.dtsi and set it as disabled.
>> Individual boards can then enable it as needed.
>>
>> As for 'okay', looks like we may need to patch of_device_is_available()
>> in drivers/of/base.c (~284) if we want to be consistent with IEEE1275.
>
> No need to change of_device_is_available() -- it handles the
> standards-compliant "okay" as well as "ok" which is non-compliant but
> probably exists in some broken real OF trees (and even if not, it's bad
> to break compatibility with older device trees without a good reason).
>
> Maybe add a comment indicating which should be used.

I need to re-jig this part anyway, so will update to "okay" too---looks 
like a fairly harmless change.

Would it make sense to change drivers/of/base.c to emit a warning if "ok" 
is used? Or are there already too many devicetrees in the wild that use 
"ok"?

>
> -Scott
>
>

-- 
Jamie Lentin


From jason at lakedaemon.net  Mon Mar 26 12:52:55 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Mon, 26 Mar 2012 16:52:55 +0000
Subject: [PATCH] ARM: kirkwood: fdt: use IEEE1275 status = "okay".
In-Reply-To: <4F70991E.1000204@freescale.com>
References: <4F70991E.1000204@freescale.com>
Message-ID: <1332780775-3694-1-git-send-email-jason@lakedaemon.net>

Signed-off-by: Jason Cooper <jason at lakedaemon.net>
---
 - This should prevent others from making the same mistake I did when searching
   the code.

 arch/arm/boot/dts/kirkwood-dreamplug.dts |    2 +-
 drivers/of/base.c                        |    1 +
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index a5376b8..7b2b961 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -18,7 +18,7 @@
 	ocp at f1000000 {
 		serial at 12000 {
 			clock-frequency = <200000000>;
-			status = "ok";
+			status = "okay";
 		};
 	};
 };
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 133908a..31eac15 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -285,6 +285,7 @@ int of_device_is_available(const struct device_node *device)
 		return 1;
 
 	if (statlen > 0) {
+		/* new boards should use "okay" according to IEEE1275 */
 		if (!strcmp(status, "okay") || !strcmp(status, "ok"))
 			return 1;
 	}
-- 
1.7.3.4



From stigge at antcom.de  Mon Mar 26 12:48:23 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 26 Mar 2012 18:48:23 +0200
Subject: uImage with integrated dtb file
In-Reply-To: <4F7085DA.6030402@wwwdotorg.org>
References: <4F6E5D5B.8050306@antcom.de> <4F7085DA.6030402@wwwdotorg.org>
Message-ID: <4F709DD7.2080606@antcom.de>

On 26/03/12 17:06, Stephen Warren wrote:
>>  quiet_cmd_uimage = UIMAGE  $@
>> -      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
>> +      cmd_uimage = cat $< arch/arm/boot/*.dtb > $<.tmp ; \
> 
> That won't work well when multiple .dtb files are built.

That's completely correct! Therefore I called it "hack" (maybe
forgetting to prefix it "ugly"), so please don't use it. ;-)

Roland


From oleg at redhat.com  Mon Mar 26 13:04:43 2012
From: oleg at redhat.com (Oleg Nesterov)
Date: Mon, 26 Mar 2012 19:04:43 +0200
Subject: [PATCH v2.1 01/10] cpu: Introduce clear_tasks_mm_cpumask() helper
In-Reply-To: <1332748746.16159.62.camel@twins>
References: <20120324102609.GA28356@lizard> <20120324102751.GA29067@lizard>
 <1332593021.16159.27.camel@twins> <20120324164316.GB3640@lizard>
 <20120325174210.GA23605@redhat.com> <1332748746.16159.62.camel@twins>
Message-ID: <20120326170443.GA25229@redhat.com>

On 03/26, Peter Zijlstra wrote:
>
> On Sun, 2012-03-25 at 19:42 +0200, Oleg Nesterov wrote:
> > __cpu_disable() is called by __stop_machine(), we know that nobody
> > can preempt us and other CPUs can do nothing.
>
> It would be very good to not rely on that though,

Yes, yes, perhaps I wasn't clear but I think the patches are fine.

> I would love to get
> rid of the stop_machine usage in cpu hotplug some day.

Interesting... Why? I mean, why do you dislike stop_machine() in
_cpu_down() ? Just curious.

Oleg.



From alexg at meprolight.com  Mon Mar 26 13:30:05 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Mon, 26 Mar 2012 19:30:05 +0200
Subject: [PATCH] regmap: Add 24 bits support
In-Reply-To: <20120326145054.GV3098@opensource.wolfsonmicro.com>
References: <1332772808-13346-1-git-send-email-alexg@meprolight.com>,
 <20120326145054.GV3098@opensource.wolfsonmicro.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD1C@MEP-EXCH.meprolight.com>


 
>Subject: Re: [PATCH] regmap: Add 24 bits support

On Mon, Mar 26, 2012 at 04:40:08PM +0200, Alex Gershgorin wrote:
> This patch adds support for PMIC who use regmap and 24 bit registers
> For example MC13892, the patch was tested on i.MX35-PDK

> >A similar patch from Marc Reilly has already been applied.  You don't
> >have his signoff here but then...

Sorry Marc, I missed the patch 

> +typedef struct { __u8 b[3]; } __be24;

> > ...you're adding stuff like this to the regmap headers which *clearly*
> > isn't regmap specific so this looks like a separate development.

You right,

I think it makes no sense to fix it,
why do we need two similar patches

Thanks  


From jon-hunter at ti.com  Mon Mar 26 13:42:26 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Mon, 26 Mar 2012 12:42:26 -0500
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A9317BB895@DBDE01.ent.ti.com>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
 <4F6D0569.6080203@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A9317BB895@DBDE01.ent.ti.com>
Message-ID: <4F70AA82.3000204@ti.com>

Hi Afzal,

On 3/26/2012 3:04, Mohammed, Afzal wrote:
> Hi Jon,
>
> On Sat, Mar 24, 2012 at 04:51:13, Hunter, Jon wrote:
>>> +struct gpmc_child {
>>> +	char			*name;
>>> +	int			id;
>>> +	struct resource		*res;
>>> +	unsigned		num_res;
>>> +	struct resource		gpmc_res[GPMC_CS_NUM];
>>
>> Does this imply a gpmc child device can use more than one chip-select? I
>> am trying to understand the link between number of resources and
>> GPMC_CS_NUM.
>
> Yes, relevant portion in commit message as follows,
>
> A peripheral connected to GPMC can have multiple
> address spaces using different chip select. Hence
> GPMC driver has been provided capability to
> distinguish this scenario, i.e. create platform
> devices only once for each connected peripheral,
> and not for each configured chip select. The
> peripheral that made it necessary was tusb6010.

Ok, makes sense. I believe that most devices are using a single CS and 
less common for devices to use more than one. Therefore, I was not sure 
if it made sense to allocate the gpmc_res struct dynamically as I doubt 
you will ever have a device using all 8 chip-selects ;-)

Also, I don't see where the gpmc_child->res and gpmc_child->num_res are 
actually used. Are these needed?

[snip]

>> Do we need to free irqs here?
>
> Irqs has been conveniently forgotten in this patch, in mainline, I could
> not find any platforms using GPMC irq. This can be added later once
> driver conversion is done, if required.

I just meant that if we allocate them during the probe maybe we should 
remove when exiting.

[snip]

>>> +	/* GPMC specific */
>>> +	unsigned		cs;
>>> +	unsigned long		mem_size;
>>> +	unsigned long		mem_start;
>>> +	unsigned long		mem_offset;
>>> +	struct gpmc_config	*config;
>>> +	unsigned		num_config;
>>> +	struct gpmc_timings	*timing;
>>> +};
>>> +
>>> +struct gpmc_pdata {
>>> +	/* GPMC_FCLK rate in picoseconds */
>>> +	unsigned long			fclk_rate;
>>
>> fclk_period
>>
>>> +	struct gpmc_device_pdata	*device_pdata;
>>> +	unsigned			num_device;
>>> +};
>>
>> Do you need both gpmc_pdata and gpmc_device_pdata? Would not a single
>> structure work?
>
> Gpmc_device_data is dedicated to each CS, gpmc_pdata is required
> at least to inform driver about clock rate.

Ok, understood! So the struct gpmc_device_pdata only has a single 
chip-select entry and so looking at the code you will have multiple 
instances of this structure of a gpmc device that uses more than one 
chip-select. Any reason you did it this way and not have a single pdata 
struct for each device defining all chip-selects it uses?

> Generally, as the change involved moving a lot of code, seems more reviews
> are on those than the actual changes than what I intended to get reviewed,
> next patch series will be modified not to move existing code, hence some
> of your suggested changes may not be present in it, probably those to be
> done as another cleanup patch.

Yes I understand. However, it is a good opportunity to clean some of 
this up even if it is existing code :-)

Cheers
Jon


From broonie at opensource.wolfsonmicro.com  Mon Mar 26 13:43:30 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 26 Mar 2012 18:43:30 +0100
Subject: [GIT PULL] pxa io.h clean-up fixes
In-Reply-To: <4F6FC82C.2040303@gmail.com>
References: <4F6FC82C.2040303@gmail.com>
Message-ID: <20120326174330.GI3789@opensource.wolfsonmicro.com>

On Sun, Mar 25, 2012 at 08:36:44PM -0500, Rob Herring wrote:

> There's some new breakage when I merged the current next in and built
> with Russell's pxa test config. The failures are due to struct device
> removal in this commit:

Paul Gortmaker did send some attempts at fixing these, I don't know if
they ever got applied though.
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From jon-hunter at ti.com  Mon Mar 26 13:51:50 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Mon, 26 Mar 2012 12:51:50 -0500
Subject: [TMP][PATCH 5/5] OMAP3EVM: Test gpmc-nand
In-Reply-To: <1332484630-22181-1-git-send-email-afzal@ti.com>
References: <1332484630-22181-1-git-send-email-afzal@ti.com>
Message-ID: <4F70ACB6.5070208@ti.com>

Hi Afzal,

On 3/23/2012 1:37, Afzal Mohammed wrote:

[snip]

>   static void __init omap3_evm_init(void)
>   {
> +	struct omap_nand_platform_data *nand_data;
> +
>   	omap3_evm_get_revision();
>
>   	if (cpu_is_omap3630())
> @@ -684,6 +747,25 @@ static void __init omap3_evm_init(void)
>   	omap3evm_init_smsc911x();
>   	omap3_evm_display_init();
>   	omap3_evm_wl12xx_init();
> +	/* NAND */
> +	nand_data = omap_nand_init(omap3_evm_nand_partitions,
> +			ARRAY_SIZE(omap3_evm_nand_partitions),
> +			0, NAND_BUSWIDTH_16, nand_default_timings);
> +	if (nand_data == NULL) {
> +		pr_err("omap_nand_init() failed\n");
> +		return;
> +	}
> +
> +	gpmc_data.device_pdata = gpmc_nand_init(nand_data);
> +	if (gpmc_data.device_pdata == NULL) {
> +		pr_err("gpmc_nand_init() failed\n");
> +		return;
> +	}
> +
> +	gpmc_data.num_device++;
> +	gpmc_data.fclk_rate = gpmc_get_fclk_period();
> +
> +	platform_device_register(&gpmc_device);
>   }

I see this is marked as a temp patch, but this is actually needed to 
register the device. Actually, we would need to do this for all boards, 
right?

Rather than registering the device here, may be we should add a function 
in arch/arm/mach-omap2/devices.c called "omap_gpmc_init()" that is 
called from all of the boards files passing the pdata structure. Then 
the omap_gmpc_init() function should use omap_device_build() API to 
register the device. If you look at arch/arm/mach-omap2/devices.c you 
can look at omap4_keyboard_init() as an example. Let me know if this is 
clear.

Cheers
Jon


From a.p.zijlstra at chello.nl  Mon Mar 26 13:23:44 2012
From: a.p.zijlstra at chello.nl (Peter Zijlstra)
Date: Mon, 26 Mar 2012 19:23:44 +0200
Subject: [PATCH v2.1 01/10] cpu: Introduce clear_tasks_mm_cpumask() helper
In-Reply-To: <20120326170443.GA25229@redhat.com>
References: <20120324102609.GA28356@lizard> <20120324102751.GA29067@lizard>
 <1332593021.16159.27.camel@twins> <20120324164316.GB3640@lizard>
 <20120325174210.GA23605@redhat.com> <1332748746.16159.62.camel@twins>
 <20120326170443.GA25229@redhat.com>
Message-ID: <1332782624.16159.145.camel@twins>

On Mon, 2012-03-26 at 19:04 +0200, Oleg Nesterov wrote:

> Interesting... Why? I mean, why do you dislike stop_machine() in
> _cpu_down() ? Just curious.

It disturbs all cpus, the -rt people don't like that their FIFO tasks
don't get to run, the trading people don't like their RDMA poll loops to
be interrupted.. etc.

Now arguably, one should simply not do hotplug crap while such things
are running, and mostly that's a perfectly fine constraint. But it
doesn't help that people view cpu hotplug as a power savings or resource
provisioning 'feature' and there's userspace daemons that plug
on-demand.

But my ultimate goal is to completely remove synchronization that is
actively machine wide, since we all know that as long as such stuff
exists people will want to use it.

Now I don't know we'll ever fully get there -- see the BKL saga -- but
its worth trying I think. The module unload and esp. the text_poke usage
of stop_machine are much worse offenders, since both those are
relatively common and much harder to avoid.


From festevam at gmail.com  Mon Mar 26 14:09:34 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 26 Mar 2012 15:09:34 -0300
Subject: [PATCH 4/4] ARM i.MX 3ds debugboard: register a dummy regulator
 for the smsc911x device
In-Reply-To: <1330774804-7310-5-git-send-email-s.hauer@pengutronix.de>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
 <1330774804-7310-5-git-send-email-s.hauer@pengutronix.de>
Message-ID: <CAOMZO5DL8YQT2qb=vxdQtdN+zfZLK9H9_1qu5sS+1YAvSo5SAA@mail.gmail.com>

Hi Sascha,

On Sat, Mar 3, 2012 at 8:40 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>

...
> ? ? ? ?/* Register Lan device on the debugboard */
> + ? ? ? regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));

I am using linux-next, which has this patch applied and I am getting:

smsc911x smsc911x.0: Failed to get supply 'vdd33a': -517
smsc911x smsc911x.0: (unregistered net_device): couldn't get regulators -517
platform smsc911x.0: Driver smsc911x requests probe deferral

Does this work for you on pcm037?

If I select CONFIG_REGULATOR_DUMMY then the the smsc driver is probed
correctly, but if I understand correctly your suggestion was to not
select CONFIG_REGULATOR_DUMMY, right?


From s.hauer at pengutronix.de  Mon Mar 26 14:19:12 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 26 Mar 2012 20:19:12 +0200
Subject: [PATCH 4/4] ARM i.MX 3ds debugboard: register a dummy regulator
 for the smsc911x device
In-Reply-To: <CAOMZO5DL8YQT2qb=vxdQtdN+zfZLK9H9_1qu5sS+1YAvSo5SAA@mail.gmail.com>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
 <1330774804-7310-5-git-send-email-s.hauer@pengutronix.de>
 <CAOMZO5DL8YQT2qb=vxdQtdN+zfZLK9H9_1qu5sS+1YAvSo5SAA@mail.gmail.com>
Message-ID: <20120326181912.GV3852@pengutronix.de>

On Mon, Mar 26, 2012 at 03:09:34PM -0300, Fabio Estevam wrote:
> Hi Sascha,
> 
> On Sat, Mar 3, 2012 at 8:40 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> > Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
> 
> ...
> > ? ? ? ?/* Register Lan device on the debugboard */
> > + ? ? ? regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
> 
> I am using linux-next, which has this patch applied and I am getting:
> 
> smsc911x smsc911x.0: Failed to get supply 'vdd33a': -517
> smsc911x smsc911x.0: (unregistered net_device): couldn't get regulators -517
> platform smsc911x.0: Driver smsc911x requests probe deferral
> 
> Does this work for you on pcm037?

At least it did work when I sent the patches, but -EPROBE_DEFER did not
exist at that time. Do you have the fixed regulator enabled in your
config?

> 
> If I select CONFIG_REGULATOR_DUMMY then the the smsc driver is probed
> correctly, but if I understand correctly your suggestion was to not
> select CONFIG_REGULATOR_DUMMY, right?

Right.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From festevam at gmail.com  Mon Mar 26 14:25:38 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 26 Mar 2012 15:25:38 -0300
Subject: [PATCH 4/4] ARM i.MX 3ds debugboard: register a dummy regulator
 for the smsc911x device
In-Reply-To: <20120326181912.GV3852@pengutronix.de>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
 <1330774804-7310-5-git-send-email-s.hauer@pengutronix.de>
 <CAOMZO5DL8YQT2qb=vxdQtdN+zfZLK9H9_1qu5sS+1YAvSo5SAA@mail.gmail.com>
 <20120326181912.GV3852@pengutronix.de>
Message-ID: <CAOMZO5Bw4fFOYSDyiE8o9AnnrzTOukJtA1JFbNBeMMzx-jBVvA@mail.gmail.com>

On Mon, Mar 26, 2012 at 3:19 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:

> At least it did work when I sent the patches, but -EPROBE_DEFER did not
> exist at that time. Do you have the fixed regulator enabled in your
> config?

Yes, I do. I am using imx_v6_v7_defconfig, which has fixed regulator
enabled by default.


From festevam at gmail.com  Mon Mar 26 14:38:19 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 26 Mar 2012 15:38:19 -0300
Subject: [PATCH 4/4] ARM i.MX 3ds debugboard: register a dummy regulator
 for the smsc911x device
In-Reply-To: <CAOMZO5Bw4fFOYSDyiE8o9AnnrzTOukJtA1JFbNBeMMzx-jBVvA@mail.gmail.com>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
 <1330774804-7310-5-git-send-email-s.hauer@pengutronix.de>
 <CAOMZO5DL8YQT2qb=vxdQtdN+zfZLK9H9_1qu5sS+1YAvSo5SAA@mail.gmail.com>
 <20120326181912.GV3852@pengutronix.de>
 <CAOMZO5Bw4fFOYSDyiE8o9AnnrzTOukJtA1JFbNBeMMzx-jBVvA@mail.gmail.com>
Message-ID: <CAOMZO5Am-igTOwWhGRmd0PCihUaWMQPEMxWJk4YuezafMJStjA@mail.gmail.com>

On Mon, Mar 26, 2012 at 3:25 PM, Fabio Estevam <festevam at gmail.com> wrote:
> On Mon, Mar 26, 2012 at 3:19 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>
>> At least it did work when I sent the patches, but -EPROBE_DEFER did not
>> exist at that time. Do you have the fixed regulator enabled in your
>> config?
>
> Yes, I do. I am using imx_v6_v7_defconfig, which has fixed regulator
> enabled by default.

--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -151,8 +151,8 @@ static struct irq_chip expio_irq_chip = {
 };

If I do the change below, smsc driver is probed correctly:

 static struct regulator_consumer_supply dummy_supplies[] = {
-       REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-       REGULATOR_SUPPLY("vddvario", "smsc911x"),
+       REGULATOR_SUPPLY("vdd33a", NULL),
+       REGULATOR_SUPPLY("vddvario", NULL),
 };

Is this OK?


From festevam at gmail.com  Mon Mar 26 14:48:07 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Mon, 26 Mar 2012 15:48:07 -0300
Subject: [PATCH 4/4] ARM i.MX 3ds debugboard: register a dummy regulator
 for the smsc911x device
In-Reply-To: <CAOMZO5Am-igTOwWhGRmd0PCihUaWMQPEMxWJk4YuezafMJStjA@mail.gmail.com>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
 <1330774804-7310-5-git-send-email-s.hauer@pengutronix.de>
 <CAOMZO5DL8YQT2qb=vxdQtdN+zfZLK9H9_1qu5sS+1YAvSo5SAA@mail.gmail.com>
 <20120326181912.GV3852@pengutronix.de>
 <CAOMZO5Bw4fFOYSDyiE8o9AnnrzTOukJtA1JFbNBeMMzx-jBVvA@mail.gmail.com>
 <CAOMZO5Am-igTOwWhGRmd0PCihUaWMQPEMxWJk4YuezafMJStjA@mail.gmail.com>
Message-ID: <CAOMZO5AW8EHBcs+YZk9wpaTBCDHe8ZErUDdJoPQAofHCivQxGw@mail.gmail.com>

On Mon, Mar 26, 2012 at 3:38 PM, Fabio Estevam <festevam at gmail.com> wrote:

> ?static struct regulator_consumer_supply dummy_supplies[] = {
> - ? ? ? REGULATOR_SUPPLY("vdd33a", "smsc911x"),
> - ? ? ? REGULATOR_SUPPLY("vddvario", "smsc911x"),
> + ? ? ? REGULATOR_SUPPLY("vdd33a", NULL),
> + ? ? ? REGULATOR_SUPPLY("vddvario", NULL),

Actually the proper fix is:

--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -80,7 +80,7 @@ static struct smsc911x_platform_config smsc911x_config = {

 static struct platform_device smsc_lan9217_device = {
        .name = "smsc911x",
-       .id = 0,
+       .id = -1,
        .dev = {
                .platform_data = &smsc911x_config,
        },

Will send you the patch shortly.


From fabio.estevam at freescale.com  Mon Mar 26 14:53:57 2012
From: fabio.estevam at freescale.com (Fabio Estevam)
Date: Mon, 26 Mar 2012 15:53:57 -0300
Subject: [PATCH] ARM: 3ds_debugboard: Fix smsc911x driver probe
Message-ID: <1332788037-31064-1-git-send-email-fabio.estevam@freescale.com>

Fix smsc911x id field in order to fix smsc911x driver probe error:

smsc911x smsc911x.0: Failed to get supply 'vdd33a': -517
smsc911x smsc911x.0: (unregistered net_device): couldn't get regulators -517
platform smsc911x.0: Driver smsc911x requests probe deferral

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/plat-mxc/3ds_debugboard.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index d1e31fa..5cac2c5 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -80,7 +80,7 @@ static struct smsc911x_platform_config smsc911x_config = {
 
 static struct platform_device smsc_lan9217_device = {
 	.name = "smsc911x",
-	.id = 0,
+	.id = -1,
 	.dev = {
 		.platform_data = &smsc911x_config,
 	},
-- 
1.7.1




From alexg at meprolight.com  Mon Mar 26 14:56:35 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Mon, 26 Mar 2012 20:56:35 +0200
Subject: [PATCH v1] regulator: i.MX35-PDK Add regulator support
In-Reply-To: <20120326153429.GX3098@opensource.wolfsonmicro.com>
References: <1332772593-13313-1-git-send-email-alexg@meprolight.com>
 <20120326144712.GA8579@sirena.org.uk>
 <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD16@MEP-EXCH.meprolight.com>,
 <20120326153429.GX3098@opensource.wolfsonmicro.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD1F@MEP-EXCH.meprolight.com>


On Mon, Mar 26, 2012 at 05:28:55PM +0200, Alex Gershgorin wrote:
> On Mon, Mar 26, 2012 at 04:36:33PM +0200, Alex Gershgorin wrote:

> It's not quite true, I was based on the Freescale BSP and I assume,
> that this is checked.  I also tested it on v3.3

> > Uh, presence in a vendor BSP isn't a guarantee of sanity...  Since you
> > didn't specify any consumers the regulator API obviously won't do
> > anything with the voltage range provided but to repeat it's really not
> > at all obvious that anything sane ever would.

Thanks Mark I think that understand you,
if not have consumers do not set ranges.
I will correct it

Thanks 
Alex Gershgorin





From rubini at gnudd.com  Mon Mar 26 16:32:09 2012
From: rubini at gnudd.com (Alessandro Rubini)
Date: Mon, 26 Mar 2012 22:32:09 +0200
Subject: [PATCH] amba-pl011: fix panic introduced by "clear pending interrupts"
Message-ID: <20120326203209.GA8182@mail.gnudd.com>

patch 9b96fba, currently in linux-next, clears interrupts using
uap->port.membase that has not been assigned.  My x86 system,
that uses a pci-to-amba bridge, panics with a message like:

   BUG: unable to handle kernel NULL pointer dereference at 00000038
   IP: [<c12c85ed>] pl011_probe+0x119/0x303

Signed-off-by: Alessandro Rubini <rubini at gnudd.com>
Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi at st.com>
---
 drivers/tty/serial/amba-pl011.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 2b4e981..38c992d 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1947,8 +1947,8 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 	}
 
 	/* Ensure interrupts from this UART are masked and cleared */
-	writew(0, uap->port.membase + UART011_IMSC);
-	writew(0xffff, uap->port.membase + UART011_ICR);
+	writew(0, base + UART011_IMSC);
+	writew(0xffff, base + UART011_ICR);
 
 	uap->vendor = vendor;
 	uap->lcrh_rx = vendor->lcrh_rx;
-- 
1.7.7.2


From khilman at ti.com  Mon Mar 26 18:07:22 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 26 Mar 2012 15:07:22 -0700
Subject: [PATCH 6/6] ARM: OMAP: fix cpufreq build
In-Reply-To: <20120326083256.GC22608@n2100.arm.linux.org.uk> (Russell King's
 message of "Mon, 26 Mar 2012 09:32:56 +0100")
References: <20120315102845.GB16389@n2100.arm.linux.org.uk>
 <E1S87xU-0000N8-6u@rmk-PC.arm.linux.org.uk>
 <20120326083256.GC22608@n2100.arm.linux.org.uk>
Message-ID: <87ehsfrp7p.fsf@ti.com>

Russell King - ARM Linux <linux at arm.linux.org.uk> writes:

> Kevin,
>
> I only just found this via the arm-soc tree, while trying to merge the
> kautobuildv2 build tree.
>
> You changed my patch and broke it:
>
> config ARM_OMAP2PLUS_CPUFREQ
>         bool "TI OMAP2+"
>         default ARCH_OMAP2PLUS
>         select CPU_FREQ_TABLE
>
> So now, OMAP2 CPUFREQ is selectable on ANYTHING but it will only build
> successfully on OMAP.

Yes, I screwed it up.

I wanted it to be selectable, but majorly screwed it up and it is
certainly not randconfig friendly.

This was also pointed out by Grazvydas soon after merging[1], and I was
expecting a patch from him to remedy that, but I will take care of it
and submit a patch for v3.4-rc right away.
 
> If you're going to change someone elses patch, do them the favour of
> re-posting it back to them for comment *BEFORE* you commit it and send
> it upstream, 

I did.  On Feb 16th, I posted my modified version with you and
linux-arm-kernel Cc'd:

   http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/085053.html

and then I didn't send the pull request for this for another 3 weeks.

> rather than making it look like they're a total tosser for
> authoring a patch which fucks up other architecture builds.

/me has cache miss on tosser in American jargon cache
/me looks up in urban dictionary.

> Many thanks for that.

Many apologies.

Kevin

[1] http://marc.info/?l=linux-omap&m=133174677506294&w=2



From khilman at ti.com  Mon Mar 26 19:09:07 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 26 Mar 2012 16:09:07 -0700
Subject: [PATCH 9/9] ARM: omap: select CPU_FREQ_TABLE where needed
In-Reply-To: <20120323182746.GF9859@atomide.com> (Tony Lindgren's message of
 "Fri, 23 Mar 2012 11:27:46 -0700")
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
 <1332522836-29517-10-git-send-email-mathieu.poirier@linaro.org>
 <20120323182746.GF9859@atomide.com>
Message-ID: <87limnq7sb.fsf@ti.com>

Tony Lindgren <tony at atomide.com> writes:

> * mathieu.poirier at linaro.org <mathieu.poirier at linaro.org> [120323 10:17]:
>> From: Arnd Bergmann <arnd at arndb.de>
>> 
>> The omap platform requires CPU_FREQ_TABLE support to be enabled for its
>> CPU_FREQ implementations, so automatically select that when CPU_FREQ
>> is enabled.
>
> I think this is also solved now, Kevin might be able to confirm this.

Yes, this is solved in mainline by selecting it from
drivers/cpufreq/Kconfig.arm

Kevin


From khilman at ti.com  Mon Mar 26 20:05:17 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 26 Mar 2012 17:05:17 -0700
Subject: arm-soc/next/boards: mis-merge breaks build on OMAP4/Panda
Message-ID: <877gy6rjr6.fsf@ti.com>

Hi Arnd,

Looks like a conflict resolution in next/boards is causing a build
failure for OMAP4/Panda in arm-soc/for-next.

This merge:

  Merge tag 'asoc-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into next/boards

broke the build on OMAP4/Panda due to a missing ';' at the end of the
newly added panda_abe_audio platform_device.

Since you already sent the pull request to Linus, here's a patch on top
of next/boards to fix it.

Kevin

>From 3180f1d289b80dbe63f38931edd1245f10b619a0 Mon Sep 17 00:00:00 2001
From: Kevin Hilman <khilman at ti.com>
Date: Mon, 26 Mar 2012 16:57:40 -0700
Subject: [PATCH] ARM: OMAP4: Panda: fix mis-merge build error

Merging some board changes from the ASoC tree with some board fixes
from the OMAP tree resulted in a minor mis-merge causing build failure
on OMAP4/Panda.  Fix it.

Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/board-omap4panda.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 7459844..7866749 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -114,7 +114,7 @@ static struct platform_device panda_abe_audio = {
 	.dev = {
 		.platform_data = &panda_abe_audio_data,
 	},
-}
+};
 
 static struct platform_device btwilink_device = {
 	.name	= "btwilink",
-- 
1.7.9.2







From pullip.cho at samsung.com  Mon Mar 26 20:08:25 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Tue, 27 Mar 2012 09:08:25 +0900
Subject: [PATCH v12 3/3] iommu/exynos: Add iommu driver for Exynos
 Platforms
In-Reply-To: <001401cd0b4f$bbf0e120$33d2a360$%szyprowski@samsung.com>
References: <000301cd0286$2f4310d0$8dc93270$%cho@samsung.com>
 <001401cd0b4f$bbf0e120$33d2a360$%szyprowski@samsung.com>
Message-ID: <CAHQjnONY9f6jNLWGH+JtVOfWT42YHJxMdHtEGnDoqAL3B0M-yQ@mail.gmail.com>

On Mon, Mar 26, 2012 at 9:55 PM, Marek Szyprowski
<m.szyprowski at samsung.com> wrote:
> Hello,
>
> I'm sorry for a delay, I was quite busy recently, but I have finally found some
> time to review the code.
No problem. Thank you.

>
> On Thursday, March 15, 2012 9:33 AM Cho KyongHo wrote:
>
>> This is the System MMU driver and IOMMU API implementation for
>> Exynos SOC platforms. Exynos platforms has more than 10 System
>> MMUs dedicated for each multimedia accelerators.
>>
>> The System MMU driver is already in arc/arm/plat-s5p but it is
>> moved to drivers/iommu due to Ohad Ben-Cohen gathered IOMMU drivers
>> there
>>
>> Any device driver in Exynos platforms that needs to control its
>> System MMU must call platform_set_sysmmu() to inform System MMU
>> driver who will control it.
>> platform_set_sysmmu() is defined in <mach/sysmmu.h>
>>
>> Cc: Joerg Roedel <joerg.roedel at amd.com>
>> Cc: Kukjin Kim <kgene.kim at samsung.com>
>> Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
>
>
> (snipped)
>
>> diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
>> new file mode 100644
>> index 0000000..b8daf7c
>> --- /dev/null
>> +++ b/drivers/iommu/exynos-iommu.c
>> @@ -0,0 +1,1057 @@
>> +/* linux/drivers/iommu/exynos_iommu.c
>> + *
>> + * Copyright (c) 2011 Samsung Electronics Co., Ltd.
>> + * ? ? ? ? ? http://www.samsung.com
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>
> (snipped)
>
>> +static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
>> +{
>> + ? ? /* SYSMMU is in blocked when interrupt occurred. */
>> + ? ? struct sysmmu_drvdata *data = dev_id;
>> + ? ? struct resource *irqres;
>> + ? ? struct platform_device *pdev;
>> + ? ? enum exynos_sysmmu_inttype itype;
>> + ? ? unsigned long addr = -1;
>> +
>> + ? ? int i, ret = -ENOSYS;
>> +
>> + ? ? read_lock(&data->lock);
>> +
>> + ? ? WARN_ON(!is_sysmmu_active(data));
>> +
>> + ? ? pdev = to_platform_device(data->sysmmu);
>> + ? ? for (i = 0; i < pdev->num_resources; i++) {
>> + ? ? ? ? ? ? irqres = platform_get_resource(pdev, IORESOURCE_IRQ, i);
>> + ? ? ? ? ? ? if (irqres && ((int)irqres->start == irq))
>> + ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? }
>> +
>> + ? ? if (i == pdev->num_resources) {
>> + ? ? ? ? ? ? itype = SYSMMU_FAULT_UNKNOWN;
>> + ? ? } else {
>> + ? ? ? ? ? ? i /= 2;
>> +
>> + ? ? ? ? ? ? itype = (enum exynos_sysmmu_inttype)
>> + ? ? ? ? ? ? ? ? ? ? __ffs(__raw_readl(data->sfrbases[i] + REG_INT_STATUS));
>> + ? ? ? ? ? ? if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
>> + ? ? ? ? ? ? ? ? ? ? itype = SYSMMU_FAULT_UNKNOWN;
>> + ? ? ? ? ? ? else
>> + ? ? ? ? ? ? ? ? ? ? addr = __raw_readl(
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->sfrbases[i] + fault_reg_offset[itype]);
>> + ? ? }
>> +
>> + ? ? if (data->domain)
>> + ? ? ? ? ? ? ret = report_iommu_fault(data->domain, data->dev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? addr, itype);
>> +
>> + ? ? if ((ret == -ENOSYS) && data->fault_handler) {
>> + ? ? ? ? ? ? unsigned long base = data->pgtable;
>> + ? ? ? ? ? ? if (itype != SYSMMU_FAULT_UNKNOWN)
>> + ? ? ? ? ? ? ? ? ? ? base = __raw_readl(
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->sfrbases[i] + REG_PT_BASE_ADDR);
>> + ? ? ? ? ? ? ret = data->fault_handler(itype, base, addr);
>> + ? ? }
>> +
>> + ? ? if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
>> + ? ? ? ? ? ? __raw_writel(1 << itype, data->sfrbases[i] + REG_INT_CLEAR);
>> + ? ? else
>> + ? ? ? ? ? ? dev_dbg(data->sysmmu, "(%s) %s is not handled.\n",
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->dbgname, sysmmu_fault_name[itype]);
>> +
>> + ? ? if (itype != SYSMMU_FAULT_UNKNOWN)
>> + ? ? ? ? ? ? sysmmu_unblock(data->sfrbases[i]);
>> +
>> + ? ? read_unlock(&data->lock);
>> +
>> + ? ? return IRQ_HANDLED;
>> +}
>
> (snipped)
>
>> +static int exynos_sysmmu_probe(struct platform_device *pdev)
>> +{
>> + ? ? int i, ret;
>> + ? ? struct device *dev;
>> + ? ? struct sysmmu_drvdata *data;
>> +
>> + ? ? dev = &pdev->dev;
>> +
>> + ? ? data = kzalloc(sizeof(*data), GFP_KERNEL);
>> + ? ? if (!data) {
>> + ? ? ? ? ? ? dev_dbg(dev, "Not enough memory\n");
>> + ? ? ? ? ? ? ret = -ENOMEM;
>> + ? ? ? ? ? ? goto err_alloc;
>> + ? ? }
>> +
>> + ? ? ret = dev_set_drvdata(dev, data);
>> + ? ? if (ret) {
>> + ? ? ? ? ? ? dev_dbg(dev, "Unabled to initialize driver data\n");
>> + ? ? ? ? ? ? goto err_init;
>> + ? ? }
>> +
>> + ? ? data->nsfrs = pdev->num_resources / 2;
>> + ? ? data->sfrbases = kmalloc(sizeof(*data->sfrbases) * data->nsfrs,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? GFP_KERNEL);
>> + ? ? if (data->sfrbases == NULL) {
>> + ? ? ? ? ? ? dev_dbg(dev, "Not enough memory\n");
>> + ? ? ? ? ? ? ret = -ENOMEM;
>> + ? ? ? ? ? ? goto err_init;
>> + ? ? }
>> +
>> + ? ? for (i = 0; i < data->nsfrs; i++) {
>> + ? ? ? ? ? ? struct resource *res;
>> + ? ? ? ? ? ? res = platform_get_resource(pdev, IORESOURCE_MEM, i);
>> + ? ? ? ? ? ? if (!res) {
>> + ? ? ? ? ? ? ? ? ? ? dev_dbg(dev, "Unable to find IOMEM region\n");
>> + ? ? ? ? ? ? ? ? ? ? ret = -ENOENT;
>> + ? ? ? ? ? ? ? ? ? ? goto err_res;
>> + ? ? ? ? ? ? }
>> +
>> + ? ? ? ? ? ? data->sfrbases[i] = ioremap(res->start, resource_size(res));
>> + ? ? ? ? ? ? if (!data->sfrbases[i]) {
>> + ? ? ? ? ? ? ? ? ? ? dev_dbg(dev, "Unable to map IOMEM @ PA:%#x\n",
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? res->start);
>> + ? ? ? ? ? ? ? ? ? ? ret = -ENOENT;
>> + ? ? ? ? ? ? ? ? ? ? goto err_res;
>> + ? ? ? ? ? ? }
>> + ? ? }
>> +
>> + ? ? for (i = 0; i < data->nsfrs; i++) {
>> + ? ? ? ? ? ? ret = platform_get_irq(pdev, i);
>> + ? ? ? ? ? ? if (ret <= 0) {
>> + ? ? ? ? ? ? ? ? ? ? dev_dbg(dev, "Unable to find IRQ resource\n");
>> + ? ? ? ? ? ? ? ? ? ? goto err_irq;
>> + ? ? ? ? ? ? }
>> +
>> + ? ? ? ? ? ? ret = request_irq(ret, exynos_sysmmu_irq, 0,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dev_name(dev), data);
>> + ? ? ? ? ? ? if (ret) {
>> + ? ? ? ? ? ? ? ? ? ? dev_dbg(dev, "Unabled to register interrupt handler\n");
>> + ? ? ? ? ? ? ? ? ? ? goto err_irq;
>> + ? ? ? ? ? ? }
>> + ? ? }
>
> Please look at those loops and the interrupt function above. Those for-loops over
> all the resources looks really ugly and makes the driver less portable. The previous
> version (v8 afair) had much cleaned design.
>
I agree.
It might look unclear and the previous version is straightforward design.
For some devices like MFC and ISP, many system MMUs pretend
that they are a single device.

> It would be better not to squash multiple sysmmu controllers into a single instance
> of the driver. Please keep the driver simple. Sysmmu driver's resource should consist
> only of one io register area and one irq, nothing more. Such approach will remove
> the need for all that custom data in platform_data and it also make the future
> integration much easier for other non-samsung platforms (the sysmmu hardware is also
> used by other hw vendors). Support for device tree is also easier to add if the device
> driver is kept simple (supporting only one instance of the hardware block).
>
The current change that a single device descriptor for many System
MMUs keeps all other
parts of this device driver simpler. The only 2 parts of the driver,
probe() and interrupt handler
look unclear. A disadvantages of this change is that this driver needs
platform_data
and the definition of the data structure stored in the platform_data.

> The only reason I can see, which might have suggested you to squash hardware sysmmu
> controllers into one single instance was to provide the same virtual io mappings
> for all these sub-devices (it is mainly used by fims-isp complex block).
>
True.
But there is another reason, atomicity.
Enabling and disabling System MMU is in race condition. MFC driver
enables System MMU
before decoding a frame and disables it after decoding a frame, for example.
Enabling and disabling it can be performed in different process
contexts. System MMU is
enabled in normal context but disabled in interrupt context.
To protect enabling several system MMUs from racing, the entire region
that includes
from pm_runtime_get_sync() to accessing control registers must be
inside a spinlock
with IRQ disabled. Otherwise, a System MMU may be enabled while
another System MMU is
disabled at a moment even though they are in a block.
However, as you know, pm_runtime_get_sync() is a blocking function.

BTW, the problem can be solved in other way you may agree.

> This can be achieved in a much clearer design by using one, common iommu domain
> and attaching all these separate iommu controllers to it. Of course this will also
> require having a separate platform devices for each sub-device, but sooner or later
> you will need them anyway. The good example here is the MFC module, which already
> have separate devices: mfc_l and mfc_r for each memory controller.
>
Ok. I will look into MFC driver about your opinion.

>> + ? ? if (dev_get_platdata(dev)) {
>> + ? ? ? ? ? ? char *deli, *beg;
>> + ? ? ? ? ? ? struct sysmmu_platform_data *platdata = dev_get_platdata(dev);
>> +
>> + ? ? ? ? ? ? beg = platdata->clockname;
>> +
>> + ? ? ? ? ? ? for (deli = beg; (*deli != '\0') && (*deli != ','); deli++)
>> + ? ? ? ? ? ? ? ? ? ? /* NOTHING */;
>> +
>> + ? ? ? ? ? ? if (*deli == '\0')
>> + ? ? ? ? ? ? ? ? ? ? deli = NULL;
>> + ? ? ? ? ? ? else
>> + ? ? ? ? ? ? ? ? ? ? *deli = '\0';
>> +
>> + ? ? ? ? ? ? data->clk[0] = clk_get(dev, beg);
>> + ? ? ? ? ? ? if (IS_ERR(data->clk[0])) {
>> + ? ? ? ? ? ? ? ? ? ? data->clk[0] = NULL;
>> + ? ? ? ? ? ? ? ? ? ? dev_dbg(dev, "No clock descriptor registered\n");
>> + ? ? ? ? ? ? }
>> +
>> + ? ? ? ? ? ? if (data->clk[0] && deli) {
>> + ? ? ? ? ? ? ? ? ? ? *deli = ',';
>> + ? ? ? ? ? ? ? ? ? ? data->clk[1] = clk_get(dev, deli + 1);
>> + ? ? ? ? ? ? ? ? ? ? if (IS_ERR(data->clk[1]))
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? data->clk[1] = NULL;
>> + ? ? ? ? ? ? }
>> +
>> + ? ? ? ? ? ? data->dbgname = platdata->dbgname;
>> + ? ? }
>
> Passing clocks via platform data is also considered as a bad idea, especially if
> you need to parse string to extract the clock names. It would be much cleaner to
> have 2 (or more if required) variants of sysmmu driver, each one for a different
> version of the sysmmu hardware (I noticed only that some of the sysmmu units
> require one clock, the other require 2 clocks).

I agree. Thanks.
The reason of this approach is a block that has many System MMUs like ISP.
Their clock gating sources are spread into 2 control registers.

Thank you for review.

KyongHo


From khilman at ti.com  Mon Mar 26 20:19:28 2012
From: khilman at ti.com (Kevin Hilman)
Date: Mon, 26 Mar 2012 17:19:28 -0700
Subject: [PATCH] cpufreq: OMAP: fix build errors: depends on ARCH_OMAP2PLUS
Message-ID: <1332807568-638-1-git-send-email-khilman@ti.com>

The OMAP driver needs a 'depends on ARCH_OMAP2PLUS' since it only
builds for OMAP2+ platforms.

This 'depends on' was in the original patch from Russell King, but was
erroneously removed by me when making this option user-selectable in
commit b09db45c (cpufreq: OMAP driver depends CPUfreq tables.)  This
patch remedies that.

Apologies to Russell King for breaking his originally working patch.

Also, thanks to Grazvydas Ignotas for reporting the same problem.

Cc: Russell King <rmk+kernel at arm.linux.org.uk>
Cc: Grazvydas Ignotas <notasas at gmail.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
Dave, this applies on top of your current fixes branch, and fixes a 
problem introduced there by me.  Please merge for v3.4-rc.  Thanks.

 drivers/cpufreq/Kconfig.arm |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 82f1aa9..555a57b 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -4,6 +4,7 @@
 
 config ARM_OMAP2PLUS_CPUFREQ
 	bool "TI OMAP2+"
+	depends on ARCH_OMAP2PLUS
 	default ARCH_OMAP2PLUS
 	select CPU_FREQ_TABLE
 
-- 
1.7.9.2



From boojin.kim at samsung.com  Mon Mar 26 20:26:54 2012
From: boojin.kim at samsung.com (Boojin Kim)
Date: Tue, 27 Mar 2012 09:26:54 +0900
Subject: [PATCH 1/2] ARM: lib: Add optimized memcpy with 64 byte pld size
In-Reply-To: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
Message-ID: <00cf01cd0bb0$4fa49c30$eeedd490$%kim@samsung.com>

This patch adds the optimized memcpy() for the architecture that has 64 byte PLD size.

Signed-off-by: Boojin Kim <boojin.kim at samsung.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/Kconfig             |    7 ++++++
 arch/arm/lib/copy_template.S |   44 +++++++++++++++++++++++++++++++++--------
 2 files changed, 42 insertions(+), 9 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8fec56d..ba306b3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1132,6 +1132,13 @@ config ARM_NR_BANKS
 	default 16 if ARCH_EP93XX
 	default 8

+config ARM_PLD_SIZE
+	int
+	default 64 if ARCH_EXYNOS5
+	default 32
+	help
+	  Configure preload size used on memcpy(). Select 64 for cortex-a15.
+
 config IWMMXT
 	bool "Enable iWMMXt support"
 	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 805e3f8..7dc5b8c 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -66,6 +66,7 @@
  *	than one 32bit instruction in Thumb-2)
  */

+#define PLDSIZE	(CONFIG_ARM_PLD_SIZE)

 		enter	r4, lr

@@ -90,19 +91,44 @@
 	CALGN(	add	pc, r4, ip		)

 	PLD(	pld	[r1, #0]		)
-2:	PLD(	subs	r2, r2, #96		)
-	PLD(	pld	[r1, #28]		)
+
+#if (PLDSIZE == 64)
+2:	PLD(	cmp	r2, #32)
+	PLD(	blt	.32cpy)
+.64cpy:	PLD(	subs	r2, r2, #(PLDSIZE*3+32)	)
+	PLD(	pld	[r1, #PLDSIZE-4]	)
 	PLD(	blt	4f			)
-	PLD(	pld	[r1, #60]		)
-	PLD(	pld	[r1, #92]		)
+	PLD(	pld	[r1, #PLDSIZE*2-4]	)
+	PLD(	pld	[r1, #PLDSIZE*3-4]	)
+
+3:	PLD(	pld	[r1, #PLDSIZE*4-4]	)
+4:		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+		subs	r2, r2, #PLDSIZE
+		bge	3b
+	PLD(	cmn	r2, #(PLDSIZE*3)	)
+	PLD(	bge	4b			)
+	PLD(	cmn	r2, #(PLDSIZE*4-32)	)
+	PLD(	blt	5f)
+.32cpy:		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+#else
+2:	PLD(	subs	r2, r2, #(PLDSIZE*3)	)
+	PLD(	pld	[r1, #(PLDSIZE-4)]	)
+	PLD(	blt	4f			)
+	PLD(	pld	[r1, #(PLDSIZE*2-4)]	)
+	PLD(	pld	[r1, #(PLDSIZE*3-4)]	)

-3:	PLD(	pld	[r1, #124]		)
-4:		ldr8w	r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
-		subs	r2, r2, #32
-		str8w	r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+3:	PLD(	pld	[r1, #(PLDSIZE*4-4)]	)
+4:		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+		subs	r2, r2, #PLDSIZE
+		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
 		bge	3b
-	PLD(	cmn	r2, #96			)
+	PLD(	cmn	r2, #(PLDSIZE*3)	)
 	PLD(	bge	4b			)
+#endif

 5:		ands	ip, r2, #28
 		rsb	ip, ip, #32
--
1.7.1




From boojin.kim at samsung.com  Mon Mar 26 20:27:52 2012
From: boojin.kim at samsung.com (Boojin Kim)
Date: Tue, 27 Mar 2012 09:27:52 +0900
Subject: [PATCH 2/2] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
Message-ID: <00d501cd0bb0$724ab260$56e01720$%kim@samsung.com>

This patch uses LDRD/STRD that loads and stores data as DWORD unit.
It brings better performance than LDRM/STRM with cortex-a15.

Signed-off-by: Boojin Kim <boojin.kim at samsung.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/lib/copy_from_user.S |    9 +++++++++
 arch/arm/lib/copy_template.S  |   14 ++++++++------
 arch/arm/lib/copy_to_user.S   |    9 +++++++++
 arch/arm/lib/memcpy.S         |    9 +++++++++
 4 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
index 66a477a..dd1fe01 100644
--- a/arch/arm/lib/copy_from_user.S
+++ b/arch/arm/lib/copy_from_user.S
@@ -68,6 +68,15 @@
 	stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
 	.endm

+	.macro cpy8w dst src reg1 reg2 abort
+	.irp offset, #0, #8, #16, #24
+	ldr1w \src, \reg1, \abort
+	ldr1w \src, \reg2, \abort
+	strd \reg1, \reg2, [\dst, \offset]
+	.endr
+	add \dst, \dst, #32
+	.endm
+
 	.macro str1b ptr reg cond=al abort
 	str\cond\()b \reg, [\ptr], #1
 	.endm
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 7dc5b8c..a2dd5e2 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -47,6 +47,11 @@
  *	Same as their ldr* counterparts, but data is stored to 'ptr' location
  *	rather than being loaded.
  *
+ * cpy8w src dst reg1 reg2 abort
+ *
+ *	This loads eight words starting from 'src' and stores them to 'dst'.
+ *	The 'abort' argument is used for fixup tables.
+ *
  * enter reg1 reg2
  *
  *	Preserve the provided registers on the stack plus any additional
@@ -102,18 +107,15 @@
 	PLD(	pld	[r1, #PLDSIZE*3-4]	)

 3:	PLD(	pld	[r1, #PLDSIZE*4-4]	)
-4:		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
-		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
-		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
-		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+4:		cpy8w   r0, r1, r4, r5, abort=20f
+		cpy8w   r0, r1, r4, r5, abort=20f
 		subs	r2, r2, #PLDSIZE
 		bge	3b
 	PLD(	cmn	r2, #(PLDSIZE*3)	)
 	PLD(	bge	4b			)
 	PLD(	cmn	r2, #(PLDSIZE*4-32)	)
 	PLD(	blt	5f)
-.32cpy:		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
-		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+32copy:		cpy8w   r0, r1, r4, r5, abort=20f
 #else
 2:	PLD(	subs	r2, r2, #(PLDSIZE*3)	)
 	PLD(	pld	[r1, #(PLDSIZE-4)]	)
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index d066df6..fc8ea7a 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -71,6 +71,15 @@
 	str1w \ptr, \reg8, \abort
 	.endm

+	.macro cpy8w dst src reg1 reg2 abort
+	.irp offset, #0, #8, #16, #24
+	ldrd \reg1, \reg2, [\src, \offset]
+	str1w \dst, \reg1, \abort
+	str1w \dst, \reg2, \abort
+	.endr
+	add \src, \src, #32
+	.endm
+
 	.macro str1b ptr reg cond=al abort
 	strusr	\reg, \ptr, 1, \cond, abort=\abort
 	.endm
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index a9b9e22..5b4ca72 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -40,6 +40,15 @@
 	stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
 	.endm

+	.macro cpy8w dst src reg1 reg2 abort
+	.irp offset, #0, #8, #16, #24
+	ldrd \reg1, \reg2, [\src, \offset]
+	strd \reg1, \reg2, [\dst, \offset]
+	.endr
+	add \src, \src, #32
+	add \dst, \dst, #32
+	.endm
+
 	.macro str1b ptr reg cond=al abort
 	str\cond\()b \reg, [\ptr], #1
 	.endm
--
1.7.1





From nico at fluxnic.net  Mon Mar 26 22:35:37 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 26 Mar 2012 22:35:37 -0400 (EDT)
Subject: [PATCH 1/2] ARM: lib: Add optimized memcpy with 64 byte pld size
In-Reply-To: <00cf01cd0bb0$4fa49c30$eeedd490$%kim@samsung.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <00cf01cd0bb0$4fa49c30$eeedd490$%kim@samsung.com>
Message-ID: <alpine.LFD.2.02.1203262231220.24151@xanadu.home>

On Tue, 27 Mar 2012, Boojin Kim wrote:

> This patch adds the optimized memcpy() for the architecture that has 64 byte PLD size.
> 
> Signed-off-by: Boojin Kim <boojin.kim at samsung.com>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>

This creates quite convoluted code.  If this is worth doing, we'll have 
to find a cleaner way to do this.

Could you please provide performance measurement numbers with and 
without this patch, and similarly for the next patch?

Did you try enabling the cache alignment code?  What performance 
difference if any did you see?

> ---
>  arch/arm/Kconfig             |    7 ++++++
>  arch/arm/lib/copy_template.S |   44 +++++++++++++++++++++++++++++++++--------
>  2 files changed, 42 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 8fec56d..ba306b3 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1132,6 +1132,13 @@ config ARM_NR_BANKS
>  	default 16 if ARCH_EP93XX
>  	default 8
> 
> +config ARM_PLD_SIZE
> +	int
> +	default 64 if ARCH_EXYNOS5
> +	default 32
> +	help
> +	  Configure preload size used on memcpy(). Select 64 for cortex-a15.
> +
>  config IWMMXT
>  	bool "Enable iWMMXt support"
>  	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
> diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
> index 805e3f8..7dc5b8c 100644
> --- a/arch/arm/lib/copy_template.S
> +++ b/arch/arm/lib/copy_template.S
> @@ -66,6 +66,7 @@
>   *	than one 32bit instruction in Thumb-2)
>   */
> 
> +#define PLDSIZE	(CONFIG_ARM_PLD_SIZE)
> 
>  		enter	r4, lr
> 
> @@ -90,19 +91,44 @@
>  	CALGN(	add	pc, r4, ip		)
> 
>  	PLD(	pld	[r1, #0]		)
> -2:	PLD(	subs	r2, r2, #96		)
> -	PLD(	pld	[r1, #28]		)
> +
> +#if (PLDSIZE == 64)
> +2:	PLD(	cmp	r2, #32)
> +	PLD(	blt	.32cpy)
> +.64cpy:	PLD(	subs	r2, r2, #(PLDSIZE*3+32)	)
> +	PLD(	pld	[r1, #PLDSIZE-4]	)
>  	PLD(	blt	4f			)
> -	PLD(	pld	[r1, #60]		)
> -	PLD(	pld	[r1, #92]		)
> +	PLD(	pld	[r1, #PLDSIZE*2-4]	)
> +	PLD(	pld	[r1, #PLDSIZE*3-4]	)
> +
> +3:	PLD(	pld	[r1, #PLDSIZE*4-4]	)
> +4:		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> +		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> +		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> +		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> +		subs	r2, r2, #PLDSIZE
> +		bge	3b
> +	PLD(	cmn	r2, #(PLDSIZE*3)	)
> +	PLD(	bge	4b			)
> +	PLD(	cmn	r2, #(PLDSIZE*4-32)	)
> +	PLD(	blt	5f)
> +.32cpy:		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> +		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> +#else
> +2:	PLD(	subs	r2, r2, #(PLDSIZE*3)	)
> +	PLD(	pld	[r1, #(PLDSIZE-4)]	)
> +	PLD(	blt	4f			)
> +	PLD(	pld	[r1, #(PLDSIZE*2-4)]	)
> +	PLD(	pld	[r1, #(PLDSIZE*3-4)]	)
> 
> -3:	PLD(	pld	[r1, #124]		)
> -4:		ldr8w	r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> -		subs	r2, r2, #32
> -		str8w	r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> +3:	PLD(	pld	[r1, #(PLDSIZE*4-4)]	)
> +4:		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> +		subs	r2, r2, #PLDSIZE
> +		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
>  		bge	3b
> -	PLD(	cmn	r2, #96			)
> +	PLD(	cmn	r2, #(PLDSIZE*3)	)
>  	PLD(	bge	4b			)
> +#endif
> 
>  5:		ands	ip, r2, #28
>  		rsb	ip, ip, #32
> --
> 1.7.1
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


From skannan at codeaurora.org  Tue Mar 27 00:35:35 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Mon, 26 Mar 2012 21:35:35 -0700
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <4F694484.1030706@codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <20120320141811.GF32469@S2101-09.ap.freescale.net>
 <20120320181050.GN3852@pengutronix.de> <4F68E34A.70207@codeaurora.org>
 <20120320231242.GP3852@pengutronix.de>
 <CAJOA=zOGTW7OqACWgJQW6HSPLVev+apdNhv4vNXjHTcp=7N+uQ@mail.gmail.com>
 <4F694484.1030706@codeaurora.org>
Message-ID: <4F714397.6080608@codeaurora.org>

Mike,

(*nudge*) (*nudge*)

-Saravana


On 03/20/2012 08:01 PM, Saravana Kannan wrote:
> On 03/20/2012 06:47 PM, Turquette, Mike wrote:
>> On Tue, Mar 20, 2012 at 4:12 PM, Sascha Hauer<s.hauer at pengutronix.de>
>> wrote:
>>> On Tue, Mar 20, 2012 at 01:06:34PM -0700, Saravana Kannan wrote:
>>>> On 03/20/2012 11:10 AM, Sascha Hauer wrote:
>>>>> On Tue, Mar 20, 2012 at 10:18:14PM +0800, Shawn Guo wrote:
>>>>>> On Tue, Mar 20, 2012 at 10:40:31AM +0100, Sascha Hauer wrote:
>>>>>> ...
>>>>>>> I am using these functions and don't need a static array, I just
>>>>>>> call
>>>>>>> the functions with the desired parameters.
>>>>>>>
>>>>>> With this patch getting in, you do not have to use them then. I feel
>>>>>> a static array will be much more readable than a long list of
>>>>>> function
>>>>>> calls with a long list of hardcoded arguments to each.
>>>>>
>>>>> I'm also not a fan of long argument lists; a divider like defined
>>>>> in my
>>>>> tree takes 5 arguments, a gate 4 and a mux 6. While 6 is already at
>>>>> the
>>>>> border I think it's still acceptable.
>>>>>
>>>>> What I like in terms of readability is one line per clock which makes
>>>>> for quite short clock files.
>>>>
>>>> It certainly makes for short clock files, but it's definitely less
>>>> readable that the expanded struct. For the original author the "one
>>>> line per clock" looks readable since they wrote it. But for someone
>>>> looking at the code to modify it, the expanded one would be much
>>>> easier to read. Also, you can always declare your own macro if you
>>>> really want to follow the one line approach.
>>>>
>>>>> So when we use structs to initialize the clocks we'll probably have
>>>>> something like this:
>>>>>
>>>>> static struct clk_divider somediv = {
>>>>> .reg = CCM_BASE + 0x14,
>>>>> .width = 3,
>>>>> .shift = 17,
>>>>> .lock =&ccm_lock,
>>>>> .hw.parent = "someotherdiv",
>>>>> .hw.flags = CLK_SET_RATE_PARENT,
>>>>> };
>>>>
>>>> Taken from your patches:
>>>>
>>>> imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
>>>> ARRAY_SIZE(spll_sel_clks));
>>>>
>>>> Compare the struct to the one line call. Now tell me, what does "1"
>>>> represent? No clue. But in the struct, I can immediately tell what
>>>> each one of the parameters are.
>>>>
>>>> Anyway, my patch certainly isn't forcing you to use multiple lines.
>>>> So, hopefully this won't be a point of contention.
>>>>
>>>>> This will make a 4000 line file out of a 500 line file. Now when for
>>>>> some reason struct clk_divider changes we end with big patches. If the
>>>>> clk core gets a new fancy CLK_ flag which we want to have then again
>>>>> we end up with big patches. Then there's also the possibility that
>>>>> someone finds out that .lock and .hw.flags are common to all dividers
>>>>> and comes up with a #define DEFINE_CLK_DIVIDER again to share common
>>>>> fields.
>>>>
>>>> This patch won't prevent you from doing any of that. You can still
>>>> create macros for that (there are already one for that). Also, what
>>>> you are pointing out is a bigger problem for the current
>>>> clk_register() function since you might have to change the no. of
>>>> params of all the callers even if a new field is optional.
>>>>
>>>>> All this can be solved when we introduce a small wrapper function and
>>>>> use it in the clock files:
>>>>>
>>>>> static inline struct clk *imx_clk_divider(const char *name, const
>>>>> char *parent,
>>>>> void __iomem *reg, u8 shift, u8 width)
>>>>> {
>>>>> return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
>>>>> reg, shift, width, 0,&imx_ccm_lock);
>>>>> }
>>>>>
>>>>> It decouples us from the structs used by the clock framework, we can
>>>>> add our preferred flags and still can share common fields like the
>>>>> lock.
>>>>>
>>>>> While this was not the intention when I first converted from struct
>>>>> initializers to function initializers I am confident that it will make
>>>>> a good job.
>>>>
>>>> Now I'm confused -- it's not clear if you are leaning towards my
>>>> patch or away from it?
>>>
>>> There was a tendency to get rid of static initializers and I like the
>>> idea of not exposing any of the internally used members outside the
>>> clock framework.
>>
>> I'm with Sascha on this. I feel that dividing the interface strictly
>> into two halves is the best way.
>
> I addressed this concern in my earlier comments. We can make a copy or
> we can agree the fields I moved to clk_hw aren't really useful wrt
> writing hacky code and call it a day. Can you please clarify why neither
> of these options are acceptable?
>
>> I have an uneasy feeling about
>> exposing this stuff into struct clk_hw (or clk_initializer or
>> whatever). This stretches the data out across three structures and
>> just doesn't feel right to me.
>
> Wrt this discussion, there are three distinct classes of data:
> 1) Those specific to the platform driver that the common code shouldn't
> care about.
> 2) Those specific to the common code that the platform driver shouldn't
> care about.
> 3) Stuff that's shared/passed between common code and the platform driver.
>
> When we have three classes of data, I don't what's wrong with having
> three struct types to contain them. If anything, it's better than the
> current approach of exposing the common clock code specific data (struct
> clk) to code outside of common clock code just because we want to allow
> static initialization. The end goal should be to move struct clk inside
> clk.c.
>
> I think this patch just takes us one step close to that since IMX and
> MSM won't have to include clk-private.h in any of our platform specific
> files while also allowing OMAP to include it for the near term.
>
>>> Now people try their best to make themselves comfortable with the
>>> static initializers and you even discussed the possibility of removing
>>> the clk_register_* functions (which make it possible for users not
>>> to use any of the internal struct members). That's what I don't like
>>> about your patches. But if we go for static initializers anyway then
>>> your
>>> patches probably change things for the better.
>>
>> Static initialization is something I have fought for; in fact the
>> original patches provided no way to do it, so clearly what we have
>> today is some progress for the folks desiring static init.
>
> I too desire static init. Sorry if I was unclear and gave people the
> misconception that I wanted to remove static init.
>
>> The patch
>> above doesn't actually prevent allocation from happening as it still
>> must call into clk_register and kmalloc struct clk,
>
> Correct.
>
>> so besides
>> readability, I'm not sure what these patches buy us.
>
> I think readability is very important and if this buys us nothing but
> readability, we should still take this patch. But there are other
> benefits too -- I mentioned them in the commit text.
>
>> Assuming that C99 designated initializers (for the sole purpose of
>> readability) is the main draw of the above patch, please let me know
>> what you think about modifying the existing static init macros so that
>> your clock data looks like this:
>>
>> DEFINE_CLK_DIVIDER(dpll_iva_m5x2_ck,&dpll_iva_x2_ck, "dpll_iva_x2_ck",
>> .flags = 0x0,
>> .reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
>> .shift = OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT,
>> .width = OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH,
>> .flags = CLK_DIVIDER_ONE_BASED,
>> .lock = NULL
>> );
>>
>> Note that the first argument is the name of this clock (and will be
>> properly stringified for .name = "whatever") and that the second and
>> third arguments are both the parent clock, used for initializing the
>> parent pointer and .parent_names, respectively. If that aspect of the
>> macro is too ugly then those can even be broken out into a separate
>> macro since they are independent data structure (struct clk **parents,
>> and char **parent_names). Or you could just open code those data
>> structures and only use a macro for struct clk and struct clk_foo.
>>
>> This gives you the readability of C99 designated initializers while
>> keeping struct clk's members totally hidden from the rest of the
>> world.
>
> But it still leaves the struct clk exposed to people who do static init
> of the clock tree. I think agreeing that the name, parent names, flags
> and ops are not used to hack with or just making a copy of all of them
> (and mark the originals as __init if that's doable). is a better
> solution than trying to go with macros and leave struct clk exposed to
> everyone who want to do static init of the clock tree.
>
> At a later point when we are ready to move struct clk inside clk.c, with
> this patch applied right now, IMX and MSM won't have to churn their code.
>
> Thanks,
> Saravana
>


-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From afzal at ti.com  Tue Mar 27 00:24:49 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 27 Mar 2012 09:54:49 +0530
Subject: [RFC][PATCH v2 0/5] Convert GPMC to driver
Message-ID: <cover.1332771189.git.afzal@ti.com>


Hi,

Convert GPCM code to be a driver. Existing GPMC
NAND platform handling has been modified to work
with the new GPMC driver (patches 2 & 3). Patch 5
is to test the driver in OMAP3EVM.

TODO
1. Let NAND driver deal with GPMC NAND block
2. Remove struct gpmc * stored as static
3. Convert all peripherals to use GPMC driver
4. Devise method to handle OneNAND cleanly
5. Handle acquiring CS# cases
6. Decide on where GPMC driver should live
7. Adapt to HWMOD, use RPM
8. GPMC driver cleanup

Regards
Afzal

Afzal Mohammed (5):
  ARM: OMAP2+: gpmc: driver conversion
  ARM: OMAP2+: nand: create platform data structure
  ARM: OMAP2+: gpmc-nand: populate gpmc configs
  mtd: nand: omap2: obtain memory from resource
  OMAP3EVM: Test gpmc-nand

v2: Avoid code movement that kept similar code together (for easy review)

 arch/arm/mach-omap2/board-devkit8000.c     |    6 +-
 arch/arm/mach-omap2/board-flash.c          |   63 ++---
 arch/arm/mach-omap2/board-flash.h          |   13 +-
 arch/arm/mach-omap2/board-ldp.c            |    4 +-
 arch/arm/mach-omap2/board-omap3beagle.c    |    6 +-
 arch/arm/mach-omap2/board-omap3evm.c       |   82 +++++++
 arch/arm/mach-omap2/board-omap3touchbook.c |    6 +-
 arch/arm/mach-omap2/board-overo.c          |    5 +-
 arch/arm/mach-omap2/board-zoom.c           |    5 +-
 arch/arm/mach-omap2/common-board-devices.c |   46 ----
 arch/arm/mach-omap2/common-board-devices.h |    1 -
 arch/arm/mach-omap2/gpmc-nand.c            |   88 +++----
 arch/arm/mach-omap2/gpmc.c                 |  366 +++++++++++++++++++++-------
 arch/arm/plat-omap/include/plat/gpmc.h     |   34 ++-
 arch/arm/plat-omap/include/plat/nand.h     |    9 +-
 drivers/mtd/nand/omap2.c                   |   19 +-
 16 files changed, 502 insertions(+), 251 deletions(-)

-- 
1.7.9.3



From afzal at ti.com  Tue Mar 27 00:25:52 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 27 Mar 2012 09:55:52 +0530
Subject: [RFC][PATCH v2 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <cover.1332771189.git.afzal@ti.com>
References: <cover.1332771189.git.afzal@ti.com>
Message-ID: <c3b3832c04676a44c690854ef57728638f58173a.1332771189.git.afzal@ti.com>

Convert GPMC code to driver. Boards using GPMC should provide driver
with type of configuration, timing, CS, GPMC address space details
(if already configured, driver will retrieve, as is existing).
Platform devices would the be created for each connected peripheral
(details also to be passed by board so that it reaches respective
driver). And GPMC driver would populate memory resource details for
the driver of connected peripheral.

A peripheral connected to GPMC can have multiple address spaces using
different chip select. Hence GPMC driver has been provided capability
to distinguish this scenario, i.e. create platform devices only once
for each connected peripheral, and not for each configured chip
select. The peripheral that made it necessary was tusb6010.

Final destination for this driver is being investigated. Before moving
to the new location, all existing GPMC users has to be converted to
work with this driver.

NAND driver for NAND used via GPMC is tightly coupled with GPMC
driver (GPMC has few blocks exclusively for NAND), while that is not
the case for most of the other users (they need GPMCs help only for
initial configuration). Currently NAND driver manage using exported
GPMC symbols. This is being planned to remove later & would need
informing NAND driver about GPMC NAND registers. This would help to
have export symbol free GPMC driver, and probably
"mv omap2.c gpmc-nand.c" for OMAP NAND driver.
Thanks to Vaibhav Hiremath for his ideas on this.

Acquiring CS# for NAND is done on a few boards. It means, depending
on bootloader to embed this information. Probably CS# being used can
be set in the Kernel, and acquiring it can be removed. If ever this
capbility is needed, GPMC driver has to be made aware of handling it.

OneNAND - as it may involve reconfiguring GPMC for synchronous may
need a quirk to handle or driver has to be made more intelligent to
handle it.

Code related to GPMC clock may have to continue live in platform
folders (even if the driver is moved to MFD) as input clock is beyond
the control of GPMC and calculating timing for the peripheral may
need other helpers.

TODO
1. Let NAND driver deal with GPMC NAND block
2. Remove struct gpmc * stored as static
3. Convert all peripherals to use GPMC driver
4. Devise method to handle OneNAND cleanly
5. Handle acquiring CS# cases
6. Decide on where GPMC driver should live
7. Adapt to HWMOD, use RPM
8. GPMC driver cleanup

Cc: Vaibhav Hiremath <hvaibhav at ti.com>
Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
v2: Avoid code movement that kept similar code together

 arch/arm/mach-omap2/gpmc.c             |  366 ++++++++++++++++++++++++--------
 arch/arm/plat-omap/include/plat/gpmc.h |   34 ++-
 2 files changed, 305 insertions(+), 95 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 00d5108..8556153 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -14,8 +14,11 @@
  */
 #undef DEBUG
 
+#include <linux/platform_device.h>
+
 #include <linux/irq.h>
 #include <linux/kernel.h>
+#include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/err.h>
 #include <linux/clk.h>
@@ -64,6 +67,35 @@
 #define ENABLE_PREFETCH		(0x1 << 7)
 #define DMA_MPU_MODE		2
 
+#define	DRIVER_NAME	"omap-gpmc"
+
+struct gpmc_child {
+	char			*name;
+	int			id;
+	struct resource		*res;
+	unsigned		num_res;
+	struct resource		gpmc_res[GPMC_CS_NUM];
+	unsigned		gpmc_num_res;
+	void			*pdata;
+	unsigned		pdata_size;
+};
+
+struct gpmc {
+	struct device		*dev;
+	unsigned long		fclk_period;
+	void __iomem		*io_base;
+	unsigned long		phys_base;
+	u32			memsize;
+	unsigned		cs_map;
+	int			ecc_used;
+	spinlock_t		mem_lock;
+	struct resource		mem_root;
+	struct resource		cs_mem[GPMC_CS_NUM];
+	struct gpmc_child	child_device[GPMC_CS_NUM];
+	unsigned		num_child;
+	unsigned		num_device;
+};
+
 /* Structure to save gpmc cs context */
 struct gpmc_cs_config {
 	u32 config1;
@@ -91,58 +123,50 @@ struct omap3_gpmc_regs {
 	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 };
 
-static struct resource	gpmc_mem_root;
-static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
-static DEFINE_SPINLOCK(gpmc_mem_lock);
-static unsigned int gpmc_cs_map;	/* flag for cs which are initialized */
-static int gpmc_ecc_used = -EINVAL;	/* cs using ecc engine */
-
-static void __iomem *gpmc_base;
-
 static struct clk *gpmc_l3_clk;
 
-static irqreturn_t gpmc_handle_irq(int irq, void *dev);
+static struct gpmc *gpmc;
 
 static void gpmc_write_reg(int idx, u32 val)
 {
-	__raw_writel(val, gpmc_base + idx);
+	writel(val, gpmc->io_base + idx);
 }
 
 static u32 gpmc_read_reg(int idx)
 {
-	return __raw_readl(gpmc_base + idx);
+	return readl(gpmc->io_base + idx);
 }
 
 static void gpmc_cs_write_byte(int cs, int idx, u8 val)
 {
 	void __iomem *reg_addr;
 
-	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-	__raw_writeb(val, reg_addr);
+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+	writeb(val, reg_addr);
 }
 
 static u8 gpmc_cs_read_byte(int cs, int idx)
 {
 	void __iomem *reg_addr;
 
-	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-	return __raw_readb(reg_addr);
+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+	return readb(reg_addr);
 }
 
 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 {
 	void __iomem *reg_addr;
 
-	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-	__raw_writel(val, reg_addr);
+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+	writel(val, reg_addr);
 }
 
 u32 gpmc_cs_read_reg(int cs, int idx)
 {
 	void __iomem *reg_addr;
 
-	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-	return __raw_readl(reg_addr);
+	reg_addr = gpmc->io_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
+	return readl(reg_addr);
 }
 
 /* TODO: Add support for gpmc_fck to clock framework and use it */
@@ -332,7 +356,7 @@ static void gpmc_cs_disable_mem(int cs)
 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 }
 
-static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
+static __devinit void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 {
 	u32 l;
 	u32 mask;
@@ -351,23 +375,23 @@ static int gpmc_cs_mem_enabled(int cs)
 	return l & GPMC_CONFIG7_CSVALID;
 }
 
-int gpmc_cs_set_reserved(int cs, int reserved)
+static int gpmc_cs_set_reserved(int cs, int reserved)
 {
 	if (cs > GPMC_CS_NUM)
 		return -ENODEV;
 
-	gpmc_cs_map &= ~(1 << cs);
-	gpmc_cs_map |= (reserved ? 1 : 0) << cs;
+	gpmc->cs_map &= ~(1 << cs);
+	gpmc->cs_map |= (reserved ? 1 : 0) << cs;
 
 	return 0;
 }
 
-int gpmc_cs_reserved(int cs)
+static int gpmc_cs_reserved(int cs)
 {
 	if (cs > GPMC_CS_NUM)
 		return -ENODEV;
 
-	return gpmc_cs_map & (1 << cs);
+	return gpmc->cs_map & (1 << cs);
 }
 
 static unsigned long gpmc_mem_align(unsigned long size)
@@ -384,24 +408,25 @@ static unsigned long gpmc_mem_align(unsigned long size)
 	return size;
 }
 
-static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
+static __devinit
+int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 {
-	struct resource	*res = &gpmc_cs_mem[cs];
+	struct resource	*res = &gpmc->cs_mem[cs];
 	int r;
 
 	size = gpmc_mem_align(size);
-	spin_lock(&gpmc_mem_lock);
+	spin_lock(&gpmc->mem_lock);
 	res->start = base;
 	res->end = base + size - 1;
-	r = request_resource(&gpmc_mem_root, res);
-	spin_unlock(&gpmc_mem_lock);
+	r = request_resource(&gpmc->mem_root, res);
+	spin_unlock(&gpmc->mem_lock);
 
 	return r;
 }
 
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
-	struct resource *res = &gpmc_cs_mem[cs];
+	struct resource *res = &gpmc->cs_mem[cs];
 	int r = -1;
 
 	if (cs > GPMC_CS_NUM)
@@ -411,7 +436,7 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 	if (size > (1 << GPMC_SECTION_SHIFT))
 		return -ENOMEM;
 
-	spin_lock(&gpmc_mem_lock);
+	spin_lock(&gpmc->mem_lock);
 	if (gpmc_cs_reserved(cs)) {
 		r = -EBUSY;
 		goto out;
@@ -419,7 +444,7 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 	if (gpmc_cs_mem_enabled(cs))
 		r = adjust_resource(res, res->start & ~(size - 1), size);
 	if (r < 0)
-		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
+		r = allocate_resource(&gpmc->mem_root, res, size, 0, ~0,
 				      size, NULL, NULL);
 	if (r < 0)
 		goto out;
@@ -428,24 +453,24 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 	*base = res->start;
 	gpmc_cs_set_reserved(cs, 1);
 out:
-	spin_unlock(&gpmc_mem_lock);
+	spin_unlock(&gpmc->mem_lock);
 	return r;
 }
 EXPORT_SYMBOL(gpmc_cs_request);
 
 void gpmc_cs_free(int cs)
 {
-	spin_lock(&gpmc_mem_lock);
+	spin_lock(&gpmc->mem_lock);
 	if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
 		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
 		BUG();
-		spin_unlock(&gpmc_mem_lock);
+		spin_unlock(&gpmc->mem_lock);
 		return;
 	}
 	gpmc_cs_disable_mem(cs);
-	release_resource(&gpmc_cs_mem[cs]);
+	release_resource(&gpmc->cs_mem[cs]);
 	gpmc_cs_set_reserved(cs, 0);
-	spin_unlock(&gpmc_mem_lock);
+	spin_unlock(&gpmc->mem_lock);
 }
 EXPORT_SYMBOL(gpmc_cs_free);
 
@@ -668,7 +693,7 @@ int gpmc_prefetch_reset(int cs)
 }
 EXPORT_SYMBOL(gpmc_prefetch_reset);
 
-static void __init gpmc_mem_init(void)
+static __devinit void gpmc_mem_init(void)
 {
 	int cs;
 	unsigned long boot_rom_space = 0;
@@ -680,8 +705,8 @@ static void __init gpmc_mem_init(void)
 	/* In apollon the CS0 is mapped as 0x0000 0000 */
 	if (machine_is_omap_apollon())
 		boot_rom_space = 0;
-	gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
-	gpmc_mem_root.end = GPMC_MEM_END;
+	gpmc->mem_root.start = GPMC_MEM_START + boot_rom_space;
+	gpmc->mem_root.end = GPMC_MEM_END;
 
 	/* Reserve all regions that has been set up by bootloader */
 	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
@@ -697,27 +722,15 @@ static void __init gpmc_mem_init(void)
 
 static int __init gpmc_init(void)
 {
-	u32 l, irq;
-	int cs, ret = -EINVAL;
-	int gpmc_irq;
+	int ret = -EINVAL;
 	char *ck = NULL;
 
-	if (cpu_is_omap24xx()) {
+	if (cpu_is_omap24xx())
 		ck = "core_l3_ck";
-		if (cpu_is_omap2420())
-			l = OMAP2420_GPMC_BASE;
-		else
-			l = OMAP34XX_GPMC_BASE;
-		gpmc_irq = INT_34XX_GPMC_IRQ;
-	} else if (cpu_is_omap34xx()) {
+	else if (cpu_is_omap34xx())
 		ck = "gpmc_fck";
-		l = OMAP34XX_GPMC_BASE;
-		gpmc_irq = INT_34XX_GPMC_IRQ;
-	} else if (cpu_is_omap44xx()) {
+	else if (cpu_is_omap44xx())
 		ck = "gpmc_ck";
-		l = OMAP44XX_GPMC_BASE;
-		gpmc_irq = OMAP44XX_IRQ_GPMC;
-	}
 
 	if (WARN_ON(!ck))
 		return ret;
@@ -728,54 +741,221 @@ static int __init gpmc_init(void)
 		BUG();
 	}
 
-	gpmc_base = ioremap(l, SZ_4K);
-	if (!gpmc_base) {
-		clk_put(gpmc_l3_clk);
-		printk(KERN_ERR "Could not get GPMC register memory\n");
-		BUG();
+	clk_enable(gpmc_l3_clk);
+
+	return 0;
+}
+postcore_initcall(gpmc_init);
+
+static inline int __devinit gpmc_find_next_child_slot(void)
+{
+	return gpmc->num_child;
+}
+
+static int __devinit gpmc_match_child(char *name, int id)
+{
+	int i;
+	struct gpmc_child *p;
+
+	for (i = 0, p = gpmc->child_device; i < gpmc->num_child; i++, p++)
+		if (!strcmp(p->name, name) && (p->id == id))
+			return i;
+
+	return -ENOENT;
+}
+
+static __devinit int gpmc_setup_child(struct gpmc_device_pdata *gdp)
+{
+	struct gpmc_config *c;
+	int i, ret = 0;
+	struct resource res;
+	unsigned long start;
+
+	start = gdp->mem_start;
+
+	ret = gpmc_cs_request(gdp->cs, gdp->mem_size, &start);
+	if (IS_ERR_VALUE(ret)) {
+		dev_err(gpmc->dev, "error: gpmc request on CS: %u\n", gdp->cs);
+		return ret;
 	}
 
-	clk_enable(gpmc_l3_clk);
+	c = gdp->config;
+	if (!c) {
+		dev_err(gpmc->dev, "config not present for CS: %u\n", gdp->cs);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < gdp->num_config; c++, i++) {
+		ret = gpmc_cs_configure(gdp->cs, c->cmd, c->val);
+		if (IS_ERR_VALUE(ret)) {
+			dev_err(gpmc->dev, "invalid cmd or value on CS:	\
+			 %u: cmd: %d value: %d\n", gdp->cs, c->cmd, c->val);
+			return ret;
+		}
+	}
+
+	if (gdp->timing) {
+		ret = gpmc_cs_set_timings(gdp->cs, gdp->timing);
+		if (IS_ERR_VALUE(ret)) {
+			dev_err(gpmc->dev, "error: setting timing on CS: %d\n",
+								gdp->cs);
+			return ret;
+		}
+	}
+
+	res.start = start + gdp->mem_offset;
+	res.end = res.start + gdp->mem_size - 1;
+	res.flags = IORESOURCE_MEM;
+
+	i = gpmc_match_child(gdp->name, gdp->id);
+	/* i >= GPMC_CS_NUM can never happen, this is for compiler to shutup */
+	if (i >= 0 && i < GPMC_CS_NUM) {
+		int j;
+
+		j = gpmc->child_device[i].gpmc_num_res;
+		gpmc->child_device[i].gpmc_res[j] = res;
+	} else if (i == -ENOENT) {
+		i = gpmc_find_next_child_slot();
+		if (IS_ERR_VALUE(i)) {
+			dev_err(gpmc->dev, "error: childs exceeded\n");
+			return -ENODEV;
+		}
+		gpmc->child_device[i].name = gdp->name;
+		gpmc->child_device[i].id = gdp->id;
+		gpmc->child_device[i].pdata = gdp->pdata;
+		gpmc->child_device[i].pdata_size = gdp->pdata_size;
+		gpmc->child_device[i].gpmc_res[0] = res;
+	} else {
+		/* should never come here */
+		dev_err(gpmc->dev, "error: childs exceeded\n");
+		return -ENODEV;
+	}
+
+	gpmc->child_device[i].gpmc_num_res++;
+
+	return ret;
+}
+
+static __devinit int gpmc_create_child(int cnt)
+{
+	struct gpmc_child *p = gpmc->child_device + cnt;
+	int num = p->num_res + p->gpmc_num_res;
+	struct resource *res;
+
+	res = kzalloc(sizeof(struct resource) * num, GFP_KERNEL);
+	if (!res) {
+		dev_err(gpmc->dev, "error: allocating memory\n");
+		return -ENOMEM;
+	}
+
+	memcpy((char *)res, (const char *) p->gpmc_res,
+				sizeof(struct resource) * p->gpmc_num_res);
+	memcpy((char *)(res + p->gpmc_num_res), (const char *)p->res,
+				sizeof(struct resource) * p->num_res);
+
+	platform_device_register_resndata(gpmc->dev, p->name, p->id, res,
+						num, p->pdata, p->pdata_size);
+
+	return 0;
+}
+
+static __devinit int gpmc_probe(struct platform_device *pdev)
+{
+	u32 l;
+	int i;
+	int ret = -EINVAL;
+	struct resource *res = NULL;
+	struct gpmc_pdata *gp = dev_get_platdata(&pdev->dev);
+	struct gpmc_device_pdata *gdp = NULL;
+
+	gpmc = devm_kzalloc(&pdev->dev, sizeof(struct gpmc), GFP_KERNEL);
+	if (!gpmc) {
+		dev_err(&pdev->dev, "Failed to allocate memory\n");
+		return -ENOMEM;
+	}
+
+	gpmc->dev = &pdev->dev;
+	gpmc->fclk_period = gp->fclk_period;
+	gpmc->num_device = gp->num_device;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		ret = -ENOENT;
+		dev_err(gpmc->dev, "Failed to get resource: memory\n");
+		goto err_res;
+	}
+	gpmc->phys_base = res->start;
+	gpmc->memsize = resource_size(res);
+
+	if (request_mem_region(gpmc->phys_base,
+		gpmc->memsize, DRIVER_NAME) == NULL) {
+		ret = -ENOMEM;
+		dev_err(gpmc->dev, "Failed to request memory region\n");
+		goto err_mem;
+	}
+
+	gpmc->io_base = ioremap(gpmc->phys_base, gpmc->memsize);
+	if (!gpmc->io_base) {
+		ret = -ENOMEM;
+		dev_err(gpmc->dev, "Failed to ioremap memory\n");
+		goto err_remap;
+	}
+
+	gpmc->ecc_used = -EINVAL;
+	spin_lock_init(&gpmc->mem_lock);
+	platform_set_drvdata(pdev, gpmc);
 
 	l = gpmc_read_reg(GPMC_REVISION);
-	printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
-	/* Set smart idle mode and automatic L3 clock gating */
-	l = gpmc_read_reg(GPMC_SYSCONFIG);
-	l &= 0x03 << 3;
-	l |= (0x02 << 3) | (1 << 0);
-	gpmc_write_reg(GPMC_SYSCONFIG, l);
+	dev_info(gpmc->dev, "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
+
 	gpmc_mem_init();
 
-	/* initalize the irq_chained */
-	irq = OMAP_GPMC_IRQ_BASE;
-	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-		irq_set_chip_and_handler(irq, &dummy_irq_chip,
-						handle_simple_irq);
-		set_irq_flags(irq, IRQF_VALID);
-		irq++;
+	for (i = 0, gdp = gp->device_pdata; i < gp->num_device; gdp++, i++) {
+		ret = gpmc_setup_child(gdp);
+		if (IS_ERR_VALUE(ret))
+			dev_err(gpmc->dev, "gpmc setup on CS: %u failed\n",
+								gdp->cs);
+		else
+			gpmc->num_child++;
 	}
 
-	ret = request_irq(gpmc_irq,
-			gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
-	if (ret)
-		pr_err("gpmc: irq-%d could not claim: err %d\n",
-						gpmc_irq, ret);
+	/* XXX: This would get modified once MFD */
+	for (i = 0; i < gpmc->num_child; i++)
+		gpmc_create_child(i);
+
+	return ret;
+
+err_remap:
+	release_mem_region(gpmc->phys_base, gpmc->memsize);
+err_mem:
+err_res:
+	devm_kfree(&pdev->dev, gpmc);
 	return ret;
 }
-postcore_initcall(gpmc_init);
 
-static irqreturn_t gpmc_handle_irq(int irq, void *dev)
+static __devexit int gpmc_remove(struct platform_device *pdev)
 {
-	u8 cs;
+	struct gpmc *gpmc = platform_get_drvdata(pdev);
 
-	/* check cs to invoke the irq */
-	cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
-	if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
-		generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
+	platform_set_drvdata(pdev, NULL);
+	iounmap(gpmc->io_base);
+	release_mem_region(gpmc->phys_base, gpmc->memsize);
+	devm_kfree(&pdev->dev, gpmc);
 
-	return IRQ_HANDLED;
+	return 0;
 }
 
+static struct platform_driver gpmc_driver = {
+	.probe		= gpmc_probe,
+	.remove		= __devexit_p(gpmc_remove),
+	.driver		= {
+		.name	= DRIVER_NAME,
+		.owner	= THIS_MODULE,
+	},
+};
+
+module_platform_driver(gpmc_driver);
+
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_gpmc_regs gpmc_context;
 
@@ -855,10 +1035,10 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
 	unsigned int val;
 
 	/* check if ecc module is in used */
-	if (gpmc_ecc_used != -EINVAL)
+	if (gpmc->ecc_used != -EINVAL)
 		return -EINVAL;
 
-	gpmc_ecc_used = cs;
+	gpmc->ecc_used = cs;
 
 	/* clear ecc and enable bits */
 	val = ((0x00000001<<8) | 0x00000001);
@@ -906,7 +1086,7 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
 {
 	unsigned int val = 0x0;
 
-	if (gpmc_ecc_used != cs)
+	if (gpmc->ecc_used != cs)
 		return -EINVAL;
 
 	/* read ecc result */
@@ -916,7 +1096,7 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
 	/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
 	*ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
 
-	gpmc_ecc_used = -EINVAL;
+	gpmc->ecc_used = -EINVAL;
 	return 0;
 }
 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 1527929..1e02d85 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -131,6 +131,38 @@ struct gpmc_timings {
 	u16 wr_data_mux_bus;	/* WRDATAONADMUXBUS */
 };
 
+struct gpmc_config {
+	int cmd;
+	int val;
+};
+
+struct gpmc_device_pdata {
+	/* connected peripheral specific */
+	char			*name;
+	int			id;
+	/* resources configured via GPMC will be created by GPMC driver */
+	struct resource		*res;
+	unsigned		num_res;
+	void			*pdata;
+	unsigned		pdata_size;
+
+	/* GPMC specific */
+	unsigned		cs;
+	unsigned long		mem_size;
+	unsigned long		mem_start;
+	unsigned long		mem_offset;
+	struct gpmc_config	*config;
+	unsigned		num_config;
+	struct gpmc_timings	*timing;
+};
+
+struct gpmc_pdata {
+	/* GPMC_FCLK rate in picoseconds */
+	unsigned long			fclk_period;
+	struct gpmc_device_pdata	*device_pdata;
+	unsigned			num_device;
+};
+
 extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
 extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
@@ -143,8 +175,6 @@ extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
-extern int gpmc_cs_set_reserved(int cs, int reserved);
-extern int gpmc_cs_reserved(int cs);
 extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
 					unsigned int u32_count, int is_write);
 extern int gpmc_prefetch_reset(int cs);
-- 
1.7.9.3



From afzal at ti.com  Tue Mar 27 00:26:01 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 27 Mar 2012 09:56:01 +0530
Subject: [RFC][PATCH v2 2/5] ARM: OMAP2+: nand: create platform data structure
In-Reply-To: <cover.1332771189.git.afzal@ti.com>
References: <cover.1332771189.git.afzal@ti.com>
Message-ID: <9213eb1bfb683135172becdfe0c121c14ee40e7c.1332771189.git.afzal@ti.com>

New API for updating nand platform data. This has
been created by unifying the two existing ones and
taking out gpmc hardware handling.

>From now on, platforms can call omap_nand_init to
initialize platform nand structures, it's fields.
Or can statically create the same.

Acquiring gpmc CS has been removed. Acquiring CS
probably should be avoided, if ever required, do
in GPMC driver.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/board-devkit8000.c     |    6 ++-
 arch/arm/mach-omap2/board-flash.c          |   63 ++++++++++++++--------------
 arch/arm/mach-omap2/board-flash.h          |   13 ++++--
 arch/arm/mach-omap2/board-ldp.c            |    4 +-
 arch/arm/mach-omap2/board-omap3beagle.c    |    6 ++-
 arch/arm/mach-omap2/board-omap3touchbook.c |    6 ++-
 arch/arm/mach-omap2/board-overo.c          |    5 ++-
 arch/arm/mach-omap2/board-zoom.c           |    5 ++-
 arch/arm/mach-omap2/common-board-devices.c |   46 --------------------
 arch/arm/mach-omap2/common-board-devices.h |    1 -
 10 files changed, 61 insertions(+), 94 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 11cd2a8..1a9ce9d 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -59,6 +59,7 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
 #define OMAP_DM9000_GPIO_IRQ	25
@@ -648,8 +649,9 @@ static void __init devkit8000_init(void)
 
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
-	omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
-			     ARRAY_SIZE(devkit8000_nand_partitions));
+	omap_nand_init(devkit8000_nand_partitions,
+		ARRAY_SIZE(devkit8000_nand_partitions), GPMC_CS_NUM + 1,
+		NAND_BUSWIDTH_16, NULL);
 
 	/* Ensure SDRC pins are mux'd for self-refresh */
 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 0349fd2..26c70b8 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -108,45 +108,45 @@ __init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
 		defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 
 /* Note that all values in this struct are in nanoseconds */
-static struct gpmc_timings nand_timings = {
+struct gpmc_timings nand_default_timings[1] = {
+	{
+		.sync_clk = 0,
 
-	.sync_clk = 0,
+		.cs_on = 0,
+		.cs_rd_off = 36,
+		.cs_wr_off = 36,
 
-	.cs_on = 0,
-	.cs_rd_off = 36,
-	.cs_wr_off = 36,
+		.adv_on = 6,
+		.adv_rd_off = 24,
+		.adv_wr_off = 36,
 
-	.adv_on = 6,
-	.adv_rd_off = 24,
-	.adv_wr_off = 36,
+		.we_off = 30,
+		.oe_off = 48,
 
-	.we_off = 30,
-	.oe_off = 48,
+		.access = 54,
+		.rd_cycle = 72,
+		.wr_cycle = 72,
 
-	.access = 54,
-	.rd_cycle = 72,
-	.wr_cycle = 72,
-
-	.wr_access = 30,
-	.wr_data_mux_bus = 0,
+		.wr_access = 30,
+		.wr_data_mux_bus = 0,
+	},
 };
 
-static struct omap_nand_platform_data board_nand_data = {
-	.gpmc_t		= &nand_timings,
+static struct omap_nand_platform_data omap_nand_data = {
+	.gpmc_t		= nand_default_timings,
 };
 
-void
-__init board_nand_init(struct mtd_partition *nand_parts,
-			u8 nr_parts, u8 cs, int nand_type)
+struct omap_nand_platform_data *
+__init omap_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
+				int nand_type, struct gpmc_timings *gpmc_t)
 {
-	board_nand_data.cs		= cs;
-	board_nand_data.parts		= nand_parts;
-	board_nand_data.nr_parts	= nr_parts;
-	board_nand_data.devsize		= nand_type;
-
-	board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
-	board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
-	gpmc_nand_init(&board_nand_data);
+	omap_nand_data.cs		= cs;
+	omap_nand_data.parts		= nand_parts;
+	omap_nand_data.nr_parts		= nr_parts;
+	omap_nand_data.devsize		= nand_type;
+	omap_nand_data.gpmc_t		= gpmc_t;
+
+	return &omap_nand_data;
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
 
@@ -242,6 +242,7 @@ void __init board_flash_init(struct flash_partitions partition_info[],
 	if (nandcs > GPMC_CS_NUM)
 		pr_err("NAND: Unable to find configuration in GPMC\n");
 	else
-		board_nand_init(partition_info[2].parts,
-			partition_info[2].nr_parts, nandcs, nand_type);
+		omap_nand_init(partition_info[2].parts,
+			partition_info[2].nr_parts, nandcs,
+			nand_type, nand_default_timings);
 }
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index d25503a..1d3f039 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -39,11 +39,16 @@ static inline void board_flash_init(struct flash_partitions part[],
 
 #if defined(CONFIG_MTD_NAND_OMAP2) || \
 		defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-extern void board_nand_init(struct mtd_partition *nand_parts,
-					u8 nr_parts, u8 cs, int nand_type);
+extern struct gpmc_timings nand_default_timings[];
+extern struct omap_nand_platform_data *
+__init omap_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
+				int nand_type, struct gpmc_timings *gpmc_t);
 #else
-static inline void board_nand_init(struct mtd_partition *nand_parts,
-					u8 nr_parts, u8 cs, int nand_type)
+#define	nand_default_timings	NULL
+static inline struct omap_nand_platform_data *
+omap_nand_init(struct mtd_partition *nand_parts,
+		u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t)
 {
+	return NULL;
 }
 #endif
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d50a562a..c3f7220 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -420,8 +420,8 @@ static void __init omap_ldp_init(void)
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
 	usb_musb_init(NULL);
-	board_nand_init(ldp_nand_partitions,
-		ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
+	omap_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions),
+				ZOOM_NAND_CS, 0, nand_default_timings);
 
 	omap_hsmmc_init(mmc);
 	ldp_display_init();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7be8d65..f9beece 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -51,6 +51,7 @@
 #include "mux.h"
 #include "hsmmc.h"
 #include "pm.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
 /*
@@ -542,8 +543,9 @@ static void __init omap3_beagle_init(void)
 
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
-	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
-			     ARRAY_SIZE(omap3beagle_nand_partitions));
+	omap_nand_init(omap3beagle_nand_partitions,
+		ARRAY_SIZE(omap3beagle_nand_partitions), GPMC_CS_NUM + 1,
+		NAND_BUSWIDTH_16, NULL);
 
 	/* Ensure msecure is mux'd to be able to set the RTC. */
 	omap_mux_init_signal("sys_drm_msecure", OMAP_PIN_OFF_OUTPUT_HIGH);
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 8842e04..6a3e77e 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -51,6 +51,7 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
 #include <asm/setup.h>
@@ -369,8 +370,9 @@ static void __init omap3_touchbook_init(void)
 	omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
-	omap_nand_flash_init(NAND_BUSWIDTH_16, omap3touchbook_nand_partitions,
-			     ARRAY_SIZE(omap3touchbook_nand_partitions));
+	omap_nand_init(omap3touchbook_nand_partitions,
+		ARRAY_SIZE(omap3touchbook_nand_partitions), GPMC_CS_NUM + 1,
+		NAND_BUSWIDTH_16, NULL);
 
 	/* Ensure SDRC pins are mux'd for self-refresh */
 	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 668533e..28cbdb5 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -57,6 +57,7 @@
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
+#include "board-flash.h"
 #include "common-board-devices.h"
 
 #define OVERO_GPIO_BT_XGATE	15
@@ -509,8 +510,8 @@ static void __init overo_init(void)
 	omap_serial_init();
 	omap_sdrc_init(mt46h32m32lf6_sdrc_params,
 				  mt46h32m32lf6_sdrc_params);
-	omap_nand_flash_init(0, overo_nand_partitions,
-			     ARRAY_SIZE(overo_nand_partitions));
+	omap_nand_init(overo_nand_partitions,
+		ARRAY_SIZE(overo_nand_partitions), GPMC_CS_NUM + 1, 0, NULL);
 	usb_musb_init(NULL);
 	usbhs_init(&usbhs_bdata);
 	overo_spi_init();
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 5c20bcc..0faef81 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -114,8 +114,9 @@ static void __init omap_zoom_init(void)
 		usbhs_init(&usbhs_bdata);
 	}
 
-	board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
-						ZOOM_NAND_CS, NAND_BUSWIDTH_16);
+	omap_nand_init(zoom_nand_partitions,
+			ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS,
+			NAND_BUSWIDTH_16, nand_default_timings);
 	zoom_debugboard_init();
 	zoom_peripherals_init();
 
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 9498b0f..ab8702d 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -93,49 +93,3 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 {
 }
 #endif
-
-#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-static struct omap_nand_platform_data nand_data;
-
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
-				 int nr_parts)
-{
-	u8 cs = 0;
-	u8 nandcs = GPMC_CS_NUM + 1;
-
-	/* find out the chip-select on which NAND exists */
-	while (cs < GPMC_CS_NUM) {
-		u32 ret = 0;
-		ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-		if ((ret & 0xC00) == 0x800) {
-			printk(KERN_INFO "Found NAND on CS%d\n", cs);
-			if (nandcs > GPMC_CS_NUM)
-				nandcs = cs;
-		}
-		cs++;
-	}
-
-	if (nandcs > GPMC_CS_NUM) {
-		printk(KERN_INFO "NAND: Unable to find configuration "
-				 "in GPMC\n ");
-		return;
-	}
-
-	if (nandcs < GPMC_CS_NUM) {
-		nand_data.cs = nandcs;
-		nand_data.parts = parts;
-		nand_data.nr_parts = nr_parts;
-		nand_data.devsize = options;
-
-		printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-		if (gpmc_nand_init(&nand_data) < 0)
-			printk(KERN_ERR "Unable to register NAND device\n");
-	}
-}
-#else
-void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
-				 int nr_parts)
-{
-}
-#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index a0b4a428..72bb41b 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -10,6 +10,5 @@ struct ads7846_platform_data;
 
 void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 		       struct ads7846_platform_data *board_pdata);
-void omap_nand_flash_init(int opts, struct mtd_partition *parts, int n_parts);
 
 #endif /* __OMAP_COMMON_BOARD_DEVICES__ */
-- 
1.7.9.3



From afzal at ti.com  Tue Mar 27 00:26:09 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 27 Mar 2012 09:56:09 +0530
Subject: [RFC][PATCH v2 3/5] ARM: OMAP2+: gpmc-nand: populate gpmc configs
In-Reply-To: <cover.1332771189.git.afzal@ti.com>
References: <cover.1332771189.git.afzal@ti.com>
Message-ID: <fb1ef94abb901b4705dc8042cffe7de0b12f1987.1332771189.git.afzal@ti.com>

Currently gpmc is configured in platform for nand.
As configuring gpmc has been moved to gpmc driver,
populate details needed for the driver to configure
gpmc. gpmc driver would configure based on this
information.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/gpmc-nand.c        |   88 ++++++++++++--------------------
 arch/arm/plat-omap/include/plat/nand.h |    8 +--
 2 files changed, 39 insertions(+), 57 deletions(-)

diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 386dec8..acec0ea 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -21,24 +21,29 @@
 #include <plat/board.h>
 #include <plat/gpmc.h>
 
-static struct resource gpmc_nand_resource = {
-	.flags		= IORESOURCE_MEM,
+
+#define	GPMC_NAND_CONFIG_NUM	3
+
+static struct gpmc_config gpmc_nand_config[GPMC_NAND_CONFIG_NUM] = {
+	{ GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND},
 };
 
-static struct platform_device gpmc_nand_device = {
+static struct gpmc_device_pdata gpmc_nand_info = {
 	.name		= "omap2-nand",
 	.id		= 0,
-	.num_resources	= 1,
-	.resource	= &gpmc_nand_resource,
+	.config		= gpmc_nand_config,
+	.num_config	= ARRAY_SIZE(gpmc_nand_config),
 };
 
-static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
-{
-	struct gpmc_timings t;
-	int err;
+static struct gpmc_timings t;
 
-	if (!gpmc_nand_data->gpmc_t)
+static struct gpmc_timings *
+gpmc_nand_retime(struct omap_nand_platform_data *gpmc_nand_data)
+{
+	if (!gpmc_nand_data->gpmc_t) {
+		pr_warn("gpmc timings not provided\n");
 		return 0;
+	}
 
 	memset(&t, 0, sizeof(t));
 	t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk;
@@ -68,56 +73,31 @@ static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data
 	t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off);
 	t.wr_cycle  = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
 
-	/* Configure GPMC */
-	if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
-		gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
-	else
-		gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
-	gpmc_cs_configure(gpmc_nand_data->cs,
-			GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
-	err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
-	if (err)
-		return err;
-
-	return 0;
+	return &t;
 }
 
-int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
+struct gpmc_device_pdata *
+__init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
 {
-	int err	= 0;
-	struct device *dev = &gpmc_nand_device.dev;
+	gpmc_nand_info.pdata = gpmc_nand_data;
+	gpmc_nand_info.pdata_size = sizeof(*gpmc_nand_data);
 
-	gpmc_nand_device.dev.platform_data = gpmc_nand_data;
+	gpmc_nand_info.cs = gpmc_nand_data->cs;
+	gpmc_nand_info.mem_size = NAND_IO_SIZE;
 
-	err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
-				&gpmc_nand_data->phys_base);
-	if (err < 0) {
-		dev_err(dev, "Cannot request GPMC CS\n");
-		return err;
-	}
+	gpmc_nand_info.timing = gpmc_nand_retime(gpmc_nand_data);
 
-	 /* Set timings in GPMC */
-	err = omap2_nand_gpmc_retime(gpmc_nand_data);
-	if (err < 0) {
-		dev_err(dev, "Unable to set gpmc timings: %d\n", err);
-		return err;
-	}
-
-	/* Enable RD PIN Monitoring Reg */
-	if (gpmc_nand_data->dev_ready) {
-		gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
-	}
-
-	err = platform_device_register(&gpmc_nand_device);
-	if (err < 0) {
-		dev_err(dev, "Unable to register NAND device\n");
-		goto out_free_cs;
-	}
-
-	return 0;
+	gpmc_nand_config[1].cmd = GPMC_CONFIG_DEV_SIZE;
+	if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
+		gpmc_nand_config[1].val = 1;
+	else
+		gpmc_nand_config[1].val = 0;
 
-out_free_cs:
-	gpmc_cs_free(gpmc_nand_data->cs);
+	gpmc_nand_config[2].cmd = GPMC_CONFIG_RDY_BSY;
+	if (gpmc_nand_data->dev_ready)
+		gpmc_nand_config[2].val = 1;
+	else
+		gpmc_nand_config[2].val = 0;
 
-	return err;
+	return &gpmc_nand_info;
 }
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 67fc506..d2daeba 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -35,10 +35,12 @@ struct omap_nand_platform_data {
 #define	NAND_IO_SIZE	4
 
 #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-extern int gpmc_nand_init(struct omap_nand_platform_data *d);
+extern struct gpmc_device_pdata *
+gpmc_nand_init(struct omap_nand_platform_data *d);
 #else
-static inline int gpmc_nand_init(struct omap_nand_platform_data *d)
+static inline struct gpmc_device_pdata *
+gpmc_nand_init(struct omap_nand_platform_data *d)
 {
-	return 0;
+	return NULL;
 }
 #endif
-- 
1.7.9.3



From afzal at ti.com  Tue Mar 27 00:26:15 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 27 Mar 2012 09:56:15 +0530
Subject: [RFC][PATCH v2 4/5] mtd: nand: omap2: obtain memory from resource
In-Reply-To: <cover.1332771189.git.afzal@ti.com>
References: <cover.1332771189.git.afzal@ti.com>
Message-ID: <76fd4ed3e29d5f3e6d31fe4c3a570abbfc4cdb8f.1332771189.git.afzal@ti.com>

gpmc being converted to driver, provides drivers
of peripheral connected memory space used by the
peripheral as memory resource.

Modify nand omap driver to obtain memory detials
from resource structure.

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/plat-omap/include/plat/nand.h |    1 -
 drivers/mtd/nand/omap2.c               |   19 +++++++++++++++----
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index d2daeba..fa49fc4 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -26,7 +26,6 @@ struct omap_nand_platform_data {
 	bool			dev_ready;
 	int			gpmc_irq;
 	enum nand_io		xfer_type;
-	unsigned long		phys_base;
 	int			devsize;
 	enum omap_ecc           ecc_opt;
 };
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index b3a883e..f6c018e 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -118,6 +118,7 @@ struct omap_nand_info {
 
 	int				gpmc_cs;
 	unsigned long			phys_base;
+	unsigned long			mem_size;
 	struct completion		comp;
 	int				dma_ch;
 	int				gpmc_irq;
@@ -931,6 +932,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 	struct omap_nand_platform_data	*pdata;
 	int				err;
 	int				i, offset;
+	struct resource			*res;
 
 	pdata = pdev->dev.platform_data;
 	if (pdata == NULL) {
@@ -950,7 +952,6 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 	info->pdev = pdev;
 
 	info->gpmc_cs		= pdata->cs;
-	info->phys_base		= pdata->phys_base;
 
 	info->mtd.priv		= &info->nand;
 	info->mtd.name		= dev_name(&pdev->dev);
@@ -962,13 +963,23 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 	/* NAND write protect off */
 	gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
 
-	if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		err = -EINVAL;
+		dev_err(&pdev->dev, "error getting memory resource\n");
+		goto out_free_info;
+	}
+
+	info->phys_base = res->start;
+	info->mem_size = resource_size(res);
+
+	if (!request_mem_region(info->phys_base, info->mem_size,
 				pdev->dev.driver->name)) {
 		err = -EBUSY;
 		goto out_free_info;
 	}
 
-	info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
+	info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size);
 	if (!info->nand.IO_ADDR_R) {
 		err = -ENOMEM;
 		goto out_release_mem_region;
@@ -1109,7 +1120,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 	return 0;
 
 out_release_mem_region:
-	release_mem_region(info->phys_base, NAND_IO_SIZE);
+	release_mem_region(info->phys_base, info->mem_size);
 out_free_info:
 	kfree(info);
 
-- 
1.7.9.3



From afzal at ti.com  Tue Mar 27 00:26:22 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 27 Mar 2012 09:56:22 +0530
Subject: [TMP][PATCH v2 5/5] OMAP3EVM: Test gpmc-nand
In-Reply-To: <cover.1332771189.git.afzal@ti.com>
References: <cover.1332771189.git.afzal@ti.com>
Message-ID: <f0ca413f6b09bc36b4bf2f1ea16720f6a5e3e71a.1332771189.git.afzal@ti.com>

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
 arch/arm/mach-omap2/board-omap3evm.c |   82 ++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index a659e19..2695663 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -23,6 +23,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/leds.h>
 #include <linux/interrupt.h>
+#include <linux/mtd/nand.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -41,6 +42,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include <plat/nand.h>
 #include <plat/board.h>
 #include <plat/usb.h>
 #include "common.h"
@@ -52,6 +54,7 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
 #include "common-board-devices.h"
+#include "board-flash.h"
 
 #define OMAP3_EVM_TS_GPIO	175
 #define OMAP3_EVM_EHCI_VBUS	22
@@ -102,6 +105,9 @@ static void __init omap3_evm_get_revision(void)
 	}
 }
 
+#undef CONFIG_SMSC911X
+#undef CONFIG_SMSC911X_MODULE
+
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #include <plat/gpmc-smsc911x.h>
 
@@ -533,6 +539,41 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
 	.reset_gpio_port[2]  = -EINVAL
 };
 
+/*
+ * NAND
+ */
+static struct mtd_partition omap3_evm_nand_partitions[] = {
+	/* All the partition sizes are listed in terms of NAND block size */
+	{
+		.name		= "X-Loader-NAND",
+		.offset		= 0,
+		.size		= 4 * (64 * 2048),
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	{
+		.name		= "U-Boot-NAND",
+		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x80000 */
+		.size		= 10 * (64 * 2048),
+		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
+	},
+	{
+		.name		= "Boot Env-NAND",
+
+		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x1c0000 */
+		.size		= 6 * (64 * 2048),
+	},
+	{
+		.name		= "Kernel-NAND",
+		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x280000 */
+		.size		= 40 * (64 * 2048),
+	},
+	{
+		.name		= "File System - NAND",
+		.size		= MTDPART_SIZ_FULL,
+		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x780000 */
+	},
+};
+
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux omap35x_board_mux[] __initdata = {
 	OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
@@ -632,8 +673,30 @@ static void __init omap3_evm_wl12xx_init(void)
 #endif
 }
 
+static struct gpmc_pdata gpmc_data;
+
+static struct resource gpmc_resources[] = {
+	{
+		.start = OMAP34XX_GPMC_BASE,
+		.end   = OMAP34XX_GPMC_BASE + SZ_4K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device gpmc_device = {
+	.name		= "omap-gpmc",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(gpmc_resources),
+	.resource	= gpmc_resources,
+	.dev	= {
+		.platform_data = &gpmc_data,
+	}
+};
+
 static void __init omap3_evm_init(void)
 {
+	struct omap_nand_platform_data *nand_data;
+
 	omap3_evm_get_revision();
 
 	if (cpu_is_omap3630())
@@ -684,6 +747,25 @@ static void __init omap3_evm_init(void)
 	omap3evm_init_smsc911x();
 	omap3_evm_display_init();
 	omap3_evm_wl12xx_init();
+	/* NAND */
+	nand_data = omap_nand_init(omap3_evm_nand_partitions,
+			ARRAY_SIZE(omap3_evm_nand_partitions),
+			0, NAND_BUSWIDTH_16, nand_default_timings);
+	if (nand_data == NULL) {
+		pr_err("omap_nand_init() failed\n");
+		return;
+	}
+
+	gpmc_data.device_pdata = gpmc_nand_init(nand_data);
+	if (gpmc_data.device_pdata == NULL) {
+		pr_err("gpmc_nand_init() failed\n");
+		return;
+	}
+
+	gpmc_data.num_device++;
+	gpmc_data.fclk_period = gpmc_get_fclk_period();
+
+	platform_device_register(&gpmc_device);
 }
 
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
-- 
1.7.9.3



From afzal at ti.com  Tue Mar 27 01:12:07 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Tue, 27 Mar 2012 05:12:07 +0000
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <4F70AA82.3000204@ti.com>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
 <4F6D0569.6080203@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A9317BB895@DBDE01.ent.ti.com>
 <4F70AA82.3000204@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A9317BD6E2@DBDE01.ent.ti.com>

Hi Jon,

On Mon, Mar 26, 2012 at 23:12:26, Hunter, Jon wrote:
> Also, I don't see where the gpmc_child->res and gpmc_child->num_res are 
> actually used. Are these needed?

These are for the peripheral resources not in control of GPMC, like
gpio irq. These are copied in gpmc_create_child.

> > Gpmc_device_data is dedicated to each CS, gpmc_pdata is required
> > at least to inform driver about clock rate.
> 
> Ok, understood! So the struct gpmc_device_pdata only has a single 
> chip-select entry and so looking at the code you will have multiple 
> instances of this structure of a gpmc device that uses more than one 
> chip-select. Any reason you did it this way and not have a single pdata 
> struct for each device defining all chip-selects it uses?

When coding started, multiple CS for a peripheral was not taken into
consideration, later handling multiple CS was incorporated making it
this way. But your suggestion seems better to me, will see if code can
modified accordingly in later patch series (v2 already sent)

> 
> > Generally, as the change involved moving a lot of code, seems more reviews
> > are on those than the actual changes than what I intended to get reviewed,
> > next patch series will be modified not to move existing code, hence some
> > of your suggested changes may not be present in it, probably those to be
> > done as another cleanup patch.
> 
> Yes I understand. However, it is a good opportunity to clean some of 
> this up even if it is existing code :-)

Ok

Regards
Afzal


From afzal at ti.com  Tue Mar 27 01:19:32 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Tue, 27 Mar 2012 05:19:32 +0000
Subject: [TMP][PATCH 5/5] OMAP3EVM: Test gpmc-nand
In-Reply-To: <4F70ACB6.5070208@ti.com>
References: <1332484630-22181-1-git-send-email-afzal@ti.com>
 <4F70ACB6.5070208@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A9317BD700@DBDE01.ent.ti.com>

Hi Jon,

On Mon, Mar 26, 2012 at 23:21:50, Hunter, Jon wrote:
> I see this is marked as a temp patch, but this is actually needed to 
> register the device. Actually, we would need to do this for all boards, 
> right?

Yes, as NAND support on OMAP3EVM was not in mainline, made it TMP.
Once GPMC driver interfaces are acceptable, other boards too will
be modified accordingly.

> Rather than registering the device here, may be we should add a function 
> in arch/arm/mach-omap2/devices.c called "omap_gpmc_init()" that is 
> called from all of the boards files passing the pdata structure. Then 
> the omap_gmpc_init() function should use omap_device_build() API to 
> register the device. If you look at arch/arm/mach-omap2/devices.c you 
> can look at omap4_keyboard_init() as an example. Let me know if this is 
> clear.

Yes that is the final plan, i.e. once driver is ok, it has to be adapted
to HWMOD, and this will be taken care.

Regards
Afzal


From jtzhou at marvell.com  Tue Mar 27 01:25:16 2012
From: jtzhou at marvell.com (Jett.Zhou)
Date: Tue, 27 Mar 2012 13:25:16 +0800
Subject: [PATCH 1/3] regulator: add pre-regulator support for 88pm860x
Message-ID: <1332825916-2183-1-git-send-email-jtzhou@marvell.com>

Pre-regulator of 88pm8606 is mainly for support charging based on vbus,
it needs to be enabled for charging battery, and will be disabled in
some exception condition like over-temp.

Signed-off-by: Jett.Zhou <jtzhou at marvell.com>
---
 drivers/mfd/88pm860x-core.c  |   24 ++++++++++++++-
 drivers/regulator/88pm8607.c |   66 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/mfd/88pm860x.h |    1 +
 3 files changed, 90 insertions(+), 1 deletions(-)

diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c
index 17dfe9b..6953841 100644
--- a/drivers/mfd/88pm860x-core.c
+++ b/drivers/mfd/88pm860x-core.c
@@ -90,6 +90,10 @@ static struct resource charger_resources[] __devinitdata = {
 	{PM8607_IRQ_VCHG, PM8607_IRQ_VCHG, "vchg voltage",    IORESOURCE_IRQ,},
 };
 
+static struct resource preg_resources[] __devinitdata = {
+	{PM8606_ID_PREG,  PM8606_ID_PREG,  "preg",   IORESOURCE_IO,},
+};
+
 static struct resource rtc_resources[] __devinitdata = {
 	{PM8607_IRQ_RTC, PM8607_IRQ_RTC, "rtc", IORESOURCE_IRQ,},
 };
@@ -142,9 +146,19 @@ static struct mfd_cell codec_devs[] = {
 	{"88pm860x-codec", -1,},
 };
 
+static struct regulator_consumer_supply preg_supply[] = {
+	REGULATOR_SUPPLY("preg", NULL),
+};
+
+static struct regulator_init_data preg_init_data = {
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &preg_supply[0],
+};
+
 static struct mfd_cell power_devs[] = {
 	{"88pm860x-battery", -1,},
 	{"88pm860x-charger", -1,},
+	{"88pm860x-preg",    -1,},
 };
 
 static struct mfd_cell rtc_devs[] = {
@@ -655,7 +669,6 @@ static void __devinit device_power_init(struct pm860x_chip *chip,
 
 	if (pdata == NULL)
 		return;
-
 	power_devs[0].platform_data = pdata->power;
 	power_devs[0].pdata_size = sizeof(struct pm860x_power_pdata);
 	power_devs[0].num_resources = ARRAY_SIZE(battery_resources);
@@ -673,6 +686,15 @@ static void __devinit device_power_init(struct pm860x_chip *chip,
 			      &charger_resources[0], chip->irq_base);
 	if (ret < 0)
 		dev_err(chip->dev, "Failed to add charger subdev\n");
+
+	power_devs[2].platform_data = &preg_init_data;
+	power_devs[2].pdata_size = sizeof(struct regulator_init_data);
+	power_devs[2].num_resources = ARRAY_SIZE(preg_resources);
+	power_devs[2].resources = &preg_resources[0],
+	ret = mfd_add_devices(chip->dev, 0, &power_devs[2], 1,
+			      &preg_resources[0], chip->irq_base);
+	if (ret < 0)
+		dev_err(chip->dev, "Failed to add preg subdev\n");
 }
 
 static void __devinit device_onkey_init(struct pm860x_chip *chip,
diff --git a/drivers/regulator/88pm8607.c b/drivers/regulator/88pm8607.c
index 28b81ae..6165c63 100644
--- a/drivers/regulator/88pm8607.c
+++ b/drivers/regulator/88pm8607.c
@@ -23,6 +23,7 @@ struct pm8607_regulator_info {
 	struct pm860x_chip	*chip;
 	struct regulator_dev	*regulator;
 	struct i2c_client	*i2c;
+	struct i2c_client	*i2c_8606;
 
 	unsigned int	*vol_table;
 	unsigned int	*vol_suspend;
@@ -327,6 +328,35 @@ static int pm8607_is_enabled(struct regulator_dev *rdev)
 	return !!((unsigned char)ret & (1 << info->enable_bit));
 }
 
+static int pm8606_preg_enable(struct regulator_dev *rdev)
+{
+	struct pm8607_regulator_info *info = rdev_get_drvdata(rdev);
+
+	return pm860x_set_bits(info->i2c, info->enable_reg,
+			       1 << info->enable_bit, 0);
+}
+
+static int pm8606_preg_disable(struct regulator_dev *rdev)
+{
+	struct pm8607_regulator_info *info = rdev_get_drvdata(rdev);
+
+	return pm860x_set_bits(info->i2c, info->enable_reg,
+			       1 << info->enable_bit,
+			       1 << info->enable_bit);
+}
+
+static int pm8606_preg_is_enabled(struct regulator_dev *rdev)
+{
+	struct pm8607_regulator_info *info = rdev_get_drvdata(rdev);
+	int ret;
+
+	ret = pm860x_reg_read(info->i2c, info->enable_reg);
+	if (ret < 0)
+		return ret;
+
+	return !((unsigned char)ret & (1 << info->enable_bit));
+}
+
 static struct regulator_ops pm8607_regulator_ops = {
 	.set_voltage	= pm8607_set_voltage,
 	.get_voltage	= pm8607_get_voltage,
@@ -335,6 +365,25 @@ static struct regulator_ops pm8607_regulator_ops = {
 	.is_enabled	= pm8607_is_enabled,
 };
 
+static struct regulator_ops pm8606_preg_ops = {
+	.enable		= pm8606_preg_enable,
+	.disable	= pm8606_preg_disable,
+	.is_enabled	= pm8606_preg_is_enabled,
+};
+
+#define PM8606_PREG(ereg, ebit)						\
+{									\
+	.desc	= {							\
+		.name	= "PREG",					\
+		.ops	= &pm8606_preg_ops,				\
+		.type	= REGULATOR_CURRENT,				\
+		.id	= PM8606_ID_PREG,				\
+		.owner	= THIS_MODULE,					\
+	},								\
+	.enable_reg	= PM8606_##ereg,				\
+	.enable_bit	= (ebit),					\
+}
+
 #define PM8607_DVC(vreg, nbits, ureg, ubit, ereg, ebit)			\
 {									\
 	.desc	= {							\
@@ -393,6 +442,8 @@ static struct pm8607_regulator_info pm8607_regulator_info[] = {
 	PM8607_LDO(12,        LDO12, 0, 4, SUPPLIES_EN12, 5),
 	PM8607_LDO(13, VIBRATOR_SET, 1, 3,  VIBRATOR_SET, 0),
 	PM8607_LDO(14,        LDO14, 0, 3, SUPPLIES_EN12, 6),
+
+	PM8606_PREG(PREREGULATORB, 5),
 };
 
 static int __devinit pm8607_regulator_probe(struct platform_device *pdev)
@@ -419,6 +470,8 @@ static int __devinit pm8607_regulator_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 	info->i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion;
+	info->i2c_8606 = (chip->id == CHIP_PM8607) ? chip->companion :
+			chip->client;
 	info->chip = chip;
 
 	/* check DVC ramp slope double */
@@ -447,6 +500,18 @@ static int __devexit pm8607_regulator_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static struct platform_device_id pm8607_regulator_driver_ids[] = {
+	{
+		.name	= "88pm860x-regulator",
+		.driver_data	= 0,
+	}, {
+		.name	= "88pm860x-preg",
+		.driver_data	= 0,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(platform, pm8607_regulator_driver_ids);
+
 static struct platform_driver pm8607_regulator_driver = {
 	.driver		= {
 		.name	= "88pm860x-regulator",
@@ -454,6 +519,7 @@ static struct platform_driver pm8607_regulator_driver = {
 	},
 	.probe		= pm8607_regulator_probe,
 	.remove		= __devexit_p(pm8607_regulator_remove),
+	.id_table	= pm8607_regulator_driver_ids,
 };
 
 static int __init pm8607_regulator_init(void)
diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index 92be347..26926fb 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -136,6 +136,7 @@ enum {
 	PM8607_ID_LDO13,
 	PM8607_ID_LDO14,
 	PM8607_ID_LDO15,
+	PM8606_ID_PREG,
 
 	PM8607_ID_RG_MAX,
 };
-- 
1.7.0.4



From jtzhou at marvell.com  Tue Mar 27 01:25:31 2012
From: jtzhou at marvell.com (Jett.Zhou)
Date: Tue, 27 Mar 2012 13:25:31 +0800
Subject: [PATCH 2/3] power_supply: Enable battery-charger for 88pm860x
Message-ID: <1332825931-2222-1-git-send-email-jtzhou@marvell.com>

There are charger and battery measurement feature for 88pm860x PMIC.

For charger, it can support pre-charge with small current when battery is
nearly exausted and then changed into fast-charge with CC&CV mode.

For battery monitor, it can support battery measurement such as
vbat,vsys,vchg and ibat etc,it can aslo accumulating the Coulomb value
charged or discharged from battery based on Conlomb Counter, we use it
to estimate battery capacity.

Signed-off-by: Jett.Zhou <jtzhou at marvell.com>
---
 drivers/mfd/88pm860x-core.c      |   24 +-
 drivers/power/88pm860x_battery.c | 1026 ++++++++++++++++++++++++++++++++++++++
 drivers/power/88pm860x_charger.c |  833 +++++++++++++++++++++++++++++++
 drivers/power/Kconfig            |   12 +
 drivers/power/Makefile           |    2 +
 include/linux/mfd/88pm860x.h     |   85 +++-
 6 files changed, 1978 insertions(+), 4 deletions(-)
 create mode 100644 drivers/power/88pm860x_battery.c
 create mode 100644 drivers/power/88pm860x_charger.c

diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c
index 6953841..b2132e9 100644
--- a/drivers/mfd/88pm860x-core.c
+++ b/drivers/mfd/88pm860x-core.c
@@ -18,6 +18,7 @@
 #include <linux/mfd/core.h>
 #include <linux/mfd/88pm860x.h>
 #include <linux/regulator/machine.h>
+#include <linux/power/charger-manager.h>
 
 #define INT_STATUS_NUM			3
 
@@ -84,7 +85,8 @@ static struct resource battery_resources[] __devinitdata = {
 static struct resource charger_resources[] __devinitdata = {
 	{PM8607_IRQ_CHG,  PM8607_IRQ_CHG,  "charger detect",  IORESOURCE_IRQ,},
 	{PM8607_IRQ_CHG_DONE,  PM8607_IRQ_CHG_DONE,  "charging done",       IORESOURCE_IRQ,},
-	{PM8607_IRQ_CHG_FAULT, PM8607_IRQ_CHG_FAULT, "charging timeout",    IORESOURCE_IRQ,},
+	{PM8607_IRQ_CHG_FAIL,  PM8607_IRQ_CHG_FAIL,  "charging timeout",    IORESOURCE_IRQ,},
+	{PM8607_IRQ_CHG_FAULT, PM8607_IRQ_CHG_FAULT, "charging fault",	    IORESOURCE_IRQ,},
 	{PM8607_IRQ_GPADC1,    PM8607_IRQ_GPADC1,    "battery temperature", IORESOURCE_IRQ,},
 	{PM8607_IRQ_VBAT, PM8607_IRQ_VBAT, "battery voltage", IORESOURCE_IRQ,},
 	{PM8607_IRQ_VCHG, PM8607_IRQ_VCHG, "vchg voltage",    IORESOURCE_IRQ,},
@@ -147,7 +149,7 @@ static struct mfd_cell codec_devs[] = {
 };
 
 static struct regulator_consumer_supply preg_supply[] = {
-	REGULATOR_SUPPLY("preg", NULL),
+	REGULATOR_SUPPLY("88pm860x-preg", NULL),
 };
 
 static struct regulator_init_data preg_init_data = {
@@ -155,10 +157,15 @@ static struct regulator_init_data preg_init_data = {
 	.consumer_supplies	= &preg_supply[0],
 };
 
+static struct regulator_bulk_data chg_desc_regulator_data[] = {
+	{ .supply = "88pm860x-preg", },
+};
+
 static struct mfd_cell power_devs[] = {
 	{"88pm860x-battery", -1,},
 	{"88pm860x-charger", -1,},
 	{"88pm860x-preg",    -1,},
+	{"charger-manager", -1,},
 };
 
 static struct mfd_cell rtc_devs[] = {
@@ -695,6 +702,19 @@ static void __devinit device_power_init(struct pm860x_chip *chip,
 			      &preg_resources[0], chip->irq_base);
 	if (ret < 0)
 		dev_err(chip->dev, "Failed to add preg subdev\n");
+
+	if (pdata->chg_desc) {
+		pdata->chg_desc->charger_regulators =
+			&chg_desc_regulator_data[0];
+		pdata->chg_desc->num_charger_regulators	=
+			ARRAY_SIZE(chg_desc_regulator_data),
+		power_devs[3].platform_data = pdata->chg_desc;
+		power_devs[3].pdata_size = sizeof(struct charger_desc);
+		ret = mfd_add_devices(chip->dev, 0, &power_devs[3], 1,
+				      NULL, chip->irq_base);
+		if (ret < 0)
+			dev_err(chip->dev, "Failed to add chg-manager subdev\n");
+	}
 }
 
 static void __devinit device_onkey_init(struct pm860x_chip *chip,
diff --git a/drivers/power/88pm860x_battery.c b/drivers/power/88pm860x_battery.c
new file mode 100644
index 0000000..132e2ee
--- /dev/null
+++ b/drivers/power/88pm860x_battery.c
@@ -0,0 +1,1026 @@
+/*
+ * Battery driver for Marvell 88PM860x PMIC
+ *
+ * Copyright (c) 2012 Marvell International Ltd.
+ * Author:	Jett Zhou <jtzhou at marvell.com>
+ *		Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/string.h>
+#include <linux/power_supply.h>
+#include <linux/mfd/88pm860x.h>
+#include <linux/delay.h>
+
+/* bit definitions of Status Query Interface 2 */
+#define STATUS2_CHG			(1 << 2)
+#define STATUS2_BAT			(1 << 3)
+#define STATUS2_VBUS			(1 << 4)
+
+/* bit definitions of Measurement Enable 1 Register */
+#define MEAS1_TINT			(1 << 3)
+#define MEAS1_GP1			(1 << 5)
+
+/* bit definitions of Measurement Enable 3 Register */
+#define MEAS3_IBAT			(1 << 0)
+#define MEAS3_BAT_DET			(1 << 1)
+#define MEAS3_CC			(1 << 2)
+
+/* bit definitions of Measurement Off Time Register */
+#define MEAS_OFF_SLEEP_EN		(1 << 1)
+
+/* bit definitions of GPADC Bias Current 2 Register */
+#define GPBIAS2_GPADC1_SET		(2 << 4)
+/* GPADC1 Bias Current value in uA unit */
+#define GPBIAS2_GPADC1_UA		((GPBIAS2_GPADC1_SET >> 4) * 5 + 1)
+
+/* bit definitions of GPADC Misc 1 Register */
+#define GPMISC1_GPADC_EN		(1 << 0)
+
+/* bit definitions of Charger Control 6 Register */
+#define CC6_BAT_DET_GPADC1		1
+
+/* bit definitions of Coulomb Counter Reading Register */
+#define CCNT_AVG_SEL			(4 << 3)
+
+/* bit definitions of RTC miscellaneous Register1 */
+#define RTC_SOC_5LSB		(0x1F << 3)
+
+/* bit definitions of RTC Register1 */
+#define RTC_SOC_3MSB		(0x7)
+
+/* bit definitions of Power up Log register */
+#define BAT_WU_LOG			(1<<6)
+
+/* coulomb counter index */
+#define CCNT_POS1			0
+#define CCNT_POS2			1
+#define CCNT_NEG1			2
+#define CCNT_NEG2			3
+#define CCNT_SPOS			4
+#define CCNT_SNEG			5
+
+/* OCV -- Open Circuit Voltage */
+#define OCV_MODE_ACTIVE			0
+#define OCV_MODE_SLEEP			1
+
+/* Vbat range of CC for measuring Rbat */
+#define LOW_BAT_THRESHOLD		3600
+#define VBATT_RESISTOR_MIN		3800
+#define VBATT_RESISTOR_MAX		4100
+
+/* TBAT for batt, TINT for chip itself */
+#define PM860X_TEMP_TINT		(0)
+#define PM860X_TEMP_TBAT		(1)
+
+/*
+ * Battery temperature based on NTC resistor, defined
+ * corresponding resistor value  -- Ohm / C degeree.
+ */
+#define TBAT_NEG_25D		127773	/* -25 */
+#define TBAT_NEG_10D		54564	/* -10 */
+#define TBAT_0D			32330	/* 0 */
+#define TBAT_10D		19785	/* 10 */
+#define TBAT_20D		12468	/* 20 */
+#define TBAT_30D		8072	/* 30 */
+#define TBAT_40D		5356	/* 40 */
+
+struct pm860x_battery_info {
+	struct pm860x_chip *chip;
+	struct i2c_client *i2c;
+	struct device *dev;
+
+	struct power_supply battery;
+	struct mutex lock;
+	int status;
+	int irq_cc;
+	int irq_batt;
+	int max_capacity;
+	int resistor;		/* Battery Internal Resistor */
+	int last_capacity;
+	int start_soc;
+	unsigned present:1;
+	unsigned temp_type:1;	/* TINT or TBAT */
+};
+
+struct ccnt {
+	unsigned long long int pos;
+	unsigned long long int neg;
+	unsigned int spos;
+	unsigned int sneg;
+
+	int total_chg;		/* mAh(3.6C) */
+	int total_dischg;	/* mAh(3.6C) */
+};
+
+/*
+ * State of Charge.
+ * The first number is mAh(=3.6C), and the second number is percent point.
+ */
+int array_soc[][2] = { {4170, 100},
+{4154, 99}, {4136, 98}, {4122, 97}, {4107, 96},
+{4102, 95}, {4088, 94}, {4081, 93}, {4070, 92},
+{4060, 91}, {4053, 90}, {4044, 89}, {4035, 88},
+{4028, 87}, {4019, 86}, {4013, 85}, {4006, 84},
+{3995, 83}, {3987, 82}, {3982, 81}, {3976, 80},
+{3968, 79}, {3962, 78}, {3954, 77}, {3946, 76},
+{3941, 75}, {3934, 74}, {3929, 73}, {3922, 72},
+{3916, 71}, {3910, 70}, {3904, 69}, {3898, 68},
+{3892, 67}, {3887, 66}, {3880, 65}, {3874, 64},
+{3868, 63}, {3862, 62}, {3854, 61}, {3849, 60},
+{3843, 59}, {3840, 58}, {3833, 57}, {3829, 56},
+{3824, 55}, {3818, 54}, {3815, 53}, {3810, 52},
+{3808, 51}, {3804, 50}, {3801, 49}, {3798, 48},
+{3796, 47}, {3792, 46}, {3789, 45}, {3785, 44},
+{3784, 43}, {3782, 42}, {3780, 41}, {3777, 40},
+{3776, 39}, {3774, 38}, {3772, 37}, {3771, 36},
+{3769, 35}, {3768, 34}, {3764, 33}, {3763, 32},
+{3760, 31}, {3760, 30}, {3754, 29}, {3750, 28},
+{3749, 27}, {3744, 26}, {3740, 25}, {3734, 24},
+{3732, 23}, {3728, 22}, {3726, 21}, {3720, 20},
+{3716, 19}, {3709, 18}, {3703, 17}, {3698, 16},
+{3692, 15}, {3683, 14}, {3675, 13}, {3670, 12},
+{3665, 11}, {3661, 10}, {3657, 9}, {3649, 8},
+{3637, 7}, {3622, 6}, {3609, 5}, {3580, 4},
+{3558, 3}, {3540, 2}, {3510, 1}, {3429, 0}
+};
+
+static struct ccnt ccnt_data;
+
+static int calc_ccnt(struct pm860x_battery_info *info, struct ccnt *ccnt);
+static int calc_soc(struct pm860x_battery_info *info, int state, int *soc);
+static int clear_ccnt(struct pm860x_battery_info *info, struct ccnt *ccnt);
+static int measure_current(struct pm860x_battery_info *info, int *data);
+
+static irqreturn_t pm860x_coulomb_handler(int irq, void *data)
+{
+	struct pm860x_battery_info *info = data;
+
+	calc_ccnt(info, &ccnt_data);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t pm860x_batt_handler(int irq, void *data)
+{
+	struct pm860x_battery_info *info = data;
+	int ret;
+
+	mutex_lock(&info->lock);
+	ret = pm860x_reg_read(info->i2c, PM8607_STATUS_2);
+	if (ret & STATUS2_BAT) {
+		info->present = 1;
+		info->temp_type = PM860X_TEMP_TBAT;
+	} else {
+		info->present = 0;
+		info->temp_type = PM860X_TEMP_TINT;
+	}
+	mutex_unlock(&info->lock);
+	/* clear ccnt since battery is attached or dettached */
+	clear_ccnt(info, &ccnt_data);
+	return IRQ_HANDLED;
+}
+
+static void pm860x_init_battery(struct pm860x_battery_info *info)
+{
+	unsigned char buf[2];
+	int ret, data;
+	int bat_remove, soc;
+
+	/* measure enable on GPADC1 */
+	data = MEAS1_GP1;
+	if (info->temp_type == PM860X_TEMP_TINT)
+		data |= MEAS1_TINT;
+	ret = pm860x_set_bits(info->i2c, PM8607_MEAS_EN1, data, data);
+	if (ret)
+		goto out;
+
+	/* measure enable on IBAT, BAT_DET, CC. IBAT is depend on CC. */
+	data = MEAS3_IBAT | MEAS3_BAT_DET | MEAS3_CC;
+	ret = pm860x_set_bits(info->i2c, PM8607_MEAS_EN3, data, data);
+	if (ret)
+		goto out;
+
+	/* measure disable CC in sleep time  */
+	ret = pm860x_reg_write(info->i2c, PM8607_MEAS_OFF_TIME1, 0x82);
+	if (ret)
+		goto out;
+	ret = pm860x_reg_write(info->i2c, PM8607_MEAS_OFF_TIME2, 0x6c);
+	if (ret)
+		goto out;
+
+	/* enable GPADC */
+	ret = pm860x_set_bits(info->i2c, PM8607_GPADC_MISC1,
+			    GPMISC1_GPADC_EN, GPMISC1_GPADC_EN);
+	if (ret < 0)
+		goto out;
+
+	/* detect battery via GPADC1 */
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL6,
+			    CC6_BAT_DET_GPADC1, CC6_BAT_DET_GPADC1);
+	if (ret < 0)
+		goto out;
+
+	ret = pm860x_set_bits(info->i2c, PM8607_CCNT, 7 << 3,
+			      CCNT_AVG_SEL);
+	if (ret < 0)
+		goto out;
+
+	/* set GPADC1 bias */
+	ret = pm860x_set_bits(info->i2c, PM8607_GP_BIAS2, 0xF << 4,
+			      GPBIAS2_GPADC1_SET);
+	if (ret < 0)
+		goto out;
+
+	/* check whether battery present) */
+	mutex_lock(&info->lock);
+	ret = pm860x_reg_read(info->i2c, PM8607_STATUS_2);
+	if (ret < 0) {
+		mutex_unlock(&info->lock);
+		goto out;
+	}
+	if (ret & STATUS2_BAT) {
+		info->present = 1;
+		info->temp_type = PM860X_TEMP_TBAT;
+	} else {
+		info->present = 0;
+		info->temp_type = PM860X_TEMP_TINT;
+	}
+	mutex_unlock(&info->lock);
+
+	calc_soc(info, OCV_MODE_ACTIVE, &soc);
+
+	data = pm860x_reg_read(info->i2c, PM8607_POWER_UP_LOG);
+	bat_remove = data & BAT_WU_LOG;
+
+	dev_dbg(info->dev, "battery wake up? %s\n",
+		bat_remove != 0 ? "yes" : "no");
+
+	/* restore SOC from RTC domain register */
+	if (bat_remove == 0) {
+		buf[0] = pm860x_reg_read(info->i2c, PM8607_RTC_MISC2);
+		buf[1] = pm860x_reg_read(info->i2c, PM8607_RTC1);
+		data = ((buf[1] & 0x3) << 5) | ((buf[0] >> 3) & 0x1F);
+		if (data > soc + 15)
+			info->start_soc = soc;
+		else if (data < soc - 15)
+			info->start_soc = soc;
+		else
+			info->start_soc = data;
+		dev_dbg(info->dev, "soc_rtc %d, soc_ocv :%d\n", data, soc);
+	} else {
+		pm860x_set_bits(info->i2c, PM8607_POWER_UP_LOG,
+				BAT_WU_LOG, BAT_WU_LOG);
+		info->start_soc = soc;
+	}
+	info->last_capacity = info->start_soc;
+	dev_dbg(info->dev, "init soc : %d\n", info->last_capacity);
+out:
+	return;
+}
+
+/*
+ * register 1 bit[7:0] -- bit[11:4] of measured value of voltage
+ * register 0 bit[3:0] -- bit[3:0] of measured value of voltage
+ */
+static int measure_12bit_voltage(struct pm860x_battery_info *info,
+				 int offset, int *data)
+{
+	unsigned char buf[2];
+	int ret;
+
+	if (!data)
+		return -EINVAL;
+
+	ret = pm860x_bulk_read(info->i2c, offset, 2, buf);
+	if (ret < 0)
+		return ret;
+
+	*data = ((buf[0] & 0xff) << 4) | (buf[1] & 0x0f);
+	/* V_MEAS(mV) = data * 1.8 * 1000 / (2^12) */
+	*data = ((*data & 0xfff) * 9 * 25) >> 9;
+	return 0;
+}
+
+static int measure_vbatt(struct pm860x_battery_info *info, int state,
+			 int *data)
+{
+	unsigned char buf[5];
+	int ret = 0;
+
+	switch (state) {
+	case OCV_MODE_ACTIVE:
+		ret = measure_12bit_voltage(info, PM8607_VBAT_MEAS1, data);
+		if (ret)
+			return ret;
+		/* V_BATT_MEAS(mV) = value * 3 * 1.8 * 1000 / (2^12) */
+		*data *= 3;
+		break;
+	case OCV_MODE_SLEEP:
+		/*
+		 * voltage value of VBATT in sleep mode is saved in different
+		 * registers.
+		 * bit[11:10] -- bit[7:6] of LDO9(0x18)
+		 * bit[9:8] -- bit[7:6] of LDO8(0x17)
+		 * bit[7:6] -- bit[7:6] of LDO7(0x16)
+		 * bit[5:4] -- bit[7:6] of LDO6(0x15)
+		 * bit[3:0] -- bit[7:4] of LDO5(0x14)
+		 */
+		ret = pm860x_bulk_read(info->i2c, PM8607_LDO5, 5, buf);
+		if (ret < 0)
+			return ret;
+		ret = ((buf[4] >> 6) << 10) | ((buf[3] >> 6) << 8)
+		    | ((buf[2] >> 6) << 6) | ((buf[1] >> 6) << 4)
+		    | (buf[0] >> 4);
+		/* V_BATT_MEAS(mV) = data * 3 * 1.8 * 1000 / (2^12) */
+		*data = ((*data & 0xff) * 27 * 25) >> 9;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static void set_temp_threshold(struct pm860x_battery_info *info,
+			       int min, int max)
+{
+	int data;
+
+	/* (tmp << 8) / 1800 */
+	if (min <= 0)
+		data = 0;
+	else
+		data = (min << 8) / 1800;
+	pm860x_reg_write(info->i2c, PM8607_GPADC1_HIGHTH, data);
+	dev_dbg(info->dev, "TEMP_HIGHTH : min: %d, 0x%x\n", min, data);
+
+	if (max <= 0)
+		data = 0xff;
+	else
+		data = (max << 8) / 1800;
+	pm860x_reg_write(info->i2c, PM8607_GPADC1_LOWTH, data);
+	dev_dbg(info->dev, "TEMP_LOWTH:max : %d, 0x%x\n", max, data);
+}
+
+static int measure_temp(struct pm860x_battery_info *info, int *data)
+{
+	int ret, temp;
+	int min, max;
+
+	if (!data)
+		return -EINVAL;
+	if (info->temp_type == PM860X_TEMP_TINT) {
+		ret = measure_12bit_voltage(info, PM8607_TINT_MEAS1, data);
+		if (ret)
+			return ret;
+		*data = (*data - 884) * 1000 / 3611;
+	} else {
+		ret = measure_12bit_voltage(info, PM8607_GPADC1_MEAS1, data);
+		if (ret)
+			return ret;
+		/* meausered Vtbat(mV) / Ibias_current(11uA)*/
+		*data = (*data * 1000) / GPBIAS2_GPADC1_UA;
+
+		if (*data > TBAT_NEG_25D) {
+			temp = -30;	/* over cold , suppose -30 roughly */
+			max = TBAT_NEG_10D * GPBIAS2_GPADC1_UA / 1000;
+			set_temp_threshold(info, 0, max);
+		} else if (*data > TBAT_NEG_10D) {
+			temp = -15;	/* -15 degree, code */
+			max = TBAT_NEG_10D * GPBIAS2_GPADC1_UA / 1000;
+			set_temp_threshold(info, 0, max);
+		} else if (*data > TBAT_0D) {
+			temp = -5;	/* -5 degree */
+			min = TBAT_NEG_10D * GPBIAS2_GPADC1_UA / 1000;
+			max = TBAT_40D * GPBIAS2_GPADC1_UA / 1000;
+			set_temp_threshold(info, min, max);
+		} else if (*data > TBAT_10D) {
+			temp = 5;	/* in range of (0, 10) */
+			min = TBAT_NEG_10D * GPBIAS2_GPADC1_UA / 1000;
+			max = TBAT_40D * GPBIAS2_GPADC1_UA / 1000;
+			set_temp_threshold(info, min, max);
+		} else if (*data > TBAT_20D) {
+			temp = 15;	/* in range of (10, 20) */
+			min = TBAT_NEG_10D * GPBIAS2_GPADC1_UA / 1000;
+			max = TBAT_40D * GPBIAS2_GPADC1_UA / 1000;
+			set_temp_threshold(info, min, max);
+		} else if (*data > TBAT_30D) {
+			temp = 25;	/* in range of (20, 30) */
+			min = TBAT_NEG_10D * GPBIAS2_GPADC1_UA / 1000;
+			max = TBAT_40D * GPBIAS2_GPADC1_UA / 1000;
+			set_temp_threshold(info, min, max);
+		} else if (*data > TBAT_40D) {
+			temp = 35;	/* in range of (30, 40) */
+			min = TBAT_NEG_10D * GPBIAS2_GPADC1_UA / 1000;
+			max = TBAT_40D * GPBIAS2_GPADC1_UA / 1000;
+			set_temp_threshold(info, min, max);
+		} else {
+			min = TBAT_40D * GPBIAS2_GPADC1_UA / 1000;
+			set_temp_threshold(info, min, 0);
+			temp = 45;	/* over heat ,suppose 45 roughly */
+		}
+
+		dev_dbg(info->dev, "temp_C:%d C,temp_mv:%d mv\n", temp, *data);
+		*data = temp;
+	}
+	return 0;
+}
+
+/*
+ * Return value is signed data.
+ * Negative value means discharging, and positive value means charging.
+ */
+static int measure_current(struct pm860x_battery_info *info, int *data)
+{
+	unsigned char buf[2];
+	short s;
+	int ret;
+
+	if (!data)
+		return -EINVAL;
+
+	ret = pm860x_bulk_read(info->i2c, PM8607_IBAT_MEAS1, 2, buf);
+	if (ret < 0)
+		return ret;
+
+	s = ((buf[0] & 0xff) << 8) | (buf[1] & 0xff);
+	/* current(mA) = value * 0.125 */
+	*data = s >> 3;
+	return 0;
+}
+
+static int set_charger_current(struct pm860x_battery_info *info, int data,
+			       int *old)
+{
+	int ret;
+
+	if (data < 50 || data > 1600 || !old)
+		return -EINVAL;
+
+	data = ((data - 50) / 50) & 0x1f;
+	*old = pm860x_reg_read(info->i2c, PM8607_CHG_CTRL2);
+	*old = (*old & 0x1f) * 50 + 50;
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL2, 0x1f, data);
+	if (ret < 0)
+		return ret;
+	return 0;
+}
+
+static int calc_resistor(struct pm860x_battery_info *info)
+{
+	int ret, i, data;
+	int vbatt_sum1, vbatt_sum2, chg_current;
+	int ibatt_sum1, ibatt_sum2;
+
+	ret = measure_current(info, &data);
+	/* make sure that charging is launched by data > 0 */
+	if (ret || data < 0)
+		goto out;
+
+	ret = measure_vbatt(info, OCV_MODE_ACTIVE, &data);
+	if (ret)
+		goto out;
+	/* calculate resistor only in CC charge mode */
+	if (data < VBATT_RESISTOR_MIN || data > VBATT_RESISTOR_MAX)
+		goto out;
+
+	/* current is saved */
+	if (set_charger_current(info, 500, &chg_current))
+		goto out;
+
+	msleep(500);
+
+	for (i = 0, vbatt_sum1 = 0, ibatt_sum1 = 0; i < 10; i++) {
+		ret = measure_vbatt(info, OCV_MODE_ACTIVE, &data);
+		if (ret)
+			goto out_meas;
+		vbatt_sum1 += data;
+		ret = measure_current(info, &data);
+		if (ret)
+			goto out_meas;
+
+		if (data < 0)
+			ibatt_sum1 = ibatt_sum1 - data;	/* discharging */
+		else
+			ibatt_sum1 = ibatt_sum1 + data;	/* charging */
+	}
+
+	if (set_charger_current(info, 100, &ret))
+		goto out_meas;
+
+	msleep(500);
+
+	for (i = 0, vbatt_sum2 = 0, ibatt_sum2 = 0; i < 10; i++) {
+		ret = measure_vbatt(info, OCV_MODE_ACTIVE, &data);
+		if (ret)
+			goto out_meas;
+		vbatt_sum2 += data;
+		ret = measure_current(info, &data);
+		if (ret)
+			goto out_meas;
+
+		if (data < 0)
+			ibatt_sum2 = ibatt_sum2 - data;	/* discharging */
+		else
+			ibatt_sum2 = ibatt_sum2 + data;	/* charging */
+	}
+
+	/* restore current setting */
+	if (set_charger_current(info, chg_current, &ret))
+		goto out_meas;
+
+	if ((vbatt_sum1 > vbatt_sum2) && (ibatt_sum1 > ibatt_sum2)
+	    && (ibatt_sum2 > 0)) {
+		/* calculate resistor in discharging case */
+		data = 1000 * (vbatt_sum1 - vbatt_sum2)
+		    / (ibatt_sum1 - ibatt_sum2);
+		if ((data - info->resistor > 0)
+		    && (data - info->resistor < info->resistor))
+			info->resistor = data;
+		if ((info->resistor - data > 0)
+		    && (info->resistor - data < data))
+			info->resistor = data;
+	}
+	return 0;
+
+out_meas:
+	set_charger_current(info, chg_current, &ret);
+out:
+	return -EINVAL;
+}
+
+static int read_ccnt(struct pm860x_battery_info *info, int offset,
+		     int *ccnt)
+{
+	unsigned char buf[2];
+	int ret;
+
+	if (!ccnt)
+		return -EINVAL;
+
+	ret = pm860x_set_bits(info->i2c, PM8607_CCNT, 7, offset & 7);
+	if (ret < 0)
+		goto out;
+	ret = pm860x_bulk_read(info->i2c, PM8607_CCNT_MEAS1, 2, buf);
+	if (ret < 0)
+		goto out;
+	*ccnt = ((buf[0] & 0xff) << 8) | (buf[1] & 0xff);
+	return 0;
+out:
+	return ret;
+}
+
+static int calc_ccnt(struct pm860x_battery_info *info, struct ccnt *ccnt)
+{
+	unsigned int sum;
+	int ret, data;
+
+	ret = read_ccnt(info, CCNT_POS1, &data);
+	if (ret)
+		goto out;
+	sum = data & 0xffff;
+	ret = read_ccnt(info, CCNT_POS2, &data);
+	if (ret)
+		goto out;
+	sum |= (data & 0xffff) << 16;
+	ccnt->pos += sum;
+
+	ret = read_ccnt(info, CCNT_NEG1, &data);
+	if (ret)
+		goto out;
+	sum = data & 0xffff;
+	ret = read_ccnt(info, CCNT_NEG2, &data);
+	if (ret)
+		goto out;
+	sum |= (data & 0xffff) << 16;
+	sum = ~sum + 1;		/* since it's negative */
+	ccnt->neg += sum;
+
+	ret = read_ccnt(info, CCNT_SPOS, &data);
+	if (ret)
+		goto out;
+	ccnt->spos += data;
+	ret = read_ccnt(info, CCNT_SNEG, &data);
+	if (ret)
+		goto out;
+
+	/*
+	 * charge(mAh)  = count * 1.6984 * 1e(-8)
+	 *              = count * 16984 * 1.024 * 1.024 * 1.024 / (2 ^ 40)
+	 *              = count * 18236 / (2 ^ 40)
+	 */
+	ccnt->total_chg = (int) ((ccnt->pos * 18236) >> 40);
+	ccnt->total_dischg = (int) ((ccnt->neg * 18236) >> 40);
+	return 0;
+out:
+	return ret;
+}
+
+static int clear_ccnt(struct pm860x_battery_info *info, struct ccnt *ccnt)
+{
+	int data;
+
+	memset(ccnt, 0, sizeof(struct ccnt));
+	/* read to clear ccnt */
+	read_ccnt(info, CCNT_POS1, &data);
+	read_ccnt(info, CCNT_POS2, &data);
+	read_ccnt(info, CCNT_NEG1, &data);
+	read_ccnt(info, CCNT_NEG2, &data);
+	read_ccnt(info, CCNT_SPOS, &data);
+	read_ccnt(info, CCNT_SNEG, &data);
+	return 0;
+}
+
+/* Calculate Open Circuit Voltage */
+static int calc_ocv(struct pm860x_battery_info *info, int *ocv)
+{
+	int ret, i, data;
+	int vbatt_avg, vbatt_sum, ibatt_avg, ibatt_sum;
+
+	if (!ocv)
+		return -EINVAL;
+
+	for (i = 0, ibatt_sum = 0, vbatt_sum = 0; i < 10; i++) {
+		ret = measure_vbatt(info, OCV_MODE_ACTIVE, &data);
+		if (ret)
+			goto out;
+		vbatt_sum += data;
+		ret = measure_current(info, &data);
+		if (ret)
+			goto out;
+		ibatt_sum += data;
+	}
+	vbatt_avg = vbatt_sum / 10;
+	ibatt_avg = ibatt_sum / 10;
+
+	mutex_lock(&info->lock);
+	if (info->present)
+		*ocv = vbatt_avg - ibatt_avg * info->resistor / 1000;
+	else
+		*ocv = vbatt_avg;
+	mutex_unlock(&info->lock);
+	dev_dbg(info->dev, "VBAT average:%d, OCV:%d\n", vbatt_avg, *ocv);
+	return 0;
+out:
+	return ret;
+}
+
+/* Calculate State of Charge (percent points) */
+static int calc_soc(struct pm860x_battery_info *info, int state, int *soc)
+{
+	int i, ocv, count, ret = -EINVAL;
+
+	if (!soc)
+		return -EINVAL;
+
+	switch (state) {
+	case OCV_MODE_ACTIVE:
+		ret = calc_ocv(info, &ocv);
+		break;
+	case OCV_MODE_SLEEP:
+		ret = measure_vbatt(info, OCV_MODE_SLEEP, &ocv);
+		break;
+	}
+	if (ret)
+		goto out;
+
+	count = ARRAY_SIZE(array_soc);
+	if (ocv < array_soc[count - 1][0]) {
+		*soc = 0;
+		return 0;
+	}
+
+	for (i = 0; i < count; i++) {
+		if (ocv >= array_soc[i][0]) {
+			*soc = array_soc[i][1];
+			break;
+		}
+	}
+	return 0;
+out:
+	return ret;
+}
+
+static int calc_capacity(struct pm860x_battery_info *info, int *cap)
+{
+	int ret, data, ibat;
+	int cap_ocv = 0, cap_cc = 0;
+
+	ret = calc_ccnt(info, &ccnt_data);
+	if (ret)
+		goto out;
+soc:
+	data = info->max_capacity * info->start_soc / 100;
+	if (ccnt_data.total_dischg - ccnt_data.total_chg <= data) {
+		cap_cc =
+		    data + ccnt_data.total_chg - ccnt_data.total_dischg;
+	} else {
+		clear_ccnt(info, &ccnt_data);
+		calc_soc(info, OCV_MODE_ACTIVE, &info->start_soc);
+		dev_dbg(info->dev, "restart soc = %d !\n",
+			info->start_soc);
+		goto soc;
+	}
+
+	cap_cc = cap_cc * 100 / info->max_capacity;
+	if (cap_cc < 0)
+		cap_cc = 0;
+	else if (cap_cc > 100)
+		cap_cc = 100;
+
+	dev_dbg(info->dev, "%s, last cap : %d", __func__,
+		info->last_capacity);
+
+	ret = measure_current(info, &ibat);
+	if (ret)
+		goto out;
+	/* Calculate the capacity when discharging(ibat < 0) */
+	if (ibat < 0) {
+		ret = calc_soc(info, OCV_MODE_ACTIVE, &cap_ocv);
+		if (ret)
+			cap_ocv = info->last_capacity;
+		ret = measure_vbatt(info, OCV_MODE_ACTIVE, &data);
+		if (ret)
+			goto out;
+		if (data <= LOW_BAT_THRESHOLD) {
+			/* choose the lower capacity value to report
+			 * between vbat and CC when vbat < 3.6v;
+			 * than 3.6v;
+			 */
+			*cap = min(cap_ocv, cap_cc);
+		} else {
+			/* when detect vbat > 3.6v, but cap_cc < 15,and
+			 * cap_ocv is 10% larger than cap_cc, we can think
+			 * CC have some accumulation error, switch to OCV
+			 * to estimate capacity;
+			 * */
+			if (cap_cc < 15 && cap_ocv - cap_cc > 10)
+				*cap = cap_ocv;
+			else
+				*cap = cap_cc;
+		}
+		/* when discharging, make sure current capacity
+		 * is lower than last*/
+		if (*cap > info->last_capacity)
+			*cap = info->last_capacity;
+	} else {
+		*cap = cap_cc;
+	}
+	info->last_capacity = *cap;
+
+	dev_dbg(info->dev, "%s, cap_ocv:%d cap_cc:%d, cap:%d\n",
+		(ibat < 0) ? "discharging" : "charging",
+		 cap_ocv, cap_cc, *cap);
+	/*
+	 * store the current capacity to RTC domain register,
+	 * after next power up , it will be restored.
+	 */
+	pm860x_set_bits(info->i2c, PM8607_RTC_MISC2, RTC_SOC_5LSB,
+			(*cap & 0x1F) << 3);
+	pm860x_set_bits(info->i2c, PM8607_RTC1, RTC_SOC_3MSB,
+			((*cap >> 5) & 0x3));
+	return 0;
+out:
+	return ret;
+}
+
+static void pm860x_external_power_changed(struct power_supply *psy)
+{
+	struct pm860x_battery_info *info;
+
+	info = container_of(psy, struct pm860x_battery_info, battery);
+	calc_resistor(info);
+	return;
+}
+
+static int pm860x_batt_get_prop(struct power_supply *psy,
+				enum power_supply_property psp,
+				union power_supply_propval *val)
+{
+	struct pm860x_battery_info *info =
+	    dev_get_drvdata(psy->dev->parent);
+	int data, ret;
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_PRESENT:
+		val->intval = info->present;
+		break;
+	case POWER_SUPPLY_PROP_CAPACITY:
+		ret = calc_capacity(info, &data);
+		if (ret)
+			goto out;
+		if (data < 0)
+			data = 0;
+		else if (data > 100)
+			data = 100;
+		/* return 100 if battery is not attached */
+		if (!info->present)
+			data = 100;
+		val->intval = data;
+		break;
+	case POWER_SUPPLY_PROP_TECHNOLOGY:
+		val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+		/* return real vbatt Voltage */
+		ret = measure_vbatt(info, OCV_MODE_ACTIVE, &data);
+		if (ret)
+			goto out;
+		val->intval = data * 1000;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_AVG:
+		/* return Open Circuit Voltage (not measured voltage) */
+		ret = calc_ocv(info, &data);
+		if (ret)
+			goto out;
+		val->intval = data * 1000;
+		break;
+	case POWER_SUPPLY_PROP_CURRENT_NOW:
+		ret = measure_current(info, &data);
+		if (ret)
+			goto out;
+		val->intval = data;
+		break;
+	case POWER_SUPPLY_PROP_TEMP:
+		if (info->present) {
+			ret = measure_temp(info, &data);
+			if (ret)
+				goto out;
+			data *= 10;
+		} else {
+			/* Fake Temp 25C Without Battery */
+			data = 250;
+		}
+		val->intval = data;
+		break;
+	default:
+		return -ENODEV;
+	}
+	return 0;
+out:
+	return ret;
+}
+
+static int pm860x_batt_set_prop(struct power_supply *psy,
+				       enum power_supply_property psp,
+				       const union power_supply_propval *val)
+{
+	struct pm860x_battery_info *info =
+	    dev_get_drvdata(psy->dev->parent);
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_CHARGE_FULL:
+		clear_ccnt(info, &ccnt_data);
+		info->start_soc = 100;
+		dev_dbg(info->dev, "chg done, update soc = %d\n",
+			info->start_soc);
+		break;
+	default:
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+
+static enum power_supply_property pm860x_batt_props[] = {
+	POWER_SUPPLY_PROP_PRESENT,
+	POWER_SUPPLY_PROP_CAPACITY,
+	POWER_SUPPLY_PROP_TECHNOLOGY,
+	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+	POWER_SUPPLY_PROP_VOLTAGE_AVG,
+	POWER_SUPPLY_PROP_CURRENT_NOW,
+	POWER_SUPPLY_PROP_TEMP,
+};
+
+static __devinit int pm860x_battery_probe(struct platform_device *pdev)
+{
+	struct pm860x_chip *chip = dev_get_drvdata(pdev->dev.parent);
+	struct pm860x_battery_info *info;
+	struct pm860x_power_pdata *pdata;
+	int ret;
+
+	info = kzalloc(sizeof(struct pm860x_battery_info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+	info->irq_cc = platform_get_irq(pdev, 0);
+	if (info->irq_cc < 0) {
+		dev_err(&pdev->dev, "No IRQ resource!\n");
+		ret = -EINVAL;
+		goto out;
+	}
+	info->irq_batt = platform_get_irq(pdev, 1);
+	if (info->irq_batt < 0) {
+		dev_err(&pdev->dev, "No IRQ resource!\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	info->chip = chip;
+	info->i2c =
+	    (chip->id == CHIP_PM8607) ? chip->client : chip->companion;
+	info->dev = &pdev->dev;
+	info->status = POWER_SUPPLY_STATUS_UNKNOWN;
+	pdata = pdev->dev.platform_data;
+
+	ret = request_threaded_irq(info->irq_cc, NULL,
+				pm860x_coulomb_handler, IRQF_ONESHOT,
+				"coulomb", info);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+			info->irq_cc, ret);
+		goto out;
+	}
+	ret = request_threaded_irq(info->irq_batt, NULL, pm860x_batt_handler,
+				IRQF_ONESHOT, "battery", info);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+			info->irq_batt, ret);
+		goto out_coulomb;
+	}
+
+	mutex_init(&info->lock);
+	platform_set_drvdata(pdev, info);
+
+	pm860x_init_battery(info);
+
+	info->battery.name = "battery-monitor";
+	info->battery.type = POWER_SUPPLY_TYPE_BATTERY;
+	info->battery.properties = pm860x_batt_props;
+	info->battery.num_properties = ARRAY_SIZE(pm860x_batt_props);
+	info->battery.get_property = pm860x_batt_get_prop;
+	info->battery.set_property = pm860x_batt_set_prop;
+	info->battery.external_power_changed = pm860x_external_power_changed;
+
+	if (pdata && pdata->max_capacity)
+		info->max_capacity = pdata->max_capacity;
+	else
+		info->max_capacity = 1500;	/* set default capacity */
+	if (pdata && pdata->resistor)
+		info->resistor = pdata->resistor;
+	else
+		info->resistor = 300;	/* set default internal resistor */
+
+	ret = power_supply_register(&pdev->dev, &info->battery);
+	if (ret)
+		goto out_reg;
+	info->battery.dev->parent = &pdev->dev;
+
+	return 0;
+
+out_reg:
+	free_irq(info->irq_batt, info);
+out_coulomb:
+	free_irq(info->irq_cc, info);
+out:
+	kfree(info);
+	return ret;
+}
+
+static int __devexit pm860x_battery_remove(struct platform_device *pdev)
+{
+	struct pm860x_battery_info *info = platform_get_drvdata(pdev);
+
+	power_supply_unregister(&info->battery);
+	free_irq(info->irq_batt, info);
+	free_irq(info->irq_cc, info);
+	kfree(info);
+	platform_set_drvdata(pdev, NULL);
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int pm860x_battery_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static int pm860x_battery_resume(struct device *dev)
+{
+	return 0;
+}
+#endif
+static SIMPLE_DEV_PM_OPS(pm860x_battery_pm_ops, pm860x_battery_suspend,
+			 pm860x_battery_resume);
+
+static struct platform_driver pm860x_battery_driver = {
+	.driver = {
+		   .name = "88pm860x-battery",
+		   .owner = THIS_MODULE,
+		   .pm = &pm860x_battery_pm_ops,
+		   },
+	.probe = pm860x_battery_probe,
+	.remove = __devexit_p(pm860x_battery_remove),
+};
+
+module_platform_driver(pm860x_battery_driver);
+
+MODULE_DESCRIPTION("Marvell 88PM860x Battery driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/power/88pm860x_charger.c b/drivers/power/88pm860x_charger.c
new file mode 100644
index 0000000..0089ad4
--- /dev/null
+++ b/drivers/power/88pm860x_charger.c
@@ -0,0 +1,833 @@
+/*
+ * Battery driver for Marvell 88PM860x PMIC
+ *
+ * Copyright (c) 2012 Marvell International Ltd.
+ * Author:	Jett Zhou <jtzhou at marvell.com>
+ *		Haojian Zhuang <haojian.zhuang at marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/power_supply.h>
+#include <linux/mfd/88pm860x.h>
+#include <linux/delay.h>
+#include <linux/uaccess.h>
+#include <asm/div64.h>
+
+
+/* bit definitions of Status Query Interface 2 */
+#define STATUS2_CHG		(1 << 2)
+
+/* bit definitions of Reset Out Register */
+#define RESET_SW_PD		(1 << 7)
+
+/* bit definitions of PreReg 1 */
+#define PREREG1_90MA		(0x0)
+#define PREREG1_180MA		(0x1)
+#define PREREG1_450MA		(0x4)
+#define PREREG1_540MA		(0x5)
+#define PREREG1_1350MA		(0xE)
+#define PREREG1_VSYS_4_5V	(3 << 4)
+
+/* bit definitions of Charger Control 1 Register */
+#define CC1_MODE_OFF		(0)
+#define CC1_MODE_PRECHARGE	(1)
+#define CC1_MODE_FASTCHARGE	(2)
+#define CC1_MODE_PULSECHARGE	(3)
+#define CC1_ITERM_20MA		(0 << 2)
+#define CC1_ITERM_60MA		(2 << 2)
+#define CC1_VFCHG_4_2V		(9 << 4)
+
+/* bit definitions of Charger Control 2 Register */
+#define CC2_ICHG_100MA		(0x1)
+#define CC2_ICHG_500MA		(0x9)
+#define CC2_ICHG_1000MA		(0x13)
+
+/* bit definitions of Charger Control 3 Register */
+#define CC3_180MIN_TIMEOUT	(0x6 << 4)
+#define CC3_270MIN_TIMEOUT	(0x7 << 4)
+#define CC3_360MIN_TIMEOUT	(0xA << 4)
+#define CC3_DISABLE_TIMEOUT	(0xF << 4)
+
+/* bit definitions of Charger Control 4 Register */
+#define CC4_IPRE_40MA		(7)
+#define CC4_VPCHG_3_2V		(3 << 4)
+#define CC4_IFCHG_MON_EN	(1 << 6)
+#define CC4_BTEMP_MON_EN	(1 << 7)
+
+/* bit definitions of Charger Control 6 Register */
+#define CC6_BAT_OV_EN		(1 << 2)
+#define CC6_BAT_UV_EN		(1 << 3)
+#define CC6_UV_VBAT_SET		(0x3 << 6)	/* 2.8v */
+
+/* bit definitions of Charger Control 7 Register */
+#define CC7_BAT_REM_EN		(1 << 3)
+#define CC7_IFSM_EN		(1 << 7)
+
+/* bit definitions of Measurement Enable 1 Register */
+#define MEAS1_VBAT		(1 << 0)
+
+/* bit definitions of Measurement Enable 3 Register */
+#define MEAS3_IBAT_EN		(1 << 0)
+#define MEAS3_CC_EN		(1 << 2)
+
+#define FSM_INIT		0
+#define FSM_DISCHARGE		1
+#define FSM_PRECHARGE		2
+#define FSM_FASTCHARGE		3
+
+#define PRECHARGE_THRESHOLD	3100
+#define POWEROFF_THRESHOLD	3400
+#define CHARGE_THRESHOLD	4000
+#define DISCHARGE_THRESHOLD	4180
+
+/* over-temperature on PM8606 setting */
+#define OVER_TEMP_FLAG		(1 << 6)
+#define OVTEMP_AUTORECOVER	(1 << 3)
+
+/* over-voltage protect on vchg setting mv */
+#define VCHG_NORMAL_LOW		4200
+#define VCHG_NORMAL_CHECK	5800
+#define VCHG_NORMAL_HIGH	6000
+#define VCHG_OVP_LOW		5500
+
+struct pm860x_charger_info {
+	struct pm860x_chip *chip;
+	struct i2c_client *i2c;
+	struct i2c_client *i2c_8606;
+	struct device *dev;
+
+	struct power_supply usb;
+	struct mutex lock;
+	int irq_nums;
+	int irq[7];
+	unsigned state:3;	/* fsm state */
+	unsigned online:1;	/* usb charger */
+	unsigned present:1;	/* battery present */
+	unsigned allowed:1;
+};
+
+static char *pm860x_supplied_to[] = {
+	"battery-monitor",
+};
+
+static int stop_charge(struct pm860x_charger_info *info, int vbatt);
+static int set_charging_fsm(struct pm860x_charger_info *info);
+static void set_vbatt_threshold(struct pm860x_charger_info *info,
+				int min, int max);
+static void set_vchg_threshold(struct pm860x_charger_info *info,
+			       int min, int max);
+static int measure_vchg(struct pm860x_charger_info *info, int *data);
+
+static irqreturn_t pm860x_charger_handler(int irq, void *data)
+{
+	struct pm860x_charger_info *info = data;
+	int ret;
+
+	mutex_lock(&info->lock);
+	ret = pm860x_reg_read(info->i2c, PM8607_STATUS_2);
+	if (ret < 0) {
+		mutex_unlock(&info->lock);
+		goto out;
+	}
+	if (ret & STATUS2_CHG) {
+		info->online = 1;
+		info->allowed = 1;
+	} else {
+		info->online = 0;
+		info->allowed = 0;
+	}
+	mutex_unlock(&info->lock);
+	dev_dbg(info->dev, "%s, Charger:%s, Allowed:%d\n", __func__,
+		(info->online) ? "online" : "N/A", info->allowed);
+
+	set_charging_fsm(info);
+
+	power_supply_changed(&info->usb);
+out:
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t pm860x_temp_handler(int irq, void *data)
+{
+	struct power_supply *psy;
+	struct pm860x_charger_info *info = data;
+	union power_supply_propval temp;
+	int value, ret = -EINVAL;
+
+	psy = power_supply_get_by_name(pm860x_supplied_to[0]);
+	if (!psy)
+		goto out;
+	ret = psy->get_property(psy, POWER_SUPPLY_PROP_TEMP, &temp);
+	if (ret)
+		goto out;
+	value = temp.intval / 10;
+
+	mutex_lock(&info->lock);
+	/* Temperature < -10 C or >40 C, Will not allow charge */
+	if (value < -10 || value > 40)
+		info->allowed = 0;
+	else
+		info->allowed = 1;
+	dev_dbg(info->dev, "%s, Allowed: %d\n", __func__, info->allowed);
+	mutex_unlock(&info->lock);
+
+	set_charging_fsm(info);
+out:
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t pm860x_exception_handler(int irq, void *data)
+{
+	struct pm860x_charger_info *info = data;
+
+	mutex_lock(&info->lock);
+	info->allowed = 0;
+	mutex_unlock(&info->lock);
+	dev_dbg(info->dev, "%s, irq: %d\n", __func__, irq);
+
+	set_charging_fsm(info);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t pm860x_done_handler(int irq, void *data)
+{
+	struct pm860x_charger_info *info = data;
+	struct power_supply *psy;
+	union power_supply_propval val;
+	int ret, vbatt;
+
+	mutex_lock(&info->lock);
+	/* pre-charge done, will transimit to fast-charge stage */
+	if (info->state == FSM_PRECHARGE) {
+		info->allowed = 1;
+		goto out;
+	}
+	/*
+	 * Fast charge done, delay to read
+	 * the correct status of CHG_DET.
+	 */
+	mdelay(5);
+	info->allowed = 0;
+	psy = power_supply_get_by_name(pm860x_supplied_to[0]);
+	if (!psy)
+		goto out;
+	ret = psy->get_property(psy, POWER_SUPPLY_PROP_VOLTAGE_NOW, &val);
+	if (ret)
+		goto out;
+	vbatt = val.intval / 1000;
+	/*
+	 * CHG_DONE interrupt is faster than CHG_DET interrupt when
+	 * plug in/out usb, So we can not rely on info->online, we
+	 * need check pm8607 status register to check usb is online
+	 * or not, then we can decide it is real charge done
+	 * automatically or it is triggered by usb plug out;
+	 */
+	ret = pm860x_reg_read(info->i2c, PM8607_STATUS_2);
+	if (ret < 0)
+		goto out;
+	if (vbatt > CHARGE_THRESHOLD && ret & STATUS2_CHG)
+		psy->set_property(psy, POWER_SUPPLY_PROP_CHARGE_FULL, &val);
+
+out:
+	mutex_unlock(&info->lock);
+	dev_dbg(info->dev, "%s, Allowed: %d\n", __func__, info->allowed);
+	set_charging_fsm(info);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t pm860x_vbattery_handler(int irq, void *data)
+{
+	struct pm860x_charger_info *info = data;
+
+	mutex_lock(&info->lock);
+
+	set_vbatt_threshold(info, 0, 0);
+
+	if (info->present && info->online)
+		info->allowed = 1;
+	else
+		info->allowed = 0;
+	mutex_unlock(&info->lock);
+	dev_dbg(info->dev, "%s, Allowed: %d\n", __func__, info->allowed);
+
+	set_charging_fsm(info);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t pm860x_vchg_handler(int irq, void *data)
+{
+	struct pm860x_charger_info *info = data;
+	int vchg = 0, status = 0;
+
+	if (info->present)
+		goto out;
+
+	measure_vchg(info, &vchg);
+
+	mutex_lock(&info->lock);
+	if (!info->online) {
+		/* check if over-temp on pm8606 or not */
+		status = pm860x_reg_read(info->i2c_8606, PM8606_FLAGS);
+		if (status & OVER_TEMP_FLAG) {
+			/* clear over temp flag and set auto recover */
+			pm860x_set_bits(info->i2c_8606, PM8606_FLAGS,
+					OVER_TEMP_FLAG, OVER_TEMP_FLAG);
+			pm860x_set_bits(info->i2c_8606,
+					PM8606_VSYS,
+					OVTEMP_AUTORECOVER,
+					OVTEMP_AUTORECOVER);
+			dev_dbg(info->dev,
+				"%s, pm8606 over-temp occure\n", __func__);
+		}
+	}
+
+	if (vchg > VCHG_NORMAL_CHECK) {
+		set_vchg_threshold(info, VCHG_OVP_LOW, 0);
+		info->allowed = 0;
+		dev_dbg(info->dev,
+			"%s,pm8607 over-vchg occure,vchg = %dmv\n",
+			__func__, vchg);
+	} else if (vchg < VCHG_OVP_LOW) {
+		set_vchg_threshold(info, VCHG_NORMAL_LOW,
+				   VCHG_NORMAL_HIGH);
+		info->allowed = 1;
+		dev_dbg(info->dev,
+			"%s,pm8607 over-vchg recover,vchg = %dmv\n",
+			__func__, vchg);
+	}
+	mutex_unlock(&info->lock);
+
+	dev_dbg(info->dev, "%s, Allowed: %d\n", __func__, info->allowed);
+	set_charging_fsm(info);
+out:
+	return IRQ_HANDLED;
+}
+
+static ssize_t stop_charging(struct device *dev,
+			     struct device_attribute *attr,
+			     const char *buf, size_t count)
+{
+	struct pm860x_charger_info *info = dev_get_drvdata(dev);
+	int disable;
+
+	sscanf(buf, "%d", &disable);
+	if (disable && info) {
+		dev_dbg(info->dev, "stop charging by manual\n");
+
+		mutex_lock(&info->lock);
+		info->allowed = 0;
+		mutex_unlock(&info->lock);
+		set_charging_fsm(info);
+	}
+	return strnlen(buf, PAGE_SIZE);
+}
+
+static DEVICE_ATTR(stop, S_IWUSR, NULL, stop_charging);
+
+static int pm860x_usb_get_prop(struct power_supply *psy,
+			       enum power_supply_property psp,
+			       union power_supply_propval *val)
+{
+	struct pm860x_charger_info *info =
+	    dev_get_drvdata(psy->dev->parent);
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_STATUS:
+		val->intval = (info->state == FSM_FASTCHARGE ||
+				info->state == FSM_PRECHARGE);
+		break;
+	case POWER_SUPPLY_PROP_ONLINE:
+		val->intval = info->online;
+		break;
+	default:
+		return -ENODEV;
+	}
+	return 0;
+}
+
+static enum power_supply_property pm860x_usb_props[] = {
+	POWER_SUPPLY_PROP_STATUS,
+	POWER_SUPPLY_PROP_ONLINE,
+};
+
+static int measure_vchg(struct pm860x_charger_info *info, int *data)
+{
+	unsigned char buf[2];
+	int ret = 0;
+
+	ret = pm860x_bulk_read(info->i2c, PM8607_VCHG_MEAS1, 2, buf);
+	if (ret < 0)
+		return ret;
+
+	*data = ((buf[0] & 0xff) << 4) | (buf[1] & 0x0f);
+	/* V_BATT_MEAS(mV) = value * 5 * 1.8 * 1000 / (2^12) */
+	*data = ((*data & 0xfff) * 9 * 125) >> 9;
+
+	dev_dbg(info->dev, "%s, vchg: %d mv\n", __func__, *data);
+
+	return ret;
+}
+
+static void set_vchg_threshold(struct pm860x_charger_info *info,
+			       int min, int max)
+{
+	int data;
+
+	/* (tmp << 8) * / 5 / 1800 */
+	if (min <= 0)
+		data = 0;
+	else
+		data = (min << 5) / 1125;
+	pm860x_reg_write(info->i2c, PM8607_VCHG_LOWTH, data);
+	dev_dbg(info->dev, "VCHG_LOWTH:%dmv, 0x%x\n", min, data);
+
+	if (max <= 0)
+		data = 0xff;
+	else
+		data = (max << 5) / 1125;
+	pm860x_reg_write(info->i2c, PM8607_VCHG_HIGHTH, data);
+	dev_dbg(info->dev, "VCHG_HIGHTH:%dmv, 0x%x\n", max, data);
+
+}
+
+static void set_vbatt_threshold(struct pm860x_charger_info *info,
+				int min, int max)
+{
+	int data;
+
+	/* (tmp << 8) * 3 / 1800 */
+	if (min <= 0)
+		data = 0;
+	else
+		data = (min << 5) / 675;
+	pm860x_reg_write(info->i2c, PM8607_VBAT_LOWTH, data);
+	dev_dbg(info->dev, "VBAT Min:%dmv, LOWTH:0x%x\n", min, data);
+
+	if (max <= 0)
+		data = 0xff;
+	else
+		data = (max << 5) / 675;
+	pm860x_reg_write(info->i2c, PM8607_VBAT_HIGHTH, data);
+	dev_dbg(info->dev, "VBAT Max:%dmv, HIGHTH:0x%x\n", max, data);
+
+	return;
+}
+
+static int start_precharge(struct pm860x_charger_info *info)
+{
+	int ret;
+
+	dev_dbg(info->dev, "Start Pre-charging!\n");
+	set_vbatt_threshold(info, 0, 0);
+
+	ret = pm860x_reg_write(info->i2c_8606, PM8606_PREREGULATORA,
+			       PREREG1_1350MA | PREREG1_VSYS_4_5V);
+	if (ret < 0)
+		goto out;
+	/* stop charging */
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL1, 3,
+			      CC1_MODE_OFF);
+	if (ret < 0)
+		goto out;
+	/* set 270 minutes timeout */
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL3, (0xf << 4),
+			      CC3_270MIN_TIMEOUT);
+	if (ret < 0)
+		goto out;
+	/* set precharge current, termination voltage, IBAT & TBAT monitor */
+	ret = pm860x_reg_write(info->i2c, PM8607_CHG_CTRL4,
+			       CC4_IPRE_40MA | CC4_VPCHG_3_2V |
+			       CC4_IFCHG_MON_EN | CC4_BTEMP_MON_EN);
+	if (ret < 0)
+		goto out;
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL7,
+			      CC7_BAT_REM_EN | CC7_IFSM_EN,
+			      CC7_BAT_REM_EN | CC7_IFSM_EN);
+	if (ret < 0)
+		goto out;
+	/* trigger precharge */
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL1, 3,
+			      CC1_MODE_PRECHARGE);
+out:
+	return ret;
+}
+
+static int start_fastcharge(struct pm860x_charger_info *info)
+{
+	int ret;
+
+	dev_dbg(info->dev, "Start Fast-charging!\n");
+
+	/* set fastcharge termination current & voltage, disable charging */
+	ret = pm860x_reg_write(info->i2c, PM8607_CHG_CTRL1,
+			       CC1_MODE_OFF | CC1_ITERM_60MA |
+			       CC1_VFCHG_4_2V);
+	if (ret < 0)
+		goto out;
+	ret = pm860x_reg_write(info->i2c_8606, PM8606_PREREGULATORA,
+			       PREREG1_540MA | PREREG1_VSYS_4_5V);
+	if (ret < 0)
+		goto out;
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL2, 0x1f,
+			      CC2_ICHG_500MA);
+	if (ret < 0)
+		goto out;
+	/* set 270 minutes timeout */
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL3, (0xf << 4),
+			      CC3_270MIN_TIMEOUT);
+	if (ret < 0)
+		goto out;
+	/* set IBAT & TBAT monitor */
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL4,
+			      CC4_IFCHG_MON_EN | CC4_BTEMP_MON_EN,
+			      CC4_IFCHG_MON_EN | CC4_BTEMP_MON_EN);
+	if (ret < 0)
+		goto out;
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL6,
+			      CC6_BAT_OV_EN | CC6_BAT_UV_EN |
+			      CC6_UV_VBAT_SET,
+			      CC6_BAT_OV_EN | CC6_BAT_UV_EN |
+			      CC6_UV_VBAT_SET);
+	if (ret < 0)
+		goto out;
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL7,
+			      CC7_BAT_REM_EN | CC7_IFSM_EN,
+			      CC7_BAT_REM_EN | CC7_IFSM_EN);
+	if (ret < 0)
+		goto out;
+	/* launch fast-charge */
+	ret = pm860x_set_bits(info->i2c, PM8607_CHG_CTRL1, 3,
+			      CC1_MODE_FASTCHARGE);
+	/* vchg threshold setting */
+	set_vchg_threshold(info, VCHG_NORMAL_LOW, VCHG_NORMAL_HIGH);
+out:
+	return ret;
+}
+
+static int stop_charge(struct pm860x_charger_info *info, int vbatt)
+{
+	dev_dbg(info->dev, "Stop charging!\n");
+	pm860x_set_bits(info->i2c, PM8607_CHG_CTRL1, 3, CC1_MODE_OFF);
+	if (vbatt > CHARGE_THRESHOLD && info->online)
+		set_vbatt_threshold(info, CHARGE_THRESHOLD, 0);
+	return 0;
+}
+
+static int power_off_notification(struct pm860x_charger_info *info)
+{
+	dev_dbg(info->dev, "Power-off notification!\n");
+	return 0;
+}
+
+static int set_charging_fsm(struct pm860x_charger_info *info)
+{
+	struct power_supply *psy;
+	union power_supply_propval data;
+	unsigned char fsm_state[][16] = { "init", "discharge", "precharge",
+		"fastcharge",
+	};
+	int ret = -EINVAL;
+	int vbatt;
+
+	psy = power_supply_get_by_name(pm860x_supplied_to[0]);
+	if (!psy)
+		goto out;
+	ret = psy->get_property(psy, POWER_SUPPLY_PROP_VOLTAGE_NOW, &data);
+	if (ret)
+		goto out;
+	vbatt = data.intval / 1000;
+
+	ret = psy->get_property(psy, POWER_SUPPLY_PROP_PRESENT, &data);
+	if (ret)
+		goto out;
+
+	mutex_lock(&info->lock);
+	info->present = data.intval;
+
+	dev_dbg(info->dev, "Entering FSM:%s, Charger:%s, Battery:%s, "
+		"Allowed:%d\n",
+		&fsm_state[info->state][0],
+		(info->online) ? "online" : "N/A",
+		(info->present) ? "present" : "N/A", info->allowed);
+	dev_dbg(info->dev, "set_charging_fsm:vbatt:%d(mV)\n", vbatt);
+
+	switch (info->state) {
+	case FSM_INIT:
+		if (info->online && info->present && info->allowed) {
+			if (vbatt < PRECHARGE_THRESHOLD) {
+				info->state = FSM_PRECHARGE;
+				start_precharge(info);
+			} else if (vbatt > DISCHARGE_THRESHOLD) {
+				info->state = FSM_DISCHARGE;
+				stop_charge(info, vbatt);
+			} else if (vbatt < DISCHARGE_THRESHOLD) {
+				info->state = FSM_FASTCHARGE;
+				start_fastcharge(info);
+			}
+		} else {
+			if (vbatt < POWEROFF_THRESHOLD) {
+				power_off_notification(info);
+			} else {
+				info->state = FSM_DISCHARGE;
+				stop_charge(info, vbatt);
+			}
+		}
+		break;
+	case FSM_PRECHARGE:
+		if (info->online && info->present && info->allowed) {
+			if (vbatt > PRECHARGE_THRESHOLD) {
+				info->state = FSM_FASTCHARGE;
+				start_fastcharge(info);
+			}
+		} else {
+			info->state = FSM_DISCHARGE;
+			stop_charge(info, vbatt);
+		}
+		break;
+	case FSM_FASTCHARGE:
+		if (info->online && info->present && info->allowed) {
+			if (vbatt < PRECHARGE_THRESHOLD) {
+				info->state = FSM_PRECHARGE;
+				start_precharge(info);
+			}
+		} else {
+			info->state = FSM_DISCHARGE;
+			stop_charge(info, vbatt);
+		}
+		break;
+	case FSM_DISCHARGE:
+		if (info->online && info->present && info->allowed) {
+			if (vbatt < PRECHARGE_THRESHOLD) {
+				info->state = FSM_PRECHARGE;
+				start_precharge(info);
+			} else if (vbatt < DISCHARGE_THRESHOLD) {
+				info->state = FSM_FASTCHARGE;
+				start_fastcharge(info);
+			}
+		} else {
+			if (vbatt < POWEROFF_THRESHOLD) {
+				power_off_notification(info);
+			} else if (vbatt > CHARGE_THRESHOLD
+				   && info->online)
+				set_vbatt_threshold(info, CHARGE_THRESHOLD,
+						    0);
+		}
+		break;
+	default:
+		dev_warn(info->dev, "FSM meets wrong state:%d\n",
+			 info->state);
+		break;
+	}
+	dev_dbg(info->dev,
+		"Out FSM:%s, Charger:%s, Battery:%s, Allowed:%d\n",
+		&fsm_state[info->state][0],
+		(info->online) ? "online" : "N/A",
+		(info->present) ? "present" : "N/A", info->allowed);
+	mutex_unlock(&info->lock);
+
+	return 0;
+out:
+	return ret;
+}
+
+static int pm860x_init_charger(struct pm860x_charger_info *info)
+{
+	int ret;
+
+	mutex_lock(&info->lock);
+	info->state = FSM_INIT;
+	ret = pm860x_reg_read(info->i2c, PM8607_STATUS_2);
+	if (ret < 0)
+		goto out;
+	if (ret & STATUS2_CHG) {
+		info->online = 1;
+		info->allowed = 1;
+	} else {
+		info->online = 0;
+		info->allowed = 0;
+	}
+	mutex_unlock(&info->lock);
+
+	set_charging_fsm(info);
+	return 0;
+out:
+	return ret;
+}
+
+static __devinit int pm860x_charger_probe(struct platform_device *pdev)
+{
+	struct pm860x_chip *chip = dev_get_drvdata(pdev->dev.parent);
+	struct pm860x_charger_info *info;
+	int ret, i, j, count;
+
+	info = kzalloc(sizeof(struct pm860x_charger_info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	ret = device_create_file(&pdev->dev, &dev_attr_stop);
+	if (ret < 0)
+		goto out;
+
+	count = pdev->num_resources;
+	for (i = 0, j = 0; i < count; i++) {
+		info->irq[j] = platform_get_irq(pdev, i);
+		if (info->irq[j] < 0)
+			continue;
+		j++;
+	}
+	info->irq_nums = j;
+
+	info->chip = chip;
+	info->i2c =
+	    (chip->id == CHIP_PM8607) ? chip->client : chip->companion;
+	info->i2c_8606 =
+	    (chip->id == CHIP_PM8607) ? chip->companion : chip->client;
+	if (!info->i2c_8606) {
+		dev_err(&pdev->dev, "Missed I2C address of 88PM8606!\n");
+		ret = -EINVAL;
+		goto out_dev;
+	}
+	info->dev = &pdev->dev;
+
+	/* set init value for the case we are not using battery */
+	set_vchg_threshold(info, VCHG_NORMAL_LOW, VCHG_OVP_LOW);
+
+	ret = request_threaded_irq(info->irq[0], NULL,
+				   pm860x_charger_handler,
+				   IRQF_ONESHOT, "usb supply detect",
+				   info);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+			info->irq[0], ret);
+		goto out_dev;
+	}
+
+	ret = request_threaded_irq(info->irq[1], NULL,
+				   pm860x_done_handler,
+				   IRQF_ONESHOT, "charge done", info);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+			info->irq[1], ret);
+		goto out_irq1;
+	}
+	ret = request_threaded_irq(info->irq[2], NULL,
+				   pm860x_exception_handler,
+				   IRQF_ONESHOT, "charge timeout", info);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+			info->irq[2], ret);
+		goto out_irq2;
+	}
+	ret = request_threaded_irq(info->irq[3], NULL,
+				   pm860x_exception_handler,
+				   IRQF_ONESHOT, "charge fault", info);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+			info->irq[3], ret);
+		goto out_irq3;
+	}
+	ret = request_threaded_irq(info->irq[4], NULL,
+				   pm860x_temp_handler,
+				   IRQF_ONESHOT, "temperature", info);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+			info->irq[4], ret);
+		goto out_irq4;
+	}
+	ret = request_threaded_irq(info->irq[5], NULL,
+				   pm860x_vbattery_handler,
+				   IRQF_ONESHOT, "vbatt", info);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+			info->irq[5], ret);
+		goto out_irq5;
+	}
+	ret = request_threaded_irq(info->irq[6], NULL,
+				   pm860x_vchg_handler,
+				   IRQF_ONESHOT, "vchg", info);
+	if (ret < 0) {
+		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+			info->irq[6], ret);
+		goto out_irq6;
+	}
+	if (info->irq_nums <= 6) {
+		dev_err(chip->dev, "IRQ numbers aren't matched\n");
+		goto out_nums;
+	}
+
+	mutex_init(&info->lock);
+	platform_set_drvdata(pdev, info);
+
+	info->usb.name = "usb";
+	info->usb.type = POWER_SUPPLY_TYPE_USB;
+	info->usb.supplied_to = pm860x_supplied_to;
+	info->usb.num_supplicants = ARRAY_SIZE(pm860x_supplied_to);
+	info->usb.properties = pm860x_usb_props;
+	info->usb.num_properties = ARRAY_SIZE(pm860x_usb_props);
+	info->usb.get_property = pm860x_usb_get_prop;
+	ret = power_supply_register(&pdev->dev, &info->usb);
+	if (ret)
+		goto out_nums;
+
+	pm860x_init_charger(info);
+
+	return 0;
+
+out_nums:
+	free_irq(info->irq[6], info);
+out_irq6:
+	free_irq(info->irq[5], info);
+out_irq5:
+	free_irq(info->irq[4], info);
+out_irq4:
+	free_irq(info->irq[3], info);
+out_irq3:
+	free_irq(info->irq[2], info);
+out_irq2:
+	free_irq(info->irq[1], info);
+out_irq1:
+	free_irq(info->irq[0], info);
+out_dev:
+	device_remove_file(&pdev->dev, &dev_attr_stop);
+out:
+	kfree(info);
+	return ret;
+}
+
+static int __devexit pm860x_charger_remove(struct platform_device *pdev)
+{
+	struct pm860x_charger_info *info = platform_get_drvdata(pdev);
+	int i;
+
+	platform_set_drvdata(pdev, NULL);
+	power_supply_unregister(&info->usb);
+	free_irq(info->irq[0], info);
+	for (i = 1; i < info->irq_nums; i++)
+		free_irq(info->irq[i], info);
+	device_remove_file(info->dev, &dev_attr_stop);
+	kfree(info);
+	return 0;
+}
+
+static struct platform_driver pm860x_charger_driver = {
+	.driver = {
+		   .name = "88pm860x-charger",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = pm860x_charger_probe,
+	.remove = __devexit_p(pm860x_charger_remove),
+};
+
+module_platform_driver(pm860x_charger_driver);
+
+MODULE_DESCRIPTION("Marvell 88PM860x Charger driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 3a8daf8..1af49ca 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -62,6 +62,12 @@ config TEST_POWER
 	help
 	  This driver is used for testing. It's safe to say M here.
 
+config BATTERY_88PM860X
+	tristate "Marvell 88PM860x battery driver"
+	depends on MFD_88PM860X
+	help
+	  Say Y here to enable battery monitor for Marvell 88PM860x chip.
+
 config BATTERY_DS2760
 	tristate "DS2760 battery driver (HP iPAQ & others)"
 	depends on W1 && W1_SLAVE_DS2760
@@ -188,6 +194,12 @@ config BATTERY_S3C_ADC
 	help
 	  Say Y here to enable support for iPAQ h1930/h1940/rx1950 battery
 
+config CHARGER_88PM860X
+	tristate "Marvell 88PM860x Charger driver"
+	depends on MFD_88PM860X && BATTERY_88PM860X
+	help
+	  Say Y here to enable charger for Marvell 88PM860x chip.
+
 config CHARGER_PCF50633
 	tristate "NXP PCF50633 MBC"
 	depends on MFD_PCF50633
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index e429008..f6ec9fc 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_WM831X_POWER)	+= wm831x_power.o
 obj-$(CONFIG_WM8350_POWER)	+= wm8350_power.o
 obj-$(CONFIG_TEST_POWER)	+= test_power.o
 
+obj-$(CONFIG_BATTERY_88PM860X)	+= 88pm860x_battery.o
 obj-$(CONFIG_BATTERY_DS2760)	+= ds2760_battery.o
 obj-$(CONFIG_BATTERY_DS2780)	+= ds2780_battery.o
 obj-$(CONFIG_BATTERY_DS2782)	+= ds2782_battery.o
@@ -30,6 +31,7 @@ obj-$(CONFIG_BATTERY_MAX17040)	+= max17040_battery.o
 obj-$(CONFIG_BATTERY_MAX17042)	+= max17042_battery.o
 obj-$(CONFIG_BATTERY_Z2)	+= z2_battery.o
 obj-$(CONFIG_BATTERY_S3C_ADC)	+= s3c_adc_battery.o
+obj-$(CONFIG_CHARGER_88PM860X)	+= 88pm860x_charger.o
 obj-$(CONFIG_CHARGER_PCF50633)	+= pcf50633-charger.o
 obj-$(CONFIG_BATTERY_JZ4740)	+= jz4740-battery.o
 obj-$(CONFIG_BATTERY_INTEL_MID)	+= intel_mid_battery.o
diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index 26926fb..fc0b52f 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -194,6 +194,21 @@ enum {
 #define PM8607_VIBRATOR_SET		(0x28)
 #define PM8607_VIBRATOR_PWM		(0x29)
 
+#define PM8607_MISC2			(0x42)
+
+/* Power Up Log Register */
+#define PM8607_POWER_UP_LOG		(0x3F)
+
+/* Charger Control Registers */
+#define PM8607_CCNT			(0x47)
+#define PM8607_CHG_CTRL1		(0x48)
+#define PM8607_CHG_CTRL2		(0x49)
+#define PM8607_CHG_CTRL3		(0x4A)
+#define PM8607_CHG_CTRL4		(0x4B)
+#define PM8607_CHG_CTRL5		(0x4C)
+#define PM8607_CHG_CTRL6		(0x4D)
+#define PM8607_CHG_CTRL7		(0x4E)
+
 /* GPADC Registers */
 #define PM8607_GP_BIAS1			(0x4F)
 #define PM8607_MEAS_EN1			(0x50)
@@ -205,6 +220,71 @@ enum {
 #define PM8607_PD_PREBIAS		(0x56)	/* prebias time */
 #define PM8607_GPADC_MISC1		(0x57)
 
+/* bit definitions of  MEAS_EN1*/
+#define PM8607_MEAS_EN1_VBAT		(1 << 0)
+#define PM8607_MEAS_EN1_VCHG		(1 << 1)
+#define PM8607_MEAS_EN1_VSYS		(1 << 2)
+#define PM8607_MEAS_EN1_TINT		(1 << 3)
+#define PM8607_MEAS_EN1_RFTMP		(1 << 4)
+#define PM8607_MEAS_EN1_TBAT		(1 << 5)
+#define PM8607_MEAS_EN1_GPADC2		(1 << 6)
+#define PM8607_MEAS_EN1_GPADC3		(1 << 7)
+
+/* Battery Monitor Registers */
+#define PM8607_GP_BIAS2			(0x5A)
+#define PM8607_VBAT_LOWTH		(0x5B)
+#define PM8607_VCHG_LOWTH		(0x5C)
+#define PM8607_VSYS_LOWTH		(0x5D)
+#define PM8607_TINT_LOWTH		(0x5E)
+#define PM8607_GPADC0_LOWTH		(0x5F)
+#define PM8607_GPADC1_LOWTH		(0x60)
+#define PM8607_GPADC2_LOWTH		(0x61)
+#define PM8607_GPADC3_LOWTH		(0x62)
+#define PM8607_VBAT_HIGHTH		(0x63)
+#define PM8607_VCHG_HIGHTH		(0x64)
+#define PM8607_VSYS_HIGHTH		(0x65)
+#define PM8607_TINT_HIGHTH		(0x66)
+#define PM8607_GPADC0_HIGHTH		(0x67)
+#define PM8607_GPADC1_HIGHTH		(0x68)
+#define PM8607_GPADC2_HIGHTH		(0x69)
+#define PM8607_GPADC3_HIGHTH		(0x6A)
+#define PM8607_IBAT_MEAS1		(0x6B)
+#define PM8607_IBAT_MEAS2		(0x6C)
+#define PM8607_VBAT_MEAS1		(0x6D)
+#define PM8607_VBAT_MEAS2		(0x6E)
+#define PM8607_VCHG_MEAS1		(0x6F)
+#define PM8607_VCHG_MEAS2		(0x70)
+#define PM8607_VSYS_MEAS1		(0x71)
+#define PM8607_VSYS_MEAS2		(0x72)
+#define PM8607_TINT_MEAS1		(0x73)
+#define PM8607_TINT_MEAS2		(0x74)
+#define PM8607_GPADC0_MEAS1		(0x75)
+#define PM8607_GPADC0_MEAS2		(0x76)
+#define PM8607_GPADC1_MEAS1		(0x77)
+#define PM8607_GPADC1_MEAS2		(0x78)
+#define PM8607_GPADC2_MEAS1		(0x79)
+#define PM8607_GPADC2_MEAS2		(0x7A)
+#define PM8607_GPADC3_MEAS1		(0x7B)
+#define PM8607_GPADC3_MEAS2		(0x7C)
+#define PM8607_CCNT_MEAS1		(0x95)
+#define PM8607_CCNT_MEAS2		(0x96)
+#define PM8607_VBAT_AVG			(0x97)
+#define PM8607_VCHG_AVG			(0x98)
+#define PM8607_VSYS_AVG			(0x99)
+#define PM8607_VBAT_MIN			(0x9A)
+#define PM8607_VCHG_MIN			(0x9B)
+#define PM8607_VSYS_MIN			(0x9C)
+#define PM8607_VBAT_MAX			(0x9D)
+#define PM8607_VCHG_MAX			(0x9E)
+#define PM8607_VSYS_MAX			(0x9F)
+
+#define PM8607_GPADC_MISC2		(0x59)
+#define PM8607_GPADC0_GP_BIAS_A0	(1 << 0)
+#define PM8607_GPADC1_GP_BIAS_A1	(1 << 1)
+#define PM8607_GPADC2_GP_BIAS_A2	(1 << 2)
+#define PM8607_GPADC3_GP_BIAS_A3	(1 << 3)
+#define PM8607_GPADC2_GP_BIAS_OUT2	(1 << 6)
+
 /* RTC Control Registers */
 #define PM8607_RTC1			(0xA0)
 #define PM8607_RTC_COUNTER1		(0xA1)
@@ -350,7 +430,8 @@ struct pm860x_touch_pdata {
 };
 
 struct pm860x_power_pdata {
-	unsigned	fast_charge;	/* charge current */
+	int		max_capacity;
+	int		resistor;
 };
 
 struct pm860x_platform_data {
@@ -359,6 +440,7 @@ struct pm860x_platform_data {
 	struct pm860x_rtc_pdata		*rtc;
 	struct pm860x_touch_pdata	*touch;
 	struct pm860x_power_pdata	*power;
+	struct charger_desc		*chg_desc;
 	struct regulator_init_data	*regulator;
 
 	unsigned short	companion_addr;	/* I2C address of companion chip */
@@ -388,5 +470,4 @@ extern int pm860x_page_set_bits(struct i2c_client *, int, unsigned char,
 extern int pm860x_device_init(struct pm860x_chip *chip,
 			      struct pm860x_platform_data *pdata) __devinit ;
 extern void pm860x_device_exit(struct pm860x_chip *chip) __devexit ;
-
 #endif /* __LINUX_MFD_88PM860X_H */
-- 
1.7.0.4



From jtzhou at marvell.com  Tue Mar 27 01:25:46 2012
From: jtzhou at marvell.com (Jett.Zhou)
Date: Tue, 27 Mar 2012 13:25:46 +0800
Subject: [PATCH 3/3] ARM: MMP: add 88pm860x battery-charger support
Message-ID: <1332825946-2260-1-git-send-email-jtzhou@marvell.com>

Add 88pm860x chg_desc platform data for ttc platform.

Signed-off-by: Jett.Zhou <jtzhou at marvell.com>
---
 arch/arm/mach-mmp/ttc_dkb.c |   37 +++++++++++++++++++++++++++++++++++++
 1 files changed, 37 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 5ac5d58..4e18be7 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -17,6 +17,9 @@
 #include <linux/interrupt.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/gpio.h>
+#include <linux/mfd/88pm860x.h>
+#include <linux/regulator/consumer.h>
+#include <linux/power/charger-manager.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -134,8 +137,42 @@ static struct pca953x_platform_data max7312_data[] = {
 	},
 };
 
+static char *ttc_psy_chg_stat[] = {"usb", NULL};
+/*
+ * Temperature can be handled by battery monitor base on interrupt
+ * scheme, so dummy it to make sure charger-manager initialize ok.
+ */
+static int dummy_temp_out_of_range(int *mC)
+{
+	*mC = 2500;
+	return 0;
+}
+
+struct charger_desc chg_desc_data = {
+	.polling_mode		= CM_POLL_ALWAYS,
+	.polling_interval_ms	= 180000,
+	.battery_present	= CM_FUEL_GAUGE,
+	.psy_charger_stat	= &ttc_psy_chg_stat[0],
+	.psy_fuel_gauge		= "battery-monitor",
+	.temperature_out_of_range	= dummy_temp_out_of_range,
+};
+
+static struct pm860x_platform_data ttc_dkb_pm8607_info = {
+	.chg_desc	= &chg_desc_data,
+	.companion_addr	= 0x11,
+	.irq_mode	= 0,
+	.irq_base	= IRQ_BOARD_START,
+	.i2c_port	= GI2C_PORT,
+};
+
 static struct i2c_board_info ttc_dkb_i2c_info[] = {
 	{
+		.type		= "88PM860x",
+		.addr		= 0x34,
+		.platform_data	= &ttc_dkb_pm8607_info,
+		.irq		= IRQ_PXA910_PMIC_INT,
+	},
+	{
 		.type		= "max7312",
 		.addr		= 0x23,
 		.irq		= MMP_GPIO_TO_IRQ(80),
-- 
1.7.0.4



From afzal at ti.com  Tue Mar 27 01:38:58 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Tue, 27 Mar 2012 05:38:58 +0000
Subject: [TMP][PATCH 5/5] OMAP3EVM: Test gpmc-nand
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A9317BD700@DBDE01.ent.ti.com>
References: <1332484630-22181-1-git-send-email-afzal@ti.com>
 <4F70ACB6.5070208@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A9317BD700@DBDE01.ent.ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A9317BD76F@DBDE01.ent.ti.com>

Hi Jon,

On Tue, Mar 27, 2012 at 10:49:32, Mohammed, Afzal wrote:
> Hi Jon,
> 
> On Mon, Mar 26, 2012 at 23:21:50, Hunter, Jon wrote:
> > I see this is marked as a temp patch, but this is actually needed to 
> > register the device. Actually, we would need to do this for all boards, 
> > right?
> 
> Yes, as NAND support on OMAP3EVM was not in mainline, made it TMP.
> Once GPMC driver interfaces are acceptable, other boards too will
> be modified accordingly.

Forgot to add that this patch was meant for testing and as the way
platforms deal with GPMC may change, this was kept as TMP for now.

Regards
Afzal


From shubhrajyoti at ti.com  Tue Mar 27 02:14:12 2012
From: shubhrajyoti at ti.com (Shubhrajyoti)
Date: Tue, 27 Mar 2012 11:44:12 +0530
Subject: [PATCH] ARM: OMAP: fix section mismatches in usb-host.c
In-Reply-To: <1332773470-22800-1-git-send-email-grinberg@compulab.co.il>
References: <1332773470-22800-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <4F715AB4.6070900@ti.com>

Hi Igor,
On Monday 26 March 2012 08:21 PM, Igor Grinberg wrote:
> Fix the below section mismatch warning and alike:
>
> WARNING: vmlinux.o(.text+0x281d4): Section mismatch in reference from
> the function setup_ehci_io_mux() to the function
> .init.text:omap_mux_init_signal()
> The function setup_ehci_io_mux() references
> the function __init omap_mux_init_signal().
> This is often because setup_ehci_io_mux lacks a __init
> annotation or the annotation of omap_mux_init_signal is wrong.
>
These functions are called from init section only so the functions also
should also have the __init
annotation.
Reviewed-by: Shubhrajyoti D <shubhrajyoti at ti.com>

> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
> ---
>  arch/arm/mach-omap2/usb-host.c |   10 ++++++----
>  1 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
> index f51348d..dde8a11 100644
> --- a/arch/arm/mach-omap2/usb-host.c
> +++ b/arch/arm/mach-omap2/usb-host.c
> @@ -54,7 +54,7 @@ static struct omap_device_pm_latency omap_uhhtll_latency[] = {
>  /*
>   * setup_ehci_io_mux - initialize IO pad mux for USBHOST
>   */
> -static void setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
> +static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  {
>  	switch (port_mode[0]) {
>  	case OMAP_EHCI_PORT_MODE_PHY:
> @@ -197,7 +197,8 @@ static void setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  	return;
>  }
>  
> -static void setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
> +static
> +void __init setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  {
>  	switch (port_mode[0]) {
>  	case OMAP_EHCI_PORT_MODE_PHY:
> @@ -315,7 +316,7 @@ static void setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  	}
>  }
>  
> -static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
> +static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  {
>  	switch (port_mode[0]) {
>  	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
> @@ -412,7 +413,8 @@ static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  	}
>  }
>  
> -static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
> +static
> +void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  {
>  	switch (port_mode[0]) {
>  	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:



From myungjoo.ham at samsung.com  Tue Mar 27 02:40:21 2012
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Tue, 27 Mar 2012 15:40:21 +0900
Subject: [PATCH v4 2/2] regulator: add device tree support for max8997
In-Reply-To: <1332582590-16382-3-git-send-email-thomas.abraham@linaro.org>
References: <1332582590-16382-1-git-send-email-thomas.abraham@linaro.org>
 <1332582590-16382-3-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CAJ0PZbR3n6Eq36VM23EHA41Y7ag9P1DaXE6cLLNUEntu1mWFcg@mail.gmail.com>

On Sat, Mar 24, 2012 at 6:49 PM, Thomas Abraham
<thomas.abraham at linaro.org> wrote:
> Add device tree based discovery support for max8997.
>
> Cc: MyungJoo Ham <myungjoo.ham at samsung.com>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>

Acked-by: MyungJoo Ham <myungjoo.ham at samsung.com>

> ---
> ?.../devicetree/bindings/regulator/max8997-pmic.txt | ?133 ++++++++++++++++++
> ?drivers/mfd/max8997.c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 73 ++++++++++-
> ?drivers/regulator/max8997.c ? ? ? ? ? ? ? ? ? ? ? ?| ?143 +++++++++++++++++++-
> ?include/linux/mfd/max8997-private.h ? ? ? ? ? ? ? ?| ? ?1 +
> ?include/linux/mfd/max8997.h ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
> ?5 files changed, 347 insertions(+), 4 deletions(-)
> ?create mode 100644 Documentation/devicetree/bindings/regulator/max8997-pmic.txt
>
> diff --git a/Documentation/devicetree/bindings/regulator/max8997-pmic.txt b/Documentation/devicetree/bindings/regulator/max8997-pmic.txt
> new file mode 100644
> index 0000000..90a730b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/regulator/max8997-pmic.txt
> @@ -0,0 +1,133 @@
> +* Maxim MAX8997 Voltage and Current Regulator
> +
> +The Maxim MAX8997 is a multi-function device which includes volatage and
> +current regulators, rtc, charger controller and other sub-blocks. It is
> +interfaced to the host controller using a i2c interface. Each sub-block is
> +addressed by the host system using different i2c slave address. This document
> +describes the bindings for 'pmic' sub-block of max8997.
> +
> +Required properties:
> +- compatible: Should be "maxim,max8997-pmic".
> +- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
> +
> +- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
> + ?units for buck1 when changing voltage using gpio dvs. Refer to [1] below
> + ?for additional information.
> +
> +- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
> + ?units for buck2 when changing voltage using gpio dvs. Refer to [1] below
> + ?for additional information.
> +
> +- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
> + ?units for buck5 when changing voltage using gpio dvs. Refer to [1] below
> + ?for additional information.
> +
> +[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
> + ? ?property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage'
> + ? ?property should specify atleast one voltage level (which would be a
> + ? ?safe operating voltage).
> +
> + ? ?If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
> + ? ?property is specified, then all the eigth voltage values for the
> + ? ?'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified.
> +
> +Optional properties:
> +- interrupt-parent: Specifies the phandle of the interrupt controller to which
> + ?the interrupts from max8997 are delivered to.
> +- interrupts: Interrupt specifiers for two interrupt sources.
> + ?- First interrupt specifier is for 'irq1' interrupt.
> + ?- Second interrupt specifier is for 'alert' interrupt.
> +- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs.
> +- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
> +- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs.
> +
> +Additional properties required if either of the optional properties are used:
> +- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for
> + ?multiple bucks, changing the voltage value of one of the bucks may affect
> + ?that of another buck, which is the side effect of the change (set_voltage).
> + ?Use this property to ignore such side effects and change the voltage.
> +
> +- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from
> + ?the possible 8 options selectable by the dvs gpios. The value of this
> + ?property should be between 0 and 7. If not specified or if out of range, the
> + ?default value of this property is set to 0.
> +
> +- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used
> + ?for dvs. The format of the gpio specifier depends in the gpio controller.
> +
> +
> +Regulators: The regulators of max8997 that have to be instantiated should be
> +included in a sub-node named 'regulators'. Regulator nodes included in this
> +sub-node should be of the format as below. Note: The 'n' in LDOn and BUCKn
> +represents the LDO or BUCK number as per the datasheet of max8997.
> +
> + ? ?For LDO's:
> + ? ? ? ? ? ? ? LDOn {
> + ? ? ? ? ? ? ? ? ? ? ? standard regulator bindings here
> + ? ? ? ? ? ? ? };
> +
> + ? ?For BUCK's:
> + ? ? ? ? ? ? ? BUCKn {
> + ? ? ? ? ? ? ? ? ? ? ? standard regulator bindings here
> + ? ? ? ? ? ? ? };
> +
> +The bindings inside the regulator nodes use the standard regulator bindings
> +which are documented elsewhere.
> +
> +Example:
> +
> + ? ? ? max8997_pmic at 66 {
> + ? ? ? ? ? ? ? compatible = "maxim,max8997-pmic";
> + ? ? ? ? ? ? ? interrupt-parent = <&wakeup_eint>;
> + ? ? ? ? ? ? ? reg = <0x66>;
> + ? ? ? ? ? ? ? interrupts = <4 0>, <3 0>;
> +
> + ? ? ? ? ? ? ? max8997,pmic-buck1-uses-gpio-dvs;
> + ? ? ? ? ? ? ? max8997,pmic-buck2-uses-gpio-dvs;
> + ? ? ? ? ? ? ? max8997,pmic-buck5-uses-gpio-dvs;
> +
> + ? ? ? ? ? ? ? max8997,pmic-ignore-gpiodvs-side-effect;
> + ? ? ? ? ? ? ? max8997,pmic-buck125-default-dvs-idx = <0>;
> +
> + ? ? ? ? ? ? ? max8997,pmic-buck125-dvs-gpios = <&gpx0 0 1 0 0>, /* SET1 */
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<&gpx0 1 1 0 0>, /* SET2 */
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<&gpx0 2 1 0 0>; /* SET3 */
> +
> + ? ? ? ? ? ? ? max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<1250000>, <1200000>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<1150000>, <1100000>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<1000000>, <950000>;
> +
> + ? ? ? ? ? ? ? max8997,pmic-buck2-dvs-voltage = <1100000>, <1100000>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<1100000>, <1100000>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<1000000>, <1000000>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<1000000>, <1000000>;
> +
> + ? ? ? ? ? ? ? max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<1200000>, <1200000>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<1200000>, <1200000>,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?<1200000>, <1200000>;
> +
> + ? ? ? ? ? ? ? regulators {
> + ? ? ? ? ? ? ? ? ? ? ? ldo1_reg: LDO1 {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-name = "VDD_ABB_3.3V";
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-min-microvolt = <3300000>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-max-microvolt = <3300000>;
> + ? ? ? ? ? ? ? ? ? ? ? };
> +
> + ? ? ? ? ? ? ? ? ? ? ? ldo2_reg: LDO2 {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-name = "VDD_ALIVE_1.1V";
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-min-microvolt = <1100000>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-max-microvolt = <1100000>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-always-on;
> + ? ? ? ? ? ? ? ? ? ? ? };
> +
> + ? ? ? ? ? ? ? ? ? ? ? buck1_reg: BUCK1 {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-name = "VDD_ARM_1.2V";
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-min-microvolt = <950000>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-max-microvolt = <1350000>;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-always-on;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? regulator-boot-on;
> + ? ? ? ? ? ? ? ? ? ? ? };
> + ? ? ? ? ? ? ? };
> + ? ? ? };
> diff --git a/drivers/mfd/max8997.c b/drivers/mfd/max8997.c
> index 20ecad3..1c38e98 100644
> --- a/drivers/mfd/max8997.c
> +++ b/drivers/mfd/max8997.c
> @@ -21,8 +21,10 @@
> ?* This driver is based on max8998.c
> ?*/
>
> +#include <linux/err.h>
> ?#include <linux/slab.h>
> ?#include <linux/i2c.h>
> +#include <linux/of_irq.h>
> ?#include <linux/interrupt.h>
> ?#include <linux/pm_runtime.h>
> ?#include <linux/module.h>
> @@ -47,6 +49,13 @@ static struct mfd_cell max8997_devs[] = {
> ? ? ? ?{ .name = "max8997-led", .id = 2 },
> ?};
>
> +#ifdef CONFIG_OF
> +static struct of_device_id __devinitdata max8997_pmic_dt_match[] = {
> + ? ? ? { .compatible = "maxim,max8997-pmic", .data = TYPE_MAX8997 },
> + ? ? ? {},
> +};
> +#endif
> +
> ?int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest)
> ?{
> ? ? ? ?struct max8997_dev *max8997 = i2c_get_clientdata(i2c);
> @@ -123,6 +132,58 @@ int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask)
> ?}
> ?EXPORT_SYMBOL_GPL(max8997_update_reg);
>
> +#ifdef CONFIG_OF
> +/*
> + * Only the common platform data elements for max8997 are parsed here from the
> + * device tree. Other sub-modules of max8997 such as pmic, rtc and others have
> + * to parse their own platform data elements from device tree.
> + *
> + * The max8997 platform data structure is instantiated here and the drivers for
> + * the sub-modules need not instantiate another instance while parsing their
> + * platform data.
> + */
> +static struct max8997_platform_data *max8997_i2c_parse_dt_pdata(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct device *dev)
> +{
> + ? ? ? struct max8997_platform_data *pd;
> +
> + ? ? ? pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
> + ? ? ? if (!pd) {
> + ? ? ? ? ? ? ? dev_err(dev, "could not allocate memory for pdata\n");
> + ? ? ? ? ? ? ? return ERR_PTR(-ENOMEM);
> + ? ? ? }
> +
> + ? ? ? pd->ono = irq_of_parse_and_map(dev->of_node, 1);
> +
> + ? ? ? /*
> + ? ? ? ?* ToDo: the 'wakeup' member in the platform data is more of a linux
> + ? ? ? ?* specfic information. Hence, there is no binding for that yet and
> + ? ? ? ?* not parsed here.
> + ? ? ? ?*/
> +
> + ? ? ? return pd;
> +}
> +#else
> +static int max8997_i2c_parse_dt_pdata(struct device *dev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct max8997_platform_data **pdata)
> +{
> + ? ? ? return 0;
> +}
> +#endif
> +
> +static inline int max8997_i2c_get_driver_data(struct i2c_client *i2c,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const struct i2c_device_id *id)
> +{
> +#ifdef CONFIG_OF
> + ? ? ? if (i2c->dev.of_node) {
> + ? ? ? ? ? ? ? const struct of_device_id *match;
> + ? ? ? ? ? ? ? match = of_match_node(max8997_pmic_dt_match, i2c->dev.of_node);
> + ? ? ? ? ? ? ? return (int)match->data;
> + ? ? ? }
> +#endif
> + ? ? ? return (int)id->driver_data;
> +}
> +
> ?static int max8997_i2c_probe(struct i2c_client *i2c,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ?const struct i2c_device_id *id)
> ?{
> @@ -137,12 +198,21 @@ static int max8997_i2c_probe(struct i2c_client *i2c,
> ? ? ? ?i2c_set_clientdata(i2c, max8997);
> ? ? ? ?max8997->dev = &i2c->dev;
> ? ? ? ?max8997->i2c = i2c;
> - ? ? ? max8997->type = id->driver_data;
> + ? ? ? max8997->type = max8997_i2c_get_driver_data(i2c, id);
> ? ? ? ?max8997->irq = i2c->irq;
>
> + ? ? ? if (max8997->dev->of_node) {
> + ? ? ? ? ? ? ? pdata = max8997_i2c_parse_dt_pdata(max8997->dev);
> + ? ? ? ? ? ? ? if (IS_ERR(pdata)) {
> + ? ? ? ? ? ? ? ? ? ? ? ret = PTR_ERR(pdata);
> + ? ? ? ? ? ? ? ? ? ? ? goto err;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> ? ? ? ?if (!pdata)
> ? ? ? ? ? ? ? ?goto err;
>
> + ? ? ? max8997->pdata = pdata;
> ? ? ? ?max8997->ono = pdata->ono;
>
> ? ? ? ?mutex_init(&max8997->iolock);
> @@ -434,6 +504,7 @@ static struct i2c_driver max8997_i2c_driver = {
> ? ? ? ? ? ? ? ? ? .name = "max8997",
> ? ? ? ? ? ? ? ? ? .owner = THIS_MODULE,
> ? ? ? ? ? ? ? ? ? .pm = &max8997_pm,
> + ? ? ? ? ? ? ? ? ?.of_match_table = of_match_ptr(max8997_pmic_dt_match),
> ? ? ? ?},
> ? ? ? ?.probe = max8997_i2c_probe,
> ? ? ? ?.remove = max8997_i2c_remove,
> diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
> index 9657929..dce8aaf 100644
> --- a/drivers/regulator/max8997.c
> +++ b/drivers/regulator/max8997.c
> @@ -25,6 +25,7 @@
> ?#include <linux/delay.h>
> ?#include <linux/err.h>
> ?#include <linux/gpio.h>
> +#include <linux/of_gpio.h>
> ?#include <linux/slab.h>
> ?#include <linux/module.h>
> ?#include <linux/platform_device.h>
> @@ -32,6 +33,7 @@
> ?#include <linux/regulator/machine.h>
> ?#include <linux/mfd/max8997.h>
> ?#include <linux/mfd/max8997-private.h>
> +#include <linux/regulator/of_regulator.h>
>
> ?struct max8997_data {
> ? ? ? ?struct device *dev;
> @@ -953,21 +955,155 @@ static struct regulator_desc regulators[] = {
> ? ? ? ?},
> ?};
>
> +#ifdef CONFIG_OF
> +static int max8997_pmic_dt_parse_dvs_gpio(struct max8997_dev *iodev,
> + ? ? ? ? ? ? ? ? ? ? ? struct max8997_platform_data *pdata,
> + ? ? ? ? ? ? ? ? ? ? ? struct device_node *pmic_np)
> +{
> + ? ? ? int i, gpio;
> +
> + ? ? ? for (i = 0; i < 3; i++) {
> + ? ? ? ? ? ? ? gpio = of_get_named_gpio(pmic_np,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "max8997,pmic-buck125-dvs-gpios", i);
> + ? ? ? ? ? ? ? if (!gpio_is_valid(gpio)) {
> + ? ? ? ? ? ? ? ? ? ? ? dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
> + ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? pdata->buck125_gpios[i] = gpio;
> + ? ? ? }
> + ? ? ? return 0;
> +}
> +
> +static int max8997_pmic_dt_parse_pdata(struct max8997_dev *iodev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct max8997_platform_data *pdata)
> +{
> + ? ? ? struct device_node *pmic_np, *regulators_np, *reg_np;
> + ? ? ? struct max8997_regulator_data *rdata;
> + ? ? ? unsigned int i, dvs_voltage_nr = 1, ret;
> +
> + ? ? ? pmic_np = iodev->dev->of_node;
> + ? ? ? if (!pmic_np) {
> + ? ? ? ? ? ? ? dev_err(iodev->dev, "could not find pmic sub-node\n");
> + ? ? ? ? ? ? ? return -ENODEV;
> + ? ? ? }
> +
> + ? ? ? regulators_np = of_find_node_by_name(pmic_np, "regulators");
> + ? ? ? if (!regulators_np) {
> + ? ? ? ? ? ? ? dev_err(iodev->dev, "could not find regulators sub-node\n");
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? /* count the number of regulators to be supported in pmic */
> + ? ? ? pdata->num_regulators = 0;
> + ? ? ? for_each_child_of_node(regulators_np, reg_np)
> + ? ? ? ? ? ? ? pdata->num_regulators++;
> +
> + ? ? ? rdata = devm_kzalloc(iodev->dev, sizeof(*rdata) *
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdata->num_regulators, GFP_KERNEL);
> + ? ? ? if (!rdata) {
> + ? ? ? ? ? ? ? dev_err(iodev->dev, "could not allocate memory for "
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "regulator data\n");
> + ? ? ? ? ? ? ? return -ENOMEM;
> + ? ? ? }
> +
> + ? ? ? pdata->regulators = rdata;
> + ? ? ? for_each_child_of_node(regulators_np, reg_np) {
> + ? ? ? ? ? ? ? for (i = 0; i < ARRAY_SIZE(regulators); i++)
> + ? ? ? ? ? ? ? ? ? ? ? if (!of_node_cmp(reg_np->name, regulators[i].name))
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? rdata->id = i;
> + ? ? ? ? ? ? ? rdata->initdata = of_get_regulator_init_data(
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? iodev->dev, reg_np);
> + ? ? ? ? ? ? ? rdata->reg_node = reg_np;
> + ? ? ? ? ? ? ? rdata++;
> + ? ? ? }
> +
> + ? ? ? if (of_get_property(pmic_np, "max8997,pmic-buck1-uses-gpio-dvs", NULL))
> + ? ? ? ? ? ? ? pdata->buck1_gpiodvs = true;
> +
> + ? ? ? if (of_get_property(pmic_np, "max8997,pmic-buck2-uses-gpio-dvs", NULL))
> + ? ? ? ? ? ? ? pdata->buck2_gpiodvs = true;
> +
> + ? ? ? if (of_get_property(pmic_np, "max8997,pmic-buck5-uses-gpio-dvs", NULL))
> + ? ? ? ? ? ? ? pdata->buck5_gpiodvs = true;
> +
> + ? ? ? if (pdata->buck1_gpiodvs || pdata->buck2_gpiodvs ||
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdata->buck5_gpiodvs) {
> + ? ? ? ? ? ? ? ret = max8997_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np);
> + ? ? ? ? ? ? ? if (ret)
> + ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;
> +
> + ? ? ? ? ? ? ? if (of_property_read_u32(pmic_np,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "max8997,pmic-buck125-default-dvs-idx",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &pdata->buck125_default_idx)) {
> + ? ? ? ? ? ? ? ? ? ? ? pdata->buck125_default_idx = 0;
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? if (pdata->buck125_default_idx >= 8) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdata->buck125_default_idx = 0;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dev_info(iodev->dev, "invalid value for "
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "default dvs index, using 0 instead\n");
> + ? ? ? ? ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? if (of_get_property(pmic_np,
> + ? ? ? ? ? ? ? ? ? ? ? "max8997,pmic-ignore-gpiodvs-side-effect", NULL))
> + ? ? ? ? ? ? ? ? ? ? ? pdata->ignore_gpiodvs_side_effect = true;
> +
> + ? ? ? ? ? ? ? dvs_voltage_nr = 8;
> + ? ? ? }
> +
> + ? ? ? if (of_property_read_u32_array(pmic_np,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "max8997,pmic-buck1-dvs-voltage",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdata->buck1_voltage, dvs_voltage_nr)) {
> + ? ? ? ? ? ? ? dev_err(iodev->dev, "buck1 voltages not specified\n");
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? if (of_property_read_u32_array(pmic_np,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "max8997,pmic-buck2-dvs-voltage",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdata->buck2_voltage, dvs_voltage_nr)) {
> + ? ? ? ? ? ? ? dev_err(iodev->dev, "buck2 voltages not specified\n");
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? if (of_property_read_u32_array(pmic_np,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "max8997,pmic-buck5-dvs-voltage",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdata->buck5_voltage, dvs_voltage_nr)) {
> + ? ? ? ? ? ? ? dev_err(iodev->dev, "buck5 voltages not specified\n");
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? return 0;
> +}
> +#else
> +static int max8997_pmic_dt_parse_pdata(struct max8997_dev *iodev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct max8997_platform_data *pdata)
> +{
> + ? ? ? return 0;
> +}
> +#endif /* CONFIG_OF */
> +
> ?static __devinit int max8997_pmic_probe(struct platform_device *pdev)
> ?{
> ? ? ? ?struct max8997_dev *iodev = dev_get_drvdata(pdev->dev.parent);
> - ? ? ? struct max8997_platform_data *pdata = dev_get_platdata(iodev->dev);
> + ? ? ? struct max8997_platform_data *pdata = iodev->pdata;
> ? ? ? ?struct regulator_dev **rdev;
> ? ? ? ?struct max8997_data *max8997;
> ? ? ? ?struct i2c_client *i2c;
> ? ? ? ?int i, ret, size;
> ? ? ? ?u8 max_buck1 = 0, max_buck2 = 0, max_buck5 = 0;
>
> - ? ? ? if (!pdata) {
> + ? ? ? if (IS_ERR_OR_NULL(pdata)) {
> ? ? ? ? ? ? ? ?dev_err(pdev->dev.parent, "No platform init data supplied.\n");
> ? ? ? ? ? ? ? ?return -ENODEV;
> ? ? ? ?}
>
> + ? ? ? if (iodev->dev->of_node) {
> + ? ? ? ? ? ? ? ret = max8997_pmic_dt_parse_pdata(iodev, pdata);
> + ? ? ? ? ? ? ? if (ret)
> + ? ? ? ? ? ? ? ? ? ? ? return ret;
> + ? ? ? }
> +
> ? ? ? ?max8997 = kzalloc(sizeof(struct max8997_data), GFP_KERNEL);
> ? ? ? ?if (!max8997)
> ? ? ? ? ? ? ? ?return -ENOMEM;
> @@ -1141,7 +1277,8 @@ static __devinit int max8997_pmic_probe(struct platform_device *pdev)
> ? ? ? ? ? ? ? ? ? ? ? ?regulators[id].n_voltages = 16;
>
> ? ? ? ? ? ? ? ?rdev[i] = regulator_register(&regulators[id], max8997->dev,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdata->regulators[i].initdata, max8997, NULL);
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdata->regulators[i].initdata, max8997,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdata->regulators[i].reg_node);
> ? ? ? ? ? ? ? ?if (IS_ERR(rdev[i])) {
> ? ? ? ? ? ? ? ? ? ? ? ?ret = PTR_ERR(rdev[i]);
> ? ? ? ? ? ? ? ? ? ? ? ?dev_err(max8997->dev, "regulator init failed for %d\n",
> diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
> index 830152c..6ae21bf 100644
> --- a/include/linux/mfd/max8997-private.h
> +++ b/include/linux/mfd/max8997-private.h
> @@ -316,6 +316,7 @@ enum max8997_irq {
> ?#define MAX8997_NUM_GPIO ? ? ? 12
> ?struct max8997_dev {
> ? ? ? ?struct device *dev;
> + ? ? ? struct max8997_platform_data *pdata;
> ? ? ? ?struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
> ? ? ? ?struct i2c_client *rtc; /* slave addr 0x0c */
> ? ? ? ?struct i2c_client *haptic; /* slave addr 0x90 */
> diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
> index 818486c..ba92375 100644
> --- a/include/linux/mfd/max8997.h
> +++ b/include/linux/mfd/max8997.h
> @@ -75,6 +75,7 @@ enum max8998_regulators {
> ?struct max8997_regulator_data {
> ? ? ? ?int id;
> ? ? ? ?struct regulator_init_data *initdata;
> + ? ? ? struct device_node *reg_node;
> ?};
>
> ?enum max8997_muic_usb_type {
> --
> 1.6.6.rc2
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html



-- 
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab, DMC Business, Samsung Electronics


From linus.walleij at linaro.org  Tue Mar 27 03:07:22 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Tue, 27 Mar 2012 09:07:22 +0200
Subject: [PATCH] amba-pl011: fix panic introduced by "clear pending
 interrupts"
In-Reply-To: <20120326203209.GA8182@mail.gnudd.com>
References: <20120326203209.GA8182@mail.gnudd.com>
Message-ID: <CACRpkdZXhJn241n8wMU8yUFwL7mpWrV3hP6C-_r_P1GGWgd_Og@mail.gmail.com>

On Mon, Mar 26, 2012 at 10:32 PM, Alessandro Rubini <rubini at gnudd.com> wrote:

> patch 9b96fba, currently in linux-next, clears interrupts using
> uap->port.membase that has not been assigned. ?My x86 system,
> that uses a pci-to-amba bridge, panics with a message like:
>
> ? BUG: unable to handle kernel NULL pointer dereference at 00000038
> ? IP: [<c12c85ed>] pl011_probe+0x119/0x303
>
> Signed-off-by: Alessandro Rubini <rubini at gnudd.com>
> Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi at st.com>

Yep I know, already sent the remedy, just waiting for Greg to pick it up:
http://marc.info/?l=linux-serial&m=133235774423240&w=2

But thanks for the quick attention :-)

Yours,
Linus Walleij


From shawn.guo at linaro.org  Tue Mar 27 03:23:19 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 15:23:19 +0800
Subject: [PATCH 00/10] clk: cleanup on basic clks
Message-ID: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>

The series makes some cleanup on basic clks.  Two patches from Mark
are folded here as they are doing the same thing.

Regards,
Shawn

---
Mark Brown (2):
      clk: fixed-rate: Don't open code kstrdup()
      clk: Constify parent name arrays

Shawn Guo (8):
      clk: use kzalloc in clk_register_mux
      clk: remove unnecessary EXPORT_SYMBOL_GPL
      clk: add "const" for clk_ops of basic clks
      clk: declare clk_ops of basic clks in clk-provider.h
      clk: align error return of basic clks registeration
      clk: fixed-rate: registration error handling fixup
      clk: dynamically allocate parent_names basic clk registration
      clk: copy parent_names in clk-mux registration

 drivers/clk/clk-divider.c    |   19 +++++++++++--------
 drivers/clk/clk-fixed-rate.c |   33 +++++++++++++++++----------------
 drivers/clk/clk-gate.c       |   20 ++++++++++++--------
 drivers/clk/clk-mux.c        |   39 +++++++++++++++++++++++++++++++--------
 drivers/clk/clk.c            |    2 +-
 include/linux/clk-private.h  |   10 +---------
 include/linux/clk-provider.h |   10 ++++++----
 7 files changed, 79 insertions(+), 54 deletions(-)


From shawn.guo at linaro.org  Tue Mar 27 03:23:20 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 15:23:20 +0800
Subject: [PATCH 01/10] clk: use kzalloc in clk_register_mux
In-Reply-To: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1332833009-4121-2-git-send-email-shawn.guo@linaro.org>

Change clk_register_mux to use kzalloc, just like what all other basic
clk registration functions do.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/clk/clk-mux.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index c71ad1f..50e0595 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -97,7 +97,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 {
 	struct clk_mux *mux;
 
-	mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL);
+	mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
 
 	if (!mux) {
 		pr_err("%s: could not allocate mux clk\n", __func__);
-- 
1.7.5.4



From shawn.guo at linaro.org  Tue Mar 27 03:23:21 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 15:23:21 +0800
Subject: [PATCH 02/10] clk: remove unnecessary EXPORT_SYMBOL_GPL
In-Reply-To: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1332833009-4121-3-git-send-email-shawn.guo@linaro.org>

It makes no sense to have EXPORT_SYMBOL_GPL on static functions.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/clk/clk-divider.c    |    3 ---
 drivers/clk/clk-fixed-rate.c |    1 -
 drivers/clk/clk-gate.c       |    3 ---
 drivers/clk/clk-mux.c        |    2 --
 4 files changed, 0 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index d5ac6a7..231cd6e 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -45,7 +45,6 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
 
 	return parent_rate / div;
 }
-EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
 
 /*
  * The reverse of DIV_ROUND_UP: The maximum number which
@@ -117,7 +116,6 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
 		return r / div;
 	}
 }
-EXPORT_SYMBOL_GPL(clk_divider_round_rate);
 
 static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
 {
@@ -147,7 +145,6 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(clk_divider_set_rate);
 
 struct clk_ops clk_divider_ops = {
 	.recalc_rate = clk_divider_recalc_rate,
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 90c79fb..651b06f 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -32,7 +32,6 @@ static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
 {
 	return to_clk_fixed_rate(hw)->fixed_rate;
 }
-EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate);
 
 struct clk_ops clk_fixed_rate_ops = {
 	.recalc_rate = clk_fixed_rate_recalc_rate,
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index b5902e2..b688f47 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -71,7 +71,6 @@ static int clk_gate_enable(struct clk_hw *hw)
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(clk_gate_enable);
 
 static void clk_gate_disable(struct clk_hw *hw)
 {
@@ -82,7 +81,6 @@ static void clk_gate_disable(struct clk_hw *hw)
 	else
 		clk_gate_clear_bit(gate);
 }
-EXPORT_SYMBOL_GPL(clk_gate_disable);
 
 static int clk_gate_is_enabled(struct clk_hw *hw)
 {
@@ -99,7 +97,6 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
 
 	return reg ? 1 : 0;
 }
-EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
 
 struct clk_ops clk_gate_ops = {
 	.enable = clk_gate_enable,
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 50e0595..45cad61 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -55,7 +55,6 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
 
 	return val;
 }
-EXPORT_SYMBOL_GPL(clk_mux_get_parent);
 
 static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 {
@@ -82,7 +81,6 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(clk_mux_set_parent);
 
 struct clk_ops clk_mux_ops = {
 	.get_parent = clk_mux_get_parent,
-- 
1.7.5.4



From shawn.guo at linaro.org  Tue Mar 27 03:23:22 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 15:23:22 +0800
Subject: [PATCH 03/10] clk: add "const" for clk_ops of basic clks
In-Reply-To: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1332833009-4121-4-git-send-email-shawn.guo@linaro.org>

The clk_ops of basic clks should have "const" to match the definition
in "struct clk" and clk_register prototype.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/clk/clk-divider.c    |    2 +-
 drivers/clk/clk-fixed-rate.c |    2 +-
 drivers/clk/clk-gate.c       |    2 +-
 drivers/clk/clk-mux.c        |    2 +-
 include/linux/clk-private.h  |    8 ++++----
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 231cd6e..b1c4b02 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -146,7 +146,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
 	return 0;
 }
 
-struct clk_ops clk_divider_ops = {
+const struct clk_ops clk_divider_ops = {
 	.recalc_rate = clk_divider_recalc_rate,
 	.round_rate = clk_divider_round_rate,
 	.set_rate = clk_divider_set_rate,
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 651b06f..027e477 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -33,7 +33,7 @@ static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
 	return to_clk_fixed_rate(hw)->fixed_rate;
 }
 
-struct clk_ops clk_fixed_rate_ops = {
+const struct clk_ops clk_fixed_rate_ops = {
 	.recalc_rate = clk_fixed_rate_recalc_rate,
 };
 EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index b688f47..fe2ff9e 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -98,7 +98,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
 	return reg ? 1 : 0;
 }
 
-struct clk_ops clk_gate_ops = {
+const struct clk_ops clk_gate_ops = {
 	.enable = clk_gate_enable,
 	.disable = clk_gate_disable,
 	.is_enabled = clk_gate_is_enabled,
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 45cad61..5424488 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -82,7 +82,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
 	return 0;
 }
 
-struct clk_ops clk_mux_ops = {
+const struct clk_ops clk_mux_ops = {
 	.get_parent = clk_mux_get_parent,
 	.set_parent = clk_mux_set_parent,
 };
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 5e4312b..5f4ccd7 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -55,7 +55,7 @@ struct clk {
  * alternative macro for static initialization
  */
 
-extern struct clk_ops clk_fixed_rate_ops;
+extern const struct clk_ops clk_fixed_rate_ops;
 
 #define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate,		\
 				_fixed_rate_flags)		\
@@ -78,7 +78,7 @@ extern struct clk_ops clk_fixed_rate_ops;
 		.flags = _flags,				\
 	};
 
-extern struct clk_ops clk_gate_ops;
+extern const struct clk_ops clk_gate_ops;
 
 #define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,	\
 				_flags, _reg, _bit_idx,		\
@@ -110,7 +110,7 @@ extern struct clk_ops clk_gate_ops;
 		.flags = _flags,				\
 	};
 
-extern struct clk_ops clk_divider_ops;
+extern const struct clk_ops clk_divider_ops;
 
 #define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
 				_flags, _reg, _shift, _width,	\
@@ -143,7 +143,7 @@ extern struct clk_ops clk_divider_ops;
 		.flags = _flags,				\
 	};
 
-extern struct clk_ops clk_mux_ops;
+extern const struct clk_ops clk_mux_ops;
 
 #define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags,	\
 				_reg, _shift, _width,		\
-- 
1.7.5.4



From shawn.guo at linaro.org  Tue Mar 27 03:23:23 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 15:23:23 +0800
Subject: [PATCH 04/10] clk: declare clk_ops of basic clks in clk-provider.h
In-Reply-To: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1332833009-4121-5-git-send-email-shawn.guo@linaro.org>

Besides the static initialization, the clk_ops of basic clks could
also be used by particular clk type being subclass of the basic clks.

For example, clk_busy_divider has the same clk_ops as clk_divider,
except it has to wait for a busy bit before return success with
.set_rate.  clk_busy_divider will somehow reuse clk_ops of clk_divider.

Since clk-provider.h is included by clk-private.h, it's safe to move
those clk_ops declaration of basic clks form  clk-private.h into
clk-provider.h, so that implementation of clks like clk_busy_divider
above do not need to include clk-private.h to access those clk_ops.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 include/linux/clk-private.h  |    8 --------
 include/linux/clk-provider.h |    4 ++++
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 5f4ccd7..f19fee0 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -55,8 +55,6 @@ struct clk {
  * alternative macro for static initialization
  */
 
-extern const struct clk_ops clk_fixed_rate_ops;
-
 #define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate,		\
 				_fixed_rate_flags)		\
 	static struct clk _name;				\
@@ -78,8 +76,6 @@ extern const struct clk_ops clk_fixed_rate_ops;
 		.flags = _flags,				\
 	};
 
-extern const struct clk_ops clk_gate_ops;
-
 #define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,	\
 				_flags, _reg, _bit_idx,		\
 				_gate_flags, _lock)		\
@@ -110,8 +106,6 @@ extern const struct clk_ops clk_gate_ops;
 		.flags = _flags,				\
 	};
 
-extern const struct clk_ops clk_divider_ops;
-
 #define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,	\
 				_flags, _reg, _shift, _width,	\
 				_divider_flags, _lock)		\
@@ -143,8 +137,6 @@ extern const struct clk_ops clk_divider_ops;
 		.flags = _flags,				\
 	};
 
-extern const struct clk_ops clk_mux_ops;
-
 #define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags,	\
 				_reg, _shift, _width,		\
 				_mux_flags, _lock)		\
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5508897..6eb8e5d 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -149,6 +149,7 @@ struct clk_fixed_rate {
 	u8		flags;
 };
 
+extern const struct clk_ops clk_fixed_rate_ops;
 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		unsigned long fixed_rate);
@@ -180,6 +181,7 @@ struct clk_gate {
 
 #define CLK_GATE_SET_TO_DISABLE		BIT(0)
 
+extern const struct clk_ops clk_gate_ops;
 struct clk *clk_register_gate(struct device *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 bit_idx,
@@ -218,6 +220,7 @@ struct clk_divider {
 #define CLK_DIVIDER_ONE_BASED		BIT(0)
 #define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
 
+extern const struct clk_ops clk_divider_ops;
 struct clk *clk_register_divider(struct device *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
@@ -252,6 +255,7 @@ struct clk_mux {
 #define CLK_MUX_INDEX_ONE		BIT(0)
 #define CLK_MUX_INDEX_BIT		BIT(1)
 
+extern const struct clk_ops clk_mux_ops;
 struct clk *clk_register_mux(struct device *dev, const char *name,
 		char **parent_names, u8 num_parents, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
-- 
1.7.5.4



From shawn.guo at linaro.org  Tue Mar 27 03:23:24 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 15:23:24 +0800
Subject: [PATCH 05/10] clk: align error return of basic clks registeration
In-Reply-To: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1332833009-4121-6-git-send-email-shawn.guo@linaro.org>

clk_register_gate and clk_register_divider return NULL for error,
which is aligned with clk_register function.  But clk_register_mux
and clk_register_fixed_rate return ERR_PTR.  Change them to return
NULL for better aligning with other registeration functions.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/clk/clk-fixed-rate.c |    2 +-
 drivers/clk/clk-mux.c        |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 027e477..d268439 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -50,7 +50,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 
 	if (!fixed) {
 		pr_err("%s: could not allocate fixed clk\n", __func__);
-		return ERR_PTR(-ENOMEM);
+		return NULL;
 	}
 
 	/* struct clk_fixed_rate assignments */
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 5424488..19f3116 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -99,7 +99,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 
 	if (!mux) {
 		pr_err("%s: could not allocate mux clk\n", __func__);
-		return ERR_PTR(-ENOMEM);
+		return NULL;
 	}
 
 	/* struct clk_mux assignments */
-- 
1.7.5.4



From shawn.guo at linaro.org  Tue Mar 27 03:23:25 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 15:23:25 +0800
Subject: [PATCH 06/10] clk: fixed-rate: Don't open code kstrdup()
In-Reply-To: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1332833009-4121-7-git-send-email-shawn.guo@linaro.org>

From: Mark Brown <broonie at opensource.wolfsonmicro.com>

Save a little code by using the library function.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 drivers/clk/clk-fixed-rate.c |    7 +------
 1 files changed, 1 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index d268439..1f87a03 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -44,7 +44,6 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 {
 	struct clk_fixed_rate *fixed;
 	char **parent_names = NULL;
-	u8 len;
 
 	fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
 
@@ -62,14 +61,10 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 		if (! parent_names)
 			goto out;
 
-		len = sizeof(char) * strlen(parent_name);
-
-		parent_names[0] = kmalloc(len, GFP_KERNEL);
+		parent_names[0] = kstrdup(parent_name, GFP_KERNEL);
 
 		if (!parent_names[0])
 			goto out;
-
-		strncpy(parent_names[0], parent_name, len);
 	}
 
 out:
-- 
1.7.5.4



From shawn.guo at linaro.org  Tue Mar 27 03:23:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 15:23:26 +0800
Subject: [PATCH 07/10] clk: Constify parent name arrays
In-Reply-To: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1332833009-4121-8-git-send-email-shawn.guo@linaro.org>

From: Mark Brown <broonie at opensource.wolfsonmicro.com>

Drivers should be able to declare their arrays of parent names as const
so the APIs need to accept const arguments.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 drivers/clk/clk-fixed-rate.c |    2 +-
 drivers/clk/clk-mux.c        |    2 +-
 drivers/clk/clk.c            |    2 +-
 include/linux/clk-private.h  |    2 +-
 include/linux/clk-provider.h |    6 +++---
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 1f87a03..295f0d5 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -43,7 +43,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 		unsigned long fixed_rate)
 {
 	struct clk_fixed_rate *fixed;
-	char **parent_names = NULL;
+	const char **parent_names = NULL;
 
 	fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
 
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 19f3116..1ff90a6 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -89,7 +89,7 @@ const struct clk_ops clk_mux_ops = {
 EXPORT_SYMBOL_GPL(clk_mux_ops);
 
 struct clk *clk_register_mux(struct device *dev, const char *name,
-		char **parent_names, u8 num_parents, unsigned long flags,
+		const char **parent_names, u8 num_parents, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_mux_flags, spinlock_t *lock)
 {
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 9cf6f59..33ef0df 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1322,7 +1322,7 @@ out:
  */
 struct clk *clk_register(struct device *dev, const char *name,
 		const struct clk_ops *ops, struct clk_hw *hw,
-		char **parent_names, u8 num_parents, unsigned long flags)
+		const char **parent_names, u8 num_parents, unsigned long flags)
 {
 	struct clk *clk;
 
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index f19fee0..e9c8b98 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -30,7 +30,7 @@ struct clk {
 	const struct clk_ops	*ops;
 	struct clk_hw		*hw;
 	struct clk		*parent;
-	char			**parent_names;
+	const char		**parent_names;
 	struct clk		**parents;
 	u8			num_parents;
 	unsigned long		rate;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 6eb8e5d..24c5013 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -214,7 +214,7 @@ struct clk_divider {
 	u8		width;
 	u8		flags;
 	spinlock_t	*lock;
-	char		*parent[1];
+	const char	*parent[1];
 };
 
 #define CLK_DIVIDER_ONE_BASED		BIT(0)
@@ -257,7 +257,7 @@ struct clk_mux {
 
 extern const struct clk_ops clk_mux_ops;
 struct clk *clk_register_mux(struct device *dev, const char *name,
-		char **parent_names, u8 num_parents, unsigned long flags,
+		const char **parent_names, u8 num_parents, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_mux_flags, spinlock_t *lock);
 
@@ -278,7 +278,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
  */
 struct clk *clk_register(struct device *dev, const char *name,
 		const struct clk_ops *ops, struct clk_hw *hw,
-		char **parent_names, u8 num_parents, unsigned long flags);
+		const char **parent_names, u8 num_parents, unsigned long flags);
 
 /* helper functions */
 const char *__clk_get_name(struct clk *clk);
-- 
1.7.5.4



From shawn.guo at linaro.org  Tue Mar 27 03:23:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 15:23:27 +0800
Subject: [PATCH 08/10] clk: fixed-rate: registration error handling fixup
In-Reply-To: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1332833009-4121-9-git-send-email-shawn.guo@linaro.org>

The clk_register_fixed_rate should not call clk_register on "out:"
path.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/clk/clk-fixed-rate.c |   19 +++++++++++++------
 1 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 295f0d5..0d80827 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -43,6 +43,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 		unsigned long fixed_rate)
 {
 	struct clk_fixed_rate *fixed;
+	struct clk *clk;
 	const char **parent_names = NULL;
 
 	fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
@@ -56,21 +57,27 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 	fixed->fixed_rate = fixed_rate;
 
 	if (parent_name) {
-		parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
-
-		if (! parent_names)
+		parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
+		if (!parent_names)
 			goto out;
 
 		parent_names[0] = kstrdup(parent_name, GFP_KERNEL);
-
 		if (!parent_names[0])
 			goto out;
 	}
 
-out:
-	return clk_register(dev, name,
+	clk = clk_register(dev, name,
 			&clk_fixed_rate_ops, &fixed->hw,
 			parent_names,
 			(parent_name ? 1 : 0),
 			flags);
+	if (clk)
+		return clk;
+
+out:
+	kfree(parent_names[0]);
+	kfree(parent_names);
+	kfree(fixed);
+
+	return NULL;
 }
-- 
1.7.5.4



From shawn.guo at linaro.org  Tue Mar 27 03:23:28 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 15:23:28 +0800
Subject: [PATCH 09/10] clk: dynamically allocate parent_names basic clk
 registration
In-Reply-To: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1332833009-4121-10-git-send-email-shawn.guo@linaro.org>

It's not necessary to have "char *parent[1]" carried in struct clk_gate
and clk_divider.  Instead, it can be dynamically allocated in
registration function, just like what clk_register_fixed_rate does.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/clk/clk-divider.c    |   14 ++++++++++----
 drivers/clk/clk-gate.c       |   15 +++++++++++----
 include/linux/clk-provider.h |    2 --
 3 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index b1c4b02..df03a61 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -160,6 +160,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
 {
 	struct clk_divider *div;
 	struct clk *clk;
+	const char **parent_names = NULL;
 
 	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
 
@@ -176,21 +177,26 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
 	div->lock = lock;
 
 	if (parent_name) {
-		div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
-		if (!div->parent[0])
+		parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
+		if (!parent_names)
+			goto out;
+
+		parent_names[0] = kstrdup(parent_name, GFP_KERNEL);
+		if (!parent_names[0])
 			goto out;
 	}
 
 	clk = clk_register(dev, name,
 			&clk_divider_ops, &div->hw,
-			div->parent,
+			parent_names,
 			(parent_name ? 1 : 0),
 			flags);
 	if (clk)
 		return clk;
 
 out:
-	kfree(div->parent[0]);
+	kfree(parent_names[0]);
+	kfree(parent_names);
 	kfree(div);
 
 	return NULL;
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index fe2ff9e..51c56cb 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -112,6 +112,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 {
 	struct clk_gate *gate;
 	struct clk *clk;
+	const char **parent_names = NULL;
 
 	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
 
@@ -127,20 +128,26 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 	gate->lock = lock;
 
 	if (parent_name) {
-		gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
-		if (!gate->parent[0])
+		parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
+		if (!parent_names)
+			goto out;
+
+		parent_names[0] = kstrdup(parent_name, GFP_KERNEL);
+		if (parent_names[0])
 			goto out;
 	}
 
 	clk = clk_register(dev, name,
 			&clk_gate_ops, &gate->hw,
-			gate->parent,
+			parent_names,
 			(parent_name ? 1 : 0),
 			flags);
 	if (clk)
 		return clk;
+
 out:
-	kfree(gate->parent[0]);
+	kfree(parent_names[0]);
+	kfree(parent_names);
 	kfree(gate);
 
 	return NULL;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 24c5013..7948640 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -176,7 +176,6 @@ struct clk_gate {
 	u8		bit_idx;
 	u8		flags;
 	spinlock_t	*lock;
-	char		*parent[1];
 };
 
 #define CLK_GATE_SET_TO_DISABLE		BIT(0)
@@ -214,7 +213,6 @@ struct clk_divider {
 	u8		width;
 	u8		flags;
 	spinlock_t	*lock;
-	const char	*parent[1];
 };
 
 #define CLK_DIVIDER_ONE_BASED		BIT(0)
-- 
1.7.5.4



From shawn.guo at linaro.org  Tue Mar 27 03:23:29 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 15:23:29 +0800
Subject: [PATCH 10/10] clk: copy parent_names in clk-mux registration
In-Reply-To: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1332833009-4121-11-git-send-email-shawn.guo@linaro.org>

Just like what all other basic clks do, copy parent_names in clk-mux
registration, so that clock driver can mark the parent_names
__initconst.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/clk/clk-mux.c |   29 +++++++++++++++++++++++++++--
 1 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 1ff90a6..353fcb7 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -94,6 +94,9 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 		u8 clk_mux_flags, spinlock_t *lock)
 {
 	struct clk_mux *mux;
+	struct clk *clk;
+	const char **parents = NULL;
+	int i = 0;
 
 	mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
 
@@ -109,6 +112,28 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
 	mux->flags = clk_mux_flags;
 	mux->lock = lock;
 
-	return clk_register(dev, name, &clk_mux_ops, &mux->hw,
-			parent_names, num_parents, flags);
+	if (num_parents) {
+		parents = kzalloc(sizeof(char *) * num_parents, GFP_KERNEL);
+		if (!parents)
+			goto out;
+
+		for (i = 0; i < num_parents; i++) {
+			parents[i] = kstrdup(parent_names[i], GFP_KERNEL);
+			if (!parents[i])
+				goto out;
+		}
+	}
+
+	clk =  clk_register(dev, name, &clk_mux_ops, &mux->hw,
+			parents, num_parents, flags);
+	if (clk)
+		return clk;
+
+out:
+	for (i--; i >= 0; i--)
+		kfree(parents[i]);
+	kfree(parents);
+	kfree(mux);
+
+	return NULL;
 }
-- 
1.7.5.4



From joancarles at fqingenieria.es  Tue Mar 27 03:32:36 2012
From: joancarles at fqingenieria.es (joancarles)
Date: Tue, 27 Mar 2012 09:32:36 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
Message-ID: <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>

G'day

This is still present, and we have absolutely no idea where to continue 
searching for the solution of the problem. Any pointers? Any git trees 
of mmc driver changes we could try? Anybody else with a MX25 that has 
this issue?

>> Hi:
>> -110 is the timeout problem.
>> You can dump the esdhc registers if you want to debug into this 
>> issue
>> when this timeout problem occurred.
>> The register dump can help to figure out what's wrong on the bus.
>
> I have no familiarity with the SDHC drivers, so there's nothing
> useful for me in the output as of this moment:
>
> [ 1080.818765] sdhci: ===========================================
> [ 1080.818830] mmc0: req done (CMD17): 0: 00000900 00000000 00000000 
> 00000000
> [ 1080.818862] mmc0:     512 bytes transferred: 0
> [ 1080.819395] mmc0: starting CMD24 arg 00008800 flags 000000b5
> [ 1080.819444] mmc0:     blksz 512 blocks 1 flags 00000100 tsac 300 
> ms nsac 0
> [ 1080.819544] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000009
> [ 1080.819595] sdhci [sdhci_data_irq()]: mmc0: DMA base 0x82547c00,
> transferred 0x038400 bytes, next 0x82580000
> [ 1080.819630] sdhci: =========== REGISTER DUMP (mmc0)===========
> [ 1080.819658] sdhci: Sys addr: 0x82547e00 | Version:  0x00000000
> [ 1080.819683] sdhci: Blk size: 0x00000200 | Blk cnt:  0x00000000
> [ 1080.819707] sdhci: Argument: 0x00008800 | Trn mode: 0x00000003
> [ 1080.819732] sdhci: Present:  0xfe880006 | Host ctl: 0x00000023
> [ 1080.819756] sdhci: Power:    0x00000000 | Blk gap:  0x00000000
> [ 1080.819780] sdhci: Wake-up:  0x00000000 | Clock:    0x00000107
> [ 1080.819804] sdhci: Timeout:  0x0000000c | Int stat: 0x00100002
> [ 1080.819830] sdhci: Int enab: 0x107f000b | Sig enab: 0x107f000b
> [ 1080.819854] sdhci: AC12 err: 0x00000000 | Slot int: 0x00001001
> [ 1080.819879] sdhci: Caps:     0x07eb0000 | Caps_1:   0x04100410
> [ 1080.819904] sdhci: Cmd:      0x0000183a | Max curr: 0x00000000
> [ 1080.819926] sdhci: Host ctl2: 0x00000000
> [ 1080.819942] sdhci: ===========================================
> [ 1080.819985] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00100002
> [ 1080.820048] mmc0: req done (CMD24): 0: 00000900 00000000 00000000 
> 00000000
> [ 1080.820082] mmc0:     0 bytes transferred: -110
> [ 1080.820134] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1080.820201] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.820259] mmc0: req done (CMD13): 0: 00000e00 00000000 00000000 
> 00000000
> [ 1080.820330] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1080.820391] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.820445] mmc0: req done (CMD13): 0: 00000e00 00000000 00000000 
> 00000000
> [ 1080.820504] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1080.820572] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.820627] mmc0: req done (CMD13): 0: 00000e00 00000000 00000000 
> 00000000
> [ 1080.820785] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1080.820879] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.820946] mmc0: req done (CMD13): 0: 00000e00 00000000 00000000 
> 00000000
> [ 1080.821021] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1080.821085] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.821140] mmc0: req done (CMD13): 0: 00000e00 00000000 00000000 
> 00000000
> [ 1080.821197] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1080.821255] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.821308] mmc0: req done (CMD13): 0: 00000e00 00000000 00000000 
> 00000000
> [ 1080.824944] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1080.825041] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.825112] mmc0: req done (CMD13): 0: 00000e00 00000000 00000000 
> 00000000
> [ 1080.825186] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1080.825248] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.825302] mmc0: req done (CMD13): 0: 00000e00 00000000 00000000 
> 00000000
> [ 1080.825364] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1080.825432] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.825485] mmc0: req done (CMD13): 0: 00000e00 00000000 00000000 
> 00000000
> [ 1080.825640] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1080.825736] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.825803] mmc0: req done (CMD13): 0: 00000900 00000000 00000000 
> 00000000
> [ 1080.825883] mmcblk0: error -110 transferring data, sector 68, nr
> 1, cmd response 0x900, card status 0x0
> [ 1080.849435] mmc0: starting CMD55 arg 00020000 flags 00000095
> [ 1080.849531] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.849596] mmc0: req done (CMD55): 0: 00000920 00000000 00000000 
> 00000000
> [ 1080.850319] mmc0: starting CMD22 arg 00000000 flags 000000b5
> [ 1080.850367] mmc0:     blksz 4 blocks 1 flags 00000200 tsac 100 ms 
> nsac 0
> [ 1080.850468] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.850523] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x0020000a
> [ 1080.850591] mmc0: req done (CMD22): 0: 00000920 00000000 00000000 
> 00000000
> [ 1080.850624] mmc0:     0 bytes transferred: -84
> [ 1080.851339] end_request: I/O error, dev mmcblk0, sector 68
> [ 1080.856881] Buffer I/O error on device mmcblk0p1, logical block 6
> [ 1080.862998] lost page write due to I/O error on mmcblk0p1
> [ 1080.897203] mmc0: starting CMD17 arg 00008800 flags 000000b5
> [ 1080.897250] mmc0:     blksz 512 blocks 1 flags 00000200 tsac 100 
> ms nsac 0
> [ 1080.897350] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.898143] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x0020000a
> [ 1080.898241] mmc0: req done (CMD17): 0: 00000900 00000000 00000000 
> 00000000
> [ 1080.898276] mmc0:     0 bytes transferred: -84
> [ 1080.898949] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1080.899134] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1080.899204] mmc0: req done (CMD13): 0: 00000900 00000000 00000000 
> 00000000
> [ 1080.899284] mmcblk0: error -84 transferring data, sector 68, nr 1,
> cmd response 0x900, card status 0x0
> [ 1080.908738] end_request: I/O error, dev mmcblk0, sector 68
> [ 1080.914465] FAT-fs (mmcblk0p1): FAT read failed (blocknr 6)
> [ 1085.809683] mmc0: starting CMD24 arg 00045e00 flags 000000b5
> [ 1085.809731] mmc0:     blksz 512 blocks 1 flags 00000100 tsac 300 
> ms nsac 0
> [ 1085.809831] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000009
> [ 1085.809880] sdhci [sdhci_data_irq()]: mmc0: DMA base 0x82548200,
> transferred 0x037e00 bytes, next 0x82580000
> [ 1085.809914] sdhci: =========== REGISTER DUMP (mmc0)===========
> [ 1085.809941] sdhci: Sys addr: 0x82548400 | Version:  0x00000000
> [ 1085.809967] sdhci: Blk size: 0x00000200 | Blk cnt:  0x00000000
> [ 1085.809992] sdhci: Argument: 0x00045e00 | Trn mode: 0x00000003
> [ 1085.810017] sdhci: Present:  0xff880000 | Host ctl: 0x00000021
> [ 1085.810042] sdhci: Power:    0x00000000 | Blk gap:  0x00000000
> [ 1085.810067] sdhci: Wake-up:  0x00000000 | Clock:    0x00000107
> [ 1085.810093] sdhci: Timeout:  0x0000000c | Int stat: 0x00200002
> [ 1085.810119] sdhci: Int enab: 0x107f000b | Sig enab: 0x107f000b
> [ 1085.810143] sdhci: AC12 err: 0x00000000 | Slot int: 0x00001001
> [ 1085.810169] sdhci: Caps:     0x07eb0000 | Caps_1:   0x04100410
> [ 1085.810193] sdhci: Cmd:      0x0000183a | Max curr: 0x00000000
> [ 1085.810214] sdhci: Host ctl2: 0x00000000
> [ 1085.810232] sdhci: ===========================================
> [ 1085.810275] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00200002
> [ 1085.810340] mmc0: req done (CMD24): 0: 00000900 00000000 00000000 
> 00000000
> [ 1085.810373] mmc0:     0 bytes transferred: -84
> [ 1085.810427] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1085.810489] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1085.810543] mmc0: req done (CMD13): 0: 00000900 00000000 00000000 
> 00000000
> [ 1085.810616] mmc0: starting CMD13 arg 00020000 flags 00000195
> [ 1085.810690] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1085.810747] mmc0: req done (CMD13): 0: 00000900 00000000 00000000 
> 00000000
> [ 1085.810838] mmcblk0: error -84 transferring data, sector 559, nr
> 1, cmd response 0x900, card status 0x0
> [ 1085.834557] mmc0: starting CMD55 arg 00020000 flags 00000095
> [ 1085.834651] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1085.834722] mmc0: req done (CMD55): 0: 00000920 00000000 00000000 
> 00000000
> [ 1085.834802] mmc0: starting CMD22 arg 00000000 flags 000000b5
> [ 1085.834839] mmc0:     blksz 4 blocks 1 flags 00000200 tsac 100 ms 
> nsac 0
> [ 1085.834915] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x00000001
> [ 1085.834986] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 
> 0x0020000a
> [ 1085.835056] mmc0: req done (CMD22): 0: 00000920 00000000 00000000 
> 00000000
>
> What else can I provide you with? The MMC/SDHC/eSDHC driver framework
> is a huge piece of software, so I don't really know where to start
> looking. Electrically, there seems nothing really wrong with the
> signal of the clock; the only thing that looks a wee bit suspicious 
> is
> that the MX25 clock for the SDHC is currently offering a 33MHz signal
> (as gathered from the oscilloscope).

-- 
Joan C. Abelaira


From linux at arm.linux.org.uk  Tue Mar 27 03:40:39 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 27 Mar 2012 08:40:39 +0100
Subject: [PATCH 2/2] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <00d501cd0bb0$724ab260$56e01720$%kim@samsung.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <00d501cd0bb0$724ab260$56e01720$%kim@samsung.com>
Message-ID: <20120327074039.GJ5611@n2100.arm.linux.org.uk>

On Tue, Mar 27, 2012 at 09:27:52AM +0900, Boojin Kim wrote:
> This patch uses LDRD/STRD that loads and stores data as DWORD unit.
> It brings better performance than LDRM/STRM with cortex-a15.

Why should I bother looking at this rubbish?  You've been told before
that using ldrd and strd unconditionally is not acceptable.  Stop
wasting peoples review time.


From linux at arm.linux.org.uk  Tue Mar 27 03:49:31 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 27 Mar 2012 08:49:31 +0100
Subject: [CPUFREQ] Fix exposure of ARM_EXYNOS4210_CPUFREQ
In-Reply-To: <00aa01ccf084$93c98a70$bb5c9f50$%kim@samsung.com>
References: <20120213094940.GA15338@n2100.arm.linux.org.uk>
 <4F3CF3DA.7000806@samsung.com>
 <20120216160250.GP13673@n2100.arm.linux.org.uk>
 <00aa01ccf084$93c98a70$bb5c9f50$%kim@samsung.com>
Message-ID: <20120327074931.GK5611@n2100.arm.linux.org.uk>

On Tue, Feb 21, 2012 at 07:35:49PM +0900, Kukjin Kim wrote:
> Russell King - ARM Linux wrote:
> > 
> > On Thu, Feb 16, 2012 at 09:17:30PM +0900, Kukjin Kim wrote:
> > > On 02/13/12 18:49, Russell King - ARM Linux wrote:
> > >> From: Russell King<rmk+kernel at arm.linux.org.uk>
> > >>
> > >> exynos4210-cpufreq.c is not buildable on non-exynos builds, so it's
> > >> pointless allowing this option to be exposed.  Fix this by adding a
> > >> dependency on ARCH_EXYNOS.
> > >>
> > >> drivers/cpufreq/exynos4210-cpufreq.c:20:29: error: mach/regs-clock.h:
> > No such file or directory
> > >> drivers/cpufreq/exynos4210-cpufreq.c:21:26: error: mach/cpufreq.h: No
> > such file or directory
> > >>
> > >> Signed-off-by: Russell King<rmk+kernel at arm.linux.org.uk>
> > >> Cc: Dave Jones<davej at redhat.com>
> > >> Cc: cpufreq at vger.kernel.org
> > >> Cc: Kukjin Kim<kgene.kim at samsung.com>
> > >> ---
> > >>   drivers/cpufreq/Kconfig.arm |    1 +
> > >>   1 files changed, 1 insertions(+), 0 deletions(-)
> > >>
> > >> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> > >> index e0664fe..c8bde43 100644
> > >> --- a/drivers/cpufreq/Kconfig.arm
> > >> +++ b/drivers/cpufreq/Kconfig.arm
> > >> @@ -34,6 +34,7 @@ config ARM_EXYNOS_CPUFREQ
> > >>
> > >>   config ARM_EXYNOS4210_CPUFREQ
> > >>   	bool "Samsung EXYNOS4210"
> > >> +	depends on ARCH_EXYNOS
> > >>   	help
> > >>   	  This adds the CPUFreq driver for Samsung EXYNOS4210
> > >>   	  SoC (S5PV310 or S5PC210).
> > >>
> > >
> > > Yes, you're right. Should be added it.
> > > BTW, how about following?
> > >
> > > diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> > > index e0664fe..a5e0487 100644
> > > --- a/drivers/cpufreq/Kconfig.arm
> > > +++ b/drivers/cpufreq/Kconfig.arm
> > > @@ -33,7 +33,7 @@ config ARM_EXYNOS_CPUFREQ
> > >           If in doubt, say N.
> > >
> > >  config ARM_EXYNOS4210_CPUFREQ
> > > -       bool "Samsung EXYNOS4210"
> > > +       bool
> > >         help
> > >           This adds the CPUFreq driver for Samsung EXYNOS4210
> > >           SoC (S5PV310 or S5PC210).
> > >
> > > I think, when selecting "ARM_EXYNOS_CPUFREQ", "ARM_EXYNOS4210_CPUFREQ"
> > > will be selected on EXYNOS4210 with above changes.
> > 
> Hi Russell,
> 
> > I don't think so.  If you select this symbol you'll get a complaint
> > that CPU_FREQ is not selected.
> 
> Hmm..when I selected this symbol, I didn't get any warning about CPU_FREQ,
> because the cpufreq/Kconfig.arm depends on CPU_FREQ. It means, when CPU_FREQ
> is not selected, I can't select anything in cpufreq/Kconfig.arm.
> 
> > What's probably much better is:
> > 
> Yes, looks better than mine.
> 
> > config ARM_EXYNOS4210_CPUFREQ
> > 	def_bool ARCH_EXYNOS
> 
> But, should be...
> 	def_bool CPU_EXYNOS4210
> 
> Because the ARM_EXYNOS4210_CPUFREQ is only for EXYNOS4210 and the
> ARM_EXYNOS4X12_CPUFREQ will be added, actually submitted for other
> SOC_EXYNOS4212 and SOC_EXYNOS4412.
> 
> > 
> > because that ensures that if the CPU_FREQ dependencies change you don't
> > have to update numerous places for that too.
> 
> OK, I agree.
> 
> So could you  please re-send/re-work this?

As predicted, this is breaking other ARM platforms.  Please fix this
yourself before your crappy code gets pushed into mainline.  Thanks.


From paul.liu at linaro.org  Tue Mar 27 03:54:01 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Tue, 27 Mar 2012 15:54:01 +0800
Subject: [PATCH] Regulator: anatop-regulator: patching to device-tree property
 "reg".
Message-ID: <1332834841-13925-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Change "reg" to "anatop-reg-offset" due to there is a warning of handling no
size field in reg.

This patch also adds the missing device-tree binding documentation.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Liam Girdwood <lrg at ti.com>
---
 .../bindings/regulator/anatop-regulator.txt        |   29 ++++++++++++++++++++
 drivers/regulator/anatop-regulator.c               |    5 ++-
 2 files changed, 32 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.txt

diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
new file mode 100644
index 0000000..357758c
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -0,0 +1,29 @@
+Anatop Voltage regulators
+
+Required properties:
+- compatible: Must be "fsl,anatop-regulator"
+- anatop-reg-offset: Anatop MFD register offset
+- anatop-vol-bit-shift: Bit shift for the register
+- anatop-vol-bit-width: Number of bits used in the register
+- anatop-min-bit-val: Minimum value of this register
+- anatop-min-voltage: Minimum voltage of this regulator
+- anatop-max-voltage: Maximum voltage of this regulator
+
+Any property defined as part of the core regulator
+binding, defined in regulator.txt, can also be used.
+
+Example:
+
+	regulator-vddpu {
+		compatible = "fsl,anatop-regulator";
+		regulator-name = "vddpu";
+		regulator-min-microvolt = <725000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-always-on;
+		anatop-reg-offset = <0x140>;
+		anatop-vol-bit-shift = <9>;
+		anatop-vol-bit-width = <5>;
+		anatop-min-bit-val = <1>;
+		anatop-min-voltage = <725000>;
+		anatop-max-voltage = <1300000>;
+	};
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
index 17499a5..53969af 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -138,9 +138,10 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
 	rdesc->type = REGULATOR_VOLTAGE;
 	rdesc->owner = THIS_MODULE;
 	sreg->mfd = anatopmfd;
-	ret = of_property_read_u32(np, "reg", &sreg->control_reg);
+	ret = of_property_read_u32(np, "anatop-reg-offset",
+				   &sreg->control_reg);
 	if (ret) {
-		dev_err(dev, "no reg property set\n");
+		dev_err(dev, "no anatop-reg-offset property set\n");
 		goto anatop_probe_end;
 	}
 	ret = of_property_read_u32(np, "anatop-vol-bit-width",
-- 
1.7.9.1



From linux at arm.linux.org.uk  Tue Mar 27 03:56:00 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 27 Mar 2012 08:56:00 +0100
Subject: [PATCH v8 RESEND] ARM: net: JIT compiler for packet filters
In-Reply-To: <20120325133506.GG5611@n2100.arm.linux.org.uk>
References: <1331933316-10197-1-git-send-email-mgherzan@gmail.com>
 <20120319.172005.1889334604020296555.davem@davemloft.net>
 <4F6EEAB5.7070009@gmail.com> <20120325095711.GC5611@n2100.arm.linux.org.uk>
 <4F6F19C2.60602@gmail.com> <20120325133506.GG5611@n2100.arm.linux.org.uk>
Message-ID: <20120327075600.GL5611@n2100.arm.linux.org.uk>

Mircea, could you please supply an ack for the below fix to silence a
warning.  Thanks.

8<=====
ARM: fix Kconfig warning for HAVE_BPF_JIT

Last night's randconfig and the allnoconfig builds spat out the
following warning while building:

warning: (ARM) selects HAVE_BPF_JIT which has unmet direct dependencies (NET)

Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
---
 arch/arm/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9e21b6e..6a54606 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -33,7 +33,7 @@ config ARM
 	select GENERIC_IRQ_SHOW
 	select CPU_PM if (SUSPEND || CPU_IDLE)
 	select GENERIC_PCI_IOMAP
-	select HAVE_BPF_JIT
+	select HAVE_BPF_JIT if NET
 	help
 	  The ARM series is a line of low-power-consumption RISC chip designs
 	  licensed by ARM Ltd and targeted at embedded applications and


From joancarles at fqingenieria.es  Tue Mar 27 03:59:48 2012
From: joancarles at fqingenieria.es (joancarles)
Date: Tue, 27 Mar 2012 09:59:48 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
Message-ID: <e96253f3ad8c336db8ff86c3b9ab57e1@mail.fqingenieria.es>

ADDENDUM:

On Tue, 27 Mar 2012 09:32:36 +0200, joancarles wrote:
> G'day
>
> This is still present, and we have absolutely no idea where to
> continue searching for the solution of the problem. Any pointers? Any
> git trees of mmc driver changes we could try? Anybody else with a 
> MX25
> that has this issue?

Enabling CONFIG_MMC_CLKGATE, I have managed to create an oops simply be 
trying to remove a file:

[  192.821592] mmcblk0: error -110 transferring data, sector 559, nr 1, 
cmd response 0x900, card status 0x0
[  192.846928] mmc0: starting CMD55 arg 00020000 flags 00000095
[  192.846991] mmc0: clock 50000000Hz busmode 2 powermode 2 cs 0 Vdd 17 
width 2 timing 2
[  192.847048] sdhci-esdhc-imx sdhci-esdhc-imx25.0: desired SD clock: 
50000000, actual: 33250000
[  192.848090] mmc0: ungated MCI clock
[  192.848159] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 0x00000001
[  192.848221] mmc0: req done (CMD55): 0: 00000920 00000000 00000000 
00000000
[  192.848353] mmc0: clock 0Hz busmode 2 powermode 2 cs 0 Vdd 17 width 
2 timing 2
[  192.848400] mmc0: gated MCI clock
[  192.848458] Division by zero in kernel.
[  192.852384] [<c00141f0>] (unwind_backtrace+0x0/0x130) from 
[<c01c0bb4>] (Ldiv0+0x8/0x10)
[  192.867389] [<c01c0bb4>] (Ldiv0+0x8/0x10) from [<c029b288>] 
(mmc_sd_num_wr_blocks+0x148/0x230)
[  192.876924] [<c029b288>] (mmc_sd_num_wr_blocks+0x148/0x230) from 
[<c029c900>] (mmc_blk_issue_rw_rq+0x3fc/0x4ac)
[  192.887944] [<c029c900>] (mmc_blk_issue_rw_rq+0x3fc/0x4ac) from 
[<c029cbe8>] (mmc_blk_issue_rq+0x238/0x514)
[  192.898606] [<c029cbe8>] (mmc_blk_issue_rq+0x238/0x514) from 
[<c029d3b8>] (mmc_queue_thread+0x58/0x144)
[  192.908879] [<c029d3b8>] (mmc_queue_thread+0x58/0x144) from 
[<c0038b44>] (kthread+0x84/0x90)
[  192.918477] [<c0038b44>] (kthread+0x84/0x90) from [<c000f9a0>] 
(kernel_thread_exit+0x0/0x8)
[  192.927654] mmc0: starting CMD22 arg 00000000 flags 000000b5
[  192.927700] mmc0:     blksz 4 blocks 1 flags 00000200 tsac 100 ms 
nsac 0
[  192.927752] mmc0: clock 50000000Hz busmode 2 powermode 2 cs 0 Vdd 17 
width 2 timing 2
[  192.927810] sdhci-esdhc-imx sdhci-esdhc-imx25.0: desired SD clock: 
50000000, actual: 33250000
[  192.928852] mmc0: ungated MCI clock
[  192.928940] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 0x00000001
[  192.928991] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 0x0000000a
[  192.929031] sdhci [sdhci_data_irq()]: mmc0: DMA base 0x839a3040, 
transferred 0x05cfc0 bytes, next 0x83a00000
[  192.929094] mmc0: req done (CMD22): 0: 00000920 00000000 00000000 
00000000
[  192.929126] mmc0:     4 bytes transferred: 0
[  192.929242] mmc0: clock 0Hz busmode 2 powermode 2 cs 0 Vdd 17 width 
2 timing 2
[  192.929288] mmc0: gated MCI clock

Maybe this helps. The file, in fact, has been removed, as far as I can 
see. Also, how come, the actual clock differs so much from the desired 
clock of 50MHz? As commented before, we do actually see the 33.25MHz 
clock in the oscilloscope.

Best regards
-- 
Joan C. Abelaira



From eric at eukrea.com  Tue Mar 27 04:12:59 2012
From: eric at eukrea.com (Eric =?ISO-8859-1?B?QuluYXJk?=)
Date: Tue, 27 Mar 2012 10:12:59 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
Message-ID: <20120327101259.73525f9d@eb-e6520>

Hi,

Le Tue, 27 Mar 2012 09:32:36 +0200,
joancarles <joancarles at fqingenieria.es> a ?crit :

> G'day
> 
> This is still present, and we have absolutely no idea where to continue 
> searching for the solution of the problem. Any pointers? Any git trees 
> of mmc driver changes we could try? Anybody else with a MX25 that has 
> this issue?
> 
does that attached patch fix your problem ?

Eric
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From bryan.wu at canonical.com  Tue Mar 27 04:19:01 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Tue, 27 Mar 2012 16:19:01 +0800
Subject: =?UTF-8?Q?Question=EF=BC=9ALeds_handling_in_drivers?=
Message-ID: <CAK5ve-+p=RS00V=bmaCU6jYtX1R3X71dS4H7Zqd_f=UWQfVp+w@mail.gmail.com>

Russell,

I'm still working on the LEDS consolidation stuff and try to convert
the old style to LED CPU trigger driver [1].

But in drivers/char/nwflash.c:
---
$ grep leds_event drivers/char/nwflash.c
	leds_event(led_claim);
	leds_event(led_green_on);
	leds_event(led_release);
	leds_event(led_amber_on);
	leds_event(led_amber_off);
	leds_event(led_red_on);
				leds_event(led_amber_off);
				leds_event(led_red_on);
	leds_event(led_amber_off);
	leds_event(led_green_on);
---

It looks like very difficult to fit this in LEDS CPU trigger driver,
looks like an new LEDS trigger driver to indicate FLASH
reading/writing/verifying activities.
How do you think of this? Any suggestion?

[1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/088639.html

Thanks,
-- 
Bryan Wu <bryan.wu at canonical.com>
Kernel Developer ? ?+86.138-1617-6545 Mobile
Canonical Ltd. ? ? ?www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com


From shc_work at mail.ru  Tue Mar 27 04:22:49 2012
From: shc_work at mail.ru (Alexander Shiyan)
Date: Tue, 27 Mar 2012 12:22:49 +0400
Subject: [PATCH] ARM: clps711x: serial driver hungs are a result of call
 disable_irq within ISR
Message-ID: <1332836569-11726-1-git-send-email-shc_work@mail.ru>

Since 2.6.30-rc1 clps711x serial driver hungs system. This is a result
of call disable_irq from ISR. synchronize_irq waits for end of interrupt
and goes to infinite loop. This patch fix this problem.

Signed-off-by: Alexander Shiyan <shc_work at mail.ru>
---
 drivers/tty/serial/clps711x.c |   14 ++++++++------
 1 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c
index e6c3dbd..836fe273 100644
--- a/drivers/tty/serial/clps711x.c
+++ b/drivers/tty/serial/clps711x.c
@@ -154,10 +154,9 @@ static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id)
 		port->x_char = 0;
 		return IRQ_HANDLED;
 	}
-	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
-		clps711xuart_stop_tx(port);
-		return IRQ_HANDLED;
-	}
+
+	if (uart_circ_empty(xmit) || uart_tx_stopped(port))
+		goto disable_tx_irq;
 
 	count = port->fifosize >> 1;
 	do {
@@ -171,8 +170,11 @@ static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id)
 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 		uart_write_wakeup(port);
 
-	if (uart_circ_empty(xmit))
-		clps711xuart_stop_tx(port);
+	if (uart_circ_empty(xmit)) {
+	disable_tx_irq:
+		disable_irq_nosync(TX_IRQ(port));
+		tx_enabled(port) = 0;
+	}
 
 	return IRQ_HANDLED;
 }
-- 
1.7.3.4



From oskar at scara.com  Tue Mar 27 04:24:19 2012
From: oskar at scara.com (Oskar Schirmer)
Date: 27 Mar 2012 08:24:19 +0000
Subject: [PATCH v4 4/4] mfd: mc13xxx: Add i2c driver
In-Reply-To: <1332129838-7080-5-git-send-email-marc@cpdesign.com.au>
References: <1332129838-7080-1-git-send-email-marc@cpdesign.com.au>
 <1332129838-7080-5-git-send-email-marc@cpdesign.com.au>
Message-ID: <20120327082419.GA5080@curry>

Test against Linux 3.3 fails as crucial patches in regmap core
are not yet mainline. However, with commit cc374fbf5305 from
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git
applied, this series works fine.

Signed-off-by: Oskar Schirmer <oskar at scara.com>

On Mon, Mar 19, 2012 at 15:03:58 +1100, Marc Reilly wrote:
> Adds support for mc13xxx family ICs connected via i2c.
> 
> Signed-off-by: Marc Reilly <marc at cpdesign.com.au>
> ---
>  drivers/mfd/Kconfig       |    8 +++-
>  drivers/mfd/Makefile      |    1 +
>  drivers/mfd/mc13xxx-i2c.c |  128 +++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 136 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/mfd/mc13xxx-i2c.c
[...]


From joancarles at fqingenieria.es  Tue Mar 27 04:46:45 2012
From: joancarles at fqingenieria.es (joancarles)
Date: Tue, 27 Mar 2012 10:46:45 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <20120327101259.73525f9d@eb-e6520>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
Message-ID: <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>

Hi Eric

>> G'day
>>
>> This is still present, and we have absolutely no idea where to 
>> continue
>> searching for the solution of the problem. Any pointers? Any git 
>> trees
>> of mmc driver changes we could try? Anybody else with a MX25 that 
>> has
>> this issue?
>>
> does that attached patch fix your problem ?

YES, indeed it does to a certain degree. The timeout errors do not 
occur anymore and I can successfully perform many fs->ops, such as READ, 
WRITE, UNLINK ... . So thank you very much for this insight through your 
patch!

The speed of the card is excruciatingly slow, however. We roughly get 
between 34KB/s and 64KB/s from a dd if=/dev/zero write to any of the 
following partitions:

root at mx25-noah:~$> grep mmc /proc/mounts
/dev/mmcblk0p2 /media/card-ext3 ext3 
rw,sync,relatime,user_xattr,barrier=1,nodelalloc,data=ordered 0 0
/dev/mmcblk0p1 /media/card vfat 
rw,sync,relatime,fmask=0022,dmask=0022,codepage=cp437,iocharset=iso8859-1,shortname=mixed,errors=remount-ro 
0 0
root at mx25-noah:~$> df -kh | grep mmc
/dev/mmcblk0p2            1.7G    133.1M      1.5G   8% 
/media/card-ext3
/dev/mmcblk0p1          123.6M      2.7M    120.9M   2% /media/card
root at mx25-noah:~$> dd if=/dev/zero of=/media/card/test-10M bs=1024K 
count=10
10+0 records in
10+0 records out
10485760 bytes (10.0MB) copied, 296.004564 seconds, 34.6KB/s
root at mx25-noah:~$> dd if=/dev/zero of=/media/card-ext3/test-10M 
bs=1024K count=10
10+0 records in
10+0 records out
10485760 bytes (10.0MB) copied, 158.207481 seconds, 64.7KB/s

What's going on here, why is it so slow?

root at mx25-noah:~$> dmesg | grep -A1 CMD24
[  635.195042] mmc0: starting CMD24 arg 0e5c1600 flags 000000b5
[  635.195081] mmc0:     blksz 512 blocks 1 flags 00000100 tsac 300 ms 
nsac 0
--
[  635.199831] mmc0: req done (CMD24): 0: 00000900 00000000 00000000 
00000000
[  635.199866] mmc0:     512 bytes transferred: 0
--
[  635.200212] mmc0: starting CMD24 arg 0e5c1800 flags 000000b5
[  635.200251] mmc0:     blksz 512 blocks 1 flags 00000100 tsac 300 ms 
nsac 0
--
[  635.206516] mmc0: req done (CMD24): 0: 00000900 00000000 00000000 
00000000
[  635.206549] mmc0:     512 bytes transferred: 0
--
[  635.206892] mmc0: starting CMD24 arg 0e5c1a00 flags 000000b5
[  635.206932] mmc0:     blksz 512 blocks 1 flags 00000100 tsac 300 ms 
nsac 0
--
[  635.211763] mmc0: req done (CMD24): 0: 00000900 00000000 00000000 
00000000
[  635.211796] mmc0:     512 bytes transferred: 0
--
[  635.212409] mmc0: starting CMD24 arg 0e5c1c00 flags 000000b5
[  635.212449] mmc0:     blksz 512 blocks 1 flags 00000100 tsac 300 ms 
nsac 0

Also, debugfs values don't make sense to me:

root at mx25-noah:/sys/kernel/debug/mmc0$> cat clock
50000000
root at mx25-noah:/sys/kernel/debug/mmc0$> cat ios
clock:		50000000 Hz
vdd:		17 (2.9 ~ 3.0 V)
bus mode:	2 (push-pull)
chip select:	0 (don't care)
power mode:	2 (on)
bus width:	2 (4 bits)
timing spec:	2 (sd high-speed)
root at mx25-noah:/sys/kernel/debug/mmc0$> cat mmc0\:0002/stat
state   status
root at mx25-noah:/sys/kernel/debug/mmc0$> cat mmc0\:0002/state
0x00000005
root at mx25-noah:/sys/kernel/debug/mmc0$> cat mmc0\:0002/status
00000900

Best regards and thank you so much for this real improvement of our 
situation here.
-- 
Joan C. Abelaira


From balbi at ti.com  Tue Mar 27 04:54:27 2012
From: balbi at ti.com (Felipe Balbi)
Date: Tue, 27 Mar 2012 11:54:27 +0300
Subject: [PATCH] ARM: OMAP: fix section mismatches in usb-host.c
In-Reply-To: <1332773470-22800-1-git-send-email-grinberg@compulab.co.il>
References: <1332773470-22800-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <20120327085426.GI7379@arwen.pp.htv.fi>

On Mon, Mar 26, 2012 at 04:51:10PM +0200, Igor Grinberg wrote:
> Fix the below section mismatch warning and alike:
> 
> WARNING: vmlinux.o(.text+0x281d4): Section mismatch in reference from
> the function setup_ehci_io_mux() to the function
> .init.text:omap_mux_init_signal()
> The function setup_ehci_io_mux() references
> the function __init omap_mux_init_signal().
> This is often because setup_ehci_io_mux lacks a __init
> annotation or the annotation of omap_mux_init_signal is wrong.
> 
> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>

Acked-by: Felipe Balbi <balbi at ti.com>

> ---
>  arch/arm/mach-omap2/usb-host.c |   10 ++++++----
>  1 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
> index f51348d..dde8a11 100644
> --- a/arch/arm/mach-omap2/usb-host.c
> +++ b/arch/arm/mach-omap2/usb-host.c
> @@ -54,7 +54,7 @@ static struct omap_device_pm_latency omap_uhhtll_latency[] = {
>  /*
>   * setup_ehci_io_mux - initialize IO pad mux for USBHOST
>   */
> -static void setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
> +static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  {
>  	switch (port_mode[0]) {
>  	case OMAP_EHCI_PORT_MODE_PHY:
> @@ -197,7 +197,8 @@ static void setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  	return;
>  }
>  
> -static void setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
> +static
> +void __init setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  {
>  	switch (port_mode[0]) {
>  	case OMAP_EHCI_PORT_MODE_PHY:
> @@ -315,7 +316,7 @@ static void setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  	}
>  }
>  
> -static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
> +static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  {
>  	switch (port_mode[0]) {
>  	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
> @@ -412,7 +413,8 @@ static void setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  	}
>  }
>  
> -static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
> +static
> +void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
>  {
>  	switch (port_mode[0]) {
>  	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
> -- 
> 1.7.3.4
> 

-- 
balbi
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From s.hauer at pengutronix.de  Tue Mar 27 04:55:14 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 27 Mar 2012 10:55:14 +0200
Subject: [PATCH 09/10] clk: dynamically allocate parent_names basic clk
 registration
In-Reply-To: <1332833009-4121-10-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-10-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120327085514.GI29317@pengutronix.de>

On Tue, Mar 27, 2012 at 03:23:28PM +0800, Shawn Guo wrote:
> It's not necessary to have "char *parent[1]" carried in struct clk_gate
> and clk_divider.  Instead, it can be dynamically allocated in
> registration function, just like what clk_register_fixed_rate does.

I patched it the way it is to get rid of the additional malloc which
seemed unnecessary. Maybe the real question is whether the core should
duplicate the parent strings instead of the basic clock types.

Sascha

> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> ---
>  drivers/clk/clk-divider.c    |   14 ++++++++++----
>  drivers/clk/clk-gate.c       |   15 +++++++++++----
>  include/linux/clk-provider.h |    2 --
>  3 files changed, 21 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index b1c4b02..df03a61 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -160,6 +160,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
>  {
>  	struct clk_divider *div;
>  	struct clk *clk;
> +	const char **parent_names = NULL;
>  
>  	div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
>  
> @@ -176,21 +177,26 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
>  	div->lock = lock;
>  
>  	if (parent_name) {
> -		div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
> -		if (!div->parent[0])
> +		parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
> +		if (!parent_names)
> +			goto out;
> +
> +		parent_names[0] = kstrdup(parent_name, GFP_KERNEL);
> +		if (!parent_names[0])
>  			goto out;
>  	}
>  
>  	clk = clk_register(dev, name,
>  			&clk_divider_ops, &div->hw,
> -			div->parent,
> +			parent_names,
>  			(parent_name ? 1 : 0),
>  			flags);
>  	if (clk)
>  		return clk;
>  
>  out:
> -	kfree(div->parent[0]);
> +	kfree(parent_names[0]);
> +	kfree(parent_names);
>  	kfree(div);
>  
>  	return NULL;
> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> index fe2ff9e..51c56cb 100644
> --- a/drivers/clk/clk-gate.c
> +++ b/drivers/clk/clk-gate.c
> @@ -112,6 +112,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
>  {
>  	struct clk_gate *gate;
>  	struct clk *clk;
> +	const char **parent_names = NULL;
>  
>  	gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
>  
> @@ -127,20 +128,26 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
>  	gate->lock = lock;
>  
>  	if (parent_name) {
> -		gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
> -		if (!gate->parent[0])
> +		parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
> +		if (!parent_names)
> +			goto out;
> +
> +		parent_names[0] = kstrdup(parent_name, GFP_KERNEL);
> +		if (parent_names[0])
>  			goto out;
>  	}
>  
>  	clk = clk_register(dev, name,
>  			&clk_gate_ops, &gate->hw,
> -			gate->parent,
> +			parent_names,
>  			(parent_name ? 1 : 0),
>  			flags);
>  	if (clk)
>  		return clk;
> +
>  out:
> -	kfree(gate->parent[0]);
> +	kfree(parent_names[0]);
> +	kfree(parent_names);
>  	kfree(gate);
>  
>  	return NULL;
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 24c5013..7948640 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -176,7 +176,6 @@ struct clk_gate {
>  	u8		bit_idx;
>  	u8		flags;
>  	spinlock_t	*lock;
> -	char		*parent[1];
>  };
>  
>  #define CLK_GATE_SET_TO_DISABLE		BIT(0)
> @@ -214,7 +213,6 @@ struct clk_divider {
>  	u8		width;
>  	u8		flags;
>  	spinlock_t	*lock;
> -	const char	*parent[1];
>  };
>  
>  #define CLK_DIVIDER_ONE_BASED		BIT(0)
> -- 
> 1.7.5.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Tue Mar 27 04:56:59 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 27 Mar 2012 10:56:59 +0200
Subject: [PATCH] ARM: 3ds_debugboard: Fix smsc911x driver probe
In-Reply-To: <1332788037-31064-1-git-send-email-fabio.estevam@freescale.com>
References: <1332788037-31064-1-git-send-email-fabio.estevam@freescale.com>
Message-ID: <20120327085659.GW3852@pengutronix.de>

On Mon, Mar 26, 2012 at 03:53:57PM -0300, Fabio Estevam wrote:
> Fix smsc911x id field in order to fix smsc911x driver probe error:
> 
> smsc911x smsc911x.0: Failed to get supply 'vdd33a': -517
> smsc911x smsc911x.0: (unregistered net_device): couldn't get regulators -517
> platform smsc911x.0: Driver smsc911x requests probe deferral

Looks good. I couldn't test it on the 3ds board. Could you collect your
patches until the beginning of next week? I'm on holidays right now and
will be back next week.

Sascha

> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  arch/arm/plat-mxc/3ds_debugboard.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
> index d1e31fa..5cac2c5 100644
> --- a/arch/arm/plat-mxc/3ds_debugboard.c
> +++ b/arch/arm/plat-mxc/3ds_debugboard.c
> @@ -80,7 +80,7 @@ static struct smsc911x_platform_config smsc911x_config = {
>  
>  static struct platform_device smsc_lan9217_device = {
>  	.name = "smsc911x",
> -	.id = 0,
> +	.id = -1,
>  	.dev = {
>  		.platform_data = &smsc911x_config,
>  	},
> -- 
> 1.7.1
> 
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From eric at eukrea.com  Tue Mar 27 04:58:19 2012
From: eric at eukrea.com (Eric =?ISO-8859-1?B?QuluYXJk?=)
Date: Tue, 27 Mar 2012 10:58:19 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
Message-ID: <20120327105819.00d89783@eb-e6520>

Hi Joan Carles,

Le Tue, 27 Mar 2012 10:46:45 +0200,
joancarles <joancarles at fqingenieria.es> a ?crit :
> >> This is still present, and we have absolutely no idea where to 
> >> continue
> >> searching for the solution of the problem. Any pointers? Any git 
> >> trees
> >> of mmc driver changes we could try? Anybody else with a MX25 that 
> >> has
> >> this issue?
> >>
> > does that attached patch fix your problem ?
> 
> YES, indeed it does to a certain degree. The timeout errors do not 
> occur anymore and I can successfully perform many fs->ops, such as READ, 
> WRITE, UNLINK ... . So thank you very much for this insight through your 
> patch!
> 
> The speed of the card is excruciatingly slow, however. We roughly get 
> between 34KB/s and 64KB/s from a dd if=/dev/zero write to any of the 
> following partitions:
> 
I have the same speed problem here on i.MX25 but still haven't found
the reason.
Shawn, Richard : do you have an idea of why the eSDHC is so slow on
i.MX25 ?

Thanks,
Eric


From w.sang at pengutronix.de  Tue Mar 27 05:01:49 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 27 Mar 2012 11:01:49 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
Message-ID: <20120327090148.GB6790@pengutronix.de>


> >does that attached patch fix your problem ?
> 
> YES, indeed it does to a certain degree. The timeout errors do not
> occur anymore and I can successfully perform many fs->ops, such as

Interesting question is now why it worked on your older kernel? The code
around BROKEN_TIMEOUT is there for much longer, I'd think.

> The speed of the card is excruciatingly slow, however. We roughly
> get between 34KB/s and 64KB/s from a dd if=/dev/zero write to any of
> the following partitions:

Check the code below what is patched. That's currently the best solution
for the errata. There might be better ones, though, but you'd need to
find out.

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From eric at eukrea.com  Tue Mar 27 05:06:15 2012
From: eric at eukrea.com (Eric =?ISO-8859-1?B?QuluYXJk?=)
Date: Tue, 27 Mar 2012 11:06:15 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <20120327090148.GB6790@pengutronix.de>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
 <20120327090148.GB6790@pengutronix.de>
Message-ID: <20120327110615.3bfaf969@eb-e6520>

Hi Wolfram,

Le Tue, 27 Mar 2012 11:01:49 +0200,
Wolfram Sang <w.sang at pengutronix.de> a ?crit :
> > >does that attached patch fix your problem ?
> > 
> > YES, indeed it does to a certain degree. The timeout errors do not
> > occur anymore and I can successfully perform many fs->ops, such as
> 
> Interesting question is now why it worked on your older kernel? The code
> around BROKEN_TIMEOUT is there for much longer, I'd think.
> 
not in fact it seems to have been broken from a long time and I think
I'm responsible of that in 37865fe91582582a6f6c00652f6a2b1ff71f8a78
"mmc: sdhci-esdhc-imx: fix timeout on i.MX's sdhc"
because unlike the i.MX35 it seems that the i.MX25 manages to read
properly the partition table even without the timeout quirk and it
seems that I didn't do more extensive tests for this patch.

Eric


From w.sang at pengutronix.de  Tue Mar 27 05:14:25 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 27 Mar 2012 11:14:25 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <20120327110615.3bfaf969@eb-e6520>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
 <20120327090148.GB6790@pengutronix.de>
 <20120327110615.3bfaf969@eb-e6520>
Message-ID: <20120327091425.GC6790@pengutronix.de>


> > Interesting question is now why it worked on your older kernel? The code
> > around BROKEN_TIMEOUT is there for much longer, I'd think.
> > 
> not in fact it seems to have been broken from a long time and I think

I know and you are saying the same, in fact :) Your patch came in around
2.6.37 and here it was said that 2.6.39 works fine. Might be random,
though.

> because unlike the i.MX35 it seems that the i.MX25 manages to read
> properly the partition table even without the timeout quirk and it
> seems that I didn't do more extensive tests for this patch.

Please do next time.

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From thomas.abraham at linaro.org  Tue Mar 27 05:26:01 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 27 Mar 2012 14:56:01 +0530
Subject: [PATCH 0/4] ARM: Exynos: Fixes for Exynos5 device tree support
Message-ID: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>

This series includes general fixes for Exynos5 device tree support. This
is based on the following tree. Both Exynos4 and Exynos5 device tree
support have been tested when this series.

http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git [for-next]


Thomas Abraham (4):
  ARM: Exynos: Use CHIP_ID to detect cpu type during decompression setup
  ARM: Exynos: Remove a new bus_type instance for Exynos5
  ARM: Exynos5: Fix incorrect initialization of GIC
  ARM: Exynos5: Add PDMA and MDMA physical base address defines

 arch/arm/mach-exynos/common.c                  |   21 +++------------------
 arch/arm/mach-exynos/include/mach/map.h        |    5 +++++
 arch/arm/mach-exynos/include/mach/uncompress.h |    6 +++++-
 arch/arm/mach-exynos/mach-exynos5-dt.c         |    3 ++-
 4 files changed, 15 insertions(+), 20 deletions(-)



From thomas.abraham at linaro.org  Tue Mar 27 05:26:02 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 27 Mar 2012 14:56:02 +0530
Subject: [PATCH 1/4] ARM: Exynos: Use CHIP_ID to detect cpu type during
 decompression setup
In-Reply-To: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>
References: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332840365-24827-2-git-send-email-thomas.abraham@linaro.org>

The config option MACH_SMDK5250 is not available for Exynos5 since only
a device tree based machine is supported and selected by MACH_EXYNOS5_DT.
Hence, the detection of the cpu type based on machine_is_smdk5250 always
fails and boot hangs due to incorrect uart base being used. Fix this by
reading the chip id to determine the cpu type and setup the uart_base
accordingly.

Signed-off-by: Thomas Abraham <thomas.ab at samsung.com>
---
 arch/arm/mach-exynos/include/mach/uncompress.h |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 493f4f3..603ea9b 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -14,15 +14,19 @@
 
 #include <asm/mach-types.h>
 
+#include <plat/cpu.h>
 #include <mach/map.h>
 
 volatile u8 *uart_base;
 
 #include <plat/uncompress.h>
 
+#define __raw_readl(addr)		\
+	(*((volatile unsigned int __force *)(addr)))
+
 static void arch_detect_cpu(void)
 {
-	if (machine_is_smdk5250())
+	if ((__raw_readl(EXYNOS_PA_CHIPID) & EXYNOS5_SOC_MASK) == EXYNOS5250_SOC_ID)
 		uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 	else
 		uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Tue Mar 27 05:26:03 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 27 Mar 2012 14:56:03 +0530
Subject: [PATCH 2/4] ARM: Exynos: Remove a new bus_type instance for Exynos5
In-Reply-To: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>
References: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332840365-24827-3-git-send-email-thomas.abraham@linaro.org>

A seperate bus_type instance is not required for Exynos5. The existing bus_type
instance used with Exynos4 is sufficient for both Exynos4 and Exynos5. This
also solves issue of uninitialized usage of exynos4_subsys in Exynos4 power
management code that is reused for Exynos5 also.

Signed-off-by: Thomas Abraham <thomas.ab at samsung.com>
---
 arch/arm/mach-exynos/common.c |   19 ++-----------------
 1 files changed, 2 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index a750a5d..f265dc4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -563,25 +563,13 @@ struct bus_type exynos4_subsys = {
 	.dev_name	= "exynos4-core",
 };
 
-struct bus_type exynos5_subsys = {
-	.name		= "exynos5-core",
-	.dev_name	= "exynos5-core",
-};
-
 static struct device exynos4_dev = {
 	.bus	= &exynos4_subsys,
 };
 
-static struct device exynos5_dev = {
-	.bus	= &exynos5_subsys,
-};
-
 static int __init exynos_core_init(void)
 {
-	if (soc_is_exynos5250())
-		return subsys_system_register(&exynos5_subsys, NULL);
-	else
-		return subsys_system_register(&exynos4_subsys, NULL);
+	return subsys_system_register(&exynos4_subsys, NULL);
 }
 core_initcall(exynos_core_init);
 
@@ -667,10 +655,7 @@ static int __init exynos_init(void)
 {
 	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 
-	if (soc_is_exynos5250())
-		return device_register(&exynos5_dev);
-	else
-		return device_register(&exynos4_dev);
+	return device_register(&exynos4_dev);
 }
 
 /* uart registration process */
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Tue Mar 27 05:26:04 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 27 Mar 2012 14:56:04 +0530
Subject: [PATCH 3/4] ARM: Exynos5: Fix incorrect initialization of GIC
In-Reply-To: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>
References: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332840365-24827-4-git-send-email-thomas.abraham@linaro.org>

Use the of_irq_init() call to setup the gic which also properly registers
the gic device node pointer with gic irq domain, without which all interrupt
specifier translations for gic fail.

Signed-off-by: Thomas Abraham <thomas.ab at samsung.com>
---
 arch/arm/mach-exynos/common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f265dc4..3bf39a8 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -542,7 +542,7 @@ void __init exynos5_init_irq(void)
 {
 	int irq;
 
-	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+	of_irq_init(exynos4_dt_irq_match);
 
 	for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
 		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-- 
1.6.6.rc2



From thomas.abraham at linaro.org  Tue Mar 27 05:26:05 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Tue, 27 Mar 2012 14:56:05 +0530
Subject: [PATCH 4/4] ARM: Exynos5: Add PDMA and MDMA physical base address
 defines
In-Reply-To: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>
References: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <1332840365-24827-5-git-send-email-thomas.abraham@linaro.org>

Add PDMA and MDMA physical base address macros which is require for Exynos5
of_dev_auxdata setup.

Signed-off-by: Thomas Abraham <thomas.ab at samsung.com>
---
 arch/arm/mach-exynos/include/mach/map.h |    5 +++++
 arch/arm/mach-exynos/mach-exynos5-dt.c  |    3 ++-
 2 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 024d38f..37d93fd 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -90,6 +90,11 @@
 #define EXYNOS4_PA_PDMA0		0x12680000
 #define EXYNOS4_PA_PDMA1		0x12690000
 
+#define EXYNOS5_PA_PDMA0		0x121A0000
+#define EXYNOS5_PA_PDMA1		0x121B0000
+#define EXYNOS5_PA_MDMA0		0x10800000
+#define EXYNOS5_PA_MDMA1		0x11C10000
+
 #define EXYNOS4_PA_SYSMMU_MDMA		0x10A40000
 #define EXYNOS4_PA_SYSMMU_SSS		0x10A50000
 #define EXYNOS4_PA_SYSMMU_FIMC0		0x11A20000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 0d26f50..cdc3a26 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -45,7 +45,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"exynos4210-uart.3", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
-	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA0, "dma-pl330.2", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA0, "dma-pl330.3", NULL),
 	{},
 };
 
-- 
1.6.6.rc2



From eric at eukrea.com  Tue Mar 27 05:23:42 2012
From: eric at eukrea.com (Eric =?ISO-8859-1?B?QuluYXJk?=)
Date: Tue, 27 Mar 2012 11:23:42 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <20120327091425.GC6790@pengutronix.de>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
 <20120327090148.GB6790@pengutronix.de>
 <20120327110615.3bfaf969@eb-e6520>
 <20120327091425.GC6790@pengutronix.de>
Message-ID: <20120327112342.73a85a1b@eb-e6520>

Le Tue, 27 Mar 2012 11:14:25 +0200,
Wolfram Sang <w.sang at pengutronix.de> a ?crit :

> 
> > > Interesting question is now why it worked on your older kernel? The code
> > > around BROKEN_TIMEOUT is there for much longer, I'd think.
> > > 
> > not in fact it seems to have been broken from a long time and I think
> 
> I know and you are saying the same, in fact :) Your patch came in around
> 2.6.37 and here it was said that 2.6.39 works fine. Might be random,
> though.
> 
what is surprising is that no one reported this problem between 2.6.37
and 3.3

> > because unlike the i.MX35 it seems that the i.MX25 manages to read
> > properly the partition table even without the timeout quirk and it
> > seems that I didn't do more extensive tests for this patch.
> 
> Please do next time.
> 
well I should have said "enough extensive" tests as I did a lot of tests
on the 3 archs (i.MX25, i.MX35 and i.MX51). What I see here is that on
i.MX35 and i.MX51 the problem is very easy to reproduce without
extensive tests (card not detected) and that on i.MX25 it needs more
tests as the card is properly detected.

Eric


From joancarles at fqingenieria.es  Tue Mar 27 05:33:57 2012
From: joancarles at fqingenieria.es (joancarles)
Date: Tue, 27 Mar 2012 11:33:57 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <20120327110615.3bfaf969@eb-e6520>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
 <20120327090148.GB6790@pengutronix.de> <20120327110615.3bfaf969@eb-e6520>
Message-ID: <7f2ae9e3800848e140461a0506808fb4@mail.fqingenieria.es>

Hi

>> Interesting question is now why it worked on your older kernel? The 
>> code
>> around BROKEN_TIMEOUT is there for much longer, I'd think.
>>
> not in fact it seems to have been broken from a long time and I think
> I'm responsible of that in 37865fe91582582a6f6c00652f6a2b1ff71f8a78
> "mmc: sdhci-esdhc-imx: fix timeout on i.MX's sdhc"
> because unlike the i.MX35 it seems that the i.MX25 manages to read
> properly the partition table even without the timeout quirk and it
> seems that I didn't do more extensive tests for this patch.

Might be unrelated, however I have been keeping my eyes on the fix of 
ENGcm07207 quirk introduced with 16a790bcc. According to the 
IMX25CE.pdf, to abort data transfers on the AHB, software can reset the 
eSDHC by writing 1 to SYSCTL[24] (RSTA), which currently is not done 
with SDHCI_QUIRK_NO_MULTIBLOCK. It sets the max_blk_count to 1 instead 
of 65535. Not sure if this is also limiting the speed.

I have tried putting the SD card into an ALL-in-One reader via USB and 
I get 6MB/s read and 15MB/s write performance. Since I didn't know the 
exact class of the card, this reassures me that there is nothing 
substantially wrong with the card per se.

So, how can we find a solution to this speed issue? Also, do you plan 
on submitting your patch to revert the timeout quirk for MX25?

Cheers
-- 
Joan C. Abelaira



From w.sang at pengutronix.de  Tue Mar 27 05:36:44 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 27 Mar 2012 11:36:44 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <20120327112342.73a85a1b@eb-e6520>
References: <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
 <20120327090148.GB6790@pengutronix.de>
 <20120327110615.3bfaf969@eb-e6520>
 <20120327091425.GC6790@pengutronix.de>
 <20120327112342.73a85a1b@eb-e6520>
Message-ID: <20120327093644.GD6790@pengutronix.de>


> well I should have said "enough extensive" tests as I did a lot of tests
> on the 3 archs (i.MX25, i.MX35 and i.MX51). What I see here is that on
> i.MX35 and i.MX51 the problem is very easy to reproduce without
> extensive tests (card not detected) and that on i.MX25 it needs more
> tests as the card is properly detected.

Ah, okay, thanks for the clarification! Well, since you retested now and
found it is harder to trigger that could explain why nobody reported it
and why 2.6.39 seems to work (although it maybe doesn't). Thanks for
rechecking. If you submit the patch, you can add my

Acked-by: Wolfram Sang <w.sang at pengutronix.de>

Best regards.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From eric at eukrea.com  Tue Mar 27 05:40:48 2012
From: eric at eukrea.com (Eric =?ISO-8859-1?B?QuluYXJk?=)
Date: Tue, 27 Mar 2012 11:40:48 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <7f2ae9e3800848e140461a0506808fb4@mail.fqingenieria.es>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
 <20120327090148.GB6790@pengutronix.de>
 <20120327110615.3bfaf969@eb-e6520>
 <7f2ae9e3800848e140461a0506808fb4@mail.fqingenieria.es>
Message-ID: <20120327114048.6af2e178@eb-e6520>

Hi,

Le Tue, 27 Mar 2012 11:33:57 +0200,
joancarles <joancarles at fqingenieria.es> a ?crit :
> >> Interesting question is now why it worked on your older kernel? The 
> >> code
> >> around BROKEN_TIMEOUT is there for much longer, I'd think.
> >>
> > not in fact it seems to have been broken from a long time and I think
> > I'm responsible of that in 37865fe91582582a6f6c00652f6a2b1ff71f8a78
> > "mmc: sdhci-esdhc-imx: fix timeout on i.MX's sdhc"
> > because unlike the i.MX35 it seems that the i.MX25 manages to read
> > properly the partition table even without the timeout quirk and it
> > seems that I didn't do more extensive tests for this patch.
> 
> Might be unrelated, however I have been keeping my eyes on the fix of 
> ENGcm07207 quirk introduced with 16a790bcc. According to the 
> IMX25CE.pdf, to abort data transfers on the AHB, software can reset the 
> eSDHC by writing 1 to SYSCTL[24] (RSTA), which currently is not done 
> with SDHCI_QUIRK_NO_MULTIBLOCK. It sets the max_blk_count to 1 instead 
> of 65535. Not sure if this is also limiting the speed.
> 
I tried to increase max_blk_count and it breaks after a few tests.
Using an oscilloscope it seems we have a big latency between each
transfer which could explain the low throughput, I didn't have the
time to look deeper at this problem.

> I have tried putting the SD card into an ALL-in-One reader via USB and 
> I get 6MB/s read and 15MB/s write performance. Since I didn't know the 
> exact class of the card, this reassures me that there is nothing 
> substantially wrong with the card per se.
> 
> So, how can we find a solution to this speed issue? Also, do you plan 
> on submitting your patch to revert the timeout quirk for MX25?
> 
yes, I'm writing a proper commit message and will send it in a few
minutes.

Eric


From mgherzan at gmail.com  Tue Mar 27 05:41:32 2012
From: mgherzan at gmail.com (Mircea Gherzan)
Date: Tue, 27 Mar 2012 11:41:32 +0200
Subject: [PATCH v8 RESEND] ARM: net: JIT compiler for packet filters
In-Reply-To: <20120327075600.GL5611@n2100.arm.linux.org.uk>
References: <1331933316-10197-1-git-send-email-mgherzan@gmail.com>
 <20120319.172005.1889334604020296555.davem@davemloft.net>
 <4F6EEAB5.7070009@gmail.com>
 <20120325095711.GC5611@n2100.arm.linux.org.uk>
 <4F6F19C2.60602@gmail.com>
 <20120325133506.GG5611@n2100.arm.linux.org.uk>
 <20120327075600.GL5611@n2100.arm.linux.org.uk>
Message-ID: <CAN9tCgSi_Lat+i3LqNGWGCk01cmJTvLfD-mXTHhks9od-nj6Gg@mail.gmail.com>

2012/3/27 Russell King - ARM Linux <linux at arm.linux.org.uk>:
> Mircea, could you please supply an ack for the below fix to silence a
> warning. ?Thanks.
>
> 8<=====
> ARM: fix Kconfig warning for HAVE_BPF_JIT
>
> Last night's randconfig and the allnoconfig builds spat out the
> following warning while building:
>
> warning: (ARM) selects HAVE_BPF_JIT which has unmet direct dependencies (NET)
>
> Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
> ---
> ?arch/arm/Kconfig | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 9e21b6e..6a54606 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -33,7 +33,7 @@ config ARM
> ? ? ? ?select GENERIC_IRQ_SHOW
> ? ? ? ?select CPU_PM if (SUSPEND || CPU_IDLE)
> ? ? ? ?select GENERIC_PCI_IOMAP
> - ? ? ? select HAVE_BPF_JIT
> + ? ? ? select HAVE_BPF_JIT if NET
> ? ? ? ?help
> ? ? ? ? ?The ARM series is a line of low-power-consumption RISC chip designs
> ? ? ? ? ?licensed by ARM Ltd and targeted at embedded applications and

Acked-by: Mircea Gherzan <mgherzan at gmail.com>


From w.sang at pengutronix.de  Tue Mar 27 05:45:45 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 27 Mar 2012 11:45:45 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <7f2ae9e3800848e140461a0506808fb4@mail.fqingenieria.es>
References: <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
 <20120327090148.GB6790@pengutronix.de>
 <20120327110615.3bfaf969@eb-e6520>
 <7f2ae9e3800848e140461a0506808fb4@mail.fqingenieria.es>
Message-ID: <20120327094545.GE6790@pengutronix.de>


> Might be unrelated, however I have been keeping my eyes on the fix
> of ENGcm07207 quirk introduced with 16a790bcc. According to the
> IMX25CE.pdf, to abort data transfers on the AHB, software can reset
> the eSDHC by writing 1 to SYSCTL[24] (RSTA), which currently is not
> done with SDHCI_QUIRK_NO_MULTIBLOCK. It sets the max_blk_count to 1
> instead of 65535. Not sure if this is also limiting the speed.

Oh, it is limiting speed, for sure.

SDHCI_QUIRK_NO_MULTIBLOCK is a _generic_ quirk which can be enabled by
various buggy sdhci implementations, not only esdhc (which is pretty
good at being buggy). It is not there to fix MX25 specific issues,
that would have to be done seperately in sdhci-esdhc-imx.c.

So, the above quirk is a big hammer solution. There might be more
precise ones, but those still would have to be developed. I don't know
of anyone planning to do this.

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From rnayak at ti.com  Tue Mar 27 05:58:31 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Tue, 27 Mar 2012 15:28:31 +0530
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used OMAP4
 onwards
Message-ID: <1332842311-12308-1-git-send-email-rnayak@ti.com>

Some functions like _omap4_disable_module() and _omap4_wait_target_disable()
are (will be) used on all OMAPs OMAP4 and beyond which support module level
control. Fix the error checks in these functions to return if called on
any platform pre OMAP4 (i.e OMAP2 and OMAP3) instead of checking for
!cpu_is_omap44xx(). This avoids having to update the error check with a
'&& !cpu_is_omap54xx()' when OMAP5 is introduced and possibly similar updates
when further OMAP generations are added.

Signed-off-by: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 8ac26f2..f2a9afa 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -808,7 +808,7 @@ static void _enable_module(struct omap_hwmod *oh)
  */
 static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 {
-	if (!cpu_is_omap44xx())
+	if (cpu_is_omap24xx() || cpu_is_omap34xx())
 		return 0;
 
 	if (!oh)
@@ -838,7 +838,7 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
 	int v;
 
 	/* The module mode does not exist prior OMAP4 */
-	if (!cpu_is_omap44xx())
+	if (cpu_is_omap24xx() || cpu_is_omap34xx())
 		return -EINVAL;
 
 	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
-- 
1.7.1



From m.szyprowski at samsung.com  Tue Mar 27 05:59:34 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 11:59:34 +0200
Subject: [GIT PULL] DMA-mapping framework updates for 3.4
In-Reply-To: <CA+55aFy9oxMrfm-+deMqV=XnFOa98aKXqW+8PR-P-zOARtC2BQ@mail.gmail.com>
References: <1332228283-29077-1-git-send-email-m.szyprowski@samsung.com>
 <CA+55aFy9oxMrfm-+deMqV=XnFOa98aKXqW+8PR-P-zOARtC2BQ@mail.gmail.com>
Message-ID: <007101cd0c00$4ff08af0$efd1a0d0$%szyprowski@samsung.com>

Hi Linus,

On Friday, March 23, 2012 10:36 PM Linus Torvalds wrote:

> On Tue, Mar 20, 2012 at 12:24 AM, Marek Szyprowski
> <m.szyprowski at samsung.com> wrote:
> >
> > ?git://git.infradead.org/users/kmpark/linux-samsung dma-mapping-next
> >
> > Those patches introduce a new alloc method (with support for memory
> > attributes) in dma_map_ops structure, which will later replace
> > dma_alloc_coherent and dma_alloc_writecombine functions.
> 
> So I'm quite unhappy with these patches.
> 
> Here's just the few problems I saw from some *very* quick look-through
> of the git tree:
> 
>  - I'm not seeing ack's from the architecture maintainers for the
> patches that change some architecture.

Ok, I've asked personally each respective maintainer for an ack or 
comments. Before I've sent my pull request there were only a few comments
on the mailing lists, but this topic have been discussed at ELC-E in Prague
and Linaro Memory-management summit in Budapest (May 2011).
 
>  - Even more importantly, what I really want is acks and comments from
> the people who are expected to *use* this.

The plan is to use it as a base for further cleanup in the dma-mapping 
implementations, especially on ARM architecture. The changes are designed
in such a way to keep compatibility with the existing users of the API. 
ARM will be the first architecture which will use the new attributes. 
The main clients for this new API will be mainly multimedia drivers (v4l2,
drm) and dma_buf buffer sharing. The advantage of this approach is the 
fact that the same drivers can be used on other architectures without any
changes in the dma calls. The attributes which are not supported by the
architecture will be simply ignored.

>  - it looks like patches break compilation half-way through the
> series. Just one example I noticed: the "x86 adaptation" patch changes
> the functions in lib/swiotlb.c, but afaik ia64 *also* uses those. So
> now ia64 is broken until a couple of patches later. I suspect there
> are other examples like that.

Ok, I missed this and I will fix this issue asap.

>  - the sign-off chains are odd. What happened there? Several patches
> are signed off by Kyungmin Park, but he doesn't seem to be "in the
> chain" at all. Whazzup? (*)

That was caused by our internal flow of the patches, but I see that it 
made only a lot of confusion. I got my own git repository at 
git.linaro.org and I will resolve these sign-off issues correctly there.

>  - Finally, how/why are "dma attributes" different from the per-device
> dma limits ("device_dma_parameters")

Device dma parameters are global for all dma mapping operations for the 
specified device, while dma attributes can be set for each allocation or
mapping call. Dma attributes are mainly used to provide some hints to the
dma mapping core, which might improve speed/performance/throughput for
some particular sw&hw architectures. Unsupported attributes are ignored,
so the in the worst case a driver gets coherent mapping.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From thomas.ab at samsung.com  Tue Mar 27 06:16:43 2012
From: thomas.ab at samsung.com (Thomas Abraham)
Date: Tue, 27 Mar 2012 15:46:43 +0530
Subject: [PATCH] ARM: Samsung: Make PM_GENERIC_DOMAINS config depend on
 CONFIG_PM
Message-ID: <1332843404-25476-1-git-send-email-thomas.ab@samsung.com>

For s3c64xx and exynos platforms, make the selection of PM_GENERIC_DOMAINS
depend on the CONFIG_PM.

Signed-off-by: Thomas Abraham <thomas.ab at samsung.com>
---
 arch/arm/mach-exynos/Kconfig  |    2 +-
 arch/arm/mach-s3c64xx/Kconfig |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 0491cee..6c8f17b 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -35,7 +35,7 @@ config CPU_EXYNOS4210
 	select ARM_CPU_SUSPEND if PM
 	select S5P_PM if PM
 	select S5P_SLEEP if PM
-	select PM_GENERIC_DOMAINS
+	select PM_GENERIC_DOMAINS if PM
 	help
 	  Enable EXYNOS4210 CPU support
 
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 82c0915..2609349 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -8,7 +8,7 @@ config PLAT_S3C64XX
 	bool
 	depends on ARCH_S3C64XX
 	select SAMSUNG_WAKEMASK
-	select PM_GENERIC_DOMAINS
+	select PM_GENERIC_DOMAINS if PM
 	default y
 	help
 	  Base platform code for any Samsung S3C64XX device
-- 
1.6.6.rc2



From thomas.ab at samsung.com  Tue Mar 27 06:16:44 2012
From: thomas.ab at samsung.com (Thomas Abraham)
Date: Tue, 27 Mar 2012 15:46:44 +0530
Subject: [PATCH] ARM: Samsung: Make PM_GENERIC_DOMAINS config depend on
 CONFIG_PM
In-Reply-To: <1332843404-25476-1-git-send-email-thomas.ab@samsung.com>
References: <1332843404-25476-1-git-send-email-thomas.ab@samsung.com>
Message-ID: <1332843404-25476-2-git-send-email-thomas.ab@samsung.com>

For s3c64xx and exynos platforms, make the selection of PM_GENERIC_DOMAINS
depend on the CONFIG_PM.

Signed-off-by: Thomas Abraham <thomas.ab at samsung.com>
---
 arch/arm/mach-exynos/Kconfig  |    2 +-
 arch/arm/mach-s3c64xx/Kconfig |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 0491cee..6c8f17b 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -35,7 +35,7 @@ config CPU_EXYNOS4210
 	select ARM_CPU_SUSPEND if PM
 	select S5P_PM if PM
 	select S5P_SLEEP if PM
-	select PM_GENERIC_DOMAINS
+	select PM_GENERIC_DOMAINS if PM
 	help
 	  Enable EXYNOS4210 CPU support
 
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 82c0915..2609349 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -8,7 +8,7 @@ config PLAT_S3C64XX
 	bool
 	depends on ARCH_S3C64XX
 	select SAMSUNG_WAKEMASK
-	select PM_GENERIC_DOMAINS
+	select PM_GENERIC_DOMAINS if PM
 	default y
 	help
 	  Base platform code for any Samsung S3C64XX device
-- 
1.6.6.rc2



From viresh.kumar at st.com  Tue Mar 27 06:27:42 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Tue, 27 Mar 2012 15:57:42 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203221420.10127.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203211236.37891.arnd@arndb.de>
 <CAOh2x=k6ZfamB8DnPgVPjxZ7E1gTuHOQYg6s1Nd1ybA+TSquWA@mail.gmail.com>
 <201203221420.10127.arnd@arndb.de>
Message-ID: <4F71961E.2080208@st.com>

On 3/22/2012 7:50 PM, Arnd Bergmann wrote:
> The direct replacement is of_machine_is_compatible(), but there are a lot
> of cases where it's better to have a local property in the device node
> that a driver is using.

Hey Arnd,

I used of_machine_is_compatible() at several places, where it is not working :(
Actually all these usages are before a call to of_platform_populate() and
it looks the tree is not up by this time.

So, of_machine_is_compatible() always fails. The places where i am using this
routine are:
- spear3xx_dt_init(): to call SoC specific of_platform_populate()
- spear3xx_clk_init(): to call SoC specific clk_register()

Can you please suggest what should i do here?

-- 
viresh


From joancarles at fqingenieria.es  Tue Mar 27 06:56:31 2012
From: joancarles at fqingenieria.es (joancarles)
Date: Tue, 27 Mar 2012 12:56:31 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <20120327114048.6af2e178@eb-e6520>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
 <20120327090148.GB6790@pengutronix.de> <20120327110615.3bfaf969@eb-e6520>
 <7f2ae9e3800848e140461a0506808fb4@mail.fqingenieria.es>
 <20120327114048.6af2e178@eb-e6520>
Message-ID: <137e8b8e079af62aea2fd4d363be6273@mail.fqingenieria.es>

Hi

>> Might be unrelated, however I have been keeping my eyes on the fix 
>> of
>> ENGcm07207 quirk introduced with 16a790bcc. According to the
>> IMX25CE.pdf, to abort data transfers on the AHB, software can reset 
>> the
>> eSDHC by writing 1 to SYSCTL[24] (RSTA), which currently is not done
>> with SDHCI_QUIRK_NO_MULTIBLOCK. It sets the max_blk_count to 1 
>> instead
>> of 65535. Not sure if this is also limiting the speed.
>>
> I tried to increase max_blk_count and it breaks after a few tests.

I will redo your tests in a jiffy, however the latency issues worry me 
a wee bit.

> Using an oscilloscope it seems we have a big latency between each
> transfer which could explain the low throughput, I didn't have the
> time to look deeper at this problem.

The latency we can see here in the oscilloscope is tremendous between 
two CMD24: 8ms! What is causing this? It is certainly unrelated to the 
MULTIBLOCK feature. Having a clock at 33.25MHz, our maximal read, as 
confirmed by dd is:

33.25[MHz] * 4[bits data] / 8[bits/Byte] * 30 [us write] / 8000 [us 
sleep] =~ 60KB/s

So, what's keeping the driver 8ms from sending the data??? Any pointers 
on where I could twiddle some bits in the driver? Where do I start 
looking?

Cheers
-- 
Joan C. Abelaira



From arnd at arndb.de  Tue Mar 27 07:15:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 27 Mar 2012 11:15:07 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <4F71961E.2080208@st.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203221420.10127.arnd@arndb.de> <4F71961E.2080208@st.com>
Message-ID: <201203271115.07805.arnd@arndb.de>

On Tuesday 27 March 2012, Viresh Kumar wrote:
> On 3/22/2012 7:50 PM, Arnd Bergmann wrote:
> > The direct replacement is of_machine_is_compatible(), but there are a lot
> > of cases where it's better to have a local property in the device node
> > that a driver is using.
> 
> Hey Arnd,
> 
> I used of_machine_is_compatible() at several places, where it is not working :(
> Actually all these usages are before a call to of_platform_populate() and
> it looks the tree is not up by this time.
> 
> So, of_machine_is_compatible() always fails. The places where i am using this
> routine are:
> - spear3xx_dt_init(): to call SoC specific of_platform_populate()
> - spear3xx_clk_init(): to call SoC specific clk_register()
> 
> Can you please suggest what should i do here?

The normal way is to turn around the logic so you don't have to include this test
at all. Just have one soc-specific init_machine and map_io function, that calls
both soc-specific and shared soc functions, e.g.

void __init spear3xx_clk_init(void)
{
	int i;
	struct clk_lookup *lookups;

	for (i = 0; i < ARRAY_SIZE(spear3xx_clk_lookups); i++) 
		clk_register(&spear3xx_clk_lookups[i])
}

void __init spear300_clk_init(void)
{
	int i;
	struct clk_lookup *lookups;

	spear3xx_clk_init();

	for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++) 
		clk_register(&spear300_clk_lookups[i])

	clk_init();
}

void __init spear300_map_io(void)
{
	spear3xx_map_io();
	spear300_clk_init();
}

The other option would be to try to move stuff to a later point, e.g. don't
initialize the clocks until the basic device tree is set up.
of_machine_is_compatible() should work at init_early() time, but not at
map_io() time. Other platforms set up the clocks at init_early() time.
The spear3xx_dt_init function should be called from init_machine(), which
happens much later, so I'm pretty sure you can use of_machine_is_compatible()
if you can't just avoid it.

In the long run, I would hope that a lot of the differences go away anyway
as information that is now hardcoded just moves into the device tree.
At that point, you should no longer need to care which soc you are running
on. I realize that there is still significant amount of work to be done
until you get there.

In case of the clocks, I think you could already merge all the clk_lookup
arrays into one, which would result in a larger kernel image but should
do no harm otherwise.

	Arnd


From viresh.kumar at st.com  Tue Mar 27 07:27:40 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Tue, 27 Mar 2012 16:57:40 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203271115.07805.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203221420.10127.arnd@arndb.de> <4F71961E.2080208@st.com>
 <201203271115.07805.arnd@arndb.de>
Message-ID: <4F71A42C.3090108@st.com>

On 3/27/2012 4:45 PM, Arnd Bergmann wrote:
> On Tuesday 27 March 2012, Viresh Kumar wrote:
> The normal way is to turn around the logic so you don't have to include this test
> at all. Just have one soc-specific init_machine and map_io function, that calls
> both soc-specific and shared soc functions, e.g.

But with that, i need multiple DT_MACHINE_START(). Isn't it?
Is this advisable?

> The other option would be to try to move stuff to a later point, e.g. don't
> initialize the clocks until the basic device tree is set up.
> of_machine_is_compatible() should work at init_early() time, but not at
> map_io() time. Other platforms set up the clocks at init_early() time.
> The spear3xx_dt_init function should be called from init_machine(), which
> happens much later, so I'm pretty sure you can use of_machine_is_compatible()
> if you can't just avoid it.

DT should be up but, nodes would be up only once we call
of_platform_populate() from this init routine. And i had following code in
my patch:

static void __init spear3xx_dt_init(void)
{
...
	if (of_machine_is_compatible("st,spear300"))
		of_platform_populate(NULL, of_default_bus_match_table,
				spear300_auxdata_lookup, NULL);
	else if (of_machine_is_compatible("st,spear310"))
		of_platform_populate(NULL, of_default_bus_match_table,
				spear310_auxdata_lookup, NULL);
	else if (of_machine_is_compatible("st,spear320"))
		of_platform_populate(NULL, of_default_bus_match_table,
				spear320_auxdata_lookup, NULL);

...
}

And so these checks are not working here. :(

> In case of the clocks, I think you could already merge all the clk_lookup
> arrays into one, which would result in a larger kernel image but should
> do no harm otherwise.

Actually we can't do it. :(
If i boot 300 then i will also get clocks of 310 and 320 in my clock list.
And once i go through this clock list to create clock tree (parent-child
relationship), i will try to access hardware registers of 310 & 320,
which are just not valid for 300. Kernel Crash!!

-- 
viresh


From viresh.kumar at st.com  Tue Mar 27 07:45:37 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Tue, 27 Mar 2012 17:15:37 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <4F71A42C.3090108@st.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203221420.10127.arnd@arndb.de> <4F71961E.2080208@st.com>
 <201203271115.07805.arnd@arndb.de> <4F71A42C.3090108@st.com>
Message-ID: <4F71A861.6090106@st.com>

On 3/27/2012 4:57 PM, Viresh Kumar wrote:
> DT should be up but, nodes would be up only once we call
> of_platform_populate() from this init routine.

I was wrong here atleast :(
Can use these routines here before calling populate().

But question regarding multiple DT_MACHINE_START() is still valid.

-- 
viresh


From sshtylyov at mvista.com  Tue Mar 27 08:12:05 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Tue, 27 Mar 2012 16:12:05 +0400
Subject: [PATCH] amba-pl011: fix panic introduced by "clear pending
 interrupts"
In-Reply-To: <20120326203209.GA8182@mail.gnudd.com>
References: <20120326203209.GA8182@mail.gnudd.com>
Message-ID: <4F71AE95.9080600@mvista.com>

Hello.

On 27-03-2012 0:32, Alessandro Rubini wrote:

> patch 9b96fba, currently in linux-next, clears interrupts using

    Please also specify the summary of this commit in parens.

> uap->port.membase that has not been assigned.  My x86 system,
> that uses a pci-to-amba bridge, panics with a message like:

>     BUG: unable to handle kernel NULL pointer dereference at 00000038
>     IP: [<c12c85ed>] pl011_probe+0x119/0x303

> Signed-off-by: Alessandro Rubini<rubini at gnudd.com>
> Acked-by: Giancarlo Asnaghi<giancarlo.asnaghi at st.com>

WBR, Sergei


From shawn.guo at linaro.org  Tue Mar 27 08:51:24 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 20:51:24 +0800
Subject: [PATCH 09/10] clk: dynamically allocate parent_names basic clk
 registration
In-Reply-To: <20120327085514.GI29317@pengutronix.de>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-10-git-send-email-shawn.guo@linaro.org>
 <20120327085514.GI29317@pengutronix.de>
Message-ID: <20120327125122.GB3719@S2101-09.ap.freescale.net>

On Tue, Mar 27, 2012 at 10:55:14AM +0200, Sascha Hauer wrote:
> On Tue, Mar 27, 2012 at 03:23:28PM +0800, Shawn Guo wrote:
> > It's not necessary to have "char *parent[1]" carried in struct clk_gate
> > and clk_divider.  Instead, it can be dynamically allocated in
> > registration function, just like what clk_register_fixed_rate does.
> 
> I patched it the way it is to get rid of the additional malloc which
> seemed unnecessary. Maybe the real question is whether the core should
> duplicate the parent strings instead of the basic clock types.
> 
If we can ensure the parent strings will only be used during
clk_register call, we do not need to duplicate the parent strings.

But right now the parent strings is used not only in clk_register call
but also __clk_set_parent for finding parent index in case the search
on cached parent points fails.  I guess Mike has a good reason for that.

-- 
Regards,
Shawn


From r65037 at freescale.com  Tue Mar 27 09:03:08 2012
From: r65037 at freescale.com (Zhu Richard-R65037)
Date: Tue, 27 Mar 2012 13:03:08 +0000
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <20120327105819.00d89783@eb-e6520>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
 <20120327105819.00d89783@eb-e6520>
Message-ID: <0E83723C55F66F43A6041464FE31119D0A26D3@039-SN2MPN1-011.039d.mgd.msft.net>

Hi Eric:
I'm on my business trip out of my FSL office, can't reproduce this issue on i.MX25 board now.
Sorry about that.

Best Regards
Richard Zhu

-----Original Message-----
From: Eric B?nard [mailto:eric at eukrea.com] 
Sent: 2012?3?27? 3:58
To: joancarles
Cc: Zhu Richard-R65037; shawn.guo at linaro.org; linux-mmc at vger.kernel.org; Wolfram Sang; linux-arm-kernel at lists.infradead.org
Subject: Re: [MX25][MMC] mmc esdhc failure in 3.3

Hi Joan Carles,

Le Tue, 27 Mar 2012 10:46:45 +0200,
joancarles <joancarles at fqingenieria.es> a ?crit :
> >> This is still present, and we have absolutely no idea where to 
> >> continue searching for the solution of the problem. Any pointers? 
> >> Any git trees of mmc driver changes we could try? Anybody else with 
> >> a MX25 that has this issue?
> >>
> > does that attached patch fix your problem ?
> 
> YES, indeed it does to a certain degree. The timeout errors do not 
> occur anymore and I can successfully perform many fs->ops, such as 
> READ, WRITE, UNLINK ... . So thank you very much for this insight 
> through your patch!
> 
> The speed of the card is excruciatingly slow, however. We roughly get 
> between 34KB/s and 64KB/s from a dd if=/dev/zero write to any of the 
> following partitions:
> 
I have the same speed problem here on i.MX25 but still haven't found the reason.
Shawn, Richard : do you have an idea of why the eSDHC is so slow on
i.MX25 ?

Thanks,
Eric


From shawn.guo at linaro.org  Tue Mar 27 09:10:04 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 27 Mar 2012 21:10:04 +0800
Subject: [PATCH 02/10] clk: remove unnecessary EXPORT_SYMBOL_GPL
In-Reply-To: <20120327092828.GA16397@lunn.ch>
References: <20120327092828.GA16397@lunn.ch>
Message-ID: <20120327131002.GC3719@S2101-09.ap.freescale.net>

On Tue, Mar 27, 2012 at 11:28:28AM +0200, Andrew Lunn wrote:
> > Date: Tue, 27 Mar 2012 15:23:21 +0800
> > From: Shawn Guo <shawn.guo at linaro.org>
> > To: linux-arm-kernel at lists.infradead.org
> > Cc: Shawn Guo <shawn.guo at linaro.org>, Mike Turquette
> >        <mturquette at linaro.org>
> > Subject: [PATCH 02/10] clk: remove unnecessary EXPORT_SYMBOL_GPL
> > Message-ID: <1332833009-4121-3-git-send-email-shawn.guo at linaro.org>
> >
> > It makes no sense to have EXPORT_SYMBOL_GPL on static functions.
> 
> Hi Shawn
> 
> I agree, exporting static functions makes no sense.
> 
> However, i think it would be good to export them. I will probably need
> to build a clk very similar to the gated clock. I would like to use
> these functions when building my ops structure and just add wrappers
> around them where needed.
> 
> Could you instead remove the static?
> 
Hmm, I would not.

I have a similar need for clk_divider_ops calls.  Instead of exporting
every single clk_gate_ops call, we should just export "struct clk_ops
clk_gate_ops".  That's exactly why I have the patch #4 here.

-- 
Regards,
Shawn


From will.deacon at arm.com  Tue Mar 27 09:32:26 2012
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 27 Mar 2012 14:32:26 +0100
Subject: ARM11MPcore: tlb_ops_need_broadcast causes deadlock
In-Reply-To: <274124B9C6907D4B8CE985903EAA19E91B2D5798D9@SI-MBX06.de.bosch.com>
References: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
 <20120323173055.GC16225@mudshark.cambridge.arm.com>
 <274124B9C6907D4B8CE985903EAA19E91B2D5798D9@SI-MBX06.de.bosch.com>
Message-ID: <20120327133226.GE18738@mudshark.cambridge.arm.com>

Peter,

On Mon, Mar 26, 2012 at 05:10:45PM +0100, EXTERNAL Waechtler Peter (Fa. TCP, CM-AI/PJ-CF31) wrote:
> Probably just an "expected deadlock" as mentioned in the comment
> of the v6_early_abort macro:
> 
>  * Purpose : obtain information about current aborted instruction.
>  * Note: we read user space.  This means we might cause a data
>  * abort here if the I-TLB and D-TLB aren't seeing the same
>  * picture.  Unfortunately, this does happen.  We live with it.

I don't see this referring to an expected deadlock.

> For now the errata workarounds are removed for the 11MPcore
> like proposed in this thread to avoid faulting with IRQs turned off:
> 
> http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/041869.html
> 
> But there it looked like an optimization, but it wasn't.

I have a theory about what goes on:

Say we have a valid (i.e. non-faulting) page which contains a load instruction
that will fault. A CPU executes this load and takes a data abort but at the
same time another CPU marks the page being executed as old. So when the
original CPU tries to load the faulting instruction in do_thumb_abort, we take
a second data abort (assumedly because we don't have a D-side TLB entry for the
text page, so we immediately see that it is old) and, because interrupts were
not yet re-enabled in the first fault, they are not enabled in the nested fault
either.

At this point, the faulting CPU will be unable to get the lock on the page,
since the other guy has it and is waiting for the TLB broadcast to complete.
Given that interrupts are disabled on the faulting CPU, everything locks up.

Possible solutions:

(1) Enable interrupts if they are enabled in the faulting context before
    loading instructions on the dabt path.

(2) Use the FSR to determine whather a fault is due to a read or a write on
    ARMv6 - only load and disassemble the instruction on 1136 CPUs affected
    by erratum #325103 (which aren't SMP, so cannot hit the problem above).

The latter is probably best. Please can you try the patch below? I've
checked that it does the right thing on an r0p1 1136 core using a simple
fork/swp program to trigger a CoW.

Will


diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dfb0312..dedb885 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1163,6 +1163,15 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
+config ARM_ERRATA_326103
+       bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
+       depends on CPU_V6
+       help
+         Executing a SWP instruction to read-only memory does not set bit 11
+         of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
+         treat the access as a read, preventing a COW from occurring and
+         causing the faulting task to livelock.
+
 config ARM_ERRATA_411920
        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
        depends on CPU_V6 || CPU_V6K
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index ff1f7cc..8074199 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -26,18 +26,23 @@ ENTRY(v6_early_abort)
        mrc     p15, 0, r1, c5, c0, 0           @ get FSR
        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
 /*
- * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
- * The test below covers all the write situations, including Java bytecodes
+ * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
  */
-       bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
+#ifdef CONFIG_ARM_ERRATA_326103
+       ldr     ip, =0x4107b36
+       mrc     p15, 0, r3, c0, c0, 0           @ get processor id
+       teq     ip, r3, lsr #4                  @ r0 ARM1136?
+       bne     do_DataAbort
        tst     r5, #PSR_J_BIT                  @ Java?
+       tsteq   r5, #PSR_T_BIT                  @ Thumb?
        bne     do_DataAbort
-       do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
-       ldreq   r3, [r4]                        @ read aborted ARM instruction
+       bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
+       ldr     r3, [r4]                        @ read aborted ARM instruction
 #ifdef CONFIG_CPU_ENDIAN_BE8
-       reveq   r3, r3
+       rev     r3, r3
 #endif
        do_ldrd_abort tmp=ip, insn=r3
        tst     r3, #1 << 20                    @ L = 0 -> write
        orreq   r1, r1, #1 << 11                @ yes.
+#endif
        b       do_DataAbort



From arnd at arndb.de  Tue Mar 27 07:59:35 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 27 Mar 2012 11:59:35 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <4F71A42C.3090108@st.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203271115.07805.arnd@arndb.de> <4F71A42C.3090108@st.com>
Message-ID: <201203271159.35306.arnd@arndb.de>

On Tuesday 27 March 2012, Viresh Kumar wrote:
> On 3/27/2012 4:45 PM, Arnd Bergmann wrote:
> > On Tuesday 27 March 2012, Viresh Kumar wrote:
> > The normal way is to turn around the logic so you don't have to include this test
> > at all. Just have one soc-specific init_machine and map_io function, that calls
> > both soc-specific and shared soc functions, e.g.
> 
> But with that, i need multiple DT_MACHINE_START(). Isn't it?
> Is this advisable?

Having one DT_MACHINE_START per soc is ok if it helps you. Of course if you
have multiple ones that are basically identical, it's simpler to just
combine them.

> > In case of the clocks, I think you could already merge all the clk_lookup
> > arrays into one, which would result in a larger kernel image but should
> > do no harm otherwise.
> 
> Actually we can't do it. :(
> If i boot 300 then i will also get clocks of 310 and 320 in my clock list.
> And once i go through this clock list to create clock tree (parent-child
> relationship), i will try to access hardware registers of 310 & 320,
> which are just not valid for 300. Kernel Crash!!

Ok, I see. BTW, have you tried what I first recommended to you, which is
to check the compatible property of the clock node instead of the machine?

Obviously that only works when you initialize the clocks from init_early()
instead of from map_io(), but I think that would be the cleanest choice
if you want to have single function with run-time dependencies.

	Arnd



From m.szyprowski at samsung.com  Tue Mar 27 09:42:34 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:34 +0200
Subject: [PATCHv2 00/14] DMA-mapping framework redesign preparation
Message-ID: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>

Hello everyone,

This is an updated version of the DMA-mapping framework redesign
preparation patches, which resolves issues pointed by Linus:

https://lkml.org/lkml/2012/3/23/305

These patches are the first step to clean up a bit dma-mapping api and
introduce support for architecture specific performance improving hints
in a generic way.

For more information please refer to the thread with the first version
of the patches:

https://lkml.org/lkml/2011/12/23/97


Best regards
Marek Szyprowski
Samsung Poland R&D Center


Patch summary:

Andrzej Pietrasiewicz (8):
  X86 & IA64: adapt for dma_map_ops changes
  MIPS: adapt for dma_map_ops changes
  PowerPC: adapt for dma_map_ops changes
  SPARC: adapt for dma_map_ops changes
  Alpha: adapt for dma_map_ops changes
  SH: adapt for dma_map_ops changes
  Microblaze: adapt for dma_map_ops changes
  Unicore32: adapt for dma_map_ops changes

Marek Szyprowski (6):
  common: dma-mapping: introduce alloc_attrs and free_attrs methods
  Hexagon: adapt for dma_map_ops changes
  common: dma-mapping: remove old alloc_coherent and free_coherent
    methods
  common: dma-mapping: introduce mmap method
  common: DMA-mapping: add WRITE_COMBINE attribute
  common: DMA-mapping: add NON-CONSISTENT attribute

 Documentation/DMA-attributes.txt          |   19 +++++++++++++++++++
 arch/alpha/include/asm/dma-mapping.h      |   18 ++++++++++++------
 arch/alpha/kernel/pci-noop.c              |   10 ++++++----
 arch/alpha/kernel/pci_iommu.c             |   10 ++++++----
 arch/hexagon/include/asm/dma-mapping.h    |   18 ++++++++++++------
 arch/hexagon/kernel/dma.c                 |    9 +++++----
 arch/ia64/hp/common/sba_iommu.c           |   11 ++++++-----
 arch/ia64/include/asm/dma-mapping.h       |   18 ++++++++++++------
 arch/ia64/kernel/pci-swiotlb.c            |   14 +++++++++++---
 arch/ia64/sn/pci/pci_dma.c                |    9 +++++----
 arch/microblaze/include/asm/dma-mapping.h |   18 ++++++++++++------
 arch/microblaze/kernel/dma.c              |   10 ++++++----
 arch/mips/cavium-octeon/dma-octeon.c      |   12 ++++++------
 arch/mips/include/asm/dma-mapping.h       |   18 ++++++++++++------
 arch/mips/mm/dma-default.c                |    8 ++++----
 arch/powerpc/include/asm/dma-mapping.h    |   24 ++++++++++++++++--------
 arch/powerpc/kernel/dma-iommu.c           |   10 ++++++----
 arch/powerpc/kernel/dma-swiotlb.c         |    4 ++--
 arch/powerpc/kernel/dma.c                 |   10 ++++++----
 arch/powerpc/kernel/ibmebus.c             |   10 ++++++----
 arch/powerpc/kernel/vio.c                 |   14 ++++++++------
 arch/powerpc/platforms/cell/iommu.c       |   16 +++++++++-------
 arch/powerpc/platforms/ps3/system-bus.c   |   13 +++++++------
 arch/sh/include/asm/dma-mapping.h         |   28 ++++++++++++++++++----------
 arch/sh/kernel/dma-nommu.c                |    4 ++--
 arch/sh/mm/consistent.c                   |    6 ++++--
 arch/sparc/include/asm/dma-mapping.h      |   18 ++++++++++++------
 arch/sparc/kernel/iommu.c                 |   10 ++++++----
 arch/sparc/kernel/ioport.c                |   18 ++++++++++--------
 arch/sparc/kernel/pci_sun4v.c             |    9 +++++----
 arch/unicore32/include/asm/dma-mapping.h  |   18 ++++++++++++------
 arch/unicore32/mm/dma-swiotlb.c           |   18 ++++++++++++++++--
 arch/x86/include/asm/dma-mapping.h        |   26 ++++++++++++++++----------
 arch/x86/kernel/amd_gart_64.c             |   11 ++++++-----
 arch/x86/kernel/pci-calgary_64.c          |    9 +++++----
 arch/x86/kernel/pci-dma.c                 |    3 ++-
 arch/x86/kernel/pci-nommu.c               |    6 +++---
 arch/x86/kernel/pci-swiotlb.c             |   17 +++++++++++++----
 arch/x86/xen/pci-swiotlb-xen.c            |    4 ++--
 drivers/iommu/amd_iommu.c                 |   10 ++++++----
 drivers/iommu/intel-iommu.c               |    9 +++++----
 drivers/xen/swiotlb-xen.c                 |    5 +++--
 include/linux/dma-attrs.h                 |    2 ++
 include/linux/dma-mapping.h               |   13 +++++++++----
 include/xen/swiotlb-xen.h                 |    6 ++++--
 45 files changed, 355 insertions(+), 198 deletions(-)

-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:40 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:40 +0200
Subject: [PATCHv2 06/14] Alpha: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-7-git-send-email-m.szyprowski@samsung.com>

From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>

Adapt core Alpha architecture code for dma_map_ops changes: replace
alloc/free_coherent with generic alloc/free methods.

Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/alpha/include/asm/dma-mapping.h |   18 ++++++++++++------
 arch/alpha/kernel/pci-noop.c         |   10 ++++++----
 arch/alpha/kernel/pci_iommu.c        |   10 ++++++----
 3 files changed, 24 insertions(+), 14 deletions(-)

diff --git a/arch/alpha/include/asm/dma-mapping.h b/arch/alpha/include/asm/dma-mapping.h
index 4567aca..dfa32f0 100644
--- a/arch/alpha/include/asm/dma-mapping.h
+++ b/arch/alpha/include/asm/dma-mapping.h
@@ -12,16 +12,22 @@ static inline struct dma_map_ops *get_dma_ops(struct device *dev)
 
 #include <asm-generic/dma-mapping-common.h>
 
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t gfp)
+#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)
+
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+				    dma_addr_t *dma_handle, gfp_t gfp,
+				    struct dma_attrs *attrs)
 {
-	return get_dma_ops(dev)->alloc_coherent(dev, size, dma_handle, gfp);
+	return get_dma_ops(dev)->alloc(dev, size, dma_handle, gfp, attrs);
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *vaddr, dma_addr_t dma_handle)
+#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+				  void *vaddr, dma_addr_t dma_handle,
+				  struct dma_attrs *attrs)
 {
-	get_dma_ops(dev)->free_coherent(dev, size, vaddr, dma_handle);
+	get_dma_ops(dev)->free(dev, size, vaddr, dma_handle, attrs);
 }
 
 static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
diff --git a/arch/alpha/kernel/pci-noop.c b/arch/alpha/kernel/pci-noop.c
index 04eea48..df24b76 100644
--- a/arch/alpha/kernel/pci-noop.c
+++ b/arch/alpha/kernel/pci-noop.c
@@ -108,7 +108,8 @@ sys_pciconfig_write(unsigned long bus, unsigned long dfn,
 }
 
 static void *alpha_noop_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t gfp)
+				       dma_addr_t *dma_handle, gfp_t gfp,
+				       struct dma_attrs *attrs)
 {
 	void *ret;
 
@@ -123,7 +124,8 @@ static void *alpha_noop_alloc_coherent(struct device *dev, size_t size,
 }
 
 static void alpha_noop_free_coherent(struct device *dev, size_t size,
-				     void *cpu_addr, dma_addr_t dma_addr)
+				     void *cpu_addr, dma_addr_t dma_addr,
+				     struct dma_attrs *attrs)
 {
 	free_pages((unsigned long)cpu_addr, get_order(size));
 }
@@ -174,8 +176,8 @@ static int alpha_noop_set_mask(struct device *dev, u64 mask)
 }
 
 struct dma_map_ops alpha_noop_ops = {
-	.alloc_coherent		= alpha_noop_alloc_coherent,
-	.free_coherent		= alpha_noop_free_coherent,
+	.alloc			= alpha_noop_alloc_coherent,
+	.free			= alpha_noop_free_coherent,
 	.map_page		= alpha_noop_map_page,
 	.map_sg			= alpha_noop_map_sg,
 	.mapping_error		= alpha_noop_mapping_error,
diff --git a/arch/alpha/kernel/pci_iommu.c b/arch/alpha/kernel/pci_iommu.c
index 4361080..cd63479 100644
--- a/arch/alpha/kernel/pci_iommu.c
+++ b/arch/alpha/kernel/pci_iommu.c
@@ -434,7 +434,8 @@ static void alpha_pci_unmap_page(struct device *dev, dma_addr_t dma_addr,
    else DMA_ADDRP is undefined.  */
 
 static void *alpha_pci_alloc_coherent(struct device *dev, size_t size,
-				      dma_addr_t *dma_addrp, gfp_t gfp)
+				      dma_addr_t *dma_addrp, gfp_t gfp,
+				      struct dma_attrs *attrs)
 {
 	struct pci_dev *pdev = alpha_gendev_to_pci(dev);
 	void *cpu_addr;
@@ -478,7 +479,8 @@ try_again:
    DMA_ADDR past this call are illegal.  */
 
 static void alpha_pci_free_coherent(struct device *dev, size_t size,
-				    void *cpu_addr, dma_addr_t dma_addr)
+				    void *cpu_addr, dma_addr_t dma_addr,
+				    struct dma_attrs *attrs)
 {
 	struct pci_dev *pdev = alpha_gendev_to_pci(dev);
 	pci_unmap_single(pdev, dma_addr, size, PCI_DMA_BIDIRECTIONAL);
@@ -952,8 +954,8 @@ static int alpha_pci_set_mask(struct device *dev, u64 mask)
 }
 
 struct dma_map_ops alpha_pci_ops = {
-	.alloc_coherent		= alpha_pci_alloc_coherent,
-	.free_coherent		= alpha_pci_free_coherent,
+	.alloc			= alpha_pci_alloc_coherent,
+	.free			= alpha_pci_free_coherent,
 	.map_page		= alpha_pci_map_page,
 	.unmap_page		= alpha_pci_unmap_page,
 	.map_sg			= alpha_pci_map_sg,
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:35 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:35 +0200
Subject: [PATCHv2 01/14] common: dma-mapping: introduce alloc_attrs and
 free_attrs methods
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-2-git-send-email-m.szyprowski@samsung.com>

Introduce new generic alloc and free methods with attributes argument.

Existing alloc_coherent and free_coherent can be implemented on top of the
new calls with NULL attributes argument. Later also dma_alloc_non_coherent
can be implemented using DMA_ATTR_NONCOHERENT attribute as well as
dma_alloc_writecombine with separate DMA_ATTR_WRITECOMBINE attribute.

This way the drivers will get more generic, platform independent way of
allocating dma buffers with specific parameters.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
Reviewed-by: David Gibson <david at gibson.dropbear.ud.au>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 include/linux/dma-mapping.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index e13117c..8cc7f95 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -13,6 +13,12 @@ struct dma_map_ops {
 				dma_addr_t *dma_handle, gfp_t gfp);
 	void (*free_coherent)(struct device *dev, size_t size,
 			      void *vaddr, dma_addr_t dma_handle);
+	void* (*alloc)(struct device *dev, size_t size,
+				dma_addr_t *dma_handle, gfp_t gfp,
+				struct dma_attrs *attrs);
+	void (*free)(struct device *dev, size_t size,
+			      void *vaddr, dma_addr_t dma_handle,
+			      struct dma_attrs *attrs);
 	dma_addr_t (*map_page)(struct device *dev, struct page *page,
 			       unsigned long offset, size_t size,
 			       enum dma_data_direction dir,
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:41 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:41 +0200
Subject: [PATCHv2 07/14] SH: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-8-git-send-email-m.szyprowski@samsung.com>

From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>

Adapt core SH architecture code for dma_map_ops changes: replace
alloc/free_coherent with generic alloc/free methods.

Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/sh/include/asm/dma-mapping.h |   28 ++++++++++++++++++----------
 arch/sh/kernel/dma-nommu.c        |    4 ++--
 arch/sh/mm/consistent.c           |    6 ++++--
 3 files changed, 24 insertions(+), 14 deletions(-)

diff --git a/arch/sh/include/asm/dma-mapping.h b/arch/sh/include/asm/dma-mapping.h
index 1a73c3e..8bd965e 100644
--- a/arch/sh/include/asm/dma-mapping.h
+++ b/arch/sh/include/asm/dma-mapping.h
@@ -52,25 +52,31 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 	return dma_addr == 0;
 }
 
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t gfp)
+#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)
+
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+				    dma_addr_t *dma_handle, gfp_t gfp,
+				    struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
 	void *memory;
 
 	if (dma_alloc_from_coherent(dev, size, dma_handle, &memory))
 		return memory;
-	if (!ops->alloc_coherent)
+	if (!ops->alloc)
 		return NULL;
 
-	memory = ops->alloc_coherent(dev, size, dma_handle, gfp);
+	memory = ops->alloc(dev, size, dma_handle, gfp, attrs);
 	debug_dma_alloc_coherent(dev, size, *dma_handle, memory);
 
 	return memory;
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *vaddr, dma_addr_t dma_handle)
+#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+				  void *vaddr, dma_addr_t dma_handle,
+				  struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
 
@@ -78,14 +84,16 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
 		return;
 
 	debug_dma_free_coherent(dev, size, vaddr, dma_handle);
-	if (ops->free_coherent)
-		ops->free_coherent(dev, size, vaddr, dma_handle);
+	if (ops->free)
+		ops->free(dev, size, vaddr, dma_handle, attrs);
 }
 
 /* arch/sh/mm/consistent.c */
 extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
-					dma_addr_t *dma_addr, gfp_t flag);
+					dma_addr_t *dma_addr, gfp_t flag,
+					struct dma_attrs *attrs);
 extern void dma_generic_free_coherent(struct device *dev, size_t size,
-				      void *vaddr, dma_addr_t dma_handle);
+				      void *vaddr, dma_addr_t dma_handle,
+				      struct dma_attrs *attrs);
 
 #endif /* __ASM_SH_DMA_MAPPING_H */
diff --git a/arch/sh/kernel/dma-nommu.c b/arch/sh/kernel/dma-nommu.c
index 3c55b87..5b0bfcd 100644
--- a/arch/sh/kernel/dma-nommu.c
+++ b/arch/sh/kernel/dma-nommu.c
@@ -63,8 +63,8 @@ static void nommu_sync_sg(struct device *dev, struct scatterlist *sg,
 #endif
 
 struct dma_map_ops nommu_dma_ops = {
-	.alloc_coherent		= dma_generic_alloc_coherent,
-	.free_coherent		= dma_generic_free_coherent,
+	.alloc			= dma_generic_alloc_coherent,
+	.free			= dma_generic_free_coherent,
 	.map_page		= nommu_map_page,
 	.map_sg			= nommu_map_sg,
 #ifdef CONFIG_DMA_NONCOHERENT
diff --git a/arch/sh/mm/consistent.c b/arch/sh/mm/consistent.c
index f251b5f..b81d9db 100644
--- a/arch/sh/mm/consistent.c
+++ b/arch/sh/mm/consistent.c
@@ -33,7 +33,8 @@ static int __init dma_init(void)
 fs_initcall(dma_init);
 
 void *dma_generic_alloc_coherent(struct device *dev, size_t size,
-				 dma_addr_t *dma_handle, gfp_t gfp)
+				 dma_addr_t *dma_handle, gfp_t gfp,
+				 struct dma_attrs *attrs)
 {
 	void *ret, *ret_nocache;
 	int order = get_order(size);
@@ -64,7 +65,8 @@ void *dma_generic_alloc_coherent(struct device *dev, size_t size,
 }
 
 void dma_generic_free_coherent(struct device *dev, size_t size,
-			       void *vaddr, dma_addr_t dma_handle)
+			       void *vaddr, dma_addr_t dma_handle,
+			       struct dma_attrs *attrs)
 {
 	int order = get_order(size);
 	unsigned long pfn = dma_handle >> PAGE_SHIFT;
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:44 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:44 +0200
Subject: [PATCHv2 10/14] Hexagon: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-11-git-send-email-m.szyprowski@samsung.com>

Adapt core Hexagon architecture code for dma_map_ops changes: replace
alloc/free_coherent with generic alloc/free methods.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/hexagon/include/asm/dma-mapping.h |   18 ++++++++++++------
 arch/hexagon/kernel/dma.c              |    9 +++++----
 2 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/arch/hexagon/include/asm/dma-mapping.h b/arch/hexagon/include/asm/dma-mapping.h
index 448b224..233ed3d 100644
--- a/arch/hexagon/include/asm/dma-mapping.h
+++ b/arch/hexagon/include/asm/dma-mapping.h
@@ -71,29 +71,35 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 	return (dma_addr == bad_dma_address);
 }
 
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t flag)
+#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)
+
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+				    dma_addr_t *dma_handle, gfp_t flag,
+				    struct dma_attrs *attrs)
 {
 	void *ret;
 	struct dma_map_ops *ops = get_dma_ops(dev);
 
 	BUG_ON(!dma_ops);
 
-	ret = ops->alloc_coherent(dev, size, dma_handle, flag);
+	ret = ops->alloc(dev, size, dma_handle, flag, attrs);
 
 	debug_dma_alloc_coherent(dev, size, *dma_handle, ret);
 
 	return ret;
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *cpu_addr, dma_addr_t dma_handle)
+#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+				  void *cpu_addr, dma_addr_t dma_handle,
+				  struct dma_attrs *attrs)
 {
 	struct dma_map_ops *dma_ops = get_dma_ops(dev);
 
 	BUG_ON(!dma_ops);
 
-	dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
+	dma_ops->free(dev, size, cpu_addr, dma_handle, attrs);
 
 	debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
 }
diff --git a/arch/hexagon/kernel/dma.c b/arch/hexagon/kernel/dma.c
index e711ace..3730221 100644
--- a/arch/hexagon/kernel/dma.c
+++ b/arch/hexagon/kernel/dma.c
@@ -54,7 +54,8 @@ static struct gen_pool *coherent_pool;
 /* Allocates from a pool of uncached memory that was reserved at boot time */
 
 void *hexagon_dma_alloc_coherent(struct device *dev, size_t size,
-				 dma_addr_t *dma_addr, gfp_t flag)
+				 dma_addr_t *dma_addr, gfp_t flag,
+				 struct dma_attrs *attrs)
 {
 	void *ret;
 
@@ -81,7 +82,7 @@ void *hexagon_dma_alloc_coherent(struct device *dev, size_t size,
 }
 
 static void hexagon_free_coherent(struct device *dev, size_t size, void *vaddr,
-				  dma_addr_t dma_addr)
+				  dma_addr_t dma_addr, struct dma_attrs *attrs)
 {
 	gen_pool_free(coherent_pool, (unsigned long) vaddr, size);
 }
@@ -202,8 +203,8 @@ static void hexagon_sync_single_for_device(struct device *dev,
 }
 
 struct dma_map_ops hexagon_dma_ops = {
-	.alloc_coherent	= hexagon_dma_alloc_coherent,
-	.free_coherent	= hexagon_free_coherent,
+	.alloc		= hexagon_dma_alloc_coherent,
+	.free		= hexagon_free_coherent,
 	.map_sg		= hexagon_map_sg,
 	.map_page	= hexagon_map_page,
 	.sync_single_for_cpu = hexagon_sync_single_for_cpu,
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:37 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:37 +0200
Subject: [PATCHv2 03/14] MIPS: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-4-git-send-email-m.szyprowski@samsung.com>

From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>

Adapt core MIPS architecture code for dma_map_ops changes: replace
alloc/free_coherent with generic alloc/free methods.

Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
[added missing changes to arch/mips/cavium-octeon/dma-octeon.c,
 fixed attrs argument in dma-mapping.h]
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/mips/cavium-octeon/dma-octeon.c |   12 ++++++------
 arch/mips/include/asm/dma-mapping.h  |   18 ++++++++++++------
 arch/mips/mm/dma-default.c           |    8 ++++----
 3 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index b6bb92c..41dd0088 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -157,7 +157,7 @@ static void octeon_dma_sync_sg_for_device(struct device *dev,
 }
 
 static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
-	dma_addr_t *dma_handle, gfp_t gfp)
+	dma_addr_t *dma_handle, gfp_t gfp, struct dma_attrs *attrs)
 {
 	void *ret;
 
@@ -192,7 +192,7 @@ static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
 }
 
 static void octeon_dma_free_coherent(struct device *dev, size_t size,
-	void *vaddr, dma_addr_t dma_handle)
+	void *vaddr, dma_addr_t dma_handle, struct dma_attrs *attrs)
 {
 	int order = get_order(size);
 
@@ -240,8 +240,8 @@ EXPORT_SYMBOL(dma_to_phys);
 
 static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
 	.dma_map_ops = {
-		.alloc_coherent = octeon_dma_alloc_coherent,
-		.free_coherent = octeon_dma_free_coherent,
+		.alloc = octeon_dma_alloc_coherent,
+		.free = octeon_dma_free_coherent,
 		.map_page = octeon_dma_map_page,
 		.unmap_page = swiotlb_unmap_page,
 		.map_sg = octeon_dma_map_sg,
@@ -325,8 +325,8 @@ void __init plat_swiotlb_setup(void)
 #ifdef CONFIG_PCI
 static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = {
 	.dma_map_ops = {
-		.alloc_coherent = octeon_dma_alloc_coherent,
-		.free_coherent = octeon_dma_free_coherent,
+		.alloc = octeon_dma_alloc_coherent,
+		.free = octeon_dma_free_coherent,
 		.map_page = octeon_dma_map_page,
 		.unmap_page = swiotlb_unmap_page,
 		.map_sg = octeon_dma_map_sg,
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 7aa37dd..be39a12 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -57,25 +57,31 @@ dma_set_mask(struct device *dev, u64 mask)
 extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
 	       enum dma_data_direction direction);
 
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t gfp)
+#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)
+
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+				    dma_addr_t *dma_handle, gfp_t gfp,
+				    struct dma_attrs *attrs)
 {
 	void *ret;
 	struct dma_map_ops *ops = get_dma_ops(dev);
 
-	ret = ops->alloc_coherent(dev, size, dma_handle, gfp);
+	ret = ops->alloc(dev, size, dma_handle, gfp, attrs);
 
 	debug_dma_alloc_coherent(dev, size, *dma_handle, ret);
 
 	return ret;
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *vaddr, dma_addr_t dma_handle)
+#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+				  void *vaddr, dma_addr_t dma_handle,
+				  struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
 
-	ops->free_coherent(dev, size, vaddr, dma_handle);
+	ops->free(dev, size, vaddr, dma_handle, attrs);
 
 	debug_dma_free_coherent(dev, size, vaddr, dma_handle);
 }
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 4608491..3fab204 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -98,7 +98,7 @@ void *dma_alloc_noncoherent(struct device *dev, size_t size,
 EXPORT_SYMBOL(dma_alloc_noncoherent);
 
 static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
-	dma_addr_t * dma_handle, gfp_t gfp)
+	dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs)
 {
 	void *ret;
 
@@ -132,7 +132,7 @@ void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
 EXPORT_SYMBOL(dma_free_noncoherent);
 
 static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
-	dma_addr_t dma_handle)
+	dma_addr_t dma_handle, struct dma_attrs *attrs)
 {
 	unsigned long addr = (unsigned long) vaddr;
 	int order = get_order(size);
@@ -323,8 +323,8 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
 EXPORT_SYMBOL(dma_cache_sync);
 
 static struct dma_map_ops mips_default_dma_map_ops = {
-	.alloc_coherent = mips_dma_alloc_coherent,
-	.free_coherent = mips_dma_free_coherent,
+	.alloc = mips_dma_alloc_coherent,
+	.free = mips_dma_free_coherent,
 	.map_page = mips_dma_map_page,
 	.unmap_page = mips_dma_unmap_page,
 	.map_sg = mips_dma_map_sg,
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:45 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:45 +0200
Subject: [PATCHv2 11/14] common: dma-mapping: remove old alloc_coherent and
 free_coherent methods
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-12-git-send-email-m.szyprowski@samsung.com>

Remove old, unused alloc_coherent and free_coherent methods from
dma_map_ops structure.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 include/linux/dma-mapping.h |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 8cc7f95..2fc413a 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -9,10 +9,6 @@
 #include <linux/scatterlist.h>
 
 struct dma_map_ops {
-	void* (*alloc_coherent)(struct device *dev, size_t size,
-				dma_addr_t *dma_handle, gfp_t gfp);
-	void (*free_coherent)(struct device *dev, size_t size,
-			      void *vaddr, dma_addr_t dma_handle);
 	void* (*alloc)(struct device *dev, size_t size,
 				dma_addr_t *dma_handle, gfp_t gfp,
 				struct dma_attrs *attrs);
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:38 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:38 +0200
Subject: [PATCHv2 04/14] PowerPC: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-5-git-send-email-m.szyprowski@samsung.com>

From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>

Adapt core PowerPC architecture code for dma_map_ops changes: replace
alloc/free_coherent with generic alloc/free methods.

Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
[added missing changes to arch/powerpc/kernel/vio.c]
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Reviewed-by: David Gibson <david at gibson.dropbear.id.au>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/powerpc/include/asm/dma-mapping.h  |   24 ++++++++++++++++--------
 arch/powerpc/kernel/dma-iommu.c         |   10 ++++++----
 arch/powerpc/kernel/dma-swiotlb.c       |    4 ++--
 arch/powerpc/kernel/dma.c               |   10 ++++++----
 arch/powerpc/kernel/ibmebus.c           |   10 ++++++----
 arch/powerpc/kernel/vio.c               |   14 ++++++++------
 arch/powerpc/platforms/cell/iommu.c     |   16 +++++++++-------
 arch/powerpc/platforms/ps3/system-bus.c |   13 +++++++------
 8 files changed, 60 insertions(+), 41 deletions(-)

diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index dd70fac..62678e3 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -22,9 +22,11 @@
 
 /* Some dma direct funcs must be visible for use in other dma_ops */
 extern void *dma_direct_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t flag);
+				       dma_addr_t *dma_handle, gfp_t flag,
+				       struct dma_attrs *attrs);
 extern void dma_direct_free_coherent(struct device *dev, size_t size,
-				     void *vaddr, dma_addr_t dma_handle);
+				     void *vaddr, dma_addr_t dma_handle,
+				     struct dma_attrs *attrs);
 
 
 #ifdef CONFIG_NOT_COHERENT_CACHE
@@ -130,23 +132,29 @@ static inline int dma_supported(struct device *dev, u64 mask)
 
 extern int dma_set_mask(struct device *dev, u64 dma_mask);
 
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t flag)
+#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)
+
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+				    dma_addr_t *dma_handle, gfp_t flag,
+				    struct dma_attrs *attrs)
 {
 	struct dma_map_ops *dma_ops = get_dma_ops(dev);
 	void *cpu_addr;
 
 	BUG_ON(!dma_ops);
 
-	cpu_addr = dma_ops->alloc_coherent(dev, size, dma_handle, flag);
+	cpu_addr = dma_ops->alloc(dev, size, dma_handle, flag, attrs);
 
 	debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
 
 	return cpu_addr;
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *cpu_addr, dma_addr_t dma_handle)
+#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+				  void *cpu_addr, dma_addr_t dma_handle,
+				  struct dma_attrs *attrs)
 {
 	struct dma_map_ops *dma_ops = get_dma_ops(dev);
 
@@ -154,7 +162,7 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
 
 	debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
 
-	dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
+	dma_ops->free(dev, size, cpu_addr, dma_handle, attrs);
 }
 
 static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c
index 3f6464b..bcfdcd2 100644
--- a/arch/powerpc/kernel/dma-iommu.c
+++ b/arch/powerpc/kernel/dma-iommu.c
@@ -17,7 +17,8 @@
  * to the dma address (mapping) of the first page.
  */
 static void *dma_iommu_alloc_coherent(struct device *dev, size_t size,
-				      dma_addr_t *dma_handle, gfp_t flag)
+				      dma_addr_t *dma_handle, gfp_t flag,
+				      struct dma_attrs *attrs)
 {
 	return iommu_alloc_coherent(dev, get_iommu_table_base(dev), size,
 				    dma_handle, dev->coherent_dma_mask, flag,
@@ -25,7 +26,8 @@ static void *dma_iommu_alloc_coherent(struct device *dev, size_t size,
 }
 
 static void dma_iommu_free_coherent(struct device *dev, size_t size,
-				    void *vaddr, dma_addr_t dma_handle)
+				    void *vaddr, dma_addr_t dma_handle,
+				    struct dma_attrs *attrs)
 {
 	iommu_free_coherent(get_iommu_table_base(dev), size, vaddr, dma_handle);
 }
@@ -105,8 +107,8 @@ static u64 dma_iommu_get_required_mask(struct device *dev)
 }
 
 struct dma_map_ops dma_iommu_ops = {
-	.alloc_coherent		= dma_iommu_alloc_coherent,
-	.free_coherent		= dma_iommu_free_coherent,
+	.alloc			= dma_iommu_alloc_coherent,
+	.free			= dma_iommu_free_coherent,
 	.map_sg			= dma_iommu_map_sg,
 	.unmap_sg		= dma_iommu_unmap_sg,
 	.dma_supported		= dma_iommu_dma_supported,
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index 1ebc918..4ab88da 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -47,8 +47,8 @@ static u64 swiotlb_powerpc_get_required(struct device *dev)
  * for everything else.
  */
 struct dma_map_ops swiotlb_dma_ops = {
-	.alloc_coherent = dma_direct_alloc_coherent,
-	.free_coherent = dma_direct_free_coherent,
+	.alloc = dma_direct_alloc_coherent,
+	.free = dma_direct_free_coherent,
 	.map_sg = swiotlb_map_sg_attrs,
 	.unmap_sg = swiotlb_unmap_sg_attrs,
 	.dma_supported = swiotlb_dma_supported,
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index 7d0233c..b1ec983 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -26,7 +26,8 @@
 
 
 void *dma_direct_alloc_coherent(struct device *dev, size_t size,
-				dma_addr_t *dma_handle, gfp_t flag)
+				dma_addr_t *dma_handle, gfp_t flag,
+				struct dma_attrs *attrs)
 {
 	void *ret;
 #ifdef CONFIG_NOT_COHERENT_CACHE
@@ -54,7 +55,8 @@ void *dma_direct_alloc_coherent(struct device *dev, size_t size,
 }
 
 void dma_direct_free_coherent(struct device *dev, size_t size,
-			      void *vaddr, dma_addr_t dma_handle)
+			      void *vaddr, dma_addr_t dma_handle,
+			      struct dma_attrs *attrs)
 {
 #ifdef CONFIG_NOT_COHERENT_CACHE
 	__dma_free_coherent(size, vaddr);
@@ -150,8 +152,8 @@ static inline void dma_direct_sync_single(struct device *dev,
 #endif
 
 struct dma_map_ops dma_direct_ops = {
-	.alloc_coherent			= dma_direct_alloc_coherent,
-	.free_coherent			= dma_direct_free_coherent,
+	.alloc				= dma_direct_alloc_coherent,
+	.free				= dma_direct_free_coherent,
 	.map_sg				= dma_direct_map_sg,
 	.unmap_sg			= dma_direct_unmap_sg,
 	.dma_supported			= dma_direct_dma_supported,
diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c
index d39ae60..716d918 100644
--- a/arch/powerpc/kernel/ibmebus.c
+++ b/arch/powerpc/kernel/ibmebus.c
@@ -65,7 +65,8 @@ static struct of_device_id __initdata ibmebus_matches[] = {
 static void *ibmebus_alloc_coherent(struct device *dev,
 				    size_t size,
 				    dma_addr_t *dma_handle,
-				    gfp_t flag)
+				    gfp_t flag,
+				    struct dma_attrs *attrs)
 {
 	void *mem;
 
@@ -77,7 +78,8 @@ static void *ibmebus_alloc_coherent(struct device *dev,
 
 static void ibmebus_free_coherent(struct device *dev,
 				  size_t size, void *vaddr,
-				  dma_addr_t dma_handle)
+				  dma_addr_t dma_handle,
+				  struct dma_attrs *attrs)
 {
 	kfree(vaddr);
 }
@@ -136,8 +138,8 @@ static u64 ibmebus_dma_get_required_mask(struct device *dev)
 }
 
 static struct dma_map_ops ibmebus_dma_ops = {
-	.alloc_coherent     = ibmebus_alloc_coherent,
-	.free_coherent      = ibmebus_free_coherent,
+	.alloc              = ibmebus_alloc_coherent,
+	.free               = ibmebus_free_coherent,
 	.map_sg             = ibmebus_map_sg,
 	.unmap_sg           = ibmebus_unmap_sg,
 	.dma_supported      = ibmebus_dma_supported,
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index 8b08629..2d49c32 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -487,7 +487,8 @@ static void vio_cmo_balance(struct work_struct *work)
 }
 
 static void *vio_dma_iommu_alloc_coherent(struct device *dev, size_t size,
-                                          dma_addr_t *dma_handle, gfp_t flag)
+					  dma_addr_t *dma_handle, gfp_t flag,
+					  struct dma_attrs *attrs)
 {
 	struct vio_dev *viodev = to_vio_dev(dev);
 	void *ret;
@@ -497,7 +498,7 @@ static void *vio_dma_iommu_alloc_coherent(struct device *dev, size_t size,
 		return NULL;
 	}
 
-	ret = dma_iommu_ops.alloc_coherent(dev, size, dma_handle, flag);
+	ret = dma_iommu_ops.alloc(dev, size, dma_handle, flag, attrs);
 	if (unlikely(ret == NULL)) {
 		vio_cmo_dealloc(viodev, roundup(size, PAGE_SIZE));
 		atomic_inc(&viodev->cmo.allocs_failed);
@@ -507,11 +508,12 @@ static void *vio_dma_iommu_alloc_coherent(struct device *dev, size_t size,
 }
 
 static void vio_dma_iommu_free_coherent(struct device *dev, size_t size,
-                                        void *vaddr, dma_addr_t dma_handle)
+					void *vaddr, dma_addr_t dma_handle,
+					struct dma_attrs *attrs)
 {
 	struct vio_dev *viodev = to_vio_dev(dev);
 
-	dma_iommu_ops.free_coherent(dev, size, vaddr, dma_handle);
+	dma_iommu_ops.free(dev, size, vaddr, dma_handle, attrs);
 
 	vio_cmo_dealloc(viodev, roundup(size, PAGE_SIZE));
 }
@@ -612,8 +614,8 @@ static u64 vio_dma_get_required_mask(struct device *dev)
 }
 
 struct dma_map_ops vio_dma_mapping_ops = {
-	.alloc_coherent    = vio_dma_iommu_alloc_coherent,
-	.free_coherent     = vio_dma_iommu_free_coherent,
+	.alloc             = vio_dma_iommu_alloc_coherent,
+	.free              = vio_dma_iommu_free_coherent,
 	.map_sg            = vio_dma_iommu_map_sg,
 	.unmap_sg          = vio_dma_iommu_unmap_sg,
 	.map_page          = vio_dma_iommu_map_page,
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index ae9fc7b..b9f509a 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -564,7 +564,8 @@ static struct iommu_table *cell_get_iommu_table(struct device *dev)
 /* A coherent allocation implies strong ordering */
 
 static void *dma_fixed_alloc_coherent(struct device *dev, size_t size,
-				      dma_addr_t *dma_handle, gfp_t flag)
+				      dma_addr_t *dma_handle, gfp_t flag,
+				      struct dma_attrs *attrs)
 {
 	if (iommu_fixed_is_weak)
 		return iommu_alloc_coherent(dev, cell_get_iommu_table(dev),
@@ -572,18 +573,19 @@ static void *dma_fixed_alloc_coherent(struct device *dev, size_t size,
 					    device_to_mask(dev), flag,
 					    dev_to_node(dev));
 	else
-		return dma_direct_ops.alloc_coherent(dev, size, dma_handle,
-						     flag);
+		return dma_direct_ops.alloc(dev, size, dma_handle, flag,
+					    attrs);
 }
 
 static void dma_fixed_free_coherent(struct device *dev, size_t size,
-				    void *vaddr, dma_addr_t dma_handle)
+				    void *vaddr, dma_addr_t dma_handle,
+				    struct dma_attrs *attrs)
 {
 	if (iommu_fixed_is_weak)
 		iommu_free_coherent(cell_get_iommu_table(dev), size, vaddr,
 				    dma_handle);
 	else
-		dma_direct_ops.free_coherent(dev, size, vaddr, dma_handle);
+		dma_direct_ops.free(dev, size, vaddr, dma_handle, attrs);
 }
 
 static dma_addr_t dma_fixed_map_page(struct device *dev, struct page *page,
@@ -642,8 +644,8 @@ static int dma_fixed_dma_supported(struct device *dev, u64 mask)
 static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask);
 
 struct dma_map_ops dma_iommu_fixed_ops = {
-	.alloc_coherent = dma_fixed_alloc_coherent,
-	.free_coherent  = dma_fixed_free_coherent,
+	.alloc          = dma_fixed_alloc_coherent,
+	.free           = dma_fixed_free_coherent,
 	.map_sg         = dma_fixed_map_sg,
 	.unmap_sg       = dma_fixed_unmap_sg,
 	.dma_supported  = dma_fixed_dma_supported,
diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c
index 880eb9c..5606fe3 100644
--- a/arch/powerpc/platforms/ps3/system-bus.c
+++ b/arch/powerpc/platforms/ps3/system-bus.c
@@ -515,7 +515,8 @@ core_initcall(ps3_system_bus_init);
  * to the dma address (mapping) of the first page.
  */
 static void * ps3_alloc_coherent(struct device *_dev, size_t size,
-				      dma_addr_t *dma_handle, gfp_t flag)
+				 dma_addr_t *dma_handle, gfp_t flag,
+				 struct dma_attrs *attrs)
 {
 	int result;
 	struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev);
@@ -552,7 +553,7 @@ clean_none:
 }
 
 static void ps3_free_coherent(struct device *_dev, size_t size, void *vaddr,
-	dma_addr_t dma_handle)
+			      dma_addr_t dma_handle, struct dma_attrs *attrs)
 {
 	struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev);
 
@@ -701,8 +702,8 @@ static u64 ps3_dma_get_required_mask(struct device *_dev)
 }
 
 static struct dma_map_ops ps3_sb_dma_ops = {
-	.alloc_coherent = ps3_alloc_coherent,
-	.free_coherent = ps3_free_coherent,
+	.alloc = ps3_alloc_coherent,
+	.free = ps3_free_coherent,
 	.map_sg = ps3_sb_map_sg,
 	.unmap_sg = ps3_sb_unmap_sg,
 	.dma_supported = ps3_dma_supported,
@@ -712,8 +713,8 @@ static struct dma_map_ops ps3_sb_dma_ops = {
 };
 
 static struct dma_map_ops ps3_ioc0_dma_ops = {
-	.alloc_coherent = ps3_alloc_coherent,
-	.free_coherent = ps3_free_coherent,
+	.alloc = ps3_alloc_coherent,
+	.free = ps3_free_coherent,
 	.map_sg = ps3_ioc0_map_sg,
 	.unmap_sg = ps3_ioc0_unmap_sg,
 	.dma_supported = ps3_dma_supported,
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:36 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:36 +0200
Subject: [PATCHv2 02/14] X86 & IA64: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-3-git-send-email-m.szyprowski@samsung.com>

From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>

Adapt core x86 and IA64 architecture code for dma_map_ops changes: replace
alloc/free_coherent with generic alloc/free methods.

Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
[removed swiotlb related changes and replaced it with wrappers,
 merged with IA64 patch to avoid inter-patch dependences in intel-iommu code]
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/ia64/hp/common/sba_iommu.c     |   11 ++++++-----
 arch/ia64/include/asm/dma-mapping.h |   18 ++++++++++++------
 arch/ia64/kernel/pci-swiotlb.c      |   14 +++++++++++---
 arch/ia64/sn/pci/pci_dma.c          |    9 +++++----
 arch/x86/include/asm/dma-mapping.h  |   26 ++++++++++++++++----------
 arch/x86/kernel/amd_gart_64.c       |   11 ++++++-----
 arch/x86/kernel/pci-calgary_64.c    |    9 +++++----
 arch/x86/kernel/pci-dma.c           |    3 ++-
 arch/x86/kernel/pci-nommu.c         |    6 +++---
 arch/x86/kernel/pci-swiotlb.c       |   17 +++++++++++++----
 arch/x86/xen/pci-swiotlb-xen.c      |    4 ++--
 drivers/iommu/amd_iommu.c           |   10 ++++++----
 drivers/iommu/intel-iommu.c         |    9 +++++----
 drivers/xen/swiotlb-xen.c           |    5 +++--
 include/xen/swiotlb-xen.h           |    6 ++++--
 15 files changed, 99 insertions(+), 59 deletions(-)

diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c
index f5f4ef1..e5eb9c4 100644
--- a/arch/ia64/hp/common/sba_iommu.c
+++ b/arch/ia64/hp/common/sba_iommu.c
@@ -1130,7 +1130,8 @@ void sba_unmap_single_attrs(struct device *dev, dma_addr_t iova, size_t size,
  * See Documentation/DMA-API-HOWTO.txt
  */
 static void *
-sba_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flags)
+sba_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
+		   gfp_t flags, struct dma_attrs *attrs)
 {
 	struct ioc *ioc;
 	void *addr;
@@ -1192,8 +1193,8 @@ sba_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, gfp
  *
  * See Documentation/DMA-API-HOWTO.txt
  */
-static void sba_free_coherent (struct device *dev, size_t size, void *vaddr,
-			       dma_addr_t dma_handle)
+static void sba_free_coherent(struct device *dev, size_t size, void *vaddr,
+			      dma_addr_t dma_handle, struct dma_attrs *attrs)
 {
 	sba_unmap_single_attrs(dev, dma_handle, size, 0, NULL);
 	free_pages((unsigned long) vaddr, get_order(size));
@@ -2213,8 +2214,8 @@ sba_page_override(char *str)
 __setup("sbapagesize=",sba_page_override);
 
 struct dma_map_ops sba_dma_ops = {
-	.alloc_coherent		= sba_alloc_coherent,
-	.free_coherent		= sba_free_coherent,
+	.alloc			= sba_alloc_coherent,
+	.free			= sba_free_coherent,
 	.map_page		= sba_map_page,
 	.unmap_page		= sba_unmap_page,
 	.map_sg			= sba_map_sg_attrs,
diff --git a/arch/ia64/include/asm/dma-mapping.h b/arch/ia64/include/asm/dma-mapping.h
index 4336d08..4f5e814 100644
--- a/arch/ia64/include/asm/dma-mapping.h
+++ b/arch/ia64/include/asm/dma-mapping.h
@@ -23,23 +23,29 @@ extern void machvec_dma_sync_single(struct device *, dma_addr_t, size_t,
 extern void machvec_dma_sync_sg(struct device *, struct scatterlist *, int,
 				enum dma_data_direction);
 
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *daddr, gfp_t gfp)
+#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)
+
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+				    dma_addr_t *daddr, gfp_t gfp,
+				    struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = platform_dma_get_ops(dev);
 	void *caddr;
 
-	caddr = ops->alloc_coherent(dev, size, daddr, gfp);
+	caddr = ops->alloc(dev, size, daddr, gfp, attrs);
 	debug_dma_alloc_coherent(dev, size, *daddr, caddr);
 	return caddr;
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *caddr, dma_addr_t daddr)
+#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+				  void *caddr, dma_addr_t daddr,
+				  struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = platform_dma_get_ops(dev);
 	debug_dma_free_coherent(dev, size, caddr, daddr);
-	ops->free_coherent(dev, size, caddr, daddr);
+	ops->free(dev, size, caddr, daddr, attrs);
 }
 
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
diff --git a/arch/ia64/kernel/pci-swiotlb.c b/arch/ia64/kernel/pci-swiotlb.c
index d9485d9..939260a 100644
--- a/arch/ia64/kernel/pci-swiotlb.c
+++ b/arch/ia64/kernel/pci-swiotlb.c
@@ -15,16 +15,24 @@ int swiotlb __read_mostly;
 EXPORT_SYMBOL(swiotlb);
 
 static void *ia64_swiotlb_alloc_coherent(struct device *dev, size_t size,
-					 dma_addr_t *dma_handle, gfp_t gfp)
+					 dma_addr_t *dma_handle, gfp_t gfp,
+					 struct dma_attrs *attrs)
 {
 	if (dev->coherent_dma_mask != DMA_BIT_MASK(64))
 		gfp |= GFP_DMA;
 	return swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
 }
 
+static void ia64_swiotlb_free_coherent(struct device *dev, size_t size,
+				       void *vaddr, dma_addr_t dma_addr,
+				       struct dma_attrs *attrs)
+{
+	swiotlb_free_coherent(dev, size, vaddr, dma_addr);
+}
+
 struct dma_map_ops swiotlb_dma_ops = {
-	.alloc_coherent = ia64_swiotlb_alloc_coherent,
-	.free_coherent = swiotlb_free_coherent,
+	.alloc = ia64_swiotlb_alloc_coherent,
+	.free = ia64_swiotlb_free_coherent,
 	.map_page = swiotlb_map_page,
 	.unmap_page = swiotlb_unmap_page,
 	.map_sg = swiotlb_map_sg_attrs,
diff --git a/arch/ia64/sn/pci/pci_dma.c b/arch/ia64/sn/pci/pci_dma.c
index a9d310d..3290d6e 100644
--- a/arch/ia64/sn/pci/pci_dma.c
+++ b/arch/ia64/sn/pci/pci_dma.c
@@ -76,7 +76,8 @@ EXPORT_SYMBOL(sn_dma_set_mask);
  * more information.
  */
 static void *sn_dma_alloc_coherent(struct device *dev, size_t size,
-				   dma_addr_t * dma_handle, gfp_t flags)
+				   dma_addr_t * dma_handle, gfp_t flags,
+				   struct dma_attrs *attrs)
 {
 	void *cpuaddr;
 	unsigned long phys_addr;
@@ -137,7 +138,7 @@ static void *sn_dma_alloc_coherent(struct device *dev, size_t size,
  * any associated IOMMU mappings.
  */
 static void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
-				 dma_addr_t dma_handle)
+				 dma_addr_t dma_handle, struct dma_attrs *attrs)
 {
 	struct pci_dev *pdev = to_pci_dev(dev);
 	struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
@@ -466,8 +467,8 @@ int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 }
 
 static struct dma_map_ops sn_dma_ops = {
-	.alloc_coherent		= sn_dma_alloc_coherent,
-	.free_coherent		= sn_dma_free_coherent,
+	.alloc			= sn_dma_alloc_coherent,
+	.free			= sn_dma_free_coherent,
 	.map_page		= sn_dma_map_page,
 	.unmap_page		= sn_dma_unmap_page,
 	.map_sg			= sn_dma_map_sg,
diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h
index ed3065f..4b4331d 100644
--- a/arch/x86/include/asm/dma-mapping.h
+++ b/arch/x86/include/asm/dma-mapping.h
@@ -59,7 +59,8 @@ extern int dma_supported(struct device *hwdev, u64 mask);
 extern int dma_set_mask(struct device *dev, u64 mask);
 
 extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
-					dma_addr_t *dma_addr, gfp_t flag);
+					dma_addr_t *dma_addr, gfp_t flag,
+					struct dma_attrs *attrs);
 
 static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
 {
@@ -111,9 +112,11 @@ static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
        return gfp;
 }
 
+#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)
+
 static inline void *
-dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
-		gfp_t gfp)
+dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
+		gfp_t gfp, struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
 	void *memory;
@@ -129,18 +132,21 @@ dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
 	if (!is_device_dma_capable(dev))
 		return NULL;
 
-	if (!ops->alloc_coherent)
+	if (!ops->alloc)
 		return NULL;
 
-	memory = ops->alloc_coherent(dev, size, dma_handle,
-				     dma_alloc_coherent_gfp_flags(dev, gfp));
+	memory = ops->alloc(dev, size, dma_handle,
+			    dma_alloc_coherent_gfp_flags(dev, gfp), attrs);
 	debug_dma_alloc_coherent(dev, size, *dma_handle, memory);
 
 	return memory;
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *vaddr, dma_addr_t bus)
+#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+				  void *vaddr, dma_addr_t bus,
+				  struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
 
@@ -150,8 +156,8 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
 		return;
 
 	debug_dma_free_coherent(dev, size, vaddr, bus);
-	if (ops->free_coherent)
-		ops->free_coherent(dev, size, vaddr, bus);
+	if (ops->free)
+		ops->free(dev, size, vaddr, bus, attrs);
 }
 
 #endif
diff --git a/arch/x86/kernel/amd_gart_64.c b/arch/x86/kernel/amd_gart_64.c
index b1e7c7f..e663112 100644
--- a/arch/x86/kernel/amd_gart_64.c
+++ b/arch/x86/kernel/amd_gart_64.c
@@ -477,7 +477,7 @@ error:
 /* allocate and map a coherent mapping */
 static void *
 gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
-		    gfp_t flag)
+		    gfp_t flag, struct dma_attrs *attrs)
 {
 	dma_addr_t paddr;
 	unsigned long align_mask;
@@ -500,7 +500,8 @@ gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
 		}
 		__free_pages(page, get_order(size));
 	} else
-		return dma_generic_alloc_coherent(dev, size, dma_addr, flag);
+		return dma_generic_alloc_coherent(dev, size, dma_addr, flag,
+						  attrs);
 
 	return NULL;
 }
@@ -508,7 +509,7 @@ gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
 /* free a coherent mapping */
 static void
 gart_free_coherent(struct device *dev, size_t size, void *vaddr,
-		   dma_addr_t dma_addr)
+		   dma_addr_t dma_addr, struct dma_attrs *attrs)
 {
 	gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, NULL);
 	free_pages((unsigned long)vaddr, get_order(size));
@@ -700,8 +701,8 @@ static struct dma_map_ops gart_dma_ops = {
 	.unmap_sg			= gart_unmap_sg,
 	.map_page			= gart_map_page,
 	.unmap_page			= gart_unmap_page,
-	.alloc_coherent			= gart_alloc_coherent,
-	.free_coherent			= gart_free_coherent,
+	.alloc				= gart_alloc_coherent,
+	.free				= gart_free_coherent,
 	.mapping_error			= gart_mapping_error,
 };
 
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index 726494b..07b587c 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -431,7 +431,7 @@ static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
 }
 
 static void* calgary_alloc_coherent(struct device *dev, size_t size,
-	dma_addr_t *dma_handle, gfp_t flag)
+	dma_addr_t *dma_handle, gfp_t flag, struct dma_attrs *attrs)
 {
 	void *ret = NULL;
 	dma_addr_t mapping;
@@ -464,7 +464,8 @@ error:
 }
 
 static void calgary_free_coherent(struct device *dev, size_t size,
-				  void *vaddr, dma_addr_t dma_handle)
+				  void *vaddr, dma_addr_t dma_handle,
+				  struct dma_attrs *attrs)
 {
 	unsigned int npages;
 	struct iommu_table *tbl = find_iommu_table(dev);
@@ -477,8 +478,8 @@ static void calgary_free_coherent(struct device *dev, size_t size,
 }
 
 static struct dma_map_ops calgary_dma_ops = {
-	.alloc_coherent = calgary_alloc_coherent,
-	.free_coherent = calgary_free_coherent,
+	.alloc = calgary_alloc_coherent,
+	.free = calgary_free_coherent,
 	.map_sg = calgary_map_sg,
 	.unmap_sg = calgary_unmap_sg,
 	.map_page = calgary_map_page,
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 1c4d769..75e1cc1 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -96,7 +96,8 @@ void __init pci_iommu_alloc(void)
 	}
 }
 void *dma_generic_alloc_coherent(struct device *dev, size_t size,
-				 dma_addr_t *dma_addr, gfp_t flag)
+				 dma_addr_t *dma_addr, gfp_t flag,
+				 struct dma_attrs *attrs)
 {
 	unsigned long dma_mask;
 	struct page *page;
diff --git a/arch/x86/kernel/pci-nommu.c b/arch/x86/kernel/pci-nommu.c
index 3af4af8..f960506 100644
--- a/arch/x86/kernel/pci-nommu.c
+++ b/arch/x86/kernel/pci-nommu.c
@@ -75,7 +75,7 @@ static int nommu_map_sg(struct device *hwdev, struct scatterlist *sg,
 }
 
 static void nommu_free_coherent(struct device *dev, size_t size, void *vaddr,
-				dma_addr_t dma_addr)
+				dma_addr_t dma_addr, struct dma_attrs *attrs)
 {
 	free_pages((unsigned long)vaddr, get_order(size));
 }
@@ -96,8 +96,8 @@ static void nommu_sync_sg_for_device(struct device *dev,
 }
 
 struct dma_map_ops nommu_dma_ops = {
-	.alloc_coherent		= dma_generic_alloc_coherent,
-	.free_coherent		= nommu_free_coherent,
+	.alloc			= dma_generic_alloc_coherent,
+	.free			= nommu_free_coherent,
 	.map_sg			= nommu_map_sg,
 	.map_page		= nommu_map_page,
 	.sync_single_for_device = nommu_sync_single_for_device,
diff --git a/arch/x86/kernel/pci-swiotlb.c b/arch/x86/kernel/pci-swiotlb.c
index 8f972cb..6c483ba 100644
--- a/arch/x86/kernel/pci-swiotlb.c
+++ b/arch/x86/kernel/pci-swiotlb.c
@@ -15,21 +15,30 @@
 int swiotlb __read_mostly;
 
 static void *x86_swiotlb_alloc_coherent(struct device *hwdev, size_t size,
-					dma_addr_t *dma_handle, gfp_t flags)
+					dma_addr_t *dma_handle, gfp_t flags,
+					struct dma_attrs *attrs)
 {
 	void *vaddr;
 
-	vaddr = dma_generic_alloc_coherent(hwdev, size, dma_handle, flags);
+	vaddr = dma_generic_alloc_coherent(hwdev, size, dma_handle, flags,
+					   attrs);
 	if (vaddr)
 		return vaddr;
 
 	return swiotlb_alloc_coherent(hwdev, size, dma_handle, flags);
 }
 
+static void x86_swiotlb_free_coherent(struct device *dev, size_t size,
+				      void *vaddr, dma_addr_t dma_addr,
+				      struct dma_attrs *attrs)
+{
+	swiotlb_free_coherent(dev, size, vaddr, dma_addr);
+}
+
 static struct dma_map_ops swiotlb_dma_ops = {
 	.mapping_error = swiotlb_dma_mapping_error,
-	.alloc_coherent = x86_swiotlb_alloc_coherent,
-	.free_coherent = swiotlb_free_coherent,
+	.alloc = x86_swiotlb_alloc_coherent,
+	.free = x86_swiotlb_free_coherent,
 	.sync_single_for_cpu = swiotlb_sync_single_for_cpu,
 	.sync_single_for_device = swiotlb_sync_single_for_device,
 	.sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
diff --git a/arch/x86/xen/pci-swiotlb-xen.c b/arch/x86/xen/pci-swiotlb-xen.c
index b480d42..967633a 100644
--- a/arch/x86/xen/pci-swiotlb-xen.c
+++ b/arch/x86/xen/pci-swiotlb-xen.c
@@ -12,8 +12,8 @@ int xen_swiotlb __read_mostly;
 
 static struct dma_map_ops xen_swiotlb_dma_ops = {
 	.mapping_error = xen_swiotlb_dma_mapping_error,
-	.alloc_coherent = xen_swiotlb_alloc_coherent,
-	.free_coherent = xen_swiotlb_free_coherent,
+	.alloc = xen_swiotlb_alloc_coherent,
+	.free = xen_swiotlb_free_coherent,
 	.sync_single_for_cpu = xen_swiotlb_sync_single_for_cpu,
 	.sync_single_for_device = xen_swiotlb_sync_single_for_device,
 	.sync_sg_for_cpu = xen_swiotlb_sync_sg_for_cpu,
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index f75e060..daa333f 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -2707,7 +2707,8 @@ static void unmap_sg(struct device *dev, struct scatterlist *sglist,
  * The exported alloc_coherent function for dma_ops.
  */
 static void *alloc_coherent(struct device *dev, size_t size,
-			    dma_addr_t *dma_addr, gfp_t flag)
+			    dma_addr_t *dma_addr, gfp_t flag,
+			    struct dma_attrs *attrs)
 {
 	unsigned long flags;
 	void *virt_addr;
@@ -2765,7 +2766,8 @@ out_free:
  * The exported free_coherent function for dma_ops.
  */
 static void free_coherent(struct device *dev, size_t size,
-			  void *virt_addr, dma_addr_t dma_addr)
+			  void *virt_addr, dma_addr_t dma_addr,
+			  struct dma_attrs *attrs)
 {
 	unsigned long flags;
 	struct protection_domain *domain;
@@ -2846,8 +2848,8 @@ static void prealloc_protection_domains(void)
 }
 
 static struct dma_map_ops amd_iommu_dma_ops = {
-	.alloc_coherent = alloc_coherent,
-	.free_coherent = free_coherent,
+	.alloc = alloc_coherent,
+	.free = free_coherent,
 	.map_page = map_page,
 	.unmap_page = unmap_page,
 	.map_sg = map_sg,
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index c9c6053..e39bfdc 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -2938,7 +2938,8 @@ static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
 }
 
 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
-				  dma_addr_t *dma_handle, gfp_t flags)
+				  dma_addr_t *dma_handle, gfp_t flags,
+				  struct dma_attrs *attrs)
 {
 	void *vaddr;
 	int order;
@@ -2970,7 +2971,7 @@ static void *intel_alloc_coherent(struct device *hwdev, size_t size,
 }
 
 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
-				dma_addr_t dma_handle)
+				dma_addr_t dma_handle, struct dma_attrs *attrs)
 {
 	int order;
 
@@ -3115,8 +3116,8 @@ static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
 }
 
 struct dma_map_ops intel_dma_ops = {
-	.alloc_coherent = intel_alloc_coherent,
-	.free_coherent = intel_free_coherent,
+	.alloc = intel_alloc_coherent,
+	.free = intel_free_coherent,
 	.map_sg = intel_map_sg,
 	.unmap_sg = intel_unmap_sg,
 	.map_page = intel_map_page,
diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c
index 19e6a20..1afb4fb 100644
--- a/drivers/xen/swiotlb-xen.c
+++ b/drivers/xen/swiotlb-xen.c
@@ -204,7 +204,8 @@ error:
 
 void *
 xen_swiotlb_alloc_coherent(struct device *hwdev, size_t size,
-			   dma_addr_t *dma_handle, gfp_t flags)
+			   dma_addr_t *dma_handle, gfp_t flags,
+			   struct dma_attrs *attrs)
 {
 	void *ret;
 	int order = get_order(size);
@@ -253,7 +254,7 @@ EXPORT_SYMBOL_GPL(xen_swiotlb_alloc_coherent);
 
 void
 xen_swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr,
-			  dma_addr_t dev_addr)
+			  dma_addr_t dev_addr, struct dma_attrs *attrs)
 {
 	int order = get_order(size);
 	phys_addr_t phys;
diff --git a/include/xen/swiotlb-xen.h b/include/xen/swiotlb-xen.h
index 2ea2fdc..4f4d449 100644
--- a/include/xen/swiotlb-xen.h
+++ b/include/xen/swiotlb-xen.h
@@ -7,11 +7,13 @@ extern void xen_swiotlb_init(int verbose);
 
 extern void
 *xen_swiotlb_alloc_coherent(struct device *hwdev, size_t size,
-			    dma_addr_t *dma_handle, gfp_t flags);
+			    dma_addr_t *dma_handle, gfp_t flags,
+			    struct dma_attrs *attrs);
 
 extern void
 xen_swiotlb_free_coherent(struct device *hwdev, size_t size,
-			  void *vaddr, dma_addr_t dma_handle);
+			  void *vaddr, dma_addr_t dma_handle,
+			  struct dma_attrs *attrs);
 
 extern dma_addr_t xen_swiotlb_map_page(struct device *dev, struct page *page,
 				       unsigned long offset, size_t size,
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:47 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:47 +0200
Subject: [PATCHv2 13/14] common: DMA-mapping: add WRITE_COMBINE attribute
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-14-git-send-email-m.szyprowski@samsung.com>

DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
buffered to improve performance. It will be used by the replacement for
ARM/ARV32 specific dma_alloc_writecombine() function.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 Documentation/DMA-attributes.txt |   10 ++++++++++
 include/linux/dma-attrs.h        |    1 +
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt
index b768cc0..811a5d4 100644
--- a/Documentation/DMA-attributes.txt
+++ b/Documentation/DMA-attributes.txt
@@ -31,3 +31,13 @@ may be weakly ordered, that is that reads and writes may pass each other.
 Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
 those that do not will simply ignore the attribute and exhibit default
 behavior.
+
+DMA_ATTR_WRITE_COMBINE
+----------------------
+
+DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be
+buffered to improve performance.
+
+Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE,
+those that do not will simply ignore the attribute and exhibit default
+behavior.
diff --git a/include/linux/dma-attrs.h b/include/linux/dma-attrs.h
index 71ad34e..ada61e1 100644
--- a/include/linux/dma-attrs.h
+++ b/include/linux/dma-attrs.h
@@ -13,6 +13,7 @@
 enum dma_attr {
 	DMA_ATTR_WRITE_BARRIER,
 	DMA_ATTR_WEAK_ORDERING,
+	DMA_ATTR_WRITE_COMBINE,
 	DMA_ATTR_MAX,
 };
 
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:39 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:39 +0200
Subject: [PATCHv2 05/14] SPARC: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-6-git-send-email-m.szyprowski@samsung.com>

From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>

Adapt core SPARC architecture code for dma_map_ops changes: replace
alloc/free_coherent with generic alloc/free methods.

Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: David S. Miller <davem at davemloft.net>
---
 arch/sparc/include/asm/dma-mapping.h |   18 ++++++++++++------
 arch/sparc/kernel/iommu.c            |   10 ++++++----
 arch/sparc/kernel/ioport.c           |   18 ++++++++++--------
 arch/sparc/kernel/pci_sun4v.c        |    9 +++++----
 4 files changed, 33 insertions(+), 22 deletions(-)

diff --git a/arch/sparc/include/asm/dma-mapping.h b/arch/sparc/include/asm/dma-mapping.h
index 8c0e4f7..48a7c65 100644
--- a/arch/sparc/include/asm/dma-mapping.h
+++ b/arch/sparc/include/asm/dma-mapping.h
@@ -26,24 +26,30 @@ static inline struct dma_map_ops *get_dma_ops(struct device *dev)
 
 #include <asm-generic/dma-mapping-common.h>
 
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t flag)
+#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)
+
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+				    dma_addr_t *dma_handle, gfp_t flag,
+				    struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
 	void *cpu_addr;
 
-	cpu_addr = ops->alloc_coherent(dev, size, dma_handle, flag);
+	cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
 	debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
 	return cpu_addr;
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *cpu_addr, dma_addr_t dma_handle)
+#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+				  void *cpu_addr, dma_addr_t dma_handle,
+				  struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
 
 	debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
-	ops->free_coherent(dev, size, cpu_addr, dma_handle);
+	ops->free(dev, size, cpu_addr, dma_handle, attrs);
 }
 
 static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
diff --git a/arch/sparc/kernel/iommu.c b/arch/sparc/kernel/iommu.c
index 4643d68..070ed14 100644
--- a/arch/sparc/kernel/iommu.c
+++ b/arch/sparc/kernel/iommu.c
@@ -280,7 +280,8 @@ static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
 }
 
 static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
-				   dma_addr_t *dma_addrp, gfp_t gfp)
+				   dma_addr_t *dma_addrp, gfp_t gfp,
+				   struct dma_attrs *attrs)
 {
 	unsigned long flags, order, first_page;
 	struct iommu *iommu;
@@ -330,7 +331,8 @@ static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
 }
 
 static void dma_4u_free_coherent(struct device *dev, size_t size,
-				 void *cpu, dma_addr_t dvma)
+				 void *cpu, dma_addr_t dvma,
+				 struct dma_attrs *attrs)
 {
 	struct iommu *iommu;
 	unsigned long flags, order, npages;
@@ -825,8 +827,8 @@ static void dma_4u_sync_sg_for_cpu(struct device *dev,
 }
 
 static struct dma_map_ops sun4u_dma_ops = {
-	.alloc_coherent		= dma_4u_alloc_coherent,
-	.free_coherent		= dma_4u_free_coherent,
+	.alloc			= dma_4u_alloc_coherent,
+	.free			= dma_4u_free_coherent,
 	.map_page		= dma_4u_map_page,
 	.unmap_page		= dma_4u_unmap_page,
 	.map_sg			= dma_4u_map_sg,
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index d0479e2..21bd739 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -261,7 +261,8 @@ EXPORT_SYMBOL(sbus_set_sbus64);
  * CPU may access them without any explicit flushing.
  */
 static void *sbus_alloc_coherent(struct device *dev, size_t len,
-				 dma_addr_t *dma_addrp, gfp_t gfp)
+				 dma_addr_t *dma_addrp, gfp_t gfp,
+				 struct dma_attrs *attrs)
 {
 	struct platform_device *op = to_platform_device(dev);
 	unsigned long len_total = PAGE_ALIGN(len);
@@ -315,7 +316,7 @@ err_nopages:
 }
 
 static void sbus_free_coherent(struct device *dev, size_t n, void *p,
-			       dma_addr_t ba)
+			       dma_addr_t ba, struct dma_attrs *attrs)
 {
 	struct resource *res;
 	struct page *pgv;
@@ -407,8 +408,8 @@ static void sbus_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
 }
 
 struct dma_map_ops sbus_dma_ops = {
-	.alloc_coherent		= sbus_alloc_coherent,
-	.free_coherent		= sbus_free_coherent,
+	.alloc			= sbus_alloc_coherent,
+	.free			= sbus_free_coherent,
 	.map_page		= sbus_map_page,
 	.unmap_page		= sbus_unmap_page,
 	.map_sg			= sbus_map_sg,
@@ -436,7 +437,8 @@ arch_initcall(sparc_register_ioport);
  * hwdev should be valid struct pci_dev pointer for PCI devices.
  */
 static void *pci32_alloc_coherent(struct device *dev, size_t len,
-				  dma_addr_t *pba, gfp_t gfp)
+				  dma_addr_t *pba, gfp_t gfp,
+				  struct dma_attrs *attrs)
 {
 	unsigned long len_total = PAGE_ALIGN(len);
 	void *va;
@@ -489,7 +491,7 @@ err_nopages:
  * past this call are illegal.
  */
 static void pci32_free_coherent(struct device *dev, size_t n, void *p,
-				dma_addr_t ba)
+				dma_addr_t ba, struct dma_attrs *attrs)
 {
 	struct resource *res;
 
@@ -645,8 +647,8 @@ static void pci32_sync_sg_for_device(struct device *device, struct scatterlist *
 }
 
 struct dma_map_ops pci32_dma_ops = {
-	.alloc_coherent		= pci32_alloc_coherent,
-	.free_coherent		= pci32_free_coherent,
+	.alloc			= pci32_alloc_coherent,
+	.free			= pci32_free_coherent,
 	.map_page		= pci32_map_page,
 	.unmap_page		= pci32_unmap_page,
 	.map_sg			= pci32_map_sg,
diff --git a/arch/sparc/kernel/pci_sun4v.c b/arch/sparc/kernel/pci_sun4v.c
index af5755d..7661e84 100644
--- a/arch/sparc/kernel/pci_sun4v.c
+++ b/arch/sparc/kernel/pci_sun4v.c
@@ -128,7 +128,8 @@ static inline long iommu_batch_end(void)
 }
 
 static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
-				   dma_addr_t *dma_addrp, gfp_t gfp)
+				   dma_addr_t *dma_addrp, gfp_t gfp,
+				   struct dma_attrs *attrs)
 {
 	unsigned long flags, order, first_page, npages, n;
 	struct iommu *iommu;
@@ -198,7 +199,7 @@ range_alloc_fail:
 }
 
 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
-				 dma_addr_t dvma)
+				 dma_addr_t dvma, struct dma_attrs *attrs)
 {
 	struct pci_pbm_info *pbm;
 	struct iommu *iommu;
@@ -527,8 +528,8 @@ static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
 }
 
 static struct dma_map_ops sun4v_dma_ops = {
-	.alloc_coherent			= dma_4v_alloc_coherent,
-	.free_coherent			= dma_4v_free_coherent,
+	.alloc				= dma_4v_alloc_coherent,
+	.free				= dma_4v_free_coherent,
 	.map_page			= dma_4v_map_page,
 	.unmap_page			= dma_4v_unmap_page,
 	.map_sg				= dma_4v_map_sg,
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:43 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:43 +0200
Subject: [PATCHv2 09/14] Unicore32: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-10-git-send-email-m.szyprowski@samsung.com>

From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>

Adapt core Unicore32 architecture code for dma_map_ops changes: replace
alloc/free_coherent with generic alloc/free methods.

Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
[added swiotlb_alloc/free_coherent wrappers]
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/unicore32/include/asm/dma-mapping.h |   18 ++++++++++++------
 arch/unicore32/mm/dma-swiotlb.c          |   18 ++++++++++++++++--
 2 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/arch/unicore32/include/asm/dma-mapping.h b/arch/unicore32/include/asm/dma-mapping.h
index 9258e59..366460a 100644
--- a/arch/unicore32/include/asm/dma-mapping.h
+++ b/arch/unicore32/include/asm/dma-mapping.h
@@ -82,20 +82,26 @@ static inline int dma_set_mask(struct device *dev, u64 dma_mask)
 	return 0;
 }
 
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-				       dma_addr_t *dma_handle, gfp_t flag)
+#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)
+
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+				    dma_addr_t *dma_handle, gfp_t flag,
+				    struct dma_attrs *attrs)
 {
 	struct dma_map_ops *dma_ops = get_dma_ops(dev);
 
-	return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
+	return dma_ops->alloc(dev, size, dma_handle, flag, attrs);
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *cpu_addr, dma_addr_t dma_handle)
+#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+				  void *cpu_addr, dma_addr_t dma_handle,
+				  struct dma_attrs *attrs)
 {
 	struct dma_map_ops *dma_ops = get_dma_ops(dev);
 
-	dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
+	dma_ops->free(dev, size, cpu_addr, dma_handle, attrs);
 }
 
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
diff --git a/arch/unicore32/mm/dma-swiotlb.c b/arch/unicore32/mm/dma-swiotlb.c
index bfa9fbb..4cf5f0c 100644
--- a/arch/unicore32/mm/dma-swiotlb.c
+++ b/arch/unicore32/mm/dma-swiotlb.c
@@ -17,9 +17,23 @@
 
 #include <asm/dma.h>
 
+static void *unicore_swiotlb_alloc_coherent(struct device *dev, size_t size,
+					    dma_addr_t *dma_handle, gfp_t flags,
+					    struct dma_attrs *attrs)
+{
+	return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
+}
+
+static void unicode_swiotlb_free_coherent(struct device *dev, size_t size,
+					  void *vaddr, dma_addr_t dma_addr,
+					  struct dma_attrs *attrs)
+{
+	swiotlb_free_coherent(dev, size, vaddr, dma_addr);
+}
+
 struct dma_map_ops swiotlb_dma_map_ops = {
-	.alloc_coherent = swiotlb_alloc_coherent,
-	.free_coherent = swiotlb_free_coherent,
+	.alloc = unicore_swiotlb_alloc_coherent,
+	.free = unicore_swiotlb_free_coherent,
 	.map_sg = swiotlb_map_sg_attrs,
 	.unmap_sg = swiotlb_unmap_sg_attrs,
 	.dma_supported = swiotlb_dma_supported,
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:48 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:48 +0200
Subject: [PATCHv2 14/14] common: DMA-mapping: add NON-CONSISTENT attribute
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-15-git-send-email-m.szyprowski@samsung.com>

DMA_ATTR_NON_CONSISTENT lets the platform to choose to return either
consistent or non-consistent memory as it sees fit.  By using this API,
you are guaranteeing to the platform that you have all the correct and
necessary sync points for this memory in the driver should it choose to
return non-consistent memory.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 Documentation/DMA-attributes.txt |    9 +++++++++
 include/linux/dma-attrs.h        |    1 +
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txt
index 811a5d4..9120de2 100644
--- a/Documentation/DMA-attributes.txt
+++ b/Documentation/DMA-attributes.txt
@@ -41,3 +41,12 @@ buffered to improve performance.
 Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE,
 those that do not will simply ignore the attribute and exhibit default
 behavior.
+
+DMA_ATTR_NON_CONSISTENT
+-----------------------
+
+DMA_ATTR_NON_CONSISTENT lets the platform to choose to return either
+consistent or non-consistent memory as it sees fit.  By using this API,
+you are guaranteeing to the platform that you have all the correct and
+necessary sync points for this memory in the driver should it choose to
+return non-consistent memory.
diff --git a/include/linux/dma-attrs.h b/include/linux/dma-attrs.h
index ada61e1..547ab56 100644
--- a/include/linux/dma-attrs.h
+++ b/include/linux/dma-attrs.h
@@ -14,6 +14,7 @@ enum dma_attr {
 	DMA_ATTR_WRITE_BARRIER,
 	DMA_ATTR_WEAK_ORDERING,
 	DMA_ATTR_WRITE_COMBINE,
+	DMA_ATTR_NON_CONSISTENT,
 	DMA_ATTR_MAX,
 };
 
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:46 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:46 +0200
Subject: [PATCHv2 12/14] common: dma-mapping: introduce mmap method
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-13-git-send-email-m.szyprowski@samsung.com>

Introduce new generic mmap method with attributes argument.

This method lets drivers to create a userspace mapping for a DMA buffer
in generic, architecture independent way.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 include/linux/dma-mapping.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 2fc413a..b903a20 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -15,6 +15,9 @@ struct dma_map_ops {
 	void (*free)(struct device *dev, size_t size,
 			      void *vaddr, dma_addr_t dma_handle,
 			      struct dma_attrs *attrs);
+	int (*mmap)(struct device *, struct vm_area_struct *,
+			  void *, dma_addr_t, size_t, struct dma_attrs *attrs);
+
 	dma_addr_t (*map_page)(struct device *dev, struct page *page,
 			       unsigned long offset, size_t size,
 			       enum dma_data_direction dir,
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Tue Mar 27 09:42:42 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Tue, 27 Mar 2012 15:42:42 +0200
Subject: [PATCHv2 08/14] Microblaze: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332855768-32583-9-git-send-email-m.szyprowski@samsung.com>

From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>

Adapt core Microblaze architecture code for dma_map_ops changes: replace
alloc/free_coherent with generic alloc/free methods.

Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
[fixed coding style issues]
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
---
 arch/microblaze/include/asm/dma-mapping.h |   18 ++++++++++++------
 arch/microblaze/kernel/dma.c              |   10 ++++++----
 2 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/arch/microblaze/include/asm/dma-mapping.h b/arch/microblaze/include/asm/dma-mapping.h
index 3a3e5b8..01d2282 100644
--- a/arch/microblaze/include/asm/dma-mapping.h
+++ b/arch/microblaze/include/asm/dma-mapping.h
@@ -123,28 +123,34 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
 
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-					dma_addr_t *dma_handle, gfp_t flag)
+#define dma_alloc_coherent(d, s, h, f) dma_alloc_attrs(d, s, h, f, NULL)
+
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+				    dma_addr_t *dma_handle, gfp_t flag,
+				    struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
 	void *memory;
 
 	BUG_ON(!ops);
 
-	memory = ops->alloc_coherent(dev, size, dma_handle, flag);
+	memory = ops->alloc(dev, size, dma_handle, flag, attrs);
 
 	debug_dma_alloc_coherent(dev, size, *dma_handle, memory);
 	return memory;
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-				     void *cpu_addr, dma_addr_t dma_handle)
+#define dma_free_coherent(d,s,c,h) dma_free_attrs(d, s, c, h, NULL)
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+				  void *cpu_addr, dma_addr_t dma_handle,
+				  struct dma_attrs *attrs)
 {
 	struct dma_map_ops *ops = get_dma_ops(dev);
 
 	BUG_ON(!ops);
 	debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
-	ops->free_coherent(dev, size, cpu_addr, dma_handle);
+	ops->free(dev, size, cpu_addr, dma_handle, attrs);
 }
 
 static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
diff --git a/arch/microblaze/kernel/dma.c b/arch/microblaze/kernel/dma.c
index 65a4af4..a2bfa2c 100644
--- a/arch/microblaze/kernel/dma.c
+++ b/arch/microblaze/kernel/dma.c
@@ -33,7 +33,8 @@ static unsigned long get_dma_direct_offset(struct device *dev)
 #define NOT_COHERENT_CACHE
 
 static void *dma_direct_alloc_coherent(struct device *dev, size_t size,
-				dma_addr_t *dma_handle, gfp_t flag)
+				       dma_addr_t *dma_handle, gfp_t flag,
+				       struct dma_attrs *attrs)
 {
 #ifdef NOT_COHERENT_CACHE
 	return consistent_alloc(flag, size, dma_handle);
@@ -57,7 +58,8 @@ static void *dma_direct_alloc_coherent(struct device *dev, size_t size,
 }
 
 static void dma_direct_free_coherent(struct device *dev, size_t size,
-			      void *vaddr, dma_addr_t dma_handle)
+				     void *vaddr, dma_addr_t dma_handle,
+				     struct dma_attrs *attrs)
 {
 #ifdef NOT_COHERENT_CACHE
 	consistent_free(size, vaddr);
@@ -176,8 +178,8 @@ dma_direct_sync_sg_for_device(struct device *dev,
 }
 
 struct dma_map_ops dma_direct_ops = {
-	.alloc_coherent	= dma_direct_alloc_coherent,
-	.free_coherent	= dma_direct_free_coherent,
+	.alloc		= dma_direct_alloc_coherent,
+	.free		= dma_direct_free_coherent,
 	.map_sg		= dma_direct_map_sg,
 	.unmap_sg	= dma_direct_unmap_sg,
 	.dma_supported	= dma_direct_dma_supported,
-- 
1.7.1.569.g6f426



From dave.martin at linaro.org  Tue Mar 27 09:54:01 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Tue, 27 Mar 2012 14:54:01 +0100
Subject: [PATCH v2 0/4] ARM: opcodes: Facilitate custom opcode injection
Message-ID: <1332856445-7007-1-git-send-email-dave.martin@linaro.org>

Changes since v1:

 * This update contains minor typo fixes and extra clarification
   in the commit messages.  There are no functional changes.

Thanks to Nico for his review.


Original cover letter:

Since my "uniform assembler" series had some problems and did not
meet with widespread agreement, this can't be used as a basis for a
mechanism to safely inject custom instruction opcodes (which was my
immediate reason for writing those patchse).

This series follows a more conventional approach to achieve the
goal for safe opcode injection across all kernel endianness and
instruction set configurations.

I have made best efforts to verify that these patches do the right
thing for big-endian configurations, but review/testing from people
who are actively working with big-endian targets would be
appreciated.  There's no code in the kernel using these macros yet,
but you can experiment with the __HVC() macro added by the final
patch.  If this disassembles correctly in vmlinux (see below), then
the macros should be safe for your configuration.


Note that for BE8 targets, you _will_ get weird-looking instruction
data in your .o files:  because the ".inst" family of assembler
directives is relatively new I use data directives instead.  This
means that the data for those directives has to be pre-swapped by
the opcode injection macros, whereas _instruction_ data should get
byteswapped by the linker in the final link (with ld --be8).  Using
with older assembler versions.

To check correctness, you should therefore review the final linker
output (vmlinux) if you want to be certain what the final
instruction stream looks like.  You may need to strip data mapping
symbols (strip -N'$d') from vmlinux in order for the injected
instructions to be disassembled properly -- note that this has no
effect on the run-time meaning of the image.

For BE32 the situation is simpler again, because like LE, BE32 uses
the same endianness for data and instructions.


Dave Martin (4):
  ARM: opcodes: Don't define the thumb32 byteswapping macros for BE32
  ARM: opcodes: Make opcode byteswapping macros assembly-compatible
  ARM: opcodes: Add helpers for emitting custom opcodes
  ARM: opcodes: Opcode definitions for the Virtualization Extensions

 arch/arm/include/asm/opcodes-virt.h |   29 ++++++
 arch/arm/include/asm/opcodes.h      |  181 ++++++++++++++++++++++++++++++++---
 2 files changed, 195 insertions(+), 15 deletions(-)
 create mode 100644 arch/arm/include/asm/opcodes-virt.h

-- 
1.7.4.1



From dave.martin at linaro.org  Tue Mar 27 09:54:02 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Tue, 27 Mar 2012 14:54:02 +0100
Subject: [PATCH v2 1/4] ARM: opcodes: Don't define the thumb32 byteswapping
 macros for BE32
In-Reply-To: <1332856445-7007-1-git-send-email-dave.martin@linaro.org>
References: <1332856445-7007-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1332856445-7007-2-git-send-email-dave.martin@linaro.org>

The existing __mem_to_opcode_thumb32() is incorrect for BE32
platforms.  However, these don't support Thumb-2 kernels, so this
option is not so relevant for those platforms anyway.

This operation is complicated by the lack of unaligned memory
access support prior to ARMv6.

Rather than provide a "working" macro which will probably won't get
used (or worse, will get misused), this patch removes the macro for
BE32 kernels.  People manipulating Thumb opcodes prior to ARMv6
should almost certainly be splitting these operations into
halfwords anyway, using __opcode_thumb32_{first,second,compose}()
and the 16-bit opcode transformations.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Acked-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/opcodes.h |   15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 19c48de..6bf54f9 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -49,18 +49,31 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 #include <linux/swab.h>
 
 #ifdef CONFIG_CPU_ENDIAN_BE8
+
 #define __opcode_to_mem_arm(x) swab32(x)
 #define __opcode_to_mem_thumb16(x) swab16(x)
 #define __opcode_to_mem_thumb32(x) swahb32(x)
-#else
+
+#else /* ! CONFIG_CPU_ENDIAN_BE8 */
+
 #define __opcode_to_mem_arm(x) ((u32)(x))
 #define __opcode_to_mem_thumb16(x) ((u16)(x))
+#ifndef CONFIG_CPU_ENDIAN_BE32
+/*
+ * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
+ * work in all cases, due to alignment constraints.  For now, a correct
+ * version is not provided for BE32.
+ */
 #define __opcode_to_mem_thumb32(x) swahw32(x)
 #endif
 
+#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
+
 #define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
 #define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
 #define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
+#endif
 
 /* Operations specific to Thumb opcodes */
 
-- 
1.7.4.1



From dave.martin at linaro.org  Tue Mar 27 09:54:03 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Tue, 27 Mar 2012 14:54:03 +0100
Subject: [PATCH v2 2/4] ARM: opcodes: Make opcode byteswapping macros
 assembly-compatible
In-Reply-To: <1332856445-7007-1-git-send-email-dave.martin@linaro.org>
References: <1332856445-7007-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1332856445-7007-3-git-send-email-dave.martin@linaro.org>

Most of the existing macros don't work with assembler, due to the
use of type casts and C functions from <linux/swab.h>.

This patch abstracts out those operations and provides simple
explicit versions for use in assembly code.

__opcode_is_thumb32() and __opcode_is_thumb16() are also converted
to do bitmask-based testing to avoid confusion if these are used in
assembly code (the assembler typically treats all arithmetic values
as signed).

These changes avoid the need for the compiler to pre-evaluate
constant expressions used to generate opcodes.  By ensuring that
the forms of these expressions can be evaluated directly by the
assembler, we can just stringify the expressions directly into the
asm during the preprocessing pass.  The alternative approach
(passing the evaluated expression via an inline asm "i" constraint)
gets painful because the contents of the asm and the constraints
must be kept in sync.  This makes the resulting macros awkward to
use.

Retaining the C forms of the macros allows more efficient code to
be generated when opcodes are generated programmatically at run-
time, but there is no way to embed run-time-generated opcodes in
asm() blocks.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Acked-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/opcodes.h |   97 +++++++++++++++++++++++++++++++++------
 1 files changed, 82 insertions(+), 15 deletions(-)

diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index 6bf54f9..f57e417 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -19,6 +19,33 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 
 
 /*
+ * Assembler opcode byteswap helpers.
+ * These are only intended for use by this header: don't use them directly,
+ * because they will be suboptimal in most cases.
+ */
+#define ___asm_opcode_swab32(x) (	\
+	  (((x) << 24) & 0xFF000000)	\
+	| (((x) <<  8) & 0x00FF0000)	\
+	| (((x) >>  8) & 0x0000FF00)	\
+	| (((x) >> 24) & 0x000000FF)	\
+)
+#define ___asm_opcode_swab16(x) (	\
+	  (((x) << 8) & 0xFF00)		\
+	| (((x) >> 8) & 0x00FF)		\
+)
+#define ___asm_opcode_swahb32(x) (	\
+	  (((x) << 8) & 0xFF00FF00)	\
+	| (((x) >> 8) & 0x00FF00FF)	\
+)
+#define ___asm_opcode_swahw32(x) (	\
+	  (((x) << 16) & 0xFFFF0000)	\
+	| (((x) >> 16) & 0x0000FFFF)	\
+)
+#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
+#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
+
+
+/*
  * Opcode byteswap helpers
  *
  * These macros help with converting instructions between a canonical integer
@@ -41,30 +68,58 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
  * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
  * represent any valid Thumb-2 instruction.  For this range,
  * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
+ *
+ * The ___asm variants are intended only for use by this header, in situations
+ * involving inline assembler.  For .S files, the normal __opcode_*() macros
+ * should do the right thing.
  */
+#ifdef __ASSEMBLY__
 
-#ifndef __ASSEMBLY__
+#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
+#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
+#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
+#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
+#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
+#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
+
+#else /* ! __ASSEMBLY__ */
 
 #include <linux/types.h>
 #include <linux/swab.h>
 
+#define ___opcode_swab32(x) swab32(x)
+#define ___opcode_swab16(x) swab16(x)
+#define ___opcode_swahb32(x) swahb32(x)
+#define ___opcode_swahw32(x) swahw32(x)
+#define ___opcode_identity32(x) ((u32)(x))
+#define ___opcode_identity16(x) ((u16)(x))
+
+#endif /* ! __ASSEMBLY__ */
+
+
 #ifdef CONFIG_CPU_ENDIAN_BE8
 
-#define __opcode_to_mem_arm(x) swab32(x)
-#define __opcode_to_mem_thumb16(x) swab16(x)
-#define __opcode_to_mem_thumb32(x) swahb32(x)
+#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
+#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
 
 #else /* ! CONFIG_CPU_ENDIAN_BE8 */
 
-#define __opcode_to_mem_arm(x) ((u32)(x))
-#define __opcode_to_mem_thumb16(x) ((u16)(x))
+#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
 #ifndef CONFIG_CPU_ENDIAN_BE32
 /*
  * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
  * work in all cases, due to alignment constraints.  For now, a correct
  * version is not provided for BE32.
  */
-#define __opcode_to_mem_thumb32(x) swahw32(x)
+#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
 #endif
 
 #endif /* ! CONFIG_CPU_ENDIAN_BE8 */
@@ -78,15 +133,27 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 /* Operations specific to Thumb opcodes */
 
 /* Instruction size checks: */
-#define __opcode_is_thumb32(x) ((u32)(x) >= 0xE8000000UL)
-#define __opcode_is_thumb16(x) ((u32)(x) < 0xE800UL)
+#define __opcode_is_thumb32(x) (		\
+	   ((x) & 0xF8000000) == 0xE8000000	\
+	|| ((x) & 0xF0000000) == 0xF0000000	\
+)
+#define __opcode_is_thumb16(x) (					\
+	   ((x) & 0xFFFF0000) == 0					\
+	&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)	\
+)
 
 /* Operations to construct or split 32-bit Thumb instructions: */
-#define __opcode_thumb32_first(x) ((u16)((x) >> 16))
-#define __opcode_thumb32_second(x) ((u16)(x))
-#define __opcode_thumb32_compose(first, second) \
-	(((u32)(u16)(first) << 16) | (u32)(u16)(second))
-
-#endif /* __ASSEMBLY__ */
+#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
+#define __opcode_thumb32_second(x) (___opcode_identity16(x))
+#define __opcode_thumb32_compose(first, second) (			\
+	  (___opcode_identity32(___opcode_identity16(first)) << 16)	\
+	| ___opcode_identity32(___opcode_identity16(second))		\
+)
+#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
+#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
+#define ___asm_opcode_thumb32_compose(first, second) (			    \
+	  (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
+	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
+)
 
 #endif /* __ASM_ARM_OPCODES_H */
-- 
1.7.4.1



From dave.martin at linaro.org  Tue Mar 27 09:54:04 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Tue, 27 Mar 2012 14:54:04 +0100
Subject: [PATCH v2 3/4] ARM: opcodes: Add helpers for emitting custom opcodes
In-Reply-To: <1332856445-7007-1-git-send-email-dave.martin@linaro.org>
References: <1332856445-7007-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1332856445-7007-4-git-send-email-dave.martin@linaro.org>

This patch adds some __inst_() macros for injecting custom opcodes
in assembler (both inline and in .S files).  They should make it
easier and cleaner to get things right in little-/big-
endian/ARM/Thumb-2 kernels without a lot of #ifdefs.

This pure-preprocessor approach is preferred over the alternative
method of wedging extra assembler directives into the assembler
input using top-level asm() blocks, since there is no way to
guarantee that the compiler won't reorder those with respect to
each other or with respect to non-toplevel asm() blocks, unless
-fno-toplevel-reorder is passed (which is in itself somewhat
undesirable because it defeats some potential optimisations).

Currently <asm/unified.h> _does_ silently rely on the compiler not
reordering at the top level, but it seems better to avoid adding
extra code which depends on this if the same result can be achieved
in another way.

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Acked-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/opcodes.h |   69 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 69 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index f57e417..f7937e1 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -156,4 +156,73 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
 	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
 )
 
+/*
+ * Opcode injection helpers
+ *
+ * In rare cases it is necessary to assemble an opcode which the
+ * assembler does not support directly, or which would normally be
+ * rejected because of the CFLAGS or AFLAGS used to build the affected
+ * file.
+ *
+ * Before using these macros, consider carefully whether it is feasible
+ * instead to change the build flags for your file, or whether it really
+ * makes sense to support old assembler versions when building that
+ * particular kernel feature.
+ *
+ * The macros defined here should only be used where there is no viable
+ * alternative.
+ *
+ *
+ * __inst_arm(x): emit the specified ARM opcode
+ * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
+ * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
+ *
+ * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
+ *	16-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
+ *	32-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ *
+ * Note that using these macros directly is poor practice.  Instead, you
+ * should use them to define human-readable wrapper macros to encode the
+ * instructions that you care about.  In code which might run on ARMv7 or
+ * above, you can usually use the __inst_arm_thumb{16,32} macros to
+ * specify the ARM and Thumb alternatives at the same time.  This ensures
+ * that the correct opcode gets emitted depending on the instruction set
+ * used for the kernel build.
+ */
+#include <linux/stringify.h>
+
+#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
+#define __inst_thumb32(x) ___inst_thumb32(				\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),	\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))	\
+)
+#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
+
+#ifdef CONFIG_THUMB2_KERNEL
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
+	__inst_thumb16(thumb_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
+	__inst_thumb32(thumb_opcode)
+#else
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#endif
+
+/* Helpers for the helpers.  Don't use these directly. */
+#ifdef __ASSEMBLY__
+#define ___inst_arm(x) .long x
+#define ___inst_thumb16(x) .short x
+#define ___inst_thumb32(first, second) .short first, second
+#else
+#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
+#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
+#define ___inst_thumb32(first, second) \
+	".short " __stringify(first) ", " __stringify(second) "\n\t"
+#endif
+
 #endif /* __ASM_ARM_OPCODES_H */
-- 
1.7.4.1



From dave.martin at linaro.org  Tue Mar 27 09:54:05 2012
From: dave.martin at linaro.org (Dave Martin)
Date: Tue, 27 Mar 2012 14:54:05 +0100
Subject: [PATCH v2 4/4] ARM: opcodes: Opcode definitions for the
 Virtualization Extensions
In-Reply-To: <1332856445-7007-1-git-send-email-dave.martin@linaro.org>
References: <1332856445-7007-1-git-send-email-dave.martin@linaro.org>
Message-ID: <1332856445-7007-5-git-send-email-dave.martin@linaro.org>

For now, this patch just adds a definition for the HVC instruction.
More can be added here later, as needed.

Now that we have a real example of how to use the opcode injection
macros properly, this patch also adds a cross-reference from the
explanation in opcodes.h (since without an example, figuring out
how to use the macros is not that easy).

Signed-off-by: Dave Martin <dave.martin at linaro.org>
Acked-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/include/asm/opcodes-virt.h |   29 +++++++++++++++++++++++++++++
 arch/arm/include/asm/opcodes.h      |    2 ++
 2 files changed, 31 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/opcodes-virt.h

diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
new file mode 100644
index 0000000..b85665a
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-virt.h
@@ -0,0 +1,29 @@
+/*
+ * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
+ * Copyright (C) 2012  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARM_OPCODES_VIRT_H
+#define __ASM_ARM_OPCODES_VIRT_H
+
+#include <asm/opcodes.h>
+
+#define __HVC(imm16) __inst_arm_thumb32(				\
+	0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),	\
+	0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)	\
+)
+
+#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
index f7937e1..74e211a 100644
--- a/arch/arm/include/asm/opcodes.h
+++ b/arch/arm/include/asm/opcodes.h
@@ -193,6 +193,8 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
  * specify the ARM and Thumb alternatives at the same time.  This ensures
  * that the correct opcode gets emitted depending on the instruction set
  * used for the kernel build.
+ *
+ * Look at opcodes-virt.h for an example of how to use these macros.
  */
 #include <linux/stringify.h>
 
-- 
1.7.4.1



From notasas at gmail.com  Tue Mar 27 09:57:40 2012
From: notasas at gmail.com (Grazvydas Ignotas)
Date: Tue, 27 Mar 2012 16:57:40 +0300
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators for
 v3.4
In-Reply-To: <87pqchv1pc.fsf@ti.com>
References: <877gywjhht.fsf@ti.com> <20120308021843.GQ12083@atomide.com>
 <87399jc6cj.fsf@ti.com> <20120309003217.GB12083@atomide.com>
 <20120309114731.GA3273@opensource.wolfsonmicro.com>
 <87zkbp4wtj.fsf@ti.com>
 <20120311204232.GC3171@opensource.wolfsonmicro.com>
 <87399dzq5e.fsf@ti.com>
 <20120312173215.GL3110@opensource.wolfsonmicro.com>
 <87pqchv1pc.fsf@ti.com>
Message-ID: <CANOLnOMfsdGn-B0zftcV-zh+tSCGgmf0g1BsrFB0+Kh-HnNq0g@mail.gmail.com>

On Tue, Mar 13, 2012 at 1:28 AM, Kevin Hilman <khilman at ti.com> wrote:
> Tony, updated pull request below. ?This includes all the TWL depencies
> merged from the 'topic/twl' tag in Mark's tree.
>

Has this been lost now? It seems regulator parts got merged, but
voltage parts are missing from Arnd's pull requests and are not
showing up in linux-next.
Was looking forward for voltage control in 3.4 to achieve higher clock
rates on our aging OMAP3 hardware.

>
> The following changes since commit b01543dfe67bb1d191998e90d20534dc354de059:
>
> ?Linux 3.3-rc4 (2012-02-18 15:53:33 -0800)
>
> are available in the git repository at:
>
> ?git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git for_3.4/pm/smps-regulator
>
> for you to fetch changes up to 39358f2b57f37fe079eff4159307c844a0bfb176:
>
> ?Merge branch 'pm-wip/smps-regulator' into for_3.4/pm/smps-regulator (2012-03-12 15:36:45 -0700)
>
> ----------------------------------------------------------------
>
> Kevin Hilman (3):
> ? ? ?ARM: OMAP2+: voltage: ensure voltage used is exact voltage from OPP table
> ? ? ?Merge tag 'topic/twl' into for_3.4/pm/smps-regulator
> ? ? ?Merge branch 'pm-wip/smps-regulator' into for_3.4/pm/smps-regulator
>
> Laxman Dewangan (1):
> ? ? ?regulator: twl6030: Fix voltage selection logic
>
> Peter Ujfalusi (2):
> ? ? ?regulator: twl-regulator: Add fixed LDO for V1V8, V2V1 supply
> ? ? ?mfd: twl-core: regulator configuration for twl6030 V1V8, V2V1 SMPS
>
> Rajendra Nayak (1):
> ? ? ?regulator: twl: adapt twl-regulator driver to dt
>
> Tero Kristo (6):
> ? ? ?arm: omap3: voltage: fix channel configuration
> ? ? ?arm: omap3: add common twl configurations for vdd1 and vdd2
> ? ? ?arm: omap3: twl: add external controllers for core voltage regulators
> ? ? ?arm: omap4: add common twl configurations for vdd1, vdd2 and vdd3
> ? ? ?regulator: twl4030: add support for external voltage get/set
> ? ? ?regulator: twl6030: add support for vdd1, vdd2 and vdd3 regulators
>
> ?.../bindings/regulator/twl-regulator.txt ? ? ? ? ? | ? 68 ++++
> ?arch/arm/mach-omap2/twl-common.c ? ? ? ? ? ? ? ? ? | ?147 +++++++++
> ?arch/arm/mach-omap2/vc3xxx_data.c ? ? ? ? ? ? ? ? ?| ? ?1 +
> ?arch/arm/mach-omap2/voltage.c ? ? ? ? ? ? ? ? ? ? ?| ? 21 +-
> ?drivers/mfd/twl-core.c ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? 41 ++-
> ?drivers/regulator/twl-regulator.c ? ? ? ? ? ? ? ? ?| ?327 +++++++++++++++-----
> ?include/linux/i2c/twl.h ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 14 +-
> ?7 files changed, 532 insertions(+), 87 deletions(-)
> ?create mode 100644 Documentation/devicetree/bindings/regulator/twl-regulator.txt
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html


--
Gra?vydas


From arnd at arndb.de  Tue Mar 27 09:59:16 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 27 Mar 2012 13:59:16 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <CAOh2x==7gNt2Jb3-EHz9-R1pTy6zL93FmUmTBMdpYUnW3F=9Uw@mail.gmail.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203271159.35306.arnd@arndb.de>
 <CAOh2x==7gNt2Jb3-EHz9-R1pTy6zL93FmUmTBMdpYUnW3F=9Uw@mail.gmail.com>
Message-ID: <201203271359.16553.arnd@arndb.de>

On Tuesday 27 March 2012, viresh kumar wrote:
> On Mar 27, 2012 7:07 PM, "Arnd Bergmann" <arnd at arndb.de> wrote:
> >
> > On Tuesday 27 March 2012, Viresh Kumar wrote:
> > > On 3/27/2012 4:45 PM, Arnd Bergmann wrote:
> > > > On Tuesday 27 March 2012, Viresh Kumar wrote:
> > > > The normal way is to turn around the logic so you don't have to include this test
> > > > at all. Just have one soc-specific init_machine and map_io function, that calls
> > > > both soc-specific and shared soc functions, e.g.
> > >
> > > But with that, i need multiple DT_MACHINE_START(). Isn't it?
> > > Is this advisable?
> >
> > Having one DT_MACHINE_START per soc is ok if it helps you. Of course if you
> > have multiple ones that are basically identical, it's simpler to just
> > combine them.
> 
> That's what i have done in V1. And then only i came to
> The first problem i mentioned.

Right. I mean you can feel free to do whichever works best for you. If it's easy
to combine the DT_MACHINE_START sections, then do, otherwise don't.

> > Obviously that only works when you initialize the clocks from init_early()
> > instead of from map_io(), but I think that would be the cleanest choice
> > if you want to have single function with run-time dependencies.
> 
> But then why not use machine_init() for doing this too.

That would be even better. I think we should generally try do initialization
as late as possible, ideally from initcalls. The init_early() function should
only be used for code that absolutely has to be run from setup_arch() and
no later, while the map_io() function should ideally only be used to set up
the static mappings and nothing else.

	Arnd


From philippe.retornaz at epfl.ch  Tue Mar 27 11:06:36 2012
From: philippe.retornaz at epfl.ch (Philippe =?ISO-8859-1?Q?R=E9tornaz?=)
Date: Tue, 27 Mar 2012 17:06:36 +0200
Subject: [PATCH v5 2/8] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <1331888204-27058-3-git-send-email-shawn.guo@linaro.org>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-3-git-send-email-shawn.guo@linaro.org>
Message-ID: <2976261.6mYHfHvpym@laptop>

Le vendredi 16 mars 2012 16:56:38 Shawn Guo a ?crit :
> Freescale PowerPC and ARM/IMX families share the same SSI IP block.
> The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
> code sharing and consolidation can happen.
> 
> This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
> in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
> IMX platform.
> 
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

This patch has been merged ? If yes in which tree is it available ? 

Thanks,

Philippe




From jon-hunter at ti.com  Tue Mar 27 11:31:56 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Tue, 27 Mar 2012 10:31:56 -0500
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A9317BD6E2@DBDE01.ent.ti.com>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
 <4F6D0569.6080203@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A9317BB895@DBDE01.ent.ti.com>
 <4F70AA82.3000204@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A9317BD6E2@DBDE01.ent.ti.com>
Message-ID: <4F71DD6C.5010305@ti.com>

Hi Afzal,

On 3/27/2012 0:12, Mohammed, Afzal wrote:
> Hi Jon,
>
> On Mon, Mar 26, 2012 at 23:12:26, Hunter, Jon wrote:
>> Also, I don't see where the gpmc_child->res and gpmc_child->num_res are
>> actually used. Are these needed?
>
> These are for the peripheral resources not in control of GPMC, like
> gpio irq. These are copied in gpmc_create_child.

Right, I see they are copied during gpmc_create_child. However, I don't 
see where they are initialised before that. The function 
gpmc_setup_child is only initialising gpmc_res and gpmc_num_res and not 
res and num_res. So I still don't see who is initialising these before 
they are copied.

>>> Gpmc_device_data is dedicated to each CS, gpmc_pdata is required
>>> at least to inform driver about clock rate.
>>
>> Ok, understood! So the struct gpmc_device_pdata only has a single
>> chip-select entry and so looking at the code you will have multiple
>> instances of this structure of a gpmc device that uses more than one
>> chip-select. Any reason you did it this way and not have a single pdata
>> struct for each device defining all chip-selects it uses?
>
> When coding started, multiple CS for a peripheral was not taken into
> consideration, later handling multiple CS was incorporated making it
> this way. But your suggestion seems better to me, will see if code can
> modified accordingly in later patch series (v2 already sent)

Ok great. I will wait for your v3.

>>
>>> Generally, as the change involved moving a lot of code, seems more reviews
>>> are on those than the actual changes than what I intended to get reviewed,
>>> next patch series will be modified not to move existing code, hence some
>>> of your suggested changes may not be present in it, probably those to be
>>> done as another cleanup patch.
>>
>> Yes I understand. However, it is a good opportunity to clean some of
>> this up even if it is existing code :-)
>
> Ok

I see you did not incorporate any clean-up in v2. Do you want me to send 
you some patches to include?

Cheers
Jon


From cjb at laptop.org  Tue Mar 27 11:50:24 2012
From: cjb at laptop.org (Chris Ball)
Date: Tue, 27 Mar 2012 11:50:24 -0400
Subject: [PATCH v3 0/6] mmc: sdhci-s3c: Rework platform data and add
 device tree support
In-Reply-To: <m2vcn0496y.fsf@bob.laptop.org> (Chris Ball's message of "Tue, 21
 Feb 2012 08:17:41 -0500")
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>
 <003401cce730$baf979a0$30ec6ce0$%kim@samsung.com>
 <m2aa4pkq5g.fsf@bob.laptop.org> <4F3CFEED.6060206@samsung.com>
 <m239abgc32.fsf@bob.laptop.org>
 <00b901ccf08d$2fc18b50$8f44a1f0$%kim@samsung.com>
 <m2vcn0496y.fsf@bob.laptop.org>
Message-ID: <87k426vy9r.fsf@laptop.org>

Hi Kukjin,

On Tue, Feb 21 2012, Chris Ball wrote:
> On Tue, Feb 21 2012, Kukjin Kim wrote:
>> I created topic branch for this we talked. You can pull that following:
>>   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>> v3.4-for-cjb
>>
>> If any problems, please kindly let me know.
>
> Pushed to mmc-next, thanks.  (I'm expecting that you'll do the merge
> to Linus.)

I was expecting you to merge these patches, but they aren't in the
arm-soc tree and haven't been sent to Linus, and we're in the last few
days of the merge window.

As a result I'm dropping this tree -- and all of the patches that I
have on top of it -- from mmc-next so that I can get a pull request
out.  This means that I'm dropping:

mmc: sdhci-s3c: Add device tree support
mmc: sdhci-s3c: Keep a copy of platform data and use it
mmc: sdhci-s3c: derive transfer width host capability from max_width in 
ARM: SAMSUNG: remove all uses of clk_type member in sdhci platform data
ARM: EXYNOS: use 'exynos4-sdhci' as device name for sdhci controllers
mmc: sdhci-s3c: Remove usage of clk_type member in platform data

.. which I was expecting you to merge, and also:

mmc: sdhci-s3c: fix broken compilation for non-Exynos SoCs
mmc: sdhci-s3c: Enable runtime power management
mmc: sdhci-s3c: Use CONFIG_PM_SLEEP to ifdef system suspend
mmc: sdhci-s3c: use devm_ functions

.. which were merged on top of the above patches.

We'll have to try again with 3.5 for the new features, and post-rc1 for
the fixes.  Please let me know what happened with this merge.  Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From grinberg at compulab.co.il  Tue Mar 27 11:53:52 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Tue, 27 Mar 2012 17:53:52 +0200
Subject: [PATCH 05/12] Add dummy smsc911x regulators to cm-t35.
In-Reply-To: <1332494504-10251-6-git-send-email-Russ.Dill@ti.com>
References: <1332494504-10251-1-git-send-email-Russ.Dill@ti.com>
 <1332494504-10251-6-git-send-email-Russ.Dill@ti.com>
Message-ID: <4F71E290.2050403@compulab.co.il>

Hi Russ,

This patch works, but can we, please use the attached patch instead?

Thanks

On 03/23/12 11:21, Russ Dill wrote:
> Signed-off-by: Russ Dill <russ.dill at ti.com>
> ---
>  arch/arm/mach-omap2/board-cm-t35.c |    9 +++++++++
>  1 files changed, 9 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
> index 41b0a2f..289ded3 100644
> --- a/arch/arm/mach-omap2/board-cm-t35.c
> +++ b/arch/arm/mach-omap2/board-cm-t35.c
> @@ -26,6 +26,7 @@
>  
>  #include <linux/i2c/at24.h>
>  #include <linux/i2c/twl.h>
> +#include <linux/regulator/fixed.h>
>  #include <linux/regulator/machine.h>
>  #include <linux/mmc/host.h>
>  
> @@ -630,10 +631,18 @@ static inline void cm_t3730_init_mux(void) {}
>  static struct omap_board_config_kernel cm_t35_config[] __initdata = {
>  };
>  
> +static struct regulator_consumer_supply dummy_supplies[] = {
> +	REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
> +	REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
> +	REGULATOR_SUPPLY("vddvario", "smsc911x.1"),
> +	REGULATOR_SUPPLY("vdd33a", "smsc911x.1"),
> +};
> +
>  static void __init cm_t3x_common_init(void)
>  {
>  	omap_board_config = cm_t35_config;
>  	omap_board_config_size = ARRAY_SIZE(cm_t35_config);
> +	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
>  	omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
>  	omap_serial_init();
>  	omap_sdrc_init(mt46h32m32lf6_sdrc_params,

-- 
Regards,
Igor.
-------------- next part --------------
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From mattst88 at gmail.com  Tue Mar 27 11:56:43 2012
From: mattst88 at gmail.com (Matt Turner)
Date: Tue, 27 Mar 2012 11:56:43 -0400
Subject: [PATCHv2 06/14] Alpha: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-7-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
 <1332855768-32583-7-git-send-email-m.szyprowski@samsung.com>
Message-ID: <CAEdQ38H6xJsHDZh2LJA4NZOQJ0AEtYLKK2i7w=+98TXCCRxEQw@mail.gmail.com>

On Tue, Mar 27, 2012 at 9:42 AM, Marek Szyprowski
<m.szyprowski at samsung.com> wrote:
> From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
>
> Adapt core Alpha architecture code for dma_map_ops changes: replace
> alloc/free_coherent with generic alloc/free methods.
>
> Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
> Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Reviewed-by: Arnd Bergmann <arnd at arndb.de>
> ---
> ?arch/alpha/include/asm/dma-mapping.h | ? 18 ++++++++++++------
> ?arch/alpha/kernel/pci-noop.c ? ? ? ? | ? 10 ++++++----
> ?arch/alpha/kernel/pci_iommu.c ? ? ? ?| ? 10 ++++++----
> ?3 files changed, 24 insertions(+), 14 deletions(-)
>
> diff --git a/arch/alpha/include/asm/dma-mapping.h b/arch/alpha/include/asm/dma-mapping.h
> index 4567aca..dfa32f0 100644
> --- a/arch/alpha/include/asm/dma-mapping.h
> +++ b/arch/alpha/include/asm/dma-mapping.h
> @@ -12,16 +12,22 @@ static inline struct dma_map_ops *get_dma_ops(struct device *dev)
>
> ?#include <asm-generic/dma-mapping-common.h>
>
> -static inline void *dma_alloc_coherent(struct device *dev, size_t size,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?dma_addr_t *dma_handle, gfp_t gfp)
> +#define dma_alloc_coherent(d,s,h,f) ? ?dma_alloc_attrs(d,s,h,f,NULL)
> +
> +static inline void *dma_alloc_attrs(struct device *dev, size_t size,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_addr_t *dma_handle, gfp_t gfp,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct dma_attrs *attrs)
> ?{
> - ? ? ? return get_dma_ops(dev)->alloc_coherent(dev, size, dma_handle, gfp);
> + ? ? ? return get_dma_ops(dev)->alloc(dev, size, dma_handle, gfp, attrs);
> ?}
>
> -static inline void dma_free_coherent(struct device *dev, size_t size,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?void *vaddr, dma_addr_t dma_handle)
> +#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
> +
> +static inline void dma_free_attrs(struct device *dev, size_t size,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? void *vaddr, dma_addr_t dma_handle,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct dma_attrs *attrs)
> ?{
> - ? ? ? get_dma_ops(dev)->free_coherent(dev, size, vaddr, dma_handle);
> + ? ? ? get_dma_ops(dev)->free(dev, size, vaddr, dma_handle, attrs);
> ?}
>
> ?static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
> diff --git a/arch/alpha/kernel/pci-noop.c b/arch/alpha/kernel/pci-noop.c
> index 04eea48..df24b76 100644
> --- a/arch/alpha/kernel/pci-noop.c
> +++ b/arch/alpha/kernel/pci-noop.c
> @@ -108,7 +108,8 @@ sys_pciconfig_write(unsigned long bus, unsigned long dfn,
> ?}
>
> ?static void *alpha_noop_alloc_coherent(struct device *dev, size_t size,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?dma_addr_t *dma_handle, gfp_t gfp)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?dma_addr_t *dma_handle, gfp_t gfp,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct dma_attrs *attrs)
> ?{
> ? ? ? ?void *ret;
>
> @@ -123,7 +124,8 @@ static void *alpha_noop_alloc_coherent(struct device *dev, size_t size,
> ?}
>
> ?static void alpha_noop_free_coherent(struct device *dev, size_t size,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?void *cpu_addr, dma_addr_t dma_addr)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?void *cpu_addr, dma_addr_t dma_addr,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct dma_attrs *attrs)
> ?{
> ? ? ? ?free_pages((unsigned long)cpu_addr, get_order(size));
> ?}
> @@ -174,8 +176,8 @@ static int alpha_noop_set_mask(struct device *dev, u64 mask)
> ?}
>
> ?struct dma_map_ops alpha_noop_ops = {
> - ? ? ? .alloc_coherent ? ? ? ? = alpha_noop_alloc_coherent,
> - ? ? ? .free_coherent ? ? ? ? ?= alpha_noop_free_coherent,
> + ? ? ? .alloc ? ? ? ? ? ? ? ? ?= alpha_noop_alloc_coherent,
> + ? ? ? .free ? ? ? ? ? ? ? ? ? = alpha_noop_free_coherent,
> ? ? ? ?.map_page ? ? ? ? ? ? ? = alpha_noop_map_page,
> ? ? ? ?.map_sg ? ? ? ? ? ? ? ? = alpha_noop_map_sg,
> ? ? ? ?.mapping_error ? ? ? ? ?= alpha_noop_mapping_error,
> diff --git a/arch/alpha/kernel/pci_iommu.c b/arch/alpha/kernel/pci_iommu.c
> index 4361080..cd63479 100644
> --- a/arch/alpha/kernel/pci_iommu.c
> +++ b/arch/alpha/kernel/pci_iommu.c
> @@ -434,7 +434,8 @@ static void alpha_pci_unmap_page(struct device *dev, dma_addr_t dma_addr,
> ? ?else DMA_ADDRP is undefined. ?*/
>
> ?static void *alpha_pci_alloc_coherent(struct device *dev, size_t size,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_addr_t *dma_addrp, gfp_t gfp)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dma_addr_t *dma_addrp, gfp_t gfp,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct dma_attrs *attrs)
> ?{
> ? ? ? ?struct pci_dev *pdev = alpha_gendev_to_pci(dev);
> ? ? ? ?void *cpu_addr;
> @@ -478,7 +479,8 @@ try_again:
> ? ?DMA_ADDR past this call are illegal. ?*/
>
> ?static void alpha_pci_free_coherent(struct device *dev, size_t size,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? void *cpu_addr, dma_addr_t dma_addr)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? void *cpu_addr, dma_addr_t dma_addr,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct dma_attrs *attrs)
> ?{
> ? ? ? ?struct pci_dev *pdev = alpha_gendev_to_pci(dev);
> ? ? ? ?pci_unmap_single(pdev, dma_addr, size, PCI_DMA_BIDIRECTIONAL);
> @@ -952,8 +954,8 @@ static int alpha_pci_set_mask(struct device *dev, u64 mask)
> ?}
>
> ?struct dma_map_ops alpha_pci_ops = {
> - ? ? ? .alloc_coherent ? ? ? ? = alpha_pci_alloc_coherent,
> - ? ? ? .free_coherent ? ? ? ? ?= alpha_pci_free_coherent,
> + ? ? ? .alloc ? ? ? ? ? ? ? ? ?= alpha_pci_alloc_coherent,
> + ? ? ? .free ? ? ? ? ? ? ? ? ? = alpha_pci_free_coherent,
> ? ? ? ?.map_page ? ? ? ? ? ? ? = alpha_pci_map_page,
> ? ? ? ?.unmap_page ? ? ? ? ? ? = alpha_pci_unmap_page,
> ? ? ? ?.map_sg ? ? ? ? ? ? ? ? = alpha_pci_map_sg,
> --
> 1.7.1.569.g6f426
>

Acked-by: Matt Turner <mattst88 at gmail.com>


From arnd at arndb.de  Tue Mar 27 12:15:43 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 27 Mar 2012 16:15:43 +0000
Subject: [PATCH v3 6/6] mmc: sdhci-s3c: Add device tree support
In-Reply-To: <1328032576-9269-7-git-send-email-thomas.abraham@linaro.org>
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>
 <1328032576-9269-7-git-send-email-thomas.abraham@linaro.org>
Message-ID: <201203271615.43394.arnd@arndb.de>

On Tuesday 31 January 2012, Thomas Abraham wrote:
> +
> +Optional Board Specific Properties:
> +- samsung,sdhci-bus-width: Number of data lines connected to the controller.
> +  Note: This excludes the clock,command and card detect lines. If this property
> +  is not specified, default value is 1.
> +
> +- samsung,cd-gpio-invert: If 'samsung,sdhci-cd-gpio' card detect method is
> +  selected, this property can be optionally specified to invert the value of
> +  external card detect gpio line.
> +
> +- One of the following properties for card detect type.
> +  - samsung,sdhci-cd-internal: Card detect line from the card slot  is
> +    connected to the card detect pad of the sdhci controller. A gpio is
> +    used for this connection (with possible pin function settings).
> +  - samsung,sdhci-cd-gpio: A gpio line (with possible pin function settings)
> +    is used a card detect line. This gpio line is not connected to card detect
> +    pad of the sdhci controller.
> +  - samsung,sdhci-cd-none: There is no card detect line. Polling is used to
> +    detect the presence of the card. (DEFAULT, if no card detect property
> +    is specified).
> +  - samsung,sdhci-cd-permanent: There is no card detect line. The card is
> +    permanently connected to the sdhci controller.
> +
> +- gpio-cd: The gpio to be used as card detect line for
> +  'samsung,sdhci-cd-internal' or 'samsung,sdhci-cd-gpio' card detection method.
> +  The gpio specifier format depends on the gpio controller.

These bindings came up in a discussion IRC today. I think it's rather bad that
we can't agree on a common way to name the properties for mmc. We have
bindings being proposed or already included from Anton, Stephen, Shawn,
Rajendra, Viresh, Lee and Thomas. Almost all of them define GPIO pins
for card detect and write protect, as well properties to define the bus
width and high-speed modes, but we seem to have almost as many different
definitions of these as we have drivers.

Can we please come up with a common binding for these?

	Arnd



From arnd at arndb.de  Tue Mar 27 12:19:13 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Tue, 27 Mar 2012 16:19:13 +0000
Subject: [PATCH v3 6/6] mmc: sdhci-s3c: Add device tree support
In-Reply-To: <1328032576-9269-7-git-send-email-thomas.abraham@linaro.org>
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>
 <1328032576-9269-7-git-send-email-thomas.abraham@linaro.org>
Message-ID: <201203271619.13320.arnd@arndb.de>

On Tuesday 31 January 2012, Thomas Abraham wrote:
> +
> +Optional Board Specific Properties:
> +- samsung,sdhci-bus-width: Number of data lines connected to the controller.
> +  Note: This excludes the clock,command and card detect lines. If this property
> +  is not specified, default value is 1.
> +
> +- samsung,cd-gpio-invert: If 'samsung,sdhci-cd-gpio' card detect method is
> +  selected, this property can be optionally specified to invert the value of
> +  external card detect gpio line.
> +
> +- One of the following properties for card detect type.
> +  - samsung,sdhci-cd-internal: Card detect line from the card slot  is
> +    connected to the card detect pad of the sdhci controller. A gpio is
> +    used for this connection (with possible pin function settings).
> +  - samsung,sdhci-cd-gpio: A gpio line (with possible pin function settings)
> +    is used a card detect line. This gpio line is not connected to card detect
> +    pad of the sdhci controller.
> +  - samsung,sdhci-cd-none: There is no card detect line. Polling is used to
> +    detect the presence of the card. (DEFAULT, if no card detect property
> +    is specified).
> +  - samsung,sdhci-cd-permanent: There is no card detect line. The card is
> +    permanently connected to the sdhci controller.
> +
> +- gpio-cd: The gpio to be used as card detect line for
> +  'samsung,sdhci-cd-internal' or 'samsung,sdhci-cd-gpio' card detection method.
> +  The gpio specifier format depends on the gpio controller.

These bindings came up in a discussion IRC today. I think it's rather bad that
we can't agree on a common way to name the properties for mmc. We have
bindings being proposed or already included from Anton, Stephen, Shawn,
Rajendra, Viresh, Lee and Thomas. Almost all of them define GPIO pins
for card detect and write protect, as well properties to define the bus
width and high-speed modes, but we seem to have almost as many different
definitions of these as we have drivers.

Can we please come up with a common binding for these?

	Arnd


From rkuo at codeaurora.org  Tue Mar 27 12:41:40 2012
From: rkuo at codeaurora.org (Richard Kuo)
Date: Tue, 27 Mar 2012 11:41:40 -0500
Subject: [PATCHv2 10/14] Hexagon: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-11-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
 <1332855768-32583-11-git-send-email-m.szyprowski@samsung.com>
Message-ID: <20120327164140.GA3916@codeaurora.org>

On Tue, Mar 27, 2012 at 03:42:44PM +0200, Marek Szyprowski wrote:
> Adapt core Hexagon architecture code for dma_map_ops changes: replace
> alloc/free_coherent with generic alloc/free methods.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
> Reviewed-by: Arnd Bergmann <arnd at arndb.de>
> ---
>  arch/hexagon/include/asm/dma-mapping.h |   18 ++++++++++++------
>  arch/hexagon/kernel/dma.c              |    9 +++++----
>  2 files changed, 17 insertions(+), 10 deletions(-)
> 

Acked-by: Richard Kuo <rkuo at codeaurora.org> 

-- 

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From jonathan.austin at arm.com  Tue Mar 27 12:50:38 2012
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 27 Mar 2012 17:50:38 +0100
Subject: [PATCH RESEND 1/2] ARM: ThumbEE: Disable userspace TEEHBR access for
 !CONFIG_ARM_THUMBEE
Message-ID: <1332867039-3567-1-git-send-email-jonathan.austin@arm.com>

Currently when ThumbEE is not enabled (!CONFIG_ARM_THUMBEE) the ThumbEE
register states are not saved/restored at context switch. The default state
of the ThumbEE Ctrl register (TEECR) allows userspace accesses to the
ThumbEE Base Handler register (TEEHBR). This can cause unexpected behaviour
when people use ThumbEE on !CONFIG_ARM_THUMBEE kernels, as well as allowing
covert communication - eg between userspace tasks running inside chroot
jails.

This patch sets up TEECR in order to prevent user-space access to TEEHBR
when !CONFIG_ARM_THUMBEE. In this case, tasks are sent SIGILL if they try to
access TEEHBR.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---

Resending these patches, rebased on v3.3. If there are no comments again
this time around I will submit them to the patch-system when RC1 comes
around.


 arch/arm/mm/proc-v7.S |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index f1c8486..c2e2b66 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -255,6 +255,18 @@ __v7_setup:
 	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
 	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
 #endif
+#ifndef CONFIG_ARM_THUMBEE
+	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
+	and	r0, r0, #(0xf << 12)		@ ThumbEE enabled field
+	teq	r0, #(1 << 12)			@ check if ThumbEE is present
+	bne	1f
+	mov	r5, #0
+	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0
+	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR
+	orr	r0, r0, #1			@ set the 1st bit in order to
+	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access
+1:
+#endif
 	adr	r5, v7_crval
 	ldmia	r5, {r5, r6}
 #ifdef CONFIG_CPU_ENDIAN_BE8
-- 
1.7.1




From jonathan.austin at arm.com  Tue Mar 27 12:50:39 2012
From: jonathan.austin at arm.com (Jonathan Austin)
Date: Tue, 27 Mar 2012 17:50:39 +0100
Subject: [PATCH RESEND 2/2] ARM: ThumbEE: Use cpuid macros to read ID_PFR0 for
 ThumbEE
In-Reply-To: <1332867039-3567-1-git-send-email-jonathan.austin@arm.com>
References: <1332867039-3567-1-git-send-email-jonathan.austin@arm.com>
Message-ID: <1332867039-3567-2-git-send-email-jonathan.austin@arm.com>

The ThumbEE probe code uses inline assembly to read ID_PFR0 in order to
detect whether ThumbEE is implemented by the processor.

This patch replaces the inline asm with the read_cpuid_ext macro.

Signed-off-by: Jonathan Austin <jonathan.austin at arm.com>
Reviewed-by: Will Deacon <will.deacon at arm.com>
---

Resending these patches, rebased on v3.3. If there are no comments again
this time around I will submit them to the patch-system when RC1 comes
around.
 

 arch/arm/kernel/thumbee.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c
index 9cb7aac..3471f63 100644
--- a/arch/arm/kernel/thumbee.c
+++ b/arch/arm/kernel/thumbee.c
@@ -20,6 +20,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
+#include <asm/cputype.h>
 #include <asm/thread_notify.h>
 
 /*
@@ -66,8 +67,7 @@ static int __init thumbee_init(void)
 	if (cpu_arch < CPU_ARCH_ARMv7)
 		return 0;
 
-	/* processor feature register 0 */
-	asm("mrc	p15, 0, %0, c0, c1, 0\n" : "=r" (pfr0));
+	pfr0 = read_cpuid_ext(CPUID_EXT_PFR0);
 	if ((pfr0 & 0x0000f000) != 0x00001000)
 		return 0;
 
-- 
1.7.1




From tony at atomide.com  Tue Mar 27 13:04:45 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 27 Mar 2012 10:04:45 -0700
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators
 for v3.4
In-Reply-To: <CANOLnOMfsdGn-B0zftcV-zh+tSCGgmf0g1BsrFB0+Kh-HnNq0g@mail.gmail.com>
References: <20120308021843.GQ12083@atomide.com> <87399jc6cj.fsf@ti.com>
 <20120309003217.GB12083@atomide.com>
 <20120309114731.GA3273@opensource.wolfsonmicro.com>
 <87zkbp4wtj.fsf@ti.com>
 <20120311204232.GC3171@opensource.wolfsonmicro.com>
 <87399dzq5e.fsf@ti.com>
 <20120312173215.GL3110@opensource.wolfsonmicro.com>
 <87pqchv1pc.fsf@ti.com>
 <CANOLnOMfsdGn-B0zftcV-zh+tSCGgmf0g1BsrFB0+Kh-HnNq0g@mail.gmail.com>
Message-ID: <20120327170445.GP9859@atomide.com>

* Grazvydas Ignotas <notasas at gmail.com> [120327 07:00]:
> On Tue, Mar 13, 2012 at 1:28 AM, Kevin Hilman <khilman at ti.com> wrote:
> > Tony, updated pull request below. ?This includes all the TWL depencies
> > merged from the 'topic/twl' tag in Mark's tree.
> >
> 
> Has this been lost now? It seems regulator parts got merged, but
> voltage parts are missing from Arnd's pull requests and are not
> showing up in linux-next.
> Was looking forward for voltage control in 3.4 to achieve higher clock
> rates on our aging OMAP3 hardware.

Sounds like this is something we should get merged early to arm-soc
tree after the merge window.

Regards,

Tony


From tony at atomide.com  Tue Mar 27 13:28:20 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 27 Mar 2012 10:28:20 -0700
Subject: [PATCH 05/12] Add dummy smsc911x regulators to cm-t35.
In-Reply-To: <4F71E290.2050403@compulab.co.il>
References: <1332494504-10251-1-git-send-email-Russ.Dill@ti.com>
 <1332494504-10251-6-git-send-email-Russ.Dill@ti.com>
 <4F71E290.2050403@compulab.co.il>
Message-ID: <20120327172819.GQ9859@atomide.com>

* Igor Grinberg <grinberg at compulab.co.il> [120327 08:56]:
> Hi Russ,
> 
> This patch works, but can we, please use the attached patch instead?

Hmm what's the difference here? Do you have some real controllable
regulator for one of the smsc911x instances?

Anyways, I take it that you have tested that both smsc911x interfaces
work now?

Regards,

Tony


From gdavis at mvista.com  Tue Mar 27 13:41:52 2012
From: gdavis at mvista.com (George G. Davis)
Date: Tue, 27 Mar 2012 13:41:52 -0400
Subject: ARM11MPcore: tlb_ops_need_broadcast causes deadlock
In-Reply-To: <20120327133226.GE18738@mudshark.cambridge.arm.com>
References: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
 <20120323173055.GC16225@mudshark.cambridge.arm.com>
 <274124B9C6907D4B8CE985903EAA19E91B2D5798D9@SI-MBX06.de.bosch.com>
 <20120327133226.GE18738@mudshark.cambridge.arm.com>
Message-ID: <20120327174152.GA905@mvista.com>

Hello,

On Tue, Mar 27, 2012 at 02:32:26PM +0100, Will Deacon wrote:
> Peter,
> 
> On Mon, Mar 26, 2012 at 05:10:45PM +0100, EXTERNAL Waechtler Peter (Fa. TCP, CM-AI/PJ-CF31) wrote:
> > Probably just an "expected deadlock" as mentioned in the comment
> > of the v6_early_abort macro:
> > 
> >  * Purpose : obtain information about current aborted instruction.
> >  * Note: we read user space.  This means we might cause a data
> >  * abort here if the I-TLB and D-TLB aren't seeing the same
> >  * picture.  Unfortunately, this does happen.  We live with it.
> 
> I don't see this referring to an expected deadlock.
> 
> > For now the errata workarounds are removed for the 11MPcore
> > like proposed in this thread to avoid faulting with IRQs turned off:
> > 
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/041869.html
> > 
> > But there it looked like an optimization, but it wasn't.
> 
> I have a theory about what goes on:
> 
> Say we have a valid (i.e. non-faulting) page which contains a load instruction
> that will fault. A CPU executes this load and takes a data abort but at the
> same time another CPU marks the page being executed as old. So when the
> original CPU tries to load the faulting instruction in do_thumb_abort, we take
> a second data abort (assumedly because we don't have a D-side TLB entry for the
> text page, so we immediately see that it is old) and, because interrupts were
> not yet re-enabled in the first fault, they are not enabled in the nested fault
> either.

This is precisely what happened here.  The only difference is that the traces
I've reviewed faulted at "not_thumb:" while attempting to read the userspace
ARM instruction which lead to the (second) data abort with interrupts disabled.


> At this point, the faulting CPU will be unable to get the lock on the page,
> since the other guy has it and is waiting for the TLB broadcast to complete.
> Given that interrupts are disabled on the faulting CPU, everything locks up.

Right again.


> Possible solutions:
> 
> (1) Enable interrupts if they are enabled in the faulting context before
>     loading instructions on the dabt path.
> 
> (2) Use the FSR to determine whather a fault is due to a read or a write on
>     ARMv6 - only load and disassemble the instruction on 1136 CPUs affected
>     by erratum #325103 (which aren't SMP, so cannot hit the problem above).

We submitted a change similar to (2) above to the ARM Linux kernel mailing
list for RFC [1] over a year ago.  That change [1] is similar to your change
below.


> The latter is probably best. Please can you try the patch below? I've
> checked that it does the right thing on an r0p1 1136 core using a simple
> fork/swp program to trigger a CoW.

I tested your patch but only on a CPU_V6K based SMP machine.  In this
case, ARM_ERRATA_326103 depends on CPU_V6, so is left disabled, renderring
this patch functionally equivaltent to [1] below.


> Will
> 
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index dfb0312..dedb885 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1163,6 +1163,15 @@ if !MMU
>  source "arch/arm/Kconfig-nommu"
>  endif
>  
> +config ARM_ERRATA_326103
> +       bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
> +       depends on CPU_V6
> +       help
> +         Executing a SWP instruction to read-only memory does not set bit 11
> +         of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
> +         treat the access as a read, preventing a COW from occurring and
> +         causing the faulting task to livelock.
> +
>  config ARM_ERRATA_411920
>         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
>         depends on CPU_V6 || CPU_V6K
> diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
> index ff1f7cc..8074199 100644
> --- a/arch/arm/mm/abort-ev6.S
> +++ b/arch/arm/mm/abort-ev6.S
> @@ -26,18 +26,23 @@ ENTRY(v6_early_abort)
>         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
>         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
>  /*
> - * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
> - * The test below covers all the write situations, including Java bytecodes
> + * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
>   */
> -       bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
> +#ifdef CONFIG_ARM_ERRATA_326103
> +       ldr     ip, =0x4107b36
> +       mrc     p15, 0, r3, c0, c0, 0           @ get processor id
> +       teq     ip, r3, lsr #4                  @ r0 ARM1136?
> +       bne     do_DataAbort
>         tst     r5, #PSR_J_BIT                  @ Java?
> +       tsteq   r5, #PSR_T_BIT                  @ Thumb?
>         bne     do_DataAbort
> -       do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
> -       ldreq   r3, [r4]                        @ read aborted ARM instruction
> +       bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
> +       ldr     r3, [r4]                        @ read aborted ARM instruction
>  #ifdef CONFIG_CPU_ENDIAN_BE8
> -       reveq   r3, r3
> +       rev     r3, r3
>  #endif
>         do_ldrd_abort tmp=ip, insn=r3
>         tst     r3, #1 << 20                    @ L = 0 -> write
>         orreq   r1, r1, #1 << 11                @ yes.
> +#endif
>         b       do_DataAbort

FYI/FWIW, your patch above suffered whitespace damage.

Thanks!

--
Regards,
George

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/041733.html


From khilman at ti.com  Tue Mar 27 13:49:32 2012
From: khilman at ti.com (Kevin Hilman)
Date: Tue, 27 Mar 2012 10:49:32 -0700
Subject: [GIT PULL] ARM: OMAP2+: PM: core support for SMPS regulators for
 v3.4
In-Reply-To: <CANOLnOMfsdGn-B0zftcV-zh+tSCGgmf0g1BsrFB0+Kh-HnNq0g@mail.gmail.com>
 (Grazvydas Ignotas's message of "Tue, 27 Mar 2012 16:57:40 +0300")
References: <877gywjhht.fsf@ti.com> <20120308021843.GQ12083@atomide.com>
 <87399jc6cj.fsf@ti.com> <20120309003217.GB12083@atomide.com>
 <20120309114731.GA3273@opensource.wolfsonmicro.com>
 <87zkbp4wtj.fsf@ti.com>
 <20120311204232.GC3171@opensource.wolfsonmicro.com>
 <87399dzq5e.fsf@ti.com>
 <20120312173215.GL3110@opensource.wolfsonmicro.com>
 <87pqchv1pc.fsf@ti.com>
 <CANOLnOMfsdGn-B0zftcV-zh+tSCGgmf0g1BsrFB0+Kh-HnNq0g@mail.gmail.com>
Message-ID: <87k426ndcj.fsf@ti.com>

Grazvydas Ignotas <notasas at gmail.com> writes:

> On Tue, Mar 13, 2012 at 1:28 AM, Kevin Hilman <khilman at ti.com> wrote:
>> Tony, updated pull request below. ?This includes all the TWL depencies
>> merged from the 'topic/twl' tag in Mark's tree.
>>
>
> Has this been lost now? It seems regulator parts got merged, but
> voltage parts are missing from Arnd's pull requests and are not
> showing up in linux-next.

Not lost, just delayed.   Due to problems in working out the
dependencies with the regulator core, this pull request was too late to
make it for v3.4.

Kevin


From gregkh at linuxfoundation.org  Tue Mar 27 13:54:33 2012
From: gregkh at linuxfoundation.org (Greg KH)
Date: Tue, 27 Mar 2012 10:54:33 -0700
Subject: [PATCH] atmel-serial: fix RS485 half-duplex problem
In-Reply-To: <6FF0F449D45DEE479E93D93A0C07A8BD025E8F0631@USROCEX01>
References: <6FF0F449D45DEE479E93D93A0C07A8BD025E8F0631@USROCEX01>
Message-ID: <20120327175433.GA6623@kroah.com>

On Tue, Mar 27, 2012 at 01:43:39PM -0400, Siftar, Gabe wrote:
> On our custom board, we are using RS485 in half-duplex mode on an AT91SAM9G45. 
> SER_RS485_RX_DURING_TX is not set as we do not want to receive the data we 
> transmit (our transceiver will receive transmitted data).  Although the current 
> driver attempts to disable and enable the receiver at the appropriate points, 
> incoming data is still loaded into the receive register causing our code to 
> receive the very last byte that was sent once the receiver is enabled.
>  
> I ran this by Atmel support and they wrote:  "The issue comes from the fact 
> that you disable the PDC/DMA Reception and not the USART Reception channel.  In 
> your case, the[n] you will still receive data into the USART_RHR register, and 
> maybe you [h]ave the overun flag set.  So please disable the USART reception 
> channel."
>   
> The following patch should force the driver to enable/disable the receiver via 
> RXEN/RXDIS fields of the USART control register.  It fixed the issue I was 
> having - perhaps others will find it useful as well.
> 
> Signed-off-by: Gabe Siftar <gabe.siftar at getingeusa.com>

That's nice, but:

> This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to which they are addressed. If you have received this email in error please notify the system manager. This message contains confidential information and is intended only for the individual named. If you are not the named addressee you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately by e-mail if you have received this e-mail by mistake and delete this e-mail from your system. If you are not the intended recipient you are notified that disclosing, copying, distributing or taking any action in reliance on the contents of this information is strictly prohibited.--

This footer just contridicted your signed-off-by:

So, what should I believe?

Hint, please remove such footers, and tell anyone who insists on them
that they directly prevent you from contributing to the kernel, as I can
not accept patches with this on it.

Care to resend this without the footer so I can accept it?

greg k-h


From Russ.Dill at ti.com  Tue Mar 27 14:32:13 2012
From: Russ.Dill at ti.com (Russ Dill)
Date: Tue, 27 Mar 2012 11:32:13 -0700
Subject: [PATCH 05/12] Add dummy smsc911x regulators to cm-t35.
In-Reply-To: <4F71E290.2050403@compulab.co.il>
References: <1332494504-10251-1-git-send-email-Russ.Dill@ti.com>
 <1332494504-10251-6-git-send-email-Russ.Dill@ti.com>
 <4F71E290.2050403@compulab.co.il>
Message-ID: <CA+Bv8XYiv+gr4yB+k7sWSSjdYSsYdnRJuTO3A5zZhh4bkoziXw@mail.gmail.com>

No objection.

On Tue, Mar 27, 2012 at 8:53 AM, Igor Grinberg <grinberg at compulab.co.il> wrote:
> Hi Russ,
>
> This patch works, but can we, please use the attached patch instead?
>
> Thanks
>
> On 03/23/12 11:21, Russ Dill wrote:
>> Signed-off-by: Russ Dill <russ.dill at ti.com>
>> ---
>> ?arch/arm/mach-omap2/board-cm-t35.c | ? ?9 +++++++++
>> ?1 files changed, 9 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
>> index 41b0a2f..289ded3 100644
>> --- a/arch/arm/mach-omap2/board-cm-t35.c
>> +++ b/arch/arm/mach-omap2/board-cm-t35.c
>> @@ -26,6 +26,7 @@
>>
>> ?#include <linux/i2c/at24.h>
>> ?#include <linux/i2c/twl.h>
>> +#include <linux/regulator/fixed.h>
>> ?#include <linux/regulator/machine.h>
>> ?#include <linux/mmc/host.h>
>>
>> @@ -630,10 +631,18 @@ static inline void cm_t3730_init_mux(void) {}
>> ?static struct omap_board_config_kernel cm_t35_config[] __initdata = {
>> ?};
>>
>> +static struct regulator_consumer_supply dummy_supplies[] = {
>> + ? ? REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
>> + ? ? REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
>> + ? ? REGULATOR_SUPPLY("vddvario", "smsc911x.1"),
>> + ? ? REGULATOR_SUPPLY("vdd33a", "smsc911x.1"),
>> +};
>> +
>> ?static void __init cm_t3x_common_init(void)
>> ?{
>> ? ? ? omap_board_config = cm_t35_config;
>> ? ? ? omap_board_config_size = ARRAY_SIZE(cm_t35_config);
>> + ? ? regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
>> ? ? ? omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
>> ? ? ? omap_serial_init();
>> ? ? ? omap_sdrc_init(mt46h32m32lf6_sdrc_params,
>
> --
> Regards,
> Igor.


From mturquette at ti.com  Tue Mar 27 14:49:25 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 27 Mar 2012 11:49:25 -0700
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <4F714397.6080608@codeaurora.org>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <20120320141811.GF32469@S2101-09.ap.freescale.net>
 <20120320181050.GN3852@pengutronix.de> <4F68E34A.70207@codeaurora.org>
 <20120320231242.GP3852@pengutronix.de>
 <CAJOA=zOGTW7OqACWgJQW6HSPLVev+apdNhv4vNXjHTcp=7N+uQ@mail.gmail.com>
 <4F694484.1030706@codeaurora.org> <4F714397.6080608@codeaurora.org>
Message-ID: <CAJOA=zOq=kYfZUEnnQT_D4w=Kpp5n7R=k9oOCrxF59P5W-nw-w@mail.gmail.com>

On Mon, Mar 26, 2012 at 9:35 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
> Mike,
>
> (*nudge*) (*nudge*)

Hi Saravana,

I spent some time mulling over the ideas this weekend and I agree that
we have 3 types of data, so having the three structs makes some sense.
 I'm checking this patch out more earnestly today.

Regards,
Mike

> -Saravana
>
>
>
> On 03/20/2012 08:01 PM, Saravana Kannan wrote:
>>
>> On 03/20/2012 06:47 PM, Turquette, Mike wrote:
>>>
>>> On Tue, Mar 20, 2012 at 4:12 PM, Sascha Hauer<s.hauer at pengutronix.de>
>>> wrote:
>>>>
>>>> On Tue, Mar 20, 2012 at 01:06:34PM -0700, Saravana Kannan wrote:
>>>>>
>>>>> On 03/20/2012 11:10 AM, Sascha Hauer wrote:
>>>>>>
>>>>>> On Tue, Mar 20, 2012 at 10:18:14PM +0800, Shawn Guo wrote:
>>>>>>>
>>>>>>> On Tue, Mar 20, 2012 at 10:40:31AM +0100, Sascha Hauer wrote:
>>>>>>> ...
>>>>>>>>
>>>>>>>> I am using these functions and don't need a static array, I just
>>>>>>>> call
>>>>>>>> the functions with the desired parameters.
>>>>>>>>
>>>>>>> With this patch getting in, you do not have to use them then. I feel
>>>>>>> a static array will be much more readable than a long list of
>>>>>>> function
>>>>>>> calls with a long list of hardcoded arguments to each.
>>>>>>
>>>>>>
>>>>>> I'm also not a fan of long argument lists; a divider like defined
>>>>>> in my
>>>>>> tree takes 5 arguments, a gate 4 and a mux 6. While 6 is already at
>>>>>> the
>>>>>> border I think it's still acceptable.
>>>>>>
>>>>>> What I like in terms of readability is one line per clock which makes
>>>>>> for quite short clock files.
>>>>>
>>>>>
>>>>> It certainly makes for short clock files, but it's definitely less
>>>>> readable that the expanded struct. For the original author the "one
>>>>> line per clock" looks readable since they wrote it. But for someone
>>>>> looking at the code to modify it, the expanded one would be much
>>>>> easier to read. Also, you can always declare your own macro if you
>>>>> really want to follow the one line approach.
>>>>>
>>>>>> So when we use structs to initialize the clocks we'll probably have
>>>>>> something like this:
>>>>>>
>>>>>> static struct clk_divider somediv = {
>>>>>> .reg = CCM_BASE + 0x14,
>>>>>> .width = 3,
>>>>>> .shift = 17,
>>>>>> .lock =&ccm_lock,
>>>>>> .hw.parent = "someotherdiv",
>>>>>> .hw.flags = CLK_SET_RATE_PARENT,
>>>>>> };
>>>>>
>>>>>
>>>>> Taken from your patches:
>>>>>
>>>>> imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
>>>>> ARRAY_SIZE(spll_sel_clks));
>>>>>
>>>>> Compare the struct to the one line call. Now tell me, what does "1"
>>>>> represent? No clue. But in the struct, I can immediately tell what
>>>>> each one of the parameters are.
>>>>>
>>>>> Anyway, my patch certainly isn't forcing you to use multiple lines.
>>>>> So, hopefully this won't be a point of contention.
>>>>>
>>>>>> This will make a 4000 line file out of a 500 line file. Now when for
>>>>>> some reason struct clk_divider changes we end with big patches. If the
>>>>>> clk core gets a new fancy CLK_ flag which we want to have then again
>>>>>> we end up with big patches. Then there's also the possibility that
>>>>>> someone finds out that .lock and .hw.flags are common to all dividers
>>>>>> and comes up with a #define DEFINE_CLK_DIVIDER again to share common
>>>>>> fields.
>>>>>
>>>>>
>>>>> This patch won't prevent you from doing any of that. You can still
>>>>> create macros for that (there are already one for that). Also, what
>>>>> you are pointing out is a bigger problem for the current
>>>>> clk_register() function since you might have to change the no. of
>>>>> params of all the callers even if a new field is optional.
>>>>>
>>>>>> All this can be solved when we introduce a small wrapper function and
>>>>>> use it in the clock files:
>>>>>>
>>>>>> static inline struct clk *imx_clk_divider(const char *name, const
>>>>>> char *parent,
>>>>>> void __iomem *reg, u8 shift, u8 width)
>>>>>> {
>>>>>> return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
>>>>>> reg, shift, width, 0,&imx_ccm_lock);
>>>>>> }
>>>>>>
>>>>>> It decouples us from the structs used by the clock framework, we can
>>>>>> add our preferred flags and still can share common fields like the
>>>>>> lock.
>>>>>>
>>>>>> While this was not the intention when I first converted from struct
>>>>>> initializers to function initializers I am confident that it will make
>>>>>> a good job.
>>>>>
>>>>>
>>>>> Now I'm confused -- it's not clear if you are leaning towards my
>>>>> patch or away from it?
>>>>
>>>>
>>>> There was a tendency to get rid of static initializers and I like the
>>>> idea of not exposing any of the internally used members outside the
>>>> clock framework.
>>>
>>>
>>> I'm with Sascha on this. I feel that dividing the interface strictly
>>> into two halves is the best way.
>>
>>
>> I addressed this concern in my earlier comments. We can make a copy or
>> we can agree the fields I moved to clk_hw aren't really useful wrt
>> writing hacky code and call it a day. Can you please clarify why neither
>> of these options are acceptable?
>>
>>> I have an uneasy feeling about
>>> exposing this stuff into struct clk_hw (or clk_initializer or
>>> whatever). This stretches the data out across three structures and
>>> just doesn't feel right to me.
>>
>>
>> Wrt this discussion, there are three distinct classes of data:
>> 1) Those specific to the platform driver that the common code shouldn't
>> care about.
>> 2) Those specific to the common code that the platform driver shouldn't
>> care about.
>> 3) Stuff that's shared/passed between common code and the platform driver.
>>
>> When we have three classes of data, I don't what's wrong with having
>> three struct types to contain them. If anything, it's better than the
>> current approach of exposing the common clock code specific data (struct
>> clk) to code outside of common clock code just because we want to allow
>> static initialization. The end goal should be to move struct clk inside
>> clk.c.
>>
>> I think this patch just takes us one step close to that since IMX and
>> MSM won't have to include clk-private.h in any of our platform specific
>> files while also allowing OMAP to include it for the near term.
>>
>>>> Now people try their best to make themselves comfortable with the
>>>> static initializers and you even discussed the possibility of removing
>>>> the clk_register_* functions (which make it possible for users not
>>>> to use any of the internal struct members). That's what I don't like
>>>> about your patches. But if we go for static initializers anyway then
>>>> your
>>>> patches probably change things for the better.
>>>
>>>
>>> Static initialization is something I have fought for; in fact the
>>> original patches provided no way to do it, so clearly what we have
>>> today is some progress for the folks desiring static init.
>>
>>
>> I too desire static init. Sorry if I was unclear and gave people the
>> misconception that I wanted to remove static init.
>>
>>> The patch
>>> above doesn't actually prevent allocation from happening as it still
>>> must call into clk_register and kmalloc struct clk,
>>
>>
>> Correct.
>>
>>> so besides
>>> readability, I'm not sure what these patches buy us.
>>
>>
>> I think readability is very important and if this buys us nothing but
>> readability, we should still take this patch. But there are other
>> benefits too -- I mentioned them in the commit text.
>>
>>> Assuming that C99 designated initializers (for the sole purpose of
>>> readability) is the main draw of the above patch, please let me know
>>> what you think about modifying the existing static init macros so that
>>> your clock data looks like this:
>>>
>>> DEFINE_CLK_DIVIDER(dpll_iva_m5x2_ck,&dpll_iva_x2_ck, "dpll_iva_x2_ck",
>>> .flags = 0x0,
>>> .reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
>>> .shift = OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT,
>>> .width = OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH,
>>> .flags = CLK_DIVIDER_ONE_BASED,
>>> .lock = NULL
>>> );
>>>
>>> Note that the first argument is the name of this clock (and will be
>>> properly stringified for .name = "whatever") and that the second and
>>> third arguments are both the parent clock, used for initializing the
>>> parent pointer and .parent_names, respectively. If that aspect of the
>>> macro is too ugly then those can even be broken out into a separate
>>> macro since they are independent data structure (struct clk **parents,
>>> and char **parent_names). Or you could just open code those data
>>> structures and only use a macro for struct clk and struct clk_foo.
>>>
>>> This gives you the readability of C99 designated initializers while
>>> keeping struct clk's members totally hidden from the rest of the
>>> world.
>>
>>
>> But it still leaves the struct clk exposed to people who do static init
>> of the clock tree. I think agreeing that the name, parent names, flags
>> and ops are not used to hack with or just making a copy of all of them
>> (and mark the originals as __init if that's doable). is a better
>> solution than trying to go with macros and leave struct clk exposed to
>> everyone who want to do static init of the clock tree.
>>
>> At a later point when we are ready to move struct clk inside clk.c, with
>> this patch applied right now, IMX and MSM won't have to churn their code.
>>
>> Thanks,
>> Saravana
>>
>
>
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From s.hauer at pengutronix.de  Tue Mar 27 15:40:10 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 27 Mar 2012 21:40:10 +0200
Subject: [PATCH 09/10] clk: dynamically allocate parent_names basic clk
 registration
In-Reply-To: <20120327125122.GB3719@S2101-09.ap.freescale.net>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-10-git-send-email-shawn.guo@linaro.org>
 <20120327085514.GI29317@pengutronix.de>
 <20120327125122.GB3719@S2101-09.ap.freescale.net>
Message-ID: <20120327194010.GJ29317@pengutronix.de>

On Tue, Mar 27, 2012 at 08:51:24PM +0800, Shawn Guo wrote:
> On Tue, Mar 27, 2012 at 10:55:14AM +0200, Sascha Hauer wrote:
> > On Tue, Mar 27, 2012 at 03:23:28PM +0800, Shawn Guo wrote:
> > > It's not necessary to have "char *parent[1]" carried in struct clk_gate
> > > and clk_divider.  Instead, it can be dynamically allocated in
> > > registration function, just like what clk_register_fixed_rate does.
> > 
> > I patched it the way it is to get rid of the additional malloc which
> > seemed unnecessary. Maybe the real question is whether the core should
> > duplicate the parent strings instead of the basic clock types.
> > 
> If we can ensure the parent strings will only be used during
> clk_register call, we do not need to duplicate the parent strings.
> 
> But right now the parent strings is used not only in clk_register call
> but also __clk_set_parent for finding parent index in case the search
> on cached parent points fails.  I guess Mike has a good reason for that.

Probably. That's why I suggest to copy the strings in the framework.
Then we do not have to duplicate the code to copy the strings and also
make sure that the core works on its own strings.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From jon-hunter at ti.com  Tue Mar 27 15:52:49 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Tue, 27 Mar 2012 14:52:49 -0500
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used
 OMAP4 onwards
In-Reply-To: <1332842311-12308-1-git-send-email-rnayak@ti.com>
References: <1332842311-12308-1-git-send-email-rnayak@ti.com>
Message-ID: <4F721A91.7000102@ti.com>

Hi Rajendra,

On 3/27/2012 4:58, Rajendra Nayak wrote:
> Some functions like _omap4_disable_module() and _omap4_wait_target_disable()
> are (will be) used on all OMAPs OMAP4 and beyond which support module level
> control. Fix the error checks in these functions to return if called on
> any platform pre OMAP4 (i.e OMAP2 and OMAP3) instead of checking for
> !cpu_is_omap44xx(). This avoids having to update the error check with a
> '&&  !cpu_is_omap54xx()' when OMAP5 is introduced and possibly similar updates
> when further OMAP generations are added.
>
> Signed-off-by: Rajendra Nayak<rnayak at ti.com>
> ---
>   arch/arm/mach-omap2/omap_hwmod.c |    4 ++--
>   1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 8ac26f2..f2a9afa 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -808,7 +808,7 @@ static void _enable_module(struct omap_hwmod *oh)
>    */
>   static int _omap4_wait_target_disable(struct omap_hwmod *oh)
>   {
> -	if (!cpu_is_omap44xx())
> +	if (cpu_is_omap24xx() || cpu_is_omap34xx())
>   		return 0;

What about omap36xx?

>   	if (!oh)
> @@ -838,7 +838,7 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
>   	int v;
>
>   	/* The module mode does not exist prior OMAP4 */
> -	if (!cpu_is_omap44xx())
> +	if (cpu_is_omap24xx() || cpu_is_omap34xx())
>   		return -EINVAL;

Same here.

>
>   	if (!oh->clkdm || !oh->prcm.omap4.modulemode)

Cheers
Jon


From gregkh at linuxfoundation.org  Tue Mar 27 16:26:28 2012
From: gregkh at linuxfoundation.org (Greg KH)
Date: Tue, 27 Mar 2012 13:26:28 -0700
Subject: [PATCH] atmel-serial: fix RS485 half-duplex problem
In-Reply-To: <6FF0F449D45DEE479E93D93A0C07A8BD025E9F8D47@USROCEX01>
References: <6FF0F449D45DEE479E93D93A0C07A8BD025E8F0631@USROCEX01>
 <20120327175433.GA6623@kroah.com>
 <6FF0F449D45DEE479E93D93A0C07A8BD025E9F8D47@USROCEX01>
Message-ID: <20120327202628.GB15798@kroah.com>

On Tue, Mar 27, 2012 at 04:20:51PM -0400, Siftar, Gabe wrote:
> >From: Greg KH [mailto:gregkh at linuxfoundation.org]
> >Sent: Tuesday, March 27, 2012 1:55 PM
> >Care to resend this without the footer so I can accept it?
> 
> Sorry.  It turns out that the footer was added by our 3rd party email 
> filtering service - I hope that it's no longer being included.

Looks good, thanks, I'll queue this up once 3.4-rc1 is out.

thanks,

greg k-h


From jon-hunter at ti.com  Tue Mar 27 17:08:51 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Tue, 27 Mar 2012 16:08:51 -0500
Subject: [PATCH 1/3] OMAP2+: UART: Remove cpu checks for populating errata
 flags
In-Reply-To: <1332325501-10467-2-git-send-email-govindraj.raja@ti.com>
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
 <1332325501-10467-2-git-send-email-govindraj.raja@ti.com>
Message-ID: <4F722C63.9080900@ti.com>

Hi Govindraj,

On 3/21/2012 5:24, Govindraj.R wrote:
> From: "Govindraj.R"<govindraj.raja at ti.com>
>
> Currently the errata is populated based on cpu checks this can
> be removed and replaced with module version check of uart ip block.
> MVR reg is provided within the uart reg map use the same
> to populate the errata and thus now errata population and handling
> can be managed within the driver itself.
>
> Cc: Paul Walmsley<paul at pwsan.com>
> Cc: Kevin Hilman<khilman at ti.com>
> Signed-off-by: Felipe Balbi<balbi at ti.com>
> Signed-off-by: Govindraj.R<govindraj.raja at ti.com>
> ---
>   arch/arm/mach-omap2/serial.c                  |    8 ---
>   arch/arm/plat-omap/include/plat/omap-serial.h |    1 -
>   drivers/tty/serial/omap-serial.c              |   62 ++++++++++++++++++++++++-
>   3 files changed, 61 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
> index f590afc..330ee04 100644
> --- a/arch/arm/mach-omap2/serial.c
> +++ b/arch/arm/mach-omap2/serial.c
> @@ -357,14 +357,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
>   	omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
>   	omap_up.autosuspend_timeout = info->autosuspend_timeout;
>
> -	/* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
> -	if (!cpu_is_omap2420()&&  !cpu_is_ti816x())
> -		omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
> -
> -	/* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
> -	if (cpu_is_omap34xx() || cpu_is_omap3630())
> -		omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
> -
>   	pdata =&omap_up;
>   	pdata_size = sizeof(struct omap_uart_port_info);
>
> diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
> index 9ff4444..1a52725 100644
> --- a/arch/arm/plat-omap/include/plat/omap-serial.h
> +++ b/arch/arm/plat-omap/include/plat/omap-serial.h
> @@ -65,7 +65,6 @@ struct omap_uart_port_info {
>   	bool			dma_enabled;	/* To specify DMA Mode */
>   	unsigned int		uartclk;	/* UART clock rate */
>   	upf_t			flags;		/* UPF_* flags */
> -	u32			errata;
>   	unsigned int		dma_rx_buf_size;
>   	unsigned int		dma_rx_timeout;
>   	unsigned int		autosuspend_timeout;
> diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
> index f809041..c7666d6 100644
> --- a/drivers/tty/serial/omap-serial.c
> +++ b/drivers/tty/serial/omap-serial.c
> @@ -44,6 +44,13 @@
>   #include<plat/dmtimer.h>
>   #include<plat/omap-serial.h>
>
> +#define UART_BUILD_REVISION(x, y)	(((x)<<  8) | (y))
> +
> +#define OMAP_UART_REV_42 0x0402
> +#define OMAP_UART_REV_46 0x0406
> +#define OMAP_UART_REV_52 0x0502
> +#define OMAP_UART_REV_63 0x0603
> +
>   #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
>
>   /* SCR register bitmasks */
> @@ -1346,6 +1353,58 @@ static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
>   	return;
>   }
>
> +static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
> +{
> +	u32 mvr, scheme;
> +	u16 revision, major, minor;
> +
> +	mvr = serial_in(up, UART_OMAP_MVER);
> +
> +	/* Check revision register scheme */
> +	scheme = mvr&  (0x03<<  30);
> +	scheme>>= 30;

Minor nit-pick, why not ...

	scheme = mvr >> 30;

> +	switch (scheme) {
> +	case 0: /* Legacy Scheme: OMAP2/3 */
> +		/* MINOR_REV[0:4], MAJOR_REV[4:7] */

This scheme is also true from OMAP1 devices. Maybe we could include in 
the comment.

> +		major = (mvr&  0xf0)>>  4;
> +		minor = (mvr&  0x0f);
> +		break;
> +	case 1:
> +		/* New Scheme: OMAP4+ */
> +		/* MINOR_REV[0:5], MAJOR_REV[8:10] */
> +		major = (mvr&  0x7<<  8)>>  8;

Nit-pick ...

	major = (mvr >> 8) & 0x7;

Cheers
Jon


From mturquette at ti.com  Tue Mar 27 17:09:28 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 27 Mar 2012 14:09:28 -0700
Subject: [PATCH 02/10] clk: remove unnecessary EXPORT_SYMBOL_GPL
In-Reply-To: <20120327131002.GC3719@S2101-09.ap.freescale.net>
References: <20120327092828.GA16397@lunn.ch>
 <20120327131002.GC3719@S2101-09.ap.freescale.net>
Message-ID: <CAJOA=zMEtyYuPwSAnnJ2PUnymkn-QWD7rJaymemH5on21EB4Sw@mail.gmail.com>

On Tue, Mar 27, 2012 at 6:10 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Tue, Mar 27, 2012 at 11:28:28AM +0200, Andrew Lunn wrote:
>> > Date: Tue, 27 Mar 2012 15:23:21 +0800
>> > From: Shawn Guo <shawn.guo at linaro.org>
>> > To: linux-arm-kernel at lists.infradead.org
>> > Cc: Shawn Guo <shawn.guo at linaro.org>, Mike Turquette
>> > ? ? ? ?<mturquette at linaro.org>
>> > Subject: [PATCH 02/10] clk: remove unnecessary EXPORT_SYMBOL_GPL
>> > Message-ID: <1332833009-4121-3-git-send-email-shawn.guo at linaro.org>
>> >
>> > It makes no sense to have EXPORT_SYMBOL_GPL on static functions.
>>
>> Hi Shawn
>>
>> I agree, exporting static functions makes no sense.
>>
>> However, i think it would be good to export them. I will probably need
>> to build a clk very similar to the gated clock. I would like to use
>> these functions when building my ops structure and just add wrappers
>> around them where needed.
>>
>> Could you instead remove the static?
>>
> Hmm, I would not.
>
> I have a similar need for clk_divider_ops calls. ?Instead of exporting
> every single clk_gate_ops call, we should just export "struct clk_ops
> clk_gate_ops". ?That's exactly why I have the patch #4 here.

Andrew, does this approach work for you?  I prefer it over the EXPORT madness.

Regards,
Mike


From tony.luck at intel.com  Tue Mar 27 17:20:05 2012
From: tony.luck at intel.com (Tony Luck)
Date: Tue, 27 Mar 2012 14:20:05 -0700
Subject: [PATCH 05/14] IA64: adapt for dma_map_ops changes
In-Reply-To: <1324643253-3024-6-git-send-email-m.szyprowski@samsung.com>
References: <1324643253-3024-1-git-send-email-m.szyprowski@samsung.com>
 <1324643253-3024-6-git-send-email-m.szyprowski@samsung.com>
Message-ID: <CA+8MBbLAafFbVwviFmkjD0DNz5RsCbB_TNLL67wEi2k-hyXkXA@mail.gmail.com>

On Fri, Dec 23, 2011 at 4:27 AM, Marek Szyprowski
<m.szyprowski at samsung.com> wrote:
> From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
>
> Adapt core IA64 architecture code for dma_map_ops changes: replace
> alloc/free_coherent with generic alloc/free methods.
>
> Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
> ?arch/ia64/hp/common/sba_iommu.c ? ? | ? 11 ++++++-----
> ?arch/ia64/include/asm/dma-mapping.h | ? 18 ++++++++++++------
> ?arch/ia64/kernel/pci-swiotlb.c ? ? ?| ? ?9 +++++----
> ?arch/ia64/sn/pci/pci_dma.c ? ? ? ? ?| ? ?9 +++++----
> ?4 files changed, 28 insertions(+), 19 deletions(-)

The series breaks bisection from part 2 (when the x86 part changes
lib/swiotlb.c)
until part 5 (when ia64 sees the changes to match).  You could either merge part
5 into part 2 (to make a combined x86+ia64 piece) ... or try to pull
the libswiotlb
changes into their own piece (which would have some of the ia64 and x86 bits).
Or at the very least minimize the breakage window by putting ia64
right after x86
in the patch sequence.

Otherwise seems OK

Acked-by: Tony Luck <tony.luck at intel.com>


From tony.luck at intel.com  Tue Mar 27 17:53:01 2012
From: tony.luck at intel.com (Luck, Tony)
Date: Tue, 27 Mar 2012 21:53:01 +0000
Subject: [PATCH 05/14] IA64: adapt for dma_map_ops changes
In-Reply-To: <CA+8MBbLAafFbVwviFmkjD0DNz5RsCbB_TNLL67wEi2k-hyXkXA@mail.gmail.com>
References: <1324643253-3024-1-git-send-email-m.szyprowski@samsung.com>
 <1324643253-3024-6-git-send-email-m.szyprowski@samsung.com>
 <CA+8MBbLAafFbVwviFmkjD0DNz5RsCbB_TNLL67wEi2k-hyXkXA@mail.gmail.com>
Message-ID: <3908561D78D1C84285E8C5FCA982C28F15B724D8@ORSMSX104.amr.corp.intel.com>

> until part 5 (when ia64 sees the changes to match).  You could either merge part
> 5 into part 2 (to make a combined x86+ia64 piece

Doh! I see that you already did this in the re-post you did a few hours
ago (which my mail client had filed away in my linux-arch folder).

-Tony
 



From jm at lentin.co.uk  Tue Mar 27 17:54:13 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Tue, 27 Mar 2012 22:54:13 +0100
Subject: [PATCH V3 3/5] ARM: kirkwood: Allow nand to be configured via.
 devicetree
In-Reply-To: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
References: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1332885255-8304-4-git-send-email-jm@lentin.co.uk>

Add default configuration for NAND, to be enabled in your board config. Ensure
clock gating is set appropriately when the NAND is enabled.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
 arch/arm/boot/dts/kirkwood.dtsi |   15 ++++++++++++++-
 arch/arm/mach-kirkwood/common.c |   12 ++++++++++++
 2 files changed, 26 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 3474ef8..6b80374 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -5,7 +5,7 @@
 
 	ocp at f1000000 {
 		compatible = "simple-bus";
-		ranges = <0 0xf1000000 0x1000000>;
+		ranges = <0 0xf1000000 0x4000000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
@@ -32,5 +32,18 @@
 			reg = <0x10300 0x20>;
 			interrupts = <53>;
 		};
+
+		nand at 3000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cle = <0>;
+			ale = <1>;
+			bank-width = <8>;
+			compatible = "mrvl,orion-nand";
+			reg = <0x3000000 0x400>;
+			chip-delay = <25>;
+			/* set partition map and/or chip-delay in board dts */
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index a02cae8..3ad0373 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -15,6 +15,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mtd/nand.h>
 #include <linux/dma-mapping.h>
+#include <linux/of.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -482,6 +483,9 @@ static int __init kirkwood_clock_gate(void)
 	unsigned int curr = readl(CLOCK_GATING_CTRL);
 	u32 dev, rev;
 
+#ifdef CONFIG_OF
+	struct device_node *np;
+#endif
 	kirkwood_pcie_id(&dev, &rev);
 	printk(KERN_DEBUG "Gating clock of unused units\n");
 	printk(KERN_DEBUG "before: 0x%08x\n", curr);
@@ -489,6 +493,14 @@ static int __init kirkwood_clock_gate(void)
 	/* Make sure those units are accessible */
 	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 
+#ifdef CONFIG_OF
+	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-nand");
+	if (np && of_device_is_available(np)) {
+		kirkwood_clk_ctrl |= CGC_RUNIT;
+		of_node_put(np);
+	}
+#endif
+
 	/* For SATA: first shutdown the phy */
 	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
 		/* Disable PLL and IVREF */
-- 
1.7.9.1



From jm at lentin.co.uk  Tue Mar 27 17:54:12 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Tue, 27 Mar 2012 22:54:12 +0100
Subject: [PATCH V3 2/5] mtd: Add orion_nand devicetree bindings
In-Reply-To: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
References: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1332885255-8304-3-git-send-email-jm@lentin.co.uk>

Allow a NAND chip using the orion_nand driver to be described using devicetree.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
 .../devicetree/bindings/mtd/orion-nand.txt         |   46 ++++++++++++++++++++
 drivers/mtd/nand/orion_nand.c                      |   35 ++++++++++++++-
 2 files changed, 79 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
new file mode 100644
index 0000000..22c7438
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/orion-nand.txt
@@ -0,0 +1,46 @@
+NAND support for Marvell Orion SoC platforms
+
+Required properties:
+- compatible : "mrvl,orion-nand".
+- reg : Base physical address of the NAND and length of memory mapped
+	region
+
+Optional properties:
+- cle :
+- ale :
+- bank-width :
+- chip-delay :
+
+Examples:
+
+nand at f4000000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cle = <0>;
+	ale = <1>;
+	bank-width = <8>;
+	chip-delay = <25>;
+	compatible = "mrvl,orion-nand";
+	reg = <0xf4000000 0x400>;
+
+	partition at 0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+		read-only;
+	};
+
+	partition at 100000 {
+		label = "uImage";
+		reg = <0x0100000 0x200000>;
+	};
+
+	partition at 300000 {
+		label = "dtb";
+		reg = <0x0300000 0x100000>;
+	};
+
+	partition at 400000 {
+		label = "root";
+		reg = <0x0400000 0x7d00000>;
+	};
+};
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index 29f505a..3b7c82f 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -13,6 +13,7 @@
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
@@ -74,11 +75,13 @@ static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 static int __init orion_nand_probe(struct platform_device *pdev)
 {
 	struct mtd_info *mtd;
+	struct mtd_part_parser_data ppdata = {};
 	struct nand_chip *nc;
 	struct orion_nand_data *board;
 	struct resource *res;
 	void __iomem *io_base;
 	int ret = 0;
+	u32 val = 0;
 
 	nc = kzalloc(sizeof(struct nand_chip) + sizeof(struct mtd_info), GFP_KERNEL);
 	if (!nc) {
@@ -101,7 +104,26 @@ static int __init orion_nand_probe(struct platform_device *pdev)
 		goto no_res;
 	}
 
-	board = pdev->dev.platform_data;
+	if (pdev->dev.of_node) {
+		board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data),
+					GFP_KERNEL);
+		if (!board) {
+			printk(KERN_ERR "orion_nand: failed to allocate board structure.\n");
+			ret = -ENOMEM;
+			goto no_res;
+		}
+		if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
+			board->cle = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
+			board->ale = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node,
+						"bank-width", &val))
+			board->width = (u8)val;
+		if (!of_property_read_u32(pdev->dev.of_node,
+						"chip-delay", &val))
+			board->chip_delay = (u8)val;
+	} else
+		board = pdev->dev.platform_data;
 
 	mtd->priv = nc;
 	mtd->owner = THIS_MODULE;
@@ -129,7 +151,8 @@ static int __init orion_nand_probe(struct platform_device *pdev)
 	}
 
 	mtd->name = "orion_nand";
-	ret = mtd_device_parse_register(mtd, NULL, 0,
+	ppdata.of_node = pdev->dev.of_node;
+	ret = mtd_device_parse_register(mtd, NULL, &ppdata,
 			board->parts, board->nr_parts);
 	if (ret) {
 		nand_release(mtd);
@@ -161,11 +184,19 @@ static int __devexit orion_nand_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id orion_nand_of_match_table[] = {
+	{ .compatible = "mrvl,orion-nand", },
+	{},
+};
+#endif
+
 static struct platform_driver orion_nand_driver = {
 	.remove		= __devexit_p(orion_nand_remove),
 	.driver		= {
 		.name	= "orion_nand",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(orion_nand_of_match_table),
 	},
 };
 
-- 
1.7.9.1



From jm at lentin.co.uk  Tue Mar 27 17:54:15 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Tue, 27 Mar 2012 22:54:15 +0100
Subject: [PATCH V3 5/5] mtd: Move fdt partition documentation to a seperate
 file
In-Reply-To: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
References: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1332885255-8304-6-git-send-email-jm@lentin.co.uk>

Partitions are described in the same way for all mtd devices when using
devicetree, move the documentation to a separate file and add references
to it.

Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
 .../devicetree/bindings/mtd/arm-versatile.txt      |    4 +-
 .../devicetree/bindings/mtd/atmel-dataflash.txt    |    3 ++
 .../devicetree/bindings/mtd/fsl-upm-nand.txt       |    4 ++
 .../devicetree/bindings/mtd/gpio-control-nand.txt  |    3 ++
 .../devicetree/bindings/mtd/mtd-physmap.txt        |   23 +-----------
 .../devicetree/bindings/mtd/orion-nand.txt         |    3 ++
 .../devicetree/bindings/mtd/partition.txt          |   38 ++++++++++++++++++++
 7 files changed, 55 insertions(+), 23 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/partition.txt

diff --git a/Documentation/devicetree/bindings/mtd/arm-versatile.txt b/Documentation/devicetree/bindings/mtd/arm-versatile.txt
index 476845d..beace4b 100644
--- a/Documentation/devicetree/bindings/mtd/arm-versatile.txt
+++ b/Documentation/devicetree/bindings/mtd/arm-versatile.txt
@@ -4,5 +4,5 @@ Required properties:
 - compatible : must be "arm,versatile-flash";
 - bank-width : width in bytes of flash interface.
 
-Optional properties:
-- Subnode partition map from mtd flash binding
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
diff --git a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt b/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt
index ef66ddd..1889a4d 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt
@@ -3,6 +3,9 @@
 Required properties:
 - compatible : "atmel,<model>", "atmel,<series>", "atmel,dataflash".
 
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
 Example:
 
 flash at 1 {
diff --git a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
index 00f1f54..fce4894 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
@@ -19,6 +19,10 @@ Optional properties:
 	read registers (tR). Required if property "gpios" is not used
 	(R/B# pins not connected).
 
+Each flash chip described may optionally contain additional sub-nodes
+describing partitions of the address space. See partition.txt for more
+detail.
+
 Examples:
 
 upm at 1,0 {
diff --git a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
index 719f4dc..36ef07d 100644
--- a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
@@ -25,6 +25,9 @@ Optional properties:
   GPIO state and before and after command byte writes, this register will be
   read to ensure that the GPIO accesses have completed.
 
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
 Examples:
 
 gpio-nand at 1,0 {
diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
index 80152cb..a63c2bd7 100644
--- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
@@ -23,27 +23,8 @@ are defined:
  - vendor-id : Contains the flash chip's vendor id (1 byte).
  - device-id : Contains the flash chip's device id (1 byte).
 
-In addition to the information on the mtd bank itself, the
-device tree may optionally contain additional information
-describing partitions of the address space.  This can be
-used on platforms which have strong conventions about which
-portions of a flash are used for what purposes, but which don't
-use an on-flash partition table such as RedBoot.
-
-Each partition is represented as a sub-node of the mtd device.
-Each node's name represents the name of the corresponding
-partition of the mtd device.
-
-Flash partitions
- - reg : The partition's offset and size within the mtd bank.
- - label : (optional) The label / name for this partition.
-   If omitted, the label is taken from the node name (excluding
-   the unit address).
- - read-only : (optional) This parameter, if present, is a hint to
-   Linux that this partition should only be mounted
-   read-only.  This is usually used for flash partitions
-   containing early-boot firmware images or data which should not
-   be clobbered.
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
index 22c7438..d606009 100644
--- a/Documentation/devicetree/bindings/mtd/orion-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/orion-nand.txt
@@ -11,6 +11,9 @@ Optional properties:
 - bank-width :
 - chip-delay :
 
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
 Examples:
 
 nand at f4000000 {
diff --git a/Documentation/devicetree/bindings/mtd/partition.txt b/Documentation/devicetree/bindings/mtd/partition.txt
new file mode 100644
index 0000000..f114ce1
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/partition.txt
@@ -0,0 +1,38 @@
+Representing flash partitions in devicetree
+
+Partitions can be represented by sub-nodes of an mtd device. This can be used
+on platforms which have strong conventions about which portions of a flash are
+used for what purposes, but which don't use an on-flash partition table such
+as RedBoot.
+
+#address-cells & #size-cells must both be present in the mtd device and be
+equal to 1.
+
+Required properties:
+- reg : The partition's offset and size within the mtd bank.
+
+Optional properties:
+- label : The label / name for this partition.  If omitted, the label is taken
+  from the node name (excluding the unit address).
+- read-only : This parameter, if present, is a hint to Linux that this
+  partition should only be mounted read-only. This is usually used for flash
+  partitions containing early-boot firmware images or data which should not be
+  clobbered.
+
+Examples:
+
+
+flash at 0 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition at 0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+		read-only;
+	};
+
+	uimage at 100000 {
+		reg = <0x0100000 0x200000>;
+	};
+];
-- 
1.7.9.1



From jm at lentin.co.uk  Tue Mar 27 17:54:14 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Tue, 27 Mar 2012 22:54:14 +0100
Subject: [PATCH V3 4/5] ARM: kirkwood: Define DNS-320/DNS-325 NAND in fdt
In-Reply-To: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
References: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1332885255-8304-5-git-send-email-jm@lentin.co.uk>

Use devicetree to define NAND partitions. Use D-link partition scheme by
default, to be vaguely compatible with their userland.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Jason Cooper <jason at lakedaemon.net>
Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
 arch/arm/boot/dts/kirkwood-dns320.dts |   35 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-dns325.dts |   35 +++++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dnskw.c  |   31 -----------------------------
 3 files changed, 70 insertions(+), 31 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index 78c834f..dc09a73 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -25,5 +25,40 @@
 			clock-frequency = <166666667>;
 			status = "okay";
 		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x0100000 0x500000>;
+			};
+
+			partition at 600000 {
+				label = "ramdisk";
+				reg = <0x0600000 0x500000>;
+			};
+
+			partition at b00000 {
+				label = "image";
+				reg = <0x0b00000 0x6600000>;
+			};
+
+			partition at 7100000 {
+				label = "mini firmware";
+				reg = <0x7100000 0xa00000>;
+			};
+
+			partition at 7b00000 {
+				label = "config";
+				reg = <0x7b00000 0x500000>;
+			};
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index 23241ab..c2a5562 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -20,5 +20,40 @@
 			clock-frequency = <200000000>;
 			status = "okay";
 		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x0100000 0x500000>;
+			};
+
+			partition at 600000 {
+				label = "ramdisk";
+				reg = <0x0600000 0x500000>;
+			};
+
+			partition at b00000 {
+				label = "image";
+				reg = <0x0b00000 0x6600000>;
+			};
+
+			partition at 7100000 {
+				label = "mini firmware";
+				reg = <0x7100000 0xa00000>;
+			};
+
+			partition at 7b00000 {
+				label = "config";
+				reg = <0x7b00000 0x500000>;
+			};
+		};
 	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 7cb7f6a..dc4e80a 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -23,7 +23,6 @@
 #include <linux/gpio_keys.h>
 #include <linux/gpio-fan.h>
 #include <linux/leds.h>
-#include <linux/mtd/physmap.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,35 +31,6 @@
 #include "common.h"
 #include "mpp.h"
 
-static struct mtd_partition dnskw_nand_parts[] = {
-	{
-		.name		= "u-boot",
-		.offset		= 0,
-		.size		= SZ_1M,
-		.mask_flags	= MTD_WRITEABLE
-	}, {
-		.name		= "uImage",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	}, {
-		.name		= "ramdisk",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	}, {
-		.name		= "image",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 102 * SZ_1M
-	}, {
-		.name		= "mini firmware",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 10 * SZ_1M
-	}, {
-		.name		= "config",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	},
-};
-
 static struct mv643xx_eth_platform_data dnskw_ge00_data = {
 	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
 };
@@ -272,7 +242,6 @@ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
 void __init dnskw_init(void)
 {
 	kirkwood_mpp_conf(dnskw_mpp_config);
-	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
 
 	kirkwood_ehci_init();
 	kirkwood_ge00_init(&dnskw_ge00_data);
-- 
1.7.9.1



From jm at lentin.co.uk  Tue Mar 27 17:54:10 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Tue, 27 Mar 2012 22:54:10 +0100
Subject: [PATCH V3 0/5] Add support for DNS-320 and DNS-325 using devicetree
Message-ID: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>

Thanks again to Arnd, Jason & Scott. The differences here are fairly minor.
Apart from documentation, I'm guessing that the changes aren't significant
enough to revoke Acked-by, please flame me if I'm wrong!

Changes since v2:
* Split patches further, separating orion_nand and kirkwood changes
* dts renames: "bank-width", not "width". "okay", not "ok"
* Separate documentation out into separate patch, add references to
  partition.txt to all mtd bindings.

Changes since v1:
* Rebase against kirkwood_dt_for_3.4, removing premature devicetree ports.
* Move additions into a separate board-dnskw.c. It could be separated further
  into a board-dns320.c and board-dns325.c but it probably isn't worth it.
* s/marvell,/mrvl,/g
* Include an example dtb partition in documentation
* Copy structure of serial nodes to allow common options for NAND to be set
  in kirkwood.dtsi
* Simplifications in orion-nand.c

Jamie Lentin (5):
  ARM: kirkwood: Basic support for DNS-320 and DNS-325
  mtd: Add orion_nand devicetree bindings
  ARM: kirkwood: Allow nand to be configured via. devicetree
  ARM: kirkwood: Define DNS-320/DNS-325 NAND in fdt
  mtd: Move fdt partition documentation to a seperate file

 .../devicetree/bindings/mtd/arm-versatile.txt      |    4 +-
 .../devicetree/bindings/mtd/atmel-dataflash.txt    |    3 +
 .../devicetree/bindings/mtd/fsl-upm-nand.txt       |    4 +
 .../devicetree/bindings/mtd/gpio-control-nand.txt  |    3 +
 .../devicetree/bindings/mtd/mtd-physmap.txt        |   23 +--
 .../devicetree/bindings/mtd/orion-nand.txt         |   49 ++++
 .../devicetree/bindings/mtd/partition.txt          |   38 +++
 arch/arm/boot/dts/kirkwood-dns320.dts              |   64 +++++
 arch/arm/boot/dts/kirkwood-dns325.dts              |   59 +++++
 arch/arm/boot/dts/kirkwood.dtsi                    |   15 +-
 arch/arm/mach-kirkwood/Kconfig                     |   23 ++
 arch/arm/mach-kirkwood/Makefile                    |    1 +
 arch/arm/mach-kirkwood/Makefile.boot               |    2 +
 arch/arm/mach-kirkwood/board-dnskw.c               |  275 ++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c                  |    5 +
 arch/arm/mach-kirkwood/common.c                    |   12 +
 arch/arm/mach-kirkwood/common.h                    |    6 +
 drivers/mtd/nand/orion_nand.c                      |   35 +++-
 18 files changed, 595 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt
 create mode 100644 Documentation/devicetree/bindings/mtd/partition.txt
 create mode 100644 arch/arm/boot/dts/kirkwood-dns320.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-dns325.dts
 create mode 100644 arch/arm/mach-kirkwood/board-dnskw.c

-- 
1.7.9.1



From jm at lentin.co.uk  Tue Mar 27 17:54:11 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Tue, 27 Mar 2012 22:54:11 +0100
Subject: [PATCH V3 1/5] ARM: kirkwood: Basic support for DNS-320 and DNS-325
In-Reply-To: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
References: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1332885255-8304-2-git-send-email-jm@lentin.co.uk>

Add support for the DNS-320 and DNS-325. Describe as much as currently possible
in the devicetree files, create a board-dnskw.c for everything else.

Use IEEE-compliant "okay", rather than "ok"

Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Jason Cooper <jason at lakedaemon.net>
Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
 arch/arm/boot/dts/kirkwood-dns320.dts |   29 +++
 arch/arm/boot/dts/kirkwood-dns325.dts |   24 +++
 arch/arm/mach-kirkwood/Kconfig        |   23 +++
 arch/arm/mach-kirkwood/Makefile       |    1 +
 arch/arm/mach-kirkwood/Makefile.boot  |    2 +
 arch/arm/mach-kirkwood/board-dnskw.c  |  306 +++++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dt.c     |    5 +
 arch/arm/mach-kirkwood/common.h       |    6 +
 8 files changed, 396 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/kirkwood-dns320.dts
 create mode 100644 arch/arm/boot/dts/kirkwood-dns325.dts
 create mode 100644 arch/arm/mach-kirkwood/board-dnskw.c

diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
new file mode 100644
index 0000000..78c834f
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "D-Link DNS-320 NAS (Rev A1)";
+	compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		serial at 12000 {
+			clock-frequency = <166666667>;
+			status = "okay";
+		};
+
+		serial at 12100 {
+			clock-frequency = <166666667>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
new file mode 100644
index 0000000..23241ab
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+	model = "D-Link DNS-325 NAS (Rev A1)";
+	compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200n8 earlyprintk";
+	};
+
+	ocp at f1000000 {
+		serial at 12000 {
+			clock-frequency = <200000000>;
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 90ceab7..d594b6e 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -58,6 +58,29 @@ config MACH_DREAMPLUG_DT
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell DreamPlug (Flattened Device Tree).
 
+config MACH_DNSKW_DT
+        bool
+
+config MACH_DNS320_DT
+	bool "D-Link DNS-320 (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	select MACH_DNSKW_DT
+	select CONFIG_MTD_OF_PARTS
+	select CONFIG_SERIAL_OF_PLATFORM
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  D-Link DNS-320 NAS, using Flattened Device Tree.
+
+config MACH_DNS325_DT
+	bool "D-Link DNS-325 (Flattened Device Tree)"
+	select ARCH_KIRKWOOD_DT
+	select MACH_DNSKW_DT
+	select CONFIG_MTD_OF_PARTS
+	select CONFIG_SERIAL_OF_PLATFORM
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  D-Link DNS-325 NAS, using Flattened Device Tree.
+
 config MACH_TS219
 	bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
 	help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e299a95..b092af5 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_T5325)		+= t5325-setup.o
 obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)		+= board-dt.o
 obj-$(CONFIG_MACH_DREAMPLUG_DT)		+= board-dreamplug.o
+obj-$(CONFIG_MACH_DNSKW_DT)		+= board-dnskw.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 16f9385..9c5e45f 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -3,3 +3,5 @@ params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
 
 dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
+dtb-$(CONFIG_MACH_DNS320_DT) += kirkwood-dns320.dtb
+dtb-$(CONFIG_MACH_DNS325_DT) += kirkwood-dns325.dtb
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
new file mode 100644
index 0000000..7cb7f6a
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright 2012 (C), Jamie Lentin <jm at lentin.co.uk>
+ *
+ * arch/arm/mach-kirkwood/board-dnskw.c
+ *
+ * D-link DNS-320 & DNS-325 NAS Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio-fan.h>
+#include <linux/leds.h>
+#include <linux/mtd/physmap.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mtd_partition dnskw_nand_parts[] = {
+	{
+		.name		= "u-boot",
+		.offset		= 0,
+		.size		= SZ_1M,
+		.mask_flags	= MTD_WRITEABLE
+	}, {
+		.name		= "uImage",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 5 * SZ_1M
+	}, {
+		.name		= "ramdisk",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 5 * SZ_1M
+	}, {
+		.name		= "image",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 102 * SZ_1M
+	}, {
+		.name		= "mini firmware",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 10 * SZ_1M
+	}, {
+		.name		= "config",
+		.offset		= MTDPART_OFS_NXTBLK,
+		.size		= 5 * SZ_1M
+	},
+};
+
+static struct mv643xx_eth_platform_data dnskw_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
+};
+
+static struct mv_sata_platform_data dnskw_sata_data = {
+	.n_ports	= 2,
+};
+
+static unsigned int dnskw_mpp_config[] __initdata = {
+	MPP13_UART1_TXD,	/* Custom ... */
+	MPP14_UART1_RXD,	/* ... Controller (DNS-320 only) */
+	MPP20_SATA1_ACTn,	/* LED: White Right HDD */
+	MPP21_SATA0_ACTn,	/* LED: White Left HDD */
+	MPP24_GPIO,
+	MPP25_GPIO,
+	MPP26_GPIO,	/* LED: Power */
+	MPP27_GPIO,	/* LED: Red Right HDD */
+	MPP28_GPIO,	/* LED: Red Left HDD */
+	MPP29_GPIO,	/* LED: Red USB (DNS-325 only) */
+	MPP30_GPIO,
+	MPP31_GPIO,
+	MPP32_GPIO,
+	MPP33_GPO,
+	MPP34_GPIO,	/* Button: Front power */
+	MPP35_GPIO,	/* LED: Red USB (DNS-320 only) */
+	MPP36_GPIO,	/* Power: Turn off board */
+	MPP37_GPIO,	/* Power: Turn back on after power failure */
+	MPP38_GPIO,
+	MPP39_GPIO,	/* Power: SATA0 */
+	MPP40_GPIO,	/* Power: SATA1 */
+	MPP41_GPIO,
+	MPP42_GPIO,
+	MPP43_GPIO,	/* LED: White USB */
+	MPP44_GPIO,	/* Fan: Tachometer Pin */
+	MPP45_GPIO,	/* Fan: high speed */
+	MPP46_GPIO,	/* Fan: low speed */
+	MPP47_GPIO,	/* Button: Back unmount */
+	MPP48_GPIO,	/* Button: Back reset */
+	MPP49_GPIO,	/* Pin of unused U5 (DNS-320 only) */
+	0
+};
+
+static struct gpio_led dns325_led_pins[] = {
+	{
+		.name	= "dns325:white:power",
+		.gpio	= 26,
+		.active_low = 1,
+		.default_trigger = "default-on",
+	},
+	{
+		.name	= "dns325:white:usb",
+		.gpio	= 43,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns325:red:l_hdd",
+		.gpio	= 28,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns325:red:r_hdd",
+		.gpio	= 27,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns325:red:usb",
+		.gpio	= 29,
+		.active_low = 1,
+	},
+};
+
+static struct gpio_led_platform_data dns325_led_data = {
+	.num_leds	= ARRAY_SIZE(dns325_led_pins),
+	.leds		= dns325_led_pins,
+};
+
+static struct platform_device dns325_led_device = {
+	.name		= "leds-gpio",
+	.id		= -1,
+	.dev		= {
+		.platform_data	= &dns325_led_data,
+	},
+};
+
+static struct gpio_led dns320_led_pins[] = {
+	{
+		.name	= "dns320:blue:power",
+		.gpio	= 26,
+		.active_low = 1,
+		.default_trigger = "default-on",
+	},
+	{
+		.name	= "dns320:blue:usb",
+		.gpio	= 43,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns320:orange:l_hdd",
+		.gpio	= 28,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns320:orange:r_hdd",
+		.gpio	= 27,
+		.active_low = 1,
+	},
+	{
+		.name	= "dns320:orange:usb",
+		.gpio	= 35,
+		.active_low = 1,
+	},
+};
+
+static struct gpio_led_platform_data dns320_led_data = {
+	.num_leds	= ARRAY_SIZE(dns320_led_pins),
+	.leds		= dns320_led_pins,
+};
+
+static struct platform_device dns320_led_device = {
+	.name		= "leds-gpio",
+	.id		= -1,
+	.dev		= {
+		.platform_data	= &dns320_led_data,
+	},
+};
+
+static struct i2c_board_info dns325_i2c_board_info[] __initdata = {
+	{
+		I2C_BOARD_INFO("lm75", 0x48),
+	},
+	/* Something at 0x0c also */
+};
+
+static struct gpio_keys_button dnskw_button_pins[] = {
+	{
+		.code		= KEY_POWER,
+		.gpio		= 34,
+		.desc		= "Power button",
+		.active_low	= 1,
+	},
+	{
+		.code		= KEY_EJECTCD,
+		.gpio		= 47,
+		.desc		= "USB unmount button",
+		.active_low	= 1,
+	},
+	{
+		.code		= KEY_RESTART,
+		.gpio		= 48,
+		.desc		= "Reset button",
+		.active_low	= 1,
+	},
+};
+
+static struct gpio_keys_platform_data dnskw_button_data = {
+	.buttons	= dnskw_button_pins,
+	.nbuttons	= ARRAY_SIZE(dnskw_button_pins),
+};
+
+static struct platform_device dnskw_button_device = {
+	.name		= "gpio-keys",
+	.id		= -1,
+	.num_resources	= 0,
+	.dev		= {
+		.platform_data	= &dnskw_button_data,
+	}
+};
+
+/* Fan: ADDA AD045HB-G73 40mm 6000rpm at 5v */
+static struct gpio_fan_speed dnskw_fan_speed[] = {
+	{    0,  0 },
+	{ 3000,	 1 },
+	{ 6000,	 2 },
+};
+static unsigned dnskw_fan_pins[] = {46, 45};
+
+static struct gpio_fan_platform_data dnskw_fan_data = {
+	.num_ctrl	= ARRAY_SIZE(dnskw_fan_pins),
+	.ctrl		= dnskw_fan_pins,
+	.num_speed	= ARRAY_SIZE(dnskw_fan_speed),
+	.speed		= dnskw_fan_speed,
+};
+
+static struct platform_device dnskw_fan_device = {
+	.name	= "gpio-fan",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &dnskw_fan_data,
+	},
+};
+
+static void dnskw_power_off(void)
+{
+	gpio_set_value(36, 1);
+}
+
+/* Register any GPIO for output and set the value */
+static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
+{
+	if (gpio_request(gpio, name) == 0 &&
+	    gpio_direction_output(gpio, 0) == 0) {
+		gpio_set_value(gpio, def);
+		if (gpio_export(gpio, 0) != 0)
+			pr_err("dnskw: Failed to export GPIO %s\n", name);
+	} else
+		pr_err("dnskw: Failed to register %s\n", name);
+}
+
+void __init dnskw_init(void)
+{
+	kirkwood_mpp_conf(dnskw_mpp_config);
+	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
+
+	kirkwood_ehci_init();
+	kirkwood_ge00_init(&dnskw_ge00_data);
+	kirkwood_sata_init(&dnskw_sata_data);
+	kirkwood_i2c_init();
+
+	platform_device_register(&dnskw_button_device);
+	platform_device_register(&dnskw_fan_device);
+
+	if (of_machine_is_compatible("dlink,dns-325")) {
+		i2c_register_board_info(0, dns325_i2c_board_info,
+					ARRAY_SIZE(dns325_i2c_board_info));
+		platform_device_register(&dns325_led_device);
+
+	} else if (of_machine_is_compatible("dlink,dns-320"))
+		platform_device_register(&dns320_led_device);
+
+	/* Register power-off GPIO. */
+	if (gpio_request(36, "dnskw:power:off") == 0
+	    && gpio_direction_output(36, 0) == 0)
+		pm_power_off = dnskw_power_off;
+	else
+		pr_err("dnskw: failed to configure power-off GPIO\n");
+
+	/* Ensure power is supplied to both HDDs */
+	dnskw_gpio_register(39, "dnskw:power:sata0", 1);
+	dnskw_gpio_register(40, "dnskw:power:sata1", 1);
+
+	/* Set NAS to turn back on after a power failure */
+	dnskw_gpio_register(37, "dnskw:power:recover", 1);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 1c672d9..eadc4d7 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -55,11 +55,16 @@ static void __init kirkwood_dt_init(void)
 	if (of_machine_is_compatible("globalscale,dreamplug"))
 		dreamplug_init();
 
+	if (of_machine_is_compatible("dlink,dns-kirkwood"))
+		dnskw_init();
+
 	of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
 }
 
 static const char *kirkwood_dt_board_compat[] = {
 	"globalscale,dreamplug",
+	"dlink,dns-320",
+	"dlink,dns-325",
 	NULL
 };
 
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index fa8e768..8c8c733 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -58,6 +58,12 @@ void dreamplug_init(void);
 static inline void dreamplug_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_DNSKW_DT
+void dnskw_init(void);
+#else
+static inline void dnskw_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
-- 
1.7.9.1



From olof at lixom.net  Tue Mar 27 18:26:15 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 27 Mar 2012 15:26:15 -0700
Subject: [GIT PULL 06/09] ARM: board specific updates
In-Reply-To: <1332626568-17812-9-git-send-email-arnd@arndb.de>
References: <1332626568-17812-1-git-send-email-arnd@arndb.de>
 <1332626568-17812-9-git-send-email-arnd@arndb.de>
Message-ID: <CAOesGMhhS4Hat1mzvz+rxdwwPXnNx9e6G7pQR1JNYXmhL_BLUQ@mail.gmail.com>

Linus,

On Sat, Mar 24, 2012 at 3:02 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> These changes are all specific to one board only. We're trying to keep
> the number of board files low, but generally board level updates are
> ok on platforms that are working on moving towards DT based probing,
> which will eventually lead to removing them.
>
> The board-ams-delta.c board file gets a conflict between the removal of
> ams_delta_config and the addition of a lot of other data. The Kconfig
> file has two changes in the same line, and in exynos, the power domain
> cleanup conflicts with the addition of the image sensor device.
>
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
>
> The following changes since commit "abd43e4 Merge branch 'next/boards'
> into for-next", leading up to commit " b9e1122 Merge tag 'asoc-3.4'
> of git://git.kernel.org/pub/scm", are available in
>
> git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git tags/boards

The topmost commit on the branch had a mismerge causing compilation
failures on OMAP4 (arch/arm/mach-omap2/board-oamp4panda.c).

I've amended in the fix with the top merge commit to fix it, updated
the tag and pushed out the new branch and tag to the repo. The
diffstat should be identical, but the signature is obviously from me,
not Arnd.


-Olof


From skannan at codeaurora.org  Tue Mar 27 18:27:35 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 27 Mar 2012 15:27:35 -0700
Subject: [PATCH 2/2] clk: Move init fields from clk to clk_hw
In-Reply-To: <CAJOA=zOq=kYfZUEnnQT_D4w=Kpp5n7R=k9oOCrxF59P5W-nw-w@mail.gmail.com>
References: <CAJOA=zN2cSSpM92oRnW0RyU_ZzyoQ=jthc-fAkf-P3z37uWt7w@mail.gmail.com>
 <1332214706-675-1-git-send-email-skannan@codeaurora.org>
 <1332214706-675-2-git-send-email-skannan@codeaurora.org>
 <20120320072018.GC32469@S2101-09.ap.freescale.net>
 <cbd6490459b9fd68875fec4a7c7de073.squirrel@www.codeaurora.org>
 <20120320094031.GI3852@pengutronix.de>
 <20120320141811.GF32469@S2101-09.ap.freescale.net>
 <20120320181050.GN3852@pengutronix.de> <4F68E34A.70207@codeaurora.org>
 <20120320231242.GP3852@pengutronix.de>
 <CAJOA=zOGTW7OqACWgJQW6HSPLVev+apdNhv4vNXjHTcp=7N+uQ@mail.gmail.com>
 <4F694484.1030706@codeaurora.org> <4F714397.6080608@codeaurora.org>
 <CAJOA=zOq=kYfZUEnnQT_D4w=Kpp5n7R=k9oOCrxF59P5W-nw-w@mail.gmail.com>
Message-ID: <4F723ED7.7010800@codeaurora.org>

On 03/27/2012 11:49 AM, Turquette, Mike wrote:
> On Mon, Mar 26, 2012 at 9:35 PM, Saravana Kannan<skannan at codeaurora.org>  wrote:
>> Mike,
>>
>> (*nudge*) (*nudge*)
>
> Hi Saravana,
>
> I spent some time mulling over the ideas this weekend and I agree that
> we have 3 types of data, so having the three structs makes some sense.
>   I'm checking this patch out more earnestly today.
>

Thanks Mike. The patch has a few things to clean up. I would be glad to 
send out a cleaned up patch once we have an approximate consensus on 
what to copy/not copy.

Thanks,
Saravana


From olof at lixom.net  Tue Mar 27 19:02:56 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 27 Mar 2012 16:02:56 -0700
Subject: [GIT PULL] pxa io.h clean-up fixes
In-Reply-To: <4F6FC82C.2040303@gmail.com>
References: <4F6FC82C.2040303@gmail.com>
Message-ID: <CAOesGMiCb3_kgwU6n-RcSQfJfic0bCzPtm651uuqHwG0tN=f4w@mail.gmail.com>

Hi,

On Sun, Mar 25, 2012 at 6:36 PM, Rob Herring <robherring2 at gmail.com> wrote:

> The following changes since commit a2a47ca36642e3995e982957bc42678cf11ca6ac:
>
> ?ARM: __io abuse cleanup (2012-03-13 21:25:21 -0500)
>
> are available in the git repository at:
> ?git://sources.calxeda.com/kernel/linux.git io-cleanup-for-3.4

Thanks, pulled into next/cleanup2 (same as previous pull of the same
branch) and will be sent in the second set pulls for 3.4.


-Olof


From mturquette at ti.com  Tue Mar 27 19:17:37 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 27 Mar 2012 16:17:37 -0700
Subject: [PATCH 09/10] clk: dynamically allocate parent_names basic clk
 registration
In-Reply-To: <20120327194010.GJ29317@pengutronix.de>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-10-git-send-email-shawn.guo@linaro.org>
 <20120327085514.GI29317@pengutronix.de>
 <20120327125122.GB3719@S2101-09.ap.freescale.net>
 <20120327194010.GJ29317@pengutronix.de>
Message-ID: <CAJOA=zNWvfWX8Qc-f758O1GbO41T00+7umjgk1_N1Tu_KGtwgw@mail.gmail.com>

On Tue, Mar 27, 2012 at 12:40 PM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> On Tue, Mar 27, 2012 at 08:51:24PM +0800, Shawn Guo wrote:
>> On Tue, Mar 27, 2012 at 10:55:14AM +0200, Sascha Hauer wrote:
>> > On Tue, Mar 27, 2012 at 03:23:28PM +0800, Shawn Guo wrote:
>> > > It's not necessary to have "char *parent[1]" carried in struct clk_gate
>> > > and clk_divider. ?Instead, it can be dynamically allocated in
>> > > registration function, just like what clk_register_fixed_rate does.
>> >
>> > I patched it the way it is to get rid of the additional malloc which
>> > seemed unnecessary. Maybe the real question is whether the core should
>> > duplicate the parent strings instead of the basic clock types.
>> >
>> If we can ensure the parent strings will only be used during
>> clk_register call, we do not need to duplicate the parent strings.
>>
>> But right now the parent strings is used not only in clk_register call
>> but also __clk_set_parent for finding parent index in case the search
>> on cached parent points fails. ?I guess Mike has a good reason for that.

I'd like to think my reasons are good ;-)

The common clk framework pulls together clock data from many sources,
and we can never assume that the tree of struct clk's is "complete".
For example an on-SoC multiplexer clock might have one input from an
external PMIC.  It is conceivable that clock data / common clk support
for that PMIC isn't yet merged.  Should that prevent the on-SoC mux
clock from using that source via clk_set_parent?  Absolutely not.
That is why the parent_names arrays are necessary.  They represent
"complete" data even in the absence of actual clock data.  Using only
the index of the array the .set_rate callback should be able to do the
[register write | i2c command | whatever] in order to switch to the
PMIC source.  The rate will be unknown, but at least the operation is
possible.

> Probably. That's why I suggest to copy the strings in the framework.
> Then we do not have to duplicate the code to copy the strings and also
> make sure that the core works on its own strings.

Copying the strings in the fwk is sensible.  I'll throw together a
patch which takes in the const char *parent_name and passes that to
clk_register directly, which builds up the char **parent_names itself.

Regards,
Mike


From mturquette at ti.com  Tue Mar 27 19:28:19 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 27 Mar 2012 16:28:19 -0700
Subject: [PATCH 05/10] clk: align error return of basic clks registeration
In-Reply-To: <1332833009-4121-6-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-6-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAJOA=zOVVnq8DgfAzqnC+XrGtSGU7SLF+8Qwn3L76EfwqOGzNw@mail.gmail.com>

On Tue, Mar 27, 2012 at 12:23 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> clk_register_gate and clk_register_divider return NULL for error,
> which is aligned with clk_register function. ?But clk_register_mux
> and clk_register_fixed_rate return ERR_PTR. ?Change them to return
> NULL for better aligning with other registeration functions.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Thanks for the patch Shawn, but this is actually the opposite
direction that I want to go.  In light of the other thread with
Saravana and Russell on a similar topic, I'd like to make sure that
the driver-facing functions clearly return -EERROR during failure.
I've lined up a patch for the same on my side.

Regards,
Mike

> ---
> ?drivers/clk/clk-fixed-rate.c | ? ?2 +-
> ?drivers/clk/clk-mux.c ? ? ? ?| ? ?2 +-
> ?2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
> index 027e477..d268439 100644
> --- a/drivers/clk/clk-fixed-rate.c
> +++ b/drivers/clk/clk-fixed-rate.c
> @@ -50,7 +50,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
>
> ? ? ? ?if (!fixed) {
> ? ? ? ? ? ? ? ?pr_err("%s: could not allocate fixed clk\n", __func__);
> - ? ? ? ? ? ? ? return ERR_PTR(-ENOMEM);
> + ? ? ? ? ? ? ? return NULL;
> ? ? ? ?}
>
> ? ? ? ?/* struct clk_fixed_rate assignments */
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index 5424488..19f3116 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -99,7 +99,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
>
> ? ? ? ?if (!mux) {
> ? ? ? ? ? ? ? ?pr_err("%s: could not allocate mux clk\n", __func__);
> - ? ? ? ? ? ? ? return ERR_PTR(-ENOMEM);
> + ? ? ? ? ? ? ? return NULL;
> ? ? ? ?}
>
> ? ? ? ?/* struct clk_mux assignments */
> --
> 1.7.5.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From mturquette at ti.com  Tue Mar 27 19:29:48 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 27 Mar 2012 16:29:48 -0700
Subject: [PATCH 03/10] clk: add "const" for clk_ops of basic clks
In-Reply-To: <1332833009-4121-4-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-4-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAJOA=zOp1sgTbYmWiaiNBo4PtCqAgboKOFLMHiWfz9yYfsUtzA@mail.gmail.com>

On Tue, Mar 27, 2012 at 12:23 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> The clk_ops of basic clks should have "const" to match the definition
> in "struct clk" and clk_register prototype.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Thanks for the patch.  Will take into my fixes branch.

Regards,
Mike

> ---
> ?drivers/clk/clk-divider.c ? ?| ? ?2 +-
> ?drivers/clk/clk-fixed-rate.c | ? ?2 +-
> ?drivers/clk/clk-gate.c ? ? ? | ? ?2 +-
> ?drivers/clk/clk-mux.c ? ? ? ?| ? ?2 +-
> ?include/linux/clk-private.h ?| ? ?8 ++++----
> ?5 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 231cd6e..b1c4b02 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -146,7 +146,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
> ? ? ? ?return 0;
> ?}
>
> -struct clk_ops clk_divider_ops = {
> +const struct clk_ops clk_divider_ops = {
> ? ? ? ?.recalc_rate = clk_divider_recalc_rate,
> ? ? ? ?.round_rate = clk_divider_round_rate,
> ? ? ? ?.set_rate = clk_divider_set_rate,
> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
> index 651b06f..027e477 100644
> --- a/drivers/clk/clk-fixed-rate.c
> +++ b/drivers/clk/clk-fixed-rate.c
> @@ -33,7 +33,7 @@ static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
> ? ? ? ?return to_clk_fixed_rate(hw)->fixed_rate;
> ?}
>
> -struct clk_ops clk_fixed_rate_ops = {
> +const struct clk_ops clk_fixed_rate_ops = {
> ? ? ? ?.recalc_rate = clk_fixed_rate_recalc_rate,
> ?};
> ?EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
> diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
> index b688f47..fe2ff9e 100644
> --- a/drivers/clk/clk-gate.c
> +++ b/drivers/clk/clk-gate.c
> @@ -98,7 +98,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
> ? ? ? ?return reg ? 1 : 0;
> ?}
>
> -struct clk_ops clk_gate_ops = {
> +const struct clk_ops clk_gate_ops = {
> ? ? ? ?.enable = clk_gate_enable,
> ? ? ? ?.disable = clk_gate_disable,
> ? ? ? ?.is_enabled = clk_gate_is_enabled,
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index 45cad61..5424488 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -82,7 +82,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
> ? ? ? ?return 0;
> ?}
>
> -struct clk_ops clk_mux_ops = {
> +const struct clk_ops clk_mux_ops = {
> ? ? ? ?.get_parent = clk_mux_get_parent,
> ? ? ? ?.set_parent = clk_mux_set_parent,
> ?};
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> index 5e4312b..5f4ccd7 100644
> --- a/include/linux/clk-private.h
> +++ b/include/linux/clk-private.h
> @@ -55,7 +55,7 @@ struct clk {
> ?* alternative macro for static initialization
> ?*/
>
> -extern struct clk_ops clk_fixed_rate_ops;
> +extern const struct clk_ops clk_fixed_rate_ops;
>
> ?#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_fixed_rate_flags) ? ? ? ? ? ? ?\
> @@ -78,7 +78,7 @@ extern struct clk_ops clk_fixed_rate_ops;
> ? ? ? ? ? ? ? ?.flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?};
>
> -extern struct clk_ops clk_gate_ops;
> +extern const struct clk_ops clk_gate_ops;
>
> ?#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_flags, _reg, _bit_idx, ? ? ? ? \
> @@ -110,7 +110,7 @@ extern struct clk_ops clk_gate_ops;
> ? ? ? ? ? ? ? ?.flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?};
>
> -extern struct clk_ops clk_divider_ops;
> +extern const struct clk_ops clk_divider_ops;
>
> ?#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, ? \
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_flags, _reg, _shift, _width, ? \
> @@ -143,7 +143,7 @@ extern struct clk_ops clk_divider_ops;
> ? ? ? ? ? ? ? ?.flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?};
>
> -extern struct clk_ops clk_mux_ops;
> +extern const struct clk_ops clk_mux_ops;
>
> ?#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_reg, _shift, _width, ? ? ? ? ? \
> --
> 1.7.5.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From mturquette at ti.com  Tue Mar 27 19:31:17 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 27 Mar 2012 16:31:17 -0700
Subject: [PATCH 01/10] clk: use kzalloc in clk_register_mux
In-Reply-To: <1332833009-4121-2-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAJOA=zOGdjZ_-U8AuDJG2k8SRCfcf=8aUg__+A-fWSz4FOSStA@mail.gmail.com>

On Tue, Mar 27, 2012 at 12:23 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> Change clk_register_mux to use kzalloc, just like what all other basic
> clk registration functions do.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Thanks for the patch.  Will take into my fixes branch.

Regards,
Mike

> ---
> ?drivers/clk/clk-mux.c | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index c71ad1f..50e0595 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -97,7 +97,7 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
> ?{
> ? ? ? ?struct clk_mux *mux;
>
> - ? ? ? mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL);
> + ? ? ? mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
>
> ? ? ? ?if (!mux) {
> ? ? ? ? ? ? ? ?pr_err("%s: could not allocate mux clk\n", __func__);
> --
> 1.7.5.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From mturquette at ti.com  Tue Mar 27 19:36:22 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 27 Mar 2012 16:36:22 -0700
Subject: [PATCH 06/10] clk: fixed-rate: Don't open code kstrdup()
In-Reply-To: <1332833009-4121-7-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-7-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAJOA=zOsrNV66bB0zjQ_gOkcpzfSWeTMDpP_W=Pn2JfhG_MgeQ@mail.gmail.com>

On Tue, Mar 27, 2012 at 12:23 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> From: Mark Brown <broonie at opensource.wolfsonmicro.com>
>
> Save a little code by using the library function.
>
> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

Shawn,  thanks for reposting.

Mark, thanks for the patch.  I wrote a near-identical patch in my
branch, but it returns -EERROR instead of just returning NULL on
failure so I'll stick with my version.

Thanks,
Mike

> ---
> ?drivers/clk/clk-fixed-rate.c | ? ?7 +------
> ?1 files changed, 1 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
> index d268439..1f87a03 100644
> --- a/drivers/clk/clk-fixed-rate.c
> +++ b/drivers/clk/clk-fixed-rate.c
> @@ -44,7 +44,6 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> ?{
> ? ? ? ?struct clk_fixed_rate *fixed;
> ? ? ? ?char **parent_names = NULL;
> - ? ? ? u8 len;
>
> ? ? ? ?fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
>
> @@ -62,14 +61,10 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> ? ? ? ? ? ? ? ?if (! parent_names)
> ? ? ? ? ? ? ? ? ? ? ? ?goto out;
>
> - ? ? ? ? ? ? ? len = sizeof(char) * strlen(parent_name);
> -
> - ? ? ? ? ? ? ? parent_names[0] = kmalloc(len, GFP_KERNEL);
> + ? ? ? ? ? ? ? parent_names[0] = kstrdup(parent_name, GFP_KERNEL);
>
> ? ? ? ? ? ? ? ?if (!parent_names[0])
> ? ? ? ? ? ? ? ? ? ? ? ?goto out;
> -
> - ? ? ? ? ? ? ? strncpy(parent_names[0], parent_name, len);
> ? ? ? ?}
>
> ?out:
> --
> 1.7.5.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From akpm at linux-foundation.org  Tue Mar 27 19:47:59 2012
From: akpm at linux-foundation.org (Andrew Morton)
Date: Tue, 27 Mar 2012 16:47:59 -0700
Subject: [V2 2/4] rtc: fix 88pm860x rtc irq enable callback
In-Reply-To: <1331259874-26503-1-git-send-email-jtzhou@marvell.com>
References: <1329997662-2931-1-git-send-email-jtzhou@marvell.com>
 <1331259874-26503-1-git-send-email-jtzhou@marvell.com>
Message-ID: <20120327164759.ec04c62e.akpm@linux-foundation.org>

On Fri,  9 Mar 2012 10:24:34 +0800
"Jett.Zhou" <jtzhou at marvell.com> wrote:

> According to 88pm860x spec, rtc alarm irq enable control is bit3 for
> RTC_ALARM_EN, so fix it.
> 
> Signed-off-by: Jett.Zhou <jtzhou at marvell.com>
> ---
>  drivers/rtc/rtc-88pm860x.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/rtc/rtc-88pm860x.c b/drivers/rtc/rtc-88pm860x.c
> index f04761e..8b72b4c 100644
> --- a/drivers/rtc/rtc-88pm860x.c
> +++ b/drivers/rtc/rtc-88pm860x.c
> @@ -72,9 +72,9 @@ static int pm860x_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
>  	struct pm860x_rtc_info *info = dev_get_drvdata(dev);
>  
>  	if (enabled)
> -		pm860x_set_bits(info->i2c, PM8607_RTC1, ALARM, ALARM);
> +		pm860x_set_bits(info->i2c, PM8607_RTC1, ALARM_EN, ALARM_EN);
>  	else
> -		pm860x_set_bits(info->i2c, PM8607_RTC1, ALARM, 0);
> +		pm860x_set_bits(info->i2c, PM8607_RTC1, ALARM_EN, 0);
>  	return 0;
>  }

It's surprising that the driver has been in-tree for a year and nobody
has noticed this bug.  This makes me wonder if the fix is wrong.

Has the patch been runtime tested?


From benh at kernel.crashing.org  Tue Mar 27 20:01:14 2012
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Wed, 28 Mar 2012 11:01:14 +1100
Subject: [PATCH v2.1 01/10] cpu: Introduce clear_tasks_mm_cpumask() helper
In-Reply-To: <20120325174210.GA23605@redhat.com>
References: <20120324102609.GA28356@lizard> <20120324102751.GA29067@lizard>
 <1332593021.16159.27.camel@twins> <20120324164316.GB3640@lizard>
 <20120325174210.GA23605@redhat.com>
Message-ID: <1332892874.2882.66.camel@pasglop>

On Sun, 2012-03-25 at 19:42 +0200, Oleg Nesterov wrote:
> > Also, Per Peter Zijlstra's idea, now we don't grab tasklist_lock in
> > the new helper, instead we take the rcu read lock. We can do this
> > because the function is called after the cpu is taken down and
> marked
> > offline, so no new tasks will get this cpu set in their mm mask.
> 
> And only powerpc needs rcu_read_lock() and task_lock().
> 
> OTOH, I do not understand why powepc does this on CPU_DEAD...
> And probably CPU_UP_CANCELED doesn't need to clear mm_cpumask().
> 
> That said, personally I think these patches are fine, the common
> helper makes sense. 

Not strictly speaking a problem with this patch, but I was wondering...

Do we know for sure that the mmu context has been fully flushed out
before the unplug ? idle_task_exit() will do a context switch but in our
case that may not be enough.

Once the CPU is offline, tlb flushes won't hit it any more so it can get
out of sync (in some cases the offlining process is just some kind of
deep sleep loop that doesn't involve a TLB state loss).

Should we add a flush_tlb_mm of all those bits in that loop ? that would
be a tad expensive... we don't have a flush_tlb_all() as a generic kind
of accessors, but we could add something like that as a requirement for
ppc_md.cpu_die ?

Cheers,
Ben.




From boojin.kim at samsung.com  Tue Mar 27 20:19:49 2012
From: boojin.kim at samsung.com (Boojin Kim)
Date: Wed, 28 Mar 2012 09:19:49 +0900
Subject: [PATCH 2/2] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <20120327074039.GJ5611@n2100.arm.linux.org.uk>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <00d501cd0bb0$724ab260$56e01720$%kim@samsung.com>
 <20120327074039.GJ5611@n2100.arm.linux.org.uk>
Message-ID: <012d01cd0c78$7d2f19a0$778d4ce0$%kim@samsung.com>

Russell King wrote:
> Sent: Tuesday, March 27, 2012 4:41 PM
> To: Boojin Kim
> Cc: linux-arm-kernel at lists.infradead.org; 'Catalin Marinas'; 'Nicolas Pitre';
> kgene.kim at samsung.com
> Subject: Re: [PATCH 2/2] ARM: lib: use LDRD/STRD for data copy
>
> On Tue, Mar 27, 2012 at 09:27:52AM +0900, Boojin Kim wrote:
> > This patch uses LDRD/STRD that loads and stores data as DWORD unit.
> > It brings better performance than LDRM/STRM with cortex-a15.
>
> Why should I bother looking at this rubbish?  You've been told before
> that using ldrd and strd unconditionally is not acceptable.  Stop
> wasting peoples review time.
This patch brings better memcpy results on Cortex-a15.
Please see following result. I measured it on cortex-a15.
2nd line is default memcpy.
3rd line is memcpy using ldrd/strd with this patch.
4th line is memcpy using ldrd/strd and PLD optimization on my 1st patch.
===================================================================
Memcpy performance (unit: size: Bytes, results: MBps)
===================================================================
size		default	ldrd/strd	ldrd/strd + PLD opti
===================================================================
64		1245.615434	1565.004006		1565.004006
128		1743.861607	2393.535539		2491.230867
256		2199.46509	3212.376645		3487.723214
512		2569.901316	4137.976695		4479.644495
1024		2880.715339	4245.923913		5250.336022
2048		3623.608534	4752.128954		5365.728022
4096		4120.516878	5119.593709		5710.891813
8192		4431.366988	5126.312336		5440.45961
16384		4603.712434	5040.322581		5529.016277
32768		4559.381383	4712.002413		5238.893546
65536		3483.446661	3513.802215		3516.965843
131072		3495.623479	3498.460677		3506.31136
262144		3484.02921	3475.987876		3499.783013
524288		3427.662608	3430.037525		3454.637159
1048576	2263.903195	2225.9222		2458.911587
2097152	1732.182125	1703.940362		1833.96223
4194304	1713.663165	1708.351146		1781.780052
===================================================================
I think it brings meaningful results on cache boundary. So I tried it again.
And, I saw your review. So, I make this patch be effective on cortex-a15 only if machine selects it.
Thanks for your time and review :)




From boojin.kim at samsung.com  Tue Mar 27 20:28:54 2012
From: boojin.kim at samsung.com (Boojin Kim)
Date: Wed, 28 Mar 2012 09:28:54 +0900
Subject: [PATCH 1/2] ARM: lib: Add optimized memcpy with 64 byte pld size
In-Reply-To: <alpine.LFD.2.02.1203262231220.24151@xanadu.home>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <00cf01cd0bb0$4fa49c30$eeedd490$%kim@samsung.com>
 <alpine.LFD.2.02.1203262231220.24151@xanadu.home>
Message-ID: <013501cd0c79$c1e244e0$45a6cea0$%kim@samsung.com>

Nicolas wrote:

> This creates quite convoluted code.  If this is worth doing, we'll have
> to find a cleaner way to do this.
>
> Could you please provide performance measurement numbers with and
> without this patch, and similarly for the next patch?
>
> Did you try enabling the cache alignment code?  What performance
> difference if any did you see?
My patch brings about 10% better result on cache boundary.
64bytes PLD size makes the cache efficiency be higher on machines that has 64byte cache line.
And, Which one is convoluted code? Can you explain it more detail?
Thank you for  your review.

>
> > ---
> >  arch/arm/Kconfig             |    7 ++++++
> >  arch/arm/lib/copy_template.S |   44 +++++++++++++++++++++++++++++++++--------
> >  2 files changed, 42 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 8fec56d..ba306b3 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1132,6 +1132,13 @@ config ARM_NR_BANKS
> >  	default 16 if ARCH_EP93XX
> >  	default 8
> >
> > +config ARM_PLD_SIZE
> > +	int
> > +	default 64 if ARCH_EXYNOS5
> > +	default 32
> > +	help
> > +	  Configure preload size used on memcpy(). Select 64 for cortex-a15.
> > +
> >  config IWMMXT
> >  	bool "Enable iWMMXt support"
> >  	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
> > diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
> > index 805e3f8..7dc5b8c 100644
> > --- a/arch/arm/lib/copy_template.S
> > +++ b/arch/arm/lib/copy_template.S
> > @@ -66,6 +66,7 @@
> >   *	than one 32bit instruction in Thumb-2)
> >   */
> >
> > +#define PLDSIZE	(CONFIG_ARM_PLD_SIZE)
> >
> >  		enter	r4, lr
> >
> > @@ -90,19 +91,44 @@
> >  	CALGN(	add	pc, r4, ip		)
> >
> >  	PLD(	pld	[r1, #0]		)
> > -2:	PLD(	subs	r2, r2, #96		)
> > -	PLD(	pld	[r1, #28]		)
> > +
> > +#if (PLDSIZE == 64)
> > +2:	PLD(	cmp	r2, #32)
> > +	PLD(	blt	.32cpy)
> > +.64cpy:	PLD(	subs	r2, r2, #(PLDSIZE*3+32)	)
> > +	PLD(	pld	[r1, #PLDSIZE-4]	)
> >  	PLD(	blt	4f			)
> > -	PLD(	pld	[r1, #60]		)
> > -	PLD(	pld	[r1, #92]		)
> > +	PLD(	pld	[r1, #PLDSIZE*2-4]	)
> > +	PLD(	pld	[r1, #PLDSIZE*3-4]	)
> > +
> > +3:	PLD(	pld	[r1, #PLDSIZE*4-4]	)
> > +4:		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> > +		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> > +		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> > +		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> > +		subs	r2, r2, #PLDSIZE
> > +		bge	3b
> > +	PLD(	cmn	r2, #(PLDSIZE*3)	)
> > +	PLD(	bge	4b			)
> > +	PLD(	cmn	r2, #(PLDSIZE*4-32)	)
> > +	PLD(	blt	5f)
> > +.32cpy:		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> > +		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> > +#else
> > +2:	PLD(	subs	r2, r2, #(PLDSIZE*3)	)
> > +	PLD(	pld	[r1, #(PLDSIZE-4)]	)
> > +	PLD(	blt	4f			)
> > +	PLD(	pld	[r1, #(PLDSIZE*2-4)]	)
> > +	PLD(	pld	[r1, #(PLDSIZE*3-4)]	)
> >
> > -3:	PLD(	pld	[r1, #124]		)
> > -4:		ldr8w	r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> > -		subs	r2, r2, #32
> > -		str8w	r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> > +3:	PLD(	pld	[r1, #(PLDSIZE*4-4)]	)
> > +4:		ldr8w   r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> > +		subs	r2, r2, #PLDSIZE
> > +		str8w   r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
> >  		bge	3b
> > -	PLD(	cmn	r2, #96			)
> > +	PLD(	cmn	r2, #(PLDSIZE*3)	)
> >  	PLD(	bge	4b			)
> > +#endif
> >
> >  5:		ands	ip, r2, #28
> >  		rsb	ip, ip, #32
> > --
> > 1.7.1
> >
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel




From mturquette at ti.com  Tue Mar 27 20:31:45 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 27 Mar 2012 17:31:45 -0700
Subject: [PATCH 08/10] clk: fixed-rate: registration error handling fixup
In-Reply-To: <1332833009-4121-9-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-9-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAJOA=zPyiK4f2yCPXHOfik5nQObuiMdm8FiabZGarwo1qTvFYg@mail.gmail.com>

On Tue, Mar 27, 2012 at 12:23 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> The clk_register_fixed_rate should not call clk_register on "out:"
> path.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Hi Shawn,

I already had a patch for this sitting in my fixes branch and it
properly returns -EERROR for failures, so I'll stick with that one.

Thanks,
Mike

> ---
> ?drivers/clk/clk-fixed-rate.c | ? 19 +++++++++++++------
> ?1 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
> index 295f0d5..0d80827 100644
> --- a/drivers/clk/clk-fixed-rate.c
> +++ b/drivers/clk/clk-fixed-rate.c
> @@ -43,6 +43,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> ? ? ? ? ? ? ? ?unsigned long fixed_rate)
> ?{
> ? ? ? ?struct clk_fixed_rate *fixed;
> + ? ? ? struct clk *clk;
> ? ? ? ?const char **parent_names = NULL;
>
> ? ? ? ?fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
> @@ -56,21 +57,27 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> ? ? ? ?fixed->fixed_rate = fixed_rate;
>
> ? ? ? ?if (parent_name) {
> - ? ? ? ? ? ? ? parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
> -
> - ? ? ? ? ? ? ? if (! parent_names)
> + ? ? ? ? ? ? ? parent_names = kzalloc(sizeof(char *), GFP_KERNEL);
> + ? ? ? ? ? ? ? if (!parent_names)
> ? ? ? ? ? ? ? ? ? ? ? ?goto out;
>
> ? ? ? ? ? ? ? ?parent_names[0] = kstrdup(parent_name, GFP_KERNEL);
> -
> ? ? ? ? ? ? ? ?if (!parent_names[0])
> ? ? ? ? ? ? ? ? ? ? ? ?goto out;
> ? ? ? ?}
>
> -out:
> - ? ? ? return clk_register(dev, name,
> + ? ? ? clk = clk_register(dev, name,
> ? ? ? ? ? ? ? ? ? ? ? ?&clk_fixed_rate_ops, &fixed->hw,
> ? ? ? ? ? ? ? ? ? ? ? ?parent_names,
> ? ? ? ? ? ? ? ? ? ? ? ?(parent_name ? 1 : 0),
> ? ? ? ? ? ? ? ? ? ? ? ?flags);
> + ? ? ? if (clk)
> + ? ? ? ? ? ? ? return clk;
> +
> +out:
> + ? ? ? kfree(parent_names[0]);
> + ? ? ? kfree(parent_names);
> + ? ? ? kfree(fixed);
> +
> + ? ? ? return NULL;
> ?}
> --
> 1.7.5.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From olof at lixom.net  Tue Mar 27 20:56:08 2012
From: olof at lixom.net (Olof Johansson)
Date: Tue, 27 Mar 2012 17:56:08 -0700
Subject: [GIT PULL] ARM: tegra: Include assembler.h in sleep.S to fix
 build break
In-Reply-To: <4F709723.4080206@wwwdotorg.org>
References: <4F709723.4080206@wwwdotorg.org>
Message-ID: <CAOesGMiK3fLQP0oNZS0QwTM1+4uLs_QfAWbLXzH-=TWXSXbY7A@mail.gmail.com>

Hi,

On Mon, Mar 26, 2012 at 9:19 AM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> Arnd, Olof,
>
> This pull request depends on the merge of:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
> devel/io-cleanup
> (specifically 6f6f6a7 ARM: create a common IOMEM definition)
>
> and:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git for-3.4/soc
> (specifically c76fcc8 ARM: tegra: assembler code for LP3)
>
> and is based on a local branch that merges the two branches above.
>
> The following changes since commit 1ad105fc77e61f9dd7a272659a248e2979fdb893:
> ?Stephen Warren (1):
> ? ? ? ?Merge remote branch 'remotes/korg_olof_tegra/for-3.4/soc' into
> for-3.4/fixes-for-io-cleanup

Thanks, pulled into next/cleanup2 (after pulling in tegra/t30-smp into
the same).


-Olof


From mturquette at ti.com  Tue Mar 27 21:03:49 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Tue, 27 Mar 2012 18:03:49 -0700
Subject: [PATCH 07/10] clk: Constify parent name arrays
In-Reply-To: <1332833009-4121-8-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-8-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAJOA=zOXwtpefp2vgHprnmdpaOsHzo_rtMPMrN=X=K7YXM2EYA@mail.gmail.com>

On Tue, Mar 27, 2012 at 12:23 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> From: Mark Brown <broonie at opensource.wolfsonmicro.com>
>
> Drivers should be able to declare their arrays of parent names as const
> so the APIs need to accept const arguments.
>
> Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

Thanks for reposting Shawn.

Mark, I've taken this in to my fixes branch, but I dropped the change
in drivers/clk/clk-fixed-rate.c (since that code has shuffled) and I
also marked the char *parent[1] in fixed-rate and gate clocks as
const, in addition to the divider you did in your patch.

Thanks,
Mike


From gxt at mprc.pku.edu.cn  Tue Mar 27 22:22:54 2012
From: gxt at mprc.pku.edu.cn (Guan Xuetao)
Date: Wed, 28 Mar 2012 10:22:54 +0800
Subject: [PATCHv2 09/14] Unicore32: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-10-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
 <1332855768-32583-10-git-send-email-m.szyprowski@samsung.com>
Message-ID: <4F7275FE.8000100@mprc.pku.edu.cn>

On 03/27/2012 09:42 PM, Marek Szyprowski wrote:
> diff --git a/arch/unicore32/mm/dma-swiotlb.c b/arch/unicore32/mm/dma-swiotlb.c
> index bfa9fbb..4cf5f0c 100644
> --- a/arch/unicore32/mm/dma-swiotlb.c
> +++ b/arch/unicore32/mm/dma-swiotlb.c
> @@ -17,9 +17,23 @@
>
>   #include<asm/dma.h>
>
> +static void *unicore_swiotlb_alloc_coherent(struct device *dev, size_t size,
> +					    dma_addr_t *dma_handle, gfp_t flags,
> +					    struct dma_attrs *attrs)
> +{
> +	return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
> +}
> +
> +static void unicode_swiotlb_free_coherent(struct device *dev, size_t size,
The bit is ok for me. Only a typo here, please change unicode to unicore.

Thanks and Regards.

Guan Xuetao



From paul at pwsan.com  Tue Mar 27 22:39:34 2012
From: paul at pwsan.com (Paul Walmsley)
Date: Tue, 27 Mar 2012 20:39:34 -0600 (MDT)
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used
 OMAP4 onwards
In-Reply-To: <4F721A91.7000102@ti.com>
References: <1332842311-12308-1-git-send-email-rnayak@ti.com>
 <4F721A91.7000102@ti.com>
Message-ID: <alpine.DEB.2.00.1203272039010.22961@utopia.booyaka.com>

Hi Jon,

On Tue, 27 Mar 2012, Jon Hunter wrote:

> On 3/27/2012 4:58, Rajendra Nayak wrote:
>
> > diff --git a/arch/arm/mach-omap2/omap_hwmod.c
> > b/arch/arm/mach-omap2/omap_hwmod.c
> > index 8ac26f2..f2a9afa 100644
> > --- a/arch/arm/mach-omap2/omap_hwmod.c
> > +++ b/arch/arm/mach-omap2/omap_hwmod.c
> > @@ -808,7 +808,7 @@ static void _enable_module(struct omap_hwmod *oh)
> >    */
> >   static int _omap4_wait_target_disable(struct omap_hwmod *oh)
> >   {
> > -	if (!cpu_is_omap44xx())
> > +	if (cpu_is_omap24xx() || cpu_is_omap34xx())
> >   		return 0;
> 
> What about omap36xx?

Unfortunately, cpu_is_omap34xx() also covers OMAP36xx :-(

- Paul


From shawn.guo at linaro.org  Tue Mar 27 22:42:18 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 28 Mar 2012 10:42:18 +0800
Subject: [PATCH v5 2/8] ASoC: imx: merge sound/soc/imx into sound/soc/fsl
In-Reply-To: <2976261.6mYHfHvpym@laptop>
References: <1331888204-27058-1-git-send-email-shawn.guo@linaro.org>
 <1331888204-27058-3-git-send-email-shawn.guo@linaro.org>
 <2976261.6mYHfHvpym@laptop>
Message-ID: <CAAQ0ZWSPJ-5gAJGEYwbyUzjM_Ho851RAHSTBYKgcMtYNRn6ktQ@mail.gmail.com>

2012/3/27 Philippe R?tornaz <philippe.retornaz at epfl.ch>:
> Le vendredi 16 mars 2012 16:56:38 Shawn Guo a ?crit :
>> Freescale PowerPC and ARM/IMX families share the same SSI IP block.
>> The patch merges sound/soc/imx into sound/soc/fsl, so that the possible
>> code sharing and consolidation can happen.
>>
>> This is a plain merge, except that menuconfig SND_POWERPC_SOC is added
>> in Kconfig for PowerPC platform as a correspondence to SND_IMX_SOC for
>> IMX platform.
>>
>> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
>> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
>
> This patch has been merged ? If yes in which tree is it available ?
>
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-3.5

Regards,
Shawn


From shawn.guo at linaro.org  Tue Mar 27 22:45:27 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 28 Mar 2012 10:45:27 +0800
Subject: [PATCH] Regulator: anatop-regulator: patching to device-tree
 property "reg".
In-Reply-To: <1332834841-13925-1-git-send-email-paul.liu@linaro.org>
References: <1332834841-13925-1-git-send-email-paul.liu@linaro.org>
Message-ID: <CAAQ0ZWRh30PhS_zDhG5U1s8vTjETNQ0auHa9oNRt+Pv4zeCN1Q@mail.gmail.com>

On 27 March 2012 15:54, Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org> wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
>
> Change "reg" to "anatop-reg-offset" due to there is a warning of handling no
> size field in reg.
>
> This patch also adds the missing device-tree binding documentation.
>
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Liam Girdwood <lrg at ti.com>

Acked-by: Shawn Guo <shawn.guo at linaro.org>


From skannan at codeaurora.org  Tue Mar 27 23:06:56 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Tue, 27 Mar 2012 20:06:56 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zM47mB8tY2hV1QDVm1GZRqQrjrktkbLQ-Vp7hBjA8H5xg@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
 <4F6946AA.4070201@codeaurora.org> <4F6CEC0C.4060704@codeaurora.org>
 <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>
 <4F6CF555.4080109@codeaurora.org>
 <CAJOA=zOnR1NwZ1Cmkfb+b7f7=N_vg+txAUqKXF2Nf2nVYFMjjg@mail.gmail.com>
 <4F6D0167.3040704@codeaurora.org>
 <CAJOA=zM47mB8tY2hV1QDVm1GZRqQrjrktkbLQ-Vp7hBjA8H5xg@mail.gmail.com>
Message-ID: <4F728050.9030904@codeaurora.org>

On 03/23/2012 04:28 PM, Turquette, Mike wrote:
> On Fri, Mar 23, 2012 at 4:04 PM, Saravana Kannan<skannan at codeaurora.org>  wrote:
>> On 03/23/2012 03:32 PM, Turquette, Mike wrote:
>>> .recalc_rate serves two purposes: first it recalculates the rate after
>>> the rate has changed and you pass in a new parent_rate argument.  The
>>> second purpose is to "speculate" a rate change.  You can pass in any
>>> rate for the parent_rate parameter when you call .recalc_rates.  This
>>> is what __speculate_rates does before the rate changes.  For
>>> clk_set_parent we call,
>>>
>>> __clk_speculate_rates(clk, parent->rate);
>>>
>>> Where parent above is the *new* parent.  So this will let us propagate
>>> pre-rate change notifiers with the new rate.
>>>
>>> Your .recalc_rate callback doesn't need to differentiate between the
>>> two calls to .recalc_rate.  It should just take in the parent_rate
>>> value and do the calculation required of it.
>>
>> Yeah, this is generally true. But, in this specific case, the clock is a mux
>> that can literally measure the real rate. I would like the rate of this mux
>> clock to be the real measured rate and not just the parent rate.
>
> That's pretty cool hardware.  Do you find that software-only tracking
> doesn't match up with sampling the frequency in hardware?  If software
> tracking of the rate changes is correct then you could just skip using
> this hardware feature.

We use this HW for automated testing of the SW. It's very handy. So, I 
definitely need to support it.

>> I could actually measure the current rate and return that for recalc_rate(),
>> but then the reported rate change during the pre-change notification would
>> be wrong. Having the "msg" will let us at least fake the rate correctly for
>> pre change notifiers.
>
> In previous series I had separate .recalc_rate and .speculate_rate
> callbacks.  I merged them since they were almost identical.  I'd
> prefer not to reintroduce them since it creates a burden on others to
> support seperate callbacks, and passing in the message is one way to
> solve that... I'll think on this a bit more.

For this specific clock, I don't think anyone is really going to care if 
the pre rate change notification is correct. So, I will just go with 
reporting the wrong rate during pre-change for now.

But it does increase the total testing time quite a bit as I have to 
measure the real rate during pre and post change and measurement is 
relatively slow. It actually does add up into minutes when the whole 
test suite is run. So, would be nice to have this fixed eventually but 
it's not urgent for this measure clock.

>> How does a child (or grand child) clock (not a driver using the clock)
>> reject a rate change if it know it can't handle that freq from the parent? I
>> won't claim to know this part of the code thoroughly, but I can't find an
>> easy way to do this.
>
> Technically you could subscribe a notifier to your grand-child clock,
> even if there is no driver for it.  The same code that implements your
> platform's clock operations could register the notifier handler.
 >
> You can see how this works in clk_propagate_rate_change.  That usage
> is certainly targeted more at drivers but could be made to work for
> your case.  Let me know what you think; this is an interesting issue.

I think notifications should be left to drivers. Notifications are too 
heavy handed for enforcing requirements of the clock tree. Also, clk_hw 
to clk might no longer be a 1-1 mapping in the future. It's quite 
possible that each clk_get() would get a different struct clk based on 
the caller to keep track of their constraints separately. So, clock 
drivers shouldn't ever use them to identify a clock.

>> Reason for rejection could be things like the counter (for division, etc)
>> has an upper limit on how fast it can run.
>
> Are you hitting this in practice today?

Such HW limitations are real. But we don't use clk_set_parent() in our 
drivers often.

> The clock framework shouldn't
> be a perfect piece of code that can validate every possible
> combination imaginable.  Some burden falls on the code calling the clk
> api (especially if that code is platform code) to make sure that it
> doesn't do stupid things.

We can't expect a normal driver to know that the clk_set_parent() 
shouldn't be called when the parent is at a particular rate since there 
are clock HW limitations. The clock framework doesn't need to validate 
everything, but it should give the clock driver the option of rejecting 
invalid requests.

Btw, I think this earlier comment from me is wrong.
 > Nevermind, my brain isn't working today. I can just do that different
 > ordering in ops->set_parent().

I think there is still a problem with not being able to differentiate 
between pre-change recalc and post-change recalc. This applies for any 
set parent and set rate on a clock that has children.

Consider this simple example:
* Divider clock B is fed from clock A.
* Clock B can never output > 120 MHz due to downstream
   HW/clock limitations.
* Clock A is running at 200 MHz
* Clock B divider is set to 2.

Now, say the rate of clock A is changing from 200 MHz to 300 MHz (due to 
set rate or set parent). In this case, the clock B divider should be set 
to 3 pre-rate change to guarantee that the output of clock B is never > 
120 MHz. So the rate of clock B will go from 100 MHz (200/2) to 66 MHz 
(200/3) to 100 MHz (300/3) and everything is good.

Assume we somehow managed to do the above. So, now clock A is at 300 
MHz, clock B divider is at 3 and the clock B output is 100 MHz.

Now, say the rate of clock A changes from 300 MHz to 100 MHz. In this 
case the clock B divider should only be changed post rate change. If we 
do it pre rate change, then the output will go from 100 MHz (300/3) to 
150 MHz (300/1) to 100 MHz (100/1). We went past the 120 MHz limit of 
clock B's output rate.

If we do this post rate change, we can do this without exceeding the max 
output limit of clock B. It will go from 100 MHz (300/3) to 33 MHz 
(100/3) to 100 MHz (100/1). We never went past the 120 MHz limit.

So, at least for this reason above, I think we need to pass a pre/post 
parameter to the recalc ops.

While we are at it, we should probably just add a failure option for 
recalc to make it easy to reject unacceptable rate changes. To keep the 
clock framework code simpler, you could decide to allow errors only for 
the pre-change recalc calls. That way, the error case roll back code 
won't be crazy.

>>> Do you have a real use case for this?  Due to the way that we match
>>> the parent pointer with the cached clk->parents member it would be
>>> painful to support NULL parents as valid.
>>
>> I don't have a real use case for MSM. We just have a ground_clock.
>
> I'm electing to ignore the issue until we have a real use-case for it.

Sounds reasonable.

Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From benh at kernel.crashing.org  Tue Mar 27 23:56:40 2012
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Wed, 28 Mar 2012 14:56:40 +1100
Subject: [PATCHv2 04/14] PowerPC: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-5-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
 <1332855768-32583-5-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1332907000.2882.74.camel@pasglop>

On Tue, 2012-03-27 at 15:42 +0200, Marek Szyprowski wrote:
> From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
> 
> Adapt core PowerPC architecture code for dma_map_ops changes: replace
> alloc/free_coherent with generic alloc/free methods.
> 
> Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
> [added missing changes to arch/powerpc/kernel/vio.c]
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Reviewed-by: David Gibson <david at gibson.dropbear.id.au>
> Reviewed-by: Arnd Bergmann <arnd at arndb.de>
> ---

FYI. David and Arnd reviews are good enough for me ppc-side.

Cheers,
Ben.




From boojin.kim at samsung.com  Wed Mar 28 00:10:55 2012
From: boojin.kim at samsung.com (Boojin Kim)
Date: Wed, 28 Mar 2012 13:10:55 +0900
Subject: [PATCH 2/2] ARM: lib: use LDRD/STRD for data copy
In-Reply-To: <012d01cd0c78$7d2f19a0$778d4ce0$%kim@samsung.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <00d501cd0bb0$724ab260$56e01720$%kim@samsung.com>
 <20120327074039.GJ5611@n2100.arm.linux.org.uk>
 <012d01cd0c78$7d2f19a0$778d4ce0$%kim@samsung.com>
Message-ID: <014e01cd0c98$c5e899d0$51b9cd70$%kim@samsung.com>

Boojin Kim wrote:
> > Cc: linux-arm-kernel at lists.infradead.org; 'Catalin Marinas'; 'Nicolas Pitre';
> > kgene.kim at samsung.com
> > Subject: Re: [PATCH 2/2] ARM: lib: use LDRD/STRD for data copy
> >
> > On Tue, Mar 27, 2012 at 09:27:52AM +0900, Boojin Kim wrote:
> > > This patch uses LDRD/STRD that loads and stores data as DWORD unit.
> > > It brings better performance than LDRM/STRM with cortex-a15.
> >
> > Why should I bother looking at this rubbish?  You've been told before
> > that using ldrd and strd unconditionally is not acceptable.  Stop
> > wasting peoples review time.
> This patch brings better memcpy results on Cortex-a15.
Additionally, Following is ARM's memcpy implementation that mentions LDRD/STRD is better for cortex-a15.
http://sourceware.org/ml/newlib/2011/msg00469.html
I'm tring to optimize memcpy for cortex-a15 because it's seems to be worth.
Thank you..

> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel




From lethal at linux-sh.org  Wed Mar 28 00:15:03 2012
From: lethal at linux-sh.org (Paul Mundt)
Date: Wed, 28 Mar 2012 13:15:03 +0900
Subject: [PATCHv2 07/14] SH: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-8-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
 <1332855768-32583-8-git-send-email-m.szyprowski@samsung.com>
Message-ID: <20120328041503.GM26543@linux-sh.org>

On Tue, Mar 27, 2012 at 03:42:41PM +0200, Marek Szyprowski wrote:
> From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
> 
> Adapt core SH architecture code for dma_map_ops changes: replace
> alloc/free_coherent with generic alloc/free methods.
> 
> Signed-off-by: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
> Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Reviewed-by: Arnd Bergmann <arnd at arndb.de>

Acked-by: Paul Mundt <lethal at linux-sh.org>


From chao.xie at marvell.com  Wed Mar 28 01:08:41 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Wed, 28 Mar 2012 13:08:41 +0800
Subject: [PATCH 1/4] Input: pxa27x_keypad keep clock on as wakeup source
Message-ID: <1332911324-9840-1-git-send-email-chao.xie@marvell.com>

When the keypad is used as wake up source, the clock can not
be disabled. Or it can not detect key pressing.
If the keypad is used as wake up source, when resume back,
do not enable the clock and configure it again because the
register content is retained.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/input/keyboard/pxa27x_keypad.c |   27 ++++++++++++++++++---------
 1 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index 29fe1b2..1c5752f 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -419,10 +419,14 @@ static int pxa27x_keypad_suspend(struct device *dev)
 	struct platform_device *pdev = to_platform_device(dev);
 	struct pxa27x_keypad *keypad = platform_get_drvdata(pdev);
 
-	clk_disable(keypad->clk);
-
+	/*
+	 * If the keypad is used a wake up source, clock can not be disabled.
+	 * Or it can not detect the key pressing.
+	 */
 	if (device_may_wakeup(&pdev->dev))
 		enable_irq_wake(keypad->irq);
+	else
+		clk_disable(keypad->clk);
 
 	return 0;
 }
@@ -433,19 +437,24 @@ static int pxa27x_keypad_resume(struct device *dev)
 	struct pxa27x_keypad *keypad = platform_get_drvdata(pdev);
 	struct input_dev *input_dev = keypad->input_dev;
 
+	/*
+	 * If the keypad is used as wake up source, the clock is not turned
+	 * off. So do not need configure it again.
+	 */
 	if (device_may_wakeup(&pdev->dev))
 		disable_irq_wake(keypad->irq);
+	else {
+		mutex_lock(&input_dev->mutex);
 
-	mutex_lock(&input_dev->mutex);
+		if (input_dev->users) {
+			/* Enable unit clock */
+			clk_enable(keypad->clk);
+			pxa27x_keypad_config(keypad);
+		}
 
-	if (input_dev->users) {
-		/* Enable unit clock */
-		clk_enable(keypad->clk);
-		pxa27x_keypad_config(keypad);
+		mutex_unlock(&input_dev->mutex);
 	}
 
-	mutex_unlock(&input_dev->mutex);
-
 	return 0;
 }
 
-- 
1.7.0.4



From chao.xie at marvell.com  Wed Mar 28 01:08:42 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Wed, 28 Mar 2012 13:08:42 +0800
Subject: [PATCH 2/4] Input: pxa27x_keypad bug fix for direct_key_mask
In-Reply-To: <1332911324-9840-1-git-send-email-chao.xie@marvell.com>
References: <1332911324-9840-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1332911324-9840-2-git-send-email-chao.xie@marvell.com>

When direcct_key_num is 0, the mask should be 0.
When direcct_key_num is 1, the mask should be 0b1.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/input/keyboard/pxa27x_keypad.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index 1c5752f..f9a76d4 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -383,7 +383,7 @@ static void pxa27x_keypad_config(struct pxa27x_keypad *keypad)
 	if (pdata->direct_key_num > direct_key_num)
 		direct_key_num = pdata->direct_key_num;
 
-	keypad->direct_key_mask = ((2 << direct_key_num) - 1) & ~mask;
+	keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask;
 
 	/* enable direct key */
 	if (direct_key_num)
-- 
1.7.0.4



From chao.xie at marvell.com  Wed Mar 28 01:08:43 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Wed, 28 Mar 2012 13:08:43 +0800
Subject: [PATCH 3/4] Input: pxa27x_keypad direct key may be low active
In-Reply-To: <1332911324-9840-1-git-send-email-chao.xie@marvell.com>
References: <1332911324-9840-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1332911324-9840-3-git-send-email-chao.xie@marvell.com>

KPDK_DK only indicates the pin level of direct key.
So it is related to board, and low level may be active which
indicates that a key is pressed.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa27x_keypad.h |    2 ++
 drivers/input/keyboard/pxa27x_keypad.c         |   10 +++++++++-
 2 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
index abcc36e..7ffb16b 100644
--- a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -44,6 +44,8 @@ struct pxa27x_keypad_platform_data {
 	/* direct keys */
 	int		direct_key_num;
 	unsigned int	direct_key_map[MAX_DIRECT_KEY_NUM];
+	/* the key output may be low active */
+	int		direct_key_low_active;
 
 	/* rotary encoders 0 */
 	int		enable_rotary0;
diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index f9a76d4..b41ebda 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -311,7 +311,15 @@ static void pxa27x_keypad_scan_direct(struct pxa27x_keypad *keypad)
 	if (pdata->enable_rotary0 || pdata->enable_rotary1)
 		pxa27x_keypad_scan_rotary(keypad);
 
-	new_state = KPDK_DK(kpdk) & keypad->direct_key_mask;
+	/*
+	 * The KPDR_DK only output the key pin level, so it relates to board,
+	 * and low level may be active.
+	 */
+	if (pdata->direct_key_low_active)
+		new_state = ~KPDK_DK(kpdk) & keypad->direct_key_mask;
+	else
+		new_state = KPDK_DK(kpdk) & keypad->direct_key_mask;
+
 	bits_changed = keypad->direct_key_state ^ new_state;
 
 	if (bits_changed == 0)
-- 
1.7.0.4



From chao.xie at marvell.com  Wed Mar 28 01:08:44 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Wed, 28 Mar 2012 13:08:44 +0800
Subject: [PATCH 4/4] Input: pxa27x_keypad add choice to set direct_key_mask
In-Reply-To: <1332911324-9840-1-git-send-email-chao.xie@marvell.com>
References: <1332911324-9840-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1332911324-9840-4-git-send-email-chao.xie@marvell.com>

Direct keys usage may not start from KP_DKIN0, add a msk option
to configure the specifics for platforms that can skip some keys.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa27x_keypad.h |    2 ++
 drivers/input/keyboard/pxa27x_keypad.c         |    7 ++++++-
 2 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
index 7ffb16b..5ce8d5e 100644
--- a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -46,6 +46,8 @@ struct pxa27x_keypad_platform_data {
 	unsigned int	direct_key_map[MAX_DIRECT_KEY_NUM];
 	/* the key output may be low active */
 	int		direct_key_low_active;
+	/* give board a chance to choose the start direct key */
+	unsigned int	direct_key_mask;
 
 	/* rotary encoders 0 */
 	int		enable_rotary0;
diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index b41ebda..661892b 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -391,7 +391,12 @@ static void pxa27x_keypad_config(struct pxa27x_keypad *keypad)
 	if (pdata->direct_key_num > direct_key_num)
 		direct_key_num = pdata->direct_key_num;
 
-	keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask;
+	/* Direct keys usage may not start from KP_DKIN0, check the platfrom
+	 * msk data to config the specific */
+	if (pdata->direct_key_mask)
+		keypad->direct_key_mask = pdata->direct_key_mask;
+	else
+		keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask;
 
 	/* enable direct key */
 	if (direct_key_num)
-- 
1.7.0.4



From viresh.kumar at st.com  Wed Mar 28 01:03:21 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 28 Mar 2012 10:33:21 +0530
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <201203271359.16553.arnd@arndb.de>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203271159.35306.arnd@arndb.de>
 <CAOh2x==7gNt2Jb3-EHz9-R1pTy6zL93FmUmTBMdpYUnW3F=9Uw@mail.gmail.com>
 <201203271359.16553.arnd@arndb.de>
Message-ID: <4F729B99.4020909@st.com>

On 3/27/2012 7:29 PM, Arnd Bergmann wrote:
> That would be even better. I think we should generally try do initialization
> as late as possible, ideally from initcalls. The init_early() function should
> only be used for code that absolutely has to be run from setup_arch() and
> no later, while the map_io() function should ideally only be used to set up
> the static mappings and nothing else.

I remember now why we do it in map_io().
Timers need clock support and they are up before machine_init() is called.

So, i believe i must have DT_MACHINE_START per SoC.

I will post V2 for 3xx DT support today, but can i have initial level of review
from you, so that i can fixup minor issues in V2 only?

-- 
viresh


From afzal at ti.com  Wed Mar 28 01:04:51 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Wed, 28 Mar 2012 05:04:51 +0000
Subject: [RFC][PATCH 1/5] ARM: OMAP2+: gpmc: driver conversion
In-Reply-To: <4F71DD6C.5010305@ti.com>
References: <1332484600-21947-1-git-send-email-afzal@ti.com>
 <4F6D0569.6080203@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A9317BB895@DBDE01.ent.ti.com>
 <4F70AA82.3000204@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A9317BD6E2@DBDE01.ent.ti.com>
 <4F71DD6C.5010305@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A9317BFECE@DBDE01.ent.ti.com>

Hi Jon,

On Tue, Mar 27, 2012 at 21:01:56, Hunter, Jon wrote:
> > These are for the peripheral resources not in control of GPMC, like
> > gpio irq. These are copied in gpmc_create_child.
> 
> Right, I see they are copied during gpmc_create_child. However, I don't 
> see where they are initialised before that. The function 
> gpmc_setup_child is only initialising gpmc_res and gpmc_num_res and not 
> res and num_res. So I still don't see who is initialising these before 
> they are copied.

These are to be initialized by platform code, NAND have none so is
not currently seen, but devices like ethernet have to.

 
> I see you did not incorporate any clean-up in v2. Do you want me to send 
> you some patches to include?

Thanks for offering to help.

Cleanup is being deferred to be done once driver is finalized, I may
need your help later.

Regards
Afzal


From nico at fluxnic.net  Wed Mar 28 01:23:56 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 28 Mar 2012 01:23:56 -0400 (EDT)
Subject: [PATCH 1/2] ARM: lib: Add optimized memcpy with 64 byte pld size
In-Reply-To: <013501cd0c79$c1e244e0$45a6cea0$%kim@samsung.com>
References: <007201cd059e$4af2cc10$e0d86430$%kim@samsung.com>
 <00cf01cd0bb0$4fa49c30$eeedd490$%kim@samsung.com>
 <alpine.LFD.2.02.1203262231220.24151@xanadu.home>
 <013501cd0c79$c1e244e0$45a6cea0$%kim@samsung.com>
Message-ID: <alpine.LFD.2.02.1203280119550.24151@xanadu.home>

On Wed, 28 Mar 2012, Boojin Kim wrote:

> Nicolas wrote:
> 
> > This creates quite convoluted code.  If this is worth doing, we'll have
> > to find a cleaner way to do this.
> >
> > Could you please provide performance measurement numbers with and
> > without this patch, and similarly for the next patch?
> >
> > Did you try enabling the cache alignment code?  What performance
> > difference if any did you see?
> My patch brings about 10% better result on cache boundary.
> 64bytes PLD size makes the cache efficiency be higher on machines that has 64byte cache line.
> And, Which one is convoluted code? Can you explain it more detail?

Yes, I will.  I now have reworked this code to be extensible and still 
as clean as possible.  I'm not going to post it right away though, given 
that it is late and I prefer to have another look at it after I had some 
sleep.


Nicolas


From shawn.guo at freescale.com  Wed Mar 28 01:58:04 2012
From: shawn.guo at freescale.com (Shawn Guo)
Date: Wed, 28 Mar 2012 13:58:04 +0800
Subject: [PATCH v2 1/1] ARM: imx28: add basic dt support
In-Reply-To: <1332513070-5400-1-git-send-email-b29396@freescale.com>
References: <1332513070-5400-1-git-send-email-b29396@freescale.com>
Message-ID: <20120328055801.GA3953@S2100-06.ap.freescale.net>

On Fri, Mar 23, 2012 at 10:31:10PM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> This patch includes basic dt support which can boot via nfs rootfs.
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
> ChangeLog v1->v2:
>  * Some fixes addressed Rob's review comments.
>    Remove using of OF_DEV_AUXDATA.
>  * Remove mac address from dts file
>    Currently we use the mac address got from uboot to work.
>    Will submit a p separate atch using prom_update_property to fix this
>    issue for driver based on suggestions from Grant and Lothar.
>  * rename mxs-dt.c to mach-mxs.c which is supposed to support mx23 dt
>    too in the future.
>  * add compatible string "fsl,imx28" per Sascha's suggestion
>  * add more devices in dtsi file
>    For those devices still not in use, set the state to "disabled"
>    by default.
> 
> For other patches i sent with this in the first series like mmc and sdma
> dt support, i will send out them separately since this patch does not depend
> on them and does not block you to run dt via nfs rootfs.
> ---
>  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
>  arch/arm/boot/dts/imx28-evk.dts               |   35 +++
>  arch/arm/boot/dts/imx28.dtsi                  |  358 +++++++++++++++++++++++++
>  arch/arm/mach-mxs/Kconfig                     |    8 +
>  arch/arm/mach-mxs/Makefile                    |    1 +
>  arch/arm/mach-mxs/clock-mx28.c                |    4 +
>  arch/arm/mach-mxs/mach-mxs.c                  |   69 +++++
>  7 files changed, 479 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/imx28-evk.dts
>  create mode 100644 arch/arm/boot/dts/imx28.dtsi
>  create mode 100644 arch/arm/mach-mxs/mach-mxs.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> index 54bddda..9f21faf 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -1,6 +1,10 @@
>  Freescale i.MX Platforms Device Tree Bindings
>  -----------------------------------------------
>  
> +i.MX28 Evaluation Kit
> +Required root node properties:
> +    - compatible = "fsl,imx28-evk", "fsl,imx28";
> +
>  i.MX51 Babbage Board
>  Required root node properties:
>      - compatible = "fsl,imx51-babbage", "fsl,imx51";
> diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
> new file mode 100644
> index 0000000..5402495
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx28-evk.dts
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "imx28.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX28 Evaluation Kit";
> +	compatible = "fsl,imx28-evk", "fsl,imx28";
> +
> +	memory {
> +		device_type = "memory";

This is already in skeleton.dtsi included by imx28.dtsi.

> +		reg = <0x40000000 0x08000000>;
> +	};
> +
> +	ahb at 80080000 {
> +		ethernet at 800f0000 {
> +			phy-mode = "rmii";
> +			status = "okay";
> +		};
> +
> +		ethernet at 800f4000 {
> +			phy-mode = "rmii";
> +			status = "okay";
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> new file mode 100644
> index 0000000..9152354
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -0,0 +1,358 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;

These two are already in skeleton.dtsi.

> +	interrupt-parent = <&icoll>;
> +
> +	aliases {
> +		serial0 = &duart;
> +	};
> +
> +	cpus {
> +		cpu at 0 {
> +			compatible = "arm,arm926ejs";
> +		};
> +	};
> +
> +	apb at 80000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x80000000 0x80000>;
> +		ranges;
> +
> +		apbh at 80000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x80000000 0x3c900>;
> +			ranges;
> +
> +			icoll: interrupt-controller at 80000000 {
> +				compatible = "fsl,imx28-icoll";

I would expect it be:

	compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";

So it can be matched by both imx23 and imx28.

> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +				reg = <0x80000000 0x2000>;
> +			};
> +
> +			hsadc at 80002000 {
> +				reg = <0x80002000 2000>;
> +				interrupts = <13 87>;
> +				status = "disabled";
> +			};
> +
> +			dma-apbh at 80004000 {
> +				reg = <0x80004000 2000>;
> +				status = "disabled";
> +			};
> +
> +			perfmon at 80006000 {
> +				reg = <0x80006000 800>;
> +				interrupts = <27>;
> +				status = "disabled";
> +			};
> +
> +			bch at 8000a000 {
> +				reg = <0x8000a000 2000>;
> +				interrupts = <41>;
> +				status = "disabled";
> +			};
> +
> +			gpmi at 8000c000 {
> +				reg = <0x8000c000 2000>;
> +				interrupts = <42 88>;
> +				status = "disabled";
> +			};
> +
> +			ssp at 80010000 {
> +				reg = <0x80010000 2000>;
> +				interrupts = <96 82>;
> +				status = "disabled";
> +			};
> +
> +			ssp at 80012000 {
> +				reg = <0x80012000 2000>;
> +				interrupts = <97 83>;
> +				status = "disabled";
> +			};
> +
> +			ssp at 80014000 {
> +				reg = <0x80014000 2000>;
> +				interrupts = <98 84>;
> +				status = "disabled";
> +			};
> +
> +			ssp at 80016000 {
> +				reg = <0x80016000 2000>;
> +				interrupts = <99 85>;
> +				status = "disabled";
> +			};
> +
> +			pinctrl at 80018000 {
> +				reg = <0x80018000 2000>;
> +				status = "disabled";
> +			};
> +
> +			digctl at 8001c000 {
> +				reg = <0x8001c000 2000>;
> +				interrupts = <89>;
> +				status = "disabled";
> +			};
> +
> +			etm at 80022000 {
> +				reg = <0x80022000 2000>;
> +				status = "disabled";
> +			};
> +
> +			dma-apbx at 80024000 {
> +				reg = <0x80024000 2000>;
> +				status = "disabled";
> +			};
> +
> +			dcp at 80028000 {
> +				reg = <0x80028000 2000>;
> +				interrupts = <52 53 54>;
> +				status = "disabled";
> +			};
> +
> +			pxp at 8002a000 {
> +				reg = <0x8002a000 2000>;
> +				interrupts = <39>;
> +				status = "disabled";
> +			};
> +
> +			ocotp at 8002c000 {
> +				reg = <0x8002c000 2000>;
> +				status = "disabled";
> +			};
> +
> +			axi-ahb at 8002e000 {
> +				reg = <0x8002e000 2000>;
> +				status = "disabled";
> +			};
> +
> +			lcdif at 80030000 {
> +				reg = <0x80030000 2000>;
> +				interrupts = <38 86>;
> +				status = "disabled";
> +			};
> +
> +			can at 80032000 {
> +				reg = <0x80032000 2000>;
> +				interrupts = <8>;
> +				status = "disabled";
> +			};
> +
> +			can at 80034000 {
> +				reg = <0x80034000 2000>;
> +				interrupts = <9>;
> +				status = "disabled";
> +			};
> +
> +			simdbg at 8003c000 {
> +				reg = <0x8003c000 200>;
> +				status = "disabled";
> +			};
> +
> +			simgpmisel at 8003c200 {
> +				reg = <0x8003c200 100>;
> +				status = "disabled";
> +			};
> +
> +			simsspsel at 8003c300 {
> +				reg = <0x8003c300 100>;
> +				status = "disabled";
> +			};
> +
> +			simmemsel at 8003c400 {
> +				reg = <0x8003c400 100>;
> +				status = "disabled";
> +			};
> +
> +			gpiomon at 8003c500 {
> +				reg = <0x8003c500 100>;
> +				status = "disabled";
> +			};
> +
> +			simenet at 8003c700 {
> +				reg = <0x8003c700 100>;
> +				status = "disabled";
> +			};
> +
> +			armjtag at 8003c800 {
> +				reg = <0x8003c800 100>;
> +				status = "disabled";
> +			};
> +                };
> +
> +		apbx at 80040000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x80040000 0x40000>;
> +			ranges;
> +
> +			clkctl at 80040000 {
> +				reg = <0x80040000 2000>;
> +				status = "disabled";
> +			};
> +
> +			saif at 80042000 {
> +				reg = <0x80042000 2000>;
> +				interrupts = <59 80>;
> +				status = "disabled";
> +			};
> +
> +			power at 80044000 {
> +				reg = <0x80044000 2000>;
> +				status = "disabled";
> +			};
> +
> +			saif at 80046000 {
> +				reg = <0x80046000 2000>;
> +				interrupts = <58 81>;
> +				status = "disabled";
> +			};
> +
> +			lradc at 80050000 {
> +				reg = <0x80050000 2000>;
> +				status = "disabled";
> +			};
> +
> +			spdif at 80054000 {
> +				reg = <0x80054000 2000>;
> +				interrupts = <45 66>;
> +				status = "disabled";
> +			};
> +
> +			rtc at 80056000 {
> +				reg = <0x80056000 2000>;
> +				interrupts = <28 29>;
> +				status = "disabled";
> +			};
> +
> +			i2c at 80058000 {
> +				reg = <0x80058000 2000>;
> +				interrupts = <111 68>;
> +				status = "disabled";
> +			};
> +
> +			i2c at 8005a000 {
> +				reg = <0x8005a000 2000>;
> +				interrupts = <110 69>;
> +				status = "disabled";
> +			};
> +
> +			pwm at 80064000 {
> +				reg = <0x80064000 2000>;
> +				status = "disabled";
> +			};
> +
> +			timrot at 80068000 {
> +				reg = <0x80068000 2000>;
> +				status = "disabled";
> +			};
> +
> +			serial at 8006a000 {
> +				reg = <0x8006a000 0x2000>;
> +				interrupts = <112 70 71>;
> +				status = "disabled";
> +			};
> +
> +			serial at 8006c000 {
> +				reg = <0x8006c000 0x2000>;
> +				interrupts = <113 72 73>;
> +				status = "disabled";
> +			};
> +
> +			serial at 8006e000 {
> +				reg = <0x8006e000 0x2000>;
> +				interrupts = <114 74 75>;
> +				status = "disabled";
> +			};
> +
> +			serial at 80070000 {
> +				reg = <0x80070000 0x2000>;
> +				interrupts = <115 76 77>;
> +				status = "disabled";
> +			};
> +
> +			serial at 80072000 {
> +				reg = <0x80072000 0x2000>;
> +				interrupts = <116 78 79>;
> +				status = "disabled";
> +			};
> +
> +			duart: serial at 80074000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x80074000 0x1000>;
> +				interrupts = <47>;
> +			};
> +
> +			usbphy at 8007c000 {
> +				reg = <0x8007c000 0x2000>;
> +				status = "disabled";
> +			};
> +
> +			usbphy at 8007e000 {
> +				reg = <0x8007e000 0x2000>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	ahb at 80080000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x80080000 0x80000>;
> +		ranges;
> +
> +		usbctrl at 80080000 {
> +			reg = <0x80080000 0x10000>;
> +			status = "disabled";
> +		};
> +
> +		usbctrl at 80090000 {
> +			reg = <0x80090000 0x10000>;
> +			status = "disabled";
> +		};
> +
> +		dflpt at 800c0000 {
> +			reg = <0x800c0000 0x10000>;
> +			status = "disabled";
> +		};
> +
> +		ethernet at 800f0000 {
> +			compatible = "fsl,imx28-fec";
> +			reg = <0x800f0000 0x4000>;
> +			interrupts = <101>;
> +			status = "disabled";
> +		};
> +
> +		ethernet at 800f4000 {
> +			compatible = "fsl,imx28-fec";
> +			reg = <0x800f4000 0x4000>;
> +			interrupts = <102>;
> +			status = "disabled";
> +		};
> +
> +		switch at 800f8000 {
> +			reg = <0x800f8000 0x8000>;
> +			status = "disabled";
> +		};
> +
> +	};
> +};
> diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
> index c57f996..c776aef 100644
> --- a/arch/arm/mach-mxs/Kconfig
> +++ b/arch/arm/mach-mxs/Kconfig
> @@ -17,6 +17,14 @@ config SOC_IMX28
>  
>  comment "MXS platforms:"
>  
> +config MACH_MXS_DT
> +	bool "Support MXS platforms from device tree"
> +	select SOC_IMX28
> +	select USE_OF
> +	help
> +	  Include support for Freescale MXS platforms(i.MX23 and i.MX28)
> +	  using the device tree for discovery
> +

If I build mxs_defconfig with only MACH_MXS_DT enabled, I got

  LD      .tmp_vmlinux1
arch/arm/mach-mxs/built-in.o: In function `mxs_add_amba_device':
arch/arm/mach-mxs/devices.c:89: undefined reference to `amba_device_register'

It's caused by missing "select ARM_AMBA".  For non-dt build, it gets
selected under "config MXS_HAVE_AMBA_DUART" (mach-mxs/devices/Kconfig).

I intend to fix it in the following way.

--8<---
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 570d5d5..d076452 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -7,11 +7,13 @@ config MXS_OCOTP

 config SOC_IMX23
        bool
+       select ARM_AMBA
        select CPU_ARM926T
        select HAVE_PWM

 config SOC_IMX28
        bool
+       select ARM_AMBA
        select CPU_ARM926T
        select HAVE_PWM

diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index 18b6bf5..2febd62 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -1,6 +1,5 @@
 config MXS_HAVE_AMBA_DUART
        bool
-       select ARM_AMBA

--->8--

>  config MACH_STMP378X_DEVB
>  	bool "Support STMP378x_devb Platform"
>  	select SOC_IMX23
> diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
> index 908bf9a..8328c45 100644
> --- a/arch/arm/mach-mxs/Makefile
> +++ b/arch/arm/mach-mxs/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
>  obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
>  obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
>  
> +obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
>  obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
>  obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
>  obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
> diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
> index 5d68e41..88ed30c 100644
> --- a/arch/arm/mach-mxs/clock-mx28.c
> +++ b/arch/arm/mach-mxs/clock-mx28.c
> @@ -671,6 +671,10 @@ static struct clk_lookup lookups[] = {
>  	_REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
>  	_REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
>  	_REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
> +	/* for DT */
> +	_REGISTER_CLOCK("80074000.serial", NULL, uart_clk)
> +	_REGISTER_CLOCK("800f0000.ethernet", NULL, fec_clk)
> +	_REGISTER_CLOCK("800f4000.ethernet", NULL, fec_clk)
>  };
>  
>  static int clk_misc_init(void)
> diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
> new file mode 100644
> index 0000000..6d1e331
> --- /dev/null
> +++ b/arch/arm/mach-mxs/mach-mxs.c
> @@ -0,0 +1,69 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + * Copyright 2012 Linaro Ltd.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/init.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +#include <mach/common.h>
> +#include <mach/mx28.h>

This one is not needed.

> +
> +static int __init imx28_icoll_add_irq_domain(struct device_node *np,

mxs_icoll_add_irq_domain

> +				struct device_node *interrupt_parent)
> +{
> +	irq_domain_add_simple(np, 0);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id mxs_irq_match[] __initconst = {
> +	{ .compatible = "fsl,imx28-icoll", .data = imx28_icoll_add_irq_domain, },

"fsl,mxs-icoll"

> +	{ /* sentinel */ }
> +};
> +
> +static void __init mxs_dt_init_irq(void)
> +{
> +	icoll_init_irq();
> +	of_irq_init(mxs_irq_match);
> +}
> +
> +static void __init imx28_timer_init(void)
> +{
> +	mx28_clocks_init();
> +}
> +
> +static struct sys_timer imx28_timer = {
> +	.init = imx28_timer_init,
> +};
> +
> +static void __init imx28_machine_init(void)

mxs_init_machine(), so that imx23 can use it later and have the
function name somehow aligned with hook name .init_machine.

> +{
> +       of_platform_populate(NULL, of_default_bus_match_table,
> +		NULL, NULL);
> +}
> +
> +static const char *imx28_dt_compat[] __initdata = {

mxs_dt_compat

> +	"fsl,imx28",
> +	"fsl,imx28-evk",

I would have the list sorted from the most specific to the most
general.  That said, it's better to have "fsl,imx28" sorted after
"fsl,imx28-evk".

> +	NULL,
> +};
> +
> +DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
> +	.map_io		= mx28_map_io,
> +	.init_irq	= mxs_dt_init_irq,
> +	.timer		= &imx28_timer,
> +	.init_machine	= imx28_machine_init,
> +	.dt_compat	= imx28_dt_compat,
> +	.restart	= mxs_restart,
> +MACHINE_END
> -- 
> 1.7.0.4
> 

-- 
Regards,
Shawn



From andrew at lunn.ch  Wed Mar 28 01:42:33 2012
From: andrew at lunn.ch (Andrew Lunn)
Date: Wed, 28 Mar 2012 07:42:33 +0200
Subject: [PATCH 02/10] clk: remove unnecessary EXPORT_SYMBOL_GPL
In-Reply-To: <CAJOA=zMEtyYuPwSAnnJ2PUnymkn-QWD7rJaymemH5on21EB4Sw@mail.gmail.com>
References: <20120327092828.GA16397@lunn.ch>
 <20120327131002.GC3719@S2101-09.ap.freescale.net>
 <CAJOA=zMEtyYuPwSAnnJ2PUnymkn-QWD7rJaymemH5on21EB4Sw@mail.gmail.com>
Message-ID: <20120328054233.GA2954@lunn.ch>

> > I have a similar need for clk_divider_ops calls. ?Instead of exporting
> > every single clk_gate_ops call, we should just export "struct clk_ops
> > clk_gate_ops". ?That's exactly why I have the patch #4 here.
> 
> Andrew, does this approach work for you?  I prefer it over the EXPORT madness.

Hi Mike

I think so. I'm waiting for the first 3.4 RC to come out so I've not
tried implementing it yet.

      Andrew


From rusty at rustcorp.com.au  Wed Mar 28 02:09:31 2012
From: rusty at rustcorp.com.au (Rusty Russell)
Date: Wed, 28 Mar 2012 16:39:31 +1030
Subject: [PATCH] ARM: test for PMU feature on v7 (v2 with typo fix)
In-Reply-To: <20120326094054.GA2475@mudshark.cambridge.arm.com>
References: <4F590411.9060201@arm.com> <87ty1g88dv.fsf@rustcorp.com.au>
 <87r4wk889a.fsf@rustcorp.com.au>
 <20120323095314.GA13622@mudshark.cambridge.arm.com>
 <87fwcy9abw.fsf@rustcorp.com.au>
 <20120326094054.GA2475@mudshark.cambridge.arm.com>
Message-ID: <87pqbx9rz8.fsf@rustcorp.com.au>

On Mon, 26 Mar 2012 10:40:54 +0100, Will Deacon <will.deacon at arm.com> wrote:
> [removed some dead email addresses from CC]

Thanks!

> On Fri, Mar 23, 2012 at 11:17:07PM +0000, Rusty Russell wrote:
> > I had assumed that as we trend towards a common cross-platform kernel,
> > we should be relying on feature registers where available, not the
> > model.
> 
> The PMU is very tightly coupled with the CPU and it is necessary to know
> exactly which CPU you have so that you can map microarchitectural events to
> their identifiers. This is not discoverable in the architecture [PMUv2
> provides some support for discovering the status of architected events, but
> that is still not enough and is only present on A7 and A15 so far] so that's
> why we probe the CPU instead.

OK.

> Now, if everything was device-tree based then we could simply use a
> different binding for each CPU but since we support perf on non-DT
> platforms, probing the CPU type is the best solution. I would like to avoid
> the probing code if we are initialised from DT, but I've not got round to it
> yet (this would be useful for big.LITTLE).

I'll be interested to see how you encode the mapping of
microarchitectural events to their identifiers here.

> > > Would you be able to advertise 0 event counters instead and treat the PMU
> > > largely as RAZ/WI? The only tricky bit I can see is the cycle counter, which
> > > is mandated by the presence of a PMU, however this could also just RAZ
> > > initially.
> > 
> > Yes, that's the effect of the current emulation hack.  Far better not to
> > lie to the guest, however, than get weird results from profiling.
> 
> I'd rather lie to the guest than modify it just to avoid emulating the
> device correctly. Even then, the profiling results wouldn't be especially
> weird -- everything would be 0, which is a lot better than random
> numbers.

Sure, but nowhere as neat an experience as having "no hardware support
available" printed, and nicely defined failure mode :(

When I get back in May, I'll look at how hard it will to be implement
this properly, if noone else does.

Thanks,
Rusty.
-- 
  How could I marry someone with more hair than me?  http://baldalex.org


From m.szyprowski at samsung.com  Wed Mar 28 02:10:20 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 28 Mar 2012 08:10:20 +0200
Subject: [PATCHv2 09/14] Unicore32: adapt for dma_map_ops changes
In-Reply-To: <4F7275FE.8000100@mprc.pku.edu.cn>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
 <1332855768-32583-10-git-send-email-m.szyprowski@samsung.com>
 <4F7275FE.8000100@mprc.pku.edu.cn>
Message-ID: <00ac01cd0ca9$7508f4e0$5f1adea0$%szyprowski@samsung.com>

Hello,

On Wednesday, March 28, 2012 4:23 AM Guan Xuetao wrote:

> On 03/27/2012 09:42 PM, Marek Szyprowski wrote:
> > diff --git a/arch/unicore32/mm/dma-swiotlb.c b/arch/unicore32/mm/dma-swiotlb.c
> > index bfa9fbb..4cf5f0c 100644
> > --- a/arch/unicore32/mm/dma-swiotlb.c
> > +++ b/arch/unicore32/mm/dma-swiotlb.c
> > @@ -17,9 +17,23 @@
> >
> >   #include<asm/dma.h>
> >
> > +static void *unicore_swiotlb_alloc_coherent(struct device *dev, size_t size,
> > +					    dma_addr_t *dma_handle, gfp_t flags,
> > +					    struct dma_attrs *attrs)
> > +{
> > +	return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
> > +}
> > +
> > +static void unicode_swiotlb_free_coherent(struct device *dev, size_t size,
> The bit is ok for me. Only a typo here, please change unicode to unicore.

Ups, I'm sorry for that typo. I've fixed it on my git tree:

http://git.linaro.org/gitweb?p=people/mszyprowski/linux-dma-mapping.git;a=commitdiff;h=bbe43c05b0653
9c09f89e07bcaf61ea0fca8d67f

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From hvaibhav at ti.com  Wed Mar 28 02:32:33 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 28 Mar 2012 06:32:33 +0000
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used
 OMAP4 onwards
In-Reply-To: <1332842311-12308-1-git-send-email-rnayak@ti.com>
References: <1332842311-12308-1-git-send-email-rnayak@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83183E0CE@DBDE01.ent.ti.com>

On Tue, Mar 27, 2012 at 15:28:31, Nayak, Rajendra wrote:
> Some functions like _omap4_disable_module() and _omap4_wait_target_disable()
> are (will be) used on all OMAPs OMAP4 and beyond which support module level
> control. Fix the error checks in these functions to return if called on
> any platform pre OMAP4 (i.e OMAP2 and OMAP3) instead of checking for
> !cpu_is_omap44xx(). This avoids having to update the error check with a
> '&& !cpu_is_omap54xx()' when OMAP5 is introduced and possibly similar updates
> when further OMAP generations are added.
> 

Let me add some flavor here :)

AM33xx, which has module level control, but falls under OMAP3 family of 
devices. cpu_is_omap34xx() is true for AM33xx device and we have to add 
check in all these functions. And I am sure we will have many of such 
devices in the future.

Can we use some flag based option here, instead of cpu_is_xxx() check?

Thanks,
Vaibhav

> Signed-off-by: Rajendra Nayak <rnayak at ti.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
> index 8ac26f2..f2a9afa 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -808,7 +808,7 @@ static void _enable_module(struct omap_hwmod *oh)
>   */
>  static int _omap4_wait_target_disable(struct omap_hwmod *oh)
>  {
> -	if (!cpu_is_omap44xx())
> +	if (cpu_is_omap24xx() || cpu_is_omap34xx())
>  		return 0;
>  
>  	if (!oh)
> @@ -838,7 +838,7 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
>  	int v;
>  
>  	/* The module mode does not exist prior OMAP4 */
> -	if (!cpu_is_omap44xx())
> +	if (cpu_is_omap24xx() || cpu_is_omap34xx())
>  		return -EINVAL;
>  
>  	if (!oh->clkdm || !oh->prcm.omap4.modulemode)
> -- 
> 1.7.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 



From grinberg at compulab.co.il  Wed Mar 28 02:33:52 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 28 Mar 2012 08:33:52 +0200
Subject: [PATCH 05/12] Add dummy smsc911x regulators to cm-t35.
In-Reply-To: <20120327172819.GQ9859@atomide.com>
References: <1332494504-10251-1-git-send-email-Russ.Dill@ti.com>
 <1332494504-10251-6-git-send-email-Russ.Dill@ti.com>
 <4F71E290.2050403@compulab.co.il> <20120327172819.GQ9859@atomide.com>
Message-ID: <4F72B0D0.70703@compulab.co.il>

Hi Tony,

On 03/27/12 19:28, Tony Lindgren wrote:
> * Igor Grinberg <grinberg at compulab.co.il> [120327 08:56]:
>> Hi Russ,
>>
>> This patch works, but can we, please use the attached patch instead?
> 
> Hmm what's the difference here? Do you have some real controllable
> regulator for one of the smsc911x instances?

Well, the difference here is that those regulators will only be present
if the smsc911x controllers are present and their initialization is done
along with the controllers.
Also, I want to separate the cm-t35 from sb-t35 for future easier
refactoring of the sb-t35 code so it can be reused also on cm-t3517.

Only vddvario for smsc911x.0 is controllable - connected to VIO, but
VIO will never be disabled as it also controls many other devices
(DRAM is among them), so I prefer it to be dummy and keep it together
with vdd33a.

> 
> Anyways, I take it that you have tested that both smsc911x interfaces
> work now?

Yes, both regulators are registered and found by the smsc911x driver.
There is some kind of problem with the smsc911x.1, but it looks unrelated
to the patch:

smsc911x: Driver version 2008-10-21
irq 323: nobody cared (try booting with the "irqpoll" option)
[<c001ae6c>] (unwind_backtrace+0x0/0xfc) from [<c0088960>] (__report_bad_irq+0x28/0xbc)
[<c0088960>] (__report_bad_irq+0x28/0xbc) from [<c0088bd4>] (note_interrupt+0x1e0/0x230)
[<c0088bd4>] (note_interrupt+0x1e0/0x230) from [<c0086e48>] (handle_irq_event_percpu+0xb0/0x1a0)
[<c0086e48>] (handle_irq_event_percpu+0xb0/0x1a0) from [<c0086f74>] (handle_irq_event+0x3c/0x5c)
[<c0086f74>] (handle_irq_event+0x3c/0x5c) from [<c00895a0>] (handle_level_irq+0x90/0xfc)
[<c00895a0>] (handle_level_irq+0x90/0xfc) from [<c008699c>] (generic_handle_irq+0x38/0x40)
[<c008699c>] (generic_handle_irq+0x38/0x40) from [<c02635a0>] (gpio_irq_handler+0x1b0/0x20c)
[<c02635a0>] (gpio_irq_handler+0x1b0/0x20c) from [<c008699c>] (generic_handle_irq+0x38/0x40)
[<c008699c>] (generic_handle_irq+0x38/0x40) from [<c0015404>] (handle_IRQ+0x38/0x84)
[<c0015404>] (handle_IRQ+0x38/0x84) from [<c000865c>] (omap3_intc_handle_irq+0x48/0x4c)
[<c000865c>] (omap3_intc_handle_irq+0x48/0x4c) from [<c00140c4>] (__irq_svc+0x44/0x78)
Exception stack(0xcf02de20 to 0xcf02de68)
de20: cf02c018 cf02c000 00000000 cf02de58 60000013 c06739fc 00000143 c06739fc
de40: 60000013 00000508 c06739dc 00000000 00022d69 cf02de68 cf02b3c0 c04890fc
de60: 20000013 ffffffff
[<c00140c4>] (__irq_svc+0x44/0x78) from [<c04890fc>] (_raw_spin_unlock_irqrestore+0x64/0x68)
[<c04890fc>] (_raw_spin_unlock_irqrestore+0x64/0x68) from [<c0087d50>] (__setup_irq+0x1b4/0x3d4)
[<c0087d50>] (__setup_irq+0x1b4/0x3d4) from [<c00881a0>] (request_threaded_irq+0xdc/0x148)
[<c00881a0>] (request_threaded_irq+0xdc/0x148) from [<c0482954>] (smsc911x_drv_probe+0x350/0x528)
[<c0482954>] (smsc911x_drv_probe+0x350/0x528) from [<c02d5a8c>] (platform_drv_probe+0x18/0x1c)
[<c02d5a8c>] (platform_drv_probe+0x18/0x1c) from [<c02d4580>] (really_probe+0x64/0x160)
[<c02d4580>] (really_probe+0x64/0x160) from [<c02d46c4>] (driver_probe_device+0x48/0x60)
[<c02d46c4>] (driver_probe_device+0x48/0x60) from [<c02d4770>] (__driver_attach+0x94/0x98)
[<c02d4770>] (__driver_attach+0x94/0x98) from [<c02d2ffc>] (bus_for_each_dev+0x54/0x80)
[<c02d2ffc>] (bus_for_each_dev+0x54/0x80) from [<c02d3730>] (bus_add_driver+0xa8/0x2a4)
[<c02d3730>] (bus_add_driver+0xa8/0x2a4) from [<c02d4d6c>] (driver_register+0x78/0x184)
[<c02d4d6c>] (driver_register+0x78/0x184) from [<c0008758>] (do_one_initcall+0x34/0x184)
[<c0008758>] (do_one_initcall+0x34/0x184) from [<c0613248>] (do_basic_setup+0x34/0x40)
[<c0613248>] (do_basic_setup+0x34/0x40) from [<c06132b8>] (kernel_init+0x64/0xec)
[<c06132b8>] (kernel_init+0x64/0xec) from [<c00154cc>] (kernel_thread_exit+0x0/0x8)
handlers:
[<c032ea98>] smsc911x_irqhandler
Disabling IRQ #323

I still haven't had a chance to look into this.
Does anyone have a clue?

-- 
Regards,
Igor.


From grinberg at compulab.co.il  Wed Mar 28 02:34:29 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 28 Mar 2012 08:34:29 +0200
Subject: [PATCH 05/12] Add dummy smsc911x regulators to cm-t35.
In-Reply-To: <CA+Bv8XYiv+gr4yB+k7sWSSjdYSsYdnRJuTO3A5zZhh4bkoziXw@mail.gmail.com>
References: <1332494504-10251-1-git-send-email-Russ.Dill@ti.com>
 <1332494504-10251-6-git-send-email-Russ.Dill@ti.com>
 <4F71E290.2050403@compulab.co.il>
 <CA+Bv8XYiv+gr4yB+k7sWSSjdYSsYdnRJuTO3A5zZhh4bkoziXw@mail.gmail.com>
Message-ID: <4F72B0F5.4080705@compulab.co.il>

On 03/27/12 20:32, Russ Dill wrote:
> No objection.

10x Russ.


-- 
Regards,
Igor.


From shawn.guo at linaro.org  Wed Mar 28 03:30:33 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 28 Mar 2012 15:30:33 +0800
Subject: [PATCH] ASoC: sgtl5000: fix power on/off of MIC bias
Message-ID: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>

From: Lionel Xu <Lionel.Xu at freescale.com>

There is no sound in the recorded wav, to enable recording, the VAG
should be powered up, and the mic bias resistor should be set up with
proper value.

Signed-off-by: Lionel Xu <lionel.xu at freescale.com>
Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Cc: Zeng Zhaoming <zengzm.kernel at gmail.com>
---
 sound/soc/codecs/sgtl5000.c |   14 +++++++++++---
 1 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index d192626..a24299c 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -132,11 +132,18 @@ static int mic_bias_event(struct snd_soc_dapm_widget *w,
 		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
 				SGTL5000_BIAS_R_MASK,
 				SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
+
+		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
+				SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
 		break;
 
 	case SND_SOC_DAPM_PRE_PMD:
 		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
-				SGTL5000_BIAS_R_MASK, 0);
+				SGTL5000_BIAS_R_MASK,
+				SGTL5000_BIAS_R_off << SGTL5000_BIAS_R_SHIFT);
+
+		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
+				SGTL5000_VAG_POWERUP, 0);
 		break;
 	}
 	return 0;
@@ -197,7 +204,7 @@ static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
 	SND_SOC_DAPM_OUTPUT("HP_OUT"),
 	SND_SOC_DAPM_OUTPUT("LINE_OUT"),
 
-	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
+	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SND_SOC_NOPM, 0, 0,
 				mic_bias_event,
 				SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 
@@ -229,7 +236,8 @@ static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
 /* routes for sgtl5000 */
 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
 	{"Capture Mux", "LINE_IN", "LINE_IN"},	/* line_in --> adc_mux */
-	{"Capture Mux", "MIC_IN", "MIC_IN"},	/* mic_in --> adc_mux */
+	{"Mic Bias", NULL, "MIC_IN"},		/* mic_in --> mic bias */
+	{"Capture Mux", "MIC_IN", "Mic Bias"},	/* mic bias --> adc_mux */
 
 	{"ADC", NULL, "Capture Mux"},		/* adc_mux --> adc */
 	{"AIFOUT", NULL, "ADC"},		/* adc --> i2s_out */
-- 
1.7.4.1




From olof at lixom.net  Wed Mar 28 03:13:57 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 28 Mar 2012 00:13:57 -0700
Subject: [GIT PULL 0/5] Second batch of arm-soc changes
Message-ID: <1332918842-13521-1-git-send-email-olof@lixom.net>

Hi Linus,

Here is the second batch of arm-soc changes for this merge window. As Arnd
mentioned with the first cover letter, most of these either had external
dependencies that have now been pulled in, or just needed a bit more
linux-next bake time due to getting picked up close to the 3.3 release.


There are 128 non-merge patches, with a total diffstat of:

 346 files changed, 10790 insertions(+), 2792 deletions(-)

So, while there's been some good cleanups especially in the first branch,
there's been a net addition of code:

* New SoC family support for Samsung EXYNOS5250: clock tables, driver
  updates, etc means net gain in code.
* Added device tree conversions. Once we start to sunset non-device tree
  boards on the enabled platforms, we should see payback in code removal.
* Common clock framework. As SoCs get converted over to the framework,
  we should see more code removal from this as well.


There are a handful of merge conflicts on the branches, nothing that
should be too messy to sort out. I've described each conflict in the
corresponding pull request, including how we've resolved them in our
for-next branch.


Thanks,

-Olof



From shawn.guo at linaro.org  Wed Mar 28 03:34:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 28 Mar 2012 15:34:56 +0800
Subject: [PATCH] ASoC: fsl: assign dma peripheral type according to bus
 topology
Message-ID: <1332920096-9701-1-git-send-email-shawn.guo@linaro.org>

The dma peripheral_type for SSI should be IMX_DMATYPE_SSI_SP if the SSI
is on SPBA bus.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c     |    6 ++++++
 sound/soc/fsl/imx-pcm-dma.c |    3 ++-
 sound/soc/fsl/imx-pcm.h     |    1 +
 3 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 30ff605..4f76b5d 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -746,6 +746,12 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 		}
 		ssi_private->dma_params_tx.dma = dma_events[0];
 		ssi_private->dma_params_rx.dma = dma_events[1];
+
+		ssi_private->dma_params_tx.shared_peripheral =
+				of_device_is_compatible(of_get_parent(np),
+							"fsl,spba-bus");
+		ssi_private->dma_params_rx.shared_peripheral =
+				ssi_private->dma_params_tx.shared_peripheral;
 	}
 
 	/* Initialize the the device_attribute structure */
diff --git a/sound/soc/fsl/imx-pcm-dma.c b/sound/soc/fsl/imx-pcm-dma.c
index e43c8fa..8c43262 100644
--- a/sound/soc/fsl/imx-pcm-dma.c
+++ b/sound/soc/fsl/imx-pcm-dma.c
@@ -106,7 +106,8 @@ static int snd_imx_open(struct snd_pcm_substream *substream)
 	dma_params = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
 
 	dma_data = kzalloc(sizeof(*dma_data), GFP_KERNEL);
-	dma_data->peripheral_type = IMX_DMATYPE_SSI;
+	dma_data->peripheral_type = dma_params->shared_peripheral ?
+					IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI;
 	dma_data->priority = DMA_PRIO_HIGH;
 	dma_data->dma_request = dma_params->dma;
 
diff --git a/sound/soc/fsl/imx-pcm.h b/sound/soc/fsl/imx-pcm.h
index b5f5c3a..83c0ed7 100644
--- a/sound/soc/fsl/imx-pcm.h
+++ b/sound/soc/fsl/imx-pcm.h
@@ -22,6 +22,7 @@ struct imx_pcm_dma_params {
 	int dma;
 	unsigned long dma_addr;
 	int burstsize;
+	bool shared_peripheral;	/* The peripheral is on SPBA bus */
 };
 
 int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
-- 
1.7.4.1




From rientjes at google.com  Wed Mar 28 03:20:32 2012
From: rientjes at google.com (David Rientjes)
Date: Wed, 28 Mar 2012 00:20:32 -0700 (PDT)
Subject: [PATCH 10/10] oom: Make find_lock_task_mm() sparse-aware
In-Reply-To: <1332593574.16159.31.camel@twins>
References: <20120324102609.GA28356@lizard> <20120324103127.GJ29067@lizard>
 <1332593574.16159.31.camel@twins>
Message-ID: <alpine.DEB.2.00.1203280020100.16201@chino.kir.corp.google.com>

On Sat, 24 Mar 2012, Peter Zijlstra wrote:

> Yeah, so Nacked-by: Peter Zijlstra <a.p.zijlstra at chello.nl>
> 
> Also, why didn't lockdep catch it?
> 
> Fix sparse already instead of smearing ugly all over.
> 

Fully agreed, please don't add this to the oom killer.


From olof at lixom.net  Wed Mar 28 03:29:44 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 28 Mar 2012 00:29:44 -0700
Subject: [GIT PULL][for 3.4] pull request from arch-pxa git for board
 branch
In-Reply-To: <CAN1soZyCRQSVUQe+iBWX0nGwViWjp=W32BkYCcUUDmR894PJ9w@mail.gmail.com>
References: <CAN1soZyCRQSVUQe+iBWX0nGwViWjp=W32BkYCcUUDmR894PJ9w@mail.gmail.com>
Message-ID: <CAOesGMjD9QYCrE5wVxSghPHMoO+CuMd_CNhQUVyDS=Guyjr6YQ@mail.gmail.com>

Hi,

On Thu, Mar 22, 2012 at 11:22 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> Hi Arnd & Olof,
>
> Please help to merge this patch from arch-pxa git tree.
>
> The following changes since commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7:
>
> ?Linux 3.3 (2012-03-18 16:15:34 -0700)
>
> are available in the git repository at:
> ?git://github.com/hzhuang1/linux.git board-specific

I didn't include this branch in the pull requests I sent out today --
I couldn't tell from the pull request if it's a bug fix or support for
a new feature. If it's a fix, we can include it with the bugfix
branches we send through the -rc cycles. If not, we'll stage it for
3.5 once we start the new next/* branches. Please make it easy for us
to decide by motivating one or the other with the pull request.

Also, did you see the discussions about recent PXA fallout due to
various cleanups? You might want to double-check and make sure that
the mainline sources work well on your platforms and send fixes as
appropriate.

Finally, a nit:

> Paul Parsons (1):
> ? ? ?pxa/hx4700: Add standard UART to hx4700_pin_config[]

We tend to use:

ARM: <platform>: <subject>

for patch subjects. I don't reject patches due to a couple of slightly
misformatted patch subjects, but please update to use something like
"ARM: pxa: hx4700: <...>" in the future.


-Olof


From haojian.zhuang at gmail.com  Wed Mar 28 03:36:07 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 28 Mar 2012 15:36:07 +0800
Subject: [GIT PULL][for 3.4] pull request from arch-pxa git for board
 branch
In-Reply-To: <CAOesGMjD9QYCrE5wVxSghPHMoO+CuMd_CNhQUVyDS=Guyjr6YQ@mail.gmail.com>
References: <CAN1soZyCRQSVUQe+iBWX0nGwViWjp=W32BkYCcUUDmR894PJ9w@mail.gmail.com>
 <CAOesGMjD9QYCrE5wVxSghPHMoO+CuMd_CNhQUVyDS=Guyjr6YQ@mail.gmail.com>
Message-ID: <CAN1soZymgHW4bsgcwS655Zu-vcHQWpDtVFaaBsXdTifQ5QhjuA@mail.gmail.com>

On Wed, Mar 28, 2012 at 3:29 PM, Olof Johansson <olof at lixom.net> wrote:
> Hi,
>
> On Thu, Mar 22, 2012 at 11:22 PM, Haojian Zhuang
> <haojian.zhuang at gmail.com> wrote:
>> Hi Arnd & Olof,
>>
>> Please help to merge this patch from arch-pxa git tree.
>>
>> The following changes since commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7:
>>
>> ?Linux 3.3 (2012-03-18 16:15:34 -0700)
>>
>> are available in the git repository at:
>> ?git://github.com/hzhuang1/linux.git board-specific
>
> I didn't include this branch in the pull requests I sent out today --
> I couldn't tell from the pull request if it's a bug fix or support for
> a new feature. If it's a fix, we can include it with the bugfix
> branches we send through the -rc cycles. If not, we'll stage it for
> 3.5 once we start the new next/* branches. Please make it easy for us
> to decide by motivating one or the other with the pull request.
>
It's OK to queue this into 3.5.

> Also, did you see the discussions about recent PXA fallout due to
> various cleanups? You might want to double-check and make sure that
> the mainline sources work well on your platforms and send fixes as
> appropriate.
>
I noticed it. I'll verify it in the next week.

> Finally, a nit:
>
>> Paul Parsons (1):
>> ? ? ?pxa/hx4700: Add standard UART to hx4700_pin_config[]
>
> We tend to use:
>
> ARM: <platform>: <subject>
>
> for patch subjects. I don't reject patches due to a couple of slightly
> misformatted patch subjects, but please update to use something like
> "ARM: pxa: hx4700: <...>" in the future.
>
No problem. I'll change it.

Thanks
Haojian


From ludovic.desroches at atmel.com  Wed Mar 28 06:05:47 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 28 Mar 2012 12:05:47 +0200
Subject: [PATCH v2 0/3] atmel-mci device tree support 
Message-ID: <1332929150-14240-1-git-send-email-ludovic.desroches@atmel.com>

Hi,

This patch-set adds device tree support for atmel-mci.

Regards

Ludovic

v2:
- squash patch v1 2/4 and 3/4.
- change atmci_get_of_slots to atmci_of_init and manage pdata allocation into
it.
- correct potential issue (e.g. having only one slot which is not slot0 into
the dt) about slots by adding a reg property corresponding to the slot id.


.../devicetree/bindings/mmc/atmel-hsmci.txt        |   67 ++++++++++++++++
arch/arm/boot/dts/at91sam9g25ek.dts                |   16 ++++
arch/arm/boot/dts/at91sam9x5.dtsi                  |   24 ++++++
arch/arm/mach-at91/at91sam9x5.c                    |    2 +
drivers/mmc/host/atmel-mci.c                       |   80 ++++++++++++++++++++



From ludovic.desroches at atmel.com  Wed Mar 28 06:05:49 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 28 Mar 2012 12:05:49 +0200
Subject: [PATCH v2 2/3] arm: at91: at91sam9x5 add mci support
In-Reply-To: <1332929150-14240-1-git-send-email-ludovic.desroches@atmel.com>
References: <1332929150-14240-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1332929150-14240-3-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 arch/arm/boot/dts/at91sam9x5.dtsi |   24 ++++++++++++++++++++++++
 arch/arm/mach-at91/at91sam9x5.c   |    2 ++
 2 files changed, 26 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index c111001..c2ab650 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -191,6 +191,30 @@
 				interrupts = <27 4>;
 				status = "disabled";
 			};
+
+			mmc0: mmc at f0008000 {
+				compatible = "atmel,hsmci";
+				reg = <0xf0008000 0x600>;
+				interrupts = <12 4>;
+				status = "disabled";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				slot at 0 {
+					reg = <0>;
+				};
+			};
+
+			mmc1: mmc at f000c000 {
+				compatible = "atmel,hsmci";
+				reg = <0xf000c000 0x600>;
+				interrupts = <26 4>;
+				status = "disabled";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				slot at 0 {
+					reg = <0>;
+				};
+			};
 		};
 
 		nand0: nand at 40000000 {
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 13c8cae..39cbef3 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -225,6 +225,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
+	CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
+	CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
 	CLKDEV_CON_ID("pioA", &pioAB_clk),
 	CLKDEV_CON_ID("pioB", &pioAB_clk),
 	CLKDEV_CON_ID("pioC", &pioCD_clk),
-- 
1.7.5.4



From ludovic.desroches at atmel.com  Wed Mar 28 06:05:50 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 28 Mar 2012 12:05:50 +0200
Subject: [PATCH v2 3/3] arm: at91: dt: sam9g25ek add mci support
In-Reply-To: <1332929150-14240-1-git-send-email-ludovic.desroches@atmel.com>
References: <1332929150-14240-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1332929150-14240-4-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/boot/dts/at91sam9g25ek.dts |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 7a13d09..960de2b 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -32,6 +32,22 @@
 				phy-mode = "rmii";
 				status = "okay";
 			};
+
+			mmc0: mmc at f0008000 {
+				status = "okay";
+				slot at 0 {
+					bus-width = <4>;
+					cd-gpios = <&pioD 15 0>;
+				};
+			};
+
+			mmc1: mmc at f000c000 {
+				status = "okay";
+				slot at 0 {
+					bus-width = <4>;
+					cd-gpios = <&pioD 14 0>;
+				};
+			};
 		};
 
 		usb0: ohci at 00600000 {
-- 
1.7.5.4



From ludovic.desroches at atmel.com  Wed Mar 28 06:05:48 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 28 Mar 2012 12:05:48 +0200
Subject: [PATCH v2 1/3] mmc: atmel-mci: add device tree support
In-Reply-To: <1332929150-14240-1-git-send-email-ludovic.desroches@atmel.com>
References: <1332929150-14240-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1332929150-14240-2-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
---
 .../devicetree/bindings/mmc/atmel-hsmci.txt        |   67 ++++++++++++++++
 drivers/mmc/host/atmel-mci.c                       |   80 ++++++++++++++++++++
 2 files changed, 147 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/atmel-hsmci.txt

diff --git a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
new file mode 100644
index 0000000..bd21e52
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
@@ -0,0 +1,67 @@
+* Atmel High Speed MultiMedia Card Interface
+
+This controller on atmel products provides an interface for MMC, SD and SDIO
+types of memory cards.
+
+1) MCI node
+
+Required properties:
+- compatible: no blank "atmel,hsmci"
+- reg: should contain HSMCI registers location and length
+- interrupts: should contain HSMCI interrupt number
+- #address-cells: should be one. The cell is the slot id.
+- #size-cells: should be zero.
+- at least one slot node
+
+The node contains child nodes for each slot that the platform uses
+
+Example MCI node:
+
+mmc0: mmc at f0008000 {
+	compatible = "atmel,hsmci";
+	reg = <0xf0008000 0x600>;
+	interrupts = <12 4>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	[ child node definitions...]
+};
+
+2) slot nodes
+
+Required properties:
+- reg: should contain the slot id.
+
+Optional properties:
+- bus-width: number of data lines connected to the controller
+- cd-gpios: specify GPIOs for card detection
+- cd-invert: invert the value of external card detect gpio line
+- wp-gpios: specify GPIOs for write protection
+
+Example slot node:
+
+slot at 0 {
+	reg = <0>;
+	bus-width = <4>;
+	cd-gpios = <&pioD 15 0>
+	cd-invert;
+};
+
+Example full MCI node:
+mmc0: mmc at f0008000 {
+	compatible = "atmel,hsmci";
+	reg = <0xf0008000 0x600>;
+	interrupts = <12 4>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	slot at 0 {
+		reg = <0>;
+		bus-width = <4>;
+		cd-gpios = <&pioD 15 0>
+		cd-invert;
+	};
+	slot at 1 {
+		reg = <1>;
+		bus-width = <4>;
+	};
+};
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index b5693fd..b160be6 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -19,6 +19,9 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
 #include <linux/platform_device.h>
 #include <linux/scatterlist.h>
 #include <linux/seq_file.h>
@@ -477,6 +480,70 @@ err:
 	dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 }
 
+#if defined(CONFIG_OF)
+static const struct of_device_id atmci_dt_ids[] = {
+	{ .compatible = "atmel,hsmci" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, atmci_dt_ids);
+
+static int __devinit atmci_of_init(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct device_node *cnp;
+	struct mci_platform_data *pdata;
+	unsigned int slot_id;
+	const __be32 *reg;
+
+	if (!np)
+		return 0;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	for_each_child_of_node(np, cnp) {
+		reg = of_get_property(cnp, "reg", NULL);
+		if (!reg) {
+			dev_warn(&pdev->dev, "reg property is missing for %s\n",
+				 cnp->full_name);
+			continue;
+		}
+
+		slot_id = be32_to_cpu(reg[0]);
+
+		if (slot_id > (ATMCI_MAX_NR_SLOTS-1)) {
+			dev_warn(&pdev->dev, "can't have more than %d slots\n",
+			         ATMCI_MAX_NR_SLOTS);
+			break;
+		}
+
+		if (of_property_read_u32(cnp, "bus-width",
+		                         &pdata->slot[slot_id].bus_width))
+			pdata->slot[slot_id].bus_width = 1;
+
+		pdata->slot[slot_id].detect_pin =
+			of_get_named_gpio(cnp, "cd-gpios", 0);
+
+		if (of_find_property(cnp, "cd-invert", NULL))
+			pdata->slot[slot_id].detect_is_active_high = true;
+
+		pdata->slot[slot_id].wp_pin =
+			of_get_named_gpio(cnp, "wp-gpios", 0);
+	}
+
+	pdev->dev.platform_data = pdata;
+
+	return 0;
+}
+#else /* CONFIG_OF */
+static inline int atmci_of_init(struct platform_device *dev)
+{
+	return 0;
+}
+#endif
+
 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
 					unsigned int ns)
 {
@@ -1847,6 +1914,13 @@ static int __init atmci_init_slot(struct atmel_mci *host,
 	slot->sdc_reg = sdc_reg;
 	slot->sdio_irq = sdio_irq;
 
+	dev_dbg(&mmc->class_dev,
+	        "slot[%u]: bus_width=%u, detect_pin=%d, "
+		"detect_is_active_high=%s, wp_pin=%d\n",
+		id, slot_data->bus_width, slot_data->detect_pin,
+		slot_data->detect_is_active_high ? "true" : "false",
+		slot_data->wp_pin);
+
 	mmc->ops = &atmci_ops;
 	mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
 	mmc->f_max = host->bus_hz / 2;
@@ -2047,6 +2121,11 @@ static int __init atmci_probe(struct platform_device *pdev)
 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!regs)
 		return -ENXIO;
+
+	ret = atmci_of_init(pdev);
+	if (ret)
+		return ret;
+
 	pdata = pdev->dev.platform_data;
 	if (!pdata)
 		return -ENXIO;
@@ -2242,6 +2321,7 @@ static struct platform_driver atmci_driver = {
 	.driver		= {
 		.name		= "atmel_mci",
 		.pm		= ATMCI_PM_OPS,
+		.of_match_table	= of_match_ptr(atmci_dt_ids),
 	},
 };
 
-- 
1.7.5.4



From arnd at arndb.de  Wed Mar 28 04:13:49 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 28 Mar 2012 08:13:49 +0000
Subject: [PATCH] ARM: SPEAr600: Add device-tree support to SPEAr600 boards
In-Reply-To: <4F729B99.4020909@st.com>
References: <1331650032-15274-1-git-send-email-sr@denx.de>
 <201203271359.16553.arnd@arndb.de> <4F729B99.4020909@st.com>
Message-ID: <201203280813.49760.arnd@arndb.de>

On Wednesday 28 March 2012, Viresh Kumar wrote:
> 
> On 3/27/2012 7:29 PM, Arnd Bergmann wrote:
> > That would be even better. I think we should generally try do initialization
> > as late as possible, ideally from initcalls. The init_early() function should
> > only be used for code that absolutely has to be run from setup_arch() and
> > no later, while the map_io() function should ideally only be used to set up
> > the static mappings and nothing else.
> 
> I remember now why we do it in map_io().
> Timers need clock support and they are up before machine_init() is called.

I don't know what others do to get around this, this must be a fairly
common dependency, but there is no need to worry about it now. It might
all change if you device to port it to the common clk infrastructure.
 
> So, i believe i must have DT_MACHINE_START per SoC.

Ok.

> I will post V2 for 3xx DT support today, but can i have initial level of review
> from you, so that i can fixup minor issues in V2 only?

That's ok, yes.

	arnd


From arnd at arndb.de  Wed Mar 28 04:17:12 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 28 Mar 2012 08:17:12 +0000
Subject: [PATCH V3 5/5] mtd: Move fdt partition documentation to a
 seperate file
In-Reply-To: <1332885255-8304-6-git-send-email-jm@lentin.co.uk>
References: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
 <1332885255-8304-6-git-send-email-jm@lentin.co.uk>
Message-ID: <201203280817.12652.arnd@arndb.de>

On Tuesday 27 March 2012, Jamie Lentin wrote:
> 
> Partitions are described in the same way for all mtd devices when using
> devicetree, move the documentation to a separate file and add references
> to it.
> 
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>

Acked-by: Arnd Bergmann <arnd at arndb.de>

> ---
>  .../devicetree/bindings/mtd/arm-versatile.txt      |    4 +-
>  .../devicetree/bindings/mtd/atmel-dataflash.txt    |    3 ++
>  .../devicetree/bindings/mtd/fsl-upm-nand.txt       |    4 ++
>  .../devicetree/bindings/mtd/gpio-control-nand.txt  |    3 ++
>  .../devicetree/bindings/mtd/mtd-physmap.txt        |   23 +-----------
>  .../devicetree/bindings/mtd/orion-nand.txt         |    3 ++
>  .../devicetree/bindings/mtd/partition.txt          |   38 ++++++++++++++++++++
>  7 files changed, 55 insertions(+), 23 deletions(-)



From arnd at arndb.de  Wed Mar 28 04:19:59 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 28 Mar 2012 08:19:59 +0000
Subject: [PATCH V3 1/5] ARM: kirkwood: Basic support for DNS-320 and
 DNS-325
In-Reply-To: <1332885255-8304-2-git-send-email-jm@lentin.co.uk>
References: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
 <1332885255-8304-2-git-send-email-jm@lentin.co.uk>
Message-ID: <201203280820.00139.arnd@arndb.de>

On Tuesday 27 March 2012, Jamie Lentin wrote:
> Add support for the DNS-320 and DNS-325. Describe as much as currently possible
> in the devicetree files, create a board-dnskw.c for everything else.
> 
> Use IEEE-compliant "okay", rather than "ok"
> 
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Acked-by: Jason Cooper <jason at lakedaemon.net>
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> ---

One small note about changeset comments: The part about differences from the previous
version of the same patch normally goes below the '---' line, in front of the diffstat,
to prevent it from going into the git changelog. Otherwise people will have no idea
what it's about.

	Arnd


From linux at arm.linux.org.uk  Wed Mar 28 04:25:01 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 28 Mar 2012 09:25:01 +0100
Subject: [GIT PULL 1/5] ARM: cleanups of io includes
In-Reply-To: <1332918842-13521-2-git-send-email-olof@lixom.net>
References: <1332918842-13521-1-git-send-email-olof@lixom.net>
 <1332918842-13521-2-git-send-email-olof@lixom.net>
Message-ID: <20120328082501.GA22414@n2100.arm.linux.org.uk>

On Wed, Mar 28, 2012 at 12:13:58AM -0700, Olof Johansson wrote:
> Rob Herring has done a sweeping change cleaning up all of the mach/io.h includes,
> moving some of the oft-repeated macros to a common location and removing a bunch of
> boiler plate. This is another step closer to a common zImage for multiple platforms.

NAK.  Linus, do not pull this.  This breaks PXA compilation, which has
been known about for more than a week.


From dan.j.williams at intel.com  Wed Mar 28 04:30:37 2012
From: dan.j.williams at intel.com (Williams, Dan J)
Date: Wed, 28 Mar 2012 01:30:37 -0700
Subject: [PATCH V2] iop-adma: Corrected array overflow in RAID6 Xscale(R)
 test.
In-Reply-To: <1331834850-27409-1-git-send-email-don.morris@hp.com>
References: <1331834850-27409-1-git-send-email-don.morris@hp.com>
Message-ID: <CABE8wwsP+o9AeSYW1wUJLfZ6y1v9c8EXT8b3nfTDiDdKW0fA+A@mail.gmail.com>

On Thu, Mar 15, 2012 at 11:07 AM, Don Morris <don.morris at hp.com> wrote:
> Bug: cppcheck reported overflow in array assignment (for loop walks
> 0 to IOP_ADMA_NUM_SRC_TEST+2, array size is IOP_ADMA_NUM_SRC_TEST).
>
> Reported as: https://bugzilla.kernel.org/show_bug.cgi?id=42677
>
> Test code pq_src array was grown by two elements to correspond with actual
> usage (IOP_ADMA_NUM_SRC_TEST+2), stack consumption was kept constant by
> modifying the pq_dest two element array which is only used when pq_src
> is referenced up to IOP_ADMA_NUM_SRC_TEST elements into the address
> of the new last two elements of the pq_src array. This is presumed to
> be the original intent but would be reliant on compilers always having
> pq_dest contiguous with the final element of pq_src.
>
> Note: This is a re-send of a request for review from two weeks ago.
> Looking for review (or shootdown), adding LKML to list for a wider
> audience. Thanks.
>
> Updated per review comments of Sergei Shtylyov <sshtylyov at mvista.com>
>
> Signed-off-by: Don Morris <don.morris at hp.com>

Applied, thanks, and I'll send it along for Vinod's tree.


From ludovic.desroches at atmel.com  Wed Mar 28 06:28:33 2012
From: ludovic.desroches at atmel.com (ludovic.desroches at atmel.com)
Date: Wed, 28 Mar 2012 12:28:33 +0200
Subject: [PATCH v2 1/3] mmc: atmel-mci: correct data timeout computation
In-Reply-To: <1332344483-3915-2-git-send-email-ludovic.desroches@atmel.com>
References: <1332344483-3915-2-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <1332930513-14893-1-git-send-email-ludovic.desroches@atmel.com>

From: Ludovic Desroches <ludovic.desroches at atmel.com>

The HSMCI operates at a rate of up to Master Clock divided by two.
Moreover previous calculation can cause overflows and so wrong
timeouts.

Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
Cc: stable <stable at vger.kernel.org>
---
 drivers/mmc/host/atmel-mci.c |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index e4449a5..3a57964 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -480,7 +480,14 @@ err:
 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
 					unsigned int ns)
 {
-	return (ns * (host->bus_hz / 1000000) + 999) / 1000;
+	/*
+	 * It is easier here to use us instead of ns for the timeout,
+	 * it prevents from overflows during calculation.
+	 */
+	unsigned int us = DIV_ROUND_UP(ns, 1000);
+
+	/* Maximum clock frequency is host->bus_hz/2 */
+	return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
 }
 
 static void atmci_set_timeout(struct atmel_mci *host,
-- 
1.7.5.4



From thomas.abraham at linaro.org  Wed Mar 28 04:31:16 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 28 Mar 2012 14:01:16 +0530
Subject: [PATCH v2 1/3] mmc: atmel-mci: add device tree support
In-Reply-To: <1332929150-14240-2-git-send-email-ludovic.desroches@atmel.com>
References: <1332929150-14240-1-git-send-email-ludovic.desroches@atmel.com>
 <1332929150-14240-2-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <CAJuYYwQSyGXSYjJnQSXUJZ4DaHHY7bz=OZ5bEEBxkqboN_Sa7w@mail.gmail.com>

On 28 March 2012 15:35,  <ludovic.desroches at atmel.com> wrote:
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> ---
> ?.../devicetree/bindings/mmc/atmel-hsmci.txt ? ? ? ?| ? 67 ++++++++++++++++
> ?drivers/mmc/host/atmel-mci.c ? ? ? ? ? ? ? ? ? ? ? | ? 80 ++++++++++++++++++++
> ?2 files changed, 147 insertions(+), 0 deletions(-)
> ?create mode 100644 Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
>
> diff --git a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
> new file mode 100644
> index 0000000..bd21e52
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
> @@ -0,0 +1,67 @@
> +* Atmel High Speed MultiMedia Card Interface
> +
> +This controller on atmel products provides an interface for MMC, SD and SDIO
> +types of memory cards.
> +
> +1) MCI node
> +
> +Required properties:
> +- compatible: no blank "atmel,hsmci"
> +- reg: should contain HSMCI registers location and length
> +- interrupts: should contain HSMCI interrupt number
> +- #address-cells: should be one. The cell is the slot id.
> +- #size-cells: should be zero.
> +- at least one slot node
> +
> +The node contains child nodes for each slot that the platform uses
> +
> +Example MCI node:
> +
> +mmc0: mmc at f0008000 {
> + ? ? ? compatible = "atmel,hsmci";
> + ? ? ? reg = <0xf0008000 0x600>;
> + ? ? ? interrupts = <12 4>;
> + ? ? ? #address-cells = <1>;
> + ? ? ? #size-cells = <0>;
> +
> + ? ? ? [ child node definitions...]
> +};
> +
> +2) slot nodes
> +
> +Required properties:
> +- reg: should contain the slot id.
> +
> +Optional properties:
> +- bus-width: number of data lines connected to the controller
> +- cd-gpios: specify GPIOs for card detection
> +- cd-invert: invert the value of external card detect gpio line
> +- wp-gpios: specify GPIOs for write protection

There is a push for common bindings for sd/mmc and other card
controllers as suggested by Arnd here:
http://www.mail-archive.com/linux-mmc at vger.kernel.org/msg13421.html

> +
> +Example slot node:
> +
> +slot at 0 {
> + ? ? ? reg = <0>;
> + ? ? ? bus-width = <4>;
> + ? ? ? cd-gpios = <&pioD 15 0>
> + ? ? ? cd-invert;
> +};
> +
> +Example full MCI node:
> +mmc0: mmc at f0008000 {
> + ? ? ? compatible = "atmel,hsmci";
> + ? ? ? reg = <0xf0008000 0x600>;
> + ? ? ? interrupts = <12 4>;
> + ? ? ? #address-cells = <1>;
> + ? ? ? #size-cells = <0>;
> + ? ? ? slot at 0 {
> + ? ? ? ? ? ? ? reg = <0>;
> + ? ? ? ? ? ? ? bus-width = <4>;
> + ? ? ? ? ? ? ? cd-gpios = <&pioD 15 0>
> + ? ? ? ? ? ? ? cd-invert;
> + ? ? ? };
> + ? ? ? slot at 1 {
> + ? ? ? ? ? ? ? reg = <1>;
> + ? ? ? ? ? ? ? bus-width = <4>;
> + ? ? ? };
> +};
> diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> index b5693fd..b160be6 100644
> --- a/drivers/mmc/host/atmel-mci.c
> +++ b/drivers/mmc/host/atmel-mci.c
> @@ -19,6 +19,9 @@
> ?#include <linux/interrupt.h>
> ?#include <linux/ioport.h>
> ?#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
> ?#include <linux/platform_device.h>
> ?#include <linux/scatterlist.h>
> ?#include <linux/seq_file.h>
> @@ -477,6 +480,70 @@ err:
> ? ? ? ?dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
> ?}
>
> +#if defined(CONFIG_OF)
> +static const struct of_device_id atmci_dt_ids[] = {
> + ? ? ? { .compatible = "atmel,hsmci" },
> + ? ? ? { /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, atmci_dt_ids);
> +
> +static int __devinit atmci_of_init(struct platform_device *pdev)
> +{
> + ? ? ? struct device_node *np = pdev->dev.of_node;
> + ? ? ? struct device_node *cnp;
> + ? ? ? struct mci_platform_data *pdata;
> + ? ? ? unsigned int slot_id;
> + ? ? ? const __be32 *reg;
> +
> + ? ? ? if (!np)
> + ? ? ? ? ? ? ? return 0;
> +
> + ? ? ? pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> + ? ? ? if (!pdata)
> + ? ? ? ? ? ? ? return -ENOMEM;
> +
> + ? ? ? for_each_child_of_node(np, cnp) {
> + ? ? ? ? ? ? ? reg = of_get_property(cnp, "reg", NULL);
> + ? ? ? ? ? ? ? if (!reg) {
> + ? ? ? ? ? ? ? ? ? ? ? dev_warn(&pdev->dev, "reg property is missing for %s\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?cnp->full_name);
> + ? ? ? ? ? ? ? ? ? ? ? continue;
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? slot_id = be32_to_cpu(reg[0]);
> +
> + ? ? ? ? ? ? ? if (slot_id > (ATMCI_MAX_NR_SLOTS-1)) {
> + ? ? ? ? ? ? ? ? ? ? ? dev_warn(&pdev->dev, "can't have more than %d slots\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ATMCI_MAX_NR_SLOTS);
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> +
> + ? ? ? ? ? ? ? if (of_property_read_u32(cnp, "bus-width",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?&pdata->slot[slot_id].bus_width))
> + ? ? ? ? ? ? ? ? ? ? ? pdata->slot[slot_id].bus_width = 1;
> +
> + ? ? ? ? ? ? ? pdata->slot[slot_id].detect_pin =
> + ? ? ? ? ? ? ? ? ? ? ? of_get_named_gpio(cnp, "cd-gpios", 0);
> +
> + ? ? ? ? ? ? ? if (of_find_property(cnp, "cd-invert", NULL))
> + ? ? ? ? ? ? ? ? ? ? ? pdata->slot[slot_id].detect_is_active_high = true;
> +
> + ? ? ? ? ? ? ? pdata->slot[slot_id].wp_pin =
> + ? ? ? ? ? ? ? ? ? ? ? of_get_named_gpio(cnp, "wp-gpios", 0);
> + ? ? ? }
> +
> + ? ? ? pdev->dev.platform_data = pdata;

Assigning a pointer to pdev->dev.platform as done above is not
allowed. The pointer to pdata obtained from dt should be stored as
part of the driver's private data and used. (I used to do the same
mistake until I learnt this lesson learnt from Grant).

> +
> + ? ? ? return 0;
> +}
> +#else /* CONFIG_OF */
> +static inline int atmci_of_init(struct platform_device *dev)
> +{
> + ? ? ? return 0;
> +}
> +#endif
> +
> ?static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned int ns)
> ?{
> @@ -1847,6 +1914,13 @@ static int __init atmci_init_slot(struct atmel_mci *host,
> ? ? ? ?slot->sdc_reg = sdc_reg;
> ? ? ? ?slot->sdio_irq = sdio_irq;
>
> + ? ? ? dev_dbg(&mmc->class_dev,
> + ? ? ? ? ? ? ? "slot[%u]: bus_width=%u, detect_pin=%d, "
> + ? ? ? ? ? ? ? "detect_is_active_high=%s, wp_pin=%d\n",
> + ? ? ? ? ? ? ? id, slot_data->bus_width, slot_data->detect_pin,
> + ? ? ? ? ? ? ? slot_data->detect_is_active_high ? "true" : "false",
> + ? ? ? ? ? ? ? slot_data->wp_pin);
> +
> ? ? ? ?mmc->ops = &atmci_ops;
> ? ? ? ?mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
> ? ? ? ?mmc->f_max = host->bus_hz / 2;
> @@ -2047,6 +2121,11 @@ static int __init atmci_probe(struct platform_device *pdev)
> ? ? ? ?regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> ? ? ? ?if (!regs)
> ? ? ? ? ? ? ? ?return -ENXIO;
> +
> + ? ? ? ret = atmci_of_init(pdev);
> + ? ? ? if (ret)
> + ? ? ? ? ? ? ? return ret;
> +
> ? ? ? ?pdata = pdev->dev.platform_data;
> ? ? ? ?if (!pdata)
> ? ? ? ? ? ? ? ?return -ENXIO;
> @@ -2242,6 +2321,7 @@ static struct platform_driver atmci_driver = {
> ? ? ? ?.driver ? ? ? ? = {
> ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "atmel_mci",
> ? ? ? ? ? ? ? ?.pm ? ? ? ? ? ? = ATMCI_PM_OPS,
> + ? ? ? ? ? ? ? .of_match_table = of_match_ptr(atmci_dt_ids),
> ? ? ? ?},
> ?};
>
> --
> 1.7.5.4

Thanks,
Thomas.


From will.deacon at arm.com  Wed Mar 28 04:56:11 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 28 Mar 2012 09:56:11 +0100
Subject: ARM11MPcore: tlb_ops_need_broadcast causes deadlock
In-Reply-To: <20120327174152.GA905@mvista.com>
References: <274124B9C6907D4B8CE985903EAA19E91B2D579066@SI-MBX06.de.bosch.com>
 <20120323173055.GC16225@mudshark.cambridge.arm.com>
 <274124B9C6907D4B8CE985903EAA19E91B2D5798D9@SI-MBX06.de.bosch.com>
 <20120327133226.GE18738@mudshark.cambridge.arm.com>
 <20120327174152.GA905@mvista.com>
Message-ID: <20120328085611.GA11524@mudshark.cambridge.arm.com>

On Tue, Mar 27, 2012 at 06:41:52PM +0100, George G. Davis wrote:
> On Tue, Mar 27, 2012 at 02:32:26PM +0100, Will Deacon wrote:
> > I have a theory about what goes on:
> > 
> > Say we have a valid (i.e. non-faulting) page which contains a load instruction
> > that will fault. A CPU executes this load and takes a data abort but at the
> > same time another CPU marks the page being executed as old. So when the
> > original CPU tries to load the faulting instruction in do_thumb_abort, we take
> > a second data abort (assumedly because we don't have a D-side TLB entry for the
> > text page, so we immediately see that it is old) and, because interrupts were
> > not yet re-enabled in the first fault, they are not enabled in the nested fault
> > either.
> 
> This is precisely what happened here.  The only difference is that the traces
> I've reviewed faulted at "not_thumb:" while attempting to read the userspace
> ARM instruction which lead to the (second) data abort with interrupts disabled.

Right, I think that's the same problem though.

> > Possible solutions:
> > 
> > (1) Enable interrupts if they are enabled in the faulting context before
> >     loading instructions on the dabt path.
> > 
> > (2) Use the FSR to determine whather a fault is due to a read or a write on
> >     ARMv6 - only load and disassemble the instruction on 1136 CPUs affected
> >     by erratum #325103 (which aren't SMP, so cannot hit the problem above).
> 
> We submitted a change similar to (2) above to the ARM Linux kernel mailing
> list for RFC [1] over a year ago.  That change [1] is similar to your change
> below.

Apologies, I missed that. Are you happy for me to continue with my change
below? I'd really like it if Peter could confirm it fixes his problem.

> > The latter is probably best. Please can you try the patch below? I've
> > checked that it does the right thing on an r0p1 1136 core using a simple
> > fork/swp program to trigger a CoW.
> 
> I tested your patch but only on a CPU_V6K based SMP machine.  In this
> case, ARM_ERRATA_326103 depends on CPU_V6, so is left disabled, renderring
> this patch functionally equivaltent to [1] below.

Thanks George. Do you have a testcase for reliably reproducing the deadlock
without this patch applied?

> FYI/FWIW, your patch above suffered whitespace damage.

That'll be the sorry excuse for an email system that I'm forced to use.
Perhaps the list archive has a better version:

http://lists.arm.linux.org.uk/lurker/attach/1 at 20120327.133226.639a8b79.attach

Will


From ludovic.desroches at atmel.com  Wed Mar 28 05:04:39 2012
From: ludovic.desroches at atmel.com (Ludovic Desroches)
Date: Wed, 28 Mar 2012 11:04:39 +0200
Subject: [PATCH v2 1/3] mmc: atmel-mci: add device tree support
In-Reply-To: <CAJuYYwQSyGXSYjJnQSXUJZ4DaHHY7bz=OZ5bEEBxkqboN_Sa7w@mail.gmail.com>
References: <1332929150-14240-1-git-send-email-ludovic.desroches@atmel.com>
 <1332929150-14240-2-git-send-email-ludovic.desroches@atmel.com>
 <CAJuYYwQSyGXSYjJnQSXUJZ4DaHHY7bz=OZ5bEEBxkqboN_Sa7w@mail.gmail.com>
Message-ID: <20120328090439.GC32137@ldesroches-Latitude-E6320>

Hi Thomas,

On Wed, Mar 28, 2012 at 02:01:16PM +0530, Thomas Abraham wrote:
> On 28 March 2012 15:35,  <ludovic.desroches at atmel.com> wrote:
> > From: Ludovic Desroches <ludovic.desroches at atmel.com>
> >
> > Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
> > ---
> > ?.../devicetree/bindings/mmc/atmel-hsmci.txt ? ? ? ?| ? 67 ++++++++++++++++
> > ?drivers/mmc/host/atmel-mci.c ? ? ? ? ? ? ? ? ? ? ? | ? 80 ++++++++++++++++++++
> > ?2 files changed, 147 insertions(+), 0 deletions(-)
> > ?create mode 100644 Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
> > new file mode 100644
> > index 0000000..bd21e52
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
> > @@ -0,0 +1,67 @@
> > +* Atmel High Speed MultiMedia Card Interface
> > +
> > +This controller on atmel products provides an interface for MMC, SD and SDIO
> > +types of memory cards.
> > +
> > +1) MCI node
> > +
> > +Required properties:
> > +- compatible: no blank "atmel,hsmci"
> > +- reg: should contain HSMCI registers location and length
> > +- interrupts: should contain HSMCI interrupt number
> > +- #address-cells: should be one. The cell is the slot id.
> > +- #size-cells: should be zero.
> > +- at least one slot node
> > +
> > +The node contains child nodes for each slot that the platform uses
> > +
> > +Example MCI node:
> > +
> > +mmc0: mmc at f0008000 {
> > + ? ? ? compatible = "atmel,hsmci";
> > + ? ? ? reg = <0xf0008000 0x600>;
> > + ? ? ? interrupts = <12 4>;
> > + ? ? ? #address-cells = <1>;
> > + ? ? ? #size-cells = <0>;
> > +
> > + ? ? ? [ child node definitions...]
> > +};
> > +
> > +2) slot nodes
> > +
> > +Required properties:
> > +- reg: should contain the slot id.
> > +
> > +Optional properties:
> > +- bus-width: number of data lines connected to the controller
> > +- cd-gpios: specify GPIOs for card detection
> > +- cd-invert: invert the value of external card detect gpio line
> > +- wp-gpios: specify GPIOs for write protection
> 
> There is a push for common bindings for sd/mmc and other card
> controllers as suggested by Arnd here:
> http://www.mail-archive.com/linux-mmc at vger.kernel.org/msg13421.html
> 

Thanks for the link, I have seen this discussion so I know that bindings
should change in order to have common ones.
Since I have seen no decision (or I missed it) about common bindings, I only
used existing bindings:

- cd-gpios and wp-gpios seem quite common
- bus-width is used by omap-hsmmc and samsung-sdhci
- cd-invert was into patches sent for mmci device tree support

I will change my bindings if needed.

> > +
> > +Example slot node:
> > +
> > +slot at 0 {
> > + ? ? ? reg = <0>;
> > + ? ? ? bus-width = <4>;
> > + ? ? ? cd-gpios = <&pioD 15 0>
> > + ? ? ? cd-invert;
> > +};
> > +
> > +Example full MCI node:
> > +mmc0: mmc at f0008000 {
> > + ? ? ? compatible = "atmel,hsmci";
> > + ? ? ? reg = <0xf0008000 0x600>;
> > + ? ? ? interrupts = <12 4>;
> > + ? ? ? #address-cells = <1>;
> > + ? ? ? #size-cells = <0>;
> > + ? ? ? slot at 0 {
> > + ? ? ? ? ? ? ? reg = <0>;
> > + ? ? ? ? ? ? ? bus-width = <4>;
> > + ? ? ? ? ? ? ? cd-gpios = <&pioD 15 0>
> > + ? ? ? ? ? ? ? cd-invert;
> > + ? ? ? };
> > + ? ? ? slot at 1 {
> > + ? ? ? ? ? ? ? reg = <1>;
> > + ? ? ? ? ? ? ? bus-width = <4>;
> > + ? ? ? };
> > +};
> > diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> > index b5693fd..b160be6 100644
> > --- a/drivers/mmc/host/atmel-mci.c
> > +++ b/drivers/mmc/host/atmel-mci.c
> > @@ -19,6 +19,9 @@
> > ?#include <linux/interrupt.h>
> > ?#include <linux/ioport.h>
> > ?#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_gpio.h>
> > ?#include <linux/platform_device.h>
> > ?#include <linux/scatterlist.h>
> > ?#include <linux/seq_file.h>
> > @@ -477,6 +480,70 @@ err:
> > ? ? ? ?dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
> > ?}
> >
> > +#if defined(CONFIG_OF)
> > +static const struct of_device_id atmci_dt_ids[] = {
> > + ? ? ? { .compatible = "atmel,hsmci" },
> > + ? ? ? { /* sentinel */ }
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, atmci_dt_ids);
> > +
> > +static int __devinit atmci_of_init(struct platform_device *pdev)
> > +{
> > + ? ? ? struct device_node *np = pdev->dev.of_node;
> > + ? ? ? struct device_node *cnp;
> > + ? ? ? struct mci_platform_data *pdata;
> > + ? ? ? unsigned int slot_id;
> > + ? ? ? const __be32 *reg;
> > +
> > + ? ? ? if (!np)
> > + ? ? ? ? ? ? ? return 0;
> > +
> > + ? ? ? pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> > + ? ? ? if (!pdata)
> > + ? ? ? ? ? ? ? return -ENOMEM;
> > +
> > + ? ? ? for_each_child_of_node(np, cnp) {
> > + ? ? ? ? ? ? ? reg = of_get_property(cnp, "reg", NULL);
> > + ? ? ? ? ? ? ? if (!reg) {
> > + ? ? ? ? ? ? ? ? ? ? ? dev_warn(&pdev->dev, "reg property is missing for %s\n",
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?cnp->full_name);
> > + ? ? ? ? ? ? ? ? ? ? ? continue;
> > + ? ? ? ? ? ? ? }
> > +
> > + ? ? ? ? ? ? ? slot_id = be32_to_cpu(reg[0]);
> > +
> > + ? ? ? ? ? ? ? if (slot_id > (ATMCI_MAX_NR_SLOTS-1)) {
> > + ? ? ? ? ? ? ? ? ? ? ? dev_warn(&pdev->dev, "can't have more than %d slots\n",
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ATMCI_MAX_NR_SLOTS);
> > + ? ? ? ? ? ? ? ? ? ? ? break;
> > + ? ? ? ? ? ? ? }
> > +
> > + ? ? ? ? ? ? ? if (of_property_read_u32(cnp, "bus-width",
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?&pdata->slot[slot_id].bus_width))
> > + ? ? ? ? ? ? ? ? ? ? ? pdata->slot[slot_id].bus_width = 1;
> > +
> > + ? ? ? ? ? ? ? pdata->slot[slot_id].detect_pin =
> > + ? ? ? ? ? ? ? ? ? ? ? of_get_named_gpio(cnp, "cd-gpios", 0);
> > +
> > + ? ? ? ? ? ? ? if (of_find_property(cnp, "cd-invert", NULL))
> > + ? ? ? ? ? ? ? ? ? ? ? pdata->slot[slot_id].detect_is_active_high = true;
> > +
> > + ? ? ? ? ? ? ? pdata->slot[slot_id].wp_pin =
> > + ? ? ? ? ? ? ? ? ? ? ? of_get_named_gpio(cnp, "wp-gpios", 0);
> > + ? ? ? }
> > +
> > + ? ? ? pdev->dev.platform_data = pdata;
> 
> Assigning a pointer to pdev->dev.platform as done above is not
> allowed. The pointer to pdata obtained from dt should be stored as
> part of the driver's private data and used. (I used to do the same
> mistake until I learnt this lesson learnt from Grant).
> 

Thanks for this lesson. It seems to be a usual error. I will correct it.

> > +
> > + ? ? ? return 0;
> > +}
> > +#else /* CONFIG_OF */
> > +static inline int atmci_of_init(struct platform_device *dev)
> > +{
> > + ? ? ? return 0;
> > +}
> > +#endif
> > +
> > ?static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned int ns)
> > ?{
> > @@ -1847,6 +1914,13 @@ static int __init atmci_init_slot(struct atmel_mci *host,
> > ? ? ? ?slot->sdc_reg = sdc_reg;
> > ? ? ? ?slot->sdio_irq = sdio_irq;
> >
> > + ? ? ? dev_dbg(&mmc->class_dev,
> > + ? ? ? ? ? ? ? "slot[%u]: bus_width=%u, detect_pin=%d, "
> > + ? ? ? ? ? ? ? "detect_is_active_high=%s, wp_pin=%d\n",
> > + ? ? ? ? ? ? ? id, slot_data->bus_width, slot_data->detect_pin,
> > + ? ? ? ? ? ? ? slot_data->detect_is_active_high ? "true" : "false",
> > + ? ? ? ? ? ? ? slot_data->wp_pin);
> > +
> > ? ? ? ?mmc->ops = &atmci_ops;
> > ? ? ? ?mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
> > ? ? ? ?mmc->f_max = host->bus_hz / 2;
> > @@ -2047,6 +2121,11 @@ static int __init atmci_probe(struct platform_device *pdev)
> > ? ? ? ?regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > ? ? ? ?if (!regs)
> > ? ? ? ? ? ? ? ?return -ENXIO;
> > +
> > + ? ? ? ret = atmci_of_init(pdev);
> > + ? ? ? if (ret)
> > + ? ? ? ? ? ? ? return ret;
> > +
> > ? ? ? ?pdata = pdev->dev.platform_data;
> > ? ? ? ?if (!pdata)
> > ? ? ? ? ? ? ? ?return -ENXIO;
> > @@ -2242,6 +2321,7 @@ static struct platform_driver atmci_driver = {
> > ? ? ? ?.driver ? ? ? ? = {
> > ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "atmel_mci",
> > ? ? ? ? ? ? ? ?.pm ? ? ? ? ? ? = ATMCI_PM_OPS,
> > + ? ? ? ? ? ? ? .of_match_table = of_match_ptr(atmci_dt_ids),
> > ? ? ? ?},
> > ?};
> >
> > --
> > 1.7.5.4
> 
> Thanks,
> Thomas.
>

Thanks

Regards

Ludovic


From olof at lixom.net  Wed Mar 28 05:05:50 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 28 Mar 2012 02:05:50 -0700
Subject: [GIT PULL 1/5] ARM: cleanups of io includes
In-Reply-To: <20120328082501.GA22414@n2100.arm.linux.org.uk>
References: <1332918842-13521-1-git-send-email-olof@lixom.net>
 <1332918842-13521-2-git-send-email-olof@lixom.net>
 <20120328082501.GA22414@n2100.arm.linux.org.uk>
Message-ID: <CAOesGMjwZOON9kFNvaEq8QhSvjAgsJT_J1Ysb9-AbePd6g+-rQ@mail.gmail.com>

On Wed, Mar 28, 2012 at 1:25 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Wed, Mar 28, 2012 at 12:13:58AM -0700, Olof Johansson wrote:
>> Rob Herring has done a sweeping change cleaning up all of the mach/io.h includes,
>> moving some of the oft-repeated macros to a common location and removing a bunch of
>> boiler plate. This is another step closer to a common zImage for multiple platforms.
>
> NAK. ?Linus, do not pull this. ?This breaks PXA compilation, which has
> been known about for more than a week.

The branch contains fixes for the compilation failures, they were
pulled in right before I staged the tag for the pull request:

http://marc.info/?l=linux-arm-kernel&m=133272592723334

If you prefer to let it sit in linux-next for a day or two before
going in, that's fine. But I verified that the original build problem
introduced was fixed before I sent it out.

Unfortunately, PXA is also broken due to the regulator changes
mentioned in the above referenced mail, which is already upstream and
unrelated to the changes in this branch.

Linus; the rest of the pull requests should be OK to go in
independently of this, so please go ahead with those if you don't
mind. The only changes to those branches in the last few days is the
merge resolution I did to the drivers2 branch/tag.


-Olof


From zengzm.kernel at gmail.com  Wed Mar 28 05:05:58 2012
From: zengzm.kernel at gmail.com (Zeng Zhaoming)
Date: Wed, 28 Mar 2012 17:05:58 +0800
Subject: [PATCH] ASoC: sgtl5000: fix power on/off of MIC bias
In-Reply-To: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
References: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120328090558.GA31596@zzm-ubuntu>

It is OK to me, Thanks.

Acked-by: Zeng Zhaoming <zengzm.kernel at gmail.com>

On Wed 2012-03-28 15:30:33, Shawn Guo wrote:
> From: Lionel Xu <Lionel.Xu at freescale.com>
> 
> There is no sound in the recorded wav, to enable recording, the VAG
> should be powered up, and the mic bias resistor should be set up with
> proper value.
> 
> Signed-off-by: Lionel Xu <lionel.xu at freescale.com>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> Cc: Zeng Zhaoming <zengzm.kernel at gmail.com>
> ---
>  sound/soc/codecs/sgtl5000.c |   14 +++++++++++---
>  1 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
> index d192626..a24299c 100644
> --- a/sound/soc/codecs/sgtl5000.c
> +++ b/sound/soc/codecs/sgtl5000.c
> @@ -132,11 +132,18 @@ static int mic_bias_event(struct snd_soc_dapm_widget *w,
>  		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
>  				SGTL5000_BIAS_R_MASK,
>  				SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
> +
> +		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
> +				SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
>  		break;
>  
>  	case SND_SOC_DAPM_PRE_PMD:
>  		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
> -				SGTL5000_BIAS_R_MASK, 0);
> +				SGTL5000_BIAS_R_MASK,
> +				SGTL5000_BIAS_R_off << SGTL5000_BIAS_R_SHIFT);
> +
> +		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
> +				SGTL5000_VAG_POWERUP, 0);
>  		break;
>  	}
>  	return 0;
> @@ -197,7 +204,7 @@ static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
>  	SND_SOC_DAPM_OUTPUT("HP_OUT"),
>  	SND_SOC_DAPM_OUTPUT("LINE_OUT"),
>  
> -	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
> +	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SND_SOC_NOPM, 0, 0,
>  				mic_bias_event,
>  				SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
>  
> @@ -229,7 +236,8 @@ static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
>  /* routes for sgtl5000 */
>  static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
>  	{"Capture Mux", "LINE_IN", "LINE_IN"},	/* line_in --> adc_mux */
> -	{"Capture Mux", "MIC_IN", "MIC_IN"},	/* mic_in --> adc_mux */
> +	{"Mic Bias", NULL, "MIC_IN"},		/* mic_in --> mic bias */
> +	{"Capture Mux", "MIC_IN", "Mic Bias"},	/* mic bias --> adc_mux */
>  
>  	{"ADC", NULL, "Capture Mux"},		/* adc_mux --> adc */
>  	{"AIFOUT", NULL, "ADC"},		/* adc --> i2s_out */
> -- 
> 1.7.4.1


From joancarles at fqingenieria.es  Wed Mar 28 05:26:50 2012
From: joancarles at fqingenieria.es (joancarles)
Date: Wed, 28 Mar 2012 11:26:50 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <137e8b8e079af62aea2fd4d363be6273@mail.fqingenieria.es>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
 <20120327090148.GB6790@pengutronix.de> <20120327110615.3bfaf969@eb-e6520>
 <7f2ae9e3800848e140461a0506808fb4@mail.fqingenieria.es>
 <20120327114048.6af2e178@eb-e6520>
 <137e8b8e079af62aea2fd4d363be6273@mail.fqingenieria.es>
Message-ID: <c4306c7d39eac8f1751957eefe20a6c2@mail.fqingenieria.es>

ADDENDUM:

>> I tried to increase max_blk_count and it breaks after a few tests.
>
> I will redo your tests in a jiffy, however the latency issues worry
> me a wee bit.

Increasing max_blk_count did not help really, however I am not sure if 
setting it unconditionally to 65535 was the only change I had to make.

> So, what's keeping the driver 8ms from sending the data??? Any
> pointers on where I could twiddle some bits in the driver? Where do I
> start looking?

Using the following setup, I tried to get some more information:

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c 
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 0be4e20..4896f24 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -467,8 +467,7 @@ static int __devinit sdhci_esdhc_imx_probe(struct 
platform_device *pdev)
         clk_enable(clk);
         pltfm_host->clk = clk;

-       if (!is_imx25_esdhc(imx_data))
-               host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
+       host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;

         if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 
*/
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 8d66706..0b60d14 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -713,6 +713,8 @@ static void sdhci_prepare_data(struct sdhci_host 
*host, struct mmc_command *cmd)
                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
         }

+       sdhci_dumpregs(host);
+
         if (!data)
                 return;

echo 'file core.c line 193 +p' > 
/sys/kernel/debug/dynamic_debug/control
echo 'file core.c line 158 +p' > 
/sys/kernel/debug/dynamic_debug/control
echo 'file sdhci.c line 72-115 +p' > 
/sys/kernel/debug/dynamic_debug/control
mount /media/card
dd if=/dev/urandom of=/media/card/file-4K bs=4K count=1

[  119.895460] mmc0: starting CMD24 arg 00045e00 flags 000000b5
[  119.895531] sdhci: =========== REGISTER DUMP (mmc0)===========
[  119.895570] sdhci: Sys addr: 0x82480000 | Version:  0x00000000
[  119.895602] sdhci: Blk size: 0x00000200 | Blk cnt:  0x00000000
[  119.895633] sdhci: Argument: 0x00049c00 | Trn mode: 0x00000013
[  119.895664] sdhci: Present:  0xff880000 | Host ctl: 0x00000023
[  119.895693] sdhci: Power:    0x00000000 | Blk gap:  0x00000000
[  119.895724] sdhci: Wake-up:  0x00000000 | Clock:    0x00000107
[  119.895754] sdhci: Timeout:  0x0000000e | Int stat: 0x00000000
[  119.895787] sdhci: Int enab: 0x107f000b | Sig enab: 0x107f000b
[  119.895819] sdhci: AC12 err: 0x00000000 | Slot int: 0x00001001
[  119.895852] sdhci: Caps:     0x07eb0000 | Caps_1:   0x04100410
[  119.895883] sdhci: Cmd:      0x0000113a | Max curr: 0x00000000
[  119.895911] sdhci: Host ctl2: 0x00000000
[  119.895936] sdhci: ===========================================
[  119.900527] mmc0: starting CMD13 arg 00020000 flags 00000195
[  119.900585] sdhci: =========== REGISTER DUMP (mmc0)===========
[  119.900624] sdhci: Sys addr: 0x82452400 | Version:  0x00000000
[  119.900655] sdhci: Blk size: 0x00000200 | Blk cnt:  0x00000000
[  119.900687] sdhci: Argument: 0x00045e00 | Trn mode: 0x00000003
[  119.900718] sdhci: Present:  0xff880000 | Host ctl: 0x00000023
[  119.900746] sdhci: Power:    0x00000000 | Blk gap:  0x00000000
[  119.900776] sdhci: Wake-up:  0x00000000 | Clock:    0x00000107
[  119.900807] sdhci: Timeout:  0x0000000e | Int stat: 0x00000000
[  119.900840] sdhci: Int enab: 0x107f000b | Sig enab: 0x107f000b
[  119.900869] sdhci: AC12 err: 0x00000000 | Slot int: 0x00001001
[  119.900902] sdhci: Caps:     0x07eb0000 | Caps_1:   0x04100410
[  119.900933] sdhci: Cmd:      0x0000183a | Max curr: 0x00000000
[  119.900962] sdhci: Host ctl2: 0x00000000
[  119.900985] sdhci: ===========================================
[  119.901357] mmc0: starting CMD17 arg 00009000 flags 000000b5
[  119.901419] sdhci: =========== REGISTER DUMP (mmc0)===========
[  119.901458] sdhci: Sys addr: 0x82452400 | Version:  0x00000000
[  119.901490] sdhci: Blk size: 0x00000200 | Blk cnt:  0x00000000
[  119.901520] sdhci: Argument: 0x00020000 | Trn mode: 0x00000003
[  119.901551] sdhci: Present:  0xff880000 | Host ctl: 0x00000023
[  119.901579] sdhci: Power:    0x00000000 | Blk gap:  0x00000000
[  119.901610] sdhci: Wake-up:  0x00000000 | Clock:    0x00000107
[  119.901641] sdhci: Timeout:  0x0000000e | Int stat: 0x00000000
[  119.901673] sdhci: Int enab: 0x107f000b | Sig enab: 0x107f000b
[  119.901703] sdhci: AC12 err: 0x00000000 | Slot int: 0x00001001
[  119.901735] sdhci: Caps:     0x07eb0000 | Caps_1:   0x04100410
[  119.901765] sdhci: Cmd:      0x00000d1a | Max curr: 0x00000000
[  119.901793] sdhci: Host ctl2: 0x00000000
[  119.901816] sdhci: ===========================================
[  119.908072] mmc0: starting CMD17 arg 00009200 flags 000000b5
[  119.908141] sdhci: =========== REGISTER DUMP (mmc0)===========
[  119.908179] sdhci: Sys addr: 0x82480000 | Version:  0x00000000
[  119.908212] sdhci: Blk size: 0x00000200 | Blk cnt:  0x00000000
[  119.908243] sdhci: Argument: 0x00009000 | Trn mode: 0x00000013
[  119.908274] sdhci: Present:  0xff880000 | Host ctl: 0x00000023
[  119.908304] sdhci: Power:    0x00000000 | Blk gap:  0x00000000
[  119.908335] sdhci: Wake-up:  0x00000000 | Clock:    0x00000107
[  119.908367] sdhci: Timeout:  0x0000000e | Int stat: 0x00000000
[  119.908400] sdhci: Int enab: 0x107f000b | Sig enab: 0x107f000b
[  119.908432] sdhci: AC12 err: 0x00000000 | Slot int: 0x00001001
[  119.908464] sdhci: Caps:     0x07eb0000 | Caps_1:   0x04100410
[  119.908495] sdhci: Cmd:      0x0000113a | Max curr: 0x00000000
[  119.908524] sdhci: Host ctl2: 0x00000000
[  119.908547] sdhci: ===========================================
[  119.910858] mmc0: starting CMD17 arg 00009400 flags 000000b5
[  119.910929] sdhci: =========== REGISTER DUMP (mmc0)===========
[  119.910969] sdhci: Sys addr: 0x82480000 | Version:  0x00000000
[  119.911002] sdhci: Blk size: 0x00000200 | Blk cnt:  0x00000000
[  119.911034] sdhci: Argument: 0x00009200 | Trn mode: 0x00000013
[  119.911065] sdhci: Present:  0xff880000 | Host ctl: 0x00000023
[  119.911095] sdhci: Power:    0x00000000 | Blk gap:  0x00000000
[  119.911126] sdhci: Wake-up:  0x00000000 | Clock:    0x00000107
[  119.911157] sdhci: Timeout:  0x0000000e | Int stat: 0x00000000
[  119.911191] sdhci: Int enab: 0x107f000b | Sig enab: 0x107f000b
[  119.911223] sdhci: AC12 err: 0x00000000 | Slot int: 0x00001001
[  119.911255] sdhci: Caps:     0x07eb0000 | Caps_1:   0x04100410
[  119.911286] sdhci: Cmd:      0x0000113a | Max curr: 0x00000000
[  119.911314] sdhci: Host ctl2: 0x00000000
[  119.911338] sdhci: ===========================================
[  119.913935] mmc0: starting CMD24 arg 00009000 flags 000000b5
[  119.914004] sdhci: =========== REGISTER DUMP (mmc0)===========
[  119.914042] sdhci: Sys addr: 0x82480000 | Version:  0x00000000
[  119.914073] sdhci: Blk size: 0x00000200 | Blk cnt:  0x00000000
[  119.914105] sdhci: Argument: 0x00009400 | Trn mode: 0x00000013
[  119.914135] sdhci: Present:  0xff880000 | Host ctl: 0x00000023
[  119.914164] sdhci: Power:    0x00000000 | Blk gap:  0x00000000
[  119.914194] sdhci: Wake-up:  0x00000000 | Clock:    0x00000107
[  119.914224] sdhci: Timeout:  0x0000000e | Int stat: 0x00000000
[  119.914257] sdhci: Int enab: 0x107f000b | Sig enab: 0x107f000b
[  119.914288] sdhci: AC12 err: 0x00000000 | Slot int: 0x00001001
[  119.914321] sdhci: Caps:     0x07eb0000 | Caps_1:   0x04100410
[  119.914352] sdhci: Cmd:      0x0000113a | Max curr: 0x00000000
[  119.914380] sdhci: Host ctl2: 0x00000000
[  119.914404] sdhci: ===========================================
[  119.921304] mmc0: starting CMD13 arg 00020000 flags 00000195
[  119.921368] sdhci: =========== REGISTER DUMP (mmc0)===========
[  119.921407] sdhci: Sys addr: 0x82403600 | Version:  0x00000000
[  119.921440] sdhci: Blk size: 0x00000200 | Blk cnt:  0x00000000
[  119.921472] sdhci: Argument: 0x00009000 | Trn mode: 0x00000003
[  119.921503] sdhci: Present:  0xff880000 | Host ctl: 0x00000023
[  119.921532] sdhci: Power:    0x00000000 | Blk gap:  0x00000000
[  119.921564] sdhci: Wake-up:  0x00000000 | Clock:    0x00000107
[  119.921594] sdhci: Timeout:  0x0000000e | Int stat: 0x00000000
[  119.921626] sdhci: Int enab: 0x107f000b | Sig enab: 0x107f000b
[  119.921658] sdhci: AC12 err: 0x00000000 | Slot int: 0x00001001
[  119.921689] sdhci: Caps:     0x07eb0000 | Caps_1:   0x04100410
[  119.921720] sdhci: Cmd:      0x0000183a | Max curr: 0x00000000
[  119.921747] sdhci: Host ctl2: 0x00000000
[  119.921770] sdhci: ===========================================
[  119.921889] mmc0: starting CMD24 arg 00009200 flags 000000b5
[  119.921941] sdhci: =========== REGISTER DUMP (mmc0)===========
[  119.921976] sdhci: Sys addr: 0x82403600 | Version:  0x00000000
[  119.922007] sdhci: Blk size: 0x00000200 | Blk cnt:  0x00000000
[  119.922038] sdhci: Argument: 0x00020000 | Trn mode: 0x00000003
[  119.922070] sdhci: Present:  0xff880000 | Host ctl: 0x00000023
[  119.922098] sdhci: Power:    0x00000000 | Blk gap:  0x00000000
[  119.922129] sdhci: Wake-up:  0x00000000 | Clock:    0x00000107
[  119.922161] sdhci: Timeout:  0x0000000e | Int stat: 0x00000000
[  119.922193] sdhci: Int enab: 0x107f000b | Sig enab: 0x107f000b
[  119.922223] sdhci: AC12 err: 0x00000000 | Slot int: 0x00001001
[  119.922256] sdhci: Caps:     0x07eb0000 | Caps_1:   0x04100410
[  119.922287] sdhci: Cmd:      0x00000d1a | Max curr: 0x00000000
[  119.922315] sdhci: Host ctl2: 0x00000000
[  119.922338] sdhci: ===========================================
[  119.927417] mmc0: starting CMD13 arg 00020000 flags 00000195
[  119.927481] sdhci: =========== REGISTER DUMP (mmc0)===========
[  119.927523] sdhci: Sys addr: 0x82403800 | Version:  0x00000000
[  119.927554] sdhci: Blk size: 0x00000200 | Blk cnt:  0x00000000
[  119.927586] sdhci: Argument: 0x00009200 | Trn mode: 0x00000003
[  119.927616] sdhci: Present:  0xff880000 | Host ctl: 0x00000023
[  119.927645] sdhci: Power:    0x00000000 | Blk gap:  0x00000000
[  119.927675] sdhci: Wake-up:  0x00000000 | Clock:    0x00000107
[  119.927707] sdhci: Timeout:  0x0000000e | Int stat: 0x00000000
[  119.927740] sdhci: Int enab: 0x107f000b | Sig enab: 0x107f000b
[  119.927772] sdhci: AC12 err: 0x00000000 | Slot int: 0x00001001
[  119.927804] sdhci: Caps:     0x07eb0000 | Caps_1:   0x04100410
[  119.927835] sdhci: Cmd:      0x0000183a | Max curr: 0x00000000
[  119.927864] sdhci: Host ctl2: 0x00000000

[CMD24/CMD13 changes go on like this ...]

Anybody with more insights? Why is the interval between two CMD24 more 
or less in the range of 6ms and the CMD13 follows in varying intervals 
between 1ms to 4ms? What's keeping the driver from bursting CMD24 and 
successive CMD13 requests?

Thanks and best regards
-- 
Joan C. Abelaira


From aisheng.dong at freescale.com  Wed Mar 28 05:53:47 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 28 Mar 2012 17:53:47 +0800
Subject: [PATCH v2 1/1] ARM: imx28: add basic dt support
In-Reply-To: <20120328055801.GA3953@S2100-06.ap.freescale.net>
References: <1332513070-5400-1-git-send-email-b29396@freescale.com>
 <20120328055801.GA3953@S2100-06.ap.freescale.net>
Message-ID: <20120328095346.GA31901@shlinux2.ap.freescale.net>

On Wed, Mar 28, 2012 at 01:58:04PM +0800, Guo Shawn-R65073 wrote:
> On Fri, Mar 23, 2012 at 10:31:10PM +0800, Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
...
> > +/dts-v1/;
> > +/include/ "imx28.dtsi"
> > +
> > +/ {
> > +	model = "Freescale i.MX28 Evaluation Kit";
> > +	compatible = "fsl,imx28-evk", "fsl,imx28";
> > +
> > +	memory {
> > +		device_type = "memory";
> 
> This is already in skeleton.dtsi included by imx28.dtsi.
> 
Correct.

> > +/include/ "skeleton.dtsi"
> > +
> > +/ {
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> 
> These two are already in skeleton.dtsi.
> 
will remove.

> > +			icoll: interrupt-controller at 80000000 {
> > +				compatible = "fsl,imx28-icoll";
> 
> I would expect it be:
> 
> 	compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
> 
> So it can be matched by both imx23 and imx28.
> 
Yes, i can change like that.

> > +				#interrupt-cells = <1>;
> > +			};
> > +
> > diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
> > index c57f996..c776aef 100644
> > --- a/arch/arm/mach-mxs/Kconfig
> > +++ b/arch/arm/mach-mxs/Kconfig
> > @@ -17,6 +17,14 @@ config SOC_IMX28
> >  
> >  comment "MXS platforms:"
> >  
> > +config MACH_MXS_DT
> > +	bool "Support MXS platforms from device tree"
> > +	select SOC_IMX28
> > +	select USE_OF
> > +	help
> > +	  Include support for Freescale MXS platforms(i.MX23 and i.MX28)
> > +	  using the device tree for discovery
> > +
> 
> If I build mxs_defconfig with only MACH_MXS_DT enabled, I got
> 
>   LD      .tmp_vmlinux1
> arch/arm/mach-mxs/built-in.o: In function `mxs_add_amba_device':
> arch/arm/mach-mxs/devices.c:89: undefined reference to `amba_device_register'
> 
It looks ideally we do not need to compile devices.c and devices/* for only dt.

> It's caused by missing "select ARM_AMBA".  For non-dt build, it gets
> selected under "config MXS_HAVE_AMBA_DUART" (mach-mxs/devices/Kconfig).
> 
> I intend to fix it in the following way.
> 
I agree with this temporary fix.

> --8<---
> diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
> index 570d5d5..d076452 100644
> --- a/arch/arm/mach-mxs/Kconfig
> +++ b/arch/arm/mach-mxs/Kconfig
> @@ -7,11 +7,13 @@ config MXS_OCOTP
> 
>  config SOC_IMX23
>         bool
> +       select ARM_AMBA
>         select CPU_ARM926T
>         select HAVE_PWM
> 
>  config SOC_IMX28
>         bool
> +       select ARM_AMBA
>         select CPU_ARM926T
>         select HAVE_PWM
> 
> diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
> index 18b6bf5..2febd62 100644
> --- a/arch/arm/mach-mxs/devices/Kconfig
> +++ b/arch/arm/mach-mxs/devices/Kconfig
> @@ -1,6 +1,5 @@
>  config MXS_HAVE_AMBA_DUART
>         bool
> -       select ARM_AMBA
> 
> --->8--
> 
> > +#include <linux/init.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_platform.h>
> > +#include <asm/mach/arch.h>
> > +#include <asm/mach/time.h>
> > +#include <mach/common.h>
> > +#include <mach/mx28.h>
> 
> This one is not needed.
> 
Correct.

> > +
> > +static int __init imx28_icoll_add_irq_domain(struct device_node *np,
> 
> mxs_icoll_add_irq_domain
> 
> > +				struct device_node *interrupt_parent)
> > +{
> > +	irq_domain_add_simple(np, 0);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct of_device_id mxs_irq_match[] __initconst = {
> > +	{ .compatible = "fsl,imx28-icoll", .data = imx28_icoll_add_irq_domain, },
> 
> "fsl,mxs-icoll"
> 
Will change.

> > +	{ /* sentinel */ }
> > +};
> > +
> > +static void __init mxs_dt_init_irq(void)
> > +{
> > +	icoll_init_irq();
> > +	of_irq_init(mxs_irq_match);
> > +}
> > +
> > +static void __init imx28_timer_init(void)
> > +{
> > +	mx28_clocks_init();
> > +}
> > +
> > +static struct sys_timer imx28_timer = {
> > +	.init = imx28_timer_init,
> > +};
> > +
> > +static void __init imx28_machine_init(void)
> 
> mxs_init_machine(), so that imx23 can use it later and have the
> function name somehow aligned with hook name .init_machine.
> 
I can do it, but, as icoll, that means we're doing things by assuming
no difference between mx23 and mx28 before we really start mx23 dt work.
However, i think at least of_platform_populate should be common.
So i agree to change to mxs_init_machine right now.
If any difference we may change accordingly latter.

> > +{
> > +       of_platform_populate(NULL, of_default_bus_match_table,
> > +		NULL, NULL);
> > +}
> > +
> > +static const char *imx28_dt_compat[] __initdata = {
> 
> mxs_dt_compat
> 
If changed like that, is it reasonable for mx23 to use this
compatible string list?
I planed to have separate compatible string for mx23 and mx28.

> > +	"fsl,imx28",
> > +	"fsl,imx28-evk",
> 
> I would have the list sorted from the most specific to the most
> general.  That said, it's better to have "fsl,imx28" sorted after
> "fsl,imx28-evk".
> 
I prefer to keep the basic one first, then for future boards support
we just add them below rather than insert above the basic one "fsl,imx28".
However, it's really not a big deal.
If you persist to do like that, i can also do it.

> > +	NULL,
> > +};
> > +
> > +DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
> > +	.map_io		= mx28_map_io,
> > +	.init_irq	= mxs_dt_init_irq,
> > +	.timer		= &imx28_timer,
> > +	.init_machine	= imx28_machine_init,
> > +	.dt_compat	= imx28_dt_compat,
> > +	.restart	= mxs_restart,
> > +MACHINE_END
> > -- 
> > 1.7.0.4
> > 
> 

Regards
Dong Aisheng



From mad_soft at inbox.ru  Wed Mar 28 05:42:20 2012
From: mad_soft at inbox.ru (Dmitry Artamonow)
Date: Wed, 28 Mar 2012 13:42:20 +0400
Subject: [PATCH] dma: fix sa11x0-dma build error when CONFIG_PM_SLEEP=n
Message-ID: <1332927740-12557-1-git-send-email-mad_soft@inbox.ru>

Add no-op sa11x0_dma_suspend/sa11x0_dma_resume for !CONFIG_PM_SLEEP case
to fix following build error:

  CC [M]  drivers/dma/sa11x0-dma.o
drivers/dma/sa11x0-dma.c:1064:19: error: 'sa11x0_dma_suspend' undeclared here (not in a function)
drivers/dma/sa11x0-dma.c:1065:18: error: 'sa11x0_dma_resume' undeclared here (not in a function)

Signed-off-by: Dmitry Artamonow <mad_soft at inbox.ru>
---
 drivers/dma/sa11x0-dma.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/dma/sa11x0-dma.c b/drivers/dma/sa11x0-dma.c
index 16a6b48..cac4eed 100644
--- a/drivers/dma/sa11x0-dma.c
+++ b/drivers/dma/sa11x0-dma.c
@@ -1058,6 +1058,9 @@ static int sa11x0_dma_resume(struct device *dev)
 
 	return 0;
 }
+#else
+#define sa11x0_dma_suspend NULL
+#define sa11x0_dma_resume  NULL
 #endif
 
 static const struct dev_pm_ops sa11x0_dma_pm_ops = {
-- 
1.7.5.1.300.gc565c



From linux at arm.linux.org.uk  Wed Mar 28 05:43:51 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 28 Mar 2012 10:43:51 +0100
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <20120314123236.GE3133@opensource.wolfsonmicro.com>
References: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
 <1331242494-3157-1-git-send-email-paul.gortmaker@windriver.com>
 <CAN1soZzDRR4XQ34WDL48=j+Ff8t5fsCFaccqZAKOQ1OAPeDXcA@mail.gmail.com>
 <4F608F4F.8020106@windriver.com>
 <20120314123236.GE3133@opensource.wolfsonmicro.com>
Message-ID: <20120328094351.GB22414@n2100.arm.linux.org.uk>

On Wed, Mar 14, 2012 at 12:32:36PM +0000, Mark Brown wrote:
> On Wed, Mar 14, 2012 at 08:30:07AM -0400, Paul Gortmaker wrote:
> > On 12-03-14 04:38 AM, Haojian Zhuang wrote:
> 
> > > How do you think about Mark's comments? Use dev_name() at here.
> 
> > I'm not sure I quite understand you.  I'd looked up the
> > structs and got their respective value that would be
> > returned by dev_name(), which is what I thought was
> > requested of me.
> 
> Yes, that's what you should do.  Calling dev_name() is only possible if
> you have the struct device and removing the need for the struct device
> is exactly what we're trying to avoid here.

So what the hell is happening here to fix the breakage which the
regulator tree caused in mainline?  From this thread, it looks like
it's been known about since 8th March which is now twenty days ago,
and it's still broken.


From viresh.kumar at st.com  Wed Mar 28 05:30:10 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 28 Mar 2012 15:00:10 +0530
Subject: [PATCH V2 0/7] SPEAr DT support updates
Message-ID: <cover.1332926608.git.viresh.kumar@st.com>

Hello,

This patchset updates DT support for SPEAr3xx and 6xx.
It has following changes:
- updates DT support Mainly for SPEAr3xx family
- updates dma support for SPEAr6xx
- updates defconfig

It has dependency on following patchsets:
- ehci & ohci: http://www.spinics.net/lists/linux-usb/msg60362.html
- rtc: http://lkml.org/lkml/2012/3/26/96
- keyboard: http://www.spinics.net/lists/linux-input/msg19904.html

V2:
- Separate DT_MACHINE_INIT macros are defined per SoC.
- PATCH 1/7 was sent earlier as individual patch, and is now included in this
  patchset for completeness.
- clock support for ehci and ohci added
- plat data for UART PL011 removed as it is not required
- Minor issues fixed

Viresh Kumar (7):
  SPEAr: Use CLKDEV_INIT for defining clk_lookups
  SPEAr3xx: Add clock instance of usb hosts - ehci and ohci 0 and 1
  SPEAr6xx: Add compilation support for dtbs using 'make dtbs'
  SPEAr3xx: Replace printk() with pr_*()
  ARM: SPEAr3xx: Add device-tree support to SPEAr3xx architecture
  SPEAr: Add PL080 DMA support for 3xx and 6xx
  SPEAr: Update defconfigs

 Documentation/arm/SPEAr/overview.txt            |   13 +-
 Documentation/devicetree/bindings/arm/spear.txt |   18 ++
 arch/arm/Makefile                               |    6 +-
 arch/arm/boot/dts/spear300-evb.dts              |  183 +++++++++++
 arch/arm/boot/dts/spear300.dtsi                 |   74 +++++
 arch/arm/boot/dts/spear310-evb.dts              |  111 +++++++
 arch/arm/boot/dts/spear310.dtsi                 |   75 +++++
 arch/arm/boot/dts/spear320-evb.dts              |  112 +++++++
 arch/arm/boot/dts/spear320.dtsi                 |   92 ++++++
 arch/arm/boot/dts/spear3xx.dtsi                 |  153 ++++++++++
 arch/arm/boot/dts/spear600-evb.dts              |    4 +
 arch/arm/boot/dts/spear600.dtsi                 |    8 +
 arch/arm/configs/spear3xx_defconfig             |   52 +++-
 arch/arm/configs/spear6xx_defconfig             |   41 ++-
 arch/arm/mach-spear3xx/Kconfig                  |   40 +--
 arch/arm/mach-spear3xx/Makefile                 |   19 +-
 arch/arm/mach-spear3xx/Makefile.boot            |    4 +
 arch/arm/mach-spear3xx/clock.c                  |  208 +++++++------
 arch/arm/mach-spear3xx/include/mach/generic.h   |   52 ++--
 arch/arm/mach-spear3xx/include/mach/irqs.h      |    6 +-
 arch/arm/mach-spear3xx/include/mach/spear300.h  |    4 +-
 arch/arm/mach-spear3xx/include/mach/spear310.h  |    4 +-
 arch/arm/mach-spear3xx/include/mach/spear320.h  |    4 +-
 arch/arm/mach-spear3xx/spear300.c               |  284 +++++++++++++++--
 arch/arm/mach-spear3xx/spear300_evb.c           |   75 -----
 arch/arm/mach-spear3xx/spear310.c               |  324 ++++++++++++++++++--
 arch/arm/mach-spear3xx/spear310_evb.c           |   81 -----
 arch/arm/mach-spear3xx/spear320.c               |  323 ++++++++++++++++++--
 arch/arm/mach-spear3xx/spear320_evb.c           |   79 -----
 arch/arm/mach-spear3xx/spear3xx.c               |  157 +++++-----
 arch/arm/mach-spear6xx/Makefile.boot            |    2 +
 arch/arm/mach-spear6xx/clock.c                  |   80 ++---
 arch/arm/mach-spear6xx/spear6xx.c               |  372 ++++++++++++++++++++++-
 arch/arm/plat-spear/Kconfig                     |    5 +-
 arch/arm/plat-spear/Makefile                    |    4 +-
 arch/arm/plat-spear/include/plat/pl080.h        |   21 ++
 arch/arm/plat-spear/pl080.c                     |   79 +++++
 37 files changed, 2556 insertions(+), 613 deletions(-)
 create mode 100644 arch/arm/boot/dts/spear300-evb.dts
 create mode 100644 arch/arm/boot/dts/spear300.dtsi
 create mode 100644 arch/arm/boot/dts/spear310-evb.dts
 create mode 100644 arch/arm/boot/dts/spear310.dtsi
 create mode 100644 arch/arm/boot/dts/spear320-evb.dts
 create mode 100644 arch/arm/boot/dts/spear320.dtsi
 create mode 100644 arch/arm/boot/dts/spear3xx.dtsi
 delete mode 100644 arch/arm/mach-spear3xx/spear300_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear310_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear320_evb.c
 create mode 100644 arch/arm/plat-spear/include/plat/pl080.h
 create mode 100644 arch/arm/plat-spear/pl080.c

-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Wed Mar 28 05:30:11 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 28 Mar 2012 15:00:11 +0530
Subject: [PATCH V2 1/7] SPEAr: Use CLKDEV_INIT for defining clk_lookups
In-Reply-To: <cover.1332926608.git.viresh.kumar@st.com>
References: <cover.1332926608.git.viresh.kumar@st.com>
Message-ID: <082491f368250d0079067053efa3e9be54dedb4b.1332926608.git.viresh.kumar@st.com>

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/mach-spear3xx/clock.c |  111 ++++++++++++++++++++--------------------
 arch/arm/mach-spear6xx/clock.c |   80 ++++++++++++++---------------
 2 files changed, 96 insertions(+), 95 deletions(-)

diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6c4841f..6b2cd9b 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -11,6 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/clkdev.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
@@ -652,85 +653,85 @@ static struct clk pwm_clk = {
 
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-	{ .con_id = "apb_pclk",		.clk = &dummy_apb_pclk},
+	CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
 	/* root clks */
-	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
-	{ .con_id = "osc_24m_clk",	.clk = &osc_24m_clk},
+	CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+	CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
 	/* clock derived from 32 KHz osc clk */
-	{ .dev_id = "rtc-spear",	.clk = &rtc_clk},
+	CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
 	/* clock derived from 24 MHz osc clk */
-	{ .con_id = "pll1_clk",		.clk = &pll1_clk},
-	{ .con_id = "pll3_48m_clk",	.clk = &pll3_48m_clk},
-	{ .dev_id = "wdt",		.clk = &wdt_clk},
+	CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+	CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+	CLKDEV_INIT("wdt", NULL, &wdt_clk),
 	/* clock derived from pll1 clk */
-	{ .con_id = "cpu_clk",		.clk = &cpu_clk},
-	{ .con_id = "ahb_clk",		.clk = &ahb_clk},
-	{ .con_id = "uart_synth_clk",	.clk = &uart_synth_clk},
-	{ .con_id = "firda_synth_clk",	.clk = &firda_synth_clk},
-	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
-	{ .con_id = "gpt1_synth_clk",	.clk = &gpt1_synth_clk},
-	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
-	{ .dev_id = "uart",		.clk = &uart_clk},
-	{ .dev_id = "firda",		.clk = &firda_clk},
-	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
-	{ .dev_id = "gpt1",		.clk = &gpt1_clk},
-	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
+	CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+	CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+	CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+	CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+	CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+	CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
+	CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+	CLKDEV_INIT("uart", NULL, &uart_clk),
+	CLKDEV_INIT("firda", NULL, &firda_clk),
+	CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+	CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+	CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
 	/* clock derived from pll3 clk */
-	{ .dev_id = "designware_udc",   .clk = &usbd_clk},
-	{ .con_id = "usbh_clk",		.clk = &usbh_clk},
+	CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+	CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
 	/* clock derived from ahb clk */
-	{ .con_id = "apb_clk",		.clk = &apb_clk},
-	{ .dev_id = "i2c_designware.0",	.clk = &i2c_clk},
-	{ .dev_id = "dma",		.clk = &dma_clk},
-	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
-	{ .dev_id = "gmac",		.clk = &gmac_clk},
-	{ .dev_id = "smi",		.clk = &smi_clk},
-	{ .dev_id = "c3",		.clk = &c3_clk},
+	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+	CLKDEV_INIT("i2c_designware.0", NULL, &i2c_clk),
+	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+	CLKDEV_INIT("gmac", NULL, &gmac_clk),
+	CLKDEV_INIT("smi", NULL, &smi_clk),
+	CLKDEV_INIT("c3", NULL, &c3_clk),
 	/* clock derived from apb clk */
-	{ .dev_id = "adc",		.clk = &adc_clk},
-	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
-	{ .dev_id = "gpio",		.clk = &gpio_clk},
+	CLKDEV_INIT("adc", NULL, &adc_clk),
+	CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
+	CLKDEV_INIT("gpio", NULL, &gpio_clk),
 };
 
 /* array of all spear 300 clock lookups */
 #ifdef CONFIG_MACH_SPEAR300
 static struct clk_lookup spear300_clk_lookups[] = {
-	{ .dev_id = "clcd",		.clk = &clcd_clk},
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
-	{ .dev_id = "gpio1",		.clk = &gpio1_clk},
-	{ .dev_id = "keyboard",		.clk = &kbd_clk},
-	{ .dev_id = "sdhci",		.clk = &sdhci_clk},
+	CLKDEV_INIT("clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+	CLKDEV_INIT("gpio1", NULL, &gpio1_clk),
+	CLKDEV_INIT("keyboard", NULL, &kbd_clk),
+	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
 };
 #endif
 
 /* array of all spear 310 clock lookups */
 #ifdef CONFIG_MACH_SPEAR310
 static struct clk_lookup spear310_clk_lookups[] = {
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
-	{ .con_id = "emi",		.clk = &emi_clk},
-	{ .dev_id = "uart1",		.clk = &uart1_clk},
-	{ .dev_id = "uart2",		.clk = &uart2_clk},
-	{ .dev_id = "uart3",		.clk = &uart3_clk},
-	{ .dev_id = "uart4",		.clk = &uart4_clk},
-	{ .dev_id = "uart5",		.clk = &uart5_clk},
+	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+	CLKDEV_INIT(NULL, "emi", &emi_clk),
+	CLKDEV_INIT("uart1", NULL, &uart1_clk),
+	CLKDEV_INIT("uart2", NULL, &uart2_clk),
+	CLKDEV_INIT("uart3", NULL, &uart3_clk),
+	CLKDEV_INIT("uart4", NULL, &uart4_clk),
+	CLKDEV_INIT("uart5", NULL, &uart5_clk),
 };
 #endif
 
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
 static struct clk_lookup spear320_clk_lookups[] = {
-	{ .dev_id = "clcd",		.clk = &clcd_clk},
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
-	{ .dev_id = "i2c_designware.1",	.clk = &i2c1_clk},
-	{ .con_id = "emi",		.clk = &emi_clk},
-	{ .dev_id = "pwm",		.clk = &pwm_clk},
-	{ .dev_id = "sdhci",		.clk = &sdhci_clk},
-	{ .dev_id = "c_can_platform.0",	.clk = &can0_clk},
-	{ .dev_id = "c_can_platform.1",	.clk = &can1_clk},
-	{ .dev_id = "ssp-pl022.1",	.clk = &ssp1_clk},
-	{ .dev_id = "ssp-pl022.2",	.clk = &ssp2_clk},
-	{ .dev_id = "uart1",		.clk = &uart1_clk},
-	{ .dev_id = "uart2",		.clk = &uart2_clk},
+	CLKDEV_INIT("clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+	CLKDEV_INIT("i2c_designware.1", NULL, &i2c1_clk),
+	CLKDEV_INIT(NULL, "emi", &emi_clk),
+	CLKDEV_INIT("pwm", NULL, &pwm_clk),
+	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
+	CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
+	CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
+	CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
+	CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
+	CLKDEV_INIT("uart1", NULL, &uart1_clk),
+	CLKDEV_INIT("uart2", NULL, &uart2_clk),
 };
 #endif
 
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index f051804..5a46980 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -623,53 +623,53 @@ static struct clk dummy_apb_pclk;
 
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-	{ .con_id = "apb_pclk",		.clk = &dummy_apb_pclk},
+	CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
 	/* root clks */
-	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
-	{ .con_id = "osc_30m_clk",	.clk = &osc_30m_clk},
+	CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+	CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk),
 	/* clock derived from 32 KHz os		 clk */
-	{ .dev_id = "rtc-spear",	.clk = &rtc_clk},
+	CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
 	/* clock derived from 30 MHz os		 clk */
-	{ .con_id = "pll1_clk",		.clk = &pll1_clk},
-	{ .con_id = "pll3_48m_clk",	.clk = &pll3_48m_clk},
-	{ .dev_id = "wdt",		.clk = &wdt_clk},
+	CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+	CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+	CLKDEV_INIT("wdt", NULL, &wdt_clk),
 	/* clock derived from pll1 clk */
-	{ .con_id = "cpu_clk",		.clk = &cpu_clk},
-	{ .con_id = "ahb_clk",		.clk = &ahb_clk},
-	{ .con_id = "uart_synth_clk",	.clk = &uart_synth_clk},
-	{ .con_id = "firda_synth_clk",	.clk = &firda_synth_clk},
-	{ .con_id = "clcd_synth_clk",	.clk = &clcd_synth_clk},
-	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
-	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
-	{ .con_id = "gpt3_synth_clk",	.clk = &gpt3_synth_clk},
-	{ .dev_id = "d0000000.serial",	.clk = &uart0_clk},
-	{ .dev_id = "d0080000.serial",	.clk = &uart1_clk},
-	{ .dev_id = "firda",		.clk = &firda_clk},
-	{ .dev_id = "clcd",		.clk = &clcd_clk},
-	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
-	{ .dev_id = "gpt1",		.clk = &gpt1_clk},
-	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
-	{ .dev_id = "gpt3",		.clk = &gpt3_clk},
+	CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+	CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+	CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+	CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+	CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk),
+	CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+	CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+	CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk),
+	CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk),
+	CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk),
+	CLKDEV_INIT("firda", NULL, &firda_clk),
+	CLKDEV_INIT("clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+	CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+	CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
+	CLKDEV_INIT("gpt3", NULL, &gpt3_clk),
 	/* clock derived from pll3 clk */
-	{ .dev_id = "designware_udc",	.clk = &usbd_clk},
-	{ .con_id = "usbh.0_clk",	.clk = &usbh0_clk},
-	{ .con_id = "usbh.1_clk",	.clk = &usbh1_clk},
+	CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+	CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+	CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
 	/* clock derived from ahb clk */
-	{ .con_id = "apb_clk",		.clk = &apb_clk},
-	{ .dev_id = "d0200000.i2c",	.clk = &i2c_clk},
-	{ .dev_id = "dma",		.clk = &dma_clk},
-	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
-	{ .dev_id = "gmac",		.clk = &gmac_clk},
-	{ .dev_id = "fc000000.flash",	.clk = &smi_clk},
-	{ .dev_id = "d1800000.flash",	.clk = &fsmc_clk},
+	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+	CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
+	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+	CLKDEV_INIT("gmac", NULL, &gmac_clk),
+	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
+	CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk),
 	/* clock derived from apb clk */
-	{ .dev_id = "adc",		.clk = &adc_clk},
-	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
-	{ .dev_id = "ssp-pl022.1",	.clk = &ssp1_clk},
-	{ .dev_id = "ssp-pl022.2",	.clk = &ssp2_clk},
-	{ .dev_id = "f0100000.gpio",	.clk = &gpio0_clk},
-	{ .dev_id = "fc980000.gpio",	.clk = &gpio1_clk},
-	{ .dev_id = "d8100000.gpio",	.clk = &gpio2_clk},
+	CLKDEV_INIT("adc", NULL, &adc_clk),
+	CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
+	CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
+	CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
+	CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk),
+	CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk),
+	CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk),
 };
 
 void __init spear6xx_clk_init(void)
-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Wed Mar 28 05:30:12 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 28 Mar 2012 15:00:12 +0530
Subject: [PATCH V2 2/7] SPEAr3xx: Add clock instance of usb hosts - ehci and
 ohci 0 and 1
In-Reply-To: <cover.1332926608.git.viresh.kumar@st.com>
References: <cover.1332926608.git.viresh.kumar@st.com>
Message-ID: <9cfb8b3efdf277838f4c3adddf4c24d2c770e00b.1332926608.git.viresh.kumar@st.com>

This patch adds following clocks: "usbh.0_clk" and "usbh.1_clk". They are used
by ehci and ohci drivers for SPEAr3xx usb host devices.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/mach-spear3xx/clock.c |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6b2cd9b..47d4535 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -412,6 +412,21 @@ static struct clk usbd_clk = {
 	.recalc = &follow_parent,
 };
 
+/* clock derived from usbh clk */
+/* usbh0 clock */
+static struct clk usbh0_clk = {
+	.flags = ALWAYS_ENABLED,
+	.pclk = &usbh_clk,
+	.recalc = &follow_parent,
+};
+
+/* usbh1 clock */
+static struct clk usbh1_clk = {
+	.flags = ALWAYS_ENABLED,
+	.pclk = &usbh_clk,
+	.recalc = &follow_parent,
+};
+
 /* clock derived from ahb clk */
 /* apb masks structure */
 static struct bus_clk_masks apb_masks = {
@@ -679,6 +694,9 @@ static struct clk_lookup spear_clk_lookups[] = {
 	/* clock derived from pll3 clk */
 	CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
 	CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
+	/* clock derived from usbh clk */
+	CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+	CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
 	/* clock derived from ahb clk */
 	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
 	CLKDEV_INIT("i2c_designware.0", NULL, &i2c_clk),
-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Wed Mar 28 05:30:13 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 28 Mar 2012 15:00:13 +0530
Subject: [PATCH V2 3/7] SPEAr6xx: Add compilation support for dtbs using 'make
 dtbs'
In-Reply-To: <cover.1332926608.git.viresh.kumar@st.com>
References: <cover.1332926608.git.viresh.kumar@st.com>
Message-ID: <bae0539600c2b9720b4d68dd9a19414a77d1626c.1332926608.git.viresh.kumar@st.com>

'make dtbs' compiles all dtbs for a family. For this we need to add entries for
all board dtb's in Makefile.boot file. This patch does it.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/mach-spear6xx/Makefile.boot |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c..af493da 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_BOARD_SPEAR600_DT)	+= spear600-evb.dtb
-- 
1.7.10.rc2.10.gb47606



From aisheng.dong at freescale.com  Wed Mar 28 05:58:58 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Wed, 28 Mar 2012 17:58:58 +0800
Subject: [alsa-devel] [PATCH] ASoC: sgtl5000: fix power on/off of MIC bias
In-Reply-To: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
References: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120328095857.GA29787@shlinux2.ap.freescale.net>

On Wed, Mar 28, 2012 at 03:30:33PM +0800, Shawn Guo wrote:
> From: Lionel Xu <Lionel.Xu at freescale.com>
> 
> There is no sound in the recorded wav, to enable recording, the VAG
> should be powered up, and the mic bias resistor should be set up with
> proper value.
> 
> Signed-off-by: Lionel Xu <lionel.xu at freescale.com>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> Cc: Zeng Zhaoming <zengzm.kernel at gmail.com>
> ---
>  sound/soc/codecs/sgtl5000.c |   14 +++++++++++---
>  1 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
> index d192626..a24299c 100644
> --- a/sound/soc/codecs/sgtl5000.c
> +++ b/sound/soc/codecs/sgtl5000.c
> @@ -132,11 +132,18 @@ static int mic_bias_event(struct snd_soc_dapm_widget *w,
>  		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
>  				SGTL5000_BIAS_R_MASK,
>  				SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
> +
> +		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
> +				SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
Only enable SGTL5000_VAG_POWERUP for mic bias_event may not be sufficient.
IIRC for line-in record, we also need to enable VAG_POWER.
Will verify it later when i'm free.

Regards
Dong Aisheng
>  		break;
>  
>  	case SND_SOC_DAPM_PRE_PMD:
>  		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
> -				SGTL5000_BIAS_R_MASK, 0);
> +				SGTL5000_BIAS_R_MASK,
> +				SGTL5000_BIAS_R_off << SGTL5000_BIAS_R_SHIFT);
> +
> +		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
> +				SGTL5000_VAG_POWERUP, 0);
>  		break;
>  	}
>  	return 0;
> @@ -197,7 +204,7 @@ static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
>  	SND_SOC_DAPM_OUTPUT("HP_OUT"),
>  	SND_SOC_DAPM_OUTPUT("LINE_OUT"),
>  
> -	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
> +	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SND_SOC_NOPM, 0, 0,
>  				mic_bias_event,
>  				SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
>  
> @@ -229,7 +236,8 @@ static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
>  /* routes for sgtl5000 */
>  static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
>  	{"Capture Mux", "LINE_IN", "LINE_IN"},	/* line_in --> adc_mux */
> -	{"Capture Mux", "MIC_IN", "MIC_IN"},	/* mic_in --> adc_mux */
> +	{"Mic Bias", NULL, "MIC_IN"},		/* mic_in --> mic bias */
> +	{"Capture Mux", "MIC_IN", "Mic Bias"},	/* mic bias --> adc_mux */
>  
>  	{"ADC", NULL, "Capture Mux"},		/* adc_mux --> adc */
>  	{"AIFOUT", NULL, "ADC"},		/* adc --> i2s_out */
> -- 
> 1.7.4.1
> 
> 
> _______________________________________________
> Alsa-devel mailing list
> Alsa-devel at alsa-project.org
> http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
> 



From grinberg at compulab.co.il  Wed Mar 28 05:51:18 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 28 Mar 2012 11:51:18 +0200
Subject: [PATCH] ARM: OMAP3: cm-t35: add support for power off
Message-ID: <1332928278-6582-1-git-send-email-grinberg@compulab.co.il>

Enable the power off feature of the TPS65930 on-board PMIC.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
---
 arch/arm/mach-omap2/board-cm-t35.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 8770be1..46275c6 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -499,6 +499,10 @@ static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
 	.setup          = cm_t35_twl_gpio_setup,
 };
 
+static struct twl4030_power_data cm_t35_power_data = {
+	.use_poweroff	= true,
+};
+
 static struct twl4030_platform_data cm_t35_twldata = {
 	/* platform_data for children goes here */
 	.keypad		= &cm_t35_kp_data,
@@ -506,6 +510,7 @@ static struct twl4030_platform_data cm_t35_twldata = {
 	.vmmc1		= &cm_t35_vmmc1,
 	.vsim		= &cm_t35_vsim,
 	.vio		= &cm_t35_vio,
+	.power		= &cm_t35_power_data,
 };
 
 static void __init cm_t35_init_i2c(void)
-- 
1.7.3.4



From B29396 at freescale.com  Wed Mar 28 05:52:15 2012
From: B29396 at freescale.com (Dong Aisheng-B29396)
Date: Wed, 28 Mar 2012 09:52:15 +0000
Subject: [alsa-devel] [PATCH] ASoC: sgtl5000: fix power on/off of MIC bias
In-Reply-To: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
References: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <7FE21149F4667147B645348EC605788514EDFF@039-SN2MPN1-011.039d.mgd.msft.net>

> -----Original Message-----
> From: alsa-devel-bounces at alsa-project.org [mailto:alsa-devel-
> bounces at alsa-project.org] On Behalf Of Shawn Guo
> Sent: Wednesday, March 28, 2012 3:31 PM
> To: alsa-devel at alsa-project.org
> Cc: Xu Lionel-R63889; Mark Brown; Zeng at alsa-project.org; Zhaoming; Shawn
> Guo; Xu Lionel-R63889; linux-arm-kernel at lists.infradead.org
> Subject: [alsa-devel] [PATCH] ASoC: sgtl5000: fix power on/off of MIC
> bias
> 
> From: Lionel Xu <Lionel.Xu at freescale.com>
> 
> There is no sound in the recorded wav, to enable recording, the VAG
> should be powered up, and the mic bias resistor should be set up with
> proper value.
> 
> Signed-off-by: Lionel Xu <lionel.xu at freescale.com>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> Cc: Zeng Zhaoming <zengzm.kernel at gmail.com>
> ---
>  sound/soc/codecs/sgtl5000.c |   14 +++++++++++---
>  1 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
> index d192626..a24299c 100644
> --- a/sound/soc/codecs/sgtl5000.c
> +++ b/sound/soc/codecs/sgtl5000.c
> @@ -132,11 +132,18 @@ static int mic_bias_event(struct
> snd_soc_dapm_widget *w,
>  		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
>  				SGTL5000_BIAS_R_MASK,
>  				SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
> +
> +		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
> +				SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
Did you test line-in record?
IIRC for line-in record, it may also need VAG_POWER up.
Then only enable VAG_POWER for mic_bias_event may not be sufficient.
Will verify it latter when I'm free.

Regards
Dong Aisheng

>  		break;
> 
>  	case SND_SOC_DAPM_PRE_PMD:
>  		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
> -				SGTL5000_BIAS_R_MASK, 0);
> +				SGTL5000_BIAS_R_MASK,
> +				SGTL5000_BIAS_R_off << SGTL5000_BIAS_R_SHIFT);
> +
> +		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
> +				SGTL5000_VAG_POWERUP, 0);
>  		break;
>  	}
>  	return 0;
> @@ -197,7 +204,7 @@ static const struct snd_soc_dapm_widget
> sgtl5000_dapm_widgets[] = {
>  	SND_SOC_DAPM_OUTPUT("HP_OUT"),
>  	SND_SOC_DAPM_OUTPUT("LINE_OUT"),
> 
> -	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
> +	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SND_SOC_NOPM, 0, 0,
>  				mic_bias_event,
>  				SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
> 
> @@ -229,7 +236,8 @@ static const struct snd_soc_dapm_widget
> sgtl5000_dapm_widgets[] = {
>  /* routes for sgtl5000 */
>  static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
>  	{"Capture Mux", "LINE_IN", "LINE_IN"},	/* line_in --> adc_mux */
> -	{"Capture Mux", "MIC_IN", "MIC_IN"},	/* mic_in --> adc_mux */
> +	{"Mic Bias", NULL, "MIC_IN"},		/* mic_in --> mic bias */
> +	{"Capture Mux", "MIC_IN", "Mic Bias"},	/* mic bias --> adc_mux
> */
> 
>  	{"ADC", NULL, "Capture Mux"},		/* adc_mux --> adc */
>  	{"AIFOUT", NULL, "ADC"},		/* adc --> i2s_out */
> --
> 1.7.4.1
> 
> 
> _______________________________________________
> Alsa-devel mailing list
> Alsa-devel at alsa-project.org
> http://mailman.alsa-project.org/mailman/listinfo/alsa-devel




From broonie at opensource.wolfsonmicro.com  Wed Mar 28 05:54:50 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 10:54:50 +0100
Subject: [PATCH v3 0/6] mmc: sdhci-s3c: Rework platform data and add
 device tree support
In-Reply-To: <87k426vy9r.fsf@laptop.org>
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>
 <003401cce730$baf979a0$30ec6ce0$%kim@samsung.com>
 <m2aa4pkq5g.fsf@bob.laptop.org> <4F3CFEED.6060206@samsung.com>
 <m239abgc32.fsf@bob.laptop.org>
 <00b901ccf08d$2fc18b50$8f44a1f0$%kim@samsung.com>
 <m2vcn0496y.fsf@bob.laptop.org> <87k426vy9r.fsf@laptop.org>
Message-ID: <20120328095450.GA23005@sirena.org.uk>

On Tue, Mar 27, 2012 at 11:50:24AM -0400, Chris Ball wrote:
> On Tue, Feb 21 2012, Chris Ball wrote:
> > On Tue, Feb 21 2012, Kukjin Kim wrote:

> >> I created topic branch for this we talked. You can pull that following:
> >>   git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
> >> v3.4-for-cjb

> >> If any problems, please kindly let me know.

> > Pushed to mmc-next, thanks.  (I'm expecting that you'll do the merge
> > to Linus.)

> I was expecting you to merge these patches, but they aren't in the
> arm-soc tree and haven't been sent to Linus, and we're in the last few
> days of the merge window.

> As a result I'm dropping this tree -- and all of the patches that I
> have on top of it -- from mmc-next so that I can get a pull request
> out.  This means that I'm dropping:

If they're already in your tree why not just send them to Linus?  Given
that everything's in git I don't understand why you'd need Kukjin to
push them separately or what the benefit of that would be?

This is all extremely frustrating fromm the contributor point of view.


From viresh.kumar at st.com  Wed Mar 28 05:41:45 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 28 Mar 2012 15:11:45 +0530
Subject: [PATCH V2 4/7] SPEAr3xx: Replace printk() with pr_*()
In-Reply-To: <cover.1332926608.git.viresh.kumar@st.com>
References: <cover.1332926608.git.viresh.kumar@st.com>
Message-ID: <f678c2fee8c82f7e8a7aef197e6d429a51330361.1332926608.git.viresh.kumar@st.com>

For better print logs/messages, it is advisable to use pr_*() routines instead
of directly calling printks. This patch removes direct calling of printks for
spear3xx.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/mach-spear3xx/spear300.c |    8 +++++---
 arch/arm/mach-spear3xx/spear310.c |   13 +++++++------
 arch/arm/mach-spear3xx/spear320.c |   11 ++++++-----
 arch/arm/mach-spear3xx/spear3xx.c |    2 ++
 4 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db668..adee72b 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr300: " fmt
+
 #include <linux/types.h>
 #include <linux/amba/pl061.h>
 #include <linux/ptrace.h>
@@ -447,7 +449,7 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 	if (shirq_ras1.regs.base) {
 		ret = spear_shirq_register(&shirq_ras1);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ\n");
+			pr_err("Error registering Shared IRQ\n");
 	}
 
 	/* pmx initialization */
@@ -459,8 +461,8 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 	if (pmx_driver.base) {
 		ret = pmx_register(&pmx_driver);
 		if (ret)
-			printk(KERN_ERR "padmux: registration failed. err no"
-					": %d\n", ret);
+			pr_err("padmux: registration failed. err no: %d\n",
+					ret);
 		/* Free Mapping, device selection already done */
 		iounmap(pmx_driver.base);
 	}
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6f..b7c2876 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr310: " fmt
+
 #include <linux/ptrace.h>
 #include <asm/irq.h>
 #include <plat/shirq.h>
@@ -274,25 +276,25 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 		shirq_ras1.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras1);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 1\n");
+			pr_err("Error registering Shared IRQ 1\n");
 
 		/* shirq 2 */
 		shirq_ras2.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras2);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 2\n");
+			pr_err("Error registering Shared IRQ 2\n");
 
 		/* shirq 3 */
 		shirq_ras3.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras3);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 3\n");
+			pr_err("Error registering Shared IRQ 3\n");
 
 		/* shirq 4 */
 		shirq_intrcomm_ras.regs.base = base;
 		ret = spear_shirq_register(&shirq_intrcomm_ras);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 4\n");
+			pr_err("Error registering Shared IRQ 4\n");
 	}
 
 	/* pmx initialization */
@@ -303,6 +305,5 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 
 	ret = pmx_register(&pmx_driver);
 	if (ret)
-		printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-				ret);
+		pr_err("padmux: registration failed. err no: %d\n", ret);
 }
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf19..7bd39c0 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr320: " fmt
+
 #include <linux/ptrace.h>
 #include <asm/irq.h>
 #include <plat/shirq.h>
@@ -527,19 +529,19 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 		shirq_ras1.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras1);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 1\n");
+			pr_err("Error registering Shared IRQ 1\n");
 
 		/* shirq 3 */
 		shirq_ras3.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras3);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 3\n");
+			pr_err("Error registering Shared IRQ 3\n");
 
 		/* shirq 4 */
 		shirq_intrcomm_ras.regs.base = base;
 		ret = spear_shirq_register(&shirq_intrcomm_ras);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 4\n");
+			pr_err("Error registering Shared IRQ 4\n");
 	}
 
 	/* pmx initialization */
@@ -550,6 +552,5 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 
 	ret = pmx_register(&pmx_driver);
 	if (ret)
-		printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-				ret);
+		pr_err("padmux: registration failed. err no: %d\n", ret);
 }
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c3..a236925 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr3xx: " fmt
+
 #include <linux/types.h>
 #include <linux/amba/pl061.h>
 #include <linux/ptrace.h>
-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Wed Mar 28 05:41:47 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 28 Mar 2012 15:11:47 +0530
Subject: [PATCH V2 6/7] SPEAr: Add PL080 DMA support for 3xx and 6xx
In-Reply-To: <cover.1332926608.git.viresh.kumar@st.com>
References: <cover.1332926608.git.viresh.kumar@st.com>
Message-ID: <65fdac4686742c08b01d241770b36955ed975ea6.1332926608.git.viresh.kumar@st.com>

Both SPEAr3xx and SPEAr6xx families have one instance of ARM PL080 DMA
controller. This patch adds in support for that.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/boot/dts/spear300-evb.dts            |    4 +
 arch/arm/boot/dts/spear310-evb.dts            |    4 +
 arch/arm/boot/dts/spear320-evb.dts            |    4 +
 arch/arm/boot/dts/spear3xx.dtsi               |    8 +
 arch/arm/boot/dts/spear600-evb.dts            |    4 +
 arch/arm/boot/dts/spear600.dtsi               |    8 +
 arch/arm/mach-spear3xx/clock.c                |    2 +-
 arch/arm/mach-spear3xx/include/mach/generic.h |    6 +-
 arch/arm/mach-spear3xx/spear300.c             |  191 +++++++++++++
 arch/arm/mach-spear3xx/spear310.c             |  190 +++++++++++++
 arch/arm/mach-spear3xx/spear320.c             |  190 +++++++++++++
 arch/arm/mach-spear3xx/spear3xx.c             |   19 ++
 arch/arm/mach-spear6xx/clock.c                |    2 +-
 arch/arm/mach-spear6xx/spear6xx.c             |  372 ++++++++++++++++++++++++-
 arch/arm/plat-spear/Makefile                  |    2 +-
 arch/arm/plat-spear/include/plat/pl080.h      |   21 ++
 arch/arm/plat-spear/pl080.c                   |   79 ++++++
 17 files changed, 1101 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/plat-spear/include/plat/pl080.h
 create mode 100644 arch/arm/plat-spear/pl080.c

diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index f2ee991..eaecc29 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -29,6 +29,10 @@
 			status = "okay";
 		};
 
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		fsmc: flash at 94000000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index ec19d7b..c86af33 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -25,6 +25,10 @@
 	};
 
 	ahb {
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		fsmc: flash at 44000000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index 5681a97..d43de71 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -29,6 +29,10 @@
 			status = "okay";
 		};
 
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		fsmc: flash at 4c000000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index a31e52e..c3f3c41 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -38,6 +38,14 @@
 			#interrupt-cells = <1>;
 		};
 
+		dma at fc400000 {
+			compatible = "arm,pl080", "arm,primecell";
+			reg = <0xfc400000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <8>;
+			status = "disabled";
+		};
+
 		gmac: eth at e0800000 {
 			compatible = "st,spear600-gmac";
 			reg = <0xe0800000 0x8000>;
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e..790a7a8 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,6 +24,10 @@
 	};
 
 	ahb {
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		gmac: ethernet at e0800000 {
 			phy-mode = "gmii";
 			status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885..d777e3a 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
 			#interrupt-cells = <1>;
 		};
 
+		dma at fc400000 {
+			compatible = "arm,pl080", "arm,primecell";
+			reg = <0xfc400000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <10>;
+			status = "disabled";
+		};
+
 		gmac: ethernet at e0800000 {
 			compatible = "st,spear600-gmac";
 			reg = <0xe0800000 0x8000>;
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6833d08..4eaff9b 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -701,7 +701,7 @@ static struct clk_lookup spear_clk_lookups[] = {
 	/* clock derived from ahb clk */
 	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
 	CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
-	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
 	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
 	CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
 	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 8af11da..153f68b 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,6 +14,7 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
 
+#include <linux/amba/pl08x.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
@@ -33,11 +34,14 @@
 /* Add spear3xx family device structure declarations here */
 extern struct sys_timer spear3xx_timer;
 extern struct pl022_ssp_controller pl022_plat_data;
+extern struct pl08x_platform_data pl080_plat_data;
 
 /* SPEAr3xx auxdata to pass platform data */
 #define SPEAR3XX_AUXDATA_LOOKUP					\
 	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, \
-			&pl022_plat_data)
+			&pl022_plat_data),			\
+	OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, \
+			&pl080_plat_data)
 
 /* Add spear3xx family function declarations here */
 void __init spear_setup_timer(void);
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 1a1bd93..5fc5213 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -13,6 +13,7 @@
 
 #define pr_fmt(fmt) "SPEAr300: " fmt
 
+#include <linux/amba/pl08x.h>
 #include <linux/of_platform.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -440,6 +441,193 @@ static struct pmx_dev *spear300_evb_pmx_devs[] = {
 	&spear300_pmx_gpio1,
 };
 
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear300_dma_info[] = {
+	{
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	},
+};
+
 /* Add SPEAr300 auxdata to pass platform data */
 static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
 	SPEAR3XX_AUXDATA_LOOKUP,
@@ -450,6 +638,9 @@ static void __init spear300_dt_init(void)
 {
 	int ret = -EINVAL;
 
+	pl080_plat_data.slave_channels = spear300_dma_info;
+	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
+
 	of_platform_populate(NULL, of_default_bus_match_table,
 			spear300_auxdata_lookup, NULL);
 
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 0b58313..dccef4b 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -284,6 +284,193 @@ static struct pmx_dev *spear310_evb_pmx_devs[] = {
 	&spear310_pmx_tdm0,
 };
 
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear310_dma_info[] = {
+	{
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart2_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart2_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart3_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart3_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart4_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart4_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart5_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart5_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	},
+};
+
 /* uart devices plat data */
 static struct amba_pl011_data spear310_uart_data[] = {
 	{
@@ -330,6 +517,9 @@ static void __init spear310_dt_init(void)
 	void __iomem *base;
 	int ret = 0;
 
+	pl080_plat_data.slave_channels = spear310_dma_info;
+	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
+
 	of_platform_populate(NULL, of_default_bus_match_table,
 			spear310_auxdata_lookup, NULL);
 
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index fb9b17e..1512711 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -535,6 +535,193 @@ static struct pmx_dev *spear320_evb_pmx_devs[] = {
 	&spear320_pmx_mii1,
 };
 
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear320_dma_info[] = {
+	{
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c0_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c0_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp1_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp1_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp2_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp2_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c1_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c1_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c2_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c2_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "rs485_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "rs485_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	},
+};
+
 static struct pl022_ssp_controller spear320_ssp_data[] = {
 	{
 		.bus_id = 1,
@@ -584,6 +771,9 @@ static void __init spear320_dt_init(void)
 	void __iomem *base;
 	int ret = 0;
 
+	pl080_plat_data.slave_channels = spear320_dma_info;
+	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
+
 	of_platform_populate(NULL, of_default_bus_match_table,
 			spear320_auxdata_lookup, NULL);
 
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index f074638..9585cec 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -17,7 +17,9 @@
 #include <linux/amba/pl08x.h>
 #include <linux/of_irq.h>
 #include <linux/io.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
@@ -465,6 +467,23 @@ struct pl022_ssp_controller pl022_plat_data = {
 	.num_chipselect = 2,
 };
 
+/* dmac device registration */
+struct pl08x_platform_data pl080_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl080_get_signal,
+	.put_signal = pl080_put_signal,
+};
+
 /* Following will create static virtual/physical mappings */
 struct map_desc spear3xx_io_desc[] __initdata = {
 	{
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 5a46980..adadef2 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -657,7 +657,7 @@ static struct clk_lookup spear_clk_lookups[] = {
 	/* clock derived from ahb clk */
 	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
 	CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
-	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
 	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
 	CLKDEV_INIT("gmac", NULL, &gmac_clk),
 	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14..5b9e30f 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,15 +13,377 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/amba/pl08x.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
+/* dmac device registration */
+static struct pl08x_channel_data spear600_dma_info[] = {
+	{
+		.bus_id = "ssp1_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp1_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp2_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp2_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ext0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	},
+};
+
+struct pl08x_platform_data pl080_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl080_get_signal,
+	.put_signal = pl080_put_signal,
+	.slave_channels = spear600_dma_info,
+	.num_slave_channels = ARRAY_SIZE(spear600_dma_info),
+};
+
 /* Following will create static virtual/physical mappings */
 static struct map_desc spear6xx_io_desc[] __initdata = {
 	{
@@ -92,9 +454,17 @@ struct sys_timer spear6xx_timer = {
 	.init = spear6xx_timer_init,
 };
 
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
+			&pl080_plat_data),
+	{}
+};
+
 static void __init spear600_dt_init(void)
 {
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table,
+			spear6xx_auxdata_lookup, NULL);
 }
 
 static const char *spear600_dt_board_compat[] = {
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 4b906bb..cc87823 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
 #
 
 # Common support
-obj-y	:= clock.o restart.o time.o
+obj-y	:= clock.o restart.o time.o pl080.o
 
 obj-$(CONFIG_ARCH_SPEAR3XX_DT)	+= shirq.o padmux.o
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644
index 0000000..e14a3e4
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/plat-spear/include/plat/pl080.h
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PL080_H
+#define __PLAT_PL080_H
+
+struct pl08x_dma_chan;
+int pl080_get_signal(struct pl08x_dma_chan *ch);
+void pl080_put_signal(struct pl08x_dma_chan *ch);
+
+#endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644
index 0000000..d53d75e
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,79 @@
+/*
+ * arch/arm/plat-spear/pl080.c
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/bus.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spinlock_types.h>
+#include <mach/misc_regs.h>
+
+static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
+
+struct {
+	unsigned char busy;
+	unsigned char val;
+} signals[16] = {{0, 0}, };
+
+int pl080_get_signal(struct pl08x_dma_chan *ch)
+{
+	const struct pl08x_channel_data *cd = ch->cd;
+	unsigned int signal = cd->min_signal, val;
+	unsigned long flags;
+
+	spin_lock_irqsave(&lock, flags);
+
+	/* Return if signal is already acquired by somebody else */
+	if (signals[signal].busy &&
+			(signals[signal].val != cd->muxval)) {
+		spin_unlock_irqrestore(&lock, flags);
+		return -EBUSY;
+	}
+
+	/* If acquiring for the first time, configure it */
+	if (!signals[signal].busy) {
+		val = readl(DMA_CHN_CFG);
+
+		/*
+		 * Each request line has two bits in DMA_CHN_CFG register. To
+		 * goto the bits of current request line, do left shift of
+		 * value by 2 * signal number.
+		 */
+		val &= ~(0x3 << (signal * 2));
+		val |= cd->muxval << (signal * 2);
+		writel(val, DMA_CHN_CFG);
+	}
+
+	signals[signal].busy++;
+	signals[signal].val = cd->muxval;
+	spin_unlock_irqrestore(&lock, flags);
+
+	return signal;
+}
+
+void pl080_put_signal(struct pl08x_dma_chan *ch)
+{
+	const struct pl08x_channel_data *cd = ch->cd;
+	unsigned long flags;
+
+	spin_lock_irqsave(&lock, flags);
+
+	/* if signal is not used */
+	if (!signals[cd->min_signal].busy)
+		BUG();
+
+	signals[cd->min_signal].busy--;
+
+	spin_unlock_irqrestore(&lock, flags);
+}
-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Wed Mar 28 05:41:48 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 28 Mar 2012 15:11:48 +0530
Subject: [PATCH V2 7/7] SPEAr: Update defconfigs
In-Reply-To: <cover.1332926608.git.viresh.kumar@st.com>
References: <cover.1332926608.git.viresh.kumar@st.com>
Message-ID: <eb2b18266fd36d198fa2e7bfb1d8399ea559167a.1332926608.git.viresh.kumar@st.com>

Recently device tree support is added for SPEAr3xx & SPEAr6xx and we must
upgrade defconfig for that to get compiled. This patches does it.

There are few more rearrangements done in defconfig automatically, when i run
make savedefconfig.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/configs/spear3xx_defconfig |   52 +++++++++++++++++++++++++++--------
 arch/arm/configs/spear6xx_defconfig |   41 +++++++++++++++++++++------
 2 files changed, 74 insertions(+), 19 deletions(-)

diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f..1fba278 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,67 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
-CONFIG_BOARD_SPEAR300_EVB=y
-CONFIG_BOARD_SPEAR310_EVB=y
-CONFIG_BOARD_SPEAR320_EVB=y
+CONFIG_MACH_SPEAR300_DT=y
+CONFIG_MACH_SPEAR310_DT=y
+CONFIG_MACH_SPEAR320_DT=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
 # CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +73,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -48,6 +80,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e83..cf94bc7 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,58 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
-CONFIG_BOARD_SPEAR600_EVB=y
+CONFIG_BOARD_SPEAR600_DT=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +64,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -44,6 +71,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Wed Mar 28 05:41:46 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 28 Mar 2012 15:11:46 +0530
Subject: [PATCH V2 5/7] ARM: SPEAr3xx: Add device-tree support to SPEAr3xx
 architecture
In-Reply-To: <cover.1332926608.git.viresh.kumar@st.com>
References: <cover.1332926608.git.viresh.kumar@st.com>
Message-ID: <f4ad79023c6155d4de7e87c3cd798aadd493454e.1332926608.git.viresh.kumar@st.com>

This patch adds a generic target for SPEAr3xx machines that can be configured
via the device-tree. Currently the following devices are supported via the
devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- PL110 CLCD
- SP805 WDT
- Synopsys DW I2C
- Synopsys DW ethernet
- ST FSMC-NAND
- ST SPEAR-SMI
- ST SPEAR-KEYBOARD
- ST SPEAR-RTC
- ARASAN SDHCI-SPEAR
- SPEAR-EHCI
- SPEAR-OHCI

Other peripheral devices will follow in later patches.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 Documentation/arm/SPEAr/overview.txt            |   13 +-
 Documentation/devicetree/bindings/arm/spear.txt |   18 +++
 arch/arm/Makefile                               |    6 +-
 arch/arm/boot/dts/spear300-evb.dts              |  179 +++++++++++++++++++++++
 arch/arm/boot/dts/spear300.dtsi                 |   74 ++++++++++
 arch/arm/boot/dts/spear310-evb.dts              |  107 ++++++++++++++
 arch/arm/boot/dts/spear310.dtsi                 |   75 ++++++++++
 arch/arm/boot/dts/spear320-evb.dts              |  108 ++++++++++++++
 arch/arm/boot/dts/spear320.dtsi                 |   92 ++++++++++++
 arch/arm/boot/dts/spear3xx.dtsi                 |  145 ++++++++++++++++++
 arch/arm/mach-spear3xx/Kconfig                  |   40 ++---
 arch/arm/mach-spear3xx/Makefile                 |   19 +--
 arch/arm/mach-spear3xx/Makefile.boot            |    4 +
 arch/arm/mach-spear3xx/clock.c                  |  129 ++++++++--------
 arch/arm/mach-spear3xx/include/mach/generic.h   |   48 +++---
 arch/arm/mach-spear3xx/include/mach/irqs.h      |    6 +-
 arch/arm/mach-spear3xx/include/mach/spear300.h  |    4 +-
 arch/arm/mach-spear3xx/include/mach/spear310.h  |    4 +-
 arch/arm/mach-spear3xx/include/mach/spear320.h  |    4 +-
 arch/arm/mach-spear3xx/spear300.c               |   85 ++++++++---
 arch/arm/mach-spear3xx/spear300_evb.c           |   75 ----------
 arch/arm/mach-spear3xx/spear310.c               |  121 +++++++++++++--
 arch/arm/mach-spear3xx/spear310_evb.c           |   81 ----------
 arch/arm/mach-spear3xx/spear320.c               |  122 +++++++++++++--
 arch/arm/mach-spear3xx/spear320_evb.c           |   79 ----------
 arch/arm/mach-spear3xx/spear3xx.c               |  136 +++++++++--------
 arch/arm/plat-spear/Kconfig                     |    5 +-
 arch/arm/plat-spear/Makefile                    |    2 +-
 28 files changed, 1273 insertions(+), 508 deletions(-)
 create mode 100644 arch/arm/boot/dts/spear300-evb.dts
 create mode 100644 arch/arm/boot/dts/spear300.dtsi
 create mode 100644 arch/arm/boot/dts/spear310-evb.dts
 create mode 100644 arch/arm/boot/dts/spear310.dtsi
 create mode 100644 arch/arm/boot/dts/spear320-evb.dts
 create mode 100644 arch/arm/boot/dts/spear320.dtsi
 create mode 100644 arch/arm/boot/dts/spear3xx.dtsi
 delete mode 100644 arch/arm/mach-spear3xx/spear300_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear310_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear320_evb.c

diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c..28a9af9 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -17,14 +17,14 @@ Introduction
   SPEAr (Platform)
 	- SPEAr3XX (3XX SOC series, based on ARM9)
 		- SPEAr300 (SOC)
-			- SPEAr300_EVB (Evaluation Board)
+			- SPEAr300 Evaluation Board
 		- SPEAr310 (SOC)
-			- SPEAr310_EVB (Evaluation Board)
+			- SPEAr310 Evaluation Board
 		- SPEAr320 (SOC)
-			- SPEAr320_EVB (Evaluation Board)
+			- SPEAr320 Evaluation Board
 	- SPEAr6XX (6XX SOC series, based on ARM9)
 		- SPEAr600 (SOC)
-			- SPEAr600_EVB (Evaluation Board)
+			- SPEAr600 Evaluation Board
 	- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
 		- SPEAr1300 (SOC)
 
@@ -51,10 +51,11 @@ Introduction
   Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
   spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
   specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
-  mach-spear* also contains board specific files for each machine type.
+  mach-spear* doesn't contains board specific files as they fully support
+  Flattened Device Tree.
 
 
   Document Author
   ---------------
 
-  Viresh Kumar, (c) 2010 ST Microelectronics
+  Viresh Kumar <viresh.kumar at st.com>, (c) 2010-2012 ST Microelectronics
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
index f8e54f0..aa5f355 100644
--- a/Documentation/devicetree/bindings/arm/spear.txt
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -6,3 +6,21 @@ Boards with the ST SPEAr600 SoC shall have the following properties:
 Required root node property:
 
 compatible = "st,spear600";
+
+Boards with the ST SPEAr300 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear300";
+
+Boards with the ST SPEAr310 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear310";
+
+Boards with the ST SPEAr320 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear320";
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 047a207..0f0acd9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -192,9 +192,9 @@ machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
 machine-$(CONFIG_ARCH_VT8500)		:= vt8500
 machine-$(CONFIG_ARCH_W90X900)		:= w90x900
 machine-$(CONFIG_FOOTBRIDGE)		:= footbridge
-machine-$(CONFIG_MACH_SPEAR300)		:= spear3xx
-machine-$(CONFIG_MACH_SPEAR310)		:= spear3xx
-machine-$(CONFIG_MACH_SPEAR320)		:= spear3xx
+machine-$(CONFIG_MACH_SPEAR300_DT)	:= spear3xx
+machine-$(CONFIG_MACH_SPEAR310_DT)	:= spear3xx
+machine-$(CONFIG_MACH_SPEAR320_DT)	:= spear3xx
 machine-$(CONFIG_MACH_SPEAR600)		:= spear6xx
 machine-$(CONFIG_ARCH_ZYNQ)		:= zynq
 
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644
index 0000000..f2ee991
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,179 @@
+/*
+ * DTS file for SPEAr300 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear300.dtsi"
+
+/ {
+	model = "ST SPEAr300 Evaluation Board";
+	compatible = "st,spear300-evb", "st,spear300";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		clcd at 60000000 {
+			status = "okay";
+		};
+
+		fsmc: flash at 94000000 {
+			status = "okay";
+		};
+
+		gmac: eth at e0800000 {
+			status = "okay";
+		};
+
+		sdhci at 70000000 {
+			int-gpio = <&gpio1 0 0>;
+			power-gpio = <&gpio1 2 1>;
+			status = "okay";
+		};
+
+		smi: flash at fc000000 {
+			status = "okay";
+		};
+
+		spi0: spi at d0100000 {
+			status = "okay";
+		};
+
+		ehci at e1800000 {
+			status = "okay";
+		};
+
+		ohci at e1900000 {
+			status = "okay";
+		};
+
+		ohci at e2100000 {
+			status = "okay";
+		};
+
+		apb {
+			gpio0: gpio at fc980000 {
+			       status = "okay";
+			};
+
+			gpio1: gpio at a9000000 {
+			       status = "okay";
+			};
+
+			i2c0: i2c at d0180000 {
+			       status = "okay";
+			};
+
+			kbd at a0000000 {
+				linux,keymap = < 0x00010000
+						 0x00020100
+						 0x00030200
+						 0x00040300
+						 0x00050400
+						 0x00060500
+						 0x00070600
+						 0x00080700
+						 0x00090800
+						 0x000a0001
+						 0x000c0101
+						 0x000d0201
+						 0x000e0301
+						 0x000f0401
+						 0x00100501
+						 0x00110601
+						 0x00120701
+						 0x00130801
+						 0x00140002
+						 0x00150102
+						 0x00160202
+						 0x00170302
+						 0x00180402
+						 0x00190502
+						 0x001a0602
+						 0x001b0702
+						 0x001c0802
+						 0x001d0003
+						 0x001e0103
+						 0x001f0203
+						 0x00200303
+						 0x00210403
+						 0x00220503
+						 0x00230603
+						 0x00240703
+						 0x00250803
+						 0x00260004
+						 0x00270104
+						 0x00280204
+						 0x00290304
+						 0x002a0404
+						 0x002b0504
+						 0x002c0604
+						 0x002d0704
+						 0x002e0804
+						 0x002f0005
+						 0x00300105
+						 0x00310205
+						 0x00320305
+						 0x00330405
+						 0x00340505
+						 0x00350605
+						 0x00360705
+						 0x00370805
+						 0x00380006
+						 0x00390106
+						 0x003a0206
+						 0x003b0306
+						 0x003c0406
+						 0x003d0506
+						 0x003e0606
+						 0x003f0706
+						 0x00400806
+						 0x00410007
+						 0x00420107
+						 0x00430207
+						 0x00440307
+						 0x00450407
+						 0x00460507
+						 0x00470607
+						 0x00480707
+						 0x00490807
+						 0x004a0008
+						 0x004b0108
+						 0x004c0208
+						 0x004d0308
+						 0x004e0408
+						 0x004f0508
+						 0x00500608
+						 0x00510708
+						 0x00520808 >;
+			       autorepeat;
+			       st,mode = <0>;
+			       status = "okay";
+			};
+
+			rtc at fc900000 {
+			       status = "okay";
+			};
+
+			serial at d0000000 {
+			       status = "okay";
+			};
+
+			wdt at fc880000 {
+			       status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644
index 0000000..0f4bb90
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,74 @@
+/*
+ * DTS file for SPEAr300 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x60000000 0x60000000 0x50000000
+			  0xd0000000 0xd0000000 0x30000000>;
+
+		clcd at 60000000 {
+			compatible = "arm,clcd-pl110", "arm,primecell";
+			reg = <0x60000000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <30>;
+			status = "disabled";
+		};
+
+		fsmc: flash at 94000000 {
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x94000000 0x1000	/* FSMC Register */
+			       0x80000000 0x0010>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x20000>;
+			st,cle-off = <0x10000>;
+			status = "disabled";
+		};
+
+		sdhci at 70000000 {
+			compatible = "st,sdhci-spear";
+			reg = <0x70000000 0x100>;
+			interrupt-parent = <&vic>;
+			interrupts = <1>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xa0000000 0xa0000000 0x10000000
+				  0xd0000000 0xd0000000 0x30000000>;
+
+			gpio1: gpio at a9000000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xa9000000 0x1000>;
+				status = "disabled";
+			};
+
+			kbd at a0000000 {
+				compatible = "st,spear300-kbd";
+				reg = <0xa0000000 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644
index 0000000..ec19d7b
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,107 @@
+/*
+ * DTS file for SPEAr310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear310.dtsi"
+
+/ {
+	model = "ST SPEAr310 Evaluation Board";
+	compatible = "st,spear310-evb", "st,spear310";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		fsmc: flash at 44000000 {
+			status = "okay";
+		};
+
+		gmac: eth at e0800000 {
+			status = "okay";
+		};
+
+		smi: flash at fc000000 {
+			status = "okay";
+			clock-rate=<50000000>;
+
+			flash at f8000000 {
+				label = "m25p64";
+				reg = <0xf8000000 0x800000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				st,smi-fast-mode;
+			};
+		};
+
+		spi0: spi at d0100000 {
+			status = "okay";
+		};
+
+		ehci at e1800000 {
+			status = "okay";
+		};
+
+		ohci at e1900000 {
+			status = "okay";
+		};
+
+		ohci at e2100000 {
+			status = "okay";
+		};
+
+		apb {
+			gpio0: gpio at fc980000 {
+			       status = "okay";
+			};
+
+			i2c0: i2c at d0180000 {
+			       status = "okay";
+			};
+
+			rtc at fc900000 {
+			       status = "okay";
+			};
+
+			serial at d0000000 {
+			       status = "okay";
+			};
+
+			serial at b2000000 {
+			       status = "okay";
+			};
+
+			serial at b2080000 {
+			       status = "okay";
+			};
+
+			serial at b2100000 {
+			       status = "okay";
+			};
+
+			serial at b2180000 {
+			       status = "okay";
+			};
+
+			serial at b2200000 {
+			       status = "okay";
+			};
+
+			wdt at fc880000 {
+			       status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644
index 0000000..dc7fa14
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,75 @@
+/*
+ * DTS file for SPEAr310 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x40000000 0x40000000 0x10000000
+			  0xb0000000 0xb0000000 0x10000000
+			  0xd0000000 0xd0000000 0x30000000>;
+
+		fsmc: flash at 44000000 {
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x44000000 0x1000	/* FSMC Register */
+			       0x40000000 0x0010>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x10000>;
+			st,cle-off = <0x20000>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xb0000000 0xb0000000 0x10000000
+				  0xd0000000 0xd0000000 0x30000000>;
+
+			serial at b2000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2000000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2080000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2080000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2100000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2100000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2180000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2180000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2200000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2200000 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644
index 0000000..5681a97
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,108 @@
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear320.dtsi"
+
+/ {
+	model = "ST SPEAr300 Evaluation Board";
+	compatible = "st,spear300-evb", "st,spear300";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		clcd at 90000000 {
+			status = "okay";
+		};
+
+		fsmc: flash at 4c000000 {
+			status = "okay";
+		};
+
+		gmac: eth at e0800000 {
+			status = "okay";
+		};
+
+		sdhci at 70000000 {
+			power-gpio = <&gpio0 2 1>;
+			power_always_enb;
+			status = "okay";
+		};
+
+		smi: flash at fc000000 {
+			status = "okay";
+		};
+
+		spi0: spi at d0100000 {
+			status = "okay";
+		};
+
+		spi1: spi at a5000000 {
+			status = "okay";
+		};
+
+		spi2: spi at a6000000 {
+			status = "okay";
+		};
+
+		ehci at e1800000 {
+			status = "okay";
+		};
+
+		ohci at e1900000 {
+			status = "okay";
+		};
+
+		ohci at e2100000 {
+			status = "okay";
+		};
+
+		apb {
+			gpio0: gpio at fc980000 {
+			       status = "okay";
+			};
+
+			i2c0: i2c at d0180000 {
+			       status = "okay";
+			};
+
+			i2c1: i2c at a7000000 {
+			       status = "okay";
+			};
+
+			rtc at fc900000 {
+			       status = "okay";
+			};
+
+			serial at d0000000 {
+			       status = "okay";
+			};
+
+			serial at a3000000 {
+			       status = "okay";
+			};
+
+			serial at a4000000 {
+			       status = "okay";
+			};
+
+			wdt at fc880000 {
+			       status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644
index 0000000..8ca0591
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,92 @@
+/*
+ * DTS file for SPEAr320 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x40000000 0x40000000 0x70000000
+			  0xd0000000 0xd0000000 0x30000000>;
+
+		clcd at 90000000 {
+			compatible = "arm,clcd-pl110", "arm,primecell";
+			reg = <0x90000000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <33>;
+			status = "disabled";
+		};
+
+		fsmc: flash at 4c000000 {
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x4c000000 0x1000	/* FSMC Register */
+			       0x50000000 0x0010>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x20000>;
+			st,cle-off = <0x10000>;
+			status = "disabled";
+		};
+
+		sdhci at 70000000 {
+			compatible = "st,sdhci-spear";
+			reg = <0x70000000 0x100>;
+			interrupt-parent = <&vic>;
+			interrupts = <29>;
+			status = "disabled";
+		};
+
+		spi1: spi at a5000000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0xa5000000 0x1000>;
+			status = "disabled";
+		};
+
+		spi2: spi at a6000000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0xa6000000 0x1000>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xa0000000 0xa0000000 0x10000000
+				  0xd0000000 0xd0000000 0x30000000>;
+
+			i2c1: i2c at a7000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,designware-i2c";
+				reg = <0xa7000000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at a3000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xa3000000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at a4000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xa4000000 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644
index 0000000..a31e52e
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,145 @@
+/*
+ * DTS file for all SPEAr3xx SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+		vic: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		gmac: eth at e0800000 {
+			compatible = "st,spear600-gmac";
+			reg = <0xe0800000 0x8000>;
+			interrupt-parent = <&vic>;
+			interrupts = <23 22>;
+			interrupt-names = "macirq", "eth_wake_irq";
+			status = "disabled";
+		};
+
+		smi: flash at fc000000 {
+			compatible = "st,spear600-smi";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xfc000000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <9>;
+			status = "disabled";
+		};
+
+		spi0: spi at d0100000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0xd0100000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <20>;
+			status = "disabled";
+		};
+
+		ehci at e1800000 {
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe1800000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <26>;
+			status = "disabled";
+		};
+
+		ohci at e1900000 {
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe1900000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <25>;
+			status = "disabled";
+		};
+
+		ohci at e2100000 {
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe2100000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <27>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+			gpio0: gpio at fc980000 {
+				compatible = "arm,pl061", "arm,primecell";
+				reg = <0xfc980000 0x1000>;
+				interrupt-parent = <&vic>;
+				interrupts = <11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			i2c0: i2c at d0180000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,designware-i2c";
+				reg = <0xd0180000 0x1000>;
+				interrupt-parent = <&vic>;
+				interrupts = <21>;
+				status = "disabled";
+			};
+
+			rtc at fc900000 {
+				compatible = "st,spear-rtc";
+				reg = <0xfc900000 0x1000>;
+				interrupt-parent = <&vic>;
+				interrupts = <10>;
+				status = "disabled";
+			};
+
+			serial at d0000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0000000 0x1000>;
+				interrupt-parent = <&vic>;
+				interrupts = <19>;
+				status = "disabled";
+			};
+
+			wdt at fc880000 {
+				compatible = "arm,sp805", "arm,primecell";
+				reg = <0xfc880000 0x1000>;
+				interrupt-parent = <&vic>;
+				interrupts = <12>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0..2817b46 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -2,42 +2,22 @@
 # SPEAr3XX Machine configuration file
 #
 
-if ARCH_SPEAR3XX
+if ARCH_SPEAR3XX_DT
 
 menu "SPEAr3xx Implementations"
-config BOARD_SPEAR300_EVB
-	bool "SPEAr300 Evaluation Board"
-	select MACH_SPEAR300
+config MACH_SPEAR300_DT
+	bool "SPEAr300 Machine support with Device Tree"
 	help
-	  Supports ST SPEAr300 Evaluation Board
+	  Supports ST SPEAr300 machine configured via the device-tree
 
-config BOARD_SPEAR310_EVB
-	bool "SPEAr310 Evaluation Board"
-	select MACH_SPEAR310
+config MACH_SPEAR310_DT
+	bool "SPEAr310 Machine support with Device Tree"
 	help
-	  Supports ST SPEAr310 Evaluation Board
+	  Supports ST SPEAr310 machine configured via the device-tree
 
-config BOARD_SPEAR320_EVB
-	bool "SPEAr320 Evaluation Board"
-	select MACH_SPEAR320
+config MACH_SPEAR320_DT
+	bool "SPEAr320 Machine support with Device Tree"
 	help
-	  Supports ST SPEAr320 Evaluation Board
-
+	  Supports ST SPEAr320 machine configured via the device-tree
 endmenu
-
-config MACH_SPEAR300
-	bool "SPEAr300"
-	help
-	  Supports ST SPEAr300 Machine
-
-config MACH_SPEAR310
-	bool "SPEAr310"
-	help
-	  Supports ST SPEAr310 Machine
-
-config MACH_SPEAR320
-	bool "SPEAr320"
-	help
-	  Supports ST SPEAr320 Machine
-
 endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b248624..25526b6 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
 #
 
 # common files
-obj-y	+= spear3xx.o clock.o
+obj-$(CONFIG_ARCH_SPEAR3XX_DT)	+= spear3xx.o clock.o
 
 # spear300 specific files
-obj-$(CONFIG_MACH_SPEAR300) += spear300.o
-
-# spear300 boards files
-obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
-
+obj-$(CONFIG_MACH_SPEAR300_DT) += spear300.o
 
 # spear310 specific files
-obj-$(CONFIG_MACH_SPEAR310) += spear310.o
-
-# spear310 boards files
-obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
-
+obj-$(CONFIG_MACH_SPEAR310_DT) += spear310.o
 
 # spear320 specific files
-obj-$(CONFIG_MACH_SPEAR320) += spear320.o
-
-# spear320 boards files
-obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
+obj-$(CONFIG_MACH_SPEAR320_DT) += spear320.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c..fe371b7 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
 zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR300_DT)	+= spear300-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR310_DT)	+= spear310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR320_DT)	+= spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 47d4535..6833d08 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of_platform.h>
 #include <asm/mach-types.h>
 #include <plat/clock.h>
 #include <mach/misc_regs.h>
@@ -508,7 +509,7 @@ static struct clk adc_clk = {
 	.recalc = &follow_parent,
 };
 
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR310_DT) || defined(CONFIG_MACH_SPEAR320_DT)
 /* emi clock */
 static struct clk emi_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -535,8 +536,8 @@ static struct clk gpio_clk = {
 
 static struct clk dummy_apb_pclk;
 
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
-	defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR300_DT) || defined(CONFIG_MACH_SPEAR310_DT) || \
+	defined(CONFIG_MACH_SPEAR320_DT)
 /* fsmc clock */
 static struct clk fsmc_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -546,7 +547,7 @@ static struct clk fsmc_clk = {
 #endif
 
 /* common clocks to spear310 and spear320 */
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR310_DT) || defined(CONFIG_MACH_SPEAR320_DT)
 /* uart1 clock */
 static struct clk uart1_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -560,10 +561,10 @@ static struct clk uart2_clk = {
 	.pclk = &apb_clk,
 	.recalc = &follow_parent,
 };
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
+#endif /* CONFIG_MACH_SPEAR310_DT || CONFIG_MACH_SPEAR320_DT */
 
 /* common clocks to spear300 and spear320 */
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR300_DT) || defined(CONFIG_MACH_SPEAR310_DT)
 /* clcd clock */
 static struct clk clcd_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -577,10 +578,10 @@ static struct clk sdhci_clk = {
 	.pclk = &ahb_clk,
 	.recalc = &follow_parent,
 };
-#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
+#endif /* CONFIG_MACH_SPEAR300_DT || CONFIG_MACH_SPEAR320_DT */
 
 /* spear300 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR300
+#ifdef CONFIG_MACH_SPEAR300_DT
 /* gpio1 clock */
 static struct clk gpio1_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -598,7 +599,7 @@ static struct clk kbd_clk = {
 #endif
 
 /* spear310 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR310
+#ifdef CONFIG_MACH_SPEAR310_DT
 /* uart3 clock */
 static struct clk uart3_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -622,7 +623,7 @@ static struct clk uart5_clk = {
 #endif
 
 /* spear320 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR320
+#ifdef CONFIG_MACH_SPEAR320_DT
 /* can0 clock */
 static struct clk can0_clk = {
 	.flags = ALWAYS_ENABLED,
@@ -673,11 +674,11 @@ static struct clk_lookup spear_clk_lookups[] = {
 	CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
 	CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
 	/* clock derived from 32 KHz osc clk */
-	CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
+	CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk),
 	/* clock derived from 24 MHz osc clk */
 	CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
 	CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
-	CLKDEV_INIT("wdt", NULL, &wdt_clk),
+	CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk),
 	/* clock derived from pll1 clk */
 	CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
 	CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
@@ -686,7 +687,7 @@ static struct clk_lookup spear_clk_lookups[] = {
 	CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
 	CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
 	CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
-	CLKDEV_INIT("uart", NULL, &uart_clk),
+	CLKDEV_INIT("d0000000.serial", NULL, &uart_clk),
 	CLKDEV_INIT("firda", NULL, &firda_clk),
 	CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
 	CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
@@ -699,81 +700,95 @@ static struct clk_lookup spear_clk_lookups[] = {
 	CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
 	/* clock derived from ahb clk */
 	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
-	CLKDEV_INIT("i2c_designware.0", NULL, &i2c_clk),
+	CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
 	CLKDEV_INIT("dma", NULL, &dma_clk),
 	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
-	CLKDEV_INIT("gmac", NULL, &gmac_clk),
-	CLKDEV_INIT("smi", NULL, &smi_clk),
+	CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
+	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
 	CLKDEV_INIT("c3", NULL, &c3_clk),
 	/* clock derived from apb clk */
 	CLKDEV_INIT("adc", NULL, &adc_clk),
-	CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
-	CLKDEV_INIT("gpio", NULL, &gpio_clk),
+	CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk),
+	CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk),
 };
 
 /* array of all spear 300 clock lookups */
-#ifdef CONFIG_MACH_SPEAR300
+#ifdef CONFIG_MACH_SPEAR300_DT
 static struct clk_lookup spear300_clk_lookups[] = {
-	CLKDEV_INIT("clcd", NULL, &clcd_clk),
-	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
-	CLKDEV_INIT("gpio1", NULL, &gpio1_clk),
-	CLKDEV_INIT("keyboard", NULL, &kbd_clk),
-	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
+	CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk),
+	CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk),
+	CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk),
+	CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
 };
+
+void __init spear300_clk_init(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+		clk_register(&spear_clk_lookups[i]);
+
+	for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++)
+		clk_register(&spear300_clk_lookups[i]);
+
+	clk_init();
+}
 #endif
 
 /* array of all spear 310 clock lookups */
-#ifdef CONFIG_MACH_SPEAR310
+#ifdef CONFIG_MACH_SPEAR310_DT
 static struct clk_lookup spear310_clk_lookups[] = {
-	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+	CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk),
 	CLKDEV_INIT(NULL, "emi", &emi_clk),
-	CLKDEV_INIT("uart1", NULL, &uart1_clk),
-	CLKDEV_INIT("uart2", NULL, &uart2_clk),
-	CLKDEV_INIT("uart3", NULL, &uart3_clk),
-	CLKDEV_INIT("uart4", NULL, &uart4_clk),
-	CLKDEV_INIT("uart5", NULL, &uart5_clk),
+	CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk),
+	CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk),
+	CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk),
+	CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk),
+	CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk),
 };
+
+void __init spear310_clk_init(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+		clk_register(&spear_clk_lookups[i]);
+
+	for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++)
+		clk_register(&spear310_clk_lookups[i]);
+
+	clk_init();
+}
 #endif
 
 /* array of all spear 320 clock lookups */
-#ifdef CONFIG_MACH_SPEAR320
+#ifdef CONFIG_MACH_SPEAR320_DT
 static struct clk_lookup spear320_clk_lookups[] = {
-	CLKDEV_INIT("clcd", NULL, &clcd_clk),
-	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
-	CLKDEV_INIT("i2c_designware.1", NULL, &i2c1_clk),
+	CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk),
+	CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk),
 	CLKDEV_INIT(NULL, "emi", &emi_clk),
 	CLKDEV_INIT("pwm", NULL, &pwm_clk),
-	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
+	CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
 	CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
 	CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
-	CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
-	CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
-	CLKDEV_INIT("uart1", NULL, &uart1_clk),
-	CLKDEV_INIT("uart2", NULL, &uart2_clk),
+	CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk),
+	CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk),
+	CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk),
+	CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk),
 };
-#endif
 
-void __init spear3xx_clk_init(void)
+void __init spear320_clk_init(void)
 {
-	int i, cnt;
-	struct clk_lookup *lookups;
-
-	if (machine_is_spear300()) {
-		cnt = ARRAY_SIZE(spear300_clk_lookups);
-		lookups = spear300_clk_lookups;
-	} else if (machine_is_spear310()) {
-		cnt = ARRAY_SIZE(spear310_clk_lookups);
-		lookups = spear310_clk_lookups;
-	} else {
-		cnt = ARRAY_SIZE(spear320_clk_lookups);
-		lookups = spear320_clk_lookups;
-	}
+	int i;
 
 	for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
 		clk_register(&spear_clk_lookups[i]);
 
-	for (i = 0; i < cnt; i++)
-		clk_register(&lookups[i]);
+	for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++)
+		clk_register(&spear320_clk_lookups[i]);
 
 	clk_init();
 }
+#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5..8af11da 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -31,16 +31,18 @@
 #define SPEAR_GPT0_CHAN1_IRQ	SPEAR3XX_IRQ_CPU_GPT1_2
 
 /* Add spear3xx family device structure declarations here */
-extern struct amba_device spear3xx_gpio_device;
-extern struct amba_device spear3xx_uart_device;
 extern struct sys_timer spear3xx_timer;
+extern struct pl022_ssp_controller pl022_plat_data;
+
+/* SPEAr3xx auxdata to pass platform data */
+#define SPEAR3XX_AUXDATA_LOOKUP					\
+	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, \
+			&pl022_plat_data)
 
 /* Add spear3xx family function declarations here */
-void __init spear3xx_clk_init(void);
 void __init spear_setup_timer(void);
 void __init spear3xx_map_io(void);
-void __init spear3xx_init_irq(void);
-void __init spear3xx_init(void);
+void __init spear3xx_dt_init_irq(void);
 
 void spear_restart(char, const char *);
 
@@ -78,7 +80,7 @@ extern struct pmx_dev spear3xx_pmx_uart0;
 extern struct pmx_dev spear3xx_pmx_timer_3_4;
 extern struct pmx_dev spear3xx_pmx_timer_1_2;
 
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR310_DT) || defined(CONFIG_MACH_SPEAR320_DT)
 /* padmux plgpio devices */
 extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
 extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
@@ -98,10 +100,7 @@ extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
 #endif
 
 /* spear300 declarations */
-#ifdef CONFIG_MACH_SPEAR300
-/* Add spear300 machine device structure declarations here */
-extern struct amba_device spear300_gpio1_device;
-
+#ifdef CONFIG_MACH_SPEAR300_DT
 /* pad mux modes */
 extern struct pmx_mode spear300_nand_mode;
 extern struct pmx_mode spear300_nor_mode;
@@ -133,16 +132,13 @@ extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
 extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
 extern struct pmx_dev spear300_pmx_gpio1;
 
-/* Add spear300 machine function declarations here */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count);
+/* Add spear300 machine declarations here */
+void __init spear300_clk_init(void);
 
-#endif /* CONFIG_MACH_SPEAR300 */
+#endif /* CONFIG_MACH_SPEAR300_DT */
 
 /* spear310 declarations */
-#ifdef CONFIG_MACH_SPEAR310
-/* Add spear310 machine device structure declarations here */
-
+#ifdef CONFIG_MACH_SPEAR310_DT
 /* pad mux devices */
 extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
 extern struct pmx_dev spear310_pmx_emi_cs_2_3;
@@ -153,16 +149,13 @@ extern struct pmx_dev spear310_pmx_fsmc;
 extern struct pmx_dev spear310_pmx_rs485_0_1;
 extern struct pmx_dev spear310_pmx_tdm0;
 
-/* Add spear310 machine function declarations here */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count);
+/* Add spear310 machine declarations here */
+void __init spear310_clk_init(void);
 
-#endif /* CONFIG_MACH_SPEAR310 */
+#endif /* CONFIG_MACH_SPEAR310_DT */
 
 /* spear320 declarations */
-#ifdef CONFIG_MACH_SPEAR320
-/* Add spear320 machine device structure declarations here */
-
+#ifdef CONFIG_MACH_SPEAR320_DT
 /* pad mux modes */
 extern struct pmx_mode spear320_auto_net_smii_mode;
 extern struct pmx_mode spear320_auto_net_mii_mode;
@@ -193,10 +186,9 @@ extern struct pmx_dev spear320_pmx_smii0;
 extern struct pmx_dev spear320_pmx_smii1;
 extern struct pmx_dev spear320_pmx_i2c1;
 
-/* Add spear320 machine function declarations here */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count);
+/* Add spear320 machine declarations here */
+void __init spear320_clk_init(void);
 
-#endif /* CONFIG_MACH_SPEAR320 */
+#endif /* CONFIG_MACH_SPEAR320_DT */
 
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e26544..90ed5ef 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -129,9 +129,9 @@
  * Use the lowest number for the GPIO virtual IRQs base on which subarchs
  * we have compiled in
  */
-#if defined(CONFIG_MACH_SPEAR310)
+#if defined(CONFIG_MACH_SPEAR310_DT)
 #define SPEAR3XX_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 18)
-#elif defined(CONFIG_MACH_SPEAR320)
+#elif defined(CONFIG_MACH_SPEAR320_DT)
 #define SPEAR3XX_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 17)
 #else
 #define SPEAR3XX_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 9)
@@ -140,7 +140,7 @@
 #define SPEAR300_GPIO1_INT_BASE			(SPEAR3XX_GPIO_INT_BASE + 8)
 #define SPEAR3XX_PLGPIO_COUNT	102
 
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR310_DT) || defined(CONFIG_MACH_SPEAR320_DT)
 #define SPEAR3XX_PLGPIO_INT_BASE		(SPEAR3XX_GPIO_INT_BASE + 8)
 #define SPEAR3XX_GPIO_INT_END			(SPEAR3XX_PLGPIO_INT_BASE + \
 							SPEAR3XX_PLGPIO_COUNT)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index 3b6ea07..260794d 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -11,7 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifdef	CONFIG_MACH_SPEAR300
+#ifdef	CONFIG_MACH_SPEAR300_DT
 
 #ifndef __MACH_SPEAR300_H
 #define __MACH_SPEAR300_H
@@ -51,4 +51,4 @@
 
 #endif /* __MACH_SPEAR300_H */
 
-#endif /* CONFIG_MACH_SPEAR300 */
+#endif /* CONFIG_MACH_SPEAR300_DT */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 1567d0da..bc9c06d 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -11,7 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifdef	CONFIG_MACH_SPEAR310
+#ifdef	CONFIG_MACH_SPEAR310_DT
 
 #ifndef __MACH_SPEAR310_H
 #define __MACH_SPEAR310_H
@@ -55,4 +55,4 @@
 
 #endif /* __MACH_SPEAR310_H */
 
-#endif /* CONFIG_MACH_SPEAR310 */
+#endif /* CONFIG_MACH_SPEAR310_DT */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 8cfa83f..e6ac0da 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -11,7 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifdef	CONFIG_MACH_SPEAR320
+#ifdef	CONFIG_MACH_SPEAR320_DT
 
 #ifndef __MACH_SPEAR320_H
 #define __MACH_SPEAR320_H
@@ -64,4 +64,4 @@
 
 #endif /* __MACH_SPEAR320_H */
 
-#endif /* CONFIG_MACH_SPEAR320 */
+#endif /* CONFIG_MACH_SPEAR300_DT */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index adee72b..1a1bd93 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,8 +3,8 @@
  *
  * SPEAr300 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,10 +13,9 @@
 
 #define pr_fmt(fmt) "SPEAr300: " fmt
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
@@ -425,24 +424,34 @@ static struct spear_shirq shirq_ras1 = {
 	},
 };
 
-/* Add spear300 specific devices here */
-/* arm gpio1 device registration */
-static struct pl061_platform_data gpio1_plat_data = {
-	.gpio_base	= 8,
-	.irq_base	= SPEAR300_GPIO1_INT_BASE,
+/* padmux devices to enable */
+static struct pmx_dev *spear300_evb_pmx_devs[] = {
+	/* spear3xx specific devices */
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp_cs,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_mii,
+	&spear3xx_pmx_uart0,
+
+	/* spear300 specific devices */
+	&spear300_pmx_fsmc_2_chips,
+	&spear300_pmx_clcd,
+	&spear300_pmx_telecom_sdhci_4bit,
+	&spear300_pmx_gpio1,
 };
 
-AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
-	{SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
+/* Add SPEAr300 auxdata to pass platform data */
+static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
+	SPEAR3XX_AUXDATA_LOOKUP,
+	{}
+};
 
-/* spear300 routines */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count)
+static void __init spear300_dt_init(void)
 {
-	int ret = 0;
+	int ret = -EINVAL;
 
-	/* call spear3xx family common init function */
-	spear3xx_init();
+	of_platform_populate(NULL, of_default_bus_match_table,
+			spear300_auxdata_lookup, NULL);
 
 	/* shared irq registration */
 	shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
@@ -452,10 +461,15 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 			pr_err("Error registering Shared IRQ\n");
 	}
 
-	/* pmx initialization */
-	pmx_driver.mode = pmx_mode;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = pmx_dev_count;
+	if (of_machine_is_compatible("st,spear300-evb")) {
+		/* pmx initialization */
+		pmx_driver.mode = &spear300_photo_frame_mode;
+		pmx_driver.devs = spear300_evb_pmx_devs;
+		pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
+	} else {
+		pr_err("Invalid board\n");
+		return;
+	}
 
 	pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
 	if (pmx_driver.base) {
@@ -466,4 +480,29 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 		/* Free Mapping, device selection already done */
 		iounmap(pmx_driver.base);
 	}
+
+	if (ret)
+		pr_err("Initialization Failed");
+}
+
+static const char * const spear300_dt_board_compat[] = {
+	"st,spear300",
+	"st,spear300-evb",
+	NULL,
+};
+
+static void __init spear300_map_io(void)
+{
+	spear3xx_map_io();
+	spear300_clk_init();
 }
+
+DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
+	.map_io		=	spear300_map_io,
+	.init_irq	=	spear3xx_dt_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear3xx_timer,
+	.init_machine	=	spear300_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear300_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9..0000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear300_evb.c
- *
- * SPEAr300 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-	/* spear3xx specific devices */
-	&spear3xx_pmx_i2c,
-	&spear3xx_pmx_ssp_cs,
-	&spear3xx_pmx_ssp,
-	&spear3xx_pmx_mii,
-	&spear3xx_pmx_uart0,
-
-	/* spear300 specific devices */
-	&spear300_pmx_fsmc_2_chips,
-	&spear300_pmx_clcd,
-	&spear300_pmx_telecom_sdhci_4bit,
-	&spear300_pmx_gpio1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	/* spear3xx specific devices */
-	&spear3xx_gpio_device,
-	&spear3xx_uart_device,
-
-	/* spear300 specific devices */
-	&spear300_gpio1_device,
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-	/* spear3xx specific devices */
-
-	/* spear300 specific devices */
-};
-
-static void __init spear300_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear300 machine init function */
-	spear300_init(&spear300_photo_frame_mode, pmx_devs,
-			ARRAY_SIZE(pmx_devs));
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear3xx_map_io,
-	.init_irq	=	spear3xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear3xx_timer,
-	.init_machine	=	spear300_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index b7c2876..0b58313 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,8 +3,8 @@
  *
  * SPEAr310 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,8 +13,11 @@
 
 #define pr_fmt(fmt) "SPEAr310: " fmt
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
@@ -257,17 +260,78 @@ static struct spear_shirq shirq_intrcomm_ras = {
 	},
 };
 
-/* Add spear310 specific devices here */
+/* padmux devices to enable */
+static struct pmx_dev *spear310_evb_pmx_devs[] = {
+	/* spear3xx specific devices */
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_gpio_pin0,
+	&spear3xx_pmx_gpio_pin1,
+	&spear3xx_pmx_gpio_pin2,
+	&spear3xx_pmx_gpio_pin3,
+	&spear3xx_pmx_gpio_pin4,
+	&spear3xx_pmx_gpio_pin5,
+	&spear3xx_pmx_uart0,
+
+	/* spear310 specific devices */
+	&spear310_pmx_emi_cs_0_1_4_5,
+	&spear310_pmx_emi_cs_2_3,
+	&spear310_pmx_uart1,
+	&spear310_pmx_uart2,
+	&spear310_pmx_uart3_4_5,
+	&spear310_pmx_fsmc,
+	&spear310_pmx_rs485_0_1,
+	&spear310_pmx_tdm0,
+};
+
+/* uart devices plat data */
+static struct amba_pl011_data spear310_uart_data[] = {
+	{
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart1_tx",
+		.dma_rx_param = "uart1_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart2_tx",
+		.dma_rx_param = "uart2_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart3_tx",
+		.dma_rx_param = "uart3_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart4_tx",
+		.dma_rx_param = "uart4_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart5_tx",
+		.dma_rx_param = "uart5_rx",
+	},
+};
 
-/* spear310 routines */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count)
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
+	SPEAR3XX_AUXDATA_LOOKUP,
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
+			&spear310_uart_data[0]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
+			&spear310_uart_data[1]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
+			&spear310_uart_data[2]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
+			&spear310_uart_data[3]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
+			&spear310_uart_data[4]),
+	{}
+};
+
+static void __init spear310_dt_init(void)
 {
 	void __iomem *base;
 	int ret = 0;
 
-	/* call spear3xx family common init function */
-	spear3xx_init();
+	of_platform_populate(NULL, of_default_bus_match_table,
+			spear310_auxdata_lookup, NULL);
 
 	/* shared irq registration */
 	base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -297,13 +361,40 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 			pr_err("Error registering Shared IRQ 4\n");
 	}
 
-	/* pmx initialization */
-	pmx_driver.base = base;
-	pmx_driver.mode = pmx_mode;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = pmx_dev_count;
+	if (of_machine_is_compatible("st,spear310-evb")) {
+		/* pmx initialization */
+		pmx_driver.base = base;
+		pmx_driver.mode = NULL;
+		pmx_driver.devs = spear310_evb_pmx_devs;
+		pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs);
+	} else {
+		pr_err("Invalid board\n");
+		return;
+	}
 
 	ret = pmx_register(&pmx_driver);
 	if (ret)
 		pr_err("padmux: registration failed. err no: %d\n", ret);
 }
+
+static const char * const spear310_dt_board_compat[] = {
+	"st,spear310",
+	"st,spear310-evb",
+	NULL,
+};
+
+static void __init spear310_map_io(void)
+{
+	spear3xx_map_io();
+	spear310_clk_init();
+}
+
+DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
+	.map_io		=	spear310_map_io,
+	.init_irq	=	spear3xx_dt_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear3xx_timer,
+	.init_machine	=	spear310_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear310_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c499..0000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear310_evb.c
- *
- * SPEAr310 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-	/* spear3xx specific devices */
-	&spear3xx_pmx_i2c,
-	&spear3xx_pmx_ssp,
-	&spear3xx_pmx_gpio_pin0,
-	&spear3xx_pmx_gpio_pin1,
-	&spear3xx_pmx_gpio_pin2,
-	&spear3xx_pmx_gpio_pin3,
-	&spear3xx_pmx_gpio_pin4,
-	&spear3xx_pmx_gpio_pin5,
-	&spear3xx_pmx_uart0,
-
-	/* spear310 specific devices */
-	&spear310_pmx_emi_cs_0_1_4_5,
-	&spear310_pmx_emi_cs_2_3,
-	&spear310_pmx_uart1,
-	&spear310_pmx_uart2,
-	&spear310_pmx_uart3_4_5,
-	&spear310_pmx_fsmc,
-	&spear310_pmx_rs485_0_1,
-	&spear310_pmx_tdm0,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	/* spear3xx specific devices */
-	&spear3xx_gpio_device,
-	&spear3xx_uart_device,
-
-	/* spear310 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-	/* spear3xx specific devices */
-
-	/* spear310 specific devices */
-};
-
-static void __init spear310_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear310 machine init function */
-	spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear3xx_map_io,
-	.init_irq	=	spear3xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear3xx_timer,
-	.init_machine	=	spear310_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 7bd39c0..fb9b17e 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,8 +3,8 @@
  *
  * SPEAr320 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,8 +13,12 @@
 
 #define pr_fmt(fmt) "SPEAr320: " fmt
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
@@ -510,17 +514,78 @@ static struct spear_shirq shirq_intrcomm_ras = {
 	},
 };
 
-/* Add spear320 specific devices here */
+/* padmux devices to enable */
+static struct pmx_dev *spear320_evb_pmx_devs[] = {
+	/* spear3xx specific devices */
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_mii,
+	&spear3xx_pmx_uart0,
+
+	/* spear320 specific devices */
+	&spear320_pmx_fsmc,
+	&spear320_pmx_sdhci,
+	&spear320_pmx_i2s,
+	&spear320_pmx_uart1,
+	&spear320_pmx_uart2,
+	&spear320_pmx_can,
+	&spear320_pmx_pwm0,
+	&spear320_pmx_pwm1,
+	&spear320_pmx_pwm2,
+	&spear320_pmx_mii1,
+};
+
+static struct pl022_ssp_controller spear320_ssp_data[] = {
+	{
+		.bus_id = 1,
+		.enable_dma = 1,
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "ssp1_tx",
+		.dma_rx_param = "ssp1_rx",
+		.num_chipselect = 2,
+	}, {
+		.bus_id = 2,
+		.enable_dma = 1,
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "ssp2_tx",
+		.dma_rx_param = "ssp2_rx",
+		.num_chipselect = 2,
+	}
+};
+
+static struct amba_pl011_data spear320_uart_data[] = {
+	{
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart1_tx",
+		.dma_rx_param = "uart1_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart2_tx",
+		.dma_rx_param = "uart2_rx",
+	},
+};
 
-/* spear320 routines */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count)
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
+	SPEAR3XX_AUXDATA_LOOKUP,
+	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
+			&spear320_ssp_data[0]),
+	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
+			&spear320_ssp_data[1]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
+			&spear320_uart_data[0]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
+			&spear320_uart_data[1]),
+	{}
+};
+
+static void __init spear320_dt_init(void)
 {
 	void __iomem *base;
 	int ret = 0;
 
-	/* call spear3xx family common init function */
-	spear3xx_init();
+	of_platform_populate(NULL, of_default_bus_match_table,
+			spear320_auxdata_lookup, NULL);
 
 	/* shared irq registration */
 	base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -544,13 +609,40 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 			pr_err("Error registering Shared IRQ 4\n");
 	}
 
-	/* pmx initialization */
-	pmx_driver.base = base;
-	pmx_driver.mode = pmx_mode;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = pmx_dev_count;
+	if (of_machine_is_compatible("st,spear320-evb")) {
+		/* pmx initialization */
+		pmx_driver.base = base;
+		pmx_driver.mode = &spear320_auto_net_mii_mode;
+		pmx_driver.devs = spear320_evb_pmx_devs;
+		pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
+	} else {
+		pr_err("Invalid board\n");
+		return;
+	}
 
 	ret = pmx_register(&pmx_driver);
 	if (ret)
 		pr_err("padmux: registration failed. err no: %d\n", ret);
 }
+
+static const char * const spear320_dt_board_compat[] = {
+	"st,spear320",
+	"st,spear320-evb",
+	NULL,
+};
+
+static void __init spear320_map_io(void)
+{
+	spear3xx_map_io();
+	spear320_clk_init();
+}
+
+DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
+	.map_io		=	spear320_map_io,
+	.init_irq	=	spear3xx_dt_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear3xx_timer,
+	.init_machine	=	spear320_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear320_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334a..0000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear320_evb.c
- *
- * SPEAr320 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-	/* spear3xx specific devices */
-	&spear3xx_pmx_i2c,
-	&spear3xx_pmx_ssp,
-	&spear3xx_pmx_mii,
-	&spear3xx_pmx_uart0,
-
-	/* spear320 specific devices */
-	&spear320_pmx_fsmc,
-	&spear320_pmx_sdhci,
-	&spear320_pmx_i2s,
-	&spear320_pmx_uart1,
-	&spear320_pmx_uart2,
-	&spear320_pmx_can,
-	&spear320_pmx_pwm0,
-	&spear320_pmx_pwm1,
-	&spear320_pmx_pwm2,
-	&spear320_pmx_mii1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	/* spear3xx specific devices */
-	&spear3xx_gpio_device,
-	&spear3xx_uart_device,
-
-	/* spear320 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-	/* spear3xx specific devices */
-
-	/* spear320 specific devices */
-};
-
-static void __init spear320_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear320 machine init function */
-	spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
-			ARRAY_SIZE(pmx_devs));
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear3xx_map_io,
-	.init_irq	=	spear3xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear3xx_timer,
-	.init_machine	=	spear320_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index a236925..f074638 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,8 +3,8 @@
  *
  * SPEAr3XX machines common source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,76 +13,14 @@
 
 #define pr_fmt(fmt) "SPEAr3xx: " fmt
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of_irq.h>
 #include <linux/io.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
-/* Add spear3xx machines common devices here */
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data = {
-	.gpio_base	= 0,
-	.irq_base	= SPEAR3XX_GPIO_INT_BASE,
-};
-
-AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
-	{SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
-
-/* uart device registration */
-AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
-	{SPEAR3XX_IRQ_UART}, NULL);
-
-/* Do spear3xx familiy common initialization part here */
-void __init spear3xx_init(void)
-{
-	/* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear3xx_init_irq(void)
-{
-	vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
-}
-
-/* Following will create static virtual/physical mappings */
-struct map_desc spear3xx_io_desc[] __initdata = {
-	{
-		.virtual	= VA_SPEAR3XX_ICM1_UART_BASE,
-		.pfn		= __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE
-	}, {
-		.virtual	= VA_SPEAR3XX_ML1_VIC_BASE,
-		.pfn		= __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE
-	}, {
-		.virtual	= VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
-		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE
-	}, {
-		.virtual	= VA_SPEAR3XX_ICM3_MISC_REG_BASE,
-		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE
-	},
-};
-
-/* This will create static memory mapping for selected devices */
-void __init spear3xx_map_io(void)
-{
-	iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
-
-	/* This will initialize clock framework */
-	spear3xx_clk_init();
-}
-
 /* pad multiplexing support */
 /* devices */
 static struct pmx_dev_mode pmx_firda_modes[] = {
@@ -295,7 +233,7 @@ struct pmx_dev spear3xx_pmx_timer_1_2 = {
 	.enb_on_reset = 0,
 };
 
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+#if defined(CONFIG_MACH_SPEAR310_DT) || defined(CONFIG_MACH_SPEAR320_DT)
 /* plgpios devices */
 static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
 	{
@@ -506,7 +444,57 @@ struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
 	.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
 	.enb_on_reset = 1,
 };
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
+#endif /* CONFIG_MACH_SPEAR310_DT || CONFIG_MACH_SPEAR320_DT */
+
+/* ssp device registration */
+struct pl022_ssp_controller pl022_plat_data = {
+	.bus_id = 0,
+	.enable_dma = 1,
+	.dma_filter = pl08x_filter_id,
+	.dma_tx_param = "ssp0_tx",
+	.dma_rx_param = "ssp0_rx",
+	/*
+	 * This is number of spi devices that can be connected to spi. There are
+	 * two type of chipselects on which slave devices can work. One is chip
+	 * select provided by spi masters other is controlled through external
+	 * gpio's. We can't use chipselect provided from spi master (because as
+	 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+	 * this number now depends on number of gpios available for spi. each
+	 * slave on each master requires a separate gpio pin.
+	 */
+	.num_chipselect = 2,
+};
+
+/* Following will create static virtual/physical mappings */
+struct map_desc spear3xx_io_desc[] __initdata = {
+	{
+		.virtual	= VA_SPEAR3XX_ICM1_UART_BASE,
+		.pfn		= __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	= VA_SPEAR3XX_ML1_VIC_BASE,
+		.pfn		= __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	= VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
+		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	= VA_SPEAR3XX_ICM3_MISC_REG_BASE,
+		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	},
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear3xx_map_io(void)
+{
+	iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
+}
 
 static void __init spear3xx_timer_init(void)
 {
@@ -538,3 +526,13 @@ static void __init spear3xx_timer_init(void)
 struct sys_timer spear3xx_timer = {
 	.init = spear3xx_timer_init,
 };
+
+static const struct of_device_id vic_of_match[] __initconst = {
+	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ /* Sentinel */ }
+};
+
+void __init spear3xx_dt_init_irq(void)
+{
+	of_irq_init(vic_of_match);
+}
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbc..a6ff4c8 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -8,10 +8,11 @@ choice
 	prompt "ST SPEAr Family"
 	default ARCH_SPEAR3XX
 
-config ARCH_SPEAR3XX
-	bool "SPEAr3XX"
+config ARCH_SPEAR3XX_DT
+	bool "ST SPEAr3xx with Device Tree"
 	select ARM_VIC
 	select CPU_ARM926T
+	select USE_OF
 	help
 	  Supports for ARM's SPEAR3XX family
 
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b..4b906bb 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -5,4 +5,4 @@
 # Common support
 obj-y	:= clock.o restart.o time.o
 
-obj-$(CONFIG_ARCH_SPEAR3XX)	+= shirq.o padmux.o
+obj-$(CONFIG_ARCH_SPEAR3XX_DT)	+= shirq.o padmux.o
-- 
1.7.10.rc2.10.gb47606



From viresh.kumar at st.com  Wed Mar 28 05:43:25 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Wed, 28 Mar 2012 15:13:25 +0530
Subject: [PATCH] watchdog: sp805: call watchdog_set_drvdata() early
Message-ID: <78377bb3c0a861281cfdc5c166f0c082e126f4b7.1332927751.git.viresh.kumar@st.com>

wdt_setload() uses watchdog_get_drvdata() and hence we must call
watchdog_set_drvdata() before actually calling wdt_setload(). This patch moves
watchdog_set_drvdata() up in code.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/sp805_wdt.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 40e628a..ef85676 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -250,6 +250,7 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
 	wdt->wdd.ops = &wdt_ops;
 
 	spin_lock_init(&wdt->lock);
+	watchdog_set_drvdata(&wdt->wdd, wdt);
 	watchdog_set_nowayout(&wdt->wdd, nowayout);
 	wdt_setload(&wdt->wdd, DEFAULT_TIMEOUT);
 
@@ -260,7 +261,6 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
 		goto err_register;
 	}
 	amba_set_drvdata(adev, wdt);
-	watchdog_set_drvdata(&wdt->wdd, wdt);
 
 	dev_info(&adev->dev, "registration successful\n");
 	return 0;
-- 
1.7.10.rc2.10.gb47606



From broonie at opensource.wolfsonmicro.com  Wed Mar 28 06:06:17 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 11:06:17 +0100
Subject: [V2 2/4] rtc: fix 88pm860x rtc irq enable callback
In-Reply-To: <20120327164759.ec04c62e.akpm@linux-foundation.org>
References: <1329997662-2931-1-git-send-email-jtzhou@marvell.com>
 <1331259874-26503-1-git-send-email-jtzhou@marvell.com>
 <20120327164759.ec04c62e.akpm@linux-foundation.org>
Message-ID: <20120328100617.GB3232@opensource.wolfsonmicro.com>

On Tue, Mar 27, 2012 at 04:47:59PM -0700, Andrew Morton wrote:

> It's surprising that the driver has been in-tree for a year and nobody
> has noticed this bug.  This makes me wonder if the fix is wrong.

I rather suspect few of the boards that use this chip ever run mainline
and we're seeing the effects of Android's ICS release rolling out here -
it's using 3.0 as the default kernel which was the first version which
included this driver as standard.
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From jg1.han at samsung.com  Wed Mar 28 06:07:15 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Wed, 28 Mar 2012 19:07:15 +0900
Subject: [PATCH v3 3/4] ARM: s3c64xx: Decouple lcd type from display
 controller window data
In-Reply-To: <1332606528-32338-4-git-send-email-thomas.abraham@linaro.org>
References: <1332606528-32338-1-git-send-email-thomas.abraham@linaro.org>
 <1332606528-32338-4-git-send-email-thomas.abraham@linaro.org>
Message-ID: <008801cd0cca$8d72cad0$a8586070$%han@samsung.com>

On 25 March 2012 01:29, Thomas Abraham < thomas.abraham at linaro.org> wrote:
> Subject: [PATCH v3 3/4] ARM: s3c64xx: Decouple lcd type from display controller window data
> 
> The display controller window data should contain window configuration data
> for only one type of lcd panel. So, for real6410 and mini6410 boards, split
> the existing display controller window data, which contains window
> configuration data for two different types of lcd panels, into two seperate
> instances and register one of them depending on the type of the lcd panel
> detected at runtime.
> 
> This is a prerequisite change for a subsequent commit that reorders the
> platform data of display controller by moving video interface timing out
> of window setup data.
> 
> Cc: Darius Augulis <augulis.darius at gmail.com>
> Cc: Jingoo Han <jg1.han at samsung.com>

It looks good.

Acked-by: Jingoo Han <jg1.han at samsung.com>

> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> ---
>  arch/arm/mach-s3c64xx/mach-mini6410.c |   82 +++++++++++++++++---------------
>  arch/arm/mach-s3c64xx/mach-real6410.c |   82 +++++++++++++++++---------------
>  2 files changed, 88 insertions(+), 76 deletions(-)
> 
> diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
> index c34c2ab..34f5195 100644
> --- a/arch/arm/mach-s3c64xx/mach-mini6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
> @@ -151,41 +151,49 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
>  	.sets		= mini6410_nand_sets,
>  };
> 
> -static struct s3c_fb_pd_win mini6410_fb_win[] = {
> -	{
> -		.win_mode	= {	/* 4.3" 480x272 */
> -			.left_margin	= 3,
> -			.right_margin	= 2,
> -			.upper_margin	= 1,
> -			.lower_margin	= 1,
> -			.hsync_len	= 40,
> -			.vsync_len	= 1,
> -			.xres		= 480,
> -			.yres		= 272,
> -		},
> -		.max_bpp	= 32,
> -		.default_bpp	= 16,
> -	}, {
> -		.win_mode	= {	/* 7.0" 800x480 */
> -			.left_margin	= 8,
> -			.right_margin	= 13,
> -			.upper_margin	= 7,
> -			.lower_margin	= 5,
> -			.hsync_len	= 3,
> -			.vsync_len	= 1,
> -			.xres		= 800,
> -			.yres		= 480,
> -		},
> -		.max_bpp	= 32,
> -		.default_bpp	= 16,
> +static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
> +	.win_mode	= {	/* 4.3" 480x272 */
> +		.left_margin	= 3,
> +		.right_margin	= 2,
> +		.upper_margin	= 1,
> +		.lower_margin	= 1,
> +		.hsync_len	= 40,
> +		.vsync_len	= 1,
> +		.xres		= 480,
> +		.yres		= 272,
>  	},
> +	.max_bpp	= 32,
> +	.default_bpp	= 16,
>  };
> 
> -static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
> -	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> -	.win[0]		= &mini6410_fb_win[0],
> -	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> -	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> +static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
> +	.win_mode	= {	/* 7.0" 800x480 */
> +		.left_margin	= 8,
> +		.right_margin	= 13,
> +		.upper_margin	= 7,
> +		.lower_margin	= 5,
> +		.hsync_len	= 3,
> +		.vsync_len	= 1,
> +		.xres		= 800,
> +		.yres		= 480,
> +	},
> +	.max_bpp	= 32,
> +	.default_bpp	= 16,
> +};
> +
> +static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
> +	{
> +		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +		.win[0]		= &mini6410_lcd_type0_fb_win,
> +		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> +		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> +	}, {
> +		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +		.win[0]		= &mini6410_lcd_type1_fb_win,
> +		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> +		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> +	},
> +	{ },
>  };
> 
>  static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
> @@ -283,7 +291,7 @@ static void mini6410_parse_features(
>  					"screen type already set\n", f);
>  			} else {
>  				int li = f - '0';
> -				if (li >= ARRAY_SIZE(mini6410_fb_win))
> +				if (li >= ARRAY_SIZE(mini6410_lcd_pdata))
>  					printk(KERN_INFO "MINI6410: '%c' out "
>  						"of range LCD mode\n", f);
>  				else {
> @@ -307,14 +315,12 @@ static void __init mini6410_machine_init(void)
>  	/* Parse the feature string */
>  	mini6410_parse_features(&features, mini6410_features_str);
> 
> -	mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
> -
>  	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
> -		mini6410_lcd_pdata.win[0]->win_mode.xres,
> -		mini6410_lcd_pdata.win[0]->win_mode.yres);
> +		mini6410_lcd_pdata[features.lcd_index].win[0]->win_mode.xres,
> +		mini6410_lcd_pdata[features.lcd_index].win[0]->win_mode.yres);
> 
>  	s3c_nand_set_platdata(&mini6410_nand_info);
> -	s3c_fb_set_platdata(&mini6410_lcd_pdata);
> +	s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
>  	s3c24xx_ts_set_platdata(NULL);
> 
>  	/* configure nCS1 width to 16 bits */
> diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
> index be2a9a2..21f91e5 100644
> --- a/arch/arm/mach-s3c64xx/mach-real6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-real6410.c
> @@ -117,41 +117,49 @@ static struct platform_device real6410_device_eth = {
>  	},
>  };
> 
> -static struct s3c_fb_pd_win real6410_fb_win[] = {
> -	{
> -		.win_mode	= {	/* 4.3" 480x272 */
> -			.left_margin	= 3,
> -			.right_margin	= 2,
> -			.upper_margin	= 1,
> -			.lower_margin	= 1,
> -			.hsync_len	= 40,
> -			.vsync_len	= 1,
> -			.xres		= 480,
> -			.yres		= 272,
> -		},
> -		.max_bpp	= 32,
> -		.default_bpp	= 16,
> -	}, {
> -		.win_mode	= {	/* 7.0" 800x480 */
> -			.left_margin	= 8,
> -			.right_margin	= 13,
> -			.upper_margin	= 7,
> -			.lower_margin	= 5,
> -			.hsync_len	= 3,
> -			.vsync_len	= 1,
> -			.xres		= 800,
> -			.yres		= 480,
> -		},
> -		.max_bpp	= 32,
> -		.default_bpp	= 16,
> +static struct s3c_fb_pd_win real6410_lcd_type0_fb_win = {
> +	.win_mode	= {	/* 4.3" 480x272 */
> +		.left_margin	= 3,
> +		.right_margin	= 2,
> +		.upper_margin	= 1,
> +		.lower_margin	= 1,
> +		.hsync_len	= 40,
> +		.vsync_len	= 1,
> +		.xres		= 480,
> +		.yres		= 272,
>  	},
> +	.max_bpp	= 32,
> +	.default_bpp	= 16,
>  };
> 
> -static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
> -	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> -	.win[0]		= &real6410_fb_win[0],
> -	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> -	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> +static struct s3c_fb_pd_win real6410_lcd_type1_fb_win = {
> +	.win_mode	= {	/* 7.0" 800x480 */
> +		.left_margin	= 8,
> +		.right_margin	= 13,
> +		.upper_margin	= 7,
> +		.lower_margin	= 5,
> +		.hsync_len	= 3,
> +		.vsync_len	= 1,
> +		.xres		= 800,
> +		.yres		= 480,
> +	},
> +	.max_bpp	= 32,
> +	.default_bpp	= 16,
> +};
> +
> +static struct s3c_fb_platdata real6410_lcd_pdata[] __initdata = {
> +	{
> +		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +		.win[0]		= &real6410_lcd_type0_fb_win,
> +		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> +		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> +	}, {
> +		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +		.win[0]		= &real6410_lcd_type1_fb_win,
> +		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
> +		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> +	},
> +	{ },
>  };
> 
>  static struct mtd_partition real6410_nand_part[] = {
> @@ -264,7 +272,7 @@ static void real6410_parse_features(
>  					"screen type already set\n", f);
>  			} else {
>  				int li = f - '0';
> -				if (li >= ARRAY_SIZE(real6410_fb_win))
> +				if (li >= ARRAY_SIZE(real6410_lcd_pdata))
>  					printk(KERN_INFO "REAL6410: '%c' out "
>  						"of range LCD mode\n", f);
>  				else {
> @@ -288,13 +296,11 @@ static void __init real6410_machine_init(void)
>  	/* Parse the feature string */
>  	real6410_parse_features(&features, real6410_features_str);
> 
> -	real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
> -
>  	printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
> -		real6410_lcd_pdata.win[0]->win_mode.xres,
> -		real6410_lcd_pdata.win[0]->win_mode.yres);
> +		real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.xres,
> +		real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.yres);
> 
> -	s3c_fb_set_platdata(&real6410_lcd_pdata);
> +	s3c_fb_set_platdata(&real6410_lcd_pdata[features.lcd_index]);
>  	s3c_nand_set_platdata(&real6410_nand_info);
>  	s3c24xx_ts_set_platdata(NULL);
> 
> --
> 1.6.6.rc2



From jg1.han at samsung.com  Wed Mar 28 06:07:14 2012
From: jg1.han at samsung.com (Jingoo Han)
Date: Wed, 28 Mar 2012 19:07:14 +0900
Subject: [PATCH v3 4/4] ARM: Samsung: Rework platform data of s3c-fb driver
In-Reply-To: <1332606528-32338-5-git-send-email-thomas.abraham@linaro.org>
References: <1332606528-32338-1-git-send-email-thomas.abraham@linaro.org>
 <1332606528-32338-5-git-send-email-thomas.abraham@linaro.org>
Message-ID: <008701cd0cca$8cbc7320$a6355960$%han@samsung.com>

On 25 March 2012 01:29, Thomas Abraham < thomas.abraham at linaro.org> wrote:
> Subject: [PATCH v3 4/4] ARM: Samsung: Rework platform data of s3c-fb driver
> 
> For all the Samsung SoC based boards which have the platform data for
> s3c-fb driver, the 'default_win' element in the platform data is removed
> and the lcd panel video timing values are moved out of individual window
> configuration data.
> 
> Cc: Jingoo Han <jg1.han at samsung.com>

It looks good for SMDK boards.

Acked-by: Jingoo Han <jg1.han at samsung.com>

> Cc: Kyungmin Park <kyungmin.park at samsung.com>
> Cc: JeongHyeon Kim <jhkim at insignal.co.kr>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Cc: Heiko Stuebner <heiko at sntech.de>
> Cc: Ben Dooks <ben-linux at fluff.org>
> Cc: Kwangwoo Lee <kwangwoo.lee at gmail.com>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Peter Korsgaard <jacmet at sunsite.dk>
> Cc: Darius Augulis <augulis.darius at gmail.com>
> Cc: Maurus Cuelenaere <mcuelenaere at gmail.com>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> ---
>  arch/arm/mach-exynos/mach-nuri.c           |   26 ++++++++------
>  arch/arm/mach-exynos/mach-origen.c         |   24 +++++++-----
>  arch/arm/mach-exynos/mach-smdkv310.c       |   28 ++++++++------
>  arch/arm/mach-exynos/mach-universal_c210.c |   26 ++++++++------
>  arch/arm/mach-s3c24xx/mach-smdk2416.c      |   27 ++++++++------
>  arch/arm/mach-s3c64xx/mach-anw6410.c       |   25 +++++++------
>  arch/arm/mach-s3c64xx/mach-crag6410.c      |   25 +++++++------
>  arch/arm/mach-s3c64xx/mach-hmt.c           |   24 +++++++-----
>  arch/arm/mach-s3c64xx/mach-mini6410.c      |   54 ++++++++++++++++-----------
>  arch/arm/mach-s3c64xx/mach-real6410.c      |   52 +++++++++++++++-----------
>  arch/arm/mach-s3c64xx/mach-smartq5.c       |   26 ++++++++------
>  arch/arm/mach-s3c64xx/mach-smartq7.c       |   26 ++++++++------
>  arch/arm/mach-s3c64xx/mach-smdk6410.c      |   25 +++++++------
>  arch/arm/mach-s5p64x0/mach-smdk6440.c      |   24 +++++++-----
>  arch/arm/mach-s5p64x0/mach-smdk6450.c      |   24 +++++++-----
>  arch/arm/mach-s5pc100/mach-smdkc100.c      |   27 ++++++++------
>  arch/arm/mach-s5pv210/mach-aquila.c        |   36 ++++++++----------
>  arch/arm/mach-s5pv210/mach-goni.c          |   26 ++++++++------
>  arch/arm/mach-s5pv210/mach-smdkv210.c      |   24 +++++++-----
>  19 files changed, 311 insertions(+), 238 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
> index 7ac81ce..a7e6731 100644
> --- a/arch/arm/mach-exynos/mach-nuri.c
> +++ b/arch/arm/mach-exynos/mach-nuri.c
> @@ -212,25 +212,29 @@ static struct platform_device nuri_gpio_keys = {
> 
>  /* Frame Buffer */
>  static struct s3c_fb_pd_win nuri_fb_win0 = {
> -	.win_mode = {
> -		.left_margin	= 64,
> -		.right_margin	= 16,
> -		.upper_margin	= 64,
> -		.lower_margin	= 1,
> -		.hsync_len	= 48,
> -		.vsync_len	= 3,
> -		.xres		= 1024,
> -		.yres		= 600,
> -		.refresh	= 60,
> -	},
>  	.max_bpp	= 24,
>  	.default_bpp	= 16,
> +	.xres		= 1024,
> +	.yres		= 600,
>  	.virtual_x	= 1024,
>  	.virtual_y	= 2 * 600,
>  };
> 
> +static struct fb_videomode nuri_lcd_timing = {
> +	.left_margin	= 64,
> +	.right_margin	= 16,
> +	.upper_margin	= 64,
> +	.lower_margin	= 1,
> +	.hsync_len	= 48,
> +	.vsync_len	= 3,
> +	.xres		= 1024,
> +	.yres		= 600,
> +	.refresh	= 60,
> +};
> +
>  static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
>  	.win[0]		= &nuri_fb_win0,
> +	.vtiming	= &nuri_lcd_timing,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
>  			  VIDCON0_CLKSEL_LCD,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
> index 25c9b46..de71237 100644
> --- a/arch/arm/mach-exynos/mach-origen.c
> +++ b/arch/arm/mach-exynos/mach-origen.c
> @@ -583,22 +583,26 @@ static struct platform_device origen_lcd_hv070wsa = {
>  };
> 
>  static struct s3c_fb_pd_win origen_fb_win0 = {
> -	.win_mode = {
> -		.left_margin	= 64,
> -		.right_margin	= 16,
> -		.upper_margin	= 64,
> -		.lower_margin	= 16,
> -		.hsync_len	= 48,
> -		.vsync_len	= 3,
> -		.xres		= 1024,
> -		.yres		= 600,
> -	},
> +	.xres			= 1024,
> +	.yres			= 600,
>  	.max_bpp		= 32,
>  	.default_bpp		= 24,
>  };
> 
> +static struct fb_videomode origen_lcd_timing = {
> +	.left_margin	= 64,
> +	.right_margin	= 16,
> +	.upper_margin	= 64,
> +	.lower_margin	= 16,
> +	.hsync_len	= 48,
> +	.vsync_len	= 3,
> +	.xres		= 1024,
> +	.yres		= 600,
> +};
> +
>  static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
>  	.win[0]		= &origen_fb_win0,
> +	.vtiming	= &origen_lcd_timing,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
>  				VIDCON1_INV_VCLK,
> diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
> index f08529f..6c00fa6 100644
> --- a/arch/arm/mach-exynos/mach-smdkv310.c
> +++ b/arch/arm/mach-exynos/mach-smdkv310.c
> @@ -157,22 +157,26 @@ static struct platform_device smdkv310_lcd_lte480wv = {
>  };
> 
>  static struct s3c_fb_pd_win smdkv310_fb_win0 = {
> -	.win_mode = {
> -		.left_margin	= 13,
> -		.right_margin	= 8,
> -		.upper_margin	= 7,
> -		.lower_margin	= 5,
> -		.hsync_len	= 3,
> -		.vsync_len	= 1,
> -		.xres		= 800,
> -		.yres		= 480,
> -	},
> -	.max_bpp		= 32,
> -	.default_bpp		= 24,
> +	.max_bpp	= 32,
> +	.default_bpp	= 24,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
> +static struct fb_videomode smdkv310_lcd_timing = {
> +	.left_margin	= 13,
> +	.right_margin	= 8,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
>  };
> 
>  static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
>  	.win[0]		= &smdkv310_fb_win0,
> +	.vtiming	= &smdkv310_lcd_timing,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>  	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
> diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
> index 57e4418..67a9547 100644
> --- a/arch/arm/mach-exynos/mach-universal_c210.c
> +++ b/arch/arm/mach-exynos/mach-universal_c210.c
> @@ -813,25 +813,29 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
> 
>  /* Frame Buffer */
>  static struct s3c_fb_pd_win universal_fb_win0 = {
> -	.win_mode = {
> -		.left_margin	= 16,
> -		.right_margin	= 16,
> -		.upper_margin	= 2,
> -		.lower_margin	= 28,
> -		.hsync_len	= 2,
> -		.vsync_len	= 1,
> -		.xres		= 480,
> -		.yres		= 800,
> -		.refresh	= 55,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 480,
> +	.yres		= 800,
>  	.virtual_x	= 480,
>  	.virtual_y	= 2 * 800,
>  };
> 
> +static struct fb_videomode universal_lcd_timing = {
> +	.left_margin	= 16,
> +	.right_margin	= 16,
> +	.upper_margin	= 2,
> +	.lower_margin	= 28,
> +	.hsync_len	= 2,
> +	.vsync_len	= 1,
> +	.xres		= 480,
> +	.yres		= 800,
> +	.refresh	= 55,
> +};
> +
>  static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
>  	.win[0]		= &universal_fb_win0,
> +	.vtiming	= &universal_lcd_timing,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
>  			  VIDCON0_CLKSEL_LCD,
>  	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
> diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
> index 30a44f8..c3100a0 100644
> --- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
> +++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
> @@ -148,23 +148,25 @@ static struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
> 
>  static struct s3c_fb_pd_win smdk2416_fb_win[] = {
>  	[0] = {
> -		/* think this is the same as the smdk6410 */
> -		.win_mode	= {
> -			.pixclock	= 41094,
> -			.left_margin	= 8,
> -			.right_margin	= 13,
> -			.upper_margin	= 7,
> -			.lower_margin	= 5,
> -			.hsync_len	= 3,
> -			.vsync_len	= 1,
> -			.xres           = 800,
> -			.yres           = 480,
> -		},
>  		.default_bpp	= 16,
>  		.max_bpp	= 32,
> +		.xres           = 800,
> +		.yres           = 480,
>  	},
>  };
> 
> +static struct fb_videomode smdk2416_lcd_timing = {
> +	.pixclock	= 41094,
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres           = 800,
> +	.yres           = 480,
> +};
> +
>  static void s3c2416_fb_gpio_setup_24bpp(void)
>  {
>  	unsigned int gpio;
> @@ -187,6 +189,7 @@ static void s3c2416_fb_gpio_setup_24bpp(void)
> 
>  static struct s3c_fb_platdata smdk2416_fb_platdata = {
>  	.win[0]		= &smdk2416_fb_win[0],
> +	.vtiming	= &smdk2416_lcd_timing,
>  	.setup_gpio	= s3c2416_fb_gpio_setup_24bpp,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
> index b86f277..58fd0e3 100644
> --- a/arch/arm/mach-s3c64xx/mach-anw6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
> @@ -134,24 +134,27 @@ static struct platform_device anw6410_lcd_powerdev = {
>  };
> 
>  static struct s3c_fb_pd_win anw6410_fb_win0 = {
> -	/* this is to ensure we use win0 */
> -	.win_mode	= {
> -		.left_margin	= 8,
> -		.right_margin	= 13,
> -		.upper_margin	= 7,
> -		.lower_margin	= 5,
> -		.hsync_len	= 3,
> -		.vsync_len	= 1,
> -		.xres		= 800,
> -		.yres		= 480,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
> +static struct fb_videomode anw6410_lcd_timing = {
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
>  };
> 
>  /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
>  static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
>  	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +	.vtiming	= &anw6410_lcd_timing,
>  	.win[0]		= &anw6410_fb_win0,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
> index e20bf58..c1ef57e 100644
> --- a/arch/arm/mach-s3c64xx/mach-crag6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
> @@ -151,26 +151,29 @@ static struct platform_device crag6410_lcd_powerdev = {
> 
>  /* 640x480 URT */
>  static struct s3c_fb_pd_win crag6410_fb_win0 = {
> -	/* this is to ensure we use win0 */
> -	.win_mode	= {
> -		.left_margin	= 150,
> -		.right_margin	= 80,
> -		.upper_margin	= 40,
> -		.lower_margin	= 5,
> -		.hsync_len	= 40,
> -		.vsync_len	= 5,
> -		.xres		= 640,
> -		.yres		= 480,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 640,
> +	.yres		= 480,
>  	.virtual_y	= 480 * 2,
>  	.virtual_x	= 640,
>  };
> 
> +static struct fb_videomode crag6410_lcd_timing = {
> +	.left_margin	= 150,
> +	.right_margin	= 80,
> +	.upper_margin	= 40,
> +	.lower_margin	= 5,
> +	.hsync_len	= 40,
> +	.vsync_len	= 5,
> +	.xres		= 640,
> +	.yres		= 480,
> +};
> +
>  /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
>  static struct s3c_fb_platdata crag6410_lcd_pdata __initdata = {
>  	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +	.vtiming	= &crag6410_lcd_timing,
>  	.win[0]		= &crag6410_fb_win0,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
> index 521e07b..4e9b1ac 100644
> --- a/arch/arm/mach-s3c64xx/mach-hmt.c
> +++ b/arch/arm/mach-s3c64xx/mach-hmt.c
> @@ -129,23 +129,27 @@ static struct platform_device hmt_backlight_device = {
>  };
> 
>  static struct s3c_fb_pd_win hmt_fb_win0 = {
> -	.win_mode	= {
> -		.left_margin	= 8,
> -		.right_margin	= 13,
> -		.upper_margin	= 7,
> -		.lower_margin	= 5,
> -		.hsync_len	= 3,
> -		.vsync_len	= 1,
> -		.xres		= 800,
> -		.yres		= 480,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
> +static struct fb_videomode hmt_lcd_timing = {
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
>  };
> 
>  /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
>  static struct s3c_fb_platdata hmt_lcd_pdata __initdata = {
>  	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +	.vtiming	= &hmt_lcd_timing,
>  	.win[0]		= &hmt_fb_win0,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
> index 34f5195..2f425d5 100644
> --- a/arch/arm/mach-s3c64xx/mach-mini6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
> @@ -152,43 +152,53 @@ static struct s3c2410_platform_nand mini6410_nand_info = {
>  };
> 
>  static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
> -	.win_mode	= {	/* 4.3" 480x272 */
> -		.left_margin	= 3,
> -		.right_margin	= 2,
> -		.upper_margin	= 1,
> -		.lower_margin	= 1,
> -		.hsync_len	= 40,
> -		.vsync_len	= 1,
> -		.xres		= 480,
> -		.yres		= 272,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 480,
> +	.yres		= 272,
> +};
> +
> +static struct fb_videomode mini6410_lcd_type0_timing = {
> +	/* 4.3" 480x272 */
> +	.left_margin	= 3,
> +	.right_margin	= 2,
> +	.upper_margin	= 1,
> +	.lower_margin	= 1,
> +	.hsync_len	= 40,
> +	.vsync_len	= 1,
> +	.xres		= 480,
> +	.yres		= 272,
>  };
> 
>  static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
> -	.win_mode	= {	/* 7.0" 800x480 */
> -		.left_margin	= 8,
> -		.right_margin	= 13,
> -		.upper_margin	= 7,
> -		.lower_margin	= 5,
> -		.hsync_len	= 3,
> -		.vsync_len	= 1,
> -		.xres		= 800,
> -		.yres		= 480,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
> +static struct fb_videomode mini6410_lcd_type1_timing = {
> +	/* 7.0" 800x480 */
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
>  };
> 
>  static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
>  	{
>  		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +		.vtiming	= &mini6410_lcd_type0_timing,
>  		.win[0]		= &mini6410_lcd_type0_fb_win,
>  		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>  	}, {
>  		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +		.vtiming	= &mini6410_lcd_type1_timing,
>  		.win[0]		= &mini6410_lcd_type1_fb_win,
>  		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> @@ -316,8 +326,8 @@ static void __init mini6410_machine_init(void)
>  	mini6410_parse_features(&features, mini6410_features_str);
> 
>  	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
> -		mini6410_lcd_pdata[features.lcd_index].win[0]->win_mode.xres,
> -		mini6410_lcd_pdata[features.lcd_index].win[0]->win_mode.yres);
> +		mini6410_lcd_pdata[features.lcd_index].win[0]->xres,
> +		mini6410_lcd_pdata[features.lcd_index].win[0]->yres);
> 
>  	s3c_nand_set_platdata(&mini6410_nand_info);
>  	s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
> diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
> index 21f91e5..0fbd32c 100644
> --- a/arch/arm/mach-s3c64xx/mach-real6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-real6410.c
> @@ -118,43 +118,51 @@ static struct platform_device real6410_device_eth = {
>  };
> 
>  static struct s3c_fb_pd_win real6410_lcd_type0_fb_win = {
> -	.win_mode	= {	/* 4.3" 480x272 */
> -		.left_margin	= 3,
> -		.right_margin	= 2,
> -		.upper_margin	= 1,
> -		.lower_margin	= 1,
> -		.hsync_len	= 40,
> -		.vsync_len	= 1,
> -		.xres		= 480,
> -		.yres		= 272,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 480,
> +	.yres		= 272,
> +};
> +
> +static struct fb_videomode real6410_lcd_type0_timing = {
> +	/* 4.3" 480x272 */
> +	.left_margin	= 3,
> +	.right_margin	= 2,
> +	.upper_margin	= 1,
> +	.lower_margin	= 1,
> +	.hsync_len	= 40,
> +	.vsync_len	= 1,
>  };
> 
>  static struct s3c_fb_pd_win real6410_lcd_type1_fb_win = {
> -	.win_mode	= {	/* 7.0" 800x480 */
> -		.left_margin	= 8,
> -		.right_margin	= 13,
> -		.upper_margin	= 7,
> -		.lower_margin	= 5,
> -		.hsync_len	= 3,
> -		.vsync_len	= 1,
> -		.xres		= 800,
> -		.yres		= 480,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
> +static struct fb_videomode real6410_lcd_type1_timing = {
> +	/* 7.0" 800x480 */
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
>  };
> 
>  static struct s3c_fb_platdata real6410_lcd_pdata[] __initdata = {
>  	{
>  		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +		.vtiming	= &real6410_lcd_type0_timing,
>  		.win[0]		= &real6410_lcd_type0_fb_win,
>  		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>  	}, {
>  		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +		.vtiming	= &real6410_lcd_type1_timing,
>  		.win[0]		= &real6410_lcd_type1_fb_win,
>  		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> @@ -297,8 +305,8 @@ static void __init real6410_machine_init(void)
>  	real6410_parse_features(&features, real6410_features_str);
> 
>  	printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
> -		real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.xres,
> -		real6410_lcd_pdata[features.lcd_index].win[0]->win_mode.yres);
> +		real6410_lcd_pdata[features.lcd_index].win[0]->xres,
> +		real6410_lcd_pdata[features.lcd_index].win[0]->yres);
> 
>  	s3c_fb_set_platdata(&real6410_lcd_pdata[features.lcd_index]);
>  	s3c_nand_set_platdata(&real6410_nand_info);
> diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
> index 3f42431..03a2f88 100644
> --- a/arch/arm/mach-s3c64xx/mach-smartq5.c
> +++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
> @@ -108,23 +108,27 @@ static struct platform_device smartq5_buttons_device  = {
>  };
> 
>  static struct s3c_fb_pd_win smartq5_fb_win0 = {
> -	.win_mode	= {
> -		.left_margin	= 216,
> -		.right_margin	= 40,
> -		.upper_margin	= 35,
> -		.lower_margin	= 10,
> -		.hsync_len	= 1,
> -		.vsync_len	= 1,
> -		.xres		= 800,
> -		.yres		= 480,
> -		.refresh	= 80,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
> +static struct fb_videomode smartq5_lcd_timing = {
> +	.left_margin	= 216,
> +	.right_margin	= 40,
> +	.upper_margin	= 35,
> +	.lower_margin	= 10,
> +	.hsync_len	= 1,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
> +	.refresh	= 80,
>  };
> 
>  static struct s3c_fb_platdata smartq5_lcd_pdata __initdata = {
>  	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +	.vtiming	= &smartq5_lcd_timing,
>  	.win[0]		= &smartq5_fb_win0,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
> diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
> index e5c09b6..4e3b038 100644
> --- a/arch/arm/mach-s3c64xx/mach-smartq7.c
> +++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
> @@ -124,23 +124,27 @@ static struct platform_device smartq7_buttons_device  = {
>  };
> 
>  static struct s3c_fb_pd_win smartq7_fb_win0 = {
> -	.win_mode	= {
> -		.left_margin	= 3,
> -		.right_margin	= 5,
> -		.upper_margin	= 1,
> -		.lower_margin	= 20,
> -		.hsync_len	= 10,
> -		.vsync_len	= 3,
> -		.xres		= 800,
> -		.yres		= 480,
> -		.refresh	= 80,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
> +static struct fb_videomode smartq7_lcd_timing = {
> +	.left_margin	= 3,
> +	.right_margin	= 5,
> +	.upper_margin	= 1,
> +	.lower_margin	= 20,
> +	.hsync_len	= 10,
> +	.vsync_len	= 3,
> +	.xres		= 800,
> +	.yres		= 480,
> +	.refresh	= 80,
>  };
> 
>  static struct s3c_fb_platdata smartq7_lcd_pdata __initdata = {
>  	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +	.vtiming	= &smartq7_lcd_timing,
>  	.win[0]		= &smartq7_fb_win0,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
> diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
> index d55bc96..3cfc90f 100644
> --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
> +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
> @@ -146,26 +146,29 @@ static struct platform_device smdk6410_lcd_powerdev = {
>  };
> 
>  static struct s3c_fb_pd_win smdk6410_fb_win0 = {
> -	/* this is to ensure we use win0 */
> -	.win_mode	= {
> -		.left_margin	= 8,
> -		.right_margin	= 13,
> -		.upper_margin	= 7,
> -		.lower_margin	= 5,
> -		.hsync_len	= 3,
> -		.vsync_len	= 1,
> -		.xres		= 800,
> -		.yres		= 480,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 800,
> +	.yres		= 480,
>  	.virtual_y	= 480 * 2,
>  	.virtual_x	= 800,
>  };
> 
> +static struct fb_videomode smdk6410_lcd_timing = {
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
>  /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
>  static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
>  	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
> +	.vtiming	= &smdk6410_lcd_timing,
>  	.win[0]		= &smdk6410_fb_win0,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
> diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
> index a40e325..92fefad 100644
> --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
> +++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
> @@ -103,22 +103,26 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
> 
>  /* Frame Buffer */
>  static struct s3c_fb_pd_win smdk6440_fb_win0 = {
> -	.win_mode = {
> -		.left_margin	= 8,
> -		.right_margin	= 13,
> -		.upper_margin	= 7,
> -		.lower_margin	= 5,
> -		.hsync_len	= 3,
> -		.vsync_len	= 1,
> -		.xres		= 800,
> -		.yres		= 480,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 24,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
> +static struct fb_videomode smdk6440_lcd_timing = {
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
>  };
> 
>  static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = {
>  	.win[0]		= &smdk6440_fb_win0,
> +	.vtiming	= &smdk6440_lcd_timing,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>  	.setup_gpio	= s5p64x0_fb_gpio_setup_24bpp,
> diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
> index efb69e2..e2335ec 100644
> --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
> +++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
> @@ -121,22 +121,26 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
> 
>  /* Frame Buffer */
>  static struct s3c_fb_pd_win smdk6450_fb_win0 = {
> -	.win_mode	= {
> -		.left_margin	= 8,
> -		.right_margin	= 13,
> -		.upper_margin	= 7,
> -		.lower_margin	= 5,
> -		.hsync_len	= 3,
> -		.vsync_len	= 1,
> -		.xres		= 800,
> -		.yres		= 480,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 24,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
> +static struct fb_videomode smdk6450_lcd_timing = {
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
>  };
> 
>  static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = {
>  	.win[0]		= &smdk6450_fb_win0,
> +	.vtiming	= &smdk6450_lcd_timing,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>  	.setup_gpio	= s5p64x0_fb_gpio_setup_24bpp,
> diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
> index 674d229..0c3ae38 100644
> --- a/arch/arm/mach-s5pc100/mach-smdkc100.c
> +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
> @@ -136,24 +136,27 @@ static struct platform_device smdkc100_lcd_powerdev = {
> 
>  /* Frame Buffer */
>  static struct s3c_fb_pd_win smdkc100_fb_win0 = {
> -	/* this is to ensure we use win0 */
> -	.win_mode	= {
> -		.left_margin	= 8,
> -		.right_margin	= 13,
> -		.upper_margin	= 7,
> -		.lower_margin	= 5,
> -		.hsync_len	= 3,
> -		.vsync_len	= 1,
> -		.xres		= 800,
> -		.yres		= 480,
> -		.refresh	= 80,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
> +static struct fb_videomode smdkc100_lcd_timing = {
> +	.left_margin	= 8,
> +	.right_margin	= 13,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
> +	.refresh	= 80,
>  };
> 
>  static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
>  	.win[0]		= &smdkc100_fb_win0,
> +	.vtiming	= &smdkc100_lcd_timing,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>  	.setup_gpio	= s5pc100_fb_gpio_setup_24bpp,
> diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
> index a9ea64e..7b91bbf 100644
> --- a/arch/arm/mach-s5pv210/mach-aquila.c
> +++ b/arch/arm/mach-s5pv210/mach-aquila.c
> @@ -96,38 +96,34 @@ static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
> 
>  /* Frame Buffer */
>  static struct s3c_fb_pd_win aquila_fb_win0 = {
> -	.win_mode = {
> -		.left_margin = 16,
> -		.right_margin = 16,
> -		.upper_margin = 3,
> -		.lower_margin = 28,
> -		.hsync_len = 2,
> -		.vsync_len = 2,
> -		.xres = 480,
> -		.yres = 800,
> -	},
>  	.max_bpp = 32,
>  	.default_bpp = 16,
> +	.xres = 480,
> +	.yres = 800,
>  };
> 
>  static struct s3c_fb_pd_win aquila_fb_win1 = {
> -	.win_mode = {
> -		.left_margin = 16,
> -		.right_margin = 16,
> -		.upper_margin = 3,
> -		.lower_margin = 28,
> -		.hsync_len = 2,
> -		.vsync_len = 2,
> -		.xres = 480,
> -		.yres = 800,
> -	},
>  	.max_bpp = 32,
>  	.default_bpp = 16,
> +	.xres = 480,
> +	.yres = 800,
> +};
> +
> +static struct fb_videomode aquila_lcd_timing = {
> +	.left_margin = 16,
> +	.right_margin = 16,
> +	.upper_margin = 3,
> +	.lower_margin = 28,
> +	.hsync_len = 2,
> +	.vsync_len = 2,
> +	.xres = 480,
> +	.yres = 800,
>  };
> 
>  static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
>  	.win[0]		= &aquila_fb_win0,
>  	.win[1]		= &aquila_fb_win1,
> +	.vtiming	= &aquila_lcd_timing,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
>  			  VIDCON1_INV_VCLK | VIDCON1_INV_VDEN,
> diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
> index 2cf5ed7..07a840d 100644
> --- a/arch/arm/mach-s5pv210/mach-goni.c
> +++ b/arch/arm/mach-s5pv210/mach-goni.c
> @@ -105,25 +105,29 @@ static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
> 
>  /* Frame Buffer */
>  static struct s3c_fb_pd_win goni_fb_win0 = {
> -	.win_mode = {
> -		.left_margin	= 16,
> -		.right_margin	= 16,
> -		.upper_margin	= 2,
> -		.lower_margin	= 28,
> -		.hsync_len	= 2,
> -		.vsync_len	= 1,
> -		.xres		= 480,
> -		.yres		= 800,
> -		.refresh	= 55,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 16,
> +	.xres		= 480,
> +	.yres		= 800,
>  	.virtual_x	= 480,
>  	.virtual_y	= 2 * 800,
>  };
> 
> +static struct fb_videomode goni_lcd_timing = {
> +	.left_margin	= 16,
> +	.right_margin	= 16,
> +	.upper_margin	= 2,
> +	.lower_margin	= 28,
> +	.hsync_len	= 2,
> +	.vsync_len	= 1,
> +	.xres		= 480,
> +	.yres		= 800,
> +	.refresh	= 55,
> +};
> +
>  static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
>  	.win[0]		= &goni_fb_win0,
> +	.vtiming	= &goni_lcd_timing,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
>  			  VIDCON0_CLKSEL_LCD,
>  	.vidcon1	= VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
> diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
> index 91d4ad8..5e0c955 100644
> --- a/arch/arm/mach-s5pv210/mach-smdkv210.c
> +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
> @@ -189,22 +189,26 @@ static struct platform_device smdkv210_lcd_lte480wv = {
>  };
> 
>  static struct s3c_fb_pd_win smdkv210_fb_win0 = {
> -	.win_mode = {
> -		.left_margin	= 13,
> -		.right_margin	= 8,
> -		.upper_margin	= 7,
> -		.lower_margin	= 5,
> -		.hsync_len	= 3,
> -		.vsync_len	= 1,
> -		.xres		= 800,
> -		.yres		= 480,
> -	},
>  	.max_bpp	= 32,
>  	.default_bpp	= 24,
> +	.xres		= 800,
> +	.yres		= 480,
> +};
> +
> +static struct fb_videomode smdkv210_lcd_timing = {
> +	.left_margin	= 13,
> +	.right_margin	= 8,
> +	.upper_margin	= 7,
> +	.lower_margin	= 5,
> +	.hsync_len	= 3,
> +	.vsync_len	= 1,
> +	.xres		= 800,
> +	.yres		= 480,
>  };
> 
>  static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
>  	.win[0]		= &smdkv210_fb_win0,
> +	.vtiming	= &smdkv210_lcd_timing,
>  	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
>  	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
>  	.setup_gpio	= s5pv210_fb_gpio_setup_24bpp,
> --
> 1.6.6.rc2



From broonie at opensource.wolfsonmicro.com  Wed Mar 28 06:07:44 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 11:07:44 +0100
Subject: [PATCH 07/10] clk: Constify parent name arrays
In-Reply-To: <CAJOA=zOXwtpefp2vgHprnmdpaOsHzo_rtMPMrN=X=K7YXM2EYA@mail.gmail.com>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-8-git-send-email-shawn.guo@linaro.org>
 <CAJOA=zOXwtpefp2vgHprnmdpaOsHzo_rtMPMrN=X=K7YXM2EYA@mail.gmail.com>
Message-ID: <20120328100743.GC3232@opensource.wolfsonmicro.com>

On Tue, Mar 27, 2012 at 06:03:49PM -0700, Turquette, Mike wrote:

> Mark, I've taken this in to my fixes branch, but I dropped the change
> in drivers/clk/clk-fixed-rate.c (since that code has shuffled) and I
> also marked the char *parent[1] in fixed-rate and gate clocks as
> const, in addition to the divider you did in your patch.

That one's more fun as you should really be declaring them as something
like a const array of pointers to const char which is very cumbersome to
actually do and looks ugly as hell.
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From zengzm.kernel at gmail.com  Wed Mar 28 06:11:17 2012
From: zengzm.kernel at gmail.com (Zeng Zhaoming)
Date: Wed, 28 Mar 2012 18:11:17 +0800
Subject: [alsa-devel] [PATCH] ASoC: sgtl5000: fix power on/off of MIC bias
In-Reply-To: <7FE21149F4667147B645348EC605788514EDFF@039-SN2MPN1-011.039d.mgd.msft.net>
References: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
 <7FE21149F4667147B645348EC605788514EDFF@039-SN2MPN1-011.039d.mgd.msft.net>
Message-ID: <20120328101117.GA2940@zzm-ubuntu>

On Wed 2012-03-28 09:52:15, Dong Aisheng-B29396 wrote:
> > -----Original Message-----
> > From: alsa-devel-bounces at alsa-project.org [mailto:alsa-devel-
> > bounces at alsa-project.org] On Behalf Of Shawn Guo
> > Sent: Wednesday, March 28, 2012 3:31 PM
> > To: alsa-devel at alsa-project.org
> > Cc: Xu Lionel-R63889; Mark Brown; Zeng at alsa-project.org; Zhaoming; Shawn
> > Guo; Xu Lionel-R63889; linux-arm-kernel at lists.infradead.org
> > Subject: [alsa-devel] [PATCH] ASoC: sgtl5000: fix power on/off of MIC
> > bias
> > 
> > From: Lionel Xu <Lionel.Xu at freescale.com>
> > 
> > There is no sound in the recorded wav, to enable recording, the VAG
> > should be powered up, and the mic bias resistor should be set up with
> > proper value.
> > 
> > Signed-off-by: Lionel Xu <lionel.xu at freescale.com>
> > Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> > Cc: Zeng Zhaoming <zengzm.kernel at gmail.com>
> > ---
> >  sound/soc/codecs/sgtl5000.c |   14 +++++++++++---
> >  1 files changed, 11 insertions(+), 3 deletions(-)
> > 
> > diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
> > index d192626..a24299c 100644
> > --- a/sound/soc/codecs/sgtl5000.c
> > +++ b/sound/soc/codecs/sgtl5000.c
> > @@ -132,11 +132,18 @@ static int mic_bias_event(struct
> > snd_soc_dapm_widget *w,
> >  		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
> >  				SGTL5000_BIAS_R_MASK,
> >  				SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
> > +
> > +		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
> > +				SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
> Did you test line-in record?
> IIRC for line-in record, it may also need VAG_POWER up.
> Then only enable VAG_POWER for mic_bias_event may not be sufficient.
> Will verify it latter when I'm free.
> 
Yes, if mic bias needs VAG powerup, LINE-IN capture has the same issue.
But I remember Line-out test passed in mx28, it there any defect I ignored?

Thanks.
Zeng Zhaoming

> Regards
> Dong Aisheng
> 
> >  		break;
> > 
> >  	case SND_SOC_DAPM_PRE_PMD:
> >  		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
> > -				SGTL5000_BIAS_R_MASK, 0);
> > +				SGTL5000_BIAS_R_MASK,
> > +				SGTL5000_BIAS_R_off << SGTL5000_BIAS_R_SHIFT);
> > +
> > +		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
> > +				SGTL5000_VAG_POWERUP, 0);
> >  		break;
> >  	}
> >  	return 0;
> > @@ -197,7 +204,7 @@ static const struct snd_soc_dapm_widget
> > sgtl5000_dapm_widgets[] = {
> >  	SND_SOC_DAPM_OUTPUT("HP_OUT"),
> >  	SND_SOC_DAPM_OUTPUT("LINE_OUT"),
> > 
> > -	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
> > +	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SND_SOC_NOPM, 0, 0,
> >  				mic_bias_event,
> >  				SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
> > 
> > @@ -229,7 +236,8 @@ static const struct snd_soc_dapm_widget
> > sgtl5000_dapm_widgets[] = {
> >  /* routes for sgtl5000 */
> >  static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
> >  	{"Capture Mux", "LINE_IN", "LINE_IN"},	/* line_in --> adc_mux */
> > -	{"Capture Mux", "MIC_IN", "MIC_IN"},	/* mic_in --> adc_mux */
> > +	{"Mic Bias", NULL, "MIC_IN"},		/* mic_in --> mic bias */
> > +	{"Capture Mux", "MIC_IN", "Mic Bias"},	/* mic bias --> adc_mux
> > */
> > 
> >  	{"ADC", NULL, "Capture Mux"},		/* adc_mux --> adc */
> >  	{"AIFOUT", NULL, "ADC"},		/* adc --> i2s_out */
> > --
> > 1.7.4.1
> > 
> > 
> > _______________________________________________
> > Alsa-devel mailing list
> > Alsa-devel at alsa-project.org
> > http://mailman.alsa-project.org/mailman/listinfo/alsa-devel


From broonie at opensource.wolfsonmicro.com  Wed Mar 28 06:18:52 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 11:18:52 +0100
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <20120328094351.GB22414@n2100.arm.linux.org.uk>
References: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
 <1331242494-3157-1-git-send-email-paul.gortmaker@windriver.com>
 <CAN1soZzDRR4XQ34WDL48=j+Ff8t5fsCFaccqZAKOQ1OAPeDXcA@mail.gmail.com>
 <4F608F4F.8020106@windriver.com>
 <20120314123236.GE3133@opensource.wolfsonmicro.com>
 <20120328094351.GB22414@n2100.arm.linux.org.uk>
Message-ID: <20120328101852.GE3232@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 10:43:51AM +0100, Russell King - ARM Linux wrote:
> On Wed, Mar 14, 2012 at 12:32:36PM +0000, Mark Brown wrote:

> > Yes, that's what you should do.  Calling dev_name() is only possible if
> > you have the struct device and removing the need for the struct device
> > is exactly what we're trying to avoid here.

> So what the hell is happening here to fix the breakage which the
> regulator tree caused in mainline?  From this thread, it looks like
> it's been known about since 8th March which is now twenty days ago,
> and it's still broken.

Yes, please at least apply Paul's patches - honestly, given how old
these boards are and the general lack of activity I'd rather expect that
the only thing anyone's doing with them these days is build tests.
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From lee.jones at linaro.org  Wed Mar 28 06:49:47 2012
From: lee.jones at linaro.org (Lee Jones)
Date: Wed, 28 Mar 2012 11:49:47 +0100
Subject: [PATCH] ARM: ux500: fix compile error in new timer code
Message-ID: <1332931787-27741-1-git-send-email-lee.jones@linaro.org>

This patch fixes the errors below:

error: implicit declaration of function ?pr_err?
error: implicit declaration of function ?BUG?

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/mach-ux500/timer.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index e9d5807..21ec778 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -4,6 +4,8 @@
  * License Terms: GNU General Public License v2
  * Author: Mattias Wallin <mattias.wallin at stericsson.com> for ST-Ericsson
  */
+#include <linux/kernel.h>
+#include <linux/bug.h>
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/clksrc-dbx500-prcmu.h>
-- 
1.7.5.4



From broonie at opensource.wolfsonmicro.com  Wed Mar 28 06:51:22 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 11:51:22 +0100
Subject: [PATCH] ARM: Samsung: Make PM_GENERIC_DOMAINS config depend on
 CONFIG_PM
In-Reply-To: <1332843404-25476-1-git-send-email-thomas.ab@samsung.com>
References: <1332843404-25476-1-git-send-email-thomas.ab@samsung.com>
Message-ID: <20120328105122.GF3232@opensource.wolfsonmicro.com>

On Tue, Mar 27, 2012 at 03:46:43PM +0530, Thomas Abraham wrote:
> For s3c64xx and exynos platforms, make the selection of PM_GENERIC_DOMAINS
> depend on the CONFIG_PM.

What's the underlying issue here?  This seems like something the PM core
should be dealing with gracefully...
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From broonie at opensource.wolfsonmicro.com  Wed Mar 28 06:53:10 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 11:53:10 +0100
Subject: [PATCH] Regulator: anatop-regulator: patching to device-tree
 property "reg".
In-Reply-To: <1332834841-13925-1-git-send-email-paul.liu@linaro.org>
References: <1332834841-13925-1-git-send-email-paul.liu@linaro.org>
Message-ID: <20120328105310.GG3232@opensource.wolfsonmicro.com>

On Tue, Mar 27, 2012 at 03:54:01PM +0800, Ying-Chun Liu (PaulLiu) wrote:
> From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>
> 
> Change "reg" to "anatop-reg-offset" due to there is a warning of handling no
> size field in reg.
> 
> This patch also adds the missing device-tree binding documentation.

Applied, thanks, but please do split patches.
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From broonie at opensource.wolfsonmicro.com  Wed Mar 28 06:57:45 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 11:57:45 +0100
Subject: [PATCH 4/4] ARM i.MX 3ds debugboard: register a dummy regulator
 for the smsc911x device
In-Reply-To: <20120326181912.GV3852@pengutronix.de>
References: <1330774804-7310-1-git-send-email-s.hauer@pengutronix.de>
 <1330774804-7310-5-git-send-email-s.hauer@pengutronix.de>
 <CAOMZO5DL8YQT2qb=vxdQtdN+zfZLK9H9_1qu5sS+1YAvSo5SAA@mail.gmail.com>
 <20120326181912.GV3852@pengutronix.de>
Message-ID: <20120328105745.GH3232@opensource.wolfsonmicro.com>

On Mon, Mar 26, 2012 at 08:19:12PM +0200, Sascha Hauer wrote:

> At least it did work when I sent the patches, but -EPROBE_DEFER did not
> exist at that time. Do you have the fixed regulator enabled in your
> config?

FWIW all the -EPROBE_DEFER change does is change the error code returned
when we can't find a supply, if we're hitting that case we'd have failed
without it too.
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From broonie at opensource.wolfsonmicro.com  Wed Mar 28 07:07:36 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 12:07:36 +0100
Subject: [PATCH] ASoC: fsl: assign dma peripheral type according to bus
 topology
In-Reply-To: <1332920096-9701-1-git-send-email-shawn.guo@linaro.org>
References: <1332920096-9701-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120328110735.GL3232@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 03:34:56PM +0800, Shawn Guo wrote:
> The dma peripheral_type for SSI should be IMX_DMATYPE_SSI_SP if the SSI
> is on SPBA bus.

Applied, thanks.
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From govindraj.raja at ti.com  Wed Mar 28 07:09:37 2012
From: govindraj.raja at ti.com (Raja, Govindraj)
Date: Wed, 28 Mar 2012 16:39:37 +0530
Subject: [PATCH 1/3] OMAP2+: UART: Remove cpu checks for populating errata
 flags
In-Reply-To: <4F722C63.9080900@ti.com>
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
 <1332325501-10467-2-git-send-email-govindraj.raja@ti.com>
 <4F722C63.9080900@ti.com>
Message-ID: <CAMrsUdKfsoks4fB4GhrRcEur8niJsaWuYGE34+j5Bk6u2XiZQQ@mail.gmail.com>

On Wed, Mar 28, 2012 at 2:38 AM, Jon Hunter <jon-hunter at ti.com> wrote:
> Hi Govindraj,
>
>
> On 3/21/2012 5:24, Govindraj.R wrote:
>>
>> From: "Govindraj.R"<govindraj.raja at ti.com>
>>
>> Currently the errata is populated based on cpu checks this can
>> be removed and replaced with module version check of uart ip block.
>> MVR reg is provided within the uart reg map use the same
>> to populate the errata and thus now errata population and handling
>> can be managed within the driver itself.
>>
>> Cc: Paul Walmsley<paul at pwsan.com>
>> Cc: Kevin Hilman<khilman at ti.com>
>> Signed-off-by: Felipe Balbi<balbi at ti.com>
>> Signed-off-by: Govindraj.R<govindraj.raja at ti.com>
>> ---
>> ?arch/arm/mach-omap2/serial.c ? ? ? ? ? ? ? ? ?| ? ?8 ---
>> ?arch/arm/plat-omap/include/plat/omap-serial.h | ? ?1 -
>> ?drivers/tty/serial/omap-serial.c ? ? ? ? ? ? ?| ? 62
>> ++++++++++++++++++++++++-
>> ?3 files changed, 61 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
>> index f590afc..330ee04 100644
>> --- a/arch/arm/mach-omap2/serial.c
>> +++ b/arch/arm/mach-omap2/serial.c
>> @@ -357,14 +357,6 @@ void __init omap_serial_init_port(struct
>> omap_board_data *bdata,
>> ? ? ? ?omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
>> ? ? ? ?omap_up.autosuspend_timeout = info->autosuspend_timeout;
>>
>> - ? ? ? /* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
>> - ? ? ? if (!cpu_is_omap2420()&& ?!cpu_is_ti816x())
>>
>> - ? ? ? ? ? ? ? omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
>> -
>> - ? ? ? /* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
>> - ? ? ? if (cpu_is_omap34xx() || cpu_is_omap3630())
>> - ? ? ? ? ? ? ? omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
>> -
>> ? ? ? ?pdata =&omap_up;
>> ? ? ? ?pdata_size = sizeof(struct omap_uart_port_info);
>>
>> diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h
>> b/arch/arm/plat-omap/include/plat/omap-serial.h
>> index 9ff4444..1a52725 100644
>> --- a/arch/arm/plat-omap/include/plat/omap-serial.h
>> +++ b/arch/arm/plat-omap/include/plat/omap-serial.h
>> @@ -65,7 +65,6 @@ struct omap_uart_port_info {
>> ? ? ? ?bool ? ? ? ? ? ? ? ? ? ?dma_enabled; ? ?/* To specify DMA Mode */
>> ? ? ? ?unsigned int ? ? ? ? ? ?uartclk; ? ? ? ?/* UART clock rate */
>> ? ? ? ?upf_t ? ? ? ? ? ? ? ? ? flags; ? ? ? ? ?/* UPF_* flags */
>> - ? ? ? u32 ? ? ? ? ? ? ? ? ? ? errata;
>> ? ? ? ?unsigned int ? ? ? ? ? ?dma_rx_buf_size;
>> ? ? ? ?unsigned int ? ? ? ? ? ?dma_rx_timeout;
>> ? ? ? ?unsigned int ? ? ? ? ? ?autosuspend_timeout;
>> diff --git a/drivers/tty/serial/omap-serial.c
>> b/drivers/tty/serial/omap-serial.c
>> index f809041..c7666d6 100644
>> --- a/drivers/tty/serial/omap-serial.c
>> +++ b/drivers/tty/serial/omap-serial.c
>> @@ -44,6 +44,13 @@
>> ?#include<plat/dmtimer.h>
>> ?#include<plat/omap-serial.h>
>>
>> +#define UART_BUILD_REVISION(x, y) ? ? ?(((x)<< ?8) | (y))
>> +
>> +#define OMAP_UART_REV_42 0x0402
>> +#define OMAP_UART_REV_46 0x0406
>> +#define OMAP_UART_REV_52 0x0502
>> +#define OMAP_UART_REV_63 0x0603
>> +
>> ?#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
>>
>> ?/* SCR register bitmasks */
>> @@ -1346,6 +1353,58 @@ static void uart_tx_dma_callback(int lch, u16
>> ch_status, void *data)
>> ? ? ? ?return;
>> ?}
>>
>> +static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
>> +{
>> + ? ? ? u32 mvr, scheme;
>> + ? ? ? u16 revision, major, minor;
>> +
>> + ? ? ? mvr = serial_in(up, UART_OMAP_MVER);
>> +
>> + ? ? ? /* Check revision register scheme */
>> + ? ? ? scheme = mvr& ?(0x03<< ?30);
>> + ? ? ? scheme>>= 30;
>
>
> Minor nit-pick, why not ...
>
> ? ? ? ?scheme = mvr >> 30;
>

yes will correct it.

>
>> + ? ? ? switch (scheme) {
>> + ? ? ? case 0: /* Legacy Scheme: OMAP2/3 */
>> + ? ? ? ? ? ? ? /* MINOR_REV[0:4], MAJOR_REV[4:7] */
>
>
> This scheme is also true from OMAP1 devices. Maybe we could include in the
> comment.

No omap1 from $SUBJECT also reason,

mach-omap1/serial.c => 8250.c
mach-omap2/serial.c => omap-serial.c

>
>> + ? ? ? ? ? ? ? major = (mvr& ?0xf0)>> ?4;
>> + ? ? ? ? ? ? ? minor = (mvr& ?0x0f);
>>
>> + ? ? ? ? ? ? ? break;
>> + ? ? ? case 1:
>> + ? ? ? ? ? ? ? /* New Scheme: OMAP4+ */
>> + ? ? ? ? ? ? ? /* MINOR_REV[0:5], MAJOR_REV[8:10] */
>> + ? ? ? ? ? ? ? major = (mvr& ?0x7<< ?8)>> ?8;
>
>
> Nit-pick ...
>
> ? ? ? ?major = (mvr >> 8) & 0x7;

yes fine will correct this.

--
Thanks,
Govindraj.R


From R63889 at freescale.com  Wed Mar 28 07:17:13 2012
From: R63889 at freescale.com (Xu Lionel-R63889)
Date: Wed, 28 Mar 2012 11:17:13 +0000
Subject: [alsa-devel] [PATCH] ASoC: sgtl5000: fix power on/off of MIC bias
In-Reply-To: <20120328101117.GA2940@zzm-ubuntu>
References: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
 <7FE21149F4667147B645348EC605788514EDFF@039-SN2MPN1-011.039d.mgd.msft.net>
 <20120328101117.GA2940@zzm-ubuntu>
Message-ID: <1134DBD29ABD7C45BA97B9951E61EC9007DF10@039-SN2MPN1-011.039d.mgd.msft.net>

Yes, theoretically it should be added to line-in record too, 
I check the mx53smd board just now, found the line-in port is connected to a connector,
I am afraid we did not check the line-in record before. 

-----Original Message-----
From: Zeng Zhaoming [mailto:zengzm.kernel at gmail.com] 
Sent: Wednesday, March 28, 2012 6:11 PM
To: Dong Aisheng-B29396
Cc: Shawn Guo; alsa-devel at alsa-project.org; Xu Lionel-R63889; Mark Brown; Zeng at alsa-project.org; linux-arm-kernel at lists.infradead.org
Subject: Re: [alsa-devel] [PATCH] ASoC: sgtl5000: fix power on/off of MIC bias

On Wed 2012-03-28 09:52:15, Dong Aisheng-B29396 wrote:
> > -----Original Message-----
> > From: alsa-devel-bounces at alsa-project.org [mailto:alsa-devel- 
> > bounces at alsa-project.org] On Behalf Of Shawn Guo
> > Sent: Wednesday, March 28, 2012 3:31 PM
> > To: alsa-devel at alsa-project.org
> > Cc: Xu Lionel-R63889; Mark Brown; Zeng at alsa-project.org; Zhaoming; 
> > Shawn Guo; Xu Lionel-R63889; linux-arm-kernel at lists.infradead.org
> > Subject: [alsa-devel] [PATCH] ASoC: sgtl5000: fix power on/off of 
> > MIC bias
> > 
> > From: Lionel Xu <Lionel.Xu at freescale.com>
> > 
> > There is no sound in the recorded wav, to enable recording, the VAG 
> > should be powered up, and the mic bias resistor should be set up 
> > with proper value.
> > 
> > Signed-off-by: Lionel Xu <lionel.xu at freescale.com>
> > Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> > Cc: Zeng Zhaoming <zengzm.kernel at gmail.com>
> > ---
> >  sound/soc/codecs/sgtl5000.c |   14 +++++++++++---
> >  1 files changed, 11 insertions(+), 3 deletions(-)
> > 
> > diff --git a/sound/soc/codecs/sgtl5000.c 
> > b/sound/soc/codecs/sgtl5000.c index d192626..a24299c 100644
> > --- a/sound/soc/codecs/sgtl5000.c
> > +++ b/sound/soc/codecs/sgtl5000.c
> > @@ -132,11 +132,18 @@ static int mic_bias_event(struct 
> > snd_soc_dapm_widget *w,
> >  		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
> >  				SGTL5000_BIAS_R_MASK,
> >  				SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
> > +
> > +		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
> > +				SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
> Did you test line-in record?
> IIRC for line-in record, it may also need VAG_POWER up.
> Then only enable VAG_POWER for mic_bias_event may not be sufficient.
> Will verify it latter when I'm free.
> 
Yes, if mic bias needs VAG powerup, LINE-IN capture has the same issue.
But I remember Line-out test passed in mx28, it there any defect I ignored?

Thanks.
Zeng Zhaoming

> Regards
> Dong Aisheng
> 
> >  		break;
> > 
> >  	case SND_SOC_DAPM_PRE_PMD:
> >  		snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
> > -				SGTL5000_BIAS_R_MASK, 0);
> > +				SGTL5000_BIAS_R_MASK,
> > +				SGTL5000_BIAS_R_off << SGTL5000_BIAS_R_SHIFT);
> > +
> > +		snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
> > +				SGTL5000_VAG_POWERUP, 0);
> >  		break;
> >  	}
> >  	return 0;
> > @@ -197,7 +204,7 @@ static const struct snd_soc_dapm_widget 
> > sgtl5000_dapm_widgets[] = {
> >  	SND_SOC_DAPM_OUTPUT("HP_OUT"),
> >  	SND_SOC_DAPM_OUTPUT("LINE_OUT"),
> > 
> > -	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
> > +	SND_SOC_DAPM_MICBIAS_E("Mic Bias", SND_SOC_NOPM, 0, 0,
> >  				mic_bias_event,
> >  				SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
> > 
> > @@ -229,7 +236,8 @@ static const struct snd_soc_dapm_widget 
> > sgtl5000_dapm_widgets[] = {
> >  /* routes for sgtl5000 */
> >  static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
> >  	{"Capture Mux", "LINE_IN", "LINE_IN"},	/* line_in --> adc_mux */
> > -	{"Capture Mux", "MIC_IN", "MIC_IN"},	/* mic_in --> adc_mux */
> > +	{"Mic Bias", NULL, "MIC_IN"},		/* mic_in --> mic bias */
> > +	{"Capture Mux", "MIC_IN", "Mic Bias"},	/* mic bias --> adc_mux
> > */
> > 
> >  	{"ADC", NULL, "Capture Mux"},		/* adc_mux --> adc */
> >  	{"AIFOUT", NULL, "ADC"},		/* adc --> i2s_out */
> > --
> > 1.7.4.1
> > 
> > 
> > _______________________________________________
> > Alsa-devel mailing list
> > Alsa-devel at alsa-project.org
> > http://mailman.alsa-project.org/mailman/listinfo/alsa-devel




From thomas.abraham at linaro.org  Wed Mar 28 07:21:32 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 28 Mar 2012 16:51:32 +0530
Subject: [PATCH] ARM: Samsung: Make PM_GENERIC_DOMAINS config depend on
 CONFIG_PM
In-Reply-To: <20120328105122.GF3232@opensource.wolfsonmicro.com>
References: <1332843404-25476-1-git-send-email-thomas.ab@samsung.com>
 <20120328105122.GF3232@opensource.wolfsonmicro.com>
Message-ID: <CAJuYYwQgZqN6nguddjS6bjLhx_ZhUZ5AfcrSAKBa7Ft-Bn6wPQ@mail.gmail.com>

On 28 March 2012 16:21, Mark Brown <broonie at opensource.wolfsonmicro.com> wrote:
> On Tue, Mar 27, 2012 at 03:46:43PM +0530, Thomas Abraham wrote:
>> For s3c64xx and exynos platforms, make the selection of PM_GENERIC_DOMAINS
>> depend on the CONFIG_PM.
>
> What's the underlying issue here? ?This seems like something the PM core
> should be dealing with gracefully...

The PM_GENERIC_DOMAINS config option has dependency on CONFIG_PM
option. When building with PM disabled, the following errors occur.

warning: (PLAT_S3C64XX && CPU_EXYNOS4210) selects PM_GENERIC_DOMAINS
which has unmet direct dependencies (PM)
warning: (MACH_EXYNOS5_DT) selects SOC_EXYNOS5250 which has unmet
direct dependencies (ARCH_EXYNOS && ARCH_EXYNOS5)
warning: (PLAT_S3C64XX && CPU_EXYNOS4210) selects PM_GENERIC_DOMAINS
which has unmet direct dependencies (PM)
warning: (MACH_EXYNOS5_DT) selects SOC_EXYNOS5250 which has unmet
direct dependencies (ARCH_EXYNOS && ARCH_EXYNOS5)

[...]

drivers/base/power/domain.c: In function '__pm_genpd_add_device':
drivers/base/power/domain.c:1132: error: implicit declaration of
function 'genpd_acquire_lock'
drivers/base/power/domain.c:1168: error: implicit declaration of
function 'genpd_release_lock'
drivers/base/power/domain.c: In function 'pm_genpd_add_subdomain':
drivers/base/power/domain.c:1298: error: implicit declaration of
function 'genpd_sd_counter_inc'
drivers/base/power/domain.c: In function 'pm_genpd_remove_subdomain':
drivers/base/power/domain.c:1341: error: implicit declaration of
function 'genpd_sd_counter_dec'
make[3]: *** [drivers/base/power/domain.o] Error 1

Thanks,
Thomas.


From sshtylyov at mvista.com  Wed Mar 28 07:29:07 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 28 Mar 2012 15:29:07 +0400
Subject: [PATCHv2 01/14] common: dma-mapping: introduce alloc_attrs and
 free_attrs methods
In-Reply-To: <1332855768-32583-2-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
 <1332855768-32583-2-git-send-email-m.szyprowski@samsung.com>
Message-ID: <4F72F603.2000803@mvista.com>

Hello.

On 27-03-2012 17:42, Marek Szyprowski wrote:

> Introduce new generic alloc and free methods with attributes argument.

    The method names don't match the ones in the subject.

> Existing alloc_coherent and free_coherent can be implemented on top of the
> new calls with NULL attributes argument. Later also dma_alloc_non_coherent
> can be implemented using DMA_ATTR_NONCOHERENT attribute as well as
> dma_alloc_writecombine with separate DMA_ATTR_WRITECOMBINE attribute.

> This way the drivers will get more generic, platform independent way of
> allocating dma buffers with specific parameters.

> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
> Reviewed-by: David Gibson <david at gibson.dropbear.ud.au>
> Reviewed-by: Arnd Bergmann <arnd at arndb.de>

WBR, Sergei


From broonie at opensource.wolfsonmicro.com  Wed Mar 28 07:34:19 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 12:34:19 +0100
Subject: [PATCH] ARM: Samsung: Make PM_GENERIC_DOMAINS config depend on
 CONFIG_PM
In-Reply-To: <CAJuYYwQgZqN6nguddjS6bjLhx_ZhUZ5AfcrSAKBa7Ft-Bn6wPQ@mail.gmail.com>
References: <1332843404-25476-1-git-send-email-thomas.ab@samsung.com>
 <20120328105122.GF3232@opensource.wolfsonmicro.com>
 <CAJuYYwQgZqN6nguddjS6bjLhx_ZhUZ5AfcrSAKBa7Ft-Bn6wPQ@mail.gmail.com>
Message-ID: <20120328113419.GM3232@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 04:51:32PM +0530, Thomas Abraham wrote:
> On 28 March 2012 16:21, Mark Brown <broonie at opensource.wolfsonmicro.com> wrote:

> > What's the underlying issue here? ?This seems like something the PM core
> > should be dealing with gracefully...

> The PM_GENERIC_DOMAINS config option has dependency on CONFIG_PM
> option. When building with PM disabled, the following errors occur.

Right, this does seem like something which it'd be better to handle
more gracefully in the PM core.
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From thomas.abraham at linaro.org  Wed Mar 28 07:37:03 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Wed, 28 Mar 2012 17:07:03 +0530
Subject: [PATCH] ARM: Samsung: Make PM_GENERIC_DOMAINS config depend on
 CONFIG_PM
In-Reply-To: <20120328113419.GM3232@opensource.wolfsonmicro.com>
References: <1332843404-25476-1-git-send-email-thomas.ab@samsung.com>
 <20120328105122.GF3232@opensource.wolfsonmicro.com>
 <CAJuYYwQgZqN6nguddjS6bjLhx_ZhUZ5AfcrSAKBa7Ft-Bn6wPQ@mail.gmail.com>
 <20120328113419.GM3232@opensource.wolfsonmicro.com>
Message-ID: <CAJuYYwRR6eo8LruyOtyi3Sp96jydRvPFhMnbF6wfk55eM-zjbw@mail.gmail.com>

On 28 March 2012 17:04, Mark Brown <broonie at opensource.wolfsonmicro.com> wrote:
> On Wed, Mar 28, 2012 at 04:51:32PM +0530, Thomas Abraham wrote:
>> On 28 March 2012 16:21, Mark Brown <broonie at opensource.wolfsonmicro.com> wrote:
>
>> > What's the underlying issue here? ?This seems like something the PM core
>> > should be dealing with gracefully...
>
>> The PM_GENERIC_DOMAINS config option has dependency on CONFIG_PM
>> option. When building with PM disabled, the following errors occur.
>
> Right, this does seem like something which it'd be better to handle
> more gracefully in the PM core.

Ok. Selecting PM_GENERIC_DOMAINS without checking for dependency on PM
did not seem correct.


From broonie at opensource.wolfsonmicro.com  Wed Mar 28 07:42:08 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 12:42:08 +0100
Subject: [PATCH] ARM: Samsung: Make PM_GENERIC_DOMAINS config depend on
 CONFIG_PM
In-Reply-To: <CAJuYYwRR6eo8LruyOtyi3Sp96jydRvPFhMnbF6wfk55eM-zjbw@mail.gmail.com>
References: <1332843404-25476-1-git-send-email-thomas.ab@samsung.com>
 <20120328105122.GF3232@opensource.wolfsonmicro.com>
 <CAJuYYwQgZqN6nguddjS6bjLhx_ZhUZ5AfcrSAKBa7Ft-Bn6wPQ@mail.gmail.com>
 <20120328113419.GM3232@opensource.wolfsonmicro.com>
 <CAJuYYwRR6eo8LruyOtyi3Sp96jydRvPFhMnbF6wfk55eM-zjbw@mail.gmail.com>
Message-ID: <20120328114208.GP3232@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 05:07:03PM +0530, Thomas Abraham wrote:
> On 28 March 2012 17:04, Mark Brown <broonie at opensource.wolfsonmicro.com> wrote:

> > Right, this does seem like something which it'd be better to handle
> > more gracefully in the PM core.

> Ok. Selecting PM_GENERIC_DOMAINS without checking for dependency on PM
> did not seem correct.

I dunno, perhaps the PM guys will disagree but it seems like if the
idiomatic way to use this is to select it the API ought to cope with
being selected when half enabled.

As I've said before I'm in favour of just making CONFIG_PM non-optional,
I'm not convinced there's much meaningful use case for disabling it.
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From nicolas.ferre at atmel.com  Wed Mar 28 07:44:37 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 28 Mar 2012 13:44:37 +0200
Subject: [PATCH v2 1/3] mmc: atmel-mci: correct data timeout computation
In-Reply-To: <1332930513-14893-1-git-send-email-ludovic.desroches@atmel.com>
References: <1332344483-3915-2-git-send-email-ludovic.desroches@atmel.com>
 <1332930513-14893-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <4F72F9A5.60900@atmel.com>

On 03/28/2012 12:28 PM, ludovic.desroches at atmel.com :
> From: Ludovic Desroches <ludovic.desroches at atmel.com>
> 
> The HSMCI operates at a rate of up to Master Clock divided by two.
> Moreover previous calculation can cause overflows and so wrong
> timeouts.
> 
> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>

Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

> Cc: stable <stable at vger.kernel.org>
> ---
>  drivers/mmc/host/atmel-mci.c |    9 ++++++++-
>  1 files changed, 8 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
> index e4449a5..3a57964 100644
> --- a/drivers/mmc/host/atmel-mci.c
> +++ b/drivers/mmc/host/atmel-mci.c
> @@ -480,7 +480,14 @@ err:
>  static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
>  					unsigned int ns)
>  {
> -	return (ns * (host->bus_hz / 1000000) + 999) / 1000;
> +	/*
> +	 * It is easier here to use us instead of ns for the timeout,
> +	 * it prevents from overflows during calculation.
> +	 */
> +	unsigned int us = DIV_ROUND_UP(ns, 1000);
> +
> +	/* Maximum clock frequency is host->bus_hz/2 */
> +	return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
>  }
>  
>  static void atmci_set_timeout(struct atmel_mci *host,


-- 
Nicolas Ferre


From alexg at meprolight.com  Wed Mar 28 07:52:07 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Wed, 28 Mar 2012 13:52:07 +0200
Subject: [PATCH v2] regulator: i.MX35-PDK Add regulator support
Message-ID: <1332935527-21414-1-git-send-email-alexg@meprolight.com>

This version rebased for v3.4, also removes ranges from regulators
who do not have consumers and adds consumers for same regulators.

Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
---
 arch/arm/mach-imx/mach-mx35_3ds.c |  193 +++++++++++++++++++++++++++++++++++++
 1 files changed, 193 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index e14291d..aad7fb9 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -34,6 +34,8 @@
 #include <linux/usb/otg.h>
 
 #include <linux/mtd/physmap.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -253,6 +255,8 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
 	MX35_PAD_CSI_MCLK__IPU_CSI_MCLK,
 	MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK,
 	MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC,
+	/*PMIC IRQ*/
+	MX35_PAD_GPIO2_0__GPIO2_0,
 };
 
 /*
@@ -317,6 +321,193 @@ static struct platform_device mx35_3ds_ov2640 = {
 	},
 };
 
+static struct regulator_consumer_supply sw1_consumers[] = {
+	{
+		.supply = "cpu_vcc",
+	}
+};
+
+static struct regulator_consumer_supply vcam_consumers[] = {
+	/* sgtl5000 */
+	REGULATOR_SUPPLY("VDDA", "1-000a"),
+};
+
+static struct regulator_consumer_supply vaudio_consumers[] = {
+	REGULATOR_SUPPLY("cmos_vio", "soc-camera-pdrv.0"),
+};
+
+static struct regulator_init_data sw1_init = {
+	.constraints = {
+		.name = "SW1",
+		.min_uV = 600000,
+		.max_uV = 1375000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.valid_modes_mask = 0,
+		.always_on = 1,
+		.boot_on = 1,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+	.consumer_supplies = sw1_consumers,
+};
+
+static struct regulator_init_data sw2_init = {
+	.constraints = {
+		.name = "SW2",
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data sw3_init = {
+	.constraints = {
+		.name = "SW3",
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data sw4_init = {
+	.constraints = {
+		.name = "SW4",
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data viohi_init = {
+	.constraints = {
+		.name = "VIOHI",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vusb_init = {
+	.constraints = {
+		.name = "VUSB",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vdig_init = {
+	.constraints = {
+		.name = "VDIG",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vpll_init = {
+	.constraints = {
+		.name = "VPLL",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vusb2_init = {
+	.constraints = {
+		.name = "VUSB2",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vvideo_init = {
+	.constraints = {
+		.name = "VVIDEO",
+		.boot_on = 1
+	}
+};
+
+static struct regulator_init_data vaudio_init = {
+	.constraints = {
+		.name = "VAUDIO",
+		.min_uV = 2300000,
+		.max_uV = 3000000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1
+	},
+	.num_consumer_supplies = ARRAY_SIZE(vaudio_consumers),
+	.consumer_supplies = vaudio_consumers,
+};
+
+static struct regulator_init_data vcam_init = {
+	.constraints = {
+		.name = "VCAM",
+		.min_uV = 2500000,
+		.max_uV = 3000000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+					REGULATOR_CHANGE_MODE,
+		.valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
+		.boot_on = 1
+	},
+	.num_consumer_supplies = ARRAY_SIZE(vcam_consumers),
+	.consumer_supplies = vcam_consumers,
+};
+
+static struct regulator_init_data vgen1_init = {
+	.constraints = {
+		.name = "VGEN1",
+	}
+};
+
+static struct regulator_init_data vgen2_init = {
+	.constraints = {
+		.name = "VGEN2",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vgen3_init = {
+	.constraints = {
+		.name = "VGEN3",
+	}
+};
+
+static struct mc13xxx_regulator_init_data mx35_3ds_regulators[] = {
+	{ .id = MC13892_SW1, .init_data = &sw1_init },
+	{ .id = MC13892_SW2, .init_data = &sw2_init },
+	{ .id = MC13892_SW3, .init_data = &sw3_init },
+	{ .id = MC13892_SW4, .init_data = &sw4_init },
+	{ .id = MC13892_VIOHI, .init_data = &viohi_init },
+	{ .id = MC13892_VPLL, .init_data = &vpll_init },
+	{ .id = MC13892_VDIG, .init_data = &vdig_init },
+	{ .id = MC13892_VUSB2, .init_data = &vusb2_init },
+	{ .id = MC13892_VVIDEO, .init_data = &vvideo_init },
+	{ .id = MC13892_VAUDIO, .init_data = &vaudio_init },
+	{ .id = MC13892_VCAM, .init_data = &vcam_init },
+	{ .id = MC13892_VGEN1, .init_data = &vgen1_init },
+	{ .id = MC13892_VGEN2, .init_data = &vgen2_init },
+	{ .id = MC13892_VGEN3, .init_data = &vgen3_init },
+	{ .id = MC13892_VUSB, .init_data = &vusb_init },
+};
+
+static struct mc13xxx_platform_data mx35_3ds_mc13892_data = {
+	.flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
+	.regulators = {
+		.num_regulators = ARRAY_SIZE(mx35_3ds_regulators),
+		.regulators = mx35_3ds_regulators,
+	},
+};
+
+#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
+
+static struct i2c_board_info mx35_3ds_i2c_mc13892 = {
+
+	I2C_BOARD_INFO("mc13892", 0x08),
+	.platform_data = &mx35_3ds_mc13892_data,
+	.irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
+};
+
+static void __init imx35_3ds_init_mc13892(void)
+{
+	int ret = gpio_request_one(GPIO_PMIC_INT, GPIOF_DIR_IN, "pmic irq");
+
+	if (ret) {
+		pr_err("failed to get pmic irq: %d\n", ret);
+		return;
+	}
+
+	i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1);
+}
+
 static int mx35_3ds_otg_init(struct platform_device *pdev)
 {
 	return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
@@ -412,6 +603,8 @@ static void __init mx35_3ds_init(void)
 	imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 	mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
 	platform_device_register(&mx35_3ds_lcd);
+
+	imx35_3ds_init_mc13892();
 }
 
 static void __init mx35pdk_timer_init(void)
-- 
1.7.0.4



From festevam at gmail.com  Wed Mar 28 08:12:31 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 28 Mar 2012 09:12:31 -0300
Subject: [PATCH v2] regulator: i.MX35-PDK Add regulator support
In-Reply-To: <1332935527-21414-1-git-send-email-alexg@meprolight.com>
References: <1332935527-21414-1-git-send-email-alexg@meprolight.com>
Message-ID: <CAOMZO5DE0wcdbk7xbXuOFKJ=NNtSrWTPaLjRAdDfewOmPR-eVw@mail.gmail.com>

On Wed, Mar 28, 2012 at 8:52 AM, Alex Gershgorin <alexg at meprolight.com> wrote:
> This version rebased for v3.4, also removes ranges from regulators
> who do not have consumers and adds consumers for same regulators.

In your subject: prefix it with "ARM" as this patch should go via the arm tree.

Also, do not put comments about kernel version in the commit log.
If you want to talk about kernel version/patch history you can do so
below the --- line.

...
> +static struct regulator_consumer_supply vcam_consumers[] = {
> + ? ? ? /* sgtl5000 */
> + ? ? ? REGULATOR_SUPPLY("VDDA", "1-000a"),

This should be "0-000a" instead.


From alexg at meprolight.com  Wed Mar 28 08:20:27 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Wed, 28 Mar 2012 14:20:27 +0200
Subject: [PATCH v2] regulator: i.MX35-PDK Add regulator support
In-Reply-To: <CAOMZO5DE0wcdbk7xbXuOFKJ=NNtSrWTPaLjRAdDfewOmPR-eVw@mail.gmail.com>
References: <1332935527-21414-1-git-send-email-alexg@meprolight.com>,
 <CAOMZO5DE0wcdbk7xbXuOFKJ=NNtSrWTPaLjRAdDfewOmPR-eVw@mail.gmail.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD22@MEP-EXCH.meprolight.com>

Hi Fabio,

Thanks for you comments,

On Wed, Mar 28, 2012 at 8:52 AM, Alex Gershgorin <alexg at meprolight.com> wrote:
> This version rebased for v3.4, also removes ranges from regulators
> who do not have consumers and adds consumers for same regulators.

> > In your subject: prefix it with "ARM" as this patch should go via the arm tree.

> > Also, do not put comments about kernel version in the commit log.
> > If you want to talk about kernel version/patch history you can do so
> > below the --- line.

I will take note of this 
...
> +static struct regulator_consumer_supply vcam_consumers[] = {
> +       /* sgtl5000 */
> +       REGULATOR_SUPPLY("VDDA", "1-000a"),

> > This should be "0-000a" instead.

oops... I will correct this 




From arnd at arndb.de  Wed Mar 28 08:27:31 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 28 Mar 2012 12:27:31 +0000
Subject: [PATCH V2 5/7] ARM: SPEAr3xx: Add device-tree support to SPEAr3xx
 architecture
In-Reply-To: <f4ad79023c6155d4de7e87c3cd798aadd493454e.1332926608.git.viresh.kumar@st.com>
References: <cover.1332926608.git.viresh.kumar@st.com>
 <f4ad79023c6155d4de7e87c3cd798aadd493454e.1332926608.git.viresh.kumar@st.com>
Message-ID: <201203281227.32299.arnd@arndb.de>

On Wednesday 28 March 2012, Viresh Kumar wrote:
> This patch adds a generic target for SPEAr3xx machines that can be configured
> via the device-tree. Currently the following devices are supported via the
> devicetree:
> 
> - VIC interrupts
> - PL011 UART
> - PL061 GPIO
> - PL110 CLCD
> - SP805 WDT
> - Synopsys DW I2C
> - Synopsys DW ethernet
> - ST FSMC-NAND
> - ST SPEAR-SMI
> - ST SPEAR-KEYBOARD
> - ST SPEAR-RTC
> - ARASAN SDHCI-SPEAR
> - SPEAR-EHCI
> - SPEAR-OHCI
> 
> Other peripheral devices will follow in later patches.

Hi Viresh,

I found a few small issues here, nothing serious:

> @@ -192,9 +192,9 @@ machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
>  machine-$(CONFIG_ARCH_VT8500)		:= vt8500
>  machine-$(CONFIG_ARCH_W90X900)		:= w90x900
>  machine-$(CONFIG_FOOTBRIDGE)		:= footbridge
> -machine-$(CONFIG_MACH_SPEAR300)		:= spear3xx
> -machine-$(CONFIG_MACH_SPEAR310)		:= spear3xx
> -machine-$(CONFIG_MACH_SPEAR320)		:= spear3xx
> +machine-$(CONFIG_MACH_SPEAR300_DT)	:= spear3xx
> +machine-$(CONFIG_MACH_SPEAR310_DT)	:= spear3xx
> +machine-$(CONFIG_MACH_SPEAR320_DT)	:= spear3xx
>  machine-$(CONFIG_MACH_SPEAR600)		:= spear6xx
>  machine-$(CONFIG_ARCH_ZYNQ)		:= zynq

Since you're actually removing the non-DT support, I don't see a point in
renaming the config symbols. Your patch should become quite a bit smaller
if you leave them the way they are now.

> +/ {
> +	ahb {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		ranges = <0x60000000 0x60000000 0x50000000
> +			  0xd0000000 0xd0000000 0x30000000>;
> +
> +		clcd at 60000000 {
> +			compatible = "arm,clcd-pl110", "arm,primecell";
> +			reg = <0x60000000 0x1000>;
> +			interrupt-parent = <&vic>;
> +			interrupts = <30>;
> +			status = "disabled";
> +		};

You can move the interrupt-parent property that points to vic into the
root node to define vic as the default parent so you don't have to
list it individually in all the nodes using it.

> +
> +			serial at d0000000 {
> +			       status = "okay";
> +			};
> +
> +			serial at b2000000 {
> +			       status = "okay";
> +			};
> +
> +			serial at b2080000 {
> +			       status = "okay";
> +			};
> +
> +			serial at b2100000 {
> +			       status = "okay";
> +			};
> +
> +			serial at b2180000 {
> +			       status = "okay";
> +			};
> +
> +			serial at b2200000 {
> +			       status = "okay";
> +			};

Does spear310-evb really connect all seven serial ports?

> +/* Add SPEAr300 auxdata to pass platform data */
> +static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
> +	SPEAR3XX_AUXDATA_LOOKUP,
> +	{}
> +};

I don't really like the use of macros in this way. Better copy the
contents here, especially if you don't expect to add more stuff to
that macro.

> -/* spear300 routine
> +	if (of_machine_is_compatible("st,spear300-evb")) {
> +		/* pmx initialization */
> +		pmx_driver.mode = &spear300_photo_frame_mode;
> +		pmx_driver.devs = spear300_evb_pmx_devs;
> +		pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
> +	} else {
> +		pr_err("Invalid board\n");
> +		return;
> +	}

I would not report the board as invalid if it doesn't match your list.
Just keep going here in the hope that the board does work with its
device tree contents.

> +
> +/* Following will create static virtual/physical mappings */
> +struct map_desc spear3xx_io_desc[] __initdata = {
> +	{
> +		.virtual	= VA_SPEAR3XX_ICM1_UART_BASE,
> +		.pfn		= __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE
> +	}, {
> +		.virtual	= VA_SPEAR3XX_ML1_VIC_BASE,
> +		.pfn		= __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE
> +	}, {
> +		.virtual	= VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
> +		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE
> +	}, {
> +		.virtual	= VA_SPEAR3XX_ICM3_MISC_REG_BASE,
> +		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
> +		.length		= SZ_4K,
> +		.type		= MT_DEVICE
> +	},
> +};

Note: there no real reason to just map 4K pages here, or to compute the
virtual addresses using the IO_ADDRESS macro. Using larger mappings mean
you have more efficient TLB lookup for any I/O windows that are located
closely together.

I would actually write this something like
struct map_desc spear3xx_io_desc[] __initdata = {
	{
		.virtual = 0xf0000000,
		.pfn	 = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
		.length	 = SZ_16M,
		.type	 = MT_DEVICE,
	}, {
		.virtual = 0xf1000000,
		.pfn	 = __phys_to_pfn(SPEAR3XX_ICM4_BASE),
		.length  = 3 * SZ_16M,
		.type	 = MT_DEVICE,
	}, {
		.virtual = 0xf4000000,
		.pfn	 = __phys_to_pfn(SPEAR3XX_ICM3_ML1_2_BASE),
		.length  = 2 * SZ_16M,
		.type	 = MT_DEVICE,
	}, {
		.virtual = 0xf6000000,
		.pfn	 = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
		.length  = SZ_16M,
		.type	 = MT_DEVICE,
	},
};

This would cover almost all of your devices with just seven TLB entries,
and ioremap can now find the right virtual addresses automatically.

	Arnd



From arnd at arndb.de  Wed Mar 28 08:34:10 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 28 Mar 2012 12:34:10 +0000
Subject: [GIT PULL 1/5] ARM: cleanups of io includes
In-Reply-To: <CAOesGMjwZOON9kFNvaEq8QhSvjAgsJT_J1Ysb9-AbePd6g+-rQ@mail.gmail.com>
References: <1332918842-13521-1-git-send-email-olof@lixom.net>
 <20120328082501.GA22414@n2100.arm.linux.org.uk>
 <CAOesGMjwZOON9kFNvaEq8QhSvjAgsJT_J1Ysb9-AbePd6g+-rQ@mail.gmail.com>
Message-ID: <201203281234.10632.arnd@arndb.de>

On Wednesday 28 March 2012, Olof Johansson wrote:
> If you prefer to let it sit in linux-next for a day or two before
> going in, that's fine. But I verified that the original build problem
> introduced was fixed before I sent it out.
> 
> Unfortunately, PXA is also broken due to the regulator changes
> mentioned in the above referenced mail, which is already upstream and
> unrelated to the changes in this branch.
> 
> Linus; the rest of the pull requests should be OK to go in
> independently of this, so please go ahead with those if you don't
> mind. The only changes to those branches in the last few days is the
> merge resolution I did to the drivers2 branch/tag.

Yes, sounds good. I've also verified that none of the other branches
depends on this one.

	Arnd


From shawn.guo at linaro.org  Wed Mar 28 09:22:29 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 28 Mar 2012 21:22:29 +0800
Subject: [PATCH v2 1/1] ARM: imx28: add basic dt support
In-Reply-To: <20120328095346.GA31901@shlinux2.ap.freescale.net>
References: <1332513070-5400-1-git-send-email-b29396@freescale.com>
 <20120328055801.GA3953@S2100-06.ap.freescale.net>
 <20120328095346.GA31901@shlinux2.ap.freescale.net>
Message-ID: <20120328132227.GA3254@S2101-09.ap.freescale.net>

On Wed, Mar 28, 2012 at 05:53:47PM +0800, Dong Aisheng wrote:
> On Wed, Mar 28, 2012 at 01:58:04PM +0800, Guo Shawn-R65073 wrote:
> > On Fri, Mar 23, 2012 at 10:31:10PM +0800, Dong Aisheng wrote:
> > > From: Dong Aisheng <dong.aisheng at linaro.org>
...
> > > +static const char *imx28_dt_compat[] __initdata = {
> > 
> > mxs_dt_compat
> > 
> If changed like that, is it reasonable for mx23 to use this
> compatible string list?
> I planed to have separate compatible string for mx23 and mx28.

Ok, I'm fine with that, since we will have separate DT_MACHINE_START
for imx23 and imx28.

> 
> > > +	"fsl,imx28",
> > > +	"fsl,imx28-evk",
> > 
> > I would have the list sorted from the most specific to the most
> > general.  That said, it's better to have "fsl,imx28" sorted after
> > "fsl,imx28-evk".
> > 
> I prefer to keep the basic one first, then for future boards support
> we just add them below rather than insert above the basic one "fsl,imx28".
> However, it's really not a big deal.
> If you persist to do like that, i can also do it.
> 
Yes, please.  Listing items from the most specific to the general is
the rule for compatible property and match table.

-- 
Regards,
Shawn


From haojian.zhuang at gmail.com  Wed Mar 28 09:36:05 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 28 Mar 2012 21:36:05 +0800
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <20120328101852.GE3232@opensource.wolfsonmicro.com>
References: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
 <1331242494-3157-1-git-send-email-paul.gortmaker@windriver.com>
 <CAN1soZzDRR4XQ34WDL48=j+Ff8t5fsCFaccqZAKOQ1OAPeDXcA@mail.gmail.com>
 <4F608F4F.8020106@windriver.com>
 <20120314123236.GE3133@opensource.wolfsonmicro.com>
 <20120328094351.GB22414@n2100.arm.linux.org.uk>
 <20120328101852.GE3232@opensource.wolfsonmicro.com>
Message-ID: <CAN1soZzypFA_EsmF5AHzjwHNom2-nY2io=6R8qPyBbn5m3aa0Q@mail.gmail.com>

On Wed, Mar 28, 2012 at 6:18 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Wed, Mar 28, 2012 at 10:43:51AM +0100, Russell King - ARM Linux wrote:
>> On Wed, Mar 14, 2012 at 12:32:36PM +0000, Mark Brown wrote:
>
>> > Yes, that's what you should do. ?Calling dev_name() is only possible if
>> > you have the struct device and removing the need for the struct device
>> > is exactly what we're trying to avoid here.
>
>> So what the hell is happening here to fix the breakage which the
>> regulator tree caused in mainline? ?From this thread, it looks like
>> it's been known about since 8th March which is now twenty days ago,
>> and it's still broken.
>
> Yes, please at least apply Paul's patches - honestly, given how old
> these boards are and the general lack of activity I'd rather expect that
> the only thing anyone's doing with them these days is build tests.

Applied. I'll submit this fix to Arnd and Olof.

Best Regards
Haojian


From haojian.zhuang at gmail.com  Wed Mar 28 09:51:16 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 28 Mar 2012 21:51:16 +0800
Subject: [GIT PULL] pull request from arch-pxa git on fixes branch
Message-ID: <CAN1soZytJ-CxepQAZn5oZ06=ezTQ85O-iC7tUDOeWqi=zpuf8A@mail.gmail.com>

Hi Arnd & Olof,

Please help to pull fixes branch in arch-pxa git. This fix can resolve
build issues on updating regulator interface.

The following changes since commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7:

  Linux 3.3 (2012-03-18 16:15:34 -0700)

are available in the git repository at:
  git://github.com/hzhuang1/linux.git fixes

Paul Gortmaker (1):
      ARM: pxa: fix regulator related build fail in magician_defconfig

 arch/arm/mach-pxa/hx4700.c   |    2 --
 arch/arm/mach-pxa/magician.c |    2 --
 2 files changed, 0 insertions(+), 4 deletions(-)


From joancarles at fqingenieria.es  Wed Mar 28 10:01:46 2012
From: joancarles at fqingenieria.es (joancarles)
Date: Wed, 28 Mar 2012 16:01:46 +0200
Subject: [MX25][MMC] mmc esdhc failure in 3.3
In-Reply-To: <c4306c7d39eac8f1751957eefe20a6c2@mail.fqingenieria.es>
References: <5e57eb999780335721212bb8d411406f@mail.fqingenieria.es>
 <20120312132423.GC2459@pengutronix.de>
 <9018463dfcd3c9e9a311aeed42b758bf@mail.fqingenieria.es>
 <0E83723C55F66F43A6041464FE31119D099A34@039-SN2MPN1-011.039d.mgd.msft.net>
 <a06e68c3687c7390e15950bc20831fd4@mail.fqingenieria.es>
 <85b807b77d73328485781d6fa1568e46@mail.fqingenieria.es>
 <20120327101259.73525f9d@eb-e6520>
 <ac05d6e5c1ce4bf9cfc5c28d235f866f@mail.fqingenieria.es>
 <20120327090148.GB6790@pengutronix.de> <20120327110615.3bfaf969@eb-e6520>
 <7f2ae9e3800848e140461a0506808fb4@mail.fqingenieria.es>
 <20120327114048.6af2e178@eb-e6520>
 <137e8b8e079af62aea2fd4d363be6273@mail.fqingenieria.es>
 <c4306c7d39eac8f1751957eefe20a6c2@mail.fqingenieria.es>
Message-ID: <cb665484c55065958358acb4fd91bbdb@mail.fqingenieria.es>

> Anybody with more insights? Why is the interval between two CMD24
> more or less in the range of 6ms and the CMD13 follows in varying
> intervals between 1ms to 4ms? What's keeping the driver from bursting
> CMD24 and successive CMD13 requests?

A 4*128KB dd run shows the following patterns of latency between 
various CMDs issued:

http://i43.tinypic.com/2bcmsw.png

The latency distribution is plotted here:

http://i41.tinypic.com/9gvbqo.png

bin limits	freq count	pct
<0ms	0	0.0%
<1ms	922	43.6%
<6ms	491	23.2%
<10ms	411	19.4%
<20ms	113	5.3%
<100ms	163	7.7%
<300ms	9	0.4%
<1000ms	7	0.3%

It took 25 seconds to write 4*128KB to the SD-card using the current 
drivers. More than 50% of the CMD requests issued take more than 1ms 
from issuing to response between the host and the card. Anybody else 
with this issue on the i.MX25? How can I pinpoint this down to the 
culprits in the kernel source?

Regards
-- 
Joan C. Abelaira


From alexg at meprolight.com  Wed Mar 28 10:01:13 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Wed, 28 Mar 2012 16:01:13 +0200
Subject: [PATCH] mfd: mc13xxx: add I2C support fix building for v3.4
Message-ID: <1332943273-22447-1-git-send-email-alexg@meprolight.com>

This patch fixes the compilation errors after the patches
from series mc13xxx-add-I2C-support-V4 were applied.

Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
---
 drivers/mfd/Kconfig        |    2 ++
 drivers/mfd/mc13xxx-core.c |    2 +-
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c3fbc5e..2119732 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -577,6 +577,8 @@ config MFD_MC13XXX
 	depends on SPI_MASTER || I2C
 	select MFD_CORE
 	select MFD_MC13783
+	select REGMAP_I2C if I2C
+	select REGMAP_SPI if SPI_MASTER
 	help
 	  Enable support for the Freescale MC13783 and MC13892 PMICs.
 	  This driver provides common support for accessing the device,
diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
index 31dbf91..5a60273 100644
--- a/drivers/mfd/mc13xxx-core.c
+++ b/drivers/mfd/mc13xxx-core.c
@@ -616,7 +616,7 @@ static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
 #ifdef CONFIG_OF
 static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
 {
-	struct device_node *np = mc13xxx->dev.of_node;
+	struct device_node *np = mc13xxx->dev->of_node;
 
 	if (!np)
 		return -ENODEV;
-- 
1.7.0.4



From hvaibhav at ti.com  Wed Mar 28 10:16:13 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 28 Mar 2012 14:16:13 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>

On Wed, Mar 21, 2012 at 19:30:01, Shilimkar, Santosh wrote:
> On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> > On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
> >> On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
> >> > On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >> >>
> >> >> I think you made very good point here. With the above patch, we are almost missing the capability of registering dmtimer as a clocksource for OMAP.
> >> >> It will always use 32k-counter, and never fall back to dmtimer.
> >> >>
> >> >> Then the only options we have here is,
> >> >>
> >> >> 1) Register both the timers, 32k-counter and dmtimer for clocksource; let
> >> >> ? Kernel pick up best rating clocksource out of these two.
> >> >>
> >> >> ? In case of OMAP1/2/3/4, kernel will use dmtimer, since it has better
> >> >> ? Rating. User can choose the 32k-counter clocksource via bootargs.
> >> >>
> >> >> ? Impact: without bootargs for clocksource selection, kernel will choose
> >> >> ? ? dmtimer, impacting loss of time during suspend/resume.
> >> >>
> >> This is the right option. The problem is gptimer clocksource
> >> doesn't work across power transitions and hence it is broken.
> >>
> >> Even for the perf, with PM enabled, dmtimer can't be used or it needs
> >> to be used with 32KHz clock which makes it no better than sync timer.
> >>
> >> So here keeping 32K sync timer is default clocksource makes sense since
> >> it is the only working and viable option.
> >>
> >> So what can be done is register both 32K and gptimer together but make
> >> gptimer clocksource registration depends on PM enabled.
> >>
> >> This should solve all the needs I guess.
> >>
> >
> > I am not sure this will work on all platforms, for example, AM33XX, where
> > We do not have 32ksync timer available, but we need PM support. Also, I
> > personally think, we should not again use compile time option here.
> >
> Why not ?
> If 32ksync timer is not available, don't register it. Then in AM case
> you just have one clock-source. 

In case of AM33xx, what about kernel without PM support?
As clocksource registration would be dependent on PM option, it won't work.

> I am against the idea of making
> gptimer as the default and asking user to choose sync32k from
> command-line.
> 

I understand your concern here.


> Btw, if you need PM, how are you going to use GPTIMER
> as a clocksource. Note sys-clock is generally stopped in
> low power states. So that leaves you option with using
> gptimer with 32K clock and in that case, GPTIMER
> is not a better clock-source compare to 32K sync timer
> and so shouldn't be the rating.
> 

AM33xx has GPTIMER1 in wakeup domain, so that we are already using as a
Clocksource, without any issues.

Thanks,
Vaibhav

> Regards
> Santosh
> 



From nico at fluxnic.net  Wed Mar 28 10:17:29 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 28 Mar 2012 10:17:29 -0400 (EDT)
Subject: [PATCH] ARM: test for PMU feature on v7 (v2 with typo fix)
In-Reply-To: <20120326094054.GA2475@mudshark.cambridge.arm.com>
References: <4F590411.9060201@arm.com> <87ty1g88dv.fsf@rustcorp.com.au>
 <87r4wk889a.fsf@rustcorp.com.au>
 <20120323095314.GA13622@mudshark.cambridge.arm.com>
 <87fwcy9abw.fsf@rustcorp.com.au>
 <20120326094054.GA2475@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1203281005110.24151@xanadu.home>

On Mon, 26 Mar 2012, Will Deacon wrote:

> Now, if everything was device-tree based then we could simply use a
> different binding for each CPU but since we support perf on non-DT
> platforms, probing the CPU type is the best solution. I would like to avoid
> the probing code if we are initialised from DT, but I've not got round to it
> yet (this would be useful for big.LITTLE).

Still... my opinion is that we should try to autodetect as much as 
possible and avoid overstuffing the DT with content that can otherwise 
be run-time probed.  OK to use DT to override the probe for corner 
cases, but IMHO the probe should be the default method of 
initialization.  The rational is that we want to spread knowledge about 
part of the system and have it confined into respective drivers and 
subsystems for easier maintenance.  If the guy who has to maintain the 
dts has to know all the details for everything then that won't scale and 
the risk for discrepancies is increased.


Nicolas


From shawn.guo at linaro.org  Wed Mar 28 10:18:14 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 28 Mar 2012 22:18:14 +0800
Subject: [alsa-devel] [PATCH] ASoC: sgtl5000: fix power on/off of MIC bias
In-Reply-To: <7FE21149F4667147B645348EC605788514EDFF@039-SN2MPN1-011.039d.mgd.msft.net>
References: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
 <7FE21149F4667147B645348EC605788514EDFF@039-SN2MPN1-011.039d.mgd.msft.net>
Message-ID: <20120328141812.GB3254@S2101-09.ap.freescale.net>

On Wed, Mar 28, 2012 at 09:52:15AM +0000, Dong Aisheng-B29396 wrote:
> Did you test line-in record?

No, I did not.  I'm playing imx51 babbage board which has no LINE-IN
routed.

> IIRC for line-in record, it may also need VAG_POWER up.
> Then only enable VAG_POWER for mic_bias_event may not be sufficient.
> Will verify it latter when I'm free.
> 
This patch only fixes MIC.  I think you can submit another patch after
you confirm LINE-IN has the same issue.

-- 
Regards,
Shawn


From santosh.shilimkar at ti.com  Wed Mar 28 10:20:02 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 28 Mar 2012 19:50:02 +0530
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
Message-ID: <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>

On Wed, Mar 28, 2012 at 7:46 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> On Wed, Mar 21, 2012 at 19:30:01, Shilimkar, Santosh wrote:
>> On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>> > On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
>> >> On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
>> >> > On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:

[...]

>
>> Btw, if you need PM, how are you going to use GPTIMER
>> as a clocksource. Note sys-clock is generally stopped in
>> low power states. So that leaves you option with using
>> gptimer with 32K clock and in that case, GPTIMER
>> is not a better clock-source compare to 32K sync timer
>> and so shouldn't be the rating.
>>
>
> AM33xx has GPTIMER1 in wakeup domain, so that we are already using as a
> Clocksource, without any issues.
>
GPTIMER1 is in wakeup domain on OMAP too but that doesn't
solve the issue I am talking. Once the sysclock is stopped, GPTIMER
can't tick anymore even if it is in wakeup domain.

The only way it will work is using always running 32KHz clock as
the clock input to GPT1. And then the end result is the accuracy
of GPTIMER = sync 32K timer. So they are of same rating.

Hope it is clear now.

Regards
Santosh


From robherring2 at gmail.com  Wed Mar 28 10:26:50 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Wed, 28 Mar 2012 09:26:50 -0500
Subject: [GIT PULL 0/5] Second batch of arm-soc changes
In-Reply-To: <1332918842-13521-1-git-send-email-olof@lixom.net>
References: <1332918842-13521-1-git-send-email-olof@lixom.net>
Message-ID: <4F731FAA.5040708@gmail.com>

On 03/28/2012 02:13 AM, Olof Johansson wrote:
> Hi Linus,
> 
> Here is the second batch of arm-soc changes for this merge window. As Arnd
> mentioned with the first cover letter, most of these either had external
> dependencies that have now been pulled in, or just needed a bit more
> linux-next bake time due to getting picked up close to the 3.3 release.
> 
> 
> There are 128 non-merge patches, with a total diffstat of:
> 
>  346 files changed, 10790 insertions(+), 2792 deletions(-)
> 
> So, while there's been some good cleanups especially in the first branch,
> there's been a net addition of code:
> 
> * New SoC family support for Samsung EXYNOS5250: clock tables, driver
>   updates, etc means net gain in code.
> * Added device tree conversions. Once we start to sunset non-device tree
>   boards on the enabled platforms, we should see payback in code removal.
> * Common clock framework. As SoCs get converted over to the framework,
>   we should see more code removal from this as well.
> 
> 
> There are a handful of merge conflicts on the branches, nothing that
> should be too messy to sort out. I've described each conflict in the
> corresponding pull request, including how we've resolved them in our
> for-next branch.
> 

Why isn't lakml getting copied on emails 1-5? The same thing happened
with Arnd's pull request. Are they getting hung up for moderator approval?

Rob


From thierry.reding at avionic-design.de  Wed Mar 28 10:33:42 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:42 +0200
Subject: [PATCH v5 00/16] Add PWM framework and device tree support
Message-ID: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>

This patch series adds very rudimentary device-tree support for PWM
devices. With all of these patches applied (plus one board-specific
patch that is not included), I'm able to control the backlight on the
device I'm working on using the sysfs interface provided by the pwm-bl
driver and the backlight class.

This series is based on Sascha Hauer's series of patches[0] to add a
generic PWM framework. The first patch in this series is taken from
Sascha's branch, while the second patch enables each PWM chip to provide
multiple PWM devices (the Blackfin and PXA drivers have been ported to
the framework for reference). Currently a global namespace is still
provided to keep backwards-compatibility with the legacy PWM API. In
order to achieve this, the number of global PWM devices is limited to
1024. However, patch 2 introduces per-chip indexing of PWM devices in
the core and patch 4 adds an API to request a PWM device using a lookup
table registered by board setup code. They are supposed to eventually
replace pwm_request() and allow to get rid of the global namespace. The
device tree support code does not use the global namespace.

Patch 3 adds a debugfs interface.

Patch 5 adds some code to lookup a PWM chip given its device-tree
handle. This code will be used later on by the pwm-bl driver to find the
PWM device that it should be using. If the no corresponding PWM chip is
available yet, the code returns EPROBE_DEFER to have users automatically
probed again later when the PWM provider may have become available.
Device tree binding documentation is also provided.

Patch 6 was taken from the Chromium tree and is required to provide
proper clocking of the Tegra2 PWFM controller. All Chromium-specific
tags have been removed from the commit message. Some cleanup of the
clock registration for Tegra is done in patch 7 because a subsequent
patch will instantiate one PWFM controller device instead of four.

Patch 8 adds a generic PWM framework driver for the Tegra2 PWFM
controller. The code is taken from the Chromium tree with some
adjustments to integrate it with the PWM framework. Device tree based
probing of the driver is implemented in patch 9.

Patches 10 and 11 are ports of the Blackfin PWM and the PXA PWM drivers
to the PWM framework. These are only compile-tested as I do not have any
hardware to test them on.

Patches 12, 13 and 14 move the i.MX, Samsung and VT8500 drivers over to
the framework. These are originally by Sascha Hauer and were updated to
take advantage of the multiple PWM devices per chip feature.

Patch 15 implements DT-based probing in the pwm-backlight driver. Note
that this code only handles the "pwms" property (by looking up the PWM
device via the new PWM DT binding). Switching power to the backlight via
GPIOs is not supported yet. The DT binding also deviates from the
platform data in that it requires a list of brightness levels to be
specified instead of assuming a linearily spaced range from 0 to a given
maximum brightness.

Finally, patch 16 makes me the new maintainer of the PWM subsystem.

The whole series is based on the linux-next tree from 20120328. I think
I've addressed all of the concerns raised in the first four versions.

Thierry

[0]: http://git.pengutronix.de/?p=imx/linux-2.6.git;a=shortlog;h=refs/heads/pwmlib

Sascha Hauer (4):
  pwm: Add PWM framework support
  ARM i.MX: Move i.MX pwm driver to pwm framework
  ARM Samsung: Move s3c pwm driver to pwm framework
  ARM vt8500: Move vt8500 pwm driver to pwm framework

Simon Que (1):
  ARM: tegra: Fix PWM clock programming

Thierry Reding (11):
  pwm: Allow chips to support multiple PWMs
  pwm: Add debugfs interface
  pwm: Add table-based lookup for static mappings
  pwm: Add device tree support
  ARM: tegra: Provide clock for only one PWM controller
  pwm: Add NVIDIA Tegra SoC support
  pwm: tegra: Add device tree support
  pwm: Move Blackfin PWM driver to PWM framework
  pwm: Move PXA PWM driver to PWM framework
  pwm-backlight: Add rudimentary device tree support
  pwm: Take over maintainership of the PWM subsystem

 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |   18 +
 Documentation/devicetree/bindings/pwm/pwm.txt      |   53 ++
 .../bindings/video/backlight/pwm-backlight         |   30 +
 Documentation/pwm.txt                              |   76 +++
 MAINTAINERS                                        |   12 +
 arch/arm/boot/dts/tegra20.dtsi                     |    6 +
 arch/arm/boot/dts/tegra30.dtsi                     |    6 +
 arch/arm/mach-tegra/board-dt-tegra20.c             |    1 +
 arch/arm/mach-tegra/board-dt-tegra30.c             |    3 +
 arch/arm/mach-tegra/tegra2_clocks.c                |   36 +-
 arch/arm/mach-tegra/tegra30_clocks.c               |    6 +-
 arch/arm/mach-vt8500/Makefile                      |    2 -
 arch/arm/plat-mxc/Kconfig                          |    6 -
 arch/arm/plat-mxc/Makefile                         |    1 -
 arch/arm/plat-pxa/Makefile                         |    1 -
 arch/arm/plat-samsung/Makefile                     |    4 -
 arch/blackfin/Kconfig                              |   10 -
 arch/blackfin/kernel/Makefile                      |    1 -
 arch/blackfin/kernel/pwm.c                         |  100 ---
 drivers/Kconfig                                    |    2 +
 drivers/Makefile                                   |    1 +
 drivers/pwm/Kconfig                                |   67 ++
 drivers/pwm/Makefile                               |    7 +
 drivers/pwm/core.c                                 |  679 ++++++++++++++++++++
 drivers/pwm/pwm-bfin.c                             |  164 +++++
 arch/arm/plat-mxc/pwm.c => drivers/pwm/pwm-imx.c   |  182 ++----
 arch/arm/plat-pxa/pwm.c => drivers/pwm/pwm-pxa.c   |  172 ++---
 .../pwm.c => drivers/pwm/pwm-samsung.c             |  228 +++----
 drivers/pwm/pwm-tegra.c                            |  265 ++++++++
 .../mach-vt8500/pwm.c => drivers/pwm/pwm-vt8500.c  |  169 ++---
 drivers/video/backlight/Kconfig                    |    2 +-
 drivers/video/backlight/pwm_bl.c                   |  145 ++++-
 include/linux/of_pwm.h                             |   34 +
 include/linux/pwm.h                                |  115 ++++
 include/linux/pwm_backlight.h                      |    1 +
 35 files changed, 1967 insertions(+), 638 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
 create mode 100644 Documentation/devicetree/bindings/pwm/pwm.txt
 create mode 100644 Documentation/devicetree/bindings/video/backlight/pwm-backlight
 create mode 100644 Documentation/pwm.txt
 delete mode 100644 arch/blackfin/kernel/pwm.c
 create mode 100644 drivers/pwm/Kconfig
 create mode 100644 drivers/pwm/Makefile
 create mode 100644 drivers/pwm/core.c
 create mode 100644 drivers/pwm/pwm-bfin.c
 rename arch/arm/plat-mxc/pwm.c => drivers/pwm/pwm-imx.c (58%)
 rename arch/arm/plat-pxa/pwm.c => drivers/pwm/pwm-pxa.c (57%)
 rename arch/arm/plat-samsung/pwm.c => drivers/pwm/pwm-samsung.c (58%)
 create mode 100644 drivers/pwm/pwm-tegra.c
 rename arch/arm/mach-vt8500/pwm.c => drivers/pwm/pwm-vt8500.c (52%)
 create mode 100644 include/linux/of_pwm.h

-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:45 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:45 +0200
Subject: [PATCH v5 03/16] pwm: Add debugfs interface
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-4-git-send-email-thierry.reding@avionic-design.de>

This commit adds a debugfs interface that can be used to list the
current internal state of the PWM devices registered with the PWM
framework.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v5:
- new patch splitting off debugfs interface implementation
- use seq_file's iterator interface for debugfs support
- add missing forward declaration of struct seq_file

 drivers/pwm/core.c  |   90 +++++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/pwm.h |    6 ++++
 2 files changed, 96 insertions(+)

diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 46dcbe1..12a643d 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -27,6 +27,8 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/device.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
 
 #define MAX_PWMS 1024
 
@@ -334,3 +336,91 @@ void pwm_disable(struct pwm_device *pwm)
 		pwm->chip->ops->disable(pwm->chip, pwm);
 }
 EXPORT_SYMBOL_GPL(pwm_disable);
+
+#ifdef CONFIG_DEBUG_FS
+static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s)
+{
+	unsigned int i;
+
+	for (i = 0; i < chip->npwm; i++) {
+		struct pwm_device *pwm = &chip->pwms[i];
+
+		seq_printf(s, " pwm-%-3d (%-20.20s):", i, pwm->label);
+
+		if (test_bit(PWMF_REQUESTED, &pwm->flags))
+			seq_printf(s, " requested");
+
+		if (test_bit(PWMF_ENABLED, &pwm->flags))
+			seq_printf(s, " enabled");
+
+		seq_printf(s, "\n");
+	}
+}
+
+static void *pwm_seq_start(struct seq_file *s, loff_t *pos)
+{
+	mutex_lock(&pwm_lock);
+	s->private = "";
+
+	return seq_list_start(&pwm_chips, *pos);
+}
+
+static void *pwm_seq_next(struct seq_file *s, void *v, loff_t *pos)
+{
+	s->private = "\n";
+
+	return seq_list_next(v, &pwm_chips, pos);
+}
+
+static void pwm_seq_stop(struct seq_file *s, void *v)
+{
+	mutex_unlock(&pwm_lock);
+}
+
+static int pwm_seq_show(struct seq_file *s, void *v)
+{
+	struct pwm_chip *chip = list_entry(v, struct pwm_chip, list);
+
+	seq_printf(s, "%s%s/%s, %d PWM device%s\n", (char *)s->private,
+		   chip->dev->bus ? chip->dev->bus->name : "no-bus",
+		   dev_name(chip->dev), chip->npwm,
+		   (chip->npwm != 1) ? "s" : "");
+
+	if (chip->ops->dbg_show)
+		chip->ops->dbg_show(chip, s);
+	else
+		pwm_dbg_show(chip, s);
+
+	return 0;
+}
+
+static const struct seq_operations pwm_seq_ops = {
+	.start = pwm_seq_start,
+	.next = pwm_seq_next,
+	.stop = pwm_seq_stop,
+	.show = pwm_seq_show,
+};
+
+static int pwm_seq_open(struct inode *inode, struct file *file)
+{
+	return seq_open(file, &pwm_seq_ops);
+}
+
+static const struct file_operations pwm_debugfs_ops = {
+	.owner = THIS_MODULE,
+	.open = pwm_seq_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = seq_release,
+};
+
+static int __init pwm_debugfs_init(void)
+{
+	debugfs_create_file("pwm", S_IFREG | S_IRUGO, NULL, NULL,
+			    &pwm_debugfs_ops);
+
+	return 0;
+}
+
+subsys_initcall(pwm_debugfs_init);
+#endif /* CONFIG_DEBUG_FS */
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index 5710391..047cd53 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -2,6 +2,7 @@
 #define __LINUX_PWM_H
 
 struct pwm_device;
+struct seq_file;
 
 /*
  * pwm_request - request a PWM device
@@ -65,6 +66,7 @@ static inline unsigned int pwm_get_period(struct pwm_device *pwm)
  * @config: configure duty cycles and period length for this PWM
  * @enable: enable PWM output toggling
  * @disable: disable PWM output toggling
+ * @dbg_show: optional routine to show contents in debugfs
  * @owner: helps prevent removal of modules exporting active PWMs
  */
 struct pwm_ops {
@@ -79,6 +81,10 @@ struct pwm_ops {
 					  struct pwm_device *pwm);
 	void			(*disable)(struct pwm_chip *chip,
 					   struct pwm_device *pwm);
+#ifdef CONFIG_DEBUG_FS
+	void			(*dbg_show)(struct pwm_chip *chip,
+					    struct seq_file *s);
+#endif
 	struct module		*owner;
 };
 
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:49 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:49 +0200
Subject: [PATCH v5 07/16] ARM: tegra: Provide clock for only one PWM controller
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-8-git-send-email-thierry.reding@avionic-design.de>

A subsequent patch will add a generic PWM API driver for the Tegra PWFM
controller, supporting all four PWM devices with a single PWM chip. The
device will be named tegra-pwm and only one clock needs to be provided.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
Acked-by: Stephen Warren <swarren at nvidia.com>
---
Changes in v5:
- rename the device name to "tegra-pwm" in the clock lookup table
- get rid of all CLK_DUPLICATE entries which are no longer needed

 arch/arm/mach-tegra/tegra2_clocks.c  |    6 +-----
 arch/arm/mach-tegra/tegra30_clocks.c |    6 +-----
 2 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 64735bd..c95a878 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -2170,7 +2170,7 @@ static struct clk tegra_list_clks[] = {
 	PERIPH_CLK("i2s2",	"tegra-i2s.1",		NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("spdif_out",	"spdif_out",		NULL,	10,	0x108,	100000000, mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("spdif_in",	"spdif_in",		NULL,	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71),
-	PERIPH_CLK("pwm",	"pwm",			NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71 | MUX_PWM),
+	PERIPH_CLK("pwm",	"tegra-pwm",		NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71 | MUX_PWM),
 	PERIPH_CLK("spi",	"spi",			NULL,	43,	0x114,	40000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("xio",	"xio",			NULL,	45,	0x120,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("twc",	"twc",			NULL,	16,	0x12c,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
@@ -2269,10 +2269,6 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
 	CLK_DUPLICATE("usbd", "tegra-otg", NULL),
 	CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
 	CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-	CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
-	CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
-	CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
-	CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
 	CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
 	CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
 	CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 6d08b53..18afd0c 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -2886,7 +2886,7 @@ struct clk tegra_list_clks[] = {
 	PERIPH_CLK("i2s4",	"tegra30-i2s.4",	NULL,	102,	0x3c0,	26000000,  mux_pllaout0_audio4_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
 	PERIPH_CLK("spdif_out",	"tegra30-spdif",	"spdif_out",	10,	0x108,	100000000, mux_pllaout0_audio_2x_pllp_clkm,	MUX | DIV_U71 | PERIPH_ON_APB),
 	PERIPH_CLK("spdif_in",	"tegra30-spdif",	"spdif_in",	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71 | PERIPH_ON_APB),
-	PERIPH_CLK("pwm",	"pwm",			NULL,	17,	0x110,	432000000, mux_pllp_pllc_clk32_clkm,	MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
+	PERIPH_CLK("pwm",	"tegra-pwm",		NULL,	17,	0x110,	432000000, mux_pllp_pllc_clk32_clkm,	MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
 	PERIPH_CLK("d_audio",	"tegra30-ahub",		"d_audio", 106,	0x3d0,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("dam0",	"tegra30-dam.0",	NULL,   108,	0x3d8,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("dam1",	"tegra30-dam.1",	NULL,   109,	0x3dc,	48000000,  mux_plla_pllc_pllp_clkm,	MUX | DIV_U71),
@@ -2990,10 +2990,6 @@ struct clk_duplicate tegra_clk_duplicates[] = {
 	CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
 	CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
 	CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
-	CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
-	CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
-	CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
-	CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
 	CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
 	CLK_DUPLICATE("bsev", "nvavp", "bsev"),
 	CLK_DUPLICATE("vde", "tegra-aes", "vde"),
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:48 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:48 +0200
Subject: [PATCH v5 06/16] ARM: tegra: Fix PWM clock programming
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-7-git-send-email-thierry.reding@avionic-design.de>

From: Simon Que <sque at chromium.org>

PWM clock source registers in Tegra 2 have different clock source selection bit
fields than other registers.  PWM clock source bits in CLK_SOURCE_PWM_0 register
are located at bit field bit[30:28] while others are at bit field bit[31:30] in
their respective clock source register.

This patch updates the clock programming to correctly reflect that, by adding a
flag to indicate the alternate bit field format and checking for it when
selecting a clock source (parent clock).

Signed-off-by: Bill Huang <bilhuang at nvidia.com>
Signed-off-by: Simon Que <sque at chromium.org>
Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
Acked-by: Stephen Warren <swarren at wwwdotorg.org>
---
Changes in v4:
  - reuse PWM flag from Tegra 30 clock programming
  - mask out bit 31 explicitly

 arch/arm/mach-tegra/tegra2_clocks.c |   32 ++++++++++++++++++++++++++++----
 1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 592a4ee..64735bd 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -69,6 +69,8 @@
 
 #define PERIPH_CLK_SOURCE_MASK		(3<<30)
 #define PERIPH_CLK_SOURCE_SHIFT		30
+#define PERIPH_CLK_SOURCE_PWM_MASK	(7<<28)
+#define PERIPH_CLK_SOURCE_PWM_SHIFT	28
 #define PERIPH_CLK_SOURCE_ENABLE	(1<<28)
 #define PERIPH_CLK_SOURCE_DIVU71_MASK	0xFF
 #define PERIPH_CLK_SOURCE_DIVU16_MASK	0xFFFF
@@ -908,9 +910,20 @@ static void tegra2_periph_clk_init(struct clk *c)
 	u32 val = clk_readl(c->reg);
 	const struct clk_mux_sel *mux = NULL;
 	const struct clk_mux_sel *sel;
+	u32 shift;
+	u32 mask;
+
+	if (c->flags & MUX_PWM) {
+		shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+		mask = PERIPH_CLK_SOURCE_PWM_MASK;
+	} else {
+		shift = PERIPH_CLK_SOURCE_SHIFT;
+		mask = PERIPH_CLK_SOURCE_MASK;
+	}
+
 	if (c->flags & MUX) {
 		for (sel = c->inputs; sel->input != NULL; sel++) {
-			if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
+			if ((val & mask) >> shift == sel->value)
 				mux = sel;
 		}
 		BUG_ON(!mux);
@@ -1023,12 +1036,23 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
 {
 	u32 val;
 	const struct clk_mux_sel *sel;
+	u32 mask, shift;
+
 	pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+
+	if (c->flags & MUX_PWM) {
+		shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+		mask = PERIPH_CLK_SOURCE_PWM_MASK;
+	} else {
+		shift = PERIPH_CLK_SOURCE_SHIFT;
+		mask = PERIPH_CLK_SOURCE_MASK;
+	}
+
 	for (sel = c->inputs; sel->input != NULL; sel++) {
 		if (sel->input == p) {
 			val = clk_readl(c->reg);
-			val &= ~PERIPH_CLK_SOURCE_MASK;
-			val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
+			val &= ~mask;
+			val |= (sel->value) << shift;
 
 			if (c->refcnt)
 				clk_enable(p);
@@ -2146,7 +2170,7 @@ static struct clk tegra_list_clks[] = {
 	PERIPH_CLK("i2s2",	"tegra-i2s.1",		NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("spdif_out",	"spdif_out",		NULL,	10,	0x108,	100000000, mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("spdif_in",	"spdif_in",		NULL,	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71),
-	PERIPH_CLK("pwm",	"pwm",			NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71),
+	PERIPH_CLK("pwm",	"pwm",			NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71 | MUX_PWM),
 	PERIPH_CLK("spi",	"spi",			NULL,	43,	0x114,	40000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("xio",	"xio",			NULL,	45,	0x120,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
 	PERIPH_CLK("twc",	"twc",			NULL,	16,	0x12c,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:47 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:47 +0200
Subject: [PATCH v5 05/16] pwm: Add device tree support
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-6-git-send-email-thierry.reding@avionic-design.de>

This patch adds helpers to support device tree bindings for the generic
PWM API. Device tree binding documentation for PWM controllers is also
provided.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v5:
- use IS_ENABLED(CONFIG_OF) along with the compiler's DCE instead of
  empty implementations of of_pwmchip_add() and of_pwmchip_remove() in
  the !OF case
- remove OF_PWM Kconfig symbol and make OF support code conditional on
  the OF symbol only
- use "pwms" and "pwm-names" fixed property names
- remove redundant check in of_pwm_simple_xlate()
- use pwm_request_from_chip() instead of pwm_request_from_device()
- integrate OF support with pwm_get() from new patch 4

Changes in v4:
- add OF-specific code removed from patch 2
- make of_node_to_pwmchip() and of_pwm_simple_xlate() static
- rename of_get_named_pwm() to of_pwm_request(), return a struct
  pwm_device, get rid of the now unused spec parameter and use the
  device_node.name field as the PWM's name
- return a requested struct pwm_device from pwm_chip.of_xlate and
  drop the now unused spec parameter
- move OF support code into drivers/pwm/core.c
- used deferred probing if a PWM chip is not available yet

Changes in v2:
- add device tree binding documentation
- add of_xlate to parse controller-specific PWM-specifier

 Documentation/devicetree/bindings/pwm/pwm.txt |   53 ++++++++++
 drivers/pwm/core.c                            |  135 ++++++++++++++++++++++++-
 include/linux/of_pwm.h                        |   34 +++++++
 include/linux/pwm.h                           |    6 ++
 4 files changed, 226 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pwm/pwm.txt
 create mode 100644 include/linux/of_pwm.h

diff --git a/Documentation/devicetree/bindings/pwm/pwm.txt b/Documentation/devicetree/bindings/pwm/pwm.txt
new file mode 100644
index 0000000..bf2addc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm.txt
@@ -0,0 +1,53 @@
+Specifying PWM information for devices
+======================================
+
+1) PWM user nodes
+-----------------
+
+PWM users should specify a list of PWM devices that they want to use
+with a property containing a 'pwm-list':
+
+	pwm-list ::= <single-pwm> [pwm-list]
+	single-pwm ::= <pwm-phandle> <pwm-specifier>
+	pwm-phandle : phandle to PWM controller node
+	pwm-specifier : array of #pwm-cells specifying the given PWM
+			(controller specific)
+
+PWM properties should be named "pwms". The exact meaning of each pwms
+property must be documented in the device tree binding for each device.
+An optional property "pwm-names" may contain a list of strings to label
+each of the PWM devices listed in the "pwms" property. If no "pwm-names"
+property is given, the name of the user node will be used as fallback.
+
+The following example could be used to describe a PWM-based backlight
+device:
+
+	pwm: pwm {
+		#pwm-cells = <2>;
+	};
+
+	[...]
+
+	bl: backlight {
+		pwms = <&pwm 0 5000000>;
+		pwm-names = "backlight";
+	};
+
+pwm-specifier typically encodes the chip-relative PWM number and the PWM
+period in nanoseconds. Note that in the example above, specifying the
+"pwm-names" is redundant because the name "backlight" would be used as
+fallback anyway.
+
+2) PWM controller nodes
+-----------------------
+
+PWM controller nodes must specify the number of cells used for the
+specifier using the '#pwm-cells' property.
+
+An example PWM controller might look like this:
+
+	pwm: pwm at 7000a000 {
+		compatible = "nvidia,tegra20-pwm";
+		reg = <0x7000a000 0x100>;
+		#pwm-cells = <2>;
+	};
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 77961e0..c22dd9a 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -20,6 +20,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/of_pwm.h>
 #include <linux/pwm.h>
 #include <linux/radix-tree.h>
 #include <linux/list.h>
@@ -129,6 +130,45 @@ static int pwm_device_request(struct pwm_device *pwm, const char *label)
 	return 0;
 }
 
+static struct pwm_device *of_pwm_simple_xlate(struct pwm_chip *pc,
+					      const struct of_phandle_args *args)
+{
+	struct pwm_device *pwm;
+
+	if (pc->of_pwm_n_cells < 2)
+		return ERR_PTR(-EINVAL);
+
+	if (args->args[0] >= pc->npwm)
+		return ERR_PTR(-EINVAL);
+
+	pwm = pwm_request_from_chip(pc, args->args[0], NULL);
+	if (IS_ERR(pwm))
+		return ERR_PTR(-ENODEV);
+
+	pwm_set_period(pwm, args->args[1]);
+
+	return pwm;
+}
+
+void of_pwmchip_add(struct pwm_chip *chip)
+{
+	if (!chip->dev || !chip->dev->of_node)
+		return;
+
+	if (!chip->of_xlate) {
+		chip->of_xlate = of_pwm_simple_xlate;
+		chip->of_pwm_n_cells = 2;
+	}
+
+	of_node_get(chip->dev->of_node);
+}
+
+void of_pwmchip_remove(struct pwm_chip *chip)
+{
+	if (chip->dev && chip->dev->of_node)
+		of_node_put(chip->dev->of_node);
+}
+
 /**
  * pwm_set_chip_data() - set private chip data for a PWM
  * @pwm: PWM device
@@ -197,6 +237,9 @@ int pwmchip_add(struct pwm_chip *chip)
 	INIT_LIST_HEAD(&chip->list);
 	list_add(&chip->list, &pwm_chips);
 
+	if (IS_ENABLED(CONFIG_OF))
+		of_pwmchip_add(chip);
+
 out:
 	mutex_unlock(&pwm_lock);
 	return ret;
@@ -227,6 +270,10 @@ int pwmchip_remove(struct pwm_chip *chip)
 	}
 
 	list_del_init(&chip->list);
+
+	if (IS_ENABLED(CONFIG_OF))
+		of_pwmchip_remove(chip);
+
 	free_pwms(chip);
 
 out:
@@ -352,6 +399,85 @@ void pwm_disable(struct pwm_device *pwm)
 }
 EXPORT_SYMBOL_GPL(pwm_disable);
 
+#ifdef CONFIG_OF
+static struct pwm_chip *of_node_to_pwmchip(struct device_node *np)
+{
+	struct pwm_chip *chip;
+
+	mutex_lock(&pwm_lock);
+
+	list_for_each_entry(chip, &pwm_chips, list)
+		if (chip->dev && chip->dev->of_node == np) {
+			mutex_unlock(&pwm_lock);
+			return chip;
+		}
+
+	mutex_unlock(&pwm_lock);
+
+	return ERR_PTR(-EPROBE_DEFER);
+}
+
+/**
+ * of_pwm_request() - request a PWM via the PWM framework
+ * @np: device node to get the PWM from
+ * @index: index of the PWM
+ *
+ * Returns the PWM device parsed from the phandle and index specified in the
+ * "pwms" property of a device tree node or a negative error-code on failure.
+ * Values parsed from the device tree are stored in the returned PWM device
+ * object.
+ */
+struct pwm_device *of_pwm_request(struct device_node *np, int index)
+{
+	struct pwm_device *pwm = NULL;
+	struct of_phandle_args args;
+	struct pwm_chip *pc;
+	int err;
+
+	err = of_parse_phandle_with_args(np, "pwms", "#pwm-cells", index,
+					 &args);
+	if (err) {
+		pr_debug("%s(): can't parse \"pwms\" property\n", __func__);
+		return ERR_PTR(err);
+	}
+
+	pc = of_node_to_pwmchip(args.np);
+	if (IS_ERR(pc)) {
+		pr_debug("%s(): PWM chip not found\n", __func__);
+		pwm = ERR_CAST(pc);
+		goto put;
+	}
+
+	if (args.args_count != pc->of_pwm_n_cells) {
+		pr_debug("%s: wrong #pwm-cells for %s\n", np->full_name,
+			 args.np->full_name);
+		pwm = ERR_PTR(-EINVAL);
+		goto put;
+	}
+
+	pwm = pc->of_xlate(pc, &args);
+	if (IS_ERR(pwm))
+		goto put;
+
+	err = of_property_read_string_index(np, "pwm-names", index,
+					    &pwm->label);
+	if (err < 0) {
+		/*
+		 * Fallback to name of user node if the name cannot be parsed
+		 * from the "pwm-names" property (e.g. the property doesn't
+		 * exist or an error occurred).
+		 */
+		pwm->label = np->name;
+	}
+
+put:
+	of_node_put(args.np);
+
+	return pwm;
+}
+EXPORT_SYMBOL(of_pwm_request);
+#endif
+
 /**
  * pwm_add_table() - register PWM device consumers
  * @table: array of consumers to register
@@ -380,8 +506,9 @@ void __init pwm_add_table(struct pwm_lookup *table, size_t num)
  * @provider: name of provider PWM chip
  * @index: per-chip index of PWM to request
  *
- * Look up a PWM chip and a relative index via a table supplied by board setup
- * code (see pwm_add_table()).
+ * Lookup is first attempted using DT. If the device was not instantiated from
+ * a device tree, a PWM chip and a relative index is looked up via a table
+ * supplied by board setup code (see pwm_add_table()).
  *
  * Once a PWM chip has been found the specified PWM device will be requested
  * and is ready to be used.
@@ -394,6 +521,10 @@ struct pwm_device *pwm_get(struct device *dev, const char *consumer)
 	struct pwm_lookup *p;
 	unsigned int index;
 
+	/* look up via DT first */
+	if (dev && dev->of_node)
+		return of_pwm_request(dev->of_node, 0);
+
 	/*
 	 * We look up the provider in the static table typically provided by
 	 * board setup code. We first try to lookup the consumer device by
diff --git a/include/linux/of_pwm.h b/include/linux/of_pwm.h
new file mode 100644
index 0000000..8c4ed9f
--- /dev/null
+++ b/include/linux/of_pwm.h
@@ -0,0 +1,34 @@
+/*
+ * OF helpers for the PWM API
+ *
+ * Copyright (c) 2011-2012 Avionic Design GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_OF_PWM_H
+#define __LINUX_OF_PWM_H
+
+#include <linux/err.h>
+#include <linux/pwm.h>
+
+struct device_node;
+
+#ifdef CONFIG_OF
+
+struct pwm_device *of_pwm_request(struct device_node *np, int index);
+
+#else
+
+static inline struct pwm_device *of_pwm_request(struct device_node *np,
+						int index)
+{
+	return ERR_PTR(-ENOSYS);
+}
+
+#endif /* CONFIG_OF */
+
+#endif /* __LINUX_OF_PWM_H */
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index a32d2b7..e19c92a 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -1,6 +1,8 @@
 #ifndef __LINUX_PWM_H
 #define __LINUX_PWM_H
 
+#include <linux/of.h>
+
 struct pwm_device;
 struct seq_file;
 
@@ -105,6 +107,10 @@ struct pwm_chip {
 	unsigned int		npwm;
 
 	struct pwm_device	*pwms;
+
+	struct pwm_device *	(*of_xlate)(struct pwm_chip *pc,
+					    const struct of_phandle_args *args);
+	unsigned int		of_pwm_n_cells;
 };
 
 int pwm_set_chip_data(struct pwm_device *pwm, void *data);
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:53 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:53 +0200
Subject: [PATCH v5 11/16] pwm: Move PXA PWM driver to PWM framework
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-12-git-send-email-thierry.reding@avionic-design.de>

This commit moves the PXA PWM driver to the drivers/pwm subdirectory and
converts it to use the new PWM framework.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v5:
- replace __raw_readl()/__raw_writel() by readl()/writel()
- use clk_prepare_enable() and clk_disable_unprepare()

Changes in v3:
- update PWM ops for changes in patch 2

 arch/arm/plat-pxa/Makefile                       |    1 -
 drivers/pwm/Kconfig                              |    9 ++
 drivers/pwm/Makefile                             |    1 +
 arch/arm/plat-pxa/pwm.c => drivers/pwm/pwm-pxa.c |  172 ++++++++--------------
 4 files changed, 68 insertions(+), 115 deletions(-)
 rename arch/arm/plat-pxa/pwm.c => drivers/pwm/pwm-pxa.c (57%)

diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index f302d04..af8e484 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -8,5 +8,4 @@ obj-$(CONFIG_PXA3xx)		+= mfp.o
 obj-$(CONFIG_PXA95x)		+= mfp.o
 obj-$(CONFIG_ARCH_MMP)		+= mfp.o
 
-obj-$(CONFIG_HAVE_PWM)		+= pwm.o
 obj-$(CONFIG_PXA_SSP)		+= ssp.o
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index eb54042..0ef4f30 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -18,6 +18,15 @@ config PWM_BFIN
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-bfin.
 
+config PWM_PXA
+	tristate "PXA PWM support"
+	depends on ARCH_PXA
+	help
+	  Generic PWM framework driver for PXA.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-pxa.
+
 config PWM_TEGRA
 	tristate "NVIDIA Tegra PWM support"
 	depends on ARCH_TEGRA
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 251b8d2..e859c51 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_PWM)		+= core.o
 obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
+obj-$(CONFIG_PWM_PXA)		+= pwm-pxa.o
 obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
diff --git a/arch/arm/plat-pxa/pwm.c b/drivers/pwm/pwm-pxa.c
similarity index 57%
rename from arch/arm/plat-pxa/pwm.c
rename to drivers/pwm/pwm-pxa.c
index ef32686..d5c6ce5 100644
--- a/arch/arm/plat-pxa/pwm.c
+++ b/drivers/pwm/pwm-pxa.c
@@ -43,33 +43,39 @@ MODULE_DEVICE_TABLE(platform, pwm_id_table);
 #define PWMCR_SD	(1 << 6)
 #define PWMDCR_FD	(1 << 10)
 
-struct pwm_device {
-	struct list_head	node;
-	struct pwm_device	*secondary;
-	struct platform_device	*pdev;
+struct pxa_pwm_chip {
+	struct pwm_chip	chip;
+	struct device	*dev;
 
-	const char	*label;
 	struct clk	*clk;
 	int		clk_enabled;
 	void __iomem	*mmio_base;
-
-	unsigned int	use_count;
-	unsigned int	pwm_id;
 };
 
+static inline struct pxa_pwm_chip *to_pxa_pwm_chip(struct pwm_chip *chip)
+{
+	return container_of(chip, struct pxa_pwm_chip, chip);
+}
+
 /*
  * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
  * duty_ns   = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
  */
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+			  int duty_ns, int period_ns)
 {
+	struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
 	unsigned long long c;
 	unsigned long period_cycles, prescale, pv, dc;
+	unsigned long offset;
+	int rc;
 
-	if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
+	if (period_ns == 0 || duty_ns > period_ns)
 		return -EINVAL;
 
-	c = clk_get_rate(pwm->clk);
+	offset = pwm->hwpwm ? 0x10 : 0;
+
+	c = clk_get_rate(pc->clk);
 	c = c * period_ns;
 	do_div(c, 1000000000);
 	period_cycles = c;
@@ -90,98 +96,56 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 	/* NOTE: the clock to PWM has to be enabled first
 	 * before writing to the registers
 	 */
-	clk_enable(pwm->clk);
-	__raw_writel(prescale, pwm->mmio_base + PWMCR);
-	__raw_writel(dc, pwm->mmio_base + PWMDCR);
-	__raw_writel(pv, pwm->mmio_base + PWMPCR);
-	clk_disable(pwm->clk);
+	rc = clk_prepare_enable(pc->clk);
+	if (rc < 0)
+		return rc;
+
+	writel(prescale, pc->mmio_base + offset + PWMCR);
+	writel(dc, pc->mmio_base + offset + PWMDCR);
+	writel(pv, pc->mmio_base + offset + PWMPCR);
 
+	clk_disable_unprepare(pc->clk);
 	return 0;
 }
-EXPORT_SYMBOL(pwm_config);
 
-int pwm_enable(struct pwm_device *pwm)
+static int pxa_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
+	struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
 	int rc = 0;
 
-	if (!pwm->clk_enabled) {
-		rc = clk_enable(pwm->clk);
+	if (!pc->clk_enabled) {
+		rc = clk_prepare_enable(pc->clk);
 		if (!rc)
-			pwm->clk_enabled = 1;
+			pc->clk_enabled++;
 	}
 	return rc;
 }
-EXPORT_SYMBOL(pwm_enable);
 
-void pwm_disable(struct pwm_device *pwm)
+static void pxa_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
-	if (pwm->clk_enabled) {
-		clk_disable(pwm->clk);
-		pwm->clk_enabled = 0;
-	}
-}
-EXPORT_SYMBOL(pwm_disable);
+	struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip);
 
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-	struct pwm_device *pwm;
-	int found = 0;
-
-	mutex_lock(&pwm_lock);
-
-	list_for_each_entry(pwm, &pwm_list, node) {
-		if (pwm->pwm_id == pwm_id) {
-			found = 1;
-			break;
-		}
+	if (pc->clk_enabled) {
+		clk_disable_unprepare(pc->clk);
+		pc->clk_enabled--;
 	}
-
-	if (found) {
-		if (pwm->use_count == 0) {
-			pwm->use_count++;
-			pwm->label = label;
-		} else
-			pwm = ERR_PTR(-EBUSY);
-	} else
-		pwm = ERR_PTR(-ENOENT);
-
-	mutex_unlock(&pwm_lock);
-	return pwm;
 }
-EXPORT_SYMBOL(pwm_request);
-
-void pwm_free(struct pwm_device *pwm)
-{
-	mutex_lock(&pwm_lock);
 
-	if (pwm->use_count) {
-		pwm->use_count--;
-		pwm->label = NULL;
-	} else
-		pr_warning("PWM device already freed\n");
-
-	mutex_unlock(&pwm_lock);
-}
-EXPORT_SYMBOL(pwm_free);
-
-static inline void __add_pwm(struct pwm_device *pwm)
-{
-	mutex_lock(&pwm_lock);
-	list_add_tail(&pwm->node, &pwm_list);
-	mutex_unlock(&pwm_lock);
-}
+static struct pwm_ops pxa_pwm_ops = {
+	.config = pxa_pwm_config,
+	.enable = pxa_pwm_enable,
+	.disable = pxa_pwm_disable,
+	.owner = THIS_MODULE,
+};
 
 static int __devinit pwm_probe(struct platform_device *pdev)
 {
 	const struct platform_device_id *id = platform_get_device_id(pdev);
-	struct pwm_device *pwm, *secondary = NULL;
+	struct pxa_pwm_chip *pwm;
 	struct resource *r;
 	int ret = 0;
 
-	pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
+	pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
 	if (pwm == NULL) {
 		dev_err(&pdev->dev, "failed to allocate memory\n");
 		return -ENOMEM;
@@ -194,9 +158,10 @@ static int __devinit pwm_probe(struct platform_device *pdev)
 	}
 	pwm->clk_enabled = 0;
 
-	pwm->use_count = 0;
-	pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id;
-	pwm->pdev = pdev;
+	pwm->chip.dev = &pdev->dev;
+	pwm->chip.ops = &pxa_pwm_ops;
+	pwm->chip.base = -1;
+	pwm->chip.npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
@@ -219,25 +184,12 @@ static int __devinit pwm_probe(struct platform_device *pdev)
 		goto err_free_mem;
 	}
 
-	if (id->driver_data & HAS_SECONDARY_PWM) {
-		secondary = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
-		if (secondary == NULL) {
-			ret = -ENOMEM;
-			goto err_free_mem;
-		}
-
-		*secondary = *pwm;
-		pwm->secondary = secondary;
-
-		/* registers for the second PWM has offset of 0x10 */
-		secondary->mmio_base = pwm->mmio_base + 0x10;
-		secondary->pwm_id = pdev->id + 2;
+	ret = pwmchip_add(&pwm->chip);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
+		return ret;
 	}
 
-	__add_pwm(pwm);
-	if (secondary)
-		__add_pwm(secondary);
-
 	platform_set_drvdata(pdev, pwm);
 	return 0;
 
@@ -252,30 +204,22 @@ err_free:
 
 static int __devexit pwm_remove(struct platform_device *pdev)
 {
-	struct pwm_device *pwm;
+	struct pxa_pwm_chip *chip;
 	struct resource *r;
 
-	pwm = platform_get_drvdata(pdev);
-	if (pwm == NULL)
+	chip = platform_get_drvdata(pdev);
+	if (chip == NULL)
 		return -ENODEV;
 
-	mutex_lock(&pwm_lock);
-
-	if (pwm->secondary) {
-		list_del(&pwm->secondary->node);
-		kfree(pwm->secondary);
-	}
+	pwmchip_remove(&chip->chip);
 
-	list_del(&pwm->node);
-	mutex_unlock(&pwm_lock);
-
-	iounmap(pwm->mmio_base);
+	iounmap(chip->mmio_base);
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	release_mem_region(r->start, resource_size(r));
 
-	clk_put(pwm->clk);
-	kfree(pwm);
+	clk_put(chip->clk);
+	kfree(chip);
 	return 0;
 }
 
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:43 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:43 +0200
Subject: [PATCH v5 01/16] pwm: Add PWM framework support
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-2-git-send-email-thierry.reding@avionic-design.de>

From: Sascha Hauer <s.hauer at pengutronix.de>

This patch adds framework support for PWM (pulse width modulation) devices.

The is a barebone PWM API already in the kernel under include/linux/pwm.h,
but it does not allow for multiple drivers as each of them implements the
pwm_*() functions.

There are other PWM framework patches around from Bill Gatliff. Unlike
his framework this one does not change the existing API for PWMs so that
this framework can act as a drop in replacement for the existing API.

Why another framework?

Several people argue that there should not be another framework for PWMs
but they should be integrated into one of the existing frameworks like led
or hwmon. Unlike these frameworks the PWM framework is agnostic to the
purpose of the PWM. In fact, a PWM can drive a LED, but this makes the
LED framework a user of a PWM, like already done in leds-pwm.c. The gpio
framework also is not suitable for PWMs. Every gpio could be turned into
a PWM using timer based toggling, but on the other hand not every PWM hardware
device can be turned into a gpio due to the lack of hardware capabilities.

This patch does not try to improve the PWM API yet, this could be done in
subsequent patches.

[thierry.reding at avionic-design.de: fixup typos, kerneldoc comments]
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Acked-by: Kurt Van Dijck <kurt.van.dijck at eia.be>
Reviewed-by: Arnd Bergmann <arnd at arndb.de>
Reviewed-by: Matthias Kaehlcke <matthias at kaehlcke.net>
Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v5:
- minor cleanups and typo fixes
- add some kerneldoc comments

 Documentation/pwm.txt |   54 ++++++++++++
 MAINTAINERS           |    6 ++
 drivers/Kconfig       |    2 +
 drivers/Makefile      |    1 +
 drivers/pwm/Kconfig   |   12 +++
 drivers/pwm/Makefile  |    1 +
 drivers/pwm/core.c    |  227 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/pwm.h   |   38 +++++++++
 8 files changed, 341 insertions(+)
 create mode 100644 Documentation/pwm.txt
 create mode 100644 drivers/pwm/Kconfig
 create mode 100644 drivers/pwm/Makefile
 create mode 100644 drivers/pwm/core.c

diff --git a/Documentation/pwm.txt b/Documentation/pwm.txt
new file mode 100644
index 0000000..03e39d1
--- /dev/null
+++ b/Documentation/pwm.txt
@@ -0,0 +1,54 @@
+Pulse Width Modulation (PWM) interface
+
+This provides an overview about the Linux PWM interface
+
+PWMs are commonly used for controlling LEDs, fans or vibrators in
+cell phones. PWMs with a fixed purpose have no need implementing
+the Linux PWM API (although they could). However, PWMs are often
+found as discrete devices on SoCs which have no fixed purpose. It's
+up to the board designer to connect them to LEDs or fans. To provide
+this kind of flexibility the generic PWM API exists.
+
+Identifying PWMs
+----------------
+
+Users of the legacy PWM API use unique IDs to refer to PWM devices. One
+goal of the new PWM framework is to get rid of this global namespace.
+
+Using PWMs
+----------
+
+A PWM can be requested using pwm_request() and freed after usage with
+pwm_free(). After being requested a PWM has to be configured using
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
+
+To start/stop toggling the PWM output use pwm_enable()/pwm_disable().
+
+Implementing a PWM driver
+-------------------------
+
+Currently there are two ways to implement pwm drivers. Traditionally
+there only has been the barebone API meaning that each driver has
+to implement the pwm_*() functions itself. This means that it's impossible
+to have multiple PWM drivers in the system. For this reason it's mandatory
+for new drivers to use the generic PWM framework.
+A new PWM device can be added using pwmchip_add() and removed again with
+pwmchip_remove(). pwmchip_add() takes a filled in struct pwm_chip as
+argument which provides the ops and the pwm id to the framework.
+
+Locking
+-------
+
+The PWM core list manipulations are protected by a mutex, so pwm_request()
+and pwm_free() may not be called from an atomic context. Currently the
+PWM core does not enforce any locking to pwm_enable(), pwm_disable() and
+pwm_config(), so the calling context is currently driver specific. This
+is an issue derived from the former barebone API and should be fixed soon.
+
+Helpers
+-------
+
+Currently a PWM can only be configured with period_ns and duty_ns. For several
+use cases freq_hz and duty_percent might be better. Instead of calculating
+this in your driver please consider adding appropriate helpers to the framework.
diff --git a/MAINTAINERS b/MAINTAINERS
index c934395..d68feef 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5429,6 +5429,12 @@ S:	Maintained
 F:	Documentation/video4linux/README.pvrusb2
 F:	drivers/media/video/pvrusb2/
 
+PWM core
+M:	Sascha Hauer <s.hauer at pengutronix.de>
+L:	linux-kernel at vger.kernel.org
+S:	Maintained
+F:	drivers/pwm/
+
 PXA2xx/PXA3xx SUPPORT
 M:	Eric Miao <eric.y.miao at gmail.com>
 M:	Russell King <linux at arm.linux.org.uk>
diff --git a/drivers/Kconfig b/drivers/Kconfig
index b3ae9e5..ec094b5 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -142,4 +142,6 @@ source "drivers/devfreq/Kconfig"
 
 source "drivers/modem_shm/Kconfig"
 
+source "drivers/pwm/Kconfig"
+
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 4855a1a..52fe956 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -8,6 +8,7 @@
 # GPIO must come after pinctrl as gpios may need to mux pins etc
 obj-y				+= pinctrl/
 obj-y				+= gpio/
+obj-y				+= pwm/
 obj-$(CONFIG_PCI)		+= pci/
 obj-$(CONFIG_PARISC)		+= parisc/
 obj-$(CONFIG_RAPIDIO)		+= rapidio/
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
new file mode 100644
index 0000000..93c1052
--- /dev/null
+++ b/drivers/pwm/Kconfig
@@ -0,0 +1,12 @@
+menuconfig PWM
+	bool "PWM Support"
+	help
+	  This enables PWM support through the generic PWM framework.
+	  You only need to enable this, if you also want to enable
+	  one or more of the PWM drivers below.
+
+	  If unsure, say N.
+
+if PWM
+
+endif
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
new file mode 100644
index 0000000..3469c3d
--- /dev/null
+++ b/drivers/pwm/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PWM)		+= core.o
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
new file mode 100644
index 0000000..db2f048
--- /dev/null
+++ b/drivers/pwm/core.c
@@ -0,0 +1,227 @@
+/*
+ * Generic pwmlib implementation
+ *
+ * Copyright (C) 2011 Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2, or (at your option)
+ *  any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; see the file COPYING.  If not, write to
+ *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/pwm.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+
+struct pwm_device {
+	struct			pwm_chip *chip;
+	const char		*label;
+	unsigned long		flags;
+#define FLAG_REQUESTED	0
+#define FLAG_ENABLED	1
+	struct list_head	node;
+};
+
+static LIST_HEAD(pwm_list);
+
+static DEFINE_MUTEX(pwm_lock);
+
+static struct pwm_device *_find_pwm(int pwm_id)
+{
+	struct pwm_device *pwm;
+
+	list_for_each_entry(pwm, &pwm_list, node) {
+		if (pwm->chip->pwm_id == pwm_id)
+			return pwm;
+	}
+
+	return NULL;
+}
+
+/**
+ * pwmchip_add() - register a new PWM chip
+ * @chip: the PWM chip to add
+ */
+int pwmchip_add(struct pwm_chip *chip)
+{
+	struct pwm_device *pwm;
+	int ret = 0;
+
+	pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
+	if (!pwm)
+		return -ENOMEM;
+
+	pwm->chip = chip;
+
+	mutex_lock(&pwm_lock);
+
+	if (chip->pwm_id >= 0 && _find_pwm(chip->pwm_id)) {
+		ret = -EBUSY;
+		goto out;
+	}
+
+	list_add_tail(&pwm->node, &pwm_list);
+out:
+	mutex_unlock(&pwm_lock);
+
+	if (ret)
+		kfree(pwm);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(pwmchip_add);
+
+/**
+ * pwmchip_remove() - remove a PWM chip
+ * @chip: the PWM chip to remove
+ *
+ * Removes a PWM chip. This function may return busy if the PWM chip provides
+ * a PWM device that is still requested.
+ */
+int pwmchip_remove(struct pwm_chip *chip)
+{
+	struct pwm_device *pwm;
+	int ret = 0;
+
+	mutex_lock(&pwm_lock);
+
+	pwm = _find_pwm(chip->pwm_id);
+	if (!pwm) {
+		ret = -ENOENT;
+		goto out;
+	}
+
+	if (test_bit(FLAG_REQUESTED, &pwm->flags)) {
+		ret = -EBUSY;
+		goto out;
+	}
+
+	list_del(&pwm->node);
+
+	kfree(pwm);
+out:
+	mutex_unlock(&pwm_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(pwmchip_remove);
+
+/**
+ * pwm_request() - request a PWM device
+ * @pwm: global PWM device index
+ * @label: PWM device label
+ */
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+	struct pwm_device *pwm;
+	int ret;
+
+	mutex_lock(&pwm_lock);
+
+	pwm = _find_pwm(pwm_id);
+	if (!pwm) {
+		pwm = ERR_PTR(-ENOENT);
+		goto out;
+	}
+
+	if (test_bit(FLAG_REQUESTED, &pwm->flags)) {
+		pwm = ERR_PTR(-EBUSY);
+		goto out;
+	}
+
+	if (!try_module_get(pwm->chip->ops->owner)) {
+		pwm = ERR_PTR(-ENODEV);
+		goto out;
+	}
+
+	if (pwm->chip->ops->request) {
+		ret = pwm->chip->ops->request(pwm->chip);
+		if (ret) {
+			pwm = ERR_PTR(ret);
+			goto out_put;
+		}
+	}
+
+	pwm->label = label;
+	set_bit(FLAG_REQUESTED, &pwm->flags);
+
+	goto out;
+
+out_put:
+	module_put(pwm->chip->ops->owner);
+out:
+	mutex_unlock(&pwm_lock);
+
+	return pwm;
+}
+EXPORT_SYMBOL_GPL(pwm_request);
+
+/**
+ * pwm_free() - free a PWM device
+ * @pwm: PWM device
+ */
+void pwm_free(struct pwm_device *pwm)
+{
+	mutex_lock(&pwm_lock);
+
+	if (!test_and_clear_bit(FLAG_REQUESTED, &pwm->flags)) {
+		pr_warning("PWM device already freed\n");
+		goto out;
+	}
+
+	pwm->label = NULL;
+
+	module_put(pwm->chip->ops->owner);
+out:
+	mutex_unlock(&pwm_lock);
+}
+EXPORT_SYMBOL_GPL(pwm_free);
+
+/**
+ * pwm_config() - change a PWM device configuration
+ * @pwm: PWM device
+ * @duty_ns: "on" time (in nanoseconds)
+ * @period_ns: duration (in nanoseconds) of one cycle
+ */
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+	return pwm->chip->ops->config(pwm->chip, duty_ns, period_ns);
+}
+EXPORT_SYMBOL_GPL(pwm_config);
+
+/**
+ * pwm_enable() - start a PWM output toggling
+ * @pwm: PWM device
+ */
+int pwm_enable(struct pwm_device *pwm)
+{
+	if (!test_and_set_bit(FLAG_ENABLED, &pwm->flags))
+		return pwm->chip->ops->enable(pwm->chip);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pwm_enable);
+
+/**
+ * pwm_disable() - stop a PWM output toggling
+ * @pwm: PWM device
+ */
+void pwm_disable(struct pwm_device *pwm)
+{
+	if (test_and_clear_bit(FLAG_ENABLED, &pwm->flags))
+		pwm->chip->ops->disable(pwm->chip);
+}
+EXPORT_SYMBOL_GPL(pwm_disable);
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index 7c77575..4bad29c 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -28,4 +28,42 @@ int pwm_enable(struct pwm_device *pwm);
  */
 void pwm_disable(struct pwm_device *pwm);
 
+#ifdef CONFIG_PWM
+struct pwm_chip;
+
+/**
+ * struct pwm_ops - PWM controller operations
+ * @request: optional hook for requesting a PWM
+ * @free: optional hook for freeing a PWM
+ * @config: configure duty cycles and period length for this PWM
+ * @enable: enable PWM output toggling
+ * @disable: disable PWM output toggling
+ * @owner: helps prevent removal of modules exporting active PWMs
+ */
+struct pwm_ops {
+	int			(*request)(struct pwm_chip *chip);
+	void			(*free)(struct pwm_chip *chip);
+	int			(*config)(struct pwm_chip *chip, int duty_ns,
+						int period_ns);
+	int			(*enable)(struct pwm_chip *chip);
+	void			(*disable)(struct pwm_chip *chip);
+	struct module		*owner;
+};
+
+/**
+ * struct pwm_chip - abstract a PWM
+ * @label: for diagnostics
+ * @owner: helps prevent removal of modules exporting active PWMs
+ * @ops: The callbacks for this PWM
+ */
+struct pwm_chip {
+	int			pwm_id;
+	const char		*label;
+	struct pwm_ops		*ops;
+};
+
+int pwmchip_add(struct pwm_chip *chip);
+int pwmchip_remove(struct pwm_chip *chip);
+#endif
+
 #endif /* __LINUX_PWM_H */
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:51 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:51 +0200
Subject: [PATCH v5 09/16] pwm: tegra: Add device tree support
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-10-git-send-email-thierry.reding@avionic-design.de>

Add auxdata to instantiate the PWFM controller from a device tree,
include the corresponding nodes in the dtsi files for Tegra 20 and
Tegra 30 and add binding documentation.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
Acked-by: Stephen Warren <swarren at wwwdotorg.org>
---
Changes in v5:
- rename tegra-pwm.txt to nvidia,tegra20-pwm.txt

Changes in v4:
- add DT binding documentation
- allow nvidia,tegra20-pwm as fallback for nvidia,tegra30-pwm
- export OF device table (for module auto-loading)

Changes in v3:
- add missing include for mach/iomap.h

 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt |   18 ++++++++++++++++++
 arch/arm/boot/dts/tegra20.dtsi                     |    6 ++++++
 arch/arm/boot/dts/tegra30.dtsi                     |    6 ++++++
 arch/arm/mach-tegra/board-dt-tegra20.c             |    1 +
 arch/arm/mach-tegra/board-dt-tegra30.c             |    3 +++
 drivers/pwm/pwm-tegra.c                            |   11 +++++++++++
 6 files changed, 45 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt

diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
new file mode 100644
index 0000000..bbbeedb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -0,0 +1,18 @@
+Tegra SoC PWFM controller
+
+Required properties:
+- compatible: should be one of:
+  - "nvidia,tegra20-pwm"
+  - "nvidia,tegra30-pwm"
+- reg: physical base address and length of the controller's registers
+- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
+  first cell specifies the per-chip index of the PWM to use and the second
+  cell is the duty cycle in nanoseconds.
+
+Example:
+
+	pwm: pwm at 7000a000 {
+		compatible = "nvidia,tegra20-pwm";
+		reg = <0x7000a000 0x100>;
+		#pwm-cells = <2>;
+	};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 108e894..55b28fd 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -154,6 +154,12 @@
 		interrupts = < 0 91 0x04 >;
 	};
 
+	pwm: pwm at 7000a000 {
+		compatible = "nvidia,tegra20-pwm";
+		reg = <0x7000a000 0x100>;
+		#pwm-cells = <2>;
+	};
+
 	emc at 7000f400 {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 62a7b39..3fa5211 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -154,6 +154,12 @@
 		interrupts = < 0 91 0x04 >;
 	};
 
+	pwm: pwm at 7000a000 {
+		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
+		reg = <0x7000a000 0x100>;
+		#pwm-cells = <2>;
+	};
+
 	sdhci at 78000000 {
 		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 		reg = <0x78000000 0x200>;
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index e20b419..2180954 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -73,6 +73,7 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 		       &tegra_ehci2_device.dev.platform_data),
 	OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
 		       &tegra_ehci3_device.dev.platform_data),
+	OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
 	{}
 };
 
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 5f7c03e..5e1180f 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -33,6 +33,8 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
 
+#include <mach/iomap.h>
+
 #include "board.h"
 #include "clock.h"
 
@@ -51,6 +53,7 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
 	{}
 };
 
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 2219be1..981f28a 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -239,9 +239,20 @@ static int __devexit tegra_pwm_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id tegra_pwm_of_match[] = {
+	{ .compatible = "nvidia,tegra20-pwm" },
+	{ .compatible = "nvidia,tegra30-pwm" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
+#endif
+
 static struct platform_driver tegra_pwm_driver = {
 	.driver = {
 		.name = "tegra-pwm",
+		.of_match_table = of_match_ptr(tegra_pwm_of_match),
 	},
 	.probe = tegra_pwm_probe,
 	.remove = __devexit_p(tegra_pwm_remove),
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:54 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:54 +0200
Subject: [PATCH v5 12/16] ARM i.MX: Move i.MX pwm driver to pwm framework
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-13-git-send-email-thierry.reding@avionic-design.de>

From: Sascha Hauer <s.hauer at pengutronix.de>

Move the driver to drivers/pwm/ and convert it to use the framework.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v5:
- adopt patch by Sascha Hauer to move i.MX driver to PWM framework
- rename to imx_pwm internally

 arch/arm/plat-mxc/Kconfig                        |    6 -
 arch/arm/plat-mxc/Makefile                       |    1 -
 drivers/pwm/Kconfig                              |    9 ++
 drivers/pwm/Makefile                             |    1 +
 arch/arm/plat-mxc/pwm.c => drivers/pwm/pwm-imx.c |  182 +++++++++-------------
 5 files changed, 81 insertions(+), 118 deletions(-)
 rename arch/arm/plat-mxc/pwm.c => drivers/pwm/pwm-imx.c (58%)

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index c722f9c..baf9064 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -47,12 +47,6 @@ config MXC_TZIC
 config MXC_AVIC
 	bool
 
-config MXC_PWM
-	tristate "Enable PWM driver"
-	select HAVE_PWM
-	help
-	  Enable support for the i.MX PWM controller(s).
-
 config MXC_DEBUG_BOARD
 	bool "Enable MXC debug board(for 3-stack)"
 	help
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index e81290c..46ba8de 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -11,7 +11,6 @@ obj-$(CONFIG_MXC_AVIC) += avic.o
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
-obj-$(CONFIG_MXC_PWM)  += pwm.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 0ef4f30..a9a9715 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -18,6 +18,15 @@ config PWM_BFIN
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-bfin.
 
+config PWM_IMX
+	tristate "i.MX pwm support"
+	depends on ARCH_MXC
+	help
+	  Generic PWM framework driver for i.MX.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-imx.
+
 config PWM_PXA
 	tristate "PXA PWM support"
 	depends on ARCH_PXA
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index e859c51..3dd1b83 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_PWM)		+= core.o
 obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
+obj-$(CONFIG_PWM_IMX)		+= pwm-imx.o
 obj-$(CONFIG_PWM_PXA)		+= pwm-pxa.o
 obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
diff --git a/arch/arm/plat-mxc/pwm.c b/drivers/pwm/pwm-imx.c
similarity index 58%
rename from arch/arm/plat-mxc/pwm.c
rename to drivers/pwm/pwm-imx.c
index c0cab22..ef9c51b 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/drivers/pwm/pwm-imx.c
@@ -39,33 +39,28 @@
 #define MX3_PWMCR_CLKSRC_IPG      (1 << 16)
 #define MX3_PWMCR_EN              (1 << 0)
 
-
-
-struct pwm_device {
-	struct list_head	node;
-	struct platform_device *pdev;
-
-	const char	*label;
+struct imx_chip {
 	struct clk	*clk;
 
 	int		clk_enabled;
 	void __iomem	*mmio_base;
 
-	unsigned int	use_count;
-	unsigned int	pwm_id;
+	struct pwm_chip	chip;
 };
 
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+#define to_imx_chip(chip)	container_of(chip, struct imx_chip, chip)
+
+static int imx_pwm_config(struct pwm_chip *chip,
+		struct pwm_device *pwm, int duty_ns, int period_ns)
 {
-	if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
-		return -EINVAL;
+	struct imx_chip *imx = to_imx_chip(chip);
 
 	if (!(cpu_is_mx1() || cpu_is_mx21())) {
 		unsigned long long c;
 		unsigned long period_cycles, duty_cycles, prescale;
 		u32 cr;
 
-		c = clk_get_rate(pwm->clk);
+		c = clk_get_rate(imx->clk);
 		c = c * period_ns;
 		do_div(c, 1000000000);
 		period_cycles = c;
@@ -86,8 +81,8 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 		else
 			period_cycles = 0;
 
-		writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);
-		writel(period_cycles, pwm->mmio_base + MX3_PWMPR);
+		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
+		writel(period_cycles, imx->mmio_base + MX3_PWMPR);
 
 		cr = MX3_PWMCR_PRESCALER(prescale) |
 			MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
@@ -98,7 +93,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 		else
 			cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
 
-		writel(cr, pwm->mmio_base + MX3_PWMCR);
+		writel(cr, imx->mmio_base + MX3_PWMCR);
 	} else if (cpu_is_mx1() || cpu_is_mx21()) {
 		/* The PWM subsystem allows for exact frequencies. However,
 		 * I cannot connect a scope on my device to the PWM line and
@@ -116,110 +111,72 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 		 * both the prescaler (/1 .. /128) and then by CLKSEL
 		 * (/2 .. /16).
 		 */
-		u32 max = readl(pwm->mmio_base + MX1_PWMP);
+		u32 max = readl(imx->mmio_base + MX1_PWMP);
 		u32 p = max * duty_ns / period_ns;
-		writel(max - p, pwm->mmio_base + MX1_PWMS);
+		writel(max - p, imx->mmio_base + MX1_PWMS);
 	} else {
 		BUG();
 	}
 
 	return 0;
 }
-EXPORT_SYMBOL(pwm_config);
 
-int pwm_enable(struct pwm_device *pwm)
+static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
+	struct imx_chip *imx = to_imx_chip(chip);
 	int rc = 0;
 
-	if (!pwm->clk_enabled) {
-		rc = clk_prepare_enable(pwm->clk);
+	if (!imx->clk_enabled) {
+		rc = clk_prepare_enable(imx->clk);
 		if (!rc)
-			pwm->clk_enabled = 1;
+			imx->clk_enabled = 1;
 	}
 	return rc;
 }
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-	writel(0, pwm->mmio_base + MX3_PWMCR);
-
-	if (pwm->clk_enabled) {
-		clk_disable_unprepare(pwm->clk);
-		pwm->clk_enabled = 0;
-	}
-}
-EXPORT_SYMBOL(pwm_disable);
-
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
 
-struct pwm_device *pwm_request(int pwm_id, const char *label)
+static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
-	struct pwm_device *pwm;
-	int found = 0;
+	struct imx_chip *imx = to_imx_chip(chip);
 
-	mutex_lock(&pwm_lock);
+	writel(0, imx->mmio_base + MX3_PWMCR);
 
-	list_for_each_entry(pwm, &pwm_list, node) {
-		if (pwm->pwm_id == pwm_id) {
-			found = 1;
-			break;
-		}
+	if (imx->clk_enabled) {
+		clk_disable_unprepare(imx->clk);
+		imx->clk_enabled = 0;
 	}
-
-	if (found) {
-		if (pwm->use_count == 0) {
-			pwm->use_count++;
-			pwm->label = label;
-		} else
-			pwm = ERR_PTR(-EBUSY);
-	} else
-		pwm = ERR_PTR(-ENOENT);
-
-	mutex_unlock(&pwm_lock);
-	return pwm;
 }
-EXPORT_SYMBOL(pwm_request);
-
-void pwm_free(struct pwm_device *pwm)
-{
-	mutex_lock(&pwm_lock);
-
-	if (pwm->use_count) {
-		pwm->use_count--;
-		pwm->label = NULL;
-	} else
-		pr_warning("PWM device already freed\n");
 
-	mutex_unlock(&pwm_lock);
-}
-EXPORT_SYMBOL(pwm_free);
+static struct pwm_ops imx_pwm_ops = {
+	.enable = imx_pwm_enable,
+	.disable = imx_pwm_disable,
+	.config = imx_pwm_config,
+	.owner = THIS_MODULE,
+};
 
-static int __devinit mxc_pwm_probe(struct platform_device *pdev)
+static int __devinit imx_pwm_probe(struct platform_device *pdev)
 {
-	struct pwm_device *pwm;
+	struct imx_chip *imx;
 	struct resource *r;
 	int ret = 0;
 
-	pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
-	if (pwm == NULL) {
+	imx = kzalloc(sizeof(*imx), GFP_KERNEL);
+	if (imx == NULL) {
 		dev_err(&pdev->dev, "failed to allocate memory\n");
 		return -ENOMEM;
 	}
 
-	pwm->clk = clk_get(&pdev->dev, "pwm");
+	imx->clk = clk_get(&pdev->dev, "pwm");
 
-	if (IS_ERR(pwm->clk)) {
-		ret = PTR_ERR(pwm->clk);
+	if (IS_ERR(imx->clk)) {
+		ret = PTR_ERR(imx->clk);
 		goto err_free;
 	}
 
-	pwm->clk_enabled = 0;
+	imx->chip.ops = &imx_pwm_ops;
+	imx->chip.base = -1;
+	imx->chip.npwm = 1;
 
-	pwm->use_count = 0;
-	pwm->pwm_id = pdev->id;
-	pwm->pdev = pdev;
+	imx->clk_enabled = 0;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
@@ -235,72 +192,75 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev)
 		goto err_free_clk;
 	}
 
-	pwm->mmio_base = ioremap(r->start, resource_size(r));
-	if (pwm->mmio_base == NULL) {
+	imx->mmio_base = ioremap(r->start, resource_size(r));
+	if (imx->mmio_base == NULL) {
 		dev_err(&pdev->dev, "failed to ioremap() registers\n");
 		ret = -ENODEV;
 		goto err_free_mem;
 	}
 
-	mutex_lock(&pwm_lock);
-	list_add_tail(&pwm->node, &pwm_list);
-	mutex_unlock(&pwm_lock);
+	ret = pwmchip_add(&imx->chip);
+	if (ret)
+		goto err_iounmap;
 
-	platform_set_drvdata(pdev, pwm);
+	platform_set_drvdata(pdev, imx);
 	return 0;
 
+err_iounmap:
+	iounmap(imx->mmio_base);
 err_free_mem:
 	release_mem_region(r->start, resource_size(r));
 err_free_clk:
-	clk_put(pwm->clk);
+	clk_put(imx->clk);
 err_free:
-	kfree(pwm);
+	kfree(imx);
 	return ret;
 }
 
-static int __devexit mxc_pwm_remove(struct platform_device *pdev)
+static int __devexit imx_pwm_remove(struct platform_device *pdev)
 {
-	struct pwm_device *pwm;
+	struct imx_chip *imx;
 	struct resource *r;
+	int ret;
 
-	pwm = platform_get_drvdata(pdev);
-	if (pwm == NULL)
+	imx = platform_get_drvdata(pdev);
+	if (imx == NULL)
 		return -ENODEV;
 
-	mutex_lock(&pwm_lock);
-	list_del(&pwm->node);
-	mutex_unlock(&pwm_lock);
+	ret = pwmchip_remove(&imx->chip);
+	if (ret)
+		return ret;
 
-	iounmap(pwm->mmio_base);
+	iounmap(imx->mmio_base);
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	release_mem_region(r->start, resource_size(r));
 
-	clk_put(pwm->clk);
+	clk_put(imx->clk);
 
-	kfree(pwm);
+	kfree(imx);
 	return 0;
 }
 
-static struct platform_driver mxc_pwm_driver = {
+static struct platform_driver imx_pwm_driver = {
 	.driver		= {
 		.name	= "mxc_pwm",
 	},
-	.probe		= mxc_pwm_probe,
-	.remove		= __devexit_p(mxc_pwm_remove),
+	.probe		= imx_pwm_probe,
+	.remove		= __devexit_p(imx_pwm_remove),
 };
 
-static int __init mxc_pwm_init(void)
+static int __init imx_pwm_init(void)
 {
-	return platform_driver_register(&mxc_pwm_driver);
+	return platform_driver_register(&imx_pwm_driver);
 }
-arch_initcall(mxc_pwm_init);
+arch_initcall(imx_pwm_init);
 
-static void __exit mxc_pwm_exit(void)
+static void __exit imx_pwm_exit(void)
 {
-	platform_driver_unregister(&mxc_pwm_driver);
+	platform_driver_unregister(&imx_pwm_driver);
 }
-module_exit(mxc_pwm_exit);
+module_exit(imx_pwm_exit);
 
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de>");
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:52 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:52 +0200
Subject: [PATCH v5 10/16] pwm: Move Blackfin PWM driver to PWM framework
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-11-git-send-email-thierry.reding@avionic-design.de>

This commit moves the Blackfin PWM driver to the drivers/pwm sub-
directory and converts it to register with the new PWM framework.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
 arch/blackfin/Kconfig         |   10 ---
 arch/blackfin/kernel/Makefile |    1 -
 arch/blackfin/kernel/pwm.c    |  100 -------------------------
 drivers/pwm/Kconfig           |    9 +++
 drivers/pwm/Makefile          |    1 +
 drivers/pwm/pwm-bfin.c        |  164 +++++++++++++++++++++++++++++++++++++++++
 6 files changed, 174 insertions(+), 111 deletions(-)
 delete mode 100644 arch/blackfin/kernel/pwm.c
 create mode 100644 drivers/pwm/pwm-bfin.c

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index c1269a1..e08f39b 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -950,16 +950,6 @@ config BFIN_GPTIMERS
 	  To compile this driver as a module, choose M here: the module
 	  will be called gptimers.
 
-config HAVE_PWM
-	tristate "Enable PWM API support"
-	depends on BFIN_GPTIMERS
-	help
-	  Enable support for the Pulse Width Modulation framework (as
-	  found in linux/pwm.h).
-
-	  To compile this driver as a module, choose M here: the module
-	  will be called pwm.
-
 choice
 	prompt "Uncached DMA region"
 	default DMA_UNCACHED_1M
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 9a0d6d7..00fef32 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_FUNCTION_TRACER)        += ftrace-entry.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)  += ftrace.o
 CFLAGS_REMOVE_ftrace.o = -pg
 
-obj-$(CONFIG_HAVE_PWM)               += pwm.o
 obj-$(CONFIG_IPIPE)                  += ipipe.o
 obj-$(CONFIG_BFIN_GPTIMERS)          += gptimers.o
 obj-$(CONFIG_CPLB_INFO)              += cplbinfo.o
diff --git a/arch/blackfin/kernel/pwm.c b/arch/blackfin/kernel/pwm.c
deleted file mode 100644
index 33f5942..0000000
--- a/arch/blackfin/kernel/pwm.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Blackfin Pulse Width Modulation (PWM) core
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/pwm.h>
-#include <linux/slab.h>
-
-#include <asm/gptimers.h>
-#include <asm/portmux.h>
-
-struct pwm_device {
-	unsigned id;
-	unsigned short pin;
-};
-
-static const unsigned short pwm_to_gptimer_per[] = {
-	P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR4, P_TMR5,
-	P_TMR6, P_TMR7, P_TMR8, P_TMR9, P_TMR10, P_TMR11,
-};
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-	struct pwm_device *pwm;
-	int ret;
-
-	/* XXX: pwm_id really should be unsigned */
-	if (pwm_id < 0)
-		return NULL;
-
-	pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
-	if (!pwm)
-		return pwm;
-
-	pwm->id = pwm_id;
-	if (pwm->id >= ARRAY_SIZE(pwm_to_gptimer_per))
-		goto err;
-
-	pwm->pin = pwm_to_gptimer_per[pwm->id];
-	ret = peripheral_request(pwm->pin, label);
-	if (ret)
-		goto err;
-
-	return pwm;
- err:
-	kfree(pwm);
-	return NULL;
-}
-EXPORT_SYMBOL(pwm_request);
-
-void pwm_free(struct pwm_device *pwm)
-{
-	peripheral_free(pwm->pin);
-	kfree(pwm);
-}
-EXPORT_SYMBOL(pwm_free);
-
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
-{
-	unsigned long period, duty;
-	unsigned long long val;
-
-	if (duty_ns < 0 || duty_ns > period_ns)
-		return -EINVAL;
-
-	val = (unsigned long long)get_sclk() * period_ns;
-	do_div(val, NSEC_PER_SEC);
-	period = val;
-
-	val = (unsigned long long)period * duty_ns;
-	do_div(val, period_ns);
-	duty = period - val;
-
-	if (duty >= period)
-		duty = period - 1;
-
-	set_gptimer_config(pwm->id, TIMER_MODE_PWM | TIMER_PERIOD_CNT);
-	set_gptimer_pwidth(pwm->id, duty);
-	set_gptimer_period(pwm->id, period);
-
-	return 0;
-}
-EXPORT_SYMBOL(pwm_config);
-
-int pwm_enable(struct pwm_device *pwm)
-{
-	enable_gptimer(pwm->id);
-	return 0;
-}
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-	disable_gptimer(pwm->id);
-}
-EXPORT_SYMBOL(pwm_disable);
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index bda6f23..eb54042 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -9,6 +9,15 @@ menuconfig PWM
 
 if PWM
 
+config PWM_BFIN
+	tristate "Blackfin PWM support"
+	depends on BFIN_GPTIMERS
+	help
+	  Generic PWM framework driver for Blackfin.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-bfin.
+
 config PWM_TEGRA
 	tristate "NVIDIA Tegra PWM support"
 	depends on ARCH_TEGRA
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 12300f5..251b8d2 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_PWM)		+= core.o
+obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
 obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
diff --git a/drivers/pwm/pwm-bfin.c b/drivers/pwm/pwm-bfin.c
new file mode 100644
index 0000000..a0c6bf9
--- /dev/null
+++ b/drivers/pwm/pwm-bfin.c
@@ -0,0 +1,164 @@
+/*
+ * Blackfin Pulse Width Modulation (PWM) core
+ *
+ * Copyright (c) 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/slab.h>
+
+#include <asm/gptimers.h>
+#include <asm/portmux.h>
+
+struct bfin_pwm_chip {
+	struct pwm_chip chip;
+};
+
+struct bfin_pwm {
+	unsigned short pin;
+};
+
+static const unsigned short pwm_to_gptimer_per[] = {
+	P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR4, P_TMR5,
+	P_TMR6, P_TMR7, P_TMR8, P_TMR9, P_TMR10, P_TMR11,
+};
+
+static int bfin_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct bfin_pwm *priv;
+	int ret;
+
+	if (pwm->hwpwm >= ARRAY_SIZE(pwm_to_gptimer_per))
+		return -EINVAL;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->pin = pwm_to_gptimer_per[pwm->hwpwm];
+
+	ret = peripheral_request(priv->pin, NULL);
+	if (ret) {
+		kfree(priv);
+		return ret;
+	}
+
+	pwm_set_chip_data(pwm, priv);
+
+	return 0;
+}
+
+static void bfin_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct bfin_pwm *priv = pwm_get_chip_data(pwm);
+
+	if (priv) {
+		peripheral_free(priv->pin);
+		kfree(priv);
+	}
+}
+
+static int bfin_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+		int duty_ns, int period_ns)
+{
+	struct bfin_pwm *priv = pwm_get_chip_data(pwm);
+	unsigned long period, duty;
+	unsigned long long val;
+
+	if (duty_ns < 0 || duty_ns > period_ns)
+		return -EINVAL;
+
+	val = (unsigned long long)get_sclk() * period_ns;
+	do_div(val, NSEC_PER_SEC);
+	period = val;
+
+	val = (unsigned long long)period * duty_ns;
+	do_div(val, period_ns);
+	duty = period - val;
+
+	if (duty >= period)
+		duty = period - 1;
+
+	set_gptimer_config(priv->pin, TIMER_MODE_PWM | TIMER_PERIOD_CNT);
+	set_gptimer_pwidth(priv->pin, duty);
+	set_gptimer_period(priv->pin, period);
+
+	return 0;
+}
+
+static int bfin_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct bfin_pwm *priv = pwm_get_chip_data(pwm);
+
+	enable_gptimer(priv->pin);
+
+	return 0;
+}
+
+static void bfin_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct bfin_pwm *priv = pwm_get_chip_data(pwm);
+
+	disable_gptimer(priv->pin);
+}
+
+static struct pwm_ops bfin_pwm_ops = {
+	.request = bfin_pwm_request,
+	.free = bfin_pwm_free,
+	.config = bfin_pwm_config,
+	.enable = bfin_pwm_enable,
+	.disable = bfin_pwm_disable,
+	.owner = THIS_MODULE,
+};
+
+static int bfin_pwm_probe(struct platform_device *pdev)
+{
+	struct bfin_pwm_chip *pwm;
+	int ret;
+
+	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
+	if (!pwm) {
+		dev_err(&pdev->dev, "failed to allocate memory\n");
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, pwm);
+
+	pwm->chip.dev = &pdev->dev;
+	pwm->chip.ops = &bfin_pwm_ops;
+	pwm->chip.base = -1;
+	pwm->chip.npwm = 12;
+
+	ret = pwmchip_add(&pwm->chip);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __devexit bfin_pwm_remove(struct platform_device *pdev)
+{
+	struct bfin_pwm_chip *pwm = platform_get_drvdata(pdev);
+
+	pwmchip_remove(&pwm->chip);
+
+	return 0;
+}
+
+static struct platform_driver bfin_pwm_driver = {
+	.driver = {
+		.name = "bfin-pwm",
+	},
+	.probe = bfin_pwm_probe,
+	.remove = __devexit_p(bfin_pwm_remove),
+};
+
+module_platform_driver(bfin_pwm_driver);
+
+MODULE_LICENSE("GPL");
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:50 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:50 +0200
Subject: [PATCH v5 08/16] pwm: Add NVIDIA Tegra SoC support
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-9-git-send-email-thierry.reding@avionic-design.de>

This commit adds a generic PWM framework driver for the PWFM controller
found on NVIDIA Tegra SoCs. The driver is based on code from the
Chromium kernel tree and was originally written by Gary King (NVIDIA)
and later modified by Simon Que (Chromium).

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v5:
- use devm_request_and_ioremap()
- use clk_prepare_enable() and clk_disable_unprepare()
- call pwmchip_remove() after disabling PWM devices
- remove tegra_pwm_chip.enable[] field and use the PWM flags instead
- use pwm_readl()/pwm_writel() for register accesses and split out clock
  management to where it's needed
- add MODULE_ALIAS to enable automatic module loading

Changes in v4:
- merge patch from ChromiumOS kernel to fix a rounding issue
- move DT code to patch 7

Changes in v3:
- use pwm_device.hwpwm instead of recomputing it
- update pwm_ops for changes in patch 2

Changes in v2:
- set pwm_chip.dev field
- rename clk_enb to enable
- introduce NUM_PWM macro instead of hard-coding the number of PWM
  devices
- update comment in tegra_pwm_config
- fix coding-style for multi-line comments
- use module_platform_driver
- change license to GPL

 drivers/pwm/Kconfig     |   10 ++
 drivers/pwm/Makefile    |    1 +
 drivers/pwm/pwm-tegra.c |  254 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 265 insertions(+)
 create mode 100644 drivers/pwm/pwm-tegra.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 93c1052..bda6f23 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -9,4 +9,14 @@ menuconfig PWM
 
 if PWM
 
+config PWM_TEGRA
+	tristate "NVIDIA Tegra PWM support"
+	depends on ARCH_TEGRA
+	help
+	  Generic PWM framework driver for the PWFM controller found on NVIDIA
+	  Tegra SoCs.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-tegra.
+
 endif
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 3469c3d..12300f5 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_PWM)		+= core.o
+obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
new file mode 100644
index 0000000..2219be1
--- /dev/null
+++ b/drivers/pwm/pwm-tegra.c
@@ -0,0 +1,254 @@
+/*
+ * drivers/pwm/pwm-tegra.c
+ *
+ * Tegra pulse-width-modulation controller driver
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pwm.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#define PWM_ENABLE	(1 << 31)
+#define PWM_DUTY_WIDTH	8
+#define PWM_DUTY_SHIFT	16
+#define PWM_SCALE_WIDTH	13
+#define PWM_SCALE_SHIFT	0
+
+#define NUM_PWM 4
+
+struct tegra_pwm_chip {
+	struct pwm_chip		chip;
+	struct device		*dev;
+
+	struct clk		*clk;
+
+	void __iomem		*mmio_base;
+};
+
+static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
+{
+	return container_of(chip, struct tegra_pwm_chip, chip);
+}
+
+static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
+{
+	return readl(chip->mmio_base + (num << 4));
+}
+
+static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
+			     unsigned long val)
+{
+	writel(val, chip->mmio_base + (num << 4));
+}
+
+static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+			    int duty_ns, int period_ns)
+{
+	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
+	unsigned long long c;
+	unsigned long rate, hz;
+	u32 val = 0;
+	int err;
+
+	/*
+	 * Convert from duty_ns / period_ns to a fixed number of duty ticks
+	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
+	 * nearest integer during division.
+	 */
+	c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
+	do_div(c, period_ns);
+
+	val = (u32)c << PWM_DUTY_SHIFT;
+
+	/*
+	 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
+	 * cycles at the PWM clock rate will take period_ns nanoseconds.
+	 */
+	rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
+	hz = 1000000000ul / period_ns;
+
+	rate = (rate + (hz / 2)) / hz;
+
+	/*
+	 * Since the actual PWM divider is the register's frequency divider
+	 * field minus 1, we need to decrement to get the correct value to
+	 * write to the register.
+	 */
+	if (rate > 0)
+		rate--;
+
+	/*
+	 * Make sure that the rate will fit in the register's frequency
+	 * divider field.
+	 */
+	if (rate >> PWM_SCALE_WIDTH)
+		return -EINVAL;
+
+	val |= rate << PWM_SCALE_SHIFT;
+
+	/*
+	 * If the PWM channel is disabled, make sure to turn on the clock
+	 * before writing the register. Otherwise, keep it enabled.
+	 */
+	if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
+		err = clk_prepare_enable(pc->clk);
+		if (err < 0)
+			return err;
+	} else
+		val |= PWM_ENABLE;
+
+	pwm_writel(pc, pwm->hwpwm, val);
+
+	/*
+	 * If the PWM is not enabled, turn the clock off again to save power.
+	 */
+	if (!test_bit(PWMF_ENABLED, &pwm->flags))
+		clk_disable_unprepare(pc->clk);
+
+	return 0;
+}
+
+static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
+	int rc = 0;
+	u32 val;
+
+	rc = clk_prepare_enable(pc->clk);
+	if (rc < 0)
+		return rc;
+
+	val = pwm_readl(pc, pwm->hwpwm);
+	val |= PWM_ENABLE;
+	pwm_writel(pc, pwm->hwpwm, val);
+
+	return 0;
+}
+
+static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
+	u32 val;
+
+	val = pwm_readl(pc, pwm->hwpwm);
+	val &= ~PWM_ENABLE;
+	pwm_writel(pc, pwm->hwpwm, val);
+
+	clk_disable_unprepare(pc->clk);
+}
+
+static struct pwm_ops tegra_pwm_ops = {
+	.config = tegra_pwm_config,
+	.enable = tegra_pwm_enable,
+	.disable = tegra_pwm_disable,
+	.owner = THIS_MODULE,
+};
+
+static int tegra_pwm_probe(struct platform_device *pdev)
+{
+	struct tegra_pwm_chip *pwm;
+	struct resource *r;
+	int ret;
+
+	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
+	if (!pwm) {
+		dev_err(&pdev->dev, "failed to allocate memory\n");
+		return -ENOMEM;
+	}
+
+	pwm->dev = &pdev->dev;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r) {
+		dev_err(&pdev->dev, "no memory resources defined\n");
+		return -ENODEV;
+	}
+
+	pwm->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
+	if (!pwm->mmio_base) {
+		dev_err(&pdev->dev, "failed to ioremap() region\n");
+		return -ENODEV;
+	}
+
+	platform_set_drvdata(pdev, pwm);
+
+	pwm->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(pwm->clk))
+		return PTR_ERR(pwm->clk);
+
+	pwm->chip.dev = &pdev->dev;
+	pwm->chip.ops = &tegra_pwm_ops;
+	pwm->chip.base = -1;
+	pwm->chip.npwm = NUM_PWM;
+
+	ret = pwmchip_add(&pwm->chip);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
+		clk_put(pwm->clk);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int __devexit tegra_pwm_remove(struct platform_device *pdev)
+{
+	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
+	int i;
+
+	if (WARN_ON(!pc))
+		return -ENODEV;
+
+	for (i = 0; i < NUM_PWM; i++) {
+		struct pwm_device *pwm = &pc->chip.pwms[i];
+
+		if (!test_bit(PWMF_ENABLED, &pwm->flags))
+			if (clk_prepare_enable(pc->clk) < 0)
+				continue;
+
+		pwm_writel(pc, i, 0);
+
+		clk_disable_unprepare(pc->clk);
+	}
+
+	pwmchip_remove(&pc->chip);
+	clk_put(pc->clk);
+
+	return 0;
+}
+
+static struct platform_driver tegra_pwm_driver = {
+	.driver = {
+		.name = "tegra-pwm",
+	},
+	.probe = tegra_pwm_probe,
+	.remove = __devexit_p(tegra_pwm_remove),
+};
+
+module_platform_driver(tegra_pwm_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("NVIDIA Corporation");
+MODULE_ALIAS("platform:tegra-pwm");
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:44 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:44 +0200
Subject: [PATCH v5 02/16] pwm: Allow chips to support multiple PWMs
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-3-git-send-email-thierry.reding@avionic-design.de>

Many PWM controllers provide access to more than a single PWM output and
may even share some resource among them. Allowing a PWM chip to provide
multiple PWM devices enables better sharing of those resources. As a
side-effect this change allows easy integration with the device tree
where a given PWM can be looked up based on the PWM chip's phandle and a
corresponding index.

This commit modifies the PWM core to support multiple PWMs per struct
pwm_chip. It achieves this in a similar way to how gpiolib works, by
allowing PWM ranges to be requested dynamically (pwm_chip.base == -1) or
starting at a given offset (pwm_chip.base >= 0). A chip specifies how
many PWMs it controls using the npwm member. Each of the functions in
the pwm_ops structure gets an additional argument that specified the PWM
number (it can be converted to a per-chip index by subtracting the
chip's base).

The total maximum number of PWM devices is currently fixed to 1024 while
the data is actually stored in a radix tree, thus saving resources if
not all of them are used.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v5:
- add sanity checks to pwmchip_add()
- make pwm_chip.pwm_ops constant
- remove unused pwm_request_from_device() function
- check for valid chip in pwm_request_from_chip()
- add sanity checks to pwm_config(), pwm_enable() and pwm_disable()
- update Documentation/pwm.txt
- use deferred driver probing if pwm_request() cannot find a PWM

Changes in v4:
- remove OF-specific code to preserve bisectability
- add pwm_request_from_device() and pwm_request_from_chip() functions
- refactor PWM requesting code
- store period in struct pwm_device and get rid of the unused struct
  pwm_spec

Changes in v3:
- get rid of pwm_desc structure and keep only struct pwm_device
- keep a list of pwm_chip structures for fast and easy lookup
- pass struct pwm_device directly to pwm_ops
- add debugfs file

Changes in v2:
- add 'struct device *dev' field to pwm_chip, drop label field
- use radix tree for PWM descriptors
- add pwm_set_chip_data() and pwm_get_chip_data() functions to allow
  storing and retrieving chip-specific per-PWM data

 Documentation/pwm.txt |    9 +-
 drivers/pwm/core.c    |  263 ++++++++++++++++++++++++++++++++++---------------
 include/linux/pwm.h   |   71 ++++++++++---
 3 files changed, 250 insertions(+), 93 deletions(-)

diff --git a/Documentation/pwm.txt b/Documentation/pwm.txt
index 03e39d1..48f598a 100644
--- a/Documentation/pwm.txt
+++ b/Documentation/pwm.txt
@@ -33,9 +33,12 @@ there only has been the barebone API meaning that each driver has
 to implement the pwm_*() functions itself. This means that it's impossible
 to have multiple PWM drivers in the system. For this reason it's mandatory
 for new drivers to use the generic PWM framework.
-A new PWM device can be added using pwmchip_add() and removed again with
-pwmchip_remove(). pwmchip_add() takes a filled in struct pwm_chip as
-argument which provides the ops and the pwm id to the framework.
+
+A new PWM controller/chip can be added using pwmchip_add() and removed
+again with pwmchip_remove(). pwmchip_add() takes a filled in struct
+pwm_chip as argument which provides a description of the PWM chip, the
+number of PWM devices provider by the chip and the chip-specific
+implementation of the supported PWM operations to the framework.
 
 Locking
 -------
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index db2f048..46dcbe1 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -2,6 +2,7 @@
  * Generic pwmlib implementation
  *
  * Copyright (C) 2011 Sascha Hauer <s.hauer at pengutronix.de>
+ * Copyright (C) 2011-2012 Avionic Design GmbH
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -20,66 +21,157 @@
 
 #include <linux/module.h>
 #include <linux/pwm.h>
+#include <linux/radix-tree.h>
 #include <linux/list.h>
 #include <linux/mutex.h>
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/device.h>
 
-struct pwm_device {
-	struct			pwm_chip *chip;
-	const char		*label;
-	unsigned long		flags;
-#define FLAG_REQUESTED	0
-#define FLAG_ENABLED	1
-	struct list_head	node;
-};
-
-static LIST_HEAD(pwm_list);
+#define MAX_PWMS 1024
 
 static DEFINE_MUTEX(pwm_lock);
+static LIST_HEAD(pwm_chips);
+static DECLARE_BITMAP(allocated_pwms, MAX_PWMS);
+static RADIX_TREE(pwm_tree, GFP_KERNEL);
 
-static struct pwm_device *_find_pwm(int pwm_id)
+static struct pwm_device *pwm_to_device(unsigned int pwm)
 {
-	struct pwm_device *pwm;
+	return radix_tree_lookup(&pwm_tree, pwm);
+}
+
+static int alloc_pwms(int pwm, unsigned int count)
+{
+	unsigned int from = 0;
+	unsigned int start;
+
+	if (pwm >= MAX_PWMS)
+		return -EINVAL;
+
+	if (pwm >= 0)
+		from = pwm;
+
+	start = bitmap_find_next_zero_area(allocated_pwms, MAX_PWMS, from,
+					   count, 0);
+
+	if (pwm >= 0 && start != pwm)
+		return -EEXIST;
+
+	if (start + count > MAX_PWMS)
+		return -ENOSPC;
+
+	return start;
+}
 
-	list_for_each_entry(pwm, &pwm_list, node) {
-		if (pwm->chip->pwm_id == pwm_id)
-			return pwm;
+static void free_pwms(struct pwm_chip *chip)
+{
+	unsigned int i;
+
+	for (i = 0; i < chip->npwm; i++) {
+		struct pwm_device *pwm = &chip->pwms[i];
+		radix_tree_delete(&pwm_tree, pwm->pwm);
+	}
+
+	bitmap_clear(allocated_pwms, chip->base, chip->npwm);
+
+	kfree(chip->pwms);
+	chip->pwms = NULL;
+}
+
+static int pwm_device_request(struct pwm_device *pwm, const char *label)
+{
+	int err;
+
+	if (test_bit(PWMF_REQUESTED, &pwm->flags))
+		return -EBUSY;
+
+	if (!try_module_get(pwm->chip->ops->owner))
+		return -ENODEV;
+
+	if (pwm->chip->ops->request) {
+		err = pwm->chip->ops->request(pwm->chip, pwm);
+		if (err) {
+			module_put(pwm->chip->ops->owner);
+			return err;
+		}
 	}
 
-	return NULL;
+	set_bit(PWMF_REQUESTED, &pwm->flags);
+	pwm->label = label;
+
+	return 0;
+}
+
+/**
+ * pwm_set_chip_data() - set private chip data for a PWM
+ * @pwm: PWM device
+ * @data: pointer to chip-specific data
+ */
+int pwm_set_chip_data(struct pwm_device *pwm, void *data)
+{
+	if (!pwm)
+		return -EINVAL;
+
+	pwm->chip_data = data;
+
+	return 0;
+}
+
+/**
+ * pwm_get_chip_data() - get private chip data for a PWM
+ * @pwm: PWM device
+ */
+void *pwm_get_chip_data(struct pwm_device *pwm)
+{
+	return pwm ? pwm->chip_data : NULL;
 }
 
 /**
  * pwmchip_add() - register a new PWM chip
  * @chip: the PWM chip to add
+ *
+ * Register a new PWM chip. If chip->base < 0 then a dynamically assigned base
+ * will be used.
  */
 int pwmchip_add(struct pwm_chip *chip)
 {
 	struct pwm_device *pwm;
-	int ret = 0;
-
-	pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
-	if (!pwm)
-		return -ENOMEM;
+	unsigned int i;
+	int ret;
 
-	pwm->chip = chip;
+	if (!chip || !chip->dev || !chip->ops || !chip->ops->config ||
+	    !chip->ops->enable || !chip->ops->disable)
+		return -EINVAL;
 
 	mutex_lock(&pwm_lock);
 
-	if (chip->pwm_id >= 0 && _find_pwm(chip->pwm_id)) {
-		ret = -EBUSY;
+	ret = alloc_pwms(chip->base, chip->npwm);
+	if (ret < 0)
 		goto out;
+
+	chip->pwms = kzalloc(chip->npwm * sizeof(*pwm), GFP_KERNEL);
+	if (!chip->pwms)
+		return -ENOMEM;
+
+	chip->base = ret;
+
+	for (i = 0; i < chip->npwm; i++) {
+		pwm = &chip->pwms[i];
+
+		pwm->chip = chip;
+		pwm->pwm = chip->base + i;
+		pwm->hwpwm = i;
+
+		radix_tree_insert(&pwm_tree, pwm->pwm, pwm);
 	}
 
-	list_add_tail(&pwm->node, &pwm_list);
-out:
-	mutex_unlock(&pwm_lock);
+	bitmap_set(allocated_pwms, chip->base, chip->npwm);
 
-	if (ret)
-		kfree(pwm);
+	INIT_LIST_HEAD(&chip->list);
+	list_add(&chip->list, &pwm_chips);
 
+out:
+	mutex_unlock(&pwm_lock);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(pwmchip_add);
@@ -93,28 +185,25 @@ EXPORT_SYMBOL_GPL(pwmchip_add);
  */
 int pwmchip_remove(struct pwm_chip *chip)
 {
-	struct pwm_device *pwm;
+	unsigned int i;
 	int ret = 0;
 
 	mutex_lock(&pwm_lock);
 
-	pwm = _find_pwm(chip->pwm_id);
-	if (!pwm) {
-		ret = -ENOENT;
-		goto out;
-	}
+	for (i = 0; i < chip->npwm; i++) {
+		struct pwm_device *pwm = &chip->pwms[i];
 
-	if (test_bit(FLAG_REQUESTED, &pwm->flags)) {
-		ret = -EBUSY;
-		goto out;
+		if (test_bit(PWMF_REQUESTED, &pwm->flags)) {
+			ret = -EBUSY;
+			goto out;
+		}
 	}
 
-	list_del(&pwm->node);
+	list_del_init(&chip->list);
+	free_pwms(chip);
 
-	kfree(pwm);
 out:
 	mutex_unlock(&pwm_lock);
-
 	return ret;
 }
 EXPORT_SYMBOL_GPL(pwmchip_remove);
@@ -124,50 +213,64 @@ EXPORT_SYMBOL_GPL(pwmchip_remove);
  * @pwm: global PWM device index
  * @label: PWM device label
  */
-struct pwm_device *pwm_request(int pwm_id, const char *label)
+struct pwm_device *pwm_request(int pwm, const char *label)
 {
-	struct pwm_device *pwm;
-	int ret;
+	struct pwm_device *dev;
+	int err;
+
+	if (pwm < 0 || pwm >= MAX_PWMS)
+		return ERR_PTR(-EINVAL);
 
 	mutex_lock(&pwm_lock);
 
-	pwm = _find_pwm(pwm_id);
-	if (!pwm) {
-		pwm = ERR_PTR(-ENOENT);
+	dev = pwm_to_device(pwm);
+	if (!dev) {
+		dev = ERR_PTR(-EPROBE_DEFER);
 		goto out;
 	}
 
-	if (test_bit(FLAG_REQUESTED, &pwm->flags)) {
-		pwm = ERR_PTR(-EBUSY);
-		goto out;
-	}
+	err = pwm_device_request(dev, label);
+	if (err < 0)
+		dev = ERR_PTR(err);
 
-	if (!try_module_get(pwm->chip->ops->owner)) {
-		pwm = ERR_PTR(-ENODEV);
-		goto out;
-	}
+out:
+	mutex_unlock(&pwm_lock);
 
-	if (pwm->chip->ops->request) {
-		ret = pwm->chip->ops->request(pwm->chip);
-		if (ret) {
-			pwm = ERR_PTR(ret);
-			goto out_put;
-		}
-	}
+	return dev;
+}
+EXPORT_SYMBOL_GPL(pwm_request);
 
-	pwm->label = label;
-	set_bit(FLAG_REQUESTED, &pwm->flags);
+/**
+ * pwm_request_from_chip() - request a PWM device relative to a PWM chip
+ * @chip: PWM chip
+ * @index: per-chip index of the PWM to request
+ * @label: a literal description string of this PWM
+ *
+ * Returns the PWM at the given index of the given PWM chip. A negative error
+ * code is returned if the index is not valid for the specified PWM chip or
+ * if the PWM device cannot be requested.
+ */
+struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip,
+					 unsigned int index,
+					 const char *label)
+{
+	struct pwm_device *pwm;
+	int err;
 
-	goto out;
+	if (!chip || index >= chip->npwm)
+		return ERR_PTR(-EINVAL);
 
-out_put:
-	module_put(pwm->chip->ops->owner);
-out:
-	mutex_unlock(&pwm_lock);
+	mutex_lock(&pwm_lock);
+	pwm = &chip->pwms[index];
 
+	err = pwm_device_request(pwm, label);
+	if (err < 0)
+		pwm = ERR_PTR(err);
+
+	mutex_unlock(&pwm_lock);
 	return pwm;
 }
-EXPORT_SYMBOL_GPL(pwm_request);
+EXPORT_SYMBOL_GPL(pwm_request_from_chip);
 
 /**
  * pwm_free() - free a PWM device
@@ -177,11 +280,14 @@ void pwm_free(struct pwm_device *pwm)
 {
 	mutex_lock(&pwm_lock);
 
-	if (!test_and_clear_bit(FLAG_REQUESTED, &pwm->flags)) {
+	if (!test_and_clear_bit(PWMF_REQUESTED, &pwm->flags)) {
 		pr_warning("PWM device already freed\n");
 		goto out;
 	}
 
+	if (pwm->chip->ops->free)
+		pwm->chip->ops->free(pwm->chip, pwm);
+
 	pwm->label = NULL;
 
 	module_put(pwm->chip->ops->owner);
@@ -198,7 +304,10 @@ EXPORT_SYMBOL_GPL(pwm_free);
  */
 int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 {
-	return pwm->chip->ops->config(pwm->chip, duty_ns, period_ns);
+	if (!pwm || period_ns == 0 || duty_ns > period_ns)
+		return -EINVAL;
+
+	return pwm->chip->ops->config(pwm->chip, pwm, duty_ns, period_ns);
 }
 EXPORT_SYMBOL_GPL(pwm_config);
 
@@ -208,10 +317,10 @@ EXPORT_SYMBOL_GPL(pwm_config);
  */
 int pwm_enable(struct pwm_device *pwm)
 {
-	if (!test_and_set_bit(FLAG_ENABLED, &pwm->flags))
-		return pwm->chip->ops->enable(pwm->chip);
+	if (pwm && !test_and_set_bit(PWMF_ENABLED, &pwm->flags))
+		return pwm->chip->ops->enable(pwm->chip, pwm);
 
-	return 0;
+	return pwm ? 0 : -EINVAL;
 }
 EXPORT_SYMBOL_GPL(pwm_enable);
 
@@ -221,7 +330,7 @@ EXPORT_SYMBOL_GPL(pwm_enable);
  */
 void pwm_disable(struct pwm_device *pwm)
 {
-	if (test_and_clear_bit(FLAG_ENABLED, &pwm->flags))
-		pwm->chip->ops->disable(pwm->chip);
+	if (pwm && test_and_clear_bit(PWMF_ENABLED, &pwm->flags))
+		pwm->chip->ops->disable(pwm->chip, pwm);
 }
 EXPORT_SYMBOL_GPL(pwm_disable);
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index 4bad29c..5710391 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -31,6 +31,33 @@ void pwm_disable(struct pwm_device *pwm);
 #ifdef CONFIG_PWM
 struct pwm_chip;
 
+enum {
+	PWMF_REQUESTED = 1 << 0,
+	PWMF_ENABLED = 1 << 1,
+};
+
+struct pwm_device {
+	const char		*label;
+	unsigned long		flags;
+	unsigned int		hwpwm;
+	unsigned int		pwm;
+	struct pwm_chip		*chip;
+	void			*chip_data;
+
+	unsigned int		period; /* in nanoseconds */
+};
+
+static inline void pwm_set_period(struct pwm_device *pwm, unsigned int period)
+{
+	if (pwm)
+		pwm->period = period;
+}
+
+static inline unsigned int pwm_get_period(struct pwm_device *pwm)
+{
+	return pwm ? pwm->period : 0;
+}
+
 /**
  * struct pwm_ops - PWM controller operations
  * @request: optional hook for requesting a PWM
@@ -41,29 +68,47 @@ struct pwm_chip;
  * @owner: helps prevent removal of modules exporting active PWMs
  */
 struct pwm_ops {
-	int			(*request)(struct pwm_chip *chip);
-	void			(*free)(struct pwm_chip *chip);
-	int			(*config)(struct pwm_chip *chip, int duty_ns,
-						int period_ns);
-	int			(*enable)(struct pwm_chip *chip);
-	void			(*disable)(struct pwm_chip *chip);
+	int			(*request)(struct pwm_chip *chip,
+					   struct pwm_device *pwm);
+	void			(*free)(struct pwm_chip *chip,
+					struct pwm_device *pwm);
+	int			(*config)(struct pwm_chip *chip,
+					  struct pwm_device *pwm,
+					  int duty_ns, int period_ns);
+	int			(*enable)(struct pwm_chip *chip,
+					  struct pwm_device *pwm);
+	void			(*disable)(struct pwm_chip *chip,
+					   struct pwm_device *pwm);
 	struct module		*owner;
 };
 
 /**
- * struct pwm_chip - abstract a PWM
- * @label: for diagnostics
- * @owner: helps prevent removal of modules exporting active PWMs
- * @ops: The callbacks for this PWM
+ * struct pwm_chip - abstract a PWM controller
+ * @dev: device providing the PWMs
+ * @list: list node for internal use
+ * @ops: callbacks for this PWM controller
+ * @base: number of first PWM controlled by this chip
+ * @npwm: number of PWMs controlled by this chip
+ * @pwms: array of PWM devices allocated by the framework
  */
 struct pwm_chip {
-	int			pwm_id;
-	const char		*label;
-	struct pwm_ops		*ops;
+	struct device		*dev;
+	struct list_head	list;
+	const struct pwm_ops	*ops;
+	int			base;
+	unsigned int		npwm;
+
+	struct pwm_device	*pwms;
 };
 
+int pwm_set_chip_data(struct pwm_device *pwm, void *data);
+void *pwm_get_chip_data(struct pwm_device *pwm);
+
 int pwmchip_add(struct pwm_chip *chip);
 int pwmchip_remove(struct pwm_chip *chip);
+struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip,
+					 unsigned int index,
+					 const char *label);
 #endif
 
 #endif /* __LINUX_PWM_H */
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:46 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:46 +0200
Subject: [PATCH v5 04/16] pwm: Add table-based lookup for static mappings
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-5-git-send-email-thierry.reding@avionic-design.de>

In order to get rid of the global namespace for PWM devices, this commit
provides an alternative method, similar to that of the regulator or
clock frameworks, for registering a static mapping for PWM devices. This
works by providing a table with a provider/consumer map in the board
setup code.

With the new pwm_get() and pwm_put() functions available, usage of
pwm_request() and pwm_free() becomes deprecated.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v5:
- new patch with table-based lookup for statically registered devices
- update Documentation/pwm.txt

 Documentation/pwm.txt |   27 +++++++--
 drivers/pwm/core.c    |  152 ++++++++++++++++++++++++++++++++++++++++++++-----
 include/linux/pwm.h   |   20 +++++++
 3 files changed, 180 insertions(+), 19 deletions(-)

diff --git a/Documentation/pwm.txt b/Documentation/pwm.txt
index 48f598a..bb3d2f9 100644
--- a/Documentation/pwm.txt
+++ b/Documentation/pwm.txt
@@ -12,14 +12,33 @@ this kind of flexibility the generic PWM API exists.
 Identifying PWMs
 ----------------
 
-Users of the legacy PWM API use unique IDs to refer to PWM devices. One
-goal of the new PWM framework is to get rid of this global namespace.
+Users of the legacy PWM API use unique IDs to refer to PWM devices.
+
+Instead of referring to a PWM device via its unique ID, board setup code
+should instead register a static mapping that can be used to match PWM
+consumers to providers, as given in the following example:
+
+	static struct pwm_lookup board_pwm_lookup[] = {
+		PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight"),
+	};
+
+	static void __init board_init(void)
+	{
+		...
+		pwm_add_table(board_pwm_lookup, ARRAY_SIZE(board_pwm_lookup));
+		...
+	}
 
 Using PWMs
 ----------
 
-A PWM can be requested using pwm_request() and freed after usage with
-pwm_free(). After being requested a PWM has to be configured using
+Legacy users can request a PWM device using pwm_request() and free it
+after usage with pwm_free().
+
+New users should use the pwm_get() function and pass to it the consumer
+device or a consumer name. pwm_put() is used to free the PWM device.
+
+After being requested a PWM has to be configured using:
 
 int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
 
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 12a643d..77961e0 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -32,6 +32,8 @@
 
 #define MAX_PWMS 1024
 
+static DEFINE_MUTEX(pwm_lookup_lock);
+static LIST_HEAD(pwm_lookup_list);
 static DEFINE_MUTEX(pwm_lock);
 static LIST_HEAD(pwm_chips);
 static DECLARE_BITMAP(allocated_pwms, MAX_PWMS);
@@ -80,6 +82,29 @@ static void free_pwms(struct pwm_chip *chip)
 	chip->pwms = NULL;
 }
 
+static struct pwm_chip *pwmchip_find_by_name(const char *name)
+{
+	struct pwm_chip *chip;
+
+	if (!name)
+		return NULL;
+
+	mutex_lock(&pwm_lock);
+
+	list_for_each_entry(chip, &pwm_chips, list) {
+		const char *chip_name = dev_name(chip->dev);
+
+		if (chip_name && strcmp(chip_name, name) == 0) {
+			mutex_unlock(&pwm_lock);
+			return chip;
+		}
+	}
+
+	mutex_unlock(&pwm_lock);
+
+	return NULL;
+}
+
 static int pwm_device_request(struct pwm_device *pwm, const char *label)
 {
 	int err;
@@ -214,6 +239,8 @@ EXPORT_SYMBOL_GPL(pwmchip_remove);
  * pwm_request() - request a PWM device
  * @pwm: global PWM device index
  * @label: PWM device label
+ *
+ * This function is deprecated, use pwm_get() instead.
  */
 struct pwm_device *pwm_request(int pwm, const char *label)
 {
@@ -277,24 +304,12 @@ EXPORT_SYMBOL_GPL(pwm_request_from_chip);
 /**
  * pwm_free() - free a PWM device
  * @pwm: PWM device
+ *
+ * This function is deprecated, use pwm_put() instead.
  */
 void pwm_free(struct pwm_device *pwm)
 {
-	mutex_lock(&pwm_lock);
-
-	if (!test_and_clear_bit(PWMF_REQUESTED, &pwm->flags)) {
-		pr_warning("PWM device already freed\n");
-		goto out;
-	}
-
-	if (pwm->chip->ops->free)
-		pwm->chip->ops->free(pwm->chip, pwm);
-
-	pwm->label = NULL;
-
-	module_put(pwm->chip->ops->owner);
-out:
-	mutex_unlock(&pwm_lock);
+	pwm_put(pwm);
 }
 EXPORT_SYMBOL_GPL(pwm_free);
 
@@ -337,6 +352,113 @@ void pwm_disable(struct pwm_device *pwm)
 }
 EXPORT_SYMBOL_GPL(pwm_disable);
 
+/**
+ * pwm_add_table() - register PWM device consumers
+ * @table: array of consumers to register
+ * @num: number of consumers in table
+ */
+void __init pwm_add_table(struct pwm_lookup *table, size_t num)
+{
+	mutex_lock(&pwm_lookup_lock);
+
+	while (num--) {
+		if (table->provider && table->consumer)
+			list_add_tail(&table->list, &pwm_lookup_list);
+		else
+			pr_err("%s(): provider/consumer must be specified\n",
+			       __func__);
+
+		table++;
+	}
+
+	mutex_unlock(&pwm_lookup_lock);
+}
+
+/**
+ * pwm_get() - look up and request a PWM device
+ * @dev: device for PWM consumer
+ * @provider: name of provider PWM chip
+ * @index: per-chip index of PWM to request
+ *
+ * Look up a PWM chip and a relative index via a table supplied by board setup
+ * code (see pwm_add_table()).
+ *
+ * Once a PWM chip has been found the specified PWM device will be requested
+ * and is ready to be used.
+ */
+struct pwm_device *pwm_get(struct device *dev, const char *consumer)
+{
+	const char *device_name = dev ? dev_name(dev): NULL;
+	struct pwm_device *pwm = ERR_PTR(-EPROBE_DEFER);
+	struct pwm_chip *chip = NULL;
+	struct pwm_lookup *p;
+	unsigned int index;
+
+	/*
+	 * We look up the provider in the static table typically provided by
+	 * board setup code. We first try to lookup the consumer device by
+	 * name. If the consumer device was passed in as NULL or if no match
+	 * was found, we try to find the consumer by directly looking it up
+	 * by name.
+	 *
+	 * If a match is found, the provider PWM chip is looked up by name
+	 * and a PWM device is requested using the PWM device per-chip index.
+	 */
+	mutex_lock(&pwm_lookup_lock);
+
+	if (device_name)
+		list_for_each_entry(p, &pwm_lookup_list, list)
+			if (strcmp(p->consumer, device_name) == 0) {
+				chip = pwmchip_find_by_name(p->provider);
+				consumer = device_name;
+				index = p->index;
+				break;
+			}
+
+	if (!chip && consumer)
+		list_for_each_entry(p, &pwm_lookup_list, list)
+			if (strcmp(p->consumer, consumer) == 0) {
+				chip = pwmchip_find_by_name(p->provider);
+				index = p->index;
+				break;
+			}
+
+	if (chip)
+		pwm = pwm_request_from_chip(chip, index, consumer);
+
+	mutex_unlock(&pwm_lookup_lock);
+
+	return pwm;
+}
+EXPORT_SYMBOL_GPL(pwm_get);
+
+/**
+ * pwm_put() - release a PWM device
+ * @pwm: PWM device
+ */
+void pwm_put(struct pwm_device *pwm)
+{
+	if (!pwm)
+		return;
+
+	mutex_lock(&pwm_lock);
+
+	if (!test_and_clear_bit(PWMF_REQUESTED, &pwm->flags)) {
+		pr_warning("PWM device already freed\n");
+		goto out;
+	}
+
+	if (pwm->chip->ops->free)
+		pwm->chip->ops->free(pwm->chip, pwm);
+
+	pwm->label = NULL;
+
+	module_put(pwm->chip->ops->owner);
+out:
+	mutex_unlock(&pwm_lock);
+}
+EXPORT_SYMBOL_GPL(pwm_put);
+
 #ifdef CONFIG_DEBUG_FS
 static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s)
 {
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index 047cd53..a32d2b7 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -115,6 +115,26 @@ int pwmchip_remove(struct pwm_chip *chip);
 struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip,
 					 unsigned int index,
 					 const char *label);
+
+struct pwm_device *pwm_get(struct device *dev, const char *consumer);
+void pwm_put(struct pwm_device *pwm);
+
+struct pwm_lookup {
+	struct list_head list;
+	const char *provider;
+	unsigned int index;
+	const char *consumer;
+};
+
+#define PWM_LOOKUP(_provider, _index, _consumer)	\
+	{						\
+		.provider = _provider,			\
+		.index = _index,			\
+		.consumer = _consumer,			\
+	}
+
+void pwm_add_table(struct pwm_lookup *table, size_t num);
+
 #endif
 
 #endif /* __LINUX_PWM_H */
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:55 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:55 +0200
Subject: [PATCH v5 13/16] ARM Samsung: Move s3c pwm driver to pwm framework
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-14-git-send-email-thierry.reding@avionic-design.de>

From: Sascha Hauer <s.hauer at pengutronix.de>

Move the driver to drivers/pwm/ and convert it to use the framework.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v5:
- adopt patch by Sascha Hauer to move s3c driver to PWM framework
- This driver could use some cleanups and rework to actually take advantage
  of the multiple PWM devices per PWM chip feature. Currently, information
  about the controlling timers is passed via platform resources but is not
  used. Perhaps the corresponding information can be passed in a better way
  via platform data?

 arch/arm/plat-samsung/Makefile                     |    4 -
 drivers/pwm/Kconfig                                |    9 +
 drivers/pwm/Makefile                               |    1 +
 .../pwm.c => drivers/pwm/pwm-samsung.c             |  228 ++++++++------------
 4 files changed, 97 insertions(+), 145 deletions(-)
 rename arch/arm/plat-samsung/pwm.c => drivers/pwm/pwm-samsung.c (58%)

diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 6012366..f09a7cf 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -50,7 +50,3 @@ obj-$(CONFIG_SAMSUNG_WAKEMASK)	+= wakeup-mask.o
 # PD support
 
 obj-$(CONFIG_SAMSUNG_PD)	+= pd.o
-
-# PWM support
-
-obj-$(CONFIG_HAVE_PWM)		+= pwm.o
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index a9a9715..0d9aa92 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -36,6 +36,15 @@ config PWM_PXA
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-pxa.
 
+config PWM_SAMSUNG
+	tristate "Samsung pwm support"
+	depends on PLAT_SAMSUNG
+	help
+	  Generic PWM framework driver for Samsung.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-samsung.
+
 config PWM_TEGRA
 	tristate "NVIDIA Tegra PWM support"
 	depends on ARCH_TEGRA
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 3dd1b83..a1d87b1 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -2,4 +2,5 @@ obj-$(CONFIG_PWM)		+= core.o
 obj-$(CONFIG_PWM_BFIN)		+= pwm-bfin.o
 obj-$(CONFIG_PWM_IMX)		+= pwm-imx.o
 obj-$(CONFIG_PWM_PXA)		+= pwm-pxa.o
+obj-$(CONFIG_PWM_SAMSUNG)	+= pwm-samsung.o
 obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
diff --git a/arch/arm/plat-samsung/pwm.c b/drivers/pwm/pwm-samsung.c
similarity index 58%
rename from arch/arm/plat-samsung/pwm.c
rename to drivers/pwm/pwm-samsung.c
index c559d84..631edf0 100644
--- a/arch/arm/plat-samsung/pwm.c
+++ b/drivers/pwm/pwm-samsung.c
@@ -24,8 +24,7 @@
 
 #include <plat/regs-timer.h>
 
-struct pwm_device {
-	struct list_head	 list;
+struct s3c_chip {
 	struct platform_device	*pdev;
 
 	struct clk		*clk_div;
@@ -36,117 +35,65 @@ struct pwm_device {
 	unsigned int		 duty_ns;
 
 	unsigned char		 tcon_base;
-	unsigned char		 running;
-	unsigned char		 use_count;
 	unsigned char		 pwm_id;
+	struct pwm_chip		 chip;
 };
 
+#define to_s3c_chip(chip)	container_of(chip, struct s3c_chip, chip)
+
 #define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg)
 
 static struct clk *clk_scaler[2];
 
-static inline int pwm_is_tdiv(struct pwm_device *pwm)
-{
-	return clk_get_parent(pwm->clk) == pwm->clk_div;
-}
-
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-	struct pwm_device *pwm;
-	int found = 0;
-
-	mutex_lock(&pwm_lock);
-
-	list_for_each_entry(pwm, &pwm_list, list) {
-		if (pwm->pwm_id == pwm_id) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (found) {
-		if (pwm->use_count == 0) {
-			pwm->use_count = 1;
-			pwm->label = label;
-		} else
-			pwm = ERR_PTR(-EBUSY);
-	} else
-		pwm = ERR_PTR(-ENOENT);
-
-	mutex_unlock(&pwm_lock);
-	return pwm;
-}
-
-EXPORT_SYMBOL(pwm_request);
-
-
-void pwm_free(struct pwm_device *pwm)
+static inline int pwm_is_tdiv(struct s3c_chip *chip)
 {
-	mutex_lock(&pwm_lock);
-
-	if (pwm->use_count) {
-		pwm->use_count--;
-		pwm->label = NULL;
-	} else
-		printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id);
-
-	mutex_unlock(&pwm_lock);
+	return clk_get_parent(chip->clk) == chip->clk_div;
 }
 
-EXPORT_SYMBOL(pwm_free);
-
 #define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0))
 #define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2))
 #define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3))
 #define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1))
 
-int pwm_enable(struct pwm_device *pwm)
+static int s3c_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
+	struct s3c_chip *s3c = to_s3c_chip(chip);
 	unsigned long flags;
 	unsigned long tcon;
 
 	local_irq_save(flags);
 
 	tcon = __raw_readl(S3C2410_TCON);
-	tcon |= pwm_tcon_start(pwm);
+	tcon |= pwm_tcon_start(s3c);
 	__raw_writel(tcon, S3C2410_TCON);
 
 	local_irq_restore(flags);
 
-	pwm->running = 1;
 	return 0;
 }
 
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
+static void s3c_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
+	struct s3c_chip *s3c = to_s3c_chip(chip);
 	unsigned long flags;
 	unsigned long tcon;
 
 	local_irq_save(flags);
 
 	tcon = __raw_readl(S3C2410_TCON);
-	tcon &= ~pwm_tcon_start(pwm);
+	tcon &= ~pwm_tcon_start(s3c);
 	__raw_writel(tcon, S3C2410_TCON);
 
 	local_irq_restore(flags);
-
-	pwm->running = 0;
 }
 
-EXPORT_SYMBOL(pwm_disable);
-
-static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
+static unsigned long pwm_calc_tin(struct s3c_chip *s3c, unsigned long freq)
 {
 	unsigned long tin_parent_rate;
 	unsigned int div;
 
-	tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div));
-	pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate);
+	tin_parent_rate = clk_get_rate(clk_get_parent(s3c->clk_div));
+	pwm_dbg(s3c, "tin parent at %lu\n", tin_parent_rate);
 
 	for (div = 2; div <= 16; div *= 2) {
 		if ((tin_parent_rate / (div << 16)) < freq)
@@ -158,8 +105,10 @@ static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
 
 #define NS_IN_HZ (1000000000UL)
 
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+static int s3c_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+		int duty_ns, int period_ns)
 {
+	struct s3c_chip *s3c = to_s3c_chip(chip);
 	unsigned long tin_rate;
 	unsigned long tin_ns;
 	unsigned long period;
@@ -178,38 +127,38 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 	if (duty_ns > period_ns)
 		return -EINVAL;
 
-	if (period_ns == pwm->period_ns &&
-	    duty_ns == pwm->duty_ns)
+	if (period_ns == s3c->period_ns &&
+	    duty_ns == s3c->duty_ns)
 		return 0;
 
 	/* The TCMP and TCNT can be read without a lock, they're not
 	 * shared between the timers. */
 
-	tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id));
-	tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id));
+	tcmp = __raw_readl(S3C2410_TCMPB(s3c->pwm_id));
+	tcnt = __raw_readl(S3C2410_TCNTB(s3c->pwm_id));
 
 	period = NS_IN_HZ / period_ns;
 
-	pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n",
+	pwm_dbg(s3c, "duty_ns=%d, period_ns=%d (%lu)\n",
 		duty_ns, period_ns, period);
 
 	/* Check to see if we are changing the clock rate of the PWM */
 
-	if (pwm->period_ns != period_ns) {
-		if (pwm_is_tdiv(pwm)) {
-			tin_rate = pwm_calc_tin(pwm, period);
-			clk_set_rate(pwm->clk_div, tin_rate);
+	if (s3c->period_ns != period_ns) {
+		if (pwm_is_tdiv(s3c)) {
+			tin_rate = pwm_calc_tin(s3c, period);
+			clk_set_rate(s3c->clk_div, tin_rate);
 		} else
-			tin_rate = clk_get_rate(pwm->clk);
+			tin_rate = clk_get_rate(s3c->clk);
 
-		pwm->period_ns = period_ns;
+		s3c->period_ns = period_ns;
 
-		pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate);
+		pwm_dbg(s3c, "tin_rate=%lu\n", tin_rate);
 
 		tin_ns = NS_IN_HZ / tin_rate;
 		tcnt = period_ns / tin_ns;
 	} else
-		tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk);
+		tin_ns = NS_IN_HZ / clk_get_rate(s3c->clk);
 
 	/* Note, counters count down */
 
@@ -220,7 +169,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 	if (tcmp == tcnt)
 		tcmp--;
 
-	pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
+	pwm_dbg(s3c, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
 
 	if (tcmp < 0)
 		tcmp = 0;
@@ -229,15 +178,15 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 
 	local_irq_save(flags);
 
-	__raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id));
-	__raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id));
+	__raw_writel(tcmp, S3C2410_TCMPB(s3c->pwm_id));
+	__raw_writel(tcnt, S3C2410_TCNTB(s3c->pwm_id));
 
 	tcon = __raw_readl(S3C2410_TCON);
-	tcon |= pwm_tcon_manulupdate(pwm);
-	tcon |= pwm_tcon_autoreload(pwm);
+	tcon |= pwm_tcon_manulupdate(s3c);
+	tcon |= pwm_tcon_autoreload(s3c);
 	__raw_writel(tcon, S3C2410_TCON);
 
-	tcon &= ~pwm_tcon_manulupdate(pwm);
+	tcon &= ~pwm_tcon_manulupdate(s3c);
 	__raw_writel(tcon, S3C2410_TCON);
 
 	local_irq_restore(flags);
@@ -245,24 +194,17 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 	return 0;
 }
 
-EXPORT_SYMBOL(pwm_config);
-
-static int pwm_register(struct pwm_device *pwm)
-{
-	pwm->duty_ns = -1;
-	pwm->period_ns = -1;
-
-	mutex_lock(&pwm_lock);
-	list_add_tail(&pwm->list, &pwm_list);
-	mutex_unlock(&pwm_lock);
-
-	return 0;
-}
+static struct pwm_ops s3c_pwm_ops = {
+	.enable = s3c_pwm_enable,
+	.disable = s3c_pwm_disable,
+	.config = s3c_pwm_config,
+	.owner = THIS_MODULE,
+};
 
 static int s3c_pwm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
-	struct pwm_device *pwm;
+	struct s3c_chip *s3c;
 	unsigned long flags;
 	unsigned long tcon;
 	unsigned int id = pdev->id;
@@ -273,83 +215,87 @@ static int s3c_pwm_probe(struct platform_device *pdev)
 		return -ENXIO;
 	}
 
-	pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
-	if (pwm == NULL) {
+	s3c = kzalloc(sizeof(*s3c), GFP_KERNEL);
+	if (s3c == NULL) {
 		dev_err(dev, "failed to allocate pwm_device\n");
 		return -ENOMEM;
 	}
 
-	pwm->pdev = pdev;
-	pwm->pwm_id = id;
-
 	/* calculate base of control bits in TCON */
-	pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4;
+	s3c->tcon_base = id == 0 ? 0 : (id * 4) + 4;
+	s3c->chip.ops = &s3c_pwm_ops;
+	s3c->chip.base = -1;
+	s3c->chip.npwm = 1;
 
-	pwm->clk = clk_get(dev, "pwm-tin");
-	if (IS_ERR(pwm->clk)) {
+	s3c->clk = clk_get(dev, "pwm-tin");
+	if (IS_ERR(s3c->clk)) {
 		dev_err(dev, "failed to get pwm tin clk\n");
-		ret = PTR_ERR(pwm->clk);
+		ret = PTR_ERR(s3c->clk);
 		goto err_alloc;
 	}
 
-	pwm->clk_div = clk_get(dev, "pwm-tdiv");
-	if (IS_ERR(pwm->clk_div)) {
+	s3c->clk_div = clk_get(dev, "pwm-tdiv");
+	if (IS_ERR(s3c->clk_div)) {
 		dev_err(dev, "failed to get pwm tdiv clk\n");
-		ret = PTR_ERR(pwm->clk_div);
+		ret = PTR_ERR(s3c->clk_div);
 		goto err_clk_tin;
 	}
 
-	clk_enable(pwm->clk);
-	clk_enable(pwm->clk_div);
+	clk_enable(s3c->clk);
+	clk_enable(s3c->clk_div);
 
 	local_irq_save(flags);
 
 	tcon = __raw_readl(S3C2410_TCON);
-	tcon |= pwm_tcon_invert(pwm);
+	tcon |= pwm_tcon_invert(s3c);
 	__raw_writel(tcon, S3C2410_TCON);
 
 	local_irq_restore(flags);
 
-
-	ret = pwm_register(pwm);
+	ret = pwmchip_add(&s3c->chip);
 	if (ret) {
 		dev_err(dev, "failed to register pwm\n");
 		goto err_clk_tdiv;
 	}
 
-	pwm_dbg(pwm, "config bits %02x\n",
-		(__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f);
+	pwm_dbg(s3c, "config bits %02x\n",
+		(__raw_readl(S3C2410_TCON) >> s3c->tcon_base) & 0x0f);
 
 	dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n",
-		 clk_get_rate(pwm->clk),
-		 clk_get_rate(pwm->clk_div),
-		 pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base);
+		 clk_get_rate(s3c->clk),
+		 clk_get_rate(s3c->clk_div),
+		 pwm_is_tdiv(s3c) ? "div" : "ext", s3c->tcon_base);
 
-	platform_set_drvdata(pdev, pwm);
+	platform_set_drvdata(pdev, s3c);
 	return 0;
 
  err_clk_tdiv:
-	clk_disable(pwm->clk_div);
-	clk_disable(pwm->clk);
-	clk_put(pwm->clk_div);
+	clk_disable(s3c->clk_div);
+	clk_disable(s3c->clk);
+	clk_put(s3c->clk_div);
 
  err_clk_tin:
-	clk_put(pwm->clk);
+	clk_put(s3c->clk);
 
  err_alloc:
-	kfree(pwm);
+	kfree(s3c);
 	return ret;
 }
 
 static int __devexit s3c_pwm_remove(struct platform_device *pdev)
 {
-	struct pwm_device *pwm = platform_get_drvdata(pdev);
+	struct s3c_chip *s3c = platform_get_drvdata(pdev);
+	int err;
+
+	err = pwmchip_remove(&s3c->chip);
+	if (err < 0)
+		return err;
 
-	clk_disable(pwm->clk_div);
-	clk_disable(pwm->clk);
-	clk_put(pwm->clk_div);
-	clk_put(pwm->clk);
-	kfree(pwm);
+	clk_disable(s3c->clk_div);
+	clk_disable(s3c->clk);
+	clk_put(s3c->clk_div);
+	clk_put(s3c->clk);
+	kfree(s3c);
 
 	return 0;
 }
@@ -357,26 +303,26 @@ static int __devexit s3c_pwm_remove(struct platform_device *pdev)
 #ifdef CONFIG_PM
 static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state)
 {
-	struct pwm_device *pwm = platform_get_drvdata(pdev);
+	struct s3c_chip *s3c = platform_get_drvdata(pdev);
 
 	/* No one preserve these values during suspend so reset them
 	 * Otherwise driver leaves PWM unconfigured if same values
 	 * passed to pwm_config
 	 */
-	pwm->period_ns = 0;
-	pwm->duty_ns = 0;
+	s3c->period_ns = 0;
+	s3c->duty_ns = 0;
 
 	return 0;
 }
 
 static int s3c_pwm_resume(struct platform_device *pdev)
 {
-	struct pwm_device *pwm = platform_get_drvdata(pdev);
+	struct s3c_chip *s3c = platform_get_drvdata(pdev);
 	unsigned long tcon;
 
 	/* Restore invertion */
 	tcon = __raw_readl(S3C2410_TCON);
-	tcon |= pwm_tcon_invert(pwm);
+	tcon |= pwm_tcon_invert(s3c);
 	__raw_writel(tcon, S3C2410_TCON);
 
 	return 0;
-- 
1.7.9.4



From broonie at opensource.wolfsonmicro.com  Wed Mar 28 10:36:50 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 15:36:50 +0100
Subject: [alsa-devel] [PATCH] ASoC: sgtl5000: fix power on/off of MIC bias
In-Reply-To: <20120328141812.GB3254@S2101-09.ap.freescale.net>
References: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
 <7FE21149F4667147B645348EC605788514EDFF@039-SN2MPN1-011.039d.mgd.msft.net>
 <20120328141812.GB3254@S2101-09.ap.freescale.net>
Message-ID: <20120328143649.GU3232@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 10:18:14PM +0800, Shawn Guo wrote:
> On Wed, Mar 28, 2012 at 09:52:15AM +0000, Dong Aisheng-B29396 wrote:

> > IIRC for line-in record, it may also need VAG_POWER up.
> > Then only enable VAG_POWER for mic_bias_event may not be sufficient.
> > Will verify it latter when I'm free.

> This patch only fixes MIC.  I think you can submit another patch after
> you confirm LINE-IN has the same issue.

I think this is a sensible approach, two patches fixing two issues seems
reasonable (and I'd not expect line input to need the mic bias itself).
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From hvaibhav at ti.com  Wed Mar 28 10:37:53 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Wed, 28 Mar 2012 14:37:53 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>

On Wed, Mar 28, 2012 at 19:50:02, Shilimkar, Santosh wrote:
> On Wed, Mar 28, 2012 at 7:46 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> > On Wed, Mar 21, 2012 at 19:30:01, Shilimkar, Santosh wrote:
> >> On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >> > On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
> >> >> On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
> >> >> > On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> 
> [...]
> 
> >
> >> Btw, if you need PM, how are you going to use GPTIMER
> >> as a clocksource. Note sys-clock is generally stopped in
> >> low power states. So that leaves you option with using
> >> gptimer with 32K clock and in that case, GPTIMER
> >> is not a better clock-source compare to 32K sync timer
> >> and so shouldn't be the rating.
> >>
> >
> > AM33xx has GPTIMER1 in wakeup domain, so that we are already using as a
> > Clocksource, without any issues.
> >
> GPTIMER1 is in wakeup domain on OMAP too but that doesn't
> solve the issue I am talking. Once the sysclock is stopped, GPTIMER
> can't tick anymore even if it is in wakeup domain.
> 
> The only way it will work is using always running 32KHz clock as
> the clock input to GPT1. And then the end result is the accuracy
> of GPTIMER = sync 32K timer. So they are of same rating.
> 

Ohh ok, sorry I should have clarified it in my last response itself.

AM33xx architecture is bit different than OMAP family, and gmtimer1 is 
sourced from RTC32K clock, which is in wakeup domain.
This means we have RTC32K clock always running across suspend/resume.

0 - SEL1: Select CLK_M_OSC clock
1 - SEL2: Select CLK_32KHZ clock
2 - SEL3: Select TCLKIN clock
3 - SEL4: Select CLK_RC32K clock
4 - SEL5: Selects the CLK_32768 from 32KHz Crystal Osc


We use value "4" here, for RTC32K (always on clock).
I hope this clarifies what I am trying to say here.


Thanks,
Vaibhav

> Hope it is clear now.
> 
> Regards
> Santosh
> 



From m.szyprowski at samsung.com  Wed Mar 28 10:38:40 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 28 Mar 2012 16:38:40 +0200
Subject: [PATCHv2 01/14] common: dma-mapping: introduce alloc_attrs and
 free_attrs methods
In-Reply-To: <4F72F603.2000803@mvista.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
 <1332855768-32583-2-git-send-email-m.szyprowski@samsung.com>
 <4F72F603.2000803@mvista.com>
Message-ID: <016001cd0cf0$7807bdb0$68173910$%szyprowski@samsung.com>

Hi Sergei,

On Wednesday, March 28, 2012 1:29 PM Sergei Shtylyov wrote:

> On 27-03-2012 17:42, Marek Szyprowski wrote:
> 
> > Introduce new generic alloc and free methods with attributes argument.
> 
>     The method names don't match the ones in the subject.

Right, I will reword the subject to "common: dma-mapping: introduce generic alloc()
and free() methods".

> > Existing alloc_coherent and free_coherent can be implemented on top of the
> > new calls with NULL attributes argument. Later also dma_alloc_non_coherent
> > can be implemented using DMA_ATTR_NONCOHERENT attribute as well as
> > dma_alloc_writecombine with separate DMA_ATTR_WRITECOMBINE attribute.
> 
> > This way the drivers will get more generic, platform independent way of
> > allocating dma buffers with specific parameters.
> 
> > Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> > Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
> > Reviewed-by: David Gibson <david at gibson.dropbear.ud.au>
> > Reviewed-by: Arnd Bergmann <arnd at arndb.de>
> 

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From broonie at opensource.wolfsonmicro.com  Wed Mar 28 10:40:17 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 15:40:17 +0100
Subject: [PATCH] mfd: mc13xxx: add I2C support fix building for v3.4
In-Reply-To: <1332943273-22447-1-git-send-email-alexg@meprolight.com>
References: <1332943273-22447-1-git-send-email-alexg@meprolight.com>
Message-ID: <20120328144017.GV3232@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 04:01:13PM +0200, Alex Gershgorin wrote:

> index c3fbc5e..2119732 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -577,6 +577,8 @@ config MFD_MC13XXX
>  	depends on SPI_MASTER || I2C
>  	select MFD_CORE
>  	select MFD_MC13783
> +	select REGMAP_I2C if I2C
> +	select REGMAP_SPI if SPI_MASTER
>  	help
>  	  Enable support for the Freescale MC13783 and MC13892 PMICs.
>  	  This driver provides common support for accessing the device,

I'd really expect this to be squashed into the patches adding the regmap
usage for I2C and SPI, how can those patches work without this?

> diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
> index 31dbf91..5a60273 100644
> --- a/drivers/mfd/mc13xxx-core.c
> +++ b/drivers/mfd/mc13xxx-core.c
> @@ -616,7 +616,7 @@ static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
>  #ifdef CONFIG_OF
>  static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
>  {
> -	struct device_node *np = mc13xxx->dev.of_node;
> +	struct device_node *np = mc13xxx->dev->of_node;

This looks like it should be submitted properly as a bug fix for
inclusion on 3.4 or squashed into whatever change introduces the issue
if it's not present in 3.4.
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From jason at lakedaemon.net  Wed Mar 28 10:41:55 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Wed, 28 Mar 2012 10:41:55 -0400
Subject: [PATCH V3 5/5] mtd: Move fdt partition documentation to a
 seperate file
In-Reply-To: <1332885255-8304-6-git-send-email-jm@lentin.co.uk>
References: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
 <1332885255-8304-6-git-send-email-jm@lentin.co.uk>
Message-ID: <20120328144155.GA32333@titan.lakedaemon.net>

On Tue, Mar 27, 2012 at 10:54:15PM +0100, Jamie Lentin wrote:
> Partitions are described in the same way for all mtd devices when using
> devicetree, move the documentation to a separate file and add references
> to it.
> 
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>

Acked-by: Jason Cooper <jason at lakedaemon.net>

> ---
>  .../devicetree/bindings/mtd/arm-versatile.txt      |    4 +-
>  .../devicetree/bindings/mtd/atmel-dataflash.txt    |    3 ++
>  .../devicetree/bindings/mtd/fsl-upm-nand.txt       |    4 ++
>  .../devicetree/bindings/mtd/gpio-control-nand.txt  |    3 ++
>  .../devicetree/bindings/mtd/mtd-physmap.txt        |   23 +-----------
>  .../devicetree/bindings/mtd/orion-nand.txt         |    3 ++
>  .../devicetree/bindings/mtd/partition.txt          |   38 ++++++++++++++++++++
>  7 files changed, 55 insertions(+), 23 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mtd/partition.txt



From santosh.shilimkar at ti.com  Wed Mar 28 10:49:07 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 28 Mar 2012 20:19:07 +0530
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
Message-ID: <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>

On Wed, Mar 28, 2012 at 8:07 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> On Wed, Mar 28, 2012 at 19:50:02, Shilimkar, Santosh wrote:
>> On Wed, Mar 28, 2012 at 7:46 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>> > On Wed, Mar 21, 2012 at 19:30:01, Shilimkar, Santosh wrote:
>> >> On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>> >> > On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
>> >> >> On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
>> >> >> > On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>>
>> [...]
>>
>> >
>> >> Btw, if you need PM, how are you going to use GPTIMER
>> >> as a clocksource. Note sys-clock is generally stopped in
>> >> low power states. So that leaves you option with using
>> >> gptimer with 32K clock and in that case, GPTIMER
>> >> is not a better clock-source compare to 32K sync timer
>> >> and so shouldn't be the rating.
>> >>
>> >
>> > AM33xx has GPTIMER1 in wakeup domain, so that we are already using as a
>> > Clocksource, without any issues.
>> >
>> GPTIMER1 is in wakeup domain on OMAP too but that doesn't
>> solve the issue I am talking. Once the sysclock is stopped, GPTIMER
>> can't tick anymore even if it is in wakeup domain.
>>
>> The only way it will work is using always running 32KHz clock as
>> the clock input to GPT1. And then the end result is the accuracy
>> of GPTIMER = sync 32K timer. So they are of same rating.
>>
>
> Ohh ok, sorry I should have clarified it in my last response itself.
>
np.

> AM33xx architecture is bit different than OMAP family, and gmtimer1 is
> sourced from RTC32K clock, which is in wakeup domain.
> This means we have RTC32K clock always running across suspend/resume.
>
> 0 - SEL1: Select CLK_M_OSC clock
> 1 - SEL2: Select CLK_32KHZ clock
> 2 - SEL3: Select TCLKIN clock
> 3 - SEL4: Select CLK_RC32K clock
> 4 - SEL5: Selects the CLK_32768 from 32KHz Crystal Osc
>
>
> We use value "4" here, for RTC32K (always on clock).
> I hope this clarifies what I am trying to say here.
>
I thought so and now if you look at last part of my comment.

Rating of 32K based synctimer and 32K based GPTIMER
should be same because of the precision. That's the main
point why I was saying that GPTIMER is not a better
clock-source( with 32k clock src)  than sync timer when
both are enabled together.

Regards
Santosh


From arnd at arndb.de  Wed Mar 28 10:53:59 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 28 Mar 2012 14:53:59 +0000
Subject: [PATCH v5 05/16] pwm: Add device tree support
In-Reply-To: <1332945238-14897-6-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-6-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <201203281454.00457.arnd@arndb.de>

On Wednesday 28 March 2012, Thierry Reding wrote:
> This patch adds helpers to support device tree bindings for the generic
> PWM API. Device tree binding documentation for PWM controllers is also
> provided.
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>

Acked-by: Arnd Bergmann <arnd at arndb.de>

I'm very happy with how the binding turned out.


From arnd at arndb.de  Wed Mar 28 10:59:40 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 28 Mar 2012 14:59:40 +0000
Subject: [GIT PULL 0/5] Second batch of arm-soc changes
In-Reply-To: <4F731FAA.5040708@gmail.com>
References: <1332918842-13521-1-git-send-email-olof@lixom.net>
 <4F731FAA.5040708@gmail.com>
Message-ID: <201203281459.41188.arnd@arndb.de>

On Wednesday 28 March 2012, Rob Herring wrote:
> On 03/28/2012 02:13 AM, Olof Johansson wrote:
> > There are a handful of merge conflicts on the branches, nothing that
> > should be too messy to sort out. I've described each conflict in the
> > corresponding pull request, including how we've resolved them in our
> > for-next branch.
> > 
> 
> Why isn't lakml getting copied on emails 1-5? The same thing happened
> with Arnd's pull request. Are they getting hung up for moderator approval?

For some reason, the mailing list rejected the emails with 'suspicious header'
warnings, but did not list which headers were suspicious. I think I've
had this problem before and solved it, but don't remember the solution
any more now. linux-kernel took the emails though.

	Arnd


From thierry.reding at avionic-design.de  Wed Mar 28 10:33:58 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:58 +0200
Subject: [PATCH v5 16/16] pwm: Take over maintainership of the PWM subsystem
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-17-git-send-email-thierry.reding@avionic-design.de>

I'm taking over the maintainership of the PWM subsystem. This commit
also adds the URLs to the gitorious project and repository as well as
any missing files related to the PWM subsystem.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Note: I guess this patch in particular could use some Acked-by, maybe from
Arnd and Sascha so that people will know this happens with their blessing.

 MAINTAINERS |   10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index d68feef..769055a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5429,10 +5429,16 @@ S:	Maintained
 F:	Documentation/video4linux/README.pvrusb2
 F:	drivers/media/video/pvrusb2/
 
-PWM core
-M:	Sascha Hauer <s.hauer at pengutronix.de>
+PWM SUBSYSTEM
+M:	Thierry Reding <thierry.reding at avionic-design.de>
 L:	linux-kernel at vger.kernel.org
 S:	Maintained
+W:	http://gitorious.org/linux-pwm
+T:	git git://gitorious.org/linux-pwm/linux-pwm.git
+F:	Documentation/pwm.txt
+F:	Documentation/devicetree/bindings/pwm/
+F:	include/linux/pwm.h
+F:	include/linux/of_pwm.h
 F:	drivers/pwm/
 
 PXA2xx/PXA3xx SUPPORT
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:57 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:57 +0200
Subject: [PATCH v5 15/16] pwm-backlight: Add rudimentary device tree support
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-16-git-send-email-thierry.reding@avionic-design.de>

This commit adds very basic support for device tree probing. Currently,
only a PWM and a list of distinct brightness levels can be specified.
Enabling or disabling backlight power via GPIOs is not yet supported.

Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v5:
- use "pwms" fixed property name
- document brightness-levels and default-brightness-level properties
- check default-brightness-level against brightness-levels
- use new PWM API (pwm_get() and pwm_put()), legacy API (pwm_request())
  as fallback

Changes in v4:
- store a PWM requested with of_pwm_request() in the platform data

Changes in v3:
- use a list of distinct brightness levels instead of a linear range
  as discussed with Stephen Warren and Mitch Bradley

Changes in v2:
- avoid oops by keeping a reference to the platform-specific exit()
  callback

TODO:
- add fixed-regulator support for backlight enable/disable

 .../bindings/video/backlight/pwm-backlight         |   30 ++++
 drivers/video/backlight/Kconfig                    |    2 +-
 drivers/video/backlight/pwm_bl.c                   |  145 +++++++++++++++++---
 include/linux/pwm_backlight.h                      |    1 +
 4 files changed, 157 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/video/backlight/pwm-backlight

diff --git a/Documentation/devicetree/bindings/video/backlight/pwm-backlight b/Documentation/devicetree/bindings/video/backlight/pwm-backlight
new file mode 100644
index 0000000..bc2d08d
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/backlight/pwm-backlight
@@ -0,0 +1,30 @@
+pwm-backlight bindings
+
+Required properties:
+  - compatible: "pwm-backlight"
+  - pwms: OF device-tree PWM specification (see PWM binding[0])
+  - num-brightness-levels: number of distinct brightness levels
+  - brightness-levels: Array of distinct brightness levels. Typically these
+      are in the range from 0 to 255, but any range starting at 0 will do.
+      The actual brightness level (PWM duty cycle) will be interpolated
+      from these values. 0 means a 0% duty cycle (darkest/off), while the
+      last value in the array represents a 100% duty cycle (brightest).
+  - default-brightness-level: the default brightness level (index into the
+      array defined by the "brightness-levels" property)
+
+Optional properties:
+  - pwm-names: a list of names for the PWM devices specified in the
+               "pwms" property (see PWM binding[0])
+
+[0]: Documentation/devicetree/bindings/pwm/pwm.txt
+
+Example:
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 5000000>;
+
+		num-brightness-levels = <8>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+	};
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index 7ed9991..cd77e79 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -233,7 +233,7 @@ config BACKLIGHT_CARILLO_RANCH
 
 config BACKLIGHT_PWM
 	tristate "Generic PWM based Backlight Driver"
-	depends on HAVE_PWM
+	depends on PWM
 	help
 	  If you have a LCD backlight adjustable by PWM, say Y to enable
 	  this driver.
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
index 342b7d7..b996548 100644
--- a/drivers/video/backlight/pwm_bl.c
+++ b/drivers/video/backlight/pwm_bl.c
@@ -26,11 +26,13 @@ struct pwm_bl_data {
 	struct device		*dev;
 	unsigned int		period;
 	unsigned int		lth_brightness;
+	unsigned int		*levels;
 	int			(*notify)(struct device *,
 					  int brightness);
 	void			(*notify_after)(struct device *,
 					int brightness);
 	int			(*check_fb)(struct device *, struct fb_info *);
+	void			(*exit)(struct device *);
 };
 
 static int pwm_backlight_update_status(struct backlight_device *bl)
@@ -52,6 +54,11 @@ static int pwm_backlight_update_status(struct backlight_device *bl)
 		pwm_config(pb->pwm, 0, pb->period);
 		pwm_disable(pb->pwm);
 	} else {
+		if (pb->levels) {
+			brightness = pb->levels[brightness];
+			max = pb->levels[max];
+		}
+
 		brightness = pb->lth_brightness +
 			(brightness * (pb->period - pb->lth_brightness) / max);
 		pwm_config(pb->pwm, brightness, pb->period);
@@ -83,17 +90,94 @@ static const struct backlight_ops pwm_backlight_ops = {
 	.check_fb	= pwm_backlight_check_fb,
 };
 
+#ifdef CONFIG_OF
+static int pwm_backlight_parse_dt(struct device *dev,
+				  struct platform_pwm_backlight_data *data)
+{
+	struct device_node *node = dev->of_node;
+	u32 value;
+	int ret;
+
+	if (!node)
+		return -ENODEV;
+
+	memset(data, 0, sizeof(*data));
+
+	ret = of_property_read_u32(node, "num-brightness-levels", &value);
+	if (ret < 0)
+		return ret;
+
+	data->max_brightness = value;
+
+	if (data->max_brightness > 0) {
+		size_t size = sizeof(*data->levels) * data->max_brightness;
+
+		data->levels = devm_kzalloc(dev, size, GFP_KERNEL);
+		if (!data->levels)
+			return -ENOMEM;
+
+		ret = of_property_read_u32_array(node, "brightness-levels",
+						 data->levels,
+						 data->max_brightness);
+		if (ret < 0)
+			return ret;
+
+		ret = of_property_read_u32(node, "default-brightness-level",
+					   &value);
+		if (ret < 0)
+			return ret;
+
+		if (value >= data->max_brightness) {
+			dev_warn(dev, "invalid default brightness level: %u, using %u\n",
+				 value, data->max_brightness - 1);
+			value = data->max_brightness - 1;
+		}
+
+		data->dft_brightness = value;
+		data->max_brightness--;
+	}
+
+	/*
+	 * TODO: Most users of this driver use a number of GPIOs to control
+	 *       backlight power. Support for specifying these needs to be
+	 *       added.
+	 */
+
+	return 0;
+}
+
+static struct of_device_id pwm_backlight_of_match[] = {
+	{ .compatible = "pwm-backlight" },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, pwm_backlight_of_match);
+#else
+static int pwm_backlight_parse_dt(struct device *dev,
+				  struct platform_pwm_backlight_data *data)
+{
+	return -ENODEV;
+}
+#endif
+
 static int pwm_backlight_probe(struct platform_device *pdev)
 {
-	struct backlight_properties props;
 	struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
+	struct platform_pwm_backlight_data defdata;
+	struct backlight_properties props;
 	struct backlight_device *bl;
 	struct pwm_bl_data *pb;
+	unsigned int max;
 	int ret;
 
 	if (!data) {
-		dev_err(&pdev->dev, "failed to find platform data\n");
-		return -EINVAL;
+		ret = pwm_backlight_parse_dt(&pdev->dev, &defdata);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "failed to find platform data\n");
+			return ret;
+		}
+
+		data = &defdata;
 	}
 
 	if (data->init) {
@@ -109,21 +193,42 @@ static int pwm_backlight_probe(struct platform_device *pdev)
 		goto err_alloc;
 	}
 
-	pb->period = data->pwm_period_ns;
+	if (data->levels) {
+		max = data->levels[data->max_brightness];
+		pb->levels = data->levels;
+	} else
+		max = data->max_brightness;
+
 	pb->notify = data->notify;
 	pb->notify_after = data->notify_after;
 	pb->check_fb = data->check_fb;
-	pb->lth_brightness = data->lth_brightness *
-		(data->pwm_period_ns / data->max_brightness);
+	pb->exit = data->exit;
 	pb->dev = &pdev->dev;
 
-	pb->pwm = pwm_request(data->pwm_id, "backlight");
+	pb->pwm = pwm_get(&pdev->dev, "pwm-backlight");
 	if (IS_ERR(pb->pwm)) {
-		dev_err(&pdev->dev, "unable to request PWM for backlight\n");
-		ret = PTR_ERR(pb->pwm);
-		goto err_alloc;
-	} else
-		dev_dbg(&pdev->dev, "got pwm for backlight\n");
+		dev_err(&pdev->dev, "unable to request PWM, trying legacy API\n");
+
+		pb->pwm = pwm_request(data->pwm_id, "pwm-backlight");
+		if (IS_ERR(pb->pwm)) {
+			dev_err(&pdev->dev, "unable to request legacy PWM\n");
+			ret = PTR_ERR(pb->pwm);
+			goto err_alloc;
+		}
+	}
+
+	dev_dbg(&pdev->dev, "got pwm for backlight\n");
+
+	/*
+	 * The DT case will set the pwm_period_ns field to 0 and store the
+	 * period, parsed from the DT, in the PWM device. For the non-DT case,
+	 * set the period from platform data.
+	 */
+	if (data->pwm_period_ns > 0)
+		pwm_set_period(pb->pwm, data->pwm_period_ns);
+
+	pb->period = pwm_get_period(pb->pwm);
+	pb->lth_brightness = data->lth_brightness * (pb->period / max);
 
 	memset(&props, 0, sizeof(struct backlight_properties));
 	props.type = BACKLIGHT_RAW;
@@ -143,7 +248,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
 	return 0;
 
 err_bl:
-	pwm_free(pb->pwm);
+	pwm_put(pb->pwm);
 err_alloc:
 	if (data->exit)
 		data->exit(&pdev->dev);
@@ -152,16 +257,15 @@ err_alloc:
 
 static int pwm_backlight_remove(struct platform_device *pdev)
 {
-	struct platform_pwm_backlight_data *data = pdev->dev.platform_data;
 	struct backlight_device *bl = platform_get_drvdata(pdev);
 	struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev);
 
 	backlight_device_unregister(bl);
 	pwm_config(pb->pwm, 0, pb->period);
 	pwm_disable(pb->pwm);
-	pwm_free(pb->pwm);
-	if (data->exit)
-		data->exit(&pdev->dev);
+	pwm_put(pb->pwm);
+	if (pb->exit)
+		pb->exit(&pdev->dev);
 	return 0;
 }
 
@@ -195,11 +299,12 @@ static SIMPLE_DEV_PM_OPS(pwm_backlight_pm_ops, pwm_backlight_suspend,
 
 static struct platform_driver pwm_backlight_driver = {
 	.driver		= {
-		.name	= "pwm-backlight",
-		.owner	= THIS_MODULE,
+		.name		= "pwm-backlight",
+		.owner		= THIS_MODULE,
 #ifdef CONFIG_PM
-		.pm	= &pwm_backlight_pm_ops,
+		.pm		= &pwm_backlight_pm_ops,
 #endif
+		.of_match_table	= of_match_ptr(pwm_backlight_of_match),
 	},
 	.probe		= pwm_backlight_probe,
 	.remove		= pwm_backlight_remove,
diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h
index 63d2df4..56f4a86 100644
--- a/include/linux/pwm_backlight.h
+++ b/include/linux/pwm_backlight.h
@@ -12,6 +12,7 @@ struct platform_pwm_backlight_data {
 	unsigned int dft_brightness;
 	unsigned int lth_brightness;
 	unsigned int pwm_period_ns;
+	unsigned int *levels;
 	int (*init)(struct device *dev);
 	int (*notify)(struct device *dev, int brightness);
 	void (*notify_after)(struct device *dev, int brightness);
-- 
1.7.9.4



From thierry.reding at avionic-design.de  Wed Mar 28 10:33:56 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Wed, 28 Mar 2012 16:33:56 +0200
Subject: [PATCH v5 14/16] ARM vt8500: Move vt8500 pwm driver to pwm framework
In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <1332945238-14897-15-git-send-email-thierry.reding@avionic-design.de>

From: Sascha Hauer <s.hauer at pengutronix.de>

Move the driver to drivers/pwm/ and convert it to use the framework.

Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Alexey Charkov <alchark at gmail.com>
Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
---
Changes in v5:
- adopt patch by Sascha Hauer to move vt8500 driver to PWM framework

 arch/arm/mach-vt8500/Makefile                      |    2 -
 drivers/pwm/Kconfig                                |    9 ++
 drivers/pwm/Makefile                               |    1 +
 .../mach-vt8500/pwm.c => drivers/pwm/pwm-vt8500.c  |  169 +++++++-------------
 4 files changed, 66 insertions(+), 115 deletions(-)
 rename arch/arm/mach-vt8500/pwm.c => drivers/pwm/pwm-vt8500.c (52%)

diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 81aedb7..8df9e4a 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -5,5 +5,3 @@ obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o
 
 obj-$(CONFIG_MACH_BV07) += bv07.o
 obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o
-
-obj-$(CONFIG_HAVE_PWM) += pwm.o
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 0d9aa92..a93feff 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -55,4 +55,13 @@ config PWM_TEGRA
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-tegra.
 
+config PWM_VT8500
+	tristate "vt8500 pwm support"
+	depends on ARCH_VT8500
+	help
+	  Generic PWM framework driver for vt8500.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-vt8500.
+
 endif
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index a1d87b1..b7c0fcf 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PWM_IMX)		+= pwm-imx.o
 obj-$(CONFIG_PWM_PXA)		+= pwm-pxa.o
 obj-$(CONFIG_PWM_SAMSUNG)	+= pwm-samsung.o
 obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
+obj-$(CONFIG_PWM_VT8500)	+= pwm-vt8500.o
diff --git a/arch/arm/mach-vt8500/pwm.c b/drivers/pwm/pwm-vt8500.c
similarity index 52%
rename from arch/arm/mach-vt8500/pwm.c
rename to drivers/pwm/pwm-vt8500.c
index 8ad825e..3db0746 100644
--- a/arch/arm/mach-vt8500/pwm.c
+++ b/drivers/pwm/pwm-vt8500.c
@@ -26,21 +26,13 @@
 
 #define VT8500_NR_PWMS 4
 
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
-
-struct pwm_device {
-	struct list_head	node;
-	struct platform_device	*pdev;
-
-	const char	*label;
-
-	void __iomem	*regbase;
-
-	unsigned int	use_count;
-	unsigned int	pwm_id;
+struct vt8500_chip {
+	struct pwm_chip chip;
+	void __iomem *base;
 };
 
+#define to_vt8500_chip(chip)	container_of(chip, struct vt8500_chip, chip)
+
 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 static inline void pwm_busy_wait(void __iomem *reg, u8 bitmask)
 {
@@ -53,14 +45,13 @@ static inline void pwm_busy_wait(void __iomem *reg, u8 bitmask)
 			   bitmask);
 }
 
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+		int duty_ns, int period_ns)
 {
+	struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
 	unsigned long long c;
 	unsigned long period_cycles, prescale, pv, dc;
 
-	if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
-		return -EINVAL;
-
 	c = 25000000/2; /* wild guess --- need to implement clocks */
 	c = c * period_ns;
 	do_div(c, 1000000000);
@@ -80,104 +71,58 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 	do_div(c, period_ns);
 	dc = c;
 
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 1));
-	writel(prescale, pwm->regbase + 0x4 + (pwm->pwm_id << 4));
+	pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 1));
+	writel(prescale, vt8500->base + 0x4 + (pwm->hwpwm << 4));
 
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 2));
-	writel(pv, pwm->regbase + 0x8 + (pwm->pwm_id << 4));
+	pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 2));
+	writel(pv, vt8500->base + 0x8 + (pwm->hwpwm << 4));
 
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 3));
-	writel(dc, pwm->regbase + 0xc + (pwm->pwm_id << 4));
+	pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 3));
+	writel(dc, vt8500->base + 0xc + (pwm->hwpwm << 4));
 
 	return 0;
 }
-EXPORT_SYMBOL(pwm_config);
 
-int pwm_enable(struct pwm_device *pwm)
+static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 0));
-	writel(5, pwm->regbase + (pwm->pwm_id << 4));
-	return 0;
-}
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-	pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 0));
-	writel(0, pwm->regbase + (pwm->pwm_id << 4));
-}
-EXPORT_SYMBOL(pwm_disable);
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-	struct pwm_device *pwm;
-	int found = 0;
-
-	mutex_lock(&pwm_lock);
+	struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
 
-	list_for_each_entry(pwm, &pwm_list, node) {
-		if (pwm->pwm_id == pwm_id) {
-			found = 1;
-			break;
-		}
-	}
-
-	if (found) {
-		if (pwm->use_count == 0) {
-			pwm->use_count++;
-			pwm->label = label;
-		} else {
-			pwm = ERR_PTR(-EBUSY);
-		}
-	} else {
-		pwm = ERR_PTR(-ENOENT);
-	}
-
-	mutex_unlock(&pwm_lock);
-	return pwm;
+	pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 0));
+	writel(5, vt8500->base + (pwm->hwpwm << 4));
+	return 0;
 }
-EXPORT_SYMBOL(pwm_request);
 
-void pwm_free(struct pwm_device *pwm)
+static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 {
-	mutex_lock(&pwm_lock);
-
-	if (pwm->use_count) {
-		pwm->use_count--;
-		pwm->label = NULL;
-	} else {
-		pr_warning("PWM device already freed\n");
-	}
+	struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
 
-	mutex_unlock(&pwm_lock);
+	pwm_busy_wait(vt8500->base + 0x40 + pwm->hwpwm, (1 << 0));
+	writel(0, vt8500->base + (pwm->hwpwm << 4));
 }
-EXPORT_SYMBOL(pwm_free);
 
-static inline void __add_pwm(struct pwm_device *pwm)
-{
-	mutex_lock(&pwm_lock);
-	list_add_tail(&pwm->node, &pwm_list);
-	mutex_unlock(&pwm_lock);
-}
+static struct pwm_ops vt8500_pwm_ops = {
+	.enable = vt8500_pwm_enable,
+	.disable = vt8500_pwm_disable,
+	.config = vt8500_pwm_config,
+	.owner = THIS_MODULE,
+};
 
 static int __devinit pwm_probe(struct platform_device *pdev)
 {
-	struct pwm_device *pwms;
+	struct vt8500_chip *chip;
 	struct resource *r;
-	int ret = 0;
-	int i;
+	int ret;
 
-	pwms = kzalloc(sizeof(struct pwm_device) * VT8500_NR_PWMS, GFP_KERNEL);
-	if (pwms == NULL) {
+	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
+	if (chip == NULL) {
 		dev_err(&pdev->dev, "failed to allocate memory\n");
 		return -ENOMEM;
 	}
 
-	for (i = 0; i < VT8500_NR_PWMS; i++) {
-		pwms[i].use_count = 0;
-		pwms[i].pwm_id = i;
-		pwms[i].pdev = pdev;
-	}
+	chip->chip.dev = &pdev->dev;
+	chip->chip.ops = &vt8500_pwm_ops;
+	chip->chip.base = -1;
+	chip->chip.npwm = VT8500_NR_PWMS;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
@@ -193,51 +138,49 @@ static int __devinit pwm_probe(struct platform_device *pdev)
 		goto err_free;
 	}
 
-	pwms[0].regbase = ioremap(r->start, resource_size(r));
-	if (pwms[0].regbase == NULL) {
+	chip->base = ioremap(r->start, resource_size(r));
+	if (chip->base == NULL) {
 		dev_err(&pdev->dev, "failed to ioremap() registers\n");
 		ret = -ENODEV;
 		goto err_free_mem;
 	}
 
-	for (i = 1; i < VT8500_NR_PWMS; i++)
-		pwms[i].regbase = pwms[0].regbase;
-
-	for (i = 0; i < VT8500_NR_PWMS; i++)
-		__add_pwm(&pwms[i]);
+	ret = pwmchip_add(&chip->chip);
+	if (ret < 0)
+		goto err_unmap;
 
-	platform_set_drvdata(pdev, pwms);
-	return 0;
+	platform_set_drvdata(pdev, chip);
+	return ret;
 
+err_unmap:
+	iounmap(chip->base);
 err_free_mem:
 	release_mem_region(r->start, resource_size(r));
 err_free:
-	kfree(pwms);
+	kfree(chip);
 	return ret;
 }
 
 static int __devexit pwm_remove(struct platform_device *pdev)
 {
-	struct pwm_device *pwms;
+	struct vt8500_chip *chip;
 	struct resource *r;
-	int i;
+	int err;
 
-	pwms = platform_get_drvdata(pdev);
-	if (pwms == NULL)
+	chip = platform_get_drvdata(pdev);
+	if (chip == NULL)
 		return -ENODEV;
 
-	mutex_lock(&pwm_lock);
-
-	for (i = 0; i < VT8500_NR_PWMS; i++)
-		list_del(&pwms[i].node);
-	mutex_unlock(&pwm_lock);
+	err = pwmchip_remove(&chip->chip);
+	if (err < 0)
+		return err;
 
-	iounmap(pwms[0].regbase);
+	iounmap(chip->base);
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	release_mem_region(r->start, resource_size(r));
 
-	kfree(pwms);
+	kfree(chip);
 	return 0;
 }
 
-- 
1.7.9.4



From Bill.Randle at aei.com  Wed Mar 28 11:13:57 2012
From: Bill.Randle at aei.com (Randle, Bill)
Date: Wed, 28 Mar 2012 15:13:57 +0000
Subject: i.MX28 die temperature
Message-ID: <330B740BA662BF4E8386F534DF556ED819731A@AEDCEXC09.aei.com>

Has anyone developed a driver for reading the die temperature from the i.MX28? I haven't found anything yet in my searching, but didn't want to duplicate effort if someone has something already.

	-Bill Randle


This message, including any attachments, may contain 
information that is confidential and proprietary information 
of Advanced Energy Industries, Inc.  The dissemination,
distribution, use or copying of this message or any of its
attachments is strictly prohibited without the express 
written consent of Advanced Energy Industries, Inc.


From grinberg at compulab.co.il  Wed Mar 28 11:21:59 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 28 Mar 2012 17:21:59 +0200
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <4F732C97.2030804@compulab.co.il>

Hi Paul,

I've finally found one of em-x270 to test on...

On 03/09/12 00:06, Paul Gortmaker wrote:
> Commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0 (linux-next)
> 
>   "regulator: Remove support for supplies specified by struct device"
> 
> caused this file to break, since it was still relying on the
> device field to be present.  Update them to use the new dev_name
> entries instead.
> 
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> CC: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---
> 
> [v2: replace dev with dev_name instead of just deleting dev.
>  Note however there is dev_name overlap; not sure if that matters? ]
> 
> diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
> index c1b65da..0ffc100 100644
> --- a/arch/arm/mach-pxa/em-x270.c
> +++ b/arch/arm/mach-pxa/em-x270.c
> @@ -1083,19 +1083,19 @@ static void __init em_x270_userspace_consumers_init(void)
>  }
>  
>  /* DA9030 related initializations */
> -#define REGULATOR_CONSUMER(_name, _dev, _supply)			       \
> +#define REGULATOR_CONSUMER(_name, _dev_name, _supply)		        \
>  	static struct regulator_consumer_supply _name##_consumers[] = {	\
>  		{							\
> -			.dev = _dev,					\
> +			.dev_name = _dev_name,				\
>  			.supply = _supply,				\
>  		},							\
>  	}
>  
> -REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps");
> +REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer", "vcc gps");

If you make this:
REGULATOR_CONSUMER(ldo3, NULL, "vcc gps");

>  REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
> -REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
> +REGULATOR_CONSUMER(ldo10, "pxa2xx-mci", "vcc sdio");
>  REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
> -REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
> +REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer", "vcc gprs");

and this:
REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs");

the device even boots...

>  REGULATOR_CONSUMER(buck2, NULL, "vcc_core");
>  
>  #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask)		\


Thanks for the patch, with the changes above:
Tested-by: Igor Grinberg <grinberg at compulab.co.il>

Haojian, can this patch be included in your pull request (or another one)?
It fixes the build for em_x270_defconfig and with the updates above
gets the board to boot.

Thanks.

-- 
Regards,
Igor.


From grinberg at compulab.co.il  Wed Mar 28 11:24:04 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 28 Mar 2012 17:24:04 +0200
Subject: [GIT PULL] pull request from arch-pxa git on fixes branch
In-Reply-To: <CAN1soZytJ-CxepQAZn5oZ06=ezTQ85O-iC7tUDOeWqi=zpuf8A@mail.gmail.com>
References: <CAN1soZytJ-CxepQAZn5oZ06=ezTQ85O-iC7tUDOeWqi=zpuf8A@mail.gmail.com>
Message-ID: <4F732D14.3020803@compulab.co.il>

Hi Haojian,

On 03/28/12 15:51, Haojian Zhuang wrote:
> Hi Arnd & Olof,
> 
> Please help to pull fixes branch in arch-pxa git. This fix can resolve
> build issues on updating regulator interface.
> 
> The following changes since commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7:
> 
>   Linux 3.3 (2012-03-18 16:15:34 -0700)
> 
> are available in the git repository at:
>   git://github.com/hzhuang1/linux.git fixes
> 
> Paul Gortmaker (1):
>       ARM: pxa: fix regulator related build fail in magician_defconfig
> 
>  arch/arm/mach-pxa/hx4700.c   |    2 --
>  arch/arm/mach-pxa/magician.c |    2 --
>  2 files changed, 0 insertions(+), 4 deletions(-)

Can Paul's patch [1] be included in this or later request?

Thanks.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/091750.html


-- 
Regards,
Igor.


From broonie at opensource.wolfsonmicro.com  Wed Mar 28 11:27:44 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 16:27:44 +0100
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <4F732C97.2030804@compulab.co.il>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
Message-ID: <20120328152743.GW3232@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 05:21:59PM +0200, Igor Grinberg wrote:
> On 03/09/12 00:06, Paul Gortmaker wrote:

> > +REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer", "vcc gps");

> If you make this:
> REGULATOR_CONSUMER(ldo3, NULL, "vcc gps");

> > +REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer", "vcc gprs");
> 
> and this:
> REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs");

These don't look like good fixes, you should be specifying the
dev_name() for the consumer device?  Presumably it's two separate
consumers and should be .0 and .1 or something?
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From haojian.zhuang at gmail.com  Wed Mar 28 11:37:37 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Wed, 28 Mar 2012 23:37:37 +0800
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <20120328152743.GW3232@opensource.wolfsonmicro.com>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
 <20120328152743.GW3232@opensource.wolfsonmicro.com>
Message-ID: <CAN1soZy7jB_H0meVyh_H8nmbaSDmiDpjBYi_WO=pmjYzEf9r6Q@mail.gmail.com>

On Wed, Mar 28, 2012 at 11:27 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Wed, Mar 28, 2012 at 05:21:59PM +0200, Igor Grinberg wrote:
>> On 03/09/12 00:06, Paul Gortmaker wrote:
>
>> > +REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer", "vcc gps");
>
>> If you make this:
>> REGULATOR_CONSUMER(ldo3, NULL, "vcc gps");
>
>> > +REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer", "vcc gprs");
>>
>> and this:
>> REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs");
>
> These don't look like good fixes, you should be specifying the
> dev_name() for the consumer device? ?Presumably it's two separate
> consumers and should be .0 and .1 or something?

Paul,

Could you do a quick update on dev_name() according to Mark's comment?

-REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
+REGULAOTR_CONSUMER(ldo10, dev_name(&pxa_device_mci.dev), "vcc sdio");

Best Regards
Haojian


From broonie at opensource.wolfsonmicro.com  Wed Mar 28 11:39:18 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 16:39:18 +0100
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <CAN1soZy7jB_H0meVyh_H8nmbaSDmiDpjBYi_WO=pmjYzEf9r6Q@mail.gmail.com>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
 <20120328152743.GW3232@opensource.wolfsonmicro.com>
 <CAN1soZy7jB_H0meVyh_H8nmbaSDmiDpjBYi_WO=pmjYzEf9r6Q@mail.gmail.com>
Message-ID: <20120328153918.GX3232@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 11:37:37PM +0800, Haojian Zhuang wrote:
> On Wed, Mar 28, 2012 at 11:27 PM, Mark Brown

> > These don't look like good fixes, you should be specifying the
> > dev_name() for the consumer device? ?Presumably it's two separate
> > consumers and should be .0 and .1 or something?

> Could you do a quick update on dev_name() according to Mark's comment?

> -REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
> +REGULAOTR_CONSUMER(ldo10, dev_name(&pxa_device_mci.dev), "vcc sdio");

No, you're missing the point again.  As I said previously the whole
point of this interface is that you don't have to have access to the
struct device.  This should be the string *returned* by dev_name(), not
a direct call to dev_name().
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From jon-hunter at ti.com  Tue Mar 27 17:03:28 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Tue, 27 Mar 2012 16:03:28 -0500
Subject: [PATCH 1/3] OMAP2+: UART: Remove cpu checks for populating errata
 flags
In-Reply-To: <1332325501-10467-2-git-send-email-govindraj.raja@ti.com>
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
 <1332325501-10467-2-git-send-email-govindraj.raja@ti.com>
Message-ID: <4F722B20.8080503@ti.com>

Hi Govindraj,

On 3/21/2012 5:24, Govindraj.R wrote:
> From: "Govindraj.R"<govindraj.raja at ti.com>
>
> Currently the errata is populated based on cpu checks this can
> be removed and replaced with module version check of uart ip block.
> MVR reg is provided within the uart reg map use the same
> to populate the errata and thus now errata population and handling
> can be managed within the driver itself.
>
> Cc: Paul Walmsley<paul at pwsan.com>
> Cc: Kevin Hilman<khilman at ti.com>
> Signed-off-by: Felipe Balbi<balbi at ti.com>
> Signed-off-by: Govindraj.R<govindraj.raja at ti.com>
> ---
>   arch/arm/mach-omap2/serial.c                  |    8 ---
>   arch/arm/plat-omap/include/plat/omap-serial.h |    1 -
>   drivers/tty/serial/omap-serial.c              |   62 ++++++++++++++++++++++++-
>   3 files changed, 61 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
> index f590afc..330ee04 100644
> --- a/arch/arm/mach-omap2/serial.c
> +++ b/arch/arm/mach-omap2/serial.c
> @@ -357,14 +357,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
>   	omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
>   	omap_up.autosuspend_timeout = info->autosuspend_timeout;
>
> -	/* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
> -	if (!cpu_is_omap2420()&&  !cpu_is_ti816x())
> -		omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
> -
> -	/* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
> -	if (cpu_is_omap34xx() || cpu_is_omap3630())
> -		omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
> -
>   	pdata =&omap_up;
>   	pdata_size = sizeof(struct omap_uart_port_info);
>
> diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
> index 9ff4444..1a52725 100644
> --- a/arch/arm/plat-omap/include/plat/omap-serial.h
> +++ b/arch/arm/plat-omap/include/plat/omap-serial.h
> @@ -65,7 +65,6 @@ struct omap_uart_port_info {
>   	bool			dma_enabled;	/* To specify DMA Mode */
>   	unsigned int		uartclk;	/* UART clock rate */
>   	upf_t			flags;		/* UPF_* flags */
> -	u32			errata;
>   	unsigned int		dma_rx_buf_size;
>   	unsigned int		dma_rx_timeout;
>   	unsigned int		autosuspend_timeout;
> diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
> index f809041..c7666d6 100644
> --- a/drivers/tty/serial/omap-serial.c
> +++ b/drivers/tty/serial/omap-serial.c
> @@ -44,6 +44,13 @@
>   #include<plat/dmtimer.h>
>   #include<plat/omap-serial.h>
>
> +#define UART_BUILD_REVISION(x, y)	(((x)<<  8) | (y))
> +
> +#define OMAP_UART_REV_42 0x0402
> +#define OMAP_UART_REV_46 0x0406
> +#define OMAP_UART_REV_52 0x0502
> +#define OMAP_UART_REV_63 0x0603
> +
>   #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
>
>   /* SCR register bitmasks */
> @@ -1346,6 +1353,58 @@ static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
>   	return;
>   }
>
> +static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
> +{
> +	u32 mvr, scheme;
> +	u16 revision, major, minor;
> +
> +	mvr = serial_in(up, UART_OMAP_MVER);
> +
> +	/* Check revision register scheme */
> +	scheme = mvr&  (0x03<<  30);
> +	scheme>>= 30;

Minor nit-pick, why not just ...

	scheme = mvr >> 30;

> +	switch (scheme) {
> +	case 0: /* Legacy Scheme: OMAP2/3 */
> +		/* MINOR_REV[0:4], MAJOR_REV[4:7] */

Same scheme applies to OMAP1 devices too. So maybe we should include in 
the comment.

> +		major = (mvr&  0xf0)>>  4;
> +		minor = (mvr&  0x0f);
> +		break;
> +	case 1:
> +		/* New Scheme: OMAP4+ */
> +		/* MINOR_REV[0:5], MAJOR_REV[8:10] */
> +		major = (mvr&  0x7<<  8)>>  8;

Nit-pick ...

	major = (mvr >> 8) & 0x7;

> +		minor = (mvr&  0x3f);
> +		break;
> +	default:
> +		dev_warn(&up->pdev->dev,
> +			"Unknown %s revision, defaulting to highest\n",
> +			up->name);
> +		/* highest possible revision */
> +		major = 0xff;
> +		minor = 0xff;
> +	}
> +
> +	/* normalize revision for the driver */
> +	revision = UART_BUILD_REVISION(major, minor);
> +
> +	switch (revision) {
> +	case OMAP_UART_REV_46:
> +		up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
> +				UART_ERRATA_i291_DMA_FORCEIDLE);
> +		break;
> +	case OMAP_UART_REV_52:
> +		up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
> +				UART_ERRATA_i291_DMA_FORCEIDLE);
> +		break;
> +	case OMAP_UART_REV_63:
> +		up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
> +		break;
> +	default:
> +		break;
> +	}

Should we also warn on an unknown revision?

> +}
> +
>   static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
>   {
>   	struct omap_uart_port_info *omap_up_info;
> @@ -1443,7 +1502,6 @@ static int serial_omap_probe(struct platform_device *pdev)
>   						"%d\n", DEFAULT_CLK_SPEED);
>   	}
>   	up->uart_dma.uart_base = mem->start;
> -	up->errata = omap_up_info->errata;
>
>   	if (omap_up_info->dma_enabled) {
>   		up->uart_dma.uart_dma_tx = dma_tx->start;
> @@ -1473,6 +1531,8 @@ static int serial_omap_probe(struct platform_device *pdev)
>   	pm_runtime_enable(&pdev->dev);
>   	pm_runtime_get_sync(&pdev->dev);
>
> +	omap_serial_fill_features_erratas(up);
> +
>   	ui[up->port.line] = up;
>   	serial_omap_add_console_port(up);
>


From paul.gortmaker at windriver.com  Wed Mar 28 11:59:41 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Wed, 28 Mar 2012 11:59:41 -0400
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <20120328152743.GW3232@opensource.wolfsonmicro.com>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
 <20120328152743.GW3232@opensource.wolfsonmicro.com>
Message-ID: <4F73356D.5080401@windriver.com>

On 12-03-28 11:27 AM, Mark Brown wrote:
> On Wed, Mar 28, 2012 at 05:21:59PM +0200, Igor Grinberg wrote:
>> On 03/09/12 00:06, Paul Gortmaker wrote:
> 
>>> +REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer", "vcc gps");
> 
>> If you make this:
>> REGULATOR_CONSUMER(ldo3, NULL, "vcc gps");
> 
>>> +REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer", "vcc gprs");
>>
>> and this:
>> REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs");
> 
> These don't look like good fixes, you should be specifying the
> dev_name() for the consumer device?  Presumably it's two separate
> consumers and should be .0 and .1 or something?

Here is what I meant when I said in my v2 comment that there was
naming overlap, and that I wasn't sure what impact that had.

The two consumers are:

static struct platform_device em_x270_gps_userspace_consumer = {
        .name           = "reg-userspace-consumer",
        .id             = 0,
        .dev            = {
                .platform_data = &em_x270_gps_consumer_data,
        },
};

and 

static struct platform_device em_x270_gprs_userspace_consumer = {
        .name           = "reg-userspace-consumer",
        .id             = 1,
        .dev            = {
                .platform_data = &em_x270_gprs_consumer_data,
        }
};

Note that the existing names currently don't incorporate the .id
field as a suffix, and so never were unique.

Paul.



From broonie at opensource.wolfsonmicro.com  Wed Mar 28 12:13:05 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 17:13:05 +0100
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <4F73356D.5080401@windriver.com>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
 <20120328152743.GW3232@opensource.wolfsonmicro.com>
 <4F73356D.5080401@windriver.com>
Message-ID: <20120328161305.GZ3232@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 11:59:41AM -0400, Paul Gortmaker wrote:
> On 12-03-28 11:27 AM, Mark Brown wrote:

> static struct platform_device em_x270_gps_userspace_consumer = {
>         .name           = "reg-userspace-consumer",
>         .id             = 0,

> static struct platform_device em_x270_gprs_userspace_consumer = {
>         .name           = "reg-userspace-consumer",
>         .id             = 1,

> Note that the existing names currently don't incorporate the .id
> field as a suffix, and so never were unique.

No, this is just a basic part of how platform devices work - the device
name is always the same and if you've got more than one of them they get
different .ids.  dev_name() returns name.id, or just name if id is set
to -1 indicating that there's onyl one device of a given type.
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From alexg at meprolight.com  Wed Mar 28 12:31:04 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Wed, 28 Mar 2012 18:31:04 +0200
Subject: [PATCH] mfd: mc13xxx: add I2C support fix building for v3.4
In-Reply-To: <20120328144017.GV3232@opensource.wolfsonmicro.com>
References: <1332943273-22447-1-git-send-email-alexg@meprolight.com>,
 <20120328144017.GV3232@opensource.wolfsonmicro.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD25@MEP-EXCH.meprolight.com>


On Wed, Mar 28, 2012 at 04:01:13PM +0200, Alex Gershgorin wrote:

> index c3fbc5e..2119732 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -577,6 +577,8 @@ config MFD_MC13XXX
>       depends on SPI_MASTER || I2C
>       select MFD_CORE
>       select MFD_MC13783
> +     select REGMAP_I2C if I2C
> +     select REGMAP_SPI if SPI_MASTER
>       help
>         Enable support for the Freescale MC13783 and MC13892 PMICs.
>         This driver provides common support for accessing the device,

> > I'd really expect this to be squashed into the patches adding the regmap
> > usage for I2C and SPI, how can those patches work without this?

You ask me about another solution?
 
> diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
> index 31dbf91..5a60273 100644
> --- a/drivers/mfd/mc13xxx-core.c
> +++ b/drivers/mfd/mc13xxx-core.c
> @@ -616,7 +616,7 @@ static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
>  #ifdef CONFIG_OF
>  static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
>  {
> -     struct device_node *np = mc13xxx->dev.of_node;
> +     struct device_node *np = mc13xxx->dev->of_node;

> >This looks like it should be submitted properly as a bug fix for
> >inclusion on 3.4 or squashed into whatever change introduces the issue
> >if it's not present in 3.4.

Ok 

  




From broonie at opensource.wolfsonmicro.com  Wed Mar 28 12:35:13 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 17:35:13 +0100
Subject: [PATCH] mfd: mc13xxx: add I2C support fix building for v3.4
In-Reply-To: <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD25@MEP-EXCH.meprolight.com>
References: <1332943273-22447-1-git-send-email-alexg@meprolight.com>
 <20120328144017.GV3232@opensource.wolfsonmicro.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD25@MEP-EXCH.meprolight.com>
Message-ID: <20120328163512.GB3232@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 06:31:04PM +0200, Alex Gershgorin wrote:
> On Wed, Mar 28, 2012 at 04:01:13PM +0200, Alex Gershgorin wrote:

> > +     select REGMAP_I2C if I2C
> > +     select REGMAP_SPI if SPI_MASTER

> > > I'd really expect this to be squashed into the patches adding the regmap
> > > usage for I2C and SPI, how can those patches work without this?

> You ask me about another solution?

I'm saying either I'm missing something or this needs to be fixed in the
patches that introduce the regmap usage.
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From jon-hunter at ti.com  Wed Mar 28 12:36:27 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Wed, 28 Mar 2012 11:36:27 -0500
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used
 OMAP4 onwards
In-Reply-To: <alpine.DEB.2.00.1203272039010.22961@utopia.booyaka.com>
References: <1332842311-12308-1-git-send-email-rnayak@ti.com>
 <4F721A91.7000102@ti.com>
 <alpine.DEB.2.00.1203272039010.22961@utopia.booyaka.com>
Message-ID: <4F733E0B.2020901@ti.com>

Hi Paul,

On 3/27/2012 21:39, Paul Walmsley wrote:
> Hi Jon,
>
> On Tue, 27 Mar 2012, Jon Hunter wrote:
>
>> On 3/27/2012 4:58, Rajendra Nayak wrote:
>>
>>> diff --git a/arch/arm/mach-omap2/omap_hwmod.c
>>> b/arch/arm/mach-omap2/omap_hwmod.c
>>> index 8ac26f2..f2a9afa 100644
>>> --- a/arch/arm/mach-omap2/omap_hwmod.c
>>> +++ b/arch/arm/mach-omap2/omap_hwmod.c
>>> @@ -808,7 +808,7 @@ static void _enable_module(struct omap_hwmod *oh)
>>>     */
>>>    static int _omap4_wait_target_disable(struct omap_hwmod *oh)
>>>    {
>>> -	if (!cpu_is_omap44xx())
>>> +	if (cpu_is_omap24xx() || cpu_is_omap34xx())
>>>    		return 0;
>>
>> What about omap36xx?
>
> Unfortunately, cpu_is_omap34xx() also covers OMAP36xx :-(

Thanks. Is that still the case when MULTI_OMAP2 is defined? I can see if 
it is not define then it will always return 1 for all OMAP3, but for 
MULTI_OMAP2 it did not seem to me that it would. May be I should test ...

Cheers
Jon


From jon-hunter at ti.com  Wed Mar 28 12:43:48 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Wed, 28 Mar 2012 11:43:48 -0500
Subject: [PATCH 1/3] OMAP2+: UART: Remove cpu checks for populating errata
 flags
In-Reply-To: <CAMrsUdKfsoks4fB4GhrRcEur8niJsaWuYGE34+j5Bk6u2XiZQQ@mail.gmail.com>
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
 <1332325501-10467-2-git-send-email-govindraj.raja@ti.com>
 <4F722C63.9080900@ti.com>
 <CAMrsUdKfsoks4fB4GhrRcEur8niJsaWuYGE34+j5Bk6u2XiZQQ@mail.gmail.com>
Message-ID: <4F733FC4.9010506@ti.com>

Hi Govindraj,

On 3/28/2012 6:09, Raja, Govindraj wrote:
> On Wed, Mar 28, 2012 at 2:38 AM, Jon Hunter<jon-hunter at ti.com>  wrote:
>> Hi Govindraj,
>>
>>
>> On 3/21/2012 5:24, Govindraj.R wrote:
>>>
>>> From: "Govindraj.R"<govindraj.raja at ti.com>
>>>
>>> Currently the errata is populated based on cpu checks this can
>>> be removed and replaced with module version check of uart ip block.
>>> MVR reg is provided within the uart reg map use the same
>>> to populate the errata and thus now errata population and handling
>>> can be managed within the driver itself.
>>>
>>> Cc: Paul Walmsley<paul at pwsan.com>
>>> Cc: Kevin Hilman<khilman at ti.com>
>>> Signed-off-by: Felipe Balbi<balbi at ti.com>
>>> Signed-off-by: Govindraj.R<govindraj.raja at ti.com>
>>> ---
>>>   arch/arm/mach-omap2/serial.c                  |    8 ---
>>>   arch/arm/plat-omap/include/plat/omap-serial.h |    1 -
>>>   drivers/tty/serial/omap-serial.c              |   62
>>> ++++++++++++++++++++++++-
>>>   3 files changed, 61 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
>>> index f590afc..330ee04 100644
>>> --- a/arch/arm/mach-omap2/serial.c
>>> +++ b/arch/arm/mach-omap2/serial.c
>>> @@ -357,14 +357,6 @@ void __init omap_serial_init_port(struct
>>> omap_board_data *bdata,
>>>         omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
>>>         omap_up.autosuspend_timeout = info->autosuspend_timeout;
>>>
>>> -       /* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
>>> -       if (!cpu_is_omap2420()&&    !cpu_is_ti816x())
>>>
>>> -               omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
>>> -
>>> -       /* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
>>> -       if (cpu_is_omap34xx() || cpu_is_omap3630())
>>> -               omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
>>> -
>>>         pdata =&omap_up;
>>>         pdata_size = sizeof(struct omap_uart_port_info);
>>>
>>> diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h
>>> b/arch/arm/plat-omap/include/plat/omap-serial.h
>>> index 9ff4444..1a52725 100644
>>> --- a/arch/arm/plat-omap/include/plat/omap-serial.h
>>> +++ b/arch/arm/plat-omap/include/plat/omap-serial.h
>>> @@ -65,7 +65,6 @@ struct omap_uart_port_info {
>>>         bool                    dma_enabled;    /* To specify DMA Mode */
>>>         unsigned int            uartclk;        /* UART clock rate */
>>>         upf_t                   flags;          /* UPF_* flags */
>>> -       u32                     errata;
>>>         unsigned int            dma_rx_buf_size;
>>>         unsigned int            dma_rx_timeout;
>>>         unsigned int            autosuspend_timeout;
>>> diff --git a/drivers/tty/serial/omap-serial.c
>>> b/drivers/tty/serial/omap-serial.c
>>> index f809041..c7666d6 100644
>>> --- a/drivers/tty/serial/omap-serial.c
>>> +++ b/drivers/tty/serial/omap-serial.c
>>> @@ -44,6 +44,13 @@
>>>   #include<plat/dmtimer.h>
>>>   #include<plat/omap-serial.h>
>>>
>>> +#define UART_BUILD_REVISION(x, y)      (((x)<<    8) | (y))
>>> +
>>> +#define OMAP_UART_REV_42 0x0402
>>> +#define OMAP_UART_REV_46 0x0406
>>> +#define OMAP_UART_REV_52 0x0502
>>> +#define OMAP_UART_REV_63 0x0603
>>> +
>>>   #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
>>>
>>>   /* SCR register bitmasks */
>>> @@ -1346,6 +1353,58 @@ static void uart_tx_dma_callback(int lch, u16
>>> ch_status, void *data)
>>>         return;
>>>   }
>>>
>>> +static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
>>> +{
>>> +       u32 mvr, scheme;
>>> +       u16 revision, major, minor;
>>> +
>>> +       mvr = serial_in(up, UART_OMAP_MVER);
>>> +
>>> +       /* Check revision register scheme */
>>> +       scheme = mvr&    (0x03<<    30);
>>> +       scheme>>= 30;
>>
>>
>> Minor nit-pick, why not ...
>>
>>         scheme = mvr>>  30;
>>
>
> yes will correct it.

Thinking some more, could be better to add some #defines for 
OMAP_MVR_VERSION_MASK/SHIFT here.

>>
>>> +       switch (scheme) {
>>> +       case 0: /* Legacy Scheme: OMAP2/3 */
>>> +               /* MINOR_REV[0:4], MAJOR_REV[4:7] */
>>
>>
>> This scheme is also true from OMAP1 devices. Maybe we could include in the
>> comment.
>
> No omap1 from $SUBJECT also reason,
>
> mach-omap1/serial.c =>  8250.c
> mach-omap2/serial.c =>  omap-serial.c

Got it! Thanks.

>>> +               major = (mvr&    0xf0)>>    4;
>>> +               minor = (mvr&    0x0f);
>>>
>>> +               break;
>>> +       case 1:
>>> +               /* New Scheme: OMAP4+ */
>>> +               /* MINOR_REV[0:5], MAJOR_REV[8:10] */
>>> +               major = (mvr&    0x7<<    8)>>    8;
>>
>>
>> Nit-pick ...
>>
>>         major = (mvr>>  8)&  0x7;
>
> yes fine will correct this.

May be we should add #defines here to for OMAP_UART_MVR1_MAJ_MASK/SHIFT, 
OMAP_UART_MVR1_MIN_MASK/SHIFT, OMAP_UART_MVR2_MAJ_MASK/SHIFT and 
OMAP_UART_MVR2_MIN_MASK/SHIFT.

Jon


From paul.gortmaker at windriver.com  Wed Mar 28 12:59:39 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Wed, 28 Mar 2012 12:59:39 -0400
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <20120328161305.GZ3232@opensource.wolfsonmicro.com>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
 <20120328152743.GW3232@opensource.wolfsonmicro.com>
 <4F73356D.5080401@windriver.com>
 <20120328161305.GZ3232@opensource.wolfsonmicro.com>
Message-ID: <4F73437B.6070806@windriver.com>

On 12-03-28 12:13 PM, Mark Brown wrote:
> On Wed, Mar 28, 2012 at 11:59:41AM -0400, Paul Gortmaker wrote:
>> On 12-03-28 11:27 AM, Mark Brown wrote:
> 
>> static struct platform_device em_x270_gps_userspace_consumer = {
>>         .name           = "reg-userspace-consumer",
>>         .id             = 0,
> 
>> static struct platform_device em_x270_gprs_userspace_consumer = {
>>         .name           = "reg-userspace-consumer",
>>         .id             = 1,
> 
>> Note that the existing names currently don't incorporate the .id
>> field as a suffix, and so never were unique.
> 
> No, this is just a basic part of how platform devices work - the device
> name is always the same and if you've got more than one of them they get
> different .ids.  dev_name() returns name.id, or just name if id is set
> to -1 indicating that there's onyl one device of a given type.

OK, so Igor - can you simply retest the v2 patch, but make the
two trivial changes:

-REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer", "vcc gps");
+REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer.0", "vcc gps");

-REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer", "vcc gprs");
+REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer.1", "vcc gprs");

Thanks,
Paul.


From k.lewandowsk at samsung.com  Wed Mar 28 13:03:28 2012
From: k.lewandowsk at samsung.com (Karol Lewandowski)
Date: Wed, 28 Mar 2012 19:03:28 +0200
Subject: [PATCH v4 2/2] regulator: add device tree support for max8997
In-Reply-To: <1332582590-16382-3-git-send-email-thomas.abraham@linaro.org>
References: <1332582590-16382-1-git-send-email-thomas.abraham@linaro.org>
 <1332582590-16382-3-git-send-email-thomas.abraham@linaro.org>
Message-ID: <4F734460.4060605@samsung.com>

On 24.03.2012 10:49, Thomas Abraham wrote:

Hi Thomas!

> Add device tree based discovery support for max8997.
... 
> +Regulators: The regulators of max8997 that have to be instantiated should be
> +included in a sub-node named 'regulators'. Regulator nodes included in this
> +sub-node should be of the format as below. Note: The 'n' in LDOn and BUCKn
> +represents the LDO or BUCK number as per the datasheet of max8997.
> +
> +    For LDO's:
> +		LDOn {
> +			standard regulator bindings here
> +		};
> +
> +    For BUCK's:
> +		BUCKn {
> +			standard regulator bindings here
> +		};
> +


Small note - driver supports[1] configuring following regulators by
using respective DT node names:

 - EN32KHz_AP
 - EN32KHz_CP
 - ENVICHG
 - ESAFEOUT1
 - ESAFEOUT2
 - CHARGER
 - CHARGER_CV
 - CHARGER_TOPOFF

I wonder if these should be mentioned in documentation too.

[1] These are used in e.g. mach-nuri.c

> diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c> index 9657929..dce8aaf 100644

> --- a/drivers/regulator/max8997.c
> +++ b/drivers/regulator/max8997.c
..
> +static int max8997_pmic_dt_parse_pdata(struct max8997_dev *iodev,
> +					struct max8997_platform_data *pdata)
> +{
> +	struct device_node *pmic_np, *regulators_np, *reg_np;
> +	struct max8997_regulator_data *rdata;
> +	unsigned int i, dvs_voltage_nr = 1, ret;
> +
> +	pmic_np = iodev->dev->of_node;
> +	if (!pmic_np) {
> +		dev_err(iodev->dev, "could not find pmic sub-node\n");
> +		return -ENODEV;
> +	}
> +
> +	regulators_np = of_find_node_by_name(pmic_np, "regulators");
> +	if (!regulators_np) {
> +		dev_err(iodev->dev, "could not find regulators sub-node\n");
> +		return -EINVAL;
> +	}
> +
> +	/* count the number of regulators to be supported in pmic */
> +	pdata->num_regulators = 0;
> +	for_each_child_of_node(regulators_np, reg_np)
> +		pdata->num_regulators++;
> +
> +	rdata = devm_kzalloc(iodev->dev, sizeof(*rdata) *
> +				pdata->num_regulators, GFP_KERNEL);
> +	if (!rdata) {
> +		dev_err(iodev->dev, "could not allocate memory for "
> +						"regulator data\n");
> +		return -ENOMEM;
> +	}

> +	pdata->regulators = rdata;

> +	for_each_child_of_node(regulators_np, reg_np) {
> +		for (i = 0; i < ARRAY_SIZE(regulators); i++)
> +			if (!of_node_cmp(reg_np->name, regulators[i].name))
> +				break;
> +		rdata->id = i;


rdata->id will be equal to ARRAY_SIZE(regulators) when one adds DT node
name (below "regulators") which is different from what can be found in
regulators[] table.

On my test machine this results in hard lockup - possibly because
something tries to access regulators[ARRAY_SIZE(regulators)]
later on.

Following patch fixes this on my machine (using DTS with misspelled LDO1 for LDx1):

diff --git a/drivers/regulator/max8997.c b/drivers/regulator/max8997.c
index dce8aaf..c20fd72 100644
--- a/drivers/regulator/max8997.c
+++ b/drivers/regulator/max8997.c
@@ -1011,6 +1011,13 @@ static int max8997_pmic_dt_parse_pdata(struct max8997_dev *iodev,
                for (i = 0; i < ARRAY_SIZE(regulators); i++)
                        if (!of_node_cmp(reg_np->name, regulators[i].name))
                                break;
+
+               if (i == ARRAY_SIZE(regulators)) {
+                       dev_warn(iodev->dev, "don't know how to configure regulator %s\n",
+                                reg_np->name);
+                       continue;
+               }
+
                rdata->id = i;
                rdata->initdata = of_get_regulator_init_data(
                                                iodev->dev, reg_np);


Regards,
-- 
Karol Lewandowski | Samsung Poland R&D Center | Linux/Platform


From mturquette at ti.com  Wed Mar 28 13:08:56 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 28 Mar 2012 10:08:56 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <4F728050.9030904@codeaurora.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
 <4F6946AA.4070201@codeaurora.org> <4F6CEC0C.4060704@codeaurora.org>
 <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>
 <4F6CF555.4080109@codeaurora.org>
 <CAJOA=zOnR1NwZ1Cmkfb+b7f7=N_vg+txAUqKXF2Nf2nVYFMjjg@mail.gmail.com>
 <4F6D0167.3040704@codeaurora.org>
 <CAJOA=zM47mB8tY2hV1QDVm1GZRqQrjrktkbLQ-Vp7hBjA8H5xg@mail.gmail.com>
 <4F728050.9030904@codeaurora.org>
Message-ID: <CAJOA=zM0_czNzdqXfJDn8vzfpVLywBvYTg3SxKs6BHUOsRNd9w@mail.gmail.com>

On Tue, Mar 27, 2012 at 8:06 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
> On 03/23/2012 04:28 PM, Turquette, Mike wrote:
>> On Fri, Mar 23, 2012 at 4:04 PM, Saravana Kannan<skannan at codeaurora.org>
>> ?wrote:
>>> On 03/23/2012 03:32 PM, Turquette, Mike wrote:
>>> How does a child (or grand child) clock (not a driver using the clock)
>>> reject a rate change if it know it can't handle that freq from the
>>> parent? I
>>> won't claim to know this part of the code thoroughly, but I can't find an
>>> easy way to do this.
>>
>>
>> Technically you could subscribe a notifier to your grand-child clock,
>> even if there is no driver for it. ?The same code that implements your
>> platform's clock operations could register the notifier handler.
>
>>
>>
>> You can see how this works in clk_propagate_rate_change. ?That usage
>> is certainly targeted more at drivers but could be made to work for
>> your case. ?Let me know what you think; this is an interesting issue.
>
>
> I think notifications should be left to drivers. Notifications are too heavy
> handed for enforcing requirements of the clock tree.

Agreed.  I'm working on a "clock dependency" design at the moment,
which should hopefully answer your question.

> Also, clk_hw to clk
> might no longer be a 1-1 mapping in the future. It's quite possible that
> each clk_get() would get a different struct clk based on the caller to keep
> track of their constraints separately. So, clock drivers shouldn't ever use
> them to identify a clock.

I'm also working on this same thing!  Lots to keep me busy these days.

snip

> I think there is still a problem with not being able to differentiate
> between pre-change recalc and post-change recalc. This applies for any set
> parent and set rate on a clock that has children.
>
> Consider this simple example:
> * Divider clock B is fed from clock A.
> * Clock B can never output > 120 MHz due to downstream
> ?HW/clock limitations.
> * Clock A is running at 200 MHz
> * Clock B divider is set to 2.
>
> Now, say the rate of clock A is changing from 200 MHz to 300 MHz (due to set
> rate or set parent). In this case, the clock B divider should be set to 3
> pre-rate change to guarantee that the output of clock B is never > 120 MHz.
> So the rate of clock B will go from 100 MHz (200/2) to 66 MHz (200/3) to 100
> MHz (300/3) and everything is good.
>
> Assume we somehow managed to do the above. So, now clock A is at 300 MHz,
> clock B divider is at 3 and the clock B output is 100 MHz.
>
> Now, say the rate of clock A changes from 300 MHz to 100 MHz. In this case
> the clock B divider should only be changed post rate change. If we do it pre
> rate change, then the output will go from 100 MHz (300/3) to 150 MHz (300/1)
> to 100 MHz (100/1). We went past the 120 MHz limit of clock B's output rate.
>
> If we do this post rate change, we can do this without exceeding the max
> output limit of clock B. It will go from 100 MHz (300/3) to 33 MHz (100/3)
> to 100 MHz (100/1). We never went past the 120 MHz limit.
>
> So, at least for this reason above, I think we need to pass a pre/post
> parameter to the recalc ops.
>
> While we are at it, we should probably just add a failure option for recalc
> to make it easy to reject unacceptable rate changes. To keep the clock
> framework code simpler, you could decide to allow errors only for the
> pre-change recalc calls. That way, the error case roll back code won't be
> crazy.

recalc is too late to catch this.  I think you mean round_rate.  We
want to determine which rate changes are out-of-spec during
clk_calc_new_rates (for clk_set_rate) which involves round_rate being
a bit smarter about what it can and cannot do.

Anyways I'm looking at ways to do this in my clk-dependencies branch.

Regards,
Mike


From olof at lixom.net  Wed Mar 28 13:12:59 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 28 Mar 2012 10:12:59 -0700
Subject: [GIT PULL] pull request from arch-pxa git on fixes branch
In-Reply-To: <4F732D14.3020803@compulab.co.il>
References: <CAN1soZytJ-CxepQAZn5oZ06=ezTQ85O-iC7tUDOeWqi=zpuf8A@mail.gmail.com>
 <4F732D14.3020803@compulab.co.il>
Message-ID: <CAOesGMgxq-HEeKSPvaW-kTLqNyDJUUmG0OEpockMBNninQL0wQ@mail.gmail.com>

Hi,

On Wed, Mar 28, 2012 at 8:24 AM, Igor Grinberg <grinberg at compulab.co.il> wrote:

> Can Paul's patch [1] be included in this or later request?
>
> Thanks.
>
> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/091750.html

Yes, Haojian, please add that to the branch (with the proposed fixups)
as well so we can pick it up and send it in ASAP. Both are broken
today in Russell's PXA defconfig.

There is one more failure as well, that I haven't seen a patch posted for:

arch/arm/mach-pxa/cm-x300.c:716:3: error: unknown field 'dev'
specified in initializer



-Olof


From mturquette at ti.com  Wed Mar 28 13:18:24 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 28 Mar 2012 10:18:24 -0700
Subject: [PATCH 02/10] clk: remove unnecessary EXPORT_SYMBOL_GPL
In-Reply-To: <20120328054233.GA2954@lunn.ch>
References: <20120327092828.GA16397@lunn.ch>
 <20120327131002.GC3719@S2101-09.ap.freescale.net>
 <CAJOA=zMEtyYuPwSAnnJ2PUnymkn-QWD7rJaymemH5on21EB4Sw@mail.gmail.com>
 <20120328054233.GA2954@lunn.ch>
Message-ID: <CAJOA=zOR1PQ7WmKve8uBBtMr=zvDToHp5y_bm4Piigio7x7n_w@mail.gmail.com>

On Tue, Mar 27, 2012 at 10:42 PM, Andrew Lunn <andrew at lunn.ch> wrote:
>> > I have a similar need for clk_divider_ops calls. ?Instead of exporting
>> > every single clk_gate_ops call, we should just export "struct clk_ops
>> > clk_gate_ops". ?That's exactly why I have the patch #4 here.
>>
>> Andrew, does this approach work for you? ?I prefer it over the EXPORT madness.
>
> Hi Mike
>
> I think so. I'm waiting for the first 3.4 RC to come out so I've not
> tried implementing it yet.

In that case I'm going to roll it into my fixes branch.  I want to
send that branch to Arnd ASAP so I can't afford to wait on feedback
from -rc1.  Please do shout if you find it problematic after -rc1,
though.

Thanks,
Mike


From linus.walleij at linaro.org  Wed Mar 28 13:37:12 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Wed, 28 Mar 2012 19:37:12 +0200
Subject: [PATCH] ARM: ux500: fix compile error in new timer code
In-Reply-To: <1332931787-27741-1-git-send-email-lee.jones@linaro.org>
References: <1332931787-27741-1-git-send-email-lee.jones@linaro.org>
Message-ID: <CACRpkdbi3JM_iGmWiV9pF0Pff+p9_4taw1aQOpgzprgrnLFdWQ@mail.gmail.com>

On Wed, Mar 28, 2012 at 12:49 PM, Lee Jones <lee.jones at linaro.org> wrote:

> This patch fixes the errors below:
>
> error: implicit declaration of function ?pr_err?
> error: implicit declaration of function ?BUG?
>
> Signed-off-by: Lee Jones <lee.jones at linaro.org>

Acked-by: Linus Walleij <linus.walleij at linaro.org>

I'll apply and funnel to ARM-SoC when I'm back in Europe unless
you want to push it to Arnd/Olof directly.

Thanks,
Linus Walleij


From alexg at meprolight.com  Wed Mar 28 13:38:56 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Wed, 28 Mar 2012 19:38:56 +0200
Subject: [PATCH] mfd: mc13xxx: add I2C support fix building for v3.4
In-Reply-To: <20120328163512.GB3232@opensource.wolfsonmicro.com>
References: <1332943273-22447-1-git-send-email-alexg@meprolight.com>
 <20120328144017.GV3232@opensource.wolfsonmicro.com>
 <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD25@MEP-EXCH.meprolight.com>,
 <20120328163512.GB3232@opensource.wolfsonmicro.com>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD26@MEP-EXCH.meprolight.com>

 
> You ask me about another solution?

> > I'm saying either I'm missing something or this needs to be fixed in the
> > patches that introduce the regmap usage.

You understood correctly, it took me time to understand :-)
No problem I can split this patch:

> > +     select REGMAP_I2C if I2C
> > +     select REGMAP_SPI if SPI_MASTER

It will go to  v4 mfd: mc13xxx-core: use regmap for register access, 

Only the second part will be in this patch

-	struct device_node *np = mc13xxx->dev.of_node;
+	struct device_node *np = mc13xxx->dev->of_node;

 










From tony at atomide.com  Wed Mar 28 13:03:17 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 28 Mar 2012 10:03:17 -0700
Subject: [PATCH 05/12] Add dummy smsc911x regulators to cm-t35.
In-Reply-To: <4F72B0D0.70703@compulab.co.il>
References: <1332494504-10251-1-git-send-email-Russ.Dill@ti.com>
 <1332494504-10251-6-git-send-email-Russ.Dill@ti.com>
 <4F71E290.2050403@compulab.co.il>
 <20120327172819.GQ9859@atomide.com> <4F72B0D0.70703@compulab.co.il>
Message-ID: <20120328170316.GR9859@atomide.com>

* Igor Grinberg <grinberg at compulab.co.il> [120327 23:36]:
> Hi Tony,
> 
> On 03/27/12 19:28, Tony Lindgren wrote:
> > * Igor Grinberg <grinberg at compulab.co.il> [120327 08:56]:
> >> Hi Russ,
> >>
> >> This patch works, but can we, please use the attached patch instead?
> > 
> > Hmm what's the difference here? Do you have some real controllable
> > regulator for one of the smsc911x instances?
> 
> Well, the difference here is that those regulators will only be present
> if the smsc911x controllers are present and their initialization is done
> along with the controllers.
> Also, I want to separate the cm-t35 from sb-t35 for future easier
> refactoring of the sb-t35 code so it can be reused also on cm-t3517.
> 
> Only vddvario for smsc911x.0 is controllable - connected to VIO, but
> VIO will never be disabled as it also controls many other devices
> (DRAM is among them), so I prefer it to be dummy and keep it together
> with vdd33a.

OK thanks for the clarification. 

> > Anyways, I take it that you have tested that both smsc911x interfaces
> > work now?
> 
> Yes, both regulators are registered and found by the smsc911x driver.
> There is some kind of problem with the smsc911x.1, but it looks unrelated
> to the patch:

OK good to hear. Regarding the following problem..
 
> smsc911x: Driver version 2008-10-21
> irq 323: nobody cared (try booting with the "irqpoll" option)
> [<c001ae6c>] (unwind_backtrace+0x0/0xfc) from [<c0088960>] (__report_bad_irq+0x28/0xbc)
> [<c0088960>] (__report_bad_irq+0x28/0xbc) from [<c0088bd4>] (note_interrupt+0x1e0/0x230)
> [<c0088bd4>] (note_interrupt+0x1e0/0x230) from [<c0086e48>] (handle_irq_event_percpu+0xb0/0x1a0)
> [<c0086e48>] (handle_irq_event_percpu+0xb0/0x1a0) from [<c0086f74>] (handle_irq_event+0x3c/0x5c)
> [<c0086f74>] (handle_irq_event+0x3c/0x5c) from [<c00895a0>] (handle_level_irq+0x90/0xfc)
> [<c00895a0>] (handle_level_irq+0x90/0xfc) from [<c008699c>] (generic_handle_irq+0x38/0x40)
> [<c008699c>] (generic_handle_irq+0x38/0x40) from [<c02635a0>] (gpio_irq_handler+0x1b0/0x20c)
> [<c02635a0>] (gpio_irq_handler+0x1b0/0x20c) from [<c008699c>] (generic_handle_irq+0x38/0x40)
> [<c008699c>] (generic_handle_irq+0x38/0x40) from [<c0015404>] (handle_IRQ+0x38/0x84)
> [<c0015404>] (handle_IRQ+0x38/0x84) from [<c000865c>] (omap3_intc_handle_irq+0x48/0x4c)
> [<c000865c>] (omap3_intc_handle_irq+0x48/0x4c) from [<c00140c4>] (__irq_svc+0x44/0x78)
> Exception stack(0xcf02de20 to 0xcf02de68)
> de20: cf02c018 cf02c000 00000000 cf02de58 60000013 c06739fc 00000143 c06739fc
> de40: 60000013 00000508 c06739dc 00000000 00022d69 cf02de68 cf02b3c0 c04890fc
> de60: 20000013 ffffffff
> [<c00140c4>] (__irq_svc+0x44/0x78) from [<c04890fc>] (_raw_spin_unlock_irqrestore+0x64/0x68)
> [<c04890fc>] (_raw_spin_unlock_irqrestore+0x64/0x68) from [<c0087d50>] (__setup_irq+0x1b4/0x3d4)
> [<c0087d50>] (__setup_irq+0x1b4/0x3d4) from [<c00881a0>] (request_threaded_irq+0xdc/0x148)
> [<c00881a0>] (request_threaded_irq+0xdc/0x148) from [<c0482954>] (smsc911x_drv_probe+0x350/0x528)
> [<c0482954>] (smsc911x_drv_probe+0x350/0x528) from [<c02d5a8c>] (platform_drv_probe+0x18/0x1c)
> [<c02d5a8c>] (platform_drv_probe+0x18/0x1c) from [<c02d4580>] (really_probe+0x64/0x160)
> [<c02d4580>] (really_probe+0x64/0x160) from [<c02d46c4>] (driver_probe_device+0x48/0x60)
> [<c02d46c4>] (driver_probe_device+0x48/0x60) from [<c02d4770>] (__driver_attach+0x94/0x98)
> [<c02d4770>] (__driver_attach+0x94/0x98) from [<c02d2ffc>] (bus_for_each_dev+0x54/0x80)
> [<c02d2ffc>] (bus_for_each_dev+0x54/0x80) from [<c02d3730>] (bus_add_driver+0xa8/0x2a4)
> [<c02d3730>] (bus_add_driver+0xa8/0x2a4) from [<c02d4d6c>] (driver_register+0x78/0x184)
> [<c02d4d6c>] (driver_register+0x78/0x184) from [<c0008758>] (do_one_initcall+0x34/0x184)
> [<c0008758>] (do_one_initcall+0x34/0x184) from [<c0613248>] (do_basic_setup+0x34/0x40)
> [<c0613248>] (do_basic_setup+0x34/0x40) from [<c06132b8>] (kernel_init+0x64/0xec)
> [<c06132b8>] (kernel_init+0x64/0xec) from [<c00154cc>] (kernel_thread_exit+0x0/0x8)
> handlers:
> [<c032ea98>] smsc911x_irqhandler
> Disabling IRQ #323
> 
> I still haven't had a chance to look into this.
> Does anyone have a clue?

..care to see if you have OMAP_GPIO_IRQ entry for your board? If so, we're
still waiting for the cleanup-fixes branch to get merged that changes
things to use gpio_to_irq() instead.

Regards,

Tony


From linux at arm.linux.org.uk  Wed Mar 28 13:56:13 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 28 Mar 2012 18:56:13 +0100
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <20120328101852.GE3232@opensource.wolfsonmicro.com>
References: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
 <1331242494-3157-1-git-send-email-paul.gortmaker@windriver.com>
 <CAN1soZzDRR4XQ34WDL48=j+Ff8t5fsCFaccqZAKOQ1OAPeDXcA@mail.gmail.com>
 <4F608F4F.8020106@windriver.com>
 <20120314123236.GE3133@opensource.wolfsonmicro.com>
 <20120328094351.GB22414@n2100.arm.linux.org.uk>
 <20120328101852.GE3232@opensource.wolfsonmicro.com>
Message-ID: <20120328175613.GC22414@n2100.arm.linux.org.uk>

On Wed, Mar 28, 2012 at 11:18:52AM +0100, Mark Brown wrote:
> On Wed, Mar 28, 2012 at 10:43:51AM +0100, Russell King - ARM Linux wrote:
> > On Wed, Mar 14, 2012 at 12:32:36PM +0000, Mark Brown wrote:
> 
> > > Yes, that's what you should do.  Calling dev_name() is only possible if
> > > you have the struct device and removing the need for the struct device
> > > is exactly what we're trying to avoid here.
> 
> > So what the hell is happening here to fix the breakage which the
> > regulator tree caused in mainline?  From this thread, it looks like
> > it's been known about since 8th March which is now twenty days ago,
> > and it's still broken.
> 
> Yes, please at least apply Paul's patches - honestly, given how old
> these boards are and the general lack of activity I'd rather expect that
> the only thing anyone's doing with them these days is build tests.

Is that a reason to push breakage to them upstream?  No.  Please take
Paul's patches to fix the breakage which was introduced through your
tree yourself.  I've got enough problems this merge window to deal with
without having to add further patches to my tree.

Thanks.


From sshtylyov at mvista.com  Wed Mar 28 14:04:05 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 28 Mar 2012 22:04:05 +0400
Subject: [PATCH 4/4] Input: pxa27x_keypad add choice to set direct_key_mask
In-Reply-To: <1332911324-9840-4-git-send-email-chao.xie@marvell.com>
References: <1332911324-9840-1-git-send-email-chao.xie@marvell.com>
 <1332911324-9840-4-git-send-email-chao.xie@marvell.com>
Message-ID: <4F735295.2010604@mvista.com>

Hello.

On 03/28/2012 09:08 AM, Chao Xie wrote:

> Direct keys usage may not start from KP_DKIN0, add a msk option
> to configure the specifics for platforms that can skip some keys.

> Signed-off-by: Chao Xie<chao.xie at marvell.com>
[...]

> diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
> index b41ebda..661892b 100644
> --- a/drivers/input/keyboard/pxa27x_keypad.c
> +++ b/drivers/input/keyboard/pxa27x_keypad.c
> @@ -391,7 +391,12 @@ static void pxa27x_keypad_config(struct pxa27x_keypad *keypad)
>   	if (pdata->direct_key_num>  direct_key_num)
>   		direct_key_num = pdata->direct_key_num;
>
> -	keypad->direct_key_mask = ((1<<  direct_key_num) - 1)&  ~mask;
> +	/* Direct keys usage may not start from KP_DKIN0, check the platfrom
> +	 * msk data to config the specific */

    The preferred multi-line comment style is not this one. You got it right in 
the previous patch. :-)

WBR, Sergei


From broonie at opensource.wolfsonmicro.com  Wed Mar 28 14:10:06 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 28 Mar 2012 19:10:06 +0100
Subject: [PATCH] ARM: pxa: fix regulator related build fail in
 magician_defconfig
In-Reply-To: <20120328175613.GC22414@n2100.arm.linux.org.uk>
References: <1331084814.11802.YahooMailClassic@web29012.mail.ird.yahoo.com>
 <1331242494-3157-1-git-send-email-paul.gortmaker@windriver.com>
 <CAN1soZzDRR4XQ34WDL48=j+Ff8t5fsCFaccqZAKOQ1OAPeDXcA@mail.gmail.com>
 <4F608F4F.8020106@windriver.com>
 <20120314123236.GE3133@opensource.wolfsonmicro.com>
 <20120328094351.GB22414@n2100.arm.linux.org.uk>
 <20120328101852.GE3232@opensource.wolfsonmicro.com>
 <20120328175613.GC22414@n2100.arm.linux.org.uk>
Message-ID: <20120328181005.GC3232@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 06:56:13PM +0100, Russell King - ARM Linux wrote:
> On Wed, Mar 28, 2012 at 11:18:52AM +0100, Mark Brown wrote:

> > Yes, please at least apply Paul's patches - honestly, given how old
> > these boards are and the general lack of activity I'd rather expect that
> > the only thing anyone's doing with them these days is build tests.

> Is that a reason to push breakage to them upstream?  No.  Please take
> Paul's patches to fix the breakage which was introduced through your
> tree yourself.  I've got enough problems this merge window to deal with
> without having to add further patches to my tree.

Well, I'd expect this stuff to be going via the pxa tree to arm-soc
rather than via your tree anyway (which seems to be what's happening at
this point) - half the point with arm-soc was to ensure you didn't have
to deal with things like this.

Quite frankly I thought the fixes had already been applied, they were
posted and reviewed in good time for the merge window and the issues
weren't being reported in -next any more; had someone asked I'd have
applied them as I did with the equivalent stuff for u300.  If they were
being totally ignored I'd probably have applied them too, though perhaps
not.
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From lost.distance at yahoo.com  Wed Mar 28 14:12:16 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Wed, 28 Mar 2012 19:12:16 +0100 (BST)
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
Message-ID: <1332958336.11131.YahooMailClassic@web29001.mail.ird.yahoo.com>

On PXA2xx platforms, the MFP API (described in Documentation/arm/pxa/mfp.txt)
provides values for the following:

1. GPIO inputs (e.g. GPIO105_GPIO).
2. Alternate function inputs (e.g. GPIO105_CIF_DD_1).
3. Alternate function outputs (e.g. GPIO105_KP_MKOUT_2).

It does not provide values for GPIO outputs (i.e. AF0 outputs).

One cannot use the macro used by the MFP API internally - MFP_CFG_OUT() - to
define new GPIO output values, since that macro is forbidden in platform code.

Without the ability to add GPIO outputs to the MFP configuration, it is not
possible to drive GPIO outputs high during sleep mode.

This would be useful, for example, on the hx4700 platform, where driving the
infrared powerdown GPIO 105 high during sleep mode would save some mA.

So my question is: what method should one use to add GPIO outputs to the MFP
configuration?

One possible method, namely manually defining values in the platform code:

	MFP_PIN_GPIO105 | MFP_AF0 | MFP_DIR_OUT | MFP_LPM_DRIVE_HIGH,

is essentially no different from using the forbidden MFP_CFG_OUT() macro.



From hartleys at visionengravers.com  Wed Mar 28 14:12:48 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 28 Mar 2012 11:12:48 -0700
Subject: [PATCH 0/5] mtd: plat_nand: Add default partition parser and use it
Message-ID: <201203281112.48788.hartleys@visionengravers.com>

This patch series adds cmdlinepart as the default partition parser for the
plat_nand driver and updates all the arch setup code to use it.

Arch setup code that requires other partition parsers can still pass that
information as chip.part_probe_types.

Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
  mtd: plat_nand: Add default partition parser to driver
  arm: Use the plat_nand default partition parser
  blackfin: Use the plat_nand default partition parser
  mips: Use the plat_nand default partition parser
  sh: Use the plat_nand default partition parser

 arch/arm/mach-ep93xx/snappercl15.c        |    3 ---
 arch/arm/mach-ep93xx/ts72xx.c             |    3 ---
 arch/arm/mach-ixp4xx/ixdp425-setup.c      |    3 ---
 arch/arm/mach-omap1/board-fsample.c       |    3 ---
 arch/arm/mach-omap1/board-h2.c            |    3 ---
 arch/arm/mach-omap1/board-h3.c            |    3 ---
 arch/arm/mach-omap1/board-perseus2.c      |    3 ---
 arch/arm/mach-orion5x/ts78xx-setup.c      |    3 ---
 arch/arm/mach-pxa/balloon3.c              |    3 ---
 arch/arm/mach-pxa/em-x270.c               |    3 ---
 arch/arm/mach-pxa/palmtx.c                |    3 ---
 arch/blackfin/mach-bf561/boards/acvilon.c |    3 ---
 arch/mips/alchemy/devboards/db1200.c      |    3 ---
 arch/mips/alchemy/devboards/db1300.c      |    3 ---
 arch/mips/alchemy/devboards/db1550.c      |    3 ---
 arch/mips/pnx833x/common/platform.c       |    6 ------
 arch/sh/boards/mach-migor/setup.c         |    1 -
 drivers/mtd/nand/plat_nand.c              |    8 ++++++--
 18 files changed, 6 insertions(+), 54 deletions(-)


From hartleys at visionengravers.com  Wed Mar 28 14:13:09 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 28 Mar 2012 11:13:09 -0700
Subject: [PATCH 2/5] arm: Use the plat_nand default partition parser
Message-ID: <201203281113.10684.hartleys@visionengravers.com>

Use the default partition parser, cmdlinepart, provided by the plat_nand driver.

Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Cc: Ryan Mallon <rmallon at gmail.com>
Cc: Imre Kaloz <kaloz at openwrt.org>
Cc: Krzysztof Halasa <khc at pm.waw.pl>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Alexander Clouter <alex at digriz.org.uk>
Cc: Nicolas Pitre <nico at fluxnic.net>
Cc: Eric Miao <eric.y.miao at gmail.com>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: Marek Vasut <marek.vasut at gmail.com>

---

diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index 0c00852..5df9092 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -82,8 +82,6 @@ static int snappercl15_nand_dev_ready(struct mtd_info *mtd)
 	return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY);
 }
 
-static const char *snappercl15_nand_part_probes[] = {"cmdlinepart", NULL};
-
 static struct mtd_partition snappercl15_nand_parts[] = {
 	{
 		.name		= "Kernel",
@@ -100,7 +98,6 @@ static struct mtd_partition snappercl15_nand_parts[] = {
 static struct platform_nand_data snappercl15_nand_data = {
 	.chip = {
 		.nr_chips		= 1,
-		.part_probe_types	= snappercl15_nand_part_probes,
 		.partitions		= snappercl15_nand_parts,
 		.nr_partitions		= ARRAY_SIZE(snappercl15_nand_parts),
 		.options		= NAND_NO_AUTOINCR,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 5ea7909..14d7121 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -105,8 +105,6 @@ static int ts72xx_nand_device_ready(struct mtd_info *mtd)
 	return !!(__raw_readb(addr) & 0x20);
 }
 
-static const char *ts72xx_nand_part_probes[] = { "cmdlinepart", NULL };
-
 #define TS72XX_BOOTROM_PART_SIZE	(SZ_16K)
 #define TS72XX_REDBOOT_PART_SIZE	(SZ_2M + SZ_1M)
 
@@ -134,7 +132,6 @@ static struct platform_nand_data ts72xx_nand_data = {
 		.nr_chips	= 1,
 		.chip_offset	= 0,
 		.chip_delay	= 15,
-		.part_probe_types = ts72xx_nand_part_probes,
 		.partitions	= ts72xx_nand_parts,
 		.nr_partitions	= ARRAY_SIZE(ts72xx_nand_parts),
 	},
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 3d742ae..fccfc73 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -60,8 +60,6 @@ static struct platform_device ixdp425_flash = {
 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
     defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
 
-const char *part_probes[] = { "cmdlinepart", NULL };
-
 static struct mtd_partition ixdp425_partitions[] = {
 	{
 		.name	= "ixp400 NAND FS 0",
@@ -101,7 +99,6 @@ static struct platform_nand_data ixdp425_flash_nand_data = {
 		.nr_chips		= 1,
 		.chip_delay		= 30,
 		.options		= NAND_NO_AUTOINCR,
-		.part_probe_types 	= part_probes,
 		.partitions	 	= ixdp425_partitions,
 		.nr_partitions	 	= ARRAY_SIZE(ixdp425_partitions),
 	},
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 80bd43c..62a1e11 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -206,14 +206,11 @@ static int nand_dev_ready(struct mtd_info *mtd)
 	return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
 }
 
-static const char *part_probes[] = { "cmdlinepart", NULL };
-
 static struct platform_nand_data nand_data = {
 	.chip	= {
 		.nr_chips		= 1,
 		.chip_offset		= 0,
 		.options		= NAND_SAMSUNG_LP_OPTIONS,
-		.part_probe_types	= part_probes,
 	},
 	.ctrl	= {
 		.cmd_ctrl	= nand_cmd_ctl,
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index c306862..a914a7d 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -200,8 +200,6 @@ static int h2_nand_dev_ready(struct mtd_info *mtd)
 	return gpio_get_value(H2_NAND_RB_GPIO_PIN);
 }
 
-static const char *h2_part_probes[] = { "cmdlinepart", NULL };
-
 static struct platform_nand_data h2_nand_platdata = {
 	.chip	= {
 		.nr_chips		= 1,
@@ -209,7 +207,6 @@ static struct platform_nand_data h2_nand_platdata = {
 		.nr_partitions		= ARRAY_SIZE(h2_nand_partitions),
 		.partitions		= h2_nand_partitions,
 		.options		= NAND_SAMSUNG_LP_OPTIONS,
-		.part_probe_types	= h2_part_probes,
 	},
 	.ctrl	= {
 		.cmd_ctrl	= h2_nand_cmd_ctl,
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 64b8584..49952b9 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -202,8 +202,6 @@ static int nand_dev_ready(struct mtd_info *mtd)
 	return gpio_get_value(H3_NAND_RB_GPIO_PIN);
 }
 
-static const char *part_probes[] = { "cmdlinepart", NULL };
-
 static struct platform_nand_data nand_platdata = {
 	.chip	= {
 		.nr_chips		= 1,
@@ -211,7 +209,6 @@ static struct platform_nand_data nand_platdata = {
 		.nr_partitions		= ARRAY_SIZE(nand_partitions),
 		.partitions		= nand_partitions,
 		.options		= NAND_SAMSUNG_LP_OPTIONS,
-		.part_probe_types	= part_probes,
 	},
 	.ctrl	= {
 		.cmd_ctrl	= nand_cmd_ctl,
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 76d4ee0..eb8b2c7 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -164,14 +164,11 @@ static int nand_dev_ready(struct mtd_info *mtd)
 	return gpio_get_value(P2_NAND_RB_GPIO_PIN);
 }
 
-static const char *part_probes[] = { "cmdlinepart", NULL };
-
 static struct platform_nand_data nand_data = {
 	.chip	= {
 		.nr_chips		= 1,
 		.chip_offset		= 0,
 		.options		= NAND_SAMSUNG_LP_OPTIONS,
-		.part_probe_types	= part_probes,
 	},
 	.ctrl	= {
 		.cmd_ctrl	= nand_cmd_ctl,
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index c96f374..53e595e 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -245,8 +245,6 @@ static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
 		readsb(io_base, buf, len);
 }
 
-const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
-
 static struct mtd_partition ts78xx_ts_nand_parts[] = {
 	{
 		.name		= "mbr",
@@ -271,7 +269,6 @@ static struct mtd_partition ts78xx_ts_nand_parts[] = {
 static struct platform_nand_data ts78xx_ts_nand_data = {
 	.chip	= {
 		.nr_chips		= 1,
-		.part_probe_types	= ts_nand_part_probes,
 		.partitions		= ts78xx_ts_nand_parts,
 		.nr_partitions		= ARRAY_SIZE(ts78xx_ts_nand_parts),
 		.chip_delay		= 15,
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index c35456f..7ece2625 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -679,8 +679,6 @@ static struct mtd_partition balloon3_partition_info[] = {
 	},
 };
 
-static const char *balloon3_part_probes[] = { "cmdlinepart", NULL };
-
 struct platform_nand_data balloon3_nand_pdata = {
 	.chip = {
 		.nr_chips	= 4,
@@ -688,7 +686,6 @@ struct platform_nand_data balloon3_nand_pdata = {
 		.nr_partitions	= ARRAY_SIZE(balloon3_partition_info),
 		.partitions	= balloon3_partition_info,
 		.chip_delay	= 50,
-		.part_probe_types = balloon3_part_probes,
 	},
 	.ctrl = {
 		.hwcontrol	= 0,
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index c1b65da..34b1cd8 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -338,8 +338,6 @@ static struct mtd_partition em_x270_partition_info[] = {
 	},
 };
 
-static const char *em_x270_part_probes[] = { "cmdlinepart", NULL };
-
 struct platform_nand_data em_x270_nand_platdata = {
 	.chip = {
 		.nr_chips = 1,
@@ -347,7 +345,6 @@ struct platform_nand_data em_x270_nand_platdata = {
 		.nr_partitions = ARRAY_SIZE(em_x270_partition_info),
 		.partitions = em_x270_partition_info,
 		.chip_delay = 20,
-		.part_probe_types = em_x270_part_probes,
 	},
 	.ctrl = {
 		.hwcontrol = 0,
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 9507605..0da35dc 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -268,8 +268,6 @@ static struct mtd_partition palmtx_partition_info[] = {
 	},
 };
 
-static const char *palmtx_part_probes[] = { "cmdlinepart", NULL };
-
 struct platform_nand_data palmtx_nand_platdata = {
 	.chip	= {
 		.nr_chips		= 1,
@@ -277,7 +275,6 @@ struct platform_nand_data palmtx_nand_platdata = {
 		.nr_partitions		= ARRAY_SIZE(palmtx_partition_info),
 		.partitions		= palmtx_partition_info,
 		.chip_delay		= 20,
-		.part_probe_types 	= palmtx_part_probes,
 	},
 	.ctrl	= {
 		.cmd_ctrl	= palmtx_nand_cmd_ctl,


From linux at arm.linux.org.uk  Wed Mar 28 15:28:16 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 28 Mar 2012 20:28:16 +0100
Subject: [GIT PULL 1/5] ARM: cleanups of io includes
In-Reply-To: <CAOesGMjwZOON9kFNvaEq8QhSvjAgsJT_J1Ysb9-AbePd6g+-rQ@mail.gmail.com>
References: <1332918842-13521-1-git-send-email-olof@lixom.net>
 <1332918842-13521-2-git-send-email-olof@lixom.net>
 <20120328082501.GA22414@n2100.arm.linux.org.uk>
 <CAOesGMjwZOON9kFNvaEq8QhSvjAgsJT_J1Ysb9-AbePd6g+-rQ@mail.gmail.com>
Message-ID: <20120328192816.GD22414@n2100.arm.linux.org.uk>

On Wed, Mar 28, 2012 at 02:05:50AM -0700, Olof Johansson wrote:
> On Wed, Mar 28, 2012 at 1:25 AM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > On Wed, Mar 28, 2012 at 12:13:58AM -0700, Olof Johansson wrote:
> >> Rob Herring has done a sweeping change cleaning up all of the mach/io.h includes,
> >> moving some of the oft-repeated macros to a common location and removing a bunch of
> >> boiler plate. This is another step closer to a common zImage for multiple platforms.
> >
> > NAK. ?Linus, do not pull this. ?This breaks PXA compilation, which has
> > been known about for more than a week.
> 
> The branch contains fixes for the compilation failures, they were
> pulled in right before I staged the tag for the pull request:
> 
> http://marc.info/?l=linux-arm-kernel&m=133272592723334
> 
> If you prefer to let it sit in linux-next for a day or two before
> going in, that's fine. But I verified that the original build problem
> introduced was fixed before I sent it out.

Right, having merged the latest arm-soc tree this evening into the build
tree and forced a rebuild, the errors induced by Rob's patches are now
gone, so I'm fine with this going in now.

> Unfortunately, PXA is also broken due to the regulator changes
> mentioned in the above referenced mail, which is already upstream and
> unrelated to the changes in this branch.

Yes, I noticed that appearing when I updated the build tree on the 27th.
Not impressed by that.


From torvalds at linux-foundation.org  Wed Mar 28 15:36:39 2012
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Wed, 28 Mar 2012 12:36:39 -0700
Subject: [GIT PULL 4/5] ARM: More device tree support updates
In-Reply-To: <1332918842-13521-5-git-send-email-olof@lixom.net>
References: <1332918842-13521-1-git-send-email-olof@lixom.net>
 <1332918842-13521-5-git-send-email-olof@lixom.net>
Message-ID: <CA+55aFy4QNiDTL2b37Y870kZ-09sFp9qsFn+SaKCbzWqm8xtoQ@mail.gmail.com>

On Wed, Mar 28, 2012 at 12:14 AM, Olof Johansson <olof at lixom.net> wrote:
>
> Merge conflicts and proposed solutions:
>
> arch/arm/mach-ux500/Kconfig: Two new config options. Keep both.

Guys, I'm seeing merge problems that go way beyond this.

Look at that MACH_U8500 config option. It got renamed to MACH_MOP500,
but it continues to live in the tree.

This rename conflict happened earlier and I didn't notice (grep for
it: it's used by a staging driver), so it's already in my pushed out
tree. But it seems to be getting worse, and your proposed merge
solution doesn't cover it.

I'll try to fix things up, but you need to verify my merge. And you
guys should have noticed and noted it, rather than leave it to my
random bumbling about.

                     Linus


From snjw23 at gmail.com  Wed Mar 28 15:45:14 2012
From: snjw23 at gmail.com (Sylwester Nawrocki)
Date: Wed, 28 Mar 2012 21:45:14 +0200
Subject: Handling device shared SFR on dt platform
In-Reply-To: <20120324193200.822AD3E0B06@localhost>
References: <4F6A5853.9090809@gmail.com> <20120324193200.822AD3E0B06@localhost>
Message-ID: <4F736A4A.6050302@gmail.com>

Hello Grant,

On 03/24/2012 08:32 PM, Grant Likely wrote:
>
> Generally, this is handled by having a third node for the shared
> register block and both device nodes holding a phandle to it.
> 
> No, there isn't any common infrastructure for implementing this, but
> it isn't very much code.

Thank you, that sounds good. I'm just wondering how to handle the shared
resource access synchronisation. There is an IORESOURCE_MUXED resource type 
flag which could be used to prevent drivers from stomping on each others 
feet when accessing the shared register, if I understand the software muxed
resource semantics correctly. That is, using something like 
request_muxed_(mem_)region()/release_mem_region() for the shared register
protection.

What concerns me, is an overhead from region request/ioremap(?)/release, just
to access a single 32-bit register. I'm going to see if those accesses could
be moved to only device driver's probe() and remove() callbacks and what might
be the resulting power consumption increase from that, if any.


--

Thanks,
Sylwester


From marek.vasut at gmail.com  Wed Mar 28 16:53:13 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 28 Mar 2012 22:53:13 +0200
Subject: [PATCH 2/5] arm: Use the plat_nand default partition parser
In-Reply-To: <201203281113.10684.hartleys@visionengravers.com>
References: <201203281113.10684.hartleys@visionengravers.com>
Message-ID: <201203282253.13408.marek.vasut@gmail.com>

Dear H Hartley Sweeten,

> Use the default partition parser, cmdlinepart, provided by the plat_nand
> driver.
> 
> Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <rmallon at gmail.com>
> Cc: Imre Kaloz <kaloz at openwrt.org>
> Cc: Krzysztof Halasa <khc at pm.waw.pl>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Alexander Clouter <alex at digriz.org.uk>
> Cc: Nicolas Pitre <nico at fluxnic.net>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Marek Vasut <marek.vasut at gmail.com>

Acked-by: Marek Vasut <marek.vasut at gmail.com>

> 
> ---
> 
> diff --git a/arch/arm/mach-ep93xx/snappercl15.c
> b/arch/arm/mach-ep93xx/snappercl15.c index 0c00852..5df9092 100644
> --- a/arch/arm/mach-ep93xx/snappercl15.c
> +++ b/arch/arm/mach-ep93xx/snappercl15.c
> @@ -82,8 +82,6 @@ static int snappercl15_nand_dev_ready(struct mtd_info
> *mtd) return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY);
> }
> 
> -static const char *snappercl15_nand_part_probes[] = {"cmdlinepart", NULL};
> -
>  static struct mtd_partition snappercl15_nand_parts[] = {
>  	{
>  		.name		= "Kernel",
> @@ -100,7 +98,6 @@ static struct mtd_partition snappercl15_nand_parts[] = {
>  static struct platform_nand_data snappercl15_nand_data = {
>  	.chip = {
>  		.nr_chips		= 1,
> -		.part_probe_types	= snappercl15_nand_part_probes,
>  		.partitions		= snappercl15_nand_parts,
>  		.nr_partitions		= ARRAY_SIZE(snappercl15_nand_parts),
>  		.options		= NAND_NO_AUTOINCR,
> diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
> index 5ea7909..14d7121 100644
> --- a/arch/arm/mach-ep93xx/ts72xx.c
> +++ b/arch/arm/mach-ep93xx/ts72xx.c
> @@ -105,8 +105,6 @@ static int ts72xx_nand_device_ready(struct mtd_info
> *mtd) return !!(__raw_readb(addr) & 0x20);
>  }
> 
> -static const char *ts72xx_nand_part_probes[] = { "cmdlinepart", NULL };
> -
>  #define TS72XX_BOOTROM_PART_SIZE	(SZ_16K)
>  #define TS72XX_REDBOOT_PART_SIZE	(SZ_2M + SZ_1M)
> 
> @@ -134,7 +132,6 @@ static struct platform_nand_data ts72xx_nand_data = {
>  		.nr_chips	= 1,
>  		.chip_offset	= 0,
>  		.chip_delay	= 15,
> -		.part_probe_types = ts72xx_nand_part_probes,
>  		.partitions	= ts72xx_nand_parts,
>  		.nr_partitions	= ARRAY_SIZE(ts72xx_nand_parts),
>  	},
> diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c
> b/arch/arm/mach-ixp4xx/ixdp425-setup.c index 3d742ae..fccfc73 100644
> --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
> +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
> @@ -60,8 +60,6 @@ static struct platform_device ixdp425_flash = {
>  #if defined(CONFIG_MTD_NAND_PLATFORM) || \
>      defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
> 
> -const char *part_probes[] = { "cmdlinepart", NULL };
> -
>  static struct mtd_partition ixdp425_partitions[] = {
>  	{
>  		.name	= "ixp400 NAND FS 0",
> @@ -101,7 +99,6 @@ static struct platform_nand_data ixdp425_flash_nand_data
> = { .nr_chips		= 1,
>  		.chip_delay		= 30,
>  		.options		= NAND_NO_AUTOINCR,
> -		.part_probe_types 	= part_probes,
>  		.partitions	 	= ixdp425_partitions,
>  		.nr_partitions	 	= ARRAY_SIZE(ixdp425_partitions),
>  	},
> diff --git a/arch/arm/mach-omap1/board-fsample.c
> b/arch/arm/mach-omap1/board-fsample.c index 80bd43c..62a1e11 100644
> --- a/arch/arm/mach-omap1/board-fsample.c
> +++ b/arch/arm/mach-omap1/board-fsample.c
> @@ -206,14 +206,11 @@ static int nand_dev_ready(struct mtd_info *mtd)
>  	return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
>  }
> 
> -static const char *part_probes[] = { "cmdlinepart", NULL };
> -
>  static struct platform_nand_data nand_data = {
>  	.chip	= {
>  		.nr_chips		= 1,
>  		.chip_offset		= 0,
>  		.options		= NAND_SAMSUNG_LP_OPTIONS,
> -		.part_probe_types	= part_probes,
>  	},
>  	.ctrl	= {
>  		.cmd_ctrl	= nand_cmd_ctl,
> diff --git a/arch/arm/mach-omap1/board-h2.c
> b/arch/arm/mach-omap1/board-h2.c index c306862..a914a7d 100644
> --- a/arch/arm/mach-omap1/board-h2.c
> +++ b/arch/arm/mach-omap1/board-h2.c
> @@ -200,8 +200,6 @@ static int h2_nand_dev_ready(struct mtd_info *mtd)
>  	return gpio_get_value(H2_NAND_RB_GPIO_PIN);
>  }
> 
> -static const char *h2_part_probes[] = { "cmdlinepart", NULL };
> -
>  static struct platform_nand_data h2_nand_platdata = {
>  	.chip	= {
>  		.nr_chips		= 1,
> @@ -209,7 +207,6 @@ static struct platform_nand_data h2_nand_platdata = {
>  		.nr_partitions		= ARRAY_SIZE(h2_nand_partitions),
>  		.partitions		= h2_nand_partitions,
>  		.options		= NAND_SAMSUNG_LP_OPTIONS,
> -		.part_probe_types	= h2_part_probes,
>  	},
>  	.ctrl	= {
>  		.cmd_ctrl	= h2_nand_cmd_ctl,
> diff --git a/arch/arm/mach-omap1/board-h3.c
> b/arch/arm/mach-omap1/board-h3.c index 64b8584..49952b9 100644
> --- a/arch/arm/mach-omap1/board-h3.c
> +++ b/arch/arm/mach-omap1/board-h3.c
> @@ -202,8 +202,6 @@ static int nand_dev_ready(struct mtd_info *mtd)
>  	return gpio_get_value(H3_NAND_RB_GPIO_PIN);
>  }
> 
> -static const char *part_probes[] = { "cmdlinepart", NULL };
> -
>  static struct platform_nand_data nand_platdata = {
>  	.chip	= {
>  		.nr_chips		= 1,
> @@ -211,7 +209,6 @@ static struct platform_nand_data nand_platdata = {
>  		.nr_partitions		= ARRAY_SIZE(nand_partitions),
>  		.partitions		= nand_partitions,
>  		.options		= NAND_SAMSUNG_LP_OPTIONS,
> -		.part_probe_types	= part_probes,
>  	},
>  	.ctrl	= {
>  		.cmd_ctrl	= nand_cmd_ctl,
> diff --git a/arch/arm/mach-omap1/board-perseus2.c
> b/arch/arm/mach-omap1/board-perseus2.c index 76d4ee0..eb8b2c7 100644
> --- a/arch/arm/mach-omap1/board-perseus2.c
> +++ b/arch/arm/mach-omap1/board-perseus2.c
> @@ -164,14 +164,11 @@ static int nand_dev_ready(struct mtd_info *mtd)
>  	return gpio_get_value(P2_NAND_RB_GPIO_PIN);
>  }
> 
> -static const char *part_probes[] = { "cmdlinepart", NULL };
> -
>  static struct platform_nand_data nand_data = {
>  	.chip	= {
>  		.nr_chips		= 1,
>  		.chip_offset		= 0,
>  		.options		= NAND_SAMSUNG_LP_OPTIONS,
> -		.part_probe_types	= part_probes,
>  	},
>  	.ctrl	= {
>  		.cmd_ctrl	= nand_cmd_ctl,
> diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c
> b/arch/arm/mach-orion5x/ts78xx-setup.c index c96f374..53e595e 100644
> --- a/arch/arm/mach-orion5x/ts78xx-setup.c
> +++ b/arch/arm/mach-orion5x/ts78xx-setup.c
> @@ -245,8 +245,6 @@ static void ts78xx_ts_nand_read_buf(struct mtd_info
> *mtd, readsb(io_base, buf, len);
>  }
> 
> -const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
> -
>  static struct mtd_partition ts78xx_ts_nand_parts[] = {
>  	{
>  		.name		= "mbr",
> @@ -271,7 +269,6 @@ static struct mtd_partition ts78xx_ts_nand_parts[] = {
>  static struct platform_nand_data ts78xx_ts_nand_data = {
>  	.chip	= {
>  		.nr_chips		= 1,
> -		.part_probe_types	= ts_nand_part_probes,
>  		.partitions		= ts78xx_ts_nand_parts,
>  		.nr_partitions		= ARRAY_SIZE(ts78xx_ts_nand_parts),
>  		.chip_delay		= 15,
> diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
> index c35456f..7ece2625 100644
> --- a/arch/arm/mach-pxa/balloon3.c
> +++ b/arch/arm/mach-pxa/balloon3.c
> @@ -679,8 +679,6 @@ static struct mtd_partition balloon3_partition_info[] =
> { },
>  };
> 
> -static const char *balloon3_part_probes[] = { "cmdlinepart", NULL };
> -
>  struct platform_nand_data balloon3_nand_pdata = {
>  	.chip = {
>  		.nr_chips	= 4,
> @@ -688,7 +686,6 @@ struct platform_nand_data balloon3_nand_pdata = {
>  		.nr_partitions	= ARRAY_SIZE(balloon3_partition_info),
>  		.partitions	= balloon3_partition_info,
>  		.chip_delay	= 50,
> -		.part_probe_types = balloon3_part_probes,
>  	},
>  	.ctrl = {
>  		.hwcontrol	= 0,
> diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
> index c1b65da..34b1cd8 100644
> --- a/arch/arm/mach-pxa/em-x270.c
> +++ b/arch/arm/mach-pxa/em-x270.c
> @@ -338,8 +338,6 @@ static struct mtd_partition em_x270_partition_info[] =
> { },
>  };
> 
> -static const char *em_x270_part_probes[] = { "cmdlinepart", NULL };
> -
>  struct platform_nand_data em_x270_nand_platdata = {
>  	.chip = {
>  		.nr_chips = 1,
> @@ -347,7 +345,6 @@ struct platform_nand_data em_x270_nand_platdata = {
>  		.nr_partitions = ARRAY_SIZE(em_x270_partition_info),
>  		.partitions = em_x270_partition_info,
>  		.chip_delay = 20,
> -		.part_probe_types = em_x270_part_probes,
>  	},
>  	.ctrl = {
>  		.hwcontrol = 0,
> diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
> index 9507605..0da35dc 100644
> --- a/arch/arm/mach-pxa/palmtx.c
> +++ b/arch/arm/mach-pxa/palmtx.c
> @@ -268,8 +268,6 @@ static struct mtd_partition palmtx_partition_info[] = {
>  	},
>  };
> 
> -static const char *palmtx_part_probes[] = { "cmdlinepart", NULL };
> -
>  struct platform_nand_data palmtx_nand_platdata = {
>  	.chip	= {
>  		.nr_chips		= 1,
> @@ -277,7 +275,6 @@ struct platform_nand_data palmtx_nand_platdata = {
>  		.nr_partitions		= ARRAY_SIZE(palmtx_partition_info),
>  		.partitions		= palmtx_partition_info,
>  		.chip_delay		= 20,
> -		.part_probe_types 	= palmtx_part_probes,
>  	},
>  	.ctrl	= {
>  		.cmd_ctrl	= palmtx_nand_cmd_ctl,


From arnd at arndb.de  Wed Mar 28 16:58:19 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Wed, 28 Mar 2012 20:58:19 +0000
Subject: [GIT PULL 4/5] ARM: More device tree support updates
In-Reply-To: <CA+55aFy4QNiDTL2b37Y870kZ-09sFp9qsFn+SaKCbzWqm8xtoQ@mail.gmail.com>
References: <1332918842-13521-1-git-send-email-olof@lixom.net>
 <1332918842-13521-5-git-send-email-olof@lixom.net>
 <CA+55aFy4QNiDTL2b37Y870kZ-09sFp9qsFn+SaKCbzWqm8xtoQ@mail.gmail.com>
Message-ID: <201203282058.20226.arnd@arndb.de>

On Wednesday 28 March 2012, Linus Torvalds wrote:
> On Wed, Mar 28, 2012 at 12:14 AM, Olof Johansson <olof at lixom.net> wrote:
> >
> > Merge conflicts and proposed solutions:
> >
> > arch/arm/mach-ux500/Kconfig: Two new config options. Keep both.
> 
> Guys, I'm seeing merge problems that go way beyond this.
> 
> Look at that MACH_U8500 config option. It got renamed to MACH_MOP500,
> but it continues to live in the tree.
> 
> This rename conflict happened earlier and I didn't notice (grep for
> it: it's used by a staging driver), so it's already in my pushed out
> tree. But it seems to be getting worse, and your proposed merge
> solution doesn't cover it.

Your solution looks good. I had the MACH_UX500_DT option above U5500
instead of below it in our for-next branch, but either way makes sense.

> I'll try to fix things up, but you need to verify my merge. And you
> guys should have noticed and noted it, rather than leave it to my
> random bumbling about.

Yes, noted for next time. We had a lot of merge conflicts because of
being relatively late in the merge window (this one was purely
self made though), and it's not always easy to decide which ones
to eliminate in advance, leave in or describe the resolution we found.

Since we usually see the same conflicts and resolve them in the
for-next branch, I guess it's easy enough to just always provide
the branch with the resolutions as a help for cases like this one.

	Arnd


From alex at digriz.org.uk  Wed Mar 28 17:13:28 2012
From: alex at digriz.org.uk (Alexander Clouter)
Date: Wed, 28 Mar 2012 22:13:28 +0100
Subject: [PATCH 2/5] arm: Use the plat_nand default partition parser
In-Reply-To: <201203281113.10684.hartleys@visionengravers.com>
References: <201203281113.10684.hartleys@visionengravers.com>
Message-ID: <20120328211327.GC6586@marmot>

* H Hartley Sweeten <hartleys at visionengravers.com> [2012-03-28 11:13:09-0700]:
>
> Use the default partition parser, cmdlinepart, provided by the plat_nand driver.
> 
> Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <rmallon at gmail.com>
> Cc: Imre Kaloz <kaloz at openwrt.org>
> Cc: Krzysztof Halasa <khc at pm.waw.pl>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Alexander Clouter <alex at digriz.org.uk>
> Cc: Nicolas Pitre <nico at fluxnic.net>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Marek Vasut <marek.vasut at gmail.com>
> 
Acked-by: Alexander Clouter <alex at digriz.org.uk>

Thanks

-- 
Alexander Clouter
.sigmonster says: The only rose without thorns is friendship.


From mturquette at ti.com  Wed Mar 28 17:20:30 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 28 Mar 2012 14:20:30 -0700
Subject: [PATCH 04/10] clk: declare clk_ops of basic clks in clk-provider.h
In-Reply-To: <1332833009-4121-5-git-send-email-shawn.guo@linaro.org>
References: <1332833009-4121-1-git-send-email-shawn.guo@linaro.org>
 <1332833009-4121-5-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAJOA=zOCyCVG-uk_BoO1fj0Tt6p2WbWgtktP5arjGqjk9RyhXg@mail.gmail.com>

On Tue, Mar 27, 2012 at 12:23 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> Besides the static initialization, the clk_ops of basic clks could
> also be used by particular clk type being subclass of the basic clks.
>
> For example, clk_busy_divider has the same clk_ops as clk_divider,
> except it has to wait for a busy bit before return success with
> .set_rate. ?clk_busy_divider will somehow reuse clk_ops of clk_divider.
>
> Since clk-provider.h is included by clk-private.h, it's safe to move
> those clk_ops declaration of basic clks form ?clk-private.h into
> clk-provider.h, so that implementation of clks like clk_busy_divider
> above do not need to include clk-private.h to access those clk_ops.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Hi Shawn,

Thanks for the patch.  After Andrew's response on using clk_ops over
the EXPORT'd functions I'll take this in my fixes branch.

Mike

> ---
> ?include/linux/clk-private.h ?| ? ?8 --------
> ?include/linux/clk-provider.h | ? ?4 ++++
> ?2 files changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
> index 5f4ccd7..f19fee0 100644
> --- a/include/linux/clk-private.h
> +++ b/include/linux/clk-private.h
> @@ -55,8 +55,6 @@ struct clk {
> ?* alternative macro for static initialization
> ?*/
>
> -extern const struct clk_ops clk_fixed_rate_ops;
> -
> ?#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_fixed_rate_flags) ? ? ? ? ? ? ?\
> ? ? ? ?static struct clk _name; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> @@ -78,8 +76,6 @@ extern const struct clk_ops clk_fixed_rate_ops;
> ? ? ? ? ? ? ? ?.flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?};
>
> -extern const struct clk_ops clk_gate_ops;
> -
> ?#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_flags, _reg, _bit_idx, ? ? ? ? \
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_gate_flags, _lock) ? ? ? ? ? ? \
> @@ -110,8 +106,6 @@ extern const struct clk_ops clk_gate_ops;
> ? ? ? ? ? ? ? ?.flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?};
>
> -extern const struct clk_ops clk_divider_ops;
> -
> ?#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, ? \
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_flags, _reg, _shift, _width, ? \
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_divider_flags, _lock) ? ? ? ? ?\
> @@ -143,8 +137,6 @@ extern const struct clk_ops clk_divider_ops;
> ? ? ? ? ? ? ? ?.flags = _flags, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?};
>
> -extern const struct clk_ops clk_mux_ops;
> -
> ?#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_reg, _shift, _width, ? ? ? ? ? \
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?_mux_flags, _lock) ? ? ? ? ? ? ?\
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 5508897..6eb8e5d 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -149,6 +149,7 @@ struct clk_fixed_rate {
> ? ? ? ?u8 ? ? ? ? ? ? ?flags;
> ?};
>
> +extern const struct clk_ops clk_fixed_rate_ops;
> ?struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
> ? ? ? ? ? ? ? ?const char *parent_name, unsigned long flags,
> ? ? ? ? ? ? ? ?unsigned long fixed_rate);
> @@ -180,6 +181,7 @@ struct clk_gate {
>
> ?#define CLK_GATE_SET_TO_DISABLE ? ? ? ? ? ? ? ?BIT(0)
>
> +extern const struct clk_ops clk_gate_ops;
> ?struct clk *clk_register_gate(struct device *dev, const char *name,
> ? ? ? ? ? ? ? ?const char *parent_name, unsigned long flags,
> ? ? ? ? ? ? ? ?void __iomem *reg, u8 bit_idx,
> @@ -218,6 +220,7 @@ struct clk_divider {
> ?#define CLK_DIVIDER_ONE_BASED ? ? ? ? ?BIT(0)
> ?#define CLK_DIVIDER_POWER_OF_TWO ? ? ? BIT(1)
>
> +extern const struct clk_ops clk_divider_ops;
> ?struct clk *clk_register_divider(struct device *dev, const char *name,
> ? ? ? ? ? ? ? ?const char *parent_name, unsigned long flags,
> ? ? ? ? ? ? ? ?void __iomem *reg, u8 shift, u8 width,
> @@ -252,6 +255,7 @@ struct clk_mux {
> ?#define CLK_MUX_INDEX_ONE ? ? ? ? ? ? ?BIT(0)
> ?#define CLK_MUX_INDEX_BIT ? ? ? ? ? ? ?BIT(1)
>
> +extern const struct clk_ops clk_mux_ops;
> ?struct clk *clk_register_mux(struct device *dev, const char *name,
> ? ? ? ? ? ? ? ?char **parent_names, u8 num_parents, unsigned long flags,
> ? ? ? ? ? ? ? ?void __iomem *reg, u8 shift, u8 width,
> --
> 1.7.5.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From marc at cpdesign.com.au  Wed Mar 28 16:47:50 2012
From: marc at cpdesign.com.au (Marc Reilly)
Date: Thu, 29 Mar 2012 07:47:50 +1100
Subject: [PATCH] mfd: mc13xxx: add I2C support fix building for v3.4
In-Reply-To: <1332943273-22447-1-git-send-email-alexg@meprolight.com>
References: <1332943273-22447-1-git-send-email-alexg@meprolight.com>
Message-ID: <201203290747.50881.marc@cpdesign.com.au>

Hi,

As Mark Brown already said, these changes should be squashed into a new 
version of the patches.

On Thursday, March 29, 2012 01:01:13 AM Alex Gershgorin wrote:
> This patch fixes the compilation errors after the patches
> from series mc13xxx-add-I2C-support-V4 were applied.
> 
> Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
> ---
>  drivers/mfd/Kconfig        |    2 ++
>  drivers/mfd/mc13xxx-core.c |    2 +-
>  2 files changed, 3 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index c3fbc5e..2119732 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -577,6 +577,8 @@ config MFD_MC13XXX
>  	depends on SPI_MASTER || I2C
>  	select MFD_CORE
>  	select MFD_MC13783
> +	select REGMAP_I2C if I2C
This can go under the "config MFD_MC13XXX_I2C" entry in patch 4/4 (the "if 
I2C" won't be needed)

> +	select REGMAP_SPI if SPI_MASTER
This can go under the "config MFD_MC13XXX_SPI" entry in patch 3/4


>  	help
>  	  Enable support for the Freescale MC13783 and MC13892 PMICs.
>  	  This driver provides common support for accessing the device,
> diff --git a/drivers/mfd/mc13xxx-core.c b/drivers/mfd/mc13xxx-core.c
> index 31dbf91..5a60273 100644
> --- a/drivers/mfd/mc13xxx-core.c
> +++ b/drivers/mfd/mc13xxx-core.c
> @@ -616,7 +616,7 @@ static int mc13xxx_add_subdevice(struct mc13xxx
> *mc13xxx, const char *format) #ifdef CONFIG_OF
>  static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
>  {
> -	struct device_node *np = mc13xxx->dev.of_node;
> +	struct device_node *np = mc13xxx->dev->of_node;

Good catch! This can be fixed up in 4/4

@Alex, you seen keen to do this, so I'll leave it to you :)
Otherwise, I'm happy to do it, just let me know.

Cheers,
Marc



From skannan at codeaurora.org  Wed Mar 28 18:25:46 2012
From: skannan at codeaurora.org (Saravana Kannan)
Date: Wed, 28 Mar 2012 15:25:46 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <CAJOA=zM0_czNzdqXfJDn8vzfpVLywBvYTg3SxKs6BHUOsRNd9w@mail.gmail.com>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
 <4F6946AA.4070201@codeaurora.org> <4F6CEC0C.4060704@codeaurora.org>
 <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>
 <4F6CF555.4080109@codeaurora.org>
 <CAJOA=zOnR1NwZ1Cmkfb+b7f7=N_vg+txAUqKXF2Nf2nVYFMjjg@mail.gmail.com>
 <4F6D0167.3040704@codeaurora.org>
 <CAJOA=zM47mB8tY2hV1QDVm1GZRqQrjrktkbLQ-Vp7hBjA8H5xg@mail.gmail.com>
 <4F728050.9030904@codeaurora.org>
 <CAJOA=zM0_czNzdqXfJDn8vzfpVLywBvYTg3SxKs6BHUOsRNd9w@mail.gmail.com>
Message-ID: <4F738FEA.9020109@codeaurora.org>

On 03/28/2012 10:08 AM, Turquette, Mike wrote:
> On Tue, Mar 27, 2012 at 8:06 PM, Saravana Kannan<skannan at codeaurora.org>  wrote:

snip

>> I think there is still a problem with not being able to differentiate
>> between pre-change recalc and post-change recalc. This applies for any set
>> parent and set rate on a clock that has children.
>>
>> Consider this simple example:
>> * Divider clock B is fed from clock A.
>> * Clock B can never output>  120 MHz due to downstream
>>   HW/clock limitations.
>> * Clock A is running at 200 MHz
>> * Clock B divider is set to 2.
>>
>> Now, say the rate of clock A is changing from 200 MHz to 300 MHz (due to set
>> rate or set parent). In this case, the clock B divider should be set to 3
>> pre-rate change to guarantee that the output of clock B is never>  120 MHz.
>> So the rate of clock B will go from 100 MHz (200/2) to 66 MHz (200/3) to 100
>> MHz (300/3) and everything is good.
>>
>> Assume we somehow managed to do the above. So, now clock A is at 300 MHz,
>> clock B divider is at 3 and the clock B output is 100 MHz.
>>
>> Now, say the rate of clock A changes from 300 MHz to 100 MHz. In this case
>> the clock B divider should only be changed post rate change. If we do it pre
>> rate change, then the output will go from 100 MHz (300/3) to 150 MHz (300/1)
>> to 100 MHz (100/1). We went past the 120 MHz limit of clock B's output rate.
>>
>> If we do this post rate change, we can do this without exceeding the max
>> output limit of clock B. It will go from 100 MHz (300/3) to 33 MHz (100/3)
>> to 100 MHz (100/1). We never went past the 120 MHz limit.
>>
>> So, at least for this reason above, I think we need to pass a pre/post
>> parameter to the recalc ops.

Sorry if I wasn't clear. But the case above is a separate issue from 
what I mention below. What are your thoughts on handling this? Pass 
"msg" to recalc_rates?

>> While we are at it, we should probably just add a failure option for recalc
>> to make it easy to reject unacceptable rate changes. To keep the clock
>> framework code simpler, you could decide to allow errors only for the
>> pre-change recalc calls. That way, the error case roll back code won't be
>> crazy.
>
> recalc is too late to catch this.  I think you mean round_rate.  We
> want to determine which rate changes are out-of-spec during
> clk_calc_new_rates (for clk_set_rate) which involves round_rate being
> a bit smarter about what it can and cannot do.

The case I'm referring to is set_parent(). set_rate() and set_parent() 
have a lot of common implications and it doesn't look like the clock 
framework is handling the common cases the same way for both 
set_parent() and set_rate().

It almost feels like set_parent() and set_rate() should just be wrappers 
around some common function that handles most of the work. After all, 
set_parent() is just a slimmed down version of set_rate(). Set rate is 
just a combination of set parent and set divider.

>
> Anyways I'm looking at ways to do this in my clk-dependencies branch.
>

Are you also looking into the pre/post rate change divider handling case 
I mentioned above?

Thanks,
Saravana

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From stigge at antcom.de  Wed Mar 28 18:36:26 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 29 Mar 2012 00:36:26 +0200
Subject: [PATCH] net: lpc_eth: Fix rename of dev_hw_addr_random
Message-ID: <1332974186-12962-1-git-send-email-stigge@antcom.de>

In parallel to the integration of lpc_eth.c, dev_hw_addr_random() has been
renamed to eth_hw_addr_random(). This patch fixes it also in the new driver
lpc_eth.c.

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 drivers/net/ethernet/nxp/lpc_eth.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- linux-2.6.orig/drivers/net/ethernet/nxp/lpc_eth.c
+++ linux-2.6/drivers/net/ethernet/nxp/lpc_eth.c
@@ -1441,7 +1441,7 @@ static int lpc_eth_drv_probe(struct plat
 	}
 #endif
 	if (!is_valid_ether_addr(ndev->dev_addr))
-		dev_hw_addr_random(ndev, ndev->dev_addr);
+		eth_hw_addr_random(ndev);
 
 	/* Reset the ethernet controller */
 	__lpc_eth_reset(pldat);


From stigge at antcom.de  Wed Mar 28 18:49:56 2012
From: stigge at antcom.de (Roland Stigge)
Date: Thu, 29 Mar 2012 00:49:56 +0200
Subject: [PATCH] ARM: LPC32xx: clock.c: Fix lpc-eth clock reference
Message-ID: <1332974996-13045-1-git-send-email-stigge@antcom.de>

During a complex merge for v3.4, one line of the commit
c20b909be9ba27173294a52d08cab293ec030a2c ("ARM: LPC32xx: Ethernet support") was
reverted wrongly ("lpc-eth.0" -> "lpc-net.0") while the other conflicts were
merged correctly. This patch re-applies the clock name "lpc-eth.0".

Signed-off-by: Roland Stigge <stigge at antcom.de>

---
 Applies on top of Olof's 1f5b7dcfdad3840d4bce27ab0b3cc8f376b81544 in
 preparation of v3.4-rc1

 arch/arm/mach-lpc32xx/clock.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- linux-2.6.orig/arch/arm/mach-lpc32xx/clock.c
+++ linux-2.6/arch/arm/mach-lpc32xx/clock.c
@@ -1134,7 +1134,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
 	_REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
 	_REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
-	_REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
+	_REGISTER_CLOCK("lpc-eth.0", NULL, clk_net)
 	_REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
 	_REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
 	_REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)


From mturquette at ti.com  Wed Mar 28 19:49:13 2012
From: mturquette at ti.com (Turquette, Mike)
Date: Wed, 28 Mar 2012 16:49:13 -0700
Subject: [PATCH v7 2/3] clk: introduce the common clock framework
In-Reply-To: <4F738FEA.9020109@codeaurora.org>
References: <1331878280-2758-1-git-send-email-mturquette@linaro.org>
 <1331878280-2758-3-git-send-email-mturquette@linaro.org>
 <20120320140220.GE32469@S2101-09.ap.freescale.net>
 <efca11f1b68186dbf1771c09fe3a2f0a.squirrel@www.codeaurora.org>
 <CAJOA=zNmgSQfYAUZ-vqqTk0w3s3eKz3tjVOpyDgO35Q_Ogkz0g@mail.gmail.com>
 <4F6946AA.4070201@codeaurora.org> <4F6CEC0C.4060704@codeaurora.org>
 <CAJOA=zNDKesFtuRgv+6brmBvmbQQecKEOJ89EiG-+YzXVTosWw@mail.gmail.com>
 <4F6CF555.4080109@codeaurora.org>
 <CAJOA=zOnR1NwZ1Cmkfb+b7f7=N_vg+txAUqKXF2Nf2nVYFMjjg@mail.gmail.com>
 <4F6D0167.3040704@codeaurora.org>
 <CAJOA=zM47mB8tY2hV1QDVm1GZRqQrjrktkbLQ-Vp7hBjA8H5xg@mail.gmail.com>
 <4F728050.9030904@codeaurora.org>
 <CAJOA=zM0_czNzdqXfJDn8vzfpVLywBvYTg3SxKs6BHUOsRNd9w@mail.gmail.com>
 <4F738FEA.9020109@codeaurora.org>
Message-ID: <CAJOA=zNd=JTByP+yfXJpZrAb1cswo+XD0F4vzrhOsOoROPT8sQ@mail.gmail.com>

On Wed, Mar 28, 2012 at 3:25 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
> On 03/28/2012 10:08 AM, Turquette, Mike wrote:
>> On Tue, Mar 27, 2012 at 8:06 PM, Saravana Kannan<skannan at codeaurora.org>
>> ?wrote:
>>> I think there is still a problem with not being able to differentiate
>>> between pre-change recalc and post-change recalc. This applies for any
>>> set
>>> parent and set rate on a clock that has children.
>>>
>>> Consider this simple example:
>>> * Divider clock B is fed from clock A.
>>> * Clock B can never output> ?120 MHz due to downstream
>>> ?HW/clock limitations.
>>> * Clock A is running at 200 MHz
>>> * Clock B divider is set to 2.
>>>
>>> Now, say the rate of clock A is changing from 200 MHz to 300 MHz (due to
>>> set
>>> rate or set parent). In this case, the clock B divider should be set to 3
>>> pre-rate change to guarantee that the output of clock B is never> ?120
>>> MHz.
>>> So the rate of clock B will go from 100 MHz (200/2) to 66 MHz (200/3) to
>>> 100
>>> MHz (300/3) and everything is good.
>>>
>>> Assume we somehow managed to do the above. So, now clock A is at 300 MHz,
>>> clock B divider is at 3 and the clock B output is 100 MHz.
>>>
>>> Now, say the rate of clock A changes from 300 MHz to 100 MHz. In this
>>> case
>>> the clock B divider should only be changed post rate change. If we do it
>>> pre
>>> rate change, then the output will go from 100 MHz (300/3) to 150 MHz
>>> (300/1)
>>> to 100 MHz (100/1). We went past the 120 MHz limit of clock B's output
>>> rate.
>>>
>>> If we do this post rate change, we can do this without exceeding the max
>>> output limit of clock B. It will go from 100 MHz (300/3) to 33 MHz
>>> (100/3)
>>> to 100 MHz (100/1). We never went past the 120 MHz limit.
>>>
>>> So, at least for this reason above, I think we need to pass a pre/post
>>> parameter to the recalc ops.
>
> Sorry if I wasn't clear. But the case above is a separate issue from what I
> mention below. What are your thoughts on handling this? Pass "msg" to
> recalc_rates?

I'm OK passing the msg to in .recalc_rates for your hardware which
samples frequency.

>>> While we are at it, we should probably just add a failure option for
>>> recalc
>>> to make it easy to reject unacceptable rate changes. To keep the clock
>>> framework code simpler, you could decide to allow errors only for the
>>> pre-change recalc calls. That way, the error case roll back code won't be
>>> crazy.

We do need a rate validation mechanism, which neither .round_rate or
.recalc_rates provide.  But I don't want to bolt one on right now because
the proper solution to that problem is not a quick fix.  Coupled to
this issue are lingering topics that we've discussed tentatively in
the past:

1) rate ranges (min/max)

2) clock dependencies; these should enforce functional dependencies
between clocks

3) intended rates; this strays into the scary arena of policy, which
has traditionally fallen outside the purview of the clock framework.
But if we want a better clock framework we probably need a way for
downstream clocks to make intelligent decisions about their rates when
parent rates change.  We could overload .round_rate to do this for
clk_set_rate, but that doesn't help out clk_set_parent.  And I'm
against overloading the functionality of these callbacks any more than
I already have.

I'm not sure that just overloading .recalc_rates is the best approach.
 I like that .recalc_rates only recalculates the rate!  For clocks
that need to make an intelligent decision about their rates when
parent rates change we might need to introduce a new callback and/or
refactor the clk_set_rate and clk_set_parent paths to use some common
code.

>> recalc is too late to catch this. ?I think you mean round_rate. ?We
>> want to determine which rate changes are out-of-spec during
>> clk_calc_new_rates (for clk_set_rate) which involves round_rate being
>> a bit smarter about what it can and cannot do.
>
>
> The case I'm referring to is set_parent(). set_rate() and set_parent() have
> a lot of common implications and it doesn't look like the clock framework is
> handling the common cases the same way for both set_parent() and set_rate().

Agreed that there needs to be some unification here.  Certainly a
common rate validation mechanism is missing and the downstream
notification diverged in the last set of patches.

> It almost feels like set_parent() and set_rate() should just be wrappers
> around some common function that handles most of the work. After all,
> set_parent() is just a slimmed down version of set_rate(). Set rate is just
> a combination of set parent and set divider.

I mostly agree.  A big caveat is that clk_set_parent will never
propagate a request up the tree, but that doesn't mean the
implementation details of the two functions are mutually exclusive.

>> Anyways I'm looking at ways to do this in my clk-dependencies branch.
>>
>
> Are you also looking into the pre/post rate change divider handling case I
> mentioned above?

I'll admit that my initial focus on clk-deps was more along the lines of:

"Clock A wants to go faster, and has a functional dependency to scale
Clock B to a faster rate first"

That sort of situation is often necessary to keep certain timing
requirements valid.  But your example reinforces that clocks need to
have some clue about rate ranges, and it resets my opinion on writing
a clk-dep mechanism which is just focused on raising rates.  The real
solution should be generic and able to handle lowering and NACKing
rates also.

In short: for now I'll just pass the msg into .recalc_rates.  The
other stuff is a design activity which is out-of-scope for the
upcoming -rc bugfix windows.

Regards,
Mike


From kgene.kim at samsung.com  Wed Mar 28 20:14:34 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 29 Mar 2012 09:14:34 +0900
Subject: [PATCH] ARM: S3C24XX: fix missing common.h in mach-s3c24xx/
Message-ID: <1332980074-4614-1-git-send-email-kgene.kim@samsung.com>

This patch fixes missing mach-s3c24xx/common.h which has been
lost when regarding s3c24xx directories merged.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s3c24xx/common.h |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s3c24xx/common.h

diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
new file mode 100644
index 0000000..a7cd62f
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Common Header for S3C24XX SoCs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
+#define __ARCH_ARM_MACH_S3C24XX_COMMON_H
+
+#ifdef CONFIG_CPU_S3C2410
+void s3c2410_restart(char mode, const char *cmd);
+#endif
+
+#ifdef CONFIG_CPU_S3C244X
+void s3c244x_restart(char mode, const char *cmd);
+#endif
+
+#endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */
-- 
1.7.2.3



From kgene.kim at samsung.com  Wed Mar 28 20:59:13 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 28 Mar 2012 17:59:13 -0700
Subject: [CPUFREQ] Fix exposure of ARM_EXYNOS4210_CPUFREQ
In-Reply-To: <20120327074931.GK5611@n2100.arm.linux.org.uk>
References: <20120213094940.GA15338@n2100.arm.linux.org.uk>
 <4F3CF3DA.7000806@samsung.com>
 <20120216160250.GP13673@n2100.arm.linux.org.uk>
 <00aa01ccf084$93c98a70$bb5c9f50$%kim@samsung.com>
 <20120327074931.GK5611@n2100.arm.linux.org.uk>
Message-ID: <4F73B3E1.4080807@samsung.com>

Russell King wrote:
> On Tue, Feb 21, 2012 at 07:35:49PM +0900, Kukjin Kim wrote:
>> Russell King - ARM Linux wrote:
>>>
>>> On Thu, Feb 16, 2012 at 09:17:30PM +0900, Kukjin Kim wrote:
>>>> On 02/13/12 18:49, Russell King - ARM Linux wrote:
>>>>> From: Russell King<rmk+kernel at arm.linux.org.uk>
>>>>>
>>>>> exynos4210-cpufreq.c is not buildable on non-exynos builds, so it's
>>>>> pointless allowing this option to be exposed.  Fix this by adding a
>>>>> dependency on ARCH_EXYNOS.
>>>>>
>>>>> drivers/cpufreq/exynos4210-cpufreq.c:20:29: error: mach/regs-clock.h:
>>> No such file or directory
>>>>> drivers/cpufreq/exynos4210-cpufreq.c:21:26: error: mach/cpufreq.h: No
>>> such file or directory
>>>>>
>>>>> Signed-off-by: Russell King<rmk+kernel at arm.linux.org.uk>
>>>>> Cc: Dave Jones<davej at redhat.com>
>>>>> Cc: cpufreq at vger.kernel.org
>>>>> Cc: Kukjin Kim<kgene.kim at samsung.com>
>>>>> ---
>>>>>    drivers/cpufreq/Kconfig.arm |    1 +
>>>>>    1 files changed, 1 insertions(+), 0 deletions(-)
>>>>>
>>>>> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
>>>>> index e0664fe..c8bde43 100644
>>>>> --- a/drivers/cpufreq/Kconfig.arm
>>>>> +++ b/drivers/cpufreq/Kconfig.arm
>>>>> @@ -34,6 +34,7 @@ config ARM_EXYNOS_CPUFREQ
>>>>>
>>>>>    config ARM_EXYNOS4210_CPUFREQ
>>>>>    	bool "Samsung EXYNOS4210"
>>>>> +	depends on ARCH_EXYNOS
>>>>>    	help
>>>>>    	  This adds the CPUFreq driver for Samsung EXYNOS4210
>>>>>    	  SoC (S5PV310 or S5PC210).
>>>>>
>>>>
>>>> Yes, you're right. Should be added it.
>>>> BTW, how about following?
>>>>
>>>> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
>>>> index e0664fe..a5e0487 100644
>>>> --- a/drivers/cpufreq/Kconfig.arm
>>>> +++ b/drivers/cpufreq/Kconfig.arm
>>>> @@ -33,7 +33,7 @@ config ARM_EXYNOS_CPUFREQ
>>>>            If in doubt, say N.
>>>>
>>>>   config ARM_EXYNOS4210_CPUFREQ
>>>> -       bool "Samsung EXYNOS4210"
>>>> +       bool
>>>>          help
>>>>            This adds the CPUFreq driver for Samsung EXYNOS4210
>>>>            SoC (S5PV310 or S5PC210).
>>>>
>>>> I think, when selecting "ARM_EXYNOS_CPUFREQ", "ARM_EXYNOS4210_CPUFREQ"
>>>> will be selected on EXYNOS4210 with above changes.
>>>
>> Hi Russell,
>>
>>> I don't think so.  If you select this symbol you'll get a complaint
>>> that CPU_FREQ is not selected.
>>
>> Hmm..when I selected this symbol, I didn't get any warning about CPU_FREQ,
>> because the cpufreq/Kconfig.arm depends on CPU_FREQ. It means, when CPU_FREQ
>> is not selected, I can't select anything in cpufreq/Kconfig.arm.
>>
>>> What's probably much better is:
>>>
>> Yes, looks better than mine.
>>
>>> config ARM_EXYNOS4210_CPUFREQ
>>> 	def_bool ARCH_EXYNOS
>>
>> But, should be...
>> 	def_bool CPU_EXYNOS4210
>>
>> Because the ARM_EXYNOS4210_CPUFREQ is only for EXYNOS4210 and the
>> ARM_EXYNOS4X12_CPUFREQ will be added, actually submitted for other
>> SOC_EXYNOS4212 and SOC_EXYNOS4412.
>>
>>>
>>> because that ensures that if the CPU_FREQ dependencies change you don't
>>> have to update numerous places for that too.
>>
>> OK, I agree.
>>
>> So could you  please re-send/re-work this?
>
> As predicted, this is breaking other ARM platforms.  Please fix this
> yourself before your crappy code gets pushed into mainline.  Thanks.
>
I fixed it.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Wed Mar 28 21:23:47 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 28 Mar 2012 18:23:47 -0700
Subject: [PATCH v12 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
In-Reply-To: <20120318132746.GL26973@8bytes.org>
References: <000201cd0286$2e6fbb40$8b4f31c0$%cho@samsung.com>
 <20120315111227.GA2384@amd.com> <4F61FF1D.5000502@samsung.com>
 <4F630841.2070307@linaro.org> <4F63A6F6.9050506@samsung.com>
 <20120318132746.GL26973@8bytes.org>
Message-ID: <4F73B9A3.30605@samsung.com>

Joerg Roedel wrote:
> On Fri, Mar 16, 2012 at 01:47:50PM -0700, Kukjin Kim wrote:
>> Anyway Joerg, how do you want to handle this? Do you want to pick up
>> 1/2/3 all of them in your tree? If so, 2nd patch should be on top of
>> some samsung topic stuff.
>
> Since patch 2 only applies to the Samsung tree, it is best to carry
> this in your tree for merging. Feel free to add my Acked-by to patch 3.
> But any further patches for the Exynos IOMMU drivers should go through
> my tree after it is merged.
>

Hi Joerg,

Now that 1st and 2nd can be applied cleanly into latest mainline. But 
unfortunately, I have no chance to send them to Linus now and I'm not 
sure you can do it during this merge window. If it is possible, please 
keep going on with my ack.

KyongHo, just note, happens follwoing complaint with checkpatch, but I'm 
not sure this should be fixed right now. I think, if required, we can 
fix it later.

ERROR: Macros with complex values should be enclosed in parenthesis
#698: FILE: arch/arm/mach-exynos/dev-sysmmu.c:64:
+#define DEFINE_SYSMMU_RESOURCE(core, mem, irq)                         \
+       DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem),      \
+       DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)

ERROR: Macros with complex values should be enclosed in parenthesis
#702: FILE: arch/arm/mach-exynos/dev-sysmmu.c:68:
+#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq)                 \
+       SYSMMU_RESOURCE(core, ipname) {                                 \
+               DEFINE_SYSMMU_RESOURCE(core, mem, irq)                  \
+       }

WARNING: quoted string split across lines
#914: FILE: arch/arm/mach-exynos/dev-sysmmu.c:259:
+                               pr_err("%s: Failed to add device 
resources for "
+                                               "%s.%d\n", __func__,

total: 2 errors, 1 warnings, 1062 lines checked

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From grant.likely at secretlab.ca  Wed Mar 28 19:04:26 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Wed, 28 Mar 2012 17:04:26 -0600
Subject: [PATCH V3 2/5] mtd: Add orion_nand devicetree bindings
In-Reply-To: <1332885255-8304-3-git-send-email-jm@lentin.co.uk>
References: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
 <1332885255-8304-3-git-send-email-jm@lentin.co.uk>
Message-ID: <20120328230426.CF3A43E104C@localhost>

On Tue, 27 Mar 2012 22:54:12 +0100, Jamie Lentin <jm at lentin.co.uk> wrote:
> Allow a NAND chip using the orion_nand driver to be described using devicetree.
> 
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> ---
>  .../devicetree/bindings/mtd/orion-nand.txt         |   46 ++++++++++++++++++++
>  drivers/mtd/nand/orion_nand.c                      |   35 ++++++++++++++-
>  2 files changed, 79 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt
> 
> diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
> new file mode 100644
> index 0000000..22c7438
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/orion-nand.txt
> @@ -0,0 +1,46 @@
> +NAND support for Marvell Orion SoC platforms
> +
> +Required properties:
> +- compatible : "mrvl,orion-nand".
> +- reg : Base physical address of the NAND and length of memory mapped
> +	region
> +
> +Optional properties:
> +- cle :
> +- ale :
> +- bank-width :
> +- chip-delay :

Please state what data these properties contain.  :-)



From grant.likely at secretlab.ca  Wed Mar 28 19:08:56 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Wed, 28 Mar 2012 17:08:56 -0600
Subject: [PATCH V3 5/5] mtd: Move fdt partition documentation to a
 seperate file
In-Reply-To: <201203280817.12652.arnd@arndb.de>
References: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
 <1332885255-8304-6-git-send-email-jm@lentin.co.uk>
 <201203280817.12652.arnd@arndb.de>
Message-ID: <20120328230856.ECB9F3E1151@localhost>

On Wed, 28 Mar 2012 08:17:12 +0000, Arnd Bergmann <arnd at arndb.de> wrote:
> On Tuesday 27 March 2012, Jamie Lentin wrote:
> > 
> > Partitions are described in the same way for all mtd devices when using
> > devicetree, move the documentation to a separate file and add references
> > to it.
> > 
> > Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> 
> Acked-by: Arnd Bergmann <arnd at arndb.de>

Merged, thanks (dropping the orion-nand.txt hunk) because I'm not
applying the rest of the series!)

g.


From kgene.kim at samsung.com  Wed Mar 28 21:34:05 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 28 Mar 2012 18:34:05 -0700
Subject: [PATCH 1/4] ARM: Exynos: Use CHIP_ID to detect cpu type during
 decompression setup
In-Reply-To: <1332840365-24827-2-git-send-email-thomas.abraham@linaro.org>
References: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>
 <1332840365-24827-2-git-send-email-thomas.abraham@linaro.org>
Message-ID: <4F73BC0D.7070004@samsung.com>

Thomas Abraham wrote:
> The config option MACH_SMDK5250 is not available for Exynos5 since only
> a device tree based machine is supported and selected by MACH_EXYNOS5_DT.
> Hence, the detection of the cpu type based on machine_is_smdk5250 always
> fails and boot hangs due to incorrect uart base being used. Fix this by
> reading the chip id to determine the cpu type and setup the uart_base
> accordingly.
> 
> Signed-off-by: Thomas Abraham<thomas.ab at samsung.com>
> ---
>   arch/arm/mach-exynos/include/mach/uncompress.h |    6 +++++-
>   1 files changed, 5 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
> index 493f4f3..603ea9b 100644
> --- a/arch/arm/mach-exynos/include/mach/uncompress.h
> +++ b/arch/arm/mach-exynos/include/mach/uncompress.h
> @@ -14,15 +14,19 @@
> 
>   #include<asm/mach-types.h>
> 
> +#include<plat/cpu.h>
>   #include<mach/map.h>
> 
>   volatile u8 *uart_base;
> 
>   #include<plat/uncompress.h>
> 
> +#define __raw_readl(addr)		\
> +	(*((volatile unsigned int __force *)(addr)))
> +
>   static void arch_detect_cpu(void)
>   {
> -	if (machine_is_smdk5250())
> +	if ((__raw_readl(EXYNOS_PA_CHIPID)&  EXYNOS5_SOC_MASK) == EXYNOS5250_SOC_ID)
>   		uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
>   	else
>   		uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);

Hi Thomas,

Thanks for fix.

But I have following patch and it is not required to add inclusion of
<plat/cpu.h>. How do you think? If you're ok, I would preferred to use
follwoing.

diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h
b/arch/arm/mach-exynos/include/mach/uncompress.h
index 493f4f3..2979995 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -20,9 +20,24 @@ volatile u8 *uart_base;

 #include <plat/uncompress.h>

+static unsigned int __raw_readl(unsigned int ptr)
+{
+	return *((volatile unsigned int *)ptr);
+}
+
 static void arch_detect_cpu(void)
 {
-	if (machine_is_smdk5250())
+	u32 chip_id = __raw_readl(EXYNOS_PA_CHIPID);
+
+	/*
+	 * product_id is bits 31:12
+	 *    bits 23:20 describe the exynosX family
+	 *
+	 */
+	chip_id >>= 20;
+	chip_id &= 0xf;
+
+	if (chip_id == 0x5)
 		uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET *
CONFIG_S3C_LOWLEVEL_UART_PORT);
 	else
 		uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET *
CONFIG_S3C_LOWLEVEL_UART_PORT);


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From pullip.cho at samsung.com  Wed Mar 28 21:43:44 2012
From: pullip.cho at samsung.com (KyongHo Cho)
Date: Thu, 29 Mar 2012 10:43:44 +0900
Subject: [PATCH v12 2/3] ARM: EXYNOS: Change System MMU platform device
 definitions
In-Reply-To: <4F73B9A3.30605@samsung.com>
References: <000201cd0286$2e6fbb40$8b4f31c0$%cho@samsung.com>
 <20120315111227.GA2384@amd.com> <4F61FF1D.5000502@samsung.com>
 <4F630841.2070307@linaro.org> <4F63A6F6.9050506@samsung.com>
 <20120318132746.GL26973@8bytes.org> <4F73B9A3.30605@samsung.com>
Message-ID: <CAHQjnOMPvg5en_PzrPYx4nUAuPOgxiKm8HMHWAhJ4GhJqU8jKw@mail.gmail.com>

On Thu, Mar 29, 2012 at 10:23 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Joerg Roedel wrote:
>>
>> On Fri, Mar 16, 2012 at 01:47:50PM -0700, Kukjin Kim wrote:
>>>
>>> Anyway Joerg, how do you want to handle this? Do you want to pick up
>>> 1/2/3 all of them in your tree? If so, 2nd patch should be on top of
>>> some samsung topic stuff.
>>
>>
>> Since patch 2 only applies to the Samsung tree, it is best to carry
>> this in your tree for merging. Feel free to add my Acked-by to patch 3.
>> But any further patches for the Exynos IOMMU drivers should go through
>> my tree after it is merged.
>>
>
> Hi Joerg,
>
> Now that 1st and 2nd can be applied cleanly into latest mainline. But
> unfortunately, I have no chance to send them to Linus now and I'm not sure
> you can do it during this merge window. If it is possible, please keep going
> on with my ack.
>
> KyongHo, just note, happens follwoing complaint with checkpatch, but I'm not
> sure this should be fixed right now. I think, if required, we can fix it
> later.
>
> ERROR: Macros with complex values should be enclosed in parenthesis
> #698: FILE: arch/arm/mach-exynos/dev-sysmmu.c:64:
>
> +#define DEFINE_SYSMMU_RESOURCE(core, mem, irq) ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem), ? ? ?\
> + ? ? ? DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
>
DEFINE_SYSMMU_RESOURCE macro defines 2 array elements. The replacement string
must not be enclosed by parenthesis.

> ERROR: Macros with complex values should be enclosed in parenthesis
> #702: FILE: arch/arm/mach-exynos/dev-sysmmu.c:68:
>
> +#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq) ? ? ? ? ? ? ? ? \
> + ? ? ? SYSMMU_RESOURCE(core, ipname) { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ? ? ? ? ? ? DEFINE_SYSMMU_RESOURCE(core, mem, irq) ? ? ? ? ? ? ? ? ?\
> + ? ? ? }
>
Ditto.

> WARNING: quoted string split across lines
> #914: FILE: arch/arm/mach-exynos/dev-sysmmu.c:259:
>
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pr_err("%s: Failed to add device resources
> for "
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "%s.%d\n", __func__,
>
It does not happened in the patch I posted and the email received also does
not have such problem. I wonder why the "pr_err(..." line is split into 2 lines.

Thank you for concerning :)

KyongHo.


From kgene.kim at samsung.com  Wed Mar 28 21:46:09 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 28 Mar 2012 18:46:09 -0700
Subject: [PATCH 3/4] ARM: Exynos5: Fix incorrect initialization of GIC
In-Reply-To: <1332840365-24827-4-git-send-email-thomas.abraham@linaro.org>
References: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>
 <1332840365-24827-4-git-send-email-thomas.abraham@linaro.org>
Message-ID: <4F73BEE1.5050301@samsung.com>

Thomas Abraham wrote:
> Use the of_irq_init() call to setup the gic which also properly registers
> the gic device node pointer with gic irq domain, without which all interrupt
> specifier translations for gic fail.
> 
> Signed-off-by: Thomas Abraham<thomas.ab at samsung.com>
> ---
>   arch/arm/mach-exynos/common.c |    2 +-
>   1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index f265dc4..3bf39a8 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -542,7 +542,7 @@ void __init exynos5_init_irq(void)
>   {
>   	int irq;
> 
> -	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
> +	of_irq_init(exynos4_dt_irq_match);
> 
>   	for (irq = 0; irq<  EXYNOS5_MAX_COMBINER_NR; irq++) {
>   		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),

Yes, right. The of_irq_init() shold be used instead. But I need to check
about the usage of SPI and if any updates, let you know :)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Wed Mar 28 21:54:52 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 28 Mar 2012 18:54:52 -0700
Subject: [PATCH 4/4] ARM: Exynos5: Add PDMA and MDMA physical base address
 defines
In-Reply-To: <1332840365-24827-5-git-send-email-thomas.abraham@linaro.org>
References: <1332840365-24827-1-git-send-email-thomas.abraham@linaro.org>
 <1332840365-24827-5-git-send-email-thomas.abraham@linaro.org>
Message-ID: <4F73C0EC.60201@samsung.com>

Thomas Abraham wrote:
> Add PDMA and MDMA physical base address macros which is require for Exynos5
> of_dev_auxdata setup.
> 
> Signed-off-by: Thomas Abraham<thomas.ab at samsung.com>
> ---
>   arch/arm/mach-exynos/include/mach/map.h |    5 +++++
>   arch/arm/mach-exynos/mach-exynos5-dt.c  |    3 ++-
>   2 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index 024d38f..37d93fd 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -90,6 +90,11 @@
>   #define EXYNOS4_PA_PDMA0		0x12680000
>   #define EXYNOS4_PA_PDMA1		0x12690000
> 
> +#define EXYNOS5_PA_PDMA0		0x121A0000
> +#define EXYNOS5_PA_PDMA1		0x121B0000
> +#define EXYNOS5_PA_MDMA0		0x10800000
> +#define EXYNOS5_PA_MDMA1		0x11C10000
> +

See, "ARM: EXYNOS: Support DMA for Exynos5250 SoC"
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/085434.html

But this merge window is not including it :(

>   #define EXYNOS4_PA_SYSMMU_MDMA		0x10A40000
>   #define EXYNOS4_PA_SYSMMU_SSS		0x10A50000
>   #define EXYNOS4_PA_SYSMMU_FIMC0		0x11A20000
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index 0d26f50..cdc3a26 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -45,7 +45,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
>   				"exynos4210-uart.3", NULL),
>   	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
>   	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
> -	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
> +	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA0, "dma-pl330.2", NULL),

OK.

> +	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA0, "dma-pl330.3", NULL),

Well...there is a MDMA1 on EXYNOS5250 SoC, so if we can use MDMA1,
should be MDMA1 for dma-pl330.3 but...I think, I need to check :)

>   	{},
>   };
> 

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Wed Mar 28 22:05:53 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 28 Mar 2012 19:05:53 -0700
Subject: [PATCH v4 05/12] ARM: EXYNOS: add support uart for EXYNOS4 and
 EXYNOS5
In-Reply-To: <CAJuYYwT5_EHPD4D+Qx0rX8bUVGLbLYUps2BYSUihLbuKGnhHdA@mail.gmail.com>
References: <1331736138-28964-1-git-send-email-kgene.kim@samsung.com>
 <1331736138-28964-6-git-send-email-kgene.kim@samsung.com>
 <CAJuYYwTJsA1M1Qj2P1-1K=pWzi0BPo8YJNDSx4NqGC7NX0030g@mail.gmail.com>
 <074401cd074f$c2946b90$47bd42b0$%szyprowski@samsung.com>
 <4F6B3256.40304@samsung.com>
 <CAJuYYwT5_EHPD4D+Qx0rX8bUVGLbLYUps2BYSUihLbuKGnhHdA@mail.gmail.com>
Message-ID: <4F73C381.1090504@samsung.com>

Thomas Abraham wrote:
> 2012/3/22 Kukjin Kim<kgene.kim at samsung.com>:
>> On 03/21/12 03:45, Marek Szyprowski wrote:
>>>
>>> Hello,
>>>
>>> On Wednesday, March 21, 2012 10:14 AM Thomas Abraham wrote:
>>>
>>>> On 14 March 2012 20:12, Kukjin Kim<kgene.kim at samsung.com>    wrote:
>>>>>
>>>>> Actually, the base address of uart is different between EXYNOS4
>>>>> and EXYNOS5 and this patch enables to support uart for EXYNOS4
>>>>> and EXYNOS5 SoCs at runtime.
>>>>>
>>>>> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
>>>>> ---
>>>>
>>>>
>>>> [...]
>>>>
>>>>> diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S
>>>>> b/arch/arm/mach-
>>>>
>>>> exynos/include/mach/debug-macro.S
>>>>>
>>>>> index 6cacf16..6c857ff 100644
>>>>> --- a/arch/arm/mach-exynos/include/mach/debug-macro.S
>>>>> +++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
>>>>> @@ -21,8 +21,13 @@
>>>>>          */
>>>>>
>>>>>         .macro addruart, rp, rv, tmp
>>>>> -               ldr     \rp, = S3C_PA_UART
>>>>> -               ldr     \rv, = S3C_VA_UART
>>>>> +               mov     \rp, #0x10000000
>>>>
>>>>
>>>> This is physical address of Exynos4/5 CPUID register which cannot be
>>>> used here. And virtual address S5P_VA_CPUID also cannot be used here
>>>> since this will be called before paging_init when earlyprintk boot
>>>> param is used. So, with this change, earlyprintk does not work for
>>>> both Exynos4 and Exynos5.
>>>
>>>
>>> I confirm, printascii freeze the system on EXYNOS4 after that patch,
>>> tested on Exynos4210 Nuri board.
>>>
>> Hi,
>>
>> I think, it can be solved with following and if no problems, it will be
>> fixed during v3.4-rcX.
>>
>> diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S
>> b/arch/arm/mach-exynos/in
>> index 6c857ff..a865417 100644
>> --- a/arch/arm/mach-exynos/include/mach/debug-macro.S
>> +++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
>> @@ -21,10 +21,10 @@
>>
>>          */
>>
>>         .macro addruart, rp, rv, tmp
>> -               mov     \rp, #0x10000000
>> -               ldr     \rp, [\rp, #0x0]
>> -               and     \rp, \rp, #0xf00000
>> -               teq     \rp, #0x500000          @@ EXYNOS5
>> +               mrc     p15, 0, \tmp, c0, c0, 0
>> +               and     \tmp, \tmp, #0xf0
>> +               teq     \tmp, #0xf0             @@ A15
>> +
>>                 ldreq   \rp, =EXYNOS5_PA_UART
>>
>>                 movne   \rp, #EXYNOS4_PA_UART   @@ EXYNOS4
>>                 ldr     \rv, =S3C_VA_UART
>>
>
> Dear Mr. Kim,
>
> I have tested the above patch on Exynos5. Thanks.
>
> Tested-by: Thomas Abraham<thomas.abraham at linaro.org>

Hi Marek, Thomas,

Thanks for your test.
I will apply above patch with your 'Tested-by:...'

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From shawn.guo at linaro.org  Wed Mar 28 22:37:20 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 29 Mar 2012 10:37:20 +0800
Subject: i.MX28 die temperature
In-Reply-To: <330B740BA662BF4E8386F534DF556ED819731A@AEDCEXC09.aei.com>
References: <330B740BA662BF4E8386F534DF556ED819731A@AEDCEXC09.aei.com>
Message-ID: <20120329023718.GC3254@S2101-09.ap.freescale.net>

On Wed, Mar 28, 2012 at 03:13:57PM +0000, Randle, Bill wrote:
> Has anyone developed a driver for reading the die temperature from the i.MX28? I haven't found anything yet in my searching, but didn't want to duplicate effort if someone has something already.
> 
The mainline kernel has no support for it, but the release from
Freescale has.

  arch/arm/mach-mx28/device.c (battery_data)
  drivers/power/mxs/ddi_bc_ramp.c

It'd be nice if you can bring it to mainline.

-- 
Regards,
Shawn


From b32955 at freescale.com  Wed Mar 28 22:45:26 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 29 Mar 2012 10:45:26 +0800
Subject: [PATCH V2 1/3] lib: add support for stmp-style devices
In-Reply-To: <1332368519-22660-2-git-send-email-w.sang@pengutronix.de>
References: <1332368519-22660-1-git-send-email-w.sang@pengutronix.de>
 <1332368519-22660-2-git-send-email-w.sang@pengutronix.de>
Message-ID: <4F73CCC6.6000001@freescale.com>

Hi Wolfram:
>  include/linux/stmp_device.h |   20 +++++++++++
IMHO, this header should be placed at include/linux/fsl/.
But the patch "mxs-dma : move the mxs dma.h to a more common place" is
still in the l2-mtd tree, not pushed
to upstream. :(

BR
Huang Shijie




From shawn.guo at linaro.org  Wed Mar 28 22:53:41 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 29 Mar 2012 10:53:41 +0800
Subject: [PATCH] ASoC: fsl: enable ssi clock in probe function
Message-ID: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>

For power saving, most IMX platform initilization code turns off
modules' clock, and expects driver turn on clock as needed.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 sound/soc/fsl/fsl_ssi.c |   24 ++++++++++++++++++++++--
 1 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 4f76b5d..4ed2afd 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
+#include <linux/clk.h>
 #include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
@@ -119,6 +120,7 @@ struct fsl_ssi_private {
 
 	bool new_binding;
 	bool ssi_on_imx;
+	struct clk *clk;
 	struct platform_device *imx_pcm_pdev;
 	struct imx_pcm_dma_params dma_params_tx;
 	struct imx_pcm_dma_params dma_params_rx;
@@ -722,6 +724,15 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
 		u32 dma_events[2];
 		ssi_private->ssi_on_imx = true;
+
+		ssi_private->clk = clk_get(&pdev->dev, NULL);
+		if (IS_ERR(ssi_private->clk)) {
+			ret = PTR_ERR(ssi_private->clk);
+			dev_err(&pdev->dev, "could not get clock: %d\n", ret);
+			goto error_irq;
+		}
+		clk_prepare_enable(ssi_private->clk);
+
 		/*
 		 * We have burstsize be "fifo_depth - 2" to match the SSI
 		 * watermark setting in fsl_ssi_startup().
@@ -742,7 +753,7 @@ static int __devinit fsl_ssi_probe(struct platform_device *pdev)
 					"fsl,ssi-dma-events", dma_events, 2);
 		if (ret) {
 			dev_err(&pdev->dev, "could not get dma events\n");
-			goto error_irq;
+			goto error_clk;
 		}
 		ssi_private->dma_params_tx.dma = dma_events[0];
 		ssi_private->dma_params_rx.dma = dma_events[1];
@@ -830,6 +841,12 @@ error_dev:
 	dev_set_drvdata(&pdev->dev, NULL);
 	device_remove_file(&pdev->dev, dev_attr);
 
+error_clk:
+	if (ssi_private->ssi_on_imx) {
+		clk_disable_unprepare(ssi_private->clk);
+		clk_put(ssi_private->clk);
+	}
+
 error_irq:
 	free_irq(ssi_private->irq, ssi_private);
 
@@ -851,8 +868,11 @@ static int fsl_ssi_remove(struct platform_device *pdev)
 
 	if (!ssi_private->new_binding)
 		platform_device_unregister(ssi_private->pdev);
-	if (ssi_private->ssi_on_imx)
+	if (ssi_private->ssi_on_imx) {
 		platform_device_unregister(ssi_private->imx_pcm_pdev);
+		clk_disable_unprepare(ssi_private->clk);
+		clk_put(ssi_private->clk);
+	}
 	snd_soc_unregister_dai(&pdev->dev);
 	device_remove_file(&pdev->dev, &ssi_private->dev_attr);
 
-- 
1.7.5.4



From kgene.kim at samsung.com  Wed Mar 28 23:15:35 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 28 Mar 2012 20:15:35 -0700
Subject: [PATCH v3 0/6] mmc: sdhci-s3c: Rework platform data and add device
 tree support
In-Reply-To: <20120328095450.GA23005@sirena.org.uk>
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>
 <003401cce730$baf979a0$30ec6ce0$%kim@samsung.com>
 <m2aa4pkq5g.fsf@bob.laptop.org> <4F3CFEED.6060206@samsung.com>
 <m239abgc32.fsf@bob.laptop.org>
 <00b901ccf08d$2fc18b50$8f44a1f0$%kim@samsung.com>
 <m2vcn0496y.fsf@bob.laptop.org> <87k426vy9r.fsf@laptop.org>
 <20120328095450.GA23005@sirena.org.uk>
Message-ID: <4F73D3D7.1010202@samsung.com>

On 03/28/12 02:54, Mark Brown wrote:
> On Tue, Mar 27, 2012 at 11:50:24AM -0400, Chris Ball wrote:
>> On Tue, Feb 21 2012, Chris Ball wrote:
>>> On Tue, Feb 21 2012, Kukjin Kim wrote:
>
>>>> I created topic branch for this we talked. You can pull that following:
>>>>    git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
>>>> v3.4-for-cjb
>
>>>> If any problems, please kindly let me know.
>
>>> Pushed to mmc-next, thanks.  (I'm expecting that you'll do the merge
>>> to Linus.)
>
>> I was expecting you to merge these patches, but they aren't in the
>> arm-soc tree and haven't been sent to Linus,

(Cc'ed Olof and Arnd)

Chris, Yeah, it is not in arm-soc tree now. Because I sent a pull 
request of samsung-mmc which is including this v3.4-for-cjb but Olof 
wanted to merge only arch/arm/ part for samsung mmc because they are not 
unrelated to the branch, v3.4-for-cjb sent to you. Since I thought the 
branch would be sent to upstream via your tree and you were included in 
the mailing loop, I agreed. So there is no it in arm-soc.

>> and we're in the last few
>> days of the merge window.
>
Yeah...it means not closed yet ;)

>> As a result I'm dropping this tree -- and all of the patches that I
>> have on top of it -- from mmc-next so that I can get a pull request
>> out.  This means that I'm dropping:
>
Hmm, I think, if you're ok, you can send a second pull request to Linus 
for it and actually, it is in linux-next for a long time via mmc and 
samsung tree.

Note, please don't rebase it because its resolution for conflicts is in 
linux-next and I think Linus will use it when happens conflicts...Or I 
can provide new tree on top of latest mainline. But I'm not sure about 
latter.

> If they're already in your tree why not just send them to Linus?  Given
> that everything's in git I don't understand why you'd need Kukjin to
> push them separately or what the benefit of that would be?
>
Yes, I already agreed its merging in the mmc tree :)

> This is all extremely frustrating fromm the contributor point of view.

If any my effort is required, feel free to contact me.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From inderpal.singh at linaro.org  Wed Mar 28 23:25:17 2012
From: inderpal.singh at linaro.org (Inderpal Singh)
Date: Thu, 29 Mar 2012 08:55:17 +0530
Subject: [PATCH] ARM: EXYNOS4: Support Suspend/Resume for EXYNOS4412
Message-ID: <1332991517-3083-1-git-send-email-inderpal.singh@linaro.org>

This patch provides the suspend/resume support for EXYNOS4412.

Signed-off-by: Inderpal Singh <inderpal.singh at linaro.org>
---
 arch/arm/mach-exynos/include/mach/regs-pmu.h |   10 +++++++++-
 arch/arm/mach-exynos/pm.c                    |    2 +-
 arch/arm/mach-exynos/pmu.c                   |   24 ++++++++++++++++++++----
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4c53f38..606b199 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -177,7 +177,7 @@
 
 #define S5P_PMU_LCD1_CONF		S5P_PMUREG(0x3CA0)
 
-/* Only for EXYNOS4212 */
+/* Only for EXYNOS4x12 */
 #define S5P_ISP_ARM_LOWPWR			S5P_PMUREG(0x1050)
 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR	S5P_PMUREG(0x1054)
 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR	S5P_PMUREG(0x1058)
@@ -218,4 +218,12 @@
 #define S5P_SECSS_MEM_OPTION			S5P_PMUREG(0x2EC8)
 #define S5P_ROTATOR_MEM_OPTION			S5P_PMUREG(0x2F48)
 
+/* Only for EXYNOS4412 */
+#define S5P_ARM_CORE2_LOWPWR			S5P_PMUREG(0x1020)
+#define S5P_DIS_IRQ_CORE2			S5P_PMUREG(0x1024)
+#define S5P_DIS_IRQ_CENTRAL2			S5P_PMUREG(0x1028)
+#define S5P_ARM_CORE3_LOWPWR			S5P_PMUREG(0x1030)
+#define S5P_DIS_IRQ_CORE3			S5P_PMUREG(0x1034)
+#define S5P_DIS_IRQ_CENTRAL3			S5P_PMUREG(0x1038)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 428cfeb..f0bb467 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -313,7 +313,7 @@ static int exynos4_pm_suspend(void)
 	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
-	if (soc_is_exynos4212()) {
+	if (soc_is_exynos4212() || soc_is_exynos4412()) {
 		tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
 		tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
 			 S5P_USE_STANDBYWFE_ISP_ARM);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index bba48f5..77c6815 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
 	{ PMU_TABLE_END,},
 };
 
-static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
+static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
 	{ S5P_ARM_CORE0_LOWPWR,			{ 0x0, 0x0, 0x2 } },
 	{ S5P_DIS_IRQ_CORE0,			{ 0x0, 0x0, 0x0 } },
 	{ S5P_DIS_IRQ_CENTRAL0,			{ 0x0, 0x0, 0x0 } },
@@ -202,6 +202,16 @@ static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
 	{ PMU_TABLE_END,},
 };
 
+static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
+	{ S5P_ARM_CORE2_LOWPWR,			{ 0x0, 0x0, 0x2 } },
+	{ S5P_DIS_IRQ_CORE2,			{ 0x0, 0x0, 0x0 } },
+	{ S5P_DIS_IRQ_CENTRAL2,			{ 0x0, 0x0, 0x0 } },
+	{ S5P_ARM_CORE3_LOWPWR,			{ 0x0, 0x0, 0x2 } },
+	{ S5P_DIS_IRQ_CORE3,			{ 0x0, 0x0, 0x0 } },
+	{ S5P_DIS_IRQ_CENTRAL3,			{ 0x0, 0x0, 0x0 } },
+	{ PMU_TABLE_END,},
+};
+
 void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
 {
 	unsigned int i;
@@ -209,6 +219,12 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
 	for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
 		__raw_writel(exynos4_pmu_config[i].val[mode],
 				exynos4_pmu_config[i].reg);
+
+	if (soc_is_exynos4412()) {
+		for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
+			__raw_writel(exynos4412_pmu_config[i].val[mode],
+				exynos4412_pmu_config[i].reg);
+	}
 }
 
 static int __init exynos4_pmu_init(void)
@@ -218,9 +234,9 @@ static int __init exynos4_pmu_init(void)
 	if (soc_is_exynos4210()) {
 		exynos4_pmu_config = exynos4210_pmu_config;
 		pr_info("EXYNOS4210 PMU Initialize\n");
-	} else if (soc_is_exynos4212()) {
-		exynos4_pmu_config = exynos4212_pmu_config;
-		pr_info("EXYNOS4212 PMU Initialize\n");
+	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+		exynos4_pmu_config = exynos4x12_pmu_config;
+		pr_info("EXYNOS4x12 PMU Initialize\n");
 	} else {
 		pr_info("EXYNOS4: PMU not supported\n");
 	}
-- 
1.7.5.4



From nico at fluxnic.net  Thu Mar 29 00:00:20 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 29 Mar 2012 00:00:20 -0400
Subject: [PATCH 0/4] memcpy optimized with strd/ldrd
In-Reply-To: <alpine.LFD.2.02.1203280119550.24151@xanadu.home>
References: <alpine.LFD.2.02.1203280119550.24151@xanadu.home>
Message-ID: <1332993624-16552-1-git-send-email-nico@fluxnic.net>


Here's my version.  Lightly tested.
I have no A15 hardware to run any performance comparison though.



From nico at fluxnic.net  Thu Mar 29 00:00:21 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 29 Mar 2012 00:00:21 -0400
Subject: [PATCH 1/4] ARM: copy_template.S: move some registers around
In-Reply-To: <1332993624-16552-1-git-send-email-nico@fluxnic.net>
References: <alpine.LFD.2.02.1203280119550.24151@xanadu.home>
 <1332993624-16552-1-git-send-email-nico@fluxnic.net>
Message-ID: <1332993624-16552-2-git-send-email-nico@fluxnic.net>

From: Nicolas Pitre <nicolas.pitre at linaro.org>

The copy length is held in r2, making it difficult to use a consecutive
set of registers starting on an even register number as required by the
LDRD and STRD instructions.  Let's move the length to lr instead, and
adjust affected code accordingly.

Functionally speaking, this patch is a no-op.

Signed-off-by: nicolas Pitre <nico at linaro.org>
---
 arch/arm/lib/copy_template.S |   92 +++++++++++++++++++++---------------------
 1 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 805e3f8fb0..7244dcef0d 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -69,7 +69,7 @@
 
 		enter	r4, lr
 
-		subs	r2, r2, #4
+		subs	lr, r2, #4
 		blt	8f
 		ands	ip, r0, #3
 	PLD(	pld	[r1, #0]		)
@@ -77,34 +77,34 @@
 		ands	ip, r1, #3
 		bne	10f
 
-1:		subs	r2, r2, #(28)
+1:		subs	lr, lr, #(28)
 		stmfd	sp!, {r5 - r8}
 		blt	5f
 
 	CALGN(	ands	ip, r0, #31		)
 	CALGN(	rsb	r3, ip, #32		)
-	CALGN(	sbcnes	r4, r3, r2		)  @ C is always set here
+	CALGN(	sbcnes	r4, r3, lr		)  @ C is always set here
 	CALGN(	bcs	2f			)
 	CALGN(	adr	r4, 6f			)
-	CALGN(	subs	r2, r2, r3		)  @ C gets set
+	CALGN(	subs	lr, lr, r3		)  @ C gets set
 	CALGN(	add	pc, r4, ip		)
 
 	PLD(	pld	[r1, #0]		)
-2:	PLD(	subs	r2, r2, #96		)
+2:	PLD(	subs	lr, lr, #96		)
 	PLD(	pld	[r1, #28]		)
 	PLD(	blt	4f			)
 	PLD(	pld	[r1, #60]		)
 	PLD(	pld	[r1, #92]		)
 
 3:	PLD(	pld	[r1, #124]		)
-4:		ldr8w	r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
-		subs	r2, r2, #32
-		str8w	r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
+4:		ldr8w	r1, r2, r3, r4, r5, r6, r7, r8, ip, abort=20f
+		subs	lr, lr, #32
+		str8w	r0, r2, r3, r4, r5, r6, r7, r8, ip, abort=20f
 		bge	3b
-	PLD(	cmn	r2, #96			)
+	PLD(	cmn	lr, #96			)
 	PLD(	bge	4b			)
 
-5:		ands	ip, r2, #28
+5:		ands	ip, lr, #28
 		rsb	ip, ip, #32
 #if LDR1W_SHIFT > 0
 		lsl	ip, ip, #LDR1W_SHIFT
@@ -115,13 +115,13 @@
 		.rept	(1 << LDR1W_SHIFT)
 		W(nop)
 		.endr
+		ldr1w	r1, r2, abort=20f
 		ldr1w	r1, r3, abort=20f
 		ldr1w	r1, r4, abort=20f
 		ldr1w	r1, r5, abort=20f
 		ldr1w	r1, r6, abort=20f
 		ldr1w	r1, r7, abort=20f
 		ldr1w	r1, r8, abort=20f
-		ldr1w	r1, lr, abort=20f
 
 #if LDR1W_SHIFT < STR1W_SHIFT
 		lsl	ip, ip, #STR1W_SHIFT - LDR1W_SHIFT
@@ -133,73 +133,75 @@
 		.rept	(1 << STR1W_SHIFT)
 		W(nop)
 		.endr
+		str1w	r0, r2, abort=20f
 		str1w	r0, r3, abort=20f
 		str1w	r0, r4, abort=20f
 		str1w	r0, r5, abort=20f
 		str1w	r0, r6, abort=20f
 		str1w	r0, r7, abort=20f
 		str1w	r0, r8, abort=20f
-		str1w	r0, lr, abort=20f
 
 	CALGN(	bcs	2b			)
 
 7:		ldmfd	sp!, {r5 - r8}
 
-8:		movs	r2, r2, lsl #31
-		ldr1b	r1, r3, ne, abort=21f
+8:		movs	lr, lr, lsl #31
+		ldr1b	r1, r2, ne, abort=21f
+		ldr1b	r1, r3, cs, abort=21f
 		ldr1b	r1, r4, cs, abort=21f
-		ldr1b	r1, ip, cs, abort=21f
-		str1b	r0, r3, ne, abort=21f
+		str1b	r0, r2, ne, abort=21f
+		str1b	r0, r3, cs, abort=21f
 		str1b	r0, r4, cs, abort=21f
-		str1b	r0, ip, cs, abort=21f
 
 		exit	r4, pc
 
 9:		rsb	ip, ip, #4
 		cmp	ip, #2
-		ldr1b	r1, r3, gt, abort=21f
-		ldr1b	r1, r4, ge, abort=21f
-		ldr1b	r1, lr, abort=21f
-		str1b	r0, r3, gt, abort=21f
-		str1b	r0, r4, ge, abort=21f
-		subs	r2, r2, ip
-		str1b	r0, lr, abort=21f
+		ldr1b	r1, r2, gt, abort=21f
+		ldr1b	r1, r3, ge, abort=21f
+		ldr1b	r1, r4, abort=21f
+		str1b	r0, r2, gt, abort=21f
+		str1b	r0, r3, ge, abort=21f
+		subs	lr, lr, ip
+		str1b	r0, r4, abort=21f
 		blt	8b
 		ands	ip, r1, #3
 		beq	1b
 
 10:		bic	r1, r1, #3
 		cmp	ip, #2
-		ldr1w	r1, lr, abort=21f
+		ldr1w	r1, ip, abort=21f
 		beq	17f
 		bgt	18f
 
 
 		.macro	forward_copy_shift pull push
 
-		subs	r2, r2, #28
+		subs	lr, lr, #28
 		blt	14f
 
-	CALGN(	ands	ip, r0, #31		)
-	CALGN(	rsb	ip, ip, #32		)
-	CALGN(	sbcnes	r4, ip, r2		)  @ C is always set here
-	CALGN(	subcc	r2, r2, ip		)
+	CALGN(	ands	r3, r0, #31		)
+	CALGN(	rsb	r3, r3, #32		)
+	CALGN(	sbcnes	r4, r3, lr		)  @ C is always set here
+	CALGN(	subcc	lr, lr, r3		)
 	CALGN(	bcc	15f			)
 
 11:		stmfd	sp!, {r5 - r9}
 
 	PLD(	pld	[r1, #0]		)
-	PLD(	subs	r2, r2, #96		)
+	PLD(	subs	lr, lr, #96		)
 	PLD(	pld	[r1, #28]		)
 	PLD(	blt	13f			)
 	PLD(	pld	[r1, #60]		)
 	PLD(	pld	[r1, #92]		)
 
 12:	PLD(	pld	[r1, #124]		)
-13:		ldr4w	r1, r4, r5, r6, r7, abort=19f
-		mov	r3, lr, pull #\pull
-		subs	r2, r2, #32
-		ldr4w	r1, r8, r9, ip, lr, abort=19f
+13:		ldr4w	r1, r3, r4, r5, r6, abort=19f
+		mov	r2, ip, pull #\pull
+		subs	lr, lr, #32
+		ldr4w	r1, r7, r8, r9, ip, abort=19f
+		orr	r2, r2, r3, push #\push
+		mov	r3, r3, pull #\pull
 		orr	r3, r3, r4, push #\push
 		mov	r4, r4, pull #\pull
 		orr	r4, r4, r5, push #\push
@@ -213,25 +215,23 @@
 		orr	r8, r8, r9, push #\push
 		mov	r9, r9, pull #\pull
 		orr	r9, r9, ip, push #\push
-		mov	ip, ip, pull #\pull
-		orr	ip, ip, lr, push #\push
-		str8w	r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
+		str8w	r0, r2, r3, r4, r5, r6, r7, r8, r9, abort=19f
 		bge	12b
-	PLD(	cmn	r2, #96			)
+	PLD(	cmn	lr, #96			)
 	PLD(	bge	13b			)
 
 		ldmfd	sp!, {r5 - r9}
 
-14:		ands	ip, r2, #28
+14:		ands	r3, lr, #28
 		beq	16f
 
-15:		mov	r3, lr, pull #\pull
-		ldr1w	r1, lr, abort=21f
-		subs	ip, ip, #4
-		orr	r3, r3, lr, push #\push
-		str1w	r0, r3, abort=21f
+15:		mov	r2, ip, pull #\pull
+		ldr1w	r1, ip, abort=21f
+		subs	r3, r3, #4
+		orr	r2, r2, ip, push #\push
+		str1w	r0, r2, abort=21f
 		bgt	15b
-	CALGN(	cmp	r2, #0			)
+	CALGN(	cmp	lr, #0			)
 	CALGN(	bge	11b			)
 
 16:		sub	r1, r1, #(\push / 8)
-- 
1.7.9.rc2



From nico at fluxnic.net  Thu Mar 29 00:00:22 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 29 Mar 2012 00:00:22 -0400
Subject: [PATCH 2/4] ARM: copy_template.S: rework the unaligned copy loop
In-Reply-To: <1332993624-16552-1-git-send-email-nico@fluxnic.net>
References: <alpine.LFD.2.02.1203280119550.24151@xanadu.home>
 <1332993624-16552-1-git-send-email-nico@fluxnic.net>
Message-ID: <1332993624-16552-3-git-send-email-nico@fluxnic.net>

From: Nicolas Pitre <nicolas.pitre at linaro.org>

Let's rework the unaligned copy loop to enforce a range of contigous
registers starting from an even register, and to use a single ldr8w
construct instead of two ldr4w's.  There are no users of ldr4w anymore,
so its various definitions are removed.

By using one additional temporary registers, it is possible to have the
same register set for the loads and the stores, and to make the loop
friendlier to superscalar CPUs at the same time.

Signed-off-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/lib/copy_from_user.S |   11 +++----
 arch/arm/lib/copy_template.S  |   57 ++++++++++++++++++++---------------------
 arch/arm/lib/copy_to_user.S   |    4 ---
 arch/arm/lib/memcpy.S         |    4 ---
 4 files changed, 33 insertions(+), 43 deletions(-)

diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
index 66a477a3e3..d1df0ec62b 100644
--- a/arch/arm/lib/copy_from_user.S
+++ b/arch/arm/lib/copy_from_user.S
@@ -44,16 +44,15 @@
 	ldrusr	\reg, \ptr, 4, abort=\abort
 	.endm
 
-	.macro ldr4w ptr reg1 reg2 reg3 reg4 abort
+	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
 	ldr1w \ptr, \reg1, \abort
 	ldr1w \ptr, \reg2, \abort
 	ldr1w \ptr, \reg3, \abort
 	ldr1w \ptr, \reg4, \abort
-	.endm
-
-	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
-	ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
-	ldr4w \ptr, \reg5, \reg6, \reg7, \reg8, \abort
+	ldr1w \ptr, \reg5, \abort
+	ldr1w \ptr, \reg6, \abort
+	ldr1w \ptr, \reg7, \abort
+	ldr1w \ptr, \reg8, \abort
 	.endm
 
 	.macro ldr1b ptr reg cond=al abort
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 7244dcef0d..84e94cd48c 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -27,10 +27,9 @@
  *	This loads one word from 'ptr', stores it in 'reg' and increments
  *	'ptr' to the next word. The 'abort' argument is used for fixup tables.
  *
- * ldr4w ptr reg1 reg2 reg3 reg4 abort
  * ldr8w ptr, reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
  *
- *	This loads four or eight words starting from 'ptr', stores them
+ *	This loads eight words starting from 'ptr', stores them
  *	in provided registers and increments 'ptr' past those words.
  *	The'abort' argument is used for fixup tables.
  *
@@ -63,7 +62,7 @@
  *
  *	Correction to be applied to the "ip" register when branching into
  *	the ldr1w or str1w instructions (some of these macros may expand to
- *	than one 32bit instruction in Thumb-2)
+ *	more than one 32bit instruction in Thumb-2)
  */
 
 
@@ -170,7 +169,7 @@
 
 10:		bic	r1, r1, #3
 		cmp	ip, #2
-		ldr1w	r1, ip, abort=21f
+		ldr1w	r1, r2, abort=21f
 		beq	17f
 		bgt	18f
 
@@ -178,6 +177,7 @@
 		.macro	forward_copy_shift pull push
 
 		subs	lr, lr, #28
+		mov	ip, r2, pull #\pull
 		blt	14f
 
 	CALGN(	ands	r3, r0, #31		)
@@ -186,7 +186,7 @@
 	CALGN(	subcc	lr, lr, r3		)
 	CALGN(	bcc	15f			)
 
-11:		stmfd	sp!, {r5 - r9}
+11:		stmfd	sp!, {r5 - sl}
 
 	PLD(	pld	[r1, #0]		)
 	PLD(	subs	lr, lr, #96		)
@@ -196,40 +196,39 @@
 	PLD(	pld	[r1, #92]		)
 
 12:	PLD(	pld	[r1, #124]		)
-13:		ldr4w	r1, r3, r4, r5, r6, abort=19f
-		mov	r2, ip, pull #\pull
+13:		ldr8w	r1, r2, r3, r4, r5, r6, r7, r8, r9, abort=19f
 		subs	lr, lr, #32
-		ldr4w	r1, r7, r8, r9, ip, abort=19f
-		orr	r2, r2, r3, push #\push
-		mov	r3, r3, pull #\pull
-		orr	r3, r3, r4, push #\push
-		mov	r4, r4, pull #\pull
-		orr	r4, r4, r5, push #\push
-		mov	r5, r5, pull #\pull
-		orr	r5, r5, r6, push #\push
-		mov	r6, r6, pull #\pull
-		orr	r6, r6, r7, push #\push
-		mov	r7, r7, pull #\pull
-		orr	r7, r7, r8, push #\push
-		mov	r8, r8, pull #\pull
-		orr	r8, r8, r9, push #\push
-		mov	r9, r9, pull #\pull
-		orr	r9, r9, ip, push #\push
+		mov	sl, r2, pull #\pull
+		orr	r2, ip, r2, push #\push
+		mov	ip, r3, pull #\pull
+		orr	r3, sl, r3, push #\push
+		mov	sl, r4, pull #\pull
+		orr	r4, ip, r4, push #\push
+		mov	ip, r5, pull #\pull
+		orr	r5, sl, r5, push #\push
+		mov	sl, r6, pull #\pull
+		orr	r6, ip, r6, push #\push
+		mov	ip, r7, pull #\pull
+		orr	r7, sl, r7, push #\push
+		mov	sl, r8, pull #\pull
+		orr	r8, ip, r8, push #\push
+		mov	ip, r9, pull #\pull
+		orr	r9, sl, r9, push #\push
 		str8w	r0, r2, r3, r4, r5, r6, r7, r8, r9, abort=19f
 		bge	12b
 	PLD(	cmn	lr, #96			)
 	PLD(	bge	13b			)
 
-		ldmfd	sp!, {r5 - r9}
+		ldmfd	sp!, {r5 - sl}
 
 14:		ands	r3, lr, #28
 		beq	16f
 
-15:		mov	r2, ip, pull #\pull
-		ldr1w	r1, ip, abort=21f
+15:		ldr1w	r1, r2, abort=21f
 		subs	r3, r3, #4
-		orr	r2, r2, ip, push #\push
-		str1w	r0, r2, abort=21f
+		orr	r4, ip, r2, push #\push
+		mov	ip, r2, pull #\pull
+		str1w	r0, r4, abort=21f
 		bgt	15b
 	CALGN(	cmp	lr, #0			)
 	CALGN(	bge	11b			)
@@ -255,7 +254,7 @@
  */
 
 	.macro	copy_abort_preamble
-19:	ldmfd	sp!, {r5 - r9}
+19:	ldmfd	sp!, {r5 - sl}
 	b	21f
 20:	ldmfd	sp!, {r5 - r8}
 21:
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index d066df686e..a83bc04365 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -44,10 +44,6 @@
 	W(ldr) \reg, [\ptr], #4
 	.endm
 
-	.macro ldr4w ptr reg1 reg2 reg3 reg4 abort
-	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
-	.endm
-
 	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
 	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
 	.endm
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index a9b9e2287a..adbccc6e2d 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -20,10 +20,6 @@
 	W(ldr) \reg, [\ptr], #4
 	.endm
 
-	.macro ldr4w ptr reg1 reg2 reg3 reg4 abort
-	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
-	.endm
-
 	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
 	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
 	.endm
-- 
1.7.9.rc2



From nico at fluxnic.net  Thu Mar 29 00:00:23 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 29 Mar 2012 00:00:23 -0400
Subject: [PATCH 3/4] ARM: copy_template.S: enforce contigous register set with
 memory accessors
In-Reply-To: <1332993624-16552-1-git-send-email-nico@fluxnic.net>
References: <alpine.LFD.2.02.1203280119550.24151@xanadu.home>
 <1332993624-16552-1-git-send-email-nico@fluxnic.net>
Message-ID: <1332993624-16552-4-git-send-email-nico@fluxnic.net>

From: Nicolas Pitre <nicolas.pitre at linaro.org>

Let's enforce a range of contigous registers with the remaining ldr8w
and str8w accessors.  An additional register needs to be preserved to
achieve this although not strictly necessary otherwise, but this will
allow for a greater flexibility inthe accessor implementation.

Signed-off-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/lib/copy_template.S |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 84e94cd48c..f6f42c3330 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -77,7 +77,7 @@
 		bne	10f
 
 1:		subs	lr, lr, #(28)
-		stmfd	sp!, {r5 - r8}
+		stmfd	sp!, {r5 - r9}
 		blt	5f
 
 	CALGN(	ands	ip, r0, #31		)
@@ -96,9 +96,9 @@
 	PLD(	pld	[r1, #92]		)
 
 3:	PLD(	pld	[r1, #124]		)
-4:		ldr8w	r1, r2, r3, r4, r5, r6, r7, r8, ip, abort=20f
+4:		ldr8w	r1, r2, r3, r4, r5, r6, r7, r8, r9, abort=20f
 		subs	lr, lr, #32
-		str8w	r0, r2, r3, r4, r5, r6, r7, r8, ip, abort=20f
+		str8w	r0, r2, r3, r4, r5, r6, r7, r8, r9, abort=20f
 		bge	3b
 	PLD(	cmn	lr, #96			)
 	PLD(	bge	4b			)
@@ -142,7 +142,7 @@
 
 	CALGN(	bcs	2b			)
 
-7:		ldmfd	sp!, {r5 - r8}
+7:		ldmfd	sp!, {r5 - r9}
 
 8:		movs	lr, lr, lsl #31
 		ldr1b	r1, r2, ne, abort=21f
@@ -256,7 +256,7 @@
 	.macro	copy_abort_preamble
 19:	ldmfd	sp!, {r5 - sl}
 	b	21f
-20:	ldmfd	sp!, {r5 - r8}
+20:	ldmfd	sp!, {r5 - r9}
 21:
 	.endm
 
-- 
1.7.9.rc2



From nico at fluxnic.net  Thu Mar 29 00:00:24 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 29 Mar 2012 00:00:24 -0400
Subject: [PATCH 4/4] ARM: option to select LDRD/STRD optimized memory copy
In-Reply-To: <1332993624-16552-1-git-send-email-nico@fluxnic.net>
References: <alpine.LFD.2.02.1203280119550.24151@xanadu.home>
 <1332993624-16552-1-git-send-email-nico@fluxnic.net>
Message-ID: <1332993624-16552-5-git-send-email-nico@fluxnic.net>

From: Nicolas Pitre <nicolas.pitre at linaro.org>

Because STRD requires a 64-bit aligned destination pointer, we
unconditionally enable the cache alignment code.

Same concern with LDRD, but we conditionally execute them or the LDM
fallback depending on the source pointer alignment.

Obviously, this could be optimized further by duplicating each loop and
increasing the code.  Convincing benchmarks would be in order before
doing so.

Signed-off-by: Nicolas Pitre <nico at linaro.org>
---
 arch/arm/Kconfig              |    9 +++++++++
 arch/arm/lib/copy_from_user.S |   15 ++++++++++++++-
 arch/arm/lib/copy_template.S  |    3 +++
 arch/arm/lib/copy_to_user.S   |   11 ++++++++++-
 arch/arm/lib/memcpy.S         |   26 ++++++++++++++++++++++++--
 5 files changed, 60 insertions(+), 4 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5098564d58..b87069730a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1826,6 +1826,15 @@ config UACCESS_WITH_MEMCPY
 	  However, if the CPU data cache is using a write-allocate mode,
 	  this option is unlikely to provide any performance gain.
 
+config USE_LDRDSTRD_OVER_LDMSTM
+	bool "Use 64-bit access instructions to optimize memory copy"
+	depends on CPU_V7
+	help
+	  Some processors, notably the Cortex-A15, are known to perform
+	  better when accessing memory using LDRD/STRD instructions instead
+	  of LDM/STM.  Select this to optimize memory copy routines
+	  accordingly.
+
 config SECCOMP
 	bool
 	prompt "Enable seccomp to safely compute untrusted bytecode"
diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
index d1df0ec62b..375cbbf0e5 100644
--- a/arch/arm/lib/copy_from_user.S
+++ b/arch/arm/lib/copy_from_user.S
@@ -40,6 +40,12 @@
 #endif
 #define STR1W_SHIFT	0
 
+#ifdef CONFIG_USE_LDRDSTRD_OVER_LDMSTM
+/* Enforce destination cache line alignment */
+#undef CALGN
+#define CALGN(x...) x
+#endif
+
 	.macro ldr1w ptr reg abort
 	ldrusr	\reg, \ptr, 4, abort=\abort
 	.endm
@@ -64,7 +70,14 @@
 	.endm
 
 	.macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
-	stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+#ifdef CONFIG_USE_LDRDSTRD_OVER_LDMSTM
+	strd	\reg1, \reg2, [\ptr], #8
+	strd	\reg3, \reg4, [\ptr], #8
+	strd	\reg5, \reg6, [\ptr], #8
+	strd	\reg7, \reg8, [\ptr], #8
+#else
+	stmia	\ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+#endif
 	.endm
 
 	.macro str1b ptr reg cond=al abort
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index f6f42c3330..6a9823d51f 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -63,6 +63,9 @@
  *	Correction to be applied to the "ip" register when branching into
  *	the ldr1w or str1w instructions (some of these macros may expand to
  *	more than one 32bit instruction in Thumb-2)
+ *
+ * Note: ldr8w is the only accessor that is allowed to change the
+ * condition code. 
  */
 
 
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index a83bc04365..11534edea1 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -45,7 +45,16 @@
 	.endm
 
 	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
-	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+#ifdef CONFIG_USE_LDRDSTRD_OVER_LDMSTM
+	tst	\ptr, #7
+	ldreqd	\reg1, \reg2, [\ptr], #8
+	ldreqd	\reg3, \reg4, [\ptr], #8
+	ldreqd	\reg5, \reg6, [\ptr], #8
+	ldreqd	\reg7, \reg8, [\ptr], #8
+	ldmneia	\ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+#else
+	ldmia	\ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+#endif
 	.endm
 
 	.macro ldr1b ptr reg cond=al abort
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index adbccc6e2d..db49a300c8 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -16,12 +16,27 @@
 #define LDR1W_SHIFT	0
 #define STR1W_SHIFT	0
 
+#ifdef CONFIG_USE_LDRDSTRD_OVER_LDMSTM
+/* Enforce destination cache line alignment */
+#undef CALGN
+#define CALGN(x...) x
+#endif
+
 	.macro ldr1w ptr reg abort
 	W(ldr) \reg, [\ptr], #4
 	.endm
 
 	.macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
-	ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+#ifdef CONFIG_USE_LDRDSTRD_OVER_LDMSTM
+	tst	\ptr, #7
+	ldreqd	\reg1, \reg2, [\ptr], #8
+	ldreqd	\reg3, \reg4, [\ptr], #8
+	ldreqd	\reg5, \reg6, [\ptr], #8
+	ldreqd	\reg7, \reg8, [\ptr], #8
+	ldmneia	\ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+#else
+	ldmia	\ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+#endif
 	.endm
 
 	.macro ldr1b ptr reg cond=al abort
@@ -33,7 +48,14 @@
 	.endm
 
 	.macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
-	stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+#ifdef CONFIG_USE_LDRDSTRD_OVER_LDMSTM
+	strd	\reg1, \reg2, [\ptr], #8
+	strd	\reg3, \reg4, [\ptr], #8
+	strd	\reg5, \reg6, [\ptr], #8
+	strd	\reg7, \reg8, [\ptr], #8
+#else
+	stmia	\ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
+#endif
 	.endm
 
 	.macro str1b ptr reg cond=al abort
-- 
1.7.9.rc2



From olof at lixom.net  Thu Mar 29 00:58:07 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 28 Mar 2012 21:58:07 -0700
Subject: [PATCH v2 1/4] ARM: OMAP1: boards: Fix OMAP_GPIO_IRQ usage with
 gpio_to_irq()
In-Reply-To: <1332158817-26311-2-git-send-email-tarun.kanti@ti.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
 <1332158817-26311-2-git-send-email-tarun.kanti@ti.com>
Message-ID: <CAOesGMg0eZAGdnU4A6Ubbyrn-zZAK4xvBVqoPkhhVReoHTAfaQ@mail.gmail.com>

Hi,

Sorry for the slow reply, I noticed this when dealing with merge
conflicts pulling in this patch and others from Tony.

On Mon, Mar 19, 2012 at 5:06 AM, Tarun Kanti DebBarma
<tarun.kanti at ti.com> wrote:
> With dynamic allocation of IRQ the usage of OMAP_GPIO_IRQ
> is no longer valid. We should be using gpio_to_irq() instead.
>
> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> ---
> ?arch/arm/mach-omap1/board-h2.c ? ? ? ?| ? ?8 ++++----
> ?arch/arm/mach-omap1/board-h3.c ? ? ? ?| ? ?9 ++++-----
> ?arch/arm/mach-omap1/board-htcherald.c | ? ?6 +++---
> ?arch/arm/mach-omap1/board-innovator.c | ? ?4 ++--
> ?arch/arm/mach-omap1/board-nokia770.c ?| ? ?2 +-
> ?arch/arm/mach-omap1/board-osk.c ? ? ? | ? 12 ++++++------
> ?arch/arm/mach-omap1/board-palmte.c ? ?| ? ?2 +-
> ?arch/arm/mach-omap1/board-palmtt.c ? ?| ? ?2 +-
> ?arch/arm/mach-omap1/board-palmz71.c ? | ? ?2 +-
> ?arch/arm/mach-omap1/board-voiceblue.c | ? 16 +++++++---------
> ?10 files changed, 30 insertions(+), 33 deletions(-)
>
> diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
> index 00ad6b2..ad0eece 100644
> --- a/arch/arm/mach-omap1/board-h2.c
> +++ b/arch/arm/mach-omap1/board-h2.c
> @@ -244,8 +244,6 @@ static struct resource h2_smc91x_resources[] = {
> ? ? ? ? ? ? ? ?.flags ?= IORESOURCE_MEM,
> ? ? ? ?},
> ? ? ? ?[1] = {
> - ? ? ? ? ? ? ? .start ?= OMAP_GPIO_IRQ(0),
> - ? ? ? ? ? ? ? .end ? ?= OMAP_GPIO_IRQ(0),
> ? ? ? ? ? ? ? ?.flags ?= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
> ? ? ? ?},
> ?};
> @@ -364,11 +362,9 @@ static struct tps65010_board tps_board = {
> ?static struct i2c_board_info __initdata h2_i2c_board_info[] = {
> ? ? ? ?{
> ? ? ? ? ? ? ? ?I2C_BOARD_INFO("tps65010", 0x48),
> - ? ? ? ? ? ? ? .irq ? ? ? ? ? ?= OMAP_GPIO_IRQ(58),
> ? ? ? ? ? ? ? ?.platform_data ?= &tps_board,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?I2C_BOARD_INFO("isp1301_omap", 0x2d),
> - ? ? ? ? ? ? ? .irq ? ? ? ? ? ?= OMAP_GPIO_IRQ(2),
> ? ? ? ?},
> ?};
>
> @@ -437,10 +433,14 @@ static void __init h2_init(void)
> ? ? ? ?omap_cfg_reg(E19_1610_KBR4);
> ? ? ? ?omap_cfg_reg(N19_1610_KBR5);
>
> + ? ? ? h2_devices[2]->resource[1].start = gpio_to_irq(0);
> + ? ? ? h2_devices[2]->resource[1].end = gpio_to_irq(0);

Never, ever, ever do this. What happens here when someone else adds
another device to the h2_devices array before the smc91x one?  Booom.
Extremely fragile code.

There's already a named resource struct you can use for this
(h2_smc91x_resources). Use it.

Same comments go for the other locations in this file as well as the
other OMAP2+ patch, where appropriate.

-Olof


From olof at lixom.net  Thu Mar 29 01:01:23 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 28 Mar 2012 22:01:23 -0700
Subject: [GIT PULL] omap fixes for merge window
In-Reply-To: <20120321180536.GK9859@atomide.com>
References: <20120321180536.GK9859@atomide.com>
Message-ID: <CAOesGMiKc5Tc2e5X9=gSiFS87JtMWGmmtOLSStWJcO7ayoE6Rg@mail.gmail.com>

Hi Tony,

On Wed, Mar 21, 2012 at 11:05 AM, Tony Lindgren <tony at atomide.com> wrote:
> Hi Arnd & Olof,
>
> Here's a set of fixes that would be nice to get merged during
> the merge window before the GPIO changes get merged to avoid
> boot issues on many omap boards.
>
> The changes queued in the GPIO tree require getting rid of
> OMAP_GPIO_IRQ and use gpio_to_irq() instead. This is needed for
> dynamically allocated GPIO interrupt ranges.

Sorry for the slow response on this, we've been focused on getting the
main pulls going in. I'm about to start a fixes branch now and looked
at this pull request.

I replied to one of the original patches in this branch, they need to
be fixed before they can go in:

http://marc.info/?l=linux-omap&m=133299716528617&w=2

Also, that way we can get a clean branch based on current mainline
without merge conflicts.


-Olof


From tarun.kanti at ti.com  Thu Mar 29 01:34:40 2012
From: tarun.kanti at ti.com (DebBarma, Tarun Kanti)
Date: Thu, 29 Mar 2012 11:04:40 +0530
Subject: [PATCH v2 1/4] ARM: OMAP1: boards: Fix OMAP_GPIO_IRQ usage with
 gpio_to_irq()
In-Reply-To: <CAOesGMg0eZAGdnU4A6Ubbyrn-zZAK4xvBVqoPkhhVReoHTAfaQ@mail.gmail.com>
References: <1332158817-26311-1-git-send-email-tarun.kanti@ti.com>
 <1332158817-26311-2-git-send-email-tarun.kanti@ti.com>
 <CAOesGMg0eZAGdnU4A6Ubbyrn-zZAK4xvBVqoPkhhVReoHTAfaQ@mail.gmail.com>
Message-ID: <CAC83ZvK9eSutCywynvzJRfz0jH-fCATrLH09_Y-G1+hnggfYmQ@mail.gmail.com>

On Thu, Mar 29, 2012 at 10:28 AM, Olof Johansson <olof at lixom.net> wrote:
> Hi,
>
> Sorry for the slow reply, I noticed this when dealing with merge
> conflicts pulling in this patch and others from Tony.
>
> On Mon, Mar 19, 2012 at 5:06 AM, Tarun Kanti DebBarma
> <tarun.kanti at ti.com> wrote:
>> With dynamic allocation of IRQ the usage of OMAP_GPIO_IRQ
>> is no longer valid. We should be using gpio_to_irq() instead.
>>
>> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
>> ---
>> ?arch/arm/mach-omap1/board-h2.c ? ? ? ?| ? ?8 ++++----
>> ?arch/arm/mach-omap1/board-h3.c ? ? ? ?| ? ?9 ++++-----
>> ?arch/arm/mach-omap1/board-htcherald.c | ? ?6 +++---
>> ?arch/arm/mach-omap1/board-innovator.c | ? ?4 ++--
>> ?arch/arm/mach-omap1/board-nokia770.c ?| ? ?2 +-
>> ?arch/arm/mach-omap1/board-osk.c ? ? ? | ? 12 ++++++------
>> ?arch/arm/mach-omap1/board-palmte.c ? ?| ? ?2 +-
>> ?arch/arm/mach-omap1/board-palmtt.c ? ?| ? ?2 +-
>> ?arch/arm/mach-omap1/board-palmz71.c ? | ? ?2 +-
>> ?arch/arm/mach-omap1/board-voiceblue.c | ? 16 +++++++---------
>> ?10 files changed, 30 insertions(+), 33 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
>> index 00ad6b2..ad0eece 100644
>> --- a/arch/arm/mach-omap1/board-h2.c
>> +++ b/arch/arm/mach-omap1/board-h2.c
>> @@ -244,8 +244,6 @@ static struct resource h2_smc91x_resources[] = {
>> ? ? ? ? ? ? ? ?.flags ?= IORESOURCE_MEM,
>> ? ? ? ?},
>> ? ? ? ?[1] = {
>> - ? ? ? ? ? ? ? .start ?= OMAP_GPIO_IRQ(0),
>> - ? ? ? ? ? ? ? .end ? ?= OMAP_GPIO_IRQ(0),
>> ? ? ? ? ? ? ? ?.flags ?= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
>> ? ? ? ?},
>> ?};
>> @@ -364,11 +362,9 @@ static struct tps65010_board tps_board = {
>> ?static struct i2c_board_info __initdata h2_i2c_board_info[] = {
>> ? ? ? ?{
>> ? ? ? ? ? ? ? ?I2C_BOARD_INFO("tps65010", 0x48),
>> - ? ? ? ? ? ? ? .irq ? ? ? ? ? ?= OMAP_GPIO_IRQ(58),
>> ? ? ? ? ? ? ? ?.platform_data ?= &tps_board,
>> ? ? ? ?}, {
>> ? ? ? ? ? ? ? ?I2C_BOARD_INFO("isp1301_omap", 0x2d),
>> - ? ? ? ? ? ? ? .irq ? ? ? ? ? ?= OMAP_GPIO_IRQ(2),
>> ? ? ? ?},
>> ?};
>>
>> @@ -437,10 +433,14 @@ static void __init h2_init(void)
>> ? ? ? ?omap_cfg_reg(E19_1610_KBR4);
>> ? ? ? ?omap_cfg_reg(N19_1610_KBR5);
>>
>> + ? ? ? h2_devices[2]->resource[1].start = gpio_to_irq(0);
>> + ? ? ? h2_devices[2]->resource[1].end = gpio_to_irq(0);
>
> Never, ever, ever do this. What happens here when someone else adds
> another device to the h2_devices array before the smc91x one? ?Booom.
> Extremely fragile code.
Ok.

>
> There's already a named resource struct you can use for this
> (h2_smc91x_resources). Use it.
Sure, I will use this one.

>
> Same comments go for the other locations in this file as well as the
> other OMAP2+ patch, where appropriate.
Alright, I will make appropriate changes. Thanks.
--
Tarun

>
> -Olof


From shawn.guo at linaro.org  Thu Mar 29 01:56:06 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 29 Mar 2012 13:56:06 +0800
Subject: [PATCH] ASoC: sgtl5000: fix power on/off of MIC bias
In-Reply-To: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
References: <1332919833-9641-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120329055604.GB19506@S2101-09.ap.freescale.net>

On Wed, Mar 28, 2012 at 03:30:33PM +0800, Shawn Guo wrote:
> From: Lionel Xu <Lionel.Xu at freescale.com>
> 
> There is no sound in the recorded wav, to enable recording, the VAG
> should be powered up, and the mic bias resistor should be set up with
> proper value.
> 
> Signed-off-by: Lionel Xu <lionel.xu at freescale.com>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
> Cc: Zeng Zhaoming <zengzm.kernel at gmail.com>

Mark, I just send a patch authored by Zeng Zhaoming, which fixes the
problem in a more sensible way.  So please ignore this one.

-- 
Regards,
Shawn


From rnayak at ti.com  Thu Mar 29 02:12:34 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 29 Mar 2012 11:42:34 +0530
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used
 OMAP4 onwards
In-Reply-To: <79CD15C6BA57404B839C016229A409A83183E0CE@DBDE01.ent.ti.com>
References: <1332842311-12308-1-git-send-email-rnayak@ti.com>
 <79CD15C6BA57404B839C016229A409A83183E0CE@DBDE01.ent.ti.com>
Message-ID: <4F73FD52.60209@ti.com>

On Wednesday 28 March 2012 12:02 PM, Hiremath, Vaibhav wrote:
> On Tue, Mar 27, 2012 at 15:28:31, Nayak, Rajendra wrote:
>> Some functions like _omap4_disable_module() and _omap4_wait_target_disable()
>> are (will be) used on all OMAPs OMAP4 and beyond which support module level
>> control. Fix the error checks in these functions to return if called on
>> any platform pre OMAP4 (i.e OMAP2 and OMAP3) instead of checking for
>> !cpu_is_omap44xx(). This avoids having to update the error check with a
>> '&&  !cpu_is_omap54xx()' when OMAP5 is introduced and possibly similar updates
>> when further OMAP generations are added.
>>
>
> Let me add some flavor here :)
>
> AM33xx, which has module level control, but falls under OMAP3 family of
> devices. cpu_is_omap34xx() is true for AM33xx device and we have to add
> check in all these functions. And I am sure we will have many of such
> devices in the future.
>
> Can we use some flag based option here, instead of cpu_is_xxx() check?
>

The intent of this patch was to make the error handling uniform across
all modules control functions in hwmod, and it atleast addresses one
problem of having to update these checks every time a new OMAP gets
added.

The problem that you bring up with AM33xx is regardless of this patch
(you would still need to go update every !cpu_is_omap44xx() check)
and IMHO should be handled separately, with a flag like you are
suggesting or by some other means. If you already have patches on how
this can be done, you should go ahead and post them out.


From viresh.kumar at st.com  Thu Mar 29 02:39:02 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 29 Mar 2012 12:09:02 +0530
Subject: [PATCH V2 5/7] ARM: SPEAr3xx: Add device-tree support to SPEAr3xx
 architecture
In-Reply-To: <201203281227.32299.arnd@arndb.de>
References: <cover.1332926608.git.viresh.kumar@st.com>
 <f4ad79023c6155d4de7e87c3cd798aadd493454e.1332926608.git.viresh.kumar@st.com>
 <201203281227.32299.arnd@arndb.de>
Message-ID: <4F740386.2080509@st.com>

On 3/28/2012 5:57 PM, Arnd Bergmann wrote:

Hi Arnd,

Thanks for reviewing. :)

All comments accepted.

> Does spear310-evb really connect all seven serial ports?

Yes, since it was an evaluation board, it contained all of them.

>> +/* Following will create static virtual/physical mappings */
>> > +struct map_desc spear3xx_io_desc[] __initdata = {
>> > +	{
>> > +		.virtual	= VA_SPEAR3XX_ICM1_UART_BASE,
>> > +		.pfn		= __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
>> > +		.length		= SZ_4K,
>> > +		.type		= MT_DEVICE
>> > +	}, {
>> > +		.virtual	= VA_SPEAR3XX_ML1_VIC_BASE,
>> > +		.pfn		= __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
>> > +		.length		= SZ_4K,
>> > +		.type		= MT_DEVICE
>> > +	}, {
>> > +		.virtual	= VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
>> > +		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
>> > +		.length		= SZ_4K,
>> > +		.type		= MT_DEVICE
>> > +	}, {
>> > +		.virtual	= VA_SPEAR3XX_ICM3_MISC_REG_BASE,
>> > +		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
>> > +		.length		= SZ_4K,
>> > +		.type		= MT_DEVICE
>> > +	},
>> > +};
> Note: there no real reason to just map 4K pages here, or to compute the
> virtual addresses using the IO_ADDRESS macro. Using larger mappings mean
> you have more efficient TLB lookup for any I/O windows that are located
> closely together.

Agreed.

> I would actually write this something like
> struct map_desc spear3xx_io_desc[] __initdata = {
> 	{
> 		.virtual = 0xf0000000,
> 		.pfn	 = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
> 		.length	 = SZ_16M,
> 		.type	 = MT_DEVICE,
> 	}, {
> 		.virtual = 0xf1000000,
> 		.pfn	 = __phys_to_pfn(SPEAR3XX_ICM4_BASE),
> 		.length  = 3 * SZ_16M,
> 		.type	 = MT_DEVICE,
> 	}, {
> 		.virtual = 0xf4000000,
> 		.pfn	 = __phys_to_pfn(SPEAR3XX_ICM3_ML1_2_BASE),
> 		.length  = 2 * SZ_16M,
> 		.type	 = MT_DEVICE,
> 	}, {
> 		.virtual = 0xf6000000,
> 		.pfn	 = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
> 		.length  = SZ_16M,
> 		.type	 = MT_DEVICE,
> 	},
> };
> 
> This would cover almost all of your devices with just seven TLB entries,
> and ioremap can now find the right virtual addresses automatically.

But there are few concerns.
Firstly, i wasn't aware that ioremap will reuse these mappings.
I believed that it will create new mappings and this is what i
saw till 2-6.37. What will happen if iounmap is called?

Over that, board would not be using all the devices present in SoC. So,
we don't really need to map everything. And so above wouldn't be valid
there.

To avoid holes, that were created in my original mappings, i can pick your
idea of dropping IO_ADDRESS() in .virtual field and use tightly aligned
virtual address for all peripherals.

Like: UART - 4K - 0xf0000000 - 0xf0001000
      SPI - 4K -  0xf0001000 - 0xf0002000

      ...

-- 
viresh


From w.sang at pengutronix.de  Thu Mar 29 02:43:20 2012
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 29 Mar 2012 08:43:20 +0200
Subject: [PATCH V2 1/3] lib: add support for stmp-style devices
In-Reply-To: <4F73CCC6.6000001@freescale.com>
References: <1332368519-22660-1-git-send-email-w.sang@pengutronix.de>
 <1332368519-22660-2-git-send-email-w.sang@pengutronix.de>
 <4F73CCC6.6000001@freescale.com>
Message-ID: <20120329064320.GA20840@pengutronix.de>

Hi,

> >  include/linux/stmp_device.h |   20 +++++++++++
> IMHO, this header should be placed at include/linux/fsl/.

Hmm, one never knows if somewhen in the future some other vendor decides to do
do a device with this register layout. It is just a layout, not an IP core per
se. So, I'd prefer to leave it as is.

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From hdoyu at nvidia.com  Thu Mar 29 03:19:27 2012
From: hdoyu at nvidia.com (Hiroshi Doyu)
Date: Thu, 29 Mar 2012 10:19:27 +0300
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
Message-ID: <20120329101927.8ab6b1993475b7e16ae2258f@nvidia.com>

Hi Marek,

On Wed, 29 Feb 2012 16:04:22 +0100
Marek Szyprowski <m.szyprowski at samsung.com> wrote:

> This patch add a complete implementation of DMA-mapping API for
> devices that have IOMMU support. All DMA-mapping calls are supported.
> 
> This patch contains some of the code kindly provided by Krishna Reddy
> <vdumpa at nvidia.com> and Andrzej Pietrasiewicz <andrzej.p at samsung.com>
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
> ---
>  arch/arm/Kconfig                 |    8 +
>  arch/arm/include/asm/device.h    |    3 +
>  arch/arm/include/asm/dma-iommu.h |   34 ++
>  arch/arm/mm/dma-mapping.c        |  726 +++++++++++++++++++++++++++++++++++++-
>  arch/arm/mm/vmregion.h           |    2 +-
>  5 files changed, 758 insertions(+), 15 deletions(-)
>  create mode 100644 arch/arm/include/asm/dma-iommu.h
> 

<snip>

> +/*
> + * Map a part of the scatter-gather list into contiguous io address space
> + */
> +static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
> +                         size_t size, dma_addr_t *handle,
> +                         enum dma_data_direction dir)
> +{
> +       struct dma_iommu_mapping *mapping = dev->archdata.mapping;
> +       dma_addr_t iova, iova_base;
> +       int ret = 0;
> +       unsigned int count;
> +       struct scatterlist *s;
> +
> +       size = PAGE_ALIGN(size);
> +       *handle = ARM_DMA_ERROR;
> +
> +       iova_base = iova = __alloc_iova(mapping, size);
> +       if (iova == ARM_DMA_ERROR)
> +               return -ENOMEM;
> +
> +       for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s))
> +       {
> +               phys_addr_t phys = page_to_phys(sg_page(s));
> +               unsigned int len = PAGE_ALIGN(s->offset + s->length);
> +
> +               if (!arch_is_coherent())
> +                       __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
> +
> +               ret = iommu_map(mapping->domain, iova, phys, len, 0);
> +               if (ret < 0)
> +                       goto fail;
> +               count += len >> PAGE_SHIFT;
> +               iova += len;
> +       }
> +       *handle = iova_base;
> +
> +       return 0;
> +fail:
> +       iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
> +       __free_iova(mapping, iova_base, size);
> +       return ret;
> +}

Do we need to set dma_address as below?

>From e8bcc3cdac5375b5d7f5ac5b3f716a11c1008f38 Mon Sep 17 00:00:00 2001
From: Hiroshi DOYU <hdoyu at nvidia.com>
Date: Thu, 29 Mar 2012 09:59:04 +0300
Subject: [PATCH 1/1] ARM: dma-mapping: Fix dma_address in sglist

s->dma_address wasn't set at mapping.

Signed-off-by: Hiroshi DOYU <hdoyu at nvidia.com>
---
 arch/arm/mm/dma-mapping.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 3347c37..11a9d65 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1111,6 +1111,8 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
 		ret = iommu_map(mapping->domain, iova, phys, len, 0);
 		if (ret < 0)
 			goto fail;
+		s->dma_address = iova;
+
 		count += len >> PAGE_SHIFT;
 		iova += len;
 	}
-- 
1.7.5.4


From govindraj.raja at ti.com  Thu Mar 29 03:35:24 2012
From: govindraj.raja at ti.com (Raja, Govindraj)
Date: Thu, 29 Mar 2012 13:05:24 +0530
Subject: [PATCH 1/3] OMAP2+: UART: Remove cpu checks for populating errata
 flags
In-Reply-To: <4F733FC4.9010506@ti.com>
References: <1332325501-10467-1-git-send-email-govindraj.raja@ti.com>
 <1332325501-10467-2-git-send-email-govindraj.raja@ti.com>
 <4F722C63.9080900@ti.com>
 <CAMrsUdKfsoks4fB4GhrRcEur8niJsaWuYGE34+j5Bk6u2XiZQQ@mail.gmail.com>
 <4F733FC4.9010506@ti.com>
Message-ID: <CAMrsUdKAAcc=tnC_vGRosEsqUmJBVaDQ9T=n898+9n30QwsSag@mail.gmail.com>

On Wed, Mar 28, 2012 at 10:13 PM, Jon Hunter <jon-hunter at ti.com> wrote:
> Hi Govindraj,
>
>
> On 3/28/2012 6:09, Raja, Govindraj wrote:
>>
>> On Wed, Mar 28, 2012 at 2:38 AM, Jon Hunter<jon-hunter at ti.com> ?wrote:
>>>
>>> Hi Govindraj,
>>>
>>>

[...]

>>>> + ? ? ? u32 mvr, scheme;
>>>> + ? ? ? u16 revision, major, minor;
>>>> +
>>>> + ? ? ? mvr = serial_in(up, UART_OMAP_MVER);
>>>> +
>>>> + ? ? ? /* Check revision register scheme */
>>>> + ? ? ? scheme = mvr& ? ?(0x03<< ? ?30);
>>>> + ? ? ? scheme>>= 30;
>>>
>>>
>>>
>>> Minor nit-pick, why not ...
>>>
>>> ? ? ? ?scheme = mvr>> ?30;
>>>
>>
>> yes will correct it.
>
>
> Thinking some more, could be better to add some #defines for
> OMAP_MVR_VERSION_MASK/SHIFT here.
>

Yes sure.

>
>>>
>>>> + ? ? ? switch (scheme) {
>>>> + ? ? ? case 0: /* Legacy Scheme: OMAP2/3 */
>>>> + ? ? ? ? ? ? ? /* MINOR_REV[0:4], MAJOR_REV[4:7] */
>>>
>>>
>>>
>>> This scheme is also true from OMAP1 devices. Maybe we could include in
>>> the
>>> comment.
>>
>>
>> No omap1 from $SUBJECT also reason,
>>
>> mach-omap1/serial.c => ?8250.c
>> mach-omap2/serial.c => ?omap-serial.c
>
>
> Got it! Thanks.
>
>>>> + ? ? ? ? ? ? ? major = (mvr& ? ?0xf0)>> ? ?4;
>>>> + ? ? ? ? ? ? ? minor = (mvr& ? ?0x0f);
>>>>
>>>> + ? ? ? ? ? ? ? break;
>>>> + ? ? ? case 1:
>>>> + ? ? ? ? ? ? ? /* New Scheme: OMAP4+ */
>>>> + ? ? ? ? ? ? ? /* MINOR_REV[0:5], MAJOR_REV[8:10] */
>>>> + ? ? ? ? ? ? ? major = (mvr& ? ?0x7<< ? ?8)>> ? ?8;
>>>
>>>
>>>
>>> Nit-pick ...
>>>
>>> ? ? ? ?major = (mvr>> ?8)& ?0x7;
>>
>>
>> yes fine will correct this.
>
>
> May be we should add #defines here to for OMAP_UART_MVR1_MAJ_MASK/SHIFT,
> OMAP_UART_MVR1_MIN_MASK/SHIFT, OMAP_UART_MVR2_MAJ_MASK/SHIFT and
> OMAP_UART_MVR2_MIN_MASK/SHIFT.
>

okay will add this.

--
Thanks,
Govindraj.R


From alexg at meprolight.com  Thu Mar 29 03:51:32 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Thu, 29 Mar 2012 09:51:32 +0200
Subject: [PATCH] mfd: mc13xxx: add I2C support fix building for v3.4
In-Reply-To: <201203290747.50881.marc@cpdesign.com.au>
References: <1332943273-22447-1-git-send-email-alexg@meprolight.com>,
 <201203290747.50881.marc@cpdesign.com.au>
Message-ID: <4875438356E7CA4A8F2145FCD3E61C0B2CC34CAD28@MEP-EXCH.meprolight.com>


Hi Marc,

> @Alex, you seen keen to do this, so I'll leave it to you :)
> Otherwise, I'm happy to do it, just let me know.

No problem, I would gladly give it to you :-)

Regards,
Alex Gershgorin



From arnd at arndb.de  Thu Mar 29 03:53:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 29 Mar 2012 07:53:04 +0000
Subject: [PATCH V2 5/7] ARM: SPEAr3xx: Add device-tree support to SPEAr3xx
 architecture
In-Reply-To: <4F740386.2080509@st.com>
References: <cover.1332926608.git.viresh.kumar@st.com>
 <201203281227.32299.arnd@arndb.de> <4F740386.2080509@st.com>
Message-ID: <201203290753.04758.arnd@arndb.de>

On Thursday 29 March 2012, Viresh Kumar wrote:
> But there are few concerns.
> Firstly, i wasn't aware that ioremap will reuse these mappings.
> I believed that it will create new mappings and this is what i
> saw till 2-6.37. What will happen if iounmap is called?

Yes, it was a fairly recent change. iounmap on one of these areas
will do nothing.

> Over that, board would not be using all the devices present in SoC. So,
> we don't really need to map everything. And so above wouldn't be valid
> there.

That should not really be a concern, you only waste a little bit of
the vmalloc space that you gained recently when ioremap was changed.
Nothing should ever be able to get to those pointers other than by
calling ioremap, so it doesn't hurt to have them mapped, except for
the very unlikely scenario that you get a wild pointer dereference
in the kernel that would otherwise result in an oops.

> To avoid holes, that were created in my original mappings, i can pick your
> idea of dropping IO_ADDRESS() in .virtual field and use tightly aligned
> virtual address for all peripherals.
> 
> Like: UART - 4K - 0xf0000000 - 0xf0001000
>       SPI - 4K -  0xf0001000 - 0xf0002000

Well, if you use the 4k mappings here, you won't benefit from reduced
TLB pressure through section maps, although you still get rid of IO_ADDRESS.
I would not put any devices into the static mapping, other than those
you need to access before mm_init() or when you can actually use the section
mapping.

	Arnd


From m.szyprowski at samsung.com  Thu Mar 29 04:00:14 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Thu, 29 Mar 2012 10:00:14 +0200
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <20120329101927.8ab6b1993475b7e16ae2258f@nvidia.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <20120329101927.8ab6b1993475b7e16ae2258f@nvidia.com>
Message-ID: <01b301cd0d81$f935d750$eba185f0$%szyprowski@samsung.com>

Hello,

On Thursday, March 29, 2012 9:19 AM Hiroshi Doyu wrote:

> On Wed, 29 Feb 2012 16:04:22 +0100
> Marek Szyprowski <m.szyprowski at samsung.com> wrote:
> 
> > This patch add a complete implementation of DMA-mapping API for
> > devices that have IOMMU support. All DMA-mapping calls are supported.
> >
> > This patch contains some of the code kindly provided by Krishna Reddy
> > <vdumpa at nvidia.com> and Andrzej Pietrasiewicz <andrzej.p at samsung.com>
> >
> > Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk at oracle.com>
> > ---
> >  arch/arm/Kconfig                 |    8 +
> >  arch/arm/include/asm/device.h    |    3 +
> >  arch/arm/include/asm/dma-iommu.h |   34 ++
> >  arch/arm/mm/dma-mapping.c        |  726 +++++++++++++++++++++++++++++++++++++-
> >  arch/arm/mm/vmregion.h           |    2 +-
> >  5 files changed, 758 insertions(+), 15 deletions(-)
> >  create mode 100644 arch/arm/include/asm/dma-iommu.h
> >
> 
> <snip>
> 
> > +/*
> > + * Map a part of the scatter-gather list into contiguous io address space
> > + */
> > +static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
> > +                         size_t size, dma_addr_t *handle,
> > +                         enum dma_data_direction dir)
> > +{
> > +       struct dma_iommu_mapping *mapping = dev->archdata.mapping;
> > +       dma_addr_t iova, iova_base;
> > +       int ret = 0;
> > +       unsigned int count;
> > +       struct scatterlist *s;
> > +
> > +       size = PAGE_ALIGN(size);
> > +       *handle = ARM_DMA_ERROR;
> > +
> > +       iova_base = iova = __alloc_iova(mapping, size);
> > +       if (iova == ARM_DMA_ERROR)
> > +               return -ENOMEM;
> > +
> > +       for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s))
> > +       {
> > +               phys_addr_t phys = page_to_phys(sg_page(s));
> > +               unsigned int len = PAGE_ALIGN(s->offset + s->length);
> > +
> > +               if (!arch_is_coherent())
> > +                       __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
> > +
> > +               ret = iommu_map(mapping->domain, iova, phys, len, 0);
> > +               if (ret < 0)
> > +                       goto fail;
> > +               count += len >> PAGE_SHIFT;
> > +               iova += len;
> > +       }
> > +       *handle = iova_base;
> > +
> > +       return 0;
> > +fail:
> > +       iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
> > +       __free_iova(mapping, iova_base, size);
> > +       return ret;
> > +}
> 
> Do we need to set dma_address as below?

Nope, this one is not correct. Please check the arm_iommu_map_sg() function. It calls 
__map_sg_chunk() and gives it &dma->dma_address as one of the arguments, so the dma 
address is correctly stored in the scatter list. Please note that scatterlist is really
non-trivial structure and information about physical memory pages/chunks is disjoint 
from the information about dma address space chunks, although both are stored on the 
same list. In arm_iommu_map_sg() 's' pointer is used for physical memory chunks and 
'dma' pointer is used for dma address space chunks. 

The number of dma address space chunks (returned by arm_iommu_map_sq) can be lower 
than the number of physical memory chunks (given as nents argument).

In case of IOMMU you usually construct the scatter list in such a way, that you get
only one dma address chunk (so in fact you get a buffer mapped contiguously in 
virtual io address space).

> From e8bcc3cdac5375b5d7f5ac5b3f716a11c1008f38 Mon Sep 17 00:00:00 2001
> From: Hiroshi DOYU <hdoyu at nvidia.com>
> Date: Thu, 29 Mar 2012 09:59:04 +0300
> Subject: [PATCH 1/1] ARM: dma-mapping: Fix dma_address in sglist
> 
> s->dma_address wasn't set at mapping.
> 
> Signed-off-by: Hiroshi DOYU <hdoyu at nvidia.com>
> ---
>  arch/arm/mm/dma-mapping.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
> index 3347c37..11a9d65 100644
> --- a/arch/arm/mm/dma-mapping.c
> +++ b/arch/arm/mm/dma-mapping.c
> @@ -1111,6 +1111,8 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
>  		ret = iommu_map(mapping->domain, iova, phys, len, 0);
>  		if (ret < 0)
>  			goto fail;
> +		s->dma_address = iova;
> +
>  		count += len >> PAGE_SHIFT;
>  		iova += len;
>  	}

The above patch is not needed at all.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From prylowski at metasoft.pl  Thu Mar 29 04:10:15 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Thu, 29 Mar 2012 10:10:15 +0200
Subject: [PATCH 0/3] Add PATA host controller support for Cirrus Logic EP93xx
 CPU
Message-ID: <4F7418E7.4060500@metasoft.pl>

Hi.

The following patchset adds support for IDE interface controller found on
Cirrus Logic's EP931x CPUs. It is based on an earlier work done by
Alessandro Zummo, Lennert Buytenhek, Joao Ramos and Bartlomiej
Zolnierkiewicz. I tried to take the best parts of code from previous
attempts for inclusion and added dma support. The driver is working
correctly in both PIO and DMA mode (with exception that it could give
timeouts in DMA mode occasionally - the problem has been solved by me
and solution proposed to LAKML; it's not related to this driver, but
DMA/interrupt handling of ep93xx IMHO).

I'm not sure about correctness of the following in the driver:
- module copyrights/authorship - I just added all copyrights of the
  earlier drivers and MODULE_AUTHOR macro lists their authors,
- timeout in IORDY polling (how long to wait for IORDY?),
- GPIO/IDE pin muxing - I hope it's done in a way acceptable for
  ep93xx maintainers (patch 2/3). I would like for the driver to refuse
  loading when muxing is wrong (first commented out lines of
  ep93xx_pata_probe, patch 1/3), but some api is needed as raw access
  to SYSCON register is prohibited in drivers.

Patchset is against current mainline kernel.

Regards,
RP


[PATCH 1/3] PATA host controller driver for ep93xx
[PATCH 2/3] ep93xx: IDE driver platform support code
[PATCH 3/3] ep93xx: Add IDE support to edb93xx boards

 arch/arm/mach-ep93xx/core.c                  |   36
 arch/arm/mach-ep93xx/edb93xx.c               |   23
 arch/arm/mach-ep93xx/include/mach/platform.h |    1
 arch/arm/mach-ep93xx/soc.h                   |    1
 drivers/ata/Kconfig                          |    9
 drivers/ata/Makefile                         |    1
 drivers/ata/pata_ep93xx.c                    |  949 +++++++++++++++++
 7 files changed, 1020 insertions(+)


From prylowski at metasoft.pl  Thu Mar 29 04:17:53 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Thu, 29 Mar 2012 10:17:53 +0200
Subject: [PATCH 1/3] PATA host controller driver for ep93xx
In-Reply-To: <4F7418E7.4060500@metasoft.pl>
References: <4F7418E7.4060500@metasoft.pl>
Message-ID: <4F741AB1.4000107@metasoft.pl>

Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
Cc: Joao Ramos <joao.ramos at inov.pt>
Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
Cc: Ryan Mallon <ryan at bluewatersys.com>
Cc: Sergei Shtylyov <sshtylyov at ru.montavista.com>
Cc: Bartlomiej Zolnierkiewicz <bzolnier at gmail.com>

---
 drivers/ata/Kconfig       |    9
 drivers/ata/Makefile      |    1
 drivers/ata/pata_ep93xx.c |  949 ++++++++++++++++++++++++++++++++++++
 3 files changed, 959 insertions(+)

Index: linux-2.6/drivers/ata/pata_ep93xx.c
===================================================================
--- /dev/null
+++ linux-2.6/drivers/ata/pata_ep93xx.c
@@ -0,0 +1,949 @@
+/*
+ * EP93XX PATA controller driver.
+ *
+ * Copyright (c) 2012, Metasoft s.c.
+ *	Rafal Prylowski <prylowski at metasoft.pl>
+ *
+ * Based on pata_scc.c, pata_icside.c and on earlier version of EP93XX
+ * PATA driver by Lennert Buytenhek and Alessandro Zummo.
+ * Read/Write timings, resource management and other improvements
+ * from driver by Joao Ramos and Bartlomiej Zolnierkiewicz.
+ * DMA engine support based on spi-ep93xx.c by Mika Westerberg.
+ *
+ * Original copyrights:
+ *
+ * Support for Cirrus Logic's EP93xx (EP9312, EP9315) CPUs
+ * PATA host controller driver.
+ *
+ * Copyright (c) 2009, Bartlomiej Zolnierkiewicz
+ *
+ * Heavily based on the ep93xx-ide.c driver:
+ *
+ * Copyright (c) 2009, Joao Ramos <joao.ramos at inov.pt>
+ *		      INESC Inovacao (INOV)
+ *
+ * EP93XX PATA controller driver.
+ * Copyright (C) 2007 Lennert Buytenhek <buytenh at wantstofly.org>
+ *
+ * An ATA driver for the Cirrus Logic EP93xx PATA controller.
+ *
+ * Based on an earlier version by Alessandro Zummo, which is:
+ *   Copyright (C) 2006 Tower Technologies
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <scsi/scsi_host.h>
+#include <linux/ata.h>
+#include <linux/libata.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+
+#include <mach/dma.h>
+#include <asm/mach-types.h>
+#include <mach/ep93xx-regs.h>
+#include <mach/platform.h>
+
+#define DRV_NAME	"ep93xx-ide"
+#define DRV_VERSION	"1.0"
+
+enum {
+	/* IDE Control Register */
+	IDECtrl				= 0x00,
+	IDECtrl_CS0n			= (1 << 0),
+	IDECtrl_CS1n			= (1 << 1),
+	IDECtrl_DIORn			= (1 << 5),
+	IDECtrl_DIOWn			= (1 << 6),
+	IDECtrl_INTRQ			= (1 << 9),
+	IDECtrl_IORDY			= (1 << 10),
+
+	/* IDE Configuration Register */
+	IDECfg				= 0x04,
+	IDECfg_IDEEN			= (1 << 0),
+	IDECfg_PIO			= (1 << 1),
+	IDECfg_MDMA			= (1 << 2),
+	IDECfg_UDMA			= (1 << 3),
+	IDECfg_MODE_SHIFT		= 4,
+	IDECfg_MODE_MASK		= (0xf << 4),
+	IDECfg_WST_SHIFT		= 8,
+	IDECfg_WST_MASK			= (0x3 << 8),
+
+	/* MDMA Operation Register */
+	IDEMDMAOp			= 0x08,
+
+	/* UDMA Operation Register */
+	IDEUDMAOp			= 0x0c,
+	IDEUDMAOp_UEN			= (1 << 0),
+	IDEUDMAOp_RWOP			= (1 << 1),
+
+	/* PIO/MDMA/UDMA Data Registers */
+	IDEDataOut			= 0x10,
+	IDEDataIn			= 0x14,
+	IDEMDMADataOut			= 0x18,
+	IDEMDMADataIn			= 0x1c,
+	IDEUDMADataOut			= 0x20,
+	IDEUDMADataIn			= 0x24,
+
+	/* UDMA Status Register */
+	IDEUDMASts			= 0x28,
+	IDEUDMASts_DMAide		= (1 << 16),
+	IDEUDMASts_INTide		= (1 << 17),
+	IDEUDMASts_SBUSY		= (1 << 18),
+	IDEUDMASts_NDO			= (1 << 24),
+	IDEUDMASts_NDI			= (1 << 25),
+	IDEUDMASts_N4X			= (1 << 26),
+
+	/* UDMA Debug Status Register */
+	IDEUDMADebug			= 0x2c,
+};
+
+struct ep93xx_pata_data /* private_data in ata_host */
+{
+	void __iomem *ide_base;
+	const struct ata_timing *t, *cmd_t;
+	bool iordy;
+
+	unsigned long udma_in_phys;
+	unsigned long udma_out_phys;
+
+	struct dma_chan *dma_rx_channel;
+	struct ep93xx_dma_data dma_rx_data;
+	struct dma_chan *dma_tx_channel;
+	struct ep93xx_dma_data dma_tx_data;
+};
+
+static void ep93xx_pata_clear_regs(void __iomem *base)
+{
+	writel(IDECtrl_CS0n | IDECtrl_CS1n | IDECtrl_DIORn |
+		IDECtrl_DIOWn, base + IDECtrl);
+
+	writel(0, base + IDECfg);
+	writel(0, base + IDEMDMAOp);
+	writel(0, base + IDEUDMAOp);
+	writel(0, base + IDEDataOut);
+	writel(0, base + IDEDataIn);
+	writel(0, base + IDEMDMADataOut);
+	writel(0, base + IDEMDMADataIn);
+	writel(0, base + IDEUDMADataOut);
+	writel(0, base + IDEUDMADataIn);
+	writel(0, base + IDEUDMADebug);
+}
+
+static inline int ep93xx_pata_check_iordy(void __iomem *base)
+{
+	return (readl(base + IDECtrl) & IDECtrl_IORDY) ? 1 : 0;
+}
+
+/*
+ * According to EP93xx User's Guide, WST field of IDECfg specifies number
+ * of HCLK cycles to hold the data bus after a PIO write operation.
+ * It should be programmed to guarantee following delays:
+ *
+ * PIO Mode   [ns]
+ * 0          30
+ * 1          20
+ * 2          15
+ * 3          10
+ * 4          5
+ *
+ * Maximum possible value for HCLK is 100MHz.
+ */
+static inline int ep93xx_pata_get_wst(int pio_mode)
+{
+	return (pio_mode == 0 ? 3 : pio_mode < 3 ? 2 : 1)
+		<< IDECfg_WST_SHIFT;
+}
+
+static inline void ep93xx_pata_enable_pio(void __iomem *base, int pio_mode)
+{
+	writel(IDECfg_IDEEN | IDECfg_PIO |
+		ep93xx_pata_get_wst(pio_mode) |
+		(pio_mode << IDECfg_MODE_SHIFT), base + IDECfg);
+}
+
+static u16 ep93xx_pata_read(struct ep93xx_pata_data *drv_data,
+			    void *addr_io,
+			    const struct ata_timing *t)
+{
+	unsigned long addr = (unsigned long) addr_io & 0x1f;
+	void __iomem *base = drv_data->ide_base;
+	u16 ret;
+
+	writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
+	ndelay(t->setup);
+	writel(IDECtrl_DIOWn | addr, base + IDECtrl);
+	ndelay(t->act8b);
+	if (drv_data->iordy) {
+		/* min. 1s timeout (at cpu cycle = 5ns) */
+		unsigned int timeout = 200000;
+		while (!ep93xx_pata_check_iordy(base) && --timeout)
+			cpu_relax();
+	}
+	/*
+	 * The IDEDataIn register is loaded from the DD pins at the positive
+	 * edge of the DIORn signal. (EP93xx UG p27-14)
+	 */
+	writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
+	ret = readl(base + IDEDataIn);
+	ndelay(t->cyc8b - t->act8b - t->setup);
+	return ret;
+}
+
+static void ep93xx_pata_write(struct ep93xx_pata_data *drv_data,
+			      u16 value, void *addr_io,
+			      const struct ata_timing *t)
+{
+	unsigned long addr = (unsigned long) addr_io & 0x1f;
+	void __iomem *base = drv_data->ide_base;
+
+	writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
+	ndelay(t->setup);
+	/*
+	 * Value from IDEDataOut register is driven onto the DD pins when
+	 * DIOWn is low. (EP93xx UG p27-13)
+	 */
+	writel(value, base + IDEDataOut);
+	writel(IDECtrl_DIORn | addr, base + IDECtrl);
+	ndelay(t->act8b);
+	if (drv_data->iordy) {
+		/* min. 1s timeout */
+		unsigned int timeout = 200000;
+		while (!ep93xx_pata_check_iordy(base) && --timeout)
+			cpu_relax();
+	}
+	writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
+	ndelay(t->cyc8b - t->act8b - t->setup);
+}
+
+static void ep93xx_pata_set_piomode(struct ata_port *ap,
+				    struct ata_device *adev)
+{
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	struct ata_device *pair = ata_dev_pair(adev);
+
+	drv_data->t = ata_timing_find_mode(adev->pio_mode);
+	drv_data->cmd_t = drv_data->t;
+	drv_data->iordy = ata_pio_need_iordy(adev);
+
+	if (pair && pair->pio_mode < adev->pio_mode)
+		drv_data->cmd_t = ata_timing_find_mode(pair->pio_mode);
+
+	ep93xx_pata_enable_pio(drv_data->ide_base,
+			       adev->pio_mode - XFER_PIO_0);
+}
+
+static u8 ep93xx_pata_check_status(struct ata_port *ap)
+{
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	return ep93xx_pata_read(drv_data, ap->ioaddr.status_addr,
+				drv_data->cmd_t);
+}
+
+static u8 ep93xx_pata_check_altstatus(struct ata_port *ap)
+{
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	return ep93xx_pata_read(drv_data, ap->ioaddr.altstatus_addr,
+				drv_data->cmd_t);
+}
+
+static void ep93xx_pata_tf_load(struct ata_port *ap,
+				const struct ata_taskfile *tf)
+{
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	const struct ata_timing *t = drv_data->cmd_t;
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
+
+	if (tf->ctl != ap->last_ctl) {
+		ep93xx_pata_write(drv_data, tf->ctl, ioaddr->ctl_addr, t);
+		ap->last_ctl = tf->ctl;
+		ata_wait_idle(ap);
+	}
+
+	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
+		ep93xx_pata_write(drv_data, tf->hob_feature,
+			ioaddr->feature_addr, t);
+		ep93xx_pata_write(drv_data, tf->hob_nsect,
+			ioaddr->nsect_addr, t);
+		ep93xx_pata_write(drv_data, tf->hob_lbal,
+			ioaddr->lbal_addr, t);
+		ep93xx_pata_write(drv_data, tf->hob_lbam,
+			ioaddr->lbam_addr, t);
+		ep93xx_pata_write(drv_data, tf->hob_lbah,
+			ioaddr->lbah_addr, t);
+		VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
+			tf->hob_feature, tf->hob_nsect, tf->hob_lbal,
+			tf->hob_lbam, tf->hob_lbah);
+	}
+
+	if (is_addr) {
+		ep93xx_pata_write(drv_data, tf->feature,
+			ioaddr->feature_addr, t);
+		ep93xx_pata_write(drv_data, tf->nsect, ioaddr->nsect_addr, t);
+		ep93xx_pata_write(drv_data, tf->lbal, ioaddr->lbal_addr, t);
+		ep93xx_pata_write(drv_data, tf->lbam, ioaddr->lbam_addr, t);
+		ep93xx_pata_write(drv_data, tf->lbah, ioaddr->lbah_addr, t);
+		VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
+			tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
+	}
+
+	if (tf->flags & ATA_TFLAG_DEVICE) {
+		ep93xx_pata_write(drv_data, tf->device, ioaddr->device_addr, t);
+		VPRINTK("device 0x%X\n", tf->device);
+	}
+
+	ata_wait_idle(ap);
+}
+
+static void ep93xx_pata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
+{
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	const struct ata_timing *t = drv_data->cmd_t;
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+
+	tf->command = ep93xx_pata_check_status(ap);
+	tf->feature = ep93xx_pata_read(drv_data, ioaddr->feature_addr, t);
+	tf->nsect = ep93xx_pata_read(drv_data, ioaddr->nsect_addr, t);
+	tf->lbal = ep93xx_pata_read(drv_data, ioaddr->lbal_addr, t);
+	tf->lbam = ep93xx_pata_read(drv_data, ioaddr->lbam_addr, t);
+	tf->lbah = ep93xx_pata_read(drv_data, ioaddr->lbah_addr, t);
+	tf->device = ep93xx_pata_read(drv_data, ioaddr->device_addr, t);
+
+	if (tf->flags & ATA_TFLAG_LBA48) {
+		ep93xx_pata_write(drv_data, tf->ctl | ATA_HOB,
+			ioaddr->ctl_addr, t);
+		tf->hob_feature = ep93xx_pata_read(drv_data,
+			ioaddr->feature_addr, t);
+		tf->hob_nsect = ep93xx_pata_read(drv_data,
+			ioaddr->nsect_addr, t);
+		tf->hob_lbal = ep93xx_pata_read(drv_data,
+			ioaddr->lbal_addr, t);
+		tf->hob_lbam = ep93xx_pata_read(drv_data,
+			ioaddr->lbam_addr, t);
+		tf->hob_lbah = ep93xx_pata_read(drv_data,
+			ioaddr->lbah_addr, t);
+		ep93xx_pata_write(drv_data, tf->ctl, ioaddr->ctl_addr, t);
+		ap->last_ctl = tf->ctl;
+	}
+}
+
+static void ep93xx_pata_exec_command(struct ata_port *ap,
+				     const struct ata_taskfile *tf)
+{
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
+
+	ep93xx_pata_write(drv_data, tf->command,
+			  ap->ioaddr.command_addr, drv_data->cmd_t);
+	ata_sff_pause(ap);
+}
+
+static void ep93xx_pata_dev_select(struct ata_port *ap, unsigned int device)
+{
+	u8 tmp;
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+
+	if (device == 0)
+		tmp = ATA_DEVICE_OBS;
+	else
+		tmp = ATA_DEVICE_OBS | ATA_DEV1;
+
+	ep93xx_pata_write(drv_data, tmp, ap->ioaddr.device_addr,
+			  drv_data->cmd_t);
+	ata_sff_pause(ap);	/* needed; also flushes, for mmio */
+}
+
+static void ep93xx_pata_set_devctl(struct ata_port *ap, u8 ctl)
+{
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	ep93xx_pata_write(drv_data, ctl, ap->ioaddr.ctl_addr,
+			  drv_data->cmd_t);
+}
+
+unsigned int ep93xx_pata_data_xfer(struct ata_device *adev, unsigned char *buf,
+				   unsigned int buflen, int rw)
+{
+	struct ata_port *ap = adev->link->ap;
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	const struct ata_timing *t = drv_data->t;
+	void *data_addr = ap->ioaddr.data_addr;
+	u16 *data = (u16 *) buf;
+	unsigned int words = buflen >> 1;
+
+	/* Transfer multiple of 2 bytes */
+	if (rw == READ)
+		while (words--)
+			*data++ = cpu_to_le16(
+				ep93xx_pata_read(drv_data, data_addr, t));
+	else
+		while (words--)
+			ep93xx_pata_write(drv_data, le16_to_cpu(*data++),
+				data_addr, t);
+
+	/* Transfer trailing 1 byte, if any. */
+	if (unlikely(buflen & 0x01)) {
+		unsigned char pad[2] = { };
+
+		buf += buflen - 1;
+
+		if (rw == READ) {
+			*pad = cpu_to_le16(
+				ep93xx_pata_read(drv_data, data_addr, t));
+			*buf = pad[0];
+		} else {
+			pad[0] = *buf;
+			ep93xx_pata_write(drv_data, le16_to_cpu(*pad),
+					  data_addr, t);
+		}
+		words++;
+	}
+
+	return words << 1;
+}
+
+static unsigned int ep93xx_pata_dev_check(struct ata_port *ap,
+					  unsigned int device)
+{
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	const struct ata_timing *t = drv_data->cmd_t;
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	u8 nsect, lbal;
+
+	ap->ops->sff_dev_select(ap, device);
+
+	ep93xx_pata_write(drv_data, 0x55, ioaddr->nsect_addr, t);
+	ep93xx_pata_write(drv_data, 0xaa, ioaddr->lbal_addr, t);
+
+	ep93xx_pata_write(drv_data, 0xaa, ioaddr->nsect_addr, t);
+	ep93xx_pata_write(drv_data, 0x55, ioaddr->lbal_addr, t);
+
+	ep93xx_pata_write(drv_data, 0x55, ioaddr->nsect_addr, t);
+	ep93xx_pata_write(drv_data, 0xaa, ioaddr->lbal_addr, t);
+
+	nsect = ep93xx_pata_read(drv_data, ioaddr->nsect_addr, t);
+	lbal = ep93xx_pata_read(drv_data, ioaddr->lbal_addr, t);
+
+	if ((nsect == 0x55) && (lbal == 0xaa))
+		return 1;	/* we found a device */
+
+	return 0;		/* nothing found */
+}
+
+int ep93xx_pata_wait_after_reset(struct ata_link *link, unsigned int devmask,
+				 unsigned long deadline)
+{
+	struct ata_port *ap = link->ap;
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	const struct ata_timing *t = drv_data->cmd_t;
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	unsigned int dev0 = devmask & (1 << 0);
+	unsigned int dev1 = devmask & (1 << 1);
+	int rc, ret = 0;
+
+	ata_msleep(ap, ATA_WAIT_AFTER_RESET);
+
+	/* always check readiness of the master device */
+	rc = ata_sff_wait_ready(link, deadline);
+	/* -ENODEV means the odd clown forgot the D7 pulldown resistor
+	 * and TF status is 0xff, bail out on it too.
+	 */
+	if (rc)
+		return rc;
+
+	/* if device 1 was found in ata_devchk, wait for register
+	 * access briefly, then wait for BSY to clear.
+	 */
+	if (dev1) {
+		int i;
+
+		ap->ops->sff_dev_select(ap, 1);
+
+		/* Wait for register access.  Some ATAPI devices fail
+		 * to set nsect/lbal after reset, so don't waste too
+		 * much time on it.  We're gonna wait for !BSY anyway.
+		 */
+		for (i = 0; i < 2; i++) {
+			u8 nsect, lbal;
+
+			nsect = ep93xx_pata_read(drv_data,
+				ioaddr->nsect_addr, t);
+			lbal = ep93xx_pata_read(drv_data,
+				ioaddr->lbal_addr, t);
+			if (nsect == 1 && lbal == 1)
+				break;
+			msleep(50);	/* give drive a breather */
+		}
+
+		rc = ata_sff_wait_ready(link, deadline);
+		if (rc) {
+			if (rc != -ENODEV)
+				return rc;
+			ret = rc;
+		}
+	}
+	/* is all this really necessary? */
+	ap->ops->sff_dev_select(ap, 0);
+	if (dev1)
+		ap->ops->sff_dev_select(ap, 1);
+	if (dev0)
+		ap->ops->sff_dev_select(ap, 0);
+
+	return ret;
+}
+
+static int ep93xx_pata_bus_softreset(struct ata_port *ap, unsigned int devmask,
+				     unsigned long deadline)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	const struct ata_timing *t = drv_data->cmd_t;
+
+	DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
+
+	ep93xx_pata_write(drv_data, ap->ctl, ioaddr->ctl_addr, t);
+	udelay(20);		/* FIXME: flush */
+	ep93xx_pata_write(drv_data, ap->ctl | ATA_SRST, ioaddr->ctl_addr, t);
+	udelay(20);		/* FIXME: flush */
+	ep93xx_pata_write(drv_data, ap->ctl, ioaddr->ctl_addr, t);
+	ap->last_ctl = ap->ctl;
+
+	return ep93xx_pata_wait_after_reset(&ap->link, devmask, deadline);
+}
+
+static bool ep93xx_pata_dma_filter(struct dma_chan *chan, void *filter_param)
+{
+	if (ep93xx_dma_chan_is_m2p(chan))
+		return false;
+
+	chan->private = filter_param;
+	return true;
+}
+
+static int ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
+{
+	dma_cap_mask_t mask;
+
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	/*
+	 * Request two channels for IDE. Another possibility would be
+	 * to request only one channel, and reprogram it's direction at
+	 * start of new transfer.
+	 */
+	drv_data->dma_rx_data.port = EP93XX_DMA_IDE;
+	drv_data->dma_rx_data.direction = DMA_FROM_DEVICE;
+	drv_data->dma_rx_data.name = "ep93xx-pata-rx";
+	drv_data->dma_tx_data.port = EP93XX_DMA_IDE;
+	drv_data->dma_tx_data.direction = DMA_TO_DEVICE;
+	drv_data->dma_tx_data.name = "ep93xx-pata-tx";
+	drv_data->dma_rx_channel = dma_request_channel(mask,
+		ep93xx_pata_dma_filter, &drv_data->dma_rx_data);
+	drv_data->dma_tx_channel = dma_request_channel(mask,
+		ep93xx_pata_dma_filter, &drv_data->dma_tx_data);
+	return drv_data->dma_rx_channel && drv_data->dma_tx_channel;
+}
+
+static void ep93xx_pata_dma_start(struct ata_queued_cmd *qc)
+{
+	struct dma_async_tx_descriptor *txd;
+	struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
+	void __iomem *base = drv_data->ide_base;
+	struct ata_device *adev = qc->dev;
+	u32 v = qc->dma_dir == DMA_TO_DEVICE ? IDEUDMAOp_RWOP : 0;
+	struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE
+		? drv_data->dma_tx_channel : drv_data->dma_rx_channel;
+
+	txd = channel->device->device_prep_slave_sg(channel, qc->sg,
+		 qc->n_elem, qc->dma_dir, DMA_CTRL_ACK);
+	if (!txd) {
+		dev_err(qc->ap->dev, "failed to prepare slave for sg dma\n");
+		BUG();
+	}
+	txd->callback = NULL;
+	txd->callback_param = NULL;
+
+	if (dmaengine_submit(txd) < 0) {
+		dev_err(qc->ap->dev, "failed to submit dma transfer\n");
+		BUG();
+	}
+	dma_async_issue_pending(channel);
+
+	/*
+	 * When enabling UDMA operation, IDEUDMAOp register needs to be
+	 * programmed in three step sequence:
+	 * 1) set or clear the RWOP bit,
+	 * 2) perform dummy read of the register,
+	 * 3) set the UEN bit.
+	 */
+	writel(v, base + IDEUDMAOp);
+	readl(base + IDEUDMAOp);
+	writel(v | IDEUDMAOp_UEN, base + IDEUDMAOp);
+
+	writel(IDECfg_IDEEN | IDECfg_UDMA |
+		((adev->xfer_mode - XFER_UDMA_0) << IDECfg_MODE_SHIFT),
+		base + IDECfg);
+}
+
+static void ep93xx_pata_dma_stop(struct ata_queued_cmd *qc)
+{
+	struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
+	void __iomem *base = drv_data->ide_base;
+
+	/* terminate all dma transfers, if not yet finished */
+	dmaengine_terminate_all(drv_data->dma_rx_channel);
+	dmaengine_terminate_all(drv_data->dma_tx_channel);
+
+	/*
+	 * To properly stop IDE-DMA, IDEUDMAOp register must to be cleared
+	 * and IDECtrl register must be set to default value.
+	 */
+	writel(0, base + IDEUDMAOp);
+	writel(readl(base + IDECtrl) | IDECtrl_DIOWn | IDECtrl_DIORn |
+		IDECtrl_CS0n | IDECtrl_CS1n, base + IDECtrl);
+
+	ep93xx_pata_enable_pio(drv_data->ide_base,
+		qc->dev->pio_mode - XFER_PIO_0);
+
+	ata_sff_dma_pause(qc->ap);
+}
+
+static void ep93xx_pata_dma_setup(struct ata_queued_cmd *qc)
+{
+	struct dma_slave_config conf;
+	struct ata_port *ap = qc->ap;
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE
+		? drv_data->dma_tx_channel : drv_data->dma_rx_channel;
+
+	memset(&conf, 0, sizeof(conf));
+	conf.direction = qc->dma_dir;
+	if (qc->dma_dir == DMA_FROM_DEVICE) {
+		conf.src_addr = drv_data->udma_in_phys;
+		conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	} else {
+		conf.dst_addr = drv_data->udma_out_phys;
+		conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	}
+	if (dmaengine_slave_config(channel, &conf)) {
+		dev_err(qc->ap->dev, "failed to configure slave for sg dma\n");
+		BUG();
+	}
+
+	ap->ops->sff_exec_command(ap, &qc->tf);
+}
+
+static u8 ep93xx_pata_dma_status(struct ata_port *ap)
+{
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+	u32 val = readl(drv_data->ide_base + IDEUDMASts);
+
+	/*
+	 * UDMA Status Register bits:
+	 *
+	 * DMAide - DMA request signal from UDMA state machine,
+	 * INTide - INT line generated by UDMA because of errors in the
+	 *          state machine,
+	 * SBUSY - UDMA state machine busy, not in idle state,
+	 * NDO   - error for data-out not completed,
+	 * NDI   - error for data-in not completed,
+	 * N4X   - error for data transferred not multiplies of four
+	 *         32-bit words.
+	 * (EP93xx UG p27-17)
+	 */
+	if (val & IDEUDMASts_NDO || val & IDEUDMASts_NDI ||
+	    val & IDEUDMASts_N4X || val & IDEUDMASts_INTide)
+		return ATA_DMA_ERR;
+
+	/* read INTRQ (INT[3]) pin input state */
+	if (readl(drv_data->ide_base + IDECtrl) & IDECtrl_INTRQ)
+		return ATA_DMA_INTR;
+
+	if (val & IDEUDMASts_SBUSY || val & IDEUDMASts_DMAide)
+		return ATA_DMA_ACTIVE;
+
+	return 0;
+}
+
+static int ep93xx_pata_softreset(struct ata_link *al, unsigned int *classes,
+				 unsigned long deadline)
+{
+	struct ata_port *ap = al->ap;
+	unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
+	unsigned int devmask = 0;
+	int rc;
+	u8 err;
+
+	DPRINTK("ENTER\n");
+
+	/* determine if device 0/1 are present */
+	if (ep93xx_pata_dev_check(ap, 0))
+		devmask |= (1 << 0);
+	if (slave_possible && ep93xx_pata_dev_check(ap, 1))
+		devmask |= (1 << 1);
+
+	/* select device 0 again */
+	ap->ops->sff_dev_select(al->ap, 0);
+
+	/* issue bus reset */
+	DPRINTK("about to softreset, devmask=%x\n", devmask);
+	rc = ep93xx_pata_bus_softreset(ap, devmask, deadline);
+	/* if link is ocuppied, -ENODEV too is an error */
+	if (rc && (rc != -ENODEV || sata_scr_valid(al))) {
+		ata_link_printk(al, KERN_ERR, "SRST failed (errno=%d)\n",
+				rc);
+		return rc;
+	}
+
+	/* determine by signature whether we have ATA or ATAPI devices */
+	classes[0] = ata_sff_dev_classify(&al->device[0], devmask & (1 << 0),
+					  &err);
+	if (slave_possible && err != 0x81)
+		classes[1] = ata_sff_dev_classify(&al->device[1],
+						  devmask & (1 << 1), &err);
+
+	DPRINTK("EXIT, classes[0]=%u, [1]=%u\n", classes[0],
+		classes[1]);
+	return 0;
+}
+
+void ep93xx_pata_drain_fifo(struct ata_queued_cmd *qc)
+{
+	int count;
+	struct ata_port *ap;
+	struct ep93xx_pata_data *drv_data;
+
+	/* We only need to flush incoming data when a command was running */
+	if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
+		return;
+
+	ap = qc->ap;
+	drv_data = ap->host->private_data;
+	/* Drain up to 64K of data before we give up this recovery method */
+	for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
+		     && count < 65536; count += 2)
+		ep93xx_pata_read(drv_data, ap->ioaddr.data_addr,
+				 drv_data->cmd_t);
+
+	/* Can become DEBUG later */
+	if (count)
+		ata_port_printk(ap, KERN_DEBUG,
+				"drained %d bytes to clear DRQ.\n", count);
+
+}
+
+static int ep93xx_pata_port_start(struct ata_port *ap)
+{
+	struct ep93xx_pata_data *drv_data = ap->host->private_data;
+
+	drv_data->cmd_t = ata_timing_find_mode(XFER_PIO_0);
+	return 0;
+}
+
+static struct scsi_host_template ep93xx_pata_sht = {
+	ATA_BASE_SHT(DRV_NAME),
+	/* ep93xx dma implementation limit */
+	.sg_tablesize		= 32,
+	/* ep93xx dma can't transfer 65536 bytes at once */
+	.dma_boundary		= 0x7fff,
+};
+
+static struct ata_port_operations ep93xx_pata_port_ops = {
+	.inherits		= &ata_bmdma_port_ops,
+
+	.qc_prep		= ata_noop_qc_prep,
+
+	.softreset		= ep93xx_pata_softreset,
+	.hardreset		= ATA_OP_NULL,
+
+	.sff_dev_select		= ep93xx_pata_dev_select,
+	.sff_set_devctl		= ep93xx_pata_set_devctl,
+	.sff_check_status	= ep93xx_pata_check_status,
+	.sff_check_altstatus	= ep93xx_pata_check_altstatus,
+	.sff_tf_load		= ep93xx_pata_tf_load,
+	.sff_tf_read		= ep93xx_pata_tf_read,
+	.sff_exec_command	= ep93xx_pata_exec_command,
+	.sff_data_xfer		= ep93xx_pata_data_xfer,
+	.sff_drain_fifo		= ep93xx_pata_drain_fifo,
+	.sff_irq_clear		= ATA_OP_NULL,
+
+	.set_piomode		= ep93xx_pata_set_piomode,
+
+	.bmdma_setup		= ep93xx_pata_dma_setup,
+	.bmdma_start		= ep93xx_pata_dma_start,
+	.bmdma_stop		= ep93xx_pata_dma_stop,
+	.bmdma_status		= ep93xx_pata_dma_status,
+
+	.cable_detect		= ata_cable_unknown,
+	.port_start		= ep93xx_pata_port_start,
+};
+
+static void ep93xx_pata_setup_port(struct ata_ioports *ioaddr)
+{
+	/*
+	 * the device IDE register to be accessed is selected through
+	 * IDECTRL register's specific bitfields 'DA', 'CS1n' and 'CS0n':
+	 *   b4   b3   b2    b1     b0
+	 *   A2   A1   A0   CS1n   CS0n
+	 * the values filled in this structure allows the value to be directly
+	 * ORed to the IDECTRL register, hence giving directly the A[2:0] and
+	 * CS1n/CS0n values for each IDE register.
+	 * The values correspond to the transformation:
+	 *   ((real IDE address) << 2) | CS1n value << 1 | CS0n value
+	 */
+	ioaddr->cmd_addr	= (void __iomem *) 0 + 2; /* CS1 */
+
+	ioaddr->data_addr	= (void __iomem *) (ATA_REG_DATA << 2) + 2;
+	ioaddr->error_addr	= (void __iomem *) (ATA_REG_ERR << 2) + 2;
+	ioaddr->feature_addr	= (void __iomem *) (ATA_REG_FEATURE << 2) + 2;
+	ioaddr->nsect_addr	= (void __iomem *) (ATA_REG_NSECT << 2) + 2;
+	ioaddr->lbal_addr	= (void __iomem *) (ATA_REG_LBAL << 2) + 2;
+	ioaddr->lbam_addr	= (void __iomem *) (ATA_REG_LBAM << 2) + 2;
+	ioaddr->lbah_addr	= (void __iomem *) (ATA_REG_LBAH << 2) + 2;
+	ioaddr->device_addr	= (void __iomem *) (ATA_REG_DEVICE << 2) + 2;
+	ioaddr->status_addr	= (void __iomem *) (ATA_REG_STATUS << 2) + 2;
+	ioaddr->command_addr	= (void __iomem *) (ATA_REG_CMD << 2) + 2;
+
+	ioaddr->altstatus_addr	= (void __iomem *) (0x06 << 2) + 1; /* CS0 */
+	ioaddr->ctl_addr	= (void __iomem *) (0x06 << 2) + 1; /* CS0 */
+}
+
+static int __devinit ep93xx_pata_probe(struct platform_device *pdev)
+{
+	struct ep93xx_pata_data *drv_data;
+	struct ata_host *host;
+	struct ata_port *ap;
+	unsigned int irq;
+	struct resource *mem_res;
+	void __iomem *ide_base;
+
+	/*if (readl(EP93XX_SYSCON_DEVCFG) & (EP93XX_SYSCON_DEVCFG_EONIDE
+		| EP93XX_SYSCON_DEVCFG_GONIDE | EP93XX_SYSCON_DEVCFG_HONIDE)) {
+		dev_err(&pdev->dev, "IDE/GPIO pin conflict\n");
+		return -EINVAL;
+	}*/
+
+	/* INT[3] (IRQ_EP93XX_EXT3) line connected as pull down */
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "IRQ allocation failed\n");
+		return -ENXIO;
+	}
+
+	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem_res) {
+		dev_err(&pdev->dev, "resources allocation failed\n");
+		return -ENXIO;
+	}
+
+	ide_base = devm_request_and_ioremap(&pdev->dev, mem_res);
+	if (!ide_base) {
+		dev_err(&pdev->dev, "memory region request/map failed\n");
+		return -ENOMEM;
+	}
+
+	drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
+	if (!drv_data) {
+		dev_err(&pdev->dev, "unable to allocate memory\n");
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, drv_data);
+	drv_data->ide_base = ide_base;
+	drv_data->udma_in_phys = mem_res->start + IDEUDMADataIn;
+	drv_data->udma_out_phys = mem_res->start + IDEUDMADataOut;
+	ep93xx_pata_dma_init(drv_data);
+
+	/* allocate host */
+	host = ata_host_alloc(&pdev->dev, 1);
+	if (!host) {
+		dev_err(&pdev->dev, "ata_host_alloc() failed\n");
+		return -ENOMEM;
+	}
+
+	ep93xx_pata_clear_regs(ide_base);
+
+	host->n_ports = 1;
+	host->private_data = drv_data;
+
+	ap = host->ports[0];
+	ap->dev = &pdev->dev;
+	ap->ops = &ep93xx_pata_port_ops;
+	ap->flags |= ATA_FLAG_SLAVE_POSS;
+	ap->pio_mask = ATA_PIO4;
+	/*
+	 * Maximum UDMA modes:
+	 * EP931x rev.E0 - UDMA2
+	 * EP931x rev.E1 - UDMA3
+	 * EP931x rev.E2 - UDMA4
+	 *
+	 * MWDMA support was removed from EP931x rev.E2,
+	 * so this driver supports only UDMA modes.
+	 */
+	if (drv_data->dma_rx_channel && drv_data->dma_tx_channel) {
+		int chip_rev = ep93xx_chip_revision();
+		if (chip_rev == EP93XX_CHIP_REV_E1)
+			ap->udma_mask = ATA_UDMA3;
+		else if (chip_rev == EP93XX_CHIP_REV_E2)
+			ap->udma_mask = ATA_UDMA4;
+		else
+			ap->udma_mask = ATA_UDMA2;
+	}
+
+	ep93xx_pata_setup_port(&ap->ioaddr);
+
+	/* defaults, pio 0 */
+	ep93xx_pata_enable_pio(ide_base, 0);
+
+	dev_info(&pdev->dev, "version " DRV_VERSION "\n");
+
+	/* activate host */
+	return ata_host_activate(host, irq, ata_bmdma_interrupt, 0,
+		&ep93xx_pata_sht);
+}
+
+static int __devexit ep93xx_pata_remove(struct platform_device *pdev)
+{
+	struct ata_host *host = platform_get_drvdata(pdev);
+	struct ep93xx_pata_data *drv_data = host->private_data;
+
+	ata_host_detach(host);
+	if (drv_data->dma_rx_channel)
+		dma_release_channel(drv_data->dma_rx_channel);
+	if (drv_data->dma_tx_channel)
+		dma_release_channel(drv_data->dma_tx_channel);
+	ep93xx_pata_clear_regs(drv_data->ide_base);
+	return 0;
+}
+
+static struct platform_driver ep93xx_pata_platform_driver = {
+	.driver = {
+		.name = DRV_NAME,
+		.owner = THIS_MODULE,
+	},
+	.probe = ep93xx_pata_probe,
+	.remove = __devexit_p(ep93xx_pata_remove),
+};
+
+static int __init ep93xx_pata_init(void)
+{
+	return platform_driver_register(&ep93xx_pata_platform_driver);
+}
+
+static void __exit ep93xx_pata_exit(void)
+{
+	platform_driver_unregister(&ep93xx_pata_platform_driver);
+}
+
+module_init(ep93xx_pata_init);
+module_exit(ep93xx_pata_exit);
+
+MODULE_AUTHOR("Alessandro Zummo, Lennert Buytenhek, Joao Ramos, "
+		"Bartlomiej Zolnierkiewicz, Rafal Prylowski");
+MODULE_DESCRIPTION("low-level driver for cirrus ep93xx IDE controller");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+MODULE_ALIAS("platform:pata_ep93xx");
Index: linux-2.6/drivers/ata/Kconfig
===================================================================
--- linux-2.6.orig/drivers/ata/Kconfig
+++ linux-2.6/drivers/ata/Kconfig
@@ -416,6 +416,15 @@ config PATA_EFAR
 
 	  If unsure, say N.
 
+config PATA_EP93XX
+	tristate "Cirrus Logic EP93xx PATA support"
+	depends on ARCH_EP93XX
+	help
+	  This option enables support for the PATA controller in
+	  the Cirrus Logic EP9312 and EP9315 ARM CPU.
+
+	  If unsure, say N.
+
 config PATA_HPT366
 	tristate "HPT 366/368 PATA support"
 	depends on PCI
Index: linux-2.6/drivers/ata/Makefile
===================================================================
--- linux-2.6.orig/drivers/ata/Makefile
+++ linux-2.6/drivers/ata/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_PATA_CS5535)	+= pata_cs5535
 obj-$(CONFIG_PATA_CS5536)	+= pata_cs5536.o
 obj-$(CONFIG_PATA_CYPRESS)	+= pata_cypress.o
 obj-$(CONFIG_PATA_EFAR)		+= pata_efar.o
+obj-$(CONFIG_PATA_EP93XX)	+= pata_ep93xx.o
 obj-$(CONFIG_PATA_HPT366)	+= pata_hpt366.o
 obj-$(CONFIG_PATA_HPT37X)	+= pata_hpt37x.o
 obj-$(CONFIG_PATA_HPT3X2N)	+= pata_hpt3x2n.o


From prylowski at metasoft.pl  Thu Mar 29 04:19:19 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Thu, 29 Mar 2012 10:19:19 +0200
Subject: [PATCH 2/3] ep93xx: IDE driver platform support code
In-Reply-To: <4F7418E7.4060500@metasoft.pl>
References: <4F7418E7.4060500@metasoft.pl>
Message-ID: <4F741B07.7040107@metasoft.pl>

Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
Cc: Ryan Mallon <ryan at bluewatersys.com>

---
 arch/arm/mach-ep93xx/core.c                  |   36 +++++++++++++++++
 arch/arm/mach-ep93xx/include/mach/platform.h |    1
 arch/arm/mach-ep93xx/soc.h                   |    1
 3 files changed, 38 insertions(+)

Index: linux-2.6/arch/arm/mach-ep93xx/soc.h
===================================================================
--- linux-2.6.orig/arch/arm/mach-ep93xx/soc.h
+++ linux-2.6/arch/arm/mach-ep93xx/soc.h
@@ -69,6 +69,7 @@
 
 #define EP93XX_BOOT_ROM_BASE		EP93XX_AHB_IOMEM(0x00090000)
 
+#define EP93XX_IDE_PHYS_BASE		EP93XX_AHB_PHYS(0x000a0000)
 #define EP93XX_IDE_BASE			EP93XX_AHB_IOMEM(0x000a0000)
 
 #define EP93XX_VIC1_BASE		EP93XX_AHB_IOMEM(0x000b0000)
Index: linux-2.6/arch/arm/mach-ep93xx/core.c
===================================================================
--- linux-2.6.orig/arch/arm/mach-ep93xx/core.c
+++ linux-2.6/arch/arm/mach-ep93xx/core.c
@@ -868,6 +868,42 @@ static struct platform_device ep93xx_wdt
 	.resource	= ep93xx_wdt_resources,
 };
 
+/*************************************************************************
+ * EP93xx IDE
+ *************************************************************************/
+static struct resource ep93xx_ide_resources[] = {
+	[0] = {
+		.start	= EP93XX_IDE_PHYS_BASE,
+		.end	= EP93XX_IDE_PHYS_BASE + 0xffff,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_EP93XX_EXT3,
+		.end	= IRQ_EP93XX_EXT3,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ep93xx_ide_device = {
+	.name		= "ep93xx-ide",
+	.id		= -1,
+	.dev		= {
+		.dma_mask		= &ep93xx_ide_device.dev.coherent_dma_mask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+	.num_resources	= ARRAY_SIZE(ep93xx_ide_resources),
+	.resource	= ep93xx_ide_resources,
+};
+
+void __init ep93xx_register_ide(void)
+{
+	/* GPIO ports E, G and H used by IDE */
+	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
+				 EP93XX_SYSCON_DEVCFG_GONIDE |
+				 EP93XX_SYSCON_DEVCFG_HONIDE);
+	platform_device_register(&ep93xx_ide_device);
+}
+
 void __init ep93xx_init_devices(void)
 {
 	/* Disallow access to MaverickCrunch initially */
Index: linux-2.6/arch/arm/mach-ep93xx/include/mach/platform.h
===================================================================
--- linux-2.6.orig/arch/arm/mach-ep93xx/include/mach/platform.h
+++ linux-2.6/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -48,6 +48,7 @@ void ep93xx_register_i2s(void);
 int ep93xx_i2s_acquire(void);
 void ep93xx_i2s_release(void);
 void ep93xx_register_ac97(void);
+void ep93xx_register_ide(void);
 
 void ep93xx_init_devices(void);
 extern struct sys_timer ep93xx_timer;


From alexg at meprolight.com  Thu Mar 29 04:12:45 2012
From: alexg at meprolight.com (Alex Gershgorin)
Date: Thu, 29 Mar 2012 10:12:45 +0200
Subject: [PATCH v3] ARM: regulator: i.MX35-PDK Add regulator support
Message-ID: <1333008765-26114-1-git-send-email-alexg@meprolight.com>

Signed-off-by: Alex Gershgorin <alexg at meprolight.com>
---
Applies to v3.4

Changes since v2:
 * Renaming dev_name from "1-000a" to "0-000a"
---
 arch/arm/mach-imx/mach-mx35_3ds.c |  193 +++++++++++++++++++++++++++++++++++++
 1 files changed, 193 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index e14291d..9247a79 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -34,6 +34,8 @@
 #include <linux/usb/otg.h>
 
 #include <linux/mtd/physmap.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -253,6 +255,8 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
 	MX35_PAD_CSI_MCLK__IPU_CSI_MCLK,
 	MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK,
 	MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC,
+	/*PMIC IRQ*/
+	MX35_PAD_GPIO2_0__GPIO2_0,
 };
 
 /*
@@ -317,6 +321,193 @@ static struct platform_device mx35_3ds_ov2640 = {
 	},
 };
 
+static struct regulator_consumer_supply sw1_consumers[] = {
+	{
+		.supply = "cpu_vcc",
+	}
+};
+
+static struct regulator_consumer_supply vcam_consumers[] = {
+	/* sgtl5000 */
+	REGULATOR_SUPPLY("VDDA", "0-000a"),
+};
+
+static struct regulator_consumer_supply vaudio_consumers[] = {
+	REGULATOR_SUPPLY("cmos_vio", "soc-camera-pdrv.0"),
+};
+
+static struct regulator_init_data sw1_init = {
+	.constraints = {
+		.name = "SW1",
+		.min_uV = 600000,
+		.max_uV = 1375000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.valid_modes_mask = 0,
+		.always_on = 1,
+		.boot_on = 1,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+	.consumer_supplies = sw1_consumers,
+};
+
+static struct regulator_init_data sw2_init = {
+	.constraints = {
+		.name = "SW2",
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data sw3_init = {
+	.constraints = {
+		.name = "SW3",
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data sw4_init = {
+	.constraints = {
+		.name = "SW4",
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data viohi_init = {
+	.constraints = {
+		.name = "VIOHI",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vusb_init = {
+	.constraints = {
+		.name = "VUSB",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vdig_init = {
+	.constraints = {
+		.name = "VDIG",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vpll_init = {
+	.constraints = {
+		.name = "VPLL",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vusb2_init = {
+	.constraints = {
+		.name = "VUSB2",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vvideo_init = {
+	.constraints = {
+		.name = "VVIDEO",
+		.boot_on = 1
+	}
+};
+
+static struct regulator_init_data vaudio_init = {
+	.constraints = {
+		.name = "VAUDIO",
+		.min_uV = 2300000,
+		.max_uV = 3000000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1
+	},
+	.num_consumer_supplies = ARRAY_SIZE(vaudio_consumers),
+	.consumer_supplies = vaudio_consumers,
+};
+
+static struct regulator_init_data vcam_init = {
+	.constraints = {
+		.name = "VCAM",
+		.min_uV = 2500000,
+		.max_uV = 3000000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+					REGULATOR_CHANGE_MODE,
+		.valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
+		.boot_on = 1
+	},
+	.num_consumer_supplies = ARRAY_SIZE(vcam_consumers),
+	.consumer_supplies = vcam_consumers,
+};
+
+static struct regulator_init_data vgen1_init = {
+	.constraints = {
+		.name = "VGEN1",
+	}
+};
+
+static struct regulator_init_data vgen2_init = {
+	.constraints = {
+		.name = "VGEN2",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vgen3_init = {
+	.constraints = {
+		.name = "VGEN3",
+	}
+};
+
+static struct mc13xxx_regulator_init_data mx35_3ds_regulators[] = {
+	{ .id = MC13892_SW1, .init_data = &sw1_init },
+	{ .id = MC13892_SW2, .init_data = &sw2_init },
+	{ .id = MC13892_SW3, .init_data = &sw3_init },
+	{ .id = MC13892_SW4, .init_data = &sw4_init },
+	{ .id = MC13892_VIOHI, .init_data = &viohi_init },
+	{ .id = MC13892_VPLL, .init_data = &vpll_init },
+	{ .id = MC13892_VDIG, .init_data = &vdig_init },
+	{ .id = MC13892_VUSB2, .init_data = &vusb2_init },
+	{ .id = MC13892_VVIDEO, .init_data = &vvideo_init },
+	{ .id = MC13892_VAUDIO, .init_data = &vaudio_init },
+	{ .id = MC13892_VCAM, .init_data = &vcam_init },
+	{ .id = MC13892_VGEN1, .init_data = &vgen1_init },
+	{ .id = MC13892_VGEN2, .init_data = &vgen2_init },
+	{ .id = MC13892_VGEN3, .init_data = &vgen3_init },
+	{ .id = MC13892_VUSB, .init_data = &vusb_init },
+};
+
+static struct mc13xxx_platform_data mx35_3ds_mc13892_data = {
+	.flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
+	.regulators = {
+		.num_regulators = ARRAY_SIZE(mx35_3ds_regulators),
+		.regulators = mx35_3ds_regulators,
+	},
+};
+
+#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
+
+static struct i2c_board_info mx35_3ds_i2c_mc13892 = {
+
+	I2C_BOARD_INFO("mc13892", 0x08),
+	.platform_data = &mx35_3ds_mc13892_data,
+	.irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
+};
+
+static void __init imx35_3ds_init_mc13892(void)
+{
+	int ret = gpio_request_one(GPIO_PMIC_INT, GPIOF_DIR_IN, "pmic irq");
+
+	if (ret) {
+		pr_err("failed to get pmic irq: %d\n", ret);
+		return;
+	}
+
+	i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1);
+}
+
 static int mx35_3ds_otg_init(struct platform_device *pdev)
 {
 	return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
@@ -412,6 +603,8 @@ static void __init mx35_3ds_init(void)
 	imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 	mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
 	platform_device_register(&mx35_3ds_lcd);
+
+	imx35_3ds_init_mc13892();
 }
 
 static void __init mx35pdk_timer_init(void)
-- 
1.7.0.4



From prylowski at metasoft.pl  Thu Mar 29 04:20:15 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Thu, 29 Mar 2012 10:20:15 +0200
Subject: [PATCH 3/3] ep93xx: Add IDE support to edb93xx boards
In-Reply-To: <4F7418E7.4060500@metasoft.pl>
References: <4F7418E7.4060500@metasoft.pl>
Message-ID: <4F741B3F.4000507@metasoft.pl>

Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
Cc: Ryan Mallon <ryan at bluewatersys.com>

---
 arch/arm/mach-ep93xx/edb93xx.c |   23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Index: linux-2.6/arch/arm/mach-ep93xx/edb93xx.c
===================================================================
--- linux-2.6.orig/arch/arm/mach-ep93xx/edb93xx.c
+++ linux-2.6/arch/arm/mach-ep93xx/edb93xx.c
@@ -233,6 +233,28 @@ static void __init edb93xx_register_fb(v
 }
 
 
+/*************************************************************************
+ * EDB93xx IDE
+ *************************************************************************/
+static int __init edb93xx_has_ide(void)
+{
+	/*
+	 * Although EDB9312 and EDB9315 do have IDE capability, they have
+	 * INTRQ line wired as pull-up, which makes using IDE interface
+	 * problematic.
+	 */
+	return machine_is_edb9315a();
+}
+
+static void __init edb93xx_register_ide(void)
+{
+	if (!edb93xx_has_ide())
+		return;
+
+	ep93xx_register_ide();
+}
+
+
 static void __init edb93xx_init_machine(void)
 {
 	ep93xx_init_devices();
@@ -243,6 +265,7 @@ static void __init edb93xx_init_machine(
 	edb93xx_register_i2s();
 	edb93xx_register_pwm();
 	edb93xx_register_fb();
+	edb93xx_register_ide();
 }
 
 


From hvaibhav at ti.com  Thu Mar 29 04:56:11 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Thu, 29 Mar 2012 08:56:11 +0000
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used
 OMAP4 onwards
In-Reply-To: <4F73FD52.60209@ti.com>
References: <1332842311-12308-1-git-send-email-rnayak@ti.com>
 <79CD15C6BA57404B839C016229A409A83183E0CE@DBDE01.ent.ti.com>
 <4F73FD52.60209@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83183FB9F@DBDE01.ent.ti.com>

On Thu, Mar 29, 2012 at 11:42:34, Nayak, Rajendra wrote:
> On Wednesday 28 March 2012 12:02 PM, Hiremath, Vaibhav wrote:
> > On Tue, Mar 27, 2012 at 15:28:31, Nayak, Rajendra wrote:
> >> Some functions like _omap4_disable_module() and _omap4_wait_target_disable()
> >> are (will be) used on all OMAPs OMAP4 and beyond which support module level
> >> control. Fix the error checks in these functions to return if called on
> >> any platform pre OMAP4 (i.e OMAP2 and OMAP3) instead of checking for
> >> !cpu_is_omap44xx(). This avoids having to update the error check with a
> >> '&&  !cpu_is_omap54xx()' when OMAP5 is introduced and possibly similar updates
> >> when further OMAP generations are added.
> >>
> >
> > Let me add some flavor here :)
> >
> > AM33xx, which has module level control, but falls under OMAP3 family of
> > devices. cpu_is_omap34xx() is true for AM33xx device and we have to add
> > check in all these functions. And I am sure we will have many of such
> > devices in the future.
> >
> > Can we use some flag based option here, instead of cpu_is_xxx() check?
> >
> 
> The intent of this patch was to make the error handling uniform across
> all modules control functions in hwmod, and it atleast addresses one
> problem of having to update these checks every time a new OMAP gets
> added.
> 
> The problem that you bring up with AM33xx is regardless of this patch
> (you would still need to go update every !cpu_is_omap44xx() check)

Indeed, in any of cpu_is_xxx() check implementation, I have to add check
for cpu_is_am33xx().

The point I was trying to make here was, cpu_is_xxx() check will become ugly,
as more and more devices gets added to the list, am33xx being the first one 
in omap34xx family.

> and IMHO should be handled separately, with a flag like you are
> suggesting or by some other means. If you already have patches on how
> this can be done, you should go ahead and post them out.
> 

Nope.

But I can work on it, once I finish my AM33xx baseport submission.

Thanks,
Vaibhav



From rnayak at ti.com  Thu Mar 29 05:02:34 2012
From: rnayak at ti.com (Rajendra Nayak)
Date: Thu, 29 Mar 2012 14:32:34 +0530
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used
 OMAP4 onwards
In-Reply-To: <79CD15C6BA57404B839C016229A409A83183FB9F@DBDE01.ent.ti.com>
References: <1332842311-12308-1-git-send-email-rnayak@ti.com>
 <79CD15C6BA57404B839C016229A409A83183E0CE@DBDE01.ent.ti.com>
 <4F73FD52.60209@ti.com>
 <79CD15C6BA57404B839C016229A409A83183FB9F@DBDE01.ent.ti.com>
Message-ID: <4F74252A.7060809@ti.com>

On Thursday 29 March 2012 02:26 PM, Hiremath, Vaibhav wrote:
> The point I was trying to make here was, cpu_is_xxx() check will become ugly,
> as more and more devices gets added to the list, am33xx being the first one
> in omap34xx family.

So are there more, other than AM33xx which are cortex A8 based but
share the OMAP4 PRCM IP block?


From hvaibhav at ti.com  Thu Mar 29 05:14:19 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Thu, 29 Mar 2012 09:14:19 +0000
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used
 OMAP4 onwards
In-Reply-To: <4F74252A.7060809@ti.com>
References: <1332842311-12308-1-git-send-email-rnayak@ti.com>
 <79CD15C6BA57404B839C016229A409A83183E0CE@DBDE01.ent.ti.com>
 <4F73FD52.60209@ti.com>
 <79CD15C6BA57404B839C016229A409A83183FB9F@DBDE01.ent.ti.com>
 <4F74252A.7060809@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A83183FC32@DBDE01.ent.ti.com>

On Thu, Mar 29, 2012 at 14:32:34, Nayak, Rajendra wrote:
> On Thursday 29 March 2012 02:26 PM, Hiremath, Vaibhav wrote:
> > The point I was trying to make here was, cpu_is_xxx() check will become ugly,
> > as more and more devices gets added to the list, am33xx being the first one
> > in omap34xx family.
> 
> So are there more, other than AM33xx which are cortex A8 based but
> share the OMAP4 PRCM IP block?
> 

I would say, probably yes. 

But, things are so dynamic and you never know how things will shape up by 
the time you freeze the design.

Thanks,
Vaibhav



From cxie4 at marvell.com  Thu Mar 29 05:15:00 2012
From: cxie4 at marvell.com (Chao Xie)
Date: Thu, 29 Mar 2012 02:15:00 -0700
Subject: [PATCH 4/4] Input: pxa27x_keypad add choice to set direct_key_mask
In-Reply-To: <4F735295.2010604@mvista.com>
References: <1332911324-9840-1-git-send-email-chao.xie@marvell.com>
 <1332911324-9840-4-git-send-email-chao.xie@marvell.com>
 <4F735295.2010604@mvista.com>
Message-ID: <AAD1C6EB06EE3649B35B7E026785068D1A7474ABC7@SC-VEXCH2.marvell.com>

Thanks. I will sent V2 patches.

-----Original Message-----
From: Sergei Shtylyov [mailto:sshtylyov at mvista.com] 
Sent: Thursday, March 29, 2012 2:04 AM
To: Chao Xie
Cc: linux-input at vger.kernel.org; eric.y.miao at gmail.com; Haojian Zhuang; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH 4/4] Input: pxa27x_keypad add choice to set direct_key_mask

Hello.

On 03/28/2012 09:08 AM, Chao Xie wrote:

> Direct keys usage may not start from KP_DKIN0, add a msk option
> to configure the specifics for platforms that can skip some keys.

> Signed-off-by: Chao Xie<chao.xie at marvell.com>
[...]

> diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
> index b41ebda..661892b 100644
> --- a/drivers/input/keyboard/pxa27x_keypad.c
> +++ b/drivers/input/keyboard/pxa27x_keypad.c
> @@ -391,7 +391,12 @@ static void pxa27x_keypad_config(struct pxa27x_keypad *keypad)
>   	if (pdata->direct_key_num>  direct_key_num)
>   		direct_key_num = pdata->direct_key_num;
>
> -	keypad->direct_key_mask = ((1<<  direct_key_num) - 1)&  ~mask;
> +	/* Direct keys usage may not start from KP_DKIN0, check the platfrom
> +	 * msk data to config the specific */

    The preferred multi-line comment style is not this one. You got it right in 
the previous patch. :-)

WBR, Sergei


From pullip.cho at samsung.com  Thu Mar 29 05:55:32 2012
From: pullip.cho at samsung.com (Cho KyongHo)
Date: Thu, 29 Mar 2012 18:55:32 +0900
Subject: arm: mm: fix faulty calculation of area to perform cache operation
Message-ID: <002c01cd0d92$14acd5f0$3e0681d0$%cho@samsung.com>

In dma_cache_maint_page(), if offset is larger than PAGE_SIZE,
len becomes PAGE_SIZE - offset. If size is smaller than
PAGE_SIZE - offset, next calcuation of left cause overflow.

Signed-off-by: KyongHo Cho <pullip.cho at samsung.com>
---
 arch/arm/mm/dma-mapping.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 1aa664a..14f53b6 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -517,7 +517,7 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
 					page += offset / PAGE_SIZE;
 					offset %= PAGE_SIZE;
 				}
-				len = PAGE_SIZE - offset;
+				len = min_t(size_t, PAGE_SIZE - offset, len);
 			}
 			vaddr = kmap_high_get(page);
 			if (vaddr) {
-- 
1.7.1




From tarun.kanti at ti.com  Thu Mar 29 06:01:53 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Thu, 29 Mar 2012 15:31:53 +0530
Subject: [PATCH v3 0/4] ARM: OMAP: boards: changes to support dynamic irq alloc
Message-ID: <1333015317-11866-1-git-send-email-tarun.kanti@ti.com>

These four patches incorporate changes to OMAP1 and OMAP2 platforms
board files whereby older references to OMAP_GPIO_IRQ macro are
now replaced with gpio_to_irq(), thereby getting rid of static
irq references.

Reference: git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git omap/dt
Commit: fde7d9049e55ab85a390be7f415d74c9f62dd0f9

Test info:
OMAP1 Platforms:
Boot test on OMAP1710 H3.

OMAP2PLUS Platforms:
Boot test on OMAP2430SDP, OMAP3430SDP, OMAP3630-ZOOM3, OMAP4430-SDP.

v3:
Avoid accessing devices using device array index. Consider following list:

static struct platform_device *h2_devices[] __initdata = {
        &h2_nor_device,
        &h2_nand_device,
        &h2_smc91x_device,
        &h2_irda_device,
        &h2_kp_device,
        &h2_lcd_device,
};

static void __init h2_init(void)
{
[...]
       h2_devices[2]->resource[1].start = gpio_to_irq(0);
       h2_devices[2]->resource[1].end = gpio_to_irq(0);
[...]
}

The above implementation is immune to failure if someone inserts new device
in the list before h2_smc91x_device. In order to avoid such a problem access
the devices directly like this:

       h2_smc91x_resources[1].start = gpio_to_irq(0);
       h2_smc91x_resources[1].end = gpio_to_irq(0);

Similar change incorporated for all the boards wherever applicable.

v2:
- Modified the patch subjects as per convention.
- Added a new patch to remove OMAP_GPIO_IRQ from ams_delta_serio driver.
- Added a new patch to remove OMAP_GPIO_IRQ macro definition.

Tarun Kanti DebBarma (4):
  ARM: OMAP1: boards: Fix OMAP_GPIO_IRQ usage with gpio_to_irq()
  ARM: OMAP2+: boards: Fix OMAP_GPIO_IRQ usage with gpio_to_irq()
  drivers: input: Fix OMAP_GPIO_IRQ with gpio_to_irq() in
    ams_delta_serio_exit()
  ARM: OMAP: Remove OMAP_GPIO_IRQ macro definition

 arch/arm/mach-omap1/board-h2.c               |    8 ++++----
 arch/arm/mach-omap1/board-h3.c               |    9 ++++-----
 arch/arm/mach-omap1/board-htcherald.c        |    6 +++---
 arch/arm/mach-omap1/board-innovator.c        |    4 ++--
 arch/arm/mach-omap1/board-nokia770.c         |    2 +-
 arch/arm/mach-omap1/board-osk.c              |   12 ++++++------
 arch/arm/mach-omap1/board-palmte.c           |    2 +-
 arch/arm/mach-omap1/board-palmtt.c           |    2 +-
 arch/arm/mach-omap1/board-palmz71.c          |    2 +-
 arch/arm/mach-omap1/board-voiceblue.c        |   16 +++++++---------
 arch/arm/mach-omap2/board-2430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-4430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-apollon.c          |    4 ++--
 arch/arm/mach-omap2/board-devkit8000.c       |    2 +-
 arch/arm/mach-omap2/board-h4.c               |    2 +-
 arch/arm/mach-omap2/board-omap3evm.c         |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c       |    2 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c |    3 ++-
 arch/arm/mach-omap2/board-zoom-debugboard.c  |    3 ++-
 arch/arm/mach-omap2/board-zoom-peripherals.c |    6 ++++--
 arch/arm/mach-omap2/common-board-devices.c   |    2 +-
 arch/arm/plat-omap/include/plat/gpio.h       |    4 ----
 drivers/input/serio/ams_delta_serio.c        |    2 +-
 23 files changed, 48 insertions(+), 51 deletions(-)



From tarun.kanti at ti.com  Thu Mar 29 06:01:57 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Thu, 29 Mar 2012 15:31:57 +0530
Subject: [PATCH v3 4/4] ARM: OMAP: Remove OMAP_GPIO_IRQ macro definition
In-Reply-To: <1333015317-11866-1-git-send-email-tarun.kanti@ti.com>
References: <1333015317-11866-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1333015317-11866-5-git-send-email-tarun.kanti@ti.com>

Since all references to OMAP_GPIO_IRQ macro are replaced now
with gpio_to_irq(), this can be removed altogether.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 arch/arm/plat-omap/include/plat/gpio.h |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 9e86ee0..d4df414 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -158,10 +158,6 @@
 #define OMAP_MPUIO(nr)		(OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr)	((nr) >= OMAP_MAX_GPIO_LINES)
 
-#define OMAP_GPIO_IRQ(nr)	(OMAP_GPIO_IS_MPUIO(nr) ? \
-				 IH_MPUIO_BASE + ((nr) & 0x0f) : \
-				 IH_GPIO_BASE + (nr))
-
 #define METHOD_MPUIO		0
 #define METHOD_GPIO_1510	1
 #define METHOD_GPIO_1610	2
-- 
1.7.0.4



From tarun.kanti at ti.com  Thu Mar 29 06:01:56 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Thu, 29 Mar 2012 15:31:56 +0530
Subject: [PATCH v3 3/4] drivers: input: Fix OMAP_GPIO_IRQ with gpio_to_irq()
 in ams_delta_serio_exit()
In-Reply-To: <1333015317-11866-1-git-send-email-tarun.kanti@ti.com>
References: <1333015317-11866-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1333015317-11866-4-git-send-email-tarun.kanti@ti.com>

Even though ams-delta-serio input driver uses gpio_to_irq() in all
relevent places to get irq number, the ams_delta_serio_exit() still
uses OMAP_GPIO_IRQ macro. Fix this.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 drivers/input/serio/ams_delta_serio.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/input/serio/ams_delta_serio.c b/drivers/input/serio/ams_delta_serio.c
index d4d08bd..dbe1ae8 100644
--- a/drivers/input/serio/ams_delta_serio.c
+++ b/drivers/input/serio/ams_delta_serio.c
@@ -170,7 +170,7 @@ module_init(ams_delta_serio_init);
 static void __exit ams_delta_serio_exit(void)
 {
 	serio_unregister_port(ams_delta_serio);
-	free_irq(OMAP_GPIO_IRQ(AMS_DELTA_GPIO_PIN_KEYBRD_CLK), 0);
+	free_irq(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK), 0);
 	gpio_free(AMS_DELTA_GPIO_PIN_KEYBRD_CLK);
 	gpio_free(AMS_DELTA_GPIO_PIN_KEYBRD_DATA);
 }
-- 
1.7.0.4



From tarun.kanti at ti.com  Thu Mar 29 06:01:55 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Thu, 29 Mar 2012 15:31:55 +0530
Subject: [PATCH v3 2/4] ARM: OMAP2+: boards: Fix OMAP_GPIO_IRQ usage with
 gpio_to_irq()
In-Reply-To: <1333015317-11866-1-git-send-email-tarun.kanti@ti.com>
References: <1333015317-11866-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1333015317-11866-3-git-send-email-tarun.kanti@ti.com>

With dynamic allocation of IRQ the usage of OMAP_GPIO_IRQ
is no longer valid. We should be using gpio_to_irq() instead.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 arch/arm/mach-omap2/board-2430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-4430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-apollon.c          |    4 ++--
 arch/arm/mach-omap2/board-devkit8000.c       |    2 +-
 arch/arm/mach-omap2/board-h4.c               |    2 +-
 arch/arm/mach-omap2/board-omap3evm.c         |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c       |    2 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c |    3 ++-
 arch/arm/mach-omap2/board-zoom-debugboard.c  |    3 ++-
 arch/arm/mach-omap2/board-zoom-peripherals.c |    6 ++++--
 arch/arm/mach-omap2/common-board-devices.c   |    2 +-
 11 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 7370983..5a1b6af 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -230,12 +230,12 @@ static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = {
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2D),
 		.flags = I2C_CLIENT_WAKE,
-		.irq = OMAP_GPIO_IRQ(78),
 	},
 };
 
 static int __init omap2430_i2c_init(void)
 {
+	sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
 	omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
 			ARRAY_SIZE(sdp2430_i2c1_boardinfo));
 	omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 4e90715..a09c699 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -873,7 +873,6 @@ static void __init omap4_sdp4430_wifi_mux_init(void)
 }
 
 static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
 	.board_ref_clock = WL12XX_REFCLOCK_26,
 	.board_tcxo_clock = WL12XX_TCXOCLOCK_26,
 };
@@ -883,6 +882,7 @@ static void __init omap4_sdp4430_wifi_init(void)
 	int ret;
 
 	omap4_sdp4430_wifi_mux_init();
+	omap4_sdp4430_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
 	ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
 	if (ret)
 		pr_err("Error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index ac77382..768ece2 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -136,8 +136,6 @@ static struct resource apollon_smc91x_resources[] = {
 		.flags  = IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
-		.end	= OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -341,6 +339,8 @@ static void __init omap_apollon_init(void)
 	 * You have to mux them off in device drivers later on
 	 * if not needed.
 	 */
+	apollon_smc91x_resources[1].start = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
+	apollon_smc91x_resources[1].end = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
 	platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index e873063..87cdb86 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -410,7 +410,6 @@ static struct resource omap_dm9000_resources[] = {
 		.flags		= IORESOURCE_MEM,
 	},
 	[2] = {
-		.start		= OMAP_GPIO_IRQ(OMAP_DM9000_GPIO_IRQ),
 		.flags		= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
 	},
 };
@@ -637,6 +636,7 @@ static void __init devkit8000_init(void)
 	omap_dm9000_init();
 
 	devkit8000_i2c_init();
+	omap_dm9000_resources[2].start = gpio_to_irq(OMAP_DM9000_GPIO_IRQ);
 	platform_add_devices(devkit8000_devices,
 			ARRAY_SIZE(devkit8000_devices));
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 54af800..0bbbabe 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -348,7 +348,6 @@ static struct at24_platform_data m24c01 = {
 static struct i2c_board_info __initdata h4_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(125),
 	},
 	{	/* EEPROM on mainboard */
 		I2C_BOARD_INFO("24c01", 0x52),
@@ -377,6 +376,7 @@ static void __init omap_h4_init(void)
 	 */
 
 	board_mkp_init();
+	h4_i2c_board_info[0].irq = gpio_to_irq(125);
 	i2c_register_board_info(1, h4_i2c_board_info,
 			ARRAY_SIZE(h4_i2c_board_info));
 
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c877236..eed88a4 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -487,7 +487,6 @@ static struct platform_device omap3evm_wlan_regulator = {
 };
 
 struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
 	.board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
 };
 #endif
@@ -623,6 +622,7 @@ static void __init omap3_evm_wl12xx_init(void)
 	int ret;
 
 	/* WL12xx WLAN Init */
+	omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
 	ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 28fc271..4496007 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -199,7 +199,6 @@ static struct platform_device omap_vwlan_device = {
 };
 
 struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
-	.irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
 	/* PANDA ref clock is 38.4 MHz */
 	.board_ref_clock = 2,
 };
@@ -494,6 +493,7 @@ static void __init omap4_panda_init(void)
 		package = OMAP_PACKAGE_CBL;
 	omap4_mux_init(board_mux, NULL, package);
 
+	omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
 	ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index acb4e77..1cec076 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -172,7 +172,6 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
 		.modalias		= "tsc2005",
 		.bus_num		= 1,
 		.chip_select		= 0,
-		.irq			= OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
 		.max_speed_hz		= 6000000,
 		.controller_data	= &tsc2005_mcspi_config,
 		.platform_data		= &tsc2005_pdata,
@@ -1124,6 +1123,8 @@ static void __init rx51_init_tsc2005(void)
 		"tsc2005 reset");
 	if (r >= 0) {
 		tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
+		rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq =
+					gpio_to_irq(RX51_TSC2005_IRQ_GPIO);
 	} else {
 		printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
 		tsc2005_pdata.esd_timeout_ms = 0;
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 369c2eb..1e8540e 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -43,7 +43,6 @@ static inline void __init zoom_init_smsc911x(void)
 static struct plat_serial8250_port serial_platform_data[] = {
 	{
 		.mapbase	= ZOOM_UART_BASE,
-		.irq		= OMAP_GPIO_IRQ(102),
 		.flags		= UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ,
 		.irqflags	= IRQF_SHARED | IRQF_TRIGGER_RISING,
 		.iotype		= UPIO_MEM,
@@ -89,6 +88,8 @@ static inline void __init zoom_init_quaduart(void)
 	if (gpio_request_one(quart_gpio, GPIOF_IN, "TL16CP754C GPIO") < 0)
 		printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n",
 								quart_gpio);
+
+	serial_platform_data[0].irq = gpio_to_irq(102);
 }
 
 static inline int omap_zoom_debugboard_detect(void)
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index c126461..a489f82 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -193,7 +193,6 @@ static struct platform_device omap_vwlan_device = {
 };
 
 static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO),
 	/* ZOOM ref clock is 26 MHz */
 	.board_ref_clock = 1,
 };
@@ -296,7 +295,10 @@ static void enable_board_wakeup_source(void)
 
 void __init zoom_peripherals_init(void)
 {
-	int ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
+	int ret;
+
+	omap_zoom_wlan_data.irq = gpio_to_irq(OMAP_ZOOM_WLAN_IRQ_GPIO);
+	ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
 
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index bcb0c58..4cb17b4 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -79,7 +79,7 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 	ads7846_config.gpio_pendown = gpio_pendown;
 
 	spi_bi->bus_num	= bus_num;
-	spi_bi->irq	= OMAP_GPIO_IRQ(gpio_pendown);
+	spi_bi->irq	= gpio_to_irq(gpio_pendown);
 
 	if (board_pdata)
 		spi_bi->platform_data = board_pdata;
-- 
1.7.0.4



From tarun.kanti at ti.com  Thu Mar 29 06:01:54 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Thu, 29 Mar 2012 15:31:54 +0530
Subject: [PATCH v3 1/4] ARM: OMAP1: boards: Fix OMAP_GPIO_IRQ usage with
 gpio_to_irq()
In-Reply-To: <1333015317-11866-1-git-send-email-tarun.kanti@ti.com>
References: <1333015317-11866-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <1333015317-11866-2-git-send-email-tarun.kanti@ti.com>

With dynamic allocation of IRQ the usage of OMAP_GPIO_IRQ
is no longer valid. We should be using gpio_to_irq() instead.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 arch/arm/mach-omap1/board-h2.c        |    8 ++++----
 arch/arm/mach-omap1/board-h3.c        |    9 ++++-----
 arch/arm/mach-omap1/board-htcherald.c |    6 +++---
 arch/arm/mach-omap1/board-innovator.c |    4 ++--
 arch/arm/mach-omap1/board-nokia770.c  |    2 +-
 arch/arm/mach-omap1/board-osk.c       |   12 ++++++------
 arch/arm/mach-omap1/board-palmte.c    |    2 +-
 arch/arm/mach-omap1/board-palmtt.c    |    2 +-
 arch/arm/mach-omap1/board-palmz71.c   |    2 +-
 arch/arm/mach-omap1/board-voiceblue.c |   16 +++++++---------
 10 files changed, 30 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 00ad6b2..b6926d4 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -244,8 +244,6 @@ static struct resource h2_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -364,11 +362,9 @@ static struct tps65010_board tps_board = {
 static struct i2c_board_info __initdata h2_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("tps65010", 0x48),
-		.irq            = OMAP_GPIO_IRQ(58),
 		.platform_data	= &tps_board,
 	}, {
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(2),
 	},
 };
 
@@ -437,10 +433,14 @@ static void __init h2_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	h2_smc91x_resources[1].start = gpio_to_irq(0);
+	h2_smc91x_resources[1].end = gpio_to_irq(0);
 	platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
 	omap_board_config = h2_config;
 	omap_board_config_size = ARRAY_SIZE(h2_config);
 	omap_serial_init();
+	h2_i2c_board_info[0].irq = gpio_to_irq(58);
+	h2_i2c_board_info[1].irq = gpio_to_irq(2);
 	omap_register_i2c_bus(1, 100, h2_i2c_board_info,
 			      ARRAY_SIZE(h2_i2c_board_info));
 	omap1_usb_init(&h2_usb_config);
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 4a7f251..15f1028 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -246,8 +246,6 @@ static struct resource smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(40),
-		.end	= OMAP_GPIO_IRQ(40),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -337,7 +335,6 @@ static struct spi_board_info h3_spi_board_info[] __initdata = {
 		.modalias	= "tsc2101",
 		.bus_num	= 2,
 		.chip_select	= 0,
-		.irq		= OMAP_GPIO_IRQ(H3_TS_GPIO),
 		.max_speed_hz	= 16000000,
 		/* .platform_data	= &tsc_platform_data, */
 	},
@@ -377,11 +374,9 @@ static struct omap_board_config_kernel h3_config[] __initdata = {
 static struct i2c_board_info __initdata h3_i2c_board_info[] = {
        {
 		I2C_BOARD_INFO("tps65013", 0x48),
-               /* .irq         = OMAP_GPIO_IRQ(??), */
        },
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(14),
 	},
 };
 
@@ -423,12 +418,16 @@ static void __init h3_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	smc91x_resources[1].start = gpio_to_irq(40);
+	smc91x_resources[1].end = gpio_to_irq(40);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
+	h3_spi_board_info[0].irq = gpio_to_irq(H3_TS_GPIO);
 	spi_register_board_info(h3_spi_board_info,
 				ARRAY_SIZE(h3_spi_board_info));
 	omap_board_config = h3_config;
 	omap_board_config_size = ARRAY_SIZE(h3_config);
 	omap_serial_init();
+	h3_i2c_board_info[1].irq = gpio_to_irq(14);
 	omap_register_i2c_bus(1, 100, h3_i2c_board_info,
 			      ARRAY_SIZE(h3_i2c_board_info));
 	omap1_usb_init(&h3_usb_config);
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 731cc3d..cc04144 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -324,8 +324,6 @@ static struct platform_device gpio_leds_device = {
 
 static struct resource htcpld_resources[] = {
 	[0] = {
-		.start  = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
-		.end    = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
 		.flags  = IORESOURCE_IRQ,
 	},
 };
@@ -454,7 +452,6 @@ static struct spi_board_info __initdata htcherald_spi_board_info[] = {
 	{
 		.modalias		= "ads7846",
 		.platform_data		= &htcherald_ts_platform_data,
-		.irq			= OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS),
 		.max_speed_hz		= 2500000,
 		.bus_num		= 2,
 		.chip_select		= 1,
@@ -582,6 +579,8 @@ static void __init htcherald_init(void)
 	/* Do board initialization before we register all the devices */
 	omap_board_config = htcherald_config;
 	omap_board_config_size = ARRAY_SIZE(htcherald_config);
+	htcpld_resources[0].start = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
+	htcpld_resources[0].end = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	htcherald_disable_watchdog();
@@ -589,6 +588,7 @@ static void __init htcherald_init(void)
 	htcherald_usb_enable();
 	omap1_usb_init(&htcherald_usb_config);
 
+	htcherald_spi_board_info[0].irq = gpio_to_irq(HTCHERALD_GPIO_TS);
 	spi_register_board_info(htcherald_spi_board_info,
 		ARRAY_SIZE(htcherald_spi_board_info));
 
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index be2002f..5e5dee7 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -244,8 +244,6 @@ static struct resource innovator1610_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -409,6 +407,8 @@ static void __init innovator_init(void)
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
 	if (!cpu_is_omap1510()) {
+		innovator1610_smc91x_resources[1].start = gpio_to_irq(0);
+		innovator1610_smc91x_resources[1].end = gpio_to_irq(0);
 		platform_add_devices(innovator1610_devices, ARRAY_SIZE(innovator1610_devices));
 	}
 #endif
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index f9efc03..364e3d7 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -145,7 +145,6 @@ static struct spi_board_info nokia770_spi_board_info[] __initdata = {
 		.bus_num        = 2,
 		.chip_select    = 0,
 		.max_speed_hz   = 2500000,
-		.irq		= OMAP_GPIO_IRQ(15),
 		.platform_data	= &nokia770_ads7846_platform_data,
 	},
 };
@@ -240,6 +239,7 @@ static void __init omap_nokia770_init(void)
 	omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
 
 	platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
+	nokia770_spi_board_info[1].irq = gpio_to_irq(15);
 	spi_register_board_info(nokia770_spi_board_info,
 				ARRAY_SIZE(nokia770_spi_board_info));
 	omap_serial_init();
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 675de06..b1a9e61 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -129,8 +129,6 @@ static struct resource osk5912_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -147,8 +145,6 @@ static struct platform_device osk5912_smc91x_device = {
 
 static struct resource osk5912_cf_resources[] = {
 	[0] = {
-		.start	= OMAP_GPIO_IRQ(62),
-		.end	= OMAP_GPIO_IRQ(62),
 		.flags	= IORESOURCE_IRQ,
 	},
 };
@@ -240,7 +236,6 @@ static struct tps65010_board tps_board = {
 static struct i2c_board_info __initdata osk_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("tps65010", 0x48),
-		.irq		= OMAP_GPIO_IRQ(OMAP_MPUIO(1)),
 		.platform_data	= &tps_board,
 
 	},
@@ -414,7 +409,6 @@ static struct spi_board_info __initdata mistral_boardinfo[] = { {
 	/* MicroWire (bus 2) CS0 has an ads7846e */
 	.modalias		= "ads7846",
 	.platform_data		= &mistral_ts_info,
-	.irq			= OMAP_GPIO_IRQ(4),
 	.max_speed_hz		= 120000 /* max sample rate at 3V */
 					* 26 /* command + data + overhead */,
 	.bus_num		= 2,
@@ -477,6 +471,7 @@ static void __init osk_mistral_init(void)
 	gpio_direction_input(4);
 	irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
 
+	mistral_boardinfo[0].irq = gpio_to_irq(4);
 	spi_register_board_info(mistral_boardinfo,
 			ARRAY_SIZE(mistral_boardinfo));
 
@@ -548,6 +543,10 @@ static void __init osk_init(void)
 
 	osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
 	osk_flash_resource.end += SZ_32M - 1;
+	osk5912_smc91x_resources[1].start = gpio_to_irq(0);
+	osk5912_smc91x_resources[1].end = gpio_to_irq(0);
+	osk5912_cf_resources[0].start = gpio_to_irq(62);
+	osk5912_cf_resources[0].end = gpio_to_irq(62);
 	platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
 	omap_board_config = osk_config;
 	omap_board_config_size = ARRAY_SIZE(osk_config);
@@ -564,6 +563,7 @@ static void __init osk_init(void)
 		gpio_direction_input(OMAP_MPUIO(1));
 
 	omap_serial_init();
+	osk_i2c_board_info[0].irq = gpio_to_irq(OMAP_MPUIO(1));
 	omap_register_i2c_bus(1, 400, osk_i2c_board_info,
 			      ARRAY_SIZE(osk_i2c_board_info));
 	osk_mistral_init();
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 81fa27f..108c7d1 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -218,7 +218,6 @@ static struct spi_board_info palmte_spi_info[] __initdata = {
 		.modalias	= "tsc2102",
 		.bus_num	= 2,	/* uWire (officially) */
 		.chip_select	= 0,	/* As opposed to 3 */
-		.irq		= OMAP_GPIO_IRQ(PALMTE_PINTDAV_GPIO),
 		.max_speed_hz	= 8000000,
 	},
 };
@@ -255,6 +254,7 @@ static void __init omap_palmte_init(void)
 
 	platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices));
 
+	palmte_spi_info[0].irq = gpio_to_irq(PALMTE_PINTDAV_GPIO);
 	spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
 	palmte_misc_gpio_setup();
 	omap_serial_init();
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 81cb821..b87a92f 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -255,7 +255,6 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
 		/* MicroWire (bus 2) CS0 has an ads7846e */
 		.modalias	= "ads7846",
 		.platform_data	= &palmtt_ts_info,
-		.irq		= OMAP_GPIO_IRQ(6),
 		.max_speed_hz	= 120000	/* max sample rate at 3V */
 					* 26	/* command + data + overhead */,
 		.bus_num	= 2,
@@ -303,6 +302,7 @@ static void __init omap_palmtt_init(void)
 
 	platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices));
 
+	palmtt_boardinfo[0].irq = gpio_to_irq(6);
 	spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
 	omap_serial_init();
 	omap1_usb_init(&palmtt_usb_config);
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index e881945..0ff25fa 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -222,7 +222,6 @@ static struct spi_board_info __initdata palmz71_boardinfo[] = { {
 	/* MicroWire (bus 2) CS0 has an ads7846e */
 	.modalias	= "ads7846",
 	.platform_data	= &palmz71_ts_info,
-	.irq		= OMAP_GPIO_IRQ(PALMZ71_PENIRQ_GPIO),
 	.max_speed_hz	= 120000	/* max sample rate at 3V */
 				* 26	/* command + data + overhead */,
 	.bus_num	= 2,
@@ -318,6 +317,7 @@ omap_palmz71_init(void)
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
+	palmz71_boardinfo[0].irq = gpio_to_irq(PALMZ71_PENIRQ_GPIO);
 	spi_register_board_info(palmz71_boardinfo,
 				ARRAY_SIZE(palmz71_boardinfo));
 	omap1_usb_init(&palmz71_usb_config);
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index f83a502..85b62e7 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -42,7 +42,6 @@
 static struct plat_serial8250_port voiceblue_ports[] = {
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x40000),
-		.irq		= OMAP_GPIO_IRQ(12),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -50,7 +49,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x50000),
-		.irq		= OMAP_GPIO_IRQ(13),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -58,7 +56,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x60000),
-		.irq		= OMAP_GPIO_IRQ(14),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -66,7 +63,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x70000),
-		.irq		= OMAP_GPIO_IRQ(15),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -78,9 +74,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 static struct platform_device serial_device = {
 	.name			= "serial8250",
 	.id			= PLAT8250_DEV_PLATFORM1,
-	.dev			= {
-		.platform_data	= voiceblue_ports,
-	},
 };
 
 static int __init ext_uart_init(void)
@@ -88,6 +81,11 @@ static int __init ext_uart_init(void)
 	if (!machine_is_voiceblue())
 		return -ENODEV;
 
+	voiceblue_ports[0].irq = gpio_to_irq(12);
+	voiceblue_ports[1].irq = gpio_to_irq(13);
+	voiceblue_ports[2].irq = gpio_to_irq(14);
+	voiceblue_ports[3].irq = gpio_to_irq(15);
+	serial_device.dev.platform_data = voiceblue_ports;
 	return platform_device_register(&serial_device);
 }
 arch_initcall(ext_uart_init);
@@ -126,8 +124,6 @@ static struct resource voiceblue_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(8),
-		.end	= OMAP_GPIO_IRQ(8),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -273,6 +269,8 @@ static void __init voiceblue_init(void)
 	irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
 	irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
 
+	voiceblue_smc91x_resources[1].start = gpio_to_irq(8);
+	voiceblue_smc91x_resources[1].end = gpio_to_irq(8);
 	platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
 	omap_board_config = voiceblue_config;
 	omap_board_config_size = ARRAY_SIZE(voiceblue_config);
-- 
1.7.0.4



From tarun.kanti at ti.com  Thu Mar 29 06:08:26 2012
From: tarun.kanti at ti.com (Tarun Kanti DebBarma)
Date: Thu, 29 Mar 2012 15:38:26 +0530
Subject: [PATCH v3 1/4] ARM: OMAP1: boards: Fix OMAP_GPIO_IRQ usage with
 gpio_to_irq()
Message-ID: <1333015706-11931-1-git-send-email-tarun.kanti@ti.com>

With dynamic allocation of IRQ the usage of OMAP_GPIO_IRQ
is no longer valid. We should be using gpio_to_irq() instead.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
---
 arch/arm/mach-omap1/board-h2.c        |    8 ++++----
 arch/arm/mach-omap1/board-h3.c        |    9 ++++-----
 arch/arm/mach-omap1/board-htcherald.c |    6 +++---
 arch/arm/mach-omap1/board-innovator.c |    4 ++--
 arch/arm/mach-omap1/board-nokia770.c  |    2 +-
 arch/arm/mach-omap1/board-osk.c       |   12 ++++++------
 arch/arm/mach-omap1/board-palmte.c    |    2 +-
 arch/arm/mach-omap1/board-palmtt.c    |    2 +-
 arch/arm/mach-omap1/board-palmz71.c   |    2 +-
 arch/arm/mach-omap1/board-voiceblue.c |   16 +++++++---------
 10 files changed, 30 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 00ad6b2..b6926d4 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -244,8 +244,6 @@ static struct resource h2_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -364,11 +362,9 @@ static struct tps65010_board tps_board = {
 static struct i2c_board_info __initdata h2_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("tps65010", 0x48),
-		.irq            = OMAP_GPIO_IRQ(58),
 		.platform_data	= &tps_board,
 	}, {
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(2),
 	},
 };
 
@@ -437,10 +433,14 @@ static void __init h2_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	h2_smc91x_resources[1].start = gpio_to_irq(0);
+	h2_smc91x_resources[1].end = gpio_to_irq(0);
 	platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
 	omap_board_config = h2_config;
 	omap_board_config_size = ARRAY_SIZE(h2_config);
 	omap_serial_init();
+	h2_i2c_board_info[0].irq = gpio_to_irq(58);
+	h2_i2c_board_info[1].irq = gpio_to_irq(2);
 	omap_register_i2c_bus(1, 100, h2_i2c_board_info,
 			      ARRAY_SIZE(h2_i2c_board_info));
 	omap1_usb_init(&h2_usb_config);
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 4a7f251..15f1028 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -246,8 +246,6 @@ static struct resource smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(40),
-		.end	= OMAP_GPIO_IRQ(40),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -337,7 +335,6 @@ static struct spi_board_info h3_spi_board_info[] __initdata = {
 		.modalias	= "tsc2101",
 		.bus_num	= 2,
 		.chip_select	= 0,
-		.irq		= OMAP_GPIO_IRQ(H3_TS_GPIO),
 		.max_speed_hz	= 16000000,
 		/* .platform_data	= &tsc_platform_data, */
 	},
@@ -377,11 +374,9 @@ static struct omap_board_config_kernel h3_config[] __initdata = {
 static struct i2c_board_info __initdata h3_i2c_board_info[] = {
        {
 		I2C_BOARD_INFO("tps65013", 0x48),
-               /* .irq         = OMAP_GPIO_IRQ(??), */
        },
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(14),
 	},
 };
 
@@ -423,12 +418,16 @@ static void __init h3_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	smc91x_resources[1].start = gpio_to_irq(40);
+	smc91x_resources[1].end = gpio_to_irq(40);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
+	h3_spi_board_info[0].irq = gpio_to_irq(H3_TS_GPIO);
 	spi_register_board_info(h3_spi_board_info,
 				ARRAY_SIZE(h3_spi_board_info));
 	omap_board_config = h3_config;
 	omap_board_config_size = ARRAY_SIZE(h3_config);
 	omap_serial_init();
+	h3_i2c_board_info[1].irq = gpio_to_irq(14);
 	omap_register_i2c_bus(1, 100, h3_i2c_board_info,
 			      ARRAY_SIZE(h3_i2c_board_info));
 	omap1_usb_init(&h3_usb_config);
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 731cc3d..cc04144 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -324,8 +324,6 @@ static struct platform_device gpio_leds_device = {
 
 static struct resource htcpld_resources[] = {
 	[0] = {
-		.start  = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
-		.end    = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
 		.flags  = IORESOURCE_IRQ,
 	},
 };
@@ -454,7 +452,6 @@ static struct spi_board_info __initdata htcherald_spi_board_info[] = {
 	{
 		.modalias		= "ads7846",
 		.platform_data		= &htcherald_ts_platform_data,
-		.irq			= OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS),
 		.max_speed_hz		= 2500000,
 		.bus_num		= 2,
 		.chip_select		= 1,
@@ -582,6 +579,8 @@ static void __init htcherald_init(void)
 	/* Do board initialization before we register all the devices */
 	omap_board_config = htcherald_config;
 	omap_board_config_size = ARRAY_SIZE(htcherald_config);
+	htcpld_resources[0].start = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
+	htcpld_resources[0].end = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	htcherald_disable_watchdog();
@@ -589,6 +588,7 @@ static void __init htcherald_init(void)
 	htcherald_usb_enable();
 	omap1_usb_init(&htcherald_usb_config);
 
+	htcherald_spi_board_info[0].irq = gpio_to_irq(HTCHERALD_GPIO_TS);
 	spi_register_board_info(htcherald_spi_board_info,
 		ARRAY_SIZE(htcherald_spi_board_info));
 
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index be2002f..5e5dee7 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -244,8 +244,6 @@ static struct resource innovator1610_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -409,6 +407,8 @@ static void __init innovator_init(void)
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
 	if (!cpu_is_omap1510()) {
+		innovator1610_smc91x_resources[1].start = gpio_to_irq(0);
+		innovator1610_smc91x_resources[1].end = gpio_to_irq(0);
 		platform_add_devices(innovator1610_devices, ARRAY_SIZE(innovator1610_devices));
 	}
 #endif
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index f9efc03..364e3d7 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -145,7 +145,6 @@ static struct spi_board_info nokia770_spi_board_info[] __initdata = {
 		.bus_num        = 2,
 		.chip_select    = 0,
 		.max_speed_hz   = 2500000,
-		.irq		= OMAP_GPIO_IRQ(15),
 		.platform_data	= &nokia770_ads7846_platform_data,
 	},
 };
@@ -240,6 +239,7 @@ static void __init omap_nokia770_init(void)
 	omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
 
 	platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
+	nokia770_spi_board_info[1].irq = gpio_to_irq(15);
 	spi_register_board_info(nokia770_spi_board_info,
 				ARRAY_SIZE(nokia770_spi_board_info));
 	omap_serial_init();
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 675de06..b1a9e61 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -129,8 +129,6 @@ static struct resource osk5912_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -147,8 +145,6 @@ static struct platform_device osk5912_smc91x_device = {
 
 static struct resource osk5912_cf_resources[] = {
 	[0] = {
-		.start	= OMAP_GPIO_IRQ(62),
-		.end	= OMAP_GPIO_IRQ(62),
 		.flags	= IORESOURCE_IRQ,
 	},
 };
@@ -240,7 +236,6 @@ static struct tps65010_board tps_board = {
 static struct i2c_board_info __initdata osk_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("tps65010", 0x48),
-		.irq		= OMAP_GPIO_IRQ(OMAP_MPUIO(1)),
 		.platform_data	= &tps_board,
 
 	},
@@ -414,7 +409,6 @@ static struct spi_board_info __initdata mistral_boardinfo[] = { {
 	/* MicroWire (bus 2) CS0 has an ads7846e */
 	.modalias		= "ads7846",
 	.platform_data		= &mistral_ts_info,
-	.irq			= OMAP_GPIO_IRQ(4),
 	.max_speed_hz		= 120000 /* max sample rate at 3V */
 					* 26 /* command + data + overhead */,
 	.bus_num		= 2,
@@ -477,6 +471,7 @@ static void __init osk_mistral_init(void)
 	gpio_direction_input(4);
 	irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
 
+	mistral_boardinfo[0].irq = gpio_to_irq(4);
 	spi_register_board_info(mistral_boardinfo,
 			ARRAY_SIZE(mistral_boardinfo));
 
@@ -548,6 +543,10 @@ static void __init osk_init(void)
 
 	osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
 	osk_flash_resource.end += SZ_32M - 1;
+	osk5912_smc91x_resources[1].start = gpio_to_irq(0);
+	osk5912_smc91x_resources[1].end = gpio_to_irq(0);
+	osk5912_cf_resources[0].start = gpio_to_irq(62);
+	osk5912_cf_resources[0].end = gpio_to_irq(62);
 	platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
 	omap_board_config = osk_config;
 	omap_board_config_size = ARRAY_SIZE(osk_config);
@@ -564,6 +563,7 @@ static void __init osk_init(void)
 		gpio_direction_input(OMAP_MPUIO(1));
 
 	omap_serial_init();
+	osk_i2c_board_info[0].irq = gpio_to_irq(OMAP_MPUIO(1));
 	omap_register_i2c_bus(1, 400, osk_i2c_board_info,
 			      ARRAY_SIZE(osk_i2c_board_info));
 	osk_mistral_init();
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 81fa27f..108c7d1 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -218,7 +218,6 @@ static struct spi_board_info palmte_spi_info[] __initdata = {
 		.modalias	= "tsc2102",
 		.bus_num	= 2,	/* uWire (officially) */
 		.chip_select	= 0,	/* As opposed to 3 */
-		.irq		= OMAP_GPIO_IRQ(PALMTE_PINTDAV_GPIO),
 		.max_speed_hz	= 8000000,
 	},
 };
@@ -255,6 +254,7 @@ static void __init omap_palmte_init(void)
 
 	platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices));
 
+	palmte_spi_info[0].irq = gpio_to_irq(PALMTE_PINTDAV_GPIO);
 	spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
 	palmte_misc_gpio_setup();
 	omap_serial_init();
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 81cb821..b87a92f 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -255,7 +255,6 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
 		/* MicroWire (bus 2) CS0 has an ads7846e */
 		.modalias	= "ads7846",
 		.platform_data	= &palmtt_ts_info,
-		.irq		= OMAP_GPIO_IRQ(6),
 		.max_speed_hz	= 120000	/* max sample rate at 3V */
 					* 26	/* command + data + overhead */,
 		.bus_num	= 2,
@@ -303,6 +302,7 @@ static void __init omap_palmtt_init(void)
 
 	platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices));
 
+	palmtt_boardinfo[0].irq = gpio_to_irq(6);
 	spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
 	omap_serial_init();
 	omap1_usb_init(&palmtt_usb_config);
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index e881945..0ff25fa 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -222,7 +222,6 @@ static struct spi_board_info __initdata palmz71_boardinfo[] = { {
 	/* MicroWire (bus 2) CS0 has an ads7846e */
 	.modalias	= "ads7846",
 	.platform_data	= &palmz71_ts_info,
-	.irq		= OMAP_GPIO_IRQ(PALMZ71_PENIRQ_GPIO),
 	.max_speed_hz	= 120000	/* max sample rate at 3V */
 				* 26	/* command + data + overhead */,
 	.bus_num	= 2,
@@ -318,6 +317,7 @@ omap_palmz71_init(void)
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
+	palmz71_boardinfo[0].irq = gpio_to_irq(PALMZ71_PENIRQ_GPIO);
 	spi_register_board_info(palmz71_boardinfo,
 				ARRAY_SIZE(palmz71_boardinfo));
 	omap1_usb_init(&palmz71_usb_config);
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index f83a502..85b62e7 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -42,7 +42,6 @@
 static struct plat_serial8250_port voiceblue_ports[] = {
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x40000),
-		.irq		= OMAP_GPIO_IRQ(12),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -50,7 +49,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x50000),
-		.irq		= OMAP_GPIO_IRQ(13),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -58,7 +56,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x60000),
-		.irq		= OMAP_GPIO_IRQ(14),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -66,7 +63,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x70000),
-		.irq		= OMAP_GPIO_IRQ(15),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -78,9 +74,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 static struct platform_device serial_device = {
 	.name			= "serial8250",
 	.id			= PLAT8250_DEV_PLATFORM1,
-	.dev			= {
-		.platform_data	= voiceblue_ports,
-	},
 };
 
 static int __init ext_uart_init(void)
@@ -88,6 +81,11 @@ static int __init ext_uart_init(void)
 	if (!machine_is_voiceblue())
 		return -ENODEV;
 
+	voiceblue_ports[0].irq = gpio_to_irq(12);
+	voiceblue_ports[1].irq = gpio_to_irq(13);
+	voiceblue_ports[2].irq = gpio_to_irq(14);
+	voiceblue_ports[3].irq = gpio_to_irq(15);
+	serial_device.dev.platform_data = voiceblue_ports;
 	return platform_device_register(&serial_device);
 }
 arch_initcall(ext_uart_init);
@@ -126,8 +124,6 @@ static struct resource voiceblue_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(8),
-		.end	= OMAP_GPIO_IRQ(8),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -273,6 +269,8 @@ static void __init voiceblue_init(void)
 	irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
 	irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
 
+	voiceblue_smc91x_resources[1].start = gpio_to_irq(8);
+	voiceblue_smc91x_resources[1].end = gpio_to_irq(8);
 	platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
 	omap_board_config = voiceblue_config;
 	omap_board_config_size = ARRAY_SIZE(voiceblue_config);
-- 
1.7.0.4



From govindraj.raja at ti.com  Thu Mar 29 06:09:22 2012
From: govindraj.raja at ti.com (Govindraj.R)
Date: Thu, 29 Mar 2012 15:39:22 +0530
Subject: [PATCH] omap2+: pm: fix compilation break.
Message-ID: <1333015762-476-1-git-send-email-govindraj.raja@ti.com>

From: "Govindraj.R" <govindraj.raja at ti.com>

Fix the compilation break observed on latest mainline.

Fixes below compilation break:

arch/arm/mach-omap2/pm.c: In function 'omap_pm_begin':
arch/arm/mach-omap2/pm.c:239: error: implicit declaration of function 'disable_hlt'
arch/arm/mach-omap2/pm.c: In function 'omap_pm_end':
arch/arm/mach-omap2/pm.c:247: error: implicit declaration of function 'enable_hlt'

Cc: Kevin Hilman <khilman at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
---
 arch/arm/mach-omap2/pm.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index a7bdec6..70da4f7 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -16,6 +16,7 @@
 #include <linux/opp.h>
 #include <linux/export.h>
 #include <linux/suspend.h>
+#include <asm/system_misc.h>
 
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>
-- 
1.7.5.4



From viresh.kumar at st.com  Thu Mar 29 06:44:46 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 29 Mar 2012 16:14:46 +0530
Subject: [PATCH V2 5/7] ARM: SPEAr3xx: Add device-tree support to SPEAr3xx
 architecture
In-Reply-To: <201203290753.04758.arnd@arndb.de>
References: <cover.1332926608.git.viresh.kumar@st.com>
 <201203281227.32299.arnd@arndb.de> <4F740386.2080509@st.com>
 <201203290753.04758.arnd@arndb.de>
Message-ID: <4F743D1E.9030209@st.com>

On 3/29/2012 1:23 PM, Arnd Bergmann wrote:
> That should not really be a concern, you only waste a little bit of
> the vmalloc space that you gained recently when ioremap was changed.
> Nothing should ever be able to get to those pointers other than by
> calling ioremap, so it doesn't hurt to have them mapped, except for
> the very unlikely scenario that you get a wild pointer dereference
> in the kernel that would otherwise result in an oops.

Ok. I will create two 16M mappings for now:

PHYSICAL			VIRTUAL
0xD0000000 - 0xD1000000		0xFD000000
0xFC000000 - 0xFD000000		0xFC000000


-- 
viresh


From viresh.kumar at st.com  Thu Mar 29 06:40:58 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 29 Mar 2012 16:10:58 +0530
Subject: [PATCH V3 0/7] SPEAr DT support updates
Message-ID: <cover.1333017183.git.viresh.kumar@st.com>

Hello,

This patchset updates DT support for SPEAr3xx and 6xx.
It has following changes:
- updates DT support Mainly for SPEAr3xx family
- updates dma support for SPEAr6xx
- updates defconfig

It has dependency on following patchsets:
- ehci & ohci: http://www.spinics.net/lists/linux-usb/msg60362.html
- rtc: http://lkml.org/lkml/2012/3/26/96
- keyboard: http://www.spinics.net/lists/linux-input/msg19904.html

V2->V3:
- Removed macro for adding entries in auxdata array for ssp and dma
- removed IO_ADDRESS() completely
- Create 16M static mappings instead of 4K mappings
- Don't return error from spear*dt_init() if board doesn't match for padmux
- Config symbols and #ifdef,#endif are not updated for DT
- interrupt-parenti=<&vic> moved to root node.

V1->V2:
- Separate DT_MACHINE_INIT macros are defined per SoC.
- PATCH 1/7 was sent earlier as individual patch, and is now included in this
  patchset for completeness.
- clock support for ehci and ohci added
- plat data for UART PL011 removed as it is not required
- Minor issues fixed

Viresh Kumar (7):
  SPEAr: Use CLKDEV_INIT for defining clk_lookups
  SPEAr3xx: Add clock instance of usb hosts - ehci and ohci 0 and 1
  SPEAr6xx: Add compilation support for dtbs using 'make dtbs'
  SPEAr3xx: Replace printk() with pr_*()
  ARM: SPEAr3xx: Add device-tree support to SPEAr3xx architecture
  SPEAr: Add PL080 DMA support for 3xx and 6xx
  SPEAr: Update defconfigs

 Documentation/arm/SPEAr/overview.txt            |   13 +-
 Documentation/devicetree/bindings/arm/spear.txt |   18 ++
 arch/arm/boot/dts/spear300-evb.dts              |  183 +++++++++++
 arch/arm/boot/dts/spear300.dtsi                 |   72 +++++
 arch/arm/boot/dts/spear310-evb.dts              |  111 +++++++
 arch/arm/boot/dts/spear310.dtsi                 |   75 +++++
 arch/arm/boot/dts/spear320-evb.dts              |  112 +++++++
 arch/arm/boot/dts/spear320.dtsi                 |   90 ++++++
 arch/arm/boot/dts/spear3xx.dtsi                 |  144 +++++++++
 arch/arm/boot/dts/spear600-evb.dts              |    4 +
 arch/arm/boot/dts/spear600.dtsi                 |    8 +
 arch/arm/configs/spear3xx_defconfig             |   52 +++-
 arch/arm/configs/spear6xx_defconfig             |   41 ++-
 arch/arm/mach-spear3xx/Kconfig                  |   34 +--
 arch/arm/mach-spear3xx/Makefile                 |   13 +-
 arch/arm/mach-spear3xx/Makefile.boot            |    4 +
 arch/arm/mach-spear3xx/clock.c                  |  182 +++++++-----
 arch/arm/mach-spear3xx/include/mach/generic.h   |   31 +--
 arch/arm/mach-spear3xx/include/mach/hardware.h  |    3 -
 arch/arm/mach-spear3xx/include/mach/spear.h     |    9 +-
 arch/arm/mach-spear3xx/spear300.c               |  294 ++++++++++++++++--
 arch/arm/mach-spear3xx/spear300_evb.c           |   75 -----
 arch/arm/mach-spear3xx/spear310.c               |  329 +++++++++++++++++++--
 arch/arm/mach-spear3xx/spear310_evb.c           |   81 -----
 arch/arm/mach-spear3xx/spear320.c               |  328 +++++++++++++++++++--
 arch/arm/mach-spear3xx/spear320_evb.c           |   79 -----
 arch/arm/mach-spear3xx/spear3xx.c               |  148 +++++----
 arch/arm/mach-spear6xx/Makefile.boot            |    2 +
 arch/arm/mach-spear6xx/clock.c                  |   80 +++---
 arch/arm/mach-spear6xx/spear6xx.c               |  372 ++++++++++++++++++++++-
 arch/arm/plat-spear/Kconfig                     |    3 +-
 arch/arm/plat-spear/Makefile                    |    2 +-
 arch/arm/plat-spear/include/plat/pl080.h        |   21 ++
 arch/arm/plat-spear/pl080.c                     |   79 +++++
 34 files changed, 2505 insertions(+), 587 deletions(-)
 create mode 100644 arch/arm/boot/dts/spear300-evb.dts
 create mode 100644 arch/arm/boot/dts/spear300.dtsi
 create mode 100644 arch/arm/boot/dts/spear310-evb.dts
 create mode 100644 arch/arm/boot/dts/spear310.dtsi
 create mode 100644 arch/arm/boot/dts/spear320-evb.dts
 create mode 100644 arch/arm/boot/dts/spear320.dtsi
 create mode 100644 arch/arm/boot/dts/spear3xx.dtsi
 delete mode 100644 arch/arm/mach-spear3xx/spear300_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear310_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear320_evb.c
 create mode 100644 arch/arm/plat-spear/include/plat/pl080.h
 create mode 100644 arch/arm/plat-spear/pl080.c

-- 
1.7.9



From viresh.kumar at st.com  Thu Mar 29 06:41:01 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 29 Mar 2012 16:11:01 +0530
Subject: [PATCH V3 3/7] SPEAr6xx: Add compilation support for dtbs using 'make
 dtbs'
In-Reply-To: <cover.1333017183.git.viresh.kumar@st.com>
References: <cover.1333017183.git.viresh.kumar@st.com>
Message-ID: <b60bcdd8cca9d6d2bca5741344708599cae4f591.1333017183.git.viresh.kumar@st.com>

'make dtbs' compiles all dtbs for a family. For this we need to add entries for
all board dtb's in Makefile.boot file. This patch does it.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/mach-spear6xx/Makefile.boot |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c..af493da 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_BOARD_SPEAR600_DT)	+= spear600-evb.dtb
-- 
1.7.9



From viresh.kumar at st.com  Thu Mar 29 06:41:00 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 29 Mar 2012 16:11:00 +0530
Subject: [PATCH V3 2/7] SPEAr3xx: Add clock instance of usb hosts - ehci and
 ohci 0 and 1
In-Reply-To: <cover.1333017183.git.viresh.kumar@st.com>
References: <cover.1333017183.git.viresh.kumar@st.com>
Message-ID: <4874b04e10d82eca2c48ce7a4ad69954532e55a3.1333017183.git.viresh.kumar@st.com>

This patch adds following clocks: "usbh.0_clk" and "usbh.1_clk". They are used
by ehci and ohci drivers for SPEAr3xx usb host devices.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/mach-spear3xx/clock.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6b2cd9b..47d4535 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -412,6 +412,21 @@ static struct clk usbd_clk = {
 	.recalc = &follow_parent,
 };
 
+/* clock derived from usbh clk */
+/* usbh0 clock */
+static struct clk usbh0_clk = {
+	.flags = ALWAYS_ENABLED,
+	.pclk = &usbh_clk,
+	.recalc = &follow_parent,
+};
+
+/* usbh1 clock */
+static struct clk usbh1_clk = {
+	.flags = ALWAYS_ENABLED,
+	.pclk = &usbh_clk,
+	.recalc = &follow_parent,
+};
+
 /* clock derived from ahb clk */
 /* apb masks structure */
 static struct bus_clk_masks apb_masks = {
@@ -679,6 +694,9 @@ static struct clk_lookup spear_clk_lookups[] = {
 	/* clock derived from pll3 clk */
 	CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
 	CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
+	/* clock derived from usbh clk */
+	CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+	CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
 	/* clock derived from ahb clk */
 	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
 	CLKDEV_INIT("i2c_designware.0", NULL, &i2c_clk),
-- 
1.7.9



From viresh.kumar at st.com  Thu Mar 29 06:40:59 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 29 Mar 2012 16:10:59 +0530
Subject: [PATCH V3 1/7] SPEAr: Use CLKDEV_INIT for defining clk_lookups
In-Reply-To: <cover.1333017183.git.viresh.kumar@st.com>
References: <cover.1333017183.git.viresh.kumar@st.com>
Message-ID: <be5e7f4568973ff23078d638499b373124d89c41.1333017183.git.viresh.kumar@st.com>

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/mach-spear3xx/clock.c |  111 ++++++++++++++++++++--------------------
 arch/arm/mach-spear6xx/clock.c |   80 ++++++++++++++--------------
 2 files changed, 96 insertions(+), 95 deletions(-)

diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6c4841f..6b2cd9b 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -11,6 +11,7 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/clkdev.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
@@ -652,85 +653,85 @@ static struct clk pwm_clk = {
 
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-	{ .con_id = "apb_pclk",		.clk = &dummy_apb_pclk},
+	CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
 	/* root clks */
-	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
-	{ .con_id = "osc_24m_clk",	.clk = &osc_24m_clk},
+	CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+	CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
 	/* clock derived from 32 KHz osc clk */
-	{ .dev_id = "rtc-spear",	.clk = &rtc_clk},
+	CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
 	/* clock derived from 24 MHz osc clk */
-	{ .con_id = "pll1_clk",		.clk = &pll1_clk},
-	{ .con_id = "pll3_48m_clk",	.clk = &pll3_48m_clk},
-	{ .dev_id = "wdt",		.clk = &wdt_clk},
+	CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+	CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+	CLKDEV_INIT("wdt", NULL, &wdt_clk),
 	/* clock derived from pll1 clk */
-	{ .con_id = "cpu_clk",		.clk = &cpu_clk},
-	{ .con_id = "ahb_clk",		.clk = &ahb_clk},
-	{ .con_id = "uart_synth_clk",	.clk = &uart_synth_clk},
-	{ .con_id = "firda_synth_clk",	.clk = &firda_synth_clk},
-	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
-	{ .con_id = "gpt1_synth_clk",	.clk = &gpt1_synth_clk},
-	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
-	{ .dev_id = "uart",		.clk = &uart_clk},
-	{ .dev_id = "firda",		.clk = &firda_clk},
-	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
-	{ .dev_id = "gpt1",		.clk = &gpt1_clk},
-	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
+	CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+	CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+	CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+	CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+	CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+	CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
+	CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+	CLKDEV_INIT("uart", NULL, &uart_clk),
+	CLKDEV_INIT("firda", NULL, &firda_clk),
+	CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+	CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+	CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
 	/* clock derived from pll3 clk */
-	{ .dev_id = "designware_udc",   .clk = &usbd_clk},
-	{ .con_id = "usbh_clk",		.clk = &usbh_clk},
+	CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+	CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
 	/* clock derived from ahb clk */
-	{ .con_id = "apb_clk",		.clk = &apb_clk},
-	{ .dev_id = "i2c_designware.0",	.clk = &i2c_clk},
-	{ .dev_id = "dma",		.clk = &dma_clk},
-	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
-	{ .dev_id = "gmac",		.clk = &gmac_clk},
-	{ .dev_id = "smi",		.clk = &smi_clk},
-	{ .dev_id = "c3",		.clk = &c3_clk},
+	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+	CLKDEV_INIT("i2c_designware.0", NULL, &i2c_clk),
+	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+	CLKDEV_INIT("gmac", NULL, &gmac_clk),
+	CLKDEV_INIT("smi", NULL, &smi_clk),
+	CLKDEV_INIT("c3", NULL, &c3_clk),
 	/* clock derived from apb clk */
-	{ .dev_id = "adc",		.clk = &adc_clk},
-	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
-	{ .dev_id = "gpio",		.clk = &gpio_clk},
+	CLKDEV_INIT("adc", NULL, &adc_clk),
+	CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
+	CLKDEV_INIT("gpio", NULL, &gpio_clk),
 };
 
 /* array of all spear 300 clock lookups */
 #ifdef CONFIG_MACH_SPEAR300
 static struct clk_lookup spear300_clk_lookups[] = {
-	{ .dev_id = "clcd",		.clk = &clcd_clk},
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
-	{ .dev_id = "gpio1",		.clk = &gpio1_clk},
-	{ .dev_id = "keyboard",		.clk = &kbd_clk},
-	{ .dev_id = "sdhci",		.clk = &sdhci_clk},
+	CLKDEV_INIT("clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+	CLKDEV_INIT("gpio1", NULL, &gpio1_clk),
+	CLKDEV_INIT("keyboard", NULL, &kbd_clk),
+	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
 };
 #endif
 
 /* array of all spear 310 clock lookups */
 #ifdef CONFIG_MACH_SPEAR310
 static struct clk_lookup spear310_clk_lookups[] = {
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
-	{ .con_id = "emi",		.clk = &emi_clk},
-	{ .dev_id = "uart1",		.clk = &uart1_clk},
-	{ .dev_id = "uart2",		.clk = &uart2_clk},
-	{ .dev_id = "uart3",		.clk = &uart3_clk},
-	{ .dev_id = "uart4",		.clk = &uart4_clk},
-	{ .dev_id = "uart5",		.clk = &uart5_clk},
+	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+	CLKDEV_INIT(NULL, "emi", &emi_clk),
+	CLKDEV_INIT("uart1", NULL, &uart1_clk),
+	CLKDEV_INIT("uart2", NULL, &uart2_clk),
+	CLKDEV_INIT("uart3", NULL, &uart3_clk),
+	CLKDEV_INIT("uart4", NULL, &uart4_clk),
+	CLKDEV_INIT("uart5", NULL, &uart5_clk),
 };
 #endif
 
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
 static struct clk_lookup spear320_clk_lookups[] = {
-	{ .dev_id = "clcd",		.clk = &clcd_clk},
-	{ .con_id = "fsmc",		.clk = &fsmc_clk},
-	{ .dev_id = "i2c_designware.1",	.clk = &i2c1_clk},
-	{ .con_id = "emi",		.clk = &emi_clk},
-	{ .dev_id = "pwm",		.clk = &pwm_clk},
-	{ .dev_id = "sdhci",		.clk = &sdhci_clk},
-	{ .dev_id = "c_can_platform.0",	.clk = &can0_clk},
-	{ .dev_id = "c_can_platform.1",	.clk = &can1_clk},
-	{ .dev_id = "ssp-pl022.1",	.clk = &ssp1_clk},
-	{ .dev_id = "ssp-pl022.2",	.clk = &ssp2_clk},
-	{ .dev_id = "uart1",		.clk = &uart1_clk},
-	{ .dev_id = "uart2",		.clk = &uart2_clk},
+	CLKDEV_INIT("clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+	CLKDEV_INIT("i2c_designware.1", NULL, &i2c1_clk),
+	CLKDEV_INIT(NULL, "emi", &emi_clk),
+	CLKDEV_INIT("pwm", NULL, &pwm_clk),
+	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
+	CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
+	CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
+	CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
+	CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
+	CLKDEV_INIT("uart1", NULL, &uart1_clk),
+	CLKDEV_INIT("uart2", NULL, &uart2_clk),
 };
 #endif
 
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index f051804..5a46980 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -623,53 +623,53 @@ static struct clk dummy_apb_pclk;
 
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-	{ .con_id = "apb_pclk",		.clk = &dummy_apb_pclk},
+	CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
 	/* root clks */
-	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
-	{ .con_id = "osc_30m_clk",	.clk = &osc_30m_clk},
+	CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
+	CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk),
 	/* clock derived from 32 KHz os		 clk */
-	{ .dev_id = "rtc-spear",	.clk = &rtc_clk},
+	CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
 	/* clock derived from 30 MHz os		 clk */
-	{ .con_id = "pll1_clk",		.clk = &pll1_clk},
-	{ .con_id = "pll3_48m_clk",	.clk = &pll3_48m_clk},
-	{ .dev_id = "wdt",		.clk = &wdt_clk},
+	CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
+	CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
+	CLKDEV_INIT("wdt", NULL, &wdt_clk),
 	/* clock derived from pll1 clk */
-	{ .con_id = "cpu_clk",		.clk = &cpu_clk},
-	{ .con_id = "ahb_clk",		.clk = &ahb_clk},
-	{ .con_id = "uart_synth_clk",	.clk = &uart_synth_clk},
-	{ .con_id = "firda_synth_clk",	.clk = &firda_synth_clk},
-	{ .con_id = "clcd_synth_clk",	.clk = &clcd_synth_clk},
-	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
-	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
-	{ .con_id = "gpt3_synth_clk",	.clk = &gpt3_synth_clk},
-	{ .dev_id = "d0000000.serial",	.clk = &uart0_clk},
-	{ .dev_id = "d0080000.serial",	.clk = &uart1_clk},
-	{ .dev_id = "firda",		.clk = &firda_clk},
-	{ .dev_id = "clcd",		.clk = &clcd_clk},
-	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
-	{ .dev_id = "gpt1",		.clk = &gpt1_clk},
-	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
-	{ .dev_id = "gpt3",		.clk = &gpt3_clk},
+	CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
+	CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
+	CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
+	CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
+	CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk),
+	CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
+	CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
+	CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk),
+	CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk),
+	CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk),
+	CLKDEV_INIT("firda", NULL, &firda_clk),
+	CLKDEV_INIT("clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
+	CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
+	CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
+	CLKDEV_INIT("gpt3", NULL, &gpt3_clk),
 	/* clock derived from pll3 clk */
-	{ .dev_id = "designware_udc",	.clk = &usbd_clk},
-	{ .con_id = "usbh.0_clk",	.clk = &usbh0_clk},
-	{ .con_id = "usbh.1_clk",	.clk = &usbh1_clk},
+	CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
+	CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+	CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
 	/* clock derived from ahb clk */
-	{ .con_id = "apb_clk",		.clk = &apb_clk},
-	{ .dev_id = "d0200000.i2c",	.clk = &i2c_clk},
-	{ .dev_id = "dma",		.clk = &dma_clk},
-	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
-	{ .dev_id = "gmac",		.clk = &gmac_clk},
-	{ .dev_id = "fc000000.flash",	.clk = &smi_clk},
-	{ .dev_id = "d1800000.flash",	.clk = &fsmc_clk},
+	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
+	CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
+	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
+	CLKDEV_INIT("gmac", NULL, &gmac_clk),
+	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
+	CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk),
 	/* clock derived from apb clk */
-	{ .dev_id = "adc",		.clk = &adc_clk},
-	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
-	{ .dev_id = "ssp-pl022.1",	.clk = &ssp1_clk},
-	{ .dev_id = "ssp-pl022.2",	.clk = &ssp2_clk},
-	{ .dev_id = "f0100000.gpio",	.clk = &gpio0_clk},
-	{ .dev_id = "fc980000.gpio",	.clk = &gpio1_clk},
-	{ .dev_id = "d8100000.gpio",	.clk = &gpio2_clk},
+	CLKDEV_INIT("adc", NULL, &adc_clk),
+	CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
+	CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
+	CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
+	CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk),
+	CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk),
+	CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk),
 };
 
 void __init spear6xx_clk_init(void)
-- 
1.7.9



From viresh.kumar at st.com  Thu Mar 29 06:41:02 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 29 Mar 2012 16:11:02 +0530
Subject: [PATCH V3 4/7] SPEAr3xx: Replace printk() with pr_*()
In-Reply-To: <cover.1333017183.git.viresh.kumar@st.com>
References: <cover.1333017183.git.viresh.kumar@st.com>
Message-ID: <e852e09d702a241259924801c1fc306447e4dee2.1333017183.git.viresh.kumar@st.com>

For better print logs/messages, it is advisable to use pr_*() routines instead
of directly calling printks. This patch removes direct calling of printks for
spear3xx.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/mach-spear3xx/spear300.c |    8 +++++---
 arch/arm/mach-spear3xx/spear310.c |   13 +++++++------
 arch/arm/mach-spear3xx/spear320.c |   11 ++++++-----
 arch/arm/mach-spear3xx/spear3xx.c |    2 ++
 4 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db668..adee72b 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr300: " fmt
+
 #include <linux/types.h>
 #include <linux/amba/pl061.h>
 #include <linux/ptrace.h>
@@ -447,7 +449,7 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 	if (shirq_ras1.regs.base) {
 		ret = spear_shirq_register(&shirq_ras1);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ\n");
+			pr_err("Error registering Shared IRQ\n");
 	}
 
 	/* pmx initialization */
@@ -459,8 +461,8 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 	if (pmx_driver.base) {
 		ret = pmx_register(&pmx_driver);
 		if (ret)
-			printk(KERN_ERR "padmux: registration failed. err no"
-					": %d\n", ret);
+			pr_err("padmux: registration failed. err no: %d\n",
+					ret);
 		/* Free Mapping, device selection already done */
 		iounmap(pmx_driver.base);
 	}
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6f..b7c2876 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr310: " fmt
+
 #include <linux/ptrace.h>
 #include <asm/irq.h>
 #include <plat/shirq.h>
@@ -274,25 +276,25 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 		shirq_ras1.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras1);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 1\n");
+			pr_err("Error registering Shared IRQ 1\n");
 
 		/* shirq 2 */
 		shirq_ras2.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras2);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 2\n");
+			pr_err("Error registering Shared IRQ 2\n");
 
 		/* shirq 3 */
 		shirq_ras3.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras3);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 3\n");
+			pr_err("Error registering Shared IRQ 3\n");
 
 		/* shirq 4 */
 		shirq_intrcomm_ras.regs.base = base;
 		ret = spear_shirq_register(&shirq_intrcomm_ras);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 4\n");
+			pr_err("Error registering Shared IRQ 4\n");
 	}
 
 	/* pmx initialization */
@@ -303,6 +305,5 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 
 	ret = pmx_register(&pmx_driver);
 	if (ret)
-		printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-				ret);
+		pr_err("padmux: registration failed. err no: %d\n", ret);
 }
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf19..7bd39c0 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr320: " fmt
+
 #include <linux/ptrace.h>
 #include <asm/irq.h>
 #include <plat/shirq.h>
@@ -527,19 +529,19 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 		shirq_ras1.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras1);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 1\n");
+			pr_err("Error registering Shared IRQ 1\n");
 
 		/* shirq 3 */
 		shirq_ras3.regs.base = base;
 		ret = spear_shirq_register(&shirq_ras3);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 3\n");
+			pr_err("Error registering Shared IRQ 3\n");
 
 		/* shirq 4 */
 		shirq_intrcomm_ras.regs.base = base;
 		ret = spear_shirq_register(&shirq_intrcomm_ras);
 		if (ret)
-			printk(KERN_ERR "Error registering Shared IRQ 4\n");
+			pr_err("Error registering Shared IRQ 4\n");
 	}
 
 	/* pmx initialization */
@@ -550,6 +552,5 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 
 	ret = pmx_register(&pmx_driver);
 	if (ret)
-		printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-				ret);
+		pr_err("padmux: registration failed. err no: %d\n", ret);
 }
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c3..a236925 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -11,6 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define pr_fmt(fmt) "SPEAr3xx: " fmt
+
 #include <linux/types.h>
 #include <linux/amba/pl061.h>
 #include <linux/ptrace.h>
-- 
1.7.9



From viresh.kumar at st.com  Thu Mar 29 06:41:04 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 29 Mar 2012 16:11:04 +0530
Subject: [PATCH V3 6/7] SPEAr: Add PL080 DMA support for 3xx and 6xx
In-Reply-To: <cover.1333017183.git.viresh.kumar@st.com>
References: <cover.1333017183.git.viresh.kumar@st.com>
Message-ID: <6fb0ec92c408efe9e0192b54cc00dd4828331a45.1333017183.git.viresh.kumar@st.com>

Both SPEAr3xx and SPEAr6xx families have one instance of ARM PL080 DMA
controller. This patch adds in support for that.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/boot/dts/spear300-evb.dts            |    4 +
 arch/arm/boot/dts/spear310-evb.dts            |    4 +
 arch/arm/boot/dts/spear320-evb.dts            |    4 +
 arch/arm/boot/dts/spear3xx.dtsi               |    8 +
 arch/arm/boot/dts/spear600-evb.dts            |    4 +
 arch/arm/boot/dts/spear600.dtsi               |    8 +
 arch/arm/mach-spear3xx/clock.c                |    2 +-
 arch/arm/mach-spear3xx/include/mach/generic.h |    2 +
 arch/arm/mach-spear3xx/spear300.c             |  193 +++++++++++++
 arch/arm/mach-spear3xx/spear310.c             |  192 +++++++++++++
 arch/arm/mach-spear3xx/spear320.c             |  192 +++++++++++++
 arch/arm/mach-spear3xx/spear3xx.c             |   19 ++
 arch/arm/mach-spear6xx/clock.c                |    2 +-
 arch/arm/mach-spear6xx/spear6xx.c             |  372 ++++++++++++++++++++++++-
 arch/arm/plat-spear/Makefile                  |    2 +-
 arch/arm/plat-spear/include/plat/pl080.h      |   21 ++
 arch/arm/plat-spear/pl080.c                   |   79 ++++++
 17 files changed, 1104 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/plat-spear/include/plat/pl080.h
 create mode 100644 arch/arm/plat-spear/pl080.c

diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
index f2ee991..eaecc29 100644
--- a/arch/arm/boot/dts/spear300-evb.dts
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -29,6 +29,10 @@
 			status = "okay";
 		};
 
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		fsmc: flash at 94000000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
index ec19d7b..c86af33 100644
--- a/arch/arm/boot/dts/spear310-evb.dts
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -25,6 +25,10 @@
 	};
 
 	ahb {
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		fsmc: flash at 44000000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index 5681a97..d43de71 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -29,6 +29,10 @@
 			status = "okay";
 		};
 
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		fsmc: flash at 4c000000 {
 			status = "okay";
 		};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index 924a6f6..0ae7c8e 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -40,6 +40,14 @@
 			#interrupt-cells = <1>;
 		};
 
+		dma at fc400000 {
+			compatible = "arm,pl080", "arm,primecell";
+			reg = <0xfc400000 0x1000>;
+			interrupt-parent = <&vic>;
+			interrupts = <8>;
+			status = "disabled";
+		};
+
 		gmac: eth at e0800000 {
 			compatible = "st,spear600-gmac";
 			reg = <0xe0800000 0x8000>;
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e..790a7a8 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,6 +24,10 @@
 	};
 
 	ahb {
+		dma at fc400000 {
+			status = "okay";
+		};
+
 		gmac: ethernet at e0800000 {
 			phy-mode = "gmii";
 			status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885..d777e3a 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
 			#interrupt-cells = <1>;
 		};
 
+		dma at fc400000 {
+			compatible = "arm,pl080", "arm,primecell";
+			reg = <0xfc400000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <10>;
+			status = "disabled";
+		};
+
 		gmac: ethernet at e0800000 {
 			compatible = "st,spear600-gmac";
 			reg = <0xe0800000 0x8000>;
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 9293c14..eeafe38 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -701,7 +701,7 @@ static struct clk_lookup spear_clk_lookups[] = {
 	/* clock derived from ahb clk */
 	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
 	CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
-	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
 	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
 	CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
 	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 84ee2bb..a756958 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,6 +14,7 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
 
+#include <linux/amba/pl08x.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
@@ -33,6 +34,7 @@
 /* Add spear3xx family device structure declarations here */
 extern struct sys_timer spear3xx_timer;
 extern struct pl022_ssp_controller pl022_plat_data;
+extern struct pl08x_platform_data pl080_plat_data;
 
 /* Add spear3xx family function declarations here */
 void __init spear_setup_timer(void);
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index c876c6a..f46fc26 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -13,6 +13,7 @@
 
 #define pr_fmt(fmt) "SPEAr300: " fmt
 
+#include <linux/amba/pl08x.h>
 #include <linux/of_platform.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -440,10 +441,199 @@ static struct pmx_dev *spear300_evb_pmx_devs[] = {
 	&spear300_pmx_gpio1,
 };
 
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear300_dma_info[] = {
+	{
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	},
+};
+
 /* Add SPEAr300 auxdata to pass platform data */
 static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
 			&pl022_plat_data),
+	OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+			&pl080_plat_data),
 	{}
 };
 
@@ -451,6 +641,9 @@ static void __init spear300_dt_init(void)
 {
 	int ret = -EINVAL;
 
+	pl080_plat_data.slave_channels = spear300_dma_info;
+	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
+
 	of_platform_populate(NULL, of_default_bus_match_table,
 			spear300_auxdata_lookup, NULL);
 
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 641fd4c..063e7da 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -284,6 +284,193 @@ static struct pmx_dev *spear310_evb_pmx_devs[] = {
 	&spear310_pmx_tdm0,
 };
 
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear310_dma_info[] = {
+	{
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart2_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart2_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart3_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart3_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart4_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart4_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart5_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart5_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	},
+};
+
 /* uart devices plat data */
 static struct amba_pl011_data spear310_uart_data[] = {
 	{
@@ -313,6 +500,8 @@ static struct amba_pl011_data spear310_uart_data[] = {
 static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
 			&pl022_plat_data),
+	OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+			&pl080_plat_data),
 	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
 			&spear310_uart_data[0]),
 	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
@@ -331,6 +520,9 @@ static void __init spear310_dt_init(void)
 	void __iomem *base;
 	int ret = 0;
 
+	pl080_plat_data.slave_channels = spear310_dma_info;
+	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
+
 	of_platform_populate(NULL, of_default_bus_match_table,
 			spear310_auxdata_lookup, NULL);
 
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 9c571d0..1e74031 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -535,6 +535,193 @@ static struct pmx_dev *spear320_evb_pmx_devs[] = {
 	&spear320_pmx_mii1,
 };
 
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear320_dma_info[] = {
+	{
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c0_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c0_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp1_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp1_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp2_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp2_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "uart2_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c1_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c1_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c2_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2c2_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "i2s_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "rs485_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "rs485_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	},
+};
+
 static struct pl022_ssp_controller spear320_ssp_data[] = {
 	{
 		.bus_id = 1,
@@ -569,6 +756,8 @@ static struct amba_pl011_data spear320_uart_data[] = {
 static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
 			&pl022_plat_data),
+	OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+			&pl080_plat_data),
 	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
 			&spear320_ssp_data[0]),
 	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
@@ -585,6 +774,9 @@ static void __init spear320_dt_init(void)
 	void __iomem *base;
 	int ret = 0;
 
+	pl080_plat_data.slave_channels = spear320_dma_info;
+	pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
+
 	of_platform_populate(NULL, of_default_bus_match_table,
 			spear320_auxdata_lookup, NULL);
 
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index a94d8c1..17d4ac9 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -17,7 +17,9 @@
 #include <linux/amba/pl08x.h>
 #include <linux/of_irq.h>
 #include <linux/io.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
@@ -465,6 +467,23 @@ struct pl022_ssp_controller pl022_plat_data = {
 	.num_chipselect = 2,
 };
 
+/* dmac device registration */
+struct pl08x_platform_data pl080_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl080_get_signal,
+	.put_signal = pl080_put_signal,
+};
+
 /*
  * Following will create 16MB static virtual/physical mappings
  * PHYSICAL		VIRTUAL
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 5a46980..adadef2 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -657,7 +657,7 @@ static struct clk_lookup spear_clk_lookups[] = {
 	/* clock derived from ahb clk */
 	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
 	CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
-	CLKDEV_INIT("dma", NULL, &dma_clk),
+	CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
 	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
 	CLKDEV_INIT("gmac", NULL, &gmac_clk),
 	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14..5b9e30f 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,15 +13,377 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/amba/pl08x.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
+/* dmac device registration */
+static struct pl08x_channel_data spear600_dma_info[] = {
+	{
+		.bus_id = "ssp1_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp1_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp2_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp2_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ext0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	},
+};
+
+struct pl08x_platform_data pl080_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl080_get_signal,
+	.put_signal = pl080_put_signal,
+	.slave_channels = spear600_dma_info,
+	.num_slave_channels = ARRAY_SIZE(spear600_dma_info),
+};
+
 /* Following will create static virtual/physical mappings */
 static struct map_desc spear6xx_io_desc[] __initdata = {
 	{
@@ -92,9 +454,17 @@ struct sys_timer spear6xx_timer = {
 	.init = spear6xx_timer_init,
 };
 
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
+			&pl080_plat_data),
+	{}
+};
+
 static void __init spear600_dt_init(void)
 {
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table,
+			spear6xx_auxdata_lookup, NULL);
 }
 
 static const char *spear600_dt_board_compat[] = {
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b..4af6258 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
 #
 
 # Common support
-obj-y	:= clock.o restart.o time.o
+obj-y	:= clock.o restart.o time.o pl080.o
 
 obj-$(CONFIG_ARCH_SPEAR3XX)	+= shirq.o padmux.o
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644
index 0000000..e14a3e4
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/plat-spear/include/plat/pl080.h
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PL080_H
+#define __PLAT_PL080_H
+
+struct pl08x_dma_chan;
+int pl080_get_signal(struct pl08x_dma_chan *ch);
+void pl080_put_signal(struct pl08x_dma_chan *ch);
+
+#endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644
index 0000000..d53d75e
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,79 @@
+/*
+ * arch/arm/plat-spear/pl080.c
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/bus.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spinlock_types.h>
+#include <mach/misc_regs.h>
+
+static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
+
+struct {
+	unsigned char busy;
+	unsigned char val;
+} signals[16] = {{0, 0}, };
+
+int pl080_get_signal(struct pl08x_dma_chan *ch)
+{
+	const struct pl08x_channel_data *cd = ch->cd;
+	unsigned int signal = cd->min_signal, val;
+	unsigned long flags;
+
+	spin_lock_irqsave(&lock, flags);
+
+	/* Return if signal is already acquired by somebody else */
+	if (signals[signal].busy &&
+			(signals[signal].val != cd->muxval)) {
+		spin_unlock_irqrestore(&lock, flags);
+		return -EBUSY;
+	}
+
+	/* If acquiring for the first time, configure it */
+	if (!signals[signal].busy) {
+		val = readl(DMA_CHN_CFG);
+
+		/*
+		 * Each request line has two bits in DMA_CHN_CFG register. To
+		 * goto the bits of current request line, do left shift of
+		 * value by 2 * signal number.
+		 */
+		val &= ~(0x3 << (signal * 2));
+		val |= cd->muxval << (signal * 2);
+		writel(val, DMA_CHN_CFG);
+	}
+
+	signals[signal].busy++;
+	signals[signal].val = cd->muxval;
+	spin_unlock_irqrestore(&lock, flags);
+
+	return signal;
+}
+
+void pl080_put_signal(struct pl08x_dma_chan *ch)
+{
+	const struct pl08x_channel_data *cd = ch->cd;
+	unsigned long flags;
+
+	spin_lock_irqsave(&lock, flags);
+
+	/* if signal is not used */
+	if (!signals[cd->min_signal].busy)
+		BUG();
+
+	signals[cd->min_signal].busy--;
+
+	spin_unlock_irqrestore(&lock, flags);
+}
-- 
1.7.9



From viresh.kumar at st.com  Thu Mar 29 06:41:03 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 29 Mar 2012 16:11:03 +0530
Subject: [PATCH V3 5/7] ARM: SPEAr3xx: Add device-tree support to SPEAr3xx
 architecture
In-Reply-To: <cover.1333017183.git.viresh.kumar@st.com>
References: <cover.1333017183.git.viresh.kumar@st.com>
Message-ID: <c64379ae6e00c89ba1eb313b825862a9fb37a347.1333017183.git.viresh.kumar@st.com>

This patch adds a generic target for SPEAr3xx machines that can be configured
via the device-tree. Currently the following devices are supported via the
devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- PL110 CLCD
- SP805 WDT
- Synopsys DW I2C
- Synopsys DW ethernet
- ST FSMC-NAND
- ST SPEAR-SMI
- ST SPEAR-KEYBOARD
- ST SPEAR-RTC
- ARASAN SDHCI-SPEAR
- SPEAR-EHCI
- SPEAR-OHCI

Other peripheral devices will follow in later patches.

This also removes IO_ADDRESS macro and creates 16 MB static mappings instead of
4K for individual peripherals. This is done to have efficient TLB lookup for any
I/O windows that are located closely together. ioremap() on this range will
return this mapping only instead of creating another.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 Documentation/arm/SPEAr/overview.txt            |   13 +-
 Documentation/devicetree/bindings/arm/spear.txt |   18 +++
 arch/arm/boot/dts/spear300-evb.dts              |  179 +++++++++++++++++++++++
 arch/arm/boot/dts/spear300.dtsi                 |   72 +++++++++
 arch/arm/boot/dts/spear310-evb.dts              |  107 ++++++++++++++
 arch/arm/boot/dts/spear310.dtsi                 |   75 ++++++++++
 arch/arm/boot/dts/spear320-evb.dts              |  108 ++++++++++++++
 arch/arm/boot/dts/spear320.dtsi                 |   90 ++++++++++++
 arch/arm/boot/dts/spear3xx.dtsi                 |  136 +++++++++++++++++
 arch/arm/mach-spear3xx/Kconfig                  |   34 +----
 arch/arm/mach-spear3xx/Makefile                 |   13 +--
 arch/arm/mach-spear3xx/Makefile.boot            |    4 +
 arch/arm/mach-spear3xx/clock.c                  |  103 ++++++++------
 arch/arm/mach-spear3xx/include/mach/generic.h   |   29 +---
 arch/arm/mach-spear3xx/include/mach/hardware.h  |    3 -
 arch/arm/mach-spear3xx/include/mach/spear.h     |    9 +-
 arch/arm/mach-spear3xx/spear300.c               |   97 +++++++++----
 arch/arm/mach-spear3xx/spear300_evb.c           |   75 ----------
 arch/arm/mach-spear3xx/spear310.c               |  126 ++++++++++++++---
 arch/arm/mach-spear3xx/spear310_evb.c           |   81 ----------
 arch/arm/mach-spear3xx/spear320.c               |  127 ++++++++++++++---
 arch/arm/mach-spear3xx/spear320_evb.c           |   79 ----------
 arch/arm/mach-spear3xx/spear3xx.c               |  127 ++++++++---------
 arch/arm/plat-spear/Kconfig                     |    3 +-
 24 files changed, 1222 insertions(+), 486 deletions(-)
 create mode 100644 arch/arm/boot/dts/spear300-evb.dts
 create mode 100644 arch/arm/boot/dts/spear300.dtsi
 create mode 100644 arch/arm/boot/dts/spear310-evb.dts
 create mode 100644 arch/arm/boot/dts/spear310.dtsi
 create mode 100644 arch/arm/boot/dts/spear320-evb.dts
 create mode 100644 arch/arm/boot/dts/spear320.dtsi
 create mode 100644 arch/arm/boot/dts/spear3xx.dtsi
 delete mode 100644 arch/arm/mach-spear3xx/spear300_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear310_evb.c
 delete mode 100644 arch/arm/mach-spear3xx/spear320_evb.c

diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c..28a9af9 100644
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -17,14 +17,14 @@ Introduction
   SPEAr (Platform)
 	- SPEAr3XX (3XX SOC series, based on ARM9)
 		- SPEAr300 (SOC)
-			- SPEAr300_EVB (Evaluation Board)
+			- SPEAr300 Evaluation Board
 		- SPEAr310 (SOC)
-			- SPEAr310_EVB (Evaluation Board)
+			- SPEAr310 Evaluation Board
 		- SPEAr320 (SOC)
-			- SPEAr320_EVB (Evaluation Board)
+			- SPEAr320 Evaluation Board
 	- SPEAr6XX (6XX SOC series, based on ARM9)
 		- SPEAr600 (SOC)
-			- SPEAr600_EVB (Evaluation Board)
+			- SPEAr600 Evaluation Board
 	- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
 		- SPEAr1300 (SOC)
 
@@ -51,10 +51,11 @@ Introduction
   Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
   spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
   specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
-  mach-spear* also contains board specific files for each machine type.
+  mach-spear* doesn't contains board specific files as they fully support
+  Flattened Device Tree.
 
 
   Document Author
   ---------------
 
-  Viresh Kumar, (c) 2010 ST Microelectronics
+  Viresh Kumar <viresh.kumar at st.com>, (c) 2010-2012 ST Microelectronics
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
index f8e54f0..aa5f355 100644
--- a/Documentation/devicetree/bindings/arm/spear.txt
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -6,3 +6,21 @@ Boards with the ST SPEAr600 SoC shall have the following properties:
 Required root node property:
 
 compatible = "st,spear600";
+
+Boards with the ST SPEAr300 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear300";
+
+Boards with the ST SPEAr310 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear310";
+
+Boards with the ST SPEAr320 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear320";
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644
index 0000000..f2ee991
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,179 @@
+/*
+ * DTS file for SPEAr300 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear300.dtsi"
+
+/ {
+	model = "ST SPEAr300 Evaluation Board";
+	compatible = "st,spear300-evb", "st,spear300";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		clcd at 60000000 {
+			status = "okay";
+		};
+
+		fsmc: flash at 94000000 {
+			status = "okay";
+		};
+
+		gmac: eth at e0800000 {
+			status = "okay";
+		};
+
+		sdhci at 70000000 {
+			int-gpio = <&gpio1 0 0>;
+			power-gpio = <&gpio1 2 1>;
+			status = "okay";
+		};
+
+		smi: flash at fc000000 {
+			status = "okay";
+		};
+
+		spi0: spi at d0100000 {
+			status = "okay";
+		};
+
+		ehci at e1800000 {
+			status = "okay";
+		};
+
+		ohci at e1900000 {
+			status = "okay";
+		};
+
+		ohci at e2100000 {
+			status = "okay";
+		};
+
+		apb {
+			gpio0: gpio at fc980000 {
+			       status = "okay";
+			};
+
+			gpio1: gpio at a9000000 {
+			       status = "okay";
+			};
+
+			i2c0: i2c at d0180000 {
+			       status = "okay";
+			};
+
+			kbd at a0000000 {
+				linux,keymap = < 0x00010000
+						 0x00020100
+						 0x00030200
+						 0x00040300
+						 0x00050400
+						 0x00060500
+						 0x00070600
+						 0x00080700
+						 0x00090800
+						 0x000a0001
+						 0x000c0101
+						 0x000d0201
+						 0x000e0301
+						 0x000f0401
+						 0x00100501
+						 0x00110601
+						 0x00120701
+						 0x00130801
+						 0x00140002
+						 0x00150102
+						 0x00160202
+						 0x00170302
+						 0x00180402
+						 0x00190502
+						 0x001a0602
+						 0x001b0702
+						 0x001c0802
+						 0x001d0003
+						 0x001e0103
+						 0x001f0203
+						 0x00200303
+						 0x00210403
+						 0x00220503
+						 0x00230603
+						 0x00240703
+						 0x00250803
+						 0x00260004
+						 0x00270104
+						 0x00280204
+						 0x00290304
+						 0x002a0404
+						 0x002b0504
+						 0x002c0604
+						 0x002d0704
+						 0x002e0804
+						 0x002f0005
+						 0x00300105
+						 0x00310205
+						 0x00320305
+						 0x00330405
+						 0x00340505
+						 0x00350605
+						 0x00360705
+						 0x00370805
+						 0x00380006
+						 0x00390106
+						 0x003a0206
+						 0x003b0306
+						 0x003c0406
+						 0x003d0506
+						 0x003e0606
+						 0x003f0706
+						 0x00400806
+						 0x00410007
+						 0x00420107
+						 0x00430207
+						 0x00440307
+						 0x00450407
+						 0x00460507
+						 0x00470607
+						 0x00480707
+						 0x00490807
+						 0x004a0008
+						 0x004b0108
+						 0x004c0208
+						 0x004d0308
+						 0x004e0408
+						 0x004f0508
+						 0x00500608
+						 0x00510708
+						 0x00520808 >;
+			       autorepeat;
+			       st,mode = <0>;
+			       status = "okay";
+			};
+
+			rtc at fc900000 {
+			       status = "okay";
+			};
+
+			serial at d0000000 {
+			       status = "okay";
+			};
+
+			wdt at fc880000 {
+			       status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644
index 0000000..f9fcbf4
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,72 @@
+/*
+ * DTS file for SPEAr300 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x60000000 0x60000000 0x50000000
+			  0xd0000000 0xd0000000 0x30000000>;
+
+		clcd at 60000000 {
+			compatible = "arm,clcd-pl110", "arm,primecell";
+			reg = <0x60000000 0x1000>;
+			interrupts = <30>;
+			status = "disabled";
+		};
+
+		fsmc: flash at 94000000 {
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x94000000 0x1000	/* FSMC Register */
+			       0x80000000 0x0010>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x20000>;
+			st,cle-off = <0x10000>;
+			status = "disabled";
+		};
+
+		sdhci at 70000000 {
+			compatible = "st,sdhci-spear";
+			reg = <0x70000000 0x100>;
+			interrupts = <1>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xa0000000 0xa0000000 0x10000000
+				  0xd0000000 0xd0000000 0x30000000>;
+
+			gpio1: gpio at a9000000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xa9000000 0x1000>;
+				status = "disabled";
+			};
+
+			kbd at a0000000 {
+				compatible = "st,spear300-kbd";
+				reg = <0xa0000000 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644
index 0000000..ec19d7b
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,107 @@
+/*
+ * DTS file for SPEAr310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear310.dtsi"
+
+/ {
+	model = "ST SPEAr310 Evaluation Board";
+	compatible = "st,spear310-evb", "st,spear310";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		fsmc: flash at 44000000 {
+			status = "okay";
+		};
+
+		gmac: eth at e0800000 {
+			status = "okay";
+		};
+
+		smi: flash at fc000000 {
+			status = "okay";
+			clock-rate=<50000000>;
+
+			flash at f8000000 {
+				label = "m25p64";
+				reg = <0xf8000000 0x800000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				st,smi-fast-mode;
+			};
+		};
+
+		spi0: spi at d0100000 {
+			status = "okay";
+		};
+
+		ehci at e1800000 {
+			status = "okay";
+		};
+
+		ohci at e1900000 {
+			status = "okay";
+		};
+
+		ohci at e2100000 {
+			status = "okay";
+		};
+
+		apb {
+			gpio0: gpio at fc980000 {
+			       status = "okay";
+			};
+
+			i2c0: i2c at d0180000 {
+			       status = "okay";
+			};
+
+			rtc at fc900000 {
+			       status = "okay";
+			};
+
+			serial at d0000000 {
+			       status = "okay";
+			};
+
+			serial at b2000000 {
+			       status = "okay";
+			};
+
+			serial at b2080000 {
+			       status = "okay";
+			};
+
+			serial at b2100000 {
+			       status = "okay";
+			};
+
+			serial at b2180000 {
+			       status = "okay";
+			};
+
+			serial at b2200000 {
+			       status = "okay";
+			};
+
+			wdt at fc880000 {
+			       status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644
index 0000000..dc7fa14
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,75 @@
+/*
+ * DTS file for SPEAr310 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x40000000 0x40000000 0x10000000
+			  0xb0000000 0xb0000000 0x10000000
+			  0xd0000000 0xd0000000 0x30000000>;
+
+		fsmc: flash at 44000000 {
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x44000000 0x1000	/* FSMC Register */
+			       0x40000000 0x0010>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x10000>;
+			st,cle-off = <0x20000>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xb0000000 0xb0000000 0x10000000
+				  0xd0000000 0xd0000000 0x30000000>;
+
+			serial at b2000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2000000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2080000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2080000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2100000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2100000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2180000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2180000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at b2200000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xb2200000 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644
index 0000000..5681a97
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,108 @@
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear320.dtsi"
+
+/ {
+	model = "ST SPEAr300 Evaluation Board";
+	compatible = "st,spear300-evb", "st,spear300";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		clcd at 90000000 {
+			status = "okay";
+		};
+
+		fsmc: flash at 4c000000 {
+			status = "okay";
+		};
+
+		gmac: eth at e0800000 {
+			status = "okay";
+		};
+
+		sdhci at 70000000 {
+			power-gpio = <&gpio0 2 1>;
+			power_always_enb;
+			status = "okay";
+		};
+
+		smi: flash at fc000000 {
+			status = "okay";
+		};
+
+		spi0: spi at d0100000 {
+			status = "okay";
+		};
+
+		spi1: spi at a5000000 {
+			status = "okay";
+		};
+
+		spi2: spi at a6000000 {
+			status = "okay";
+		};
+
+		ehci at e1800000 {
+			status = "okay";
+		};
+
+		ohci at e1900000 {
+			status = "okay";
+		};
+
+		ohci at e2100000 {
+			status = "okay";
+		};
+
+		apb {
+			gpio0: gpio at fc980000 {
+			       status = "okay";
+			};
+
+			i2c0: i2c at d0180000 {
+			       status = "okay";
+			};
+
+			i2c1: i2c at a7000000 {
+			       status = "okay";
+			};
+
+			rtc at fc900000 {
+			       status = "okay";
+			};
+
+			serial at d0000000 {
+			       status = "okay";
+			};
+
+			serial at a3000000 {
+			       status = "okay";
+			};
+
+			serial at a4000000 {
+			       status = "okay";
+			};
+
+			wdt at fc880000 {
+			       status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644
index 0000000..9a0267a
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,90 @@
+/*
+ * DTS file for SPEAr320 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x40000000 0x40000000 0x70000000
+			  0xd0000000 0xd0000000 0x30000000>;
+
+		clcd at 90000000 {
+			compatible = "arm,clcd-pl110", "arm,primecell";
+			reg = <0x90000000 0x1000>;
+			interrupts = <33>;
+			status = "disabled";
+		};
+
+		fsmc: flash at 4c000000 {
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x4c000000 0x1000	/* FSMC Register */
+			       0x50000000 0x0010>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x20000>;
+			st,cle-off = <0x10000>;
+			status = "disabled";
+		};
+
+		sdhci at 70000000 {
+			compatible = "st,sdhci-spear";
+			reg = <0x70000000 0x100>;
+			interrupts = <29>;
+			status = "disabled";
+		};
+
+		spi1: spi at a5000000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0xa5000000 0x1000>;
+			status = "disabled";
+		};
+
+		spi2: spi at a6000000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0xa6000000 0x1000>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xa0000000 0xa0000000 0x10000000
+				  0xd0000000 0xd0000000 0x30000000>;
+
+			i2c1: i2c at a7000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,designware-i2c";
+				reg = <0xa7000000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at a3000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xa3000000 0x1000>;
+				status = "disabled";
+			};
+
+			serial at a4000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xa4000000 0x1000>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644
index 0000000..924a6f6
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,136 @@
+/*
+ * DTS file for all SPEAr3xx SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar at st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&vic>;
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+		vic: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		gmac: eth at e0800000 {
+			compatible = "st,spear600-gmac";
+			reg = <0xe0800000 0x8000>;
+			interrupts = <23 22>;
+			interrupt-names = "macirq", "eth_wake_irq";
+			status = "disabled";
+		};
+
+		smi: flash at fc000000 {
+			compatible = "st,spear600-smi";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xfc000000 0x1000>;
+			interrupts = <9>;
+			status = "disabled";
+		};
+
+		spi0: spi at d0100000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0xd0100000 0x1000>;
+			interrupts = <20>;
+			status = "disabled";
+		};
+
+		ehci at e1800000 {
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe1800000 0x1000>;
+			interrupts = <26>;
+			status = "disabled";
+		};
+
+		ohci at e1900000 {
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe1900000 0x1000>;
+			interrupts = <25>;
+			status = "disabled";
+		};
+
+		ohci at e2100000 {
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe2100000 0x1000>;
+			interrupts = <27>;
+			status = "disabled";
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+			gpio0: gpio at fc980000 {
+				compatible = "arm,pl061", "arm,primecell";
+				reg = <0xfc980000 0x1000>;
+				interrupts = <11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			i2c0: i2c at d0180000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,designware-i2c";
+				reg = <0xd0180000 0x1000>;
+				interrupts = <21>;
+				status = "disabled";
+			};
+
+			rtc at fc900000 {
+				compatible = "st,spear-rtc";
+				reg = <0xfc900000 0x1000>;
+				interrupts = <10>;
+				status = "disabled";
+			};
+
+			serial at d0000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0000000 0x1000>;
+				interrupts = <19>;
+				status = "disabled";
+			};
+
+			wdt at fc880000 {
+				compatible = "arm,sp805", "arm,primecell";
+				reg = <0xfc880000 0x1000>;
+				interrupts = <12>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0..d9fe11c 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,19 @@
 if ARCH_SPEAR3XX
 
 menu "SPEAr3xx Implementations"
-config BOARD_SPEAR300_EVB
-	bool "SPEAr300 Evaluation Board"
-	select MACH_SPEAR300
-	help
-	  Supports ST SPEAr300 Evaluation Board
-
-config BOARD_SPEAR310_EVB
-	bool "SPEAr310 Evaluation Board"
-	select MACH_SPEAR310
-	help
-	  Supports ST SPEAr310 Evaluation Board
-
-config BOARD_SPEAR320_EVB
-	bool "SPEAr320 Evaluation Board"
-	select MACH_SPEAR320
-	help
-	  Supports ST SPEAr320 Evaluation Board
-
-endmenu
-
 config MACH_SPEAR300
-	bool "SPEAr300"
+	bool "SPEAr300 Machine support with Device Tree"
 	help
-	  Supports ST SPEAr300 Machine
+	  Supports ST SPEAr300 machine configured via the device-tree
 
 config MACH_SPEAR310
-	bool "SPEAr310"
+	bool "SPEAr310 Machine support with Device Tree"
 	help
-	  Supports ST SPEAr310 Machine
+	  Supports ST SPEAr310 machine configured via the device-tree
 
 config MACH_SPEAR320
-	bool "SPEAr320"
+	bool "SPEAr320 Machine support with Device Tree"
 	help
-	  Supports ST SPEAr320 Machine
-
+	  Supports ST SPEAr320 machine configured via the device-tree
+endmenu
 endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b248624..17b5d83 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
 #
 
 # common files
-obj-y	+= spear3xx.o clock.o
+obj-$(CONFIG_ARCH_SPEAR3XX)	+= spear3xx.o clock.o
 
 # spear300 specific files
 obj-$(CONFIG_MACH_SPEAR300) += spear300.o
 
-# spear300 boards files
-obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
-
-
 # spear310 specific files
 obj-$(CONFIG_MACH_SPEAR310) += spear310.o
 
-# spear310 boards files
-obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
-
-
 # spear320 specific files
 obj-$(CONFIG_MACH_SPEAR320) += spear320.o
-
-# spear320 boards files
-obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c..d93e217 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
 zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR300)	+= spear300-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR310)	+= spear310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR320)	+= spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 47d4535..9293c14 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of_platform.h>
 #include <asm/mach-types.h>
 #include <plat/clock.h>
 #include <mach/misc_regs.h>
@@ -673,11 +674,11 @@ static struct clk_lookup spear_clk_lookups[] = {
 	CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
 	CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
 	/* clock derived from 32 KHz osc clk */
-	CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
+	CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk),
 	/* clock derived from 24 MHz osc clk */
 	CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
 	CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
-	CLKDEV_INIT("wdt", NULL, &wdt_clk),
+	CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk),
 	/* clock derived from pll1 clk */
 	CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
 	CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
@@ -686,7 +687,7 @@ static struct clk_lookup spear_clk_lookups[] = {
 	CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
 	CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
 	CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
-	CLKDEV_INIT("uart", NULL, &uart_clk),
+	CLKDEV_INIT("d0000000.serial", NULL, &uart_clk),
 	CLKDEV_INIT("firda", NULL, &firda_clk),
 	CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
 	CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
@@ -699,81 +700,95 @@ static struct clk_lookup spear_clk_lookups[] = {
 	CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
 	/* clock derived from ahb clk */
 	CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
-	CLKDEV_INIT("i2c_designware.0", NULL, &i2c_clk),
+	CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
 	CLKDEV_INIT("dma", NULL, &dma_clk),
 	CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
-	CLKDEV_INIT("gmac", NULL, &gmac_clk),
-	CLKDEV_INIT("smi", NULL, &smi_clk),
+	CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
+	CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
 	CLKDEV_INIT("c3", NULL, &c3_clk),
 	/* clock derived from apb clk */
 	CLKDEV_INIT("adc", NULL, &adc_clk),
-	CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
-	CLKDEV_INIT("gpio", NULL, &gpio_clk),
+	CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk),
+	CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk),
 };
 
 /* array of all spear 300 clock lookups */
 #ifdef CONFIG_MACH_SPEAR300
 static struct clk_lookup spear300_clk_lookups[] = {
-	CLKDEV_INIT("clcd", NULL, &clcd_clk),
-	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
-	CLKDEV_INIT("gpio1", NULL, &gpio1_clk),
-	CLKDEV_INIT("keyboard", NULL, &kbd_clk),
-	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
+	CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk),
+	CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk),
+	CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk),
+	CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
 };
+
+void __init spear300_clk_init(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+		clk_register(&spear_clk_lookups[i]);
+
+	for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++)
+		clk_register(&spear300_clk_lookups[i]);
+
+	clk_init();
+}
 #endif
 
 /* array of all spear 310 clock lookups */
 #ifdef CONFIG_MACH_SPEAR310
 static struct clk_lookup spear310_clk_lookups[] = {
-	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
+	CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk),
 	CLKDEV_INIT(NULL, "emi", &emi_clk),
-	CLKDEV_INIT("uart1", NULL, &uart1_clk),
-	CLKDEV_INIT("uart2", NULL, &uart2_clk),
-	CLKDEV_INIT("uart3", NULL, &uart3_clk),
-	CLKDEV_INIT("uart4", NULL, &uart4_clk),
-	CLKDEV_INIT("uart5", NULL, &uart5_clk),
+	CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk),
+	CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk),
+	CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk),
+	CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk),
+	CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk),
 };
+
+void __init spear310_clk_init(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+		clk_register(&spear_clk_lookups[i]);
+
+	for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++)
+		clk_register(&spear310_clk_lookups[i]);
+
+	clk_init();
+}
 #endif
 
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
 static struct clk_lookup spear320_clk_lookups[] = {
-	CLKDEV_INIT("clcd", NULL, &clcd_clk),
-	CLKDEV_INIT("fsmc", NULL, &fsmc_clk),
-	CLKDEV_INIT("i2c_designware.1", NULL, &i2c1_clk),
+	CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk),
+	CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk),
+	CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk),
 	CLKDEV_INIT(NULL, "emi", &emi_clk),
 	CLKDEV_INIT("pwm", NULL, &pwm_clk),
-	CLKDEV_INIT("sdhci", NULL, &sdhci_clk),
+	CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
 	CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
 	CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
-	CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
-	CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
-	CLKDEV_INIT("uart1", NULL, &uart1_clk),
-	CLKDEV_INIT("uart2", NULL, &uart2_clk),
+	CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk),
+	CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk),
+	CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk),
+	CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk),
 };
-#endif
 
-void __init spear3xx_clk_init(void)
+void __init spear320_clk_init(void)
 {
-	int i, cnt;
-	struct clk_lookup *lookups;
-
-	if (machine_is_spear300()) {
-		cnt = ARRAY_SIZE(spear300_clk_lookups);
-		lookups = spear300_clk_lookups;
-	} else if (machine_is_spear310()) {
-		cnt = ARRAY_SIZE(spear310_clk_lookups);
-		lookups = spear310_clk_lookups;
-	} else {
-		cnt = ARRAY_SIZE(spear320_clk_lookups);
-		lookups = spear320_clk_lookups;
-	}
+	int i;
 
 	for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
 		clk_register(&spear_clk_lookups[i]);
 
-	for (i = 0; i < cnt; i++)
-		clk_register(&lookups[i]);
+	for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++)
+		clk_register(&spear320_clk_lookups[i]);
 
 	clk_init();
 }
+#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5..84ee2bb 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -31,16 +31,13 @@
 #define SPEAR_GPT0_CHAN1_IRQ	SPEAR3XX_IRQ_CPU_GPT1_2
 
 /* Add spear3xx family device structure declarations here */
-extern struct amba_device spear3xx_gpio_device;
-extern struct amba_device spear3xx_uart_device;
 extern struct sys_timer spear3xx_timer;
+extern struct pl022_ssp_controller pl022_plat_data;
 
 /* Add spear3xx family function declarations here */
-void __init spear3xx_clk_init(void);
 void __init spear_setup_timer(void);
 void __init spear3xx_map_io(void);
-void __init spear3xx_init_irq(void);
-void __init spear3xx_init(void);
+void __init spear3xx_dt_init_irq(void);
 
 void spear_restart(char, const char *);
 
@@ -99,9 +96,6 @@ extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
 
 /* spear300 declarations */
 #ifdef CONFIG_MACH_SPEAR300
-/* Add spear300 machine device structure declarations here */
-extern struct amba_device spear300_gpio1_device;
-
 /* pad mux modes */
 extern struct pmx_mode spear300_nand_mode;
 extern struct pmx_mode spear300_nor_mode;
@@ -133,16 +127,13 @@ extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
 extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
 extern struct pmx_dev spear300_pmx_gpio1;
 
-/* Add spear300 machine function declarations here */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count);
+/* Add spear300 machine declarations here */
+void __init spear300_clk_init(void);
 
 #endif /* CONFIG_MACH_SPEAR300 */
 
 /* spear310 declarations */
 #ifdef CONFIG_MACH_SPEAR310
-/* Add spear310 machine device structure declarations here */
-
 /* pad mux devices */
 extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
 extern struct pmx_dev spear310_pmx_emi_cs_2_3;
@@ -153,16 +144,13 @@ extern struct pmx_dev spear310_pmx_fsmc;
 extern struct pmx_dev spear310_pmx_rs485_0_1;
 extern struct pmx_dev spear310_pmx_tdm0;
 
-/* Add spear310 machine function declarations here */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count);
+/* Add spear310 machine declarations here */
+void __init spear310_clk_init(void);
 
 #endif /* CONFIG_MACH_SPEAR310 */
 
 /* spear320 declarations */
 #ifdef CONFIG_MACH_SPEAR320
-/* Add spear320 machine device structure declarations here */
-
 /* pad mux modes */
 extern struct pmx_mode spear320_auto_net_smii_mode;
 extern struct pmx_mode spear320_auto_net_mii_mode;
@@ -193,9 +181,8 @@ extern struct pmx_dev spear320_pmx_smii0;
 extern struct pmx_dev spear320_pmx_smii1;
 extern struct pmx_dev spear320_pmx_i2c1;
 
-/* Add spear320 machine function declarations here */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count);
+/* Add spear320 machine declarations here */
+void __init spear320_clk_init(void);
 
 #endif /* CONFIG_MACH_SPEAR320 */
 
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d8..defa374 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -17,7 +17,4 @@
 #include <plat/hardware.h>
 #include <mach/spear.h>
 
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)		(x | 0xF0000000)
-
 #endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd983..8e3900a 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -25,8 +25,9 @@
 
 /* ICM1 - Low speed connection */
 #define SPEAR3XX_ICM1_2_BASE		UL(0xD0000000)
+#define VA_SPEAR3XX_ICM1_2_BASE		UL(0xFD000000)
 #define SPEAR3XX_ICM1_UART_BASE		UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_UART_BASE	IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
+#define VA_SPEAR3XX_ICM1_UART_BASE	(VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
 #define SPEAR3XX_ICM1_ADC_BASE		UL(0xD0080000)
 #define SPEAR3XX_ICM1_SSP_BASE		UL(0xD0100000)
 #define SPEAR3XX_ICM1_I2C_BASE		UL(0xD0180000)
@@ -53,11 +54,11 @@
 #define SPEAR3XX_ICM3_ML1_2_BASE	UL(0xF0000000)
 #define SPEAR3XX_ML1_TMR_BASE		UL(0xF0000000)
 #define SPEAR3XX_ML1_VIC_BASE		UL(0xF1100000)
-#define VA_SPEAR3XX_ML1_VIC_BASE	IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
 
 /* ICM3 - Basic Subsystem */
 #define SPEAR3XX_ICM3_SMEM_BASE		UL(0xF8000000)
 #define SPEAR3XX_ICM3_SMI_CTRL_BASE	UL(0xFC000000)
+#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE	UL(0xFC000000)
 #define SPEAR3XX_ICM3_DMA_BASE		UL(0xFC400000)
 #define SPEAR3XX_ICM3_SDRAM_CTRL_BASE	UL(0xFC600000)
 #define SPEAR3XX_ICM3_TMR0_BASE		UL(0xFC800000)
@@ -65,9 +66,9 @@
 #define SPEAR3XX_ICM3_RTC_BASE		UL(0xFC900000)
 #define SPEAR3XX_ICM3_GPIO_BASE		UL(0xFC980000)
 #define SPEAR3XX_ICM3_SYS_CTRL_BASE	UL(0xFCA00000)
-#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE	IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE	(VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR3XX_ICM3_MISC_REG_BASE	UL(0xFCA80000)
-#define VA_SPEAR3XX_ICM3_MISC_REG_BASE	IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
+#define VA_SPEAR3XX_ICM3_MISC_REG_BASE	(VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
 #define SPEAR3XX_ICM3_TMR1_BASE		UL(0xFCB00000)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index adee72b..c876c6a 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,8 +3,8 @@
  *
  * SPEAr300 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,10 +13,9 @@
 
 #define pr_fmt(fmt) "SPEAr300: " fmt
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
@@ -425,24 +424,35 @@ static struct spear_shirq shirq_ras1 = {
 	},
 };
 
-/* Add spear300 specific devices here */
-/* arm gpio1 device registration */
-static struct pl061_platform_data gpio1_plat_data = {
-	.gpio_base	= 8,
-	.irq_base	= SPEAR300_GPIO1_INT_BASE,
+/* padmux devices to enable */
+static struct pmx_dev *spear300_evb_pmx_devs[] = {
+	/* spear3xx specific devices */
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp_cs,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_mii,
+	&spear3xx_pmx_uart0,
+
+	/* spear300 specific devices */
+	&spear300_pmx_fsmc_2_chips,
+	&spear300_pmx_clcd,
+	&spear300_pmx_telecom_sdhci_4bit,
+	&spear300_pmx_gpio1,
 };
 
-AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
-	{SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
+/* Add SPEAr300 auxdata to pass platform data */
+static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+			&pl022_plat_data),
+	{}
+};
 
-/* spear300 routines */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count)
+static void __init spear300_dt_init(void)
 {
-	int ret = 0;
+	int ret = -EINVAL;
 
-	/* call spear3xx family common init function */
-	spear3xx_init();
+	of_platform_populate(NULL, of_default_bus_match_table,
+			spear300_auxdata_lookup, NULL);
 
 	/* shared irq registration */
 	shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
@@ -452,18 +462,45 @@ void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 			pr_err("Error registering Shared IRQ\n");
 	}
 
-	/* pmx initialization */
-	pmx_driver.mode = pmx_mode;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = pmx_dev_count;
+	if (of_machine_is_compatible("st,spear300-evb")) {
+		/* pmx initialization */
+		pmx_driver.mode = &spear300_photo_frame_mode;
+		pmx_driver.devs = spear300_evb_pmx_devs;
+		pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
+
+		pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
+		if (pmx_driver.base) {
+			ret = pmx_register(&pmx_driver);
+			if (ret)
+				pr_err("padmux: registration failed. err no: %d\n",
+						ret);
+			/* Free Mapping, device selection already done */
+			iounmap(pmx_driver.base);
+		}
 
-	pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
-	if (pmx_driver.base) {
-		ret = pmx_register(&pmx_driver);
 		if (ret)
-			pr_err("padmux: registration failed. err no: %d\n",
-					ret);
-		/* Free Mapping, device selection already done */
-		iounmap(pmx_driver.base);
+			pr_err("Initialization Failed");
 	}
 }
+
+static const char * const spear300_dt_board_compat[] = {
+	"st,spear300",
+	"st,spear300-evb",
+	NULL,
+};
+
+static void __init spear300_map_io(void)
+{
+	spear3xx_map_io();
+	spear300_clk_init();
+}
+
+DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
+	.map_io		=	spear300_map_io,
+	.init_irq	=	spear3xx_dt_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear3xx_timer,
+	.init_machine	=	spear300_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear300_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9..0000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear300_evb.c
- *
- * SPEAr300 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-	/* spear3xx specific devices */
-	&spear3xx_pmx_i2c,
-	&spear3xx_pmx_ssp_cs,
-	&spear3xx_pmx_ssp,
-	&spear3xx_pmx_mii,
-	&spear3xx_pmx_uart0,
-
-	/* spear300 specific devices */
-	&spear300_pmx_fsmc_2_chips,
-	&spear300_pmx_clcd,
-	&spear300_pmx_telecom_sdhci_4bit,
-	&spear300_pmx_gpio1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	/* spear3xx specific devices */
-	&spear3xx_gpio_device,
-	&spear3xx_uart_device,
-
-	/* spear300 specific devices */
-	&spear300_gpio1_device,
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-	/* spear3xx specific devices */
-
-	/* spear300 specific devices */
-};
-
-static void __init spear300_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear300 machine init function */
-	spear300_init(&spear300_photo_frame_mode, pmx_devs,
-			ARRAY_SIZE(pmx_devs));
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear3xx_map_io,
-	.init_irq	=	spear3xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear3xx_timer,
-	.init_machine	=	spear300_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index b7c2876..641fd4c 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,8 +3,8 @@
  *
  * SPEAr310 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,8 +13,11 @@
 
 #define pr_fmt(fmt) "SPEAr310: " fmt
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
@@ -257,17 +260,79 @@ static struct spear_shirq shirq_intrcomm_ras = {
 	},
 };
 
-/* Add spear310 specific devices here */
+/* padmux devices to enable */
+static struct pmx_dev *spear310_evb_pmx_devs[] = {
+	/* spear3xx specific devices */
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_gpio_pin0,
+	&spear3xx_pmx_gpio_pin1,
+	&spear3xx_pmx_gpio_pin2,
+	&spear3xx_pmx_gpio_pin3,
+	&spear3xx_pmx_gpio_pin4,
+	&spear3xx_pmx_gpio_pin5,
+	&spear3xx_pmx_uart0,
+
+	/* spear310 specific devices */
+	&spear310_pmx_emi_cs_0_1_4_5,
+	&spear310_pmx_emi_cs_2_3,
+	&spear310_pmx_uart1,
+	&spear310_pmx_uart2,
+	&spear310_pmx_uart3_4_5,
+	&spear310_pmx_fsmc,
+	&spear310_pmx_rs485_0_1,
+	&spear310_pmx_tdm0,
+};
+
+/* uart devices plat data */
+static struct amba_pl011_data spear310_uart_data[] = {
+	{
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart1_tx",
+		.dma_rx_param = "uart1_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart2_tx",
+		.dma_rx_param = "uart2_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart3_tx",
+		.dma_rx_param = "uart3_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart4_tx",
+		.dma_rx_param = "uart4_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart5_tx",
+		.dma_rx_param = "uart5_rx",
+	},
+};
 
-/* spear310 routines */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count)
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+			&pl022_plat_data),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
+			&spear310_uart_data[0]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
+			&spear310_uart_data[1]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
+			&spear310_uart_data[2]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
+			&spear310_uart_data[3]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
+			&spear310_uart_data[4]),
+	{}
+};
+
+static void __init spear310_dt_init(void)
 {
 	void __iomem *base;
 	int ret = 0;
 
-	/* call spear3xx family common init function */
-	spear3xx_init();
+	of_platform_populate(NULL, of_default_bus_match_table,
+			spear310_auxdata_lookup, NULL);
 
 	/* shared irq registration */
 	base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -297,13 +362,38 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 			pr_err("Error registering Shared IRQ 4\n");
 	}
 
-	/* pmx initialization */
-	pmx_driver.base = base;
-	pmx_driver.mode = pmx_mode;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = pmx_dev_count;
+	if (of_machine_is_compatible("st,spear310-evb")) {
+		/* pmx initialization */
+		pmx_driver.base = base;
+		pmx_driver.mode = NULL;
+		pmx_driver.devs = spear310_evb_pmx_devs;
+		pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs);
 
-	ret = pmx_register(&pmx_driver);
-	if (ret)
-		pr_err("padmux: registration failed. err no: %d\n", ret);
+		ret = pmx_register(&pmx_driver);
+		if (ret)
+			pr_err("padmux: registration failed. err no: %d\n",
+					ret);
+	}
 }
+
+static const char * const spear310_dt_board_compat[] = {
+	"st,spear310",
+	"st,spear310-evb",
+	NULL,
+};
+
+static void __init spear310_map_io(void)
+{
+	spear3xx_map_io();
+	spear310_clk_init();
+}
+
+DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
+	.map_io		=	spear310_map_io,
+	.init_irq	=	spear3xx_dt_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear3xx_timer,
+	.init_machine	=	spear310_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear310_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c499..0000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear310_evb.c
- *
- * SPEAr310 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-	/* spear3xx specific devices */
-	&spear3xx_pmx_i2c,
-	&spear3xx_pmx_ssp,
-	&spear3xx_pmx_gpio_pin0,
-	&spear3xx_pmx_gpio_pin1,
-	&spear3xx_pmx_gpio_pin2,
-	&spear3xx_pmx_gpio_pin3,
-	&spear3xx_pmx_gpio_pin4,
-	&spear3xx_pmx_gpio_pin5,
-	&spear3xx_pmx_uart0,
-
-	/* spear310 specific devices */
-	&spear310_pmx_emi_cs_0_1_4_5,
-	&spear310_pmx_emi_cs_2_3,
-	&spear310_pmx_uart1,
-	&spear310_pmx_uart2,
-	&spear310_pmx_uart3_4_5,
-	&spear310_pmx_fsmc,
-	&spear310_pmx_rs485_0_1,
-	&spear310_pmx_tdm0,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	/* spear3xx specific devices */
-	&spear3xx_gpio_device,
-	&spear3xx_uart_device,
-
-	/* spear310 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-	/* spear3xx specific devices */
-
-	/* spear310 specific devices */
-};
-
-static void __init spear310_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear310 machine init function */
-	spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear3xx_map_io,
-	.init_irq	=	spear3xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear3xx_timer,
-	.init_machine	=	spear310_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 7bd39c0..9c571d0 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,8 +3,8 @@
  *
  * SPEAr320 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,8 +13,12 @@
 
 #define pr_fmt(fmt) "SPEAr320: " fmt
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
@@ -510,17 +514,79 @@ static struct spear_shirq shirq_intrcomm_ras = {
 	},
 };
 
-/* Add spear320 specific devices here */
+/* padmux devices to enable */
+static struct pmx_dev *spear320_evb_pmx_devs[] = {
+	/* spear3xx specific devices */
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_mii,
+	&spear3xx_pmx_uart0,
+
+	/* spear320 specific devices */
+	&spear320_pmx_fsmc,
+	&spear320_pmx_sdhci,
+	&spear320_pmx_i2s,
+	&spear320_pmx_uart1,
+	&spear320_pmx_uart2,
+	&spear320_pmx_can,
+	&spear320_pmx_pwm0,
+	&spear320_pmx_pwm1,
+	&spear320_pmx_pwm2,
+	&spear320_pmx_mii1,
+};
+
+static struct pl022_ssp_controller spear320_ssp_data[] = {
+	{
+		.bus_id = 1,
+		.enable_dma = 1,
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "ssp1_tx",
+		.dma_rx_param = "ssp1_rx",
+		.num_chipselect = 2,
+	}, {
+		.bus_id = 2,
+		.enable_dma = 1,
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "ssp2_tx",
+		.dma_rx_param = "ssp2_rx",
+		.num_chipselect = 2,
+	}
+};
+
+static struct amba_pl011_data spear320_uart_data[] = {
+	{
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart1_tx",
+		.dma_rx_param = "uart1_rx",
+	}, {
+		.dma_filter = pl08x_filter_id,
+		.dma_tx_param = "uart2_tx",
+		.dma_rx_param = "uart2_rx",
+	},
+};
 
-/* spear320 routines */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-		u8 pmx_dev_count)
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+			&pl022_plat_data),
+	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
+			&spear320_ssp_data[0]),
+	OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
+			&spear320_ssp_data[1]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
+			&spear320_uart_data[0]),
+	OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
+			&spear320_uart_data[1]),
+	{}
+};
+
+static void __init spear320_dt_init(void)
 {
 	void __iomem *base;
 	int ret = 0;
 
-	/* call spear3xx family common init function */
-	spear3xx_init();
+	of_platform_populate(NULL, of_default_bus_match_table,
+			spear320_auxdata_lookup, NULL);
 
 	/* shared irq registration */
 	base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -544,13 +610,38 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 			pr_err("Error registering Shared IRQ 4\n");
 	}
 
-	/* pmx initialization */
-	pmx_driver.base = base;
-	pmx_driver.mode = pmx_mode;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = pmx_dev_count;
+	if (of_machine_is_compatible("st,spear320-evb")) {
+		/* pmx initialization */
+		pmx_driver.base = base;
+		pmx_driver.mode = &spear320_auto_net_mii_mode;
+		pmx_driver.devs = spear320_evb_pmx_devs;
+		pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
 
-	ret = pmx_register(&pmx_driver);
-	if (ret)
-		pr_err("padmux: registration failed. err no: %d\n", ret);
+		ret = pmx_register(&pmx_driver);
+		if (ret)
+			pr_err("padmux: registration failed. err no: %d\n",
+					ret);
+	}
 }
+
+static const char * const spear320_dt_board_compat[] = {
+	"st,spear320",
+	"st,spear320-evb",
+	NULL,
+};
+
+static void __init spear320_map_io(void)
+{
+	spear3xx_map_io();
+	spear320_clk_init();
+}
+
+DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
+	.map_io		=	spear320_map_io,
+	.init_irq	=	spear3xx_dt_init_irq,
+	.handle_irq	=	vic_handle_irq,
+	.timer		=	&spear3xx_timer,
+	.init_machine	=	spear320_dt_init,
+	.restart	=	spear_restart,
+	.dt_compat	=	spear320_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334a..0000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear320_evb.c
- *
- * SPEAr320 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-	/* spear3xx specific devices */
-	&spear3xx_pmx_i2c,
-	&spear3xx_pmx_ssp,
-	&spear3xx_pmx_mii,
-	&spear3xx_pmx_uart0,
-
-	/* spear320 specific devices */
-	&spear320_pmx_fsmc,
-	&spear320_pmx_sdhci,
-	&spear320_pmx_i2s,
-	&spear320_pmx_uart1,
-	&spear320_pmx_uart2,
-	&spear320_pmx_can,
-	&spear320_pmx_pwm0,
-	&spear320_pmx_pwm1,
-	&spear320_pmx_pwm2,
-	&spear320_pmx_mii1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	/* spear3xx specific devices */
-	&spear3xx_gpio_device,
-	&spear3xx_uart_device,
-
-	/* spear320 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-	/* spear3xx specific devices */
-
-	/* spear320 specific devices */
-};
-
-static void __init spear320_evb_init(void)
-{
-	unsigned int i;
-
-	/* call spear320 machine init function */
-	spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
-			ARRAY_SIZE(pmx_devs));
-
-	/* Add Platform Devices */
-	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-	/* Add Amba Devices */
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-		amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
-	.atag_offset	=	0x100,
-	.map_io		=	spear3xx_map_io,
-	.init_irq	=	spear3xx_init_irq,
-	.handle_irq	=	vic_handle_irq,
-	.timer		=	&spear3xx_timer,
-	.init_machine	=	spear320_evb_init,
-	.restart	=	spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index a236925..a94d8c1 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,8 +3,8 @@
  *
  * SPEAr3XX machines common source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar at st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar at st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -13,76 +13,14 @@
 
 #define pr_fmt(fmt) "SPEAr3xx: " fmt
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of_irq.h>
 #include <linux/io.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
 #include <mach/generic.h>
 #include <mach/hardware.h>
 
-/* Add spear3xx machines common devices here */
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data = {
-	.gpio_base	= 0,
-	.irq_base	= SPEAR3XX_GPIO_INT_BASE,
-};
-
-AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
-	{SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
-
-/* uart device registration */
-AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
-	{SPEAR3XX_IRQ_UART}, NULL);
-
-/* Do spear3xx familiy common initialization part here */
-void __init spear3xx_init(void)
-{
-	/* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear3xx_init_irq(void)
-{
-	vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
-}
-
-/* Following will create static virtual/physical mappings */
-struct map_desc spear3xx_io_desc[] __initdata = {
-	{
-		.virtual	= VA_SPEAR3XX_ICM1_UART_BASE,
-		.pfn		= __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE
-	}, {
-		.virtual	= VA_SPEAR3XX_ML1_VIC_BASE,
-		.pfn		= __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE
-	}, {
-		.virtual	= VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
-		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE
-	}, {
-		.virtual	= VA_SPEAR3XX_ICM3_MISC_REG_BASE,
-		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE
-	},
-};
-
-/* This will create static memory mapping for selected devices */
-void __init spear3xx_map_io(void)
-{
-	iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
-
-	/* This will initialize clock framework */
-	spear3xx_clk_init();
-}
-
 /* pad multiplexing support */
 /* devices */
 static struct pmx_dev_mode pmx_firda_modes[] = {
@@ -508,6 +446,51 @@ struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
 };
 #endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
 
+/* ssp device registration */
+struct pl022_ssp_controller pl022_plat_data = {
+	.bus_id = 0,
+	.enable_dma = 1,
+	.dma_filter = pl08x_filter_id,
+	.dma_tx_param = "ssp0_tx",
+	.dma_rx_param = "ssp0_rx",
+	/*
+	 * This is number of spi devices that can be connected to spi. There are
+	 * two type of chipselects on which slave devices can work. One is chip
+	 * select provided by spi masters other is controlled through external
+	 * gpio's. We can't use chipselect provided from spi master (because as
+	 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+	 * this number now depends on number of gpios available for spi. each
+	 * slave on each master requires a separate gpio pin.
+	 */
+	.num_chipselect = 2,
+};
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL		VIRTUAL
+ * 0xD0000000		0xFD000000
+ * 0xFC000000		0xFC000000
+ */
+struct map_desc spear3xx_io_desc[] __initdata = {
+	{
+		.virtual	= VA_SPEAR3XX_ICM1_2_BASE,
+		.pfn		= __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
+		.length		= SZ_16M,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	= VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
+		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
+		.length		= SZ_16M,
+		.type		= MT_DEVICE
+	},
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear3xx_map_io(void)
+{
+	iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
+}
+
 static void __init spear3xx_timer_init(void)
 {
 	char pclk_name[] = "pll3_48m_clk";
@@ -538,3 +521,13 @@ static void __init spear3xx_timer_init(void)
 struct sys_timer spear3xx_timer = {
 	.init = spear3xx_timer_init,
 };
+
+static const struct of_device_id vic_of_match[] __initconst = {
+	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ /* Sentinel */ }
+};
+
+void __init spear3xx_dt_init_irq(void)
+{
+	of_irq_init(vic_of_match);
+}
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbc..6c066fc 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -9,9 +9,10 @@ choice
 	default ARCH_SPEAR3XX
 
 config ARCH_SPEAR3XX
-	bool "SPEAr3XX"
+	bool "ST SPEAr3xx with Device Tree"
 	select ARM_VIC
 	select CPU_ARM926T
+	select USE_OF
 	help
 	  Supports for ARM's SPEAR3XX family
 
-- 
1.7.9



From viresh.kumar at st.com  Thu Mar 29 06:41:05 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Thu, 29 Mar 2012 16:11:05 +0530
Subject: [PATCH V3 7/7] SPEAr: Update defconfigs
In-Reply-To: <cover.1333017183.git.viresh.kumar@st.com>
References: <cover.1333017183.git.viresh.kumar@st.com>
Message-ID: <4af7a82d5d794c3004a53c8f8f71a11c1f4117c6.1333017183.git.viresh.kumar@st.com>

Recently device tree support is added for SPEAr3xx & SPEAr6xx and we must
upgrade defconfig for that to get compiled. This patches does it.

There are few more rearrangements done in defconfig automatically, when i run
make savedefconfig.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 arch/arm/configs/spear3xx_defconfig |   52 +++++++++++++++++++++++++++-------
 arch/arm/configs/spear6xx_defconfig |   41 ++++++++++++++++++++++-----
 2 files changed, 74 insertions(+), 19 deletions(-)

diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f..7ed4291 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,67 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
-CONFIG_BOARD_SPEAR300_EVB=y
-CONFIG_BOARD_SPEAR310_EVB=y
-CONFIG_BOARD_SPEAR320_EVB=y
+CONFIG_MACH_SPEAR300=y
+CONFIG_MACH_SPEAR310=y
+CONFIG_MACH_SPEAR320=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
 # CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +73,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -48,6 +80,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e83..cf94bc7 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,58 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
-CONFIG_BOARD_SPEAR600_EVB=y
+CONFIG_BOARD_SPEAR600_DT=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +64,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -44,6 +71,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
-- 
1.7.9



From broonie at opensource.wolfsonmicro.com  Thu Mar 29 07:29:49 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 29 Mar 2012 12:29:49 +0100
Subject: [PATCH] ASoC: fsl: enable ssi clock in probe function
In-Reply-To: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>
References: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120329112949.GM3668@opensource.wolfsonmicro.com>

On Thu, Mar 29, 2012 at 10:53:41AM +0800, Shawn Guo wrote:
> For power saving, most IMX platform initilization code turns off
> modules' clock, and expects driver turn on clock as needed.

Applied, thanks (though checking return codes would be nice).  

Ideally you'd be able to enable the clocks only when needed at runtime
though the power savings would doubtless be very small, pm_runtime
callbacks might be helpful.  Having the clocks present on PowerPC (even
if just dummy) so we don't have the conditional code would also be nice.
-------------- next part --------------
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From linux at arm.linux.org.uk  Thu Mar 29 08:10:01 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 29 Mar 2012 13:10:01 +0100
Subject: arm: mm: fix faulty calculation of area to perform cache operation
In-Reply-To: <002c01cd0d92$14acd5f0$3e0681d0$%cho@samsung.com>
References: <002c01cd0d92$14acd5f0$3e0681d0$%cho@samsung.com>
Message-ID: <20120329121000.GE22414@n2100.arm.linux.org.uk>

On Thu, Mar 29, 2012 at 06:55:32PM +0900, Cho KyongHo wrote:
> In dma_cache_maint_page(), if offset is larger than PAGE_SIZE,
> len becomes PAGE_SIZE - offset. If size is smaller than
> PAGE_SIZE - offset, next calcuation of left cause overflow.

It is invalid for offset to be larger than PAGE_SIZE here.


From sshtylyov at mvista.com  Thu Mar 29 08:28:31 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Thu, 29 Mar 2012 16:28:31 +0400
Subject: [PATCH] ARM: S3C24XX: fix missing common.h in mach-s3c24xx/
In-Reply-To: <1332980074-4614-1-git-send-email-kgene.kim@samsung.com>
References: <1332980074-4614-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <4F74556F.10704@mvista.com>

Hello.

On 29-03-2012 4:14, Kukjin Kim wrote:

> This patch fixes missing mach-s3c24xx/common.h which has been
> lost when regarding s3c24xx directories merged.

> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
> ---
>   arch/arm/mach-s3c24xx/common.h |   23 +++++++++++++++++++++++
>   1 files changed, 23 insertions(+), 0 deletions(-)
>   create mode 100644 arch/arm/mach-s3c24xx/common.h

> diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
> new file mode 100644
> index 0000000..a7cd62f
> --- /dev/null
> +++ b/arch/arm/mach-s3c24xx/common.h
> @@ -0,0 +1,23 @@
> +/*
> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * Common Header for S3C24XX SoCs
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
> +#define __ARCH_ARM_MACH_S3C24XX_COMMON_H
> +
> +#ifdef CONFIG_CPU_S3C2410
> +void s3c2410_restart(char mode, const char *cmd);
> +#endif
> +
> +#ifdef CONFIG_CPU_S3C244X
> +void s3c244x_restart(char mode, const char *cmd);
> +#endif

    Those #ifdef's around function prototypes are not necessary.

> +
> +#endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */

WBR, Sergei


From nicolas.ferre at atmel.com  Thu Mar 29 09:27:22 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:22 +0200
Subject: [PATCH 11/12] USB: ehci-atmel: add needed of.h header file
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <9c773949b61764153d82c9612a228256b535c581.1333026637.git.nicolas.ferre@atmel.com>

Compilation error in case of non-DT configuration without this
of.h header file.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 drivers/usb/host/ehci-atmel.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
index 19f318a..cf14c95 100644
--- a/drivers/usb/host/ehci-atmel.c
+++ b/drivers/usb/host/ehci-atmel.c
@@ -13,6 +13,7 @@
 
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/of_platform.h>
 
 /* interface and function clocks */
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:15 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:15 +0200
Subject: [PATCH 04/12] ARM: at91/dts: USB host vbus is active low
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <44829c6b9071853311b87eaf3b8952fd6c5b8d82.1333026637.git.nicolas.ferre@atmel.com>

Change vbus gpio configuration in .dts files to switch to
active low configuration.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: stable <stable at vger.kernel.org>
---
 arch/arm/boot/dts/at91sam9g25ek.dts    |    4 ++--
 arch/arm/boot/dts/at91sam9m10g45ek.dts |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index ac0dc00..7829a4d 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -37,8 +37,8 @@
 		usb0: ohci at 00600000 {
 			status = "okay";
 			num-ports = <2>;
-			atmel,vbus-gpio = <&pioD 19 0
-					   &pioD 20 0
+			atmel,vbus-gpio = <&pioD 19 1
+					   &pioD 20 1
 					  >;
 		};
 
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index c4c8ae4..6abb571 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -73,8 +73,8 @@
 		usb0: ohci at 00700000 {
 			status = "okay";
 			num-ports = <2>;
-			atmel,vbus-gpio = <&pioD 1 0
-					   &pioD 3 0>;
+			atmel,vbus-gpio = <&pioD 1 1
+					   &pioD 3 1>;
 		};
 
 		usb1: ehci at 00800000 {
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:18 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:18 +0200
Subject: [PATCH 07/12] USB: ohci-at91: coding style modifications with
 one-line ifs
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <ebf89ca2b0cb635d900e5fd3cc350935e41918ea.1333026637.git.nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 drivers/usb/host/ohci-at91.c |   12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index cf9707d..dd58b555 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -327,9 +327,8 @@ static int ohci_at91_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 			dev_dbg(hcd->self.controller,
 				"ClearPortFeature: OVER_CURRENT\n");
 
-			if (wIndex && wIndex <= ARRAY_SIZE(pdata->vbus_pin)) {
+			if (wIndex && wIndex <= ARRAY_SIZE(pdata->vbus_pin))
 				pdata->overcurrent_status[wIndex-1] = 0;
-			}
 
 			goto out;
 
@@ -382,17 +381,14 @@ static int ohci_at91_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 		dev_dbg(hcd->self.controller, "GetPortStatus(%d)\n", wIndex);
 
 		if (wIndex && wIndex <= ARRAY_SIZE(pdata->vbus_pin)) {
-			if (! ohci_at91_usb_get_power(pdata, wIndex-1)) {
+			if (! ohci_at91_usb_get_power(pdata, wIndex-1))
 				*data &= ~cpu_to_le32(RH_PS_PPS);
-			}
 
-			if (pdata->overcurrent_changed[wIndex-1]) {
+			if (pdata->overcurrent_changed[wIndex-1])
 				*data |= cpu_to_le32(RH_PS_OCIC);
-			}
 
-			if (pdata->overcurrent_status[wIndex-1]) {
+			if (pdata->overcurrent_status[wIndex-1])
 				*data |= cpu_to_le32(RH_PS_POCI);
-			}
 		}
 	}
 
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:19 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:19 +0200
Subject: [PATCH 08/12] USB: ohci-at91: trivial return code name change
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <50fc3e3c625bfe22ae8fbf07d9e60df15ef41dd2.1333026637.git.nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 drivers/usb/host/ohci-at91.c |    7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index dd58b555..81c1f3d 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -546,10 +546,9 @@ static int ohci_hcd_at91_drv_probe(struct platform_device *pdev)
 	int			gpio;
 	int			ret;
 
-	i = ohci_at91_of_init(pdev);
-
-	if (i)
-		return i;
+	ret = ohci_at91_of_init(pdev);
+	if (ret)
+		return ret;
 
 	pdata = pdev->dev.platform_data;
 
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:13 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:13 +0200
Subject: [PATCH 02/12] USB: ohci-at91: fix vbus_pin_active_low handling
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <c84380a20a92dc854a1cc0251aca62c08b2eae41.1333026637.git.nicolas.ferre@atmel.com>

The information is not properly taken into account
for {get|set}_power() functions.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: stable <stable at vger.kernel.org>		[3.2+]
---
 drivers/usb/host/ohci-at91.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index db8963f..4d266ae 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -247,7 +247,7 @@ static void ohci_at91_usb_set_power(struct at91_usbh_data *pdata, int port, int
 		return;
 
 	gpio_set_value(pdata->vbus_pin[port],
-		       !pdata->vbus_pin_active_low[port] ^ enable);
+		       pdata->vbus_pin_active_low[port] ^ enable);
 }
 
 static int ohci_at91_usb_get_power(struct at91_usbh_data *pdata, int port)
@@ -259,7 +259,7 @@ static int ohci_at91_usb_get_power(struct at91_usbh_data *pdata, int port)
 		return -EINVAL;
 
 	return gpio_get_value(pdata->vbus_pin[port]) ^
-		!pdata->vbus_pin_active_low[port];
+		pdata->vbus_pin_active_low[port];
 }
 
 /*
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:23 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:23 +0200
Subject: [PATCH 12/12] ARM: at91: fix check of valid GPIO for SPI and USB
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <8849f8f500eeccdf26576228f1c3a98bdc627ecd.1333026637.git.nicolas.ferre@atmel.com>

SPI chip select pins have to be checked by gpio_is_valid().
The USB host overcurrent_pin checking was missing.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/mach-at91/at91sam9260_devices.c |    3 +++
 arch/arm/mach-at91/at91sam9261_devices.c |    3 +++
 arch/arm/mach-at91/at91sam9263_devices.c |    3 +++
 arch/arm/mach-at91/at91sam9g45_devices.c |    5 ++++-
 arch/arm/mach-at91/at91sam9rl_devices.c  |    3 +++
 5 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 7e5651e..5652dde 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -598,6 +598,9 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 		else
 			cs_pin = spi1_standard_cs[devices[i].chip_select];
 
+		if (!gpio_is_valid(cs_pin))
+			continue;
+
 		if (devices[i].bus_num == 0)
 			enable_spi0 = 1;
 		else
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 096da87..4db961a 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -415,6 +415,9 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 		else
 			cs_pin = spi1_standard_cs[devices[i].chip_select];
 
+		if (!gpio_is_valid(cs_pin))
+			continue;
+
 		if (devices[i].bus_num == 0)
 			enable_spi0 = 1;
 		else
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 5cdca89d..32ce589 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -672,6 +672,9 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 		else
 			cs_pin = spi1_standard_cs[devices[i].chip_select];
 
+		if (!gpio_is_valid(cs_pin))
+			continue;
+
 		if (devices[i].bus_num == 0)
 			enable_spi0 = 1;
 		else
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 763deba..9cff8b4 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -133,7 +133,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 
 	/* Enable overcurrent notification */
 	for (i = 0; i < data->ports; i++) {
-		if (data->overcurrent_pin[i])
+		if (gpio_is_valid(data->overcurrent_pin[i]))
 			at91_set_gpio_input(data->overcurrent_pin[i], 1);
 	}
 
@@ -788,6 +788,9 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 		else
 			cs_pin = spi1_standard_cs[devices[i].chip_select];
 
+		if (!gpio_is_valid(cs_pin))
+			continue;
+
 		if (devices[i].bus_num == 0)
 			enable_spi0 = 1;
 		else
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index eda72e8..fe4ae22 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -419,6 +419,9 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 		else
 			cs_pin = spi_standard_cs[devices[i].chip_select];
 
+		if (!gpio_is_valid(cs_pin))
+			continue;
+
 		/* enable chip-select pin */
 		at91_set_gpio_output(cs_pin, 1);
 
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:21 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:21 +0200
Subject: [PATCH 10/12] ARM: at91/NAND DT bindings: add comments
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <eefe2b261313fbebec777c278dde61a397670be5.1333026637.git.nicolas.ferre@atmel.com>

Add comments to NAND "gpios" property to make it clearer.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 .../devicetree/bindings/mtd/atmel-nand.txt         |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index 5903ecf..a200695 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -27,13 +27,13 @@ nand0: nand at 40000000,0 {
 	reg = <0x40000000 0x10000000
 	       0xffffe800 0x200
 	      >;
-	atmel,nand-addr-offset = <21>;
-	atmel,nand-cmd-offset = <22>;
+	atmel,nand-addr-offset = <21>;	/* ale */
+	atmel,nand-cmd-offset = <22>;	/* cle */
 	nand-on-flash-bbt;
 	nand-ecc-mode = "soft";
-	gpios = <&pioC 13 0
-		 &pioC 14 0
-		 0
+	gpios = <&pioC 13 0	/* rdy */
+		 &pioC 14 0 	/* nce */
+		 0		/* cd */
 		>;
 	partition at 0 {
 		...
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:11 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:11 +0200
Subject: [PATCH 00/12] at91: 3.4-rc1 fixes
Message-ID: <cover.1333026637.git.nicolas.ferre@atmel.com>

Here is a bunch of fixes for AT91 that will go on top of material already
included in linus' tree.
Some modifications are related to certain drivers (USB ohci-at91 for instance)
but are touching the core AT91 devices/board files and Device Tree files.
The modification of "vbus_pin_active_low" in particular cannot be separated
from the modification of .dts[i] and devices/board files.

I will have to collect "Acked-by" from USB people on the ohci-at91
modifications (Greg?).

Best regards,

Nicolas Ferre (12):
  ARM: at91/at91sam9x5: add clkdev entries for DMA controllers
  USB: ohci-at91: fix vbus_pin_active_low handling
  ARM: at91/USB host: specify and handle properly vbus_pin_active_low
  ARM: at91/dts: USB host vbus is active low
  USB: ohci-at91: rework and fix initialization
  USB: ohci-at91: change maximum number of ports
  USB: ohci-at91: coding style modifications with one-line ifs
  USB: ohci-at91: trivial return code name change
  ARM: at91/at91sam9x5.dtsi: fix NAND ale/cle in DT file
  ARM: at91/NAND DT bindings: add comments
  USB: ehci-atmel: add needed of.h header file
  ARM: at91: fix check of valid GPIO for SPI and USB

 .../devicetree/bindings/mtd/atmel-nand.txt         |   10 +-
 arch/arm/boot/dts/at91sam9g25ek.dts                |    4 +-
 arch/arm/boot/dts/at91sam9m10g45ek.dts             |    4 +-
 arch/arm/boot/dts/at91sam9x5.dtsi                  |    4 +-
 arch/arm/mach-at91/at91sam9260_devices.c           |    3 +
 arch/arm/mach-at91/at91sam9261_devices.c           |    3 +
 arch/arm/mach-at91/at91sam9263_devices.c           |    6 +-
 arch/arm/mach-at91/at91sam9g45_devices.c           |   11 +-
 arch/arm/mach-at91/at91sam9rl_devices.c            |    3 +
 arch/arm/mach-at91/at91sam9x5.c                    |    2 +
 arch/arm/mach-at91/board-sam9263ek.c               |    1 +
 arch/arm/mach-at91/board-sam9m10g45ek.c            |    1 +
 arch/arm/mach-at91/include/mach/board.h            |   13 +-
 drivers/usb/host/ehci-atmel.c                      |    1 +
 drivers/usb/host/ohci-at91.c                       |  129 ++++++++++----------
 15 files changed, 111 insertions(+), 84 deletions(-)

-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:17 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:17 +0200
Subject: [PATCH 06/12] USB: ohci-at91: change maximum number of ports
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <8072618d667d37cca7a0d8d3ce14e54919c013cc.1333026637.git.nicolas.ferre@atmel.com>

Change number of ports to 3 for newer SoCs. Modify pdata structure
and ohci-at91 code that was dealing with ports information and check
of port indexes.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/mach-at91/include/mach/board.h |   13 +++++++------
 drivers/usb/host/ohci-at91.c            |   22 +++++++++++++---------
 2 files changed, 20 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 544a5d5..49a8211 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -86,14 +86,15 @@ extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *d
 extern void __init at91_add_device_eth(struct macb_platform_data *data);
 
  /* USB Host */
+#define AT91_MAX_USBH_PORTS	3
 struct at91_usbh_data {
-	u8		ports;		/* number of ports on root hub */
-	int		vbus_pin[2];	/* port power-control pin */
-	u8              vbus_pin_active_low[2];
+	int		vbus_pin[AT91_MAX_USBH_PORTS];	/* port power-control pin */
+	int             overcurrent_pin[AT91_MAX_USBH_PORTS];
+	u8		ports;				/* number of ports on root hub */
 	u8              overcurrent_supported;
-	int             overcurrent_pin[2];
-	u8              overcurrent_status[2];
-	u8              overcurrent_changed[2];
+	u8              vbus_pin_active_low[AT91_MAX_USBH_PORTS];
+	u8              overcurrent_status[AT91_MAX_USBH_PORTS];
+	u8              overcurrent_changed[AT91_MAX_USBH_PORTS];
 };
 extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
 extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 1262532..cf9707d 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -240,7 +240,7 @@ ohci_at91_start (struct usb_hcd *hcd)
 
 static void ohci_at91_usb_set_power(struct at91_usbh_data *pdata, int port, int enable)
 {
-	if (port < 0 || port >= 2)
+	if (port < 0 || port >= ARRAY_SIZE(pdata->vbus_pin))
 		return;
 
 	if (!gpio_is_valid(pdata->vbus_pin[port]))
@@ -252,7 +252,7 @@ static void ohci_at91_usb_set_power(struct at91_usbh_data *pdata, int port, int
 
 static int ohci_at91_usb_get_power(struct at91_usbh_data *pdata, int port)
 {
-	if (port < 0 || port >= 2)
+	if (port < 0 || port >= ARRAY_SIZE(pdata->vbus_pin))
 		return -EINVAL;
 
 	if (!gpio_is_valid(pdata->vbus_pin[port]))
@@ -301,7 +301,11 @@ static int ohci_at91_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 	case SetPortFeature:
 		if (wValue == USB_PORT_FEAT_POWER) {
 			dev_dbg(hcd->self.controller, "SetPortFeat: POWER\n");
-			ohci_at91_usb_set_power(pdata, wIndex - 1, 1);
+			if (wIndex && wIndex <= ARRAY_SIZE(pdata->vbus_pin)) {
+				ohci_at91_usb_set_power(pdata, wIndex - 1, 1);
+				ret = 0;
+			}
+
 			goto out;
 		}
 		break;
@@ -312,7 +316,7 @@ static int ohci_at91_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 			dev_dbg(hcd->self.controller,
 				"ClearPortFeature: C_OVER_CURRENT\n");
 
-			if (wIndex == 1 || wIndex == 2) {
+			if (wIndex && wIndex <= ARRAY_SIZE(pdata->vbus_pin)) {
 				pdata->overcurrent_changed[wIndex-1] = 0;
 				pdata->overcurrent_status[wIndex-1] = 0;
 			}
@@ -323,7 +327,7 @@ static int ohci_at91_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 			dev_dbg(hcd->self.controller,
 				"ClearPortFeature: OVER_CURRENT\n");
 
-			if (wIndex == 1 || wIndex == 2) {
+			if (wIndex && wIndex <= ARRAY_SIZE(pdata->vbus_pin)) {
 				pdata->overcurrent_status[wIndex-1] = 0;
 			}
 
@@ -333,7 +337,7 @@ static int ohci_at91_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 			dev_dbg(hcd->self.controller,
 				"ClearPortFeature: POWER\n");
 
-			if (wIndex == 1 || wIndex == 2) {
+			if (wIndex && wIndex <= ARRAY_SIZE(pdata->vbus_pin)) {
 				ohci_at91_usb_set_power(pdata, wIndex - 1, 0);
 				return 0;
 			}
@@ -377,7 +381,7 @@ static int ohci_at91_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 
 		dev_dbg(hcd->self.controller, "GetPortStatus(%d)\n", wIndex);
 
-		if (wIndex == 1 || wIndex == 2) {
+		if (wIndex && wIndex <= ARRAY_SIZE(pdata->vbus_pin)) {
 			if (! ohci_at91_usb_get_power(pdata, wIndex-1)) {
 				*data &= ~cpu_to_le32(RH_PS_PPS);
 			}
@@ -514,7 +518,7 @@ static int __devinit ohci_at91_of_init(struct platform_device *pdev)
 	if (!of_property_read_u32(np, "num-ports", &ports))
 		pdata->ports = ports;
 
-	for (i = 0; i < 2; i++) {
+	for (i = 0; i < ARRAY_SIZE(pdata->vbus_pin); i++) {
 		gpio = of_get_named_gpio_flags(np, "atmel,vbus-gpio", i, &flags);
 		pdata->vbus_pin[i] = gpio;
 		if (!gpio_is_valid(gpio))
@@ -522,7 +526,7 @@ static int __devinit ohci_at91_of_init(struct platform_device *pdev)
 		pdata->vbus_pin_active_low[i] = flags & OF_GPIO_ACTIVE_LOW;
 	}
 
-	for (i = 0; i < 2; i++)
+	for (i = 0; i < ARRAY_SIZE(pdata->overcurrent_pin); i++)
 		pdata->overcurrent_pin[i] =
 			of_get_named_gpio_flags(np, "atmel,oc-gpio", i, &flags);
 
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:12 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:12 +0200
Subject: [PATCH 01/12] ARM: at91/at91sam9x5: add clkdev entries for DMA
 controllers
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <5e980fb93069db1362c29c23534a47d08feb3e2a.1333026637.git.nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/mach-at91/at91sam9x5.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index b6831ee..13c8cae 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -223,6 +223,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
 	CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
 	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
+	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
+	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
 	CLKDEV_CON_ID("pioA", &pioAB_clk),
 	CLKDEV_CON_ID("pioB", &pioAB_clk),
 	CLKDEV_CON_ID("pioC", &pioCD_clk),
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:14 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:14 +0200
Subject: [PATCH 03/12] ARM: at91/USB host: specify and handle properly
 vbus_pin_active_low
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <ce442f466ded5a4c75a0fc15700dc14fe60b91d8.1333026637.git.nicolas.ferre@atmel.com>

Due to an error while handling vbus_pin_active_low in ohci-at91 driver,
the specification of this property was not good in devices/board files.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: stable <stable at vger.kernel.org>         [3.2+]
---
 arch/arm/mach-at91/at91sam9263_devices.c |    3 ++-
 arch/arm/mach-at91/at91sam9g45_devices.c |    6 ++++--
 arch/arm/mach-at91/board-sam9263ek.c     |    1 +
 arch/arm/mach-at91/board-sam9m10g45ek.c  |    1 +
 4 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 53688c4..5cdca89d 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -72,7 +72,8 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
 	/* Enable VBus control for UHP ports */
 	for (i = 0; i < data->ports; i++) {
 		if (gpio_is_valid(data->vbus_pin[i]))
-			at91_set_gpio_output(data->vbus_pin[i], 0);
+			at91_set_gpio_output(data->vbus_pin[i],
+					     data->vbus_pin_active_low[i] ^ 0);
 	}
 
 	/* Enable overcurrent notification */
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 4320b20..763deba 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -127,7 +127,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
 	/* Enable VBus control for UHP ports */
 	for (i = 0; i < data->ports; i++) {
 		if (gpio_is_valid(data->vbus_pin[i]))
-			at91_set_gpio_output(data->vbus_pin[i], 0);
+			at91_set_gpio_output(data->vbus_pin[i],
+					     data->vbus_pin_active_low[i] ^ 0);
 	}
 
 	/* Enable overcurrent notification */
@@ -188,7 +189,8 @@ void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
 	/* Enable VBus control for UHP ports */
 	for (i = 0; i < data->ports; i++) {
 		if (gpio_is_valid(data->vbus_pin[i]))
-			at91_set_gpio_output(data->vbus_pin[i], 0);
+			at91_set_gpio_output(data->vbus_pin[i],
+					     data->vbus_pin_active_low[i] ^ 0);
 	}
 
 	usbh_ehci_data = *data;
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 66f0ddf..2ffe50f 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -74,6 +74,7 @@ static void __init ek_init_early(void)
 static struct at91_usbh_data __initdata ek_usbh_data = {
 	.ports		= 2,
 	.vbus_pin	= { AT91_PIN_PA24, AT91_PIN_PA21 },
+	.vbus_pin_active_low = {1, 1},
 	.overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index e1bea73..c88e908 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -71,6 +71,7 @@ static void __init ek_init_early(void)
 static struct at91_usbh_data __initdata ek_usbh_hs_data = {
 	.ports		= 2,
 	.vbus_pin	= {AT91_PIN_PD1, AT91_PIN_PD3},
+	.vbus_pin_active_low = {1, 1},
 	.overcurrent_pin= {-EINVAL, -EINVAL},
 };
 
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:16 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:16 +0200
Subject: [PATCH 05/12] USB: ohci-at91: rework and fix initialization
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <c75ee9a49a205e74db26aaa9834c3caf1da15b89.1333026637.git.nicolas.ferre@atmel.com>

The DT information are filled in a pdata structure and then passed on
to the usual check code of the probe function. Thus we do not need to
redo the gpio checking and irq configuration in the DT-related code.
On the other hand, we setup GPIO direction in driver for vbus and
overcurrent. It will be useful when moving to pinctrl subsystem.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 drivers/usb/host/ohci-at91.c |   88 ++++++++++++++++++++++--------------------
 1 file changed, 46 insertions(+), 42 deletions(-)

diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 4d266ae..1262532 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -492,7 +492,7 @@ static u64 at91_ohci_dma_mask = DMA_BIT_MASK(32);
 static int __devinit ohci_at91_of_init(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
-	int i, ret, gpio;
+	int i, gpio;
 	enum of_gpio_flags flags;
 	struct at91_usbh_data	*pdata;
 	u32 ports;
@@ -520,42 +520,11 @@ static int __devinit ohci_at91_of_init(struct platform_device *pdev)
 		if (!gpio_is_valid(gpio))
 			continue;
 		pdata->vbus_pin_active_low[i] = flags & OF_GPIO_ACTIVE_LOW;
-		ret = gpio_request(gpio, "ohci_vbus");
-		if (ret) {
-			dev_warn(&pdev->dev, "can't request vbus gpio %d", gpio);
-			continue;
-		}
-		ret = gpio_direction_output(gpio, !(flags & OF_GPIO_ACTIVE_LOW) ^ 1);
-		if (ret)
-			dev_warn(&pdev->dev, "can't put vbus gpio %d as output %d",
-				 !(flags & OF_GPIO_ACTIVE_LOW) ^ 1, gpio);
 	}
 
-	for (i = 0; i < 2; i++) {
-		gpio = of_get_named_gpio_flags(np, "atmel,oc-gpio", i, &flags);
-		pdata->overcurrent_pin[i] = gpio;
-		if (!gpio_is_valid(gpio))
-			continue;
-		ret = gpio_request(gpio, "ohci_overcurrent");
-		if (ret) {
-			dev_err(&pdev->dev, "can't request overcurrent gpio %d", gpio);
-			continue;
-		}
-
-		ret = gpio_direction_input(gpio);
-		if (ret) {
-			dev_err(&pdev->dev, "can't configure overcurrent gpio %d as input", gpio);
-			continue;
-		}
-
-		ret = request_irq(gpio_to_irq(gpio),
-				  ohci_hcd_at91_overcurrent_irq,
-				  IRQF_SHARED, "ohci_overcurrent", pdev);
-		if (ret) {
-			gpio_free(gpio);
-			dev_warn(& pdev->dev, "cannot get GPIO IRQ for overcurrent\n");
-		}
-	}
+	for (i = 0; i < 2; i++)
+		pdata->overcurrent_pin[i] =
+			of_get_named_gpio_flags(np, "atmel,oc-gpio", i, &flags);
 
 	pdev->dev.platform_data = pdata;
 
@@ -574,6 +543,8 @@ static int ohci_hcd_at91_drv_probe(struct platform_device *pdev)
 {
 	struct at91_usbh_data	*pdata;
 	int			i;
+	int			gpio;
+	int			ret;
 
 	i = ohci_at91_of_init(pdev);
 
@@ -586,23 +557,56 @@ static int ohci_hcd_at91_drv_probe(struct platform_device *pdev)
 		for (i = 0; i < ARRAY_SIZE(pdata->vbus_pin); i++) {
 			if (!gpio_is_valid(pdata->vbus_pin[i]))
 				continue;
-			gpio_request(pdata->vbus_pin[i], "ohci_vbus");
+			gpio = pdata->vbus_pin[i];
+
+			ret = gpio_request(gpio, "ohci_vbus");
+			if (ret) {
+				dev_err(&pdev->dev,
+					"can't request vbus gpio %d\n", gpio);
+				continue;
+			}
+			ret = gpio_direction_output(gpio,
+					pdata->vbus_pin_active_low[i] ^ 1);
+			if (ret) {
+				dev_err(&pdev->dev,
+					"can't put vbus gpio %d as output %d\n",
+					gpio, pdata->vbus_pin_active_low[i] ^ 1);
+				gpio_free(gpio);
+				continue;
+			}
+
 			ohci_at91_usb_set_power(pdata, i, 1);
 		}
 
 		for (i = 0; i < ARRAY_SIZE(pdata->overcurrent_pin); i++) {
-			int ret;
-
 			if (!gpio_is_valid(pdata->overcurrent_pin[i]))
 				continue;
-			gpio_request(pdata->overcurrent_pin[i], "ohci_overcurrent");
+			gpio = pdata->overcurrent_pin[i];
+
+			ret = gpio_request(gpio, "ohci_overcurrent");
+			if (ret) {
+				dev_err(&pdev->dev,
+					"can't request overcurrent gpio %d\n",
+					gpio);
+				continue;
+			}
+
+			ret = gpio_direction_input(gpio);
+			if (ret) {
+				dev_err(&pdev->dev,
+					"can't configure overcurrent gpio %d as input\n",
+					gpio);
+				gpio_free(gpio);
+				continue;
+			}
 
-			ret = request_irq(gpio_to_irq(pdata->overcurrent_pin[i]),
+			ret = request_irq(gpio_to_irq(gpio),
 					  ohci_hcd_at91_overcurrent_irq,
 					  IRQF_SHARED, "ohci_overcurrent", pdev);
 			if (ret) {
-				gpio_free(pdata->overcurrent_pin[i]);
-				dev_warn(& pdev->dev, "cannot get GPIO IRQ for overcurrent\n");
+				gpio_free(gpio);
+				dev_err(&pdev->dev,
+					"can't get gpio IRQ for overcurrent\n");
 			}
 		}
 	}
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:27:20 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:27:20 +0200
Subject: [PATCH 09/12] ARM: at91/at91sam9x5.dtsi: fix NAND ale/cle in DT file
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <21ac379005dbf085c26e8ebb2066649dbbe3964c.1333026637.git.nicolas.ferre@atmel.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 arch/arm/boot/dts/at91sam9x5.dtsi |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index c111001..6597177 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -201,8 +201,8 @@
 			      >;
 			atmel,nand-addr-offset = <21>;
 			atmel,nand-cmd-offset = <22>;
-			gpios = <&pioC 8 0
-				 &pioC 14 0
+			gpios = <&pioD 5 0
+				 &pioD 4 0
 				 0
 				>;
 			status = "disabled";
-- 
1.7.9.4



From nicolas.ferre at atmel.com  Thu Mar 29 09:40:05 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 29 Mar 2012 15:40:05 +0200
Subject: [PATCH] tty/serial: atmel_serial: fix RS485 half-duplex problem
In-Reply-To: <20120327202628.GB15798@kroah.com>
References: <20120327202628.GB15798@kroah.com>
Message-ID: <1333028405-10051-1-git-send-email-nicolas.ferre@atmel.com>

From: "Siftar, Gabe" <Gabe.Siftar at getingeusa.com>

On our custom board, we are using RS485 in half-duplex mode on an AT91SAM9G45.
SER_RS485_RX_DURING_TX is not set as we do not want to receive the data we
transmit (our transceiver will receive transmitted data).
Although the current driver attempts to disable and enable the receiver at the
appropriate points, incoming data is still loaded into the receive register
causing our code to receive the very last byte that was sent once the receiver
is enabled.

I ran this by Atmel support and they wrote: "The issue comes from the fact
that you disable the PDC/DMA Reception and not the USART Reception channel. In
your case, the[n] you will still receive data into the USART_RHR register, and
maybe you [h]ave the overrun flag set. So please disable the USART reception
channel."

The following patch should force the driver to enable/disable the receiver via
RXEN/RXDIS fields of the USART control register. It fixed the issue I was
having.

Signed-off-by: Gabe Siftar <gabe.siftar at getingeusa.com>
[nicolas.ferre at atmel.com: slightly modify commit message]
Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
Greg,

Here is an updated version of the patch that you received from Gabe. I have
removed a superfluous tab in empty line, remove commit message non needed parts
and added my "Signed-off-by" line.

Feel free to queue this version for 3.4-rc.

Thanks, best regards,
  Nicolas

 drivers/tty/serial/atmel_serial.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index 10605ec..bc3cece 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -389,6 +389,8 @@ static void atmel_start_rx(struct uart_port *port)
 {
 	UART_PUT_CR(port, ATMEL_US_RSTSTA);  /* reset status and receiver */
 
+	UART_PUT_CR(port, ATMEL_US_RXEN);
+
 	if (atmel_use_dma_rx(port)) {
 		/* enable PDC controller */
 		UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
@@ -404,6 +406,8 @@ static void atmel_start_rx(struct uart_port *port)
  */
 static void atmel_stop_rx(struct uart_port *port)
 {
+	UART_PUT_CR(port, ATMEL_US_RXDIS);
+
 	if (atmel_use_dma_rx(port)) {
 		/* disable PDC receive */
 		UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
-- 
1.7.9.4



From arnd at arndb.de  Thu Mar 29 09:43:37 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 29 Mar 2012 13:43:37 +0000
Subject: [PATCH] ARM: ux500: fix compile error in new timer code
In-Reply-To: <CACRpkdbi3JM_iGmWiV9pF0Pff+p9_4taw1aQOpgzprgrnLFdWQ@mail.gmail.com>
References: <1332931787-27741-1-git-send-email-lee.jones@linaro.org>
 <CACRpkdbi3JM_iGmWiV9pF0Pff+p9_4taw1aQOpgzprgrnLFdWQ@mail.gmail.com>
Message-ID: <201203291343.37298.arnd@arndb.de>

On Wednesday 28 March 2012, Linus Walleij wrote:
> On Wed, Mar 28, 2012 at 12:49 PM, Lee Jones <lee.jones at linaro.org> wrote:
> 
> > This patch fixes the errors below:
> >
> > error: implicit declaration of function ?pr_err?
> > error: implicit declaration of function ?BUG?
> >
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> 
> Acked-by: Linus Walleij <linus.walleij at linaro.org>
> 
> I'll apply and funnel to ARM-SoC when I'm back in Europe unless
> you want to push it to Arnd/Olof directly.

I've applied it now to the fixes branch, as I'm collecting other patches
as well.

	Arnd


From arnd at arndb.de  Thu Mar 29 09:46:45 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 29 Mar 2012 13:46:45 +0000
Subject: [PATCH] drivers/base: fix compiler warning in SoC export driver -
 idr should be ida
In-Reply-To: <201203172116.30154.arnd@arndb.de>
References: <4F6456BD.9080205@linaro.org> <201203172116.30154.arnd@arndb.de>
Message-ID: <201203291346.45328.arnd@arndb.de>

On Saturday 17 March 2012, Arnd Bergmann wrote:
> On Saturday 17 March 2012, Lee Jones wrote:
> > 
> > This fixes:
> >   note: expected ?struct ida *? but argument is of type ?struct idr *?
> >   warning: passing argument 1 of ?ida_pre_get? from incompatible pointer type
> > 
> > Reported-by: Arnd Bergman <arnd at arndb.de>
> > Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> > Signed-off-by: Lee Jones <lee.jones at linaro.org>
> >
> >  drivers/base/soc.c |    2 +-
> 
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> 
> Greg, are you taking this through your tree?

I've applied it to arm-soc/fixes now. Greg, if you have any objections,
tell me before the weekend and I'll take it out again, otherwise I'll
submit it before -rc1.

	Arnd


From tglx at linutronix.de  Thu Mar 29 09:51:36 2012
From: tglx at linutronix.de (Thomas Gleixner)
Date: Thu, 29 Mar 2012 15:51:36 +0200 (CEST)
Subject: [PATCHv2 02/14] X86 & IA64: adapt for dma_map_ops changes
In-Reply-To: <1332855768-32583-3-git-send-email-m.szyprowski@samsung.com>
References: <1332855768-32583-1-git-send-email-m.szyprowski@samsung.com>
 <1332855768-32583-3-git-send-email-m.szyprowski@samsung.com>
Message-ID: <alpine.LFD.2.02.1203291545520.2542@ionos>

On Tue, 27 Mar 2012, Marek Szyprowski wrote:
> From: Andrzej Pietrasiewicz <andrzej.p at samsung.com>
> -static inline void *dma_alloc_coherent(struct device *dev, size_t size,
> -				       dma_addr_t *daddr, gfp_t gfp)
> +#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)

Please make this an inline function.

>  
> +#define dma_alloc_coherent(d,s,h,f)	dma_alloc_attrs(d,s,h,f,NULL)

Inline please.

> -static inline void dma_free_coherent(struct device *dev, size_t size,
> -				     void *vaddr, dma_addr_t bus)
> +#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)

Ditto

Reviewed-by: Thomas Gleixner <tglx at linutronix.de>

Thanks,

	tglx


From b-cousson at ti.com  Thu Mar 29 10:08:00 2012
From: b-cousson at ti.com (Cousson, Benoit)
Date: Thu, 29 Mar 2012 16:08:00 +0200
Subject: [GIT PULL] ARM: OMAP: i2c, gpio, spi,
 regulator and mmc DTS updates
In-Reply-To: <201203150801.13183.arnd@arndb.de>
References: <4F612C29.40608@ti.com> <20120315004638.GW12083@atomide.com>
 <201203150801.13183.arnd@arndb.de>
Message-ID: <4F746CC0.9050507@ti.com>

Hi Arnd and Olof,

On 3/15/2012 9:01 AM, Arnd Bergmann wrote:
> On Thursday 15 March 2012, Tony Lindgren wrote:
>> * Cousson, Benoit<b-cousson at ti.com>  [120314 16:41]:
>>> Hi Tony,
>>>
>>> Here are the remaining DTS patches for 3.4.
>>>
>>> On top of the previous pull request, I just added the MMC DTS since the driver adaptation just got queued.
>>>
>>> It will be still be good to have that for 3.4 if possible, otherwise we will
>>> have a bunch of drivers DT adapted but no DTS file to use them :-(
>>
>> This might be doable as a follow-up patch series at the end
>> of the merge window or at -rc1 when the related driver changes
>> have been merged.
>>
>> Arnd and Olof, what do you guys think?
>
> I'll have to look at the patches more closely, but from the diffstat it definitely
> looks ok for a later merge once the driver is in. If you can rebase the branch on
> top of the mmc tree (or the merge of that tree with whatever else is needed), it
> should give us a bisectable history and I can stick it into a late/* branch right
> away.

FYI, MMC DT adaptation just got merged, I2C, GPIO, SPI, regulator DT 
adaptation were already merged before, so it means that this branch can 
be merged to take advantage of all the DT adapted drivers.

Thanks,
Benoit


From grinberg at compulab.co.il  Thu Mar 29 10:28:48 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Thu, 29 Mar 2012 16:28:48 +0200
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <4F73437B.6070806@windriver.com>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
 <20120328152743.GW3232@opensource.wolfsonmicro.com>
 <4F73356D.5080401@windriver.com>
 <20120328161305.GZ3232@opensource.wolfsonmicro.com>
 <4F73437B.6070806@windriver.com>
Message-ID: <4F7471A0.6070208@compulab.co.il>

On 03/28/12 18:59, Paul Gortmaker wrote:
> On 12-03-28 12:13 PM, Mark Brown wrote:
>> On Wed, Mar 28, 2012 at 11:59:41AM -0400, Paul Gortmaker wrote:
>>> On 12-03-28 11:27 AM, Mark Brown wrote:
>>
>>> static struct platform_device em_x270_gps_userspace_consumer = {
>>>         .name           = "reg-userspace-consumer",
>>>         .id             = 0,
>>
>>> static struct platform_device em_x270_gprs_userspace_consumer = {
>>>         .name           = "reg-userspace-consumer",
>>>         .id             = 1,
>>
>>> Note that the existing names currently don't incorporate the .id
>>> field as a suffix, and so never were unique.
>>
>> No, this is just a basic part of how platform devices work - the device
>> name is always the same and if you've got more than one of them they get
>> different .ids.  dev_name() returns name.id, or just name if id is set
>> to -1 indicating that there's onyl one device of a given type.
> 
> OK, so Igor - can you simply retest the v2 patch, but make the
> two trivial changes:
> 
> -REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer", "vcc gps");
> +REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer.0", "vcc gps");
> 
> -REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer", "vcc gprs");
> +REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer.1", "vcc gprs");

Well, I thought of this solution, but I don't like it, as it makes
the whole thing very fragile and sensitive to the reg-userspace-consumer
platform device registration order and count, isn't it?
(That's why I proposed to use NULL...).

So, Mark, how do you think the above issues can be handled without
putting NULL into the dev_name?

-- 
Regards,
Igor.


From grinberg at compulab.co.il  Thu Mar 29 10:36:11 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Thu, 29 Mar 2012 16:36:11 +0200
Subject: [GIT PULL] pull request from arch-pxa git on fixes branch
In-Reply-To: <CAOesGMgxq-HEeKSPvaW-kTLqNyDJUUmG0OEpockMBNninQL0wQ@mail.gmail.com>
References: <CAN1soZytJ-CxepQAZn5oZ06=ezTQ85O-iC7tUDOeWqi=zpuf8A@mail.gmail.com>
 <4F732D14.3020803@compulab.co.il>
 <CAOesGMgxq-HEeKSPvaW-kTLqNyDJUUmG0OEpockMBNninQL0wQ@mail.gmail.com>
Message-ID: <4F74735B.7060000@compulab.co.il>

On 03/28/12 19:12, Olof Johansson wrote:
> Hi,
> 
> On Wed, Mar 28, 2012 at 8:24 AM, Igor Grinberg <grinberg at compulab.co.il> wrote:
> 
>> Can Paul's patch [1] be included in this or later request?
>>
>> Thanks.
>>
>> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/091750.html
> 
> Yes, Haojian, please add that to the branch (with the proposed fixups)
> as well so we can pick it up and send it in ASAP. Both are broken
> today in Russell's PXA defconfig.
> 
> There is one more failure as well, that I haven't seen a patch posted for:
> 
> arch/arm/mach-pxa/cm-x300.c:716:3: error: unknown field 'dev'
> specified in initializer

Thanks for spotting I will look into this first thing tomorrow morning...
Sorry, I can't do it earlier...


-- 
Regards,
Igor.


From tony at atomide.com  Thu Mar 29 10:41:52 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 29 Mar 2012 07:41:52 -0700
Subject: [GIT PULL] omap fixes for merge window
In-Reply-To: <CAOesGMiKc5Tc2e5X9=gSiFS87JtMWGmmtOLSStWJcO7ayoE6Rg@mail.gmail.com>
References: <20120321180536.GK9859@atomide.com>
 <CAOesGMiKc5Tc2e5X9=gSiFS87JtMWGmmtOLSStWJcO7ayoE6Rg@mail.gmail.com>
Message-ID: <20120329144151.GS9859@atomide.com>

* Olof Johansson <olof at lixom.net> [120328 22:04]:
> Hi Tony,
> 
> On Wed, Mar 21, 2012 at 11:05 AM, Tony Lindgren <tony at atomide.com> wrote:
> > Hi Arnd & Olof,
> >
> > Here's a set of fixes that would be nice to get merged during
> > the merge window before the GPIO changes get merged to avoid
> > boot issues on many omap boards.
> >
> > The changes queued in the GPIO tree require getting rid of
> > OMAP_GPIO_IRQ and use gpio_to_irq() instead. This is needed for
> > dynamically allocated GPIO interrupt ranges.
> 
> Sorry for the slow response on this, we've been focused on getting the
> main pulls going in. I'm about to start a fixes branch now and looked
> at this pull request.
> 
> I replied to one of the original patches in this branch, they need to
> be fixed before they can go in:
> 
> http://marc.info/?l=linux-omap&m=133299716528617&w=2

Thanks, that's a good catch.
 
> Also, that way we can get a clean branch based on current mainline
> without merge conflicts.

Yes will do.

Regards,

Tony


From broonie at opensource.wolfsonmicro.com  Thu Mar 29 10:54:37 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 29 Mar 2012 15:54:37 +0100
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <4F7471A0.6070208@compulab.co.il>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
 <20120328152743.GW3232@opensource.wolfsonmicro.com>
 <4F73356D.5080401@windriver.com>
 <20120328161305.GZ3232@opensource.wolfsonmicro.com>
 <4F73437B.6070806@windriver.com> <4F7471A0.6070208@compulab.co.il>
Message-ID: <20120329145436.GS3668@opensource.wolfsonmicro.com>

On Thu, Mar 29, 2012 at 04:28:48PM +0200, Igor Grinberg wrote:
> On 03/28/12 18:59, Paul Gortmaker wrote:

> >>> static struct platform_device em_x270_gps_userspace_consumer = {
> >>>         .name           = "reg-userspace-consumer",
> >>>         .id             = 0,

> >>> static struct platform_device em_x270_gprs_userspace_consumer = {
> >>>         .name           = "reg-userspace-consumer",
> >>>         .id             = 1,

> > -REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer", "vcc gprs");
> > +REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer.1", "vcc gprs");

> Well, I thought of this solution, but I don't like it, as it makes
> the whole thing very fragile and sensitive to the reg-userspace-consumer
> platform device registration order and count, isn't it?
> (That's why I proposed to use NULL...).

No the platform device numbering should be totally stable for a given
board unless someone deliberately sets out to renumber them - the .ids
are explicitly assigned by the board when it registers the device.

> So, Mark, how do you think the above issues can be handled without
> putting NULL into the dev_name?

It shouldn't be a problem I think.
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From paul.gortmaker at windriver.com  Thu Mar 29 10:55:07 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Thu, 29 Mar 2012 10:55:07 -0400
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <4F7471A0.6070208@compulab.co.il>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
 <20120328152743.GW3232@opensource.wolfsonmicro.com>
 <4F73356D.5080401@windriver.com>
 <20120328161305.GZ3232@opensource.wolfsonmicro.com>
 <4F73437B.6070806@windriver.com> <4F7471A0.6070208@compulab.co.il>
Message-ID: <4F7477CB.5070206@windriver.com>

On 12-03-29 10:28 AM, Igor Grinberg wrote:
> On 03/28/12 18:59, Paul Gortmaker wrote:
>> On 12-03-28 12:13 PM, Mark Brown wrote:
>>> On Wed, Mar 28, 2012 at 11:59:41AM -0400, Paul Gortmaker wrote:
>>>> On 12-03-28 11:27 AM, Mark Brown wrote:
>>>
>>>> static struct platform_device em_x270_gps_userspace_consumer = {
>>>>         .name           = "reg-userspace-consumer",
>>>>         .id             = 0,
>>>
>>>> static struct platform_device em_x270_gprs_userspace_consumer = {
>>>>         .name           = "reg-userspace-consumer",
>>>>         .id             = 1,
>>>
>>>> Note that the existing names currently don't incorporate the .id
>>>> field as a suffix, and so never were unique.
>>>
>>> No, this is just a basic part of how platform devices work - the device
>>> name is always the same and if you've got more than one of them they get
>>> different .ids.  dev_name() returns name.id, or just name if id is set
>>> to -1 indicating that there's onyl one device of a given type.
>>
>> OK, so Igor - can you simply retest the v2 patch, but make the
>> two trivial changes:
>>
>> -REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer", "vcc gps");
>> +REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer.0", "vcc gps");
>>
>> -REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer", "vcc gprs");
>> +REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer.1", "vcc gprs");
> 
> Well, I thought of this solution, but I don't like it, as it makes
> the whole thing very fragile and sensitive to the reg-userspace-consumer
> platform device registration order and count, isn't it?

Why would it be order dependent?  You can see in the above structs
that they explicitly call out an ID value -- it is _not_ chosen at
the time of registration.  So it will always be:

reg-userspace-consumer.0  -->  gps consumer
reg-userspace-consumer.1  -->  gprs consumer

At least that is my (limited) understanding, based on what
Mark was saying.

Paul.
--

> (That's why I proposed to use NULL...).
> 
> So, Mark, how do you think the above issues can be handled without
> putting NULL into the dev_name?
> 


From paul.gortmaker at windriver.com  Thu Mar 29 10:57:08 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Thu, 29 Mar 2012 10:57:08 -0400
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <20120329145436.GS3668@opensource.wolfsonmicro.com>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
 <20120328152743.GW3232@opensource.wolfsonmicro.com>
 <4F73356D.5080401@windriver.com>
 <20120328161305.GZ3232@opensource.wolfsonmicro.com>
 <4F73437B.6070806@windriver.com> <4F7471A0.6070208@compulab.co.il>
 <20120329145436.GS3668@opensource.wolfsonmicro.com>
Message-ID: <4F747844.9000900@windriver.com>

On 12-03-29 10:54 AM, Mark Brown wrote:
> On Thu, Mar 29, 2012 at 04:28:48PM +0200, Igor Grinberg wrote:
>> On 03/28/12 18:59, Paul Gortmaker wrote:
> 
>>>>> static struct platform_device em_x270_gps_userspace_consumer = {
>>>>>         .name           = "reg-userspace-consumer",
>>>>>         .id             = 0,
> 
>>>>> static struct platform_device em_x270_gprs_userspace_consumer = {
>>>>>         .name           = "reg-userspace-consumer",
>>>>>         .id             = 1,
> 
>>> -REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer", "vcc gprs");
>>> +REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer.1", "vcc gprs");
> 
>> Well, I thought of this solution, but I don't like it, as it makes
>> the whole thing very fragile and sensitive to the reg-userspace-consumer
>> platform device registration order and count, isn't it?
>> (That's why I proposed to use NULL...).
> 
> No the platform device numbering should be totally stable for a given
> board unless someone deliberately sets out to renumber them - the .ids
> are explicitly assigned by the board when it registers the device.
> 
>> So, Mark, how do you think the above issues can be handled without
>> putting NULL into the dev_name?
> 
> It shouldn't be a problem I think.

Mark,

Would you like me to send a v3 with the .0 and .1 added, or
are you OK with making that small change to v2 yourself?

Paul.


From jon-hunter at ti.com  Thu Mar 29 11:01:48 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Thu, 29 Mar 2012 10:01:48 -0500
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used
 OMAP4 onwards
In-Reply-To: <79CD15C6BA57404B839C016229A409A83183FC32@DBDE01.ent.ti.com>
References: <1332842311-12308-1-git-send-email-rnayak@ti.com>
 <79CD15C6BA57404B839C016229A409A83183E0CE@DBDE01.ent.ti.com>
 <4F73FD52.60209@ti.com>
 <79CD15C6BA57404B839C016229A409A83183FB9F@DBDE01.ent.ti.com>
 <4F74252A.7060809@ti.com>
 <79CD15C6BA57404B839C016229A409A83183FC32@DBDE01.ent.ti.com>
Message-ID: <4F74795C.1080506@ti.com>

Hi Viabhav,

On 3/29/2012 4:14, Hiremath, Vaibhav wrote:
> On Thu, Mar 29, 2012 at 14:32:34, Nayak, Rajendra wrote:
>> On Thursday 29 March 2012 02:26 PM, Hiremath, Vaibhav wrote:
>>> The point I was trying to make here was, cpu_is_xxx() check will become ugly,
>>> as more and more devices gets added to the list, am33xx being the first one
>>> in omap34xx family.
>>
>> So are there more, other than AM33xx which are cortex A8 based but
>> share the OMAP4 PRCM IP block?
>>
>
> I would say, probably yes.
>
> But, things are so dynamic and you never know how things will shape up by
> the time you freeze the design.

So this begs the question, why does AM33xx return true from 
cpu_is_omap34xx() is the architecture is based upon OMAP4 and not OMAP3?

I understand it is a Cortex-A8 versus Corex-A9, but if the architecture 
is closer to OMAP4, then should it not be classed as OMAP4 and not OMAP3?

Raises another question if we should really have arch_is_omapXXXX and 
not cpu_is_omapXXXX.

Cheers
Jon


From jon-hunter at ti.com  Thu Mar 29 11:03:17 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Thu, 29 Mar 2012 10:03:17 -0500
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used
 OMAP4 onwards
In-Reply-To: <79CD15C6BA57404B839C016229A409A83183FB9F@DBDE01.ent.ti.com>
References: <1332842311-12308-1-git-send-email-rnayak@ti.com>
 <79CD15C6BA57404B839C016229A409A83183E0CE@DBDE01.ent.ti.com>
 <4F73FD52.60209@ti.com>
 <79CD15C6BA57404B839C016229A409A83183FB9F@DBDE01.ent.ti.com>
Message-ID: <4F7479B5.5060401@ti.com>

Hi Viabhav,

On 3/29/2012 3:56, Hiremath, Vaibhav wrote:
> On Thu, Mar 29, 2012 at 11:42:34, Nayak, Rajendra wrote:
>> On Wednesday 28 March 2012 12:02 PM, Hiremath, Vaibhav wrote:
>>> On Tue, Mar 27, 2012 at 15:28:31, Nayak, Rajendra wrote:
>>>> Some functions like _omap4_disable_module() and _omap4_wait_target_disable()
>>>> are (will be) used on all OMAPs OMAP4 and beyond which support module level
>>>> control. Fix the error checks in these functions to return if called on
>>>> any platform pre OMAP4 (i.e OMAP2 and OMAP3) instead of checking for
>>>> !cpu_is_omap44xx(). This avoids having to update the error check with a
>>>> '&&   !cpu_is_omap54xx()' when OMAP5 is introduced and possibly similar updates
>>>> when further OMAP generations are added.
>>>>
>>>
>>> Let me add some flavor here :)
>>>
>>> AM33xx, which has module level control, but falls under OMAP3 family of
>>> devices. cpu_is_omap34xx() is true for AM33xx device and we have to add
>>> check in all these functions. And I am sure we will have many of such
>>> devices in the future.
>>>
>>> Can we use some flag based option here, instead of cpu_is_xxx() check?
>>>
>>
>> The intent of this patch was to make the error handling uniform across
>> all modules control functions in hwmod, and it atleast addresses one
>> problem of having to update these checks every time a new OMAP gets
>> added.
>>
>> The problem that you bring up with AM33xx is regardless of this patch
>> (you would still need to go update every !cpu_is_omap44xx() check)
>
> Indeed, in any of cpu_is_xxx() check implementation, I have to add check
> for cpu_is_am33xx().

I hope we can avoid adding more cpu_is_amXXXX. That should be a last resort.

Jon


From stern at rowland.harvard.edu  Thu Mar 29 11:04:38 2012
From: stern at rowland.harvard.edu (Alan Stern)
Date: Thu, 29 Mar 2012 11:04:38 -0400 (EDT)
Subject: [PATCH 06/12] USB: ohci-at91: change maximum number of ports
In-Reply-To: <8072618d667d37cca7a0d8d3ce14e54919c013cc.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <Pine.LNX.4.44L0.1203291100400.1417-100000@iolanthe.rowland.org>

On Thu, 29 Mar 2012, Nicolas Ferre wrote:

> Change number of ports to 3 for newer SoCs. Modify pdata structure
> and ohci-at91 code that was dealing with ports information and check
> of port indexes.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
> ---
>  arch/arm/mach-at91/include/mach/board.h |   13 +++++++------
>  drivers/usb/host/ohci-at91.c            |   22 +++++++++++++---------
>  2 files changed, 20 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
> index 544a5d5..49a8211 100644
> --- a/arch/arm/mach-at91/include/mach/board.h
> +++ b/arch/arm/mach-at91/include/mach/board.h
> @@ -86,14 +86,15 @@ extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *d
>  extern void __init at91_add_device_eth(struct macb_platform_data *data);
>  
>   /* USB Host */
> +#define AT91_MAX_USBH_PORTS	3
>  struct at91_usbh_data {
> -	u8		ports;		/* number of ports on root hub */
> -	int		vbus_pin[2];	/* port power-control pin */
> -	u8              vbus_pin_active_low[2];
> +	int		vbus_pin[AT91_MAX_USBH_PORTS];	/* port power-control pin */
> +	int             overcurrent_pin[AT91_MAX_USBH_PORTS];
> +	u8		ports;				/* number of ports on root hub */
>  	u8              overcurrent_supported;
> -	int             overcurrent_pin[2];
> -	u8              overcurrent_status[2];
> -	u8              overcurrent_changed[2];
> +	u8              vbus_pin_active_low[AT91_MAX_USBH_PORTS];
> +	u8              overcurrent_status[AT91_MAX_USBH_PORTS];
> +	u8              overcurrent_changed[AT91_MAX_USBH_PORTS];
>  };
>  extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
>  extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
> diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
> index 1262532..cf9707d 100644
> --- a/drivers/usb/host/ohci-at91.c
> +++ b/drivers/usb/host/ohci-at91.c
> @@ -240,7 +240,7 @@ ohci_at91_start (struct usb_hcd *hcd)
>  
>  static void ohci_at91_usb_set_power(struct at91_usbh_data *pdata, int port, int enable)
>  {
> -	if (port < 0 || port >= 2)
> +	if (port < 0 || port >= ARRAY_SIZE(pdata->vbus_pin))

Here and below, it will be a lot clearer to write AT91_MAX_USBH_PORTS 
instead of ARRAY_SIZE(padata->...).

> @@ -301,7 +301,11 @@ static int ohci_at91_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
>  	case SetPortFeature:
>  		if (wValue == USB_PORT_FEAT_POWER) {
>  			dev_dbg(hcd->self.controller, "SetPortFeat: POWER\n");
> -			ohci_at91_usb_set_power(pdata, wIndex - 1, 1);
> +			if (wIndex && wIndex <= ARRAY_SIZE(pdata->vbus_pin)) {
> +				ohci_at91_usb_set_power(pdata, wIndex - 1, 1);

Here and throughout the hub_control routine, things will be a lot 
simpler if you decrement wIndex at the start of the SetPortFeature 
case.  Same for ClearPortFeature and maybe also GetPortStatus.

Alan Stern



From tony at atomide.com  Thu Mar 29 11:11:29 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 29 Mar 2012 08:11:29 -0700
Subject: [PATCH] omap2+: pm: fix compilation break.
In-Reply-To: <1333015762-476-1-git-send-email-govindraj.raja@ti.com>
References: <1333015762-476-1-git-send-email-govindraj.raja@ti.com>
Message-ID: <20120329151128.GT9859@atomide.com>

* Govindraj.R <govindraj.raja at ti.com> [120329 03:12]:
> From: "Govindraj.R" <govindraj.raja at ti.com>
> 
> Fix the compilation break observed on latest mainline.
> 
> Fixes below compilation break:
> 
> arch/arm/mach-omap2/pm.c: In function 'omap_pm_begin':
> arch/arm/mach-omap2/pm.c:239: error: implicit declaration of function 'disable_hlt'
> arch/arm/mach-omap2/pm.c: In function 'omap_pm_end':
> arch/arm/mach-omap2/pm.c:247: error: implicit declaration of function 'enable_hlt'

Care to mention which commit broke the compile?

Regards,

Tony
 
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
> ---
>  arch/arm/mach-omap2/pm.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
> index a7bdec6..70da4f7 100644
> --- a/arch/arm/mach-omap2/pm.c
> +++ b/arch/arm/mach-omap2/pm.c
> @@ -16,6 +16,7 @@
>  #include <linux/opp.h>
>  #include <linux/export.h>
>  #include <linux/suspend.h>
> +#include <asm/system_misc.h>
>  
>  #include <plat/omap-pm.h>
>  #include <plat/omap_device.h>
> -- 
> 1.7.5.4
> 


From broonie at opensource.wolfsonmicro.com  Thu Mar 29 11:11:57 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 29 Mar 2012 16:11:57 +0100
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <4F747844.9000900@windriver.com>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
 <20120328152743.GW3232@opensource.wolfsonmicro.com>
 <4F73356D.5080401@windriver.com>
 <20120328161305.GZ3232@opensource.wolfsonmicro.com>
 <4F73437B.6070806@windriver.com> <4F7471A0.6070208@compulab.co.il>
 <20120329145436.GS3668@opensource.wolfsonmicro.com>
 <4F747844.9000900@windriver.com>
Message-ID: <20120329151157.GT3668@opensource.wolfsonmicro.com>

On Thu, Mar 29, 2012 at 10:57:08AM -0400, Paul Gortmaker wrote:

> Would you like me to send a v3 with the .0 and .1 added, or
> are you OK with making that small change to v2 yourself?

Please resend, makes life easier.  I'm not sure if it's me or Haojin
who will end up applying the change anyway.
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From tony at atomide.com  Thu Mar 29 11:47:06 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 29 Mar 2012 08:47:06 -0700
Subject: [PATCH 2/5] arm: Use the plat_nand default partition parser
In-Reply-To: <201203281113.10684.hartleys@visionengravers.com>
References: <201203281113.10684.hartleys@visionengravers.com>
Message-ID: <20120329154706.GU9859@atomide.com>

* H Hartley Sweeten <hartleys at visionengravers.com> [120328 11:16]:
> Use the default partition parser, cmdlinepart, provided by the plat_nand driver.
> 
> Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <rmallon at gmail.com>
> Cc: Imre Kaloz <kaloz at openwrt.org>
> Cc: Krzysztof Halasa <khc at pm.waw.pl>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Alexander Clouter <alex at digriz.org.uk>
> Cc: Nicolas Pitre <nico at fluxnic.net>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Marek Vasut <marek.vasut at gmail.com>

Acked-by: Tony Lindgren <tony at atomide.com>


From Bill.Randle at aei.com  Thu Mar 29 11:52:51 2012
From: Bill.Randle at aei.com (Randle, Bill)
Date: Thu, 29 Mar 2012 15:52:51 +0000
Subject: i.MX28 die temperature
In-Reply-To: <20120329023718.GC3254@S2101-09.ap.freescale.net>
References: <330B740BA662BF4E8386F534DF556ED819731A@AEDCEXC09.aei.com>
 <20120329023718.GC3254@S2101-09.ap.freescale.net>
Message-ID: <330B740BA662BF4E8386F534DF556ED8196D1D99@AEDCEXC09.aei.com>

On Wednesday, March 28, 2012 7:37 PM Shawn Guo wrote:
> On Wed, Mar 28, 2012 at 03:13:57PM +0000, Randle, Bill wrote:
> > Has anyone developed a driver for reading the die temperature from the i.MX28? I haven't found anything yet in my searching, but didn't want to duplicate effort if someone has something already.
> > 
> The mainline kernel has no support for it, but the release from
> Freescale has.
> 
>   arch/arm/mach-mx28/device.c (battery_data)
>   drivers/power/mxs/ddi_bc_ramp.c
> 
> It'd be nice if you can bring it to mainline.

Thanks for the pointers, Shawn. I'll take a look at the Freescale code.

    -Bill


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From timur at freescale.com  Thu Mar 29 12:01:21 2012
From: timur at freescale.com (Timur Tabi)
Date: Thu, 29 Mar 2012 11:01:21 -0500
Subject: [PATCH] ASoC: fsl: enable ssi clock in probe function
In-Reply-To: <20120329112949.GM3668@opensource.wolfsonmicro.com>
References: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>
 <20120329112949.GM3668@opensource.wolfsonmicro.com>
Message-ID: <4F748751.3020300@freescale.com>

Mark Brown wrote:
> Applied, thanks (though checking return codes would be nice).  

Speaking of return codes, I can't even get ASoC for-3.5 to compile:

/home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c: In function
'soc_bind_dai_link':
/home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c:805:11: error:
'EPROBE_DEFER' undeclared (first use in this function)
/home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c:805:11: note: each
undeclared identifier is reported only once for each function it appears in
/home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c: In function
'soc_check_aux_dev':
/home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c:1346:10: error:
'EPROBE_DEFER' undeclared (first use in this function)
/home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c: In function
'soc_probe_aux_dev':
/home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c:1369:10: error:
'EPROBE_DEFER' undeclared (first use in this function)
/home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c: In function
'soc_check_aux_dev':
/home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c:1347:1: warning:
control reaches end of non-void function



-- 
Timur Tabi
Linux kernel developer at Freescale



From tony at atomide.com  Thu Mar 29 12:03:45 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 29 Mar 2012 09:03:45 -0700
Subject: [PATCH v3 0/4] ARM: OMAP: boards: changes to support dynamic
 irq alloc
In-Reply-To: <1333015317-11866-1-git-send-email-tarun.kanti@ti.com>
References: <1333015317-11866-1-git-send-email-tarun.kanti@ti.com>
Message-ID: <20120329160344.GV9859@atomide.com>

* Tarun Kanti DebBarma <tarun.kanti at ti.com> [120329 03:05]:
> These four patches incorporate changes to OMAP1 and OMAP2 platforms
> board files whereby older references to OMAP_GPIO_IRQ macro are
> now replaced with gpio_to_irq(), thereby getting rid of static
> irq references.

Thanks, I'll take your updated patches 1/4 and 2/4 combined
into one. And I'll use my earlier updated comments to mention
the breaking commits. As 3/4 and 4/4 have not changed, I'll
use the earlier ones with an ack from Dmitry.

Updated combined 1/4 and 2/4 below.

Tony


From: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Date: Thu, 29 Mar 2012 08:41:01 -0700
Subject: [PATCH] ARM: OMAP: boards: Fix OMAP_GPIO_IRQ usage with gpio_to_irq()

The following commits change gpio-omap to use dynamic
IRQ allocation:

25db711 gpio/omap: Fix IRQ handling for SPARSE_IRQ
384ebe1 gpio/omap: Add DT support to GPIO driver

With dynamic allocation of IRQ the usage of OMAP_GPIO_IRQ
is no longer valid. We must be using gpio_to_irq() instead.

Signed-off-by: Tarun Kanti DebBarma <tarun.kanti at ti.com>
[tony at atomide.com: updated comments]
Signed-off-by: Tony Lindgren <tony at atomide.com>

diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 03e0050..3768088 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -244,8 +244,6 @@ static struct resource h2_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -364,11 +362,9 @@ static struct tps65010_board tps_board = {
 static struct i2c_board_info __initdata h2_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("tps65010", 0x48),
-		.irq            = OMAP_GPIO_IRQ(58),
 		.platform_data	= &tps_board,
 	}, {
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(2),
 	},
 };
 
@@ -437,10 +433,14 @@ static void __init h2_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	h2_smc91x_resources[1].start = gpio_to_irq(0);
+	h2_smc91x_resources[1].end = gpio_to_irq(0);
 	platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
 	omap_board_config = h2_config;
 	omap_board_config_size = ARRAY_SIZE(h2_config);
 	omap_serial_init();
+	h2_i2c_board_info[0].irq = gpio_to_irq(58);
+	h2_i2c_board_info[1].irq = gpio_to_irq(2);
 	omap_register_i2c_bus(1, 100, h2_i2c_board_info,
 			      ARRAY_SIZE(h2_i2c_board_info));
 	omap1_usb_init(&h2_usb_config);
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index f304fe2..09e8582 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -246,8 +246,6 @@ static struct resource smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(40),
-		.end	= OMAP_GPIO_IRQ(40),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -337,7 +335,6 @@ static struct spi_board_info h3_spi_board_info[] __initdata = {
 		.modalias	= "tsc2101",
 		.bus_num	= 2,
 		.chip_select	= 0,
-		.irq		= OMAP_GPIO_IRQ(H3_TS_GPIO),
 		.max_speed_hz	= 16000000,
 		/* .platform_data	= &tsc_platform_data, */
 	},
@@ -377,11 +374,9 @@ static struct omap_board_config_kernel h3_config[] __initdata = {
 static struct i2c_board_info __initdata h3_i2c_board_info[] = {
        {
 		I2C_BOARD_INFO("tps65013", 0x48),
-               /* .irq         = OMAP_GPIO_IRQ(??), */
        },
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(14),
 	},
 };
 
@@ -423,12 +418,16 @@ static void __init h3_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	smc91x_resources[1].start = gpio_to_irq(40);
+	smc91x_resources[1].end = gpio_to_irq(40);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
+	h3_spi_board_info[0].irq = gpio_to_irq(H3_TS_GPIO);
 	spi_register_board_info(h3_spi_board_info,
 				ARRAY_SIZE(h3_spi_board_info));
 	omap_board_config = h3_config;
 	omap_board_config_size = ARRAY_SIZE(h3_config);
 	omap_serial_init();
+	h3_i2c_board_info[1].irq = gpio_to_irq(14);
 	omap_register_i2c_bus(1, 100, h3_i2c_board_info,
 			      ARRAY_SIZE(h3_i2c_board_info));
 	omap1_usb_init(&h3_usb_config);
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index fa52d14..797bbd6 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -323,8 +323,6 @@ static struct platform_device gpio_leds_device = {
 
 static struct resource htcpld_resources[] = {
 	[0] = {
-		.start  = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
-		.end    = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
 		.flags  = IORESOURCE_IRQ,
 	},
 };
@@ -453,7 +451,6 @@ static struct spi_board_info __initdata htcherald_spi_board_info[] = {
 	{
 		.modalias		= "ads7846",
 		.platform_data		= &htcherald_ts_platform_data,
-		.irq			= OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS),
 		.max_speed_hz		= 2500000,
 		.bus_num		= 2,
 		.chip_select		= 1,
@@ -581,6 +578,8 @@ static void __init htcherald_init(void)
 	/* Do board initialization before we register all the devices */
 	omap_board_config = htcherald_config;
 	omap_board_config_size = ARRAY_SIZE(htcherald_config);
+	htcpld_resources[0].start = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
+	htcpld_resources[0].end = gpio_to_irq(HTCHERALD_GIRQ_BTNS);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	htcherald_disable_watchdog();
@@ -588,6 +587,7 @@ static void __init htcherald_init(void)
 	htcherald_usb_enable();
 	omap1_usb_init(&htcherald_usb_config);
 
+	htcherald_spi_board_info[0].irq = gpio_to_irq(HTCHERALD_GPIO_TS);
 	spi_register_board_info(htcherald_spi_board_info,
 		ARRAY_SIZE(htcherald_spi_board_info));
 
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 289a6b8..315c021 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -247,8 +247,6 @@ static struct resource innovator1610_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };
@@ -412,6 +410,8 @@ static void __init innovator_init(void)
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
 	if (!cpu_is_omap1510()) {
+		innovator1610_smc91x_resources[1].start = gpio_to_irq(0);
+		innovator1610_smc91x_resources[1].end = gpio_to_irq(0);
 		platform_add_devices(innovator1610_devices, ARRAY_SIZE(innovator1610_devices));
 	}
 #endif
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index abdbdb0..1d87332 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -147,7 +147,6 @@ static struct spi_board_info nokia770_spi_board_info[] __initdata = {
 		.bus_num        = 2,
 		.chip_select    = 0,
 		.max_speed_hz   = 2500000,
-		.irq		= OMAP_GPIO_IRQ(15),
 		.platform_data	= &nokia770_ads7846_platform_data,
 	},
 };
@@ -242,6 +241,7 @@ static void __init omap_nokia770_init(void)
 	omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
 
 	platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
+	nokia770_spi_board_info[1].irq = gpio_to_irq(15);
 	spi_register_board_info(nokia770_spi_board_info,
 				ARRAY_SIZE(nokia770_spi_board_info));
 	omap_serial_init();
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index e2d7ae4..a0c1a1c 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -128,8 +128,6 @@ static struct resource osk5912_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(0),
-		.end	= OMAP_GPIO_IRQ(0),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -146,8 +144,6 @@ static struct platform_device osk5912_smc91x_device = {
 
 static struct resource osk5912_cf_resources[] = {
 	[0] = {
-		.start	= OMAP_GPIO_IRQ(62),
-		.end	= OMAP_GPIO_IRQ(62),
 		.flags	= IORESOURCE_IRQ,
 	},
 };
@@ -239,7 +235,6 @@ static struct tps65010_board tps_board = {
 static struct i2c_board_info __initdata osk_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("tps65010", 0x48),
-		.irq		= OMAP_GPIO_IRQ(OMAP_MPUIO(1)),
 		.platform_data	= &tps_board,
 
 	},
@@ -413,7 +408,6 @@ static struct spi_board_info __initdata mistral_boardinfo[] = { {
 	/* MicroWire (bus 2) CS0 has an ads7846e */
 	.modalias		= "ads7846",
 	.platform_data		= &mistral_ts_info,
-	.irq			= OMAP_GPIO_IRQ(4),
 	.max_speed_hz		= 120000 /* max sample rate at 3V */
 					* 26 /* command + data + overhead */,
 	.bus_num		= 2,
@@ -476,6 +470,7 @@ static void __init osk_mistral_init(void)
 	gpio_direction_input(4);
 	irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
 
+	mistral_boardinfo[0].irq = gpio_to_irq(4);
 	spi_register_board_info(mistral_boardinfo,
 			ARRAY_SIZE(mistral_boardinfo));
 
@@ -547,6 +542,10 @@ static void __init osk_init(void)
 
 	osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
 	osk_flash_resource.end += SZ_32M - 1;
+	osk5912_smc91x_resources[1].start = gpio_to_irq(0);
+	osk5912_smc91x_resources[1].end = gpio_to_irq(0);
+	osk5912_cf_resources[0].start = gpio_to_irq(62);
+	osk5912_cf_resources[0].end = gpio_to_irq(62);
 	platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
 	omap_board_config = osk_config;
 	omap_board_config_size = ARRAY_SIZE(osk_config);
@@ -563,6 +562,7 @@ static void __init osk_init(void)
 		gpio_direction_input(OMAP_MPUIO(1));
 
 	omap_serial_init();
+	osk_i2c_board_info[0].irq = gpio_to_irq(OMAP_MPUIO(1));
 	omap_register_i2c_bus(1, 400, osk_i2c_board_info,
 			      ARRAY_SIZE(osk_i2c_board_info));
 	osk_mistral_init();
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 04efa7e..66e2a74 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -220,7 +220,6 @@ static struct spi_board_info palmte_spi_info[] __initdata = {
 		.modalias	= "tsc2102",
 		.bus_num	= 2,	/* uWire (officially) */
 		.chip_select	= 0,	/* As opposed to 3 */
-		.irq		= OMAP_GPIO_IRQ(PALMTE_PINTDAV_GPIO),
 		.max_speed_hz	= 8000000,
 	},
 };
@@ -257,6 +256,7 @@ static void __init omap_palmte_init(void)
 
 	platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices));
 
+	palmte_spi_info[0].irq = gpio_to_irq(PALMTE_PINTDAV_GPIO);
 	spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
 	palmte_misc_gpio_setup();
 	omap_serial_init();
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index acd1f36..fa9ce9c 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -256,7 +256,6 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
 		/* MicroWire (bus 2) CS0 has an ads7846e */
 		.modalias	= "ads7846",
 		.platform_data	= &palmtt_ts_info,
-		.irq		= OMAP_GPIO_IRQ(6),
 		.max_speed_hz	= 120000	/* max sample rate at 3V */
 					* 26	/* command + data + overhead */,
 		.bus_num	= 2,
@@ -304,6 +303,7 @@ static void __init omap_palmtt_init(void)
 
 	platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices));
 
+	palmtt_boardinfo[0].irq = gpio_to_irq(6);
 	spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
 	omap_serial_init();
 	omap1_usb_init(&palmtt_usb_config);
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index c1cd0f2..b21df2f 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -223,7 +223,6 @@ static struct spi_board_info __initdata palmz71_boardinfo[] = { {
 	/* MicroWire (bus 2) CS0 has an ads7846e */
 	.modalias	= "ads7846",
 	.platform_data	= &palmz71_ts_info,
-	.irq		= OMAP_GPIO_IRQ(PALMZ71_PENIRQ_GPIO),
 	.max_speed_hz	= 120000	/* max sample rate at 3V */
 				* 26	/* command + data + overhead */,
 	.bus_num	= 2,
@@ -319,6 +318,7 @@ omap_palmz71_init(void)
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
+	palmz71_boardinfo[0].irq = gpio_to_irq(PALMZ71_PENIRQ_GPIO);
 	spi_register_board_info(palmz71_boardinfo,
 				ARRAY_SIZE(palmz71_boardinfo));
 	omap1_usb_init(&palmz71_usb_config);
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 659d0f7..37232d0 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -44,7 +44,6 @@
 static struct plat_serial8250_port voiceblue_ports[] = {
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x40000),
-		.irq		= OMAP_GPIO_IRQ(12),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -52,7 +51,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x50000),
-		.irq		= OMAP_GPIO_IRQ(13),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -60,7 +58,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x60000),
-		.irq		= OMAP_GPIO_IRQ(14),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -68,7 +65,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 	},
 	{
 		.mapbase	= (unsigned long)(OMAP_CS1_PHYS + 0x70000),
-		.irq		= OMAP_GPIO_IRQ(15),
 		.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 		.iotype		= UPIO_MEM,
 		.regshift	= 1,
@@ -80,9 +76,6 @@ static struct plat_serial8250_port voiceblue_ports[] = {
 static struct platform_device serial_device = {
 	.name			= "serial8250",
 	.id			= PLAT8250_DEV_PLATFORM1,
-	.dev			= {
-		.platform_data	= voiceblue_ports,
-	},
 };
 
 static int __init ext_uart_init(void)
@@ -90,6 +83,11 @@ static int __init ext_uart_init(void)
 	if (!machine_is_voiceblue())
 		return -ENODEV;
 
+	voiceblue_ports[0].irq = gpio_to_irq(12);
+	voiceblue_ports[1].irq = gpio_to_irq(13);
+	voiceblue_ports[2].irq = gpio_to_irq(14);
+	voiceblue_ports[3].irq = gpio_to_irq(15);
+	serial_device.dev.platform_data = voiceblue_ports;
 	return platform_device_register(&serial_device);
 }
 arch_initcall(ext_uart_init);
@@ -128,8 +126,6 @@ static struct resource voiceblue_smc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(8),
-		.end	= OMAP_GPIO_IRQ(8),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -275,6 +271,8 @@ static void __init voiceblue_init(void)
 	irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
 	irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
 
+	voiceblue_smc91x_resources[1].start = gpio_to_irq(8);
+	voiceblue_smc91x_resources[1].end = gpio_to_irq(8);
 	platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
 	omap_board_config = voiceblue_config;
 	omap_board_config_size = ARRAY_SIZE(voiceblue_config);
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 7370983..5a1b6af 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -230,12 +230,12 @@ static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = {
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2D),
 		.flags = I2C_CLIENT_WAKE,
-		.irq = OMAP_GPIO_IRQ(78),
 	},
 };
 
 static int __init omap2430_i2c_init(void)
 {
+	sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
 	omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
 			ARRAY_SIZE(sdp2430_i2c1_boardinfo));
 	omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 4e90715..a09c699 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -873,7 +873,6 @@ static void __init omap4_sdp4430_wifi_mux_init(void)
 }
 
 static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
 	.board_ref_clock = WL12XX_REFCLOCK_26,
 	.board_tcxo_clock = WL12XX_TCXOCLOCK_26,
 };
@@ -883,6 +882,7 @@ static void __init omap4_sdp4430_wifi_init(void)
 	int ret;
 
 	omap4_sdp4430_wifi_mux_init();
+	omap4_sdp4430_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
 	ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
 	if (ret)
 		pr_err("Error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index ac77382..768ece2 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -136,8 +136,6 @@ static struct resource apollon_smc91x_resources[] = {
 		.flags  = IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
-		.end	= OMAP_GPIO_IRQ(APOLLON_ETHR_GPIO_IRQ),
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };
@@ -341,6 +339,8 @@ static void __init omap_apollon_init(void)
 	 * You have to mux them off in device drivers later on
 	 * if not needed.
 	 */
+	apollon_smc91x_resources[1].start = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
+	apollon_smc91x_resources[1].end = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
 	platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index e873063..87cdb86 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -410,7 +410,6 @@ static struct resource omap_dm9000_resources[] = {
 		.flags		= IORESOURCE_MEM,
 	},
 	[2] = {
-		.start		= OMAP_GPIO_IRQ(OMAP_DM9000_GPIO_IRQ),
 		.flags		= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
 	},
 };
@@ -637,6 +636,7 @@ static void __init devkit8000_init(void)
 	omap_dm9000_init();
 
 	devkit8000_i2c_init();
+	omap_dm9000_resources[2].start = gpio_to_irq(OMAP_DM9000_GPIO_IRQ);
 	platform_add_devices(devkit8000_devices,
 			ARRAY_SIZE(devkit8000_devices));
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 54af800..0bbbabe 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -348,7 +348,6 @@ static struct at24_platform_data m24c01 = {
 static struct i2c_board_info __initdata h4_i2c_board_info[] = {
 	{
 		I2C_BOARD_INFO("isp1301_omap", 0x2d),
-		.irq		= OMAP_GPIO_IRQ(125),
 	},
 	{	/* EEPROM on mainboard */
 		I2C_BOARD_INFO("24c01", 0x52),
@@ -377,6 +376,7 @@ static void __init omap_h4_init(void)
 	 */
 
 	board_mkp_init();
+	h4_i2c_board_info[0].irq = gpio_to_irq(125);
 	i2c_register_board_info(1, h4_i2c_board_info,
 			ARRAY_SIZE(h4_i2c_board_info));
 
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c775bea..20a4743 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -487,7 +487,6 @@ static struct platform_device omap3evm_wlan_regulator = {
 };
 
 struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
 	.board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
 };
 #endif
@@ -623,6 +622,7 @@ static void __init omap3_evm_wl12xx_init(void)
 	int ret;
 
 	/* WL12xx WLAN Init */
+	omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
 	ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 28fc271..4496007 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -199,7 +199,6 @@ static struct platform_device omap_vwlan_device = {
 };
 
 struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
-	.irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
 	/* PANDA ref clock is 38.4 MHz */
 	.board_ref_clock = 2,
 };
@@ -494,6 +493,7 @@ static void __init omap4_panda_init(void)
 		package = OMAP_PACKAGE_CBL;
 	omap4_mux_init(board_mux, NULL, package);
 
+	omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
 	ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 0a66891..2b6db67 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -169,7 +169,6 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
 		.modalias		= "tsc2005",
 		.bus_num		= 1,
 		.chip_select		= 0,
-		.irq			= OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
 		.max_speed_hz		= 6000000,
 		.controller_data	= &tsc2005_mcspi_config,
 		.platform_data		= &tsc2005_pdata,
@@ -1121,6 +1120,8 @@ static void __init rx51_init_tsc2005(void)
 		"tsc2005 reset");
 	if (r >= 0) {
 		tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
+		rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq =
+					gpio_to_irq(RX51_TSC2005_IRQ_GPIO);
 	} else {
 		printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
 		tsc2005_pdata.esd_timeout_ms = 0;
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 369c2eb..1e8540e 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -43,7 +43,6 @@ static inline void __init zoom_init_smsc911x(void)
 static struct plat_serial8250_port serial_platform_data[] = {
 	{
 		.mapbase	= ZOOM_UART_BASE,
-		.irq		= OMAP_GPIO_IRQ(102),
 		.flags		= UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ,
 		.irqflags	= IRQF_SHARED | IRQF_TRIGGER_RISING,
 		.iotype		= UPIO_MEM,
@@ -89,6 +88,8 @@ static inline void __init zoom_init_quaduart(void)
 	if (gpio_request_one(quart_gpio, GPIOF_IN, "TL16CP754C GPIO") < 0)
 		printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n",
 								quart_gpio);
+
+	serial_platform_data[0].irq = gpio_to_irq(102);
 }
 
 static inline int omap_zoom_debugboard_detect(void)
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index c126461..a489f82 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -193,7 +193,6 @@ static struct platform_device omap_vwlan_device = {
 };
 
 static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
-	.irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO),
 	/* ZOOM ref clock is 26 MHz */
 	.board_ref_clock = 1,
 };
@@ -296,7 +295,10 @@ static void enable_board_wakeup_source(void)
 
 void __init zoom_peripherals_init(void)
 {
-	int ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
+	int ret;
+
+	omap_zoom_wlan_data.irq = gpio_to_irq(OMAP_ZOOM_WLAN_IRQ_GPIO);
+	ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
 
 	if (ret)
 		pr_err("error setting wl12xx data: %d\n", ret);
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 2d1d775..9238ce0 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -78,7 +78,7 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
 	ads7846_config.gpio_pendown = gpio_pendown;
 
 	spi_bi->bus_num	= bus_num;
-	spi_bi->irq	= OMAP_GPIO_IRQ(gpio_pendown);
+	spi_bi->irq	= gpio_to_irq(gpio_pendown);
 
 	if (board_pdata)
 		spi_bi->platform_data = board_pdata;


From shawn.guo at linaro.org  Thu Mar 29 12:09:19 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 30 Mar 2012 00:09:19 +0800
Subject: [PATCH] ASoC: fsl: enable ssi clock in probe function
In-Reply-To: <4F748751.3020300@freescale.com>
References: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>
 <20120329112949.GM3668@opensource.wolfsonmicro.com>
 <4F748751.3020300@freescale.com>
Message-ID: <20120329160916.GG19506@S2101-09.ap.freescale.net>

On Thu, Mar 29, 2012 at 11:01:21AM -0500, Timur Tabi wrote:
> Mark Brown wrote:
> > Applied, thanks (though checking return codes would be nice).  
> 
> Speaking of return codes, I can't even get ASoC for-3.5 to compile:
> 
> /home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c: In function
> 'soc_bind_dai_link':
> /home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c:805:11: error:
> 'EPROBE_DEFER' undeclared (first use in this function)
> /home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c:805:11: note: each
> undeclared identifier is reported only once for each function it appears in
> /home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c: In function
> 'soc_check_aux_dev':
> /home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c:1346:10: error:
> 'EPROBE_DEFER' undeclared (first use in this function)
> /home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c: In function
> 'soc_probe_aux_dev':
> /home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c:1369:10: error:
> 'EPROBE_DEFER' undeclared (first use in this function)
> /home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c: In function
> 'soc_check_aux_dev':
> /home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c:1347:1: warning:
> control reaches end of non-void function
> 
Yes.  To build the branch, we have to revert the commit below.

d18b63ab0b04af1bad01e59a96b88fc8cda08752
ASoC: core: Use driver core probe deferral

-- 
Regards,
Shawn


From timur at freescale.com  Thu Mar 29 12:23:42 2012
From: timur at freescale.com (Timur Tabi)
Date: Thu, 29 Mar 2012 11:23:42 -0500
Subject: [PATCH] ASoC: fsl: enable ssi clock in probe function
In-Reply-To: <20120329160916.GG19506@S2101-09.ap.freescale.net>
References: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>
 <20120329112949.GM3668@opensource.wolfsonmicro.com>
 <4F748751.3020300@freescale.com>
 <20120329160916.GG19506@S2101-09.ap.freescale.net>
Message-ID: <4F748C8E.1010702@freescale.com>

Shawn Guo wrote:
> d18b63ab0b04af1bad01e59a96b88fc8cda08752
> ASoC: core: Use driver core probe deferral

That fixed it, but the SHA in my repository is
97883ef0a8f61fbd5fb8242980f6998290d1dd95

Anyway, I just want to say that for-3.5 still works on PowerPC.

I do have one question though.  I don't know much about the clock layer.
When you do this:

	ssi_private->clk = clk_get(&pdev->dev, NULL);

What clock are you getting?

-- 
Timur Tabi
Linux kernel developer at Freescale



From hartleys at visionengravers.com  Thu Mar 29 12:26:41 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Thu, 29 Mar 2012 11:26:41 -0500
Subject: [PATCH 2/3] ep93xx: IDE driver platform support code
In-Reply-To: <4F741B07.7040107@metasoft.pl>
References: <4F7418E7.4060500@metasoft.pl> <4F741B07.7040107@metasoft.pl>
Message-ID: <ADE657CA350FB648AAC2C43247A983F00206970255B6@AUSP01VMBX24.collaborationhost.net>

On Thursday, March 29, 2012 1:19 AM, Rafal Prylowski wrote:
> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
> Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <ryan at bluewatersys.com>
>
> ---
>  arch/arm/mach-ep93xx/core.c                  |   36 +++++++++++++++++
>  arch/arm/mach-ep93xx/include/mach/platform.h |    1
>  arch/arm/mach-ep93xx/soc.h                   |    1
>  3 files changed, 38 insertions(+)
>
> Index: linux-2.6/arch/arm/mach-ep93xx/soc.h
> ===================================================================
> --- linux-2.6.orig/arch/arm/mach-ep93xx/soc.h
> +++ linux-2.6/arch/arm/mach-ep93xx/soc.h
> @@ -69,6 +69,7 @@
>  
>  #define EP93XX_BOOT_ROM_BASE		EP93XX_AHB_IOMEM(0x00090000)
>  
> +#define EP93XX_IDE_PHYS_BASE		EP93XX_AHB_PHYS(0x000a0000)
>  #define EP93XX_IDE_BASE			EP93XX_AHB_IOMEM(0x000a0000)
>  
>  #define EP93XX_VIC1_BASE		EP93XX_AHB_IOMEM(0x000b0000)
> Index: linux-2.6/arch/arm/mach-ep93xx/core.c
> ===================================================================
> --- linux-2.6.orig/arch/arm/mach-ep93xx/core.c
> +++ linux-2.6/arch/arm/mach-ep93xx/core.c
> @@ -868,6 +868,42 @@ static struct platform_device ep93xx_wdt
>  	.resource	= ep93xx_wdt_resources,
>  };
>  
> +/*************************************************************************
> + * EP93xx IDE
> + *************************************************************************/
> +static struct resource ep93xx_ide_resources[] = {
> +	[0] = {
> +		.start	= EP93XX_IDE_PHYS_BASE,
> +		.end	= EP93XX_IDE_PHYS_BASE + 0xffff,
> +		.flags	= IORESOURCE_MEM,
> +	},
> +	[1] = {
> +		.start	= IRQ_EP93XX_EXT3,
> +		.end	= IRQ_EP93XX_EXT3,
> +		.flags	= IORESOURCE_IRQ,
> +	},
> +};

Please use the DEFINE_RES_* macros.
Also, the last register in the IDE interface is at offset 0x34, so something like this:

static struct resource ep93xx_ide_resources[] = {
	DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38),
	DEFINE_RES_IRQ(IRQ_EP93XX_EXT3),
};

> +static struct platform_device ep93xx_ide_device = {
> +	.name		= "ep93xx-ide",
> +	.id		= -1,
> +	.dev		= {
> +		.dma_mask		= &ep93xx_ide_device.dev.coherent_dma_mask,
> +		.coherent_dma_mask	= DMA_BIT_MASK(32),
> +	},
> +	.num_resources	= ARRAY_SIZE(ep93xx_ide_resources),
> +	.resource	= ep93xx_ide_resources,
> +};
> +
> +void __init ep93xx_register_ide(void)
> +{
> +	/* GPIO ports E, G and H used by IDE */
> +	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
> +				 EP93XX_SYSCON_DEVCFG_GONIDE |
> +				 EP93XX_SYSCON_DEVCFG_HONIDE);
> +	platform_device_register(&ep93xx_ide_device);
> +}

Please create ep93xx_ide_acquire_gpio and ep93xx_ide_acquire_gpio functions
to set/clear the necessary SYSCON bits during the probe/remove of the ide driver.

This should also address your concern mentioned in PATCH 0/3 about making sure
the pin muxing is correct when the driver is loaded.

The *_acquire_gpio function should also gpio_request  the pins before setting the
SYSCON bits. That way if any of the pins are unavailable the driver will not load. Make
sure to gpio_free the pins in the *_release_gpio function.  Look at how the keypad
is handled for an example.

> +
>  void __init ep93xx_init_devices(void)
>  {
>  	/* Disallow access to MaverickCrunch initially */
> Index: linux-2.6/arch/arm/mach-ep93xx/include/mach/platform.h
> ===================================================================
> --- linux-2.6.orig/arch/arm/mach-ep93xx/include/mach/platform.h
> +++ linux-2.6/arch/arm/mach-ep93xx/include/mach/platform.h
> @@ -48,6 +48,7 @@ void ep93xx_register_i2s(void);
>  int ep93xx_i2s_acquire(void);
>  void ep93xx_i2s_release(void);
>  void ep93xx_register_ac97(void);
> +void ep93xx_register_ide(void);
>  
>  void ep93xx_init_devices(void);
>  extern struct sys_timer ep93xx_timer;

Regards,
Hartley



From broonie at opensource.wolfsonmicro.com  Thu Mar 29 12:30:06 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 29 Mar 2012 17:30:06 +0100
Subject: [PATCH] ASoC: fsl: enable ssi clock in probe function
In-Reply-To: <4F748751.3020300@freescale.com>
References: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>
 <20120329112949.GM3668@opensource.wolfsonmicro.com>
 <4F748751.3020300@freescale.com>
Message-ID: <20120329163005.GV3668@opensource.wolfsonmicro.com>

On Thu, Mar 29, 2012 at 11:01:21AM -0500, Timur Tabi wrote:
> Mark Brown wrote:
> > Applied, thanks (though checking return codes would be nice).  

> Speaking of return codes, I can't even get ASoC for-3.5 to compile:

> /home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c: In function
> 'soc_bind_dai_link':
> /home/b04825/git/linux.ssi-clk/sound/soc/soc-core.c:805:11: error:
> 'EPROBE_DEFER' undeclared (first use in this function)

It only works on top of Linus' tree, I'll be rebasing it once -rc1 comes
out.
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From broonie at opensource.wolfsonmicro.com  Thu Mar 29 12:30:59 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 29 Mar 2012 17:30:59 +0100
Subject: [PATCH] ASoC: fsl: enable ssi clock in probe function
In-Reply-To: <4F748C8E.1010702@freescale.com>
References: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>
 <20120329112949.GM3668@opensource.wolfsonmicro.com>
 <4F748751.3020300@freescale.com>
 <20120329160916.GG19506@S2101-09.ap.freescale.net>
 <4F748C8E.1010702@freescale.com>
Message-ID: <20120329163059.GW3668@opensource.wolfsonmicro.com>

On Thu, Mar 29, 2012 at 11:23:42AM -0500, Timur Tabi wrote:

> I do have one question though.  I don't know much about the clock layer.
> When you do this:

> 	ssi_private->clk = clk_get(&pdev->dev, NULL);

> What clock are you getting?

The default clock - personally I much prefer always naming the clocks
even if there's one of them but more people seem to prefer this style.
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From hartleys at visionengravers.com  Thu Mar 29 12:32:28 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Thu, 29 Mar 2012 11:32:28 -0500
Subject: [PATCH 3/3] ep93xx: Add IDE support to edb93xx boards
In-Reply-To: <4F741B3F.4000507@metasoft.pl>
References: <4F7418E7.4060500@metasoft.pl> <4F741B3F.4000507@metasoft.pl>
Message-ID: <ADE657CA350FB648AAC2C43247A983F00206970255C3@AUSP01VMBX24.collaborationhost.net>

On Thursday, March 29, 2012 1:20 AM, Rafal Prylowski wrote:
> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
> Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <ryan at bluewatersys.com>
>
> ---
>  arch/arm/mach-ep93xx/edb93xx.c |   23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> Index: linux-2.6/arch/arm/mach-ep93xx/edb93xx.c
> ===================================================================
> --- linux-2.6.orig/arch/arm/mach-ep93xx/edb93xx.c
> +++ linux-2.6/arch/arm/mach-ep93xx/edb93xx.c
> @@ -233,6 +233,28 @@ static void __init edb93xx_register_fb(v
>  }
>  
>  
> +/*************************************************************************
> + * EDB93xx IDE
> + *************************************************************************/
> +static int __init edb93xx_has_ide(void)
> +{
> +	/*
> +	 * Although EDB9312 and EDB9315 do have IDE capability, they have
> +	 * INTRQ line wired as pull-up, which makes using IDE interface
> +	 * problematic.
> +	 */
> +	return machine_is_edb9315a();

Allow the driver to be loaded on the EDB9312 and EDB9315 but leave the comment.
If a use of these boards wishes to use the IDE they could remove the pull-up and add
a pull-down to their board.

> +}
> +
> +static void __init edb93xx_register_ide(void)
> +{
> +	if (!edb93xx_has_ide())
> +		return;
> +
> +	ep93xx_register_ide();
> +}
> +
> +
>  static void __init edb93xx_init_machine(void)
>  {
>  	ep93xx_init_devices();
> @@ -243,6 +265,7 @@ static void __init edb93xx_init_machine(
>  	edb93xx_register_i2s();
>  	edb93xx_register_pwm();
>  	edb93xx_register_fb();
> +	edb93xx_register_ide();
>  }

Regards,
Hartley

 


From tony at atomide.com  Thu Mar 29 12:33:10 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 29 Mar 2012 09:33:10 -0700
Subject: [PATCH] omap2+: pm: fix compilation break.
In-Reply-To: <20120329151128.GT9859@atomide.com>
References: <1333015762-476-1-git-send-email-govindraj.raja@ti.com>
 <20120329151128.GT9859@atomide.com>
Message-ID: <20120329163309.GW9859@atomide.com>

* Tony Lindgren <tony at atomide.com> [120329 08:14]:
> * Govindraj.R <govindraj.raja at ti.com> [120329 03:12]:
> > From: "Govindraj.R" <govindraj.raja at ti.com>
> > 
> > Fix the compilation break observed on latest mainline.
> > 
> > Fixes below compilation break:
> > 
> > arch/arm/mach-omap2/pm.c: In function 'omap_pm_begin':
> > arch/arm/mach-omap2/pm.c:239: error: implicit declaration of function 'disable_hlt'
> > arch/arm/mach-omap2/pm.c: In function 'omap_pm_end':
> > arch/arm/mach-omap2/pm.c:247: error: implicit declaration of function 'enable_hlt'
> 
> Care to mention which commit broke the compile?

Seems like it was 9f97da78 (Disintegrate asm/system.h for ARM),
and also needs to be fixed for omap1 too. Using the updated
patch below.

Tony


From: Govindraj.R <govindraj.raja at ti.com>
Date: Thu, 29 Mar 2012 09:30:28 -0700
Subject: [PATCH] ARM: OMAP: pm: fix compilation break
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Fix the compilation break observed on latest mainline caused
by 9f97da78 (Disintegrate asm/system.h for ARM):

arch/arm/mach-omap1/pm.c: In function ?omap_pm_prepare?:
arch/arm/mach-omap1/pm.c:587: error: implicit declaration of function ?disable_hlt?
arch/arm/mach-omap1/pm.c: In function ?omap_pm_finish?:
arch/arm/mach-omap1/pm.c:624: error: implicit declaration of function ?enable_hlt?
arch/arm/mach-omap1/pm.c: In function ?omap_pm_init?:
arch/arm/mach-omap1/pm.c:681: error: ?arm_pm_idle? undeclared (first use in this function)
...

arch/arm/mach-omap2/pm.c: In function 'omap_pm_begin':
arch/arm/mach-omap2/pm.c:239: error: implicit declaration of function 'disable_hlt'
arch/arm/mach-omap2/pm.c: In function 'omap_pm_end':
arch/arm/mach-omap2/pm.c:247: error: implicit declaration of function 'enable_hlt'

Cc: Kevin Hilman <khilman at ti.com>
Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
[tony at atomide.com: updated to fix omap1 too]
Signed-off-by: Tony Lindgren <tony at atomide.com>

diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 306beac..f66c329 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -44,6 +44,7 @@
 #include <linux/io.h>
 #include <linux/atomic.h>
 
+#include <asm/system_misc.h>
 #include <asm/irq.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index a7bdec6..d0c1c96 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -17,6 +17,8 @@
 #include <linux/export.h>
 #include <linux/suspend.h>
 
+#include <asm/system_misc.h>
+
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>
 #include "common.h"


From viresh.linux at gmail.com  Thu Mar 29 12:34:15 2012
From: viresh.linux at gmail.com (viresh kumar)
Date: Thu, 29 Mar 2012 22:04:15 +0530
Subject: [RFC] pinctrl: Replace list_groups() with get_groups_count()
Message-ID: <CAOh2x==LTHPM+O9LXVFVdX2NfzKs2bttiYLm8VcL6qLXKrUMBg@mail.gmail.com>

Most of the SoC drivers implement list_*() routines for pinctrl, pinmux,
pinconf, etc, And these routines continue returning zero until the second
argument is greater than total count of available groups, function, etc.

I will take struct pinctrl_ops as an example to elaborate my concern/doubts.

There are few concerns here:
- list_groups() is called multiple times. If the purpose of this routine is to
  only check the number of groups available, then why not remove it and create
  another routine which returns number of total groups. Over which, we can run a
  simple loop.
- All client drivers have checks in their ops routines to check the range of
  groups, which is just not required if we pass the correct number to pinctrl
  framework. Because these ops are going to be called via pinctrl, and we can
  trust on it and place these range checkers there only to make SoC drivers
  simple.

I just wanted to have different views about my concerns/idea before i start
coding. If this idea looks fine, i would do this change across pinmux framework.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 include/linux/pinctrl/pinctrl.h |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 4e9f078..740fb99 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -64,9 +64,7 @@ struct pinctrl_gpio_range {
 /**
  * struct pinctrl_ops - global pin control operations, to be implemented by
  * pin controller drivers.
- * @list_groups: list the number of selectable named groups available
- *	in this pinmux driver, the core will begin on 0 and call this
- *	repeatedly as long as it returns >= 0 to enumerate the groups
+ * @get_group_count: Returns the count of total number of groups registered.
  * @get_group_name: return the group name of the pin group
  * @get_group_pins: return an array of pins corresponding to a certain
  *	group selector @pins, and the size of the array in @num_pins
@@ -74,7 +72,7 @@ struct pinctrl_gpio_range {
  *	info for a certain pin in debugfs
  */
 struct pinctrl_ops {
-	int (*list_groups) (struct pinctrl_dev *pctldev, unsigned selector);
+	int (*get_group_count) (struct pinctrl_dev *pctldev);
 	const char *(*get_group_name) (struct pinctrl_dev *pctldev,
 				       unsigned selector);
 	int (*get_group_pins) (struct pinctrl_dev *pctldev,
-- 
1.7.9


From khilman at ti.com  Thu Mar 29 12:55:37 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 29 Mar 2012 09:55:37 -0700
Subject: [PATCH] omap2+: pm: fix compilation break.
In-Reply-To: <20120329163309.GW9859@atomide.com> (Tony Lindgren's message of
 "Thu, 29 Mar 2012 09:33:10 -0700")
References: <1333015762-476-1-git-send-email-govindraj.raja@ti.com>
 <20120329151128.GT9859@atomide.com>
 <20120329163309.GW9859@atomide.com>
Message-ID: <87aa2zmjna.fsf@ti.com>

Tony Lindgren <tony at atomide.com> writes:

> * Tony Lindgren <tony at atomide.com> [120329 08:14]:
>> * Govindraj.R <govindraj.raja at ti.com> [120329 03:12]:
>> > From: "Govindraj.R" <govindraj.raja at ti.com>
>> > 
>> > Fix the compilation break observed on latest mainline.
>> > 
>> > Fixes below compilation break:
>> > 
>> > arch/arm/mach-omap2/pm.c: In function 'omap_pm_begin':
>> > arch/arm/mach-omap2/pm.c:239: error: implicit declaration of function 'disable_hlt'
>> > arch/arm/mach-omap2/pm.c: In function 'omap_pm_end':
>> > arch/arm/mach-omap2/pm.c:247: error: implicit declaration of function 'enable_hlt'
>> 
>> Care to mention which commit broke the compile?
>
> Seems like it was 9f97da78 (Disintegrate asm/system.h for ARM),
> and also needs to be fixed for omap1 too. Using the updated
> patch below.
>
> Tony
>
>
> From: Govindraj.R <govindraj.raja at ti.com>
> Date: Thu, 29 Mar 2012 09:30:28 -0700
> Subject: [PATCH] ARM: OMAP: pm: fix compilation break
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
>
> Fix the compilation break observed on latest mainline caused
> by 9f97da78 (Disintegrate asm/system.h for ARM):
>
> arch/arm/mach-omap1/pm.c: In function ?omap_pm_prepare?:
> arch/arm/mach-omap1/pm.c:587: error: implicit declaration of function ?disable_hlt?
> arch/arm/mach-omap1/pm.c: In function ?omap_pm_finish?:
> arch/arm/mach-omap1/pm.c:624: error: implicit declaration of function ?enable_hlt?
> arch/arm/mach-omap1/pm.c: In function ?omap_pm_init?:
> arch/arm/mach-omap1/pm.c:681: error: ?arm_pm_idle? undeclared (first use in this function)
> ...
>
> arch/arm/mach-omap2/pm.c: In function 'omap_pm_begin':
> arch/arm/mach-omap2/pm.c:239: error: implicit declaration of function 'disable_hlt'
> arch/arm/mach-omap2/pm.c: In function 'omap_pm_end':
> arch/arm/mach-omap2/pm.c:247: error: implicit declaration of function 'enable_hlt'
>
> Cc: Kevin Hilman <khilman at ti.com>
> Signed-off-by: Govindraj.R <govindraj.raja at ti.com>
> [tony at atomide.com: updated to fix omap1 too]
> Signed-off-by: Tony Lindgren <tony at atomide.com>

Acked-by: Kevin Hilman <khilman at ti.com>


From hartleys at visionengravers.com  Thu Mar 29 13:25:21 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Thu, 29 Mar 2012 12:25:21 -0500
Subject: [PATCH 1/3] PATA host controller driver for ep93xx
In-Reply-To: <4F741AB1.4000107@metasoft.pl>
References: <4F7418E7.4060500@metasoft.pl> <4F741AB1.4000107@metasoft.pl>
Message-ID: <ADE657CA350FB648AAC2C43247A983F0020697025609@AUSP01VMBX24.collaborationhost.net>

On Thursday, March 29, 2012 1:18 AM, Rafal Prylowski wrote:
>
> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
> Cc: Joao Ramos <joao.ramos at inov.pt>
> Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <ryan at bluewatersys.com>
> Cc: Sergei Shtylyov <sshtylyov at ru.montavista.com>
> Cc: Bartlomiej Zolnierkiewicz <bzolnier at gmail.com>

Unfortunately I don't have any ep93xx boards that support IDE.
But, I'll try to compile test this later.  Comments follow...

> ---
>  drivers/ata/Kconfig       |    9
>  drivers/ata/Makefile      |    1
>  drivers/ata/pata_ep93xx.c |  949 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 959 insertions(+)
>
> Index: linux-2.6/drivers/ata/pata_ep93xx.c
> ===================================================================
> --- /dev/null
> +++ linux-2.6/drivers/ata/pata_ep93xx.c
> @@ -0,0 +1,949 @@
> +/*
> + * EP93XX PATA controller driver.
> + *
> + * Copyright (c) 2012, Metasoft s.c.
> + *   Rafal Prylowski <prylowski at metasoft.pl>
> + *
> + * Based on pata_scc.c, pata_icside.c and on earlier version of EP93XX
> + * PATA driver by Lennert Buytenhek and Alessandro Zummo.
> + * Read/Write timings, resource management and other improvements
> + * from driver by Joao Ramos and Bartlomiej Zolnierkiewicz.
> + * DMA engine support based on spi-ep93xx.c by Mika Westerberg.
> + *
> + * Original copyrights:
> + *
> + * Support for Cirrus Logic's EP93xx (EP9312, EP9315) CPUs
> + * PATA host controller driver.
> + *
> + * Copyright (c) 2009, Bartlomiej Zolnierkiewicz
> + *
> + * Heavily based on the ep93xx-ide.c driver:
> + *
> + * Copyright (c) 2009, Joao Ramos <joao.ramos at inov.pt>
> + *                 INESC Inovacao (INOV)
> + *
> + * EP93XX PATA controller driver.
> + * Copyright (C) 2007 Lennert Buytenhek <buytenh at wantstofly.org>
> + *
> + * An ATA driver for the Cirrus Logic EP93xx PATA controller.
> + *
> + * Based on an earlier version by Alessandro Zummo, which is:
> + *   Copyright (C) 2006 Tower Technologies
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/blkdev.h>
> +#include <scsi/scsi_host.h>
> +#include <linux/ata.h>
> +#include <linux/libata.h>
> +#include <linux/platform_device.h>
> +#include <linux/delay.h>
> +#include <linux/dmaengine.h>
> +
> +#include <mach/dma.h>
> +#include <asm/mach-types.h>
> +#include <mach/ep93xx-regs.h>

mach-types.h and ep93xx-regs.h should not be needed.

> +#include <mach/platform.h>
> +
> +#define DRV_NAME     "ep93xx-ide"
> +#define DRV_VERSION  "1.0"
> +
> +enum {
> +     /* IDE Control Register */
> +     IDECtrl                         = 0x00,
> +     IDECtrl_CS0n                    = (1 << 0),
> +     IDECtrl_CS1n                    = (1 << 1),
> +     IDECtrl_DIORn                   = (1 << 5),
> +     IDECtrl_DIOWn                   = (1 << 6),
> +     IDECtrl_INTRQ                   = (1 << 9),
> +     IDECtrl_IORDY                   = (1 << 10),
> +
> +     /* IDE Configuration Register */
> +     IDECfg                          = 0x04,
> +     IDECfg_IDEEN                    = (1 << 0),
> +     IDECfg_PIO                      = (1 << 1),
> +     IDECfg_MDMA                     = (1 << 2),
> +     IDECfg_UDMA                     = (1 << 3),
> +     IDECfg_MODE_SHIFT               = 4,
> +     IDECfg_MODE_MASK                = (0xf << 4),
> +     IDECfg_WST_SHIFT                = 8,
> +     IDECfg_WST_MASK                 = (0x3 << 8),
> +
> +     /* MDMA Operation Register */
> +     IDEMDMAOp                       = 0x08,
> +
> +     /* UDMA Operation Register */
> +     IDEUDMAOp                       = 0x0c,
> +     IDEUDMAOp_UEN                   = (1 << 0),
> +     IDEUDMAOp_RWOP                  = (1 << 1),
> +
> +     /* PIO/MDMA/UDMA Data Registers */
> +     IDEDataOut                      = 0x10,
> +     IDEDataIn                       = 0x14,
> +     IDEMDMADataOut                  = 0x18,
> +     IDEMDMADataIn                   = 0x1c,
> +     IDEUDMADataOut                  = 0x20,
> +     IDEUDMADataIn                   = 0x24,
> +
> +     /* UDMA Status Register */
> +     IDEUDMASts                      = 0x28,
> +     IDEUDMASts_DMAide               = (1 << 16),
> +     IDEUDMASts_INTide               = (1 << 17),
> +     IDEUDMASts_SBUSY                = (1 << 18),
> +     IDEUDMASts_NDO                  = (1 << 24),
> +     IDEUDMASts_NDI                  = (1 << 25),
> +     IDEUDMASts_N4X                  = (1 << 26),
> +
> +     /* UDMA Debug Status Register */
> +     IDEUDMADebug                    = 0x2c,
> +};
> +
> +struct ep93xx_pata_data /* private_data in ata_host */
> +{
> +     void __iomem *ide_base;
> +     const struct ata_timing *t, *cmd_t;
> +     bool iordy;
> +
> +     unsigned long udma_in_phys;
> +     unsigned long udma_out_phys;
> +
> +     struct dma_chan *dma_rx_channel;
> +     struct ep93xx_dma_data dma_rx_data;
> +     struct dma_chan *dma_tx_channel;
> +     struct ep93xx_dma_data dma_tx_data;
> +};
> +
> +static void ep93xx_pata_clear_regs(void __iomem *base)
> +{
> +     writel(IDECtrl_CS0n | IDECtrl_CS1n | IDECtrl_DIORn |
> +             IDECtrl_DIOWn, base + IDECtrl);
> +
> +     writel(0, base + IDECfg);
> +     writel(0, base + IDEMDMAOp);
> +     writel(0, base + IDEUDMAOp);
> +     writel(0, base + IDEDataOut);
> +     writel(0, base + IDEDataIn);
> +     writel(0, base + IDEMDMADataOut);
> +     writel(0, base + IDEMDMADataIn);
> +     writel(0, base + IDEUDMADataOut);
> +     writel(0, base + IDEUDMADataIn);
> +     writel(0, base + IDEUDMADebug);
> + }
> +
> +static inline int ep93xx_pata_check_iordy(void __iomem *base)
> +{
> +     return (readl(base + IDECtrl) & IDECtrl_IORDY) ? 1 : 0;
> +}
> +
> +/*
> + * According to EP93xx User's Guide, WST field of IDECfg specifies number
> + * of HCLK cycles to hold the data bus after a PIO write operation.
> + * It should be programmed to guarantee following delays:
> + *
> + * PIO Mode   [ns]
> + * 0          30
> + * 1          20
> + * 2          15
> + * 3          10
> + * 4          5
> + *
> + * Maximum possible value for HCLK is 100MHz.
> + */
> +static inline int ep93xx_pata_get_wst(int pio_mode)
> +{
> +     return (pio_mode == 0 ? 3 : pio_mode < 3 ? 2 : 1)
> +             << IDECfg_WST_SHIFT;
> +}
> +
> +static inline void ep93xx_pata_enable_pio(void __iomem *base, int pio_mode)
> +{
> +     writel(IDECfg_IDEEN | IDECfg_PIO |
> +             ep93xx_pata_get_wst(pio_mode) |
> +             (pio_mode << IDECfg_MODE_SHIFT), base + IDECfg);
> +}
> +
> +static u16 ep93xx_pata_read(struct ep93xx_pata_data *drv_data,
> +                         void *addr_io,
> +                         const struct ata_timing *t)
> +{
> +     unsigned long addr = (unsigned long) addr_io & 0x1f;
> +     void __iomem *base = drv_data->ide_base;
> +     u16 ret;
> +
> +     writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
> +     ndelay(t->setup);
> +     writel(IDECtrl_DIOWn | addr, base + IDECtrl);
> +     ndelay(t->act8b);
> +     if (drv_data->iordy) {
> +             /* min. 1s timeout (at cpu cycle = 5ns) */
> +             unsigned int timeout = 200000;
> +             while (!ep93xx_pata_check_iordy(base) && --timeout)
> +                     cpu_relax();
> +     }
> +     /*
> +      * The IDEDataIn register is loaded from the DD pins at the positive
> +      * edge of the DIORn signal. (EP93xx UG p27-14)
> +      */
> +     writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
> +     ret = readl(base + IDEDataIn);
> +     ndelay(t->cyc8b - t->act8b - t->setup);
> +     return ret;
> +}
> +
> +static void ep93xx_pata_write(struct ep93xx_pata_data *drv_data,
> +                           u16 value, void *addr_io,
> +                           const struct ata_timing *t)
> +{
> +     unsigned long addr = (unsigned long) addr_io & 0x1f;
> +     void __iomem *base = drv_data->ide_base;
> +
> +     writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
> +     ndelay(t->setup);
> +     /*
> +      * Value from IDEDataOut register is driven onto the DD pins when
> +      * DIOWn is low. (EP93xx UG p27-13)
> +      */
> +     writel(value, base + IDEDataOut);
> +     writel(IDECtrl_DIORn | addr, base + IDECtrl);
> +     ndelay(t->act8b);
> +     if (drv_data->iordy) {
> +             /* min. 1s timeout */
> +             unsigned int timeout = 200000;
> +             while (!ep93xx_pata_check_iordy(base) && --timeout)
> +                     cpu_relax();
> +     }
> +     writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
> +     ndelay(t->cyc8b - t->act8b - t->setup);
> +}
> +
> +static void ep93xx_pata_set_piomode(struct ata_port *ap,
> +                                 struct ata_device *adev)
> +{
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +     struct ata_device *pair = ata_dev_pair(adev);
> +
> +     drv_data->t = ata_timing_find_mode(adev->pio_mode);
> +     drv_data->cmd_t = drv_data->t;
> +     drv_data->iordy = ata_pio_need_iordy(adev);
> +
> +     if (pair && pair->pio_mode < adev->pio_mode)
> +             drv_data->cmd_t = ata_timing_find_mode(pair->pio_mode);
> +
> +     ep93xx_pata_enable_pio(drv_data->ide_base,
> +                            adev->pio_mode - XFER_PIO_0);
> +}
> +
> +static u8 ep93xx_pata_check_status(struct ata_port *ap)
> +{
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;

Please add a whitespace here.

> +     return ep93xx_pata_read(drv_data, ap->ioaddr.status_addr,
> +                             drv_data->cmd_t);
> +}
> +
> +static u8 ep93xx_pata_check_altstatus(struct ata_port *ap)
> +{
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;

Please add a whitespace here.

> +     return ep93xx_pata_read(drv_data, ap->ioaddr.altstatus_addr,
> +                             drv_data->cmd_t);
> +}
> +
> +static void ep93xx_pata_tf_load(struct ata_port *ap,
> +                             const struct ata_taskfile *tf)
> +{
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +     const struct ata_timing *t = drv_data->cmd_t;
> +     struct ata_ioports *ioaddr = &ap->ioaddr;
> +     unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
> +
> +     if (tf->ctl != ap->last_ctl) {
> +             ep93xx_pata_write(drv_data, tf->ctl, ioaddr->ctl_addr, t);
> +             ap->last_ctl = tf->ctl;
> +             ata_wait_idle(ap);
> +     }
> +
> +     if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
> +             ep93xx_pata_write(drv_data, tf->hob_feature,
> +                     ioaddr->feature_addr, t);
> +             ep93xx_pata_write(drv_data, tf->hob_nsect,
> +                     ioaddr->nsect_addr, t);
> +             ep93xx_pata_write(drv_data, tf->hob_lbal,
> +                     ioaddr->lbal_addr, t);
> +             ep93xx_pata_write(drv_data, tf->hob_lbam,
> +                     ioaddr->lbam_addr, t);
> +             ep93xx_pata_write(drv_data, tf->hob_lbah,
> +                     ioaddr->lbah_addr, t);
> +             VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
> +                     tf->hob_feature, tf->hob_nsect, tf->hob_lbal,
> +                     tf->hob_lbam, tf->hob_lbah);
> +     }
> +
> +     if (is_addr) {
> +             ep93xx_pata_write(drv_data, tf->feature,
> +                     ioaddr->feature_addr, t);
> +             ep93xx_pata_write(drv_data, tf->nsect, ioaddr->nsect_addr, t);
> +             ep93xx_pata_write(drv_data, tf->lbal, ioaddr->lbal_addr, t);
> +             ep93xx_pata_write(drv_data, tf->lbam, ioaddr->lbam_addr, t);
> +             ep93xx_pata_write(drv_data, tf->lbah, ioaddr->lbah_addr, t);
> +             VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
> +                     tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
> +     }
> +
> +     if (tf->flags & ATA_TFLAG_DEVICE) {
> +             ep93xx_pata_write(drv_data, tf->device, ioaddr->device_addr, t);
> +             VPRINTK("device 0x%X\n", tf->device);
> +     }
> +
> +     ata_wait_idle(ap);
> +}
> +
> +static void ep93xx_pata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
> +{
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +     const struct ata_timing *t = drv_data->cmd_t;
> +     struct ata_ioports *ioaddr = &ap->ioaddr;
> +
> +     tf->command = ep93xx_pata_check_status(ap);
> +     tf->feature = ep93xx_pata_read(drv_data, ioaddr->feature_addr, t);
> +     tf->nsect = ep93xx_pata_read(drv_data, ioaddr->nsect_addr, t);
> +     tf->lbal = ep93xx_pata_read(drv_data, ioaddr->lbal_addr, t);
> +     tf->lbam = ep93xx_pata_read(drv_data, ioaddr->lbam_addr, t);
> +     tf->lbah = ep93xx_pata_read(drv_data, ioaddr->lbah_addr, t);
> +     tf->device = ep93xx_pata_read(drv_data, ioaddr->device_addr, t);
> +
> +     if (tf->flags & ATA_TFLAG_LBA48) {
> +             ep93xx_pata_write(drv_data, tf->ctl | ATA_HOB,
> +                     ioaddr->ctl_addr, t);
> +             tf->hob_feature = ep93xx_pata_read(drv_data,
> +                     ioaddr->feature_addr, t);
> +             tf->hob_nsect = ep93xx_pata_read(drv_data,
> +                     ioaddr->nsect_addr, t);
> +             tf->hob_lbal = ep93xx_pata_read(drv_data,
> +                     ioaddr->lbal_addr, t);
> +             tf->hob_lbam = ep93xx_pata_read(drv_data,
> +                     ioaddr->lbam_addr, t);
> +             tf->hob_lbah = ep93xx_pata_read(drv_data,
> +                     ioaddr->lbah_addr, t);
> +             ep93xx_pata_write(drv_data, tf->ctl, ioaddr->ctl_addr, t);
> +             ap->last_ctl = tf->ctl;
> +     }
> +}
> +
> +static void ep93xx_pata_exec_command(struct ata_port *ap,
> +                                  const struct ata_taskfile *tf)
> +{
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;

Please add a whitespace here.

> +     DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
> +
> +     ep93xx_pata_write(drv_data, tf->command,
> +                       ap->ioaddr.command_addr, drv_data->cmd_t);
> +     ata_sff_pause(ap);
> +}
> +
> +static void ep93xx_pata_dev_select(struct ata_port *ap, unsigned int device)
> +{
> +     u8 tmp;
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +
> +     if (device == 0)
> +             tmp = ATA_DEVICE_OBS;
> +     else
> +             tmp = ATA_DEVICE_OBS | ATA_DEV1;
> +
> +     ep93xx_pata_write(drv_data, tmp, ap->ioaddr.device_addr,
> +                       drv_data->cmd_t);
> +     ata_sff_pause(ap);      /* needed; also flushes, for mmio */
> +}
> +
> +static void ep93xx_pata_set_devctl(struct ata_port *ap, u8 ctl)
> +{
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;

Please add a whitespace here.

> +     ep93xx_pata_write(drv_data, ctl, ap->ioaddr.ctl_addr,
> +                       drv_data->cmd_t);
> +}
> +
> +unsigned int ep93xx_pata_data_xfer(struct ata_device *adev, unsigned char *buf,
> +                                unsigned int buflen, int rw)
> +{
> +     struct ata_port *ap = adev->link->ap;
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +     const struct ata_timing *t = drv_data->t;
> +     void *data_addr = ap->ioaddr.data_addr;
> +     u16 *data = (u16 *) buf;
> +     unsigned int words = buflen >> 1;
> +
> +     /* Transfer multiple of 2 bytes */
> +     if (rw == READ)
> +             while (words--)
> +                     *data++ = cpu_to_le16(
> +                             ep93xx_pata_read(drv_data, data_addr, t));
> +     else
> +             while (words--)
> +                     ep93xx_pata_write(drv_data, le16_to_cpu(*data++),
> +                             data_addr, t);
> +
> +     /* Transfer trailing 1 byte, if any. */
> +     if (unlikely(buflen & 0x01)) {
> +             unsigned char pad[2] = { };
> +
> +             buf += buflen - 1;
> +
> +             if (rw == READ) {
> +                     *pad = cpu_to_le16(
> +                             ep93xx_pata_read(drv_data, data_addr, t));
> +                     *buf = pad[0];
> +             } else {
> +                     pad[0] = *buf;
> +                     ep93xx_pata_write(drv_data, le16_to_cpu(*pad),
> +                                       data_addr, t);
> +             }
> +             words++;
> +     }
> +
> +     return words << 1;
> +}
> +
> +static unsigned int ep93xx_pata_dev_check(struct ata_port *ap,
> +                                       unsigned int device)
> +{
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +     const struct ata_timing *t = drv_data->cmd_t;
> +     struct ata_ioports *ioaddr = &ap->ioaddr;
> +     u8 nsect, lbal;
> +
> +     ap->ops->sff_dev_select(ap, device);
> +
> +     ep93xx_pata_write(drv_data, 0x55, ioaddr->nsect_addr, t);
> +     ep93xx_pata_write(drv_data, 0xaa, ioaddr->lbal_addr, t);
> +
> +     ep93xx_pata_write(drv_data, 0xaa, ioaddr->nsect_addr, t);
> +     ep93xx_pata_write(drv_data, 0x55, ioaddr->lbal_addr, t);
> +
> +     ep93xx_pata_write(drv_data, 0x55, ioaddr->nsect_addr, t);
> +     ep93xx_pata_write(drv_data, 0xaa, ioaddr->lbal_addr, t);
> +
> +     nsect = ep93xx_pata_read(drv_data, ioaddr->nsect_addr, t);
> +     lbal = ep93xx_pata_read(drv_data, ioaddr->lbal_addr, t);
> +
> +     if ((nsect == 0x55) && (lbal == 0xaa))
> +             return 1;       /* we found a device */
> +
> +     return 0;               /* nothing found */
> +}
> +
> +int ep93xx_pata_wait_after_reset(struct ata_link *link, unsigned int devmask,
> +                              unsigned long deadline)
> +{
> +     struct ata_port *ap = link->ap;
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +     const struct ata_timing *t = drv_data->cmd_t;
> +     struct ata_ioports *ioaddr = &ap->ioaddr;
> +     unsigned int dev0 = devmask & (1 << 0);
> +     unsigned int dev1 = devmask & (1 << 1);
> +     int rc, ret = 0;
> +
> +     ata_msleep(ap, ATA_WAIT_AFTER_RESET);
> +
> +     /* always check readiness of the master device */
> +     rc = ata_sff_wait_ready(link, deadline);
> +     /* -ENODEV means the odd clown forgot the D7 pulldown resistor
> +      * and TF status is 0xff, bail out on it too.
> +      */
> +     if (rc)
> +             return rc;
> +
> +     /* if device 1 was found in ata_devchk, wait for register
> +      * access briefly, then wait for BSY to clear.
> +      */
> +     if (dev1) {
> +             int i;
> +
> +             ap->ops->sff_dev_select(ap, 1);
> +
> +             /* Wait for register access.  Some ATAPI devices fail
> +              * to set nsect/lbal after reset, so don't waste too
> +              * much time on it.  We're gonna wait for !BSY anyway.
> +              */
> +             for (i = 0; i < 2; i++) {
> +                     u8 nsect, lbal;
> +
> +                     nsect = ep93xx_pata_read(drv_data,
> +                             ioaddr->nsect_addr, t);
> +                     lbal = ep93xx_pata_read(drv_data,
> +                             ioaddr->lbal_addr, t);
> +                     if (nsect == 1 && lbal == 1)
> +                             break;
> +                     msleep(50);     /* give drive a breather */
> +             }
> +
> +             rc = ata_sff_wait_ready(link, deadline);
> +             if (rc) {
> +                     if (rc != -ENODEV)
> +                             return rc;
> +                     ret = rc;
> +             }
> +     }
> +     /* is all this really necessary? */
> +     ap->ops->sff_dev_select(ap, 0);
> +     if (dev1)
> +             ap->ops->sff_dev_select(ap, 1);
> +     if (dev0)
> +             ap->ops->sff_dev_select(ap, 0);

Is it necessary? If so please remove the comment.

> +
> +     return ret;
> +}
> +
> +static int ep93xx_pata_bus_softreset(struct ata_port *ap, unsigned int devmask,
> +                                  unsigned long deadline)
> +{
> +     struct ata_ioports *ioaddr = &ap->ioaddr;
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +     const struct ata_timing *t = drv_data->cmd_t;
> +
> +     DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
> +
> +     ep93xx_pata_write(drv_data, ap->ctl, ioaddr->ctl_addr, t);
> +     udelay(20);             /* FIXME: flush */
> +     ep93xx_pata_write(drv_data, ap->ctl | ATA_SRST, ioaddr->ctl_addr, t);
> +     udelay(20);             /* FIXME: flush */

What's up with the FIXME?

> +     ep93xx_pata_write(drv_data, ap->ctl, ioaddr->ctl_addr, t);
> +     ap->last_ctl = ap->ctl;
> +
> +     return ep93xx_pata_wait_after_reset(&ap->link, devmask, deadline);
> +}
> +
> +static bool ep93xx_pata_dma_filter(struct dma_chan *chan, void *filter_param)
> +{
> +     if (ep93xx_dma_chan_is_m2p(chan))
> +             return false;
> +
> +     chan->private = filter_param;
> +     return true;
> +}
> +
> +static int ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
> +{
> +     dma_cap_mask_t mask;
> +
> +     dma_cap_zero(mask);
> +     dma_cap_set(DMA_SLAVE, mask);
> +
> +     /*
> +      * Request two channels for IDE. Another possibility would be
> +      * to request only one channel, and reprogram it's direction at
> +      * start of new transfer.
> +      */
> +     drv_data->dma_rx_data.port = EP93XX_DMA_IDE;
> +     drv_data->dma_rx_data.direction = DMA_FROM_DEVICE;
> +     drv_data->dma_rx_data.name = "ep93xx-pata-rx";
> +     drv_data->dma_tx_data.port = EP93XX_DMA_IDE;
> +     drv_data->dma_tx_data.direction = DMA_TO_DEVICE;
> +     drv_data->dma_tx_data.name = "ep93xx-pata-tx";
> +     drv_data->dma_rx_channel = dma_request_channel(mask,
> +             ep93xx_pata_dma_filter, &drv_data->dma_rx_data);
> +     drv_data->dma_tx_channel = dma_request_channel(mask,
> +             ep93xx_pata_dma_filter, &drv_data->dma_tx_data);
> +     return drv_data->dma_rx_channel && drv_data->dma_tx_channel;
> +}
> +
> +static void ep93xx_pata_dma_start(struct ata_queued_cmd *qc)
> +{
> +     struct dma_async_tx_descriptor *txd;
> +     struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
> +     void __iomem *base = drv_data->ide_base;
> +     struct ata_device *adev = qc->dev;
> +     u32 v = qc->dma_dir == DMA_TO_DEVICE ? IDEUDMAOp_RWOP : 0;
> +     struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE
> +             ? drv_data->dma_tx_channel : drv_data->dma_rx_channel;
> +
> +     txd = channel->device->device_prep_slave_sg(channel, qc->sg,
> +              qc->n_elem, qc->dma_dir, DMA_CTRL_ACK);
> +     if (!txd) {
> +             dev_err(qc->ap->dev, "failed to prepare slave for sg dma\n");
> +             BUG();

Is there a better way to handle this than BUG()? Can the driver fall back to PIO mode?

> +     }
> +     txd->callback = NULL;
> +     txd->callback_param = NULL;
> +
> +     if (dmaengine_submit(txd) < 0) {
> +             dev_err(qc->ap->dev, "failed to submit dma transfer\n");
> +             BUG();
> +     }
> +     dma_async_issue_pending(channel);
> +
> +     /*
> +      * When enabling UDMA operation, IDEUDMAOp register needs to be
> +      * programmed in three step sequence:
> +      * 1) set or clear the RWOP bit,
> +      * 2) perform dummy read of the register,
> +      * 3) set the UEN bit.
> +      */
> +     writel(v, base + IDEUDMAOp);
> +     readl(base + IDEUDMAOp);
> +     writel(v | IDEUDMAOp_UEN, base + IDEUDMAOp);
> +
> +     writel(IDECfg_IDEEN | IDECfg_UDMA |
> +             ((adev->xfer_mode - XFER_UDMA_0) << IDECfg_MODE_SHIFT),
> +             base + IDECfg);
> +}
> +
> +static void ep93xx_pata_dma_stop(struct ata_queued_cmd *qc)
> +{
> +     struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
> +     void __iomem *base = drv_data->ide_base;
> +
> +     /* terminate all dma transfers, if not yet finished */
> +     dmaengine_terminate_all(drv_data->dma_rx_channel);
> +     dmaengine_terminate_all(drv_data->dma_tx_channel);
> +
> +     /*
> +      * To properly stop IDE-DMA, IDEUDMAOp register must to be cleared
> +      * and IDECtrl register must be set to default value.
> +      */
> +     writel(0, base + IDEUDMAOp);
> +     writel(readl(base + IDECtrl) | IDECtrl_DIOWn | IDECtrl_DIORn |
> +             IDECtrl_CS0n | IDECtrl_CS1n, base + IDECtrl);
> +
> +     ep93xx_pata_enable_pio(drv_data->ide_base,
> +             qc->dev->pio_mode - XFER_PIO_0);
> +
> +     ata_sff_dma_pause(qc->ap);
> +}
> +
> +static void ep93xx_pata_dma_setup(struct ata_queued_cmd *qc)
> +{
> +     struct dma_slave_config conf;
> +     struct ata_port *ap = qc->ap;
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +     struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE
> +             ? drv_data->dma_tx_channel : drv_data->dma_rx_channel;
> +
> +     memset(&conf, 0, sizeof(conf));
> +     conf.direction = qc->dma_dir;
> +     if (qc->dma_dir == DMA_FROM_DEVICE) {
> +             conf.src_addr = drv_data->udma_in_phys;
> +             conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +     } else {
> +             conf.dst_addr = drv_data->udma_out_phys;
> +             conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +     }
> +     if (dmaengine_slave_config(channel, &conf)) {
> +             dev_err(qc->ap->dev, "failed to configure slave for sg dma\n");
> +             BUG();
> +     }
> +
> +     ap->ops->sff_exec_command(ap, &qc->tf);
> +}
> +
> +static u8 ep93xx_pata_dma_status(struct ata_port *ap)
> +{
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +     u32 val = readl(drv_data->ide_base + IDEUDMASts);
> +
> +     /*
> +      * UDMA Status Register bits:
> +      *
> +      * DMAide - DMA request signal from UDMA state machine,
> +      * INTide - INT line generated by UDMA because of errors in the
> +      *          state machine,
> +      * SBUSY - UDMA state machine busy, not in idle state,
> +      * NDO   - error for data-out not completed,
> +      * NDI   - error for data-in not completed,
> +      * N4X   - error for data transferred not multiplies of four
> +      *         32-bit words.
> +      * (EP93xx UG p27-17)
> +      */
> +     if (val & IDEUDMASts_NDO || val & IDEUDMASts_NDI ||
> +         val & IDEUDMASts_N4X || val & IDEUDMASts_INTide)
> +             return ATA_DMA_ERR;
> +
> +     /* read INTRQ (INT[3]) pin input state */
> +     if (readl(drv_data->ide_base + IDECtrl) & IDECtrl_INTRQ)
> +             return ATA_DMA_INTR;
> +
> +     if (val & IDEUDMASts_SBUSY || val & IDEUDMASts_DMAide)
> +             return ATA_DMA_ACTIVE;
> +
> +     return 0;
> +}
> +
> +static int ep93xx_pata_softreset(struct ata_link *al, unsigned int *classes,
> +                              unsigned long deadline)
> +{
> +     struct ata_port *ap = al->ap;
> +     unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
> +     unsigned int devmask = 0;
> +     int rc;
> +     u8 err;
> +
> +     DPRINTK("ENTER\n");
> +
> +     /* determine if device 0/1 are present */
> +     if (ep93xx_pata_dev_check(ap, 0))
> +             devmask |= (1 << 0);
> +     if (slave_possible && ep93xx_pata_dev_check(ap, 1))
> +             devmask |= (1 << 1);
> +
> +     /* select device 0 again */
> +     ap->ops->sff_dev_select(al->ap, 0);
> +
> +     /* issue bus reset */
> +     DPRINTK("about to softreset, devmask=%x\n", devmask);
> +     rc = ep93xx_pata_bus_softreset(ap, devmask, deadline);
> +     /* if link is ocuppied, -ENODEV too is an error */
> +     if (rc && (rc != -ENODEV || sata_scr_valid(al))) {
> +             ata_link_printk(al, KERN_ERR, "SRST failed (errno=%d)\n",
> +                             rc);
> +             return rc;
> +     }
> +
> +     /* determine by signature whether we have ATA or ATAPI devices */
> +     classes[0] = ata_sff_dev_classify(&al->device[0], devmask & (1 << 0),
> +                                       &err);
> +     if (slave_possible && err != 0x81)
> +             classes[1] = ata_sff_dev_classify(&al->device[1],
> +                                               devmask & (1 << 1), &err);
> +
> +     DPRINTK("EXIT, classes[0]=%u, [1]=%u\n", classes[0],
> +             classes[1]);
> +     return 0;
> +}
> +
> +void ep93xx_pata_drain_fifo(struct ata_queued_cmd *qc)
> +{
> +     int count;
> +     struct ata_port *ap;
> +     struct ep93xx_pata_data *drv_data;
> +
> +     /* We only need to flush incoming data when a command was running */
> +     if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
> +             return;
> +
> +     ap = qc->ap;
> +     drv_data = ap->host->private_data;
> +     /* Drain up to 64K of data before we give up this recovery method */
> +     for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
> +                  && count < 65536; count += 2)
> +             ep93xx_pata_read(drv_data, ap->ioaddr.data_addr,
> +                              drv_data->cmd_t);
> +
> +     /* Can become DEBUG later */
> +     if (count)
> +             ata_port_printk(ap, KERN_DEBUG,
> +                             "drained %d bytes to clear DRQ.\n", count);
> +
> +}
> +
> +static int ep93xx_pata_port_start(struct ata_port *ap)
> +{
> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +
> +     drv_data->cmd_t = ata_timing_find_mode(XFER_PIO_0);
> +     return 0;
> +}
> +
> +static struct scsi_host_template ep93xx_pata_sht = {
> +     ATA_BASE_SHT(DRV_NAME),
> +     /* ep93xx dma implementation limit */
> +     .sg_tablesize           = 32,
> +     /* ep93xx dma can't transfer 65536 bytes at once */
> +     .dma_boundary           = 0x7fff,
> +};
> +
> +static struct ata_port_operations ep93xx_pata_port_ops = {
> +     .inherits               = &ata_bmdma_port_ops,
> +
> +     .qc_prep                = ata_noop_qc_prep,
> +
> +     .softreset              = ep93xx_pata_softreset,
> +     .hardreset              = ATA_OP_NULL,
> +
> +     .sff_dev_select         = ep93xx_pata_dev_select,
> +     .sff_set_devctl         = ep93xx_pata_set_devctl,
> +     .sff_check_status       = ep93xx_pata_check_status,
> +     .sff_check_altstatus    = ep93xx_pata_check_altstatus,
> +     .sff_tf_load            = ep93xx_pata_tf_load,
> +     .sff_tf_read            = ep93xx_pata_tf_read,
> +     .sff_exec_command       = ep93xx_pata_exec_command,
> +     .sff_data_xfer          = ep93xx_pata_data_xfer,
> +     .sff_drain_fifo         = ep93xx_pata_drain_fifo,
> +     .sff_irq_clear          = ATA_OP_NULL,
> +
> +     .set_piomode            = ep93xx_pata_set_piomode,
> +
> +     .bmdma_setup            = ep93xx_pata_dma_setup,
> +     .bmdma_start            = ep93xx_pata_dma_start,
> +     .bmdma_stop             = ep93xx_pata_dma_stop,
> +     .bmdma_status           = ep93xx_pata_dma_status,
> +
> +     .cable_detect           = ata_cable_unknown,
> +     .port_start             = ep93xx_pata_port_start,
> +};
> +
> +static void ep93xx_pata_setup_port(struct ata_ioports *ioaddr)
> +{
> +     /*
> +      * the device IDE register to be accessed is selected through
> +      * IDECTRL register's specific bitfields 'DA', 'CS1n' and 'CS0n':
> +      *   b4   b3   b2    b1     b0
> +      *   A2   A1   A0   CS1n   CS0n
> +      * the values filled in this structure allows the value to be directly
> +      * ORed to the IDECTRL register, hence giving directly the A[2:0] and
> +      * CS1n/CS0n values for each IDE register.
> +      * The values correspond to the transformation:
> +      *   ((real IDE address) << 2) | CS1n value << 1 | CS0n value
> +      */
> +     ioaddr->cmd_addr        = (void __iomem *) 0 + 2; /* CS1 */
> +
> +     ioaddr->data_addr       = (void __iomem *) (ATA_REG_DATA << 2) + 2;
> +     ioaddr->error_addr      = (void __iomem *) (ATA_REG_ERR << 2) + 2;
> +     ioaddr->feature_addr    = (void __iomem *) (ATA_REG_FEATURE << 2) + 2;
> +     ioaddr->nsect_addr      = (void __iomem *) (ATA_REG_NSECT << 2) + 2;
> +     ioaddr->lbal_addr       = (void __iomem *) (ATA_REG_LBAL << 2) + 2;
> +     ioaddr->lbam_addr       = (void __iomem *) (ATA_REG_LBAM << 2) + 2;
> +     ioaddr->lbah_addr       = (void __iomem *) (ATA_REG_LBAH << 2) + 2;
> +     ioaddr->device_addr     = (void __iomem *) (ATA_REG_DEVICE << 2) + 2;
> +     ioaddr->status_addr     = (void __iomem *) (ATA_REG_STATUS << 2) + 2;
> +     ioaddr->command_addr    = (void __iomem *) (ATA_REG_CMD << 2) + 2;
> +
> +     ioaddr->altstatus_addr  = (void __iomem *) (0x06 << 2) + 1; /* CS0 */
> +     ioaddr->ctl_addr        = (void __iomem *) (0x06 << 2) + 1; /* CS0 */

Is there any way to get rid of the casts? These aren't really (void __iomem *) anyway...

> +}
> +
> +static int __devinit ep93xx_pata_probe(struct platform_device *pdev)
> +{
> +     struct ep93xx_pata_data *drv_data;
> +     struct ata_host *host;
> +     struct ata_port *ap;
> +     unsigned int irq;
> +     struct resource *mem_res;
> +     void __iomem *ide_base;
> +
> +     /*if (readl(EP93XX_SYSCON_DEVCFG) & (EP93XX_SYSCON_DEVCFG_EONIDE
> +             | EP93XX_SYSCON_DEVCFG_GONIDE | EP93XX_SYSCON_DEVCFG_HONIDE)) {
> +             dev_err(&pdev->dev, "IDE/GPIO pin conflict\n");
> +             return -EINVAL;
> +     }*/

Remove this, see my comment in PATCH 2/3.

> +
> +     /* INT[3] (IRQ_EP93XX_EXT3) line connected as pull down */
> +     irq = platform_get_irq(pdev, 0);
> +     if (irq < 0) {
> +             dev_err(&pdev->dev, "IRQ allocation failed\n");
> +             return -ENXIO;
> +     }
> +
> +     mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +     if (!mem_res) {
> +             dev_err(&pdev->dev, "resources allocation failed\n");

Are these dev_err messages necessary?

> +             return -ENXIO;
> +     }
> +
> +     ide_base = devm_request_and_ioremap(&pdev->dev, mem_res);
> +     if (!ide_base) {
> +             dev_err(&pdev->dev, "memory region request/map failed\n");
> +             return -ENOMEM;
> +     }
> +
> +     drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
> +     if (!drv_data) {
> +             dev_err(&pdev->dev, "unable to allocate memory\n");
> +             return -ENOMEM;
> +     }
> +
> +     platform_set_drvdata(pdev, drv_data);
> +     drv_data->ide_base = ide_base;
> +     drv_data->udma_in_phys = mem_res->start + IDEUDMADataIn;
> +     drv_data->udma_out_phys = mem_res->start + IDEUDMADataOut;
> +     ep93xx_pata_dma_init(drv_data);
> +
> +     /* allocate host */
> +     host = ata_host_alloc(&pdev->dev, 1);
> +     if (!host) {
> +             dev_err(&pdev->dev, "ata_host_alloc() failed\n");
> +             return -ENOMEM;
> +     }
> +
> +     ep93xx_pata_clear_regs(ide_base);
> +
> +     host->n_ports = 1;
> +     host->private_data = drv_data;
> +
> +     ap = host->ports[0];
> +     ap->dev = &pdev->dev;
> +     ap->ops = &ep93xx_pata_port_ops;
> +     ap->flags |= ATA_FLAG_SLAVE_POSS;
> +     ap->pio_mask = ATA_PIO4;

Please add a whitespace line here.

> +     /*
> +      * Maximum UDMA modes:
> +      * EP931x rev.E0 - UDMA2
> +      * EP931x rev.E1 - UDMA3
> +      * EP931x rev.E2 - UDMA4
> +      *
> +      * MWDMA support was removed from EP931x rev.E2,
> +      * so this driver supports only UDMA modes.
> +      */
> +     if (drv_data->dma_rx_channel && drv_data->dma_tx_channel) {
> +             int chip_rev = ep93xx_chip_revision();

Please add a whitespace here.

> +             if (chip_rev == EP93XX_CHIP_REV_E1)
> +                     ap->udma_mask = ATA_UDMA3;
> +             else if (chip_rev == EP93XX_CHIP_REV_E2)
> +                     ap->udma_mask = ATA_UDMA4;
> +             else
> +                     ap->udma_mask = ATA_UDMA2;
> +     }
> +
> +     ep93xx_pata_setup_port(&ap->ioaddr);
> +
> +     /* defaults, pio 0 */
> +     ep93xx_pata_enable_pio(ide_base, 0);
> +
> +     dev_info(&pdev->dev, "version " DRV_VERSION "\n");
> +
> +     /* activate host */
> +     return ata_host_activate(host, irq, ata_bmdma_interrupt, 0,
> +             &ep93xx_pata_sht);

If the host does not activate do you need to handle any cleanup?

> +}
> +
> +static int __devexit ep93xx_pata_remove(struct platform_device *pdev)
> +{
> +     struct ata_host *host = platform_get_drvdata(pdev);
> +     struct ep93xx_pata_data *drv_data = host->private_data;
> +
> +     ata_host_detach(host);
> +     if (drv_data->dma_rx_channel)
> +             dma_release_channel(drv_data->dma_rx_channel);
> +     if (drv_data->dma_tx_channel)
> +             dma_release_channel(drv_data->dma_tx_channel);
> +     ep93xx_pata_clear_regs(drv_data->ide_base);
> +     return 0;
> +}

Make sure to call the core ep93xx_ide_release_gpio function in the remove.

> +
> +static struct platform_driver ep93xx_pata_platform_driver = {
> +     .driver = {
> +             .name = DRV_NAME,
> +             .owner = THIS_MODULE,
> +     },
> +     .probe = ep93xx_pata_probe,
> +     .remove = __devexit_p(ep93xx_pata_remove),
> +};
> +
> +static int __init ep93xx_pata_init(void)
> +{
> +     return platform_driver_register(&ep93xx_pata_platform_driver);
> +}
> +
> +static void __exit ep93xx_pata_exit(void)
> +{
> +     platform_driver_unregister(&ep93xx_pata_platform_driver);
> +}
> +
> +module_init(ep93xx_pata_init);
> +module_exit(ep93xx_pata_exit);

Please use module_platform_driver instead of module_init/module_exit.

> +
> +MODULE_AUTHOR("Alessandro Zummo, Lennert Buytenhek, Joao Ramos, "
> +             "Bartlomiej Zolnierkiewicz, Rafal Prylowski");
> +MODULE_DESCRIPTION("low-level driver for cirrus ep93xx IDE controller");
> +MODULE_LICENSE("GPL");
> +MODULE_VERSION(DRV_VERSION);
> +MODULE_ALIAS("platform:pata_ep93xx");
> Index: linux-2.6/drivers/ata/Kconfig
> ===================================================================
> --- linux-2.6.orig/drivers/ata/Kconfig
> +++ linux-2.6/drivers/ata/Kconfig
> @@ -416,6 +416,15 @@ config PATA_EFAR
>
>         If unsure, say N.
>
> +config PATA_EP93XX
> +     tristate "Cirrus Logic EP93xx PATA support"
> +     depends on ARCH_EP93XX
> +     help
> +       This option enables support for the PATA controller in
> +       the Cirrus Logic EP9312 and EP9315 ARM CPU.
> +
> +       If unsure, say N.
> +
>  config PATA_HPT366
>       tristate "HPT 366/368 PATA support"
>       depends on PCI
> Index: linux-2.6/drivers/ata/Makefile
> ===================================================================
> --- linux-2.6.orig/drivers/ata/Makefile
> +++ linux-2.6/drivers/ata/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_PATA_CS5535)   += pata_cs5535
>  obj-$(CONFIG_PATA_CS5536)    += pata_cs5536.o
>  obj-$(CONFIG_PATA_CYPRESS)   += pata_cypress.o
>  obj-$(CONFIG_PATA_EFAR)              += pata_efar.o
> +obj-$(CONFIG_PATA_EP93XX)    += pata_ep93xx.o
>  obj-$(CONFIG_PATA_HPT366)    += pata_hpt366.o
>  obj-$(CONFIG_PATA_HPT37X)    += pata_hpt37x.o
>  obj-$(CONFIG_PATA_HPT3X2N)   += pata_hpt3x2n.o

Regards,
Hartley



From swarren at wwwdotorg.org  Thu Mar 29 13:26:48 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 29 Mar 2012 11:26:48 -0600
Subject: [RFC] pinctrl: Replace list_groups() with get_groups_count()
In-Reply-To: <CAOh2x==LTHPM+O9LXVFVdX2NfzKs2bttiYLm8VcL6qLXKrUMBg@mail.gmail.com>
References: <CAOh2x==LTHPM+O9LXVFVdX2NfzKs2bttiYLm8VcL6qLXKrUMBg@mail.gmail.com>
Message-ID: <4F749B58.4070608@wwwdotorg.org>

On 03/29/2012 10:34 AM, viresh kumar wrote:
> Most of the SoC drivers implement list_*() routines for pinctrl, pinmux,
> pinconf, etc, And these routines continue returning zero until the second
> argument is greater than total count of available groups, function, etc.
> 
> I will take struct pinctrl_ops as an example to elaborate my concern/doubts.
> 
> There are few concerns here:
> - list_groups() is called multiple times. If the purpose of this routine is to
>   only check the number of groups available, then why not remove it and create
>   another routine which returns number of total groups. Over which, we can run a
>   simple loop.
> - All client drivers have checks in their ops routines to check the range of
>   groups, which is just not required if we pass the correct number to pinctrl
>   framework. Because these ops are going to be called via pinctrl, and we can
>   trust on it and place these range checkers there only to make SoC drivers
>   simple.
> 
> I just wanted to have different views about my concerns/idea before i start
> coding. If this idea looks fine, i would do this change across pinmux framework.

The concept is fine by me.

I vaguely recall raising the same issue before, and Linus saying he
wanted to be consistent with similar list_*() functions in other
subsystems, but personally I'd prefer to evaluate this aspect of the
pinctrl subsystem on its own.


From tony at atomide.com  Thu Mar 29 13:28:02 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 29 Mar 2012 10:28:02 -0700
Subject: [PATCH 0/9] omap randconfig fixes for v3.3
In-Reply-To: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
References: <1332522836-29517-1-git-send-email-mathieu.poirier@linaro.org>
Message-ID: <20120329172802.GX9859@atomide.com>

Mathieu,

* mathieu.poirier at linaro.org <mathieu.poirier at linaro.org> [120323 10:16]:
> From: "Arnd Bergmann" <arnd at arndb.de>
> 
> The following is a set of patches that have been sent
> out during the 3.1 cycle that were not acked or merged.
> 
> Sending again for completeness.  
> 
> Tony, please pull if there are no objections:
> 
> The following changes since commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7:

Can you please drop the already fixed ones and post
a new pull request?

It seems that these should merge fine to current mainline
if based on v3.3. If not, then maybe use the linux-omap fixes
branch as the base that I've just pushed at commit 2533c2cf.

Thanks,

Tony


From paul.gortmaker at windriver.com  Thu Mar 29 13:43:54 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Thu, 29 Mar 2012 13:43:54 -0400
Subject: [PATCH v3] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <20120329151157.GT3668@opensource.wolfsonmicro.com>
References: <20120329151157.GT3668@opensource.wolfsonmicro.com>
Message-ID: <1333043034-3374-1-git-send-email-paul.gortmaker@windriver.com>

Commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0

  "regulator: Remove support for supplies specified by struct device"

caused this file to break, since it was still relying on the
device field to be present.  Map it onto dev_name appropriately

Since there are two consumers with the name "reg-userspace-consumer",
we have to supply the ID as a suffix in the REGULATOR_CONSUMER calls.

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
CC: Mark Brown <broonie at opensource.wolfsonmicro.com>
---

[v3: add .0/.1 ID suffix to "reg-userspace-consumer" instances ]

diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index c1b65da..16ec557 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1083,19 +1083,19 @@ static void __init em_x270_userspace_consumers_init(void)
 }
 
 /* DA9030 related initializations */
-#define REGULATOR_CONSUMER(_name, _dev, _supply)			       \
+#define REGULATOR_CONSUMER(_name, _dev_name, _supply)		        \
 	static struct regulator_consumer_supply _name##_consumers[] = {	\
 		{							\
-			.dev = _dev,					\
+			.dev_name = _dev_name,				\
 			.supply = _supply,				\
 		},							\
 	}
 
-REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps");
+REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer.0", "vcc gps");
 REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
-REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
+REGULATOR_CONSUMER(ldo10, "pxa2xx-mci", "vcc sdio");
 REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
-REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
+REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer.1", "vcc gprs");
 REGULATOR_CONSUMER(buck2, NULL, "vcc_core");
 
 #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask)		\
-- 
1.7.9.1



From swarren at wwwdotorg.org  Thu Mar 29 13:48:14 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Thu, 29 Mar 2012 11:48:14 -0600
Subject: [RFC] pinctrl: Replace list_groups() with get_groups_count()
In-Reply-To: <CAOh2x==mGDZRoxdbuvbhKtfoxiEDVb+7vdfBEYD=u+DdMCYVhw@mail.gmail.com>
References: <CAOh2x==LTHPM+O9LXVFVdX2NfzKs2bttiYLm8VcL6qLXKrUMBg@mail.gmail.com>	<4F749B58.4070608@wwwdotorg.org>
 <CAOh2x==mGDZRoxdbuvbhKtfoxiEDVb+7vdfBEYD=u+DdMCYVhw@mail.gmail.com>
Message-ID: <4F74A05E.7050803@wwwdotorg.org>

On 03/29/2012 11:31 AM, viresh kumar wrote:
> On Mar 29, 2012 10:56 PM, Stephen Warren wrote:
>> On 03/29/2012 10:34 AM, viresh kumar wrote:
...
>> I vaguely recall raising the same issue before, and Linus saying he
>> wanted to be consistent with similar list_*() functions in other
>> subsystems, but personally I'd prefer to evaluate this aspect of the
>> pinctrl subsystem on its own.
> 
> Which other subsystems have such stuff?

For example. include/linux/regulator/driver.h struct regulator_ops field
list_voltage().


From olof at lixom.net  Thu Mar 29 14:01:03 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 29 Mar 2012 11:01:03 -0700
Subject: [GIT PULL] USB AUXDATA fix for tegra
In-Reply-To: <201203211830.25161.arnd@arndb.de>
References: <4F6A1AEA.7070505@wwwdotorg.org> <201203211830.25161.arnd@arndb.de>
Message-ID: <20120329180103.GA2659@quad.lixom.net>

On Wed, Mar 21, 2012 at 06:30:24PM +0000, Arnd Bergmann wrote:
> On Wednesday 21 March 2012, Stephen Warren wrote:
> > This is my first pull request for Tegra; hopefully it all works out OK!
> > 
> > Note: Nobody has ack'd this change. I'm a maintainer for the files that
> > are touched, but I'm not sure if maintainers are supposed to have
> > another maintainer ack the change before committing it and sending a
> > pull request (in particular for their own changes), or if it's up to
> > their discretion?
> > 
> 
> Hi Stephen,
> 
> The pull request looks good. There is no need for anyone else to ack
> your patches, but you should always post them on the appropriate
> mailing lists so people can weigh in if they see something wrong.
> 
> I'm currently trying to get the first set of my v3.4 pull requests
> out to Linus, so I'll apply this when I'm done with that.

I've started staging the first batch of fixes for 3.4-rc, and I've pulled this
into that branch. Thanks, Stephen.


-Olof


From olof at lixom.net  Thu Mar 29 14:02:47 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 29 Mar 2012 11:02:47 -0700
Subject: [PATCH] ARM: LPC32xx: clock.c: Fix lpc-eth clock reference
In-Reply-To: <1332974996-13045-1-git-send-email-stigge@antcom.de>
References: <1332974996-13045-1-git-send-email-stigge@antcom.de>
Message-ID: <20120329180247.GB2659@quad.lixom.net>

On Thu, Mar 29, 2012 at 12:49:56AM +0200, Roland Stigge wrote:
> During a complex merge for v3.4, one line of the commit
> c20b909be9ba27173294a52d08cab293ec030a2c ("ARM: LPC32xx: Ethernet support") was
> reverted wrongly ("lpc-eth.0" -> "lpc-net.0") while the other conflicts were
> merged correctly. This patch re-applies the clock name "lpc-eth.0".
> 
> Signed-off-by: Roland Stigge <stigge at antcom.de>
> 
> ---
>  Applies on top of Olof's 1f5b7dcfdad3840d4bce27ab0b3cc8f376b81544 in
>  preparation of v3.4-rc1


Looks like it was me who messed up the conflict resolution, apologies
about that. Applied to fixes branch for 3.4-rc.


-Olof


From khilman at ti.com  Thu Mar 29 14:03:40 2012
From: khilman at ti.com (Kevin Hilman)
Date: Thu, 29 Mar 2012 11:03:40 -0700
Subject: [PATCH-V3 0/3] ARM: OMAP2+: Add powerdomain & PRM support for
 AM33XX device
In-Reply-To: <1331809586-24652-1-git-send-email-hvaibhav@ti.com> (Vaibhav
 Hiremath's message of "Thu, 15 Mar 2012 16:36:23 +0530")
References: <1331809586-24652-1-git-send-email-hvaibhav@ti.com>
Message-ID: <87limjl1xf.fsf@ti.com>

Hi Vaibhav,

Vaibhav Hiremath <hvaibhav at ti.com> writes:

> After going round-n-round on how to add support for AM33XX family
> of device into kernel, especially for PRM and CM support, we have
> decided to handle it separately; as AM33XX-PRCM module is different
> than OMAP3 and OMAP4 architecture.
>
> The difference becomes very interesting/weird when it comes to
> the consistency for register offsets in PRM address space and
> bit-field offsets inside PRM registers,
> So along with Powerdomain data and PRM api's required for AM33XX
> device, this patch series adds,
>
>  - XXX_RSTST register offset to "struct omap_hwmod_omap4_prcm"
>  - PWRSTCTRL & PWRSTST register offsets to "struct powerdomain"
>  - Logicretstate and mem_on/ret/pwrst/retst mask to "struct powerdomain"
>
>
> Testing: This patch series has been boot tested on AM37xEVM and AM335x
>          based BeagleBone community board.
>
> THANKS TO PAUL HERE...for helping and concluding on this, soon I will
> have similar patch for CM support, then clock-tree and hwmod will follow...
>
> Changes from V1 & V2:
> 	- Rolled back to my original approach, where AM33xx device was
> 	  handled separately (RFC version).

My apologies for causing the run around.  

This approach (without the prminst layer) is indeed a better approach.

Thanks for your patience (and persistence.)

I went to give this a test on my BeagleBone, but it doesn't apply to
mainline.  What upstream commit is this supposed to apply onto.  I tried
it on v3.3, but patch 3 fails with a conflict in io.c.

Looking at your am335x-staging branch, it seems that it depends on
previous changes to io.c made in:

        arm:omap:am33xx: Add AM335XEVM machine support

That patch appears to need an update for mainline as well.

Kevin


From olof at lixom.net  Thu Mar 29 14:31:11 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 29 Mar 2012 11:31:11 -0700
Subject: [GIT PULL] ARM: OMAP: i2c, gpio, spi,
 regulator and mmc DTS updates
In-Reply-To: <4F746CC0.9050507@ti.com>
References: <4F612C29.40608@ti.com> <20120315004638.GW12083@atomide.com>
 <201203150801.13183.arnd@arndb.de> <4F746CC0.9050507@ti.com>
Message-ID: <CAOesGMg+xLrVNxF0XwO8poAtuduwEcxrXLN9pXa+T+y7kKMy7Q@mail.gmail.com>

On Thu, Mar 29, 2012 at 7:08 AM, Cousson, Benoit <b-cousson at ti.com> wrote:
> Hi Arnd and Olof,
>
>
> On 3/15/2012 9:01 AM, Arnd Bergmann wrote:
>>
>> On Thursday 15 March 2012, Tony Lindgren wrote:
>>>
>>> * Cousson, Benoit<b-cousson at ti.com> ?[120314 16:41]:
>>>>
>>>> Hi Tony,
>>>>
>>>> Here are the remaining DTS patches for 3.4.
>>>>
>>>> On top of the previous pull request, I just added the MMC DTS since the
>>>> driver adaptation just got queued.
>>>>
>>>> It will be still be good to have that for 3.4 if possible, otherwise we
>>>> will
>>>> have a bunch of drivers DT adapted but no DTS file to use them :-(
>>>
>>>
>>> This might be doable as a follow-up patch series at the end
>>> of the merge window or at -rc1 when the related driver changes
>>> have been merged.
>>>
>>> Arnd and Olof, what do you guys think?
>>
>>
>> I'll have to look at the patches more closely, but from the diffstat it
>> definitely
>> looks ok for a later merge once the driver is in. If you can rebase the
>> branch on
>> top of the mmc tree (or the merge of that tree with whatever else is
>> needed), it
>> should give us a bisectable history and I can stick it into a late/*
>> branch right
>> away.
>
>
> FYI, MMC DT adaptation just got merged, I2C, GPIO, SPI, regulator DT
> adaptation were already merged before, so it means that this branch can be
> merged to take advantage of all the DT adapted drivers.

I've pulled this in as late/omap-dt, included in next/dt3 and
for-next. I'll let it sit in linux-next for at least one day before
it's sent in. Since it's just device tree additions, risk for
regressions should be low.


-Olof


From tony at atomide.com  Thu Mar 29 14:56:27 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 29 Mar 2012 11:56:27 -0700
Subject: [GIT PULL] omap fixes for merge window
In-Reply-To: <20120329144151.GS9859@atomide.com>
References: <20120321180536.GK9859@atomide.com>
 <CAOesGMiKc5Tc2e5X9=gSiFS87JtMWGmmtOLSStWJcO7ayoE6Rg@mail.gmail.com>
 <20120329144151.GS9859@atomide.com>
Message-ID: <20120329185626.GY9859@atomide.com>

* Tony Lindgren <tony at atomide.com> [120329 07:44]:
> * Olof Johansson <olof at lixom.net> [120328 22:04]:
> > Hi Tony,
> > 
> > On Wed, Mar 21, 2012 at 11:05 AM, Tony Lindgren <tony at atomide.com> wrote:
> > > Hi Arnd & Olof,
> > >
> > > Here's a set of fixes that would be nice to get merged during
> > > the merge window before the GPIO changes get merged to avoid
> > > boot issues on many omap boards.
> > >
> > > The changes queued in the GPIO tree require getting rid of
> > > OMAP_GPIO_IRQ and use gpio_to_irq() instead. This is needed for
> > > dynamically allocated GPIO interrupt ranges.
> > 
> > Sorry for the slow response on this, we've been focused on getting the
> > main pulls going in. I'm about to start a fixes branch now and looked
> > at this pull request.
> > 
> > I replied to one of the original patches in this branch, they need to
> > be fixed before they can go in:
> > 
> > http://marc.info/?l=linux-omap&m=133299716528617&w=2
> 
> Thanks, that's a good catch.
>  
> > Also, that way we can get a clean branch based on current mainline
> > without merge conflicts.
> 
> Yes will do.

Olof, here's an updated pull request for your fixes staging branch.

This contains the updated gpio_to_irq patches from Tarun, and a trivial
build fix from Govindraj to #include <asm/system_misc.h> in pm.c.
The DSI mux patch is the same.

Note that the branch name is now just fixes as the necessary commits
are now all in the mainline tree.

Regards,

Tony


The following changes since commit 0195c00244dc2e9f522475868fa278c473ba7339:
  Linus Torvalds (1):
        Merge tag 'split-asm_system_h-for-linus-20120328' of git://git.kernel.org/.../dhowells/linux-asm_system

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fixes

Govindraj.R (1):
      ARM: OMAP: pm: fix compilation break

Tarun Kanti DebBarma (3):
      ARM: OMAP: boards: Fix OMAP_GPIO_IRQ usage with gpio_to_irq()
      drivers: input: Fix OMAP_GPIO_IRQ with gpio_to_irq() in ams_delta_serio_exit()
      ARM: OMAP: Remove OMAP_GPIO_IRQ macro definition

Tomi Valkeinen (1):
      ARM: OMAP2+: Remove __init from DSI mux functions

Tony Lindgren (2):
      Merge branch 'fix-dss-mux' into fixes
      Merge branch 'fixes-gpio-to-irq' into fixes

 arch/arm/mach-omap1/board-h2.c               |    8 ++++----
 arch/arm/mach-omap1/board-h3.c               |    9 ++++-----
 arch/arm/mach-omap1/board-htcherald.c        |    6 +++---
 arch/arm/mach-omap1/board-innovator.c        |    4 ++--
 arch/arm/mach-omap1/board-nokia770.c         |    2 +-
 arch/arm/mach-omap1/board-osk.c              |   12 ++++++------
 arch/arm/mach-omap1/board-palmte.c           |    2 +-
 arch/arm/mach-omap1/board-palmtt.c           |    2 +-
 arch/arm/mach-omap1/board-palmz71.c          |    2 +-
 arch/arm/mach-omap1/board-voiceblue.c        |   16 +++++++---------
 arch/arm/mach-omap1/pm.c                     |    1 +
 arch/arm/mach-omap2/board-2430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-4430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-apollon.c          |    4 ++--
 arch/arm/mach-omap2/board-devkit8000.c       |    2 +-
 arch/arm/mach-omap2/board-h4.c               |    2 +-
 arch/arm/mach-omap2/board-omap3evm.c         |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c       |    2 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c |    3 ++-
 arch/arm/mach-omap2/board-zoom-debugboard.c  |    3 ++-
 arch/arm/mach-omap2/board-zoom-peripherals.c |    6 ++++--
 arch/arm/mach-omap2/common-board-devices.c   |    2 +-
 arch/arm/mach-omap2/display.c                |    8 ++++----
 arch/arm/mach-omap2/pm.c                     |    2 ++
 arch/arm/plat-omap/include/plat/gpio.h       |    4 ----
 drivers/input/serio/ams_delta_serio.c        |    2 +-
 26 files changed, 55 insertions(+), 55 deletions(-)


From olof at lixom.net  Thu Mar 29 15:27:21 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 29 Mar 2012 12:27:21 -0700
Subject: [GIT PULL] omap fixes for merge window
In-Reply-To: <20120329185626.GY9859@atomide.com>
References: <20120321180536.GK9859@atomide.com>
 <CAOesGMiKc5Tc2e5X9=gSiFS87JtMWGmmtOLSStWJcO7ayoE6Rg@mail.gmail.com>
 <20120329144151.GS9859@atomide.com>
 <20120329185626.GY9859@atomide.com>
Message-ID: <CAOesGMjNJZTFo_t+-O97kuB_Ob-V+1skCPzJvncN3b6R5b1ptg@mail.gmail.com>

On Thu, Mar 29, 2012 at 11:56 AM, Tony Lindgren <tony at atomide.com> wrote:
> * Tony Lindgren <tony at atomide.com> [120329 07:44]:
>> * Olof Johansson <olof at lixom.net> [120328 22:04]:
>> > Hi Tony,
>> >
>> > On Wed, Mar 21, 2012 at 11:05 AM, Tony Lindgren <tony at atomide.com> wrote:
>> > > Hi Arnd & Olof,
>> > >
>> > > Here's a set of fixes that would be nice to get merged during
>> > > the merge window before the GPIO changes get merged to avoid
>> > > boot issues on many omap boards.
>> > >
>> > > The changes queued in the GPIO tree require getting rid of
>> > > OMAP_GPIO_IRQ and use gpio_to_irq() instead. This is needed for
>> > > dynamically allocated GPIO interrupt ranges.
>> >
>> > Sorry for the slow response on this, we've been focused on getting the
>> > main pulls going in. I'm about to start a fixes branch now and looked
>> > at this pull request.
>> >
>> > I replied to one of the original patches in this branch, they need to
>> > be fixed before they can go in:
>> >
>> > http://marc.info/?l=linux-omap&m=133299716528617&w=2
>>
>> Thanks, that's a good catch.
>>
>> > Also, that way we can get a clean branch based on current mainline
>> > without merge conflicts.
>>
>> Yes will do.
>
> Olof, here's an updated pull request for your fixes staging branch.
>
> This contains the updated gpio_to_irq patches from Tarun, and a trivial
> build fix from Govindraj to #include <asm/system_misc.h> in pm.c.
> The DSI mux patch is the same.
>
> Note that the branch name is now just fixes as the necessary commits
> are now all in the mainline tree.
>
> Regards,
>
> Tony
>
>
> The following changes since commit 0195c00244dc2e9f522475868fa278c473ba7339:
> ?Linus Torvalds (1):
> ? ? ? ?Merge tag 'split-asm_system_h-for-linus-20120328' of git://git.kernel.org/.../dhowells/linux-asm_system
>
> are available in the git repository at:
>
> ?git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap fixe

Thanks, pulled.


-Olof


From u.kleine-koenig at pengutronix.de  Thu Mar 29 15:58:58 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 29 Mar 2012 21:58:58 +0200
Subject: [PATCH] ARM: imx/mx21ads: remove unneeded cast
Message-ID: <1333051138-27360-1-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/mach-mx21ads.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index e432d4a..d14bbe9 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -304,8 +304,7 @@ static void __init mx21ads_board_init(void)
 	imx21_add_mxc_nand(&mx21ads_nand_board_info);
 
 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-	platform_device_register_full(
-			(struct platform_device_info *)&mx21ads_cs8900_devinfo);
+	platform_device_register_full(&mx21ads_cs8900_devinfo);
 }
 
 static void __init mx21ads_timer_init(void)
-- 
1.7.9.1



From grant.likely at secretlab.ca  Thu Mar 29 16:49:37 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 29 Mar 2012 14:49:37 -0600
Subject: [PATCH] serial: PL011: move interrupt clearing
In-Reply-To: <1332357318-8017-1-git-send-email-linus.walleij@linaro.org>
References: <1332357318-8017-1-git-send-email-linus.walleij@linaro.org>
Message-ID: <CACxGe6u+KeYzWwiJ7MK7pWG444Y99CQ1LLCZP4m3R=zdYFR_pg@mail.gmail.com>

On Wed, Mar 21, 2012 at 1:15 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> Commit 360f748b204275229f8398cb2f9f53955db1503b
> "serial: PL011: clear pending interrupts"
> attempts to clear interrupts by writing to a
> yet-unassigned memory address. This fixes the issue.
>
> The breaking patch is marked for stable so should be
> carried along with the other patch.
>
> Cc: Shreshtha Kumar Sahu <shreshthakumar.sahu at stericsson.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: stable <stable at vger.kernel.org>
> Reported-by: Viresh Kumar <viresh.kumar at st.com>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>

Ugh; the original patch is obviously broken.  How did it get applied
without testing?

Greg, can you get this out to Linus ASAP please?  I have one comment
below, but I don't think it should block merging this patch.

Tested-by: Grant Likely <grant.likely at secretlab.ca>

> ---
> ?drivers/tty/serial/amba-pl011.c | ? ?8 ++++----
> ?1 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
> index 7e01399..4ed35c5 100644
> --- a/drivers/tty/serial/amba-pl011.c
> +++ b/drivers/tty/serial/amba-pl011.c
> @@ -1930,10 +1930,6 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
> ? ? ? ? ? ? ? ?goto unmap;
> ? ? ? ?}
>
> - ? ? ? /* Ensure interrupts from this UART are masked and cleared */
> - ? ? ? writew(0, uap->port.membase + UART011_IMSC);
> - ? ? ? writew(0xffff, uap->port.membase + UART011_ICR);
> -
> ? ? ? ?uap->vendor = vendor;
> ? ? ? ?uap->lcrh_rx = vendor->lcrh_rx;
> ? ? ? ?uap->lcrh_tx = vendor->lcrh_tx;
> @@ -1951,6 +1947,10 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
> ? ? ? ?uap->port.line = i;
> ? ? ? ?pl011_dma_probe(uap);
>
> + ? ? ? /* Ensure interrupts from this UART are masked and cleared */
> + ? ? ? writew(0, uap->port.membase + UART011_IMSC);
> + ? ? ? writew(0xffff, uap->port.membase + UART011_ICR);
> +

Is it correct to move the interrupt clearing below the
pl011_dma_probe() call?  I've tested the fix with the interrupt
clearing both above and below the pl011_dma_probe() call and versatile
qemu boots in both cases.

g.


From kispalsz at gmail.com  Thu Mar 29 16:57:41 2012
From: kispalsz at gmail.com (Kispal Szabolcs)
Date: Thu, 29 Mar 2012 22:57:41 +0200
Subject: s3c_otghcd and ECONNRESET
Message-ID: <CAHVpurpt38QcAi4zPg+WL05YCd0id4D=ffoGntR=dqUcviHN4A@mail.gmail.com>

Hello!

Sorry for my bad english.
I have a Android Phone. Samsung Galaxy Note. P/n: GT-N7000.  I have to
solve the external camerastream play on lcd.


I used samsung opensource update 1. version: 2.6.35.7
I set uvcvideo as modul.
 <*>     S3C USB OTG Host support
   <*>   USB Gadget Support  --->

   USB Peripheral Controller (S3C HS USB OTG Device)  --->    .
   USB Gadget ( Android gadget)

The kernel works correct. The phone boots up.  I can load modul :
insmod uvcvideo.

I have one problem.

The external (UVC) camera is not recognized on my Android phone. I
have asked uvc development. You can see below my emails with uvc
developers. (2 mail)

They have told me:
"-104 is -ECONNRESET. This is a low-level USB issue, possibly related to your
USB controller. I'm afraid I have no experience with the S3C USB OTG
controller. You might have more luck on the linux-usb mailing list (make sure
you mention s3c_otghcd and ECONNRESET in your mail subject)."

I think, that the problem is : my device support only isochronous mode.
I attatch lsusb log from usb uvc extarnal camera.

Please help me, that this problem is:

a: hw problem, my phone will never  support this mod .
b: my hw support this mod,only in recent driver ( s3c_hsotg.c)  is not
supported.
c: you have patch to  this mod :)   ( i hope)
d:Maybe, another thing cause "ECCONNRESET Problem".

Please help me asap, because this solution is very important for me. I
have to write one apk. on the phone what use external camera.  I can't
start writting of application.

e:Can you see other solution for my problem?

Thank you for your help.
Regards, Szabolcs








On 27.03.2012 23:55, Kispal Szabolcs wrote:
> ---------- Forwarded message ----------
> From: Kispal Szabolcs<kispalsz at gmail.com>
> Date: 2012/3/27
> Subject: UVC failed to initialize the device
> To: linux-uvc-devel at lists.sourceforge.net
>
>
> Hello,
> can You help me?
>
> Sorry my bad english. :)
>
> I have a camera. I use this on linux pc. ( ubuntu 10.04.04) . On Linux PC
> work correct. I use this camera with VLC, and i see the videostream from
> camera. I attach lsusb output.
>
> I want to use this camera on Android phone. This phone is Samsung Galaxy
> Note.
> I compiled my own  kernel from samsung opensource with uvcvideo as modul.
>
> I can load the modul on Android device:
> insmod   /lib/modules/uvcvideo.ko trace=255
>
> and i see, this modul is loaded.
> When i connect the camera with OTG Host cable to Android device, i see in
> dmesg:
>
>
> [  237.726595] usb 2-1.3: new high speed USB device using s3c_otghcd and
> address 3
> [  237.754590] uvcvideo: Probing generic UVC device 1.3
> [  237.754645] uvcvideo: Found format YUV 4:2:2 (YUYV).
> [  237.754671] uvcvideo: - 640x480 (30.0 fps)
> [  237.754690] uvcvideo: - 800x600 (15.0 fps)
> [  237.754709] uvcvideo: - 1024x768 (15.0 fps)
> [  237.754728] uvcvideo: - 1280x1024 (10.0 fps)
> [  237.754747] uvcvideo: - 352x288 (30.0 fps)
> [  237.754765] uvcvideo: - 320x240 (30.0 fps)
> [  237.754782] uvcvideo: - 176x144 (30.0 fps)
> [  237.754801] uvcvideo: - 160x120 (30.0 fps)
> [  237.754819] uvcvideo: - 640x480 (10.0 fps)
> [  237.754837] uvcvideo: - 640x480 (10.0 fps)
> [  237.754877] uvcvideo: Found a Status endpoint (addr 83).
> [  237.754902] uvcvideo: Found UVC 1.00 device USB 2.0 PC Cam (090c:b371)
> [  237.754926] uvcvideo: Forcing device quirks to 0x10 by module parameter
> for testing purpose.
> [  237.754950] uvcvideo: Please report required quirks to the
> linux-uvc-devel mailing list.
> [  237.754996] uvcvideo: Added control
> 00000000-0000-0000-0000-000000000101/2 to device 1.3 entity 3
> [  237.755027] uvcvideo: Added control
> 00000000-0000-0000-0000-000000000101/3 to device 1.3 entity 3
> [  237.755056] uvcvideo: Added control
> 00000000-0000-0000-0000-000000000101/6 to device 1.3 entity 3
> [  237.755086] uvcvideo: Added control
> 00000000-0000-0000-0000-000000000101/7 to device 1.3 entity 3
> [  237.755115] uvcvideo: Added control
> 00000000-0000-0000-0000-000000000101/8 to device 1.3 entity 3
> [  237.755144] uvcvideo: Added control
> 00000000-0000-0000-0000-000000000101/9 to device 1.3 entity 3
> [  237.755177] uvcvideo: Added control
> 00000000-0000-0000-0000-000000000101/4 to device 1.3 entity 3
> [  237.755206] uvcvideo: Added control
> 00000000-0000-0000-0000-000000000101/5 to device 1.3 entity 3
> [  237.755243] uvcvideo: Added control
> 00000000-0000-0000-0000-000000000001/3 to device 1.3 entity 1
> [  237.755278] uvcvideo: Scanning UVC chain: OT 4<- PU 3<- XU 2<- IT 1
> [  237.755328] uvcvideo: Found a valid video chain (1 ->  4).
>
> [  242.766398] uvcvideo: Failed to set UVC probe control : -104 (exp. 26).
> [  247.766677] uvcvideo: Failed to query (129) UVC probe control : -104
> (exp. 26).
> [  247.766863] uvcvideo: Failed to initialize the device (-5).
>
> Why can not i initialize the camera?
>
>
> When i use the camera on the Ubuntu, the next is the log of dmesg:
>
> 39105.367196] uvcvideo: Found a valid video chain (1 ->  4).
> [39105.470991] input: USB 2.0 PC Cam as
> /devices/pci0000:00/0000:00:02.1/usb1/1-5/1-5:1.0/input/input9
> [39105.471069] uvcvideo: UVC device initialized.
>
> My kernel version on Android is : 2.6.35.7. (i could see this is the newest
> kernel from my device)
>
> Can you help me, what is the fault?
>
> I have tried debug, i see, this function return bad:
>
> int uvc_video_init(struct uvc_streaming *stream)
>
> Thank you for your help, Szabolcs

This error was get by
drivers/media/video/uvc/uvc_video.c:uvc_set_video_ctrl()

Error -104 mean ECONNRESET
see for error numbers:
include/asm-generic/errno.h

and it was send by usb_unlink_urb()
see for usb error codes:
Documentation/usb/error-codes.txt

Uvcvideo driver never calls usb_unlink_urb(). I assume it was made by
usb host controller driver. Some where here drivers/usb/*
You will need to find why it was called. May be it is some software or
hardware bug.

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Hi Kispal,

On Tuesday 27 March 2012 23:50:38 Kispal Szabolcs wrote:
> Hi,
>
> my email was rejected.... Can you help me?

You should subscribe to the linux-uvc-devel mailing list to post messages.

> On Tue, 27 Mar 2012 23:24:06 +0200 Kispal Szabolcs wrote:
> > Hello,
> > can You help me?
> >
> > Sorry my bad english. :)
> >
> > I have a camera. I use this on linux pc. ( ubuntu 10.04.04) . On Linux PC
> > work correct. I use this camera with VLC, and i see the videostream from
> > camera. I attach lsusb output.
> >
> > I want to use this camera on Android phone. This phone is Samsung Galaxy
> > Note. I compiled my own  kernel from samsung opensource with uvcvideo as
> > modul.
> >
> > I can load the modul on Android device:
> > insmod   /lib/modules/uvcvideo.ko trace=255
> >
> > and i see, this modul is loaded.
> > When i connect the camera with OTG Host cable to Android device, i see in
> > dmesg:
> >
> >
> > [  237.726595] usb 2-1.3: new high speed USB device using s3c_otghcd and
> > address 3

[snip]

> > [  242.766398] uvcvideo: Failed to set UVC probe control : -104 (exp. 26).
> > [  247.766677] uvcvideo: Failed to query (129) UVC probe control : -104
> > (exp. 26).
> > [  247.766863] uvcvideo: Failed to initialize the device (-5).
> >
> > Why can not i initialize the camera?

-104 is -ECONNRESET. This is a low-level USB issue, possibly related to your
USB controller. I'm afraid I have no experience with the S3C USB OTG
controller. You might have more luck on the linux-usb mailing list (make sure
you mention s3c_otghcd and ECONNRESET in your mail subject).
-------------- next part --------------

Bus 001 Device 007: ID 090c:b371 Feiya Technology Corp. Silicon Motion SM371 Camera
Device Descriptor:
  bLength                18
  bDescriptorType         1
  bcdUSB               2.00
  bDeviceClass          239 Miscellaneous Device
  bDeviceSubClass         2 ?
  bDeviceProtocol         1 Interface Association
  bMaxPacketSize0        64
  idVendor           0x090c Feiya Technology Corp.
  idProduct          0xb371 Silicon Motion SM371 Camera
  bcdDevice            1.00
  iManufacturer           1 Image Processor
  iProduct                2 USB 2.0 PC Cam
  iSerial                 0 
  bNumConfigurations      1
  Configuration Descriptor:
    bLength                 9
    bDescriptorType         2
    wTotalLength          685
    bNumInterfaces          2
    bConfigurationValue     1
    iConfiguration          0 
    bmAttributes         0x80
      (Bus Powered)
    MaxPower              500mA
    Interface Association:
      bLength                 8
      bDescriptorType        11
      bFirstInterface         0
      bInterfaceCount         2
      bFunctionClass         14 Video
      bFunctionSubClass       3 Video Interface Collection
      bFunctionProtocol       0 
      iFunction               0 
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        0
      bAlternateSetting       0
      bNumEndpoints           1
      bInterfaceClass        14 Video
      bInterfaceSubClass      1 Video Control
      bInterfaceProtocol      0 
      iInterface              0 
      VideoControl Interface Descriptor:
        bLength                13
        bDescriptorType        36
        bDescriptorSubtype      1 (HEADER)
        bcdUVC               1.00
        wTotalLength           77
        dwClockFrequency       30.000000MHz
        bInCollection           1
        baInterfaceNr( 0)       1
      VideoControl Interface Descriptor:
        bLength                18
        bDescriptorType        36
        bDescriptorSubtype      2 (INPUT_TERMINAL)
        bTerminalID             1
        wTerminalType      0x0201 Camera Sensor
        bAssocTerminal          0
        iTerminal               0 
        wObjectiveFocalLengthMin      0
        wObjectiveFocalLengthMax      0
        wOcularFocalLength            0
        bControlSize                  3
        bmControls           0x00000004
          Auto-Exposure Priority
      VideoControl Interface Descriptor:
        bLength                26
        bDescriptorType        36
        bDescriptorSubtype      6 (EXTENSION_UNIT)
        bUnitID                 2
        guidExtensionCode         {92423946-d10c-e34a-8783-3133f9eaaa3b}
        bNumControl             3
        bNrPins                 1
        baSourceID( 0)          1
        bControlSize            1
        bmControls( 0)       0xff
        iExtension              0 
      VideoControl Interface Descriptor:
        bLength                11
        bDescriptorType        36
        bDescriptorSubtype      5 (PROCESSING_UNIT)
      Warning: Descriptor too short
        bUnitID                 3
        bSourceID               2
        wMaxMultiplier          0
        bControlSize            2
        bmControls     0x0000063f
          Brightness
          Contrast
          Hue
          Saturation
          Sharpness
          Gamma
          Gain
          Power Line Frequency
        iProcessing             0 
        bmVideoStandards     0x 9
          None
          SECAM - 625/50
      VideoControl Interface Descriptor:
        bLength                 9
        bDescriptorType        36
        bDescriptorSubtype      3 (OUTPUT_TERMINAL)
        bTerminalID             4
        wTerminalType      0x0101 USB Streaming
        bAssocTerminal          0
        bSourceID               3
        iTerminal               0 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x83  EP 3 IN
        bmAttributes            3
          Transfer Type            Interrupt
          Synch Type               None
          Usage Type               Data
        wMaxPacketSize     0x0008  1x 8 bytes
        bInterval              16
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        1
      bAlternateSetting       0
      bNumEndpoints           0
      bInterfaceClass        14 Video
      bInterfaceSubClass      2 Video Streaming
      bInterfaceProtocol      0 
      iInterface              0 
      VideoStreaming Interface Descriptor:
        bLength                            14
        bDescriptorType                    36
        bDescriptorSubtype                  1 (INPUT_HEADER)
        bNumFormats                         1
        wTotalLength                      497
        bEndPointAddress                  129
        bmInfo                              0
        bTerminalLink                       4
        bStillCaptureMethod                 2
        bTriggerSupport                     1
        bTriggerUsage                       0
        bControlSize                        1
        bmaControls( 0)                    27
      VideoStreaming Interface Descriptor:
        bLength                            27
        bDescriptorType                    36
        bDescriptorSubtype                  4 (FORMAT_UNCOMPRESSED)
        bFormatIndex                        1
        bNumFrameDescriptors               10
        guidFormat                            {59555932-0000-1000-8000-00aa00389b71}
        bBitsPerPixel                      16
        bDefaultFrameIndex                  1
        bAspectRatioX                       0
        bAspectRatioY                       0
        bmInterlaceFlags                 0x00
          Interlaced stream or variable: No
          Fields per frame: 1 fields
          Field 1 first: No
          Field pattern: Field 1 only
          bCopyProtect                      0
      VideoStreaming Interface Descriptor:
        bLength                            42
        bDescriptorType                    36
        bDescriptorSubtype                  5 (FRAME_UNCOMPRESSED)
        bFrameIndex                         1
        bmCapabilities                   0x00
          Still image unsupported
        wWidth                            640
        wHeight                           480
        dwMinBitRate                   912384
        dwMaxBitRate                   912384
        dwMaxVideoFrameBufferSize      614400
        dwDefaultFrameInterval         333333
        bFrameIntervalType                  4
        dwFrameInterval( 0)            333333
        dwFrameInterval( 1)            500000
        dwFrameInterval( 2)            666666
        dwFrameInterval( 3)          10000000
      VideoStreaming Interface Descriptor:
        bLength                            42
        bDescriptorType                    36
        bDescriptorSubtype                  5 (FRAME_UNCOMPRESSED)
        bFrameIndex                         2
        bmCapabilities                   0x00
          Still image unsupported
        wWidth                            800
        wHeight                           600
        dwMinBitRate                   912384
        dwMaxBitRate                   912384
        dwMaxVideoFrameBufferSize      960000
        dwDefaultFrameInterval         666666
        bFrameIntervalType                  4
        dwFrameInterval( 0)            666666
        dwFrameInterval( 1)           1000000
        dwFrameInterval( 2)           1333332
        dwFrameInterval( 3)          10000000
      VideoStreaming Interface Descriptor:
        bLength                            42
        bDescriptorType                    36
        bDescriptorSubtype                  5 (FRAME_UNCOMPRESSED)
        bFrameIndex                         3
        bmCapabilities                   0x00
          Still image unsupported
        wWidth                           1024
        wHeight                           768
        dwMinBitRate                   912384
        dwMaxBitRate                   912384
        dwMaxVideoFrameBufferSize     1572864
        dwDefaultFrameInterval         666666
        bFrameIntervalType                  4
        dwFrameInterval( 0)            666666
        dwFrameInterval( 1)           1000000
        dwFrameInterval( 2)           1333332
        dwFrameInterval( 3)          10000000
      VideoStreaming Interface Descriptor:
        bLength                            42
        bDescriptorType                    36
        bDescriptorSubtype                  5 (FRAME_UNCOMPRESSED)
        bFrameIndex                         4
        bmCapabilities                   0x00
          Still image unsupported
        wWidth                           1280
        wHeight                          1024
        dwMinBitRate                   912384
        dwMaxBitRate                   912384
        dwMaxVideoFrameBufferSize     2621440
        dwDefaultFrameInterval        1000000
        bFrameIntervalType                  4
        dwFrameInterval( 0)           1000000
        dwFrameInterval( 1)           1333332
        dwFrameInterval( 2)           2000000
        dwFrameInterval( 3)          10000000
      VideoStreaming Interface Descriptor:
        bLength                            42
        bDescriptorType                    36
        bDescriptorSubtype                  5 (FRAME_UNCOMPRESSED)
        bFrameIndex                         5
        bmCapabilities                   0x00
          Still image unsupported
        wWidth                            352
        wHeight                           288
        dwMinBitRate                   912384
        dwMaxBitRate                   912384
        dwMaxVideoFrameBufferSize      202752
        dwDefaultFrameInterval         333333
        bFrameIntervalType                  4
        dwFrameInterval( 0)            333333
        dwFrameInterval( 1)            500000
        dwFrameInterval( 2)            666666
        dwFrameInterval( 3)          10000000
      VideoStreaming Interface Descriptor:
        bLength                            42
        bDescriptorType                    36
        bDescriptorSubtype                  5 (FRAME_UNCOMPRESSED)
        bFrameIndex                         6
        bmCapabilities                   0x00
          Still image unsupported
        wWidth                            320
        wHeight                           240
        dwMinBitRate                   912384
        dwMaxBitRate                   912384
        dwMaxVideoFrameBufferSize      153600
        dwDefaultFrameInterval         333333
        bFrameIntervalType                  4
        dwFrameInterval( 0)            333333
        dwFrameInterval( 1)            500000
        dwFrameInterval( 2)            666666
        dwFrameInterval( 3)          10000000
      VideoStreaming Interface Descriptor:
        bLength                            42
        bDescriptorType                    36
        bDescriptorSubtype                  5 (FRAME_UNCOMPRESSED)
        bFrameIndex                         7
        bmCapabilities                   0x00
          Still image unsupported
        wWidth                            176
        wHeight                           144
        dwMinBitRate                   912384
        dwMaxBitRate                   912384
        dwMaxVideoFrameBufferSize       50688
        dwDefaultFrameInterval         333333
        bFrameIntervalType                  4
        dwFrameInterval( 0)            333333
        dwFrameInterval( 1)            500000
        dwFrameInterval( 2)            666666
        dwFrameInterval( 3)          10000000
      VideoStreaming Interface Descriptor:
        bLength                            42
        bDescriptorType                    36
        bDescriptorSubtype                  5 (FRAME_UNCOMPRESSED)
        bFrameIndex                         8
        bmCapabilities                   0x00
          Still image unsupported
        wWidth                            160
        wHeight                           120
        dwMinBitRate                   912384
        dwMaxBitRate                   912384
        dwMaxVideoFrameBufferSize       38400
        dwDefaultFrameInterval         333333
        bFrameIntervalType                  4
        dwFrameInterval( 0)            333333
        dwFrameInterval( 1)            500000
        dwFrameInterval( 2)            666666
        dwFrameInterval( 3)          10000000
      VideoStreaming Interface Descriptor:
        bLength                            42
        bDescriptorType                    36
        bDescriptorSubtype                  5 (FRAME_UNCOMPRESSED)
        bFrameIndex                         9
        bmCapabilities                   0x00
          Still image unsupported
        wWidth                            640
        wHeight                           480
        dwMinBitRate                   912384
        dwMaxBitRate                   912384
        dwMaxVideoFrameBufferSize      614400
        dwDefaultFrameInterval        1000000
        bFrameIntervalType                  4
        dwFrameInterval( 0)           1000000
        dwFrameInterval( 1)           1333332
        dwFrameInterval( 2)           2000000
        dwFrameInterval( 3)          10000000
      VideoStreaming Interface Descriptor:
        bLength                            42
        bDescriptorType                    36
        bDescriptorSubtype                  5 (FRAME_UNCOMPRESSED)
        bFrameIndex                        10
        bmCapabilities                   0x00
          Still image unsupported
        wWidth                            640
        wHeight                           480
        dwMinBitRate                   912384
        dwMaxBitRate                   912384
        dwMaxVideoFrameBufferSize      614400
        dwDefaultFrameInterval        1000000
        bFrameIntervalType                  4
        dwFrameInterval( 0)           1000000
        dwFrameInterval( 1)           1333332
        dwFrameInterval( 2)           2000000
        dwFrameInterval( 3)          10000000
      VideoStreaming Interface Descriptor:
        bLength                            30
        bDescriptorType                    36
        bDescriptorSubtype                  3 (STILL_IMAGE_FRAME)
        bEndpointAddress                    0
        bNumImageSizePatterns               6
        wWidth( 0)                        640
        wHeight( 0)                       480
        wWidth( 1)                        352
        wHeight( 1)                       288
        wWidth( 2)                        320
        wHeight( 2)                       240
        wWidth( 3)                        176
        wHeight( 3)                       144
        wWidth( 4)                        160
        wHeight( 4)                       120
        wWidth( 5)                       1280
        wHeight( 5)                      1024
        bNumCompressionPatterns             6
      VideoStreaming Interface Descriptor:
        bLength                             6
        bDescriptorType                    36
        bDescriptorSubtype                 13 (COLORFORMAT)
        bColorPrimaries                     0 (Unspecified)
        bTransferCharacteristics            0 (Unspecified)
        bMatrixCoefficients                 0 (Unspecified)
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        1
      bAlternateSetting       1
      bNumEndpoints           1
      bInterfaceClass        14 Video
      bInterfaceSubClass      2 Video Streaming
      bInterfaceProtocol      0 
      iInterface              0 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x81  EP 1 IN
        bmAttributes            5
          Transfer Type            Isochronous
          Synch Type               Asynchronous
          Usage Type               Data
        wMaxPacketSize     0x1400  3x 1024 bytes
        bInterval               1
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        1
      bAlternateSetting       2
      bNumEndpoints           1
      bInterfaceClass        14 Video
      bInterfaceSubClass      2 Video Streaming
      bInterfaceProtocol      0 
      iInterface              0 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x81  EP 1 IN
        bmAttributes            5
          Transfer Type            Isochronous
          Synch Type               Asynchronous
          Usage Type               Data
        wMaxPacketSize     0x1340  3x 832 bytes
        bInterval               1
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        1
      bAlternateSetting       3
      bNumEndpoints           1
      bInterfaceClass        14 Video
      bInterfaceSubClass      2 Video Streaming
      bInterfaceProtocol      0 
      iInterface              0 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x81  EP 1 IN
        bmAttributes            5
          Transfer Type            Isochronous
          Synch Type               Asynchronous
          Usage Type               Data
        wMaxPacketSize     0x1300  3x 768 bytes
        bInterval               1
    Interface Descriptor:
      bLength                 9
      bDescriptorType         4
      bInterfaceNumber        1
      bAlternateSetting       4
      bNumEndpoints           1
      bInterfaceClass        14 Video
      bInterfaceSubClass      2 Video Streaming
      bInterfaceProtocol      0 
      iInterface              0 
      Endpoint Descriptor:
        bLength                 7
        bDescriptorType         5
        bEndpointAddress     0x81  EP 1 IN
        bmAttributes            5
          Transfer Type            Isochronous
          Synch Type               Asynchronous
          Usage Type               Data
        wMaxPacketSize     0x12c0  3x 704 bytes
        bInterval               1
Device Qualifier (for other device speed):
  bLength                10
  bDescriptorType         6
  bcdUSB               2.00
  bDeviceClass          239 Miscellaneous Device
  bDeviceSubClass         2 ?
  bDeviceProtocol         1 Interface Association
  bMaxPacketSize0        64
  bNumConfigurations      1
Device Status:     0x0000
  (Bus Powered)

From u.kleine-koenig at pengutronix.de  Thu Mar 29 17:12:31 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 29 Mar 2012 23:12:31 +0200
Subject: [PATCH 14/17] media/video/s5p-tv: mark const init data with
 __initconst instead of __initdata
In-Reply-To: <20120329211131.GA31250@pengutronix.de>
References: <20120329211131.GA31250@pengutronix.de>
Message-ID: <1333055554-31300-14-git-send-email-u.kleine-koenig@pengutronix.de>

As long as there is no other non-const variable marked __initdata in the
same compilation unit it doesn't hurt. If there were one however
compilation would fail with

	error: $variablename causes a section type conflict

because a section containing const variables is marked read only and so
cannot contain non-const variables.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
Cc: Kyungmin Park <kyungmin.park at samsung.com>
Cc: Tomasz Stanislawski <t.stanislaws at samsung.com>
Cc: Mauro Carvalho Chehab <mchehab at infradead.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-media at vger.kernel.org
---
 drivers/media/video/s5p-tv/mixer_drv.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/media/video/s5p-tv/mixer_drv.c b/drivers/media/video/s5p-tv/mixer_drv.c
index a2c0c25..edca065 100644
--- a/drivers/media/video/s5p-tv/mixer_drv.c
+++ b/drivers/media/video/s5p-tv/mixer_drv.c
@@ -461,7 +461,7 @@ static struct platform_driver mxr_driver __refdata = {
 static int __init mxr_init(void)
 {
 	int i, ret;
-	static const char banner[] __initdata = KERN_INFO
+	static const char banner[] __initconst = KERN_INFO
 		"Samsung TV Mixer driver, "
 		"(c) 2010-2011 Samsung Electronics Co., Ltd.\n";
 	printk(banner);
-- 
1.7.9.1



From u.kleine-koenig at pengutronix.de  Thu Mar 29 17:12:20 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 29 Mar 2012 23:12:20 +0200
Subject: [PATCH 03/17] ARM: mark const init data with __initconst instead of
 __initdata
In-Reply-To: <20120329211131.GA31250@pengutronix.de>
References: <20120329211131.GA31250@pengutronix.de>
Message-ID: <1333055554-31300-3-git-send-email-u.kleine-koenig@pengutronix.de>

As long as there is no other non-const variable marked __initdata in the
same compilation unit it doesn't hurt. If there were one however
compilation would fail with

	error: $variablename causes a section type conflict

because a section containing const variables is marked read only and so
cannot contain non-const variables.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
Cc: Andrew Victor <linux at maxim.org.za>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj at jcrosoft.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Sascha Hauer <kernel at pengutronix.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Lennert Buytenhek <kernel at wantstofly.org>
Cc: Nicolas Pitre <nico at fluxnic.net>
Cc: Eric Miao <eric.y.miao at gmail.com>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: David Brown <davidb at codeaurora.org>
Cc: Daniel Walker <dwalker at fifo99.com>
Cc: Bryan Huntsman <bryanh at codeaurora.org>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Barry Song <baohua.song at csr.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Lucas De Marchi <lucas.demarchi at profusion.mobi>
Cc: linux-arm-kernel at lists.infradead.org
Cc: davinci-linux-open-source at linux.davincidsp.com
Cc: linux-samsung-soc at vger.kernel.org
Cc: linux-arm-msm at vger.kernel.org
Cc: linux-omap at vger.kernel.org
---
 arch/arm/mach-at91/board-dt.c                 |    2 +-
 arch/arm/mach-at91/clock.c                    |    2 +-
 arch/arm/mach-davinci/board-tnetv107x-evm.c   |    6 ++--
 arch/arm/mach-davinci/da830.c                 |   48 ++++++++++++------------
 arch/arm/mach-davinci/da850.c                 |    6 ++--
 arch/arm/mach-dove/addr-map.c                 |    2 +-
 arch/arm/mach-exynos/mach-exynos4-dt.c        |    2 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c        |    2 +-
 arch/arm/mach-imx/imx27-dt.c                  |    2 +-
 arch/arm/mach-imx/imx51-dt.c                  |    2 +-
 arch/arm/mach-imx/imx53-dt.c                  |    2 +-
 arch/arm/mach-imx/mach-imx6q.c                |    2 +-
 arch/arm/mach-kirkwood/addr-map.c             |    2 +-
 arch/arm/mach-mmp/mmp-dt.c                    |    2 +-
 arch/arm/mach-msm/board-msm8x60.c             |    2 +-
 arch/arm/mach-msm/board-qsd8x50.c             |    4 +-
 arch/arm/mach-omap2/board-generic.c           |    8 ++--
 arch/arm/mach-omap2/display.c                 |    6 ++--
 arch/arm/mach-omap2/voltagedomains3xxx_data.c |    2 +-
 arch/arm/mach-omap2/voltagedomains44xx_data.c |    2 +-
 arch/arm/mach-orion5x/addr-map.c              |    2 +-
 arch/arm/mach-prima2/prima2.c                 |    2 +-
 22 files changed, 55 insertions(+), 55 deletions(-)

diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index c18d4d3..1c48ea2 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -48,7 +48,7 @@ static void __init at91_dt_device_init(void)
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char *at91_dt_board_compat[] __initdata = {
+static const char *at91_dt_board_compat[] __initconst = {
 	"atmel,at91sam9m10g45ek",
 	"atmel,at91sam9x5ek",
 	"calao,usb-a9g20",
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index a0f4d74..e4a255d 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -613,7 +613,7 @@ fail:
 	return 0;
 }
 
-static struct clk *const standard_pmc_clocks[] __initdata = {
+static struct clk *const standard_pmc_clocks[] __initconst = {
 	/* four primary clocks */
 	&clk32k,
 	&main_clk,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index 5f14e30..645a587 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -88,7 +88,7 @@ static struct davinci_mmc_config mmc_config = {
 	.version	= MMC_CTLR_VERSION_1,
 };
 
-static const short sdio1_pins[] __initdata = {
+static const short sdio1_pins[] __initconst = {
 	TNETV107X_SDIO1_CLK_1,		TNETV107X_SDIO1_CMD_1,
 	TNETV107X_SDIO1_DATA0_1,	TNETV107X_SDIO1_DATA1_1,
 	TNETV107X_SDIO1_DATA2_1,	TNETV107X_SDIO1_DATA3_1,
@@ -96,12 +96,12 @@ static const short sdio1_pins[] __initdata = {
 	-1
 };
 
-static const short uart1_pins[] __initdata = {
+static const short uart1_pins[] __initconst = {
 	TNETV107X_UART1_RD,		TNETV107X_UART1_TD,
 	-1
 };
 
-static const short ssp_pins[] __initdata = {
+static const short ssp_pins[] __initconst = {
 	TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
 	TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
 	TNETV107X_SSP1_3, -1
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index deee5c2..510648e 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -838,7 +838,7 @@ static const struct mux_config da830_pins[] = {
 #endif
 };
 
-const short da830_emif25_pins[] __initdata = {
+const short da830_emif25_pins[] __initconst = {
 	DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
 	DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
 	DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
@@ -853,19 +853,19 @@ const short da830_emif25_pins[] __initdata = {
 	-1
 };
 
-const short da830_spi0_pins[] __initdata = {
+const short da830_spi0_pins[] __initconst = {
 	DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
 	DA830_NSPI0_SCS_0,
 	-1
 };
 
-const short da830_spi1_pins[] __initdata = {
+const short da830_spi1_pins[] __initconst = {
 	DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
 	DA830_NSPI1_SCS_0,
 	-1
 };
 
-const short da830_mmc_sd_pins[] __initdata = {
+const short da830_mmc_sd_pins[] __initconst = {
 	DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
 	DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
 	DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
@@ -873,32 +873,32 @@ const short da830_mmc_sd_pins[] __initdata = {
 	-1
 };
 
-const short da830_uart0_pins[] __initdata = {
+const short da830_uart0_pins[] __initconst = {
 	DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
 	-1
 };
 
-const short da830_uart1_pins[] __initdata = {
+const short da830_uart1_pins[] __initconst = {
 	DA830_UART1_RXD, DA830_UART1_TXD,
 	-1
 };
 
-const short da830_uart2_pins[] __initdata = {
+const short da830_uart2_pins[] __initconst = {
 	DA830_UART2_RXD, DA830_UART2_TXD,
 	-1
 };
 
-const short da830_usb20_pins[] __initdata = {
+const short da830_usb20_pins[] __initconst = {
 	DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
 	-1
 };
 
-const short da830_usb11_pins[] __initdata = {
+const short da830_usb11_pins[] __initconst = {
 	DA830_USB_REFCLKIN,
 	-1
 };
 
-const short da830_uhpi_pins[] __initdata = {
+const short da830_uhpi_pins[] __initconst = {
 	DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
 	DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
 	DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
@@ -909,14 +909,14 @@ const short da830_uhpi_pins[] __initdata = {
 	-1
 };
 
-const short da830_cpgmac_pins[] __initdata = {
+const short da830_cpgmac_pins[] __initconst = {
 	DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
 	DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
 	DA830_MDIO_D,
 	-1
 };
 
-const short da830_emif3c_pins[] __initdata = {
+const short da830_emif3c_pins[] __initconst = {
 	DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
 	DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
 	DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
@@ -935,7 +935,7 @@ const short da830_emif3c_pins[] __initdata = {
 	-1
 };
 
-const short da830_mcasp0_pins[] __initdata = {
+const short da830_mcasp0_pins[] __initconst = {
 	DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
 	DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
 	DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
@@ -945,7 +945,7 @@ const short da830_mcasp0_pins[] __initdata = {
 	-1
 };
 
-const short da830_mcasp1_pins[] __initdata = {
+const short da830_mcasp1_pins[] __initconst = {
 	DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
 	DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
 	DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
@@ -954,24 +954,24 @@ const short da830_mcasp1_pins[] __initdata = {
 	-1
 };
 
-const short da830_mcasp2_pins[] __initdata = {
+const short da830_mcasp2_pins[] __initconst = {
 	DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
 	DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
 	DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
 	-1
 };
 
-const short da830_i2c0_pins[] __initdata = {
+const short da830_i2c0_pins[] __initconst = {
 	DA830_I2C0_SDA, DA830_I2C0_SCL,
 	-1
 };
 
-const short da830_i2c1_pins[] __initdata = {
+const short da830_i2c1_pins[] __initconst = {
 	DA830_I2C1_SCL, DA830_I2C1_SDA,
 	-1
 };
 
-const short da830_lcdcntl_pins[] __initdata = {
+const short da830_lcdcntl_pins[] __initconst = {
 	DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
 	DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
 	DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
@@ -981,34 +981,34 @@ const short da830_lcdcntl_pins[] __initdata = {
 	-1
 };
 
-const short da830_pwm_pins[] __initdata = {
+const short da830_pwm_pins[] __initconst = {
 	DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
 	DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
 	DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
 	-1
 };
 
-const short da830_ecap0_pins[] __initdata = {
+const short da830_ecap0_pins[] __initconst = {
 	DA830_ECAP0_APWM0,
 	-1
 };
 
-const short da830_ecap1_pins[] __initdata = {
+const short da830_ecap1_pins[] __initconst = {
 	DA830_ECAP1_APWM1,
 	-1
 };
 
-const short da830_ecap2_pins[] __initdata = {
+const short da830_ecap2_pins[] __initconst = {
 	DA830_ECAP2_APWM2,
 	-1
 };
 
-const short da830_eqep0_pins[] __initdata = {
+const short da830_eqep0_pins[] __initconst = {
 	DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
 	-1
 };
 
-const short da830_eqep1_pins[] __initdata = {
+const short da830_eqep1_pins[] __initconst = {
 	DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
 	-1
 };
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b44dc84..6676dee 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -576,17 +576,17 @@ static const struct mux_config da850_pins[] = {
 #endif
 };
 
-const short da850_i2c0_pins[] __initdata = {
+const short da850_i2c0_pins[] __initconst = {
 	DA850_I2C0_SDA, DA850_I2C0_SCL,
 	-1
 };
 
-const short da850_i2c1_pins[] __initdata = {
+const short da850_i2c1_pins[] __initconst = {
 	DA850_I2C1_SCL, DA850_I2C1_SDA,
 	-1
 };
 
-const short da850_lcdcntl_pins[] __initdata = {
+const short da850_lcdcntl_pins[] __initconst = {
 	DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
 	DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
 	DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
index 98b8c83b..93ea37d 100644
--- a/arch/arm/mach-dove/addr-map.c
+++ b/arch/arm/mach-dove/addr-map.c
@@ -49,7 +49,7 @@ static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.bridge_virt_base = BRIDGE_VIRT_BASE,
 };
 
-static const struct __initdata orion_addr_map_info addr_map_info[] = {
+static const struct orion_addr_map_info addr_map_info[] __initconst = {
 	/*
 	 * Windows for PCIe IO+MEM space.
 	 */
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 8245f1c..2b76302 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -72,7 +72,7 @@ static void __init exynos4210_dt_machine_init(void)
 				exynos4210_auxdata_lookup, NULL);
 }
 
-static char const *exynos4210_dt_compat[] __initdata = {
+static char const *exynos4210_dt_compat[] __initconst = {
 	"samsung,exynos4210",
 	NULL
 };
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 0d26f50..9969dc1 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -61,7 +61,7 @@ static void __init exynos5250_dt_machine_init(void)
 				exynos5250_auxdata_lookup, NULL);
 }
 
-static char const *exynos5250_dt_compat[] __initdata = {
+static char const *exynos5250_dt_compat[] __initconst = {
 	"samsung,exynos5250",
 	NULL
 };
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 861ceb8..a797d68 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -72,7 +72,7 @@ static struct sys_timer imx27_timer = {
 	.init = imx27_timer_init,
 };
 
-static const char *imx27_dt_board_compat[] __initdata = {
+static const char *imx27_dt_board_compat[] __initconst = {
 	"fsl,imx27",
 	NULL
 };
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 5cca573..7e00748 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -102,7 +102,7 @@ static struct sys_timer imx51_timer = {
 	.init = imx51_timer_init,
 };
 
-static const char *imx51_dt_board_compat[] __initdata = {
+static const char *imx51_dt_board_compat[] __initconst = {
 	"fsl,imx51-babbage",
 	"fsl,imx51",
 	NULL
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 4172279..0a02129 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -109,7 +109,7 @@ static struct sys_timer imx53_timer = {
 	.init = imx53_timer_init,
 };
 
-static const char *imx53_dt_board_compat[] __initdata = {
+static const char *imx53_dt_board_compat[] __initconst = {
 	"fsl,imx53-ard",
 	"fsl,imx53-evk",
 	"fsl,imx53-qsb",
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index da6c1d9..59fd7de 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -129,7 +129,7 @@ static struct sys_timer imx6q_timer = {
 	.init = imx6q_timer_init,
 };
 
-static const char *imx6q_dt_compat[] __initdata = {
+static const char *imx6q_dt_compat[] __initconst = {
 	"fsl,imx6q-arm2",
 	"fsl,imx6q-sabrelite",
 	"fsl,imx6q",
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index e9a7180..8ebb4ba 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -44,7 +44,7 @@ static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.bridge_virt_base = BRIDGE_VIRT_BASE,
 };
 
-static const struct __initdata orion_addr_map_info addr_map_info[] = {
+static const struct __initconst orion_addr_map_info addr_map_info[] = {
 	/*
 	 * Windows for PCIe IO+MEM space.
 	 */
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index 6707539..43755ec 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -61,7 +61,7 @@ static void __init mmp_dt_init(void)
 			     mmp_auxdata_lookup, NULL);
 }
 
-static const char *pxa168_dt_board_compat[] __initdata = {
+static const char *pxa168_dt_board_compat[] __initconst = {
 	"mrvl,pxa168-aspenite",
 	NULL,
 };
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 962e711..25597f5 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -92,7 +92,7 @@ static void __init msm8x60_dt_init(void)
 			msm_auxdata_lookup, NULL);
 }
 
-static const char *msm8x60_fluid_match[] __initdata = {
+static const char *msm8x60_fluid_match[] __initconst = {
 	"qcom,msm8660-fluid",
 	"qcom,msm8660-surf",
 	NULL
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 7e8909c..11de242 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -39,8 +39,8 @@
 
 extern struct sys_timer msm_timer;
 
-static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
-static const unsigned        qsd8x50_surf_smc91x_gpio __initdata = 156;
+static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300;
+static const unsigned        qsd8x50_surf_smc91x_gpio __initconst = 156;
 
 /* Leave smc91x resources empty here, as we'll fill them in
  * at run-time: they vary from board to board, and the true
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 74e1687..635dee4 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -57,7 +57,7 @@ static void __init omap_generic_init(void)
 }
 
 #ifdef CONFIG_SOC_OMAP2420
-static const char *omap242x_boards_compat[] __initdata = {
+static const char *omap242x_boards_compat[] __initconst = {
 	"ti,omap2420",
 	NULL,
 };
@@ -76,7 +76,7 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_SOC_OMAP2430
-static const char *omap243x_boards_compat[] __initdata = {
+static const char *omap243x_boards_compat[] __initconst = {
 	"ti,omap2430",
 	NULL,
 };
@@ -111,7 +111,7 @@ static void __init omap3_init(void)
 	omap_generic_init();
 }
 
-static const char *omap3_boards_compat[] __initdata = {
+static const char *omap3_boards_compat[] __initconst = {
 	"ti,omap3",
 	NULL,
 };
@@ -146,7 +146,7 @@ static void __init omap4_init(void)
 	omap_generic_init();
 }
 
-static const char *omap4_boards_compat[] __initdata = {
+static const char *omap4_boards_compat[] __initconst = {
 	"ti,omap4",
 	NULL,
 };
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 9706c64..df2ef11 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -74,14 +74,14 @@ struct omap_dss_hwmod_data {
 	const int id;
 };
 
-static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
 	{ "dss_core", "omapdss_dss", -1 },
 	{ "dss_dispc", "omapdss_dispc", -1 },
 	{ "dss_rfbi", "omapdss_rfbi", -1 },
 	{ "dss_venc", "omapdss_venc", -1 },
 };
 
-static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
 	{ "dss_core", "omapdss_dss", -1 },
 	{ "dss_dispc", "omapdss_dispc", -1 },
 	{ "dss_rfbi", "omapdss_rfbi", -1 },
@@ -89,7 +89,7 @@ static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
 	{ "dss_dsi1", "omapdss_dsi", 0 },
 };
 
-static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
 	{ "dss_core", "omapdss_dss", -1 },
 	{ "dss_dispc", "omapdss_dispc", -1 },
 	{ "dss_rfbi", "omapdss_rfbi", -1 },
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index 57db203..0819a02 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -96,7 +96,7 @@ static struct voltagedomain *voltagedomains_am35xx[] __initdata = {
 };
 
 
-static const char *sys_clk_name __initdata = "sys_ck";
+static const char *sys_clk_name __initconst = "sys_ck";
 
 void __init omap3xxx_voltagedomains_init(void)
 {
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
index c3115f6..787ce89 100644
--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -89,7 +89,7 @@ static struct voltagedomain *voltagedomains_omap4[] __initdata = {
 	NULL,
 };
 
-static const char *sys_clk_name __initdata = "sys_clkin_ck";
+static const char *sys_clk_name __initconst = "sys_clkin_ck";
 
 void __init omap44xx_voltagedomains_init(void)
 {
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 3638e5c..83a3d0b 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -82,7 +82,7 @@ static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
 };
 
-static const struct __initdata orion_addr_map_info addr_map_info[] = {
+static const struct __initconst orion_addr_map_info addr_map_info[] = {
 	/*
 	 * Setup windows for PCI+PCIe IO+MEM space.
 	 */
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
index 02b9c05..978fa2f 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/prima2.c
@@ -25,7 +25,7 @@ void __init sirfsoc_mach_init(void)
 	of_platform_bus_probe(NULL, sirfsoc_of_bus_ids, NULL);
 }
 
-static const char *prima2cb_dt_match[] __initdata = {
+static const char *prima2cb_dt_match[] __initconst = {
        "sirf,prima2-cb",
        NULL
 };
-- 
1.7.9.1



From linus.walleij at linaro.org  Thu Mar 29 17:22:55 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Thu, 29 Mar 2012 23:22:55 +0200
Subject: [PATCH] serial: PL011: move interrupt clearing
In-Reply-To: <CACxGe6u+KeYzWwiJ7MK7pWG444Y99CQ1LLCZP4m3R=zdYFR_pg@mail.gmail.com>
References: <1332357318-8017-1-git-send-email-linus.walleij@linaro.org>
 <CACxGe6u+KeYzWwiJ7MK7pWG444Y99CQ1LLCZP4m3R=zdYFR_pg@mail.gmail.com>
Message-ID: <CACRpkdZ4pxUDpe3aEv3y_Smn5K17f_Q5G-k=EVPzw8NvxpF2iw@mail.gmail.com>

On Thu, Mar 29, 2012 at 10:49 PM, Grant Likely
<grant.likely at secretlab.ca> wrote:

>> Commit 360f748b204275229f8398cb2f9f53955db1503b
>> "serial: PL011: clear pending interrupts"
>> attempts to clear interrupts by writing to a
>> yet-unassigned memory address. This fixes the issue.
>
> Ugh; the original patch is obviously broken. ?How did it get applied
> without testing?

I've felt bad about that for a while, but to the best of my knowledge I did
test it. Either I did some manual slip with the boot images or there was
something else causing it to actually work as it looked... Chanho also
had it working IIRC.

> Greg, can you get this out to Linus ASAP please? ?I have one comment
> below, but I don't think it should block merging this patch.
>
> Tested-by: Grant Likely <grant.likely at secretlab.ca>

Thanks.

>> - ? ? ? /* Ensure interrupts from this UART are masked and cleared */
>> - ? ? ? writew(0, uap->port.membase + UART011_IMSC);
>> - ? ? ? writew(0xffff, uap->port.membase + UART011_ICR);
>> -
>> ? ? ? ?uap->vendor = vendor;
>> ? ? ? ?uap->lcrh_rx = vendor->lcrh_rx;
>> ? ? ? ?uap->lcrh_tx = vendor->lcrh_tx;
>> @@ -1951,6 +1947,10 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
>> ? ? ? ?uap->port.line = i;
>> ? ? ? ?pl011_dma_probe(uap);
>>
>> + ? ? ? /* Ensure interrupts from this UART are masked and cleared */
>> + ? ? ? writew(0, uap->port.membase + UART011_IMSC);
>> + ? ? ? writew(0xffff, uap->port.membase + UART011_ICR);
>> +
>
> Is it correct to move the interrupt clearing below the
> pl011_dma_probe() call? ?I've tested the fix with the interrupt
> clearing both above and below the pl011_dma_probe() call and versatile
> qemu boots in both cases.

pl011_dma_probe() basically just make logical setup so we do the
clear-out as the last step of setup.

Yours,
Linus Walleij


From gregkh at linuxfoundation.org  Thu Mar 29 17:33:33 2012
From: gregkh at linuxfoundation.org (Greg Kroah-Hartman)
Date: Thu, 29 Mar 2012 14:33:33 -0700
Subject: [PATCH] serial: PL011: move interrupt clearing
In-Reply-To: <CACxGe6u+KeYzWwiJ7MK7pWG444Y99CQ1LLCZP4m3R=zdYFR_pg@mail.gmail.com>
References: <1332357318-8017-1-git-send-email-linus.walleij@linaro.org>
 <CACxGe6u+KeYzWwiJ7MK7pWG444Y99CQ1LLCZP4m3R=zdYFR_pg@mail.gmail.com>
Message-ID: <20120329213333.GA15231@kroah.com>

On Thu, Mar 29, 2012 at 02:49:37PM -0600, Grant Likely wrote:
> On Wed, Mar 21, 2012 at 1:15 PM, Linus Walleij <linus.walleij at linaro.org> wrote:
> > Commit 360f748b204275229f8398cb2f9f53955db1503b
> > "serial: PL011: clear pending interrupts"
> > attempts to clear interrupts by writing to a
> > yet-unassigned memory address. This fixes the issue.
> >
> > The breaking patch is marked for stable so should be
> > carried along with the other patch.
> >
> > Cc: Shreshtha Kumar Sahu <shreshthakumar.sahu at stericsson.com>
> > Cc: Russell King <linux at arm.linux.org.uk>
> > Cc: stable <stable at vger.kernel.org>
> > Reported-by: Viresh Kumar <viresh.kumar at st.com>
> > Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> 
> Ugh; the original patch is obviously broken.  How did it get applied
> without testing?
> 
> Greg, can you get this out to Linus ASAP please?  I have one comment
> below, but I don't think it should block merging this patch.
> 
> Tested-by: Grant Likely <grant.likely at secretlab.ca>

Thanks, I'll get it to him after 3.4-rc1 is out, in a few days, along
with other tty fixes being queued up.

greg k-h


From broonie at opensource.wolfsonmicro.com  Thu Mar 29 17:41:10 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 29 Mar 2012 22:41:10 +0100
Subject: [PATCH v5 01/16] pwm: Add PWM framework support
In-Reply-To: <1332945238-14897-2-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-2-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120329214110.GF4153@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 04:33:43PM +0200, Thierry Reding wrote:
> From: Sascha Hauer <s.hauer at pengutronix.de>
> 
> This patch adds framework support for PWM (pulse width modulation) devices.

Looking good, hope we can get this in for 3.5!

Reviewed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
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From broonie at opensource.wolfsonmicro.com  Thu Mar 29 17:47:18 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 29 Mar 2012 22:47:18 +0100
Subject: [PATCH v5 05/16] pwm: Add device tree support
In-Reply-To: <1332945238-14897-6-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-6-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120329214717.GG4153@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 04:33:47PM +0200, Thierry Reding wrote:

> +	pwm-list ::= <single-pwm> [pwm-list]
> +	single-pwm ::= <pwm-phandle> <pwm-specifier>
> +	pwm-phandle : phandle to PWM controller node
> +	pwm-specifier : array of #pwm-cells specifying the given PWM
> +			(controller specific)

> +PWM properties should be named "pwms". The exact meaning of each pwms
> +property must be documented in the device tree binding for each device.
> +An optional property "pwm-names" may contain a list of strings to label
> +each of the PWM devices listed in the "pwms" property. If no "pwm-names"
> +property is given, the name of the user node will be used as fallback.

> +	pwm = pwm_request_from_chip(pc, args->args[0], NULL);
> +	if (IS_ERR(pwm))
> +		return ERR_PTR(-ENODEV);

It feels wrong to override the error code like this rather than passing
the error we got back to the caller.  Is there any great reason for
doing so?
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From broonie at opensource.wolfsonmicro.com  Thu Mar 29 17:50:13 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 29 Mar 2012 22:50:13 +0100
Subject: [PATCH v5 02/16] pwm: Allow chips to support multiple PWMs
In-Reply-To: <1332945238-14897-3-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-3-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120329215013.GH4153@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 04:33:44PM +0200, Thierry Reding wrote:
> Many PWM controllers provide access to more than a single PWM output and
> may even share some resource among them. Allowing a PWM chip to provide
> multiple PWM devices enables better sharing of those resources. As a
> side-effect this change allows easy integration with the device tree
> where a given PWM can be looked up based on the PWM chip's phandle and a
> corresponding index.

Reviewed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
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From broonie at opensource.wolfsonmicro.com  Thu Mar 29 17:56:00 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 29 Mar 2012 22:56:00 +0100
Subject: [PATCH v5 03/16] pwm: Add debugfs interface
In-Reply-To: <1332945238-14897-4-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-4-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120329215600.GJ4153@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 04:33:45PM +0200, Thierry Reding wrote:
> This commit adds a debugfs interface that can be used to list the
> current internal state of the PWM devices registered with the PWM
> framework.

Reviewed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

I'm not sure I don't find the style with a file per chip more managable,
but I think that's mostly a thing for GPIOs since you get so many of
them in most systems that the file gets large which isn't such an issue
with pwms, you tend to get much fewer of them.  It's certainly a matter
of taste anyway.
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From broonie at opensource.wolfsonmicro.com  Thu Mar 29 18:03:42 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 29 Mar 2012 23:03:42 +0100
Subject: [PATCH v5 04/16] pwm: Add table-based lookup for static mappings
In-Reply-To: <1332945238-14897-5-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-5-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <20120329220342.GK4153@opensource.wolfsonmicro.com>

On Wed, Mar 28, 2012 at 04:33:46PM +0200, Thierry Reding wrote:

> +	static struct pwm_lookup board_pwm_lookup[] = {
> +		PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight"),
> +	};

The clock and regulator APIs namespace the consumers by struct device -
might this not be sensible here?  pwm_get() does already take the device
as an argument.  It'd feel safer, and for example there's plenty of
phones out there with two backlit displays...

> + * pwm_get() - look up and request a PWM device
> + * @dev: device for PWM consumer
> + * @provider: name of provider PWM chip
> + * @index: per-chip index of PWM to request

The documentation is out of sync with the signature.
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From rmallon at gmail.com  Thu Mar 29 18:21:12 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Fri, 30 Mar 2012 09:21:12 +1100
Subject: [PATCH 1/3] PATA host controller driver for ep93xx
In-Reply-To: <4F741AB1.4000107@metasoft.pl>
References: <4F7418E7.4060500@metasoft.pl> <4F741AB1.4000107@metasoft.pl>
Message-ID: <4F74E058.3010607@gmail.com>

On 29/03/12 19:17, Rafal Prylowski wrote:

> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
> Cc: Joao Ramos <joao.ramos at inov.pt>
> Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <ryan at bluewatersys.com>
> Cc: Sergei Shtylyov <sshtylyov at ru.montavista.com>
> Cc: Bartlomiej Zolnierkiewicz <bzolnier at gmail.com>

Hi Rafal,

A few style comments below.

~Ryan

> ---
>  drivers/ata/Kconfig       |    9
>  drivers/ata/Makefile      |    1
>  drivers/ata/pata_ep93xx.c |  949 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 959 insertions(+)
> 
> Index: linux-2.6/drivers/ata/pata_ep93xx.c
> ===================================================================
> --- /dev/null
> +++ linux-2.6/drivers/ata/pata_ep93xx.c
> @@ -0,0 +1,949 @@
> +/*
> + * EP93XX PATA controller driver.
> + *
> + * Copyright (c) 2012, Metasoft s.c.
> + *	Rafal Prylowski <prylowski at metasoft.pl>
> + *
> + * Based on pata_scc.c, pata_icside.c and on earlier version of EP93XX
> + * PATA driver by Lennert Buytenhek and Alessandro Zummo.
> + * Read/Write timings, resource management and other improvements
> + * from driver by Joao Ramos and Bartlomiej Zolnierkiewicz.
> + * DMA engine support based on spi-ep93xx.c by Mika Westerberg.
> + *
> + * Original copyrights:
> + *
> + * Support for Cirrus Logic's EP93xx (EP9312, EP9315) CPUs
> + * PATA host controller driver.
> + *
> + * Copyright (c) 2009, Bartlomiej Zolnierkiewicz
> + *
> + * Heavily based on the ep93xx-ide.c driver:
> + *
> + * Copyright (c) 2009, Joao Ramos <joao.ramos at inov.pt>
> + *		      INESC Inovacao (INOV)
> + *
> + * EP93XX PATA controller driver.
> + * Copyright (C) 2007 Lennert Buytenhek <buytenh at wantstofly.org>
> + *
> + * An ATA driver for the Cirrus Logic EP93xx PATA controller.
> + *
> + * Based on an earlier version by Alessandro Zummo, which is:
> + *   Copyright (C) 2006 Tower Technologies
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/blkdev.h>
> +#include <scsi/scsi_host.h>
> +#include <linux/ata.h>
> +#include <linux/libata.h>
> +#include <linux/platform_device.h>
> +#include <linux/delay.h>
> +#include <linux/dmaengine.h>
> +
> +#include <mach/dma.h>
> +#include <asm/mach-types.h>
> +#include <mach/ep93xx-regs.h>


ep93xx-regs.h is now deprecated for inclusion in drivers :-).

> +#include <mach/platform.h>
> +
> +#define DRV_NAME	"ep93xx-ide"
> +#define DRV_VERSION	"1.0"
> +
> +enum {
> +	/* IDE Control Register */
> +	IDECtrl				= 0x00,


Please don't use horrible camel case names.

> +	IDECtrl_CS0n			= (1 << 0),
> +	IDECtrl_CS1n			= (1 << 1),
> +	IDECtrl_DIORn			= (1 << 5),
> +	IDECtrl_DIOWn			= (1 << 6),
> +	IDECtrl_INTRQ			= (1 << 9),
> +	IDECtrl_IORDY			= (1 << 10),
> +
> +	/* IDE Configuration Register */
> +	IDECfg				= 0x04,
> +	IDECfg_IDEEN			= (1 << 0),


Why is this one enum, when you have multiple constants which define to
the same value? This probably makes more sense as a set of defines.

> +	IDECfg_PIO			= (1 << 1),
> +	IDECfg_MDMA			= (1 << 2),
> +	IDECfg_UDMA			= (1 << 3),
> +	IDECfg_MODE_SHIFT		= 4,
> +	IDECfg_MODE_MASK		= (0xf << 4),
> +	IDECfg_WST_SHIFT		= 8,
> +	IDECfg_WST_MASK			= (0x3 << 8),
> +
> +	/* MDMA Operation Register */
> +	IDEMDMAOp			= 0x08,
> +
> +	/* UDMA Operation Register */
> +	IDEUDMAOp			= 0x0c,
> +	IDEUDMAOp_UEN			= (1 << 0),
> +	IDEUDMAOp_RWOP			= (1 << 1),
> +
> +	/* PIO/MDMA/UDMA Data Registers */
> +	IDEDataOut			= 0x10,
> +	IDEDataIn			= 0x14,
> +	IDEMDMADataOut			= 0x18,
> +	IDEMDMADataIn			= 0x1c,
> +	IDEUDMADataOut			= 0x20,
> +	IDEUDMADataIn			= 0x24,
> +
> +	/* UDMA Status Register */
> +	IDEUDMASts			= 0x28,
> +	IDEUDMASts_DMAide		= (1 << 16),
> +	IDEUDMASts_INTide		= (1 << 17),
> +	IDEUDMASts_SBUSY		= (1 << 18),
> +	IDEUDMASts_NDO			= (1 << 24),
> +	IDEUDMASts_NDI			= (1 << 25),
> +	IDEUDMASts_N4X			= (1 << 26),
> +
> +	/* UDMA Debug Status Register */
> +	IDEUDMADebug			= 0x2c,
> +};
> +
> +struct ep93xx_pata_data /* private_data in ata_host */
> +{
> +	void __iomem *ide_base;
> +	const struct ata_timing *t, *cmd_t;


Nitpick: Usually each field in a structure definition is on its own line.

> +	bool iordy;
> +
> +	unsigned long udma_in_phys;
> +	unsigned long udma_out_phys;
> +
> +	struct dma_chan *dma_rx_channel;
> +	struct ep93xx_dma_data dma_rx_data;
> +	struct dma_chan *dma_tx_channel;
> +	struct ep93xx_dma_data dma_tx_data;
> +};
> +
> +static void ep93xx_pata_clear_regs(void __iomem *base)
> +{
> +	writel(IDECtrl_CS0n | IDECtrl_CS1n | IDECtrl_DIORn |
> +		IDECtrl_DIOWn, base + IDECtrl);
> +
> +	writel(0, base + IDECfg);


Might be worth having ep93xx_pata_write/read functions so you don't have
to do the base + thing everywhere. Passing struct ep93xx_pata_data to
each function would be more typical also.

> +	writel(0, base + IDEMDMAOp);
> +	writel(0, base + IDEUDMAOp);
> +	writel(0, base + IDEDataOut);
> +	writel(0, base + IDEDataIn);
> +	writel(0, base + IDEMDMADataOut);
> +	writel(0, base + IDEMDMADataIn);
> +	writel(0, base + IDEUDMADataOut);
> +	writel(0, base + IDEUDMADataIn);
> +	writel(0, base + IDEUDMADebug);
> +}
> +
> +static inline int ep93xx_pata_check_iordy(void __iomem *base)
> +{
> +	return (readl(base + IDECtrl) & IDECtrl_IORDY) ? 1 : 0;


You can use !! here rather than ? 1 : 0.

> +}
> +
> +/*
> + * According to EP93xx User's Guide, WST field of IDECfg specifies number
> + * of HCLK cycles to hold the data bus after a PIO write operation.
> + * It should be programmed to guarantee following delays:
> + *
> + * PIO Mode   [ns]
> + * 0          30
> + * 1          20
> + * 2          15
> + * 3          10
> + * 4          5
> + *
> + * Maximum possible value for HCLK is 100MHz.
> + */
> +static inline int ep93xx_pata_get_wst(int pio_mode)
> +{
> +	return (pio_mode == 0 ? 3 : pio_mode < 3 ? 2 : 1)
> +		<< IDECfg_WST_SHIFT;


Ick, thats really hard to read. What's wrong with:

  unsigned val = 1;

  if (pio_mode == 0)
  	val = 3;
  else if (pio_mode < 3)
  	val = 2;
  else
	val = 1;

  return val << IDECFG_WST_SHIFT;

> +}
> +
> +static inline void ep93xx_pata_enable_pio(void __iomem *base, int pio_mode)


Don't bother marking functions inline. The compiler will do it for you.

> +{
> +	writel(IDECfg_IDEEN | IDECfg_PIO |
> +		ep93xx_pata_get_wst(pio_mode) |
> +		(pio_mode << IDECfg_MODE_SHIFT), base + IDECfg);
> +}
> +
> +static u16 ep93xx_pata_read(struct ep93xx_pata_data *drv_data,
> +			    void *addr_io,
> +			    const struct ata_timing *t)
> +{
> +	unsigned long addr = (unsigned long) addr_io & 0x1f;
> +	void __iomem *base = drv_data->ide_base;
> +	u16 ret;
> +
> +	writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
> +	ndelay(t->setup);
> +	writel(IDECtrl_DIOWn | addr, base + IDECtrl);
> +	ndelay(t->act8b);
> +	if (drv_data->iordy) {
> +		/* min. 1s timeout (at cpu cycle = 5ns) */
> +		unsigned int timeout = 200000;


Probably be better to use jiffies, msecs_to_jiffies and
time_before/after rather than relying on a particular clock speed.

> +		while (!ep93xx_pata_check_iordy(base) && --timeout)
> +			cpu_relax();
> +	}
> +	/*
> +	 * The IDEDataIn register is loaded from the DD pins at the positive
> +	 * edge of the DIORn signal. (EP93xx UG p27-14)
> +	 */
> +	writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
> +	ret = readl(base + IDEDataIn);
> +	ndelay(t->cyc8b - t->act8b - t->setup);
> +	return ret;
> +}
> +
> +static void ep93xx_pata_write(struct ep93xx_pata_data *drv_data,
> +			      u16 value, void *addr_io,
> +			      const struct ata_timing *t)
> +{
> +	unsigned long addr = (unsigned long) addr_io & 0x1f;
> +	void __iomem *base = drv_data->ide_base;
> +
> +	writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
> +	ndelay(t->setup);
> +	/*
> +	 * Value from IDEDataOut register is driven onto the DD pins when
> +	 * DIOWn is low. (EP93xx UG p27-13)
> +	 */
> +	writel(value, base + IDEDataOut);
> +	writel(IDECtrl_DIORn | addr, base + IDECtrl);
> +	ndelay(t->act8b);
> +	if (drv_data->iordy) {
> +		/* min. 1s timeout */
> +		unsigned int timeout = 200000;
> +		while (!ep93xx_pata_check_iordy(base) && --timeout)
> +			cpu_relax();


This loop is used more than once. Wrap it up in a function maybe.

> +	}
> +	writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
> +	ndelay(t->cyc8b - t->act8b - t->setup);
> +}
> +
> +static void ep93xx_pata_set_piomode(struct ata_port *ap,
> +				    struct ata_device *adev)
> +{
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	struct ata_device *pair = ata_dev_pair(adev);
> +
> +	drv_data->t = ata_timing_find_mode(adev->pio_mode);
> +	drv_data->cmd_t = drv_data->t;
> +	drv_data->iordy = ata_pio_need_iordy(adev);
> +
> +	if (pair && pair->pio_mode < adev->pio_mode)
> +		drv_data->cmd_t = ata_timing_find_mode(pair->pio_mode);
> +
> +	ep93xx_pata_enable_pio(drv_data->ide_base,
> +			       adev->pio_mode - XFER_PIO_0);
> +}
> +
> +static u8 ep93xx_pata_check_status(struct ata_port *ap)
> +{
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	return ep93xx_pata_read(drv_data, ap->ioaddr.status_addr,
> +				drv_data->cmd_t);
> +}
> +
> +static u8 ep93xx_pata_check_altstatus(struct ata_port *ap)
> +{
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	return ep93xx_pata_read(drv_data, ap->ioaddr.altstatus_addr,
> +				drv_data->cmd_t);
> +}
> +
> +static void ep93xx_pata_tf_load(struct ata_port *ap,
> +				const struct ata_taskfile *tf)
> +{
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	const struct ata_timing *t = drv_data->cmd_t;
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
> +
> +	if (tf->ctl != ap->last_ctl) {
> +		ep93xx_pata_write(drv_data, tf->ctl, ioaddr->ctl_addr, t);
> +		ap->last_ctl = tf->ctl;
> +		ata_wait_idle(ap);
> +	}
> +
> +	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
> +		ep93xx_pata_write(drv_data, tf->hob_feature,
> +			ioaddr->feature_addr, t);
> +		ep93xx_pata_write(drv_data, tf->hob_nsect,
> +			ioaddr->nsect_addr, t);
> +		ep93xx_pata_write(drv_data, tf->hob_lbal,
> +			ioaddr->lbal_addr, t);
> +		ep93xx_pata_write(drv_data, tf->hob_lbam,
> +			ioaddr->lbam_addr, t);
> +		ep93xx_pata_write(drv_data, tf->hob_lbah,
> +			ioaddr->lbah_addr, t);
> +		VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
> +			tf->hob_feature, tf->hob_nsect, tf->hob_lbal,
> +			tf->hob_lbam, tf->hob_lbah);


  dev_vdbg(ap->host->dev, ...)

? Same elsewhere.

> +	}
> +
> +	if (is_addr) {
> +		ep93xx_pata_write(drv_data, tf->feature,
> +			ioaddr->feature_addr, t);
> +		ep93xx_pata_write(drv_data, tf->nsect, ioaddr->nsect_addr, t);
> +		ep93xx_pata_write(drv_data, tf->lbal, ioaddr->lbal_addr, t);
> +		ep93xx_pata_write(drv_data, tf->lbam, ioaddr->lbam_addr, t);
> +		ep93xx_pata_write(drv_data, tf->lbah, ioaddr->lbah_addr, t);
> +		VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
> +			tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
> +	}
> +
> +	if (tf->flags & ATA_TFLAG_DEVICE) {
> +		ep93xx_pata_write(drv_data, tf->device, ioaddr->device_addr, t);
> +		VPRINTK("device 0x%X\n", tf->device);
> +	}
> +
> +	ata_wait_idle(ap);
> +}
> +
> +static void ep93xx_pata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
> +{
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	const struct ata_timing *t = drv_data->cmd_t;
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +
> +	tf->command = ep93xx_pata_check_status(ap);
> +	tf->feature = ep93xx_pata_read(drv_data, ioaddr->feature_addr, t);
> +	tf->nsect = ep93xx_pata_read(drv_data, ioaddr->nsect_addr, t);
> +	tf->lbal = ep93xx_pata_read(drv_data, ioaddr->lbal_addr, t);
> +	tf->lbam = ep93xx_pata_read(drv_data, ioaddr->lbam_addr, t);
> +	tf->lbah = ep93xx_pata_read(drv_data, ioaddr->lbah_addr, t);
> +	tf->device = ep93xx_pata_read(drv_data, ioaddr->device_addr, t);
> +
> +	if (tf->flags & ATA_TFLAG_LBA48) {
> +		ep93xx_pata_write(drv_data, tf->ctl | ATA_HOB,
> +			ioaddr->ctl_addr, t);
> +		tf->hob_feature = ep93xx_pata_read(drv_data,
> +			ioaddr->feature_addr, t);
> +		tf->hob_nsect = ep93xx_pata_read(drv_data,
> +			ioaddr->nsect_addr, t);
> +		tf->hob_lbal = ep93xx_pata_read(drv_data,
> +			ioaddr->lbal_addr, t);
> +		tf->hob_lbam = ep93xx_pata_read(drv_data,
> +			ioaddr->lbam_addr, t);
> +		tf->hob_lbah = ep93xx_pata_read(drv_data,
> +			ioaddr->lbah_addr, t);
> +		ep93xx_pata_write(drv_data, tf->ctl, ioaddr->ctl_addr, t);
> +		ap->last_ctl = tf->ctl;
> +	}
> +}
> +
> +static void ep93xx_pata_exec_command(struct ata_port *ap,
> +				     const struct ata_taskfile *tf)
> +{
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);


  dev_dbg(ap->host->dev, ...);

> +
> +	ep93xx_pata_write(drv_data, tf->command,
> +			  ap->ioaddr.command_addr, drv_data->cmd_t);
> +	ata_sff_pause(ap);
> +}
> +
> +static void ep93xx_pata_dev_select(struct ata_port *ap, unsigned int device)
> +{
> +	u8 tmp;
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +
> +	if (device == 0)
> +		tmp = ATA_DEVICE_OBS;
> +	else
> +		tmp = ATA_DEVICE_OBS | ATA_DEV1;


This could be:

  u8 tmp = ATA_DEVICE_OBS;

  ...

  if (device != 0)
  	tmp |= ATA_DEV1;

> +
> +	ep93xx_pata_write(drv_data, tmp, ap->ioaddr.device_addr,
> +			  drv_data->cmd_t);
> +	ata_sff_pause(ap);	/* needed; also flushes, for mmio */
> +}
> +
> +static void ep93xx_pata_set_devctl(struct ata_port *ap, u8 ctl)
> +{
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	ep93xx_pata_write(drv_data, ctl, ap->ioaddr.ctl_addr,
> +			  drv_data->cmd_t);
> +}
> +
> +unsigned int ep93xx_pata_data_xfer(struct ata_device *adev, unsigned char *buf,
> +				   unsigned int buflen, int rw)
> +{
> +	struct ata_port *ap = adev->link->ap;
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	const struct ata_timing *t = drv_data->t;
> +	void *data_addr = ap->ioaddr.data_addr;
> +	u16 *data = (u16 *) buf;


No space after the cast.

> +	unsigned int words = buflen >> 1;
> +
> +	/* Transfer multiple of 2 bytes */
> +	if (rw == READ)
> +		while (words--)
> +			*data++ = cpu_to_le16(
> +				ep93xx_pata_read(drv_data, data_addr, t));
> +	else
> +		while (words--)
> +			ep93xx_pata_write(drv_data, le16_to_cpu(*data++),
> +				data_addr, t);


This would would be a bit simpler as:

  while (words--) {
  	if (rw == READ)
		*data++ = ...;
	else
		ep93xx_pata_write(...);
  }

> +
> +	/* Transfer trailing 1 byte, if any. */
> +	if (unlikely(buflen & 0x01)) {
> +		unsigned char pad[2] = { };

> +

> +		buf += buflen - 1;
> +
> +		if (rw == READ) {
> +			*pad = cpu_to_le16(
> +				ep93xx_pata_read(drv_data, data_addr, t));
> +			*buf = pad[0];
> +		} else {
> +			pad[0] = *buf;
> +			ep93xx_pata_write(drv_data, le16_to_cpu(*pad),
> +					  data_addr, t);
> +		}
> +		words++;
> +	}
> +
> +	return words << 1;
> +}
> +
> +static unsigned int ep93xx_pata_dev_check(struct ata_port *ap,
> +					  unsigned int device)
> +{
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	const struct ata_timing *t = drv_data->cmd_t;
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +	u8 nsect, lbal;
> +
> +	ap->ops->sff_dev_select(ap, device);
> +
> +	ep93xx_pata_write(drv_data, 0x55, ioaddr->nsect_addr, t);
> +	ep93xx_pata_write(drv_data, 0xaa, ioaddr->lbal_addr, t);
> +
> +	ep93xx_pata_write(drv_data, 0xaa, ioaddr->nsect_addr, t);
> +	ep93xx_pata_write(drv_data, 0x55, ioaddr->lbal_addr, t);
> +
> +	ep93xx_pata_write(drv_data, 0x55, ioaddr->nsect_addr, t);
> +	ep93xx_pata_write(drv_data, 0xaa, ioaddr->lbal_addr, t);
> +
> +	nsect = ep93xx_pata_read(drv_data, ioaddr->nsect_addr, t);
> +	lbal = ep93xx_pata_read(drv_data, ioaddr->lbal_addr, t);
> +
> +	if ((nsect == 0x55) && (lbal == 0xaa))
> +		return 1;	/* we found a device */
> +
> +	return 0;		/* nothing found */


This function should return a bool. Maybe also change the function name
to ep93xx_pata_device_is_present, which more accurately reflects what
this does. Then you can drop the comments above too.

> +}
> +
> +int ep93xx_pata_wait_after_reset(struct ata_link *link, unsigned int devmask,
> +				 unsigned long deadline)
> +{
> +	struct ata_port *ap = link->ap;
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	const struct ata_timing *t = drv_data->cmd_t;
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +	unsigned int dev0 = devmask & (1 << 0);
> +	unsigned int dev1 = devmask & (1 << 1);
> +	int rc, ret = 0;
> +
> +	ata_msleep(ap, ATA_WAIT_AFTER_RESET);
> +
> +	/* always check readiness of the master device */
> +	rc = ata_sff_wait_ready(link, deadline);
> +	/* -ENODEV means the odd clown forgot the D7 pulldown resistor
> +	 * and TF status is 0xff, bail out on it too.
> +	 */
> +	if (rc)
> +		return rc;
> +
> +	/* if device 1 was found in ata_devchk, wait for register
> +	 * access briefly, then wait for BSY to clear.
> +	 */


  /*
   * Mutli-line comment style
   * looks like this.
   */

> +	if (dev1) {
> +		int i;
> +
> +		ap->ops->sff_dev_select(ap, 1);
> +
> +		/* Wait for register access.  Some ATAPI devices fail
> +		 * to set nsect/lbal after reset, so don't waste too
> +		 * much time on it.  We're gonna wait for !BSY anyway.
> +		 */
> +		for (i = 0; i < 2; i++) {
> +			u8 nsect, lbal;
> +
> +			nsect = ep93xx_pata_read(drv_data,
> +				ioaddr->nsect_addr, t);
> +			lbal = ep93xx_pata_read(drv_data,
> +				ioaddr->lbal_addr, t);
> +			if (nsect == 1 && lbal == 1)
> +				break;
> +			msleep(50);	/* give drive a breather */
> +		}
> +
> +		rc = ata_sff_wait_ready(link, deadline);
> +		if (rc) {
> +			if (rc != -ENODEV)
> +				return rc;
> +			ret = rc;
> +		}
> +	}
> +	/* is all this really necessary? */
> +	ap->ops->sff_dev_select(ap, 0);
> +	if (dev1)
> +		ap->ops->sff_dev_select(ap, 1);
> +	if (dev0)
> +		ap->ops->sff_dev_select(ap, 0);
> +
> +	return ret;
> +}
> +
> +static int ep93xx_pata_bus_softreset(struct ata_port *ap, unsigned int devmask,
> +				     unsigned long deadline)
> +{
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	const struct ata_timing *t = drv_data->cmd_t;
> +
> +	DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
> +
> +	ep93xx_pata_write(drv_data, ap->ctl, ioaddr->ctl_addr, t);
> +	udelay(20);		/* FIXME: flush */
> +	ep93xx_pata_write(drv_data, ap->ctl | ATA_SRST, ioaddr->ctl_addr, t);
> +	udelay(20);		/* FIXME: flush */
> +	ep93xx_pata_write(drv_data, ap->ctl, ioaddr->ctl_addr, t);
> +	ap->last_ctl = ap->ctl;
> +
> +	return ep93xx_pata_wait_after_reset(&ap->link, devmask, deadline);
> +}
> +
> +static bool ep93xx_pata_dma_filter(struct dma_chan *chan, void *filter_param)
> +{
> +	if (ep93xx_dma_chan_is_m2p(chan))
> +		return false;
> +
> +	chan->private = filter_param;
> +	return true;
> +}
> +
> +static int ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
> +{
> +	dma_cap_mask_t mask;
> +
> +	dma_cap_zero(mask);
> +	dma_cap_set(DMA_SLAVE, mask);
> +
> +	/*
> +	 * Request two channels for IDE. Another possibility would be
> +	 * to request only one channel, and reprogram it's direction at
> +	 * start of new transfer.
> +	 */
> +	drv_data->dma_rx_data.port = EP93XX_DMA_IDE;
> +	drv_data->dma_rx_data.direction = DMA_FROM_DEVICE;
> +	drv_data->dma_rx_data.name = "ep93xx-pata-rx";
> +	drv_data->dma_tx_data.port = EP93XX_DMA_IDE;
> +	drv_data->dma_tx_data.direction = DMA_TO_DEVICE;
> +	drv_data->dma_tx_data.name = "ep93xx-pata-tx";
> +	drv_data->dma_rx_channel = dma_request_channel(mask,
> +		ep93xx_pata_dma_filter, &drv_data->dma_rx_data);
> +	drv_data->dma_tx_channel = dma_request_channel(mask,
> +		ep93xx_pata_dma_filter, &drv_data->dma_tx_data);
> +	return drv_data->dma_rx_channel && drv_data->dma_tx_channel;
> +}
> +
> +static void ep93xx_pata_dma_start(struct ata_queued_cmd *qc)
> +{
> +	struct dma_async_tx_descriptor *txd;
> +	struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
> +	void __iomem *base = drv_data->ide_base;
> +	struct ata_device *adev = qc->dev;
> +	u32 v = qc->dma_dir == DMA_TO_DEVICE ? IDEUDMAOp_RWOP : 0;
> +	struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE
> +		? drv_data->dma_tx_channel : drv_data->dma_rx_channel;
> +
> +	txd = channel->device->device_prep_slave_sg(channel, qc->sg,
> +		 qc->n_elem, qc->dma_dir, DMA_CTRL_ACK);
> +	if (!txd) {
> +		dev_err(qc->ap->dev, "failed to prepare slave for sg dma\n");
> +		BUG();


Don't BUG in drivers if you can possibly avoid it. Set an error state
and try to bail out gracefully.

> +	}
> +	txd->callback = NULL;
> +	txd->callback_param = NULL;
> +
> +	if (dmaengine_submit(txd) < 0) {
> +		dev_err(qc->ap->dev, "failed to submit dma transfer\n");
> +		BUG();
> +	}
> +	dma_async_issue_pending(channel);
> +
> +	/*
> +	 * When enabling UDMA operation, IDEUDMAOp register needs to be
> +	 * programmed in three step sequence:
> +	 * 1) set or clear the RWOP bit,
> +	 * 2) perform dummy read of the register,
> +	 * 3) set the UEN bit.
> +	 */
> +	writel(v, base + IDEUDMAOp);
> +	readl(base + IDEUDMAOp);
> +	writel(v | IDEUDMAOp_UEN, base + IDEUDMAOp);
> +
> +	writel(IDECfg_IDEEN | IDECfg_UDMA |
> +		((adev->xfer_mode - XFER_UDMA_0) << IDECfg_MODE_SHIFT),
> +		base + IDECfg);
> +}
> +
> +static void ep93xx_pata_dma_stop(struct ata_queued_cmd *qc)
> +{
> +	struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
> +	void __iomem *base = drv_data->ide_base;
> +
> +	/* terminate all dma transfers, if not yet finished */
> +	dmaengine_terminate_all(drv_data->dma_rx_channel);
> +	dmaengine_terminate_all(drv_data->dma_tx_channel);
> +
> +	/*
> +	 * To properly stop IDE-DMA, IDEUDMAOp register must to be cleared
> +	 * and IDECtrl register must be set to default value.
> +	 */
> +	writel(0, base + IDEUDMAOp);
> +	writel(readl(base + IDECtrl) | IDECtrl_DIOWn | IDECtrl_DIORn |
> +		IDECtrl_CS0n | IDECtrl_CS1n, base + IDECtrl);
> +
> +	ep93xx_pata_enable_pio(drv_data->ide_base,
> +		qc->dev->pio_mode - XFER_PIO_0);
> +
> +	ata_sff_dma_pause(qc->ap);
> +}
> +
> +static void ep93xx_pata_dma_setup(struct ata_queued_cmd *qc)
> +{
> +	struct dma_slave_config conf;
> +	struct ata_port *ap = qc->ap;
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE
> +		? drv_data->dma_tx_channel : drv_data->dma_rx_channel;
> +
> +	memset(&conf, 0, sizeof(conf));
> +	conf.direction = qc->dma_dir;
> +	if (qc->dma_dir == DMA_FROM_DEVICE) {
> +		conf.src_addr = drv_data->udma_in_phys;
> +		conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +	} else {
> +		conf.dst_addr = drv_data->udma_out_phys;
> +		conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> +	}
> +	if (dmaengine_slave_config(channel, &conf)) {
> +		dev_err(qc->ap->dev, "failed to configure slave for sg dma\n");
> +		BUG();
> +	}
> +
> +	ap->ops->sff_exec_command(ap, &qc->tf);
> +}
> +
> +static u8 ep93xx_pata_dma_status(struct ata_port *ap)
> +{
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +	u32 val = readl(drv_data->ide_base + IDEUDMASts);
> +
> +	/*
> +	 * UDMA Status Register bits:
> +	 *
> +	 * DMAide - DMA request signal from UDMA state machine,
> +	 * INTide - INT line generated by UDMA because of errors in the
> +	 *          state machine,
> +	 * SBUSY - UDMA state machine busy, not in idle state,
> +	 * NDO   - error for data-out not completed,
> +	 * NDI   - error for data-in not completed,
> +	 * N4X   - error for data transferred not multiplies of four
> +	 *         32-bit words.
> +	 * (EP93xx UG p27-17)
> +	 */
> +	if (val & IDEUDMASts_NDO || val & IDEUDMASts_NDI ||
> +	    val & IDEUDMASts_N4X || val & IDEUDMASts_INTide)
> +		return ATA_DMA_ERR;
> +
> +	/* read INTRQ (INT[3]) pin input state */
> +	if (readl(drv_data->ide_base + IDECtrl) & IDECtrl_INTRQ)
> +		return ATA_DMA_INTR;
> +
> +	if (val & IDEUDMASts_SBUSY || val & IDEUDMASts_DMAide)
> +		return ATA_DMA_ACTIVE;
> +
> +	return 0;
> +}
> +
> +static int ep93xx_pata_softreset(struct ata_link *al, unsigned int *classes,
> +				 unsigned long deadline)
> +{
> +	struct ata_port *ap = al->ap;
> +	unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
> +	unsigned int devmask = 0;
> +	int rc;
> +	u8 err;
> +
> +	DPRINTK("ENTER\n");
> +
> +	/* determine if device 0/1 are present */
> +	if (ep93xx_pata_dev_check(ap, 0))
> +		devmask |= (1 << 0);
> +	if (slave_possible && ep93xx_pata_dev_check(ap, 1))
> +		devmask |= (1 << 1);
> +
> +	/* select device 0 again */
> +	ap->ops->sff_dev_select(al->ap, 0);
> +
> +	/* issue bus reset */
> +	DPRINTK("about to softreset, devmask=%x\n", devmask);
> +	rc = ep93xx_pata_bus_softreset(ap, devmask, deadline);
> +	/* if link is ocuppied, -ENODEV too is an error */
> +	if (rc && (rc != -ENODEV || sata_scr_valid(al))) {
> +		ata_link_printk(al, KERN_ERR, "SRST failed (errno=%d)\n",
> +				rc);
> +		return rc;
> +	}
> +
> +	/* determine by signature whether we have ATA or ATAPI devices */
> +	classes[0] = ata_sff_dev_classify(&al->device[0], devmask & (1 << 0),
> +					  &err);
> +	if (slave_possible && err != 0x81)
> +		classes[1] = ata_sff_dev_classify(&al->device[1],
> +						  devmask & (1 << 1), &err);
> +
> +	DPRINTK("EXIT, classes[0]=%u, [1]=%u\n", classes[0],
> +		classes[1]);
> +	return 0;
> +}
> +
> +void ep93xx_pata_drain_fifo(struct ata_queued_cmd *qc)
> +{
> +	int count;
> +	struct ata_port *ap;
> +	struct ep93xx_pata_data *drv_data;
> +
> +	/* We only need to flush incoming data when a command was running */
> +	if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
> +		return;
> +
> +	ap = qc->ap;
> +	drv_data = ap->host->private_data;
> +	/* Drain up to 64K of data before we give up this recovery method */
> +	for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
> +		     && count < 65536; count += 2)
> +		ep93xx_pata_read(drv_data, ap->ioaddr.data_addr,
> +				 drv_data->cmd_t);
> +
> +	/* Can become DEBUG later */
> +	if (count)
> +		ata_port_printk(ap, KERN_DEBUG,
> +				"drained %d bytes to clear DRQ.\n", count);
> +
> +}
> +
> +static int ep93xx_pata_port_start(struct ata_port *ap)
> +{
> +	struct ep93xx_pata_data *drv_data = ap->host->private_data;
> +
> +	drv_data->cmd_t = ata_timing_find_mode(XFER_PIO_0);
> +	return 0;
> +}
> +
> +static struct scsi_host_template ep93xx_pata_sht = {
> +	ATA_BASE_SHT(DRV_NAME),
> +	/* ep93xx dma implementation limit */
> +	.sg_tablesize		= 32,
> +	/* ep93xx dma can't transfer 65536 bytes at once */
> +	.dma_boundary		= 0x7fff,
> +};
> +
> +static struct ata_port_operations ep93xx_pata_port_ops = {
> +	.inherits		= &ata_bmdma_port_ops,
> +
> +	.qc_prep		= ata_noop_qc_prep,
> +
> +	.softreset		= ep93xx_pata_softreset,
> +	.hardreset		= ATA_OP_NULL,
> +
> +	.sff_dev_select		= ep93xx_pata_dev_select,
> +	.sff_set_devctl		= ep93xx_pata_set_devctl,
> +	.sff_check_status	= ep93xx_pata_check_status,
> +	.sff_check_altstatus	= ep93xx_pata_check_altstatus,
> +	.sff_tf_load		= ep93xx_pata_tf_load,
> +	.sff_tf_read		= ep93xx_pata_tf_read,
> +	.sff_exec_command	= ep93xx_pata_exec_command,
> +	.sff_data_xfer		= ep93xx_pata_data_xfer,
> +	.sff_drain_fifo		= ep93xx_pata_drain_fifo,
> +	.sff_irq_clear		= ATA_OP_NULL,
> +
> +	.set_piomode		= ep93xx_pata_set_piomode,
> +
> +	.bmdma_setup		= ep93xx_pata_dma_setup,
> +	.bmdma_start		= ep93xx_pata_dma_start,
> +	.bmdma_stop		= ep93xx_pata_dma_stop,
> +	.bmdma_status		= ep93xx_pata_dma_status,
> +
> +	.cable_detect		= ata_cable_unknown,
> +	.port_start		= ep93xx_pata_port_start,
> +};
> +
> +static void ep93xx_pata_setup_port(struct ata_ioports *ioaddr)
> +{
> +	/*
> +	 * the device IDE register to be accessed is selected through
> +	 * IDECTRL register's specific bitfields 'DA', 'CS1n' and 'CS0n':
> +	 *   b4   b3   b2    b1     b0
> +	 *   A2   A1   A0   CS1n   CS0n
> +	 * the values filled in this structure allows the value to be directly
> +	 * ORed to the IDECTRL register, hence giving directly the A[2:0] and
> +	 * CS1n/CS0n values for each IDE register.
> +	 * The values correspond to the transformation:
> +	 *   ((real IDE address) << 2) | CS1n value << 1 | CS0n value
> +	 */
> +	ioaddr->cmd_addr	= (void __iomem *) 0 + 2; /* CS1 */
> +
> +	ioaddr->data_addr	= (void __iomem *) (ATA_REG_DATA << 2) + 2;
> +	ioaddr->error_addr	= (void __iomem *) (ATA_REG_ERR << 2) + 2;
> +	ioaddr->feature_addr	= (void __iomem *) (ATA_REG_FEATURE << 2) + 2;
> +	ioaddr->nsect_addr	= (void __iomem *) (ATA_REG_NSECT << 2) + 2;
> +	ioaddr->lbal_addr	= (void __iomem *) (ATA_REG_LBAL << 2) + 2;
> +	ioaddr->lbam_addr	= (void __iomem *) (ATA_REG_LBAM << 2) + 2;
> +	ioaddr->lbah_addr	= (void __iomem *) (ATA_REG_LBAH << 2) + 2;
> +	ioaddr->device_addr	= (void __iomem *) (ATA_REG_DEVICE << 2) + 2;
> +	ioaddr->status_addr	= (void __iomem *) (ATA_REG_STATUS << 2) + 2;
> +	ioaddr->command_addr	= (void __iomem *) (ATA_REG_CMD << 2) + 2;
> +
> +	ioaddr->altstatus_addr	= (void __iomem *) (0x06 << 2) + 1; /* CS0 */
> +	ioaddr->ctl_addr	= (void __iomem *) (0x06 << 2) + 1; /* CS0 */


Only a couple of other pata driver appears to do this horrible casting
mess. Other drivers appear to be using (devm_ioremap). Can we clean this up?

> +}
> +
> +static int __devinit ep93xx_pata_probe(struct platform_device *pdev)
> +{
> +	struct ep93xx_pata_data *drv_data;
> +	struct ata_host *host;
> +	struct ata_port *ap;
> +	unsigned int irq;
> +	struct resource *mem_res;
> +	void __iomem *ide_base;
> +
> +	/*if (readl(EP93XX_SYSCON_DEVCFG) & (EP93XX_SYSCON_DEVCFG_EONIDE
> +		| EP93XX_SYSCON_DEVCFG_GONIDE | EP93XX_SYSCON_DEVCFG_HONIDE)) {
> +		dev_err(&pdev->dev, "IDE/GPIO pin conflict\n");
> +		return -EINVAL;
> +	}*/


Fix or remove.

> +
> +	/* INT[3] (IRQ_EP93XX_EXT3) line connected as pull down */
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0) {
> +		dev_err(&pdev->dev, "IRQ allocation failed\n");
> +		return -ENXIO;
> +	}
> +
> +	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!mem_res) {
> +		dev_err(&pdev->dev, "resources allocation failed\n");
> +		return -ENXIO;
> +	}
> +
> +	ide_base = devm_request_and_ioremap(&pdev->dev, mem_res);
> +	if (!ide_base) {
> +		dev_err(&pdev->dev, "memory region request/map failed\n");
> +		return -ENOMEM;
> +	}
> +
> +	drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
> +	if (!drv_data) {
> +		dev_err(&pdev->dev, "unable to allocate memory\n");

> +		return -ENOMEM;

> +	}
> +
> +	platform_set_drvdata(pdev, drv_data);
> +	drv_data->ide_base = ide_base;
> +	drv_data->udma_in_phys = mem_res->start + IDEUDMADataIn;
> +	drv_data->udma_out_phys = mem_res->start + IDEUDMADataOut;
> +	ep93xx_pata_dma_init(drv_data);
> +
> +	/* allocate host */
> +	host = ata_host_alloc(&pdev->dev, 1);
> +	if (!host) {
> +		dev_err(&pdev->dev, "ata_host_alloc() failed\n");

> +		return -ENOMEM;

> +	}
> +
> +	ep93xx_pata_clear_regs(ide_base);
> +
> +	host->n_ports = 1;
> +	host->private_data = drv_data;
> +
> +	ap = host->ports[0];
> +	ap->dev = &pdev->dev;
> +	ap->ops = &ep93xx_pata_port_ops;
> +	ap->flags |= ATA_FLAG_SLAVE_POSS;
> +	ap->pio_mask = ATA_PIO4;
> +	/*
> +	 * Maximum UDMA modes:
> +	 * EP931x rev.E0 - UDMA2
> +	 * EP931x rev.E1 - UDMA3
> +	 * EP931x rev.E2 - UDMA4
> +	 *
> +	 * MWDMA support was removed from EP931x rev.E2,
> +	 * so this driver supports only UDMA modes.
> +	 */
> +	if (drv_data->dma_rx_channel && drv_data->dma_tx_channel) {
> +		int chip_rev = ep93xx_chip_revision();
> +		if (chip_rev == EP93XX_CHIP_REV_E1)
> +			ap->udma_mask = ATA_UDMA3;
> +		else if (chip_rev == EP93XX_CHIP_REV_E2)
> +			ap->udma_mask = ATA_UDMA4;
> +		else
> +			ap->udma_mask = ATA_UDMA2;
> +	}
> +
> +	ep93xx_pata_setup_port(&ap->ioaddr);
> +
> +	/* defaults, pio 0 */
> +	ep93xx_pata_enable_pio(ide_base, 0);
> +
> +	dev_info(&pdev->dev, "version " DRV_VERSION "\n");
> +
> +	/* activate host */
> +	return ata_host_activate(host, irq, ata_bmdma_interrupt, 0,
> +		&ep93xx_pata_sht);

> +}

> +
> +static int __devexit ep93xx_pata_remove(struct platform_device *pdev)
> +{
> +	struct ata_host *host = platform_get_drvdata(pdev);
> +	struct ep93xx_pata_data *drv_data = host->private_data;
> +
> +	ata_host_detach(host);
> +	if (drv_data->dma_rx_channel)
> +		dma_release_channel(drv_data->dma_rx_channel);
> +	if (drv_data->dma_tx_channel)
> +		dma_release_channel(drv_data->dma_tx_channel);
> +	ep93xx_pata_clear_regs(drv_data->ide_base);

> +	return 0;
> +}
> +
> +static struct platform_driver ep93xx_pata_platform_driver = {
> +	.driver = {
> +		.name = DRV_NAME,
> +		.owner = THIS_MODULE,
> +	},
> +	.probe = ep93xx_pata_probe,
> +	.remove = __devexit_p(ep93xx_pata_remove),
> +};
> +
> +static int __init ep93xx_pata_init(void)
> +{
> +	return platform_driver_register(&ep93xx_pata_platform_driver);
> +}
> +
> +static void __exit ep93xx_pata_exit(void)
> +{
> +	platform_driver_unregister(&ep93xx_pata_platform_driver);
> +}
> +
> +module_init(ep93xx_pata_init);
> +module_exit(ep93xx_pata_exit);
> +
> +MODULE_AUTHOR("Alessandro Zummo, Lennert Buytenhek, Joao Ramos, "
> +		"Bartlomiej Zolnierkiewicz, Rafal Prylowski");
> +MODULE_DESCRIPTION("low-level driver for cirrus ep93xx IDE controller");
> +MODULE_LICENSE("GPL");
> +MODULE_VERSION(DRV_VERSION);
> +MODULE_ALIAS("platform:pata_ep93xx");
> Index: linux-2.6/drivers/ata/Kconfig
> ===================================================================
> --- linux-2.6.orig/drivers/ata/Kconfig
> +++ linux-2.6/drivers/ata/Kconfig
> @@ -416,6 +416,15 @@ config PATA_EFAR
>  
>  	  If unsure, say N.
>  
> +config PATA_EP93XX
> +	tristate "Cirrus Logic EP93xx PATA support"
> +	depends on ARCH_EP93XX
> +	help
> +	  This option enables support for the PATA controller in
> +	  the Cirrus Logic EP9312 and EP9315 ARM CPU.
> +
> +	  If unsure, say N.
> +
>  config PATA_HPT366
>  	tristate "HPT 366/368 PATA support"
>  	depends on PCI
> Index: linux-2.6/drivers/ata/Makefile
> ===================================================================
> --- linux-2.6.orig/drivers/ata/Makefile
> +++ linux-2.6/drivers/ata/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_PATA_CS5535)	+= pata_cs5535
>  obj-$(CONFIG_PATA_CS5536)	+= pata_cs5536.o
>  obj-$(CONFIG_PATA_CYPRESS)	+= pata_cypress.o
>  obj-$(CONFIG_PATA_EFAR)		+= pata_efar.o
> +obj-$(CONFIG_PATA_EP93XX)	+= pata_ep93xx.o
>  obj-$(CONFIG_PATA_HPT366)	+= pata_hpt366.o
>  obj-$(CONFIG_PATA_HPT37X)	+= pata_hpt37x.o
>  obj-$(CONFIG_PATA_HPT3X2N)	+= pata_hpt3x2n.o
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel




From rmallon at gmail.com  Thu Mar 29 18:24:17 2012
From: rmallon at gmail.com (Ryan Mallon)
Date: Fri, 30 Mar 2012 09:24:17 +1100
Subject: [PATCH 1/3] PATA host controller driver for ep93xx
In-Reply-To: <4F741AB1.4000107@metasoft.pl>
References: <4F7418E7.4060500@metasoft.pl> <4F741AB1.4000107@metasoft.pl>
Message-ID: <4F74E111.60503@gmail.com>

On 29/03/12 19:17, Rafal Prylowski wrote:

> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
> Cc: Joao Ramos <joao.ramos at inov.pt>
> Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <ryan at bluewatersys.com>


Please note. This email address is no longer valid for me.

Thanks,
~Ryan


From konkers at google.com  Thu Mar 29 18:27:01 2012
From: konkers at google.com (Erik Gilling)
Date: Thu, 29 Mar 2012 15:27:01 -0700
Subject: [PATCH v6 1/5] Extcon (external connector): import Android's
 switch class and modify.
In-Reply-To: <20120309124119.GV3273@opensource.wolfsonmicro.com>
References: <1328856038-21912-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-2-git-send-email-myungjoo.ham@samsung.com>
 <20120309124119.GV3273@opensource.wolfsonmicro.com>
Message-ID: <CACSP8ShU5tu=9N53PtYMLyFVFMS9whNRhMvu7nu8rBoPuVCy+Q@mail.gmail.com>

On Fri, Mar 9, 2012 at 4:41 AM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Mon, Feb 27, 2012 at 09:15:35PM +0900, MyungJoo Ham wrote:
>
>> +#ifdef CONFIG_ANDROID
>> + ? ? ? ? ? ? extcon_class = class_create(THIS_MODULE, "switch");
>> +#else /* !CONFIG_ANDROID */
>> + ? ? ? ? ? ? extcon_class = class_create(THIS_MODULE, "extcon");
>> +#endif /* CONFIG_ANDROID */
>
> This seems somewhat sad - if ANDROID is turned on the standard ABI
> vanishes. ?It'd be much nicer to do this with a symlink (or with
> symlinks within the android directory if the driver core doesn't support
> that). ?That way userspace code can be written to the new ABI and will
> work on Android systems without ifdefery.

This won't work if userspace code is receiving uevents through netlink
and comparing based on the device name which it does in android.  Why
change the name at all?  Extcon is much more specific than "switch."
A switch can can be used for more than just external connections such
as availability of HMDI audio (which is only available once a HDMI
mode is chosen and the interface is enabled.)

-Erik


From davidb at codeaurora.org  Thu Mar 29 18:31:36 2012
From: davidb at codeaurora.org (David Brown)
Date: Thu, 29 Mar 2012 15:31:36 -0700
Subject: [PATCH 03/17] ARM: mark const init data with __initconst instead
 of __initdata
In-Reply-To: <1333055554-31300-3-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20120329211131.GA31250@pengutronix.de>
 <1333055554-31300-3-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120329223136.GA1930@codeaurora.org>

On Thu, Mar 29, 2012 at 11:12:20PM +0200, Uwe Kleine-K?nig wrote:

>  arch/arm/mach-msm/board-msm8x60.c             |    2 +-
>  arch/arm/mach-msm/board-qsd8x50.c             |    4 +-

Acked-by: David Brown <davidb at codeaurora.org>

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From hartleys at visionengravers.com  Thu Mar 29 18:33:49 2012
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Thu, 29 Mar 2012 17:33:49 -0500
Subject: [PATCH] ep93xx: Implement double buffering for M2M DMA channels
In-Reply-To: <20120324073207.GD5812@mwesterb-mobl.ger.corp.intel.com>
References: <4F683B36.8090101@metasoft.pl>
 <20120321193836.GC3740@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48E3E@AUSP01VMBX24.collaborationhost.net>
 <20120323070446.GC5812@mwesterb-mobl.ger.corp.intel.com>
 <ADE657CA350FB648AAC2C43247A983F0020696D48EEB@AUSP01VMBX24.collaborationhost.net>
 <20120324073207.GD5812@mwesterb-mobl.ger.corp.intel.com>
Message-ID: <ADE657CA350FB648AAC2C43247A983F002069702575E@AUSP01VMBX24.collaborationhost.net>

On Saturday, March 24, 2012 12:32 AM, Mika Westerberg wrote:
> On Fri, Mar 23, 2012 at 11:09:50AM -0500, H Hartley Sweeten wrote:
>> No, I have not applied your VIC hack.
>
> Please try it. The point there was that we have a problem in ep93xx VIC/DMA
> code but it is totally different thing and not related to Rafal's patch. We
> can sort the VIC thing out separately IMHO. ep93xx dma in 3.3 is broken
> regardless this patch.

Mika,

I tried you VIC hack. It does seem to work.

I tried doing a bit more debugging with the handle_one_vic function. It
appears that the timer tick is what's causing the spi dma interrupts grief.
I'm just not sure how it's happening or how to fix it...

I modified handle_one_vic to output a message when multiple interrupts
are detected in the stat. Then, if multiple interrupts were detected, to output
a message with the new calculated stat and the actual stat. These "should"
occur one right after the other when multiple interrupts are detected. But
that's not what I'm getting. Here's a sample trace with comments:

handle_one_vic: stat:0x00060000 - handling irq:17 now
	stat shows interrupts 17 and 18
handle_one_vic: stat:0x00040010 - handling irq:4 now
	stat shows interrupts 4 and 18, 17 was handled
handle_one_vic: next stat:0x00040000 - actual stat:0x00040000
	next stat shows interrupt 18, 4 was handled, 18 is pending
handle_one_vic: stat:0x00040000 - handling irq:18 now
	stat shows interrupt 18
handle_one_vic: next stat:0x00000000 - actual stat:0x00000010
	next stat shows no interrupts, 18 was handled, 4 is pending
handle_one_vic: next stat:0x00040000 - actual stat:0x00000000
	next stat shows interrupt 18, it was already handled, none are pending
handle_one_vic: stat:0x00040000 - handling irq:18 now
	stat shows interrupt 18 (which was already handled)
dma dma1chan1: spurious interrupt: status=00002180
	bang... spurious interrupt

It looks like the timer interrupt (4) is causing vic_handle_irq to start
iterating over the VIC's while an iteration is already in progress.  One
of the iterations is handling interrupt 18 correctly but, since the stat
is only read once, the second iteration also tries to handle it.

Any ideas?

Regards,
Hartley


From sboyd at codeaurora.org  Thu Mar 29 18:37:41 2012
From: sboyd at codeaurora.org (Stephen Boyd)
Date: Thu, 29 Mar 2012 15:37:41 -0700
Subject: [PATCH v6 2/5] Extcon: support generic GPIO extcon driver
In-Reply-To: <1330344939-18394-3-git-send-email-myungjoo.ham@samsung.com>
References: <1328856038-21912-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-3-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <4F74E435.9030101@codeaurora.org>

On 02/27/12 04:15, MyungJoo Ham wrote
> +static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
> +{
> +	struct gpio_extcon_data *extcon_data =
> +	    (struct gpio_extcon_data *)dev_id;

Casting from void is unnecessary.

> +
> +static int gpio_extcon_probe(struct platform_device *pdev)

__devinit?

> +{
> +	struct gpio_extcon_platform_data *pdata = pdev->dev.platform_data;
> +	struct gpio_extcon_data *extcon_data;
> +	int ret = 0;
[snip]
> +	return ret;
> +}
> +
> +static int gpio_extcon_remove(struct platform_device *pdev)

__devexit?
> +{
> +	struct gpio_extcon_data *extcon_data = platform_get_drvdata(pdev);
[snip]
> +static struct platform_driver gpio_extcon = {
> +	.probe		= gpio_extcon_probe,
> +	.remove		= gpio_extcon_remove,

__devexit_p()?
> +	.driver		= {
> +		.name	= "extcon-gpio",
> +		.owner	= THIS_MODULE,
> +	},
> +};
> +
> +module_platform_driver(gpio_extcon);
> +
> +MODULE_AUTHOR("Mike Lockwood <lockwood at android.com>");
> +MODULE_DESCRIPTION("GPIO extcon driver");
> +MODULE_LICENSE("GPL");
-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From torvalds at linux-foundation.org  Thu Mar 29 20:09:27 2012
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Thu, 29 Mar 2012 17:09:27 -0700
Subject: [GIT PULL 1/5] ARM: cleanups of io includes
In-Reply-To: <20120328192816.GD22414@n2100.arm.linux.org.uk>
References: <1332918842-13521-1-git-send-email-olof@lixom.net>
 <1332918842-13521-2-git-send-email-olof@lixom.net>
 <20120328082501.GA22414@n2100.arm.linux.org.uk>
 <CAOesGMjwZOON9kFNvaEq8QhSvjAgsJT_J1Ysb9-AbePd6g+-rQ@mail.gmail.com>
 <20120328192816.GD22414@n2100.arm.linux.org.uk>
Message-ID: <CA+55aFyJH8yO7=AzuddsQZouHqRDtmeh-vbd8Y5VQLQx-6ZV-Q@mail.gmail.com>

On Wed, Mar 28, 2012 at 12:28 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
>
> Right, having merged the latest arm-soc tree this evening into the build
> tree and forced a rebuild, the errors induced by Rob's patches are now
> gone, so I'm fine with this going in now.

Ok, I'm getting back to this pull request, and apparently everything
is ok with it.

Holler if not, because it's not back on my queue of trees to merge
(but I haven't actually gotten to it yet - this is just a heads-up
that I will get to it later today).

                        Linus


From olof at lixom.net  Thu Mar 29 20:27:50 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 29 Mar 2012 17:27:50 -0700
Subject: [GIT PULL 1/5] ARM: cleanups of io includes
In-Reply-To: <CA+55aFyJH8yO7=AzuddsQZouHqRDtmeh-vbd8Y5VQLQx-6ZV-Q@mail.gmail.com>
References: <1332918842-13521-1-git-send-email-olof@lixom.net>
 <1332918842-13521-2-git-send-email-olof@lixom.net>
 <20120328082501.GA22414@n2100.arm.linux.org.uk>
 <CAOesGMjwZOON9kFNvaEq8QhSvjAgsJT_J1Ysb9-AbePd6g+-rQ@mail.gmail.com>
 <20120328192816.GD22414@n2100.arm.linux.org.uk>
 <CA+55aFyJH8yO7=AzuddsQZouHqRDtmeh-vbd8Y5VQLQx-6ZV-Q@mail.gmail.com>
Message-ID: <CAOesGMgaQ7mjV-1Q5uPthw8PAtU+BUfDgOqor=3jtvkL30L1ZA@mail.gmail.com>

On Thu, Mar 29, 2012 at 5:09 PM, Linus Torvalds
<torvalds at linux-foundation.org> wrote:
> On Wed, Mar 28, 2012 at 12:28 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
>>
>> Right, having merged the latest arm-soc tree this evening into the build
>> tree and forced a rebuild, the errors induced by Rob's patches are now
>> gone, so I'm fine with this going in now.
>
> Ok, I'm getting back to this pull request, and apparently everything
> is ok with it.
>
> Holler if not, because it's not back on my queue of trees to merge
> (but I haven't actually gotten to it yet - this is just a heads-up
> that I will get to it later today).

I was going to send a fresh pull request for it and include some of
the other PXA breakage fixes with it, but I haven't received those
from the PXA maintainer yet. I'll send a separate pull request for a
fixes branch when I get it instead (this pull request does not add any
new breakage).

So please, go ahead and pull. It hasn't grown any new merge conflicts
since before as of now, so see the original pull request for those.


Thanks!

-Olof


From olof at lixom.net  Thu Mar 29 20:34:04 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 29 Mar 2012 17:34:04 -0700
Subject: [GIT PULL 1/5] ARM: cleanups of io includes
In-Reply-To: <CAOesGMgaQ7mjV-1Q5uPthw8PAtU+BUfDgOqor=3jtvkL30L1ZA@mail.gmail.com>
References: <1332918842-13521-1-git-send-email-olof@lixom.net>
 <1332918842-13521-2-git-send-email-olof@lixom.net>
 <20120328082501.GA22414@n2100.arm.linux.org.uk>
 <CAOesGMjwZOON9kFNvaEq8QhSvjAgsJT_J1Ysb9-AbePd6g+-rQ@mail.gmail.com>
 <20120328192816.GD22414@n2100.arm.linux.org.uk>
 <CA+55aFyJH8yO7=AzuddsQZouHqRDtmeh-vbd8Y5VQLQx-6ZV-Q@mail.gmail.com>
 <CAOesGMgaQ7mjV-1Q5uPthw8PAtU+BUfDgOqor=3jtvkL30L1ZA@mail.gmail.com>
Message-ID: <CAOesGMj4Osx0KBCxM4_N09PMTkpTdhhQRvEcwEeY8PFKanT_-w@mail.gmail.com>

On Thu, Mar 29, 2012 at 5:27 PM, Olof Johansson <olof at lixom.net> wrote:

> It hasn't grown any new merge conflicts
> since before as of now, so see the original pull request for those.

D'oh, I did a git remote update but didn't checkout the new head for
your tree when I verified the merge conflict situation. It does have a
couple of new trivial ones:

* arch/arm/mach-tegra/Makefile: keep reset.o, remove localtimer.o
* arch/arm/mach-vexpress/include/mach/io.h: line remove vs file remove
conflict: file is gone, but a patch in rmk's tree had removed a line
from it. It's safe to still remove the file.

+ the previous ones from original pull request:

arch/arm/Kconfig: New selects added for ARCH_S3C24X. Include both
sides of the merge.

arch/arm/mach-shmobile/smp-sh73a0.c: A readl vs readw fix collided
with the io accessor cleanup. Ditch the __io() use but keep readl.

arch/arm/mach-tegra/include/mach/debug-macro.S: include of mach/io.h
is going away, iomap.h is kept.

-Olof


From haojian.zhuang at gmail.com  Thu Mar 29 20:41:58 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 30 Mar 2012 08:41:58 +0800
Subject: [PATCH v3] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <1333043034-3374-1-git-send-email-paul.gortmaker@windriver.com>
References: <20120329151157.GT3668@opensource.wolfsonmicro.com>
 <1333043034-3374-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <CAN1soZzssbD1CymiHewy9F8y=1Uc3HDZmL4ws7KTp__R+cpasA@mail.gmail.com>

On Fri, Mar 30, 2012 at 1:43 AM, Paul Gortmaker
<paul.gortmaker at windriver.com> wrote:
> Commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0
>
> ?"regulator: Remove support for supplies specified by struct device"
>
> caused this file to break, since it was still relying on the
> device field to be present. ?Map it onto dev_name appropriately
>
> Since there are two consumers with the name "reg-userspace-consumer",
> we have to supply the ID as a suffix in the REGULATOR_CONSUMER calls.
>
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> CC: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---
>
> [v3: add .0/.1 ID suffix to "reg-userspace-consumer" instances ]
>
> diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
> index c1b65da..16ec557 100644
> --- a/arch/arm/mach-pxa/em-x270.c
> +++ b/arch/arm/mach-pxa/em-x270.c
> @@ -1083,19 +1083,19 @@ static void __init em_x270_userspace_consumers_init(void)
> ?}
>
> ?/* DA9030 related initializations */
> -#define REGULATOR_CONSUMER(_name, _dev, _supply) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> +#define REGULATOR_CONSUMER(_name, _dev_name, _supply) ? ? ? ? ? ? ? ? ?\
> ? ? ? ?static struct regulator_consumer_supply _name##_consumers[] = { \
> ? ? ? ? ? ? ? ?{ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ? ? ? ? ? ? ? ? ? ? .dev = _dev, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> + ? ? ? ? ? ? ? ? ? ? ? .dev_name = _dev_name, ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ? ? ? ? ?.supply = _supply, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ? ? ? ? ?}, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
> ? ? ? ?}
>
> -REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps");
> +REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer.0", "vcc gps");
> ?REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
> -REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
> +REGULATOR_CONSUMER(ldo10, "pxa2xx-mci", "vcc sdio");
> ?REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
> -REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
> +REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer.1", "vcc gprs");
> ?REGULATOR_CONSUMER(buck2, NULL, "vcc_core");
>
> ?#define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) ? ? ? ? ? ? ?\
> --
> 1.7.9.1
>

Applied

Thanks
Haojian


From haojian.zhuang at gmail.com  Thu Mar 29 21:06:37 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 30 Mar 2012 09:06:37 +0800
Subject: [GIT PULL] pull request from arch-pxa git on fixes branch
In-Reply-To: <CAOesGMgxq-HEeKSPvaW-kTLqNyDJUUmG0OEpockMBNninQL0wQ@mail.gmail.com>
References: <CAN1soZytJ-CxepQAZn5oZ06=ezTQ85O-iC7tUDOeWqi=zpuf8A@mail.gmail.com>
 <4F732D14.3020803@compulab.co.il>
 <CAOesGMgxq-HEeKSPvaW-kTLqNyDJUUmG0OEpockMBNninQL0wQ@mail.gmail.com>
Message-ID: <CAN1soZzqxy=wsPVEXY8BxTK24szq7x5Oxk2JjuUJ6di7ij8hWA@mail.gmail.com>

On Thu, Mar 29, 2012 at 1:12 AM, Olof Johansson <olof at lixom.net> wrote:
> Hi,
>
> On Wed, Mar 28, 2012 at 8:24 AM, Igor Grinberg <grinberg at compulab.co.il> wrote:
>
>> Can Paul's patch [1] be included in this or later request?
>>
>> Thanks.
>>
>> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/091750.html
>
> Yes, Haojian, please add that to the branch (with the proposed fixups)
> as well so we can pick it up and send it in ASAP. Both are broken
> today in Russell's PXA defconfig.
>
> There is one more failure as well, that I haven't seen a patch posted for:
>
> arch/arm/mach-pxa/cm-x300.c:716:3: error: unknown field 'dev'
> specified in initializer
>
>
>
> -Olof

Now these build issues are fixed. Could you help to pull these fixes
from arch-pxa git?

The following changes since commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7:

  Linux 3.3 (2012-03-18 16:15:34 -0700)

are available in the git repository at:
  git://github.com/hzhuang1/linux.git fixes

Haojian Zhuang (2):
      ARM: pxa: fix build issue on cm-x300
      ARM: pxa: fix build issue on stargate2

Paul Gortmaker (2):
      ARM: pxa: fix regulator related build fail in magician_defconfig
      ARM: pxa: fix build failure for regulator consumer in em-x270.c

 arch/arm/mach-pxa/cm-x300.c   |    1 -
 arch/arm/mach-pxa/em-x270.c   |   10 +++++-----
 arch/arm/mach-pxa/hx4700.c    |    2 --
 arch/arm/mach-pxa/magician.c  |    2 --
 arch/arm/mach-pxa/stargate2.c |    2 +-
 5 files changed, 6 insertions(+), 11 deletions(-)


From haojian.zhuang at gmail.com  Thu Mar 29 21:33:30 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 30 Mar 2012 09:33:30 +0800
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <1332958336.11131.YahooMailClassic@web29001.mail.ird.yahoo.com>
References: <1332958336.11131.YahooMailClassic@web29001.mail.ird.yahoo.com>
Message-ID: <CAN1soZwzBqDGTX+a-maVr5baaoZ7qwgdvXyPeya5R80cN_iA0w@mail.gmail.com>

On Thu, Mar 29, 2012 at 2:12 AM, Paul Parsons <lost.distance at yahoo.com> wrote:
> On PXA2xx platforms, the MFP API (described in Documentation/arm/pxa/mfp.txt)
> provides values for the following:
>
> 1. GPIO inputs (e.g. GPIO105_GPIO).
> 2. Alternate function inputs (e.g. GPIO105_CIF_DD_1).
> 3. Alternate function outputs (e.g. GPIO105_KP_MKOUT_2).
>
> It does not provide values for GPIO outputs (i.e. AF0 outputs).
>
> One cannot use the macro used by the MFP API internally - MFP_CFG_OUT() - to
> define new GPIO output values, since that macro is forbidden in platform code.
>
> Without the ability to add GPIO outputs to the MFP configuration, it is not
> possible to drive GPIO outputs high during sleep mode.
>
> This would be useful, for example, on the hx4700 platform, where driving the
> infrared powerdown GPIO 105 high during sleep mode would save some mA.
>
> So my question is: what method should one use to add GPIO outputs to the MFP
> configuration?
>
> One possible method, namely manually defining values in the platform code:
>
> ? ? ? ?MFP_PIN_GPIO105 | MFP_AF0 | MFP_DIR_OUT | MFP_LPM_DRIVE_HIGH,
>
> is essentially no different from using the forbidden MFP_CFG_OUT() macro.
>

Does MFP_CFG_OUT() help you? This macro is defined in mfp-pxa2xx.h.


From chao.xie at marvell.com  Thu Mar 29 21:58:15 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Fri, 30 Mar 2012 09:58:15 +0800
Subject: [PATCH V2 1/4] Input: pxa27x_keypad keep clock on as wakeup source
Message-ID: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>

When the keypad is used as wake up source, the clock can not
be disabled. Or it can not detect key pressing.
If the keypad is used as wake up source, when resume back,
do not enable the clock and configure it again because the
register content is retained.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/input/keyboard/pxa27x_keypad.c |   27 ++++++++++++++++++---------
 1 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index 29fe1b2..1c5752f 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -419,10 +419,14 @@ static int pxa27x_keypad_suspend(struct device *dev)
 	struct platform_device *pdev = to_platform_device(dev);
 	struct pxa27x_keypad *keypad = platform_get_drvdata(pdev);
 
-	clk_disable(keypad->clk);
-
+	/*
+	 * If the keypad is used a wake up source, clock can not be disabled.
+	 * Or it can not detect the key pressing.
+	 */
 	if (device_may_wakeup(&pdev->dev))
 		enable_irq_wake(keypad->irq);
+	else
+		clk_disable(keypad->clk);
 
 	return 0;
 }
@@ -433,19 +437,24 @@ static int pxa27x_keypad_resume(struct device *dev)
 	struct pxa27x_keypad *keypad = platform_get_drvdata(pdev);
 	struct input_dev *input_dev = keypad->input_dev;
 
+	/*
+	 * If the keypad is used as wake up source, the clock is not turned
+	 * off. So do not need configure it again.
+	 */
 	if (device_may_wakeup(&pdev->dev))
 		disable_irq_wake(keypad->irq);
+	else {
+		mutex_lock(&input_dev->mutex);
 
-	mutex_lock(&input_dev->mutex);
+		if (input_dev->users) {
+			/* Enable unit clock */
+			clk_enable(keypad->clk);
+			pxa27x_keypad_config(keypad);
+		}
 
-	if (input_dev->users) {
-		/* Enable unit clock */
-		clk_enable(keypad->clk);
-		pxa27x_keypad_config(keypad);
+		mutex_unlock(&input_dev->mutex);
 	}
 
-	mutex_unlock(&input_dev->mutex);
-
 	return 0;
 }
 
-- 
1.7.0.4



From chao.xie at marvell.com  Thu Mar 29 21:58:16 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Fri, 30 Mar 2012 09:58:16 +0800
Subject: [PATCH V2 2/4] Input: pxa27x_keypad bug fix for direct_key_mask
In-Reply-To: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
References: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1333072698-15344-2-git-send-email-chao.xie@marvell.com>

When direcct_key_num is 0, the mask should be 0.
When direcct_key_num is 1, the mask should be 0b1.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/input/keyboard/pxa27x_keypad.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index 1c5752f..f9a76d4 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -383,7 +383,7 @@ static void pxa27x_keypad_config(struct pxa27x_keypad *keypad)
 	if (pdata->direct_key_num > direct_key_num)
 		direct_key_num = pdata->direct_key_num;
 
-	keypad->direct_key_mask = ((2 << direct_key_num) - 1) & ~mask;
+	keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask;
 
 	/* enable direct key */
 	if (direct_key_num)
-- 
1.7.0.4



From chao.xie at marvell.com  Thu Mar 29 21:58:17 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Fri, 30 Mar 2012 09:58:17 +0800
Subject: [PATCH V2 3/4] Input: pxa27x_keypad direct key may be low active
In-Reply-To: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
References: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1333072698-15344-3-git-send-email-chao.xie@marvell.com>

KPDK_DK only indicates the pin level of direct key.
So it is related to board, and low level may be active which
indicates that a key is pressed.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa27x_keypad.h |    2 ++
 drivers/input/keyboard/pxa27x_keypad.c         |   10 +++++++++-
 2 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
index abcc36e..7ffb16b 100644
--- a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -44,6 +44,8 @@ struct pxa27x_keypad_platform_data {
 	/* direct keys */
 	int		direct_key_num;
 	unsigned int	direct_key_map[MAX_DIRECT_KEY_NUM];
+	/* the key output may be low active */
+	int		direct_key_low_active;
 
 	/* rotary encoders 0 */
 	int		enable_rotary0;
diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index f9a76d4..b41ebda 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -311,7 +311,15 @@ static void pxa27x_keypad_scan_direct(struct pxa27x_keypad *keypad)
 	if (pdata->enable_rotary0 || pdata->enable_rotary1)
 		pxa27x_keypad_scan_rotary(keypad);
 
-	new_state = KPDK_DK(kpdk) & keypad->direct_key_mask;
+	/*
+	 * The KPDR_DK only output the key pin level, so it relates to board,
+	 * and low level may be active.
+	 */
+	if (pdata->direct_key_low_active)
+		new_state = ~KPDK_DK(kpdk) & keypad->direct_key_mask;
+	else
+		new_state = KPDK_DK(kpdk) & keypad->direct_key_mask;
+
 	bits_changed = keypad->direct_key_state ^ new_state;
 
 	if (bits_changed == 0)
-- 
1.7.0.4



From chao.xie at marvell.com  Thu Mar 29 21:58:18 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Fri, 30 Mar 2012 09:58:18 +0800
Subject: [PATCH V2 4/4] Input: pxa27x_keypad add choice to set direct_key_mask
In-Reply-To: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
References: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1333072698-15344-4-git-send-email-chao.xie@marvell.com>

Direct keys usage may not start from KP_DKIN0, add a msk option
to configure the specifics for platforms that can skip some keys.

Change-Id: Ia8fd28254fec9595dcf39f12a78392c1e8b675eb
Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa27x_keypad.h |    2 ++
 drivers/input/keyboard/pxa27x_keypad.c         |    9 ++++++++-
 2 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
index 7ffb16b..5ce8d5e 100644
--- a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -46,6 +46,8 @@ struct pxa27x_keypad_platform_data {
 	unsigned int	direct_key_map[MAX_DIRECT_KEY_NUM];
 	/* the key output may be low active */
 	int		direct_key_low_active;
+	/* give board a chance to choose the start direct key */
+	unsigned int	direct_key_mask;
 
 	/* rotary encoders 0 */
 	int		enable_rotary0;
diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index b41ebda..3da60b3 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -391,7 +391,14 @@ static void pxa27x_keypad_config(struct pxa27x_keypad *keypad)
 	if (pdata->direct_key_num > direct_key_num)
 		direct_key_num = pdata->direct_key_num;
 
-	keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask;
+	/*
+	 * Direct keys usage may not start from KP_DKIN0, check the platfrom
+	 * mask data to config the specific.
+	 */
+	if (pdata->direct_key_mask)
+		keypad->direct_key_mask = pdata->direct_key_mask;
+	else
+		keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask;
 
 	/* enable direct key */
 	if (direct_key_num)
-- 
1.7.0.4



From haojian.zhuang at gmail.com  Thu Mar 29 21:53:38 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 30 Mar 2012 09:53:38 +0800
Subject: [PATCH V2 1/4] Input: pxa27x_keypad keep clock on as wakeup source
In-Reply-To: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
References: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
Message-ID: <CAN1soZydBRqAChxKPKfz5pN8JSKKKbWBYua5KLfnQR8ZnQL-EA@mail.gmail.com>

On Fri, Mar 30, 2012 at 9:58 AM, Chao Xie <chao.xie at marvell.com> wrote:
> When the keypad is used as wake up source, the clock can not
> be disabled. Or it can not detect key pressing.
> If the keypad is used as wake up source, when resume back,
> do not enable the clock and configure it again because the
> register content is retained.
>
> Signed-off-by: Chao Xie <chao.xie at marvell.com>
> ---
> ?drivers/input/keyboard/pxa27x_keypad.c | ? 27 ++++++++++++++++++---------
> ?1 files changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
> index 29fe1b2..1c5752f 100644
> --- a/drivers/input/keyboard/pxa27x_keypad.c
> +++ b/drivers/input/keyboard/pxa27x_keypad.c
> @@ -419,10 +419,14 @@ static int pxa27x_keypad_suspend(struct device *dev)
> ? ? ? ?struct platform_device *pdev = to_platform_device(dev);
> ? ? ? ?struct pxa27x_keypad *keypad = platform_get_drvdata(pdev);
>
> - ? ? ? clk_disable(keypad->clk);
> -
> + ? ? ? /*
> + ? ? ? ?* If the keypad is used a wake up source, clock can not be disabled.
> + ? ? ? ?* Or it can not detect the key pressing.
> + ? ? ? ?*/
> ? ? ? ?if (device_may_wakeup(&pdev->dev))
> ? ? ? ? ? ? ? ?enable_irq_wake(keypad->irq);
> + ? ? ? else
> + ? ? ? ? ? ? ? clk_disable(keypad->clk);
I prefer to add one patch to use clk_prepare_enable() &
clk_disable_unprepare() in keypad driver.

>
> ? ? ? ?return 0;
> ?}
> @@ -433,19 +437,24 @@ static int pxa27x_keypad_resume(struct device *dev)
> ? ? ? ?struct pxa27x_keypad *keypad = platform_get_drvdata(pdev);
> ? ? ? ?struct input_dev *input_dev = keypad->input_dev;
>
> + ? ? ? /*
> + ? ? ? ?* If the keypad is used as wake up source, the clock is not turned
> + ? ? ? ?* off. So do not need configure it again.
> + ? ? ? ?*/
> ? ? ? ?if (device_may_wakeup(&pdev->dev))
> ? ? ? ? ? ? ? ?disable_irq_wake(keypad->irq);
> + ? ? ? else {
> + ? ? ? ? ? ? ? mutex_lock(&input_dev->mutex);
>
> - ? ? ? mutex_lock(&input_dev->mutex);
> + ? ? ? ? ? ? ? if (input_dev->users) {
> + ? ? ? ? ? ? ? ? ? ? ? /* Enable unit clock */
> + ? ? ? ? ? ? ? ? ? ? ? clk_enable(keypad->clk);
> + ? ? ? ? ? ? ? ? ? ? ? pxa27x_keypad_config(keypad);
> + ? ? ? ? ? ? ? }
>
> - ? ? ? if (input_dev->users) {
> - ? ? ? ? ? ? ? /* Enable unit clock */
> - ? ? ? ? ? ? ? clk_enable(keypad->clk);
> - ? ? ? ? ? ? ? pxa27x_keypad_config(keypad);
> + ? ? ? ? ? ? ? mutex_unlock(&input_dev->mutex);
> ? ? ? ?}
>
> - ? ? ? mutex_unlock(&input_dev->mutex);
> -
> ? ? ? ?return 0;
> ?}
>
> --
> 1.7.0.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From haojian.zhuang at gmail.com  Thu Mar 29 22:01:48 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 30 Mar 2012 10:01:48 +0800
Subject: [PATCH V2 4/4] Input: pxa27x_keypad add choice to set
 direct_key_mask
In-Reply-To: <1333072698-15344-4-git-send-email-chao.xie@marvell.com>
References: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
 <1333072698-15344-4-git-send-email-chao.xie@marvell.com>
Message-ID: <CAN1soZwVoCXyKD8antPjjGJ5XkKyQ-zz5Dkp5CaHOD5bsfge=g@mail.gmail.com>

On Fri, Mar 30, 2012 at 9:58 AM, Chao Xie <chao.xie at marvell.com> wrote:
> Direct keys usage may not start from KP_DKIN0, add a msk option
> to configure the specifics for platforms that can skip some keys.
>
> Change-Id: Ia8fd28254fec9595dcf39f12a78392c1e8b675eb

You need remove Change-Id

> Signed-off-by: Chao Xie <chao.xie at marvell.com>
> ---
> ?arch/arm/plat-pxa/include/plat/pxa27x_keypad.h | ? ?2 ++
> ?drivers/input/keyboard/pxa27x_keypad.c ? ? ? ? | ? ?9 ++++++++-
> ?2 files changed, 10 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
> index 7ffb16b..5ce8d5e 100644
> --- a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
> +++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
> @@ -46,6 +46,8 @@ struct pxa27x_keypad_platform_data {
> ? ? ? ?unsigned int ? ?direct_key_map[MAX_DIRECT_KEY_NUM];
> ? ? ? ?/* the key output may be low active */
> ? ? ? ?int ? ? ? ? ? ? direct_key_low_active;
> + ? ? ? /* give board a chance to choose the start direct key */
> + ? ? ? unsigned int ? ?direct_key_mask;
>
> ? ? ? ?/* rotary encoders 0 */
> ? ? ? ?int ? ? ? ? ? ? enable_rotary0;
> diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
> index b41ebda..3da60b3 100644
> --- a/drivers/input/keyboard/pxa27x_keypad.c
> +++ b/drivers/input/keyboard/pxa27x_keypad.c
> @@ -391,7 +391,14 @@ static void pxa27x_keypad_config(struct pxa27x_keypad *keypad)
> ? ? ? ?if (pdata->direct_key_num > direct_key_num)
> ? ? ? ? ? ? ? ?direct_key_num = pdata->direct_key_num;
>
> - ? ? ? keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask;
> + ? ? ? /*
> + ? ? ? ?* Direct keys usage may not start from KP_DKIN0, check the platfrom
> + ? ? ? ?* mask data to config the specific.
> + ? ? ? ?*/
> + ? ? ? if (pdata->direct_key_mask)
> + ? ? ? ? ? ? ? keypad->direct_key_mask = pdata->direct_key_mask;
> + ? ? ? else
> + ? ? ? ? ? ? ? keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask;
>
> ? ? ? ?/* enable direct key */
> ? ? ? ?if (direct_key_num)
> --
> 1.7.0.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From vdumpa at nvidia.com  Thu Mar 29 22:24:21 2012
From: vdumpa at nvidia.com (Krishna Reddy)
Date: Thu, 29 Mar 2012 19:24:21 -0700
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <01b301cd0d81$f935d750$eba185f0$%szyprowski@samsung.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <20120329101927.8ab6b1993475b7e16ae2258f@nvidia.com>
 <01b301cd0d81$f935d750$eba185f0$%szyprowski@samsung.com>
Message-ID: <401E54CE964CD94BAE1EB4A729C7087E37978A1E66@HQMAIL04.nvidia.com>

Hi,
I have found a bug in arm_iommu_map_sg(). 

> +int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
> +		     enum dma_data_direction dir, struct dma_attrs *attrs) {
> +	struct scatterlist *s = sg, *dma = sg, *start = sg;
> +	int i, count = 0;
> +	unsigned int offset = s->offset;
> +	unsigned int size = s->offset + s->length;
> +	unsigned int max = dma_get_max_seg_size(dev);
> +
> +	for (i = 1; i < nents; i++) {
> +		s->dma_address = ARM_DMA_ERROR;
> +		s->dma_length = 0;
> +
> +		s = sg_next(s);

With above code, the last sg element's dma_length is not getting set to zero.
This causing additional incorrect  unmapping during arm_iommu_unmap_sg call and 
leading to random crashes.
The order of above three lines should be as follows.
		s = sg_next(s);

		s->dma_address = ARM_DMA_ERROR;
		s->dma_length = 0;


-KR
--nvpublic


From olof at lixom.net  Fri Mar 30 00:01:24 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 29 Mar 2012 21:01:24 -0700
Subject: [GIT PULL] pull request from arch-pxa git on fixes branch
In-Reply-To: <CAN1soZzqxy=wsPVEXY8BxTK24szq7x5Oxk2JjuUJ6di7ij8hWA@mail.gmail.com>
References: <CAN1soZytJ-CxepQAZn5oZ06=ezTQ85O-iC7tUDOeWqi=zpuf8A@mail.gmail.com>
 <4F732D14.3020803@compulab.co.il>
 <CAOesGMgxq-HEeKSPvaW-kTLqNyDJUUmG0OEpockMBNninQL0wQ@mail.gmail.com>
 <CAN1soZzqxy=wsPVEXY8BxTK24szq7x5Oxk2JjuUJ6di7ij8hWA@mail.gmail.com>
Message-ID: <CAOesGMg+1WjWRJsL4dE3dFanRk61piqH3WcXcz-B=KTvJpaB0Q@mail.gmail.com>

On Thu, Mar 29, 2012 at 6:06 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:

> Now these build issues are fixed. Could you help to pull these fixes
> from arch-pxa git?
>
> The following changes since commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7:
>
> ?Linux 3.3 (2012-03-18 16:15:34 -0700)
>
> are available in the git repository at:
> ?git://github.com/hzhuang1/linux.git fixes

Pulled, thanks!


-Olof


From viresh.kumar at st.com  Fri Mar 30 00:01:11 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 30 Mar 2012 09:31:11 +0530
Subject: [RFC] pinctrl: Replace list_groups() with get_groups_count()
In-Reply-To: <4F74A05E.7050803@wwwdotorg.org>
References: <CAOh2x==LTHPM+O9LXVFVdX2NfzKs2bttiYLm8VcL6qLXKrUMBg@mail.gmail.com>
 <4F749B58.4070608@wwwdotorg.org>
 <CAOh2x==mGDZRoxdbuvbhKtfoxiEDVb+7vdfBEYD=u+DdMCYVhw@mail.gmail.com>
 <4F74A05E.7050803@wwwdotorg.org>
Message-ID: <4F753007.2030707@st.com>

On 3/29/2012 11:18 PM, Stephen Warren wrote:
>>> >> I vaguely recall raising the same issue before, and Linus saying he
>>> >> wanted to be consistent with similar list_*() functions in other
>>> >> subsystems, but personally I'd prefer to evaluate this aspect of the
>>> >> pinctrl subsystem on its own.
>> > 
>> > Which other subsystems have such stuff?
> For example. include/linux/regulator/driver.h struct regulator_ops field
> list_voltage().

Thanks.

Anyway, if others implement it, that doesn't mean we also do that, even
if we are not happy with it. It is not only about cleaning of code, but
it will save boot time too.

@Linus: Can i have your viewpoint before i start doing this?

-- 
viresh


From olof at lixom.net  Fri Mar 30 00:15:06 2012
From: olof at lixom.net (Olof Johansson)
Date: Thu, 29 Mar 2012 21:15:06 -0700
Subject: [GIT PULL] ARM: arm-soc fixes for 3.4-rc
Message-ID: <CAOesGMiGrqe6eB_pO_OxKFKprheZaRLsoQCus_CikfoPcs0H9w@mail.gmail.com>

Hi Linus,


The following changes since commit b5174fa3a7f4f8f150bfa3b917c92608953dfa0f:

  Merge tag 'mmc-merge-for-3.4-rc1' of
git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc (2012-03-28
20:59:45 -0700)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
tags/fixes-for-linus

for you to fetch changes up to f00e9b11863abdb837e555a2b1e3417e8b5d80dd:

  Merge branch 'fixes' of git://github.com/hzhuang1/linux into fixes
(2012-03-29 20:36:18 -0700)

----------------------------------------------------------------

ARM: arm-soc fixes for 3.4-rc

This is a first pass of some of the merge window fallout for ARM platforms.

Nothing controversial:

* A system.h fallout fix for OMAP
* PXA fixes for breakage caused by the regulator struct changes
* GPIO fixes for OMAP to properly deal with dynamic IRQ allocation
* A mismerge in our arm-soc tree of an lpc32xx change for networking
* A fix for USB setup on tegra
* An undo of __init annotation of display mux setup on OMAP that's needed
  at runtime

----------------------------------------------------------------
Govindraj.R (1):
      ARM: OMAP: pm: fix compilation break

Haojian Zhuang (2):
      ARM: pxa: fix build issue on cm-x300
      ARM: pxa: fix build issue on stargate2

Olof Johansson (3):
      Merge branch 'for-3.4/fixes-for-rc1-and-v3.3' of
git://git.kernel.org/.../swarren/linux-tegra into fixes
      Merge branch 'fixes' of
git://git.kernel.org/.../tmlind/linux-omap into fixes
      Merge branch 'fixes' of git://github.com/hzhuang1/linux into fixes

Paul Gortmaker (2):
      ARM: pxa: fix regulator related build fail in magician_defconfig
      ARM: pxa: fix build failure for regulator consumer in em-x270.c

Roland Stigge (1):
      ARM: LPC32xx: clock.c: Fix lpc-eth clock reference

Stephen Warren (1):
      ARM: tegra: Fix device tree AUXDATA for USB/EHCI

Tarun Kanti DebBarma (3):
      ARM: OMAP: boards: Fix OMAP_GPIO_IRQ usage with gpio_to_irq()
      drivers: input: Fix OMAP_GPIO_IRQ with gpio_to_irq() in
ams_delta_serio_exit()
      ARM: OMAP: Remove OMAP_GPIO_IRQ macro definition

Tomi Valkeinen (1):
      ARM: OMAP2+: Remove __init from DSI mux functions

Tony Lindgren (2):
      Merge branch 'fix-dss-mux' into fixes
      Merge branch 'fixes-gpio-to-irq' into fixes

 arch/arm/mach-lpc32xx/clock.c                |    2 +-
 arch/arm/mach-omap1/board-h2.c               |    8 ++++----
 arch/arm/mach-omap1/board-h3.c               |    9 ++++-----
 arch/arm/mach-omap1/board-htcherald.c        |    6 +++---
 arch/arm/mach-omap1/board-innovator.c        |    4 ++--
 arch/arm/mach-omap1/board-nokia770.c         |    2 +-
 arch/arm/mach-omap1/board-osk.c              |   12 ++++++------
 arch/arm/mach-omap1/board-palmte.c           |    2 +-
 arch/arm/mach-omap1/board-palmtt.c           |    2 +-
 arch/arm/mach-omap1/board-palmz71.c          |    2 +-
 arch/arm/mach-omap1/board-voiceblue.c        |   16 +++++++---------
 arch/arm/mach-omap1/pm.c                     |    1 +
 arch/arm/mach-omap2/board-2430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-4430sdp.c          |    2 +-
 arch/arm/mach-omap2/board-apollon.c          |    4 ++--
 arch/arm/mach-omap2/board-devkit8000.c       |    2 +-
 arch/arm/mach-omap2/board-h4.c               |    2 +-
 arch/arm/mach-omap2/board-omap3evm.c         |    2 +-
 arch/arm/mach-omap2/board-omap4panda.c       |    2 +-
 arch/arm/mach-omap2/board-rx51-peripherals.c |    3 ++-
 arch/arm/mach-omap2/board-zoom-debugboard.c  |    3 ++-
 arch/arm/mach-omap2/board-zoom-peripherals.c |    6 ++++--
 arch/arm/mach-omap2/common-board-devices.c   |    2 +-
 arch/arm/mach-omap2/display.c                |    8 ++++----
 arch/arm/mach-omap2/pm.c                     |    2 ++
 arch/arm/mach-pxa/cm-x300.c                  |    1 -
 arch/arm/mach-pxa/em-x270.c                  |   10 +++++-----
 arch/arm/mach-pxa/hx4700.c                   |    2 --
 arch/arm/mach-pxa/magician.c                 |    2 --
 arch/arm/mach-pxa/stargate2.c                |    2 +-
 arch/arm/mach-tegra/board-dt-tegra20.c       |    6 +++---
 arch/arm/mach-tegra/devices.c                |    7 +++----
 arch/arm/mach-tegra/devices.h                |    5 +++++
 arch/arm/plat-omap/include/plat/gpio.h       |    4 ----
 drivers/input/serio/ams_delta_serio.c        |    2 +-
 35 files changed, 73 insertions(+), 74 deletions(-)


From plagnioj at jcrosoft.com  Fri Mar 30 00:34:56 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 30 Mar 2012 06:34:56 +0200
Subject: [PATCH 03/17] ARM: mark const init data with __initconst
 instead of __initdata
In-Reply-To: <1333055554-31300-3-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20120329211131.GA31250@pengutronix.de>
 <1333055554-31300-3-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120330043456.GL7757@game.jcrosoft.org>

On 23:12 Thu 29 Mar     , Uwe Kleine-K?nig wrote:
> As long as there is no other non-const variable marked __initdata in the
> same compilation unit it doesn't hurt. If there were one however
> compilation would fail with
> 
> 	error: $variablename causes a section type conflict
> 
> because a section containing const variables is marked read only and so
> cannot contain non-const variables.
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> Cc: Andrew Victor <linux at maxim.org.za>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: Jean-Christophe Plagniol-Villard <plagnioj at jcrosoft.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Sekhar Nori <nsekhar at ti.com>
> Cc: Kevin Hilman <khilman at ti.com>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Cc: Sascha Hauer <kernel at pengutronix.de>
> Cc: Shawn Guo <shawn.guo at linaro.org>
> Cc: Lennert Buytenhek <kernel at wantstofly.org>
> Cc: Nicolas Pitre <nico at fluxnic.net>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: David Brown <davidb at codeaurora.org>
> Cc: Daniel Walker <dwalker at fifo99.com>
> Cc: Bryan Huntsman <bryanh at codeaurora.org>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Barry Song <baohua.song at csr.com>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Lucas De Marchi <lucas.demarchi at profusion.mobi>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: davinci-linux-open-source at linux.davincidsp.com
> Cc: linux-samsung-soc at vger.kernel.org
> Cc: linux-arm-msm at vger.kernel.org
> Cc: linux-omap at vger.kernel.org
> ---
>  arch/arm/mach-at91/board-dt.c                 |    2 +-
>  arch/arm/mach-at91/clock.c                    |    2 +-
for at91
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Best Regards,
J.


From linus.walleij at linaro.org  Fri Mar 30 01:03:00 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 30 Mar 2012 07:03:00 +0200
Subject: [RFC] pinctrl: Replace list_groups() with get_groups_count()
In-Reply-To: <4F74A05E.7050803@wwwdotorg.org>
References: <CAOh2x==LTHPM+O9LXVFVdX2NfzKs2bttiYLm8VcL6qLXKrUMBg@mail.gmail.com>
 <4F749B58.4070608@wwwdotorg.org>
 <CAOh2x==mGDZRoxdbuvbhKtfoxiEDVb+7vdfBEYD=u+DdMCYVhw@mail.gmail.com>
 <4F74A05E.7050803@wwwdotorg.org>
Message-ID: <CACRpkda8cYSw6m6GaH403SqoUfn7sky13Gw0okqmZse1ferARA@mail.gmail.com>

On Thu, Mar 29, 2012 at 7:48 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> On 03/29/2012 11:31 AM, viresh kumar wrote:
>> On Mar 29, 2012 10:56 PM, Stephen Warren wrote:
>>> On 03/29/2012 10:34 AM, viresh kumar wrote:
> ...
>>> I vaguely recall raising the same issue before, and Linus saying he
>>> wanted to be consistent with similar list_*() functions in other
>>> subsystems, but personally I'd prefer to evaluate this aspect of the
>>> pinctrl subsystem on its own.
>>
>> Which other subsystems have such stuff?
>
> For example. include/linux/regulator/driver.h struct regulator_ops field
> list_voltage().

Well, actually .list_voltage() returns the voltage per se for each
enumerator, so it works like this quick way to iterate over a list
of integers.

But since we're not really getting anything back from the .list_groups()
callback, just zero or error, there is no specific point in having
it engineered like this.

So please go ahead and patch it in whatever way makes more
sense!

Thanks,
Linus Walleij


From linus.walleij at linaro.org  Fri Mar 30 01:04:55 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 30 Mar 2012 07:04:55 +0200
Subject: [RFC] pinctrl: Replace list_groups() with get_groups_count()
In-Reply-To: <4F753007.2030707@st.com>
References: <CAOh2x==LTHPM+O9LXVFVdX2NfzKs2bttiYLm8VcL6qLXKrUMBg@mail.gmail.com>
 <4F749B58.4070608@wwwdotorg.org>
 <CAOh2x==mGDZRoxdbuvbhKtfoxiEDVb+7vdfBEYD=u+DdMCYVhw@mail.gmail.com>
 <4F74A05E.7050803@wwwdotorg.org> <4F753007.2030707@st.com>
Message-ID: <CACRpkdYaJ8sH0u6VTiaiPOJJ-D0pDo5oONyFXA4EvtL+WXEtjw@mail.gmail.com>

On Fri, Mar 30, 2012 at 6:01 AM, Viresh Kumar <viresh.kumar at st.com> wrote:

> Anyway, if others implement it, that doesn't mean we also do that, even
> if we are not happy with it. It is not only about cleaning of code, but
> it will save boot time too.
>
> @Linus: Can i have your viewpoint before i start doing this?

Just patch it, as detailed in the other letter there is really no point
for having it like this so go ahead. As long as you also patch all
the users and remove the old interface, just rewrite it. If you could
also test it on something it'd be nice ...

Yours,
Linus Walleij


From thierry.reding at avionic-design.de  Fri Mar 30 01:06:41 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 30 Mar 2012 07:06:41 +0200
Subject: [PATCH v5 04/16] pwm: Add table-based lookup for static mappings
In-Reply-To: <20120329220342.GK4153@opensource.wolfsonmicro.com>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-5-git-send-email-thierry.reding@avionic-design.de>
 <20120329220342.GK4153@opensource.wolfsonmicro.com>
Message-ID: <20120330050641.GA21823@avionic-0098.mockup.avionic-design.de>

* Mark Brown wrote:
> On Wed, Mar 28, 2012 at 04:33:46PM +0200, Thierry Reding wrote:
> 
> > +	static struct pwm_lookup board_pwm_lookup[] = {
> > +		PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight"),
> > +	};
> 
> The clock and regulator APIs namespace the consumers by struct device -
> might this not be sensible here?  pwm_get() does already take the device
> as an argument.  It'd feel safer, and for example there's plenty of
> phones out there with two backlit displays...

That's actually how this is supposed to work. "pwm-backlight" in the above
case is matched against the name of the struct device that you pass in to
pwm_get(). The only difference, at least as far as I can tell, to the clock
and regulator APIs is that a second name is not listed explicitly in the
lookup table.

So compared with the clock and regulator APIs it doesn't make too much sense
to pass both the struct device and the name to pwm_get() because it will
match the device name against the consumer name in the lookup table first and
only use the passed name if no match was found.

In case you have two backlight devices I would expect the following to work:

	static struct pwm_lookup board_pwm_lookup[] = {
		PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight.0"),
		PWM_LOOKUP("tegra-pwm", 1, "pwm-backlight.1"),
	};

> 
> > + * pwm_get() - look up and request a PWM device
> > + * @dev: device for PWM consumer
> > + * @provider: name of provider PWM chip
> > + * @index: per-chip index of PWM to request
> 
> The documentation is out of sync with the signature.

Indeed. Thanks.

Thierry
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From viresh.kumar at st.com  Fri Mar 30 01:09:07 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 30 Mar 2012 10:39:07 +0530
Subject: [RFC] pinctrl: Replace list_groups() with get_groups_count()
In-Reply-To: <CACRpkdYaJ8sH0u6VTiaiPOJJ-D0pDo5oONyFXA4EvtL+WXEtjw@mail.gmail.com>
References: <CAOh2x==LTHPM+O9LXVFVdX2NfzKs2bttiYLm8VcL6qLXKrUMBg@mail.gmail.com>
 <4F749B58.4070608@wwwdotorg.org>
 <CAOh2x==mGDZRoxdbuvbhKtfoxiEDVb+7vdfBEYD=u+DdMCYVhw@mail.gmail.com>
 <4F74A05E.7050803@wwwdotorg.org>	<4F753007.2030707@st.com>
 <CACRpkdYaJ8sH0u6VTiaiPOJJ-D0pDo5oONyFXA4EvtL+WXEtjw@mail.gmail.com>
Message-ID: <4F753FF3.4040704@st.com>

On 3/30/2012 10:34 AM, Linus Walleij wrote:
> Just patch it, as detailed in the other letter there is really no point
> for having it like this so go ahead. As long as you also patch all
> the users and remove the old interface, just rewrite it.

I have this in mind. Will fix all users.

> If you could also test it on something it'd be nice ...

I don't have any board to test it. But after i am done with this, i
will complete pinctrl support for SPEAr and there i can test it.

I hope before that lot of other people would be able to test it. :)

BTW, i am planning not to add another call, get_groups_count(),
but add another field like ngroups, which would be set by users.

-- 
viresh


From linus.walleij at linaro.org  Fri Mar 30 01:14:34 2012
From: linus.walleij at linaro.org (Linus Walleij)
Date: Fri, 30 Mar 2012 07:14:34 +0200
Subject: [RFC] pinctrl: Replace list_groups() with get_groups_count()
In-Reply-To: <4F753FF3.4040704@st.com>
References: <CAOh2x==LTHPM+O9LXVFVdX2NfzKs2bttiYLm8VcL6qLXKrUMBg@mail.gmail.com>
 <4F749B58.4070608@wwwdotorg.org>
 <CAOh2x==mGDZRoxdbuvbhKtfoxiEDVb+7vdfBEYD=u+DdMCYVhw@mail.gmail.com>
 <4F74A05E.7050803@wwwdotorg.org> <4F753007.2030707@st.com>
 <CACRpkdYaJ8sH0u6VTiaiPOJJ-D0pDo5oONyFXA4EvtL+WXEtjw@mail.gmail.com>
 <4F753FF3.4040704@st.com>
Message-ID: <CACRpkdaJpy_iRg4XzJepn=5tXLxBeYq3aMk1M_Z7WLD1+gw8iA@mail.gmail.com>

On Fri, Mar 30, 2012 at 7:09 AM, Viresh Kumar <viresh.kumar at st.com> wrote:

> BTW, i am planning not to add another call, get_groups_count(),
> but add another field like ngroups, which would be set by users.

get_groups_count() may make some sense if the number of
available groups could in some instance change at runtime.
Maybe a bit overcautious and pedantic but you never know...

But do it any way you like, I don't worry very much :-)

Yours,
Linus Walleij


From viresh.kumar at st.com  Fri Mar 30 01:15:19 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 30 Mar 2012 10:45:19 +0530
Subject: [RFC] pinctrl: Replace list_groups() with get_groups_count()
In-Reply-To: <CACRpkdaJpy_iRg4XzJepn=5tXLxBeYq3aMk1M_Z7WLD1+gw8iA@mail.gmail.com>
References: <CAOh2x==LTHPM+O9LXVFVdX2NfzKs2bttiYLm8VcL6qLXKrUMBg@mail.gmail.com>
 <4F749B58.4070608@wwwdotorg.org>
 <CAOh2x==mGDZRoxdbuvbhKtfoxiEDVb+7vdfBEYD=u+DdMCYVhw@mail.gmail.com>
 <4F74A05E.7050803@wwwdotorg.org>	<4F753007.2030707@st.com>
 <CACRpkdYaJ8sH0u6VTiaiPOJJ-D0pDo5oONyFXA4EvtL+WXEtjw@mail.gmail.com>
 <4F753FF3.4040704@st.com>
 <CACRpkdaJpy_iRg4XzJepn=5tXLxBeYq3aMk1M_Z7WLD1+gw8iA@mail.gmail.com>
Message-ID: <4F754167.4040405@st.com>

On 3/30/2012 10:44 AM, Linus Walleij wrote:
> get_groups_count() may make some sense if the number of
> available groups could in some instance change at runtime.
> Maybe a bit overcautious and pedantic but you never know...

Will go with get_groups_count(); :)

-- 
viresh


From thomas.abraham at linaro.org  Fri Mar 30 01:53:17 2012
From: thomas.abraham at linaro.org (Thomas Abraham)
Date: Fri, 30 Mar 2012 11:23:17 +0530
Subject: [PATCH v2] video: s3c-fb: Add device tree support
Message-ID: <1333086797-1625-1-git-send-email-thomas.abraham@linaro.org>

Add device tree based discovery support for Samsung's display controller
framebuffer driver.

Cc: Jingoo Han <jg1.han at samsung.com>
Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: Rob Herring <rob.herring at calxeda.com>
Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
---
 .../devicetree/bindings/fb/samsung-fb.txt          |  148 +++++++++++++
 drivers/video/s3c-fb.c                             |  230 +++++++++++++++++++-
 2 files changed, 370 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/fb/samsung-fb.txt

diff --git a/Documentation/devicetree/bindings/fb/samsung-fb.txt b/Documentation/devicetree/bindings/fb/samsung-fb.txt
new file mode 100644
index 0000000..612bd9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/fb/samsung-fb.txt
@@ -0,0 +1,148 @@
+* Samsung Display Controller Framebuffer Controller
+
+The display controller is used to transfer image data from memory to a
+external display device such as an RGB interface LCD panel. It supports
+various color formats such as rgb and yuv. It also supports multiple window
+overlays.
+
+Required properties:
+
+    - compatible: should be one of the following
+      - samsung,exynos4210-fimd: for fimd compatible with Exynos4210 fimd
+      - samsung,s5pv210-fimd: for fimd compatible with s5pv210 fimd
+
+    - reg: physical base address of the controller and length of memory
+      mapped region.
+
+    - interrupts: Three interrupts should be specified. The format of the
+      interrupt specifier depends on the interrupt controller. The interrupts
+      should be specified in the following order.
+      - VSYNC (Video Frame) interrupt
+      - Video FIFO level interrupt
+      - FIMD System Interrupt
+
+    - gpios: The gpios used to interface with the external LCD panel. For a
+      panel with rgb interface, the gpio interface consists of video data
+      lines, HSYNC, VSYNC, Pixel Clock and Data Enable. The gpio's used for
+      these interface lines can be listed under this property in any order.
+
+    - samsung,fimd-display: The fimd controller is interfaced with the a
+      display device such as a lcd panel. This property should specify the
+      phandle of the display device node. For a display device node that
+      represents a RGB type display interface, it is expected to specify the
+      video interface timing using the following properties.
+
+      - lcd-htiming: Specifies the horizontal timing for the overlay. The
+        horizontal timing includes four parameters in the following order.
+
+        - horizontal back porch (in number of lcd clocks)
+        - horizontal front porch (in number of lcd clocks)
+        - hsync pulse width (in number of lcd clocks)
+        - Display panels X resolution.
+
+      - lcd-vtiming: Specifies the vertical timing for the overlay. The
+        vertical timing includes four parameters in the following order.
+
+        - vertical back porch (in number of lcd lines)
+        - vertical front porch (in number of lcd lines)
+        - vsync pulse width (in number of lcd clocks)
+        - Y resolution.
+
+    - Overlay/Windows: Multiple overlays/windows can be specified as child
+      nodes. Each window should have the following properties (optional
+      window properties are marked as 'optional').
+
+      - samsung,fimd-win-id: Specifies the window number of the fimd controller.
+
+      - samsung,fimd-win-bpp: Specifies the bits per pixel. Two values should
+	be specified in the following order.
+        - default-bpp: bpp supported by the overlay.
+        - max-bpp: maximum required bpp for the overlay.
+
+      - samsung,fimd-win-res: (OPTIONAL) Specifies the window resolution in
+        pixels. The resolution contains the X and Y pixel values with X being
+        specified first. If this property is not specified, the window
+        resolution is set to be equal to the display panel resolution.
+
+      - samsung,fimd-win-virtres: (OPTIONAL) Specifies the resolution of the
+        virtual frame buffer for the window. The resolution contains the X
+        and Y resolution in pixels with value of X being the specified first.
+
+Optional properties:
+
+    - samsung,fimd-vidout-rgb: Video output format is RGB.
+    - samsung,fimd-inv-hsync: invert hsync pulse polarity.
+    - samsung,fimd-inv-vsync: invert vsync pulse polarity.
+    - samsung,fimd-inv-vclk: invert video clock polarity.
+    - samsung,fimd-inv-vden: invert video enable signal polarity.
+    - samsung,fimd-frame-rate: Number of video frames per second.
+
+Example:
+
+    The following is an example for the fimd framebuffer controller is split
+    into two portions. The SoC specific portion can be specified in the SoC
+    specific dts file. The board specific portion can be specified in the
+    board specific dts file.
+
+    - SoC Specific portion
+
+	fimd at 11C00000 {
+		compatible = "samsung,exynos4210-fimd";
+		interrupt-parent = <&combiner>;
+		reg = <0x11C00000 0x8000>;
+		interrupts = <11 1>, <11 0>, <11 2>;
+	};
+
+    - Board Specific portion
+
+	fimd at 11C00000 {
+		samsung,fimd-display = <&lcd_fimd0>;
+		samsung,fimd-vidout-rgb;
+		samsung,fimd-inv-hsync;
+		samsung,fimd-inv-vsync;
+		samsung,fimd-inv-vclk;
+		samsung,fimd-frame-rate = <60>;
+
+		gpios = <&gpf0 0 2 0 0>,
+			<&gpf0 1 2 0 0>,
+			<&gpf0 2 2 0 0>,
+			<&gpf0 3 2 0 0>,
+			<&gpf0 4 2 0 0>,
+			<&gpf0 5 2 0 0>,
+			<&gpf0 6 2 0 0>,
+			<&gpf0 7 2 0 0>,
+			<&gpf1 0 2 0 0>,
+			<&gpf1 1 2 0 0>,
+			<&gpf1 2 2 0 0>,
+			<&gpf1 3 2 0 0>,
+			<&gpf1 4 2 0 0>,
+			<&gpf1 5 2 0 0>,
+			<&gpf1 6 2 0 0>,
+			<&gpf1 7 2 0 0>,
+			<&gpf2 0 2 0 0>,
+			<&gpf2 1 2 0 0>,
+			<&gpf2 2 2 0 0>,
+			<&gpf2 3 2 0 0>,
+			<&gpf2 4 2 0 0>,
+			<&gpf2 5 2 0 0>,
+			<&gpf2 6 2 0 0>,
+			<&gpf2 7 2 0 0>,
+			<&gpf3 0 2 0 0>,
+			<&gpf3 1 2 0 0>,
+			<&gpf3 2 2 0 0>,
+			<&gpf3 3 2 0 0>;
+
+		window0 {
+			samsung,fimd-win-id = <0>;
+			samsung,fimd-win-bpp = <32 24>;
+			samsung,fimd-win-res = <512 300>;
+			samsung,fimd-win-vres = <1024 600>;
+		};
+
+		window1 {
+			samsung,fimd-win-id = <1>;
+			samsung,fimd-win-bpp = <32 24>;
+			samsung,fimd-win-res = <1024 200>;
+			samsung,fimd-win-vres = <1024 600>;
+		};
+	};
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 18c84b8..b8be668 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -24,6 +24,8 @@
 #include <linux/uaccess.h>
 #include <linux/interrupt.h>
 #include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
 
 #include <mach/map.h>
 #include <plat/regs-fb-v4.h>
@@ -220,6 +222,7 @@ struct s3c_fb {
 	int			 irq_no;
 	unsigned long		 irq_flags;
 	struct s3c_fb_vsync	 vsync_info;
+	int			 *gpios;
 };
 
 /**
@@ -1352,27 +1355,215 @@ static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
 	writel(reg & ~SHADOWCON_WINx_PROTECT(win), regs + SHADOWCON);
 }
 
+#ifdef CONFIG_OF
+static int s3c_fb_dt_parse_gpios(struct device *dev, struct s3c_fb *sfb,
+						bool request)
+{
+	int nr_gpios, idx, gpio, ret;
+
+	nr_gpios = sfb->pdata->win[0]->max_bpp + 4;
+	sfb->gpios = devm_kzalloc(dev, sizeof(int) * nr_gpios, GFP_KERNEL);
+	if (!sfb->gpios) {
+		dev_err(dev, "unable to allocate private data for gpio\n");
+		return -ENOMEM;
+	}
+
+	for (idx = 0; idx < nr_gpios; idx++) {
+		gpio = of_get_gpio(dev->of_node, idx);
+		if (!gpio_is_valid(gpio)) {
+			dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio);
+			return -EINVAL;
+		}
+
+		if (!request)
+			continue;
+
+		ret = gpio_request(gpio, "fimd");
+		if (ret) {
+			dev_err(dev, "gpio [%d] request failed\n", gpio);
+			goto gpio_free;
+		}
+		sfb->gpios[idx] = gpio;
+	}
+	return 0;
+
+gpio_free:
+	while (--idx >= 0)
+		gpio_free(sfb->gpios[idx]);
+	return ret;
+}
+
+static void s3c_fb_dt_free_gpios(struct s3c_fb *sfb)
+{
+	unsigned int idx, nr_gpio;
+
+	nr_gpio = sfb->pdata->win[0]->max_bpp + 4;
+	for (idx = 0; idx < nr_gpio; idx++)
+		gpio_free(sfb->gpios[idx]);
+}
+
+static struct s3c_fb_platdata *s3c_fb_dt_parse_pdata(struct device *dev)
+{
+	struct device_node *np = dev->of_node, *win_np;
+	struct device_node *disp_np;
+	struct s3c_fb_platdata *pd;
+	struct s3c_fb_pd_win *win;
+	u32 wnum = 0, data[4];
+
+	pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+	if (!pd) {
+		dev_err(dev, "memory allocation for pdata failed\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	pd->vtiming = devm_kzalloc(dev, sizeof(*pd->vtiming), GFP_KERNEL);
+	if (!pd->vtiming) {
+		dev_err(dev, "memory allocation for vtiming failed\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	if (of_get_property(np, "samsung,fimd-vidout-rgb", NULL))
+		pd->vidcon0 |= VIDCON0_VIDOUT_RGB;
+	if (of_get_property(np, "samsung,fimd-vidout-tv", NULL))
+		pd->vidcon0 |= VIDCON0_VIDOUT_TV;
+	if (of_get_property(np, "samsung,fimd-inv-hsync", NULL))
+		pd->vidcon1 |= VIDCON1_INV_HSYNC;
+	if (of_get_property(np, "samsung,fimd-inv-vsync", NULL))
+		pd->vidcon1 |= VIDCON1_INV_VSYNC;
+	if (of_get_property(np, "samsung,fimd-inv-vclk", NULL))
+		pd->vidcon1 |= VIDCON1_INV_VCLK;
+	if (of_get_property(np, "samsung,fimd-inv-vden", NULL))
+		pd->vidcon1 |= VIDCON1_INV_VDEN;
+
+	disp_np = of_parse_phandle(np, "samsung,fimd-display", 0);
+	if (!disp_np) {
+		dev_err(dev, "unable to find display panel info\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (of_property_read_u32_array(disp_np, "lcd-htiming", data, 4)) {
+		dev_err(dev, "invalid horizontal timing\n");
+		return ERR_PTR(-EINVAL);
+	}
+	pd->vtiming->left_margin = data[0];
+	pd->vtiming->right_margin = data[1];
+	pd->vtiming->hsync_len = data[2];
+	pd->vtiming->xres = data[3];
+
+	if (of_property_read_u32_array(disp_np, "lcd-vtiming", data, 4)) {
+		dev_err(dev, "invalid vertical timing\n");
+		return ERR_PTR(-EINVAL);
+	}
+	pd->vtiming->upper_margin = data[0];
+	pd->vtiming->lower_margin = data[1];
+	pd->vtiming->vsync_len = data[2];
+	pd->vtiming->yres = data[3];
+
+	of_property_read_u32_array(np, "samsung,fimd-frame-rate",
+				&pd->vtiming->refresh, 1);
+
+	for_each_child_of_node(np, win_np) {
+		if (of_property_read_u32_array(win_np, "samsung,fimd-win-id",
+						&wnum, 1)) {
+			dev_err(dev, "window id not specified\n");
+			return ERR_PTR(-EINVAL);
+		}
+
+		win = devm_kzalloc(dev, sizeof(*win), GFP_KERNEL);
+		if (!win) {
+			dev_err(dev, "no memory for window[%d] data\n", wnum);
+			return ERR_PTR(-ENOMEM);
+		}
+		pd->win[wnum] = win;
+
+		if (of_property_read_u32_array(win_np, "samsung,fimd-win-bpp",
+						data, 2)) {
+			dev_err(dev, "invalid window bpp\n");
+			return ERR_PTR(-EINVAL);
+		}
+		win->default_bpp = data[0];
+		win->max_bpp = data[1];
+
+		if (of_property_read_u32_array(win_np, "samsung,fimd-win-res",
+						data, 2)) {
+			dev_info(dev, "window [%d] resolution not specified. "
+				"Using lcd resolution X[%d] and Y[%d]", wnum,
+				pd->vtiming->xres, pd->vtiming->yres);
+			win->xres = pd->vtiming->xres;
+			win->yres = pd->vtiming->yres;
+		} else {
+			win->xres = data[0];
+			win->yres = data[1];
+		}
+
+		if (!of_property_read_u32_array(win_np,
+				"samsung,fimd-win-virtres", data, 2)) {
+			win->virtual_x = data[0];
+			win->virtual_y = data[1];
+		}
+	}
+
+	return pd;
+}
+#else
+static int s3c_fb_dt_parse_gpios(struct device *dev, struct s3c_fb *sfb,
+						bool request)
+{
+	return 0;
+}
+
+static void s3c_fb_dt_free_gpios(struct s3c_fb *sfb)
+{
+	return 0;
+}
+
+static int s3c_fb_dt_parse_pdata(struct device *dev,
+					struct s3c_fb_platdata **pdata)
+{
+	return 0;
+}
+#endif /* CONFIG_OF */
+
+static const struct of_device_id s3c_fb_dt_match[];
+
+static inline struct s3c_fb_driverdata *s3c_fb_get_driver_data(
+			struct platform_device *pdev)
+{
+#ifdef CONFIG_OF
+	if (pdev->dev.of_node) {
+		const struct of_device_id *match;
+		match = of_match_node(s3c_fb_dt_match, pdev->dev.of_node);
+		return (struct s3c_fb_driverdata *)match->data;
+	}
+#endif
+	return (struct s3c_fb_driverdata *)
+			platform_get_device_id(pdev)->driver_data;
+}
+
 static int __devinit s3c_fb_probe(struct platform_device *pdev)
 {
-	const struct platform_device_id *platid;
 	struct s3c_fb_driverdata *fbdrv;
 	struct device *dev = &pdev->dev;
-	struct s3c_fb_platdata *pd;
+	struct s3c_fb_platdata *pd = pdev->dev.platform_data;
 	struct s3c_fb *sfb;
 	struct resource *res;
 	int win;
 	int ret = 0;
 	u32 reg;
 
-	platid = platform_get_device_id(pdev);
-	fbdrv = (struct s3c_fb_driverdata *)platid->driver_data;
+	fbdrv = s3c_fb_get_driver_data(pdev);
 
 	if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
 		dev_err(dev, "too many windows, cannot attach\n");
 		return -EINVAL;
 	}
 
-	pd = pdev->dev.platform_data;
+	if (pdev->dev.of_node) {
+		pd = s3c_fb_dt_parse_pdata(&pdev->dev);
+		if (IS_ERR(pd))
+			return PTR_ERR(pd);
+	}
+
 	if (!pd) {
 		dev_err(dev, "no platform data specified\n");
 		return -EINVAL;
@@ -1449,7 +1640,12 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
 
 	/* setup gpio and output polarity controls */
 
-	pd->setup_gpio();
+	if (dev->of_node) {
+		if (s3c_fb_dt_parse_gpios(dev, sfb, true))
+			goto err_lcd_clk;
+	} else {
+		pd->setup_gpio();
+	}
 
 	writel(pd->vidcon1, sfb->regs + VIDCON1);
 
@@ -1499,6 +1695,7 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
 	return 0;
 
 err_pm_runtime:
+	s3c_fb_dt_free_gpios(sfb);
 	pm_runtime_put_sync(sfb->dev);
 
 err_lcd_clk:
@@ -1545,6 +1742,7 @@ static int __devexit s3c_fb_remove(struct platform_device *pdev)
 
 	pm_runtime_put_sync(sfb->dev);
 	pm_runtime_disable(sfb->dev);
+	s3c_fb_dt_free_gpios(sfb);
 
 	return 0;
 }
@@ -1588,7 +1786,10 @@ static int s3c_fb_resume(struct device *dev)
 		clk_enable(sfb->lcd_clk);
 
 	/* setup gpio and output polarity controls */
-	pd->setup_gpio();
+	if (dev->of_node)
+		s3c_fb_dt_parse_gpios(dev, sfb, false);
+	else
+		pd->setup_gpio();
 	writel(pd->vidcon1, sfb->regs + VIDCON1);
 
 	/* set video clock running at under-run */
@@ -1658,7 +1859,10 @@ static int s3c_fb_runtime_resume(struct device *dev)
 		clk_enable(sfb->lcd_clk);
 
 	/* setup gpio and output polarity controls */
-	pd->setup_gpio();
+	if (dev->of_node)
+		s3c_fb_dt_parse_gpios(dev, sfb, false);
+	else
+		pd->setup_gpio();
 	writel(pd->vidcon1, sfb->regs + VIDCON1);
 
 	return 0;
@@ -2028,6 +2232,15 @@ static struct platform_device_id s3c_fb_driver_ids[] = {
 };
 MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
 
+#ifdef CONFIG_OF
+static const struct of_device_id s3c_fb_dt_match[] = {
+	{ .compatible = "samsung,exynos4210-fimd",
+		.data = (void *)&s3c_fb_data_exynos4 },
+	{},
+};
+MODULE_DEVICE_TABLE(of, s3c_fb_dt_match);
+#endif
+
 static const struct dev_pm_ops s3cfb_pm_ops = {
 	SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume)
 	SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume,
@@ -2042,6 +2255,7 @@ static struct platform_driver s3c_fb_driver = {
 		.name	= "s3c-fb",
 		.owner	= THIS_MODULE,
 		.pm	= &s3cfb_pm_ops,
+		.of_match_table	= of_match_ptr(s3c_fb_dt_match),
 	},
 };
 
-- 
1.6.6.rc2



From shawn.guo at linaro.org  Fri Mar 30 01:55:53 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 30 Mar 2012 13:55:53 +0800
Subject: [PATCH] ASoC: fsl: enable ssi clock in probe function
In-Reply-To: <4F748C8E.1010702@freescale.com>
References: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>
 <20120329112949.GM3668@opensource.wolfsonmicro.com>
 <4F748751.3020300@freescale.com>
 <20120329160916.GG19506@S2101-09.ap.freescale.net>
 <4F748C8E.1010702@freescale.com>
Message-ID: <20120330055543.GH19506@S2101-09.ap.freescale.net>

On Thu, Mar 29, 2012 at 11:23:42AM -0500, Timur Tabi wrote:
> Shawn Guo wrote:
> > d18b63ab0b04af1bad01e59a96b88fc8cda08752
> > ASoC: core: Use driver core probe deferral
> 
> That fixed it, but the SHA in my repository is
> 97883ef0a8f61fbd5fb8242980f6998290d1dd95
> 
> Anyway, I just want to say that for-3.5 still works on PowerPC.
> 
I guess you only meant mpc85xx_defconfig (and mpc85xx_smp_defconfig).
I sent the patch after compile-testing for mpc85xx_defconfig, and
took it for granted that mpc8610_hpcd_defconfig will also compile.
But I just discovered that PPC_CLOCK is not enabled for
mpc8610_hpcd_defconfig, so it fails on the final link.

I just sent a patch proposing to fix it by always building in PPC_CLOCK
for FSL_SOC.

-- 
Regards,
Shawn


From shawn.guo at linaro.org  Fri Mar 30 02:11:36 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 30 Mar 2012 14:11:36 +0800
Subject: [PATCH 03/17] ARM: mark const init data with __initconst instead
 of __initdata
In-Reply-To: <1333055554-31300-3-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20120329211131.GA31250@pengutronix.de>
 <1333055554-31300-3-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120330061134.GD3254@S2101-09.ap.freescale.net>

On Thu, Mar 29, 2012 at 11:12:20PM +0200, Uwe Kleine-K?nig wrote:
...
> diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
> index 5cca573..7e00748 100644
> --- a/arch/arm/mach-imx/imx51-dt.c
> +++ b/arch/arm/mach-imx/imx51-dt.c
> @@ -102,7 +102,7 @@ static struct sys_timer imx51_timer = {
>  	.init = imx51_timer_init,
>  };
>  
> -static const char *imx51_dt_board_compat[] __initdata = {
> +static const char *imx51_dt_board_compat[] __initconst = {
>  	"fsl,imx51-babbage",
>  	"fsl,imx51",
>  	NULL

  CC      arch/arm/mach-imx/imx51-dt.o
arch/arm/mach-imx/imx51-dt.c:105:20: error: imx51_dt_board_compat causes a section type conflict
make[2]: *** [arch/arm/mach-imx/imx51-dt.o] Error 1

I do not understand why though.

-- 
Regards,
Shawn


From viresh.kumar at st.com  Fri Mar 30 01:55:40 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 30 Mar 2012 11:25:40 +0530
Subject: [PATCH] pinctrl: Replace list_*() with get_*_count()
Message-ID: <10b8e68e37a8992646e9b84521ec48953612d83c.1333086742.git.viresh.kumar@st.com>

Most of the SoC drivers implement list_groups() and list_functions() routines
for pinctrl and pinmux. These routines continue returning zero until the
selector argument is greater than total count of available groups or functions.

This patch replaces these list_*() routines with get_*_count() routines, which
returns the number of available selection for SoC driver. pinctrl layer will use
this value to check the range it can choose.

This patch fixes all user drivers for this change. There are other routines in
user drivers, which have checks to check validity of selector passed to them. It
is also no more required and hence removed.

Documentation updated as well.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 Documentation/pinctrl.txt        |   37 +++++++++++++++----------------------
 drivers/pinctrl/core.c           |    9 ++++++---
 drivers/pinctrl/pinconf.c        |    3 ++-
 drivers/pinctrl/pinctrl-pxa3xx.c |   24 ++++++++++--------------
 drivers/pinctrl/pinctrl-sirf.c   |   20 ++++++--------------
 drivers/pinctrl/pinctrl-tegra.c  |   34 ++++++----------------------------
 drivers/pinctrl/pinctrl-u300.c   |   20 ++++++--------------
 drivers/pinctrl/pinmux.c         |   11 +++++++----
 include/linux/pinctrl/pinctrl.h  |    6 ++----
 include/linux/pinctrl/pinmux.h   |    7 +++----
 10 files changed, 63 insertions(+), 108 deletions(-)

diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index f2e27ef..6e0c9ca 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -152,11 +152,9 @@ static const struct foo_group foo_groups[] = {
 };
 
 
-static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 {
-	if (selector >= ARRAY_SIZE(foo_groups))
-		return -EINVAL;
-	return 0;
+	return ARRAY_SIZE(foo_groups);
 }
 
 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -175,7 +173,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinctrl_ops foo_pctrl_ops = {
-	.list_groups = foo_list_groups,
+	.get_groups_count = foo_get_groups_count,
 	.get_group_name = foo_get_group_name,
 	.get_group_pins = foo_get_group_pins,
 };
@@ -186,13 +184,12 @@ static struct pinctrl_desc foo_desc = {
        .pctlops = &foo_pctrl_ops,
 };
 
-The pin control subsystem will call the .list_groups() function repeatedly
-beginning on 0 until it returns non-zero to determine legal selectors, then
-it will call the other functions to retrieve the name and pins of the group.
-Maintaining the data structure of the groups is up to the driver, this is
-just a simple example - in practice you may need more entries in your group
-structure, for example specific register ranges associated with each group
-and so on.
+The pin control subsystem will call the .get_groups_count() function to
+determine total number of legal selectors, then it will call the other functions
+to retrieve the name and pins of the group. Maintaining the data structure of
+the groups is up to the driver, this is just a simple example - in practice you
+may need more entries in your group structure, for example specific register
+ranges associated with each group and so on.
 
 
 Pin configuration
@@ -606,11 +603,9 @@ static const struct foo_group foo_groups[] = {
 };
 
 
-static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 {
-	if (selector >= ARRAY_SIZE(foo_groups))
-		return -EINVAL;
-	return 0;
+	return ARRAY_SIZE(foo_groups);
 }
 
 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -629,7 +624,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinctrl_ops foo_pctrl_ops = {
-	.list_groups = foo_list_groups,
+	.get_groups_count = foo_get_groups_count,
 	.get_group_name = foo_get_group_name,
 	.get_group_pins = foo_get_group_pins,
 };
@@ -663,11 +658,9 @@ static const struct foo_pmx_func foo_functions[] = {
 	},
 };
 
-int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
+int foo_get_functions_count(struct pinctrl_dev *pctldev)
 {
-	if (selector >= ARRAY_SIZE(foo_functions))
-		return -EINVAL;
-	return 0;
+	return ARRAY_SIZE(foo_functions);
 }
 
 const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
@@ -703,7 +696,7 @@ void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 struct pinmux_ops foo_pmxops = {
-	.list_functions = foo_list_funcs,
+	.get_functions_count = foo_get_functions_count,
 	.get_function_name = foo_get_fname,
 	.get_function_groups = foo_get_groups,
 	.enable = foo_enable,
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index ec3b8cc18..5ed576a 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -318,9 +318,10 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
 			       const char *pin_group)
 {
 	const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
+	unsigned ngroups = pctlops->get_groups_count(pctldev);
 	unsigned group_selector = 0;
 
-	while (pctlops->list_groups(pctldev, group_selector) >= 0) {
+	while (group_selector < ngroups) {
 		const char *gname = pctlops->get_group_name(pctldev,
 							    group_selector);
 		if (!strcmp(gname, pin_group)) {
@@ -906,16 +907,18 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
 {
 	struct pinctrl_dev *pctldev = s->private;
 	const struct pinctrl_ops *ops = pctldev->desc->pctlops;
-	unsigned selector = 0;
+	unsigned ngroups, selector = 0;
 
 	/* No grouping */
 	if (!ops)
 		return 0;
 
+	ngroups = ops->get_groups_count(pctldev);
+
 	mutex_lock(&pinctrl_mutex);
 
 	seq_puts(s, "registered pin groups:\n");
-	while (ops->list_groups(pctldev, selector) >= 0) {
+	while (selector < ngroups) {
 		const unsigned *pins;
 		unsigned num_pins;
 		const char *gname = ops->get_group_name(pctldev, selector);
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 7321e86..eb3a14f4 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -495,6 +495,7 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
 	struct pinctrl_dev *pctldev = s->private;
 	const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
 	const struct pinconf_ops *ops = pctldev->desc->confops;
+	unsigned ngroups = pctlops->get_groups_count(pctldev);
 	unsigned selector = 0;
 
 	if (!ops || !ops->pin_config_group_get)
@@ -505,7 +506,7 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
 
 	mutex_lock(&pinctrl_mutex);
 
-	while (pctlops->list_groups(pctldev, selector) >= 0) {
+	while (selector < ngroups) {
 		const char *gname = pctlops->get_group_name(pctldev, selector);
 
 		seq_printf(s, "%u (%s):", selector, gname);
diff --git a/drivers/pinctrl/pinctrl-pxa3xx.c b/drivers/pinctrl/pinctrl-pxa3xx.c
index 079dce0..7644e42 100644
--- a/drivers/pinctrl/pinctrl-pxa3xx.c
+++ b/drivers/pinctrl/pinctrl-pxa3xx.c
@@ -25,20 +25,18 @@ static struct pinctrl_gpio_range pxa3xx_pinctrl_gpio_range = {
 	.pin_base	= 0,
 };
 
-static int pxa3xx_list_groups(struct pinctrl_dev *pctrldev, unsigned selector)
+static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev)
 {
 	struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-	if (selector >= info->num_grps)
-		return -EINVAL;
-	return 0;
+
+	return info->num_grps;
 }
 
 static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev,
 					 unsigned selector)
 {
 	struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-	if (selector >= info->num_grps)
-		return NULL;
+
 	return info->grps[selector].name;
 }
 
@@ -48,25 +46,23 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
 				 unsigned *num_pins)
 {
 	struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-	if (selector >= info->num_grps)
-		return -EINVAL;
+
 	*pins = info->grps[selector].pins;
 	*num_pins = info->grps[selector].npins;
 	return 0;
 }
 
 static struct pinctrl_ops pxa3xx_pctrl_ops = {
-	.list_groups	= pxa3xx_list_groups,
+	.get_groups_count = pxa3xx_get_groups_count,
 	.get_group_name	= pxa3xx_get_group_name,
 	.get_group_pins	= pxa3xx_get_group_pins,
 };
 
-static int pxa3xx_pmx_list_func(struct pinctrl_dev *pctrldev, unsigned func)
+static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev)
 {
 	struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-	if (func >= info->num_funcs)
-		return -EINVAL;
-	return 0;
+
+	return info->num_funcs;
 }
 
 static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev,
@@ -170,7 +166,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
 }
 
 static struct pinmux_ops pxa3xx_pmx_ops = {
-	.list_functions		= pxa3xx_pmx_list_func,
+	.get_functions_count	= pxa3xx_pmx_get_funcs_count,
 	.get_function_name	= pxa3xx_pmx_get_func_name,
 	.get_function_groups	= pxa3xx_pmx_get_groups,
 	.enable			= pxa3xx_pmx_enable,
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 6b3534c..ba15b1a 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -853,18 +853,14 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
 	SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
 };
 
-static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
 {
-	if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-		return -EINVAL;
-	return 0;
+	return ARRAY_SIZE(sirfsoc_pin_groups);
 }
 
 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
 				       unsigned selector)
 {
-	if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-		return NULL;
 	return sirfsoc_pin_groups[selector].name;
 }
 
@@ -872,8 +868,6 @@ static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector
 			       const unsigned **pins,
 			       unsigned *num_pins)
 {
-	if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-		return -EINVAL;
 	*pins = sirfsoc_pin_groups[selector].pins;
 	*num_pins = sirfsoc_pin_groups[selector].num_pins;
 	return 0;
@@ -886,7 +880,7 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
 }
 
 static struct pinctrl_ops sirfsoc_pctrl_ops = {
-	.list_groups = sirfsoc_list_groups,
+	.get_groups_count = sirfsoc_get_groups_count,
 	.get_group_name = sirfsoc_get_group_name,
 	.get_group_pins = sirfsoc_get_group_pins,
 	.pin_dbg_show = sirfsoc_pin_dbg_show,
@@ -1033,11 +1027,9 @@ static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector
 	sirfsoc_pinmux_endisable(spmx, selector, false);
 }
 
-static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector)
+static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
 {
-	if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions))
-		return -EINVAL;
-	return 0;
+	return ARRAY_SIZE(sirfsoc_pmx_functions);
 }
 
 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
@@ -1074,9 +1066,9 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
 }
 
 static struct pinmux_ops sirfsoc_pinmux_ops = {
-	.list_functions = sirfsoc_pinmux_list_funcs,
 	.enable = sirfsoc_pinmux_enable,
 	.disable = sirfsoc_pinmux_disable,
+	.get_functions_count = sirfsoc_pinmux_get_funcs_count,
 	.get_function_name = sirfsoc_pinmux_get_func_name,
 	.get_function_groups = sirfsoc_pinmux_get_groups,
 	.gpio_request_enable = sirfsoc_pinmux_request_gpio,
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 9b32968..774f7fd 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -53,15 +53,11 @@ static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
 	writel(val, pmx->regs[bank] + reg);
 }
 
-static int tegra_pinctrl_list_groups(struct pinctrl_dev *pctldev,
-				     unsigned group)
+static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 {
 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-	if (group >= pmx->soc->ngroups)
-		return -EINVAL;
-
-	return 0;
+	return pmx->soc->ngroups;
 }
 
 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
@@ -69,9 +65,6 @@ static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 {
 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-	if (group >= pmx->soc->ngroups)
-		return NULL;
-
 	return pmx->soc->groups[group].name;
 }
 
@@ -82,9 +75,6 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 {
 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-	if (group >= pmx->soc->ngroups)
-		return -EINVAL;
-
 	*pins = pmx->soc->groups[group].pins;
 	*num_pins = pmx->soc->groups[group].npins;
 
@@ -99,21 +89,17 @@ static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
 }
 
 static struct pinctrl_ops tegra_pinctrl_ops = {
-	.list_groups = tegra_pinctrl_list_groups,
+	.get_groups_count = tegra_pinctrl_get_groups_count,
 	.get_group_name = tegra_pinctrl_get_group_name,
 	.get_group_pins = tegra_pinctrl_get_group_pins,
 	.pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 };
 
-static int tegra_pinctrl_list_funcs(struct pinctrl_dev *pctldev,
-				    unsigned function)
+static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 {
 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-	if (function >= pmx->soc->nfunctions)
-		return -EINVAL;
-
-	return 0;
+	return pmx->soc->nfunctions;
 }
 
 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
@@ -121,9 +107,6 @@ static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 {
 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-	if (function >= pmx->soc->nfunctions)
-		return NULL;
-
 	return pmx->soc->functions[function].name;
 }
 
@@ -134,9 +117,6 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 {
 	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-	if (function >= pmx->soc->nfunctions)
-		return -EINVAL;
-
 	*groups = pmx->soc->functions[function].groups;
 	*num_groups = pmx->soc->functions[function].ngroups;
 
@@ -151,8 +131,6 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
 	int i;
 	u32 val;
 
-	if (group >= pmx->soc->ngroups)
-		return -EINVAL;
 	g = &pmx->soc->groups[group];
 
 	if (g->mux_reg < 0)
@@ -194,7 +172,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
 }
 
 static struct pinmux_ops tegra_pinmux_ops = {
-	.list_functions = tegra_pinctrl_list_funcs,
+	.get_functions_count = tegra_pinctrl_get_funcs_count,
 	.get_function_name = tegra_pinctrl_get_func_name,
 	.get_function_groups = tegra_pinctrl_get_func_groups,
 	.enable = tegra_pinctrl_enable,
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 26eb8cc..05d0299 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -836,18 +836,14 @@ static const struct u300_pin_group u300_pin_groups[] = {
 	},
 };
 
-static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int u300_get_groups_count(struct pinctrl_dev *pctldev)
 {
-	if (selector >= ARRAY_SIZE(u300_pin_groups))
-		return -EINVAL;
-	return 0;
+	return ARRAY_SIZE(u300_pin_groups);
 }
 
 static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
 				       unsigned selector)
 {
-	if (selector >= ARRAY_SIZE(u300_pin_groups))
-		return NULL;
 	return u300_pin_groups[selector].name;
 }
 
@@ -855,8 +851,6 @@ static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 			       const unsigned **pins,
 			       unsigned *num_pins)
 {
-	if (selector >= ARRAY_SIZE(u300_pin_groups))
-		return -EINVAL;
 	*pins = u300_pin_groups[selector].pins;
 	*num_pins = u300_pin_groups[selector].num_pins;
 	return 0;
@@ -869,7 +863,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 }
 
 static struct pinctrl_ops u300_pctrl_ops = {
-	.list_groups = u300_list_groups,
+	.get_groups_count = u300_get_groups_count,
 	.get_group_name = u300_get_group_name,
 	.get_group_pins = u300_get_group_pins,
 	.pin_dbg_show = u300_pin_dbg_show,
@@ -991,11 +985,9 @@ static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
 	u300_pmx_endisable(upmx, selector, false);
 }
 
-static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
+static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 {
-	if (selector >= ARRAY_SIZE(u300_pmx_functions))
-		return -EINVAL;
-	return 0;
+	return ARRAY_SIZE(u300_pmx_functions);
 }
 
 static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
@@ -1014,7 +1006,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinmux_ops u300_pmx_ops = {
-	.list_functions = u300_pmx_list_funcs,
+	.get_functions_count = u300_pmx_get_funcs_count,
 	.get_function_name = u300_pmx_get_func_name,
 	.get_function_groups = u300_pmx_get_groups,
 	.enable = u300_pmx_enable,
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 4e62783..375b214 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -33,10 +33,11 @@
 int pinmux_check_ops(struct pinctrl_dev *pctldev)
 {
 	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned nfuncs = ops->get_functions_count(pctldev);
 	unsigned selector = 0;
 
 	/* Check that we implement required operations */
-	if (!ops->list_functions ||
+	if (!ops->get_functions_count ||
 	    !ops->get_function_name ||
 	    !ops->get_function_groups ||
 	    !ops->enable ||
@@ -44,7 +45,7 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev)
 		return -EINVAL;
 
 	/* Check that all functions registered have names */
-	while (ops->list_functions(pctldev, selector) >= 0) {
+	while (selector < nfuncs) {
 		const char *fname = ops->get_function_name(pctldev,
 							   selector);
 		if (!fname) {
@@ -287,10 +288,11 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
 					const char *function)
 {
 	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned nfuncs = ops->get_functions_count(pctldev);
 	unsigned selector = 0;
 
 	/* See if this pctldev has this function */
-	while (ops->list_functions(pctldev, selector) >= 0) {
+	while (selector < nfuncs) {
 		const char *fname = ops->get_function_name(pctldev,
 							   selector);
 
@@ -477,11 +479,12 @@ static int pinmux_functions_show(struct seq_file *s, void *what)
 {
 	struct pinctrl_dev *pctldev = s->private;
 	const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
+	unsigned nfuncs = pmxops->get_functions_count(pctldev);
 	unsigned func_selector = 0;
 
 	mutex_lock(&pinctrl_mutex);
 
-	while (pmxops->list_functions(pctldev, func_selector) >= 0) {
+	while (func_selector < nfuncs) {
 		const char *func = pmxops->get_function_name(pctldev,
 							  func_selector);
 		const char * const *groups;
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 4e9f078..515fd99 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -64,9 +64,7 @@ struct pinctrl_gpio_range {
 /**
  * struct pinctrl_ops - global pin control operations, to be implemented by
  * pin controller drivers.
- * @list_groups: list the number of selectable named groups available
- *	in this pinmux driver, the core will begin on 0 and call this
- *	repeatedly as long as it returns >= 0 to enumerate the groups
+ * @get_groups_count: Returns the count of total number of groups registered.
  * @get_group_name: return the group name of the pin group
  * @get_group_pins: return an array of pins corresponding to a certain
  *	group selector @pins, and the size of the array in @num_pins
@@ -74,7 +72,7 @@ struct pinctrl_gpio_range {
  *	info for a certain pin in debugfs
  */
 struct pinctrl_ops {
-	int (*list_groups) (struct pinctrl_dev *pctldev, unsigned selector);
+	int (*get_groups_count) (struct pinctrl_dev *pctldev);
 	const char *(*get_group_name) (struct pinctrl_dev *pctldev,
 				       unsigned selector);
 	int (*get_group_pins) (struct pinctrl_dev *pctldev,
diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h
index 47e9237..dd7bef6 100644
--- a/include/linux/pinctrl/pinmux.h
+++ b/include/linux/pinctrl/pinmux.h
@@ -29,9 +29,8 @@ struct pinctrl_dev;
  *	is allowed to answer "no" by returning a negative error code
  * @free: the reverse function of the request() callback, frees a pin after
  *	being requested
- * @list_functions: list the number of selectable named functions available
- *	in this pinmux driver, the core will begin on 0 and call this
- *	repeatedly as long as it returns >= 0 to enumerate mux settings
+ * @get_functions_count: returns number of selectable named functions available
+ *	in this pinmux driver
  * @get_function_name: return the function name of the muxing selector,
  *	called by the core to figure out which mux setting it shall map a
  *	certain device to
@@ -62,7 +61,7 @@ struct pinctrl_dev;
 struct pinmux_ops {
 	int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
 	int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
-	int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector);
+	int (*get_functions_count) (struct pinctrl_dev *pctldev);
 	const char *(*get_function_name) (struct pinctrl_dev *pctldev,
 					  unsigned selector);
 	int (*get_function_groups) (struct pinctrl_dev *pctldev,
-- 
1.7.9



From b29396 at freescale.com  Fri Mar 30 02:31:18 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Fri, 30 Mar 2012 14:31:18 +0800
Subject: [PATCH 1/1] ARM: imx28: add basic dt support
Message-ID: <1333089078-24724-1-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

This patch includes basic dt support which can boot via nfs rootfs.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog v2->v3:
 * Some minor fixes suggested by Shawn Guo
ChangeLog v1->v2:
 * Some fixes addressed Rob's review comments.
   Remove using of OF_DEV_AUXDATA.
 * Remove mac address from dts file
   Currently we use the mac address got from uboot to work.
   Will submit a p separate atch using prom_update_property to fix this
   issue for driver based on suggestions from Grant and Lothar.
 * rename mxs-dt.c to mach-mxs.c which is supposed to support mx23 dt
   too in the future.
 * add compatible string "fsl,imx28" per Sascha's suggestion
 * add more devices in dtsi file
   For those devices still not in use, set the state to "disabled"
   by default.
---
 Documentation/devicetree/bindings/arm/fsl.txt |    4 +
 arch/arm/boot/dts/imx28-evk.dts               |   34 +++
 arch/arm/boot/dts/imx28.dtsi                  |  356 +++++++++++++++++++++++++
 arch/arm/mach-mxs/Kconfig                     |   10 +
 arch/arm/mach-mxs/Makefile                    |    1 +
 arch/arm/mach-mxs/clock-mx28.c                |    4 +
 arch/arm/mach-mxs/devices/Kconfig             |    1 -
 arch/arm/mach-mxs/mach-mxs.c                  |   68 +++++
 8 files changed, 477 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx28-evk.dts
 create mode 100644 arch/arm/boot/dts/imx28.dtsi
 create mode 100644 arch/arm/mach-mxs/mach-mxs.c

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 54bddda..9f21faf 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -1,6 +1,10 @@
 Freescale i.MX Platforms Device Tree Bindings
 -----------------------------------------------
 
+i.MX28 Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx28-evk", "fsl,imx28";
+
 i.MX51 Babbage Board
 Required root node properties:
     - compatible = "fsl,imx51-babbage", "fsl,imx51";
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
new file mode 100644
index 0000000..57703ec
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+	model = "Freescale i.MX28 Evaluation Kit";
+	compatible = "fsl,imx28-evk", "fsl,imx28";
+
+	memory {
+		reg = <0x40000000 0x08000000>;
+	};
+
+	ahb at 80080000 {
+		ethernet at 800f0000 {
+			phy-mode = "rmii";
+			status = "okay";
+		};
+
+		ethernet at 800f4000 {
+			phy-mode = "rmii";
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
new file mode 100644
index 0000000..d1f4f8c
--- /dev/null
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&icoll>;
+
+	aliases {
+		serial0 = &duart;
+	};
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	apb at 80000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80000000 0x80000>;
+		ranges;
+
+		apbh at 80000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x80000000 0x3c900>;
+			ranges;
+
+			icoll: interrupt-controller at 80000000 {
+				compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x80000000 0x2000>;
+			};
+
+			hsadc at 80002000 {
+				reg = <0x80002000 2000>;
+				interrupts = <13 87>;
+				status = "disabled";
+			};
+
+			dma-apbh at 80004000 {
+				reg = <0x80004000 2000>;
+				status = "disabled";
+			};
+
+			perfmon at 80006000 {
+				reg = <0x80006000 800>;
+				interrupts = <27>;
+				status = "disabled";
+			};
+
+			bch at 8000a000 {
+				reg = <0x8000a000 2000>;
+				interrupts = <41>;
+				status = "disabled";
+			};
+
+			gpmi at 8000c000 {
+				reg = <0x8000c000 2000>;
+				interrupts = <42 88>;
+				status = "disabled";
+			};
+
+			ssp at 80010000 {
+				reg = <0x80010000 2000>;
+				interrupts = <96 82>;
+				status = "disabled";
+			};
+
+			ssp at 80012000 {
+				reg = <0x80012000 2000>;
+				interrupts = <97 83>;
+				status = "disabled";
+			};
+
+			ssp at 80014000 {
+				reg = <0x80014000 2000>;
+				interrupts = <98 84>;
+				status = "disabled";
+			};
+
+			ssp at 80016000 {
+				reg = <0x80016000 2000>;
+				interrupts = <99 85>;
+				status = "disabled";
+			};
+
+			pinctrl at 80018000 {
+				reg = <0x80018000 2000>;
+				status = "disabled";
+			};
+
+			digctl at 8001c000 {
+				reg = <0x8001c000 2000>;
+				interrupts = <89>;
+				status = "disabled";
+			};
+
+			etm at 80022000 {
+				reg = <0x80022000 2000>;
+				status = "disabled";
+			};
+
+			dma-apbx at 80024000 {
+				reg = <0x80024000 2000>;
+				status = "disabled";
+			};
+
+			dcp at 80028000 {
+				reg = <0x80028000 2000>;
+				interrupts = <52 53 54>;
+				status = "disabled";
+			};
+
+			pxp at 8002a000 {
+				reg = <0x8002a000 2000>;
+				interrupts = <39>;
+				status = "disabled";
+			};
+
+			ocotp at 8002c000 {
+				reg = <0x8002c000 2000>;
+				status = "disabled";
+			};
+
+			axi-ahb at 8002e000 {
+				reg = <0x8002e000 2000>;
+				status = "disabled";
+			};
+
+			lcdif at 80030000 {
+				reg = <0x80030000 2000>;
+				interrupts = <38 86>;
+				status = "disabled";
+			};
+
+			can at 80032000 {
+				reg = <0x80032000 2000>;
+				interrupts = <8>;
+				status = "disabled";
+			};
+
+			can at 80034000 {
+				reg = <0x80034000 2000>;
+				interrupts = <9>;
+				status = "disabled";
+			};
+
+			simdbg at 8003c000 {
+				reg = <0x8003c000 200>;
+				status = "disabled";
+			};
+
+			simgpmisel at 8003c200 {
+				reg = <0x8003c200 100>;
+				status = "disabled";
+			};
+
+			simsspsel at 8003c300 {
+				reg = <0x8003c300 100>;
+				status = "disabled";
+			};
+
+			simmemsel at 8003c400 {
+				reg = <0x8003c400 100>;
+				status = "disabled";
+			};
+
+			gpiomon at 8003c500 {
+				reg = <0x8003c500 100>;
+				status = "disabled";
+			};
+
+			simenet at 8003c700 {
+				reg = <0x8003c700 100>;
+				status = "disabled";
+			};
+
+			armjtag at 8003c800 {
+				reg = <0x8003c800 100>;
+				status = "disabled";
+			};
+                };
+
+		apbx at 80040000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x80040000 0x40000>;
+			ranges;
+
+			clkctl at 80040000 {
+				reg = <0x80040000 2000>;
+				status = "disabled";
+			};
+
+			saif at 80042000 {
+				reg = <0x80042000 2000>;
+				interrupts = <59 80>;
+				status = "disabled";
+			};
+
+			power at 80044000 {
+				reg = <0x80044000 2000>;
+				status = "disabled";
+			};
+
+			saif at 80046000 {
+				reg = <0x80046000 2000>;
+				interrupts = <58 81>;
+				status = "disabled";
+			};
+
+			lradc at 80050000 {
+				reg = <0x80050000 2000>;
+				status = "disabled";
+			};
+
+			spdif at 80054000 {
+				reg = <0x80054000 2000>;
+				interrupts = <45 66>;
+				status = "disabled";
+			};
+
+			rtc at 80056000 {
+				reg = <0x80056000 2000>;
+				interrupts = <28 29>;
+				status = "disabled";
+			};
+
+			i2c at 80058000 {
+				reg = <0x80058000 2000>;
+				interrupts = <111 68>;
+				status = "disabled";
+			};
+
+			i2c at 8005a000 {
+				reg = <0x8005a000 2000>;
+				interrupts = <110 69>;
+				status = "disabled";
+			};
+
+			pwm at 80064000 {
+				reg = <0x80064000 2000>;
+				status = "disabled";
+			};
+
+			timrot at 80068000 {
+				reg = <0x80068000 2000>;
+				status = "disabled";
+			};
+
+			serial at 8006a000 {
+				reg = <0x8006a000 0x2000>;
+				interrupts = <112 70 71>;
+				status = "disabled";
+			};
+
+			serial at 8006c000 {
+				reg = <0x8006c000 0x2000>;
+				interrupts = <113 72 73>;
+				status = "disabled";
+			};
+
+			serial at 8006e000 {
+				reg = <0x8006e000 0x2000>;
+				interrupts = <114 74 75>;
+				status = "disabled";
+			};
+
+			serial at 80070000 {
+				reg = <0x80070000 0x2000>;
+				interrupts = <115 76 77>;
+				status = "disabled";
+			};
+
+			serial at 80072000 {
+				reg = <0x80072000 0x2000>;
+				interrupts = <116 78 79>;
+				status = "disabled";
+			};
+
+			duart: serial at 80074000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x80074000 0x1000>;
+				interrupts = <47>;
+			};
+
+			usbphy at 8007c000 {
+				reg = <0x8007c000 0x2000>;
+				status = "disabled";
+			};
+
+			usbphy at 8007e000 {
+				reg = <0x8007e000 0x2000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	ahb at 80080000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80080000 0x80000>;
+		ranges;
+
+		usbctrl at 80080000 {
+			reg = <0x80080000 0x10000>;
+			status = "disabled";
+		};
+
+		usbctrl at 80090000 {
+			reg = <0x80090000 0x10000>;
+			status = "disabled";
+		};
+
+		dflpt at 800c0000 {
+			reg = <0x800c0000 0x10000>;
+			status = "disabled";
+		};
+
+		ethernet at 800f0000 {
+			compatible = "fsl,imx28-fec";
+			reg = <0x800f0000 0x4000>;
+			interrupts = <101>;
+			status = "disabled";
+		};
+
+		ethernet at 800f4000 {
+			compatible = "fsl,imx28-fec";
+			reg = <0x800f4000 0x4000>;
+			interrupts = <102>;
+			status = "disabled";
+		};
+
+		switch at 800f8000 {
+			reg = <0x800f8000 0x8000>;
+			status = "disabled";
+		};
+
+	};
+};
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c57f996..09fe0fb 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -7,16 +7,26 @@ config MXS_OCOTP
 
 config SOC_IMX23
 	bool
+	select ARM_AMBA
 	select CPU_ARM926T
 	select HAVE_PWM
 
 config SOC_IMX28
 	bool
+	select ARM_AMBA
 	select CPU_ARM926T
 	select HAVE_PWM
 
 comment "MXS platforms:"
 
+config MACH_MXS_DT
+	bool "Support MXS platforms from device tree"
+	select SOC_IMX28
+	select USE_OF
+	help
+	  Include support for Freescale MXS platforms(i.MX23 and i.MX28)
+	  using the device tree for discovery
+
 config MACH_STMP378X_DEVB
 	bool "Support STMP378x_devb Platform"
 	select SOC_IMX23
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 908bf9a..8328c45 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
 obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
 obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
 
+obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
 obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5d68e41..88ed30c 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -671,6 +671,10 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
 	_REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
 	_REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
+	/* for DT */
+	_REGISTER_CLOCK("80074000.serial", NULL, uart_clk)
+	_REGISTER_CLOCK("800f0000.ethernet", NULL, fec_clk)
+	_REGISTER_CLOCK("800f4000.ethernet", NULL, fec_clk)
 };
 
 static int clk_misc_init(void)
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index 18b6bf5..2febd62 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -1,6 +1,5 @@
 config MXS_HAVE_AMBA_DUART
 	bool
-	select ARM_AMBA
 
 config MXS_HAVE_PLATFORM_AUART
 	bool
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
new file mode 100644
index 0000000..b2b6c37
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+
+static int __init mxs_icoll_add_irq_domain(struct device_node *np,
+				struct device_node *interrupt_parent)
+{
+	irq_domain_add_simple(np, 0);
+
+	return 0;
+}
+
+static const struct of_device_id mxs_irq_match[] __initconst = {
+	{ .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
+	{ /* sentinel */ }
+};
+
+static void __init mxs_dt_init_irq(void)
+{
+	icoll_init_irq();
+	of_irq_init(mxs_irq_match);
+}
+
+static void __init imx28_timer_init(void)
+{
+	mx28_clocks_init();
+}
+
+static struct sys_timer imx28_timer = {
+	.init = imx28_timer_init,
+};
+
+static void __init mxs_machine_init(void)
+{
+       of_platform_populate(NULL, of_default_bus_match_table,
+				NULL, NULL);
+}
+
+static const char *imx28_dt_compat[] __initdata = {
+	"fsl,imx28-evk",
+	"fsl,imx28",
+	NULL,
+};
+
+DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
+	.map_io		= mx28_map_io,
+	.init_irq	= mxs_dt_init_irq,
+	.timer		= &imx28_timer,
+	.init_machine	= mxs_machine_init,
+	.dt_compat	= imx28_dt_compat,
+	.restart	= mxs_restart,
+MACHINE_END
-- 
1.7.0.4




From b29396 at freescale.com  Fri Mar 30 02:32:10 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Fri, 30 Mar 2012 14:32:10 +0800
Subject: [PATCH v3 1/1] ARM: imx28: add basic dt support
Message-ID: <1333089130-24832-1-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

This patch includes basic dt support which can boot via nfs rootfs.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog v2->v3:
 * Some minor fixes suggested by Shawn Guo
ChangeLog v1->v2:
 * Some fixes addressed Rob's review comments.
   Remove using of OF_DEV_AUXDATA.
 * Remove mac address from dts file
   Currently we use the mac address got from uboot to work.
   Will submit a p separate atch using prom_update_property to fix this
   issue for driver based on suggestions from Grant and Lothar.
 * rename mxs-dt.c to mach-mxs.c which is supposed to support mx23 dt
   too in the future.
 * add compatible string "fsl,imx28" per Sascha's suggestion
 * add more devices in dtsi file
   For those devices still not in use, set the state to "disabled"
   by default.
---
 Documentation/devicetree/bindings/arm/fsl.txt |    4 +
 arch/arm/boot/dts/imx28-evk.dts               |   34 +++
 arch/arm/boot/dts/imx28.dtsi                  |  356 +++++++++++++++++++++++++
 arch/arm/mach-mxs/Kconfig                     |   10 +
 arch/arm/mach-mxs/Makefile                    |    1 +
 arch/arm/mach-mxs/clock-mx28.c                |    4 +
 arch/arm/mach-mxs/devices/Kconfig             |    1 -
 arch/arm/mach-mxs/mach-mxs.c                  |   68 +++++
 8 files changed, 477 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx28-evk.dts
 create mode 100644 arch/arm/boot/dts/imx28.dtsi
 create mode 100644 arch/arm/mach-mxs/mach-mxs.c

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 54bddda..9f21faf 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -1,6 +1,10 @@
 Freescale i.MX Platforms Device Tree Bindings
 -----------------------------------------------
 
+i.MX28 Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx28-evk", "fsl,imx28";
+
 i.MX51 Babbage Board
 Required root node properties:
     - compatible = "fsl,imx51-babbage", "fsl,imx51";
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
new file mode 100644
index 0000000..57703ec
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+	model = "Freescale i.MX28 Evaluation Kit";
+	compatible = "fsl,imx28-evk", "fsl,imx28";
+
+	memory {
+		reg = <0x40000000 0x08000000>;
+	};
+
+	ahb at 80080000 {
+		ethernet at 800f0000 {
+			phy-mode = "rmii";
+			status = "okay";
+		};
+
+		ethernet at 800f4000 {
+			phy-mode = "rmii";
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
new file mode 100644
index 0000000..d1f4f8c
--- /dev/null
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&icoll>;
+
+	aliases {
+		serial0 = &duart;
+	};
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	apb at 80000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80000000 0x80000>;
+		ranges;
+
+		apbh at 80000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x80000000 0x3c900>;
+			ranges;
+
+			icoll: interrupt-controller at 80000000 {
+				compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x80000000 0x2000>;
+			};
+
+			hsadc at 80002000 {
+				reg = <0x80002000 2000>;
+				interrupts = <13 87>;
+				status = "disabled";
+			};
+
+			dma-apbh at 80004000 {
+				reg = <0x80004000 2000>;
+				status = "disabled";
+			};
+
+			perfmon at 80006000 {
+				reg = <0x80006000 800>;
+				interrupts = <27>;
+				status = "disabled";
+			};
+
+			bch at 8000a000 {
+				reg = <0x8000a000 2000>;
+				interrupts = <41>;
+				status = "disabled";
+			};
+
+			gpmi at 8000c000 {
+				reg = <0x8000c000 2000>;
+				interrupts = <42 88>;
+				status = "disabled";
+			};
+
+			ssp at 80010000 {
+				reg = <0x80010000 2000>;
+				interrupts = <96 82>;
+				status = "disabled";
+			};
+
+			ssp at 80012000 {
+				reg = <0x80012000 2000>;
+				interrupts = <97 83>;
+				status = "disabled";
+			};
+
+			ssp at 80014000 {
+				reg = <0x80014000 2000>;
+				interrupts = <98 84>;
+				status = "disabled";
+			};
+
+			ssp at 80016000 {
+				reg = <0x80016000 2000>;
+				interrupts = <99 85>;
+				status = "disabled";
+			};
+
+			pinctrl at 80018000 {
+				reg = <0x80018000 2000>;
+				status = "disabled";
+			};
+
+			digctl at 8001c000 {
+				reg = <0x8001c000 2000>;
+				interrupts = <89>;
+				status = "disabled";
+			};
+
+			etm at 80022000 {
+				reg = <0x80022000 2000>;
+				status = "disabled";
+			};
+
+			dma-apbx at 80024000 {
+				reg = <0x80024000 2000>;
+				status = "disabled";
+			};
+
+			dcp at 80028000 {
+				reg = <0x80028000 2000>;
+				interrupts = <52 53 54>;
+				status = "disabled";
+			};
+
+			pxp at 8002a000 {
+				reg = <0x8002a000 2000>;
+				interrupts = <39>;
+				status = "disabled";
+			};
+
+			ocotp at 8002c000 {
+				reg = <0x8002c000 2000>;
+				status = "disabled";
+			};
+
+			axi-ahb at 8002e000 {
+				reg = <0x8002e000 2000>;
+				status = "disabled";
+			};
+
+			lcdif at 80030000 {
+				reg = <0x80030000 2000>;
+				interrupts = <38 86>;
+				status = "disabled";
+			};
+
+			can at 80032000 {
+				reg = <0x80032000 2000>;
+				interrupts = <8>;
+				status = "disabled";
+			};
+
+			can at 80034000 {
+				reg = <0x80034000 2000>;
+				interrupts = <9>;
+				status = "disabled";
+			};
+
+			simdbg at 8003c000 {
+				reg = <0x8003c000 200>;
+				status = "disabled";
+			};
+
+			simgpmisel at 8003c200 {
+				reg = <0x8003c200 100>;
+				status = "disabled";
+			};
+
+			simsspsel at 8003c300 {
+				reg = <0x8003c300 100>;
+				status = "disabled";
+			};
+
+			simmemsel at 8003c400 {
+				reg = <0x8003c400 100>;
+				status = "disabled";
+			};
+
+			gpiomon at 8003c500 {
+				reg = <0x8003c500 100>;
+				status = "disabled";
+			};
+
+			simenet at 8003c700 {
+				reg = <0x8003c700 100>;
+				status = "disabled";
+			};
+
+			armjtag at 8003c800 {
+				reg = <0x8003c800 100>;
+				status = "disabled";
+			};
+                };
+
+		apbx at 80040000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x80040000 0x40000>;
+			ranges;
+
+			clkctl at 80040000 {
+				reg = <0x80040000 2000>;
+				status = "disabled";
+			};
+
+			saif at 80042000 {
+				reg = <0x80042000 2000>;
+				interrupts = <59 80>;
+				status = "disabled";
+			};
+
+			power at 80044000 {
+				reg = <0x80044000 2000>;
+				status = "disabled";
+			};
+
+			saif at 80046000 {
+				reg = <0x80046000 2000>;
+				interrupts = <58 81>;
+				status = "disabled";
+			};
+
+			lradc at 80050000 {
+				reg = <0x80050000 2000>;
+				status = "disabled";
+			};
+
+			spdif at 80054000 {
+				reg = <0x80054000 2000>;
+				interrupts = <45 66>;
+				status = "disabled";
+			};
+
+			rtc at 80056000 {
+				reg = <0x80056000 2000>;
+				interrupts = <28 29>;
+				status = "disabled";
+			};
+
+			i2c at 80058000 {
+				reg = <0x80058000 2000>;
+				interrupts = <111 68>;
+				status = "disabled";
+			};
+
+			i2c at 8005a000 {
+				reg = <0x8005a000 2000>;
+				interrupts = <110 69>;
+				status = "disabled";
+			};
+
+			pwm at 80064000 {
+				reg = <0x80064000 2000>;
+				status = "disabled";
+			};
+
+			timrot at 80068000 {
+				reg = <0x80068000 2000>;
+				status = "disabled";
+			};
+
+			serial at 8006a000 {
+				reg = <0x8006a000 0x2000>;
+				interrupts = <112 70 71>;
+				status = "disabled";
+			};
+
+			serial at 8006c000 {
+				reg = <0x8006c000 0x2000>;
+				interrupts = <113 72 73>;
+				status = "disabled";
+			};
+
+			serial at 8006e000 {
+				reg = <0x8006e000 0x2000>;
+				interrupts = <114 74 75>;
+				status = "disabled";
+			};
+
+			serial at 80070000 {
+				reg = <0x80070000 0x2000>;
+				interrupts = <115 76 77>;
+				status = "disabled";
+			};
+
+			serial at 80072000 {
+				reg = <0x80072000 0x2000>;
+				interrupts = <116 78 79>;
+				status = "disabled";
+			};
+
+			duart: serial at 80074000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x80074000 0x1000>;
+				interrupts = <47>;
+			};
+
+			usbphy at 8007c000 {
+				reg = <0x8007c000 0x2000>;
+				status = "disabled";
+			};
+
+			usbphy at 8007e000 {
+				reg = <0x8007e000 0x2000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	ahb at 80080000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80080000 0x80000>;
+		ranges;
+
+		usbctrl at 80080000 {
+			reg = <0x80080000 0x10000>;
+			status = "disabled";
+		};
+
+		usbctrl at 80090000 {
+			reg = <0x80090000 0x10000>;
+			status = "disabled";
+		};
+
+		dflpt at 800c0000 {
+			reg = <0x800c0000 0x10000>;
+			status = "disabled";
+		};
+
+		ethernet at 800f0000 {
+			compatible = "fsl,imx28-fec";
+			reg = <0x800f0000 0x4000>;
+			interrupts = <101>;
+			status = "disabled";
+		};
+
+		ethernet at 800f4000 {
+			compatible = "fsl,imx28-fec";
+			reg = <0x800f4000 0x4000>;
+			interrupts = <102>;
+			status = "disabled";
+		};
+
+		switch at 800f8000 {
+			reg = <0x800f8000 0x8000>;
+			status = "disabled";
+		};
+
+	};
+};
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c57f996..09fe0fb 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -7,16 +7,26 @@ config MXS_OCOTP
 
 config SOC_IMX23
 	bool
+	select ARM_AMBA
 	select CPU_ARM926T
 	select HAVE_PWM
 
 config SOC_IMX28
 	bool
+	select ARM_AMBA
 	select CPU_ARM926T
 	select HAVE_PWM
 
 comment "MXS platforms:"
 
+config MACH_MXS_DT
+	bool "Support MXS platforms from device tree"
+	select SOC_IMX28
+	select USE_OF
+	help
+	  Include support for Freescale MXS platforms(i.MX23 and i.MX28)
+	  using the device tree for discovery
+
 config MACH_STMP378X_DEVB
 	bool "Support STMP378x_devb Platform"
 	select SOC_IMX23
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 908bf9a..8328c45 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
 obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
 obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
 
+obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
 obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5d68e41..88ed30c 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -671,6 +671,10 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
 	_REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
 	_REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
+	/* for DT */
+	_REGISTER_CLOCK("80074000.serial", NULL, uart_clk)
+	_REGISTER_CLOCK("800f0000.ethernet", NULL, fec_clk)
+	_REGISTER_CLOCK("800f4000.ethernet", NULL, fec_clk)
 };
 
 static int clk_misc_init(void)
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index 18b6bf5..2febd62 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -1,6 +1,5 @@
 config MXS_HAVE_AMBA_DUART
 	bool
-	select ARM_AMBA
 
 config MXS_HAVE_PLATFORM_AUART
 	bool
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
new file mode 100644
index 0000000..b2b6c37
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+
+static int __init mxs_icoll_add_irq_domain(struct device_node *np,
+				struct device_node *interrupt_parent)
+{
+	irq_domain_add_simple(np, 0);
+
+	return 0;
+}
+
+static const struct of_device_id mxs_irq_match[] __initconst = {
+	{ .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
+	{ /* sentinel */ }
+};
+
+static void __init mxs_dt_init_irq(void)
+{
+	icoll_init_irq();
+	of_irq_init(mxs_irq_match);
+}
+
+static void __init imx28_timer_init(void)
+{
+	mx28_clocks_init();
+}
+
+static struct sys_timer imx28_timer = {
+	.init = imx28_timer_init,
+};
+
+static void __init mxs_machine_init(void)
+{
+       of_platform_populate(NULL, of_default_bus_match_table,
+				NULL, NULL);
+}
+
+static const char *imx28_dt_compat[] __initdata = {
+	"fsl,imx28-evk",
+	"fsl,imx28",
+	NULL,
+};
+
+DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
+	.map_io		= mx28_map_io,
+	.init_irq	= mxs_dt_init_irq,
+	.timer		= &imx28_timer,
+	.init_machine	= mxs_machine_init,
+	.dt_compat	= imx28_dt_compat,
+	.restart	= mxs_restart,
+MACHINE_END
-- 
1.7.0.4




From shawn.guo at linaro.org  Fri Mar 30 02:24:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 30 Mar 2012 14:24:49 +0800
Subject: [PATCH] =?UTF-8?q?ARM:=20imx:=20fix=20=E2=80=98arm=5Fpm=5Fidle=E2=80?=
 =?UTF-8?q?=99=20undeclared=20error?=
Message-ID: <1333088689-16135-1-git-send-email-shawn.guo@linaro.org>

Add missing #include <asm/system_misc.h> to fix the following compile
error.

  CC      arch/arm/mach-imx/mm-imx5.o
arch/arm/mach-imx/mm-imx5.c: In function ?imx51_init_early?:
arch/arm/mach-imx/mm-imx5.c:105:2: error: ?arm_pm_idle? undeclared (first use in this function)
arch/arm/mach-imx/mm-imx5.c:105:2: note: each undeclared identifier is reported only once for each function it appears in

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/mm-imx3.c |    1 +
 arch/arm/mach-imx/mm-imx5.c |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index d534d7f..7412738 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -21,6 +21,7 @@
 #include <linux/err.h>
 
 #include <asm/pgtable.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 51af9fa..05250ae 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 
+#include <asm/system_misc.h>
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
-- 
1.7.5.4



From thierry.reding at avionic-design.de  Fri Mar 30 02:24:26 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 30 Mar 2012 08:24:26 +0200
Subject: [PATCH v5 05/16] pwm: Add device tree support
In-Reply-To: <20120329214717.GG4153@opensource.wolfsonmicro.com>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-6-git-send-email-thierry.reding@avionic-design.de>
 <20120329214717.GG4153@opensource.wolfsonmicro.com>
Message-ID: <20120330062426.GA13051@avionic-0098.mockup.avionic-design.de>

* Mark Brown wrote:
> On Wed, Mar 28, 2012 at 04:33:47PM +0200, Thierry Reding wrote:
> > +	pwm = pwm_request_from_chip(pc, args->args[0], NULL);
> > +	if (IS_ERR(pwm))
> > +		return ERR_PTR(-ENODEV);
> 
> It feels wrong to override the error code like this rather than passing
> the error we got back to the caller.  Is there any great reason for
> doing so?

Yes, this certainly looks wrong. I must have forgotten to fix this up when
of_pwm_simple_xlate() was converted to return a struct pwm_device instead of
an int. Previous to that pwm_request_from_chip() would return NULL and
-ENODEV seemed like the proper error code for that situation.

I'll change this to just return pwm.

Thanks,
Thierry
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From m.szyprowski at samsung.com  Fri Mar 30 02:30:06 2012
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 30 Mar 2012 08:30:06 +0200
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <401E54CE964CD94BAE1EB4A729C7087E37978A1E66@HQMAIL04.nvidia.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <20120329101927.8ab6b1993475b7e16ae2258f@nvidia.com>
 <01b301cd0d81$f935d750$eba185f0$%szyprowski@samsung.com>
 <401E54CE964CD94BAE1EB4A729C7087E37978A1E66@HQMAIL04.nvidia.com>
Message-ID: <000001cd0e3e$8ce21380$a6a63a80$%szyprowski@samsung.com>

Hello,

On Friday, March 30, 2012 4:24 AM Krishna Reddy wrote:

> Hi,
> I have found a bug in arm_iommu_map_sg().
> 
> > +int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
> > +		     enum dma_data_direction dir, struct dma_attrs *attrs) {
> > +	struct scatterlist *s = sg, *dma = sg, *start = sg;
> > +	int i, count = 0;
> > +	unsigned int offset = s->offset;
> > +	unsigned int size = s->offset + s->length;
> > +	unsigned int max = dma_get_max_seg_size(dev);
> > +
> > +	for (i = 1; i < nents; i++) {
> > +		s->dma_address = ARM_DMA_ERROR;
> > +		s->dma_length = 0;
> > +
> > +		s = sg_next(s);
> 
> With above code, the last sg element's dma_length is not getting set to zero.
> This causing additional incorrect  unmapping during arm_iommu_unmap_sg call and
> leading to random crashes.
> The order of above three lines should be as follows.
> 		s = sg_next(s);
> 
> 		s->dma_address = ARM_DMA_ERROR;
> 		s->dma_length = 0;
> 

You are right, the order of those lines must be reversed. In all my test codes the 
scatter list was initially cleared, so I missed this typical off-by-one error. 
Thanks for spotting it!

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center




From hvaibhav at ti.com  Fri Mar 30 02:34:17 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 30 Mar 2012 06:34:17 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>

On Wed, Mar 28, 2012 at 20:19:07, Shilimkar, Santosh wrote:
> On Wed, Mar 28, 2012 at 8:07 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> > On Wed, Mar 28, 2012 at 19:50:02, Shilimkar, Santosh wrote:
> >> On Wed, Mar 28, 2012 at 7:46 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >> > On Wed, Mar 21, 2012 at 19:30:01, Shilimkar, Santosh wrote:
> >> >> On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >> >> > On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
> >> >> >> On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
> >> >> >> > On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >>
> >> [...]
> >>
> >> >
> >> >> Btw, if you need PM, how are you going to use GPTIMER
> >> >> as a clocksource. Note sys-clock is generally stopped in
> >> >> low power states. So that leaves you option with using
> >> >> gptimer with 32K clock and in that case, GPTIMER
> >> >> is not a better clock-source compare to 32K sync timer
> >> >> and so shouldn't be the rating.
> >> >>
> >> >
> >> > AM33xx has GPTIMER1 in wakeup domain, so that we are already using as a
> >> > Clocksource, without any issues.
> >> >
> >> GPTIMER1 is in wakeup domain on OMAP too but that doesn't
> >> solve the issue I am talking. Once the sysclock is stopped, GPTIMER
> >> can't tick anymore even if it is in wakeup domain.
> >>
> >> The only way it will work is using always running 32KHz clock as
> >> the clock input to GPT1. And then the end result is the accuracy
> >> of GPTIMER = sync 32K timer. So they are of same rating.
> >>
> >
> > Ohh ok, sorry I should have clarified it in my last response itself.
> >
> np.
> 
> > AM33xx architecture is bit different than OMAP family, and gmtimer1 is
> > sourced from RTC32K clock, which is in wakeup domain.
> > This means we have RTC32K clock always running across suspend/resume.
> >
> > 0 - SEL1: Select CLK_M_OSC clock
> > 1 - SEL2: Select CLK_32KHZ clock
> > 2 - SEL3: Select TCLKIN clock
> > 3 - SEL4: Select CLK_RC32K clock
> > 4 - SEL5: Selects the CLK_32768 from 32KHz Crystal Osc
> >
> >
> > We use value "4" here, for RTC32K (always on clock).
> > I hope this clarifies what I am trying to say here.
> >
> I thought so and now if you look at last part of my comment.
> 
> Rating of 32K based synctimer and 32K based GPTIMER
> should be same because of the precision. That's the main
> point why I was saying that GPTIMER is not a better
> clock-source( with 32k clock src)  than sync timer when
> both are enabled together.
> 

Santosh,

In case of OMAP, we are using timer 2 for clocksource

OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)

And timer2 as clocksource is never used, since we have CONFIG_OMAP_32K_TIMER 
defined in our defconfig.

Also, after looking at the code, I came across another problem, setup_sched_clock(). But this can be easily fixed, if we source both the timers with same clock (here 32k_fck).


Let me propose this,

How about, if I keep timer2 source always set to 32k_fclk for omap2,3,4?
And also, as mentioned by Santosh, I will register both the clocks as 
clocksource with the same rating.
By default, kernel is going to use 32k_counter as a clocksource, and through 
Command prompt user can override it without any issues.

Just to make sure that, whatever I am trying to propse here works and don't get into unknown issue; I changed my code for this, and it is working for me without any issues.

Also, this way I can completely get rid of option CONFIG_OMAP_32K_TIMER_HZ.




diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 6b12372..ded78b7 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -45,6 +45,7 @@
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
+#include <plat/clock.h>
 
 #include "powerdomain.h"
 
@@ -57,18 +58,18 @@
 #define OMAP3_32K_SOURCE	"omap_32k_fck"
 #define OMAP4_32K_SOURCE	"sys_32k_ck"
 
-#ifdef CONFIG_OMAP_32K_TIMER
+//#ifdef CONFIG_OMAP_32K_TIMER
 #define OMAP2_CLKEV_SOURCE	OMAP2_32K_SOURCE
 #define OMAP3_CLKEV_SOURCE	OMAP3_32K_SOURCE
 #define OMAP4_CLKEV_SOURCE	OMAP4_32K_SOURCE
 #define OMAP3_SECURE_TIMER	12
-#else
+/*#else
 #define OMAP2_CLKEV_SOURCE	OMAP2_MPU_SOURCE
 #define OMAP3_CLKEV_SOURCE	OMAP3_MPU_SOURCE
 #define OMAP4_CLKEV_SOURCE	OMAP4_MPU_SOURCE
 #define OMAP3_SECURE_TIMER	1
 #endif
-
+*/
 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
 #define MAX_GPTIMER_ID		12
 
@@ -244,6 +245,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
 
 /* Clocksource code */
 static struct omap_dm_timer clksrc;
+static bool is_dmtimer_clocksource;
 
 /*
  * clocksource
@@ -253,20 +255,38 @@ static cycle_t clocksource_read_cycles(struct clocksource *cs)
 	return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
 }
 
+static int clocksource_enable(struct clocksource *cs)
+{
+	__omap_dm_timer_load_start(&clksrc,
+			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
+			omap_32k_read_sched_clock(), 1);
+
+	is_dmtimer_clocksource = true;
+	return 0;
+}
+
+static void clocksource_disable(struct clocksource *cs)
+{
+	__omap_dm_timer_stop(&clksrc, 1, clksrc.rate);
+	is_dmtimer_clocksource = false;
+}
+
 static struct clocksource clocksource_gpt = {
 	.name		= "gp timer",
-	.rating		= 300,
+	.rating		= 250,
 	.read		= clocksource_read_cycles,
+	.enable		= clocksource_enable,
+	.disable	= clocksource_disable,
 	.mask		= CLOCKSOURCE_MASK(32),
 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static u32 notrace dmtimer_read_sched_clock(void)
+static u32 notrace read_sched_clock(void)
 {
-	if (clksrc.reserved)
+	if (is_dmtimer_clocksource && clksrc.reserved)
 		return __omap_dm_timer_read_counter(&clksrc, 1);
-
-	return 0;
+	else
+		return omap_32k_read_sched_clock();
 }
 
 /* Setup free-running counter for clocksource */
@@ -282,8 +302,8 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
 	 * execution will fallback to gp-timer.
 	 */
 	res = omap_init_clocksource_32k();
-	if (!res)
-		return;
+	if (res)
+		pr_err("failed to init 32k_counter as a clocksource %d\n", res);
 
 	/* Fall back to gp-timer code */
 	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
@@ -292,9 +312,9 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
 	pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
 		gptimer_id, clksrc.rate);
 
-	__omap_dm_timer_load_start(&clksrc,
-			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
-	setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
+//	__omap_dm_timer_load_start(&clksrc,
+//			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
+	setup_sched_clock(read_sched_clock, 32, clksrc.rate);
 
 	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 		pr_err("Could not register clocksource %s\n",
@@ -315,12 +335,12 @@ struct sys_timer omap##name##_timer = {					\
 };
 
 #ifdef CONFIG_ARCH_OMAP2
-OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
+OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP3_CLKEV_SOURCE)
 OMAP_SYS_TIMER(2)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
+OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_CLKEV_SOURCE)
 OMAP_SYS_TIMER(3)
 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 			2, OMAP3_MPU_SOURCE)
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 5a25de0..4d65c2f 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -37,7 +37,7 @@ static void __iomem *timer_32k_base;
 
 #define OMAP16XX_TIMER_32K_SYNCHRONIZED		0xfffbc410
 
-static u32 notrace omap_32k_read_sched_clock(void)
+u32 notrace omap_32k_read_sched_clock(void)
 {
 	return timer_32k_base ? __raw_readl(timer_32k_base) : 0;
 }
@@ -118,7 +118,7 @@ int __init omap_init_clocksource_32k(void)
 		printk(KERN_ERR "%s: can't register clocksource!\n",
 				"32k_counter");
 
-	setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
+//	setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
 
 	return 0;
 }
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index b4d7ec3..4afb19b 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -31,6 +31,7 @@
 #include <plat/omap_hwmod.h>
 
 extern int __init omap_init_clocksource_32k(void);
+extern u32 notrace omap_32k_read_sched_clock(void);
 
 extern void omap_reserve(void);
 extern int omap_dss_reset(struct omap_hwmod *);


Thanks,
Vaibhav



From viresh.kumar at st.com  Fri Mar 30 02:33:53 2012
From: viresh.kumar at st.com (Viresh Kumar)
Date: Fri, 30 Mar 2012 12:03:53 +0530
Subject: [PATCH v3 6/6] mmc: sdhci-s3c: Add device tree support
In-Reply-To: <201203271619.13320.arnd@arndb.de>
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>
 <1328032576-9269-7-git-send-email-thomas.abraham@linaro.org>
 <201203271619.13320.arnd@arndb.de>
Message-ID: <4F7553D1.4030008@st.com>

On 3/27/2012 9:49 PM, Arnd Bergmann wrote:
> These bindings came up in a discussion IRC today. I think it's rather bad that
> we can't agree on a common way to name the properties for mmc. We have
> bindings being proposed or already included from Anton, Stephen, Shawn,
> Rajendra, Viresh, Lee and Thomas. Almost all of them define GPIO pins
> for card detect and write protect, as well properties to define the bus
> width and high-speed modes, but we seem to have almost as many different
> definitions of these as we have drivers.
> 
> Can we please come up with a common binding for these?

Is there any progress on this? Sorry i wasn't following all mails.
How should i progress for sdhci-spear?

-- 
viresh


From hvaibhav at ti.com  Fri Mar 30 02:39:26 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 30 Mar 2012 06:39:26 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CACVXFVPTsFY7UJMH5jZa16V0KYEZB=o7WRYqVEYyNJw1tMq-yw@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>	<87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831823816@DBDE01.ent.ti.com>
 <CACVXFVPTsFY7UJMH5jZa16V0KYEZB=o7WRYqVEYyNJw1tMq-yw@mail.gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831840C67@DBDE01.ent.ti.com>

On Fri, Mar 23, 2012 at 13:50:25, Ming Lei wrote:
> On Wed, Mar 21, 2012 at 7:29 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> > On Mon, Mar 19, 2012 at 17:14:30, Ming Lei wrote:
> >> On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >> >
> >> > I think you made very good point here. With the above patch, we are almost missing the capability of registering dmtimer as a clocksource for OMAP.
> >> > It will always use 32k-counter, and never fall back to dmtimer.
> >> >
> >> > Then the only options we have here is,
> >> >
> >> > 1) Register both the timers, 32k-counter and dmtimer for clocksource; let
> >> > ? Kernel pick up best rating clocksource out of these two.
> >> >
> >> > ? In case of OMAP1/2/3/4, kernel will use dmtimer, since it has better
> >> > ? Rating. User can choose the 32k-counter clocksource via bootargs.
> >> >
> >> > ? Impact: without bootargs for clocksource selection, kernel will choose
> >> > ? ? dmtimer, impacting loss of time during suspend/resume.
> >> >
> >> >
> >> > 2) Let the current code be as is, means, the clocksource registration will
> >> > ? Happened based on "#ifdef CONFIG_OMAP_32K_TIMER" and this option
> >> > ? selection will be Controlled by Kconfig rules.
> >>
> >> How about the 3rd option?
> >>
> >> 3), take the way in your patch 1) at default, but will switch to
> >> register dmtimer
> >> directly and bypass 32k-counter if user need it via kernel parameter.
> >>
> >> As far as I can think of, the situations required for dmtimer are high-frequency
> >> perf sample and high precision trace points, so looks it is OK to take
> >> 32k-counter
> >> at default.
> >>
> > But if you register both the timers (dmtimer & 32ksync), then initially kernel will only pick up dmtimer, as this has better rating. And late in
> 
> Looks not so, I found that 32ksync is always selected as the default
> clocksource if both are registered.
> 

No. Kernel always chooses better-rated timer/counter for clocksource.
Please refer to the file 

"kernel/time/clocksource.c"

When you register any clocksource, the sequence is
	...
	clocksource_enqueue(cs);
	...
	clocksource_select();
	...

And clocksource_enqueue(), makes sure that the list of registered clocksource is always sorted by its rating. And clocksource_select()
Chooses best (first in the list) as a clocksource, unless you override
It using bootparams or sysfs.

Thanks,
Vaibhav

> > the boot sequence clocksource switch will happen, base on
> > kernel parameter (clocksource=).
> >
> > So logically dmtimer will be always used as a default here.
> 
> Not so at least on my Pandaboard.
> 
> 
> Thanks,
> -- 
> Ming Lei
> 



From hvaibhav at ti.com  Fri Mar 30 03:13:57 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 30 Mar 2012 07:13:57 +0000
Subject: [PATCH-V3 0/3] ARM: OMAP2+: Add powerdomain & PRM support for
 AM33XX device
In-Reply-To: <87limjl1xf.fsf@ti.com>
References: <1331809586-24652-1-git-send-email-hvaibhav@ti.com>
 <87limjl1xf.fsf@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831840CD6@DBDE01.ent.ti.com>

On Thu, Mar 29, 2012 at 23:33:40, Hilman, Kevin wrote:
> Hi Vaibhav,
> 
> Vaibhav Hiremath <hvaibhav at ti.com> writes:
> 
> > After going round-n-round on how to add support for AM33XX family
> > of device into kernel, especially for PRM and CM support, we have
> > decided to handle it separately; as AM33XX-PRCM module is different
> > than OMAP3 and OMAP4 architecture.
> >
> > The difference becomes very interesting/weird when it comes to
> > the consistency for register offsets in PRM address space and
> > bit-field offsets inside PRM registers,
> > So along with Powerdomain data and PRM api's required for AM33XX
> > device, this patch series adds,
> >
> >  - XXX_RSTST register offset to "struct omap_hwmod_omap4_prcm"
> >  - PWRSTCTRL & PWRSTST register offsets to "struct powerdomain"
> >  - Logicretstate and mem_on/ret/pwrst/retst mask to "struct powerdomain"
> >
> >
> > Testing: This patch series has been boot tested on AM37xEVM and AM335x
> >          based BeagleBone community board.
> >
> > THANKS TO PAUL HERE...for helping and concluding on this, soon I will
> > have similar patch for CM support, then clock-tree and hwmod will follow...
> >
> > Changes from V1 & V2:
> > 	- Rolled back to my original approach, where AM33xx device was
> > 	  handled separately (RFC version).
> 
> My apologies for causing the run around.  
> 
> This approach (without the prminst layer) is indeed a better approach.
> 
> Thanks for your patience (and persistence.)
> 
> I went to give this a test on my BeagleBone, but it doesn't apply to
> mainline.  What upstream commit is this supposed to apply onto.  

I and using, linux-omap/master and/or linux-omap/cleanup branches as a 
baseline for sending the patches.


> I tried it on v3.3, but patch 3 fails with a conflict in io.c.
> 

My bad. I did not include (or resend) voltage domain patch (had submitted 
last time itself). 
I will resend the all patch-series again including voltage domain addition 
patch. Just for reference, the series will follow the sequence -

voltagedomains 
powerdomains 
clockdomains
clock
hwmod


> Looking at your am335x-staging branch, it seems that it depends on
> previous changes to io.c made in:
> 
>         arm:omap:am33xx: Add AM335XEVM machine support
> 
> That patch appears to need an update for mainline as well.
>

Can you please clarify on this? I use v3.3 to check on this, and it is
Getting applied without any issues for me.

I believe you are using V5 version of this patch series, also you can pick this patch from (created to give pull request to Tony)
https://github.com/hvaibhav/am335x-linux/tree/am335x-baseport-for-tony


Log:
==============
commit 812e168a9584e180c12588ca2b0233e96461e997
Author: Afzal Mohammed <afzal at ti.com>
Date:   Tue Aug 9 14:29:41 2011 +0530

    arm:omap:am33xx: Add AM335XEVM machine support

    This patch adds minimal support for AM335X EVM.
    The approach taken here is to add AM335X EVM support
    to AM3517EVM, considering the fact that with device tree
    developement we will get rid of board-*.c.

    Signed-off-by: Afzal Mohammed <afzal at ti.com>
    Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
    [Changed ti816x_init_irq=>ti81xx_init_irq, due to recent acceptance of patches]
    Reviewed-by: Kevin Hilman <khilman at ti.com>

commit c16fa4f2ad19908a47c63d8fa436a1178438c7e7
Author: Linus Torvalds <torvalds at linux-foundation.org>
Date:   Sun Mar 18 16:15:34 2012 -0700

    Linux 3.3


 
> Kevin
> 



From hvaibhav at ti.com  Fri Mar 30 03:14:52 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 30 Mar 2012 07:14:52 +0000
Subject: [PATCH] ARM: OMAP: hwmod: Fix error handling in functions used
 OMAP4 onwards
In-Reply-To: <4F7479B5.5060401@ti.com>
References: <1332842311-12308-1-git-send-email-rnayak@ti.com>
 <79CD15C6BA57404B839C016229A409A83183E0CE@DBDE01.ent.ti.com>
 <4F73FD52.60209@ti.com>
 <79CD15C6BA57404B839C016229A409A83183FB9F@DBDE01.ent.ti.com>
 <4F7479B5.5060401@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831840CE9@DBDE01.ent.ti.com>

On Thu, Mar 29, 2012 at 20:33:17, Hunter, Jon wrote:
> Hi Viabhav,
> 
> On 3/29/2012 3:56, Hiremath, Vaibhav wrote:
> > On Thu, Mar 29, 2012 at 11:42:34, Nayak, Rajendra wrote:
> >> On Wednesday 28 March 2012 12:02 PM, Hiremath, Vaibhav wrote:
> >>> On Tue, Mar 27, 2012 at 15:28:31, Nayak, Rajendra wrote:
> >>>> Some functions like _omap4_disable_module() and _omap4_wait_target_disable()
> >>>> are (will be) used on all OMAPs OMAP4 and beyond which support module level
> >>>> control. Fix the error checks in these functions to return if called on
> >>>> any platform pre OMAP4 (i.e OMAP2 and OMAP3) instead of checking for
> >>>> !cpu_is_omap44xx(). This avoids having to update the error check with a
> >>>> '&&   !cpu_is_omap54xx()' when OMAP5 is introduced and possibly similar updates
> >>>> when further OMAP generations are added.
> >>>>
> >>>
> >>> Let me add some flavor here :)
> >>>
> >>> AM33xx, which has module level control, but falls under OMAP3 family of
> >>> devices. cpu_is_omap34xx() is true for AM33xx device and we have to add
> >>> check in all these functions. And I am sure we will have many of such
> >>> devices in the future.
> >>>
> >>> Can we use some flag based option here, instead of cpu_is_xxx() check?
> >>>
> >>
> >> The intent of this patch was to make the error handling uniform across
> >> all modules control functions in hwmod, and it atleast addresses one
> >> problem of having to update these checks every time a new OMAP gets
> >> added.
> >>
> >> The problem that you bring up with AM33xx is regardless of this patch
> >> (you would still need to go update every !cpu_is_omap44xx() check)
> >
> > Indeed, in any of cpu_is_xxx() check implementation, I have to add check
> > for cpu_is_am33xx().
> 
> I hope we can avoid adding more cpu_is_amXXXX. That should be a last resort.
> 

Yes, indeed; adding cpu_is_xxx check would be my last option.

Thanks,
Vaibhav

> Jon
> 



From subashrp at gmail.com  Fri Mar 30 03:14:47 2012
From: subashrp at gmail.com (Subash Patel)
Date: Fri, 30 Mar 2012 12:44:47 +0530
Subject: [PATCHv7 9/9] ARM: dma-mapping: add support for IOMMU mapper
In-Reply-To: <4F6B304E.5010402@gmail.com>
References: <1330527862-16234-1-git-send-email-m.szyprowski@samsung.com>
 <1330527862-16234-10-git-send-email-m.szyprowski@samsung.com>
 <CAHQjnOO5DLOj8Fw=ZriSnXg8W3k7y8Dnu--Peqe6JJX0xGMhoQ@mail.gmail.com>
 <4F688B2D.20808@gmail.com>
 <CAHQjnOMjSPDOymJe356AWnJszQv+X-QWrVrB7ahYDkXBr5HrQw@mail.gmail.com>
 <4F6B304E.5010402@gmail.com>
Message-ID: <4F755D67.5020802@gmail.com>

Hi KyongHo,

On 03/22/2012 07:29 PM, Subash Patel wrote:
> Hi KyongHo,
>
> On 03/21/2012 05:26 AM, KyongHo Cho wrote:
>> On Tue, Mar 20, 2012 at 10:50 PM, Subash Patel<subashrp at gmail.com> wrote:
>>> Sorry for digging this very late. But as part of integrating dma_map v7&
>>> sysmmu v12 on 3.3-rc5, I am facing below issue:
>>>
>>> a) By un-selecting IOMMU in menu config, I am able to allocate memory in
>>> vb2-dma-contig
>>>
>>> b) When I enable SYSMMU support for the IP's, I am receiving below
>>> fault:
>>>
>>> Unhandled fault: external abort on non-linefetch (0x818) at 0xb6f55000
>>>
>>> I think this has something to do with the access to the SYSMMU
>>> registers for
>>> writing the page table. Has anyone of you faced this issue while testing
>>> these(dma_map+iommu) patches on kernel mentioned above? This must be
>>> something related to recent changes, as I didn't have issues with these
>>> patches on 3.2 kernel.
>>>
>>
>> 0xb6f55000 is not an address of SYSMMU register if your kernel starts
>> at 0xc0000000.
>>
>> Can you tell me any detailed information or situation?
> I hate to say this, but I am not able to catch the fault location even
> with JTAG. Once the fault comes, the debugger looses all control over. I
> think now possible method is reproduction at your end :)

Thanks to you, Issue is now figured out. This was due to generic Power 
Domain code added recently. SYSMMU registers were not getting enabled 
due to this. I reverted the PD changes from the machine to architecture 
specific, and voila, SYSMMU is back into action using the 
dma-mapping-v7. I will have to see how the same would behave when the 
complete PD changes comes to mainline from maintainers for-next in future.

>>
>> Regards,
>>
>> KyongHo.
> Regards,
> Subash
Regards,
Subash


From santosh.shilimkar at ti.com  Fri Mar 30 03:41:35 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 30 Mar 2012 13:11:35 +0530
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
Message-ID: <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>

On Fri, Mar 30, 2012 at 12:04 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> On Wed, Mar 28, 2012 at 20:19:07, Shilimkar, Santosh wrote:
>> On Wed, Mar 28, 2012 at 8:07 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>> > On Wed, Mar 28, 2012 at 19:50:02, Shilimkar, Santosh wrote:
>> >> On Wed, Mar 28, 2012 at 7:46 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>> >> > On Wed, Mar 21, 2012 at 19:30:01, Shilimkar, Santosh wrote:
>> >> >> On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>> >> >> > On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
>> >> >> >> On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
>> >> >> >> > On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>> >>
[...]

>> I thought so and now if you look at last part of my comment.
>>
>> Rating of 32K based synctimer and 32K based GPTIMER
>> should be same because of the precision. That's the main
>> point why I was saying that GPTIMER is not a better
>> clock-source( with 32k clock src) ?than sync timer when
>> both are enabled together.
>>
>
> Santosh,
>
> In case of OMAP, we are using timer 2 for clocksource
>
> OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
> OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
>
> And timer2 as clocksource is never used, since we have CONFIG_OMAP_32K_TIMER
> defined in our defconfig.
>
> Also, after looking at the code, I came across another problem, setup_sched_clock(). But this can be easily fixed, if we source both the timers with same clock (here 32k_fck).
>
>
> Let me propose this,
>
> How about, if I keep timer2 source always set to 32k_fclk for omap2,3,4?
> And also, as mentioned by Santosh, I will register both the clocks as
> clocksource with the same rating.
> By default, kernel is going to use 32k_counter as a clocksource, and through
> Command prompt user can override it without any issues.
>
> Just to make sure that, whatever I am trying to propse here works and don't get into unknown issue; I changed my code for this, and it is working for me without any issues.

Let's not make this more complicated. I guess below simple patch should sort
out the issue. I briefly tested it on OMAP4 and it works. let me know
if it helps AMxxx machines.

Regards
Santosh

>From 0a9283e26174d76ff2753ac88521b61a26b24e8f Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar <santosh.shilimkar at ti.com>
Date: Fri, 30 Mar 2012 12:43:29 +0530
Subject: [PATCH] ARM: OMAP: Make OMAP clocksource source selection runtime.

Current OMAP code support couple of clocksource options based on compilation
flag. The 32KHz based sync timer and a gptimer based clock source which can
run on 32KHz or system clock (e.g 38.4 MHz). So there can be 3 options.

1. 32KHz synctimer
2. Sysclock based(e.g 38.4 MHz) gptimer
3. 32KHz based gptimer.

The optional gptimer based clocksource was added so that it can give the
high precision than synctimer so expected usage was 2 and not 3. Unfortunatlly
option 2, clocksource doesn't meet the requirement of free-running clock
as per clocksource need. It stops in low power states when  sysclock is cut.
That makes gptimer based clocksource option useless for OMAP2/3/4 devices
with sysclock as a clock input. Option 3 will still work but it is no better'
than 32K synctimer based clocksource.

So ideally we can kill the gptimer based clocksource option but there are some
OMAP based derivative SoCs like AMXXXX which doesn't have synictimer hardware IP
and need to fallback on 32KHz based gptimer clocksource.

Considering above, make synctimer and gptimer clocksource runtime
selectable so that both OMAP and AMXXXX continue to use the same code.

Not-yet-signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/timer.c |   25 ++++++++-----------------
 1 files changed, 8 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index c512bac..3878e59 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -234,21 +234,6 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
 }

 /* Clocksource code */
-
-#ifdef CONFIG_OMAP_32K_TIMER
-/*
- * When 32k-timer is enabled, don't use GPTimer for clocksource
- * instead, just leave default clocksource which uses the 32k
- * sync counter.  See clocksource setup in plat-omap/counter_32k.c
- */
-
-static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
-{
-	omap_init_clocksource_32k();
-}
-
-#else
-
 static struct omap_dm_timer clksrc;

 /*
@@ -276,7 +261,7 @@ static u32 notrace dmtimer_read_sched_clock(void)
 }

 /* Setup free-running counter for clocksource */
-static void __init omap2_gp_clocksource_init(int gptimer_id,
+static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 						const char *fck_source)
 {
 	int res;
@@ -295,7 +280,13 @@ static void __init omap2_gp_clocksource_init(int
gptimer_id,
 		pr_err("Could not register clocksource %s\n",
 			clocksource_gpt.name);
 }
-#endif
+
+static void __init omap2_gp_clocksource_init(int gptimer_id,
+                                                const char *fck_source)
+{
+	if (omap_init_clocksource_32k())
+		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
+}

 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
 				clksrc_nr, clksrc_src)			\
-- 
1.7.5.4
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From paul.liu at linaro.org  Fri Mar 30 04:09:17 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Fri, 30 Mar 2012 16:09:17 +0800
Subject: [PATCH] ARM: dts: imx6q: add anatop regulators
In-Reply-To: <20120322074520.GD2213@S2101-09.ap.freescale.net>
References: <1332214139-6833-1-git-send-email-paul.liu@linaro.org>
 <20120322074520.GD2213@S2101-09.ap.freescale.net>
Message-ID: <4F756A2D.9020500@linaro.org>

(2012?03?22? 15:45), Shawn Guo wrote:
>> +				};
>> +
>> +				regulator-1p1 at 110 {
>> +					compatible = "fsl,anatop-regulator";
>> +					regulator-name = "vdd1p1";
>> +					regulator-min-microvolt = <800000>;
>> +					regulator-max-microvolt = <1400000>;
>> +					regulator-always-on;
>> +					reg = <0x110>;
>> +					anatop-vol-bit-shift = <8>;
>> +					anatop-vol-bit-width = <5>;
>> +					anatop-min-bit-val = <4>;
>> +					anatop-min-voltage = <800000>;
>> +					anatop-max-voltage = <1400000>;
> 
> 1.375V

Hi Shawn,

Sorry, why it is not 1.4V?

LDO 1p1 should be from range 0.8V to 1.4V on section 53.3.1


From prylowski at metasoft.pl  Fri Mar 30 04:13:46 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Fri, 30 Mar 2012 10:13:46 +0200
Subject: [PATCH 1/3] PATA host controller driver for ep93xx
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F0020697025609@AUSP01VMBX24.collaborationhost.net>
References: <4F7418E7.4060500@metasoft.pl> <4F741AB1.4000107@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F0020697025609@AUSP01VMBX24.collaborationhost.net>
Message-ID: <4F756B3A.8050901@metasoft.pl>

On 2012-03-29 19:25, H Hartley Sweeten wrote:
>> +#include <asm/mach-types.h>
>> +#include <mach/ep93xx-regs.h>
> 
> mach-types.h and ep93xx-regs.h should not be needed.

Ok. Will remove.

>> +static u8 ep93xx_pata_check_status(struct ata_port *ap)
>> +{
>> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> 
> Please add a whitespace here.

Ok. Will add.

>> +static u8 ep93xx_pata_check_altstatus(struct ata_port *ap)
>> +{
>> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> 
> Please add a whitespace here.

Ditto.

>> +static void ep93xx_pata_exec_command(struct ata_port *ap,
>> +                                  const struct ata_taskfile *tf)
>> +{
>> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> 
> Please add a whitespace here.

Ditto.

>> +static void ep93xx_pata_set_devctl(struct ata_port *ap, u8 ctl)
>> +{
>> +     struct ep93xx_pata_data *drv_data = ap->host->private_data;
> 
> Please add a whitespace here.

Ditto.

>> +     /* is all this really necessary? */
>> +     ap->ops->sff_dev_select(ap, 0);
>> +     if (dev1)
>> +             ap->ops->sff_dev_select(ap, 1);
>> +     if (dev0)
>> +             ap->ops->sff_dev_select(ap, 0);
> 
> Is it necessary? If so please remove the comment.

Many libata drivers are written by copying code from libata-core.c,
libata-sff.c etc., with some needed modifications. In case of ep93xx,
all functions which will do read/write to ATA registers need to be
slightly modified. I suppose functions modified from original libata code
should comment that fact (like in pata_scc.c for example). Will add that.
So, this is original libata code, and as I'm not libata/IDE expert,
I don't have any clue if the above code is necessary ;)

>> +     ep93xx_pata_write(drv_data, ap->ctl, ioaddr->ctl_addr, t);
>> +     udelay(20);             /* FIXME: flush */
>> +     ep93xx_pata_write(drv_data, ap->ctl | ATA_SRST, ioaddr->ctl_addr, t);
>> +     udelay(20);             /* FIXME: flush */
> 
> What's up with the FIXME?
> 

Ditto.

>> +     txd = channel->device->device_prep_slave_sg(channel, qc->sg,
>> +              qc->n_elem, qc->dma_dir, DMA_CTRL_ACK);
>> +     if (!txd) {
>> +             dev_err(qc->ap->dev, "failed to prepare slave for sg dma\n");
>> +             BUG();
> 
> Is there a better way to handle this than BUG()? Can the driver fall back to PIO mode?

Another possibility would be to replace this BUG() with return, and hope libata
error handling will recover from this problem. Will do that.

>> +     ioaddr->cmd_addr        = (void __iomem *) 0 + 2; /* CS1 */
>> +
>> +     ioaddr->data_addr       = (void __iomem *) (ATA_REG_DATA << 2) + 2;
>> +     ioaddr->error_addr      = (void __iomem *) (ATA_REG_ERR << 2) + 2;
>> +     ioaddr->feature_addr    = (void __iomem *) (ATA_REG_FEATURE << 2) + 2;
>> +     ioaddr->nsect_addr      = (void __iomem *) (ATA_REG_NSECT << 2) + 2;
>> +     ioaddr->lbal_addr       = (void __iomem *) (ATA_REG_LBAL << 2) + 2;
>> +     ioaddr->lbam_addr       = (void __iomem *) (ATA_REG_LBAM << 2) + 2;
>> +     ioaddr->lbah_addr       = (void __iomem *) (ATA_REG_LBAH << 2) + 2;
>> +     ioaddr->device_addr     = (void __iomem *) (ATA_REG_DEVICE << 2) + 2;
>> +     ioaddr->status_addr     = (void __iomem *) (ATA_REG_STATUS << 2) + 2;
>> +     ioaddr->command_addr    = (void __iomem *) (ATA_REG_CMD << 2) + 2;
>> +
>> +     ioaddr->altstatus_addr  = (void __iomem *) (0x06 << 2) + 1; /* CS0 */
>> +     ioaddr->ctl_addr        = (void __iomem *) (0x06 << 2) + 1; /* CS0 */
> 
> Is there any way to get rid of the casts? These aren't really (void __iomem *) anyway...

We could store all these values as a static table of unsigned ints IMHO. Then, in each
ep93xx_pata_read/write, replace ioaddr->... with proper value from table.
This should simplify the driver a bit. Will try to do that.

>> +     /*if (readl(EP93XX_SYSCON_DEVCFG) & (EP93XX_SYSCON_DEVCFG_EONIDE
>> +             | EP93XX_SYSCON_DEVCFG_GONIDE | EP93XX_SYSCON_DEVCFG_HONIDE)) {
>> +             dev_err(&pdev->dev, "IDE/GPIO pin conflict\n");
>> +             return -EINVAL;
>> +     }*/
> 
> Remove this, see my comment in PATCH 2/3.

Ok.

>> +     mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +     if (!mem_res) {
>> +             dev_err(&pdev->dev, "resources allocation failed\n");
> 
> Are these dev_err messages necessary?

Some libata drivers do it, others not... I think we could remove them.

>> +     ap->pio_mask = ATA_PIO4;
> 
> Please add a whitespace line here.

Ok.

>> +     if (drv_data->dma_rx_channel && drv_data->dma_tx_channel) {
>> +             int chip_rev = ep93xx_chip_revision();
> 
> Please add a whitespace here.

Ok.

>> +     return ata_host_activate(host, irq, ata_bmdma_interrupt, 0,
>> +             &ep93xx_pata_sht);
> 
> If the host does not activate do you need to handle any cleanup?

Hmm.. Probably dma channels should be released. Will add.

> Make sure to call the core ep93xx_ide_release_gpio function in the remove.

Yes. I'll remember that.

>> +module_init(ep93xx_pata_init);
>> +module_exit(ep93xx_pata_exit);
> 
> Please use module_platform_driver instead of module_init/module_exit.

Ok.

Thanks for thorough review.


From shawn.guo at linaro.org  Fri Mar 30 04:14:46 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 30 Mar 2012 16:14:46 +0800
Subject: [PATCH] ARM: dts: imx6q: add anatop regulators
In-Reply-To: <4F756A2D.9020500@linaro.org>
References: <1332214139-6833-1-git-send-email-paul.liu@linaro.org>
 <20120322074520.GD2213@S2101-09.ap.freescale.net>
 <4F756A2D.9020500@linaro.org>
Message-ID: <20120330081444.GE3254@S2101-09.ap.freescale.net>

On Fri, Mar 30, 2012 at 04:09:17PM +0800, Ying-Chun Liu (PaulLiu) wrote:
> (2012?03?22? 15:45), Shawn Guo wrote:
> >> +				};
> >> +
> >> +				regulator-1p1 at 110 {
> >> +					compatible = "fsl,anatop-regulator";
> >> +					regulator-name = "vdd1p1";
> >> +					regulator-min-microvolt = <800000>;
> >> +					regulator-max-microvolt = <1400000>;
> >> +					regulator-always-on;
> >> +					reg = <0x110>;
> >> +					anatop-vol-bit-shift = <8>;
> >> +					anatop-vol-bit-width = <5>;
> >> +					anatop-min-bit-val = <4>;
> >> +					anatop-min-voltage = <800000>;
> >> +					anatop-max-voltage = <1400000>;
> > 
> > 1.375V
> 
> Hi Shawn,
> 
> Sorry, why it is not 1.4V?
> 
> LDO 1p1 should be from range 0.8V to 1.4V on section 53.3.1

Hmm, I do not see 1.4V in register description (PMU_REG_1P1).

-- 
Regards,
Shawn


From prylowski at metasoft.pl  Fri Mar 30 04:19:02 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Fri, 30 Mar 2012 10:19:02 +0200
Subject: [PATCH 1/3] PATA host controller driver for ep93xx
In-Reply-To: <4F74E111.60503@gmail.com>
References: <4F7418E7.4060500@metasoft.pl> <4F741AB1.4000107@metasoft.pl>
 <4F74E111.60503@gmail.com>
Message-ID: <4F756C76.2040206@metasoft.pl>

On 2012-03-30 00:24, Ryan Mallon wrote:
> On 29/03/12 19:17, Rafal Prylowski wrote:
> 
>> Signed-off-by: Rafal Prylowski <prylowski at metasoft.pl>
>> Cc: Joao Ramos <joao.ramos at inov.pt>
>> Cc: H Hartley Sweeten <hsweeten at visionengravers.com>
>> Cc: Ryan Mallon <ryan at bluewatersys.com>
> 
> 
> Please note. This email address is no longer valid for me.
> 
> Thanks,
> ~Ryan
> 

Sorry about that. I noticed that my email program keeps both
email addresses. I will remove invalid one.


From prylowski at metasoft.pl  Fri Mar 30 04:29:48 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Fri, 30 Mar 2012 10:29:48 +0200
Subject: [PATCH 2/3] ep93xx: IDE driver platform support code
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F00206970255B6@AUSP01VMBX24.collaborationhost.net>
References: <4F7418E7.4060500@metasoft.pl> <4F741B07.7040107@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F00206970255B6@AUSP01VMBX24.collaborationhost.net>
Message-ID: <4F756EFC.3080501@metasoft.pl>

On 2012-03-29 18:26, H Hartley Sweeten wrote:
>> +/*************************************************************************
>> + * EP93xx IDE
>> + *************************************************************************/
>> +static struct resource ep93xx_ide_resources[] = {
>> +	[0] = {
>> +		.start	= EP93XX_IDE_PHYS_BASE,
>> +		.end	= EP93XX_IDE_PHYS_BASE + 0xffff,
>> +		.flags	= IORESOURCE_MEM,
>> +	},
>> +	[1] = {
>> +		.start	= IRQ_EP93XX_EXT3,
>> +		.end	= IRQ_EP93XX_EXT3,
>> +		.flags	= IORESOURCE_IRQ,
>> +	},
>> +};
> 
> Please use the DEFINE_RES_* macros.
> Also, the last register in the IDE interface is at offset 0x34, so something like this:
> 
> static struct resource ep93xx_ide_resources[] = {
> 	DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38),
> 	DEFINE_RES_IRQ(IRQ_EP93XX_EXT3),
> };
> 

Ok. Will do.

>> +void __init ep93xx_register_ide(void)
>> +{
>> +	/* GPIO ports E, G and H used by IDE */
>> +	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
>> +				 EP93XX_SYSCON_DEVCFG_GONIDE |
>> +				 EP93XX_SYSCON_DEVCFG_HONIDE);
>> +	platform_device_register(&ep93xx_ide_device);
>> +}
> 
> Please create ep93xx_ide_acquire_gpio and ep93xx_ide_acquire_gpio functions
> to set/clear the necessary SYSCON bits during the probe/remove of the ide driver.
> 
> This should also address your concern mentioned in PATCH 0/3 about making sure
> the pin muxing is correct when the driver is loaded.
> 
> The *_acquire_gpio function should also gpio_request  the pins before setting the
> SYSCON bits. That way if any of the pins are unavailable the driver will not load. Make
> sure to gpio_free the pins in the *_release_gpio function.  Look at how the keypad
> is handled for an example.

Yes, that makes sense. I will add necessary functions and modify the driver accordingly.

Thanks for comments.

Regards,
RP



From hvaibhav at ti.com  Fri Mar 30 04:32:09 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 30 Mar 2012 08:32:09 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>

On Fri, Mar 30, 2012 at 13:11:35, Shilimkar, Santosh wrote:
> On Fri, Mar 30, 2012 at 12:04 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> > On Wed, Mar 28, 2012 at 20:19:07, Shilimkar, Santosh wrote:
> >> On Wed, Mar 28, 2012 at 8:07 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >> > On Wed, Mar 28, 2012 at 19:50:02, Shilimkar, Santosh wrote:
> >> >> On Wed, Mar 28, 2012 at 7:46 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >> >> > On Wed, Mar 21, 2012 at 19:30:01, Shilimkar, Santosh wrote:
> >> >> >> On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >> >> >> > On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
> >> >> >> >> On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
> >> >> >> >> > On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >> >>
> [...]
> 
> >> I thought so and now if you look at last part of my comment.
> >>
> >> Rating of 32K based synctimer and 32K based GPTIMER
> >> should be same because of the precision. That's the main
> >> point why I was saying that GPTIMER is not a better
> >> clock-source( with 32k clock src) ?than sync timer when
> >> both are enabled together.
> >>
> >
> > Santosh,
> >
> > In case of OMAP, we are using timer 2 for clocksource
> >
> > OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
> > OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
> >
> > And timer2 as clocksource is never used, since we have CONFIG_OMAP_32K_TIMER
> > defined in our defconfig.
> >
> > Also, after looking at the code, I came across another problem, setup_sched_clock(). But this can be easily fixed, if we source both the timers with same clock (here 32k_fck).
> >
> >
> > Let me propose this,
> >
> > How about, if I keep timer2 source always set to 32k_fclk for omap2,3,4?
> > And also, as mentioned by Santosh, I will register both the clocks as
> > clocksource with the same rating.
> > By default, kernel is going to use 32k_counter as a clocksource, and through
> > Command prompt user can override it without any issues.
> >
> > Just to make sure that, whatever I am trying to propse here works and don't get into unknown issue; I changed my code for this, and it is working for me without any issues.
> 
> Let's not make this more complicated. I guess below simple patch should sort
> out the issue. I briefly tested it on OMAP4 and it works. let me know
> if it helps AMxxx machines.
> 
> Regards
> Santosh
> 
> From 0a9283e26174d76ff2753ac88521b61a26b24e8f Mon Sep 17 00:00:00 2001
> From: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Date: Fri, 30 Mar 2012 12:43:29 +0530
> Subject: [PATCH] ARM: OMAP: Make OMAP clocksource source selection runtime.
> 
> Current OMAP code support couple of clocksource options based on compilation
> flag. The 32KHz based sync timer and a gptimer based clock source which can
> run on 32KHz or system clock (e.g 38.4 MHz). So there can be 3 options.
> 
> 1. 32KHz synctimer
> 2. Sysclock based(e.g 38.4 MHz) gptimer
> 3. 32KHz based gptimer.
> 
> The optional gptimer based clocksource was added so that it can give the
> high precision than synctimer so expected usage was 2 and not 3. Unfortunatlly
> option 2, clocksource doesn't meet the requirement of free-running clock
> as per clocksource need. It stops in low power states when  sysclock is cut.
> That makes gptimer based clocksource option useless for OMAP2/3/4 devices
> with sysclock as a clock input. Option 3 will still work but it is no better'
> than 32K synctimer based clocksource.
> 
> So ideally we can kill the gptimer based clocksource option but there are some
> OMAP based derivative SoCs like AMXXXX which doesn't have synictimer hardware IP
> and need to fallback on 32KHz based gptimer clocksource.
> 
> Considering above, make synctimer and gptimer clocksource runtime
> selectable so that both OMAP and AMXXXX continue to use the same code.
> 
> Not-yet-signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> ---
>  arch/arm/mach-omap2/timer.c |   25 ++++++++-----------------
>  1 files changed, 8 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index c512bac..3878e59 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -234,21 +234,6 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
>  }
> 
>  /* Clocksource code */
> -
> -#ifdef CONFIG_OMAP_32K_TIMER
> -/*
> - * When 32k-timer is enabled, don't use GPTimer for clocksource
> - * instead, just leave default clocksource which uses the 32k
> - * sync counter.  See clocksource setup in plat-omap/counter_32k.c
> - */
> -
> -static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
> -{
> -	omap_init_clocksource_32k();
> -}
> -
> -#else
> -
>  static struct omap_dm_timer clksrc;
> 
>  /*
> @@ -276,7 +261,7 @@ static u32 notrace dmtimer_read_sched_clock(void)
>  }
> 
>  /* Setup free-running counter for clocksource */
> -static void __init omap2_gp_clocksource_init(int gptimer_id,
> +static void __init omap2_gptimer_clocksource_init(int gptimer_id,
>  						const char *fck_source)
>  {
>  	int res;
> @@ -295,7 +280,13 @@ static void __init omap2_gp_clocksource_init(int
> gptimer_id,
>  		pr_err("Could not register clocksource %s\n",
>  			clocksource_gpt.name);
>  }
> -#endif
> +
> +static void __init omap2_gp_clocksource_init(int gptimer_id,
> +                                                const char *fck_source)
> +{
> +	if (omap_init_clocksource_32k())
> +		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
> +}
> 

With this patch, will you be able to choose gptimer as a clocksource
using bootparameter (or sysfs) for given kernel uImage?

The answer is simply NO...as the registration of gptimer is based on
failure from omap_init_clocksource_32k(). And this is nothing different 
than my original patch, my patch exactly does same thing.

The requirement after 'ming Lie' response on my patch was, there will be
usecases where we might need to use gptimer for clocksource and with 
the patch it is not possible, since you will only register 
32k_counter here.

So in order to allow user to choose between 32K and gptimer, you must 
register both and make 32k as a default thing.


Thanks,
Vaibhav



From prylowski at metasoft.pl  Fri Mar 30 04:32:25 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Fri, 30 Mar 2012 10:32:25 +0200
Subject: [PATCH 3/3] ep93xx: Add IDE support to edb93xx boards
In-Reply-To: <ADE657CA350FB648AAC2C43247A983F00206970255C3@AUSP01VMBX24.collaborationhost.net>
References: <4F7418E7.4060500@metasoft.pl> <4F741B3F.4000507@metasoft.pl>
 <ADE657CA350FB648AAC2C43247A983F00206970255C3@AUSP01VMBX24.collaborationhost.net>
Message-ID: <4F756F99.8090301@metasoft.pl>

On 2012-03-29 18:32, H Hartley Sweeten wrote:
>> +static int __init edb93xx_has_ide(void)
>> +{
>> +	/*
>> +	 * Although EDB9312 and EDB9315 do have IDE capability, they have
>> +	 * INTRQ line wired as pull-up, which makes using IDE interface
>> +	 * problematic.
>> +	 */
>> +	return machine_is_edb9315a();
> 
> Allow the driver to be loaded on the EDB9312 and EDB9315 but leave the comment.
> If a use of these boards wishes to use the IDE they could remove the pull-up and add
> a pull-down to their board.

Ok. Will do that.


From heiko at sntech.de  Fri Mar 30 04:32:54 2012
From: heiko at sntech.de (Heiko =?iso-8859-1?q?St=FCbner?=)
Date: Fri, 30 Mar 2012 10:32:54 +0200
Subject: [PATCH] ARM: S3C64XX: Add basic cpuidle driver
In-Reply-To: <20111222181359.GA19259@sirena.org.uk>
References: <1323117169-9817-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <201112061231.22570.heiko@sntech.de> <20111222181359.GA19259@sirena.org.uk>
Message-ID: <201203301032.54739.heiko@sntech.de>

Hi Mark,

Am Donnerstag, 22. Dezember 2011, 19:13:59 schrieb Mark Brown:
> On Tue, Dec 06, 2011 at 12:31:21PM +0100, Heiko St?bner wrote:
> > So I'm really looking forward to seeing a possible example on how to
> > support the STOP and DEEP-STOP modes best.
> 
> My plan there for the s3c64xx was to use pm_domain to figure out if the
> system is idle enough to drop down, I've been adding some pm_runtime
> support to provide the information to the core to let it figure this out.

sorry for digging this up again, but do you happen to have some preliminary 
code laying around for this, that I could "borrow"?


Thanks
Heiko


From myungjoo.ham at samsung.com  Fri Mar 30 04:33:44 2012
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Fri, 30 Mar 2012 17:33:44 +0900
Subject: [PATCH v6 2/5] Extcon: support generic GPIO extcon driver
In-Reply-To: <4F74E435.9030101@codeaurora.org>
References: <1328856038-21912-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-3-git-send-email-myungjoo.ham@samsung.com>
 <4F74E435.9030101@codeaurora.org>
Message-ID: <CAJ0PZbR3TLoa+UDM7mZLugjfMR_R-j7dKr7dTk0QFy9WM5etMQ@mail.gmail.com>

On Fri, Mar 30, 2012 at 7:37 AM, Stephen Boyd <sboyd at codeaurora.org> wrote:
> On 02/27/12 04:15, MyungJoo Ham wrote
>> +static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
>> +{
>> + ? ? struct gpio_extcon_data *extcon_data =
>> + ? ? ? ? (struct gpio_extcon_data *)dev_id;
>
> Casting from void is unnecessary.
>
>> +
>> +static int gpio_extcon_probe(struct platform_device *pdev)
>
> __devinit?
>
>> +{
>> + ? ? struct gpio_extcon_platform_data *pdata = pdev->dev.platform_data;
>> + ? ? struct gpio_extcon_data *extcon_data;
>> + ? ? int ret = 0;
> [snip]
>> + ? ? return ret;
>> +}
>> +
>> +static int gpio_extcon_remove(struct platform_device *pdev)
>
> __devexit?
>> +{
>> + ? ? struct gpio_extcon_data *extcon_data = platform_get_drvdata(pdev);
> [snip]
>> +static struct platform_driver gpio_extcon = {
>> + ? ? .probe ? ? ? ? ?= gpio_extcon_probe,
>> + ? ? .remove ? ? ? ? = gpio_extcon_remove,
>
> __devexit_p()?
>> + ? ? .driver ? ? ? ? = {
>> + ? ? ? ? ? ? .name ? = "extcon-gpio",
>> + ? ? ? ? ? ? .owner ?= THIS_MODULE,
>> + ? ? },
>> +};
>> +
>> +module_platform_driver(gpio_extcon);
>> +
>> +MODULE_AUTHOR("Mike Lockwood <lockwood at android.com>");
>> +MODULE_DESCRIPTION("GPIO extcon driver");
>> +MODULE_LICENSE("GPL");
> --
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
>

Thank you for the comments.

I'll apply it and test on patchset v8.



Cheers!
MyungJoo.

-- 
MyungJoo Ham, Ph.D.
Mobile Software Platform Lab, DMC Business, Samsung Electronics


From r.sricharan at ti.com  Fri Mar 30 04:35:16 2012
From: r.sricharan at ti.com (R Sricharan)
Date: Fri, 30 Mar 2012 14:05:16 +0530
Subject: [PATCH] ARM: OMAP2+: Fix omap2+ build error.
Message-ID: <1333096516-4252-1-git-send-email-r.sricharan@ti.com>

With CONFIG_OMAP4_ERRATA_I688 enabled, omap2+ build
was broken as below.

	arch/arm/kernel/io.c: In function '_memcpy_toio':
	arch/arm/kernel/io.c:29: error: implicit declaration of function 'outer_sync'
	make[1]: *** [arch/arm/kernel/io.o] Error 1

Fixing this here.

Signed-off-by: R Sricharan <r.sricharan at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/include/asm/barrier.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 44f4a09..0511238 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -2,6 +2,7 @@
 #define __ASM_BARRIER_H
 
 #ifndef __ASSEMBLY__
+#include <asm/outercache.h>
 
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
@@ -39,7 +40,6 @@
 #ifdef CONFIG_ARCH_HAS_BARRIERS
 #include <mach/barriers.h>
 #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
-#include <asm/outercache.h>
 #define mb()		do { dsb(); outer_sync(); } while (0)
 #define rmb()		dsb()
 #define wmb()		mb()
-- 
1.7.1



From santosh.shilimkar at ti.com  Fri Mar 30 04:38:20 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 30 Mar 2012 14:08:20 +0530
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
Message-ID: <4F7570FC.8000907@ti.com>

On Friday 30 March 2012 02:02 PM, Hiremath, Vaibhav wrote:
> On Fri, Mar 30, 2012 at 13:11:35, Shilimkar, Santosh wrote:
>> On Fri, Mar 30, 2012 at 12:04 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>>> On Wed, Mar 28, 2012 at 20:19:07, Shilimkar, Santosh wrote:
>>>> On Wed, Mar 28, 2012 at 8:07 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>>>>> On Wed, Mar 28, 2012 at 19:50:02, Shilimkar, Santosh wrote:
>>>>>> On Wed, Mar 28, 2012 at 7:46 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>>>>>>> On Wed, Mar 21, 2012 at 19:30:01, Shilimkar, Santosh wrote:
>>>>>>>> On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>>>>>>>>> On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
>>>>>>>>>> On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
>>>>>>>>>>> On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>>>>>>
>> [...]
>>
>>>> I thought so and now if you look at last part of my comment.
>>>>
>>>> Rating of 32K based synctimer and 32K based GPTIMER
>>>> should be same because of the precision. That's the main
>>>> point why I was saying that GPTIMER is not a better
>>>> clock-source( with 32k clock src)  than sync timer when
>>>> both are enabled together.
>>>>
>>>
>>> Santosh,
>>>
>>> In case of OMAP, we are using timer 2 for clocksource
>>>
>>> OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
>>> OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
>>>
>>> And timer2 as clocksource is never used, since we have CONFIG_OMAP_32K_TIMER
>>> defined in our defconfig.
>>>
>>> Also, after looking at the code, I came across another problem, setup_sched_clock(). But this can be easily fixed, if we source both the timers with same clock (here 32k_fck).
>>>
>>>
>>> Let me propose this,
>>>
>>> How about, if I keep timer2 source always set to 32k_fclk for omap2,3,4?
>>> And also, as mentioned by Santosh, I will register both the clocks as
>>> clocksource with the same rating.
>>> By default, kernel is going to use 32k_counter as a clocksource, and through
>>> Command prompt user can override it without any issues.
>>>
>>> Just to make sure that, whatever I am trying to propse here works and don't get into unknown issue; I changed my code for this, and it is working for me without any issues.
>>
>> Let's not make this more complicated. I guess below simple patch should sort
>> out the issue. I briefly tested it on OMAP4 and it works. let me know
>> if it helps AMxxx machines.
>>
>> Regards
>> Santosh
>>
>> From 0a9283e26174d76ff2753ac88521b61a26b24e8f Mon Sep 17 00:00:00 2001
>> From: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> Date: Fri, 30 Mar 2012 12:43:29 +0530
>> Subject: [PATCH] ARM: OMAP: Make OMAP clocksource source selection runtime.
>>
>> Current OMAP code support couple of clocksource options based on compilation
>> flag. The 32KHz based sync timer and a gptimer based clock source which can
>> run on 32KHz or system clock (e.g 38.4 MHz). So there can be 3 options.
>>
>> 1. 32KHz synctimer
>> 2. Sysclock based(e.g 38.4 MHz) gptimer
>> 3. 32KHz based gptimer.
>>
>> The optional gptimer based clocksource was added so that it can give the
>> high precision than synctimer so expected usage was 2 and not 3. Unfortunatlly
>> option 2, clocksource doesn't meet the requirement of free-running clock
>> as per clocksource need. It stops in low power states when  sysclock is cut.
>> That makes gptimer based clocksource option useless for OMAP2/3/4 devices
>> with sysclock as a clock input. Option 3 will still work but it is no better'
>> than 32K synctimer based clocksource.
>>
>> So ideally we can kill the gptimer based clocksource option but there are some
>> OMAP based derivative SoCs like AMXXXX which doesn't have synictimer hardware IP
>> and need to fallback on 32KHz based gptimer clocksource.
>>
>> Considering above, make synctimer and gptimer clocksource runtime
>> selectable so that both OMAP and AMXXXX continue to use the same code.
>>
>> Not-yet-signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> ---
>>  arch/arm/mach-omap2/timer.c |   25 ++++++++-----------------
>>  1 files changed, 8 insertions(+), 17 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
>> index c512bac..3878e59 100644
>> --- a/arch/arm/mach-omap2/timer.c
>> +++ b/arch/arm/mach-omap2/timer.c
>> @@ -234,21 +234,6 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
>>  }
>>
>>  /* Clocksource code */
>> -
>> -#ifdef CONFIG_OMAP_32K_TIMER
>> -/*
>> - * When 32k-timer is enabled, don't use GPTimer for clocksource
>> - * instead, just leave default clocksource which uses the 32k
>> - * sync counter.  See clocksource setup in plat-omap/counter_32k.c
>> - */
>> -
>> -static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
>> -{
>> -	omap_init_clocksource_32k();
>> -}
>> -
>> -#else
>> -
>>  static struct omap_dm_timer clksrc;
>>
>>  /*
>> @@ -276,7 +261,7 @@ static u32 notrace dmtimer_read_sched_clock(void)
>>  }
>>
>>  /* Setup free-running counter for clocksource */
>> -static void __init omap2_gp_clocksource_init(int gptimer_id,
>> +static void __init omap2_gptimer_clocksource_init(int gptimer_id,
>>  						const char *fck_source)
>>  {
>>  	int res;
>> @@ -295,7 +280,13 @@ static void __init omap2_gp_clocksource_init(int
>> gptimer_id,
>>  		pr_err("Could not register clocksource %s\n",
>>  			clocksource_gpt.name);
>>  }
>> -#endif
>> +
>> +static void __init omap2_gp_clocksource_init(int gptimer_id,
>> +                                                const char *fck_source)
>> +{
>> +	if (omap_init_clocksource_32k())
>> +		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
>> +}
>>
> 
> With this patch, will you be able to choose gptimer as a clocksource
> using bootparameter (or sysfs) for given kernel uImage?
> 
Why do you want that ? Look at changelog. The gptimer based clocksource
is useless for OMAP and for AM devices synctimer is not available.


> The answer is simply NO...as the registration of gptimer is based on
> failure from omap_init_clocksource_32k(). And this is nothing different 
> than my original patch, my patch exactly does same thing.
> 
I ight have missed your original patch. If that patch is similar then
no problems.

> The requirement after 'ming Lie' response on my patch was, there will be
> usecases where we might need to use gptimer for clocksource and with 
> the patch it is not possible, since you will only register 
> 32k_counter here.
> 
I think Ming Lie might have expected that gptimer clocksource might
be better which is not the case.

> So in order to allow user to choose between 32K and gptimer, you must 
> register both and make 32k as a default thing.
> 
As described in the commit log, its not needed at all. Let's not add
a feature which is just useless because the gptimer based clock
source has no advantage against the syntimer.

Hope this clarifies.

Regards
Santosh



From santosh.shilimkar at ti.com  Fri Mar 30 04:49:33 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 30 Mar 2012 14:19:33 +0530
Subject: [PATCH] ARM: OMAP2+: Fix omap2+ build error.
In-Reply-To: <1333096516-4252-1-git-send-email-r.sricharan@ti.com>
References: <1333096516-4252-1-git-send-email-r.sricharan@ti.com>
Message-ID: <CAMQu2gyqXsft-DByeGYRt8V-gWB-8B8QJk55WLj5XyO+EMYYKw@mail.gmail.com>

On Fri, Mar 30, 2012 at 2:05 PM, R Sricharan <r.sricharan at ti.com> wrote:
> With CONFIG_OMAP4_ERRATA_I688 enabled, omap2+ build
> was broken as below.
>
> ? ? ? ?arch/arm/kernel/io.c: In function '_memcpy_toio':
> ? ? ? ?arch/arm/kernel/io.c:29: error: implicit declaration of function 'outer_sync'
> ? ? ? ?make[1]: *** [arch/arm/kernel/io.o] Error 1
>
> Fixing this here.
>
> Signed-off-by: R Sricharan <r.sricharan at ti.com>
> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> ---
> ?arch/arm/include/asm/barrier.h | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
Can you please add information about the commit
after this was broken.

Regards
santosh


From shawn.guo at linaro.org  Fri Mar 30 04:51:06 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 30 Mar 2012 16:51:06 +0800
Subject: [PATCH v3 1/1] ARM: imx28: add basic dt support
In-Reply-To: <1333089130-24832-1-git-send-email-b29396@freescale.com>
References: <1333089130-24832-1-git-send-email-b29396@freescale.com>
Message-ID: <20120330085103.GF3254@S2101-09.ap.freescale.net>

I tried to apply the patch, but ...

On Fri, Mar 30, 2012 at 02:32:10PM +0800, Dong Aisheng wrote:
...
> +static int __init mxs_icoll_add_irq_domain(struct device_node *np,
> +				struct device_node *interrupt_parent)
> +{
> +	irq_domain_add_simple(np, 0);

The irq_domain_add_simple() has been removed from mainline.  You need
a rebase against Linus' tree.

> +
> +	return 0;
> +}
> +
> +static const struct of_device_id mxs_irq_match[] __initconst = {
> +	{ .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
> +	{ /* sentinel */ }
> +};
> +
> +static void __init mxs_dt_init_irq(void)
> +{
> +	icoll_init_irq();
> +	of_irq_init(mxs_irq_match);
> +}
> +
> +static void __init imx28_timer_init(void)
> +{
> +	mx28_clocks_init();
> +}
> +
> +static struct sys_timer imx28_timer = {
> +	.init = imx28_timer_init,
> +};
> +
> +static void __init mxs_machine_init(void)
> +{
> +       of_platform_populate(NULL, of_default_bus_match_table,

Given by checkpatch:

WARNING: please, no spaces at the start of a line
#565: FILE: arch/arm/mach-mxs/mach-mxs.c:51:
+       of_platform_populate(NULL, of_default_bus_match_table,$

> +				NULL, NULL);
> +}

-- 
Regards,
Shawn


From myungjoo.ham at gmail.com  Fri Mar 30 04:56:01 2012
From: myungjoo.ham at gmail.com (MyungJoo Ham)
Date: Fri, 30 Mar 2012 17:56:01 +0900
Subject: [PATCH v6 1/5] Extcon (external connector): import Android's
 switch class and modify.
In-Reply-To: <CACSP8ShU5tu=9N53PtYMLyFVFMS9whNRhMvu7nu8rBoPuVCy+Q@mail.gmail.com>
References: <1328856038-21912-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-2-git-send-email-myungjoo.ham@samsung.com>
 <20120309124119.GV3273@opensource.wolfsonmicro.com>
 <CACSP8ShU5tu=9N53PtYMLyFVFMS9whNRhMvu7nu8rBoPuVCy+Q@mail.gmail.com>
Message-ID: <CAJ0PZbT728rhQ5esf0arRw-TtgBGMCgAvZhW9-AejmbT9WOahw@mail.gmail.com>

On Fri, Mar 30, 2012 at 7:27 AM, Erik Gilling <konkers at google.com> wrote:
> On Fri, Mar 9, 2012 at 4:41 AM, Mark Brown
> <broonie at opensource.wolfsonmicro.com> wrote:
>> On Mon, Feb 27, 2012 at 09:15:35PM +0900, MyungJoo Ham wrote:
>>
>>> +#ifdef CONFIG_ANDROID
>>> + ? ? ? ? ? ? extcon_class = class_create(THIS_MODULE, "switch");
>>> +#else /* !CONFIG_ANDROID */
>>> + ? ? ? ? ? ? extcon_class = class_create(THIS_MODULE, "extcon");
>>> +#endif /* CONFIG_ANDROID */
>>
>> This seems somewhat sad - if ANDROID is turned on the standard ABI
>> vanishes. ?It'd be much nicer to do this with a symlink (or with
>> symlinks within the android directory if the driver core doesn't support
>> that). ?That way userspace code can be written to the new ABI and will
>> work on Android systems without ifdefery.
>
> This won't work if userspace code is receiving uevents through netlink
> and comparing based on the device name which it does in android. ?Why
> change the name at all? ?Extcon is much more specific than "switch."
> A switch can can be used for more than just external connections such
> as availability of HMDI audio (which is only available once a HDMI
> mode is chosen and the interface is enabled.)
>
> -Erik

With class_compat as in patchset v7, (this thread is w/ v6) does the
issue (missing link from device name directory) still exist? (I don't
think so)

In the earlier iteration of dicussion, the name "switch" was dropped
as "switch" may mislead the concept.
https://lkml.org/lkml/2011/11/29/299

For HDMI and HDMI-audio, although HDMI-audio is not physically
seperated from HDMI-cable and it is available after HDMI-cable is
"attached", HDMI-audio is still an external connection to the kernel
and its device drivers, isn' it?

Cheers!
MyungJoo.
-- 
MyungJoo Ham, Ph.D.
System S/W Lab, S/W Center, Samsung Electronics


From fabio.porcedda at gmail.com  Fri Mar 30 04:56:56 2012
From: fabio.porcedda at gmail.com (Fabio Porcedda)
Date: Fri, 30 Mar 2012 10:56:56 +0200
Subject: [PATCH] ARM: at91: add support for Telit GE863-PRO3 Evaluation Kit
Message-ID: <1333097816-8641-1-git-send-email-fabio.porcedda@gmail.com>

Based on board-sam9260ek.c.

Signed-off-by: Fabio Porcedda <fabio.porcedda at gmail.com>
---
 arch/arm/mach-at91/Kconfig            |    6 +
 arch/arm/mach-at91/Makefile           |    1 +
 arch/arm/mach-at91/board-ge863-pro3.c |  338 +++++++++++++++++++++++++++++++++
 3 files changed, 345 insertions(+)
 create mode 100644 arch/arm/mach-at91/board-ge863-pro3.c

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 45db05d..4197a2a 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -272,6 +272,12 @@ config MACH_FLEXIBITY
 	  Select this if you are using Flexibity Connect board
 	  <http://www.flexibity.com>
 
+config MACH_GE863_PRO3_EVK
+       bool "Telit GE863-PRO3 Evaluation Kit"
+       help
+         Select this if you are using Telit GE863-PRO3 Evaluation Kit
+	 <http://www.telit.com>
+
 endif
 
 # ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 8512e53..5ca096d 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_MACH_QIL_A9260)	+= board-qil-a9260.o
 obj-$(CONFIG_MACH_AFEB9260)	+= board-afeb-9260v1.o
 obj-$(CONFIG_MACH_CPU9260)	+= board-cpu9krea.o
 obj-$(CONFIG_MACH_FLEXIBITY)	+= board-flexibity.o
+obj-$(CONFIG_MACH_GE863_PRO3_EVK) += board-ge863-pro3.o
 
 # AT91SAM9261 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
diff --git a/arch/arm/mach-at91/board-ge863-pro3.c b/arch/arm/mach-at91/board-ge863-pro3.c
new file mode 100644
index 0000000..2855cc0
--- /dev/null
+++ b/arch/arm/mach-at91/board-ge863-pro3.c
@@ -0,0 +1,338 @@
+/*
+ * linux/arch/arm/mach-at91/board-ge863-pro3-evk.c
+ *
+ *  Copyright (C) 2012 Telit
+ *
+ * linux/arch/arm/mach-at91/board-sam9260ek.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/at73c213.h>
+#include <linux/clk.h>
+#include <linux/i2c/at24.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91_shdwc.h>
+#include <mach/system_rev.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+
+static void __init ek_init_early(void)
+{
+	/* Initialize processor: 6.000 MHz crystal */
+	at91_initialize(6000000);
+
+	/* DBGU on ttyS0. (Rx & Tx only) */
+	at91_register_uart(0, 0, 0);
+
+	/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+	at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
+			   | ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR
+			   | ATMEL_UART_DCD | ATMEL_UART_RI);
+
+	/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+	at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS
+			   | ATMEL_UART_RTS);
+
+	/* set serial console to ttyS0 (ie, DBGU) */
+	at91_set_serial_console(0);
+}
+
+/* USB Host port */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+	.ports		 = 2,
+	.vbus_pin	 = {-EINVAL, -EINVAL},
+	.overcurrent_pin = {-EINVAL, -EINVAL},
+};
+
+/* USB Device port */
+static struct at91_udc_data __initdata ek_udc_data = {
+	.vbus_pin	= AT91_PIN_PC5,
+	.pullup_pin	= -EINVAL,		/* pull-up driven by UDC */
+};
+
+
+/* Audio */
+static struct at73c213_board_info at73c213_data = {
+	.ssc_id		= 0,
+	.shortname	= "AT91SAM9260-EK external DAC",
+};
+
+#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
+static void __init at73c213_set_clk(struct at73c213_board_info *info)
+{
+	struct clk *pck0;
+	struct clk *plla;
+
+	pck0 = clk_get(NULL, "pck0");
+	plla = clk_get(NULL, "plla");
+
+	/* AT73C213 MCK Clock */
+	at91_set_B_periph(AT91_PIN_PC1, 0);	/* PCK0 */
+
+	clk_set_parent(pck0, plla);
+	clk_put(plla);
+
+	info->dac_clk = pck0;
+}
+#else
+static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
+#endif
+
+/* SPI devices. */
+static struct spi_board_info ek_spi_devices[] = {
+#if !defined(CONFIG_MMC_AT91)
+	{	/* DataFlash chip */
+		.modalias	= "mtd_dataflash",
+		.chip_select	= 1,
+		.max_speed_hz	= 15 * 1000 * 1000,
+		.bus_num	= 0,
+	},
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+	{	/* DataFlash card */
+		.modalias	= "mtd_dataflash",
+		.chip_select	= 0,
+		.max_speed_hz	= 15 * 1000 * 1000,
+		.bus_num	= 0,
+	},
+#endif
+#endif
+#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
+	{	/* AT73C213 DAC */
+		.modalias	= "at73c213",
+		.chip_select	= 0,
+		.max_speed_hz	= 10 * 1000 * 1000,
+		.bus_num	= 1,
+		.mode		= SPI_MODE_1,
+		.platform_data	= &at73c213_data,
+	},
+#endif
+};
+
+
+/* MACB Ethernet device */
+static struct macb_platform_data __initdata ek_macb_data = {
+	.phy_irq_pin	= AT91_PIN_PA7,
+	.is_rmii	= 1,
+};
+
+
+/* NAND flash */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+	{
+		.name	= "Partition 1",
+		.offset	= 0,
+		.size	= SZ_256K,
+	},
+	{
+		.name	= "Partition 2",
+		.offset	= MTDPART_OFS_NXTBLK,
+		.size	= MTDPART_SIZ_FULL,
+	},
+};
+
+static struct atmel_nand_data __initdata ek_nand_data = {
+	.ale		= 21,
+	.cle		= 22,
+	.det_pin	= -EINVAL,
+	.rdy_pin	= AT91_PIN_PC13,
+	.enable_pin	= AT91_PIN_PC14,
+	.parts		= ek_nand_partition,
+	.num_parts	= ARRAY_SIZE(ek_nand_partition),
+};
+
+static struct sam9_smc_config __initdata ek_nand_smc_config = {
+	.ncs_read_setup		= 0,
+	.nrd_setup		= 1,
+	.ncs_write_setup	= 0,
+	.nwe_setup		= 1,
+
+	.ncs_read_pulse		= 3,
+	.nrd_pulse		= 3,
+	.ncs_write_pulse	= 3,
+	.nwe_pulse		= 3,
+
+	.read_cycle		= 5,
+	.write_cycle		= 5,
+
+	.mode			= AT91_SMC_READMODE | AT91_SMC_WRITEMODE
+				  | AT91_SMC_EXNWMODE_DISABLE,
+	.tdf_cycles		= 2,
+};
+
+static void __init ek_add_device_nand(void)
+{
+	ek_nand_data.bus_width_16 = board_have_nand_16bit();
+	/* setup bus-width (8 or 16) */
+	if (ek_nand_data.bus_width_16)
+		ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
+	else
+		ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
+
+	/* configure chip-select 3 (NAND) */
+	sam9_smc_configure(0, 3, &ek_nand_smc_config);
+
+	at91_add_device_nand(&ek_nand_data);
+}
+
+
+/* MCI (SD/MMC) */
+static struct at91_mmc_data __initdata ek_mmc_data = {
+	.slot_b		= 1,
+	.wire4		= 1,
+	.det_pin	= -EINVAL,
+	.wp_pin		= -EINVAL,
+	.vcc_pin	= -EINVAL,
+};
+
+
+/* LEDs */
+static struct gpio_led ek_leds[] = {
+	{	/* "bottom" led, green, userled1 to be defined */
+		.name			= "ds5",
+		.gpio			= AT91_PIN_PA6,
+		.active_low		= 1,
+		.default_trigger	= "none",
+	},
+	{	/* "power" led, yellow */
+		.name			= "ds1",
+		.gpio			= AT91_PIN_PA9,
+		.default_trigger	= "heartbeat",
+	}
+};
+
+/* I2C devices */
+static struct at24_platform_data at24c512 = {
+	.byte_len	= SZ_512K / 8,
+	.page_size	= 128,
+	.flags		= AT24_FLAG_ADDR16,
+};
+
+static struct i2c_board_info __initdata ek_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("24c512", 0x50),
+		.platform_data = &at24c512,
+	},
+	/* more devices can be added using expansion connectors */
+};
+
+
+/* GPIO Buttons */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+	{
+		.gpio		= AT91_PIN_PA30,
+		.code		= BTN_3,
+		.desc		= "Button 3",
+		.active_low	= 1,
+		.wakeup		= 1,
+	},
+	{
+		.gpio		= AT91_PIN_PA31,
+		.code		= BTN_4,
+		.desc		= "Button 4",
+		.active_low	= 1,
+		.wakeup		= 1,
+	}
+};
+
+static struct gpio_keys_platform_data ek_button_data = {
+	.buttons	= ek_buttons,
+	.nbuttons	= ARRAY_SIZE(ek_buttons),
+};
+
+static struct platform_device ek_button_device = {
+	.name		= "gpio-keys",
+	.id		= -1,
+	.num_resources	= 0,
+	.dev		= {
+		.platform_data	= &ek_button_data,
+	}
+};
+
+static void __init ek_add_device_buttons(void)
+{
+	at91_set_gpio_input(AT91_PIN_PA30, 1);	/* btn3 */
+	at91_set_deglitch(AT91_PIN_PA30, 1);
+	at91_set_gpio_input(AT91_PIN_PA31, 1);	/* btn4 */
+	at91_set_deglitch(AT91_PIN_PA31, 1);
+
+	platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
+
+
+static void __init ek_board_init(void)
+{
+	/* Serial */
+	at91_add_device_serial();
+	/* USB Host */
+	at91_add_device_usbh(&ek_usbh_data);
+	/* USB Device */
+	at91_add_device_udc(&ek_udc_data);
+	/* SPI */
+	at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+	/* NAND */
+	ek_add_device_nand();
+	/* Ethernet */
+	at91_add_device_eth(&ek_macb_data);
+	/* MMC */
+	at91_add_device_mmc(0, &ek_mmc_data);
+	/* I2C */
+	at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
+	/* SSC (to AT73C213) */
+	at73c213_set_clk(&at73c213_data);
+	at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
+	/* LEDs */
+	at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+	/* Push Buttons */
+	ek_add_device_buttons();
+}
+
+MACHINE_START(GE863, "Telit GE863-PRO3 Evaluation Kit")
+	/* Maintainer: Telit */
+	.timer		= &at91sam926x_timer,
+	.map_io		= at91_map_io,
+	.init_early	= ek_init_early,
+	.init_irq	= at91_init_irq_default,
+	.init_machine	= ek_board_init,
+MACHINE_END
-- 
1.7.9.4



From r.sricharan at ti.com  Fri Mar 30 04:57:43 2012
From: r.sricharan at ti.com (R Sricharan)
Date: Fri, 30 Mar 2012 14:27:43 +0530
Subject: [PATCH v2] ARM: OMAP2+: Fix omap2+ build error.
Message-ID: <1333097863-7205-1-git-send-email-r.sricharan@ti.com>

With CONFIG_OMAP4_ERRATA_I688 enabled, omap2+ build
was broken as below.

	arch/arm/kernel/io.c: In function '_memcpy_toio':
	arch/arm/kernel/io.c:29: error: implicit declaration of function 'outer_sync'
	make[1]: *** [arch/arm/kernel/io.o] Error 1

after the commit,

	commit 9f97da78bf018206fb623cd351d454af2f105fe0
	Author: David Howells <dhowells at redhat.com>
	Date:   Wed Mar 28 18:30:01 2012 +0100

	    Disintegrate asm/system.h for ARM
    
	    Disintegrate asm/system.h for ARM.

Fixing this here.

Signed-off-by: R Sricharan <r.sricharan at ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/include/asm/barrier.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 44f4a09..0511238 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -2,6 +2,7 @@
 #define __ASM_BARRIER_H
 
 #ifndef __ASSEMBLY__
+#include <asm/outercache.h>
 
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 
@@ -39,7 +40,6 @@
 #ifdef CONFIG_ARCH_HAS_BARRIERS
 #include <mach/barriers.h>
 #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
-#include <asm/outercache.h>
 #define mb()		do { dsb(); outer_sync(); } while (0)
 #define rmb()		dsb()
 #define wmb()		mb()
-- 
1.7.1



From aisheng.dong at freescale.com  Fri Mar 30 05:11:51 2012
From: aisheng.dong at freescale.com (Dong Aisheng)
Date: Fri, 30 Mar 2012 17:11:51 +0800
Subject: [PATCH v3 1/1] ARM: imx28: add basic dt support
In-Reply-To: <20120330085103.GF3254@S2101-09.ap.freescale.net>
References: <1333089130-24832-1-git-send-email-b29396@freescale.com>
 <20120330085103.GF3254@S2101-09.ap.freescale.net>
Message-ID: <20120330091150.GA21517@shlinux2.ap.freescale.net>

On Fri, Mar 30, 2012 at 04:51:06PM +0800, Shawn Guo wrote:
> I tried to apply the patch, but ...
> 
> On Fri, Mar 30, 2012 at 02:32:10PM +0800, Dong Aisheng wrote:
> ...
> > +static int __init mxs_icoll_add_irq_domain(struct device_node *np,
> > +				struct device_node *interrupt_parent)
> > +{
> > +	irq_domain_add_simple(np, 0);
> 
> The irq_domain_add_simple() has been removed from mainline.  You need
> a rebase against Linus' tree.
> 
Will rebase.

> > +static struct sys_timer imx28_timer = {
> > +	.init = imx28_timer_init,
> > +};
> > +
> > +static void __init mxs_machine_init(void)
> > +{
> > +       of_platform_populate(NULL, of_default_bus_match_table,
> 
> Given by checkpatch:
> 
> WARNING: please, no spaces at the start of a line
> #565: FILE: arch/arm/mach-mxs/mach-mxs.c:51:
> +       of_platform_populate(NULL, of_default_bus_match_table,$
> 
Hmm, it seems my checkpatch is out of date.
With new checkpatch i found it.

Regards
Dong Aisheng



From hvaibhav at ti.com  Fri Mar 30 05:12:45 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 30 Mar 2012 09:12:45 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <4F7570FC.8000907@ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
 <4F7570FC.8000907@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>

On Fri, Mar 30, 2012 at 14:08:20, Shilimkar, Santosh wrote:
> On Friday 30 March 2012 02:02 PM, Hiremath, Vaibhav wrote:
> > On Fri, Mar 30, 2012 at 13:11:35, Shilimkar, Santosh wrote:
> >> On Fri, Mar 30, 2012 at 12:04 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >>> On Wed, Mar 28, 2012 at 20:19:07, Shilimkar, Santosh wrote:
> >>>> On Wed, Mar 28, 2012 at 8:07 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >>>>> On Wed, Mar 28, 2012 at 19:50:02, Shilimkar, Santosh wrote:
> >>>>>> On Wed, Mar 28, 2012 at 7:46 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >>>>>>> On Wed, Mar 21, 2012 at 19:30:01, Shilimkar, Santosh wrote:
> >>>>>>>> On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >>>>>>>>> On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
> >>>>>>>>>> On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
> >>>>>>>>>>> On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >>>>>>
> >> [...]
> >>
> >>>> I thought so and now if you look at last part of my comment.
> >>>>
> >>>> Rating of 32K based synctimer and 32K based GPTIMER
> >>>> should be same because of the precision. That's the main
> >>>> point why I was saying that GPTIMER is not a better
> >>>> clock-source( with 32k clock src)  than sync timer when
> >>>> both are enabled together.
> >>>>
> >>>
> >>> Santosh,
> >>>
> >>> In case of OMAP, we are using timer 2 for clocksource
> >>>
> >>> OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
> >>> OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
> >>>
> >>> And timer2 as clocksource is never used, since we have CONFIG_OMAP_32K_TIMER
> >>> defined in our defconfig.
> >>>
> >>> Also, after looking at the code, I came across another problem, setup_sched_clock(). But this can be easily fixed, if we source both the timers with same clock (here 32k_fck).
> >>>
> >>>
> >>> Let me propose this,
> >>>
> >>> How about, if I keep timer2 source always set to 32k_fclk for omap2,3,4?
> >>> And also, as mentioned by Santosh, I will register both the clocks as
> >>> clocksource with the same rating.
> >>> By default, kernel is going to use 32k_counter as a clocksource, and through
> >>> Command prompt user can override it without any issues.
> >>>
> >>> Just to make sure that, whatever I am trying to propse here works and don't get into unknown issue; I changed my code for this, and it is working for me without any issues.
> >>
> >> Let's not make this more complicated. I guess below simple patch should sort
> >> out the issue. I briefly tested it on OMAP4 and it works. let me know
> >> if it helps AMxxx machines.
> >>
> >> Regards
> >> Santosh
> >>
> >> From 0a9283e26174d76ff2753ac88521b61a26b24e8f Mon Sep 17 00:00:00 2001
> >> From: Santosh Shilimkar <santosh.shilimkar at ti.com>
> >> Date: Fri, 30 Mar 2012 12:43:29 +0530
> >> Subject: [PATCH] ARM: OMAP: Make OMAP clocksource source selection runtime.
> >>
> >> Current OMAP code support couple of clocksource options based on compilation
> >> flag. The 32KHz based sync timer and a gptimer based clock source which can
> >> run on 32KHz or system clock (e.g 38.4 MHz). So there can be 3 options.
> >>
> >> 1. 32KHz synctimer
> >> 2. Sysclock based(e.g 38.4 MHz) gptimer
> >> 3. 32KHz based gptimer.
> >>
> >> The optional gptimer based clocksource was added so that it can give the
> >> high precision than synctimer so expected usage was 2 and not 3. Unfortunatlly
> >> option 2, clocksource doesn't meet the requirement of free-running clock
> >> as per clocksource need. It stops in low power states when  sysclock is cut.
> >> That makes gptimer based clocksource option useless for OMAP2/3/4 devices
> >> with sysclock as a clock input. Option 3 will still work but it is no better'
> >> than 32K synctimer based clocksource.
> >>
> >> So ideally we can kill the gptimer based clocksource option but there are some
> >> OMAP based derivative SoCs like AMXXXX which doesn't have synictimer hardware IP
> >> and need to fallback on 32KHz based gptimer clocksource.
> >>
> >> Considering above, make synctimer and gptimer clocksource runtime
> >> selectable so that both OMAP and AMXXXX continue to use the same code.
> >>
> >> Not-yet-signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> >> ---
> >>  arch/arm/mach-omap2/timer.c |   25 ++++++++-----------------
> >>  1 files changed, 8 insertions(+), 17 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> >> index c512bac..3878e59 100644
> >> --- a/arch/arm/mach-omap2/timer.c
> >> +++ b/arch/arm/mach-omap2/timer.c
> >> @@ -234,21 +234,6 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
> >>  }
> >>
> >>  /* Clocksource code */
> >> -
> >> -#ifdef CONFIG_OMAP_32K_TIMER
> >> -/*
> >> - * When 32k-timer is enabled, don't use GPTimer for clocksource
> >> - * instead, just leave default clocksource which uses the 32k
> >> - * sync counter.  See clocksource setup in plat-omap/counter_32k.c
> >> - */
> >> -
> >> -static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
> >> -{
> >> -	omap_init_clocksource_32k();
> >> -}
> >> -
> >> -#else
> >> -
> >>  static struct omap_dm_timer clksrc;
> >>
> >>  /*
> >> @@ -276,7 +261,7 @@ static u32 notrace dmtimer_read_sched_clock(void)
> >>  }
> >>
> >>  /* Setup free-running counter for clocksource */
> >> -static void __init omap2_gp_clocksource_init(int gptimer_id,
> >> +static void __init omap2_gptimer_clocksource_init(int gptimer_id,
> >>  						const char *fck_source)
> >>  {
> >>  	int res;
> >> @@ -295,7 +280,13 @@ static void __init omap2_gp_clocksource_init(int
> >> gptimer_id,
> >>  		pr_err("Could not register clocksource %s\n",
> >>  			clocksource_gpt.name);
> >>  }
> >> -#endif
> >> +
> >> +static void __init omap2_gp_clocksource_init(int gptimer_id,
> >> +                                                const char *fck_source)
> >> +{
> >> +	if (omap_init_clocksource_32k())
> >> +		omap2_gptimer_clocksource_init(gptimer_id, fck_source);
> >> +}
> >>
> > 
> > With this patch, will you be able to choose gptimer as a clocksource
> > using bootparameter (or sysfs) for given kernel uImage?
> > 
> Why do you want that ? Look at changelog. The gptimer based clocksource
> is useless for OMAP and for AM devices synctimer is not available.
> 
> 
> > The answer is simply NO...as the registration of gptimer is based on
> > failure from omap_init_clocksource_32k(). And this is nothing different 
> > than my original patch, my patch exactly does same thing.
> > 
> I ight have missed your original patch. If that patch is similar then
> no problems.
> 
> > The requirement after 'ming Lie' response on my patch was, there will be
> > usecases where we might need to use gptimer for clocksource and with 
> > the patch it is not possible, since you will only register 
> > 32k_counter here.
> > 
> I think Ming Lie might have expected that gptimer clocksource might
> be better which is not the case.
> 
> > So in order to allow user to choose between 32K and gptimer, you must 
> > register both and make 32k as a default thing.
> > 
> As described in the commit log, its not needed at all. Let's not add
> a feature which is just useless because the gptimer based clock
> source has no advantage against the syntimer.
> 

I completely agree with you, and that is my understanding too.

After Ming Lie's comment, the point that I came to my mind was,
certainly there will be resolution difference between these two clocksources,
if  gptimer2 is sourced from sys_ck (26Mhz).

I am quite not sure, whether will there be any practical usecase where you
change the kernel clocksource for high resolution dynamically through sysfs 
or something. May be not....but still it is possible.


In that case my original patch still holds good here. I would still request
you to review the same and give your acked-by  or tested-by.


Thanks,
Vaibhav 



From santosh.shilimkar at ti.com  Fri Mar 30 05:20:02 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 30 Mar 2012 14:50:02 +0530
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
 <4F7570FC.8000907@ti.com>
 <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>
Message-ID: <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>

On Fri, Mar 30, 2012 at 2:42 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> On Fri, Mar 30, 2012 at 14:08:20, Shilimkar, Santosh wrote:
>> On Friday 30 March 2012 02:02 PM, Hiremath, Vaibhav wrote:
>> > On Fri, Mar 30, 2012 at 13:11:35, Shilimkar, Santosh wrote:

[....]

>> >
>> > With this patch, will you be able to choose gptimer as a clocksource
>> > using bootparameter (or sysfs) for given kernel uImage?
>> >
>> Why do you want that ? Look at changelog. The gptimer based clocksource
>> is useless for OMAP and for AM devices synctimer is not available.
>>
>>
>> > The answer is simply NO...as the registration of gptimer is based on
>> > failure from omap_init_clocksource_32k(). And this is nothing different
>> > than my original patch, my patch exactly does same thing.
>> >
>> I ight have missed your original patch. If that patch is similar then
>> no problems.
>>
>> > The requirement after 'ming Lie' response on my patch was, there will be
>> > usecases where we might need to use gptimer for clocksource and with
>> > the patch it is not possible, since you will only register
>> > 32k_counter here.
>> >
>> I think Ming Lie might have expected that gptimer clocksource might
>> be better which is not the case.
>>
>> > So in order to allow user to choose between 32K and gptimer, you must
>> > register both and make 32k as a default thing.
>> >
>> As described in the commit log, its not needed at all. Let's not add
>> a feature which is just useless because the gptimer based clock
>> source has no advantage against the syntimer.
>>
>
> I completely agree with you, and that is my understanding too.
>
Thanks !!

> After Ming Lie's comment, the point that I came to my mind was,
> certainly there will be resolution difference between these two clocksources,
> if ?gptimer2 is sourced from sys_ck (26Mhz).
>
GPTIMER2 with sysclock is not an option. GPTIMER is not in wakeup domain
and when sysclock is cut, it stops.

> I am quite not sure, whether will there be any practical usecase where you
> change the kernel clocksource for high resolution dynamically through sysfs
> or something. May be not....but still it is possible.
>
Even if there is a usecase, there no option with full PM.

>
> In that case my original patch still holds good here. I would still request
> you to review the same and give your acked-by ?or tested-by.
>
I just looked at that.
It looks fine to me. Can you repost that patch addressing Kevin and
Tony's comments.
Also update the change log as describe in the patch i posted.

Once that done, will ack it.

Regards
Santosh


From hvaibhav at ti.com  Fri Mar 30 05:28:08 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 30 Mar 2012 09:28:08 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
 <4F7570FC.8000907@ti.com>
 <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>
 <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831841009@DBDE01.ent.ti.com>

On Fri, Mar 30, 2012 at 14:50:02, Shilimkar, Santosh wrote:
> On Fri, Mar 30, 2012 at 2:42 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> > On Fri, Mar 30, 2012 at 14:08:20, Shilimkar, Santosh wrote:
> >> On Friday 30 March 2012 02:02 PM, Hiremath, Vaibhav wrote:
> >> > On Fri, Mar 30, 2012 at 13:11:35, Shilimkar, Santosh wrote:
> 
> [....]
> 
> >> >
> >> > With this patch, will you be able to choose gptimer as a clocksource
> >> > using bootparameter (or sysfs) for given kernel uImage?
> >> >
> >> Why do you want that ? Look at changelog. The gptimer based clocksource
> >> is useless for OMAP and for AM devices synctimer is not available.
> >>
> >>
> >> > The answer is simply NO...as the registration of gptimer is based on
> >> > failure from omap_init_clocksource_32k(). And this is nothing different
> >> > than my original patch, my patch exactly does same thing.
> >> >
> >> I ight have missed your original patch. If that patch is similar then
> >> no problems.
> >>
> >> > The requirement after 'ming Lie' response on my patch was, there will be
> >> > usecases where we might need to use gptimer for clocksource and with
> >> > the patch it is not possible, since you will only register
> >> > 32k_counter here.
> >> >
> >> I think Ming Lie might have expected that gptimer clocksource might
> >> be better which is not the case.
> >>
> >> > So in order to allow user to choose between 32K and gptimer, you must
> >> > register both and make 32k as a default thing.
> >> >
> >> As described in the commit log, its not needed at all. Let's not add
> >> a feature which is just useless because the gptimer based clock
> >> source has no advantage against the syntimer.
> >>
> >
> > I completely agree with you, and that is my understanding too.
> >
> Thanks !!
> 
> > After Ming Lie's comment, the point that I came to my mind was,
> > certainly there will be resolution difference between these two clocksources,
> > if ?gptimer2 is sourced from sys_ck (26Mhz).
> >
> GPTIMER2 with sysclock is not an option. GPTIMER is not in wakeup domain
> and when sysclock is cut, it stops.
> 
> > I am quite not sure, whether will there be any practical usecase where you
> > change the kernel clocksource for high resolution dynamically through sysfs
> > or something. May be not....but still it is possible.
> >
> Even if there is a usecase, there no option with full PM.
> 

What if before suspending the system, you switch back to 32k_counter 
everytime, and in resume you again switch to gp_timer?

Please consider this as just a technical discussion, as I am myself quite 
not sure whether we have such use-case available.

> >
> > In that case my original patch still holds good here. I would still request
> > you to review the same and give your acked-by ?or tested-by.
> >
> I just looked at that.
> It looks fine to me. Can you repost that patch addressing Kevin and
> Tony's comments.
> Also update the change log as describe in the patch i posted.
> 
> Once that done, will ack it.
> 

Thanks for the review and discussion, I will submit revised version shortly.


Thanks,
Vaibhav



From broonie at opensource.wolfsonmicro.com  Fri Mar 30 05:35:56 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 30 Mar 2012 10:35:56 +0100
Subject: [PATCH] ARM: S3C64XX: Add basic cpuidle driver
In-Reply-To: <201203301032.54739.heiko@sntech.de>
References: <1323117169-9817-1-git-send-email-broonie@opensource.wolfsonmicro.com>
 <201112061231.22570.heiko@sntech.de>
 <20111222181359.GA19259@sirena.org.uk>
 <201203301032.54739.heiko@sntech.de>
Message-ID: <20120330093556.GA21950@opensource.wolfsonmicro.com>

On Fri, Mar 30, 2012 at 10:32:54AM +0200, Heiko St?bner wrote:
> Am Donnerstag, 22. Dezember 2011, 19:13:59 schrieb Mark Brown:

> > My plan there for the s3c64xx was to use pm_domain to figure out if the
> > system is idle enough to drop down, I've been adding some pm_runtime
> > support to provide the information to the core to let it figure this out.

> sorry for digging this up again, but do you happen to have some preliminary 
> code laying around for this, that I could "borrow"?

No, sorry.  The big problem is putting all the devices in power domains
since the Samsung port always has every single machine driver directly
register devices.  Until that problem is solved it's not possible to
figure out if we're idle.
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From santosh.shilimkar at ti.com  Fri Mar 30 05:42:19 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Fri, 30 Mar 2012 15:12:19 +0530
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A831841009@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
 <4F7570FC.8000907@ti.com>
 <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>
 <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831841009@DBDE01.ent.ti.com>
Message-ID: <CAMQu2gyktrAhtTYViYfb9nQ7g8UB1btGFkmd7aLD+Kt4r8y9WQ@mail.gmail.com>

On Fri, Mar 30, 2012 at 2:58 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> On Fri, Mar 30, 2012 at 14:50:02, Shilimkar, Santosh wrote:
>> On Fri, Mar 30, 2012 at 2:42 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>> > On Fri, Mar 30, 2012 at 14:08:20, Shilimkar, Santosh wrote:
>> >> On Friday 30 March 2012 02:02 PM, Hiremath, Vaibhav wrote:
>> >> > On Fri, Mar 30, 2012 at 13:11:35, Shilimkar, Santosh wrote:
>>
>> [....]
>>
>> >> >
>> >> > With this patch, will you be able to choose gptimer as a clocksource
>> >> > using bootparameter (or sysfs) for given kernel uImage?
>> >> >
>> >> Why do you want that ? Look at changelog. The gptimer based clocksource
>> >> is useless for OMAP and for AM devices synctimer is not available.
>> >>
>> >>
>> >> > The answer is simply NO...as the registration of gptimer is based on
>> >> > failure from omap_init_clocksource_32k(). And this is nothing different
>> >> > than my original patch, my patch exactly does same thing.
>> >> >
>> >> I ight have missed your original patch. If that patch is similar then
>> >> no problems.
>> >>
>> >> > The requirement after 'ming Lie' response on my patch was, there will be
>> >> > usecases where we might need to use gptimer for clocksource and with
>> >> > the patch it is not possible, since you will only register
>> >> > 32k_counter here.
>> >> >
>> >> I think Ming Lie might have expected that gptimer clocksource might
>> >> be better which is not the case.
>> >>
>> >> > So in order to allow user to choose between 32K and gptimer, you must
>> >> > register both and make 32k as a default thing.
>> >> >
>> >> As described in the commit log, its not needed at all. Let's not add
>> >> a feature which is just useless because the gptimer based clock
>> >> source has no advantage against the syntimer.
>> >>
>> >
>> > I completely agree with you, and that is my understanding too.
>> >
>> Thanks !!
>>
>> > After Ming Lie's comment, the point that I came to my mind was,
>> > certainly there will be resolution difference between these two clocksources,
>> > if ?gptimer2 is sourced from sys_ck (26Mhz).
>> >
>> GPTIMER2 with sysclock is not an option. GPTIMER is not in wakeup domain
>> and when sysclock is cut, it stops.
>>
>> > I am quite not sure, whether will there be any practical usecase where you
>> > change the kernel clocksource for high resolution dynamically through sysfs
>> > or something. May be not....but still it is possible.
>> >
>> Even if there is a usecase, there no option with full PM.
>>
>
> What if before suspending the system, you switch back to 32k_counter
> everytime, and in resume you again switch to gp_timer?
>
This has been discussed at length. Dynamic switching between
clock-sources affects the NTP time corrections. Go through [1]
when you have time, since its a long thread.

If and when that feature works, we can update the clocksource
code.

Regards
Santosh

[1]  https://lkml.org/lkml/2011/6/2/167


From u.kleine-koenig at pengutronix.de  Fri Mar 30 05:50:24 2012
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 30 Mar 2012 11:50:24 +0200
Subject: [PATCH 03/17] ARM: mark const init data with __initconst instead
 of __initdata
In-Reply-To: <20120330061134.GD3254@S2101-09.ap.freescale.net>
References: <20120329211131.GA31250@pengutronix.de>
 <1333055554-31300-3-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120330061134.GD3254@S2101-09.ap.freescale.net>
Message-ID: <20120330095024.GS15647@pengutronix.de>

Hello Shawn,

On Fri, Mar 30, 2012 at 02:11:36PM +0800, Shawn Guo wrote:
> On Thu, Mar 29, 2012 at 11:12:20PM +0200, Uwe Kleine-K?nig wrote:
> ...
> > diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
> > index 5cca573..7e00748 100644
> > --- a/arch/arm/mach-imx/imx51-dt.c
> > +++ b/arch/arm/mach-imx/imx51-dt.c
> > @@ -102,7 +102,7 @@ static struct sys_timer imx51_timer = {
> >  	.init = imx51_timer_init,
> >  };
> >  
> > -static const char *imx51_dt_board_compat[] __initdata = {
> > +static const char *imx51_dt_board_compat[] __initconst = {
> >  	"fsl,imx51-babbage",
> >  	"fsl,imx51",
> >  	NULL
> 
>   CC      arch/arm/mach-imx/imx51-dt.o
> arch/arm/mach-imx/imx51-dt.c:105:20: error: imx51_dt_board_compat causes a section type conflict
> make[2]: *** [arch/arm/mach-imx/imx51-dt.o] Error 1
> 
> I do not understand why though.
that's because the strings are constant, but the array is not. The fix
is:

-static const char *imx51_dt_board_compat[] __initconst = {
+static const char *const imx51_dt_board_compat[] __initconst = {

or keeping __initdata.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From broonie at opensource.wolfsonmicro.com  Fri Mar 30 06:07:42 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 30 Mar 2012 11:07:42 +0100
Subject: [PATCH v6 1/5] Extcon (external connector): import Android's
 switch class and modify.
In-Reply-To: <CACSP8ShU5tu=9N53PtYMLyFVFMS9whNRhMvu7nu8rBoPuVCy+Q@mail.gmail.com>
References: <1328856038-21912-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-2-git-send-email-myungjoo.ham@samsung.com>
 <20120309124119.GV3273@opensource.wolfsonmicro.com>
 <CACSP8ShU5tu=9N53PtYMLyFVFMS9whNRhMvu7nu8rBoPuVCy+Q@mail.gmail.com>
Message-ID: <20120330100742.GB21950@opensource.wolfsonmicro.com>

On Thu, Mar 29, 2012 at 03:27:01PM -0700, Erik Gilling wrote:
> On Fri, Mar 9, 2012 at 4:41 AM, Mark Brown
> <broonie at opensource.wolfsonmicro.com> wrote:
> > On Mon, Feb 27, 2012 at 09:15:35PM +0900, MyungJoo Ham wrote:

> >> +#ifdef CONFIG_ANDROID
> >> + ? ? ? ? ? ? extcon_class = class_create(THIS_MODULE, "switch");
> >> +#else /* !CONFIG_ANDROID */
> >> + ? ? ? ? ? ? extcon_class = class_create(THIS_MODULE, "extcon");
> >> +#endif /* CONFIG_ANDROID */

> > This seems somewhat sad - if ANDROID is turned on the standard ABI
> > vanishes. ?It'd be much nicer to do this with a symlink (or with
> > symlinks within the android directory if the driver core doesn't support
> > that). ?That way userspace code can be written to the new ABI and will
> > work on Android systems without ifdefery.

> This won't work if userspace code is receiving uevents through netlink
> and comparing based on the device name which it does in android.  Why

That's not really the point here - the point is that the new ABI
vanishes as soon as you turn on the legacy Android ABI.  You're right
that the particular fix I suggested has issues but the overall problem
exists and should be dealt with more sensibly.

> change the name at all?  Extcon is much more specific than "switch."
> A switch can can be used for more than just external connections such
> as availability of HMDI audio (which is only available once a HDMI
> mode is chosen and the interface is enabled.)

I don't know myself, it was called extcon when first proposed for
mainline.  Renaming does have the advantage of indicating to userspace
that this is the mainline, reviewed version and that things might be a
bit different as a result of that review.

Things like the HDMI audio example you cite do seem close enough to the
term to still be useful, they're related to an external connection and
it's state.  If you were really worrying about it you might expect HDMI
audio to be reported via something like the ALSA APIs rather than a
totally unrelated ABI like this.
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From prylowski at metasoft.pl  Fri Mar 30 06:13:45 2012
From: prylowski at metasoft.pl (Rafal Prylowski)
Date: Fri, 30 Mar 2012 12:13:45 +0200
Subject: [PATCH 1/3] PATA host controller driver for ep93xx
In-Reply-To: <4F74E058.3010607@gmail.com>
References: <4F7418E7.4060500@metasoft.pl> <4F741AB1.4000107@metasoft.pl>
 <4F74E058.3010607@gmail.com>
Message-ID: <4F758759.9090007@metasoft.pl>

On 2012-03-30 00:21, Ryan Mallon wrote:

>> +#include <mach/ep93xx-regs.h>
> 
> 
> ep93xx-regs.h is now deprecated for inclusion in drivers :-).

Will remove.

>> +enum {
>> +	/* IDE Control Register */
>> +	IDECtrl				= 0x00,
> 
> 
> Please don't use horrible camel case names.

I used these because it's original naming from EP93xx User's Guide.
It's easier to write code and compare with this document. But if it's not
allowed I could easily change it.

>> +	IDECtrl_CS0n			= (1 << 0),
>> +	IDECtrl_CS1n			= (1 << 1),
>> +	IDECtrl_DIORn			= (1 << 5),
>> +	IDECtrl_DIOWn			= (1 << 6),
>> +	IDECtrl_INTRQ			= (1 << 9),
>> +	IDECtrl_IORDY			= (1 << 10),
>> +
>> +	/* IDE Configuration Register */
>> +	IDECfg				= 0x04,
>> +	IDECfg_IDEEN			= (1 << 0),
> 
> 
> Why is this one enum, when you have multiple constants which define to
> the same value? This probably makes more sense as a set of defines.

In previous versions I had these as a set of defines. But I noticed, that
in the driver from Bartlomiej Zolnierkiewicz enum is used (in some other
libata drivers too). Isn't it better to avoid using of preprocessor
where possible?

>> +	const struct ata_timing *t, *cmd_t;
> 
> 
> Nitpick: Usually each field in a structure definition is on its own line.

Ok. Will do.

>> +static void ep93xx_pata_clear_regs(void __iomem *base)
>> +{
>> +	writel(IDECtrl_CS0n | IDECtrl_CS1n | IDECtrl_DIORn |
>> +		IDECtrl_DIOWn, base + IDECtrl);
>> +
>> +	writel(0, base + IDECfg);
> 
> 
> Might be worth having ep93xx_pata_write/read functions so you don't have
> to do the base + thing everywhere. Passing struct ep93xx_pata_data to
> each function would be more typical also.

I'll try to do it and see if it helps to simplify driver.

>> +static inline int ep93xx_pata_check_iordy(void __iomem *base)
>> +{
>> +	return (readl(base + IDECtrl) & IDECtrl_IORDY) ? 1 : 0;
> 
> 
> You can use !! here rather than ? 1 : 0.

Ok.

>> +static inline int ep93xx_pata_get_wst(int pio_mode)
>> +{
>> +	return (pio_mode == 0 ? 3 : pio_mode < 3 ? 2 : 1)
>> +		<< IDECfg_WST_SHIFT;
> 
> 
> Ick, thats really hard to read. What's wrong with:
> 
>   unsigned val = 1;
> 
>   if (pio_mode == 0)
>   	val = 3;
>   else if (pio_mode < 3)
>   	val = 2;
>   else
> 	val = 1;
> 
>   return val << IDECFG_WST_SHIFT;

Yes, it's much simplier (at first I wrote exactly your version, but "optimized"
it later ;) ). Will chage.

>> +static inline void ep93xx_pata_enable_pio(void __iomem *base, int pio_mode)
> 
> 
> Don't bother marking functions inline. The compiler will do it for you.

Ok.

>> +	if (drv_data->iordy) {
>> +		/* min. 1s timeout (at cpu cycle = 5ns) */
>> +		unsigned int timeout = 200000;
> 
> 
> Probably be better to use jiffies, msecs_to_jiffies and
> time_before/after rather than relying on a particular clock speed.

Yes! This is much better solution IMHO. Will try to do that.

>> +		while (!ep93xx_pata_check_iordy(base) && --timeout)
>> +			cpu_relax();

>> +	if (drv_data->iordy) {
>> +		/* min. 1s timeout */
>> +		unsigned int timeout = 200000;
>> +		while (!ep93xx_pata_check_iordy(base) && --timeout)
>> +			cpu_relax();
> 
> 
> This loop is used more than once. Wrap it up in a function maybe.

Ok.

>> +		VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
>> +			tf->hob_feature, tf->hob_nsect, tf->hob_lbal,
>> +			tf->hob_lbam, tf->hob_lbah);
> 
> 
>   dev_vdbg(ap->host->dev, ...)
> 
> ? Same elsewhere.

It's original code from libata (printing is enabled by ATA_DEBUG,
ATA_VERBOSE_DEBUG). Don't know if we could just change that.

>> +	DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
> 
> 
>   dev_dbg(ap->host->dev, ...);

Ditto.

>> +	if (device == 0)
>> +		tmp = ATA_DEVICE_OBS;
>> +	else
>> +		tmp = ATA_DEVICE_OBS | ATA_DEV1;
> 
> 
> This could be:
> 
>   u8 tmp = ATA_DEVICE_OBS;
> 
>   ...
> 
>   if (device != 0)
>   	tmp |= ATA_DEV1;

This is also from original libata code. I'll change this, as I like your
version more.

>> +	u16 *data = (u16 *) buf;
> 
> 
> No space after the cast.

Ok.

>> +	/* Transfer multiple of 2 bytes */
>> +	if (rw == READ)
>> +		while (words--)
>> +			*data++ = cpu_to_le16(
>> +				ep93xx_pata_read(drv_data, data_addr, t));
>> +	else
>> +		while (words--)
>> +			ep93xx_pata_write(drv_data, le16_to_cpu(*data++),
>> +				data_addr, t);
> 
> 
> This would would be a bit simpler as:
> 
>   while (words--) {
>   	if (rw == READ)
> 		*data++ = ...;
> 	else
> 		ep93xx_pata_write(...);
>   }

Ok. Will change.

>> +
>> +	if ((nsect == 0x55) && (lbal == 0xaa))
>> +		return 1;	/* we found a device */
>> +
>> +	return 0;		/* nothing found */
> 
> 
> This function should return a bool. Maybe also change the function name
> to ep93xx_pata_device_is_present, which more accurately reflects what
> this does. Then you can drop the comments above too.

This is based on original code from libata, but I think we could change
it according to your suggestion (this function is not used as a hook
anywhere, it's only called from ep93xx_pata_softreset). Will do that.

>> +	/* if device 1 was found in ata_devchk, wait for register
>> +	 * access briefly, then wait for BSY to clear.
>> +	 */
> 
> 
>   /*
>    * Mutli-line comment style
>    * looks like this.
>    */

Original libata code. I preferred to change as little as possible in this
driver, that's why I left it as is. Will correct.

>> +	if (!txd) {
>> +		dev_err(qc->ap->dev, "failed to prepare slave for sg dma\n");
>> +		BUG();
> 
> 
> Don't BUG in drivers if you can possibly avoid it. Set an error state
> and try to bail out gracefully.

I think that changing BUG() to "return" is reasonable, as I don't know
any possibility to inform libata core about failed .bmdma_setup or .bmdma_start
(also explained in reply to Hartley).

>> +	ioaddr->cmd_addr	= (void __iomem *) 0 + 2; /* CS1 */
>> +
>> +	ioaddr->data_addr	= (void __iomem *) (ATA_REG_DATA << 2) + 2;
>> +	ioaddr->error_addr	= (void __iomem *) (ATA_REG_ERR << 2) + 2;
>> +	ioaddr->feature_addr	= (void __iomem *) (ATA_REG_FEATURE << 2) + 2;
>> +	ioaddr->nsect_addr	= (void __iomem *) (ATA_REG_NSECT << 2) + 2;
>> +	ioaddr->lbal_addr	= (void __iomem *) (ATA_REG_LBAL << 2) + 2;
>> +	ioaddr->lbam_addr	= (void __iomem *) (ATA_REG_LBAM << 2) + 2;
>> +	ioaddr->lbah_addr	= (void __iomem *) (ATA_REG_LBAH << 2) + 2;
>> +	ioaddr->device_addr	= (void __iomem *) (ATA_REG_DEVICE << 2) + 2;
>> +	ioaddr->status_addr	= (void __iomem *) (ATA_REG_STATUS << 2) + 2;
>> +	ioaddr->command_addr	= (void __iomem *) (ATA_REG_CMD << 2) + 2;
>> +
>> +	ioaddr->altstatus_addr	= (void __iomem *) (0x06 << 2) + 1; /* CS0 */
>> +	ioaddr->ctl_addr	= (void __iomem *) (0x06 << 2) + 1; /* CS0 */
> 
> 
> Only a couple of other pata driver appears to do this horrible casting
> mess. Other drivers appear to be using (devm_ioremap). Can we clean this up?

I wrote about solution with static table of these values in reply to Hartley
(I think we could avoid using this ioaddr->... everywhere in case of ep93xx).
Maybe enums can be used?

>> +	/*if (readl(EP93XX_SYSCON_DEVCFG) & (EP93XX_SYSCON_DEVCFG_EONIDE
>> +		| EP93XX_SYSCON_DEVCFG_GONIDE | EP93XX_SYSCON_DEVCFG_HONIDE)) {
>> +		dev_err(&pdev->dev, "IDE/GPIO pin conflict\n");
>> +		return -EINVAL;
>> +	}*/
> 
> 
> Fix or remove.

Will be removed.


Thanks for thorough review.

Regards,
RP


From broonie at opensource.wolfsonmicro.com  Fri Mar 30 06:14:15 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 30 Mar 2012 11:14:15 +0100
Subject: [PATCH v6 1/5] Extcon (external connector): import Android's
 switch class and modify.
In-Reply-To: <CAJ0PZbT728rhQ5esf0arRw-TtgBGMCgAvZhW9-AejmbT9WOahw@mail.gmail.com>
References: <1328856038-21912-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-2-git-send-email-myungjoo.ham@samsung.com>
 <20120309124119.GV3273@opensource.wolfsonmicro.com>
 <CACSP8ShU5tu=9N53PtYMLyFVFMS9whNRhMvu7nu8rBoPuVCy+Q@mail.gmail.com>
 <CAJ0PZbT728rhQ5esf0arRw-TtgBGMCgAvZhW9-AejmbT9WOahw@mail.gmail.com>
Message-ID: <20120330101414.GC21950@opensource.wolfsonmicro.com>

On Fri, Mar 30, 2012 at 05:56:01PM +0900, MyungJoo Ham wrote:

> With class_compat as in patchset v7, (this thread is w/ v6) does the
> issue (missing link from device name directory) still exist? (I don't
> think so)

Not unless the uevents are issued with both names.
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From broonie at opensource.wolfsonmicro.com  Fri Mar 30 06:18:00 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 30 Mar 2012 11:18:00 +0100
Subject: [PATCH v5 04/16] pwm: Add table-based lookup for static mappings
In-Reply-To: <20120330050641.GA21823@avionic-0098.mockup.avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-5-git-send-email-thierry.reding@avionic-design.de>
 <20120329220342.GK4153@opensource.wolfsonmicro.com>
 <20120330050641.GA21823@avionic-0098.mockup.avionic-design.de>
Message-ID: <20120330101800.GD21950@opensource.wolfsonmicro.com>

On Fri, Mar 30, 2012 at 07:06:41AM +0200, Thierry Reding wrote:
> * Mark Brown wrote:

> > The clock and regulator APIs namespace the consumers by struct device -
> > might this not be sensible here?  pwm_get() does already take the device
> > as an argument.  It'd feel safer, and for example there's plenty of
> > phones out there with two backlit displays...

> That's actually how this is supposed to work. "pwm-backlight" in the above
> case is matched against the name of the struct device that you pass in to
> pwm_get(). The only difference, at least as far as I can tell, to the clock
> and regulator APIs is that a second name is not listed explicitly in the
> lookup table.

Both clock and regulator APIs map (source) -> (dev, name).  This only
has a mapping (source) -> (dev).

> So compared with the clock and regulator APIs it doesn't make too much sense
> to pass both the struct device and the name to pwm_get() because it will
> match the device name against the consumer name in the lookup table first and
> only use the passed name if no match was found.

This is different to what the clock and regulator APIs do - they look up
the name in the context of the struct device.  This is because...

> In case you have two backlight devices I would expect the following to work:

> 	static struct pwm_lookup board_pwm_lookup[] = {
> 		PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight.0"),
> 		PWM_LOOKUP("tegra-pwm", 1, "pwm-backlight.1"),
> 	};

...if a single device uses more than one PWM then the above scheme won't
work - unless I'm missing something?
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From thierry.reding at avionic-design.de  Fri Mar 30 06:38:40 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Fri, 30 Mar 2012 12:38:40 +0200
Subject: [PATCH v5 04/16] pwm: Add table-based lookup for static mappings
In-Reply-To: <20120330101800.GD21950@opensource.wolfsonmicro.com>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-5-git-send-email-thierry.reding@avionic-design.de>
 <20120329220342.GK4153@opensource.wolfsonmicro.com>
 <20120330050641.GA21823@avionic-0098.mockup.avionic-design.de>
 <20120330101800.GD21950@opensource.wolfsonmicro.com>
Message-ID: <20120330103840.GB961@avionic-0098.mockup.avionic-design.de>

* Mark Brown wrote:
> On Fri, Mar 30, 2012 at 07:06:41AM +0200, Thierry Reding wrote:
> > * Mark Brown wrote:
> 
> > > The clock and regulator APIs namespace the consumers by struct device -
> > > might this not be sensible here?  pwm_get() does already take the device
> > > as an argument.  It'd feel safer, and for example there's plenty of
> > > phones out there with two backlit displays...
> 
> > That's actually how this is supposed to work. "pwm-backlight" in the above
> > case is matched against the name of the struct device that you pass in to
> > pwm_get(). The only difference, at least as far as I can tell, to the clock
> > and regulator APIs is that a second name is not listed explicitly in the
> > lookup table.
> 
> Both clock and regulator APIs map (source) -> (dev, name).  This only
> has a mapping (source) -> (dev).
> 
> > So compared with the clock and regulator APIs it doesn't make too much sense
> > to pass both the struct device and the name to pwm_get() because it will
> > match the device name against the consumer name in the lookup table first and
> > only use the passed name if no match was found.
> 
> This is different to what the clock and regulator APIs do - they look up
> the name in the context of the struct device.  This is because...
> 
> > In case you have two backlight devices I would expect the following to work:
> 
> > 	static struct pwm_lookup board_pwm_lookup[] = {
> > 		PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight.0"),
> > 		PWM_LOOKUP("tegra-pwm", 1, "pwm-backlight.1"),
> > 	};
> 
> ...if a single device uses more than one PWM then the above scheme won't
> work - unless I'm missing something?

Right, now it makes more sense. So basically if I have a single device using
two PWM devices, then I'll need to have something like this:

	static struct pwm_lookup board_pwm_lookup[] = {
		PWM_LOOKUP("tegra-pwm", 0, "pwm-foo.0", "bar"),
		PWM_LOOKUP("tegra-pwm", 1, "pwm-foo.0", "baz"),
	};

And then of course I'll need to have a second field by which the PWM device
can be identified. Good, I'll fix that up for the next round.

Thierry
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From lost.distance at yahoo.com  Fri Mar 30 06:41:33 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 30 Mar 2012 11:41:33 +0100 (BST)
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <CAN1soZwzBqDGTX+a-maVr5baaoZ7qwgdvXyPeya5R80cN_iA0w@mail.gmail.com>
Message-ID: <1333104093.65224.YahooMailClassic@web29002.mail.ird.yahoo.com>

--- On Fri, 30/3/12, Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
> On Thu, Mar 29, 2012 at 2:12 AM, Paul
> Parsons <lost.distance at yahoo.com>
> wrote:
> > On PXA2xx platforms, the MFP API (described in
> Documentation/arm/pxa/mfp.txt)
> > provides values for the following:
> >
> > 1. GPIO inputs (e.g. GPIO105_GPIO).
> > 2. Alternate function inputs (e.g. GPIO105_CIF_DD_1).
> > 3. Alternate function outputs (e.g.
> GPIO105_KP_MKOUT_2).
> >
> > It does not provide values for GPIO outputs (i.e. AF0
> outputs).
> >
> > One cannot use the macro used by the MFP API internally
> - MFP_CFG_OUT() - to
> > define new GPIO output values, since that macro is
> forbidden in platform code.
> >
> > Without the ability to add GPIO outputs to the MFP
> configuration, it is not
> > possible to drive GPIO outputs high during sleep mode.
> >
> > This would be useful, for example, on the hx4700
> platform, where driving the
> > infrared powerdown GPIO 105 high during sleep mode
> would save some mA.
> >
> > So my question is: what method should one use to add
> GPIO outputs to the MFP
> > configuration?
> >
> > One possible method, namely manually defining values in
> the platform code:
> >
> > ? ? ? ?MFP_PIN_GPIO105 | MFP_AF0 | MFP_DIR_OUT |
> MFP_LPM_DRIVE_HIGH,
> >
> > is essentially no different from using the forbidden
> MFP_CFG_OUT() macro.
> >
> 
> Does MFP_CFG_OUT() help you? This macro is defined in
> mfp-pxa2xx.h.

Yes, MFP_CFG_OUT() does help. But it has been pointed out that
MFP_CFG_OUT() is not allowed to be used in board support code:

http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086456.html

Is that no longer true?


From milamzonne at 21cn.com  Fri Mar 30 07:12:42 2012
From: milamzonne at 21cn.com (milamzonne at 21cn.com)
Date: Fri, 30 Mar 2012 19:12:42 +0800 (CST)
Subject: =?UTF-8?B?bGludXgtYXJtLWtlcm5lbO+8jA==?=
 =?UTF-8?B?5L2/55So5aW556ys5LiA5aSp77yM572R?=
 =?UTF-8?B?56uZ55qE6K6/6Zeu6YeP5bCx5aKe5Yqg5LqG?=
Message-ID: <3413115.16991333105963180.JavaMail.root@webmail4>

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From grinberg at compulab.co.il  Fri Mar 30 07:25:50 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Fri, 30 Mar 2012 14:25:50 +0300
Subject: [PATCH] ARM: pxa: fix build failure for regulator consumer in
 em-x270.c
In-Reply-To: <4F7477CB.5070206@windriver.com>
References: <CAP=VYLp-weNj35OHtmZ6pf5-t7OUxWREeu8r5sSOLhFYu0CppQ@mail.gmail.com>
 <1331244366-6147-1-git-send-email-paul.gortmaker@windriver.com>
 <4F732C97.2030804@compulab.co.il>
 <20120328152743.GW3232@opensource.wolfsonmicro.com>
 <4F73356D.5080401@windriver.com>
 <20120328161305.GZ3232@opensource.wolfsonmicro.com>
 <4F73437B.6070806@windriver.com> <4F7471A0.6070208@compulab.co.il>
 <4F7477CB.5070206@windriver.com>
Message-ID: <4F75983E.8070109@compulab.co.il>

On 03/29/12 16:55, Paul Gortmaker wrote:
> On 12-03-29 10:28 AM, Igor Grinberg wrote:
>> On 03/28/12 18:59, Paul Gortmaker wrote:
>>> On 12-03-28 12:13 PM, Mark Brown wrote:
>>>> On Wed, Mar 28, 2012 at 11:59:41AM -0400, Paul Gortmaker wrote:
>>>>> On 12-03-28 11:27 AM, Mark Brown wrote:
>>>>
>>>>> static struct platform_device em_x270_gps_userspace_consumer = {
>>>>>         .name           = "reg-userspace-consumer",
>>>>>         .id             = 0,
>>>>
>>>>> static struct platform_device em_x270_gprs_userspace_consumer = {
>>>>>         .name           = "reg-userspace-consumer",
>>>>>         .id             = 1,
>>>>
>>>>> Note that the existing names currently don't incorporate the .id
>>>>> field as a suffix, and so never were unique.
>>>>
>>>> No, this is just a basic part of how platform devices work - the device
>>>> name is always the same and if you've got more than one of them they get
>>>> different .ids.  dev_name() returns name.id, or just name if id is set
>>>> to -1 indicating that there's onyl one device of a given type.
>>>
>>> OK, so Igor - can you simply retest the v2 patch, but make the
>>> two trivial changes:
>>>
>>> -REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer", "vcc gps");
>>> +REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer.0", "vcc gps");
>>>
>>> -REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer", "vcc gprs");
>>> +REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer.1", "vcc gprs");
>>
>> Well, I thought of this solution, but I don't like it, as it makes
>> the whole thing very fragile and sensitive to the reg-userspace-consumer
>> platform device registration order and count, isn't it?
> 
> Why would it be order dependent?  You can see in the above structs
> that they explicitly call out an ID value -- it is _not_ chosen at
> the time of registration.  So it will always be:
> 
> reg-userspace-consumer.0  -->  gps consumer
> reg-userspace-consumer.1  -->  gprs consumer
> 
> At least that is my (limited) understanding, based on what
> Mark was saying.

The problem is, that someone has to stop sending emails in a hurry...
Spitting all the mix in the head when in rush...
and that would be me...

Sorry, for the mess, I'll try to fix myself up...

-- 
Regards,
Igor.


From shawn.guo at linaro.org  Fri Mar 30 07:25:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 30 Mar 2012 19:25:56 +0800
Subject: [PATCH 03/17] ARM: mark const init data with __initconst instead
 of __initdata
In-Reply-To: <20120330095024.GS15647@pengutronix.de>
References: <20120329211131.GA31250@pengutronix.de>
 <1333055554-31300-3-git-send-email-u.kleine-koenig@pengutronix.de>
 <20120330061134.GD3254@S2101-09.ap.freescale.net>
 <20120330095024.GS15647@pengutronix.de>
Message-ID: <20120330112554.GG3254@S2101-09.ap.freescale.net>

On Fri, Mar 30, 2012 at 11:50:24AM +0200, Uwe Kleine-K?nig wrote:
> Hello Shawn,
> 
> On Fri, Mar 30, 2012 at 02:11:36PM +0800, Shawn Guo wrote:
> > On Thu, Mar 29, 2012 at 11:12:20PM +0200, Uwe Kleine-K?nig wrote:
> > ...
> > > diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
> > > index 5cca573..7e00748 100644
> > > --- a/arch/arm/mach-imx/imx51-dt.c
> > > +++ b/arch/arm/mach-imx/imx51-dt.c
> > > @@ -102,7 +102,7 @@ static struct sys_timer imx51_timer = {
> > >  	.init = imx51_timer_init,
> > >  };
> > >  
> > > -static const char *imx51_dt_board_compat[] __initdata = {
> > > +static const char *imx51_dt_board_compat[] __initconst = {
> > >  	"fsl,imx51-babbage",
> > >  	"fsl,imx51",
> > >  	NULL
> > 
> >   CC      arch/arm/mach-imx/imx51-dt.o
> > arch/arm/mach-imx/imx51-dt.c:105:20: error: imx51_dt_board_compat causes a section type conflict
> > make[2]: *** [arch/arm/mach-imx/imx51-dt.o] Error 1
> > 
> > I do not understand why though.
> that's because the strings are constant, but the array is not.

Ah, yes.  It indeed could be overlooked :)

-- 
Regards,
Shawn


From hvaibhav at ti.com  Fri Mar 30 07:29:16 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 30 Mar 2012 11:29:16 +0000
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CAMQu2gyktrAhtTYViYfb9nQ7g8UB1btGFkmd7aLD+Kt4r8y9WQ@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
 <4F7570FC.8000907@ti.com>
 <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>
 <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831841009@DBDE01.ent.ti.com>
 <CAMQu2gyktrAhtTYViYfb9nQ7g8UB1btGFkmd7aLD+Kt4r8y9WQ@mail.gmail.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831841326@DBDE01.ent.ti.com>

On Fri, Mar 30, 2012 at 15:12:19, Shilimkar, Santosh wrote:
> On Fri, Mar 30, 2012 at 2:58 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> > On Fri, Mar 30, 2012 at 14:50:02, Shilimkar, Santosh wrote:
> >> On Fri, Mar 30, 2012 at 2:42 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
> >> > On Fri, Mar 30, 2012 at 14:08:20, Shilimkar, Santosh wrote:
> >> >> On Friday 30 March 2012 02:02 PM, Hiremath, Vaibhav wrote:
> >> >> > On Fri, Mar 30, 2012 at 13:11:35, Shilimkar, Santosh wrote:
> >>
<...>

Santosh & others,

Do you think, it makes sense to clean up the CONFIG_OMAP_32K_TIMER
usage in mach-omap2/timer.c file now? Specifically below code-snippet -

#ifdef CONFIG_OMAP_32K_TIMER
#define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
#define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
#define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
#define OMAP3_SECURE_TIMER      12
#else
#define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
#define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
#define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
#define OMAP3_SECURE_TIMER      1
#endif

And lets make 32k_fclk as default clocksource for gptimer, if it is being
used as clocksource. Atleast with this I can clean whole omap2/3/4 families,
and I can take omap1 thing later .
(as I have to understand/read about omap1 first).

If you agree, I can include this cleanup also in my next version of patch-
series. What's your opinion here?

Thanks,
Vaibhav


From santosh.shilimkar at ti.com  Fri Mar 30 07:35:40 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 30 Mar 2012 17:05:40 +0530
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <79CD15C6BA57404B839C016229A409A831841326@DBDE01.ent.ti.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
 <4F7570FC.8000907@ti.com>
 <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>
 <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831841009@DBDE01.ent.ti.com>
 <CAMQu2gyktrAhtTYViYfb9nQ7g8UB1btGFkmd7aLD+Kt4r8y9WQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831841326@DBDE01.ent.ti.com>
Message-ID: <4F759A8C.9020901@ti.com>

On Friday 30 March 2012 04:59 PM, Hiremath, Vaibhav wrote:
> On Fri, Mar 30, 2012 at 15:12:19, Shilimkar, Santosh wrote:
>> On Fri, Mar 30, 2012 at 2:58 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>>> On Fri, Mar 30, 2012 at 14:50:02, Shilimkar, Santosh wrote:
>>>> On Fri, Mar 30, 2012 at 2:42 PM, Hiremath, Vaibhav <hvaibhav at ti.com> wrote:
>>>>> On Fri, Mar 30, 2012 at 14:08:20, Shilimkar, Santosh wrote:
>>>>>> On Friday 30 March 2012 02:02 PM, Hiremath, Vaibhav wrote:
>>>>>>> On Fri, Mar 30, 2012 at 13:11:35, Shilimkar, Santosh wrote:
>>>>
> <...>
> 
> Santosh & others,
> 
> Do you think, it makes sense to clean up the CONFIG_OMAP_32K_TIMER
> usage in mach-omap2/timer.c file now? Specifically below code-snippet -
> 
> #ifdef CONFIG_OMAP_32K_TIMER
> #define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
> #define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
> #define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
> #define OMAP3_SECURE_TIMER      12
> #else
> #define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
> #define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
> #define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
> #define OMAP3_SECURE_TIMER      1
> #endif
> 
> And lets make 32k_fclk as default clocksource for gptimer, if it is being
> used as clocksource. Atleast with this I can clean whole omap2/3/4 families,
> and I can take omap1 thing later .
> (as I have to understand/read about omap1 first).
> 
> If you agree, I can include this cleanup also in my next version of patch-
> series. What's your opinion here?
> 
I am ok with this clean up. But I let Tony take decision on it.

Regards
Santosh



From arnd at arndb.de  Fri Mar 30 07:36:04 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 30 Mar 2012 11:36:04 +0000
Subject: [PATCH v3 6/6] mmc: sdhci-s3c: Add device tree support
In-Reply-To: <4F7553D1.4030008@st.com>
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>
 <201203271619.13320.arnd@arndb.de> <4F7553D1.4030008@st.com>
Message-ID: <201203301136.05038.arnd@arndb.de>

On Friday 30 March 2012, Viresh Kumar wrote:
> On 3/27/2012 9:49 PM, Arnd Bergmann wrote:
> > These bindings came up in a discussion IRC today. I think it's rather bad that
> > we can't agree on a common way to name the properties for mmc. We have
> > bindings being proposed or already included from Anton, Stephen, Shawn,
> > Rajendra, Viresh, Lee and Thomas. Almost all of them define GPIO pins
> > for card detect and write protect, as well properties to define the bus
> > width and high-speed modes, but we seem to have almost as many different
> > definitions of these as we have drivers.
> > 
> > Can we please come up with a common binding for these?
> 
> Is there any progress on this? Sorry i wasn't following all mails.
> How should i progress for sdhci-spear?

No progress so far. I would suggest we apply the patch below to unify
the bindings we have. I tried to minimize the impact by picking the most
common version for each property, but if we know about devices that would
get broken by this, we may have to be more careful.

Signed-off-by: Arnd Bergmann <arnd at arndb.de>

--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -0,0 +1,25 @@
+These properties are common to multiple MMC host controllers. Any host
+that requires the respective functionality should implement them using
+these definitions.
+
+Required properties:
+- bus-width: Number of data lines, can be <1>, <4>, or <8>
+
+Optional properties:
+- cd-gpios : Specify GPIOs for card detection, see gpio binding
+- wp-gpios : Specify GPIOs for write protection, see gpio binding
+- cd-inverted: when present, polarity on the wp gpio line is inverted
+- wp-inverted: when present, polarity on the wp gpio line is inverted
+- non-removable: non-removable slot (like eMMC)
+
+Example:
+
+sdhci at ab000000 {
+	compatible = "sdhci";
+	reg = <0xab000000 0x200>;
+	interrupts = <23>;
+	bus-width = <4>;
+	cd-gpios = <&gpio 69 0>;
+	cd-inverted;
+	wp-gpios = <&gpio 70 0>;
+}
diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
index 64bcb8b..0d93b4b 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
@@ -11,9 +11,11 @@ Required properties:
   - interrupt-parent : interrupt source phandle.
   - clock-frequency : specifies eSDHC base clock frequency.
   - sdhci,wp-inverted : (optional) specifies that eSDHC controller
-    reports inverted write-protect state;
+    reports inverted write-protect state; New devices should use
+    the generic "wp-inverted" property.
   - sdhci,1-bit-only : (optional) specifies that a controller can
-    only handle 1-bit data transfers.
+    only handle 1-bit data transfers. New devices should use the
+    generic "bus-width = <1>" property.
   - sdhci,auto-cmd12: (optional) specifies that a controller can
     only handle auto CMD12.
 
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
index ab22fe6..c7e404b 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
@@ -9,7 +9,7 @@ Required properties:
 - interrupts : Should contain eSDHC interrupt
 
 Optional properties:
-- fsl,card-wired : Indicate the card is wired to host permanently
+- non-removable : Indicate the card is wired to host permanently
 - fsl,cd-internal : Indicate to use controller internal card detection
 - fsl,wp-internal : Indicate to use controller internal write protection
 - cd-gpios : Specify GPIOs for card detection
diff --git a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt
index 89a0084..d64aea5 100644
--- a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt
@@ -10,7 +10,8 @@ Required properties:
 
 Optional properties:
 - gpios : may specify GPIOs in this order: Card-Detect GPIO,
-  Write-Protect GPIO.
+  Write-Protect GPIO. Note that this does not follow the
+  binding from mmc.txt, for historic reasons.
 - interrupts : the interrupt of a card detect interrupt.
 - interrupt-parent : the phandle for the interrupt controller that
   services interrupts for this device.
diff --git a/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt
index 7e51154..690a226 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt
@@ -6,13 +6,13 @@ and SDIO types of memory cards.
 Required properties:
 - compatible : Should be "nvidia,<chip>-sdhci"
 - reg : Should contain SD/MMC registers location and length
-- interrupts : Should contain SD/MMC interrupt
+- interrupt  : Should contain SD/MMC interrupt
+- bus-width : Number of data lines, can be <1>, <4>, or <8>
 
 Optional properties:
 - cd-gpios : Specify GPIOs for card detection
 - wp-gpios : Specify GPIOs for write protection
 - power-gpios : Specify GPIOs for power control
-- support-8bit : Boolean, indicates if 8-bit mode should be used.
 
 Example:
 
@@ -23,5 +23,5 @@ sdhci at c8000200 {
 	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 	power-gpios = <&gpio 155 0>; /* gpio PT3 */
-	support-8bit;
+	bus-width = <8>;
 };
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
index dbd4368..90b86e5 100644
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -15,10 +15,10 @@ Optional properties:
 ti,dual-volt: boolean, supports dual voltage cards
 <supply-name>-supply: phandle to the regulator device tree node
 "supply-name" examples are "vmmc", "vmmc_aux" etc
-ti,bus-width: Number of data lines, default assumed is 1 if the property is missing.
+bus-width: Number of data lines, default assumed is 1 if the property is missing.
 cd-gpios: GPIOs for card detection
 wp-gpios: GPIOs for write protection
-ti,non-removable: non-removable slot (like eMMC)
+non-removable: non-removable slot (like eMMC)
 ti,needs-special-reset: Requires a special softreset sequence
 
 Example:
@@ -27,7 +27,7 @@ Example:
 		reg = <0x4809c000 0x400>;
 		ti,hwmods = "mmc1";
 		ti,dual-volt;
-		ti,bus-width = <4>;
+		bus-width = <4>;
 		vmmc-supply = <&vmmc>; /* phandle to regulator node */
 		ti,non-removable;
 	};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index c7ee86c..139138a 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -35,7 +35,7 @@
 				};
 
 				esdhc at 50008000 { /* ESDHC2 */
-					fsl,card-wired;
+					non-removable;
 					status = "okay";
 				};
 
@@ -76,7 +76,7 @@
 				};
 
 				esdhc at 50020000 { /* ESDHC3 */
-					fsl,card-wired;
+					non-removable;
 					status = "okay";
 				};
 			};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index ce1c823..d2eaf52 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -41,7 +41,7 @@
 			};
 
 			usdhc at 0219c000 { /* uSDHC4 */
-				fsl,card-wired;
+				non-removable;
 				vmmc-supply = <&reg_3p3v>;
 				status = "okay";
 			};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 8c756be..5b4506c 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -57,7 +57,7 @@
 &mmc1 {
 	vmmc-supply = <&vmmc1>;
 	vmmc_aux-supply = <&vsim>;
-	ti,bus-width = <8>;
+	bus-width = <8>;
 };
 
 &mmc2 {
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index ea6f5bb..31fb421 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -55,7 +55,7 @@
 
 &mmc1 {
 	vmmc-supply = <&vmmc>;
-	ti,bus-width = <8>;
+	bus-width = <8>;
 };
 
 &mmc2 {
@@ -72,5 +72,5 @@
 
 &mmc5 {
 	ti,non-removable;
-	ti,bus-width = <4>;
+	bus-width = <4>;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 67b2e98..a1dd873 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -94,12 +94,12 @@
 
 &mmc1 {
 	vmmc-supply = <&vmmc>;
-	ti,bus-width = <8>;
+	bus-width = <8>;
 };
 
 &mmc2 {
 	vmmc-supply = <&vaux1>;
-	ti,bus-width = <8>;
+	bus-width = <8>;
 	ti,non-removable;
 };
 
@@ -112,6 +112,6 @@
 };
 
 &mmc5 {
-	ti,bus-width = <4>;
+	bus-width = <4>;
 	ti,non-removable;
 };
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index ac3fb75..67c6511 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -54,6 +54,7 @@
 		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
 		power-gpios = <&gpio 31 0>; /* gpio PD7 */
+		bus-width = <4>;
 	};
 
 	sdhci at 78000200 {
@@ -66,5 +67,6 @@
 
 	sdhci at 78000400 {
 		support-8bit;
+		bus-width = <8>;
 	};
 };
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 6e8447d..e9cae68 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -100,6 +100,7 @@
 		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 		power-gpios = <&gpio 155 0>; /* gpio PT3 */
+		bus-width = <4>;
 	};
 
 	sdhci at c8000400 {
@@ -111,5 +112,6 @@
 		wp-gpios = <&gpio 59 0>; /* gpio PH3 */
 		power-gpios = <&gpio 70 0>; /* gpio PI6 */
 		support-8bit;
+		bus-width = <8>;
 	};
 };
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 6c02abb..03d3d79 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -97,6 +97,7 @@
 		cd-gpios = <&gpio 173 0>; /* gpio PV5 */
 		wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
 		power-gpios = <&gpio 169 0>; /* gpio PV1 */
+		bus-width = <4>;
 	};
 
 	sdhci at c8000200 {
@@ -109,6 +110,7 @@
 
 	sdhci at c8000600 {
 		support-8bit;
+		bus-width = <8>;
 	};
 
 	gpio-keys {
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index dbf1c5a..8decf72 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -104,10 +104,12 @@
 		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		bus-width = <4>;
 	};
 
 	sdhci at c8000600 {
 		support-8bit;
+		bus-width = <8>;
 	};
 
 	usb at c5000000 {
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 2dcff87..29e54c7 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -100,9 +100,11 @@
 		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
 		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
 		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+		bus-width = <4>;
 	};
 
 	sdhci at c8000600 {
 		support-8bit;
+		bus-width = <8>;
 	};
 };
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 7e283c8..fe0d609 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -119,6 +119,7 @@
 		sdhc at 2e000 {
 			status = "disabled";
 			sdhci,1-bit-only;
+			bus-width = <1>;
 		};
 
 		par_io at e0100 {
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 47adb16..ae48fc7 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -1766,7 +1766,7 @@ static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
 		pdata->slots[0].nonremovable = true;
 		pdata->slots[0].no_regulator_off_init = true;
 	}
-	of_property_read_u32(np, "ti,bus-width", &bus_width);
+	of_property_read_u32(np, "bus-width", &bus_width);
 	if (bus_width == 4)
 		pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
 	else if (bus_width == 8)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 6193a0d..586a818 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -402,7 +402,7 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 	if (!np)
 		return -ENODEV;
 
-	if (of_get_property(np, "fsl,card-wired", NULL))
+	if (of_get_property(np, "non-removable", NULL))
 		boarddata->cd_type = ESDHC_CD_PERMANENT;
 
 	if (of_get_property(np, "fsl,cd-controller", NULL))
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index c5c2a48..a3858d0 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -42,7 +42,8 @@ static struct sdhci_ops sdhci_pltfm_ops = {
 #ifdef CONFIG_OF
 static bool sdhci_of_wp_inverted(struct device_node *np)
 {
-	if (of_get_property(np, "sdhci,wp-inverted", NULL))
+	if (of_get_property(np, "sdhci,wp-inverted", NULL) ||
+	    of_get_property(np, "wp-inverted", NULL))
 		return true;
 
 	/* Old device trees don't have the wp-inverted property. */
@@ -59,13 +60,16 @@ void sdhci_get_of_property(struct platform_device *pdev)
 	struct sdhci_host *host = platform_get_drvdata(pdev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	const __be32 *clk;
+	u32 bus_width;
 	int size;
 
 	if (of_device_is_available(np)) {
 		if (of_get_property(np, "sdhci,auto-cmd12", NULL))
 			host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 
-		if (of_get_property(np, "sdhci,1-bit-only", NULL))
+		if (of_get_property(np, "sdhci,1-bit-only", NULL) ||
+		    (of_property_read_u32(np, "bus-width", &bus_width) == 0 &&
+		    bus_width = 1))
 			host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
 
 		if (sdhci_of_wp_inverted(np))


From boojin.kim at samsung.com  Fri Mar 30 07:41:14 2012
From: boojin.kim at samsung.com (Boojin Kim)
Date: Fri, 30 Mar 2012 20:41:14 +0900
Subject: [PATCH 0/4] memcpy optimized with strd/ldrd
In-Reply-To: <03e101cd0e07$eec39f10$cc4add30$@com>
References: <03e101cd0e07$eec39f10$cc4add30$@com>
Message-ID: <030501cd0e6a$03642770$0a2c7650$%kim@samsung.com>

Nicolas Pitre wrote:
>
>
> Here's my version.  Lightly tested.
> I have no A15 hardware to run any performance comparison though.
>
I'm reviewing and testing your patch. But, My other work disturbs to reviewing it.
I will give you feedback soon within this week.
Wait a little more.
And, Thanks for your patches. :)

>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel




From bryan.wu at canonical.com  Fri Mar 30 07:58:15 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:15 +0800
Subject: [PATCH v5 00/18] Introduce a led trigger for CPU activity and
 consolidate LED driver in ARM
Message-ID: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>

Based on Linus Walleij's ARM LED consolidation work, this patchset introduce a
new generic led trigger for CPU not only for ARM but also for others.

For enabling CPU idle event, CPU arch code should call ledtrig_cpu() stub to
trigger idle start or idle end event.

These patches convert old style LED driver in arch/arm to gpio_led or new led
driver interface. Against linux-next 20120330 and build successfully for all the machines.

Test ledtrig-cpu driver on OMAP4 Panda board.
--
root at omap4430-panda:~# dmesg | grep trig
[    1.891265] LED trigger cpu0 indicate activity on CPU 0
[    1.896728] LED trigger cpu1 indicate activity on CPU 1
root at omap4430-panda:~# cat /sys/class/leds/pandaboard\:\:status1/trigger
none nand-disk mmc0 mmc1 timer [heartbeat] cpu0 cpu1
root at omap4430-panda:~# cat /sys/class/leds/pandaboard\:\:status2/trigger
none nand-disk [mmc0] mmc1 timer heartbeat cpu0 cpu1
root at omap4430-panda:~# echo cpu0 > /sys/class/leds/pandaboard\:\:status1/trigger
root at omap4430-panda:~# cat /sys/class/leds/pandaboard\:\:status1/trigger
none nand-disk mmc0 mmc1 timer heartbeat [cpu0] cpu1
root at omap4430-panda:~# echo cpu1 > /sys/class/leds/pandaboard\:\:status2/trigger
root at omap4430-panda:~# cat /sys/class/leds/pandaboard\:\:status2/trigger
none nand-disk mmc0 mmc1 timer heartbeat cpu0 [cpu1]

Then try some heavy task like dd and use taskset to assign the task to a specific CPU,
LED will turn on or off as expect
--

Please find these patches here:
       git://kernel.ubuntu.com/roc/linux-2.6/.git leds

v4 --> v5:
 * rebase all the patches on top of latest linux-next
 * replace on_each_cpu() with for_each_possible_cpu()
 * add some description of ledtrig_cpu() API
 * remove old leds code from driver nwflash.c, which should use a new led trigger then
 * this trigger driver can be built as module now

v3 --> v4:
 * fix a typo pointed by Jochen Friedrich
 * fix some building errors
 * add Reviewed-by and Tested-by into patch log

v2 --> v3:
 * almost rewrote the whole ledtrig-cpu driver, which is more simple
 * every CPU will have a per-CPU trigger
 * cpu trigger can be assigned to any leds
 * fix a lockdep issue in led-trigger common code
 * other fix according to review

v1 --> v2:
 * remove select operations in Kconfig of every machines
 * add back supporting of led in core module of mach-integrator
 * solidate name scheme in ledtrig-cpu.c
 * add comments of CPU_LED_* cpu led events
 * fold patches of RealView and Versatile together
 * add machine_is_ check during assabet led driver init
 * add some Acked-by in patch logs
 * remove code for simpad machine in machine-sa11000, since Jochen Friedrich
 introduced gpiolib and gpio-led driver for simpad
 * on Assabet and Netwinder machine, LED operations is reversed like:
 setting bit means turn off leds
 clearing bit means turn on leds
 * add a new function to read CM_CTRL register for led driver

Bryan Wu (18):
  led-triggers: create a trigger for CPU activity
  ARM: at91: convert old leds drivers to gpio_led and led_trigger
    drivers
  ARM: mach-realview and mach-versatile: retire custom LED code
  ARM: mach-ks8695: remove leds driver, since nobody use it
  ARM: mach-shark: retire custom LED code
  ARM: mach-orion5x: convert custom LED code to gpio_led and LED CPU
    trigger
  ARM: mach-integrator: move CM_CTRL to header file for accessing by
    other functions
  ARM: mach-integrator: retire custom LED code
  ARM: mach-clps711x: retire custom LED code of P720T machine
  ARM: mach-ebsa110: retire custom LED code
  ARM: mach-footbridge: retire custom LED code
  char: nwflash: remove old led event code
  ARM: mach-pxa: retire custom LED code
  ARM: plat-samsung: remove including old leds event API header file
  ARM: mach-pnx4008: remove including old leds event API header file
  ARM: mach-omap1: retire custom LED code
  ARM: mach-sa1100: retire custom LED code
  ARM: use new LEDS CPU trigger stub to replace old one

 arch/arm/Kconfig                             |   53 -----
 arch/arm/include/asm/leds.h                  |   50 -----
 arch/arm/kernel/Makefile                     |    1 -
 arch/arm/kernel/leds.c                       |  121 -----------
 arch/arm/kernel/process.c                    |    6 +-
 arch/arm/kernel/time.c                       |   17 --
 arch/arm/mach-at91/board-csb337.c            |    3 -
 arch/arm/mach-at91/board-ecbat91.c           |   18 ++-
 arch/arm/mach-at91/board-eco920.c            |   23 ++-
 arch/arm/mach-at91/board-kafa.c              |   17 ++-
 arch/arm/mach-at91/board-kb9202.c            |   23 ++-
 arch/arm/mach-at91/board-rm9200dk.c          |    3 -
 arch/arm/mach-at91/board-rm9200ek.c          |    3 -
 arch/arm/mach-at91/board-sam9-l9260.c        |   23 ++-
 arch/arm/mach-at91/board-sam9261ek.c         |    3 -
 arch/arm/mach-at91/board-yl-9200.c           |    3 -
 arch/arm/mach-at91/include/mach/board.h      |    1 -
 arch/arm/mach-at91/leds.c                    |  105 ---------
 arch/arm/mach-clps711x/Makefile              |    2 -
 arch/arm/mach-clps711x/common.c              |    1 -
 arch/arm/mach-clps711x/include/mach/time.h   |    2 -
 arch/arm/mach-clps711x/p720t-leds.c          |   66 ------
 arch/arm/mach-clps711x/p720t.c               |   59 +++++
 arch/arm/mach-ebsa110/Makefile               |    4 +-
 arch/arm/mach-ebsa110/leds.c                 |   79 +++++---
 arch/arm/mach-footbridge/Makefile            |    4 -
 arch/arm/mach-footbridge/ebsa285-leds.c      |  138 ------------
 arch/arm/mach-footbridge/ebsa285.c           |   79 +++++++
 arch/arm/mach-footbridge/netwinder-hw.c      |  110 +++++++++--
 arch/arm/mach-footbridge/netwinder-leds.c    |  138 ------------
 arch/arm/mach-integrator/Makefile            |    3 +-
 arch/arm/mach-integrator/core.c              |    3 -
 arch/arm/mach-integrator/include/mach/cm.h   |    2 +
 arch/arm/mach-integrator/leds.c              |  158 +++++++++------
 arch/arm/mach-ks8695/Makefile                |    3 -
 arch/arm/mach-ks8695/devices.c               |   21 --
 arch/arm/mach-ks8695/include/mach/devices.h  |    5 -
 arch/arm/mach-ks8695/leds.c                  |   92 --------
 arch/arm/mach-omap1/Makefile                 |    8 -
 arch/arm/mach-omap1/board-h2.c               |   32 +++
 arch/arm/mach-omap1/board-h3.c               |   32 +++
 arch/arm/mach-omap1/board-osk.c              |   33 +++
 arch/arm/mach-omap1/leds-h2p2-debug.c        |  166 ---------------
 arch/arm/mach-omap1/leds-innovator.c         |   98 ---------
 arch/arm/mach-omap1/leds-osk.c               |  113 ----------
 arch/arm/mach-omap1/leds.c                   |   69 ------
 arch/arm/mach-omap1/leds.h                   |    3 -
 arch/arm/mach-omap1/time.c                   |    1 -
 arch/arm/mach-omap1/timer32k.c               |    1 -
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c |    1 -
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c  |    1 -
 arch/arm/mach-orion5x/rd88f5182-setup.c      |   72 ++-----
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c |    1 -
 arch/arm/mach-pnx4008/time.c                 |    1 -
 arch/arm/mach-pxa/Makefile                   |    8 -
 arch/arm/mach-pxa/idp.c                      |   79 +++++++
 arch/arm/mach-pxa/leds-idp.c                 |  115 ----------
 arch/arm/mach-pxa/leds-lubbock.c             |  124 -----------
 arch/arm/mach-pxa/leds-mainstone.c           |  119 -----------
 arch/arm/mach-pxa/leds.c                     |   32 ---
 arch/arm/mach-pxa/leds.h                     |   13 --
 arch/arm/mach-pxa/lubbock.c                  |   93 ++++++++
 arch/arm/mach-pxa/mainstone.c                |   92 ++++++++
 arch/arm/mach-realview/core.c                |   39 ----
 arch/arm/mach-realview/core.h                |    2 -
 arch/arm/mach-realview/realview_eb.c         |    5 -
 arch/arm/mach-realview/realview_pb1176.c     |    5 -
 arch/arm/mach-realview/realview_pb11mp.c     |    5 -
 arch/arm/mach-realview/realview_pba8.c       |    5 -
 arch/arm/mach-realview/realview_pbx.c        |    5 -
 arch/arm/mach-sa1100/Makefile                |    9 -
 arch/arm/mach-sa1100/assabet.c               |   83 ++++++++
 arch/arm/mach-sa1100/badge4.c                |   30 +++
 arch/arm/mach-sa1100/cerf.c                  |   42 ++++
 arch/arm/mach-sa1100/hackkit.c               |   32 +++
 arch/arm/mach-sa1100/lart.c                  |   26 +++
 arch/arm/mach-sa1100/leds-assabet.c          |  113 ----------
 arch/arm/mach-sa1100/leds-badge4.c           |  110 ----------
 arch/arm/mach-sa1100/leds-cerf.c             |  109 ----------
 arch/arm/mach-sa1100/leds-hackkit.c          |  111 ----------
 arch/arm/mach-sa1100/leds-lart.c             |  100 ---------
 arch/arm/mach-sa1100/leds.c                  |   50 -----
 arch/arm/mach-sa1100/leds.h                  |   13 --
 arch/arm/mach-shark/Makefile                 |    4 +-
 arch/arm/mach-shark/core.c                   |    1 -
 arch/arm/mach-shark/leds.c                   |  226 ++++++++------------
 arch/arm/mach-versatile/core.c               |    5 -
 arch/arm/plat-omap/Kconfig                   |    3 +-
 arch/arm/plat-omap/debug-leds.c              |  293 ++++++--------------------
 arch/arm/plat-samsung/time.c                 |    1 -
 arch/arm/plat-versatile/Kconfig              |    4 +-
 arch/arm/plat-versatile/leds.c               |   13 +-
 drivers/char/nwflash.c                       |   34 ---
 drivers/leds/Kconfig                         |   10 +
 drivers/leds/Makefile                        |    1 +
 drivers/leds/ledtrig-cpu.c                   |  138 ++++++++++++
 include/linux/leds.h                         |   23 ++
 97 files changed, 1410 insertions(+), 2989 deletions(-)
 delete mode 100644 arch/arm/include/asm/leds.h
 delete mode 100644 arch/arm/kernel/leds.c
 delete mode 100644 arch/arm/mach-clps711x/p720t-leds.c
 delete mode 100644 arch/arm/mach-footbridge/ebsa285-leds.c
 delete mode 100644 arch/arm/mach-footbridge/netwinder-leds.c
 delete mode 100644 arch/arm/mach-ks8695/leds.c
 delete mode 100644 arch/arm/mach-omap1/leds-h2p2-debug.c
 delete mode 100644 arch/arm/mach-omap1/leds-innovator.c
 delete mode 100644 arch/arm/mach-omap1/leds-osk.c
 delete mode 100644 arch/arm/mach-omap1/leds.c
 delete mode 100644 arch/arm/mach-omap1/leds.h
 delete mode 100644 arch/arm/mach-pxa/leds-idp.c
 delete mode 100644 arch/arm/mach-pxa/leds-lubbock.c
 delete mode 100644 arch/arm/mach-pxa/leds-mainstone.c
 delete mode 100644 arch/arm/mach-pxa/leds.c
 delete mode 100644 arch/arm/mach-pxa/leds.h
 delete mode 100644 arch/arm/mach-sa1100/leds-assabet.c
 delete mode 100644 arch/arm/mach-sa1100/leds-badge4.c
 delete mode 100644 arch/arm/mach-sa1100/leds-cerf.c
 delete mode 100644 arch/arm/mach-sa1100/leds-hackkit.c
 delete mode 100644 arch/arm/mach-sa1100/leds-lart.c
 delete mode 100644 arch/arm/mach-sa1100/leds.c
 delete mode 100644 arch/arm/mach-sa1100/leds.h
 create mode 100644 drivers/leds/ledtrig-cpu.c

-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:16 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:16 +0800
Subject: [PATCH 01/18] led-triggers: create a trigger for CPU activity
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-2-git-send-email-bryan.wu@canonical.com>

Attempting to consolidate the ARM LED code, this removes the
custom RealView LED trigger code to turn LEDs on and off in
response to CPU activity and replace it with a standard trigger.

(bryan.wu at canonical.com:
It moves arch/arm/kernel/leds.c syscore stubs into this trigger.
It also provides ledtrig_cpu trigger event stub in <linux/leds.h>.
Although it was inspired by ARM work, it can be used in other arch.)

Cc: Richard Purdie <rpurdie at rpsys.net>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Bryan Wu <bryan.wu at canonical.com>

Reviewed-by: Jamie Iles <jamie at jamieiles.com>
Tested-by: Jochen Friedrich <jochen at scram.de>
---
 drivers/leds/Kconfig       |   10 +++
 drivers/leds/Makefile      |    1 +
 drivers/leds/ledtrig-cpu.c |  138 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/leds.h       |   23 +++++++
 4 files changed, 172 insertions(+), 0 deletions(-)
 create mode 100644 drivers/leds/ledtrig-cpu.c

diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index ff4b8cf..cf02fb8 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -448,6 +448,16 @@ config LEDS_TRIGGER_BACKLIGHT
 
 	  If unsure, say N.
 
+config LEDS_TRIGGER_CPU
+	tristate "LED CPU Trigger"
+	depends on LEDS_TRIGGERS
+	help
+	  This allows LEDs to be controlled by active CPUs. This shows
+	  the active CPUs across an array of LEDs so you can see what
+	  CPUs are active on the system at any given moment.
+
+	  If unsure, say N.
+
 config LEDS_TRIGGER_GPIO
 	tristate "LED GPIO Trigger"
 	depends on LEDS_TRIGGERS
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 890481c..0a3d5ad 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -55,4 +55,5 @@ obj-$(CONFIG_LEDS_TRIGGER_IDE_DISK)	+= ledtrig-ide-disk.o
 obj-$(CONFIG_LEDS_TRIGGER_HEARTBEAT)	+= ledtrig-heartbeat.o
 obj-$(CONFIG_LEDS_TRIGGER_BACKLIGHT)	+= ledtrig-backlight.o
 obj-$(CONFIG_LEDS_TRIGGER_GPIO)		+= ledtrig-gpio.o
+obj-$(CONFIG_LEDS_TRIGGER_CPU)		+= ledtrig-cpu.o
 obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON)	+= ledtrig-default-on.o
diff --git a/drivers/leds/ledtrig-cpu.c b/drivers/leds/ledtrig-cpu.c
new file mode 100644
index 0000000..d48c4b5
--- /dev/null
+++ b/drivers/leds/ledtrig-cpu.c
@@ -0,0 +1,138 @@
+/*
+ * ledtrig-cpu.c - LED trigger based on CPU activity
+ *
+ * This LED trigger will be registered for each possible CPU and named as
+ * cpu0, cpu1, cpu2, cpu3, etc.
+ *
+ * It can be binded with any LEDs as other triggers does, either in board
+ * file or via sysfs interface.
+ *
+ * An API named ledtrig_cpu is exported for any user, who want to add CPU
+ * activity indication in their code
+ *
+ * Copyright 2011 Linus Walleij <linus.walleij at linaro.org>
+ * Copyright 2011 - 2012 Bryan Wu <bryan.wu at canonical.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/percpu.h>
+#include <linux/syscore_ops.h>
+#include "leds.h"
+
+#define MAX_NAME_LEN	8
+
+static DEFINE_PER_CPU(struct led_trigger *, cpu_trig);
+static DEFINE_PER_CPU(char [MAX_NAME_LEN], trig_name);
+
+void ledtrig_cpu(enum cpu_led_event ledevt)
+{
+	struct led_trigger *trig = __get_cpu_var(cpu_trig);
+
+	if (!trig)
+		return;
+
+	/* Locate the correct CPU LED */
+	switch (ledevt) {
+	case CPU_LED_IDLE_END:
+	case CPU_LED_START:
+		/* Will turn the LED on, max brightness */
+		led_trigger_event(trig, LED_FULL);
+		break;
+
+	case CPU_LED_IDLE_START:
+	case CPU_LED_STOP:
+	case CPU_LED_HALTED:
+		/* Will turn the LED off */
+		led_trigger_event(trig, LED_OFF);
+		break;
+
+	default:
+		/* Will leave the LED as it is */
+		break;
+	}
+}
+EXPORT_SYMBOL(ledtrig_cpu);
+
+static int ledtrig_cpu_syscore_suspend(void)
+{
+	ledtrig_cpu(CPU_LED_STOP);
+	return 0;
+}
+
+static void ledtrig_cpu_syscore_resume(void)
+{
+	ledtrig_cpu(CPU_LED_START);
+}
+
+static void ledtrig_cpu_syscore_shutdown(void)
+{
+	ledtrig_cpu(CPU_LED_HALTED);
+}
+
+static struct syscore_ops ledtrig_cpu_syscore_ops = {
+	.shutdown	= ledtrig_cpu_syscore_shutdown,
+	.suspend	= ledtrig_cpu_syscore_suspend,
+	.resume		= ledtrig_cpu_syscore_resume,
+};
+
+static void __init ledtrig_cpu_register(void)
+{
+	int cpuid = smp_processor_id();
+	struct led_trigger *trig;
+	char *name = __get_cpu_var(trig_name);
+
+	snprintf(name, MAX_NAME_LEN, "cpu%d", cpuid);
+	led_trigger_register_simple(name, &trig);
+
+	pr_info("LED trigger %s indicate activity on CPU %d\n",
+		trig->name, cpuid);
+
+	__get_cpu_var(cpu_trig) = trig;
+}
+
+static void __exit ledtrig_cpu_unregister(void)
+{
+	struct led_trigger *trig = __get_cpu_var(cpu_trig);
+	char *name = __get_cpu_var(trig_name);
+
+	led_trigger_unregister_simple(trig);
+	__get_cpu_var(cpu_trig) = NULL;
+	memset(name, 0, MAX_NAME_LEN);
+}
+
+static int __init ledtrig_cpu_init(void)
+{
+	int cpu;
+
+	for_each_possible_cpu(cpu)
+		ledtrig_cpu_register();
+
+	register_syscore_ops(&ledtrig_cpu_syscore_ops);
+
+	return 0;
+}
+module_init(ledtrig_cpu_init);
+
+static void __exit ledtrig_cpu_exit(void)
+{
+	int cpu;
+
+	for_each_possible_cpu(cpu)
+		ledtrig_cpu_unregister();
+
+	unregister_syscore_ops(&ledtrig_cpu_syscore_ops);
+}
+module_exit(ledtrig_cpu_exit);
+
+MODULE_AUTHOR("Linus Walleij <linus.walleij at linaro.org>");
+MODULE_AUTHOR("Bryan Wu <bryan.wu at canonical.com>");
+MODULE_DESCRIPTION("CPU LED trigger");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/leds.h b/include/linux/leds.h
index 5884def..1215b94 100644
--- a/include/linux/leds.h
+++ b/include/linux/leds.h
@@ -210,4 +210,27 @@ struct gpio_led_platform_data {
 struct platform_device *gpio_led_register_device(
 		int id, const struct gpio_led_platform_data *pdata);
 
+enum cpu_led_event {
+	CPU_LED_IDLE_START,	/* CPU enters idle */
+	CPU_LED_IDLE_END,	/* CPU idle ends */
+	CPU_LED_START,		/* Machine starts, especially resume */
+	CPU_LED_STOP,		/* Machine stops, especially suspend */
+	CPU_LED_HALTED,		/* Machine shutdown */
+};
+#if defined(CONFIG_LEDS_TRIGGER_CPU) || defined(CONFIG_LEDS_TRIGGER_CPU_MODULE)
+/**
+ * ledtrig_cpu - emit a CPU event as a trigger
+ * @evt: CPU event to be emitted
+ *
+ * Emit a CPU event on a CPU core, which will trigger a
+ * binded LED to turn on or turn off.
+ */
+extern void ledtrig_cpu(enum cpu_led_event evt);
+#else
+static inline void ledtrig_cpu(enum cpu_led_event evt)
+{
+	return;
+}
+#endif
+
 #endif		/* __LINUX_LEDS_H_INCLUDED */
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:17 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:17 +0800
Subject: [PATCH 02/18] ARM: at91: convert old leds drivers to gpio_led and
 led_trigger drivers
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-3-git-send-email-bryan.wu@canonical.com>

Build with at91 defconfigs successfully

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
 arch/arm/mach-at91/board-csb337.c       |    3 -
 arch/arm/mach-at91/board-ecbat91.c      |   18 +++++-
 arch/arm/mach-at91/board-eco920.c       |   23 ++++++-
 arch/arm/mach-at91/board-kafa.c         |   17 ++++-
 arch/arm/mach-at91/board-kb9202.c       |   23 ++++++-
 arch/arm/mach-at91/board-rm9200dk.c     |    3 -
 arch/arm/mach-at91/board-rm9200ek.c     |    3 -
 arch/arm/mach-at91/board-sam9-l9260.c   |   23 ++++++-
 arch/arm/mach-at91/board-sam9261ek.c    |    3 -
 arch/arm/mach-at91/board-yl-9200.c      |    3 -
 arch/arm/mach-at91/include/mach/board.h |    1 -
 arch/arm/mach-at91/leds.c               |  105 -------------------------------
 12 files changed, 89 insertions(+), 136 deletions(-)

diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 1a1547b..ce2eea3 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -48,9 +48,6 @@ static void __init csb337_init_early(void)
 	/* Initialize processor: 3.6864 MHz crystal */
 	at91_initialize(3686400);
 
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
-
 	/* DBGU on ttyS0 */
 	at91_register_uart(0, 0, 0);
 
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 69966ce..da671f5 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -51,9 +51,6 @@ static void __init ecb_at91init_early(void)
 	/* Initialize processor: 18.432 MHz crystal */
 	at91_initialize(18432000);
 
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
-
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
 
@@ -149,6 +146,18 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = {
 	},
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led ecb_leds[] = {
+	{	/* D1 */
+		.name			= "led1",
+		.gpio			= AT91_PIN_PC7,
+		.active_low		= 1,
+		.default_trigger	= "heartbeat",
+	}
+};
+
 static void __init ecb_at91board_init(void)
 {
 	/* Serial */
@@ -168,6 +177,9 @@ static void __init ecb_at91board_init(void)
 
 	/* SPI */
 	at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
+
+	/* LEDs */
+	at91_gpio_leds(ecb_leds, ARRAY_SIZE(ecb_leds));
 }
 
 MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index f23aabe..3484eac 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -38,9 +38,6 @@ static void __init eco920_init_early(void)
 
 	at91_initialize(18432000);
 
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
-
 	/* DBGU on ttyS0. (Rx & Tx only */
 	at91_register_uart(0, 0, 0);
 
@@ -101,6 +98,24 @@ static struct spi_board_info eco920_spi_devices[] = {
 	},
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led eco920_leds[] = {
+	{	/* D1 */
+		.name			= "led1",
+		.gpio			= AT91_PIN_PB0,
+		.active_low		= 1,
+		.default_trigger	= "heartbeat",
+	},
+	{	/* D2 */
+		.name			= "led2",
+		.gpio			= AT91_PIN_PB1,
+		.active_low		= 1,
+		.default_trigger	= "timer",
+	}
+};
+
 static void __init eco920_board_init(void)
 {
 	at91_add_device_serial();
@@ -131,6 +146,8 @@ static void __init eco920_board_init(void)
 	);
 
 	at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
+	/* LEDs */
+	at91_gpio_leds(eco920_leds, ARRAY_SIZE(eco920_leds));
 }
 
 MACHINE_START(ECO920, "eco920")
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index efde1b2..bcd7f44 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -48,9 +48,6 @@ static void __init kafa_init_early(void)
 	/* Initialize processor: 18.432 MHz crystal */
 	at91_initialize(18432000);
 
-	/* Set up the LEDs */
-	at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
-
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
 
@@ -77,6 +74,18 @@ static struct at91_udc_data __initdata kafa_udc_data = {
 	.pullup_pin	= AT91_PIN_PB7,
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led kafa_leds[] = {
+	{	/* D1 */
+		.name			= "led1",
+		.gpio			= AT91_PIN_PB4,
+		.active_low		= 1,
+		.default_trigger	= "heartbeat",
+	},
+};
+
 static void __init kafa_board_init(void)
 {
 	/* Serial */
@@ -91,6 +100,8 @@ static void __init kafa_board_init(void)
 	at91_add_device_i2c(NULL, 0);
 	/* SPI */
 	at91_add_device_spi(NULL, 0);
+	/* LEDs */
+	at91_gpio_leds(kafa_leds, ARRAY_SIZE(kafa_leds));
 }
 
 MACHINE_START(KAFA, "Sperry-Sun KAFA")
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 59b92aa..df74b72 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -51,9 +51,6 @@ static void __init kb9202_init_early(void)
 	/* Initialize processor: 10 MHz crystal */
 	at91_initialize(10000000);
 
-	/* Set up the LEDs */
-	at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
-
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
 
@@ -113,6 +110,24 @@ static struct atmel_nand_data __initdata kb9202_nand_data = {
 	.num_parts	= ARRAY_SIZE(kb9202_nand_partition),
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led kb9202_leds[] = {
+	{	/* D1 */
+		.name			= "led1",
+		.gpio			= AT91_PIN_PC19,
+		.active_low		= 1,
+		.default_trigger	= "heartbeat",
+	},
+	{	/* D2 */
+		.name			= "led2",
+		.gpio			= AT91_PIN_PC18,
+		.active_low		= 1,
+		.default_trigger	= "timer",
+	}
+};
+
 static void __init kb9202_board_init(void)
 {
 	/* Serial */
@@ -131,6 +146,8 @@ static void __init kb9202_board_init(void)
 	at91_add_device_spi(NULL, 0);
 	/* NAND */
 	at91_add_device_nand(&kb9202_nand_data);
+	/* LEDs */
+	at91_gpio_leds(kb9202_leds, ARRAY_SIZE(kb9202_leds));
 }
 
 MACHINE_START(KB9200, "KB920x")
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 01332aa..d89a2ff 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -51,9 +51,6 @@ static void __init dk_init_early(void)
 	/* Initialize processor: 18.432 MHz crystal */
 	at91_initialize(18432000);
 
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
-
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
 
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 11cbaa8..a14727d 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -51,9 +51,6 @@ static void __init ek_init_early(void)
 	/* Initialize processor: 18.432 MHz crystal */
 	at91_initialize(18432000);
 
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
-
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
 
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index e8b116b..7e4405e1 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -49,9 +49,6 @@ static void __init ek_init_early(void)
 	/* Initialize processor: 18.432 MHz crystal */
 	at91_initialize(18432000);
 
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
-
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
 
@@ -182,6 +179,24 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
 	.vcc_pin	= -EINVAL,
 };
 
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+	{	/* D1 */
+		.name			= "led1",
+		.gpio			= AT91_PIN_PA9,
+		.active_low		= 1,
+		.default_trigger	= "heartbeat",
+	},
+	{	/* D2 */
+		.name			= "led2",
+		.gpio			= AT91_PIN_PA6,
+		.active_low		= 1,
+		.default_trigger	= "timer",
+	}
+};
+
 static void __init ek_board_init(void)
 {
 	/* Serial */
@@ -200,6 +215,8 @@ static void __init ek_board_init(void)
 	at91_add_device_mmc(0, &ek_mmc_data);
 	/* I2C */
 	at91_add_device_i2c(NULL, 0);
+	/* LEDs */
+	at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 
 MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index c3f9944..0eaadc7 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -59,9 +59,6 @@ static void __init ek_init_early(void)
 	/* Initialize processor: 18.432 MHz crystal */
 	at91_initialize(18432000);
 
-	/* Setup the LEDs */
-	at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
-
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
 
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 38dd279..23e547b 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -59,9 +59,6 @@ static void __init yl9200_init_early(void)
 	/* Initialize processor: 18.432 MHz crystal */
 	at91_initialize(18432000);
 
-	/* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
-	at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
-
 	/* DBGU on ttyS0. (Rx & Tx only) */
 	at91_register_uart(0, 0, 0);
 
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 544a5d5..964e06f 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -187,7 +187,6 @@ struct at91_can_data {
 extern void __init at91_add_device_can(struct at91_can_data *data);
 
  /* LEDs */
-extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
 
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index 8dfafe7..1b1e62b 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -90,108 +90,3 @@ void __init at91_pwm_leds(struct gpio_led *leds, int nr)
 #else
 void __init at91_pwm_leds(struct gpio_led *leds, int nr){}
 #endif
-
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_LEDS)
-
-#include <asm/leds.h>
-
-/*
- * Old ARM-specific LED framework; not fully functional when generic time is
- * in use.
- */
-
-static u8 at91_leds_cpu;
-static u8 at91_leds_timer;
-
-static inline void at91_led_on(unsigned int led)
-{
-	at91_set_gpio_value(led, 0);
-}
-
-static inline void at91_led_off(unsigned int led)
-{
-	at91_set_gpio_value(led, 1);
-}
-
-static inline void at91_led_toggle(unsigned int led)
-{
-	unsigned long is_off = at91_get_gpio_value(led);
-	if (is_off)
-		at91_led_on(led);
-	else
-		at91_led_off(led);
-}
-
-
-/*
- * Handle LED events.
- */
-static void at91_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch(evt) {
-	case led_start:		/* System startup */
-		at91_led_on(at91_leds_cpu);
-		break;
-
-	case led_stop:		/* System stop / suspend */
-		at91_led_off(at91_leds_cpu);
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:		/* Every 50 timer ticks */
-		at91_led_toggle(at91_leds_timer);
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:	/* Entering idle state */
-		at91_led_off(at91_leds_cpu);
-		break;
-
-	case led_idle_end:	/* Exit idle state */
-		at91_led_on(at91_leds_cpu);
-		break;
-#endif
-
-	default:
-		break;
-	}
-
-	local_irq_restore(flags);
-}
-
-
-static int __init leds_init(void)
-{
-	if (!at91_leds_timer || !at91_leds_cpu)
-		return -ENODEV;
-
-	leds_event = at91_leds_event;
-
-	leds_event(led_start);
-	return 0;
-}
-
-__initcall(leds_init);
-
-
-void __init at91_init_leds(u8 cpu_led, u8 timer_led)
-{
-	/* Enable GPIO to access the LEDs */
-	at91_set_gpio_output(cpu_led, 1);
-	at91_set_gpio_output(timer_led, 1);
-
-	at91_leds_cpu	= cpu_led;
-	at91_leds_timer	= timer_led;
-}
-
-#else
-void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
-#endif
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:18 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:18 +0800
Subject: [PATCH 03/18] ARM: mach-realview and mach-versatile: retire custom
 LED code
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-4-git-send-email-bryan.wu@canonical.com>

This replaces the custom LED trigger code in mach-realview with
some overarching platform code for the plat-versatile family that
will lock down LEDs 2 thru 5 for CPU activity indication. The
day we have 8 core ARM systems the plat-versatile code will have
to become more elaborate.

Tested on RealView PB11MPCore by invoking four different CPU
hogs (yes > /dev/null&) and see the LEDs go on one at a time.
They all go off as the hogs are killed. Tested on the PB1176
as well - just one activity led (led 2) goes on and off with
CPU activity.

(bryan.wu at canonical.com: use ledtrig-cpu instead of ledtrig-arm-cpu)

Cc: Richard Purdie <rpurdie at rpsys.net>
Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
Acked-by: Pawel Moll <pawel.moll at arm.com>
---
 arch/arm/mach-realview/core.c            |   39 ------------------------------
 arch/arm/mach-realview/core.h            |    2 -
 arch/arm/mach-realview/realview_eb.c     |    5 ----
 arch/arm/mach-realview/realview_pb1176.c |    5 ----
 arch/arm/mach-realview/realview_pb11mp.c |    5 ----
 arch/arm/mach-realview/realview_pba8.c   |    5 ----
 arch/arm/mach-realview/realview_pbx.c    |    5 ----
 arch/arm/mach-versatile/core.c           |    5 ----
 arch/arm/plat-versatile/Kconfig          |    4 ++-
 arch/arm/plat-versatile/leds.c           |   13 +++++++---
 10 files changed, 12 insertions(+), 76 deletions(-)

diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 45868bb..d22dee9 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -35,7 +35,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
@@ -436,44 +435,6 @@ struct clcd_board clcd_plat_data = {
 	.remove		= versatile_clcd_remove_dma,
 };
 
-#ifdef CONFIG_LEDS
-#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
-
-void realview_leds_event(led_event_t ledevt)
-{
-	unsigned long flags;
-	u32 val;
-	u32 led = 1 << smp_processor_id();
-
-	local_irq_save(flags);
-	val = readl(VA_LEDS_BASE);
-
-	switch (ledevt) {
-	case led_idle_start:
-		val = val & ~led;
-		break;
-
-	case led_idle_end:
-		val = val | led;
-		break;
-
-	case led_timer:
-		val = val ^ REALVIEW_SYS_LED7;
-		break;
-
-	case led_halted:
-		val = 0;
-		break;
-
-	default:
-		break;
-	}
-
-	writel(val, VA_LEDS_BASE);
-	local_irq_restore(flags);
-}
-#endif	/* CONFIG_LEDS */
-
 /*
  * Where is the timer (VA)?
  */
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index f8f2c0a..f2141ae 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -26,7 +26,6 @@
 #include <linux/io.h>
 
 #include <asm/setup.h>
-#include <asm/leds.h>
 
 #define APB_DEVICE(name, busid, base, plat)			\
 static AMBA_APB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
@@ -47,7 +46,6 @@ extern void __iomem *timer1_va_base;
 extern void __iomem *timer2_va_base;
 extern void __iomem *timer3_va_base;
 
-extern void realview_leds_event(led_event_t ledevt);
 extern void realview_timer_init(unsigned int timer_irq);
 extern int realview_flash_register(struct resource *res, u32 num);
 extern int realview_eth_register(const char *name, struct resource *res);
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index baf382c..21661ad 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -30,7 +30,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
 #include <asm/pgtable.h>
@@ -462,10 +461,6 @@ static void __init realview_eb_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index b1d7caf..c0ff882 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -32,7 +32,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
 #include <asm/pgtable.h>
@@ -375,10 +374,6 @@ static void __init realview_pb1176_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index a98c536..30779ae 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -30,7 +30,6 @@
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
 #include <asm/pgtable.h>
@@ -357,10 +356,6 @@ static void __init realview_pb11mp_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 5965017..081cd72 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -29,7 +29,6 @@
 #include <linux/io.h>
 
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
 #include <asm/pgtable.h>
@@ -299,10 +298,6 @@ static void __init realview_pba8_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 3f2f605..1ce62b9 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -28,7 +28,6 @@
 #include <linux/io.h>
 
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
 #include <asm/smp_twd.h>
@@ -394,10 +393,6 @@ static void __init realview_pbx_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = realview_leds_event;
-#endif
 }
 
 MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 6bbd74e..762f7c4 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -37,7 +37,6 @@
 #include <linux/mtd/physmap.h>
 
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
 #include <asm/hardware/vic.h>
@@ -778,10 +777,6 @@ void __init versatile_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
-
-#ifdef CONFIG_LEDS
-	leds_event = versatile_leds_event;
-#endif
 }
 
 /*
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 043f7b0..b393bb5 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -7,8 +7,10 @@ config PLAT_VERSATILE_FPGA_IRQ
 	bool
 
 config PLAT_VERSATILE_LEDS
-	def_bool y if LEDS_CLASS
+	def_bool y if NEW_LEDS
 	depends on ARCH_REALVIEW || ARCH_VERSATILE
+	select LEDS_CLASS
+	select LEDS_TRIGGER
 
 config PLAT_VERSATILE_SCHED_CLOCK
 	def_bool y
diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c
index 3169fa5..50090c4 100644
--- a/arch/arm/plat-versatile/leds.c
+++ b/arch/arm/plat-versatile/leds.c
@@ -37,10 +37,10 @@ static const struct {
 } versatile_leds[] = {
 	{ "versatile:0", "heartbeat", },
 	{ "versatile:1", "mmc0", },
-	{ "versatile:2", },
-	{ "versatile:3", },
-	{ "versatile:4", },
-	{ "versatile:5", },
+	{ "versatile:2", "cpu0" },
+	{ "versatile:3", "cpu1" },
+	{ "versatile:4", "cpu2" },
+	{ "versatile:5", "cpu3" },
 	{ "versatile:6", },
 	{ "versatile:7", },
 };
@@ -85,6 +85,11 @@ static int __init versatile_leds_init(void)
 		led->cdev.brightness_set = versatile_led_set;
 		led->cdev.brightness_get = versatile_led_get;
 		led->cdev.default_trigger = versatile_leds[i].trigger;
+		/* Some trigger data for CPU LEDs */
+		if (i >= 2 && i <= 5) {
+			/* This is the CPU number actually */
+			led->cdev.trigger_data = (void *) i - 2;
+		}
 		led->mask = BIT(i);
 
 		if (led_classdev_register(NULL, &led->cdev) < 0) {
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:19 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:19 +0800
Subject: [PATCH 04/18] ARM: mach-ks8695: remove leds driver,
 since nobody use it
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-5-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
Acked-by: Andrew Victor <linux at maxim.org.za>
---
 arch/arm/mach-ks8695/Makefile               |    3 -
 arch/arm/mach-ks8695/devices.c              |   21 ------
 arch/arm/mach-ks8695/include/mach/devices.h |    5 --
 arch/arm/mach-ks8695/leds.c                 |   92 ---------------------------
 4 files changed, 0 insertions(+), 121 deletions(-)
 delete mode 100644 arch/arm/mach-ks8695/leds.c

diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile
index 853efd9..9324ef9 100644
--- a/arch/arm/mach-ks8695/Makefile
+++ b/arch/arm/mach-ks8695/Makefile
@@ -11,9 +11,6 @@ obj-				:=
 # PCI support is optional
 obj-$(CONFIG_PCI)		+= pci.o
 
-# LEDs
-obj-$(CONFIG_LEDS)		+= leds.o
-
 # Board-specific support
 obj-$(CONFIG_MACH_KS8695)	+= board-micrel.o
 obj-$(CONFIG_MACH_DSM320)	+= board-dsm320.o
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c
index 73bd638..47399bc 100644
--- a/arch/arm/mach-ks8695/devices.c
+++ b/arch/arm/mach-ks8695/devices.c
@@ -182,27 +182,6 @@ static void __init ks8695_add_device_watchdog(void)
 }
 
 
-/* --------------------------------------------------------------------
- *  LEDs
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_LEDS)
-short ks8695_leds_cpu = -1;
-short ks8695_leds_timer = -1;
-
-void __init ks8695_init_leds(u8 cpu_led, u8 timer_led)
-{
-	/* Enable GPIO to access the LEDs */
-	gpio_direction_output(cpu_led, 1);
-	gpio_direction_output(timer_led, 1);
-
-	ks8695_leds_cpu	  = cpu_led;
-	ks8695_leds_timer = timer_led;
-}
-#else
-void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {}
-#endif
-
 /* -------------------------------------------------------------------- */
 
 /*
diff --git a/arch/arm/mach-ks8695/include/mach/devices.h b/arch/arm/mach-ks8695/include/mach/devices.h
index 85a3c9a..1e6594a 100644
--- a/arch/arm/mach-ks8695/include/mach/devices.h
+++ b/arch/arm/mach-ks8695/include/mach/devices.h
@@ -18,11 +18,6 @@ extern void __init ks8695_add_device_wan(void);
 extern void __init ks8695_add_device_lan(void);
 extern void __init ks8695_add_device_hpna(void);
 
- /* LEDs */
-extern short ks8695_leds_cpu;
-extern short ks8695_leds_timer;
-extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
-
  /* PCI */
 #define KS8695_MODE_PCI		0
 #define KS8695_MODE_MINIPCI	1
diff --git a/arch/arm/mach-ks8695/leds.c b/arch/arm/mach-ks8695/leds.c
deleted file mode 100644
index 4bd7075..0000000
--- a/arch/arm/mach-ks8695/leds.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * LED driver for KS8695-based boards.
- *
- * Copyright (C) Andrew Victor
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <mach/devices.h>
-
-
-static inline void ks8695_led_on(unsigned int led)
-{
-	gpio_set_value(led, 0);
-}
-
-static inline void ks8695_led_off(unsigned int led)
-{
-	gpio_set_value(led, 1);
-}
-
-static inline void ks8695_led_toggle(unsigned int led)
-{
-	unsigned long is_off = gpio_get_value(led);
-	if (is_off)
-		ks8695_led_on(led);
-	else
-		ks8695_led_off(led);
-}
-
-
-/*
- * Handle LED events.
- */
-static void ks8695_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch(evt) {
-	case led_start:		/* System startup */
-		ks8695_led_on(ks8695_leds_cpu);
-		break;
-
-	case led_stop:		/* System stop / suspend */
-		ks8695_led_off(ks8695_leds_cpu);
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:		/* Every 50 timer ticks */
-		ks8695_led_toggle(ks8695_leds_timer);
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:	/* Entering idle state */
-		ks8695_led_off(ks8695_leds_cpu);
-		break;
-
-	case led_idle_end:	/* Exit idle state */
-		ks8695_led_on(ks8695_leds_cpu);
-		break;
-#endif
-
-	default:
-		break;
-	}
-
-	local_irq_restore(flags);
-}
-
-
-static int __init leds_init(void)
-{
-	if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1))
-		return -ENODEV;
-
-	leds_event = ks8695_leds_event;
-
-	leds_event(led_start);
-	return 0;
-}
-
-__initcall(leds_init);
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:20 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:20 +0800
Subject: [PATCH 05/18] ARM: mach-shark: retire custom LED code
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-6-git-send-email-bryan.wu@canonical.com>

The CPU activity LED is now handled by the trigger in the leds
subsystem, retire this old CONFIG_LEDS-based code.

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-shark/Makefile |    4 +-
 arch/arm/mach-shark/core.c   |    1 -
 arch/arm/mach-shark/leds.c   |  226 ++++++++++++++++-------------------------
 3 files changed, 89 insertions(+), 142 deletions(-)

diff --git a/arch/arm/mach-shark/Makefile b/arch/arm/mach-shark/Makefile
index 45be9b0..2965718 100644
--- a/arch/arm/mach-shark/Makefile
+++ b/arch/arm/mach-shark/Makefile
@@ -4,9 +4,7 @@
 
 # Object file lists.
 
-obj-y			:= core.o dma.o irq.o pci.o
+obj-y			:= core.o dma.o irq.o pci.o leds.o
 obj-m			:=
 obj-n			:=
 obj-			:=
-
-obj-$(CONFIG_LEDS)	+= leds.o
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 6a2a7f2..58f6c65 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -13,7 +13,6 @@
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/param.h>
 
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c
index 2560907..55433b0 100644
--- a/arch/arm/mach-shark/leds.c
+++ b/arch/arm/mach-shark/leds.c
@@ -1,165 +1,115 @@
 /*
- * arch/arm/mach-shark/leds.c
- * by Alexander Schulz
- *
- * derived from:
- * arch/arm/kernel/leds-footbridge.c
- * Copyright (C) 1998-1999 Russell King
- *
  * DIGITAL Shark LED control routines.
  *
- * The leds use is as follows:
- *  - Green front - toggles state every 50 timer interrupts
- *  - Amber front - Unused, this is a dual color led (Amber/Green)
- *  - Amber back  - On if system is not idle
+ * Driver for the 3 user LEDs found on the Shark
+ * Based on Versatile and RealView machine LED code
  *
- * Changelog:
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Bryan Wu <bryan.wu at canonical.com>
  */
 #include <linux/kernel.h>
-#include <linux/module.h>
 #include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/ioport.h>
 #include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
-#include <asm/leds.h>
+#include <asm/mach-types.h>
 
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
+struct shark_led {
+	struct led_classdev cdev;
+	u8 mask;
+};
 
-#define SEQUOIA_LED_GREEN       (1<<6)
-#define SEQUOIA_LED_AMBER       (1<<5)
-#define SEQUOIA_LED_BACK        (1<<7)
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} shark_leds[] = {
+	{ "shark:amber0", "default-on", },	/* Bit 5 */
+	{ "shark:green", "heartbeat", },	/* Bit 6 */
+	{ "shark:amber1", "cpu0" },		/* Bit 7 */
+};
+
+static u16 led_reg_read(void)
+{
+	outw(0x09, 0x24);
+	return inw(0x26);
+}
 
-static char led_state;
-static short hw_led_state;
-static short saved_state;
+static void led_reg_write(u16 value)
+{
+	outw(0x09, 0x24);
+	outw(value, 0x26);
+}
 
-static DEFINE_RAW_SPINLOCK(leds_lock);
+static void shark_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
+{
+	struct shark_led *led = container_of(cdev,
+						 struct shark_led, cdev);
+	u16 reg = led_reg_read();
 
-short sequoia_read(int addr) {
-  outw(addr,0x24);
-  return inw(0x26);
-}
+	if (b != LED_OFF)
+		reg |= led->mask;
+	else
+		reg &= ~led->mask;
 
-void sequoia_write(short value,short addr) {
-  outw(addr,0x24);
-  outw(value,0x26);
+	led_reg_write(reg);
 }
 
-static void sequoia_leds_event(led_event_t evt)
+static enum led_brightness shark_led_get(struct led_classdev *cdev)
 {
-	unsigned long flags;
-
-	raw_spin_lock_irqsave(&leds_lock, flags);
-
-	hw_led_state = sequoia_read(0x09);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state |= SEQUOIA_LED_GREEN;
-		hw_led_state |= SEQUOIA_LED_AMBER;
-#ifdef CONFIG_LEDS_CPU
-		hw_led_state |= SEQUOIA_LED_BACK;
-#else
-		hw_led_state &= ~SEQUOIA_LED_BACK;
-#endif
-		led_state |= LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		hw_led_state &= ~SEQUOIA_LED_BACK;
-		hw_led_state |= SEQUOIA_LED_GREEN;
-		hw_led_state |= SEQUOIA_LED_AMBER;
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		saved_state = hw_led_state;
-		hw_led_state &= ~SEQUOIA_LED_BACK;
-		hw_led_state |= SEQUOIA_LED_GREEN;
-		hw_led_state |= SEQUOIA_LED_AMBER;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = saved_state;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= SEQUOIA_LED_GREEN;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~SEQUOIA_LED_BACK;
-		break;
-
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= SEQUOIA_LED_BACK;
-		break;
-#endif
-
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~SEQUOIA_LED_GREEN;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= SEQUOIA_LED_GREEN;
-		break;
-
-	case led_amber_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~SEQUOIA_LED_AMBER;
-		break;
-
-	case led_amber_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= SEQUOIA_LED_AMBER;
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= SEQUOIA_LED_BACK;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~SEQUOIA_LED_BACK;
-		break;
-
-	default:
-		break;
-	}
-
-	if  (led_state & LED_STATE_ENABLED)
-		sequoia_write(hw_led_state,0x09);
+	struct shark_led *led = container_of(cdev,
+						 struct shark_led, cdev);
+	u16 reg = led_reg_read();
 
-	raw_spin_unlock_irqrestore(&leds_lock, flags);
+	return (reg & led->mask) ? LED_FULL : LED_OFF;
 }
 
-static int __init leds_init(void)
+static int __init shark_leds_init(void)
 {
-	extern void (*leds_event)(led_event_t);
-	short temp;
-	
-	leds_event = sequoia_leds_event;
+	int i;
+	u16 reg;
+
+	if (!machine_is_shark())
+		return -ENODEV;
+
+	for (i = 0; i < ARRAY_SIZE(shark_leds); i++) {
+		struct shark_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = shark_leds[i].name;
+		led->cdev.brightness_set = shark_led_set;
+		led->cdev.brightness_get = shark_led_get;
+		led->cdev.default_trigger = shark_leds[i].trigger;
+
+		/* Count in 5 bits offset */
+		led->mask = BIT(i + 5);
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
 
 	/* Make LEDs independent of power-state */
-	request_region(0x24,4,"sequoia");
-	temp = sequoia_read(0x09);
-	temp |= 1<<10;
-	sequoia_write(temp,0x09);
-	leds_event(led_start);
+	request_region(0x24, 4, "led_reg");
+	reg = led_reg_read();
+	reg |= 1 << 10;
+	led_reg_write(reg);
+
 	return 0;
 }
 
-__initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(shark_leds_init);
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:21 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:21 +0800
Subject: [PATCH 06/18] ARM: mach-orion5x: convert custom LED code to gpio_led
 and LED CPU trigger
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-7-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
Acked-by: Nicolas Pitre <nico at fluxnic.net>
---
 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c |    1 -
 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c  |    1 -
 arch/arm/mach-orion5x/rd88f5182-setup.c      |   72 ++++++++------------------
 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c |    1 -
 4 files changed, 22 insertions(+), 53 deletions(-)

diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 292038f..698ad13 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -18,7 +18,6 @@
 #include <linux/ethtool.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index c44eaba..0379f5b 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -19,7 +19,6 @@
 #include <linux/i2c.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index e3ce617..8bc8962 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -19,8 +19,8 @@
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/i2c.h>
+#include <linux/leds.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
@@ -53,12 +53,6 @@
 #define RD88F5182_PCI_SLOT0_IRQ_A_PIN	7
 #define RD88F5182_PCI_SLOT0_IRQ_B_PIN	6
 
-/*
- * GPIO Debug LED
- */
-
-#define RD88F5182_GPIO_DBG_LED		0
-
 /*****************************************************************************
  * 16M NOR Flash on Device bus CS1
  ****************************************************************************/
@@ -83,55 +77,32 @@ static struct platform_device rd88f5182_nor_flash = {
 	.resource		= &rd88f5182_nor_flash_resource,
 };
 
-#ifdef CONFIG_LEDS
-
 /*****************************************************************************
- * Use GPIO debug led as CPU active indication
+ * Use GPIO LED as CPU active indication
  ****************************************************************************/
 
-static void rd88f5182_dbgled_event(led_event_t evt)
-{
-	int val;
-
-	if (evt == led_idle_end)
-		val = 1;
-	else if (evt == led_idle_start)
-		val = 0;
-	else
-		return;
-
-	gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
-}
-
-static int __init rd88f5182_dbgled_init(void)
-{
-	int pin;
-
-	if (machine_is_rd88f5182()) {
-		pin = RD88F5182_GPIO_DBG_LED;
+#define RD88F5182_GPIO_LED		0
 
-		if (gpio_request(pin, "DBGLED") == 0) {
-			if (gpio_direction_output(pin, 0) != 0) {
-				printk(KERN_ERR "rd88f5182_dbgled_init failed "
-						"to set output pin %d\n", pin);
-				gpio_free(pin);
-				return 0;
-			}
-		} else {
-			printk(KERN_ERR "rd88f5182_dbgled_init failed "
-					"to request gpio %d\n", pin);
-			return 0;
-		}
-
-		leds_event = rd88f5182_dbgled_event;
-	}
-
-	return 0;
-}
+static struct gpio_led rd88f5182_gpio_led_pins[] = {
+	{
+		.name		= "rd88f5182:cpu",
+		.default_trigger = "cpu0",
+		.gpio		= RD88F5182_GPIO_LED,
+	},
+};
 
-__initcall(rd88f5182_dbgled_init);
+static struct gpio_led_platform_data rd88f5182_gpio_led_data = {
+	.leds		= rd88f5182_gpio_led_pins,
+	.num_leds	= ARRAY_SIZE(rd88f5182_gpio_led_pins),
+};
 
-#endif
+static struct platform_device rd88f5182_gpio_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &rd88f5182_gpio_led_data,
+	},
+};
 
 /*****************************************************************************
  * PCI
@@ -299,6 +270,7 @@ static void __init rd88f5182_init(void)
 
 	orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
 	platform_device_register(&rd88f5182_nor_flash);
+	platform_device_register(&rd88f5182_gpio_leds);
 
 	i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
 }
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 2c5fab0..e2fd500 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -21,7 +21,6 @@
 #include <linux/ethtool.h>
 #include <net/dsa.h>
 #include <asm/mach-types.h>
-#include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:22 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:22 +0800
Subject: [PATCH 07/18] ARM: mach-integrator: move CM_CTRL to header file for
 accessing by other functions
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-8-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-integrator/core.c            |    2 --
 arch/arm/mach-integrator/include/mach/cm.h |    2 ++
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index eaf6c63..8c53562 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -172,8 +172,6 @@ static struct amba_pl010_data integrator_uart_data = {
 	.set_mctrl = integrator_uart_set_mctrl,
 };
 
-#define CM_CTRL	IO_ADDRESS(INTEGRATOR_HDR_CTRL)
-
 static DEFINE_RAW_SPINLOCK(cm_lock);
 
 /**
diff --git a/arch/arm/mach-integrator/include/mach/cm.h b/arch/arm/mach-integrator/include/mach/cm.h
index 445d57a..1a78692e 100644
--- a/arch/arm/mach-integrator/include/mach/cm.h
+++ b/arch/arm/mach-integrator/include/mach/cm.h
@@ -3,6 +3,8 @@
  */
 void cm_control(u32, u32);
 
+#define CM_CTRL	IO_ADDRESS(INTEGRATOR_HDR_CTRL)
+
 #define CM_CTRL_LED			(1 << 0)
 #define CM_CTRL_nMBDET			(1 << 1)
 #define CM_CTRL_REMAP			(1 << 2)
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:23 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:23 +0800
Subject: [PATCH 08/18] ARM: mach-integrator: retire custom LED code
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-9-git-send-email-bryan.wu@canonical.com>

Use the LED in core module for CPU activity and also enable 4
debugging LEDs in baseboard.

The CPU activity LED is now handled by the trigger in the leds
subsystem, retire this old CONFIG_LEDS-based code.

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-integrator/Makefile |    3 +-
 arch/arm/mach-integrator/core.c   |    1 -
 arch/arm/mach-integrator/leds.c   |  158 ++++++++++++++++++++++---------------
 3 files changed, 96 insertions(+), 66 deletions(-)

diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index ebeef96..5521d18 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -4,11 +4,10 @@
 
 # Object file lists.
 
-obj-y					:= core.o lm.o
+obj-y					:= core.o lm.o leds.o
 obj-$(CONFIG_ARCH_INTEGRATOR_AP)	+= integrator_ap.o
 obj-$(CONFIG_ARCH_INTEGRATOR_CP)	+= integrator_cp.o
 
-obj-$(CONFIG_LEDS)			+= leds.o
 obj-$(CONFIG_PCI)			+= pci_v3.o pci.o
 obj-$(CONFIG_CPU_FREQ_INTEGRATOR)	+= cpu.o
 obj-$(CONFIG_INTEGRATOR_IMPD1)		+= impd1.o
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 8c53562..0c7c4ef 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -28,7 +28,6 @@
 #include <mach/cm.h>
 #include <mach/irqs.h>
 
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index 466defa..dab912b 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -1,90 +1,122 @@
 /*
- *  linux/arch/arm/mach-integrator/leds.c
+ * Driver for the 4 user LEDs found on the Integrator AP/CP baseboard
+ * Based on Versatile and RealView machine LED code
  *
- *  Integrator/AP and Integrator/CP LED control routines
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Bryan Wu <bryan.wu at canonical.com>
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/spinlock.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
+#include <mach/cm.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-#include <mach/cm.h>
 
-static int saved_leds;
+#define ALPHA_REG __io_address(INTEGRATOR_DBG_BASE)
+#define LEDREG	(__io_address(INTEGRATOR_DBG_BASE) + INTEGRATOR_DBG_LEDS_OFFSET)
+
+struct integrator_led {
+	struct led_classdev	cdev;
+	u8			mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} integrator_leds[] = {
+	{ "integrator:green0", "heartbeat", },
+	{ "integrator:yellow", },
+	{ "integrator:red", },
+	{ "integrator:green1", },
+	{ "integrator:core_module", "cpu0", },
+};
 
-static void integrator_leds_event(led_event_t ledevt)
+static void integrator_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
 {
-	unsigned long flags;
-	const unsigned int dbg_base = IO_ADDRESS(INTEGRATOR_DBG_BASE);
-	unsigned int update_alpha_leds;
+	struct integrator_led *led = container_of(cdev,
+						 struct integrator_led, cdev);
+	u32 reg = __raw_readl(LEDREG);
 
-	// yup, change the LEDs
-	local_irq_save(flags);
-	update_alpha_leds = 0;
+	if (b != LED_OFF)
+		reg |= led->mask;
+	else
+		reg &= ~led->mask;
 
-	switch(ledevt) {
-	case led_idle_start:
-		cm_control(CM_CTRL_LED, 0);
-		break;
+	while (__raw_readl(ALPHA_REG) & 1)
+		cpu_relax();
 
-	case led_idle_end:
-		cm_control(CM_CTRL_LED, CM_CTRL_LED);
-		break;
+	__raw_writel(reg, LEDREG);
+}
 
-	case led_timer:
-		saved_leds ^= GREEN_LED;
-		update_alpha_leds = 1;
-		break;
+static enum led_brightness integrator_led_get(struct led_classdev *cdev)
+{
+	struct integrator_led *led = container_of(cdev,
+						 struct integrator_led, cdev);
+	u32 reg = __raw_readl(LEDREG);
 
-	case led_red_on:
-		saved_leds |= RED_LED;
-		update_alpha_leds = 1;
-		break;
+	return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
 
-	case led_red_off:
-		saved_leds &= ~RED_LED;
-		update_alpha_leds = 1;
-		break;
+static void cm_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
+{
+	if (b != LED_OFF)
+		cm_control(CM_CTRL_LED, CM_CTRL_LED);
+	else
+		cm_control(CM_CTRL_LED, 0);
+}
 
-	default:
-		break;
-	}
+static enum led_brightness cm_led_get(struct led_classdev *cdev)
+{
+	u32 reg = readl(CM_CTRL);
 
-	if (update_alpha_leds) {
-		while (__raw_readl(dbg_base + INTEGRATOR_DBG_ALPHA_OFFSET) & 1);
-		__raw_writel(saved_leds, dbg_base + INTEGRATOR_DBG_LEDS_OFFSET);
-	}
-	local_irq_restore(flags);
+	return (reg & CM_CTRL_LED) ? LED_FULL : LED_OFF;
 }
 
-static int __init leds_init(void)
+static int __init integrator_leds_init(void)
 {
-	if (machine_is_integrator() || machine_is_cintegrator())
-		leds_event = integrator_leds_event;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(integrator_leds); i++) {
+		struct integrator_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+
+		led->cdev.name = integrator_leds[i].name;
+
+		if (i == 4) { /* Setting for LED in core module */
+			led->cdev.brightness_set = cm_led_set;
+			led->cdev.brightness_get = cm_led_get;
+		} else {
+			led->cdev.brightness_set = integrator_led_set;
+			led->cdev.brightness_get = integrator_led_get;
+		}
+
+		led->cdev.default_trigger = integrator_leds[i].trigger;
+		led->mask = BIT(i);
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
 
 	return 0;
 }
 
-core_initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(integrator_leds_init);
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:24 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:24 +0800
Subject: [PATCH 09/18] ARM: mach-clps711x: retire custom LED code of P720T
 machine
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-10-git-send-email-bryan.wu@canonical.com>

Add tigger based LED driver into board file of P720T.
Remove old LED driver file.

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-clps711x/Makefile            |    2 -
 arch/arm/mach-clps711x/common.c            |    1 -
 arch/arm/mach-clps711x/include/mach/time.h |    2 -
 arch/arm/mach-clps711x/p720t-leds.c        |   66 ----------------------------
 arch/arm/mach-clps711x/p720t.c             |   59 +++++++++++++++++++++++++
 5 files changed, 59 insertions(+), 71 deletions(-)
 delete mode 100644 arch/arm/mach-clps711x/p720t-leds.c

diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index f2f0256..5872b49 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -16,5 +16,3 @@ obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o
 obj-$(CONFIG_ARCH_EDB7211)  += edb7211-arch.o edb7211-mm.o
 obj-$(CONFIG_ARCH_FORTUNET) += fortunet.o
 obj-$(CONFIG_ARCH_P720T)    += p720t.o
-leds-$(CONFIG_ARCH_P720T)   += p720t-leds.o
-obj-$(CONFIG_LEDS)          += $(leds-y)
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 3c5b5bb..c9ba167 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -31,7 +31,6 @@
 #include <asm/sizes.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
-#include <asm/leds.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-clps711x/include/mach/time.h b/arch/arm/mach-clps711x/include/mach/time.h
index 61fef91..bafc325 100644
--- a/arch/arm/mach-clps711x/include/mach/time.h
+++ b/arch/arm/mach-clps711x/include/mach/time.h
@@ -17,7 +17,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#include <asm/leds.h>
 #include <asm/hardware/clps7111.h>
 
 extern void clps711x_setup_timer(void);
@@ -29,7 +28,6 @@ static irqreturn_t
 p720t_timer_interrupt(int irq, void *dev_id)
 {
 	struct pt_regs *regs = get_irq_regs();
-	do_leds();
 	xtime_update(1);
 #ifndef CONFIG_SMP
 	update_process_times(user_mode(regs));
diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c
deleted file mode 100644
index dd9a6cd..0000000
--- a/arch/arm/mach-clps711x/p720t-leds.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/leds.c
- *
- *  Integrator LED control routines
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include <asm/hardware/clps7111.h>
-#include <asm/hardware/ep7212.h>
-
-static void p720t_leds_event(led_event_t ledevt)
-{
-	unsigned long flags;
-	u32 pddr;
-
-	local_irq_save(flags);
-	switch(ledevt) {
-	case led_idle_start:
-		break;
-
-	case led_idle_end:
-		break;
-
-	case led_timer:
-		pddr = clps_readb(PDDR);
-		clps_writeb(pddr ^ 1, PDDR);
-		break;
-
-	default:
-		break;
-	}
-
-	local_irq_restore(flags);
-}
-
-static int __init leds_init(void)
-{
-	if (machine_is_p720t())
-		leds_event = p720t_leds_event;
-
-	return 0;
-}
-
-arch_initcall(leds_init);
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index 42ee8f3..c782cbf 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -23,6 +23,8 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <mach/hardware.h>
 #include <asm/pgtable.h>
@@ -34,6 +36,8 @@
 #include <asm/mach/map.h>
 #include <mach/syspld.h>
 
+#include <asm/hardware/clps7111.h>
+
 #include "common.h"
 
 /*
@@ -121,3 +125,58 @@ static int p720t_hw_init(void)
 
 __initcall(p720t_hw_init);
 
+/*
+ * LED controled by CPLD
+ */
+static void p720t_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
+{
+	u8 reg = clps_readb(PDDR);
+
+	if (b != LED_OFF)
+		reg |= 0x1;
+	else
+		reg &= ~0x1;
+
+	clps_writeb(reg, PDDR);
+}
+
+static enum led_brightness p720t_led_get(struct led_classdev *cdev)
+{
+	u8 reg = clps_readb(PDDR);
+
+	return (reg & 0x1) ? LED_FULL : LED_OFF;
+}
+
+static int __init p720t_leds_init(void)
+{
+
+	struct led_classdev *cdev;
+	int ret;
+
+	if (!machine_is_p720t())
+		return -ENODEV;
+
+	cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
+	if (!cdev)
+		return -ENOMEM;
+
+	cdev->name = "p720t:0";
+	cdev->brightness_set = p720t_led_set;
+	cdev->brightness_get = p720t_led_get;
+	cdev->default_trigger = "heartbeat";
+
+	ret = led_classdev_register(NULL, cdev);
+	if (ret	< 0) {
+		kfree(cdev);
+		return ret;
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(p720t_leds_init);
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:25 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:25 +0800
Subject: [PATCH 10/18] ARM: mach-ebsa110: retire custom LED code
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-11-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-ebsa110/Makefile |    4 +--
 arch/arm/mach-ebsa110/leds.c   |   79 ++++++++++++++++++++++++----------------
 2 files changed, 49 insertions(+), 34 deletions(-)

diff --git a/arch/arm/mach-ebsa110/Makefile b/arch/arm/mach-ebsa110/Makefile
index 6520ac8..935e4af 100644
--- a/arch/arm/mach-ebsa110/Makefile
+++ b/arch/arm/mach-ebsa110/Makefile
@@ -4,9 +4,7 @@
 
 # Object file lists.
 
-obj-y			:= core.o io.o
+obj-y			:= core.o io.o leds.o
 obj-m			:=
 obj-n			:=
 obj-			:=
-
-obj-$(CONFIG_LEDS)	+= leds.o
diff --git a/arch/arm/mach-ebsa110/leds.c b/arch/arm/mach-ebsa110/leds.c
index 99e14e3..b7dd0a5 100644
--- a/arch/arm/mach-ebsa110/leds.c
+++ b/arch/arm/mach-ebsa110/leds.c
@@ -1,52 +1,69 @@
 /*
- *  linux/arch/arm/mach-ebsa110/leds.c
+ * Driver for the LED found on the EBSA110 machine
+ * Based on Versatile and RealView machine LED code
  *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  EBSA-110 LED control routines.  We use the led as follows:
- *
- *   - Red - toggles state every 50 timer interrupts
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Bryan Wu <bryan.wu at canonical.com>
  */
-#include <linux/module.h>
-#include <linux/spinlock.h>
+#include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
-#include <mach/hardware.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 
 #include "core.h"
 
-static spinlock_t leds_lock;
-
-static void ebsa110_leds_event(led_event_t ledevt)
+static void ebsa110_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
 {
-	unsigned long flags;
+	u8 reg = __raw_readb(SOFT_BASE);
 
-	spin_lock_irqsave(&leds_lock, flags);
+	if (b != LED_OFF)
+		reg |= 0x80;
+	else
+		reg &= ~0x80;
 
-	switch(ledevt) {
-	case led_timer:
-		*(volatile unsigned char *)SOFT_BASE ^= 128;
-		break;
+	__raw_writeb(reg, SOFT_BASE);
+}
 
-	default:
-		break;
-	}
+static enum led_brightness ebsa110_led_get(struct led_classdev *cdev)
+{
+	u8 reg = __raw_readb(SOFT_BASE);
 
-	spin_unlock_irqrestore(&leds_lock, flags);
+	return (reg & 0x80) ? LED_FULL : LED_OFF;
 }
 
-static int __init leds_init(void)
+static int __init ebsa110_leds_init(void)
 {
-	if (machine_is_ebsa110())
-		leds_event = ebsa110_leds_event;
+
+	struct led_classdev *cdev;
+	int ret;
+
+	if (!machine_is_ebsa110())
+		return -ENODEV;
+
+	cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
+	if (!cdev)
+		return -ENOMEM;
+
+	cdev->name = "ebsa110:0";
+	cdev->brightness_set = ebsa110_led_set;
+	cdev->brightness_get = ebsa110_led_get;
+	cdev->default_trigger = "heartbeat";
+
+	ret = led_classdev_register(NULL, cdev);
+	if (ret	< 0) {
+		kfree(cdev);
+		return ret;
+	}
 
 	return 0;
 }
 
-__initcall(leds_init);
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(ebsa110_leds_init);
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:26 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:26 +0800
Subject: [PATCH 11/18] ARM: mach-footbridge: retire custom LED code
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-12-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-footbridge/Makefile         |    4 -
 arch/arm/mach-footbridge/ebsa285-leds.c   |  138 -----------------------------
 arch/arm/mach-footbridge/ebsa285.c        |   79 ++++++++++++++++
 arch/arm/mach-footbridge/netwinder-hw.c   |  110 ++++++++++++++++++++---
 arch/arm/mach-footbridge/netwinder-leds.c |  138 -----------------------------
 5 files changed, 175 insertions(+), 294 deletions(-)
 delete mode 100644 arch/arm/mach-footbridge/ebsa285-leds.c
 delete mode 100644 arch/arm/mach-footbridge/netwinder-leds.c

diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile
index 3afb1b2..0b64dd4 100644
--- a/arch/arm/mach-footbridge/Makefile
+++ b/arch/arm/mach-footbridge/Makefile
@@ -14,15 +14,11 @@ pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o
 pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
 pci-$(CONFIG_ARCH_PERSONAL_SERVER) += personal-pci.o
 
-leds-$(CONFIG_ARCH_EBSA285) += ebsa285-leds.o
-leds-$(CONFIG_ARCH_NETWINDER) += netwinder-leds.o
-
 obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o
 obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o
 obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o
 obj-$(CONFIG_ARCH_PERSONAL_SERVER) += personal.o dc21285-timer.o
 
 obj-$(CONFIG_PCI)	+=$(pci-y)
-obj-$(CONFIG_LEDS)	+=$(leds-y)
 
 obj-$(CONFIG_ISA)	+= isa.o isa-rtc.o
diff --git a/arch/arm/mach-footbridge/ebsa285-leds.c b/arch/arm/mach-footbridge/ebsa285-leds.c
deleted file mode 100644
index 5bd2667..0000000
--- a/arch/arm/mach-footbridge/ebsa285-leds.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- *  linux/arch/arm/mach-footbridge/ebsa285-leds.c
- *
- *  Copyright (C) 1998-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- * EBSA-285 control routines.
- *
- * The EBSA-285 uses the leds as follows:
- *  - Green - toggles state every 50 timer interrupts
- *  - Amber - On if system is not idle
- *  - Red   - currently unused
- *
- * Changelog:
- *   02-05-1999	RMK	Various cleanups
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-static char led_state;
-static char hw_led_state;
-
-static DEFINE_SPINLOCK(leds_lock);
-
-static void ebsa285_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&leds_lock, flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN;
-#ifndef CONFIG_LEDS_CPU
-		hw_led_state |= XBUS_LED_AMBER;
-#endif
-		led_state |= LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN | XBUS_LED_AMBER;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = XBUS_LED_RED | XBUS_LED_GREEN | XBUS_LED_AMBER;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= XBUS_LED_GREEN;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= XBUS_LED_AMBER;
-		break;
-
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~XBUS_LED_AMBER;
-		break;
-#endif
-
-	case led_halted:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~XBUS_LED_RED;
-		break;
-
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~XBUS_LED_GREEN;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= XBUS_LED_GREEN;
-		break;
-
-	case led_amber_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~XBUS_LED_AMBER;
-		break;
-
-	case led_amber_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= XBUS_LED_AMBER;
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~XBUS_LED_RED;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= XBUS_LED_RED;
-		break;
-
-	default:
-		break;
-	}
-
-	if  (led_state & LED_STATE_ENABLED)
-		*XBUS_LEDS = hw_led_state;
-
-	spin_unlock_irqrestore(&leds_lock, flags);
-}
-
-static int __init leds_init(void)
-{
-	if (machine_is_ebsa285())
-		leds_event = ebsa285_leds_event;
-
-	leds_event(led_start);
-
-	return 0;
-}
-
-__initcall(leds_init);
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index 27716a7..2ab83c3 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -5,6 +5,8 @@
  */
 #include <linux/init.h>
 #include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <asm/hardware/dec21285.h>
 #include <asm/mach-types.h>
@@ -13,6 +15,83 @@
 
 #include "common.h"
 
+/* LEDs */
+struct ebsa285_led {
+	struct led_classdev     cdev;
+	u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} ebsa285_leds[] = {
+	{ "ebsa285:amber", "heartbeat", },
+	{ "ebsa285:green", "cpu0", },
+	{ "ebsa285:red",},
+};
+
+static void ebsa285_led_set(struct led_classdev *cdev,
+		enum led_brightness b)
+{
+	struct ebsa285_led *led = container_of(cdev,
+			struct ebsa285_led, cdev);
+
+	if (b != LED_OFF)
+		*XBUS_LEDS |= led->mask;
+	else
+		*XBUS_LEDS &= ~led->mask;
+}
+
+static enum led_brightness ebsa285_led_get(struct led_classdev *cdev)
+{
+	struct ebsa285_led *led = container_of(cdev,
+			struct ebsa285_led, cdev);
+
+	return (*XBUS_LEDS & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init ebsa285_leds_init(void)
+{
+	int i;
+
+	if (machine_is_ebsa285())
+		return -ENODEV;
+
+	/* 3 LEDS All ON */
+	*XBUS_LEDS |= XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED;
+
+	for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) {
+		struct ebsa285_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = ebsa285_leds[i].name;
+		led->cdev.brightness_set = ebsa285_led_set;
+		led->cdev.brightness_get = ebsa285_led_get;
+		led->cdev.default_trigger = ebsa285_leds[i].trigger;
+		led->mask = BIT(i);
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(ebsa285_leds_init);
+
 MACHINE_START(EBSA285, "EBSA285")
 	/* Maintainer: Russell King */
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index cac9f67..a0a31bb 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -12,9 +12,10 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <asm/hardware/dec21285.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 #include <asm/system_misc.h>
@@ -27,13 +28,6 @@
 #define GP1_IO_BASE		0x338
 #define GP2_IO_BASE		0x33a
 
-
-#ifdef CONFIG_LEDS
-#define DEFAULT_LEDS	0
-#else
-#define DEFAULT_LEDS	GPIO_GREEN_LED
-#endif
-
 /*
  * Winbond WB83977F accessibility stuff
  */
@@ -611,15 +605,9 @@ static void __init rwa010_init(void)
 static int __init nw_hw_init(void)
 {
 	if (machine_is_netwinder()) {
-		unsigned long flags;
-
 		wb977_init();
 		cpld_init();
 		rwa010_init();
-
-		raw_spin_lock_irqsave(&nw_gpio_lock, flags);
-		nw_gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS);
-		raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
 	}
 	return 0;
 }
@@ -672,6 +660,100 @@ static void netwinder_restart(char mode, const char *cmd)
 	}
 }
 
+/* LEDs */
+struct netwinder_led {
+	struct led_classdev     cdev;
+	u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} netwinder_leds[] = {
+	{ "netwinder:green", "heartbeat", },
+	{ "netwinder:red", "cpu0", },
+};
+
+/*
+ * The LED control in Netwinder is reversed:
+ *  - setting bit means turn off LED
+ *  - clearing bit means turn on LED
+ */
+static void netwinder_led_set(struct led_classdev *cdev,
+		enum led_brightness b)
+{
+	struct netwinder_led *led = container_of(cdev,
+			struct netwinder_led, cdev);
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(&nw_gpio_lock, flags);
+	reg = nw_gpio_read();
+	if (b != LED_OFF)
+		reg &= ~led->mask;
+	else
+		reg |= led->mask;
+	nw_gpio_modify_op(led->mask, reg);
+	spin_unlock_irqrestore(&nw_gpio_lock, flags);
+}
+
+static enum led_brightness netwinder_led_get(struct led_classdev *cdev)
+{
+	struct netwinder_led *led = container_of(cdev,
+			struct netwinder_led, cdev);
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(&nw_gpio_lock, flags);
+	reg = nw_gpio_read();
+	spin_unlock_irqrestore(&nw_gpio_lock, flags);
+
+	return (reg & led->mask) ? LED_OFF : LED_FULL;
+}
+
+static int __init netwinder_leds_init(void)
+{
+	int i;
+
+	if (!machine_is_netwinder())
+		return -ENODEV;
+
+	for (i = 0; i < ARRAY_SIZE(netwinder_leds); i++) {
+		struct netwinder_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = netwinder_leds[i].name;
+		led->cdev.brightness_set = netwinder_led_set;
+		led->cdev.brightness_get = netwinder_led_get;
+		led->cdev.default_trigger = netwinder_leds[i].trigger;
+
+		if (i == 0)
+			led->mask = GPIO_GREEN_LED;
+		else
+			led->mask = GPIO_RED_LED;
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(netwinder_leds_init);
+
 MACHINE_START(NETWINDER, "Rebel-NetWinder")
 	/* Maintainer: Russell King/Rebel.com */
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-footbridge/netwinder-leds.c b/arch/arm/mach-footbridge/netwinder-leds.c
deleted file mode 100644
index 5a2bd89..0000000
--- a/arch/arm/mach-footbridge/netwinder-leds.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- *  linux/arch/arm/mach-footbridge/netwinder-leds.c
- *
- *  Copyright (C) 1998-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * NetWinder LED control routines.
- *
- * The Netwinder uses the leds as follows:
- *  - Green - toggles state every 50 timer interrupts
- *  - Red   - On if the system is not idle
- *
- * Changelog:
- *   02-05-1999	RMK	Various cleanups
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-static char led_state;
-static char hw_led_state;
-
-static DEFINE_RAW_SPINLOCK(leds_lock);
-
-static void netwinder_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	raw_spin_lock_irqsave(&leds_lock, flags);
-
-	switch (evt) {
-	case led_start:
-		led_state |= LED_STATE_ENABLED;
-		hw_led_state = GPIO_GREEN_LED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= GPIO_GREEN_LED;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~GPIO_RED_LED;
-		break;
-
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= GPIO_RED_LED;
-		break;
-#endif
-
-	case led_halted:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= GPIO_RED_LED;
-		break;
-
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= GPIO_GREEN_LED;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~GPIO_GREEN_LED;
-		break;
-
-	case led_amber_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= GPIO_GREEN_LED | GPIO_RED_LED;
-		break;
-
-	case led_amber_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~(GPIO_GREEN_LED | GPIO_RED_LED);
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= GPIO_RED_LED;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~GPIO_RED_LED;
-		break;
-
-	default:
-		break;
-	}
-
-	raw_spin_unlock_irqrestore(&leds_lock, flags);
-
-	if  (led_state & LED_STATE_ENABLED) {
-		raw_spin_lock_irqsave(&nw_gpio_lock, flags);
-		nw_gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state);
-		raw_spin_unlock_irqrestore(&nw_gpio_lock, flags);
-	}
-}
-
-static int __init leds_init(void)
-{
-	if (machine_is_netwinder())
-		leds_event = netwinder_leds_event;
-
-	leds_event(led_start);
-
-	return 0;
-}
-
-__initcall(leds_init);
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:27 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:27 +0800
Subject: [PATCH 12/18] char: nwflash: remove old led event code
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-13-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 drivers/char/nwflash.c |   34 ----------------------------------
 1 files changed, 0 insertions(+), 34 deletions(-)

diff --git a/drivers/char/nwflash.c b/drivers/char/nwflash.c
index d45c334..a0e2f7d 100644
--- a/drivers/char/nwflash.c
+++ b/drivers/char/nwflash.c
@@ -30,7 +30,6 @@
 
 #include <asm/hardware/dec21285.h>
 #include <asm/io.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/uaccess.h>
 
@@ -179,9 +178,6 @@ static ssize_t flash_write(struct file *file, const char __user *buf,
 
 	written = 0;
 
-	leds_event(led_claim);
-	leds_event(led_green_on);
-
 	nBlock = (int) p >> 16;	//block # of 64K bytes
 
 	/*
@@ -258,11 +254,6 @@ static ssize_t flash_write(struct file *file, const char __user *buf,
 			printk(KERN_DEBUG "flash_write: written 0x%X bytes OK.\n", written);
 	}
 
-	/*
-	 * restore reg on exit
-	 */
-	leds_event(led_release);
-
 	mutex_unlock(&nwflash_mutex);
 
 	return written;
@@ -334,11 +325,6 @@ static int erase_block(int nBlock)
 	int temp, temp1;
 
 	/*
-	 * orange LED == erase
-	 */
-	leds_event(led_amber_on);
-
-	/*
 	 * reset footbridge to the correct offset 0 (...0..3)
 	 */
 	*CSR_ROMWRITEREG = 0;
@@ -446,12 +432,6 @@ static int write_block(unsigned long p, const char __user *buf, int count)
 	unsigned long timeout;
 	unsigned long timeout1;
 
-	/*
-	 * red LED == write
-	 */
-	leds_event(led_amber_off);
-	leds_event(led_red_on);
-
 	pWritePtr = (unsigned char *) ((unsigned int) (FLASH_BASE + p));
 
 	/*
@@ -558,17 +538,9 @@ static int write_block(unsigned long p, const char __user *buf, int count)
 					       pWritePtr - FLASH_BASE);
 
 				/*
-				 * no LED == waiting
-				 */
-				leds_event(led_amber_off);
-				/*
 				 * wait couple ms
 				 */
 				msleep(10);
-				/*
-				 * red LED == write
-				 */
-				leds_event(led_red_on);
 
 				goto WriteRetry;
 			} else {
@@ -583,12 +555,6 @@ static int write_block(unsigned long p, const char __user *buf, int count)
 		}
 	}
 
-	/*
-	 * green LED == read/verify
-	 */
-	leds_event(led_amber_off);
-	leds_event(led_green_on);
-
 	msleep(10);
 
 	pWritePtr = (unsigned char *) ((unsigned int) (FLASH_BASE + p));
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:29 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:29 +0800
Subject: [PATCH 14/18] ARM: plat-samsung: remove including old leds event API
 header file
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-15-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/plat-samsung/time.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index 4dcb11c..60552e2 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -28,7 +28,6 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 
 #include <asm/irq.h>
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:28 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:28 +0800
Subject: [PATCH 13/18] ARM: mach-pxa: retire custom LED code
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-14-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-pxa/Makefile         |    8 --
 arch/arm/mach-pxa/idp.c            |   79 +++++++++++++++++++++++
 arch/arm/mach-pxa/leds-idp.c       |  115 ---------------------------------
 arch/arm/mach-pxa/leds-lubbock.c   |  124 ------------------------------------
 arch/arm/mach-pxa/leds-mainstone.c |  119 ----------------------------------
 arch/arm/mach-pxa/leds.c           |   32 ---------
 arch/arm/mach-pxa/leds.h           |   13 ----
 arch/arm/mach-pxa/lubbock.c        |   93 +++++++++++++++++++++++++++
 arch/arm/mach-pxa/mainstone.c      |   92 ++++++++++++++++++++++++++
 9 files changed, 264 insertions(+), 411 deletions(-)
 delete mode 100644 arch/arm/mach-pxa/leds-idp.c
 delete mode 100644 arch/arm/mach-pxa/leds-lubbock.c
 delete mode 100644 arch/arm/mach-pxa/leds-mainstone.c
 delete mode 100644 arch/arm/mach-pxa/leds.c
 delete mode 100644 arch/arm/mach-pxa/leds.h

diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index be0f7df..d4337e3 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -95,12 +95,4 @@ obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR)	+= raumfeld.o
 obj-$(CONFIG_MACH_RAUMFELD_SPEAKER)	+= raumfeld.o
 obj-$(CONFIG_MACH_ZIPIT2)	+= z2.o
 
-# Support for blinky lights
-led-y := leds.o
-led-$(CONFIG_ARCH_LUBBOCK)	+= leds-lubbock.o
-led-$(CONFIG_MACH_MAINSTONE)	+= leds-mainstone.o
-led-$(CONFIG_ARCH_PXA_IDP)	+= leds-idp.o
-
-obj-$(CONFIG_LEDS)		+= $(led-y)
-
 obj-$(CONFIG_TOSA_BT)		+= tosa-bt.o
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 6ff466b..3c58d95 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -191,6 +191,85 @@ static void __init idp_map_io(void)
 	iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
 }
 
+/* LEDs */
+struct idp_led {
+	struct led_classdev     cdev;
+	u8                      mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} idp_leds[] = {
+	{ "idp:green", "heartbeat", },
+	{ "idp:red", "cpu0", },
+};
+
+static void idp_led_set(struct led_classdev *cdev,
+		enum led_brightness b)
+{
+	struct idp_led *led = container_of(cdev,
+			struct idp_led, cdev);
+	u32 reg = IDP_CPLD_LED_CONTROL;
+
+	if (b != LED_OFF)
+		reg &= ~led->mask;
+	else
+		reg |= led->mask;
+
+	IDP_CPLD_LED_CONTROL = reg;
+}
+
+static enum led_brightness idp_led_get(struct led_classdev *cdev)
+{
+	struct idp_led *led = container_of(cdev,
+			struct idp_led, cdev);
+
+	return (IDP_CPLD_LED_CONTROL & led->mask) ? LED_OFF : LED_FULL;
+}
+
+static int __init idp_leds_init(void)
+{
+	int i;
+
+	if (!machine_is_pxa_idp())
+		return -ENODEV;
+
+	for (i = 0; i < ARRAY_SIZE(idp_leds); i++) {
+		struct idp_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = idp_leds[i].name;
+		led->cdev.brightness_set = idp_led_set;
+		led->cdev.brightness_get = idp_led_get;
+		led->cdev.default_trigger = idp_leds[i].trigger;
+
+		if (i == 0)
+			led->mask = IDP_HB_LED;
+		else
+			led->mask = IDP_BUSY_LED;
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(idp_leds_init);
 
 MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
 	/* Maintainer: Vibren Technologies */
diff --git a/arch/arm/mach-pxa/leds-idp.c b/arch/arm/mach-pxa/leds-idp.c
deleted file mode 100644
index 06b0600..0000000
--- a/arch/arm/mach-pxa/leds-idp.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-idp.c
- *
- * Copyright (C) 2000 John Dorsey <john+ at cs.cmu.edu>
- *
- * Copyright (c) 2001 Jeff Sutherland <jeffs at accelent.com>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Macros for actual LED manipulation should be in machine specific
- * files in this 'mach' directory.
- */
-
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include <mach/pxa25x.h>
-#include <mach/idp.h>
-
-#include "leds.h"
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void idp_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = IDP_HB_LED | IDP_BUSY_LED;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= IDP_HB_LED;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~IDP_BUSY_LED;
-		break;
-
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= IDP_BUSY_LED;
-		break;
-#endif
-
-	case led_halted:
-		break;
-
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= IDP_HB_LED;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~IDP_HB_LED;
-		break;
-
-	case led_amber_on:
-		break;
-
-	case led_amber_off:
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= IDP_BUSY_LED;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~IDP_BUSY_LED;
-		break;
-
-	default:
-		break;
-	}
-
-	if  (led_state & LED_STATE_ENABLED)
-		IDP_CPLD_LED_CONTROL = ( (IDP_CPLD_LED_CONTROL | IDP_LEDS_MASK) & ~hw_led_state);
-	else
-		IDP_CPLD_LED_CONTROL |= IDP_LEDS_MASK;
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds-lubbock.c b/arch/arm/mach-pxa/leds-lubbock.c
deleted file mode 100644
index 0bd85c8..0000000
--- a/arch/arm/mach-pxa/leds-lubbock.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-lubbock.c
- *
- * Copyright (C) 2000 John Dorsey <john+ at cs.cmu.edu>
- *
- * Copyright (c) 2001 Jeff Sutherland <jeffs at accelent.com>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Major surgery on April 2004 by Nicolas Pitre for less global
- * namespace collision.  Mostly adapted the Mainstone version.
- */
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <mach/pxa25x.h>
-#include <mach/lubbock.h>
-
-#include "leds.h"
-
-/*
- * 8 discrete leds available for general use:
- *
- * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
- * so be sure to not monkey with them here.
- */
-
-#define D28			(1 << 0)
-#define D27			(1 << 1)
-#define D26			(1 << 2)
-#define D25			(1 << 3)
-#define D24			(1 << 4)
-#define D23			(1 << 5)
-#define D22			(1 << 6)
-#define D21			(1 << 7)
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void lubbock_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = 0;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		hw_led_state ^= D26;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		hw_led_state &= ~D27;
-		break;
-
-	case led_idle_end:
-		hw_led_state |= D27;
-		break;
-#endif
-
-	case led_halted:
-		break;
-
-	case led_green_on:
-		hw_led_state |= D21;
-		break;
-
-	case led_green_off:
-		hw_led_state &= ~D21;
-		break;
-
-	case led_amber_on:
-		hw_led_state |= D22;
-		break;
-
-	case led_amber_off:
-		hw_led_state &= ~D22;
-		break;
-
-	case led_red_on:
-		hw_led_state |= D23;
-		break;
-
-	case led_red_off:
-		hw_led_state &= ~D23;
-		break;
-
-	default:
-		break;
-	}
-
-	if  (led_state & LED_STATE_ENABLED)
-		LUB_DISC_BLNK_LED = (LUB_DISC_BLNK_LED | 0xff) & ~hw_led_state;
-	else
-		LUB_DISC_BLNK_LED |= 0xff;
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds-mainstone.c b/arch/arm/mach-pxa/leds-mainstone.c
deleted file mode 100644
index 4058ab3..0000000
--- a/arch/arm/mach-pxa/leds-mainstone.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds-mainstone.c
- *
- * Author:     Nicolas Pitre
- * Created:    Nov 05, 2002
- * Copyright:  MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include <mach/pxa27x.h>
-#include <mach/mainstone.h>
-
-#include "leds.h"
-
-
-/* 8 discrete leds available for general use: */
-#define D28			(1 << 0)
-#define D27			(1 << 1)
-#define D26			(1 << 2)
-#define D25			(1 << 3)
-#define D24			(1 << 4)
-#define D23			(1 << 5)
-#define D22			(1 << 6)
-#define D21			(1 << 7)
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void mainstone_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = 0;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		hw_led_state ^= D26;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		hw_led_state &= ~D27;
-		break;
-
-	case led_idle_end:
-		hw_led_state |= D27;
-		break;
-#endif
-
-	case led_halted:
-		break;
-
-	case led_green_on:
-		hw_led_state |= D21;
-		break;
-
-	case led_green_off:
-		hw_led_state &= ~D21;
-		break;
-
-	case led_amber_on:
-		hw_led_state |= D22;
-		break;
-
-	case led_amber_off:
-		hw_led_state &= ~D22;
-		break;
-
-	case led_red_on:
-		hw_led_state |= D23;
-		break;
-
-	case led_red_off:
-		hw_led_state &= ~D23;
-		break;
-
-	default:
-		break;
-	}
-
-	if  (led_state & LED_STATE_ENABLED)
-		MST_LEDCTRL = (MST_LEDCTRL | 0xff) & ~hw_led_state;
-	else
-		MST_LEDCTRL |= 0xff;
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-pxa/leds.c b/arch/arm/mach-pxa/leds.c
deleted file mode 100644
index bbe4d5f..0000000
--- a/arch/arm/mach-pxa/leds.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/leds.c
- *
- * xscale LEDs dispatcher
- *
- * Copyright (C) 2001 Nicolas Pitre
- *
- * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc.
- */
-#include <linux/compiler.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include "leds.h"
-
-static int __init
-pxa_leds_init(void)
-{
-	if (machine_is_lubbock())
-		leds_event = lubbock_leds_event;
-	if (machine_is_mainstone())
-		leds_event = mainstone_leds_event;
-	if (machine_is_pxa_idp())
-		leds_event = idp_leds_event;
-
-	leds_event(led_start);
-	return 0;
-}
-
-core_initcall(pxa_leds_init);
diff --git a/arch/arm/mach-pxa/leds.h b/arch/arm/mach-pxa/leds.h
deleted file mode 100644
index 7f0dfe0..0000000
--- a/arch/arm/mach-pxa/leds.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-pxa/leds.h
- *
- * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc.
- *
- * blinky lights for various PXA-based systems:
- *
- */
-
-extern void idp_leds_event(led_event_t evt);
-extern void lubbock_leds_event(led_event_t evt);
-extern void mainstone_leds_event(led_event_t evt);
-extern void trizeps4_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 6bb3f47..f3a300f 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/syscore_ops.h>
 #include <linux/major.h>
@@ -23,6 +24,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/smc91x.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -549,6 +552,96 @@ static void __init lubbock_map_io(void)
 	PCFR |= PCFR_OPDE;
 }
 
+/*
+ * Driver for the 8 discrete LEDs available for general use:
+ * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
+ * so be sure to not monkey with them here.
+ */
+
+struct lubbock_led {
+	struct led_classdev	cdev;
+	u8			mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} lubbock_leds[] = {
+	{ "lubbock:D28", "default-on", },
+	{ "lubbock:D27", "cpu0", },
+	{ "lubbock:D26", "heartbeat" },
+	{ "lubbock:D25", },
+	{ "lubbock:D24", },
+	{ "lubbock:D23", },
+	{ "lubbock:D22", },
+	{ "lubbock:D21", },
+};
+
+static void lubbock_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
+{
+	struct lubbock_led *led = container_of(cdev,
+					 struct lubbock_led, cdev);
+	u32 reg = LUB_DISC_BLNK_LED;
+
+	if (b != LED_OFF)
+		reg |= led->mask;
+	else
+		reg &= ~led->mask;
+
+	LUB_DISC_BLNK_LED = reg;
+}
+
+static enum led_brightness lubbock_led_get(struct led_classdev *cdev)
+{
+	struct lubbock_led *led = container_of(cdev,
+					 struct lubbock_led, cdev);
+	u32 reg = LUB_DISC_BLNK_LED;
+
+	return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init lubbock_leds_init(void)
+{
+	int i;
+
+	if (!machine_is_lubbock())
+		return -ENODEV;
+
+	/* All ON */
+	LUB_DISC_BLNK_LED |= 0xff;
+	for (i = 0; i < ARRAY_SIZE(lubbock_leds); i++) {
+		struct lubbock_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = lubbock_leds[i].name;
+		led->cdev.brightness_set = lubbock_led_set;
+		led->cdev.brightness_get = lubbock_led_get;
+		led->cdev.default_trigger = lubbock_leds[i].trigger;
+		led->mask = BIT(i);
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(lubbock_leds_init);
+
 MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
 	/* Maintainer: MontaVista Software Inc. */
 	.map_io		= lubbock_map_io,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 1aebaf7..2ef1570 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -28,6 +28,8 @@
 #include <linux/pwm_backlight.h>
 #include <linux/smc91x.h>
 #include <linux/i2c/pxa-i2c.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -613,6 +615,96 @@ static void __init mainstone_map_io(void)
  	PCFR = 0x66;
 }
 
+/*
+ * Driver for the 8 discrete LEDs available for general use:
+ * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
+ * so be sure to not monkey with them here.
+ */
+
+struct mainstone_led {
+	struct led_classdev	cdev;
+	u8			mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} mainstone_leds[] = {
+	{ "mainstone:D28", "default-on", },
+	{ "mainstone:D27", "cpu0", },
+	{ "mainstone:D26", "heartbeat" },
+	{ "mainstone:D25", },
+	{ "mainstone:D24", },
+	{ "mainstone:D23", },
+	{ "mainstone:D22", },
+	{ "mainstone:D21", },
+};
+
+static void mainstone_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
+{
+	struct mainstone_led *led = container_of(cdev,
+					 struct mainstone_led, cdev);
+	u32 reg = MST_LEDCTRL;
+
+	if (b != LED_OFF)
+		reg |= led->mask;
+	else
+		reg &= ~led->mask;
+
+	MST_LEDCTRL = reg;
+}
+
+static enum led_brightness mainstone_led_get(struct led_classdev *cdev)
+{
+	struct mainstone_led *led = container_of(cdev,
+					 struct mainstone_led, cdev);
+	u32 reg = MST_LEDCTRL;
+
+	return (reg & led->mask) ? LED_FULL : LED_OFF;
+}
+
+static int __init mainstone_leds_init(void)
+{
+	int i;
+
+	if (!machine_is_mainstone())
+		return -ENODEV;
+
+	/* All ON */
+	MST_LEDCTRL |= 0xff;
+	for (i = 0; i < ARRAY_SIZE(mainstone_leds); i++) {
+		struct mainstone_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = mainstone_leds[i].name;
+		led->cdev.brightness_set = mainstone_led_set;
+		led->cdev.brightness_get = mainstone_led_get;
+		led->cdev.default_trigger = mainstone_leds[i].trigger;
+		led->mask = BIT(i);
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(mainstone_leds_init);
+
 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
 	/* Maintainer: MontaVista Software Inc. */
 	.atag_offset	= 0x100,	/* BLOB boot parameter setting */
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:30 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:30 +0800
Subject: [PATCH 15/18] ARM: mach-pnx4008: remove including old leds event API
 header file
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-16-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-pnx4008/time.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
index 0cfe8af..47a7ae9 100644
--- a/arch/arm/mach-pnx4008/time.c
+++ b/arch/arm/mach-pnx4008/time.c
@@ -25,7 +25,6 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
-#include <asm/leds.h>
 #include <asm/mach/time.h>
 #include <asm/errno.h>
 
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:31 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:31 +0800
Subject: [PATCH 16/18] ARM: mach-omap1: retire custom LED code
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-17-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
Acked-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/Makefile          |    8 -
 arch/arm/mach-omap1/board-h2.c        |   32 ++++
 arch/arm/mach-omap1/board-h3.c        |   32 ++++
 arch/arm/mach-omap1/board-osk.c       |   33 ++++
 arch/arm/mach-omap1/leds-h2p2-debug.c |  166 -------------------
 arch/arm/mach-omap1/leds-innovator.c  |   98 -----------
 arch/arm/mach-omap1/leds-osk.c        |  113 -------------
 arch/arm/mach-omap1/leds.c            |   69 --------
 arch/arm/mach-omap1/leds.h            |    3 -
 arch/arm/mach-omap1/time.c            |    1 -
 arch/arm/mach-omap1/timer32k.c        |    1 -
 arch/arm/plat-omap/Kconfig            |    3 +-
 arch/arm/plat-omap/debug-leds.c       |  293 ++++++++-------------------------
 13 files changed, 165 insertions(+), 687 deletions(-)
 delete mode 100644 arch/arm/mach-omap1/leds-h2p2-debug.c
 delete mode 100644 arch/arm/mach-omap1/leds-innovator.c
 delete mode 100644 arch/arm/mach-omap1/leds-osk.c
 delete mode 100644 arch/arm/mach-omap1/leds.c
 delete mode 100644 arch/arm/mach-omap1/leds.h

diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 9923f92..e63e6e7 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -56,14 +56,6 @@ obj-$(CONFIG_ARCH_OMAP850)		+= gpio7xx.o
 obj-$(CONFIG_ARCH_OMAP15XX)		+= gpio15xx.o
 obj-$(CONFIG_ARCH_OMAP16XX)		+= gpio16xx.o
 
-# LEDs support
-led-$(CONFIG_MACH_OMAP_H2)		+= leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_H3)		+= leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_INNOVATOR)	+= leds-innovator.o
-led-$(CONFIG_MACH_OMAP_PERSEUS2)	+= leds-h2p2-debug.o
-led-$(CONFIG_MACH_OMAP_OSK)		+= leds-osk.o
-obj-$(CONFIG_LEDS)			+= $(led-y)
-
 ifneq ($(CONFIG_FB_OMAP),)
 obj-y += lcd_dma.o
 endif
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 553a2e5..6a22696 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -31,6 +31,7 @@
 #include <linux/i2c/tps65010.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
+#include <linux/leds.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -324,12 +325,39 @@ static struct platform_device h2_irda_device = {
 	.resource	= h2_irda_resources,
 };
 
+static struct gpio_led h2_gpio_led_pins[] = {
+	{
+		.name		= "h2:red",
+		.default_trigger = "heartbeat",
+		.gpio		= 3,
+	},
+	{
+		.name		= "h2:green",
+		.default_trigger = "cpu0",
+		.gpio		= OMAP_MPUIO(4),
+	},
+};
+
+static struct gpio_led_platform_data h2_gpio_led_data = {
+	.leds		= h2_gpio_led_pins,
+	.num_leds	= ARRAY_SIZE(h2_gpio_led_pins),
+};
+
+static struct platform_device h2_gpio_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &h2_gpio_led_data,
+	},
+};
+
 static struct platform_device *h2_devices[] __initdata = {
 	&h2_nor_device,
 	&h2_nand_device,
 	&h2_smc91x_device,
 	&h2_irda_device,
 	&h2_kp_device,
+	&h2_gpio_leds,
 };
 
 static void __init h2_init_smc91x(void)
@@ -424,6 +452,10 @@ static void __init h2_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	/* GPIO based LEDs */
+	omap_cfg_reg(P18_1610_GPIO3);
+	omap_cfg_reg(MPUIO4);
+
 	h2_smc91x_resources[1].start = gpio_to_irq(0);
 	h2_smc91x_resources[1].end = gpio_to_irq(0);
 	platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 4c19f4c..4acdc71 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -31,6 +31,7 @@
 #include <linux/i2c/tps65010.h>
 #include <linux/smc91x.h>
 #include <linux/omapfb.h>
+#include <linux/leds.h>
 
 #include <asm/setup.h>
 #include <asm/page.h>
@@ -341,6 +342,32 @@ static struct spi_board_info h3_spi_board_info[] __initdata = {
 	},
 };
 
+static struct gpio_led h3_gpio_led_pins[] = {
+	{
+		.name		= "h3:red",
+		.default_trigger = "heartbeat",
+		.gpio		= 3,
+	},
+	{
+		.name		= "h3:green",
+		.default_trigger = "cpu0",
+		.gpio		= OMAP_MPUIO(4),
+	},
+};
+
+static struct gpio_led_platform_data h3_gpio_led_data = {
+	.leds		= h3_gpio_led_pins,
+	.num_leds	= ARRAY_SIZE(h3_gpio_led_pins),
+};
+
+static struct platform_device h3_gpio_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &h3_gpio_led_data,
+	},
+};
+
 static struct platform_device *devices[] __initdata = {
 	&nor_device,
 	&nand_device,
@@ -348,6 +375,7 @@ static struct platform_device *devices[] __initdata = {
 	&intlat_device,
 	&h3_kp_device,
 	&h3_lcd_device,
+	&h3_gpio_leds,
 };
 
 static struct omap_usb_config h3_usb_config __initdata = {
@@ -415,6 +443,10 @@ static void __init h3_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
+	/* GPIO based LEDs */
+	omap_cfg_reg(P18_1610_GPIO3);
+	omap_cfg_reg(MPUIO4);
+
 	smc91x_resources[1].start = gpio_to_irq(40);
 	smc91x_resources[1].end = gpio_to_irq(40);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index a5f85dd..de8d1f3 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -380,10 +380,37 @@ static struct platform_device osk5912_lcd_device = {
 	.id		= -1,
 };
 
+static struct gpio_led mistral_gpio_led_pins[] = {
+	{
+		.name		= "mistral:red",
+		.default_trigger = "heartbeat",
+		.gpio		= 3,
+	},
+	{
+		.name		= "mistral:green",
+		.default_trigger = "cpu0",
+		.gpio		= OMAP_MPUIO(4),
+	},
+};
+
+static struct gpio_led_platform_data mistral_gpio_led_data = {
+	.leds		= mistral_gpio_led_pins,
+	.num_leds	= ARRAY_SIZE(mistral_gpio_led_pins),
+};
+
+static struct platform_device mistral_gpio_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &mistral_gpio_led_data,
+	},
+};
+
 static struct platform_device *mistral_devices[] __initdata = {
 	&osk5912_kp_device,
 	&mistral_bl_device,
 	&osk5912_lcd_device,
+	&mistral_gpio_leds,
 };
 
 static int mistral_get_pendown_state(void)
@@ -508,6 +535,12 @@ static void __init osk_mistral_init(void)
 	if (gpio_request(2, "lcd_pwr") == 0)
 		gpio_direction_output(2, 1);
 
+	/*
+	 * GPIO based LEDs
+	 */
+	omap_cfg_reg(P18_1610_GPIO3);
+	omap_cfg_reg(MPUIO4);
+
 	i2c_register_board_info(1, mistral_i2c_board_info,
 			ARRAY_SIZE(mistral_i2c_board_info));
 
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
deleted file mode 100644
index f6b14a1..0000000
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-h2p2-debug.c
- *
- * Copyright 2003 by Texas Instruments Incorporated
- *
- * There are 16 LEDs on the debug board (all green); four may be used
- * for logical 'green', 'amber', 'red', and 'blue' (after "claiming").
- *
- * The "surfer" expansion board and H2 sample board also have two-color
- * green+red LEDs (in parallel), used here for timer and idle indicators.
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include <plat/fpga.h>
-
-#include "leds.h"
-
-
-#define GPIO_LED_RED		3
-#define GPIO_LED_GREEN		OMAP_MPUIO(4)
-
-
-#define LED_STATE_ENABLED	0x01
-#define LED_STATE_CLAIMED	0x02
-#define LED_TIMER_ON		0x04
-
-#define GPIO_IDLE		GPIO_LED_GREEN
-#define GPIO_TIMER		GPIO_LED_RED
-
-
-void h2p2_dbg_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	static struct h2p2_dbg_fpga __iomem *fpga;
-	static u16 led_state, hw_led_state;
-
-	local_irq_save(flags);
-
-	if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-		goto done;
-
-	switch (evt) {
-	case led_start:
-		if (!fpga)
-			fpga = ioremap(H2P2_DBG_FPGA_START,
-						H2P2_DBG_FPGA_SIZE);
-		if (fpga) {
-			led_state |= LED_STATE_ENABLED;
-			__raw_writew(~0, &fpga->leds);
-		}
-		break;
-
-	case led_stop:
-	case led_halted:
-		/* all leds off during suspend or shutdown */
-
-		if (! machine_is_omap_perseus2()) {
-			gpio_set_value(GPIO_TIMER, 0);
-			gpio_set_value(GPIO_IDLE, 0);
-		}
-
-		__raw_writew(~0, &fpga->leds);
-		led_state &= ~LED_STATE_ENABLED;
-		if (evt == led_halted) {
-			iounmap(fpga);
-			fpga = NULL;
-		}
-
-		goto done;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		led_state ^= LED_TIMER_ON;
-
-		if (machine_is_omap_perseus2())
-			hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
-		else {
-			gpio_set_value(GPIO_TIMER, led_state & LED_TIMER_ON);
-			goto done;
-		}
-
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (machine_is_omap_perseus2())
-			hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
-		else {
-			gpio_set_value(GPIO_IDLE, 1);
-			goto done;
-		}
-
-		break;
-
-	case led_idle_end:
-		if (machine_is_omap_perseus2())
-			hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
-		else {
-			gpio_set_value(GPIO_IDLE, 0);
-			goto done;
-		}
-
-		break;
-#endif
-
-	case led_green_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
-		break;
-	case led_green_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
-		break;
-
-	case led_amber_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
-		break;
-	case led_amber_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
-		break;
-
-	case led_red_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_RED;
-		break;
-	case led_red_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
-		break;
-
-	case led_blue_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
-		break;
-	case led_blue_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
-		break;
-
-	default:
-		break;
-	}
-
-
-	/*
-	 *  Actually burn the LEDs
-	 */
-	if (led_state & LED_STATE_ENABLED)
-		__raw_writew(~hw_led_state, &fpga->leds);
-
-done:
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds-innovator.c b/arch/arm/mach-omap1/leds-innovator.c
deleted file mode 100644
index 3a066ee..0000000
--- a/arch/arm/mach-omap1/leds-innovator.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-innovator.c
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-void innovator_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = 0;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		hw_led_state = 0;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= 0;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= 0;
-		break;
-
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~0;
-		break;
-#endif
-
-	case led_halted:
-		break;
-
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~0;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= 0;
-		break;
-
-	case led_amber_on:
-		break;
-
-	case led_amber_off:
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~0;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= 0;
-		break;
-
-	default:
-		break;
-	}
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds-osk.c b/arch/arm/mach-omap1/leds-osk.c
deleted file mode 100644
index 936ed42..0000000
--- a/arch/arm/mach-omap1/leds-osk.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds-osk.c
- *
- * LED driver for OSK with optional Mistral QVGA board
- */
-#include <linux/gpio.h>
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	(1 << 0)
-#define LED_STATE_CLAIMED	(1 << 1)
-static u8 led_state;
-
-#define	TIMER_LED		(1 << 3)	/* Mistral board */
-#define	IDLE_LED		(1 << 4)	/* Mistral board */
-static u8 hw_led_state;
-
-
-#ifdef	CONFIG_OMAP_OSK_MISTRAL
-
-/* For now, all system indicators require the Mistral board, since that
- * LED can be manipulated without a task context.  This LED is either red,
- * or green, but not both; it can't give the full "disco led" effect.
- */
-
-#define GPIO_LED_RED		3
-#define GPIO_LED_GREEN		OMAP_MPUIO(4)
-
-static void mistral_setled(void)
-{
-	int	red = 0;
-	int	green = 0;
-
-	if (hw_led_state & TIMER_LED)
-		red = 1;
-	else if (hw_led_state & IDLE_LED)
-		green = 1;
-	/* else both sides are disabled */
-
-	gpio_set_value(GPIO_LED_GREEN, green);
-	gpio_set_value(GPIO_LED_RED, red);
-}
-
-#endif
-
-void osk_leds_event(led_event_t evt)
-{
-	unsigned long	flags;
-	u16		leds;
-
-	local_irq_save(flags);
-
-	if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-		goto done;
-
-	leds = hw_led_state;
-	switch (evt) {
-	case led_start:
-		led_state |= LED_STATE_ENABLED;
-		hw_led_state = 0;
-		leds = ~0;
-		break;
-
-	case led_halted:
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		hw_led_state = 0;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		leds = ~0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-#ifdef	CONFIG_OMAP_OSK_MISTRAL
-
-	case led_timer:
-		hw_led_state ^= TIMER_LED;
-		mistral_setled();
-		break;
-
-	case led_idle_start:	/* idle == off */
-		hw_led_state &= ~IDLE_LED;
-		mistral_setled();
-		break;
-
-	case led_idle_end:
-		hw_led_state |= IDLE_LED;
-		mistral_setled();
-		break;
-
-#endif	/* CONFIG_OMAP_OSK_MISTRAL */
-
-	default:
-		break;
-	}
-
-	leds ^= hw_led_state;
-
-done:
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c
deleted file mode 100644
index ae6dd93..0000000
--- a/arch/arm/mach-omap1/leds.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * linux/arch/arm/mach-omap1/leds.c
- *
- * OMAP LEDs dispatcher
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include <plat/mux.h>
-
-#include "leds.h"
-
-static int __init
-omap_leds_init(void)
-{
-	if (!cpu_class_is_omap1())
-		return -ENODEV;
-
-	if (machine_is_omap_innovator())
-		leds_event = innovator_leds_event;
-
-	else if (machine_is_omap_h2()
-			|| machine_is_omap_h3()
-			|| machine_is_omap_perseus2())
-		leds_event = h2p2_dbg_leds_event;
-
-	else if (machine_is_omap_osk())
-		leds_event = osk_leds_event;
-
-	else
-		return -1;
-
-	if (machine_is_omap_h2()
-			|| machine_is_omap_h3()
-#ifdef	CONFIG_OMAP_OSK_MISTRAL
-			|| machine_is_omap_osk()
-#endif
-			) {
-
-		/* LED1/LED2 pins can be used as GPIO (as done here), or by
-		 * the LPG (works even in deep sleep!), to drive a bicolor
-		 * LED on the H2 sample board, and another on the H2/P2
-		 * "surfer" expansion board.
-		 *
-		 * The same pins drive a LED on the OSK Mistral board, but
-		 * that's a different kind of LED (just one color at a time).
-		 */
-		omap_cfg_reg(P18_1610_GPIO3);
-		if (gpio_request(3, "LED red") == 0)
-			gpio_direction_output(3, 1);
-		else
-			printk(KERN_WARNING "LED: can't get GPIO3/red?\n");
-
-		omap_cfg_reg(MPUIO4);
-		if (gpio_request(OMAP_MPUIO(4), "LED green") == 0)
-			gpio_direction_output(OMAP_MPUIO(4), 1);
-		else
-			printk(KERN_WARNING "LED: can't get MPUIO4/green?\n");
-	}
-
-	leds_event(led_start);
-	return 0;
-}
-
-__initcall(omap_leds_init);
diff --git a/arch/arm/mach-omap1/leds.h b/arch/arm/mach-omap1/leds.h
deleted file mode 100644
index a1e9fed..0000000
--- a/arch/arm/mach-omap1/leds.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern void innovator_leds_event(led_event_t evt);
-extern void h2p2_dbg_leds_event(led_event_t evt);
-extern void osk_leds_event(led_event_t evt);
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 4d8dd9a..050ef74 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -44,7 +44,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/sched_clock.h>
 
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 325b9a0..ac7e713 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -46,7 +46,6 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 
-#include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ce1e9b9..137ad46 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -40,9 +40,8 @@ config OMAP_DEBUG_DEVICES
 	  For debug cards on TI reference boards.
 
 config OMAP_DEBUG_LEDS
-	bool
+	def_bool y if NEW_LEDS
 	depends on OMAP_DEBUG_DEVICES
-	default y if LEDS_CLASS
 
 config OMAP_SMARTREFLEX
 	bool "SmartReflex support"
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 39407cb..24e23f3 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -1,279 +1,118 @@
 /*
  * linux/arch/arm/plat-omap/debug-leds.c
  *
+ * Copyright 2011 by Bryan Wu <bryan.wu at canonical.com>
  * Copyright 2003 by Texas Instruments Incorporated
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/gpio.h>
+
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 
 #include <mach/hardware.h>
-#include <asm/leds.h>
 #include <asm/mach-types.h>
 
 #include <plat/fpga.h>
 
-
 /* Many OMAP development platforms reuse the same "debug board"; these
  * platforms include H2, H3, H4, and Perseus2.  There are 16 LEDs on the
  * debug board (all green), accessed through FPGA registers.
- *
- * The "surfer" expansion board and H2 sample board also have two-color
- * green+red LEDs (in parallel), used here for timer and idle indicators
- * in preference to the ones on the debug board, for a "Disco LED" effect.
- *
- * This driver exports either the original ARM LED API, the new generic
- * one, or both.
- */
-
-static spinlock_t			lock;
-static struct h2p2_dbg_fpga __iomem	*fpga;
-static u16				led_state, hw_led_state;
-
-
-#ifdef	CONFIG_OMAP_DEBUG_LEDS
-#define new_led_api()	1
-#else
-#define new_led_api()	0
-#endif
-
-
-/*-------------------------------------------------------------------------*/
-
-/* original ARM debug LED API:
- *  - timer and idle leds (some boards use non-FPGA leds here);
- *  - up to 4 generic leds, easily accessed in-kernel (any context)
  */
 
-#define GPIO_LED_RED		3
-#define GPIO_LED_GREEN		OMAP_MPUIO(4)
-
-#define LED_STATE_ENABLED	0x01
-#define LED_STATE_CLAIMED	0x02
-#define LED_TIMER_ON		0x04
-
-#define GPIO_IDLE		GPIO_LED_GREEN
-#define GPIO_TIMER		GPIO_LED_RED
-
-static void h2p2_dbg_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&lock, flags);
-
-	if (!(led_state & LED_STATE_ENABLED) && evt != led_start)
-		goto done;
-
-	switch (evt) {
-	case led_start:
-		if (fpga)
-			led_state |= LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-	case led_halted:
-		/* all leds off during suspend or shutdown */
-
-		if (!(machine_is_omap_perseus2() || machine_is_omap_h4())) {
-			gpio_set_value(GPIO_TIMER, 0);
-			gpio_set_value(GPIO_IDLE, 0);
-		}
-
-		__raw_writew(~0, &fpga->leds);
-		led_state &= ~LED_STATE_ENABLED;
-		goto done;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = 0;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		led_state ^= LED_TIMER_ON;
-
-		if (machine_is_omap_perseus2() || machine_is_omap_h4())
-			hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
-		else {
-			gpio_set_value(GPIO_TIMER,
-					led_state & LED_TIMER_ON);
-			goto done;
-		}
-
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	/* LED lit iff busy */
-	case led_idle_start:
-		if (machine_is_omap_perseus2() || machine_is_omap_h4())
-			hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
-		else {
-			gpio_set_value(GPIO_IDLE, 1);
-			goto done;
-		}
-
-		break;
+static struct h2p2_dbg_fpga __iomem *fpga;
 
-	case led_idle_end:
-		if (machine_is_omap_perseus2() || machine_is_omap_h4())
-			hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
-		else {
-			gpio_set_value(GPIO_IDLE, 0);
-			goto done;
-		}
-
-		break;
-#endif
-
-	case led_green_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_GREEN;
-		break;
-	case led_green_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_GREEN;
-		break;
-
-	case led_amber_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_AMBER;
-		break;
-	case led_amber_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_AMBER;
-		break;
-
-	case led_red_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_RED;
-		break;
-	case led_red_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_RED;
-		break;
-
-	case led_blue_on:
-		hw_led_state |= H2P2_DBG_FPGA_LED_BLUE;
-		break;
-	case led_blue_off:
-		hw_led_state &= ~H2P2_DBG_FPGA_LED_BLUE;
-		break;
-
-	default:
-		break;
-	}
-
-
-	/*
-	 *  Actually burn the LEDs
-	 */
-	if (led_state & LED_STATE_ENABLED)
-		__raw_writew(~hw_led_state, &fpga->leds);
-
-done:
-	spin_unlock_irqrestore(&lock, flags);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* "new" LED API
- *  - with syfs access and generic triggering
- *  - not readily accessible to in-kernel drivers
- */
+static u16 fpga_led_state;
 
 struct dbg_led {
 	struct led_classdev	cdev;
 	u16			mask;
 };
 
-static struct dbg_led dbg_leds[] = {
-	/* REVISIT at least H2 uses different timer & cpu leds... */
-#ifndef CONFIG_LEDS_TIMER
-	{ .mask = 1 << 0,  .cdev.name =  "d4:green",
-		.cdev.default_trigger = "heartbeat", },
-#endif
-#ifndef CONFIG_LEDS_CPU
-	{ .mask = 1 << 1,  .cdev.name =  "d5:green", },		/* !idle */
-#endif
-	{ .mask = 1 << 2,  .cdev.name =  "d6:green", },
-	{ .mask = 1 << 3,  .cdev.name =  "d7:green", },
-
-	{ .mask = 1 << 4,  .cdev.name =  "d8:green", },
-	{ .mask = 1 << 5,  .cdev.name =  "d9:green", },
-	{ .mask = 1 << 6,  .cdev.name = "d10:green", },
-	{ .mask = 1 << 7,  .cdev.name = "d11:green", },
-
-	{ .mask = 1 << 8,  .cdev.name = "d12:green", },
-	{ .mask = 1 << 9,  .cdev.name = "d13:green", },
-	{ .mask = 1 << 10, .cdev.name = "d14:green", },
-	{ .mask = 1 << 11, .cdev.name = "d15:green", },
-
-#ifndef	CONFIG_LEDS
-	{ .mask = 1 << 12, .cdev.name = "d16:green", },
-	{ .mask = 1 << 13, .cdev.name = "d17:green", },
-	{ .mask = 1 << 14, .cdev.name = "d18:green", },
-	{ .mask = 1 << 15, .cdev.name = "d19:green", },
-#endif
+static const struct {
+	const char *name;
+	const char *trigger;
+} dbg_leds[] = {
+	{ "dbg:d4", "heartbeat", },
+	{ "dbg:d5", "cpu0", },
+	{ "dbg:d6", "default-on", },
+	{ "dbg:d7", },
+	{ "dbg:d8", },
+	{ "dbg:d9", },
+	{ "dbg:d10", },
+	{ "dbg:d11", },
+	{ "dbg:d12", },
+	{ "dbg:d13", },
+	{ "dbg:d14", },
+	{ "dbg:d15", },
+	{ "dbg:d16", },
+	{ "dbg:d17", },
+	{ "dbg:d18", },
+	{ "dbg:d19", },
 };
 
-static void
-fpga_led_set(struct led_classdev *cdev, enum led_brightness value)
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static void dbg_led_set(struct led_classdev *cdev,
+			      enum led_brightness b)
 {
-	struct dbg_led	*led = container_of(cdev, struct dbg_led, cdev);
-	unsigned long	flags;
+	struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
+	u16 reg;
 
-	spin_lock_irqsave(&lock, flags);
-	if (value == LED_OFF)
-		hw_led_state &= ~led->mask;
+	reg = __raw_readw(&fpga->leds);
+	if (b != LED_OFF)
+		reg |= led->mask;
 	else
-		hw_led_state |= led->mask;
-	__raw_writew(~hw_led_state, &fpga->leds);
-	spin_unlock_irqrestore(&lock, flags);
+		reg &= ~led->mask;
+	__raw_writew(reg, &fpga->leds);
 }
 
-static void __init newled_init(struct device *dev)
+static enum led_brightness dbg_led_get(struct led_classdev *cdev)
 {
-	unsigned	i;
-	struct dbg_led	*led;
-	int		status;
+	struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
+	u16 reg;
 
-	for (i = 0, led = dbg_leds; i < ARRAY_SIZE(dbg_leds); i++, led++) {
-		led->cdev.brightness_set = fpga_led_set;
-		status = led_classdev_register(dev, &led->cdev);
-		if (status < 0)
-			break;
-	}
-	return;
+	reg = __raw_readw(&fpga->leds);
+	return (reg & led->mask) ? LED_FULL : LED_OFF;
 }
 
-
-/*-------------------------------------------------------------------------*/
-
-static int /* __init */ fpga_probe(struct platform_device *pdev)
+static int fpga_probe(struct platform_device *pdev)
 {
 	struct resource	*iomem;
-
-	spin_lock_init(&lock);
+	int i;
 
 	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!iomem)
 		return -ENODEV;
 
 	fpga = ioremap(iomem->start, H2P2_DBG_FPGA_SIZE);
-	__raw_writew(~0, &fpga->leds);
+	__raw_writew(0xff, &fpga->leds);
+
+	for (i = 0; i < ARRAY_SIZE(dbg_leds); i++) {
+		struct dbg_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
 
-#ifdef	CONFIG_LEDS
-	leds_event = h2p2_dbg_leds_event;
-	leds_event(led_start);
-#endif
+		led->cdev.name = dbg_leds[i].name;
+		led->cdev.brightness_set = dbg_led_set;
+		led->cdev.brightness_get = dbg_led_get;
+		led->cdev.default_trigger = dbg_leds[i].trigger;
+		led->mask = BIT(i);
 
-	if (new_led_api()) {
-		newled_init(&pdev->dev);
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
 	}
 
 	return 0;
@@ -281,13 +120,15 @@ static int /* __init */ fpga_probe(struct platform_device *pdev)
 
 static int fpga_suspend_noirq(struct device *dev)
 {
-	__raw_writew(~0, &fpga->leds);
+	fpga_led_state = __raw_readw(&fpga->leds);
+	__raw_writew(0xff, &fpga->leds);
+
 	return 0;
 }
 
 static int fpga_resume_noirq(struct device *dev)
 {
-	__raw_writew(~hw_led_state, &fpga->leds);
+	__raw_writew(~fpga_led_state, &fpga->leds);
 	return 0;
 }
 
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:32 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:32 +0800
Subject: [PATCH 17/18] ARM: mach-sa1100: retire custom LED code
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-18-git-send-email-bryan.wu@canonical.com>

Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/mach-sa1100/Makefile       |    9 ---
 arch/arm/mach-sa1100/assabet.c      |   83 +++++++++++++++++++++++++
 arch/arm/mach-sa1100/badge4.c       |   30 +++++++++
 arch/arm/mach-sa1100/cerf.c         |   42 +++++++++++++
 arch/arm/mach-sa1100/hackkit.c      |   32 ++++++++++
 arch/arm/mach-sa1100/lart.c         |   26 ++++++++
 arch/arm/mach-sa1100/leds-assabet.c |  113 -----------------------------------
 arch/arm/mach-sa1100/leds-badge4.c  |  110 ----------------------------------
 arch/arm/mach-sa1100/leds-cerf.c    |  109 ---------------------------------
 arch/arm/mach-sa1100/leds-hackkit.c |  111 ----------------------------------
 arch/arm/mach-sa1100/leds-lart.c    |  100 -------------------------------
 arch/arm/mach-sa1100/leds.c         |   50 ---------------
 arch/arm/mach-sa1100/leds.h         |   13 ----
 13 files changed, 213 insertions(+), 615 deletions(-)
 delete mode 100644 arch/arm/mach-sa1100/leds-assabet.c
 delete mode 100644 arch/arm/mach-sa1100/leds-badge4.c
 delete mode 100644 arch/arm/mach-sa1100/leds-cerf.c
 delete mode 100644 arch/arm/mach-sa1100/leds-hackkit.c
 delete mode 100644 arch/arm/mach-sa1100/leds-lart.c
 delete mode 100644 arch/arm/mach-sa1100/leds.c
 delete mode 100644 arch/arm/mach-sa1100/leds.h

diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index 60b97ec..1aed9e7 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -7,21 +7,17 @@ obj-y := clock.o generic.o irq.o time.o #nmi-oopser.o
 obj-m :=
 obj-n :=
 obj-  :=
-led-y := leds.o
 
 obj-$(CONFIG_CPU_FREQ_SA1100)		+= cpu-sa1100.o
 obj-$(CONFIG_CPU_FREQ_SA1110)		+= cpu-sa1110.o
 
 # Specific board support
 obj-$(CONFIG_SA1100_ASSABET)		+= assabet.o
-led-$(CONFIG_SA1100_ASSABET)		+= leds-assabet.o
 obj-$(CONFIG_ASSABET_NEPONSET)		+= neponset.o
 
 obj-$(CONFIG_SA1100_BADGE4)		+= badge4.o
-led-$(CONFIG_SA1100_BADGE4)		+= leds-badge4.o
 
 obj-$(CONFIG_SA1100_CERF)		+= cerf.o
-led-$(CONFIG_SA1100_CERF)		+= leds-cerf.o
 
 obj-$(CONFIG_SA1100_COLLIE)		+= collie.o
 
@@ -29,13 +25,11 @@ obj-$(CONFIG_SA1100_H3100)		+= h3100.o h3xxx.o
 obj-$(CONFIG_SA1100_H3600)		+= h3600.o h3xxx.o
 
 obj-$(CONFIG_SA1100_HACKKIT)		+= hackkit.o
-led-$(CONFIG_SA1100_HACKKIT)		+= leds-hackkit.o
 
 obj-$(CONFIG_SA1100_JORNADA720)		+= jornada720.o
 obj-$(CONFIG_SA1100_JORNADA720_SSP)	+= jornada720_ssp.o
 
 obj-$(CONFIG_SA1100_LART)		+= lart.o
-led-$(CONFIG_SA1100_LART)		+= leds-lart.o
 
 obj-$(CONFIG_SA1100_NANOENGINE)		+= nanoengine.o
 obj-$(CONFIG_PCI_NANOENGINE)		+= pci-nanoengine.o
@@ -46,9 +40,6 @@ obj-$(CONFIG_SA1100_SHANNON)		+= shannon.o
 
 obj-$(CONFIG_SA1100_SIMPAD)		+= simpad.o
 
-# LEDs support
-obj-$(CONFIG_LEDS) += $(led-y)
-
 # Miscellaneous functions
 obj-$(CONFIG_PM)			+= pm.o sleep.o
 obj-$(CONFIG_SA1100_SSP)		+= ssp.o
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 375d3f7..0e29ec2 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -20,6 +20,8 @@
 #include <linux/mtd/partitions.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
+#include <linux/leds.h>
+#include <linux/slab.h>
 
 #include <video/sa1100fb.h>
 
@@ -529,6 +531,87 @@ static void __init assabet_map_io(void)
 	sa1100_register_uart(2, 3);
 }
 
+/* LEDs */
+struct assabet_led {
+	struct led_classdev cdev;
+	u32 mask;
+};
+
+/*
+ * The triggers lines up below will only be used if the
+ * LED triggers are compiled in.
+ */
+static const struct {
+	const char *name;
+	const char *trigger;
+} assabet_leds[] = {
+	{ "assabet:red", "cpu0",},
+	{ "assabet:green", "heartbeat", },
+};
+
+/*
+ * The LED control in Assabet is reversed:
+ *  - setting bit means turn off LED
+ *  - clearing bit means turn on LED
+ */
+static void assabet_led_set(struct led_classdev *cdev,
+		enum led_brightness b)
+{
+	struct assabet_led *led = container_of(cdev,
+			struct assabet_led, cdev);
+
+	if (b != LED_OFF)
+		ASSABET_BCR_clear(led->mask);
+	else
+		ASSABET_BCR_set(led->mask);
+}
+
+static enum led_brightness assabet_led_get(struct led_classdev *cdev)
+{
+	struct assabet_led *led = container_of(cdev,
+			struct assabet_led, cdev);
+
+	return (ASSABET_BCR & led->mask) ? LED_OFF : LED_FULL;
+}
+
+static int __init assabet_leds_init(void)
+{
+	int i;
+
+	if (!machine_is_assabet())
+		return -ENODEV;
+
+	for (i = 0; i < ARRAY_SIZE(assabet_leds); i++) {
+		struct assabet_led *led;
+
+		led = kzalloc(sizeof(*led), GFP_KERNEL);
+		if (!led)
+			break;
+
+		led->cdev.name = assabet_leds[i].name;
+		led->cdev.brightness_set = assabet_led_set;
+		led->cdev.brightness_get = assabet_led_get;
+		led->cdev.default_trigger = assabet_leds[i].trigger;
+
+		if (!i)
+			led->mask = ASSABET_BCR_LED_RED;
+		else
+			led->mask = ASSABET_BCR_LED_GREEN;
+
+		if (led_classdev_register(NULL, &led->cdev) < 0) {
+			kfree(led);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Since we may have triggers on any subsystem, defer registration
+ * until after subsystem_init.
+ */
+fs_initcall(assabet_leds_init);
 
 MACHINE_START(ASSABET, "Intel-Assabet")
 	.atag_offset	= 0x100,
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index e0f0c03..58b2d95 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -22,6 +22,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/errno.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -76,8 +78,36 @@ static struct platform_device sa1111_device = {
 	.resource	= sa1111_resources,
 };
 
+/* LEDs */
+struct gpio_led badge4_gpio_leds[] = {
+	{
+		.name			= "badge4:red",
+		.default_trigger	= "heartbeat",
+		.gpio			= 7,
+	},
+	{
+		.name			= "badge4:green",
+		.default_trigger	= "cpu0",
+		.gpio			= 9,
+	},
+};
+
+static struct gpio_led_platform_data badge4_gpio_led_info = {
+	.leds		= badge4_gpio_leds,
+	.num_leds	= ARRAY_SIZE(badge4_gpio_leds),
+};
+
+static struct platform_device badge4_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &badge4_gpio_led_info,
+	}
+};
+
 static struct platform_device *devices[] __initdata = {
 	&sa1111_device,
+	&badge4_leds,
 };
 
 static int __init badge4_sa1111_init(void)
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 4a61f60..c4edf2e 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -17,6 +17,8 @@
 #include <linux/irq.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
 
 #include <mach/hardware.h>
 #include <asm/setup.h>
@@ -43,8 +45,48 @@ static struct platform_device cerfuart2_device = {
 	.resource	= cerfuart2_resources,
 };
 
+/* LEDs */
+struct gpio_led cerf_gpio_leds[] = {
+	{
+		.name			= "cerf:d0",
+		.default_trigger	= "heartbeat",
+		.gpio			= 0,
+	},
+	{
+		.name			= "cerf:d1",
+		.default_trigger	= "cpu0",
+		.gpio			= 1,
+	},
+	{
+		.name			= "cerf:d2",
+		.default_trigger	= "default-on",
+		.gpio			= 2,
+	},
+	{
+		.name			= "cerf:d3",
+		.default_trigger	= "default-on",
+		.gpio			= 3,
+	},
+
+};
+
+static struct gpio_led_platform_data cerf_gpio_led_info = {
+	.leds		= cerf_gpio_leds,
+	.num_leds	= ARRAY_SIZE(cerf_gpio_leds),
+};
+
+static struct platform_device cerf_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &cerf_gpio_led_info,
+	}
+};
+
+
 static struct platform_device *cerf_devices[] __initdata = {
 	&cerfuart2_device,
+	&cerf_leds,
 };
 
 #ifdef CONFIG_SA1100_CERF_FLASH_32MB
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index 5535475..85e82ab 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -21,6 +21,10 @@
 #include <linux/serial_core.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/tty.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach-types.h>
 #include <asm/setup.h>
@@ -183,9 +187,37 @@ static struct flash_platform_data hackkit_flash_data = {
 static struct resource hackkit_flash_resource =
 	DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M);
 
+/* LEDs */
+struct gpio_led hackkit_gpio_leds[] = {
+	{
+		.name			= "hackkit:red",
+		.default_trigger	= "cpu0",
+		.gpio			= 22,
+	},
+	{
+		.name			= "hackkit:green",
+		.default_trigger	= "heartbeat",
+		.gpio			= 23,
+	},
+};
+
+static struct gpio_led_platform_data hackkit_gpio_led_info = {
+	.leds		= hackkit_gpio_leds,
+	.num_leds	= ARRAY_SIZE(hackkit_gpio_leds),
+};
+
+static struct platform_device hackkit_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &hackkit_gpio_led_info,
+	}
+};
+
 static void __init hackkit_init(void)
 {
 	sa11x0_register_mtd(&hackkit_flash_data, &hackkit_flash_resource, 1);
+	platform_device_register(&hackkit_leds);
 }
 
 /**********************************************************************
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index eb6534e..9a4b4ab 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -5,6 +5,9 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/tty.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
 
 #include <video/sa1100fb.h>
 
@@ -126,6 +129,27 @@ static struct map_desc lart_io_desc[] __initdata = {
 	}
 };
 
+/* LEDs */
+struct gpio_led lart_gpio_leds[] = {
+	{
+		.name			= "lart:red",
+		.default_trigger	= "cpu0",
+		.gpio			= 23,
+	},
+};
+
+static struct gpio_led_platform_data lart_gpio_led_info = {
+	.leds		= lart_gpio_leds,
+	.num_leds	= ARRAY_SIZE(lart_gpio_leds),
+};
+
+static struct platform_device lart_leds = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &lart_gpio_led_info,
+	}
+};
 static void __init lart_map_io(void)
 {
 	sa1100_map_io();
@@ -139,6 +163,8 @@ static void __init lart_map_io(void)
 	GPDR |= GPIO_UART_TXD;
 	GPDR &= ~GPIO_UART_RXD;
 	PPAR |= PPAR_UPR;
+
+	platform_device_register(&lart_leds);
 }
 
 MACHINE_START(LART, "LART")
diff --git a/arch/arm/mach-sa1100/leds-assabet.c b/arch/arm/mach-sa1100/leds-assabet.c
deleted file mode 100644
index 3699176..0000000
--- a/arch/arm/mach-sa1100/leds-assabet.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-assabet.c
- *
- * Copyright (C) 2000 John Dorsey <john+ at cs.cmu.edu>
- *
- * Original (leds-footbridge.c) by Russell King
- *
- * Assabet uses the LEDs as follows:
- *   - Green - toggles state every 50 timer interrupts
- *   - Red   - on if system is not idle
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <mach/assabet.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define ASSABET_BCR_LED_MASK	(ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED)
-
-void assabet_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch (evt) {
-	case led_start:
-		hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-		ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state);
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= ASSABET_BCR_LED_GREEN;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= ASSABET_BCR_LED_RED;
-		break;
-
-	case led_idle_end:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~ASSABET_BCR_LED_RED;
-		break;
-#endif
-
-	case led_halted:
-		break;
-
-	case led_green_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~ASSABET_BCR_LED_GREEN;
-		break;
-
-	case led_green_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= ASSABET_BCR_LED_GREEN;
-		break;
-
-	case led_amber_on:
-		break;
-
-	case led_amber_off:
-		break;
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~ASSABET_BCR_LED_RED;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= ASSABET_BCR_LED_RED;
-		break;
-
-	default:
-		break;
-	}
-
-	if  (led_state & LED_STATE_ENABLED)
-		ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state);
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-badge4.c b/arch/arm/mach-sa1100/leds-badge4.c
deleted file mode 100644
index f99fac3..0000000
--- a/arch/arm/mach-sa1100/leds-badge4.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-badge4.c
- *
- * Author: Christopher Hoover <ch at hpl.hp.com>
- * Copyright (C) 2002 Hewlett-Packard Company
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_RED		GPIO_GPIO(7)
-#define LED_GREEN       GPIO_GPIO(9)
-#define LED_MASK	(LED_RED|LED_GREEN)
-
-#define LED_IDLE	LED_GREEN
-#define LED_TIMER	LED_RED
-
-void badge4_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-	local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-		GPDR |= LED_MASK;
-                hw_led_state = LED_MASK;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= LED_TIMER;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-		/* LED off when system is idle */
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_IDLE;
-                break;
-
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_IDLE;
-                break;
-#endif
-
-        case led_red_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_RED;
-                break;
-
-        case led_red_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_RED;
-                break;
-
-        case led_green_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_GREEN;
-                break;
-
-        case led_green_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_GREEN;
-                break;
-
-	default:
-		break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-cerf.c b/arch/arm/mach-sa1100/leds-cerf.c
deleted file mode 100644
index 040540f..0000000
--- a/arch/arm/mach-sa1100/leds-cerf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-cerf.c
- *
- * Author: ???
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_D0          GPIO_GPIO(0)
-#define LED_D1          GPIO_GPIO(1)
-#define LED_D2          GPIO_GPIO(2)
-#define LED_D3          GPIO_GPIO(3)
-#define LED_MASK        (LED_D0|LED_D1|LED_D2|LED_D3)
-
-void cerf_leds_event(led_event_t evt)
-{
-        unsigned long flags;
-
-	local_irq_save(flags);
-
-        switch (evt) {
-        case led_start:
-                hw_led_state = LED_MASK;
-                led_state = LED_STATE_ENABLED;
-                break;
-
-        case led_stop:
-                led_state &= ~LED_STATE_ENABLED;
-                break;
-
-        case led_claim:
-                led_state |= LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-        case led_release:
-                led_state &= ~LED_STATE_CLAIMED;
-                hw_led_state = LED_MASK;
-                break;
-
-#ifdef CONFIG_LEDS_TIMER
-        case led_timer:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state ^= LED_D0;
-                break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-        case led_idle_start:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D1;
-                break;
-
-        case led_idle_end:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D1;
-                break;
-#endif
-        case led_green_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D2;
-                break;
-
-        case led_green_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D2;
-                break;
-
-        case led_amber_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D3;
-                break;
-
-        case led_amber_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D3;
-                break;
-
-        case led_red_on:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state &= ~LED_D1;
-                break;
-
-        case led_red_off:
-                if (!(led_state & LED_STATE_CLAIMED))
-                        hw_led_state |= LED_D1;
-                break;
-
-        default:
-                break;
-        }
-
-        if  (led_state & LED_STATE_ENABLED) {
-                GPSR = hw_led_state;
-                GPCR = hw_led_state ^ LED_MASK;
-        }
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-hackkit.c b/arch/arm/mach-sa1100/leds-hackkit.c
deleted file mode 100644
index 6a23524..0000000
--- a/arch/arm/mach-sa1100/leds-hackkit.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-hackkit.c
- *
- * based on leds-lart.c
- *
- * (C) Erik Mouw (J.A.K.Mouw at its.tudelft.nl), April 21, 2000
- * (C) Stefan Eletzhofer <stefan.eletzhofer at eletztrick.de>, 2002
- *
- * The HackKit has two leds (GPIO 22/23). The red led (gpio 22) is used
- * as cpu led, the green one is used as timer led.
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_GREEN    GPIO_GPIO23
-#define LED_RED    GPIO_GPIO22
-#define LED_MASK  (LED_RED | LED_GREEN)
-
-void hackkit_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch(evt) {
-		case led_start:
-			/* pin 22/23 are outputs */
-			GPDR |= LED_MASK;
-			hw_led_state = LED_MASK;
-			led_state = LED_STATE_ENABLED;
-			break;
-
-		case led_stop:
-			led_state &= ~LED_STATE_ENABLED;
-			break;
-
-		case led_claim:
-			led_state |= LED_STATE_CLAIMED;
-			hw_led_state = LED_MASK;
-			break;
-
-		case led_release:
-			led_state &= ~LED_STATE_CLAIMED;
-			hw_led_state = LED_MASK;
-			break;
-
-#ifdef CONFIG_LEDS_TIMER
-		case led_timer:
-			if (!(led_state & LED_STATE_CLAIMED))
-				hw_led_state ^= LED_GREEN;
-			break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-		case led_idle_start:
-			/* The LART people like the LED to be off when the
-			   system is idle... */
-			if (!(led_state & LED_STATE_CLAIMED))
-				hw_led_state &= ~LED_RED;
-			break;
-
-		case led_idle_end:
-			/* ... and on if the system is not idle */
-			if (!(led_state & LED_STATE_CLAIMED))
-				hw_led_state |= LED_RED;
-			break;
-#endif
-
-		case led_red_on:
-			if (led_state & LED_STATE_CLAIMED)
-				hw_led_state &= ~LED_RED;
-			break;
-
-		case led_red_off:
-			if (led_state & LED_STATE_CLAIMED)
-				hw_led_state |= LED_RED;
-			break;
-
-		case led_green_on:
-			if (led_state & LED_STATE_CLAIMED)
-				hw_led_state &= ~LED_GREEN;
-			break;
-
-		case led_green_off:
-			if (led_state & LED_STATE_CLAIMED)
-				hw_led_state |= LED_GREEN;
-			break;
-
-		default:
-			break;
-	}
-
-	/* Now set the GPIO state, or nothing will happen at all */
-	if (led_state & LED_STATE_ENABLED) {
-		GPSR = hw_led_state;
-		GPCR = hw_led_state ^ LED_MASK;
-	}
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds-lart.c b/arch/arm/mach-sa1100/leds-lart.c
deleted file mode 100644
index a51830c..0000000
--- a/arch/arm/mach-sa1100/leds-lart.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds-lart.c
- *
- * (C) Erik Mouw (J.A.K.Mouw at its.tudelft.nl), April 21, 2000
- *
- * LART uses the LED as follows:
- *   - GPIO23 is the LED, on if system is not idle
- *  You can use both CONFIG_LEDS_CPU and CONFIG_LEDS_TIMER at the same
- *  time, but in that case the timer events will still dictate the
- *  pace of the LED.
- */
-#include <linux/init.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-
-#include "leds.h"
-
-
-#define LED_STATE_ENABLED	1
-#define LED_STATE_CLAIMED	2
-
-static unsigned int led_state;
-static unsigned int hw_led_state;
-
-#define LED_23    GPIO_GPIO23
-#define LED_MASK  (LED_23)
-
-void lart_leds_event(led_event_t evt)
-{
-	unsigned long flags;
-
-	local_irq_save(flags);
-
-	switch(evt) {
-	case led_start:
-		/* pin 23 is output pin */
-		GPDR |= LED_23;
-		hw_led_state = LED_MASK;
-		led_state = LED_STATE_ENABLED;
-		break;
-
-	case led_stop:
-		led_state &= ~LED_STATE_ENABLED;
-		break;
-
-	case led_claim:
-		led_state |= LED_STATE_CLAIMED;
-		hw_led_state = LED_MASK;
-		break;
-
-	case led_release:
-		led_state &= ~LED_STATE_CLAIMED;
-		hw_led_state = LED_MASK;
-		break;
-
-#ifdef CONFIG_LEDS_TIMER
-	case led_timer:
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state ^= LED_23;
-		break;
-#endif
-
-#ifdef CONFIG_LEDS_CPU
-	case led_idle_start:
-		/* The LART people like the LED to be off when the
-                   system is idle... */
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state &= ~LED_23;
-		break;
-
-	case led_idle_end:
-		/* ... and on if the system is not idle */
-		if (!(led_state & LED_STATE_CLAIMED))
-			hw_led_state |= LED_23;
-		break;
-#endif
-
-	case led_red_on:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state &= ~LED_23;
-		break;
-
-	case led_red_off:
-		if (led_state & LED_STATE_CLAIMED)
-			hw_led_state |= LED_23;
-		break;
-
-	default:
-		break;
-	}
-
-	/* Now set the GPIO state, or nothing will happen at all */
-	if (led_state & LED_STATE_ENABLED) {
-		GPSR = hw_led_state;
-		GPCR = hw_led_state ^ LED_MASK;
-	}
-
-	local_irq_restore(flags);
-}
diff --git a/arch/arm/mach-sa1100/leds.c b/arch/arm/mach-sa1100/leds.c
deleted file mode 100644
index 5fe71a0..0000000
--- a/arch/arm/mach-sa1100/leds.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * linux/arch/arm/mach-sa1100/leds.c
- *
- * SA1100 LEDs dispatcher
- *
- * Copyright (C) 2001 Nicolas Pitre
- */
-#include <linux/compiler.h>
-#include <linux/init.h>
-
-#include <asm/leds.h>
-#include <asm/mach-types.h>
-
-#include "leds.h"
-
-static int __init
-sa1100_leds_init(void)
-{
-	if (machine_is_assabet())
-		leds_event = assabet_leds_event;
-	if (machine_is_consus())
-		leds_event = consus_leds_event;
-	if (machine_is_badge4())
-		leds_event = badge4_leds_event;
-	if (machine_is_brutus())
-		leds_event = brutus_leds_event;
-	if (machine_is_cerf())
-		leds_event = cerf_leds_event;
-	if (machine_is_flexanet())
-		leds_event = flexanet_leds_event;
-	if (machine_is_graphicsclient())
-		leds_event = graphicsclient_leds_event;
-	if (machine_is_hackkit())
-		leds_event = hackkit_leds_event;
-	if (machine_is_lart())
-		leds_event = lart_leds_event;
-	if (machine_is_pfs168())
-		leds_event = pfs168_leds_event;
-	if (machine_is_graphicsmaster())
-		leds_event = graphicsmaster_leds_event;
-	if (machine_is_adsbitsy())
-		leds_event = adsbitsy_leds_event;
-	if (machine_is_pt_system3())
-		leds_event = system3_leds_event;
-
-	leds_event(led_start);
-	return 0;
-}
-
-core_initcall(sa1100_leds_init);
diff --git a/arch/arm/mach-sa1100/leds.h b/arch/arm/mach-sa1100/leds.h
deleted file mode 100644
index 776b602..0000000
--- a/arch/arm/mach-sa1100/leds.h
+++ /dev/null
@@ -1,13 +0,0 @@
-extern void assabet_leds_event(led_event_t evt);
-extern void badge4_leds_event(led_event_t evt);
-extern void consus_leds_event(led_event_t evt);
-extern void brutus_leds_event(led_event_t evt);
-extern void cerf_leds_event(led_event_t evt);
-extern void flexanet_leds_event(led_event_t evt);
-extern void graphicsclient_leds_event(led_event_t evt);
-extern void hackkit_leds_event(led_event_t evt);
-extern void lart_leds_event(led_event_t evt);
-extern void pfs168_leds_event(led_event_t evt);
-extern void graphicsmaster_leds_event(led_event_t evt);
-extern void adsbitsy_leds_event(led_event_t evt);
-extern void system3_leds_event(led_event_t evt);
-- 
1.7.9.1



From bryan.wu at canonical.com  Fri Mar 30 07:58:33 2012
From: bryan.wu at canonical.com (Bryan Wu)
Date: Fri, 30 Mar 2012 19:58:33 +0800
Subject: [PATCH 18/18] ARM: use new LEDS CPU trigger stub to replace old one
In-Reply-To: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
References: <1333108713-12707-1-git-send-email-bryan.wu@canonical.com>
Message-ID: <1333108713-12707-19-git-send-email-bryan.wu@canonical.com>

Cc:  Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Bryan Wu <bryan.wu at canonical.com>
---
 arch/arm/Kconfig            |   53 -------------------
 arch/arm/include/asm/leds.h |   50 ------------------
 arch/arm/kernel/Makefile    |    1 -
 arch/arm/kernel/leds.c      |  121 -------------------------------------------
 arch/arm/kernel/process.c   |    6 +-
 arch/arm/kernel/time.c      |   17 ------
 6 files changed, 3 insertions(+), 245 deletions(-)
 delete mode 100644 arch/arm/include/asm/leds.h
 delete mode 100644 arch/arm/kernel/leds.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bd84f2d..3e247a6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1760,59 +1760,6 @@ config FORCE_MAX_ZONEORDER
 	  This config option is actually maximum order plus one. For example,
 	  a value of 11 means that the largest free memory block is 2^10 pages.
 
-config LEDS
-	bool "Timer and CPU usage LEDs"
-	depends on ARCH_CDB89712 || ARCH_EBSA110 || \
-		   ARCH_EBSA285 || ARCH_INTEGRATOR || \
-		   ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
-		   ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
-		   ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
-		   ARCH_AT91 || ARCH_DAVINCI || \
-		   ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
-	help
-	  If you say Y here, the LEDs on your machine will be used
-	  to provide useful information about your current system status.
-
-	  If you are compiling a kernel for a NetWinder or EBSA-285, you will
-	  be able to select which LEDs are active using the options below. If
-	  you are compiling a kernel for the EBSA-110 or the LART however, the
-	  red LED will simply flash regularly to indicate that the system is
-	  still functional. It is safe to say Y here if you have a CATS
-	  system, but the driver will do nothing.
-
-config LEDS_TIMER
-	bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
-			    OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
-			    || MACH_OMAP_PERSEUS2
-	depends on LEDS
-	depends on !GENERIC_CLOCKEVENTS
-	default y if ARCH_EBSA110
-	help
-	  If you say Y here, one of the system LEDs (the green one on the
-	  NetWinder, the amber one on the EBSA285, or the red one on the LART)
-	  will flash regularly to indicate that the system is still
-	  operational. This is mainly useful to kernel hackers who are
-	  debugging unstable kernels.
-
-	  The LART uses the same LED for both Timer LED and CPU usage LED
-	  functions. You may choose to use both, but the Timer LED function
-	  will overrule the CPU usage LED.
-
-config LEDS_CPU
-	bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
-			!ARCH_OMAP) \
-			|| OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
-			|| MACH_OMAP_PERSEUS2
-	depends on LEDS
-	help
-	  If you say Y here, the red LED will be used to give a good real
-	  time indication of CPU usage, by lighting whenever the idle task
-	  is not currently executing.
-
-	  The LART uses the same LED for both Timer LED and CPU usage LED
-	  functions. You may choose to use both, but the Timer LED function
-	  will overrule the CPU usage LED.
-
 config ALIGNMENT_TRAP
 	bool
 	depends on CPU_CP15_MMU
diff --git a/arch/arm/include/asm/leds.h b/arch/arm/include/asm/leds.h
deleted file mode 100644
index c545739..0000000
--- a/arch/arm/include/asm/leds.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- *  arch/arm/include/asm/leds.h
- *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Event-driven interface for LEDs on machines
- *  Added led_start and led_stop- Alex Holden, 28th Dec 1998.
- */
-#ifndef ASM_ARM_LEDS_H
-#define ASM_ARM_LEDS_H
-
-
-typedef enum {
-	led_idle_start,
-	led_idle_end,
-	led_timer,
-	led_start,
-	led_stop,
-	led_claim,		/* override idle & timer leds */
-	led_release,		/* restore idle & timer leds */
-	led_start_timer_mode,
-	led_stop_timer_mode,
-	led_green_on,
-	led_green_off,
-	led_amber_on,
-	led_amber_off,
-	led_red_on,
-	led_red_off,
-	led_blue_on,
-	led_blue_off,
-	/*
-	 * I want this between led_timer and led_start, but
-	 * someone has decided to export this to user space
-	 */
-	led_halted
-} led_event_t;
-
-/* Use this routine to handle LEDs */
-
-#ifdef CONFIG_LEDS
-extern void (*leds_event)(led_event_t);
-#else
-#define leds_event(e)
-#endif
-
-#endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7b787d6..fec979c 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -21,7 +21,6 @@ obj-y		:= elf.o entry-armv.o entry-common.o irq.o opcodes.o \
 
 obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
 
-obj-$(CONFIG_LEDS)		+= leds.o
 obj-$(CONFIG_OC_ETM)		+= etm.o
 obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 obj-$(CONFIG_ISA_DMA_API)	+= dma.o
diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c
deleted file mode 100644
index 1911dae..0000000
--- a/arch/arm/kernel/leds.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * LED support code, ripped out of arch/arm/kernel/time.c
- *
- *  Copyright (C) 1994-2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/syscore_ops.h>
-#include <linux/string.h>
-
-#include <asm/leds.h>
-
-static void dummy_leds_event(led_event_t evt)
-{
-}
-
-void (*leds_event)(led_event_t) = dummy_leds_event;
-
-struct leds_evt_name {
-	const char	name[8];
-	int		on;
-	int		off;
-};
-
-static const struct leds_evt_name evt_names[] = {
-	{ "amber", led_amber_on, led_amber_off },
-	{ "blue",  led_blue_on,  led_blue_off  },
-	{ "green", led_green_on, led_green_off },
-	{ "red",   led_red_on,   led_red_off   },
-};
-
-static ssize_t leds_store(struct device *dev,
-			struct device_attribute *attr,
-			const char *buf, size_t size)
-{
-	int ret = -EINVAL, len = strcspn(buf, " ");
-
-	if (len > 0 && buf[len] == '\0')
-		len--;
-
-	if (strncmp(buf, "claim", len) == 0) {
-		leds_event(led_claim);
-		ret = size;
-	} else if (strncmp(buf, "release", len) == 0) {
-		leds_event(led_release);
-		ret = size;
-	} else {
-		int i;
-
-		for (i = 0; i < ARRAY_SIZE(evt_names); i++) {
-			if (strlen(evt_names[i].name) != len ||
-			    strncmp(buf, evt_names[i].name, len) != 0)
-				continue;
-			if (strncmp(buf+len, " on", 3) == 0) {
-				leds_event(evt_names[i].on);
-				ret = size;
-			} else if (strncmp(buf+len, " off", 4) == 0) {
-				leds_event(evt_names[i].off);
-				ret = size;
-			}
-			break;
-		}
-	}
-	return ret;
-}
-
-static DEVICE_ATTR(event, 0200, NULL, leds_store);
-
-static struct bus_type leds_subsys = {
-	.name		= "leds",
-	.dev_name	= "leds",
-};
-
-static struct device leds_device = {
-	.id		= 0,
-	.bus		= &leds_subsys,
-};
-
-static int leds_suspend(void)
-{
-	leds_event(led_stop);
-	return 0;
-}
-
-static void leds_resume(void)
-{
-	leds_event(led_start);
-}
-
-static void leds_shutdown(void)
-{
-	leds_event(led_halted);
-}
-
-static struct syscore_ops leds_syscore_ops = {
-	.shutdown	= leds_shutdown,
-	.suspend	= leds_suspend,
-	.resume		= leds_resume,
-};
-
-static int __init leds_init(void)
-{
-	int ret;
-	ret = subsys_system_register(&leds_subsys, NULL);
-	if (ret == 0)
-		ret = device_register(&leds_device);
-	if (ret == 0)
-		ret = device_create_file(&leds_device, &dev_attr_event);
-	if (ret == 0)
-		register_syscore_ops(&leds_syscore_ops);
-	return ret;
-}
-
-device_initcall(leds_init);
-
-EXPORT_SYMBOL(leds_event);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 2b7b017..89546da 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -31,9 +31,9 @@
 #include <linux/random.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/cpuidle.h>
+#include <linux/leds.h>
 
 #include <asm/cacheflush.h>
-#include <asm/leds.h>
 #include <asm/processor.h>
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
@@ -209,7 +209,7 @@ void cpu_idle(void)
 	while (1) {
 		tick_nohz_idle_enter();
 		rcu_idle_enter();
-		leds_event(led_idle_start);
+		ledtrig_cpu(CPU_LED_IDLE_START);
 		while (!need_resched()) {
 #ifdef CONFIG_HOTPLUG_CPU
 			if (cpu_is_offline(smp_processor_id()))
@@ -240,7 +240,7 @@ void cpu_idle(void)
 			} else
 				local_irq_enable();
 		}
-		leds_event(led_idle_end);
+		ledtrig_cpu(CPU_LED_IDLE_END);
 		rcu_idle_exit();
 		tick_nohz_idle_exit();
 		schedule_preempt_disabled();
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index fe31b22..9f92eba 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -25,7 +25,6 @@
 #include <linux/timer.h>
 #include <linux/irq.h>
 
-#include <asm/leds.h>
 #include <asm/thread_info.h>
 #include <asm/sched_clock.h>
 #include <asm/stacktrace.h>
@@ -80,21 +79,6 @@ u32 arch_gettimeoffset(void)
 }
 #endif /* CONFIG_ARCH_USES_GETTIMEOFFSET */
 
-#ifdef CONFIG_LEDS_TIMER
-static inline void do_leds(void)
-{
-	static unsigned int count = HZ/2;
-
-	if (--count == 0) {
-		count = HZ/2;
-		leds_event(led_timer);
-	}
-}
-#else
-#define	do_leds()
-#endif
-
-
 #ifndef CONFIG_GENERIC_CLOCKEVENTS
 /*
  * Kernel system timer support.
@@ -102,7 +86,6 @@ static inline void do_leds(void)
 void timer_tick(void)
 {
 	profile_tick(CPU_PROFILING);
-	do_leds();
 	xtime_update(1);
 #ifndef CONFIG_SMP
 	update_process_times(user_mode(get_irq_regs()));
-- 
1.7.9.1



From plagnioj at jcrosoft.com  Fri Mar 30 07:59:06 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Fri, 30 Mar 2012 13:59:06 +0200
Subject: [PATCH] ARM: at91: add support for Telit GE863-PRO3 Evaluation Kit
In-Reply-To: <1333097816-8641-1-git-send-email-fabio.porcedda@gmail.com>
References: <1333097816-8641-1-git-send-email-fabio.porcedda@gmail.com>
Message-ID: <20120330115906.GM7757@game.jcrosoft.org>

On 10:56 Fri 30 Mar     , Fabio Porcedda wrote:
> Based on board-sam9260ek.c.
> 
> Signed-off-by: Fabio Porcedda <fabio.porcedda at gmail.com>
> ---
>  arch/arm/mach-at91/Kconfig            |    6 +
>  arch/arm/mach-at91/Makefile           |    1 +
>  arch/arm/mach-at91/board-ge863-pro3.c |  338 +++++++++++++++++++++++++++++++++
>  3 files changed, 345 insertions(+)
>  create mode 100644 arch/arm/mach-at91/board-ge863-pro3.c
> 
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index 45db05d..4197a2a 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -272,6 +272,12 @@ config MACH_FLEXIBITY
>  	  Select this if you are using Flexibity Connect board
>  	  <http://www.flexibity.com>
>  
> +config MACH_GE863_PRO3_EVK
> +       bool "Telit GE863-PRO3 Evaluation Kit"
> +       help
> +         Select this if you are using Telit GE863-PRO3 Evaluation Kit
> +	 <http://www.telit.com>
> +
>  endif
tks for the patch but now we have close the non dt board for this soc

and for 3.5 nearly all the devices of this soc will converted to DT

so you need to switch to DT too

As today I've not finished the pinctrl support you need to do all the pin mux
in the bootlader. For 3.5 it will not be the case anymore

Best Rebards,
J.


From grinberg at compulab.co.il  Fri Mar 30 08:24:37 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Fri, 30 Mar 2012 15:24:37 +0300
Subject: [PATCH v3] ARM: pxa: fix build failure for regulator consumer
 in em-x270.c
In-Reply-To: <1333043034-3374-1-git-send-email-paul.gortmaker@windriver.com>
References: <20120329151157.GT3668@opensource.wolfsonmicro.com>
 <1333043034-3374-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <4F75A605.8040601@compulab.co.il>

On 03/29/12 19:43, Paul Gortmaker wrote:
> Commit 737f360d5bef5e01c6cfa755dca0b449a154c1e0
> 
>   "regulator: Remove support for supplies specified by struct device"
> 
> caused this file to break, since it was still relying on the
> device field to be present.  Map it onto dev_name appropriately
> 
> Since there are two consumers with the name "reg-userspace-consumer",
> we have to supply the ID as a suffix in the REGULATOR_CONSUMER calls.
> 
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> CC: Mark Brown <broonie at opensource.wolfsonmicro.com>
> ---
> 
> [v3: add .0/.1 ID suffix to "reg-userspace-consumer" instances ]
> 
> diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
> index c1b65da..16ec557 100644
> --- a/arch/arm/mach-pxa/em-x270.c
> +++ b/arch/arm/mach-pxa/em-x270.c
> @@ -1083,19 +1083,19 @@ static void __init em_x270_userspace_consumers_init(void)
>  }
>  
>  /* DA9030 related initializations */
> -#define REGULATOR_CONSUMER(_name, _dev, _supply)			       \
> +#define REGULATOR_CONSUMER(_name, _dev_name, _supply)		        \
>  	static struct regulator_consumer_supply _name##_consumers[] = {	\
>  		{							\
> -			.dev = _dev,					\
> +			.dev_name = _dev_name,				\
>  			.supply = _supply,				\
>  		},							\
>  	}
>  
> -REGULATOR_CONSUMER(ldo3, &em_x270_gps_userspace_consumer.dev, "vcc gps");
> +REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer.0", "vcc gps");
>  REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
> -REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
> +REGULATOR_CONSUMER(ldo10, "pxa2xx-mci", "vcc sdio");
>  REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
> -REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
> +REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer.1", "vcc gprs");
>  REGULATOR_CONSUMER(buck2, NULL, "vcc_core");
>  
>  #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask)		\

Better late then never...
Tested and works as expected.
Thanks for the patch.


-- 
Regards,
Igor.


From catalin.marinas at arm.com  Fri Mar 30 08:29:47 2012
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 30 Mar 2012 13:29:47 +0100
Subject: [PATCH] ARM: Do not map the vectors page as write-through on UP
 systems
Message-ID: <1333110587-12879-1-git-send-email-catalin.marinas@arm.com>

The vectors page has been traditionally mapped as WT on UP systems but
this creates a mismatched alias with the directly mapped RAM that is
using WB attributes. On newer processors like Cortex-A15 this has
implications on the data/instructions coherency at the point of
unification (usually L2).

This patch removes such restriction.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Tested-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/mm/mmu.c |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 94c5a0c..21c20e3 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -415,12 +415,6 @@ static void __init build_mem_type_table(void)
 	vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 
 	/*
-	 * Only use write-through for non-SMP systems
-	 */
-	if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
-		vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
-
-	/*
 	 * Enable CPU-specific coherency if supported.
 	 * (Only available on XSC3 at the moment.)
 	 */



From nicolas.ferre at atmel.com  Fri Mar 30 08:31:09 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 30 Mar 2012 14:31:09 +0200
Subject: [PATCH] ARM: at91: include newly created system_misc.h file
In-Reply-To: <cover.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <1333110669-24554-1-git-send-email-nicolas.ferre@atmel.com>

system.h file has been split by commit "0195c00". Now include
system_misc.h for having access to arm_pm_restart.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
---
Hi,

It seems that this split of system.h is now in linus' tree. AT91 build
is broken without this patch.

I will include it in a "at91-fixes" series that I will rebase on top
of 3.4-rc1.

 arch/arm/mach-at91/setup.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 1083739..d4d334a 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -12,6 +12,7 @@
 #include <linux/of_address.h>
 
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 
 #include <mach/hardware.h>
 #include <mach/cpu.h>
-- 
1.7.9.4



From santosh.shilimkar at ti.com  Fri Mar 30 08:53:30 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 30 Mar 2012 18:23:30 +0530
Subject: [PATCHv2 0/5] coupled cpuidle state support
In-Reply-To: <CAMbhsRQAw2+as13NVvWkh7ojyRs+jNpFist2gmiiEY52U=o84A@mail.gmail.com>
References: <1331749794-8056-1-git-send-email-ccross@android.com>
 <CAMbhsRQAw2+as13NVvWkh7ojyRs+jNpFist2gmiiEY52U=o84A@mail.gmail.com>
Message-ID: <4F75ACCA.4090009@ti.com>

Colin,

On Friday 16 March 2012 05:07 AM, Colin Cross wrote:
> On Wed, Mar 14, 2012 at 11:29 AM, Colin Cross <ccross at android.com> wrote:

[...]

>>
>> v2:
>>   * removed the coupled lock, replacing it with atomic counters
>>   * added a check for outstanding pokes before beginning the
>>     final transition to avoid extra wakeups
>>   * made the cpuidle_coupled struct completely private
>>   * fixed kerneldoc comment formatting
>>   * added a patch with a helper function for resynchronizing
>>     cpus after aborting idle
>>   * added a patch (not for merging) to add trace events for
>>     verification and performance testing
> 
> I forgot to mention, this patch series is on v3.3-rc7, and will
> conflict with the cpuidle timekeeping patches.  If those go in first
> (which is likely), I will rework this series on top of it.  I left it
> on v3.3-rc7 now to make testing easier.

I have re-based your series against Len Browns
next branch [1] which has time keeping and other cpuidle patches.
Have also folded the CPU hotplug fix which I posted in the
original coupled idle patch.

If you want, the updated branch can be pulled from:

git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
for_3.5/coupled_cpuidle-rebase

Regards
Santosh

[1] Power Management
git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux.git


From fabio.porcedda at gmail.com  Fri Mar 30 09:02:35 2012
From: fabio.porcedda at gmail.com (Fabio Porcedda)
Date: Fri, 30 Mar 2012 15:02:35 +0200
Subject: [PATCH] ARM: at91: add support for Telit GE863-PRO3 Evaluation Kit
In-Reply-To: <20120330115906.GM7757@game.jcrosoft.org>
References: <1333097816-8641-1-git-send-email-fabio.porcedda@gmail.com>
 <20120330115906.GM7757@game.jcrosoft.org>
Message-ID: <CAHkwnC9XZneX-9def=0VYifyVDG4ZtXo1L+ZJNQDhxSm1fPj9A@mail.gmail.com>

On Fri, Mar 30, 2012 at 1:59 PM, Jean-Christophe PLAGNIOL-VILLARD
<plagnioj at jcrosoft.com> wrote:
> tks for the patch but now we have close the non dt board for this soc

Thanks for the reply.

> and for 3.5 nearly all the devices of this soc will converted to DT
>
> so you need to switch to DT too

Ok, i will switch to DT too.
Do you plan to add support to any 9260 board to the board-dt.c for 3.5?
I think that, as far as there is a working 9260 board using DT, i can
work on the GE863-PRO3 support using DT.

> As today I've not finished the pinctrl support you need to do all the pin mux
> in the bootlader. For 3.5 it will not be the case anymore
>
> Best Regards,
> J.

Thanks and regards
-- 
Fabio Porcedda


From timur at freescale.com  Fri Mar 30 09:03:28 2012
From: timur at freescale.com (Timur Tabi)
Date: Fri, 30 Mar 2012 08:03:28 -0500
Subject: [PATCH] ASoC: fsl: enable ssi clock in probe function
In-Reply-To: <20120330055543.GH19506@S2101-09.ap.freescale.net>
References: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>
 <20120329112949.GM3668@opensource.wolfsonmicro.com>
 <4F748751.3020300@freescale.com>
 <20120329160916.GG19506@S2101-09.ap.freescale.net>
 <4F748C8E.1010702@freescale.com>
 <20120330055543.GH19506@S2101-09.ap.freescale.net>
Message-ID: <4F75AF20.6080009@freescale.com>

Shawn Guo wrote:
> I guess you only meant mpc85xx_defconfig (and mpc85xx_smp_defconfig).
> I sent the patch after compile-testing for mpc85xx_defconfig, and
> took it for granted that mpc8610_hpcd_defconfig will also compile.
> But I just discovered that PPC_CLOCK is not enabled for
> mpc8610_hpcd_defconfig, so it fails on the final link.

Argh.  I was thinking about testing mpc8610 as well, but I thought, "Hey,
p1022ds works, why bother testing the 8610?  Why would it fail?"

> I just sent a patch proposing to fix it by always building in PPC_CLOCK
> for FSL_SOC.

You'll need to get Kumar Gala's ACK on that one, but if only the 8610 is
broken, then I don't think he'll like it.

-- 
Timur Tabi
Linux kernel developer at Freescale



From linux at arm.linux.org.uk  Fri Mar 30 09:12:00 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 30 Mar 2012 14:12:00 +0100
Subject: [PATCH] cpufreq: OMAP: fix build errors: depends on ARCH_OMAP2PLUS
In-Reply-To: <1332807568-638-1-git-send-email-khilman@ti.com>
References: <1332807568-638-1-git-send-email-khilman@ti.com>
Message-ID: <20120330131200.GA23442@n2100.arm.linux.org.uk>

On Mon, Mar 26, 2012 at 05:19:28PM -0700, Kevin Hilman wrote:
> The OMAP driver needs a 'depends on ARCH_OMAP2PLUS' since it only
> builds for OMAP2+ platforms.
> 
> This 'depends on' was in the original patch from Russell King, but was
> erroneously removed by me when making this option user-selectable in
> commit b09db45c (cpufreq: OMAP driver depends CPUfreq tables.)  This
> patch remedies that.
> 
> Apologies to Russell King for breaking his originally working patch.
> 
> Also, thanks to Grazvydas Ignotas for reporting the same problem.
> 
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> Cc: Grazvydas Ignotas <notasas at gmail.com>
> Signed-off-by: Kevin Hilman <khilman at ti.com>
> ---
> Dave, this applies on top of your current fixes branch, and fixes a 
> problem introduced there by me.  Please merge for v3.4-rc.  Thanks.

Can you please check that you've picked up everything that's necessary,
as I'm still seeing the below as outstanding from my original patch.

commit e55a42528cebb8fa7408dc95abb3859639a46750
Author: Russell King <rmk+kernel at arm.linux.org.uk>
Date:   Wed Feb 15 11:20:51 2012 +0000

    ARM: OMAP: fix cpufreq build
    
    OMAPs cpufreq requires the frequency table support, but nothing ensures
    that this is selected.  This can result in configurations which fail to
    build:
    
    drivers/built-in.o:(.data+0x5238): undefined reference to `cpufreq_freq_attr_scaling_available_freqs'
    drivers/cpufreq/omap-cpufreq.c:88: undefined reference to `cpufreq_frequency_table_target'
    drivers/cpufreq/omap-cpufreq.c:60: undefined reference to `cpufreq_frequency_table_verify'
    drivers/cpufreq/omap-cpufreq.c:186: undefined reference to `cpufreq_frequency_table_cpuinfo'
    drivers/cpufreq/omap-cpufreq.c:190: undefined reference to `cpufreq_frequency_table_get_attr'
    
    Fix this by introducing a new configuration variable and having that
    select CPU_FREQ_TABLE.
    
    Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>

diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 7072e0d..ad35d4e 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -166,7 +166,7 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 	return 0;
 }
 
-#ifdef CONFIG_CPU_FREQ
+#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
 /*
  * Walk PRCM rate table and fillout cpufreq freq_table
  * XXX This should be replaced by an OPP layer in the near future
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index f57ed5b..450feb0 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -536,7 +536,7 @@ struct clk_functions omap2_clk_functions = {
 	.clk_set_rate		= omap2_clk_set_rate,
 	.clk_set_parent		= omap2_clk_set_parent,
 	.clk_disable_unused	= omap2_clk_disable_unused,
-#ifdef CONFIG_CPU_FREQ
+#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
 	/* These will be removed when the OPP code is integrated */
 	.clk_init_cpufreq_table	= omap2_clk_init_cpufreq_table,
 	.clk_exit_cpufreq_table	= omap2_clk_exit_cpufreq_table,
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b8c2a68..f331cfc 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -146,7 +146,7 @@ extern const struct clksel_rate gpt_sys_rates[];
 extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 
-#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
+#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_ARM_OMAP2PLUS_CPUFREQ)
 extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #else
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 56b6f8b..618cf80 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -398,7 +398,7 @@ struct clk dummy_ck = {
 	.ops	= &clkops_null,
 };
 
-#ifdef CONFIG_CPU_FREQ
+#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
 void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 {
 	unsigned long flags;
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 240a7b9..879ba27 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -283,7 +283,7 @@ struct clk_functions {
 	void		(*clk_allow_idle)(struct clk *clk);
 	void		(*clk_deny_idle)(struct clk *clk);
 	void		(*clk_disable_unused)(struct clk *clk);
-#ifdef CONFIG_CPU_FREQ
+#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
 	void		(*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
 	void		(*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
 #endif
@@ -301,7 +301,7 @@ extern void recalculate_root_clocks(void);
 extern unsigned long followparent_recalc(struct clk *clk);
 extern void clk_enable_init_clocks(void);
 unsigned long omap_fixed_divisor_recalc(struct clk *clk);
-#ifdef CONFIG_CPU_FREQ
+#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 32d790d..587b578 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -3,8 +3,8 @@
 #
 
 config ARM_OMAP2PLUS_CPUFREQ
-	bool "TI OMAP2+"
-	default ARCH_OMAP2PLUS
+	def_bool y
+	depends on ARCH_OMAP2PLUS
 	select CPU_FREQ_TABLE
 
 config ARM_S3C2416_CPUFREQ



From shawn.guo at linaro.org  Fri Mar 30 09:13:24 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 30 Mar 2012 21:13:24 +0800
Subject: [PATCH v3] ARM: mxs: Add initial support for Bluegiga APX4
 Development Kit
In-Reply-To: <20120105113106.GR11810@n2100.arm.linux.org.uk>
References: <1323766966-30502-1-git-send-email-lauri.hintsala@bluegiga.com>
 <20111219071350.GH4962@S2100-06.ap.freescale.net>
 <4EEEE40C.3000200@bluegiga.com>
 <20111219091916.GJ4962@S2100-06.ap.freescale.net>
 <20111219091322.GD14542@n2100.arm.linux.org.uk>
 <20120104135204.GA14741@S2100-06.ap.freescale.net>
 <20120104211800.GF11810@n2100.arm.linux.org.uk>
 <20120105113106.GR11810@n2100.arm.linux.org.uk>
Message-ID: <20120330131320.GH3254@S2101-09.ap.freescale.net>

On Thu, Jan 05, 2012 at 11:31:06AM +0000, Russell King - ARM Linux wrote:
> On Wed, Jan 04, 2012 at 09:18:00PM +0000, Russell King - ARM Linux wrote:
> > On Wed, Jan 04, 2012 at 09:52:05PM +0800, Shawn Guo wrote:
> > > On Mon, Dec 19, 2011 at 09:13:22AM +0000, Russell King - ARM Linux wrote:
> > > > No.  It will be automatically removed from any update as long as it does
> > > > not conform to the requirements - that is, in this case, the strings
> > > > being out of sync indentified in the message to which you replied to.
> > > > 
> > > > Someone needs to tell me what the correct entry is supposed to look like.
> > > > 
> > > Hi Russell,
> > > 
> > > Any chance to have APX4DEVKIT included in your patch 'ARM: Update
> > > mach-types' for 3.3?
> > 
> > As it appears when I run the update script, the answer is yes.  I'll
> > update the commit in the next couple of days (I want to reduce the
> > number of times I re-merge the tree now that I've a git-rerere immune
> > conflict to deal with.)
> 
> I'll change that - as 3.2 was released last night.  I'm not going to
> update mach-types now as that would be suicide - updating it will
> mean a bunch of entries will be deleted, and we don't know whether that
> will cause build failures.
> 
> So... not this side of the merge window.

Hi Russell,

I thought you will send a mach-types update during v3.4 merge window,
so I merged APX4DEVKIT board file and it's now on mainline (not enabled
in mxs_defconfig though).  But I have not seen mach-types update yet
while the merge window is almost done.  Do you still plan to send an
update or plan to stop updating mach-types?

Regards,
Shawn


From linux at arm.linux.org.uk  Fri Mar 30 09:15:10 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 30 Mar 2012 14:15:10 +0100
Subject: [PATCH v3] ARM: mxs: Add initial support for Bluegiga APX4
 Development Kit
In-Reply-To: <20120330131320.GH3254@S2101-09.ap.freescale.net>
References: <1323766966-30502-1-git-send-email-lauri.hintsala@bluegiga.com>
 <20111219071350.GH4962@S2100-06.ap.freescale.net>
 <4EEEE40C.3000200@bluegiga.com>
 <20111219091916.GJ4962@S2100-06.ap.freescale.net>
 <20111219091322.GD14542@n2100.arm.linux.org.uk>
 <20120104135204.GA14741@S2100-06.ap.freescale.net>
 <20120104211800.GF11810@n2100.arm.linux.org.uk>
 <20120105113106.GR11810@n2100.arm.linux.org.uk>
 <20120330131320.GH3254@S2101-09.ap.freescale.net>
Message-ID: <20120330131509.GE22981@n2100.arm.linux.org.uk>

On Fri, Mar 30, 2012 at 09:13:24PM +0800, Shawn Guo wrote:
> On Thu, Jan 05, 2012 at 11:31:06AM +0000, Russell King - ARM Linux wrote:
> > On Wed, Jan 04, 2012 at 09:18:00PM +0000, Russell King - ARM Linux wrote:
> > > On Wed, Jan 04, 2012 at 09:52:05PM +0800, Shawn Guo wrote:
> > > > On Mon, Dec 19, 2011 at 09:13:22AM +0000, Russell King - ARM Linux wrote:
> > > > > No.  It will be automatically removed from any update as long as it does
> > > > > not conform to the requirements - that is, in this case, the strings
> > > > > being out of sync indentified in the message to which you replied to.
> > > > > 
> > > > > Someone needs to tell me what the correct entry is supposed to look like.
> > > > > 
> > > > Hi Russell,
> > > > 
> > > > Any chance to have APX4DEVKIT included in your patch 'ARM: Update
> > > > mach-types' for 3.3?
> > > 
> > > As it appears when I run the update script, the answer is yes.  I'll
> > > update the commit in the next couple of days (I want to reduce the
> > > number of times I re-merge the tree now that I've a git-rerere immune
> > > conflict to deal with.)
> > 
> > I'll change that - as 3.2 was released last night.  I'm not going to
> > update mach-types now as that would be suicide - updating it will
> > mean a bunch of entries will be deleted, and we don't know whether that
> > will cause build failures.
> > 
> > So... not this side of the merge window.
> 
> Hi Russell,
> 
> I thought you will send a mach-types update during v3.4 merge window,
> so I merged APX4DEVKIT board file and it's now on mainline (not enabled
> in mxs_defconfig though).  But I have not seen mach-types update yet
> while the merge window is almost done.  Do you still plan to send an
> update or plan to stop updating mach-types?

Well, it seems I've been missing having that branch in linux-next for
almost the entire previous cycle.  It would be utterly irresponsible
to now commit that into mainline because of the -now- huge number of
platform IDs that it deletes.

I assume, therefore, that you don't keep an eye on what's in linux-next.


From shawn.guo at linaro.org  Fri Mar 30 09:16:56 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 30 Mar 2012 21:16:56 +0800
Subject: [PATCH] ASoC: fsl: enable ssi clock in probe function
In-Reply-To: <4F75AF20.6080009@freescale.com>
References: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>
 <20120329112949.GM3668@opensource.wolfsonmicro.com>
 <4F748751.3020300@freescale.com>
 <20120329160916.GG19506@S2101-09.ap.freescale.net>
 <4F748C8E.1010702@freescale.com>
 <20120330055543.GH19506@S2101-09.ap.freescale.net>
 <4F75AF20.6080009@freescale.com>
Message-ID: <CAAQ0ZWR5ws7od92bOcLn-kDdbSPAVRDQwdVu-90tRfDSH_49KA@mail.gmail.com>

On 30 March 2012 21:03, Timur Tabi <timur at freescale.com> wrote:
...
> You'll need to get Kumar Gala's ACK on that one, but if only the 8610 is
> broken, then I don't think he'll like it.
>
It's only about building in arch/powerpc/kernel/clock.c, which is a
pretty dummy clk API and does not take much cost.

Regards,
Shawn


From nicolas.pitre at linaro.org  Fri Mar 30 09:19:13 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 30 Mar 2012 09:19:13 -0400 (EDT)
Subject: [PATCH 0/4] memcpy optimized with strd/ldrd
In-Reply-To: <030501cd0e6a$03642770$0a2c7650$%kim@samsung.com>
References: <03e101cd0e07$eec39f10$cc4add30$@com>
 <030501cd0e6a$03642770$0a2c7650$%kim@samsung.com>
Message-ID: <alpine.LFD.2.02.1203300914510.24151@xanadu.home>

On Fri, 30 Mar 2012, Boojin Kim wrote:

> Nicolas Pitre wrote:
> >
> >
> > Here's my version.  Lightly tested.
> > I have no A15 hardware to run any performance comparison though.
> >
> I'm reviewing and testing your patch. But, My other work disturbs to reviewing it.
> I will give you feedback soon within this week.
> Wait a little more.
> And, Thanks for your patches. :)

FYI, it occurred to me that some corner cases might not be quite right 
with regards to alignment for the STRD instruction.  It seems that the 
hardware on which I tested it (Marvell Dove CPU) apparently copes with 
misaligned SDRD's when they're still 32-bit aligned.  So I need to run 
this code through a real validation harness on different hardware.


Nicolas


From timur at freescale.com  Fri Mar 30 09:19:44 2012
From: timur at freescale.com (Timur Tabi)
Date: Fri, 30 Mar 2012 08:19:44 -0500
Subject: [PATCH] ASoC: fsl: enable ssi clock in probe function
In-Reply-To: <CAAQ0ZWR5ws7od92bOcLn-kDdbSPAVRDQwdVu-90tRfDSH_49KA@mail.gmail.com>
References: <1332989621-5211-1-git-send-email-shawn.guo@linaro.org>
 <20120329112949.GM3668@opensource.wolfsonmicro.com>
 <4F748751.3020300@freescale.com>
 <20120329160916.GG19506@S2101-09.ap.freescale.net>
 <4F748C8E.1010702@freescale.com>
 <20120330055543.GH19506@S2101-09.ap.freescale.net>
 <4F75AF20.6080009@freescale.com>
 <CAAQ0ZWR5ws7od92bOcLn-kDdbSPAVRDQwdVu-90tRfDSH_49KA@mail.gmail.com>
Message-ID: <4F75B2F0.6090104@freescale.com>

Shawn Guo wrote:
>> > You'll need to get Kumar Gala's ACK on that one, but if only the 8610 is
>> > broken, then I don't think he'll like it.
>> >
> It's only about building in arch/powerpc/kernel/clock.c, which is a
> pretty dummy clk API and does not take much cost.

Like I said, it needs Kumar's review.  You should ping him on it.  He may
just want the 8610 fixed.

-- 
Timur Tabi
Linux kernel developer at Freescale



From linux at arm.linux.org.uk  Fri Mar 30 09:20:40 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 30 Mar 2012 14:20:40 +0100
Subject: [PATCH v3] ARM: mxs: Add initial support for Bluegiga APX4
 Development Kit
In-Reply-To: <20120330131509.GE22981@n2100.arm.linux.org.uk>
References: <1323766966-30502-1-git-send-email-lauri.hintsala@bluegiga.com>
 <20111219071350.GH4962@S2100-06.ap.freescale.net>
 <4EEEE40C.3000200@bluegiga.com>
 <20111219091916.GJ4962@S2100-06.ap.freescale.net>
 <20111219091322.GD14542@n2100.arm.linux.org.uk>
 <20120104135204.GA14741@S2100-06.ap.freescale.net>
 <20120104211800.GF11810@n2100.arm.linux.org.uk>
 <20120105113106.GR11810@n2100.arm.linux.org.uk>
 <20120330131320.GH3254@S2101-09.ap.freescale.net>
 <20120330131509.GE22981@n2100.arm.linux.org.uk>
Message-ID: <20120330132040.GF22981@n2100.arm.linux.org.uk>

On Fri, Mar 30, 2012 at 02:15:10PM +0100, Russell King - ARM Linux wrote:
> On Fri, Mar 30, 2012 at 09:13:24PM +0800, Shawn Guo wrote:
> > On Thu, Jan 05, 2012 at 11:31:06AM +0000, Russell King - ARM Linux wrote:
> > > On Wed, Jan 04, 2012 at 09:18:00PM +0000, Russell King - ARM Linux wrote:
> > > > On Wed, Jan 04, 2012 at 09:52:05PM +0800, Shawn Guo wrote:
> > > > > On Mon, Dec 19, 2011 at 09:13:22AM +0000, Russell King - ARM Linux wrote:
> > > > > > No.  It will be automatically removed from any update as long as it does
> > > > > > not conform to the requirements - that is, in this case, the strings
> > > > > > being out of sync indentified in the message to which you replied to.
> > > > > > 
> > > > > > Someone needs to tell me what the correct entry is supposed to look like.
> > > > > > 
> > > > > Hi Russell,
> > > > > 
> > > > > Any chance to have APX4DEVKIT included in your patch 'ARM: Update
> > > > > mach-types' for 3.3?
> > > > 
> > > > As it appears when I run the update script, the answer is yes.  I'll
> > > > update the commit in the next couple of days (I want to reduce the
> > > > number of times I re-merge the tree now that I've a git-rerere immune
> > > > conflict to deal with.)
> > > 
> > > I'll change that - as 3.2 was released last night.  I'm not going to
> > > update mach-types now as that would be suicide - updating it will
> > > mean a bunch of entries will be deleted, and we don't know whether that
> > > will cause build failures.
> > > 
> > > So... not this side of the merge window.
> > 
> > Hi Russell,
> > 
> > I thought you will send a mach-types update during v3.4 merge window,
> > so I merged APX4DEVKIT board file and it's now on mainline (not enabled
> > in mxs_defconfig though).  But I have not seen mach-types update yet
> > while the merge window is almost done.  Do you still plan to send an
> > update or plan to stop updating mach-types?
> 
> Well, it seems I've been missing having that branch in linux-next for
> almost the entire previous cycle.  It would be utterly irresponsible
> to now commit that into mainline because of the -now- huge number of
> platform IDs that it deletes.
> 
> I assume, therefore, that you don't keep an eye on what's in linux-next.

You've actually asked around the same time in the cycle as you asked last
time, and I gave more or less the same reply back then.  Nothing's really
changed.  There is no way in hell that I'm committing any kind of
mach-types update _during_ a merge window.

The only time that I'd consider doing that is _outside_ of a merge window
in preparation for the _next_ merge window, and having it sit in linux-next
for a decent amount of time so that people can see it coming, and deal with
the implications of that update.  I'd say a minimum of a month in linux-next
is required to avoid problems with people on vacations and the like.


From shawn.guo at linaro.org  Fri Mar 30 09:22:59 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 30 Mar 2012 21:22:59 +0800
Subject: [PATCH v3] ARM: mxs: Add initial support for Bluegiga APX4
 Development Kit
In-Reply-To: <20120330131509.GE22981@n2100.arm.linux.org.uk>
References: <1323766966-30502-1-git-send-email-lauri.hintsala@bluegiga.com>
 <20111219071350.GH4962@S2100-06.ap.freescale.net>
 <4EEEE40C.3000200@bluegiga.com>
 <20111219091916.GJ4962@S2100-06.ap.freescale.net>
 <20111219091322.GD14542@n2100.arm.linux.org.uk>
 <20120104135204.GA14741@S2100-06.ap.freescale.net>
 <20120104211800.GF11810@n2100.arm.linux.org.uk>
 <20120105113106.GR11810@n2100.arm.linux.org.uk>
 <20120330131320.GH3254@S2101-09.ap.freescale.net>
 <20120330131509.GE22981@n2100.arm.linux.org.uk>
Message-ID: <20120330132256.GI3254@S2101-09.ap.freescale.net>

On Fri, Mar 30, 2012 at 02:15:10PM +0100, Russell King - ARM Linux wrote:
...
> Well, it seems I've been missing having that branch in linux-next for
> almost the entire previous cycle.  It would be utterly irresponsible
> to now commit that into mainline because of the -now- huge number of
> platform IDs that it deletes.
> 
I can live with that since mxs_defconfig has not enabled it.
randconfig build will probably complain though.

> I assume, therefore, that you don't keep an eye on what's in linux-next.

I have seen it's on the linux-next at the early time of the cycle,
but I have to admit that I have not done that at the later time.

-- 
Regards,
Shawn


From haojian.zhuang at gmail.com  Fri Mar 30 09:25:50 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 30 Mar 2012 21:25:50 +0800
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <1333104093.65224.YahooMailClassic@web29002.mail.ird.yahoo.com>
References: <CAN1soZwzBqDGTX+a-maVr5baaoZ7qwgdvXyPeya5R80cN_iA0w@mail.gmail.com>
 <1333104093.65224.YahooMailClassic@web29002.mail.ird.yahoo.com>
Message-ID: <CAN1soZwgUooLEcDimUxyLO20x0__pAa+J3wRrH3zoW3pJsR2bg@mail.gmail.com>

On Fri, Mar 30, 2012 at 6:41 PM, Paul Parsons <lost.distance at yahoo.com> wrote:
> --- On Fri, 30/3/12, Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
>> On Thu, Mar 29, 2012 at 2:12 AM, Paul
>> Parsons <lost.distance at yahoo.com>
>> wrote:
>> > On PXA2xx platforms, the MFP API (described in
>> Documentation/arm/pxa/mfp.txt)
>> > provides values for the following:
>> >
>> > 1. GPIO inputs (e.g. GPIO105_GPIO).
>> > 2. Alternate function inputs (e.g. GPIO105_CIF_DD_1).
>> > 3. Alternate function outputs (e.g.
>> GPIO105_KP_MKOUT_2).
>> >
>> > It does not provide values for GPIO outputs (i.e. AF0
>> outputs).
>> >
>> > One cannot use the macro used by the MFP API internally
>> - MFP_CFG_OUT() - to
>> > define new GPIO output values, since that macro is
>> forbidden in platform code.
>> >
>> > Without the ability to add GPIO outputs to the MFP
>> configuration, it is not
>> > possible to drive GPIO outputs high during sleep mode.
>> >
>> > This would be useful, for example, on the hx4700
>> platform, where driving the
>> > infrared powerdown GPIO 105 high during sleep mode
>> would save some mA.
>> >
>> > So my question is: what method should one use to add
>> GPIO outputs to the MFP
>> > configuration?
>> >
>> > One possible method, namely manually defining values in
>> the platform code:
>> >
>> > ? ? ? ?MFP_PIN_GPIO105 | MFP_AF0 | MFP_DIR_OUT |
>> MFP_LPM_DRIVE_HIGH,
>> >
>> > is essentially no different from using the forbidden
>> MFP_CFG_OUT() macro.
>> >
>>
>> Does MFP_CFG_OUT() help you? This macro is defined in
>> mfp-pxa2xx.h.
>
> Yes, MFP_CFG_OUT() does help. But it has been pointed out that
> MFP_CFG_OUT() is not allowed to be used in board support code:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086456.html
>
> Is that no longer true?

I'm sorry that I messed it. Since GPIOxx_GPIO is always defined as MFP_CFG_IN().
It seems that you're blocked to specify MFP_CFG_OUT().

Actually it's not a problem. While you're using it as output, you must
assign special
usage for this pin, like some peripheral rest signal. So I think that
you can define new
macro GPIOxx_yy() in mfp-pxa27x.h, like GPIO9_HZ_CLK(). Is it meaningful?

Best Regards
Haojian


From santosh.shilimkar at ti.com  Fri Mar 30 09:27:25 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 30 Mar 2012 18:57:25 +0530
Subject: [PATCH 0/3] OMAP4: CPUidle: Add coupled idle support
Message-ID: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>

The series adds the coupled cpuidle support for OMAP4 based on the v2
series posted [1]. This makes OMAP4 to support SMP cpuidle and also
removes the hard dependency of off-lining CPU1 to trigger deeper
C-states.

I have put together a branch which is based on 3.3 kernel with
Len Browns next branch [2] which has time keeping and other cpuidle
patches which will mostly get merged by 3.4-rc1 and rebased coupled
idle series from [1].

git://gitorious.org/omap-sw-develoment/linux-omap-dev.git
for_3.5/omap4_coupled_cpuidle-rebase

Special thanks to Kevin Hilman and Colin Cross on their help on this
series.

Kevin Hilman (1):
  ARM: OMAP4: CPUidle: add synchronization for coupled idle states

Santosh Shilimkar (2):
  ARM: OMAP: timer: allow gp timer clock-event to be used on both cpus
  ARM: OMAP4: cpuidle: Use coupled cpuidle states to implement SMP
    cpuidle.

 arch/arm/mach-omap2/Kconfig       |    1 +
 arch/arm/mach-omap2/cpuidle44xx.c |  187 ++++++++++++++++++++++++-------------
 arch/arm/mach-omap2/timer.c       |    4 +-
 3 files changed, 124 insertions(+), 68 deletions(-)


Regards
Santosh
[1] http://lwn.net/Articles/486484/

[2] Power Management
git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux.git


From santosh.shilimkar at ti.com  Fri Mar 30 09:27:26 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 30 Mar 2012 18:57:26 +0530
Subject: [PATCH 1/3] ARM: OMAP: timer: allow gp timer clock-event to be used
 on both cpus
In-Reply-To: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1333114048-26136-2-git-send-email-santosh.shilimkar@ti.com>

For coupled cpuidle to work when both cpus are active, it needs a global timer
that can handle events for both cpus.  This timer is used as the broadcast
clock-event when the per-cpu timer hardware stop in low power states.
Set the cpumask of clockevent_gpt to all cpus, set the rating correctly, and
set the irq to allow the clockevent core to determine the affinity of the
timer.

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
---
 arch/arm/mach-omap2/timer.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index fc73567..e33f9c4 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -135,6 +135,7 @@ static struct clock_event_device clockevent_gpt = {
 	.name		= "gp timer",
 	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 	.shift		= 32,
+	.rating		= 300,
 	.set_next_event	= omap2_gp_timer_set_next_event,
 	.set_mode	= omap2_gp_timer_set_mode,
 };
@@ -225,7 +226,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
 		clockevent_delta2ns(3, &clockevent_gpt);
 		/* Timer internal resynch latency. */
 
-	clockevent_gpt.cpumask = cpumask_of(0);
+	clockevent_gpt.cpumask = cpu_all_mask;
+	clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
 	clockevents_register_device(&clockevent_gpt);
 
 	pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
-- 
1.7.5.4



From santosh.shilimkar at ti.com  Fri Mar 30 09:27:27 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 30 Mar 2012 18:57:27 +0530
Subject: [PATCH 2/3] ARM: OMAP4: cpuidle: Use coupled cpuidle states to
 implement SMP cpuidle.
In-Reply-To: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1333114048-26136-3-git-send-email-santosh.shilimkar@ti.com>

OMAP4 CPUDILE driver is converted mainly based on notes from the
coupled cpuidle patch series.

The changes include :
- Register both CPUs and C-states to cpuidle driver.
- Set struct cpuidle_device.coupled_cpus
- Set struct cpuidle_device.safe_state to non coupled state.
- Set CPUIDLE_FLAG_COUPLED in struct cpuidle_state.flags for each
  state that affects multiple cpus.
- Separate ->enter hooks for coupled & simple idle.
- CPU0 wait loop for CPU1 power transition.
- CPU1 wakeup mechanism for the idle exit.
- Enabling ARCH_NEEDS_CPU_IDLE_COUPLED for OMAP4.

Thanks to Kevin Hilman and Colin Cross on the suggestions/fixes
on the intermediate version of this patch.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
CC: Kevin Hilman <khilman at ti.com>
Cc: Colin Cross <ccross at android.com>
---
 arch/arm/mach-omap2/Kconfig       |    1 +
 arch/arm/mach-omap2/cpuidle44xx.c |  167 ++++++++++++++++++++++---------------
 2 files changed, 101 insertions(+), 67 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index e20c8ab..250786e 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -54,6 +54,7 @@ config ARCH_OMAP4
 	select PM_OPP if PM
 	select USB_ARCH_HAS_EHCI
 	select ARM_CPU_SUSPEND if PM
+	select ARCH_NEEDS_CPU_IDLE_COUPLED if CPU_IDLE
 
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index f386cbe..5724393 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -21,6 +21,7 @@
 #include "common.h"
 #include "pm.h"
 #include "prm.h"
+#include "clockdomain.h"
 
 #ifdef CONFIG_CPU_IDLE
 
@@ -44,10 +45,11 @@ static struct cpuidle_params cpuidle_params_table[] = {
 #define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
 
 struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
-static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
+static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
+static struct clockdomain *cpu_clkdm[NR_CPUS];
 
 /**
- * omap4_enter_idle - Programs OMAP4 to enter the specified state
+ * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
  * @dev: cpuidle device
  * @drv: cpuidle driver
  * @index: the index of state to be entered
@@ -56,34 +58,40 @@ static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
  * specified low power state selected by the governor.
  * Returns the amount of time spent in the low power state.
  */
-static int omap4_enter_idle(struct cpuidle_device *dev,
+static int omap4_enter_idle_simple(struct cpuidle_device *dev,
+				   struct cpuidle_driver *drv,
+				   int index)
+{
+	local_fiq_disable();
+	omap_do_wfi();
+	local_fiq_enable();
+
+	return index;
+}
+
+static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
 			struct cpuidle_driver *drv,
 			int index)
 {
 	struct omap4_idle_statedata *cx =
 			cpuidle_get_statedata(&dev->states_usage[index]);
-	u32 cpu1_state;
 	int cpu_id = smp_processor_id();
 
 	local_fiq_disable();
 
+	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
+
 	/*
-	 * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
+	 * CPU0 has to wait and stay ON until CPU1 is OFF state.
 	 * This is necessary to honour hardware recommondation
 	 * of triggeing all the possible low power modes once CPU1 is
 	 * out of coherency and in OFF mode.
-	 * Update dev->last_state so that governor stats reflects right
-	 * data.
 	 */
-	cpu1_state = pwrdm_read_pwrst(cpu1_pd);
-	if (cpu1_state != PWRDM_POWER_OFF) {
-		index = drv->safe_state_index;
-		cx = cpuidle_get_statedata(&dev->states_usage[index]);
+	if (dev->cpu == 0) {
+		while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF)
+			cpu_relax();
 	}
 
-	if (index > 0)
-		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
-
 	/*
 	 * Call idle CPU PM enter notifier chain so that
 	 * VFP and per CPU interrupt context is saved.
@@ -91,25 +99,35 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
 	if (cx->cpu_state == PWRDM_POWER_OFF)
 		cpu_pm_enter();
 
-	pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
-	omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
-
-	/*
-	 * Call idle CPU cluster PM enter notifier chain
-	 * to save GIC and wakeupgen context.
-	 */
-	if ((cx->mpu_state == PWRDM_POWER_RET) &&
-		(cx->mpu_logic_state == PWRDM_POWER_OFF))
-			cpu_cluster_pm_enter();
+	if (dev->cpu == 0) {
+		pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
+		omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
+
+		/*
+		 * Call idle CPU cluster PM enter notifier chain
+		 * to save GIC and wakeupgen context.
+		 */
+		if ((cx->mpu_state == PWRDM_POWER_RET) &&
+			(cx->mpu_logic_state == PWRDM_POWER_OFF))
+				cpu_cluster_pm_enter();
+	}
 
 	omap4_enter_lowpower(dev->cpu, cx->cpu_state);
 
+	if (dev->cpu == 0) {
+		/* Wakeup CPU1 only if it is not offlined */
+		if (cpumask_test_cpu(1, cpu_online_mask)) {
+			clkdm_wakeup(cpu_clkdm[1]);
+			clkdm_allow_idle(cpu_clkdm[1]);
+		}
+	}
+
 	/*
 	 * Call idle CPU PM exit notifier chain to restore
 	 * VFP and per CPU IRQ context. Only CPU0 state is
 	 * considered since CPU1 is managed by CPU hotplug.
 	 */
-	if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
+	if (pwrdm_read_prev_pwrst(cpu_pd[dev->cpu]) == PWRDM_POWER_OFF)
 		cpu_pm_exit();
 
 	/*
@@ -119,8 +137,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
 	if (omap4_mpuss_read_prev_context_state())
 		cpu_cluster_pm_exit();
 
-	if (index > 0)
-		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
+	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
 
 	local_fiq_enable();
 
@@ -136,14 +153,17 @@ struct cpuidle_driver omap4_idle_driver = {
 };
 
 static inline void _fill_cstate(struct cpuidle_driver *drv,
-					int idx, const char *descr)
+					int idx, const char *descr, int flags)
 {
 	struct cpuidle_state *state = &drv->states[idx];
 
 	state->exit_latency	= cpuidle_params_table[idx].exit_latency;
 	state->target_residency	= cpuidle_params_table[idx].target_residency;
-	state->flags		= CPUIDLE_FLAG_TIME_VALID;
-	state->enter		= omap4_enter_idle;
+	state->flags		= (CPUIDLE_FLAG_TIME_VALID | flags);
+	if (state->flags & CPUIDLE_FLAG_COUPLED)
+		state->enter		= omap4_enter_idle_coupled;
+	else
+		state->enter		= omap4_enter_idle_simple;
 	sprintf(state->name, "C%d", idx + 1);
 	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
 }
@@ -177,47 +197,60 @@ int __init omap4_idle_init(void)
 	unsigned int cpu_id = 0;
 
 	mpu_pd = pwrdm_lookup("mpu_pwrdm");
-	cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
-	cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
-	if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
+	cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
+	cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
+	if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
 		return -ENODEV;
 
+	cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
+	cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
+	if (!cpu_clkdm[0] || !cpu_clkdm[1])
+		return -ENODEV;
 
-	drv->safe_state_index = -1;
-	dev = &per_cpu(omap4_idle_dev, cpu_id);
-	dev->cpu = cpu_id;
-
-	/* C1 - CPU0 ON + CPU1 ON + MPU ON */
-	_fill_cstate(drv, 0, "MPUSS ON");
-	drv->safe_state_index = 0;
-	cx = _fill_cstate_usage(dev, 0);
-	cx->valid = 1;	/* C1 is always valid */
-	cx->cpu_state = PWRDM_POWER_ON;
-	cx->mpu_state = PWRDM_POWER_ON;
-	cx->mpu_logic_state = PWRDM_POWER_RET;
-
-	/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
-	_fill_cstate(drv, 1, "MPUSS CSWR");
-	cx = _fill_cstate_usage(dev, 1);
-	cx->cpu_state = PWRDM_POWER_OFF;
-	cx->mpu_state = PWRDM_POWER_RET;
-	cx->mpu_logic_state = PWRDM_POWER_RET;
-
-	/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
-	_fill_cstate(drv, 2, "MPUSS OSWR");
-	cx = _fill_cstate_usage(dev, 2);
-	cx->cpu_state = PWRDM_POWER_OFF;
-	cx->mpu_state = PWRDM_POWER_RET;
-	cx->mpu_logic_state = PWRDM_POWER_OFF;
-
-	drv->state_count = OMAP4_NUM_STATES;
-	cpuidle_register_driver(&omap4_idle_driver);
-
-	dev->state_count = OMAP4_NUM_STATES;
-	if (cpuidle_register_device(dev)) {
-		pr_err("%s: CPUidle register device failed\n", __func__);
-			return -EIO;
+	for_each_cpu(cpu_id, cpu_online_mask) {
+		drv->safe_state_index = -1;
+		dev = &per_cpu(omap4_idle_dev, cpu_id);
+		dev->cpu = cpu_id;
+		dev->state_count = 0;
+		dev->coupled_cpus = *cpu_online_mask;
+		drv->state_count = 0;
+
+		/* C1 - CPU0 ON + CPU1 ON + MPU ON */
+		_fill_cstate(drv, 0, "MPUSS ON", 0);
+		drv->safe_state_index = 0;
+		cx = _fill_cstate_usage(dev, 0);
+		cx->valid = 1;	/* C1 is always valid */
+		cx->cpu_state = PWRDM_POWER_ON;
+		cx->mpu_state = PWRDM_POWER_ON;
+		cx->mpu_logic_state = PWRDM_POWER_RET;
+		dev->state_count++;
+		drv->state_count++;
+
+		/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
+		_fill_cstate(drv, 1, "MPUSS CSWR", CPUIDLE_FLAG_COUPLED);
+		cx = _fill_cstate_usage(dev, 1);
+		cx->cpu_state = PWRDM_POWER_OFF;
+		cx->mpu_state = PWRDM_POWER_RET;
+		cx->mpu_logic_state = PWRDM_POWER_RET;
+		dev->state_count++;
+		drv->state_count++;
+
+		/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+		_fill_cstate(drv, 2, "MPUSS OSWR", CPUIDLE_FLAG_COUPLED);
+		cx = _fill_cstate_usage(dev, 2);
+		cx->cpu_state = PWRDM_POWER_OFF;
+		cx->mpu_state = PWRDM_POWER_RET;
+		cx->mpu_logic_state = PWRDM_POWER_OFF;
+		dev->state_count++;
+		drv->state_count++;
+
+		cpuidle_register_driver(&omap4_idle_driver);
+
+		if (cpuidle_register_device(dev)) {
+			pr_err("%s: CPUidle register failed\n", __func__);
+				return -EIO;
 		}
+	}
 
 	return 0;
 }
-- 
1.7.5.4



From santosh.shilimkar at ti.com  Fri Mar 30 09:27:28 2012
From: santosh.shilimkar at ti.com (Santosh Shilimkar)
Date: Fri, 30 Mar 2012 18:57:28 +0530
Subject: [PATCH 3/3] ARM: OMAP4: CPUidle: add synchronization for coupled idle
 states
In-Reply-To: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <1333114048-26136-4-git-send-email-santosh.shilimkar@ti.com>

From: Kevin Hilman <khilman at ti.com>

With coupled idle states, a failure for any CPU to hit a low power
state must be coordinated such that all CPUs abort.

On OMAP4, when entering a coupled state, CPU0 has to wait for CPU1 to
enter its low power state before it can enter its low power state.

This is implemented by letting CPU0 wait for the CPU1 powerdomain to
hit off.  However, there are conditions where CPU1 might abort/fail
and not hit off while CPU0 is waiting for it.  For example, a CPU1
wakeup or a failed attempt to hit off due to hardware conditions.

To avoid the deadlock where CPU0 would continually wait for CPU1 to
hit off-mode, this patch adds a flag to signal when each CPU has come
out of its low-power state.  CPU0 then checks whether CPU1 has hit off
*or* has already completed its attempt to hit off.  If the latter,
CPU0 must abort its attempt to hit a low-power state so the coupled
state enter method can return.

In addition, cpuidle_coupled_parallel_barrier() is used to ensure the
clearing of the 'done' flag is synchronized on all CPUs.

Cc: Colin Cross <ccross at android.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Kevin Hilman <khilman at ti.com>
---
 arch/arm/mach-omap2/cpuidle44xx.c |   22 +++++++++++++++++++++-
 1 files changed, 21 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 5724393..fcf6653 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -48,6 +48,9 @@ struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
 static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
 static struct clockdomain *cpu_clkdm[NR_CPUS];
 
+static atomic_t abort_barrier;
+static bool cpu_done[NR_CPUS];
+
 /**
  * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
  * @dev: cpuidle device
@@ -88,8 +91,20 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
 	 * out of coherency and in OFF mode.
 	 */
 	if (dev->cpu == 0) {
-		while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF)
+		while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
 			cpu_relax();
+
+			/*
+			 * CPU1 could have already entered & exited idle
+			 * without hitting off because of a wakeup
+			 * or a failed attempt to hit off mode.  Check for
+			 * that here, otherwise we could spin forever
+			 * waiting for CPU1 off.
+			 */
+			if (cpu_done[1])
+			    goto fail;
+
+		}
 	}
 
 	/*
@@ -113,6 +128,7 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
 	}
 
 	omap4_enter_lowpower(dev->cpu, cx->cpu_state);
+	cpu_done[dev->cpu] = true;
 
 	if (dev->cpu == 0) {
 		/* Wakeup CPU1 only if it is not offlined */
@@ -137,6 +153,10 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
 	if (omap4_mpuss_read_prev_context_state())
 		cpu_cluster_pm_exit();
 
+fail:
+	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
+	cpu_done[dev->cpu] = false;
+
 	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
 
 	local_fiq_enable();
-- 
1.7.5.4



From linux at arm.linux.org.uk  Fri Mar 30 09:28:40 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 30 Mar 2012 14:28:40 +0100
Subject: [PATCH v3] ARM: mxs: Add initial support for Bluegiga APX4
 Development Kit
In-Reply-To: <20120330132256.GI3254@S2101-09.ap.freescale.net>
References: <20111219071350.GH4962@S2100-06.ap.freescale.net>
 <4EEEE40C.3000200@bluegiga.com>
 <20111219091916.GJ4962@S2100-06.ap.freescale.net>
 <20111219091322.GD14542@n2100.arm.linux.org.uk>
 <20120104135204.GA14741@S2100-06.ap.freescale.net>
 <20120104211800.GF11810@n2100.arm.linux.org.uk>
 <20120105113106.GR11810@n2100.arm.linux.org.uk>
 <20120330131320.GH3254@S2101-09.ap.freescale.net>
 <20120330131509.GE22981@n2100.arm.linux.org.uk>
 <20120330132256.GI3254@S2101-09.ap.freescale.net>
Message-ID: <20120330132840.GG22981@n2100.arm.linux.org.uk>

On Fri, Mar 30, 2012 at 09:22:59PM +0800, Shawn Guo wrote:
> I have seen it's on the linux-next at the early time of the cycle,
> but I have to admit that I have not done that at the later time.

Well, I did lose track of which branches I had in linux-next during this
last cycle, which is probably how it got dropped.

The last update gave this against mainline:

 arch/arm/tools/mach-types |  186 ++++++++++++++++++++++++--------------------
 1 files changed, 101 insertions(+), 85 deletions(-)

and the latest update gives this also against mainline:

 arch/arm/tools/mach-types |  416 ++++++++++++++++++++++++---------------------
 1 files changed, 219 insertions(+), 197 deletions(-)

so that's 196 platform IDs deleted, which is way too much to be 'safe'.


From paul.liu at linaro.org  Fri Mar 30 09:46:53 2012
From: paul.liu at linaro.org (Ying-Chun Liu (PaulLiu))
Date: Fri, 30 Mar 2012 21:46:53 +0800
Subject: [PATCH v2] ARM: dts: imx6q: add anatop regulators
Message-ID: <1333115213-28922-1-git-send-email-paul.liu@linaro.org>

From: "Ying-Chun Liu (PaulLiu)" <paul.liu at linaro.org>

Add anatop regulators to imx6q.dtsi for all imx6q platforms.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu at linaro.org>
Signed-off-by: Richard Zhao <richard.zhao at linaro.org>
Cc: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/boot/dts/imx6q.dtsi |   86 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 86 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 263e8f3..79f59e7 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -346,6 +346,92 @@
 				compatible = "fsl,imx6q-anatop";
 				reg = <0x020c8000 0x1000>;
 				interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				regulator-1p1 at 110 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd1p1";
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1375000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x110>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <4>;
+					anatop-min-voltage = <800000>;
+					anatop-max-voltage = <1375000>;
+				};
+
+				regulator-3p0 at 120 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd3p0";
+					regulator-min-microvolt = <2800000>;
+					regulator-max-microvolt = <3150000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x120>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <0>;
+					anatop-min-voltage = <2625000>;
+					anatop-max-voltage = <3400000>;
+				};
+
+				regulator-2p5 at 130 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd2p5";
+					regulator-min-microvolt = <2000000>;
+					regulator-max-microvolt = <2750000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x130>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <0>;
+					anatop-min-voltage = <2000000>;
+					anatop-max-voltage = <2750000>;
+				};
+
+				regulator-vddcore at 140 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "cpu";
+					regulator-min-microvolt = <725000>;
+					regulator-max-microvolt = <1450000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x140>;
+					anatop-vol-bit-shift = <0>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <1>;
+					anatop-min-voltage = <725000>;
+					anatop-max-voltage = <1450000>;
+				};
+
+				regulator-vddpu at 140 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vddpu";
+					regulator-min-microvolt = <725000>;
+					regulator-max-microvolt = <1450000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x140>;
+					anatop-vol-bit-shift = <9>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <1>;
+					anatop-min-voltage = <725000>;
+					anatop-max-voltage = <1450000>;
+				};
+
+				regulator-vddsoc at 140 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vddsoc";
+					regulator-min-microvolt = <725000>;
+					regulator-max-microvolt = <1450000>;
+					regulator-always-on;
+					anatop-reg-offset = <0x140>;
+					anatop-vol-bit-shift = <18>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <1>;
+					anatop-min-voltage = <725000>;
+					anatop-max-voltage = <1450000>;
+				};
 			};
 
 			usbphy at 020c9000 { /* USBPHY1 */
-- 
1.7.9.1



From shawn.guo at linaro.org  Fri Mar 30 09:55:37 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 30 Mar 2012 21:55:37 +0800
Subject: [PATCH] ARM: amba: adapt to regulator probe deferral change
Message-ID: <1333115737-1654-1-git-send-email-shawn.guo@linaro.org>

The commit 04bf301 (regulator: Support driver probe deferral) changes
regulator_get() and regulator_register() to return -EPROBE_DEFER
instead of -ENODEV.  Adapt amba bus driver to the change, otherwise
amba_probe() will fail on the platforms that do not have "vcore"
regulator device.

It fixes the boot failure on i.mx28 which uses amba-pl011 as serial
console.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/amba/bus.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 01c2cf4..aafee73 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -362,8 +362,8 @@ static int amba_get_enable_vcore(struct amba_device *pcdev)
 	pcdev->vcore = vcore;
 
 	if (IS_ERR(vcore)) {
-		/* It is OK not to supply a vcore regulator */
-		if (PTR_ERR(vcore) == -ENODEV)
+		/* It should not fail in case of -EPROBE_DEFER */
+		if (PTR_ERR(vcore) == -EPROBE_DEFER)
 			return 0;
 		return PTR_ERR(vcore);
 	}
-- 
1.7.5.4



From hvaibhav at ti.com  Fri Mar 30 09:54:12 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 30 Mar 2012 19:24:12 +0530
Subject: [PATCH-V2 0/3] ARM: OMAP: Make OMAP clocksource source selection
 runtime
Message-ID: <1333115655-28530-1-git-send-email-hvaibhav@ti.com>

Current OMAP code supports couple of clocksource options based
on compilation flag (CONFIG_OMAP_32K_TIMER). The 32KHz sync-timer
and a gptimer which can run on 32KHz or system clock (e.g 38.4 MHz)

This patch series cleans up the existing 32k-sync timer implementation
without any major code change, in order to enable runtime selection between
32k sync-timer and gptimer and adds hwmod lookup for omap2+ devices,
if lookup fails then fall back to gp-timer.

With this, we should be able to support multi-omap boot
including devices with/without 32k-sync timer.
For example, AM33xx device doesn't have 32k-sync timer available,
which breaks multi-omap boot.

This patch-series has been boot tested on AM37xEVM platform, it
would be helpful if somebody help me to validate it on OMAP1/2
platforms.

Changes from previous submissions:
==================================

Changes from V1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/081037.html

	- Based on Tony's comment, added pbase & size argument to
	  omap_init_clocksource_32k(), to avoid cpu_is_xxx() check.
	- Added commit description based on discussion on list
	  (Thanks to Santosh here)
	- Reorder patch sequence


Vaibhav Hiremath (3):
  ARM: OMAP2/3: Add idle_st bits for ST_32KSYNC timer to prcm-common
    header
  ARM: OMAP2+: hwmod data: Add 32k-sync timer data to hwmod database
  ARM: OMAP: Make OMAP clocksource source selection runtime

 arch/arm/mach-omap1/timer32k.c             |    6 ++-
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |   53 +++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |   52 +++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   51 ++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    2 +-
 arch/arm/mach-omap2/prcm-common.h          |    4 +
 arch/arm/mach-omap2/timer.c                |   45 ++++++++------
 arch/arm/plat-omap/counter_32k.c           |   86 ++++++++++++----------------
 arch/arm/plat-omap/include/plat/common.h   |    2 +-
 9 files changed, 229 insertions(+), 72 deletions(-)



From hvaibhav at ti.com  Fri Mar 30 09:54:13 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 30 Mar 2012 19:24:13 +0530
Subject: [PATCH-V2 1/3] ARM: OMAP2/3: Add idle_st bits for ST_32KSYNC timer to
 prcm-common header
In-Reply-To: <1333115655-28530-1-git-send-email-hvaibhav@ti.com>
References: <1333115655-28530-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1333115655-28530-2-git-send-email-hvaibhav@ti.com>

Add missing idle_st bit for 32k-sync timer into the prcm-common
header file, required for hwmod data.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Felipe Balbi <balbi at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Paul Walmsley <paul at pwsan.com>
CC: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Ming Lei <tom.leiming at gmail.com>
---
 arch/arm/mach-omap2/prcm-common.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 5aa5435..29955d5 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -177,6 +177,8 @@
 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
 #define OMAP24XX_ST_GPIOS_SHIFT				2
 #define OMAP24XX_ST_GPIOS_MASK				(1 << 2)
+#define OMAP24XX_ST_32KSYNC_SHIFT			1
+#define OMAP24XX_ST_32KSYNC_MASK			(1 << 1)
 #define OMAP24XX_ST_GPT1_SHIFT				0
 #define OMAP24XX_ST_GPT1_MASK				(1 << 0)

@@ -307,6 +309,8 @@
 #define OMAP3430_ST_SR1_MASK				(1 << 6)
 #define OMAP3430_ST_GPIO1_SHIFT				3
 #define OMAP3430_ST_GPIO1_MASK				(1 << 3)
+#define OMAP3430_ST_32KSYNC_SHIFT			2
+#define OMAP3430_ST_32KSYNC_MASK			(1 << 2)
 #define OMAP3430_ST_GPT12_SHIFT				1
 #define OMAP3430_ST_GPT12_MASK				(1 << 1)
 #define OMAP3430_ST_GPT1_SHIFT				0
--
1.7.0.4



From hvaibhav at ti.com  Fri Mar 30 09:54:14 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 30 Mar 2012 19:24:14 +0530
Subject: [PATCH-V2 2/3] ARM: OMAP2+: hwmod data: Add 32k-sync timer data to
 hwmod database
In-Reply-To: <1333115655-28530-1-git-send-email-hvaibhav@ti.com>
References: <1333115655-28530-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1333115655-28530-3-git-send-email-hvaibhav@ti.com>

Add 32k-sync timer hwmod data to omap2 & 3 hwmod table
and also enable existing hwmod data for omap4 (was disabled before).

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Paul Walmsley <paul at pwsan.com>
CC: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Ming Lei <tom.leiming at gmail.com>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |   53 ++++++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |   52 +++++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |   51 ++++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |    2 +-
 4 files changed, 157 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a5409ce..2091a5c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -54,6 +54,7 @@ static struct omap_hwmod omap2420_gpio4_hwmod;
 static struct omap_hwmod omap2420_dma_system_hwmod;
 static struct omap_hwmod omap2420_mcspi1_hwmod;
 static struct omap_hwmod omap2420_mcspi2_hwmod;
+static struct omap_hwmod omap2420_counter_32k_hwmod;

 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@@ -1513,6 +1514,55 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
 	.slaves_cnt	= ARRAY_SIZE(omap2420_mcbsp2_slaves),
 };

+/*
+ * '32K sync counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+static struct omap_hwmod_class omap2420_counter_hwmod_class = {
+	.name = "counter",
+};
+
+/* counter_32k */
+static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
+	{
+		.pa_start	= 0x48004000,
+		.pa_end		= 0x48004000 + SZ_4K,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
+	.master		= &omap2420_l4_wkup_hwmod,
+	.slave		= &omap2420_counter_32k_hwmod,
+	.clk		= "l4_ck",
+	.addr		= omap2420_counter_32k_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* counter_32k slave ports */
+static struct omap_hwmod_ocp_if *omap2420_counter_32k_slaves[] = {
+	&omap2420_l4_wkup__counter_32k,
+};
+
+static struct omap_hwmod omap2420_counter_32k_hwmod = {
+	.name		= "counter_32k",
+	.class		= &omap2420_counter_hwmod_class,
+	.main_clk	= "sync_32k_ick",
+	.prcm = {
+		.omap2	= {
+			.module_offs		= WKUP_MOD,
+			.prcm_reg_id		= 1,
+			.module_bit		= OMAP24XX_ST_32KSYNC_SHIFT,
+			.idlest_reg_id		= 1,
+			.idlest_idle_bit	= OMAP24XX_ST_32KSYNC_SHIFT,
+		},
+	},
+	.slaves		= omap2420_counter_32k_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2420_counter_32k_slaves),
+};
+
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
 	&omap2420_l3_main_hwmod,
 	&omap2420_l4_core_hwmod,
@@ -1565,6 +1615,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
 	/* mcspi class */
 	&omap2420_mcspi1_hwmod,
 	&omap2420_mcspi2_hwmod,
+
+	/* 32k sync timer */
+	&omap2420_counter_32k_hwmod,
 	NULL,
 };

diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c4f56cb..f7cc4bb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -64,6 +64,7 @@ static struct omap_hwmod omap2430_mcspi2_hwmod;
 static struct omap_hwmod omap2430_mcspi3_hwmod;
 static struct omap_hwmod omap2430_mmc1_hwmod;
 static struct omap_hwmod omap2430_mmc2_hwmod;
+static struct omap_hwmod omap2430_counter_32k_hwmod;

 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -2001,6 +2002,55 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
 	.class		= &omap2430_mmc_class,
 };

+/*
+ * '32K sync counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+static struct omap_hwmod_class omap2430_counter_hwmod_class = {
+	.name = "counter",
+};
+
+/* counter_32k */
+static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
+	{
+		.pa_start	= 0x49020000,
+		.pa_end		= 0x49020000 + SZ_4K,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
+	.master		= &omap2430_l4_wkup_hwmod,
+	.slave		= &omap2430_counter_32k_hwmod,
+	.clk		= "l4_ck",
+	.addr		= omap2430_counter_32k_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* counter_32k slave ports */
+static struct omap_hwmod_ocp_if *omap2430_counter_32k_slaves[] = {
+	&omap2430_l4_wkup__counter_32k,
+};
+
+static struct omap_hwmod omap2430_counter_32k_hwmod = {
+	.name		= "counter_32k",
+	.class		= &omap2430_counter_hwmod_class,
+	.main_clk	= "sync_32k_ick",
+	.prcm		= {
+		.omap2	= {
+			.module_offs		= WKUP_MOD,
+			.prcm_reg_id		= 1,
+			.module_bit		= OMAP24XX_ST_32KSYNC_SHIFT,
+			.idlest_reg_id		= 1,
+			.idlest_idle_bit	= OMAP24XX_ST_32KSYNC_SHIFT,
+		},
+	},
+	.slaves		= omap2430_counter_32k_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2430_counter_32k_slaves),
+};
+
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
 	&omap2430_l3_main_hwmod,
 	&omap2430_l4_core_hwmod,
@@ -2064,6 +2114,8 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
 	/* usbotg class*/
 	&omap2430_usbhsotg_hwmod,

+	/* 32k sync timer */
+	&omap2430_counter_32k_hwmod,
 	NULL,
 };

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3c8dd92..54738b0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -86,6 +86,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
+static struct omap_hwmod omap3xxx_counter_32k_hwmod;

 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -3520,6 +3521,55 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
 	.slaves_cnt	= ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
 };

+/*
+ * '32K sync counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
+	.name = "counter",
+};
+
+/* counter_32k */
+static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
+	{
+		.pa_start	= 0x48320000,
+		.pa_end		= 0x48320000 + SZ_4K,
+		.flags		= ADDR_TYPE_RT
+	},
+	{ }
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
+	.master		= &omap3xxx_l4_wkup_hwmod,
+	.slave		= &omap3xxx_counter_32k_hwmod,
+	.clk		= "wkup_l4_ick",
+	.addr		= omap3xxx_counter_32k_addrs,
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* counter_32k slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_counter_32k_slaves[] = {
+	&omap3xxx_l4_wkup__counter_32k,
+};
+
+static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
+	.name		= "counter_32k",
+	.class		= &omap3xxx_counter_hwmod_class,
+	.main_clk	= "omap_32ksync_ick",
+	.prcm		= {
+		.omap2	= {
+			.module_offs		= WKUP_MOD,
+			.prcm_reg_id		= 1,
+			.module_bit		= OMAP3430_ST_32KSYNC_SHIFT,
+			.idlest_reg_id		= 1,
+			.idlest_idle_bit	= OMAP3430_ST_32KSYNC_SHIFT,
+		},
+	},
+	.slaves		= omap3xxx_counter_32k_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap3xxx_counter_32k_slaves),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 	&omap3xxx_l3_main_hwmod,
 	&omap3xxx_l4_core_hwmod,
@@ -3577,6 +3627,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 	&omap34xx_mcspi3,
 	&omap34xx_mcspi4,

+	&omap3xxx_counter_32k_hwmod,
 	NULL,
 };

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ef0524c..090bd59 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -5512,7 +5512,7 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 	&omap44xx_bandgap_hwmod,

 	/* counter class */
-/*	&omap44xx_counter_32k_hwmod, */
+	&omap44xx_counter_32k_hwmod,

 	/* dma class */
 	&omap44xx_dma_system_hwmod,
--
1.7.0.4



From hvaibhav at ti.com  Fri Mar 30 09:54:15 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 30 Mar 2012 19:24:15 +0530
Subject: [PATCH-V2 3/3] ARM: OMAP: Make OMAP clocksource source selection
 runtime
In-Reply-To: <1333115655-28530-1-git-send-email-hvaibhav@ti.com>
References: <1333115655-28530-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1333115655-28530-4-git-send-email-hvaibhav@ti.com>

Current OMAP code supports couple of clocksource options based
on compilation flag (CONFIG_OMAP_32K_TIMER). The 32KHz sync-timer
and a gptimer which can run on 32KHz or system clock (e.g 38.4 MHz).
So there can be 3 options -

1. 32KHz sync-timer
2. Sys_clock based (e.g 13/19.2/26/38.4 MHz) gptimer
3. 32KHz based gptimer.

The optional gptimer based clocksource was added so that it can
give the high precision than sync-timer, so expected usage was 2
and not 3.
Unfortunately option 2, clocksource doesn't meet the requirement of
free-running clock as per clocksource need. It stops in low power states
when sys_clock is cut. That makes gptimer based clocksource option
useless for OMAP2/3/4 devices with sys_clock as a clock input.
Option 3 will still work but it is no better than 32K sync-timer
based clocksource.

So ideally we can kill the gptimer based clocksource option but there
are some OMAP based derivative SoCs like AM33XX which doesn't have
32K sync-timer hardware IP and need to fallback on 32KHz based gptimer
clocksource.
Considering above, make sync-timer and gptimer clocksource runtime
selectable so that both OMAP and AMXXXX continue to use the same code.

Use hwmod database lookup mechanism, through which at run-time
we can identify availability of 32k-sync timer on the device,
else fall back to gptimer.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Signed-off-by: Felipe Balbi <balbi at ti.com>
CC: Santosh Shilimkar <santosh.shilimkar at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Tarun Kanti DebBarma <tarun.kanti at ti.com>
Cc: Ming Lei <tom.leiming at gmail.com>
---
 arch/arm/mach-omap1/timer32k.c           |    6 ++-
 arch/arm/mach-omap2/timer.c              |   45 +++++++++-------
 arch/arm/plat-omap/counter_32k.c         |   86 ++++++++++++-----------------
 arch/arm/plat-omap/include/plat/common.h |    2 +-
 4 files changed, 68 insertions(+), 71 deletions(-)

diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index a2e6d07..3f96a00 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -72,6 +72,7 @@

 /* 16xx specific defines */
 #define OMAP1_32K_TIMER_BASE		0xfffb9000
+#define OMAP1_32KSYNC_TIMER_BASE	0xfffbc410
 #define OMAP1_32K_TIMER_CR		0x08
 #define OMAP1_32K_TIMER_TVR		0x00
 #define OMAP1_32K_TIMER_TCR		0x04
@@ -185,7 +186,10 @@ static __init void omap_init_32k_timer(void)
  */
 bool __init omap_32k_timer_init(void)
 {
-	omap_init_clocksource_32k();
+	u32 pbase;
+
+	pbase = cpu_is_omap16xx() ? OMAP1_32KSYNC_TIMER_BASE : NULL;
+	omap_init_clocksource_32k(pbase, SZ_1K);
 	omap_init_32k_timer();

 	return true;
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5c9acea..f35db1a 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -234,21 +234,6 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
 }

 /* Clocksource code */
-
-#ifdef CONFIG_OMAP_32K_TIMER
-/*
- * When 32k-timer is enabled, don't use GPTimer for clocksource
- * instead, just leave default clocksource which uses the 32k
- * sync counter.  See clocksource setup in plat-omap/counter_32k.c
- */
-
-static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
-{
-	omap_init_clocksource_32k();
-}
-
-#else
-
 static struct omap_dm_timer clksrc;

 /*
@@ -280,13 +265,33 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
 						const char *fck_source)
 {
 	int res;
+	struct omap_hwmod *oh;
+	const char *oh_name = "counter_32k";
+
+	/*
+	 * First check for availability for 32k-sync timer.
+	 *
+	 * In case of failure in finding 32k_counter module or
+	 * registering it as clocksource, execution will fallback to
+	 * gp-timer.
+	 */
+	oh = omap_hwmod_lookup(oh_name);
+	if (oh && oh->slaves_cnt != 0) {
+		u32 pbase;
+		unsigned long size;
+
+		pbase = oh->slaves[0]->addr->pa_start + 0x10;
+		size = oh->slaves[0]->addr->pa_end -
+			oh->slaves[0]->addr->pa_start;
+		res = omap_init_clocksource_32k(pbase, size);
+		if (!res)
+			return;
+	}

+	/* Fall back to gp-timer code */
 	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
 	BUG_ON(res);

-	pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
-		gptimer_id, clksrc.rate);
-
 	__omap_dm_timer_load_start(&clksrc,
 			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
 	setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
@@ -294,8 +299,10 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
 	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 		pr_err("Could not register clocksource %s\n",
 			clocksource_gpt.name);
+	else
+		pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
+			gptimer_id, clksrc.rate);
 }
-#endif

 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
 				clksrc_nr, clksrc_src)			\
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 5068fe5..c1af18c 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -35,8 +35,6 @@
  */
 static void __iomem *timer_32k_base;

-#define OMAP16XX_TIMER_32K_SYNCHRONIZED		0xfffbc410
-
 static u32 notrace omap_32k_read_sched_clock(void)
 {
 	return timer_32k_base ? __raw_readl(timer_32k_base) : 0;
@@ -68,54 +66,42 @@ void read_persistent_clock(struct timespec *ts)
 	*ts = *tsp;
 }

-int __init omap_init_clocksource_32k(void)
+int __init omap_init_clocksource_32k(u32 pbase, unsigned long size)
 {
-	static char err[] __initdata = KERN_ERR
-			"%s: can't register clocksource!\n";
-
-	if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
-		u32 pbase;
-		unsigned long size = SZ_4K;
-		void __iomem *base;
-		struct clk *sync_32k_ick;
-
-		if (cpu_is_omap16xx()) {
-			pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
-			size = SZ_1K;
-		} else if (cpu_is_omap2420())
-			pbase = OMAP2420_32KSYNCT_BASE + 0x10;
-		else if (cpu_is_omap2430())
-			pbase = OMAP2430_32KSYNCT_BASE + 0x10;
-		else if (cpu_is_omap34xx())
-			pbase = OMAP3430_32KSYNCT_BASE + 0x10;
-		else if (cpu_is_omap44xx())
-			pbase = OMAP4430_32KSYNCT_BASE + 0x10;
-		else
-			return -ENODEV;
-
-		/* For this to work we must have a static mapping in io.c for this area */
-		base = ioremap(pbase, size);
-		if (!base)
-			return -ENODEV;
-
-		sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
-		if (!IS_ERR(sync_32k_ick))
-			clk_enable(sync_32k_ick);
-
-		timer_32k_base = base;
-
-		/*
-		 * 120000 rough estimate from the calculations in
-		 * __clocksource_updatefreq_scale.
-		 */
-		clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
-				32768, NSEC_PER_SEC, 120000);
-
-		if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
-					  clocksource_mmio_readl_up))
-			printk(err, "32k_counter");
-
-		setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
-	}
+	void __iomem *base;
+	struct clk *sync_32k_ick;
+
+	if (!pbase || !size)
+		return -ENODEV;
+	/*
+	 * For this to work we must have a static mapping in io.c
+	 * for this area
+	 */
+	base = ioremap(pbase, size);
+	if (!base)
+		return -ENODEV;
+
+	sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
+	if (!IS_ERR(sync_32k_ick))
+		clk_enable(sync_32k_ick);
+
+	timer_32k_base = base;
+
+	/*
+	 * 120000 rough estimate from the calculations in
+	 * __clocksource_updatefreq_scale.
+	 */
+	clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
+			32768, NSEC_PER_SEC, 120000);
+
+	if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
+				clocksource_mmio_readl_up))
+		pr_err("32k_counter: can't register clocksource!\n");
+
+	else
+		pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
+
+	setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
+
 	return 0;
 }
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index b4d7ec3..6cc1e43 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -30,7 +30,7 @@
 #include <plat/i2c.h>
 #include <plat/omap_hwmod.h>

-extern int __init omap_init_clocksource_32k(void);
+extern int __init omap_init_clocksource_32k(u32 pbase, unsigned long size);

 extern void omap_reserve(void);
 extern int omap_dss_reset(struct omap_hwmod *);
--
1.7.0.4



From festevam at gmail.com  Fri Mar 30 10:23:13 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 30 Mar 2012 11:23:13 -0300
Subject: [PATCH] ARM: amba: adapt to regulator probe deferral change
In-Reply-To: <1333115737-1654-1-git-send-email-shawn.guo@linaro.org>
References: <1333115737-1654-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAOMZO5ATwkFOc=B55atMgugx7uiwVe1MyTHS2ynSX7dF5N+S3A@mail.gmail.com>

On Fri, Mar 30, 2012 at 10:55 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> The commit 04bf301 (regulator: Support driver probe deferral) changes
> regulator_get() and regulator_register() to return -EPROBE_DEFER
> instead of -ENODEV. ?Adapt amba bus driver to the change, otherwise
> amba_probe() will fail on the platforms that do not have "vcore"
> regulator device.
>
> It fixes the boot failure on i.mx28 which uses amba-pl011 as serial
> console.

Tested this patch in linux-next-20120330 and my mx28evk still does not boot.

Any other patch is needed?


From khilman at ti.com  Fri Mar 30 10:24:18 2012
From: khilman at ti.com (Kevin Hilman)
Date: Fri, 30 Mar 2012 07:24:18 -0700
Subject: [PATCH] cpufreq: OMAP: fix build errors: depends on ARCH_OMAP2PLUS
In-Reply-To: <20120330131200.GA23442@n2100.arm.linux.org.uk> (Russell King's
 message of "Fri, 30 Mar 2012 14:12:00 +0100")
References: <1332807568-638-1-git-send-email-khilman@ti.com>
 <20120330131200.GA23442@n2100.arm.linux.org.uk>
Message-ID: <87limif9pp.fsf@ti.com>

Russell King - ARM Linux <linux at arm.linux.org.uk> writes:

> On Mon, Mar 26, 2012 at 05:19:28PM -0700, Kevin Hilman wrote:
>> The OMAP driver needs a 'depends on ARCH_OMAP2PLUS' since it only
>> builds for OMAP2+ platforms.
>> 
>> This 'depends on' was in the original patch from Russell King, but was
>> erroneously removed by me when making this option user-selectable in
>> commit b09db45c (cpufreq: OMAP driver depends CPUfreq tables.)  This
>> patch remedies that.
>> 
>> Apologies to Russell King for breaking his originally working patch.
>> 
>> Also, thanks to Grazvydas Ignotas for reporting the same problem.
>> 
>> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
>> Cc: Grazvydas Ignotas <notasas at gmail.com>
>> Signed-off-by: Kevin Hilman <khilman at ti.com>
>> ---
>> Dave, this applies on top of your current fixes branch, and fixes a 
>> problem introduced there by me.  Please merge for v3.4-rc.  Thanks.
>
> Can you please check that you've picked up everything that's necessary,
> as I'm still seeing the below as outstanding from my original patch.

Yes, all the code you touch below is now removed, and queued by Paul,
but unfortunately, that branch didn't make it in time for v3.4. :(

Paul, maybe you can pull out my "cleanup cpufreq leftovers" patch and
submit for v3.4-rc?

Thanks,

Kevin

>
> commit e55a42528cebb8fa7408dc95abb3859639a46750
> Author: Russell King <rmk+kernel at arm.linux.org.uk>
> Date:   Wed Feb 15 11:20:51 2012 +0000
>
>     ARM: OMAP: fix cpufreq build
>     
>     OMAPs cpufreq requires the frequency table support, but nothing ensures
>     that this is selected.  This can result in configurations which fail to
>     build:
>     
>     drivers/built-in.o:(.data+0x5238): undefined reference to `cpufreq_freq_attr_scaling_available_freqs'
>     drivers/cpufreq/omap-cpufreq.c:88: undefined reference to `cpufreq_frequency_table_target'
>     drivers/cpufreq/omap-cpufreq.c:60: undefined reference to `cpufreq_frequency_table_verify'
>     drivers/cpufreq/omap-cpufreq.c:186: undefined reference to `cpufreq_frequency_table_cpuinfo'
>     drivers/cpufreq/omap-cpufreq.c:190: undefined reference to `cpufreq_frequency_table_get_attr'
>     
>     Fix this by introducing a new configuration variable and having that
>     select CPU_FREQ_TABLE.
>     
>     Signed-off-by: Russell King <rmk+kernel at arm.linux.org.uk>
>
> diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> index 7072e0d..ad35d4e 100644
> --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
> @@ -166,7 +166,7 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
>  	return 0;
>  }
>  
> -#ifdef CONFIG_CPU_FREQ
> +#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
>  /*
>   * Walk PRCM rate table and fillout cpufreq freq_table
>   * XXX This should be replaced by an OPP layer in the near future
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index f57ed5b..450feb0 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -536,7 +536,7 @@ struct clk_functions omap2_clk_functions = {
>  	.clk_set_rate		= omap2_clk_set_rate,
>  	.clk_set_parent		= omap2_clk_set_parent,
>  	.clk_disable_unused	= omap2_clk_disable_unused,
> -#ifdef CONFIG_CPU_FREQ
> +#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
>  	/* These will be removed when the OPP code is integrated */
>  	.clk_init_cpufreq_table	= omap2_clk_init_cpufreq_table,
>  	.clk_exit_cpufreq_table	= omap2_clk_exit_cpufreq_table,
> diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
> index b8c2a68..f331cfc 100644
> --- a/arch/arm/mach-omap2/clock.h
> +++ b/arch/arm/mach-omap2/clock.h
> @@ -146,7 +146,7 @@ extern const struct clksel_rate gpt_sys_rates[];
>  extern const struct clksel_rate gfx_l3_rates[];
>  extern const struct clksel_rate dsp_ick_rates[];
>  
> -#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
> +#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_ARM_OMAP2PLUS_CPUFREQ)
>  extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
>  extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
>  #else
> diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
> index 56b6f8b..618cf80 100644
> --- a/arch/arm/plat-omap/clock.c
> +++ b/arch/arm/plat-omap/clock.c
> @@ -398,7 +398,7 @@ struct clk dummy_ck = {
>  	.ops	= &clkops_null,
>  };
>  
> -#ifdef CONFIG_CPU_FREQ
> +#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
>  void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
>  {
>  	unsigned long flags;
> diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
> index 240a7b9..879ba27 100644
> --- a/arch/arm/plat-omap/include/plat/clock.h
> +++ b/arch/arm/plat-omap/include/plat/clock.h
> @@ -283,7 +283,7 @@ struct clk_functions {
>  	void		(*clk_allow_idle)(struct clk *clk);
>  	void		(*clk_deny_idle)(struct clk *clk);
>  	void		(*clk_disable_unused)(struct clk *clk);
> -#ifdef CONFIG_CPU_FREQ
> +#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
>  	void		(*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
>  	void		(*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
>  #endif
> @@ -301,7 +301,7 @@ extern void recalculate_root_clocks(void);
>  extern unsigned long followparent_recalc(struct clk *clk);
>  extern void clk_enable_init_clocks(void);
>  unsigned long omap_fixed_divisor_recalc(struct clk *clk);
> -#ifdef CONFIG_CPU_FREQ
> +#ifdef CONFIG_ARM_OMAP2PLUS_CPUFREQ
>  extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
>  extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
>  #endif
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index 32d790d..587b578 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -3,8 +3,8 @@
>  #
>  
>  config ARM_OMAP2PLUS_CPUFREQ
> -	bool "TI OMAP2+"
> -	default ARCH_OMAP2PLUS
> +	def_bool y
> +	depends on ARCH_OMAP2PLUS
>  	select CPU_FREQ_TABLE
>  
>  config ARM_S3C2416_CPUFREQ
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From lost.distance at yahoo.com  Fri Mar 30 10:30:33 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 30 Mar 2012 15:30:33 +0100 (BST)
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <CAN1soZwgUooLEcDimUxyLO20x0__pAa+J3wRrH3zoW3pJsR2bg@mail.gmail.com>
Message-ID: <1333117833.65604.YahooMailClassic@web29013.mail.ird.yahoo.com>

--- On Fri, 30/3/12, Haojian Zhuang <haojian.zhuang at gmail.com> wrote:
> On Fri, Mar 30, 2012 at 6:41 PM, Paul
> Parsons <lost.distance at yahoo.com>
> wrote:
> > --- On Fri, 30/3/12, Haojian Zhuang <haojian.zhuang at gmail.com>
> wrote:
> >> On Thu, Mar 29, 2012 at 2:12 AM, Paul
> >> Parsons <lost.distance at yahoo.com>
> >> wrote:
> >> > On PXA2xx platforms, the MFP API (described
> in
> >> Documentation/arm/pxa/mfp.txt)
> >> > provides values for the following:
> >> >
> >> > 1. GPIO inputs (e.g. GPIO105_GPIO).
> >> > 2. Alternate function inputs (e.g.
> GPIO105_CIF_DD_1).
> >> > 3. Alternate function outputs (e.g.
> >> GPIO105_KP_MKOUT_2).
> >> >
> >> > It does not provide values for GPIO outputs
> (i.e. AF0
> >> outputs).
> >> >
> >> > One cannot use the macro used by the MFP API
> internally
> >> - MFP_CFG_OUT() - to
> >> > define new GPIO output values, since that
> macro is
> >> forbidden in platform code.
> >> >
> >> > Without the ability to add GPIO outputs to the
> MFP
> >> configuration, it is not
> >> > possible to drive GPIO outputs high during
> sleep mode.
> >> >
> >> > This would be useful, for example, on the
> hx4700
> >> platform, where driving the
> >> > infrared powerdown GPIO 105 high during sleep
> mode
> >> would save some mA.
> >> >
> >> > So my question is: what method should one use
> to add
> >> GPIO outputs to the MFP
> >> > configuration?
> >> >
> >> > One possible method, namely manually defining
> values in
> >> the platform code:
> >> >
> >> > ? ? ? ?MFP_PIN_GPIO105 | MFP_AF0 |
> MFP_DIR_OUT |
> >> MFP_LPM_DRIVE_HIGH,
> >> >
> >> > is essentially no different from using the
> forbidden
> >> MFP_CFG_OUT() macro.
> >> >
> >>
> >> Does MFP_CFG_OUT() help you? This macro is defined
> in
> >> mfp-pxa2xx.h.
> >
> > Yes, MFP_CFG_OUT() does help. But it has been pointed
> out that
> > MFP_CFG_OUT() is not allowed to be used in board
> support code:
> >
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086456.html
> >
> > Is that no longer true?
> 
> I'm sorry that I messed it. Since GPIOxx_GPIO is always
> defined as MFP_CFG_IN().
> It seems that you're blocked to specify MFP_CFG_OUT().
> 
> Actually it's not a problem. While you're using it as
> output, you must
> assign special
> usage for this pin, like some peripheral rest signal. So I
> think that
> you can define new
> macro GPIOxx_yy() in mfp-pxa27x.h, like GPIO9_HZ_CLK(). Is
> it meaningful?

The GPIO output value I wish to add is specific to the hx4700 platform;
it is not defined in any PXA27x documentation.

Is it acceptable to add such platform-specific values to the generic
mfp-pxa27x.h file?

Regards,
Paul


From olof at lixom.net  Fri Mar 30 10:38:01 2012
From: olof at lixom.net (Olof Johansson)
Date: Fri, 30 Mar 2012 07:38:01 -0700
Subject: [PATCH 1/2] ARM: fix builds due to missing <asm/system_misc.h>
 includes
Message-ID: <1333118281-25295-1-git-send-email-olof@lixom.net>

This does a sweeping change fixing up all the missing system_misc.h and
system_info.h includes from the system.h split-up change. These were the
ones I came across when building all defconfigs in arch/arm/configs, there
might be more but they lack adequate build coverage to be easily caught.

I'm expecting to get a lot of these piecemeal by each maintainer, so we
might just as well do one sweeping change to get them all at once.


Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Sascha Hauer <kernel at pengutronix.de>
Cc: Imre Kaloz <kaloz at openwrt.org>
Cc: Krzysztof Halasa <khc at pm.waw.pl>
Cc: Eric Miao <eric.y.miao at gmail.com>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: Wan ZongShun <mcuos.com at gmail.com>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-at91/at91x40.c  |    1 +
 arch/arm/mach-at91/setup.c    |    1 +
 arch/arm/mach-h720x/common.c  |    1 +
 arch/arm/mach-imx/mm-imx3.c   |    1 +
 arch/arm/mach-imx/mm-imx5.c   |    1 +
 arch/arm/mach-ixp23xx/core.c  |    1 +
 arch/arm/mach-ixp4xx/common.c |    1 +
 arch/arm/mach-pxa/raumfeld.c  |    2 ++
 arch/arm/mach-shark/core.c    |    1 +
 arch/arm/mach-w90x900/dev.c   |    1 +
 arch/arm/plat-s3c24xx/cpu.c   |    1 +
 11 files changed, 12 insertions(+)

diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 5400a1d..d62fe09 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <asm/proc-fns.h>
+#include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <mach/at91x40.h>
 #include <mach/at91_st.h>
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 1083739..97cc04d 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -11,6 +11,7 @@
 #include <linux/pm.h>
 #include <linux/of_address.h>
 
+#include <asm/system_misc.h>
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index e756d1a..aa1331e 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -24,6 +24,7 @@
 #include <asm/dma.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/system_misc.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index d534d7f..7412738 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -21,6 +21,7 @@
 #include <linux/err.h>
 
 #include <asm/pgtable.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 51af9fa..05250ae 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 
+#include <asm/system_misc.h>
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index d2c2dc3..d345424 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -36,6 +36,7 @@
 #include <asm/irq.h>
 #include <asm/tlbflush.h>
 #include <asm/pgtable.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index c60e7b8..ebbd7fc 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -37,6 +37,7 @@
 #include <asm/page.h>
 #include <asm/irq.h>
 #include <asm/sched_clock.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 7d691e5..5905ed1 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -43,6 +43,8 @@
 #include <linux/regulator/consumer.h>
 #include <linux/delay.h>
 
+#include <asm/system_info.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 6a2a7f2..2704bcd 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -15,6 +15,7 @@
 #include <asm/mach-types.h>
 #include <asm/leds.h>
 #include <asm/param.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index db82568..48f5b9f 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -27,6 +27,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 
+#include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 0db73ae..290942d 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -36,6 +36,7 @@
 #include <asm/irq.h>
 #include <asm/cacheflush.h>
 #include <asm/system_info.h>
+#include <asm/system_misc.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-- 
1.7.9.2.359.gebfc2



From olof at lixom.net  Fri Mar 30 10:38:46 2012
From: olof at lixom.net (Olof Johansson)
Date: Fri, 30 Mar 2012 07:38:46 -0700
Subject: [PATCH 2/2] ARM: clps711x: fix missing include file
Message-ID: <1333118326-25438-1-git-send-email-olof@lixom.net>

linux/bug.h is needed due to an ARRAY_SIZE being used:

arch/arm/mach-clps711x/edb7211-mm.c: In function 'edb7211_map_io':
arch/arm/mach-clps711x/edb7211-mm.c:79:9: error: implicit declaration of function 'BUILD_BUG_ON_ZERO'

Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-clps711x/edb7211-mm.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-clps711x/edb7211-mm.c b/arch/arm/mach-clps711x/edb7211-mm.c
index 0bea145..4372f06 100644
--- a/arch/arm/mach-clps711x/edb7211-mm.c
+++ b/arch/arm/mach-clps711x/edb7211-mm.c
@@ -21,6 +21,7 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/bug.h>
 
 #include <mach/hardware.h>
 #include <asm/page.h>
-- 
1.7.9.2.359.gebfc2



From haojian.zhuang at gmail.com  Fri Mar 30 10:50:42 2012
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 30 Mar 2012 22:50:42 +0800
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <1333117833.65604.YahooMailClassic@web29013.mail.ird.yahoo.com>
References: <CAN1soZwgUooLEcDimUxyLO20x0__pAa+J3wRrH3zoW3pJsR2bg@mail.gmail.com>
 <1333117833.65604.YahooMailClassic@web29013.mail.ird.yahoo.com>
Message-ID: <CAN1soZwSOiKZQdRrykoP6oSPr-00svu+qKy4X61tCTSqQRv76w@mail.gmail.com>

>
> The GPIO output value I wish to add is specific to the hx4700 platform;
> it is not defined in any PXA27x documentation.
>
> Is it acceptable to add such platform-specific values to the generic
> mfp-pxa27x.h file?
>
Unless we append a new macro to resolve this issue. But I don't want to
put too much effort on MFP code. I'm planning to migrate to pinmux driver
since it could integrate with gpio and suspend code better.

Actually I appended pinmux driver for pxa3xx/mmp. They could be found
in linux-next tree. For next stage, I'll add support for DT and suspend.
If you like, you can also add pxa2xx support.

So I prefer you change mfp-pxa27x.h directly.

Best Regards
Haojian


From grinberg at compulab.co.il  Fri Mar 30 10:59:50 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Fri, 30 Mar 2012 17:59:50 +0300
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <1332958336.11131.YahooMailClassic@web29001.mail.ird.yahoo.com>
References: <1332958336.11131.YahooMailClassic@web29001.mail.ird.yahoo.com>
Message-ID: <4F75CA66.606@compulab.co.il>

On 03/28/12 20:12, Paul Parsons wrote:
> On PXA2xx platforms, the MFP API (described in Documentation/arm/pxa/mfp.txt)
> provides values for the following:
> 
> 1. GPIO inputs (e.g. GPIO105_GPIO).
> 2. Alternate function inputs (e.g. GPIO105_CIF_DD_1).
> 3. Alternate function outputs (e.g. GPIO105_KP_MKOUT_2).
> 
> It does not provide values for GPIO outputs (i.e. AF0 outputs).
> 
> One cannot use the macro used by the MFP API internally - MFP_CFG_OUT() - to
> define new GPIO output values, since that macro is forbidden in platform code.
> 
> Without the ability to add GPIO outputs to the MFP configuration, it is not
> possible to drive GPIO outputs high during sleep mode.
> 
> This would be useful, for example, on the hx4700 platform, where driving the
> infrared powerdown GPIO 105 high during sleep mode would save some mA.
> 
> So my question is: what method should one use to add GPIO outputs to the MFP
> configuration?
> 
> One possible method, namely manually defining values in the platform code:
> 
> 	MFP_PIN_GPIO105 | MFP_AF0 | MFP_DIR_OUT | MFP_LPM_DRIVE_HIGH,

Have you tried:
GPIO105_GPIO | MFP_LPM_DRIVE_HIGH,
?

This way it works on other boards.


-- 
Regards,
Igor.


From lost.distance at yahoo.com  Fri Mar 30 11:06:01 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 30 Mar 2012 16:06:01 +0100 (BST)
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <4F75CA66.606@compulab.co.il>
Message-ID: <1333119961.87678.YahooMailClassic@web29013.mail.ird.yahoo.com>

--- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il> wrote:
> On 03/28/12 20:12, Paul Parsons
> wrote:
> > On PXA2xx platforms, the MFP API (described in
> Documentation/arm/pxa/mfp.txt)
> > provides values for the following:
> > 
> > 1. GPIO inputs (e.g. GPIO105_GPIO).
> > 2. Alternate function inputs (e.g. GPIO105_CIF_DD_1).
> > 3. Alternate function outputs (e.g.
> GPIO105_KP_MKOUT_2).
> > 
> > It does not provide values for GPIO outputs (i.e. AF0
> outputs).
> > 
> > One cannot use the macro used by the MFP API internally
> - MFP_CFG_OUT() - to
> > define new GPIO output values, since that macro is
> forbidden in platform code.
> > 
> > Without the ability to add GPIO outputs to the MFP
> configuration, it is not
> > possible to drive GPIO outputs high during sleep mode.
> > 
> > This would be useful, for example, on the hx4700
> platform, where driving the
> > infrared powerdown GPIO 105 high during sleep mode
> would save some mA.
> > 
> > So my question is: what method should one use to add
> GPIO outputs to the MFP
> > configuration?
> > 
> > One possible method, namely manually defining values in
> the platform code:
> > 
> > ??? MFP_PIN_GPIO105 | MFP_AF0 |
> MFP_DIR_OUT | MFP_LPM_DRIVE_HIGH,
> 
> Have you tried:
> GPIO105_GPIO | MFP_LPM_DRIVE_HIGH,
> ?
> 
> This way it works on other boards.

Hello Igor,

GPIO105_GPIO expands to a GPIO input - MFP_CFG_IN(GPIO105, AF0) -
not an output.

Regards,
Paul



From grinberg at compulab.co.il  Fri Mar 30 11:23:04 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Fri, 30 Mar 2012 18:23:04 +0300
Subject: [PATCH 05/12] Add dummy smsc911x regulators to cm-t35.
In-Reply-To: <20120328170316.GR9859@atomide.com>
References: <1332494504-10251-1-git-send-email-Russ.Dill@ti.com>
 <1332494504-10251-6-git-send-email-Russ.Dill@ti.com>
 <4F71E290.2050403@compulab.co.il> <20120327172819.GQ9859@atomide.com>
 <4F72B0D0.70703@compulab.co.il> <20120328170316.GR9859@atomide.com>
Message-ID: <4F75CFD8.7050809@compulab.co.il>

On 03/28/12 19:03, Tony Lindgren wrote:
> * Igor Grinberg <grinberg at compulab.co.il> [120327 23:36]:
>> Hi Tony,
>>
>> On 03/27/12 19:28, Tony Lindgren wrote:
>>> * Igor Grinberg <grinberg at compulab.co.il> [120327 08:56]:
>>>> Hi Russ,
>>>>
>>>> This patch works, but can we, please use the attached patch instead?
>>>
>>> Hmm what's the difference here? Do you have some real controllable
>>> regulator for one of the smsc911x instances?
>>
>> Well, the difference here is that those regulators will only be present
>> if the smsc911x controllers are present and their initialization is done
>> along with the controllers.
>> Also, I want to separate the cm-t35 from sb-t35 for future easier
>> refactoring of the sb-t35 code so it can be reused also on cm-t3517.
>>
>> Only vddvario for smsc911x.0 is controllable - connected to VIO, but
>> VIO will never be disabled as it also controls many other devices
>> (DRAM is among them), so I prefer it to be dummy and keep it together
>> with vdd33a.
> 
> OK thanks for the clarification. 
> 
>>> Anyways, I take it that you have tested that both smsc911x interfaces
>>> work now?
>>
>> Yes, both regulators are registered and found by the smsc911x driver.
>> There is some kind of problem with the smsc911x.1, but it looks unrelated
>> to the patch:
> 
> OK good to hear. Regarding the following problem..
>  
>> smsc911x: Driver version 2008-10-21
>> irq 323: nobody cared (try booting with the "irqpoll" option)
>> [<c001ae6c>] (unwind_backtrace+0x0/0xfc) from [<c0088960>] (__report_bad_irq+0x28/0xbc)
>> [<c0088960>] (__report_bad_irq+0x28/0xbc) from [<c0088bd4>] (note_interrupt+0x1e0/0x230)
>> [<c0088bd4>] (note_interrupt+0x1e0/0x230) from [<c0086e48>] (handle_irq_event_percpu+0xb0/0x1a0)
>> [<c0086e48>] (handle_irq_event_percpu+0xb0/0x1a0) from [<c0086f74>] (handle_irq_event+0x3c/0x5c)
>> [<c0086f74>] (handle_irq_event+0x3c/0x5c) from [<c00895a0>] (handle_level_irq+0x90/0xfc)
>> [<c00895a0>] (handle_level_irq+0x90/0xfc) from [<c008699c>] (generic_handle_irq+0x38/0x40)
>> [<c008699c>] (generic_handle_irq+0x38/0x40) from [<c02635a0>] (gpio_irq_handler+0x1b0/0x20c)
>> [<c02635a0>] (gpio_irq_handler+0x1b0/0x20c) from [<c008699c>] (generic_handle_irq+0x38/0x40)
>> [<c008699c>] (generic_handle_irq+0x38/0x40) from [<c0015404>] (handle_IRQ+0x38/0x84)
>> [<c0015404>] (handle_IRQ+0x38/0x84) from [<c000865c>] (omap3_intc_handle_irq+0x48/0x4c)
>> [<c000865c>] (omap3_intc_handle_irq+0x48/0x4c) from [<c00140c4>] (__irq_svc+0x44/0x78)
>> Exception stack(0xcf02de20 to 0xcf02de68)
>> de20: cf02c018 cf02c000 00000000 cf02de58 60000013 c06739fc 00000143 c06739fc
>> de40: 60000013 00000508 c06739dc 00000000 00022d69 cf02de68 cf02b3c0 c04890fc
>> de60: 20000013 ffffffff
>> [<c00140c4>] (__irq_svc+0x44/0x78) from [<c04890fc>] (_raw_spin_unlock_irqrestore+0x64/0x68)
>> [<c04890fc>] (_raw_spin_unlock_irqrestore+0x64/0x68) from [<c0087d50>] (__setup_irq+0x1b4/0x3d4)
>> [<c0087d50>] (__setup_irq+0x1b4/0x3d4) from [<c00881a0>] (request_threaded_irq+0xdc/0x148)
>> [<c00881a0>] (request_threaded_irq+0xdc/0x148) from [<c0482954>] (smsc911x_drv_probe+0x350/0x528)
>> [<c0482954>] (smsc911x_drv_probe+0x350/0x528) from [<c02d5a8c>] (platform_drv_probe+0x18/0x1c)
>> [<c02d5a8c>] (platform_drv_probe+0x18/0x1c) from [<c02d4580>] (really_probe+0x64/0x160)
>> [<c02d4580>] (really_probe+0x64/0x160) from [<c02d46c4>] (driver_probe_device+0x48/0x60)
>> [<c02d46c4>] (driver_probe_device+0x48/0x60) from [<c02d4770>] (__driver_attach+0x94/0x98)
>> [<c02d4770>] (__driver_attach+0x94/0x98) from [<c02d2ffc>] (bus_for_each_dev+0x54/0x80)
>> [<c02d2ffc>] (bus_for_each_dev+0x54/0x80) from [<c02d3730>] (bus_add_driver+0xa8/0x2a4)
>> [<c02d3730>] (bus_add_driver+0xa8/0x2a4) from [<c02d4d6c>] (driver_register+0x78/0x184)
>> [<c02d4d6c>] (driver_register+0x78/0x184) from [<c0008758>] (do_one_initcall+0x34/0x184)
>> [<c0008758>] (do_one_initcall+0x34/0x184) from [<c0613248>] (do_basic_setup+0x34/0x40)
>> [<c0613248>] (do_basic_setup+0x34/0x40) from [<c06132b8>] (kernel_init+0x64/0xec)
>> [<c06132b8>] (kernel_init+0x64/0xec) from [<c00154cc>] (kernel_thread_exit+0x0/0x8)
>> handlers:
>> [<c032ea98>] smsc911x_irqhandler
>> Disabling IRQ #323
>>
>> I still haven't had a chance to look into this.
>> Does anyone have a clue?
> 
> ..care to see if you have OMAP_GPIO_IRQ entry for your board? If so, we're
> still waiting for the cleanup-fixes branch to get merged that changes
> things to use gpio_to_irq() instead.

Nope, no OMAP_GPIO_IRQ in the board code.
Also, the GPIO -> IRQ mapping for the smsc911x is done in gpmc-smsc911x.c
and it uses gpio_to_irq() already.


-- 
Regards,
Igor.


From grinberg at compulab.co.il  Fri Mar 30 11:28:37 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Fri, 30 Mar 2012 18:28:37 +0300
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <1333119961.87678.YahooMailClassic@web29013.mail.ird.yahoo.com>
References: <1333119961.87678.YahooMailClassic@web29013.mail.ird.yahoo.com>
Message-ID: <4F75D125.2070203@compulab.co.il>

On 03/30/12 18:06, Paul Parsons wrote:
> --- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il> wrote:
>> On 03/28/12 20:12, Paul Parsons
>> wrote:
>>> On PXA2xx platforms, the MFP API (described in
>> Documentation/arm/pxa/mfp.txt)
>>> provides values for the following:
>>>
>>> 1. GPIO inputs (e.g. GPIO105_GPIO).
>>> 2. Alternate function inputs (e.g. GPIO105_CIF_DD_1).
>>> 3. Alternate function outputs (e.g.
>> GPIO105_KP_MKOUT_2).
>>>
>>> It does not provide values for GPIO outputs (i.e. AF0
>> outputs).
>>>
>>> One cannot use the macro used by the MFP API internally
>> - MFP_CFG_OUT() - to
>>> define new GPIO output values, since that macro is
>> forbidden in platform code.
>>>
>>> Without the ability to add GPIO outputs to the MFP
>> configuration, it is not
>>> possible to drive GPIO outputs high during sleep mode.
>>>
>>> This would be useful, for example, on the hx4700
>> platform, where driving the
>>> infrared powerdown GPIO 105 high during sleep mode
>> would save some mA.
>>>
>>> So my question is: what method should one use to add
>> GPIO outputs to the MFP
>>> configuration?
>>>
>>> One possible method, namely manually defining values in
>> the platform code:
>>>
>>>     MFP_PIN_GPIO105 | MFP_AF0 |
>> MFP_DIR_OUT | MFP_LPM_DRIVE_HIGH,
>>
>> Have you tried:
>> GPIO105_GPIO | MFP_LPM_DRIVE_HIGH,
>> ?
>>
>> This way it works on other boards.
> 
> Hello Igor,
> 
> GPIO105_GPIO expands to a GPIO input - MFP_CFG_IN(GPIO105, AF0) -
> not an output.

Yeah, I know... but read in mfp-pxa2xx.h, lines 6-20:
/*
 * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
 *
 *  MFP_PIN(x)
 *  MFP_AFx
 *  MFP_LPM_DRIVE_{LOW, HIGH}
 *  MFP_LPM_EDGE_x
 *
 * other MFP_x bit definitions will be ignored
 *
 * and adds the below two bits specifically for pxa2xx:
 *
 * bit     23 - Input/Output (PXA2xx specific)
 * bit     24 - Wakeup Enable(PXA2xx specific)
 */

Also, PXA2xx h/w does not have an MFP registers, but only AF setting regs,
So the whole MFP for PXA2xx is only to conform to newer "PXA" platform features...

-- 
Regards,
Igor.


From grinberg at compulab.co.il  Fri Mar 30 11:34:01 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Fri, 30 Mar 2012 18:34:01 +0300
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <1333119961.87678.YahooMailClassic@web29013.mail.ird.yahoo.com>
References: <1333119961.87678.YahooMailClassic@web29013.mail.ird.yahoo.com>
Message-ID: <4F75D269.7030500@compulab.co.il>



On 03/30/12 18:06, Paul Parsons wrote:
> --- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il> wrote:
>> On 03/28/12 20:12, Paul Parsons
>> wrote:
>>> On PXA2xx platforms, the MFP API (described in
>> Documentation/arm/pxa/mfp.txt)
>>> provides values for the following:
>>>
>>> 1. GPIO inputs (e.g. GPIO105_GPIO).
>>> 2. Alternate function inputs (e.g. GPIO105_CIF_DD_1).
>>> 3. Alternate function outputs (e.g.
>> GPIO105_KP_MKOUT_2).
>>>
>>> It does not provide values for GPIO outputs (i.e. AF0
>> outputs).
>>>
>>> One cannot use the macro used by the MFP API internally
>> - MFP_CFG_OUT() - to
>>> define new GPIO output values, since that macro is
>> forbidden in platform code.
>>>
>>> Without the ability to add GPIO outputs to the MFP
>> configuration, it is not
>>> possible to drive GPIO outputs high during sleep mode.
>>>
>>> This would be useful, for example, on the hx4700
>> platform, where driving the
>>> infrared powerdown GPIO 105 high during sleep mode
>> would save some mA.
>>>
>>> So my question is: what method should one use to add
>> GPIO outputs to the MFP
>>> configuration?
>>>
>>> One possible method, namely manually defining values in
>> the platform code:
>>>
>>>     MFP_PIN_GPIO105 | MFP_AF0 |
>> MFP_DIR_OUT | MFP_LPM_DRIVE_HIGH,
>>
>> Have you tried:
>> GPIO105_GPIO | MFP_LPM_DRIVE_HIGH,
>> ?
>>
>> This way it works on other boards.
> 
> Hello Igor,
> 
> GPIO105_GPIO expands to a GPIO input - MFP_CFG_IN(GPIO105, AF0) -
> not an output.

Yeah, I know... but read in mfp-pxa2xx.h, lines 6-20:
/*
 * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
 *
 *  MFP_PIN(x)
 *  MFP_AFx
 *  MFP_LPM_DRIVE_{LOW, HIGH}
 *  MFP_LPM_EDGE_x
 *
 * other MFP_x bit definitions will be ignored
 *
 * and adds the below two bits specifically for pxa2xx:
 *
 * bit     23 - Input/Output (PXA2xx specific)
 * bit     24 - Wakeup Enable(PXA2xx specific)
 */

This means, that there is no difference between: MFP_CFG_IN and MFP_CFG_OUT for PXA2xx.
The reason for this is that PXA2xx h/w does not have a dedicated MFP registers.
All goes through the GPIO controller, so the whole MFP for PXA2xx is only to conform
to newer "PXA" platform features...


-- 
Regards,
Igor.


From jon-hunter at ti.com  Fri Mar 30 11:34:40 2012
From: jon-hunter at ti.com (Jon Hunter)
Date: Fri, 30 Mar 2012 10:34:40 -0500
Subject: [PATCH-V2 3/3] ARM: OMAP: Make OMAP clocksource source selection
 runtime
In-Reply-To: <1333115655-28530-4-git-send-email-hvaibhav@ti.com>
References: <1333115655-28530-1-git-send-email-hvaibhav@ti.com>
 <1333115655-28530-4-git-send-email-hvaibhav@ti.com>
Message-ID: <4F75D290.8090706@ti.com>

Hi Vaibhav,

On 3/30/2012 8:54, Vaibhav Hiremath wrote:

> Current OMAP code supports couple of clocksource options based
> on compilation flag (CONFIG_OMAP_32K_TIMER). The 32KHz sync-timer
> and a gptimer which can run on 32KHz or system clock (e.g 38.4 MHz).
> So there can be 3 options -
> 
> 1. 32KHz sync-timer
> 2. Sys_clock based (e.g 13/19.2/26/38.4 MHz) gptimer
> 3. 32KHz based gptimer.
> 
> The optional gptimer based clocksource was added so that it can
> give the high precision than sync-timer, so expected usage was 2
> and not 3.
> Unfortunately option 2, clocksource doesn't meet the requirement of
> free-running clock as per clocksource need. It stops in low power states
> when sys_clock is cut. That makes gptimer based clocksource option
> useless for OMAP2/3/4 devices with sys_clock as a clock input.
> Option 3 will still work but it is no better than 32K sync-timer
> based clocksource.
> 
> So ideally we can kill the gptimer based clocksource option but there
> are some OMAP based derivative SoCs like AM33XX which doesn't have
> 32K sync-timer hardware IP and need to fallback on 32KHz based gptimer
> clocksource.
> Considering above, make sync-timer and gptimer clocksource runtime
> selectable so that both OMAP and AMXXXX continue to use the same code.
> 
> Use hwmod database lookup mechanism, through which at run-time
> we can identify availability of 32k-sync timer on the device,
> else fall back to gptimer.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
> Signed-off-by: Felipe Balbi <balbi at ti.com>
> CC: Santosh Shilimkar <santosh.shilimkar at ti.com>
> Cc: Benoit Cousson <b-cousson at ti.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Paul Walmsley <paul at pwsan.com>
> Cc: Tarun Kanti DebBarma <tarun.kanti at ti.com>
> Cc: Ming Lei <tom.leiming at gmail.com>
> ---
>  arch/arm/mach-omap1/timer32k.c           |    6 ++-
>  arch/arm/mach-omap2/timer.c              |   45 +++++++++-------
>  arch/arm/plat-omap/counter_32k.c         |   86 ++++++++++++-----------------
>  arch/arm/plat-omap/include/plat/common.h |    2 +-
>  4 files changed, 68 insertions(+), 71 deletions(-)

[...]

> @@ -280,13 +265,33 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
>  						const char *fck_source)
>  {
>  	int res;
> +	struct omap_hwmod *oh;
> +	const char *oh_name = "counter_32k";
> +
> +	/*
> +	 * First check for availability for 32k-sync timer.
> +	 *
> +	 * In case of failure in finding 32k_counter module or
> +	 * registering it as clocksource, execution will fallback to
> +	 * gp-timer.
> +	 */
> +	oh = omap_hwmod_lookup(oh_name);
> +	if (oh && oh->slaves_cnt != 0) {
> +		u32 pbase;
> +		unsigned long size;
> +
> +		pbase = oh->slaves[0]->addr->pa_start + 0x10;
> +		size = oh->slaves[0]->addr->pa_end -
> +			oh->slaves[0]->addr->pa_start;
> +		res = omap_init_clocksource_32k(pbase, size);
> +		if (!res)
> +			return;


If omap_init_clocksource_32k() fails should we also call BUG_ON here?

> +	}
> 
> +	/* Fall back to gp-timer code */
>  	res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
>  	BUG_ON(res);
> 
> -	pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
> -		gptimer_id, clksrc.rate);
> -
>  	__omap_dm_timer_load_start(&clksrc,
>  			OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
>  	setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
> @@ -294,8 +299,10 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
>  	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
>  		pr_err("Could not register clocksource %s\n",
>  			clocksource_gpt.name);
> +	else
> +		pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
> +			gptimer_id, clksrc.rate);
>  }
> -#endif
> 
>  #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,			\
>  				clksrc_nr, clksrc_src)			\
> diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
> index 5068fe5..c1af18c 100644
> --- a/arch/arm/plat-omap/counter_32k.c
> +++ b/arch/arm/plat-omap/counter_32k.c
> @@ -35,8 +35,6 @@
>   */
>  static void __iomem *timer_32k_base;
> 
> -#define OMAP16XX_TIMER_32K_SYNCHRONIZED		0xfffbc410
> -
>  static u32 notrace omap_32k_read_sched_clock(void)
>  {
>  	return timer_32k_base ? __raw_readl(timer_32k_base) : 0;
> @@ -68,54 +66,42 @@ void read_persistent_clock(struct timespec *ts)
>  	*ts = *tsp;
>  }
> 
> -int __init omap_init_clocksource_32k(void)
> +int __init omap_init_clocksource_32k(u32 pbase, unsigned long size)
>  {
> -	static char err[] __initdata = KERN_ERR
> -			"%s: can't register clocksource!\n";
> -
> -	if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
> -		u32 pbase;
> -		unsigned long size = SZ_4K;
> -		void __iomem *base;
> -		struct clk *sync_32k_ick;
> -
> -		if (cpu_is_omap16xx()) {
> -			pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
> -			size = SZ_1K;
> -		} else if (cpu_is_omap2420())
> -			pbase = OMAP2420_32KSYNCT_BASE + 0x10;
> -		else if (cpu_is_omap2430())
> -			pbase = OMAP2430_32KSYNCT_BASE + 0x10;
> -		else if (cpu_is_omap34xx())
> -			pbase = OMAP3430_32KSYNCT_BASE + 0x10;
> -		else if (cpu_is_omap44xx())
> -			pbase = OMAP4430_32KSYNCT_BASE + 0x10;
> -		else
> -			return -ENODEV;
> -
> -		/* For this to work we must have a static mapping in io.c for this area */
> -		base = ioremap(pbase, size);
> -		if (!base)
> -			return -ENODEV;
> -
> -		sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
> -		if (!IS_ERR(sync_32k_ick))
> -			clk_enable(sync_32k_ick);

> -

> -		timer_32k_base = base;
> -
> -		/*
> -		 * 120000 rough estimate from the calculations in
> -		 * __clocksource_updatefreq_scale.
> -		 */
> -		clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
> -				32768, NSEC_PER_SEC, 120000);
> -
> -		if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
> -					  clocksource_mmio_readl_up))
> -			printk(err, "32k_counter");
> -
> -		setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
> -	}
> +	void __iomem *base;
> +	struct clk *sync_32k_ick;
> +
> +	if (!pbase || !size)
> +		return -ENODEV;
> +	/*
> +	 * For this to work we must have a static mapping in io.c
> +	 * for this area
> +	 */
> +	base = ioremap(pbase, size);
> +	if (!base)
> +		return -ENODEV;
> +
> +	sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
> +	if (!IS_ERR(sync_32k_ick))
> +		clk_enable(sync_32k_ick);


I know that this is carry over from the original code, but seems that if
clk_get fails we should return an error. So maybe ...


	sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
	if (IS_ERR(sync_32k_ick))
		return -ENODEV;

	clk_enable(sync_32k_ick);

> +
> +	timer_32k_base = base;
> +
> +	/*
> +	 * 120000 rough estimate from the calculations in
> +	 * __clocksource_updatefreq_scale.
> +	 */
> +	clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
> +			32768, NSEC_PER_SEC, 120000);
> +
> +	if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
> +				clocksource_mmio_readl_up))
> +		pr_err("32k_counter: can't register clocksource!\n");
> +


Extra line added here that should be removed.

Cheers
Jon


From marek.vasut at gmail.com  Fri Mar 30 11:38:57 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 30 Mar 2012 17:38:57 +0200
Subject: zImage and raw ramdisk support -- test
Message-ID: <201203301738.57972.marek.vasut@gmail.com>

Guys,

I need final test on as much platforms as possible. Can you please run these two 
following patches and tell me if they work with zImage and raw ramdisk for you?

http://patchwork.ozlabs.org/patch/146848/
http://patchwork.ozlabs.org/patch/147440/

I can't promise they will make it to this release (I've been pestering WD pretty 
thoroughly (sorry about that), though I'm starting to be unhappy to merge this 
stuff at the verge of release myself).

Best regards,
Marek Vasut


From swarren at wwwdotorg.org  Fri Mar 30 11:48:16 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 09:48:16 -0600
Subject: [PATCH v3 6/6] mmc: sdhci-s3c: Add device tree support
In-Reply-To: <201203301136.05038.arnd@arndb.de>
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>
 <201203271619.13320.arnd@arndb.de> <4F7553D1.4030008@st.com>
 <201203301136.05038.arnd@arndb.de>
Message-ID: <4F75D5C0.5050307@wwwdotorg.org>

On 03/30/2012 05:36 AM, Arnd Bergmann wrote:
> On Friday 30 March 2012, Viresh Kumar wrote:
>> On 3/27/2012 9:49 PM, Arnd Bergmann wrote:
>>> These bindings came up in a discussion IRC today. I think it's rather bad that
>>> we can't agree on a common way to name the properties for mmc. We have
>>> bindings being proposed or already included from Anton, Stephen, Shawn,
>>> Rajendra, Viresh, Lee and Thomas. Almost all of them define GPIO pins
>>> for card detect and write protect, as well properties to define the bus
>>> width and high-speed modes, but we seem to have almost as many different
>>> definitions of these as we have drivers.
>>>
>>> Can we please come up with a common binding for these?
>>
>> Is there any progress on this? Sorry i wasn't following all mails.
>> How should i progress for sdhci-spear?
> 
> No progress so far. I would suggest we apply the patch below to unify
> the bindings we have. I tried to minimize the impact by picking the most
> common version for each property, but if we know about devices that would
> get broken by this, we may have to be more careful.
> 
> Signed-off-by: Arnd Bergmann <arnd at arndb.de>
> 
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/mmc.txt
> @@ -0,0 +1,25 @@
> +These properties are common to multiple MMC host controllers. Any host
> +that requires the respective functionality should implement them using
> +these definitions.
> +
> +Required properties:
> +- bus-width: Number of data lines, can be <1>, <4>, or <8>

That property looks very reasonable.

Question: This would be a non-backwards-compatible change to the binding
definition. How should this be handled? In the past, I believe it's been
stated that new kernels need to run against old device trees, and hence
once a DT binding was defined and in use, it couldn't change except in a
backwards-compatible way. However, more recently, Grant has said that
his opinion is that (some or all?) bindings are currently considered
experimental and subject to change. And besides, the .dts files are
contained in the kernel tree at present... Some generally stated and
agreed upon policy here might be useful.

> +Optional properties:
> +- cd-gpios : Specify GPIOs for card detection, see gpio binding
> +- wp-gpios : Specify GPIOs for write protection, see gpio binding

> +- cd-inverted: when present, polarity on the wp gpio line is inverted
> +- wp-inverted: when present, polarity on the wp gpio line is inverted

I'm not sure about those two: Some of the GPIO bindings have flags in
the GPIO specifier (Tegra, ARM PL061, gpio.txt mentions the possibility
of polarity being in the specifier), and bit 0 of the flags is used to
indicate inversion. I think that either we should rely on GPIO
specifiers having such flags and remove these xxx-inverted properties
from the MMC binding, or remove that flag bit from the GPIO bindings.

Note that anything using of_gpio_simple_xlate() is going to end up using
the GPIO flag definitions from <linux/of_gpio.h> in their GPIO
specifier, and there a number of active users of this feature; grep for
OF_GPIO_ACTIVE_LOW.

The rather begs the question why of_get_named_gpio() exists; surely
of_get_named_gpio_flags() should always be used so that consumers know
whether the GPIO value should be inverted, or are the GPIO flags
supposed to be processed by the OF/GPIO core or GPIO driver somehow, and
act transparently to GPIO consumers?

> diff --git a/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt
...
> -- interrupts : Should contain SD/MMC interrupt
> +- interrupt  : Should contain SD/MMC interrupt

Isn't that usually pluralized, so interrupts?

> +- bus-width : Number of data lines, can be <1>, <4>, or <8>

For the device-specific binding documentation, rather than repeating the
core bindings, shouldn't we say something like:

This binding is based on the core MMC bindings documented in mmc.txt.
This file only documents additions or changes to those bindings.

... and then remove any of the common properties from the individual files?

> diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
...
> @@ -66,5 +67,6 @@
>  
>  	sdhci at 78000400 {
>  		support-8bit;
> +		bus-width = <8>;
>  	};
>  };

Ah OK, so the first phase is to add all the new standardize properties,
then later remove all the legacy properties once the drivers have been
updated.

You've missed additions of "non-removable", but I can add them later. or
provide you an incremental patch or something.

> diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c

This doesn't seem to decode cd-inverted, or do anything with the
bus-width property value that it reads. Was that intentional?


From lost.distance at yahoo.com  Fri Mar 30 11:52:13 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 30 Mar 2012 16:52:13 +0100 (BST)
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <4F75D269.7030500@compulab.co.il>
Message-ID: <1333122733.41820.YahooMailClassic@web29002.mail.ird.yahoo.com>

--- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il> wrote:
> On 03/30/12 18:06, Paul Parsons wrote:
> > --- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il>
> wrote:
> >> On 03/28/12 20:12, Paul Parsons
> >> wrote:
> >>> On PXA2xx platforms, the MFP API (described in
> >> Documentation/arm/pxa/mfp.txt)
> >>> provides values for the following:
> >>>
> >>> 1. GPIO inputs (e.g. GPIO105_GPIO).
> >>> 2. Alternate function inputs (e.g.
> GPIO105_CIF_DD_1).
> >>> 3. Alternate function outputs (e.g.
> >> GPIO105_KP_MKOUT_2).
> >>>
> >>> It does not provide values for GPIO outputs
> (i.e. AF0
> >> outputs).
> >>>
> >>> One cannot use the macro used by the MFP API
> internally
> >> - MFP_CFG_OUT() - to
> >>> define new GPIO output values, since that macro
> is
> >> forbidden in platform code.
> >>>
> >>> Without the ability to add GPIO outputs to the
> MFP
> >> configuration, it is not
> >>> possible to drive GPIO outputs high during
> sleep mode.
> >>>
> >>> This would be useful, for example, on the
> hx4700
> >> platform, where driving the
> >>> infrared powerdown GPIO 105 high during sleep
> mode
> >> would save some mA.
> >>>
> >>> So my question is: what method should one use
> to add
> >> GPIO outputs to the MFP
> >>> configuration?
> >>>
> >>> One possible method, namely manually defining
> values in
> >> the platform code:
> >>>
> >>>? ???MFP_PIN_GPIO105 |
> MFP_AF0 |
> >> MFP_DIR_OUT | MFP_LPM_DRIVE_HIGH,
> >>
> >> Have you tried:
> >> GPIO105_GPIO | MFP_LPM_DRIVE_HIGH,
> >> ?
> >>
> >> This way it works on other boards.
> > 
> > Hello Igor,
> > 
> > GPIO105_GPIO expands to a GPIO input -
> MFP_CFG_IN(GPIO105, AF0) -
> > not an output.
> 
> Yeah, I know... but read in mfp-pxa2xx.h, lines 6-20:
> /*
>  * the following MFP_xxx bit definitions in mfp.h are
> re-used for pxa2xx:
>  *
>  *? MFP_PIN(x)
>  *? MFP_AFx
>  *? MFP_LPM_DRIVE_{LOW, HIGH}
>  *? MFP_LPM_EDGE_x
>  *
>  * other MFP_x bit definitions will be ignored
>  *
>  * and adds the below two bits specifically for pxa2xx:
>  *
>  * bit? ???23 - Input/Output (PXA2xx
> specific)
>  * bit? ???24 - Wakeup Enable(PXA2xx
> specific)
>  */
> 
> This means, that there is no difference between: MFP_CFG_IN
> and MFP_CFG_OUT for PXA2xx.

The mfp-pxa2xx.c code says otherwise. It uses the MFP direction bit
to set the GPDR registers on entering sleep mode:

   353	static int pxa2xx_mfp_suspend(void)
   354	{
   355		int i;
        ...
   368		for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
   369	
        ...
   375			GPDR(i * 32) = gpdr_lpm[i];
   376		}
   377		return 0;
   378	}

gpdr_lpm[] is initialized at startup to the current GPDR values, and
thereafter is updated by the value of the MFP_DIR_OUT bit in calls to
__mfp_config_gpio().

> The reason for this is that PXA2xx h/w does not have a
> dedicated MFP registers.
> All goes through the GPIO controller, so the whole MFP for
> PXA2xx is only to conform
> to newer "PXA" platform features...

Regards,
Paul



From rabin at rab.in  Fri Mar 30 11:55:14 2012
From: rabin at rab.in (Rabin Vincent)
Date: Fri, 30 Mar 2012 21:25:14 +0530
Subject: [PATCH v2] video: s3c-fb: Add device tree support
In-Reply-To: <1333086797-1625-1-git-send-email-thomas.abraham@linaro.org>
References: <1333086797-1625-1-git-send-email-thomas.abraham@linaro.org>
Message-ID: <CAH+eYFCrdtYC+v3tgqsaCS9-Y61JCwA1MLkkPtH14p=JWBbzBw@mail.gmail.com>

On Fri, Mar 30, 2012 at 11:23, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> + ? ?- samsung,fimd-display: The fimd controller is interfaced with the a
> + ? ? ?display device such as a lcd panel. This property should specify the
> + ? ? ?phandle of the display device node. For a display device node that
> + ? ? ?represents a RGB type display interface, it is expected to specify the
> + ? ? ?video interface timing using the following properties.
> +
> + ? ? ?- lcd-htiming: Specifies the horizontal timing for the overlay. The
> + ? ? ? ?horizontal timing includes four parameters in the following order.
> +
> + ? ? ? ?- horizontal back porch (in number of lcd clocks)
> + ? ? ? ?- horizontal front porch (in number of lcd clocks)
> + ? ? ? ?- hsync pulse width (in number of lcd clocks)
> + ? ? ? ?- Display panels X resolution.
> +
> + ? ? ?- lcd-vtiming: Specifies the vertical timing for the overlay. The
> + ? ? ? ?vertical timing includes four parameters in the following order.
> +
> + ? ? ? ?- vertical back porch (in number of lcd lines)
> + ? ? ? ?- vertical front porch (in number of lcd lines)
> + ? ? ? ?- vsync pulse width (in number of lcd clocks)
> + ? ? ? ?- Y resolution.

In this old thread, it was suggested to use a raw EDID block to supply
timings, and since then a couple of drivers in mainline (sm501fb and
fsl-diu) are doing it that way:

http://lists.ozlabs.org/pipermail/linuxppc-dev/2010-February/080683.html

Shouldn't this driver be doing the same thing?  If not, shouldn't
whatever interface this is adding be provided in a common helper (like
that old patch was trying to add) so it's standardized between drivers?


From omar.luna at linaro.org  Fri Mar 30 12:03:49 2012
From: omar.luna at linaro.org (Omar Ramirez Luna)
Date: Fri, 30 Mar 2012 11:03:49 -0500
Subject: [PATCH] iommu: OMAP: device detach on domain destroy
Message-ID: <1333123429-3727-1-git-send-email-omar.luna@linaro.org>

'domain_destroy with devices attached' case isn't yet handled, instead
code assumes that the device was already detached.

If the domain is destroyed the hardware still has access to invalid
pointers to its page table and internal iommu object. In order to
detach the users we need to track devices using the iommu, current
use cases only have one user of iommu per instance. When required
this can evolve to a list with the devices using the iommu_dev.

Reported-by: Joerg Roedel <joro at 8bytes.org>
Reviewed-by: Ohad Ben-Cohen <ohad at wizery.com>
Signed-off-by: Omar Ramirez Luna <omar.luna at linaro.org>
---
 drivers/iommu/omap-iommu.c |   32 +++++++++++++++++++++++---------
 1 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index 821062a..e32bd15 100644
--- a/drivers/iommu/omap-iommu.c
+++ b/drivers/iommu/omap-iommu.c
@@ -41,11 +41,13 @@
  * @pgtable:	the page table
  * @iommu_dev:	an omap iommu device attached to this domain. only a single
  *		iommu device can be attached for now.
+ * @dev:	Device using this domain.
  * @lock:	domain lock, should be taken when attaching/detaching
  */
 struct omap_iommu_domain {
 	u32 *pgtable;
 	struct omap_iommu *iommu_dev;
+	struct device *dev;
 	spinlock_t lock;
 };
 
@@ -1074,6 +1076,7 @@ omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
 	}
 
 	omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
+	omap_domain->dev = dev;
 	oiommu->domain = domain;
 
 	/* temporary workaround */
@@ -1084,19 +1087,16 @@ out:
 	return ret;
 }
 
-static void omap_iommu_detach_dev(struct iommu_domain *domain,
-				 struct device *dev)
+static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
+			struct device *dev)
 {
-	struct omap_iommu_domain *omap_domain = domain->priv;
-	struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
 	struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
-
-	spin_lock(&omap_domain->lock);
+	struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
 
 	/* only a single device is supported per domain for now */
 	if (omap_domain->iommu_dev != oiommu) {
 		dev_err(dev, "invalid iommu device\n");
-		goto out;
+		return;
 	}
 
 	iopgtable_clear_entry_all(oiommu);
@@ -1104,11 +1104,19 @@ static void omap_iommu_detach_dev(struct iommu_domain *domain,
 	omap_iommu_detach(oiommu);
 
 	omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
+	omap_domain->dev = NULL;
 
 	/* temporary workaround */
 	clk_disable(oiommu->clk);
+}
 
-out:
+static void omap_iommu_detach_dev(struct iommu_domain *domain,
+				 struct device *dev)
+{
+	struct omap_iommu_domain *omap_domain = domain->priv;
+
+	spin_lock(&omap_domain->lock);
+	_omap_iommu_detach_dev(omap_domain, dev);
 	spin_unlock(&omap_domain->lock);
 }
 
@@ -1147,13 +1155,19 @@ out:
 	return -ENOMEM;
 }
 
-/* assume device was already detached */
 static void omap_iommu_domain_destroy(struct iommu_domain *domain)
 {
 	struct omap_iommu_domain *omap_domain = domain->priv;
 
 	domain->priv = NULL;
 
+	/*
+	 * An iommu device is still attached
+	 * (currently, only one device can be attached) ?
+	 */
+	if (omap_domain->iommu_dev)
+		_omap_iommu_detach_dev(omap_domain, omap_domain->dev);
+
 	kfree(omap_domain->pgtable);
 	kfree(omap_domain);
 }
-- 
1.7.4.1



From hvaibhav at ti.com  Fri Mar 30 12:03:51 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 30 Mar 2012 21:33:51 +0530
Subject: [PATCH-V4 0/4] ARM: OMAP2+: Add voltagedomain,
 powerdomain & PRM support for AM33XX device
Message-ID: <1333123435-27186-1-git-send-email-hvaibhav@ti.com>

After some healthy discussion, now we have come to the conclusion and
decided to handle AM33XX PRM/CM part separately; as AM33XX-PRCM module is
different than OMAP3 and OMAP4 architecture.

The difference becomes very interesting/weird when it comes to
the consistency for register offsets in PRM address space and
bit-field offsets inside PRM registers,
So along with Powerdomain data and PRM api's required for AM33XX
device, this patch series adds,

 - XXX_RSTST register offset to "struct omap_hwmod_omap4_prcm"
 - PWRSTCTRL & PWRSTST register offsets to "struct powerdomain"
 - Logicretstate and mem_on/ret/pwrst/retst mask to "struct
   powerdomain"

Testing: This patch series has been boot tested on AM37xEVM and AM335x
         based BeagleBone community board.

Thanks to Paul here...for helping and concluding on this,
shortly I will submit similar patch for CM, clockdomain and clock-tree
support for AM33xx.

This patch-series is created on top of "linux-omap/cleanup" branch, and
also gets applied to "linux-omap/master" branch.
The patches are also available at -
https://github.com/hvaibhav/am335x-linux/tree/am335x-prm-cm

Changes from previous versions:
===============================
>From V3:
	- No code change, only added Voltagedomain patch (from V2 series)
	  to this series.

>From V1 & V2:
    	- Rolled back to my original approach, where AM33xx
	  device was handled separately (RFC version).
	- As per Paul's comments, added Register offsets & bit-fields
	  masks.

Vaibhav Hiremath (4):
  ARM: OMAP3+: am33xx: Add voltage domain data
  ARM: OMAP3/4: omap_hwmod: Add rstst_off field to struct
    omap_hwmod_omap4_prcm
  ARM: OMAP2+: powerdomain: Add offset & mask fields to struct
    powerdomain
  ARM: OMAP3+: am33xx: Add powerdomain & PRM support

 arch/arm/mach-omap2/Makefile                  |    6 +
 arch/arm/mach-omap2/io.c                      |    2 +
 arch/arm/mach-omap2/omap_hwmod.c              |   32 ++-
 arch/arm/mach-omap2/powerdomain.h             |   23 ++-
 arch/arm/mach-omap2/powerdomain33xx.c         |  230 ++++++++++++++++
 arch/arm/mach-omap2/powerdomains33xx_data.c   |  185 +++++++++++++
 arch/arm/mach-omap2/prm-regbits-33xx.h        |  357 +++++++++++++++++++++++++
 arch/arm/mach-omap2/prm33xx.c                 |  134 +++++++++
 arch/arm/mach-omap2/prm33xx.h                 |  129 +++++++++
 arch/arm/mach-omap2/voltage.h                 |    1 +
 arch/arm/mach-omap2/voltagedomains33xx_data.c |   43 +++
 arch/arm/plat-omap/include/plat/omap_hwmod.h  |    2 +
 12 files changed, 1139 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-omap2/powerdomain33xx.c
 create mode 100644 arch/arm/mach-omap2/powerdomains33xx_data.c
 create mode 100644 arch/arm/mach-omap2/prm-regbits-33xx.h
 create mode 100644 arch/arm/mach-omap2/prm33xx.c
 create mode 100644 arch/arm/mach-omap2/prm33xx.h
 create mode 100644 arch/arm/mach-omap2/voltagedomains33xx_data.c



From hvaibhav at ti.com  Fri Mar 30 12:03:52 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 30 Mar 2012 21:33:52 +0530
Subject: [PATCH-V4 1/4] ARM: OMAP3+: am33xx: Add voltage domain data
In-Reply-To: <1333123435-27186-1-git-send-email-hvaibhav@ti.com>
References: <1333123435-27186-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1333123435-27186-2-git-send-email-hvaibhav@ti.com>

Currently dummy voltage domain data is being created
in order to succeed boot process, nothing has been done
w.r.t actual hardware (voltage control).

Also, hook up the AM33XX voltage domain to OMAP framework.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Signed-off-by: Afzal Mohammed <afzal at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/Makefile                  |    2 +
 arch/arm/mach-omap2/io.c                      |    1 +
 arch/arm/mach-omap2/voltage.h                 |    1 +
 arch/arm/mach-omap2/voltagedomains33xx_data.c |   43 +++++++++++++++++++++++++
 4 files changed, 47 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-omap2/voltagedomains33xx_data.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 74ae499..8d90f9f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -99,6 +99,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= $(voltagedomain-common) \
 					   voltagedomains2xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= $(voltagedomain-common) \
 					   voltagedomains3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX)		+= $(voltagedomain-common) \
+					   voltagedomains33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(voltagedomain-common) \
 					   voltagedomains44xx_data.o

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 51d4df8..523fb6d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -466,6 +466,7 @@ void __init am33xx_init_early(void)
 {
 	omap2_set_globals_am33xx();
 	omap_common_init_early();
+	am33xx_voltagedomains_init();
 	omap3xxx_clk_init();
 }
 #endif
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 16a1b09..a7c43c1 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -156,6 +156,7 @@ int omap_voltage_late_init(void);

 extern void omap2xxx_voltagedomains_init(void);
 extern void omap3xxx_voltagedomains_init(void);
+extern void am33xx_voltagedomains_init(void);
 extern void omap44xx_voltagedomains_init(void);

 struct voltagedomain *voltdm_lookup(const char *name);
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c
new file mode 100644
index 0000000..965458d
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c
@@ -0,0 +1,43 @@
+/*
+ * AM33XX voltage domain data
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "voltage.h"
+
+static struct voltagedomain am33xx_voltdm_mpu = {
+	.name		= "mpu",
+};
+
+static struct voltagedomain am33xx_voltdm_core = {
+	.name		= "core",
+};
+
+static struct voltagedomain am33xx_voltdm_rtc = {
+	.name		= "rtc",
+};
+
+static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
+	&am33xx_voltdm_mpu,
+	&am33xx_voltdm_core,
+	&am33xx_voltdm_rtc,
+	NULL,
+};
+
+void __init am33xx_voltagedomains_init(void)
+{
+	voltdm_init(voltagedomains_am33xx);
+}
--
1.7.0.4



From hvaibhav at ti.com  Fri Mar 30 12:03:53 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 30 Mar 2012 21:33:53 +0530
Subject: [PATCH-V4 2/4] ARM: OMAP3/4: omap_hwmod: Add rstst_off field to
 struct omap_hwmod_omap4_prcm
In-Reply-To: <1333123435-27186-1-git-send-email-hvaibhav@ti.com>
References: <1333123435-27186-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1333123435-27186-3-git-send-email-hvaibhav@ti.com>

In case of AM33XX device, XXX_RSTST register offset is not
consistent across PRM modules/instances,

PRM_XXX            RSTST
=========================
PRM_PER_MOD:       0x04
PRM_WKUP_MOD:      0x0C
PRM_MPU_MOD:       NA
PRM_DEVICE_MOD:    0x08

This means, we need to pass on XXX_RSTST register offset
information through omap_hwmod data, similar to XXX_RSTCTRL.

Currently, this field is only applicable and used for AM33XX
devices.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 9ae87eb..50f42ec 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -374,11 +374,13 @@ struct omap_hwmod_omap2_prcm {
  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
  * @clkctrl_reg: PRCM address of the clock control register
  * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
+ * @rstst_reg: (AM33XX Only) address of the XXX_RSTST register located in the PRM
  * @submodule_wkdep_bit: bit shift of the WKDEP range
  */
 struct omap_hwmod_omap4_prcm {
 	u16		clkctrl_offs;
 	u16		rstctrl_offs;
+	u16		rstst_offs;
 	u16		context_offs;
 	u8		submodule_wkdep_bit;
 	u8		modulemode;
--
1.7.0.4



From hvaibhav at ti.com  Fri Mar 30 12:03:54 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 30 Mar 2012 21:33:54 +0530
Subject: [PATCH-V4 3/4] ARM: OMAP2+: powerdomain: Add offset & mask fields to
 struct powerdomain
In-Reply-To: <1333123435-27186-1-git-send-email-hvaibhav@ti.com>
References: <1333123435-27186-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1333123435-27186-4-git-send-email-hvaibhav@ti.com>

In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -

PRM_XXX           PWRSTCTRL     PWRSTST
=======================================
PRM_PER_MOD:      0x0C,         0x08
PRM_WKUP_MOD:     0x04,         0x08
PRM_MPU_MOD:      0x00,         0x04
PRM_DEVICE_MOD:   NA,           NA

And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -

PRM_XXX           LOGICRET  MEMON  MEMRET
=======================================
GFX_PWRCTRL:      2,        17,    6
PER_PWRCTRL:      3,        25,    29
MPU_PWRCTRL:      2,        18,    22
WKUP_PWRCTRL:     3,        NA,    NA

This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
   - PWRSTCTRL/ST register offset
   - Logic retention state mask
   - mem_on/ret/pwrst/retst mask

Currently, this fields is only applicable and used for AM33XX devices.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/powerdomain.h |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 0d72a8a..8fc50b2 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -92,6 +92,15 @@ struct powerdomain;
  * @pwrdm_clkdms: Clockdomains in this powerdomain
  * @node: list_head linking all powerdomains
  * @voltdm_node: list_head linking all powerdomains in a voltagedomain
+ * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
+ * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
+ * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
+ *	in @pwrstctrl_offs
+ * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
+ * @mem_ret_mask: (AM33XX only) mask for mem retention bitfield in @pwrstctrl_offs
+ * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
+ * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
+ *	in @pwrstctrl_offs
  * @state:
  * @state_counter:
  * @timer:
@@ -121,6 +130,14 @@ struct powerdomain {
 	unsigned ret_logic_off_counter;
 	unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];

+	const u8 pwrstctrl_offs;
+	const u8 pwrstst_offs;
+	const u32 logicretstate_mask;
+	const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
+	const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
+	const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
+	const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
+
 #ifdef CONFIG_PM_DEBUG
 	s64 timer;
 	s64 state_timer[PWRDM_MAX_PWRSTS];
--
1.7.0.4



From hvaibhav at ti.com  Fri Mar 30 12:03:55 2012
From: hvaibhav at ti.com (Vaibhav Hiremath)
Date: Fri, 30 Mar 2012 21:33:55 +0530
Subject: [PATCH-V4 4/4] ARM: OMAP3+: am33xx: Add powerdomain & PRM support
In-Reply-To: <1333123435-27186-1-git-send-email-hvaibhav@ti.com>
References: <1333123435-27186-1-git-send-email-hvaibhav@ti.com>
Message-ID: <1333123435-27186-5-git-send-email-hvaibhav@ti.com>

As far as PRM/CM/PRCM modules are concerned, AM33XX device is
different than OMAP3 and OMAP4 architectures; so we need to
handle it separately.
This patch adds support for, Powerdomain, Powerdomain data,
PRM api's required for AM33XX device.

And also, hooks up AM33XX powerdomain to existing OMAP framework.

Signed-off-by: Vaibhav Hiremath <hvaibhav at ti.com>
Signed-off-by: Afzal Mohammed <afzal at ti.com>
Cc: Benoit Cousson <b-cousson at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Paul Walmsley <paul at pwsan.com>
Cc: Rajendra Nayak <rnayak at ti.com>
---
 arch/arm/mach-omap2/Makefile                |    4 +
 arch/arm/mach-omap2/io.c                    |    1 +
 arch/arm/mach-omap2/omap_hwmod.c            |   32 +++-
 arch/arm/mach-omap2/powerdomain.h           |    6 +-
 arch/arm/mach-omap2/powerdomain33xx.c       |  230 +++++++++++++++++
 arch/arm/mach-omap2/powerdomains33xx_data.c |  185 ++++++++++++++
 arch/arm/mach-omap2/prm-regbits-33xx.h      |  357 +++++++++++++++++++++++++++
 arch/arm/mach-omap2/prm33xx.c               |  134 ++++++++++
 arch/arm/mach-omap2/prm33xx.h               |  129 ++++++++++
 9 files changed, 1073 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-omap2/powerdomain33xx.c
 create mode 100644 arch/arm/mach-omap2/powerdomains33xx_data.c
 create mode 100644 arch/arm/mach-omap2/prm-regbits-33xx.h
 create mode 100644 arch/arm/mach-omap2/prm33xx.c
 create mode 100644 arch/arm/mach-omap2/prm33xx.h

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8d90f9f..8220369 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -114,6 +114,10 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(powerdomain-common) \
 					   powerdomain2xxx_3xxx.o \
 					   powerdomains3xxx_data.o \
 					   powerdomains2xxx_3xxx_data.o
+obj-$(CONFIG_SOC_OMAPAM33XX)		+= $(powerdomain-common) \
+					   prm33xx.o \
+					   powerdomain33xx.o \
+					   powerdomains33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common) \
 					   powerdomain44xx.o \
 					   powerdomains44xx_data.o
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 523fb6d..b8fd170 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -467,6 +467,7 @@ void __init am33xx_init_early(void)
 	omap2_set_globals_am33xx();
 	omap_common_init_early();
 	am33xx_voltagedomains_init();
+	am33xx_powerdomains_init();
 	omap3xxx_clk_init();
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5192cab..97b47f2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -150,6 +150,7 @@
 #include "cminst44xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
+#include "prm33xx.h"
 #include "prminst44xx.h"
 #include "mux.h"

@@ -1288,7 +1289,15 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
 	if (IS_ERR_VALUE(ret))
 		return ret;

-	if (cpu_is_omap24xx() || cpu_is_omap34xx())
+	/*
+	 * cpu_is_omap34xx() is true for am33xx device as well, so
+	 * fist check for cpu_is_am33xx().
+	 */
+	if (cpu_is_am33xx())
+		return am33xx_prm_assert_hardreset(ohri.rst_shift,
+				oh->clkdm->pwrdm.ptr->prcm_offs,
+				oh->prcm.omap4.rstctrl_offs);
+	else if (cpu_is_omap24xx() || cpu_is_omap34xx())
 		return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
 						  ohri.rst_shift);
 	else if (cpu_is_omap44xx())
@@ -1322,7 +1331,16 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 	if (IS_ERR_VALUE(ret))
 		return ret;

-	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+	/*
+	 * cpu_is_omap34xx() is true for am33xx device as well, so
+	 * fist check for cpu_is_am33xx().
+	 */
+	if (cpu_is_am33xx()) {
+		return am33xx_prm_deassert_hardreset(ohri.rst_shift,
+				oh->clkdm->pwrdm.ptr->prcm_offs,
+				oh->prcm.omap4.rstctrl_offs,
+				oh->prcm.omap4.rstst_offs);
+	} else if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
 		ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
 						   ohri.rst_shift,
 						   ohri.st_shift);
@@ -1364,7 +1382,15 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 	if (IS_ERR_VALUE(ret))
 		return ret;

-	if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+	/*
+	 * cpu_is_omap34xx() is true for am33xx device as well, so
+	 * fist check for cpu_is_am33xx().
+	 */
+	if (cpu_is_am33xx()) {
+		return am33xx_prm_is_hardreset_asserted(ohri.rst_shift,
+				oh->clkdm->pwrdm.ptr->prcm_offs,
+				oh->prcm.omap4.rstctrl_offs);
+	} else if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
 		return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
 						       ohri.st_shift);
 	} else if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 8fc50b2..53e42a9 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -67,9 +67,9 @@

 /*
  * Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain on OMAP4 is the worst case
+ * PER powerdomain on AM33XX is the worst case
  */
-#define PWRDM_MAX_CLKDMS	9
+#define PWRDM_MAX_CLKDMS	11

 /* XXX A completely arbitrary number. What is reasonable here? */
 #define PWRDM_TRANSITION_BAILOUT 100000
@@ -240,10 +240,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
 extern void omap242x_powerdomains_init(void);
 extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
+extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);

 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
+extern struct pwrdm_ops am33xx_pwrdm_operations;
 extern struct pwrdm_ops omap4_pwrdm_operations;

 /* Common Internal functions used across OMAP rev's */
diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c
new file mode 100644
index 0000000..c53f8d8
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain33xx.c
@@ -0,0 +1,230 @@
+/*
+ * AM33XX Powerdomain control
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
+ * <rnayak at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include <plat/prcm.h>
+
+#include "powerdomain.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+
+static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+	am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
+			(pwrst << OMAP_POWERSTATE_SHIFT),
+			pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+	return 0;
+}
+
+static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs,  pwrdm->pwrstctrl_offs);
+	v &= OMAP_POWERSTATE_MASK;
+	v >>= OMAP_POWERSTATE_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+	v &= OMAP_POWERSTATEST_MASK;
+	v >>= OMAP_POWERSTATEST_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+	v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
+	v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+	am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
+			(1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
+			pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+	return 0;
+}
+
+static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+	am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
+			AM33XX_LASTPOWERSTATEENTERED_MASK,
+			pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+	return 0;
+}
+
+static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+	u32 m;
+
+	m = pwrdm->logicretstate_mask;
+	if (!m)
+		return -EINVAL;
+
+	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+			pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+	return 0;
+}
+
+static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+	v &= AM33XX_LOGICSTATEST_MASK;
+	v >>= AM33XX_LOGICSTATEST_SHIFT;
+
+	return v;
+}
+
+static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+	u32 v, m;
+
+	m = pwrdm->logicretstate_mask;
+	if (!m)
+		return -EINVAL;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+	v &= m;
+	v >>= __ffs(m);
+
+	return v;
+}
+
+static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+		u8 pwrst)
+{
+	u32 m;
+
+	m = pwrdm->mem_on_mask[bank];
+	if (!m)
+		return -EINVAL;
+
+	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+			pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+	return 0;
+}
+
+static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+					u8 pwrst)
+{
+	u32 m;
+
+	m = pwrdm->mem_ret_mask[bank];
+	if (!m)
+		return -EINVAL;
+
+	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+			pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+	return 0;
+}
+
+static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+	u32 m, v;
+
+	m = pwrdm->mem_pwrst_mask[bank];
+	if (!m)
+		return -EINVAL;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+	v &= m;
+	v >>= __ffs(m);
+
+	return v;
+}
+
+static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+	u32 m, v;
+
+	m = pwrdm->mem_retst_mask[bank];
+	if (!m)
+		return -EINVAL;
+
+	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+	v &= m;
+	v >>= __ffs(m);
+
+	return v;
+}
+
+static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+	u32 c = 0;
+
+	/*
+	 * REVISIT: pwrdm_wait_transition() may be better implemented
+	 * via a callback and a periodic timer check -- how long do we expect
+	 * powerdomain transitions to take?
+	 */
+
+	/* XXX Is this udelay() value meaningful? */
+	while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
+			& OMAP_INTRANSITION_MASK) &&
+			(c++ < PWRDM_TRANSITION_BAILOUT))
+		udelay(1);
+
+	if (c > PWRDM_TRANSITION_BAILOUT) {
+		printk(KERN_ERR "powerdomain: waited too long for "
+				"powerdomain %s to complete transition\n",
+				pwrdm->name);
+		return -EAGAIN;
+	}
+
+	pr_debug("powerdomain: completed transition in %d loops\n", c);
+
+	return 0;
+}
+
+struct pwrdm_ops am33xx_pwrdm_operations = {
+	.pwrdm_set_next_pwrst		= am33xx_pwrdm_set_next_pwrst,
+	.pwrdm_read_next_pwrst		= am33xx_pwrdm_read_next_pwrst,
+	.pwrdm_read_pwrst		= am33xx_pwrdm_read_pwrst,
+	.pwrdm_read_prev_pwrst		= am33xx_pwrdm_read_prev_pwrst,
+	.pwrdm_set_logic_retst		= am33xx_pwrdm_set_logic_retst,
+	.pwrdm_read_logic_pwrst		= am33xx_pwrdm_read_logic_pwrst,
+	.pwrdm_read_logic_retst		= am33xx_pwrdm_read_logic_retst,
+	.pwrdm_clear_all_prev_pwrst	= am33xx_pwrdm_clear_all_prev_pwrst,
+	.pwrdm_set_lowpwrstchange	= am33xx_pwrdm_set_lowpwrstchange,
+	.pwrdm_read_mem_pwrst		= am33xx_pwrdm_read_mem_pwrst,
+	.pwrdm_read_mem_retst		= am33xx_pwrdm_read_mem_retst,
+	.pwrdm_set_mem_onst		= am33xx_pwrdm_set_mem_onst,
+	.pwrdm_set_mem_retst		= am33xx_pwrdm_set_mem_retst,
+	.pwrdm_wait_transition		= am33xx_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
new file mode 100644
index 0000000..869adb8
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -0,0 +1,185 @@
+/*
+ * AM33XX Power domain data
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+#include "prcm-common.h"
+#include "prm-regbits-33xx.h"
+#include "prm33xx.h"
+
+static struct powerdomain gfx_33xx_pwrdm = {
+	.name			= "gfx_pwrdm",
+	.voltdm			= { .name = "core" },
+	.prcm_offs		= AM33XX_PRM_GFX_MOD,
+	.pwrstctrl_offs		= AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
+	.pwrstst_offs		= AM33XX_PM_GFX_PWRSTST_OFFSET,
+	.pwrsts			= PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+	.banks			= 1,
+	.logicretstate_mask	= AM33XX_LOGICRETSTATE_MASK,
+	.mem_on_mask		= {
+		[0]		= AM33XX_GFX_MEM_ONSTATE_MASK,	/* gfx_mem */
+	},
+	.mem_ret_mask		= {
+		[0]		= AM33XX_GFX_MEM_RETSTATE_MASK,	/* gfx_mem */
+	},
+	.mem_pwrst_mask		= {
+		[0]		= AM33XX_GFX_MEM_STATEST_MASK,	/* gfx_mem */
+	},
+	.mem_retst_mask		= {
+		[0]		= AM33XX_GFX_MEM_RETSTATE_MASK,	/* gfx_mem */
+	},
+	.pwrsts_mem_ret		= {
+		[0]		= PWRSTS_OFF_RET,	/* gfx_mem */
+	},
+	.pwrsts_mem_on		= {
+		[0]		= PWRSTS_ON,		/* gfx_mem */
+	},
+};
+
+static struct powerdomain rtc_33xx_pwrdm = {
+	.name			= "rtc_pwrdm",
+	.voltdm			= { .name = "rtc" },
+	.prcm_offs		= AM33XX_PRM_RTC_MOD,
+	.pwrstctrl_offs		= AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
+	.pwrstst_offs		= AM33XX_PM_RTC_PWRSTST_OFFSET,
+	.pwrsts			= PWRSTS_ON,
+	.logicretstate_mask	= AM33XX_LOGICRETSTATE_MASK,
+};
+
+static struct powerdomain wkup_33xx_pwrdm = {
+	.name			= "wkup_pwrdm",
+	.voltdm			= { .name = "core" },
+	.prcm_offs		= AM33XX_PRM_WKUP_MOD,
+	.pwrstctrl_offs		= AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
+	.pwrstst_offs		= AM33XX_PM_WKUP_PWRSTST_OFFSET,
+	.pwrsts			= PWRSTS_ON,
+	.logicretstate_mask	= AM33XX_LOGICRETSTATE_3_3_MASK,
+};
+
+static struct powerdomain per_33xx_pwrdm = {
+	.name			= "per_pwrdm",
+	.voltdm			= { .name = "core" },
+	.prcm_offs		= AM33XX_PRM_PER_MOD,
+	.pwrstctrl_offs		= AM33XX_PM_PER_PWRSTCTRL_OFFSET,
+	.pwrstst_offs		= AM33XX_PM_PER_PWRSTST_OFFSET,
+	.pwrsts			= PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+	.banks			= 3,
+	.logicretstate_mask	= AM33XX_LOGICRETSTATE_3_3_MASK,
+	.mem_on_mask		= {
+		[0]		= AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
+		[1]		= AM33XX_PER_MEM_ONSTATE_MASK,	/* per_mem */
+		[2]		= AM33XX_RAM_MEM_ONSTATE_MASK,	/* ram_mem */
+	},
+	.mem_ret_mask		= {
+		[0]		= AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
+		[1]		= AM33XX_PER_MEM_RETSTATE_MASK,	/* per_mem */
+		[2]		= AM33XX_RAM_MEM_RETSTATE_MASK,	/* ram_mem */
+	},
+	.mem_pwrst_mask		= {
+		[0]		= AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
+		[1]		= AM33XX_PER_MEM_STATEST_MASK,	/* per_mem */
+		[2]		= AM33XX_RAM_MEM_STATEST_MASK,	/* ram_mem */
+	},
+	.mem_retst_mask		= {
+		[0]		= AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
+		[1]		= AM33XX_PER_MEM_RETSTATE_MASK,	/* per_mem */
+		[2]		= AM33XX_RAM_MEM_RETSTATE_MASK,	/* ram_mem */
+	},
+	.pwrsts_mem_ret		= {
+		[0]		= PWRSTS_OFF_RET,	/* pruss_mem */
+		[1]		= PWRSTS_OFF_RET,	/* per_mem */
+		[2]		= PWRSTS_OFF_RET,	/* ram_mem */
+	},
+	.pwrsts_mem_on		= {
+		[0]		= PWRSTS_ON,		/* pruss_mem */
+		[1]		= PWRSTS_ON,		/* per_mem */
+		[2]		= PWRSTS_ON,		/* ram_mem */
+	},
+};
+
+static struct powerdomain mpu_33xx_pwrdm = {
+	.name			= "mpu_pwrdm",
+	.voltdm			= { .name = "mpu" },
+	.prcm_offs		= AM33XX_PRM_MPU_MOD,
+	.pwrstctrl_offs		= AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
+	.pwrstst_offs		= AM33XX_PM_MPU_PWRSTST_OFFSET,
+	.pwrsts			= PWRSTS_OFF_RET_ON,
+	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
+	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
+	.banks			= 3,
+	.logicretstate_mask	= AM33XX_LOGICRETSTATE_MASK,
+	.mem_on_mask		= {
+		[0]		= AM33XX_MPU_L1_ONSTATE_MASK,	/* mpu_l1 */
+		[1]		= AM33XX_MPU_L2_ONSTATE_MASK,	/* mpu_l2 */
+		[2]		= AM33XX_MPU_RAM_ONSTATE_MASK,	/* mpu_ram */
+	},
+	.mem_ret_mask		= {
+		[0]		= AM33XX_MPU_L1_RETSTATE_MASK,	/* mpu_l1 */
+		[1]		= AM33XX_MPU_L2_RETSTATE_MASK,	/* mpu_l2 */
+		[2]		= AM33XX_MPU_RAM_RETSTATE_MASK,	/* mpu_ram */
+	},
+	.mem_pwrst_mask		= {
+		[0]		= AM33XX_MPU_L1_STATEST_MASK,	/* mpu_l1 */
+		[1]		= AM33XX_MPU_L2_STATEST_MASK,	/* mpu_l2 */
+		[2]		= AM33XX_MPU_RAM_STATEST_MASK,	/* mpu_ram */
+	},
+	.mem_retst_mask		= {
+		[0]		= AM33XX_MPU_L1_RETSTATE_MASK,	/* mpu_l1 */
+		[1]		= AM33XX_MPU_L2_RETSTATE_MASK,	/* mpu_l2 */
+		[2]		= AM33XX_MPU_RAM_RETSTATE_MASK,	/* mpu_ram */
+	},
+	.pwrsts_mem_ret		= {
+		[0]		= PWRSTS_OFF_RET,	/* mpu_l1 */
+		[1]		= PWRSTS_OFF_RET,	/* mpu_l2 */
+		[2]		= PWRSTS_OFF_RET,	/* mpu_ram */
+	},
+	.pwrsts_mem_on		= {
+		[0]		= PWRSTS_ON,		/* mpu_l1 */
+		[1]		= PWRSTS_ON,		/* mpu_l2 */
+		[2]		= PWRSTS_ON,		/* mpu_ram */
+	},
+};
+
+static struct powerdomain cefuse_33xx_pwrdm = {
+	.name		= "cefuse_pwrdm",
+	.voltdm		= { .name = "core" },
+	.prcm_offs	= AM33XX_PRM_CEFUSE_MOD,
+	.pwrstctrl_offs	= AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
+	.pwrstst_offs	= AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
+	.pwrsts		= PWRSTS_OFF_ON,
+};
+
+static struct powerdomain *powerdomains_am33xx[] __initdata = {
+	&gfx_33xx_pwrdm,
+	&rtc_33xx_pwrdm,
+	&wkup_33xx_pwrdm,
+	&per_33xx_pwrdm,
+	&mpu_33xx_pwrdm,
+	&cefuse_33xx_pwrdm,
+	NULL,
+};
+
+void __init am33xx_powerdomains_init(void)
+{
+	pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
+	pwrdm_register_pwrdms(powerdomains_am33xx);
+	pwrdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
new file mode 100644
index 0000000..0221b5c
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -0,0 +1,357 @@
+/*
+ * AM33XX PRM_XXX register bits
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+
+#include "prm.h"
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT			1
+#define AM33XX_ABBOFF_ACT_EXPORT_MASK			(1 << 1)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT		2
+#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK			(1 << 2)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_AIPOFF_SHIFT				8
+#define AM33XX_AIPOFF_MASK				(1 << 8)
+
+/* Used by PM_WKUP_PWRSTST */
+#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT		17
+#define AM33XX_DEBUGSS_MEM_STATEST_MASK			(0x3 << 17)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_DISABLE_RTA_EXPORT_SHIFT			0
+#define AM33XX_DISABLE_RTA_EXPORT_MASK			(1 << 0)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT			12
+#define AM33XX_DPLL_CORE_RECAL_EN_MASK			(1 << 12)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT			12
+#define AM33XX_DPLL_CORE_RECAL_ST_MASK			(1 << 12)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT			14
+#define AM33XX_DPLL_DDR_RECAL_EN_MASK			(1 << 14)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT			14
+#define AM33XX_DPLL_DDR_RECAL_ST_MASK			(1 << 14)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT			15
+#define AM33XX_DPLL_DISP_RECAL_EN_MASK			(1 << 15)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT			13
+#define AM33XX_DPLL_DISP_RECAL_ST_MASK			(1 << 13)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT			11
+#define AM33XX_DPLL_MPU_RECAL_EN_MASK			(1 << 11)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT			11
+#define AM33XX_DPLL_MPU_RECAL_ST_MASK			(1 << 11)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_PER_RECAL_EN_SHIFT			13
+#define AM33XX_DPLL_PER_RECAL_EN_MASK			(1 << 13)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_PER_RECAL_ST_SHIFT			15
+#define AM33XX_DPLL_PER_RECAL_ST_MASK			(1 << 15)
+
+/* Used by RM_WKUP_RSTST */
+#define AM33XX_EMULATION_M3_RST_SHIFT			6
+#define AM33XX_EMULATION_M3_RST_MASK			(1 << 6)
+
+/* Used by RM_MPU_RSTST */
+#define AM33XX_EMULATION_MPU_RST_SHIFT			5
+#define AM33XX_EMULATION_MPU_RST_MASK			(1 << 5)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC1_EXPORT_SHIFT			3
+#define AM33XX_ENFUNC1_EXPORT_MASK			(1 << 3)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC3_EXPORT_SHIFT			5
+#define AM33XX_ENFUNC3_EXPORT_MASK			(1 << 5)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC4_SHIFT				6
+#define AM33XX_ENFUNC4_MASK				(1 << 6)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC5_SHIFT				7
+#define AM33XX_ENFUNC5_MASK				(1 << 7)
+
+/* Used by PRM_RSTST */
+#define AM33XX_EXTERNAL_WARM_RST_SHIFT			5
+#define AM33XX_EXTERNAL_WARM_RST_MASK			(1 << 5)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_FORCEWKUP_EN_SHIFT			10
+#define AM33XX_FORCEWKUP_EN_MASK			(1 << 10)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_FORCEWKUP_ST_SHIFT			10
+#define AM33XX_FORCEWKUP_ST_MASK			(1 << 10)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define AM33XX_GFX_MEM_ONSTATE_SHIFT			17
+#define AM33XX_GFX_MEM_ONSTATE_MASK			(0x3 << 17)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define AM33XX_GFX_MEM_RETSTATE_SHIFT			6
+#define AM33XX_GFX_MEM_RETSTATE_MASK			(1 << 6)
+
+/* Used by PM_GFX_PWRSTST */
+#define AM33XX_GFX_MEM_STATEST_SHIFT			4
+#define AM33XX_GFX_MEM_STATEST_MASK			(0x3 << 4)
+
+/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
+#define AM33XX_GFX_RST_SHIFT				0
+#define AM33XX_GFX_RST_MASK				(1 << 0)
+
+/* Used by PRM_RSTST */
+#define AM33XX_GLOBAL_COLD_RST_SHIFT			0
+#define AM33XX_GLOBAL_COLD_RST_MASK			(1 << 0)
+
+/* Used by PRM_RSTST */
+#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT			1
+#define AM33XX_GLOBAL_WARM_SW_RST_MASK			(1 << 1)
+
+/* Used by RM_WKUP_RSTST */
+#define AM33XX_ICECRUSHER_M3_RST_SHIFT			7
+#define AM33XX_ICECRUSHER_M3_RST_MASK			(1 << 7)
+
+/* Used by RM_MPU_RSTST */
+#define AM33XX_ICECRUSHER_MPU_RST_SHIFT			6
+#define AM33XX_ICECRUSHER_MPU_RST_MASK			(1 << 6)
+
+/* Used by PRM_RSTST */
+#define AM33XX_ICEPICK_RST_SHIFT			9
+#define AM33XX_ICEPICK_RST_MASK				(1 << 9)
+
+/* Used by RM_PER_RSTCTRL */
+#define AM33XX_PRUSS_LRST_SHIFT				1
+#define AM33XX_PRUSS_LRST_MASK				(1 << 1)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT			5
+#define AM33XX_PRUSS_MEM_ONSTATE_MASK			(0x3 << 5)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT			7
+#define AM33XX_PRUSS_MEM_RETSTATE_MASK			(1 << 7)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_PRUSS_MEM_STATEST_SHIFT			23
+#define AM33XX_PRUSS_MEM_STATEST_MASK			(0x3 << 23)
+
+/*
+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ */
+#define AM33XX_INTRANSITION_SHIFT			20
+#define AM33XX_INTRANSITION_MASK			(1 << 20)
+
+/* Used by PM_CEFUSE_PWRSTST */
+#define AM33XX_LASTPOWERSTATEENTERED_SHIFT		24
+#define AM33XX_LASTPOWERSTATEENTERED_MASK		(0x3 << 24)
+
+/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
+#define AM33XX_LOGICRETSTATE_SHIFT			2
+#define AM33XX_LOGICRETSTATE_MASK			(1 << 2)
+
+/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
+#define AM33XX_LOGICRETSTATE_3_3_SHIFT			3
+#define AM33XX_LOGICRETSTATE_3_3_MASK			(1 << 3)
+
+/*
+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ */
+#define AM33XX_LOGICSTATEST_SHIFT			2
+#define AM33XX_LOGICSTATEST_MASK			(1 << 2)
+
+/*
+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
+ */
+#define AM33XX_LOWPOWERSTATECHANGE_SHIFT		4
+#define AM33XX_LOWPOWERSTATECHANGE_MASK			(1 << 4)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L1_ONSTATE_SHIFT			18
+#define AM33XX_MPU_L1_ONSTATE_MASK			(0x3 << 18)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L1_RETSTATE_SHIFT			22
+#define AM33XX_MPU_L1_RETSTATE_MASK			(1 << 22)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_L1_STATEST_SHIFT			6
+#define AM33XX_MPU_L1_STATEST_MASK			(0x3 << 6)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L2_ONSTATE_SHIFT			20
+#define AM33XX_MPU_L2_ONSTATE_MASK			(0x3 << 20)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L2_RETSTATE_SHIFT			23
+#define AM33XX_MPU_L2_RETSTATE_MASK			(1 << 23)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_L2_STATEST_SHIFT			8
+#define AM33XX_MPU_L2_STATEST_MASK			(0x3 << 8)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_RAM_ONSTATE_SHIFT			16
+#define AM33XX_MPU_RAM_ONSTATE_MASK			(0x3 << 16)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_RAM_RETSTATE_SHIFT			24
+#define AM33XX_MPU_RAM_RETSTATE_MASK			(1 << 24)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_RAM_STATEST_SHIFT			4
+#define AM33XX_MPU_RAM_STATEST_MASK			(0x3 << 4)
+
+/* Used by PRM_RSTST */
+#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT		2
+#define AM33XX_MPU_SECURITY_VIOL_RST_MASK		(1 << 2)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_PCHARGECNT_VALUE_SHIFT			0
+#define AM33XX_PCHARGECNT_VALUE_MASK			(0x3f << 0)
+
+/* Used by RM_PER_RSTCTRL */
+#define AM33XX_PCI_LRST_SHIFT				0
+#define AM33XX_PCI_LRST_MASK				(1 << 0)
+
+/* Renamed from PCI_LRST Used by RM_PER_RSTST */
+#define AM33XX_PCI_LRST_5_5_SHIFT			5
+#define AM33XX_PCI_LRST_5_5_MASK			(1 << 5)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PER_MEM_ONSTATE_SHIFT			25
+#define AM33XX_PER_MEM_ONSTATE_MASK			(0x3 << 25)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PER_MEM_RETSTATE_SHIFT			29
+#define AM33XX_PER_MEM_RETSTATE_MASK			(1 << 29)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_PER_MEM_STATEST_SHIFT			17
+#define AM33XX_PER_MEM_STATEST_MASK			(0x3 << 17)
+
+/*
+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL
+ */
+#define AM33XX_POWERSTATE_SHIFT				0
+#define AM33XX_POWERSTATE_MASK				(0x3 << 0)
+
+/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
+#define AM33XX_POWERSTATEST_SHIFT			0
+#define AM33XX_POWERSTATEST_MASK			(0x3 << 0)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_RAM_MEM_ONSTATE_SHIFT			30
+#define AM33XX_RAM_MEM_ONSTATE_MASK			(0x3 << 30)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_RAM_MEM_RETSTATE_SHIFT			27
+#define AM33XX_RAM_MEM_RETSTATE_MASK			(1 << 27)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_RAM_MEM_STATEST_SHIFT			21
+#define AM33XX_RAM_MEM_STATEST_MASK			(0x3 << 21)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_RETMODE_ENABLE_SHIFT			0
+#define AM33XX_RETMODE_ENABLE_MASK			(1 << 0)
+
+/* Used by REVISION_PRM */
+#define AM33XX_REV_SHIFT				0
+#define AM33XX_REV_MASK					(0xff << 0)
+
+/* Used by PRM_RSTTIME */
+#define AM33XX_RSTTIME1_SHIFT				0
+#define AM33XX_RSTTIME1_MASK				(0xff << 0)
+
+/* Used by PRM_RSTTIME */
+#define AM33XX_RSTTIME2_SHIFT				8
+#define AM33XX_RSTTIME2_MASK				(0x1f << 8)
+
+/* Used by PRM_RSTCTRL */
+#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT			1
+#define AM33XX_RST_GLOBAL_COLD_SW_MASK			(1 << 1)
+
+/* Used by PRM_RSTCTRL */
+#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT			0
+#define AM33XX_RST_GLOBAL_WARM_SW_MASK			(1 << 0)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_SLPCNT_VALUE_SHIFT			16
+#define AM33XX_SLPCNT_VALUE_MASK			(0xff << 16)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_SRAMLDO_STATUS_SHIFT			8
+#define AM33XX_SRAMLDO_STATUS_MASK			(1 << 8)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_SRAM_IN_TRANSITION_SHIFT			9
+#define AM33XX_SRAM_IN_TRANSITION_MASK			(1 << 9)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_STARTUP_COUNT_SHIFT			24
+#define AM33XX_STARTUP_COUNT_MASK			(0xff << 24)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_TRANSITION_EN_SHIFT			8
+#define AM33XX_TRANSITION_EN_MASK			(1 << 8)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_TRANSITION_ST_SHIFT			8
+#define AM33XX_TRANSITION_ST_MASK			(1 << 8)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_VSETUPCNT_VALUE_SHIFT			8
+#define AM33XX_VSETUPCNT_VALUE_MASK			(0xff << 8)
+
+/* Used by PRM_RSTST */
+#define AM33XX_WDT0_RST_SHIFT				3
+#define AM33XX_WDT0_RST_MASK				(1 << 3)
+
+/* Used by PRM_RSTST */
+#define AM33XX_WDT1_RST_SHIFT				4
+#define AM33XX_WDT1_RST_MASK				(1 << 4)
+
+/* Used by RM_WKUP_RSTCTRL */
+#define AM33XX_WKUP_M3_LRST_SHIFT			3
+#define AM33XX_WKUP_M3_LRST_MASK			(1 << 3)
+
+/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
+#define AM33XX_WKUP_M3_LRST_5_5_SHIFT			5
+#define AM33XX_WKUP_M3_LRST_5_5_MASK			(1 << 5)
+
+#endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
new file mode 100644
index 0000000..7444855
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -0,0 +1,134 @@
+/*
+ * AM33XX PRM functions
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "common.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+/* Read a register in a PRM instance */
+u32 am33xx_prm_read_reg(s16 inst, u16 idx)
+{
+	return __raw_readl(prm_base + inst + idx);
+}
+
+/* Write into a register in a PRM instance */
+void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
+{
+	__raw_writel(val, prm_base + inst + idx);
+}
+
+/* Read-modify-write a register in PRM. Caller must lock */
+u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(inst, idx);
+	v &= ~mask;
+	v |= bits;
+	am33xx_prm_write_reg(v, inst, idx);
+
+	return v;
+}
+
+/**
+ * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @shift: register bit shift corresponding to the reset line to check
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_offs: RM_RSTCTRL register address offset for this module
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL upon parameter error.
+ */
+int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
+{
+	u32 v;
+
+	v = am33xx_prm_read_reg(inst, rstctrl_offs);
+	v &= 1 << shift;
+	v >>= shift;
+
+	return v;
+}
+
+/**
+ * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
+ * @shift: register bit shift corresponding to the reset line to assert
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
+{
+	u32 mask = 1 << shift;
+
+	am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
+
+	return 0;
+}
+
+/**
+ * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
+ * wait
+ * @shift: register bit shift corresponding to the reset line to deassert
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @rstst_reg: RM_RSTST register address for this module
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+		u16 rstctrl_offs, u16 rstst_offs)
+{
+	int c;
+	u32 mask = 1 << shift;
+
+	/* Check the current status to avoid  de-asserting the line twice */
+	if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
+		return -EEXIST;
+
+	/* Clear the reset status by writing 1 to the status bit */
+	am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
+	/* de-assert the reset control line */
+	am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
+	/* wait the status to be set */
+
+	omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
+				rstst_offs), MAX_MODULE_HARDRESET_WAIT, c);
+
+	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
new file mode 100644
index 0000000..3f25c56
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -0,0 +1,129 @@
+/*
+ * AM33XX PRM instance offset macros
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+
+#define AM33XX_PRM_BASE               0x44E00000
+
+#define AM33XX_PRM_REGADDR(inst, reg)                         \
+	AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define AM33XX_PRM_OCP_SOCKET_MOD	0x0B00
+#define AM33XX_PRM_PER_MOD		0x0C00
+#define AM33XX_PRM_WKUP_MOD		0x0D00
+#define AM33XX_PRM_MPU_MOD		0x0E00
+#define AM33XX_PRM_DEVICE_MOD		0x0F00
+#define AM33XX_PRM_RTC_MOD		0x1000
+#define AM33XX_PRM_GFX_MOD		0x1100
+#define AM33XX_PRM_CEFUSE_MOD		0x1200
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define AM33XX_REVISION_PRM_OFFSET		0x0000
+#define AM33XX_REVISION_PRM			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
+#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET		0x0004
+#define AM33XX_PRM_IRQSTATUS_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
+#define AM33XX_PRM_IRQENABLE_MPU_OFFSET		0x0008
+#define AM33XX_PRM_IRQENABLE_MPU		AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
+#define AM33XX_PRM_IRQSTATUS_M3_OFFSET		0x000c
+#define AM33XX_PRM_IRQSTATUS_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
+#define AM33XX_PRM_IRQENABLE_M3_OFFSET		0x0010
+#define AM33XX_PRM_IRQENABLE_M3			AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
+
+/* PRM.PER_PRM register offsets */
+#define AM33XX_RM_PER_RSTCTRL_OFFSET		0x0000
+#define AM33XX_RM_PER_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
+#define AM33XX_RM_PER_RSTST_OFFSET		0x0004
+#define AM33XX_RM_PER_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
+#define AM33XX_PM_PER_PWRSTST_OFFSET		0x0008
+#define AM33XX_PM_PER_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
+#define AM33XX_PM_PER_PWRSTCTRL_OFFSET		0x000c
+#define AM33XX_PM_PER_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
+
+/* PRM.WKUP_PRM register offsets */
+#define AM33XX_RM_WKUP_RSTCTRL_OFFSET		0x0000
+#define AM33XX_RM_WKUP_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
+#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET		0x0004
+#define AM33XX_PM_WKUP_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
+#define AM33XX_PM_WKUP_PWRSTST_OFFSET		0x0008
+#define AM33XX_PM_WKUP_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
+#define AM33XX_RM_WKUP_RSTST_OFFSET		0x000c
+#define AM33XX_RM_WKUP_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
+
+/* PRM.MPU_PRM register offsets */
+#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET		0x0000
+#define AM33XX_PM_MPU_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
+#define AM33XX_PM_MPU_PWRSTST_OFFSET		0x0004
+#define AM33XX_PM_MPU_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
+#define AM33XX_RM_MPU_RSTST_OFFSET		0x0008
+#define AM33XX_RM_MPU_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
+
+/* PRM.DEVICE_PRM register offsets */
+#define AM33XX_PRM_RSTCTRL_OFFSET		0x0000
+#define AM33XX_PRM_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
+#define AM33XX_PRM_RSTTIME_OFFSET		0x0004
+#define AM33XX_PRM_RSTTIME			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
+#define AM33XX_PRM_RSTST_OFFSET			0x0008
+#define AM33XX_PRM_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
+#define AM33XX_PRM_SRAM_COUNT_OFFSET		0x000c
+#define AM33XX_PRM_SRAM_COUNT			AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET	0x0010
+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET	0x0014
+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET	0x0018
+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET	0x001c
+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
+
+/* PRM.RTC_PRM register offsets */
+#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET		0x0000
+#define AM33XX_PM_RTC_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
+#define AM33XX_PM_RTC_PWRSTST_OFFSET		0x0004
+#define AM33XX_PM_RTC_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
+
+/* PRM.GFX_PRM register offsets */
+#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET		0x0000
+#define AM33XX_PM_GFX_PWRSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
+#define AM33XX_RM_GFX_RSTCTRL_OFFSET		0x0004
+#define AM33XX_RM_GFX_RSTCTRL			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
+#define AM33XX_PM_GFX_PWRSTST_OFFSET		0x0010
+#define AM33XX_PM_GFX_PWRSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
+#define AM33XX_RM_GFX_RSTST_OFFSET		0x0014
+#define AM33XX_RM_GFX_RSTST			AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
+
+/* PRM.CEFUSE_PRM register offsets */
+#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET	0x0000
+#define AM33XX_PM_CEFUSE_PWRSTCTRL		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
+#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET		0x0004
+#define AM33XX_PM_CEFUSE_PWRSTST		AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
+
+extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
+extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
+extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+extern void am33xx_prm_global_warm_sw_reset(void);
+extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
+		u16 rstctrl_offs);
+extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
+extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+		u16 rstctrl_offs, u16 rstst_offs);
+#endif
--
1.7.0.4



From tony at atomide.com  Fri Mar 30 12:11:31 2012
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 30 Mar 2012 09:11:31 -0700
Subject: [PATCH 03/17] ARM: mark const init data with __initconst
 instead of __initdata
In-Reply-To: <1333055554-31300-3-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20120329211131.GA31250@pengutronix.de>
 <1333055554-31300-3-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20120330161130.GA8240@atomide.com>

* Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de> [120329 14:16]:
> As long as there is no other non-const variable marked __initdata in the
> same compilation unit it doesn't hurt. If there were one however
> compilation would fail with
> 
> 	error: $variablename causes a section type conflict
> 
> because a section containing const variables is marked read only and so
> cannot contain non-const variables.

Acked-by: Tony Lindgren <tony at atomide.com>


From hvaibhav at ti.com  Fri Mar 30 12:22:07 2012
From: hvaibhav at ti.com (Hiremath, Vaibhav)
Date: Fri, 30 Mar 2012 16:22:07 +0000
Subject: [PATCH-V4 0/4] ARM: OMAP2+: Add voltagedomain, powerdomain &
 PRM support for AM33XX device
In-Reply-To: <1333123435-27186-1-git-send-email-hvaibhav@ti.com>
References: <1333123435-27186-1-git-send-email-hvaibhav@ti.com>
Message-ID: <79CD15C6BA57404B839C016229A409A831841943@DBDE01.ent.ti.com>

On Fri, Mar 30, 2012 at 21:33:51, Hiremath, Vaibhav wrote:
> After some healthy discussion, now we have come to the conclusion and
> decided to handle AM33XX PRM/CM part separately; as AM33XX-PRCM module is
> different than OMAP3 and OMAP4 architecture.
> 
> The difference becomes very interesting/weird when it comes to
> the consistency for register offsets in PRM address space and
> bit-field offsets inside PRM registers,
> So along with Powerdomain data and PRM api's required for AM33XX
> device, this patch series adds,
> 
>  - XXX_RSTST register offset to "struct omap_hwmod_omap4_prcm"
>  - PWRSTCTRL & PWRSTST register offsets to "struct powerdomain"
>  - Logicretstate and mem_on/ret/pwrst/retst mask to "struct
>    powerdomain"
> 
> Testing: This patch series has been boot tested on AM37xEVM and AM335x
>          based BeagleBone community board.
> 
> Thanks to Paul here...for helping and concluding on this,
> shortly I will submit similar patch for CM, clockdomain and clock-tree
> support for AM33xx.
> 
> This patch-series is created on top of "linux-omap/cleanup" branch, and
> also gets applied to "linux-omap/master" branch.
> The patches are also available at -
> https://github.com/hvaibhav/am335x-linux/tree/am335x-prm-cm
> 

Please use "am335x-upstream-staging" branch, to able to boot on BeagleBone
board, due to missing clock & hwmod data.

I am in the process of submitting these patches.

Thanks,
Vaibhav




From swarren at wwwdotorg.org  Fri Mar 30 12:23:26 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 10:23:26 -0600
Subject: [PATCH] pinctrl: Replace list_*() with get_*_count()
In-Reply-To: <10b8e68e37a8992646e9b84521ec48953612d83c.1333086742.git.viresh.kumar@st.com>
References: <10b8e68e37a8992646e9b84521ec48953612d83c.1333086742.git.viresh.kumar@st.com>
Message-ID: <4F75DDFE.3030408@wwwdotorg.org>

On 03/29/2012 11:55 PM, Viresh Kumar wrote:
> Most of the SoC drivers implement list_groups() and list_functions() routines
> for pinctrl and pinmux. These routines continue returning zero until the
> selector argument is greater than total count of available groups or functions.
> 
> This patch replaces these list_*() routines with get_*_count() routines, which
> returns the number of available selection for SoC driver. pinctrl layer will use
> this value to check the range it can choose.
> 
> This patch fixes all user drivers for this change. There are other routines in
> user drivers, which have checks to check validity of selector passed to them. It
> is also no more required and hence removed.
> 
> Documentation updated as well.
> 
> Signed-off-by: Viresh Kumar <viresh.kumar at st.com>

This looks fine to me, so:

Acked-by: Stephen Warren <swarren at wwwdotorg.org>

One small issue to fix though: In pinctrl-tegra.c, you've removed all
the range-checkes from the ops functions, except you forgot to update
tegra_pinctrl_disable().

This is simple enough I don't think I need to test it; it doesn't
actually apply to my local tree since it conflicts with all the pinctrl
DT work I have.


From will.deacon at arm.com  Fri Mar 30 12:55:36 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 30 Mar 2012 17:55:36 +0100
Subject: [PATCH v4 0/3] ARM support for syscall tracing
In-Reply-To: <4F6C8DAE.9070209@mentor.com>
References: <4F44FF58.3060907@mentor.com> <4F4E3780.4060904@mentor.com>
 <4F54D0D4.7070905@mentor.com> <4F6C8DAE.9070209@mentor.com>
Message-ID: <20120330165536.GC11451@mudshark.cambridge.arm.com>

Hi Wade,

On Fri, Mar 23, 2012 at 02:50:22PM +0000, Wade Farnsworth wrote:
> Russell, now that this has been reviewed by Will and tested with both
> ABIs, is this okay to submit to your patch tracker?

I'd recommend putting this into the patch system once -rc1 has landed.
Any conflicts after that are fairly unlikely and Russell can decide what
to do with the patches then.

Cheers,

Will


From will.deacon at arm.com  Fri Mar 30 13:04:01 2012
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 30 Mar 2012 18:04:01 +0100
Subject: [PATCH] ARM: test for PMU feature on v7 (v2 with typo fix)
In-Reply-To: <alpine.LFD.2.02.1203281005110.24151@xanadu.home>
References: <4F590411.9060201@arm.com> <87ty1g88dv.fsf@rustcorp.com.au>
 <87r4wk889a.fsf@rustcorp.com.au>
 <20120323095314.GA13622@mudshark.cambridge.arm.com>
 <87fwcy9abw.fsf@rustcorp.com.au>
 <20120326094054.GA2475@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1203281005110.24151@xanadu.home>
Message-ID: <20120330170401.GD11451@mudshark.cambridge.arm.com>

Hi Nicolas,

On Wed, Mar 28, 2012 at 03:17:29PM +0100, Nicolas Pitre wrote:
> On Mon, 26 Mar 2012, Will Deacon wrote:
> 
> > Now, if everything was device-tree based then we could simply use a
> > different binding for each CPU but since we support perf on non-DT
> > platforms, probing the CPU type is the best solution. I would like to avoid
> > the probing code if we are initialised from DT, but I've not got round to it
> > yet (this would be useful for big.LITTLE).
> 
> Still... my opinion is that we should try to autodetect as much as 
> possible and avoid overstuffing the DT with content that can otherwise 
> be run-time probed.  OK to use DT to override the probe for corner 
> cases, but IMHO the probe should be the default method of 
> initialization.  The rational is that we want to spread knowledge about 
> part of the system and have it confined into respective drivers and 
> subsystems for easier maintenance.  If the guy who has to maintain the 
> dts has to know all the details for everything then that won't scale and 
> the risk for discrepancies is increased.

I agree that probing is preferable where possible but, since the PMUs are
banked, we cannot reliably probe them on big.LITTLE platforms. I guess if
there were some infrastructure for probing on the remote cluster, I could
use that, but it seems like DT would be easier.

Will


From konkers at google.com  Fri Mar 30 13:29:27 2012
From: konkers at google.com (Erik Gilling)
Date: Fri, 30 Mar 2012 10:29:27 -0700
Subject: [PATCH v6 1/5] Extcon (external connector): import Android's
 switch class and modify.
In-Reply-To: <20120330100742.GB21950@opensource.wolfsonmicro.com>
References: <1328856038-21912-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-2-git-send-email-myungjoo.ham@samsung.com>
 <20120309124119.GV3273@opensource.wolfsonmicro.com>
 <CACSP8ShU5tu=9N53PtYMLyFVFMS9whNRhMvu7nu8rBoPuVCy+Q@mail.gmail.com>
 <20120330100742.GB21950@opensource.wolfsonmicro.com>
Message-ID: <CACSP8SjhOZcXZa2hCNsH8zS+hm8X-i9uNm50UH=_VwOV=BJGmA@mail.gmail.com>

On Fri, Mar 30, 2012 at 3:07 AM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Thu, Mar 29, 2012 at 03:27:01PM -0700, Erik Gilling wrote:
>> On Fri, Mar 9, 2012 at 4:41 AM, Mark Brown
>
>> > This seems somewhat sad - if ANDROID is turned on the standard ABI
>> > vanishes. ?It'd be much nicer to do this with a symlink (or with
>> > symlinks within the android directory if the driver core doesn't support
>> > that). ?That way userspace code can be written to the new ABI and will
>> > work on Android systems without ifdefery.
>
>> This won't work if userspace code is receiving uevents through netlink
>> and comparing based on the device name which it does in android. ?Why
>
> That's not really the point here - the point is that the new ABI
> vanishes as soon as you turn on the legacy Android ABI. ?You're right
> that the particular fix I suggested has issues but the overall problem
> exists and should be dealt with more sensibly.

I'm also not in favor of having functionality conditionally compiled
based on CONFIG_ANDROID.  If fact, going through the patch stack
there's much more that changes the ABI from the switch driver than
just the name.  Android asumes that there is a single "switch" for
each logical entity (called cable types in extcon) each with a binary
state (0,1).  Here things have changed to have a single extcon
instance that can have a bitmask of states which are sent as strings
in the uevent.

As it stands, this patch does not solve the cases where we use switch
today and we'll probably continue to carry the switch driver in the
common android tree.  If, instead, we got rid of the idea of multiple
states and mutual exclusivity and relied on the driver that uses
extcon to have multiple instances for each logical entity and deal
with mutual exclusion itself, we'd have a driver that would be pretty
easy to support in android.

-Erik


From dima at android.com  Fri Mar 30 13:38:30 2012
From: dima at android.com (Dima Zavin)
Date: Fri, 30 Mar 2012 10:38:30 -0700
Subject: [PATCH v6 1/5] Extcon (external connector): import Android's
 switch class and modify.
In-Reply-To: <CACSP8SjhOZcXZa2hCNsH8zS+hm8X-i9uNm50UH=_VwOV=BJGmA@mail.gmail.com>
References: <1328856038-21912-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-2-git-send-email-myungjoo.ham@samsung.com>
 <20120309124119.GV3273@opensource.wolfsonmicro.com>
 <CACSP8ShU5tu=9N53PtYMLyFVFMS9whNRhMvu7nu8rBoPuVCy+Q@mail.gmail.com>
 <20120330100742.GB21950@opensource.wolfsonmicro.com>
 <CACSP8SjhOZcXZa2hCNsH8zS+hm8X-i9uNm50UH=_VwOV=BJGmA@mail.gmail.com>
Message-ID: <CAPz4a6C9J+7pSHsCabdtF8pXgx7msFDjYNBi2KviHuSShXWuZQ@mail.gmail.com>

On Fri, Mar 30, 2012 at 10:29 AM, Erik Gilling <konkers at google.com> wrote:
> On Fri, Mar 30, 2012 at 3:07 AM, Mark Brown
> <broonie at opensource.wolfsonmicro.com> wrote:
>> On Thu, Mar 29, 2012 at 03:27:01PM -0700, Erik Gilling wrote:
>>> On Fri, Mar 9, 2012 at 4:41 AM, Mark Brown
>>
>>> > This seems somewhat sad - if ANDROID is turned on the standard ABI
>>> > vanishes. ?It'd be much nicer to do this with a symlink (or with
>>> > symlinks within the android directory if the driver core doesn't support
>>> > that). ?That way userspace code can be written to the new ABI and will
>>> > work on Android systems without ifdefery.
>>
>>> This won't work if userspace code is receiving uevents through netlink
>>> and comparing based on the device name which it does in android. ?Why
>>
>> That's not really the point here - the point is that the new ABI
>> vanishes as soon as you turn on the legacy Android ABI. ?You're right
>> that the particular fix I suggested has issues but the overall problem
>> exists and should be dealt with more sensibly.
>
> I'm also not in favor of having functionality conditionally compiled
> based on CONFIG_ANDROID. ?If fact, going through the patch stack
> there's much more that changes the ABI from the switch driver than
> just the name. ?Android asumes that there is a single "switch" for
> each logical entity (called cable types in extcon) each with a binary
> state (0,1). ?Here things have changed to have a single extcon
> instance that can have a bitmask of states which are sent as strings
> in the uevent.

In addition to all this added complexity, the fact that you now have
to white-list the possible "cable types" is also undesirable. If I
wanted to expose a new cable type, I now have to modify the extcon.h
file and the extcon.c file and I don't see what that white-list buys
me. The class device itself should not care for which cable types can
be registered, nor how they relate to each other. Let the client
drivers decide, just enforce uniqueness.

--Dima

>
> As it stands, this patch does not solve the cases where we use switch
> today and we'll probably continue to carry the switch driver in the
> common android tree. ?If, instead, we got rid of the idea of multiple
> states and mutual exclusivity and relied on the driver that uses
> extcon to have multiple instances for each logical entity and deal
> with mutual exclusion itself, we'd have a driver that would be pretty
> easy to support in android.
>
> -Erik


From grinberg at compulab.co.il  Fri Mar 30 13:59:51 2012
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Fri, 30 Mar 2012 20:59:51 +0300
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <1333122733.41820.YahooMailClassic@web29002.mail.ird.yahoo.com>
References: <1333122733.41820.YahooMailClassic@web29002.mail.ird.yahoo.com>
Message-ID: <4F75F497.50909@compulab.co.il>

On 03/30/12 18:52, Paul Parsons wrote:
> --- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il> wrote:
>> On 03/30/12 18:06, Paul Parsons wrote:
>>> --- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il>
>> wrote:
>>>> On 03/28/12 20:12, Paul Parsons
>>>> wrote:
>>>>> On PXA2xx platforms, the MFP API (described in
>>>> Documentation/arm/pxa/mfp.txt)
>>>>> provides values for the following:
>>>>>
>>>>> 1. GPIO inputs (e.g. GPIO105_GPIO).
>>>>> 2. Alternate function inputs (e.g.
>> GPIO105_CIF_DD_1).
>>>>> 3. Alternate function outputs (e.g.
>>>> GPIO105_KP_MKOUT_2).
>>>>>
>>>>> It does not provide values for GPIO outputs
>> (i.e. AF0
>>>> outputs).
>>>>>
>>>>> One cannot use the macro used by the MFP API
>> internally
>>>> - MFP_CFG_OUT() - to
>>>>> define new GPIO output values, since that macro
>> is
>>>> forbidden in platform code.
>>>>>
>>>>> Without the ability to add GPIO outputs to the
>> MFP
>>>> configuration, it is not
>>>>> possible to drive GPIO outputs high during
>> sleep mode.
>>>>>
>>>>> This would be useful, for example, on the
>> hx4700
>>>> platform, where driving the
>>>>> infrared powerdown GPIO 105 high during sleep
>> mode
>>>> would save some mA.
>>>>>
>>>>> So my question is: what method should one use
>> to add
>>>> GPIO outputs to the MFP
>>>>> configuration?
>>>>>
>>>>> One possible method, namely manually defining
>> values in
>>>> the platform code:
>>>>>
>>>>>      MFP_PIN_GPIO105 |
>> MFP_AF0 |
>>>> MFP_DIR_OUT | MFP_LPM_DRIVE_HIGH,
>>>>
>>>> Have you tried:
>>>> GPIO105_GPIO | MFP_LPM_DRIVE_HIGH,
>>>> ?
>>>>
>>>> This way it works on other boards.
>>>
>>> Hello Igor,
>>>
>>> GPIO105_GPIO expands to a GPIO input -
>> MFP_CFG_IN(GPIO105, AF0) -
>>> not an output.
>>
>> Yeah, I know... but read in mfp-pxa2xx.h, lines 6-20:
>> /*
>>  * the following MFP_xxx bit definitions in mfp.h are
>> re-used for pxa2xx:
>>  *
>>  *  MFP_PIN(x)
>>  *  MFP_AFx
>>  *  MFP_LPM_DRIVE_{LOW, HIGH}
>>  *  MFP_LPM_EDGE_x
>>  *
>>  * other MFP_x bit definitions will be ignored
>>  *
>>  * and adds the below two bits specifically for pxa2xx:
>>  *
>>  * bit     23 - Input/Output (PXA2xx
>> specific)
>>  * bit     24 - Wakeup Enable(PXA2xx
>> specific)
>>  */
>>
>> This means, that there is no difference between: MFP_CFG_IN
>> and MFP_CFG_OUT for PXA2xx.
> 
> The mfp-pxa2xx.c code says otherwise.

That's just great... outdated documentation...

> It uses the MFP direction bit
> to set the GPDR registers on entering sleep mode:
> 
>    353	static int pxa2xx_mfp_suspend(void)
>    354	{
>    355		int i;
>         ...
>    368		for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
>    369	
>         ...
>    375			GPDR(i * 32) = gpdr_lpm[i];
>    376		}
>    377		return 0;
>    378	}
> 
> gpdr_lpm[] is initialized at startup to the current GPDR values, and
> thereafter is updated by the value of the MFP_DIR_OUT bit in calls to
> __mfp_config_gpio().

static int __mfp_config_gpio(unsigned gpio, unsigned long c)
{
	unsigned long gafr, mask = GPIO_bit(gpio);
	int bank = gpio_to_bank(gpio);
	int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */
	int shft = (gpio & 0xf) << 1;
	int fn = MFP_AF(c);
	int is_out = (c & MFP_DIR_OUT) ? 1 : 0;

[...]

	/* alternate function and direction at low power mode */
	switch (c & MFP_LPM_STATE_MASK) {
	case MFP_LPM_DRIVE_HIGH:
		PGSR(bank) |= mask;
		is_out = 1;
		break;
	case MFP_LPM_DRIVE_LOW:
		PGSR(bank) &= ~mask;
		is_out = 1;
		break;

And in the lines above, it gets overridden by MFP_LPM_DRIVE_*,
or am I missing something?
[...]

	if (is_out ^ gpio_desc[gpio].dir_inverted)
		gpdr_lpm[bank] |= mask;
	else
		gpdr_lpm[bank] &= ~mask;


So, I think,
GPIO105_GPIO | MFP_LPM_DRIVE_HIGH,
as I've proposed in my first email, should still work for you.

-- 
Regards,
Igor.


From linux at arm.linux.org.uk  Fri Mar 30 14:01:34 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 30 Mar 2012 19:01:34 +0100
Subject: [PATCH] ARM: amba: adapt to regulator probe deferral change
In-Reply-To: <1333115737-1654-1-git-send-email-shawn.guo@linaro.org>
References: <1333115737-1654-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120330180134.GJ22981@n2100.arm.linux.org.uk>

On Fri, Mar 30, 2012 at 09:55:37PM +0800, Shawn Guo wrote:
> The commit 04bf301 (regulator: Support driver probe deferral) changes
> regulator_get() and regulator_register() to return -EPROBE_DEFER
> instead of -ENODEV.  Adapt amba bus driver to the change, otherwise
> amba_probe() will fail on the platforms that do not have "vcore"
> regulator device.

Are you sure this is correct?  Did you read and understand the comment
you removed?

What do platforms do which have AMBA devices but don't have any vcore
regulators?

We're not going through the same farce that the smsc network driver has
gone through: OMAP3430LDP remains fucked through that idiotic ill-thought
out change (c7e963f68888, net/smsc911x: Add regulator support).  See
http://www.arm.linux.org.uk/developer/build/result.php?type=boot&idx=99


From nico at fluxnic.net  Fri Mar 30 13:40:59 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 30 Mar 2012 13:40:59 -0400 (EDT)
Subject: [PATCH] ARM: test for PMU feature on v7 (v2 with typo fix)
In-Reply-To: <20120330170401.GD11451@mudshark.cambridge.arm.com>
References: <4F590411.9060201@arm.com> <87ty1g88dv.fsf@rustcorp.com.au>
 <87r4wk889a.fsf@rustcorp.com.au>
 <20120323095314.GA13622@mudshark.cambridge.arm.com>
 <87fwcy9abw.fsf@rustcorp.com.au>
 <20120326094054.GA2475@mudshark.cambridge.arm.com>
 <alpine.LFD.2.02.1203281005110.24151@xanadu.home>
 <20120330170401.GD11451@mudshark.cambridge.arm.com>
Message-ID: <alpine.LFD.2.02.1203301336480.24151@xanadu.home>

On Fri, 30 Mar 2012, Will Deacon wrote:

> Hi Nicolas,
> 
> On Wed, Mar 28, 2012 at 03:17:29PM +0100, Nicolas Pitre wrote:
> > On Mon, 26 Mar 2012, Will Deacon wrote:
> > 
> > > Now, if everything was device-tree based then we could simply use a
> > > different binding for each CPU but since we support perf on non-DT
> > > platforms, probing the CPU type is the best solution. I would like to avoid
> > > the probing code if we are initialised from DT, but I've not got round to it
> > > yet (this would be useful for big.LITTLE).
> > 
> > Still... my opinion is that we should try to autodetect as much as 
> > possible and avoid overstuffing the DT with content that can otherwise 
> > be run-time probed.  OK to use DT to override the probe for corner 
> > cases, but IMHO the probe should be the default method of 
> > initialization.  The rational is that we want to spread knowledge about 
> > part of the system and have it confined into respective drivers and 
> > subsystems for easier maintenance.  If the guy who has to maintain the 
> > dts has to know all the details for everything then that won't scale and 
> > the risk for discrepancies is increased.
> 
> I agree that probing is preferable where possible but, since the PMUs are
> banked, we cannot reliably probe them on big.LITTLE platforms.

Are they tied to each cluster power domains?  If so you'll have to 
preserve/restore their state when clusters are suspended even if the 
interface tries to present a consistent view to users.  The probe can be 
done there, and differences in capabilities adjusted dynamically.


Nicolas


From paul.gortmaker at windriver.com  Fri Mar 30 14:42:30 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Fri, 30 Mar 2012 14:42:30 -0400
Subject: [PATCH] ARM: imx: fix compile error on missing arm_pm_idle
Message-ID: <1333132950-28357-1-git-send-email-paul.gortmaker@windriver.com>

This shows up in imx_v6_v7_defconfig build:

arch/arm/mach-imx/mm-imx3.c: In function 'imx31_init_early':
arch/arm/mach-imx/mm-imx3.c:138: error: 'arm_pm_idle' undeclared
arch/arm/mach-imx/mm-imx5.c: In function 'imx51_init_early':
arch/arm/mach-imx/mm-imx5.c:105: error: 'arm_pm_idle' undeclared
arch/arm/mach-imx/mm-imx3.c: In function 'imx35_init_early':
arch/arm/mach-imx/mm-imx3.c:210: error: 'arm_pm_idle' undeclared
arch/arm/mach-imx/mm-imx5.c: In function 'imx51_init_early':
arch/arm/mach-imx/mm-imx5.c:105: error: 'arm_pm_idle' undeclared

Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>

diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index d534d7f..7412738 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -21,6 +21,7 @@
 #include <linux/err.h>
 
 #include <asm/pgtable.h>
+#include <asm/system_misc.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 51af9fa..05250ae 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 
+#include <asm/system_misc.h>
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
-- 
1.7.9.1



From arnd at arndb.de  Fri Mar 30 14:45:07 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 30 Mar 2012 18:45:07 +0000
Subject: [PATCH v3 6/6] mmc: sdhci-s3c: Add device tree support
In-Reply-To: <4F75D5C0.5050307@wwwdotorg.org>
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>
 <201203301136.05038.arnd@arndb.de> <4F75D5C0.5050307@wwwdotorg.org>
Message-ID: <201203301845.07534.arnd@arndb.de>

On Friday 30 March 2012, Stephen Warren wrote:
> That property looks very reasonable.
> 
> Question: This would be a non-backwards-compatible change to the binding
> definition. How should this be handled? In the past, I believe it's been
> stated that new kernels need to run against old device trees, and hence
> once a DT binding was defined and in use, it couldn't change except in a
> backwards-compatible way. However, more recently, Grant has said that
> his opinion is that (some or all?) bindings are currently considered
> experimental and subject to change. And besides, the .dts files are
> contained in the kernel tree at present... Some generally stated and
> agreed upon policy here might be useful.

I tried to leave the ones that look like they've been around for a while
backwards compatible (gpio, esdhc), while changing the relatively new
ones without backwards compatibility code.

> > +Optional properties:
> > +- cd-gpios : Specify GPIOs for card detection, see gpio binding
> > +- wp-gpios : Specify GPIOs for write protection, see gpio binding
> 
> > +- cd-inverted: when present, polarity on the wp gpio line is inverted
> > +- wp-inverted: when present, polarity on the wp gpio line is inverted
> 
> I'm not sure about those two: Some of the GPIO bindings have flags in
> the GPIO specifier (Tegra, ARM PL061, gpio.txt mentions the possibility
> of polarity being in the specifier), and bit 0 of the flags is used to
> indicate inversion. I think that either we should rely on GPIO
> specifiers having such flags and remove these xxx-inverted properties
> from the MMC binding, or remove that flag bit from the GPIO bindings.

Maybe the GPIO maintainer can comment on this. My understanding is
that not all gpio controllers support this in their bindings. If they
do, I agree that we can remove the extra properties here.

> Note that anything using of_gpio_simple_xlate() is going to end up using
> the GPIO flag definitions from <linux/of_gpio.h> in their GPIO
> specifier, and there a number of active users of this feature; grep for
> OF_GPIO_ACTIVE_LOW.
> 
> The rather begs the question why of_get_named_gpio() exists; surely
> of_get_named_gpio_flags() should always be used so that consumers know
> whether the GPIO value should be inverted, or are the GPIO flags
> supposed to be processed by the OF/GPIO core or GPIO driver somehow, and
> act transparently to GPIO consumers?
> 
> > diff --git a/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt
> ...
> > -- interrupts : Should contain SD/MMC interrupt
> > +- interrupt  : Should contain SD/MMC interrupt
> 
> Isn't that usually pluralized, so interrupts?

Right, my mistake.

> > +- bus-width : Number of data lines, can be <1>, <4>, or <8>
> 
> For the device-specific binding documentation, rather than repeating the
> core bindings, shouldn't we say something like:
> 
> This binding is based on the core MMC bindings documented in mmc.txt.
> This file only documents additions or changes to those bindings.
> 
> ... and then remove any of the common properties from the individual files?

yes, good idea.

> > diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
> ...
> > @@ -66,5 +67,6 @@
> >  
> >       sdhci at 78000400 {
> >               support-8bit;
> > +             bus-width = <8>;
> >       };
> >  };
> 
> Ah OK, so the first phase is to add all the new standardize properties,
> then later remove all the legacy properties once the drivers have been
> updated.
> 
> You've missed additions of "non-removable", but I can add them later. or
> provide you an incremental patch or something.
> 
> > diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
> 
> This doesn't seem to decode cd-inverted, or do anything with the
> bus-width property value that it reads. Was that intentional?

For now, I was trying to get the binding document right. I suppose as a follow-up,
we can actually add a common helper function to decode these attributes and set
the right flag in the mmc device, but that is not urgent. Right now, I mainly
want to make sure we gain no new users that have conflicting bindings.

	Arnd



From paul.gortmaker at windriver.com  Fri Mar 30 14:51:05 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Fri, 30 Mar 2012 14:51:05 -0400
Subject: [PATCH] ARM: imx: fix compile error on missing arm_pm_idle
In-Reply-To: <1333132950-28357-1-git-send-email-paul.gortmaker@windriver.com>
References: <1333132950-28357-1-git-send-email-paul.gortmaker@windriver.com>
Message-ID: <4F760099.6040105@windriver.com>

On 12-03-30 02:42 PM, Paul Gortmaker wrote:
> This shows up in imx_v6_v7_defconfig build:

Ignore this patch.  I see Olof has already fixed them in bulk.

http://marc.info/?l=linux-arm-kernel&m=133311840811220&w=2

Thanks,
Paul.

> 
> arch/arm/mach-imx/mm-imx3.c: In function 'imx31_init_early':
> arch/arm/mach-imx/mm-imx3.c:138: error: 'arm_pm_idle' undeclared
> arch/arm/mach-imx/mm-imx5.c: In function 'imx51_init_early':
> arch/arm/mach-imx/mm-imx5.c:105: error: 'arm_pm_idle' undeclared
> arch/arm/mach-imx/mm-imx3.c: In function 'imx35_init_early':
> arch/arm/mach-imx/mm-imx3.c:210: error: 'arm_pm_idle' undeclared
> arch/arm/mach-imx/mm-imx5.c: In function 'imx51_init_early':
> arch/arm/mach-imx/mm-imx5.c:105: error: 'arm_pm_idle' undeclared
> 
> Signed-off-by: Paul Gortmaker <paul.gortmaker at windriver.com>
> 
> diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
> index d534d7f..7412738 100644
> --- a/arch/arm/mach-imx/mm-imx3.c
> +++ b/arch/arm/mach-imx/mm-imx3.c
> @@ -21,6 +21,7 @@
>  #include <linux/err.h>
>  
>  #include <asm/pgtable.h>
> +#include <asm/system_misc.h>
>  #include <asm/hardware/cache-l2x0.h>
>  #include <asm/mach/map.h>
>  
> diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
> index 51af9fa..05250ae 100644
> --- a/arch/arm/mach-imx/mm-imx5.c
> +++ b/arch/arm/mach-imx/mm-imx5.c
> @@ -15,6 +15,7 @@
>  #include <linux/init.h>
>  #include <linux/clk.h>
>  
> +#include <asm/system_misc.h>
>  #include <asm/mach/map.h>
>  
>  #include <mach/hardware.h>


From swarren at wwwdotorg.org  Fri Mar 30 14:57:18 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 12:57:18 -0600
Subject: [PATCH v5 08/16] pwm: Add NVIDIA Tegra SoC support
In-Reply-To: <1332945238-14897-9-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-9-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F76020E.30207@wwwdotorg.org>

On 03/28/2012 08:33 AM, Thierry Reding wrote:
> This commit adds a generic PWM framework driver for the PWFM controller
> found on NVIDIA Tegra SoCs. The driver is based on code from the
> Chromium kernel tree and was originally written by Gary King (NVIDIA)
> and later modified by Simon Que (Chromium).
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>

Acked-by: Stephen Warren <swarren at wwwdotorg.org>


From swarren at wwwdotorg.org  Fri Mar 30 15:00:29 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 13:00:29 -0600
Subject: [PATCH v5 09/16] pwm: tegra: Add device tree support
In-Reply-To: <1332945238-14897-10-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-10-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F7602CD.2010808@wwwdotorg.org>

On 03/28/2012 08:33 AM, Thierry Reding wrote:
> Add auxdata to instantiate the PWFM controller from a device tree,
> include the corresponding nodes in the dtsi files for Tegra 20 and
> Tegra 30 and add binding documentation.
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>
> Acked-by: Stephen Warren <swarren at wwwdotorg.org>

> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
...
> +#ifdef CONFIG_OF
> +static struct of_device_id tegra_pwm_of_match[] = {
> +	{ .compatible = "nvidia,tegra20-pwm" },
> +	{ .compatible = "nvidia,tegra30-pwm" },

Could you swap those two lines, so that tegra30-pwm matches first. It
makes no difference at present, but might in the future if the driver
actually has to differentiate the two SoCs.


From swarren at wwwdotorg.org  Fri Mar 30 15:04:28 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 13:04:28 -0600
Subject: [PATCH v5 15/16] pwm-backlight: Add rudimentary device tree
 support
In-Reply-To: <1332945238-14897-16-git-send-email-thierry.reding@avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-16-git-send-email-thierry.reding@avionic-design.de>
Message-ID: <4F7603BC.2050300@wwwdotorg.org>

On 03/28/2012 08:33 AM, Thierry Reding wrote:
> This commit adds very basic support for device tree probing. Currently,
> only a PWM and a list of distinct brightness levels can be specified.
> Enabling or disabling backlight power via GPIOs is not yet supported.
> 
> Signed-off-by: Thierry Reding <thierry.reding at avionic-design.de>

> diff --git a/Documentation/devicetree/bindings/video/backlight/pwm-backlight b/Documentation/devicetree/bindings/video/backlight/pwm-backlight
> +Required properties:
> +  - compatible: "pwm-backlight"
> +  - pwms: OF device-tree PWM specification (see PWM binding[0])
> +  - num-brightness-levels: number of distinct brightness levels

Do we need the "num-brightness-levels" property at all; it's just the
length of the brightness-levels property.

> +  - brightness-levels: Array of distinct brightness levels. Typically these
> +      are in the range from 0 to 255, but any range starting at 0 will do.
> +      The actual brightness level (PWM duty cycle) will be interpolated
> +      from these values. 0 means a 0% duty cycle (darkest/off), while the
> +      last value in the array represents a 100% duty cycle (brightest).
...> +Example:
> +
> +	backlight {
> +		compatible = "pwm-backlight";
> +		pwms = <&pwm 0 5000000>;
> +
> +		num-brightness-levels = <8>;
> +		brightness-levels = <0 4 8 16 32 64 128 255>;
> +		default-brightness-level = <6>;
> +	};


From robertcnelson at gmail.com  Fri Mar 30 15:30:08 2012
From: robertcnelson at gmail.com (Robert Nelson)
Date: Fri, 30 Mar 2012 14:30:08 -0500
Subject: [U-Boot] zImage and raw ramdisk support -- test
In-Reply-To: <201203301738.57972.marek.vasut@gmail.com>
References: <201203301738.57972.marek.vasut@gmail.com>
Message-ID: <CAOCHtYiewpJ6PERFP_O-0gXkkrQte1kL3m4za9=9ZaNBMgyqLg@mail.gmail.com>

On Fri, Mar 30, 2012 at 10:38 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Guys,
>
> I need final test on as much platforms as possible. Can you please run these two
> following patches and tell me if they work with zImage and raw ramdisk for you?
>
> http://patchwork.ozlabs.org/patch/146848/
> http://patchwork.ozlabs.org/patch/147440/
>
> I can't promise they will make it to this release (I've been pestering WD pretty
> thoroughly (sorry about that), though I'm starting to be unhappy to merge this
> stuff at the verge of release myself).

Hi Marek,

These work great on my omap3 Beagle xM C / omap4 Panda, using a zImage
and initramfs..

Just added the two appropriate board configs, to enable it..
#define CONFIG_CMD_BOOTZ
#define CONFIG_SUPPORT_RAW_INITRD

and used todays u-boot git head:
http://git.denx.de/?p=u-boot.git;a=commit;h=7cb30b13f12077c7eec8ce2419cd96cd65ace8e2

Tested-by: Robert Nelson <robertcnelson at gmail.com>

Regards,
-- 
Robert Nelson
http://www.rcn-ee.com/


From ccross at android.com  Fri Mar 30 15:43:29 2012
From: ccross at android.com (Colin Cross)
Date: Fri, 30 Mar 2012 12:43:29 -0700
Subject: [PATCH 2/3] ARM: OMAP4: cpuidle: Use coupled cpuidle states to
 implement SMP cpuidle.
In-Reply-To: <1333114048-26136-3-git-send-email-santosh.shilimkar@ti.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-3-git-send-email-santosh.shilimkar@ti.com>
Message-ID: <CAMbhsRRAQxDh_yZKayqMedvGkeSP9UGxiud9LbotWp-aMQ7cSw@mail.gmail.com>

On Fri, Mar 30, 2012 at 6:27 AM, Santosh Shilimkar
<santosh.shilimkar at ti.com> wrote:
> OMAP4 CPUDILE driver is converted mainly based on notes from the
> coupled cpuidle patch series.
>
> The changes include :
> - Register both CPUs and C-states to cpuidle driver.
> - Set struct cpuidle_device.coupled_cpus
> - Set struct cpuidle_device.safe_state to non coupled state.
> - Set CPUIDLE_FLAG_COUPLED in struct cpuidle_state.flags for each
> ?state that affects multiple cpus.
> - Separate ->enter hooks for coupled & simple idle.
> - CPU0 wait loop for CPU1 power transition.
> - CPU1 wakeup mechanism for the idle exit.
> - Enabling ARCH_NEEDS_CPU_IDLE_COUPLED for OMAP4.
>
> Thanks to Kevin Hilman and Colin Cross on the suggestions/fixes
> on the intermediate version of this patch.
>
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
> CC: Kevin Hilman <khilman at ti.com>
> Cc: Colin Cross <ccross at android.com>
> ---
> ?arch/arm/mach-omap2/Kconfig ? ? ? | ? ?1 +
> ?arch/arm/mach-omap2/cpuidle44xx.c | ?167 ++++++++++++++++++++++---------------
> ?2 files changed, 101 insertions(+), 67 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index e20c8ab..250786e 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -54,6 +54,7 @@ config ARCH_OMAP4
> ? ? ? ?select PM_OPP if PM
> ? ? ? ?select USB_ARCH_HAS_EHCI
> ? ? ? ?select ARM_CPU_SUSPEND if PM
> + ? ? ? select ARCH_NEEDS_CPU_IDLE_COUPLED if CPU_IDLE
The "if CPU_IDLE" is not necessary, ARCH_NEEDS_CPU_IDLE_COUPLED is
designed to have no effect if CPU_IDLE is not set.

>
> ?comment "OMAP Core Type"
> ? ? ? ?depends on ARCH_OMAP2
> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
> index f386cbe..5724393 100644
> --- a/arch/arm/mach-omap2/cpuidle44xx.c
> +++ b/arch/arm/mach-omap2/cpuidle44xx.c
> @@ -21,6 +21,7 @@
> ?#include "common.h"
> ?#include "pm.h"
> ?#include "prm.h"
> +#include "clockdomain.h"
>
> ?#ifdef CONFIG_CPU_IDLE
>
> @@ -44,10 +45,11 @@ static struct cpuidle_params cpuidle_params_table[] = {
> ?#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
>
> ?struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
> -static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
> +static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
> +static struct clockdomain *cpu_clkdm[NR_CPUS];
>
> ?/**
> - * omap4_enter_idle - Programs OMAP4 to enter the specified state
> + * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
> ?* @dev: cpuidle device
> ?* @drv: cpuidle driver
> ?* @index: the index of state to be entered
> @@ -56,34 +58,40 @@ static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
> ?* specified low power state selected by the governor.
> ?* Returns the amount of time spent in the low power state.
> ?*/
> -static int omap4_enter_idle(struct cpuidle_device *dev,
> +static int omap4_enter_idle_simple(struct cpuidle_device *dev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct cpuidle_driver *drv,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int index)
> +{
> + ? ? ? local_fiq_disable();
> + ? ? ? omap_do_wfi();
> + ? ? ? local_fiq_enable();
> +
> + ? ? ? return index;
> +}
> +
> +static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
> ? ? ? ? ? ? ? ? ? ? ? ?struct cpuidle_driver *drv,
> ? ? ? ? ? ? ? ? ? ? ? ?int index)
> ?{
> ? ? ? ?struct omap4_idle_statedata *cx =
> ? ? ? ? ? ? ? ? ? ? ? ?cpuidle_get_statedata(&dev->states_usage[index]);
> - ? ? ? u32 cpu1_state;
> ? ? ? ?int cpu_id = smp_processor_id();
>
> ? ? ? ?local_fiq_disable();
>
> + ? ? ? clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
> +
> ? ? ? ?/*
> - ? ? ? ?* CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
> + ? ? ? ?* CPU0 has to wait and stay ON until CPU1 is OFF state.
> ? ? ? ? * This is necessary to honour hardware recommondation
> ? ? ? ? * of triggeing all the possible low power modes once CPU1 is
> ? ? ? ? * out of coherency and in OFF mode.
> - ? ? ? ?* Update dev->last_state so that governor stats reflects right
> - ? ? ? ?* data.
> ? ? ? ? */
> - ? ? ? cpu1_state = pwrdm_read_pwrst(cpu1_pd);
> - ? ? ? if (cpu1_state != PWRDM_POWER_OFF) {
> - ? ? ? ? ? ? ? index = drv->safe_state_index;
> - ? ? ? ? ? ? ? cx = cpuidle_get_statedata(&dev->states_usage[index]);
> + ? ? ? if (dev->cpu == 0) {
> + ? ? ? ? ? ? ? while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF)
> + ? ? ? ? ? ? ? ? ? ? ? cpu_relax();
If something goes wrong in the core coupled code or in the cpu 1 power
state transition, this will hang forever and be hard to debug.  It
might be worth adding a timeout with a BUG_ON.

> ? ? ? ?}
>
> - ? ? ? if (index > 0)
> - ? ? ? ? ? ? ? clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
> -
> ? ? ? ?/*
> ? ? ? ? * Call idle CPU PM enter notifier chain so that
> ? ? ? ? * VFP and per CPU interrupt context is saved.
> @@ -91,25 +99,35 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
> ? ? ? ?if (cx->cpu_state == PWRDM_POWER_OFF)
> ? ? ? ? ? ? ? ?cpu_pm_enter();
This should never get called without cpu_state == PWRDM_POWER_OFF, and
even if it did, calling cpu_pm_enter shouldn't hurt anything.  It
would be clearer to unconditionally call cpu_pm_enter().

>
> - ? ? ? pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
> - ? ? ? omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
> -
> - ? ? ? /*
> - ? ? ? ?* Call idle CPU cluster PM enter notifier chain
> - ? ? ? ?* to save GIC and wakeupgen context.
> - ? ? ? ?*/
> - ? ? ? if ((cx->mpu_state == PWRDM_POWER_RET) &&
> - ? ? ? ? ? ? ? (cx->mpu_logic_state == PWRDM_POWER_OFF))
> - ? ? ? ? ? ? ? ? ? ? ? cpu_cluster_pm_enter();
> + ? ? ? if (dev->cpu == 0) {
> + ? ? ? ? ? ? ? pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
> + ? ? ? ? ? ? ? omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
> +
> + ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ?* Call idle CPU cluster PM enter notifier chain
> + ? ? ? ? ? ? ? ?* to save GIC and wakeupgen context.
> + ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? if ((cx->mpu_state == PWRDM_POWER_RET) &&
> + ? ? ? ? ? ? ? ? ? ? ? (cx->mpu_logic_state == PWRDM_POWER_OFF))
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cpu_cluster_pm_enter();
> + ? ? ? }
>
> ? ? ? ?omap4_enter_lowpower(dev->cpu, cx->cpu_state);
>
> + ? ? ? if (dev->cpu == 0) {
> + ? ? ? ? ? ? ? /* Wakeup CPU1 only if it is not offlined */
> + ? ? ? ? ? ? ? if (cpumask_test_cpu(1, cpu_online_mask)) {
> + ? ? ? ? ? ? ? ? ? ? ? clkdm_wakeup(cpu_clkdm[1]);
> + ? ? ? ? ? ? ? ? ? ? ? clkdm_allow_idle(cpu_clkdm[1]);
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> ? ? ? ?/*
> ? ? ? ? * Call idle CPU PM exit notifier chain to restore
> ? ? ? ? * VFP and per CPU IRQ context. Only CPU0 state is
> ? ? ? ? * considered since CPU1 is managed by CPU hotplug.
> ? ? ? ? */
This comment is no longer accurate?  cpu_pm_enter is called on cpu 1 above.

> - ? ? ? if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
> + ? ? ? if (pwrdm_read_prev_pwrst(cpu_pd[dev->cpu]) == PWRDM_POWER_OFF)
> ? ? ? ? ? ? ? ?cpu_pm_exit();
This should get called unconditionally.  It's not explicitly stated,
but the cpu_pm_* api expects cpu_pm_exit() to be called after
cpu_pm_enter(), even if the low power state was not entered.
Otherwise, a cpu_pm_enter notifier that disables the hardware will not
get a chance to re-enable it.


From u.kleine-koenig at pengutronix.de  Fri Mar 30 16:04:52 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Fri, 30 Mar 2012 22:04:52 +0200
Subject: [PATCH v2 02/15] ARM: mark const init data with __initconst instead
 of __initdata
In-Reply-To: <20120330200358.GV15647@pengutronix.de>
References: <20120330200358.GV15647@pengutronix.de>
Message-ID: <1333137905-13809-2-git-send-email-u.kleine-koenig@pengutronix.de>

As long as there is no other non-const variable marked __initdata in the
same compilation unit it doesn't hurt. If there were one however
compilation would fail with

	error: $variablename causes a section type conflict

because a section containing const variables is marked read only and so
cannot contain non-const variables.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
Cc: Andrew Victor <linux at maxim.org.za>
Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj at jcrosoft.com>
Cc: Russell King <linux at arm.linux.org.uk>
Cc: Sekhar Nori <nsekhar at ti.com>
Cc: Kevin Hilman <khilman at ti.com>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Sascha Hauer <kernel at pengutronix.de>
Cc: Shawn Guo <shawn.guo at linaro.org>
Cc: Lennert Buytenhek <kernel at wantstofly.org>
Cc: Nicolas Pitre <nico at fluxnic.net>
Cc: Eric Miao <eric.y.miao at gmail.com>
Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
Cc: David Brown <davidb at codeaurora.org>
Cc: Daniel Walker <dwalker at fifo99.com>
Cc: Bryan Huntsman <bryanh at codeaurora.org>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Barry Song <baohua.song at csr.com>
Cc: Andrew Lunn <andrew at lunn.ch>
Cc: Lucas De Marchi <lucas.demarchi at profusion.mobi>
Cc: linux-arm-kernel at lists.infradead.org
Cc: davinci-linux-open-source at linux.davincidsp.com
Cc: linux-samsung-soc at vger.kernel.org
Cc: linux-arm-msm at vger.kernel.org
Cc: linux-omap at vger.kernel.org
---
changes since (implicit) v1:
 - drop changes to several files that were wrong:
   - arch/arm/mach-at91/board-dt.c
   - arch/arm/mach-exynos/*
   - arch/arm/mach-imx/*
   - arch/arm/mach-mmp/mmp-dt.c
   - arch/arm/mach-msm/board-msm8x60.c
   - arch/arm/mach-omap2/board-generic.c
   - arch/arm/mach-omap2/voltagedomains{3x,44}xx_data.c
   - arch/arm/mach-prima2
 - fix position of __initconst
   - arch/arm/mach-kirkwood/addr-map.c
   - arch/arm/mach-orion5x/addr-map.c

 arch/arm/mach-at91/clock.c                  |    2 +-
 arch/arm/mach-davinci/board-tnetv107x-evm.c |    6 ++--
 arch/arm/mach-davinci/da830.c               |   48 +++++++++++++--------------
 arch/arm/mach-davinci/da850.c               |    6 ++--
 arch/arm/mach-dove/addr-map.c               |    2 +-
 arch/arm/mach-kirkwood/addr-map.c           |    2 +-
 arch/arm/mach-msm/board-qsd8x50.c           |    4 +--
 arch/arm/mach-omap2/display.c               |    6 ++--
 arch/arm/mach-orion5x/addr-map.c            |    2 +-
 9 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index a0f4d74..e4a255d 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -613,7 +613,7 @@ fail:
 	return 0;
 }
 
-static struct clk *const standard_pmc_clocks[] __initdata = {
+static struct clk *const standard_pmc_clocks[] __initconst = {
 	/* four primary clocks */
 	&clk32k,
 	&main_clk,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index 5f14e30..645a587 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -88,7 +88,7 @@ static struct davinci_mmc_config mmc_config = {
 	.version	= MMC_CTLR_VERSION_1,
 };
 
-static const short sdio1_pins[] __initdata = {
+static const short sdio1_pins[] __initconst = {
 	TNETV107X_SDIO1_CLK_1,		TNETV107X_SDIO1_CMD_1,
 	TNETV107X_SDIO1_DATA0_1,	TNETV107X_SDIO1_DATA1_1,
 	TNETV107X_SDIO1_DATA2_1,	TNETV107X_SDIO1_DATA3_1,
@@ -96,12 +96,12 @@ static const short sdio1_pins[] __initdata = {
 	-1
 };
 
-static const short uart1_pins[] __initdata = {
+static const short uart1_pins[] __initconst = {
 	TNETV107X_UART1_RD,		TNETV107X_UART1_TD,
 	-1
 };
 
-static const short ssp_pins[] __initdata = {
+static const short ssp_pins[] __initconst = {
 	TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
 	TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
 	TNETV107X_SSP1_3, -1
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index deee5c2..510648e 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -838,7 +838,7 @@ static const struct mux_config da830_pins[] = {
 #endif
 };
 
-const short da830_emif25_pins[] __initdata = {
+const short da830_emif25_pins[] __initconst = {
 	DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
 	DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
 	DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
@@ -853,19 +853,19 @@ const short da830_emif25_pins[] __initdata = {
 	-1
 };
 
-const short da830_spi0_pins[] __initdata = {
+const short da830_spi0_pins[] __initconst = {
 	DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
 	DA830_NSPI0_SCS_0,
 	-1
 };
 
-const short da830_spi1_pins[] __initdata = {
+const short da830_spi1_pins[] __initconst = {
 	DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
 	DA830_NSPI1_SCS_0,
 	-1
 };
 
-const short da830_mmc_sd_pins[] __initdata = {
+const short da830_mmc_sd_pins[] __initconst = {
 	DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
 	DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
 	DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
@@ -873,32 +873,32 @@ const short da830_mmc_sd_pins[] __initdata = {
 	-1
 };
 
-const short da830_uart0_pins[] __initdata = {
+const short da830_uart0_pins[] __initconst = {
 	DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
 	-1
 };
 
-const short da830_uart1_pins[] __initdata = {
+const short da830_uart1_pins[] __initconst = {
 	DA830_UART1_RXD, DA830_UART1_TXD,
 	-1
 };
 
-const short da830_uart2_pins[] __initdata = {
+const short da830_uart2_pins[] __initconst = {
 	DA830_UART2_RXD, DA830_UART2_TXD,
 	-1
 };
 
-const short da830_usb20_pins[] __initdata = {
+const short da830_usb20_pins[] __initconst = {
 	DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
 	-1
 };
 
-const short da830_usb11_pins[] __initdata = {
+const short da830_usb11_pins[] __initconst = {
 	DA830_USB_REFCLKIN,
 	-1
 };
 
-const short da830_uhpi_pins[] __initdata = {
+const short da830_uhpi_pins[] __initconst = {
 	DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
 	DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
 	DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
@@ -909,14 +909,14 @@ const short da830_uhpi_pins[] __initdata = {
 	-1
 };
 
-const short da830_cpgmac_pins[] __initdata = {
+const short da830_cpgmac_pins[] __initconst = {
 	DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
 	DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
 	DA830_MDIO_D,
 	-1
 };
 
-const short da830_emif3c_pins[] __initdata = {
+const short da830_emif3c_pins[] __initconst = {
 	DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
 	DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
 	DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
@@ -935,7 +935,7 @@ const short da830_emif3c_pins[] __initdata = {
 	-1
 };
 
-const short da830_mcasp0_pins[] __initdata = {
+const short da830_mcasp0_pins[] __initconst = {
 	DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
 	DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
 	DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
@@ -945,7 +945,7 @@ const short da830_mcasp0_pins[] __initdata = {
 	-1
 };
 
-const short da830_mcasp1_pins[] __initdata = {
+const short da830_mcasp1_pins[] __initconst = {
 	DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
 	DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
 	DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
@@ -954,24 +954,24 @@ const short da830_mcasp1_pins[] __initdata = {
 	-1
 };
 
-const short da830_mcasp2_pins[] __initdata = {
+const short da830_mcasp2_pins[] __initconst = {
 	DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
 	DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
 	DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
 	-1
 };
 
-const short da830_i2c0_pins[] __initdata = {
+const short da830_i2c0_pins[] __initconst = {
 	DA830_I2C0_SDA, DA830_I2C0_SCL,
 	-1
 };
 
-const short da830_i2c1_pins[] __initdata = {
+const short da830_i2c1_pins[] __initconst = {
 	DA830_I2C1_SCL, DA830_I2C1_SDA,
 	-1
 };
 
-const short da830_lcdcntl_pins[] __initdata = {
+const short da830_lcdcntl_pins[] __initconst = {
 	DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
 	DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
 	DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
@@ -981,34 +981,34 @@ const short da830_lcdcntl_pins[] __initdata = {
 	-1
 };
 
-const short da830_pwm_pins[] __initdata = {
+const short da830_pwm_pins[] __initconst = {
 	DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
 	DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
 	DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
 	-1
 };
 
-const short da830_ecap0_pins[] __initdata = {
+const short da830_ecap0_pins[] __initconst = {
 	DA830_ECAP0_APWM0,
 	-1
 };
 
-const short da830_ecap1_pins[] __initdata = {
+const short da830_ecap1_pins[] __initconst = {
 	DA830_ECAP1_APWM1,
 	-1
 };
 
-const short da830_ecap2_pins[] __initdata = {
+const short da830_ecap2_pins[] __initconst = {
 	DA830_ECAP2_APWM2,
 	-1
 };
 
-const short da830_eqep0_pins[] __initdata = {
+const short da830_eqep0_pins[] __initconst = {
 	DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
 	-1
 };
 
-const short da830_eqep1_pins[] __initdata = {
+const short da830_eqep1_pins[] __initconst = {
 	DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
 	-1
 };
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b44dc84..6676dee 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -576,17 +576,17 @@ static const struct mux_config da850_pins[] = {
 #endif
 };
 
-const short da850_i2c0_pins[] __initdata = {
+const short da850_i2c0_pins[] __initconst = {
 	DA850_I2C0_SDA, DA850_I2C0_SCL,
 	-1
 };
 
-const short da850_i2c1_pins[] __initdata = {
+const short da850_i2c1_pins[] __initconst = {
 	DA850_I2C1_SCL, DA850_I2C1_SDA,
 	-1
 };
 
-const short da850_lcdcntl_pins[] __initdata = {
+const short da850_lcdcntl_pins[] __initconst = {
 	DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
 	DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
 	DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
index 98b8c83b..93ea37d 100644
--- a/arch/arm/mach-dove/addr-map.c
+++ b/arch/arm/mach-dove/addr-map.c
@@ -49,7 +49,7 @@ static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.bridge_virt_base = BRIDGE_VIRT_BASE,
 };
 
-static const struct __initdata orion_addr_map_info addr_map_info[] = {
+static const struct orion_addr_map_info addr_map_info[] __initconst = {
 	/*
 	 * Windows for PCIe IO+MEM space.
 	 */
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index e9a7180..b2c0dee 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -44,7 +44,7 @@ static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.bridge_virt_base = BRIDGE_VIRT_BASE,
 };
 
-static const struct __initdata orion_addr_map_info addr_map_info[] = {
+static const struct orion_addr_map_info addr_map_info[] __initconst = {
 	/*
 	 * Windows for PCIe IO+MEM space.
 	 */
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 7e8909c..11de242 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -39,8 +39,8 @@
 
 extern struct sys_timer msm_timer;
 
-static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
-static const unsigned        qsd8x50_surf_smc91x_gpio __initdata = 156;
+static const resource_size_t qsd8x50_surf_smc91x_base __initconst = 0x70000300;
+static const unsigned        qsd8x50_surf_smc91x_gpio __initconst = 156;
 
 /* Leave smc91x resources empty here, as we'll fill them in
  * at run-time: they vary from board to board, and the true
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 9706c64..df2ef11 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -74,14 +74,14 @@ struct omap_dss_hwmod_data {
 	const int id;
 };
 
-static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
 	{ "dss_core", "omapdss_dss", -1 },
 	{ "dss_dispc", "omapdss_dispc", -1 },
 	{ "dss_rfbi", "omapdss_rfbi", -1 },
 	{ "dss_venc", "omapdss_venc", -1 },
 };
 
-static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
 	{ "dss_core", "omapdss_dss", -1 },
 	{ "dss_dispc", "omapdss_dispc", -1 },
 	{ "dss_rfbi", "omapdss_rfbi", -1 },
@@ -89,7 +89,7 @@ static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
 	{ "dss_dsi1", "omapdss_dsi", 0 },
 };
 
-static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
+static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
 	{ "dss_core", "omapdss_dss", -1 },
 	{ "dss_dispc", "omapdss_dispc", -1 },
 	{ "dss_rfbi", "omapdss_rfbi", -1 },
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 3638e5c..277fcf4 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -82,7 +82,7 @@ static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
 };
 
-static const struct __initdata orion_addr_map_info addr_map_info[] = {
+static const struct orion_addr_map_info addr_map_info[] __initconst = {
 	/*
 	 * Setup windows for PCI+PCIe IO+MEM space.
 	 */
-- 
1.7.9.5



From u.kleine-koenig at pengutronix.de  Fri Mar 30 16:05:03 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Fri, 30 Mar 2012 22:05:03 +0200
Subject: [PATCH v2 13/15] media/video/s5p-tv: mark const init data with
 __initconst instead of __initdata
In-Reply-To: <20120330200358.GV15647@pengutronix.de>
References: <20120330200358.GV15647@pengutronix.de>
Message-ID: <1333137905-13809-13-git-send-email-u.kleine-koenig@pengutronix.de>

As long as there is no other non-const variable marked __initdata in the
same compilation unit it doesn't hurt. If there were one however
compilation would fail with

	error: $variablename causes a section type conflict

because a section containing const variables is marked read only and so
cannot contain non-const variables.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
Cc: Kyungmin Park <kyungmin.park at samsung.com>
Cc: Tomasz Stanislawski <t.stanislaws at samsung.com>
Cc: Mauro Carvalho Chehab <mchehab at infradead.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-media at vger.kernel.org
---
no changes since (implicit) v1

 drivers/media/video/s5p-tv/mixer_drv.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/video/s5p-tv/mixer_drv.c b/drivers/media/video/s5p-tv/mixer_drv.c
index a2c0c25..edca065 100644
--- a/drivers/media/video/s5p-tv/mixer_drv.c
+++ b/drivers/media/video/s5p-tv/mixer_drv.c
@@ -461,7 +461,7 @@ static struct platform_driver mxr_driver __refdata = {
 static int __init mxr_init(void)
 {
 	int i, ret;
-	static const char banner[] __initdata = KERN_INFO
+	static const char banner[] __initconst = KERN_INFO
 		"Samsung TV Mixer driver, "
 		"(c) 2010-2011 Samsung Electronics Co., Ltd.\n";
 	printk(banner);
-- 
1.7.9.5



From u.kleine-koenig at pengutronix.de  Fri Mar 30 16:13:53 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Fri, 30 Mar 2012 22:13:53 +0200
Subject: [PATCH] ARM: davinci: mark spi_board_info arg to da8xx_register_spi
 as const
Message-ID: <1333138433-14637-1-git-send-email-u.kleine-koenig@pengutronix.de>

No further changes necessary

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-davinci/devices-da8xx.c      |    2 +-
 arch/arm/mach-davinci/include/mach/da8xx.h |    3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 42dbf3d..d1624a3 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -831,7 +831,7 @@ static struct platform_device da8xx_spi_device[] = {
 	},
 };
 
-int __init da8xx_register_spi(int instance, struct spi_board_info *info,
+int __init da8xx_register_spi(int instance, const struct spi_board_info *info,
 			      unsigned len)
 {
 	int ret;
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index ee3461d..a2f1f27 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -76,7 +76,8 @@ void __init da850_init(void);
 int da830_register_edma(struct edma_rsv_info *rsv);
 int da850_register_edma(struct edma_rsv_info *rsv[2]);
 int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
-int da8xx_register_spi(int instance, struct spi_board_info *info, unsigned len);
+int da8xx_register_spi(int instance,
+		const struct spi_board_info *info, unsigned len);
 int da8xx_register_watchdog(void);
 int da8xx_register_usb20(unsigned mA, unsigned potpgt);
 int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
-- 
1.7.9.5



From arnd at arndb.de  Fri Mar 30 16:18:43 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 30 Mar 2012 20:18:43 +0000
Subject: [PATCH 1/3] PATA host controller driver for ep93xx
In-Reply-To: <4F741AB1.4000107@metasoft.pl>
References: <4F7418E7.4060500@metasoft.pl> <4F741AB1.4000107@metasoft.pl>
Message-ID: <201203302018.43681.arnd@arndb.de>

On Thursday 29 March 2012, Rafal Prylowski wrote:

> +static u16 ep93xx_pata_read(struct ep93xx_pata_data *drv_data,
> +			    void *addr_io,
> +			    const struct ata_timing *t)
> +{
> +	unsigned long addr = (unsigned long) addr_io & 0x1f;
> +	void __iomem *base = drv_data->ide_base;
> +	u16 ret;
> +
> +	writel(IDECtrl_DIOWn | IDECtrl_DIORn | addr, base + IDECtrl);
> +	ndelay(t->setup);
> +	writel(IDECtrl_DIOWn | addr, base + IDECtrl);

The pointer arithmetic that you do here on addr_io looks really evil.
Basically your registers are indirect and cannot be accessed through
pointer dereference. Maybe you should not be trying to do that then
and not use the ata_port->ioaddr structure.

> +	ndelay(t->act8b);

I'm not too familar with ata drivers, but I don't think you're supposed
to have delays in the code for the timings, rather than programming
the timings into the controller registers. Are you sure this is the
right thing here?

> +	if (drv_data->iordy) {
> +		/* min. 1s timeout (at cpu cycle = 5ns) */
> +		unsigned int timeout = 200000;
> +		while (!ep93xx_pata_check_iordy(base) && --timeout)
> +			cpu_relax();
> +	}

This is not a reliable way to implement a timeout. Instead, you should
use time_before() to check if hte timeout has expired.


> +static void ep93xx_pata_setup_port(struct ata_ioports *ioaddr)
> +{
> +	/*
> +	 * the device IDE register to be accessed is selected through
> +	 * IDECTRL register's specific bitfields 'DA', 'CS1n' and 'CS0n':
> +	 *   b4   b3   b2    b1     b0
> +	 *   A2   A1   A0   CS1n   CS0n
> +	 * the values filled in this structure allows the value to be directly
> +	 * ORed to the IDECTRL register, hence giving directly the A[2:0] and
> +	 * CS1n/CS0n values for each IDE register.
> +	 * The values correspond to the transformation:
> +	 *   ((real IDE address) << 2) | CS1n value << 1 | CS0n value
> +	 */
> +	ioaddr->cmd_addr	= (void __iomem *) 0 + 2; /* CS1 */
> +
> +	ioaddr->data_addr	= (void __iomem *) (ATA_REG_DATA << 2) + 2;
> +	ioaddr->error_addr	= (void __iomem *) (ATA_REG_ERR << 2) + 2;
> +	ioaddr->feature_addr	= (void __iomem *) (ATA_REG_FEATURE << 2) + 2;
> +	ioaddr->nsect_addr	= (void __iomem *) (ATA_REG_NSECT << 2) + 2;
> +	ioaddr->lbal_addr	= (void __iomem *) (ATA_REG_LBAL << 2) + 2;
> +	ioaddr->lbam_addr	= (void __iomem *) (ATA_REG_LBAM << 2) + 2;
> +	ioaddr->lbah_addr	= (void __iomem *) (ATA_REG_LBAH << 2) + 2;
> +	ioaddr->device_addr	= (void __iomem *) (ATA_REG_DEVICE << 2) + 2;
> +	ioaddr->status_addr	= (void __iomem *) (ATA_REG_STATUS << 2) + 2;
> +	ioaddr->command_addr	= (void __iomem *) (ATA_REG_CMD << 2) + 2;
> +
> +	ioaddr->altstatus_addr	= (void __iomem *) (0x06 << 2) + 1; /* CS0 */
> +	ioaddr->ctl_addr	= (void __iomem *) (0x06 << 2) + 1; /* CS0 */
> +}

As mentioned above, this seems to make no sense.

> ===================================================================
> --- linux-2.6.orig/drivers/ata/Kconfig
> +++ linux-2.6/drivers/ata/Kconfig
> @@ -416,6 +416,15 @@ config PATA_EFAR
>  
>  	  If unsure, say N.
>  
> +config PATA_EP93XX
> +	tristate "Cirrus Logic EP93xx PATA support"
> +	depends on ARCH_EP93XX
> +	help
> +	  This option enables support for the PATA controller in
> +	  the Cirrus Logic EP9312 and EP9315 ARM CPU.
> +
> +	  If unsure, say N.
> +
>  config PATA_HPT366
>  	tristate "HPT 366/368 PATA support"
>  	depends on PCI

And I think this should be consequently be sorted below nonstandard ports, instead of the SFF list.

	Arnd


From marek.vasut at gmail.com  Fri Mar 30 16:24:20 2012
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 30 Mar 2012 22:24:20 +0200
Subject: [U-Boot] zImage and raw ramdisk support -- test
In-Reply-To: <CAOCHtYiewpJ6PERFP_O-0gXkkrQte1kL3m4za9=9ZaNBMgyqLg@mail.gmail.com>
References: <201203301738.57972.marek.vasut@gmail.com>
 <CAOCHtYiewpJ6PERFP_O-0gXkkrQte1kL3m4za9=9ZaNBMgyqLg@mail.gmail.com>
Message-ID: <201203302224.20196.marek.vasut@gmail.com>

Dear Robert Nelson,

> On Fri, Mar 30, 2012 at 10:38 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > Guys,
> > 
> > I need final test on as much platforms as possible. Can you please run
> > these two following patches and tell me if they work with zImage and raw
> > ramdisk for you?
> > 
> > http://patchwork.ozlabs.org/patch/146848/
> > http://patchwork.ozlabs.org/patch/147440/
> > 
> > I can't promise they will make it to this release (I've been pestering WD
> > pretty thoroughly (sorry about that), though I'm starting to be unhappy
> > to merge this stuff at the verge of release myself).
> 
> Hi Marek,
> 
> These work great on my omap3 Beagle xM C / omap4 Panda, using a zImage
> and initramfs..
> 
> Just added the two appropriate board configs, to enable it..
> #define CONFIG_CMD_BOOTZ
> #define CONFIG_SUPPORT_RAW_INITRD
> 
> and used todays u-boot git head:
> http://git.denx.de/?p=u-boot.git;a=commit;h=7cb30b13f12077c7eec8ce2419cd96c
> d65ace8e2

And it makes u-boot about 20% cooler, doesn't it ;-)

Thanks a lot for your testing!

> Tested-by: Robert Nelson <robertcnelson at gmail.com>
> 
> Regards,

Best regards,
Marek Vasut


From u.kleine-koenig at pengutronix.de  Fri Mar 30 16:29:20 2012
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Fri, 30 Mar 2012 22:29:20 +0200
Subject: [PATCH] ARM: davinci/da850-evm: fix section mismatch
Message-ID: <1333139360-6791-1-git-send-email-u.kleine-koenig@pengutronix.de>

This fixes:
	WARNING: arch/arm/mach-davinci/built-in.o(.text+0x2d84): Section mismatch in reference from the function da850_evm_ui_expander_setup() to the (unknown reference) .init.data:(unknown)
	The function da850_evm_ui_expander_setup() references
	the (unknown reference) __initdata (unknown).
	This is often because da850_evm_ui_expander_setup lacks a __initdata
	annotation or the annotation of (unknown) is wrong.

Note this is a real issue because if the tca6416 driver only binds when
the init sections are already discarded da850_evm_ui_expander_setup is
called when da850_evm_devices might already be overwritten.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-davinci/board-da850-evm.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index a70de24..09f6107 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -284,7 +284,7 @@ static struct platform_device da850_evm_nandflash_device = {
 	.resource	= da850_evm_nandflash_resource,
 };
 
-static struct platform_device *da850_evm_devices[] __initdata = {
+static struct platform_device *da850_evm_devices[] = {
 	&da850_evm_nandflash_device,
 	&da850_evm_norflash_device,
 };
-- 
1.7.9.5



From manabian at gmail.com  Fri Mar 30 17:03:50 2012
From: manabian at gmail.com (manabian at gmail.com)
Date: Fri, 30 Mar 2012 23:03:50 +0200
Subject: [PATCH] ARM: at91: Export at91_ramc_base
Message-ID: <4f761fd8.8843cc0a.22b0.6caa@mx.google.com>

From: Joachim Eastwood <joachim.eastwood at jotron.com>

After commit f363c407b42c4 building at91_cf as a module fails with:
  ERROR: "at91_ramc_base" [drivers/pcmcia/at91_cf.ko] undefined!
  make[1]: *** [__modpost] Error 1
  make: *** [modules] Error 2

Export at91_ramc_base symbol to allow drivers using at91_ramc_*
functions to be built as modules again.

Signed-off-by: Joachim Eastwood <joachim.eastwood at jotron.com>
---

This makes at91_cf compile again but it still doesn't work. Still
trying to figure out why.

 arch/arm/mach-at91/setup.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 1083739..aa010a9 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -53,6 +53,7 @@ void __init at91_init_interrupts(unsigned int *priority)
 }
 
 void __iomem *at91_ramc_base[2];
+EXPORT_SYMBOL(at91_ramc_base);
 
 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
 {
-- 
1.7.9.2



From lost.distance at yahoo.com  Fri Mar 30 17:13:16 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 30 Mar 2012 22:13:16 +0100 (BST)
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <4F75F497.50909@compulab.co.il>
Message-ID: <1333141996.98835.YahooMailClassic@web29014.mail.ird.yahoo.com>

--- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il> wrote:
> On 03/30/12 18:52, Paul Parsons
> wrote:
> > --- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il>
> wrote:
> >> On 03/30/12 18:06, Paul Parsons wrote:
> >>> --- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il>
> >> wrote:
> >>>> On 03/28/12 20:12, Paul Parsons
> >>>> wrote:
> >>>>> On PXA2xx platforms, the MFP API
> (described in
> >>>> Documentation/arm/pxa/mfp.txt)
> >>>>> provides values for the following:
> >>>>>
> >>>>> 1. GPIO inputs (e.g. GPIO105_GPIO).
> >>>>> 2. Alternate function inputs (e.g.
> >> GPIO105_CIF_DD_1).
> >>>>> 3. Alternate function outputs (e.g.
> >>>> GPIO105_KP_MKOUT_2).
> >>>>>
> >>>>> It does not provide values for GPIO
> outputs
> >> (i.e. AF0
> >>>> outputs).
> >>>>>
> >>>>> One cannot use the macro used by the
> MFP API
> >> internally
> >>>> - MFP_CFG_OUT() - to
> >>>>> define new GPIO output values, since
> that macro
> >> is
> >>>> forbidden in platform code.
> >>>>>
> >>>>> Without the ability to add GPIO outputs
> to the
> >> MFP
> >>>> configuration, it is not
> >>>>> possible to drive GPIO outputs high
> during
> >> sleep mode.
> >>>>>
> >>>>> This would be useful, for example, on
> the
> >> hx4700
> >>>> platform, where driving the
> >>>>> infrared powerdown GPIO 105 high during
> sleep
> >> mode
> >>>> would save some mA.
> >>>>>
> >>>>> So my question is: what method should
> one use
> >> to add
> >>>> GPIO outputs to the MFP
> >>>>> configuration?
> >>>>>
> >>>>> One possible method, namely manually
> defining
> >> values in
> >>>> the platform code:
> >>>>>
> >>>>>? ? ? MFP_PIN_GPIO105 |
> >> MFP_AF0 |
> >>>> MFP_DIR_OUT | MFP_LPM_DRIVE_HIGH,
> >>>>
> >>>> Have you tried:
> >>>> GPIO105_GPIO | MFP_LPM_DRIVE_HIGH,
> >>>> ?
> >>>>
> >>>> This way it works on other boards.
> >>>
> >>> Hello Igor,
> >>>
> >>> GPIO105_GPIO expands to a GPIO input -
> >> MFP_CFG_IN(GPIO105, AF0) -
> >>> not an output.
> >>
> >> Yeah, I know... but read in mfp-pxa2xx.h, lines
> 6-20:
> >> /*
> >>? * the following MFP_xxx bit definitions in
> mfp.h are
> >> re-used for pxa2xx:
> >>? *
> >>? *? MFP_PIN(x)
> >>? *? MFP_AFx
> >>? *? MFP_LPM_DRIVE_{LOW, HIGH}
> >>? *? MFP_LPM_EDGE_x
> >>? *
> >>? * other MFP_x bit definitions will be
> ignored
> >>? *
> >>? * and adds the below two bits specifically
> for pxa2xx:
> >>? *
> >>? * bit? ???23 -
> Input/Output (PXA2xx
> >> specific)
> >>? * bit? ???24 - Wakeup
> Enable(PXA2xx
> >> specific)
> >>? */
> >>
> >> This means, that there is no difference between:
> MFP_CFG_IN
> >> and MFP_CFG_OUT for PXA2xx.
> > 
> > The mfp-pxa2xx.c code says otherwise.
> 
> That's just great... outdated documentation...
> 
> > It uses the MFP direction bit
> > to set the GPDR registers on entering sleep mode:
> > 
> >? ? 353??? static int
> pxa2xx_mfp_suspend(void)
> >? ? 354??? {
> >? ? 355??? ???
> int i;
> >? ? ? ???...
> >? ? 368??? ???
> for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
> >? ? 369??? 
> >? ? ? ???...
> >? ? 375??? ???
> ??? GPDR(i * 32) = gpdr_lpm[i];
> >? ? 376??? ???
> }
> >? ? 377??? ???
> return 0;
> >? ? 378??? }
> > 
> > gpdr_lpm[] is initialized at startup to the current
> GPDR values, and
> > thereafter is updated by the value of the MFP_DIR_OUT
> bit in calls to
> > __mfp_config_gpio().
> 
> static int __mfp_config_gpio(unsigned gpio, unsigned long
> c)
> {
> ??? unsigned long gafr, mask =
> GPIO_bit(gpio);
> ??? int bank = gpio_to_bank(gpio);
> ??? int uorl = !!(gpio & 0x10); /*
> GAFRx_U or GAFRx_L ? */
> ??? int shft = (gpio & 0xf) << 1;
> ??? int fn = MFP_AF(c);
> ??? int is_out = (c & MFP_DIR_OUT) ? 1 :
> 0;
> 
> [...]
> 
> ??? /* alternate function and direction at
> low power mode */
> ??? switch (c & MFP_LPM_STATE_MASK) {
> ??? case MFP_LPM_DRIVE_HIGH:
> ??? ??? PGSR(bank) |= mask;
> ??? ??? is_out = 1;
> ??? ??? break;
> ??? case MFP_LPM_DRIVE_LOW:
> ??? ??? PGSR(bank) &=
> ~mask;
> ??? ??? is_out = 1;
> ??? ??? break;
> 
> And in the lines above, it gets overridden by
> MFP_LPM_DRIVE_*,
> or am I missing something?

No, that looks to be the case: the LPM states DRIVE_HIGH and DRIVE_LOW
override the sleep mode direction. I completely missed that.

> [...]
> 
> ??? if (is_out ^
> gpio_desc[gpio].dir_inverted)
> ??? ??? gpdr_lpm[bank] |=
> mask;
> ??? else
> ??? ??? gpdr_lpm[bank] &=
> ~mask;
> 
> 
> So, I think,
> GPIO105_GPIO | MFP_LPM_DRIVE_HIGH,
> as I've proposed in my first email, should still work for
> you.

Yes it should. Thanks.

Regards,
Paul


From manabian at gmail.com  Fri Mar 30 17:13:22 2012
From: manabian at gmail.com (Joachim Eastwood)
Date: Fri, 30 Mar 2012 23:13:22 +0200
Subject: [PATCH] ARM: include linux/bug.h in insn.c
Message-ID: <1333142002-15431-1-git-send-email-joachim.eastwood@jotron.com>

After commit d82227cf8 building the kernel fails with:
  arch/arm/kernel/insn.c: In function '__arm_gen_branch_thumb2':
  arch/arm/kernel/insn.c:13: error: implicit declaration of function 'WARN_ON_ONCE'
  make[1]: *** [arch/arm/kernel/insn.o] Error 1
  make: *** [arch/arm/kernel] Error 2

insn.c uses WARN_ON_ONCE so lets include bug.h.

Signed-off-by: Joachim Eastwood <joachim.eastwood at jotron.com>
---
 arch/arm/kernel/insn.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/kernel/insn.c b/arch/arm/kernel/insn.c
index ab312e5..080fc70 100644
--- a/arch/arm/kernel/insn.c
+++ b/arch/arm/kernel/insn.c
@@ -1,4 +1,5 @@
 #include <linux/kernel.h>
+#include <linux/bug.h>
 #include <asm/opcodes.h>
 
 static unsigned long
-- 
1.7.9.2



From festevam at gmail.com  Fri Mar 30 17:26:43 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 30 Mar 2012 18:26:43 -0300
Subject: [PATCH] ARM: mach-imx: Include <asm/system_misc.h>
Message-ID: <1333142803-24183-1-git-send-email-festevam@gmail.com>

Fix the following build error:

arch/arm/mach-imx/mm-imx3.c:138:2: error: 'arm_pm_idle' undeclared (first use in this function)
arch/arm/mach-imx/mm-imx3.c:210:2: error: 'arm_pm_idle' undeclared (first use in this function)
make[2]: *** [arch/arm/mach-imx/mm-imx3.o] Error 1
arch/arm/mach-imx/mm-imx5.c:105:2: error: 'arm_pm_idle' undeclared (first use in this function)

This was caused by commit 4a3ea24 (ARM: plat-mxc: hook special idle handlers to arm_pm_idle)

Include <asm/system_misc.h> to avoid the build error.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
This applies against linux-next
 arch/arm/mach-imx/mm-imx3.c |    1 +
 arch/arm/mach-imx/mm-imx5.c |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index d534d7f..1da77fa 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -23,6 +23,7 @@
 #include <asm/pgtable.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 
 #include <mach/common.h>
 #include <mach/devices-common.h>
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 51af9fa..ac8e35c 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -16,6 +16,7 @@
 #include <linux/clk.h>
 
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-- 
1.7.1



From wd at denx.de  Fri Mar 30 17:38:31 2012
From: wd at denx.de (Wolfgang Denk)
Date: Fri, 30 Mar 2012 23:38:31 +0200
Subject: [U-Boot] zImage and raw ramdisk support -- test
In-Reply-To: <201203302224.20196.marek.vasut@gmail.com>
References: <201203301738.57972.marek.vasut@gmail.com>
 <CAOCHtYiewpJ6PERFP_O-0gXkkrQte1kL3m4za9=9ZaNBMgyqLg@mail.gmail.com>
 <201203302224.20196.marek.vasut@gmail.com>
Message-ID: <20120330213831.34630202B2B@gemini.denx.de>

Dear Marek Vasut,

In message <201203302224.20196.marek.vasut at gmail.com> you wrote:
> 
> > and used todays u-boot git head:
> > http://git.denx.de/?p=u-boot.git;a=commit;h=7cb30b13f12077c7eec8ce2419cd96c
> > d65ace8e2
> 
> And it makes u-boot about 20% cooler, doesn't it ;-)

No. Just so many more build warnigns :-(

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Bradley's Bromide: If computers get too  powerful,  we  can  organize
them into a committee - that will do them in.


From lost.distance at yahoo.com  Fri Mar 30 17:40:47 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Fri, 30 Mar 2012 22:40:47 +0100 (BST)
Subject: How to add GPIO outputs to the PXA2xx MFP configuration?
In-Reply-To: <1333141996.98835.YahooMailClassic@web29014.mail.ird.yahoo.com>
Message-ID: <1333143647.24376.YahooMailClassic@web29010.mail.ird.yahoo.com>

--- On Fri, 30/3/12, Paul Parsons <lost.distance at yahoo.com> wrote:
> --- On Fri, 30/3/12, Igor Grinberg
> <grinberg at compulab.co.il>
> wrote:
> > On 03/30/12 18:52, Paul Parsons
> > wrote:
> > > --- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il>
> > wrote:
> > >> On 03/30/12 18:06, Paul Parsons wrote:
> > >>> --- On Fri, 30/3/12, Igor Grinberg <grinberg at compulab.co.il>
> > >> wrote:
> > >>>> On 03/28/12 20:12, Paul Parsons
> > >>>> wrote:
> > >>>>> On PXA2xx platforms, the MFP API
> > (described in
> > >>>> Documentation/arm/pxa/mfp.txt)
> > >>>>> provides values for the
> following:
> > >>>>>
> > >>>>> 1. GPIO inputs (e.g.
> GPIO105_GPIO).
> > >>>>> 2. Alternate function inputs
> (e.g.
> > >> GPIO105_CIF_DD_1).
> > >>>>> 3. Alternate function outputs
> (e.g.
> > >>>> GPIO105_KP_MKOUT_2).
> > >>>>>
> > >>>>> It does not provide values for
> GPIO
> > outputs
> > >> (i.e. AF0
> > >>>> outputs).
> > >>>>>
> > >>>>> One cannot use the macro used by
> the
> > MFP API
> > >> internally
> > >>>> - MFP_CFG_OUT() - to
> > >>>>> define new GPIO output values,
> since
> > that macro
> > >> is
> > >>>> forbidden in platform code.
> > >>>>>
> > >>>>> Without the ability to add GPIO
> outputs
> > to the
> > >> MFP
> > >>>> configuration, it is not
> > >>>>> possible to drive GPIO outputs
> high
> > during
> > >> sleep mode.
> > >>>>>
> > >>>>> This would be useful, for example,
> on
> > the
> > >> hx4700
> > >>>> platform, where driving the
> > >>>>> infrared powerdown GPIO 105 high
> during
> > sleep
> > >> mode
> > >>>> would save some mA.
> > >>>>>
> > >>>>> So my question is: what method
> should
> > one use
> > >> to add
> > >>>> GPIO outputs to the MFP
> > >>>>> configuration?
> > >>>>>
> > >>>>> One possible method, namely
> manually
> > defining
> > >> values in
> > >>>> the platform code:
> > >>>>>
> > >>>>>? ? ? MFP_PIN_GPIO105 |
> > >> MFP_AF0 |
> > >>>> MFP_DIR_OUT | MFP_LPM_DRIVE_HIGH,
> > >>>>
> > >>>> Have you tried:
> > >>>> GPIO105_GPIO | MFP_LPM_DRIVE_HIGH,
> > >>>> ?
> > >>>>
> > >>>> This way it works on other boards.
> > >>>
> > >>> Hello Igor,
> > >>>
> > >>> GPIO105_GPIO expands to a GPIO input -
> > >> MFP_CFG_IN(GPIO105, AF0) -
> > >>> not an output.
> > >>
> > >> Yeah, I know... but read in mfp-pxa2xx.h,
> lines
> > 6-20:
> > >> /*
> > >>? * the following MFP_xxx bit definitions in
> > mfp.h are
> > >> re-used for pxa2xx:
> > >>? *
> > >>? *? MFP_PIN(x)
> > >>? *? MFP_AFx
> > >>? *? MFP_LPM_DRIVE_{LOW, HIGH}
> > >>? *? MFP_LPM_EDGE_x
> > >>? *
> > >>? * other MFP_x bit definitions will be
> > ignored
> > >>? *
> > >>? * and adds the below two bits specifically
> > for pxa2xx:
> > >>? *
> > >>? * bit? ???23 -
> > Input/Output (PXA2xx
> > >> specific)
> > >>? * bit? ???24 - Wakeup
> > Enable(PXA2xx
> > >> specific)
> > >>? */
> > >>
> > >> This means, that there is no difference
> between:
> > MFP_CFG_IN
> > >> and MFP_CFG_OUT for PXA2xx.
> > > 
> > > The mfp-pxa2xx.c code says otherwise.
> > 
> > That's just great... outdated documentation...
> > 
> > > It uses the MFP direction bit
> > > to set the GPDR registers on entering sleep mode:
> > > 
> > >? ? 353??? static int
> > pxa2xx_mfp_suspend(void)
> > >? ? 354??? {
> > >? ? 355??? ???
> > int i;
> > >? ? ? ???...
> > >? ? 368??? ???
> > for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++)
> {
> > >? ? 369??? 
> > >? ? ? ???...
> > >? ? 375??? ???
> > ??? GPDR(i * 32) = gpdr_lpm[i];
> > >? ? 376??? ???
> > }
> > >? ? 377??? ???
> > return 0;
> > >? ? 378??? }
> > > 
> > > gpdr_lpm[] is initialized at startup to the
> current
> > GPDR values, and
> > > thereafter is updated by the value of the
> MFP_DIR_OUT
> > bit in calls to
> > > __mfp_config_gpio().
> > 
> > static int __mfp_config_gpio(unsigned gpio, unsigned
> long
> > c)
> > {
> > ??? unsigned long gafr, mask =
> > GPIO_bit(gpio);
> > ??? int bank = gpio_to_bank(gpio);
> > ??? int uorl = !!(gpio & 0x10); /*
> > GAFRx_U or GAFRx_L ? */
> > ??? int shft = (gpio & 0xf) << 1;
> > ??? int fn = MFP_AF(c);
> > ??? int is_out = (c & MFP_DIR_OUT) ? 1 :
> > 0;
> > 
> > [...]
> > 
> > ??? /* alternate function and direction at
> > low power mode */
> > ??? switch (c & MFP_LPM_STATE_MASK) {
> > ??? case MFP_LPM_DRIVE_HIGH:
> > ??? ??? PGSR(bank) |= mask;
> > ??? ??? is_out = 1;
> > ??? ??? break;
> > ??? case MFP_LPM_DRIVE_LOW:
> > ??? ??? PGSR(bank) &=
> > ~mask;
> > ??? ??? is_out = 1;
> > ??? ??? break;
> > 
> > And in the lines above, it gets overridden by
> > MFP_LPM_DRIVE_*,
> > or am I missing something?
> 
> No, that looks to be the case: the LPM states DRIVE_HIGH and
> DRIVE_LOW
> override the sleep mode direction. I completely missed
> that.
> 
> > [...]
> > 
> > ??? if (is_out ^
> > gpio_desc[gpio].dir_inverted)
> > ??? ??? gpdr_lpm[bank] |=
> > mask;
> > ??? else
> > ??? ??? gpdr_lpm[bank] &=
> > ~mask;
> > 
> > 
> > So, I think,
> > GPIO105_GPIO | MFP_LPM_DRIVE_HIGH,
> > as I've proposed in my first email, should still work
> for
> > you.
> 
> Yes it should. Thanks.

However MFP_LPM_KEEP_OUTPUT does not do likewise, so for example:

    GPIO72_GPIO | MFP_LPM_KEEP_OUTPUT,

will set GPIO72 as an input in sleep mode. hmm...


From paul.gortmaker at windriver.com  Fri Mar 30 18:04:22 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Fri, 30 Mar 2012 18:04:22 -0400
Subject: [PATCH] ARM: mach-imx: Include <asm/system_misc.h>
In-Reply-To: <1333142803-24183-1-git-send-email-festevam@gmail.com>
References: <1333142803-24183-1-git-send-email-festevam@gmail.com>
Message-ID: <CAP=VYLoiHyrE+C8FvvakOZ9NSZQz3MGp0+e1hu21x6Jgr0HGLg@mail.gmail.com>

On Fri, Mar 30, 2012 at 5:26 PM, Fabio Estevam <festevam at gmail.com> wrote:
> Fix the following build error:
>
> arch/arm/mach-imx/mm-imx3.c:138:2: error: 'arm_pm_idle' undeclared (first use in this function)
> arch/arm/mach-imx/mm-imx3.c:210:2: error: 'arm_pm_idle' undeclared (first use in this function)
> make[2]: *** [arch/arm/mach-imx/mm-imx3.o] Error 1
> arch/arm/mach-imx/mm-imx5.c:105:2: error: 'arm_pm_idle' undeclared (first use in this function)

Olof has already fixed them all in bulk.

http://marc.info/?l=linux-arm-kernel&m=133311840811220&w=2

Paul.

>
> This was caused by commit 4a3ea24 (ARM: plat-mxc: hook special idle handlers to arm_pm_idle)
>
> Include <asm/system_misc.h> to avoid the build error.
>
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
> This applies against linux-next
> ?arch/arm/mach-imx/mm-imx3.c | ? ?1 +
> ?arch/arm/mach-imx/mm-imx5.c | ? ?1 +
> ?2 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
> index d534d7f..1da77fa 100644
> --- a/arch/arm/mach-imx/mm-imx3.c
> +++ b/arch/arm/mach-imx/mm-imx3.c
> @@ -23,6 +23,7 @@
> ?#include <asm/pgtable.h>
> ?#include <asm/hardware/cache-l2x0.h>
> ?#include <asm/mach/map.h>
> +#include <asm/system_misc.h>
>
> ?#include <mach/common.h>
> ?#include <mach/devices-common.h>
> diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
> index 51af9fa..ac8e35c 100644
> --- a/arch/arm/mach-imx/mm-imx5.c
> +++ b/arch/arm/mach-imx/mm-imx5.c
> @@ -16,6 +16,7 @@
> ?#include <linux/clk.h>
>
> ?#include <asm/mach/map.h>
> +#include <asm/system_misc.h>
>
> ?#include <mach/hardware.h>
> ?#include <mach/common.h>
> --
> 1.7.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From paul.gortmaker at windriver.com  Fri Mar 30 18:06:07 2012
From: paul.gortmaker at windriver.com (Paul Gortmaker)
Date: Fri, 30 Mar 2012 18:06:07 -0400
Subject: [PATCH] ARM: include linux/bug.h in insn.c
In-Reply-To: <1333142002-15431-1-git-send-email-joachim.eastwood@jotron.com>
References: <1333142002-15431-1-git-send-email-joachim.eastwood@jotron.com>
Message-ID: <CAP=VYLp173qpMwrLDRuvNURjJ6+TvkP7dHb6vDWgELiz9T9kGg@mail.gmail.com>

On Fri, Mar 30, 2012 at 5:13 PM, Joachim Eastwood <manabian at gmail.com> wrote:
> After commit d82227cf8 building the kernel fails with:

Please also list the shortlog when giving a commit ID, i.e.

   "ARM: 7331/1: extract out insn generation code from ftrace"

Thanks,
Paul.

> ?arch/arm/kernel/insn.c: In function '__arm_gen_branch_thumb2':
> ?arch/arm/kernel/insn.c:13: error: implicit declaration of function 'WARN_ON_ONCE'
> ?make[1]: *** [arch/arm/kernel/insn.o] Error 1
> ?make: *** [arch/arm/kernel] Error 2
>
> insn.c uses WARN_ON_ONCE so lets include bug.h.
>
> Signed-off-by: Joachim Eastwood <joachim.eastwood at jotron.com>
> ---
> ?arch/arm/kernel/insn.c | ? ?1 +
> ?1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/kernel/insn.c b/arch/arm/kernel/insn.c
> index ab312e5..080fc70 100644
> --- a/arch/arm/kernel/insn.c
> +++ b/arch/arm/kernel/insn.c
> @@ -1,4 +1,5 @@
> ?#include <linux/kernel.h>
> +#include <linux/bug.h>
> ?#include <asm/opcodes.h>
>
> ?static unsigned long
> --
> 1.7.9.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From kgene.kim at samsung.com  Fri Mar 30 18:24:34 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 30 Mar 2012 15:24:34 -0700
Subject: [PATCH 1/2] ARM: fix builds due to missing <asm/system_misc.h>
 includes
In-Reply-To: <1333118281-25295-1-git-send-email-olof@lixom.net>
References: <1333118281-25295-1-git-send-email-olof@lixom.net>
Message-ID: <4F7632A2.7030302@samsung.com>

Olof Johansson wrote:
> This does a sweeping change fixing up all the missing system_misc.h and
> system_info.h includes from the system.h split-up change. These were the
> ones I came across when building all defconfigs in arch/arm/configs, there
> might be more but they lack adequate build coverage to be easily caught.
>
> I'm expecting to get a lot of these piecemeal by each maintainer, so we
> might just as well do one sweeping change to get them all at once.
>
>
> Cc: Nicolas Ferre<nicolas.ferre at atmel.com>
> Cc: Russell King<linux at arm.linux.org.uk>
> Cc: Sascha Hauer<kernel at pengutronix.de>
> Cc: Imre Kaloz<kaloz at openwrt.org>
> Cc: Krzysztof Halasa<khc at pm.waw.pl>
> Cc: Eric Miao<eric.y.miao at gmail.com>
> Cc: Haojian Zhuang<haojian.zhuang at gmail.com>
> Cc: Wan ZongShun<mcuos.com at gmail.com>
> Cc: Kukjin Kim<kgene.kim at samsung.com>

Acked-by: Kukjin Kim <kgene.kim at samsung.com>

Thansk, this fixes following:

arch/arm/plat-s3c24xx/cpu.c: In function 's3c24xx_init_io':
arch/arm/plat-s3c24xx/cpu.c:221: error: 'arm_pm_idle' undeclared (first 
use in this function)
arch/arm/plat-s3c24xx/cpu.c:221: error: (Each undeclared identifier is 
reported only once
arch/arm/plat-s3c24xx/cpu.c:221: error: for each function it appears in.)
make[2]: *** [arch/arm/plat-s3c24xx/cpu.o] Error 1
make[2]: *** Waiting for unfinished jobs....

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

> Signed-off-by: Olof Johansson<olof at lixom.net>
> ---
>   arch/arm/mach-at91/at91x40.c  |    1 +
>   arch/arm/mach-at91/setup.c    |    1 +
>   arch/arm/mach-h720x/common.c  |    1 +
>   arch/arm/mach-imx/mm-imx3.c   |    1 +
>   arch/arm/mach-imx/mm-imx5.c   |    1 +
>   arch/arm/mach-ixp23xx/core.c  |    1 +
>   arch/arm/mach-ixp4xx/common.c |    1 +
>   arch/arm/mach-pxa/raumfeld.c  |    2 ++
>   arch/arm/mach-shark/core.c    |    1 +
>   arch/arm/mach-w90x900/dev.c   |    1 +
>   arch/arm/plat-s3c24xx/cpu.c   |    1 +
>   11 files changed, 12 insertions(+)

[...]


From linux at baker-net.org.uk  Fri Mar 30 18:30:49 2012
From: linux at baker-net.org.uk (Adam Baker)
Date: Fri, 30 Mar 2012 23:30:49 +0100
Subject: Support for Iomega iConnect
Message-ID: <201203302330.49834.linux@baker-net.org.uk>

Hi,

Is anyone aware of any technical reason why support for the Iomega iConnect is 
not included in the mainline kernel (e.g. there are significant changes 
happening in the area of the Kirkwood CPUs that mean now isn't a good time to 
include it). There are several versions floating around the internet but as far 
as I can see the only mention of the iConnect on this list is Russell saying 
he will remove it from mach types soon as there is no mainline support for it.

Based upon work that Iomega posted to the open source code area on their web 
site and code that was submitted to OpenWRT with a sign off line from Wojciech 
Dubowik, I have patched support into the 3.2.11 kernel. If there is no 
objection in principle to inclusion then I will rebase the patch and submit 
it.

Is Linus' git repository still the preferred baseline for linux-arm patches?

Regards

Adam Baker


From nicolas.pitre at linaro.org  Fri Mar 30 18:43:18 2012
From: nicolas.pitre at linaro.org (Nicolas Pitre)
Date: Fri, 30 Mar 2012 18:43:18 -0400 (EDT)
Subject: [PATCH v3] ARM: mxs: Add initial support for Bluegiga APX4
 Development Kit
In-Reply-To: <20120330132840.GG22981@n2100.arm.linux.org.uk>
References: <20111219071350.GH4962@S2100-06.ap.freescale.net>
 <4EEEE40C.3000200@bluegiga.com>
 <20111219091916.GJ4962@S2100-06.ap.freescale.net>
 <20111219091322.GD14542@n2100.arm.linux.org.uk>
 <20120104135204.GA14741@S2100-06.ap.freescale.net>
 <20120104211800.GF11810@n2100.arm.linux.org.uk>
 <20120105113106.GR11810@n2100.arm.linux.org.uk>
 <20120330131320.GH3254@S2101-09.ap.freescale.net>
 <20120330131509.GE22981@n2100.arm.linux.org.uk>
 <20120330132256.GI3254@S2101-09.ap.freescale.net>
 <20120330132840.GG22981@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.02.1203301837550.24151@xanadu.home>

On Fri, 30 Mar 2012, Russell King - ARM Linux wrote:

> On Fri, Mar 30, 2012 at 09:22:59PM +0800, Shawn Guo wrote:
> > I have seen it's on the linux-next at the early time of the cycle,
> > but I have to admit that I have not done that at the later time.
> 
> Well, I did lose track of which branches I had in linux-next during this
> last cycle, which is probably how it got dropped.
> 
> The last update gave this against mainline:
> 
>  arch/arm/tools/mach-types |  186 ++++++++++++++++++++++++--------------------
>  1 files changed, 101 insertions(+), 85 deletions(-)
> 
> and the latest update gives this also against mainline:
> 
>  arch/arm/tools/mach-types |  416 ++++++++++++++++++++++++---------------------
>  1 files changed, 219 insertions(+), 197 deletions(-)
> 
> so that's 196 platform IDs deleted, which is way too much to be 'safe'.

The "safest" at this point might be to just push the added and modified 
lines and postpone any removal for the next cycle.


Nicolas


And not to make things 





> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 


From manabian at gmail.com  Fri Mar 30 18:46:06 2012
From: manabian at gmail.com (manabian at gmail.com)
Date: Sat, 31 Mar 2012 00:46:06 +0200
Subject: [PATCH] ARM: at91: resurrect mach-at91/include/mach/io.h
Message-ID: <4f7637c4.51e4cc0a.35ba.ffffce95@mx.google.com>

From: Joachim Eastwood <joachim.eastwood at jotron.com>

Commmit 4d5fc58dbe34b78 "ARM: remove bunch of now unused mach/io.h files"
removed the at91 io.h header. This makes pata_pcmcia when used with at91_cf
fail on ioport_map in pcmcia_init_one.

Adding io.h and NEED_MACH_IO_H makes my CF card work again.

Signed-off-by: Joachim Eastwood <joachim.eastwood at jotron.com>
---

If there is better/correct way to solve the problem please disregard this
patch.

 arch/arm/mach-at91/Kconfig           |    1 +
 arch/arm/mach-at91/include/mach/io.h |   32 ++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+)
 create mode 100644 arch/arm/mach-at91/include/mach/io.h

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6631d35..8bcf917 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -37,6 +37,7 @@ config ARCH_AT91RM9200
 	select GENERIC_CLOCKEVENTS
 	select HAVE_AT91_DBGU0
 	select HAVE_AT91_USART3
+	select NEED_MACH_IO_H
 
 config ARCH_AT91SAM9260
 	bool "AT91SAM9260 or AT91SAM9XE"
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
new file mode 100644
index 0000000..ba9a22f
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-at91/include/mach/io.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT		0xFFFFFFFF
+
+#define __io(a)			__typesafe_io(a)
+#define __mem_pci(a)		(a)
+
+#endif
+
-- 
1.7.9.2



From kgene.kim at samsung.com  Fri Mar 30 18:50:43 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 30 Mar 2012 15:50:43 -0700
Subject: error: 'SEGMENT_SIZE' undeclared with arm-eabi-gcc toolchain
Message-ID: <4F7638C3.4060301@samsung.com>

Hi all,

Occurs following error with arm-eabi-gcc toolchain (gcc version 4.4.3 -
GCC). But there is no error with arm-none-linux-gnueabi-gcc toolchain
(gcc version 4.4.1 - Sourcery G++ Lite 2009q3)...

fs/binfmt_aout.c: In function 'load_aout_binary':
fs/binfmt_aout.c:255: error: 'SEGMENT_SIZE' undeclared (first use in
this function)
fs/binfmt_aout.c:255: error: (Each undeclared identifier is reported
only once
fs/binfmt_aout.c:255: error: for each function it appears in.)
make[2]: *** [fs/binfmt_aout.o] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [fs] Error 2

Any idea?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From kgene.kim at samsung.com  Fri Mar 30 18:58:39 2012
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 30 Mar 2012 15:58:39 -0700
Subject: [PATCH] ARM: S3C24XX: fix missing common.h in mach-s3c24xx/
In-Reply-To: <4F74556F.10704@mvista.com>
References: <1332980074-4614-1-git-send-email-kgene.kim@samsung.com>
 <4F74556F.10704@mvista.com>
Message-ID: <4F763A9F.2010907@samsung.com>

Sergei Shtylyov wrote:
> Hello.
>
> On 29-03-2012 4:14, Kukjin Kim wrote:
>

[...]

>> +#ifdef CONFIG_CPU_S3C2410
>> +void s3c2410_restart(char mode, const char *cmd);
>> +#endif
>> +
>> +#ifdef CONFIG_CPU_S3C244X
>> +void s3c244x_restart(char mode, const char *cmd);
>> +#endif
>
> Those #ifdef's around function prototypes are not necessary.
>
OK, thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.


From swarren at wwwdotorg.org  Fri Mar 30 18:59:53 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 16:59:53 -0600
Subject: [PATCH 00/11] ARM: tegra: GPIO and pinmux-related changes
Message-ID: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

This series:
* Updates the Tegra GPIO driver to interact with pinctrl per the recent
  gpio.txt documentation changes. Consequently, there's no need for
  tegra_gpio_enable() any more, and no need for board-pinmux.c to do
  anything GPIO-related.
* Switches to the new Tegra pinctrl driver, and deletes the old one.
* Moves pinctrl configuration to the device tree when booted using DT, so
  that board-dt-tegra*.c no longer depend on anything in board*.[ch].

Note to self: This series relies upon DT support in pinctrl, which
should be merged in 3.5.

Stephen Warren (11):
  usb: ehci-tegra: Add vbus_gpio to platform data
  ARM: tegra: Remove VBUS_GPIO handling from board files
  gpio: tegra: fix register address calculations for Tegra30
  gpio: tegra: Iterate over the correct number of banks
  gpio: tegra: configure pins during irq_set_type
  ARM: tegra: seaboard: Don't gpio_request() ISL29018_IRQ
  gpio: tegra: Hide tegra_gpio_enable/disable()
  ARM: tegra: Switch to new pinctrl driver
  ARM: tegra: Remove pre-pinctrl pinmux driver
  ARM: dt: tegra cardhu: add pinmux to device tree
  ARM: dt: tegra20: add pinmux to device tree

 arch/arm/boot/dts/tegra-cardhu.dts                |   44 +
 arch/arm/boot/dts/tegra-harmony.dts               |  224 +++++
 arch/arm/boot/dts/tegra-paz00.dts                 |  220 +++++
 arch/arm/boot/dts/tegra-seaboard.dts              |  243 +++++
 arch/arm/boot/dts/tegra-trimslice.dts             |  230 +++++
 arch/arm/boot/dts/tegra-ventana.dts               |  230 +++++
 arch/arm/mach-tegra/Makefile                      |    3 -
 arch/arm/mach-tegra/board-dt-tegra20.c            |   31 -
 arch/arm/mach-tegra/board-harmony-pinmux.c        |  266 +++---
 arch/arm/mach-tegra/board-paz00-pinmux.c          |  263 +++---
 arch/arm/mach-tegra/board-pinmux.c                |  105 +--
 arch/arm/mach-tegra/board-pinmux.h                |   38 +-
 arch/arm/mach-tegra/board-seaboard-pinmux.c       |  346 ++++----
 arch/arm/mach-tegra/board-seaboard.c              |   21 +-
 arch/arm/mach-tegra/board-trimslice-pinmux.c      |  264 +++---
 arch/arm/mach-tegra/board-trimslice.c             |   15 +-
 arch/arm/mach-tegra/devices.c                     |    3 +
 arch/arm/mach-tegra/include/mach/gpio-tegra.h     |    9 -
 arch/arm/mach-tegra/include/mach/pinmux-tegra20.h |  184 ----
 arch/arm/mach-tegra/include/mach/pinmux-tegra30.h |  320 -------
 arch/arm/mach-tegra/include/mach/pinmux.h         |  302 -------
 arch/arm/mach-tegra/pinmux-tegra20-tables.c       |  244 -----
 arch/arm/mach-tegra/pinmux-tegra30-tables.c       |  376 --------
 arch/arm/mach-tegra/pinmux.c                      |  987 ---------------------
 arch/arm/mach-tegra/usb_phy.c                     |    1 -
 drivers/gpio/gpio-tegra.c                         |   98 ++-
 drivers/mmc/host/sdhci-tegra.c                    |   24 +-
 drivers/pinctrl/pinctrl-tegra.c                   |    6 +-
 drivers/usb/host/ehci-tegra.c                     |   13 +-
 include/linux/platform_data/tegra_usb.h           |    1 +
 30 files changed, 1887 insertions(+), 3224 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
 delete mode 100644 arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
 delete mode 100644 arch/arm/mach-tegra/include/mach/pinmux.h
 delete mode 100644 arch/arm/mach-tegra/pinmux-tegra20-tables.c
 delete mode 100644 arch/arm/mach-tegra/pinmux-tegra30-tables.c
 delete mode 100644 arch/arm/mach-tegra/pinmux.c



From swarren at wwwdotorg.org  Fri Mar 30 18:59:54 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 16:59:54 -0600
Subject: [PATCH 01/11] usb: ehci-tegra: Add vbus_gpio to platform data
In-Reply-To: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1333148404-17691-2-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Add a vbus_gpio field to platform data. This mirrors the device tree
property nvidia,vbus-gpio. This makes the VBUS GPIO handling identical
between booting with board files and device tree; the driver always does
it.

This removes the need for board files to request and initialize the GPIO
early during their boot process, perhaps even before the GPIO driver is
ready to process the request.

Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
Cc: Alan Stern <stern at rowland.harvard.edu>
Cc: linux-usb at vger.kernel.org
Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/mach-tegra/devices.c           |    3 +++
 drivers/usb/host/ehci-tegra.c           |   13 +++++++------
 include/linux/platform_data/tegra_usb.h |    1 +
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index c3b9900..fcd872d 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -448,17 +448,20 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
 struct tegra_ehci_platform_data tegra_ehci1_pdata = {
 	.operating_mode = TEGRA_USB_OTG,
 	.power_down_on_bus_suspend = 1,
+	.vbus_gpio = -1,
 };
 
 struct tegra_ehci_platform_data tegra_ehci2_pdata = {
 	.phy_config = &tegra_ehci2_ulpi_phy_config,
 	.operating_mode = TEGRA_USB_HOST,
 	.power_down_on_bus_suspend = 1,
+	.vbus_gpio = -1,
 };
 
 struct tegra_ehci_platform_data tegra_ehci3_pdata = {
 	.operating_mode = TEGRA_USB_HOST,
 	.power_down_on_bus_suspend = 1,
+	.vbus_gpio = -1,
 };
 
 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 3de48a2..faed4c4 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -579,15 +579,16 @@ static const struct hc_driver tegra_ehci_hc_driver = {
 	.port_handed_over	= ehci_port_handed_over,
 };
 
-static int setup_vbus_gpio(struct platform_device *pdev)
+static int setup_vbus_gpio(struct platform_device *pdev,
+			   struct tegra_ehci_platform_data *pdata)
 {
 	int err = 0;
 	int gpio;
 
-	if (!pdev->dev.of_node)
-		return 0;
-
-	gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0);
+	gpio = pdata->vbus_gpio;
+	if (!gpio_is_valid(gpio))
+		gpio = of_get_named_gpio(pdev->dev.of_node,
+					 "nvidia,vbus-gpio", 0);
 	if (!gpio_is_valid(gpio))
 		return 0;
 
@@ -631,7 +632,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
 	if (!pdev->dev.dma_mask)
 		pdev->dev.dma_mask = &tegra_ehci_dma_mask;
 
-	setup_vbus_gpio(pdev);
+	setup_vbus_gpio(pdev, pdata);
 
 	tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
 	if (!tegra)
diff --git a/include/linux/platform_data/tegra_usb.h b/include/linux/platform_data/tegra_usb.h
index 6bca5b5..66c673f 100644
--- a/include/linux/platform_data/tegra_usb.h
+++ b/include/linux/platform_data/tegra_usb.h
@@ -26,6 +26,7 @@ struct tegra_ehci_platform_data {
 	/* power down the phy on bus suspend */
 	int power_down_on_bus_suspend;
 	void *phy_config;
+	int vbus_gpio;
 };
 
 #endif /* _TEGRA_USB_H_ */
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Mar 30 18:59:55 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 16:59:55 -0600
Subject: [PATCH 02/11] ARM: tegra: Remove VBUS_GPIO handling from board files
In-Reply-To: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1333148404-17691-3-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Instead of having board files manually request and initialize USB VBUS
GPIOs, fill in the USB driver's platform data and have it do it.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/mach-tegra/board-seaboard.c  |   17 ++++-------------
 arch/arm/mach-tegra/board-trimslice.c |   15 +++++----------
 2 files changed, 9 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index 0e2957f..e6642c6 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
+#include <linux/platform_data/tegra_usb.h>
 
 #include <sound/wm8903.h>
 
@@ -185,20 +186,10 @@ static struct i2c_board_info __initdata wm8903_device = {
 
 static int seaboard_ehci_init(void)
 {
-	int gpio_status;
+	struct tegra_ehci_platform_data *pdata;
 
-	gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1");
-	if (gpio_status < 0) {
-		pr_err("VBUS_USB1 request GPIO FAILED\n");
-		WARN_ON(1);
-	}
-
-	gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1);
-	if (gpio_status < 0) {
-		pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n");
-		WARN_ON(1);
-	}
-	gpio_set_value(TEGRA_GPIO_USB1, 1);
+	pdata = tegra_ehci1_device.dev.platform_data;
+	pdata->vbus_gpio = TEGRA_GPIO_USB1;
 
 	platform_device_register(&tegra_ehci1_device);
 	platform_device_register(&tegra_ehci3_device);
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index ba2e047..7a21cf5 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -25,6 +25,7 @@
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/tegra_usb.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
@@ -110,19 +111,13 @@ static void trimslice_i2c_init(void)
 
 static void trimslice_usb_init(void)
 {
-	int err;
+	struct tegra_ehci_platform_data *pdata;
 
-	platform_device_register(&tegra_ehci3_device);
+	pdata = tegra_ehci1_device.dev.platform_data;
+	pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
 
+	platform_device_register(&tegra_ehci3_device);
 	platform_device_register(&tegra_ehci2_device);
-
-	err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH,
-			       "usb1mode");
-	if (err) {
-		pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err);
-		return;
-	}
-
 	platform_device_register(&tegra_ehci1_device);
 }
 
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Mar 30 18:59:56 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 16:59:56 -0600
Subject: [PATCH 03/11] gpio: tegra: fix register address calculations for
 Tegra30
In-Reply-To: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1333148404-17691-4-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Tegra20 and Tegra30 share the same register layout within registers, but
the addresses of the registers is a little different. Fix the driver to
cope with this.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 drivers/gpio/gpio-tegra.c |   55 ++++++++++++++++++++++++++++++++++----------
 1 files changed, 42 insertions(+), 13 deletions(-)

diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 32de670..7d05a34 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -22,7 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
-#include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/module.h>
 #include <linux/irqdomain.h>
@@ -37,7 +37,8 @@
 #define GPIO_PORT(x)		(((x) >> 3) & 0x3)
 #define GPIO_BIT(x)		((x) & 0x7)
 
-#define GPIO_REG(x)		(GPIO_BANK(x) * 0x80 + GPIO_PORT(x) * 4)
+#define GPIO_REG(x)		(GPIO_BANK(x) * tegra_gpio_bank_stride + \
+					GPIO_PORT(x) * 4)
 
 #define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
 #define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
@@ -48,12 +49,12 @@
 #define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
 #define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)
 
-#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + 0x800)
-#define GPIO_MSK_OE(x)		(GPIO_REG(x) + 0x810)
-#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + 0X820)
-#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + 0x840)
-#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + 0x850)
-#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + 0x860)
+#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
+#define GPIO_MSK_OE(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
+#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
+#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
+#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
+#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
 
 #define GPIO_INT_LVL_MASK		0x010101
 #define GPIO_INT_LVL_EDGE_RISING	0x000101
@@ -78,6 +79,8 @@ struct tegra_gpio_bank {
 static struct irq_domain *irq_domain;
 static void __iomem *regs;
 static u32 tegra_gpio_bank_count;
+static u32 tegra_gpio_bank_stride;
+static u32 tegra_gpio_upper_offset;
 static struct tegra_gpio_bank *tegra_gpio_banks;
 
 static inline void tegra_gpio_writel(u32 val, u32 reg)
@@ -333,6 +336,26 @@ static struct irq_chip tegra_gpio_irq_chip = {
 #endif
 };
 
+struct tegra_gpio_soc_config {
+	u32 bank_stride;
+	u32 upper_offset;
+};
+
+static struct tegra_gpio_soc_config tegra20_gpio_config = {
+	.bank_stride = 0x80,
+	.upper_offset = 0x800,
+};
+
+static struct tegra_gpio_soc_config tegra30_gpio_config = {
+	.bank_stride = 0x100,
+	.upper_offset = 0x80,
+};
+
+static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
+	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
+	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
+	{ },
+};
 
 /* This lock class tells lockdep that GPIO irqs are in a different
  * category than their parents, so it won't report false recursion.
@@ -341,6 +364,8 @@ static struct lock_class_key gpio_lock_class;
 
 static int __devinit tegra_gpio_probe(struct platform_device *pdev)
 {
+	const struct of_device_id *match;
+	struct tegra_gpio_soc_config *config;
 	int irq_base;
 	struct resource *res;
 	struct tegra_gpio_bank *bank;
@@ -348,6 +373,15 @@ static int __devinit tegra_gpio_probe(struct platform_device *pdev)
 	int i;
 	int j;
 
+	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
+	if (match)
+		config = (struct tegra_gpio_soc_config *)match->data;
+	else
+		config = &tegra20_gpio_config;
+
+	tegra_gpio_bank_stride = config->bank_stride;
+	tegra_gpio_upper_offset = config->upper_offset;
+
 	for (;;) {
 		res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
 		if (!res)
@@ -441,11 +475,6 @@ static int __devinit tegra_gpio_probe(struct platform_device *pdev)
 	return 0;
 }
 
-static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
-	{ .compatible = "nvidia,tegra20-gpio", },
-	{ },
-};
-
 static struct platform_driver tegra_gpio_driver = {
 	.driver		= {
 		.name	= "tegra-gpio",
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Mar 30 18:59:57 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 16:59:57 -0600
Subject: [PATCH 04/11] gpio: tegra: Iterate over the correct number of banks
In-Reply-To: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1333148404-17691-5-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

When Tegra30 support was added to the Tegra GPIO driver, a few places
which iterated over all banks were not converted to use the variable
tegra_gpio_bank_count rather than hard-coding the bank count. Fix this.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 drivers/gpio/gpio-tegra.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 7d05a34..12f349b 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -436,7 +436,7 @@ static int __devinit tegra_gpio_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	for (i = 0; i < 7; i++) {
+	for (i = 0; i < tegra_gpio_bank_count; i++) {
 		for (j = 0; j < 4; j++) {
 			int gpio = tegra_gpio_compose(i, j, 0);
 			tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
@@ -514,7 +514,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
 	int i;
 	int j;
 
-	for (i = 0; i < 7; i++) {
+	for (i = 0; i < tegra_gpio_bank_count; i++) {
 		for (j = 0; j < 4; j++) {
 			int gpio = tegra_gpio_compose(i, j, 0);
 			seq_printf(s,
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Mar 30 18:59:58 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 16:59:58 -0600
Subject: [PATCH 05/11] gpio: tegra: configure pins during irq_set_type
In-Reply-To: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1333148404-17691-6-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

When a Tegra GPIO is used as an IRQ, it should be enabled as a GPIO (so
the pinmux module isn't driving it as an output) and configured as a GPIO
input (so the GPIO module isn't driving it as an output). Set this up
automatically whenever an IRQ is requested, so that users of IRQs don't
need to do this.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 drivers/gpio/gpio-tegra.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 12f349b..4383a72 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -224,6 +224,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 
 	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 
+	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
+	tegra_gpio_enable(gpio);
+
 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 		__irq_set_handler_locked(d->irq, handle_level_irq);
 	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Mar 30 18:59:59 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 16:59:59 -0600
Subject: [PATCH 06/11] ARM: tegra: seaboard: Don't gpio_request() ISL29018_IRQ
In-Reply-To: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1333148404-17691-7-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Don't call gpio_request() or gpio_direction_input() for ISL29018_IRQ.
This pin is only used as an IRQ, and hence no GPIO configuration should
be necessary; the GPIO/IRQ driver should (and does) perform any required
setup when the IRQ is requested.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/mach-tegra/board-seaboard.c |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index e6642c6..0b2b9ce 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -199,9 +199,6 @@ static int seaboard_ehci_init(void)
 
 static void __init seaboard_i2c_init(void)
 {
-	gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
-	gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
-
 	isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
 	i2c_register_board_info(0, &isl29018_device, 1);
 
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Mar 30 19:00:00 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 17:00:00 -0600
Subject: [PATCH 07/11] gpio: tegra: Hide tegra_gpio_enable/disable()
In-Reply-To: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1333148404-17691-8-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

Recent pinctrl discussions concluded that gpiolib APIs should in fact do
whatever is required to mux a GPIO onto pins, by calling pinctrl APIs if
required. This change implements this for the Tegra GPIO driver, and removes
calls to the Tegra-specific APIs from drivers and board files.

Cc: Chris Ball <cjb at laptop.org>
Cc: linux-mmc at vger.kernel.org
Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
v2: Adjusted per changes to latest version of Documentation/gpio.txt.
Fixed tegra_board_pinmux_bus_notify() to still check the device name,
so it waits for the pinmux device to be registered, not just /any/ device.
---
 arch/arm/mach-tegra/board-dt-tegra20.c        |    1 -
 arch/arm/mach-tegra/board-harmony-pinmux.c    |   17 -----------
 arch/arm/mach-tegra/board-paz00-pinmux.c      |   14 ---------
 arch/arm/mach-tegra/board-pinmux.c            |   33 +++--------------------
 arch/arm/mach-tegra/board-pinmux.h            |    5 ---
 arch/arm/mach-tegra/board-seaboard-pinmux.c   |   32 ----------------------
 arch/arm/mach-tegra/board-seaboard.c          |    1 -
 arch/arm/mach-tegra/board-trimslice-pinmux.c  |   12 --------
 arch/arm/mach-tegra/include/mach/gpio-tegra.h |    9 ------
 arch/arm/mach-tegra/usb_phy.c                 |    1 -
 drivers/gpio/gpio-tegra.c                     |   36 ++++++++++++------------
 drivers/mmc/host/sdhci-tegra.c                |   24 +++-------------
 12 files changed, 27 insertions(+), 158 deletions(-)

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 0952494..65a5249 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -55,7 +55,6 @@ void ventana_pinmux_init(void);
 
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
-	OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 1af85bc..3ebe2c8 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -15,13 +15,11 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/gpio.h>
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
 #include <mach/pinmux-tegra20.h>
 
-#include "gpio-names.h"
 #include "board-harmony.h"
 #include "board-pinmux.h"
 
@@ -144,24 +142,9 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static struct tegra_gpio_table gpio_table[] = {
-	{ .gpio = TEGRA_GPIO_SD2_CD,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_SD2_WP,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_SD2_POWER,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_SD4_CD,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_SD4_WP,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_SD4_POWER,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_CDC_IRQ,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_HP_DET,		.enable = true	},
-	{ .gpio = TEGRA_GPIO_INT_MIC_EN,	.enable = true	},
-	{ .gpio = TEGRA_GPIO_EXT_MIC_EN,	.enable = true	},
-};
-
 static struct tegra_board_pinmux_conf conf = {
 	.pgs = harmony_pinmux,
 	.pg_count = ARRAY_SIZE(harmony_pinmux),
-	.gpios = gpio_table,
-	.gpio_count = ARRAY_SIZE(gpio_table),
 };
 
 void harmony_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index c775572..f0ec466 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -15,13 +15,11 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/gpio.h>
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
 #include <mach/pinmux-tegra20.h>
 
-#include "gpio-names.h"
 #include "board-paz00.h"
 #include "board-pinmux.h"
 
@@ -144,21 +142,9 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
 	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static struct tegra_gpio_table gpio_table[] = {
-	{ .gpio = TEGRA_GPIO_SD1_CD,	.enable = true },
-	{ .gpio = TEGRA_GPIO_SD1_WP,	.enable = true },
-	{ .gpio = TEGRA_GPIO_SD1_POWER,	.enable = true },
-	{ .gpio = TEGRA_ULPI_RST,	.enable = true },
-	{ .gpio = TEGRA_WIFI_PWRN,	.enable = true },
-	{ .gpio = TEGRA_WIFI_RST,	.enable = true },
-	{ .gpio = TEGRA_WIFI_LED,	.enable = true },
-};
-
 static struct tegra_board_pinmux_conf conf = {
 	.pgs = paz00_pinmux,
 	.pg_count = ARRAY_SIZE(paz00_pinmux),
-	.gpios = gpio_table,
-	.gpio_count = ARRAY_SIZE(gpio_table),
 };
 
 void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
index adc3efe..3015b5a 100644
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -18,7 +18,6 @@
 #include <linux/of.h>
 #include <linux/string.h>
 
-#include <mach/gpio-tegra.h>
 #include <mach/pinmux.h>
 
 #include "board-pinmux.h"
@@ -26,18 +25,6 @@
 
 struct tegra_board_pinmux_conf *confs[2];
 
-static void tegra_board_pinmux_setup_gpios(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(confs); i++) {
-		if (!confs[i])
-			continue;
-
-		tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
-	}
-}
-
 static void tegra_board_pinmux_setup_pinmux(void)
 {
 	int i;
@@ -57,29 +44,17 @@ static void tegra_board_pinmux_setup_pinmux(void)
 static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
 					 unsigned long event, void *vdev)
 {
-	static bool had_gpio;
-	static bool had_pinmux;
-
 	struct device *dev = vdev;
-	const char *devname;
 
 	if (event != BUS_NOTIFY_BOUND_DRIVER)
 		return NOTIFY_DONE;
 
-	devname = dev_name(dev);
+	if (strcmp(dev_name(dev), PINMUX_DEV))
+		return NOTIFY_DONE;
 
-	if (!had_gpio && !strcmp(devname, GPIO_DEV)) {
-		tegra_board_pinmux_setup_gpios();
-		had_gpio = true;
-	} else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
-		tegra_board_pinmux_setup_pinmux();
-		had_pinmux = true;
-	}
+	tegra_board_pinmux_setup_pinmux();
 
-	if (had_gpio && had_pinmux)
-		return NOTIFY_STOP_MASK;
-	else
-		return NOTIFY_DONE;
+	return NOTIFY_STOP_MASK;
 }
 
 static struct notifier_block nb = {
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
index 4aac735..e08214d 100644
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -15,11 +15,9 @@
 #ifndef __MACH_TEGRA_BOARD_PINMUX_H
 #define __MACH_TEGRA_BOARD_PINMUX_H
 
-#define GPIO_DEV "tegra-gpio"
 #define PINMUX_DEV "tegra-pinmux"
 
 struct tegra_pingroup_config;
-struct tegra_gpio_table;
 
 struct tegra_board_pinmux_conf {
 	struct tegra_pingroup_config *pgs;
@@ -27,9 +25,6 @@ struct tegra_board_pinmux_conf {
 
 	struct tegra_drive_pingroup_config *drives;
 	int drive_count;
-
-	struct tegra_gpio_table *gpios;
-	int gpio_count;
 };
 
 void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 55e7e43..3bf7e97 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -15,13 +15,11 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/gpio.h>
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
 #include <mach/pinmux-tegra20.h>
 
-#include "gpio-names.h"
 #include "board-pinmux.h"
 #include "board-seaboard.h"
 
@@ -179,35 +177,9 @@ static struct tegra_pingroup_config ventana_pinmux[] = {
 	{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 };
 
-static struct tegra_gpio_table common_gpio_table[] = {
-	{ .gpio = TEGRA_GPIO_SD2_CD,		.enable = true },
-	{ .gpio = TEGRA_GPIO_SD2_WP,		.enable = true },
-	{ .gpio = TEGRA_GPIO_SD2_POWER,		.enable = true },
-	{ .gpio = TEGRA_GPIO_CDC_IRQ,		.enable = true },
-};
-
-static struct tegra_gpio_table seaboard_gpio_table[] = {
-	{ .gpio = TEGRA_GPIO_LIDSWITCH,		.enable = true },
-	{ .gpio = TEGRA_GPIO_POWERKEY,		.enable = true },
-	{ .gpio = TEGRA_GPIO_HP_DET,		.enable = true },
-	{ .gpio = TEGRA_GPIO_ISL29018_IRQ,	.enable = true },
-	{ .gpio = TEGRA_GPIO_USB1,		.enable = true },
-};
-
-static struct tegra_gpio_table ventana_gpio_table[] = {
-	/* hp_det */
-	{ .gpio = TEGRA_GPIO_PW2,		.enable = true },
-	/* int_mic_en */
-	{ .gpio = TEGRA_GPIO_PX0,		.enable = true },
-	/* ext_mic_en */
-	{ .gpio = TEGRA_GPIO_PX1,		.enable = true },
-};
-
 static struct tegra_board_pinmux_conf common_conf = {
 	.pgs = common_pinmux,
 	.pg_count = ARRAY_SIZE(common_pinmux),
-	.gpios = common_gpio_table,
-	.gpio_count = ARRAY_SIZE(common_gpio_table),
 };
 
 static struct tegra_board_pinmux_conf seaboard_conf = {
@@ -215,15 +187,11 @@ static struct tegra_board_pinmux_conf seaboard_conf = {
 	.pg_count = ARRAY_SIZE(seaboard_pinmux),
 	.drives = seaboard_drive_pinmux,
 	.drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
-	.gpios = seaboard_gpio_table,
-	.gpio_count = ARRAY_SIZE(seaboard_gpio_table),
 };
 
 static struct tegra_board_pinmux_conf ventana_conf = {
 	.pgs = ventana_pinmux,
 	.pg_count = ARRAY_SIZE(ventana_pinmux),
-	.gpios = ventana_gpio_table,
-	.gpio_count = ARRAY_SIZE(ventana_gpio_table),
 };
 
 void seaboard_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index 0b2b9ce..a31e0d8 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -248,7 +248,6 @@ static void __init tegra_kaen_init(void)
 	debug_uart_platform_data[0].irq = INT_UARTB;
 
 	seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
-	tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
 
 	seaboard_common_init();
 
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index a21a2be..a1902d4 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  *
  */
-#include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/of.h>
@@ -21,7 +20,6 @@
 #include <mach/pinmux.h>
 #include <mach/pinmux-tegra20.h>
 
-#include "gpio-names.h"
 #include "board-pinmux.h"
 #include "board-trimslice.h"
 
@@ -144,19 +142,9 @@ static struct tegra_pingroup_config trimslice_pinmux[] = {
 	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
 };
 
-static struct tegra_gpio_table gpio_table[] = {
-	{ .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true	}, /* mmc4 cd */
-	{ .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true	}, /* mmc4 wp */
-
-	{ .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */
-	{ .gpio = TRIMSLICE_GPIO_USB2_RST,  .enable = true }, /* USB2 PHY rst */
-};
-
 static struct tegra_board_pinmux_conf conf = {
 	.pgs = trimslice_pinmux,
 	.pg_count = ARRAY_SIZE(trimslice_pinmux),
-	.gpios = gpio_table,
-	.gpio_count = ARRAY_SIZE(gpio_table),
 };
 
 void trimslice_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
index 6140820..a978b3c 100644
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
@@ -25,13 +25,4 @@
 
 #define TEGRA_NR_GPIOS		INT_GPIO_NR
 
-struct tegra_gpio_table {
-	int	gpio;	/* GPIO number */
-	bool	enable;	/* Enable for GPIO at init? */
-};
-
-void tegra_gpio_config(struct tegra_gpio_table *table, int num);
-void tegra_gpio_enable(int gpio);
-void tegra_gpio_disable(int gpio);
-
 #endif
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index c5b2ac0..d71d2fe 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -711,7 +711,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
 			err = -ENXIO;
 			goto err1;
 		}
-		tegra_gpio_enable(ulpi_config->reset_gpio);
 		gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
 		gpio_direction_output(ulpi_config->reset_gpio, 0);
 		phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 4383a72..dc5184d 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -26,10 +26,10 @@
 #include <linux/platform_device.h>
 #include <linux/module.h>
 #include <linux/irqdomain.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <asm/mach/irq.h>
 
-#include <mach/gpio-tegra.h>
 #include <mach/iomap.h>
 #include <mach/suspend.h>
 
@@ -108,18 +108,29 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
 	tegra_gpio_writel(val, reg);
 }
 
-void tegra_gpio_enable(int gpio)
+static void tegra_gpio_enable(int gpio)
 {
 	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 }
 EXPORT_SYMBOL_GPL(tegra_gpio_enable);
 
-void tegra_gpio_disable(int gpio)
+static void tegra_gpio_disable(int gpio)
 {
 	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 }
 EXPORT_SYMBOL_GPL(tegra_gpio_disable);
 
+int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	return pinctrl_request_gpio(offset);
+}
+
+void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+	pinctrl_free_gpio(offset);
+	tegra_gpio_disable(offset);
+}
+
 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
 	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
@@ -133,6 +144,7 @@ static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
 	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
+	tegra_gpio_enable(offset);
 	return 0;
 }
 
@@ -141,6 +153,7 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 {
 	tegra_gpio_set(chip, offset, value);
 	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
+	tegra_gpio_enable(offset);
 	return 0;
 }
 
@@ -151,13 +164,14 @@ static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 
 static struct gpio_chip tegra_gpio_chip = {
 	.label			= "tegra-gpio",
+	.request		= tegra_gpio_request,
+	.free			= tegra_gpio_free,
 	.direction_input	= tegra_gpio_direction_input,
 	.get			= tegra_gpio_get,
 	.direction_output	= tegra_gpio_direction_output,
 	.set			= tegra_gpio_set,
 	.to_irq			= tegra_gpio_to_irq,
 	.base			= 0,
-	.ngpio			= TEGRA_NR_GPIOS,
 };
 
 static void tegra_gpio_irq_ack(struct irq_data *d)
@@ -493,20 +507,6 @@ static int __init tegra_gpio_init(void)
 }
 postcore_initcall(tegra_gpio_init);
 
-void tegra_gpio_config(struct tegra_gpio_table *table, int num)
-{
-	int i;
-
-	for (i = 0; i < num; i++) {
-		int gpio = table[i].gpio;
-
-		if (table[i].enable)
-			tegra_gpio_enable(gpio);
-		else
-			tegra_gpio_disable(gpio);
-	}
-}
-
 #ifdef	CONFIG_DEBUG_FS
 
 #include <linux/debugfs.h>
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 53b2650..ff5a169 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -269,7 +269,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
 				"failed to allocate power gpio\n");
 			goto err_power_req;
 		}
-		tegra_gpio_enable(plat->power_gpio);
 		gpio_direction_output(plat->power_gpio, 1);
 	}
 
@@ -280,7 +279,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
 				"failed to allocate cd gpio\n");
 			goto err_cd_req;
 		}
-		tegra_gpio_enable(plat->cd_gpio);
 		gpio_direction_input(plat->cd_gpio);
 
 		rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
@@ -301,7 +299,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
 				"failed to allocate wp gpio\n");
 			goto err_wp_req;
 		}
-		tegra_gpio_enable(plat->wp_gpio);
 		gpio_direction_input(plat->wp_gpio);
 	}
 
@@ -329,23 +326,17 @@ err_add_host:
 	clk_disable(pltfm_host->clk);
 	clk_put(pltfm_host->clk);
 err_clk_get:
-	if (gpio_is_valid(plat->wp_gpio)) {
-		tegra_gpio_disable(plat->wp_gpio);
+	if (gpio_is_valid(plat->wp_gpio))
 		gpio_free(plat->wp_gpio);
-	}
 err_wp_req:
 	if (gpio_is_valid(plat->cd_gpio))
 		free_irq(gpio_to_irq(plat->cd_gpio), host);
 err_cd_irq_req:
-	if (gpio_is_valid(plat->cd_gpio)) {
-		tegra_gpio_disable(plat->cd_gpio);
+	if (gpio_is_valid(plat->cd_gpio))
 		gpio_free(plat->cd_gpio);
-	}
 err_cd_req:
-	if (gpio_is_valid(plat->power_gpio)) {
-		tegra_gpio_disable(plat->power_gpio);
+	if (gpio_is_valid(plat->power_gpio))
 		gpio_free(plat->power_gpio);
-	}
 err_power_req:
 err_no_plat:
 	sdhci_pltfm_free(pdev);
@@ -362,21 +353,16 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
 
 	sdhci_remove_host(host, dead);
 
-	if (gpio_is_valid(plat->wp_gpio)) {
-		tegra_gpio_disable(plat->wp_gpio);
+	if (gpio_is_valid(plat->wp_gpio))
 		gpio_free(plat->wp_gpio);
-	}
 
 	if (gpio_is_valid(plat->cd_gpio)) {
 		free_irq(gpio_to_irq(plat->cd_gpio), host);
-		tegra_gpio_disable(plat->cd_gpio);
 		gpio_free(plat->cd_gpio);
 	}
 
-	if (gpio_is_valid(plat->power_gpio)) {
-		tegra_gpio_disable(plat->power_gpio);
+	if (gpio_is_valid(plat->power_gpio))
 		gpio_free(plat->power_gpio);
-	}
 
 	clk_disable(pltfm_host->clk);
 	clk_put(pltfm_host->clk);
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Mar 30 19:00:01 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 17:00:01 -0600
Subject: [PATCH 08/11] ARM: tegra: Switch to new pinctrl driver
In-Reply-To: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1333148404-17691-9-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

* Rename old pinmux and new pinctrl platform driver and DT match table
  entries, so the new driver gets instantiated.
* Re-write board-pinmux.c, so that it uses pinctrl APIs to configura the
  pinmux.
* Re-write board-*-pinmux.c so that the pinmux configuration tables are
  in pinctrl format.

Ventana's pin mux table needed some edits on top of the basic format
conversion, since some mux options that were previously marked as
reserved are now valid in the new pinctrl driver. Attempting to use the
old reserved names will result in a failure. Specifically, groups lpw0,
lpw2, lsc1, lsck, and lsda were changed from function rsvd4 to displaya,
and group pta was changed from function rsvd2 to hdmi.

All boards' pin mux tables needed some edits on top of the based format
conversion, since function i2c was split into i2c1 (first general I2C
controller) and i2cp (power I2C controller) to better align function
definitions with HW blocks.

Due to the split of mux tables into pure mux and pull/tristate tables,
many entries in the separate Seaboard/Ventana tables could be merged
into the common table, since the entries differed only in the portion
in one of the tables, not both.

Most pin groups allow configuration of mux, tri-state, and pull. However,
some don't allow pull configuration, which is instead configured by new
groups that only allow pull configuration. This is a reflection of the
true HW capabilities, which weren't fully represented by the old pinmux
driver. This required adding new pull table entries for those new groups,
and setting many other entries' pull configuration to
TEGRA_PINCONFIG_DONT_SET.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
v3: Remove GPIO-related code, use mapping table instead of pinctrl APIs
    for all pinconfig setup. Don't tristate PCIe pingroups on Harmony.
    Note: Before this version, this patch had the following acks, but I've
    removed them due to the rework:
    Linus Walleij <linus.walleij at linaro.org>
    Olof Johansson <olof at lixom.net>
v2: No change?
---
 arch/arm/mach-tegra/board-harmony-pinmux.c   |  249 ++++++++++----------
 arch/arm/mach-tegra/board-paz00-pinmux.c     |  249 ++++++++++----------
 arch/arm/mach-tegra/board-pinmux.c           |   76 ++++---
 arch/arm/mach-tegra/board-pinmux.h           |   35 +++-
 arch/arm/mach-tegra/board-seaboard-pinmux.c  |  314 +++++++++++++-------------
 arch/arm/mach-tegra/board-trimslice-pinmux.c |  252 +++++++++++----------
 arch/arm/mach-tegra/pinmux.c                 |    6 +-
 drivers/pinctrl/pinctrl-tegra.c              |    6 +-
 8 files changed, 609 insertions(+), 578 deletions(-)

diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 3ebe2c8..83d420f 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/board-harmony-pinmux.c
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -15,136 +16,138 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/of.h>
-
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
 
 #include "board-harmony.h"
 #include "board-pinmux.h"
 
-static struct tegra_pingroup_config harmony_pinmux[] = {
-	{TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTA,   TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTB,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTC,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTD,   TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTE,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMC,   TEGRA_MUX_UARTD,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LCSN,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSCK,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSDA,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSDI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+static struct pinctrl_map harmony_map[] = {
+	TEGRA_MAP_MUXCONF("ata",   "ide",           none, driven),
+	TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
+	TEGRA_MAP_MUXCONF("atc",   "nand",          none, driven),
+	TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
+	TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
+	TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
+	TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
+	TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
+	TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
+	TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
+	TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
+	TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
+	TEGRA_MAP_MUXCONF("dta",   "sdio2",         up,   driven),
+	TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, driven),
+	TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
+	TEGRA_MAP_MUXCONF("dtd",   "sdio2",         up,   driven),
+	TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
+	TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, tristate),
+	TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
+	TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("gmc",   "uartd",         none, driven),
+	TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
+	TEGRA_MAP_MUXCONF("gpu",   "gmi",           none, tristate),
+	TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
+	TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
+	TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
+	TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
+	TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   tristate),
+	TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   tristate),
+	TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("owc",   "rsvd2",         na,   tristate),
+	TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
+	TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
+	TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
+	TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
+	TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
+	TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
+	TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, tristate),
+	TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
+	TEGRA_MAP_MUXCONF("slxc",  "spdif",         none, tristate),
+	TEGRA_MAP_MUXCONF("slxd",  "spdif",         none, tristate),
+	TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
+	TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
+	TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, tristate),
+	TEGRA_MAP_MUXCONF("spia",  "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("spib",  "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   tristate),
+	TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
+	TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
+	TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
+	TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      none, tristate),
+	TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
+	TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
+	TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
+	TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, tristate),
+	TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
+	TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
+	TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
+	TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
+	TEGRA_MAP_CONF("ck32",    none, na),
+	TEGRA_MAP_CONF("ddrc",    none, na),
+	TEGRA_MAP_CONF("pmca",    none, na),
+	TEGRA_MAP_CONF("pmcb",    none, na),
+	TEGRA_MAP_CONF("pmcc",    none, na),
+	TEGRA_MAP_CONF("pmcd",    none, na),
+	TEGRA_MAP_CONF("pmce",    none, na),
+	TEGRA_MAP_CONF("xm2c",    none, na),
+	TEGRA_MAP_CONF("xm2d",    none, na),
+	TEGRA_MAP_CONF("ls",      up,   na),
+	TEGRA_MAP_CONF("lc",      up,   na),
+	TEGRA_MAP_CONF("ld17_0",  down, na),
+	TEGRA_MAP_CONF("ld19_18", down, na),
+	TEGRA_MAP_CONF("ld21_20", down, na),
+	TEGRA_MAP_CONF("ld23_22", down, na),
 };
 
 static struct tegra_board_pinmux_conf conf = {
-	.pgs = harmony_pinmux,
-	.pg_count = ARRAY_SIZE(harmony_pinmux),
+	.maps = harmony_map,
+	.map_count = ARRAY_SIZE(harmony_map),
 };
 
 void harmony_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index f0ec466..6f1111b 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/board-paz00-pinmux.c
  *
  * Copyright (C) 2010 Marc Dietrich <marvin24 at gmx.de>
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -15,136 +16,138 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/of.h>
-
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
 
 #include "board-paz00.h"
 #include "board-pinmux.h"
 
-static struct tegra_pingroup_config paz00_pinmux[] = {
-	{TEGRA_PINGROUP_ATA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATC,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_CSUS,  TEGRA_MUX_PLLC_OUT1,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DAP2,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTA,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTB,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTC,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTD,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTE,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMC,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCB,  TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCD,  TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LCSN,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSCK,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSDA,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSDI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_OWC,   TEGRA_MUX_OWR,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_TWC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPI4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPI4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPID,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIE,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIF,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_UAD,   TEGRA_MUX_SPDIF,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+static struct pinctrl_map paz00_map[] = {
+	TEGRA_MAP_MUXCONF("ata",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
+	TEGRA_MAP_MUXCONF("atc",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
+	TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, driven),
+	TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
+	TEGRA_MAP_MUXCONF("csus",  "pllc_out1",     down, tristate),
+	TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
+	TEGRA_MAP_MUXCONF("dap2",  "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
+	TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
+	TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
+	TEGRA_MAP_MUXCONF("dta",   "rsvd1",         up,   tristate),
+	TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, tristate),
+	TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
+	TEGRA_MAP_MUXCONF("dtd",   "rsvd1",         up,   tristate),
+	TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
+	TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
+	TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
+	TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("gmc",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
+	TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
+	TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
+	TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
+	TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   driven),
+	TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
+	TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   driven),
+	TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   driven),
+	TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbcb",  "sdio2",         up,   driven),
+	TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbcd",  "sdio2",         up,   driven),
+	TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("owc",   "owr",           up,   tristate),
+	TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
+	TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
+	TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
+	TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
+	TEGRA_MAP_MUXCONF("sdc",   "twc",           up,   tristate),
+	TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
+	TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
+	TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, tristate),
+	TEGRA_MAP_MUXCONF("slxc",  "spi4",          none, tristate),
+	TEGRA_MAP_MUXCONF("slxd",  "spi4",          none, tristate),
+	TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
+	TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
+	TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
+	TEGRA_MAP_MUXCONF("spia",  "gmi",           down, tristate),
+	TEGRA_MAP_MUXCONF("spib",  "gmi",           down, tristate),
+	TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
+	TEGRA_MAP_MUXCONF("spid",  "gmi",           down, tristate),
+	TEGRA_MAP_MUXCONF("spie",  "gmi",           up,   tristate),
+	TEGRA_MAP_MUXCONF("spif",  "rsvd4",         down, tristate),
+	TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   driven),
+	TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
+	TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
+	TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
+	TEGRA_MAP_MUXCONF("uac",   "rsvd4",         none, driven),
+	TEGRA_MAP_MUXCONF("uad",   "spdif",         up,   tristate),
+	TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
+	TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
+	TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
+	TEGRA_MAP_CONF("ck32",    none, na),
+	TEGRA_MAP_CONF("ddrc",    none, na),
+	TEGRA_MAP_CONF("pmca",    none, na),
+	TEGRA_MAP_CONF("pmcb",    none, na),
+	TEGRA_MAP_CONF("pmcc",    none, na),
+	TEGRA_MAP_CONF("pmcd",    none, na),
+	TEGRA_MAP_CONF("pmce",    none, na),
+	TEGRA_MAP_CONF("xm2c",    none, na),
+	TEGRA_MAP_CONF("xm2d",    none, na),
+	TEGRA_MAP_CONF("ls",      up,   na),
+	TEGRA_MAP_CONF("lc",      up,   na),
+	TEGRA_MAP_CONF("ld17_0",  down, na),
+	TEGRA_MAP_CONF("ld19_18", down, na),
+	TEGRA_MAP_CONF("ld21_20", down, na),
+	TEGRA_MAP_CONF("ld23_22", down, na),
 };
 
 static struct tegra_board_pinmux_conf conf = {
-	.pgs = paz00_pinmux,
-	.pg_count = ARRAY_SIZE(paz00_pinmux),
+	.maps = paz00_map,
+	.map_count = ARRAY_SIZE(paz00_map),
 };
 
 void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
index 3015b5a..3b7ad07 100644
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -18,47 +18,57 @@
 #include <linux/of.h>
 #include <linux/string.h>
 
-#include <mach/pinmux.h>
-
 #include "board-pinmux.h"
 #include "devices.h"
 
-struct tegra_board_pinmux_conf *confs[2];
+unsigned long tegra_pincfg_pullnone_driven[2] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
+};
 
-static void tegra_board_pinmux_setup_pinmux(void)
-{
-	int i;
+unsigned long tegra_pincfg_pullnone_tristate[2] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
+};
 
-	for (i = 0; i < ARRAY_SIZE(confs); i++) {
-		if (!confs[i])
-			continue;
+unsigned long tegra_pincfg_pullnone_na[1] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
+};
 
-		tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count);
+unsigned long tegra_pincfg_pullup_driven[2] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
+};
 
-		if (confs[i]->drives)
-			tegra_drive_pinmux_config_table(confs[i]->drives,
-							confs[i]->drive_count);
-	}
-}
+unsigned long tegra_pincfg_pullup_tristate[2] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
+};
 
-static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
-					 unsigned long event, void *vdev)
-{
-	struct device *dev = vdev;
+unsigned long tegra_pincfg_pullup_na[1] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
+};
 
-	if (event != BUS_NOTIFY_BOUND_DRIVER)
-		return NOTIFY_DONE;
+unsigned long tegra_pincfg_pulldown_driven[2] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
+};
 
-	if (strcmp(dev_name(dev), PINMUX_DEV))
-		return NOTIFY_DONE;
+unsigned long tegra_pincfg_pulldown_tristate[2] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
+};
 
-	tegra_board_pinmux_setup_pinmux();
+unsigned long tegra_pincfg_pulldown_na[1] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
+};
 
-	return NOTIFY_STOP_MASK;
-}
+unsigned long tegra_pincfg_pullna_driven[1] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
+};
 
-static struct notifier_block nb = {
-	.notifier_call = tegra_board_pinmux_bus_notify,
+unsigned long tegra_pincfg_pullna_tristate[1] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
 };
 
 static struct platform_device *devices[] = {
@@ -69,10 +79,10 @@ static struct platform_device *devices[] = {
 void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
 			     struct tegra_board_pinmux_conf *conf_b)
 {
-	confs[0] = conf_a;
-	confs[1] = conf_b;
-
-	bus_register_notifier(&platform_bus_type, &nb);
+	if (conf_a)
+		pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
+	if (conf_b)
+		pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
 
 	if (!of_machine_is_compatible("nvidia,tegra20"))
 		platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
index e08214d..45b5ad8 100644
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -15,16 +15,37 @@
 #ifndef __MACH_TEGRA_BOARD_PINMUX_H
 #define __MACH_TEGRA_BOARD_PINMUX_H
 
+#include <linux/pinctrl/machine.h>
+
+#include <mach/pinconf-tegra.h>
+
 #define PINMUX_DEV "tegra-pinmux"
 
-struct tegra_pingroup_config;
+#define TEGRA_MAP_MUX(_group_, _function_) \
+	PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
 
-struct tegra_board_pinmux_conf {
-	struct tegra_pingroup_config *pgs;
-	int pg_count;
+#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
+	PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
 
-	struct tegra_drive_pingroup_config *drives;
-	int drive_count;
+#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
+	TEGRA_MAP_MUX(_group_, _function_), \
+	TEGRA_MAP_CONF(_group_, _pull_, _drive_)
+
+extern unsigned long tegra_pincfg_pullnone_driven[2];
+extern unsigned long tegra_pincfg_pullnone_tristate[2];
+extern unsigned long tegra_pincfg_pullnone_na[1];
+extern unsigned long tegra_pincfg_pullup_driven[2];
+extern unsigned long tegra_pincfg_pullup_tristate[2];
+extern unsigned long tegra_pincfg_pullup_na[1];
+extern unsigned long tegra_pincfg_pulldown_driven[2];
+extern unsigned long tegra_pincfg_pulldown_tristate[2];
+extern unsigned long tegra_pincfg_pulldown_na[1];
+extern unsigned long tegra_pincfg_pullna_driven[1];
+extern unsigned long tegra_pincfg_pullna_tristate[1];
+
+struct tegra_board_pinmux_conf {
+	struct pinctrl_map *maps;
+	int map_count;
 };
 
 void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 3bf7e97..11fc8a5 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010,2011 NVIDIA Corporation
+ * Copyright (C) 2010-2012 NVIDIA Corporation
  * Copyright (C) 2011 Google, Inc.
  *
  * This software is licensed under the terms of the GNU General Public
@@ -14,184 +14,176 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/of.h>
 
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-
-#include "board-pinmux.h"
 #include "board-seaboard.h"
+#include "board-pinmux.h"
 
-#define DEFAULT_DRIVE(_name)					\
-	{							\
-		.pingroup = TEGRA_DRIVE_PINGROUP_##_name,	\
-		.hsm = TEGRA_HSM_DISABLE,			\
-		.schmitt = TEGRA_SCHMITT_ENABLE,		\
-		.drive = TEGRA_DRIVE_DIV_1,			\
-		.pull_down = TEGRA_PULL_31,			\
-		.pull_up = TEGRA_PULL_31,			\
-		.slew_rising = TEGRA_SLEW_SLOWEST,		\
-		.slew_falling = TEGRA_SLEW_SLOWEST,		\
-	}
-
-static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
-	DEFAULT_DRIVE(SDIO1),
+static unsigned long seaboard_pincfg_drive_sdio1[] = {
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3),
+	TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3),
 };
 
-static struct tegra_pingroup_config common_pinmux[] = {
-	{TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTA,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTB,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTC,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTD,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTE,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_GMC,   TEGRA_MUX_UARTD,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LCSN,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LDC,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LM0,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LM1,   TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LPW1,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LSDI,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LVP0,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SDB,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+static struct pinctrl_map common_map[] = {
+	TEGRA_MAP_MUXCONF("ata",   "ide",           none, driven),
+	TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
+	TEGRA_MAP_MUXCONF("atc",   "nand",          none, driven),
+	TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
+	TEGRA_MAP_MUXCONF("ate",   "gmi",           none, tristate),
+	TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
+	TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     none, driven),
+	TEGRA_MAP_MUXCONF("crtp",  "crt",           up,   tristate),
+	TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", none, tristate),
+	TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
+	TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, driven),
+	TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
+	TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, driven),
+	TEGRA_MAP_MUXCONF("dta",   "vi",            down, driven),
+	TEGRA_MAP_MUXCONF("dtb",   "vi",            down, driven),
+	TEGRA_MAP_MUXCONF("dtc",   "vi",            down, driven),
+	TEGRA_MAP_MUXCONF("dtd",   "vi",            down, driven),
+	TEGRA_MAP_MUXCONF("dte",   "vi",            down, tristate),
+	TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
+	TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
+	TEGRA_MAP_MUXCONF("gmb",   "gmi",           up,   tristate),
+	TEGRA_MAP_MUXCONF("gmc",   "uartd",         none, driven),
+	TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
+	TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
+	TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
+	TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, tristate),
+	TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
+	TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
+	TEGRA_MAP_MUXCONF("irrx",  "uartb",         none, driven),
+	TEGRA_MAP_MUXCONF("irtx",  "uartb",         none, driven),
+	TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
+	TEGRA_MAP_MUXCONF("lcsn",  "rsvd4",         na,   tristate),
+	TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ldc",   "rsvd4",         na,   tristate),
+	TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lm0",   "rsvd4",         na,   driven),
+	TEGRA_MAP_MUXCONF("lm1",   "crt",           na,   tristate),
+	TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lpw1",  "rsvd4",         na,   tristate),
+	TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lsdi",  "rsvd4",         na,   tristate),
+	TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lvp0",  "rsvd4",         na,   tristate),
+	TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("owc",   "rsvd2",         none, tristate),
+	TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
+	TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
+	TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
+	TEGRA_MAP_MUXCONF("sdb",   "sdio3",         na,   driven),
+	TEGRA_MAP_MUXCONF("sdc",   "sdio3",         none, driven),
+	TEGRA_MAP_MUXCONF("sdd",   "sdio3",         none, driven),
+	TEGRA_MAP_MUXCONF("sdio1", "sdio1",         up,   driven),
+	TEGRA_MAP_MUXCONF("slxa",  "pcie",          up,   tristate),
+	TEGRA_MAP_MUXCONF("slxd",  "spdif",         none, driven),
+	TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
+	TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, driven),
+	TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
+	TEGRA_MAP_MUXCONF("spib",  "gmi",           none, tristate),
+	TEGRA_MAP_MUXCONF("spid",  "spi1",          none, tristate),
+	TEGRA_MAP_MUXCONF("spie",  "spi1",          none, tristate),
+	TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
+	TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
+	TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
+	TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
+	TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, driven),
+	TEGRA_MAP_MUXCONF("uad",   "irda",          none, driven),
+	TEGRA_MAP_MUXCONF("uca",   "uartc",         none, driven),
+	TEGRA_MAP_MUXCONF("ucb",   "uartc",         none, driven),
+	TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
+	TEGRA_MAP_CONF("ck32",    none, na),
+	TEGRA_MAP_CONF("ddrc",    none, na),
+	TEGRA_MAP_CONF("pmca",    none, na),
+	TEGRA_MAP_CONF("pmcb",    none, na),
+	TEGRA_MAP_CONF("pmcc",    none, na),
+	TEGRA_MAP_CONF("pmcd",    none, na),
+	TEGRA_MAP_CONF("pmce",    none, na),
+	TEGRA_MAP_CONF("xm2c",    none, na),
+	TEGRA_MAP_CONF("xm2d",    none, na),
+	TEGRA_MAP_CONF("ls",      up,   na),
+	TEGRA_MAP_CONF("lc",      up,   na),
+	TEGRA_MAP_CONF("ld17_0",  down, na),
+	TEGRA_MAP_CONF("ld19_18", down, na),
+	TEGRA_MAP_CONF("ld21_20", down, na),
+	TEGRA_MAP_CONF("ld23_22", down, na),
 };
 
-static struct tegra_pingroup_config seaboard_pinmux[] = {
-	{TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LPW0,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LPW2,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LSC1,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSCK,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSDA,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+static struct pinctrl_map seaboard_map[] = {
+	TEGRA_MAP_MUXCONF("ddc",   "rsvd2",         none, tristate),
+	TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, driven),
+	TEGRA_MAP_MUXCONF("lpw0",  "hdmi",          na,   driven),
+	TEGRA_MAP_MUXCONF("lpw2",  "hdmi",          na,   driven),
+	TEGRA_MAP_MUXCONF("lsc1",  "hdmi",          na,   tristate),
+	TEGRA_MAP_MUXCONF("lsck",  "hdmi",          na,   tristate),
+	TEGRA_MAP_MUXCONF("lsda",  "hdmi",          na,   tristate),
+	TEGRA_MAP_MUXCONF("slxc",  "spdif",         none, tristate),
+	TEGRA_MAP_MUXCONF("spia",  "gmi",           up,   tristate),
+	TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
+	TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   tristate),
+	PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1),
 };
 
-static struct tegra_pingroup_config ventana_pinmux[] = {
-	{TEGRA_PINGROUP_DDC,  TEGRA_MUX_RSVD2,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMD,  TEGRA_MUX_SFLASH,   TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_PTA,  TEGRA_MUX_RSVD2,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+static struct pinctrl_map ventana_map[] = {
+	TEGRA_MAP_MUXCONF("ddc",   "rsvd2",         none, driven),
+	TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, tristate),
+	TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("slxc",  "sdio3",         none, driven),
+	TEGRA_MAP_MUXCONF("spia",  "gmi",           none, tristate),
+	TEGRA_MAP_MUXCONF("spic",  "gmi",           none, tristate),
+	TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      none, tristate),
 };
 
 static struct tegra_board_pinmux_conf common_conf = {
-	.pgs = common_pinmux,
-	.pg_count = ARRAY_SIZE(common_pinmux),
+	.maps = common_map,
+	.map_count = ARRAY_SIZE(common_map),
 };
 
 static struct tegra_board_pinmux_conf seaboard_conf = {
-	.pgs = seaboard_pinmux,
-	.pg_count = ARRAY_SIZE(seaboard_pinmux),
-	.drives = seaboard_drive_pinmux,
-	.drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
+	.maps = seaboard_map,
+	.map_count = ARRAY_SIZE(seaboard_map),
 };
 
 static struct tegra_board_pinmux_conf ventana_conf = {
-	.pgs = ventana_pinmux,
-	.pg_count = ARRAY_SIZE(ventana_pinmux),
+	.maps = ventana_map,
+	.map_count = ARRAY_SIZE(ventana_map),
 };
 
 void seaboard_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index a1902d4..7b39511 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/board-trimslice-pinmux.c
  *
  * Copyright (C) 2011 CompuLab, Ltd.
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -14,137 +15,138 @@
  *
  */
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/of.h>
 
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-
-#include "board-pinmux.h"
 #include "board-trimslice.h"
+#include "board-pinmux.h"
 
-static struct tegra_pingroup_config trimslice_pinmux[] = {
-	{TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,	TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,	TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,	TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,	TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,	TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTA,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTB,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTC,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTD,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTE,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMB,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_GMC,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GME,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_UARTA,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LCSN,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSCK,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSDA,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSDI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_PTA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_SPDI,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPDO,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIA,  TEGRA_MUX_SPI2,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIB,  TEGRA_MUX_SPI2,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIC,  TEGRA_MUX_SPI2,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+static struct pinctrl_map trimslice_map[] = {
+	TEGRA_MAP_MUXCONF("ata",   "ide",           none, tristate),
+	TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
+	TEGRA_MAP_MUXCONF("atc",   "nand",          none, tristate),
+	TEGRA_MAP_MUXCONF("atd",   "gmi",           none, tristate),
+	TEGRA_MAP_MUXCONF("ate",   "gmi",           none, tristate),
+	TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
+	TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
+	TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
+	TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
+	TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
+	TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
+	TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
+	TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
+	TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
+	TEGRA_MAP_MUXCONF("dta",   "vi",            none, tristate),
+	TEGRA_MAP_MUXCONF("dtb",   "vi",            none, tristate),
+	TEGRA_MAP_MUXCONF("dtc",   "vi",            none, tristate),
+	TEGRA_MAP_MUXCONF("dtd",   "vi",            none, tristate),
+	TEGRA_MAP_MUXCONF("dte",   "vi",            none, tristate),
+	TEGRA_MAP_MUXCONF("dtf",   "i2c3",          up,   driven),
+	TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
+	TEGRA_MAP_MUXCONF("gmb",   "nand",          none, tristate),
+	TEGRA_MAP_MUXCONF("gmc",   "sflash",        none, driven),
+	TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, driven),
+	TEGRA_MAP_MUXCONF("gme",   "gmi",           none, tristate),
+	TEGRA_MAP_MUXCONF("gpu",   "uarta",         none, driven),
+	TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
+	TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
+	TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
+	TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, tristate),
+	TEGRA_MAP_MUXCONF("irrx",  "uartb",         up,   tristate),
+	TEGRA_MAP_MUXCONF("irtx",  "uartb",         up,   tristate),
+	TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   tristate),
+	TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   tristate),
+	TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   tristate),
+	TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   tristate),
+	TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   tristate),
+	TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   tristate),
+	TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
+	TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
+	TEGRA_MAP_MUXCONF("owc",   "rsvd2",         up,   tristate),
+	TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   tristate),
+	TEGRA_MAP_MUXCONF("pta",   "gmi",           none, tristate),
+	TEGRA_MAP_MUXCONF("rm",    "i2c1",          up,   driven),
+	TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   driven),
+	TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
+	TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   driven),
+	TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
+	TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
+	TEGRA_MAP_MUXCONF("slxc",  "sdio3",         none, tristate),
+	TEGRA_MAP_MUXCONF("slxd",  "sdio3",         none, tristate),
+	TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
+	TEGRA_MAP_MUXCONF("spdi",  "spdif",         none, tristate),
+	TEGRA_MAP_MUXCONF("spdo",  "spdif",         none, tristate),
+	TEGRA_MAP_MUXCONF("spia",  "spi2",          down, tristate),
+	TEGRA_MAP_MUXCONF("spib",  "spi2",          down, tristate),
+	TEGRA_MAP_MUXCONF("spic",  "spi2",          up,   tristate),
+	TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
+	TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
+	TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
+	TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   tristate),
+	TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
+	TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
+	TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
+	TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, driven),
+	TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
+	TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
+	TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
+	TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
+	TEGRA_MAP_CONF("ck32",    none, na),
+	TEGRA_MAP_CONF("ddrc",    none, na),
+	TEGRA_MAP_CONF("pmca",    none, na),
+	TEGRA_MAP_CONF("pmcb",    none, na),
+	TEGRA_MAP_CONF("pmcc",    none, na),
+	TEGRA_MAP_CONF("pmcd",    none, na),
+	TEGRA_MAP_CONF("pmce",    none, na),
+	TEGRA_MAP_CONF("xm2c",    none, na),
+	TEGRA_MAP_CONF("xm2d",    none, na),
+	TEGRA_MAP_CONF("ls",      up,   na),
+	TEGRA_MAP_CONF("lc",      up,   na),
+	TEGRA_MAP_CONF("ld17_0",  down, na),
+	TEGRA_MAP_CONF("ld19_18", down, na),
+	TEGRA_MAP_CONF("ld21_20", down, na),
+	TEGRA_MAP_CONF("ld23_22", down, na),
 };
 
 static struct tegra_board_pinmux_conf conf = {
-	.pgs = trimslice_pinmux,
-	.pg_count = ARRAY_SIZE(trimslice_pinmux),
+	.maps = trimslice_map,
+	.map_count = ARRAY_SIZE(trimslice_map),
 };
 
 void trimslice_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index ac35d2b..7867a12 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -711,10 +711,10 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
 
 static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
-	{ .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
+	{ .compatible = "nvidia,tegra20-pinmux-disabled", tegra20_pinmux_init },
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
-	{ .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
+	{ .compatible = "nvidia,tegra30-pinmux-disabled", tegra30_pinmux_init },
 #endif
 	{ },
 };
@@ -809,7 +809,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
 
 static struct platform_driver tegra_pinmux_driver = {
 	.driver		= {
-		.name	= "tegra-pinmux",
+		.name	= "tegra-pinmux-disabled",
 		.owner	= THIS_MODULE,
 		.of_match_table = tegra_pinmux_of_match,
 	},
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 80e97c9..ef2d495 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -33,7 +33,7 @@
 
 #include "pinctrl-tegra.h"
 
-#define DRIVER_NAME "tegra-pinmux-disabled"
+#define DRIVER_NAME "tegra-pinmux"
 
 struct tegra_pmx {
 	struct device *dev;
@@ -627,13 +627,13 @@ static struct pinctrl_desc tegra_pinctrl_desc = {
 static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = {
 #ifdef CONFIG_PINCTRL_TEGRA20
 	{
-		.compatible = "nvidia,tegra20-pinmux-disabled",
+		.compatible = "nvidia,tegra20-pinmux",
 		.data = tegra20_pinctrl_init,
 	},
 #endif
 #ifdef CONFIG_PINCTRL_TEGRA30
 	{
-		.compatible = "nvidia,tegra30-pinmux-disabled",
+		.compatible = "nvidia,tegra30-pinmux",
 		.data = tegra30_pinctrl_init,
 	},
 #endif
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Mar 30 19:00:03 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 17:00:03 -0600
Subject: [PATCH 10/11] ARM: dt: tegra cardhu: add pinmux to device tree
In-Reply-To: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1333148404-17691-11-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

This adds a minimal pinmux configuration to the Tegra Cardhu device
tree. Initially, just the built-in eMMC and SD card slot are configured.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/tegra-cardhu.dts |   44 ++++++++++++++++++++++++++++++++++++
 1 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index ac3fb75..0a9f34a 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -10,6 +10,50 @@
 		reg = < 0x80000000 0x40000000 >;
 	};
 
+	pinmux at 70000000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			sdmmc1_clk_pz0 {
+				nvidia,pins = "sdmmc1_clk_pz0";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			sdmmc1_cmd_pz1 {
+				nvidia,pins =	"sdmmc1_cmd_pz1",
+						"sdmmc1_dat0_py7",
+						"sdmmc1_dat1_py6",
+						"sdmmc1_dat2_py5",
+						"sdmmc1_dat3_py4";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+			sdmmc4_clk_pcc4 {
+				nvidia,pins =	"sdmmc4_clk_pcc4",
+						"sdmmc4_rst_n_pcc3";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			sdmmc4_dat0_paa0 {
+				nvidia,pins =	"sdmmc4_dat0_paa0",
+						"sdmmc4_dat1_paa1",
+						"sdmmc4_dat2_paa2",
+						"sdmmc4_dat3_paa3",
+						"sdmmc4_dat4_paa4",
+						"sdmmc4_dat5_paa5",
+						"sdmmc4_dat6_paa6",
+						"sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+		};
+	};
+
 	serial at 70006000 {
 		clock-frequency = < 408000000 >;
 	};
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Mar 30 19:00:02 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 17:00:02 -0600
Subject: [PATCH 09/11] ARM: tegra: Remove pre-pinctrl pinmux driver
In-Reply-To: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1333148404-17691-10-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

The pinctrl driver is now active and used by all boards. Remove the
old pinmux driver.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Acked-by: Olof Johansson <olof at lixom.net>
---
v3: No change
v2: No change?
---
 arch/arm/mach-tegra/Makefile                      |    3 -
 arch/arm/mach-tegra/include/mach/pinmux-tegra20.h |  184 ----
 arch/arm/mach-tegra/include/mach/pinmux-tegra30.h |  320 -------
 arch/arm/mach-tegra/include/mach/pinmux.h         |  302 -------
 arch/arm/mach-tegra/pinmux-tegra20-tables.c       |  244 -----
 arch/arm/mach-tegra/pinmux-tegra30-tables.c       |  376 --------
 arch/arm/mach-tegra/pinmux.c                      |  987 ---------------------
 7 files changed, 0 insertions(+), 2416 deletions(-)
 delete mode 100644 arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
 delete mode 100644 arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
 delete mode 100644 arch/arm/mach-tegra/include/mach/pinmux.h
 delete mode 100644 arch/arm/mach-tegra/pinmux-tegra20-tables.c
 delete mode 100644 arch/arm/mach-tegra/pinmux-tegra30-tables.c
 delete mode 100644 arch/arm/mach-tegra/pinmux.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d87d968..2eb4445 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -5,7 +5,6 @@ obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
-obj-y                                   += pinmux.o
 obj-y					+= fuse.o
 obj-y					+= pmc.o
 obj-y					+= flowctrl.o
@@ -14,8 +13,6 @@ obj-$(CONFIG_CPU_IDLE)			+= sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= powergate.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-tegra20-tables.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= pinmux-tegra30-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= board-dt-tegra30.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
 obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
deleted file mode 100644
index 6a40c1d..0000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
-#define __MACH_TEGRA_PINMUX_TEGRA20_H
-
-enum tegra_pingroup {
-	TEGRA_PINGROUP_ATA = 0,
-	TEGRA_PINGROUP_ATB,
-	TEGRA_PINGROUP_ATC,
-	TEGRA_PINGROUP_ATD,
-	TEGRA_PINGROUP_ATE,
-	TEGRA_PINGROUP_CDEV1,
-	TEGRA_PINGROUP_CDEV2,
-	TEGRA_PINGROUP_CRTP,
-	TEGRA_PINGROUP_CSUS,
-	TEGRA_PINGROUP_DAP1,
-	TEGRA_PINGROUP_DAP2,
-	TEGRA_PINGROUP_DAP3,
-	TEGRA_PINGROUP_DAP4,
-	TEGRA_PINGROUP_DDC,
-	TEGRA_PINGROUP_DTA,
-	TEGRA_PINGROUP_DTB,
-	TEGRA_PINGROUP_DTC,
-	TEGRA_PINGROUP_DTD,
-	TEGRA_PINGROUP_DTE,
-	TEGRA_PINGROUP_DTF,
-	TEGRA_PINGROUP_GMA,
-	TEGRA_PINGROUP_GMB,
-	TEGRA_PINGROUP_GMC,
-	TEGRA_PINGROUP_GMD,
-	TEGRA_PINGROUP_GME,
-	TEGRA_PINGROUP_GPU,
-	TEGRA_PINGROUP_GPU7,
-	TEGRA_PINGROUP_GPV,
-	TEGRA_PINGROUP_HDINT,
-	TEGRA_PINGROUP_I2CP,
-	TEGRA_PINGROUP_IRRX,
-	TEGRA_PINGROUP_IRTX,
-	TEGRA_PINGROUP_KBCA,
-	TEGRA_PINGROUP_KBCB,
-	TEGRA_PINGROUP_KBCC,
-	TEGRA_PINGROUP_KBCD,
-	TEGRA_PINGROUP_KBCE,
-	TEGRA_PINGROUP_KBCF,
-	TEGRA_PINGROUP_LCSN,
-	TEGRA_PINGROUP_LD0,
-	TEGRA_PINGROUP_LD1,
-	TEGRA_PINGROUP_LD10,
-	TEGRA_PINGROUP_LD11,
-	TEGRA_PINGROUP_LD12,
-	TEGRA_PINGROUP_LD13,
-	TEGRA_PINGROUP_LD14,
-	TEGRA_PINGROUP_LD15,
-	TEGRA_PINGROUP_LD16,
-	TEGRA_PINGROUP_LD17,
-	TEGRA_PINGROUP_LD2,
-	TEGRA_PINGROUP_LD3,
-	TEGRA_PINGROUP_LD4,
-	TEGRA_PINGROUP_LD5,
-	TEGRA_PINGROUP_LD6,
-	TEGRA_PINGROUP_LD7,
-	TEGRA_PINGROUP_LD8,
-	TEGRA_PINGROUP_LD9,
-	TEGRA_PINGROUP_LDC,
-	TEGRA_PINGROUP_LDI,
-	TEGRA_PINGROUP_LHP0,
-	TEGRA_PINGROUP_LHP1,
-	TEGRA_PINGROUP_LHP2,
-	TEGRA_PINGROUP_LHS,
-	TEGRA_PINGROUP_LM0,
-	TEGRA_PINGROUP_LM1,
-	TEGRA_PINGROUP_LPP,
-	TEGRA_PINGROUP_LPW0,
-	TEGRA_PINGROUP_LPW1,
-	TEGRA_PINGROUP_LPW2,
-	TEGRA_PINGROUP_LSC0,
-	TEGRA_PINGROUP_LSC1,
-	TEGRA_PINGROUP_LSCK,
-	TEGRA_PINGROUP_LSDA,
-	TEGRA_PINGROUP_LSDI,
-	TEGRA_PINGROUP_LSPI,
-	TEGRA_PINGROUP_LVP0,
-	TEGRA_PINGROUP_LVP1,
-	TEGRA_PINGROUP_LVS,
-	TEGRA_PINGROUP_OWC,
-	TEGRA_PINGROUP_PMC,
-	TEGRA_PINGROUP_PTA,
-	TEGRA_PINGROUP_RM,
-	TEGRA_PINGROUP_SDB,
-	TEGRA_PINGROUP_SDC,
-	TEGRA_PINGROUP_SDD,
-	TEGRA_PINGROUP_SDIO1,
-	TEGRA_PINGROUP_SLXA,
-	TEGRA_PINGROUP_SLXC,
-	TEGRA_PINGROUP_SLXD,
-	TEGRA_PINGROUP_SLXK,
-	TEGRA_PINGROUP_SPDI,
-	TEGRA_PINGROUP_SPDO,
-	TEGRA_PINGROUP_SPIA,
-	TEGRA_PINGROUP_SPIB,
-	TEGRA_PINGROUP_SPIC,
-	TEGRA_PINGROUP_SPID,
-	TEGRA_PINGROUP_SPIE,
-	TEGRA_PINGROUP_SPIF,
-	TEGRA_PINGROUP_SPIG,
-	TEGRA_PINGROUP_SPIH,
-	TEGRA_PINGROUP_UAA,
-	TEGRA_PINGROUP_UAB,
-	TEGRA_PINGROUP_UAC,
-	TEGRA_PINGROUP_UAD,
-	TEGRA_PINGROUP_UCA,
-	TEGRA_PINGROUP_UCB,
-	TEGRA_PINGROUP_UDA,
-	/* these pin groups only have pullup and pull down control */
-	TEGRA_PINGROUP_CK32,
-	TEGRA_PINGROUP_DDRC,
-	TEGRA_PINGROUP_PMCA,
-	TEGRA_PINGROUP_PMCB,
-	TEGRA_PINGROUP_PMCC,
-	TEGRA_PINGROUP_PMCD,
-	TEGRA_PINGROUP_PMCE,
-	TEGRA_PINGROUP_XM2C,
-	TEGRA_PINGROUP_XM2D,
-	TEGRA_MAX_PINGROUP,
-};
-
-enum tegra_drive_pingroup {
-	TEGRA_DRIVE_PINGROUP_AO1 = 0,
-	TEGRA_DRIVE_PINGROUP_AO2,
-	TEGRA_DRIVE_PINGROUP_AT1,
-	TEGRA_DRIVE_PINGROUP_AT2,
-	TEGRA_DRIVE_PINGROUP_CDEV1,
-	TEGRA_DRIVE_PINGROUP_CDEV2,
-	TEGRA_DRIVE_PINGROUP_CSUS,
-	TEGRA_DRIVE_PINGROUP_DAP1,
-	TEGRA_DRIVE_PINGROUP_DAP2,
-	TEGRA_DRIVE_PINGROUP_DAP3,
-	TEGRA_DRIVE_PINGROUP_DAP4,
-	TEGRA_DRIVE_PINGROUP_DBG,
-	TEGRA_DRIVE_PINGROUP_LCD1,
-	TEGRA_DRIVE_PINGROUP_LCD2,
-	TEGRA_DRIVE_PINGROUP_SDMMC2,
-	TEGRA_DRIVE_PINGROUP_SDMMC3,
-	TEGRA_DRIVE_PINGROUP_SPI,
-	TEGRA_DRIVE_PINGROUP_UAA,
-	TEGRA_DRIVE_PINGROUP_UAB,
-	TEGRA_DRIVE_PINGROUP_UART2,
-	TEGRA_DRIVE_PINGROUP_UART3,
-	TEGRA_DRIVE_PINGROUP_VI1,
-	TEGRA_DRIVE_PINGROUP_VI2,
-	TEGRA_DRIVE_PINGROUP_XM2A,
-	TEGRA_DRIVE_PINGROUP_XM2C,
-	TEGRA_DRIVE_PINGROUP_XM2D,
-	TEGRA_DRIVE_PINGROUP_XM2CLK,
-	TEGRA_DRIVE_PINGROUP_MEMCOMP,
-	TEGRA_DRIVE_PINGROUP_SDIO1,
-	TEGRA_DRIVE_PINGROUP_CRT,
-	TEGRA_DRIVE_PINGROUP_DDC,
-	TEGRA_DRIVE_PINGROUP_GMA,
-	TEGRA_DRIVE_PINGROUP_GMB,
-	TEGRA_DRIVE_PINGROUP_GMC,
-	TEGRA_DRIVE_PINGROUP_GMD,
-	TEGRA_DRIVE_PINGROUP_GME,
-	TEGRA_DRIVE_PINGROUP_OWR,
-	TEGRA_DRIVE_PINGROUP_UAD,
-	TEGRA_MAX_DRIVE_PINGROUP,
-};
-
-#endif
-
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
deleted file mode 100644
index c1aee3e..0000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2010,2011 Nvidia, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
-#define __MACH_TEGRA_PINMUX_TEGRA30_H
-
-enum tegra_pingroup {
-	TEGRA_PINGROUP_ULPI_DATA0 = 0,
-	TEGRA_PINGROUP_ULPI_DATA1,
-	TEGRA_PINGROUP_ULPI_DATA2,
-	TEGRA_PINGROUP_ULPI_DATA3,
-	TEGRA_PINGROUP_ULPI_DATA4,
-	TEGRA_PINGROUP_ULPI_DATA5,
-	TEGRA_PINGROUP_ULPI_DATA6,
-	TEGRA_PINGROUP_ULPI_DATA7,
-	TEGRA_PINGROUP_ULPI_CLK,
-	TEGRA_PINGROUP_ULPI_DIR,
-	TEGRA_PINGROUP_ULPI_NXT,
-	TEGRA_PINGROUP_ULPI_STP,
-	TEGRA_PINGROUP_DAP3_FS,
-	TEGRA_PINGROUP_DAP3_DIN,
-	TEGRA_PINGROUP_DAP3_DOUT,
-	TEGRA_PINGROUP_DAP3_SCLK,
-	TEGRA_PINGROUP_GPIO_PV0,
-	TEGRA_PINGROUP_GPIO_PV1,
-	TEGRA_PINGROUP_SDMMC1_CLK,
-	TEGRA_PINGROUP_SDMMC1_CMD,
-	TEGRA_PINGROUP_SDMMC1_DAT3,
-	TEGRA_PINGROUP_SDMMC1_DAT2,
-	TEGRA_PINGROUP_SDMMC1_DAT1,
-	TEGRA_PINGROUP_SDMMC1_DAT0,
-	TEGRA_PINGROUP_GPIO_PV2,
-	TEGRA_PINGROUP_GPIO_PV3,
-	TEGRA_PINGROUP_CLK2_OUT,
-	TEGRA_PINGROUP_CLK2_REQ,
-	TEGRA_PINGROUP_LCD_PWR1,
-	TEGRA_PINGROUP_LCD_PWR2,
-	TEGRA_PINGROUP_LCD_SDIN,
-	TEGRA_PINGROUP_LCD_SDOUT,
-	TEGRA_PINGROUP_LCD_WR_N,
-	TEGRA_PINGROUP_LCD_CS0_N,
-	TEGRA_PINGROUP_LCD_DC0,
-	TEGRA_PINGROUP_LCD_SCK,
-	TEGRA_PINGROUP_LCD_PWR0,
-	TEGRA_PINGROUP_LCD_PCLK,
-	TEGRA_PINGROUP_LCD_DE,
-	TEGRA_PINGROUP_LCD_HSYNC,
-	TEGRA_PINGROUP_LCD_VSYNC,
-	TEGRA_PINGROUP_LCD_D0,
-	TEGRA_PINGROUP_LCD_D1,
-	TEGRA_PINGROUP_LCD_D2,
-	TEGRA_PINGROUP_LCD_D3,
-	TEGRA_PINGROUP_LCD_D4,
-	TEGRA_PINGROUP_LCD_D5,
-	TEGRA_PINGROUP_LCD_D6,
-	TEGRA_PINGROUP_LCD_D7,
-	TEGRA_PINGROUP_LCD_D8,
-	TEGRA_PINGROUP_LCD_D9,
-	TEGRA_PINGROUP_LCD_D10,
-	TEGRA_PINGROUP_LCD_D11,
-	TEGRA_PINGROUP_LCD_D12,
-	TEGRA_PINGROUP_LCD_D13,
-	TEGRA_PINGROUP_LCD_D14,
-	TEGRA_PINGROUP_LCD_D15,
-	TEGRA_PINGROUP_LCD_D16,
-	TEGRA_PINGROUP_LCD_D17,
-	TEGRA_PINGROUP_LCD_D18,
-	TEGRA_PINGROUP_LCD_D19,
-	TEGRA_PINGROUP_LCD_D20,
-	TEGRA_PINGROUP_LCD_D21,
-	TEGRA_PINGROUP_LCD_D22,
-	TEGRA_PINGROUP_LCD_D23,
-	TEGRA_PINGROUP_LCD_CS1_N,
-	TEGRA_PINGROUP_LCD_M1,
-	TEGRA_PINGROUP_LCD_DC1,
-	TEGRA_PINGROUP_HDMI_INT,
-	TEGRA_PINGROUP_DDC_SCL,
-	TEGRA_PINGROUP_DDC_SDA,
-	TEGRA_PINGROUP_CRT_HSYNC,
-	TEGRA_PINGROUP_CRT_VSYNC,
-	TEGRA_PINGROUP_VI_D0,
-	TEGRA_PINGROUP_VI_D1,
-	TEGRA_PINGROUP_VI_D2,
-	TEGRA_PINGROUP_VI_D3,
-	TEGRA_PINGROUP_VI_D4,
-	TEGRA_PINGROUP_VI_D5,
-	TEGRA_PINGROUP_VI_D6,
-	TEGRA_PINGROUP_VI_D7,
-	TEGRA_PINGROUP_VI_D8,
-	TEGRA_PINGROUP_VI_D9,
-	TEGRA_PINGROUP_VI_D10,
-	TEGRA_PINGROUP_VI_D11,
-	TEGRA_PINGROUP_VI_PCLK,
-	TEGRA_PINGROUP_VI_MCLK,
-	TEGRA_PINGROUP_VI_VSYNC,
-	TEGRA_PINGROUP_VI_HSYNC,
-	TEGRA_PINGROUP_UART2_RXD,
-	TEGRA_PINGROUP_UART2_TXD,
-	TEGRA_PINGROUP_UART2_RTS_N,
-	TEGRA_PINGROUP_UART2_CTS_N,
-	TEGRA_PINGROUP_UART3_TXD,
-	TEGRA_PINGROUP_UART3_RXD,
-	TEGRA_PINGROUP_UART3_CTS_N,
-	TEGRA_PINGROUP_UART3_RTS_N,
-	TEGRA_PINGROUP_GPIO_PU0,
-	TEGRA_PINGROUP_GPIO_PU1,
-	TEGRA_PINGROUP_GPIO_PU2,
-	TEGRA_PINGROUP_GPIO_PU3,
-	TEGRA_PINGROUP_GPIO_PU4,
-	TEGRA_PINGROUP_GPIO_PU5,
-	TEGRA_PINGROUP_GPIO_PU6,
-	TEGRA_PINGROUP_GEN1_I2C_SDA,
-	TEGRA_PINGROUP_GEN1_I2C_SCL,
-	TEGRA_PINGROUP_DAP4_FS,
-	TEGRA_PINGROUP_DAP4_DIN,
-	TEGRA_PINGROUP_DAP4_DOUT,
-	TEGRA_PINGROUP_DAP4_SCLK,
-	TEGRA_PINGROUP_CLK3_OUT,
-	TEGRA_PINGROUP_CLK3_REQ,
-	TEGRA_PINGROUP_GMI_WP_N,
-	TEGRA_PINGROUP_GMI_IORDY,
-	TEGRA_PINGROUP_GMI_WAIT,
-	TEGRA_PINGROUP_GMI_ADV_N,
-	TEGRA_PINGROUP_GMI_CLK,
-	TEGRA_PINGROUP_GMI_CS0_N,
-	TEGRA_PINGROUP_GMI_CS1_N,
-	TEGRA_PINGROUP_GMI_CS2_N,
-	TEGRA_PINGROUP_GMI_CS3_N,
-	TEGRA_PINGROUP_GMI_CS4_N,
-	TEGRA_PINGROUP_GMI_CS6_N,
-	TEGRA_PINGROUP_GMI_CS7_N,
-	TEGRA_PINGROUP_GMI_AD0,
-	TEGRA_PINGROUP_GMI_AD1,
-	TEGRA_PINGROUP_GMI_AD2,
-	TEGRA_PINGROUP_GMI_AD3,
-	TEGRA_PINGROUP_GMI_AD4,
-	TEGRA_PINGROUP_GMI_AD5,
-	TEGRA_PINGROUP_GMI_AD6,
-	TEGRA_PINGROUP_GMI_AD7,
-	TEGRA_PINGROUP_GMI_AD8,
-	TEGRA_PINGROUP_GMI_AD9,
-	TEGRA_PINGROUP_GMI_AD10,
-	TEGRA_PINGROUP_GMI_AD11,
-	TEGRA_PINGROUP_GMI_AD12,
-	TEGRA_PINGROUP_GMI_AD13,
-	TEGRA_PINGROUP_GMI_AD14,
-	TEGRA_PINGROUP_GMI_AD15,
-	TEGRA_PINGROUP_GMI_A16,
-	TEGRA_PINGROUP_GMI_A17,
-	TEGRA_PINGROUP_GMI_A18,
-	TEGRA_PINGROUP_GMI_A19,
-	TEGRA_PINGROUP_GMI_WR_N,
-	TEGRA_PINGROUP_GMI_OE_N,
-	TEGRA_PINGROUP_GMI_DQS,
-	TEGRA_PINGROUP_GMI_RST_N,
-	TEGRA_PINGROUP_GEN2_I2C_SCL,
-	TEGRA_PINGROUP_GEN2_I2C_SDA,
-	TEGRA_PINGROUP_SDMMC4_CLK,
-	TEGRA_PINGROUP_SDMMC4_CMD,
-	TEGRA_PINGROUP_SDMMC4_DAT0,
-	TEGRA_PINGROUP_SDMMC4_DAT1,
-	TEGRA_PINGROUP_SDMMC4_DAT2,
-	TEGRA_PINGROUP_SDMMC4_DAT3,
-	TEGRA_PINGROUP_SDMMC4_DAT4,
-	TEGRA_PINGROUP_SDMMC4_DAT5,
-	TEGRA_PINGROUP_SDMMC4_DAT6,
-	TEGRA_PINGROUP_SDMMC4_DAT7,
-	TEGRA_PINGROUP_SDMMC4_RST_N,
-	TEGRA_PINGROUP_CAM_MCLK,
-	TEGRA_PINGROUP_GPIO_PCC1,
-	TEGRA_PINGROUP_GPIO_PBB0,
-	TEGRA_PINGROUP_CAM_I2C_SCL,
-	TEGRA_PINGROUP_CAM_I2C_SDA,
-	TEGRA_PINGROUP_GPIO_PBB3,
-	TEGRA_PINGROUP_GPIO_PBB4,
-	TEGRA_PINGROUP_GPIO_PBB5,
-	TEGRA_PINGROUP_GPIO_PBB6,
-	TEGRA_PINGROUP_GPIO_PBB7,
-	TEGRA_PINGROUP_GPIO_PCC2,
-	TEGRA_PINGROUP_JTAG_RTCK,
-	TEGRA_PINGROUP_PWR_I2C_SCL,
-	TEGRA_PINGROUP_PWR_I2C_SDA,
-	TEGRA_PINGROUP_KB_ROW0,
-	TEGRA_PINGROUP_KB_ROW1,
-	TEGRA_PINGROUP_KB_ROW2,
-	TEGRA_PINGROUP_KB_ROW3,
-	TEGRA_PINGROUP_KB_ROW4,
-	TEGRA_PINGROUP_KB_ROW5,
-	TEGRA_PINGROUP_KB_ROW6,
-	TEGRA_PINGROUP_KB_ROW7,
-	TEGRA_PINGROUP_KB_ROW8,
-	TEGRA_PINGROUP_KB_ROW9,
-	TEGRA_PINGROUP_KB_ROW10,
-	TEGRA_PINGROUP_KB_ROW11,
-	TEGRA_PINGROUP_KB_ROW12,
-	TEGRA_PINGROUP_KB_ROW13,
-	TEGRA_PINGROUP_KB_ROW14,
-	TEGRA_PINGROUP_KB_ROW15,
-	TEGRA_PINGROUP_KB_COL0,
-	TEGRA_PINGROUP_KB_COL1,
-	TEGRA_PINGROUP_KB_COL2,
-	TEGRA_PINGROUP_KB_COL3,
-	TEGRA_PINGROUP_KB_COL4,
-	TEGRA_PINGROUP_KB_COL5,
-	TEGRA_PINGROUP_KB_COL6,
-	TEGRA_PINGROUP_KB_COL7,
-	TEGRA_PINGROUP_CLK_32K_OUT,
-	TEGRA_PINGROUP_SYS_CLK_REQ,
-	TEGRA_PINGROUP_CORE_PWR_REQ,
-	TEGRA_PINGROUP_CPU_PWR_REQ,
-	TEGRA_PINGROUP_PWR_INT_N,
-	TEGRA_PINGROUP_CLK_32K_IN,
-	TEGRA_PINGROUP_OWR,
-	TEGRA_PINGROUP_DAP1_FS,
-	TEGRA_PINGROUP_DAP1_DIN,
-	TEGRA_PINGROUP_DAP1_DOUT,
-	TEGRA_PINGROUP_DAP1_SCLK,
-	TEGRA_PINGROUP_CLK1_REQ,
-	TEGRA_PINGROUP_CLK1_OUT,
-	TEGRA_PINGROUP_SPDIF_IN,
-	TEGRA_PINGROUP_SPDIF_OUT,
-	TEGRA_PINGROUP_DAP2_FS,
-	TEGRA_PINGROUP_DAP2_DIN,
-	TEGRA_PINGROUP_DAP2_DOUT,
-	TEGRA_PINGROUP_DAP2_SCLK,
-	TEGRA_PINGROUP_SPI2_MOSI,
-	TEGRA_PINGROUP_SPI2_MISO,
-	TEGRA_PINGROUP_SPI2_CS0_N,
-	TEGRA_PINGROUP_SPI2_SCK,
-	TEGRA_PINGROUP_SPI1_MOSI,
-	TEGRA_PINGROUP_SPI1_SCK,
-	TEGRA_PINGROUP_SPI1_CS0_N,
-	TEGRA_PINGROUP_SPI1_MISO,
-	TEGRA_PINGROUP_SPI2_CS1_N,
-	TEGRA_PINGROUP_SPI2_CS2_N,
-	TEGRA_PINGROUP_SDMMC3_CLK,
-	TEGRA_PINGROUP_SDMMC3_CMD,
-	TEGRA_PINGROUP_SDMMC3_DAT0,
-	TEGRA_PINGROUP_SDMMC3_DAT1,
-	TEGRA_PINGROUP_SDMMC3_DAT2,
-	TEGRA_PINGROUP_SDMMC3_DAT3,
-	TEGRA_PINGROUP_SDMMC3_DAT4,
-	TEGRA_PINGROUP_SDMMC3_DAT5,
-	TEGRA_PINGROUP_SDMMC3_DAT6,
-	TEGRA_PINGROUP_SDMMC3_DAT7,
-	TEGRA_PINGROUP_PEX_L0_PRSNT_N,
-	TEGRA_PINGROUP_PEX_L0_RST_N,
-	TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
-	TEGRA_PINGROUP_PEX_WAKE_N,
-	TEGRA_PINGROUP_PEX_L1_PRSNT_N,
-	TEGRA_PINGROUP_PEX_L1_RST_N,
-	TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
-	TEGRA_PINGROUP_PEX_L2_PRSNT_N,
-	TEGRA_PINGROUP_PEX_L2_RST_N,
-	TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
-	TEGRA_PINGROUP_HDMI_CEC,
-	TEGRA_MAX_PINGROUP,
-};
-
-enum tegra_drive_pingroup {
-	TEGRA_DRIVE_PINGROUP_AO1 = 0,
-	TEGRA_DRIVE_PINGROUP_AO2,
-	TEGRA_DRIVE_PINGROUP_AT1,
-	TEGRA_DRIVE_PINGROUP_AT2,
-	TEGRA_DRIVE_PINGROUP_AT3,
-	TEGRA_DRIVE_PINGROUP_AT4,
-	TEGRA_DRIVE_PINGROUP_AT5,
-	TEGRA_DRIVE_PINGROUP_CDEV1,
-	TEGRA_DRIVE_PINGROUP_CDEV2,
-	TEGRA_DRIVE_PINGROUP_CSUS,
-	TEGRA_DRIVE_PINGROUP_DAP1,
-	TEGRA_DRIVE_PINGROUP_DAP2,
-	TEGRA_DRIVE_PINGROUP_DAP3,
-	TEGRA_DRIVE_PINGROUP_DAP4,
-	TEGRA_DRIVE_PINGROUP_DBG,
-	TEGRA_DRIVE_PINGROUP_LCD1,
-	TEGRA_DRIVE_PINGROUP_LCD2,
-	TEGRA_DRIVE_PINGROUP_SDIO2,
-	TEGRA_DRIVE_PINGROUP_SDIO3,
-	TEGRA_DRIVE_PINGROUP_SPI,
-	TEGRA_DRIVE_PINGROUP_UAA,
-	TEGRA_DRIVE_PINGROUP_UAB,
-	TEGRA_DRIVE_PINGROUP_UART2,
-	TEGRA_DRIVE_PINGROUP_UART3,
-	TEGRA_DRIVE_PINGROUP_VI1,
-	TEGRA_DRIVE_PINGROUP_SDIO1,
-	TEGRA_DRIVE_PINGROUP_CRT,
-	TEGRA_DRIVE_PINGROUP_DDC,
-	TEGRA_DRIVE_PINGROUP_GMA,
-	TEGRA_DRIVE_PINGROUP_GMB,
-	TEGRA_DRIVE_PINGROUP_GMC,
-	TEGRA_DRIVE_PINGROUP_GMD,
-	TEGRA_DRIVE_PINGROUP_GME,
-	TEGRA_DRIVE_PINGROUP_GMF,
-	TEGRA_DRIVE_PINGROUP_GMG,
-	TEGRA_DRIVE_PINGROUP_GMH,
-	TEGRA_DRIVE_PINGROUP_OWR,
-	TEGRA_DRIVE_PINGROUP_UAD,
-	TEGRA_DRIVE_PINGROUP_GPV,
-	TEGRA_DRIVE_PINGROUP_DEV3,
-	TEGRA_DRIVE_PINGROUP_CEC,
-	TEGRA_MAX_DRIVE_PINGROUP,
-};
-
-#endif
-
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
deleted file mode 100644
index 055f179..0000000
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/include/mach/pinmux.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2010,2011 Nvidia, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_PINMUX_H
-#define __MACH_TEGRA_PINMUX_H
-
-enum tegra_mux_func {
-	TEGRA_MUX_RSVD = 0x8000,
-	TEGRA_MUX_RSVD1 = 0x8000,
-	TEGRA_MUX_RSVD2 = 0x8001,
-	TEGRA_MUX_RSVD3 = 0x8002,
-	TEGRA_MUX_RSVD4 = 0x8003,
-	TEGRA_MUX_INVALID = 0x4000,
-	TEGRA_MUX_NONE = -1,
-	TEGRA_MUX_AHB_CLK,
-	TEGRA_MUX_APB_CLK,
-	TEGRA_MUX_AUDIO_SYNC,
-	TEGRA_MUX_CRT,
-	TEGRA_MUX_DAP1,
-	TEGRA_MUX_DAP2,
-	TEGRA_MUX_DAP3,
-	TEGRA_MUX_DAP4,
-	TEGRA_MUX_DAP5,
-	TEGRA_MUX_DISPLAYA,
-	TEGRA_MUX_DISPLAYB,
-	TEGRA_MUX_EMC_TEST0_DLL,
-	TEGRA_MUX_EMC_TEST1_DLL,
-	TEGRA_MUX_GMI,
-	TEGRA_MUX_GMI_INT,
-	TEGRA_MUX_HDMI,
-	TEGRA_MUX_I2C,
-	TEGRA_MUX_I2C2,
-	TEGRA_MUX_I2C3,
-	TEGRA_MUX_IDE,
-	TEGRA_MUX_IRDA,
-	TEGRA_MUX_KBC,
-	TEGRA_MUX_MIO,
-	TEGRA_MUX_MIPI_HS,
-	TEGRA_MUX_NAND,
-	TEGRA_MUX_OSC,
-	TEGRA_MUX_OWR,
-	TEGRA_MUX_PCIE,
-	TEGRA_MUX_PLLA_OUT,
-	TEGRA_MUX_PLLC_OUT1,
-	TEGRA_MUX_PLLM_OUT1,
-	TEGRA_MUX_PLLP_OUT2,
-	TEGRA_MUX_PLLP_OUT3,
-	TEGRA_MUX_PLLP_OUT4,
-	TEGRA_MUX_PWM,
-	TEGRA_MUX_PWR_INTR,
-	TEGRA_MUX_PWR_ON,
-	TEGRA_MUX_RTCK,
-	TEGRA_MUX_SDIO1,
-	TEGRA_MUX_SDIO2,
-	TEGRA_MUX_SDIO3,
-	TEGRA_MUX_SDIO4,
-	TEGRA_MUX_SFLASH,
-	TEGRA_MUX_SPDIF,
-	TEGRA_MUX_SPI1,
-	TEGRA_MUX_SPI2,
-	TEGRA_MUX_SPI2_ALT,
-	TEGRA_MUX_SPI3,
-	TEGRA_MUX_SPI4,
-	TEGRA_MUX_TRACE,
-	TEGRA_MUX_TWC,
-	TEGRA_MUX_UARTA,
-	TEGRA_MUX_UARTB,
-	TEGRA_MUX_UARTC,
-	TEGRA_MUX_UARTD,
-	TEGRA_MUX_UARTE,
-	TEGRA_MUX_ULPI,
-	TEGRA_MUX_VI,
-	TEGRA_MUX_VI_SENSOR_CLK,
-	TEGRA_MUX_XIO,
-	TEGRA_MUX_BLINK,
-	TEGRA_MUX_CEC,
-	TEGRA_MUX_CLK12,
-	TEGRA_MUX_DAP,
-	TEGRA_MUX_DAPSDMMC2,
-	TEGRA_MUX_DDR,
-	TEGRA_MUX_DEV3,
-	TEGRA_MUX_DTV,
-	TEGRA_MUX_VI_ALT1,
-	TEGRA_MUX_VI_ALT2,
-	TEGRA_MUX_VI_ALT3,
-	TEGRA_MUX_EMC_DLL,
-	TEGRA_MUX_EXTPERIPH1,
-	TEGRA_MUX_EXTPERIPH2,
-	TEGRA_MUX_EXTPERIPH3,
-	TEGRA_MUX_GMI_ALT,
-	TEGRA_MUX_HDA,
-	TEGRA_MUX_HSI,
-	TEGRA_MUX_I2C4,
-	TEGRA_MUX_I2C5,
-	TEGRA_MUX_I2CPWR,
-	TEGRA_MUX_I2S0,
-	TEGRA_MUX_I2S1,
-	TEGRA_MUX_I2S2,
-	TEGRA_MUX_I2S3,
-	TEGRA_MUX_I2S4,
-	TEGRA_MUX_NAND_ALT,
-	TEGRA_MUX_POPSDIO4,
-	TEGRA_MUX_POPSDMMC4,
-	TEGRA_MUX_PWM0,
-	TEGRA_MUX_PWM1,
-	TEGRA_MUX_PWM2,
-	TEGRA_MUX_PWM3,
-	TEGRA_MUX_SATA,
-	TEGRA_MUX_SPI5,
-	TEGRA_MUX_SPI6,
-	TEGRA_MUX_SYSCLK,
-	TEGRA_MUX_VGP1,
-	TEGRA_MUX_VGP2,
-	TEGRA_MUX_VGP3,
-	TEGRA_MUX_VGP4,
-	TEGRA_MUX_VGP5,
-	TEGRA_MUX_VGP6,
-	TEGRA_MUX_SAFE,
-	TEGRA_MAX_MUX,
-};
-
-enum tegra_pullupdown {
-	TEGRA_PUPD_NORMAL = 0,
-	TEGRA_PUPD_PULL_DOWN,
-	TEGRA_PUPD_PULL_UP,
-};
-
-enum tegra_tristate {
-	TEGRA_TRI_NORMAL = 0,
-	TEGRA_TRI_TRISTATE = 1,
-};
-
-enum tegra_pin_io {
-	TEGRA_PIN_OUTPUT = 0,
-	TEGRA_PIN_INPUT = 1,
-};
-
-enum tegra_vddio {
-	TEGRA_VDDIO_BB = 0,
-	TEGRA_VDDIO_LCD,
-	TEGRA_VDDIO_VI,
-	TEGRA_VDDIO_UART,
-	TEGRA_VDDIO_DDR,
-	TEGRA_VDDIO_NAND,
-	TEGRA_VDDIO_SYS,
-	TEGRA_VDDIO_AUDIO,
-	TEGRA_VDDIO_SD,
-	TEGRA_VDDIO_CAM,
-	TEGRA_VDDIO_GMI,
-	TEGRA_VDDIO_PEXCTL,
-	TEGRA_VDDIO_SDMMC1,
-	TEGRA_VDDIO_SDMMC3,
-	TEGRA_VDDIO_SDMMC4,
-};
-
-struct tegra_pingroup_config {
-	int pingroup;
-	enum tegra_mux_func	func;
-	enum tegra_pullupdown	pupd;
-	enum tegra_tristate	tristate;
-};
-
-enum tegra_slew {
-	TEGRA_SLEW_FASTEST = 0,
-	TEGRA_SLEW_FAST,
-	TEGRA_SLEW_SLOW,
-	TEGRA_SLEW_SLOWEST,
-	TEGRA_MAX_SLEW,
-};
-
-enum tegra_pull_strength {
-	TEGRA_PULL_0 = 0,
-	TEGRA_PULL_1,
-	TEGRA_PULL_2,
-	TEGRA_PULL_3,
-	TEGRA_PULL_4,
-	TEGRA_PULL_5,
-	TEGRA_PULL_6,
-	TEGRA_PULL_7,
-	TEGRA_PULL_8,
-	TEGRA_PULL_9,
-	TEGRA_PULL_10,
-	TEGRA_PULL_11,
-	TEGRA_PULL_12,
-	TEGRA_PULL_13,
-	TEGRA_PULL_14,
-	TEGRA_PULL_15,
-	TEGRA_PULL_16,
-	TEGRA_PULL_17,
-	TEGRA_PULL_18,
-	TEGRA_PULL_19,
-	TEGRA_PULL_20,
-	TEGRA_PULL_21,
-	TEGRA_PULL_22,
-	TEGRA_PULL_23,
-	TEGRA_PULL_24,
-	TEGRA_PULL_25,
-	TEGRA_PULL_26,
-	TEGRA_PULL_27,
-	TEGRA_PULL_28,
-	TEGRA_PULL_29,
-	TEGRA_PULL_30,
-	TEGRA_PULL_31,
-	TEGRA_MAX_PULL,
-};
-
-enum tegra_drive {
-	TEGRA_DRIVE_DIV_8 = 0,
-	TEGRA_DRIVE_DIV_4,
-	TEGRA_DRIVE_DIV_2,
-	TEGRA_DRIVE_DIV_1,
-	TEGRA_MAX_DRIVE,
-};
-
-enum tegra_hsm {
-	TEGRA_HSM_DISABLE = 0,
-	TEGRA_HSM_ENABLE,
-};
-
-enum tegra_schmitt {
-	TEGRA_SCHMITT_DISABLE = 0,
-	TEGRA_SCHMITT_ENABLE,
-};
-
-struct tegra_drive_pingroup_config {
-	int pingroup;
-	enum tegra_hsm hsm;
-	enum tegra_schmitt schmitt;
-	enum tegra_drive drive;
-	enum tegra_pull_strength pull_down;
-	enum tegra_pull_strength pull_up;
-	enum tegra_slew slew_rising;
-	enum tegra_slew slew_falling;
-};
-
-struct tegra_drive_pingroup_desc {
-	const char *name;
-	s16 reg_bank;
-	s16 reg;
-};
-
-struct tegra_pingroup_desc {
-	const char *name;
-	int funcs[4];
-	int func_safe;
-	int vddio;
-	enum tegra_pin_io io_default;
-	s16 tri_bank;	/* Register bank the tri_reg exists within */
-	s16 mux_bank;	/* Register bank the mux_reg exists within */
-	s16 pupd_bank;	/* Register bank the pupd_reg exists within */
-	s16 tri_reg; 	/* offset into the TRISTATE_REG_* register bank */
-	s16 mux_reg;	/* offset into the PIN_MUX_CTL_* register bank */
-	s16 pupd_reg;	/* offset into the PULL_UPDOWN_REG_* register bank */
-	s8 tri_bit; 	/* offset into the TRISTATE_REG_* register bit */
-	s8 mux_bit;	/* offset into the PIN_MUX_CTL_* register bit */
-	s8 pupd_bit;	/* offset into the PULL_UPDOWN_REG_* register bit */
-	s8 lock_bit;	/* offset of the LOCK bit into mux register bit */
-	s8 od_bit;	/* offset of the OD bit into mux register bit */
-	s8 ioreset_bit;	/* offset of the IO_RESET bit into mux register bit */
-};
-
-typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
-	int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
-	int *pgdrive_max);
-
-void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
-	const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
-
-void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
-	const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
-
-int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
-int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
-
-void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
-	int len);
-
-void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
-	int len);
-void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
-	int len);
-void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
-	int len);
-void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
-	int len, enum tegra_tristate tristate);
-void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
-	int len, enum tegra_pullupdown pupd);
-#endif
diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
deleted file mode 100644
index 734add1..0000000
--- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
- *
- * Common pinmux configurations for Tegra20 SoCs
- *
- * Copyright (C) 2010 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <mach/iomap.h>
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-#include <mach/suspend.h>
-
-#define TRISTATE_REG_A		0x14
-#define PIN_MUX_CTL_REG_A	0x80
-#define PULLUPDOWN_REG_A	0xa0
-#define PINGROUP_REG_A		0x868
-
-#define DRIVE_PINGROUP(pg_name, r)				\
-	[TEGRA_DRIVE_PINGROUP_ ## pg_name] = {			\
-		.name = #pg_name,				\
-		.reg_bank = 3,					\
-		.reg = ((r) - PINGROUP_REG_A)			\
-	}
-
-static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
-	DRIVE_PINGROUP(AO1,		0x868),
-	DRIVE_PINGROUP(AO2,		0x86c),
-	DRIVE_PINGROUP(AT1,		0x870),
-	DRIVE_PINGROUP(AT2,		0x874),
-	DRIVE_PINGROUP(CDEV1,		0x878),
-	DRIVE_PINGROUP(CDEV2,		0x87c),
-	DRIVE_PINGROUP(CSUS,		0x880),
-	DRIVE_PINGROUP(DAP1,		0x884),
-	DRIVE_PINGROUP(DAP2,		0x888),
-	DRIVE_PINGROUP(DAP3,		0x88c),
-	DRIVE_PINGROUP(DAP4,		0x890),
-	DRIVE_PINGROUP(DBG,		0x894),
-	DRIVE_PINGROUP(LCD1,		0x898),
-	DRIVE_PINGROUP(LCD2,		0x89c),
-	DRIVE_PINGROUP(SDMMC2,		0x8a0),
-	DRIVE_PINGROUP(SDMMC3,		0x8a4),
-	DRIVE_PINGROUP(SPI,		0x8a8),
-	DRIVE_PINGROUP(UAA,		0x8ac),
-	DRIVE_PINGROUP(UAB,		0x8b0),
-	DRIVE_PINGROUP(UART2,		0x8b4),
-	DRIVE_PINGROUP(UART3,		0x8b8),
-	DRIVE_PINGROUP(VI1,		0x8bc),
-	DRIVE_PINGROUP(VI2,		0x8c0),
-	DRIVE_PINGROUP(XM2A,		0x8c4),
-	DRIVE_PINGROUP(XM2C,		0x8c8),
-	DRIVE_PINGROUP(XM2D,		0x8cc),
-	DRIVE_PINGROUP(XM2CLK,		0x8d0),
-	DRIVE_PINGROUP(MEMCOMP,		0x8d4),
-	DRIVE_PINGROUP(SDIO1,		0x8e0),
-	DRIVE_PINGROUP(CRT,		0x8ec),
-	DRIVE_PINGROUP(DDC,		0x8f0),
-	DRIVE_PINGROUP(GMA,		0x8f4),
-	DRIVE_PINGROUP(GMB,		0x8f8),
-	DRIVE_PINGROUP(GMC,		0x8fc),
-	DRIVE_PINGROUP(GMD,		0x900),
-	DRIVE_PINGROUP(GME,		0x904),
-	DRIVE_PINGROUP(OWR,		0x908),
-	DRIVE_PINGROUP(UAD,		0x90c),
-};
-
-#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe,		\
-		 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b)	\
-	[TEGRA_PINGROUP_ ## pg_name] = {			\
-		.name = #pg_name,				\
-		.vddio = TEGRA_VDDIO_ ## vdd,			\
-		.funcs = {					\
-			TEGRA_MUX_ ## f0,			\
-			TEGRA_MUX_ ## f1,			\
-			TEGRA_MUX_ ## f2,			\
-			TEGRA_MUX_ ## f3,			\
-		},						\
-		.func_safe = TEGRA_MUX_ ## f_safe,		\
-		.tri_bank = 0,					\
-		.tri_reg = ((tri_r) - TRISTATE_REG_A),		\
-		.tri_bit = tri_b,				\
-		.mux_bank = 1,					\
-		.mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A),	\
-		.mux_bit = mux_b,				\
-		.pupd_bank = 2,				\
-		.pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A),	\
-		.pupd_bit = pupd_b,				\
-		.lock_bit = -1,					\
-		.od_bit = -1,					\
-		.ioreset_bit = -1,				\
-		.io_default = -1,				\
-	}
-
-static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
-	PINGROUP(ATA,   NAND,  IDE,       NAND,      GMI,       RSVD,          IDE,       0x14, 0,  0x80, 24, 0xA0, 0),
-	PINGROUP(ATB,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 1,  0x80, 16, 0xA0, 2),
-	PINGROUP(ATC,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 2,  0x80, 22, 0xA0, 4),
-	PINGROUP(ATD,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 3,  0x80, 20, 0xA0, 6),
-	PINGROUP(ATE,   NAND,  IDE,       NAND,      GMI,       RSVD,          IDE,       0x18, 25, 0x80, 12, 0xA0, 8),
-	PINGROUP(CDEV1, AUDIO, OSC,       PLLA_OUT,  PLLM_OUT1, AUDIO_SYNC,    OSC,       0x14, 4,  0x88, 2,  0xA8, 0),
-	PINGROUP(CDEV2, AUDIO, OSC,       AHB_CLK,   APB_CLK,   PLLP_OUT4,     OSC,       0x14, 5,  0x88, 4,  0xA8, 2),
-	PINGROUP(CRTP,  LCD,   CRT,       RSVD,      RSVD,      RSVD,          RSVD,      0x20, 14, 0x98, 20, 0xA4, 24),
-	PINGROUP(CSUS,  VI,    PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6,  0x88, 6,  0xAC, 24),
-	PINGROUP(DAP1,  AUDIO, DAP1,      RSVD,      GMI,       SDIO2,         DAP1,      0x14, 7,  0x88, 20, 0xA0, 10),
-	PINGROUP(DAP2,  AUDIO, DAP2,      TWC,       RSVD,      GMI,           DAP2,      0x14, 8,  0x88, 22, 0xA0, 12),
-	PINGROUP(DAP3,  BB,    DAP3,      RSVD,      RSVD,      RSVD,          DAP3,      0x14, 9,  0x88, 24, 0xA0, 14),
-	PINGROUP(DAP4,  UART,  DAP4,      RSVD,      GMI,       RSVD,          DAP4,      0x14, 10, 0x88, 26, 0xA0, 16),
-	PINGROUP(DDC,   LCD,   I2C2,      RSVD,      RSVD,      RSVD,          RSVD4,     0x18, 31, 0x88, 0,  0xB0, 28),
-	PINGROUP(DTA,   VI,    RSVD,      SDIO2,     VI,        RSVD,          RSVD4,     0x14, 11, 0x84, 20, 0xA0, 18),
-	PINGROUP(DTB,   VI,    RSVD,      RSVD,      VI,        SPI1,          RSVD1,     0x14, 12, 0x84, 22, 0xA0, 20),
-	PINGROUP(DTC,   VI,    RSVD,      RSVD,      VI,        RSVD,          RSVD1,     0x14, 13, 0x84, 26, 0xA0, 22),
-	PINGROUP(DTD,   VI,    RSVD,      SDIO2,     VI,        RSVD,          RSVD1,     0x14, 14, 0x84, 28, 0xA0, 24),
-	PINGROUP(DTE,   VI,    RSVD,      RSVD,      VI,        SPI1,          RSVD1,     0x14, 15, 0x84, 30, 0xA0, 26),
-	PINGROUP(DTF,   VI,    I2C3,      RSVD,      VI,        RSVD,          RSVD4,     0x20, 12, 0x98, 30, 0xA0, 28),
-	PINGROUP(GMA,   NAND,  UARTE,     SPI3,      GMI,       SDIO4,         SPI3,      0x14, 28, 0x84, 0,  0xB0, 20),
-	PINGROUP(GMB,   NAND,  IDE,       NAND,      GMI,       GMI_INT,       GMI,       0x18, 29, 0x88, 28, 0xB0, 22),
-	PINGROUP(GMC,   NAND,  UARTD,     SPI4,      GMI,       SFLASH,        SPI4,      0x14, 29, 0x84, 2,  0xB0, 24),
-	PINGROUP(GMD,   NAND,  RSVD,      NAND,      GMI,       SFLASH,        GMI,       0x18, 30, 0x88, 30, 0xB0, 26),
-	PINGROUP(GME,   NAND,  RSVD,      DAP5,      GMI,       SDIO4,         GMI,       0x18, 0,  0x8C, 0,  0xA8, 24),
-	PINGROUP(GPU,   UART,  PWM,       UARTA,     GMI,       RSVD,          RSVD4,     0x14, 16, 0x8C, 4,  0xA4, 20),
-	PINGROUP(GPU7,  SYS,   RTCK,      RSVD,      RSVD,      RSVD,          RTCK,      0x20, 11, 0x98, 28, 0xA4, 6),
-	PINGROUP(GPV,   SD,    PCIE,      RSVD,      RSVD,      RSVD,          PCIE,      0x14, 17, 0x8C, 2,  0xA0, 30),
-	PINGROUP(HDINT, LCD,   HDMI,      RSVD,      RSVD,      RSVD,          HDMI,      0x1C, 23, 0x84, 4,  0xAC, 22),
-	PINGROUP(I2CP,  SYS,   I2C,       RSVD,      RSVD,      RSVD,          RSVD4,     0x14, 18, 0x88, 8,  0xA4, 2),
-	PINGROUP(IRRX,  UART,  UARTA,     UARTB,     GMI,       SPI4,          UARTB,     0x14, 20, 0x88, 18, 0xA8, 22),
-	PINGROUP(IRTX,  UART,  UARTA,     UARTB,     GMI,       SPI4,          UARTB,     0x14, 19, 0x88, 16, 0xA8, 20),
-	PINGROUP(KBCA,  SYS,   KBC,       NAND,      SDIO2,     EMC_TEST0_DLL, KBC,       0x14, 22, 0x88, 10, 0xA4, 8),
-	PINGROUP(KBCB,  SYS,   KBC,       NAND,      SDIO2,     MIO,           KBC,       0x14, 21, 0x88, 12, 0xA4, 10),
-	PINGROUP(KBCC,  SYS,   KBC,       NAND,      TRACE,     EMC_TEST1_DLL, KBC,       0x18, 26, 0x88, 14, 0xA4, 12),
-	PINGROUP(KBCD,  SYS,   KBC,       NAND,      SDIO2,     MIO,           KBC,       0x20, 10, 0x98, 26, 0xA4, 14),
-	PINGROUP(KBCE,  SYS,   KBC,       NAND,      OWR,       RSVD,          KBC,       0x14, 26, 0x80, 28, 0xB0, 2),
-	PINGROUP(KBCF,  SYS,   KBC,       NAND,      TRACE,     MIO,           KBC,       0x14, 27, 0x80, 26, 0xB0, 0),
-	PINGROUP(LCSN,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          RSVD4,     0x1C, 31, 0x90, 12, 0xAC, 20),
-	PINGROUP(LD0,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 0,  0x94, 0,  0xAC, 12),
-	PINGROUP(LD1,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 1,  0x94, 2,  0xAC, 12),
-	PINGROUP(LD10,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 10, 0x94, 20, 0xAC, 12),
-	PINGROUP(LD11,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 11, 0x94, 22, 0xAC, 12),
-	PINGROUP(LD12,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 12, 0x94, 24, 0xAC, 12),
-	PINGROUP(LD13,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 13, 0x94, 26, 0xAC, 12),
-	PINGROUP(LD14,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 14, 0x94, 28, 0xAC, 12),
-	PINGROUP(LD15,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 15, 0x94, 30, 0xAC, 12),
-	PINGROUP(LD16,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 16, 0x98, 0,  0xAC, 12),
-	PINGROUP(LD17,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 17, 0x98, 2,  0xAC, 12),
-	PINGROUP(LD2,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 2,  0x94, 4,  0xAC, 12),
-	PINGROUP(LD3,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 3,  0x94, 6,  0xAC, 12),
-	PINGROUP(LD4,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 4,  0x94, 8,  0xAC, 12),
-	PINGROUP(LD5,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 5,  0x94, 10, 0xAC, 12),
-	PINGROUP(LD6,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 6,  0x94, 12, 0xAC, 12),
-	PINGROUP(LD7,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 7,  0x94, 14, 0xAC, 12),
-	PINGROUP(LD8,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 8,  0x94, 16, 0xAC, 12),
-	PINGROUP(LD9,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 9,  0x94, 18, 0xAC, 12),
-	PINGROUP(LDC,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 30, 0x90, 14, 0xAC, 20),
-	PINGROUP(LDI,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 6,  0x98, 16, 0xAC, 18),
-	PINGROUP(LHP0,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 18, 0x98, 10, 0xAC, 16),
-	PINGROUP(LHP1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 19, 0x98, 4,  0xAC, 14),
-	PINGROUP(LHP2,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 20, 0x98, 6,  0xAC, 14),
-	PINGROUP(LHS,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x20, 7,  0x90, 22, 0xAC, 22),
-	PINGROUP(LM0,   LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          RSVD4,     0x1C, 24, 0x90, 26, 0xAC, 22),
-	PINGROUP(LM1,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      CRT,           RSVD3,     0x1C, 25, 0x90, 28, 0xAC, 22),
-	PINGROUP(LPP,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 8,  0x98, 14, 0xAC, 18),
-	PINGROUP(LPW0,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 3,  0x90, 0,  0xAC, 20),
-	PINGROUP(LPW1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 4,  0x90, 2,  0xAC, 20),
-	PINGROUP(LPW2,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 5,  0x90, 4,  0xAC, 20),
-	PINGROUP(LSC0,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 27, 0x90, 18, 0xAC, 22),
-	PINGROUP(LSC1,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x1C, 28, 0x90, 20, 0xAC, 20),
-	PINGROUP(LSCK,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x1C, 29, 0x90, 16, 0xAC, 20),
-	PINGROUP(LSDA,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 1,  0x90, 8,  0xAC, 20),
-	PINGROUP(LSDI,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          DISPLAYA,  0x20, 2,  0x90, 6,  0xAC, 20),
-	PINGROUP(LSPI,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       HDMI,          DISPLAYA,  0x20, 0,  0x90, 10, 0xAC, 22),
-	PINGROUP(LVP0,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 21, 0x90, 30, 0xAC, 22),
-	PINGROUP(LVP1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 22, 0x98, 8,  0xAC, 16),
-	PINGROUP(LVS,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 26, 0x90, 24, 0xAC, 22),
-	PINGROUP(OWC,   SYS,   OWR,       RSVD,      RSVD,      RSVD,          OWR,       0x14, 31, 0x84, 8,  0xB0, 30),
-	PINGROUP(PMC,   SYS,   PWR_ON,    PWR_INTR,  RSVD,      RSVD,          PWR_ON,    0x14, 23, 0x98, 18, -1,   -1),
-	PINGROUP(PTA,   NAND,  I2C2,      HDMI,      GMI,       RSVD,          RSVD4,     0x14, 24, 0x98, 22, 0xA4, 4),
-	PINGROUP(RM,    UART,  I2C,       RSVD,      RSVD,      RSVD,          RSVD4,     0x14, 25, 0x80, 14, 0xA4, 0),
-	PINGROUP(SDB,   SD,    UARTA,     PWM,       SDIO3,     SPI2,          PWM,       0x20, 15, 0x8C, 10, -1,   -1),
-	PINGROUP(SDC,   SD,    PWM,       TWC,       SDIO3,     SPI3,          TWC,       0x18, 1,  0x8C, 12, 0xAC, 28),
-	PINGROUP(SDD,   SD,    UARTA,     PWM,       SDIO3,     SPI3,          PWM,       0x18, 2,  0x8C, 14, 0xAC, 30),
-	PINGROUP(SDIO1, BB,    SDIO1,     RSVD,      UARTE,     UARTA,         RSVD2,     0x14, 30, 0x80, 30, 0xB0, 18),
-	PINGROUP(SLXA,  SD,    PCIE,      SPI4,      SDIO3,     SPI2,          PCIE,      0x18, 3,  0x84, 6,  0xA4, 22),
-	PINGROUP(SLXC,  SD,    SPDIF,     SPI4,      SDIO3,     SPI2,          SPI4,      0x18, 5,  0x84, 10, 0xA4, 26),
-	PINGROUP(SLXD,  SD,    SPDIF,     SPI4,      SDIO3,     SPI2,          SPI4,      0x18, 6,  0x84, 12, 0xA4, 28),
-	PINGROUP(SLXK,  SD,    PCIE,      SPI4,      SDIO3,     SPI2,          PCIE,      0x18, 7,  0x84, 14, 0xA4, 30),
-	PINGROUP(SPDI,  AUDIO, SPDIF,     RSVD,      I2C,       SDIO2,         RSVD2,     0x18, 8,  0x8C, 8,  0xA4, 16),
-	PINGROUP(SPDO,  AUDIO, SPDIF,     RSVD,      I2C,       SDIO2,         RSVD2,     0x18, 9,  0x8C, 6,  0xA4, 18),
-	PINGROUP(SPIA,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 10, 0x8C, 30, 0xA8, 4),
-	PINGROUP(SPIB,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 11, 0x8C, 28, 0xA8, 6),
-	PINGROUP(SPIC,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 12, 0x8C, 26, 0xA8, 8),
-	PINGROUP(SPID,  AUDIO, SPI2,      SPI1,      SPI2_ALT,  GMI,           GMI,       0x18, 13, 0x8C, 24, 0xA8, 10),
-	PINGROUP(SPIE,  AUDIO, SPI2,      SPI1,      SPI2_ALT,  GMI,           GMI,       0x18, 14, 0x8C, 22, 0xA8, 12),
-	PINGROUP(SPIF,  AUDIO, SPI3,      SPI1,      SPI2,      RSVD,          RSVD4,     0x18, 15, 0x8C, 20, 0xA8, 14),
-	PINGROUP(SPIG,  AUDIO, SPI3,      SPI2,      SPI2_ALT,  I2C,           SPI2_ALT,  0x18, 16, 0x8C, 18, 0xA8, 16),
-	PINGROUP(SPIH,  AUDIO, SPI3,      SPI2,      SPI2_ALT,  I2C,           SPI2_ALT,  0x18, 17, 0x8C, 16, 0xA8, 18),
-	PINGROUP(UAA,   BB,    SPI3,      MIPI_HS,   UARTA,     ULPI,          MIPI_HS,   0x18, 18, 0x80, 0,  0xAC, 0),
-	PINGROUP(UAB,   BB,    SPI2,      MIPI_HS,   UARTA,     ULPI,          MIPI_HS,   0x18, 19, 0x80, 2,  0xAC, 2),
-	PINGROUP(UAC,   BB,    OWR,       RSVD,      RSVD,      RSVD,          RSVD4,     0x18, 20, 0x80, 4,  0xAC, 4),
-	PINGROUP(UAD,   UART,  IRDA,      SPDIF,     UARTA,     SPI4,          SPDIF,     0x18, 21, 0x80, 6,  0xAC, 6),
-	PINGROUP(UCA,   UART,  UARTC,     RSVD,      GMI,       RSVD,          RSVD4,     0x18, 22, 0x84, 16, 0xAC, 8),
-	PINGROUP(UCB,   UART,  UARTC,     PWM,       GMI,       RSVD,          RSVD4,     0x18, 23, 0x84, 18, 0xAC, 10),
-	PINGROUP(UDA,   BB,    SPI1,      RSVD,      UARTD,     ULPI,          RSVD2,     0x20, 13, 0x80, 8,  0xB0, 16),
-	/* these pin groups only have pullup and pull down control */
-	PINGROUP(CK32,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 14),
-	PINGROUP(DDRC,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xAC, 26),
-	PINGROUP(PMCA,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 4),
-	PINGROUP(PMCB,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 6),
-	PINGROUP(PMCC,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 8),
-	PINGROUP(PMCD,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 10),
-	PINGROUP(PMCE,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 12),
-	PINGROUP(XM2C,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 30),
-	PINGROUP(XM2D,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 28),
-};
-
-void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
-		int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
-		int *pgdrive_max)
-{
-	*pg = tegra_soc_pingroups;
-	*pg_max = TEGRA_MAX_PINGROUP;
-	*pgdrive = tegra_soc_drive_pingroups;
-	*pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
-}
-
diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
deleted file mode 100644
index 14fc0e4..0000000
--- a/arch/arm/mach-tegra/pinmux-tegra30-tables.c
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
- *
- * Common pinmux configurations for Tegra30 SoCs
- *
- * Copyright (C) 2010,2011 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/string.h>
-
-#include <mach/iomap.h>
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra30.h>
-#include <mach/suspend.h>
-
-#define PINGROUP_REG_A	0x868
-#define MUXCTL_REG_A	0x3000
-
-#define DRIVE_PINGROUP(pg_name, r)		\
-	[TEGRA_DRIVE_PINGROUP_ ## pg_name] = {	\
-		.name = #pg_name,		\
-		.reg_bank = 0,			\
-		.reg = ((r) - PINGROUP_REG_A)	\
-	}
-
-static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
-	DRIVE_PINGROUP(AO1,		0x868),
-	DRIVE_PINGROUP(AO2,		0x86c),
-	DRIVE_PINGROUP(AT1,		0x870),
-	DRIVE_PINGROUP(AT2,		0x874),
-	DRIVE_PINGROUP(AT3,		0x878),
-	DRIVE_PINGROUP(AT4,		0x87c),
-	DRIVE_PINGROUP(AT5,		0x880),
-	DRIVE_PINGROUP(CDEV1,		0x884),
-	DRIVE_PINGROUP(CDEV2,		0x888),
-	DRIVE_PINGROUP(CSUS,		0x88c),
-	DRIVE_PINGROUP(DAP1,		0x890),
-	DRIVE_PINGROUP(DAP2,		0x894),
-	DRIVE_PINGROUP(DAP3,		0x898),
-	DRIVE_PINGROUP(DAP4,		0x89c),
-	DRIVE_PINGROUP(DBG,		0x8a0),
-	DRIVE_PINGROUP(LCD1,		0x8a4),
-	DRIVE_PINGROUP(LCD2,		0x8a8),
-	DRIVE_PINGROUP(SDIO2,		0x8ac),
-	DRIVE_PINGROUP(SDIO3,		0x8b0),
-	DRIVE_PINGROUP(SPI,		0x8b4),
-	DRIVE_PINGROUP(UAA,		0x8b8),
-	DRIVE_PINGROUP(UAB,		0x8bc),
-	DRIVE_PINGROUP(UART2,		0x8c0),
-	DRIVE_PINGROUP(UART3,		0x8c4),
-	DRIVE_PINGROUP(VI1,		0x8c8),
-	DRIVE_PINGROUP(SDIO1,		0x8ec),
-	DRIVE_PINGROUP(CRT,		0x8f8),
-	DRIVE_PINGROUP(DDC,		0x8fc),
-	DRIVE_PINGROUP(GMA,		0x900),
-	DRIVE_PINGROUP(GMB,		0x904),
-	DRIVE_PINGROUP(GMC,		0x908),
-	DRIVE_PINGROUP(GMD,		0x90c),
-	DRIVE_PINGROUP(GME,		0x910),
-	DRIVE_PINGROUP(GMF,		0x914),
-	DRIVE_PINGROUP(GMG,		0x918),
-	DRIVE_PINGROUP(GMH,		0x91c),
-	DRIVE_PINGROUP(OWR,		0x920),
-	DRIVE_PINGROUP(UAD,		0x924),
-	DRIVE_PINGROUP(GPV,		0x928),
-	DRIVE_PINGROUP(DEV3,		0x92c),
-	DRIVE_PINGROUP(CEC,		0x938),
-};
-
-#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg)	\
-	[TEGRA_PINGROUP_ ## pg_name] = {			\
-		.name = #pg_name,				\
-		.vddio = TEGRA_VDDIO_ ## vdd,			\
-		.funcs = {					\
-			TEGRA_MUX_ ## f0,			\
-			TEGRA_MUX_ ## f1,			\
-			TEGRA_MUX_ ## f2,			\
-			TEGRA_MUX_ ## f3,			\
-		},						\
-		.func_safe = TEGRA_MUX_ ## fs,			\
-		.tri_bank = 1,					\
-		.tri_reg = ((reg) - MUXCTL_REG_A),		\
-		.tri_bit = 4,					\
-		.mux_bank = 1,					\
-		.mux_reg = ((reg) - MUXCTL_REG_A),		\
-		.mux_bit = 0,					\
-		.pupd_bank = 1,					\
-		.pupd_reg = ((reg) - MUXCTL_REG_A),		\
-		.pupd_bit = 2,					\
-		.io_default = TEGRA_PIN_ ## iod,		\
-		.od_bit = 6,					\
-		.lock_bit = 7,					\
-		.ioreset_bit = 8,				\
-	}
-
-static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
-	/*       NAME		  VDD	    f0		f1          f2          f3          fSafe       io	reg */
-	PINGROUP(ULPI_DATA0,	  BB,	    SPI3,	HSI,	    UARTA,	ULPI,	    RSVD,	INPUT,	0x3000),
-	PINGROUP(ULPI_DATA1,	  BB,	    SPI3,	HSI,	    UARTA,	ULPI,	    RSVD,	INPUT,	0x3004),
-	PINGROUP(ULPI_DATA2,	  BB,	    SPI3,	HSI,	    UARTA,	ULPI,	    RSVD,	INPUT,	0x3008),
-	PINGROUP(ULPI_DATA3,	  BB,	    SPI3,	HSI,	    UARTA,	ULPI,	    RSVD,	INPUT,	0x300c),
-	PINGROUP(ULPI_DATA4,	  BB,	    SPI2,	HSI,	    UARTA,	ULPI,	    RSVD,	INPUT,	0x3010),
-	PINGROUP(ULPI_DATA5,	  BB,	    SPI2,	HSI,	    UARTA,	ULPI,	    RSVD,	INPUT,	0x3014),
-	PINGROUP(ULPI_DATA6,	  BB,	    SPI2,	HSI,	    UARTA,	ULPI,	    RSVD,	INPUT,	0x3018),
-	PINGROUP(ULPI_DATA7,	  BB,	    SPI2,	HSI,	    UARTA,	ULPI,	    RSVD,	INPUT,	0x301c),
-	PINGROUP(ULPI_CLK,	  BB,	    SPI1,	RSVD,	    UARTD,	ULPI,	    RSVD,	INPUT,	0x3020),
-	PINGROUP(ULPI_DIR,	  BB,	    SPI1,	RSVD,	    UARTD,	ULPI,	    RSVD,	INPUT,	0x3024),
-	PINGROUP(ULPI_NXT,	  BB,	    SPI1,	RSVD,	    UARTD,	ULPI,	    RSVD,	INPUT,	0x3028),
-	PINGROUP(ULPI_STP,	  BB,	    SPI1,	RSVD,	    UARTD,	ULPI,	    RSVD,	INPUT,	0x302c),
-	PINGROUP(DAP3_FS,	  BB,	    I2S2,	RSVD1,	    DISPLAYA,	DISPLAYB,   RSVD,	INPUT,	0x3030),
-	PINGROUP(DAP3_DIN,	  BB,	    I2S2,	RSVD1,	    DISPLAYA,	DISPLAYB,   RSVD,	INPUT,	0x3034),
-	PINGROUP(DAP3_DOUT,	  BB,	    I2S2,	RSVD1,	    DISPLAYA,	DISPLAYB,   RSVD,	INPUT,	0x3038),
-	PINGROUP(DAP3_SCLK,	  BB,	    I2S2,	RSVD1,	    DISPLAYA,	DISPLAYB,   RSVD,	INPUT,	0x303c),
-	PINGROUP(GPIO_PV0,	  BB,	    RSVD,	RSVD,	    RSVD,	RSVD,	    RSVD,	INPUT,	0x3040),
-	PINGROUP(GPIO_PV1,	  BB,	    RSVD,	RSVD,	    RSVD,	RSVD,	    RSVD,	INPUT,	0x3044),
-	PINGROUP(SDMMC1_CLK,	  SDMMC1,   SDIO1,	RSVD1,	    RSVD2,	INVALID,    RSVD,	INPUT,	0x3048),
-	PINGROUP(SDMMC1_CMD,	  SDMMC1,   SDIO1,	RSVD1,	    RSVD2,	INVALID,    RSVD,	INPUT,	0x304c),
-	PINGROUP(SDMMC1_DAT3,	  SDMMC1,   SDIO1,	RSVD1,	    UARTE,	INVALID,    RSVD,	INPUT,	0x3050),
-	PINGROUP(SDMMC1_DAT2,	  SDMMC1,   SDIO1,	RSVD1,	    UARTE,	INVALID,    RSVD,	INPUT,	0x3054),
-	PINGROUP(SDMMC1_DAT1,	  SDMMC1,   SDIO1,	RSVD1,	    UARTE,	INVALID,    RSVD,	INPUT,	0x3058),
-	PINGROUP(SDMMC1_DAT0,	  SDMMC1,   SDIO1,	RSVD1,	    UARTE,	INVALID,    RSVD,	INPUT,	0x305c),
-	PINGROUP(GPIO_PV2,	  SDMMC1,   OWR,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x3060),
-	PINGROUP(GPIO_PV3,	  SDMMC1,   INVALID,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x3064),
-	PINGROUP(CLK2_OUT,	  SDMMC1,   EXTPERIPH2,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x3068),
-	PINGROUP(CLK2_REQ,	  SDMMC1,   DAP,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x306c),
-	PINGROUP(LCD_PWR1,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x3070),
-	PINGROUP(LCD_PWR2,	  LCD,	    DISPLAYA,	DISPLAYB,   SPI5,	INVALID,    RSVD,	OUTPUT,	0x3074),
-	PINGROUP(LCD_SDIN,	  LCD,	    DISPLAYA,	DISPLAYB,   SPI5,	RSVD,	    RSVD,	OUTPUT,	0x3078),
-	PINGROUP(LCD_SDOUT,	  LCD,	    DISPLAYA,	DISPLAYB,   SPI5,	INVALID,    RSVD,	OUTPUT,	0x307c),
-	PINGROUP(LCD_WR_N,	  LCD,	    DISPLAYA,	DISPLAYB,   SPI5,	INVALID,    RSVD,	OUTPUT,	0x3080),
-	PINGROUP(LCD_CS0_N,	  LCD,	    DISPLAYA,	DISPLAYB,   SPI5,	RSVD,	    RSVD,	OUTPUT,	0x3084),
-	PINGROUP(LCD_DC0,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x3088),
-	PINGROUP(LCD_SCK,	  LCD,	    DISPLAYA,	DISPLAYB,   SPI5,	INVALID,    RSVD,	OUTPUT,	0x308c),
-	PINGROUP(LCD_PWR0,	  LCD,	    DISPLAYA,	DISPLAYB,   SPI5,	INVALID,    RSVD,	OUTPUT,	0x3090),
-	PINGROUP(LCD_PCLK,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x3094),
-	PINGROUP(LCD_DE,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x3098),
-	PINGROUP(LCD_HSYNC,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x309c),
-	PINGROUP(LCD_VSYNC,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30a0),
-	PINGROUP(LCD_D0,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30a4),
-	PINGROUP(LCD_D1,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30a8),
-	PINGROUP(LCD_D2,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30ac),
-	PINGROUP(LCD_D3,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30b0),
-	PINGROUP(LCD_D4,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30b4),
-	PINGROUP(LCD_D5,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30b8),
-	PINGROUP(LCD_D6,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30bc),
-	PINGROUP(LCD_D7,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30c0),
-	PINGROUP(LCD_D8,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30c4),
-	PINGROUP(LCD_D9,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30c8),
-	PINGROUP(LCD_D10,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30cc),
-	PINGROUP(LCD_D11,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30d0),
-	PINGROUP(LCD_D12,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30d4),
-	PINGROUP(LCD_D13,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30d8),
-	PINGROUP(LCD_D14,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30dc),
-	PINGROUP(LCD_D15,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30e0),
-	PINGROUP(LCD_D16,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30e4),
-	PINGROUP(LCD_D17,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30e8),
-	PINGROUP(LCD_D18,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30ec),
-	PINGROUP(LCD_D19,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30f0),
-	PINGROUP(LCD_D20,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30f4),
-	PINGROUP(LCD_D21,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30f8),
-	PINGROUP(LCD_D22,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x30fc),
-	PINGROUP(LCD_D23,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x3100),
-	PINGROUP(LCD_CS1_N,	  LCD,	    DISPLAYA,	DISPLAYB,   SPI5,	RSVD2,	    RSVD,	OUTPUT,	0x3104),
-	PINGROUP(LCD_M1,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x3108),
-	PINGROUP(LCD_DC1,	  LCD,	    DISPLAYA,	DISPLAYB,   RSVD1,	RSVD2,	    RSVD,	OUTPUT,	0x310c),
-	PINGROUP(HDMI_INT,	  LCD,	    RSVD,	RSVD,	    RSVD,	RSVD,	    RSVD,	INPUT,	0x3110),
-	PINGROUP(DDC_SCL,	  LCD,	    I2C4,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x3114),
-	PINGROUP(DDC_SDA,	  LCD,	    I2C4,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x3118),
-	PINGROUP(CRT_HSYNC,	  LCD,	    CRT,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x311c),
-	PINGROUP(CRT_VSYNC,	  LCD,	    CRT,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x3120),
-	PINGROUP(VI_D0,		  VI,	    INVALID,	RSVD1,	    VI,		RSVD2,	    RSVD,	INPUT,	0x3124),
-	PINGROUP(VI_D1,		  VI,	    INVALID,	SDIO2,	    VI,		RSVD1,	    RSVD,	INPUT,	0x3128),
-	PINGROUP(VI_D2,		  VI,	    INVALID,	SDIO2,	    VI,		RSVD1,	    RSVD,	INPUT,	0x312c),
-	PINGROUP(VI_D3,		  VI,	    INVALID,	SDIO2,	    VI,		RSVD1,	    RSVD,	INPUT,	0x3130),
-	PINGROUP(VI_D4,		  VI,	    INVALID,	SDIO2,	    VI,		RSVD1,	    RSVD,	INPUT,	0x3134),
-	PINGROUP(VI_D5,		  VI,	    INVALID,	SDIO2,	    VI,		RSVD1,	    RSVD,	INPUT,	0x3138),
-	PINGROUP(VI_D6,		  VI,	    INVALID,	SDIO2,	    VI,		RSVD1,	    RSVD,	INPUT,	0x313c),
-	PINGROUP(VI_D7,		  VI,	    INVALID,	SDIO2,	    VI,		RSVD1,	    RSVD,	INPUT,	0x3140),
-	PINGROUP(VI_D8,		  VI,	    INVALID,	SDIO2,	    VI,		RSVD1,	    RSVD,	INPUT,	0x3144),
-	PINGROUP(VI_D9,		  VI,	    INVALID,	SDIO2,	    VI,		RSVD1,	    RSVD,	INPUT,	0x3148),
-	PINGROUP(VI_D10,	  VI,	    INVALID,	RSVD1,	    VI,		RSVD2,	    RSVD,	INPUT,	0x314c),
-	PINGROUP(VI_D11,	  VI,	    INVALID,	RSVD1,	    VI,		RSVD2,	    RSVD,	INPUT,	0x3150),
-	PINGROUP(VI_PCLK,	  VI,	    RSVD1,	SDIO2,	    VI,		RSVD2,	    RSVD,	INPUT,	0x3154),
-	PINGROUP(VI_MCLK,	  VI,	    VI,		INVALID,    INVALID,	INVALID,    RSVD,	INPUT,	0x3158),
-	PINGROUP(VI_VSYNC,	  VI,	    INVALID,	RSVD1,	    VI,		RSVD2,	    RSVD,	INPUT,	0x315c),
-	PINGROUP(VI_HSYNC,	  VI,	    INVALID,	RSVD1,	    VI,		RSVD2,	    RSVD,	INPUT,	0x3160),
-	PINGROUP(UART2_RXD,	  UART,	    IRDA,	SPDIF,	    UARTA,	SPI4,	    RSVD,	INPUT,	0x3164),
-	PINGROUP(UART2_TXD,	  UART,	    IRDA,	SPDIF,	    UARTA,	SPI4,	    RSVD,	INPUT,	0x3168),
-	PINGROUP(UART2_RTS_N,	  UART,	    UARTA,	UARTB,	    GMI,	SPI4,	    RSVD,	INPUT,	0x316c),
-	PINGROUP(UART2_CTS_N,	  UART,	    UARTA,	UARTB,	    GMI,	SPI4,	    RSVD,	INPUT,	0x3170),
-	PINGROUP(UART3_TXD,	  UART,	    UARTC,	RSVD1,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3174),
-	PINGROUP(UART3_RXD,	  UART,	    UARTC,	RSVD1,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3178),
-	PINGROUP(UART3_CTS_N,	  UART,	    UARTC,	RSVD1,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x317c),
-	PINGROUP(UART3_RTS_N,	  UART,	    UARTC,	PWM0,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3180),
-	PINGROUP(GPIO_PU0,	  UART,	    OWR,	UARTA,	    GMI,	RSVD1,	    RSVD,	INPUT,	0x3184),
-	PINGROUP(GPIO_PU1,	  UART,	    RSVD1,	UARTA,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3188),
-	PINGROUP(GPIO_PU2,	  UART,	    RSVD1,	UARTA,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x318c),
-	PINGROUP(GPIO_PU3,	  UART,	    PWM0,	UARTA,	    GMI,	RSVD1,	    RSVD,	INPUT,	0x3190),
-	PINGROUP(GPIO_PU4,	  UART,	    PWM1,	UARTA,	    GMI,	RSVD1,	    RSVD,	INPUT,	0x3194),
-	PINGROUP(GPIO_PU5,	  UART,	    PWM2,	UARTA,	    GMI,	RSVD1,	    RSVD,	INPUT,	0x3198),
-	PINGROUP(GPIO_PU6,	  UART,	    PWM3,	UARTA,	    GMI,	RSVD1,	    RSVD,	INPUT,	0x319c),
-	PINGROUP(GEN1_I2C_SDA,	  UART,	    I2C,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x31a0),
-	PINGROUP(GEN1_I2C_SCL,	  UART,	    I2C,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x31a4),
-	PINGROUP(DAP4_FS,	  UART,	    I2S3,	RSVD1,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31a8),
-	PINGROUP(DAP4_DIN,	  UART,	    I2S3,	RSVD1,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31ac),
-	PINGROUP(DAP4_DOUT,	  UART,	    I2S3,	RSVD1,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31b0),
-	PINGROUP(DAP4_SCLK,	  UART,	    I2S3,	RSVD1,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31b4),
-	PINGROUP(CLK3_OUT,	  UART,	    EXTPERIPH3,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x31b8),
-	PINGROUP(CLK3_REQ,	  UART,	    DEV3,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x31bc),
-	PINGROUP(GMI_WP_N,	  GMI,	    RSVD1,	NAND,	    GMI,	GMI_ALT,    RSVD,	INPUT,	0x31c0),
-	PINGROUP(GMI_IORDY,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31c4),
-	PINGROUP(GMI_WAIT,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31c8),
-	PINGROUP(GMI_ADV_N,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31cc),
-	PINGROUP(GMI_CLK,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31d0),
-	PINGROUP(GMI_CS0_N,	  GMI,	    RSVD1,	NAND,	    GMI,	INVALID,    RSVD,	INPUT,	0x31d4),
-	PINGROUP(GMI_CS1_N,	  GMI,	    RSVD1,	NAND,	    GMI,	DTV,	    RSVD,	INPUT,	0x31d8),
-	PINGROUP(GMI_CS2_N,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31dc),
-	PINGROUP(GMI_CS3_N,	  GMI,	    RSVD1,	NAND,	    GMI,	GMI_ALT,    RSVD,	INPUT,	0x31e0),
-	PINGROUP(GMI_CS4_N,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31e4),
-	PINGROUP(GMI_CS6_N,	  GMI,	    NAND,	NAND_ALT,   GMI,	SATA,	    RSVD,	INPUT,	0x31e8),
-	PINGROUP(GMI_CS7_N,	  GMI,	    NAND,	NAND_ALT,   GMI,	GMI_ALT,    RSVD,	INPUT,	0x31ec),
-	PINGROUP(GMI_AD0,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31f0),
-	PINGROUP(GMI_AD1,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31f4),
-	PINGROUP(GMI_AD2,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31f8),
-	PINGROUP(GMI_AD3,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x31fc),
-	PINGROUP(GMI_AD4,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3200),
-	PINGROUP(GMI_AD5,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3204),
-	PINGROUP(GMI_AD6,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3208),
-	PINGROUP(GMI_AD7,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x320c),
-	PINGROUP(GMI_AD8,	  GMI,	    PWM0,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3210),
-	PINGROUP(GMI_AD9,	  GMI,	    PWM1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3214),
-	PINGROUP(GMI_AD10,	  GMI,	    PWM2,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3218),
-	PINGROUP(GMI_AD11,	  GMI,	    PWM3,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x321c),
-	PINGROUP(GMI_AD12,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3220),
-	PINGROUP(GMI_AD13,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3224),
-	PINGROUP(GMI_AD14,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x3228),
-	PINGROUP(GMI_AD15,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD2,	    RSVD,	INPUT,	0x322c),
-	PINGROUP(GMI_A16,	  GMI,	    UARTD,	SPI4,	    GMI,	GMI_ALT,    RSVD,	INPUT,	0x3230),
-	PINGROUP(GMI_A17,	  GMI,	    UARTD,	SPI4,	    GMI,	INVALID,    RSVD,	INPUT,	0x3234),
-	PINGROUP(GMI_A18,	  GMI,	    UARTD,	SPI4,	    GMI,	INVALID,    RSVD,	INPUT,	0x3238),
-	PINGROUP(GMI_A19,	  GMI,	    UARTD,	SPI4,	    GMI,	RSVD3,	    RSVD,	INPUT,	0x323c),
-	PINGROUP(GMI_WR_N,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD3,	    RSVD,	INPUT,	0x3240),
-	PINGROUP(GMI_OE_N,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD3,	    RSVD,	INPUT,	0x3244),
-	PINGROUP(GMI_DQS,	  GMI,	    RSVD1,	NAND,	    GMI,	RSVD3,	    RSVD,	INPUT,	0x3248),
-	PINGROUP(GMI_RST_N,	  GMI,	    NAND,	NAND_ALT,   GMI,	RSVD3,	    RSVD,	INPUT,	0x324c),
-	PINGROUP(GEN2_I2C_SCL,	  GMI,	    I2C2,	INVALID,    GMI,	RSVD3,	    RSVD,	INPUT,	0x3250),
-	PINGROUP(GEN2_I2C_SDA,	  GMI,	    I2C2,	INVALID,    GMI,	RSVD3,	    RSVD,	INPUT,	0x3254),
-	PINGROUP(SDMMC4_CLK,	  SDMMC4,   INVALID,	NAND,	    GMI,	SDIO4,	    RSVD,	INPUT,	0x3258),
-	PINGROUP(SDMMC4_CMD,	  SDMMC4,   I2C3,	NAND,	    GMI,	SDIO4,	    RSVD,	INPUT,	0x325c),
-	PINGROUP(SDMMC4_DAT0,	  SDMMC4,   UARTE,	SPI3,	    GMI,	SDIO4,	    RSVD,	INPUT,	0x3260),
-	PINGROUP(SDMMC4_DAT1,	  SDMMC4,   UARTE,	SPI3,	    GMI,	SDIO4,	    RSVD,	INPUT,	0x3264),
-	PINGROUP(SDMMC4_DAT2,	  SDMMC4,   UARTE,	SPI3,	    GMI,	SDIO4,	    RSVD,	INPUT,	0x3268),
-	PINGROUP(SDMMC4_DAT3,	  SDMMC4,   UARTE,	SPI3,	    GMI,	SDIO4,	    RSVD,	INPUT,	0x326c),
-	PINGROUP(SDMMC4_DAT4,	  SDMMC4,   I2C3,	I2S4,	    GMI,	SDIO4,	    RSVD,	INPUT,	0x3270),
-	PINGROUP(SDMMC4_DAT5,	  SDMMC4,   VGP3,	I2S4,	    GMI,	SDIO4,	    RSVD,	INPUT,	0x3274),
-	PINGROUP(SDMMC4_DAT6,	  SDMMC4,   VGP4,	I2S4,	    GMI,	SDIO4,	    RSVD,	INPUT,	0x3278),
-	PINGROUP(SDMMC4_DAT7,	  SDMMC4,   VGP5,	I2S4,	    GMI,	SDIO4,	    RSVD,	INPUT,	0x327c),
-	PINGROUP(SDMMC4_RST_N,	  SDMMC4,   VGP6,	RSVD1,	    RSVD2,	POPSDMMC4,  RSVD,	INPUT,	0x3280),
-	PINGROUP(CAM_MCLK,	  CAM,	    VI,		INVALID,    VI_ALT2,	POPSDMMC4,  RSVD,	INPUT,	0x3284),
-	PINGROUP(GPIO_PCC1,	  CAM,	    I2S4,	RSVD1,	    RSVD2,	POPSDMMC4,  RSVD,	INPUT,	0x3288),
-	PINGROUP(GPIO_PBB0,	  CAM,	    I2S4,	RSVD1,	    RSVD2,	POPSDMMC4,  RSVD,	INPUT,	0x328c),
-	PINGROUP(CAM_I2C_SCL,	  CAM,	    INVALID,	I2C3,	    RSVD2,	POPSDMMC4,  RSVD,	INPUT,	0x3290),
-	PINGROUP(CAM_I2C_SDA,	  CAM,	    INVALID,	I2C3,	    RSVD2,	POPSDMMC4,  RSVD,	INPUT,	0x3294),
-	PINGROUP(GPIO_PBB3,	  CAM,	    VGP3,	DISPLAYA,   DISPLAYB,	POPSDMMC4,  RSVD,	INPUT,	0x3298),
-	PINGROUP(GPIO_PBB4,	  CAM,	    VGP4,	DISPLAYA,   DISPLAYB,	POPSDMMC4,  RSVD,	INPUT,	0x329c),
-	PINGROUP(GPIO_PBB5,	  CAM,	    VGP5,	DISPLAYA,   DISPLAYB,	POPSDMMC4,  RSVD,	INPUT,	0x32a0),
-	PINGROUP(GPIO_PBB6,	  CAM,	    VGP6,	DISPLAYA,   DISPLAYB,	POPSDMMC4,  RSVD,	INPUT,	0x32a4),
-	PINGROUP(GPIO_PBB7,	  CAM,	    I2S4,	RSVD1,	    RSVD2,	POPSDMMC4,  RSVD,	INPUT,	0x32a8),
-	PINGROUP(GPIO_PCC2,	  CAM,	    I2S4,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x32ac),
-	PINGROUP(JTAG_RTCK,	  SYS,	    RTCK,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x32b0),
-	PINGROUP(PWR_I2C_SCL,	  SYS,	    I2CPWR,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x32b4),
-	PINGROUP(PWR_I2C_SDA,	  SYS,	    I2CPWR,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x32b8),
-	PINGROUP(KB_ROW0,	  SYS,	    KBC,	INVALID,    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x32bc),
-	PINGROUP(KB_ROW1,	  SYS,	    KBC,	INVALID,    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x32c0),
-	PINGROUP(KB_ROW2,	  SYS,	    KBC,	INVALID,    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x32c4),
-	PINGROUP(KB_ROW3,	  SYS,	    KBC,	INVALID,    RSVD2,	INVALID,    RSVD,	INPUT,	0x32c8),
-	PINGROUP(KB_ROW4,	  SYS,	    KBC,	INVALID,    TRACE,	RSVD3,	    RSVD,	INPUT,	0x32cc),
-	PINGROUP(KB_ROW5,	  SYS,	    KBC,	INVALID,    TRACE,	OWR,	    RSVD,	INPUT,	0x32d0),
-	PINGROUP(KB_ROW6,	  SYS,	    KBC,	INVALID,    SDIO2,	INVALID,    RSVD,	INPUT,	0x32d4),
-	PINGROUP(KB_ROW7,	  SYS,	    KBC,	INVALID,    SDIO2,	INVALID,    RSVD,	INPUT,	0x32d8),
-	PINGROUP(KB_ROW8,	  SYS,	    KBC,	INVALID,    SDIO2,	INVALID,    RSVD,	INPUT,	0x32dc),
-	PINGROUP(KB_ROW9,	  SYS,	    KBC,	INVALID,    SDIO2,	INVALID,    RSVD,	INPUT,	0x32e0),
-	PINGROUP(KB_ROW10,	  SYS,	    KBC,	INVALID,    SDIO2,	INVALID,    RSVD,	INPUT,	0x32e4),
-	PINGROUP(KB_ROW11,	  SYS,	    KBC,	INVALID,    SDIO2,	INVALID,    RSVD,	INPUT,	0x32e8),
-	PINGROUP(KB_ROW12,	  SYS,	    KBC,	INVALID,    SDIO2,	INVALID,    RSVD,	INPUT,	0x32ec),
-	PINGROUP(KB_ROW13,	  SYS,	    KBC,	INVALID,    SDIO2,	INVALID,    RSVD,	INPUT,	0x32f0),
-	PINGROUP(KB_ROW14,	  SYS,	    KBC,	INVALID,    SDIO2,	INVALID,    RSVD,	INPUT,	0x32f4),
-	PINGROUP(KB_ROW15,	  SYS,	    KBC,	INVALID,    SDIO2,	INVALID,    RSVD,	INPUT,	0x32f8),
-	PINGROUP(KB_COL0,	  SYS,	    KBC,	INVALID,    TRACE,	INVALID,    RSVD,	INPUT,	0x32fc),
-	PINGROUP(KB_COL1,	  SYS,	    KBC,	INVALID,    TRACE,	INVALID,    RSVD,	INPUT,	0x3300),
-	PINGROUP(KB_COL2,	  SYS,	    KBC,	INVALID,    TRACE,	RSVD,	    RSVD,	INPUT,	0x3304),
-	PINGROUP(KB_COL3,	  SYS,	    KBC,	INVALID,    TRACE,	RSVD,	    RSVD,	INPUT,	0x3308),
-	PINGROUP(KB_COL4,	  SYS,	    KBC,	INVALID,    TRACE,	RSVD,	    RSVD,	INPUT,	0x330c),
-	PINGROUP(KB_COL5,	  SYS,	    KBC,	INVALID,    TRACE,	RSVD,	    RSVD,	INPUT,	0x3310),
-	PINGROUP(KB_COL6,	  SYS,	    KBC,	INVALID,    TRACE,	INVALID,    RSVD,	INPUT,	0x3314),
-	PINGROUP(KB_COL7,	  SYS,	    KBC,	INVALID,    TRACE,	INVALID,    RSVD,	INPUT,	0x3318),
-	PINGROUP(CLK_32K_OUT,	  SYS,	    BLINK,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x331c),
-	PINGROUP(SYS_CLK_REQ,	  SYS,	    SYSCLK,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x3320),
-	PINGROUP(CORE_PWR_REQ,	  SYS,	    RSVD,	RSVD,	    RSVD,	RSVD,	    RSVD,	INPUT,	0x3324),
-	PINGROUP(CPU_PWR_REQ,	  SYS,	    RSVD,	RSVD,	    RSVD,	RSVD,	    RSVD,	INPUT,	0x3328),
-	PINGROUP(PWR_INT_N,	  SYS,	    RSVD,	RSVD,	    RSVD,	RSVD,	    RSVD,	INPUT,	0x332c),
-	PINGROUP(CLK_32K_IN,	  SYS,	    RSVD,	RSVD,	    RSVD,	RSVD,	    RSVD,	INPUT,	0x3330),
-	PINGROUP(OWR,		  SYS,	    OWR,	RSVD,	    RSVD,	RSVD,	    RSVD,	INPUT,	0x3334),
-	PINGROUP(DAP1_FS,	  AUDIO,    I2S0,	HDA,	    GMI,	SDIO2,	    RSVD,	INPUT,	0x3338),
-	PINGROUP(DAP1_DIN,	  AUDIO,    I2S0,	HDA,	    GMI,	SDIO2,	    RSVD,	INPUT,	0x333c),
-	PINGROUP(DAP1_DOUT,	  AUDIO,    I2S0,	HDA,	    GMI,	SDIO2,	    RSVD,	INPUT,	0x3340),
-	PINGROUP(DAP1_SCLK,	  AUDIO,    I2S0,	HDA,	    GMI,	SDIO2,	    RSVD,	INPUT,	0x3344),
-	PINGROUP(CLK1_REQ,	  AUDIO,    DAP,	HDA,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x3348),
-	PINGROUP(CLK1_OUT,	  AUDIO,    EXTPERIPH1,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x334c),
-	PINGROUP(SPDIF_IN,	  AUDIO,    SPDIF,	HDA,	    INVALID,	DAPSDMMC2,  RSVD,	INPUT,	0x3350),
-	PINGROUP(SPDIF_OUT,	  AUDIO,    SPDIF,	RSVD1,	    INVALID,	DAPSDMMC2,  RSVD,	INPUT,	0x3354),
-	PINGROUP(DAP2_FS,	  AUDIO,    I2S1,	HDA,	    RSVD2,	GMI,	    RSVD,	INPUT,	0x3358),
-	PINGROUP(DAP2_DIN,	  AUDIO,    I2S1,	HDA,	    RSVD2,	GMI,	    RSVD,	INPUT,	0x335c),
-	PINGROUP(DAP2_DOUT,	  AUDIO,    I2S1,	HDA,	    RSVD2,	GMI,	    RSVD,	INPUT,	0x3360),
-	PINGROUP(DAP2_SCLK,	  AUDIO,    I2S1,	HDA,	    RSVD2,	GMI,	    RSVD,	INPUT,	0x3364),
-	PINGROUP(SPI2_MOSI,	  AUDIO,    SPI6,	SPI2,	    INVALID,	GMI,	    RSVD,	INPUT,	0x3368),
-	PINGROUP(SPI2_MISO,	  AUDIO,    SPI6,	SPI2,	    INVALID,	GMI,	    RSVD,	INPUT,	0x336c),
-	PINGROUP(SPI2_CS0_N,	  AUDIO,    SPI6,	SPI2,	    INVALID,	GMI,	    RSVD,	INPUT,	0x3370),
-	PINGROUP(SPI2_SCK,	  AUDIO,    SPI6,	SPI2,	    INVALID,	GMI,	    RSVD,	INPUT,	0x3374),
-	PINGROUP(SPI1_MOSI,	  AUDIO,    SPI2,	SPI1,	    INVALID,	GMI,	    RSVD,	INPUT,	0x3378),
-	PINGROUP(SPI1_SCK,	  AUDIO,    SPI2,	SPI1,	    INVALID,	GMI,	    RSVD,	INPUT,	0x337c),
-	PINGROUP(SPI1_CS0_N,	  AUDIO,    SPI2,	SPI1,	    INVALID,	GMI,	    RSVD,	INPUT,	0x3380),
-	PINGROUP(SPI1_MISO,	  AUDIO,    INVALID,	SPI1,	    INVALID,	RSVD3,	    RSVD,	INPUT,	0x3384),
-	PINGROUP(SPI2_CS1_N,	  AUDIO,    INVALID,	SPI2,	    INVALID,	INVALID,    RSVD,	INPUT,	0x3388),
-	PINGROUP(SPI2_CS2_N,	  AUDIO,    INVALID,	SPI2,	    INVALID,	INVALID,    RSVD,	INPUT,	0x338c),
-	PINGROUP(SDMMC3_CLK,	  SDMMC3,   UARTA,	PWM2,	    SDIO3,	INVALID,    RSVD,	INPUT,	0x3390),
-	PINGROUP(SDMMC3_CMD,	  SDMMC3,   UARTA,	PWM3,	    SDIO3,	INVALID,    RSVD,	INPUT,	0x3394),
-	PINGROUP(SDMMC3_DAT0,	  SDMMC3,   RSVD,	RSVD1,	    SDIO3,	INVALID,    RSVD,	INPUT,	0x3398),
-	PINGROUP(SDMMC3_DAT1,	  SDMMC3,   RSVD,	RSVD1,	    SDIO3,	INVALID,    RSVD,	INPUT,	0x339c),
-	PINGROUP(SDMMC3_DAT2,	  SDMMC3,   RSVD,	PWM1,	    SDIO3,	INVALID,    RSVD,	INPUT,	0x33a0),
-	PINGROUP(SDMMC3_DAT3,	  SDMMC3,   RSVD,	PWM0,	    SDIO3,	INVALID,    RSVD,	INPUT,	0x33a4),
-	PINGROUP(SDMMC3_DAT4,	  SDMMC3,   PWM1,	INVALID,    SDIO3,	INVALID,    RSVD,	INPUT,	0x33a8),
-	PINGROUP(SDMMC3_DAT5,	  SDMMC3,   PWM0,	INVALID,    SDIO3,	INVALID,    RSVD,	INPUT,	0x33ac),
-	PINGROUP(SDMMC3_DAT6,	  SDMMC3,   SPDIF,	INVALID,    SDIO3,	INVALID,    RSVD,	INPUT,	0x33b0),
-	PINGROUP(SDMMC3_DAT7,	  SDMMC3,   SPDIF,	INVALID,    SDIO3,	INVALID,    RSVD,	INPUT,	0x33b4),
-	PINGROUP(PEX_L0_PRSNT_N,  PEXCTL,   PCIE,	HDA,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x33b8),
-	PINGROUP(PEX_L0_RST_N,	  PEXCTL,   PCIE,	HDA,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x33bc),
-	PINGROUP(PEX_L0_CLKREQ_N, PEXCTL,   PCIE,	HDA,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x33c0),
-	PINGROUP(PEX_WAKE_N,	  PEXCTL,   PCIE,	HDA,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x33c4),
-	PINGROUP(PEX_L1_PRSNT_N,  PEXCTL,   PCIE,	HDA,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x33c8),
-	PINGROUP(PEX_L1_RST_N,	  PEXCTL,   PCIE,	HDA,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x33cc),
-	PINGROUP(PEX_L1_CLKREQ_N, PEXCTL,   PCIE,	HDA,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x33d0),
-	PINGROUP(PEX_L2_PRSNT_N,  PEXCTL,   PCIE,	HDA,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x33d4),
-	PINGROUP(PEX_L2_RST_N,	  PEXCTL,   PCIE,	HDA,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x33d8),
-	PINGROUP(PEX_L2_CLKREQ_N, PEXCTL,   PCIE,	HDA,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x33dc),
-	PINGROUP(HDMI_CEC,	  SYS,      CEC,	RSVD1,	    RSVD2,	RSVD3,	    RSVD,	INPUT,	0x33e0),
-};
-
-void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
-		int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
-		int *pgdrive_max)
-{
-	*pg = tegra_soc_pingroups;
-	*pg_max = TEGRA_MAX_PINGROUP;
-	*pgdrive = tegra_soc_drive_pingroups;
-	*pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
-}
-
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
deleted file mode 100644
index 7867a12..0000000
--- a/arch/arm/mach-tegra/pinmux.c
+++ /dev/null
@@ -1,987 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/pinmux.c
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/of_device.h>
-
-#include <mach/iomap.h>
-#include <mach/pinmux.h>
-
-#define HSM_EN(reg)	(((reg) >> 2) & 0x1)
-#define SCHMT_EN(reg)	(((reg) >> 3) & 0x1)
-#define LPMD(reg)	(((reg) >> 4) & 0x3)
-#define DRVDN(reg)	(((reg) >> 12) & 0x1f)
-#define DRVUP(reg)	(((reg) >> 20) & 0x1f)
-#define SLWR(reg)	(((reg) >> 28) & 0x3)
-#define SLWF(reg)	(((reg) >> 30) & 0x3)
-
-static const struct tegra_pingroup_desc *pingroups;
-static const struct tegra_drive_pingroup_desc *drive_pingroups;
-static int pingroup_max;
-static int drive_max;
-
-static char *tegra_mux_names[TEGRA_MAX_MUX] = {
-	[TEGRA_MUX_AHB_CLK] = "AHB_CLK",
-	[TEGRA_MUX_APB_CLK] = "APB_CLK",
-	[TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
-	[TEGRA_MUX_CRT] = "CRT",
-	[TEGRA_MUX_DAP1] = "DAP1",
-	[TEGRA_MUX_DAP2] = "DAP2",
-	[TEGRA_MUX_DAP3] = "DAP3",
-	[TEGRA_MUX_DAP4] = "DAP4",
-	[TEGRA_MUX_DAP5] = "DAP5",
-	[TEGRA_MUX_DISPLAYA] = "DISPLAYA",
-	[TEGRA_MUX_DISPLAYB] = "DISPLAYB",
-	[TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
-	[TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
-	[TEGRA_MUX_GMI] = "GMI",
-	[TEGRA_MUX_GMI_INT] = "GMI_INT",
-	[TEGRA_MUX_HDMI] = "HDMI",
-	[TEGRA_MUX_I2C] = "I2C",
-	[TEGRA_MUX_I2C2] = "I2C2",
-	[TEGRA_MUX_I2C3] = "I2C3",
-	[TEGRA_MUX_IDE] = "IDE",
-	[TEGRA_MUX_IRDA] = "IRDA",
-	[TEGRA_MUX_KBC] = "KBC",
-	[TEGRA_MUX_MIO] = "MIO",
-	[TEGRA_MUX_MIPI_HS] = "MIPI_HS",
-	[TEGRA_MUX_NAND] = "NAND",
-	[TEGRA_MUX_OSC] = "OSC",
-	[TEGRA_MUX_OWR] = "OWR",
-	[TEGRA_MUX_PCIE] = "PCIE",
-	[TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
-	[TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
-	[TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
-	[TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
-	[TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
-	[TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
-	[TEGRA_MUX_PWM] = "PWM",
-	[TEGRA_MUX_PWR_INTR] = "PWR_INTR",
-	[TEGRA_MUX_PWR_ON] = "PWR_ON",
-	[TEGRA_MUX_RTCK] = "RTCK",
-	[TEGRA_MUX_SDIO1] = "SDIO1",
-	[TEGRA_MUX_SDIO2] = "SDIO2",
-	[TEGRA_MUX_SDIO3] = "SDIO3",
-	[TEGRA_MUX_SDIO4] = "SDIO4",
-	[TEGRA_MUX_SFLASH] = "SFLASH",
-	[TEGRA_MUX_SPDIF] = "SPDIF",
-	[TEGRA_MUX_SPI1] = "SPI1",
-	[TEGRA_MUX_SPI2] = "SPI2",
-	[TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
-	[TEGRA_MUX_SPI3] = "SPI3",
-	[TEGRA_MUX_SPI4] = "SPI4",
-	[TEGRA_MUX_TRACE] = "TRACE",
-	[TEGRA_MUX_TWC] = "TWC",
-	[TEGRA_MUX_UARTA] = "UARTA",
-	[TEGRA_MUX_UARTB] = "UARTB",
-	[TEGRA_MUX_UARTC] = "UARTC",
-	[TEGRA_MUX_UARTD] = "UARTD",
-	[TEGRA_MUX_UARTE] = "UARTE",
-	[TEGRA_MUX_ULPI] = "ULPI",
-	[TEGRA_MUX_VI] = "VI",
-	[TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
-	[TEGRA_MUX_XIO] = "XIO",
-	[TEGRA_MUX_BLINK] = "BLINK",
-	[TEGRA_MUX_CEC] = "CEC",
-	[TEGRA_MUX_CLK12] = "CLK12",
-	[TEGRA_MUX_DAP] = "DAP",
-	[TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
-	[TEGRA_MUX_DDR] = "DDR",
-	[TEGRA_MUX_DEV3] = "DEV3",
-	[TEGRA_MUX_DTV] = "DTV",
-	[TEGRA_MUX_VI_ALT1] = "VI_ALT1",
-	[TEGRA_MUX_VI_ALT2] = "VI_ALT2",
-	[TEGRA_MUX_VI_ALT3] = "VI_ALT3",
-	[TEGRA_MUX_EMC_DLL] = "EMC_DLL",
-	[TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
-	[TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
-	[TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
-	[TEGRA_MUX_GMI_ALT] = "GMI_ALT",
-	[TEGRA_MUX_HDA] = "HDA",
-	[TEGRA_MUX_HSI] = "HSI",
-	[TEGRA_MUX_I2C4] = "I2C4",
-	[TEGRA_MUX_I2C5] = "I2C5",
-	[TEGRA_MUX_I2CPWR] = "I2CPWR",
-	[TEGRA_MUX_I2S0] = "I2S0",
-	[TEGRA_MUX_I2S1] = "I2S1",
-	[TEGRA_MUX_I2S2] = "I2S2",
-	[TEGRA_MUX_I2S3] = "I2S3",
-	[TEGRA_MUX_I2S4] = "I2S4",
-	[TEGRA_MUX_NAND_ALT] = "NAND_ALT",
-	[TEGRA_MUX_POPSDIO4] = "POPSDIO4",
-	[TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
-	[TEGRA_MUX_PWM0] = "PWM0",
-	[TEGRA_MUX_PWM1] = "PWM2",
-	[TEGRA_MUX_PWM2] = "PWM2",
-	[TEGRA_MUX_PWM3] = "PWM3",
-	[TEGRA_MUX_SATA] = "SATA",
-	[TEGRA_MUX_SPI5] = "SPI5",
-	[TEGRA_MUX_SPI6] = "SPI6",
-	[TEGRA_MUX_SYSCLK] = "SYSCLK",
-	[TEGRA_MUX_VGP1] = "VGP1",
-	[TEGRA_MUX_VGP2] = "VGP2",
-	[TEGRA_MUX_VGP3] = "VGP3",
-	[TEGRA_MUX_VGP4] = "VGP4",
-	[TEGRA_MUX_VGP5] = "VGP5",
-	[TEGRA_MUX_VGP6] = "VGP6",
-	[TEGRA_MUX_SAFE] = "<safe>",
-};
-
-static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
-	[TEGRA_DRIVE_DIV_8] = "DIV_8",
-	[TEGRA_DRIVE_DIV_4] = "DIV_4",
-	[TEGRA_DRIVE_DIV_2] = "DIV_2",
-	[TEGRA_DRIVE_DIV_1] = "DIV_1",
-};
-
-static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
-	[TEGRA_SLEW_FASTEST] = "FASTEST",
-	[TEGRA_SLEW_FAST] = "FAST",
-	[TEGRA_SLEW_SLOW] = "SLOW",
-	[TEGRA_SLEW_SLOWEST] = "SLOWEST",
-};
-
-static DEFINE_SPINLOCK(mux_lock);
-
-static const char *pingroup_name(int pg)
-{
-	if (pg < 0 || pg >=  pingroup_max)
-		return "<UNKNOWN>";
-
-	return pingroups[pg].name;
-}
-
-static const char *func_name(enum tegra_mux_func func)
-{
-	if (func == TEGRA_MUX_RSVD1)
-		return "RSVD1";
-
-	if (func == TEGRA_MUX_RSVD2)
-		return "RSVD2";
-
-	if (func == TEGRA_MUX_RSVD3)
-		return "RSVD3";
-
-	if (func == TEGRA_MUX_RSVD4)
-		return "RSVD4";
-
-	if (func == TEGRA_MUX_NONE)
-		return "NONE";
-
-	if (func < 0 || func >=  TEGRA_MAX_MUX)
-		return "<UNKNOWN>";
-
-	return tegra_mux_names[func];
-}
-
-
-static const char *tri_name(unsigned long val)
-{
-	return val ? "TRISTATE" : "NORMAL";
-}
-
-static const char *pupd_name(unsigned long val)
-{
-	switch (val) {
-	case 0:
-		return "NORMAL";
-
-	case 1:
-		return "PULL_DOWN";
-
-	case 2:
-		return "PULL_UP";
-
-	default:
-		return "RSVD";
-	}
-}
-
-static int nbanks;
-static void __iomem **regs;
-
-static inline u32 pg_readl(u32 bank, u32 reg)
-{
-	return readl(regs[bank] + reg);
-}
-
-static inline void pg_writel(u32 val, u32 bank, u32 reg)
-{
-	writel(val, regs[bank] + reg);
-}
-
-static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
-{
-	int mux = -1;
-	int i;
-	unsigned long reg;
-	unsigned long flags;
-	int pg = config->pingroup;
-	enum tegra_mux_func func = config->func;
-
-	if (pg < 0 || pg >=  pingroup_max)
-		return -ERANGE;
-
-	if (pingroups[pg].mux_reg < 0)
-		return -EINVAL;
-
-	if (func < 0)
-		return -ERANGE;
-
-	if (func == TEGRA_MUX_SAFE)
-		func = pingroups[pg].func_safe;
-
-	if (func & TEGRA_MUX_RSVD) {
-		mux = func & 0x3;
-	} else {
-		for (i = 0; i < 4; i++) {
-			if (pingroups[pg].funcs[i] == func) {
-				mux = i;
-				break;
-			}
-		}
-	}
-
-	if (mux < 0)
-		return -EINVAL;
-
-	spin_lock_irqsave(&mux_lock, flags);
-
-	reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
-	reg &= ~(0x3 << pingroups[pg].mux_bit);
-	reg |= mux << pingroups[pg].mux_bit;
-	pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
-
-	spin_unlock_irqrestore(&mux_lock, flags);
-
-	return 0;
-}
-
-int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
-{
-	unsigned long reg;
-	unsigned long flags;
-
-	if (pg < 0 || pg >=  pingroup_max)
-		return -ERANGE;
-
-	if (pingroups[pg].tri_reg < 0)
-		return -EINVAL;
-
-	spin_lock_irqsave(&mux_lock, flags);
-
-	reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
-	reg &= ~(0x1 << pingroups[pg].tri_bit);
-	if (tristate)
-		reg |= 1 << pingroups[pg].tri_bit;
-	pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
-
-	spin_unlock_irqrestore(&mux_lock, flags);
-
-	return 0;
-}
-
-int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
-{
-	unsigned long reg;
-	unsigned long flags;
-
-	if (pg < 0 || pg >=  pingroup_max)
-		return -ERANGE;
-
-	if (pingroups[pg].pupd_reg < 0)
-		return -EINVAL;
-
-	if (pupd != TEGRA_PUPD_NORMAL &&
-	    pupd != TEGRA_PUPD_PULL_DOWN &&
-	    pupd != TEGRA_PUPD_PULL_UP)
-		return -EINVAL;
-
-
-	spin_lock_irqsave(&mux_lock, flags);
-
-	reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
-	reg &= ~(0x3 << pingroups[pg].pupd_bit);
-	reg |= pupd << pingroups[pg].pupd_bit;
-	pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
-
-	spin_unlock_irqrestore(&mux_lock, flags);
-
-	return 0;
-}
-
-static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
-{
-	int pingroup = config->pingroup;
-	enum tegra_mux_func func     = config->func;
-	enum tegra_pullupdown pupd   = config->pupd;
-	enum tegra_tristate tristate = config->tristate;
-	int err;
-
-	if (pingroups[pingroup].mux_reg >= 0) {
-		err = tegra_pinmux_set_func(config);
-		if (err < 0)
-			pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
-			       pingroup_name(pingroup), func_name(func), err);
-	}
-
-	if (pingroups[pingroup].pupd_reg >= 0) {
-		err = tegra_pinmux_set_pullupdown(pingroup, pupd);
-		if (err < 0)
-			pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
-			       pingroup_name(pingroup), pupd_name(pupd), err);
-	}
-
-	if (pingroups[pingroup].tri_reg >= 0) {
-		err = tegra_pinmux_set_tristate(pingroup, tristate);
-		if (err < 0)
-			pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
-			       pingroup_name(pingroup), tri_name(func), err);
-	}
-}
-
-void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++)
-		tegra_pinmux_config_pingroup(&config[i]);
-}
-
-static const char *drive_pinmux_name(int pg)
-{
-	if (pg < 0 || pg >=  drive_max)
-		return "<UNKNOWN>";
-
-	return drive_pingroups[pg].name;
-}
-
-static const char *enable_name(unsigned long val)
-{
-	return val ? "ENABLE" : "DISABLE";
-}
-
-static const char *drive_name(unsigned long val)
-{
-	if (val >= TEGRA_MAX_DRIVE)
-		return "<UNKNOWN>";
-
-	return tegra_drive_names[val];
-}
-
-static const char *slew_name(unsigned long val)
-{
-	if (val >= TEGRA_MAX_SLEW)
-		return "<UNKNOWN>";
-
-	return tegra_slew_names[val];
-}
-
-static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
-{
-	unsigned long flags;
-	u32 reg;
-	if (pg < 0 || pg >=  drive_max)
-		return -ERANGE;
-
-	if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
-		return -EINVAL;
-
-	spin_lock_irqsave(&mux_lock, flags);
-
-	reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-	if (hsm == TEGRA_HSM_ENABLE)
-		reg |= (1 << 2);
-	else
-		reg &= ~(1 << 2);
-	pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-	spin_unlock_irqrestore(&mux_lock, flags);
-
-	return 0;
-}
-
-static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
-{
-	unsigned long flags;
-	u32 reg;
-	if (pg < 0 || pg >=  drive_max)
-		return -ERANGE;
-
-	if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
-		return -EINVAL;
-
-	spin_lock_irqsave(&mux_lock, flags);
-
-	reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-	if (schmitt == TEGRA_SCHMITT_ENABLE)
-		reg |= (1 << 3);
-	else
-		reg &= ~(1 << 3);
-	pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-	spin_unlock_irqrestore(&mux_lock, flags);
-
-	return 0;
-}
-
-static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
-{
-	unsigned long flags;
-	u32 reg;
-	if (pg < 0 || pg >=  drive_max)
-		return -ERANGE;
-
-	if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
-		return -EINVAL;
-
-	spin_lock_irqsave(&mux_lock, flags);
-
-	reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-	reg &= ~(0x3 << 4);
-	reg |= drive << 4;
-	pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-	spin_unlock_irqrestore(&mux_lock, flags);
-
-	return 0;
-}
-
-static int tegra_drive_pinmux_set_pull_down(int pg,
-	enum tegra_pull_strength pull_down)
-{
-	unsigned long flags;
-	u32 reg;
-	if (pg < 0 || pg >=  drive_max)
-		return -ERANGE;
-
-	if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
-		return -EINVAL;
-
-	spin_lock_irqsave(&mux_lock, flags);
-
-	reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-	reg &= ~(0x1f << 12);
-	reg |= pull_down << 12;
-	pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-	spin_unlock_irqrestore(&mux_lock, flags);
-
-	return 0;
-}
-
-static int tegra_drive_pinmux_set_pull_up(int pg,
-	enum tegra_pull_strength pull_up)
-{
-	unsigned long flags;
-	u32 reg;
-	if (pg < 0 || pg >=  drive_max)
-		return -ERANGE;
-
-	if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
-		return -EINVAL;
-
-	spin_lock_irqsave(&mux_lock, flags);
-
-	reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-	reg &= ~(0x1f << 12);
-	reg |= pull_up << 12;
-	pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-	spin_unlock_irqrestore(&mux_lock, flags);
-
-	return 0;
-}
-
-static int tegra_drive_pinmux_set_slew_rising(int pg,
-	enum tegra_slew slew_rising)
-{
-	unsigned long flags;
-	u32 reg;
-	if (pg < 0 || pg >=  drive_max)
-		return -ERANGE;
-
-	if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
-		return -EINVAL;
-
-	spin_lock_irqsave(&mux_lock, flags);
-
-	reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-	reg &= ~(0x3 << 28);
-	reg |= slew_rising << 28;
-	pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-	spin_unlock_irqrestore(&mux_lock, flags);
-
-	return 0;
-}
-
-static int tegra_drive_pinmux_set_slew_falling(int pg,
-	enum tegra_slew slew_falling)
-{
-	unsigned long flags;
-	u32 reg;
-	if (pg < 0 || pg >=  drive_max)
-		return -ERANGE;
-
-	if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
-		return -EINVAL;
-
-	spin_lock_irqsave(&mux_lock, flags);
-
-	reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-	reg &= ~(0x3 << 30);
-	reg |= slew_falling << 30;
-	pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-
-	spin_unlock_irqrestore(&mux_lock, flags);
-
-	return 0;
-}
-
-static void tegra_drive_pinmux_config_pingroup(int pingroup,
-					  enum tegra_hsm hsm,
-					  enum tegra_schmitt schmitt,
-					  enum tegra_drive drive,
-					  enum tegra_pull_strength pull_down,
-					  enum tegra_pull_strength pull_up,
-					  enum tegra_slew slew_rising,
-					  enum tegra_slew slew_falling)
-{
-	int err;
-
-	err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
-	if (err < 0)
-		pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
-			drive_pinmux_name(pingroup),
-			enable_name(hsm), err);
-
-	err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
-	if (err < 0)
-		pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
-			drive_pinmux_name(pingroup),
-			enable_name(schmitt), err);
-
-	err = tegra_drive_pinmux_set_drive(pingroup, drive);
-	if (err < 0)
-		pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
-			drive_pinmux_name(pingroup),
-			drive_name(drive), err);
-
-	err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
-	if (err < 0)
-		pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
-			drive_pinmux_name(pingroup),
-			pull_down, err);
-
-	err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
-	if (err < 0)
-		pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
-			drive_pinmux_name(pingroup),
-			pull_up, err);
-
-	err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
-	if (err < 0)
-		pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
-			drive_pinmux_name(pingroup),
-			slew_name(slew_rising), err);
-
-	err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
-	if (err < 0)
-		pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
-			drive_pinmux_name(pingroup),
-			slew_name(slew_falling), err);
-}
-
-void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
-	int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++)
-		tegra_drive_pinmux_config_pingroup(config[i].pingroup,
-						     config[i].hsm,
-						     config[i].schmitt,
-						     config[i].drive,
-						     config[i].pull_down,
-						     config[i].pull_up,
-						     config[i].slew_rising,
-						     config[i].slew_falling);
-}
-
-void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
-	int len)
-{
-	int i;
-	struct tegra_pingroup_config c;
-
-	for (i = 0; i < len; i++) {
-		int err;
-		c = config[i];
-		if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
-			WARN_ON(1);
-			continue;
-		}
-		c.func = pingroups[c.pingroup].func_safe;
-		err = tegra_pinmux_set_func(&c);
-		if (err < 0)
-			pr_err("%s: tegra_pinmux_set_func returned %d setting "
-			       "%s to %s\n", __func__, err,
-			       pingroup_name(c.pingroup), func_name(c.func));
-	}
-}
-
-void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
-	int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++) {
-		int err;
-		if (config[i].pingroup < 0 ||
-		    config[i].pingroup >= pingroup_max) {
-			WARN_ON(1);
-			continue;
-		}
-		err = tegra_pinmux_set_func(&config[i]);
-		if (err < 0)
-			pr_err("%s: tegra_pinmux_set_func returned %d setting "
-			       "%s to %s\n", __func__, err,
-			       pingroup_name(config[i].pingroup),
-			       func_name(config[i].func));
-	}
-}
-
-void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
-	int len, enum tegra_tristate tristate)
-{
-	int i;
-	int err;
-	int pingroup;
-
-	for (i = 0; i < len; i++) {
-		pingroup = config[i].pingroup;
-		if (pingroups[pingroup].tri_reg >= 0) {
-			err = tegra_pinmux_set_tristate(pingroup, tristate);
-			if (err < 0)
-				pr_err("pinmux: can't set pingroup %s tristate"
-					" to %s: %d\n",	pingroup_name(pingroup),
-					tri_name(tristate), err);
-		}
-	}
-}
-
-void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
-	int len, enum tegra_pullupdown pupd)
-{
-	int i;
-	int err;
-	int pingroup;
-
-	for (i = 0; i < len; i++) {
-		pingroup = config[i].pingroup;
-		if (pingroups[pingroup].pupd_reg >= 0) {
-			err = tegra_pinmux_set_pullupdown(pingroup, pupd);
-			if (err < 0)
-				pr_err("pinmux: can't set pingroup %s pullupdown"
-					" to %s: %d\n",	pingroup_name(pingroup),
-					pupd_name(pupd), err);
-		}
-	}
-}
-
-static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-	{ .compatible = "nvidia,tegra20-pinmux-disabled", tegra20_pinmux_init },
-#endif
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-	{ .compatible = "nvidia,tegra30-pinmux-disabled", tegra30_pinmux_init },
-#endif
-	{ },
-};
-
-static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
-{
-	struct resource *res;
-	int i;
-	int config_bad = 0;
-	const struct of_device_id *match;
-
-	match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
-
-	if (match)
-		((pinmux_init)(match->data))(&pingroups, &pingroup_max,
-			&drive_pingroups, &drive_max);
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-	else
-		/* no device tree available, so we must be on tegra20 */
-		tegra20_pinmux_init(&pingroups, &pingroup_max,
-					&drive_pingroups, &drive_max);
-#else
-	pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
-#endif
-
-	for (i = 0; ; i++) {
-		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-		if (!res)
-			break;
-	}
-	nbanks = i;
-
-	for (i = 0; i < pingroup_max; i++) {
-		if (pingroups[i].tri_bank >= nbanks) {
-			dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
-			config_bad = 1;
-		}
-
-		if (pingroups[i].mux_bank >= nbanks) {
-			dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
-			config_bad = 1;
-		}
-
-		if (pingroups[i].pupd_bank >= nbanks) {
-			dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
-			config_bad = 1;
-		}
-	}
-
-	for (i = 0; i < drive_max; i++) {
-		if (drive_pingroups[i].reg_bank >= nbanks) {
-			dev_err(&pdev->dev,
-				"drive pingroup %d: bad reg_bank\n", i);
-			config_bad = 1;
-		}
-	}
-
-	if (config_bad)
-		return -ENODEV;
-
-	regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
-	if (!regs) {
-		dev_err(&pdev->dev, "Can't alloc regs pointer\n");
-		return -ENODEV;
-	}
-
-	for (i = 0; i < nbanks; i++) {
-		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-		if (!res) {
-			dev_err(&pdev->dev, "Missing MEM resource\n");
-			return -ENODEV;
-		}
-
-		if (!devm_request_mem_region(&pdev->dev, res->start,
-					    resource_size(res),
-					    dev_name(&pdev->dev))) {
-			dev_err(&pdev->dev,
-				"Couldn't request MEM resource %d\n", i);
-			return -ENODEV;
-		}
-
-		regs[i] = devm_ioremap(&pdev->dev, res->start,
-					resource_size(res));
-		if (!regs) {
-			dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
-			return -ENODEV;
-		}
-	}
-
-	return 0;
-}
-
-static struct platform_driver tegra_pinmux_driver = {
-	.driver		= {
-		.name	= "tegra-pinmux-disabled",
-		.owner	= THIS_MODULE,
-		.of_match_table = tegra_pinmux_of_match,
-	},
-	.probe		= tegra_pinmux_probe,
-};
-
-static int __init tegra_pinmux_init(void)
-{
-	return platform_driver_register(&tegra_pinmux_driver);
-}
-postcore_initcall(tegra_pinmux_init);
-
-#ifdef	CONFIG_DEBUG_FS
-
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-
-static void dbg_pad_field(struct seq_file *s, int len)
-{
-	seq_putc(s, ',');
-
-	while (len-- > -1)
-		seq_putc(s, ' ');
-}
-
-static int dbg_pinmux_show(struct seq_file *s, void *unused)
-{
-	int i;
-	int len;
-
-	for (i = 0; i < pingroup_max; i++) {
-		unsigned long reg;
-		unsigned long tri;
-		unsigned long mux;
-		unsigned long pupd;
-
-		seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
-		len = strlen(pingroups[i].name);
-		dbg_pad_field(s, 5 - len);
-
-		if (pingroups[i].mux_reg < 0) {
-			seq_printf(s, "TEGRA_MUX_NONE");
-			len = strlen("NONE");
-		} else {
-			reg = pg_readl(pingroups[i].mux_bank,
-					pingroups[i].mux_reg);
-			mux = (reg >> pingroups[i].mux_bit) & 0x3;
-			if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
-				seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
-				len = 5;
-			} else {
-				seq_printf(s, "TEGRA_MUX_%s",
-					   tegra_mux_names[pingroups[i].funcs[mux]]);
-				len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
-			}
-		}
-		dbg_pad_field(s, 13-len);
-
-		if (pingroups[i].pupd_reg < 0) {
-			seq_printf(s, "TEGRA_PUPD_NORMAL");
-			len = strlen("NORMAL");
-		} else {
-			reg = pg_readl(pingroups[i].pupd_bank,
-					pingroups[i].pupd_reg);
-			pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
-			seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
-			len = strlen(pupd_name(pupd));
-		}
-		dbg_pad_field(s, 9 - len);
-
-		if (pingroups[i].tri_reg < 0) {
-			seq_printf(s, "TEGRA_TRI_NORMAL");
-		} else {
-			reg = pg_readl(pingroups[i].tri_bank,
-					pingroups[i].tri_reg);
-			tri = (reg >> pingroups[i].tri_bit) & 0x1;
-
-			seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
-		}
-		seq_printf(s, "},\n");
-	}
-	return 0;
-}
-
-static int dbg_pinmux_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, dbg_pinmux_show, &inode->i_private);
-}
-
-static const struct file_operations debug_fops = {
-	.open		= dbg_pinmux_open,
-	.read		= seq_read,
-	.llseek		= seq_lseek,
-	.release	= single_release,
-};
-
-static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
-{
-	int i;
-	int len;
-
-	for (i = 0; i < drive_max; i++) {
-		u32 reg;
-
-		seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
-			drive_pingroups[i].name);
-		len = strlen(drive_pingroups[i].name);
-		dbg_pad_field(s, 7 - len);
-
-
-		reg = pg_readl(drive_pingroups[i].reg_bank,
-				drive_pingroups[i].reg);
-		if (HSM_EN(reg)) {
-			seq_printf(s, "TEGRA_HSM_ENABLE");
-			len = 16;
-		} else {
-			seq_printf(s, "TEGRA_HSM_DISABLE");
-			len = 17;
-		}
-		dbg_pad_field(s, 17 - len);
-
-		if (SCHMT_EN(reg)) {
-			seq_printf(s, "TEGRA_SCHMITT_ENABLE");
-			len = 21;
-		} else {
-			seq_printf(s, "TEGRA_SCHMITT_DISABLE");
-			len = 22;
-		}
-		dbg_pad_field(s, 22 - len);
-
-		seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
-		len = strlen(drive_name(LPMD(reg)));
-		dbg_pad_field(s, 5 - len);
-
-		seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
-		len = DRVDN(reg) < 10 ? 1 : 2;
-		dbg_pad_field(s, 2 - len);
-
-		seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
-		len = DRVUP(reg) < 10 ? 1 : 2;
-		dbg_pad_field(s, 2 - len);
-
-		seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
-		len = strlen(slew_name(SLWR(reg)));
-		dbg_pad_field(s, 7 - len);
-
-		seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
-
-		seq_printf(s, "},\n");
-	}
-	return 0;
-}
-
-static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
-}
-
-static const struct file_operations debug_drive_fops = {
-	.open		= dbg_drive_pinmux_open,
-	.read		= seq_read,
-	.llseek		= seq_lseek,
-	.release	= single_release,
-};
-
-static int __init tegra_pinmux_debuginit(void)
-{
-	(void) debugfs_create_file("tegra_pinmux", S_IRUGO,
-					NULL, NULL, &debug_fops);
-	(void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
-					NULL, NULL, &debug_drive_fops);
-	return 0;
-}
-late_initcall(tegra_pinmux_debuginit);
-#endif
-- 
1.7.0.4



From swarren at wwwdotorg.org  Fri Mar 30 19:00:04 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Fri, 30 Mar 2012 17:00:04 -0600
Subject: [PATCH 11/11] ARM: dt: tegra20: add pinmux to device tree
In-Reply-To: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
References: <1333148404-17691-1-git-send-email-swarren@wwwdotorg.org>
Message-ID: <1333148404-17691-12-git-send-email-swarren@wwwdotorg.org>

From: Stephen Warren <swarren at nvidia.com>

This adds a complete pinmux configuration to all Tegra20 device tree
files. This allows removal of board-dt-tegra20.c's use of the pinmux
board files, and the special device tree handling in board-pinmux.c.

Signed-off-by: Stephen Warren <swarren at nvidia.com>
---
 arch/arm/boot/dts/tegra-harmony.dts    |  224 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra-paz00.dts      |  220 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra-seaboard.dts   |  243 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra-trimslice.dts  |  230 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra-ventana.dts    |  230 ++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/board-dt-tegra20.c |   30 ----
 arch/arm/mach-tegra/board-pinmux.c     |    4 +-
 7 files changed, 1148 insertions(+), 33 deletions(-)

diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 6e8447d..1a0b1f1 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -10,6 +10,230 @@
 		reg = < 0x00000000 0x40000000 >;
 	};
 
+	pinmux at 70000000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+					"spia", "spib", "spic";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			dta {
+				nvidia,pins = "dta", "dtd";
+				nvidia,function = "sdio2";
+			};
+			dtb {
+				nvidia,pins = "dtb", "dtc", "dte";
+				nvidia,function = "rsvd1";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint", "pta";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uarta";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+					"ld3", "ld4", "ld5", "ld6", "ld7",
+					"ld8", "ld9", "ld10", "ld11", "ld12",
+					"ld13", "ld14", "ld15", "ld16", "ld17",
+					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
+					"lhs", "lm0", "lm1", "lpp", "lpw0",
+					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
+					"lvs";
+				nvidia,function = "displaya";
+			};
+			owc {
+				nvidia,pins = "owc", "spdi", "spdo", "uac";
+				nvidia,function = "rsvd2";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "pwm";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxc {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "spdif";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+					"cdev1", "dap1", "dtb", "gma", "gmb",
+					"gmc", "gmd", "gme", "gpu7", "gpv",
+					"i2cp", "pta", "rm", "slxa", "slxk",
+					"spia", "spib";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			conf_cdev2 {
+				nvidia,pins = "cdev2", "csus", "spid", "spif";
+				nvidia,pull = <1>;
+				nvidia,tristate = <1>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <0>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+					"dtc", "dte", "dtf", "gpu", "sdio1",
+					"slxc", "slxd", "spdi", "spdo", "spig",
+					"uac", "uda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			conf_ddc {
+				nvidia,pins = "ddc", "dta", "dtd", "kbca",
+					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+					"sdc";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
+					"lvp0", "owc", "sdb";
+				nvidia,tristate = <1>;
+			};
+			conf_irrx {
+				nvidia,pins = "irrx", "irtx", "sdd", "spic",
+					"spie", "spih", "uaa", "uab", "uad",
+					"uca", "ucb";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <2>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+					"lvs", "pmc";
+				nvidia,tristate = <0>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <1>;
+			};
+		};
+	};
+
 	pmc at 7000f400 {
 		nvidia,invert-interrupt;
 	};
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 6c02abb..10943fb 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -10,6 +10,226 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
+	pinmux at 70000000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata", "atc", "atd", "ate",
+					"dap2", "gmb", "gmc", "gmd", "spia",
+					"spib", "spic", "spid", "spie";
+				nvidia,function = "gmi";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "pllc_out1";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+				nvidia,function = "rsvd1";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gpu {
+				nvidia,pins = "gpu", "sdb", "sdd";
+				nvidia,function = "pwm";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint", "pta";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uarta";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			kbcb {
+				nvidia,pins = "kbcb", "kbcd";
+				nvidia,function = "sdio2";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+					"ld3", "ld4", "ld5", "ld6", "ld7",
+					"ld8", "ld9", "ld10", "ld11", "ld12",
+					"ld13", "ld14", "ld15", "ld16", "ld17",
+					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
+					"lhs", "lm0", "lm1", "lpp", "lpw0",
+					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
+					"lvs";
+				nvidia,function = "displaya";
+			};
+			owc {
+				nvidia,pins = "owc";
+				nvidia,function = "owr";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdc {
+				nvidia,pins = "sdc";
+				nvidia,function = "twc";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxc {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "spi4";
+			};
+			spdi {
+				nvidia,pins = "spdi", "spdo";
+				nvidia,function = "rsvd2";
+			};
+			spif {
+				nvidia,pins = "spif", "uac";
+				nvidia,function = "rsvd4";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "spdif";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+					"cdev1", "dap1", "dap2", "dtf", "gma",
+					"gmb", "gmc", "gmd", "gme", "gpu",
+					"gpu7", "gpv", "i2cp", "pta", "rm",
+					"sdio1", "slxk", "spdo", "uac", "uda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			conf_cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <0>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "dap3", "dap4", "dtb",
+					"dtc", "dte", "slxa", "slxc", "slxd",
+					"spdi";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			conf_csus {
+				nvidia,pins = "csus", "spia", "spib", "spid",
+					"spif";
+				nvidia,pull = <1>;
+				nvidia,tristate = <1>;
+			};
+			conf_ddc {
+				nvidia,pins = "ddc", "irrx", "irtx", "kbca",
+					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+					"spic", "spig", "uaa", "uab";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+			conf_dta {
+				nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
+					"spie", "spih", "uad", "uca", "ucb";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "ld0", "ld1", "ld2",
+					"ld3", "ld4", "ld5", "ld6", "ld7",
+					"ld8", "ld9", "ld10", "ld11", "ld12",
+					"ld13", "ld14", "ld15", "ld16", "ld17",
+					"ldc", "ldi", "lhs", "lsc0", "lspi",
+					"lvs", "pmc";
+				nvidia,tristate = <0>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <2>;
+			};
+			conf_lcsn {
+				nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
+					"lm0", "lm1", "lpp", "lpw0", "lpw1",
+					"lpw2", "lsc1", "lsck", "lsda", "lsdi",
+					"lvp0", "lvp1", "sdb";
+				nvidia,tristate = <1>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <1>;
+			};
+		};
+	};
+
 	i2c at 7000c000 {
 		clock-frequency = <400000>;
 
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index dbf1c5a..ec33116 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -11,6 +11,249 @@
 		reg = < 0x00000000 0x40000000 >;
 	};
 
+	pinmux at 70000000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gmb", "spia",
+					"spib", "spic";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp", "lm1";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			ddc {
+				nvidia,pins = "ddc", "owc", "spdi", "spdo",
+					"uac";
+				nvidia,function = "rsvd2";
+			};
+			dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+				nvidia,function = "vi";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gmd {
+				nvidia,pins = "gmd";
+				nvidia,function = "sflash";
+			};
+			gpu {
+				nvidia,pins = "gpu";
+				nvidia,function = "pwm";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
+					"lsck", "lsda", "pta";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uartb";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+					"lsdi", "lvp0";
+				nvidia,function = "rsvd4";
+			};
+			ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lpp", "lsc0",
+					"lspi", "lvp1", "lvs";
+				nvidia,function = "displaya";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "sdio3";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxc {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "spdif";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd",
+					"cdev1", "cdev2", "dap1", "dap2",
+					"dap4", "dtf", "gma", "gmc", "gmd",
+					"gme", "gpu", "gpu7", "i2cp", "irrx",
+					"irtx", "pta", "rm", "sdc", "sdd",
+					"slxd", "slxk", "spdi", "spdo", "uac",
+					"uad", "uca", "ucb", "uda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			conf_ate {
+				nvidia,pins = "ate", "csus", "dap3", "ddc",
+					"gpv", "owc", "slxc", "spib", "spid",
+					"spie";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <0>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "gmb", "slxa", "spia",
+					"spig", "spih";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			conf_dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+			};
+			conf_dte {
+				nvidia,pins = "dte", "spif";
+				nvidia,pull = <1>;
+				nvidia,tristate = <1>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
+					"lvp0";
+				nvidia,tristate = <1>;
+			};
+			conf_kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf", "sdio1", "spic", "uaa",
+					"uab";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <2>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+					"lvs", "pmc", "sdb";
+				nvidia,tristate = <0>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <1>;
+			};
+			drive_sdio1 {
+				nvidia,pins = "drive_sdio1";
+				nvidia,high-speed-mode = <0>;
+				nvidia,schmitt = <0>;
+				nvidia,low-power-mode = <3>;
+				nvidia,pull-down-strength = <31>;
+				nvidia,pull-up-strength = <31>;
+				nvidia,slew-rate-rising = <3>;
+				nvidia,slew-rate-falling = <3>;
+			};
+		};
+	};
+
 	i2c at 7000c000 {
 		clock-frequency = <400000>;
 
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 2524768..98efd5b 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -10,6 +10,236 @@
 		reg = < 0x00000000 0x40000000 >;
 	};
 
+	pinmux at 70000000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc", "gmb";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gme", "pta";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			ddc {
+				nvidia,pins = "ddc";
+				nvidia,function = "i2c2";
+			};
+			dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+				nvidia,function = "vi";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc", "gmd";
+				nvidia,function = "sflash";
+			};
+			gpu {
+				nvidia,pins = "gpu";
+				nvidia,function = "uarta";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uartb";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+					"ld3", "ld4", "ld5", "ld6", "ld7",
+					"ld8", "ld9", "ld10", "ld11", "ld12",
+					"ld13", "ld14", "ld15", "ld16", "ld17",
+					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
+					"lhs", "lm0", "lm1", "lpp", "lpw0",
+					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
+					"lvs";
+				nvidia,function = "displaya";
+			};
+			owc {
+				nvidia,pins = "owc", "uac";
+				nvidia,function = "rsvd2";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd";
+				nvidia,function = "pwm";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxc {
+				nvidia,pins = "slxc", "slxd";
+				nvidia,function = "sdio3";
+			};
+			spdi {
+				nvidia,pins = "spdi", "spdo";
+				nvidia,function = "spdif";
+			};
+			spia {
+				nvidia,pins = "spia", "spib", "spic";
+				nvidia,function = "spi2";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atc", "atd", "ate",
+					"crtp", "dap2", "dap3", "dap4", "dta",
+					"dtb", "dtc", "dtd", "dte", "gmb",
+					"gme", "i2cp", "pta", "slxc", "slxd",
+					"spdi", "spdo", "uda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			conf_atb {
+				nvidia,pins = "atb", "cdev1", "dap1", "gma",
+					"gmc", "gmd", "gpu", "gpu7", "gpv",
+					"sdio1", "slxa", "slxk", "uac";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			conf_cdev2 {
+				nvidia,pins = "cdev2", "csus", "spia", "spib",
+					"spid", "spif";
+				nvidia,pull = <1>;
+				nvidia,tristate = <1>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <0>;
+			};
+			conf_ddc {
+				nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
+					"lvp0", "pmc";
+				nvidia,tristate = <1>;
+			};
+			conf_irrx {
+				nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
+					"kbcc", "kbcd", "kbce", "kbcf", "owc",
+					"spic", "spie", "spig", "spih", "uaa",
+					"uab", "uad", "uca", "ucb";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <2>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+					"lvs", "sdb";
+				nvidia,tristate = <0>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <1>;
+			};
+		};
+	};
+
 	i2c at 7000c000 {
 		clock-frequency = <400000>;
 	};
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 2dcff87..71eb2e5 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -10,6 +10,236 @@
 		reg = < 0x00000000 0x40000000 >;
 	};
 
+	pinmux at 70000000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			ata {
+				nvidia,pins = "ata";
+				nvidia,function = "ide";
+			};
+			atb {
+				nvidia,pins = "atb", "gma", "gme";
+				nvidia,function = "sdio4";
+			};
+			atc {
+				nvidia,pins = "atc";
+				nvidia,function = "nand";
+			};
+			atd {
+				nvidia,pins = "atd", "ate", "gmb", "spia",
+					"spib", "spic";
+				nvidia,function = "gmi";
+			};
+			cdev1 {
+				nvidia,pins = "cdev1";
+				nvidia,function = "plla_out";
+			};
+			cdev2 {
+				nvidia,pins = "cdev2";
+				nvidia,function = "pllp_out4";
+			};
+			crtp {
+				nvidia,pins = "crtp", "lm1";
+				nvidia,function = "crt";
+			};
+			csus {
+				nvidia,pins = "csus";
+				nvidia,function = "vi_sensor_clk";
+			};
+			dap1 {
+				nvidia,pins = "dap1";
+				nvidia,function = "dap1";
+			};
+			dap2 {
+				nvidia,pins = "dap2";
+				nvidia,function = "dap2";
+			};
+			dap3 {
+				nvidia,pins = "dap3";
+				nvidia,function = "dap3";
+			};
+			dap4 {
+				nvidia,pins = "dap4";
+				nvidia,function = "dap4";
+			};
+			ddc {
+				nvidia,pins = "ddc", "owc", "spdi", "spdo",
+					"uac";
+				nvidia,function = "rsvd2";
+			};
+			dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+				nvidia,function = "vi";
+			};
+			dtf {
+				nvidia,pins = "dtf";
+				nvidia,function = "i2c3";
+			};
+			gmc {
+				nvidia,pins = "gmc";
+				nvidia,function = "uartd";
+			};
+			gmd {
+				nvidia,pins = "gmd";
+				nvidia,function = "sflash";
+			};
+			gpu {
+				nvidia,pins = "gpu";
+				nvidia,function = "pwm";
+			};
+			gpu7 {
+				nvidia,pins = "gpu7";
+				nvidia,function = "rtck";
+			};
+			gpv {
+				nvidia,pins = "gpv", "slxa", "slxk";
+				nvidia,function = "pcie";
+			};
+			hdint {
+				nvidia,pins = "hdint", "pta";
+				nvidia,function = "hdmi";
+			};
+			i2cp {
+				nvidia,pins = "i2cp";
+				nvidia,function = "i2cp";
+			};
+			irrx {
+				nvidia,pins = "irrx", "irtx";
+				nvidia,function = "uartb";
+			};
+			kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf";
+				nvidia,function = "kbc";
+			};
+			lcsn {
+				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+					"lsdi", "lvp0";
+				nvidia,function = "rsvd4";
+			};
+			ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lpp", "lpw0",
+					"lpw2", "lsc0", "lsc1", "lsck", "lsda",
+					"lspi", "lvp1", "lvs";
+				nvidia,function = "displaya";
+			};
+			pmc {
+				nvidia,pins = "pmc";
+				nvidia,function = "pwr_on";
+			};
+			rm {
+				nvidia,pins = "rm";
+				nvidia,function = "i2c1";
+			};
+			sdb {
+				nvidia,pins = "sdb", "sdc", "sdd", "slxc";
+				nvidia,function = "sdio3";
+			};
+			sdio1 {
+				nvidia,pins = "sdio1";
+				nvidia,function = "sdio1";
+			};
+			slxd {
+				nvidia,pins = "slxd";
+				nvidia,function = "spdif";
+			};
+			spid {
+				nvidia,pins = "spid", "spie", "spif";
+				nvidia,function = "spi1";
+			};
+			spig {
+				nvidia,pins = "spig", "spih";
+				nvidia,function = "spi2_alt";
+			};
+			uaa {
+				nvidia,pins = "uaa", "uab", "uda";
+				nvidia,function = "ulpi";
+			};
+			uad {
+				nvidia,pins = "uad";
+				nvidia,function = "irda";
+			};
+			uca {
+				nvidia,pins = "uca", "ucb";
+				nvidia,function = "uartc";
+			};
+			conf_ata {
+				nvidia,pins = "ata", "atb", "atc", "atd",
+					"cdev1", "cdev2", "dap1", "dap2",
+					"dap4", "ddc", "dtf", "gma", "gmc",
+					"gme", "gpu", "gpu7", "i2cp", "irrx",
+					"irtx", "pta", "rm", "sdc", "sdd",
+					"slxc", "slxd", "slxk", "spdi", "spdo",
+					"uac", "uad", "uca", "ucb", "uda";
+				nvidia,pull = <0>;
+				nvidia,tristate = <0>;
+			};
+			conf_ate {
+				nvidia,pins = "ate", "csus", "dap3", "gmd",
+					"gpv", "owc", "spia", "spib", "spic",
+					"spid", "spie", "spig";
+				nvidia,pull = <0>;
+				nvidia,tristate = <1>;
+			};
+			conf_ck32 {
+				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+				nvidia,pull = <0>;
+			};
+			conf_crtp {
+				nvidia,pins = "crtp", "gmb", "slxa", "spih";
+				nvidia,pull = <2>;
+				nvidia,tristate = <1>;
+			};
+			conf_dta {
+				nvidia,pins = "dta", "dtb", "dtc", "dtd";
+				nvidia,pull = <1>;
+				nvidia,tristate = <0>;
+			};
+			conf_dte {
+				nvidia,pins = "dte", "spif";
+				nvidia,pull = <1>;
+				nvidia,tristate = <1>;
+			};
+			conf_hdint {
+				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+					"lpw1", "lsck", "lsda", "lsdi", "lvp0";
+				nvidia,tristate = <1>;
+			};
+			conf_kbca {
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+					"kbce", "kbcf", "sdio1", "uaa", "uab";
+				nvidia,pull = <2>;
+				nvidia,tristate = <0>;
+			};
+			conf_lc {
+				nvidia,pins = "lc", "ls";
+				nvidia,pull = <2>;
+			};
+			conf_ld0 {
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+					"ld5", "ld6", "ld7", "ld8", "ld9",
+					"ld10", "ld11", "ld12", "ld13", "ld14",
+					"ld15", "ld16", "ld17", "ldi", "lhp0",
+					"lhp1", "lhp2", "lhs", "lm0", "lpp",
+					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
+					"lvp1", "lvs", "pmc", "sdb";
+				nvidia,tristate = <0>;
+			};
+			conf_ld17_0 {
+				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+					"ld23_22";
+				nvidia,pull = <1>;
+			};
+		};
+	};
+
 	i2c at 7000c000 {
 		clock-frequency = <400000>;
 
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 65a5249..5b9d5f4 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -47,14 +47,7 @@
 #include "clock.h"
 #include "devices.h"
 
-void harmony_pinmux_init(void);
-void paz00_pinmux_init(void);
-void seaboard_pinmux_init(void);
-void trimslice_pinmux_init(void);
-void ventana_pinmux_init(void);
-
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
-	OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
@@ -94,33 +87,10 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
 	{}
 };
 
-static struct {
-	char *machine;
-	void (*init)(void);
-} pinmux_configs[] = {
-	{ "compulab,trimslice", trimslice_pinmux_init },
-	{ "nvidia,harmony", harmony_pinmux_init },
-	{ "compal,paz00", paz00_pinmux_init },
-	{ "nvidia,seaboard", seaboard_pinmux_init },
-	{ "nvidia,ventana", ventana_pinmux_init },
-};
-
 static void __init tegra_dt_init(void)
 {
-	int i;
-
 	tegra_clk_init_from_table(tegra_dt_clk_init_table);
 
-	for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
-		if (of_machine_is_compatible(pinmux_configs[i].machine)) {
-			pinmux_configs[i].init();
-			break;
-		}
-	}
-
-	WARN(i == ARRAY_SIZE(pinmux_configs),
-		"Unknown platform! Pinmuxing not initialized\n");
-
 	/*
 	 * Finished with the static registrations now; fill in the missing
 	 * devices
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
index 3b7ad07..a5574c7 100644
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -15,7 +15,6 @@
 #include <linux/device.h>
 #include <linux/kernel.h>
 #include <linux/notifier.h>
-#include <linux/of.h>
 #include <linux/string.h>
 
 #include "board-pinmux.h"
@@ -84,6 +83,5 @@ void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
 	if (conf_b)
 		pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
 
-	if (!of_machine_is_compatible("nvidia,tegra20"))
-		platform_add_devices(devices, ARRAY_SIZE(devices));
+	platform_add_devices(devices, ARRAY_SIZE(devices));
 }
-- 
1.7.0.4



From olof at lixom.net  Fri Mar 30 19:20:25 2012
From: olof at lixom.net (Olof Johansson)
Date: Fri, 30 Mar 2012 16:20:25 -0700
Subject: [GIT PULL] ARM: Two more fixes for merge window fallout
Message-ID: <CAOesGMjU5tehTf7+nYQv1_7a=+gGN2hVYUdh1g_BF=WRYj0hgg@mail.gmail.com>

Linus,

Apologies for back-to-back fixes pull requests, but one of the patches
below are the kind we'll see posted over and over if we don't send it
in. I hadn't done the full sanity-check of defconfig builds by the
time I sent up the other fixes yesterday or I would have included it
then.

After this we're likely to switch to a more regular frequency of
sending fixes up.



Thanks,

-Olof



The following changes since commit f00e9b11863abdb837e555a2b1e3417e8b5d80dd:

  Merge branch 'fixes' of git://github.com/hzhuang1/linux into fixes
(2012-03-29 20:36:18 -0700)

are available in the git repository at:


  git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git fixes

for you to fetch changes up to d3c7de52096a201ac188adb95b8351b90cab11f1:

  ARM: clps711x: fix missing include file (2012-03-30 15:44:48 -0700)

----------------------------------------------------------------
ARM: A few more platform fixes for include file fallout

Two patches, one dealing with the system.h fallout, the other is a missing
linux/bug.h in a place where ARRAY_SIZE() is used.

----------------------------------------------------------------
Olof Johansson (2):
      ARM: fix builds due to missing <asm/system_misc.h> includes
      ARM: clps711x: fix missing include file

 arch/arm/mach-at91/at91x40.c        |    1 +
 arch/arm/mach-at91/setup.c          |    1 +
 arch/arm/mach-clps711x/edb7211-mm.c |    1 +
 arch/arm/mach-h720x/common.c        |    1 +
 arch/arm/mach-imx/mm-imx3.c         |    1 +
 arch/arm/mach-imx/mm-imx5.c         |    1 +
 arch/arm/mach-ixp23xx/core.c        |    1 +
 arch/arm/mach-ixp4xx/common.c       |    1 +
 arch/arm/mach-pxa/raumfeld.c        |    2 ++
 arch/arm/mach-shark/core.c          |    1 +
 arch/arm/mach-w90x900/dev.c         |    1 +
 arch/arm/plat-s3c24xx/cpu.c         |    1 +
 12 files changed, 13 insertions(+)


From jason at lakedaemon.net  Fri Mar 30 19:24:19 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 30 Mar 2012 19:24:19 -0400
Subject: Support for Iomega iConnect
In-Reply-To: <201203302330.49834.linux@baker-net.org.uk>
References: <201203302330.49834.linux@baker-net.org.uk>
Message-ID: <20120330232419.GF7274@titan.lakedaemon.net>

On Fri, Mar 30, 2012 at 11:30:49PM +0100, Adam Baker wrote:
> Hi,

Hi Adam,

> Is anyone aware of any technical reason why support for the Iomega iConnect is 
> not included in the mainline kernel (e.g. there are significant changes 
> happening in the area of the Kirkwood CPUs that mean now isn't a good time to 
> include it).

No one ushered it in.  Patches are always welcome.

> There are several versions floating around the internet but as far 
> as I can see the only mention of the iConnect on this list is Russell saying 
> he will remove it from mach types soon as there is no mainline support for it.

mach-type is no longer needed, once conversion to devicetree is done.
Converting you patches to devicetree should be pretty easy.  See my
recommendation, below.

> Based upon work that Iomega posted to the open source code area on their web 
> site and code that was submitted to OpenWRT with a sign off line from Wojciech 
> Dubowik, I have patched support into the 3.2.11 kernel. If there is no 
> objection in principle to inclusion then I will rebase the patch and submit 
> it.

Please base off of v3.3 and merge in the following branch:

git://git.infradead.org/users/jcooper/linux-kirkwood.git kirkwood_dt_for_3.4_v3

This has been merged into Linus' tree, but it's after v3.3.

You can also look at the history in this branch to see how support for
dreamplug (also kirkwood SoC) was added.  Converting drivers to
devicetree is still a work in progress, so, just match what dreamplug is
doing.

Post the resulting patches to the ml, and I'll queue it up with the others
(after sufficient review, of course).

> Is Linus' git repository still the preferred baseline for linux-arm patches?

Yes, always base off of a tag as I mentioned above.

Just shout if you have any questions.

hth,

Jason.



From oskar.andero at gmail.com  Fri Mar 30 19:37:37 2012
From: oskar.andero at gmail.com (Oskar Andero)
Date: Sat, 31 Mar 2012 01:37:37 +0200
Subject: [PATCH] ARM: versatile: fix broken build in pci.c
Message-ID: <1333150657-6534-1-git-send-email-oskar.andero@gmail.com>

An undefined reference to sys was introduced by 9f786d03.

Signed-off-by: Oskar Andero <oskar.andero at gmail.com>
---
 arch/arm/mach-versatile/pci.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index a6e23f4..e4447dd 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -190,8 +190,9 @@ static struct resource pre_mem = {
 	.flags	= IORESOURCE_MEM | IORESOURCE_PREFETCH,
 };
 
-static int __init pci_versatile_setup_resources(struct list_head *resources)
+static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
 {
+	struct list_head *resources = &sys->resources;
 	int ret = 0;
 
 	ret = request_resource(&iomem_resource, &io_mem);
@@ -249,7 +250,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 
 	if (nr == 0) {
 		sys->mem_offset = 0;
-		ret = pci_versatile_setup_resources(&sys->resources);
+		ret = pci_versatile_setup_resources(sys);
 		if (ret < 0) {
 			printk("pci_versatile_setup: resources... oops?\n");
 			goto out;
-- 
1.7.3.4



From torvalds at linux-foundation.org  Fri Mar 30 20:00:21 2012
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Fri, 30 Mar 2012 17:00:21 -0700
Subject: [GIT PULL] ARM: Two more fixes for merge window fallout
In-Reply-To: <CAOesGMjU5tehTf7+nYQv1_7a=+gGN2hVYUdh1g_BF=WRYj0hgg@mail.gmail.com>
References: <CAOesGMjU5tehTf7+nYQv1_7a=+gGN2hVYUdh1g_BF=WRYj0hgg@mail.gmail.com>
Message-ID: <CA+55aFzeN+m0mWqe6ajBB=cdTNJMF2FgW17_mm_n0BoKokQVRw@mail.gmail.com>

On Fri, Mar 30, 2012 at 4:20 PM, Olof Johansson <olof at lixom.net> wrote:
>
> are available in the git repository at:
>
> ?git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git fixes

Hmm. I *think* you meant to ask me to pull the "fixes-for-linus" tag,
which points at the same commit as the "fixes" branch. No?

You might want to double-check whatever script or workflow you use to
generate these pull requests.

               Linus


From grant.likely at secretlab.ca  Fri Mar 30 18:09:29 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 30 Mar 2012 16:09:29 -0600
Subject: [PATCH v4 2/2] regulator: add device tree support for max8997
In-Reply-To: <1332582590-16382-3-git-send-email-thomas.abraham@linaro.org>
References: <1332582590-16382-1-git-send-email-thomas.abraham@linaro.org>
 <1332582590-16382-3-git-send-email-thomas.abraham@linaro.org>
Message-ID: <20120330220929.6F0B93E0602@localhost>

On Sat, 24 Mar 2012 15:19:50 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> Add device tree based discovery support for max8997.
> 
> Cc: MyungJoo Ham <myungjoo.ham at samsung.com>
> Cc: Rajendra Nayak <rnayak at ti.com>
> Cc: Rob Herring <rob.herring at calxeda.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> ---
>  .../devicetree/bindings/regulator/max8997-pmic.txt |  133 ++++++++++++++++++
>  drivers/mfd/max8997.c                              |   73 ++++++++++-
>  drivers/regulator/max8997.c                        |  143 +++++++++++++++++++-
>  include/linux/mfd/max8997-private.h                |    1 +
>  include/linux/mfd/max8997.h                        |    1 +
>  5 files changed, 347 insertions(+), 4 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/regulator/max8997-pmic.txt
> 
> diff --git a/Documentation/devicetree/bindings/regulator/max8997-pmic.txt b/Documentation/devicetree/bindings/regulator/max8997-pmic.txt
> new file mode 100644
> index 0000000..90a730b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/regulator/max8997-pmic.txt
> @@ -0,0 +1,133 @@
> +* Maxim MAX8997 Voltage and Current Regulator
> +
> +The Maxim MAX8997 is a multi-function device which includes volatage and
> +current regulators, rtc, charger controller and other sub-blocks. It is
> +interfaced to the host controller using a i2c interface. Each sub-block is
> +addressed by the host system using different i2c slave address. This document
> +describes the bindings for 'pmic' sub-block of max8997.
> +
> +Required properties:
> +- compatible: Should be "maxim,max8997-pmic".
> +- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
> +
> +- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
> +  units for buck1 when changing voltage using gpio dvs. Refer to [1] below
> +  for additional information.
> +
> +- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
> +  units for buck2 when changing voltage using gpio dvs. Refer to [1] below
> +  for additional information.
> +
> +- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
> +  units for buck5 when changing voltage using gpio dvs. Refer to [1] below
> +  for additional information.

These are *really long* property names.  Anything over 32 characters
seems excessive to me.

Other than that the binding looks good.

g.



From grant.likely at secretlab.ca  Fri Mar 30 18:06:19 2012
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 30 Mar 2012 16:06:19 -0600
Subject: [PATCH v4 1/2] mfd: add irq domain support for max8997 interrupts
In-Reply-To: <1332582590-16382-2-git-send-email-thomas.abraham@linaro.org>
References: <1332582590-16382-1-git-send-email-thomas.abraham@linaro.org>
 <1332582590-16382-2-git-send-email-thomas.abraham@linaro.org>
Message-ID: <20120330220619.334AC3E054E@localhost>

On Sat, 24 Mar 2012 15:19:49 +0530, Thomas Abraham <thomas.abraham at linaro.org> wrote:
> Add irq domain support for max8997 interrupts. The reverse mapping method
> used is linear mapping since the sub-drivers of max8997 such as regulator
> and charger drivers can use the max8997 irq_domain to get the linux irq
> number for max8997 interrupts. All uses of irq_base in platform data and
> max8997 driver private data are removed.
> 
> Cc: MyungJoo Ham <myungjoo.ham at samsung.com>
> Signed-off-by: Thomas Abraham <thomas.abraham at linaro.org>
> Acked-by: Grant Likely <grant.likely at secretlab.ca>
> ---
>  arch/arm/mach-exynos/mach-nuri.c    |    4 --
>  arch/arm/mach-exynos/mach-origen.c  |    1 -
>  drivers/mfd/max8997-irq.c           |   61 ++++++++++++++++++++--------------
>  drivers/mfd/max8997.c               |    1 -
>  include/linux/mfd/max8997-private.h |    4 ++-
>  include/linux/mfd/max8997.h         |    1 -
>  6 files changed, 39 insertions(+), 33 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
> index 7ac81ce..b21d85d 100644
> --- a/arch/arm/mach-exynos/mach-nuri.c
> +++ b/arch/arm/mach-exynos/mach-nuri.c
> @@ -1077,12 +1077,8 @@ static struct platform_device nuri_max8903_device = {
>  static void __init nuri_power_init(void)
>  {
>  	int gpio;
> -	int irq_base = IRQ_GPIO_END + 1;
>  	int ta_en = 0;
>  
> -	nuri_max8997_pdata.irq_base = irq_base;
> -	irq_base += MAX8997_IRQ_NR;
> -
>  	gpio = EXYNOS4_GPX0(7);
>  	gpio_request(gpio, "AP_PMIC_IRQ");
>  	s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
> diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
> index 827cb99..d3b2e9d 100644
> --- a/arch/arm/mach-exynos/mach-origen.c
> +++ b/arch/arm/mach-exynos/mach-origen.c
> @@ -424,7 +424,6 @@ static struct max8997_platform_data __initdata origen_max8997_pdata = {
>  	.buck1_gpiodvs	= false,
>  	.buck2_gpiodvs	= false,
>  	.buck5_gpiodvs	= false,
> -	.irq_base	= IRQ_GPIO_END + 1,
>  
>  	.ignore_gpiodvs_side_effect = true,
>  	.buck125_default_idx = 0x0,
> diff --git a/drivers/mfd/max8997-irq.c b/drivers/mfd/max8997-irq.c
> index 09274cf..00390a1 100644
> --- a/drivers/mfd/max8997-irq.c
> +++ b/drivers/mfd/max8997-irq.c
> @@ -142,7 +142,8 @@ static void max8997_irq_sync_unlock(struct irq_data *data)
>  static const inline struct max8997_irq_data *
>  irq_to_max8997_irq(struct max8997_dev *max8997, int irq)
>  {
> -	return &max8997_irqs[irq - max8997->irq_base];
> +	struct irq_data *data = irq_get_irq_data(irq);
> +	return &max8997_irqs[data->hwirq];
>  }

Haha, this is kind of bogus now.  There are only two users of this
function, and *both* of them already have the irq_data pointer.
Instead of this, delete this function entirely and make each caller
derefernce max8997_irqs directly:

	const struct max8997_irq_data *irq_data = &max8997_irqs[data->hwirq];

Otherwise, looks good.  After fixing you can add my:

Acked-by: Grant Likely <grant.likely at secretlab.ca>

>  
>  static void max8997_irq_mask(struct irq_data *data)
> @@ -182,7 +183,7 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
>  	u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {};
>  	u8 irq_src;
>  	int ret;
> -	int i;
> +	int i, cur_irq;
>  
>  	ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src);
>  	if (ret < 0) {
> @@ -269,8 +270,11 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
>  
>  	/* Report */
>  	for (i = 0; i < MAX8997_IRQ_NR; i++) {
> -		if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask)
> -			handle_nested_irq(max8997->irq_base + i);
> +		if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) {
> +			cur_irq = irq_find_mapping(max8997->irq_domain, i);
> +			if (cur_irq)
> +				handle_nested_irq(cur_irq);
> +		}
>  	}
>  
>  	return IRQ_HANDLED;
> @@ -278,26 +282,40 @@ static irqreturn_t max8997_irq_thread(int irq, void *data)
>  
>  int max8997_irq_resume(struct max8997_dev *max8997)
>  {
> -	if (max8997->irq && max8997->irq_base)
> -		max8997_irq_thread(max8997->irq_base, max8997);
> +	if (max8997->irq && max8997->irq_domain)
> +		max8997_irq_thread(0, max8997);
> +	return 0;
> +}
> +
> +static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
> +					irq_hw_number_t hw)
> +{
> +	struct max8997_dev *max8997 = d->host_data;
> +
> +	irq_set_chip_data(irq, max8997);
> +	irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
> +	irq_set_nested_thread(irq, 1);
> +#ifdef CONFIG_ARM
> +	set_irq_flags(irq, IRQF_VALID);
> +#else
> +	irq_set_noprobe(irq);
> +#endif
>  	return 0;
>  }
>  
> +static struct irq_domain_ops max8997_irq_domain_ops = {
> +	.map = max8997_irq_domain_map,
> +};
> +
>  int max8997_irq_init(struct max8997_dev *max8997)
>  {
> +	struct irq_domain *domain;
>  	int i;
> -	int cur_irq;
>  	int ret;
>  	u8 val;
>  
>  	if (!max8997->irq) {
>  		dev_warn(max8997->dev, "No interrupt specified.\n");
> -		max8997->irq_base = 0;
> -		return 0;
> -	}
> -
> -	if (!max8997->irq_base) {
> -		dev_err(max8997->dev, "No interrupt base specified.\n");
>  		return 0;
>  	}
>  
> @@ -327,18 +345,11 @@ int max8997_irq_init(struct max8997_dev *max8997)
>  					true : false;
>  	}
>  
> -	/* Register with genirq */
> -	for (i = 0; i < MAX8997_IRQ_NR; i++) {
> -		cur_irq = i + max8997->irq_base;
> -		irq_set_chip_data(cur_irq, max8997);
> -		irq_set_chip_and_handler(cur_irq, &max8997_irq_chip,
> -				handle_edge_irq);
> -		irq_set_nested_thread(cur_irq, 1);
> -#ifdef CONFIG_ARM
> -		set_irq_flags(cur_irq, IRQF_VALID);
> -#else
> -		irq_set_noprobe(cur_irq);
> -#endif
> +	domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR,
> +					&max8997_irq_domain_ops, &max8997);
> +	if (!domain) {
> +		dev_err(max8997->dev, "could not create irq domain\n");
> +		return -ENODEV;
>  	}
>  
>  	ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread,
> diff --git a/drivers/mfd/max8997.c b/drivers/mfd/max8997.c
> index cb83a7a..20ecad3 100644
> --- a/drivers/mfd/max8997.c
> +++ b/drivers/mfd/max8997.c
> @@ -143,7 +143,6 @@ static int max8997_i2c_probe(struct i2c_client *i2c,
>  	if (!pdata)
>  		goto err;
>  
> -	max8997->irq_base = pdata->irq_base;
>  	max8997->ono = pdata->ono;
>  
>  	mutex_init(&max8997->iolock);
> diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
> index 3f4deb6..830152c 100644
> --- a/include/linux/mfd/max8997-private.h
> +++ b/include/linux/mfd/max8997-private.h
> @@ -23,6 +23,8 @@
>  #define __LINUX_MFD_MAX8997_PRIV_H
>  
>  #include <linux/i2c.h>
> +#include <linux/export.h>
> +#include <linux/irqdomain.h>
>  
>  #define MAX8997_REG_INVALID	(0xff)
>  
> @@ -325,7 +327,7 @@ struct max8997_dev {
>  
>  	int irq;
>  	int ono;
> -	int irq_base;
> +	struct irq_domain *irq_domain;
>  	struct mutex irqlock;
>  	int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
>  	int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
> diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
> index fff5905..818486c 100644
> --- a/include/linux/mfd/max8997.h
> +++ b/include/linux/mfd/max8997.h
> @@ -155,7 +155,6 @@ struct max8997_led_platform_data {
>  
>  struct max8997_platform_data {
>  	/* IRQ */
> -	int irq_base;
>  	int ono;
>  	int wakeup;
>  
> -- 
> 1.6.6.rc2
> 

-- 
Grant Likely, B.Sc, P.Eng.
Secret Lab Technologies,Ltd.


From olof at lixom.net  Fri Mar 30 21:18:40 2012
From: olof at lixom.net (Olof Johansson)
Date: Fri, 30 Mar 2012 18:18:40 -0700
Subject: [GIT PULL] ARM: Two more fixes for merge window fallout
In-Reply-To: <CA+55aFzeN+m0mWqe6ajBB=cdTNJMF2FgW17_mm_n0BoKokQVRw@mail.gmail.com>
References: <CAOesGMjU5tehTf7+nYQv1_7a=+gGN2hVYUdh1g_BF=WRYj0hgg@mail.gmail.com>
 <CA+55aFzeN+m0mWqe6ajBB=cdTNJMF2FgW17_mm_n0BoKokQVRw@mail.gmail.com>
Message-ID: <CAOesGMhrokqQajQ6RROXdWNvVUd3WNjO4i3qggGAVXo5h05TKQ@mail.gmail.com>

On Fri, Mar 30, 2012 at 5:00 PM, Linus Torvalds
<torvalds at linux-foundation.org> wrote:
> On Fri, Mar 30, 2012 at 4:20 PM, Olof Johansson <olof at lixom.net> wrote:
>>
>> are available in the git repository at:
>>
>> ?git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git fixes
>
> Hmm. I *think* you meant to ask me to pull the "fixes-for-linus" tag,
> which points at the same commit as the "fixes" branch. No?

Yes, that's correct.

> You might want to double-check whatever script or workflow you use to
> generate these pull requests.

Hmm, I had 'fixes' checked out locally, and used regular git request-pull.

Oh! I know what it was. I pushed the branch before I pushed the tag,
so when I generated the request the branch had propagated out from ra
to git.kernel.org but not the tag.

Since the branch matched but no tag did, request-pull used it and took
the local tag contents for the message so I didn't notice the
difference.

Thanks for the sanity check, I'll double-check in the future.


-Olof


From mcuos.com at gmail.com  Fri Mar 30 21:24:06 2012
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Sat, 31 Mar 2012 09:24:06 +0800
Subject: [PATCH 1/2] ARM: fix builds due to missing <asm/system_misc.h>
 includes
In-Reply-To: <1333118281-25295-1-git-send-email-olof@lixom.net>
References: <1333118281-25295-1-git-send-email-olof@lixom.net>
Message-ID: <CAKT61h9bwKdJ0WuCJJ3Avs89xeZdj_XTfKnvFMVQStF=jmLEEA@mail.gmail.com>

2012/3/30 Olof Johansson <olof at lixom.net>:
> This does a sweeping change fixing up all the missing system_misc.h and
> system_info.h includes from the system.h split-up change. These were the
> ones I came across when building all defconfigs in arch/arm/configs, there
> might be more but they lack adequate build coverage to be easily caught.
>
> I'm expecting to get a lot of these piecemeal by each maintainer, so we
> might just as well do one sweeping change to get them all at once.
>
For Winbond/Nuvoton w90x900 platform,
Acked-by: Wan ZongShun <mcuos.com at gmail.com>

>
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Sascha Hauer <kernel at pengutronix.de>
> Cc: Imre Kaloz <kaloz at openwrt.org>
> Cc: Krzysztof Halasa <khc at pm.waw.pl>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Wan ZongShun <mcuos.com at gmail.com>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Signed-off-by: Olof Johansson <olof at lixom.net>
> ---
> ?arch/arm/mach-at91/at91x40.c ?| ? ?1 +
> ?arch/arm/mach-at91/setup.c ? ?| ? ?1 +
> ?arch/arm/mach-h720x/common.c ?| ? ?1 +
> ?arch/arm/mach-imx/mm-imx3.c ? | ? ?1 +
> ?arch/arm/mach-imx/mm-imx5.c ? | ? ?1 +
> ?arch/arm/mach-ixp23xx/core.c ?| ? ?1 +
> ?arch/arm/mach-ixp4xx/common.c | ? ?1 +
> ?arch/arm/mach-pxa/raumfeld.c ?| ? ?2 ++
> ?arch/arm/mach-shark/core.c ? ?| ? ?1 +
> ?arch/arm/mach-w90x900/dev.c ? | ? ?1 +
> ?arch/arm/plat-s3c24xx/cpu.c ? | ? ?1 +
> ?11 files changed, 12 insertions(+)
>
> diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
> index 5400a1d..d62fe09 100644
> --- a/arch/arm/mach-at91/at91x40.c
> +++ b/arch/arm/mach-at91/at91x40.c
> @@ -14,6 +14,7 @@
> ?#include <linux/init.h>
> ?#include <linux/irq.h>
> ?#include <asm/proc-fns.h>
> +#include <asm/system_misc.h>
> ?#include <asm/mach/arch.h>
> ?#include <mach/at91x40.h>
> ?#include <mach/at91_st.h>
> diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
> index 1083739..97cc04d 100644
> --- a/arch/arm/mach-at91/setup.c
> +++ b/arch/arm/mach-at91/setup.c
> @@ -11,6 +11,7 @@
> ?#include <linux/pm.h>
> ?#include <linux/of_address.h>
>
> +#include <asm/system_misc.h>
> ?#include <asm/mach/map.h>
>
> ?#include <mach/hardware.h>
> diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
> index e756d1a..aa1331e 100644
> --- a/arch/arm/mach-h720x/common.c
> +++ b/arch/arm/mach-h720x/common.c
> @@ -24,6 +24,7 @@
> ?#include <asm/dma.h>
> ?#include <mach/hardware.h>
> ?#include <asm/irq.h>
> +#include <asm/system_misc.h>
> ?#include <asm/mach/irq.h>
> ?#include <asm/mach/map.h>
> ?#include <mach/irqs.h>
> diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
> index d534d7f..7412738 100644
> --- a/arch/arm/mach-imx/mm-imx3.c
> +++ b/arch/arm/mach-imx/mm-imx3.c
> @@ -21,6 +21,7 @@
> ?#include <linux/err.h>
>
> ?#include <asm/pgtable.h>
> +#include <asm/system_misc.h>
> ?#include <asm/hardware/cache-l2x0.h>
> ?#include <asm/mach/map.h>
>
> diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
> index 51af9fa..05250ae 100644
> --- a/arch/arm/mach-imx/mm-imx5.c
> +++ b/arch/arm/mach-imx/mm-imx5.c
> @@ -15,6 +15,7 @@
> ?#include <linux/init.h>
> ?#include <linux/clk.h>
>
> +#include <asm/system_misc.h>
> ?#include <asm/mach/map.h>
>
> ?#include <mach/hardware.h>
> diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
> index d2c2dc3..d345424 100644
> --- a/arch/arm/mach-ixp23xx/core.c
> +++ b/arch/arm/mach-ixp23xx/core.c
> @@ -36,6 +36,7 @@
> ?#include <asm/irq.h>
> ?#include <asm/tlbflush.h>
> ?#include <asm/pgtable.h>
> +#include <asm/system_misc.h>
>
> ?#include <asm/mach/map.h>
> ?#include <asm/mach/time.h>
> diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
> index c60e7b8..ebbd7fc 100644
> --- a/arch/arm/mach-ixp4xx/common.c
> +++ b/arch/arm/mach-ixp4xx/common.c
> @@ -37,6 +37,7 @@
> ?#include <asm/page.h>
> ?#include <asm/irq.h>
> ?#include <asm/sched_clock.h>
> +#include <asm/system_misc.h>
>
> ?#include <asm/mach/map.h>
> ?#include <asm/mach/irq.h>
> diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
> index 7d691e5..5905ed1 100644
> --- a/arch/arm/mach-pxa/raumfeld.c
> +++ b/arch/arm/mach-pxa/raumfeld.c
> @@ -43,6 +43,8 @@
> ?#include <linux/regulator/consumer.h>
> ?#include <linux/delay.h>
>
> +#include <asm/system_info.h>
> +
> ?#include <asm/mach-types.h>
> ?#include <asm/mach/arch.h>
>
> diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
> index 6a2a7f2..2704bcd 100644
> --- a/arch/arm/mach-shark/core.c
> +++ b/arch/arm/mach-shark/core.c
> @@ -15,6 +15,7 @@
> ?#include <asm/mach-types.h>
> ?#include <asm/leds.h>
> ?#include <asm/param.h>
> +#include <asm/system_misc.h>
>
> ?#include <asm/mach/map.h>
> ?#include <asm/mach/arch.h>
> diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
> index db82568..48f5b9f 100644
> --- a/arch/arm/mach-w90x900/dev.c
> +++ b/arch/arm/mach-w90x900/dev.c
> @@ -27,6 +27,7 @@
> ?#include <linux/spi/spi.h>
> ?#include <linux/spi/flash.h>
>
> +#include <asm/system_misc.h>
> ?#include <asm/mach/arch.h>
> ?#include <asm/mach/map.h>
> ?#include <asm/mach/irq.h>
> diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
> index 0db73ae..290942d 100644
> --- a/arch/arm/plat-s3c24xx/cpu.c
> +++ b/arch/arm/plat-s3c24xx/cpu.c
> @@ -36,6 +36,7 @@
> ?#include <asm/irq.h>
> ?#include <asm/cacheflush.h>
> ?#include <asm/system_info.h>
> +#include <asm/system_misc.h>
>
> ?#include <asm/mach/arch.h>
> ?#include <asm/mach/map.h>
> --
> 1.7.9.2.359.gebfc2
>



-- 
Wan ZongShun.
www.mcuos.com


From jason at lakedaemon.net  Fri Mar 30 21:30:06 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Fri, 30 Mar 2012 21:30:06 -0400
Subject: [PATCH V3 1/5] ARM: kirkwood: Basic support for DNS-320 and
 DNS-325
In-Reply-To: <1332885255-8304-2-git-send-email-jm@lentin.co.uk>
References: <1332885255-8304-1-git-send-email-jm@lentin.co.uk>
 <1332885255-8304-2-git-send-email-jm@lentin.co.uk>
Message-ID: <20120331013006.GH7274@titan.lakedaemon.net>

On Tue, Mar 27, 2012 at 10:54:11PM +0100, Jamie Lentin wrote:
> Add support for the DNS-320 and DNS-325. Describe as much as currently possible
> in the devicetree files, create a board-dnskw.c for everything else.
> 
> Use IEEE-compliant "okay", rather than "ok"
> 
> Acked-by: Arnd Bergmann <arnd at arndb.de>
> Acked-by: Jason Cooper <jason at lakedaemon.net>
> Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
> ---
>  arch/arm/boot/dts/kirkwood-dns320.dts |   29 +++
>  arch/arm/boot/dts/kirkwood-dns325.dts |   24 +++
>  arch/arm/mach-kirkwood/Kconfig        |   23 +++
>  arch/arm/mach-kirkwood/Makefile       |    1 +
>  arch/arm/mach-kirkwood/Makefile.boot  |    2 +
>  arch/arm/mach-kirkwood/board-dnskw.c  |  306 +++++++++++++++++++++++++++++++++
>  arch/arm/mach-kirkwood/board-dt.c     |    5 +
>  arch/arm/mach-kirkwood/common.h       |    6 +
>  8 files changed, 396 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/boot/dts/kirkwood-dns320.dts
>  create mode 100644 arch/arm/boot/dts/kirkwood-dns325.dts
>  create mode 100644 arch/arm/mach-kirkwood/board-dnskw.c

Jamie,

I've applied this locally, thanks.  Looks like Grant took #5 through his
tree.  As #3 and #4 depend on #2, I'll wait for the next version of #2
incorporating Grant's comments before I apply #2-#4.

thx,

Jason.


From tom.leiming at gmail.com  Fri Mar 30 21:30:31 2012
From: tom.leiming at gmail.com (Ming Lei)
Date: Sat, 31 Mar 2012 09:30:31 +0800
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
 <4F7570FC.8000907@ti.com>
 <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>
 <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>
Message-ID: <CACVXFVPbU2OqTN=S0AZCD10KuSBYxqyyRH_xee+WTaCD6VSmMQ@mail.gmail.com>

On Fri, Mar 30, 2012 at 5:20 PM, Shilimkar, Santosh <santosh.shilimkar at ti.com>
>
>> After Ming Lie's comment, the point that I came to my mind was,
>> certainly there will be resolution difference between these two clocksources,
>> if ?gptimer2 is sourced from sys_ck (26Mhz).
>>
> GPTIMER2 with sysclock is not an option. GPTIMER is not in wakeup domain
> and when sysclock is cut, it stops.

If neither CONFIG_PM or CONFIG_CPUIDLE is set, GPTIMER2 with sysclock
should be an option.

As I commented before, high resolution timer is very useful for trace, debug or
high frequency perf sample. Suppose you want to trace the running time of
one function,  32K counter can only give you a resolution of ~35us, which is
too coarse to work well.


Thanks,
-- 
Ming Lei


From shawn.guo at linaro.org  Fri Mar 30 21:33:45 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 31 Mar 2012 09:33:45 +0800
Subject: [PATCH] ARM: amba: adapt to regulator probe deferral change
In-Reply-To: <CAOMZO5ATwkFOc=B55atMgugx7uiwVe1MyTHS2ynSX7dF5N+S3A@mail.gmail.com>
References: <1333115737-1654-1-git-send-email-shawn.guo@linaro.org>
 <CAOMZO5ATwkFOc=B55atMgugx7uiwVe1MyTHS2ynSX7dF5N+S3A@mail.gmail.com>
Message-ID: <20120331013342.GJ3254@S2101-09.ap.freescale.net>

On Fri, Mar 30, 2012 at 11:23:13AM -0300, Fabio Estevam wrote:
> On Fri, Mar 30, 2012 at 10:55 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> > The commit 04bf301 (regulator: Support driver probe deferral) changes
> > regulator_get() and regulator_register() to return -EPROBE_DEFER
> > instead of -ENODEV. ?Adapt amba bus driver to the change, otherwise
> > amba_probe() will fail on the platforms that do not have "vcore"
> > regulator device.
> >
> > It fixes the boot failure on i.mx28 which uses amba-pl011 as serial
> > console.
> 
> Tested this patch in linux-next-20120330 and my mx28evk still does not boot.
> 
> Any other patch is needed?

Yes.  One more fix is needed.

serial: PL011: move interrupt clearing
http://permalink.gmane.org/gmane.linux.ports.arm.kernel/158694

-- 
Regards,
Shawn


From robherring2 at gmail.com  Fri Mar 30 23:57:28 2012
From: robherring2 at gmail.com (Rob Herring)
Date: Fri, 30 Mar 2012 22:57:28 -0500
Subject: [PATCH] ARM: at91: resurrect mach-at91/include/mach/io.h
In-Reply-To: <4f7637c4.51e4cc0a.35ba.ffffce95@mx.google.com>
References: <4f7637c4.51e4cc0a.35ba.ffffce95@mx.google.com>
Message-ID: <4F7680A8.8030803@gmail.com>

On 03/30/2012 05:46 PM, manabian at gmail.com wrote:
> From: Joachim Eastwood <joachim.eastwood at jotron.com>
> 
> Commmit 4d5fc58dbe34b78 "ARM: remove bunch of now unused mach/io.h files"
> removed the at91 io.h header. This makes pata_pcmcia when used with at91_cf
> fail on ioport_map in pcmcia_init_one.
> 
> Adding io.h and NEED_MACH_IO_H makes my CF card work again.
> 
> Signed-off-by: Joachim Eastwood <joachim.eastwood at jotron.com>
> ---
> 
> If there is better/correct way to solve the problem please disregard this
> patch.

There is but it's not planned for 3.4. This fix is fine for 3.4 with one
comment below.

The real solution involves creating a fixed i/o virtual address for all
ARM platforms. Some testing to verify would help me. The following steps
are needed:

Create a static mapping for your i/o region (up to 1MB) at virtual
address 0xfef00000. The phys addr for this would be what
cf->phys_baseaddr + CF_IO_PHYS works out to. Then define __io to this:

#define __io(x) (0xfef00000 + ((x) & 0xfffff))

The i/o address needs to be an offset from the i/o base. I think this
line is wrong (but works with old __io definition) and needs to be
removed from at91_cf.c:

	/* pcmcia layer only remaps "real" memory not iospace */
	cf->socket.io_offset = (unsigned long)
			ioremap(cf->phys_baseaddr + CF_IO_PHYS, SZ_2K);


> 
>  arch/arm/mach-at91/Kconfig           |    1 +
>  arch/arm/mach-at91/include/mach/io.h |   32 ++++++++++++++++++++++++++++++++
>  2 files changed, 33 insertions(+)
>  create mode 100644 arch/arm/mach-at91/include/mach/io.h
> 
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index 6631d35..8bcf917 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -37,6 +37,7 @@ config ARCH_AT91RM9200
>  	select GENERIC_CLOCKEVENTS
>  	select HAVE_AT91_DBGU0
>  	select HAVE_AT91_USART3
> +	select NEED_MACH_IO_H
>  
>  config ARCH_AT91SAM9260
>  	bool "AT91SAM9260 or AT91SAM9XE"
> diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
> new file mode 100644
> index 0000000..ba9a22f
> --- /dev/null
> +++ b/arch/arm/mach-at91/include/mach/io.h
> @@ -0,0 +1,32 @@
> +/*
> + * arch/arm/mach-at91/include/mach/io.h
> + *
> + *  Copyright (C) 2003 SAN People
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +
> +#ifndef __ASM_ARCH_IO_H
> +#define __ASM_ARCH_IO_H
> +
> +#include <mach/hardware.h>
> +
> +#define IO_SPACE_LIMIT		0xFFFFFFFF
> +
> +#define __io(a)			__typesafe_io(a)
> +#define __mem_pci(a)		(a)

__mem_pci is removed now.

Rob

> +
> +#endif
> +



From shawn.guo at linaro.org  Sat Mar 31 00:34:09 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 31 Mar 2012 12:34:09 +0800
Subject: [PATCH 1/2] ARM: fix builds due to missing <asm/system_misc.h>
 includes
In-Reply-To: <1333118281-25295-1-git-send-email-olof@lixom.net>
References: <1333118281-25295-1-git-send-email-olof@lixom.net>
Message-ID: <20120331043405.GI19506@S2101-09.ap.freescale.net>

On Fri, Mar 30, 2012 at 07:38:01AM -0700, Olof Johansson wrote:
> This does a sweeping change fixing up all the missing system_misc.h and
> system_info.h includes from the system.h split-up change. These were the
> ones I came across when building all defconfigs in arch/arm/configs, there
> might be more but they lack adequate build coverage to be easily caught.
> 
> I'm expecting to get a lot of these piecemeal by each maintainer, so we
> might just as well do one sweeping change to get them all at once.
> 
> 
> Cc: Nicolas Ferre <nicolas.ferre at atmel.com>
> Cc: Russell King <linux at arm.linux.org.uk>
> Cc: Sascha Hauer <kernel at pengutronix.de>
> Cc: Imre Kaloz <kaloz at openwrt.org>
> Cc: Krzysztof Halasa <khc at pm.waw.pl>
> Cc: Eric Miao <eric.y.miao at gmail.com>
> Cc: Haojian Zhuang <haojian.zhuang at gmail.com>
> Cc: Wan ZongShun <mcuos.com at gmail.com>
> Cc: Kukjin Kim <kgene.kim at samsung.com>
> Signed-off-by: Olof Johansson <olof at lixom.net>
> ---
...
>  arch/arm/mach-imx/mm-imx3.c   |    1 +
>  arch/arm/mach-imx/mm-imx5.c   |    1 +

The changes are same as the patch below that I sent a little earlier.

  ARM: imx: fix ?arm_pm_idle? undeclared error

So,

Acked-by: Shawn Guo <shawn.guo at linaro.org>

-- 
Regards,
Shawn


From nico at fluxnic.net  Sat Mar 31 00:58:47 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Sat, 31 Mar 2012 00:58:47 -0400 (EDT)
Subject: error: 'SEGMENT_SIZE' undeclared with arm-eabi-gcc toolchain
In-Reply-To: <4F7638C3.4060301@samsung.com>
References: <4F7638C3.4060301@samsung.com>
Message-ID: <alpine.LFD.2.02.1203310017440.24151@xanadu.home>

On Fri, 30 Mar 2012, Kukjin Kim wrote:

> Hi all,
> 
> Occurs following error with arm-eabi-gcc toolchain (gcc version 4.4.3 -
> GCC). But there is no error with arm-none-linux-gnueabi-gcc toolchain
> (gcc version 4.4.1 - Sourcery G++ Lite 2009q3)...
> 
> fs/binfmt_aout.c: In function 'load_aout_binary':
> fs/binfmt_aout.c:255: error: 'SEGMENT_SIZE' undeclared (first use in
> this function)
> fs/binfmt_aout.c:255: error: (Each undeclared identifier is reported
> only once
> fs/binfmt_aout.c:255: error: for each function it appears in.)
> make[2]: *** [fs/binfmt_aout.o] Error 1
> make[2]: *** Waiting for unfinished jobs....
> make[1]: *** [fs] Error 2
> 
> Any idea?

Yes.  This comes from the N_DATADDR() macro, defined in 
include/linux/a.out.h as follows:

|#define N_DATADDR(x) \
|    (N_MAGIC(x)==OMAGIC? (_N_TXTENDADDR(x)) \
|     : (_N_SEGMENT_ROUND (_N_TXTENDADDR(x))))

Then, looking at _N_SEGMENT_ROUND() in the same file:

|#define _N_SEGMENT_ROUND(x) ALIGN(x, SEGMENT_SIZE)

Here it is.  Now, why isn't SEGMENT_SIZE defined?  Well that's where 
things get way more hairy than they are already (caution, barf bag 
recommended):

|/* Address of data segment in memory after it is loaded.
|   Note that it is up to you to define SEGMENT_SIZE
|   on machines not listed here.  */
|#if defined(vax) || defined(hp300) || defined(pyr)
|#define SEGMENT_SIZE page_size
|#endif
|#ifdef	sony
|#define	SEGMENT_SIZE	0x2000
|#endif	/* Sony.  */
|#ifdef is68k
|#define SEGMENT_SIZE 0x20000
|#endif
|#if defined(m68k) && defined(PORTAR)
|#define PAGE_SIZE 0x400
|#define SEGMENT_SIZE PAGE_SIZE
|#endif
|
|#ifdef linux
|#ifdef __KERNEL__
|#include <asm/page.h>
|#else
|#include <unistd.h>
|#endif
|#if defined(__i386__) || defined(__mc68000__)
|#define SEGMENT_SIZE	1024
|#else
|#ifndef SEGMENT_SIZE
|#ifdef __KERNEL__
|#define SEGMENT_SIZE	PAGE_SIZE
|#else
|#define SEGMENT_SIZE   getpagesize()
|#endif
|#endif
|#endif
|#endif

So the clue you're looking for is probably on the 18th line above.

BTW, no one is using a.out on ARM anymore.  You should really consider 
removing CONFIG_BINFMT_AOUT from your config.


Nicolas


From shawn.guo at linaro.org  Sat Mar 31 01:25:18 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 31 Mar 2012 13:25:18 +0800
Subject: [PATCH] ARM: amba: adapt to regulator probe deferral change
In-Reply-To: <20120330180134.GJ22981@n2100.arm.linux.org.uk>
References: <1333115737-1654-1-git-send-email-shawn.guo@linaro.org>
 <20120330180134.GJ22981@n2100.arm.linux.org.uk>
Message-ID: <20120331052516.GK3254@S2101-09.ap.freescale.net>

On Fri, Mar 30, 2012 at 07:01:34PM +0100, Russell King - ARM Linux wrote:
> On Fri, Mar 30, 2012 at 09:55:37PM +0800, Shawn Guo wrote:
> > The commit 04bf301 (regulator: Support driver probe deferral) changes
> > regulator_get() and regulator_register() to return -EPROBE_DEFER
> > instead of -ENODEV.  Adapt amba bus driver to the change, otherwise
> > amba_probe() will fail on the platforms that do not have "vcore"
> > regulator device.
> 
> Are you sure this is correct?  Did you read and understand the comment
> you removed?
> 
I did read the comment and try to understand it.  Correct me if the
understanding below is wrong.

> What do platforms do which have AMBA devices but don't have any vcore
> regulators?
> 
We will have two cases for platforms that do not have any vcore
regulators.

1) CONFIG_REGULATOR is not enabled

   The regulator_get() returns NULL, and regulator_enable() returns 0.
   amba_get_enable_vcore() will succeed with 'ret' as 0.  My patch
   changes nothing for this case.

2) CONFIG_REGULATOR is enabled but platform never registers any vcore
   regulators

   Before commit 04bf301 (regulator: Support driver probe deferral),
   regulator_get() returns ERR_PTR(-ENODEV) when no "vore" regulator
   is found, and the check "if (PTR_ERR(vcore) == -ENODEV)" in
   amba_get_enable_vcore() forces a success return.   Now that commit
   changes regulator_get() to returns ERR_PTR(-EPROBE_DEFER) in case
   that no "vore" regulator is found.  My patch changes the check in
   amba_get_enable_vcore() from -ENODEV to -EPROBE_DEFER accordingly.
   And that's all what my patch does.

> We're not going through the same farce that the smsc network driver has
> gone through: OMAP3430LDP remains fucked through that idiotic ill-thought
> out change (c7e963f68888, net/smsc911x: Add regulator support).  See
> http://www.arm.linux.org.uk/developer/build/result.php?type=boot&idx=99

If the understanding above is correct, I do not see how my patch would
bring the same farce into amba driver.

-- 
Regards,
Shawn


From santosh.shilimkar at ti.com  Sat Mar 31 02:30:18 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Sat, 31 Mar 2012 12:00:18 +0530
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CACVXFVPbU2OqTN=S0AZCD10KuSBYxqyyRH_xee+WTaCD6VSmMQ@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
 <4F7570FC.8000907@ti.com>
 <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>
 <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>
 <CACVXFVPbU2OqTN=S0AZCD10KuSBYxqyyRH_xee+WTaCD6VSmMQ@mail.gmail.com>
Message-ID: <CAMQu2gzuQ-q+3RHsW0=U305jCF-td5-PEXkGZ6WnQTqA1K8oAQ@mail.gmail.com>

On Sat, Mar 31, 2012 at 7:00 AM, Ming Lei <tom.leiming at gmail.com> wrote:
> On Fri, Mar 30, 2012 at 5:20 PM, Shilimkar, Santosh <santosh.shilimkar at ti.com>
>>
>>> After Ming Lie's comment, the point that I came to my mind was,
>>> certainly there will be resolution difference between these two clocksources,
>>> if ?gptimer2 is sourced from sys_ck (26Mhz).
>>>
>> GPTIMER2 with sysclock is not an option. GPTIMER is not in wakeup domain
>> and when sysclock is cut, it stops.
>
> If neither CONFIG_PM or CONFIG_CPUIDLE is set, GPTIMER2 with sysclock
> should be an option.
>
So it's a PM disable kernel and you will recompile it.

> As I commented before, high resolution timer is very useful for trace, debug or
> high frequency perf sample. Suppose you want to trace the running time of
> one function, ?32K counter can only give you a resolution of ~35us, which is
> too coarse to work well.
>
Since you need to recompile the kernel, you can very much tweak the
clocksource to use GPTIMER with sysl clock. Support for that is still
in place.

Regards
Santosh


From santosh.shilimkar at ti.com  Sat Mar 31 02:37:14 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Sat, 31 Mar 2012 12:07:14 +0530
Subject: [PATCH 2/3] ARM: OMAP4: cpuidle: Use coupled cpuidle states to
 implement SMP cpuidle.
In-Reply-To: <CAMbhsRRAQxDh_yZKayqMedvGkeSP9UGxiud9LbotWp-aMQ7cSw@mail.gmail.com>
References: <1333114048-26136-1-git-send-email-santosh.shilimkar@ti.com>
 <1333114048-26136-3-git-send-email-santosh.shilimkar@ti.com>
 <CAMbhsRRAQxDh_yZKayqMedvGkeSP9UGxiud9LbotWp-aMQ7cSw@mail.gmail.com>
Message-ID: <CAMQu2gzN5PeOB78tA-sb=MKK8qGiCPDmTwSf2AWD77gou=sQCA@mail.gmail.com>

On Sat, Mar 31, 2012 at 1:13 AM, Colin Cross <ccross at android.com> wrote:
> On Fri, Mar 30, 2012 at 6:27 AM, Santosh Shilimkar
> <santosh.shilimkar at ti.com> wrote:
>> OMAP4 CPUDILE driver is converted mainly based on notes from the
>> coupled cpuidle patch series.
>>
>> The changes include :
>> - Register both CPUs and C-states to cpuidle driver.
>> - Set struct cpuidle_device.coupled_cpus
>> - Set struct cpuidle_device.safe_state to non coupled state.
>> - Set CPUIDLE_FLAG_COUPLED in struct cpuidle_state.flags for each
>> ?state that affects multiple cpus.
>> - Separate ->enter hooks for coupled & simple idle.
>> - CPU0 wait loop for CPU1 power transition.
>> - CPU1 wakeup mechanism for the idle exit.
>> - Enabling ARCH_NEEDS_CPU_IDLE_COUPLED for OMAP4.
>>
>> Thanks to Kevin Hilman and Colin Cross on the suggestions/fixes
>> on the intermediate version of this patch.
>>
>> Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>> CC: Kevin Hilman <khilman at ti.com>
>> Cc: Colin Cross <ccross at android.com>
>> ---
>> ?arch/arm/mach-omap2/Kconfig ? ? ? | ? ?1 +
>> ?arch/arm/mach-omap2/cpuidle44xx.c | ?167 ++++++++++++++++++++++---------------
>> ?2 files changed, 101 insertions(+), 67 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
>> index e20c8ab..250786e 100644
>> --- a/arch/arm/mach-omap2/Kconfig
>> +++ b/arch/arm/mach-omap2/Kconfig
>> @@ -54,6 +54,7 @@ config ARCH_OMAP4
>> ? ? ? ?select PM_OPP if PM
>> ? ? ? ?select USB_ARCH_HAS_EHCI
>> ? ? ? ?select ARM_CPU_SUSPEND if PM
>> + ? ? ? select ARCH_NEEDS_CPU_IDLE_COUPLED if CPU_IDLE
> The "if CPU_IDLE" is not necessary, ARCH_NEEDS_CPU_IDLE_COUPLED is
> designed to have no effect if CPU_IDLE is not set.
>
OK. Will drop that if then.

>>
>> ?comment "OMAP Core Type"
>> ? ? ? ?depends on ARCH_OMAP2
>> diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
>> index f386cbe..5724393 100644
>> --- a/arch/arm/mach-omap2/cpuidle44xx.c
>> +++ b/arch/arm/mach-omap2/cpuidle44xx.c
>> @@ -21,6 +21,7 @@
>> ?#include "common.h"
>> ?#include "pm.h"
>> ?#include "prm.h"
>> +#include "clockdomain.h"
>>
>> ?#ifdef CONFIG_CPU_IDLE
>>
>> @@ -44,10 +45,11 @@ static struct cpuidle_params cpuidle_params_table[] = {
>> ?#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
>>
>> ?struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
>> -static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
>> +static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
>> +static struct clockdomain *cpu_clkdm[NR_CPUS];
>>
>> ?/**
>> - * omap4_enter_idle - Programs OMAP4 to enter the specified state
>> + * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
>> ?* @dev: cpuidle device
>> ?* @drv: cpuidle driver
>> ?* @index: the index of state to be entered
>> @@ -56,34 +58,40 @@ static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
>> ?* specified low power state selected by the governor.
>> ?* Returns the amount of time spent in the low power state.
>> ?*/
>> -static int omap4_enter_idle(struct cpuidle_device *dev,
>> +static int omap4_enter_idle_simple(struct cpuidle_device *dev,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct cpuidle_driver *drv,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int index)
>> +{
>> + ? ? ? local_fiq_disable();
>> + ? ? ? omap_do_wfi();
>> + ? ? ? local_fiq_enable();
>> +
>> + ? ? ? return index;
>> +}
>> +
>> +static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
>> ? ? ? ? ? ? ? ? ? ? ? ?struct cpuidle_driver *drv,
>> ? ? ? ? ? ? ? ? ? ? ? ?int index)
>> ?{
>> ? ? ? ?struct omap4_idle_statedata *cx =
>> ? ? ? ? ? ? ? ? ? ? ? ?cpuidle_get_statedata(&dev->states_usage[index]);
>> - ? ? ? u32 cpu1_state;
>> ? ? ? ?int cpu_id = smp_processor_id();
>>
>> ? ? ? ?local_fiq_disable();
>>
>> + ? ? ? clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
>> +
>> ? ? ? ?/*
>> - ? ? ? ?* CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
>> + ? ? ? ?* CPU0 has to wait and stay ON until CPU1 is OFF state.
>> ? ? ? ? * This is necessary to honour hardware recommondation
>> ? ? ? ? * of triggeing all the possible low power modes once CPU1 is
>> ? ? ? ? * out of coherency and in OFF mode.
>> - ? ? ? ?* Update dev->last_state so that governor stats reflects right
>> - ? ? ? ?* data.
>> ? ? ? ? */
>> - ? ? ? cpu1_state = pwrdm_read_pwrst(cpu1_pd);
>> - ? ? ? if (cpu1_state != PWRDM_POWER_OFF) {
>> - ? ? ? ? ? ? ? index = drv->safe_state_index;
>> - ? ? ? ? ? ? ? cx = cpuidle_get_statedata(&dev->states_usage[index]);
>> + ? ? ? if (dev->cpu == 0) {
>> + ? ? ? ? ? ? ? while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF)
>> + ? ? ? ? ? ? ? ? ? ? ? cpu_relax();
> If something goes wrong in the core coupled code or in the cpu 1 power
> state transition, this will hang forever and be hard to debug. ?It
> might be worth adding a timeout with a BUG_ON.
>
This condition is handled in patch 3/3

>> ? ? ? ?}
>>
>> - ? ? ? if (index > 0)
>> - ? ? ? ? ? ? ? clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
>> -
>> ? ? ? ?/*
>> ? ? ? ? * Call idle CPU PM enter notifier chain so that
>> ? ? ? ? * VFP and per CPU interrupt context is saved.
>> @@ -91,25 +99,35 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
>> ? ? ? ?if (cx->cpu_state == PWRDM_POWER_OFF)
>> ? ? ? ? ? ? ? ?cpu_pm_enter();
> This should never get called without cpu_state == PWRDM_POWER_OFF, and
> even if it did, calling cpu_pm_enter shouldn't hurt anything. ?It
> would be clearer to unconditionally call cpu_pm_enter().
>
Actually coupled state is called only for CPU mode, so the check can be removed.

>>
>> - ? ? ? pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
>> - ? ? ? omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
>> -
>> - ? ? ? /*
>> - ? ? ? ?* Call idle CPU cluster PM enter notifier chain
>> - ? ? ? ?* to save GIC and wakeupgen context.
>> - ? ? ? ?*/
>> - ? ? ? if ((cx->mpu_state == PWRDM_POWER_RET) &&
>> - ? ? ? ? ? ? ? (cx->mpu_logic_state == PWRDM_POWER_OFF))
>> - ? ? ? ? ? ? ? ? ? ? ? cpu_cluster_pm_enter();
>> + ? ? ? if (dev->cpu == 0) {
>> + ? ? ? ? ? ? ? pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
>> + ? ? ? ? ? ? ? omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
>> +
>> + ? ? ? ? ? ? ? /*
>> + ? ? ? ? ? ? ? ?* Call idle CPU cluster PM enter notifier chain
>> + ? ? ? ? ? ? ? ?* to save GIC and wakeupgen context.
>> + ? ? ? ? ? ? ? ?*/
>> + ? ? ? ? ? ? ? if ((cx->mpu_state == PWRDM_POWER_RET) &&
>> + ? ? ? ? ? ? ? ? ? ? ? (cx->mpu_logic_state == PWRDM_POWER_OFF))
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cpu_cluster_pm_enter();
>> + ? ? ? }
>>
>> ? ? ? ?omap4_enter_lowpower(dev->cpu, cx->cpu_state);
>>
>> + ? ? ? if (dev->cpu == 0) {
>> + ? ? ? ? ? ? ? /* Wakeup CPU1 only if it is not offlined */
>> + ? ? ? ? ? ? ? if (cpumask_test_cpu(1, cpu_online_mask)) {
>> + ? ? ? ? ? ? ? ? ? ? ? clkdm_wakeup(cpu_clkdm[1]);
>> + ? ? ? ? ? ? ? ? ? ? ? clkdm_allow_idle(cpu_clkdm[1]);
>> + ? ? ? ? ? ? ? }
>> + ? ? ? }
>> +
>> ? ? ? ?/*
>> ? ? ? ? * Call idle CPU PM exit notifier chain to restore
>> ? ? ? ? * VFP and per CPU IRQ context. Only CPU0 state is
>> ? ? ? ? * considered since CPU1 is managed by CPU hotplug.
>> ? ? ? ? */
> This comment is no longer accurate? ?cpu_pm_enter is called on cpu 1 above.
>
Yep. Didn't pay much attention on the comments. Will fix it.


>> - ? ? ? if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
>> + ? ? ? if (pwrdm_read_prev_pwrst(cpu_pd[dev->cpu]) == PWRDM_POWER_OFF)
>> ? ? ? ? ? ? ? ?cpu_pm_exit();
> This should get called unconditionally. ?It's not explicitly stated,
> but the cpu_pm_* api expects cpu_pm_exit() to be called after
> cpu_pm_enter(), even if the low power state was not entered.
> Otherwise, a cpu_pm_enter notifier that disables the hardware will not
> get a chance to re-enable it.

I know what you mean now. the hardware like CPU interface can be
disabled/enabled in the notifiers so would make sense to call them
unconditionally. Will remove the check in both cases.

Regards
Santosh


From linux at arm.linux.org.uk  Sat Mar 31 04:16:59 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 31 Mar 2012 09:16:59 +0100
Subject: [PATCH] ARM: include linux/bug.h in insn.c
In-Reply-To: <1333142002-15431-1-git-send-email-joachim.eastwood@jotron.com>
References: <1333142002-15431-1-git-send-email-joachim.eastwood@jotron.com>
Message-ID: <20120331081659.GA26661@n2100.arm.linux.org.uk>

On Fri, Mar 30, 2012 at 11:13:22PM +0200, Joachim Eastwood wrote:
> After commit d82227cf8 building the kernel fails with:
>   arch/arm/kernel/insn.c: In function '__arm_gen_branch_thumb2':
>   arch/arm/kernel/insn.c:13: error: implicit declaration of function 'WARN_ON_ONCE'
>   make[1]: *** [arch/arm/kernel/insn.o] Error 1
>   make: *** [arch/arm/kernel] Error 2
> 
> insn.c uses WARN_ON_ONCE so lets include bug.h.

I already have this in my tree.


From shawn.guo at linaro.org  Sat Mar 31 04:33:31 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 31 Mar 2012 16:33:31 +0800
Subject: [PATCH 1/2] regulator: fix sysfs name collision between dummy and
 fixed dummy regulator
Message-ID: <1333182812-423-1-git-send-email-shawn.guo@linaro.org>

When regulator_register_fixed() is being used to register fixed dummy
regulator, the following line will be seen in the boot log.  And the
sysfs entry for fixed dummy regulator is not shown.

  dummy: Failed to create debugfs directory

The patch renames the fixed dummy supply to "fixed-dummy" to avoid
the name collision with dummy regulator.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 drivers/regulator/fixed-helper.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/regulator/fixed-helper.c b/drivers/regulator/fixed-helper.c
index 30d0a15..efb52dc 100644
--- a/drivers/regulator/fixed-helper.c
+++ b/drivers/regulator/fixed-helper.c
@@ -32,7 +32,7 @@ struct platform_device *regulator_register_fixed(int id,
 	if (!data)
 		return NULL;
 
-	data->cfg.supply_name = "dummy";
+	data->cfg.supply_name = "fixed-dummy";
 	data->cfg.microvolts = 0;
 	data->cfg.gpio = -EINVAL;
 	data->cfg.enabled_at_boot = 1;
-- 
1.7.5.4



From shawn.guo at linaro.org  Sat Mar 31 04:33:32 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 31 Mar 2012 16:33:32 +0800
Subject: [PATCH 2/2] regulator: rename function regulator_register_fixed
In-Reply-To: <1333182812-423-1-git-send-email-shawn.guo@linaro.org>
References: <1333182812-423-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1333182812-423-2-git-send-email-shawn.guo@linaro.org>

Function regulator_register_fixed() is only meant for registering
fixed dummy regulators.  Rename it to regulator_register_fixed_dummy()
for the explicit meaning, so that people do not attempt to register
those real fixed regulators with this function.

It also removes the kernel doc for @name which is not a parameter for
the function at all.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/mach-pcm037.c    |    3 ++-
 arch/arm/plat-mxc/3ds_debugboard.c |    3 ++-
 drivers/regulator/fixed-helper.c   |    5 ++---
 include/linux/regulator/fixed.h    |    4 ++--
 4 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 5fddf94..d8ceaba 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -586,7 +586,8 @@ static void __init pcm037_init(void)
 
 	imx31_soc_init();
 
-	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+	regulator_register_fixed_dummy(0, dummy_supplies,
+				       ARRAY_SIZE(dummy_supplies));
 
 	mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
 
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index d1e31fa..5e3cdf1 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -195,7 +195,8 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
 	irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
 
 	/* Register Lan device on the debugboard */
-	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+	regulator_register_fixed_dummy(0, dummy_supplies,
+				       ARRAY_SIZE(dummy_supplies));
 
 	smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
 	smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
diff --git a/drivers/regulator/fixed-helper.c b/drivers/regulator/fixed-helper.c
index efb52dc..b24c90b 100644
--- a/drivers/regulator/fixed-helper.c
+++ b/drivers/regulator/fixed-helper.c
@@ -17,13 +17,12 @@ static void regulator_fixed_release(struct device *dev)
 }
 
 /**
- * regulator_register_fixed - register a no-op fixed regulator
- * @name: supply name
+ * regulator_register_fixed_dummy - register a dummy no-op fixed regulator
  * @id: platform device id
  * @supplies: consumers for this regulator
  * @num_supplies: number of consumers
  */
-struct platform_device *regulator_register_fixed(int id,
+struct platform_device *regulator_register_fixed_dummy(int id,
 		struct regulator_consumer_supply *supplies, int num_supplies)
 {
 	struct fixed_regulator_data *data;
diff --git a/include/linux/regulator/fixed.h b/include/linux/regulator/fixed.h
index 936a7d8..2a956a9 100644
--- a/include/linux/regulator/fixed.h
+++ b/include/linux/regulator/fixed.h
@@ -51,10 +51,10 @@ struct fixed_voltage_config {
 struct regulator_consumer_supply;
 
 #if IS_ENABLED(CONFIG_REGULATOR)
-struct platform_device *regulator_register_fixed(int id,
+struct platform_device *regulator_register_fixed_dummy(int id,
 		struct regulator_consumer_supply *supplies, int num_supplies);
 #else
-static inline struct platform_device *regulator_register_fixed(int id,
+static inline struct platform_device *regulator_register_fixed_dummy(int id,
 		struct regulator_consumer_supply *supplies, int num_supplies)
 {
 	return NULL;
-- 
1.7.5.4



From tom.leiming at gmail.com  Sat Mar 31 04:39:36 2012
From: tom.leiming at gmail.com (Ming Lei)
Date: Sat, 31 Mar 2012 16:39:36 +0800
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CAMQu2gzuQ-q+3RHsW0=U305jCF-td5-PEXkGZ6WnQTqA1K8oAQ@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
 <4F7570FC.8000907@ti.com>
 <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>
 <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>
 <CACVXFVPbU2OqTN=S0AZCD10KuSBYxqyyRH_xee+WTaCD6VSmMQ@mail.gmail.com>
 <CAMQu2gzuQ-q+3RHsW0=U305jCF-td5-PEXkGZ6WnQTqA1K8oAQ@mail.gmail.com>
Message-ID: <CACVXFVPu1GEQy+sCgXMB8JCszPBBs8zHRVm94TYb1-y2afkqgw@mail.gmail.com>

On Sat, Mar 31, 2012 at 2:30 PM, Shilimkar, Santosh
> Since you need to recompile the kernel, you can very much tweak the
> clocksource to use GPTIMER with sysl clock. Support for that is still
> in place.

With current kernel, running 'make menuconfig' can do it, but after applying
Hiremath's patch[1], I have to edit the source code manually to get it, so looks
this kind of tweaking is not friendly enough, :-(

[1], http://marc.info/?l=linux-arm-kernel&m=133311647410324&w=2

Thanks,
-- 
Ming Lei


From shawn.guo at linaro.org  Sat Mar 31 04:46:17 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 31 Mar 2012 16:46:17 +0800
Subject: [PATCH] ARM: imx: fix mc9s08dz60_gpiochip_match parameter type
Message-ID: <1333183577-2109-1-git-send-email-shawn.guo@linaro.org>

Due to the change made by commit 6e2cf65 (gpio: constify the data
parameter to gpiochip_find()), the following compile warning is seen
on imx_v6_v7_defconfig build.

  CC      arch/arm/mach-imx/mach-mx35_3ds.o
arch/arm/mach-imx/mach-mx35_3ds.c: In function ?mx35_3ds_lcd_set_power?:
arch/arm/mach-imx/mach-mx35_3ds.c:112:5: warning: passing argument 2 of ?gpiochip_find? from incompatible pointer type [enabled by default]
include/asm-generic/gpio.h:145:26: note: expected ?int (*)(struct gpio_chip *, const void *)? but argument is of type ?int (*)(struct gpio_chip *, void *)?

Change mc9s08dz60_gpiochip_match parameter type accordingly to fix
the warning.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
---
 arch/arm/mach-imx/mach-mx35_3ds.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index e14291d..6ae51c6 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -97,7 +97,7 @@ static struct i2c_board_info __initdata i2c_devices_3ds[] = {
 static int lcd_power_gpio = -ENXIO;
 
 static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
-						     void *data)
+						     const void *data)
 {
 	return !strcmp(chip->label, data);
 }
-- 
1.7.5.4



From broonie at opensource.wolfsonmicro.com  Sat Mar 31 06:19:54 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 31 Mar 2012 11:19:54 +0100
Subject: [PATCH v6 1/5] Extcon (external connector): import Android's
 switch class and modify.
In-Reply-To: <CACSP8SjhOZcXZa2hCNsH8zS+hm8X-i9uNm50UH=_VwOV=BJGmA@mail.gmail.com>
References: <1328856038-21912-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-1-git-send-email-myungjoo.ham@samsung.com>
 <1330344939-18394-2-git-send-email-myungjoo.ham@samsung.com>
 <20120309124119.GV3273@opensource.wolfsonmicro.com>
 <CACSP8ShU5tu=9N53PtYMLyFVFMS9whNRhMvu7nu8rBoPuVCy+Q@mail.gmail.com>
 <20120330100742.GB21950@opensource.wolfsonmicro.com>
 <CACSP8SjhOZcXZa2hCNsH8zS+hm8X-i9uNm50UH=_VwOV=BJGmA@mail.gmail.com>
Message-ID: <20120331101953.GA3163@opensource.wolfsonmicro.com>

On Fri, Mar 30, 2012 at 10:29:27AM -0700, Erik Gilling wrote:

> I'm also not in favor of having functionality conditionally compiled
> based on CONFIG_ANDROID.  If fact, going through the patch stack
> there's much more that changes the ABI from the switch driver than
> just the name.  Android asumes that there is a single "switch" for
> each logical entity (called cable types in extcon) each with a binary
> state (0,1).  Here things have changed to have a single extcon
> instance that can have a bitmask of states which are sent as strings
> in the uevent.

The binary status thing isn't true for the original Android switch API,
at least not in all cases - for headsets it's a tristate indicating if
there's nothing, a headphone or headset plugged in.  This does wind up
being a bitmask because the numbers are 0, 1 and 2 but it isn't really
clear to me if this is intentional or just an effect of counting.

> As it stands, this patch does not solve the cases where we use switch
> today and we'll probably continue to carry the switch driver in the
> common android tree.  If, instead, we got rid of the idea of multiple
> states and mutual exclusivity and relied on the driver that uses
> extcon to have multiple instances for each logical entity and deal
> with mutual exclusion itself, we'd have a driver that would be pretty
> easy to support in android.

What's the advantage in not having information about mutual exclusion in
the core, and why would a userspace that isn't interested in this care?  
It seems like this could be used by userspace to do interesting things,
and I rather suspect you'll find some vendors have added features along
those lines in their Android devices.  For example, having different
configurations for desk docks and car docks even if both end up
connecting the same things up.

Even if the userspace ABI doesn't expose the information it seems
sensible to factor out the code for handling this into the core so
there's less work to do in individual drivers.
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From broonie at opensource.wolfsonmicro.com  Sat Mar 31 06:25:08 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 31 Mar 2012 11:25:08 +0100
Subject: [PATCH 2/2] regulator: rename function regulator_register_fixed
In-Reply-To: <1333182812-423-2-git-send-email-shawn.guo@linaro.org>
References: <1333182812-423-1-git-send-email-shawn.guo@linaro.org>
 <1333182812-423-2-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120331102507.GB3163@opensource.wolfsonmicro.com>

On Sat, Mar 31, 2012 at 04:33:32PM +0800, Shawn Guo wrote:

> Function regulator_register_fixed() is only meant for registering
> fixed dummy regulators.  Rename it to regulator_register_fixed_dummy()
> for the explicit meaning, so that people do not attempt to register
> those real fixed regulators with this function.

There's no harm in using it for regulators that physically exist if
nothing cares about any of the information it can't provide and renaming
it now is going to cause annoyance with cross tree issues so I'm kind of
reluctant to apply this.  Are there any concrete problems that have been
caused by this or was it just something you noticed when looking at
using it yourself?

> It also removes the kernel doc for @name which is not a parameter for
> the function at all.

This is already done, I can't remember who sent the patch off the top of
my head.
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From broonie at opensource.wolfsonmicro.com  Sat Mar 31 06:25:50 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 31 Mar 2012 11:25:50 +0100
Subject: [PATCH 1/2] regulator: fix sysfs name collision between dummy
 and fixed dummy regulator
In-Reply-To: <1333182812-423-1-git-send-email-shawn.guo@linaro.org>
References: <1333182812-423-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120331102549.GC3163@opensource.wolfsonmicro.com>

On Sat, Mar 31, 2012 at 04:33:31PM +0800, Shawn Guo wrote:
> When regulator_register_fixed() is being used to register fixed dummy
> regulator, the following line will be seen in the boot log.  And the
> sysfs entry for fixed dummy regulator is not shown.
> 
>   dummy: Failed to create debugfs directory
> 
> The patch renames the fixed dummy supply to "fixed-dummy" to avoid
> the name collision with dummy regulator.

Applied, thanks.
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From lost.distance at yahoo.com  Sat Mar 31 08:20:37 2012
From: lost.distance at yahoo.com (Paul Parsons)
Date: Sat, 31 Mar 2012 13:20:37 +0100 (BST)
Subject: [PATCH] ARM: pxa: mfp: Force gpio direction for MFP_LPM_KEEP_OUTPUT
Message-ID: <1333196437.11228.YahooMailClassic@web29011.mail.ird.yahoo.com>

Some MFP configurations specify MFP_LPM_KEEP_OUTPUT to preserve the gpio output
value (HIGH or LOW) during sleep mode. For example:

    GPIO72_GPIO | MFP_LPM_KEEP_OUTPUT,

Unfortunately MFP_LPM_KEEP_OUTPUT makes no special provision for setting the
sleep mode gpio direction, unlike MFP_LPM_DRIVE_HIGH and MFP_LPM_DRIVE_LOW.
Consequently MFP configurations of the form:

    GPIO<n>_GPIO | MFP_LPM_KEEP_OUTPUT,

will set the sleep mode gpio direction to INPUT.

This patch forces the sleep mode gpio direction to OUTPUT in cases where
MFP_LPM_KEEP_OUTPUT was specified. This brings MFP_LPM_KEEP_OUTPUT into line
with MFP_LPM_DRIVE_HIGH and MFP_LPM_DRIVE_LOW.

Signed-off-by: Paul Parsons <lost.distance at yahoo.com>
---

diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index b0a8428..3b443199 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -96,6 +96,9 @@ static int __mfp_config_gpio(unsigned gpio, unsigned long c)
 		break;
 	}
 
+	if (c & MFP_LPM_KEEP_OUTPUT)
+		is_out = 1;
+
 	if (is_out ^ gpio_desc[gpio].dir_inverted)
 		gpdr_lpm[bank] |= mask;
 	else



From b29396 at freescale.com  Sat Mar 31 08:37:48 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Sat, 31 Mar 2012 20:37:48 +0800
Subject: [PATCH 1/1] ASoC: soc-dmaengine-pcm: fix compile error since dma api
 is changed
Message-ID: <1333197468-3263-1-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

The following compiling error is caused by the API device_prep_dma_cyclic
is changed. Using dmaengine_prep_dma_cyclic to fix it.

sound/soc/soc-dmaengine-pcm.c: In function 'dmaengine_pcm_prepare_and_submit':
sound/soc/soc-dmaengine-pcm.c:149: error: too few arguments to function 'chan->device->device_prep_dma_cyclic'
make[2]: *** [sound/soc/soc-dmaengine-pcm.o] Error 1
make[1]: *** [sound/soc] Error 2
make: *** [sound] Error 2

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
 sound/soc/soc-dmaengine-pcm.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/sound/soc/soc-dmaengine-pcm.c b/sound/soc/soc-dmaengine-pcm.c
index 4420b70..4756952 100644
--- a/sound/soc/soc-dmaengine-pcm.c
+++ b/sound/soc/soc-dmaengine-pcm.c
@@ -143,7 +143,7 @@ static int dmaengine_pcm_prepare_and_submit(struct snd_pcm_substream *substream)
 	direction = snd_pcm_substream_to_dma_direction(substream);
 
 	prtd->pos = 0;
-	desc = chan->device->device_prep_dma_cyclic(chan,
+	desc = dmaengine_prep_dma_cyclic(chan,
 		substream->runtime->dma_addr,
 		snd_pcm_lib_buffer_bytes(substream),
 		snd_pcm_lib_period_bytes(substream), direction);
-- 
1.7.0.4




From lars at metafoo.de  Sat Mar 31 07:33:33 2012
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Sat, 31 Mar 2012 13:33:33 +0200
Subject: [alsa-devel] [PATCH 1/1] ASoC: soc-dmaengine-pcm: fix compile
 error	since dma api is changed
In-Reply-To: <1333197468-3263-1-git-send-email-b29396@freescale.com>
References: <1333197468-3263-1-git-send-email-b29396@freescale.com>
Message-ID: <4F76EB8D.2060200@metafoo.de>

On 03/31/2012 02:37 PM, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> The following compiling error is caused by the API device_prep_dma_cyclic
> is changed. Using dmaengine_prep_dma_cyclic to fix it.
> 
> sound/soc/soc-dmaengine-pcm.c: In function 'dmaengine_pcm_prepare_and_submit':
> sound/soc/soc-dmaengine-pcm.c:149: error: too few arguments to function 'chan->device->device_prep_dma_cyclic'
> make[2]: *** [sound/soc/soc-dmaengine-pcm.o] Error 1
> make[1]: *** [sound/soc] Error 2
> make: *** [sound] Error 2
> 

Hi,

There is already a fix for this in Mark's for-3.4 branch.


From B29396 at freescale.com  Sat Mar 31 08:39:07 2012
From: B29396 at freescale.com (Dong Aisheng-B29396)
Date: Sat, 31 Mar 2012 12:39:07 +0000
Subject: [alsa-devel] [PATCH 1/1] ASoC: soc-dmaengine-pcm: fix compile
 error	since dma api is changed
In-Reply-To: <4F76EB8D.2060200@metafoo.de>
References: <1333197468-3263-1-git-send-email-b29396@freescale.com>
 <4F76EB8D.2060200@metafoo.de>
Message-ID: <7FE21149F4667147B645348EC6057885153794@039-SN2MPN1-011.039d.mgd.msft.net>

> -----Original Message-----
> From: Lars-Peter Clausen [mailto:lars at metafoo.de]
> Sent: Saturday, March 31, 2012 7:34 PM
> To: Dong Aisheng-B29396
> Cc: alsa-devel at alsa-project.org; broonie at opensource.wolfsonmicro.com;
> lrg at ti.com; linux-arm-kernel at lists.infradead.org
> Subject: Re: [alsa-devel] [PATCH 1/1] ASoC: soc-dmaengine-pcm: fix
> compile error since dma api is changed
> Importance: High
> 
> On 03/31/2012 02:37 PM, Dong Aisheng wrote:
> > From: Dong Aisheng <dong.aisheng at linaro.org>
> >
> > The following compiling error is caused by the API
> > device_prep_dma_cyclic is changed. Using dmaengine_prep_dma_cyclic to
> fix it.
> >
> > sound/soc/soc-dmaengine-pcm.c: In function
> 'dmaengine_pcm_prepare_and_submit':
> > sound/soc/soc-dmaengine-pcm.c:149: error: too few arguments to function
> 'chan->device->device_prep_dma_cyclic'
> > make[2]: *** [sound/soc/soc-dmaengine-pcm.o] Error 1
> > make[1]: *** [sound/soc] Error 2
> > make: *** [sound] Error 2
> >
> 
> Hi,
> 
> There is already a fix for this in Mark's for-3.4 branch.
Okay, thanks for reminder.
I missed to check Mark's tree.

Regards
Dong Aisheng



From shawn.guo at linaro.org  Sat Mar 31 08:54:43 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 31 Mar 2012 20:54:43 +0800
Subject: [PATCH 2/2] regulator: rename function regulator_register_fixed
In-Reply-To: <20120331102507.GB3163@opensource.wolfsonmicro.com>
References: <1333182812-423-1-git-send-email-shawn.guo@linaro.org>
 <1333182812-423-2-git-send-email-shawn.guo@linaro.org>
 <20120331102507.GB3163@opensource.wolfsonmicro.com>
Message-ID: <20120331125440.GA2395@S2101-09.ap.freescale.net>

On Sat, Mar 31, 2012 at 11:25:08AM +0100, Mark Brown wrote:
> On Sat, Mar 31, 2012 at 04:33:32PM +0800, Shawn Guo wrote:
> 
> > Function regulator_register_fixed() is only meant for registering
> > fixed dummy regulators.  Rename it to regulator_register_fixed_dummy()
> > for the explicit meaning, so that people do not attempt to register
> > those real fixed regulators with this function.
> 
> There's no harm in using it for regulators that physically exist if
> nothing cares about any of the information it can't provide

I do not think it's practical for physical regulator to use the
function, since the function forces microvolts to be 0.

> and renaming
> it now is going to cause annoyance with cross tree issues so I'm kind of
> reluctant to apply this.  Are there any concrete problems that have been
> caused by this or was it just something you noticed when looking at
> using it yourself?

I noticed it when I was trying to use the function to register a fixed
regulator which physically exist, and it turns out that I just was
misled by the function name.

> 
> > It also removes the kernel doc for @name which is not a parameter for
> > the function at all.
> 
> This is already done, I can't remember who sent the patch off the top of
> my head.

I did not see it on regulator/for-next branch.  But it's so trivial
and I do not care much.

-- 
Regards,
Shawn


From b29396 at freescale.com  Sat Mar 31 09:26:57 2012
From: b29396 at freescale.com (Dong Aisheng)
Date: Sat, 31 Mar 2012 21:26:57 +0800
Subject: [PATCH v4 1/1] ARM: imx28: add basic dt support
Message-ID: <1333200417-11259-1-git-send-email-b29396@freescale.com>

From: Dong Aisheng <dong.aisheng at linaro.org>

This patch includes basic dt support which can boot via nfs rootfs.

Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
---
ChangeLog v3->v4:
 * update to use irq_domain_add_legacy
ChangeLog v2->v3:
 * Some minor fixes suggested by Shawn Guo
ChangeLog v1->v2:
 * Some fixes addressed Rob's review comments.
   Remove using of OF_DEV_AUXDATA.
 * Remove mac address from dts file
   Currently we use the mac address got from uboot to work.
   Will submit a p separate atch using prom_update_property to fix this
   issue for driver based on suggestions from Grant and Lothar.
 * rename mxs-dt.c to mach-mxs.c which is supposed to support mx23 dt
   too in the future.
 * add compatible string "fsl,imx28" per Sascha's suggestion
 * add more devices in dtsi file
   For those devices still not in use, set the state to "disabled"
   by default.
---
 Documentation/devicetree/bindings/arm/fsl.txt |    4 +
 arch/arm/boot/dts/imx28-evk.dts               |   34 +++
 arch/arm/boot/dts/imx28.dtsi                  |  356 +++++++++++++++++++++++++
 arch/arm/mach-mxs/Kconfig                     |   10 +
 arch/arm/mach-mxs/Makefile                    |    1 +
 arch/arm/mach-mxs/clock-mx28.c                |    4 +
 arch/arm/mach-mxs/devices/Kconfig             |    1 -
 arch/arm/mach-mxs/mach-mxs.c                  |   68 +++++
 8 files changed, 477 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx28-evk.dts
 create mode 100644 arch/arm/boot/dts/imx28.dtsi
 create mode 100644 arch/arm/mach-mxs/mach-mxs.c

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index bfbc771..fecb580 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -1,6 +1,10 @@
 Freescale i.MX Platforms Device Tree Bindings
 -----------------------------------------------
 
+i.MX28 Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx28-evk", "fsl,imx28";
+
 i.MX51 Babbage Board
 Required root node properties:
     - compatible = "fsl,imx51-babbage", "fsl,imx51";
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
new file mode 100644
index 0000000..57703ec
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+	model = "Freescale i.MX28 Evaluation Kit";
+	compatible = "fsl,imx28-evk", "fsl,imx28";
+
+	memory {
+		reg = <0x40000000 0x08000000>;
+	};
+
+	ahb at 80080000 {
+		ethernet at 800f0000 {
+			phy-mode = "rmii";
+			status = "okay";
+		};
+
+		ethernet at 800f4000 {
+			phy-mode = "rmii";
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
new file mode 100644
index 0000000..d1f4f8c
--- /dev/null
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	interrupt-parent = <&icoll>;
+
+	aliases {
+		serial0 = &duart;
+	};
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	apb at 80000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80000000 0x80000>;
+		ranges;
+
+		apbh at 80000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x80000000 0x3c900>;
+			ranges;
+
+			icoll: interrupt-controller at 80000000 {
+				compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0x80000000 0x2000>;
+			};
+
+			hsadc at 80002000 {
+				reg = <0x80002000 2000>;
+				interrupts = <13 87>;
+				status = "disabled";
+			};
+
+			dma-apbh at 80004000 {
+				reg = <0x80004000 2000>;
+				status = "disabled";
+			};
+
+			perfmon at 80006000 {
+				reg = <0x80006000 800>;
+				interrupts = <27>;
+				status = "disabled";
+			};
+
+			bch at 8000a000 {
+				reg = <0x8000a000 2000>;
+				interrupts = <41>;
+				status = "disabled";
+			};
+
+			gpmi at 8000c000 {
+				reg = <0x8000c000 2000>;
+				interrupts = <42 88>;
+				status = "disabled";
+			};
+
+			ssp at 80010000 {
+				reg = <0x80010000 2000>;
+				interrupts = <96 82>;
+				status = "disabled";
+			};
+
+			ssp at 80012000 {
+				reg = <0x80012000 2000>;
+				interrupts = <97 83>;
+				status = "disabled";
+			};
+
+			ssp at 80014000 {
+				reg = <0x80014000 2000>;
+				interrupts = <98 84>;
+				status = "disabled";
+			};
+
+			ssp at 80016000 {
+				reg = <0x80016000 2000>;
+				interrupts = <99 85>;
+				status = "disabled";
+			};
+
+			pinctrl at 80018000 {
+				reg = <0x80018000 2000>;
+				status = "disabled";
+			};
+
+			digctl at 8001c000 {
+				reg = <0x8001c000 2000>;
+				interrupts = <89>;
+				status = "disabled";
+			};
+
+			etm at 80022000 {
+				reg = <0x80022000 2000>;
+				status = "disabled";
+			};
+
+			dma-apbx at 80024000 {
+				reg = <0x80024000 2000>;
+				status = "disabled";
+			};
+
+			dcp at 80028000 {
+				reg = <0x80028000 2000>;
+				interrupts = <52 53 54>;
+				status = "disabled";
+			};
+
+			pxp at 8002a000 {
+				reg = <0x8002a000 2000>;
+				interrupts = <39>;
+				status = "disabled";
+			};
+
+			ocotp at 8002c000 {
+				reg = <0x8002c000 2000>;
+				status = "disabled";
+			};
+
+			axi-ahb at 8002e000 {
+				reg = <0x8002e000 2000>;
+				status = "disabled";
+			};
+
+			lcdif at 80030000 {
+				reg = <0x80030000 2000>;
+				interrupts = <38 86>;
+				status = "disabled";
+			};
+
+			can at 80032000 {
+				reg = <0x80032000 2000>;
+				interrupts = <8>;
+				status = "disabled";
+			};
+
+			can at 80034000 {
+				reg = <0x80034000 2000>;
+				interrupts = <9>;
+				status = "disabled";
+			};
+
+			simdbg at 8003c000 {
+				reg = <0x8003c000 200>;
+				status = "disabled";
+			};
+
+			simgpmisel at 8003c200 {
+				reg = <0x8003c200 100>;
+				status = "disabled";
+			};
+
+			simsspsel at 8003c300 {
+				reg = <0x8003c300 100>;
+				status = "disabled";
+			};
+
+			simmemsel at 8003c400 {
+				reg = <0x8003c400 100>;
+				status = "disabled";
+			};
+
+			gpiomon at 8003c500 {
+				reg = <0x8003c500 100>;
+				status = "disabled";
+			};
+
+			simenet at 8003c700 {
+				reg = <0x8003c700 100>;
+				status = "disabled";
+			};
+
+			armjtag at 8003c800 {
+				reg = <0x8003c800 100>;
+				status = "disabled";
+			};
+                };
+
+		apbx at 80040000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x80040000 0x40000>;
+			ranges;
+
+			clkctl at 80040000 {
+				reg = <0x80040000 2000>;
+				status = "disabled";
+			};
+
+			saif at 80042000 {
+				reg = <0x80042000 2000>;
+				interrupts = <59 80>;
+				status = "disabled";
+			};
+
+			power at 80044000 {
+				reg = <0x80044000 2000>;
+				status = "disabled";
+			};
+
+			saif at 80046000 {
+				reg = <0x80046000 2000>;
+				interrupts = <58 81>;
+				status = "disabled";
+			};
+
+			lradc at 80050000 {
+				reg = <0x80050000 2000>;
+				status = "disabled";
+			};
+
+			spdif at 80054000 {
+				reg = <0x80054000 2000>;
+				interrupts = <45 66>;
+				status = "disabled";
+			};
+
+			rtc at 80056000 {
+				reg = <0x80056000 2000>;
+				interrupts = <28 29>;
+				status = "disabled";
+			};
+
+			i2c at 80058000 {
+				reg = <0x80058000 2000>;
+				interrupts = <111 68>;
+				status = "disabled";
+			};
+
+			i2c at 8005a000 {
+				reg = <0x8005a000 2000>;
+				interrupts = <110 69>;
+				status = "disabled";
+			};
+
+			pwm at 80064000 {
+				reg = <0x80064000 2000>;
+				status = "disabled";
+			};
+
+			timrot at 80068000 {
+				reg = <0x80068000 2000>;
+				status = "disabled";
+			};
+
+			serial at 8006a000 {
+				reg = <0x8006a000 0x2000>;
+				interrupts = <112 70 71>;
+				status = "disabled";
+			};
+
+			serial at 8006c000 {
+				reg = <0x8006c000 0x2000>;
+				interrupts = <113 72 73>;
+				status = "disabled";
+			};
+
+			serial at 8006e000 {
+				reg = <0x8006e000 0x2000>;
+				interrupts = <114 74 75>;
+				status = "disabled";
+			};
+
+			serial at 80070000 {
+				reg = <0x80070000 0x2000>;
+				interrupts = <115 76 77>;
+				status = "disabled";
+			};
+
+			serial at 80072000 {
+				reg = <0x80072000 0x2000>;
+				interrupts = <116 78 79>;
+				status = "disabled";
+			};
+
+			duart: serial at 80074000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x80074000 0x1000>;
+				interrupts = <47>;
+			};
+
+			usbphy at 8007c000 {
+				reg = <0x8007c000 0x2000>;
+				status = "disabled";
+			};
+
+			usbphy at 8007e000 {
+				reg = <0x8007e000 0x2000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	ahb at 80080000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x80080000 0x80000>;
+		ranges;
+
+		usbctrl at 80080000 {
+			reg = <0x80080000 0x10000>;
+			status = "disabled";
+		};
+
+		usbctrl at 80090000 {
+			reg = <0x80090000 0x10000>;
+			status = "disabled";
+		};
+
+		dflpt at 800c0000 {
+			reg = <0x800c0000 0x10000>;
+			status = "disabled";
+		};
+
+		ethernet at 800f0000 {
+			compatible = "fsl,imx28-fec";
+			reg = <0x800f0000 0x4000>;
+			interrupts = <101>;
+			status = "disabled";
+		};
+
+		ethernet at 800f4000 {
+			compatible = "fsl,imx28-fec";
+			reg = <0x800f4000 0x4000>;
+			interrupts = <102>;
+			status = "disabled";
+		};
+
+		switch at 800f8000 {
+			reg = <0x800f8000 0x8000>;
+			status = "disabled";
+		};
+
+	};
+};
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c57f996..09fe0fb 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -7,16 +7,26 @@ config MXS_OCOTP
 
 config SOC_IMX23
 	bool
+	select ARM_AMBA
 	select CPU_ARM926T
 	select HAVE_PWM
 
 config SOC_IMX28
 	bool
+	select ARM_AMBA
 	select CPU_ARM926T
 	select HAVE_PWM
 
 comment "MXS platforms:"
 
+config MACH_MXS_DT
+	bool "Support MXS platforms from device tree"
+	select SOC_IMX28
+	select USE_OF
+	help
+	  Include support for Freescale MXS platforms(i.MX23 and i.MX28)
+	  using the device tree for discovery
+
 config MACH_STMP378X_DEVB
 	bool "Support STMP378x_devb Platform"
 	select SOC_IMX23
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 908bf9a..8328c45 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
 obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
 obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
 
+obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
 obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 7aa7ff8..a8b8462 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -648,6 +648,10 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
 	_REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
 	_REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
+	/* for DT */
+	_REGISTER_CLOCK("80074000.serial", NULL, uart_clk)
+	_REGISTER_CLOCK("800f0000.ethernet", NULL, fec_clk)
+	_REGISTER_CLOCK("800f4000.ethernet", NULL, fec_clk)
 };
 
 static int clk_misc_init(void)
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index b8913df..19659de 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -1,6 +1,5 @@
 config MXS_HAVE_AMBA_DUART
 	bool
-	select ARM_AMBA
 
 config MXS_HAVE_PLATFORM_AUART
 	bool
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
new file mode 100644
index 0000000..5c5cba2
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+
+static int __init mxs_icoll_add_irq_domain(struct device_node *np,
+				struct device_node *interrupt_parent)
+{
+	irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
+
+	return 0;
+}
+
+static const struct of_device_id mxs_irq_match[] __initconst = {
+	{ .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
+	{ /* sentinel */ }
+};
+
+static void __init mxs_dt_init_irq(void)
+{
+	icoll_init_irq();
+	of_irq_init(mxs_irq_match);
+}
+
+static void __init imx28_timer_init(void)
+{
+	mx28_clocks_init();
+}
+
+static struct sys_timer imx28_timer = {
+	.init = imx28_timer_init,
+};
+
+static void __init mxs_machine_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table,
+				NULL, NULL);
+}
+
+static const char *imx28_dt_compat[] __initdata = {
+	"fsl,imx28-evk",
+	"fsl,imx28",
+	NULL,
+};
+
+DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
+	.map_io		= mx28_map_io,
+	.init_irq	= mxs_dt_init_irq,
+	.timer		= &imx28_timer,
+	.init_machine	= mxs_machine_init,
+	.dt_compat	= imx28_dt_compat,
+	.restart	= mxs_restart,
+MACHINE_END
-- 
1.7.0.4




From festevam at gmail.com  Sat Mar 31 09:24:05 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sat, 31 Mar 2012 10:24:05 -0300
Subject: [PATCH] ARM: imx: fix mc9s08dz60_gpiochip_match parameter type
In-Reply-To: <1333183577-2109-1-git-send-email-shawn.guo@linaro.org>
References: <1333183577-2109-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <CAOMZO5B3W6fuQDq=WHSovtOJFOsKF0as1kJGQ5Lm9MWkh71JeA@mail.gmail.com>

Shawn,

On Sat, Mar 31, 2012 at 5:46 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> Due to the change made by commit 6e2cf65 (gpio: constify the data
> parameter to gpiochip_find()), the following compile warning is seen
> on imx_v6_v7_defconfig build.
>
> ?CC ? ? ?arch/arm/mach-imx/mach-mx35_3ds.o
> arch/arm/mach-imx/mach-mx35_3ds.c: In function ?mx35_3ds_lcd_set_power?:
> arch/arm/mach-imx/mach-mx35_3ds.c:112:5: warning: passing argument 2 of ?gpiochip_find? from incompatible pointer type [enabled by default]
> include/asm-generic/gpio.h:145:26: note: expected ?int (*)(struct gpio_chip *, const void *)? but argument is of type ?int (*)(struct gpio_chip *, void *)?
>
> Change mc9s08dz60_gpiochip_match parameter type accordingly to fix
> the warning.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

I have already sent this fix:
http://comments.gmane.org/gmane.linux.ports.arm.kernel/158438

Thanks,

Fabio Estevam


From shawn.guo at linaro.org  Sat Mar 31 09:28:16 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 31 Mar 2012 21:28:16 +0800
Subject: [PATCH] ARM: imx: fix mc9s08dz60_gpiochip_match parameter type
In-Reply-To: <CAOMZO5B3W6fuQDq=WHSovtOJFOsKF0as1kJGQ5Lm9MWkh71JeA@mail.gmail.com>
References: <1333183577-2109-1-git-send-email-shawn.guo@linaro.org>
 <CAOMZO5B3W6fuQDq=WHSovtOJFOsKF0as1kJGQ5Lm9MWkh71JeA@mail.gmail.com>
Message-ID: <CAAQ0ZWTvw4DNZF08CcE4iaDz992MhZviSxQAgr9McR3Gd8s6EQ@mail.gmail.com>

On 31 March 2012 21:24, Fabio Estevam <festevam at gmail.com> wrote:
....
> I have already sent this fix:
> http://comments.gmane.org/gmane.linux.ports.arm.kernel/158438
>
Okay, ignore mine then.

Regards,
Shawn


From broonie at opensource.wolfsonmicro.com  Sat Mar 31 09:42:15 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 31 Mar 2012 14:42:15 +0100
Subject: [PATCH] ARM: amba: adapt to regulator probe deferral change
In-Reply-To: <20120330180134.GJ22981@n2100.arm.linux.org.uk>
References: <1333115737-1654-1-git-send-email-shawn.guo@linaro.org>
 <20120330180134.GJ22981@n2100.arm.linux.org.uk>
Message-ID: <20120331134215.GA5012@opensource.wolfsonmicro.com>

On Fri, Mar 30, 2012 at 07:01:34PM +0100, Russell King - ARM Linux wrote:
> On Fri, Mar 30, 2012 at 09:55:37PM +0800, Shawn Guo wrote:
> > The commit 04bf301 (regulator: Support driver probe deferral) changes
> > regulator_get() and regulator_register() to return -EPROBE_DEFER
> > instead of -ENODEV.  Adapt amba bus driver to the change, otherwise
> > amba_probe() will fail on the platforms that do not have "vcore"
> > regulator device.

> Are you sure this is correct?  Did you read and understand the comment
> you removed?

Shawn's change is a good minimal fix for 3.4, probably the comment
should be maintained but the entire change in the regulator framework
was a change in return code so changing the return code we check for
should restore the previous behaviour for now.  Going forward we
probably want to do something else but for 3.4 this looks like the best
approach:

Reviwed-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

> What do platforms do which have AMBA devices but don't have any vcore
> regulators?

We need to change the AMBA bus so it does something better than what it
does now and work out a good way to roll this out.  The more I think
about this the less convinced I am that AMBA should have regualtor
support in the bus itself at all.

I can see a few options here:

 - Add stub vcore regulators to the code for the relevant SoCs.  This is
   tedious, annoying and defeats the point of frameworks so to me it's a
   clear non-starter.

 - Require systems which do have vcore regulators to tell AMBA about it
   when registering the devices then either have the AMBA bus suppress
   the regulator calls or tell the regulator framework about it (which
   is more idiomatic and probably easier in the long run).  This is a
   bit inelegant but should minimise the amount of work.

 - Move the vcore management from AMBA into the SoC-specific power domain
   management code for relevant SoCs.  The SoCs should know if there is a
   vcore that's supplied via a visible regulator (as opposed to power
   gating within the SoC which often has other requirements or features
   and is generally implemented via the power domain support) and this
   should integrate nicely with similar handling for clocks.

I don't know if anyone else has any better ideas?  

To me the power domain approach feels right and looking at the changelog
for the commit introducing this support that seems to be roughly the use
case.  The one actual in tree AMBA device using this stuff seems to be
the pl022 (though there don't look to be any boards with the vcore
regulator supplied) and it certainly looks like it'd fit well with this
idiom.

The current approach leaves us tied to playing init ordering games to
ensure that the regulator is available prior to the AMBA device probing.
We want to get away from relying on those since they end up breaking
down and really only work when everything is built in.  It also give us
poor error handling since we end up silently ignoring failures, for
example if the driver for a vcore regulator is not enabled or the supply
not hooked up when required on a board.

In general any patch which will just ignore errors when requesting a
regulator should be treated with suspicion.

> We're not going through the same farce that the smsc network driver has
> gone through: OMAP3430LDP remains fucked through that idiotic ill-thought
> out change (c7e963f68888, net/smsc911x: Add regulator support).  See
> http://www.arm.linux.org.uk/developer/build/result.php?type=boot&idx=99

For that board it's really very straightforward to add the required
regulators and CONFIG_REGULATOR_DUMMY will normally get things going
immediately, hopefully this is now taken care of by the latest patch
series that was floating around for that stuff?

It's one of these things where it's annoying to have to do the board
update but the update is so simple to do and the alternatives introduce
sufficient fragility and general ick to make it seem like it's the
better alternative.

In general people do need to do an audit of existing boards in the tree
when they add regulator support to an existing driver and make some
effort to at least let people know that updates are required, I did ask
for that to be done with the smsc911x change but it's apparent that this
didn't happen.

In order to reduce the amount of pain this stuff causes it's looking to
me that we should be pushing new off-SoC drivers that don't get power
from their bus to always include at least stub regulator support, that
will at least mean that if more detailed support is added in the future
we don't disrupt things too much.  One of the things I've been trying to
find time to do is adding something like what you've got for AMBA (but
with a driver specified supply list) to the driver core so that this is
as simple as possible.
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From broonie at opensource.wolfsonmicro.com  Sat Mar 31 09:45:16 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 31 Mar 2012 14:45:16 +0100
Subject: [PATCH 2/2] regulator: rename function regulator_register_fixed
In-Reply-To: <20120331125440.GA2395@S2101-09.ap.freescale.net>
References: <1333182812-423-1-git-send-email-shawn.guo@linaro.org>
 <1333182812-423-2-git-send-email-shawn.guo@linaro.org>
 <20120331102507.GB3163@opensource.wolfsonmicro.com>
 <20120331125440.GA2395@S2101-09.ap.freescale.net>
Message-ID: <20120331134515.GB5012@opensource.wolfsonmicro.com>

On Sat, Mar 31, 2012 at 08:54:43PM +0800, Shawn Guo wrote:
> On Sat, Mar 31, 2012 at 11:25:08AM +0100, Mark Brown wrote:

> > There's no harm in using it for regulators that physically exist if
> > nothing cares about any of the information it can't provide

> I do not think it's practical for physical regulator to use the
> function, since the function forces microvolts to be 0.

Yeah, but it depends if anyone actually cares what the voltage is - most
consumers never look to see what the voltage is because they have no
reason to care.  The lack of naming is more of an issue really.
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From jm at lentin.co.uk  Sat Mar 31 09:53:02 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sat, 31 Mar 2012 14:53:02 +0100
Subject: [PATCH V4 0/3] ARM: Kirkwood: Convert DNS-325 & DNS-320 to access
 nand via devicetree (was: Add support for DNS-320 and DNS-325 using
 devicetree)
Message-ID: <1333201985-2222-1-git-send-email-jm@lentin.co.uk>

Right, I've stopped being lazy and researched what the various properties
contain and documented them.

In the process I noticed that all other drivers have bank-width in bytes,
so I changed orion_nand to match. If using orion_nand without devicetree,
the width property is still in bits though. Hopefully this isn't considered too
bad? They have different names at least.

I've left out everything that has been merged into either Grant or Jason's
tree. Hopefully this was a useful thing to do.

Thanks again to everyone reviewing.

Changes since v3: Add support for DNS-320 and DNS-325 using devicetree
* Remove patches that are already merged
* Add documentation on orion_nand devicetree bindings
* Convert bank-width to be in bytes to match other properties
* Make defaults more explicit

Changes since v2: Add support for DNS-320 and DNS-325 using devicetree
* Split patches further, separating orion_nand and kirkwood changes
* dts renames: "bank-width", not "width". "okay", not "ok"
* Separate documentation out into separate patch, add references to
  partition.txt to all mtd bindings.
  
Changes since v1: Add support for DNS-320 and DNS-325 using devicetree
* Rebase against kirkwood_dt_for_3.4, removing premature devicetree ports.
* Move additions into a separate board-dnskw.c. It could be separated further
  into a board-dns320.c and board-dns325.c but it probably isn't worth it.
* s/marvell,/mrvl,/g
* Include an example dtb partition in documentation
* Copy structure of serial nodes to allow common options for NAND to be set
  in kirkwood.dtsi
* Simplifications in orion-nand.c

Jamie Lentin (3):
  mtd: Add orion_nand devicetree bindings
  kirkwood: Allow nand to be configured via. devicetree
  ARM: kirkwood: Define DNS-320/DNS-325 NAND in fdt

 .../devicetree/bindings/mtd/orion-nand.txt         |   50 ++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-dns320.dts              |   35 ++++++++++++++
 arch/arm/boot/dts/kirkwood-dns325.dts              |   35 ++++++++++++++
 arch/arm/boot/dts/kirkwood.dtsi                    |   15 ++++++-
 arch/arm/mach-kirkwood/board-dnskw.c               |   31 ------------
 arch/arm/mach-kirkwood/common.c                    |   12 +++++
 drivers/mtd/nand/orion_nand.c                      |   41 +++++++++++++++-
 7 files changed, 185 insertions(+), 34 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt

-- 
1.7.9.1



From jm at lentin.co.uk  Sat Mar 31 09:53:04 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sat, 31 Mar 2012 14:53:04 +0100
Subject: [PATCH V4 2/3] kirkwood: Allow nand to be configured via. devicetree
In-Reply-To: <1333201985-2222-1-git-send-email-jm@lentin.co.uk>
References: <1333201985-2222-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1333201985-2222-3-git-send-email-jm@lentin.co.uk>

Add default configuration for NAND, to be enabled in your board config. Ensure
clock gating is set appropriately when the NAND is enabled.

Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
Update bank-width to be in bytes

 arch/arm/boot/dts/kirkwood.dtsi |   15 ++++++++++++++-
 arch/arm/mach-kirkwood/common.c |   12 ++++++++++++
 2 files changed, 26 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 3474ef8..926528b 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -5,7 +5,7 @@
 
 	ocp at f1000000 {
 		compatible = "simple-bus";
-		ranges = <0 0xf1000000 0x1000000>;
+		ranges = <0 0xf1000000 0x4000000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
@@ -32,5 +32,18 @@
 			reg = <0x10300 0x20>;
 			interrupts = <53>;
 		};
+
+		nand at 3000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cle = <0>;
+			ale = <1>;
+			bank-width = <1>;
+			compatible = "mrvl,orion-nand";
+			reg = <0x3000000 0x400>;
+			chip-delay = <25>;
+			/* set partition map and/or chip-delay in board dts */
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index a02cae8..3ad0373 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -15,6 +15,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mtd/nand.h>
 #include <linux/dma-mapping.h>
+#include <linux/of.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -482,6 +483,9 @@ static int __init kirkwood_clock_gate(void)
 	unsigned int curr = readl(CLOCK_GATING_CTRL);
 	u32 dev, rev;
 
+#ifdef CONFIG_OF
+	struct device_node *np;
+#endif
 	kirkwood_pcie_id(&dev, &rev);
 	printk(KERN_DEBUG "Gating clock of unused units\n");
 	printk(KERN_DEBUG "before: 0x%08x\n", curr);
@@ -489,6 +493,14 @@ static int __init kirkwood_clock_gate(void)
 	/* Make sure those units are accessible */
 	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 
+#ifdef CONFIG_OF
+	np = of_find_compatible_node(NULL, NULL, "mrvl,orion-nand");
+	if (np && of_device_is_available(np)) {
+		kirkwood_clk_ctrl |= CGC_RUNIT;
+		of_node_put(np);
+	}
+#endif
+
 	/* For SATA: first shutdown the phy */
 	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
 		/* Disable PLL and IVREF */
-- 
1.7.9.1



From jm at lentin.co.uk  Sat Mar 31 09:53:03 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sat, 31 Mar 2012 14:53:03 +0100
Subject: [PATCH V4 1/3] mtd: Add orion_nand devicetree bindings
In-Reply-To: <1333201985-2222-1-git-send-email-jm@lentin.co.uk>
References: <1333201985-2222-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1333201985-2222-2-git-send-email-jm@lentin.co.uk>

Allow a NAND chip using the orion_nand driver to be described using devicetree.

Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
* Document all parameters.
* Convert bank-width to be in bytes
* Add explicit defaults for cle, ale and bank-width

 .../devicetree/bindings/mtd/orion-nand.txt         |   50 ++++++++++++++++++++
 drivers/mtd/nand/orion_nand.c                      |   41 +++++++++++++++-
 2 files changed, 89 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt
new file mode 100644
index 0000000..b2356b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/orion-nand.txt
@@ -0,0 +1,50 @@
+NAND support for Marvell Orion SoC platforms
+
+Required properties:
+- compatible : "mrvl,orion-nand".
+- reg : Base physical address of the NAND and length of memory mapped
+	region
+
+Optional properties:
+- cle : Address line number connected to CLE. Default is 0
+- ale : Address line number connected to ALE. Default is 1
+- bank-width : Width in bytes of the device. Default is 1
+- chip-delay : Chip dependent delay for transferring data from array to read
+               registers in usecs
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+nand at f4000000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	cle = <0>;
+	ale = <1>;
+	bank-width = <1>;
+	chip-delay = <25>;
+	compatible = "mrvl,orion-nand";
+	reg = <0xf4000000 0x400>;
+
+	partition at 0 {
+		label = "u-boot";
+		reg = <0x0000000 0x100000>;
+		read-only;
+	};
+
+	partition at 100000 {
+		label = "uImage";
+		reg = <0x0100000 0x200000>;
+	};
+
+	partition at 300000 {
+		label = "dtb";
+		reg = <0x0300000 0x100000>;
+	};
+
+	partition at 400000 {
+		label = "root";
+		reg = <0x0400000 0x7d00000>;
+	};
+};
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index 29f505a..dd3ece8 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -13,6 +13,7 @@
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
@@ -74,11 +75,13 @@ static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 static int __init orion_nand_probe(struct platform_device *pdev)
 {
 	struct mtd_info *mtd;
+	struct mtd_part_parser_data ppdata = {};
 	struct nand_chip *nc;
 	struct orion_nand_data *board;
 	struct resource *res;
 	void __iomem *io_base;
 	int ret = 0;
+	u32 val = 0;
 
 	nc = kzalloc(sizeof(struct nand_chip) + sizeof(struct mtd_info), GFP_KERNEL);
 	if (!nc) {
@@ -101,7 +104,32 @@ static int __init orion_nand_probe(struct platform_device *pdev)
 		goto no_res;
 	}
 
-	board = pdev->dev.platform_data;
+	if (pdev->dev.of_node) {
+		board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data),
+					GFP_KERNEL);
+		if (!board) {
+			printk(KERN_ERR "orion_nand: failed to allocate board structure.\n");
+			ret = -ENOMEM;
+			goto no_res;
+		}
+		if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
+			board->cle = (u8)val;
+		else
+			board->cle = 0;
+		if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
+			board->ale = (u8)val;
+		else
+			board->ale = 1;
+		if (!of_property_read_u32(pdev->dev.of_node,
+						"bank-width", &val))
+			board->width = (u8)val * 8;
+		else
+			board->width = 8;
+		if (!of_property_read_u32(pdev->dev.of_node,
+						"chip-delay", &val))
+			board->chip_delay = (u8)val;
+	} else
+		board = pdev->dev.platform_data;
 
 	mtd->priv = nc;
 	mtd->owner = THIS_MODULE;
@@ -129,7 +157,8 @@ static int __init orion_nand_probe(struct platform_device *pdev)
 	}
 
 	mtd->name = "orion_nand";
-	ret = mtd_device_parse_register(mtd, NULL, 0,
+	ppdata.of_node = pdev->dev.of_node;
+	ret = mtd_device_parse_register(mtd, NULL, &ppdata,
 			board->parts, board->nr_parts);
 	if (ret) {
 		nand_release(mtd);
@@ -161,11 +190,19 @@ static int __devexit orion_nand_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id orion_nand_of_match_table[] = {
+	{ .compatible = "mrvl,orion-nand", },
+	{},
+};
+#endif
+
 static struct platform_driver orion_nand_driver = {
 	.remove		= __devexit_p(orion_nand_remove),
 	.driver		= {
 		.name	= "orion_nand",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(orion_nand_of_match_table),
 	},
 };
 
-- 
1.7.9.1



From jm at lentin.co.uk  Sat Mar 31 09:53:05 2012
From: jm at lentin.co.uk (Jamie Lentin)
Date: Sat, 31 Mar 2012 14:53:05 +0100
Subject: [PATCH V4 3/3] ARM: kirkwood: Define DNS-320/DNS-325 NAND in fdt
In-Reply-To: <1333201985-2222-1-git-send-email-jm@lentin.co.uk>
References: <1333201985-2222-1-git-send-email-jm@lentin.co.uk>
Message-ID: <1333201985-2222-4-git-send-email-jm@lentin.co.uk>

Use devicetree to define NAND partitions. Use D-link partition scheme by
default, to be vaguely compatible with their userland.

Acked-by: Arnd Bergmann <arnd at arndb.de>
Acked-by: Jason Cooper <jason at lakedaemon.net>
Signed-off-by: Jamie Lentin <jm at lentin.co.uk>
---
Unchanged since V3

 arch/arm/boot/dts/kirkwood-dns320.dts |   35 +++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/kirkwood-dns325.dts |   35 +++++++++++++++++++++++++++++++++
 arch/arm/mach-kirkwood/board-dnskw.c  |   31 -----------------------------
 3 files changed, 70 insertions(+), 31 deletions(-)

diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index 78c834f..dc09a73 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -25,5 +25,40 @@
 			clock-frequency = <166666667>;
 			status = "okay";
 		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x0100000 0x500000>;
+			};
+
+			partition at 600000 {
+				label = "ramdisk";
+				reg = <0x0600000 0x500000>;
+			};
+
+			partition at b00000 {
+				label = "image";
+				reg = <0x0b00000 0x6600000>;
+			};
+
+			partition at 7100000 {
+				label = "mini firmware";
+				reg = <0x7100000 0xa00000>;
+			};
+
+			partition at 7b00000 {
+				label = "config";
+				reg = <0x7b00000 0x500000>;
+			};
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index 23241ab..c2a5562 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -20,5 +20,40 @@
 			clock-frequency = <200000000>;
 			status = "okay";
 		};
+
+		nand at 3000000 {
+			status = "okay";
+
+			partition at 0 {
+				label = "u-boot";
+				reg = <0x0000000 0x100000>;
+				read-only;
+			};
+
+			partition at 100000 {
+				label = "uImage";
+				reg = <0x0100000 0x500000>;
+			};
+
+			partition at 600000 {
+				label = "ramdisk";
+				reg = <0x0600000 0x500000>;
+			};
+
+			partition at b00000 {
+				label = "image";
+				reg = <0x0b00000 0x6600000>;
+			};
+
+			partition at 7100000 {
+				label = "mini firmware";
+				reg = <0x7100000 0xa00000>;
+			};
+
+			partition at 7b00000 {
+				label = "config";
+				reg = <0x7b00000 0x500000>;
+			};
+		};
 	};
 };
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 7cb7f6a..dc4e80a 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -23,7 +23,6 @@
 #include <linux/gpio_keys.h>
 #include <linux/gpio-fan.h>
 #include <linux/leds.h>
-#include <linux/mtd/physmap.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,35 +31,6 @@
 #include "common.h"
 #include "mpp.h"
 
-static struct mtd_partition dnskw_nand_parts[] = {
-	{
-		.name		= "u-boot",
-		.offset		= 0,
-		.size		= SZ_1M,
-		.mask_flags	= MTD_WRITEABLE
-	}, {
-		.name		= "uImage",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	}, {
-		.name		= "ramdisk",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	}, {
-		.name		= "image",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 102 * SZ_1M
-	}, {
-		.name		= "mini firmware",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 10 * SZ_1M
-	}, {
-		.name		= "config",
-		.offset		= MTDPART_OFS_NXTBLK,
-		.size		= 5 * SZ_1M
-	},
-};
-
 static struct mv643xx_eth_platform_data dnskw_ge00_data = {
 	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
 };
@@ -272,7 +242,6 @@ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
 void __init dnskw_init(void)
 {
 	kirkwood_mpp_conf(dnskw_mpp_config);
-	kirkwood_nand_init(ARRAY_AND_SIZE(dnskw_nand_parts), 25);
 
 	kirkwood_ehci_init();
 	kirkwood_ge00_init(&dnskw_ge00_data);
-- 
1.7.9.1



From thierry.reding at avionic-design.de  Sat Mar 31 10:30:21 2012
From: thierry.reding at avionic-design.de (Thierry Reding)
Date: Sat, 31 Mar 2012 16:30:21 +0200
Subject: [PATCH v5 04/16] pwm: Add table-based lookup for static mappings
In-Reply-To: <20120330103840.GB961@avionic-0098.mockup.avionic-design.de>
References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de>
 <1332945238-14897-5-git-send-email-thierry.reding@avionic-design.de>
 <20120329220342.GK4153@opensource.wolfsonmicro.com>
 <20120330050641.GA21823@avionic-0098.mockup.avionic-design.de>
 <20120330101800.GD21950@opensource.wolfsonmicro.com>
 <20120330103840.GB961@avionic-0098.mockup.avionic-design.de>
Message-ID: <20120331143021.GA18382@avionic-0098.mockup.avionic-design.de>

* Thierry Reding wrote:
> * Mark Brown wrote:
> > On Fri, Mar 30, 2012 at 07:06:41AM +0200, Thierry Reding wrote:
> > > * Mark Brown wrote:
> > 
> > > > The clock and regulator APIs namespace the consumers by struct device -
> > > > might this not be sensible here?  pwm_get() does already take the device
> > > > as an argument.  It'd feel safer, and for example there's plenty of
> > > > phones out there with two backlit displays...
> > 
> > > That's actually how this is supposed to work. "pwm-backlight" in the above
> > > case is matched against the name of the struct device that you pass in to
> > > pwm_get(). The only difference, at least as far as I can tell, to the clock
> > > and regulator APIs is that a second name is not listed explicitly in the
> > > lookup table.
> > 
> > Both clock and regulator APIs map (source) -> (dev, name).  This only
> > has a mapping (source) -> (dev).
> > 
> > > So compared with the clock and regulator APIs it doesn't make too much sense
> > > to pass both the struct device and the name to pwm_get() because it will
> > > match the device name against the consumer name in the lookup table first and
> > > only use the passed name if no match was found.
> > 
> > This is different to what the clock and regulator APIs do - they look up
> > the name in the context of the struct device.  This is because...
> > 
> > > In case you have two backlight devices I would expect the following to work:
> > 
> > > 	static struct pwm_lookup board_pwm_lookup[] = {
> > > 		PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight.0"),
> > > 		PWM_LOOKUP("tegra-pwm", 1, "pwm-backlight.1"),
> > > 	};
> > 
> > ...if a single device uses more than one PWM then the above scheme won't
> > work - unless I'm missing something?
> 
> Right, now it makes more sense. So basically if I have a single device using
> two PWM devices, then I'll need to have something like this:
> 
> 	static struct pwm_lookup board_pwm_lookup[] = {
> 		PWM_LOOKUP("tegra-pwm", 0, "pwm-foo.0", "bar"),
> 		PWM_LOOKUP("tegra-pwm", 1, "pwm-foo.0", "baz"),
> 	};
> 
> And then of course I'll need to have a second field by which the PWM device
> can be identified. Good, I'll fix that up for the next round.

I've been thinking about this some more, and I can see this becoming a little
problem with the DT bindings because the unified pwm_get() always requests
the first PWM specified in the "pwms" property.

The best solution that I could come up with is to not pass the index into the
of_pwm_request() function but rather forward the consumer name as passed into
pwm_get(). The of_pwm_request() could use the "pwm-names" property to do a
reverse lookup of the index and request that. One good thing about that would
be that I no longer need to export the of_pwm_request() function. The "bad"
thing is that it'll make the "pwm-names" property mandatory if more than a
single PWM is requested.

Does that sound reasonable?

Thierry
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From shijie8 at gmail.com  Sat Mar 31 22:36:57 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Sat, 31 Mar 2012 22:36:57 -0400
Subject: [PATCH] mtd/gpmi : do not include the mxs.h
Message-ID: <1333247817-18472-1-git-send-email-shijie8@gmail.com>

The mxs.h does not exit in the mx6q.
So rewrite the __mxs_clrl()/__mxs_setl() and remove the mxs.h.

Signed-off-by: Huang Shijie <shijie8 at gmail.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 85e6071..649d459 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -21,7 +21,6 @@
 #include <linux/mtd/gpmi-nand.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
-#include <mach/mxs.h>
 
 #include "gpmi-nand.h"
 #include "gpmi-regs.h"
@@ -37,6 +36,8 @@ struct timing_threshod timing_default_threshold = {
 	.max_dll_delay_in_ns         = 16,
 };
 
+#define MXS_SET_ADDR		0x4
+#define MXS_CLR_ADDR		0x8
 /*
  * Clear the bit and poll it cleared.  This is usually called with
  * a reset address and mask being either SFTRST(bit 31) or CLKGATE
@@ -47,7 +48,7 @@ static int clear_poll_bit(void __iomem *addr, u32 mask)
 	int timeout = 0x400;
 
 	/* clear the bit */
-	__mxs_clrl(mask, addr);
+	writel(mask, addr + MXS_CLR_ADDR);
 
 	/*
 	 * SFTRST needs 3 GPMI clocks to settle, the reference manual
@@ -92,11 +93,11 @@ static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
 		goto error;
 
 	/* clear CLKGATE */
-	__mxs_clrl(MODULE_CLKGATE, reset_addr);
+	writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
 
 	if (!just_enable) {
 		/* set SFTRST to reset the block */
-		__mxs_setl(MODULE_SFTRST, reset_addr);
+		writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR);
 		udelay(1);
 
 		/* poll CLKGATE becoming set */
-- 
1.7.4.4



From linux at arm.linux.org.uk  Sat Mar 31 10:35:39 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 31 Mar 2012 15:35:39 +0100
Subject: [PATCH] ARM: amba: adapt to regulator probe deferral change
In-Reply-To: <20120331134215.GA5012@opensource.wolfsonmicro.com>
References: <1333115737-1654-1-git-send-email-shawn.guo@linaro.org>
 <20120330180134.GJ22981@n2100.arm.linux.org.uk>
 <20120331134215.GA5012@opensource.wolfsonmicro.com>
Message-ID: <20120331143539.GB26661@n2100.arm.linux.org.uk>

On Sat, Mar 31, 2012 at 02:42:15PM +0100, Mark Brown wrote:
> We need to change the AMBA bus so it does something better than what it
> does now and work out a good way to roll this out.  The more I think
> about this the less convinced I am that AMBA should have regualtor
> support in the bus itself at all.

How else does it power up the peripheral to read out the IDs?  You can't
bind a driver until you've read the ID, which implies that the bus layer
needs to have regulator support to turn the power on.


From paulmck at linux.vnet.ibm.com  Sat Mar 31 12:33:21 2012
From: paulmck at linux.vnet.ibm.com (Paul E. McKenney)
Date: Sun, 1 Apr 2012 00:33:21 +0800
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
Message-ID: <20120331163321.GA15809@linux.vnet.ibm.com>

Although there have been numerous complaints about the complexity of
parallel programming (especially over the past 5-10 years), the plain
truth is that the incremental complexity of parallel programming over
that of sequential programming is not as large as is commonly believed.
Despite that you might have heard, the mind-numbing complexity of modern
computer systems is not due so much to there being multiple CPUs, but
rather to there being any CPUs at all.  In short, for the ultimate in
computer-system simplicity, the optimal choice is NR_CPUS=0.

This commit therefore limits kernel builds to zero CPUs.  This change
has the beneficial side effect of rendering all kernel bugs harmless.
Furthermore, this commit enables additional beneficial changes, for
example, the removal of those parts of the kernel that are not needed
when there are zero CPUs.

Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
Reviewed-by: Thomas Gleixner <tglx at linutronix.de>
---

 alpha/Kconfig                     |   11 ++++++-----
 arm/Kconfig                       |    6 +++---
 blackfin/Kconfig                  |    3 ++-
 hexagon/Kconfig                   |    9 +++++----
 ia64/Kconfig                      |    9 +++++----
 m32r/Kconfig                      |   10 ++++++----
 mips/Kconfig                      |   21 +++++++++++----------
 mn10300/Kconfig                   |    3 ++-
 parisc/Kconfig                    |    6 +++---
 powerpc/platforms/Kconfig.cputype |    8 ++++----
 s390/Kconfig                      |   12 +++++++-----
 sh/Kconfig                        |   11 ++++++-----
 sparc/Kconfig                     |    8 ++++----
 tile/Kconfig                      |    9 +++++----
 x86/Kconfig                       |   16 +++++++++-------
 15 files changed, 78 insertions(+), 64 deletions(-)

diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 56a4df9..1766b4a 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -541,14 +541,15 @@ config HAVE_DEC_LOCK
 	default y
 
 config NR_CPUS
-	int "Maximum number of CPUs (2-32)"
-	range 2 32
+	int "Maximum number of CPUs (0-0)"
+	range 0 0
 	depends on SMP
-	default "32" if ALPHA_GENERIC || ALPHA_MARVEL
-	default "4" if !ALPHA_GENERIC && !ALPHA_MARVEL
+	default "0" if ALPHA_GENERIC || ALPHA_MARVEL
+	default "0" if !ALPHA_GENERIC && !ALPHA_MARVEL
 	help
 	  MARVEL support can handle a maximum of 32 CPUs, all the others
-          with working support have a maximum of 4 CPUs.
+          with working support have a maximum of 4 CPUs.  But why take
+	  chances?  Just stick with zero CPUs.
 
 config ARCH_DISCONTIGMEM_ENABLE
 	bool "Discontiguous Memory Support (EXPERIMENTAL)"
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a48aecc..1f07a3a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1551,10 +1551,10 @@ config PAGE_OFFSET
 	default 0xC0000000
 
 config NR_CPUS
-	int "Maximum number of CPUs (2-32)"
-	range 2 32
+	int "Maximum number of CPUs (0-0)"
+	range 0 0
 	depends on SMP
-	default "4"
+	default "0"
 
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index abe5a9e..6a78549 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -241,7 +241,8 @@ config SMP
 config NR_CPUS
 	int
 	depends on SMP
-	default 2 if BF561
+	range 0 0
+	default 0 if BF561
 
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs"
diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig
index 9059e39..daab009 100644
--- a/arch/hexagon/Kconfig
+++ b/arch/hexagon/Kconfig
@@ -158,13 +158,14 @@ config SMP
 
 config NR_CPUS
 	int "Maximum number of CPUs" if SMP
-	range 2 6 if SMP
-	default "1" if !SMP
-	default "6" if SMP
+	range 0 0 if SMP
+	default "0" if !SMP
+	default "0" if SMP
 	---help---
 	  This allows you to specify the maximum number of CPUs which this
 	  kernel will support.  The maximum supported value is 6 and the
-	  minimum value which makes sense is 2.
+	  minimum value which makes sense is 2.  But a limit of zero is
+	  so much safer!
 
 	  This is purely to save memory - each supported CPU adds
 	  approximately eight kilobytes to the kernel image.
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index bd72669..fea0e6d 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -373,16 +373,17 @@ config SMP
 	  If you don't know what to do here, say N.
 
 config NR_CPUS
-	int "Maximum number of CPUs (2-4096)"
-	range 2 4096
+	int "Maximum number of CPUs (0-0)"
+	range 0 0
 	depends on SMP
-	default "4096"
+	default "0"
 	help
 	  You should set this to the number of CPUs in your system, but
 	  keep in mind that a kernel compiled for, e.g., 2 CPUs will boot but
 	  only use 2 CPUs on a >2 CPU system.  Setting this to a value larger
 	  than 64 will cause the use of a CPU mask array, causing a small
-	  performance hit.
+	  performance hit.  And setting it larger than zero risks all
+	  manner of software bugs, so we just play it safe.
 
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index ef80a65..68b9e88 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -300,14 +300,16 @@ config CHIP_M32700_TS1
 	default n
 
 config NR_CPUS
-	int "Maximum number of CPUs (2-32)"
-	range 2 32
+	int "Maximum number of CPUs (0-0)"
+	range 0 0
 	depends on SMP
-	default "2"
+	default "0"
 	help
 	  This allows you to specify the maximum number of CPUs which this
 	  kernel will support.  The maximum supported value is 32 and the
-	  minimum value which makes sense is 2.
+	  minimum value which makes sense is 2.  Zero may not make sense,
+	  but given that there is much in this world that does not make
+	  sense, zero it is!
 
 	  This is purely to save memory - each supported CPU adds
 	  approximately eight kilobytes to the kernel image.
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5ab6e89..3d7d06c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2192,16 +2192,16 @@ config NR_CPUS_DEFAULT_64
 	bool
 
 config NR_CPUS
-	int "Maximum number of CPUs (2-64)"
-	range 1 64 if NR_CPUS_DEFAULT_1
+	int "Maximum number of CPUs (0-0)"
+	range 0 0 if NR_CPUS_DEFAULT_1
 	depends on SMP
-	default "1" if NR_CPUS_DEFAULT_1
-	default "2" if NR_CPUS_DEFAULT_2
-	default "4" if NR_CPUS_DEFAULT_4
-	default "8" if NR_CPUS_DEFAULT_8
-	default "16" if NR_CPUS_DEFAULT_16
-	default "32" if NR_CPUS_DEFAULT_32
-	default "64" if NR_CPUS_DEFAULT_64
+	default "0" if NR_CPUS_DEFAULT_1
+	default "0" if NR_CPUS_DEFAULT_2
+	default "0" if NR_CPUS_DEFAULT_4
+	default "0" if NR_CPUS_DEFAULT_8
+	default "0" if NR_CPUS_DEFAULT_16
+	default "0" if NR_CPUS_DEFAULT_32
+	default "0" if NR_CPUS_DEFAULT_64
 	help
 	  This allows you to specify the maximum number of CPUs which this
 	  kernel will support.  The maximum supported value is 32 for 32-bit
@@ -2212,7 +2212,8 @@ config NR_CPUS
 	  This is purely to save memory - each supported CPU adds
 	  approximately eight kilobytes to the kernel image.  For best
 	  performance should round up your number of processors to the next
-	  power of two.
+	  power of two.  And just think how much more memory we will
+	  save by setting the limit to zero!
 
 source "kernel/time/Kconfig"
 
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 8f1c40d..85fc112 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -201,7 +201,8 @@ config SMP
 config NR_CPUS
 	int
 	depends on SMP
-	default "2"
+	range 0 0
+	default "0"
 
 source "kernel/Kconfig.preempt"
 
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 242a1b7..358eaf8 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -254,10 +254,10 @@ config HPUX
 	depends on !64BIT
 
 config NR_CPUS
-	int "Maximum number of CPUs (2-32)"
-	range 2 32
+	int "Maximum number of CPUs (0-0)"
+	range 0 0
 	depends on SMP
-	default "32"
+	default "0"
 
 endmenu
 
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 425db18..5e607e0 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -356,11 +356,11 @@ config SMP
 	  If you don't know what to do here, say N.
 
 config NR_CPUS
-	int "Maximum number of CPUs (2-8192)"
-	range 2 8192
+	int "Maximum number of CPUs (0-0)"
+	range 0 0
 	depends on SMP
-	default "32" if PPC64
-	default "4"
+	default "0" if PPC64
+	default "0"
 
 config NOT_COHERENT_CACHE
 	bool
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index d172758..f9bc067 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -169,15 +169,17 @@ config SMP
 	  Even if you don't know what to do here, say Y.
 
 config NR_CPUS
-	int "Maximum number of CPUs (2-64)"
-	range 2 64
+	int "Maximum number of CPUs (0-0)"
+	range 0 0
 	depends on SMP
-	default "32" if !64BIT
-	default "64" if 64BIT
+	default "0" if !64BIT
+	default "0" if 64BIT
 	help
 	  This allows you to specify the maximum number of CPUs which this
 	  kernel will support.  The maximum supported value is 64 and the
-	  minimum value which makes sense is 2.
+	  minimum value which makes sense is 2.  The minimal value that
+	  makes sense might well be 2, but we all know that the only
+	  -sane- value is zero!
 
 	  This is purely to save memory - each supported CPU adds
 	  approximately sixteen kilobytes to the kernel image.
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 713fb58..5ddc7c0 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -705,18 +705,19 @@ config SMP
 	  If you don't know what to do here, say N.
 
 config NR_CPUS
-	int "Maximum number of CPUs (2-32)"
-	range 2 32
+	int "Maximum number of CPUs (0-0)"
+	range 0 0
 	depends on SMP
-	default "4" if CPU_SUBTYPE_SHX3
-	default "2"
+	default "0" if CPU_SUBTYPE_SHX3
+	default "0"
 	help
 	  This allows you to specify the maximum number of CPUs which this
 	  kernel will support.  The maximum supported value is 32 and the
 	  minimum value which makes sense is 2.
 
 	  This is purely to save memory - each supported CPU adds
-	  approximately eight kilobytes to the kernel image.
+	  approximately eight kilobytes to the kernel image.  Debloating
+	  is the way, NR_CPUS to zero today!!!
 
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index ca5580e..0de9f0f 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -177,10 +177,10 @@ config SMP
 config NR_CPUS
 	int "Maximum number of CPUs"
 	depends on SMP
-	range 2 32 if SPARC32
-	range 2 1024 if SPARC64
-	default 32 if SPARC32
-	default 64 if SPARC64
+	range 0 0 if SPARC32
+	range 0 0 if SPARC64
+	default 0 if SPARC32
+	default 0 if SPARC64
 
 source kernel/Kconfig.hz
 
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 11270ca..a05112c 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -126,14 +126,15 @@ source "init/Kconfig"
 menu "Tilera-specific configuration"
 
 config NR_CPUS
-	int "Maximum number of tiles (2-255)"
-	range 2 255
+	int "Maximum number of tiles (0-0)"
+	range 0 0
 	depends on SMP
-	default "64"
+	default "0"
 	---help---
 	  Building with 64 is the recommended value, but a slightly
 	  smaller kernel memory footprint results from using a smaller
-	  value on chips with fewer tiles.
+	  value on chips with fewer tiles.  To minimize both memory
+	  footprint and bugs, use zero and only zero.
 
 source "kernel/time/Kconfig"
 
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5bed94e..a6977f2 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -773,19 +773,21 @@ config MAXSMP
 
 config NR_CPUS
 	int "Maximum number of CPUs" if SMP && !MAXSMP
-	range 2 8 if SMP && X86_32 && !X86_BIGSMP
-	range 2 512 if SMP && !MAXSMP
-	default "1" if !SMP
-	default "4096" if MAXSMP
-	default "32" if SMP && (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP || X86_ES7000)
-	default "8" if SMP
+	range 0 0 if SMP && X86_32 && !X86_BIGSMP
+	range 0 0 if SMP && !MAXSMP
+	default "0" if !SMP
+	default "0" if MAXSMP
+	default "0" if SMP && (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP || X86_ES7000)
+	default "0" if SMP
 	---help---
 	  This allows you to specify the maximum number of CPUs which this
 	  kernel will support.  The maximum supported value is 512 and the
 	  minimum value which makes sense is 2.
 
 	  This is purely to save memory - each supported CPU adds
-	  approximately eight kilobytes to the kernel image.
+	  approximately eight kilobytes to the kernel image.  But
+	  the first supported CPU brings a lot of bugs with it, so
+	  for ultimate reliability, set the number of CPUs to zero.
 
 config SCHED_SMT
 	bool "SMT (Hyperthreading) scheduler support"



From geert at linux-m68k.org  Sat Mar 31 12:40:30 2012
From: geert at linux-m68k.org (Geert Uytterhoeven)
Date: Sat, 31 Mar 2012 18:40:30 +0200
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
In-Reply-To: <20120331163321.GA15809@linux.vnet.ibm.com>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
Message-ID: <CAMuHMdWTB+_AtqM6JixY=Oo_zmzX_dNxnivpARBYSbPJzp4t6A@mail.gmail.com>

Hi Paul,

On Sat, Mar 31, 2012 at 18:33, Paul E. McKenney
<paulmck at linux.vnet.ibm.com> wrote:
> Although there have been numerous complaints about the complexity of
> parallel programming (especially over the past 5-10 years), the plain
> truth is that the incremental complexity of parallel programming over
> that of sequential programming is not as large as is commonly believed.
> Despite that you might have heard, the mind-numbing complexity of modern
> computer systems is not due so much to there being multiple CPUs, but
> rather to there being any CPUs at all. ?In short, for the ultimate in
> computer-system simplicity, the optimal choice is NR_CPUS=0.
>
> This commit therefore limits kernel builds to zero CPUs. ?This change
> has the beneficial side effect of rendering all kernel bugs harmless.
> Furthermore, this commit enables additional beneficial changes, for
> example, the removal of those parts of the kernel that are not needed
> when there are zero CPUs.
>
> Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> Reviewed-by: Thomas Gleixner <tglx at linutronix.de>
> ---
>
> ?alpha/Kconfig ? ? ? ? ? ? ? ? ? ? | ? 11 ++++++-----
> ?arm/Kconfig ? ? ? ? ? ? ? ? ? ? ? | ? ?6 +++---
> ?blackfin/Kconfig ? ? ? ? ? ? ? ? ?| ? ?3 ++-
> ?hexagon/Kconfig ? ? ? ? ? ? ? ? ? | ? ?9 +++++----
> ?ia64/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? ?9 +++++----
> ?m32r/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? 10 ++++++----
> ?mips/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? 21 +++++++++++----------
> ?mn10300/Kconfig ? ? ? ? ? ? ? ? ? | ? ?3 ++-
> ?parisc/Kconfig ? ? ? ? ? ? ? ? ? ?| ? ?6 +++---
> ?powerpc/platforms/Kconfig.cputype | ? ?8 ++++----
> ?s390/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? 12 +++++++-----
> ?sh/Kconfig ? ? ? ? ? ? ? ? ? ? ? ?| ? 11 ++++++-----
> ?sparc/Kconfig ? ? ? ? ? ? ? ? ? ? | ? ?8 ++++----
> ?tile/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? ?9 +++++----
> ?x86/Kconfig ? ? ? ? ? ? ? ? ? ? ? | ? 16 +++++++++-------
> ?15 files changed, 78 insertions(+), 64 deletions(-)

You forgot to fix half of the architectures, a.o. m68k?

Gr{oetje,eeting}s,

? ? ? ? ? ? ? ? ? ? ? ? Geert (still at GMT+2)

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
? ? ? ? ? ? ? ? ? ? ? ? ? ?? ?? -- Linus Torvalds


From broonie at opensource.wolfsonmicro.com  Sat Mar 31 12:44:53 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 31 Mar 2012 17:44:53 +0100
Subject: [PATCH] ARM: ux300: Fix unimplementable regulation constraints
Message-ID: <1333212293-6287-1-git-send-email-broonie@opensource.wolfsonmicro.com>

It doesn't make sense to grant permission to change the status of a
regulator that is also set as always on and similarly it doesn't make
sense to allow a driver to change the voltage of a regulator which can
only be set to a single voltage.

Signed-off-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
---
 arch/arm/mach-u300/i2c.c |    9 +--------
 1 files changed, 1 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index a38f802..cb04bd6 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
 				.min_uV = 1800000,
 				.max_uV = 1800000,
 				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_VOLTAGE |
-				REGULATOR_CHANGE_STATUS,
 				.always_on = 1,
 				.boot_on = 1,
 			},
@@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
 				.min_uV = 2500000,
 				.max_uV = 2500000,
 				.valid_modes_mask = REGULATOR_MODE_NORMAL,
-				.valid_ops_mask =
-				REGULATOR_CHANGE_VOLTAGE |
-				REGULATOR_CHANGE_STATUS,
 				.always_on = 1,
 				.boot_on = 1,
 			},
@@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = {
 				.max_uV = 1800000,
 				.valid_modes_mask = REGULATOR_MODE_NORMAL,
 				.valid_ops_mask =
-				REGULATOR_CHANGE_VOLTAGE |
-				REGULATOR_CHANGE_STATUS,
+				REGULATOR_CHANGE_VOLTAGE,
 				.always_on = 1,
 				.boot_on = 1,
 			},
-- 
1.7.9.1



From broonie at opensource.wolfsonmicro.com  Sat Mar 31 12:53:02 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 31 Mar 2012 17:53:02 +0100
Subject: [PATCH] ARM: amba: adapt to regulator probe deferral change
In-Reply-To: <20120331143539.GB26661@n2100.arm.linux.org.uk>
References: <1333115737-1654-1-git-send-email-shawn.guo@linaro.org>
 <20120330180134.GJ22981@n2100.arm.linux.org.uk>
 <20120331134215.GA5012@opensource.wolfsonmicro.com>
 <20120331143539.GB26661@n2100.arm.linux.org.uk>
Message-ID: <20120331165301.GC5012@opensource.wolfsonmicro.com>

On Sat, Mar 31, 2012 at 03:35:39PM +0100, Russell King - ARM Linux wrote:
> On Sat, Mar 31, 2012 at 02:42:15PM +0100, Mark Brown wrote:

> > We need to change the AMBA bus so it does something better than what it
> > does now and work out a good way to roll this out.  The more I think
> > about this the less convinced I am that AMBA should have regualtor
> > support in the bus itself at all.

> How else does it power up the peripheral to read out the IDs?  You can't
> bind a driver until you've read the ID, which implies that the bus layer
> needs to have regulator support to turn the power on.

Like I said further down my mail it seems like any systems which do have
individual regulators for the AMBA devices probably ought to be managing
this via power domain code rather than by going direct to the regulator
API.  If actual regulators are required the power domain code for the
platform would be responsible for doing that rather than AMBA itself but
for most SoCs it's likely to not go through the regulator API if there's
any sort of gating support at all.

It's possible I'm misreading this as I'm not terribly familiar with AMBA
but based on what I do know plus the changelog for the patch introducing
it and the one driver that manages vcore at runtime it really does look
like what's going on.
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From paulmck at linux.vnet.ibm.com  Sat Mar 31 12:54:01 2012
From: paulmck at linux.vnet.ibm.com (Paul E. McKenney)
Date: Sat, 31 Mar 2012 09:54:01 -0700
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
In-Reply-To: <CAMuHMdWTB+_AtqM6JixY=Oo_zmzX_dNxnivpARBYSbPJzp4t6A@mail.gmail.com>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
 <CAMuHMdWTB+_AtqM6JixY=Oo_zmzX_dNxnivpARBYSbPJzp4t6A@mail.gmail.com>
Message-ID: <20120331165401.GD2450@linux.vnet.ibm.com>

On Sat, Mar 31, 2012 at 06:40:30PM +0200, Geert Uytterhoeven wrote:
> Hi Paul,
> 
> On Sat, Mar 31, 2012 at 18:33, Paul E. McKenney
> <paulmck at linux.vnet.ibm.com> wrote:
> > Although there have been numerous complaints about the complexity of
> > parallel programming (especially over the past 5-10 years), the plain
> > truth is that the incremental complexity of parallel programming over
> > that of sequential programming is not as large as is commonly believed.
> > Despite that you might have heard, the mind-numbing complexity of modern
> > computer systems is not due so much to there being multiple CPUs, but
> > rather to there being any CPUs at all. ?In short, for the ultimate in
> > computer-system simplicity, the optimal choice is NR_CPUS=0.
> >
> > This commit therefore limits kernel builds to zero CPUs. ?This change
> > has the beneficial side effect of rendering all kernel bugs harmless.
> > Furthermore, this commit enables additional beneficial changes, for
> > example, the removal of those parts of the kernel that are not needed
> > when there are zero CPUs.
> >
> > Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> > Reviewed-by: Thomas Gleixner <tglx at linutronix.de>
> > ---
> >
> > ?alpha/Kconfig ? ? ? ? ? ? ? ? ? ? | ? 11 ++++++-----
> > ?arm/Kconfig ? ? ? ? ? ? ? ? ? ? ? | ? ?6 +++---
> > ?blackfin/Kconfig ? ? ? ? ? ? ? ? ?| ? ?3 ++-
> > ?hexagon/Kconfig ? ? ? ? ? ? ? ? ? | ? ?9 +++++----
> > ?ia64/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? ?9 +++++----
> > ?m32r/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? 10 ++++++----
> > ?mips/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? 21 +++++++++++----------
> > ?mn10300/Kconfig ? ? ? ? ? ? ? ? ? | ? ?3 ++-
> > ?parisc/Kconfig ? ? ? ? ? ? ? ? ? ?| ? ?6 +++---
> > ?powerpc/platforms/Kconfig.cputype | ? ?8 ++++----
> > ?s390/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? 12 +++++++-----
> > ?sh/Kconfig ? ? ? ? ? ? ? ? ? ? ? ?| ? 11 ++++++-----
> > ?sparc/Kconfig ? ? ? ? ? ? ? ? ? ? | ? ?8 ++++----
> > ?tile/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? ?9 +++++----
> > ?x86/Kconfig ? ? ? ? ? ? ? ? ? ? ? | ? 16 +++++++++-------
> > ?15 files changed, 78 insertions(+), 64 deletions(-)
> 
> You forgot to fix half of the architectures, a.o. m68k?

I must confess that I fixed only the SMP-capable architectures.

I of course would welcome additions for UP-only architectures.

							Thanx, Paul



From jason at lakedaemon.net  Sat Mar 31 14:12:40 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 31 Mar 2012 14:12:40 -0400
Subject: [PATCH V4 0/3] ARM: Kirkwood: Convert DNS-325 & DNS-320 to
 access nand via devicetree (was: Add support for DNS-320 and DNS-325 using
 devicetree)
In-Reply-To: <1333201985-2222-1-git-send-email-jm@lentin.co.uk>
References: <1333201985-2222-1-git-send-email-jm@lentin.co.uk>
Message-ID: <20120331181240.GA817@titan.lakedaemon.net>

On Sat, Mar 31, 2012 at 02:53:02PM +0100, Jamie Lentin wrote:
> Right, I've stopped being lazy and researched what the various properties
> contain and documented them.
> 
> In the process I noticed that all other drivers have bank-width in bytes,
> so I changed orion_nand to match. If using orion_nand without devicetree,
> the width property is still in bits though. Hopefully this isn't considered too
> bad? They have different names at least.
> 
> I've left out everything that has been merged into either Grant or Jason's
> tree. Hopefully this was a useful thing to do.
> 
> Thanks again to everyone reviewing.
> 
> Changes since v3: Add support for DNS-320 and DNS-325 using devicetree
> * Remove patches that are already merged
> * Add documentation on orion_nand devicetree bindings
> * Convert bank-width to be in bytes to match other properties
> * Make defaults more explicit
> 
> Changes since v2: Add support for DNS-320 and DNS-325 using devicetree
> * Split patches further, separating orion_nand and kirkwood changes
> * dts renames: "bank-width", not "width". "okay", not "ok"
> * Separate documentation out into separate patch, add references to
>   partition.txt to all mtd bindings.
>   
> Changes since v1: Add support for DNS-320 and DNS-325 using devicetree
> * Rebase against kirkwood_dt_for_3.4, removing premature devicetree ports.
> * Move additions into a separate board-dnskw.c. It could be separated further
>   into a board-dns320.c and board-dns325.c but it probably isn't worth it.
> * s/marvell,/mrvl,/g
> * Include an example dtb partition in documentation
> * Copy structure of serial nodes to allow common options for NAND to be set
>   in kirkwood.dtsi
> * Simplifications in orion-nand.c
> 
> Jamie Lentin (3):
>   mtd: Add orion_nand devicetree bindings
>   kirkwood: Allow nand to be configured via. devicetree
>   ARM: kirkwood: Define DNS-320/DNS-325 NAND in fdt
> 
>  .../devicetree/bindings/mtd/orion-nand.txt         |   50 ++++++++++++++++++++
>  arch/arm/boot/dts/kirkwood-dns320.dts              |   35 ++++++++++++++
>  arch/arm/boot/dts/kirkwood-dns325.dts              |   35 ++++++++++++++
>  arch/arm/boot/dts/kirkwood.dtsi                    |   15 ++++++-
>  arch/arm/mach-kirkwood/board-dnskw.c               |   31 ------------
>  arch/arm/mach-kirkwood/common.c                    |   12 +++++
>  drivers/mtd/nand/orion_nand.c                      |   41 +++++++++++++++-
>  7 files changed, 185 insertions(+), 34 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt

Looks good, I'll let it sit a few days to catch any other comments.

For the whole series:

Acked-by: Jason Cooper <jason at lakedaemon.net>

thx,

Jason.


From jason at lakedaemon.net  Sat Mar 31 14:27:22 2012
From: jason at lakedaemon.net (Jason Cooper)
Date: Sat, 31 Mar 2012 14:27:22 -0400
Subject: Support for Iomega iConnect
In-Reply-To: <20120330232419.GF7274@titan.lakedaemon.net>
References: <201203302330.49834.linux@baker-net.org.uk>
 <20120330232419.GF7274@titan.lakedaemon.net>
Message-ID: <20120331182722.GB817@titan.lakedaemon.net>

On Fri, Mar 30, 2012 at 07:24:19PM -0400, Jason Cooper wrote:
> You can also look at the history in this branch to see how support for
> dreamplug (also kirkwood SoC) was added.  Converting drivers to
> devicetree is still a work in progress, so, just match what dreamplug is
> doing.

Here's another example to follow, the Buffalo DNS-32[05]:

First patch is here:

http://www.spinics.net/lists/arm-kernel/msg166774.html

Converting the nand driver and using it is here:

http://www.spinics.net/lists/arm-kernel/msg167308.html

hth,

Jason.


From heqiaomai at 21cn.com  Sat Mar 31 14:35:20 2012
From: heqiaomai at 21cn.com (heqiaomai at 21cn.com)
Date: Sun, 1 Apr 2012 02:35:20 +0800 (CST)
Subject: =?UTF-8?Q?=E8=A6=81=E6=88=90=E5=8A=9F=E6=B5=B7?=
 =?UTF-8?Q?=E9=87=8F=E5=8F=91=E9=80=81EM?=
 =?UTF-8?Q?A1L,=E5=85=B3=E9=94=AE=E6=98=AF=E8=A6=81=E6=89=BE=E5=AF=B9?=
 =?UTF-8?Q?=E5=B7=A5=E5=85=B7__linux-arm-kernel?=
Message-ID: <2857090.37591333218923653.JavaMail.root@webmail5>

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From santosh.shilimkar at ti.com  Sat Mar 31 15:10:29 2012
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Sun, 1 Apr 2012 00:40:29 +0530
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CACVXFVPu1GEQy+sCgXMB8JCszPBBs8zHRVm94TYb1-y2afkqgw@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com> <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
 <4F7570FC.8000907@ti.com>
 <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>
 <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>
 <CACVXFVPbU2OqTN=S0AZCD10KuSBYxqyyRH_xee+WTaCD6VSmMQ@mail.gmail.com>
 <CAMQu2gzuQ-q+3RHsW0=U305jCF-td5-PEXkGZ6WnQTqA1K8oAQ@mail.gmail.com>
 <CACVXFVPu1GEQy+sCgXMB8JCszPBBs8zHRVm94TYb1-y2afkqgw@mail.gmail.com>
Message-ID: <CAMQu2gwuRpZ133962r3N4Y4K3oQ88ySa=SyoS6v=sSHGA=SGKw@mail.gmail.com>

On Sat, Mar 31, 2012 at 2:09 PM, Ming Lei <tom.leiming at gmail.com> wrote:
> On Sat, Mar 31, 2012 at 2:30 PM, Shilimkar, Santosh
>> Since you need to recompile the kernel, you can very much tweak the
>> clocksource to use GPTIMER with sysl clock. Support for that is still
>> in place.
>
> With current kernel, running 'make menuconfig' can do it, but after applying
> Hiremath's patch[1], I have to edit the source code manually to get it, so looks
> this kind of tweaking is not friendly enough, :-(
>
It's not friendly but doable. But above can be supported I guess.

Since you are talking about doing menuconfig
and rebuilding kernel so what can be done is when one disable CPUIDLE
and PM, one can disabled 32K source as well. And then 32K clocksource
init should fail and fallback on gptimer clock source.

Vaibhav,
Can you update your patch to support above. The patch which I
did was doing exactly that but was not using hwmod. The problem with your
patch is synctimer hwmod lookup on OMAP will never fail if the hwmod
entry is supported.

So you might better use failure case of omap_init_clocksource_32k() for
fall back on gptimer source as I tried in my patch. That should support
the usage mentioned by Ming Lie

Regards
Santosh


From paulmck at linux.vnet.ibm.com  Sat Mar 31 16:14:22 2012
From: paulmck at linux.vnet.ibm.com (Paul E. McKenney)
Date: Sat, 31 Mar 2012 13:14:22 -0700
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
In-Reply-To: <CAHrUA35Bz68DtP-Znr=-+U+6P9CONXzN=9JdMXRfRwmVV9fy=Q@mail.gmail.com>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
 <CAHrUA35Bz68DtP-Znr=-+U+6P9CONXzN=9JdMXRfRwmVV9fy=Q@mail.gmail.com>
Message-ID: <20120331201422.GG2450@linux.vnet.ibm.com>

On Sat, Mar 31, 2012 at 02:57:46PM -0500, Linas Vepstas wrote:
> Hi,
> 
> I didn't actually try to compile the patch below; it didn't look like C
> code so I wasn't sure what compiler to run it through.  I guess maybe its
> python?  However, I'm very sure that the patches are completely correct,
> because I read them, and I also know that Paul is a trustworthy programmer.
>  Thus, please add my ack
> 
> Ack'ed by: Linas Vepstas <linasvepstas at gmail.com>

It is Linux-kernel Kconfig language, which processed during kernel
builds.  I have added your Acked-by.  ;-)

							Thanx, Paul

> On 31 March 2012 11:33, Paul E. McKenney <paulmck at linux.vnet.ibm.com> wrote:
> 
> > Although there have been numerous complaints about the complexity of
> > parallel programming (especially over the past 5-10 years), the plain
> > truth is that the incremental complexity of parallel programming over
> > that of sequential programming is not as large as is commonly believed.
> > Despite that you might have heard, the mind-numbing complexity of modern
> > computer systems is not due so much to there being multiple CPUs, but
> > rather to there being any CPUs at all.  In short, for the ultimate in
> > computer-system simplicity, the optimal choice is NR_CPUS=0.
> >
> > This commit therefore limits kernel builds to zero CPUs.  This change
> > has the beneficial side effect of rendering all kernel bugs harmless.
> > Furthermore, this commit enables additional beneficial changes, for
> > example, the removal of those parts of the kernel that are not needed
> > when there are zero CPUs.
> >
> > Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> > Reviewed-by: Thomas Gleixner <tglx at linutronix.de>
> > ---
> >
> >  alpha/Kconfig                     |   11 ++++++-----
> >  arm/Kconfig                       |    6 +++---
> >  blackfin/Kconfig                  |    3 ++-
> >  hexagon/Kconfig                   |    9 +++++----
> >  ia64/Kconfig                      |    9 +++++----
> >  m32r/Kconfig                      |   10 ++++++----
> >  mips/Kconfig                      |   21 +++++++++++----------
> >  mn10300/Kconfig                   |    3 ++-
> >  parisc/Kconfig                    |    6 +++---
> >  powerpc/platforms/Kconfig.cputype |    8 ++++----
> >  s390/Kconfig                      |   12 +++++++-----
> >  sh/Kconfig                        |   11 ++++++-----
> >  sparc/Kconfig                     |    8 ++++----
> >  tile/Kconfig                      |    9 +++++----
> >  x86/Kconfig                       |   16 +++++++++-------
> >  15 files changed, 78 insertions(+), 64 deletions(-)
> >
> > diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
> > index 56a4df9..1766b4a 100644
> > --- a/arch/alpha/Kconfig
> > +++ b/arch/alpha/Kconfig
> > @@ -541,14 +541,15 @@ config HAVE_DEC_LOCK
> >        default y
> >
> >  config NR_CPUS
> > -       int "Maximum number of CPUs (2-32)"
> > -       range 2 32
> > +       int "Maximum number of CPUs (0-0)"
> > +       range 0 0
> >        depends on SMP
> > -       default "32" if ALPHA_GENERIC || ALPHA_MARVEL
> > -       default "4" if !ALPHA_GENERIC && !ALPHA_MARVEL
> > +       default "0" if ALPHA_GENERIC || ALPHA_MARVEL
> > +       default "0" if !ALPHA_GENERIC && !ALPHA_MARVEL
> >        help
> >          MARVEL support can handle a maximum of 32 CPUs, all the others
> > -          with working support have a maximum of 4 CPUs.
> > +          with working support have a maximum of 4 CPUs.  But why take
> > +         chances?  Just stick with zero CPUs.
> >
> >  config ARCH_DISCONTIGMEM_ENABLE
> >        bool "Discontiguous Memory Support (EXPERIMENTAL)"
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index a48aecc..1f07a3a 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -1551,10 +1551,10 @@ config PAGE_OFFSET
> >        default 0xC0000000
> >
> >  config NR_CPUS
> > -       int "Maximum number of CPUs (2-32)"
> > -       range 2 32
> > +       int "Maximum number of CPUs (0-0)"
> > +       range 0 0
> >        depends on SMP
> > -       default "4"
> > +       default "0"
> >
> >  config HOTPLUG_CPU
> >        bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
> > diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
> > index abe5a9e..6a78549 100644
> > --- a/arch/blackfin/Kconfig
> > +++ b/arch/blackfin/Kconfig
> > @@ -241,7 +241,8 @@ config SMP
> >  config NR_CPUS
> >        int
> >        depends on SMP
> > -       default 2 if BF561
> > +       range 0 0
> > +       default 0 if BF561
> >
> >  config HOTPLUG_CPU
> >        bool "Support for hot-pluggable CPUs"
> > diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig
> > index 9059e39..daab009 100644
> > --- a/arch/hexagon/Kconfig
> > +++ b/arch/hexagon/Kconfig
> > @@ -158,13 +158,14 @@ config SMP
> >
> >  config NR_CPUS
> >        int "Maximum number of CPUs" if SMP
> > -       range 2 6 if SMP
> > -       default "1" if !SMP
> > -       default "6" if SMP
> > +       range 0 0 if SMP
> > +       default "0" if !SMP
> > +       default "0" if SMP
> >        ---help---
> >          This allows you to specify the maximum number of CPUs which this
> >          kernel will support.  The maximum supported value is 6 and the
> > -         minimum value which makes sense is 2.
> > +         minimum value which makes sense is 2.  But a limit of zero is
> > +         so much safer!
> >
> >          This is purely to save memory - each supported CPU adds
> >          approximately eight kilobytes to the kernel image.
> > diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
> > index bd72669..fea0e6d 100644
> > --- a/arch/ia64/Kconfig
> > +++ b/arch/ia64/Kconfig
> > @@ -373,16 +373,17 @@ config SMP
> >          If you don't know what to do here, say N.
> >
> >  config NR_CPUS
> > -       int "Maximum number of CPUs (2-4096)"
> > -       range 2 4096
> > +       int "Maximum number of CPUs (0-0)"
> > +       range 0 0
> >        depends on SMP
> > -       default "4096"
> > +       default "0"
> >        help
> >          You should set this to the number of CPUs in your system, but
> >          keep in mind that a kernel compiled for, e.g., 2 CPUs will boot
> > but
> >          only use 2 CPUs on a >2 CPU system.  Setting this to a value
> > larger
> >          than 64 will cause the use of a CPU mask array, causing a small
> > -         performance hit.
> > +         performance hit.  And setting it larger than zero risks all
> > +         manner of software bugs, so we just play it safe.
> >
> >  config HOTPLUG_CPU
> >        bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
> > diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
> > index ef80a65..68b9e88 100644
> > --- a/arch/m32r/Kconfig
> > +++ b/arch/m32r/Kconfig
> > @@ -300,14 +300,16 @@ config CHIP_M32700_TS1
> >        default n
> >
> >  config NR_CPUS
> > -       int "Maximum number of CPUs (2-32)"
> > -       range 2 32
> > +       int "Maximum number of CPUs (0-0)"
> > +       range 0 0
> >        depends on SMP
> > -       default "2"
> > +       default "0"
> >        help
> >          This allows you to specify the maximum number of CPUs which this
> >          kernel will support.  The maximum supported value is 32 and the
> > -         minimum value which makes sense is 2.
> > +         minimum value which makes sense is 2.  Zero may not make sense,
> > +         but given that there is much in this world that does not make
> > +         sense, zero it is!
> >
> >          This is purely to save memory - each supported CPU adds
> >          approximately eight kilobytes to the kernel image.
> > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> > index 5ab6e89..3d7d06c 100644
> > --- a/arch/mips/Kconfig
> > +++ b/arch/mips/Kconfig
> > @@ -2192,16 +2192,16 @@ config NR_CPUS_DEFAULT_64
> >        bool
> >
> >  config NR_CPUS
> > -       int "Maximum number of CPUs (2-64)"
> > -       range 1 64 if NR_CPUS_DEFAULT_1
> > +       int "Maximum number of CPUs (0-0)"
> > +       range 0 0 if NR_CPUS_DEFAULT_1
> >        depends on SMP
> > -       default "1" if NR_CPUS_DEFAULT_1
> > -       default "2" if NR_CPUS_DEFAULT_2
> > -       default "4" if NR_CPUS_DEFAULT_4
> > -       default "8" if NR_CPUS_DEFAULT_8
> > -       default "16" if NR_CPUS_DEFAULT_16
> > -       default "32" if NR_CPUS_DEFAULT_32
> > -       default "64" if NR_CPUS_DEFAULT_64
> > +       default "0" if NR_CPUS_DEFAULT_1
> > +       default "0" if NR_CPUS_DEFAULT_2
> > +       default "0" if NR_CPUS_DEFAULT_4
> > +       default "0" if NR_CPUS_DEFAULT_8
> > +       default "0" if NR_CPUS_DEFAULT_16
> > +       default "0" if NR_CPUS_DEFAULT_32
> > +       default "0" if NR_CPUS_DEFAULT_64
> >        help
> >          This allows you to specify the maximum number of CPUs which this
> >          kernel will support.  The maximum supported value is 32 for 32-bit
> > @@ -2212,7 +2212,8 @@ config NR_CPUS
> >          This is purely to save memory - each supported CPU adds
> >          approximately eight kilobytes to the kernel image.  For best
> >          performance should round up your number of processors to the next
> > -         power of two.
> > +         power of two.  And just think how much more memory we will
> > +         save by setting the limit to zero!
> >
> >  source "kernel/time/Kconfig"
> >
> > diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
> > index 8f1c40d..85fc112 100644
> > --- a/arch/mn10300/Kconfig
> > +++ b/arch/mn10300/Kconfig
> > @@ -201,7 +201,8 @@ config SMP
> >  config NR_CPUS
> >        int
> >        depends on SMP
> > -       default "2"
> > +       range 0 0
> > +       default "0"
> >
> >  source "kernel/Kconfig.preempt"
> >
> > diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
> > index 242a1b7..358eaf8 100644
> > --- a/arch/parisc/Kconfig
> > +++ b/arch/parisc/Kconfig
> > @@ -254,10 +254,10 @@ config HPUX
> >        depends on !64BIT
> >
> >  config NR_CPUS
> > -       int "Maximum number of CPUs (2-32)"
> > -       range 2 32
> > +       int "Maximum number of CPUs (0-0)"
> > +       range 0 0
> >        depends on SMP
> > -       default "32"
> > +       default "0"
> >
> >  endmenu
> >
> > diff --git a/arch/powerpc/platforms/Kconfig.cputype
> > b/arch/powerpc/platforms/Kconfig.cputype
> > index 425db18..5e607e0 100644
> > --- a/arch/powerpc/platforms/Kconfig.cputype
> > +++ b/arch/powerpc/platforms/Kconfig.cputype
> > @@ -356,11 +356,11 @@ config SMP
> >          If you don't know what to do here, say N.
> >
> >  config NR_CPUS
> > -       int "Maximum number of CPUs (2-8192)"
> > -       range 2 8192
> > +       int "Maximum number of CPUs (0-0)"
> > +       range 0 0
> >        depends on SMP
> > -       default "32" if PPC64
> > -       default "4"
> > +       default "0" if PPC64
> > +       default "0"
> >
> >  config NOT_COHERENT_CACHE
> >        bool
> > diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
> > index d172758..f9bc067 100644
> > --- a/arch/s390/Kconfig
> > +++ b/arch/s390/Kconfig
> > @@ -169,15 +169,17 @@ config SMP
> >          Even if you don't know what to do here, say Y.
> >
> >  config NR_CPUS
> > -       int "Maximum number of CPUs (2-64)"
> > -       range 2 64
> > +       int "Maximum number of CPUs (0-0)"
> > +       range 0 0
> >        depends on SMP
> > -       default "32" if !64BIT
> > -       default "64" if 64BIT
> > +       default "0" if !64BIT
> > +       default "0" if 64BIT
> >        help
> >          This allows you to specify the maximum number of CPUs which this
> >          kernel will support.  The maximum supported value is 64 and the
> > -         minimum value which makes sense is 2.
> > +         minimum value which makes sense is 2.  The minimal value that
> > +         makes sense might well be 2, but we all know that the only
> > +         -sane- value is zero!
> >
> >          This is purely to save memory - each supported CPU adds
> >          approximately sixteen kilobytes to the kernel image.
> > diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
> > index 713fb58..5ddc7c0 100644
> > --- a/arch/sh/Kconfig
> > +++ b/arch/sh/Kconfig
> > @@ -705,18 +705,19 @@ config SMP
> >          If you don't know what to do here, say N.
> >
> >  config NR_CPUS
> > -       int "Maximum number of CPUs (2-32)"
> > -       range 2 32
> > +       int "Maximum number of CPUs (0-0)"
> > +       range 0 0
> >        depends on SMP
> > -       default "4" if CPU_SUBTYPE_SHX3
> > -       default "2"
> > +       default "0" if CPU_SUBTYPE_SHX3
> > +       default "0"
> >        help
> >          This allows you to specify the maximum number of CPUs which this
> >          kernel will support.  The maximum supported value is 32 and the
> >          minimum value which makes sense is 2.
> >
> >          This is purely to save memory - each supported CPU adds
> > -         approximately eight kilobytes to the kernel image.
> > +         approximately eight kilobytes to the kernel image.  Debloating
> > +         is the way, NR_CPUS to zero today!!!
> >
> >  config HOTPLUG_CPU
> >        bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
> > diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
> > index ca5580e..0de9f0f 100644
> > --- a/arch/sparc/Kconfig
> > +++ b/arch/sparc/Kconfig
> > @@ -177,10 +177,10 @@ config SMP
> >  config NR_CPUS
> >        int "Maximum number of CPUs"
> >        depends on SMP
> > -       range 2 32 if SPARC32
> > -       range 2 1024 if SPARC64
> > -       default 32 if SPARC32
> > -       default 64 if SPARC64
> > +       range 0 0 if SPARC32
> > +       range 0 0 if SPARC64
> > +       default 0 if SPARC32
> > +       default 0 if SPARC64
> >
> >  source kernel/Kconfig.hz
> >
> > diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
> > index 11270ca..a05112c 100644
> > --- a/arch/tile/Kconfig
> > +++ b/arch/tile/Kconfig
> > @@ -126,14 +126,15 @@ source "init/Kconfig"
> >  menu "Tilera-specific configuration"
> >
> >  config NR_CPUS
> > -       int "Maximum number of tiles (2-255)"
> > -       range 2 255
> > +       int "Maximum number of tiles (0-0)"
> > +       range 0 0
> >        depends on SMP
> > -       default "64"
> > +       default "0"
> >        ---help---
> >          Building with 64 is the recommended value, but a slightly
> >          smaller kernel memory footprint results from using a smaller
> > -         value on chips with fewer tiles.
> > +         value on chips with fewer tiles.  To minimize both memory
> > +         footprint and bugs, use zero and only zero.
> >
> >  source "kernel/time/Kconfig"
> >
> > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> > index 5bed94e..a6977f2 100644
> > --- a/arch/x86/Kconfig
> > +++ b/arch/x86/Kconfig
> > @@ -773,19 +773,21 @@ config MAXSMP
> >
> >  config NR_CPUS
> >        int "Maximum number of CPUs" if SMP && !MAXSMP
> > -       range 2 8 if SMP && X86_32 && !X86_BIGSMP
> > -       range 2 512 if SMP && !MAXSMP
> > -       default "1" if !SMP
> > -       default "4096" if MAXSMP
> > -       default "32" if SMP && (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP ||
> > X86_ES7000)
> > -       default "8" if SMP
> > +       range 0 0 if SMP && X86_32 && !X86_BIGSMP
> > +       range 0 0 if SMP && !MAXSMP
> > +       default "0" if !SMP
> > +       default "0" if MAXSMP
> > +       default "0" if SMP && (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP ||
> > X86_ES7000)
> > +       default "0" if SMP
> >        ---help---
> >          This allows you to specify the maximum number of CPUs which this
> >          kernel will support.  The maximum supported value is 512 and the
> >          minimum value which makes sense is 2.
> >
> >          This is purely to save memory - each supported CPU adds
> > -         approximately eight kilobytes to the kernel image.
> > +         approximately eight kilobytes to the kernel image.  But
> > +         the first supported CPU brings a lot of bugs with it, so
> > +         for ultimate reliability, set the number of CPUs to zero.
> >
> >  config SCHED_SMT
> >        bool "SMT (Hyperthreading) scheduler support"
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-hexagon" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> >



From linasvepstas at gmail.com  Sat Mar 31 16:15:00 2012
From: linasvepstas at gmail.com (Linas Vepstas)
Date: Sat, 31 Mar 2012 15:15:00 -0500
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
In-Reply-To: <20120331163321.GA15809@linux.vnet.ibm.com>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
Message-ID: <20120331201500.GA27640@linas.org>


Hi,

I didn't actually try to compile the patch below; it didn't look like
C code so I wasn't sure what compiler to run it through.  I guess maybe
its python?  However, I'm very sure that the patches are completely
correct, because I read them, and I also know Paul.  And I've heard of
Thomas Gleixner.

Thus, please add my ack --

Ack'ed by: Linas Vepstas <linasvepstas at gmail.com>


On Sun, Apr 01, 2012 at 12:33:21AM +0800, Paul E. McKenney was heard to remark:
> Although there have been numerous complaints about the complexity of
> parallel programming (especially over the past 5-10 years), the plain
> truth is that the incremental complexity of parallel programming over
> that of sequential programming is not as large as is commonly believed.
> Despite that you might have heard, the mind-numbing complexity of modern
> computer systems is not due so much to there being multiple CPUs, but
> rather to there being any CPUs at all.  In short, for the ultimate in
> computer-system simplicity, the optimal choice is NR_CPUS=0.
> 
> This commit therefore limits kernel builds to zero CPUs.  This change
> has the beneficial side effect of rendering all kernel bugs harmless.
> Furthermore, this commit enables additional beneficial changes, for
> example, the removal of those parts of the kernel that are not needed
> when there are zero CPUs.
> 
> Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> Reviewed-by: Thomas Gleixner <tglx at linutronix.de>
> ---
> 
>  alpha/Kconfig                     |   11 ++++++-----
>  arm/Kconfig                       |    6 +++---
>  blackfin/Kconfig                  |    3 ++-
>  hexagon/Kconfig                   |    9 +++++----
>  ia64/Kconfig                      |    9 +++++----
>  m32r/Kconfig                      |   10 ++++++----
>  mips/Kconfig                      |   21 +++++++++++----------
>  mn10300/Kconfig                   |    3 ++-
>  parisc/Kconfig                    |    6 +++---
>  powerpc/platforms/Kconfig.cputype |    8 ++++----
>  s390/Kconfig                      |   12 +++++++-----
>  sh/Kconfig                        |   11 ++++++-----
>  sparc/Kconfig                     |    8 ++++----
>  tile/Kconfig                      |    9 +++++----
>  x86/Kconfig                       |   16 +++++++++-------
>  15 files changed, 78 insertions(+), 64 deletions(-)
> 
> diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
> index 56a4df9..1766b4a 100644
> --- a/arch/alpha/Kconfig
> +++ b/arch/alpha/Kconfig
> @@ -541,14 +541,15 @@ config HAVE_DEC_LOCK
>  	default y
>  
>  config NR_CPUS
> -	int "Maximum number of CPUs (2-32)"
> -	range 2 32
> +	int "Maximum number of CPUs (0-0)"
> +	range 0 0
>  	depends on SMP
> -	default "32" if ALPHA_GENERIC || ALPHA_MARVEL
> -	default "4" if !ALPHA_GENERIC && !ALPHA_MARVEL
> +	default "0" if ALPHA_GENERIC || ALPHA_MARVEL
> +	default "0" if !ALPHA_GENERIC && !ALPHA_MARVEL
>  	help
>  	  MARVEL support can handle a maximum of 32 CPUs, all the others
> -          with working support have a maximum of 4 CPUs.
> +          with working support have a maximum of 4 CPUs.  But why take
> +	  chances?  Just stick with zero CPUs.
>  
>  config ARCH_DISCONTIGMEM_ENABLE
>  	bool "Discontiguous Memory Support (EXPERIMENTAL)"
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index a48aecc..1f07a3a 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1551,10 +1551,10 @@ config PAGE_OFFSET
>  	default 0xC0000000
>  
>  config NR_CPUS
> -	int "Maximum number of CPUs (2-32)"
> -	range 2 32
> +	int "Maximum number of CPUs (0-0)"
> +	range 0 0
>  	depends on SMP
> -	default "4"
> +	default "0"
>  
>  config HOTPLUG_CPU
>  	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
> diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
> index abe5a9e..6a78549 100644
> --- a/arch/blackfin/Kconfig
> +++ b/arch/blackfin/Kconfig
> @@ -241,7 +241,8 @@ config SMP
>  config NR_CPUS
>  	int
>  	depends on SMP
> -	default 2 if BF561
> +	range 0 0
> +	default 0 if BF561
>  
>  config HOTPLUG_CPU
>  	bool "Support for hot-pluggable CPUs"
> diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig
> index 9059e39..daab009 100644
> --- a/arch/hexagon/Kconfig
> +++ b/arch/hexagon/Kconfig
> @@ -158,13 +158,14 @@ config SMP
>  
>  config NR_CPUS
>  	int "Maximum number of CPUs" if SMP
> -	range 2 6 if SMP
> -	default "1" if !SMP
> -	default "6" if SMP
> +	range 0 0 if SMP
> +	default "0" if !SMP
> +	default "0" if SMP
>  	---help---
>  	  This allows you to specify the maximum number of CPUs which this
>  	  kernel will support.  The maximum supported value is 6 and the
> -	  minimum value which makes sense is 2.
> +	  minimum value which makes sense is 2.  But a limit of zero is
> +	  so much safer!
>  
>  	  This is purely to save memory - each supported CPU adds
>  	  approximately eight kilobytes to the kernel image.
> diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
> index bd72669..fea0e6d 100644
> --- a/arch/ia64/Kconfig
> +++ b/arch/ia64/Kconfig
> @@ -373,16 +373,17 @@ config SMP
>  	  If you don't know what to do here, say N.
>  
>  config NR_CPUS
> -	int "Maximum number of CPUs (2-4096)"
> -	range 2 4096
> +	int "Maximum number of CPUs (0-0)"
> +	range 0 0
>  	depends on SMP
> -	default "4096"
> +	default "0"
>  	help
>  	  You should set this to the number of CPUs in your system, but
>  	  keep in mind that a kernel compiled for, e.g., 2 CPUs will boot but
>  	  only use 2 CPUs on a >2 CPU system.  Setting this to a value larger
>  	  than 64 will cause the use of a CPU mask array, causing a small
> -	  performance hit.
> +	  performance hit.  And setting it larger than zero risks all
> +	  manner of software bugs, so we just play it safe.
>  
>  config HOTPLUG_CPU
>  	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
> diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
> index ef80a65..68b9e88 100644
> --- a/arch/m32r/Kconfig
> +++ b/arch/m32r/Kconfig
> @@ -300,14 +300,16 @@ config CHIP_M32700_TS1
>  	default n
>  
>  config NR_CPUS
> -	int "Maximum number of CPUs (2-32)"
> -	range 2 32
> +	int "Maximum number of CPUs (0-0)"
> +	range 0 0
>  	depends on SMP
> -	default "2"
> +	default "0"
>  	help
>  	  This allows you to specify the maximum number of CPUs which this
>  	  kernel will support.  The maximum supported value is 32 and the
> -	  minimum value which makes sense is 2.
> +	  minimum value which makes sense is 2.  Zero may not make sense,
> +	  but given that there is much in this world that does not make
> +	  sense, zero it is!
>  
>  	  This is purely to save memory - each supported CPU adds
>  	  approximately eight kilobytes to the kernel image.
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 5ab6e89..3d7d06c 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2192,16 +2192,16 @@ config NR_CPUS_DEFAULT_64
>  	bool
>  
>  config NR_CPUS
> -	int "Maximum number of CPUs (2-64)"
> -	range 1 64 if NR_CPUS_DEFAULT_1
> +	int "Maximum number of CPUs (0-0)"
> +	range 0 0 if NR_CPUS_DEFAULT_1
>  	depends on SMP
> -	default "1" if NR_CPUS_DEFAULT_1
> -	default "2" if NR_CPUS_DEFAULT_2
> -	default "4" if NR_CPUS_DEFAULT_4
> -	default "8" if NR_CPUS_DEFAULT_8
> -	default "16" if NR_CPUS_DEFAULT_16
> -	default "32" if NR_CPUS_DEFAULT_32
> -	default "64" if NR_CPUS_DEFAULT_64
> +	default "0" if NR_CPUS_DEFAULT_1
> +	default "0" if NR_CPUS_DEFAULT_2
> +	default "0" if NR_CPUS_DEFAULT_4
> +	default "0" if NR_CPUS_DEFAULT_8
> +	default "0" if NR_CPUS_DEFAULT_16
> +	default "0" if NR_CPUS_DEFAULT_32
> +	default "0" if NR_CPUS_DEFAULT_64
>  	help
>  	  This allows you to specify the maximum number of CPUs which this
>  	  kernel will support.  The maximum supported value is 32 for 32-bit
> @@ -2212,7 +2212,8 @@ config NR_CPUS
>  	  This is purely to save memory - each supported CPU adds
>  	  approximately eight kilobytes to the kernel image.  For best
>  	  performance should round up your number of processors to the next
> -	  power of two.
> +	  power of two.  And just think how much more memory we will
> +	  save by setting the limit to zero!
>  
>  source "kernel/time/Kconfig"
>  
> diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
> index 8f1c40d..85fc112 100644
> --- a/arch/mn10300/Kconfig
> +++ b/arch/mn10300/Kconfig
> @@ -201,7 +201,8 @@ config SMP
>  config NR_CPUS
>  	int
>  	depends on SMP
> -	default "2"
> +	range 0 0
> +	default "0"
>  
>  source "kernel/Kconfig.preempt"
>  
> diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
> index 242a1b7..358eaf8 100644
> --- a/arch/parisc/Kconfig
> +++ b/arch/parisc/Kconfig
> @@ -254,10 +254,10 @@ config HPUX
>  	depends on !64BIT
>  
>  config NR_CPUS
> -	int "Maximum number of CPUs (2-32)"
> -	range 2 32
> +	int "Maximum number of CPUs (0-0)"
> +	range 0 0
>  	depends on SMP
> -	default "32"
> +	default "0"
>  
>  endmenu
>  
> diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
> index 425db18..5e607e0 100644
> --- a/arch/powerpc/platforms/Kconfig.cputype
> +++ b/arch/powerpc/platforms/Kconfig.cputype
> @@ -356,11 +356,11 @@ config SMP
>  	  If you don't know what to do here, say N.
>  
>  config NR_CPUS
> -	int "Maximum number of CPUs (2-8192)"
> -	range 2 8192
> +	int "Maximum number of CPUs (0-0)"
> +	range 0 0
>  	depends on SMP
> -	default "32" if PPC64
> -	default "4"
> +	default "0" if PPC64
> +	default "0"
>  
>  config NOT_COHERENT_CACHE
>  	bool
> diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
> index d172758..f9bc067 100644
> --- a/arch/s390/Kconfig
> +++ b/arch/s390/Kconfig
> @@ -169,15 +169,17 @@ config SMP
>  	  Even if you don't know what to do here, say Y.
>  
>  config NR_CPUS
> -	int "Maximum number of CPUs (2-64)"
> -	range 2 64
> +	int "Maximum number of CPUs (0-0)"
> +	range 0 0
>  	depends on SMP
> -	default "32" if !64BIT
> -	default "64" if 64BIT
> +	default "0" if !64BIT
> +	default "0" if 64BIT
>  	help
>  	  This allows you to specify the maximum number of CPUs which this
>  	  kernel will support.  The maximum supported value is 64 and the
> -	  minimum value which makes sense is 2.
> +	  minimum value which makes sense is 2.  The minimal value that
> +	  makes sense might well be 2, but we all know that the only
> +	  -sane- value is zero!
>  
>  	  This is purely to save memory - each supported CPU adds
>  	  approximately sixteen kilobytes to the kernel image.
> diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
> index 713fb58..5ddc7c0 100644
> --- a/arch/sh/Kconfig
> +++ b/arch/sh/Kconfig
> @@ -705,18 +705,19 @@ config SMP
>  	  If you don't know what to do here, say N.
>  
>  config NR_CPUS
> -	int "Maximum number of CPUs (2-32)"
> -	range 2 32
> +	int "Maximum number of CPUs (0-0)"
> +	range 0 0
>  	depends on SMP
> -	default "4" if CPU_SUBTYPE_SHX3
> -	default "2"
> +	default "0" if CPU_SUBTYPE_SHX3
> +	default "0"
>  	help
>  	  This allows you to specify the maximum number of CPUs which this
>  	  kernel will support.  The maximum supported value is 32 and the
>  	  minimum value which makes sense is 2.
>  
>  	  This is purely to save memory - each supported CPU adds
> -	  approximately eight kilobytes to the kernel image.
> +	  approximately eight kilobytes to the kernel image.  Debloating
> +	  is the way, NR_CPUS to zero today!!!
>  
>  config HOTPLUG_CPU
>  	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
> diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
> index ca5580e..0de9f0f 100644
> --- a/arch/sparc/Kconfig
> +++ b/arch/sparc/Kconfig
> @@ -177,10 +177,10 @@ config SMP
>  config NR_CPUS
>  	int "Maximum number of CPUs"
>  	depends on SMP
> -	range 2 32 if SPARC32
> -	range 2 1024 if SPARC64
> -	default 32 if SPARC32
> -	default 64 if SPARC64
> +	range 0 0 if SPARC32
> +	range 0 0 if SPARC64
> +	default 0 if SPARC32
> +	default 0 if SPARC64
>  
>  source kernel/Kconfig.hz
>  
> diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
> index 11270ca..a05112c 100644
> --- a/arch/tile/Kconfig
> +++ b/arch/tile/Kconfig
> @@ -126,14 +126,15 @@ source "init/Kconfig"
>  menu "Tilera-specific configuration"
>  
>  config NR_CPUS
> -	int "Maximum number of tiles (2-255)"
> -	range 2 255
> +	int "Maximum number of tiles (0-0)"
> +	range 0 0
>  	depends on SMP
> -	default "64"
> +	default "0"
>  	---help---
>  	  Building with 64 is the recommended value, but a slightly
>  	  smaller kernel memory footprint results from using a smaller
> -	  value on chips with fewer tiles.
> +	  value on chips with fewer tiles.  To minimize both memory
> +	  footprint and bugs, use zero and only zero.
>  
>  source "kernel/time/Kconfig"
>  
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index 5bed94e..a6977f2 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -773,19 +773,21 @@ config MAXSMP
>  
>  config NR_CPUS
>  	int "Maximum number of CPUs" if SMP && !MAXSMP
> -	range 2 8 if SMP && X86_32 && !X86_BIGSMP
> -	range 2 512 if SMP && !MAXSMP
> -	default "1" if !SMP
> -	default "4096" if MAXSMP
> -	default "32" if SMP && (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP || X86_ES7000)
> -	default "8" if SMP
> +	range 0 0 if SMP && X86_32 && !X86_BIGSMP
> +	range 0 0 if SMP && !MAXSMP
> +	default "0" if !SMP
> +	default "0" if MAXSMP
> +	default "0" if SMP && (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP || X86_ES7000)
> +	default "0" if SMP
>  	---help---
>  	  This allows you to specify the maximum number of CPUs which this
>  	  kernel will support.  The maximum supported value is 512 and the
>  	  minimum value which makes sense is 2.
>  
>  	  This is purely to save memory - each supported CPU adds
> -	  approximately eight kilobytes to the kernel image.
> +	  approximately eight kilobytes to the kernel image.  But
> +	  the first supported CPU brings a lot of bugs with it, so
> +	  for ultimate reliability, set the number of CPUs to zero.
>  
>  config SCHED_SMT
>  	bool "SMT (Hyperthreading) scheduler support"
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-hexagon" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
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From rdunlap at xenotime.net  Sat Mar 31 16:25:02 2012
From: rdunlap at xenotime.net (Randy Dunlap)
Date: Sat, 31 Mar 2012 13:25:02 -0700
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
In-Reply-To: <20120331201500.GA27640@linas.org>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
 <20120331201500.GA27640@linas.org>
Message-ID: <4F77681E.5010608@xenotime.net>

On 03/31/2012 01:15 PM, Linas Vepstas wrote:

> 
> Hi,
> 
> I didn't actually try to compile the patch below; it didn't look like
> C code so I wasn't sure what compiler to run it through.  I guess maybe
> its python?  However, I'm very sure that the patches are completely
> correct, because I read them, and I also know Paul.  And I've heard of
> Thomas Gleixner.


x86_64 defconfig has many build errors and warnings.  :(

back to my abacus.

-- 
~Randy


From paulmck at linux.vnet.ibm.com  Sat Mar 31 16:43:32 2012
From: paulmck at linux.vnet.ibm.com (Paul E. McKenney)
Date: Sat, 31 Mar 2012 13:43:32 -0700
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
In-Reply-To: <4F77681E.5010608@xenotime.net>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
 <20120331201500.GA27640@linas.org> <4F77681E.5010608@xenotime.net>
Message-ID: <20120331204332.GH2450@linux.vnet.ibm.com>

On Sat, Mar 31, 2012 at 01:25:02PM -0700, Randy Dunlap wrote:
> On 03/31/2012 01:15 PM, Linas Vepstas wrote:
> 
> > 
> > Hi,
> > 
> > I didn't actually try to compile the patch below; it didn't look like
> > C code so I wasn't sure what compiler to run it through.  I guess maybe
> > its python?  However, I'm very sure that the patches are completely
> > correct, because I read them, and I also know Paul.  And I've heard of
> > Thomas Gleixner.
> 
> 
> x86_64 defconfig has many build errors and warnings.  :(

I suggest removing the code containing the errors and warnings.  I bet
that the offending code is not needed when running with zero CPUs.

> back to my abacus.

;-)

							Thanx, Paul



From eric.dumazet at gmail.com  Sat Mar 31 17:00:08 2012
From: eric.dumazet at gmail.com (Eric Dumazet)
Date: Sat, 31 Mar 2012 23:00:08 +0200
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
In-Reply-To: <20120331163321.GA15809@linux.vnet.ibm.com>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
Message-ID: <1333227608.2325.4054.camel@edumazet-glaptop>

On Sun, 2012-04-01 at 00:33 +0800, Paul E. McKenney wrote:
> Although there have been numerous complaints about the complexity of
> parallel programming (especially over the past 5-10 years), the plain
> truth is that the incremental complexity of parallel programming over
> that of sequential programming is not as large as is commonly believed.
> Despite that you might have heard, the mind-numbing complexity of modern
> computer systems is not due so much to there being multiple CPUs, but
> rather to there being any CPUs at all.  In short, for the ultimate in
> computer-system simplicity, the optimal choice is NR_CPUS=0.
> 
> This commit therefore limits kernel builds to zero CPUs.  This change
> has the beneficial side effect of rendering all kernel bugs harmless.
> Furthermore, this commit enables additional beneficial changes, for
> example, the removal of those parts of the kernel that are not needed
> when there are zero CPUs.
> 
> Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> Reviewed-by: Thomas Gleixner <tglx at linutronix.de>
> ---

Hmm... I believe you could go one step forward and allow negative values
as well. Antimatter was proven to exist after all.

Hint : nr_cpu_ids is an "int", not an "unsigned int"

Bonus: Existing bugs become "must have" features.

Of course there is no hurry and this can wait 365 days.




From paulmck at linux.vnet.ibm.com  Sat Mar 31 17:21:49 2012
From: paulmck at linux.vnet.ibm.com (Paul E. McKenney)
Date: Sat, 31 Mar 2012 14:21:49 -0700
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
In-Reply-To: <1333227608.2325.4054.camel@edumazet-glaptop>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
 <1333227608.2325.4054.camel@edumazet-glaptop>
Message-ID: <20120331212149.GI2450@linux.vnet.ibm.com>

On Sat, Mar 31, 2012 at 11:00:08PM +0200, Eric Dumazet wrote:
> On Sun, 2012-04-01 at 00:33 +0800, Paul E. McKenney wrote:
> > Although there have been numerous complaints about the complexity of
> > parallel programming (especially over the past 5-10 years), the plain
> > truth is that the incremental complexity of parallel programming over
> > that of sequential programming is not as large as is commonly believed.
> > Despite that you might have heard, the mind-numbing complexity of modern
> > computer systems is not due so much to there being multiple CPUs, but
> > rather to there being any CPUs at all.  In short, for the ultimate in
> > computer-system simplicity, the optimal choice is NR_CPUS=0.
> > 
> > This commit therefore limits kernel builds to zero CPUs.  This change
> > has the beneficial side effect of rendering all kernel bugs harmless.
> > Furthermore, this commit enables additional beneficial changes, for
> > example, the removal of those parts of the kernel that are not needed
> > when there are zero CPUs.
> > 
> > Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> > Reviewed-by: Thomas Gleixner <tglx at linutronix.de>
> > ---
> 
> Hmm... I believe you could go one step forward and allow negative values
> as well. Antimatter was proven to exist after all.
> 
> Hint : nr_cpu_ids is an "int", not an "unsigned int"
> 
> Bonus: Existing bugs become "must have" features.

;-) ;-) ;-)

> Of course there is no hurry and this can wait 365 days.

James Bottomley suggested imaginary numbers of CPUs some time back,
and I suppose there is no reason you cannot have fractional numbers of
CPUs, and perhaps irrational numbers as well.  Of course, these last two
would require use of floating-point arithmetic (or something similar)
in the kernel.  So I guess we have at several years worth.  Over to you
for the negative numbers.  ;-)

							Thanx, Paul



From sshtylyov at mvista.com  Sat Mar 31 17:21:59 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sun, 01 Apr 2012 01:21:59 +0400
Subject: [PATCH] ARM: include linux/bug.h in insn.c
In-Reply-To: <1333142002-15431-1-git-send-email-joachim.eastwood@jotron.com>
References: <1333142002-15431-1-git-send-email-joachim.eastwood@jotron.com>
Message-ID: <4F777577.4020305@mvista.com>

Hello.

On 31-03-2012 1:13, Joachim Eastwood wrote:

> After commit d82227cf8 building the kernel fails with:

    Please also specify that commit summary in parens.

>    arch/arm/kernel/insn.c: In function '__arm_gen_branch_thumb2':
>    arch/arm/kernel/insn.c:13: error: implicit declaration of function 'WARN_ON_ONCE'
>    make[1]: *** [arch/arm/kernel/insn.o] Error 1
>    make: *** [arch/arm/kernel] Error 2

> insn.c uses WARN_ON_ONCE so lets include bug.h.

    Let's.

> Signed-off-by: Joachim Eastwood<joachim.eastwood at jotron.com>

WBR, Sergei


From sshtylyov at mvista.com  Sat Mar 31 17:23:30 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sun, 01 Apr 2012 01:23:30 +0400
Subject: [PATCH] ARM: at91: Export at91_ramc_base
In-Reply-To: <4f761fd8.8843cc0a.22b0.6caa@mx.google.com>
References: <4f761fd8.8843cc0a.22b0.6caa@mx.google.com>
Message-ID: <4F7775D2.7050608@mvista.com>

Hello.

On 31-03-2012 1:03, manabian at gmail.com wrote:

> From: Joachim Eastwood<joachim.eastwood at jotron.com>

> After commit f363c407b42c4 building at91_cf as a module fails with:

    Please also specify that commit's summary in parens.

>    ERROR: "at91_ramc_base" [drivers/pcmcia/at91_cf.ko] undefined!
>    make[1]: *** [__modpost] Error 1
>    make: *** [modules] Error 2

> Export at91_ramc_base symbol to allow drivers using at91_ramc_*
> functions to be built as modules again.

> Signed-off-by: Joachim Eastwood<joachim.eastwood at jotron.com>

WBR, Sergei



From sshtylyov at mvista.com  Sat Mar 31 17:38:36 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sun, 01 Apr 2012 01:38:36 +0400
Subject: [PATCH] ARM: at91: include newly created system_misc.h file
In-Reply-To: <1333110669-24554-1-git-send-email-nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
 <1333110669-24554-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <4F77795C.6050109@mvista.com>

Hello.

On 30-03-2012 16:31, Nicolas Ferre wrote:

> system.h file has been split by commit "0195c00".

    Please also specify that commit's summary in parens. And don't put commit 
ID into quoates.

> Now include
> system_misc.h for having access to arm_pm_restart.

> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

WBR, Sergei



From sshtylyov at mvista.com  Sat Mar 31 17:44:32 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sun, 01 Apr 2012 01:44:32 +0400
Subject: [PATCH V2 4/4] Input: pxa27x_keypad add choice to set
 direct_key_mask
In-Reply-To: <1333072698-15344-4-git-send-email-chao.xie@marvell.com>
References: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
 <1333072698-15344-4-git-send-email-chao.xie@marvell.com>
Message-ID: <4F777AC0.8040304@mvista.com>

Hello.

On 30-03-2012 5:58, Chao Xie wrote:

> Direct keys usage may not start from KP_DKIN0, add a msk option
> to configure the specifics for platforms that can skip some keys.

> Change-Id: Ia8fd28254fec9595dcf39f12a78392c1e8b675eb

    Remove this line please -- it has no place in upstream patch.

> Signed-off-by: Chao Xie <chao.xie at marvell.com>

WBR, Sergei


From sshtylyov at mvista.com  Sat Mar 31 17:47:10 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sun, 01 Apr 2012 01:47:10 +0400
Subject: [PATCH V2 1/4] Input: pxa27x_keypad keep clock on as wakeup source
In-Reply-To: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
References: <1333072698-15344-1-git-send-email-chao.xie@marvell.com>
Message-ID: <4F777B5E.5080500@mvista.com>

Hello.

On 30-03-2012 5:58, Chao Xie wrote:

> When the keypad is used as wake up source, the clock can not
> be disabled. Or it can not detect key pressing.
> If the keypad is used as wake up source, when resume back,
> do not enable the clock and configure it again because the
> register content is retained.

> Signed-off-by: Chao Xie<chao.xie at marvell.com>
> ---
>   drivers/input/keyboard/pxa27x_keypad.c |   27 ++++++++++++++++++---------
>   1 files changed, 18 insertions(+), 9 deletions(-)

> diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
> index 29fe1b2..1c5752f 100644
> --- a/drivers/input/keyboard/pxa27x_keypad.c
> +++ b/drivers/input/keyboard/pxa27x_keypad.c
[...]
> @@ -433,19 +437,24 @@ static int pxa27x_keypad_resume(struct device *dev)
>   	struct pxa27x_keypad *keypad = platform_get_drvdata(pdev);
>   	struct input_dev *input_dev = keypad->input_dev;
>
> +	/*
> +	 * If the keypad is used as wake up source, the clock is not turned
> +	 * off. So do not need configure it again.
> +	 */
>   	if (device_may_wakeup(&pdev->dev))
>   		disable_irq_wake(keypad->irq);
> +	else {

    According to CodingStyle, {} should be an all branches of *if* statement, 
if it's used at least in one branch.

WBR, Sergei


From sshtylyov at mvista.com  Sat Mar 31 17:51:43 2012
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sun, 01 Apr 2012 01:51:43 +0400
Subject: [PATCH 03/12] ARM: at91/USB host: specify and handle properly
 vbus_pin_active_low
In-Reply-To: <ce442f466ded5a4c75a0fc15700dc14fe60b91d8.1333026637.git.nicolas.ferre@atmel.com>
References: <cover.1333026637.git.nicolas.ferre@atmel.com>
 <ce442f466ded5a4c75a0fc15700dc14fe60b91d8.1333026637.git.nicolas.ferre@atmel.com>
Message-ID: <4F777C6F.2070603@mvista.com>

Hello.

On 29-03-2012 17:27, Nicolas Ferre wrote:

> Due to an error while handling vbus_pin_active_low in ohci-at91 driver,
> the specification of this property was not good in devices/board files.

> Signed-off-by: Nicolas Ferre<nicolas.ferre at atmel.com>
> Acked-by: Jean-Christophe PLAGNIOL-VILLARD<plagnioj at jcrosoft.com>
> Cc: stable<stable at vger.kernel.org>          [3.2+]
> ---
>   arch/arm/mach-at91/at91sam9263_devices.c |    3 ++-
>   arch/arm/mach-at91/at91sam9g45_devices.c |    6 ++++--
>   arch/arm/mach-at91/board-sam9263ek.c     |    1 +
>   arch/arm/mach-at91/board-sam9m10g45ek.c  |    1 +
>   4 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
> index 53688c4..5cdca89d 100644
> --- a/arch/arm/mach-at91/at91sam9263_devices.c
> +++ b/arch/arm/mach-at91/at91sam9263_devices.c
> @@ -72,7 +72,8 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
>   	/* Enable VBus control for UHP ports */
>   	for (i = 0; i<  data->ports; i++) {
>   		if (gpio_is_valid(data->vbus_pin[i]))
> -			at91_set_gpio_output(data->vbus_pin[i], 0);
> +			at91_set_gpio_output(data->vbus_pin[i],
> +					     data->vbus_pin_active_low[i] ^ 0);

    Note that XOR with 0 is a nop, left operand doesn't change its value.

WBR, Sergei


From linuxppcemb at lkmail.de  Sat Mar 31 18:19:25 2012
From: linuxppcemb at lkmail.de (Lorenz Kolb)
Date: Sun, 01 Apr 2012 00:19:25 +0200
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
In-Reply-To: <20120331212149.GI2450@linux.vnet.ibm.com>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
 <1333227608.2325.4054.camel@edumazet-glaptop>
 <20120331212149.GI2450@linux.vnet.ibm.com>
Message-ID: <4F7782ED.7050407@lkmail.de>

With that patchset in mind, I am working on a really huge patch, which 
will greatly simplify the Linux kernel  for the real problem of having 
that number of CPUs.

That patch will have a lot of changes all over the architectures, so 
what will be the best way to post it? Should I split it architecture 
dependend and into one generic part.

Currently it is a large blob of millions of changes, but will greatly 
simplify the Linux kernel.

Regards,

Lorenz Kolb

Am 31.03.2012 23:21, schrieb Paul E. McKenney:
> On Sat, Mar 31, 2012 at 11:00:08PM +0200, Eric Dumazet wrote:
>    
>> On Sun, 2012-04-01 at 00:33 +0800, Paul E. McKenney wrote:
>>      
>>> Although there have been numerous complaints about the complexity of
>>> parallel programming (especially over the past 5-10 years), the plain
>>> truth is that the incremental complexity of parallel programming over
>>> that of sequential programming is not as large as is commonly believed.
>>> Despite that you might have heard, the mind-numbing complexity of modern
>>> computer systems is not due so much to there being multiple CPUs, but
>>> rather to there being any CPUs at all.  In short, for the ultimate in
>>> computer-system simplicity, the optimal choice is NR_CPUS=0.
>>>
>>> This commit therefore limits kernel builds to zero CPUs.  This change
>>> has the beneficial side effect of rendering all kernel bugs harmless.
>>> Furthermore, this commit enables additional beneficial changes, for
>>> example, the removal of those parts of the kernel that are not needed
>>> when there are zero CPUs.
>>>
>>> Signed-off-by: Paul E. McKenney<paulmck at linux.vnet.ibm.com>
>>> Reviewed-by: Thomas Gleixner<tglx at linutronix.de>
>>> ---
>>>        
>> Hmm... I believe you could go one step forward and allow negative values
>> as well. Antimatter was proven to exist after all.
>>
>> Hint : nr_cpu_ids is an "int", not an "unsigned int"
>>
>> Bonus: Existing bugs become "must have" features.
>>      
> ;-) ;-) ;-)
>
>    
>> Of course there is no hurry and this can wait 365 days.
>>      
> James Bottomley suggested imaginary numbers of CPUs some time back,
> and I suppose there is no reason you cannot have fractional numbers of
> CPUs, and perhaps irrational numbers as well.  Of course, these last two
> would require use of floating-point arithmetic (or something similar)
> in the kernel.  So I guess we have at several years worth.  Over to you
> for the negative numbers.  ;-)
>
> 							Thanx, Paul
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>    



From linux at arm.linux.org.uk  Sat Mar 31 18:32:00 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 31 Mar 2012 23:32:00 +0100
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
In-Reply-To: <20120331163321.GA15809@linux.vnet.ibm.com>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
Message-ID: <20120331223200.GA32482@n2100.arm.linux.org.uk>

On Sun, Apr 01, 2012 at 12:33:21AM +0800, Paul E. McKenney wrote:
> Although there have been numerous complaints about the complexity of
> parallel programming (especially over the past 5-10 years), the plain
> truth is that the incremental complexity of parallel programming over
> that of sequential programming is not as large as is commonly believed.
> Despite that you might have heard, the mind-numbing complexity of modern
> computer systems is not due so much to there being multiple CPUs, but
> rather to there being any CPUs at all.  In short, for the ultimate in
> computer-system simplicity, the optimal choice is NR_CPUS=0.
> 
> This commit therefore limits kernel builds to zero CPUs.  This change
> has the beneficial side effect of rendering all kernel bugs harmless.
> Furthermore, this commit enables additional beneficial changes, for
> example, the removal of those parts of the kernel that are not needed
> when there are zero CPUs.
> 
> Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> Reviewed-by: Thomas Gleixner <tglx at linutronix.de>

Great work, but I don't think you've gone far enough with this.

What would really help is if you could consolidate all these NR_CPUS
definitions into one place so we don't have essentially the same thing
scattered across all these architectures.  We're already doing this on
ARM across our platforms, and its about time such an approach was taken
across the entire kernel tree.

It looks like the MIPS solution would be the best one to pick.
Could you rework your patch to do this please?

While you're at it, you might like to consider that having zero CPUs
makes all this architecture support redundant, so maybe you've missed
a trick there - according to my count, we could get rid of almost 3
million lines of code from arch.  We could replace all that with a
single standard implementation.

Bah, maybe I shouldn't have pushed that bpf_jit code for ARM after all...


From paulmck at linux.vnet.ibm.com  Sat Mar 31 18:34:09 2012
From: paulmck at linux.vnet.ibm.com (Paul E. McKenney)
Date: Sat, 31 Mar 2012 15:34:09 -0700
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state space
In-Reply-To: <4F7782ED.7050407@lkmail.de>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
 <1333227608.2325.4054.camel@edumazet-glaptop>
 <20120331212149.GI2450@linux.vnet.ibm.com>
 <4F7782ED.7050407@lkmail.de>
Message-ID: <20120331223409.GM2450@linux.vnet.ibm.com>

On Sun, Apr 01, 2012 at 12:19:25AM +0200, Lorenz Kolb wrote:
> With that patchset in mind, I am working on a really huge patch,
> which will greatly simplify the Linux kernel  for the real problem
> of having that number of CPUs.
> 
> That patch will have a lot of changes all over the architectures, so
> what will be the best way to post it? Should I split it architecture
> dependend and into one generic part.
> 
> Currently it is a large blob of millions of changes, but will
> greatly simplify the Linux kernel.

Perhaps a branch on a public git tree?  If you are doing what I suspect
you are, you will end up with a very large patch set.  ;-)

							Thanx, Paul

> Regards,
> 
> Lorenz Kolb
> 
> Am 31.03.2012 23:21, schrieb Paul E. McKenney:
> >On Sat, Mar 31, 2012 at 11:00:08PM +0200, Eric Dumazet wrote:
> >>On Sun, 2012-04-01 at 00:33 +0800, Paul E. McKenney wrote:
> >>>Although there have been numerous complaints about the complexity of
> >>>parallel programming (especially over the past 5-10 years), the plain
> >>>truth is that the incremental complexity of parallel programming over
> >>>that of sequential programming is not as large as is commonly believed.
> >>>Despite that you might have heard, the mind-numbing complexity of modern
> >>>computer systems is not due so much to there being multiple CPUs, but
> >>>rather to there being any CPUs at all.  In short, for the ultimate in
> >>>computer-system simplicity, the optimal choice is NR_CPUS=0.
> >>>
> >>>This commit therefore limits kernel builds to zero CPUs.  This change
> >>>has the beneficial side effect of rendering all kernel bugs harmless.
> >>>Furthermore, this commit enables additional beneficial changes, for
> >>>example, the removal of those parts of the kernel that are not needed
> >>>when there are zero CPUs.
> >>>
> >>>Signed-off-by: Paul E. McKenney<paulmck at linux.vnet.ibm.com>
> >>>Reviewed-by: Thomas Gleixner<tglx at linutronix.de>
> >>>---
> >>Hmm... I believe you could go one step forward and allow negative values
> >>as well. Antimatter was proven to exist after all.
> >>
> >>Hint : nr_cpu_ids is an "int", not an "unsigned int"
> >>
> >>Bonus: Existing bugs become "must have" features.
> >;-) ;-) ;-)
> >
> >>Of course there is no hurry and this can wait 365 days.
> >James Bottomley suggested imaginary numbers of CPUs some time back,
> >and I suppose there is no reason you cannot have fractional numbers of
> >CPUs, and perhaps irrational numbers as well.  Of course, these last two
> >would require use of floating-point arithmetic (or something similar)
> >in the kernel.  So I guess we have at several years worth.  Over to you
> >for the negative numbers.  ;-)
> >
> >							Thanx, Paul
> >
> >_______________________________________________
> >Linuxppc-dev mailing list
> >Linuxppc-dev at lists.ozlabs.org
> >https://lists.ozlabs.org/listinfo/linuxppc-dev
> 



From jonsmirl at gmail.com  Sat Mar 31 19:12:43 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Sat, 31 Mar 2012 19:12:43 -0400
Subject: ioremap to a specific virtual address
In-Reply-To: <alpine.LFD.2.02.1203222348210.24151@xanadu.home>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <alpine.LFD.2.02.1203222348210.24151@xanadu.home>
Message-ID: <CAKON4OxVpV-2DGVswc2y+6B6LhLzkhn0ohpSEmDBCVoaNJ4vww@mail.gmail.com>

On Fri, Mar 23, 2012 at 12:00 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Thu, 22 Mar 2012, jonsmirl at gmail.com wrote:
>
>> When iotable is used to initially map memory you can specify the
>> mapping address. In this case IO_SDMMC_PHYS is 0x18000000 and it gets
>> mapped to ?0xf1800000
>>
>> NXP has supplied this handly macro
>> #define io_p2v(x) (0xf0000000 | (((x) & 0xff000000) >> 4) | ((x) & 0x000fffff))
>>
>> iotable_init(lpc313x_io_desc, ARRAY_SIZE(lpc313x_io_desc));
>>
>> ? ? ? {
>> ? ? ? ? ? ? ? .virtual ? ? ? ?= io_p2v(IO_SDMMC_PHYS),
>> ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(IO_SDMMC_PHYS),
>> ? ? ? ? ? ? ? .length ? ? ? ? = IO_SDMMC_SIZE,
>> ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE
>> ? ? ? },
>>
>> The supplied kernel is full of code that uses this type of addressing.
>> It has macros for register definition that all depend on the registers
>> being mapped to a well know location - io_p2v(x).
>>
>> I'd like to move the map out of the core code and into the SDMMC
>> device driver and then only do it if the driver loads.
>
> Why would you do that? ?Those static mappings are meant to be global and
> remain there. ?The handy macro is in fact not handy at all as it forces
> virtual addresses on you.
>
> It is OK to keep the static mappings as you can use 1MB regions and the
> mapping code will use first level mappings which are better with TLB
> usage.

I switched over to 1MB mappings. 1MB map regions are implemented on
ARM9, right? Is there some way to see if I got the huge maps?

-- 
Jon Smirl
jonsmirl at gmail.com


From nico at fluxnic.net  Sat Mar 31 19:52:31 2012
From: nico at fluxnic.net (Nicolas Pitre)
Date: Sat, 31 Mar 2012 19:52:31 -0400 (EDT)
Subject: ioremap to a specific virtual address
In-Reply-To: <CAKON4OxVpV-2DGVswc2y+6B6LhLzkhn0ohpSEmDBCVoaNJ4vww@mail.gmail.com>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <alpine.LFD.2.02.1203222348210.24151@xanadu.home>
 <CAKON4OxVpV-2DGVswc2y+6B6LhLzkhn0ohpSEmDBCVoaNJ4vww@mail.gmail.com>
Message-ID: <alpine.LFD.2.02.1203311943500.24151@xanadu.home>

On Sat, 31 Mar 2012, jonsmirl at gmail.com wrote:

> On Fri, Mar 23, 2012 at 12:00 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> > On Thu, 22 Mar 2012, jonsmirl at gmail.com wrote:
> >
> >> When iotable is used to initially map memory you can specify the
> >> mapping address. In this case IO_SDMMC_PHYS is 0x18000000 and it gets
> >> mapped to ?0xf1800000
> >>
> >> NXP has supplied this handly macro
> >> #define io_p2v(x) (0xf0000000 | (((x) & 0xff000000) >> 4) | ((x) & 0x000fffff))
> >>
> >> iotable_init(lpc313x_io_desc, ARRAY_SIZE(lpc313x_io_desc));
> >>
> >> ? ? ? {
> >> ? ? ? ? ? ? ? .virtual ? ? ? ?= io_p2v(IO_SDMMC_PHYS),
> >> ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(IO_SDMMC_PHYS),
> >> ? ? ? ? ? ? ? .length ? ? ? ? = IO_SDMMC_SIZE,
> >> ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE
> >> ? ? ? },
> >>
> >> The supplied kernel is full of code that uses this type of addressing.
> >> It has macros for register definition that all depend on the registers
> >> being mapped to a well know location - io_p2v(x).
> >>
> >> I'd like to move the map out of the core code and into the SDMMC
> >> device driver and then only do it if the driver loads.
> >
> > Why would you do that? ?Those static mappings are meant to be global and
> > remain there. ?The handy macro is in fact not handy at all as it forces
> > virtual addresses on you.
> >
> > It is OK to keep the static mappings as you can use 1MB regions and the
> > mapping code will use first level mappings which are better with TLB
> > usage.
> 
> I switched over to 1MB mappings. 1MB map regions are implemented on
> ARM9, right? Is there some way to see if I got the huge maps?

Once booted, you can look in /proc/vmallocinfo for the mappings in use.

There is no way to know for sure if the first level pagetable mappings 
are actually used, unless you instrument the kernel code.  But yes, all 
ARM architectures with a MMU support 1MB regions.


Nicolas

From jonsmirl at gmail.com  Sat Mar 31 20:08:31 2012
From: jonsmirl at gmail.com (jonsmirl at gmail.com)
Date: Sat, 31 Mar 2012 20:08:31 -0400
Subject: ioremap to a specific virtual address
In-Reply-To: <alpine.LFD.2.02.1203311943500.24151@xanadu.home>
References: <CAKON4Ox5YXvbGwbsYRetOPxV+HVDwmEd-mbqj2fyDfnCcBjaRA@mail.gmail.com>
 <alpine.LFD.2.02.1203222348210.24151@xanadu.home>
 <CAKON4OxVpV-2DGVswc2y+6B6LhLzkhn0ohpSEmDBCVoaNJ4vww@mail.gmail.com>
 <alpine.LFD.2.02.1203311943500.24151@xanadu.home>
Message-ID: <CAKON4OzohgrZ2k0ddhDrOTqumRYizf-aLUhWdcZstD-7QTYYZg@mail.gmail.com>

On Sat, Mar 31, 2012 at 7:52 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Sat, 31 Mar 2012, jonsmirl at gmail.com wrote:
>
>> On Fri, Mar 23, 2012 at 12:00 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
>> > On Thu, 22 Mar 2012, jonsmirl at gmail.com wrote:
>> >
>> >> When iotable is used to initially map memory you can specify the
>> >> mapping address. In this case IO_SDMMC_PHYS is 0x18000000 and it gets
>> >> mapped to ?0xf1800000
>> >>
>> >> NXP has supplied this handly macro
>> >> #define io_p2v(x) (0xf0000000 | (((x) & 0xff000000) >> 4) | ((x) & 0x000fffff))
>> >>
>> >> iotable_init(lpc313x_io_desc, ARRAY_SIZE(lpc313x_io_desc));
>> >>
>> >> ? ? ? {
>> >> ? ? ? ? ? ? ? .virtual ? ? ? ?= io_p2v(IO_SDMMC_PHYS),
>> >> ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(IO_SDMMC_PHYS),
>> >> ? ? ? ? ? ? ? .length ? ? ? ? = IO_SDMMC_SIZE,
>> >> ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE
>> >> ? ? ? },
>> >>
>> >> The supplied kernel is full of code that uses this type of addressing.
>> >> It has macros for register definition that all depend on the registers
>> >> being mapped to a well know location - io_p2v(x).
>> >>
>> >> I'd like to move the map out of the core code and into the SDMMC
>> >> device driver and then only do it if the driver loads.
>> >
>> > Why would you do that? ?Those static mappings are meant to be global and
>> > remain there. ?The handy macro is in fact not handy at all as it forces
>> > virtual addresses on you.
>> >
>> > It is OK to keep the static mappings as you can use 1MB regions and the
>> > mapping code will use first level mappings which are better with TLB
>> > usage.
>>
>> I switched over to 1MB mappings. 1MB map regions are implemented on
>> ARM9, right? Is there some way to see if I got the huge maps?
>
> Once booted, you can look in /proc/vmallocinfo for the mappings in use.
>
> There is no way to know for sure if the first level pagetable mappings
> are actually used, unless you instrument the kernel code. ?But yes, all
> ARM architectures with a MMU support 1MB regions.

Looks good, way cleaner than my x86 desktop which is full of 8KB
mappings. On my ARM I had about 50 regions before since I was mapping
each device individually.

root at OpenWrt:/proc# cat vmallocinfo
0xc4804000-0xc4810000   49152 cramfs_uncompress_init+0x24/0x60 pages=11 vmalloc
0xc4810000-0xc4853000  274432 jffs2_zlib_init+0x14/0xa4 pages=66 vmalloc
0xc4853000-0xc485f000   49152 jffs2_zlib_init+0x48/0xa4 pages=11 vmalloc
0xc485f000-0xc4886000  159744 ssd1289_probe+0x250/0x85c pages=38 vmalloc
0xf1300000-0xf1400000 1048576 iotable_init+0x0/0xb0 phys=13000000 ioremap
0xf1500000-0xf1600000 1048576 iotable_init+0x0/0xb0 phys=15000000 ioremap
0xf1600000-0xf1700000 1048576 iotable_init+0x0/0xb0 phys=16000000 ioremap
0xf1700000-0xf1800000 1048576 iotable_init+0x0/0xb0 phys=17000000 ioremap
0xf1800000-0xf1900000 1048576 iotable_init+0x0/0xb0 phys=18000000 ioremap
0xf1900000-0xf1a00000 1048576 iotable_init+0x0/0xb0 phys=19000000 ioremap
0xf2000000-0xf2100000 1048576 iotable_init+0x0/0xb0 phys=20000000 ioremap
0xf6000000-0xf6100000 1048576 iotable_init+0x0/0xb0 phys=60000000 ioremap
0xf7000000-0xf7100000 1048576 iotable_init+0x0/0xb0 phys=70000000 ioremap
root at OpenWrt:/proc#

-- 
Jon Smirl
jonsmirl at gmail.com


From cjb at laptop.org  Sat Mar 31 21:12:39 2012
From: cjb at laptop.org (Chris Ball)
Date: Sat, 31 Mar 2012 21:12:39 -0400
Subject: [PATCH v3 0/6] mmc: sdhci-s3c: Rework platform data and add
 device tree support
In-Reply-To: <4F73D3D7.1010202@samsung.com> (Kukjin Kim's message of "Wed, 28
 Mar 2012 20:15:35 -0700")
References: <1328032576-9269-1-git-send-email-thomas.abraham@linaro.org>
 <003401cce730$baf979a0$30ec6ce0$%kim@samsung.com>
 <m2aa4pkq5g.fsf@bob.laptop.org> <4F3CFEED.6060206@samsung.com>
 <m239abgc32.fsf@bob.laptop.org>
 <00b901ccf08d$2fc18b50$8f44a1f0$%kim@samsung.com>
 <m2vcn0496y.fsf@bob.laptop.org> <87k426vy9r.fsf@laptop.org>
 <20120328095450.GA23005@sirena.org.uk> <4F73D3D7.1010202@samsung.com>
Message-ID: <87zkawmf08.fsf@laptop.org>

Hi Kukjin,

On Wed, Mar 28 2012, Kukjin Kim wrote:
>>> As a result I'm dropping this tree -- and all of the patches that I
>>> have on top of it -- from mmc-next so that I can get a pull request
>>> out.  This means that I'm dropping:
>>
> Hmm, I think, if you're ok, you can send a second pull request to
> Linus for it and actually, it is in linux-next for a long time via mmc
> and samsung tree.
>
> Note, please don't rebase it because its resolution for conflicts is
> in linux-next and I think Linus will use it when happens
> conflicts...Or I can provide new tree on top of latest mainline. But
> I'm not sure about latter.

I can't send the tree as it is to Linus now, because Arnd has asked us
to hold off on these device tree bindings and work with the unified
bindings he's proposing instead.  (Rebasing to drop that patch will
introduce new conflicts.)

I'm going to send Mark Brown's two patches to Linus now, even though it
will cause a conflict in -next.  The rest (other than the device tree
bindings) are mergable after -rc1, because they're fixes, so we'll
eventually get everything except DT in to 3.4.  I think you should
just drop this patchset from your tree in linux-next entirely now.

Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From richard.zhao at freescale.com  Sat Mar 31 21:20:58 2012
From: richard.zhao at freescale.com (Richard Zhao)
Date: Sun, 1 Apr 2012 09:20:58 +0800
Subject: [PATCH 0/2] change lpj in arm smp common code
In-Reply-To: <87sjhtec0w.fsf@ti.com>
References: <1330499895-12364-1-git-send-email-richard.zhao@linaro.org>
 <87sjhtec0w.fsf@ti.com>
Message-ID: <20120401012057.GC2603@b20223-02.ap.freescale.net>

On Wed, Feb 29, 2012 at 10:21:19AM -0800, Kevin Hilman wrote:
> Richard Zhao <richard.zhao at linaro.org> writes:
> 
> > The two patches were originally in [PATCH V6 0/7] add a generic cpufreq driver.
> > I seperated them and hope they can go to upstream earlier.
> >
> > Richard Zhao (2):
> >   ARM: add cpufreq transiton notifier to adjust loops_per_jiffy for smp
> >   cpufreq: OMAP: remove loops_per_jiffy recalculate for smp
> 
> The first one should go into Russell's patch system.  Once he queues
> that, I can queue the OMAP one for the CPUfreq maintainer.
Hi Russel & Kevin,

Could you double check whether you've picked the patch searies?
I can not find them in 3.4rc.

Thanks
Richard
> 
> Kevin
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From paulmck at linux.vnet.ibm.com  Sat Mar 31 21:22:12 2012
From: paulmck at linux.vnet.ibm.com (Paul E. McKenney)
Date: Sat, 31 Mar 2012 18:22:12 -0700
Subject: [PATCH RFC] Simplify the Linux kernel by reducing its state	space
In-Reply-To: <20120331223200.GA32482@n2100.arm.linux.org.uk>
References: <20120331163321.GA15809@linux.vnet.ibm.com>
 <20120331223200.GA32482@n2100.arm.linux.org.uk>
Message-ID: <20120401012212.GP2450@linux.vnet.ibm.com>

On Sat, Mar 31, 2012 at 11:32:00PM +0100, Russell King - ARM Linux wrote:
> On Sun, Apr 01, 2012 at 12:33:21AM +0800, Paul E. McKenney wrote:
> > Although there have been numerous complaints about the complexity of
> > parallel programming (especially over the past 5-10 years), the plain
> > truth is that the incremental complexity of parallel programming over
> > that of sequential programming is not as large as is commonly believed.
> > Despite that you might have heard, the mind-numbing complexity of modern
> > computer systems is not due so much to there being multiple CPUs, but
> > rather to there being any CPUs at all.  In short, for the ultimate in
> > computer-system simplicity, the optimal choice is NR_CPUS=0.
> > 
> > This commit therefore limits kernel builds to zero CPUs.  This change
> > has the beneficial side effect of rendering all kernel bugs harmless.
> > Furthermore, this commit enables additional beneficial changes, for
> > example, the removal of those parts of the kernel that are not needed
> > when there are zero CPUs.
> > 
> > Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> > Reviewed-by: Thomas Gleixner <tglx at linutronix.de>
> 
> Great work, but I don't think you've gone far enough with this.
> 
> What would really help is if you could consolidate all these NR_CPUS
> definitions into one place so we don't have essentially the same thing
> scattered across all these architectures.  We're already doing this on
> ARM across our platforms, and its about time such an approach was taken
> across the entire kernel tree.
> 
> It looks like the MIPS solution would be the best one to pick.
> Could you rework your patch to do this please?
> 
> While you're at it, you might like to consider that having zero CPUs
> makes all this architecture support redundant, so maybe you've missed
> a trick there - according to my count, we could get rid of almost 3
> million lines of code from arch.  We could replace all that with a
> single standard implementation.
> 
> Bah, maybe I shouldn't have pushed that bpf_jit code for ARM after all...

;-) ;-) ;-)

							Thanx, Paul



From tom.leiming at gmail.com  Sat Mar 31 21:39:03 2012
From: tom.leiming at gmail.com (Ming Lei)
Date: Sun, 1 Apr 2012 09:39:03 +0800
Subject: [PATCH 1/3] ARM: OMAP2+: 32k-counter: Use hwmod lookup to check
 presence of 32k timer
In-Reply-To: <CAMQu2gwuRpZ133962r3N4Y4K3oQ88ySa=SyoS6v=sSHGA=SGKw@mail.gmail.com>
References: <1326983304-14619-1-git-send-email-hvaibhav@ti.com>
 <1326983304-14619-2-git-send-email-hvaibhav@ti.com>
 <87mx9ej8fp.fsf@ti.com>
 <CACVXFVOqmC0OhT-Dim8dL9pWnmGwO2-Awc4V2Jziyf7DHQdYcQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83181EF3F@DBDE01.ent.ti.com>
 <CACVXFVP4J8N271Tww77Btm9fGNiP17MepjswBJ0V-8Z4sNt8Eg@mail.gmail.com>
 <4F672364.3020403@ti.com>
 <79CD15C6BA57404B839C016229A409A83182386C@DBDE01.ent.ti.com>
 <CAMQu2gyFNXgx87Fsq5is88DOkOx-nWK6ohwyFV-CY2uTkZCGMA@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EA54@DBDE01.ent.ti.com>
 <CAMQu2gyF83HJOE9Rf-fZXXMt=p_WFjFf3DpAeW8L8+htR4E6-g@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A83183EB47@DBDE01.ent.ti.com>
 <CAMQu2gzYULK+=6-WKQnnQDpzTYW7xKAOZo7obyu2q178jtNE-Q@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840C2E@DBDE01.ent.ti.com>
 <CAMQu2gw7aceHSYSd+UMVS6kHQMqy0_maf8QTJaUMzp9z8822rQ@mail.gmail.com>
 <79CD15C6BA57404B839C016229A409A831840E0C@DBDE01.ent.ti.com>
 <4F7570FC.8000907@ti.com>
 <79CD15C6BA57404B839C016229A409A831840F82@DBDE01.ent.ti.com>
 <CAMQu2gzOkE6LD0WZ_9bKe3J-=Dv89rWaMzvWWvJHPMSPe6MzNg@mail.gmail.com>
 <CACVXFVPbU2OqTN=S0AZCD10KuSBYxqyyRH_xee+WTaCD6VSmMQ@mail.gmail.com>
 <CAMQu2gzuQ-q+3RHsW0=U305jCF-td5-PEXkGZ6WnQTqA1K8oAQ@mail.gmail.com>
 <CACVXFVPu1GEQy+sCgXMB8JCszPBBs8zHRVm94TYb1-y2afkqgw@mail.gmail.com>
 <CAMQu2gwuRpZ133962r3N4Y4K3oQ88ySa=SyoS6v=sSHGA=SGKw@mail.gmail.com>
Message-ID: <CACVXFVMjSPhF_+CfbF2vD5ts+WtZGjofEWmknB0D1OpTM7geZw@mail.gmail.com>

On Sun, Apr 1, 2012 at 3:10 AM, Shilimkar, Santosh
<santosh.shilimkar at ti.com> wrote:
> On Sat, Mar 31, 2012 at 2:09 PM, Ming Lei <tom.leiming at gmail.com> wrote:
>> On Sat, Mar 31, 2012 at 2:30 PM, Shilimkar, Santosh
>>> Since you need to recompile the kernel, you can very much tweak the
>>> clocksource to use GPTIMER with sysl clock. Support for that is still
>>> in place.
>>
>> With current kernel, running 'make menuconfig' can do it, but after applying
>> Hiremath's patch[1], I have to edit the source code manually to get it, so looks
>> this kind of tweaking is not friendly enough, :-(
>>
> It's not friendly but doable. But above can be supported I guess.
>
> Since you are talking about doing menuconfig
> and rebuilding kernel so what can be done is when one disable CPUIDLE
> and PM, one can disabled 32K source as well. And then 32K clocksource
> init should fail and fallback on gptimer clock source.

OK, it should work, but looks OMAP_32K_TIMER option has to be kept
for the usage, which may be a bit divergent to the purpose of the patch set.

So how about introducing a kernel parameter to decide if bypassing
32K source and using gptimer source directly, and let which depend
on PM?

>
> Vaibhav,
> Can you update your patch to support above. The patch which I
> did was doing exactly that but was not using hwmod. The problem with your
> patch is synctimer hwmod lookup on OMAP will never fail if the hwmod
> entry is supported.
>
> So you might better use failure case of omap_init_clocksource_32k() for
> fall back on gptimer source as I tried in my patch. That should support

You patch still doesn't work for the usage because you removed 32K option.


Thanks,
-- 
Ming Lei


From shawn.guo at linaro.org  Sat Mar 31 21:39:49 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sun, 1 Apr 2012 09:39:49 +0800
Subject: [PATCH v4 1/1] ARM: imx28: add basic dt support
In-Reply-To: <1333200417-11259-1-git-send-email-b29396@freescale.com>
References: <1333200417-11259-1-git-send-email-b29396@freescale.com>
Message-ID: <20120401013946.GB2395@S2101-09.ap.freescale.net>

On Sat, Mar 31, 2012 at 09:26:57PM +0800, Dong Aisheng wrote:
> From: Dong Aisheng <dong.aisheng at linaro.org>
> 
> This patch includes basic dt support which can boot via nfs rootfs.
> 
> Signed-off-by: Dong Aisheng <dong.aisheng at linaro.org>
> ---
> ChangeLog v3->v4:
>  * update to use irq_domain_add_legacy
> ChangeLog v2->v3:
>  * Some minor fixes suggested by Shawn Guo
> ChangeLog v1->v2:
>  * Some fixes addressed Rob's review comments.
>    Remove using of OF_DEV_AUXDATA.
>  * Remove mac address from dts file
>    Currently we use the mac address got from uboot to work.
>    Will submit a p separate atch using prom_update_property to fix this
>    issue for driver based on suggestions from Grant and Lothar.
>  * rename mxs-dt.c to mach-mxs.c which is supposed to support mx23 dt
>    too in the future.
>  * add compatible string "fsl,imx28" per Sascha's suggestion
>  * add more devices in dtsi file
>    For those devices still not in use, set the state to "disabled"
>    by default.
> ---
>  Documentation/devicetree/bindings/arm/fsl.txt |    4 +
>  arch/arm/boot/dts/imx28-evk.dts               |   34 +++
>  arch/arm/boot/dts/imx28.dtsi                  |  356 +++++++++++++++++++++++++
>  arch/arm/mach-mxs/Kconfig                     |   10 +
>  arch/arm/mach-mxs/Makefile                    |    1 +
>  arch/arm/mach-mxs/clock-mx28.c                |    4 +
>  arch/arm/mach-mxs/devices/Kconfig             |    1 -
>  arch/arm/mach-mxs/mach-mxs.c                  |   68 +++++
>  8 files changed, 477 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/boot/dts/imx28-evk.dts
>  create mode 100644 arch/arm/boot/dts/imx28.dtsi
>  create mode 100644 arch/arm/mach-mxs/mach-mxs.c
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> index bfbc771..fecb580 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -1,6 +1,10 @@
>  Freescale i.MX Platforms Device Tree Bindings
>  -----------------------------------------------
>  
> +i.MX28 Evaluation Kit
> +Required root node properties:
> +    - compatible = "fsl,imx28-evk", "fsl,imx28";
> +
>  i.MX51 Babbage Board
>  Required root node properties:
>      - compatible = "fsl,imx51-babbage", "fsl,imx51";
> diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
> new file mode 100644
> index 0000000..57703ec
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx28-evk.dts
> @@ -0,0 +1,34 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +/include/ "imx28.dtsi"
> +
> +/ {
> +	model = "Freescale i.MX28 Evaluation Kit";
> +	compatible = "fsl,imx28-evk", "fsl,imx28";
> +
> +	memory {
> +		reg = <0x40000000 0x08000000>;
> +	};
> +
> +	ahb at 80080000 {
> +		ethernet at 800f0000 {
> +			phy-mode = "rmii";
> +			status = "okay";
> +		};
> +
> +		ethernet at 800f4000 {
> +			phy-mode = "rmii";
> +			status = "okay";
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> new file mode 100644
> index 0000000..d1f4f8c
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -0,0 +1,356 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> +	interrupt-parent = <&icoll>;
> +
> +	aliases {
> +		serial0 = &duart;

This is not really needed, since there is only one instance duart.
And it really should be reserved for auart, which gets 5 instances.

I removed it and applied the patch.  Thanks.

Regards,
Shawn

> +	};
> +
> +	cpus {
> +		cpu at 0 {
> +			compatible = "arm,arm926ejs";
> +		};
> +	};
> +
> +	apb at 80000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x80000000 0x80000>;
> +		ranges;
> +
> +		apbh at 80000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x80000000 0x3c900>;
> +			ranges;
> +
> +			icoll: interrupt-controller at 80000000 {
> +				compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +				reg = <0x80000000 0x2000>;
> +			};
> +
> +			hsadc at 80002000 {
> +				reg = <0x80002000 2000>;
> +				interrupts = <13 87>;
> +				status = "disabled";
> +			};
> +
> +			dma-apbh at 80004000 {
> +				reg = <0x80004000 2000>;
> +				status = "disabled";
> +			};
> +
> +			perfmon at 80006000 {
> +				reg = <0x80006000 800>;
> +				interrupts = <27>;
> +				status = "disabled";
> +			};
> +
> +			bch at 8000a000 {
> +				reg = <0x8000a000 2000>;
> +				interrupts = <41>;
> +				status = "disabled";
> +			};
> +
> +			gpmi at 8000c000 {
> +				reg = <0x8000c000 2000>;
> +				interrupts = <42 88>;
> +				status = "disabled";
> +			};
> +
> +			ssp at 80010000 {
> +				reg = <0x80010000 2000>;
> +				interrupts = <96 82>;
> +				status = "disabled";
> +			};
> +
> +			ssp at 80012000 {
> +				reg = <0x80012000 2000>;
> +				interrupts = <97 83>;
> +				status = "disabled";
> +			};
> +
> +			ssp at 80014000 {
> +				reg = <0x80014000 2000>;
> +				interrupts = <98 84>;
> +				status = "disabled";
> +			};
> +
> +			ssp at 80016000 {
> +				reg = <0x80016000 2000>;
> +				interrupts = <99 85>;
> +				status = "disabled";
> +			};
> +
> +			pinctrl at 80018000 {
> +				reg = <0x80018000 2000>;
> +				status = "disabled";
> +			};
> +
> +			digctl at 8001c000 {
> +				reg = <0x8001c000 2000>;
> +				interrupts = <89>;
> +				status = "disabled";
> +			};
> +
> +			etm at 80022000 {
> +				reg = <0x80022000 2000>;
> +				status = "disabled";
> +			};
> +
> +			dma-apbx at 80024000 {
> +				reg = <0x80024000 2000>;
> +				status = "disabled";
> +			};
> +
> +			dcp at 80028000 {
> +				reg = <0x80028000 2000>;
> +				interrupts = <52 53 54>;
> +				status = "disabled";
> +			};
> +
> +			pxp at 8002a000 {
> +				reg = <0x8002a000 2000>;
> +				interrupts = <39>;
> +				status = "disabled";
> +			};
> +
> +			ocotp at 8002c000 {
> +				reg = <0x8002c000 2000>;
> +				status = "disabled";
> +			};
> +
> +			axi-ahb at 8002e000 {
> +				reg = <0x8002e000 2000>;
> +				status = "disabled";
> +			};
> +
> +			lcdif at 80030000 {
> +				reg = <0x80030000 2000>;
> +				interrupts = <38 86>;
> +				status = "disabled";
> +			};
> +
> +			can at 80032000 {
> +				reg = <0x80032000 2000>;
> +				interrupts = <8>;
> +				status = "disabled";
> +			};
> +
> +			can at 80034000 {
> +				reg = <0x80034000 2000>;
> +				interrupts = <9>;
> +				status = "disabled";
> +			};
> +
> +			simdbg at 8003c000 {
> +				reg = <0x8003c000 200>;
> +				status = "disabled";
> +			};
> +
> +			simgpmisel at 8003c200 {
> +				reg = <0x8003c200 100>;
> +				status = "disabled";
> +			};
> +
> +			simsspsel at 8003c300 {
> +				reg = <0x8003c300 100>;
> +				status = "disabled";
> +			};
> +
> +			simmemsel at 8003c400 {
> +				reg = <0x8003c400 100>;
> +				status = "disabled";
> +			};
> +
> +			gpiomon at 8003c500 {
> +				reg = <0x8003c500 100>;
> +				status = "disabled";
> +			};
> +
> +			simenet at 8003c700 {
> +				reg = <0x8003c700 100>;
> +				status = "disabled";
> +			};
> +
> +			armjtag at 8003c800 {
> +				reg = <0x8003c800 100>;
> +				status = "disabled";
> +			};
> +                };
> +
> +		apbx at 80040000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x80040000 0x40000>;
> +			ranges;
> +
> +			clkctl at 80040000 {
> +				reg = <0x80040000 2000>;
> +				status = "disabled";
> +			};
> +
> +			saif at 80042000 {
> +				reg = <0x80042000 2000>;
> +				interrupts = <59 80>;
> +				status = "disabled";
> +			};
> +
> +			power at 80044000 {
> +				reg = <0x80044000 2000>;
> +				status = "disabled";
> +			};
> +
> +			saif at 80046000 {
> +				reg = <0x80046000 2000>;
> +				interrupts = <58 81>;
> +				status = "disabled";
> +			};
> +
> +			lradc at 80050000 {
> +				reg = <0x80050000 2000>;
> +				status = "disabled";
> +			};
> +
> +			spdif at 80054000 {
> +				reg = <0x80054000 2000>;
> +				interrupts = <45 66>;
> +				status = "disabled";
> +			};
> +
> +			rtc at 80056000 {
> +				reg = <0x80056000 2000>;
> +				interrupts = <28 29>;
> +				status = "disabled";
> +			};
> +
> +			i2c at 80058000 {
> +				reg = <0x80058000 2000>;
> +				interrupts = <111 68>;
> +				status = "disabled";
> +			};
> +
> +			i2c at 8005a000 {
> +				reg = <0x8005a000 2000>;
> +				interrupts = <110 69>;
> +				status = "disabled";
> +			};
> +
> +			pwm at 80064000 {
> +				reg = <0x80064000 2000>;
> +				status = "disabled";
> +			};
> +
> +			timrot at 80068000 {
> +				reg = <0x80068000 2000>;
> +				status = "disabled";
> +			};
> +
> +			serial at 8006a000 {
> +				reg = <0x8006a000 0x2000>;
> +				interrupts = <112 70 71>;
> +				status = "disabled";
> +			};
> +
> +			serial at 8006c000 {
> +				reg = <0x8006c000 0x2000>;
> +				interrupts = <113 72 73>;
> +				status = "disabled";
> +			};
> +
> +			serial at 8006e000 {
> +				reg = <0x8006e000 0x2000>;
> +				interrupts = <114 74 75>;
> +				status = "disabled";
> +			};
> +
> +			serial at 80070000 {
> +				reg = <0x80070000 0x2000>;
> +				interrupts = <115 76 77>;
> +				status = "disabled";
> +			};
> +
> +			serial at 80072000 {
> +				reg = <0x80072000 0x2000>;
> +				interrupts = <116 78 79>;
> +				status = "disabled";
> +			};
> +
> +			duart: serial at 80074000 {
> +				compatible = "arm,pl011", "arm,primecell";
> +				reg = <0x80074000 0x1000>;
> +				interrupts = <47>;
> +			};
> +
> +			usbphy at 8007c000 {
> +				reg = <0x8007c000 0x2000>;
> +				status = "disabled";
> +			};
> +
> +			usbphy at 8007e000 {
> +				reg = <0x8007e000 0x2000>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	ahb at 80080000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x80080000 0x80000>;
> +		ranges;
> +
> +		usbctrl at 80080000 {
> +			reg = <0x80080000 0x10000>;
> +			status = "disabled";
> +		};
> +
> +		usbctrl at 80090000 {
> +			reg = <0x80090000 0x10000>;
> +			status = "disabled";
> +		};
> +
> +		dflpt at 800c0000 {
> +			reg = <0x800c0000 0x10000>;
> +			status = "disabled";
> +		};
> +
> +		ethernet at 800f0000 {
> +			compatible = "fsl,imx28-fec";
> +			reg = <0x800f0000 0x4000>;
> +			interrupts = <101>;
> +			status = "disabled";
> +		};
> +
> +		ethernet at 800f4000 {
> +			compatible = "fsl,imx28-fec";
> +			reg = <0x800f4000 0x4000>;
> +			interrupts = <102>;
> +			status = "disabled";
> +		};
> +
> +		switch at 800f8000 {
> +			reg = <0x800f8000 0x8000>;
> +			status = "disabled";
> +		};
> +
> +	};
> +};
> diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
> index c57f996..09fe0fb 100644
> --- a/arch/arm/mach-mxs/Kconfig
> +++ b/arch/arm/mach-mxs/Kconfig
> @@ -7,16 +7,26 @@ config MXS_OCOTP
>  
>  config SOC_IMX23
>  	bool
> +	select ARM_AMBA
>  	select CPU_ARM926T
>  	select HAVE_PWM
>  
>  config SOC_IMX28
>  	bool
> +	select ARM_AMBA
>  	select CPU_ARM926T
>  	select HAVE_PWM
>  
>  comment "MXS platforms:"
>  
> +config MACH_MXS_DT
> +	bool "Support MXS platforms from device tree"
> +	select SOC_IMX28
> +	select USE_OF
> +	help
> +	  Include support for Freescale MXS platforms(i.MX23 and i.MX28)
> +	  using the device tree for discovery
> +
>  config MACH_STMP378X_DEVB
>  	bool "Support STMP378x_devb Platform"
>  	select SOC_IMX23
> diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
> index 908bf9a..8328c45 100644
> --- a/arch/arm/mach-mxs/Makefile
> +++ b/arch/arm/mach-mxs/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
>  obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
>  obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
>  
> +obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
>  obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
>  obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
>  obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
> diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
> index 7aa7ff8..a8b8462 100644
> --- a/arch/arm/mach-mxs/clock-mx28.c
> +++ b/arch/arm/mach-mxs/clock-mx28.c
> @@ -648,6 +648,10 @@ static struct clk_lookup lookups[] = {
>  	_REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
>  	_REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
>  	_REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
> +	/* for DT */
> +	_REGISTER_CLOCK("80074000.serial", NULL, uart_clk)
> +	_REGISTER_CLOCK("800f0000.ethernet", NULL, fec_clk)
> +	_REGISTER_CLOCK("800f4000.ethernet", NULL, fec_clk)
>  };
>  
>  static int clk_misc_init(void)
> diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
> index b8913df..19659de 100644
> --- a/arch/arm/mach-mxs/devices/Kconfig
> +++ b/arch/arm/mach-mxs/devices/Kconfig
> @@ -1,6 +1,5 @@
>  config MXS_HAVE_AMBA_DUART
>  	bool
> -	select ARM_AMBA
>  
>  config MXS_HAVE_PLATFORM_AUART
>  	bool
> diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
> new file mode 100644
> index 0000000..5c5cba2
> --- /dev/null
> +++ b/arch/arm/mach-mxs/mach-mxs.c
> @@ -0,0 +1,68 @@
> +/*
> + * Copyright 2012 Freescale Semiconductor, Inc.
> + * Copyright 2012 Linaro Ltd.
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/init.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +#include <mach/common.h>
> +
> +static int __init mxs_icoll_add_irq_domain(struct device_node *np,
> +				struct device_node *interrupt_parent)
> +{
> +	irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id mxs_irq_match[] __initconst = {
> +	{ .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
> +	{ /* sentinel */ }
> +};
> +
> +static void __init mxs_dt_init_irq(void)
> +{
> +	icoll_init_irq();
> +	of_irq_init(mxs_irq_match);
> +}
> +
> +static void __init imx28_timer_init(void)
> +{
> +	mx28_clocks_init();
> +}
> +
> +static struct sys_timer imx28_timer = {
> +	.init = imx28_timer_init,
> +};
> +
> +static void __init mxs_machine_init(void)
> +{
> +	of_platform_populate(NULL, of_default_bus_match_table,
> +				NULL, NULL);
> +}
> +
> +static const char *imx28_dt_compat[] __initdata = {
> +	"fsl,imx28-evk",
> +	"fsl,imx28",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
> +	.map_io		= mx28_map_io,
> +	.init_irq	= mxs_dt_init_irq,
> +	.timer		= &imx28_timer,
> +	.init_machine	= mxs_machine_init,
> +	.dt_compat	= imx28_dt_compat,
> +	.restart	= mxs_restart,
> +MACHINE_END
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss


From chao.xie at marvell.com  Sat Mar 31 22:08:01 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Sun,  1 Apr 2012 10:08:01 +0800
Subject: [PATCH V3 1/4] Input: pxa27x_keypad keep clock on as wakeup source
Message-ID: <1333246084-14110-1-git-send-email-chao.xie@marvell.com>

When the keypad is used as wake up source, the clock can not
be disabled. Or it can not detect key pressing.
If the keypad is used as wake up source, when resume back,
do not enable the clock and configure it again because the
register content is retained.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/input/keyboard/pxa27x_keypad.c |   33 ++++++++++++++++++++-----------
 1 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index 29fe1b2..b07771e 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -399,7 +399,7 @@ static int pxa27x_keypad_open(struct input_dev *dev)
 	struct pxa27x_keypad *keypad = input_get_drvdata(dev);
 
 	/* Enable unit clock */
-	clk_enable(keypad->clk);
+	clk_prepare_enable(keypad->clk);
 	pxa27x_keypad_config(keypad);
 
 	return 0;
@@ -410,7 +410,7 @@ static void pxa27x_keypad_close(struct input_dev *dev)
 	struct pxa27x_keypad *keypad = input_get_drvdata(dev);
 
 	/* Disable clock unit */
-	clk_disable(keypad->clk);
+	clk_disable_unprepare(keypad->clk);
 }
 
 #ifdef CONFIG_PM
@@ -419,10 +419,14 @@ static int pxa27x_keypad_suspend(struct device *dev)
 	struct platform_device *pdev = to_platform_device(dev);
 	struct pxa27x_keypad *keypad = platform_get_drvdata(pdev);
 
-	clk_disable(keypad->clk);
-
+	/*
+	 * If the keypad is used a wake up source, clock can not be disabled.
+	 * Or it can not detect the key pressing.
+	 */
 	if (device_may_wakeup(&pdev->dev))
 		enable_irq_wake(keypad->irq);
+	else
+		clk_disable_unprepare(keypad->clk);
 
 	return 0;
 }
@@ -433,19 +437,24 @@ static int pxa27x_keypad_resume(struct device *dev)
 	struct pxa27x_keypad *keypad = platform_get_drvdata(pdev);
 	struct input_dev *input_dev = keypad->input_dev;
 
-	if (device_may_wakeup(&pdev->dev))
+	/*
+	 * If the keypad is used as wake up source, the clock is not turned
+	 * off. So do not need configure it again.
+	 */
+	if (device_may_wakeup(&pdev->dev)) {
 		disable_irq_wake(keypad->irq);
+	} else {
+		mutex_lock(&input_dev->mutex);
 
-	mutex_lock(&input_dev->mutex);
+		if (input_dev->users) {
+			/* Enable unit clock */
+			clk_prepare_enable(keypad->clk);
+			pxa27x_keypad_config(keypad);
+		}
 
-	if (input_dev->users) {
-		/* Enable unit clock */
-		clk_enable(keypad->clk);
-		pxa27x_keypad_config(keypad);
+		mutex_unlock(&input_dev->mutex);
 	}
 
-	mutex_unlock(&input_dev->mutex);
-
 	return 0;
 }
 
-- 
1.7.0.4



From chao.xie at marvell.com  Sat Mar 31 22:08:02 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Sun,  1 Apr 2012 10:08:02 +0800
Subject: [PATCH V3 2/4] Input: pxa27x_keypad bug fix for direct_key_mask
In-Reply-To: <1333246084-14110-1-git-send-email-chao.xie@marvell.com>
References: <1333246084-14110-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1333246084-14110-2-git-send-email-chao.xie@marvell.com>

When direcct_key_num is 0, the mask should be 0.
When direcct_key_num is 1, the mask should be 0b1.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 drivers/input/keyboard/pxa27x_keypad.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index b07771e..5d71720 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -383,7 +383,7 @@ static void pxa27x_keypad_config(struct pxa27x_keypad *keypad)
 	if (pdata->direct_key_num > direct_key_num)
 		direct_key_num = pdata->direct_key_num;
 
-	keypad->direct_key_mask = ((2 << direct_key_num) - 1) & ~mask;
+	keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask;
 
 	/* enable direct key */
 	if (direct_key_num)
-- 
1.7.0.4



From chao.xie at marvell.com  Sat Mar 31 22:08:03 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Sun,  1 Apr 2012 10:08:03 +0800
Subject: [PATCH V3 3/4] Input: pxa27x_keypad direct key may be low active
In-Reply-To: <1333246084-14110-1-git-send-email-chao.xie@marvell.com>
References: <1333246084-14110-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1333246084-14110-3-git-send-email-chao.xie@marvell.com>

KPDK_DK only indicates the pin level of direct key.
So it is related to board, and low level may be active which
indicates that a key is pressed.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa27x_keypad.h |    2 ++
 drivers/input/keyboard/pxa27x_keypad.c         |   10 +++++++++-
 2 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
index abcc36e..7ffb16b 100644
--- a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -44,6 +44,8 @@ struct pxa27x_keypad_platform_data {
 	/* direct keys */
 	int		direct_key_num;
 	unsigned int	direct_key_map[MAX_DIRECT_KEY_NUM];
+	/* the key output may be low active */
+	int		direct_key_low_active;
 
 	/* rotary encoders 0 */
 	int		enable_rotary0;
diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index 5d71720..a60f14e 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -311,7 +311,15 @@ static void pxa27x_keypad_scan_direct(struct pxa27x_keypad *keypad)
 	if (pdata->enable_rotary0 || pdata->enable_rotary1)
 		pxa27x_keypad_scan_rotary(keypad);
 
-	new_state = KPDK_DK(kpdk) & keypad->direct_key_mask;
+	/*
+	 * The KPDR_DK only output the key pin level, so it relates to board,
+	 * and low level may be active.
+	 */
+	if (pdata->direct_key_low_active)
+		new_state = ~KPDK_DK(kpdk) & keypad->direct_key_mask;
+	else
+		new_state = KPDK_DK(kpdk) & keypad->direct_key_mask;
+
 	bits_changed = keypad->direct_key_state ^ new_state;
 
 	if (bits_changed == 0)
-- 
1.7.0.4



From chao.xie at marvell.com  Sat Mar 31 22:08:04 2012
From: chao.xie at marvell.com (Chao Xie)
Date: Sun,  1 Apr 2012 10:08:04 +0800
Subject: [PATCH V3 4/4] Input: pxa27x_keypad add choice to set direct_key_mask
In-Reply-To: <1333246084-14110-1-git-send-email-chao.xie@marvell.com>
References: <1333246084-14110-1-git-send-email-chao.xie@marvell.com>
Message-ID: <1333246084-14110-4-git-send-email-chao.xie@marvell.com>

Direct keys usage may not start from KP_DKIN0, add a msk option
to configure the specifics for platforms that can skip some keys.

Signed-off-by: Chao Xie <chao.xie at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa27x_keypad.h |    2 ++
 drivers/input/keyboard/pxa27x_keypad.c         |    9 ++++++++-
 2 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
index 7ffb16b..5ce8d5e 100644
--- a/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -46,6 +46,8 @@ struct pxa27x_keypad_platform_data {
 	unsigned int	direct_key_map[MAX_DIRECT_KEY_NUM];
 	/* the key output may be low active */
 	int		direct_key_low_active;
+	/* give board a chance to choose the start direct key */
+	unsigned int	direct_key_mask;
 
 	/* rotary encoders 0 */
 	int		enable_rotary0;
diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index a60f14e..7f7b724 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -391,7 +391,14 @@ static void pxa27x_keypad_config(struct pxa27x_keypad *keypad)
 	if (pdata->direct_key_num > direct_key_num)
 		direct_key_num = pdata->direct_key_num;
 
-	keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask;
+	/*
+	 * Direct keys usage may not start from KP_DKIN0, check the platfrom
+	 * mask data to config the specific.
+	 */
+	if (pdata->direct_key_mask)
+		keypad->direct_key_mask = pdata->direct_key_mask;
+	else
+		keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask;
 
 	/* enable direct key */
 	if (direct_key_num)
-- 
1.7.0.4



From b32955 at freescale.com  Sat Mar 31 23:21:10 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Sun, 1 Apr 2012 11:21:10 +0800
Subject: Bug in v7_coherent_kern_range() ?
Message-ID: <4F77C9A6.6080601@freescale.com>

[1] Platform:
freescale's IMX6Q(4 cores) , ARM CORTEX-A9

[2] kernel:
3.0.15(I have cherry-picked many patches, and the arch/arm/mm/cache-v7.S
is same code with the latest kernel v3.4-rc1)
enable SMP, VIPT,

[3] application:
I use our our application which will clone many threads,
two threads (assume as A and B) may do the same thing at the same time
as the following code:

In most of the time, it's ok.
But in some unknown situation, cacheflush() failed and one threads
(assume A) may hung up in the following code:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

open("/usr/lib/lib_mp3_dec_arm12_elinux.so.2.10.0", O_RDONLY) = 8
read(8,
"\177ELF\1\1\1\0\0\0\0\0\0\0\0\0\3\0(\0\1\0\0\0\20\35\0\0004\0\0\0"...,
512) = 512
fstat64(8, {st_mode=S_IFREG|0644, st_size=56232, ...}) = 0
mmap2(NULL, 88032, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 8, 0)
= 0x2ff0a000
mprotect(0x2ff18000, 28672, PROT_NONE) = 0
mmap2(0x2ff1f000, 4096, PROT_READ|PROT_WRITE,
MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 8, 0xd) = 0x2ff1f000
close(8) = 0
mprotect(0x2ff0a000, 57344, PROT_READ|PROT_WRITE) = 0
mprotect(0x2ff0a000, 57344, PROT_READ|PROT_EXEC) = 0
cacheflush(0x2ff0a000, 0x2ff18000, 0, 0x6, 0x2cd03420) = 0 // System
hung up here!!!
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++


[4] kernel log
I use "echo t > /proc/sysrq-trigger" to show the tasks's information:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

multiqueue0:src D 804cd678 0 7328 5963 0x00000001
[<804cd678>] (__schedule+0x228/0x760) from [<804d0564>]
(__down_read+0xa8/0xe0)
[<804d0564>] (__down_read+0xa8/0xe0) from [<800478c4>]
(do_page_fault+0xbc/0x480)
[<800478c4>] (do_page_fault+0xbc/0x480) from [<8003841c>]
(do_DataAbort+0x34/0x98)
[<8003841c>] (do_DataAbort+0x34/0x98) from [<8003df10>]
(__dabt_svc+0x70/0xa0)
Exception stack(0xbae37ea8 to 0xbae37ef0)
7ea0: 31e05000 31e1d000 00000020 0000001f 31e05000 31e1d000
7ec0: bfac86b8 31e05000 31e1d000 bae36000 08100075 31e056fc 31e08000
bae37ef0
7ee0: 800424a8 8004a1fc 800f0013 ffffffff
[<8003df10>] (__dabt_svc+0x70/0xa0) from [<8004a1fc>]
(v7_coherent_kern_range+0x20/0x80)
[<8004a1fc>] (v7_coherent_kern_range+0x20/0x80) from [<800424a8>]
(arm_syscall+0x2a0/0x2c4)
[<800424a8>] (arm_syscall+0x2a0/0x2c4) from [<8003e500>]
(ret_fast_syscall+0x0/0x3c)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++


The do_cache_op() has already held the mm->mmap_sem, but
v7_coherent_kern_range()
cause one page fault during it flush the cache. deadlock! So it hung up
in the do_page_fault().

[5] questions:
Why the v7_coherent_kern_range() can caused the data abort?
Is there something wrong about the v7_coherent_kern_range()?


thanks
Huang Shijie






From cjb at laptop.org  Sat Mar 31 23:43:06 2012
From: cjb at laptop.org (Chris Ball)
Date: Sat, 31 Mar 2012 23:43:06 -0400
Subject: [PATCH v2 1/3] mmc: atmel-mci: correct data timeout computation
In-Reply-To: <4F72F9A5.60900@atmel.com> (Nicolas Ferre's message of "Wed, 28
 Mar 2012 13:44:37 +0200")
References: <1332344483-3915-2-git-send-email-ludovic.desroches@atmel.com>
 <1332930513-14893-1-git-send-email-ludovic.desroches@atmel.com>
 <4F72F9A5.60900@atmel.com>
Message-ID: <87vclkm81h.fsf@laptop.org>

Hi,

On Wed, Mar 28 2012, Nicolas Ferre wrote:
> On 03/28/2012 12:28 PM, ludovic.desroches at atmel.com :
>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>> 
>> The HSMCI operates at a rate of up to Master Clock divided by two.
>> Moreover previous calculation can cause overflows and so wrong
>> timeouts.
>> 
>> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>
> Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Thanks, pushed to mmc-next for 3.4.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From cjb at laptop.org  Sat Mar 31 23:43:45 2012
From: cjb at laptop.org (Chris Ball)
Date: Sat, 31 Mar 2012 23:43:45 -0400
Subject: [PATCH 2/3] mmc: atmel-mci: r/w proof capability only available
 since v2xx
In-Reply-To: <4F6B3AE3.6080901@atmel.com> (Nicolas Ferre's message of "Thu, 22
 Mar 2012 15:44:51 +0100")
References: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
 <1332344483-3915-3-git-send-email-ludovic.desroches@atmel.com>
 <4F6B3AE3.6080901@atmel.com>
Message-ID: <87r4w8m80e.fsf@laptop.org>

Hi,

On Thu, Mar 22 2012, Nicolas Ferre wrote:
> On 03/21/2012 04:41 PM, ludovic.desroches at atmel.com :
>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>> 
>> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>
> Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Thanks, pushed to mmc-next for 3.4.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From cjb at laptop.org  Sat Mar 31 23:44:41 2012
From: cjb at laptop.org (Chris Ball)
Date: Sat, 31 Mar 2012 23:44:41 -0400
Subject: [PATCH 3/3] mmc: atmel-mci: add support for odd clock dividers
In-Reply-To: <4F6B3BD0.4060702@atmel.com> (Nicolas Ferre's message of "Thu, 22
 Mar 2012 15:48:48 +0100")
References: <1332344483-3915-1-git-send-email-ludovic.desroches@atmel.com>
 <1332344483-3915-4-git-send-email-ludovic.desroches@atmel.com>
 <4F6B3BD0.4060702@atmel.com>
Message-ID: <87mx6wm7yu.fsf@laptop.org>

Hi,

On Thu, Mar 22 2012, Nicolas Ferre wrote:
> On 03/21/2012 04:41 PM, ludovic.desroches at atmel.com :
>> From: Ludovic Desroches <ludovic.desroches at atmel.com>
>> 
>> Add an odd clock divider capability available from v5xx. It also involves
>> changing the clock divider calculation.
>
> Also tell here that you have changed the way that the switch/case
> directive has been implemented.
>
>> Signed-off-by: Ludovic Desroches <ludovic.desroches at atmel.com>
>
> Otherwise:
> Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Thanks, pushed to mmc-next for 3.4 with a rewording:

    Add an odd clock divider capability available from v5xx. It also involves
    changing the clock divider calculation, and changing the switch-case
    statement to use top-down fallthrough.

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


From cjb at laptop.org  Sat Mar 31 23:49:19 2012
From: cjb at laptop.org (Chris Ball)
Date: Sat, 31 Mar 2012 23:49:19 -0400
Subject: [PATCH 0/4] atmel-mci device tree support
In-Reply-To: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
 (ludovic desroches's message of "Wed, 21 Mar 2012 19:03:10 +0100")
References: <1332352994-20983-1-git-send-email-ludovic.desroches@atmel.com>
Message-ID: <87iphkm7r4.fsf@laptop.org>

Hi,

On Wed, Mar 21 2012, ludovic.desroches at atmel.com wrote:
> Hi,
>
> This patch-set adds device tree support for atmel-mci.

Please can you resend after syncing up with Arnd's suggestions in:
   http://thread.gmane.org/gmane.linux.kernel.samsung-soc/9216/focus=13659

(It looks like the main difference is just s/cd-invert;/cd-inverted;/.)

Thanks,

- Chris.
-- 
Chris Ball   <cjb at laptop.org>   <http://printf.net/>
One Laptop Per Child


